From 645086ca124d0f8649f8c0038e003260a4e39f38 Mon Sep 17 00:00:00 2001 From: Waldemar Brodkorb Date: Sun, 24 Jan 2016 03:22:29 +0100 Subject: linux: update to 4.1.16 --- .../patches/4.1.15/0001-raspberry-pi-github.patch | 143407 -------- .../patches/4.1.16/0001-raspberry-pi-github.patch | 143407 ++++++++ .../solidrun-imx6/patches/4.1.15/0001-xbian.patch | 314813 ------------------ .../arm/solidrun-imx6/patches/4.1.15/0002-rt.patch | 75 - .../solidrun-imx6/patches/4.1.16/0001-xbian.patch | 314813 ++++++++++++++++++ .../arm/solidrun-imx6/patches/4.1.16/0002-rt.patch | 75 + 6 files changed, 458295 insertions(+), 458295 deletions(-) delete mode 100644 target/arm/bcm28xx/patches/4.1.15/0001-raspberry-pi-github.patch create mode 100644 target/arm/bcm28xx/patches/4.1.16/0001-raspberry-pi-github.patch delete mode 100644 target/arm/solidrun-imx6/patches/4.1.15/0001-xbian.patch delete mode 100644 target/arm/solidrun-imx6/patches/4.1.15/0002-rt.patch create mode 100644 target/arm/solidrun-imx6/patches/4.1.16/0001-xbian.patch create mode 100644 target/arm/solidrun-imx6/patches/4.1.16/0002-rt.patch (limited to 'target/arm') diff --git a/target/arm/bcm28xx/patches/4.1.15/0001-raspberry-pi-github.patch b/target/arm/bcm28xx/patches/4.1.15/0001-raspberry-pi-github.patch deleted file mode 100644 index 4fe3c5c2d..000000000 --- a/target/arm/bcm28xx/patches/4.1.15/0001-raspberry-pi-github.patch +++ /dev/null @@ -1,143407 +0,0 @@ -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/bcm2708_common.dtsi linux-rpi/arch/arm/boot/dts/bcm2708_common.dtsi ---- linux-4.1.13.orig/arch/arm/boot/dts/bcm2708_common.dtsi 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/bcm2708_common.dtsi 2015-11-29 09:42:34.571454018 +0100 -@@ -0,0 +1,321 @@ -+/include/ "skeleton.dtsi" -+ -+/ { -+ interrupt-parent = <&intc>; -+ -+ aliases { -+ audio = &audio; -+ sound = &sound; -+ soc = &soc; -+ dma = &dma; -+ intc = &intc; -+ watchdog = &watchdog; -+ random = &random; -+ mailbox = &mailbox; -+ gpio = &gpio; -+ uart0 = &uart0; -+ i2s = &i2s; -+ spi0 = &spi0; -+ i2c0 = &i2c0; -+ uart1 = &uart1; -+ mmc = &mmc; -+ i2c1 = &i2c1; -+ i2c2 = &i2c2; -+ usb = &usb; -+ leds = &leds; -+ fb = &fb; -+ vchiq = &vchiq; -+ thermal = &thermal; -+ clocks = &clocks; -+ }; -+ -+ /* Onboard audio */ -+ audio: audio { -+ compatible = "brcm,bcm2835-audio"; -+ brcm,pwm-channels = <8>; -+ status = "disabled"; -+ }; -+ -+ /* External sound card */ -+ sound: sound { -+ }; -+ -+ soc: soc { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ dma: dma@7e007000 { -+ compatible = "brcm,bcm2835-dma"; -+ reg = <0x7e007000 0xf00>; -+ interrupts = <1 16>, -+ <1 17>, -+ <1 18>, -+ <1 19>, -+ <1 20>, -+ <1 21>, -+ <1 22>, -+ <1 23>, -+ <1 24>, -+ <1 25>, -+ <1 26>, -+ <1 27>; -+ -+ #dma-cells = <1>; -+ brcm,dma-channel-mask = <0x0f35>; -+ }; -+ -+ intc: interrupt-controller { -+ compatible = "brcm,bcm2708-armctrl-ic"; -+ reg = <0x7e00b200 0x200>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ mailbox: mailbox@7e00b800 { -+ compatible = "brcm,bcm2835-mbox"; -+ reg = <0x7e00b880 0x40>; -+ interrupts = <0 1>; -+ #mbox-cells = <0>; -+ }; -+ -+ watchdog: watchdog@7e100000 { -+ compatible = "brcm,bcm2835-pm-wdt"; -+ reg = <0x7e100000 0x28>; -+ status = "disabled"; -+ }; -+ -+ random: rng@7e104000 { -+ compatible = "brcm,bcm2835-rng"; -+ reg = <0x7e104000 0x10>; -+ status = "disabled"; -+ }; -+ -+ gpio: gpio@7e200000 { -+ compatible = "brcm,bcm2835-gpio"; -+ reg = <0x7e200000 0xb4>; -+ interrupts = <2 17>, <2 18>; -+ -+ gpio-controller; -+ #gpio-cells = <2>; -+ -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ uart0: uart@7e201000 { -+ compatible = "arm,pl011", "arm,primecell"; -+ reg = <0x7e201000 0x1000>; -+ interrupts = <2 25>; -+ clocks = <&clk_uart0 &clk_apb_p>; -+ clock-names = "uartclk","apb_pclk"; -+ arm,primecell-periphid = <0x00241011>; // For an explanation, see -+ // https://github.com/raspberrypi/linux/commit/13731d862cf5219216533a3b0de052cee4cc5038 -+ status = "disabled"; -+ }; -+ -+ i2s: i2s@7e203000 { -+ compatible = "brcm,bcm2708-i2s"; -+ reg = <0x7e203000 0x24>, -+ <0x7e101098 0x08>; -+ -+ //dmas = <&dma 2>, -+ // <&dma 3>; -+ dma-names = "tx", "rx"; -+ status = "disabled"; -+ }; -+ -+ spi0: spi@7e204000 { -+ compatible = "brcm,bcm2835-spi"; -+ reg = <0x7e204000 0x1000>; -+ interrupts = <2 22>; -+ clocks = <&clk_core>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ /* the dma channels */ -+ dmas = <&dma 6>, <&dma 7>; -+ dma-names = "tx", "rx"; -+ /* the chipselects used - <0> means native GPIO -+ * add more gpios if necessary as <&gpio 6 1> -+ * (but do not forget to make them output!) -+ */ -+ cs-gpios = <0>, <0>; -+ }; -+ -+ i2c0: i2c@7e205000 { -+ compatible = "brcm,bcm2708-i2c"; -+ reg = <0x7e205000 0x1000>; -+ interrupts = <2 21>; -+ clocks = <&clk_i2c>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ pwm: pwm@7e20c000 { -+ compatible = "brcm,bcm2835-pwm"; -+ reg = <0x7e20c000 0x28>; -+ clocks = <&clk_pwm>; -+ #pwm-cells = <2>; -+ status = "disabled"; -+ }; -+ -+ uart1: uart@7e215040 { -+ compatible = "brcm,bcm2835-aux-uart", "ns16550"; -+ reg = <0x7e215040 0x40>; -+ interrupts = <1 29>; -+ clocks = <&clk_uart1>; -+ reg-shift = <2>; -+ no-loopback-test; -+ status = "disabled"; -+ }; -+ -+ mmc: mmc@7e300000 { -+ compatible = "brcm,bcm2835-mmc"; -+ reg = <0x7e300000 0x100>; -+ interrupts = <2 30>; -+ clocks = <&clk_mmc>; -+ dmas = <&dma 11>, -+ <&dma 11>; -+ dma-names = "tx", "rx"; -+ status = "disabled"; -+ }; -+ -+ i2c1: i2c@7e804000 { -+ compatible = "brcm,bcm2708-i2c"; -+ reg = <0x7e804000 0x1000>; -+ interrupts = <2 21>; -+ clocks = <&clk_i2c>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ i2c2: i2c@7e805000 { -+ // Beware - this is shared with the HDMI module. -+ // Careless use may break (really) your display. -+ // Caveat emptor. -+ compatible = "brcm,bcm2708-i2c"; -+ reg = <0x7e805000 0x1000>; -+ interrupts = <2 21>; -+ clocks = <&clk_i2c>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ }; -+ -+ smi: smi@7e600000 { -+ compatible = "brcm,bcm2835-smi"; -+ reg = <0x7e600000 0x44>, <0x7e1010b0 0x8>; -+ interrupts = <2 16>; -+ brcm,smi-clock-source = <6>; -+ brcm,smi-clock-divisor = <4>; -+ dmas = <&dma 4>; -+ dma-names = "rx-tx"; -+ status = "disabled"; -+ }; -+ -+ usb: usb@7e980000 { -+ compatible = "brcm,bcm2708-usb"; -+ reg = <0x7e980000 0x10000>, -+ <0x7e006000 0x1000>; -+ interrupts = <2 0>, -+ <1 9>; -+ }; -+ -+ firmware: firmware { -+ compatible = "raspberrypi,bcm2835-firmware"; -+ mboxes = <&mailbox>; -+ }; -+ -+ leds: leds { -+ compatible = "gpio-leds"; -+ }; -+ -+ fb: fb { -+ compatible = "brcm,bcm2708-fb"; -+ firmware = <&firmware>; -+ status = "disabled"; -+ }; -+ -+ vchiq: vchiq { -+ compatible = "brcm,bcm2835-vchiq"; -+ reg = <0x7e00b840 0xf>; -+ interrupts = <0 2>; -+ cache-line-size = <32>; -+ firmware = <&firmware>; -+ }; -+ -+ thermal: thermal { -+ compatible = "brcm,bcm2835-thermal"; -+ firmware = <&firmware>; -+ }; -+ }; -+ -+ clocks: clocks { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ clk_mmc: clock@0 { -+ compatible = "fixed-clock"; -+ reg = <0>; -+ #clock-cells = <0>; -+ clock-output-names = "mmc"; -+ clock-frequency = <250000000>; -+ }; -+ -+ clk_i2c: clock@1 { -+ compatible = "fixed-clock"; -+ reg = <1>; -+ #clock-cells = <0>; -+ clock-output-names = "i2c"; -+ clock-frequency = <250000000>; -+ }; -+ -+ clk_core: clock@2 { -+ compatible = "fixed-clock"; -+ reg = <2>; -+ #clock-cells = <0>; -+ clock-output-names = "core"; -+ clock-frequency = <250000000>; -+ }; -+ -+ clk_uart0: clock@3 { -+ compatible = "fixed-clock"; -+ reg = <3>; -+ #clock-cells = <0>; -+ clock-output-names = "uart0_pclk"; -+ clock-frequency = <3000000>; -+ }; -+ -+ clk_apb_p: clock@4 { -+ compatible = "fixed-clock"; -+ reg = <4>; -+ #clock-cells = <0>; -+ clock-output-names = "apb_pclk"; -+ clock-frequency = <126000000>; -+ }; -+ -+ clk_pwm: clock@5 { -+ compatible = "fixed-clock"; -+ reg = <3>; -+ #clock-cells = <0>; -+ clock-output-names = "pwm"; -+ clock-frequency = <100000000>; -+ }; -+ -+ clk_uart1: clock@6 { -+ compatible = "fixed-factor-clock"; -+ clocks = <&clk_core>; -+ #clock-cells = <0>; -+ clock-div = <1>; -+ clock-mult = <2>; -+ }; -+ }; -+ -+ __overrides__ { -+ cache_line_size = <&vchiq>, "cache-line-size:0"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/bcm2708.dtsi linux-rpi/arch/arm/boot/dts/bcm2708.dtsi ---- linux-4.1.13.orig/arch/arm/boot/dts/bcm2708.dtsi 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/bcm2708.dtsi 2015-11-29 09:42:34.571454018 +0100 -@@ -0,0 +1,25 @@ -+/include/ "bcm2708_common.dtsi" -+ -+/ { -+ compatible = "brcm,bcm2708"; -+ model = "BCM2708"; -+ -+ chosen { -+ /* No padding required - the boot loader can do that. */ -+ bootargs = ""; -+ }; -+ -+ soc { -+ ranges = <0x7e000000 0x20000000 0x01000000>; -+ -+ arm-pmu { -+ compatible = "arm,arm1176-pmu"; -+ }; -+ -+ gpiomem { -+ compatible = "brcm,bcm2835-gpiomem"; -+ reg = <0x7e200000 0x1000>; -+ status = "okay"; -+ }; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/bcm2708-rpi-b.dts linux-rpi/arch/arm/boot/dts/bcm2708-rpi-b.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/bcm2708-rpi-b.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/bcm2708-rpi-b.dts 2015-11-29 09:42:34.571454018 +0100 -@@ -0,0 +1,118 @@ -+/dts-v1/; -+ -+/include/ "bcm2708.dtsi" -+ -+/ { -+ compatible = "brcm,bcm2708"; -+ model = "Raspberry Pi Model B"; -+}; -+ -+&gpio { -+ spi0_pins: spi0_pins { -+ brcm,pins = <7 8 9 10 11>; -+ brcm,function = <4>; /* alt0 */ -+ }; -+ -+ i2c0_pins: i2c0 { -+ brcm,pins = <0 1>; -+ brcm,function = <4>; -+ }; -+ -+ i2c1_pins: i2c1 { -+ brcm,pins = <2 3>; -+ brcm,function = <4>; -+ }; -+ -+ i2s_pins: i2s { -+ brcm,pins = <28 29 30 31>; -+ brcm,function = <6>; /* alt2 */ -+ }; -+}; -+ -+&mmc { -+ status = "okay"; -+ bus-width = <4>; -+}; -+ -+&fb { -+ status = "okay"; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; -+ -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_pins>; -+ -+ spidev@0{ -+ compatible = "spidev"; -+ reg = <0>; /* CE0 */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ spi-max-frequency = <500000>; -+ }; -+ -+ spidev@1{ -+ compatible = "spidev"; -+ reg = <1>; /* CE1 */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ spi-max-frequency = <500000>; -+ }; -+}; -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins>; -+ clock-frequency = <100000>; -+}; -+ -+&i2c1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c1_pins>; -+ clock-frequency = <100000>; -+}; -+ -+&i2c2 { -+ clock-frequency = <100000>; -+}; -+ -+&i2s { -+ #sound-dai-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2s_pins>; -+}; -+ -+&leds { -+ act_led: act { -+ label = "led0"; -+ linux,default-trigger = "mmc0"; -+ gpios = <&gpio 16 1>; -+ }; -+}; -+ -+/ { -+ __overrides__ { -+ uart0 = <&uart0>,"status"; -+ uart0_clkrate = <&clk_uart0>,"clock-frequency:0"; -+ i2s = <&i2s>,"status"; -+ spi = <&spi0>,"status"; -+ i2c0 = <&i2c0>,"status"; -+ i2c1 = <&i2c1>,"status"; -+ i2c2_iknowwhatimdoing = <&i2c2>,"status"; -+ i2c0_baudrate = <&i2c0>,"clock-frequency:0"; -+ i2c1_baudrate = <&i2c1>,"clock-frequency:0"; -+ i2c2_baudrate = <&i2c2>,"clock-frequency:0"; -+ core_freq = <&clk_core>,"clock-frequency:0"; -+ -+ act_led_gpio = <&act_led>,"gpios:4"; -+ act_led_activelow = <&act_led>,"gpios:8"; -+ act_led_trigger = <&act_led>,"linux,default-trigger"; -+ -+ audio = <&audio>,"status"; -+ watchdog = <&watchdog>,"status"; -+ random = <&random>,"status"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts linux-rpi/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts 2015-11-29 09:42:34.571454018 +0100 -@@ -0,0 +1,128 @@ -+/dts-v1/; -+ -+/include/ "bcm2708.dtsi" -+ -+/ { -+ compatible = "brcm,bcm2708"; -+ model = "Raspberry Pi Model B+"; -+}; -+ -+&gpio { -+ spi0_pins: spi0_pins { -+ brcm,pins = <7 8 9 10 11>; -+ brcm,function = <4>; /* alt0 */ -+ }; -+ -+ i2c0_pins: i2c0 { -+ brcm,pins = <0 1>; -+ brcm,function = <4>; -+ }; -+ -+ i2c1_pins: i2c1 { -+ brcm,pins = <2 3>; -+ brcm,function = <4>; -+ }; -+ -+ i2s_pins: i2s { -+ brcm,pins = <18 19 20 21>; -+ brcm,function = <4>; /* alt0 */ -+ }; -+}; -+ -+&mmc { -+ status = "okay"; -+ bus-width = <4>; -+}; -+ -+&fb { -+ status = "okay"; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; -+ -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_pins>; -+ -+ spidev@0{ -+ compatible = "spidev"; -+ reg = <0>; /* CE0 */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ spi-max-frequency = <500000>; -+ }; -+ -+ spidev@1{ -+ compatible = "spidev"; -+ reg = <1>; /* CE1 */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ spi-max-frequency = <500000>; -+ }; -+}; -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins>; -+ clock-frequency = <100000>; -+}; -+ -+&i2c1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c1_pins>; -+ clock-frequency = <100000>; -+}; -+ -+&i2c2 { -+ clock-frequency = <100000>; -+}; -+ -+&i2s { -+ #sound-dai-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2s_pins>; -+}; -+ -+&leds { -+ act_led: act { -+ label = "led0"; -+ linux,default-trigger = "mmc0"; -+ gpios = <&gpio 47 0>; -+ }; -+ -+ pwr_led: pwr { -+ label = "led1"; -+ linux,default-trigger = "input"; -+ gpios = <&gpio 35 0>; -+ }; -+}; -+ -+/ { -+ __overrides__ { -+ uart0 = <&uart0>,"status"; -+ uart0_clkrate = <&clk_uart0>,"clock-frequency:0"; -+ i2s = <&i2s>,"status"; -+ spi = <&spi0>,"status"; -+ i2c0 = <&i2c0>,"status"; -+ i2c1 = <&i2c1>,"status"; -+ i2c2_iknowwhatimdoing = <&i2c2>,"status"; -+ i2c0_baudrate = <&i2c0>,"clock-frequency:0"; -+ i2c1_baudrate = <&i2c1>,"clock-frequency:0"; -+ i2c2_baudrate = <&i2c2>,"clock-frequency:0"; -+ core_freq = <&clk_core>,"clock-frequency:0"; -+ -+ act_led_gpio = <&act_led>,"gpios:4"; -+ act_led_activelow = <&act_led>,"gpios:8"; -+ act_led_trigger = <&act_led>,"linux,default-trigger"; -+ -+ pwr_led_gpio = <&pwr_led>,"gpios:4"; -+ pwr_led_activelow = <&pwr_led>,"gpios:8"; -+ pwr_led_trigger = <&pwr_led>,"linux,default-trigger"; -+ -+ audio = <&audio>,"status"; -+ watchdog = <&watchdog>,"status"; -+ random = <&random>,"status"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/bcm2708-rpi-cm.dts linux-rpi/arch/arm/boot/dts/bcm2708-rpi-cm.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/bcm2708-rpi-cm.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/bcm2708-rpi-cm.dts 2015-11-29 09:42:34.571454018 +0100 -@@ -0,0 +1,92 @@ -+/dts-v1/; -+ -+/include/ "bcm2708-rpi-cm.dtsi" -+ -+/ { -+ model = "Raspberry Pi Compute Module"; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; -+ -+&gpio { -+ spi0_pins: spi0_pins { -+ brcm,pins = <7 8 9 10 11>; -+ brcm,function = <4>; /* alt0 */ -+ }; -+ -+ i2c0_pins: i2c0 { -+ brcm,pins = <0 1>; -+ brcm,function = <4>; -+ }; -+ -+ i2c1_pins: i2c1 { -+ brcm,pins = <2 3>; -+ brcm,function = <4>; -+ }; -+ -+ i2s_pins: i2s { -+ brcm,pins = <18 19 20 21>; -+ brcm,function = <4>; /* alt0 */ -+ }; -+}; -+ -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_pins>; -+ -+ spidev@0{ -+ compatible = "spidev"; -+ reg = <0>; /* CE0 */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ spi-max-frequency = <500000>; -+ }; -+ -+ spidev@1{ -+ compatible = "spidev"; -+ reg = <1>; /* CE1 */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ spi-max-frequency = <500000>; -+ }; -+}; -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins>; -+ clock-frequency = <100000>; -+}; -+ -+&i2c1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c1_pins>; -+ clock-frequency = <100000>; -+}; -+ -+&i2c2 { -+ clock-frequency = <100000>; -+}; -+ -+&i2s { -+ #sound-dai-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2s_pins>; -+}; -+ -+/ { -+ __overrides__ { -+ uart0 = <&uart0>,"status"; -+ uart0_clkrate = <&clk_uart0>,"clock-frequency:0"; -+ i2s = <&i2s>,"status"; -+ spi = <&spi0>,"status"; -+ i2c0 = <&i2c0>,"status"; -+ i2c1 = <&i2c1>,"status"; -+ i2c2_iknowwhatimdoing = <&i2c2>,"status"; -+ i2c0_baudrate = <&i2c0>,"clock-frequency:0"; -+ i2c1_baudrate = <&i2c1>,"clock-frequency:0"; -+ i2c2_baudrate = <&i2c2>,"clock-frequency:0"; -+ core_freq = <&clk_core>,"clock-frequency:0"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi linux-rpi/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi ---- linux-4.1.13.orig/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi 2015-11-29 09:42:34.571454018 +0100 -@@ -0,0 +1,30 @@ -+/include/ "bcm2708.dtsi" -+ -+&leds { -+ act_led: act { -+ label = "led0"; -+ linux,default-trigger = "mmc0"; -+ gpios = <&gpio 47 0>; -+ }; -+}; -+ -+&mmc { -+ status = "okay"; -+ bus-width = <4>; -+}; -+ -+&fb { -+ status = "okay"; -+}; -+ -+/ { -+ __overrides__ { -+ act_led_gpio = <&act_led>,"gpios:4"; -+ act_led_activelow = <&act_led>,"gpios:8"; -+ act_led_trigger = <&act_led>,"linux,default-trigger"; -+ -+ audio = <&audio>,"status"; -+ watchdog = <&watchdog>,"status"; -+ random = <&random>,"status"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/bcm2709.dtsi linux-rpi/arch/arm/boot/dts/bcm2709.dtsi ---- linux-4.1.13.orig/arch/arm/boot/dts/bcm2709.dtsi 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/bcm2709.dtsi 2015-11-29 09:42:34.571454018 +0100 -@@ -0,0 +1,76 @@ -+/include/ "bcm2708_common.dtsi" -+ -+/ { -+ compatible = "brcm,bcm2709"; -+ model = "BCM2709"; -+ -+ chosen { -+ /* No padding required - the boot loader can do that. */ -+ bootargs = ""; -+ }; -+ -+ soc { -+ ranges = <0x7e000000 0x3f000000 0x01000000>; -+ -+ arm-pmu { -+ compatible = "arm,cortex-a7-pmu"; -+ interrupts = <3 9>; -+ }; -+ -+ gpiomem { -+ compatible = "brcm,bcm2835-gpiomem"; -+ reg = <0x7e200000 0x1000>; -+ status = "okay"; -+ }; -+ }; -+ -+ timer { -+ compatible = "arm,armv7-timer"; -+ clock-frequency = <19200000>; -+ interrupts = <3 0>, // PHYS_SECURE_PPI -+ <3 1>, // PHYS_NONSECURE_PPI -+ <3 3>, // VIRT_PPI -+ <3 2>; // HYP_PPI -+ always-on; -+ }; -+ -+ cpus: cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ v7_cpu0: cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a7"; -+ reg = <0xf00>; -+ clock-frequency = <800000000>; -+ }; -+ -+ v7_cpu1: cpu@1 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a7"; -+ reg = <0xf01>; -+ clock-frequency = <800000000>; -+ }; -+ -+ v7_cpu2: cpu@2 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a7"; -+ reg = <0xf02>; -+ clock-frequency = <800000000>; -+ }; -+ -+ v7_cpu3: cpu@3 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a7"; -+ reg = <0xf03>; -+ clock-frequency = <800000000>; -+ }; -+ }; -+ -+ __overrides__ { -+ arm_freq = <&v7_cpu0>, "clock-frequency:0", -+ <&v7_cpu1>, "clock-frequency:0", -+ <&v7_cpu2>, "clock-frequency:0", -+ <&v7_cpu3>, "clock-frequency:0"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/bcm2709-rpi-2-b.dts linux-rpi/arch/arm/boot/dts/bcm2709-rpi-2-b.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/bcm2709-rpi-2-b.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/bcm2709-rpi-2-b.dts 2015-11-29 09:42:34.571454018 +0100 -@@ -0,0 +1,128 @@ -+/dts-v1/; -+ -+/include/ "bcm2709.dtsi" -+ -+/ { -+ compatible = "brcm,bcm2709"; -+ model = "Raspberry Pi 2 Model B"; -+}; -+ -+&gpio { -+ spi0_pins: spi0_pins { -+ brcm,pins = <7 8 9 10 11>; -+ brcm,function = <4>; /* alt0 */ -+ }; -+ -+ i2c0_pins: i2c0 { -+ brcm,pins = <0 1>; -+ brcm,function = <4>; -+ }; -+ -+ i2c1_pins: i2c1 { -+ brcm,pins = <2 3>; -+ brcm,function = <4>; -+ }; -+ -+ i2s_pins: i2s { -+ brcm,pins = <18 19 20 21>; -+ brcm,function = <4>; /* alt0 */ -+ }; -+}; -+ -+&mmc { -+ status = "okay"; -+ bus-width = <4>; -+}; -+ -+&fb { -+ status = "okay"; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; -+ -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_pins>; -+ -+ spidev@0{ -+ compatible = "spidev"; -+ reg = <0>; /* CE0 */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ spi-max-frequency = <500000>; -+ }; -+ -+ spidev@1{ -+ compatible = "spidev"; -+ reg = <1>; /* CE1 */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ spi-max-frequency = <500000>; -+ }; -+}; -+ -+&i2c0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins>; -+ clock-frequency = <100000>; -+}; -+ -+&i2c1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c1_pins>; -+ clock-frequency = <100000>; -+}; -+ -+&i2c2 { -+ clock-frequency = <100000>; -+}; -+ -+&i2s { -+ #sound-dai-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2s_pins>; -+}; -+ -+&leds { -+ act_led: act { -+ label = "led0"; -+ linux,default-trigger = "mmc0"; -+ gpios = <&gpio 47 0>; -+ }; -+ -+ pwr_led: pwr { -+ label = "led1"; -+ linux,default-trigger = "input"; -+ gpios = <&gpio 35 0>; -+ }; -+}; -+ -+/ { -+ __overrides__ { -+ uart0 = <&uart0>,"status"; -+ uart0_clkrate = <&clk_uart0>,"clock-frequency:0"; -+ i2s = <&i2s>,"status"; -+ spi = <&spi0>,"status"; -+ i2c0 = <&i2c0>,"status"; -+ i2c1 = <&i2c1>,"status"; -+ i2c2_iknowwhatimdoing = <&i2c2>,"status"; -+ i2c0_baudrate = <&i2c0>,"clock-frequency:0"; -+ i2c1_baudrate = <&i2c1>,"clock-frequency:0"; -+ i2c2_baudrate = <&i2c2>,"clock-frequency:0"; -+ core_freq = <&clk_core>,"clock-frequency:0"; -+ -+ act_led_gpio = <&act_led>,"gpios:4"; -+ act_led_activelow = <&act_led>,"gpios:8"; -+ act_led_trigger = <&act_led>,"linux,default-trigger"; -+ -+ pwr_led_gpio = <&pwr_led>,"gpios:4"; -+ pwr_led_activelow = <&pwr_led>,"gpios:8"; -+ pwr_led_trigger = <&pwr_led>,"linux,default-trigger"; -+ -+ audio = <&audio>,"status"; -+ watchdog = <&watchdog>,"status"; -+ random = <&random>,"status"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/bcm2835.dtsi linux-rpi/arch/arm/boot/dts/bcm2835.dtsi ---- linux-4.1.13.orig/arch/arm/boot/dts/bcm2835.dtsi 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/bcm2835.dtsi 2015-11-29 09:42:34.571454018 +0100 -@@ -6,14 +6,15 @@ - interrupt-parent = <&intc>; - - chosen { -- bootargs = "earlyprintk console=ttyAMA0"; -+ bootargs = ""; - }; - -- soc { -+ soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x7e000000 0x20000000 0x02000000>; -+ dma-ranges = <0x40000000 0x00000000 0x20000000>; - - timer@7e003000 { - compatible = "brcm,bcm2835-system-timer"; -@@ -50,16 +51,23 @@ - #interrupt-cells = <2>; - }; - -- watchdog@7e100000 { -+ watchdog: watchdog@7e100000 { - compatible = "brcm,bcm2835-pm-wdt"; - reg = <0x7e100000 0x28>; - }; - -- rng@7e104000 { -+ random: rng@7e104000 { - compatible = "brcm,bcm2835-rng"; - reg = <0x7e104000 0x10>; - }; - -+ mailbox: mailbox@7e00b800 { -+ compatible = "brcm,bcm2835-mbox"; -+ reg = <0x7e00b880 0x40>; -+ interrupts = <0 1>; -+ #mbox-cells = <0>; -+ }; -+ - gpio: gpio@7e200000 { - compatible = "brcm,bcm2835-gpio"; - reg = <0x7e200000 0xb4>; -@@ -83,7 +91,7 @@ - #interrupt-cells = <2>; - }; - -- uart@7e201000 { -+ uart0: uart@7e201000 { - compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell"; - reg = <0x7e201000 0x1000>; - interrupts = <2 25>; -@@ -93,8 +101,8 @@ - - i2s: i2s@7e203000 { - compatible = "brcm,bcm2835-i2s"; -- reg = <0x7e203000 0x20>, -- <0x7e101098 0x02>; -+ reg = <0x7e203000 0x24>, -+ <0x7e101098 0x08>; - - dmas = <&dma 2>, - <&dma 3>; -@@ -102,7 +110,7 @@ - status = "disabled"; - }; - -- spi: spi@7e204000 { -+ spi0: spi@7e204000 { - compatible = "brcm,bcm2835-spi"; - reg = <0x7e204000 0x1000>; - interrupts = <2 22>; -@@ -122,11 +130,14 @@ - status = "disabled"; - }; - -- sdhci: sdhci@7e300000 { -- compatible = "brcm,bcm2835-sdhci"; -+ mmc: mmc@7e300000 { -+ compatible = "brcm,bcm2835-mmc"; - reg = <0x7e300000 0x100>; - interrupts = <2 30>; - clocks = <&clk_mmc>; -+ dmas = <&dma 11>, -+ <&dma 11>; -+ dma-names = "tx", "rx"; - status = "disabled"; - }; - -@@ -140,10 +151,12 @@ - status = "disabled"; - }; - -- usb@7e980000 { -- compatible = "brcm,bcm2835-usb"; -- reg = <0x7e980000 0x10000>; -- interrupts = <1 9>; -+ usb: usb@7e980000 { -+ compatible = "brcm,bcm2708-usb"; -+ reg = <0x7e980000 0x10000>, -+ <0x7e006000 0x1000>; -+ interrupts = <2 0>, -+ <1 9>; - }; - - arm-pmu { -@@ -161,7 +174,7 @@ - reg = <0>; - #clock-cells = <0>; - clock-output-names = "mmc"; -- clock-frequency = <100000000>; -+ clock-frequency = <250000000>; - }; - - clk_i2c: clock@1 { -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/bcm2835-rpi-b.dts linux-rpi/arch/arm/boot/dts/bcm2835-rpi-b.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/bcm2835-rpi-b.dts 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/bcm2835-rpi-b.dts 2015-11-29 09:42:34.571454018 +0100 -@@ -5,19 +5,28 @@ - compatible = "raspberrypi,model-b", "brcm,bcm2835"; - model = "Raspberry Pi Model B"; - -- leds { -- act { -- gpios = <&gpio 16 1>; -- }; -- }; - }; - - &gpio { -- pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>; -- -- /* I2S interface */ -- i2s_alt2: i2s_alt2 { -+ i2s_pins: i2s { - brcm,pins = <28 29 30 31>; -- brcm,function = <6>; /* alt2 */ -+ brcm,function = <4>; /* alt0 */ -+ }; -+}; -+ -+&i2s { -+ #sound-dai-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2s_pins>; -+}; -+ -+&act_led { -+ gpios = <&gpio 16 1>; -+}; -+ -+/ { -+ __overrides__ { -+ act_led_gpio = <&act_led>,"gpios:4"; -+ act_led_activelow = <&act_led>,"gpios:8"; - }; - }; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts linux-rpi/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts 2015-11-29 09:42:34.571454018 +0100 -@@ -4,27 +4,40 @@ - / { - compatible = "raspberrypi,model-b-plus", "brcm,bcm2835"; - model = "Raspberry Pi Model B+"; -- -- leds { -- act { -- gpios = <&gpio 47 0>; -- }; -- -- pwr { -- label = "PWR"; -- gpios = <&gpio 35 0>; -- default-state = "keep"; -- linux,default-trigger = "default-on"; -- }; -- }; - }; - - &gpio { -- pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>; -- -- /* I2S interface */ -- i2s_alt0: i2s_alt0 { -+ i2s_pins: i2s { - brcm,pins = <18 19 20 21>; - brcm,function = <4>; /* alt0 */ - }; - }; -+ -+&i2s { -+ #sound-dai-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2s_pins>; -+}; -+ -+&act_led { -+ gpios = <&gpio 47 0>; -+}; -+ -+&leds { -+ pwr_led: pwr { -+ label = "led1"; -+ linux,default-trigger = "input"; -+ gpios = <&gpio 35 0>; -+ }; -+}; -+ -+/ { -+ __overrides__ { -+ act_led_gpio = <&act_led>,"gpios:4"; -+ act_led_activelow = <&act_led>,"gpios:8"; -+ -+ pwr_led_gpio = <&pwr_led>,"gpios:4"; -+ pwr_led_activelow = <&pwr_led>,"gpios:8"; -+ pwr_led_trigger = <&pwr_led>,"linux,default-trigger"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/bcm2835-rpi.dtsi linux-rpi/arch/arm/boot/dts/bcm2835-rpi.dtsi ---- linux-4.1.13.orig/arch/arm/boot/dts/bcm2835-rpi.dtsi 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/bcm2835-rpi.dtsi 2015-11-29 09:42:34.571454018 +0100 -@@ -1,51 +1,133 @@ - /include/ "bcm2835.dtsi" - - / { -+ /* This is left here in case u-boot needs it */ - memory { - reg = <0 0x10000000>; - }; - -- leds { -+ aliases { -+ soc = &soc; -+ spi0 = &spi0; -+ i2c0 = &i2c0; -+ i2c1 = &i2c1; -+ i2s = &i2s; -+ gpio = &gpio; -+ intc = &intc; -+ leds = &leds; -+ sound = &sound; -+ }; -+ -+ leds: leds { - compatible = "gpio-leds"; - -- act { -- label = "ACT"; -- default-state = "keep"; -- linux,default-trigger = "heartbeat"; -+ act_led: act { -+ label = "led0"; -+ linux,default-trigger = "mmc0"; -+ }; -+ }; -+ -+ soc { -+ firmware: firmware { -+ compatible = "raspberrypi,bcm2835-firmware"; -+ mboxes = <&mailbox>; -+ }; -+ -+ fb: fb { -+ compatible = "brcm,bcm2708-fb"; -+ firmware = <&firmware>; -+ }; -+ -+ thermal: thermal { -+ compatible = "brcm,bcm2835-thermal"; -+ firmware = <&firmware>; -+ }; -+ -+ vchiq: vchiq { -+ compatible = "brcm,bcm2835-vchiq"; -+ reg = <0x7e00b840 0xf>; -+ interrupts = <0 2>; -+ cache-line-size = <32>; -+ firmware = <&firmware>; - }; - }; -+ -+ /* Onboard audio */ -+ audio: audio { -+ compatible = "brcm,bcm2835-audio"; -+ brcm,pwm-channels = <8>; -+ status = "disabled"; -+ }; -+ -+ /* External sound card */ -+ sound: sound { -+ }; - }; - - &gpio { -- pinctrl-names = "default"; -+ spi0_pins: spi0_pins { -+ brcm,pins = <7 8 9 10 11>; -+ brcm,function = <4>; /* alt0 */ -+ }; - -- gpioout: gpioout { -- brcm,pins = <6>; -- brcm,function = <1>; /* GPIO out */ -+ i2c0_pins: i2c0 { -+ brcm,pins = <0 1>; -+ brcm,function = <4>; - }; - -- alt0: alt0 { -- brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15 40 45>; -- brcm,function = <4>; /* alt0 */ -+ i2c1_pins: i2c1 { -+ brcm,pins = <2 3>; -+ brcm,function = <4>; -+ }; -+}; -+ -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_pins>; -+ -+ spidev@0{ -+ compatible = "spidev"; -+ reg = <0>; /* CE0 */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ spi-max-frequency = <500000>; - }; - -- alt3: alt3 { -- brcm,pins = <48 49 50 51 52 53>; -- brcm,function = <7>; /* alt3 */ -+ spidev@1{ -+ compatible = "spidev"; -+ reg = <1>; /* CE1 */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ spi-max-frequency = <500000>; - }; - }; - - &i2c0 { -- status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c0_pins>; - clock-frequency = <100000>; - }; - - &i2c1 { -- status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c1_pins>; - clock-frequency = <100000>; - }; - --&sdhci { -+&mmc { - status = "okay"; - bus-width = <4>; - }; -+ -+/ { -+ __overrides__ { -+ i2s = <&i2s>,"status"; -+ spi = <&spi0>,"status"; -+ i2c0 = <&i2c0>,"status"; -+ i2c1 = <&i2c1>,"status"; -+ i2c0_baudrate = <&i2c0>,"clock-frequency:0"; -+ i2c1_baudrate = <&i2c1>,"clock-frequency:0"; -+ act_led_trigger = <&act_led>,"linux,default-trigger"; -+ audio = <&audio>,"status"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/Makefile linux-rpi/arch/arm/boot/dts/Makefile ---- linux-4.1.13.orig/arch/arm/boot/dts/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/Makefile 2015-11-29 09:42:34.559454815 +0100 -@@ -1,5 +1,24 @@ - ifeq ($(CONFIG_OF),y) - -+dtb-$(CONFIG_BCM2708_DT) += bcm2708-rpi-b.dtb -+dtb-$(CONFIG_BCM2708_DT) += bcm2708-rpi-b-plus.dtb -+dtb-$(CONFIG_BCM2708_DT) += bcm2708-rpi-cm.dtb -+dtb-$(CONFIG_BCM2709_DT) += bcm2709-rpi-2-b.dtb -+ -+# Raspberry Pi -+ifeq ($(CONFIG_BCM2708_DT),y) -+ RPI_DT_OVERLAYS=y -+endif -+ifeq ($(CONFIG_BCM2709_DT),y) -+ RPI_DT_OVERLAYS=y -+endif -+ifeq ($(CONFIG_ARCH_BCM2835),y) -+ RPI_DT_OVERLAYS=y -+endif -+ifeq ($(RPI_DT_OVERLAYS),y) -+ dts-dirs += overlays -+endif -+ - dtb-$(CONFIG_ARCH_ALPINE) += \ - alpine-db.dtb - dtb-$(CONFIG_MACH_ASM9260) += \ -@@ -660,7 +679,17 @@ - mt6592-evb.dtb \ - mt8127-moose.dtb \ - mt8135-evbp1.dtb -+ -+targets += dtbs dtbs_install -+targets += $(dtb-y) -+ - endif - - always := $(dtb-y) -+subdir-y := $(dts-dirs) - clean-files := *.dtb -+ -+# Enable fixups to support overlays on BCM2708 platforms -+ifeq ($(RPI_DT_OVERLAYS),y) -+ DTC_FLAGS ?= -@ -+endif -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/ads7846-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/ads7846-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/ads7846-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/ads7846-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,83 @@ -+/* -+ * Generic Device Tree overlay for the ADS7846 touch controller -+ * -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709"; -+ -+ fragment@0 { -+ target = <&spi0>; -+ __overlay__ { -+ status = "okay"; -+ -+ spidev@0{ -+ status = "disabled"; -+ }; -+ -+ spidev@1{ -+ status = "disabled"; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&gpio>; -+ __overlay__ { -+ ads7846_pins: ads7846_pins { -+ brcm,pins = <255>; /* illegal default value */ -+ brcm,function = <0>; /* in */ -+ brcm,pull = <0>; /* none */ -+ }; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&spi0>; -+ __overlay__ { -+ /* needed to avoid dtc warning */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ads7846: ads7846@1 { -+ compatible = "ti,ads7846"; -+ reg = <1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&ads7846_pins>; -+ -+ spi-max-frequency = <2000000>; -+ interrupts = <255 2>; /* high-to-low edge triggered */ -+ interrupt-parent = <&gpio>; -+ pendown-gpio = <&gpio 255 0>; -+ -+ /* driver defaults */ -+ ti,x-min = /bits/ 16 <0>; -+ ti,y-min = /bits/ 16 <0>; -+ ti,x-max = /bits/ 16 <0x0FFF>; -+ ti,y-max = /bits/ 16 <0x0FFF>; -+ ti,pressure-min = /bits/ 16 <0>; -+ ti,pressure-max = /bits/ 16 <0xFFFF>; -+ ti,x-plate-ohms = /bits/ 16 <400>; -+ }; -+ }; -+ }; -+ __overrides__ { -+ cs = <&ads7846>,"reg:0"; -+ speed = <&ads7846>,"spi-max-frequency:0"; -+ penirq = <&ads7846_pins>,"brcm,pins:0", /* REQUIRED */ -+ <&ads7846>,"interrupts:0", -+ <&ads7846>,"pendown-gpio:4"; -+ penirq_pull = <&ads7846_pins>,"brcm,pull:0"; -+ swapxy = <&ads7846>,"ti,swap-xy?"; -+ xmin = <&ads7846>,"ti,x-min;0"; -+ ymin = <&ads7846>,"ti,y-min;0"; -+ xmax = <&ads7846>,"ti,x-max;0"; -+ ymax = <&ads7846>,"ti,y-max;0"; -+ pmin = <&ads7846>,"ti,pressure-min;0"; -+ pmax = <&ads7846>,"ti,pressure-max;0"; -+ xohms = <&ads7846>,"ti,x-plate-ohms;0"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/at86rf233-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/at86rf233-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/at86rf233-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/at86rf233-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,54 @@ -+/dts-v1/; -+/plugin/; -+ -+/* Overlay for Atmel AT86RF233 IEEE 802.15.4 WPAN transceiver on spi0.0 */ -+ -+/ { -+ compatible = "brcm,bcm2835", "brcm,bcm2836", "brcm,bcm2708", "brcm,bcm2709"; -+ -+ fragment@0 { -+ target = <&spi0>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ status = "okay"; -+ -+ spidev@0{ -+ status = "disabled"; -+ }; -+ -+ lowpan0: at86rf233@0 { -+ compatible = "atmel,at86rf233"; -+ reg = <0>; -+ interrupt-parent = <&gpio>; -+ interrupts = <23 4>; /* active high */ -+ reset-gpio = <&gpio 24 1>; -+ sleep-gpio = <&gpio 25 1>; -+ spi-max-frequency = <6000000>; -+ xtal-trim = /bits/ 8 <0xf>; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&gpio>; -+ __overlay__ { -+ lowpan0_pins: lowpan0_pins { -+ brcm,pins = <23 24 25>; -+ brcm,function = <0 1 1>; /* in out out */ -+ }; -+ }; -+ }; -+ -+ __overrides__ { -+ interrupt = <&lowpan0>, "interrupts:0", -+ <&lowpan0_pins>, "brcm,pins:0"; -+ reset = <&lowpan0>, "reset-gpio:4", -+ <&lowpan0_pins>, "brcm,pins:4"; -+ sleep = <&lowpan0>, "sleep-gpio:4", -+ <&lowpan0_pins>, "brcm,pins:8"; -+ speed = <&lowpan0>, "spi-max-frequency:0"; -+ trim = <&lowpan0>, "xtal-trim.0"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/bmp085_i2c-sensor-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/bmp085_i2c-sensor-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/bmp085_i2c-sensor-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/bmp085_i2c-sensor-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,23 @@ -+// Definitions for BMP085/BMP180 digital barometric pressure and temperature sensors from Bosch Sensortec -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2708"; -+ -+ fragment@0 { -+ target = <&i2c_arm>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ bmp085@77 { -+ compatible = "bosch,bmp085"; -+ reg = <0x77>; -+ default-oversampling = <3>; -+ status = "okay"; -+ }; -+ }; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/dht11-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/dht11-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/dht11-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/dht11-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,39 @@ -+/* -+ * Overlay for the DHT11/21/22 humidity/temperature sensor modules. -+ */ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2708"; -+ -+ fragment@0 { -+ target-path = "/"; -+ __overlay__ { -+ -+ dht11: dht11@0 { -+ compatible = "dht11"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&dht11_pins>; -+ gpios = <&gpio 4 0>; -+ status = "okay"; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&gpio>; -+ __overlay__ { -+ dht11_pins: dht11_pins { -+ brcm,pins = <4>; -+ brcm,function = <0>; // in -+ brcm,pull = <0>; // off -+ }; -+ }; -+ }; -+ -+ __overrides__ { -+ gpiopin = <&dht11_pins>,"brcm,pins:0", -+ <&dht11>,"gpios:4"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/enc28j60-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/enc28j60-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/enc28j60-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/enc28j60-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,50 @@ -+// Overlay for the Microchip ENC28J60 Ethernet Controller -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2708"; -+ -+ fragment@0 { -+ target = <&spi0>; -+ __overlay__ { -+ /* needed to avoid dtc warning */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ status = "okay"; -+ -+ spidev@0{ -+ status = "disabled"; -+ }; -+ -+ eth1: enc28j60@0{ -+ compatible = "microchip,enc28j60"; -+ reg = <0>; /* CE0 */ -+ pinctrl-names = "default"; -+ pinctrl-0 = <ð1_pins>; -+ interrupt-parent = <&gpio>; -+ interrupts = <25 0x2>; /* falling edge */ -+ spi-max-frequency = <12000000>; -+ status = "okay"; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&gpio>; -+ __overlay__ { -+ eth1_pins: eth1_pins { -+ brcm,pins = <25>; -+ brcm,function = <0>; /* in */ -+ brcm,pull = <0>; /* none */ -+ }; -+ }; -+ }; -+ -+ __overrides__ { -+ int_pin = <ð1>, "interrupts:0", -+ <ð1_pins>, "brcm,pins:0"; -+ speed = <ð1>, "spi-max-frequency:0"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/gpio-ir-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/gpio-ir-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/gpio-ir-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/gpio-ir-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,45 @@ -+// Definitions for ir-gpio module -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2708"; -+ -+ fragment@0 { -+ target-path = "/"; -+ __overlay__ { -+ gpio_ir: ir-receiver { -+ compatible = "gpio-ir-receiver"; -+ -+ // pin number, high or low -+ gpios = <&gpio 18 1>; -+ -+ // parameter for keymap name -+ linux,rc-map-name = "rc-rc6-mce"; -+ -+ status = "okay"; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&gpio>; -+ __overlay__ { -+ gpio_ir_pins: gpio_ir_pins { -+ brcm,pins = <18>; // pin 18 -+ brcm,function = <0>; // in -+ brcm,pull = <1>; // down -+ }; -+ }; -+ }; -+ -+ __overrides__ { -+ // parameters -+ gpio_pin = <&gpio_ir>,"gpios:4", -+ <&gpio_ir_pins>,"brcm,pins:0", -+ <&gpio_ir_pins>,"brcm,pull:0"; // pin number -+ gpio_pull = <&gpio_ir_pins>,"brcm,pull:0"; // pull-up/down state -+ -+ rc-map-name = <&gpio_ir>,"linux,rc-map-name"; // default rc map -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/gpio-poweroff-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/gpio-poweroff-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/gpio-poweroff-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/gpio-poweroff-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,34 @@ -+// Definitions for gpio-poweroff module -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2708"; -+ -+ fragment@0 { -+ target-path = "/"; -+ __overlay__ { -+ power_ctrl: power_ctrl { -+ compatible = "gpio-poweroff"; -+ gpios = <&gpio 26 0>; -+ force; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&gpio>; -+ __overlay__ { -+ power_ctrl_pins: power_ctrl_pins { -+ brcm,pins = <26>; -+ brcm,function = <1>; // out -+ }; -+ }; -+ }; -+ -+ __overrides__ { -+ gpiopin = <&power_ctrl>,"gpios:4", -+ <&power_ctrl_pins>,"brcm,pins:0"; -+ active_low = <&power_ctrl>,"gpios:8"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/hifiberry-amp-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/hifiberry-amp-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/hifiberry-amp-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/hifiberry-amp-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,39 @@ -+// Definitions for HiFiBerry Amp/Amp+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2708"; -+ -+ fragment@0 { -+ target = <&sound>; -+ __overlay__ { -+ compatible = "hifiberry,hifiberry-amp"; -+ i2s-controller = <&i2s>; -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&i2s>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&i2c1>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ tas5713@1b { -+ #sound-dai-cells = <0>; -+ compatible = "ti,tas5713"; -+ reg = <0x1b>; -+ status = "okay"; -+ }; -+ }; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/hifiberry-dac-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/hifiberry-dac-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/hifiberry-dac-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/hifiberry-dac-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,34 @@ -+// Definitions for HiFiBerry DAC -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2708"; -+ -+ fragment@0 { -+ target = <&sound>; -+ __overlay__ { -+ compatible = "hifiberry,hifiberry-dac"; -+ i2s-controller = <&i2s>; -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&i2s>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@2 { -+ target-path = "/"; -+ __overlay__ { -+ pcm5102a-codec { -+ #sound-dai-cells = <0>; -+ compatible = "ti,pcm5102a"; -+ status = "okay"; -+ }; -+ }; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/hifiberry-dacplus-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/hifiberry-dacplus-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/hifiberry-dacplus-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/hifiberry-dacplus-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,50 @@ -+// Definitions for HiFiBerry DAC+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2708"; -+ -+ fragment@0 { -+ target-path = "/clocks"; -+ __overlay__ { -+ dacpro_osc: dacpro_osc { -+ compatible = "hifiberry,dacpro-clk"; -+ #clock-cells = <0>; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&sound>; -+ __overlay__ { -+ compatible = "hifiberry,hifiberry-dacplus"; -+ i2s-controller = <&i2s>; -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&i2s>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@3 { -+ target = <&i2c1>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ pcm5122@4d { -+ #sound-dai-cells = <0>; -+ compatible = "ti,pcm5122"; -+ reg = <0x4d>; -+ clocks = <&dacpro_osc>; -+ status = "okay"; -+ }; -+ }; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/hifiberry-digi-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/hifiberry-digi-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/hifiberry-digi-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/hifiberry-digi-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,39 @@ -+// Definitions for HiFiBerry Digi -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2708"; -+ -+ fragment@0 { -+ target = <&sound>; -+ __overlay__ { -+ compatible = "hifiberry,hifiberry-digi"; -+ i2s-controller = <&i2s>; -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&i2s>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&i2c1>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ wm8804@3b { -+ #sound-dai-cells = <0>; -+ compatible = "wlf,wm8804"; -+ reg = <0x3b>; -+ status = "okay"; -+ }; -+ }; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/hy28a-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/hy28a-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/hy28a-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/hy28a-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,87 @@ -+/* -+ * Device Tree overlay for HY28A display -+ * -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709"; -+ -+ fragment@0 { -+ target = <&spi0>; -+ __overlay__ { -+ status = "okay"; -+ -+ spidev@0{ -+ status = "disabled"; -+ }; -+ -+ spidev@1{ -+ status = "disabled"; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&gpio>; -+ __overlay__ { -+ hy28a_pins: hy28a_pins { -+ brcm,pins = <17 25 18>; -+ brcm,function = <0 1 1>; /* in out out */ -+ }; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&spi0>; -+ __overlay__ { -+ /* needed to avoid dtc warning */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ hy28a: hy28a@0{ -+ compatible = "ilitek,ili9320"; -+ reg = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hy28a_pins>; -+ -+ spi-max-frequency = <32000000>; -+ spi-cpol; -+ spi-cpha; -+ rotate = <270>; -+ bgr; -+ fps = <50>; -+ buswidth = <8>; -+ startbyte = <0x70>; -+ reset-gpios = <&gpio 25 0>; -+ led-gpios = <&gpio 18 1>; -+ debug = <0>; -+ }; -+ -+ hy28a_ts: hy28a-ts@1 { -+ compatible = "ti,ads7846"; -+ reg = <1>; -+ -+ spi-max-frequency = <2000000>; -+ interrupts = <17 2>; /* high-to-low edge triggered */ -+ interrupt-parent = <&gpio>; -+ pendown-gpio = <&gpio 17 0>; -+ ti,x-plate-ohms = /bits/ 16 <100>; -+ ti,pressure-max = /bits/ 16 <255>; -+ }; -+ }; -+ }; -+ __overrides__ { -+ speed = <&hy28a>,"spi-max-frequency:0"; -+ rotate = <&hy28a>,"rotate:0"; -+ fps = <&hy28a>,"fps:0"; -+ debug = <&hy28a>,"debug:0"; -+ xohms = <&hy28a_ts>,"ti,x-plate-ohms;0"; -+ resetgpio = <&hy28a>,"reset-gpios:4", -+ <&hy28a_pins>, "brcm,pins:1"; -+ ledgpio = <&hy28a>,"led-gpios:4", -+ <&hy28a_pins>, "brcm,pins:2"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/hy28b-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/hy28b-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/hy28b-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/hy28b-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,142 @@ -+/* -+ * Device Tree overlay for HY28b display shield by Texy -+ * -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709"; -+ -+ fragment@0 { -+ target = <&spi0>; -+ __overlay__ { -+ status = "okay"; -+ -+ spidev@0{ -+ status = "disabled"; -+ }; -+ -+ spidev@1{ -+ status = "disabled"; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&gpio>; -+ __overlay__ { -+ hy28b_pins: hy28b_pins { -+ brcm,pins = <17 25 18>; -+ brcm,function = <0 1 1>; /* in out out */ -+ }; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&spi0>; -+ __overlay__ { -+ /* needed to avoid dtc warning */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ hy28b: hy28b@0{ -+ compatible = "ilitek,ili9325"; -+ reg = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&hy28b_pins>; -+ -+ spi-max-frequency = <48000000>; -+ spi-cpol; -+ spi-cpha; -+ rotate = <270>; -+ bgr; -+ fps = <50>; -+ buswidth = <8>; -+ startbyte = <0x70>; -+ reset-gpios = <&gpio 25 0>; -+ led-gpios = <&gpio 18 1>; -+ -+ gamma = "04 1F 4 7 7 0 7 7 6 0\n0F 00 1 7 4 0 0 0 6 7"; -+ -+ init = <0x10000e7 0x0010 -+ 0x1000000 0x0001 -+ 0x1000001 0x0100 -+ 0x1000002 0x0700 -+ 0x1000003 0x1030 -+ 0x1000004 0x0000 -+ 0x1000008 0x0207 -+ 0x1000009 0x0000 -+ 0x100000a 0x0000 -+ 0x100000c 0x0001 -+ 0x100000d 0x0000 -+ 0x100000f 0x0000 -+ 0x1000010 0x0000 -+ 0x1000011 0x0007 -+ 0x1000012 0x0000 -+ 0x1000013 0x0000 -+ 0x2000032 -+ 0x1000010 0x1590 -+ 0x1000011 0x0227 -+ 0x2000032 -+ 0x1000012 0x009c -+ 0x2000032 -+ 0x1000013 0x1900 -+ 0x1000029 0x0023 -+ 0x100002b 0x000e -+ 0x2000032 -+ 0x1000020 0x0000 -+ 0x1000021 0x0000 -+ 0x2000032 -+ 0x1000050 0x0000 -+ 0x1000051 0x00ef -+ 0x1000052 0x0000 -+ 0x1000053 0x013f -+ 0x1000060 0xa700 -+ 0x1000061 0x0001 -+ 0x100006a 0x0000 -+ 0x1000080 0x0000 -+ 0x1000081 0x0000 -+ 0x1000082 0x0000 -+ 0x1000083 0x0000 -+ 0x1000084 0x0000 -+ 0x1000085 0x0000 -+ 0x1000090 0x0010 -+ 0x1000092 0x0000 -+ 0x1000093 0x0003 -+ 0x1000095 0x0110 -+ 0x1000097 0x0000 -+ 0x1000098 0x0000 -+ 0x1000007 0x0133 -+ 0x1000020 0x0000 -+ 0x1000021 0x0000 -+ 0x2000064>; -+ debug = <0>; -+ }; -+ -+ hy28b_ts: hy28b-ts@1 { -+ compatible = "ti,ads7846"; -+ reg = <1>; -+ -+ spi-max-frequency = <2000000>; -+ interrupts = <17 2>; /* high-to-low edge triggered */ -+ interrupt-parent = <&gpio>; -+ pendown-gpio = <&gpio 17 0>; -+ ti,x-plate-ohms = /bits/ 16 <100>; -+ ti,pressure-max = /bits/ 16 <255>; -+ }; -+ }; -+ }; -+ __overrides__ { -+ speed = <&hy28b>,"spi-max-frequency:0"; -+ rotate = <&hy28b>,"rotate:0"; -+ fps = <&hy28b>,"fps:0"; -+ debug = <&hy28b>,"debug:0"; -+ xohms = <&hy28b_ts>,"ti,x-plate-ohms;0"; -+ resetgpio = <&hy28b>,"reset-gpios:4", -+ <&hy28b_pins>, "brcm,pins:1"; -+ ledgpio = <&hy28b>,"led-gpios:4", -+ <&hy28b_pins>, "brcm,pins:2"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,28 @@ -+// Overlay for i2c_gpio bitbanging host bus. -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2708"; -+ -+ fragment@0 { -+ target-path = "/"; -+ __overlay__ { -+ i2c_gpio: i2c@0 { -+ compatible = "i2c-gpio"; -+ gpios = <&gpio 23 0 /* sda */ -+ &gpio 24 0 /* scl */ -+ >; -+ i2c-gpio,delay-us = <2>; /* ~100 kHz */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ }; -+ }; -+ __overrides__ { -+ i2c_gpio_sda = <&i2c_gpio>,"gpios:4"; -+ i2c_gpio_scl = <&i2c_gpio>,"gpios:16"; -+ i2c_gpio_delay_us = <&i2c_gpio>,"i2c-gpio,delay-us:0"; -+ }; -+}; -+ -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,55 @@ -+// Definitions for several I2C based Real Time Clocks -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2708"; -+ -+ fragment@0 { -+ target = <&i2c_arm>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ ds1307: ds1307@68 { -+ compatible = "maxim,ds1307"; -+ reg = <0x68>; -+ status = "disable"; -+ }; -+ mcp7941x: mcp7941x@6f { -+ compatible = "microchip,mcp7941x"; -+ reg = <0x6f>; -+ status = "disable"; -+ }; -+ ds3231: ds3231@68 { -+ compatible = "maxim,ds3231"; -+ reg = <0x68>; -+ status = "disable"; -+ }; -+ pcf2127: pcf2127@51 { -+ compatible = "nxp,pcf2127"; -+ reg = <0x51>; -+ status = "disable"; -+ }; -+ pcf8523: pcf8523@68 { -+ compatible = "nxp,pcf8523"; -+ reg = <0x68>; -+ status = "disable"; -+ }; -+ pcf8563: pcf8563@51 { -+ compatible = "nxp,pcf8563"; -+ reg = <0x51>; -+ status = "disable"; -+ }; -+ }; -+ }; -+ __overrides__ { -+ ds1307 = <&ds1307>,"status"; -+ ds3231 = <&ds3231>,"status"; -+ mcp7941x = <&mcp7941x>,"status"; -+ pcf2127 = <&pcf2127>,"status"; -+ pcf8523 = <&pcf8523>,"status"; -+ pcf8563 = <&pcf8563>,"status"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/i2s-mmap-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/i2s-mmap-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/i2s-mmap-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/i2s-mmap-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,13 @@ -+/dts-v1/; -+/plugin/; -+ -+/{ -+ compatible = "brcm,bcm2708"; -+ -+ fragment@0 { -+ target = <&i2s>; -+ __overlay__ { -+ brcm,enable-mmap; -+ }; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/iqaudio-dac-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/iqaudio-dac-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/iqaudio-dac-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/iqaudio-dac-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,39 @@ -+// Definitions for IQaudIO DAC -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2708"; -+ -+ fragment@0 { -+ target = <&sound>; -+ __overlay__ { -+ compatible = "iqaudio,iqaudio-dac"; -+ i2s-controller = <&i2s>; -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&i2s>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&i2c1>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ pcm5122@4c { -+ #sound-dai-cells = <0>; -+ compatible = "ti,pcm5122"; -+ reg = <0x4c>; -+ status = "okay"; -+ }; -+ }; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/iqaudio-dacplus-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/iqaudio-dacplus-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/iqaudio-dacplus-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/iqaudio-dacplus-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,39 @@ -+// Definitions for IQaudIO DAC+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2708"; -+ -+ fragment@0 { -+ target = <&sound>; -+ __overlay__ { -+ compatible = "iqaudio,iqaudio-dac"; -+ i2s-controller = <&i2s>; -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&i2s>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&i2c1>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ pcm5122@4c { -+ #sound-dai-cells = <0>; -+ compatible = "ti,pcm5122"; -+ reg = <0x4c>; -+ status = "okay"; -+ }; -+ }; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/lirc-rpi-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/lirc-rpi-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/lirc-rpi-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/lirc-rpi-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,57 @@ -+// Definitions for lirc-rpi module -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2708"; -+ -+ fragment@0 { -+ target-path = "/"; -+ __overlay__ { -+ lirc_rpi: lirc_rpi { -+ compatible = "rpi,lirc-rpi"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&lirc_pins>; -+ status = "okay"; -+ -+ // Override autodetection of IR receiver circuit -+ // (0 = active high, 1 = active low, -1 = no override ) -+ rpi,sense = <0xffffffff>; -+ -+ // Software carrier -+ // (0 = off, 1 = on) -+ rpi,softcarrier = <1>; -+ -+ // Invert output -+ // (0 = off, 1 = on) -+ rpi,invert = <0>; -+ -+ // Enable debugging messages -+ // (0 = off, 1 = on) -+ rpi,debug = <0>; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&gpio>; -+ __overlay__ { -+ lirc_pins: lirc_pins { -+ brcm,pins = <17 18>; -+ brcm,function = <1 0>; // out in -+ brcm,pull = <0 1>; // off down -+ }; -+ }; -+ }; -+ -+ __overrides__ { -+ gpio_out_pin = <&lirc_pins>,"brcm,pins:0"; -+ gpio_in_pin = <&lirc_pins>,"brcm,pins:4"; -+ gpio_in_pull = <&lirc_pins>,"brcm,pull:4"; -+ -+ sense = <&lirc_rpi>,"rpi,sense:0"; -+ softcarrier = <&lirc_rpi>,"rpi,softcarrier:0"; -+ invert = <&lirc_rpi>,"rpi,invert:0"; -+ debug = <&lirc_rpi>,"rpi,debug:0"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/Makefile linux-rpi/arch/arm/boot/dts/overlays/Makefile ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/Makefile 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,77 @@ -+ifeq ($(CONFIG_OF),y) -+ -+# Overlays for the Raspberry Pi platform -+ -+ifeq ($(CONFIG_BCM2708_DT),y) -+ RPI_DT_OVERLAYS=y -+endif -+ifeq ($(CONFIG_BCM2709_DT),y) -+ RPI_DT_OVERLAYS=y -+endif -+ifeq ($(CONFIG_ARCH_BCM2835),y) -+ RPI_DT_OVERLAYS=y -+endif -+ -+dtb-$(RPI_DT_OVERLAYS) += ads7846-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += at86rf233-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += bmp085_i2c-sensor-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += dht11-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += enc28j60-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += gpio-ir-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += gpio-poweroff-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += hifiberry-amp-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += hifiberry-dac-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += hifiberry-dacplus-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += hifiberry-digi-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += hy28a-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += hy28b-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += i2c-rtc-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += i2c-gpio-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += i2s-mmap-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += iqaudio-dac-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += iqaudio-dacplus-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += lirc-rpi-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += mcp2515-can0-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += mcp2515-can1-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += mmc-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += mz61581-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += piscreen-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += piscreen2r-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += pitft28-capacitive-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += pitft28-resistive-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += pps-gpio-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += pwm-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += pwm-2chan-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += raspidac3-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += rpi-backlight-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += rpi-dac-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += rpi-display-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += rpi-ft5406-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += rpi-proto-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += rpi-sense-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += sdhost-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += sdio-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += smi-dev-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += smi-nand-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += smi-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += spi-bcm2708-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += spi-bcm2835-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += spi-dma-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += tinylcd35-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += uart1-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += vga666-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += w1-gpio-overlay.dtb -+dtb-$(RPI_DT_OVERLAYS) += w1-gpio-pullup-overlay.dtb -+ -+targets += dtbs dtbs_install -+targets += $(dtb-y) -+ -+endif -+ -+always := $(dtb-y) -+clean-files := *.dtb -+ -+# Enable fixups to support overlays on BCM2708 platforms -+ifeq ($(RPI_DT_OVERLAYS),y) -+ DTC_FLAGS ?= -@ -+endif -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/mcp2515-can0-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/mcp2515-can0-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/mcp2515-can0-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/mcp2515-can0-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,69 @@ -+/* -+ * Device tree overlay for mcp251x/can0 on spi0.0 -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2835", "brcm,bcm2836", "brcm,bcm2708", "brcm,bcm2709"; -+ /* disable spi-dev for spi0.0 */ -+ fragment@0 { -+ target = <&spi0>; -+ __overlay__ { -+ status = "okay"; -+ spidev@0{ -+ status = "disabled"; -+ }; -+ }; -+ }; -+ -+ /* the interrupt pin of the can-controller */ -+ fragment@1 { -+ target = <&gpio>; -+ __overlay__ { -+ can0_pins: can0_pins { -+ brcm,pins = <25>; -+ brcm,function = <0>; /* input */ -+ }; -+ }; -+ }; -+ -+ /* the clock/oscillator of the can-controller */ -+ fragment@2 { -+ target-path = "/clocks"; -+ __overlay__ { -+ /* external oscillator of mcp2515 on SPI0.0 */ -+ can0_osc: can0_osc { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <16000000>; -+ }; -+ }; -+ }; -+ -+ /* the spi config of the can-controller itself binding everything together */ -+ fragment@3 { -+ target = <&spi0>; -+ __overlay__ { -+ /* needed to avoid dtc warning */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ can0: mcp2515@0 { -+ reg = <0>; -+ compatible = "microchip,mcp2515"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&can0_pins>; -+ spi-max-frequency = <10000000>; -+ interrupt-parent = <&gpio>; -+ interrupts = <25 0x2>; -+ clocks = <&can0_osc>; -+ }; -+ }; -+ }; -+ __overrides__ { -+ oscillator = <&can0_osc>,"clock-frequency:0"; -+ spimaxfrequency = <&can0>,"spi-max-frequency:0"; -+ interrupt = <&can0_pins>,"brcm,pins:0",<&can0>,"interrupts:0"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/mcp2515-can1-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/mcp2515-can1-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/mcp2515-can1-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/mcp2515-can1-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,69 @@ -+/* -+ * Device tree overlay for mcp251x/can1 on spi0.1 edited by petit_miner -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2835", "brcm,bcm2836", "brcm,bcm2708", "brcm,bcm2709"; -+ /* disable spi-dev for spi0.1 */ -+ fragment@0 { -+ target = <&spi0>; -+ __overlay__ { -+ status = "okay"; -+ spidev@1{ -+ status = "disabled"; -+ }; -+ }; -+ }; -+ -+ /* the interrupt pin of the can-controller */ -+ fragment@1 { -+ target = <&gpio>; -+ __overlay__ { -+ can1_pins: can1_pins { -+ brcm,pins = <25>; -+ brcm,function = <0>; /* input */ -+ }; -+ }; -+ }; -+ -+ /* the clock/oscillator of the can-controller */ -+ fragment@2 { -+ target-path = "/clocks"; -+ __overlay__ { -+ /* external oscillator of mcp2515 on spi0.1 */ -+ can1_osc: can1_osc { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <16000000>; -+ }; -+ }; -+ }; -+ -+ /* the spi config of the can-controller itself binding everything together */ -+ fragment@3 { -+ target = <&spi0>; -+ __overlay__ { -+ /* needed to avoid dtc warning */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ can1: mcp2515@1 { -+ reg = <1>; -+ compatible = "microchip,mcp2515"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&can1_pins>; -+ spi-max-frequency = <10000000>; -+ interrupt-parent = <&gpio>; -+ interrupts = <25 0x2>; -+ clocks = <&can1_osc>; -+ }; -+ }; -+ }; -+ __overrides__ { -+ oscillator = <&can1_osc>,"clock-frequency:0"; -+ spimaxfrequency = <&can1>,"spi-max-frequency:0"; -+ interrupt = <&can1_pins>,"brcm,pins:0",<&can1>,"interrupts:0"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/mmc-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/mmc-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/mmc-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/mmc-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,19 @@ -+/dts-v1/; -+/plugin/; -+ -+/{ -+ compatible = "brcm,bcm2708"; -+ -+ fragment@0 { -+ target = <&mmc>; -+ -+ frag0: __overlay__ { -+ brcm,overclock-50 = <0>; -+ }; -+ }; -+ -+ __overrides__ { -+ overclock_50 = <&frag0>,"brcm,overclock-50:0"; -+ force_pio = <&frag0>,"brcm,force-pio?"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/mz61581-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/mz61581-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/mz61581-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/mz61581-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,111 @@ -+/* -+ * Device Tree overlay for MZ61581-PI-EXT 2014.12.28 by Tontec -+ * -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709"; -+ -+ fragment@0 { -+ target = <&spi0>; -+ __overlay__ { -+ status = "okay"; -+ -+ spidev@0{ -+ status = "disabled"; -+ }; -+ -+ spidev@1{ -+ status = "disabled"; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&gpio>; -+ __overlay__ { -+ mz61581_pins: mz61581_pins { -+ brcm,pins = <4 15 18 25>; -+ brcm,function = <0 1 1 1>; /* in out out out */ -+ }; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&spi0>; -+ __overlay__ { -+ /* needed to avoid dtc warning */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ mz61581: mz61581@0{ -+ compatible = "samsung,s6d02a1"; -+ reg = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mz61581_pins>; -+ -+ spi-max-frequency = <128000000>; -+ spi-cpol; -+ spi-cpha; -+ -+ width = <320>; -+ height = <480>; -+ rotate = <270>; -+ bgr; -+ fps = <30>; -+ buswidth = <8>; -+ txbuflen = <32768>; -+ -+ reset-gpios = <&gpio 15 0>; -+ dc-gpios = <&gpio 25 0>; -+ led-gpios = <&gpio 18 0>; -+ -+ init = <0x10000b0 00 -+ 0x1000011 -+ 0x20000ff -+ 0x10000b3 0x02 0x00 0x00 0x00 -+ 0x10000c0 0x13 0x3b 0x00 0x02 0x00 0x01 0x00 0x43 -+ 0x10000c1 0x08 0x16 0x08 0x08 -+ 0x10000c4 0x11 0x07 0x03 0x03 -+ 0x10000c6 0x00 -+ 0x10000c8 0x03 0x03 0x13 0x5c 0x03 0x07 0x14 0x08 0x00 0x21 0x08 0x14 0x07 0x53 0x0c 0x13 0x03 0x03 0x21 0x00 -+ 0x1000035 0x00 -+ 0x1000036 0xa0 -+ 0x100003a 0x55 -+ 0x1000044 0x00 0x01 -+ 0x10000d0 0x07 0x07 0x1d 0x03 -+ 0x10000d1 0x03 0x30 0x10 -+ 0x10000d2 0x03 0x14 0x04 -+ 0x1000029 -+ 0x100002c>; -+ -+ /* This is a workaround to make sure the init sequence slows down and doesn't fail */ -+ debug = <3>; -+ }; -+ -+ mz61581_ts: mz61581_ts@1 { -+ compatible = "ti,ads7846"; -+ reg = <1>; -+ -+ spi-max-frequency = <2000000>; -+ interrupts = <4 2>; /* high-to-low edge triggered */ -+ interrupt-parent = <&gpio>; -+ pendown-gpio = <&gpio 4 0>; -+ -+ ti,x-plate-ohms = /bits/ 16 <60>; -+ ti,pressure-max = /bits/ 16 <255>; -+ }; -+ }; -+ }; -+ __overrides__ { -+ speed = <&mz61581>, "spi-max-frequency:0"; -+ rotate = <&mz61581>, "rotate:0"; -+ fps = <&mz61581>, "fps:0"; -+ txbuflen = <&mz61581>, "txbuflen:0"; -+ debug = <&mz61581>, "debug:0"; -+ xohms = <&mz61581_ts>,"ti,x-plate-ohms;0"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/piscreen2r-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/piscreen2r-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/piscreen2r-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/piscreen2r-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,100 @@ -+ /* -+ * Device Tree overlay for PiScreen2 3.5" TFT with resistive touch by Ozzmaker.com -+ * -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709"; -+ -+ fragment@0 { -+ target = <&spi0>; -+ __overlay__ { -+ status = "okay"; -+ -+ spidev@0{ -+ status = "disabled"; -+ }; -+ -+ spidev@1{ -+ status = "disabled"; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&gpio>; -+ __overlay__ { -+ piscreen2_pins: piscreen2_pins { -+ brcm,pins = <17 25 24 22>; -+ brcm,function = <0 1 1 1>; /* in out out out */ -+ }; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&spi0>; -+ __overlay__ { -+ /* needed to avoid dtc warning */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ piscreen2: piscreen2@0{ -+ compatible = "ilitek,ili9486"; -+ reg = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&piscreen2_pins>; -+ bgr; -+ spi-max-frequency = <64000000>; -+ rotate = <90>; -+ fps = <30>; -+ buswidth = <8>; -+ regwidth = <16>; -+ txbuflen = <32768>; -+ reset-gpios = <&gpio 25 0>; -+ dc-gpios = <&gpio 24 0>; -+ led-gpios = <&gpio 22 1>; -+ debug = <0>; -+ -+ init = <0x10000b0 0x00 -+ 0x1000011 -+ 0x20000ff -+ 0x100003a 0x55 -+ 0x1000036 0x28 -+ 0x10000c0 0x11 0x09 -+ 0x10000c1 0x41 -+ 0x10000c5 0x00 0x00 0x00 0x00 -+ 0x10000b6 0x00 0x02 -+ 0x10000f7 0xa9 0x51 0x2c 0x2 -+ 0x10000be 0x00 0x04 -+ 0x10000e9 0x00 -+ 0x1000011 -+ 0x1000029>; -+ -+ }; -+ -+ piscreen2_ts: piscreen2-ts@1 { -+ compatible = "ti,ads7846"; -+ reg = <1>; -+ -+ spi-max-frequency = <2000000>; -+ interrupts = <17 2>; /* high-to-low edge triggered */ -+ interrupt-parent = <&gpio>; -+ pendown-gpio = <&gpio 17 0>; -+ ti,swap-xy; -+ ti,x-plate-ohms = /bits/ 16 <100>; -+ ti,pressure-max = /bits/ 16 <255>; -+ }; -+ }; -+ }; -+ __overrides__ { -+ speed = <&piscreen2>,"spi-max-frequency:0"; -+ rotate = <&piscreen2>,"rotate:0"; -+ fps = <&piscreen2>,"fps:0"; -+ debug = <&piscreen2>,"debug:0"; -+ xohms = <&piscreen2_ts>,"ti,x-plate-ohms;0"; -+ }; -+}; -+ -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/piscreen-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/piscreen-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/piscreen-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/piscreen-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,96 @@ -+/* -+ * Device Tree overlay for PiScreen 3.5" display shield by Ozzmaker -+ * -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709"; -+ -+ fragment@0 { -+ target = <&spi0>; -+ __overlay__ { -+ status = "okay"; -+ -+ spidev@0{ -+ status = "disabled"; -+ }; -+ -+ spidev@1{ -+ status = "disabled"; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&gpio>; -+ __overlay__ { -+ piscreen_pins: piscreen_pins { -+ brcm,pins = <17 25 24 22>; -+ brcm,function = <0 1 1 1>; /* in out out out */ -+ }; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&spi0>; -+ __overlay__ { -+ /* needed to avoid dtc warning */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ piscreen: piscreen@0{ -+ compatible = "ilitek,ili9486"; -+ reg = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&piscreen_pins>; -+ -+ spi-max-frequency = <24000000>; -+ rotate = <270>; -+ bgr; -+ fps = <30>; -+ buswidth = <8>; -+ regwidth = <16>; -+ reset-gpios = <&gpio 25 0>; -+ dc-gpios = <&gpio 24 0>; -+ led-gpios = <&gpio 22 1>; -+ debug = <0>; -+ -+ init = <0x10000b0 0x00 -+ 0x1000011 -+ 0x20000ff -+ 0x100003a 0x55 -+ 0x1000036 0x28 -+ 0x10000c2 0x44 -+ 0x10000c5 0x00 0x00 0x00 0x00 -+ 0x10000e0 0x0f 0x1f 0x1c 0x0c 0x0f 0x08 0x48 0x98 0x37 0x0a 0x13 0x04 0x11 0x0d 0x00 -+ 0x10000e1 0x0f 0x32 0x2e 0x0b 0x0d 0x05 0x47 0x75 0x37 0x06 0x10 0x03 0x24 0x20 0x00 -+ 0x10000e2 0x0f 0x32 0x2e 0x0b 0x0d 0x05 0x47 0x75 0x37 0x06 0x10 0x03 0x24 0x20 0x00 -+ 0x1000011 -+ 0x1000029>; -+ }; -+ -+ piscreen_ts: piscreen-ts@1 { -+ compatible = "ti,ads7846"; -+ reg = <1>; -+ -+ spi-max-frequency = <2000000>; -+ interrupts = <17 2>; /* high-to-low edge triggered */ -+ interrupt-parent = <&gpio>; -+ pendown-gpio = <&gpio 17 0>; -+ ti,swap-xy; -+ ti,x-plate-ohms = /bits/ 16 <100>; -+ ti,pressure-max = /bits/ 16 <255>; -+ }; -+ }; -+ }; -+ __overrides__ { -+ speed = <&piscreen>,"spi-max-frequency:0"; -+ rotate = <&piscreen>,"rotate:0"; -+ fps = <&piscreen>,"fps:0"; -+ debug = <&piscreen>,"debug:0"; -+ xohms = <&piscreen_ts>,"ti,x-plate-ohms;0"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/pitft28-capacitive-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/pitft28-capacitive-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/pitft28-capacitive-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/pitft28-capacitive-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,88 @@ -+/* -+ * Device Tree overlay for Adafruit PiTFT 2.8" capacitive touch screen -+ * -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709"; -+ -+ fragment@0 { -+ target = <&spi0>; -+ __overlay__ { -+ status = "okay"; -+ -+ spidev@0{ -+ status = "disabled"; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&gpio>; -+ __overlay__ { -+ pitft_pins: pitft_pins { -+ brcm,pins = <24 25>; -+ brcm,function = <0 1>; /* in out */ -+ brcm,pull = <2 0>; /* pullup none */ -+ }; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&spi0>; -+ __overlay__ { -+ /* needed to avoid dtc warning */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ pitft: pitft@0{ -+ compatible = "ilitek,ili9340"; -+ reg = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pitft_pins>; -+ -+ spi-max-frequency = <32000000>; -+ rotate = <90>; -+ fps = <25>; -+ bgr; -+ buswidth = <8>; -+ dc-gpios = <&gpio 25 0>; -+ debug = <0>; -+ }; -+ }; -+ }; -+ -+ fragment@3 { -+ target = <&i2c1>; -+ __overlay__ { -+ /* needed to avoid dtc warning */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ft6236: ft6236@38 { -+ compatible = "focaltech,ft6236"; -+ reg = <0x38>; -+ -+ interrupt-parent = <&gpio>; -+ interrupts = <24 2>; -+ touchscreen-size-x = <240>; -+ touchscreen-size-y = <320>; -+ }; -+ }; -+ }; -+ -+ __overrides__ { -+ speed = <&pitft>,"spi-max-frequency:0"; -+ rotate = <&pitft>,"rotate:0"; -+ fps = <&pitft>,"fps:0"; -+ debug = <&pitft>,"debug:0"; -+ touch-sizex = <&ft6236>,"touchscreen-size-x?"; -+ touch-sizey = <&ft6236>,"touchscreen-size-y?"; -+ touch-invx = <&ft6236>,"touchscreen-inverted-x?"; -+ touch-invy = <&ft6236>,"touchscreen-inverted-y?"; -+ touch-swapxy = <&ft6236>,"touchscreen-swapped-x-y?"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/pitft28-resistive-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/pitft28-resistive-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/pitft28-resistive-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/pitft28-resistive-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,115 @@ -+/* -+ * Device Tree overlay for Adafruit PiTFT 2.8" resistive touch screen -+ * -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709"; -+ -+ fragment@0 { -+ target = <&spi0>; -+ __overlay__ { -+ status = "okay"; -+ -+ spidev@0{ -+ status = "disabled"; -+ }; -+ -+ spidev@1{ -+ status = "disabled"; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&gpio>; -+ __overlay__ { -+ pitft_pins: pitft_pins { -+ brcm,pins = <24 25>; -+ brcm,function = <0 1>; /* in out */ -+ brcm,pull = <2 0>; /* pullup none */ -+ }; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&spi0>; -+ __overlay__ { -+ /* needed to avoid dtc warning */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ pitft: pitft@0{ -+ compatible = "ilitek,ili9340"; -+ reg = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pitft_pins>; -+ -+ spi-max-frequency = <32000000>; -+ rotate = <90>; -+ fps = <25>; -+ bgr; -+ buswidth = <8>; -+ dc-gpios = <&gpio 25 0>; -+ debug = <0>; -+ }; -+ -+ pitft_ts@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "st,stmpe610"; -+ reg = <1>; -+ -+ spi-max-frequency = <500000>; -+ irq-gpio = <&gpio 24 0x2>; /* IRQF_TRIGGER_FALLING */ -+ interrupts = <24 2>; /* high-to-low edge triggered */ -+ interrupt-parent = <&gpio>; -+ interrupt-controller; -+ -+ stmpe_touchscreen { -+ compatible = "st,stmpe-ts"; -+ st,sample-time = <4>; -+ st,mod-12b = <1>; -+ st,ref-sel = <0>; -+ st,adc-freq = <2>; -+ st,ave-ctrl = <3>; -+ st,touch-det-delay = <4>; -+ st,settling = <2>; -+ st,fraction-z = <7>; -+ st,i-drive = <0>; -+ }; -+ -+ stmpe_gpio: stmpe_gpio { -+ #gpio-cells = <2>; -+ compatible = "st,stmpe-gpio"; -+ /* -+ * only GPIO2 is wired/available -+ * and it is wired to the backlight -+ */ -+ st,norequest-mask = <0x7b>; -+ }; -+ }; -+ }; -+ }; -+ -+ fragment@3 { -+ target-path = "/soc"; -+ __overlay__ { -+ backlight { -+ compatible = "gpio-backlight"; -+ gpios = <&stmpe_gpio 2 0>; -+ default-on; -+ }; -+ }; -+ }; -+ -+ __overrides__ { -+ speed = <&pitft>,"spi-max-frequency:0"; -+ rotate = <&pitft>,"rotate:0"; -+ fps = <&pitft>,"fps:0"; -+ debug = <&pitft>,"debug:0"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/pps-gpio-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/pps-gpio-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/pps-gpio-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/pps-gpio-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,34 @@ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2708"; -+ fragment@0 { -+ target-path = "/"; -+ __overlay__ { -+ pps: pps { -+ compatible = "pps-gpio"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pps_pins>; -+ gpios = <&gpio 18 0>; -+ status = "okay"; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&gpio>; -+ __overlay__ { -+ pps_pins: pps_pins { -+ brcm,pins = <18>; -+ brcm,function = <0>; // in -+ brcm,pull = <0>; // off -+ }; -+ }; -+ }; -+ -+ __overrides__ { -+ gpiopin = <&pps>,"gpios:4", -+ <&pps_pins>,"brcm,pins:0"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/pwm-2chan-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/pwm-2chan-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/pwm-2chan-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/pwm-2chan-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,46 @@ -+/dts-v1/; -+/plugin/; -+ -+/* -+This is the 2-channel overlay - only use it if you need both channels. -+ -+Legal pin,function combinations for each channel: -+ PWM0: 12,4(Alt0) 18,2(Alt5) 40,4(Alt0) 52,5(Alt1) -+ PWM1: 13,4(Alt0) 19,2(Alt5) 41,4(Alt0) 45,4(Alt0) 53,5(Alt1) -+ -+N.B.: -+ 1) Pin 18 is the only one available on all platforms, and -+ it is the one used by the I2S audio interface. -+ Pins 12 and 13 might be better choices on an A+, B+ or Pi2. -+ 2) The onboard analogue audio output uses both PWM channels. -+ 3) So be careful mixing audio and PWM. -+*/ -+ -+/ { -+ fragment@0 { -+ target = <&gpio>; -+ __overlay__ { -+ pwm_pins: pwm_pins { -+ brcm,pins = <18 19>; -+ brcm,function = <2 2>; /* Alt5 */ -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&pwm>; -+ __overlay__ { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pwm_pins>; -+ status = "okay"; -+ }; -+ }; -+ -+ __overrides__ { -+ pin = <&pwm_pins>,"brcm,pins:0"; -+ pin2 = <&pwm_pins>,"brcm,pins:4"; -+ func = <&pwm_pins>,"brcm,function:0"; -+ func2 = <&pwm_pins>,"brcm,function:4"; -+ clock = <&clk_pwm>,"clock-frequency:0"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/pwm-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/pwm-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/pwm-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/pwm-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,42 @@ -+/dts-v1/; -+/plugin/; -+ -+/* -+Legal pin,function combinations for each channel: -+ PWM0: 12,4(Alt0) 18,2(Alt5) 40,4(Alt0) 52,5(Alt1) -+ PWM1: 13,4(Alt0) 19,2(Alt5) 41,4(Alt0) 45,4(Alt0) 53,5(Alt1) -+ -+N.B.: -+ 1) Pin 18 is the only one available on all platforms, and -+ it is the one used by the I2S audio interface. -+ Pins 12 and 13 might be better choices on an A+, B+ or Pi2. -+ 2) The onboard analogue audio output uses both PWM channels. -+ 3) So be careful mixing audio and PWM. -+*/ -+ -+/ { -+ fragment@0 { -+ target = <&gpio>; -+ __overlay__ { -+ pwm_pins: pwm_pins { -+ brcm,pins = <18>; -+ brcm,function = <2>; /* Alt5 */ -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&pwm>; -+ __overlay__ { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pwm_pins>; -+ status = "okay"; -+ }; -+ }; -+ -+ __overrides__ { -+ pin = <&pwm_pins>,"brcm,pins:0"; -+ func = <&pwm_pins>,"brcm,function:0"; -+ clock = <&clk_pwm>,"clock-frequency:0"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/raspidac3-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/raspidac3-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/raspidac3-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/raspidac3-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,45 @@ -+// Definitions for RaspiDACv3 -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2708"; -+ -+ fragment@0 { -+ target = <&sound>; -+ __overlay__ { -+ compatible = "jg,raspidacv3"; -+ i2s-controller = <&i2s>; -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&i2s>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&i2c1>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ pcm5122@4c { -+ #sound-dai-cells = <0>; -+ compatible = "ti,pcm5122"; -+ reg = <0x4c>; -+ status = "okay"; -+ }; -+ -+ tpa6130a2: tpa6130a2@60 { -+ compatible = "ti,tpa6130a2"; -+ reg = <0x60>; -+ status = "okay"; -+ }; -+ }; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/README linux-rpi/arch/arm/boot/dts/overlays/README ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/README 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/README 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,742 @@ -+Introduction -+============ -+ -+This directory contains Device Tree overlays. Device Tree makes it possible -+to support many hardware configurations with a single kernel and without the -+need to explicitly load or blacklist kernel modules. Note that this isn't a -+"pure" Device Tree configuration (c.f. MACH_BCM2835) - some on-board devices -+are still configured by the board support code, but the intention is to -+eventually reach that goal. -+ -+On Raspberry Pi, Device Tree usage is controlled from /boot/config.txt. By -+default, the Raspberry Pi kernel boots with device tree enabled. You can -+completely disable DT usage (for now) by adding: -+ -+ device_tree= -+ -+to your config.txt, which should cause your Pi to revert to the old way of -+doing things after a reboot. -+ -+In /boot you will find a .dtb for each base platform. This describes the -+hardware that is part of the Raspberry Pi board. The loader (start.elf and its -+siblings) selects the .dtb file appropriate for the platform by name, and reads -+it into memory. At this point, all of the optional interfaces (i2c, i2s, spi) -+are disabled, but they can be enabled using Device Tree parameters: -+ -+ dtparam=i2c=on,i2s=on,spi=on -+ -+However, this shouldn't be necessary in many use cases because loading an -+overlay that requires one of those interfaces will cause it to be enabled -+automatically, and it is advisable to only enable interfaces if they are -+needed. -+ -+Configuring additional, optional hardware is done using Device Tree overlays -+(see below). -+ -+raspi-config -+============ -+ -+The Advanced Options section of the raspi-config utility can enable and disable -+Device Tree use, as well as toggling the I2C and SPI interfaces. Note that it -+is possible to both enable an interface and blacklist the driver, if for some -+reason you should want to defer the loading. -+ -+Modules -+======= -+ -+As well as describing the hardware, Device Tree also gives enough information -+to allow suitable driver modules to be located and loaded, with the corollary -+that unneeded modules are not loaded. As a result it should be possible to -+remove lines from /etc/modules, and /etc/modprobe.d/raspi-blacklist.conf can -+have its contents deleted (or commented out). -+ -+Using Overlays -+============== -+ -+Overlays are loaded using the "dtoverlay" directive. As an example, consider the -+popular lirc-rpi module, the Linux Infrared Remote Control driver. In the -+pre-DT world this would be loaded from /etc/modules, with an explicit -+"modprobe lirc-rpi" command, or programmatically by lircd. With DT enabled, -+this becomes a line in config.txt: -+ -+ dtoverlay=lirc-rpi -+ -+This causes the file /boot/overlays/lirc-rpi-overlay.dtb to be loaded. By -+default it will use GPIOs 17 (out) and 18 (in), but this can be modified using -+DT parameters: -+ -+ dtoverlay=lirc-rpi,gpio_out_pin=17,gpio_in_pin=13 -+ -+Parameters always have default values, although in some cases (e.g. "w1-gpio") -+it is necessary to provided multiple overlays in order to get the desired -+behaviour. See the list of overlays below for a description of the parameters -+and their defaults. -+ -+The Overlay and Parameter Reference -+=================================== -+ -+N.B. When editing this file, please preserve the indentation levels to make it -+simple to parse programmatically. NO HARD TABS. -+ -+ -+Name: -+Info: Configures the base Raspberry Pi hardware -+Load: -+Params: -+ audio Set to "on" to enable the onboard ALSA audio -+ interface (default "off") -+ -+ i2c_arm Set to "on" to enable the ARM's i2c interface -+ (default "off") -+ -+ i2c_vc Set to "on" to enable the i2c interface -+ usually reserved for the VideoCore processor -+ (default "off") -+ -+ i2c An alias for i2c_arm -+ -+ i2c_arm_baudrate Set the baudrate of the ARM's i2c interface -+ (default "100000") -+ -+ i2c_vc_baudrate Set the baudrate of the VideoCore i2c interface -+ (default "100000") -+ -+ i2c_baudrate An alias for i2c_arm_baudrate -+ -+ i2s Set to "on" to enable the i2s interface -+ (default "off") -+ -+ spi Set to "on" to enable the spi interfaces -+ (default "off") -+ -+ random Set to "on" to enable the hardware random -+ number generator (default "off") -+ -+ uart0 Set to "off" to disable uart0 (default "on") -+ -+ watchdog Set to "on" to enable the hardware watchdog -+ (default "off") -+ -+ act_led_trigger Choose which activity the LED tracks. -+ Use "heartbeat" for a nice load indicator. -+ (default "mmc") -+ -+ act_led_activelow Set to "on" to invert the sense of the LED -+ (default "off") -+ -+ act_led_gpio Set which GPIO to use for the activity LED -+ (in case you want to connect it to an external -+ device) -+ (default "16" on a non-Plus board, "47" on a -+ Plus or Pi 2) -+ -+ pwr_led_trigger -+ pwr_led_activelow -+ pwr_led_gpio -+ As for act_led_*, but using the PWR LED. -+ Not available on Model A/B boards. -+ -+ N.B. It is recommended to only enable those interfaces that are needed. -+ Leaving all interfaces enabled can lead to unwanted behaviour (i2c_vc -+ interfering with Pi Camera, I2S and SPI hogging GPIO pins, etc.) -+ Note also that i2c, i2c_arm and i2c_vc are aliases for the physical -+ interfaces i2c0 and i2c1. Use of the numeric variants is still possible -+ but deprecated because the ARM/VC assignments differ between board -+ revisions. The same board-specific mapping applies to i2c_baudrate, -+ and the other i2c baudrate parameters. -+ -+ -+Name: ads7846 -+Info: ADS7846 Touch controller -+Load: dtoverlay=ads7846,= -+Params: cs SPI bus Chip Select (default 1) -+ speed SPI bus speed (default 2MHz, max 3.25MHz) -+ penirq GPIO used for PENIRQ. REQUIRED -+ penirq_pull Set GPIO pull (default 0=none, 2=pullup) -+ swapxy Swap x and y axis -+ xmin Minimum value on the X axis (default 0) -+ ymin Minimum value on the Y axis (default 0) -+ xmax Maximum value on the X axis (default 4095) -+ ymax Maximum value on the Y axis (default 4095) -+ pmin Minimum reported pressure value (default 0) -+ pmax Maximum reported pressure value (default 65535) -+ xohms Touchpanel sensitivity (X-plate resistance) -+ (default 400) -+ -+ penirq is required and usually xohms (60-100) has to be set as well. -+ Apart from that, pmax (255) and swapxy are also common. -+ The rest of the calibration can be done with xinput-calibrator. -+ See: github.com/notro/fbtft/wiki/FBTFT-on-Raspian -+ Device Tree binding document: -+ www.kernel.org/doc/Documentation/devicetree/bindings/input/ads7846.txt -+ -+ -+Name: at86rf233 -+Info: Configures the Atmel AT86RF233 802.15.4 low-power WPAN transceiver, -+ connected to spi0.0 -+Load: dtoverlay=at86rf233,= -+Params: interrupt GPIO used for INT (default 23) -+ reset GPIO used for Reset (default 24) -+ sleep GPIO used for Sleep (default 25) -+ speed SPI bus speed in Hz (default 6000000) -+ trim Fine tuning of the internal capacitance -+ arrays (0=+0pF, 15=+4.5pF, default 15) -+ -+ -+Name: bmp085_i2c-sensor -+Info: Configures the BMP085/BMP180 digital barometric pressure and temperature -+ sensors from Bosch Sensortec -+Load: dtoverlay=bmp085_i2c-sensor -+Params: -+ -+ -+Name: dht11 -+Info: Overlay for the DHT11/DHT21/DHT22 humidity/temperature sensors -+ Also sometimes found with the part number(s) AM230x. -+Load: dtoverlay=dht11,= -+Params: gpiopin GPIO connected to the sensor's DATA output. -+ (default 4) -+ -+ -+[ The ds1307-rtc overlay has been deleted. See i2c-rtc. ] -+ -+ -+Name: enc28j60 -+Info: Overlay for the Microchip ENC28J60 Ethernet Controller (SPI) -+Load: dtoverlay=enc28j60,= -+Params: int_pin GPIO used for INT (default 25) -+ -+ speed SPI bus speed (default 12000000) -+ -+ -+Name: gpio-ir -+Info: Use GPIO pin as rc-core style infrared receiver input. The rc-core- -+ based gpio_ir_recv driver maps received keys directly to a -+ /dev/input/event* device, all decoding is done by the kernel - LIRC is -+ not required! The key mapping and other decoding parameters can be -+ configured by "ir-keytable" tool. -+Load: dtoverlay=gpio-ir,= -+Params: gpio_pin Input pin number. Default is 18. -+ -+ gpio_pull Desired pull-up/down state (off, down, up) -+ Default is "down". -+ -+ rc-map-name Default rc keymap (can also be changed by -+ ir-keytable), defaults to "rc-rc6-mce" -+ -+ -+Name: gpio-poweroff -+Info: Drives a GPIO high or low on reboot -+Load: dtoverlay=gpio-poweroff,= -+Params: gpiopin GPIO for signalling (default 26) -+ -+ active_low Set if the power control device requires a -+ high->low transition to trigger a power-down. -+ Note that this will require the support of a -+ custom dt-blob.bin to prevent a power-down -+ during the boot process, and that a reboot -+ will also cause the pin to go low. -+ -+ -+Name: hifiberry-amp -+Info: Configures the HifiBerry Amp and Amp+ audio cards -+Load: dtoverlay=hifiberry-amp -+Params: -+ -+ -+Name: hifiberry-dac -+Info: Configures the HifiBerry DAC audio card -+Load: dtoverlay=hifiberry-dac -+Params: -+ -+ -+Name: hifiberry-dacplus -+Info: Configures the HifiBerry DAC+ audio card -+Load: dtoverlay=hifiberry-dacplus -+Params: -+ -+ -+Name: hifiberry-digi -+Info: Configures the HifiBerry Digi audio card -+Load: dtoverlay=hifiberry-digi -+Params: -+ -+ -+Name: hy28a -+Info: HY28A - 2.8" TFT LCD Display Module by HAOYU Electronics -+ Default values match Texy's display shield -+Load: dtoverlay=hy28a,= -+Params: speed Display SPI bus speed -+ -+ rotate Display rotation {0,90,180,270} -+ -+ fps Delay between frame updates -+ -+ debug Debug output level {0-7} -+ -+ xohms Touchpanel sensitivity (X-plate resistance) -+ -+ resetgpio GPIO used to reset controller -+ -+ ledgpio GPIO used to control backlight -+ -+ -+Name: hy28b -+Info: HY28B - 2.8" TFT LCD Display Module by HAOYU Electronics -+ Default values match Texy's display shield -+Load: dtoverlay=hy28b,= -+Params: speed Display SPI bus speed -+ -+ rotate Display rotation {0,90,180,270} -+ -+ fps Delay between frame updates -+ -+ debug Debug output level {0-7} -+ -+ xohms Touchpanel sensitivity (X-plate resistance) -+ -+ resetgpio GPIO used to reset controller -+ -+ ledgpio GPIO used to control backlight -+ -+ -+Name: i2c-gpio -+Info: Adds support for software i2c controller on gpio pins -+Load: dtoverlay=i2c-gpio,= -+Params: i2c_gpio_sda GPIO used for I2C data (default "23") -+ -+ i2c_gpio_scl GPIO used for I2C clock (default "24") -+ -+ i2c_gpio_delay_us Clock delay in microseconds -+ (default "2" = ~100kHz) -+ -+ -+Name: i2c-rtc -+Info: Adds support for a number of I2C Real Time Clock devices -+Load: dtoverlay=i2c-rtc,= -+Params: ds1307 Select the DS1307 device -+ -+ ds3231 Select the DS3231 device -+ -+ mcp7941x Select the MCP7941x device -+ -+ pcf2127 Select the PCF2127 device -+ -+ pcf8523 Select the PCF8523 device -+ -+ pcf8563 Select the PCF8563 device -+ -+ -+Name: i2s-mmap -+Info: Enables mmap support in the bcm2708-i2s driver -+Load: dtoverlay=i2s-mmap -+Params: -+ -+ -+Name: iqaudio-dac -+Info: Configures the IQaudio DAC audio card -+Load: dtoverlay=iqaudio-dac -+Params: -+ -+ -+Name: iqaudio-dacplus -+Info: Configures the IQaudio DAC+ audio card -+Load: dtoverlay=iqaudio-dacplus -+Params: -+ -+ -+Name: lirc-rpi -+Info: Configures lirc-rpi (Linux Infrared Remote Control for Raspberry Pi) -+ Consult the module documentation for more details. -+Load: dtoverlay=lirc-rpi,= -+Params: gpio_out_pin GPIO for output (default "17") -+ -+ gpio_in_pin GPIO for input (default "18") -+ -+ gpio_in_pull Pull up/down/off on the input pin -+ (default "down") -+ -+ sense Override the IR receive auto-detection logic: -+ "0" = force active-high -+ "1" = force active-low -+ "-1" = use auto-detection -+ (default "-1") -+ -+ softcarrier Turn the software carrier "on" or "off" -+ (default "on") -+ -+ invert "on" = invert the output pin (default "off") -+ -+ debug "on" = enable additional debug messages -+ (default "off") -+ -+ -+Name: mcp2515-can0 -+Info: Configures the MCP2515 CAN controller on spi0.0 -+Load: dtoverlay=mcp2515-can0,= -+Params: oscillator Clock frequency for the CAN controller (Hz) -+ -+ spimaxfrequency Maximum SPI frequence (Hz) -+ -+ interrupt GPIO for interrupt signal -+ -+ -+Name: mcp2515-can1 -+Info: Configures the MCP2515 CAN controller on spi0.1 -+Load: dtoverlay=mcp2515-can1,= -+Params: oscillator Clock frequency for the CAN controller (Hz) -+ -+ spimaxfrequency Maximum SPI frequence (Hz) -+ -+ interrupt GPIO for interrupt signal -+ -+ -+Name: mmc -+Info: Selects the bcm2835-mmc SD/MMC driver, optionally with overclock -+Load: dtoverlay=mmc,= -+Params: overclock_50 Clock (in MHz) to use when the MMC framework -+ requests 50MHz -+ force_pio Disable DMA support -+ -+ -+Name: mz61581 -+Info: MZ61581 display by Tontec -+Load: dtoverlay=mz61581,= -+Params: speed Display SPI bus speed -+ -+ rotate Display rotation {0,90,180,270} -+ -+ fps Delay between frame updates -+ -+ txbuflen Transmit buffer length (default 32768) -+ -+ debug Debug output level {0-7} -+ -+ xohms Touchpanel sensitivity (X-plate resistance) -+ -+ -+[ The pcf2127-rtc overlay has been deleted. See i2c-rtc. ] -+ -+ -+[ The pcf8523-rtc overlay has been deleted. See i2c-rtc. ] -+ -+ -+[ The pcf8563-rtc overlay has been deleted. See i2c-rtc. ] -+ -+ -+Name: piscreen -+Info: PiScreen display by OzzMaker.com -+Load: dtoverlay=piscreen,= -+Params: speed Display SPI bus speed -+ -+ rotate Display rotation {0,90,180,270} -+ -+ fps Delay between frame updates -+ -+ debug Debug output level {0-7} -+ -+ xohms Touchpanel sensitivity (X-plate resistance) -+ -+ -+Name: piscreen2r -+Info: PiScreen 2 with resistive TP display by OzzMaker.com -+Load: dtoverlay=piscreen2r,= -+Params: speed Display SPI bus speed -+ -+ rotate Display rotation {0,90,180,270} -+ -+ fps Delay between frame updates -+ -+ debug Debug output level {0-7} -+ -+ xohms Touchpanel sensitivity (X-plate resistance) -+ -+ -+Name: pitft28-capacitive -+Info: Adafruit PiTFT 2.8" capacitive touch screen -+Load: dtoverlay=pitft28-capacitive,= -+Params: speed Display SPI bus speed -+ -+ rotate Display rotation {0,90,180,270} -+ -+ fps Delay between frame updates -+ -+ debug Debug output level {0-7} -+ -+ touch-sizex Touchscreen size x (default 240) -+ -+ touch-sizey Touchscreen size y (default 320) -+ -+ touch-invx Touchscreen inverted x axis -+ -+ touch-invy Touchscreen inverted y axis -+ -+ touch-swapxy Touchscreen swapped x y axis -+ -+ -+Name: pitft28-resistive -+Info: Adafruit PiTFT 2.8" resistive touch screen -+Load: dtoverlay=pitft28-resistive,= -+Params: speed Display SPI bus speed -+ -+ rotate Display rotation {0,90,180,270} -+ -+ fps Delay between frame updates -+ -+ debug Debug output level {0-7} -+ -+ -+Name: pps-gpio -+Info: Configures the pps-gpio (pulse-per-second time signal via GPIO). -+Load: dtoverlay=pps-gpio,= -+Params: gpiopin Input GPIO (default "18") -+ -+ -+Name: pwm -+Info: Configures a single PWM channel -+ Legal pin,function combinations for each channel: -+ PWM0: 12,4(Alt0) 18,2(Alt5) 40,4(Alt0) 52,5(Alt1) -+ PWM1: 13,4(Alt0) 19,2(Alt5) 41,4(Alt0) 45,4(Alt0) 53,5(Alt1) -+ N.B.: -+ 1) Pin 18 is the only one available on all platforms, and -+ it is the one used by the I2S audio interface. -+ Pins 12 and 13 might be better choices on an A+, B+ or Pi2. -+ 2) The onboard analogue audio output uses both PWM channels. -+ 3) So be careful mixing audio and PWM. -+ 4) Currently the clock must have been enabled and configured -+ by other means. -+Load: dtoverlay=pwm,= -+Params: pin Output pin (default 18) - see table -+ func Pin function (default 2 = Alt5) - see above -+ clock PWM clock frequency (informational) -+ -+ -+Name: pwm-2chan -+Info: Configures both PWM channels -+ Legal pin,function combinations for each channel: -+ PWM0: 12,4(Alt0) 18,2(Alt5) 40,4(Alt0) 52,5(Alt1) -+ PWM1: 13,4(Alt0) 19,2(Alt5) 41,4(Alt0) 45,4(Alt0) 53,5(Alt1) -+ N.B.: -+ 1) Pin 18 is the only one available on all platforms, and -+ it is the one used by the I2S audio interface. -+ Pins 12 and 13 might be better choices on an A+, B+ or Pi2. -+ 2) The onboard analogue audio output uses both PWM channels. -+ 3) So be careful mixing audio and PWM. -+ 4) Currently the clock must have been enabled and configured -+ by other means. -+Load: dtoverlay=pwm-2chan,= -+Params: pin Output pin (default 18) - see table -+ pin2 Output pin for other channel (default 19) -+ func Pin function (default 2 = Alt5) - see above -+ func2 Function for pin2 (default 2 = Alt5) -+ clock PWM clock frequency (informational) -+ -+ -+Name: raspidac3 -+Info: Configures the RaspiDAV Rev.3x audio card -+Load: dtoverlay=raspidac3 -+Params: -+ -+ -+Name: rpi-backlight -+Info: Raspberry Pi official display backlight driver -+Load: dtoverlay=rpi-backlight -+Params: -+ -+ -+Name: rpi-dac -+Info: Configures the RPi DAC audio card -+Load: dtoverlay=rpi-dac -+Params: -+ -+ -+Name: rpi-display -+Info: RPi-Display - 2.8" Touch Display by Watterott -+Load: dtoverlay=rpi-display,= -+Params: speed Display SPI bus speed -+ -+ rotate Display rotation {0,90,180,270} -+ -+ fps Delay between frame updates -+ -+ debug Debug output level {0-7} -+ -+ xohms Touchpanel sensitivity (X-plate resistance) -+ -+ -+Name: rpi-ft5406 -+Info: Official Raspberry Pi display touchscreen -+Load: dtoverlay=rpi-ft5406 -+Params: -+ -+ -+Name: rpi-proto -+Info: Configures the RPi Proto audio card -+Load: dtoverlay=rpi-proto -+Params: -+ -+ -+Name: rpi-sense -+Info: Raspberry Pi Sense HAT -+Load: dtoverlay=rpi-sense -+Params: -+ -+ -+Name: sdhost -+Info: Selects the bcm2835-sdhost SD/MMC driver, optionally with overclock -+Load: dtoverlay=sdhost,= -+Params: overclock_50 Clock (in MHz) to use when the MMC framework -+ requests 50MHz -+ -+ force_pio Disable DMA support (default off) -+ -+ pio_limit Number of blocks above which to use DMA -+ (default 1) -+ -+ debug Enable debug output (default off) -+ -+ -+Name: sdio -+Info: Selects the bcm2835-sdhost SD/MMC driver, optionally with overclock, -+ and enables SDIO via GPIOs 22-27. -+Load: dtoverlay=sdio,= -+Params: overclock_50 Clock (in MHz) to use when the MMC framework -+ requests 50MHz -+ -+ force_pio Disable DMA support (default off) -+ -+ pio_limit Number of blocks above which to use DMA -+ (default 1) -+ -+ debug Enable debug output (default off) -+ -+ poll_once Disable SDIO-device polling every second -+ (default on: polling once at boot-time) -+ -+ -+Name: smi -+Info: Enables the Secondary Memory Interface peripheral. Uses GPIOs 2-25! -+Load: dtoverlay=smi -+Params: -+ -+ -+Name: smi-dev -+Info: Enables the userspace interface for the SMI driver -+Load: dtoverlay=smi-dev -+Params: -+ -+ -+Name: smi-nand -+Info: Enables access to NAND flash via the SMI interface -+Load: dtoverlay=smi-nand -+Params: -+ -+ -+Name: spi-bcm2708 -+Info: Selects the bcm2708-spi SPI driver -+Load: dtoverlay=spi-bcm2708 -+Params: -+ -+ -+Name: spi-bcm2835 -+Info: Selects the bcm2835-spi SPI driver -+Load: dtoverlay=spi-bcm2835 -+Params: -+ -+ -+Name: spi-dma -+Info: enables dma modes for spi-bcm2835 -+Load: dtoverlay=spi-dma -+Params: -+ -+ -+Name: tinylcd35 -+Info: 3.5" Color TFT Display by www.tinylcd.com -+ Options: Touch, RTC, keypad -+Load: dtoverlay=tinylcd35,= -+Params: speed Display SPI bus speed -+ -+ rotate Display rotation {0,90,180,270} -+ -+ fps Delay between frame updates -+ -+ debug Debug output level {0-7} -+ -+ touch Enable touch panel -+ -+ touchgpio Touch controller IRQ GPIO -+ -+ xohms Touchpanel: Resistance of X-plate in ohms -+ -+ rtc-pcf PCF8563 Real Time Clock -+ -+ rtc-ds DS1307 Real Time Clock -+ -+ keypad Enable keypad -+ -+ Examples: -+ Display with touchpanel, PCF8563 RTC and keypad: -+ dtoverlay=tinylcd35,touch,rtc-pcf,keypad -+ Old touch display: -+ dtoverlay=tinylcd35,touch,touchgpio=3 -+ -+ -+Name: uart1 -+Info: Enable uart1 in place of uart0 -+Load: dtoverlay=uart1,= -+Params: txd1_pin GPIO pin for TXD1 (14, 32 or 40 - default 14) -+ -+ rxd1_pin GPIO pin for RXD1 (15, 33 or 41 - default 15) -+ -+ -+Name: vga666 -+Info: Overlay for the Fen Logic VGA666 board -+ This uses GPIOs 2-21 (so no I2C), and activates the output 2-3 seconds -+ after the kernel has started. -+Load: dtoverlay=vga666 -+Params: -+ -+ -+Name: w1-gpio -+Info: Configures the w1-gpio Onewire interface module. -+ Use this overlay if you *don't* need a GPIO to drive an external pullup. -+Load: dtoverlay=w1-gpio,= -+Params: gpiopin GPIO for I/O (default "4") -+ -+ pullup Non-zero, "on", or "y" to enable the parasitic -+ power (2-wire, power-on-data) feature -+ -+ -+Name: w1-gpio-pullup -+Info: Configures the w1-gpio Onewire interface module. -+ Use this overlay if you *do* need a GPIO to drive an external pullup. -+Load: dtoverlay=w1-gpio-pullup,= -+Params: gpiopin GPIO for I/O (default "4") -+ -+ pullup Non-zero, "on", or "y" to enable the parasitic -+ power (2-wire, power-on-data) feature -+ -+ extpullup GPIO for external pullup (default "5") -+ -+ -+Troubleshooting -+=============== -+ -+If you are experiencing problems that you think are DT-related, enable DT -+diagnostic output by adding this to /boot/config.txt: -+ -+ dtdebug=on -+ -+and rebooting. Then run: -+ -+ sudo vcdbg log msg -+ -+and look for relevant messages. -+ -+Further reading -+=============== -+ -+This is only meant to be a quick introduction to the subject of Device Tree on -+Raspberry Pi. There is a more complete explanation here: -+ -+http://www.raspberrypi.org/documentation/configuration/device-tree.md -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/rpi-backlight-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/rpi-backlight-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/rpi-backlight-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/rpi-backlight-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,21 @@ -+/* -+ * Devicetree overlay for mailbox-driven Raspberry Pi DSI Display -+ * backlight controller -+ */ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2708"; -+ -+ fragment@0 { -+ target-path = "/"; -+ __overlay__ { -+ rpi_backlight: rpi_backlight { -+ compatible = "raspberrypi,rpi-backlight"; -+ firmware = <&firmware>; -+ status = "okay"; -+ }; -+ }; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/rpi-dac-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/rpi-dac-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/rpi-dac-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/rpi-dac-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,34 @@ -+// Definitions for RPi DAC -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2708"; -+ -+ fragment@0 { -+ target = <&sound>; -+ __overlay__ { -+ compatible = "rpi,rpi-dac"; -+ i2s-controller = <&i2s>; -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&i2s>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@2 { -+ target-path = "/"; -+ __overlay__ { -+ pcm1794a-codec { -+ #sound-dai-cells = <0>; -+ compatible = "ti,pcm1794a"; -+ status = "okay"; -+ }; -+ }; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/rpi-display-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/rpi-display-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/rpi-display-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/rpi-display-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,82 @@ -+/* -+ * Device Tree overlay for rpi-display by Watterott -+ * -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709"; -+ -+ fragment@0 { -+ target = <&spi0>; -+ __overlay__ { -+ status = "okay"; -+ -+ spidev@0{ -+ status = "disabled"; -+ }; -+ -+ spidev@1{ -+ status = "disabled"; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&gpio>; -+ __overlay__ { -+ rpi_display_pins: rpi_display_pins { -+ brcm,pins = <18 23 24 25>; -+ brcm,function = <1 1 1 0>; /* out out out in */ -+ brcm,pull = <0 0 0 2>; /* - - - up */ -+ }; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&spi0>; -+ __overlay__ { -+ /* needed to avoid dtc warning */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ rpidisplay: rpi-display@0{ -+ compatible = "ilitek,ili9341"; -+ reg = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&rpi_display_pins>; -+ -+ spi-max-frequency = <32000000>; -+ rotate = <270>; -+ bgr; -+ fps = <30>; -+ buswidth = <8>; -+ reset-gpios = <&gpio 23 0>; -+ dc-gpios = <&gpio 24 0>; -+ led-gpios = <&gpio 18 1>; -+ debug = <0>; -+ }; -+ -+ rpidisplay_ts: rpi-display-ts@1 { -+ compatible = "ti,ads7846"; -+ reg = <1>; -+ -+ spi-max-frequency = <2000000>; -+ interrupts = <25 2>; /* high-to-low edge triggered */ -+ interrupt-parent = <&gpio>; -+ pendown-gpio = <&gpio 25 0>; -+ ti,x-plate-ohms = /bits/ 16 <60>; -+ ti,pressure-max = /bits/ 16 <255>; -+ }; -+ }; -+ }; -+ __overrides__ { -+ speed = <&rpidisplay>,"spi-max-frequency:0"; -+ rotate = <&rpidisplay>,"rotate:0"; -+ fps = <&rpidisplay>,"fps:0"; -+ debug = <&rpidisplay>,"debug:0"; -+ xohms = <&rpidisplay_ts>,"ti,x-plate-ohms;0"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,17 @@ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2708"; -+ -+ fragment@0 { -+ target-path = "/"; -+ __overlay__ { -+ rpi_ft5406: rpi_ft5406 { -+ compatible = "rpi,rpi-ft5406"; -+ firmware = <&firmware>; -+ status = "okay"; -+ }; -+ }; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/rpi-proto-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/rpi-proto-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/rpi-proto-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/rpi-proto-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,39 @@ -+// Definitions for Rpi-Proto -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2708"; -+ -+ fragment@0 { -+ target = <&sound>; -+ __overlay__ { -+ compatible = "rpi,rpi-proto"; -+ i2s-controller = <&i2s>; -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&i2s>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&i2c1>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ wm8731@1a { -+ #sound-dai-cells = <0>; -+ compatible = "wlf,wm8731"; -+ reg = <0x1a>; -+ status = "okay"; -+ }; -+ }; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/rpi-sense-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/rpi-sense-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/rpi-sense-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/rpi-sense-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,47 @@ -+// rpi-sense HAT -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2708", "brcm,bcm2709"; -+ -+ fragment@0 { -+ target = <&i2c1>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ rpi-sense@46 { -+ compatible = "rpi,rpi-sense"; -+ reg = <0x46>; -+ keys-int-gpios = <&gpio 23 1>; -+ status = "okay"; -+ }; -+ -+ lsm9ds1-magn@1c { -+ compatible = "st,lsm9ds1-magn"; -+ reg = <0x1c>; -+ status = "okay"; -+ }; -+ -+ lsm9ds1-accel6a { -+ compatible = "st,lsm9ds1-accel"; -+ reg = <0x6a>; -+ status = "okay"; -+ }; -+ -+ lps25h-press@5c { -+ compatible = "st,lps25h-press"; -+ reg = <0x5c>; -+ status = "okay"; -+ }; -+ -+ hts221-humid@5f { -+ compatible = "st,hts221-humid"; -+ reg = <0x5f>; -+ status = "okay"; -+ }; -+ }; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/sdhost-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/sdhost-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/sdhost-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/sdhost-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,56 @@ -+/dts-v1/; -+/plugin/; -+ -+/{ -+ compatible = "brcm,bcm2708"; -+ -+ fragment@0 { -+ target = <&soc>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ sdhost: sdhost@7e202000 { -+ compatible = "brcm,bcm2835-sdhost"; -+ reg = <0x7e202000 0x100>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdhost_pins>; -+ interrupts = <2 24>; -+ clocks = <&clk_core>; -+ dmas = <&dma 13>, -+ <&dma 13>; -+ dma-names = "tx", "rx"; -+ brcm,delay-after-stop = <0>; -+ brcm,overclock-50 = <0>; -+ brcm,pio-limit = <1>; -+ status = "okay"; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&gpio>; -+ __overlay__ { -+ sdhost_pins: sdhost_pins { -+ brcm,pins = <48 49 50 51 52 53>; -+ brcm,function = <4>; /* alt0 */ -+ }; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&mmc>; -+ __overlay__ { -+ /* Find a way to disable the other driver */ -+ compatible = ""; -+ status = "disabled"; -+ }; -+ }; -+ -+ __overrides__ { -+ overclock_50 = <&sdhost>,"brcm,overclock-50:0"; -+ force_pio = <&sdhost>,"brcm,force-pio?"; -+ pio_limit = <&sdhost>,"brcm,pio-limit:0"; -+ debug = <&sdhost>,"brcm,debug?"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/sdio-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/sdio-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/sdio-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/sdio-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,33 @@ -+/* Enable SDIO from MMC interface via GPIOs 22-27. Includes sdhost overlay. */ -+ -+/include/ "sdhost-overlay.dts" -+ -+/{ -+ compatible = "brcm,bcm2708"; -+ -+ fragment@3 { -+ target = <&mmc>; -+ sdio_mmc: __overlay__ { -+ compatible = "brcm,bcm2835-mmc"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdio_pins>; -+ non-removable; -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@4 { -+ target = <&gpio>; -+ __overlay__ { -+ sdio_pins: sdio_pins { -+ brcm,pins = <22 23 24 25 26 27>; -+ brcm,function = <7 7 7 7 7 7>; /* ALT3 = SD1 */ -+ brcm,pull = <0 2 2 2 2 2>; -+ }; -+ }; -+ }; -+ -+ __overrides__ { -+ poll_once = <&sdio_mmc>,"non-removable?"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/smi-dev-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/smi-dev-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/smi-dev-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/smi-dev-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,18 @@ -+// Description: Overlay to enable character device interface for SMI. -+// Author: Luke Wren -+ -+/dts-v1/; -+/plugin/; -+ -+/{ -+ fragment@0 { -+ target = <&soc>; -+ __overlay__ { -+ smi_dev { -+ compatible = "brcm,bcm2835-smi-dev"; -+ smi_handle = <&smi>; -+ status = "okay"; -+ }; -+ }; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/smi-nand-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/smi-nand-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/smi-nand-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/smi-nand-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,69 @@ -+// Description: Overlay to enable NAND flash through -+// the secondary memory interface -+// Author: Luke Wren -+ -+/dts-v1/; -+/plugin/; -+ -+/{ -+ compatible = "brcm,bcm2708"; -+ -+ fragment@0 { -+ target = <&smi>; -+ __overlay__ { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&smi_pins>; -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&soc>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ nand: flash@0 { -+ compatible = "brcm,bcm2835-smi-nand"; -+ smi_handle = <&smi>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ status = "okay"; -+ -+ partition@0 { -+ label = "stage2"; -+ // 128k -+ reg = <0 0x20000>; -+ read-only; -+ }; -+ partition@1 { -+ label = "firmware"; -+ // 16M -+ reg = <0x20000 0x1000000>; -+ read-only; -+ }; -+ partition@2 { -+ label = "root"; -+ // 2G (will need to use 64 bit for >=4G) -+ reg = <0x1020000 0x80000000>; -+ }; -+ }; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&gpio>; -+ __overlay__ { -+ smi_pins: smi_pins { -+ brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11 -+ 12 13 14 15>; -+ /* Alt 1: SMI */ -+ brcm,function = <5 5 5 5 5 5 5 5 5 5 5 -+ 5 5 5 5 5>; -+ /* /CS, /WE and /OE are pulled high, as they are -+ generally active low signals */ -+ brcm,pull = <2 2 2 2 2 2 2 2 0 0 0 0 0 0 0 0>; -+ }; -+ }; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/smi-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/smi-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/smi-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/smi-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,37 @@ -+// Description: Overlay to enable the secondary memory interface peripheral -+// Author: Luke Wren -+ -+/dts-v1/; -+/plugin/; -+ -+/{ -+ compatible = "brcm,bcm2708"; -+ -+ fragment@0 { -+ target = <&smi>; -+ __overlay__ { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&smi_pins>; -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&gpio>; -+ __overlay__ { -+ smi_pins: smi_pins { -+ /* Don't configure the top two address bits, as -+ these are already used as ID_SD and ID_SC */ -+ brcm,pins = <2 3 4 5 6 7 8 9 10 11 12 13 14 15 -+ 16 17 18 19 20 21 22 23 24 25>; -+ /* Alt 0: SMI */ -+ brcm,function = <5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 -+ 5 5 5 5 5 5 5 5 5>; -+ /* /CS, /WE and /OE are pulled high, as they are -+ generally active low signals */ -+ brcm,pull = <2 2 2 2 2 2 0 0 0 0 0 0 0 0 0 0 0 -+ 0 0 0 0 0 0 0>; -+ }; -+ }; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/spi-bcm2708-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/spi-bcm2708-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/spi-bcm2708-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/spi-bcm2708-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,18 @@ -+/* -+ * Device tree overlay for spi-bcm2835 -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2835", "brcm,bcm2836", "brcm,bcm2708", "brcm,bcm2709"; -+ /* setting up compatiblity to allow loading the spi-bcm2835 driver */ -+ fragment@0 { -+ target = <&spi0>; -+ __overlay__ { -+ status = "okay"; -+ compatible = "brcm,bcm2708-spi"; -+ }; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/spi-bcm2835-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/spi-bcm2835-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/spi-bcm2835-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/spi-bcm2835-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,18 @@ -+/* -+ * Device tree overlay for spi-bcm2835 -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2835", "brcm,bcm2836", "brcm,bcm2708", "brcm,bcm2709"; -+ /* setting up compatiblity to allow loading the spi-bcm2835 driver */ -+ fragment@0 { -+ target = <&spi0>; -+ __overlay__ { -+ status = "okay"; -+ compatible = "brcm,bcm2835-spi"; -+ }; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/spi-dma-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/spi-dma-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/spi-dma-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/spi-dma-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,20 @@ -+/* -+ * Device tree overlay for spi-bcm2835 to allow dma -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2835", "brcm,bcm2836", "brcm,bcm2708", "brcm,bcm2709"; -+ -+ fragment@0 { -+ target = <&spi0>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ dmas = <&dma 6>, <&dma 7>; -+ dma-names = "tx", "rx"; -+ }; -+ }; -+ }; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/tinylcd35-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/tinylcd35-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/tinylcd35-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/tinylcd35-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,216 @@ -+/* -+ * tinylcd35-overlay.dts -+ * -+ * ------------------------------------------------- -+ * www.tinlylcd.com -+ * ------------------------------------------------- -+ * Device---Driver-----BUS GPIO's -+ * display tinylcd35 spi0.0 25 24 18 -+ * touch ads7846 spi0.1 5 -+ * rtc ds1307 i2c1-0068 -+ * rtc pcf8563 i2c1-0051 -+ * keypad gpio-keys --------- 17 22 27 23 28 -+ * -+ * -+ * TinyLCD.com 3.5 inch TFT -+ * -+ * Version 001 -+ * 5/3/2015 -- Noralf Trønnes Initial Device tree framework -+ * 10/3/2015 -- tinylcd@gmail.com added ds1307 support. -+ * -+ */ -+ -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709"; -+ -+ fragment@0 { -+ target = <&spi0>; -+ __overlay__ { -+ status = "okay"; -+ -+ spidev@0{ -+ status = "disabled"; -+ }; -+ -+ spidev@1{ -+ status = "disabled"; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&gpio>; -+ __overlay__ { -+ tinylcd35_pins: tinylcd35_pins { -+ brcm,pins = <25 24 18>; -+ brcm,function = <1>; /* out */ -+ }; -+ tinylcd35_ts_pins: tinylcd35_ts_pins { -+ brcm,pins = <5>; -+ brcm,function = <0>; /* in */ -+ }; -+ keypad_pins: keypad_pins { -+ brcm,pins = <4 17 22 23 27>; -+ brcm,function = <0>; /* in */ -+ brcm,pull = <1>; /* down */ -+ }; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&spi0>; -+ __overlay__ { -+ /* needed to avoid dtc warning */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ tinylcd35: tinylcd35@0{ -+ compatible = "neosec,tinylcd"; -+ reg = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&tinylcd35_pins>, -+ <&tinylcd35_ts_pins>; -+ -+ spi-max-frequency = <48000000>; -+ rotate = <270>; -+ fps = <20>; -+ bgr; -+ buswidth = <8>; -+ reset-gpios = <&gpio 25 0>; -+ dc-gpios = <&gpio 24 0>; -+ led-gpios = <&gpio 18 1>; -+ debug = <0>; -+ -+ init = <0x10000B0 0x80 -+ 0x10000C0 0x0A 0x0A -+ 0x10000C1 0x01 0x01 -+ 0x10000C2 0x33 -+ 0x10000C5 0x00 0x42 0x80 -+ 0x10000B1 0xD0 0x11 -+ 0x10000B4 0x02 -+ 0x10000B6 0x00 0x22 0x3B -+ 0x10000B7 0x07 -+ 0x1000036 0x58 -+ 0x10000F0 0x36 0xA5 0xD3 -+ 0x10000E5 0x80 -+ 0x10000E5 0x01 -+ 0x10000B3 0x00 -+ 0x10000E5 0x00 -+ 0x10000F0 0x36 0xA5 0x53 -+ 0x10000E0 0x00 0x35 0x33 0x00 0x00 0x00 0x00 0x35 0x33 0x00 0x00 0x00 -+ 0x100003A 0x55 -+ 0x1000011 -+ 0x2000001 -+ 0x1000029>; -+ }; -+ -+ tinylcd35_ts: tinylcd35_ts@1 { -+ compatible = "ti,ads7846"; -+ reg = <1>; -+ status = "disabled"; -+ -+ spi-max-frequency = <2000000>; -+ interrupts = <5 2>; /* high-to-low edge triggered */ -+ interrupt-parent = <&gpio>; -+ pendown-gpio = <&gpio 5 0>; -+ ti,x-plate-ohms = /bits/ 16 <100>; -+ ti,pressure-max = /bits/ 16 <255>; -+ }; -+ }; -+ }; -+ -+ /* RTC */ -+ -+ fragment@3 { -+ target = <&i2c1>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ pcf8563: pcf8563@51 { -+ compatible = "nxp,pcf8563"; -+ reg = <0x51>; -+ status = "disabled"; -+ }; -+ }; -+ }; -+ -+ fragment@4 { -+ target = <&i2c1>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ds1307: ds1307@68 { -+ compatible = "maxim,ds1307"; -+ reg = <0x68>; -+ status = "disabled"; -+ }; -+ }; -+ }; -+ -+ /* -+ * Values for input event code is found under the -+ * 'Keys and buttons' heading in include/uapi/linux/input.h -+ */ -+ fragment@5 { -+ target-path = "/soc"; -+ __overlay__ { -+ keypad: keypad { -+ compatible = "gpio-keys"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&keypad_pins>; -+ status = "disabled"; -+ autorepeat; -+ -+ button@17 { -+ label = "GPIO KEY_UP"; -+ linux,code = <103>; -+ gpios = <&gpio 17 0>; -+ }; -+ button@22 { -+ label = "GPIO KEY_DOWN"; -+ linux,code = <108>; -+ gpios = <&gpio 22 0>; -+ }; -+ button@27 { -+ label = "GPIO KEY_LEFT"; -+ linux,code = <105>; -+ gpios = <&gpio 27 0>; -+ }; -+ button@23 { -+ label = "GPIO KEY_RIGHT"; -+ linux,code = <106>; -+ gpios = <&gpio 23 0>; -+ }; -+ button@4 { -+ label = "GPIO KEY_ENTER"; -+ linux,code = <28>; -+ gpios = <&gpio 4 0>; -+ }; -+ }; -+ }; -+ }; -+ -+ __overrides__ { -+ speed = <&tinylcd35>,"spi-max-frequency:0"; -+ rotate = <&tinylcd35>,"rotate:0"; -+ fps = <&tinylcd35>,"fps:0"; -+ debug = <&tinylcd35>,"debug:0"; -+ touch = <&tinylcd35_ts>,"status"; -+ touchgpio = <&tinylcd35_ts_pins>,"brcm,pins:0", -+ <&tinylcd35_ts>,"interrupts:0", -+ <&tinylcd35_ts>,"pendown-gpio:4"; -+ xohms = <&tinylcd35_ts>,"ti,x-plate-ohms;0"; -+ rtc-pcf = <&i2c1>,"status", -+ <&pcf8563>,"status"; -+ rtc-ds = <&i2c1>,"status", -+ <&ds1307>,"status"; -+ keypad = <&keypad>,"status"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/uart1-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/uart1-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/uart1-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/uart1-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,38 @@ -+/dts-v1/; -+/plugin/; -+ -+/{ -+ compatible = "brcm,bcm2708"; -+ -+ fragment@0 { -+ target = <&uart1>; -+ __overlay__ { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins>; -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&gpio>; -+ __overlay__ { -+ uart1_pins: uart1_pins { -+ brcm,pins = <14 15>; -+ brcm,function = <2>; /* alt5 */ -+ brcm,pull = <0 2>; -+ }; -+ }; -+ }; -+ -+ fragment@2 { -+ target-path = "/chosen"; -+ __overlay__ { -+ bootargs = "8250.nr_uarts=1"; -+ }; -+ }; -+ -+ __overrides__ { -+ txd1_pin = <&uart1_pins>,"brcm,pins:0"; -+ rxd1_pin = <&uart1_pins>,"brcm,pins:4"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/vga666-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/vga666-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/vga666-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/vga666-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,30 @@ -+/dts-v1/; -+/plugin/; -+ -+/{ -+ compatible = "brcm,bcm2708"; -+ -+ // There is no VGA driver module, but we need a platform device -+ // node (that doesn't already use pinctrl) to hang the pinctrl -+ // reference on - leds will do -+ -+ fragment@0 { -+ target = <&leds>; -+ __overlay__ { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vga666_pins>; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&gpio>; -+ __overlay__ { -+ vga666_pins: vga666_pins { -+ brcm,pins = <2 3 4 5 6 7 8 9 10 11 12 -+ 13 14 15 16 17 18 19 20 21>; -+ brcm,function = <6>; /* alt2 */ -+ brcm,pull = <0>; /* no pull */ -+ }; -+ }; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/w1-gpio-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/w1-gpio-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/w1-gpio-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/w1-gpio-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,39 @@ -+// Definitions for w1-gpio module (without external pullup) -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2708"; -+ -+ fragment@0 { -+ target-path = "/"; -+ __overlay__ { -+ -+ w1: onewire@0 { -+ compatible = "w1-gpio"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&w1_pins>; -+ gpios = <&gpio 4 0>; -+ rpi,parasitic-power = <0>; -+ status = "okay"; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&gpio>; -+ __overlay__ { -+ w1_pins: w1_pins { -+ brcm,pins = <4>; -+ brcm,function = <0>; // in (initially) -+ brcm,pull = <0>; // off -+ }; -+ }; -+ }; -+ -+ __overrides__ { -+ gpiopin = <&w1>,"gpios:4", -+ <&w1_pins>,"brcm,pins:0"; -+ pullup = <&w1>,"rpi,parasitic-power:0"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/w1-gpio-pullup-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/w1-gpio-pullup-overlay.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/overlays/w1-gpio-pullup-overlay.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/boot/dts/overlays/w1-gpio-pullup-overlay.dts 2015-11-29 09:42:34.663447905 +0100 -@@ -0,0 +1,41 @@ -+// Definitions for w1-gpio module (with external pullup) -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2708"; -+ -+ fragment@0 { -+ target-path = "/"; -+ __overlay__ { -+ -+ w1: onewire@0 { -+ compatible = "w1-gpio"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&w1_pins>; -+ gpios = <&gpio 4 0>, <&gpio 5 1>; -+ rpi,parasitic-power = <0>; -+ status = "okay"; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&gpio>; -+ __overlay__ { -+ w1_pins: w1_pins { -+ brcm,pins = <4 5>; -+ brcm,function = <0 1>; // in out -+ brcm,pull = <0 0>; // off off -+ }; -+ }; -+ }; -+ -+ __overrides__ { -+ gpiopin = <&w1>,"gpios:4", -+ <&w1_pins>,"brcm,pins:0"; -+ extpullup = <&w1>,"gpios:16", -+ <&w1_pins>,"brcm,pins:4"; -+ pullup = <&w1>,"rpi,parasitic-power:0"; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/configs/bcm2709_defconfig linux-rpi/arch/arm/configs/bcm2709_defconfig ---- linux-4.1.13.orig/arch/arm/configs/bcm2709_defconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/configs/bcm2709_defconfig 2015-11-29 09:42:34.707444982 +0100 -@@ -0,0 +1,1260 @@ -+# CONFIG_ARM_PATCH_PHYS_VIRT is not set -+CONFIG_PHYS_OFFSET=0 -+CONFIG_LOCALVERSION="-v7" -+# CONFIG_LOCALVERSION_AUTO is not set -+CONFIG_SYSVIPC=y -+CONFIG_POSIX_MQUEUE=y -+CONFIG_FHANDLE=y -+CONFIG_NO_HZ=y -+CONFIG_HIGH_RES_TIMERS=y -+CONFIG_BSD_PROCESS_ACCT=y -+CONFIG_BSD_PROCESS_ACCT_V3=y -+CONFIG_TASKSTATS=y -+CONFIG_TASK_DELAY_ACCT=y -+CONFIG_TASK_XACCT=y -+CONFIG_TASK_IO_ACCOUNTING=y -+CONFIG_IKCONFIG=m -+CONFIG_IKCONFIG_PROC=y -+CONFIG_CGROUP_FREEZER=y -+CONFIG_CGROUP_DEVICE=y -+CONFIG_CPUSETS=y -+CONFIG_CGROUP_CPUACCT=y -+CONFIG_MEMCG=y -+CONFIG_BLK_CGROUP=y -+CONFIG_NAMESPACES=y -+CONFIG_SCHED_AUTOGROUP=y -+CONFIG_BLK_DEV_INITRD=y -+CONFIG_EMBEDDED=y -+# CONFIG_COMPAT_BRK is not set -+CONFIG_PROFILING=y -+CONFIG_OPROFILE=m -+CONFIG_KPROBES=y -+CONFIG_JUMP_LABEL=y -+CONFIG_MODULES=y -+CONFIG_MODULE_UNLOAD=y -+CONFIG_MODVERSIONS=y -+CONFIG_MODULE_SRCVERSION_ALL=y -+CONFIG_BLK_DEV_THROTTLING=y -+CONFIG_PARTITION_ADVANCED=y -+CONFIG_MAC_PARTITION=y -+CONFIG_CFQ_GROUP_IOSCHED=y -+CONFIG_ARCH_BCM2709=y -+CONFIG_BCM2709_DT=y -+# CONFIG_CACHE_L2X0 is not set -+CONFIG_SMP=y -+CONFIG_HAVE_ARM_ARCH_TIMER=y -+CONFIG_VMSPLIT_2G=y -+CONFIG_PREEMPT=y -+CONFIG_AEABI=y -+CONFIG_OABI_COMPAT=y -+CONFIG_CLEANCACHE=y -+CONFIG_FRONTSWAP=y -+CONFIG_CMA=y -+CONFIG_ZSMALLOC=m -+CONFIG_PGTABLE_MAPPING=y -+CONFIG_UACCESS_WITH_MEMCPY=y -+CONFIG_SECCOMP=y -+CONFIG_ZBOOT_ROM_TEXT=0x0 -+CONFIG_ZBOOT_ROM_BSS=0x0 -+CONFIG_CMDLINE="console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait" -+CONFIG_CPU_FREQ=y -+CONFIG_CPU_FREQ_STAT=m -+CONFIG_CPU_FREQ_STAT_DETAILS=y -+CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y -+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -+CONFIG_CPU_FREQ_GOV_USERSPACE=y -+CONFIG_CPU_FREQ_GOV_ONDEMAND=y -+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -+CONFIG_VFP=y -+CONFIG_NEON=y -+CONFIG_KERNEL_MODE_NEON=y -+CONFIG_BINFMT_MISC=m -+# CONFIG_SUSPEND is not set -+CONFIG_NET=y -+CONFIG_PACKET=y -+CONFIG_UNIX=y -+CONFIG_XFRM_USER=y -+CONFIG_NET_KEY=m -+CONFIG_INET=y -+CONFIG_IP_MULTICAST=y -+CONFIG_IP_ADVANCED_ROUTER=y -+CONFIG_IP_MULTIPLE_TABLES=y -+CONFIG_IP_ROUTE_MULTIPATH=y -+CONFIG_IP_ROUTE_VERBOSE=y -+CONFIG_IP_PNP=y -+CONFIG_IP_PNP_DHCP=y -+CONFIG_IP_PNP_RARP=y -+CONFIG_NET_IPIP=m -+CONFIG_NET_IPGRE_DEMUX=m -+CONFIG_NET_IPGRE=m -+CONFIG_IP_MROUTE=y -+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y -+CONFIG_IP_PIMSM_V1=y -+CONFIG_IP_PIMSM_V2=y -+CONFIG_SYN_COOKIES=y -+CONFIG_INET_AH=m -+CONFIG_INET_ESP=m -+CONFIG_INET_IPCOMP=m -+CONFIG_INET_XFRM_MODE_TRANSPORT=m -+CONFIG_INET_XFRM_MODE_TUNNEL=m -+CONFIG_INET_XFRM_MODE_BEET=m -+CONFIG_INET_LRO=m -+CONFIG_INET_DIAG=m -+CONFIG_INET6_AH=m -+CONFIG_INET6_ESP=m -+CONFIG_INET6_IPCOMP=m -+CONFIG_IPV6_TUNNEL=m -+CONFIG_IPV6_MULTIPLE_TABLES=y -+CONFIG_IPV6_MROUTE=y -+CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y -+CONFIG_IPV6_PIMSM_V2=y -+CONFIG_NETFILTER=y -+CONFIG_NF_CONNTRACK=m -+CONFIG_NF_CONNTRACK_ZONES=y -+CONFIG_NF_CONNTRACK_EVENTS=y -+CONFIG_NF_CONNTRACK_TIMESTAMP=y -+CONFIG_NF_CT_PROTO_DCCP=m -+CONFIG_NF_CT_PROTO_UDPLITE=m -+CONFIG_NF_CONNTRACK_AMANDA=m -+CONFIG_NF_CONNTRACK_FTP=m -+CONFIG_NF_CONNTRACK_H323=m -+CONFIG_NF_CONNTRACK_IRC=m -+CONFIG_NF_CONNTRACK_NETBIOS_NS=m -+CONFIG_NF_CONNTRACK_SNMP=m -+CONFIG_NF_CONNTRACK_PPTP=m -+CONFIG_NF_CONNTRACK_SANE=m -+CONFIG_NF_CONNTRACK_SIP=m -+CONFIG_NF_CONNTRACK_TFTP=m -+CONFIG_NF_CT_NETLINK=m -+CONFIG_NETFILTER_XT_SET=m -+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m -+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m -+CONFIG_NETFILTER_XT_TARGET_DSCP=m -+CONFIG_NETFILTER_XT_TARGET_HMARK=m -+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m -+CONFIG_NETFILTER_XT_TARGET_LED=m -+CONFIG_NETFILTER_XT_TARGET_LOG=m -+CONFIG_NETFILTER_XT_TARGET_MARK=m -+CONFIG_NETFILTER_XT_TARGET_NFLOG=m -+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m -+CONFIG_NETFILTER_XT_TARGET_TEE=m -+CONFIG_NETFILTER_XT_TARGET_TPROXY=m -+CONFIG_NETFILTER_XT_TARGET_TRACE=m -+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m -+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m -+CONFIG_NETFILTER_XT_MATCH_BPF=m -+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m -+CONFIG_NETFILTER_XT_MATCH_COMMENT=m -+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m -+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m -+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -+CONFIG_NETFILTER_XT_MATCH_CPU=m -+CONFIG_NETFILTER_XT_MATCH_DCCP=m -+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m -+CONFIG_NETFILTER_XT_MATCH_DSCP=m -+CONFIG_NETFILTER_XT_MATCH_ESP=m -+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m -+CONFIG_NETFILTER_XT_MATCH_HELPER=m -+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m -+CONFIG_NETFILTER_XT_MATCH_IPVS=m -+CONFIG_NETFILTER_XT_MATCH_LENGTH=m -+CONFIG_NETFILTER_XT_MATCH_LIMIT=m -+CONFIG_NETFILTER_XT_MATCH_MAC=m -+CONFIG_NETFILTER_XT_MATCH_MARK=m -+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -+CONFIG_NETFILTER_XT_MATCH_NFACCT=m -+CONFIG_NETFILTER_XT_MATCH_OSF=m -+CONFIG_NETFILTER_XT_MATCH_OWNER=m -+CONFIG_NETFILTER_XT_MATCH_POLICY=m -+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m -+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -+CONFIG_NETFILTER_XT_MATCH_QUOTA=m -+CONFIG_NETFILTER_XT_MATCH_RATEEST=m -+CONFIG_NETFILTER_XT_MATCH_REALM=m -+CONFIG_NETFILTER_XT_MATCH_RECENT=m -+CONFIG_NETFILTER_XT_MATCH_SOCKET=m -+CONFIG_NETFILTER_XT_MATCH_STATE=m -+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -+CONFIG_NETFILTER_XT_MATCH_STRING=m -+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -+CONFIG_NETFILTER_XT_MATCH_TIME=m -+CONFIG_NETFILTER_XT_MATCH_U32=m -+CONFIG_IP_SET=m -+CONFIG_IP_SET_BITMAP_IP=m -+CONFIG_IP_SET_BITMAP_IPMAC=m -+CONFIG_IP_SET_BITMAP_PORT=m -+CONFIG_IP_SET_HASH_IP=m -+CONFIG_IP_SET_HASH_IPPORT=m -+CONFIG_IP_SET_HASH_IPPORTIP=m -+CONFIG_IP_SET_HASH_IPPORTNET=m -+CONFIG_IP_SET_HASH_NET=m -+CONFIG_IP_SET_HASH_NETPORT=m -+CONFIG_IP_SET_HASH_NETIFACE=m -+CONFIG_IP_SET_LIST_SET=m -+CONFIG_IP_VS=m -+CONFIG_IP_VS_PROTO_TCP=y -+CONFIG_IP_VS_PROTO_UDP=y -+CONFIG_IP_VS_PROTO_ESP=y -+CONFIG_IP_VS_PROTO_AH=y -+CONFIG_IP_VS_PROTO_SCTP=y -+CONFIG_IP_VS_RR=m -+CONFIG_IP_VS_WRR=m -+CONFIG_IP_VS_LC=m -+CONFIG_IP_VS_WLC=m -+CONFIG_IP_VS_LBLC=m -+CONFIG_IP_VS_LBLCR=m -+CONFIG_IP_VS_DH=m -+CONFIG_IP_VS_SH=m -+CONFIG_IP_VS_SED=m -+CONFIG_IP_VS_NQ=m -+CONFIG_IP_VS_FTP=m -+CONFIG_IP_VS_PE_SIP=m -+CONFIG_NF_CONNTRACK_IPV4=m -+CONFIG_IP_NF_IPTABLES=m -+CONFIG_IP_NF_MATCH_AH=m -+CONFIG_IP_NF_MATCH_ECN=m -+CONFIG_IP_NF_MATCH_TTL=m -+CONFIG_IP_NF_FILTER=m -+CONFIG_IP_NF_TARGET_REJECT=m -+CONFIG_IP_NF_NAT=m -+CONFIG_IP_NF_TARGET_MASQUERADE=m -+CONFIG_IP_NF_TARGET_NETMAP=m -+CONFIG_IP_NF_TARGET_REDIRECT=m -+CONFIG_IP_NF_MANGLE=m -+CONFIG_IP_NF_TARGET_CLUSTERIP=m -+CONFIG_IP_NF_TARGET_ECN=m -+CONFIG_IP_NF_TARGET_TTL=m -+CONFIG_IP_NF_RAW=m -+CONFIG_IP_NF_ARPTABLES=m -+CONFIG_IP_NF_ARPFILTER=m -+CONFIG_IP_NF_ARP_MANGLE=m -+CONFIG_NF_CONNTRACK_IPV6=m -+CONFIG_IP6_NF_IPTABLES=m -+CONFIG_IP6_NF_MATCH_AH=m -+CONFIG_IP6_NF_MATCH_EUI64=m -+CONFIG_IP6_NF_MATCH_FRAG=m -+CONFIG_IP6_NF_MATCH_OPTS=m -+CONFIG_IP6_NF_MATCH_HL=m -+CONFIG_IP6_NF_MATCH_IPV6HEADER=m -+CONFIG_IP6_NF_MATCH_MH=m -+CONFIG_IP6_NF_MATCH_RT=m -+CONFIG_IP6_NF_TARGET_HL=m -+CONFIG_IP6_NF_FILTER=m -+CONFIG_IP6_NF_TARGET_REJECT=m -+CONFIG_IP6_NF_MANGLE=m -+CONFIG_IP6_NF_RAW=m -+CONFIG_IP6_NF_NAT=m -+CONFIG_IP6_NF_TARGET_MASQUERADE=m -+CONFIG_IP6_NF_TARGET_NPT=m -+CONFIG_BRIDGE_NF_EBTABLES=m -+CONFIG_BRIDGE_EBT_BROUTE=m -+CONFIG_BRIDGE_EBT_T_FILTER=m -+CONFIG_BRIDGE_EBT_T_NAT=m -+CONFIG_BRIDGE_EBT_802_3=m -+CONFIG_BRIDGE_EBT_AMONG=m -+CONFIG_BRIDGE_EBT_ARP=m -+CONFIG_BRIDGE_EBT_IP=m -+CONFIG_BRIDGE_EBT_IP6=m -+CONFIG_BRIDGE_EBT_LIMIT=m -+CONFIG_BRIDGE_EBT_MARK=m -+CONFIG_BRIDGE_EBT_PKTTYPE=m -+CONFIG_BRIDGE_EBT_STP=m -+CONFIG_BRIDGE_EBT_VLAN=m -+CONFIG_BRIDGE_EBT_ARPREPLY=m -+CONFIG_BRIDGE_EBT_DNAT=m -+CONFIG_BRIDGE_EBT_MARK_T=m -+CONFIG_BRIDGE_EBT_REDIRECT=m -+CONFIG_BRIDGE_EBT_SNAT=m -+CONFIG_BRIDGE_EBT_LOG=m -+CONFIG_BRIDGE_EBT_NFLOG=m -+CONFIG_SCTP_COOKIE_HMAC_SHA1=y -+CONFIG_ATM=m -+CONFIG_L2TP=m -+CONFIG_L2TP_V3=y -+CONFIG_L2TP_IP=m -+CONFIG_L2TP_ETH=m -+CONFIG_BRIDGE=m -+CONFIG_VLAN_8021Q=m -+CONFIG_VLAN_8021Q_GVRP=y -+CONFIG_ATALK=m -+CONFIG_6LOWPAN=m -+CONFIG_IEEE802154=m -+CONFIG_IEEE802154_6LOWPAN=m -+CONFIG_MAC802154=m -+CONFIG_NET_SCHED=y -+CONFIG_NET_SCH_CBQ=m -+CONFIG_NET_SCH_HTB=m -+CONFIG_NET_SCH_HFSC=m -+CONFIG_NET_SCH_PRIO=m -+CONFIG_NET_SCH_MULTIQ=m -+CONFIG_NET_SCH_RED=m -+CONFIG_NET_SCH_SFB=m -+CONFIG_NET_SCH_SFQ=m -+CONFIG_NET_SCH_TEQL=m -+CONFIG_NET_SCH_TBF=m -+CONFIG_NET_SCH_GRED=m -+CONFIG_NET_SCH_DSMARK=m -+CONFIG_NET_SCH_NETEM=m -+CONFIG_NET_SCH_DRR=m -+CONFIG_NET_SCH_MQPRIO=m -+CONFIG_NET_SCH_CHOKE=m -+CONFIG_NET_SCH_QFQ=m -+CONFIG_NET_SCH_CODEL=m -+CONFIG_NET_SCH_FQ_CODEL=m -+CONFIG_NET_SCH_INGRESS=m -+CONFIG_NET_SCH_PLUG=m -+CONFIG_NET_CLS_BASIC=m -+CONFIG_NET_CLS_TCINDEX=m -+CONFIG_NET_CLS_ROUTE4=m -+CONFIG_NET_CLS_FW=m -+CONFIG_NET_CLS_U32=m -+CONFIG_CLS_U32_MARK=y -+CONFIG_NET_CLS_RSVP=m -+CONFIG_NET_CLS_RSVP6=m -+CONFIG_NET_CLS_FLOW=m -+CONFIG_NET_CLS_CGROUP=m -+CONFIG_NET_EMATCH=y -+CONFIG_NET_EMATCH_CMP=m -+CONFIG_NET_EMATCH_NBYTE=m -+CONFIG_NET_EMATCH_U32=m -+CONFIG_NET_EMATCH_META=m -+CONFIG_NET_EMATCH_TEXT=m -+CONFIG_NET_EMATCH_IPSET=m -+CONFIG_NET_CLS_ACT=y -+CONFIG_NET_ACT_POLICE=m -+CONFIG_NET_ACT_GACT=m -+CONFIG_GACT_PROB=y -+CONFIG_NET_ACT_MIRRED=m -+CONFIG_NET_ACT_IPT=m -+CONFIG_NET_ACT_NAT=m -+CONFIG_NET_ACT_PEDIT=m -+CONFIG_NET_ACT_SIMP=m -+CONFIG_NET_ACT_SKBEDIT=m -+CONFIG_NET_ACT_CSUM=m -+CONFIG_BATMAN_ADV=m -+CONFIG_OPENVSWITCH=m -+CONFIG_NET_PKTGEN=m -+CONFIG_HAMRADIO=y -+CONFIG_AX25=m -+CONFIG_NETROM=m -+CONFIG_ROSE=m -+CONFIG_MKISS=m -+CONFIG_6PACK=m -+CONFIG_BPQETHER=m -+CONFIG_BAYCOM_SER_FDX=m -+CONFIG_BAYCOM_SER_HDX=m -+CONFIG_YAM=m -+CONFIG_CAN=m -+CONFIG_CAN_VCAN=m -+CONFIG_CAN_MCP251X=m -+CONFIG_IRDA=m -+CONFIG_IRLAN=m -+CONFIG_IRNET=m -+CONFIG_IRCOMM=m -+CONFIG_IRDA_ULTRA=y -+CONFIG_IRDA_CACHE_LAST_LSAP=y -+CONFIG_IRDA_FAST_RR=y -+CONFIG_IRTTY_SIR=m -+CONFIG_KINGSUN_DONGLE=m -+CONFIG_KSDAZZLE_DONGLE=m -+CONFIG_KS959_DONGLE=m -+CONFIG_USB_IRDA=m -+CONFIG_SIGMATEL_FIR=m -+CONFIG_MCS_FIR=m -+CONFIG_BT=m -+CONFIG_BT_RFCOMM=m -+CONFIG_BT_RFCOMM_TTY=y -+CONFIG_BT_BNEP=m -+CONFIG_BT_BNEP_MC_FILTER=y -+CONFIG_BT_BNEP_PROTO_FILTER=y -+CONFIG_BT_HIDP=m -+CONFIG_BT_6LOWPAN=m -+CONFIG_BT_HCIBTUSB=m -+CONFIG_BT_HCIBCM203X=m -+CONFIG_BT_HCIBPA10X=m -+CONFIG_BT_HCIBFUSB=m -+CONFIG_BT_HCIVHCI=m -+CONFIG_BT_MRVL=m -+CONFIG_BT_MRVL_SDIO=m -+CONFIG_BT_ATH3K=m -+CONFIG_BT_WILINK=m -+CONFIG_MAC80211=m -+CONFIG_MAC80211_MESH=y -+CONFIG_WIMAX=m -+CONFIG_RFKILL=m -+CONFIG_RFKILL_INPUT=y -+CONFIG_NET_9P=m -+CONFIG_NFC=m -+CONFIG_NFC_PN533=m -+CONFIG_DEVTMPFS=y -+CONFIG_DEVTMPFS_MOUNT=y -+CONFIG_DMA_CMA=y -+CONFIG_CMA_SIZE_MBYTES=5 -+CONFIG_MTD=m -+CONFIG_MTD_BLOCK=m -+CONFIG_MTD_NAND=m -+CONFIG_MTD_UBI=m -+CONFIG_ZRAM=m -+CONFIG_ZRAM_LZ4_COMPRESS=y -+CONFIG_BLK_DEV_LOOP=y -+CONFIG_BLK_DEV_CRYPTOLOOP=m -+CONFIG_BLK_DEV_DRBD=m -+CONFIG_BLK_DEV_NBD=m -+CONFIG_BLK_DEV_RAM=y -+CONFIG_CDROM_PKTCDVD=m -+CONFIG_ATA_OVER_ETH=m -+CONFIG_EEPROM_AT24=m -+CONFIG_TI_ST=m -+CONFIG_SCSI=y -+# CONFIG_SCSI_PROC_FS is not set -+CONFIG_BLK_DEV_SD=y -+CONFIG_CHR_DEV_ST=m -+CONFIG_CHR_DEV_OSST=m -+CONFIG_BLK_DEV_SR=m -+CONFIG_CHR_DEV_SG=m -+CONFIG_SCSI_ISCSI_ATTRS=y -+CONFIG_ISCSI_TCP=m -+CONFIG_ISCSI_BOOT_SYSFS=m -+CONFIG_MD=y -+CONFIG_MD_LINEAR=m -+CONFIG_MD_RAID0=m -+CONFIG_BLK_DEV_DM=m -+CONFIG_DM_CRYPT=m -+CONFIG_DM_SNAPSHOT=m -+CONFIG_DM_THIN_PROVISIONING=m -+CONFIG_DM_MIRROR=m -+CONFIG_DM_LOG_USERSPACE=m -+CONFIG_DM_RAID=m -+CONFIG_DM_ZERO=m -+CONFIG_DM_DELAY=m -+CONFIG_NETDEVICES=y -+CONFIG_BONDING=m -+CONFIG_DUMMY=m -+CONFIG_IFB=m -+CONFIG_MACVLAN=m -+CONFIG_NETCONSOLE=m -+CONFIG_TUN=m -+CONFIG_VETH=m -+CONFIG_ENC28J60=m -+CONFIG_MDIO_BITBANG=m -+CONFIG_PPP=m -+CONFIG_PPP_BSDCOMP=m -+CONFIG_PPP_DEFLATE=m -+CONFIG_PPP_FILTER=y -+CONFIG_PPP_MPPE=m -+CONFIG_PPP_MULTILINK=y -+CONFIG_PPPOATM=m -+CONFIG_PPPOE=m -+CONFIG_PPPOL2TP=m -+CONFIG_PPP_ASYNC=m -+CONFIG_PPP_SYNC_TTY=m -+CONFIG_SLIP=m -+CONFIG_SLIP_COMPRESSED=y -+CONFIG_SLIP_SMART=y -+CONFIG_USB_CATC=m -+CONFIG_USB_KAWETH=m -+CONFIG_USB_PEGASUS=m -+CONFIG_USB_RTL8150=m -+CONFIG_USB_RTL8152=m -+CONFIG_USB_USBNET=y -+CONFIG_USB_NET_AX8817X=m -+CONFIG_USB_NET_AX88179_178A=m -+CONFIG_USB_NET_CDCETHER=m -+CONFIG_USB_NET_CDC_EEM=m -+CONFIG_USB_NET_CDC_NCM=m -+CONFIG_USB_NET_HUAWEI_CDC_NCM=m -+CONFIG_USB_NET_CDC_MBIM=m -+CONFIG_USB_NET_DM9601=m -+CONFIG_USB_NET_SR9700=m -+CONFIG_USB_NET_SR9800=m -+CONFIG_USB_NET_SMSC75XX=m -+CONFIG_USB_NET_SMSC95XX=y -+CONFIG_USB_NET_GL620A=m -+CONFIG_USB_NET_NET1080=m -+CONFIG_USB_NET_PLUSB=m -+CONFIG_USB_NET_MCS7830=m -+CONFIG_USB_NET_CDC_SUBSET=m -+CONFIG_USB_ALI_M5632=y -+CONFIG_USB_AN2720=y -+CONFIG_USB_EPSON2888=y -+CONFIG_USB_KC2190=y -+CONFIG_USB_NET_ZAURUS=m -+CONFIG_USB_NET_CX82310_ETH=m -+CONFIG_USB_NET_KALMIA=m -+CONFIG_USB_NET_QMI_WWAN=m -+CONFIG_USB_HSO=m -+CONFIG_USB_NET_INT51X1=m -+CONFIG_USB_IPHETH=m -+CONFIG_USB_SIERRA_NET=m -+CONFIG_USB_VL600=m -+CONFIG_LIBERTAS_THINFIRM=m -+CONFIG_LIBERTAS_THINFIRM_USB=m -+CONFIG_AT76C50X_USB=m -+CONFIG_USB_ZD1201=m -+CONFIG_USB_NET_RNDIS_WLAN=m -+CONFIG_RTL8187=m -+CONFIG_MAC80211_HWSIM=m -+CONFIG_ATH_CARDS=m -+CONFIG_ATH9K=m -+CONFIG_ATH9K_HTC=m -+CONFIG_CARL9170=m -+CONFIG_ATH6KL=m -+CONFIG_ATH6KL_USB=m -+CONFIG_AR5523=m -+CONFIG_B43=m -+# CONFIG_B43_PHY_N is not set -+CONFIG_B43LEGACY=m -+CONFIG_BRCMFMAC=m -+CONFIG_BRCMFMAC_USB=y -+CONFIG_HOSTAP=m -+CONFIG_LIBERTAS=m -+CONFIG_LIBERTAS_USB=m -+CONFIG_LIBERTAS_SDIO=m -+CONFIG_P54_COMMON=m -+CONFIG_P54_USB=m -+CONFIG_RT2X00=m -+CONFIG_RT2500USB=m -+CONFIG_RT73USB=m -+CONFIG_RT2800USB=m -+CONFIG_RT2800USB_RT3573=y -+CONFIG_RT2800USB_RT53XX=y -+CONFIG_RT2800USB_RT55XX=y -+CONFIG_RT2800USB_UNKNOWN=y -+CONFIG_WL_MEDIATEK=y -+CONFIG_MT7601U=m -+CONFIG_RTL8192CU=m -+CONFIG_ZD1211RW=m -+CONFIG_MWIFIEX=m -+CONFIG_MWIFIEX_SDIO=m -+CONFIG_WIMAX_I2400M_USB=m -+CONFIG_IEEE802154_AT86RF230=m -+CONFIG_IEEE802154_MRF24J40=m -+CONFIG_IEEE802154_CC2520=m -+CONFIG_INPUT_POLLDEV=m -+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -+CONFIG_INPUT_JOYDEV=m -+CONFIG_INPUT_EVDEV=m -+# CONFIG_KEYBOARD_ATKBD is not set -+CONFIG_KEYBOARD_GPIO=m -+# CONFIG_INPUT_MOUSE is not set -+CONFIG_INPUT_JOYSTICK=y -+CONFIG_JOYSTICK_IFORCE=m -+CONFIG_JOYSTICK_IFORCE_USB=y -+CONFIG_JOYSTICK_XPAD=m -+CONFIG_JOYSTICK_XPAD_FF=y -+CONFIG_JOYSTICK_RPISENSE=m -+CONFIG_INPUT_TOUCHSCREEN=y -+CONFIG_TOUCHSCREEN_ADS7846=m -+CONFIG_TOUCHSCREEN_EGALAX=m -+CONFIG_TOUCHSCREEN_FT6236=m -+CONFIG_TOUCHSCREEN_RPI_FT5406=m -+CONFIG_TOUCHSCREEN_USB_COMPOSITE=m -+CONFIG_TOUCHSCREEN_STMPE=m -+CONFIG_INPUT_MISC=y -+CONFIG_INPUT_AD714X=m -+CONFIG_INPUT_ATI_REMOTE2=m -+CONFIG_INPUT_KEYSPAN_REMOTE=m -+CONFIG_INPUT_POWERMATE=m -+CONFIG_INPUT_YEALINK=m -+CONFIG_INPUT_CM109=m -+CONFIG_INPUT_UINPUT=m -+CONFIG_INPUT_GPIO_ROTARY_ENCODER=m -+CONFIG_INPUT_ADXL34X=m -+CONFIG_INPUT_CMA3000=m -+CONFIG_SERIO=m -+CONFIG_SERIO_RAW=m -+CONFIG_GAMEPORT=m -+CONFIG_GAMEPORT_NS558=m -+CONFIG_GAMEPORT_L4=m -+CONFIG_DEVPTS_MULTIPLE_INSTANCES=y -+# CONFIG_LEGACY_PTYS is not set -+# CONFIG_DEVKMEM is not set -+CONFIG_SERIAL_8250=y -+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set -+CONFIG_SERIAL_8250_CONSOLE=y -+# CONFIG_SERIAL_8250_DMA is not set -+CONFIG_SERIAL_8250_NR_UARTS=1 -+CONFIG_SERIAL_8250_RUNTIME_UARTS=0 -+CONFIG_SERIAL_AMBA_PL011=y -+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -+CONFIG_SERIAL_OF_PLATFORM=y -+CONFIG_TTY_PRINTK=y -+CONFIG_HW_RANDOM=y -+CONFIG_HW_RANDOM_BCM2835=m -+CONFIG_HW_RANDOM_BCM2708=m -+CONFIG_RAW_DRIVER=y -+CONFIG_BRCM_CHAR_DRIVERS=y -+CONFIG_BCM_VC_CMA=y -+CONFIG_BCM_VCIO=y -+CONFIG_BCM_VC_SM=y -+CONFIG_I2C=y -+CONFIG_I2C_CHARDEV=m -+CONFIG_I2C_BCM2708=m -+CONFIG_I2C_GPIO=m -+CONFIG_SPI=y -+CONFIG_SPI_BCM2835=m -+CONFIG_SPI_BCM2708=m -+CONFIG_SPI_SPIDEV=y -+CONFIG_PPS=m -+CONFIG_PPS_CLIENT_LDISC=m -+CONFIG_PPS_CLIENT_GPIO=m -+CONFIG_GPIO_SYSFS=y -+CONFIG_GPIO_ARIZONA=m -+CONFIG_GPIO_STMPE=y -+CONFIG_W1=m -+CONFIG_W1_MASTER_DS2490=m -+CONFIG_W1_MASTER_DS2482=m -+CONFIG_W1_MASTER_DS1WM=m -+CONFIG_W1_MASTER_GPIO=m -+CONFIG_W1_SLAVE_THERM=m -+CONFIG_W1_SLAVE_SMEM=m -+CONFIG_W1_SLAVE_DS2408=m -+CONFIG_W1_SLAVE_DS2413=m -+CONFIG_W1_SLAVE_DS2406=m -+CONFIG_W1_SLAVE_DS2423=m -+CONFIG_W1_SLAVE_DS2431=m -+CONFIG_W1_SLAVE_DS2433=m -+CONFIG_W1_SLAVE_DS2760=m -+CONFIG_W1_SLAVE_DS2780=m -+CONFIG_W1_SLAVE_DS2781=m -+CONFIG_W1_SLAVE_DS28E04=m -+CONFIG_W1_SLAVE_BQ27000=m -+CONFIG_BATTERY_DS2760=m -+CONFIG_POWER_RESET=y -+CONFIG_POWER_RESET_GPIO=y -+CONFIG_HWMON=m -+CONFIG_SENSORS_SHT21=m -+CONFIG_SENSORS_SHTC1=m -+CONFIG_THERMAL=y -+CONFIG_THERMAL_BCM2835=y -+CONFIG_WATCHDOG=y -+CONFIG_BCM2708_WDT=m -+CONFIG_BCM2835_WDT=m -+CONFIG_UCB1400_CORE=m -+CONFIG_MFD_STMPE=y -+CONFIG_STMPE_SPI=y -+CONFIG_MFD_ARIZONA_I2C=m -+CONFIG_MFD_ARIZONA_SPI=m -+CONFIG_MFD_WM5102=y -+CONFIG_MEDIA_SUPPORT=m -+CONFIG_MEDIA_CAMERA_SUPPORT=y -+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y -+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y -+CONFIG_MEDIA_RADIO_SUPPORT=y -+CONFIG_MEDIA_RC_SUPPORT=y -+CONFIG_MEDIA_CONTROLLER=y -+CONFIG_LIRC=m -+CONFIG_RC_DEVICES=y -+CONFIG_RC_ATI_REMOTE=m -+CONFIG_IR_IMON=m -+CONFIG_IR_MCEUSB=m -+CONFIG_IR_REDRAT3=m -+CONFIG_IR_STREAMZAP=m -+CONFIG_IR_IGUANA=m -+CONFIG_IR_TTUSBIR=m -+CONFIG_RC_LOOPBACK=m -+CONFIG_IR_GPIO_CIR=m -+CONFIG_MEDIA_USB_SUPPORT=y -+CONFIG_USB_VIDEO_CLASS=m -+CONFIG_USB_M5602=m -+CONFIG_USB_STV06XX=m -+CONFIG_USB_GL860=m -+CONFIG_USB_GSPCA_BENQ=m -+CONFIG_USB_GSPCA_CONEX=m -+CONFIG_USB_GSPCA_CPIA1=m -+CONFIG_USB_GSPCA_DTCS033=m -+CONFIG_USB_GSPCA_ETOMS=m -+CONFIG_USB_GSPCA_FINEPIX=m -+CONFIG_USB_GSPCA_JEILINJ=m -+CONFIG_USB_GSPCA_JL2005BCD=m -+CONFIG_USB_GSPCA_KINECT=m -+CONFIG_USB_GSPCA_KONICA=m -+CONFIG_USB_GSPCA_MARS=m -+CONFIG_USB_GSPCA_MR97310A=m -+CONFIG_USB_GSPCA_NW80X=m -+CONFIG_USB_GSPCA_OV519=m -+CONFIG_USB_GSPCA_OV534=m -+CONFIG_USB_GSPCA_OV534_9=m -+CONFIG_USB_GSPCA_PAC207=m -+CONFIG_USB_GSPCA_PAC7302=m -+CONFIG_USB_GSPCA_PAC7311=m -+CONFIG_USB_GSPCA_SE401=m -+CONFIG_USB_GSPCA_SN9C2028=m -+CONFIG_USB_GSPCA_SN9C20X=m -+CONFIG_USB_GSPCA_SONIXB=m -+CONFIG_USB_GSPCA_SONIXJ=m -+CONFIG_USB_GSPCA_SPCA500=m -+CONFIG_USB_GSPCA_SPCA501=m -+CONFIG_USB_GSPCA_SPCA505=m -+CONFIG_USB_GSPCA_SPCA506=m -+CONFIG_USB_GSPCA_SPCA508=m -+CONFIG_USB_GSPCA_SPCA561=m -+CONFIG_USB_GSPCA_SPCA1528=m -+CONFIG_USB_GSPCA_SQ905=m -+CONFIG_USB_GSPCA_SQ905C=m -+CONFIG_USB_GSPCA_SQ930X=m -+CONFIG_USB_GSPCA_STK014=m -+CONFIG_USB_GSPCA_STK1135=m -+CONFIG_USB_GSPCA_STV0680=m -+CONFIG_USB_GSPCA_SUNPLUS=m -+CONFIG_USB_GSPCA_T613=m -+CONFIG_USB_GSPCA_TOPRO=m -+CONFIG_USB_GSPCA_TV8532=m -+CONFIG_USB_GSPCA_VC032X=m -+CONFIG_USB_GSPCA_VICAM=m -+CONFIG_USB_GSPCA_XIRLINK_CIT=m -+CONFIG_USB_GSPCA_ZC3XX=m -+CONFIG_USB_PWC=m -+CONFIG_VIDEO_CPIA2=m -+CONFIG_USB_ZR364XX=m -+CONFIG_USB_STKWEBCAM=m -+CONFIG_USB_S2255=m -+CONFIG_VIDEO_USBTV=m -+CONFIG_VIDEO_PVRUSB2=m -+CONFIG_VIDEO_HDPVR=m -+CONFIG_VIDEO_USBVISION=m -+CONFIG_VIDEO_STK1160_COMMON=m -+CONFIG_VIDEO_STK1160_AC97=y -+CONFIG_VIDEO_GO7007=m -+CONFIG_VIDEO_GO7007_USB=m -+CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m -+CONFIG_VIDEO_AU0828=m -+CONFIG_VIDEO_AU0828_RC=y -+CONFIG_VIDEO_CX231XX=m -+CONFIG_VIDEO_CX231XX_ALSA=m -+CONFIG_VIDEO_CX231XX_DVB=m -+CONFIG_VIDEO_TM6000=m -+CONFIG_VIDEO_TM6000_ALSA=m -+CONFIG_VIDEO_TM6000_DVB=m -+CONFIG_DVB_USB=m -+CONFIG_DVB_USB_A800=m -+CONFIG_DVB_USB_DIBUSB_MB=m -+CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y -+CONFIG_DVB_USB_DIBUSB_MC=m -+CONFIG_DVB_USB_DIB0700=m -+CONFIG_DVB_USB_UMT_010=m -+CONFIG_DVB_USB_CXUSB=m -+CONFIG_DVB_USB_M920X=m -+CONFIG_DVB_USB_DIGITV=m -+CONFIG_DVB_USB_VP7045=m -+CONFIG_DVB_USB_VP702X=m -+CONFIG_DVB_USB_GP8PSK=m -+CONFIG_DVB_USB_NOVA_T_USB2=m -+CONFIG_DVB_USB_TTUSB2=m -+CONFIG_DVB_USB_DTT200U=m -+CONFIG_DVB_USB_OPERA1=m -+CONFIG_DVB_USB_AF9005=m -+CONFIG_DVB_USB_AF9005_REMOTE=m -+CONFIG_DVB_USB_PCTV452E=m -+CONFIG_DVB_USB_DW2102=m -+CONFIG_DVB_USB_CINERGY_T2=m -+CONFIG_DVB_USB_DTV5100=m -+CONFIG_DVB_USB_FRIIO=m -+CONFIG_DVB_USB_AZ6027=m -+CONFIG_DVB_USB_TECHNISAT_USB2=m -+CONFIG_DVB_USB_V2=m -+CONFIG_DVB_USB_AF9015=m -+CONFIG_DVB_USB_AF9035=m -+CONFIG_DVB_USB_ANYSEE=m -+CONFIG_DVB_USB_AU6610=m -+CONFIG_DVB_USB_AZ6007=m -+CONFIG_DVB_USB_CE6230=m -+CONFIG_DVB_USB_EC168=m -+CONFIG_DVB_USB_GL861=m -+CONFIG_DVB_USB_LME2510=m -+CONFIG_DVB_USB_MXL111SF=m -+CONFIG_DVB_USB_RTL28XXU=m -+CONFIG_DVB_USB_DVBSKY=m -+CONFIG_SMS_USB_DRV=m -+CONFIG_DVB_B2C2_FLEXCOP_USB=m -+CONFIG_DVB_AS102=m -+CONFIG_VIDEO_EM28XX=m -+CONFIG_VIDEO_EM28XX_V4L2=m -+CONFIG_VIDEO_EM28XX_ALSA=m -+CONFIG_VIDEO_EM28XX_DVB=m -+CONFIG_V4L_PLATFORM_DRIVERS=y -+CONFIG_VIDEO_BCM2835=y -+CONFIG_VIDEO_BCM2835_MMAL=m -+CONFIG_RADIO_SI470X=y -+CONFIG_USB_SI470X=m -+CONFIG_I2C_SI470X=m -+CONFIG_RADIO_SI4713=m -+CONFIG_I2C_SI4713=m -+CONFIG_USB_MR800=m -+CONFIG_USB_DSBR=m -+CONFIG_RADIO_SHARK=m -+CONFIG_RADIO_SHARK2=m -+CONFIG_USB_KEENE=m -+CONFIG_USB_MA901=m -+CONFIG_RADIO_TEA5764=m -+CONFIG_RADIO_SAA7706H=m -+CONFIG_RADIO_TEF6862=m -+CONFIG_RADIO_WL1273=m -+CONFIG_RADIO_WL128X=m -+# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set -+CONFIG_VIDEO_UDA1342=m -+CONFIG_VIDEO_SONY_BTF_MPX=m -+CONFIG_VIDEO_TVP5150=m -+CONFIG_VIDEO_TW2804=m -+CONFIG_VIDEO_TW9903=m -+CONFIG_VIDEO_TW9906=m -+CONFIG_VIDEO_OV7640=m -+CONFIG_VIDEO_MT9V011=m -+CONFIG_FB=y -+CONFIG_FB_BCM2708=y -+CONFIG_FB_UDL=m -+CONFIG_FB_SSD1307=m -+CONFIG_FB_RPISENSE=m -+# CONFIG_BACKLIGHT_GENERIC is not set -+CONFIG_BACKLIGHT_RPI=m -+CONFIG_BACKLIGHT_GPIO=m -+CONFIG_FRAMEBUFFER_CONSOLE=y -+CONFIG_LOGO=y -+# CONFIG_LOGO_LINUX_MONO is not set -+# CONFIG_LOGO_LINUX_VGA16 is not set -+CONFIG_SOUND=y -+CONFIG_SND=m -+CONFIG_SND_SEQUENCER=m -+CONFIG_SND_SEQ_DUMMY=m -+CONFIG_SND_MIXER_OSS=m -+CONFIG_SND_PCM_OSS=m -+CONFIG_SND_SEQUENCER_OSS=y -+CONFIG_SND_HRTIMER=m -+CONFIG_SND_DUMMY=m -+CONFIG_SND_ALOOP=m -+CONFIG_SND_VIRMIDI=m -+CONFIG_SND_MTPAV=m -+CONFIG_SND_SERIAL_U16550=m -+CONFIG_SND_MPU401=m -+CONFIG_SND_BCM2835=m -+CONFIG_SND_USB_AUDIO=m -+CONFIG_SND_USB_UA101=m -+CONFIG_SND_USB_CAIAQ=m -+CONFIG_SND_USB_CAIAQ_INPUT=y -+CONFIG_SND_USB_6FIRE=m -+CONFIG_SND_SOC=m -+CONFIG_SND_BCM2708_SOC_I2S=m -+CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m -+CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m -+CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m -+CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m -+CONFIG_SND_BCM2708_SOC_RPI_DAC=m -+CONFIG_SND_BCM2708_SOC_RPI_PROTO=m -+CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m -+CONFIG_SND_BCM2708_SOC_RASPIDAC3=m -+CONFIG_SND_SOC_ADAU1701=m -+CONFIG_SND_SOC_WM8804_I2C=m -+CONFIG_SND_SIMPLE_CARD=m -+CONFIG_SOUND_PRIME=m -+CONFIG_HIDRAW=y -+CONFIG_UHID=m -+CONFIG_HID_A4TECH=m -+CONFIG_HID_ACRUX=m -+CONFIG_HID_APPLE=m -+CONFIG_HID_BELKIN=m -+CONFIG_HID_CHERRY=m -+CONFIG_HID_CHICONY=m -+CONFIG_HID_CYPRESS=m -+CONFIG_HID_DRAGONRISE=m -+CONFIG_HID_EMS_FF=m -+CONFIG_HID_ELECOM=m -+CONFIG_HID_ELO=m -+CONFIG_HID_EZKEY=m -+CONFIG_HID_HOLTEK=m -+CONFIG_HID_KEYTOUCH=m -+CONFIG_HID_KYE=m -+CONFIG_HID_UCLOGIC=m -+CONFIG_HID_WALTOP=m -+CONFIG_HID_GYRATION=m -+CONFIG_HID_TWINHAN=m -+CONFIG_HID_KENSINGTON=m -+CONFIG_HID_LCPOWER=m -+CONFIG_HID_LOGITECH=m -+CONFIG_HID_MAGICMOUSE=m -+CONFIG_HID_MICROSOFT=m -+CONFIG_HID_MONTEREY=m -+CONFIG_HID_MULTITOUCH=m -+CONFIG_HID_NTRIG=m -+CONFIG_HID_ORTEK=m -+CONFIG_HID_PANTHERLORD=m -+CONFIG_HID_PETALYNX=m -+CONFIG_HID_PICOLCD=m -+CONFIG_HID_ROCCAT=m -+CONFIG_HID_SAMSUNG=m -+CONFIG_HID_SONY=m -+CONFIG_HID_SPEEDLINK=m -+CONFIG_HID_SUNPLUS=m -+CONFIG_HID_GREENASIA=m -+CONFIG_HID_SMARTJOYPLUS=m -+CONFIG_HID_TOPSEED=m -+CONFIG_HID_THINGM=m -+CONFIG_HID_THRUSTMASTER=m -+CONFIG_HID_WACOM=m -+CONFIG_HID_WIIMOTE=m -+CONFIG_HID_XINMO=m -+CONFIG_HID_ZEROPLUS=m -+CONFIG_HID_ZYDACRON=m -+CONFIG_HID_PID=y -+CONFIG_USB_HIDDEV=y -+CONFIG_USB=y -+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -+CONFIG_USB_MON=m -+CONFIG_USB_DWCOTG=y -+CONFIG_USB_PRINTER=m -+CONFIG_USB_STORAGE=y -+CONFIG_USB_STORAGE_REALTEK=m -+CONFIG_USB_STORAGE_DATAFAB=m -+CONFIG_USB_STORAGE_FREECOM=m -+CONFIG_USB_STORAGE_ISD200=m -+CONFIG_USB_STORAGE_USBAT=m -+CONFIG_USB_STORAGE_SDDR09=m -+CONFIG_USB_STORAGE_SDDR55=m -+CONFIG_USB_STORAGE_JUMPSHOT=m -+CONFIG_USB_STORAGE_ALAUDA=m -+CONFIG_USB_STORAGE_ONETOUCH=m -+CONFIG_USB_STORAGE_KARMA=m -+CONFIG_USB_STORAGE_CYPRESS_ATACB=m -+CONFIG_USB_STORAGE_ENE_UB6250=m -+CONFIG_USB_MDC800=m -+CONFIG_USB_MICROTEK=m -+CONFIG_USBIP_CORE=m -+CONFIG_USBIP_VHCI_HCD=m -+CONFIG_USBIP_HOST=m -+CONFIG_USB_SERIAL=m -+CONFIG_USB_SERIAL_GENERIC=y -+CONFIG_USB_SERIAL_AIRCABLE=m -+CONFIG_USB_SERIAL_ARK3116=m -+CONFIG_USB_SERIAL_BELKIN=m -+CONFIG_USB_SERIAL_CH341=m -+CONFIG_USB_SERIAL_WHITEHEAT=m -+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m -+CONFIG_USB_SERIAL_CP210X=m -+CONFIG_USB_SERIAL_CYPRESS_M8=m -+CONFIG_USB_SERIAL_EMPEG=m -+CONFIG_USB_SERIAL_FTDI_SIO=m -+CONFIG_USB_SERIAL_VISOR=m -+CONFIG_USB_SERIAL_IPAQ=m -+CONFIG_USB_SERIAL_IR=m -+CONFIG_USB_SERIAL_EDGEPORT=m -+CONFIG_USB_SERIAL_EDGEPORT_TI=m -+CONFIG_USB_SERIAL_F81232=m -+CONFIG_USB_SERIAL_GARMIN=m -+CONFIG_USB_SERIAL_IPW=m -+CONFIG_USB_SERIAL_IUU=m -+CONFIG_USB_SERIAL_KEYSPAN_PDA=m -+CONFIG_USB_SERIAL_KEYSPAN=m -+CONFIG_USB_SERIAL_KLSI=m -+CONFIG_USB_SERIAL_KOBIL_SCT=m -+CONFIG_USB_SERIAL_MCT_U232=m -+CONFIG_USB_SERIAL_METRO=m -+CONFIG_USB_SERIAL_MOS7720=m -+CONFIG_USB_SERIAL_MOS7840=m -+CONFIG_USB_SERIAL_NAVMAN=m -+CONFIG_USB_SERIAL_PL2303=m -+CONFIG_USB_SERIAL_OTI6858=m -+CONFIG_USB_SERIAL_QCAUX=m -+CONFIG_USB_SERIAL_QUALCOMM=m -+CONFIG_USB_SERIAL_SPCP8X5=m -+CONFIG_USB_SERIAL_SAFE=m -+CONFIG_USB_SERIAL_SIERRAWIRELESS=m -+CONFIG_USB_SERIAL_SYMBOL=m -+CONFIG_USB_SERIAL_TI=m -+CONFIG_USB_SERIAL_CYBERJACK=m -+CONFIG_USB_SERIAL_XIRCOM=m -+CONFIG_USB_SERIAL_OPTION=m -+CONFIG_USB_SERIAL_OMNINET=m -+CONFIG_USB_SERIAL_OPTICON=m -+CONFIG_USB_SERIAL_XSENS_MT=m -+CONFIG_USB_SERIAL_WISHBONE=m -+CONFIG_USB_SERIAL_SSU100=m -+CONFIG_USB_SERIAL_QT2=m -+CONFIG_USB_SERIAL_DEBUG=m -+CONFIG_USB_EMI62=m -+CONFIG_USB_EMI26=m -+CONFIG_USB_ADUTUX=m -+CONFIG_USB_SEVSEG=m -+CONFIG_USB_RIO500=m -+CONFIG_USB_LEGOTOWER=m -+CONFIG_USB_LCD=m -+CONFIG_USB_LED=m -+CONFIG_USB_CYPRESS_CY7C63=m -+CONFIG_USB_CYTHERM=m -+CONFIG_USB_IDMOUSE=m -+CONFIG_USB_FTDI_ELAN=m -+CONFIG_USB_APPLEDISPLAY=m -+CONFIG_USB_LD=m -+CONFIG_USB_TRANCEVIBRATOR=m -+CONFIG_USB_IOWARRIOR=m -+CONFIG_USB_TEST=m -+CONFIG_USB_ISIGHTFW=m -+CONFIG_USB_YUREX=m -+CONFIG_USB_ATM=m -+CONFIG_USB_SPEEDTOUCH=m -+CONFIG_USB_CXACRU=m -+CONFIG_USB_UEAGLEATM=m -+CONFIG_USB_XUSBATM=m -+CONFIG_MMC=y -+CONFIG_MMC_BLOCK_MINORS=32 -+CONFIG_MMC_BCM2835=y -+CONFIG_MMC_BCM2835_DMA=y -+CONFIG_MMC_BCM2835_SDHOST=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_PLTFM=y -+CONFIG_MMC_SPI=m -+CONFIG_LEDS_CLASS=y -+CONFIG_LEDS_GPIO=y -+CONFIG_LEDS_TRIGGER_TIMER=y -+CONFIG_LEDS_TRIGGER_ONESHOT=y -+CONFIG_LEDS_TRIGGER_HEARTBEAT=y -+CONFIG_LEDS_TRIGGER_BACKLIGHT=y -+CONFIG_LEDS_TRIGGER_CPU=y -+CONFIG_LEDS_TRIGGER_GPIO=y -+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y -+CONFIG_LEDS_TRIGGER_TRANSIENT=m -+CONFIG_LEDS_TRIGGER_CAMERA=m -+CONFIG_LEDS_TRIGGER_INPUT=y -+CONFIG_RTC_CLASS=y -+# CONFIG_RTC_HCTOSYS is not set -+CONFIG_RTC_DRV_DS1307=m -+CONFIG_RTC_DRV_DS1374=m -+CONFIG_RTC_DRV_DS1672=m -+CONFIG_RTC_DRV_DS3232=m -+CONFIG_RTC_DRV_MAX6900=m -+CONFIG_RTC_DRV_RS5C372=m -+CONFIG_RTC_DRV_ISL1208=m -+CONFIG_RTC_DRV_ISL12022=m -+CONFIG_RTC_DRV_ISL12057=m -+CONFIG_RTC_DRV_X1205=m -+CONFIG_RTC_DRV_PCF2127=m -+CONFIG_RTC_DRV_PCF8523=m -+CONFIG_RTC_DRV_PCF8563=m -+CONFIG_RTC_DRV_PCF8583=m -+CONFIG_RTC_DRV_M41T80=m -+CONFIG_RTC_DRV_BQ32K=m -+CONFIG_RTC_DRV_S35390A=m -+CONFIG_RTC_DRV_FM3130=m -+CONFIG_RTC_DRV_RX8581=m -+CONFIG_RTC_DRV_RX8025=m -+CONFIG_RTC_DRV_EM3027=m -+CONFIG_RTC_DRV_RV3029C2=m -+CONFIG_RTC_DRV_M41T93=m -+CONFIG_RTC_DRV_M41T94=m -+CONFIG_RTC_DRV_DS1305=m -+CONFIG_RTC_DRV_DS1390=m -+CONFIG_RTC_DRV_MAX6902=m -+CONFIG_RTC_DRV_R9701=m -+CONFIG_RTC_DRV_RS5C348=m -+CONFIG_RTC_DRV_DS3234=m -+CONFIG_RTC_DRV_PCF2123=m -+CONFIG_RTC_DRV_RX4581=m -+CONFIG_DMADEVICES=y -+CONFIG_DMA_BCM2708=y -+CONFIG_UIO=m -+CONFIG_UIO_PDRV_GENIRQ=m -+CONFIG_STAGING=y -+CONFIG_PRISM2_USB=m -+CONFIG_R8712U=m -+CONFIG_R8188EU=m -+CONFIG_R8723AU=m -+CONFIG_VT6656=m -+CONFIG_SPEAKUP=m -+CONFIG_SPEAKUP_SYNTH_SOFT=m -+CONFIG_STAGING_MEDIA=y -+CONFIG_LIRC_STAGING=y -+CONFIG_LIRC_IMON=m -+CONFIG_LIRC_RPI=m -+CONFIG_LIRC_SASEM=m -+CONFIG_LIRC_SERIAL=m -+CONFIG_FB_TFT=m -+CONFIG_FB_TFT_AGM1264K_FL=m -+CONFIG_FB_TFT_BD663474=m -+CONFIG_FB_TFT_HX8340BN=m -+CONFIG_FB_TFT_HX8347D=m -+CONFIG_FB_TFT_HX8353D=m -+CONFIG_FB_TFT_ILI9163=m -+CONFIG_FB_TFT_ILI9320=m -+CONFIG_FB_TFT_ILI9325=m -+CONFIG_FB_TFT_ILI9340=m -+CONFIG_FB_TFT_ILI9341=m -+CONFIG_FB_TFT_ILI9481=m -+CONFIG_FB_TFT_ILI9486=m -+CONFIG_FB_TFT_PCD8544=m -+CONFIG_FB_TFT_RA8875=m -+CONFIG_FB_TFT_S6D02A1=m -+CONFIG_FB_TFT_S6D1121=m -+CONFIG_FB_TFT_SSD1289=m -+CONFIG_FB_TFT_SSD1306=m -+CONFIG_FB_TFT_SSD1331=m -+CONFIG_FB_TFT_SSD1351=m -+CONFIG_FB_TFT_ST7735R=m -+CONFIG_FB_TFT_TINYLCD=m -+CONFIG_FB_TFT_TLS8204=m -+CONFIG_FB_TFT_UC1701=m -+CONFIG_FB_TFT_UPD161704=m -+CONFIG_FB_TFT_WATTEROTT=m -+CONFIG_FB_FLEX=m -+CONFIG_FB_TFT_FBTFT_DEVICE=m -+CONFIG_MAILBOX=y -+CONFIG_BCM2835_MBOX=y -+# CONFIG_IOMMU_SUPPORT is not set -+CONFIG_EXTCON=m -+CONFIG_EXTCON_ARIZONA=m -+CONFIG_IIO=m -+CONFIG_IIO_BUFFER=y -+CONFIG_IIO_BUFFER_CB=y -+CONFIG_IIO_KFIFO_BUF=m -+CONFIG_MCP320X=m -+CONFIG_DHT11=m -+CONFIG_PWM_BCM2835=m -+CONFIG_RASPBERRYPI_FIRMWARE=y -+CONFIG_EXT4_FS=y -+CONFIG_EXT4_FS_POSIX_ACL=y -+CONFIG_EXT4_FS_SECURITY=y -+CONFIG_REISERFS_FS=m -+CONFIG_REISERFS_FS_XATTR=y -+CONFIG_REISERFS_FS_POSIX_ACL=y -+CONFIG_REISERFS_FS_SECURITY=y -+CONFIG_JFS_FS=m -+CONFIG_JFS_POSIX_ACL=y -+CONFIG_JFS_SECURITY=y -+CONFIG_JFS_STATISTICS=y -+CONFIG_XFS_FS=m -+CONFIG_XFS_QUOTA=y -+CONFIG_XFS_POSIX_ACL=y -+CONFIG_XFS_RT=y -+CONFIG_GFS2_FS=m -+CONFIG_OCFS2_FS=m -+CONFIG_BTRFS_FS=m -+CONFIG_BTRFS_FS_POSIX_ACL=y -+CONFIG_NILFS2_FS=m -+CONFIG_F2FS_FS=y -+CONFIG_FANOTIFY=y -+CONFIG_QFMT_V1=m -+CONFIG_QFMT_V2=m -+CONFIG_AUTOFS4_FS=y -+CONFIG_FUSE_FS=m -+CONFIG_CUSE=m -+CONFIG_OVERLAY_FS=m -+CONFIG_FSCACHE=y -+CONFIG_FSCACHE_STATS=y -+CONFIG_FSCACHE_HISTOGRAM=y -+CONFIG_CACHEFILES=y -+CONFIG_ISO9660_FS=m -+CONFIG_JOLIET=y -+CONFIG_ZISOFS=y -+CONFIG_UDF_FS=m -+CONFIG_MSDOS_FS=y -+CONFIG_VFAT_FS=y -+CONFIG_FAT_DEFAULT_IOCHARSET="ascii" -+CONFIG_NTFS_FS=m -+CONFIG_NTFS_RW=y -+CONFIG_TMPFS=y -+CONFIG_TMPFS_POSIX_ACL=y -+CONFIG_CONFIGFS_FS=y -+CONFIG_ECRYPT_FS=m -+CONFIG_HFS_FS=m -+CONFIG_HFSPLUS_FS=m -+CONFIG_JFFS2_FS=m -+CONFIG_JFFS2_SUMMARY=y -+CONFIG_UBIFS_FS=m -+CONFIG_SQUASHFS=m -+CONFIG_SQUASHFS_XATTR=y -+CONFIG_SQUASHFS_LZO=y -+CONFIG_SQUASHFS_XZ=y -+CONFIG_NFS_FS=y -+CONFIG_NFS_V3_ACL=y -+CONFIG_NFS_V4=y -+CONFIG_NFS_SWAP=y -+CONFIG_ROOT_NFS=y -+CONFIG_NFS_FSCACHE=y -+CONFIG_NFSD=m -+CONFIG_NFSD_V3_ACL=y -+CONFIG_NFSD_V4=y -+CONFIG_CIFS=m -+CONFIG_CIFS_WEAK_PW_HASH=y -+CONFIG_CIFS_UPCALL=y -+CONFIG_CIFS_XATTR=y -+CONFIG_CIFS_POSIX=y -+CONFIG_CIFS_ACL=y -+CONFIG_CIFS_DFS_UPCALL=y -+CONFIG_CIFS_SMB2=y -+CONFIG_CIFS_FSCACHE=y -+CONFIG_9P_FS=m -+CONFIG_9P_FS_POSIX_ACL=y -+CONFIG_NLS_DEFAULT="utf8" -+CONFIG_NLS_CODEPAGE_437=y -+CONFIG_NLS_CODEPAGE_737=m -+CONFIG_NLS_CODEPAGE_775=m -+CONFIG_NLS_CODEPAGE_850=m -+CONFIG_NLS_CODEPAGE_852=m -+CONFIG_NLS_CODEPAGE_855=m -+CONFIG_NLS_CODEPAGE_857=m -+CONFIG_NLS_CODEPAGE_860=m -+CONFIG_NLS_CODEPAGE_861=m -+CONFIG_NLS_CODEPAGE_862=m -+CONFIG_NLS_CODEPAGE_863=m -+CONFIG_NLS_CODEPAGE_864=m -+CONFIG_NLS_CODEPAGE_865=m -+CONFIG_NLS_CODEPAGE_866=m -+CONFIG_NLS_CODEPAGE_869=m -+CONFIG_NLS_CODEPAGE_936=m -+CONFIG_NLS_CODEPAGE_950=m -+CONFIG_NLS_CODEPAGE_932=m -+CONFIG_NLS_CODEPAGE_949=m -+CONFIG_NLS_CODEPAGE_874=m -+CONFIG_NLS_ISO8859_8=m -+CONFIG_NLS_CODEPAGE_1250=m -+CONFIG_NLS_CODEPAGE_1251=m -+CONFIG_NLS_ASCII=y -+CONFIG_NLS_ISO8859_1=m -+CONFIG_NLS_ISO8859_2=m -+CONFIG_NLS_ISO8859_3=m -+CONFIG_NLS_ISO8859_4=m -+CONFIG_NLS_ISO8859_5=m -+CONFIG_NLS_ISO8859_6=m -+CONFIG_NLS_ISO8859_7=m -+CONFIG_NLS_ISO8859_9=m -+CONFIG_NLS_ISO8859_13=m -+CONFIG_NLS_ISO8859_14=m -+CONFIG_NLS_ISO8859_15=m -+CONFIG_NLS_KOI8_R=m -+CONFIG_NLS_KOI8_U=m -+CONFIG_DLM=m -+CONFIG_PRINTK_TIME=y -+CONFIG_BOOT_PRINTK_DELAY=y -+CONFIG_DEBUG_MEMORY_INIT=y -+CONFIG_DETECT_HUNG_TASK=y -+CONFIG_TIMER_STATS=y -+# CONFIG_DEBUG_PREEMPT is not set -+CONFIG_IRQSOFF_TRACER=y -+CONFIG_SCHED_TRACER=y -+CONFIG_STACK_TRACER=y -+CONFIG_BLK_DEV_IO_TRACE=y -+# CONFIG_KPROBE_EVENT is not set -+CONFIG_FUNCTION_PROFILER=y -+CONFIG_KGDB=y -+CONFIG_KGDB_KDB=y -+CONFIG_KDB_KEYBOARD=y -+CONFIG_CRYPTO_USER=m -+CONFIG_CRYPTO_CBC=y -+CONFIG_CRYPTO_CTS=m -+CONFIG_CRYPTO_XTS=m -+CONFIG_CRYPTO_XCBC=m -+CONFIG_CRYPTO_TGR192=m -+CONFIG_CRYPTO_WP512=m -+CONFIG_CRYPTO_CAST5=m -+CONFIG_CRYPTO_DES=y -+# CONFIG_CRYPTO_ANSI_CPRNG is not set -+CONFIG_CRYPTO_USER_API_SKCIPHER=m -+# CONFIG_CRYPTO_HW is not set -+CONFIG_ARM_CRYPTO=y -+CONFIG_CRYPTO_SHA1_ARM_NEON=m -+CONFIG_CRYPTO_SHA512_ARM_NEON=m -+CONFIG_CRYPTO_AES_ARM_BS=m -+CONFIG_CRC_ITU_T=y -+CONFIG_LIBCRC32C=y -diff -Nur linux-4.1.13.orig/arch/arm/configs/bcm2835_defconfig linux-rpi/arch/arm/configs/bcm2835_defconfig ---- linux-4.1.13.orig/arch/arm/configs/bcm2835_defconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/arch/arm/configs/bcm2835_defconfig 2015-11-29 09:42:34.707444982 +0100 -@@ -1,105 +1,1075 @@ - # CONFIG_LOCALVERSION_AUTO is not set - CONFIG_SYSVIPC=y -+CONFIG_POSIX_MQUEUE=y - CONFIG_FHANDLE=y - CONFIG_NO_HZ=y - CONFIG_HIGH_RES_TIMERS=y - CONFIG_BSD_PROCESS_ACCT=y - CONFIG_BSD_PROCESS_ACCT_V3=y -+CONFIG_TASKSTATS=y -+CONFIG_TASK_DELAY_ACCT=y -+CONFIG_TASK_XACCT=y -+CONFIG_TASK_IO_ACCOUNTING=y -+CONFIG_IKCONFIG=m -+CONFIG_IKCONFIG_PROC=y - CONFIG_LOG_BUF_SHIFT=18 - CONFIG_CGROUP_FREEZER=y - CONFIG_CGROUP_DEVICE=y - CONFIG_CPUSETS=y - CONFIG_CGROUP_CPUACCT=y --CONFIG_RESOURCE_COUNTERS=y -+CONFIG_MEMCG=y - CONFIG_CGROUP_PERF=y - CONFIG_CFS_BANDWIDTH=y - CONFIG_RT_GROUP_SCHED=y -+CONFIG_BLK_CGROUP=y - CONFIG_NAMESPACES=y - CONFIG_SCHED_AUTOGROUP=y --CONFIG_RELAY=y - CONFIG_BLK_DEV_INITRD=y --CONFIG_RD_BZIP2=y --CONFIG_RD_LZMA=y --CONFIG_RD_XZ=y --CONFIG_RD_LZO=y - CONFIG_CC_OPTIMIZE_FOR_SIZE=y --CONFIG_KALLSYMS_ALL=y - CONFIG_EMBEDDED=y - # CONFIG_COMPAT_BRK is not set - CONFIG_PROFILING=y --CONFIG_OPROFILE=y -+CONFIG_OPROFILE=m -+CONFIG_KPROBES=y - CONFIG_JUMP_LABEL=y -+CONFIG_CC_STACKPROTECTOR_REGULAR=y -+CONFIG_MODULES=y -+CONFIG_MODULE_UNLOAD=y -+CONFIG_MODVERSIONS=y -+CONFIG_MODULE_SRCVERSION_ALL=y -+CONFIG_BLK_DEV_THROTTLING=y -+CONFIG_PARTITION_ADVANCED=y -+CONFIG_MAC_PARTITION=y -+CONFIG_CFQ_GROUP_IOSCHED=y - CONFIG_ARCH_MULTI_V6=y - # CONFIG_ARCH_MULTI_V7 is not set - CONFIG_ARCH_BCM=y - CONFIG_ARCH_BCM2835=y --CONFIG_PREEMPT_VOLUNTARY=y -+CONFIG_PREEMPT=y - CONFIG_AEABI=y -+CONFIG_OABI_COMPAT=y - CONFIG_KSM=y - CONFIG_CLEANCACHE=y -+CONFIG_FRONTSWAP=y -+CONFIG_CMA=y -+CONFIG_UACCESS_WITH_MEMCPY=y - CONFIG_SECCOMP=y --CONFIG_CC_STACKPROTECTOR=y -+CONFIG_ZBOOT_ROM_TEXT=0x0 -+CONFIG_ZBOOT_ROM_BSS=0x0 - CONFIG_KEXEC=y - CONFIG_CRASH_DUMP=y -+CONFIG_CPU_FREQ=y -+CONFIG_CPU_FREQ_STAT=m -+CONFIG_CPU_FREQ_STAT_DETAILS=y -+CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y -+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -+CONFIG_CPU_FREQ_GOV_USERSPACE=y -+CONFIG_CPU_FREQ_GOV_ONDEMAND=y -+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y - CONFIG_VFP=y - # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -+CONFIG_BINFMT_MISC=m - # CONFIG_SUSPEND is not set - CONFIG_NET=y - CONFIG_PACKET=y - CONFIG_UNIX=y -+CONFIG_XFRM_USER=y -+CONFIG_NET_KEY=m - CONFIG_INET=y -+CONFIG_IP_MULTICAST=y -+CONFIG_IP_ADVANCED_ROUTER=y -+CONFIG_IP_MULTIPLE_TABLES=y -+CONFIG_IP_ROUTE_MULTIPATH=y -+CONFIG_IP_ROUTE_VERBOSE=y -+CONFIG_IP_PNP=y -+CONFIG_IP_PNP_DHCP=y -+CONFIG_IP_PNP_RARP=y -+CONFIG_NET_IPIP=m -+CONFIG_NET_IPGRE_DEMUX=m -+CONFIG_NET_IPGRE=m -+CONFIG_IP_MROUTE=y -+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y -+CONFIG_IP_PIMSM_V1=y -+CONFIG_IP_PIMSM_V2=y -+CONFIG_SYN_COOKIES=y -+CONFIG_INET_AH=m -+CONFIG_INET_ESP=m -+CONFIG_INET_IPCOMP=m -+CONFIG_INET_XFRM_MODE_TRANSPORT=m -+CONFIG_INET_XFRM_MODE_TUNNEL=m -+CONFIG_INET_XFRM_MODE_BEET=m -+CONFIG_INET_LRO=m -+CONFIG_INET_DIAG=m -+CONFIG_INET6_AH=m -+CONFIG_INET6_ESP=m -+CONFIG_INET6_IPCOMP=m -+CONFIG_IPV6_TUNNEL=m -+CONFIG_IPV6_MULTIPLE_TABLES=y -+CONFIG_IPV6_MROUTE=y -+CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y -+CONFIG_IPV6_PIMSM_V2=y - CONFIG_NETWORK_SECMARK=y - CONFIG_NETFILTER=y --CONFIG_CFG80211=y --CONFIG_MAC80211=y -+CONFIG_NF_CONNTRACK=m -+CONFIG_NF_CONNTRACK_ZONES=y -+CONFIG_NF_CONNTRACK_EVENTS=y -+CONFIG_NF_CONNTRACK_TIMESTAMP=y -+CONFIG_NF_CT_PROTO_DCCP=m -+CONFIG_NF_CT_PROTO_UDPLITE=m -+CONFIG_NF_CONNTRACK_AMANDA=m -+CONFIG_NF_CONNTRACK_FTP=m -+CONFIG_NF_CONNTRACK_H323=m -+CONFIG_NF_CONNTRACK_IRC=m -+CONFIG_NF_CONNTRACK_NETBIOS_NS=m -+CONFIG_NF_CONNTRACK_SNMP=m -+CONFIG_NF_CONNTRACK_PPTP=m -+CONFIG_NF_CONNTRACK_SANE=m -+CONFIG_NF_CONNTRACK_SIP=m -+CONFIG_NF_CONNTRACK_TFTP=m -+CONFIG_NF_CT_NETLINK=m -+CONFIG_NETFILTER_XT_SET=m -+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m -+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m -+CONFIG_NETFILTER_XT_TARGET_DSCP=m -+CONFIG_NETFILTER_XT_TARGET_HMARK=m -+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m -+CONFIG_NETFILTER_XT_TARGET_LED=m -+CONFIG_NETFILTER_XT_TARGET_LOG=m -+CONFIG_NETFILTER_XT_TARGET_MARK=m -+CONFIG_NETFILTER_XT_TARGET_NFLOG=m -+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m -+CONFIG_NETFILTER_XT_TARGET_TEE=m -+CONFIG_NETFILTER_XT_TARGET_TPROXY=m -+CONFIG_NETFILTER_XT_TARGET_TRACE=m -+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m -+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m -+CONFIG_NETFILTER_XT_MATCH_BPF=m -+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m -+CONFIG_NETFILTER_XT_MATCH_COMMENT=m -+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m -+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m -+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -+CONFIG_NETFILTER_XT_MATCH_CPU=m -+CONFIG_NETFILTER_XT_MATCH_DCCP=m -+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m -+CONFIG_NETFILTER_XT_MATCH_DSCP=m -+CONFIG_NETFILTER_XT_MATCH_ESP=m -+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m -+CONFIG_NETFILTER_XT_MATCH_HELPER=m -+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m -+CONFIG_NETFILTER_XT_MATCH_IPVS=m -+CONFIG_NETFILTER_XT_MATCH_LENGTH=m -+CONFIG_NETFILTER_XT_MATCH_LIMIT=m -+CONFIG_NETFILTER_XT_MATCH_MAC=m -+CONFIG_NETFILTER_XT_MATCH_MARK=m -+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -+CONFIG_NETFILTER_XT_MATCH_NFACCT=m -+CONFIG_NETFILTER_XT_MATCH_OSF=m -+CONFIG_NETFILTER_XT_MATCH_OWNER=m -+CONFIG_NETFILTER_XT_MATCH_POLICY=m -+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m -+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -+CONFIG_NETFILTER_XT_MATCH_QUOTA=m -+CONFIG_NETFILTER_XT_MATCH_RATEEST=m -+CONFIG_NETFILTER_XT_MATCH_REALM=m -+CONFIG_NETFILTER_XT_MATCH_RECENT=m -+CONFIG_NETFILTER_XT_MATCH_SOCKET=m -+CONFIG_NETFILTER_XT_MATCH_STATE=m -+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -+CONFIG_NETFILTER_XT_MATCH_STRING=m -+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -+CONFIG_NETFILTER_XT_MATCH_TIME=m -+CONFIG_NETFILTER_XT_MATCH_U32=m -+CONFIG_IP_SET=m -+CONFIG_IP_SET_BITMAP_IP=m -+CONFIG_IP_SET_BITMAP_IPMAC=m -+CONFIG_IP_SET_BITMAP_PORT=m -+CONFIG_IP_SET_HASH_IP=m -+CONFIG_IP_SET_HASH_IPPORT=m -+CONFIG_IP_SET_HASH_IPPORTIP=m -+CONFIG_IP_SET_HASH_IPPORTNET=m -+CONFIG_IP_SET_HASH_NET=m -+CONFIG_IP_SET_HASH_NETPORT=m -+CONFIG_IP_SET_HASH_NETIFACE=m -+CONFIG_IP_SET_LIST_SET=m -+CONFIG_IP_VS=m -+CONFIG_IP_VS_PROTO_TCP=y -+CONFIG_IP_VS_PROTO_UDP=y -+CONFIG_IP_VS_PROTO_ESP=y -+CONFIG_IP_VS_PROTO_AH=y -+CONFIG_IP_VS_PROTO_SCTP=y -+CONFIG_IP_VS_RR=m -+CONFIG_IP_VS_WRR=m -+CONFIG_IP_VS_LC=m -+CONFIG_IP_VS_WLC=m -+CONFIG_IP_VS_LBLC=m -+CONFIG_IP_VS_LBLCR=m -+CONFIG_IP_VS_DH=m -+CONFIG_IP_VS_SH=m -+CONFIG_IP_VS_SED=m -+CONFIG_IP_VS_NQ=m -+CONFIG_IP_VS_FTP=m -+CONFIG_IP_VS_PE_SIP=m -+CONFIG_NF_CONNTRACK_IPV4=m -+CONFIG_IP_NF_IPTABLES=m -+CONFIG_IP_NF_MATCH_AH=m -+CONFIG_IP_NF_MATCH_ECN=m -+CONFIG_IP_NF_MATCH_TTL=m -+CONFIG_IP_NF_FILTER=m -+CONFIG_IP_NF_TARGET_REJECT=m -+CONFIG_IP_NF_NAT=m -+CONFIG_IP_NF_TARGET_MASQUERADE=m -+CONFIG_IP_NF_TARGET_NETMAP=m -+CONFIG_IP_NF_TARGET_REDIRECT=m -+CONFIG_IP_NF_MANGLE=m -+CONFIG_IP_NF_TARGET_CLUSTERIP=m -+CONFIG_IP_NF_TARGET_ECN=m -+CONFIG_IP_NF_TARGET_TTL=m -+CONFIG_IP_NF_RAW=m -+CONFIG_IP_NF_ARPTABLES=m -+CONFIG_IP_NF_ARPFILTER=m -+CONFIG_IP_NF_ARP_MANGLE=m -+CONFIG_NF_CONNTRACK_IPV6=m -+CONFIG_IP6_NF_IPTABLES=m -+CONFIG_IP6_NF_MATCH_AH=m -+CONFIG_IP6_NF_MATCH_EUI64=m -+CONFIG_IP6_NF_MATCH_FRAG=m -+CONFIG_IP6_NF_MATCH_OPTS=m -+CONFIG_IP6_NF_MATCH_HL=m -+CONFIG_IP6_NF_MATCH_IPV6HEADER=m -+CONFIG_IP6_NF_MATCH_MH=m -+CONFIG_IP6_NF_MATCH_RT=m -+CONFIG_IP6_NF_TARGET_HL=m -+CONFIG_IP6_NF_FILTER=m -+CONFIG_IP6_NF_TARGET_REJECT=m -+CONFIG_IP6_NF_MANGLE=m -+CONFIG_IP6_NF_RAW=m -+CONFIG_IP6_NF_NAT=m -+CONFIG_IP6_NF_TARGET_MASQUERADE=m -+CONFIG_IP6_NF_TARGET_NPT=m -+CONFIG_BRIDGE_NF_EBTABLES=m -+CONFIG_BRIDGE_EBT_BROUTE=m -+CONFIG_BRIDGE_EBT_T_FILTER=m -+CONFIG_BRIDGE_EBT_T_NAT=m -+CONFIG_BRIDGE_EBT_802_3=m -+CONFIG_BRIDGE_EBT_AMONG=m -+CONFIG_BRIDGE_EBT_ARP=m -+CONFIG_BRIDGE_EBT_IP=m -+CONFIG_BRIDGE_EBT_IP6=m -+CONFIG_BRIDGE_EBT_LIMIT=m -+CONFIG_BRIDGE_EBT_MARK=m -+CONFIG_BRIDGE_EBT_PKTTYPE=m -+CONFIG_BRIDGE_EBT_STP=m -+CONFIG_BRIDGE_EBT_VLAN=m -+CONFIG_BRIDGE_EBT_ARPREPLY=m -+CONFIG_BRIDGE_EBT_DNAT=m -+CONFIG_BRIDGE_EBT_MARK_T=m -+CONFIG_BRIDGE_EBT_REDIRECT=m -+CONFIG_BRIDGE_EBT_SNAT=m -+CONFIG_BRIDGE_EBT_LOG=m -+CONFIG_BRIDGE_EBT_NFLOG=m -+CONFIG_SCTP_COOKIE_HMAC_SHA1=y -+CONFIG_ATM=m -+CONFIG_L2TP=m -+CONFIG_L2TP_V3=y -+CONFIG_L2TP_IP=m -+CONFIG_L2TP_ETH=m -+CONFIG_BRIDGE=m -+CONFIG_VLAN_8021Q=m -+CONFIG_VLAN_8021Q_GVRP=y -+CONFIG_ATALK=m -+CONFIG_6LOWPAN=m -+CONFIG_NET_SCHED=y -+CONFIG_NET_SCH_CBQ=m -+CONFIG_NET_SCH_HTB=m -+CONFIG_NET_SCH_HFSC=m -+CONFIG_NET_SCH_PRIO=m -+CONFIG_NET_SCH_MULTIQ=m -+CONFIG_NET_SCH_RED=m -+CONFIG_NET_SCH_SFB=m -+CONFIG_NET_SCH_SFQ=m -+CONFIG_NET_SCH_TEQL=m -+CONFIG_NET_SCH_TBF=m -+CONFIG_NET_SCH_GRED=m -+CONFIG_NET_SCH_DSMARK=m -+CONFIG_NET_SCH_NETEM=m -+CONFIG_NET_SCH_DRR=m -+CONFIG_NET_SCH_MQPRIO=m -+CONFIG_NET_SCH_CHOKE=m -+CONFIG_NET_SCH_QFQ=m -+CONFIG_NET_SCH_CODEL=m -+CONFIG_NET_SCH_FQ_CODEL=m -+CONFIG_NET_SCH_INGRESS=m -+CONFIG_NET_SCH_PLUG=m -+CONFIG_NET_CLS_BASIC=m -+CONFIG_NET_CLS_TCINDEX=m -+CONFIG_NET_CLS_ROUTE4=m -+CONFIG_NET_CLS_FW=m -+CONFIG_NET_CLS_U32=m -+CONFIG_CLS_U32_MARK=y -+CONFIG_NET_CLS_RSVP=m -+CONFIG_NET_CLS_RSVP6=m -+CONFIG_NET_CLS_FLOW=m -+CONFIG_NET_CLS_CGROUP=m -+CONFIG_NET_EMATCH=y -+CONFIG_NET_EMATCH_CMP=m -+CONFIG_NET_EMATCH_NBYTE=m -+CONFIG_NET_EMATCH_U32=m -+CONFIG_NET_EMATCH_META=m -+CONFIG_NET_EMATCH_TEXT=m -+CONFIG_NET_EMATCH_IPSET=m -+CONFIG_NET_CLS_ACT=y -+CONFIG_NET_ACT_POLICE=m -+CONFIG_NET_ACT_GACT=m -+CONFIG_GACT_PROB=y -+CONFIG_NET_ACT_MIRRED=m -+CONFIG_NET_ACT_IPT=m -+CONFIG_NET_ACT_NAT=m -+CONFIG_NET_ACT_PEDIT=m -+CONFIG_NET_ACT_SIMP=m -+CONFIG_NET_ACT_SKBEDIT=m -+CONFIG_NET_ACT_CSUM=m -+CONFIG_BATMAN_ADV=m -+CONFIG_OPENVSWITCH=m -+CONFIG_NET_PKTGEN=m -+CONFIG_HAMRADIO=y -+CONFIG_AX25=m -+CONFIG_NETROM=m -+CONFIG_ROSE=m -+CONFIG_MKISS=m -+CONFIG_6PACK=m -+CONFIG_BPQETHER=m -+CONFIG_BAYCOM_SER_FDX=m -+CONFIG_BAYCOM_SER_HDX=m -+CONFIG_YAM=m -+CONFIG_CAN=m -+CONFIG_CAN_VCAN=m -+CONFIG_CAN_MCP251X=m -+CONFIG_IRDA=m -+CONFIG_IRLAN=m -+CONFIG_IRNET=m -+CONFIG_IRCOMM=m -+CONFIG_IRDA_ULTRA=y -+CONFIG_IRDA_CACHE_LAST_LSAP=y -+CONFIG_IRDA_FAST_RR=y -+CONFIG_IRTTY_SIR=m -+CONFIG_KINGSUN_DONGLE=m -+CONFIG_KSDAZZLE_DONGLE=m -+CONFIG_KS959_DONGLE=m -+CONFIG_USB_IRDA=m -+CONFIG_SIGMATEL_FIR=m -+CONFIG_MCS_FIR=m -+CONFIG_BT=m -+CONFIG_BT_RFCOMM=m -+CONFIG_BT_RFCOMM_TTY=y -+CONFIG_BT_BNEP=m -+CONFIG_BT_BNEP_MC_FILTER=y -+CONFIG_BT_BNEP_PROTO_FILTER=y -+CONFIG_BT_HIDP=m -+CONFIG_BT_6LOWPAN=m -+CONFIG_BT_HCIBTUSB=m -+CONFIG_BT_HCIBCM203X=m -+CONFIG_BT_HCIBPA10X=m -+CONFIG_BT_HCIBFUSB=m -+CONFIG_BT_HCIVHCI=m -+CONFIG_BT_MRVL=m -+CONFIG_BT_MRVL_SDIO=m -+CONFIG_BT_ATH3K=m -+CONFIG_BT_WILINK=m -+CONFIG_MAC80211=m -+CONFIG_MAC80211_MESH=y -+CONFIG_WIMAX=m -+CONFIG_RFKILL=m -+CONFIG_RFKILL_INPUT=y -+CONFIG_NET_9P=m -+CONFIG_NFC=m -+CONFIG_NFC_PN533=m - CONFIG_DEVTMPFS=y - CONFIG_DEVTMPFS_MOUNT=y - # CONFIG_STANDALONE is not set -+CONFIG_DMA_CMA=y -+CONFIG_CMA_SIZE_MBYTES=5 -+CONFIG_BLK_DEV_LOOP=y -+CONFIG_BLK_DEV_CRYPTOLOOP=m -+CONFIG_BLK_DEV_DRBD=m -+CONFIG_BLK_DEV_NBD=m -+CONFIG_BLK_DEV_RAM=y -+CONFIG_CDROM_PKTCDVD=m -+CONFIG_ATA_OVER_ETH=m -+CONFIG_EEPROM_AT24=m -+CONFIG_TI_ST=m - CONFIG_SCSI=y -+# CONFIG_SCSI_PROC_FS is not set - CONFIG_BLK_DEV_SD=y --CONFIG_SCSI_MULTI_LUN=y -+CONFIG_CHR_DEV_ST=m -+CONFIG_CHR_DEV_OSST=m -+CONFIG_BLK_DEV_SR=m -+CONFIG_CHR_DEV_SG=m - CONFIG_SCSI_CONSTANTS=y - CONFIG_SCSI_SCAN_ASYNC=y -+CONFIG_SCSI_ISCSI_ATTRS=y -+CONFIG_ISCSI_TCP=m -+CONFIG_ISCSI_BOOT_SYSFS=m -+CONFIG_MD=y -+CONFIG_MD_LINEAR=m -+CONFIG_MD_RAID0=m -+CONFIG_BLK_DEV_DM=m -+CONFIG_DM_CRYPT=m -+CONFIG_DM_SNAPSHOT=m -+CONFIG_DM_MIRROR=m -+CONFIG_DM_LOG_USERSPACE=m -+CONFIG_DM_RAID=m -+CONFIG_DM_ZERO=m -+CONFIG_DM_DELAY=m - CONFIG_NETDEVICES=y -+CONFIG_BONDING=m -+CONFIG_DUMMY=m -+CONFIG_IFB=m -+CONFIG_MACVLAN=m -+CONFIG_NETCONSOLE=m -+CONFIG_TUN=m -+CONFIG_VETH=m -+CONFIG_ENC28J60=m -+CONFIG_MDIO_BITBANG=m -+CONFIG_PPP=m -+CONFIG_PPP_BSDCOMP=m -+CONFIG_PPP_DEFLATE=m -+CONFIG_PPP_FILTER=y -+CONFIG_PPP_MPPE=m -+CONFIG_PPP_MULTILINK=y -+CONFIG_PPPOATM=m -+CONFIG_PPPOE=m -+CONFIG_PPPOL2TP=m -+CONFIG_PPP_ASYNC=m -+CONFIG_PPP_SYNC_TTY=m -+CONFIG_SLIP=m -+CONFIG_SLIP_COMPRESSED=y -+CONFIG_SLIP_SMART=y -+CONFIG_USB_CATC=m -+CONFIG_USB_KAWETH=m -+CONFIG_USB_PEGASUS=m -+CONFIG_USB_RTL8150=m -+CONFIG_USB_RTL8152=m - CONFIG_USB_USBNET=y -+CONFIG_USB_NET_AX8817X=m -+CONFIG_USB_NET_AX88179_178A=m -+CONFIG_USB_NET_CDCETHER=m -+CONFIG_USB_NET_CDC_EEM=m -+CONFIG_USB_NET_CDC_NCM=m -+CONFIG_USB_NET_HUAWEI_CDC_NCM=m -+CONFIG_USB_NET_CDC_MBIM=m -+CONFIG_USB_NET_DM9601=m -+CONFIG_USB_NET_SR9700=m -+CONFIG_USB_NET_SR9800=m -+CONFIG_USB_NET_SMSC75XX=m - CONFIG_USB_NET_SMSC95XX=y --CONFIG_ZD1211RW=y --CONFIG_INPUT_EVDEV=y -+CONFIG_USB_NET_GL620A=m -+CONFIG_USB_NET_NET1080=m -+CONFIG_USB_NET_PLUSB=m -+CONFIG_USB_NET_MCS7830=m -+CONFIG_USB_NET_CDC_SUBSET=m -+CONFIG_USB_ALI_M5632=y -+CONFIG_USB_AN2720=y -+CONFIG_USB_EPSON2888=y -+CONFIG_USB_KC2190=y -+CONFIG_USB_NET_ZAURUS=m -+CONFIG_USB_NET_CX82310_ETH=m -+CONFIG_USB_NET_KALMIA=m -+CONFIG_USB_NET_QMI_WWAN=m -+CONFIG_USB_HSO=m -+CONFIG_USB_NET_INT51X1=m -+CONFIG_USB_IPHETH=m -+CONFIG_USB_SIERRA_NET=m -+CONFIG_USB_VL600=m -+CONFIG_LIBERTAS_THINFIRM=m -+CONFIG_LIBERTAS_THINFIRM_USB=m -+CONFIG_AT76C50X_USB=m -+CONFIG_USB_ZD1201=m -+CONFIG_USB_NET_RNDIS_WLAN=m -+CONFIG_RTL8187=m -+CONFIG_MAC80211_HWSIM=m -+CONFIG_ATH_CARDS=m -+CONFIG_ATH9K=m -+CONFIG_ATH9K_HTC=m -+CONFIG_CARL9170=m -+CONFIG_ATH6KL=m -+CONFIG_ATH6KL_USB=m -+CONFIG_AR5523=m -+CONFIG_B43=m -+# CONFIG_B43_PHY_N is not set -+CONFIG_B43LEGACY=m -+CONFIG_BRCMFMAC=m -+CONFIG_BRCMFMAC_USB=y -+CONFIG_HOSTAP=m -+CONFIG_LIBERTAS=m -+CONFIG_LIBERTAS_USB=m -+CONFIG_LIBERTAS_SDIO=m -+CONFIG_P54_COMMON=m -+CONFIG_P54_USB=m -+CONFIG_RT2X00=m -+CONFIG_RT2500USB=m -+CONFIG_RT73USB=m -+CONFIG_RT2800USB=m -+CONFIG_RT2800USB_RT3573=y -+CONFIG_RT2800USB_RT53XX=y -+CONFIG_RT2800USB_RT55XX=y -+CONFIG_RT2800USB_UNKNOWN=y -+CONFIG_RTL8192CU=m -+CONFIG_ZD1211RW=m -+CONFIG_MWIFIEX=m -+CONFIG_MWIFIEX_SDIO=m -+CONFIG_WIMAX_I2400M_USB=m -+CONFIG_INPUT_POLLDEV=m -+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -+CONFIG_INPUT_JOYDEV=m -+CONFIG_INPUT_EVDEV=m -+# CONFIG_KEYBOARD_ATKBD is not set -+CONFIG_KEYBOARD_GPIO=m -+# CONFIG_INPUT_MOUSE is not set -+CONFIG_INPUT_JOYSTICK=y -+CONFIG_JOYSTICK_IFORCE=m -+CONFIG_JOYSTICK_IFORCE_USB=y -+CONFIG_JOYSTICK_XPAD=m -+CONFIG_JOYSTICK_XPAD_FF=y -+CONFIG_INPUT_TOUCHSCREEN=y -+CONFIG_TOUCHSCREEN_ADS7846=m -+CONFIG_TOUCHSCREEN_EGALAX=m -+CONFIG_TOUCHSCREEN_USB_COMPOSITE=m -+CONFIG_TOUCHSCREEN_STMPE=m -+CONFIG_INPUT_MISC=y -+CONFIG_INPUT_AD714X=m -+CONFIG_INPUT_ATI_REMOTE2=m -+CONFIG_INPUT_KEYSPAN_REMOTE=m -+CONFIG_INPUT_POWERMATE=m -+CONFIG_INPUT_YEALINK=m -+CONFIG_INPUT_CM109=m -+CONFIG_INPUT_UINPUT=m -+CONFIG_INPUT_GPIO_ROTARY_ENCODER=m -+CONFIG_INPUT_ADXL34X=m -+CONFIG_INPUT_CMA3000=m -+CONFIG_SERIO=m -+CONFIG_SERIO_RAW=m -+CONFIG_GAMEPORT=m -+CONFIG_GAMEPORT_NS558=m -+CONFIG_GAMEPORT_L4=m -+CONFIG_DEVPTS_MULTIPLE_INSTANCES=y - # CONFIG_LEGACY_PTYS is not set - # CONFIG_DEVKMEM is not set - CONFIG_SERIAL_AMBA_PL011=y - CONFIG_SERIAL_AMBA_PL011_CONSOLE=y - CONFIG_TTY_PRINTK=y -+CONFIG_HW_RANDOM=y -+CONFIG_HW_RANDOM_BCM2835=m -+CONFIG_RAW_DRIVER=y -+CONFIG_BRCM_CHAR_DRIVERS=y -+CONFIG_BCM_VC_CMA=y -+CONFIG_BCM_VCIO=y -+CONFIG_BCM_VC_SM=y - CONFIG_I2C=y --CONFIG_I2C_CHARDEV=y -+CONFIG_I2C_CHARDEV=m - CONFIG_I2C_BCM2835=y - CONFIG_SPI=y --CONFIG_SPI_BCM2835=y -+CONFIG_SPI_BCM2835=m -+CONFIG_SPI_SPIDEV=y -+CONFIG_PPS=m -+CONFIG_PPS_CLIENT_LDISC=m -+CONFIG_PPS_CLIENT_GPIO=m - CONFIG_GPIO_SYSFS=y -+CONFIG_GPIO_ARIZONA=m -+CONFIG_GPIO_STMPE=y -+CONFIG_W1=m -+CONFIG_W1_MASTER_DS2490=m -+CONFIG_W1_MASTER_DS2482=m -+CONFIG_W1_MASTER_DS1WM=m -+CONFIG_W1_MASTER_GPIO=m -+CONFIG_W1_SLAVE_THERM=m -+CONFIG_W1_SLAVE_SMEM=m -+CONFIG_W1_SLAVE_DS2408=m -+CONFIG_W1_SLAVE_DS2413=m -+CONFIG_W1_SLAVE_DS2406=m -+CONFIG_W1_SLAVE_DS2423=m -+CONFIG_W1_SLAVE_DS2431=m -+CONFIG_W1_SLAVE_DS2433=m -+CONFIG_W1_SLAVE_DS2760=m -+CONFIG_W1_SLAVE_DS2780=m -+CONFIG_W1_SLAVE_DS2781=m -+CONFIG_W1_SLAVE_DS28E04=m -+CONFIG_W1_SLAVE_BQ27000=m -+CONFIG_BATTERY_DS2760=m - # CONFIG_HWMON is not set -+CONFIG_THERMAL=y -+CONFIG_THERMAL_BCM2835=y -+CONFIG_WATCHDOG=y -+CONFIG_BCM2835_WDT=y -+CONFIG_UCB1400_CORE=m -+CONFIG_MFD_STMPE=y -+CONFIG_STMPE_SPI=y -+CONFIG_MFD_ARIZONA_I2C=m -+CONFIG_MFD_ARIZONA_SPI=m -+CONFIG_MFD_WM5102=y -+CONFIG_MEDIA_SUPPORT=m -+CONFIG_MEDIA_CAMERA_SUPPORT=y -+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y -+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y -+CONFIG_MEDIA_RADIO_SUPPORT=y -+CONFIG_MEDIA_RC_SUPPORT=y -+CONFIG_MEDIA_CONTROLLER=y -+CONFIG_LIRC=m -+CONFIG_RC_DEVICES=y -+CONFIG_RC_ATI_REMOTE=m -+CONFIG_IR_IMON=m -+CONFIG_IR_MCEUSB=m -+CONFIG_IR_REDRAT3=m -+CONFIG_IR_STREAMZAP=m -+CONFIG_IR_IGUANA=m -+CONFIG_IR_TTUSBIR=m -+CONFIG_RC_LOOPBACK=m -+CONFIG_IR_GPIO_CIR=m -+CONFIG_MEDIA_USB_SUPPORT=y -+CONFIG_USB_VIDEO_CLASS=m -+CONFIG_USB_M5602=m -+CONFIG_USB_STV06XX=m -+CONFIG_USB_GL860=m -+CONFIG_USB_GSPCA_BENQ=m -+CONFIG_USB_GSPCA_CONEX=m -+CONFIG_USB_GSPCA_CPIA1=m -+CONFIG_USB_GSPCA_DTCS033=m -+CONFIG_USB_GSPCA_ETOMS=m -+CONFIG_USB_GSPCA_FINEPIX=m -+CONFIG_USB_GSPCA_JEILINJ=m -+CONFIG_USB_GSPCA_JL2005BCD=m -+CONFIG_USB_GSPCA_KINECT=m -+CONFIG_USB_GSPCA_KONICA=m -+CONFIG_USB_GSPCA_MARS=m -+CONFIG_USB_GSPCA_MR97310A=m -+CONFIG_USB_GSPCA_NW80X=m -+CONFIG_USB_GSPCA_OV519=m -+CONFIG_USB_GSPCA_OV534=m -+CONFIG_USB_GSPCA_OV534_9=m -+CONFIG_USB_GSPCA_PAC207=m -+CONFIG_USB_GSPCA_PAC7302=m -+CONFIG_USB_GSPCA_PAC7311=m -+CONFIG_USB_GSPCA_SE401=m -+CONFIG_USB_GSPCA_SN9C2028=m -+CONFIG_USB_GSPCA_SN9C20X=m -+CONFIG_USB_GSPCA_SONIXB=m -+CONFIG_USB_GSPCA_SONIXJ=m -+CONFIG_USB_GSPCA_SPCA500=m -+CONFIG_USB_GSPCA_SPCA501=m -+CONFIG_USB_GSPCA_SPCA505=m -+CONFIG_USB_GSPCA_SPCA506=m -+CONFIG_USB_GSPCA_SPCA508=m -+CONFIG_USB_GSPCA_SPCA561=m -+CONFIG_USB_GSPCA_SPCA1528=m -+CONFIG_USB_GSPCA_SQ905=m -+CONFIG_USB_GSPCA_SQ905C=m -+CONFIG_USB_GSPCA_SQ930X=m -+CONFIG_USB_GSPCA_STK014=m -+CONFIG_USB_GSPCA_STK1135=m -+CONFIG_USB_GSPCA_STV0680=m -+CONFIG_USB_GSPCA_SUNPLUS=m -+CONFIG_USB_GSPCA_T613=m -+CONFIG_USB_GSPCA_TOPRO=m -+CONFIG_USB_GSPCA_TV8532=m -+CONFIG_USB_GSPCA_VC032X=m -+CONFIG_USB_GSPCA_VICAM=m -+CONFIG_USB_GSPCA_XIRLINK_CIT=m -+CONFIG_USB_GSPCA_ZC3XX=m -+CONFIG_USB_PWC=m -+CONFIG_VIDEO_CPIA2=m -+CONFIG_USB_ZR364XX=m -+CONFIG_USB_STKWEBCAM=m -+CONFIG_USB_S2255=m -+CONFIG_VIDEO_USBTV=m -+CONFIG_VIDEO_PVRUSB2=m -+CONFIG_VIDEO_HDPVR=m -+CONFIG_VIDEO_USBVISION=m -+CONFIG_VIDEO_STK1160_COMMON=m -+CONFIG_VIDEO_STK1160_AC97=y -+CONFIG_VIDEO_GO7007=m -+CONFIG_VIDEO_GO7007_USB=m -+CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m -+CONFIG_VIDEO_AU0828=m -+CONFIG_VIDEO_AU0828_RC=y -+CONFIG_VIDEO_CX231XX=m -+CONFIG_VIDEO_CX231XX_ALSA=m -+CONFIG_VIDEO_CX231XX_DVB=m -+CONFIG_VIDEO_TM6000=m -+CONFIG_VIDEO_TM6000_ALSA=m -+CONFIG_VIDEO_TM6000_DVB=m -+CONFIG_DVB_USB=m -+CONFIG_DVB_USB_A800=m -+CONFIG_DVB_USB_DIBUSB_MB=m -+CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y -+CONFIG_DVB_USB_DIBUSB_MC=m -+CONFIG_DVB_USB_DIB0700=m -+CONFIG_DVB_USB_UMT_010=m -+CONFIG_DVB_USB_CXUSB=m -+CONFIG_DVB_USB_M920X=m -+CONFIG_DVB_USB_DIGITV=m -+CONFIG_DVB_USB_VP7045=m -+CONFIG_DVB_USB_VP702X=m -+CONFIG_DVB_USB_GP8PSK=m -+CONFIG_DVB_USB_NOVA_T_USB2=m -+CONFIG_DVB_USB_TTUSB2=m -+CONFIG_DVB_USB_DTT200U=m -+CONFIG_DVB_USB_OPERA1=m -+CONFIG_DVB_USB_AF9005=m -+CONFIG_DVB_USB_AF9005_REMOTE=m -+CONFIG_DVB_USB_PCTV452E=m -+CONFIG_DVB_USB_DW2102=m -+CONFIG_DVB_USB_CINERGY_T2=m -+CONFIG_DVB_USB_DTV5100=m -+CONFIG_DVB_USB_FRIIO=m -+CONFIG_DVB_USB_AZ6027=m -+CONFIG_DVB_USB_TECHNISAT_USB2=m -+CONFIG_DVB_USB_V2=m -+CONFIG_DVB_USB_AF9015=m -+CONFIG_DVB_USB_AF9035=m -+CONFIG_DVB_USB_ANYSEE=m -+CONFIG_DVB_USB_AU6610=m -+CONFIG_DVB_USB_AZ6007=m -+CONFIG_DVB_USB_CE6230=m -+CONFIG_DVB_USB_EC168=m -+CONFIG_DVB_USB_GL861=m -+CONFIG_DVB_USB_LME2510=m -+CONFIG_DVB_USB_MXL111SF=m -+CONFIG_DVB_USB_RTL28XXU=m -+CONFIG_DVB_USB_DVBSKY=m -+CONFIG_SMS_USB_DRV=m -+CONFIG_DVB_B2C2_FLEXCOP_USB=m -+CONFIG_DVB_AS102=m -+CONFIG_VIDEO_EM28XX=m -+CONFIG_VIDEO_EM28XX_V4L2=m -+CONFIG_VIDEO_EM28XX_ALSA=m -+CONFIG_VIDEO_EM28XX_DVB=m -+CONFIG_V4L_PLATFORM_DRIVERS=y -+CONFIG_VIDEO_BCM2835=y -+CONFIG_VIDEO_BCM2835_MMAL=m -+CONFIG_RADIO_SI470X=y -+CONFIG_USB_SI470X=m -+CONFIG_I2C_SI470X=m -+CONFIG_RADIO_SI4713=m -+CONFIG_I2C_SI4713=m -+CONFIG_USB_MR800=m -+CONFIG_USB_DSBR=m -+CONFIG_RADIO_SHARK=m -+CONFIG_RADIO_SHARK2=m -+CONFIG_USB_KEENE=m -+CONFIG_USB_MA901=m -+CONFIG_RADIO_TEA5764=m -+CONFIG_RADIO_SAA7706H=m -+CONFIG_RADIO_TEF6862=m -+CONFIG_RADIO_WL1273=m -+CONFIG_RADIO_WL128X=m -+# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set -+CONFIG_VIDEO_UDA1342=m -+CONFIG_VIDEO_SONY_BTF_MPX=m -+CONFIG_VIDEO_TVP5150=m -+CONFIG_VIDEO_TW2804=m -+CONFIG_VIDEO_TW9903=m -+CONFIG_VIDEO_TW9906=m -+CONFIG_VIDEO_OV7640=m -+CONFIG_VIDEO_MT9V011=m - CONFIG_FB=y --CONFIG_FB_SIMPLE=y -+CONFIG_FB_BCM2708=y -+CONFIG_FB_SSD1307=m -+# CONFIG_BACKLIGHT_GENERIC is not set -+CONFIG_BACKLIGHT_GPIO=m - CONFIG_FRAMEBUFFER_CONSOLE=y - CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -+CONFIG_LOGO=y -+# CONFIG_LOGO_LINUX_MONO is not set -+# CONFIG_LOGO_LINUX_VGA16 is not set -+CONFIG_SOUND=y -+CONFIG_SND=m -+CONFIG_SND_SEQUENCER=m -+CONFIG_SND_SEQ_DUMMY=m -+CONFIG_SND_MIXER_OSS=m -+CONFIG_SND_PCM_OSS=m -+CONFIG_SND_SEQUENCER_OSS=y -+CONFIG_SND_HRTIMER=m -+CONFIG_SND_DUMMY=m -+CONFIG_SND_ALOOP=m -+CONFIG_SND_VIRMIDI=m -+CONFIG_SND_MTPAV=m -+CONFIG_SND_SERIAL_U16550=m -+CONFIG_SND_MPU401=m -+CONFIG_SND_BCM2835=m -+CONFIG_SND_USB_AUDIO=m -+CONFIG_SND_USB_UA101=m -+CONFIG_SND_USB_CAIAQ=m -+CONFIG_SND_USB_CAIAQ_INPUT=y -+CONFIG_SND_USB_6FIRE=m -+CONFIG_SND_SOC=m -+CONFIG_SND_BCM2835_SOC_I2S=m -+CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m -+CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m -+CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m -+CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m -+CONFIG_SND_BCM2708_SOC_RPI_DAC=m -+CONFIG_SND_BCM2708_SOC_RPI_PROTO=m -+CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m -+CONFIG_SND_SIMPLE_CARD=m -+CONFIG_SOUND_PRIME=m -+CONFIG_HIDRAW=y -+CONFIG_HID_A4TECH=m -+CONFIG_HID_ACRUX=m -+CONFIG_HID_APPLE=m -+CONFIG_HID_BELKIN=m -+CONFIG_HID_CHERRY=m -+CONFIG_HID_CHICONY=m -+CONFIG_HID_CYPRESS=m -+CONFIG_HID_DRAGONRISE=m -+CONFIG_HID_EMS_FF=m -+CONFIG_HID_ELECOM=m -+CONFIG_HID_ELO=m -+CONFIG_HID_EZKEY=m -+CONFIG_HID_HOLTEK=m -+CONFIG_HID_KEYTOUCH=m -+CONFIG_HID_KYE=m -+CONFIG_HID_UCLOGIC=m -+CONFIG_HID_WALTOP=m -+CONFIG_HID_GYRATION=m -+CONFIG_HID_TWINHAN=m -+CONFIG_HID_KENSINGTON=m -+CONFIG_HID_LCPOWER=m -+CONFIG_HID_LOGITECH=m -+CONFIG_HID_MAGICMOUSE=m -+CONFIG_HID_MICROSOFT=m -+CONFIG_HID_MONTEREY=m -+CONFIG_HID_MULTITOUCH=m -+CONFIG_HID_NTRIG=m -+CONFIG_HID_ORTEK=m -+CONFIG_HID_PANTHERLORD=m -+CONFIG_HID_PETALYNX=m -+CONFIG_HID_PICOLCD=m -+CONFIG_HID_ROCCAT=m -+CONFIG_HID_SAMSUNG=m -+CONFIG_HID_SONY=m -+CONFIG_HID_SPEEDLINK=m -+CONFIG_HID_SUNPLUS=m -+CONFIG_HID_GREENASIA=m -+CONFIG_HID_SMARTJOYPLUS=m -+CONFIG_HID_TOPSEED=m -+CONFIG_HID_THINGM=m -+CONFIG_HID_THRUSTMASTER=m -+CONFIG_HID_WACOM=m -+CONFIG_HID_WIIMOTE=m -+CONFIG_HID_XINMO=m -+CONFIG_HID_ZEROPLUS=m -+CONFIG_HID_ZYDACRON=m -+CONFIG_HID_PID=y -+CONFIG_USB_HIDDEV=y - CONFIG_USB=y -+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -+CONFIG_USB_MON=m -+CONFIG_USB_DWCOTG=y -+CONFIG_USB_PRINTER=m - CONFIG_USB_STORAGE=y -+CONFIG_USB_STORAGE_REALTEK=m -+CONFIG_USB_STORAGE_DATAFAB=m -+CONFIG_USB_STORAGE_FREECOM=m -+CONFIG_USB_STORAGE_ISD200=m -+CONFIG_USB_STORAGE_USBAT=m -+CONFIG_USB_STORAGE_SDDR09=m -+CONFIG_USB_STORAGE_SDDR55=m -+CONFIG_USB_STORAGE_JUMPSHOT=m -+CONFIG_USB_STORAGE_ALAUDA=m -+CONFIG_USB_STORAGE_ONETOUCH=m -+CONFIG_USB_STORAGE_KARMA=m -+CONFIG_USB_STORAGE_CYPRESS_ATACB=m -+CONFIG_USB_STORAGE_ENE_UB6250=m -+CONFIG_USB_MDC800=m -+CONFIG_USB_MICROTEK=m -+CONFIG_USBIP_CORE=m -+CONFIG_USBIP_VHCI_HCD=m -+CONFIG_USBIP_HOST=m -+CONFIG_USB_DWC2=y -+CONFIG_USB_SERIAL=m -+CONFIG_USB_SERIAL_GENERIC=y -+CONFIG_USB_SERIAL_AIRCABLE=m -+CONFIG_USB_SERIAL_ARK3116=m -+CONFIG_USB_SERIAL_BELKIN=m -+CONFIG_USB_SERIAL_CH341=m -+CONFIG_USB_SERIAL_WHITEHEAT=m -+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m -+CONFIG_USB_SERIAL_CP210X=m -+CONFIG_USB_SERIAL_CYPRESS_M8=m -+CONFIG_USB_SERIAL_EMPEG=m -+CONFIG_USB_SERIAL_FTDI_SIO=m -+CONFIG_USB_SERIAL_VISOR=m -+CONFIG_USB_SERIAL_IPAQ=m -+CONFIG_USB_SERIAL_IR=m -+CONFIG_USB_SERIAL_EDGEPORT=m -+CONFIG_USB_SERIAL_EDGEPORT_TI=m -+CONFIG_USB_SERIAL_F81232=m -+CONFIG_USB_SERIAL_GARMIN=m -+CONFIG_USB_SERIAL_IPW=m -+CONFIG_USB_SERIAL_IUU=m -+CONFIG_USB_SERIAL_KEYSPAN_PDA=m -+CONFIG_USB_SERIAL_KEYSPAN=m -+CONFIG_USB_SERIAL_KLSI=m -+CONFIG_USB_SERIAL_KOBIL_SCT=m -+CONFIG_USB_SERIAL_MCT_U232=m -+CONFIG_USB_SERIAL_METRO=m -+CONFIG_USB_SERIAL_MOS7720=m -+CONFIG_USB_SERIAL_MOS7840=m -+CONFIG_USB_SERIAL_NAVMAN=m -+CONFIG_USB_SERIAL_PL2303=m -+CONFIG_USB_SERIAL_OTI6858=m -+CONFIG_USB_SERIAL_QCAUX=m -+CONFIG_USB_SERIAL_QUALCOMM=m -+CONFIG_USB_SERIAL_SPCP8X5=m -+CONFIG_USB_SERIAL_SAFE=m -+CONFIG_USB_SERIAL_SIERRAWIRELESS=m -+CONFIG_USB_SERIAL_SYMBOL=m -+CONFIG_USB_SERIAL_TI=m -+CONFIG_USB_SERIAL_CYBERJACK=m -+CONFIG_USB_SERIAL_XIRCOM=m -+CONFIG_USB_SERIAL_OPTION=m -+CONFIG_USB_SERIAL_OMNINET=m -+CONFIG_USB_SERIAL_OPTICON=m -+CONFIG_USB_SERIAL_XSENS_MT=m -+CONFIG_USB_SERIAL_WISHBONE=m -+CONFIG_USB_SERIAL_SSU100=m -+CONFIG_USB_SERIAL_QT2=m -+CONFIG_USB_SERIAL_DEBUG=m -+CONFIG_USB_EMI62=m -+CONFIG_USB_EMI26=m -+CONFIG_USB_ADUTUX=m -+CONFIG_USB_SEVSEG=m -+CONFIG_USB_RIO500=m -+CONFIG_USB_LEGOTOWER=m -+CONFIG_USB_LCD=m -+CONFIG_USB_LED=m -+CONFIG_USB_CYPRESS_CY7C63=m -+CONFIG_USB_CYTHERM=m -+CONFIG_USB_IDMOUSE=m -+CONFIG_USB_FTDI_ELAN=m -+CONFIG_USB_APPLEDISPLAY=m -+CONFIG_USB_LD=m -+CONFIG_USB_TRANCEVIBRATOR=m -+CONFIG_USB_IOWARRIOR=m -+CONFIG_USB_TEST=m -+CONFIG_USB_ISIGHTFW=m -+CONFIG_USB_YUREX=m -+CONFIG_USB_ATM=m -+CONFIG_USB_SPEEDTOUCH=m -+CONFIG_USB_CXACRU=m -+CONFIG_USB_UEAGLEATM=m -+CONFIG_USB_XUSBATM=m - CONFIG_MMC=y -+CONFIG_MMC_BLOCK_MINORS=32 -+CONFIG_MMC_BCM2835=y -+CONFIG_MMC_BCM2835_DMA=y -+CONFIG_MMC_BCM2835_SDHOST=y - CONFIG_MMC_SDHCI=y - CONFIG_MMC_SDHCI_PLTFM=y - CONFIG_MMC_SDHCI_BCM2835=y -+CONFIG_MMC_SPI=m -+CONFIG_LEDS_CLASS=y - CONFIG_LEDS_GPIO=y - CONFIG_LEDS_TRIGGER_TIMER=y - CONFIG_LEDS_TRIGGER_ONESHOT=y - CONFIG_LEDS_TRIGGER_HEARTBEAT=y -+CONFIG_LEDS_TRIGGER_BACKLIGHT=y - CONFIG_LEDS_TRIGGER_CPU=y - CONFIG_LEDS_TRIGGER_GPIO=y - CONFIG_LEDS_TRIGGER_DEFAULT_ON=y --CONFIG_LEDS_TRIGGER_TRANSIENT=y --CONFIG_LEDS_TRIGGER_CAMERA=y -+CONFIG_LEDS_TRIGGER_TRANSIENT=m -+CONFIG_LEDS_TRIGGER_CAMERA=m -+CONFIG_LEDS_TRIGGER_INPUT=y -+CONFIG_RTC_CLASS=y -+# CONFIG_RTC_HCTOSYS is not set -+CONFIG_RTC_DRV_DS1307=m -+CONFIG_RTC_DRV_DS1374=m -+CONFIG_RTC_DRV_DS1672=m -+CONFIG_RTC_DRV_DS3232=m -+CONFIG_RTC_DRV_MAX6900=m -+CONFIG_RTC_DRV_RS5C372=m -+CONFIG_RTC_DRV_ISL1208=m -+CONFIG_RTC_DRV_ISL12022=m -+CONFIG_RTC_DRV_ISL12057=m -+CONFIG_RTC_DRV_X1205=m -+CONFIG_RTC_DRV_PCF2127=m -+CONFIG_RTC_DRV_PCF8523=m -+CONFIG_RTC_DRV_PCF8563=m -+CONFIG_RTC_DRV_PCF8583=m -+CONFIG_RTC_DRV_M41T80=m -+CONFIG_RTC_DRV_BQ32K=m -+CONFIG_RTC_DRV_S35390A=m -+CONFIG_RTC_DRV_FM3130=m -+CONFIG_RTC_DRV_RX8581=m -+CONFIG_RTC_DRV_RX8025=m -+CONFIG_RTC_DRV_EM3027=m -+CONFIG_RTC_DRV_RV3029C2=m -+CONFIG_RTC_DRV_M41T93=m -+CONFIG_RTC_DRV_M41T94=m -+CONFIG_RTC_DRV_DS1305=m -+CONFIG_RTC_DRV_DS1390=m -+CONFIG_RTC_DRV_MAX6902=m -+CONFIG_RTC_DRV_R9701=m -+CONFIG_RTC_DRV_RS5C348=m -+CONFIG_RTC_DRV_DS3234=m -+CONFIG_RTC_DRV_PCF2123=m -+CONFIG_RTC_DRV_RX4581=m -+CONFIG_DMADEVICES=y -+CONFIG_DMA_BCM2708=y -+CONFIG_UIO=m -+CONFIG_UIO_PDRV_GENIRQ=m - CONFIG_STAGING=y --CONFIG_USB_DWC2=y --CONFIG_USB_DWC2_HOST=y -+CONFIG_PRISM2_USB=m -+CONFIG_R8712U=m -+CONFIG_R8188EU=m -+CONFIG_R8723AU=m -+CONFIG_VT6656=m -+CONFIG_SPEAKUP=m -+CONFIG_SPEAKUP_SYNTH_SOFT=m -+CONFIG_STAGING_MEDIA=y -+CONFIG_LIRC_STAGING=y -+CONFIG_LIRC_IMON=m -+CONFIG_LIRC_SASEM=m -+CONFIG_LIRC_SERIAL=m -+CONFIG_FB_TFT=m -+CONFIG_FB_TFT_AGM1264K_FL=m -+CONFIG_FB_TFT_BD663474=m -+CONFIG_FB_TFT_HX8340BN=m -+CONFIG_FB_TFT_HX8347D=m -+CONFIG_FB_TFT_HX8353D=m -+CONFIG_FB_TFT_ILI9320=m -+CONFIG_FB_TFT_ILI9325=m -+CONFIG_FB_TFT_ILI9340=m -+CONFIG_FB_TFT_ILI9341=m -+CONFIG_FB_TFT_ILI9481=m -+CONFIG_FB_TFT_ILI9486=m -+CONFIG_FB_TFT_PCD8544=m -+CONFIG_FB_TFT_RA8875=m -+CONFIG_FB_TFT_S6D02A1=m -+CONFIG_FB_TFT_S6D1121=m -+CONFIG_FB_TFT_SSD1289=m -+CONFIG_FB_TFT_SSD1306=m -+CONFIG_FB_TFT_SSD1331=m -+CONFIG_FB_TFT_SSD1351=m -+CONFIG_FB_TFT_ST7735R=m -+CONFIG_FB_TFT_TINYLCD=m -+CONFIG_FB_TFT_TLS8204=m -+CONFIG_FB_TFT_UC1701=m -+CONFIG_FB_TFT_UPD161704=m -+CONFIG_FB_TFT_WATTEROTT=m -+CONFIG_FB_FLEX=m -+CONFIG_FB_TFT_FBTFT_DEVICE=m -+CONFIG_MAILBOX=y -+CONFIG_BCM2835_MBOX=y - # CONFIG_IOMMU_SUPPORT is not set -+CONFIG_EXTCON=m -+CONFIG_EXTCON_ARIZONA=m -+CONFIG_RASPBERRYPI_FIRMWARE=y - CONFIG_EXT2_FS=y - CONFIG_EXT2_FS_XATTR=y - CONFIG_EXT2_FS_POSIX_ACL=y -@@ -107,18 +1077,110 @@ - CONFIG_EXT3_FS_POSIX_ACL=y - CONFIG_EXT4_FS=y - CONFIG_EXT4_FS_POSIX_ACL=y -+CONFIG_EXT4_FS_SECURITY=y -+CONFIG_REISERFS_FS=m -+CONFIG_REISERFS_FS_XATTR=y -+CONFIG_REISERFS_FS_POSIX_ACL=y -+CONFIG_REISERFS_FS_SECURITY=y -+CONFIG_JFS_FS=m -+CONFIG_JFS_POSIX_ACL=y -+CONFIG_JFS_SECURITY=y -+CONFIG_JFS_STATISTICS=y -+CONFIG_XFS_FS=m -+CONFIG_XFS_QUOTA=y -+CONFIG_XFS_POSIX_ACL=y -+CONFIG_XFS_RT=y -+CONFIG_GFS2_FS=m -+CONFIG_OCFS2_FS=m -+CONFIG_BTRFS_FS=m -+CONFIG_BTRFS_FS_POSIX_ACL=y -+CONFIG_NILFS2_FS=m -+CONFIG_F2FS_FS=y - CONFIG_FANOTIFY=y -+CONFIG_QFMT_V1=m -+CONFIG_QFMT_V2=m -+CONFIG_AUTOFS4_FS=y -+CONFIG_FUSE_FS=m -+CONFIG_CUSE=m -+CONFIG_FSCACHE=y -+CONFIG_FSCACHE_STATS=y -+CONFIG_FSCACHE_HISTOGRAM=y -+CONFIG_CACHEFILES=y -+CONFIG_ISO9660_FS=m -+CONFIG_JOLIET=y -+CONFIG_ZISOFS=y -+CONFIG_UDF_FS=m - CONFIG_MSDOS_FS=y - CONFIG_VFAT_FS=y -+CONFIG_FAT_DEFAULT_IOCHARSET="ascii" -+CONFIG_NTFS_FS=m -+CONFIG_NTFS_RW=y - CONFIG_TMPFS=y - CONFIG_TMPFS_POSIX_ACL=y --# CONFIG_MISC_FILESYSTEMS is not set -+CONFIG_CONFIGFS_FS=y -+CONFIG_ECRYPT_FS=m -+CONFIG_HFS_FS=m -+CONFIG_HFSPLUS_FS=m -+CONFIG_SQUASHFS=m -+CONFIG_SQUASHFS_XATTR=y -+CONFIG_SQUASHFS_LZO=y -+CONFIG_SQUASHFS_XZ=y - CONFIG_NFS_FS=y --CONFIG_NFSD=y -+CONFIG_NFS_V3_ACL=y -+CONFIG_NFS_V4=y -+CONFIG_NFS_SWAP=y -+CONFIG_ROOT_NFS=y -+CONFIG_NFS_FSCACHE=y -+CONFIG_NFSD=m -+CONFIG_NFSD_V3_ACL=y -+CONFIG_NFSD_V4=y -+CONFIG_CIFS=m -+CONFIG_CIFS_WEAK_PW_HASH=y -+CONFIG_CIFS_UPCALL=y -+CONFIG_CIFS_XATTR=y -+CONFIG_CIFS_POSIX=y -+CONFIG_9P_FS=m -+CONFIG_9P_FS_POSIX_ACL=y -+CONFIG_NLS_DEFAULT="utf8" - CONFIG_NLS_CODEPAGE_437=y -+CONFIG_NLS_CODEPAGE_737=m -+CONFIG_NLS_CODEPAGE_775=m -+CONFIG_NLS_CODEPAGE_850=m -+CONFIG_NLS_CODEPAGE_852=m -+CONFIG_NLS_CODEPAGE_855=m -+CONFIG_NLS_CODEPAGE_857=m -+CONFIG_NLS_CODEPAGE_860=m -+CONFIG_NLS_CODEPAGE_861=m -+CONFIG_NLS_CODEPAGE_862=m -+CONFIG_NLS_CODEPAGE_863=m -+CONFIG_NLS_CODEPAGE_864=m -+CONFIG_NLS_CODEPAGE_865=m -+CONFIG_NLS_CODEPAGE_866=m -+CONFIG_NLS_CODEPAGE_869=m -+CONFIG_NLS_CODEPAGE_936=m -+CONFIG_NLS_CODEPAGE_950=m -+CONFIG_NLS_CODEPAGE_932=m -+CONFIG_NLS_CODEPAGE_949=m -+CONFIG_NLS_CODEPAGE_874=m -+CONFIG_NLS_ISO8859_8=m -+CONFIG_NLS_CODEPAGE_1250=m -+CONFIG_NLS_CODEPAGE_1251=m - CONFIG_NLS_ASCII=y --CONFIG_NLS_ISO8859_1=y -+CONFIG_NLS_ISO8859_1=m -+CONFIG_NLS_ISO8859_2=m -+CONFIG_NLS_ISO8859_3=m -+CONFIG_NLS_ISO8859_4=m -+CONFIG_NLS_ISO8859_5=m -+CONFIG_NLS_ISO8859_6=m -+CONFIG_NLS_ISO8859_7=m -+CONFIG_NLS_ISO8859_9=m -+CONFIG_NLS_ISO8859_13=m -+CONFIG_NLS_ISO8859_14=m -+CONFIG_NLS_ISO8859_15=m -+CONFIG_NLS_KOI8_R=m -+CONFIG_NLS_KOI8_U=m - CONFIG_NLS_UTF8=y -+CONFIG_DLM=m - CONFIG_PRINTK_TIME=y - CONFIG_BOOT_PRINTK_DELAY=y - CONFIG_DYNAMIC_DEBUG=y -@@ -128,14 +1190,39 @@ - CONFIG_UNUSED_SYMBOLS=y - CONFIG_DEBUG_MEMORY_INIT=y - CONFIG_LOCKUP_DETECTOR=y -+CONFIG_TIMER_STATS=y -+# CONFIG_DEBUG_PREEMPT is not set -+CONFIG_LATENCYTOP=y -+CONFIG_IRQSOFF_TRACER=y - CONFIG_SCHED_TRACER=y - CONFIG_STACK_TRACER=y -+CONFIG_BLK_DEV_IO_TRACE=y -+# CONFIG_KPROBE_EVENT is not set - CONFIG_FUNCTION_PROFILER=y - CONFIG_TEST_KSTRTOX=y - CONFIG_KGDB=y - CONFIG_KGDB_KDB=y -+CONFIG_KDB_KEYBOARD=y - CONFIG_STRICT_DEVMEM=y - CONFIG_DEBUG_LL=y - CONFIG_EARLY_PRINTK=y -+CONFIG_CRYPTO_USER=m -+CONFIG_CRYPTO_CRYPTD=m -+CONFIG_CRYPTO_CBC=y -+CONFIG_CRYPTO_CTS=m -+CONFIG_CRYPTO_XTS=m -+CONFIG_CRYPTO_XCBC=m -+CONFIG_CRYPTO_SHA512=m -+CONFIG_CRYPTO_TGR192=m -+CONFIG_CRYPTO_WP512=m -+CONFIG_CRYPTO_CAST5=m -+CONFIG_CRYPTO_DES=y -+# CONFIG_CRYPTO_ANSI_CPRNG is not set -+# CONFIG_CRYPTO_HW is not set -+CONFIG_ARM_CRYPTO=y -+CONFIG_CRYPTO_SHA1_ARM=m -+CONFIG_CRYPTO_AES_ARM=m -+CONFIG_CRC_ITU_T=y -+CONFIG_LIBCRC32C=y - # CONFIG_XZ_DEC_ARM is not set - # CONFIG_XZ_DEC_ARMTHUMB is not set -diff -Nur linux-4.1.13.orig/arch/arm/configs/bcmrpi_defconfig linux-rpi/arch/arm/configs/bcmrpi_defconfig ---- linux-4.1.13.orig/arch/arm/configs/bcmrpi_defconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/configs/bcmrpi_defconfig 2015-11-29 09:42:34.707444982 +0100 -@@ -0,0 +1,1255 @@ -+# CONFIG_ARM_PATCH_PHYS_VIRT is not set -+CONFIG_PHYS_OFFSET=0 -+# CONFIG_LOCALVERSION_AUTO is not set -+CONFIG_SYSVIPC=y -+CONFIG_POSIX_MQUEUE=y -+CONFIG_FHANDLE=y -+CONFIG_NO_HZ=y -+CONFIG_HIGH_RES_TIMERS=y -+CONFIG_BSD_PROCESS_ACCT=y -+CONFIG_BSD_PROCESS_ACCT_V3=y -+CONFIG_TASKSTATS=y -+CONFIG_TASK_DELAY_ACCT=y -+CONFIG_TASK_XACCT=y -+CONFIG_TASK_IO_ACCOUNTING=y -+CONFIG_IKCONFIG=m -+CONFIG_IKCONFIG_PROC=y -+CONFIG_CGROUP_FREEZER=y -+CONFIG_CGROUP_DEVICE=y -+CONFIG_CPUSETS=y -+CONFIG_CGROUP_CPUACCT=y -+CONFIG_MEMCG=y -+CONFIG_BLK_CGROUP=y -+CONFIG_NAMESPACES=y -+CONFIG_SCHED_AUTOGROUP=y -+CONFIG_BLK_DEV_INITRD=y -+CONFIG_EMBEDDED=y -+# CONFIG_COMPAT_BRK is not set -+CONFIG_PROFILING=y -+CONFIG_OPROFILE=m -+CONFIG_KPROBES=y -+CONFIG_JUMP_LABEL=y -+CONFIG_MODULES=y -+CONFIG_MODULE_UNLOAD=y -+CONFIG_MODVERSIONS=y -+CONFIG_MODULE_SRCVERSION_ALL=y -+CONFIG_BLK_DEV_THROTTLING=y -+CONFIG_PARTITION_ADVANCED=y -+CONFIG_MAC_PARTITION=y -+CONFIG_CFQ_GROUP_IOSCHED=y -+CONFIG_ARCH_BCM2708=y -+CONFIG_BCM2708_DT=y -+CONFIG_PREEMPT=y -+CONFIG_AEABI=y -+CONFIG_OABI_COMPAT=y -+CONFIG_CLEANCACHE=y -+CONFIG_FRONTSWAP=y -+CONFIG_CMA=y -+CONFIG_ZSMALLOC=m -+CONFIG_PGTABLE_MAPPING=y -+CONFIG_UACCESS_WITH_MEMCPY=y -+CONFIG_SECCOMP=y -+CONFIG_ZBOOT_ROM_TEXT=0x0 -+CONFIG_ZBOOT_ROM_BSS=0x0 -+CONFIG_CMDLINE="console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait" -+CONFIG_CPU_FREQ=y -+CONFIG_CPU_FREQ_STAT=m -+CONFIG_CPU_FREQ_STAT_DETAILS=y -+CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y -+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -+CONFIG_CPU_FREQ_GOV_USERSPACE=y -+CONFIG_CPU_FREQ_GOV_ONDEMAND=y -+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -+CONFIG_VFP=y -+CONFIG_BINFMT_MISC=m -+# CONFIG_SUSPEND is not set -+CONFIG_NET=y -+CONFIG_PACKET=y -+CONFIG_UNIX=y -+CONFIG_XFRM_USER=y -+CONFIG_NET_KEY=m -+CONFIG_INET=y -+CONFIG_IP_MULTICAST=y -+CONFIG_IP_ADVANCED_ROUTER=y -+CONFIG_IP_MULTIPLE_TABLES=y -+CONFIG_IP_ROUTE_MULTIPATH=y -+CONFIG_IP_ROUTE_VERBOSE=y -+CONFIG_IP_PNP=y -+CONFIG_IP_PNP_DHCP=y -+CONFIG_IP_PNP_RARP=y -+CONFIG_NET_IPIP=m -+CONFIG_NET_IPGRE_DEMUX=m -+CONFIG_NET_IPGRE=m -+CONFIG_IP_MROUTE=y -+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y -+CONFIG_IP_PIMSM_V1=y -+CONFIG_IP_PIMSM_V2=y -+CONFIG_SYN_COOKIES=y -+CONFIG_INET_AH=m -+CONFIG_INET_ESP=m -+CONFIG_INET_IPCOMP=m -+CONFIG_INET_XFRM_MODE_TRANSPORT=m -+CONFIG_INET_XFRM_MODE_TUNNEL=m -+CONFIG_INET_XFRM_MODE_BEET=m -+CONFIG_INET_LRO=m -+CONFIG_INET_DIAG=m -+CONFIG_INET6_AH=m -+CONFIG_INET6_ESP=m -+CONFIG_INET6_IPCOMP=m -+CONFIG_IPV6_TUNNEL=m -+CONFIG_IPV6_MULTIPLE_TABLES=y -+CONFIG_IPV6_MROUTE=y -+CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y -+CONFIG_IPV6_PIMSM_V2=y -+CONFIG_NETFILTER=y -+CONFIG_NF_CONNTRACK=m -+CONFIG_NF_CONNTRACK_ZONES=y -+CONFIG_NF_CONNTRACK_EVENTS=y -+CONFIG_NF_CONNTRACK_TIMESTAMP=y -+CONFIG_NF_CT_PROTO_DCCP=m -+CONFIG_NF_CT_PROTO_UDPLITE=m -+CONFIG_NF_CONNTRACK_AMANDA=m -+CONFIG_NF_CONNTRACK_FTP=m -+CONFIG_NF_CONNTRACK_H323=m -+CONFIG_NF_CONNTRACK_IRC=m -+CONFIG_NF_CONNTRACK_NETBIOS_NS=m -+CONFIG_NF_CONNTRACK_SNMP=m -+CONFIG_NF_CONNTRACK_PPTP=m -+CONFIG_NF_CONNTRACK_SANE=m -+CONFIG_NF_CONNTRACK_SIP=m -+CONFIG_NF_CONNTRACK_TFTP=m -+CONFIG_NF_CT_NETLINK=m -+CONFIG_NETFILTER_XT_SET=m -+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m -+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m -+CONFIG_NETFILTER_XT_TARGET_DSCP=m -+CONFIG_NETFILTER_XT_TARGET_HMARK=m -+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m -+CONFIG_NETFILTER_XT_TARGET_LED=m -+CONFIG_NETFILTER_XT_TARGET_LOG=m -+CONFIG_NETFILTER_XT_TARGET_MARK=m -+CONFIG_NETFILTER_XT_TARGET_NFLOG=m -+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m -+CONFIG_NETFILTER_XT_TARGET_TEE=m -+CONFIG_NETFILTER_XT_TARGET_TPROXY=m -+CONFIG_NETFILTER_XT_TARGET_TRACE=m -+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m -+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m -+CONFIG_NETFILTER_XT_MATCH_BPF=m -+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m -+CONFIG_NETFILTER_XT_MATCH_COMMENT=m -+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m -+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m -+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -+CONFIG_NETFILTER_XT_MATCH_CPU=m -+CONFIG_NETFILTER_XT_MATCH_DCCP=m -+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m -+CONFIG_NETFILTER_XT_MATCH_DSCP=m -+CONFIG_NETFILTER_XT_MATCH_ESP=m -+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m -+CONFIG_NETFILTER_XT_MATCH_HELPER=m -+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m -+CONFIG_NETFILTER_XT_MATCH_IPVS=m -+CONFIG_NETFILTER_XT_MATCH_LENGTH=m -+CONFIG_NETFILTER_XT_MATCH_LIMIT=m -+CONFIG_NETFILTER_XT_MATCH_MAC=m -+CONFIG_NETFILTER_XT_MATCH_MARK=m -+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -+CONFIG_NETFILTER_XT_MATCH_NFACCT=m -+CONFIG_NETFILTER_XT_MATCH_OSF=m -+CONFIG_NETFILTER_XT_MATCH_OWNER=m -+CONFIG_NETFILTER_XT_MATCH_POLICY=m -+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m -+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -+CONFIG_NETFILTER_XT_MATCH_QUOTA=m -+CONFIG_NETFILTER_XT_MATCH_RATEEST=m -+CONFIG_NETFILTER_XT_MATCH_REALM=m -+CONFIG_NETFILTER_XT_MATCH_RECENT=m -+CONFIG_NETFILTER_XT_MATCH_SOCKET=m -+CONFIG_NETFILTER_XT_MATCH_STATE=m -+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -+CONFIG_NETFILTER_XT_MATCH_STRING=m -+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -+CONFIG_NETFILTER_XT_MATCH_TIME=m -+CONFIG_NETFILTER_XT_MATCH_U32=m -+CONFIG_IP_SET=m -+CONFIG_IP_SET_BITMAP_IP=m -+CONFIG_IP_SET_BITMAP_IPMAC=m -+CONFIG_IP_SET_BITMAP_PORT=m -+CONFIG_IP_SET_HASH_IP=m -+CONFIG_IP_SET_HASH_IPPORT=m -+CONFIG_IP_SET_HASH_IPPORTIP=m -+CONFIG_IP_SET_HASH_IPPORTNET=m -+CONFIG_IP_SET_HASH_NET=m -+CONFIG_IP_SET_HASH_NETPORT=m -+CONFIG_IP_SET_HASH_NETIFACE=m -+CONFIG_IP_SET_LIST_SET=m -+CONFIG_IP_VS=m -+CONFIG_IP_VS_PROTO_TCP=y -+CONFIG_IP_VS_PROTO_UDP=y -+CONFIG_IP_VS_PROTO_ESP=y -+CONFIG_IP_VS_PROTO_AH=y -+CONFIG_IP_VS_PROTO_SCTP=y -+CONFIG_IP_VS_RR=m -+CONFIG_IP_VS_WRR=m -+CONFIG_IP_VS_LC=m -+CONFIG_IP_VS_WLC=m -+CONFIG_IP_VS_LBLC=m -+CONFIG_IP_VS_LBLCR=m -+CONFIG_IP_VS_DH=m -+CONFIG_IP_VS_SH=m -+CONFIG_IP_VS_SED=m -+CONFIG_IP_VS_NQ=m -+CONFIG_IP_VS_FTP=m -+CONFIG_IP_VS_PE_SIP=m -+CONFIG_NF_CONNTRACK_IPV4=m -+CONFIG_IP_NF_IPTABLES=m -+CONFIG_IP_NF_MATCH_AH=m -+CONFIG_IP_NF_MATCH_ECN=m -+CONFIG_IP_NF_MATCH_TTL=m -+CONFIG_IP_NF_FILTER=m -+CONFIG_IP_NF_TARGET_REJECT=m -+CONFIG_IP_NF_NAT=m -+CONFIG_IP_NF_TARGET_MASQUERADE=m -+CONFIG_IP_NF_TARGET_NETMAP=m -+CONFIG_IP_NF_TARGET_REDIRECT=m -+CONFIG_IP_NF_MANGLE=m -+CONFIG_IP_NF_TARGET_CLUSTERIP=m -+CONFIG_IP_NF_TARGET_ECN=m -+CONFIG_IP_NF_TARGET_TTL=m -+CONFIG_IP_NF_RAW=m -+CONFIG_IP_NF_ARPTABLES=m -+CONFIG_IP_NF_ARPFILTER=m -+CONFIG_IP_NF_ARP_MANGLE=m -+CONFIG_NF_CONNTRACK_IPV6=m -+CONFIG_IP6_NF_IPTABLES=m -+CONFIG_IP6_NF_MATCH_AH=m -+CONFIG_IP6_NF_MATCH_EUI64=m -+CONFIG_IP6_NF_MATCH_FRAG=m -+CONFIG_IP6_NF_MATCH_OPTS=m -+CONFIG_IP6_NF_MATCH_HL=m -+CONFIG_IP6_NF_MATCH_IPV6HEADER=m -+CONFIG_IP6_NF_MATCH_MH=m -+CONFIG_IP6_NF_MATCH_RT=m -+CONFIG_IP6_NF_TARGET_HL=m -+CONFIG_IP6_NF_FILTER=m -+CONFIG_IP6_NF_TARGET_REJECT=m -+CONFIG_IP6_NF_MANGLE=m -+CONFIG_IP6_NF_RAW=m -+CONFIG_IP6_NF_NAT=m -+CONFIG_IP6_NF_TARGET_MASQUERADE=m -+CONFIG_IP6_NF_TARGET_NPT=m -+CONFIG_BRIDGE_NF_EBTABLES=m -+CONFIG_BRIDGE_EBT_BROUTE=m -+CONFIG_BRIDGE_EBT_T_FILTER=m -+CONFIG_BRIDGE_EBT_T_NAT=m -+CONFIG_BRIDGE_EBT_802_3=m -+CONFIG_BRIDGE_EBT_AMONG=m -+CONFIG_BRIDGE_EBT_ARP=m -+CONFIG_BRIDGE_EBT_IP=m -+CONFIG_BRIDGE_EBT_IP6=m -+CONFIG_BRIDGE_EBT_LIMIT=m -+CONFIG_BRIDGE_EBT_MARK=m -+CONFIG_BRIDGE_EBT_PKTTYPE=m -+CONFIG_BRIDGE_EBT_STP=m -+CONFIG_BRIDGE_EBT_VLAN=m -+CONFIG_BRIDGE_EBT_ARPREPLY=m -+CONFIG_BRIDGE_EBT_DNAT=m -+CONFIG_BRIDGE_EBT_MARK_T=m -+CONFIG_BRIDGE_EBT_REDIRECT=m -+CONFIG_BRIDGE_EBT_SNAT=m -+CONFIG_BRIDGE_EBT_LOG=m -+CONFIG_BRIDGE_EBT_NFLOG=m -+CONFIG_SCTP_COOKIE_HMAC_SHA1=y -+CONFIG_ATM=m -+CONFIG_L2TP=m -+CONFIG_L2TP_V3=y -+CONFIG_L2TP_IP=m -+CONFIG_L2TP_ETH=m -+CONFIG_BRIDGE=m -+CONFIG_VLAN_8021Q=m -+CONFIG_VLAN_8021Q_GVRP=y -+CONFIG_ATALK=m -+CONFIG_6LOWPAN=m -+CONFIG_IEEE802154=m -+CONFIG_IEEE802154_6LOWPAN=m -+CONFIG_MAC802154=m -+CONFIG_NET_SCHED=y -+CONFIG_NET_SCH_CBQ=m -+CONFIG_NET_SCH_HTB=m -+CONFIG_NET_SCH_HFSC=m -+CONFIG_NET_SCH_PRIO=m -+CONFIG_NET_SCH_MULTIQ=m -+CONFIG_NET_SCH_RED=m -+CONFIG_NET_SCH_SFB=m -+CONFIG_NET_SCH_SFQ=m -+CONFIG_NET_SCH_TEQL=m -+CONFIG_NET_SCH_TBF=m -+CONFIG_NET_SCH_GRED=m -+CONFIG_NET_SCH_DSMARK=m -+CONFIG_NET_SCH_NETEM=m -+CONFIG_NET_SCH_DRR=m -+CONFIG_NET_SCH_MQPRIO=m -+CONFIG_NET_SCH_CHOKE=m -+CONFIG_NET_SCH_QFQ=m -+CONFIG_NET_SCH_CODEL=m -+CONFIG_NET_SCH_FQ_CODEL=m -+CONFIG_NET_SCH_INGRESS=m -+CONFIG_NET_SCH_PLUG=m -+CONFIG_NET_CLS_BASIC=m -+CONFIG_NET_CLS_TCINDEX=m -+CONFIG_NET_CLS_ROUTE4=m -+CONFIG_NET_CLS_FW=m -+CONFIG_NET_CLS_U32=m -+CONFIG_CLS_U32_MARK=y -+CONFIG_NET_CLS_RSVP=m -+CONFIG_NET_CLS_RSVP6=m -+CONFIG_NET_CLS_FLOW=m -+CONFIG_NET_CLS_CGROUP=m -+CONFIG_NET_EMATCH=y -+CONFIG_NET_EMATCH_CMP=m -+CONFIG_NET_EMATCH_NBYTE=m -+CONFIG_NET_EMATCH_U32=m -+CONFIG_NET_EMATCH_META=m -+CONFIG_NET_EMATCH_TEXT=m -+CONFIG_NET_EMATCH_IPSET=m -+CONFIG_NET_CLS_ACT=y -+CONFIG_NET_ACT_POLICE=m -+CONFIG_NET_ACT_GACT=m -+CONFIG_GACT_PROB=y -+CONFIG_NET_ACT_MIRRED=m -+CONFIG_NET_ACT_IPT=m -+CONFIG_NET_ACT_NAT=m -+CONFIG_NET_ACT_PEDIT=m -+CONFIG_NET_ACT_SIMP=m -+CONFIG_NET_ACT_SKBEDIT=m -+CONFIG_NET_ACT_CSUM=m -+CONFIG_BATMAN_ADV=m -+CONFIG_OPENVSWITCH=m -+CONFIG_NET_PKTGEN=m -+CONFIG_HAMRADIO=y -+CONFIG_AX25=m -+CONFIG_NETROM=m -+CONFIG_ROSE=m -+CONFIG_MKISS=m -+CONFIG_6PACK=m -+CONFIG_BPQETHER=m -+CONFIG_BAYCOM_SER_FDX=m -+CONFIG_BAYCOM_SER_HDX=m -+CONFIG_YAM=m -+CONFIG_CAN=m -+CONFIG_CAN_VCAN=m -+CONFIG_CAN_MCP251X=m -+CONFIG_IRDA=m -+CONFIG_IRLAN=m -+CONFIG_IRNET=m -+CONFIG_IRCOMM=m -+CONFIG_IRDA_ULTRA=y -+CONFIG_IRDA_CACHE_LAST_LSAP=y -+CONFIG_IRDA_FAST_RR=y -+CONFIG_IRTTY_SIR=m -+CONFIG_KINGSUN_DONGLE=m -+CONFIG_KSDAZZLE_DONGLE=m -+CONFIG_KS959_DONGLE=m -+CONFIG_USB_IRDA=m -+CONFIG_SIGMATEL_FIR=m -+CONFIG_MCS_FIR=m -+CONFIG_BT=m -+CONFIG_BT_RFCOMM=m -+CONFIG_BT_RFCOMM_TTY=y -+CONFIG_BT_BNEP=m -+CONFIG_BT_BNEP_MC_FILTER=y -+CONFIG_BT_BNEP_PROTO_FILTER=y -+CONFIG_BT_HIDP=m -+CONFIG_BT_6LOWPAN=m -+CONFIG_BT_HCIBTUSB=m -+CONFIG_BT_HCIBCM203X=m -+CONFIG_BT_HCIBPA10X=m -+CONFIG_BT_HCIBFUSB=m -+CONFIG_BT_HCIVHCI=m -+CONFIG_BT_MRVL=m -+CONFIG_BT_MRVL_SDIO=m -+CONFIG_BT_ATH3K=m -+CONFIG_BT_WILINK=m -+CONFIG_MAC80211=m -+CONFIG_MAC80211_MESH=y -+CONFIG_WIMAX=m -+CONFIG_RFKILL=m -+CONFIG_RFKILL_INPUT=y -+CONFIG_NET_9P=m -+CONFIG_NFC=m -+CONFIG_NFC_PN533=m -+CONFIG_DEVTMPFS=y -+CONFIG_DEVTMPFS_MOUNT=y -+CONFIG_DMA_CMA=y -+CONFIG_CMA_SIZE_MBYTES=5 -+CONFIG_MTD=m -+CONFIG_MTD_BLOCK=m -+CONFIG_MTD_NAND=m -+CONFIG_MTD_UBI=m -+CONFIG_ZRAM=m -+CONFIG_ZRAM_LZ4_COMPRESS=y -+CONFIG_BLK_DEV_LOOP=y -+CONFIG_BLK_DEV_CRYPTOLOOP=m -+CONFIG_BLK_DEV_DRBD=m -+CONFIG_BLK_DEV_NBD=m -+CONFIG_BLK_DEV_RAM=y -+CONFIG_CDROM_PKTCDVD=m -+CONFIG_ATA_OVER_ETH=m -+CONFIG_EEPROM_AT24=m -+CONFIG_TI_ST=m -+CONFIG_SCSI=y -+# CONFIG_SCSI_PROC_FS is not set -+CONFIG_BLK_DEV_SD=y -+CONFIG_CHR_DEV_ST=m -+CONFIG_CHR_DEV_OSST=m -+CONFIG_BLK_DEV_SR=m -+CONFIG_CHR_DEV_SG=m -+CONFIG_SCSI_ISCSI_ATTRS=y -+CONFIG_ISCSI_TCP=m -+CONFIG_ISCSI_BOOT_SYSFS=m -+CONFIG_MD=y -+CONFIG_MD_LINEAR=m -+CONFIG_MD_RAID0=m -+CONFIG_BLK_DEV_DM=m -+CONFIG_DM_CRYPT=m -+CONFIG_DM_SNAPSHOT=m -+CONFIG_DM_THIN_PROVISIONING=m -+CONFIG_DM_MIRROR=m -+CONFIG_DM_LOG_USERSPACE=m -+CONFIG_DM_RAID=m -+CONFIG_DM_ZERO=m -+CONFIG_DM_DELAY=m -+CONFIG_NETDEVICES=y -+CONFIG_BONDING=m -+CONFIG_DUMMY=m -+CONFIG_IFB=m -+CONFIG_MACVLAN=m -+CONFIG_NETCONSOLE=m -+CONFIG_TUN=m -+CONFIG_VETH=m -+CONFIG_ENC28J60=m -+CONFIG_MDIO_BITBANG=m -+CONFIG_PPP=m -+CONFIG_PPP_BSDCOMP=m -+CONFIG_PPP_DEFLATE=m -+CONFIG_PPP_FILTER=y -+CONFIG_PPP_MPPE=m -+CONFIG_PPP_MULTILINK=y -+CONFIG_PPPOATM=m -+CONFIG_PPPOE=m -+CONFIG_PPPOL2TP=m -+CONFIG_PPP_ASYNC=m -+CONFIG_PPP_SYNC_TTY=m -+CONFIG_SLIP=m -+CONFIG_SLIP_COMPRESSED=y -+CONFIG_SLIP_SMART=y -+CONFIG_USB_CATC=m -+CONFIG_USB_KAWETH=m -+CONFIG_USB_PEGASUS=m -+CONFIG_USB_RTL8150=m -+CONFIG_USB_RTL8152=m -+CONFIG_USB_USBNET=y -+CONFIG_USB_NET_AX8817X=m -+CONFIG_USB_NET_AX88179_178A=m -+CONFIG_USB_NET_CDCETHER=m -+CONFIG_USB_NET_CDC_EEM=m -+CONFIG_USB_NET_CDC_NCM=m -+CONFIG_USB_NET_HUAWEI_CDC_NCM=m -+CONFIG_USB_NET_CDC_MBIM=m -+CONFIG_USB_NET_DM9601=m -+CONFIG_USB_NET_SR9700=m -+CONFIG_USB_NET_SR9800=m -+CONFIG_USB_NET_SMSC75XX=m -+CONFIG_USB_NET_SMSC95XX=y -+CONFIG_USB_NET_GL620A=m -+CONFIG_USB_NET_NET1080=m -+CONFIG_USB_NET_PLUSB=m -+CONFIG_USB_NET_MCS7830=m -+CONFIG_USB_NET_CDC_SUBSET=m -+CONFIG_USB_ALI_M5632=y -+CONFIG_USB_AN2720=y -+CONFIG_USB_EPSON2888=y -+CONFIG_USB_KC2190=y -+CONFIG_USB_NET_ZAURUS=m -+CONFIG_USB_NET_CX82310_ETH=m -+CONFIG_USB_NET_KALMIA=m -+CONFIG_USB_NET_QMI_WWAN=m -+CONFIG_USB_HSO=m -+CONFIG_USB_NET_INT51X1=m -+CONFIG_USB_IPHETH=m -+CONFIG_USB_SIERRA_NET=m -+CONFIG_USB_VL600=m -+CONFIG_LIBERTAS_THINFIRM=m -+CONFIG_LIBERTAS_THINFIRM_USB=m -+CONFIG_AT76C50X_USB=m -+CONFIG_USB_ZD1201=m -+CONFIG_USB_NET_RNDIS_WLAN=m -+CONFIG_RTL8187=m -+CONFIG_MAC80211_HWSIM=m -+CONFIG_ATH_CARDS=m -+CONFIG_ATH9K=m -+CONFIG_ATH9K_HTC=m -+CONFIG_CARL9170=m -+CONFIG_ATH6KL=m -+CONFIG_ATH6KL_USB=m -+CONFIG_AR5523=m -+CONFIG_B43=m -+# CONFIG_B43_PHY_N is not set -+CONFIG_B43LEGACY=m -+CONFIG_BRCMFMAC=m -+CONFIG_BRCMFMAC_USB=y -+CONFIG_HOSTAP=m -+CONFIG_LIBERTAS=m -+CONFIG_LIBERTAS_USB=m -+CONFIG_LIBERTAS_SDIO=m -+CONFIG_P54_COMMON=m -+CONFIG_P54_USB=m -+CONFIG_RT2X00=m -+CONFIG_RT2500USB=m -+CONFIG_RT73USB=m -+CONFIG_RT2800USB=m -+CONFIG_RT2800USB_RT3573=y -+CONFIG_RT2800USB_RT53XX=y -+CONFIG_RT2800USB_RT55XX=y -+CONFIG_RT2800USB_UNKNOWN=y -+CONFIG_WL_MEDIATEK=y -+CONFIG_MT7601U=m -+CONFIG_RTL8192CU=m -+CONFIG_ZD1211RW=m -+CONFIG_MWIFIEX=m -+CONFIG_MWIFIEX_SDIO=m -+CONFIG_WIMAX_I2400M_USB=m -+CONFIG_IEEE802154_AT86RF230=m -+CONFIG_IEEE802154_MRF24J40=m -+CONFIG_IEEE802154_CC2520=m -+CONFIG_INPUT_POLLDEV=m -+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -+CONFIG_INPUT_JOYDEV=m -+CONFIG_INPUT_EVDEV=m -+# CONFIG_KEYBOARD_ATKBD is not set -+CONFIG_KEYBOARD_GPIO=m -+# CONFIG_INPUT_MOUSE is not set -+CONFIG_INPUT_JOYSTICK=y -+CONFIG_JOYSTICK_IFORCE=m -+CONFIG_JOYSTICK_IFORCE_USB=y -+CONFIG_JOYSTICK_XPAD=m -+CONFIG_JOYSTICK_XPAD_FF=y -+CONFIG_JOYSTICK_RPISENSE=m -+CONFIG_INPUT_TOUCHSCREEN=y -+CONFIG_TOUCHSCREEN_ADS7846=m -+CONFIG_TOUCHSCREEN_EGALAX=m -+CONFIG_TOUCHSCREEN_FT6236=m -+CONFIG_TOUCHSCREEN_RPI_FT5406=m -+CONFIG_TOUCHSCREEN_USB_COMPOSITE=m -+CONFIG_TOUCHSCREEN_STMPE=m -+CONFIG_INPUT_MISC=y -+CONFIG_INPUT_AD714X=m -+CONFIG_INPUT_ATI_REMOTE2=m -+CONFIG_INPUT_KEYSPAN_REMOTE=m -+CONFIG_INPUT_POWERMATE=m -+CONFIG_INPUT_YEALINK=m -+CONFIG_INPUT_CM109=m -+CONFIG_INPUT_UINPUT=m -+CONFIG_INPUT_GPIO_ROTARY_ENCODER=m -+CONFIG_INPUT_ADXL34X=m -+CONFIG_INPUT_CMA3000=m -+CONFIG_SERIO=m -+CONFIG_SERIO_RAW=m -+CONFIG_GAMEPORT=m -+CONFIG_GAMEPORT_NS558=m -+CONFIG_GAMEPORT_L4=m -+CONFIG_DEVPTS_MULTIPLE_INSTANCES=y -+# CONFIG_LEGACY_PTYS is not set -+# CONFIG_DEVKMEM is not set -+CONFIG_SERIAL_8250=y -+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set -+CONFIG_SERIAL_8250_CONSOLE=y -+# CONFIG_SERIAL_8250_DMA is not set -+CONFIG_SERIAL_8250_NR_UARTS=1 -+CONFIG_SERIAL_8250_RUNTIME_UARTS=0 -+CONFIG_SERIAL_AMBA_PL011=y -+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -+CONFIG_SERIAL_OF_PLATFORM=y -+CONFIG_TTY_PRINTK=y -+CONFIG_HW_RANDOM=y -+CONFIG_HW_RANDOM_BCM2835=m -+CONFIG_HW_RANDOM_BCM2708=m -+CONFIG_RAW_DRIVER=y -+CONFIG_BRCM_CHAR_DRIVERS=y -+CONFIG_BCM_VC_CMA=y -+CONFIG_BCM_VCIO=y -+CONFIG_BCM_VC_SM=y -+CONFIG_I2C=y -+CONFIG_I2C_CHARDEV=m -+CONFIG_I2C_BCM2708=m -+CONFIG_I2C_GPIO=m -+CONFIG_SPI=y -+CONFIG_SPI_BCM2835=m -+CONFIG_SPI_BCM2708=m -+CONFIG_SPI_SPIDEV=y -+CONFIG_PPS=m -+CONFIG_PPS_CLIENT_LDISC=m -+CONFIG_PPS_CLIENT_GPIO=m -+CONFIG_GPIO_SYSFS=y -+CONFIG_GPIO_ARIZONA=m -+CONFIG_GPIO_STMPE=y -+CONFIG_W1=m -+CONFIG_W1_MASTER_DS2490=m -+CONFIG_W1_MASTER_DS2482=m -+CONFIG_W1_MASTER_DS1WM=m -+CONFIG_W1_MASTER_GPIO=m -+CONFIG_W1_SLAVE_THERM=m -+CONFIG_W1_SLAVE_SMEM=m -+CONFIG_W1_SLAVE_DS2408=m -+CONFIG_W1_SLAVE_DS2413=m -+CONFIG_W1_SLAVE_DS2406=m -+CONFIG_W1_SLAVE_DS2423=m -+CONFIG_W1_SLAVE_DS2431=m -+CONFIG_W1_SLAVE_DS2433=m -+CONFIG_W1_SLAVE_DS2760=m -+CONFIG_W1_SLAVE_DS2780=m -+CONFIG_W1_SLAVE_DS2781=m -+CONFIG_W1_SLAVE_DS28E04=m -+CONFIG_W1_SLAVE_BQ27000=m -+CONFIG_BATTERY_DS2760=m -+CONFIG_POWER_RESET=y -+CONFIG_POWER_RESET_GPIO=y -+CONFIG_HWMON=m -+CONFIG_SENSORS_SHT21=m -+CONFIG_SENSORS_SHTC1=m -+CONFIG_THERMAL=y -+CONFIG_THERMAL_BCM2835=y -+CONFIG_WATCHDOG=y -+CONFIG_BCM2708_WDT=m -+CONFIG_BCM2835_WDT=m -+CONFIG_UCB1400_CORE=m -+CONFIG_MFD_STMPE=y -+CONFIG_STMPE_SPI=y -+CONFIG_MFD_ARIZONA_I2C=m -+CONFIG_MFD_ARIZONA_SPI=m -+CONFIG_MFD_WM5102=y -+CONFIG_MEDIA_SUPPORT=m -+CONFIG_MEDIA_CAMERA_SUPPORT=y -+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y -+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y -+CONFIG_MEDIA_RADIO_SUPPORT=y -+CONFIG_MEDIA_RC_SUPPORT=y -+CONFIG_MEDIA_CONTROLLER=y -+CONFIG_LIRC=m -+CONFIG_RC_DEVICES=y -+CONFIG_RC_ATI_REMOTE=m -+CONFIG_IR_IMON=m -+CONFIG_IR_MCEUSB=m -+CONFIG_IR_REDRAT3=m -+CONFIG_IR_STREAMZAP=m -+CONFIG_IR_IGUANA=m -+CONFIG_IR_TTUSBIR=m -+CONFIG_RC_LOOPBACK=m -+CONFIG_IR_GPIO_CIR=m -+CONFIG_MEDIA_USB_SUPPORT=y -+CONFIG_USB_VIDEO_CLASS=m -+CONFIG_USB_M5602=m -+CONFIG_USB_STV06XX=m -+CONFIG_USB_GL860=m -+CONFIG_USB_GSPCA_BENQ=m -+CONFIG_USB_GSPCA_CONEX=m -+CONFIG_USB_GSPCA_CPIA1=m -+CONFIG_USB_GSPCA_DTCS033=m -+CONFIG_USB_GSPCA_ETOMS=m -+CONFIG_USB_GSPCA_FINEPIX=m -+CONFIG_USB_GSPCA_JEILINJ=m -+CONFIG_USB_GSPCA_JL2005BCD=m -+CONFIG_USB_GSPCA_KINECT=m -+CONFIG_USB_GSPCA_KONICA=m -+CONFIG_USB_GSPCA_MARS=m -+CONFIG_USB_GSPCA_MR97310A=m -+CONFIG_USB_GSPCA_NW80X=m -+CONFIG_USB_GSPCA_OV519=m -+CONFIG_USB_GSPCA_OV534=m -+CONFIG_USB_GSPCA_OV534_9=m -+CONFIG_USB_GSPCA_PAC207=m -+CONFIG_USB_GSPCA_PAC7302=m -+CONFIG_USB_GSPCA_PAC7311=m -+CONFIG_USB_GSPCA_SE401=m -+CONFIG_USB_GSPCA_SN9C2028=m -+CONFIG_USB_GSPCA_SN9C20X=m -+CONFIG_USB_GSPCA_SONIXB=m -+CONFIG_USB_GSPCA_SONIXJ=m -+CONFIG_USB_GSPCA_SPCA500=m -+CONFIG_USB_GSPCA_SPCA501=m -+CONFIG_USB_GSPCA_SPCA505=m -+CONFIG_USB_GSPCA_SPCA506=m -+CONFIG_USB_GSPCA_SPCA508=m -+CONFIG_USB_GSPCA_SPCA561=m -+CONFIG_USB_GSPCA_SPCA1528=m -+CONFIG_USB_GSPCA_SQ905=m -+CONFIG_USB_GSPCA_SQ905C=m -+CONFIG_USB_GSPCA_SQ930X=m -+CONFIG_USB_GSPCA_STK014=m -+CONFIG_USB_GSPCA_STK1135=m -+CONFIG_USB_GSPCA_STV0680=m -+CONFIG_USB_GSPCA_SUNPLUS=m -+CONFIG_USB_GSPCA_T613=m -+CONFIG_USB_GSPCA_TOPRO=m -+CONFIG_USB_GSPCA_TV8532=m -+CONFIG_USB_GSPCA_VC032X=m -+CONFIG_USB_GSPCA_VICAM=m -+CONFIG_USB_GSPCA_XIRLINK_CIT=m -+CONFIG_USB_GSPCA_ZC3XX=m -+CONFIG_USB_PWC=m -+CONFIG_VIDEO_CPIA2=m -+CONFIG_USB_ZR364XX=m -+CONFIG_USB_STKWEBCAM=m -+CONFIG_USB_S2255=m -+CONFIG_VIDEO_USBTV=m -+CONFIG_VIDEO_PVRUSB2=m -+CONFIG_VIDEO_HDPVR=m -+CONFIG_VIDEO_USBVISION=m -+CONFIG_VIDEO_STK1160_COMMON=m -+CONFIG_VIDEO_STK1160_AC97=y -+CONFIG_VIDEO_GO7007=m -+CONFIG_VIDEO_GO7007_USB=m -+CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m -+CONFIG_VIDEO_AU0828=m -+CONFIG_VIDEO_AU0828_RC=y -+CONFIG_VIDEO_CX231XX=m -+CONFIG_VIDEO_CX231XX_ALSA=m -+CONFIG_VIDEO_CX231XX_DVB=m -+CONFIG_VIDEO_TM6000=m -+CONFIG_VIDEO_TM6000_ALSA=m -+CONFIG_VIDEO_TM6000_DVB=m -+CONFIG_DVB_USB=m -+CONFIG_DVB_USB_A800=m -+CONFIG_DVB_USB_DIBUSB_MB=m -+CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y -+CONFIG_DVB_USB_DIBUSB_MC=m -+CONFIG_DVB_USB_DIB0700=m -+CONFIG_DVB_USB_UMT_010=m -+CONFIG_DVB_USB_CXUSB=m -+CONFIG_DVB_USB_M920X=m -+CONFIG_DVB_USB_DIGITV=m -+CONFIG_DVB_USB_VP7045=m -+CONFIG_DVB_USB_VP702X=m -+CONFIG_DVB_USB_GP8PSK=m -+CONFIG_DVB_USB_NOVA_T_USB2=m -+CONFIG_DVB_USB_TTUSB2=m -+CONFIG_DVB_USB_DTT200U=m -+CONFIG_DVB_USB_OPERA1=m -+CONFIG_DVB_USB_AF9005=m -+CONFIG_DVB_USB_AF9005_REMOTE=m -+CONFIG_DVB_USB_PCTV452E=m -+CONFIG_DVB_USB_DW2102=m -+CONFIG_DVB_USB_CINERGY_T2=m -+CONFIG_DVB_USB_DTV5100=m -+CONFIG_DVB_USB_FRIIO=m -+CONFIG_DVB_USB_AZ6027=m -+CONFIG_DVB_USB_TECHNISAT_USB2=m -+CONFIG_DVB_USB_V2=m -+CONFIG_DVB_USB_AF9015=m -+CONFIG_DVB_USB_AF9035=m -+CONFIG_DVB_USB_ANYSEE=m -+CONFIG_DVB_USB_AU6610=m -+CONFIG_DVB_USB_AZ6007=m -+CONFIG_DVB_USB_CE6230=m -+CONFIG_DVB_USB_EC168=m -+CONFIG_DVB_USB_GL861=m -+CONFIG_DVB_USB_LME2510=m -+CONFIG_DVB_USB_MXL111SF=m -+CONFIG_DVB_USB_RTL28XXU=m -+CONFIG_DVB_USB_DVBSKY=m -+CONFIG_SMS_USB_DRV=m -+CONFIG_DVB_B2C2_FLEXCOP_USB=m -+CONFIG_DVB_AS102=m -+CONFIG_VIDEO_EM28XX=m -+CONFIG_VIDEO_EM28XX_V4L2=m -+CONFIG_VIDEO_EM28XX_ALSA=m -+CONFIG_VIDEO_EM28XX_DVB=m -+CONFIG_V4L_PLATFORM_DRIVERS=y -+CONFIG_VIDEO_BCM2835=y -+CONFIG_VIDEO_BCM2835_MMAL=m -+CONFIG_RADIO_SI470X=y -+CONFIG_USB_SI470X=m -+CONFIG_I2C_SI470X=m -+CONFIG_RADIO_SI4713=m -+CONFIG_I2C_SI4713=m -+CONFIG_USB_MR800=m -+CONFIG_USB_DSBR=m -+CONFIG_RADIO_SHARK=m -+CONFIG_RADIO_SHARK2=m -+CONFIG_USB_KEENE=m -+CONFIG_USB_MA901=m -+CONFIG_RADIO_TEA5764=m -+CONFIG_RADIO_SAA7706H=m -+CONFIG_RADIO_TEF6862=m -+CONFIG_RADIO_WL1273=m -+CONFIG_RADIO_WL128X=m -+# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set -+CONFIG_VIDEO_UDA1342=m -+CONFIG_VIDEO_SONY_BTF_MPX=m -+CONFIG_VIDEO_TVP5150=m -+CONFIG_VIDEO_TW2804=m -+CONFIG_VIDEO_TW9903=m -+CONFIG_VIDEO_TW9906=m -+CONFIG_VIDEO_OV7640=m -+CONFIG_VIDEO_MT9V011=m -+CONFIG_FB=y -+CONFIG_FB_BCM2708=y -+CONFIG_FB_UDL=m -+CONFIG_FB_SSD1307=m -+CONFIG_FB_RPISENSE=m -+# CONFIG_BACKLIGHT_GENERIC is not set -+CONFIG_BACKLIGHT_RPI=m -+CONFIG_BACKLIGHT_GPIO=m -+CONFIG_FRAMEBUFFER_CONSOLE=y -+CONFIG_LOGO=y -+# CONFIG_LOGO_LINUX_MONO is not set -+# CONFIG_LOGO_LINUX_VGA16 is not set -+CONFIG_SOUND=y -+CONFIG_SND=m -+CONFIG_SND_SEQUENCER=m -+CONFIG_SND_SEQ_DUMMY=m -+CONFIG_SND_MIXER_OSS=m -+CONFIG_SND_PCM_OSS=m -+CONFIG_SND_SEQUENCER_OSS=y -+CONFIG_SND_HRTIMER=m -+CONFIG_SND_DUMMY=m -+CONFIG_SND_ALOOP=m -+CONFIG_SND_VIRMIDI=m -+CONFIG_SND_MTPAV=m -+CONFIG_SND_SERIAL_U16550=m -+CONFIG_SND_MPU401=m -+CONFIG_SND_BCM2835=m -+CONFIG_SND_USB_AUDIO=m -+CONFIG_SND_USB_UA101=m -+CONFIG_SND_USB_CAIAQ=m -+CONFIG_SND_USB_CAIAQ_INPUT=y -+CONFIG_SND_USB_6FIRE=m -+CONFIG_SND_SOC=m -+CONFIG_SND_BCM2708_SOC_I2S=m -+CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m -+CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m -+CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m -+CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m -+CONFIG_SND_BCM2708_SOC_RPI_DAC=m -+CONFIG_SND_BCM2708_SOC_RPI_PROTO=m -+CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m -+CONFIG_SND_BCM2708_SOC_RASPIDAC3=m -+CONFIG_SND_SOC_ADAU1701=m -+CONFIG_SND_SOC_WM8804_I2C=m -+CONFIG_SND_SIMPLE_CARD=m -+CONFIG_SOUND_PRIME=m -+CONFIG_HIDRAW=y -+CONFIG_UHID=m -+CONFIG_HID_A4TECH=m -+CONFIG_HID_ACRUX=m -+CONFIG_HID_APPLE=m -+CONFIG_HID_BELKIN=m -+CONFIG_HID_CHERRY=m -+CONFIG_HID_CHICONY=m -+CONFIG_HID_CYPRESS=m -+CONFIG_HID_DRAGONRISE=m -+CONFIG_HID_EMS_FF=m -+CONFIG_HID_ELECOM=m -+CONFIG_HID_ELO=m -+CONFIG_HID_EZKEY=m -+CONFIG_HID_HOLTEK=m -+CONFIG_HID_KEYTOUCH=m -+CONFIG_HID_KYE=m -+CONFIG_HID_UCLOGIC=m -+CONFIG_HID_WALTOP=m -+CONFIG_HID_GYRATION=m -+CONFIG_HID_TWINHAN=m -+CONFIG_HID_KENSINGTON=m -+CONFIG_HID_LCPOWER=m -+CONFIG_HID_LOGITECH=m -+CONFIG_HID_MAGICMOUSE=m -+CONFIG_HID_MICROSOFT=m -+CONFIG_HID_MONTEREY=m -+CONFIG_HID_MULTITOUCH=m -+CONFIG_HID_NTRIG=m -+CONFIG_HID_ORTEK=m -+CONFIG_HID_PANTHERLORD=m -+CONFIG_HID_PETALYNX=m -+CONFIG_HID_PICOLCD=m -+CONFIG_HID_ROCCAT=m -+CONFIG_HID_SAMSUNG=m -+CONFIG_HID_SONY=m -+CONFIG_HID_SPEEDLINK=m -+CONFIG_HID_SUNPLUS=m -+CONFIG_HID_GREENASIA=m -+CONFIG_HID_SMARTJOYPLUS=m -+CONFIG_HID_TOPSEED=m -+CONFIG_HID_THINGM=m -+CONFIG_HID_THRUSTMASTER=m -+CONFIG_HID_WACOM=m -+CONFIG_HID_WIIMOTE=m -+CONFIG_HID_XINMO=m -+CONFIG_HID_ZEROPLUS=m -+CONFIG_HID_ZYDACRON=m -+CONFIG_HID_PID=y -+CONFIG_USB_HIDDEV=y -+CONFIG_USB=y -+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -+CONFIG_USB_MON=m -+CONFIG_USB_DWCOTG=y -+CONFIG_USB_PRINTER=m -+CONFIG_USB_STORAGE=y -+CONFIG_USB_STORAGE_REALTEK=m -+CONFIG_USB_STORAGE_DATAFAB=m -+CONFIG_USB_STORAGE_FREECOM=m -+CONFIG_USB_STORAGE_ISD200=m -+CONFIG_USB_STORAGE_USBAT=m -+CONFIG_USB_STORAGE_SDDR09=m -+CONFIG_USB_STORAGE_SDDR55=m -+CONFIG_USB_STORAGE_JUMPSHOT=m -+CONFIG_USB_STORAGE_ALAUDA=m -+CONFIG_USB_STORAGE_ONETOUCH=m -+CONFIG_USB_STORAGE_KARMA=m -+CONFIG_USB_STORAGE_CYPRESS_ATACB=m -+CONFIG_USB_STORAGE_ENE_UB6250=m -+CONFIG_USB_MDC800=m -+CONFIG_USB_MICROTEK=m -+CONFIG_USBIP_CORE=m -+CONFIG_USBIP_VHCI_HCD=m -+CONFIG_USBIP_HOST=m -+CONFIG_USB_SERIAL=m -+CONFIG_USB_SERIAL_GENERIC=y -+CONFIG_USB_SERIAL_AIRCABLE=m -+CONFIG_USB_SERIAL_ARK3116=m -+CONFIG_USB_SERIAL_BELKIN=m -+CONFIG_USB_SERIAL_CH341=m -+CONFIG_USB_SERIAL_WHITEHEAT=m -+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m -+CONFIG_USB_SERIAL_CP210X=m -+CONFIG_USB_SERIAL_CYPRESS_M8=m -+CONFIG_USB_SERIAL_EMPEG=m -+CONFIG_USB_SERIAL_FTDI_SIO=m -+CONFIG_USB_SERIAL_VISOR=m -+CONFIG_USB_SERIAL_IPAQ=m -+CONFIG_USB_SERIAL_IR=m -+CONFIG_USB_SERIAL_EDGEPORT=m -+CONFIG_USB_SERIAL_EDGEPORT_TI=m -+CONFIG_USB_SERIAL_F81232=m -+CONFIG_USB_SERIAL_GARMIN=m -+CONFIG_USB_SERIAL_IPW=m -+CONFIG_USB_SERIAL_IUU=m -+CONFIG_USB_SERIAL_KEYSPAN_PDA=m -+CONFIG_USB_SERIAL_KEYSPAN=m -+CONFIG_USB_SERIAL_KLSI=m -+CONFIG_USB_SERIAL_KOBIL_SCT=m -+CONFIG_USB_SERIAL_MCT_U232=m -+CONFIG_USB_SERIAL_METRO=m -+CONFIG_USB_SERIAL_MOS7720=m -+CONFIG_USB_SERIAL_MOS7840=m -+CONFIG_USB_SERIAL_NAVMAN=m -+CONFIG_USB_SERIAL_PL2303=m -+CONFIG_USB_SERIAL_OTI6858=m -+CONFIG_USB_SERIAL_QCAUX=m -+CONFIG_USB_SERIAL_QUALCOMM=m -+CONFIG_USB_SERIAL_SPCP8X5=m -+CONFIG_USB_SERIAL_SAFE=m -+CONFIG_USB_SERIAL_SIERRAWIRELESS=m -+CONFIG_USB_SERIAL_SYMBOL=m -+CONFIG_USB_SERIAL_TI=m -+CONFIG_USB_SERIAL_CYBERJACK=m -+CONFIG_USB_SERIAL_XIRCOM=m -+CONFIG_USB_SERIAL_OPTION=m -+CONFIG_USB_SERIAL_OMNINET=m -+CONFIG_USB_SERIAL_OPTICON=m -+CONFIG_USB_SERIAL_XSENS_MT=m -+CONFIG_USB_SERIAL_WISHBONE=m -+CONFIG_USB_SERIAL_SSU100=m -+CONFIG_USB_SERIAL_QT2=m -+CONFIG_USB_SERIAL_DEBUG=m -+CONFIG_USB_EMI62=m -+CONFIG_USB_EMI26=m -+CONFIG_USB_ADUTUX=m -+CONFIG_USB_SEVSEG=m -+CONFIG_USB_RIO500=m -+CONFIG_USB_LEGOTOWER=m -+CONFIG_USB_LCD=m -+CONFIG_USB_LED=m -+CONFIG_USB_CYPRESS_CY7C63=m -+CONFIG_USB_CYTHERM=m -+CONFIG_USB_IDMOUSE=m -+CONFIG_USB_FTDI_ELAN=m -+CONFIG_USB_APPLEDISPLAY=m -+CONFIG_USB_LD=m -+CONFIG_USB_TRANCEVIBRATOR=m -+CONFIG_USB_IOWARRIOR=m -+CONFIG_USB_TEST=m -+CONFIG_USB_ISIGHTFW=m -+CONFIG_USB_YUREX=m -+CONFIG_USB_ATM=m -+CONFIG_USB_SPEEDTOUCH=m -+CONFIG_USB_CXACRU=m -+CONFIG_USB_UEAGLEATM=m -+CONFIG_USB_XUSBATM=m -+CONFIG_MMC=y -+CONFIG_MMC_BLOCK_MINORS=32 -+CONFIG_MMC_BCM2835=y -+CONFIG_MMC_BCM2835_DMA=y -+CONFIG_MMC_BCM2835_SDHOST=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_PLTFM=y -+CONFIG_MMC_SPI=m -+CONFIG_LEDS_CLASS=y -+CONFIG_LEDS_GPIO=y -+CONFIG_LEDS_TRIGGER_TIMER=y -+CONFIG_LEDS_TRIGGER_ONESHOT=y -+CONFIG_LEDS_TRIGGER_HEARTBEAT=y -+CONFIG_LEDS_TRIGGER_BACKLIGHT=y -+CONFIG_LEDS_TRIGGER_CPU=y -+CONFIG_LEDS_TRIGGER_GPIO=y -+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y -+CONFIG_LEDS_TRIGGER_TRANSIENT=m -+CONFIG_LEDS_TRIGGER_CAMERA=m -+CONFIG_LEDS_TRIGGER_INPUT=y -+CONFIG_RTC_CLASS=y -+# CONFIG_RTC_HCTOSYS is not set -+CONFIG_RTC_DRV_DS1307=m -+CONFIG_RTC_DRV_DS1374=m -+CONFIG_RTC_DRV_DS1672=m -+CONFIG_RTC_DRV_DS3232=m -+CONFIG_RTC_DRV_MAX6900=m -+CONFIG_RTC_DRV_RS5C372=m -+CONFIG_RTC_DRV_ISL1208=m -+CONFIG_RTC_DRV_ISL12022=m -+CONFIG_RTC_DRV_ISL12057=m -+CONFIG_RTC_DRV_X1205=m -+CONFIG_RTC_DRV_PCF2127=m -+CONFIG_RTC_DRV_PCF8523=m -+CONFIG_RTC_DRV_PCF8563=m -+CONFIG_RTC_DRV_PCF8583=m -+CONFIG_RTC_DRV_M41T80=m -+CONFIG_RTC_DRV_BQ32K=m -+CONFIG_RTC_DRV_S35390A=m -+CONFIG_RTC_DRV_FM3130=m -+CONFIG_RTC_DRV_RX8581=m -+CONFIG_RTC_DRV_RX8025=m -+CONFIG_RTC_DRV_EM3027=m -+CONFIG_RTC_DRV_RV3029C2=m -+CONFIG_RTC_DRV_M41T93=m -+CONFIG_RTC_DRV_M41T94=m -+CONFIG_RTC_DRV_DS1305=m -+CONFIG_RTC_DRV_DS1390=m -+CONFIG_RTC_DRV_MAX6902=m -+CONFIG_RTC_DRV_R9701=m -+CONFIG_RTC_DRV_RS5C348=m -+CONFIG_RTC_DRV_DS3234=m -+CONFIG_RTC_DRV_PCF2123=m -+CONFIG_RTC_DRV_RX4581=m -+CONFIG_DMADEVICES=y -+CONFIG_DMA_BCM2708=y -+CONFIG_UIO=m -+CONFIG_UIO_PDRV_GENIRQ=m -+CONFIG_STAGING=y -+CONFIG_PRISM2_USB=m -+CONFIG_R8712U=m -+CONFIG_R8188EU=m -+CONFIG_R8723AU=m -+CONFIG_VT6656=m -+CONFIG_SPEAKUP=m -+CONFIG_SPEAKUP_SYNTH_SOFT=m -+CONFIG_STAGING_MEDIA=y -+CONFIG_LIRC_STAGING=y -+CONFIG_LIRC_IMON=m -+CONFIG_LIRC_RPI=m -+CONFIG_LIRC_SASEM=m -+CONFIG_LIRC_SERIAL=m -+CONFIG_FB_TFT=m -+CONFIG_FB_TFT_AGM1264K_FL=m -+CONFIG_FB_TFT_BD663474=m -+CONFIG_FB_TFT_HX8340BN=m -+CONFIG_FB_TFT_HX8347D=m -+CONFIG_FB_TFT_HX8353D=m -+CONFIG_FB_TFT_ILI9163=m -+CONFIG_FB_TFT_ILI9320=m -+CONFIG_FB_TFT_ILI9325=m -+CONFIG_FB_TFT_ILI9340=m -+CONFIG_FB_TFT_ILI9341=m -+CONFIG_FB_TFT_ILI9481=m -+CONFIG_FB_TFT_ILI9486=m -+CONFIG_FB_TFT_PCD8544=m -+CONFIG_FB_TFT_RA8875=m -+CONFIG_FB_TFT_S6D02A1=m -+CONFIG_FB_TFT_S6D1121=m -+CONFIG_FB_TFT_SSD1289=m -+CONFIG_FB_TFT_SSD1306=m -+CONFIG_FB_TFT_SSD1331=m -+CONFIG_FB_TFT_SSD1351=m -+CONFIG_FB_TFT_ST7735R=m -+CONFIG_FB_TFT_TINYLCD=m -+CONFIG_FB_TFT_TLS8204=m -+CONFIG_FB_TFT_UC1701=m -+CONFIG_FB_TFT_UPD161704=m -+CONFIG_FB_TFT_WATTEROTT=m -+CONFIG_FB_FLEX=m -+CONFIG_FB_TFT_FBTFT_DEVICE=m -+CONFIG_MAILBOX=y -+CONFIG_BCM2835_MBOX=y -+# CONFIG_IOMMU_SUPPORT is not set -+CONFIG_EXTCON=m -+CONFIG_EXTCON_ARIZONA=m -+CONFIG_IIO=m -+CONFIG_IIO_BUFFER=y -+CONFIG_IIO_BUFFER_CB=y -+CONFIG_IIO_KFIFO_BUF=m -+CONFIG_MCP320X=m -+CONFIG_DHT11=m -+CONFIG_PWM_BCM2835=m -+CONFIG_RASPBERRYPI_FIRMWARE=y -+CONFIG_EXT4_FS=y -+CONFIG_EXT4_FS_POSIX_ACL=y -+CONFIG_EXT4_FS_SECURITY=y -+CONFIG_REISERFS_FS=m -+CONFIG_REISERFS_FS_XATTR=y -+CONFIG_REISERFS_FS_POSIX_ACL=y -+CONFIG_REISERFS_FS_SECURITY=y -+CONFIG_JFS_FS=m -+CONFIG_JFS_POSIX_ACL=y -+CONFIG_JFS_SECURITY=y -+CONFIG_JFS_STATISTICS=y -+CONFIG_XFS_FS=m -+CONFIG_XFS_QUOTA=y -+CONFIG_XFS_POSIX_ACL=y -+CONFIG_XFS_RT=y -+CONFIG_GFS2_FS=m -+CONFIG_OCFS2_FS=m -+CONFIG_BTRFS_FS=m -+CONFIG_BTRFS_FS_POSIX_ACL=y -+CONFIG_NILFS2_FS=m -+CONFIG_F2FS_FS=y -+CONFIG_FANOTIFY=y -+CONFIG_QFMT_V1=m -+CONFIG_QFMT_V2=m -+CONFIG_AUTOFS4_FS=y -+CONFIG_FUSE_FS=m -+CONFIG_CUSE=m -+CONFIG_OVERLAY_FS=m -+CONFIG_FSCACHE=y -+CONFIG_FSCACHE_STATS=y -+CONFIG_FSCACHE_HISTOGRAM=y -+CONFIG_CACHEFILES=y -+CONFIG_ISO9660_FS=m -+CONFIG_JOLIET=y -+CONFIG_ZISOFS=y -+CONFIG_UDF_FS=m -+CONFIG_MSDOS_FS=y -+CONFIG_VFAT_FS=y -+CONFIG_FAT_DEFAULT_IOCHARSET="ascii" -+CONFIG_NTFS_FS=m -+CONFIG_NTFS_RW=y -+CONFIG_TMPFS=y -+CONFIG_TMPFS_POSIX_ACL=y -+CONFIG_CONFIGFS_FS=y -+CONFIG_ECRYPT_FS=m -+CONFIG_HFS_FS=m -+CONFIG_HFSPLUS_FS=m -+CONFIG_JFFS2_FS=m -+CONFIG_JFFS2_SUMMARY=y -+CONFIG_UBIFS_FS=m -+CONFIG_SQUASHFS=m -+CONFIG_SQUASHFS_XATTR=y -+CONFIG_SQUASHFS_LZO=y -+CONFIG_SQUASHFS_XZ=y -+CONFIG_NFS_FS=y -+CONFIG_NFS_V3_ACL=y -+CONFIG_NFS_V4=y -+CONFIG_NFS_SWAP=y -+CONFIG_ROOT_NFS=y -+CONFIG_NFS_FSCACHE=y -+CONFIG_NFSD=m -+CONFIG_NFSD_V3_ACL=y -+CONFIG_NFSD_V4=y -+CONFIG_CIFS=m -+CONFIG_CIFS_WEAK_PW_HASH=y -+CONFIG_CIFS_UPCALL=y -+CONFIG_CIFS_XATTR=y -+CONFIG_CIFS_POSIX=y -+CONFIG_CIFS_ACL=y -+CONFIG_CIFS_DFS_UPCALL=y -+CONFIG_CIFS_SMB2=y -+CONFIG_CIFS_FSCACHE=y -+CONFIG_9P_FS=m -+CONFIG_9P_FS_POSIX_ACL=y -+CONFIG_NLS_DEFAULT="utf8" -+CONFIG_NLS_CODEPAGE_437=y -+CONFIG_NLS_CODEPAGE_737=m -+CONFIG_NLS_CODEPAGE_775=m -+CONFIG_NLS_CODEPAGE_850=m -+CONFIG_NLS_CODEPAGE_852=m -+CONFIG_NLS_CODEPAGE_855=m -+CONFIG_NLS_CODEPAGE_857=m -+CONFIG_NLS_CODEPAGE_860=m -+CONFIG_NLS_CODEPAGE_861=m -+CONFIG_NLS_CODEPAGE_862=m -+CONFIG_NLS_CODEPAGE_863=m -+CONFIG_NLS_CODEPAGE_864=m -+CONFIG_NLS_CODEPAGE_865=m -+CONFIG_NLS_CODEPAGE_866=m -+CONFIG_NLS_CODEPAGE_869=m -+CONFIG_NLS_CODEPAGE_936=m -+CONFIG_NLS_CODEPAGE_950=m -+CONFIG_NLS_CODEPAGE_932=m -+CONFIG_NLS_CODEPAGE_949=m -+CONFIG_NLS_CODEPAGE_874=m -+CONFIG_NLS_ISO8859_8=m -+CONFIG_NLS_CODEPAGE_1250=m -+CONFIG_NLS_CODEPAGE_1251=m -+CONFIG_NLS_ASCII=y -+CONFIG_NLS_ISO8859_1=m -+CONFIG_NLS_ISO8859_2=m -+CONFIG_NLS_ISO8859_3=m -+CONFIG_NLS_ISO8859_4=m -+CONFIG_NLS_ISO8859_5=m -+CONFIG_NLS_ISO8859_6=m -+CONFIG_NLS_ISO8859_7=m -+CONFIG_NLS_ISO8859_9=m -+CONFIG_NLS_ISO8859_13=m -+CONFIG_NLS_ISO8859_14=m -+CONFIG_NLS_ISO8859_15=m -+CONFIG_NLS_KOI8_R=m -+CONFIG_NLS_KOI8_U=m -+CONFIG_DLM=m -+CONFIG_PRINTK_TIME=y -+CONFIG_BOOT_PRINTK_DELAY=y -+CONFIG_DEBUG_MEMORY_INIT=y -+CONFIG_DETECT_HUNG_TASK=y -+CONFIG_TIMER_STATS=y -+# CONFIG_DEBUG_PREEMPT is not set -+CONFIG_LATENCYTOP=y -+CONFIG_IRQSOFF_TRACER=y -+CONFIG_SCHED_TRACER=y -+CONFIG_STACK_TRACER=y -+CONFIG_BLK_DEV_IO_TRACE=y -+# CONFIG_KPROBE_EVENT is not set -+CONFIG_FUNCTION_PROFILER=y -+CONFIG_KGDB=y -+CONFIG_KGDB_KDB=y -+CONFIG_KDB_KEYBOARD=y -+CONFIG_CRYPTO_USER=m -+CONFIG_CRYPTO_CRYPTD=m -+CONFIG_CRYPTO_CBC=y -+CONFIG_CRYPTO_CTS=m -+CONFIG_CRYPTO_XTS=m -+CONFIG_CRYPTO_XCBC=m -+CONFIG_CRYPTO_SHA512=m -+CONFIG_CRYPTO_TGR192=m -+CONFIG_CRYPTO_WP512=m -+CONFIG_CRYPTO_CAST5=m -+CONFIG_CRYPTO_DES=y -+# CONFIG_CRYPTO_ANSI_CPRNG is not set -+CONFIG_CRYPTO_USER_API_SKCIPHER=m -+# CONFIG_CRYPTO_HW is not set -+CONFIG_ARM_CRYPTO=y -+CONFIG_CRYPTO_SHA1_ARM=m -+CONFIG_CRYPTO_AES_ARM=m -+CONFIG_CRC_ITU_T=y -+CONFIG_LIBCRC32C=y -diff -Nur linux-4.1.13.orig/arch/arm/include/asm/entry-macro-multi.S linux-rpi/arch/arm/include/asm/entry-macro-multi.S ---- linux-4.1.13.orig/arch/arm/include/asm/entry-macro-multi.S 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/arch/arm/include/asm/entry-macro-multi.S 2015-11-29 09:42:34.731443387 +0100 -@@ -1,5 +1,6 @@ - #include - -+#ifndef CONFIG_ARCH_BCM2709 - /* - * Interrupt handling. Preserves r7, r8, r9 - */ -@@ -28,6 +29,7 @@ - #endif - 9997: - .endm -+#endif - - .macro arch_irq_handler, symbol_name - .align 5 -diff -Nur linux-4.1.13.orig/arch/arm/include/asm/irqflags.h linux-rpi/arch/arm/include/asm/irqflags.h ---- linux-4.1.13.orig/arch/arm/include/asm/irqflags.h 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/arch/arm/include/asm/irqflags.h 2015-11-29 09:42:34.735443122 +0100 -@@ -145,12 +145,22 @@ - } - - /* -- * restore saved IRQ & FIQ state -+ * restore saved IRQ state - */ - static inline void arch_local_irq_restore(unsigned long flags) - { -- asm volatile( -- " msr " IRQMASK_REG_NAME_W ", %0 @ local_irq_restore" -+ unsigned long temp = 0; -+ flags &= ~(1 << 6); -+ asm volatile ( -+ " mrs %0, cpsr" -+ : "=r" (temp) -+ : -+ : "memory", "cc"); -+ /* Preserve FIQ bit */ -+ temp &= (1 << 6); -+ flags = flags | temp; -+ asm volatile ( -+ " msr cpsr_c, %0 @ local_irq_restore" - : - : "r" (flags) - : "memory", "cc"); -diff -Nur linux-4.1.13.orig/arch/arm/include/asm/string.h linux-rpi/arch/arm/include/asm/string.h ---- linux-4.1.13.orig/arch/arm/include/asm/string.h 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/arch/arm/include/asm/string.h 2015-11-29 09:42:34.739442856 +0100 -@@ -24,6 +24,11 @@ - #define __HAVE_ARCH_MEMSET - extern void * memset(void *, int, __kernel_size_t); - -+#ifdef CONFIG_MACH_BCM2708 -+#define __HAVE_ARCH_MEMCMP -+extern int memcmp(const void *, const void *, size_t); -+#endif -+ - extern void __memzero(void *ptr, __kernel_size_t n); - - #define memset(p,v,n) \ -diff -Nur linux-4.1.13.orig/arch/arm/include/asm/uaccess.h linux-rpi/arch/arm/include/asm/uaccess.h ---- linux-4.1.13.orig/arch/arm/include/asm/uaccess.h 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/arch/arm/include/asm/uaccess.h 2015-11-29 09:42:34.739442856 +0100 -@@ -475,6 +475,7 @@ - - #ifdef CONFIG_MMU - extern unsigned long __must_check __copy_from_user(void *to, const void __user *from, unsigned long n); -+extern unsigned long __must_check __copy_from_user_std(void *to, const void __user *from, unsigned long n); - extern unsigned long __must_check __copy_to_user(void __user *to, const void *from, unsigned long n); - extern unsigned long __must_check __copy_to_user_std(void __user *to, const void *from, unsigned long n); - extern unsigned long __must_check __clear_user(void __user *addr, unsigned long n); -diff -Nur linux-4.1.13.orig/arch/arm/Kconfig linux-rpi/arch/arm/Kconfig ---- linux-4.1.13.orig/arch/arm/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/arch/arm/Kconfig 2015-11-29 09:42:34.555455081 +0100 -@@ -314,6 +314,42 @@ - default ARCH_VERSATILE if !MMU - default ARCH_MULTIPLATFORM if MMU - -+config ARCH_BCM2708 -+ bool "Broadcom BCM2708 family" -+ select CPU_V6 -+ select ARM_AMBA -+ select HAVE_SCHED_CLOCK -+ select NEED_MACH_GPIO_H -+ select NEED_MACH_MEMORY_H -+ select COMMON_CLK -+ select ARCH_HAS_CPUFREQ -+ select GENERIC_CLOCKEVENTS -+ select ARM_ERRATA_411920 -+ select MACH_BCM2708 -+ select VC4 -+ select FIQ -+ help -+ This enables support for Broadcom BCM2708 boards. -+ -+config ARCH_BCM2709 -+ bool "Broadcom BCM2709 family" -+ select ARCH_HAS_BARRIERS if SMP -+ select CPU_V7 -+ select HAVE_SMP -+ select ARM_AMBA -+ select MIGHT_HAVE_CACHE_L2X0 -+ select HAVE_SCHED_CLOCK -+ select NEED_MACH_MEMORY_H -+ select NEED_MACH_IO_H -+ select COMMON_CLK -+ select ARCH_HAS_CPUFREQ -+ select GENERIC_CLOCKEVENTS -+ select MACH_BCM2709 -+ select VC4 -+ select FIQ -+ help -+ This enables support for Broadcom BCM2709 boards. -+ - config ARCH_MULTIPLATFORM - bool "Allow multiple platforms to be selected" - depends on MMU -@@ -824,6 +860,9 @@ - # Kconfigs may be included either alphabetically (according to the - # plat- suffix) or along side the corresponding mach-* source. - # -+source "arch/arm/mach-bcm2708/Kconfig" -+source "arch/arm/mach-bcm2709/Kconfig" -+ - source "arch/arm/mach-mvebu/Kconfig" - - source "arch/arm/mach-alpine/Kconfig" -diff -Nur linux-4.1.13.orig/arch/arm/Kconfig.debug linux-rpi/arch/arm/Kconfig.debug ---- linux-4.1.13.orig/arch/arm/Kconfig.debug 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/arch/arm/Kconfig.debug 2015-11-29 09:42:34.559454815 +0100 -@@ -1197,6 +1197,14 @@ - options; the platform specific options are deprecated - and will be soon removed. - -+ config DEBUG_BCM2708_UART0 -+ bool "Broadcom BCM2708 UART0 (PL011)" -+ depends on MACH_BCM2708 -+ help -+ Say Y here if you want the debug print routines to direct -+ their output to UART 0. The port must have been initialised -+ by the boot-loader before use. -+ - endchoice - - config DEBUG_AT91_UART -diff -Nur linux-4.1.13.orig/arch/arm/kernel/fiqasm.S linux-rpi/arch/arm/kernel/fiqasm.S ---- linux-4.1.13.orig/arch/arm/kernel/fiqasm.S 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/arch/arm/kernel/fiqasm.S 2015-11-29 09:42:34.743442590 +0100 -@@ -47,3 +47,7 @@ - mov r0, r0 @ avoid hazard prior to ARMv4 - ret lr - ENDPROC(__get_fiq_regs) -+ -+ENTRY(__FIQ_Branch) -+ mov pc, r8 -+ENDPROC(__FIQ_Branch) -diff -Nur linux-4.1.13.orig/arch/arm/kernel/head.S linux-rpi/arch/arm/kernel/head.S ---- linux-4.1.13.orig/arch/arm/kernel/head.S 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/arch/arm/kernel/head.S 2015-11-29 09:42:34.747442324 +0100 -@@ -680,6 +680,14 @@ - ldrcc r7, [r4], #4 @ use branch for delay slot - bcc 1b - ret lr -+ nop -+ nop -+ nop -+ nop -+ nop -+ nop -+ nop -+ nop - #endif - ENDPROC(__fixup_a_pv_table) - -diff -Nur linux-4.1.13.orig/arch/arm/kernel/process.c linux-rpi/arch/arm/kernel/process.c ---- linux-4.1.13.orig/arch/arm/kernel/process.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/arch/arm/kernel/process.c 2015-11-29 09:42:34.747442324 +0100 -@@ -98,6 +98,16 @@ - } - #endif - -+char bcm2708_reboot_mode = 'h'; -+ -+int __init reboot_setup(char *str) -+{ -+ bcm2708_reboot_mode = str[0]; -+ return 1; -+} -+ -+__setup("reboot=", reboot_setup); -+ - void __show_regs(struct pt_regs *regs) - { - unsigned long flags; -diff -Nur linux-4.1.13.orig/arch/arm/lib/arm-mem.h linux-rpi/arch/arm/lib/arm-mem.h ---- linux-4.1.13.orig/arch/arm/lib/arm-mem.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/lib/arm-mem.h 2015-11-29 09:42:34.767440995 +0100 -@@ -0,0 +1,159 @@ -+/* -+Copyright (c) 2013, Raspberry Pi Foundation -+Copyright (c) 2013, RISC OS Open Ltd -+All rights reserved. -+ -+Redistribution and use in source and binary forms, with or without -+modification, are permitted provided that the following conditions are met: -+ * Redistributions of source code must retain the above copyright -+ notice, this list of conditions and the following disclaimer. -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ * Neither the name of the copyright holder nor the -+ names of its contributors may be used to endorse or promote products -+ derived from this software without specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY -+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+*/ -+ -+.macro myfunc fname -+ .func fname -+ .global fname -+fname: -+.endm -+ -+.macro preload_leading_step1 backwards, ptr, base -+/* If the destination is already 16-byte aligned, then we need to preload -+ * between 0 and prefetch_distance (inclusive) cache lines ahead so there -+ * are no gaps when the inner loop starts. -+ */ -+ .if backwards -+ sub ptr, base, #1 -+ bic ptr, ptr, #31 -+ .else -+ bic ptr, base, #31 -+ .endif -+ .set OFFSET, 0 -+ .rept prefetch_distance+1 -+ pld [ptr, #OFFSET] -+ .if backwards -+ .set OFFSET, OFFSET-32 -+ .else -+ .set OFFSET, OFFSET+32 -+ .endif -+ .endr -+.endm -+ -+.macro preload_leading_step2 backwards, ptr, base, leading_bytes, tmp -+/* However, if the destination is not 16-byte aligned, we may need to -+ * preload one more cache line than that. The question we need to ask is: -+ * are the leading bytes more than the amount by which the source -+ * pointer will be rounded down for preloading, and if so, by how many -+ * cache lines? -+ */ -+ .if backwards -+/* Here we compare against how many bytes we are into the -+ * cache line, counting down from the highest such address. -+ * Effectively, we want to calculate -+ * leading_bytes = dst&15 -+ * cacheline_offset = 31-((src-leading_bytes-1)&31) -+ * extra_needed = leading_bytes - cacheline_offset -+ * and test if extra_needed is <= 0, or rearranging: -+ * leading_bytes + (src-leading_bytes-1)&31 <= 31 -+ */ -+ mov tmp, base, lsl #32-5 -+ sbc tmp, tmp, leading_bytes, lsl #32-5 -+ adds tmp, tmp, leading_bytes, lsl #32-5 -+ bcc 61f -+ pld [ptr, #-32*(prefetch_distance+1)] -+ .else -+/* Effectively, we want to calculate -+ * leading_bytes = (-dst)&15 -+ * cacheline_offset = (src+leading_bytes)&31 -+ * extra_needed = leading_bytes - cacheline_offset -+ * and test if extra_needed is <= 0. -+ */ -+ mov tmp, base, lsl #32-5 -+ add tmp, tmp, leading_bytes, lsl #32-5 -+ rsbs tmp, tmp, leading_bytes, lsl #32-5 -+ bls 61f -+ pld [ptr, #32*(prefetch_distance+1)] -+ .endif -+61: -+.endm -+ -+.macro preload_trailing backwards, base, remain, tmp -+ /* We need either 0, 1 or 2 extra preloads */ -+ .if backwards -+ rsb tmp, base, #0 -+ mov tmp, tmp, lsl #32-5 -+ .else -+ mov tmp, base, lsl #32-5 -+ .endif -+ adds tmp, tmp, remain, lsl #32-5 -+ adceqs tmp, tmp, #0 -+ /* The instruction above has two effects: ensures Z is only -+ * set if C was clear (so Z indicates that both shifted quantities -+ * were 0), and clears C if Z was set (so C indicates that the sum -+ * of the shifted quantities was greater and not equal to 32) */ -+ beq 82f -+ .if backwards -+ sub tmp, base, #1 -+ bic tmp, tmp, #31 -+ .else -+ bic tmp, base, #31 -+ .endif -+ bcc 81f -+ .if backwards -+ pld [tmp, #-32*(prefetch_distance+1)] -+81: -+ pld [tmp, #-32*prefetch_distance] -+ .else -+ pld [tmp, #32*(prefetch_distance+2)] -+81: -+ pld [tmp, #32*(prefetch_distance+1)] -+ .endif -+82: -+.endm -+ -+.macro preload_all backwards, narrow_case, shift, base, remain, tmp0, tmp1 -+ .if backwards -+ sub tmp0, base, #1 -+ bic tmp0, tmp0, #31 -+ pld [tmp0] -+ sub tmp1, base, remain, lsl #shift -+ .else -+ bic tmp0, base, #31 -+ pld [tmp0] -+ add tmp1, base, remain, lsl #shift -+ sub tmp1, tmp1, #1 -+ .endif -+ bic tmp1, tmp1, #31 -+ cmp tmp1, tmp0 -+ beq 92f -+ .if narrow_case -+ /* In this case, all the data fits in either 1 or 2 cache lines */ -+ pld [tmp1] -+ .else -+91: -+ .if backwards -+ sub tmp0, tmp0, #32 -+ .else -+ add tmp0, tmp0, #32 -+ .endif -+ cmp tmp0, tmp1 -+ pld [tmp0] -+ bne 91b -+ .endif -+92: -+.endm -diff -Nur linux-4.1.13.orig/arch/arm/lib/copy_from_user.S linux-rpi/arch/arm/lib/copy_from_user.S ---- linux-4.1.13.orig/arch/arm/lib/copy_from_user.S 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/arch/arm/lib/copy_from_user.S 2015-11-29 09:42:34.767440995 +0100 -@@ -89,11 +89,13 @@ - - .text - --ENTRY(__copy_from_user) -+ENTRY(__copy_from_user_std) -+WEAK(__copy_from_user) - - #include "copy_template.S" - - ENDPROC(__copy_from_user) -+ENDPROC(__copy_from_user_std) - - .pushsection .fixup,"ax" - .align 0 -diff -Nur linux-4.1.13.orig/arch/arm/lib/exports_rpi.c linux-rpi/arch/arm/lib/exports_rpi.c ---- linux-4.1.13.orig/arch/arm/lib/exports_rpi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/lib/exports_rpi.c 2015-11-29 09:42:34.771440730 +0100 -@@ -0,0 +1,37 @@ -+/** -+ * Copyright (c) 2014, Raspberry Pi (Trading) Ltd. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+#include -+ -+EXPORT_SYMBOL(memcmp); -diff -Nur linux-4.1.13.orig/arch/arm/lib/Makefile linux-rpi/arch/arm/lib/Makefile ---- linux-4.1.13.orig/arch/arm/lib/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/arch/arm/lib/Makefile 2015-11-29 09:42:34.767440995 +0100 -@@ -6,9 +6,8 @@ - - lib-y := backtrace.o changebit.o csumipv6.o csumpartial.o \ - csumpartialcopy.o csumpartialcopyuser.o clearbit.o \ -- delay.o delay-loop.o findbit.o memchr.o memcpy.o \ -- memmove.o memset.o memzero.o setbit.o \ -- strchr.o strrchr.o \ -+ delay.o delay-loop.o findbit.o memchr.o memzero.o \ -+ setbit.o strchr.o strrchr.o \ - testchangebit.o testclearbit.o testsetbit.o \ - ashldi3.o ashrdi3.o lshrdi3.o muldi3.o \ - ucmpdi2.o lib1funcs.o div64.o \ -@@ -18,6 +17,16 @@ - mmu-y := clear_user.o copy_page.o getuser.o putuser.o \ - copy_from_user.o copy_to_user.o - -+# Choose optimised implementations for Raspberry Pi -+ifeq ($(CONFIG_MACH_BCM2708),y) -+ CFLAGS_uaccess_with_memcpy.o += -DCOPY_FROM_USER_THRESHOLD=1600 -+ CFLAGS_uaccess_with_memcpy.o += -DCOPY_TO_USER_THRESHOLD=672 -+ obj-$(CONFIG_MODULES) += exports_rpi.o -+ lib-y += memcpy_rpi.o memmove_rpi.o memset_rpi.o memcmp_rpi.o -+else -+ lib-y += memcpy.o memmove.o memset.o -+endif -+ - # using lib_ here won't override already available weak symbols - obj-$(CONFIG_UACCESS_WITH_MEMCPY) += uaccess_with_memcpy.o - -diff -Nur linux-4.1.13.orig/arch/arm/lib/memcmp_rpi.S linux-rpi/arch/arm/lib/memcmp_rpi.S ---- linux-4.1.13.orig/arch/arm/lib/memcmp_rpi.S 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/lib/memcmp_rpi.S 2015-11-29 09:42:34.771440730 +0100 -@@ -0,0 +1,285 @@ -+/* -+Copyright (c) 2013, Raspberry Pi Foundation -+Copyright (c) 2013, RISC OS Open Ltd -+All rights reserved. -+ -+Redistribution and use in source and binary forms, with or without -+modification, are permitted provided that the following conditions are met: -+ * Redistributions of source code must retain the above copyright -+ notice, this list of conditions and the following disclaimer. -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ * Neither the name of the copyright holder nor the -+ names of its contributors may be used to endorse or promote products -+ derived from this software without specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY -+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+*/ -+ -+#include -+#include "arm-mem.h" -+ -+/* Prevent the stack from becoming executable */ -+#if defined(__linux__) && defined(__ELF__) -+.section .note.GNU-stack,"",%progbits -+#endif -+ -+ .text -+ .arch armv6 -+ .object_arch armv4 -+ .arm -+ .altmacro -+ .p2align 2 -+ -+.macro memcmp_process_head unaligned -+ .if unaligned -+ ldr DAT0, [S_1], #4 -+ ldr DAT1, [S_1], #4 -+ ldr DAT2, [S_1], #4 -+ ldr DAT3, [S_1], #4 -+ .else -+ ldmia S_1!, {DAT0, DAT1, DAT2, DAT3} -+ .endif -+ ldmia S_2!, {DAT4, DAT5, DAT6, DAT7} -+.endm -+ -+.macro memcmp_process_tail -+ cmp DAT0, DAT4 -+ cmpeq DAT1, DAT5 -+ cmpeq DAT2, DAT6 -+ cmpeq DAT3, DAT7 -+ bne 200f -+.endm -+ -+.macro memcmp_leading_31bytes -+ movs DAT0, OFF, lsl #31 -+ ldrmib DAT0, [S_1], #1 -+ ldrcsh DAT1, [S_1], #2 -+ ldrmib DAT4, [S_2], #1 -+ ldrcsh DAT5, [S_2], #2 -+ movpl DAT0, #0 -+ movcc DAT1, #0 -+ movpl DAT4, #0 -+ movcc DAT5, #0 -+ submi N, N, #1 -+ subcs N, N, #2 -+ cmp DAT0, DAT4 -+ cmpeq DAT1, DAT5 -+ bne 200f -+ movs DAT0, OFF, lsl #29 -+ ldrmi DAT0, [S_1], #4 -+ ldrcs DAT1, [S_1], #4 -+ ldrcs DAT2, [S_1], #4 -+ ldrmi DAT4, [S_2], #4 -+ ldmcsia S_2!, {DAT5, DAT6} -+ movpl DAT0, #0 -+ movcc DAT1, #0 -+ movcc DAT2, #0 -+ movpl DAT4, #0 -+ movcc DAT5, #0 -+ movcc DAT6, #0 -+ submi N, N, #4 -+ subcs N, N, #8 -+ cmp DAT0, DAT4 -+ cmpeq DAT1, DAT5 -+ cmpeq DAT2, DAT6 -+ bne 200f -+ tst OFF, #16 -+ beq 105f -+ memcmp_process_head 1 -+ sub N, N, #16 -+ memcmp_process_tail -+105: -+.endm -+ -+.macro memcmp_trailing_15bytes unaligned -+ movs N, N, lsl #29 -+ .if unaligned -+ ldrcs DAT0, [S_1], #4 -+ ldrcs DAT1, [S_1], #4 -+ .else -+ ldmcsia S_1!, {DAT0, DAT1} -+ .endif -+ ldrmi DAT2, [S_1], #4 -+ ldmcsia S_2!, {DAT4, DAT5} -+ ldrmi DAT6, [S_2], #4 -+ movcc DAT0, #0 -+ movcc DAT1, #0 -+ movpl DAT2, #0 -+ movcc DAT4, #0 -+ movcc DAT5, #0 -+ movpl DAT6, #0 -+ cmp DAT0, DAT4 -+ cmpeq DAT1, DAT5 -+ cmpeq DAT2, DAT6 -+ bne 200f -+ movs N, N, lsl #2 -+ ldrcsh DAT0, [S_1], #2 -+ ldrmib DAT1, [S_1] -+ ldrcsh DAT4, [S_2], #2 -+ ldrmib DAT5, [S_2] -+ movcc DAT0, #0 -+ movpl DAT1, #0 -+ movcc DAT4, #0 -+ movpl DAT5, #0 -+ cmp DAT0, DAT4 -+ cmpeq DAT1, DAT5 -+ bne 200f -+.endm -+ -+.macro memcmp_long_inner_loop unaligned -+110: -+ memcmp_process_head unaligned -+ pld [S_2, #prefetch_distance*32 + 16] -+ memcmp_process_tail -+ memcmp_process_head unaligned -+ pld [S_1, OFF] -+ memcmp_process_tail -+ subs N, N, #32 -+ bhs 110b -+ /* Just before the final (prefetch_distance+1) 32-byte blocks, -+ * deal with final preloads */ -+ preload_trailing 0, S_1, N, DAT0 -+ preload_trailing 0, S_2, N, DAT0 -+ add N, N, #(prefetch_distance+2)*32 - 16 -+120: -+ memcmp_process_head unaligned -+ memcmp_process_tail -+ subs N, N, #16 -+ bhs 120b -+ /* Trailing words and bytes */ -+ tst N, #15 -+ beq 199f -+ memcmp_trailing_15bytes unaligned -+199: /* Reached end without detecting a difference */ -+ mov a1, #0 -+ setend le -+ pop {DAT1-DAT6, pc} -+.endm -+ -+.macro memcmp_short_inner_loop unaligned -+ subs N, N, #16 /* simplifies inner loop termination */ -+ blo 122f -+120: -+ memcmp_process_head unaligned -+ memcmp_process_tail -+ subs N, N, #16 -+ bhs 120b -+122: /* Trailing words and bytes */ -+ tst N, #15 -+ beq 199f -+ memcmp_trailing_15bytes unaligned -+199: /* Reached end without detecting a difference */ -+ mov a1, #0 -+ setend le -+ pop {DAT1-DAT6, pc} -+.endm -+ -+/* -+ * int memcmp(const void *s1, const void *s2, size_t n); -+ * On entry: -+ * a1 = pointer to buffer 1 -+ * a2 = pointer to buffer 2 -+ * a3 = number of bytes to compare (as unsigned chars) -+ * On exit: -+ * a1 = >0/=0/<0 if s1 >/=/< s2 -+ */ -+ -+.set prefetch_distance, 2 -+ -+ENTRY(memcmp) -+ S_1 .req a1 -+ S_2 .req a2 -+ N .req a3 -+ DAT0 .req a4 -+ DAT1 .req v1 -+ DAT2 .req v2 -+ DAT3 .req v3 -+ DAT4 .req v4 -+ DAT5 .req v5 -+ DAT6 .req v6 -+ DAT7 .req ip -+ OFF .req lr -+ -+ push {DAT1-DAT6, lr} -+ setend be /* lowest-addressed bytes are most significant */ -+ -+ /* To preload ahead as we go, we need at least (prefetch_distance+2) 32-byte blocks */ -+ cmp N, #(prefetch_distance+3)*32 - 1 -+ blo 170f -+ -+ /* Long case */ -+ /* Adjust N so that the decrement instruction can also test for -+ * inner loop termination. We want it to stop when there are -+ * (prefetch_distance+1) complete blocks to go. */ -+ sub N, N, #(prefetch_distance+2)*32 -+ preload_leading_step1 0, DAT0, S_1 -+ preload_leading_step1 0, DAT1, S_2 -+ tst S_2, #31 -+ beq 154f -+ rsb OFF, S_2, #0 /* no need to AND with 15 here */ -+ preload_leading_step2 0, DAT0, S_1, OFF, DAT2 -+ preload_leading_step2 0, DAT1, S_2, OFF, DAT2 -+ memcmp_leading_31bytes -+154: /* Second source now cacheline (32-byte) aligned; we have at -+ * least one prefetch to go. */ -+ /* Prefetch offset is best selected such that it lies in the -+ * first 8 of each 32 bytes - but it's just as easy to aim for -+ * the first one */ -+ and OFF, S_1, #31 -+ rsb OFF, OFF, #32*prefetch_distance -+ tst S_1, #3 -+ bne 140f -+ memcmp_long_inner_loop 0 -+140: memcmp_long_inner_loop 1 -+ -+170: /* Short case */ -+ teq N, #0 -+ beq 199f -+ preload_all 0, 0, 0, S_1, N, DAT0, DAT1 -+ preload_all 0, 0, 0, S_2, N, DAT0, DAT1 -+ tst S_2, #3 -+ beq 174f -+172: subs N, N, #1 -+ blo 199f -+ ldrb DAT0, [S_1], #1 -+ ldrb DAT4, [S_2], #1 -+ cmp DAT0, DAT4 -+ bne 200f -+ tst S_2, #3 -+ bne 172b -+174: /* Second source now 4-byte aligned; we have 0 or more bytes to go */ -+ tst S_1, #3 -+ bne 140f -+ memcmp_short_inner_loop 0 -+140: memcmp_short_inner_loop 1 -+ -+200: /* Difference found: determine sign. */ -+ movhi a1, #1 -+ movlo a1, #-1 -+ setend le -+ pop {DAT1-DAT6, pc} -+ -+ .unreq S_1 -+ .unreq S_2 -+ .unreq N -+ .unreq DAT0 -+ .unreq DAT1 -+ .unreq DAT2 -+ .unreq DAT3 -+ .unreq DAT4 -+ .unreq DAT5 -+ .unreq DAT6 -+ .unreq DAT7 -+ .unreq OFF -+ENDPROC(memcmp) -diff -Nur linux-4.1.13.orig/arch/arm/lib/memcpymove.h linux-rpi/arch/arm/lib/memcpymove.h ---- linux-4.1.13.orig/arch/arm/lib/memcpymove.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/lib/memcpymove.h 2015-11-29 09:42:34.771440730 +0100 -@@ -0,0 +1,506 @@ -+/* -+Copyright (c) 2013, Raspberry Pi Foundation -+Copyright (c) 2013, RISC OS Open Ltd -+All rights reserved. -+ -+Redistribution and use in source and binary forms, with or without -+modification, are permitted provided that the following conditions are met: -+ * Redistributions of source code must retain the above copyright -+ notice, this list of conditions and the following disclaimer. -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ * Neither the name of the copyright holder nor the -+ names of its contributors may be used to endorse or promote products -+ derived from this software without specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY -+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+*/ -+ -+.macro unaligned_words backwards, align, use_pld, words, r0, r1, r2, r3, r4, r5, r6, r7, r8 -+ .if words == 1 -+ .if backwards -+ mov r1, r0, lsl #32-align*8 -+ ldr r0, [S, #-4]! -+ orr r1, r1, r0, lsr #align*8 -+ str r1, [D, #-4]! -+ .else -+ mov r0, r1, lsr #align*8 -+ ldr r1, [S, #4]! -+ orr r0, r0, r1, lsl #32-align*8 -+ str r0, [D], #4 -+ .endif -+ .elseif words == 2 -+ .if backwards -+ ldr r1, [S, #-4]! -+ mov r2, r0, lsl #32-align*8 -+ ldr r0, [S, #-4]! -+ orr r2, r2, r1, lsr #align*8 -+ mov r1, r1, lsl #32-align*8 -+ orr r1, r1, r0, lsr #align*8 -+ stmdb D!, {r1, r2} -+ .else -+ ldr r1, [S, #4]! -+ mov r0, r2, lsr #align*8 -+ ldr r2, [S, #4]! -+ orr r0, r0, r1, lsl #32-align*8 -+ mov r1, r1, lsr #align*8 -+ orr r1, r1, r2, lsl #32-align*8 -+ stmia D!, {r0, r1} -+ .endif -+ .elseif words == 4 -+ .if backwards -+ ldmdb S!, {r2, r3} -+ mov r4, r0, lsl #32-align*8 -+ ldmdb S!, {r0, r1} -+ orr r4, r4, r3, lsr #align*8 -+ mov r3, r3, lsl #32-align*8 -+ orr r3, r3, r2, lsr #align*8 -+ mov r2, r2, lsl #32-align*8 -+ orr r2, r2, r1, lsr #align*8 -+ mov r1, r1, lsl #32-align*8 -+ orr r1, r1, r0, lsr #align*8 -+ stmdb D!, {r1, r2, r3, r4} -+ .else -+ ldmib S!, {r1, r2} -+ mov r0, r4, lsr #align*8 -+ ldmib S!, {r3, r4} -+ orr r0, r0, r1, lsl #32-align*8 -+ mov r1, r1, lsr #align*8 -+ orr r1, r1, r2, lsl #32-align*8 -+ mov r2, r2, lsr #align*8 -+ orr r2, r2, r3, lsl #32-align*8 -+ mov r3, r3, lsr #align*8 -+ orr r3, r3, r4, lsl #32-align*8 -+ stmia D!, {r0, r1, r2, r3} -+ .endif -+ .elseif words == 8 -+ .if backwards -+ ldmdb S!, {r4, r5, r6, r7} -+ mov r8, r0, lsl #32-align*8 -+ ldmdb S!, {r0, r1, r2, r3} -+ .if use_pld -+ pld [S, OFF] -+ .endif -+ orr r8, r8, r7, lsr #align*8 -+ mov r7, r7, lsl #32-align*8 -+ orr r7, r7, r6, lsr #align*8 -+ mov r6, r6, lsl #32-align*8 -+ orr r6, r6, r5, lsr #align*8 -+ mov r5, r5, lsl #32-align*8 -+ orr r5, r5, r4, lsr #align*8 -+ mov r4, r4, lsl #32-align*8 -+ orr r4, r4, r3, lsr #align*8 -+ mov r3, r3, lsl #32-align*8 -+ orr r3, r3, r2, lsr #align*8 -+ mov r2, r2, lsl #32-align*8 -+ orr r2, r2, r1, lsr #align*8 -+ mov r1, r1, lsl #32-align*8 -+ orr r1, r1, r0, lsr #align*8 -+ stmdb D!, {r5, r6, r7, r8} -+ stmdb D!, {r1, r2, r3, r4} -+ .else -+ ldmib S!, {r1, r2, r3, r4} -+ mov r0, r8, lsr #align*8 -+ ldmib S!, {r5, r6, r7, r8} -+ .if use_pld -+ pld [S, OFF] -+ .endif -+ orr r0, r0, r1, lsl #32-align*8 -+ mov r1, r1, lsr #align*8 -+ orr r1, r1, r2, lsl #32-align*8 -+ mov r2, r2, lsr #align*8 -+ orr r2, r2, r3, lsl #32-align*8 -+ mov r3, r3, lsr #align*8 -+ orr r3, r3, r4, lsl #32-align*8 -+ mov r4, r4, lsr #align*8 -+ orr r4, r4, r5, lsl #32-align*8 -+ mov r5, r5, lsr #align*8 -+ orr r5, r5, r6, lsl #32-align*8 -+ mov r6, r6, lsr #align*8 -+ orr r6, r6, r7, lsl #32-align*8 -+ mov r7, r7, lsr #align*8 -+ orr r7, r7, r8, lsl #32-align*8 -+ stmia D!, {r0, r1, r2, r3} -+ stmia D!, {r4, r5, r6, r7} -+ .endif -+ .endif -+.endm -+ -+.macro memcpy_leading_15bytes backwards, align -+ movs DAT1, DAT2, lsl #31 -+ sub N, N, DAT2 -+ .if backwards -+ ldrmib DAT0, [S, #-1]! -+ ldrcsh DAT1, [S, #-2]! -+ strmib DAT0, [D, #-1]! -+ strcsh DAT1, [D, #-2]! -+ .else -+ ldrmib DAT0, [S], #1 -+ ldrcsh DAT1, [S], #2 -+ strmib DAT0, [D], #1 -+ strcsh DAT1, [D], #2 -+ .endif -+ movs DAT1, DAT2, lsl #29 -+ .if backwards -+ ldrmi DAT0, [S, #-4]! -+ .if align == 0 -+ ldmcsdb S!, {DAT1, DAT2} -+ .else -+ ldrcs DAT2, [S, #-4]! -+ ldrcs DAT1, [S, #-4]! -+ .endif -+ strmi DAT0, [D, #-4]! -+ stmcsdb D!, {DAT1, DAT2} -+ .else -+ ldrmi DAT0, [S], #4 -+ .if align == 0 -+ ldmcsia S!, {DAT1, DAT2} -+ .else -+ ldrcs DAT1, [S], #4 -+ ldrcs DAT2, [S], #4 -+ .endif -+ strmi DAT0, [D], #4 -+ stmcsia D!, {DAT1, DAT2} -+ .endif -+.endm -+ -+.macro memcpy_trailing_15bytes backwards, align -+ movs N, N, lsl #29 -+ .if backwards -+ .if align == 0 -+ ldmcsdb S!, {DAT0, DAT1} -+ .else -+ ldrcs DAT1, [S, #-4]! -+ ldrcs DAT0, [S, #-4]! -+ .endif -+ ldrmi DAT2, [S, #-4]! -+ stmcsdb D!, {DAT0, DAT1} -+ strmi DAT2, [D, #-4]! -+ .else -+ .if align == 0 -+ ldmcsia S!, {DAT0, DAT1} -+ .else -+ ldrcs DAT0, [S], #4 -+ ldrcs DAT1, [S], #4 -+ .endif -+ ldrmi DAT2, [S], #4 -+ stmcsia D!, {DAT0, DAT1} -+ strmi DAT2, [D], #4 -+ .endif -+ movs N, N, lsl #2 -+ .if backwards -+ ldrcsh DAT0, [S, #-2]! -+ ldrmib DAT1, [S, #-1] -+ strcsh DAT0, [D, #-2]! -+ strmib DAT1, [D, #-1] -+ .else -+ ldrcsh DAT0, [S], #2 -+ ldrmib DAT1, [S] -+ strcsh DAT0, [D], #2 -+ strmib DAT1, [D] -+ .endif -+.endm -+ -+.macro memcpy_long_inner_loop backwards, align -+ .if align != 0 -+ .if backwards -+ ldr DAT0, [S, #-align]! -+ .else -+ ldr LAST, [S, #-align]! -+ .endif -+ .endif -+110: -+ .if align == 0 -+ .if backwards -+ ldmdb S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST} -+ pld [S, OFF] -+ stmdb D!, {DAT4, DAT5, DAT6, LAST} -+ stmdb D!, {DAT0, DAT1, DAT2, DAT3} -+ .else -+ ldmia S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST} -+ pld [S, OFF] -+ stmia D!, {DAT0, DAT1, DAT2, DAT3} -+ stmia D!, {DAT4, DAT5, DAT6, LAST} -+ .endif -+ .else -+ unaligned_words backwards, align, 1, 8, DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, DAT7, LAST -+ .endif -+ subs N, N, #32 -+ bhs 110b -+ /* Just before the final (prefetch_distance+1) 32-byte blocks, deal with final preloads */ -+ preload_trailing backwards, S, N, OFF -+ add N, N, #(prefetch_distance+2)*32 - 32 -+120: -+ .if align == 0 -+ .if backwards -+ ldmdb S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST} -+ stmdb D!, {DAT4, DAT5, DAT6, LAST} -+ stmdb D!, {DAT0, DAT1, DAT2, DAT3} -+ .else -+ ldmia S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST} -+ stmia D!, {DAT0, DAT1, DAT2, DAT3} -+ stmia D!, {DAT4, DAT5, DAT6, LAST} -+ .endif -+ .else -+ unaligned_words backwards, align, 0, 8, DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, DAT7, LAST -+ .endif -+ subs N, N, #32 -+ bhs 120b -+ tst N, #16 -+ .if align == 0 -+ .if backwards -+ ldmnedb S!, {DAT0, DAT1, DAT2, LAST} -+ stmnedb D!, {DAT0, DAT1, DAT2, LAST} -+ .else -+ ldmneia S!, {DAT0, DAT1, DAT2, LAST} -+ stmneia D!, {DAT0, DAT1, DAT2, LAST} -+ .endif -+ .else -+ beq 130f -+ unaligned_words backwards, align, 0, 4, DAT0, DAT1, DAT2, DAT3, LAST -+130: -+ .endif -+ /* Trailing words and bytes */ -+ tst N, #15 -+ beq 199f -+ .if align != 0 -+ add S, S, #align -+ .endif -+ memcpy_trailing_15bytes backwards, align -+199: -+ pop {DAT3, DAT4, DAT5, DAT6, DAT7} -+ pop {D, DAT1, DAT2, pc} -+.endm -+ -+.macro memcpy_medium_inner_loop backwards, align -+120: -+ .if backwards -+ .if align == 0 -+ ldmdb S!, {DAT0, DAT1, DAT2, LAST} -+ .else -+ ldr LAST, [S, #-4]! -+ ldr DAT2, [S, #-4]! -+ ldr DAT1, [S, #-4]! -+ ldr DAT0, [S, #-4]! -+ .endif -+ stmdb D!, {DAT0, DAT1, DAT2, LAST} -+ .else -+ .if align == 0 -+ ldmia S!, {DAT0, DAT1, DAT2, LAST} -+ .else -+ ldr DAT0, [S], #4 -+ ldr DAT1, [S], #4 -+ ldr DAT2, [S], #4 -+ ldr LAST, [S], #4 -+ .endif -+ stmia D!, {DAT0, DAT1, DAT2, LAST} -+ .endif -+ subs N, N, #16 -+ bhs 120b -+ /* Trailing words and bytes */ -+ tst N, #15 -+ beq 199f -+ memcpy_trailing_15bytes backwards, align -+199: -+ pop {D, DAT1, DAT2, pc} -+.endm -+ -+.macro memcpy_short_inner_loop backwards, align -+ tst N, #16 -+ .if backwards -+ .if align == 0 -+ ldmnedb S!, {DAT0, DAT1, DAT2, LAST} -+ .else -+ ldrne LAST, [S, #-4]! -+ ldrne DAT2, [S, #-4]! -+ ldrne DAT1, [S, #-4]! -+ ldrne DAT0, [S, #-4]! -+ .endif -+ stmnedb D!, {DAT0, DAT1, DAT2, LAST} -+ .else -+ .if align == 0 -+ ldmneia S!, {DAT0, DAT1, DAT2, LAST} -+ .else -+ ldrne DAT0, [S], #4 -+ ldrne DAT1, [S], #4 -+ ldrne DAT2, [S], #4 -+ ldrne LAST, [S], #4 -+ .endif -+ stmneia D!, {DAT0, DAT1, DAT2, LAST} -+ .endif -+ memcpy_trailing_15bytes backwards, align -+199: -+ pop {D, DAT1, DAT2, pc} -+.endm -+ -+.macro memcpy backwards -+ D .req a1 -+ S .req a2 -+ N .req a3 -+ DAT0 .req a4 -+ DAT1 .req v1 -+ DAT2 .req v2 -+ DAT3 .req v3 -+ DAT4 .req v4 -+ DAT5 .req v5 -+ DAT6 .req v6 -+ DAT7 .req sl -+ LAST .req ip -+ OFF .req lr -+ -+ .cfi_startproc -+ -+ push {D, DAT1, DAT2, lr} -+ -+ .cfi_def_cfa_offset 16 -+ .cfi_rel_offset D, 0 -+ .cfi_undefined S -+ .cfi_undefined N -+ .cfi_undefined DAT0 -+ .cfi_rel_offset DAT1, 4 -+ .cfi_rel_offset DAT2, 8 -+ .cfi_undefined LAST -+ .cfi_rel_offset lr, 12 -+ -+ .if backwards -+ add D, D, N -+ add S, S, N -+ .endif -+ -+ /* See if we're guaranteed to have at least one 16-byte aligned 16-byte write */ -+ cmp N, #31 -+ blo 170f -+ /* To preload ahead as we go, we need at least (prefetch_distance+2) 32-byte blocks */ -+ cmp N, #(prefetch_distance+3)*32 - 1 -+ blo 160f -+ -+ /* Long case */ -+ push {DAT3, DAT4, DAT5, DAT6, DAT7} -+ -+ .cfi_def_cfa_offset 36 -+ .cfi_rel_offset D, 20 -+ .cfi_rel_offset DAT1, 24 -+ .cfi_rel_offset DAT2, 28 -+ .cfi_rel_offset DAT3, 0 -+ .cfi_rel_offset DAT4, 4 -+ .cfi_rel_offset DAT5, 8 -+ .cfi_rel_offset DAT6, 12 -+ .cfi_rel_offset DAT7, 16 -+ .cfi_rel_offset lr, 32 -+ -+ /* Adjust N so that the decrement instruction can also test for -+ * inner loop termination. We want it to stop when there are -+ * (prefetch_distance+1) complete blocks to go. */ -+ sub N, N, #(prefetch_distance+2)*32 -+ preload_leading_step1 backwards, DAT0, S -+ .if backwards -+ /* Bug in GAS: it accepts, but mis-assembles the instruction -+ * ands DAT2, D, #60, 2 -+ * which sets DAT2 to the number of leading bytes until destination is aligned and also clears C (sets borrow) -+ */ -+ .word 0xE210513C -+ beq 154f -+ .else -+ ands DAT2, D, #15 -+ beq 154f -+ rsb DAT2, DAT2, #16 /* number of leading bytes until destination aligned */ -+ .endif -+ preload_leading_step2 backwards, DAT0, S, DAT2, OFF -+ memcpy_leading_15bytes backwards, 1 -+154: /* Destination now 16-byte aligned; we have at least one prefetch as well as at least one 16-byte output block */ -+ /* Prefetch offset is best selected such that it lies in the first 8 of each 32 bytes - but it's just as easy to aim for the first one */ -+ .if backwards -+ rsb OFF, S, #3 -+ and OFF, OFF, #28 -+ sub OFF, OFF, #32*(prefetch_distance+1) -+ .else -+ and OFF, S, #28 -+ rsb OFF, OFF, #32*prefetch_distance -+ .endif -+ movs DAT0, S, lsl #31 -+ bhi 157f -+ bcs 156f -+ bmi 155f -+ memcpy_long_inner_loop backwards, 0 -+155: memcpy_long_inner_loop backwards, 1 -+156: memcpy_long_inner_loop backwards, 2 -+157: memcpy_long_inner_loop backwards, 3 -+ -+ .cfi_def_cfa_offset 16 -+ .cfi_rel_offset D, 0 -+ .cfi_rel_offset DAT1, 4 -+ .cfi_rel_offset DAT2, 8 -+ .cfi_same_value DAT3 -+ .cfi_same_value DAT4 -+ .cfi_same_value DAT5 -+ .cfi_same_value DAT6 -+ .cfi_same_value DAT7 -+ .cfi_rel_offset lr, 12 -+ -+160: /* Medium case */ -+ preload_all backwards, 0, 0, S, N, DAT2, OFF -+ sub N, N, #16 /* simplifies inner loop termination */ -+ .if backwards -+ ands DAT2, D, #15 -+ beq 164f -+ .else -+ ands DAT2, D, #15 -+ beq 164f -+ rsb DAT2, DAT2, #16 -+ .endif -+ memcpy_leading_15bytes backwards, align -+164: /* Destination now 16-byte aligned; we have at least one 16-byte output block */ -+ tst S, #3 -+ bne 140f -+ memcpy_medium_inner_loop backwards, 0 -+140: memcpy_medium_inner_loop backwards, 1 -+ -+170: /* Short case, less than 31 bytes, so no guarantee of at least one 16-byte block */ -+ teq N, #0 -+ beq 199f -+ preload_all backwards, 1, 0, S, N, DAT2, LAST -+ tst D, #3 -+ beq 174f -+172: subs N, N, #1 -+ blo 199f -+ .if backwards -+ ldrb DAT0, [S, #-1]! -+ strb DAT0, [D, #-1]! -+ .else -+ ldrb DAT0, [S], #1 -+ strb DAT0, [D], #1 -+ .endif -+ tst D, #3 -+ bne 172b -+174: /* Destination now 4-byte aligned; we have 0 or more output bytes to go */ -+ tst S, #3 -+ bne 140f -+ memcpy_short_inner_loop backwards, 0 -+140: memcpy_short_inner_loop backwards, 1 -+ -+ .cfi_endproc -+ -+ .unreq D -+ .unreq S -+ .unreq N -+ .unreq DAT0 -+ .unreq DAT1 -+ .unreq DAT2 -+ .unreq DAT3 -+ .unreq DAT4 -+ .unreq DAT5 -+ .unreq DAT6 -+ .unreq DAT7 -+ .unreq LAST -+ .unreq OFF -+.endm -diff -Nur linux-4.1.13.orig/arch/arm/lib/memcpy_rpi.S linux-rpi/arch/arm/lib/memcpy_rpi.S ---- linux-4.1.13.orig/arch/arm/lib/memcpy_rpi.S 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/lib/memcpy_rpi.S 2015-11-29 09:42:34.771440730 +0100 -@@ -0,0 +1,59 @@ -+/* -+Copyright (c) 2013, Raspberry Pi Foundation -+Copyright (c) 2013, RISC OS Open Ltd -+All rights reserved. -+ -+Redistribution and use in source and binary forms, with or without -+modification, are permitted provided that the following conditions are met: -+ * Redistributions of source code must retain the above copyright -+ notice, this list of conditions and the following disclaimer. -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ * Neither the name of the copyright holder nor the -+ names of its contributors may be used to endorse or promote products -+ derived from this software without specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY -+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+*/ -+ -+#include -+#include "arm-mem.h" -+#include "memcpymove.h" -+ -+/* Prevent the stack from becoming executable */ -+#if defined(__linux__) && defined(__ELF__) -+.section .note.GNU-stack,"",%progbits -+#endif -+ -+ .text -+ .arch armv6 -+ .object_arch armv4 -+ .arm -+ .altmacro -+ .p2align 2 -+ -+/* -+ * void *memcpy(void * restrict s1, const void * restrict s2, size_t n); -+ * On entry: -+ * a1 = pointer to destination -+ * a2 = pointer to source -+ * a3 = number of bytes to copy -+ * On exit: -+ * a1 preserved -+ */ -+ -+.set prefetch_distance, 3 -+ -+ENTRY(memcpy) -+ memcpy 0 -+ENDPROC(memcpy) -diff -Nur linux-4.1.13.orig/arch/arm/lib/memmove_rpi.S linux-rpi/arch/arm/lib/memmove_rpi.S ---- linux-4.1.13.orig/arch/arm/lib/memmove_rpi.S 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/lib/memmove_rpi.S 2015-11-29 09:42:34.771440730 +0100 -@@ -0,0 +1,61 @@ -+/* -+Copyright (c) 2013, Raspberry Pi Foundation -+Copyright (c) 2013, RISC OS Open Ltd -+All rights reserved. -+ -+Redistribution and use in source and binary forms, with or without -+modification, are permitted provided that the following conditions are met: -+ * Redistributions of source code must retain the above copyright -+ notice, this list of conditions and the following disclaimer. -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ * Neither the name of the copyright holder nor the -+ names of its contributors may be used to endorse or promote products -+ derived from this software without specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY -+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+*/ -+ -+#include -+#include "arm-mem.h" -+#include "memcpymove.h" -+ -+/* Prevent the stack from becoming executable */ -+#if defined(__linux__) && defined(__ELF__) -+.section .note.GNU-stack,"",%progbits -+#endif -+ -+ .text -+ .arch armv6 -+ .object_arch armv4 -+ .arm -+ .altmacro -+ .p2align 2 -+ -+/* -+ * void *memmove(void *s1, const void *s2, size_t n); -+ * On entry: -+ * a1 = pointer to destination -+ * a2 = pointer to source -+ * a3 = number of bytes to copy -+ * On exit: -+ * a1 preserved -+ */ -+ -+.set prefetch_distance, 3 -+ -+ENTRY(memmove) -+ cmp a2, a1 -+ bpl memcpy /* pl works even over -1 - 0 and 0x7fffffff - 0x80000000 boundaries */ -+ memcpy 1 -+ENDPROC(memmove) -diff -Nur linux-4.1.13.orig/arch/arm/lib/memset_rpi.S linux-rpi/arch/arm/lib/memset_rpi.S ---- linux-4.1.13.orig/arch/arm/lib/memset_rpi.S 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/lib/memset_rpi.S 2015-11-29 09:42:34.771440730 +0100 -@@ -0,0 +1,121 @@ -+/* -+Copyright (c) 2013, Raspberry Pi Foundation -+Copyright (c) 2013, RISC OS Open Ltd -+All rights reserved. -+ -+Redistribution and use in source and binary forms, with or without -+modification, are permitted provided that the following conditions are met: -+ * Redistributions of source code must retain the above copyright -+ notice, this list of conditions and the following disclaimer. -+ * Redistributions in binary form must reproduce the above copyright -+ notice, this list of conditions and the following disclaimer in the -+ documentation and/or other materials provided with the distribution. -+ * Neither the name of the copyright holder nor the -+ names of its contributors may be used to endorse or promote products -+ derived from this software without specific prior written permission. -+ -+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY -+DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+*/ -+ -+#include -+#include "arm-mem.h" -+ -+/* Prevent the stack from becoming executable */ -+#if defined(__linux__) && defined(__ELF__) -+.section .note.GNU-stack,"",%progbits -+#endif -+ -+ .text -+ .arch armv6 -+ .object_arch armv4 -+ .arm -+ .altmacro -+ .p2align 2 -+ -+/* -+ * void *memset(void *s, int c, size_t n); -+ * On entry: -+ * a1 = pointer to buffer to fill -+ * a2 = byte pattern to fill with (caller-narrowed) -+ * a3 = number of bytes to fill -+ * On exit: -+ * a1 preserved -+ */ -+ENTRY(memset) -+ S .req a1 -+ DAT0 .req a2 -+ N .req a3 -+ DAT1 .req a4 -+ DAT2 .req ip -+ DAT3 .req lr -+ -+ orr DAT0, DAT0, lsl #8 -+ push {S, lr} -+ orr DAT0, DAT0, lsl #16 -+ mov DAT1, DAT0 -+ -+ /* See if we're guaranteed to have at least one 16-byte aligned 16-byte write */ -+ cmp N, #31 -+ blo 170f -+ -+161: sub N, N, #16 /* simplifies inner loop termination */ -+ /* Leading words and bytes */ -+ tst S, #15 -+ beq 164f -+ rsb DAT3, S, #0 /* bits 0-3 = number of leading bytes until aligned */ -+ movs DAT2, DAT3, lsl #31 -+ submi N, N, #1 -+ strmib DAT0, [S], #1 -+ subcs N, N, #2 -+ strcsh DAT0, [S], #2 -+ movs DAT2, DAT3, lsl #29 -+ submi N, N, #4 -+ strmi DAT0, [S], #4 -+ subcs N, N, #8 -+ stmcsia S!, {DAT0, DAT1} -+164: /* Delayed set up of DAT2 and DAT3 so we could use them as scratch registers above */ -+ mov DAT2, DAT0 -+ mov DAT3, DAT0 -+ /* Now the inner loop of 16-byte stores */ -+165: stmia S!, {DAT0, DAT1, DAT2, DAT3} -+ subs N, N, #16 -+ bhs 165b -+166: /* Trailing words and bytes */ -+ movs N, N, lsl #29 -+ stmcsia S!, {DAT0, DAT1} -+ strmi DAT0, [S], #4 -+ movs N, N, lsl #2 -+ strcsh DAT0, [S], #2 -+ strmib DAT0, [S] -+199: pop {S, pc} -+ -+170: /* Short case */ -+ mov DAT2, DAT0 -+ mov DAT3, DAT0 -+ tst S, #3 -+ beq 174f -+172: subs N, N, #1 -+ blo 199b -+ strb DAT0, [S], #1 -+ tst S, #3 -+ bne 172b -+174: tst N, #16 -+ stmneia S!, {DAT0, DAT1, DAT2, DAT3} -+ b 166b -+ -+ .unreq S -+ .unreq DAT0 -+ .unreq N -+ .unreq DAT1 -+ .unreq DAT2 -+ .unreq DAT3 -+ENDPROC(memset) -diff -Nur linux-4.1.13.orig/arch/arm/lib/uaccess_with_memcpy.c linux-rpi/arch/arm/lib/uaccess_with_memcpy.c ---- linux-4.1.13.orig/arch/arm/lib/uaccess_with_memcpy.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/arch/arm/lib/uaccess_with_memcpy.c 2015-11-29 09:42:34.771440730 +0100 -@@ -22,6 +22,14 @@ - #include - #include - -+#ifndef COPY_FROM_USER_THRESHOLD -+#define COPY_FROM_USER_THRESHOLD 64 -+#endif -+ -+#ifndef COPY_TO_USER_THRESHOLD -+#define COPY_TO_USER_THRESHOLD 64 -+#endif -+ - static int - pin_page_for_write(const void __user *_addr, pte_t **ptep, spinlock_t **ptlp) - { -@@ -85,7 +93,44 @@ - return 1; - } - --static unsigned long noinline -+static int -+pin_page_for_read(const void __user *_addr, pte_t **ptep, spinlock_t **ptlp) -+{ -+ unsigned long addr = (unsigned long)_addr; -+ pgd_t *pgd; -+ pmd_t *pmd; -+ pte_t *pte; -+ pud_t *pud; -+ spinlock_t *ptl; -+ -+ pgd = pgd_offset(current->mm, addr); -+ if (unlikely(pgd_none(*pgd) || pgd_bad(*pgd))) -+ { -+ return 0; -+ } -+ pud = pud_offset(pgd, addr); -+ if (unlikely(pud_none(*pud) || pud_bad(*pud))) -+ { -+ return 0; -+ } -+ -+ pmd = pmd_offset(pud, addr); -+ if (unlikely(pmd_none(*pmd) || pmd_bad(*pmd))) -+ return 0; -+ -+ pte = pte_offset_map_lock(current->mm, pmd, addr, &ptl); -+ if (unlikely(!pte_present(*pte) || !pte_young(*pte))) { -+ pte_unmap_unlock(pte, ptl); -+ return 0; -+ } -+ -+ *ptep = pte; -+ *ptlp = ptl; -+ -+ return 1; -+} -+ -+unsigned long noinline - __copy_to_user_memcpy(void __user *to, const void *from, unsigned long n) - { - int atomic; -@@ -135,6 +180,54 @@ - return n; - } - -+unsigned long noinline -+__copy_from_user_memcpy(void *to, const void __user *from, unsigned long n) -+{ -+ int atomic; -+ -+ if (unlikely(segment_eq(get_fs(), KERNEL_DS))) { -+ memcpy(to, (const void *)from, n); -+ return 0; -+ } -+ -+ /* the mmap semaphore is taken only if not in an atomic context */ -+ atomic = in_atomic(); -+ -+ if (!atomic) -+ down_read(¤t->mm->mmap_sem); -+ while (n) { -+ pte_t *pte; -+ spinlock_t *ptl; -+ int tocopy; -+ -+ while (!pin_page_for_read(from, &pte, &ptl)) { -+ char temp; -+ if (!atomic) -+ up_read(¤t->mm->mmap_sem); -+ if (__get_user(temp, (char __user *)from)) -+ goto out; -+ if (!atomic) -+ down_read(¤t->mm->mmap_sem); -+ } -+ -+ tocopy = (~(unsigned long)from & ~PAGE_MASK) + 1; -+ if (tocopy > n) -+ tocopy = n; -+ -+ memcpy(to, (const void *)from, tocopy); -+ to += tocopy; -+ from += tocopy; -+ n -= tocopy; -+ -+ pte_unmap_unlock(pte, ptl); -+ } -+ if (!atomic) -+ up_read(¤t->mm->mmap_sem); -+ -+out: -+ return n; -+} -+ - unsigned long - __copy_to_user(void __user *to, const void *from, unsigned long n) - { -@@ -145,10 +238,25 @@ - * With frame pointer disabled, tail call optimization kicks in - * as well making this test almost invisible. - */ -- if (n < 64) -+ if (n < COPY_TO_USER_THRESHOLD) - return __copy_to_user_std(to, from, n); - return __copy_to_user_memcpy(to, from, n); - } -+ -+unsigned long -+__copy_from_user(void *to, const void __user *from, unsigned long n) -+{ -+ /* -+ * This test is stubbed out of the main function above to keep -+ * the overhead for small copies low by avoiding a large -+ * register dump on the stack just to reload them right away. -+ * With frame pointer disabled, tail call optimization kicks in -+ * as well making this test almost invisible. -+ */ -+ if (n < COPY_FROM_USER_THRESHOLD) -+ return __copy_from_user_std(to, from, n); -+ return __copy_from_user_memcpy(to, from, n); -+} - - static unsigned long noinline - __clear_user_memset(void __user *addr, unsigned long n) -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm/board_bcm2835.c linux-rpi/arch/arm/mach-bcm/board_bcm2835.c ---- linux-4.1.13.orig/arch/arm/mach-bcm/board_bcm2835.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm/board_bcm2835.c 2015-11-29 09:42:34.787439667 +0100 -@@ -18,6 +18,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -107,6 +108,9 @@ - - static void __init bcm2835_init(void) - { -+ struct device_node *np = of_find_node_by_path("/system"); -+ u32 val; -+ u64 val64; - int ret; - - bcm2835_setup_restart(); -@@ -121,6 +125,11 @@ - pr_err("of_platform_populate failed: %d\n", ret); - BUG(); - } -+ -+ if (!of_property_read_u32(np, "linux,revision", &val)) -+ system_rev = val; -+ if (!of_property_read_u64(np, "linux,serial", &val64)) -+ system_serial_low = val64; - } - - static const char * const bcm2835_compat[] = { -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm/Kconfig linux-rpi/arch/arm/mach-bcm/Kconfig ---- linux-4.1.13.orig/arch/arm/mach-bcm/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm/Kconfig 2015-11-29 09:42:34.787439667 +0100 -@@ -114,6 +114,7 @@ - select ARM_ERRATA_411920 - select ARM_TIMER_SP804 - select CLKSRC_OF -+ select FIQ - select PINCTRL - select PINCTRL_BCM2835 - help -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/armctrl.c linux-rpi/arch/arm/mach-bcm2708/armctrl.c ---- linux-4.1.13.orig/arch/arm/mach-bcm2708/armctrl.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2708/armctrl.c 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,315 @@ -+/* -+ * linux/arch/arm/mach-bcm2708/armctrl.c -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include "armctrl.h" -+ -+/* For support of kernels >= 3.0 assume only one VIC for now*/ -+static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = { -+ INTERRUPT_VC_JPEG, -+ INTERRUPT_VC_USB, -+ INTERRUPT_VC_3D, -+ INTERRUPT_VC_DMA2, -+ INTERRUPT_VC_DMA3, -+ INTERRUPT_VC_I2C, -+ INTERRUPT_VC_SPI, -+ INTERRUPT_VC_I2SPCM, -+ INTERRUPT_VC_SDIO, -+ INTERRUPT_VC_UART, -+ INTERRUPT_VC_ARASANSDIO -+}; -+ -+static void armctrl_mask_irq(struct irq_data *d) -+{ -+ static const unsigned int disables[4] = { -+ ARM_IRQ_DIBL1, -+ ARM_IRQ_DIBL2, -+ ARM_IRQ_DIBL3, -+ 0 -+ }; -+ -+ if (d->irq >= FIQ_START) { -+ writel(0, __io_address(ARM_IRQ_FAST)); -+ } else { -+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq); -+ writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3])); -+ } -+} -+ -+static void armctrl_unmask_irq(struct irq_data *d) -+{ -+ static const unsigned int enables[4] = { -+ ARM_IRQ_ENBL1, -+ ARM_IRQ_ENBL2, -+ ARM_IRQ_ENBL3, -+ 0 -+ }; -+ -+ if (d->irq >= FIQ_START) { -+ unsigned int data = -+ (unsigned int)irq_get_chip_data(d->irq) - FIQ_START; -+ writel(0x80 | data, __io_address(ARM_IRQ_FAST)); -+ } else { -+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq); -+ writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3])); -+ } -+} -+ -+#ifdef CONFIG_OF -+ -+#define NR_IRQS_BANK0 21 -+#define NR_BANKS 3 -+#define IRQS_PER_BANK 32 -+ -+/* from drivers/irqchip/irq-bcm2835.c */ -+static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr, -+ const u32 *intspec, unsigned int intsize, -+ unsigned long *out_hwirq, unsigned int *out_type) -+{ -+ if (WARN_ON(intsize != 2)) -+ return -EINVAL; -+ -+ if (WARN_ON(intspec[0] >= NR_BANKS)) -+ return -EINVAL; -+ -+ if (WARN_ON(intspec[1] >= IRQS_PER_BANK)) -+ return -EINVAL; -+ -+ if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0)) -+ return -EINVAL; -+ -+ if (intspec[0] == 0) -+ *out_hwirq = ARM_IRQ0_BASE + intspec[1]; -+ else if (intspec[0] == 1) -+ *out_hwirq = ARM_IRQ1_BASE + intspec[1]; -+ else -+ *out_hwirq = ARM_IRQ2_BASE + intspec[1]; -+ -+ /* reverse remap_irqs[] */ -+ switch (*out_hwirq) { -+ case INTERRUPT_VC_JPEG: -+ *out_hwirq = INTERRUPT_JPEG; -+ break; -+ case INTERRUPT_VC_USB: -+ *out_hwirq = INTERRUPT_USB; -+ break; -+ case INTERRUPT_VC_3D: -+ *out_hwirq = INTERRUPT_3D; -+ break; -+ case INTERRUPT_VC_DMA2: -+ *out_hwirq = INTERRUPT_DMA2; -+ break; -+ case INTERRUPT_VC_DMA3: -+ *out_hwirq = INTERRUPT_DMA3; -+ break; -+ case INTERRUPT_VC_I2C: -+ *out_hwirq = INTERRUPT_I2C; -+ break; -+ case INTERRUPT_VC_SPI: -+ *out_hwirq = INTERRUPT_SPI; -+ break; -+ case INTERRUPT_VC_I2SPCM: -+ *out_hwirq = INTERRUPT_I2SPCM; -+ break; -+ case INTERRUPT_VC_SDIO: -+ *out_hwirq = INTERRUPT_SDIO; -+ break; -+ case INTERRUPT_VC_UART: -+ *out_hwirq = INTERRUPT_UART; -+ break; -+ case INTERRUPT_VC_ARASANSDIO: -+ *out_hwirq = INTERRUPT_ARASANSDIO; -+ break; -+ } -+ -+ *out_type = IRQ_TYPE_NONE; -+ return 0; -+} -+ -+static struct irq_domain_ops armctrl_ops = { -+ .xlate = armctrl_xlate -+}; -+ -+void __init armctrl_dt_init(void) -+{ -+ struct device_node *np; -+ struct irq_domain *domain; -+ -+ np = of_find_compatible_node(NULL, NULL, "brcm,bcm2708-armctrl-ic"); -+ if (!np) -+ return; -+ -+ domain = irq_domain_add_legacy(np, BCM2708_ALLOC_IRQS, -+ IRQ_ARMCTRL_START, 0, -+ &armctrl_ops, NULL); -+ WARN_ON(!domain); -+} -+#else -+void __init armctrl_dt_init(void) { } -+#endif /* CONFIG_OF */ -+ -+#if defined(CONFIG_PM) -+ -+/* for kernels 3.xx use the new syscore_ops apis but for older kernels use the sys dev class */ -+ -+/* Static defines -+ * struct armctrl_device - VIC PM device (< 3.xx) -+ * @sysdev: The system device which is registered. (< 3.xx) -+ * @irq: The IRQ number for the base of the VIC. -+ * @base: The register base for the VIC. -+ * @resume_sources: A bitmask of interrupts for resume. -+ * @resume_irqs: The IRQs enabled for resume. -+ * @int_select: Save for VIC_INT_SELECT. -+ * @int_enable: Save for VIC_INT_ENABLE. -+ * @soft_int: Save for VIC_INT_SOFT. -+ * @protect: Save for VIC_PROTECT. -+ */ -+struct armctrl_info { -+ void __iomem *base; -+ int irq; -+ u32 resume_sources; -+ u32 resume_irqs; -+ u32 int_select; -+ u32 int_enable; -+ u32 soft_int; -+ u32 protect; -+} armctrl; -+ -+static int armctrl_suspend(void) -+{ -+ return 0; -+} -+ -+static void armctrl_resume(void) -+{ -+ return; -+} -+ -+/** -+ * armctrl_pm_register - Register a VIC for later power management control -+ * @base: The base address of the VIC. -+ * @irq: The base IRQ for the VIC. -+ * @resume_sources: bitmask of interrupts allowed for resume sources. -+ * -+ * For older kernels (< 3.xx) do - -+ * Register the VIC with the system device tree so that it can be notified -+ * of suspend and resume requests and ensure that the correct actions are -+ * taken to re-instate the settings on resume. -+ */ -+static void __init armctrl_pm_register(void __iomem * base, unsigned int irq, -+ u32 resume_sources) -+{ -+ armctrl.base = base; -+ armctrl.resume_sources = resume_sources; -+ armctrl.irq = irq; -+} -+ -+static int armctrl_set_wake(struct irq_data *d, unsigned int on) -+{ -+ unsigned int off = d->irq & 31; -+ u32 bit = 1 << off; -+ -+ if (!(bit & armctrl.resume_sources)) -+ return -EINVAL; -+ -+ if (on) -+ armctrl.resume_irqs |= bit; -+ else -+ armctrl.resume_irqs &= ~bit; -+ -+ return 0; -+} -+ -+#else -+static inline void armctrl_pm_register(void __iomem * base, unsigned int irq, -+ u32 arg1) -+{ -+} -+ -+#define armctrl_suspend NULL -+#define armctrl_resume NULL -+#define armctrl_set_wake NULL -+#endif /* CONFIG_PM */ -+ -+static struct syscore_ops armctrl_syscore_ops = { -+ .suspend = armctrl_suspend, -+ .resume = armctrl_resume, -+}; -+ -+/** -+ * armctrl_syscore_init - initicall to register VIC pm functions -+ * -+ * This is called via late_initcall() to register -+ * the resources for the VICs due to the early -+ * nature of the VIC's registration. -+*/ -+static int __init armctrl_syscore_init(void) -+{ -+ register_syscore_ops(&armctrl_syscore_ops); -+ return 0; -+} -+ -+late_initcall(armctrl_syscore_init); -+ -+static struct irq_chip armctrl_chip = { -+ .name = "ARMCTRL", -+ .irq_ack = NULL, -+ .irq_mask = armctrl_mask_irq, -+ .irq_unmask = armctrl_unmask_irq, -+ .irq_set_wake = armctrl_set_wake, -+}; -+ -+/** -+ * armctrl_init - initialise a vectored interrupt controller -+ * @base: iomem base address -+ * @irq_start: starting interrupt number, must be muliple of 32 -+ * @armctrl_sources: bitmask of interrupt sources to allow -+ * @resume_sources: bitmask of interrupt sources to allow for resume -+ */ -+int __init armctrl_init(void __iomem * base, unsigned int irq_start, -+ u32 armctrl_sources, u32 resume_sources) -+{ -+ unsigned int irq; -+ -+ for (irq = 0; irq < BCM2708_ALLOC_IRQS; irq++) { -+ unsigned int data = irq; -+ if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO) -+ data = remap_irqs[irq - INTERRUPT_JPEG]; -+ -+ irq_set_chip(irq, &armctrl_chip); -+ irq_set_chip_data(irq, (void *)data); -+ irq_set_handler(irq, handle_level_irq); -+ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); -+ } -+ -+ armctrl_pm_register(base, irq_start, resume_sources); -+ init_FIQ(FIQ_START); -+ armctrl_dt_init(); -+ return 0; -+} -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/armctrl.h linux-rpi/arch/arm/mach-bcm2708/armctrl.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2708/armctrl.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2708/armctrl.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,27 @@ -+/* -+ * linux/arch/arm/mach-bcm2708/armctrl.h -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef __BCM2708_ARMCTRL_H -+#define __BCM2708_ARMCTRL_H -+ -+extern int __init armctrl_init(void __iomem * base, unsigned int irq_start, -+ u32 armctrl_sources, u32 resume_sources); -+ -+#endif -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/bcm2708.c linux-rpi/arch/arm/mach-bcm2708/bcm2708.c ---- linux-4.1.13.orig/arch/arm/mach-bcm2708/bcm2708.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2708/bcm2708.c 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,1162 @@ -+/* -+ * linux/arch/arm/mach-bcm2708/bcm2708.c -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include -+ -+#include "bcm2708.h" -+#include "armctrl.h" -+ -+#ifdef CONFIG_BCM_VC_CMA -+#include -+#endif -+ -+ -+/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to -+ * give us IO access only to 64Mbytes of physical memory (26 bits). We could -+ * represent this window by setting our dmamasks to 26 bits but, in fact -+ * we're not going to use addresses outside this range (they're not in real -+ * memory) so we don't bother. -+ * -+ * In the future we might include code to use this IOMMU to remap other -+ * physical addresses onto VideoCore memory then the use of 32-bits would be -+ * more legitimate. -+ */ -+#define DMA_MASK_BITS_COMMON 32 -+ -+// use GPIO 4 for the one-wire GPIO pin, if enabled -+#define W1_GPIO 4 -+// ensure one-wire GPIO pullup is disabled by default -+#define W1_PULLUP -1 -+ -+/* command line parameters */ -+static unsigned boardrev, serial; -+static unsigned uart_clock = UART0_CLOCK; -+static unsigned disk_led_gpio = 16; -+static unsigned disk_led_active_low = 1; -+static unsigned reboot_part = 0; -+static unsigned w1_gpio_pin = W1_GPIO; -+static unsigned w1_gpio_pullup = W1_PULLUP; -+static bool vc_i2c_override = false; -+static int pps_gpio_pin = -1; -+ -+static unsigned use_dt = 0; -+ -+static void __init bcm2708_init_led(void); -+ -+void __init bcm2708_init_irq(void) -+{ -+ armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0); -+} -+ -+static struct map_desc bcm2708_io_desc[] __initdata = { -+ { -+ .virtual = IO_ADDRESS(ARMCTRL_BASE), -+ .pfn = __phys_to_pfn(ARMCTRL_BASE), -+ .length = SZ_4K, -+ .type = MT_DEVICE}, -+ { -+ .virtual = IO_ADDRESS(UART0_BASE), -+ .pfn = __phys_to_pfn(UART0_BASE), -+ .length = SZ_4K, -+ .type = MT_DEVICE}, -+ { -+ .virtual = IO_ADDRESS(UART1_BASE), -+ .pfn = __phys_to_pfn(UART1_BASE), -+ .length = SZ_4K, -+ .type = MT_DEVICE}, -+ { -+ .virtual = IO_ADDRESS(DMA_BASE), -+ .pfn = __phys_to_pfn(DMA_BASE), -+ .length = SZ_4K, -+ .type = MT_DEVICE}, -+ { -+ .virtual = IO_ADDRESS(MCORE_BASE), -+ .pfn = __phys_to_pfn(MCORE_BASE), -+ .length = SZ_4K, -+ .type = MT_DEVICE}, -+ { -+ .virtual = IO_ADDRESS(ST_BASE), -+ .pfn = __phys_to_pfn(ST_BASE), -+ .length = SZ_4K, -+ .type = MT_DEVICE}, -+ { -+ .virtual = IO_ADDRESS(USB_BASE), -+ .pfn = __phys_to_pfn(USB_BASE), -+ .length = SZ_128K, -+ .type = MT_DEVICE}, -+ { -+ .virtual = IO_ADDRESS(PM_BASE), -+ .pfn = __phys_to_pfn(PM_BASE), -+ .length = SZ_4K, -+ .type = MT_DEVICE}, -+ { -+ .virtual = IO_ADDRESS(GPIO_BASE), -+ .pfn = __phys_to_pfn(GPIO_BASE), -+ .length = SZ_4K, -+ .type = MT_DEVICE} -+}; -+ -+void __init bcm2708_map_io(void) -+{ -+ iotable_init(bcm2708_io_desc, ARRAY_SIZE(bcm2708_io_desc)); -+} -+ -+/* The STC is a free running counter that increments at the rate of 1MHz */ -+#define STC_FREQ_HZ 1000000 -+ -+static inline uint32_t timer_read(void) -+{ -+ /* STC: a free running counter that increments at the rate of 1MHz */ -+ return readl(__io_address(ST_BASE + 0x04)); -+} -+ -+static unsigned long bcm2708_read_current_timer(void) -+{ -+ return timer_read(); -+} -+ -+static u64 notrace bcm2708_read_sched_clock(void) -+{ -+ return timer_read(); -+} -+ -+static cycle_t clksrc_read(struct clocksource *cs) -+{ -+ return timer_read(); -+} -+ -+static struct clocksource clocksource_stc = { -+ .name = "stc", -+ .rating = 300, -+ .read = clksrc_read, -+ .mask = CLOCKSOURCE_MASK(32), -+ .flags = CLOCK_SOURCE_IS_CONTINUOUS, -+}; -+ -+unsigned long frc_clock_ticks32(void) -+{ -+ return timer_read(); -+} -+ -+static void __init bcm2708_clocksource_init(void) -+{ -+ if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) { -+ printk(KERN_ERR "timer: failed to initialize clock " -+ "source %s\n", clocksource_stc.name); -+ } -+} -+ -+struct clk __init *bcm2708_clk_register(const char *name, unsigned long fixed_rate) -+{ -+ struct clk *clk; -+ -+ clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, -+ fixed_rate); -+ if (IS_ERR(clk)) -+ pr_err("%s not registered\n", name); -+ -+ return clk; -+} -+ -+void __init bcm2708_register_clkdev(struct clk *clk, const char *name) -+{ -+ int ret; -+ -+ ret = clk_register_clkdev(clk, NULL, name); -+ if (ret) -+ pr_err("%s alias not registered\n", name); -+} -+ -+void __init bcm2708_init_clocks(void) -+{ -+ struct clk *clk; -+ -+ clk = bcm2708_clk_register("uart0_clk", uart_clock); -+ bcm2708_register_clkdev(clk, "dev:f1"); -+ -+ clk = bcm2708_clk_register("sdhost_clk", 250000000); -+ bcm2708_register_clkdev(clk, "mmc-bcm2835.0"); -+ bcm2708_register_clkdev(clk, "bcm2708_spi.0"); -+ bcm2708_register_clkdev(clk, "bcm2708_i2c.0"); -+ bcm2708_register_clkdev(clk, "bcm2708_i2c.1"); -+} -+ -+#define UART0_IRQ { IRQ_UART, 0 /*NO_IRQ*/ } -+#define UART0_DMA { 15, 14 } -+ -+AMBA_DEVICE(uart0, "dev:f1", UART0, NULL); -+ -+static struct amba_device *amba_devs[] __initdata = { -+ &uart0_device, -+}; -+ -+static struct resource bcm2708_dmaengine_resources[] = { -+ { -+ .start = DMA_BASE, -+ .end = DMA_BASE + SZ_4K - 1, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .start = IRQ_DMA0, -+ .end = IRQ_DMA0, -+ .flags = IORESOURCE_IRQ, -+ }, { -+ .start = IRQ_DMA1, -+ .end = IRQ_DMA1, -+ .flags = IORESOURCE_IRQ, -+ }, { -+ .start = IRQ_DMA2, -+ .end = IRQ_DMA2, -+ .flags = IORESOURCE_IRQ, -+ }, { -+ .start = IRQ_DMA3, -+ .end = IRQ_DMA3, -+ .flags = IORESOURCE_IRQ, -+ }, { -+ .start = IRQ_DMA4, -+ .end = IRQ_DMA4, -+ .flags = IORESOURCE_IRQ, -+ }, { -+ .start = IRQ_DMA5, -+ .end = IRQ_DMA5, -+ .flags = IORESOURCE_IRQ, -+ }, { -+ .start = IRQ_DMA6, -+ .end = IRQ_DMA6, -+ .flags = IORESOURCE_IRQ, -+ }, { -+ .start = IRQ_DMA7, -+ .end = IRQ_DMA7, -+ .flags = IORESOURCE_IRQ, -+ }, { -+ .start = IRQ_DMA8, -+ .end = IRQ_DMA8, -+ .flags = IORESOURCE_IRQ, -+ }, { -+ .start = IRQ_DMA9, -+ .end = IRQ_DMA9, -+ .flags = IORESOURCE_IRQ, -+ }, { -+ .start = IRQ_DMA10, -+ .end = IRQ_DMA10, -+ .flags = IORESOURCE_IRQ, -+ }, { -+ .start = IRQ_DMA11, -+ .end = IRQ_DMA11, -+ .flags = IORESOURCE_IRQ, -+ }, { -+ .start = IRQ_DMA12, -+ .end = IRQ_DMA12, -+ .flags = IORESOURCE_IRQ, -+ } -+}; -+ -+static struct platform_device bcm2708_dmaengine_device = { -+ .name = "bcm2708-dmaengine", -+ .id = -1, -+ .resource = bcm2708_dmaengine_resources, -+ .num_resources = ARRAY_SIZE(bcm2708_dmaengine_resources), -+}; -+ -+#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE) -+static struct w1_gpio_platform_data w1_gpio_pdata = { -+ .pin = W1_GPIO, -+ .ext_pullup_enable_pin = W1_PULLUP, -+ .is_open_drain = 0, -+}; -+ -+static struct platform_device w1_device = { -+ .name = "w1-gpio", -+ .id = -1, -+ .dev.platform_data = &w1_gpio_pdata, -+}; -+#endif -+ -+static struct pps_gpio_platform_data pps_gpio_info = { -+ .assert_falling_edge = false, -+ .capture_clear = false, -+ .gpio_pin = -1, -+ .gpio_label = "PPS", -+}; -+ -+static struct platform_device pps_gpio_device = { -+ .name = "pps-gpio", -+ .id = PLATFORM_DEVID_NONE, -+ .dev.platform_data = &pps_gpio_info, -+}; -+ -+static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); -+ -+static struct platform_device bcm2708_fb_device = { -+ .name = "bcm2708_fb", -+ .id = -1, /* only one bcm2708_fb */ -+ .resource = NULL, -+ .num_resources = 0, -+ .dev = { -+ .dma_mask = &fb_dmamask, -+ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), -+ }, -+}; -+ -+static struct resource bcm2708_usb_resources[] = { -+ [0] = { -+ .start = USB_BASE, -+ .end = USB_BASE + SZ_128K - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = MPHI_BASE, -+ .end = MPHI_BASE + SZ_4K - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ [2] = { -+ .start = IRQ_HOSTPORT, -+ .end = IRQ_HOSTPORT, -+ .flags = IORESOURCE_IRQ, -+ }, -+ [3] = { -+ .start = IRQ_USB, -+ .end = IRQ_USB, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+ -+static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); -+ -+static struct platform_device bcm2708_usb_device = { -+ .name = "bcm2708_usb", -+ .id = -1, /* only one bcm2708_usb */ -+ .resource = bcm2708_usb_resources, -+ .num_resources = ARRAY_SIZE(bcm2708_usb_resources), -+ .dev = { -+ .dma_mask = &usb_dmamask, -+ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), -+ }, -+}; -+ -+static struct resource bcm2708_vcio_resources[] = { -+ { -+ .start = ARMCTRL_0_MAIL0_BASE, -+ .end = ARMCTRL_0_MAIL0_BASE + SZ_64 - 1, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .start = IRQ_ARM_MAILBOX, -+ .end = IRQ_ARM_MAILBOX, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static u64 vcio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); -+ -+static struct platform_device bcm2708_vcio_device = { -+ .name = "bcm2835-mbox", -+ .id = -1, /* only one VideoCore I/O area */ -+ .resource = bcm2708_vcio_resources, -+ .num_resources = ARRAY_SIZE(bcm2708_vcio_resources), -+ .dev = { -+ .dma_mask = &vcio_dmamask, -+ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), -+ }, -+}; -+ -+static u64 rpifw_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); -+ -+static struct platform_device bcm2708_rpifw_device = { -+ .name = "raspberrypi-firmware", -+ .dev = { -+ .dma_mask = &rpifw_dmamask, -+ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), -+ }, -+}; -+ -+static struct resource bcm2708_vchiq_resources[] = { -+ { -+ .start = ARMCTRL_0_BELL_BASE, -+ .end = ARMCTRL_0_BELL_BASE + 16, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .start = IRQ_ARM_DOORBELL_0, -+ .end = IRQ_ARM_DOORBELL_0, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static u64 vchiq_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); -+ -+static struct platform_device bcm2708_vchiq_device = { -+ .name = "bcm2835_vchiq", -+ .id = -1, -+ .resource = bcm2708_vchiq_resources, -+ .num_resources = ARRAY_SIZE(bcm2708_vchiq_resources), -+ .dev = { -+ .dma_mask = &vchiq_dmamask, -+ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), -+ }, -+}; -+ -+#ifdef CONFIG_BCM2708_GPIO -+#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio" -+ -+static struct resource bcm2708_gpio_resources[] = { -+ [0] = { /* general purpose I/O */ -+ .start = GPIO_BASE, -+ .end = GPIO_BASE + SZ_4K - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static u64 gpio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); -+ -+static struct platform_device bcm2708_gpio_device = { -+ .name = BCM_GPIO_DRIVER_NAME, -+ .id = -1, /* only one VideoCore I/O area */ -+ .resource = bcm2708_gpio_resources, -+ .num_resources = ARRAY_SIZE(bcm2708_gpio_resources), -+ .dev = { -+ .dma_mask = &gpio_dmamask, -+ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), -+ }, -+}; -+#endif -+ -+#ifdef CONFIG_MMC_BCM2835 /* Arasan emmc SD (new) */ -+static struct resource bcm2835_emmc_resources[] = { -+ [0] = { -+ .start = EMMC_BASE, -+ .end = EMMC_BASE + SZ_256 - 1, /* we only need this area */ -+ /* the memory map actually makes SZ_4K available */ -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = IRQ_ARASANSDIO, -+ .end = IRQ_ARASANSDIO, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static u64 bcm2835_emmc_dmamask = 0xffffffffUL; -+ -+struct platform_device bcm2835_emmc_device = { -+ .name = "mmc-bcm2835", -+ .id = 0, -+ .num_resources = ARRAY_SIZE(bcm2835_emmc_resources), -+ .resource = bcm2835_emmc_resources, -+ .dev = { -+ .dma_mask = &bcm2835_emmc_dmamask, -+ .coherent_dma_mask = 0xffffffffUL}, -+}; -+#endif /* CONFIG_MMC_BCM2835 */ -+ -+static struct platform_device bcm2708_alsa_devices[] = { -+ [0] = { -+ .name = "bcm2835_AUD0", -+ .id = 0, /* first audio device */ -+ .resource = 0, -+ .num_resources = 0, -+ }, -+ [1] = { -+ .name = "bcm2835_AUD1", -+ .id = 1, /* second audio device */ -+ .resource = 0, -+ .num_resources = 0, -+ }, -+ [2] = { -+ .name = "bcm2835_AUD2", -+ .id = 2, /* third audio device */ -+ .resource = 0, -+ .num_resources = 0, -+ }, -+ [3] = { -+ .name = "bcm2835_AUD3", -+ .id = 3, /* forth audio device */ -+ .resource = 0, -+ .num_resources = 0, -+ }, -+ [4] = { -+ .name = "bcm2835_AUD4", -+ .id = 4, /* fifth audio device */ -+ .resource = 0, -+ .num_resources = 0, -+ }, -+ [5] = { -+ .name = "bcm2835_AUD5", -+ .id = 5, /* sixth audio device */ -+ .resource = 0, -+ .num_resources = 0, -+ }, -+ [6] = { -+ .name = "bcm2835_AUD6", -+ .id = 6, /* seventh audio device */ -+ .resource = 0, -+ .num_resources = 0, -+ }, -+ [7] = { -+ .name = "bcm2835_AUD7", -+ .id = 7, /* eighth audio device */ -+ .resource = 0, -+ .num_resources = 0, -+ }, -+}; -+ -+static struct resource bcm2708_spi_resources[] = { -+ { -+ .start = SPI0_BASE, -+ .end = SPI0_BASE + SZ_256 - 1, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .start = IRQ_SPI, -+ .end = IRQ_SPI, -+ .flags = IORESOURCE_IRQ, -+ } -+}; -+ -+ -+static u64 bcm2708_spi_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); -+static struct platform_device bcm2708_spi_device = { -+ .name = "bcm2708_spi", -+ .id = 0, -+ .num_resources = ARRAY_SIZE(bcm2708_spi_resources), -+ .resource = bcm2708_spi_resources, -+ .dev = { -+ .dma_mask = &bcm2708_spi_dmamask, -+ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON)}, -+}; -+ -+#ifdef CONFIG_BCM2708_SPIDEV -+static struct spi_board_info bcm2708_spi_devices[] = { -+#ifdef CONFIG_SPI_SPIDEV -+ { -+ .modalias = "spidev", -+ .max_speed_hz = 500000, -+ .bus_num = 0, -+ .chip_select = 0, -+ .mode = SPI_MODE_0, -+ }, { -+ .modalias = "spidev", -+ .max_speed_hz = 500000, -+ .bus_num = 0, -+ .chip_select = 1, -+ .mode = SPI_MODE_0, -+ } -+#endif -+}; -+#endif -+ -+static struct resource bcm2708_bsc0_resources[] = { -+ { -+ .start = BSC0_BASE, -+ .end = BSC0_BASE + SZ_256 - 1, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .start = INTERRUPT_I2C, -+ .end = INTERRUPT_I2C, -+ .flags = IORESOURCE_IRQ, -+ } -+}; -+ -+static struct platform_device bcm2708_bsc0_device = { -+ .name = "bcm2708_i2c", -+ .id = 0, -+ .num_resources = ARRAY_SIZE(bcm2708_bsc0_resources), -+ .resource = bcm2708_bsc0_resources, -+}; -+ -+ -+static struct resource bcm2708_bsc1_resources[] = { -+ { -+ .start = BSC1_BASE, -+ .end = BSC1_BASE + SZ_256 - 1, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .start = INTERRUPT_I2C, -+ .end = INTERRUPT_I2C, -+ .flags = IORESOURCE_IRQ, -+ } -+}; -+ -+static struct platform_device bcm2708_bsc1_device = { -+ .name = "bcm2708_i2c", -+ .id = 1, -+ .num_resources = ARRAY_SIZE(bcm2708_bsc1_resources), -+ .resource = bcm2708_bsc1_resources, -+}; -+ -+static struct platform_device bcm2835_thermal_device = { -+ .name = "bcm2835_thermal", -+}; -+ -+#if defined(CONFIG_SND_BCM2708_SOC_I2S) || defined(CONFIG_SND_BCM2708_SOC_I2S_MODULE) -+static struct resource bcm2708_i2s_resources[] = { -+ { -+ .start = I2S_BASE, -+ .end = I2S_BASE + 0x20, -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .start = PCM_CLOCK_BASE, -+ .end = PCM_CLOCK_BASE + 0x02, -+ .flags = IORESOURCE_MEM, -+ } -+}; -+ -+static struct platform_device bcm2708_i2s_device = { -+ .name = "bcm2708-i2s", -+ .id = 0, -+ .num_resources = ARRAY_SIZE(bcm2708_i2s_resources), -+ .resource = bcm2708_i2s_resources, -+}; -+#endif -+ -+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC_MODULE) -+static struct platform_device snd_hifiberry_dac_device = { -+ .name = "snd-hifiberry-dac", -+ .id = 0, -+ .num_resources = 0, -+}; -+ -+static struct platform_device snd_pcm5102a_codec_device = { -+ .name = "pcm5102a-codec", -+ .id = -1, -+ .num_resources = 0, -+}; -+#endif -+ -+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS_MODULE) -+static struct platform_device snd_rpi_hifiberry_dacplus_device = { -+ .name = "snd-rpi-hifiberry-dacplus", -+ .id = 0, -+ .num_resources = 0, -+}; -+ -+static struct i2c_board_info __initdata snd_pcm512x_hbdacplus_i2c_devices[] = { -+ { -+ I2C_BOARD_INFO("pcm5122", 0x4d) -+ }, -+}; -+#endif -+ -+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI_MODULE) -+static struct platform_device snd_hifiberry_digi_device = { -+ .name = "snd-hifiberry-digi", -+ .id = 0, -+ .num_resources = 0, -+}; -+ -+static struct i2c_board_info __initdata snd_wm8804_i2c_devices[] = { -+ { -+ I2C_BOARD_INFO("wm8804", 0x3b) -+ }, -+}; -+ -+#endif -+ -+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP_MODULE) -+static struct platform_device snd_hifiberry_amp_device = { -+ .name = "snd-hifiberry-amp", -+ .id = 0, -+ .num_resources = 0, -+}; -+ -+static struct i2c_board_info __initdata snd_tas5713_i2c_devices[] = { -+ { -+ I2C_BOARD_INFO("tas5713", 0x1b) -+ }, -+}; -+#endif -+ -+#if defined(CONFIG_SND_BCM2708_SOC_RPI_DAC) || defined(CONFIG_SND_BCM2708_SOC_RPI_DAC_MODULE) -+static struct platform_device snd_rpi_dac_device = { -+ .name = "snd-rpi-dac", -+ .id = 0, -+ .num_resources = 0, -+}; -+ -+static struct platform_device snd_pcm1794a_codec_device = { -+ .name = "pcm1794a-codec", -+ .id = -1, -+ .num_resources = 0, -+}; -+#endif -+ -+ -+#if defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) || defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC_MODULE) -+static struct platform_device snd_rpi_iqaudio_dac_device = { -+ .name = "snd-rpi-iqaudio-dac", -+ .id = 0, -+ .num_resources = 0, -+}; -+ -+// Use the actual device name rather than generic driver name -+static struct i2c_board_info __initdata snd_pcm512x_i2c_devices[] = { -+ { -+ I2C_BOARD_INFO("pcm5122", 0x4c) -+ }, -+}; -+#endif -+ -+int __init bcm_register_device(struct platform_device *pdev) -+{ -+ int ret; -+ -+ ret = platform_device_register(pdev); -+ if (ret) -+ pr_debug("Unable to register platform device '%s': %d\n", -+ pdev->name, ret); -+ -+ return ret; -+} -+ -+/* -+ * Use these macros for platform and i2c devices that are present in the -+ * Device Tree. This way the devices are only added on non-DT systems. -+ */ -+#define bcm_register_device_dt(pdev) \ -+ if (!use_dt) bcm_register_device(pdev) -+ -+#define i2c_register_board_info_dt(busnum, info, n) \ -+ if (!use_dt) i2c_register_board_info(busnum, info, n) -+ -+int calc_rsts(int partition) -+{ -+ return PM_PASSWORD | -+ ((partition & (1 << 0)) << 0) | -+ ((partition & (1 << 1)) << 1) | -+ ((partition & (1 << 2)) << 2) | -+ ((partition & (1 << 3)) << 3) | -+ ((partition & (1 << 4)) << 4) | -+ ((partition & (1 << 5)) << 5); -+} -+ -+static void bcm2708_restart(enum reboot_mode mode, const char *cmd) -+{ -+ extern char bcm2708_reboot_mode; -+ uint32_t pm_rstc, pm_wdog; -+ uint32_t timeout = 10; -+ uint32_t pm_rsts = 0; -+ -+ if(bcm2708_reboot_mode == 'q') -+ { -+ // NOOBS < 1.3 booting with reboot=q -+ pm_rsts = readl(__io_address(PM_RSTS)); -+ pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET; -+ } -+ else if(bcm2708_reboot_mode == 'p') -+ { -+ // NOOBS < 1.3 halting -+ pm_rsts = readl(__io_address(PM_RSTS)); -+ pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRH_SET; -+ } -+ else -+ { -+ pm_rsts = calc_rsts(reboot_part); -+ } -+ -+ writel(pm_rsts, __io_address(PM_RSTS)); -+ -+ /* Setup watchdog for reset */ -+ pm_rstc = readl(__io_address(PM_RSTC)); -+ -+ pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0) -+ pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET; -+ -+ writel(pm_wdog, __io_address(PM_WDOG)); -+ writel(pm_rstc, __io_address(PM_RSTC)); -+} -+ -+/* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */ -+static void bcm2708_power_off(void) -+{ -+ extern char bcm2708_reboot_mode; -+ if(bcm2708_reboot_mode == 'q') -+ { -+ // NOOBS < v1.3 -+ bcm2708_restart('p', ""); -+ } -+ else -+ { -+ /* partition 63 is special code for HALT the bootloader knows not to boot*/ -+ reboot_part = 63; -+ /* continue with normal reset mechanism */ -+ bcm2708_restart(0, ""); -+ } -+} -+ -+static void __init bcm2708_init_uart1(void) -+{ -+ struct device_node *np; -+ -+ np = of_find_compatible_node(NULL, NULL, "brcm,bcm2835-aux-uart"); -+ if (of_device_is_available(np)) { -+ pr_info("bcm2708: Mini UART enabled\n"); -+ writel(1, __io_address(UART1_BASE + 0x4)); -+ } -+} -+ -+#ifdef CONFIG_OF -+static void __init bcm2708_dt_init(void) -+{ -+ int ret; -+ -+ of_clk_init(NULL); -+ ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); -+ if (ret) { -+ pr_err("of_platform_populate failed: %d\n", ret); -+ /* Proceed as if CONFIG_OF was not defined */ -+ } else { -+ use_dt = 1; -+ } -+} -+#else -+static void __init bcm2708_dt_init(void) { } -+#endif /* CONFIG_OF */ -+ -+void __init bcm2708_init(void) -+{ -+ int i; -+ -+#if defined(CONFIG_BCM_VC_CMA) -+ vc_cma_early_init(); -+#endif -+ printk("bcm2708.uart_clock = %d\n", uart_clock); -+ pm_power_off = bcm2708_power_off; -+ -+ bcm2708_init_clocks(); -+ bcm2708_dt_init(); -+ -+ bcm_register_device_dt(&bcm2708_dmaengine_device); -+ bcm_register_device_dt(&bcm2708_vcio_device); -+ bcm_register_device_dt(&bcm2708_rpifw_device); -+ bcm_register_device_dt(&bcm2708_vchiq_device); -+#ifdef CONFIG_BCM2708_GPIO -+ bcm_register_device_dt(&bcm2708_gpio_device); -+#endif -+ -+#if defined(CONFIG_PPS_CLIENT_GPIO) || defined(CONFIG_PPS_CLIENT_GPIO_MODULE) -+ if (!use_dt && (pps_gpio_pin >= 0)) { -+ pr_info("bcm2708: GPIO %d setup as pps-gpio device\n", pps_gpio_pin); -+ pps_gpio_info.gpio_pin = pps_gpio_pin; -+ pps_gpio_device.id = pps_gpio_pin; -+ bcm_register_device(&pps_gpio_device); -+ } -+#endif -+ -+#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE) -+ w1_gpio_pdata.pin = w1_gpio_pin; -+ w1_gpio_pdata.ext_pullup_enable_pin = w1_gpio_pullup; -+ bcm_register_device_dt(&w1_device); -+#endif -+ bcm_register_device_dt(&bcm2708_fb_device); -+ bcm_register_device_dt(&bcm2708_usb_device); -+ -+#ifdef CONFIG_MMC_BCM2835 -+ bcm_register_device_dt(&bcm2835_emmc_device); -+#endif -+ bcm2708_init_led(); -+ bcm2708_init_uart1(); -+ -+ /* Only create the platform devices for the ALSA driver in the -+ absence of an enabled "audio" DT node */ -+ if (!use_dt || -+ !of_device_is_available(of_find_node_by_path("/audio"))) { -+ for (i = 0; i < ARRAY_SIZE(bcm2708_alsa_devices); i++) -+ bcm_register_device(&bcm2708_alsa_devices[i]); -+ } -+ -+ bcm_register_device_dt(&bcm2708_spi_device); -+ -+ if (vc_i2c_override) { -+ bcm_register_device_dt(&bcm2708_bsc0_device); -+ bcm_register_device_dt(&bcm2708_bsc1_device); -+ } else if ((boardrev & 0xffffff) == 0x2 || (boardrev & 0xffffff) == 0x3) { -+ bcm_register_device_dt(&bcm2708_bsc0_device); -+ } else { -+ bcm_register_device_dt(&bcm2708_bsc1_device); -+ } -+ -+ bcm_register_device_dt(&bcm2835_thermal_device); -+ -+#if defined(CONFIG_SND_BCM2708_SOC_I2S) || defined(CONFIG_SND_BCM2708_SOC_I2S_MODULE) -+ bcm_register_device_dt(&bcm2708_i2s_device); -+#endif -+ -+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC_MODULE) -+ bcm_register_device_dt(&snd_hifiberry_dac_device); -+ bcm_register_device_dt(&snd_pcm5102a_codec_device); -+#endif -+ -+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS_MODULE) -+ bcm_register_device_dt(&snd_rpi_hifiberry_dacplus_device); -+ i2c_register_board_info_dt(1, snd_pcm512x_hbdacplus_i2c_devices, ARRAY_SIZE(snd_pcm512x_hbdacplus_i2c_devices)); -+#endif -+ -+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI_MODULE) -+ bcm_register_device_dt(&snd_hifiberry_digi_device); -+ i2c_register_board_info_dt(1, snd_wm8804_i2c_devices, ARRAY_SIZE(snd_wm8804_i2c_devices)); -+#endif -+ -+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP_MODULE) -+ bcm_register_device_dt(&snd_hifiberry_amp_device); -+ i2c_register_board_info_dt(1, snd_tas5713_i2c_devices, ARRAY_SIZE(snd_tas5713_i2c_devices)); -+#endif -+ -+#if defined(CONFIG_SND_BCM2708_SOC_RPI_DAC) || defined(CONFIG_SND_BCM2708_SOC_RPI_DAC_MODULE) -+ bcm_register_device_dt(&snd_rpi_dac_device); -+ bcm_register_device_dt(&snd_pcm1794a_codec_device); -+#endif -+ -+#if defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) || defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC_MODULE) -+ bcm_register_device_dt(&snd_rpi_iqaudio_dac_device); -+ i2c_register_board_info_dt(1, snd_pcm512x_i2c_devices, ARRAY_SIZE(snd_pcm512x_i2c_devices)); -+#endif -+ -+ if (!use_dt) { -+ for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { -+ struct amba_device *d = amba_devs[i]; -+ amba_device_register(d, &iomem_resource); -+ } -+ } -+ system_rev = boardrev; -+ system_serial_low = serial; -+ -+#ifdef CONFIG_BCM2708_SPIDEV -+ if (!use_dt) -+ spi_register_board_info(bcm2708_spi_devices, -+ ARRAY_SIZE(bcm2708_spi_devices)); -+#endif -+} -+ -+static void timer_set_mode(enum clock_event_mode mode, -+ struct clock_event_device *clk) -+{ -+ switch (mode) { -+ case CLOCK_EVT_MODE_ONESHOT: /* Leave the timer disabled, .set_next_event will enable it */ -+ case CLOCK_EVT_MODE_SHUTDOWN: -+ break; -+ case CLOCK_EVT_MODE_PERIODIC: -+ -+ case CLOCK_EVT_MODE_UNUSED: -+ case CLOCK_EVT_MODE_RESUME: -+ -+ default: -+ printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n", -+ (int)mode); -+ break; -+ } -+ -+} -+ -+static int timer_set_next_event(unsigned long cycles, -+ struct clock_event_device *unused) -+{ -+ unsigned long stc; -+ do { -+ stc = readl(__io_address(ST_BASE + 0x04)); -+ /* We could take a FIQ here, which may push ST above STC3 */ -+ writel(stc + cycles, __io_address(ST_BASE + 0x18)); -+ } while ((signed long) cycles >= 0 && -+ (signed long) (readl(__io_address(ST_BASE + 0x04)) - stc) -+ >= (signed long) cycles); -+ return 0; -+} -+ -+static struct clock_event_device timer0_clockevent = { -+ .name = "timer0", -+ .shift = 32, -+ .features = CLOCK_EVT_FEAT_ONESHOT, -+ .set_mode = timer_set_mode, -+ .set_next_event = timer_set_next_event, -+}; -+ -+/* -+ * IRQ handler for the timer -+ */ -+static irqreturn_t bcm2708_timer_interrupt(int irq, void *dev_id) -+{ -+ struct clock_event_device *evt = &timer0_clockevent; -+ -+ writel(1 << 3, __io_address(ST_BASE + 0x00)); /* stcs clear timer int */ -+ -+ evt->event_handler(evt); -+ -+ return IRQ_HANDLED; -+} -+ -+static struct irqaction bcm2708_timer_irq = { -+ .name = "BCM2708 Timer Tick", -+ .flags = IRQF_TIMER | IRQF_IRQPOLL, -+ .handler = bcm2708_timer_interrupt, -+}; -+ -+/* -+ * Set up timer interrupt, and return the current time in seconds. -+ */ -+ -+static struct delay_timer bcm2708_delay_timer = { -+ .read_current_timer = bcm2708_read_current_timer, -+ .freq = STC_FREQ_HZ, -+}; -+ -+static void __init bcm2708_timer_init(void) -+{ -+ /* init high res timer */ -+ bcm2708_clocksource_init(); -+ -+ /* -+ * Make irqs happen for the system timer -+ */ -+ setup_irq(IRQ_TIMER3, &bcm2708_timer_irq); -+ -+ sched_clock_register(bcm2708_read_sched_clock, 32, STC_FREQ_HZ); -+ -+ timer0_clockevent.mult = -+ div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift); -+ timer0_clockevent.max_delta_ns = -+ clockevent_delta2ns(0xffffffff, &timer0_clockevent); -+ timer0_clockevent.min_delta_ns = -+ clockevent_delta2ns(0xf, &timer0_clockevent); -+ -+ timer0_clockevent.cpumask = cpumask_of(0); -+ clockevents_register_device(&timer0_clockevent); -+ -+ register_current_timer_delay(&bcm2708_delay_timer); -+} -+ -+#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) -+#include -+ -+static struct gpio_led bcm2708_leds[] = { -+ [0] = { -+ .gpio = 16, -+ .name = "led0", -+ .default_trigger = "mmc0", -+ .active_low = 1, -+ }, -+}; -+ -+static struct gpio_led_platform_data bcm2708_led_pdata = { -+ .num_leds = ARRAY_SIZE(bcm2708_leds), -+ .leds = bcm2708_leds, -+}; -+ -+static struct platform_device bcm2708_led_device = { -+ .name = "leds-gpio", -+ .id = -1, -+ .dev = { -+ .platform_data = &bcm2708_led_pdata, -+ }, -+}; -+ -+static void __init bcm2708_init_led(void) -+{ -+ bcm2708_leds[0].gpio = disk_led_gpio; -+ bcm2708_leds[0].active_low = disk_led_active_low; -+ bcm_register_device_dt(&bcm2708_led_device); -+} -+#else -+static inline void bcm2708_init_led(void) -+{ -+} -+#endif -+ -+void __init bcm2708_init_early(void) -+{ -+ /* -+ * Some devices allocate their coherent buffers from atomic -+ * context. Increase size of atomic coherent pool to make sure such -+ * the allocations won't fail. -+ */ -+ init_dma_coherent_pool_size(SZ_4M); -+} -+ -+static void __init board_reserve(void) -+{ -+#if defined(CONFIG_BCM_VC_CMA) -+ vc_cma_reserve(); -+#endif -+} -+ -+static const char * const bcm2708_compat[] = { -+ "brcm,bcm2708", -+ NULL -+}; -+ -+MACHINE_START(BCM2708, "BCM2708") -+ /* Maintainer: Broadcom Europe Ltd. */ -+ .map_io = bcm2708_map_io, -+ .init_irq = bcm2708_init_irq, -+ .init_time = bcm2708_timer_init, -+ .init_machine = bcm2708_init, -+ .init_early = bcm2708_init_early, -+ .reserve = board_reserve, -+ .restart = bcm2708_restart, -+ .dt_compat = bcm2708_compat, -+MACHINE_END -+ -+module_param(boardrev, uint, 0644); -+module_param(serial, uint, 0644); -+module_param(uart_clock, uint, 0644); -+module_param(disk_led_gpio, uint, 0644); -+module_param(disk_led_active_low, uint, 0644); -+module_param(reboot_part, uint, 0644); -+module_param(w1_gpio_pin, uint, 0644); -+module_param(w1_gpio_pullup, uint, 0644); -+module_param(vc_i2c_override, bool, 0644); -+MODULE_PARM_DESC(vc_i2c_override, "Allow the use of VC's I2C peripheral."); -+module_param(pps_gpio_pin, int, 0644); -+MODULE_PARM_DESC(pps_gpio_pin, "Set GPIO pin to reserve for PPS"); -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/bcm2708_gpio.c linux-rpi/arch/arm/mach-bcm2708/bcm2708_gpio.c ---- linux-4.1.13.orig/arch/arm/mach-bcm2708/bcm2708_gpio.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2708/bcm2708_gpio.c 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,426 @@ -+/* -+ * linux/arch/arm/mach-bcm2708/bcm2708_gpio.c -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio" -+#define DRIVER_NAME BCM_GPIO_DRIVER_NAME -+#define BCM_GPIO_USE_IRQ 1 -+ -+#define GPIOFSEL(x) (0x00+(x)*4) -+#define GPIOSET(x) (0x1c+(x)*4) -+#define GPIOCLR(x) (0x28+(x)*4) -+#define GPIOLEV(x) (0x34+(x)*4) -+#define GPIOEDS(x) (0x40+(x)*4) -+#define GPIOREN(x) (0x4c+(x)*4) -+#define GPIOFEN(x) (0x58+(x)*4) -+#define GPIOHEN(x) (0x64+(x)*4) -+#define GPIOLEN(x) (0x70+(x)*4) -+#define GPIOAREN(x) (0x7c+(x)*4) -+#define GPIOAFEN(x) (0x88+(x)*4) -+#define GPIOUD(x) (0x94+(x)*4) -+#define GPIOUDCLK(x) (0x98+(x)*4) -+ -+#define GPIO_BANKS 2 -+ -+enum { GPIO_FSEL_INPUT, GPIO_FSEL_OUTPUT, -+ GPIO_FSEL_ALT5, GPIO_FSEL_ALT_4, -+ GPIO_FSEL_ALT0, GPIO_FSEL_ALT1, -+ GPIO_FSEL_ALT2, GPIO_FSEL_ALT3, -+}; -+ -+ /* Each of the two spinlocks protects a different set of hardware -+ * regiters and data structurs. This decouples the code of the IRQ from -+ * the GPIO code. This also makes the case of a GPIO routine call from -+ * the IRQ code simpler. -+ */ -+static DEFINE_SPINLOCK(lock); /* GPIO registers */ -+ -+struct bcm2708_gpio { -+ struct list_head list; -+ void __iomem *base; -+ struct gpio_chip gc; -+ unsigned long rising[(BCM2708_NR_GPIOS + 31) / 32]; -+ unsigned long falling[(BCM2708_NR_GPIOS + 31) / 32]; -+ unsigned long high[(BCM2708_NR_GPIOS + 31) / 32]; -+ unsigned long low[(BCM2708_NR_GPIOS + 31) / 32]; -+}; -+ -+static int bcm2708_set_function(struct gpio_chip *gc, unsigned offset, -+ int function) -+{ -+ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); -+ unsigned long flags; -+ unsigned gpiodir; -+ unsigned gpio_bank = offset / 10; -+ unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3; -+ -+//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set_function %p (%d,%d)\n", gc, offset, function); -+ if (offset >= BCM2708_NR_GPIOS) -+ return -EINVAL; -+ -+ spin_lock_irqsave(&lock, flags); -+ -+ gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank)); -+ gpiodir &= ~(7 << gpio_field_offset); -+ gpiodir |= function << gpio_field_offset; -+ writel(gpiodir, gpio->base + GPIOFSEL(gpio_bank)); -+ spin_unlock_irqrestore(&lock, flags); -+ gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank)); -+ -+ return 0; -+} -+ -+static int bcm2708_gpio_dir_in(struct gpio_chip *gc, unsigned offset) -+{ -+ return bcm2708_set_function(gc, offset, GPIO_FSEL_INPUT); -+} -+ -+static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value); -+static int bcm2708_gpio_dir_out(struct gpio_chip *gc, unsigned offset, -+ int value) -+{ -+ int ret; -+ ret = bcm2708_set_function(gc, offset, GPIO_FSEL_OUTPUT); -+ if (ret >= 0) -+ bcm2708_gpio_set(gc, offset, value); -+ return ret; -+} -+ -+static int bcm2708_gpio_get(struct gpio_chip *gc, unsigned offset) -+{ -+ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); -+ unsigned gpio_bank = offset / 32; -+ unsigned gpio_field_offset = (offset - 32 * gpio_bank); -+ unsigned lev; -+ -+ if (offset >= BCM2708_NR_GPIOS) -+ return 0; -+ lev = readl(gpio->base + GPIOLEV(gpio_bank)); -+//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_get %p (%d)=%d\n", gc, offset, 0x1 & (lev>>gpio_field_offset)); -+ return 0x1 & (lev >> gpio_field_offset); -+} -+ -+static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value) -+{ -+ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); -+ unsigned gpio_bank = offset / 32; -+ unsigned gpio_field_offset = (offset - 32 * gpio_bank); -+//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set %p (%d=%d)\n", gc, offset, value); -+ if (offset >= BCM2708_NR_GPIOS) -+ return; -+ if (value) -+ writel(1 << gpio_field_offset, gpio->base + GPIOSET(gpio_bank)); -+ else -+ writel(1 << gpio_field_offset, gpio->base + GPIOCLR(gpio_bank)); -+} -+ -+/********************** -+ * extension to configure pullups -+ */ -+int bcm2708_gpio_setpull(struct gpio_chip *gc, unsigned offset, -+ bcm2708_gpio_pull_t value) -+{ -+ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); -+ unsigned gpio_bank = offset / 32; -+ unsigned gpio_field_offset = (offset - 32 * gpio_bank); -+ -+ if (offset >= BCM2708_NR_GPIOS) -+ return -EINVAL; -+ -+ switch (value) { -+ case BCM2708_PULL_UP: -+ writel(2, gpio->base + GPIOUD(0)); -+ break; -+ case BCM2708_PULL_DOWN: -+ writel(1, gpio->base + GPIOUD(0)); -+ break; -+ case BCM2708_PULL_OFF: -+ writel(0, gpio->base + GPIOUD(0)); -+ break; -+ } -+ -+ udelay(5); -+ writel(1 << gpio_field_offset, gpio->base + GPIOUDCLK(gpio_bank)); -+ udelay(5); -+ writel(0, gpio->base + GPIOUD(0)); -+ writel(0 << gpio_field_offset, gpio->base + GPIOUDCLK(gpio_bank)); -+ -+ return 0; -+} -+EXPORT_SYMBOL(bcm2708_gpio_setpull); -+ -+/************************************************************************************************************************* -+ * bcm2708 GPIO IRQ -+ */ -+ -+#if BCM_GPIO_USE_IRQ -+ -+static int bcm2708_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) -+{ -+ return gpio_to_irq(gpio); -+} -+ -+static int bcm2708_gpio_irq_set_type(struct irq_data *d, unsigned type) -+{ -+ unsigned irq = d->irq; -+ struct bcm2708_gpio *gpio = irq_get_chip_data(irq); -+ unsigned gn = irq_to_gpio(irq); -+ unsigned gb = gn / 32; -+ unsigned go = gn % 32; -+ -+ gpio->rising[gb] &= ~(1 << go); -+ gpio->falling[gb] &= ~(1 << go); -+ gpio->high[gb] &= ~(1 << go); -+ gpio->low[gb] &= ~(1 << go); -+ -+ if (type & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) -+ return -EINVAL; -+ -+ if (type & IRQ_TYPE_EDGE_RISING) -+ gpio->rising[gb] |= (1 << go); -+ if (type & IRQ_TYPE_EDGE_FALLING) -+ gpio->falling[gb] |= (1 << go); -+ if (type & IRQ_TYPE_LEVEL_HIGH) -+ gpio->high[gb] |= (1 << go); -+ if (type & IRQ_TYPE_LEVEL_LOW) -+ gpio->low[gb] |= (1 << go); -+ return 0; -+} -+ -+static void bcm2708_gpio_irq_mask(struct irq_data *d) -+{ -+ unsigned irq = d->irq; -+ struct bcm2708_gpio *gpio = irq_get_chip_data(irq); -+ unsigned gn = irq_to_gpio(irq); -+ unsigned gb = gn / 32; -+ unsigned long rising = readl(gpio->base + GPIOREN(gb)); -+ unsigned long falling = readl(gpio->base + GPIOFEN(gb)); -+ unsigned long high = readl(gpio->base + GPIOHEN(gb)); -+ unsigned long low = readl(gpio->base + GPIOLEN(gb)); -+ -+ gn = gn % 32; -+ -+ writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb)); -+ writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb)); -+ writel(high & ~(1 << gn), gpio->base + GPIOHEN(gb)); -+ writel(low & ~(1 << gn), gpio->base + GPIOLEN(gb)); -+} -+ -+static void bcm2708_gpio_irq_unmask(struct irq_data *d) -+{ -+ unsigned irq = d->irq; -+ struct bcm2708_gpio *gpio = irq_get_chip_data(irq); -+ unsigned gn = irq_to_gpio(irq); -+ unsigned gb = gn / 32; -+ unsigned go = gn % 32; -+ unsigned long rising = readl(gpio->base + GPIOREN(gb)); -+ unsigned long falling = readl(gpio->base + GPIOFEN(gb)); -+ unsigned long high = readl(gpio->base + GPIOHEN(gb)); -+ unsigned long low = readl(gpio->base + GPIOLEN(gb)); -+ -+ if (gpio->rising[gb] & (1 << go)) { -+ writel(rising | (1 << go), gpio->base + GPIOREN(gb)); -+ } else { -+ writel(rising & ~(1 << go), gpio->base + GPIOREN(gb)); -+ } -+ -+ if (gpio->falling[gb] & (1 << go)) { -+ writel(falling | (1 << go), gpio->base + GPIOFEN(gb)); -+ } else { -+ writel(falling & ~(1 << go), gpio->base + GPIOFEN(gb)); -+ } -+ -+ if (gpio->high[gb] & (1 << go)) { -+ writel(high | (1 << go), gpio->base + GPIOHEN(gb)); -+ } else { -+ writel(high & ~(1 << go), gpio->base + GPIOHEN(gb)); -+ } -+ -+ if (gpio->low[gb] & (1 << go)) { -+ writel(low | (1 << go), gpio->base + GPIOLEN(gb)); -+ } else { -+ writel(low & ~(1 << go), gpio->base + GPIOLEN(gb)); -+ } -+} -+ -+static struct irq_chip bcm2708_irqchip = { -+ .name = "GPIO", -+ .irq_enable = bcm2708_gpio_irq_unmask, -+ .irq_disable = bcm2708_gpio_irq_mask, -+ .irq_unmask = bcm2708_gpio_irq_unmask, -+ .irq_mask = bcm2708_gpio_irq_mask, -+ .irq_set_type = bcm2708_gpio_irq_set_type, -+}; -+ -+static irqreturn_t bcm2708_gpio_interrupt(int irq, void *dev_id) -+{ -+ unsigned long edsr; -+ unsigned bank; -+ int i; -+ unsigned gpio; -+ unsigned level_bits; -+ struct bcm2708_gpio *gpio_data = dev_id; -+ -+ for (bank = 0; bank < GPIO_BANKS; bank++) { -+ edsr = readl(__io_address(GPIO_BASE) + GPIOEDS(bank)); -+ level_bits = gpio_data->high[bank] | gpio_data->low[bank]; -+ -+ for_each_set_bit(i, &edsr, 32) { -+ gpio = i + bank * 32; -+ /* ack edge triggered IRQs immediately */ -+ if (!(level_bits & (1<gc.to_irq = bcm2708_gpio_to_irq; -+ -+ for (irq = GPIO_IRQ_START; irq < (GPIO_IRQ_START + GPIO_IRQS); irq++) { -+ irq_set_chip_data(irq, ucb); -+ irq_set_chip_and_handler(irq, &bcm2708_irqchip, -+ handle_simple_irq); -+ set_irq_flags(irq, IRQF_VALID); -+ } -+ -+ bcm2708_gpio_irq.dev_id = ucb; -+ setup_irq(IRQ_GPIO3, &bcm2708_gpio_irq); -+} -+ -+#else -+ -+static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb) -+{ -+} -+ -+#endif /* #if BCM_GPIO_USE_IRQ ***************************************************************************************************************** */ -+ -+static int bcm2708_gpio_probe(struct platform_device *dev) -+{ -+ struct bcm2708_gpio *ucb; -+ struct resource *res; -+ int bank; -+ int err = 0; -+ -+ printk(KERN_INFO DRIVER_NAME ": bcm2708_gpio_probe %p\n", dev); -+ -+ ucb = kzalloc(sizeof(*ucb), GFP_KERNEL); -+ if (NULL == ucb) { -+ printk(KERN_ERR DRIVER_NAME ": failed to allocate " -+ "mailbox memory\n"); -+ err = -ENOMEM; -+ goto err; -+ } -+ -+ res = platform_get_resource(dev, IORESOURCE_MEM, 0); -+ -+ platform_set_drvdata(dev, ucb); -+ ucb->base = __io_address(GPIO_BASE); -+ -+ ucb->gc.label = "bcm2708_gpio"; -+ ucb->gc.base = 0; -+ ucb->gc.ngpio = BCM2708_NR_GPIOS; -+ ucb->gc.owner = THIS_MODULE; -+ -+ ucb->gc.direction_input = bcm2708_gpio_dir_in; -+ ucb->gc.direction_output = bcm2708_gpio_dir_out; -+ ucb->gc.get = bcm2708_gpio_get; -+ ucb->gc.set = bcm2708_gpio_set; -+ ucb->gc.can_sleep = 0; -+ -+ for (bank = 0; bank < GPIO_BANKS; bank++) { -+ writel(0, ucb->base + GPIOREN(bank)); -+ writel(0, ucb->base + GPIOFEN(bank)); -+ writel(0, ucb->base + GPIOHEN(bank)); -+ writel(0, ucb->base + GPIOLEN(bank)); -+ writel(0, ucb->base + GPIOAREN(bank)); -+ writel(0, ucb->base + GPIOAFEN(bank)); -+ writel(~0, ucb->base + GPIOEDS(bank)); -+ } -+ -+ bcm2708_gpio_irq_init(ucb); -+ -+ err = gpiochip_add(&ucb->gc); -+ -+err: -+ return err; -+ -+} -+ -+static int bcm2708_gpio_remove(struct platform_device *dev) -+{ -+ int err = 0; -+ struct bcm2708_gpio *ucb = platform_get_drvdata(dev); -+ -+ printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_remove %p\n", dev); -+ -+ gpiochip_remove(&ucb->gc); -+ -+ platform_set_drvdata(dev, NULL); -+ kfree(ucb); -+ -+ return err; -+} -+ -+static struct platform_driver bcm2708_gpio_driver = { -+ .probe = bcm2708_gpio_probe, -+ .remove = bcm2708_gpio_remove, -+ .driver = { -+ .name = "bcm2708_gpio"}, -+}; -+ -+static int __init bcm2708_gpio_init(void) -+{ -+ return platform_driver_register(&bcm2708_gpio_driver); -+} -+ -+static void __exit bcm2708_gpio_exit(void) -+{ -+ platform_driver_unregister(&bcm2708_gpio_driver); -+} -+ -+module_init(bcm2708_gpio_init); -+module_exit(bcm2708_gpio_exit); -+ -+MODULE_DESCRIPTION("Broadcom BCM2708 GPIO driver"); -+MODULE_LICENSE("GPL"); -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/bcm2708.h linux-rpi/arch/arm/mach-bcm2708/bcm2708.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2708/bcm2708.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2708/bcm2708.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,49 @@ -+/* -+ * linux/arch/arm/mach-bcm2708/bcm2708.h -+ * -+ * BCM2708 machine support header -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef __BCM2708_BCM2708_H -+#define __BCM2708_BCM2708_H -+ -+#include -+ -+extern void __init bcm2708_init(void); -+extern void __init bcm2708_init_irq(void); -+extern void __init bcm2708_map_io(void); -+extern struct sys_timer bcm2708_timer; -+extern unsigned int mmc_status(struct device *dev); -+ -+#define AMBA_DEVICE(name, busid, base, plat) \ -+static struct amba_device name##_device = { \ -+ .dev = { \ -+ .coherent_dma_mask = ~0, \ -+ .init_name = busid, \ -+ .platform_data = plat, \ -+ }, \ -+ .res = { \ -+ .start = base##_BASE, \ -+ .end = (base##_BASE) + SZ_4K - 1,\ -+ .flags = IORESOURCE_MEM, \ -+ }, \ -+ .irq = base##_IRQ, \ -+} -+ -+#endif -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/arm_control.h linux-rpi/arch/arm/mach-bcm2708/include/mach/arm_control.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/arm_control.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/arm_control.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,419 @@ -+/* -+ * linux/arch/arm/mach-bcm2708/arm_control.h -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef __BCM2708_ARM_CONTROL_H -+#define __BCM2708_ARM_CONTROL_H -+ -+/* -+ * Definitions and addresses for the ARM CONTROL logic -+ * This file is manually generated. -+ */ -+ -+#define ARM_BASE 0x7E00B000 -+ -+/* Basic configuration */ -+#define ARM_CONTROL0 HW_REGISTER_RW(ARM_BASE+0x000) -+#define ARM_C0_SIZ128M 0x00000000 -+#define ARM_C0_SIZ256M 0x00000001 -+#define ARM_C0_SIZ512M 0x00000002 -+#define ARM_C0_SIZ1G 0x00000003 -+#define ARM_C0_BRESP0 0x00000000 -+#define ARM_C0_BRESP1 0x00000004 -+#define ARM_C0_BRESP2 0x00000008 -+#define ARM_C0_BOOTHI 0x00000010 -+#define ARM_C0_UNUSED05 0x00000020 /* free */ -+#define ARM_C0_FULLPERI 0x00000040 -+#define ARM_C0_UNUSED78 0x00000180 /* free */ -+#define ARM_C0_JTAGMASK 0x00000E00 -+#define ARM_C0_JTAGOFF 0x00000000 -+#define ARM_C0_JTAGBASH 0x00000800 /* Debug on GPIO off */ -+#define ARM_C0_JTAGGPIO 0x00000C00 /* Debug on GPIO on */ -+#define ARM_C0_APROTMSK 0x0000F000 -+#define ARM_C0_DBG0SYNC 0x00010000 /* VPU0 halt sync */ -+#define ARM_C0_DBG1SYNC 0x00020000 /* VPU1 halt sync */ -+#define ARM_C0_SWDBGREQ 0x00040000 /* HW debug request */ -+#define ARM_C0_PASSHALT 0x00080000 /* ARM halt passed to debugger */ -+#define ARM_C0_PRIO_PER 0x00F00000 /* per priority mask */ -+#define ARM_C0_PRIO_L2 0x0F000000 -+#define ARM_C0_PRIO_UC 0xF0000000 -+ -+#define ARM_C0_APROTPASS 0x0000A000 /* Translate 1:1 */ -+#define ARM_C0_APROTUSER 0x00000000 /* Only user mode */ -+#define ARM_C0_APROTSYST 0x0000F000 /* Only system mode */ -+ -+ -+#define ARM_CONTROL1 HW_REGISTER_RW(ARM_BASE+0x440) -+#define ARM_C1_TIMER 0x00000001 /* re-route timer IRQ to VC */ -+#define ARM_C1_MAIL 0x00000002 /* re-route Mail IRQ to VC */ -+#define ARM_C1_BELL0 0x00000004 /* re-route Doorbell 0 to VC */ -+#define ARM_C1_BELL1 0x00000008 /* re-route Doorbell 1 to VC */ -+#define ARM_C1_PERSON 0x00000100 /* peripherals on */ -+#define ARM_C1_REQSTOP 0x00000200 /* ASYNC bridge request stop */ -+ -+#define ARM_STATUS HW_REGISTER_RW(ARM_BASE+0x444) -+#define ARM_S_ACKSTOP 0x80000000 /* Bridge stopped */ -+#define ARM_S_READPEND 0x000003FF /* pending reads counter */ -+#define ARM_S_WRITPEND 0x000FFC00 /* pending writes counter */ -+ -+#define ARM_ERRHALT HW_REGISTER_RW(ARM_BASE+0x448) -+#define ARM_EH_PERIBURST 0x00000001 /* Burst write seen on peri bus */ -+#define ARM_EH_ILLADDRS1 0x00000002 /* Address bits 25-27 error */ -+#define ARM_EH_ILLADDRS2 0x00000004 /* Address bits 31-28 error */ -+#define ARM_EH_VPU0HALT 0x00000008 /* VPU0 halted & in debug mode */ -+#define ARM_EH_VPU1HALT 0x00000010 /* VPU1 halted & in debug mode */ -+#define ARM_EH_ARMHALT 0x00000020 /* ARM in halted debug mode */ -+ -+#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C) -+#define ARM_ID HW_REGISTER_RW(ARM_BASE+0x44C) -+#define ARM_IDVAL 0x364D5241 -+ -+/* Translation memory */ -+#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100) -+/* 32 locations: 0x100.. 0x17F */ -+/* 32 spare means we CAN go to 64 pages.... */ -+ -+ -+/* Interrupts */ -+#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200) /* Top IRQ bits */ -+#define ARM_I0_TIMER 0x00000001 /* timer IRQ */ -+#define ARM_I0_MAIL 0x00000002 /* Mail IRQ */ -+#define ARM_I0_BELL0 0x00000004 /* Doorbell 0 */ -+#define ARM_I0_BELL1 0x00000008 /* Doorbell 1 */ -+#define ARM_I0_BANK1 0x00000100 /* Bank1 IRQ */ -+#define ARM_I0_BANK2 0x00000200 /* Bank2 IRQ */ -+ -+#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) /* All bank1 IRQ bits */ -+/* todo: all I1_interrupt sources */ -+#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) /* All bank2 IRQ bits */ -+/* todo: all I2_interrupt sources */ -+ -+#define ARM_IRQ_FAST HW_REGISTER_RW(ARM_BASE+0x20C) /* FIQ control */ -+#define ARM_IF_INDEX 0x0000007F /* FIQ select */ -+#define ARM_IF_ENABLE 0x00000080 /* FIQ enable */ -+#define ARM_IF_VCMASK 0x0000003F /* FIQ = (index from VC source) */ -+#define ARM_IF_TIMER 0x00000040 /* FIQ = ARM timer */ -+#define ARM_IF_MAIL 0x00000041 /* FIQ = ARM Mail */ -+#define ARM_IF_BELL0 0x00000042 /* FIQ = ARM Doorbell 0 */ -+#define ARM_IF_BELL1 0x00000043 /* FIQ = ARM Doorbell 1 */ -+#define ARM_IF_VP0HALT 0x00000044 /* FIQ = VPU0 Halt seen */ -+#define ARM_IF_VP1HALT 0x00000045 /* FIQ = VPU1 Halt seen */ -+#define ARM_IF_ILLEGAL 0x00000046 /* FIQ = Illegal access seen */ -+ -+#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) /* Bank1 enable bits */ -+#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) /* Bank2 enable bits */ -+#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) /* ARM irqs enable bits */ -+#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) /* Bank1 disable bits */ -+#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) /* Bank2 disable bits */ -+#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) /* ARM irqs disable bits */ -+#define ARM_IE_TIMER 0x00000001 /* Timer IRQ */ -+#define ARM_IE_MAIL 0x00000002 /* Mail IRQ */ -+#define ARM_IE_BELL0 0x00000004 /* Doorbell 0 */ -+#define ARM_IE_BELL1 0x00000008 /* Doorbell 1 */ -+#define ARM_IE_VP0HALT 0x00000010 /* VPU0 Halt */ -+#define ARM_IE_VP1HALT 0x00000020 /* VPU1 Halt */ -+#define ARM_IE_ILLEGAL 0x00000040 /* Illegal access seen */ -+ -+/* Timer */ -+/* For reg. fields see sp804 spec. */ -+#define ARM_T_LOAD HW_REGISTER_RW(ARM_BASE+0x400) -+#define ARM_T_VALUE HW_REGISTER_RW(ARM_BASE+0x404) -+#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408) -+#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C) -+#define ARM_T_RAWIRQ HW_REGISTER_RW(ARM_BASE+0x410) -+#define ARM_T_MSKIRQ HW_REGISTER_RW(ARM_BASE+0x414) -+#define ARM_T_RELOAD HW_REGISTER_RW(ARM_BASE+0x418) -+#define ARM_T_PREDIV HW_REGISTER_RW(ARM_BASE+0x41c) -+#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420) -+ -+#define TIMER_CTRL_ONESHOT (1 << 0) -+#define TIMER_CTRL_32BIT (1 << 1) -+#define TIMER_CTRL_DIV1 (0 << 2) -+#define TIMER_CTRL_DIV16 (1 << 2) -+#define TIMER_CTRL_DIV256 (2 << 2) -+#define TIMER_CTRL_IE (1 << 5) -+#define TIMER_CTRL_PERIODIC (1 << 6) -+#define TIMER_CTRL_ENABLE (1 << 7) -+#define TIMER_CTRL_DBGHALT (1 << 8) -+#define TIMER_CTRL_ENAFREE (1 << 9) -+#define TIMER_CTRL_FREEDIV_SHIFT 16) -+#define TIMER_CTRL_FREEDIV_MASK 0xff -+ -+/* Semaphores, Doorbells, Mailboxes */ -+#define ARM_SBM_OWN0 (ARM_BASE+0x800) -+#define ARM_SBM_OWN1 (ARM_BASE+0x900) -+#define ARM_SBM_OWN2 (ARM_BASE+0xA00) -+#define ARM_SBM_OWN3 (ARM_BASE+0xB00) -+ -+/* MAILBOXES -+ * Register flags are common across all -+ * owner registers. See end of this section -+ * -+ * Semaphores, Doorbells, Mailboxes Owner 0 -+ * -+ */ -+ -+#define ARM_0_SEMS HW_REGISTER_RW(ARM_SBM_OWN0+0x00) -+#define ARM_0_SEM0 HW_REGISTER_RW(ARM_SBM_OWN0+0x00) -+#define ARM_0_SEM1 HW_REGISTER_RW(ARM_SBM_OWN0+0x04) -+#define ARM_0_SEM2 HW_REGISTER_RW(ARM_SBM_OWN0+0x08) -+#define ARM_0_SEM3 HW_REGISTER_RW(ARM_SBM_OWN0+0x0C) -+#define ARM_0_SEM4 HW_REGISTER_RW(ARM_SBM_OWN0+0x10) -+#define ARM_0_SEM5 HW_REGISTER_RW(ARM_SBM_OWN0+0x14) -+#define ARM_0_SEM6 HW_REGISTER_RW(ARM_SBM_OWN0+0x18) -+#define ARM_0_SEM7 HW_REGISTER_RW(ARM_SBM_OWN0+0x1C) -+#define ARM_0_BELL0 HW_REGISTER_RW(ARM_SBM_OWN0+0x40) -+#define ARM_0_BELL1 HW_REGISTER_RW(ARM_SBM_OWN0+0x44) -+#define ARM_0_BELL2 HW_REGISTER_RW(ARM_SBM_OWN0+0x48) -+#define ARM_0_BELL3 HW_REGISTER_RW(ARM_SBM_OWN0+0x4C) -+/* MAILBOX 0 access in Owner 0 area */ -+/* Some addresses should ONLY be used by owner 0 */ -+#define ARM_0_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) */ -+#define ARM_0_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) Normal read */ -+#define ARM_0_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN0+0x90) /* none-pop read */ -+#define ARM_0_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN0+0x94) /* Sender read (only LS 2 bits) */ -+#define ARM_0_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN0+0x98) /* Status read */ -+#define ARM_0_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0x9C) /* Config read/write */ -+/* MAILBOX 1 access in Owner 0 area */ -+/* Owner 0 should only WRITE to this mailbox */ -+#define ARM_0_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) /* .. 0xAC (4 locations) */ -+/*#define ARM_0_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_0_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_0_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_0_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN0+0xB8) /* Status read */ -+/*#define ARM_0_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) */ /* DO NOT USE THIS !!!!! */ -+/* General SEM, BELL, MAIL config/status */ -+#define ARM_0_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE0) /* semaphore clear/debug register */ -+#define ARM_0_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE4) /* Doorbells clear/debug register */ -+#define ARM_0_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xF8) /* ALL interrupts */ -+#define ARM_0_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xFC) /* IRQS pending for owner 0 */ -+ -+/* Semaphores, Doorbells, Mailboxes Owner 1 */ -+#define ARM_1_SEMS HW_REGISTER_RW(ARM_SBM_OWN1+0x00) -+#define ARM_1_SEM0 HW_REGISTER_RW(ARM_SBM_OWN1+0x00) -+#define ARM_1_SEM1 HW_REGISTER_RW(ARM_SBM_OWN1+0x04) -+#define ARM_1_SEM2 HW_REGISTER_RW(ARM_SBM_OWN1+0x08) -+#define ARM_1_SEM3 HW_REGISTER_RW(ARM_SBM_OWN1+0x0C) -+#define ARM_1_SEM4 HW_REGISTER_RW(ARM_SBM_OWN1+0x10) -+#define ARM_1_SEM5 HW_REGISTER_RW(ARM_SBM_OWN1+0x14) -+#define ARM_1_SEM6 HW_REGISTER_RW(ARM_SBM_OWN1+0x18) -+#define ARM_1_SEM7 HW_REGISTER_RW(ARM_SBM_OWN1+0x1C) -+#define ARM_1_BELL0 HW_REGISTER_RW(ARM_SBM_OWN1+0x40) -+#define ARM_1_BELL1 HW_REGISTER_RW(ARM_SBM_OWN1+0x44) -+#define ARM_1_BELL2 HW_REGISTER_RW(ARM_SBM_OWN1+0x48) -+#define ARM_1_BELL3 HW_REGISTER_RW(ARM_SBM_OWN1+0x4C) -+/* MAILBOX 0 access in Owner 0 area */ -+/* Owner 1 should only WRITE to this mailbox */ -+#define ARM_1_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0x80) /* .. 0x8C (4 locations) */ -+/*#define ARM_1_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN1+0x80) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_1_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN1+0x98) /* Status read */ -+/*#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) */ /* DO NOT USE THIS !!!!! */ -+/* MAILBOX 1 access in Owner 0 area */ -+#define ARM_1_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) */ -+#define ARM_1_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) Normal read */ -+#define ARM_1_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN1+0xB0) /* none-pop read */ -+#define ARM_1_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN1+0xB4) /* Sender read (only LS 2 bits) */ -+#define ARM_1_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN1+0xB8) /* Status read */ -+#define ARM_1_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0xBC) -+/* General SEM, BELL, MAIL config/status */ -+#define ARM_1_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE0) /* semaphore clear/debug register */ -+#define ARM_1_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE4) /* Doorbells clear/debug register */ -+#define ARM_1_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xFC) /* IRQS pending for owner 1 */ -+#define ARM_1_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xF8) /* ALL interrupts */ -+ -+/* Semaphores, Doorbells, Mailboxes Owner 2 */ -+#define ARM_2_SEMS HW_REGISTER_RW(ARM_SBM_OWN2+0x00) -+#define ARM_2_SEM0 HW_REGISTER_RW(ARM_SBM_OWN2+0x00) -+#define ARM_2_SEM1 HW_REGISTER_RW(ARM_SBM_OWN2+0x04) -+#define ARM_2_SEM2 HW_REGISTER_RW(ARM_SBM_OWN2+0x08) -+#define ARM_2_SEM3 HW_REGISTER_RW(ARM_SBM_OWN2+0x0C) -+#define ARM_2_SEM4 HW_REGISTER_RW(ARM_SBM_OWN2+0x10) -+#define ARM_2_SEM5 HW_REGISTER_RW(ARM_SBM_OWN2+0x14) -+#define ARM_2_SEM6 HW_REGISTER_RW(ARM_SBM_OWN2+0x18) -+#define ARM_2_SEM7 HW_REGISTER_RW(ARM_SBM_OWN2+0x1C) -+#define ARM_2_BELL0 HW_REGISTER_RW(ARM_SBM_OWN2+0x40) -+#define ARM_2_BELL1 HW_REGISTER_RW(ARM_SBM_OWN2+0x44) -+#define ARM_2_BELL2 HW_REGISTER_RW(ARM_SBM_OWN2+0x48) -+#define ARM_2_BELL3 HW_REGISTER_RW(ARM_SBM_OWN2+0x4C) -+/* MAILBOX 0 access in Owner 2 area */ -+/* Owner 2 should only WRITE to this mailbox */ -+#define ARM_2_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0x80) /* .. 0x8C (4 locations) */ -+/*#define ARM_2_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN2+0x80) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_2_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN2+0x98) /* Status read */ -+/*#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C) */ /* DO NOT USE THIS !!!!! */ -+/* MAILBOX 1 access in Owner 2 area */ -+/* Owner 2 should only WRITE to this mailbox */ -+#define ARM_2_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) /* .. 0xAC (4 locations) */ -+/*#define ARM_2_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_2_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_2_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_2_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN2+0xB8) /* Status read */ -+/*#define ARM_2_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) */ /* DO NOT USE THIS !!!!! */ -+/* General SEM, BELL, MAIL config/status */ -+#define ARM_2_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE0) /* semaphore clear/debug register */ -+#define ARM_2_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE4) /* Doorbells clear/debug register */ -+#define ARM_2_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xFC) /* IRQS pending for owner 2 */ -+#define ARM_2_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xF8) /* ALL interrupts */ -+ -+/* Semaphores, Doorbells, Mailboxes Owner 3 */ -+#define ARM_3_SEMS HW_REGISTER_RW(ARM_SBM_OWN3+0x00) -+#define ARM_3_SEM0 HW_REGISTER_RW(ARM_SBM_OWN3+0x00) -+#define ARM_3_SEM1 HW_REGISTER_RW(ARM_SBM_OWN3+0x04) -+#define ARM_3_SEM2 HW_REGISTER_RW(ARM_SBM_OWN3+0x08) -+#define ARM_3_SEM3 HW_REGISTER_RW(ARM_SBM_OWN3+0x0C) -+#define ARM_3_SEM4 HW_REGISTER_RW(ARM_SBM_OWN3+0x10) -+#define ARM_3_SEM5 HW_REGISTER_RW(ARM_SBM_OWN3+0x14) -+#define ARM_3_SEM6 HW_REGISTER_RW(ARM_SBM_OWN3+0x18) -+#define ARM_3_SEM7 HW_REGISTER_RW(ARM_SBM_OWN3+0x1C) -+#define ARM_3_BELL0 HW_REGISTER_RW(ARM_SBM_OWN3+0x40) -+#define ARM_3_BELL1 HW_REGISTER_RW(ARM_SBM_OWN3+0x44) -+#define ARM_3_BELL2 HW_REGISTER_RW(ARM_SBM_OWN3+0x48) -+#define ARM_3_BELL3 HW_REGISTER_RW(ARM_SBM_OWN3+0x4C) -+/* MAILBOX 0 access in Owner 3 area */ -+/* Owner 3 should only WRITE to this mailbox */ -+#define ARM_3_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0x80) /* .. 0x8C (4 locations) */ -+/*#define ARM_3_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN3+0x80) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98) /* Status read */ -+/*#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C) */ /* DO NOT USE THIS !!!!! */ -+/* MAILBOX 1 access in Owner 3 area */ -+/* Owner 3 should only WRITE to this mailbox */ -+#define ARM_3_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) /* .. 0xAC (4 locations) */ -+/*#define ARM_3_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_3_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_3_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_3_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN3+0xB8) /* Status read */ -+/*#define ARM_3_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) */ /* DO NOT USE THIS !!!!! */ -+/* General SEM, BELL, MAIL config/status */ -+#define ARM_3_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE0) /* semaphore clear/debug register */ -+#define ARM_3_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE4) /* Doorbells clear/debug register */ -+#define ARM_3_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xFC) /* IRQS pending for owner 3 */ -+#define ARM_3_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xF8) /* ALL interrupts */ -+ -+ -+ -+/* Mailbox flags. Valid for all owners */ -+ -+/* Mailbox status register (...0x98) */ -+#define ARM_MS_FULL 0x80000000 -+#define ARM_MS_EMPTY 0x40000000 -+#define ARM_MS_LEVEL 0x400000FF /* Max. value depdnds on mailbox depth parameter */ -+ -+/* MAILBOX config/status register (...0x9C) */ -+/* ANY write to this register clears the error bits! */ -+#define ARM_MC_IHAVEDATAIRQEN 0x00000001 /* mailbox irq enable: has data */ -+#define ARM_MC_IHAVESPACEIRQEN 0x00000002 /* mailbox irq enable: has space */ -+#define ARM_MC_OPPISEMPTYIRQEN 0x00000004 /* mailbox irq enable: Opp. is empty */ -+#define ARM_MC_MAIL_CLEAR 0x00000008 /* mailbox clear write 1, then 0 */ -+#define ARM_MC_IHAVEDATAIRQPEND 0x00000010 /* mailbox irq pending: has space */ -+#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mailbox irq pending: Opp. is empty */ -+#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mailbox irq pending */ -+/* Bit 7 is unused */ -+#define ARM_MC_ERRNOOWN 0x00000100 /* error : none owner read from mailbox */ -+#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */ -+#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */ -+ -+/* Semaphore clear/debug register (...0xE0) */ -+#define ARM_SD_OWN0 0x00000003 /* Owner of sem 0 */ -+#define ARM_SD_OWN1 0x0000000C /* Owner of sem 1 */ -+#define ARM_SD_OWN2 0x00000030 /* Owner of sem 2 */ -+#define ARM_SD_OWN3 0x000000C0 /* Owner of sem 3 */ -+#define ARM_SD_OWN4 0x00000300 /* Owner of sem 4 */ -+#define ARM_SD_OWN5 0x00000C00 /* Owner of sem 5 */ -+#define ARM_SD_OWN6 0x00003000 /* Owner of sem 6 */ -+#define ARM_SD_OWN7 0x0000C000 /* Owner of sem 7 */ -+#define ARM_SD_SEM0 0x00010000 /* Status of sem 0 */ -+#define ARM_SD_SEM1 0x00020000 /* Status of sem 1 */ -+#define ARM_SD_SEM2 0x00040000 /* Status of sem 2 */ -+#define ARM_SD_SEM3 0x00080000 /* Status of sem 3 */ -+#define ARM_SD_SEM4 0x00100000 /* Status of sem 4 */ -+#define ARM_SD_SEM5 0x00200000 /* Status of sem 5 */ -+#define ARM_SD_SEM6 0x00400000 /* Status of sem 6 */ -+#define ARM_SD_SEM7 0x00800000 /* Status of sem 7 */ -+ -+/* Doorbells clear/debug register (...0xE4) */ -+#define ARM_BD_OWN0 0x00000003 /* Owner of doorbell 0 */ -+#define ARM_BD_OWN1 0x0000000C /* Owner of doorbell 1 */ -+#define ARM_BD_OWN2 0x00000030 /* Owner of doorbell 2 */ -+#define ARM_BD_OWN3 0x000000C0 /* Owner of doorbell 3 */ -+#define ARM_BD_BELL0 0x00000100 /* Status of doorbell 0 */ -+#define ARM_BD_BELL1 0x00000200 /* Status of doorbell 1 */ -+#define ARM_BD_BELL2 0x00000400 /* Status of doorbell 2 */ -+#define ARM_BD_BELL3 0x00000800 /* Status of doorbell 3 */ -+ -+/* MY IRQS register (...0xF8) */ -+#define ARM_MYIRQ_BELL 0x00000001 /* This owner has a doorbell IRQ */ -+#define ARM_MYIRQ_MAIL 0x00000002 /* This owner has a mailbox IRQ */ -+ -+/* ALL IRQS register (...0xF8) */ -+#define ARM_AIS_BELL0 0x00000001 /* Doorbell 0 IRQ pending */ -+#define ARM_AIS_BELL1 0x00000002 /* Doorbell 1 IRQ pending */ -+#define ARM_AIS_BELL2 0x00000004 /* Doorbell 2 IRQ pending */ -+#define ARM_AIS_BELL3 0x00000008 /* Doorbell 3 IRQ pending */ -+#define ARM_AIS0_HAVEDATA 0x00000010 /* MAIL 0 has data IRQ pending */ -+#define ARM_AIS0_HAVESPAC 0x00000020 /* MAIL 0 has space IRQ pending */ -+#define ARM_AIS0_OPPEMPTY 0x00000040 /* MAIL 0 opposite is empty IRQ */ -+#define ARM_AIS1_HAVEDATA 0x00000080 /* MAIL 1 has data IRQ pending */ -+#define ARM_AIS1_HAVESPAC 0x00000100 /* MAIL 1 has space IRQ pending */ -+#define ARM_AIS1_OPPEMPTY 0x00000200 /* MAIL 1 opposite is empty IRQ */ -+/* Note that bell-0, bell-1 and MAIL0 IRQ go only to the ARM */ -+/* Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC */ -+/* */ -+/* ARM JTAG BASH */ -+/* */ -+#define AJB_BASE 0x7e2000c0 -+ -+#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00) -+#define AJB_BITS0 0x000000 -+#define AJB_BITS4 0x000004 -+#define AJB_BITS8 0x000008 -+#define AJB_BITS12 0x00000C -+#define AJB_BITS16 0x000010 -+#define AJB_BITS20 0x000014 -+#define AJB_BITS24 0x000018 -+#define AJB_BITS28 0x00001C -+#define AJB_BITS32 0x000020 -+#define AJB_BITS34 0x000022 -+#define AJB_OUT_MS 0x000040 -+#define AJB_OUT_LS 0x000000 -+#define AJB_INV_CLK 0x000080 -+#define AJB_D0_RISE 0x000100 -+#define AJB_D0_FALL 0x000000 -+#define AJB_D1_RISE 0x000200 -+#define AJB_D1_FALL 0x000000 -+#define AJB_IN_RISE 0x000400 -+#define AJB_IN_FALL 0x000000 -+#define AJB_ENABLE 0x000800 -+#define AJB_HOLD0 0x000000 -+#define AJB_HOLD1 0x001000 -+#define AJB_HOLD2 0x002000 -+#define AJB_HOLD3 0x003000 -+#define AJB_RESETN 0x004000 -+#define AJB_CLKSHFT 16 -+#define AJB_BUSY 0x80000000 -+#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04) -+#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08) -+#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c) -+ -+#endif -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/clkdev.h linux-rpi/arch/arm/mach-bcm2708/include/mach/clkdev.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/clkdev.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/clkdev.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,7 @@ -+#ifndef __ASM_MACH_CLKDEV_H -+#define __ASM_MACH_CLKDEV_H -+ -+#define __clk_get(clk) ({ 1; }) -+#define __clk_put(clk) do { } while (0) -+ -+#endif -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/debug-macro.S linux-rpi/arch/arm/mach-bcm2708/include/mach/debug-macro.S ---- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/debug-macro.S 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/debug-macro.S 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,22 @@ -+/* arch/arm/mach-bcm2708/include/mach/debug-macro.S -+ * -+ * Debugging macro include header -+ * -+ * Copyright (C) 2010 Broadcom -+ * Copyright (C) 1994-1999 Russell King -+ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+*/ -+ -+#include -+ -+ .macro addruart, rp, rv, tmp -+ ldr \rp, =UART0_BASE -+ ldr \rv, =IO_ADDRESS(UART0_BASE) -+ .endm -+ -+#include -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/entry-macro.S linux-rpi/arch/arm/mach-bcm2708/include/mach/entry-macro.S ---- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/entry-macro.S 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/entry-macro.S 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,69 @@ -+/* -+ * arch/arm/mach-bcm2708/include/mach/entry-macro.S -+ * -+ * Low-level IRQ helper macros for BCM2708 platforms -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#include -+ -+ .macro disable_fiq -+ .endm -+ -+ .macro get_irqnr_preamble, base, tmp -+ ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE) -+ .endm -+ -+ .macro arch_ret_to_user, tmp1, tmp2 -+ .endm -+ -+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp -+ /* get masked status */ -+ ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)] -+ mov \irqnr, #(ARM_IRQ0_BASE + 31) -+ and \tmp, \irqstat, #0x300 @ save bits 8 and 9 -+ /* clear bits 8 and 9, and test */ -+ bics \irqstat, \irqstat, #0x300 -+ bne 1010f -+ -+ tst \tmp, #0x100 -+ ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)] -+ movne \irqnr, #(ARM_IRQ1_BASE + 31) -+ @ Mask out the interrupts also present in PEND0 - see SW-5809 -+ bicne \irqstat, #((1<<7) | (1<<9) | (1<<10)) -+ bicne \irqstat, #((1<<18) | (1<<19)) -+ bne 1010f -+ -+ tst \tmp, #0x200 -+ ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)] -+ movne \irqnr, #(ARM_IRQ2_BASE + 31) -+ @ Mask out the interrupts also present in PEND0 - see SW-5809 -+ bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25)) -+ bicne \irqstat, #((1<<30)) -+ beq 1020f -+ -+1010: -+ @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1)) -+ @ N.B. CLZ is an ARM5 instruction. -+ sub \tmp, \irqstat, #1 -+ eor \irqstat, \irqstat, \tmp -+ clz \tmp, \irqstat -+ sub \irqnr, \tmp -+ -+1020: @ EQ will be set if no irqs pending -+ -+ .endm -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/frc.h linux-rpi/arch/arm/mach-bcm2708/include/mach/frc.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/frc.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/frc.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,38 @@ -+/* -+ * arch/arm/mach-bcm2708/include/mach/timex.h -+ * -+ * BCM2708 free running counter (timer) -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef _MACH_FRC_H -+#define _MACH_FRC_H -+ -+#define FRC_TICK_RATE (1000000) -+ -+/*! Free running counter incrementing at the CLOCK_TICK_RATE -+ (slightly faster than frc_clock_ticks63() -+ */ -+extern unsigned long frc_clock_ticks32(void); -+ -+/*! Free running counter incrementing at the CLOCK_TICK_RATE -+ * Note - top bit should be ignored (see cnt32_to_63) -+ */ -+extern unsigned long long frc_clock_ticks63(void); -+ -+#endif -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/gpio.h linux-rpi/arch/arm/mach-bcm2708/include/mach/gpio.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/gpio.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/gpio.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,17 @@ -+/* -+ * arch/arm/mach-bcm2708/include/mach/gpio.h -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#ifndef __ASM_ARCH_GPIO_H -+#define __ASM_ARCH_GPIO_H -+ -+#define BCM2708_NR_GPIOS 54 // number of gpio lines -+ -+#define gpio_to_irq(x) ((x) + GPIO_IRQ_START) -+#define irq_to_gpio(x) ((x) - GPIO_IRQ_START) -+ -+#endif -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/hardware.h linux-rpi/arch/arm/mach-bcm2708/include/mach/hardware.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/hardware.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/hardware.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,28 @@ -+/* -+ * arch/arm/mach-bcm2708/include/mach/hardware.h -+ * -+ * This file contains the hardware definitions of the BCM2708 devices. -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#ifndef __ASM_ARCH_HARDWARE_H -+#define __ASM_ARCH_HARDWARE_H -+ -+#include -+#include -+ -+#endif -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/io.h linux-rpi/arch/arm/mach-bcm2708/include/mach/io.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/io.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/io.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,27 @@ -+/* -+ * arch/arm/mach-bcm2708/include/mach/io.h -+ * -+ * Copyright (C) 2003 ARM Limited -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#ifndef __ASM_ARM_ARCH_IO_H -+#define __ASM_ARM_ARCH_IO_H -+ -+#define IO_SPACE_LIMIT 0xffffffff -+ -+#define __io(a) __typesafe_io(a) -+ -+#endif -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/irqs.h linux-rpi/arch/arm/mach-bcm2708/include/mach/irqs.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/irqs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/irqs.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,199 @@ -+/* -+ * arch/arm/mach-bcm2708/include/mach/irqs.h -+ * -+ * Copyright (C) 2010 Broadcom -+ * Copyright (C) 2003 ARM Limited -+ * Copyright (C) 2000 Deep Blue Solutions Ltd. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef _BCM2708_IRQS_H_ -+#define _BCM2708_IRQS_H_ -+ -+#include -+ -+/* -+ * IRQ interrupts definitions are the same as the INT definitions -+ * held within platform.h -+ */ -+#define IRQ_ARMCTRL_START 0 -+#define IRQ_TIMER0 (IRQ_ARMCTRL_START + INTERRUPT_TIMER0) -+#define IRQ_TIMER1 (IRQ_ARMCTRL_START + INTERRUPT_TIMER1) -+#define IRQ_TIMER2 (IRQ_ARMCTRL_START + INTERRUPT_TIMER2) -+#define IRQ_TIMER3 (IRQ_ARMCTRL_START + INTERRUPT_TIMER3) -+#define IRQ_CODEC0 (IRQ_ARMCTRL_START + INTERRUPT_CODEC0) -+#define IRQ_CODEC1 (IRQ_ARMCTRL_START + INTERRUPT_CODEC1) -+#define IRQ_CODEC2 (IRQ_ARMCTRL_START + INTERRUPT_CODEC2) -+#define IRQ_JPEG (IRQ_ARMCTRL_START + INTERRUPT_JPEG) -+#define IRQ_ISP (IRQ_ARMCTRL_START + INTERRUPT_ISP) -+#define IRQ_USB (IRQ_ARMCTRL_START + INTERRUPT_USB) -+#define IRQ_3D (IRQ_ARMCTRL_START + INTERRUPT_3D) -+#define IRQ_TRANSPOSER (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER) -+#define IRQ_MULTICORESYNC0 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0) -+#define IRQ_MULTICORESYNC1 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1) -+#define IRQ_MULTICORESYNC2 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2) -+#define IRQ_MULTICORESYNC3 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3) -+#define IRQ_DMA0 (IRQ_ARMCTRL_START + INTERRUPT_DMA0) -+#define IRQ_DMA1 (IRQ_ARMCTRL_START + INTERRUPT_DMA1) -+#define IRQ_DMA2 (IRQ_ARMCTRL_START + INTERRUPT_DMA2) -+#define IRQ_DMA3 (IRQ_ARMCTRL_START + INTERRUPT_DMA3) -+#define IRQ_DMA4 (IRQ_ARMCTRL_START + INTERRUPT_DMA4) -+#define IRQ_DMA5 (IRQ_ARMCTRL_START + INTERRUPT_DMA5) -+#define IRQ_DMA6 (IRQ_ARMCTRL_START + INTERRUPT_DMA6) -+#define IRQ_DMA7 (IRQ_ARMCTRL_START + INTERRUPT_DMA7) -+#define IRQ_DMA8 (IRQ_ARMCTRL_START + INTERRUPT_DMA8) -+#define IRQ_DMA9 (IRQ_ARMCTRL_START + INTERRUPT_DMA9) -+#define IRQ_DMA10 (IRQ_ARMCTRL_START + INTERRUPT_DMA10) -+#define IRQ_DMA11 (IRQ_ARMCTRL_START + INTERRUPT_DMA11) -+#define IRQ_DMA12 (IRQ_ARMCTRL_START + INTERRUPT_DMA12) -+#define IRQ_AUX (IRQ_ARMCTRL_START + INTERRUPT_AUX) -+#define IRQ_ARM (IRQ_ARMCTRL_START + INTERRUPT_ARM) -+#define IRQ_VPUDMA (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA) -+#define IRQ_HOSTPORT (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT) -+#define IRQ_VIDEOSCALER (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER) -+#define IRQ_CCP2TX (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX) -+#define IRQ_SDC (IRQ_ARMCTRL_START + INTERRUPT_SDC) -+#define IRQ_DSI0 (IRQ_ARMCTRL_START + INTERRUPT_DSI0) -+#define IRQ_AVE (IRQ_ARMCTRL_START + INTERRUPT_AVE) -+#define IRQ_CAM0 (IRQ_ARMCTRL_START + INTERRUPT_CAM0) -+#define IRQ_CAM1 (IRQ_ARMCTRL_START + INTERRUPT_CAM1) -+#define IRQ_HDMI0 (IRQ_ARMCTRL_START + INTERRUPT_HDMI0) -+#define IRQ_HDMI1 (IRQ_ARMCTRL_START + INTERRUPT_HDMI1) -+#define IRQ_PIXELVALVE1 (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1) -+#define IRQ_I2CSPISLV (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV) -+#define IRQ_DSI1 (IRQ_ARMCTRL_START + INTERRUPT_DSI1) -+#define IRQ_PWA0 (IRQ_ARMCTRL_START + INTERRUPT_PWA0) -+#define IRQ_PWA1 (IRQ_ARMCTRL_START + INTERRUPT_PWA1) -+#define IRQ_CPR (IRQ_ARMCTRL_START + INTERRUPT_CPR) -+#define IRQ_SMI (IRQ_ARMCTRL_START + INTERRUPT_SMI) -+#define IRQ_GPIO0 (IRQ_ARMCTRL_START + INTERRUPT_GPIO0) -+#define IRQ_GPIO1 (IRQ_ARMCTRL_START + INTERRUPT_GPIO1) -+#define IRQ_GPIO2 (IRQ_ARMCTRL_START + INTERRUPT_GPIO2) -+#define IRQ_GPIO3 (IRQ_ARMCTRL_START + INTERRUPT_GPIO3) -+#define IRQ_I2C (IRQ_ARMCTRL_START + INTERRUPT_I2C) -+#define IRQ_SPI (IRQ_ARMCTRL_START + INTERRUPT_SPI) -+#define IRQ_I2SPCM (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM) -+#define IRQ_SDIO (IRQ_ARMCTRL_START + INTERRUPT_SDIO) -+#define IRQ_UART (IRQ_ARMCTRL_START + INTERRUPT_UART) -+#define IRQ_SLIMBUS (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS) -+#define IRQ_VEC (IRQ_ARMCTRL_START + INTERRUPT_VEC) -+#define IRQ_CPG (IRQ_ARMCTRL_START + INTERRUPT_CPG) -+#define IRQ_RNG (IRQ_ARMCTRL_START + INTERRUPT_RNG) -+#define IRQ_ARASANSDIO (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO) -+#define IRQ_AVSPMON (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON) -+ -+#define IRQ_ARM_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER) -+#define IRQ_ARM_MAILBOX (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX) -+#define IRQ_ARM_DOORBELL_0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0) -+#define IRQ_ARM_DOORBELL_1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1) -+#define IRQ_VPU0_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED) -+#define IRQ_VPU1_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED) -+#define IRQ_ILLEGAL_TYPE0 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0) -+#define IRQ_ILLEGAL_TYPE1 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1) -+#define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1) -+#define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2) -+ -+#define FIQ_START HARD_IRQS -+ -+/* -+ * FIQ interrupts definitions are the same as the INT definitions. -+ */ -+#define FIQ_TIMER0 (FIQ_START+INTERRUPT_TIMER0) -+#define FIQ_TIMER1 (FIQ_START+INTERRUPT_TIMER1) -+#define FIQ_TIMER2 (FIQ_START+INTERRUPT_TIMER2) -+#define FIQ_TIMER3 (FIQ_START+INTERRUPT_TIMER3) -+#define FIQ_CODEC0 (FIQ_START+INTERRUPT_CODEC0) -+#define FIQ_CODEC1 (FIQ_START+INTERRUPT_CODEC1) -+#define FIQ_CODEC2 (FIQ_START+INTERRUPT_CODEC2) -+#define FIQ_JPEG (FIQ_START+INTERRUPT_JPEG) -+#define FIQ_ISP (FIQ_START+INTERRUPT_ISP) -+#define FIQ_USB (FIQ_START+INTERRUPT_USB) -+#define FIQ_3D (FIQ_START+INTERRUPT_3D) -+#define FIQ_TRANSPOSER (FIQ_START+INTERRUPT_TRANSPOSER) -+#define FIQ_MULTICORESYNC0 (FIQ_START+INTERRUPT_MULTICORESYNC0) -+#define FIQ_MULTICORESYNC1 (FIQ_START+INTERRUPT_MULTICORESYNC1) -+#define FIQ_MULTICORESYNC2 (FIQ_START+INTERRUPT_MULTICORESYNC2) -+#define FIQ_MULTICORESYNC3 (FIQ_START+INTERRUPT_MULTICORESYNC3) -+#define FIQ_DMA0 (FIQ_START+INTERRUPT_DMA0) -+#define FIQ_DMA1 (FIQ_START+INTERRUPT_DMA1) -+#define FIQ_DMA2 (FIQ_START+INTERRUPT_DMA2) -+#define FIQ_DMA3 (FIQ_START+INTERRUPT_DMA3) -+#define FIQ_DMA4 (FIQ_START+INTERRUPT_DMA4) -+#define FIQ_DMA5 (FIQ_START+INTERRUPT_DMA5) -+#define FIQ_DMA6 (FIQ_START+INTERRUPT_DMA6) -+#define FIQ_DMA7 (FIQ_START+INTERRUPT_DMA7) -+#define FIQ_DMA8 (FIQ_START+INTERRUPT_DMA8) -+#define FIQ_DMA9 (FIQ_START+INTERRUPT_DMA9) -+#define FIQ_DMA10 (FIQ_START+INTERRUPT_DMA10) -+#define FIQ_DMA11 (FIQ_START+INTERRUPT_DMA11) -+#define FIQ_DMA12 (FIQ_START+INTERRUPT_DMA12) -+#define FIQ_AUX (FIQ_START+INTERRUPT_AUX) -+#define FIQ_ARM (FIQ_START+INTERRUPT_ARM) -+#define FIQ_VPUDMA (FIQ_START+INTERRUPT_VPUDMA) -+#define FIQ_HOSTPORT (FIQ_START+INTERRUPT_HOSTPORT) -+#define FIQ_VIDEOSCALER (FIQ_START+INTERRUPT_VIDEOSCALER) -+#define FIQ_CCP2TX (FIQ_START+INTERRUPT_CCP2TX) -+#define FIQ_SDC (FIQ_START+INTERRUPT_SDC) -+#define FIQ_DSI0 (FIQ_START+INTERRUPT_DSI0) -+#define FIQ_AVE (FIQ_START+INTERRUPT_AVE) -+#define FIQ_CAM0 (FIQ_START+INTERRUPT_CAM0) -+#define FIQ_CAM1 (FIQ_START+INTERRUPT_CAM1) -+#define FIQ_HDMI0 (FIQ_START+INTERRUPT_HDMI0) -+#define FIQ_HDMI1 (FIQ_START+INTERRUPT_HDMI1) -+#define FIQ_PIXELVALVE1 (FIQ_START+INTERRUPT_PIXELVALVE1) -+#define FIQ_I2CSPISLV (FIQ_START+INTERRUPT_I2CSPISLV) -+#define FIQ_DSI1 (FIQ_START+INTERRUPT_DSI1) -+#define FIQ_PWA0 (FIQ_START+INTERRUPT_PWA0) -+#define FIQ_PWA1 (FIQ_START+INTERRUPT_PWA1) -+#define FIQ_CPR (FIQ_START+INTERRUPT_CPR) -+#define FIQ_SMI (FIQ_START+INTERRUPT_SMI) -+#define FIQ_GPIO0 (FIQ_START+INTERRUPT_GPIO0) -+#define FIQ_GPIO1 (FIQ_START+INTERRUPT_GPIO1) -+#define FIQ_GPIO2 (FIQ_START+INTERRUPT_GPIO2) -+#define FIQ_GPIO3 (FIQ_START+INTERRUPT_GPIO3) -+#define FIQ_I2C (FIQ_START+INTERRUPT_I2C) -+#define FIQ_SPI (FIQ_START+INTERRUPT_SPI) -+#define FIQ_I2SPCM (FIQ_START+INTERRUPT_I2SPCM) -+#define FIQ_SDIO (FIQ_START+INTERRUPT_SDIO) -+#define FIQ_UART (FIQ_START+INTERRUPT_UART) -+#define FIQ_SLIMBUS (FIQ_START+INTERRUPT_SLIMBUS) -+#define FIQ_VEC (FIQ_START+INTERRUPT_VEC) -+#define FIQ_CPG (FIQ_START+INTERRUPT_CPG) -+#define FIQ_RNG (FIQ_START+INTERRUPT_RNG) -+#define FIQ_ARASANSDIO (FIQ_START+INTERRUPT_ARASANSDIO) -+#define FIQ_AVSPMON (FIQ_START+INTERRUPT_AVSPMON) -+ -+#define FIQ_ARM_TIMER (FIQ_START+INTERRUPT_ARM_TIMER) -+#define FIQ_ARM_MAILBOX (FIQ_START+INTERRUPT_ARM_MAILBOX) -+#define FIQ_ARM_DOORBELL_0 (FIQ_START+INTERRUPT_ARM_DOORBELL_0) -+#define FIQ_ARM_DOORBELL_1 (FIQ_START+INTERRUPT_ARM_DOORBELL_1) -+#define FIQ_VPU0_HALTED (FIQ_START+INTERRUPT_VPU0_HALTED) -+#define FIQ_VPU1_HALTED (FIQ_START+INTERRUPT_VPU1_HALTED) -+#define FIQ_ILLEGAL_TYPE0 (FIQ_START+INTERRUPT_ILLEGAL_TYPE0) -+#define FIQ_ILLEGAL_TYPE1 (FIQ_START+INTERRUPT_ILLEGAL_TYPE1) -+#define FIQ_PENDING1 (FIQ_START+INTERRUPT_PENDING1) -+#define FIQ_PENDING2 (FIQ_START+INTERRUPT_PENDING2) -+ -+#define HARD_IRQS (64 + 21) -+#define FIQ_IRQS (64 + 21) -+#define GPIO_IRQ_START (HARD_IRQS + FIQ_IRQS) -+#define GPIO_IRQS (32*5) -+#define SPARE_ALLOC_IRQS 64 -+#define BCM2708_ALLOC_IRQS (HARD_IRQS+FIQ_IRQS+GPIO_IRQS+SPARE_ALLOC_IRQS) -+#define FREE_IRQS 128 -+#define NR_IRQS (BCM2708_ALLOC_IRQS+FREE_IRQS) -+ -+#endif /* _BCM2708_IRQS_H_ */ -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/memory.h linux-rpi/arch/arm/mach-bcm2708/include/mach/memory.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/memory.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/memory.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,57 @@ -+/* -+ * arch/arm/mach-bcm2708/include/mach/memory.h -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#ifndef __ASM_ARCH_MEMORY_H -+#define __ASM_ARCH_MEMORY_H -+ -+/* Memory overview: -+ -+ [ARMcore] <--virtual addr--> -+ [ARMmmu] <--physical addr--> -+ [GERTmap] <--bus add--> -+ [VCperiph] -+ -+*/ -+ -+/* -+ * Physical DRAM offset. -+ */ -+#define BCM_PLAT_PHYS_OFFSET UL(0x00000000) -+#define VC_ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */ -+ -+#ifdef CONFIG_BCM2708_NOL2CACHE -+ #define _REAL_BUS_OFFSET UL(0xC0000000) /* don't use L1 or L2 caches */ -+#else -+ #define _REAL_BUS_OFFSET UL(0x40000000) /* use L2 cache */ -+#endif -+ -+/* We're using the memory at 64M in the VideoCore for Linux - this adjustment -+ * will provide the offset into this area as well as setting the bits that -+ * stop the L1 and L2 cache from being used -+ * -+ * WARNING: this only works because the ARM is given memory at a fixed location -+ * (ARMMEM_OFFSET) -+ */ -+#define BUS_OFFSET (VC_ARMMEM_OFFSET + _REAL_BUS_OFFSET) -+#define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET)) -+#define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET)) -+#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET)) -+#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET)) -+ -+#endif -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/platform.h linux-rpi/arch/arm/mach-bcm2708/include/mach/platform.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/platform.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/platform.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,230 @@ -+/* -+ * arch/arm/mach-bcm2708/include/mach/platform.h -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef _BCM2708_PLATFORM_H -+#define _BCM2708_PLATFORM_H -+ -+ -+/* macros to get at IO space when running virtually */ -+#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000) -+ -+#define __io_address(n) IOMEM(IO_ADDRESS(n)) -+ -+ -+/* -+ * SDRAM -+ */ -+#define BCM2708_SDRAM_BASE 0x00000000 -+ -+/* -+ * Logic expansion modules -+ * -+ */ -+ -+ -+/* ------------------------------------------------------------------------ -+ * BCM2708 ARMCTRL Registers -+ * ------------------------------------------------------------------------ -+ */ -+ -+#define HW_REGISTER_RW(addr) (addr) -+#define HW_REGISTER_RO(addr) (addr) -+ -+#include "arm_control.h" -+#undef ARM_BASE -+ -+/* -+ * Definitions and addresses for the ARM CONTROL logic -+ * This file is manually generated. -+ */ -+ -+#define BCM2708_PERI_BASE 0x20000000 -+#define IC0_BASE (BCM2708_PERI_BASE + 0x2000) -+#define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */ -+#define MPHI_BASE (BCM2708_PERI_BASE + 0x6000) /* Message -based Parallel Host Interface */ -+#define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */ -+#define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */ -+#define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */ -+#define PCM_CLOCK_BASE (BCM2708_PERI_BASE + 0x101098) /* PCM Clock */ -+#define RNG_BASE (BCM2708_PERI_BASE + 0x104000) /* Hardware RNG */ -+#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */ -+#define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */ -+#define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */ -+#define I2S_BASE (BCM2708_PERI_BASE + 0x203000) /* I2S */ -+#define SPI0_BASE (BCM2708_PERI_BASE + 0x204000) /* SPI0 */ -+#define BSC0_BASE (BCM2708_PERI_BASE + 0x205000) /* BSC0 I2C/TWI */ -+#define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */ -+#define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */ -+#define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */ -+#define BSC1_BASE (BCM2708_PERI_BASE + 0x804000) /* BSC1 I2C/TWI */ -+#define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */ -+#define MCORE_BASE (BCM2708_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/ -+ -+#define ARMCTRL_BASE (ARM_BASE + 0x000) -+#define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */ -+#define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */ -+#define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */ -+#define ARMCTRL_0_BELL_BASE (ARMCTRL_0_SBM_BASE + 0x40) /* User 0 (ARM)'s Doorbell */ -+#define ARMCTRL_0_MAIL0_BASE (ARMCTRL_0_SBM_BASE + 0x80) /* User 0 (ARM)'s Mailbox 0 */ -+ -+ -+/* -+ * Interrupt assignments -+ */ -+ -+#define ARM_IRQ1_BASE 0 -+#define INTERRUPT_TIMER0 (ARM_IRQ1_BASE + 0) -+#define INTERRUPT_TIMER1 (ARM_IRQ1_BASE + 1) -+#define INTERRUPT_TIMER2 (ARM_IRQ1_BASE + 2) -+#define INTERRUPT_TIMER3 (ARM_IRQ1_BASE + 3) -+#define INTERRUPT_CODEC0 (ARM_IRQ1_BASE + 4) -+#define INTERRUPT_CODEC1 (ARM_IRQ1_BASE + 5) -+#define INTERRUPT_CODEC2 (ARM_IRQ1_BASE + 6) -+#define INTERRUPT_VC_JPEG (ARM_IRQ1_BASE + 7) -+#define INTERRUPT_ISP (ARM_IRQ1_BASE + 8) -+#define INTERRUPT_VC_USB (ARM_IRQ1_BASE + 9) -+#define INTERRUPT_VC_3D (ARM_IRQ1_BASE + 10) -+#define INTERRUPT_TRANSPOSER (ARM_IRQ1_BASE + 11) -+#define INTERRUPT_MULTICORESYNC0 (ARM_IRQ1_BASE + 12) -+#define INTERRUPT_MULTICORESYNC1 (ARM_IRQ1_BASE + 13) -+#define INTERRUPT_MULTICORESYNC2 (ARM_IRQ1_BASE + 14) -+#define INTERRUPT_MULTICORESYNC3 (ARM_IRQ1_BASE + 15) -+#define INTERRUPT_DMA0 (ARM_IRQ1_BASE + 16) -+#define INTERRUPT_DMA1 (ARM_IRQ1_BASE + 17) -+#define INTERRUPT_VC_DMA2 (ARM_IRQ1_BASE + 18) -+#define INTERRUPT_VC_DMA3 (ARM_IRQ1_BASE + 19) -+#define INTERRUPT_DMA4 (ARM_IRQ1_BASE + 20) -+#define INTERRUPT_DMA5 (ARM_IRQ1_BASE + 21) -+#define INTERRUPT_DMA6 (ARM_IRQ1_BASE + 22) -+#define INTERRUPT_DMA7 (ARM_IRQ1_BASE + 23) -+#define INTERRUPT_DMA8 (ARM_IRQ1_BASE + 24) -+#define INTERRUPT_DMA9 (ARM_IRQ1_BASE + 25) -+#define INTERRUPT_DMA10 (ARM_IRQ1_BASE + 26) -+#define INTERRUPT_DMA11 (ARM_IRQ1_BASE + 27) -+#define INTERRUPT_DMA12 (ARM_IRQ1_BASE + 28) -+#define INTERRUPT_AUX (ARM_IRQ1_BASE + 29) -+#define INTERRUPT_ARM (ARM_IRQ1_BASE + 30) -+#define INTERRUPT_VPUDMA (ARM_IRQ1_BASE + 31) -+ -+#define ARM_IRQ2_BASE 32 -+#define INTERRUPT_HOSTPORT (ARM_IRQ2_BASE + 0) -+#define INTERRUPT_VIDEOSCALER (ARM_IRQ2_BASE + 1) -+#define INTERRUPT_CCP2TX (ARM_IRQ2_BASE + 2) -+#define INTERRUPT_SDC (ARM_IRQ2_BASE + 3) -+#define INTERRUPT_DSI0 (ARM_IRQ2_BASE + 4) -+#define INTERRUPT_AVE (ARM_IRQ2_BASE + 5) -+#define INTERRUPT_CAM0 (ARM_IRQ2_BASE + 6) -+#define INTERRUPT_CAM1 (ARM_IRQ2_BASE + 7) -+#define INTERRUPT_HDMI0 (ARM_IRQ2_BASE + 8) -+#define INTERRUPT_HDMI1 (ARM_IRQ2_BASE + 9) -+#define INTERRUPT_PIXELVALVE1 (ARM_IRQ2_BASE + 10) -+#define INTERRUPT_I2CSPISLV (ARM_IRQ2_BASE + 11) -+#define INTERRUPT_DSI1 (ARM_IRQ2_BASE + 12) -+#define INTERRUPT_PWA0 (ARM_IRQ2_BASE + 13) -+#define INTERRUPT_PWA1 (ARM_IRQ2_BASE + 14) -+#define INTERRUPT_CPR (ARM_IRQ2_BASE + 15) -+#define INTERRUPT_SMI (ARM_IRQ2_BASE + 16) -+#define INTERRUPT_GPIO0 (ARM_IRQ2_BASE + 17) -+#define INTERRUPT_GPIO1 (ARM_IRQ2_BASE + 18) -+#define INTERRUPT_GPIO2 (ARM_IRQ2_BASE + 19) -+#define INTERRUPT_GPIO3 (ARM_IRQ2_BASE + 20) -+#define INTERRUPT_VC_I2C (ARM_IRQ2_BASE + 21) -+#define INTERRUPT_VC_SPI (ARM_IRQ2_BASE + 22) -+#define INTERRUPT_VC_I2SPCM (ARM_IRQ2_BASE + 23) -+#define INTERRUPT_VC_SDIO (ARM_IRQ2_BASE + 24) -+#define INTERRUPT_VC_UART (ARM_IRQ2_BASE + 25) -+#define INTERRUPT_SLIMBUS (ARM_IRQ2_BASE + 26) -+#define INTERRUPT_VEC (ARM_IRQ2_BASE + 27) -+#define INTERRUPT_CPG (ARM_IRQ2_BASE + 28) -+#define INTERRUPT_RNG (ARM_IRQ2_BASE + 29) -+#define INTERRUPT_VC_ARASANSDIO (ARM_IRQ2_BASE + 30) -+#define INTERRUPT_AVSPMON (ARM_IRQ2_BASE + 31) -+ -+#define ARM_IRQ0_BASE 64 -+#define INTERRUPT_ARM_TIMER (ARM_IRQ0_BASE + 0) -+#define INTERRUPT_ARM_MAILBOX (ARM_IRQ0_BASE + 1) -+#define INTERRUPT_ARM_DOORBELL_0 (ARM_IRQ0_BASE + 2) -+#define INTERRUPT_ARM_DOORBELL_1 (ARM_IRQ0_BASE + 3) -+#define INTERRUPT_VPU0_HALTED (ARM_IRQ0_BASE + 4) -+#define INTERRUPT_VPU1_HALTED (ARM_IRQ0_BASE + 5) -+#define INTERRUPT_ILLEGAL_TYPE0 (ARM_IRQ0_BASE + 6) -+#define INTERRUPT_ILLEGAL_TYPE1 (ARM_IRQ0_BASE + 7) -+#define INTERRUPT_PENDING1 (ARM_IRQ0_BASE + 8) -+#define INTERRUPT_PENDING2 (ARM_IRQ0_BASE + 9) -+#define INTERRUPT_JPEG (ARM_IRQ0_BASE + 10) -+#define INTERRUPT_USB (ARM_IRQ0_BASE + 11) -+#define INTERRUPT_3D (ARM_IRQ0_BASE + 12) -+#define INTERRUPT_DMA2 (ARM_IRQ0_BASE + 13) -+#define INTERRUPT_DMA3 (ARM_IRQ0_BASE + 14) -+#define INTERRUPT_I2C (ARM_IRQ0_BASE + 15) -+#define INTERRUPT_SPI (ARM_IRQ0_BASE + 16) -+#define INTERRUPT_I2SPCM (ARM_IRQ0_BASE + 17) -+#define INTERRUPT_SDIO (ARM_IRQ0_BASE + 18) -+#define INTERRUPT_UART (ARM_IRQ0_BASE + 19) -+#define INTERRUPT_ARASANSDIO (ARM_IRQ0_BASE + 20) -+ -+#define MAXIRQNUM (32 + 32 + 20) -+#define MAXFIQNUM (32 + 32 + 20) -+ -+#define MAX_TIMER 2 -+#define MAX_PERIOD 699050 -+#define TICKS_PER_uSEC 1 -+ -+/* -+ * These are useconds NOT ticks. -+ * -+ */ -+#define mSEC_1 1000 -+#define mSEC_5 (mSEC_1 * 5) -+#define mSEC_10 (mSEC_1 * 10) -+#define mSEC_25 (mSEC_1 * 25) -+#define SEC_1 (mSEC_1 * 1000) -+ -+/* -+ * Watchdog -+ */ -+#define PM_RSTC (PM_BASE+0x1c) -+#define PM_RSTS (PM_BASE+0x20) -+#define PM_WDOG (PM_BASE+0x24) -+ -+#define PM_WDOG_RESET 0000000000 -+#define PM_PASSWORD 0x5a000000 -+#define PM_WDOG_TIME_SET 0x000fffff -+#define PM_RSTC_WRCFG_CLR 0xffffffcf -+#define PM_RSTC_WRCFG_SET 0x00000030 -+#define PM_RSTC_WRCFG_FULL_RESET 0x00000020 -+#define PM_RSTC_RESET 0x00000102 -+ -+#define PM_RSTS_HADPOR_SET 0x00001000 -+#define PM_RSTS_HADSRH_SET 0x00000400 -+#define PM_RSTS_HADSRF_SET 0x00000200 -+#define PM_RSTS_HADSRQ_SET 0x00000100 -+#define PM_RSTS_HADWRH_SET 0x00000040 -+#define PM_RSTS_HADWRF_SET 0x00000020 -+#define PM_RSTS_HADWRQ_SET 0x00000010 -+#define PM_RSTS_HADDRH_SET 0x00000004 -+#define PM_RSTS_HADDRF_SET 0x00000002 -+#define PM_RSTS_HADDRQ_SET 0x00000001 -+ -+#define UART0_CLOCK 3000000 -+ -+#endif -+ -+/* END */ -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/system.h linux-rpi/arch/arm/mach-bcm2708/include/mach/system.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/system.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/system.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,38 @@ -+/* -+ * arch/arm/mach-bcm2708/include/mach/system.h -+ * -+ * Copyright (C) 2010 Broadcom -+ * Copyright (C) 2003 ARM Limited -+ * Copyright (C) 2000 Deep Blue Solutions Ltd -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#ifndef __ASM_ARCH_SYSTEM_H -+#define __ASM_ARCH_SYSTEM_H -+ -+#include -+#include -+#include -+ -+static inline void arch_idle(void) -+{ -+ /* -+ * This should do all the clock switching -+ * and wait for interrupt tricks -+ */ -+ cpu_do_idle(); -+} -+ -+#endif -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/timex.h linux-rpi/arch/arm/mach-bcm2708/include/mach/timex.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/timex.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/timex.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,23 @@ -+/* -+ * arch/arm/mach-bcm2708/include/mach/timex.h -+ * -+ * BCM2708 sysem clock frequency -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#define CLOCK_TICK_RATE (1000000) -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/uncompress.h linux-rpi/arch/arm/mach-bcm2708/include/mach/uncompress.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/uncompress.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/uncompress.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,84 @@ -+/* -+ * arch/arm/mach-bcn2708/include/mach/uncompress.h -+ * -+ * Copyright (C) 2010 Broadcom -+ * Copyright (C) 2003 ARM Limited -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include -+#include -+#include -+ -+#define UART_BAUD 115200 -+ -+#define BCM2708_UART_DR __io(UART0_BASE + UART01x_DR) -+#define BCM2708_UART_FR __io(UART0_BASE + UART01x_FR) -+#define BCM2708_UART_IBRD __io(UART0_BASE + UART011_IBRD) -+#define BCM2708_UART_FBRD __io(UART0_BASE + UART011_FBRD) -+#define BCM2708_UART_LCRH __io(UART0_BASE + UART011_LCRH) -+#define BCM2708_UART_CR __io(UART0_BASE + UART011_CR) -+ -+/* -+ * This does not append a newline -+ */ -+static inline void putc(int c) -+{ -+ while (__raw_readl(BCM2708_UART_FR) & UART01x_FR_TXFF) -+ barrier(); -+ -+ __raw_writel(c, BCM2708_UART_DR); -+} -+ -+static inline void flush(void) -+{ -+ int fr; -+ -+ do { -+ fr = __raw_readl(BCM2708_UART_FR); -+ barrier(); -+ } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE); -+} -+ -+static inline void arch_decomp_setup(void) -+{ -+ int temp, div, rem, frac; -+ -+ temp = 16 * UART_BAUD; -+ div = UART0_CLOCK / temp; -+ rem = UART0_CLOCK % temp; -+ temp = (8 * rem) / UART_BAUD; -+ frac = (temp >> 1) + (temp & 1); -+ -+ /* Make sure the UART is disabled before we start */ -+ __raw_writel(0, BCM2708_UART_CR); -+ -+ /* Set the baud rate */ -+ __raw_writel(div, BCM2708_UART_IBRD); -+ __raw_writel(frac, BCM2708_UART_FBRD); -+ -+ /* Set the UART to 8n1, FIFO enabled */ -+ __raw_writel(UART01x_LCRH_WLEN_8 | UART01x_LCRH_FEN, BCM2708_UART_LCRH); -+ -+ /* Enable the UART */ -+ __raw_writel(UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_RXE, -+ BCM2708_UART_CR); -+} -+ -+/* -+ * nothing to do -+ */ -+#define arch_decomp_wdog() -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/vc_sm_defs.h linux-rpi/arch/arm/mach-bcm2708/include/mach/vc_sm_defs.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/vc_sm_defs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/vc_sm_defs.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,181 @@ -+/***************************************************************************** -+* Copyright 2011 Broadcom Corporation. All rights reserved. -+* -+* Unless you and Broadcom execute a separate written software license -+* agreement governing use of this software, this software is licensed to you -+* under the terms of the GNU General Public License version 2, available at -+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -+* -+* Notwithstanding the above, under no circumstances may you combine this -+* software in any way with any other Broadcom software provided under a -+* license other than the GPL, without Broadcom's express prior written -+* consent. -+*****************************************************************************/ -+ -+#ifndef __VC_SM_DEFS_H__INCLUDED__ -+#define __VC_SM_DEFS_H__INCLUDED__ -+ -+/* FourCC code used for VCHI connection */ -+#define VC_SM_SERVER_NAME MAKE_FOURCC("SMEM") -+ -+/* Maximum message length */ -+#define VC_SM_MAX_MSG_LEN (sizeof(VC_SM_MSG_UNION_T) + \ -+ sizeof(VC_SM_MSG_HDR_T)) -+#define VC_SM_MAX_RSP_LEN (sizeof(VC_SM_MSG_UNION_T)) -+ -+/* Resource name maximum size */ -+#define VC_SM_RESOURCE_NAME 32 -+ -+/* All message types supported for HOST->VC direction */ -+typedef enum { -+ /* Allocate shared memory block */ -+ VC_SM_MSG_TYPE_ALLOC, -+ /* Lock allocated shared memory block */ -+ VC_SM_MSG_TYPE_LOCK, -+ /* Unlock allocated shared memory block */ -+ VC_SM_MSG_TYPE_UNLOCK, -+ /* Unlock allocated shared memory block, do not answer command */ -+ VC_SM_MSG_TYPE_UNLOCK_NOANS, -+ /* Free shared memory block */ -+ VC_SM_MSG_TYPE_FREE, -+ /* Resize a shared memory block */ -+ VC_SM_MSG_TYPE_RESIZE, -+ /* Walk the allocated shared memory block(s) */ -+ VC_SM_MSG_TYPE_WALK_ALLOC, -+ -+ /* A previously applied action will need to be reverted */ -+ VC_SM_MSG_TYPE_ACTION_CLEAN, -+ VC_SM_MSG_TYPE_MAX -+} VC_SM_MSG_TYPE; -+ -+/* Type of memory to be allocated */ -+typedef enum { -+ VC_SM_ALLOC_CACHED, -+ VC_SM_ALLOC_NON_CACHED, -+ -+} VC_SM_ALLOC_TYPE_T; -+ -+/* Message header for all messages in HOST->VC direction */ -+typedef struct { -+ int32_t type; -+ uint32_t trans_id; -+ uint8_t body[0]; -+ -+} VC_SM_MSG_HDR_T; -+ -+/* Request to allocate memory (HOST->VC) */ -+typedef struct { -+ /* type of memory to allocate */ -+ VC_SM_ALLOC_TYPE_T type; -+ /* byte amount of data to allocate per unit */ -+ uint32_t base_unit; -+ /* number of unit to allocate */ -+ uint32_t num_unit; -+ /* alignement to be applied on allocation */ -+ uint32_t alignement; -+ /* identity of who allocated this block */ -+ uint32_t allocator; -+ /* resource name (for easier tracking on vc side) */ -+ char name[VC_SM_RESOURCE_NAME]; -+ -+} VC_SM_ALLOC_T; -+ -+/* Result of a requested memory allocation (VC->HOST) */ -+typedef struct { -+ /* Transaction identifier */ -+ uint32_t trans_id; -+ -+ /* Resource handle */ -+ uint32_t res_handle; -+ /* Pointer to resource buffer */ -+ void *res_mem; -+ /* Resource base size (bytes) */ -+ uint32_t res_base_size; -+ /* Resource number */ -+ uint32_t res_num; -+ -+} VC_SM_ALLOC_RESULT_T; -+ -+/* Request to free a previously allocated memory (HOST->VC) */ -+typedef struct { -+ /* Resource handle (returned from alloc) */ -+ uint32_t res_handle; -+ /* Resource buffer (returned from alloc) */ -+ void *res_mem; -+ -+} VC_SM_FREE_T; -+ -+/* Request to lock a previously allocated memory (HOST->VC) */ -+typedef struct { -+ /* Resource handle (returned from alloc) */ -+ uint32_t res_handle; -+ /* Resource buffer (returned from alloc) */ -+ void *res_mem; -+ -+} VC_SM_LOCK_UNLOCK_T; -+ -+/* Request to resize a previously allocated memory (HOST->VC) */ -+typedef struct { -+ /* Resource handle (returned from alloc) */ -+ uint32_t res_handle; -+ /* Resource buffer (returned from alloc) */ -+ void *res_mem; -+ /* Resource *new* size requested (bytes) */ -+ uint32_t res_new_size; -+ -+} VC_SM_RESIZE_T; -+ -+/* Result of a requested memory lock (VC->HOST) */ -+typedef struct { -+ /* Transaction identifier */ -+ uint32_t trans_id; -+ -+ /* Resource handle */ -+ uint32_t res_handle; -+ /* Pointer to resource buffer */ -+ void *res_mem; -+ /* Pointer to former resource buffer if the memory -+ * was reallocated */ -+ void *res_old_mem; -+ -+} VC_SM_LOCK_RESULT_T; -+ -+/* Generic result for a request (VC->HOST) */ -+typedef struct { -+ /* Transaction identifier */ -+ uint32_t trans_id; -+ -+ int32_t success; -+ -+} VC_SM_RESULT_T; -+ -+/* Request to revert a previously applied action (HOST->VC) */ -+typedef struct { -+ /* Action of interest */ -+ VC_SM_MSG_TYPE res_action; -+ /* Transaction identifier for the action of interest */ -+ uint32_t action_trans_id; -+ -+} VC_SM_ACTION_CLEAN_T; -+ -+/* Request to remove all data associated with a given allocator (HOST->VC) */ -+typedef struct { -+ /* Allocator identifier */ -+ uint32_t allocator; -+ -+} VC_SM_FREE_ALL_T; -+ -+/* Union of ALL messages */ -+typedef union { -+ VC_SM_ALLOC_T alloc; -+ VC_SM_ALLOC_RESULT_T alloc_result; -+ VC_SM_FREE_T free; -+ VC_SM_ACTION_CLEAN_T action_clean; -+ VC_SM_RESIZE_T resize; -+ VC_SM_LOCK_RESULT_T lock_result; -+ VC_SM_RESULT_T result; -+ VC_SM_FREE_ALL_T free_all; -+ -+} VC_SM_MSG_UNION_T; -+ -+#endif /* __VC_SM_DEFS_H__INCLUDED__ */ -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/vc_sm_knl.h linux-rpi/arch/arm/mach-bcm2708/include/mach/vc_sm_knl.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/vc_sm_knl.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/vc_sm_knl.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,55 @@ -+/***************************************************************************** -+* Copyright 2011 Broadcom Corporation. All rights reserved. -+* -+* Unless you and Broadcom execute a separate written software license -+* agreement governing use of this software, this software is licensed to you -+* under the terms of the GNU General Public License version 2, available at -+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -+* -+* Notwithstanding the above, under no circumstances may you combine this -+* software in any way with any other Broadcom software provided under a -+* license other than the GPL, without Broadcom's express prior written -+* consent. -+*****************************************************************************/ -+ -+#ifndef __VC_SM_KNL_H__INCLUDED__ -+#define __VC_SM_KNL_H__INCLUDED__ -+ -+#if !defined(__KERNEL__) -+#error "This interface is for kernel use only..." -+#endif -+ -+/* Type of memory to be locked (ie mapped) */ -+typedef enum { -+ VC_SM_LOCK_CACHED, -+ VC_SM_LOCK_NON_CACHED, -+ -+} VC_SM_LOCK_CACHE_MODE_T; -+ -+/* Allocate a shared memory handle and block. -+*/ -+int vc_sm_alloc(VC_SM_ALLOC_T *alloc, int *handle); -+ -+/* Free a previously allocated shared memory handle and block. -+*/ -+int vc_sm_free(int handle); -+ -+/* Lock a memory handle for use by kernel. -+*/ -+int vc_sm_lock(int handle, VC_SM_LOCK_CACHE_MODE_T mode, -+ long unsigned int *data); -+ -+/* Unlock a memory handle in use by kernel. -+*/ -+int vc_sm_unlock(int handle, int flush, int no_vc_unlock); -+ -+/* Get an internal resource handle mapped from the external one. -+*/ -+int vc_sm_int_handle(int handle); -+ -+/* Map a shared memory region for use by kernel. -+*/ -+int vc_sm_map(int handle, unsigned int sm_addr, VC_SM_LOCK_CACHE_MODE_T mode, -+ long unsigned int *data); -+ -+#endif /* __VC_SM_KNL_H__INCLUDED__ */ -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/vc_vchi_sm.h linux-rpi/arch/arm/mach-bcm2708/include/mach/vc_vchi_sm.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/vc_vchi_sm.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/vc_vchi_sm.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,82 @@ -+/***************************************************************************** -+* Copyright 2011 Broadcom Corporation. All rights reserved. -+* -+* Unless you and Broadcom execute a separate written software license -+* agreement governing use of this software, this software is licensed to you -+* under the terms of the GNU General Public License version 2, available at -+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -+* -+* Notwithstanding the above, under no circumstances may you combine this -+* software in any way with any other Broadcom software provided under a -+* license other than the GPL, without Broadcom's express prior written -+* consent. -+*****************************************************************************/ -+ -+#ifndef __VC_VCHI_SM_H__INCLUDED__ -+#define __VC_VCHI_SM_H__INCLUDED__ -+ -+#include "interface/vchi/vchi.h" -+ -+#include "vc_sm_defs.h" -+ -+/* Forward declare. -+*/ -+typedef struct sm_instance *VC_VCHI_SM_HANDLE_T; -+ -+/* Initialize the shared memory service, opens up vchi connection to talk to it. -+*/ -+VC_VCHI_SM_HANDLE_T vc_vchi_sm_init(VCHI_INSTANCE_T vchi_instance, -+ VCHI_CONNECTION_T **vchi_connections, -+ uint32_t num_connections); -+ -+/* Terminates the shared memory service. -+*/ -+int vc_vchi_sm_stop(VC_VCHI_SM_HANDLE_T *handle); -+ -+/* Ask the shared memory service to allocate some memory on videocre and -+** return the result of this allocation (which upon success will be a pointer -+** to some memory in videocore space). -+*/ -+int vc_vchi_sm_alloc(VC_VCHI_SM_HANDLE_T handle, -+ VC_SM_ALLOC_T *alloc, -+ VC_SM_ALLOC_RESULT_T *alloc_result, uint32_t *trans_id); -+ -+/* Ask the shared memory service to free up some memory that was previously -+** allocated by the vc_vchi_sm_alloc function call. -+*/ -+int vc_vchi_sm_free(VC_VCHI_SM_HANDLE_T handle, -+ VC_SM_FREE_T *free, uint32_t *trans_id); -+ -+/* Ask the shared memory service to lock up some memory that was previously -+** allocated by the vc_vchi_sm_alloc function call. -+*/ -+int vc_vchi_sm_lock(VC_VCHI_SM_HANDLE_T handle, -+ VC_SM_LOCK_UNLOCK_T *lock_unlock, -+ VC_SM_LOCK_RESULT_T *lock_result, uint32_t *trans_id); -+ -+/* Ask the shared memory service to unlock some memory that was previously -+** allocated by the vc_vchi_sm_alloc function call. -+*/ -+int vc_vchi_sm_unlock(VC_VCHI_SM_HANDLE_T handle, -+ VC_SM_LOCK_UNLOCK_T *lock_unlock, -+ uint32_t *trans_id, uint8_t wait_reply); -+ -+/* Ask the shared memory service to resize some memory that was previously -+** allocated by the vc_vchi_sm_alloc function call. -+*/ -+int vc_vchi_sm_resize(VC_VCHI_SM_HANDLE_T handle, -+ VC_SM_RESIZE_T *resize, uint32_t *trans_id); -+ -+/* Walk the allocated resources on the videocore side, the allocation will -+** show up in the log. This is purely for debug/information and takes no -+** specific actions. -+*/ -+int vc_vchi_sm_walk_alloc(VC_VCHI_SM_HANDLE_T handle); -+ -+/* Clean up following a previously interrupted action which left the system -+** in a bad state of some sort. -+*/ -+int vc_vchi_sm_clean_up(VC_VCHI_SM_HANDLE_T handle, -+ VC_SM_ACTION_CLEAN_T *action_clean); -+ -+#endif /* __VC_VCHI_SM_H__INCLUDED__ */ -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/vmalloc.h linux-rpi/arch/arm/mach-bcm2708/include/mach/vmalloc.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/vmalloc.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,20 @@ -+/* -+ * arch/arm/mach-bcm2708/include/mach/vmalloc.h -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#define VMALLOC_END (0xe8000000) -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/vmcs_sm_ioctl.h linux-rpi/arch/arm/mach-bcm2708/include/mach/vmcs_sm_ioctl.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/vmcs_sm_ioctl.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2708/include/mach/vmcs_sm_ioctl.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,248 @@ -+/***************************************************************************** -+* Copyright 2011 Broadcom Corporation. All rights reserved. -+* -+* Unless you and Broadcom execute a separate written software license -+* agreement governing use of this software, this software is licensed to you -+* under the terms of the GNU General Public License version 2, available at -+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -+* -+* Notwithstanding the above, under no circumstances may you combine this -+* software in any way with any other Broadcom software provided under a -+* license other than the GPL, without Broadcom's express prior written -+* consent. -+* -+*****************************************************************************/ -+ -+#if !defined(__VMCS_SM_IOCTL_H__INCLUDED__) -+#define __VMCS_SM_IOCTL_H__INCLUDED__ -+ -+/* ---- Include Files ---------------------------------------------------- */ -+ -+#if defined(__KERNEL__) -+#include /* Needed for standard types */ -+#else -+#include -+#endif -+ -+#include -+ -+/* ---- Constants and Types ---------------------------------------------- */ -+ -+#define VMCS_SM_RESOURCE_NAME 32 -+#define VMCS_SM_RESOURCE_NAME_DEFAULT "sm-host-resource" -+ -+/* Type define used to create unique IOCTL number */ -+#define VMCS_SM_MAGIC_TYPE 'I' -+ -+/* IOCTL commands */ -+enum vmcs_sm_cmd_e { -+ VMCS_SM_CMD_ALLOC = 0x5A, /* Start at 0x5A arbitrarily */ -+ VMCS_SM_CMD_ALLOC_SHARE, -+ VMCS_SM_CMD_LOCK, -+ VMCS_SM_CMD_LOCK_CACHE, -+ VMCS_SM_CMD_UNLOCK, -+ VMCS_SM_CMD_RESIZE, -+ VMCS_SM_CMD_UNMAP, -+ VMCS_SM_CMD_FREE, -+ VMCS_SM_CMD_FLUSH, -+ VMCS_SM_CMD_INVALID, -+ -+ VMCS_SM_CMD_SIZE_USR_HANDLE, -+ VMCS_SM_CMD_CHK_USR_HANDLE, -+ -+ VMCS_SM_CMD_MAPPED_USR_HANDLE, -+ VMCS_SM_CMD_MAPPED_USR_ADDRESS, -+ VMCS_SM_CMD_MAPPED_VC_HDL_FROM_ADDR, -+ VMCS_SM_CMD_MAPPED_VC_HDL_FROM_HDL, -+ VMCS_SM_CMD_MAPPED_VC_ADDR_FROM_HDL, -+ -+ VMCS_SM_CMD_VC_WALK_ALLOC, -+ VMCS_SM_CMD_HOST_WALK_MAP, -+ VMCS_SM_CMD_HOST_WALK_PID_ALLOC, -+ VMCS_SM_CMD_HOST_WALK_PID_MAP, -+ -+ VMCS_SM_CMD_CLEAN_INVALID, -+ -+ VMCS_SM_CMD_LAST /* Do no delete */ -+}; -+ -+/* Cache type supported, conveniently matches the user space definition in -+** user-vcsm.h. -+*/ -+enum vmcs_sm_cache_e { -+ VMCS_SM_CACHE_NONE, -+ VMCS_SM_CACHE_HOST, -+ VMCS_SM_CACHE_VC, -+ VMCS_SM_CACHE_BOTH, -+}; -+ -+/* IOCTL Data structures */ -+struct vmcs_sm_ioctl_alloc { -+ /* user -> kernel */ -+ unsigned int size; -+ unsigned int num; -+ enum vmcs_sm_cache_e cached; -+ char name[VMCS_SM_RESOURCE_NAME]; -+ -+ /* kernel -> user */ -+ unsigned int handle; -+ /* unsigned int base_addr; */ -+}; -+ -+struct vmcs_sm_ioctl_alloc_share { -+ /* user -> kernel */ -+ unsigned int handle; -+ unsigned int size; -+}; -+ -+struct vmcs_sm_ioctl_free { -+ /* user -> kernel */ -+ unsigned int handle; -+ /* unsigned int base_addr; */ -+}; -+ -+struct vmcs_sm_ioctl_lock_unlock { -+ /* user -> kernel */ -+ unsigned int handle; -+ -+ /* kernel -> user */ -+ unsigned int addr; -+}; -+ -+struct vmcs_sm_ioctl_lock_cache { -+ /* user -> kernel */ -+ unsigned int handle; -+ enum vmcs_sm_cache_e cached; -+}; -+ -+struct vmcs_sm_ioctl_resize { -+ /* user -> kernel */ -+ unsigned int handle; -+ unsigned int new_size; -+ -+ /* kernel -> user */ -+ unsigned int old_size; -+}; -+ -+struct vmcs_sm_ioctl_map { -+ /* user -> kernel */ -+ /* and kernel -> user */ -+ unsigned int pid; -+ unsigned int handle; -+ unsigned int addr; -+ -+ /* kernel -> user */ -+ unsigned int size; -+}; -+ -+struct vmcs_sm_ioctl_walk { -+ /* user -> kernel */ -+ unsigned int pid; -+}; -+ -+struct vmcs_sm_ioctl_chk { -+ /* user -> kernel */ -+ unsigned int handle; -+ -+ /* kernel -> user */ -+ unsigned int addr; -+ unsigned int size; -+ enum vmcs_sm_cache_e cache; -+}; -+ -+struct vmcs_sm_ioctl_size { -+ /* user -> kernel */ -+ unsigned int handle; -+ -+ /* kernel -> user */ -+ unsigned int size; -+}; -+ -+struct vmcs_sm_ioctl_cache { -+ /* user -> kernel */ -+ unsigned int handle; -+ unsigned int addr; -+ unsigned int size; -+}; -+ -+struct vmcs_sm_ioctl_clean_invalid { -+ /* user -> kernel */ -+ struct { -+ unsigned int cmd; -+ unsigned int handle; -+ unsigned int addr; -+ unsigned int size; -+ } s[8]; -+}; -+ -+/* IOCTL numbers */ -+#define VMCS_SM_IOCTL_MEM_ALLOC\ -+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_ALLOC,\ -+ struct vmcs_sm_ioctl_alloc) -+#define VMCS_SM_IOCTL_MEM_ALLOC_SHARE\ -+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_ALLOC_SHARE,\ -+ struct vmcs_sm_ioctl_alloc_share) -+#define VMCS_SM_IOCTL_MEM_LOCK\ -+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_LOCK,\ -+ struct vmcs_sm_ioctl_lock_unlock) -+#define VMCS_SM_IOCTL_MEM_LOCK_CACHE\ -+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_LOCK_CACHE,\ -+ struct vmcs_sm_ioctl_lock_cache) -+#define VMCS_SM_IOCTL_MEM_UNLOCK\ -+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_UNLOCK,\ -+ struct vmcs_sm_ioctl_lock_unlock) -+#define VMCS_SM_IOCTL_MEM_RESIZE\ -+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_RESIZE,\ -+ struct vmcs_sm_ioctl_resize) -+#define VMCS_SM_IOCTL_MEM_FREE\ -+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_FREE,\ -+ struct vmcs_sm_ioctl_free) -+#define VMCS_SM_IOCTL_MEM_FLUSH\ -+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_FLUSH,\ -+ struct vmcs_sm_ioctl_cache) -+#define VMCS_SM_IOCTL_MEM_INVALID\ -+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_INVALID,\ -+ struct vmcs_sm_ioctl_cache) -+#define VMCS_SM_IOCTL_MEM_CLEAN_INVALID\ -+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_CLEAN_INVALID,\ -+ struct vmcs_sm_ioctl_clean_invalid) -+ -+#define VMCS_SM_IOCTL_SIZE_USR_HDL\ -+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_SIZE_USR_HANDLE,\ -+ struct vmcs_sm_ioctl_size) -+#define VMCS_SM_IOCTL_CHK_USR_HDL\ -+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_CHK_USR_HANDLE,\ -+ struct vmcs_sm_ioctl_chk) -+ -+#define VMCS_SM_IOCTL_MAP_USR_HDL\ -+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_USR_HANDLE,\ -+ struct vmcs_sm_ioctl_map) -+#define VMCS_SM_IOCTL_MAP_USR_ADDRESS\ -+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_USR_ADDRESS,\ -+ struct vmcs_sm_ioctl_map) -+#define VMCS_SM_IOCTL_MAP_VC_HDL_FR_ADDR\ -+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_VC_HDL_FROM_ADDR,\ -+ struct vmcs_sm_ioctl_map) -+#define VMCS_SM_IOCTL_MAP_VC_HDL_FR_HDL\ -+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_VC_HDL_FROM_HDL,\ -+ struct vmcs_sm_ioctl_map) -+#define VMCS_SM_IOCTL_MAP_VC_ADDR_FR_HDL\ -+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_VC_ADDR_FROM_HDL,\ -+ struct vmcs_sm_ioctl_map) -+ -+#define VMCS_SM_IOCTL_VC_WALK_ALLOC\ -+ _IO(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_VC_WALK_ALLOC) -+#define VMCS_SM_IOCTL_HOST_WALK_MAP\ -+ _IO(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_HOST_WALK_MAP) -+#define VMCS_SM_IOCTL_HOST_WALK_PID_ALLOC\ -+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_HOST_WALK_PID_ALLOC,\ -+ struct vmcs_sm_ioctl_walk) -+#define VMCS_SM_IOCTL_HOST_WALK_PID_MAP\ -+ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_HOST_WALK_PID_MAP,\ -+ struct vmcs_sm_ioctl_walk) -+ -+/* ---- Variable Externs ------------------------------------------------- */ -+ -+/* ---- Function Prototypes ---------------------------------------------- */ -+ -+#endif /* __VMCS_SM_IOCTL_H__INCLUDED__ */ -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/Kconfig linux-rpi/arch/arm/mach-bcm2708/Kconfig ---- linux-4.1.13.orig/arch/arm/mach-bcm2708/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2708/Kconfig 2015-11-29 09:42:34.787439667 +0100 -@@ -0,0 +1,45 @@ -+menu "Broadcom BCM2708 Implementations" -+ depends on ARCH_BCM2708 -+ -+config MACH_BCM2708 -+ bool "Broadcom BCM2708 Development Platform" -+ select NEED_MACH_MEMORY_H -+ select NEED_MACH_IO_H -+ select CPU_V6 -+ help -+ Include support for the Broadcom(R) BCM2708 platform. -+ -+config BCM2708_DT -+ bool "BCM2708 Device Tree support" -+ depends on MACH_BCM2708 -+ default n -+ select USE_OF -+ select ARCH_REQUIRE_GPIOLIB -+ select PINCTRL -+ select PINCTRL_BCM2835 -+ help -+ Enable Device Tree support for BCM2708 -+ -+config BCM2708_GPIO -+ bool "BCM2708 gpio support" -+ depends on MACH_BCM2708 -+ select ARCH_REQUIRE_GPIOLIB -+ default y -+ help -+ Include support for the Broadcom(R) BCM2708 gpio. -+ -+config BCM2708_NOL2CACHE -+ bool "Videocore L2 cache disable" -+ depends on MACH_BCM2708 -+ default n -+ help -+ Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt. -+ -+config BCM2708_SPIDEV -+ bool "Bind spidev to SPI0 master" -+ depends on MACH_BCM2708 -+ depends on SPI -+ default y -+ help -+ Binds spidev driver to the SPI0 master -+endmenu -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/Makefile linux-rpi/arch/arm/mach-bcm2708/Makefile ---- linux-4.1.13.orig/arch/arm/mach-bcm2708/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2708/Makefile 2015-11-29 09:42:34.787439667 +0100 -@@ -0,0 +1,6 @@ -+# -+# Makefile for the linux kernel. -+# -+ -+obj-$(CONFIG_MACH_BCM2708) += bcm2708.o armctrl.o -+obj-$(CONFIG_BCM2708_GPIO) += bcm2708_gpio.o -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/Makefile.boot linux-rpi/arch/arm/mach-bcm2708/Makefile.boot ---- linux-4.1.13.orig/arch/arm/mach-bcm2708/Makefile.boot 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2708/Makefile.boot 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,3 @@ -+ zreladdr-y := 0x00008000 -+params_phys-y := 0x00000100 -+initrd_phys-y := 0x00800000 -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/armctrl.c linux-rpi/arch/arm/mach-bcm2709/armctrl.c ---- linux-4.1.13.orig/arch/arm/mach-bcm2709/armctrl.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2709/armctrl.c 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,384 @@ -+/* -+ * linux/arch/arm/mach-bcm2708/armctrl.c -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include "armctrl.h" -+ -+/* For support of kernels >= 3.0 assume only one VIC for now*/ -+static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = { -+ INTERRUPT_VC_JPEG, -+ INTERRUPT_VC_USB, -+ INTERRUPT_VC_3D, -+ INTERRUPT_VC_DMA2, -+ INTERRUPT_VC_DMA3, -+ INTERRUPT_VC_I2C, -+ INTERRUPT_VC_SPI, -+ INTERRUPT_VC_I2SPCM, -+ INTERRUPT_VC_SDIO, -+ INTERRUPT_VC_UART, -+ INTERRUPT_VC_ARASANSDIO -+}; -+ -+extern unsigned force_core; -+ -+static void armctrl_mask_irq(struct irq_data *d) -+{ -+ static const unsigned int disables[4] = { -+ ARM_IRQ_DIBL1, -+ ARM_IRQ_DIBL2, -+ ARM_IRQ_DIBL3, -+ 0 -+ }; -+ int i; -+ if (d->irq >= FIQ_START) { -+ writel(0, __io_address(ARM_IRQ_FAST)); -+ } else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) { -+#if 1 -+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_CNTPSIRQ; -+ for (i=0; i<4; i++) // i = raw_smp_processor_id(); // -+ { -+ unsigned int val = readl(__io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); -+ writel(val &~ (1 << data), __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); -+ } -+#endif -+ } else if (d->irq >= IRQ_ARM_LOCAL_MAILBOX0 && d->irq < IRQ_ARM_LOCAL_MAILBOX0 + 4) { -+#if 0 -+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_MAILBOX0; -+ for (i=0; i<4; i++) { -+ unsigned int val = readl(__io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); -+ writel(val &~ (1 << data), __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); -+ } -+#endif -+ } else if (d->irq >= ARM_IRQ1_BASE && d->irq < ARM_IRQ_LOCAL_BASE) { -+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq); -+ writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3])); -+ } else if (d->irq == INTERRUPT_ARM_LOCAL_PMU_FAST) { -+ writel(0xf, __io_address(ARM_LOCAL_PM_ROUTING_CLR)); -+ } else { printk("%s: %d\n", __func__, d->irq); BUG(); } -+} -+ -+static void armctrl_unmask_irq(struct irq_data *d) -+{ -+ static const unsigned int enables[4] = { -+ ARM_IRQ_ENBL1, -+ ARM_IRQ_ENBL2, -+ ARM_IRQ_ENBL3, -+ 0 -+ }; -+ int i; -+ if (d->irq >= FIQ_START) { -+ unsigned int data; -+ if (force_core) { -+ data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING)); -+ data &= ~0xc; -+ data |= ((force_core-1) << 2); -+ writel(data, __io_address(ARM_LOCAL_GPU_INT_ROUTING)); -+ } -+ else if (num_online_cpus() > 1) { -+ data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING)); -+ data &= ~0xc; -+ data |= (1 << 2); -+ writel(data, __io_address(ARM_LOCAL_GPU_INT_ROUTING)); -+ } -+ /* Unmask in ARMCTRL block after routing it properly */ -+ data = (unsigned int)irq_get_chip_data(d->irq) - FIQ_START; -+ writel(0x80 | data, __io_address(ARM_IRQ_FAST)); -+ } else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) { -+#if 1 -+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_CNTPSIRQ; -+ for (i=0; i<4; i++) // i = raw_smp_processor_id(); -+ { -+ unsigned int val = readl(__io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); -+ writel(val | (1 << data), __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); -+ } -+#endif -+ } else if (d->irq >= IRQ_ARM_LOCAL_MAILBOX0 && d->irq < IRQ_ARM_LOCAL_MAILBOX0 + 4) { -+#if 0 -+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_MAILBOX0; -+ for (i=0; i<4; i++) { -+ unsigned int val = readl(__io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); -+ writel(val | (1 << data), __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); -+ } -+#endif -+ } else if (d->irq >= ARM_IRQ1_BASE && d->irq < ARM_IRQ_LOCAL_BASE) { -+ if (force_core) { -+ unsigned int data; -+ data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING)); -+ data &= ~0x3; -+ data |= ((force_core-1) << 0); -+ writel(data, __io_address(ARM_LOCAL_GPU_INT_ROUTING)); -+ } -+ unsigned int data = (unsigned int)irq_get_chip_data(d->irq); -+ writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3])); -+ } else if (d->irq == INTERRUPT_ARM_LOCAL_PMU_FAST) { -+ writel(0xf, __io_address(ARM_LOCAL_PM_ROUTING_SET)); -+ } else { printk("%s: %d\n", __func__, d->irq); BUG(); } -+} -+ -+#ifdef CONFIG_OF -+ -+#define NR_IRQS_BANK0 21 -+#define NR_BANKS 4 -+#define IRQS_PER_BANK 32 -+ -+/* from drivers/irqchip/irq-bcm2835.c */ -+static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr, -+ const u32 *intspec, unsigned int intsize, -+ unsigned long *out_hwirq, unsigned int *out_type) -+{ -+ if (WARN_ON(intsize != 2)) -+ return -EINVAL; -+ -+ if (WARN_ON(intspec[0] >= NR_BANKS)) -+ return -EINVAL; -+ -+ if (WARN_ON(intspec[1] >= IRQS_PER_BANK)) -+ return -EINVAL; -+ -+ if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0)) -+ return -EINVAL; -+ -+ if (WARN_ON(intspec[0] == 3 && intspec[1] > 3 && intspec[1] != 5 && intspec[1] != 9)) -+ return -EINVAL; -+ -+ if (intspec[0] == 0) -+ *out_hwirq = ARM_IRQ0_BASE + intspec[1]; -+ else if (intspec[0] == 1) -+ *out_hwirq = ARM_IRQ1_BASE + intspec[1]; -+ else if (intspec[0] == 2) -+ *out_hwirq = ARM_IRQ2_BASE + intspec[1]; -+ else -+ *out_hwirq = ARM_IRQ_LOCAL_BASE + intspec[1]; -+ -+ /* reverse remap_irqs[] */ -+ switch (*out_hwirq) { -+ case INTERRUPT_VC_JPEG: -+ *out_hwirq = INTERRUPT_JPEG; -+ break; -+ case INTERRUPT_VC_USB: -+ *out_hwirq = INTERRUPT_USB; -+ break; -+ case INTERRUPT_VC_3D: -+ *out_hwirq = INTERRUPT_3D; -+ break; -+ case INTERRUPT_VC_DMA2: -+ *out_hwirq = INTERRUPT_DMA2; -+ break; -+ case INTERRUPT_VC_DMA3: -+ *out_hwirq = INTERRUPT_DMA3; -+ break; -+ case INTERRUPT_VC_I2C: -+ *out_hwirq = INTERRUPT_I2C; -+ break; -+ case INTERRUPT_VC_SPI: -+ *out_hwirq = INTERRUPT_SPI; -+ break; -+ case INTERRUPT_VC_I2SPCM: -+ *out_hwirq = INTERRUPT_I2SPCM; -+ break; -+ case INTERRUPT_VC_SDIO: -+ *out_hwirq = INTERRUPT_SDIO; -+ break; -+ case INTERRUPT_VC_UART: -+ *out_hwirq = INTERRUPT_UART; -+ break; -+ case INTERRUPT_VC_ARASANSDIO: -+ *out_hwirq = INTERRUPT_ARASANSDIO; -+ break; -+ } -+ -+ *out_type = IRQ_TYPE_NONE; -+ return 0; -+} -+ -+static struct irq_domain_ops armctrl_ops = { -+ .xlate = armctrl_xlate -+}; -+ -+void __init armctrl_dt_init(void) -+{ -+ struct device_node *np; -+ struct irq_domain *domain; -+ -+ np = of_find_compatible_node(NULL, NULL, "brcm,bcm2708-armctrl-ic"); -+ if (!np) -+ return; -+ -+ domain = irq_domain_add_legacy(np, BCM2708_ALLOC_IRQS, -+ IRQ_ARMCTRL_START, 0, -+ &armctrl_ops, NULL); -+ WARN_ON(!domain); -+} -+#else -+void __init armctrl_dt_init(void) { } -+#endif /* CONFIG_OF */ -+ -+#if defined(CONFIG_PM) -+ -+/* for kernels 3.xx use the new syscore_ops apis but for older kernels use the sys dev class */ -+ -+/* Static defines -+ * struct armctrl_device - VIC PM device (< 3.xx) -+ * @sysdev: The system device which is registered. (< 3.xx) -+ * @irq: The IRQ number for the base of the VIC. -+ * @base: The register base for the VIC. -+ * @resume_sources: A bitmask of interrupts for resume. -+ * @resume_irqs: The IRQs enabled for resume. -+ * @int_select: Save for VIC_INT_SELECT. -+ * @int_enable: Save for VIC_INT_ENABLE. -+ * @soft_int: Save for VIC_INT_SOFT. -+ * @protect: Save for VIC_PROTECT. -+ */ -+struct armctrl_info { -+ void __iomem *base; -+ int irq; -+ u32 resume_sources; -+ u32 resume_irqs; -+ u32 int_select; -+ u32 int_enable; -+ u32 soft_int; -+ u32 protect; -+} armctrl; -+ -+static int armctrl_suspend(void) -+{ -+ return 0; -+} -+ -+static void armctrl_resume(void) -+{ -+ return; -+} -+ -+/** -+ * armctrl_pm_register - Register a VIC for later power management control -+ * @base: The base address of the VIC. -+ * @irq: The base IRQ for the VIC. -+ * @resume_sources: bitmask of interrupts allowed for resume sources. -+ * -+ * For older kernels (< 3.xx) do - -+ * Register the VIC with the system device tree so that it can be notified -+ * of suspend and resume requests and ensure that the correct actions are -+ * taken to re-instate the settings on resume. -+ */ -+static void __init armctrl_pm_register(void __iomem * base, unsigned int irq, -+ u32 resume_sources) -+{ -+ armctrl.base = base; -+ armctrl.resume_sources = resume_sources; -+ armctrl.irq = irq; -+} -+ -+static int armctrl_set_wake(struct irq_data *d, unsigned int on) -+{ -+ unsigned int off = d->irq & 31; -+ u32 bit = 1 << off; -+ -+ if (!(bit & armctrl.resume_sources)) -+ return -EINVAL; -+ -+ if (on) -+ armctrl.resume_irqs |= bit; -+ else -+ armctrl.resume_irqs &= ~bit; -+ -+ return 0; -+} -+ -+#else -+static inline void armctrl_pm_register(void __iomem * base, unsigned int irq, -+ u32 arg1) -+{ -+} -+ -+#define armctrl_suspend NULL -+#define armctrl_resume NULL -+#define armctrl_set_wake NULL -+#endif /* CONFIG_PM */ -+ -+static struct syscore_ops armctrl_syscore_ops = { -+ .suspend = armctrl_suspend, -+ .resume = armctrl_resume, -+}; -+ -+/** -+ * armctrl_syscore_init - initicall to register VIC pm functions -+ * -+ * This is called via late_initcall() to register -+ * the resources for the VICs due to the early -+ * nature of the VIC's registration. -+*/ -+static int __init armctrl_syscore_init(void) -+{ -+ register_syscore_ops(&armctrl_syscore_ops); -+ return 0; -+} -+ -+late_initcall(armctrl_syscore_init); -+ -+static struct irq_chip armctrl_chip = { -+ .name = "ARMCTRL", -+ .irq_ack = NULL, -+ .irq_mask = armctrl_mask_irq, -+ .irq_unmask = armctrl_unmask_irq, -+ .irq_set_wake = armctrl_set_wake, -+}; -+ -+/** -+ * armctrl_init - initialise a vectored interrupt controller -+ * @base: iomem base address -+ * @irq_start: starting interrupt number, must be muliple of 32 -+ * @armctrl_sources: bitmask of interrupt sources to allow -+ * @resume_sources: bitmask of interrupt sources to allow for resume -+ */ -+int __init armctrl_init(void __iomem * base, unsigned int irq_start, -+ u32 armctrl_sources, u32 resume_sources) -+{ -+ unsigned int irq; -+ -+ for (irq = 0; irq < BCM2708_ALLOC_IRQS; irq++) { -+ unsigned int data = irq; -+ if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO) -+ data = remap_irqs[irq - INTERRUPT_JPEG]; -+ if (irq >= IRQ_ARM_LOCAL_CNTPSIRQ && irq <= IRQ_ARM_LOCAL_TIMER) { -+ irq_set_percpu_devid(irq); -+ irq_set_chip_and_handler(irq, &armctrl_chip, handle_percpu_devid_irq); -+ set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN); -+ } else { -+ irq_set_chip_and_handler(irq, &armctrl_chip, handle_level_irq); -+ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); -+ } -+ irq_set_chip_data(irq, (void *)data); -+ } -+ -+ armctrl_pm_register(base, irq_start, resume_sources); -+ init_FIQ(FIQ_START); -+ armctrl_dt_init(); -+ return 0; -+} -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/armctrl.h linux-rpi/arch/arm/mach-bcm2709/armctrl.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2709/armctrl.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2709/armctrl.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,27 @@ -+/* -+ * linux/arch/arm/mach-bcm2708/armctrl.h -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef __BCM2708_ARMCTRL_H -+#define __BCM2708_ARMCTRL_H -+ -+extern int __init armctrl_init(void __iomem * base, unsigned int irq_start, -+ u32 armctrl_sources, u32 resume_sources); -+ -+#endif -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/bcm2708_gpio.c linux-rpi/arch/arm/mach-bcm2709/bcm2708_gpio.c ---- linux-4.1.13.orig/arch/arm/mach-bcm2709/bcm2708_gpio.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2709/bcm2708_gpio.c 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,426 @@ -+/* -+ * linux/arch/arm/mach-bcm2708/bcm2708_gpio.c -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio" -+#define DRIVER_NAME BCM_GPIO_DRIVER_NAME -+#define BCM_GPIO_USE_IRQ 1 -+ -+#define GPIOFSEL(x) (0x00+(x)*4) -+#define GPIOSET(x) (0x1c+(x)*4) -+#define GPIOCLR(x) (0x28+(x)*4) -+#define GPIOLEV(x) (0x34+(x)*4) -+#define GPIOEDS(x) (0x40+(x)*4) -+#define GPIOREN(x) (0x4c+(x)*4) -+#define GPIOFEN(x) (0x58+(x)*4) -+#define GPIOHEN(x) (0x64+(x)*4) -+#define GPIOLEN(x) (0x70+(x)*4) -+#define GPIOAREN(x) (0x7c+(x)*4) -+#define GPIOAFEN(x) (0x88+(x)*4) -+#define GPIOUD(x) (0x94+(x)*4) -+#define GPIOUDCLK(x) (0x98+(x)*4) -+ -+#define GPIO_BANKS 2 -+ -+enum { GPIO_FSEL_INPUT, GPIO_FSEL_OUTPUT, -+ GPIO_FSEL_ALT5, GPIO_FSEL_ALT_4, -+ GPIO_FSEL_ALT0, GPIO_FSEL_ALT1, -+ GPIO_FSEL_ALT2, GPIO_FSEL_ALT3, -+}; -+ -+ /* Each of the two spinlocks protects a different set of hardware -+ * regiters and data structurs. This decouples the code of the IRQ from -+ * the GPIO code. This also makes the case of a GPIO routine call from -+ * the IRQ code simpler. -+ */ -+static DEFINE_SPINLOCK(lock); /* GPIO registers */ -+ -+struct bcm2708_gpio { -+ struct list_head list; -+ void __iomem *base; -+ struct gpio_chip gc; -+ unsigned long rising[(BCM2708_NR_GPIOS + 31) / 32]; -+ unsigned long falling[(BCM2708_NR_GPIOS + 31) / 32]; -+ unsigned long high[(BCM2708_NR_GPIOS + 31) / 32]; -+ unsigned long low[(BCM2708_NR_GPIOS + 31) / 32]; -+}; -+ -+static int bcm2708_set_function(struct gpio_chip *gc, unsigned offset, -+ int function) -+{ -+ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); -+ unsigned long flags; -+ unsigned gpiodir; -+ unsigned gpio_bank = offset / 10; -+ unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3; -+ -+//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set_function %p (%d,%d)\n", gc, offset, function); -+ if (offset >= BCM2708_NR_GPIOS) -+ return -EINVAL; -+ -+ spin_lock_irqsave(&lock, flags); -+ -+ gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank)); -+ gpiodir &= ~(7 << gpio_field_offset); -+ gpiodir |= function << gpio_field_offset; -+ writel(gpiodir, gpio->base + GPIOFSEL(gpio_bank)); -+ spin_unlock_irqrestore(&lock, flags); -+ gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank)); -+ -+ return 0; -+} -+ -+static int bcm2708_gpio_dir_in(struct gpio_chip *gc, unsigned offset) -+{ -+ return bcm2708_set_function(gc, offset, GPIO_FSEL_INPUT); -+} -+ -+static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value); -+static int bcm2708_gpio_dir_out(struct gpio_chip *gc, unsigned offset, -+ int value) -+{ -+ int ret; -+ ret = bcm2708_set_function(gc, offset, GPIO_FSEL_OUTPUT); -+ if (ret >= 0) -+ bcm2708_gpio_set(gc, offset, value); -+ return ret; -+} -+ -+static int bcm2708_gpio_get(struct gpio_chip *gc, unsigned offset) -+{ -+ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); -+ unsigned gpio_bank = offset / 32; -+ unsigned gpio_field_offset = (offset - 32 * gpio_bank); -+ unsigned lev; -+ -+ if (offset >= BCM2708_NR_GPIOS) -+ return 0; -+ lev = readl(gpio->base + GPIOLEV(gpio_bank)); -+//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_get %p (%d)=%d\n", gc, offset, 0x1 & (lev>>gpio_field_offset)); -+ return 0x1 & (lev >> gpio_field_offset); -+} -+ -+static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value) -+{ -+ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); -+ unsigned gpio_bank = offset / 32; -+ unsigned gpio_field_offset = (offset - 32 * gpio_bank); -+//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set %p (%d=%d)\n", gc, offset, value); -+ if (offset >= BCM2708_NR_GPIOS) -+ return; -+ if (value) -+ writel(1 << gpio_field_offset, gpio->base + GPIOSET(gpio_bank)); -+ else -+ writel(1 << gpio_field_offset, gpio->base + GPIOCLR(gpio_bank)); -+} -+ -+/********************** -+ * extension to configure pullups -+ */ -+int bcm2708_gpio_setpull(struct gpio_chip *gc, unsigned offset, -+ bcm2708_gpio_pull_t value) -+{ -+ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); -+ unsigned gpio_bank = offset / 32; -+ unsigned gpio_field_offset = (offset - 32 * gpio_bank); -+ -+ if (offset >= BCM2708_NR_GPIOS) -+ return -EINVAL; -+ -+ switch (value) { -+ case BCM2708_PULL_UP: -+ writel(2, gpio->base + GPIOUD(0)); -+ break; -+ case BCM2708_PULL_DOWN: -+ writel(1, gpio->base + GPIOUD(0)); -+ break; -+ case BCM2708_PULL_OFF: -+ writel(0, gpio->base + GPIOUD(0)); -+ break; -+ } -+ -+ udelay(5); -+ writel(1 << gpio_field_offset, gpio->base + GPIOUDCLK(gpio_bank)); -+ udelay(5); -+ writel(0, gpio->base + GPIOUD(0)); -+ writel(0 << gpio_field_offset, gpio->base + GPIOUDCLK(gpio_bank)); -+ -+ return 0; -+} -+EXPORT_SYMBOL(bcm2708_gpio_setpull); -+ -+/************************************************************************************************************************* -+ * bcm2708 GPIO IRQ -+ */ -+ -+#if BCM_GPIO_USE_IRQ -+ -+static int bcm2708_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) -+{ -+ return gpio_to_irq(gpio); -+} -+ -+static int bcm2708_gpio_irq_set_type(struct irq_data *d, unsigned type) -+{ -+ unsigned irq = d->irq; -+ struct bcm2708_gpio *gpio = irq_get_chip_data(irq); -+ unsigned gn = irq_to_gpio(irq); -+ unsigned gb = gn / 32; -+ unsigned go = gn % 32; -+ -+ gpio->rising[gb] &= ~(1 << go); -+ gpio->falling[gb] &= ~(1 << go); -+ gpio->high[gb] &= ~(1 << go); -+ gpio->low[gb] &= ~(1 << go); -+ -+ if (type & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) -+ return -EINVAL; -+ -+ if (type & IRQ_TYPE_EDGE_RISING) -+ gpio->rising[gb] |= (1 << go); -+ if (type & IRQ_TYPE_EDGE_FALLING) -+ gpio->falling[gb] |= (1 << go); -+ if (type & IRQ_TYPE_LEVEL_HIGH) -+ gpio->high[gb] |= (1 << go); -+ if (type & IRQ_TYPE_LEVEL_LOW) -+ gpio->low[gb] |= (1 << go); -+ return 0; -+} -+ -+static void bcm2708_gpio_irq_mask(struct irq_data *d) -+{ -+ unsigned irq = d->irq; -+ struct bcm2708_gpio *gpio = irq_get_chip_data(irq); -+ unsigned gn = irq_to_gpio(irq); -+ unsigned gb = gn / 32; -+ unsigned long rising = readl(gpio->base + GPIOREN(gb)); -+ unsigned long falling = readl(gpio->base + GPIOFEN(gb)); -+ unsigned long high = readl(gpio->base + GPIOHEN(gb)); -+ unsigned long low = readl(gpio->base + GPIOLEN(gb)); -+ -+ gn = gn % 32; -+ -+ writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb)); -+ writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb)); -+ writel(high & ~(1 << gn), gpio->base + GPIOHEN(gb)); -+ writel(low & ~(1 << gn), gpio->base + GPIOLEN(gb)); -+} -+ -+static void bcm2708_gpio_irq_unmask(struct irq_data *d) -+{ -+ unsigned irq = d->irq; -+ struct bcm2708_gpio *gpio = irq_get_chip_data(irq); -+ unsigned gn = irq_to_gpio(irq); -+ unsigned gb = gn / 32; -+ unsigned go = gn % 32; -+ unsigned long rising = readl(gpio->base + GPIOREN(gb)); -+ unsigned long falling = readl(gpio->base + GPIOFEN(gb)); -+ unsigned long high = readl(gpio->base + GPIOHEN(gb)); -+ unsigned long low = readl(gpio->base + GPIOLEN(gb)); -+ -+ if (gpio->rising[gb] & (1 << go)) { -+ writel(rising | (1 << go), gpio->base + GPIOREN(gb)); -+ } else { -+ writel(rising & ~(1 << go), gpio->base + GPIOREN(gb)); -+ } -+ -+ if (gpio->falling[gb] & (1 << go)) { -+ writel(falling | (1 << go), gpio->base + GPIOFEN(gb)); -+ } else { -+ writel(falling & ~(1 << go), gpio->base + GPIOFEN(gb)); -+ } -+ -+ if (gpio->high[gb] & (1 << go)) { -+ writel(high | (1 << go), gpio->base + GPIOHEN(gb)); -+ } else { -+ writel(high & ~(1 << go), gpio->base + GPIOHEN(gb)); -+ } -+ -+ if (gpio->low[gb] & (1 << go)) { -+ writel(low | (1 << go), gpio->base + GPIOLEN(gb)); -+ } else { -+ writel(low & ~(1 << go), gpio->base + GPIOLEN(gb)); -+ } -+} -+ -+static struct irq_chip bcm2708_irqchip = { -+ .name = "GPIO", -+ .irq_enable = bcm2708_gpio_irq_unmask, -+ .irq_disable = bcm2708_gpio_irq_mask, -+ .irq_unmask = bcm2708_gpio_irq_unmask, -+ .irq_mask = bcm2708_gpio_irq_mask, -+ .irq_set_type = bcm2708_gpio_irq_set_type, -+}; -+ -+static irqreturn_t bcm2708_gpio_interrupt(int irq, void *dev_id) -+{ -+ unsigned long edsr; -+ unsigned bank; -+ int i; -+ unsigned gpio; -+ unsigned level_bits; -+ struct bcm2708_gpio *gpio_data = dev_id; -+ -+ for (bank = 0; bank < GPIO_BANKS; bank++) { -+ edsr = readl(__io_address(GPIO_BASE) + GPIOEDS(bank)); -+ level_bits = gpio_data->high[bank] | gpio_data->low[bank]; -+ -+ for_each_set_bit(i, &edsr, 32) { -+ gpio = i + bank * 32; -+ /* ack edge triggered IRQs immediately */ -+ if (!(level_bits & (1<gc.to_irq = bcm2708_gpio_to_irq; -+ -+ for (irq = GPIO_IRQ_START; irq < (GPIO_IRQ_START + GPIO_IRQS); irq++) { -+ irq_set_chip_data(irq, ucb); -+ irq_set_chip_and_handler(irq, &bcm2708_irqchip, -+ handle_simple_irq); -+ set_irq_flags(irq, IRQF_VALID); -+ } -+ -+ bcm2708_gpio_irq.dev_id = ucb; -+ setup_irq(IRQ_GPIO3, &bcm2708_gpio_irq); -+} -+ -+#else -+ -+static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb) -+{ -+} -+ -+#endif /* #if BCM_GPIO_USE_IRQ ***************************************************************************************************************** */ -+ -+static int bcm2708_gpio_probe(struct platform_device *dev) -+{ -+ struct bcm2708_gpio *ucb; -+ struct resource *res; -+ int bank; -+ int err = 0; -+ -+ printk(KERN_INFO DRIVER_NAME ": bcm2708_gpio_probe %p\n", dev); -+ -+ ucb = kzalloc(sizeof(*ucb), GFP_KERNEL); -+ if (NULL == ucb) { -+ printk(KERN_ERR DRIVER_NAME ": failed to allocate " -+ "mailbox memory\n"); -+ err = -ENOMEM; -+ goto err; -+ } -+ -+ res = platform_get_resource(dev, IORESOURCE_MEM, 0); -+ -+ platform_set_drvdata(dev, ucb); -+ ucb->base = __io_address(GPIO_BASE); -+ -+ ucb->gc.label = "bcm2708_gpio"; -+ ucb->gc.base = 0; -+ ucb->gc.ngpio = BCM2708_NR_GPIOS; -+ ucb->gc.owner = THIS_MODULE; -+ -+ ucb->gc.direction_input = bcm2708_gpio_dir_in; -+ ucb->gc.direction_output = bcm2708_gpio_dir_out; -+ ucb->gc.get = bcm2708_gpio_get; -+ ucb->gc.set = bcm2708_gpio_set; -+ ucb->gc.can_sleep = 0; -+ -+ for (bank = 0; bank < GPIO_BANKS; bank++) { -+ writel(0, ucb->base + GPIOREN(bank)); -+ writel(0, ucb->base + GPIOFEN(bank)); -+ writel(0, ucb->base + GPIOHEN(bank)); -+ writel(0, ucb->base + GPIOLEN(bank)); -+ writel(0, ucb->base + GPIOAREN(bank)); -+ writel(0, ucb->base + GPIOAFEN(bank)); -+ writel(~0, ucb->base + GPIOEDS(bank)); -+ } -+ -+ bcm2708_gpio_irq_init(ucb); -+ -+ err = gpiochip_add(&ucb->gc); -+ -+err: -+ return err; -+ -+} -+ -+static int bcm2708_gpio_remove(struct platform_device *dev) -+{ -+ int err = 0; -+ struct bcm2708_gpio *ucb = platform_get_drvdata(dev); -+ -+ printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_remove %p\n", dev); -+ -+ gpiochip_remove(&ucb->gc); -+ -+ platform_set_drvdata(dev, NULL); -+ kfree(ucb); -+ -+ return err; -+} -+ -+static struct platform_driver bcm2708_gpio_driver = { -+ .probe = bcm2708_gpio_probe, -+ .remove = bcm2708_gpio_remove, -+ .driver = { -+ .name = "bcm2708_gpio"}, -+}; -+ -+static int __init bcm2708_gpio_init(void) -+{ -+ return platform_driver_register(&bcm2708_gpio_driver); -+} -+ -+static void __exit bcm2708_gpio_exit(void) -+{ -+ platform_driver_unregister(&bcm2708_gpio_driver); -+} -+ -+module_init(bcm2708_gpio_init); -+module_exit(bcm2708_gpio_exit); -+ -+MODULE_DESCRIPTION("Broadcom BCM2708 GPIO driver"); -+MODULE_LICENSE("GPL"); -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/bcm2709.c linux-rpi/arch/arm/mach-bcm2709/bcm2709.c ---- linux-4.1.13.orig/arch/arm/mach-bcm2709/bcm2709.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2709/bcm2709.c 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,1332 @@ -+/* -+ * linux/arch/arm/mach-bcm2709/bcm2709.c -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include -+ -+#include "bcm2709.h" -+#include "armctrl.h" -+ -+#ifdef CONFIG_BCM_VC_CMA -+#include -+#endif -+ -+//#define SYSTEM_TIMER -+ -+/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to -+ * give us IO access only to 64Mbytes of physical memory (26 bits). We could -+ * represent this window by setting our dmamasks to 26 bits but, in fact -+ * we're not going to use addresses outside this range (they're not in real -+ * memory) so we don't bother. -+ * -+ * In the future we might include code to use this IOMMU to remap other -+ * physical addresses onto VideoCore memory then the use of 32-bits would be -+ * more legitimate. -+ */ -+#define DMA_MASK_BITS_COMMON 32 -+ -+// use GPIO 4 for the one-wire GPIO pin, if enabled -+#define W1_GPIO 4 -+// ensure one-wire GPIO pullup is disabled by default -+#define W1_PULLUP -1 -+ -+/* command line parameters */ -+static unsigned boardrev, serial; -+static unsigned uart_clock = UART0_CLOCK; -+static unsigned disk_led_gpio = 16; -+static unsigned disk_led_active_low = 1; -+static unsigned reboot_part = 0; -+static unsigned w1_gpio_pin = W1_GPIO; -+static unsigned w1_gpio_pullup = W1_PULLUP; -+static bool vc_i2c_override = false; -+static int pps_gpio_pin = -1; -+unsigned force_core; -+ -+static unsigned use_dt = 0; -+ -+static void __init bcm2709_init_led(void); -+ -+void __init bcm2709_init_irq(void) -+{ -+ armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0); -+} -+ -+static struct map_desc bcm2709_io_desc[] __initdata = { -+ { -+ .virtual = IO_ADDRESS(ARMCTRL_BASE), -+ .pfn = __phys_to_pfn(ARMCTRL_BASE), -+ .length = SZ_4K, -+ .type = MT_DEVICE}, -+ { -+ .virtual = IO_ADDRESS(UART0_BASE), -+ .pfn = __phys_to_pfn(UART0_BASE), -+ .length = SZ_4K, -+ .type = MT_DEVICE}, -+ { -+ .virtual = IO_ADDRESS(UART1_BASE), -+ .pfn = __phys_to_pfn(UART1_BASE), -+ .length = SZ_4K, -+ .type = MT_DEVICE}, -+ { -+ .virtual = IO_ADDRESS(DMA_BASE), -+ .pfn = __phys_to_pfn(DMA_BASE), -+ .length = SZ_4K, -+ .type = MT_DEVICE}, -+ { -+ .virtual = IO_ADDRESS(MCORE_BASE), -+ .pfn = __phys_to_pfn(MCORE_BASE), -+ .length = SZ_4K, -+ .type = MT_DEVICE}, -+ { -+ .virtual = IO_ADDRESS(ST_BASE), -+ .pfn = __phys_to_pfn(ST_BASE), -+ .length = SZ_4K, -+ .type = MT_DEVICE}, -+ { -+ .virtual = IO_ADDRESS(USB_BASE), -+ .pfn = __phys_to_pfn(USB_BASE), -+ .length = SZ_128K, -+ .type = MT_DEVICE}, -+ { -+ .virtual = IO_ADDRESS(PM_BASE), -+ .pfn = __phys_to_pfn(PM_BASE), -+ .length = SZ_4K, -+ .type = MT_DEVICE}, -+ { -+ .virtual = IO_ADDRESS(GPIO_BASE), -+ .pfn = __phys_to_pfn(GPIO_BASE), -+ .length = SZ_4K, -+ .type = MT_DEVICE}, -+ { -+ .virtual = IO_ADDRESS(ARM_LOCAL_BASE), -+ .pfn = __phys_to_pfn(ARM_LOCAL_BASE), -+ .length = SZ_4K, -+ .type = MT_DEVICE}, -+}; -+ -+void __init bcm2709_map_io(void) -+{ -+ iotable_init(bcm2709_io_desc, ARRAY_SIZE(bcm2709_io_desc)); -+} -+ -+#ifdef SYSTEM_TIMER -+ -+/* The STC is a free running counter that increments at the rate of 1MHz */ -+#define STC_FREQ_HZ 1000000 -+ -+static inline uint32_t timer_read(void) -+{ -+ /* STC: a free running counter that increments at the rate of 1MHz */ -+ return readl(__io_address(ST_BASE + 0x04)); -+} -+ -+static unsigned long bcm2709_read_current_timer(void) -+{ -+ return timer_read(); -+} -+ -+static u64 notrace bcm2709_read_sched_clock(void) -+{ -+ return timer_read(); -+} -+ -+static cycle_t clksrc_read(struct clocksource *cs) -+{ -+ return timer_read(); -+} -+ -+static struct clocksource clocksource_stc = { -+ .name = "stc", -+ .rating = 300, -+ .read = clksrc_read, -+ .mask = CLOCKSOURCE_MASK(32), -+ .flags = CLOCK_SOURCE_IS_CONTINUOUS, -+}; -+ -+unsigned long frc_clock_ticks32(void) -+{ -+ return timer_read(); -+} -+ -+static void __init bcm2709_clocksource_init(void) -+{ -+ if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) { -+ printk(KERN_ERR "timer: failed to initialize clock " -+ "source %s\n", clocksource_stc.name); -+ } -+} -+#endif -+ -+struct clk __init *bcm2709_clk_register(const char *name, unsigned long fixed_rate) -+{ -+ struct clk *clk; -+ -+ clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, -+ fixed_rate); -+ if (IS_ERR(clk)) -+ pr_err("%s not registered\n", name); -+ -+ return clk; -+} -+ -+void __init bcm2709_register_clkdev(struct clk *clk, const char *name) -+{ -+ int ret; -+ -+ ret = clk_register_clkdev(clk, NULL, name); -+ if (ret) -+ pr_err("%s alias not registered\n", name); -+} -+ -+void __init bcm2709_init_clocks(void) -+{ -+ struct clk *clk; -+ -+ clk = bcm2709_clk_register("uart0_clk", uart_clock); -+ bcm2709_register_clkdev(clk, "dev:f1"); -+ -+ clk = bcm2709_clk_register("sdhost_clk", 250000000); -+ bcm2709_register_clkdev(clk, "mmc-bcm2835.0"); -+ bcm2709_register_clkdev(clk, "bcm2708_spi.0"); -+ bcm2709_register_clkdev(clk, "bcm2708_i2c.0"); -+ bcm2709_register_clkdev(clk, "bcm2708_i2c.1"); -+} -+ -+#define UART0_IRQ { IRQ_UART, 0 /*NO_IRQ*/ } -+#define UART0_DMA { 15, 14 } -+ -+AMBA_DEVICE(uart0, "dev:f1", UART0, NULL); -+ -+static struct amba_device *amba_devs[] __initdata = { -+ &uart0_device, -+}; -+ -+static struct resource bcm2708_dmaengine_resources[] = { -+ { -+ .start = DMA_BASE, -+ .end = DMA_BASE + SZ_4K - 1, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .start = IRQ_DMA0, -+ .end = IRQ_DMA0, -+ .flags = IORESOURCE_IRQ, -+ }, { -+ .start = IRQ_DMA1, -+ .end = IRQ_DMA1, -+ .flags = IORESOURCE_IRQ, -+ }, { -+ .start = IRQ_DMA2, -+ .end = IRQ_DMA2, -+ .flags = IORESOURCE_IRQ, -+ }, { -+ .start = IRQ_DMA3, -+ .end = IRQ_DMA3, -+ .flags = IORESOURCE_IRQ, -+ }, { -+ .start = IRQ_DMA4, -+ .end = IRQ_DMA4, -+ .flags = IORESOURCE_IRQ, -+ }, { -+ .start = IRQ_DMA5, -+ .end = IRQ_DMA5, -+ .flags = IORESOURCE_IRQ, -+ }, { -+ .start = IRQ_DMA6, -+ .end = IRQ_DMA6, -+ .flags = IORESOURCE_IRQ, -+ }, { -+ .start = IRQ_DMA7, -+ .end = IRQ_DMA7, -+ .flags = IORESOURCE_IRQ, -+ }, { -+ .start = IRQ_DMA8, -+ .end = IRQ_DMA8, -+ .flags = IORESOURCE_IRQ, -+ }, { -+ .start = IRQ_DMA9, -+ .end = IRQ_DMA9, -+ .flags = IORESOURCE_IRQ, -+ }, { -+ .start = IRQ_DMA10, -+ .end = IRQ_DMA10, -+ .flags = IORESOURCE_IRQ, -+ }, { -+ .start = IRQ_DMA11, -+ .end = IRQ_DMA11, -+ .flags = IORESOURCE_IRQ, -+ }, { -+ .start = IRQ_DMA12, -+ .end = IRQ_DMA12, -+ .flags = IORESOURCE_IRQ, -+ } -+}; -+ -+static struct platform_device bcm2708_dmaengine_device = { -+ .name = "bcm2708-dmaengine", -+ .id = -1, -+ .resource = bcm2708_dmaengine_resources, -+ .num_resources = ARRAY_SIZE(bcm2708_dmaengine_resources), -+}; -+ -+#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE) -+static struct w1_gpio_platform_data w1_gpio_pdata = { -+ .pin = W1_GPIO, -+ .ext_pullup_enable_pin = W1_PULLUP, -+ .is_open_drain = 0, -+}; -+ -+static struct platform_device w1_device = { -+ .name = "w1-gpio", -+ .id = -1, -+ .dev.platform_data = &w1_gpio_pdata, -+}; -+#endif -+ -+static struct pps_gpio_platform_data pps_gpio_info = { -+ .assert_falling_edge = false, -+ .capture_clear = false, -+ .gpio_pin = -1, -+ .gpio_label = "PPS", -+}; -+ -+static struct platform_device pps_gpio_device = { -+ .name = "pps-gpio", -+ .id = PLATFORM_DEVID_NONE, -+ .dev.platform_data = &pps_gpio_info, -+}; -+ -+static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); -+ -+static struct platform_device bcm2708_fb_device = { -+ .name = "bcm2708_fb", -+ .id = -1, /* only one bcm2708_fb */ -+ .resource = NULL, -+ .num_resources = 0, -+ .dev = { -+ .dma_mask = &fb_dmamask, -+ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), -+ }, -+}; -+ -+static struct resource bcm2708_usb_resources[] = { -+ [0] = { -+ .start = USB_BASE, -+ .end = USB_BASE + SZ_128K - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = MPHI_BASE, -+ .end = MPHI_BASE + SZ_4K - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ [2] = { -+ .start = IRQ_HOSTPORT, -+ .end = IRQ_HOSTPORT, -+ .flags = IORESOURCE_IRQ, -+ }, -+ [3] = { -+ .start = IRQ_USB, -+ .end = IRQ_USB, -+ .flags = IORESOURCE_IRQ, -+ }, -+ [4] = { -+ .start = ARM_LOCAL_BASE, -+ .end = ARM_LOCAL_BASE + SZ_4K - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ [5] = { -+ .start = IRQ_ARM_LOCAL_MAILBOX1, -+ .end = IRQ_ARM_LOCAL_MAILBOX1, -+ .flags = IORESOURCE_IRQ -+ }, -+}; -+ -+ -+static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); -+ -+static struct platform_device bcm2708_usb_device = { -+ .name = "bcm2708_usb", -+ .id = -1, /* only one bcm2708_usb */ -+ .resource = bcm2708_usb_resources, -+ .num_resources = ARRAY_SIZE(bcm2708_usb_resources), -+ .dev = { -+ .dma_mask = &usb_dmamask, -+ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), -+ }, -+}; -+ -+static struct resource bcm2708_vcio_resources[] = { -+ { -+ .start = ARMCTRL_0_MAIL0_BASE, -+ .end = ARMCTRL_0_MAIL0_BASE + SZ_64 - 1, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .start = IRQ_ARM_MAILBOX, -+ .end = IRQ_ARM_MAILBOX, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static u64 vcio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); -+ -+static struct platform_device bcm2708_vcio_device = { -+ .name = "bcm2835-mbox", -+ .id = -1, /* only one VideoCore I/O area */ -+ .resource = bcm2708_vcio_resources, -+ .num_resources = ARRAY_SIZE(bcm2708_vcio_resources), -+ .dev = { -+ .dma_mask = &vcio_dmamask, -+ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), -+ }, -+}; -+ -+static u64 rpifw_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); -+ -+static struct platform_device bcm2708_rpifw_device = { -+ .name = "raspberrypi-firmware", -+ .dev = { -+ .dma_mask = &rpifw_dmamask, -+ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), -+ }, -+}; -+ -+static struct resource bcm2708_vchiq_resources[] = { -+ { -+ .start = ARMCTRL_0_BELL_BASE, -+ .end = ARMCTRL_0_BELL_BASE + 16, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .start = IRQ_ARM_DOORBELL_0, -+ .end = IRQ_ARM_DOORBELL_0, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static u64 vchiq_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); -+ -+static struct platform_device bcm2708_vchiq_device = { -+ .name = "bcm2835_vchiq", -+ .id = -1, -+ .resource = bcm2708_vchiq_resources, -+ .num_resources = ARRAY_SIZE(bcm2708_vchiq_resources), -+ .dev = { -+ .dma_mask = &vchiq_dmamask, -+ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), -+ }, -+}; -+ -+#ifdef CONFIG_BCM2708_GPIO -+#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio" -+ -+static struct resource bcm2708_gpio_resources[] = { -+ [0] = { /* general purpose I/O */ -+ .start = GPIO_BASE, -+ .end = GPIO_BASE + SZ_4K - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static u64 gpio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); -+ -+static struct platform_device bcm2708_gpio_device = { -+ .name = BCM_GPIO_DRIVER_NAME, -+ .id = -1, /* only one VideoCore I/O area */ -+ .resource = bcm2708_gpio_resources, -+ .num_resources = ARRAY_SIZE(bcm2708_gpio_resources), -+ .dev = { -+ .dma_mask = &gpio_dmamask, -+ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), -+ }, -+}; -+#endif -+ -+#ifdef CONFIG_MMC_BCM2835 /* Arasan emmc SD (new) */ -+static struct resource bcm2835_emmc_resources[] = { -+ [0] = { -+ .start = EMMC_BASE, -+ .end = EMMC_BASE + SZ_256 - 1, /* we only need this area */ -+ /* the memory map actually makes SZ_4K available */ -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = IRQ_ARASANSDIO, -+ .end = IRQ_ARASANSDIO, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static u64 bcm2835_emmc_dmamask = 0xffffffffUL; -+ -+struct platform_device bcm2835_emmc_device = { -+ .name = "mmc-bcm2835", -+ .id = 0, -+ .num_resources = ARRAY_SIZE(bcm2835_emmc_resources), -+ .resource = bcm2835_emmc_resources, -+ .dev = { -+ .dma_mask = &bcm2835_emmc_dmamask, -+ .coherent_dma_mask = 0xffffffffUL}, -+}; -+#endif /* CONFIG_MMC_BCM2835 */ -+ -+static struct platform_device bcm2708_alsa_devices[] = { -+ [0] = { -+ .name = "bcm2835_AUD0", -+ .id = 0, /* first audio device */ -+ .resource = 0, -+ .num_resources = 0, -+ }, -+ [1] = { -+ .name = "bcm2835_AUD1", -+ .id = 1, /* second audio device */ -+ .resource = 0, -+ .num_resources = 0, -+ }, -+ [2] = { -+ .name = "bcm2835_AUD2", -+ .id = 2, /* third audio device */ -+ .resource = 0, -+ .num_resources = 0, -+ }, -+ [3] = { -+ .name = "bcm2835_AUD3", -+ .id = 3, /* forth audio device */ -+ .resource = 0, -+ .num_resources = 0, -+ }, -+ [4] = { -+ .name = "bcm2835_AUD4", -+ .id = 4, /* fifth audio device */ -+ .resource = 0, -+ .num_resources = 0, -+ }, -+ [5] = { -+ .name = "bcm2835_AUD5", -+ .id = 5, /* sixth audio device */ -+ .resource = 0, -+ .num_resources = 0, -+ }, -+ [6] = { -+ .name = "bcm2835_AUD6", -+ .id = 6, /* seventh audio device */ -+ .resource = 0, -+ .num_resources = 0, -+ }, -+ [7] = { -+ .name = "bcm2835_AUD7", -+ .id = 7, /* eighth audio device */ -+ .resource = 0, -+ .num_resources = 0, -+ }, -+}; -+ -+static struct resource bcm2708_spi_resources[] = { -+ { -+ .start = SPI0_BASE, -+ .end = SPI0_BASE + SZ_256 - 1, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .start = IRQ_SPI, -+ .end = IRQ_SPI, -+ .flags = IORESOURCE_IRQ, -+ } -+}; -+ -+ -+static u64 bcm2708_spi_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); -+static struct platform_device bcm2708_spi_device = { -+ .name = "bcm2708_spi", -+ .id = 0, -+ .num_resources = ARRAY_SIZE(bcm2708_spi_resources), -+ .resource = bcm2708_spi_resources, -+ .dev = { -+ .dma_mask = &bcm2708_spi_dmamask, -+ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON)}, -+}; -+ -+#ifdef CONFIG_BCM2708_SPIDEV -+static struct spi_board_info bcm2708_spi_devices[] = { -+#ifdef CONFIG_SPI_SPIDEV -+ { -+ .modalias = "spidev", -+ .max_speed_hz = 500000, -+ .bus_num = 0, -+ .chip_select = 0, -+ .mode = SPI_MODE_0, -+ }, { -+ .modalias = "spidev", -+ .max_speed_hz = 500000, -+ .bus_num = 0, -+ .chip_select = 1, -+ .mode = SPI_MODE_0, -+ } -+#endif -+}; -+#endif -+ -+static struct resource bcm2708_bsc0_resources[] = { -+ { -+ .start = BSC0_BASE, -+ .end = BSC0_BASE + SZ_256 - 1, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .start = INTERRUPT_I2C, -+ .end = INTERRUPT_I2C, -+ .flags = IORESOURCE_IRQ, -+ } -+}; -+ -+static struct platform_device bcm2708_bsc0_device = { -+ .name = "bcm2708_i2c", -+ .id = 0, -+ .num_resources = ARRAY_SIZE(bcm2708_bsc0_resources), -+ .resource = bcm2708_bsc0_resources, -+}; -+ -+ -+static struct resource bcm2708_bsc1_resources[] = { -+ { -+ .start = BSC1_BASE, -+ .end = BSC1_BASE + SZ_256 - 1, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .start = INTERRUPT_I2C, -+ .end = INTERRUPT_I2C, -+ .flags = IORESOURCE_IRQ, -+ } -+}; -+ -+static struct platform_device bcm2708_bsc1_device = { -+ .name = "bcm2708_i2c", -+ .id = 1, -+ .num_resources = ARRAY_SIZE(bcm2708_bsc1_resources), -+ .resource = bcm2708_bsc1_resources, -+}; -+ -+static struct platform_device bcm2835_thermal_device = { -+ .name = "bcm2835_thermal", -+}; -+ -+#if defined(CONFIG_SND_BCM2708_SOC_I2S) || defined(CONFIG_SND_BCM2708_SOC_I2S_MODULE) -+static struct resource bcm2708_i2s_resources[] = { -+ { -+ .start = I2S_BASE, -+ .end = I2S_BASE + 0x20, -+ .flags = IORESOURCE_MEM, -+ }, -+ { -+ .start = PCM_CLOCK_BASE, -+ .end = PCM_CLOCK_BASE + 0x02, -+ .flags = IORESOURCE_MEM, -+ } -+}; -+ -+static struct platform_device bcm2708_i2s_device = { -+ .name = "bcm2708-i2s", -+ .id = 0, -+ .num_resources = ARRAY_SIZE(bcm2708_i2s_resources), -+ .resource = bcm2708_i2s_resources, -+}; -+#endif -+ -+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC_MODULE) -+static struct platform_device snd_hifiberry_dac_device = { -+ .name = "snd-hifiberry-dac", -+ .id = 0, -+ .num_resources = 0, -+}; -+ -+static struct platform_device snd_pcm5102a_codec_device = { -+ .name = "pcm5102a-codec", -+ .id = -1, -+ .num_resources = 0, -+}; -+#endif -+ -+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS_MODULE) -+static struct platform_device snd_rpi_hifiberry_dacplus_device = { -+ .name = "snd-rpi-hifiberry-dacplus", -+ .id = 0, -+ .num_resources = 0, -+}; -+ -+static struct i2c_board_info __initdata snd_pcm512x_hbdacplus_i2c_devices[] = { -+ { -+ I2C_BOARD_INFO("pcm5122", 0x4d) -+ }, -+}; -+#endif -+ -+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI_MODULE) -+static struct platform_device snd_hifiberry_digi_device = { -+ .name = "snd-hifiberry-digi", -+ .id = 0, -+ .num_resources = 0, -+}; -+ -+static struct i2c_board_info __initdata snd_wm8804_i2c_devices[] = { -+ { -+ I2C_BOARD_INFO("wm8804", 0x3b) -+ }, -+}; -+ -+#endif -+ -+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP_MODULE) -+static struct platform_device snd_hifiberry_amp_device = { -+ .name = "snd-hifiberry-amp", -+ .id = 0, -+ .num_resources = 0, -+}; -+ -+static struct i2c_board_info __initdata snd_tas5713_i2c_devices[] = { -+ { -+ I2C_BOARD_INFO("tas5713", 0x1b) -+ }, -+}; -+#endif -+ -+#if defined(CONFIG_SND_BCM2708_SOC_RPI_DAC) || defined(CONFIG_SND_BCM2708_SOC_RPI_DAC_MODULE) -+static struct platform_device snd_rpi_dac_device = { -+ .name = "snd-rpi-dac", -+ .id = 0, -+ .num_resources = 0, -+}; -+ -+static struct platform_device snd_pcm1794a_codec_device = { -+ .name = "pcm1794a-codec", -+ .id = -1, -+ .num_resources = 0, -+}; -+#endif -+ -+ -+#if defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) || defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC_MODULE) -+static struct platform_device snd_rpi_iqaudio_dac_device = { -+ .name = "snd-rpi-iqaudio-dac", -+ .id = 0, -+ .num_resources = 0, -+}; -+ -+// Use the actual device name rather than generic driver name -+static struct i2c_board_info __initdata snd_pcm512x_i2c_devices[] = { -+ { -+ I2C_BOARD_INFO("pcm5122", 0x4c) -+ }, -+}; -+#endif -+ -+int __init bcm_register_device(struct platform_device *pdev) -+{ -+ int ret; -+ -+ ret = platform_device_register(pdev); -+ if (ret) -+ pr_debug("Unable to register platform device '%s': %d\n", -+ pdev->name, ret); -+ -+ return ret; -+} -+ -+/* -+ * Use these macros for platform and i2c devices that are present in the -+ * Device Tree. This way the devices are only added on non-DT systems. -+ */ -+#define bcm_register_device_dt(pdev) \ -+ if (!use_dt) bcm_register_device(pdev) -+ -+#define i2c_register_board_info_dt(busnum, info, n) \ -+ if (!use_dt) i2c_register_board_info(busnum, info, n) -+ -+int calc_rsts(int partition) -+{ -+ return PM_PASSWORD | -+ ((partition & (1 << 0)) << 0) | -+ ((partition & (1 << 1)) << 1) | -+ ((partition & (1 << 2)) << 2) | -+ ((partition & (1 << 3)) << 3) | -+ ((partition & (1 << 4)) << 4) | -+ ((partition & (1 << 5)) << 5); -+} -+ -+static void bcm2709_restart(enum reboot_mode mode, const char *cmd) -+{ -+ extern char bcm2708_reboot_mode; -+ uint32_t pm_rstc, pm_wdog; -+ uint32_t timeout = 10; -+ uint32_t pm_rsts = 0; -+ -+ if(bcm2708_reboot_mode == 'q') -+ { -+ // NOOBS < 1.3 booting with reboot=q -+ pm_rsts = readl(__io_address(PM_RSTS)); -+ pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET; -+ } -+ else if(bcm2708_reboot_mode == 'p') -+ { -+ // NOOBS < 1.3 halting -+ pm_rsts = readl(__io_address(PM_RSTS)); -+ pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRH_SET; -+ } -+ else -+ { -+ pm_rsts = calc_rsts(reboot_part); -+ } -+ -+ writel(pm_rsts, __io_address(PM_RSTS)); -+ -+ /* Setup watchdog for reset */ -+ pm_rstc = readl(__io_address(PM_RSTC)); -+ -+ pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0) -+ pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET; -+ -+ writel(pm_wdog, __io_address(PM_WDOG)); -+ writel(pm_rstc, __io_address(PM_RSTC)); -+} -+ -+/* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */ -+static void bcm2709_power_off(void) -+{ -+ extern char bcm2708_reboot_mode; -+ if(bcm2708_reboot_mode == 'q') -+ { -+ // NOOBS < v1.3 -+ bcm2709_restart('p', ""); -+ } -+ else -+ { -+ /* partition 63 is special code for HALT the bootloader knows not to boot*/ -+ reboot_part = 63; -+ /* continue with normal reset mechanism */ -+ bcm2709_restart(0, ""); -+ } -+} -+ -+static void __init bcm2709_init_uart1(void) -+{ -+ struct device_node *np; -+ -+ np = of_find_compatible_node(NULL, NULL, "brcm,bcm2835-aux-uart"); -+ if (of_device_is_available(np)) { -+ pr_info("bcm2709: Mini UART enabled\n"); -+ writel(1, __io_address(UART1_BASE + 0x4)); -+ } -+} -+ -+#ifdef CONFIG_OF -+static void __init bcm2709_dt_init(void) -+{ -+ int ret; -+ -+ of_clk_init(NULL); -+ ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); -+ if (ret) { -+ pr_err("of_platform_populate failed: %d\n", ret); -+ /* Proceed as if CONFIG_OF was not defined */ -+ } else { -+ use_dt = 1; -+ } -+} -+#else -+static void __init bcm2709_dt_init(void) { } -+#endif /* CONFIG_OF */ -+ -+void __init bcm2709_init(void) -+{ -+ int i; -+ -+#if defined(CONFIG_BCM_VC_CMA) -+ vc_cma_early_init(); -+#endif -+ printk("bcm2709.uart_clock = %d\n", uart_clock); -+ pm_power_off = bcm2709_power_off; -+ -+ bcm2709_init_clocks(); -+ bcm2709_dt_init(); -+ -+ bcm_register_device_dt(&bcm2708_dmaengine_device); -+ bcm_register_device_dt(&bcm2708_vcio_device); -+ bcm_register_device_dt(&bcm2708_rpifw_device); -+ bcm_register_device_dt(&bcm2708_vchiq_device); -+#ifdef CONFIG_BCM2708_GPIO -+ bcm_register_device_dt(&bcm2708_gpio_device); -+#endif -+ -+#if defined(CONFIG_PPS_CLIENT_GPIO) || defined(CONFIG_PPS_CLIENT_GPIO_MODULE) -+ if (!use_dt && (pps_gpio_pin >= 0)) { -+ pr_info("bcm2709: GPIO %d setup as pps-gpio device\n", pps_gpio_pin); -+ pps_gpio_info.gpio_pin = pps_gpio_pin; -+ pps_gpio_device.id = pps_gpio_pin; -+ bcm_register_device(&pps_gpio_device); -+ } -+#endif -+ -+#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE) -+ w1_gpio_pdata.pin = w1_gpio_pin; -+ w1_gpio_pdata.ext_pullup_enable_pin = w1_gpio_pullup; -+ bcm_register_device_dt(&w1_device); -+#endif -+ bcm_register_device_dt(&bcm2708_fb_device); -+ bcm_register_device_dt(&bcm2708_usb_device); -+ -+#ifdef CONFIG_MMC_BCM2835 -+ bcm_register_device_dt(&bcm2835_emmc_device); -+#endif -+ bcm2709_init_led(); -+ bcm2709_init_uart1(); -+ -+ /* Only create the platform devices for the ALSA driver in the -+ absence of an enabled "audio" DT node */ -+ if (!use_dt || -+ !of_device_is_available(of_find_node_by_path("/audio"))) { -+ for (i = 0; i < ARRAY_SIZE(bcm2708_alsa_devices); i++) -+ bcm_register_device(&bcm2708_alsa_devices[i]); -+ } -+ -+ bcm_register_device_dt(&bcm2708_spi_device); -+ -+ if (vc_i2c_override) { -+ bcm_register_device_dt(&bcm2708_bsc0_device); -+ bcm_register_device_dt(&bcm2708_bsc1_device); -+ } else if ((boardrev & 0xffffff) == 0x2 || (boardrev & 0xffffff) == 0x3) { -+ bcm_register_device_dt(&bcm2708_bsc0_device); -+ } else { -+ bcm_register_device_dt(&bcm2708_bsc1_device); -+ } -+ -+ bcm_register_device_dt(&bcm2835_thermal_device); -+ -+#if defined(CONFIG_SND_BCM2708_SOC_I2S) || defined(CONFIG_SND_BCM2708_SOC_I2S_MODULE) -+ bcm_register_device_dt(&bcm2708_i2s_device); -+#endif -+ -+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC_MODULE) -+ bcm_register_device_dt(&snd_hifiberry_dac_device); -+ bcm_register_device_dt(&snd_pcm5102a_codec_device); -+#endif -+ -+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS_MODULE) -+ bcm_register_device_dt(&snd_rpi_hifiberry_dacplus_device); -+ i2c_register_board_info_dt(1, snd_pcm512x_hbdacplus_i2c_devices, ARRAY_SIZE(snd_pcm512x_hbdacplus_i2c_devices)); -+#endif -+ -+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI_MODULE) -+ bcm_register_device_dt(&snd_hifiberry_digi_device); -+ i2c_register_board_info_dt(1, snd_wm8804_i2c_devices, ARRAY_SIZE(snd_wm8804_i2c_devices)); -+#endif -+ -+#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP_MODULE) -+ bcm_register_device_dt(&snd_hifiberry_amp_device); -+ i2c_register_board_info_dt(1, snd_tas5713_i2c_devices, ARRAY_SIZE(snd_tas5713_i2c_devices)); -+#endif -+ -+#if defined(CONFIG_SND_BCM2708_SOC_RPI_DAC) || defined(CONFIG_SND_BCM2708_SOC_RPI_DAC_MODULE) -+ bcm_register_device_dt(&snd_rpi_dac_device); -+ bcm_register_device_dt(&snd_pcm1794a_codec_device); -+#endif -+ -+#if defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) || defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC_MODULE) -+ bcm_register_device_dt(&snd_rpi_iqaudio_dac_device); -+ i2c_register_board_info_dt(1, snd_pcm512x_i2c_devices, ARRAY_SIZE(snd_pcm512x_i2c_devices)); -+#endif -+ -+ if (!use_dt) { -+ for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { -+ struct amba_device *d = amba_devs[i]; -+ amba_device_register(d, &iomem_resource); -+ } -+ } -+ system_rev = boardrev; -+ system_serial_low = serial; -+ -+#ifdef CONFIG_BCM2708_SPIDEV -+ if (!use_dt) -+ spi_register_board_info(bcm2708_spi_devices, -+ ARRAY_SIZE(bcm2708_spi_devices)); -+#endif -+} -+ -+#ifdef SYSTEM_TIMER -+static void timer_set_mode(enum clock_event_mode mode, -+ struct clock_event_device *clk) -+{ -+ switch (mode) { -+ case CLOCK_EVT_MODE_ONESHOT: /* Leave the timer disabled, .set_next_event will enable it */ -+ case CLOCK_EVT_MODE_SHUTDOWN: -+ break; -+ case CLOCK_EVT_MODE_PERIODIC: -+ -+ case CLOCK_EVT_MODE_UNUSED: -+ case CLOCK_EVT_MODE_RESUME: -+ -+ default: -+ printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n", -+ (int)mode); -+ break; -+ } -+ -+} -+ -+static int timer_set_next_event(unsigned long cycles, -+ struct clock_event_device *unused) -+{ -+ unsigned long stc; -+ do { -+ stc = readl(__io_address(ST_BASE + 0x04)); -+ /* We could take a FIQ here, which may push ST above STC3 */ -+ writel(stc + cycles, __io_address(ST_BASE + 0x18)); -+ } while ((signed long) cycles >= 0 && -+ (signed long) (readl(__io_address(ST_BASE + 0x04)) - stc) -+ >= (signed long) cycles); -+ return 0; -+} -+ -+static struct clock_event_device timer0_clockevent = { -+ .name = "timer0", -+ .shift = 32, -+ .features = CLOCK_EVT_FEAT_ONESHOT, -+ .set_mode = timer_set_mode, -+ .set_next_event = timer_set_next_event, -+}; -+ -+/* -+ * IRQ handler for the timer -+ */ -+static irqreturn_t bcm2709_timer_interrupt(int irq, void *dev_id) -+{ -+ struct clock_event_device *evt = &timer0_clockevent; -+ -+ writel(1 << 3, __io_address(ST_BASE + 0x00)); /* stcs clear timer int */ -+ -+ evt->event_handler(evt); -+ -+ return IRQ_HANDLED; -+} -+ -+static struct irqaction bcm2709_timer_irq = { -+ .name = "BCM2709 Timer Tick", -+ .flags = IRQF_TIMER | IRQF_IRQPOLL, -+ .handler = bcm2709_timer_interrupt, -+}; -+ -+/* -+ * Set up timer interrupt, and return the current time in seconds. -+ */ -+ -+static struct delay_timer bcm2709_delay_timer = { -+ .read_current_timer = bcm2709_read_current_timer, -+ .freq = STC_FREQ_HZ, -+}; -+ -+static void __init bcm2709_timer_init(void) -+{ -+ /* init high res timer */ -+ bcm2709_clocksource_init(); -+ -+ /* -+ * Make irqs happen for the system timer -+ */ -+ setup_irq(IRQ_TIMER3, &bcm2709_timer_irq); -+ -+ sched_clock_register(bcm2709_read_sched_clock, 32, STC_FREQ_HZ); -+ -+ timer0_clockevent.mult = -+ div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift); -+ timer0_clockevent.max_delta_ns = -+ clockevent_delta2ns(0xffffffff, &timer0_clockevent); -+ timer0_clockevent.min_delta_ns = -+ clockevent_delta2ns(0xf, &timer0_clockevent); -+ -+ timer0_clockevent.cpumask = cpumask_of(0); -+ clockevents_register_device(&timer0_clockevent); -+ -+ register_current_timer_delay(&bcm2709_delay_timer); -+} -+ -+#else -+ -+static void __init bcm2709_timer_init(void) -+{ -+ extern void dc4_arch_timer_init(void); -+ // timer control -+ writel(0, __io_address(ARM_LOCAL_CONTROL)); -+ // timer pre_scaler -+ writel(0x80000000, __io_address(ARM_LOCAL_PRESCALER)); // 19.2MHz -+ //writel(0x06AAAAAB, __io_address(ARM_LOCAL_PRESCALER)); // 1MHz -+ -+ if (use_dt) -+ { -+ of_clk_init(NULL); -+ clocksource_of_init(); -+ } -+ else -+ dc4_arch_timer_init(); -+} -+ -+#endif -+ -+#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) -+#include -+ -+static struct gpio_led bcm2709_leds[] = { -+ [0] = { -+ .gpio = 16, -+ .name = "led0", -+ .default_trigger = "mmc0", -+ .active_low = 1, -+ }, -+}; -+ -+static struct gpio_led_platform_data bcm2709_led_pdata = { -+ .num_leds = ARRAY_SIZE(bcm2709_leds), -+ .leds = bcm2709_leds, -+}; -+ -+static struct platform_device bcm2709_led_device = { -+ .name = "leds-gpio", -+ .id = -1, -+ .dev = { -+ .platform_data = &bcm2709_led_pdata, -+ }, -+}; -+ -+static void __init bcm2709_init_led(void) -+{ -+ bcm2709_leds[0].gpio = disk_led_gpio; -+ bcm2709_leds[0].active_low = disk_led_active_low; -+ bcm_register_device_dt(&bcm2709_led_device); -+} -+#else -+static inline void bcm2709_init_led(void) -+{ -+} -+#endif -+ -+void __init bcm2709_init_early(void) -+{ -+ /* -+ * Some devices allocate their coherent buffers from atomic -+ * context. Increase size of atomic coherent pool to make sure such -+ * the allocations won't fail. -+ */ -+ init_dma_coherent_pool_size(SZ_4M); -+} -+ -+static void __init board_reserve(void) -+{ -+#if defined(CONFIG_BCM_VC_CMA) -+ vc_cma_reserve(); -+#endif -+} -+ -+ -+#ifdef CONFIG_SMP -+#include -+ -+#include -+#include -+#include -+int dc4=0; -+//void dc4_log(unsigned x) { if (dc4) writel((x), __io_address(ST_BASE+10 + raw_smp_processor_id()*4)); } -+void dc4_log_dead(unsigned x) { if (dc4) writel((readl(__io_address(ST_BASE+0x10 + raw_smp_processor_id()*4)) & 0xffff) | ((x)<<16), __io_address(ST_BASE+0x10 + raw_smp_processor_id()*4)); } -+ -+static void bcm2835_send_doorbell(const struct cpumask *mask, unsigned int irq) -+{ -+ int cpu; -+ /* -+ * Ensure that stores to Normal memory are visible to the -+ * other CPUs before issuing the IPI. -+ */ -+ dsb(); -+ -+ /* Convert our logical CPU mask into a physical one. */ -+ for_each_cpu(cpu, mask) -+ { -+ /* submit softirq */ -+ writel(1<%x)\n", __FUNCTION__, (unsigned)virt_to_phys((void *)secondary_startup), (unsigned)__io_address(ST_BASE + 0x10)); -+ printk("[%s] ncores=%d\n", __FUNCTION__, ncores); -+ -+ for (i = 0; i < ncores; i++) { -+ set_cpu_possible(i, true); -+ /* enable IRQ (not FIQ) */ -+ writel(0x1, __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 0x4 * i)); -+ //writel(0xf, __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 0x4 * i)); -+ } -+ set_smp_cross_call(bcm2835_send_doorbell); -+} -+ -+/* -+ * for arch/arm/kernel/smp.c:smp_prepare_cpus(unsigned int max_cpus) -+ */ -+void __init bcm2709_smp_prepare_cpus(unsigned int max_cpus) -+{ -+ //void __iomem *scu_base; -+ -+ printk("[%s] enter\n", __FUNCTION__); -+ //scu_base = scu_base_addr(); -+ //scu_enable(scu_base); -+} -+ -+/* -+ * for linux/arch/arm/kernel/smp.c:secondary_start_kernel(void) -+ */ -+void __cpuinit bcm2709_secondary_init(unsigned int cpu) -+{ -+ printk("[%s] enter cpu:%d\n", __FUNCTION__, cpu); -+ //gic_secondary_init(0); -+} -+ -+/* -+ * for linux/arch/arm/kernel/smp.c:__cpu_up(..) -+ */ -+int __cpuinit bcm2709_boot_secondary(unsigned int cpu, struct task_struct *idle) -+{ -+ void secondary_startup(void); -+ void *mbox_set = __io_address(ARM_LOCAL_MAILBOX3_SET0 + 0x10 * MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0)); -+ void *mbox_clr = __io_address(ARM_LOCAL_MAILBOX3_CLR0 + 0x10 * MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0)); -+ unsigned secondary_boot = (unsigned)virt_to_phys((void *)secondary_startup); -+ int timeout=20; -+ unsigned t = -1; -+ //printk("[%s] enter cpu:%d (%x->%p) %x\n", __FUNCTION__, cpu, secondary_boot, wake, readl(wake)); -+ -+ dsb(); -+ BUG_ON(readl(mbox_clr) != 0); -+ writel(secondary_boot, mbox_set); -+ -+ while (--timeout > 0) { -+ t = readl(mbox_clr); -+ if (t == 0) break; -+ cpu_relax(); -+ } -+ if (timeout==0) -+ printk("[%s] cpu:%d failed to start (%x)\n", __FUNCTION__, cpu, t); -+ else -+ printk("[%s] cpu:%d started (%x) %d\n", __FUNCTION__, cpu, t, timeout); -+ -+ return 0; -+} -+ -+ -+struct smp_operations bcm2709_smp_ops __initdata = { -+ .smp_init_cpus = bcm2709_smp_init_cpus, -+ .smp_prepare_cpus = bcm2709_smp_prepare_cpus, -+ .smp_secondary_init = bcm2709_secondary_init, -+ .smp_boot_secondary = bcm2709_boot_secondary, -+}; -+#endif -+ -+static const char * const bcm2709_compat[] = { -+ "brcm,bcm2709", -+ "brcm,bcm2708", /* Could use bcm2708 in a pinch */ -+ NULL -+}; -+ -+MACHINE_START(BCM2709, "BCM2709") -+ /* Maintainer: Broadcom Europe Ltd. */ -+#ifdef CONFIG_SMP -+ .smp = smp_ops(bcm2709_smp_ops), -+#endif -+ .map_io = bcm2709_map_io, -+ .init_irq = bcm2709_init_irq, -+ .init_time = bcm2709_timer_init, -+ .init_machine = bcm2709_init, -+ .init_early = bcm2709_init_early, -+ .reserve = board_reserve, -+ .restart = bcm2709_restart, -+ .dt_compat = bcm2709_compat, -+MACHINE_END -+ -+MACHINE_START(BCM2708, "BCM2709") -+ /* Maintainer: Broadcom Europe Ltd. */ -+#ifdef CONFIG_SMP -+ .smp = smp_ops(bcm2709_smp_ops), -+#endif -+ .map_io = bcm2709_map_io, -+ .init_irq = bcm2709_init_irq, -+ .init_time = bcm2709_timer_init, -+ .init_machine = bcm2709_init, -+ .init_early = bcm2709_init_early, -+ .reserve = board_reserve, -+ .restart = bcm2709_restart, -+ .dt_compat = bcm2709_compat, -+MACHINE_END -+ -+module_param(force_core, uint, 0644); -+module_param(boardrev, uint, 0644); -+module_param(serial, uint, 0644); -+module_param(uart_clock, uint, 0644); -+module_param(disk_led_gpio, uint, 0644); -+module_param(disk_led_active_low, uint, 0644); -+module_param(reboot_part, uint, 0644); -+module_param(w1_gpio_pin, uint, 0644); -+module_param(w1_gpio_pullup, uint, 0644); -+module_param(vc_i2c_override, bool, 0644); -+MODULE_PARM_DESC(vc_i2c_override, "Allow the use of VC's I2C peripheral."); -+module_param(pps_gpio_pin, int, 0644); -+MODULE_PARM_DESC(pps_gpio_pin, "Set GPIO pin to reserve for PPS"); -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/bcm2709.h linux-rpi/arch/arm/mach-bcm2709/bcm2709.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2709/bcm2709.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2709/bcm2709.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,49 @@ -+/* -+ * linux/arch/arm/mach-bcm2708/bcm2708.h -+ * -+ * BCM2708 machine support header -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef __BCM2708_BCM2708_H -+#define __BCM2708_BCM2708_H -+ -+#include -+ -+extern void __init bcm2708_init(void); -+extern void __init bcm2708_init_irq(void); -+extern void __init bcm2708_map_io(void); -+extern struct sys_timer bcm2708_timer; -+extern unsigned int mmc_status(struct device *dev); -+ -+#define AMBA_DEVICE(name, busid, base, plat) \ -+static struct amba_device name##_device = { \ -+ .dev = { \ -+ .coherent_dma_mask = ~0, \ -+ .init_name = busid, \ -+ .platform_data = plat, \ -+ }, \ -+ .res = { \ -+ .start = base##_BASE, \ -+ .end = (base##_BASE) + SZ_4K - 1,\ -+ .flags = IORESOURCE_MEM, \ -+ }, \ -+ .irq = base##_IRQ, \ -+} -+ -+#endif -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/delay.S linux-rpi/arch/arm/mach-bcm2709/delay.S ---- linux-4.1.13.orig/arch/arm/mach-bcm2709/delay.S 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2709/delay.S 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,21 @@ -+/* -+ * linux/arch/arm/lib/delay.S -+ * -+ * Copyright (C) 1995, 1996 Russell King -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+#include -+#include -+#include -+ -+ .text -+.align 3 @ 8 byte alignment seems to be needed to avoid fetching stalls -+@ Delay routine -+ENTRY(bcm2708_delay) -+ subs r0, r0, #1 -+ bhi bcm2708_delay -+ mov pc, lr -+ENDPROC(bcm2708_delay) -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/arm_control.h linux-rpi/arch/arm/mach-bcm2709/include/mach/arm_control.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/arm_control.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/arm_control.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,493 @@ -+/* -+ * linux/arch/arm/mach-bcm2708/arm_control.h -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef __BCM2708_ARM_CONTROL_H -+#define __BCM2708_ARM_CONTROL_H -+ -+/* -+ * Definitions and addresses for the ARM CONTROL logic -+ * This file is manually generated. -+ */ -+ -+#define ARM_BASE 0x7E00B000 -+ -+/* Basic configuration */ -+#define ARM_CONTROL0 HW_REGISTER_RW(ARM_BASE+0x000) -+#define ARM_C0_SIZ128M 0x00000000 -+#define ARM_C0_SIZ256M 0x00000001 -+#define ARM_C0_SIZ512M 0x00000002 -+#define ARM_C0_SIZ1G 0x00000003 -+#define ARM_C0_BRESP0 0x00000000 -+#define ARM_C0_BRESP1 0x00000004 -+#define ARM_C0_BRESP2 0x00000008 -+#define ARM_C0_BOOTHI 0x00000010 -+#define ARM_C0_UNUSED05 0x00000020 /* free */ -+#define ARM_C0_FULLPERI 0x00000040 -+#define ARM_C0_UNUSED78 0x00000180 /* free */ -+#define ARM_C0_JTAGMASK 0x00000E00 -+#define ARM_C0_JTAGOFF 0x00000000 -+#define ARM_C0_JTAGBASH 0x00000800 /* Debug on GPIO off */ -+#define ARM_C0_JTAGGPIO 0x00000C00 /* Debug on GPIO on */ -+#define ARM_C0_APROTMSK 0x0000F000 -+#define ARM_C0_DBG0SYNC 0x00010000 /* VPU0 halt sync */ -+#define ARM_C0_DBG1SYNC 0x00020000 /* VPU1 halt sync */ -+#define ARM_C0_SWDBGREQ 0x00040000 /* HW debug request */ -+#define ARM_C0_PASSHALT 0x00080000 /* ARM halt passed to debugger */ -+#define ARM_C0_PRIO_PER 0x00F00000 /* per priority mask */ -+#define ARM_C0_PRIO_L2 0x0F000000 -+#define ARM_C0_PRIO_UC 0xF0000000 -+ -+#define ARM_C0_APROTPASS 0x0000A000 /* Translate 1:1 */ -+#define ARM_C0_APROTUSER 0x00000000 /* Only user mode */ -+#define ARM_C0_APROTSYST 0x0000F000 /* Only system mode */ -+ -+ -+#define ARM_CONTROL1 HW_REGISTER_RW(ARM_BASE+0x440) -+#define ARM_C1_TIMER 0x00000001 /* re-route timer IRQ to VC */ -+#define ARM_C1_MAIL 0x00000002 /* re-route Mail IRQ to VC */ -+#define ARM_C1_BELL0 0x00000004 /* re-route Doorbell 0 to VC */ -+#define ARM_C1_BELL1 0x00000008 /* re-route Doorbell 1 to VC */ -+#define ARM_C1_PERSON 0x00000100 /* peripherals on */ -+#define ARM_C1_REQSTOP 0x00000200 /* ASYNC bridge request stop */ -+ -+#define ARM_STATUS HW_REGISTER_RW(ARM_BASE+0x444) -+#define ARM_S_ACKSTOP 0x80000000 /* Bridge stopped */ -+#define ARM_S_READPEND 0x000003FF /* pending reads counter */ -+#define ARM_S_WRITPEND 0x000FFC00 /* pending writes counter */ -+ -+#define ARM_ERRHALT HW_REGISTER_RW(ARM_BASE+0x448) -+#define ARM_EH_PERIBURST 0x00000001 /* Burst write seen on peri bus */ -+#define ARM_EH_ILLADDRS1 0x00000002 /* Address bits 25-27 error */ -+#define ARM_EH_ILLADDRS2 0x00000004 /* Address bits 31-28 error */ -+#define ARM_EH_VPU0HALT 0x00000008 /* VPU0 halted & in debug mode */ -+#define ARM_EH_VPU1HALT 0x00000010 /* VPU1 halted & in debug mode */ -+#define ARM_EH_ARMHALT 0x00000020 /* ARM in halted debug mode */ -+ -+#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C) -+#define ARM_ID HW_REGISTER_RW(ARM_BASE+0x44C) -+#define ARM_IDVAL 0x364D5241 -+ -+/* Translation memory */ -+#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100) -+/* 32 locations: 0x100.. 0x17F */ -+/* 32 spare means we CAN go to 64 pages.... */ -+ -+ -+/* Interrupts */ -+#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200) /* Top IRQ bits */ -+#define ARM_I0_TIMER 0x00000001 /* timer IRQ */ -+#define ARM_I0_MAIL 0x00000002 /* Mail IRQ */ -+#define ARM_I0_BELL0 0x00000004 /* Doorbell 0 */ -+#define ARM_I0_BELL1 0x00000008 /* Doorbell 1 */ -+#define ARM_I0_BANK1 0x00000100 /* Bank1 IRQ */ -+#define ARM_I0_BANK2 0x00000200 /* Bank2 IRQ */ -+ -+#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) /* All bank1 IRQ bits */ -+/* todo: all I1_interrupt sources */ -+#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) /* All bank2 IRQ bits */ -+/* todo: all I2_interrupt sources */ -+ -+#define ARM_IRQ_FAST HW_REGISTER_RW(ARM_BASE+0x20C) /* FIQ control */ -+#define ARM_IF_INDEX 0x0000007F /* FIQ select */ -+#define ARM_IF_ENABLE 0x00000080 /* FIQ enable */ -+#define ARM_IF_VCMASK 0x0000003F /* FIQ = (index from VC source) */ -+#define ARM_IF_TIMER 0x00000040 /* FIQ = ARM timer */ -+#define ARM_IF_MAIL 0x00000041 /* FIQ = ARM Mail */ -+#define ARM_IF_BELL0 0x00000042 /* FIQ = ARM Doorbell 0 */ -+#define ARM_IF_BELL1 0x00000043 /* FIQ = ARM Doorbell 1 */ -+#define ARM_IF_VP0HALT 0x00000044 /* FIQ = VPU0 Halt seen */ -+#define ARM_IF_VP1HALT 0x00000045 /* FIQ = VPU1 Halt seen */ -+#define ARM_IF_ILLEGAL 0x00000046 /* FIQ = Illegal access seen */ -+ -+#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) /* Bank1 enable bits */ -+#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) /* Bank2 enable bits */ -+#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) /* ARM irqs enable bits */ -+#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) /* Bank1 disable bits */ -+#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) /* Bank2 disable bits */ -+#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) /* ARM irqs disable bits */ -+#define ARM_IE_TIMER 0x00000001 /* Timer IRQ */ -+#define ARM_IE_MAIL 0x00000002 /* Mail IRQ */ -+#define ARM_IE_BELL0 0x00000004 /* Doorbell 0 */ -+#define ARM_IE_BELL1 0x00000008 /* Doorbell 1 */ -+#define ARM_IE_VP0HALT 0x00000010 /* VPU0 Halt */ -+#define ARM_IE_VP1HALT 0x00000020 /* VPU1 Halt */ -+#define ARM_IE_ILLEGAL 0x00000040 /* Illegal access seen */ -+ -+/* Timer */ -+/* For reg. fields see sp804 spec. */ -+#define ARM_T_LOAD HW_REGISTER_RW(ARM_BASE+0x400) -+#define ARM_T_VALUE HW_REGISTER_RW(ARM_BASE+0x404) -+#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408) -+#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C) -+#define ARM_T_RAWIRQ HW_REGISTER_RW(ARM_BASE+0x410) -+#define ARM_T_MSKIRQ HW_REGISTER_RW(ARM_BASE+0x414) -+#define ARM_T_RELOAD HW_REGISTER_RW(ARM_BASE+0x418) -+#define ARM_T_PREDIV HW_REGISTER_RW(ARM_BASE+0x41c) -+#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420) -+ -+#define TIMER_CTRL_ONESHOT (1 << 0) -+#define TIMER_CTRL_32BIT (1 << 1) -+#define TIMER_CTRL_DIV1 (0 << 2) -+#define TIMER_CTRL_DIV16 (1 << 2) -+#define TIMER_CTRL_DIV256 (2 << 2) -+#define TIMER_CTRL_IE (1 << 5) -+#define TIMER_CTRL_PERIODIC (1 << 6) -+#define TIMER_CTRL_ENABLE (1 << 7) -+#define TIMER_CTRL_DBGHALT (1 << 8) -+#define TIMER_CTRL_ENAFREE (1 << 9) -+#define TIMER_CTRL_FREEDIV_SHIFT 16) -+#define TIMER_CTRL_FREEDIV_MASK 0xff -+ -+/* Semaphores, Doorbells, Mailboxes */ -+#define ARM_SBM_OWN0 (ARM_BASE+0x800) -+#define ARM_SBM_OWN1 (ARM_BASE+0x900) -+#define ARM_SBM_OWN2 (ARM_BASE+0xA00) -+#define ARM_SBM_OWN3 (ARM_BASE+0xB00) -+ -+/* MAILBOXES -+ * Register flags are common across all -+ * owner registers. See end of this section -+ * -+ * Semaphores, Doorbells, Mailboxes Owner 0 -+ * -+ */ -+ -+#define ARM_0_SEMS HW_REGISTER_RW(ARM_SBM_OWN0+0x00) -+#define ARM_0_SEM0 HW_REGISTER_RW(ARM_SBM_OWN0+0x00) -+#define ARM_0_SEM1 HW_REGISTER_RW(ARM_SBM_OWN0+0x04) -+#define ARM_0_SEM2 HW_REGISTER_RW(ARM_SBM_OWN0+0x08) -+#define ARM_0_SEM3 HW_REGISTER_RW(ARM_SBM_OWN0+0x0C) -+#define ARM_0_SEM4 HW_REGISTER_RW(ARM_SBM_OWN0+0x10) -+#define ARM_0_SEM5 HW_REGISTER_RW(ARM_SBM_OWN0+0x14) -+#define ARM_0_SEM6 HW_REGISTER_RW(ARM_SBM_OWN0+0x18) -+#define ARM_0_SEM7 HW_REGISTER_RW(ARM_SBM_OWN0+0x1C) -+#define ARM_0_BELL0 HW_REGISTER_RW(ARM_SBM_OWN0+0x40) -+#define ARM_0_BELL1 HW_REGISTER_RW(ARM_SBM_OWN0+0x44) -+#define ARM_0_BELL2 HW_REGISTER_RW(ARM_SBM_OWN0+0x48) -+#define ARM_0_BELL3 HW_REGISTER_RW(ARM_SBM_OWN0+0x4C) -+/* MAILBOX 0 access in Owner 0 area */ -+/* Some addresses should ONLY be used by owner 0 */ -+#define ARM_0_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) */ -+#define ARM_0_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) Normal read */ -+#define ARM_0_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN0+0x90) /* none-pop read */ -+#define ARM_0_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN0+0x94) /* Sender read (only LS 2 bits) */ -+#define ARM_0_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN0+0x98) /* Status read */ -+#define ARM_0_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0x9C) /* Config read/write */ -+/* MAILBOX 1 access in Owner 0 area */ -+/* Owner 0 should only WRITE to this mailbox */ -+#define ARM_0_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) /* .. 0xAC (4 locations) */ -+/*#define ARM_0_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_0_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_0_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_0_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN0+0xB8) /* Status read */ -+/*#define ARM_0_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) */ /* DO NOT USE THIS !!!!! */ -+/* General SEM, BELL, MAIL config/status */ -+#define ARM_0_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE0) /* semaphore clear/debug register */ -+#define ARM_0_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE4) /* Doorbells clear/debug register */ -+#define ARM_0_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xF8) /* ALL interrupts */ -+#define ARM_0_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xFC) /* IRQS pending for owner 0 */ -+ -+/* Semaphores, Doorbells, Mailboxes Owner 1 */ -+#define ARM_1_SEMS HW_REGISTER_RW(ARM_SBM_OWN1+0x00) -+#define ARM_1_SEM0 HW_REGISTER_RW(ARM_SBM_OWN1+0x00) -+#define ARM_1_SEM1 HW_REGISTER_RW(ARM_SBM_OWN1+0x04) -+#define ARM_1_SEM2 HW_REGISTER_RW(ARM_SBM_OWN1+0x08) -+#define ARM_1_SEM3 HW_REGISTER_RW(ARM_SBM_OWN1+0x0C) -+#define ARM_1_SEM4 HW_REGISTER_RW(ARM_SBM_OWN1+0x10) -+#define ARM_1_SEM5 HW_REGISTER_RW(ARM_SBM_OWN1+0x14) -+#define ARM_1_SEM6 HW_REGISTER_RW(ARM_SBM_OWN1+0x18) -+#define ARM_1_SEM7 HW_REGISTER_RW(ARM_SBM_OWN1+0x1C) -+#define ARM_1_BELL0 HW_REGISTER_RW(ARM_SBM_OWN1+0x40) -+#define ARM_1_BELL1 HW_REGISTER_RW(ARM_SBM_OWN1+0x44) -+#define ARM_1_BELL2 HW_REGISTER_RW(ARM_SBM_OWN1+0x48) -+#define ARM_1_BELL3 HW_REGISTER_RW(ARM_SBM_OWN1+0x4C) -+/* MAILBOX 0 access in Owner 0 area */ -+/* Owner 1 should only WRITE to this mailbox */ -+#define ARM_1_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0x80) /* .. 0x8C (4 locations) */ -+/*#define ARM_1_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN1+0x80) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_1_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN1+0x98) /* Status read */ -+/*#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) */ /* DO NOT USE THIS !!!!! */ -+/* MAILBOX 1 access in Owner 0 area */ -+#define ARM_1_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) */ -+#define ARM_1_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) Normal read */ -+#define ARM_1_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN1+0xB0) /* none-pop read */ -+#define ARM_1_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN1+0xB4) /* Sender read (only LS 2 bits) */ -+#define ARM_1_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN1+0xB8) /* Status read */ -+#define ARM_1_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0xBC) -+/* General SEM, BELL, MAIL config/status */ -+#define ARM_1_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE0) /* semaphore clear/debug register */ -+#define ARM_1_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE4) /* Doorbells clear/debug register */ -+#define ARM_1_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xFC) /* IRQS pending for owner 1 */ -+#define ARM_1_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xF8) /* ALL interrupts */ -+ -+/* Semaphores, Doorbells, Mailboxes Owner 2 */ -+#define ARM_2_SEMS HW_REGISTER_RW(ARM_SBM_OWN2+0x00) -+#define ARM_2_SEM0 HW_REGISTER_RW(ARM_SBM_OWN2+0x00) -+#define ARM_2_SEM1 HW_REGISTER_RW(ARM_SBM_OWN2+0x04) -+#define ARM_2_SEM2 HW_REGISTER_RW(ARM_SBM_OWN2+0x08) -+#define ARM_2_SEM3 HW_REGISTER_RW(ARM_SBM_OWN2+0x0C) -+#define ARM_2_SEM4 HW_REGISTER_RW(ARM_SBM_OWN2+0x10) -+#define ARM_2_SEM5 HW_REGISTER_RW(ARM_SBM_OWN2+0x14) -+#define ARM_2_SEM6 HW_REGISTER_RW(ARM_SBM_OWN2+0x18) -+#define ARM_2_SEM7 HW_REGISTER_RW(ARM_SBM_OWN2+0x1C) -+#define ARM_2_BELL0 HW_REGISTER_RW(ARM_SBM_OWN2+0x40) -+#define ARM_2_BELL1 HW_REGISTER_RW(ARM_SBM_OWN2+0x44) -+#define ARM_2_BELL2 HW_REGISTER_RW(ARM_SBM_OWN2+0x48) -+#define ARM_2_BELL3 HW_REGISTER_RW(ARM_SBM_OWN2+0x4C) -+/* MAILBOX 0 access in Owner 2 area */ -+/* Owner 2 should only WRITE to this mailbox */ -+#define ARM_2_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0x80) /* .. 0x8C (4 locations) */ -+/*#define ARM_2_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN2+0x80) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_2_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN2+0x98) /* Status read */ -+/*#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C) */ /* DO NOT USE THIS !!!!! */ -+/* MAILBOX 1 access in Owner 2 area */ -+/* Owner 2 should only WRITE to this mailbox */ -+#define ARM_2_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) /* .. 0xAC (4 locations) */ -+/*#define ARM_2_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_2_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_2_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_2_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN2+0xB8) /* Status read */ -+/*#define ARM_2_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) */ /* DO NOT USE THIS !!!!! */ -+/* General SEM, BELL, MAIL config/status */ -+#define ARM_2_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE0) /* semaphore clear/debug register */ -+#define ARM_2_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE4) /* Doorbells clear/debug register */ -+#define ARM_2_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xFC) /* IRQS pending for owner 2 */ -+#define ARM_2_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xF8) /* ALL interrupts */ -+ -+/* Semaphores, Doorbells, Mailboxes Owner 3 */ -+#define ARM_3_SEMS HW_REGISTER_RW(ARM_SBM_OWN3+0x00) -+#define ARM_3_SEM0 HW_REGISTER_RW(ARM_SBM_OWN3+0x00) -+#define ARM_3_SEM1 HW_REGISTER_RW(ARM_SBM_OWN3+0x04) -+#define ARM_3_SEM2 HW_REGISTER_RW(ARM_SBM_OWN3+0x08) -+#define ARM_3_SEM3 HW_REGISTER_RW(ARM_SBM_OWN3+0x0C) -+#define ARM_3_SEM4 HW_REGISTER_RW(ARM_SBM_OWN3+0x10) -+#define ARM_3_SEM5 HW_REGISTER_RW(ARM_SBM_OWN3+0x14) -+#define ARM_3_SEM6 HW_REGISTER_RW(ARM_SBM_OWN3+0x18) -+#define ARM_3_SEM7 HW_REGISTER_RW(ARM_SBM_OWN3+0x1C) -+#define ARM_3_BELL0 HW_REGISTER_RW(ARM_SBM_OWN3+0x40) -+#define ARM_3_BELL1 HW_REGISTER_RW(ARM_SBM_OWN3+0x44) -+#define ARM_3_BELL2 HW_REGISTER_RW(ARM_SBM_OWN3+0x48) -+#define ARM_3_BELL3 HW_REGISTER_RW(ARM_SBM_OWN3+0x4C) -+/* MAILBOX 0 access in Owner 3 area */ -+/* Owner 3 should only WRITE to this mailbox */ -+#define ARM_3_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0x80) /* .. 0x8C (4 locations) */ -+/*#define ARM_3_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN3+0x80) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98) /* Status read */ -+/*#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C) */ /* DO NOT USE THIS !!!!! */ -+/* MAILBOX 1 access in Owner 3 area */ -+/* Owner 3 should only WRITE to this mailbox */ -+#define ARM_3_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) /* .. 0xAC (4 locations) */ -+/*#define ARM_3_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_3_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) */ /* DO NOT USE THIS !!!!! */ -+/*#define ARM_3_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) */ /* DO NOT USE THIS !!!!! */ -+#define ARM_3_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN3+0xB8) /* Status read */ -+/*#define ARM_3_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) */ /* DO NOT USE THIS !!!!! */ -+/* General SEM, BELL, MAIL config/status */ -+#define ARM_3_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE0) /* semaphore clear/debug register */ -+#define ARM_3_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE4) /* Doorbells clear/debug register */ -+#define ARM_3_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xFC) /* IRQS pending for owner 3 */ -+#define ARM_3_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xF8) /* ALL interrupts */ -+ -+ -+ -+/* Mailbox flags. Valid for all owners */ -+ -+/* Mailbox status register (...0x98) */ -+#define ARM_MS_FULL 0x80000000 -+#define ARM_MS_EMPTY 0x40000000 -+#define ARM_MS_LEVEL 0x400000FF /* Max. value depdnds on mailbox depth parameter */ -+ -+/* MAILBOX config/status register (...0x9C) */ -+/* ANY write to this register clears the error bits! */ -+#define ARM_MC_IHAVEDATAIRQEN 0x00000001 /* mailbox irq enable: has data */ -+#define ARM_MC_IHAVESPACEIRQEN 0x00000002 /* mailbox irq enable: has space */ -+#define ARM_MC_OPPISEMPTYIRQEN 0x00000004 /* mailbox irq enable: Opp. is empty */ -+#define ARM_MC_MAIL_CLEAR 0x00000008 /* mailbox clear write 1, then 0 */ -+#define ARM_MC_IHAVEDATAIRQPEND 0x00000010 /* mailbox irq pending: has space */ -+#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mailbox irq pending: Opp. is empty */ -+#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mailbox irq pending */ -+/* Bit 7 is unused */ -+#define ARM_MC_ERRNOOWN 0x00000100 /* error : none owner read from mailbox */ -+#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */ -+#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */ -+ -+/* Semaphore clear/debug register (...0xE0) */ -+#define ARM_SD_OWN0 0x00000003 /* Owner of sem 0 */ -+#define ARM_SD_OWN1 0x0000000C /* Owner of sem 1 */ -+#define ARM_SD_OWN2 0x00000030 /* Owner of sem 2 */ -+#define ARM_SD_OWN3 0x000000C0 /* Owner of sem 3 */ -+#define ARM_SD_OWN4 0x00000300 /* Owner of sem 4 */ -+#define ARM_SD_OWN5 0x00000C00 /* Owner of sem 5 */ -+#define ARM_SD_OWN6 0x00003000 /* Owner of sem 6 */ -+#define ARM_SD_OWN7 0x0000C000 /* Owner of sem 7 */ -+#define ARM_SD_SEM0 0x00010000 /* Status of sem 0 */ -+#define ARM_SD_SEM1 0x00020000 /* Status of sem 1 */ -+#define ARM_SD_SEM2 0x00040000 /* Status of sem 2 */ -+#define ARM_SD_SEM3 0x00080000 /* Status of sem 3 */ -+#define ARM_SD_SEM4 0x00100000 /* Status of sem 4 */ -+#define ARM_SD_SEM5 0x00200000 /* Status of sem 5 */ -+#define ARM_SD_SEM6 0x00400000 /* Status of sem 6 */ -+#define ARM_SD_SEM7 0x00800000 /* Status of sem 7 */ -+ -+/* Doorbells clear/debug register (...0xE4) */ -+#define ARM_BD_OWN0 0x00000003 /* Owner of doorbell 0 */ -+#define ARM_BD_OWN1 0x0000000C /* Owner of doorbell 1 */ -+#define ARM_BD_OWN2 0x00000030 /* Owner of doorbell 2 */ -+#define ARM_BD_OWN3 0x000000C0 /* Owner of doorbell 3 */ -+#define ARM_BD_BELL0 0x00000100 /* Status of doorbell 0 */ -+#define ARM_BD_BELL1 0x00000200 /* Status of doorbell 1 */ -+#define ARM_BD_BELL2 0x00000400 /* Status of doorbell 2 */ -+#define ARM_BD_BELL3 0x00000800 /* Status of doorbell 3 */ -+ -+/* MY IRQS register (...0xF8) */ -+#define ARM_MYIRQ_BELL 0x00000001 /* This owner has a doorbell IRQ */ -+#define ARM_MYIRQ_MAIL 0x00000002 /* This owner has a mailbox IRQ */ -+ -+/* ALL IRQS register (...0xF8) */ -+#define ARM_AIS_BELL0 0x00000001 /* Doorbell 0 IRQ pending */ -+#define ARM_AIS_BELL1 0x00000002 /* Doorbell 1 IRQ pending */ -+#define ARM_AIS_BELL2 0x00000004 /* Doorbell 2 IRQ pending */ -+#define ARM_AIS_BELL3 0x00000008 /* Doorbell 3 IRQ pending */ -+#define ARM_AIS0_HAVEDATA 0x00000010 /* MAIL 0 has data IRQ pending */ -+#define ARM_AIS0_HAVESPAC 0x00000020 /* MAIL 0 has space IRQ pending */ -+#define ARM_AIS0_OPPEMPTY 0x00000040 /* MAIL 0 opposite is empty IRQ */ -+#define ARM_AIS1_HAVEDATA 0x00000080 /* MAIL 1 has data IRQ pending */ -+#define ARM_AIS1_HAVESPAC 0x00000100 /* MAIL 1 has space IRQ pending */ -+#define ARM_AIS1_OPPEMPTY 0x00000200 /* MAIL 1 opposite is empty IRQ */ -+/* Note that bell-0, bell-1 and MAIL0 IRQ go only to the ARM */ -+/* Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC */ -+/* */ -+/* ARM JTAG BASH */ -+/* */ -+#define AJB_BASE 0x7e2000c0 -+ -+#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00) -+#define AJB_BITS0 0x000000 -+#define AJB_BITS4 0x000004 -+#define AJB_BITS8 0x000008 -+#define AJB_BITS12 0x00000C -+#define AJB_BITS16 0x000010 -+#define AJB_BITS20 0x000014 -+#define AJB_BITS24 0x000018 -+#define AJB_BITS28 0x00001C -+#define AJB_BITS32 0x000020 -+#define AJB_BITS34 0x000022 -+#define AJB_OUT_MS 0x000040 -+#define AJB_OUT_LS 0x000000 -+#define AJB_INV_CLK 0x000080 -+#define AJB_D0_RISE 0x000100 -+#define AJB_D0_FALL 0x000000 -+#define AJB_D1_RISE 0x000200 -+#define AJB_D1_FALL 0x000000 -+#define AJB_IN_RISE 0x000400 -+#define AJB_IN_FALL 0x000000 -+#define AJB_ENABLE 0x000800 -+#define AJB_HOLD0 0x000000 -+#define AJB_HOLD1 0x001000 -+#define AJB_HOLD2 0x002000 -+#define AJB_HOLD3 0x003000 -+#define AJB_RESETN 0x004000 -+#define AJB_CLKSHFT 16 -+#define AJB_BUSY 0x80000000 -+#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04) -+#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08) -+#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c) -+ -+#define ARM_LOCAL_BASE 0x40000000 -+#define ARM_LOCAL_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x000) -+#define ARM_LOCAL_PRESCALER HW_REGISTER_RW(ARM_LOCAL_BASE+0x008) -+#define ARM_LOCAL_GPU_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x00C) -+#define ARM_LOCAL_PM_ROUTING_SET HW_REGISTER_RW(ARM_LOCAL_BASE+0x010) -+#define ARM_LOCAL_PM_ROUTING_CLR HW_REGISTER_RW(ARM_LOCAL_BASE+0x014) -+#define ARM_LOCAL_TIMER_LS HW_REGISTER_RW(ARM_LOCAL_BASE+0x01C) -+#define ARM_LOCAL_TIMER_MS HW_REGISTER_RW(ARM_LOCAL_BASE+0x020) -+#define ARM_LOCAL_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x024) -+#define ARM_LOCAL_AXI_COUNT HW_REGISTER_RW(ARM_LOCAL_BASE+0x02C) -+#define ARM_LOCAL_AXI_IRQ HW_REGISTER_RW(ARM_LOCAL_BASE+0x030) -+#define ARM_LOCAL_TIMER_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x034) -+#define ARM_LOCAL_TIMER_WRITE HW_REGISTER_RW(ARM_LOCAL_BASE+0x038) -+ -+#define ARM_LOCAL_TIMER_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x040) -+#define ARM_LOCAL_TIMER_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x044) -+#define ARM_LOCAL_TIMER_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x048) -+#define ARM_LOCAL_TIMER_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x04C) -+ -+#define ARM_LOCAL_MAILBOX_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x050) -+#define ARM_LOCAL_MAILBOX_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x054) -+#define ARM_LOCAL_MAILBOX_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x058) -+#define ARM_LOCAL_MAILBOX_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x05C) -+ -+#define ARM_LOCAL_IRQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x060) -+#define ARM_LOCAL_IRQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x064) -+#define ARM_LOCAL_IRQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x068) -+#define ARM_LOCAL_IRQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x06C) -+ -+#define ARM_LOCAL_FIQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x070) -+#define ARM_LOCAL_FIQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x074) -+#define ARM_LOCAL_FIQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x078) -+#define ARM_LOCAL_FIQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x07C) -+ -+#define ARM_LOCAL_MAILBOX0_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x080) -+#define ARM_LOCAL_MAILBOX1_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x084) -+#define ARM_LOCAL_MAILBOX2_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x088) -+#define ARM_LOCAL_MAILBOX3_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x08C) -+ -+#define ARM_LOCAL_MAILBOX0_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x090) -+#define ARM_LOCAL_MAILBOX1_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x094) -+#define ARM_LOCAL_MAILBOX2_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x098) -+#define ARM_LOCAL_MAILBOX3_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x09C) -+ -+#define ARM_LOCAL_MAILBOX0_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A0) -+#define ARM_LOCAL_MAILBOX1_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A4) -+#define ARM_LOCAL_MAILBOX2_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A8) -+#define ARM_LOCAL_MAILBOX3_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0AC) -+ -+#define ARM_LOCAL_MAILBOX0_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B0) -+#define ARM_LOCAL_MAILBOX1_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B4) -+#define ARM_LOCAL_MAILBOX2_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B8) -+#define ARM_LOCAL_MAILBOX3_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0BC) -+ -+#define ARM_LOCAL_MAILBOX0_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C0) -+#define ARM_LOCAL_MAILBOX1_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C4) -+#define ARM_LOCAL_MAILBOX2_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C8) -+#define ARM_LOCAL_MAILBOX3_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0CC) -+ -+#define ARM_LOCAL_MAILBOX0_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D0) -+#define ARM_LOCAL_MAILBOX1_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D4) -+#define ARM_LOCAL_MAILBOX2_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D8) -+#define ARM_LOCAL_MAILBOX3_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0DC) -+ -+#define ARM_LOCAL_MAILBOX0_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E0) -+#define ARM_LOCAL_MAILBOX1_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E4) -+#define ARM_LOCAL_MAILBOX2_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E8) -+#define ARM_LOCAL_MAILBOX3_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0EC) -+ -+#define ARM_LOCAL_MAILBOX0_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F0) -+#define ARM_LOCAL_MAILBOX1_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F4) -+#define ARM_LOCAL_MAILBOX2_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F8) -+#define ARM_LOCAL_MAILBOX3_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0FC) -+ -+#endif -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/barriers.h linux-rpi/arch/arm/mach-bcm2709/include/mach/barriers.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/barriers.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/barriers.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,3 @@ -+#define mb() dsb() -+#define rmb() dsb() -+#define wmb() mb() -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/clkdev.h linux-rpi/arch/arm/mach-bcm2709/include/mach/clkdev.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/clkdev.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/clkdev.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,7 @@ -+#ifndef __ASM_MACH_CLKDEV_H -+#define __ASM_MACH_CLKDEV_H -+ -+#define __clk_get(clk) ({ 1; }) -+#define __clk_put(clk) do { } while (0) -+ -+#endif -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/debug-macro.S linux-rpi/arch/arm/mach-bcm2709/include/mach/debug-macro.S ---- linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/debug-macro.S 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/debug-macro.S 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,22 @@ -+/* arch/arm/mach-bcm2708/include/mach/debug-macro.S -+ * -+ * Debugging macro include header -+ * -+ * Copyright (C) 2010 Broadcom -+ * Copyright (C) 1994-1999 Russell King -+ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+*/ -+ -+#include -+ -+ .macro addruart, rp, rv, tmp -+ ldr \rp, =UART0_BASE -+ ldr \rv, =IO_ADDRESS(UART0_BASE) -+ .endm -+ -+#include -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/entry-macro.S linux-rpi/arch/arm/mach-bcm2709/include/mach/entry-macro.S ---- linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/entry-macro.S 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/entry-macro.S 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,120 @@ -+/* -+ * arch/arm/mach-bcm2708/include/mach/entry-macro.S -+ * -+ * Low-level IRQ helper macros for BCM2708 platforms -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#include -+#include -+ -+ .macro arch_ret_to_user, tmp1, tmp2 -+ .endm -+ -+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp -+ -+ /* get core number */ -+ mrc p15, 0, \base, c0, c0, 5 -+ ubfx \base, \base, #0, #2 -+ -+ /* get core's local interrupt controller */ -+ ldr \irqstat, = __io_address(ARM_LOCAL_IRQ_PENDING0) @ local interrupt source -+ add \irqstat, \irqstat, \base, lsl #2 -+ ldr \tmp, [\irqstat] -+#ifdef CONFIG_SMP -+ /* test for mailbox0 (IPI) interrupt */ -+ tst \tmp, #0x10 -+ beq 1030f -+ -+ /* get core's mailbox interrupt control */ -+ ldr \irqstat, = __io_address(ARM_LOCAL_MAILBOX0_CLR0) @ mbox_clr -+ add \irqstat, \irqstat, \base, lsl #4 -+ ldr \tmp, [\irqstat] -+ clz \tmp, \tmp -+ rsb \irqnr, \tmp, #31 -+ mov \tmp, #1 -+ lsl \tmp, \irqnr -+ str \tmp, [\irqstat] @ clear interrupt source -+ dsb -+ mov r1, sp -+ adr lr, BSYM(1b) -+ b do_IPI -+#endif -+1030: -+ /* check gpu interrupt */ -+ tst \tmp, #0x100 -+ beq 1040f -+ -+ ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE) -+ /* get masked status */ -+ ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)] -+ mov \irqnr, #(ARM_IRQ0_BASE + 31) -+ and \tmp, \irqstat, #0x300 @ save bits 8 and 9 -+ /* clear bits 8 and 9, and test */ -+ bics \irqstat, \irqstat, #0x300 -+ bne 1010f -+ -+ tst \tmp, #0x100 -+ ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)] -+ movne \irqnr, #(ARM_IRQ1_BASE + 31) -+ @ Mask out the interrupts also present in PEND0 - see SW-5809 -+ bicne \irqstat, #((1<<7) | (1<<9) | (1<<10)) -+ bicne \irqstat, #((1<<18) | (1<<19)) -+ bne 1010f -+ -+ tst \tmp, #0x200 -+ ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)] -+ movne \irqnr, #(ARM_IRQ2_BASE + 31) -+ @ Mask out the interrupts also present in PEND0 - see SW-5809 -+ bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25)) -+ bicne \irqstat, #((1<<30)) -+ beq 1020f -+1010: -+ @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1)) -+ sub \tmp, \irqstat, #1 -+ eor \irqstat, \irqstat, \tmp -+ clz \tmp, \irqstat -+ sub \irqnr, \tmp -+ b 1050f -+1040: -+ cmp \tmp, #0 -+ beq 1020f -+ -+ /* handle local (e.g. timer) interrupts */ -+ @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1)) -+ mov \irqnr, #(ARM_IRQ_LOCAL_BASE + 31) -+ sub \irqstat, \tmp, #1 -+ eor \irqstat, \irqstat, \tmp -+ clz \tmp, \irqstat -+ sub \irqnr, \tmp -+1050: -+ mov r1, sp -+ @ -+ @ routine called with r0 = irq number, r1 = struct pt_regs * -+ @ -+ adr lr, BSYM(1b) -+ b asm_do_IRQ -+ -+1020: @ EQ will be set if no irqs pending -+ .endm -+ -+/* -+ * Interrupt handling. Preserves r7, r8, r9 -+ */ -+ .macro arch_irq_handler_default -+1: get_irqnr_and_base r0, r2, r6, lr -+ .endm -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/frc.h linux-rpi/arch/arm/mach-bcm2709/include/mach/frc.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/frc.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/frc.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,38 @@ -+/* -+ * arch/arm/mach-bcm2708/include/mach/timex.h -+ * -+ * BCM2708 free running counter (timer) -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef _MACH_FRC_H -+#define _MACH_FRC_H -+ -+#define FRC_TICK_RATE (1000000) -+ -+/*! Free running counter incrementing at the CLOCK_TICK_RATE -+ (slightly faster than frc_clock_ticks63() -+ */ -+extern unsigned long frc_clock_ticks32(void); -+ -+/*! Free running counter incrementing at the CLOCK_TICK_RATE -+ * Note - top bit should be ignored (see cnt32_to_63) -+ */ -+extern unsigned long long frc_clock_ticks63(void); -+ -+#endif -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/gpio.h linux-rpi/arch/arm/mach-bcm2709/include/mach/gpio.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/gpio.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/gpio.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,17 @@ -+/* -+ * arch/arm/mach-bcm2708/include/mach/gpio.h -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#ifndef __ASM_ARCH_GPIO_H -+#define __ASM_ARCH_GPIO_H -+ -+#define BCM2708_NR_GPIOS 54 // number of gpio lines -+ -+#define gpio_to_irq(x) ((x) + GPIO_IRQ_START) -+#define irq_to_gpio(x) ((x) - GPIO_IRQ_START) -+ -+#endif -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/hardware.h linux-rpi/arch/arm/mach-bcm2709/include/mach/hardware.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/hardware.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/hardware.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,28 @@ -+/* -+ * arch/arm/mach-bcm2708/include/mach/hardware.h -+ * -+ * This file contains the hardware definitions of the BCM2708 devices. -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#ifndef __ASM_ARCH_HARDWARE_H -+#define __ASM_ARCH_HARDWARE_H -+ -+#include -+#include -+ -+#endif -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/io.h linux-rpi/arch/arm/mach-bcm2709/include/mach/io.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/io.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/io.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,27 @@ -+/* -+ * arch/arm/mach-bcm2708/include/mach/io.h -+ * -+ * Copyright (C) 2003 ARM Limited -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#ifndef __ASM_ARM_ARCH_IO_H -+#define __ASM_ARM_ARCH_IO_H -+ -+#define IO_SPACE_LIMIT 0xffffffff -+ -+#define __io(a) __typesafe_io(a) -+ -+#endif -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/irqs.h linux-rpi/arch/arm/mach-bcm2709/include/mach/irqs.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/irqs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/irqs.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,225 @@ -+/* -+ * arch/arm/mach-bcm2708/include/mach/irqs.h -+ * -+ * Copyright (C) 2010 Broadcom -+ * Copyright (C) 2003 ARM Limited -+ * Copyright (C) 2000 Deep Blue Solutions Ltd. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef _BCM2708_IRQS_H_ -+#define _BCM2708_IRQS_H_ -+ -+#include -+ -+/* -+ * IRQ interrupts definitions are the same as the INT definitions -+ * held within platform.h -+ */ -+#define IRQ_ARMCTRL_START 0 -+#define IRQ_TIMER0 (IRQ_ARMCTRL_START + INTERRUPT_TIMER0) -+#define IRQ_TIMER1 (IRQ_ARMCTRL_START + INTERRUPT_TIMER1) -+#define IRQ_TIMER2 (IRQ_ARMCTRL_START + INTERRUPT_TIMER2) -+#define IRQ_TIMER3 (IRQ_ARMCTRL_START + INTERRUPT_TIMER3) -+#define IRQ_CODEC0 (IRQ_ARMCTRL_START + INTERRUPT_CODEC0) -+#define IRQ_CODEC1 (IRQ_ARMCTRL_START + INTERRUPT_CODEC1) -+#define IRQ_CODEC2 (IRQ_ARMCTRL_START + INTERRUPT_CODEC2) -+#define IRQ_JPEG (IRQ_ARMCTRL_START + INTERRUPT_JPEG) -+#define IRQ_ISP (IRQ_ARMCTRL_START + INTERRUPT_ISP) -+#define IRQ_USB (IRQ_ARMCTRL_START + INTERRUPT_USB) -+#define IRQ_3D (IRQ_ARMCTRL_START + INTERRUPT_3D) -+#define IRQ_TRANSPOSER (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER) -+#define IRQ_MULTICORESYNC0 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0) -+#define IRQ_MULTICORESYNC1 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1) -+#define IRQ_MULTICORESYNC2 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2) -+#define IRQ_MULTICORESYNC3 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3) -+#define IRQ_DMA0 (IRQ_ARMCTRL_START + INTERRUPT_DMA0) -+#define IRQ_DMA1 (IRQ_ARMCTRL_START + INTERRUPT_DMA1) -+#define IRQ_DMA2 (IRQ_ARMCTRL_START + INTERRUPT_DMA2) -+#define IRQ_DMA3 (IRQ_ARMCTRL_START + INTERRUPT_DMA3) -+#define IRQ_DMA4 (IRQ_ARMCTRL_START + INTERRUPT_DMA4) -+#define IRQ_DMA5 (IRQ_ARMCTRL_START + INTERRUPT_DMA5) -+#define IRQ_DMA6 (IRQ_ARMCTRL_START + INTERRUPT_DMA6) -+#define IRQ_DMA7 (IRQ_ARMCTRL_START + INTERRUPT_DMA7) -+#define IRQ_DMA8 (IRQ_ARMCTRL_START + INTERRUPT_DMA8) -+#define IRQ_DMA9 (IRQ_ARMCTRL_START + INTERRUPT_DMA9) -+#define IRQ_DMA10 (IRQ_ARMCTRL_START + INTERRUPT_DMA10) -+#define IRQ_DMA11 (IRQ_ARMCTRL_START + INTERRUPT_DMA11) -+#define IRQ_DMA12 (IRQ_ARMCTRL_START + INTERRUPT_DMA12) -+#define IRQ_AUX (IRQ_ARMCTRL_START + INTERRUPT_AUX) -+#define IRQ_ARM (IRQ_ARMCTRL_START + INTERRUPT_ARM) -+#define IRQ_VPUDMA (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA) -+#define IRQ_HOSTPORT (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT) -+#define IRQ_VIDEOSCALER (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER) -+#define IRQ_CCP2TX (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX) -+#define IRQ_SDC (IRQ_ARMCTRL_START + INTERRUPT_SDC) -+#define IRQ_DSI0 (IRQ_ARMCTRL_START + INTERRUPT_DSI0) -+#define IRQ_AVE (IRQ_ARMCTRL_START + INTERRUPT_AVE) -+#define IRQ_CAM0 (IRQ_ARMCTRL_START + INTERRUPT_CAM0) -+#define IRQ_CAM1 (IRQ_ARMCTRL_START + INTERRUPT_CAM1) -+#define IRQ_HDMI0 (IRQ_ARMCTRL_START + INTERRUPT_HDMI0) -+#define IRQ_HDMI1 (IRQ_ARMCTRL_START + INTERRUPT_HDMI1) -+#define IRQ_PIXELVALVE1 (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1) -+#define IRQ_I2CSPISLV (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV) -+#define IRQ_DSI1 (IRQ_ARMCTRL_START + INTERRUPT_DSI1) -+#define IRQ_PWA0 (IRQ_ARMCTRL_START + INTERRUPT_PWA0) -+#define IRQ_PWA1 (IRQ_ARMCTRL_START + INTERRUPT_PWA1) -+#define IRQ_CPR (IRQ_ARMCTRL_START + INTERRUPT_CPR) -+#define IRQ_SMI (IRQ_ARMCTRL_START + INTERRUPT_SMI) -+#define IRQ_GPIO0 (IRQ_ARMCTRL_START + INTERRUPT_GPIO0) -+#define IRQ_GPIO1 (IRQ_ARMCTRL_START + INTERRUPT_GPIO1) -+#define IRQ_GPIO2 (IRQ_ARMCTRL_START + INTERRUPT_GPIO2) -+#define IRQ_GPIO3 (IRQ_ARMCTRL_START + INTERRUPT_GPIO3) -+#define IRQ_I2C (IRQ_ARMCTRL_START + INTERRUPT_I2C) -+#define IRQ_SPI (IRQ_ARMCTRL_START + INTERRUPT_SPI) -+#define IRQ_I2SPCM (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM) -+#define IRQ_SDIO (IRQ_ARMCTRL_START + INTERRUPT_SDIO) -+#define IRQ_UART (IRQ_ARMCTRL_START + INTERRUPT_UART) -+#define IRQ_SLIMBUS (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS) -+#define IRQ_VEC (IRQ_ARMCTRL_START + INTERRUPT_VEC) -+#define IRQ_CPG (IRQ_ARMCTRL_START + INTERRUPT_CPG) -+#define IRQ_RNG (IRQ_ARMCTRL_START + INTERRUPT_RNG) -+#define IRQ_ARASANSDIO (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO) -+#define IRQ_AVSPMON (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON) -+ -+#define IRQ_ARM_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER) -+#define IRQ_ARM_MAILBOX (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX) -+#define IRQ_ARM_DOORBELL_0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0) -+#define IRQ_ARM_DOORBELL_1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1) -+#define IRQ_VPU0_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED) -+#define IRQ_VPU1_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED) -+#define IRQ_ILLEGAL_TYPE0 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0) -+#define IRQ_ILLEGAL_TYPE1 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1) -+#define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1) -+#define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2) -+ -+#define IRQ_ARM_LOCAL_CNTPSIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPSIRQ) -+#define IRQ_ARM_LOCAL_CNTPNSIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPNSIRQ) -+#define IRQ_ARM_LOCAL_CNTHPIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTHPIRQ) -+#define IRQ_ARM_LOCAL_CNTVIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTVIRQ) -+#define IRQ_ARM_LOCAL_MAILBOX0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX0) -+#define IRQ_ARM_LOCAL_MAILBOX1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX1) -+#define IRQ_ARM_LOCAL_MAILBOX2 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX2) -+#define IRQ_ARM_LOCAL_MAILBOX3 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX3) -+#define IRQ_ARM_LOCAL_GPU_FAST (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_GPU_FAST) -+#define IRQ_ARM_LOCAL_PMU_FAST (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_PMU_FAST) -+#define IRQ_ARM_LOCAL_ZERO (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_ZERO) -+#define IRQ_ARM_LOCAL_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_TIMER) -+ -+#define FIQ_START HARD_IRQS -+ -+/* -+ * FIQ interrupts definitions are the same as the INT definitions. -+ */ -+#define FIQ_TIMER0 (FIQ_START+INTERRUPT_TIMER0) -+#define FIQ_TIMER1 (FIQ_START+INTERRUPT_TIMER1) -+#define FIQ_TIMER2 (FIQ_START+INTERRUPT_TIMER2) -+#define FIQ_TIMER3 (FIQ_START+INTERRUPT_TIMER3) -+#define FIQ_CODEC0 (FIQ_START+INTERRUPT_CODEC0) -+#define FIQ_CODEC1 (FIQ_START+INTERRUPT_CODEC1) -+#define FIQ_CODEC2 (FIQ_START+INTERRUPT_CODEC2) -+#define FIQ_JPEG (FIQ_START+INTERRUPT_JPEG) -+#define FIQ_ISP (FIQ_START+INTERRUPT_ISP) -+#define FIQ_USB (FIQ_START+INTERRUPT_USB) -+#define FIQ_3D (FIQ_START+INTERRUPT_3D) -+#define FIQ_TRANSPOSER (FIQ_START+INTERRUPT_TRANSPOSER) -+#define FIQ_MULTICORESYNC0 (FIQ_START+INTERRUPT_MULTICORESYNC0) -+#define FIQ_MULTICORESYNC1 (FIQ_START+INTERRUPT_MULTICORESYNC1) -+#define FIQ_MULTICORESYNC2 (FIQ_START+INTERRUPT_MULTICORESYNC2) -+#define FIQ_MULTICORESYNC3 (FIQ_START+INTERRUPT_MULTICORESYNC3) -+#define FIQ_DMA0 (FIQ_START+INTERRUPT_DMA0) -+#define FIQ_DMA1 (FIQ_START+INTERRUPT_DMA1) -+#define FIQ_DMA2 (FIQ_START+INTERRUPT_DMA2) -+#define FIQ_DMA3 (FIQ_START+INTERRUPT_DMA3) -+#define FIQ_DMA4 (FIQ_START+INTERRUPT_DMA4) -+#define FIQ_DMA5 (FIQ_START+INTERRUPT_DMA5) -+#define FIQ_DMA6 (FIQ_START+INTERRUPT_DMA6) -+#define FIQ_DMA7 (FIQ_START+INTERRUPT_DMA7) -+#define FIQ_DMA8 (FIQ_START+INTERRUPT_DMA8) -+#define FIQ_DMA9 (FIQ_START+INTERRUPT_DMA9) -+#define FIQ_DMA10 (FIQ_START+INTERRUPT_DMA10) -+#define FIQ_DMA11 (FIQ_START+INTERRUPT_DMA11) -+#define FIQ_DMA12 (FIQ_START+INTERRUPT_DMA12) -+#define FIQ_AUX (FIQ_START+INTERRUPT_AUX) -+#define FIQ_ARM (FIQ_START+INTERRUPT_ARM) -+#define FIQ_VPUDMA (FIQ_START+INTERRUPT_VPUDMA) -+#define FIQ_HOSTPORT (FIQ_START+INTERRUPT_HOSTPORT) -+#define FIQ_VIDEOSCALER (FIQ_START+INTERRUPT_VIDEOSCALER) -+#define FIQ_CCP2TX (FIQ_START+INTERRUPT_CCP2TX) -+#define FIQ_SDC (FIQ_START+INTERRUPT_SDC) -+#define FIQ_DSI0 (FIQ_START+INTERRUPT_DSI0) -+#define FIQ_AVE (FIQ_START+INTERRUPT_AVE) -+#define FIQ_CAM0 (FIQ_START+INTERRUPT_CAM0) -+#define FIQ_CAM1 (FIQ_START+INTERRUPT_CAM1) -+#define FIQ_HDMI0 (FIQ_START+INTERRUPT_HDMI0) -+#define FIQ_HDMI1 (FIQ_START+INTERRUPT_HDMI1) -+#define FIQ_PIXELVALVE1 (FIQ_START+INTERRUPT_PIXELVALVE1) -+#define FIQ_I2CSPISLV (FIQ_START+INTERRUPT_I2CSPISLV) -+#define FIQ_DSI1 (FIQ_START+INTERRUPT_DSI1) -+#define FIQ_PWA0 (FIQ_START+INTERRUPT_PWA0) -+#define FIQ_PWA1 (FIQ_START+INTERRUPT_PWA1) -+#define FIQ_CPR (FIQ_START+INTERRUPT_CPR) -+#define FIQ_SMI (FIQ_START+INTERRUPT_SMI) -+#define FIQ_GPIO0 (FIQ_START+INTERRUPT_GPIO0) -+#define FIQ_GPIO1 (FIQ_START+INTERRUPT_GPIO1) -+#define FIQ_GPIO2 (FIQ_START+INTERRUPT_GPIO2) -+#define FIQ_GPIO3 (FIQ_START+INTERRUPT_GPIO3) -+#define FIQ_I2C (FIQ_START+INTERRUPT_I2C) -+#define FIQ_SPI (FIQ_START+INTERRUPT_SPI) -+#define FIQ_I2SPCM (FIQ_START+INTERRUPT_I2SPCM) -+#define FIQ_SDIO (FIQ_START+INTERRUPT_SDIO) -+#define FIQ_UART (FIQ_START+INTERRUPT_UART) -+#define FIQ_SLIMBUS (FIQ_START+INTERRUPT_SLIMBUS) -+#define FIQ_VEC (FIQ_START+INTERRUPT_VEC) -+#define FIQ_CPG (FIQ_START+INTERRUPT_CPG) -+#define FIQ_RNG (FIQ_START+INTERRUPT_RNG) -+#define FIQ_ARASANSDIO (FIQ_START+INTERRUPT_ARASANSDIO) -+#define FIQ_AVSPMON (FIQ_START+INTERRUPT_AVSPMON) -+ -+#define FIQ_ARM_TIMER (FIQ_START+INTERRUPT_ARM_TIMER) -+#define FIQ_ARM_MAILBOX (FIQ_START+INTERRUPT_ARM_MAILBOX) -+#define FIQ_ARM_DOORBELL_0 (FIQ_START+INTERRUPT_ARM_DOORBELL_0) -+#define FIQ_ARM_DOORBELL_1 (FIQ_START+INTERRUPT_ARM_DOORBELL_1) -+#define FIQ_VPU0_HALTED (FIQ_START+INTERRUPT_VPU0_HALTED) -+#define FIQ_VPU1_HALTED (FIQ_START+INTERRUPT_VPU1_HALTED) -+#define FIQ_ILLEGAL_TYPE0 (FIQ_START+INTERRUPT_ILLEGAL_TYPE0) -+#define FIQ_ILLEGAL_TYPE1 (FIQ_START+INTERRUPT_ILLEGAL_TYPE1) -+#define FIQ_PENDING1 (FIQ_START+INTERRUPT_PENDING1) -+#define FIQ_PENDING2 (FIQ_START+INTERRUPT_PENDING2) -+ -+#define FIQ_ARM_LOCAL_CNTPSIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPSIRQ) -+#define FIQ_ARM_LOCAL_CNTPNSIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPNSIRQ) -+#define FIQ_ARM_LOCAL_CNTHPIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTHPIRQ) -+#define FIQ_ARM_LOCAL_CNTVIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTVIRQ) -+#define FIQ_ARM_LOCAL_MAILBOX0 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX0) -+#define FIQ_ARM_LOCAL_MAILBOX1 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX1) -+#define FIQ_ARM_LOCAL_MAILBOX2 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX2) -+#define FIQ_ARM_LOCAL_MAILBOX3 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX3) -+#define FIQ_ARM_LOCAL_GPU_FAST (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_GPU_FAST) -+#define FIQ_ARM_LOCAL_PMU_FAST (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_PMU_FAST) -+#define FIQ_ARM_LOCAL_ZERO (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_ZERO) -+#define FIQ_ARM_LOCAL_TIMER (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_TIMER) -+ -+#define HARD_IRQS (128) -+#define FIQ_IRQS (128) -+#define GPIO_IRQ_START (HARD_IRQS + FIQ_IRQS) -+#define GPIO_IRQS (32*5) -+#define SPARE_ALLOC_IRQS 64 -+#define BCM2708_ALLOC_IRQS (HARD_IRQS+FIQ_IRQS+GPIO_IRQS+SPARE_ALLOC_IRQS) -+#define FREE_IRQS 128 -+#define NR_IRQS (BCM2708_ALLOC_IRQS+FREE_IRQS) -+ -+#endif /* _BCM2708_IRQS_H_ */ -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/memory.h linux-rpi/arch/arm/mach-bcm2709/include/mach/memory.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/memory.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/memory.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,57 @@ -+/* -+ * arch/arm/mach-bcm2708/include/mach/memory.h -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#ifndef __ASM_ARCH_MEMORY_H -+#define __ASM_ARCH_MEMORY_H -+ -+/* Memory overview: -+ -+ [ARMcore] <--virtual addr--> -+ [ARMmmu] <--physical addr--> -+ [GERTmap] <--bus add--> -+ [VCperiph] -+ -+*/ -+ -+/* -+ * Physical DRAM offset. -+ */ -+#define BCM_PLAT_PHYS_OFFSET UL(0x00000000) -+#define VC_ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */ -+ -+#ifdef CONFIG_BCM2708_NOL2CACHE -+ #define _REAL_BUS_OFFSET UL(0xC0000000) /* don't use L1 or L2 caches */ -+#else -+ #define _REAL_BUS_OFFSET UL(0x40000000) /* use L2 cache */ -+#endif -+ -+/* We're using the memory at 64M in the VideoCore for Linux - this adjustment -+ * will provide the offset into this area as well as setting the bits that -+ * stop the L1 and L2 cache from being used -+ * -+ * WARNING: this only works because the ARM is given memory at a fixed location -+ * (ARMMEM_OFFSET) -+ */ -+#define BUS_OFFSET (VC_ARMMEM_OFFSET + _REAL_BUS_OFFSET) -+#define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET)) -+#define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET)) -+#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET)) -+#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET)) -+ -+#endif -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/platform.h linux-rpi/arch/arm/mach-bcm2709/include/mach/platform.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/platform.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/platform.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,227 @@ -+/* -+ * arch/arm/mach-bcm2708/include/mach/platform.h -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef _BCM2708_PLATFORM_H -+#define _BCM2708_PLATFORM_H -+ -+ -+/* macros to get at IO space when running virtually */ -+#define IO_ADDRESS(x) (((x) & 0x00ffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000) -+ -+#define __io_address(n) IOMEM(IO_ADDRESS(n)) -+ -+ -+/* -+ * SDRAM -+ */ -+#define BCM2708_SDRAM_BASE 0x00000000 -+ -+/* -+ * Logic expansion modules -+ * -+ */ -+ -+ -+/* ------------------------------------------------------------------------ -+ * BCM2708 ARMCTRL Registers -+ * ------------------------------------------------------------------------ -+ */ -+ -+#define HW_REGISTER_RW(addr) (addr) -+#define HW_REGISTER_RO(addr) (addr) -+ -+#include "arm_control.h" -+#undef ARM_BASE -+ -+/* -+ * Definitions and addresses for the ARM CONTROL logic -+ * This file is manually generated. -+ */ -+ -+#define BCM2708_PERI_BASE 0x3F000000 -+#define IC0_BASE (BCM2708_PERI_BASE + 0x2000) -+#define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */ -+#define MPHI_BASE (BCM2708_PERI_BASE + 0x6000) /* Message -based Parallel Host Interface */ -+#define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */ -+#define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */ -+#define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */ -+#define PCM_CLOCK_BASE (BCM2708_PERI_BASE + 0x101098) /* PCM Clock */ -+#define RNG_BASE (BCM2708_PERI_BASE + 0x104000) /* Hardware RNG */ -+#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */ -+#define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */ -+#define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */ -+#define I2S_BASE (BCM2708_PERI_BASE + 0x203000) /* I2S */ -+#define SPI0_BASE (BCM2708_PERI_BASE + 0x204000) /* SPI0 */ -+#define BSC0_BASE (BCM2708_PERI_BASE + 0x205000) /* BSC0 I2C/TWI */ -+#define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */ -+#define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */ -+#define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */ -+#define BSC1_BASE (BCM2708_PERI_BASE + 0x804000) /* BSC1 I2C/TWI */ -+#define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */ -+#define MCORE_BASE (BCM2708_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/ -+ -+#define ARMCTRL_BASE (ARM_BASE + 0x000) -+#define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */ -+#define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */ -+#define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */ -+#define ARMCTRL_0_BELL_BASE (ARMCTRL_0_SBM_BASE + 0x40) /* User 0 (ARM)'s Doorbell */ -+#define ARMCTRL_0_MAIL0_BASE (ARMCTRL_0_SBM_BASE + 0x80) /* User 0 (ARM)'s Mailbox 0 */ -+ -+ -+/* -+ * Interrupt assignments -+ */ -+ -+#define ARM_IRQ1_BASE 0 -+#define INTERRUPT_TIMER0 (ARM_IRQ1_BASE + 0) -+#define INTERRUPT_TIMER1 (ARM_IRQ1_BASE + 1) -+#define INTERRUPT_TIMER2 (ARM_IRQ1_BASE + 2) -+#define INTERRUPT_TIMER3 (ARM_IRQ1_BASE + 3) -+#define INTERRUPT_CODEC0 (ARM_IRQ1_BASE + 4) -+#define INTERRUPT_CODEC1 (ARM_IRQ1_BASE + 5) -+#define INTERRUPT_CODEC2 (ARM_IRQ1_BASE + 6) -+#define INTERRUPT_VC_JPEG (ARM_IRQ1_BASE + 7) -+#define INTERRUPT_ISP (ARM_IRQ1_BASE + 8) -+#define INTERRUPT_VC_USB (ARM_IRQ1_BASE + 9) -+#define INTERRUPT_VC_3D (ARM_IRQ1_BASE + 10) -+#define INTERRUPT_TRANSPOSER (ARM_IRQ1_BASE + 11) -+#define INTERRUPT_MULTICORESYNC0 (ARM_IRQ1_BASE + 12) -+#define INTERRUPT_MULTICORESYNC1 (ARM_IRQ1_BASE + 13) -+#define INTERRUPT_MULTICORESYNC2 (ARM_IRQ1_BASE + 14) -+#define INTERRUPT_MULTICORESYNC3 (ARM_IRQ1_BASE + 15) -+#define INTERRUPT_DMA0 (ARM_IRQ1_BASE + 16) -+#define INTERRUPT_DMA1 (ARM_IRQ1_BASE + 17) -+#define INTERRUPT_VC_DMA2 (ARM_IRQ1_BASE + 18) -+#define INTERRUPT_VC_DMA3 (ARM_IRQ1_BASE + 19) -+#define INTERRUPT_DMA4 (ARM_IRQ1_BASE + 20) -+#define INTERRUPT_DMA5 (ARM_IRQ1_BASE + 21) -+#define INTERRUPT_DMA6 (ARM_IRQ1_BASE + 22) -+#define INTERRUPT_DMA7 (ARM_IRQ1_BASE + 23) -+#define INTERRUPT_DMA8 (ARM_IRQ1_BASE + 24) -+#define INTERRUPT_DMA9 (ARM_IRQ1_BASE + 25) -+#define INTERRUPT_DMA10 (ARM_IRQ1_BASE + 26) -+#define INTERRUPT_DMA11 (ARM_IRQ1_BASE + 27) -+#define INTERRUPT_DMA12 (ARM_IRQ1_BASE + 28) -+#define INTERRUPT_AUX (ARM_IRQ1_BASE + 29) -+#define INTERRUPT_ARM (ARM_IRQ1_BASE + 30) -+#define INTERRUPT_VPUDMA (ARM_IRQ1_BASE + 31) -+ -+#define ARM_IRQ2_BASE 32 -+#define INTERRUPT_HOSTPORT (ARM_IRQ2_BASE + 0) -+#define INTERRUPT_VIDEOSCALER (ARM_IRQ2_BASE + 1) -+#define INTERRUPT_CCP2TX (ARM_IRQ2_BASE + 2) -+#define INTERRUPT_SDC (ARM_IRQ2_BASE + 3) -+#define INTERRUPT_DSI0 (ARM_IRQ2_BASE + 4) -+#define INTERRUPT_AVE (ARM_IRQ2_BASE + 5) -+#define INTERRUPT_CAM0 (ARM_IRQ2_BASE + 6) -+#define INTERRUPT_CAM1 (ARM_IRQ2_BASE + 7) -+#define INTERRUPT_HDMI0 (ARM_IRQ2_BASE + 8) -+#define INTERRUPT_HDMI1 (ARM_IRQ2_BASE + 9) -+#define INTERRUPT_PIXELVALVE1 (ARM_IRQ2_BASE + 10) -+#define INTERRUPT_I2CSPISLV (ARM_IRQ2_BASE + 11) -+#define INTERRUPT_DSI1 (ARM_IRQ2_BASE + 12) -+#define INTERRUPT_PWA0 (ARM_IRQ2_BASE + 13) -+#define INTERRUPT_PWA1 (ARM_IRQ2_BASE + 14) -+#define INTERRUPT_CPR (ARM_IRQ2_BASE + 15) -+#define INTERRUPT_SMI (ARM_IRQ2_BASE + 16) -+#define INTERRUPT_GPIO0 (ARM_IRQ2_BASE + 17) -+#define INTERRUPT_GPIO1 (ARM_IRQ2_BASE + 18) -+#define INTERRUPT_GPIO2 (ARM_IRQ2_BASE + 19) -+#define INTERRUPT_GPIO3 (ARM_IRQ2_BASE + 20) -+#define INTERRUPT_VC_I2C (ARM_IRQ2_BASE + 21) -+#define INTERRUPT_VC_SPI (ARM_IRQ2_BASE + 22) -+#define INTERRUPT_VC_I2SPCM (ARM_IRQ2_BASE + 23) -+#define INTERRUPT_VC_SDIO (ARM_IRQ2_BASE + 24) -+#define INTERRUPT_VC_UART (ARM_IRQ2_BASE + 25) -+#define INTERRUPT_SLIMBUS (ARM_IRQ2_BASE + 26) -+#define INTERRUPT_VEC (ARM_IRQ2_BASE + 27) -+#define INTERRUPT_CPG (ARM_IRQ2_BASE + 28) -+#define INTERRUPT_RNG (ARM_IRQ2_BASE + 29) -+#define INTERRUPT_VC_ARASANSDIO (ARM_IRQ2_BASE + 30) -+#define INTERRUPT_AVSPMON (ARM_IRQ2_BASE + 31) -+ -+#define ARM_IRQ0_BASE 64 -+#define INTERRUPT_ARM_TIMER (ARM_IRQ0_BASE + 0) -+#define INTERRUPT_ARM_MAILBOX (ARM_IRQ0_BASE + 1) -+#define INTERRUPT_ARM_DOORBELL_0 (ARM_IRQ0_BASE + 2) -+#define INTERRUPT_ARM_DOORBELL_1 (ARM_IRQ0_BASE + 3) -+#define INTERRUPT_VPU0_HALTED (ARM_IRQ0_BASE + 4) -+#define INTERRUPT_VPU1_HALTED (ARM_IRQ0_BASE + 5) -+#define INTERRUPT_ILLEGAL_TYPE0 (ARM_IRQ0_BASE + 6) -+#define INTERRUPT_ILLEGAL_TYPE1 (ARM_IRQ0_BASE + 7) -+#define INTERRUPT_PENDING1 (ARM_IRQ0_BASE + 8) -+#define INTERRUPT_PENDING2 (ARM_IRQ0_BASE + 9) -+#define INTERRUPT_JPEG (ARM_IRQ0_BASE + 10) -+#define INTERRUPT_USB (ARM_IRQ0_BASE + 11) -+#define INTERRUPT_3D (ARM_IRQ0_BASE + 12) -+#define INTERRUPT_DMA2 (ARM_IRQ0_BASE + 13) -+#define INTERRUPT_DMA3 (ARM_IRQ0_BASE + 14) -+#define INTERRUPT_I2C (ARM_IRQ0_BASE + 15) -+#define INTERRUPT_SPI (ARM_IRQ0_BASE + 16) -+#define INTERRUPT_I2SPCM (ARM_IRQ0_BASE + 17) -+#define INTERRUPT_SDIO (ARM_IRQ0_BASE + 18) -+#define INTERRUPT_UART (ARM_IRQ0_BASE + 19) -+#define INTERRUPT_ARASANSDIO (ARM_IRQ0_BASE + 20) -+ -+#define ARM_IRQ_LOCAL_BASE 96 -+#define INTERRUPT_ARM_LOCAL_CNTPSIRQ (ARM_IRQ_LOCAL_BASE + 0) -+#define INTERRUPT_ARM_LOCAL_CNTPNSIRQ (ARM_IRQ_LOCAL_BASE + 1) -+#define INTERRUPT_ARM_LOCAL_CNTHPIRQ (ARM_IRQ_LOCAL_BASE + 2) -+#define INTERRUPT_ARM_LOCAL_CNTVIRQ (ARM_IRQ_LOCAL_BASE + 3) -+#define INTERRUPT_ARM_LOCAL_MAILBOX0 (ARM_IRQ_LOCAL_BASE + 4) -+#define INTERRUPT_ARM_LOCAL_MAILBOX1 (ARM_IRQ_LOCAL_BASE + 5) -+#define INTERRUPT_ARM_LOCAL_MAILBOX2 (ARM_IRQ_LOCAL_BASE + 6) -+#define INTERRUPT_ARM_LOCAL_MAILBOX3 (ARM_IRQ_LOCAL_BASE + 7) -+#define INTERRUPT_ARM_LOCAL_GPU_FAST (ARM_IRQ_LOCAL_BASE + 8) -+#define INTERRUPT_ARM_LOCAL_PMU_FAST (ARM_IRQ_LOCAL_BASE + 9) -+#define INTERRUPT_ARM_LOCAL_ZERO (ARM_IRQ_LOCAL_BASE + 10) -+#define INTERRUPT_ARM_LOCAL_TIMER (ARM_IRQ_LOCAL_BASE + 11) -+ -+/* -+ * Watchdog -+ */ -+#define PM_RSTC (PM_BASE+0x1c) -+#define PM_RSTS (PM_BASE+0x20) -+#define PM_WDOG (PM_BASE+0x24) -+ -+#define PM_WDOG_RESET 0000000000 -+#define PM_PASSWORD 0x5a000000 -+#define PM_WDOG_TIME_SET 0x000fffff -+#define PM_RSTC_WRCFG_CLR 0xffffffcf -+#define PM_RSTC_WRCFG_SET 0x00000030 -+#define PM_RSTC_WRCFG_FULL_RESET 0x00000020 -+#define PM_RSTC_RESET 0x00000102 -+ -+#define PM_RSTS_HADPOR_SET 0x00001000 -+#define PM_RSTS_HADSRH_SET 0x00000400 -+#define PM_RSTS_HADSRF_SET 0x00000200 -+#define PM_RSTS_HADSRQ_SET 0x00000100 -+#define PM_RSTS_HADWRH_SET 0x00000040 -+#define PM_RSTS_HADWRF_SET 0x00000020 -+#define PM_RSTS_HADWRQ_SET 0x00000010 -+#define PM_RSTS_HADDRH_SET 0x00000004 -+#define PM_RSTS_HADDRF_SET 0x00000002 -+#define PM_RSTS_HADDRQ_SET 0x00000001 -+ -+#define UART0_CLOCK 3000000 -+ -+#endif -+ -+/* END */ -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/system.h linux-rpi/arch/arm/mach-bcm2709/include/mach/system.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/system.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/system.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,38 @@ -+/* -+ * arch/arm/mach-bcm2708/include/mach/system.h -+ * -+ * Copyright (C) 2010 Broadcom -+ * Copyright (C) 2003 ARM Limited -+ * Copyright (C) 2000 Deep Blue Solutions Ltd -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#ifndef __ASM_ARCH_SYSTEM_H -+#define __ASM_ARCH_SYSTEM_H -+ -+#include -+#include -+#include -+ -+static inline void arch_idle(void) -+{ -+ /* -+ * This should do all the clock switching -+ * and wait for interrupt tricks -+ */ -+ cpu_do_idle(); -+} -+ -+#endif -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/timex.h linux-rpi/arch/arm/mach-bcm2709/include/mach/timex.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/timex.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/timex.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,23 @@ -+/* -+ * arch/arm/mach-bcm2708/include/mach/timex.h -+ * -+ * BCM2708 sysem clock frequency -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#define CLOCK_TICK_RATE (1000000) -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/uncompress.h linux-rpi/arch/arm/mach-bcm2709/include/mach/uncompress.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/uncompress.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/uncompress.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,84 @@ -+/* -+ * arch/arm/mach-bcn2708/include/mach/uncompress.h -+ * -+ * Copyright (C) 2010 Broadcom -+ * Copyright (C) 2003 ARM Limited -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include -+#include -+#include -+ -+#define UART_BAUD 115200 -+ -+#define BCM2708_UART_DR __io(UART0_BASE + UART01x_DR) -+#define BCM2708_UART_FR __io(UART0_BASE + UART01x_FR) -+#define BCM2708_UART_IBRD __io(UART0_BASE + UART011_IBRD) -+#define BCM2708_UART_FBRD __io(UART0_BASE + UART011_FBRD) -+#define BCM2708_UART_LCRH __io(UART0_BASE + UART011_LCRH) -+#define BCM2708_UART_CR __io(UART0_BASE + UART011_CR) -+ -+/* -+ * This does not append a newline -+ */ -+static inline void putc(int c) -+{ -+ while (__raw_readl(BCM2708_UART_FR) & UART01x_FR_TXFF) -+ barrier(); -+ -+ __raw_writel(c, BCM2708_UART_DR); -+} -+ -+static inline void flush(void) -+{ -+ int fr; -+ -+ do { -+ fr = __raw_readl(BCM2708_UART_FR); -+ barrier(); -+ } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE); -+} -+ -+static inline void arch_decomp_setup(void) -+{ -+ int temp, div, rem, frac; -+ -+ temp = 16 * UART_BAUD; -+ div = UART0_CLOCK / temp; -+ rem = UART0_CLOCK % temp; -+ temp = (8 * rem) / UART_BAUD; -+ frac = (temp >> 1) + (temp & 1); -+ -+ /* Make sure the UART is disabled before we start */ -+ __raw_writel(0, BCM2708_UART_CR); -+ -+ /* Set the baud rate */ -+ __raw_writel(div, BCM2708_UART_IBRD); -+ __raw_writel(frac, BCM2708_UART_FBRD); -+ -+ /* Set the UART to 8n1, FIFO enabled */ -+ __raw_writel(UART01x_LCRH_WLEN_8 | UART01x_LCRH_FEN, BCM2708_UART_LCRH); -+ -+ /* Enable the UART */ -+ __raw_writel(UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_RXE, -+ BCM2708_UART_CR); -+} -+ -+/* -+ * nothing to do -+ */ -+#define arch_decomp_wdog() -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/vc_support.h linux-rpi/arch/arm/mach-bcm2709/include/mach/vc_support.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/vc_support.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/vc_support.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,69 @@ -+#ifndef _VC_SUPPORT_H_ -+#define _VC_SUPPORT_H_ -+ -+/* -+ * vc_support.h -+ * -+ * Created on: 25 Nov 2012 -+ * Author: Simon -+ */ -+ -+enum { -+/* -+ If a MEM_HANDLE_T is discardable, the memory manager may resize it to size -+ 0 at any time when it is not locked or retained. -+ */ -+ MEM_FLAG_DISCARDABLE = 1 << 0, -+ -+ /* -+ If a MEM_HANDLE_T is allocating (or normal), its block of memory will be -+ accessed in an allocating fashion through the cache. -+ */ -+ MEM_FLAG_NORMAL = 0 << 2, -+ MEM_FLAG_ALLOCATING = MEM_FLAG_NORMAL, -+ -+ /* -+ If a MEM_HANDLE_T is direct, its block of memory will be accessed -+ directly, bypassing the cache. -+ */ -+ MEM_FLAG_DIRECT = 1 << 2, -+ -+ /* -+ If a MEM_HANDLE_T is coherent, its block of memory will be accessed in a -+ non-allocating fashion through the cache. -+ */ -+ MEM_FLAG_COHERENT = 2 << 2, -+ -+ /* -+ If a MEM_HANDLE_T is L1-nonallocating, its block of memory will be accessed by -+ the VPU in a fashion which is allocating in L2, but only coherent in L1. -+ */ -+ MEM_FLAG_L1_NONALLOCATING = (MEM_FLAG_DIRECT | MEM_FLAG_COHERENT), -+ -+ /* -+ If a MEM_HANDLE_T is zero'd, its contents are set to 0 rather than -+ MEM_HANDLE_INVALID on allocation and resize up. -+ */ -+ MEM_FLAG_ZERO = 1 << 4, -+ -+ /* -+ If a MEM_HANDLE_T is uninitialised, it will not be reset to a defined value -+ (either zero, or all 1's) on allocation. -+ */ -+ MEM_FLAG_NO_INIT = 1 << 5, -+ -+ /* -+ Hints. -+ */ -+ MEM_FLAG_HINT_PERMALOCK = 1 << 6, /* Likely to be locked for long periods of time. */ -+}; -+ -+unsigned int AllocateVcMemory(unsigned int *pHandle, unsigned int size, unsigned int alignment, unsigned int flags); -+unsigned int ReleaseVcMemory(unsigned int handle); -+unsigned int LockVcMemory(unsigned int *pBusAddress, unsigned int handle); -+unsigned int UnlockVcMemory(unsigned int handle); -+ -+unsigned int ExecuteVcCode(unsigned int code, -+ unsigned int r0, unsigned int r1, unsigned int r2, unsigned int r3, unsigned int r4, unsigned int r5); -+ -+#endif -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/vmalloc.h linux-rpi/arch/arm/mach-bcm2709/include/mach/vmalloc.h ---- linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2709/include/mach/vmalloc.h 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,20 @@ -+/* -+ * arch/arm/mach-bcm2708/include/mach/vmalloc.h -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+#define VMALLOC_END (0xff000000) -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/Kconfig linux-rpi/arch/arm/mach-bcm2709/Kconfig ---- linux-4.1.13.orig/arch/arm/mach-bcm2709/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2709/Kconfig 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,42 @@ -+menu "Broadcom BCM2709 Implementations" -+ depends on ARCH_BCM2709 -+ -+config MACH_BCM2709 -+ bool "Broadcom BCM2709 Development Platform" -+ help -+ Include support for the Broadcom(R) BCM2709 platform. -+ -+config BCM2709_DT -+ bool "BCM2709 Device Tree support" -+ depends on MACH_BCM2709 -+ default n -+ select USE_OF -+ select ARCH_REQUIRE_GPIOLIB -+ select PINCTRL -+ select PINCTRL_BCM2835 -+ help -+ Enable Device Tree support for BCM2709 -+ -+config BCM2708_GPIO -+ bool "BCM2709 gpio support" -+ depends on MACH_BCM2709 -+ select ARCH_REQUIRE_GPIOLIB -+ default y -+ help -+ Include support for the Broadcom(R) BCM2709 gpio. -+ -+config BCM2708_NOL2CACHE -+ bool "Videocore L2 cache disable" -+ depends on MACH_BCM2709 -+ default y -+ help -+ Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt. -+ -+config BCM2708_SPIDEV -+ bool "Bind spidev to SPI0 master" -+ depends on MACH_BCM2709 -+ depends on SPI -+ default y -+ help -+ Binds spidev driver to the SPI0 master -+endmenu -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/Makefile linux-rpi/arch/arm/mach-bcm2709/Makefile ---- linux-4.1.13.orig/arch/arm/mach-bcm2709/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2709/Makefile 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,6 @@ -+# -+# Makefile for the linux kernel. -+# -+ -+obj-$(CONFIG_MACH_BCM2709) += bcm2709.o armctrl.o -+obj-$(CONFIG_BCM2708_GPIO) += bcm2708_gpio.o -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/Makefile.boot linux-rpi/arch/arm/mach-bcm2709/Makefile.boot ---- linux-4.1.13.orig/arch/arm/mach-bcm2709/Makefile.boot 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2709/Makefile.boot 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,3 @@ -+ zreladdr-y := 0x00008000 -+params_phys-y := 0x00000100 -+initrd_phys-y := 0x00800000 -diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/vc_support.c linux-rpi/arch/arm/mach-bcm2709/vc_support.c ---- linux-4.1.13.orig/arch/arm/mach-bcm2709/vc_support.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/arch/arm/mach-bcm2709/vc_support.c 2015-11-29 09:42:34.791439401 +0100 -@@ -0,0 +1,318 @@ -+/* -+ * vc_support.c -+ * -+ * Created on: 25 Nov 2012 -+ * Author: Simon -+ */ -+ -+#include -+#include -+ -+#ifdef ECLIPSE_IGNORE -+ -+#define __user -+#define __init -+#define __exit -+#define __iomem -+#define KERN_DEBUG -+#define KERN_ERR -+#define KERN_WARNING -+#define KERN_INFO -+#define _IOWR(a, b, c) b -+#define _IOW(a, b, c) b -+#define _IO(a, b) b -+ -+#endif -+ -+/****** VC MAILBOX FUNCTIONALITY ******/ -+unsigned int AllocateVcMemory(unsigned int *pHandle, unsigned int size, unsigned int alignment, unsigned int flags) -+{ -+ struct vc_msg -+ { -+ unsigned int m_msgSize; -+ unsigned int m_response; -+ -+ struct vc_tag -+ { -+ unsigned int m_tagId; -+ unsigned int m_sendBufferSize; -+ union { -+ unsigned int m_sendDataSize; -+ unsigned int m_recvDataSize; -+ }; -+ -+ struct args -+ { -+ union { -+ unsigned int m_size; -+ unsigned int m_handle; -+ }; -+ unsigned int m_alignment; -+ unsigned int m_flags; -+ } m_args; -+ } m_tag; -+ -+ unsigned int m_endTag; -+ } msg; -+ int s; -+ -+ msg.m_msgSize = sizeof(msg); -+ msg.m_response = 0; -+ msg.m_endTag = 0; -+ -+ //fill in the tag for the allocation command -+ msg.m_tag.m_tagId = 0x3000c; -+ msg.m_tag.m_sendBufferSize = 12; -+ msg.m_tag.m_sendDataSize = 12; -+ -+ //fill in our args -+ msg.m_tag.m_args.m_size = size; -+ msg.m_tag.m_args.m_alignment = alignment; -+ msg.m_tag.m_args.m_flags = flags; -+ -+ //run the command -+ s = bcm_mailbox_property(&msg, sizeof(msg)); -+ -+ if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004) -+ { -+ *pHandle = msg.m_tag.m_args.m_handle; -+ return 0; -+ } -+ else -+ { -+ printk(KERN_ERR "failed to allocate vc memory: s=%d response=%08x recv data size=%08x\n", -+ s, msg.m_response, msg.m_tag.m_recvDataSize); -+ return 1; -+ } -+} -+ -+unsigned int ReleaseVcMemory(unsigned int handle) -+{ -+ struct vc_msg -+ { -+ unsigned int m_msgSize; -+ unsigned int m_response; -+ -+ struct vc_tag -+ { -+ unsigned int m_tagId; -+ unsigned int m_sendBufferSize; -+ union { -+ unsigned int m_sendDataSize; -+ unsigned int m_recvDataSize; -+ }; -+ -+ struct args -+ { -+ union { -+ unsigned int m_handle; -+ unsigned int m_error; -+ }; -+ } m_args; -+ } m_tag; -+ -+ unsigned int m_endTag; -+ } msg; -+ int s; -+ -+ msg.m_msgSize = sizeof(msg); -+ msg.m_response = 0; -+ msg.m_endTag = 0; -+ -+ //fill in the tag for the release command -+ msg.m_tag.m_tagId = 0x3000f; -+ msg.m_tag.m_sendBufferSize = 4; -+ msg.m_tag.m_sendDataSize = 4; -+ -+ //pass across the handle -+ msg.m_tag.m_args.m_handle = handle; -+ -+ s = bcm_mailbox_property(&msg, sizeof(msg)); -+ -+ if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004 && msg.m_tag.m_args.m_error == 0) -+ return 0; -+ else -+ { -+ printk(KERN_ERR "failed to release vc memory: s=%d response=%08x recv data size=%08x error=%08x\n", -+ s, msg.m_response, msg.m_tag.m_recvDataSize, msg.m_tag.m_args.m_error); -+ return 1; -+ } -+} -+ -+unsigned int LockVcMemory(unsigned int *pBusAddress, unsigned int handle) -+{ -+ struct vc_msg -+ { -+ unsigned int m_msgSize; -+ unsigned int m_response; -+ -+ struct vc_tag -+ { -+ unsigned int m_tagId; -+ unsigned int m_sendBufferSize; -+ union { -+ unsigned int m_sendDataSize; -+ unsigned int m_recvDataSize; -+ }; -+ -+ struct args -+ { -+ union { -+ unsigned int m_handle; -+ unsigned int m_busAddress; -+ }; -+ } m_args; -+ } m_tag; -+ -+ unsigned int m_endTag; -+ } msg; -+ int s; -+ -+ msg.m_msgSize = sizeof(msg); -+ msg.m_response = 0; -+ msg.m_endTag = 0; -+ -+ //fill in the tag for the lock command -+ msg.m_tag.m_tagId = 0x3000d; -+ msg.m_tag.m_sendBufferSize = 4; -+ msg.m_tag.m_sendDataSize = 4; -+ -+ //pass across the handle -+ msg.m_tag.m_args.m_handle = handle; -+ -+ s = bcm_mailbox_property(&msg, sizeof(msg)); -+ -+ if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004) -+ { -+ //pick out the bus address -+ *pBusAddress = msg.m_tag.m_args.m_busAddress; -+ return 0; -+ } -+ else -+ { -+ printk(KERN_ERR "failed to lock vc memory: s=%d response=%08x recv data size=%08x\n", -+ s, msg.m_response, msg.m_tag.m_recvDataSize); -+ return 1; -+ } -+} -+ -+unsigned int UnlockVcMemory(unsigned int handle) -+{ -+ struct vc_msg -+ { -+ unsigned int m_msgSize; -+ unsigned int m_response; -+ -+ struct vc_tag -+ { -+ unsigned int m_tagId; -+ unsigned int m_sendBufferSize; -+ union { -+ unsigned int m_sendDataSize; -+ unsigned int m_recvDataSize; -+ }; -+ -+ struct args -+ { -+ union { -+ unsigned int m_handle; -+ unsigned int m_error; -+ }; -+ } m_args; -+ } m_tag; -+ -+ unsigned int m_endTag; -+ } msg; -+ int s; -+ -+ msg.m_msgSize = sizeof(msg); -+ msg.m_response = 0; -+ msg.m_endTag = 0; -+ -+ //fill in the tag for the unlock command -+ msg.m_tag.m_tagId = 0x3000e; -+ msg.m_tag.m_sendBufferSize = 4; -+ msg.m_tag.m_sendDataSize = 4; -+ -+ //pass across the handle -+ msg.m_tag.m_args.m_handle = handle; -+ -+ s = bcm_mailbox_property(&msg, sizeof(msg)); -+ -+ //check the error code too -+ if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004 && msg.m_tag.m_args.m_error == 0) -+ return 0; -+ else -+ { -+ printk(KERN_ERR "failed to unlock vc memory: s=%d response=%08x recv data size=%08x error%08x\n", -+ s, msg.m_response, msg.m_tag.m_recvDataSize, msg.m_tag.m_args.m_error); -+ return 1; -+ } -+} -+ -+unsigned int ExecuteVcCode(unsigned int code, -+ unsigned int r0, unsigned int r1, unsigned int r2, unsigned int r3, unsigned int r4, unsigned int r5) -+{ -+ struct vc_msg -+ { -+ unsigned int m_msgSize; -+ unsigned int m_response; -+ -+ struct vc_tag -+ { -+ unsigned int m_tagId; -+ unsigned int m_sendBufferSize; -+ union { -+ unsigned int m_sendDataSize; -+ unsigned int m_recvDataSize; -+ }; -+ -+ struct args -+ { -+ union { -+ unsigned int m_pCode; -+ unsigned int m_return; -+ }; -+ unsigned int m_r0; -+ unsigned int m_r1; -+ unsigned int m_r2; -+ unsigned int m_r3; -+ unsigned int m_r4; -+ unsigned int m_r5; -+ } m_args; -+ } m_tag; -+ -+ unsigned int m_endTag; -+ } msg; -+ int s; -+ -+ msg.m_msgSize = sizeof(msg); -+ msg.m_response = 0; -+ msg.m_endTag = 0; -+ -+ //fill in the tag for the unlock command -+ msg.m_tag.m_tagId = 0x30010; -+ msg.m_tag.m_sendBufferSize = 28; -+ msg.m_tag.m_sendDataSize = 28; -+ -+ //pass across the handle -+ msg.m_tag.m_args.m_pCode = code; -+ msg.m_tag.m_args.m_r0 = r0; -+ msg.m_tag.m_args.m_r1 = r1; -+ msg.m_tag.m_args.m_r2 = r2; -+ msg.m_tag.m_args.m_r3 = r3; -+ msg.m_tag.m_args.m_r4 = r4; -+ msg.m_tag.m_args.m_r5 = r5; -+ -+ s = bcm_mailbox_property(&msg, sizeof(msg)); -+ -+ //check the error code too -+ if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004) -+ return msg.m_tag.m_args.m_return; -+ else -+ { -+ printk(KERN_ERR "failed to execute: s=%d response=%08x recv data size=%08x\n", -+ s, msg.m_response, msg.m_tag.m_recvDataSize); -+ return 1; -+ } -+} -diff -Nur linux-4.1.13.orig/arch/arm/Makefile linux-rpi/arch/arm/Makefile ---- linux-4.1.13.orig/arch/arm/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/arch/arm/Makefile 2015-11-29 09:42:34.559454815 +0100 -@@ -150,6 +150,8 @@ - - # Machine directory name. This list is sorted alphanumerically - # by CONFIG_* macro name. -+machine-$(CONFIG_ARCH_BCM2708) += bcm2708 -+machine-$(CONFIG_ARCH_BCM2709) += bcm2709 - machine-$(CONFIG_ARCH_ALPINE) += alpine - machine-$(CONFIG_ARCH_AT91) += at91 - machine-$(CONFIG_ARCH_AXXIA) += axxia -diff -Nur linux-4.1.13.orig/arch/arm/mm/Kconfig linux-rpi/arch/arm/mm/Kconfig ---- linux-4.1.13.orig/arch/arm/mm/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/arch/arm/mm/Kconfig 2015-11-29 09:42:35.047422392 +0100 -@@ -358,7 +358,7 @@ - - # ARMv6 - config CPU_V6 -- bool "Support ARM V6 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V6) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX) -+ bool "Support ARM V6 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V6) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || MACH_BCM2708) - select CPU_32v6 - select CPU_ABRT_EV6 - select CPU_CACHE_V6 -diff -Nur linux-4.1.13.orig/arch/arm/mm/proc-v6.S linux-rpi/arch/arm/mm/proc-v6.S ---- linux-4.1.13.orig/arch/arm/mm/proc-v6.S 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/arch/arm/mm/proc-v6.S 2015-11-29 09:42:35.055421861 +0100 -@@ -73,10 +73,19 @@ - * - * IRQs are already disabled. - */ -+ -+/* See jira SW-5991 for details of this workaround */ - ENTRY(cpu_v6_do_idle) -- mov r1, #0 -- mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode -- mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt -+ .align 5 -+ mov r1, #2 -+1: subs r1, #1 -+ nop -+ mcreq p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode -+ mcreq p15, 0, r1, c7, c0, 4 @ wait for interrupt -+ nop -+ nop -+ nop -+ bne 1b - ret lr - - ENTRY(cpu_v6_dcache_clean_area) -diff -Nur linux-4.1.13.orig/arch/arm/mm/proc-v7.S linux-rpi/arch/arm/mm/proc-v7.S ---- linux-4.1.13.orig/arch/arm/mm/proc-v7.S 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/arch/arm/mm/proc-v7.S 2015-11-29 09:42:35.055421861 +0100 -@@ -460,6 +460,7 @@ - orr r0, r0, r6 @ set them - THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions - ret lr @ return to head.S:__ret -+ .space 256 - ENDPROC(__v7_setup) - - .align 2 -diff -Nur linux-4.1.13.orig/arch/arm/tools/mach-types linux-rpi/arch/arm/tools/mach-types ---- linux-4.1.13.orig/arch/arm/tools/mach-types 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/arch/arm/tools/mach-types 2015-11-29 09:42:35.103418671 +0100 -@@ -522,6 +522,8 @@ - prima2_evb MACH_PRIMA2_EVB PRIMA2_EVB 3103 - paz00 MACH_PAZ00 PAZ00 3128 - acmenetusfoxg20 MACH_ACMENETUSFOXG20 ACMENETUSFOXG20 3129 -+bcm2708 MACH_BCM2708 BCM2708 3138 -+bcm2709 MACH_BCM2709 BCM2709 3139 - ag5evm MACH_AG5EVM AG5EVM 3189 - ics_if_voip MACH_ICS_IF_VOIP ICS_IF_VOIP 3206 - wlf_cragg_6410 MACH_WLF_CRAGG_6410 WLF_CRAGG_6410 3207 -diff -Nur linux-4.1.13.orig/Documentation/ABI/stable/sysfs-driver-w1_ds28ea00 linux-rpi/Documentation/ABI/stable/sysfs-driver-w1_ds28ea00 ---- linux-4.1.13.orig/Documentation/ABI/stable/sysfs-driver-w1_ds28ea00 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/Documentation/ABI/stable/sysfs-driver-w1_ds28ea00 2015-11-29 09:42:34.091485909 +0100 -@@ -0,0 +1,6 @@ -+What: /sys/bus/w1/devices/.../w1_seq -+Date: Apr 2015 -+Contact: Matt Campbell -+Description: Support for the DS28EA00 chain sequence function -+ see Documentation/w1/slaves/w1_therm for detailed information -+Users: any user space application which wants to communicate with DS28EA00 -diff -Nur linux-4.1.13.orig/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt linux-rpi/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt ---- linux-4.1.13.orig/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt 2015-11-29 09:42:34.191479265 +0100 -@@ -48,8 +48,8 @@ - - bcm2835_i2s: i2s@7e203000 { - compatible = "brcm,bcm2835-i2s"; -- reg = < 0x7e203000 0x20>, -- < 0x7e101098 0x02>; -+ reg = < 0x7e203000 0x24>, -+ < 0x7e101098 0x08>; - - dmas = <&dma 2>, - <&dma 3>; -diff -Nur linux-4.1.13.orig/Documentation/devicetree/bindings/input/touchscreen/focaltech-ft6236.txt linux-rpi/Documentation/devicetree/bindings/input/touchscreen/focaltech-ft6236.txt ---- linux-4.1.13.orig/Documentation/devicetree/bindings/input/touchscreen/focaltech-ft6236.txt 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/Documentation/devicetree/bindings/input/touchscreen/focaltech-ft6236.txt 2015-11-29 09:42:34.203478468 +0100 -@@ -0,0 +1,35 @@ -+* FocalTech FT6236 I2C touchscreen controller -+ -+Required properties: -+ - compatible : "focaltech,ft6236" -+ - reg : I2C slave address of the chip (0x38) -+ - interrupt-parent : a phandle pointing to the interrupt controller -+ serving the interrupt for this chip -+ - interrupts : interrupt specification for the touch controller -+ interrupt -+ - reset-gpios : GPIO specification for the RSTN input -+ - touchscreen-size-x : horizontal resolution of touchscreen (in pixels) -+ - touchscreen-size-y : vertical resolution of touchscreen (in pixels) -+ -+Optional properties: -+ - touchscreen-fuzz-x : horizontal noise value of the absolute input -+ device (in pixels) -+ - touchscreen-fuzz-y : vertical noise value of the absolute input -+ device (in pixels) -+ - touchscreen-inverted-x : X axis is inverted (boolean) -+ - touchscreen-inverted-y : Y axis is inverted (boolean) -+ - touchscreen-swapped-x-y: X and Y axis are swapped (boolean) -+ Swapping is done after inverting the axis -+ -+Example: -+ -+ ft6x06@38 { -+ compatible = "focaltech,ft6236"; -+ reg = <0x38>; -+ interrupt-parent = <&gpio>; -+ interrupts = <23 2>; -+ touchscreen-size-x = <320>; -+ touchscreen-size-y = <480>; -+ touchscreen-inverted-x; -+ touchscreen-swapped-x-y; -+ }; -diff -Nur linux-4.1.13.orig/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi-dev.txt linux-rpi/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi-dev.txt ---- linux-4.1.13.orig/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi-dev.txt 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi-dev.txt 2015-11-29 09:42:34.211477936 +0100 -@@ -0,0 +1,17 @@ -+* Broadcom BCM2835 SMI character device driver. -+ -+SMI or secondary memory interface is a peripheral specific to certain Broadcom -+SOCs, and is helpful for talking to things like parallel-interface displays -+and NAND flashes (in fact, most things with a parallel register interface). -+ -+This driver adds a character device which provides a user-space interface to -+an instance of the SMI driver. -+ -+Required properties: -+- compatible: "brcm,bcm2835-smi-dev" -+- smi_handle: a phandle to the smi node. -+ -+Optional properties: -+- None. -+ -+ -diff -Nur linux-4.1.13.orig/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi.txt linux-rpi/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi.txt ---- linux-4.1.13.orig/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi.txt 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi.txt 2015-11-29 09:42:34.211477936 +0100 -@@ -0,0 +1,48 @@ -+* Broadcom BCM2835 SMI driver. -+ -+SMI or secondary memory interface is a peripheral specific to certain Broadcom -+SOCs, and is helpful for talking to things like parallel-interface displays -+and NAND flashes (in fact, most things with a parallel register interface). -+ -+Required properties: -+- compatible: "brcm,bcm2835-smi" -+- reg: Should contain location and length of SMI registers and SMI clkman regs -+- interrupts: *the* SMI interrupt. -+- pinctrl-names: should be "default". -+- pinctrl-0: the phandle of the gpio pin node. -+- brcm,smi-clock-source: the clock source for clkman -+- brcm,smi-clock-divisor: the integer clock divisor for clkman -+- dmas: the dma controller phandle and the DREQ number (4 on a 2835) -+- dma-names: the name used by the driver to request its channel. -+ Should be "rx-tx". -+ -+Optional properties: -+- None. -+ -+Examples: -+ -+8 data pin configuration: -+ -+smi: smi@7e600000 { -+ compatible = "brcm,bcm2835-smi"; -+ reg = <0x7e600000 0x44>, <0x7e1010b0 0x8>; -+ interrupts = <2 16>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&smi_pins>; -+ brcm,smi-clock-source = <6>; -+ brcm,smi-clock-divisor = <4>; -+ dmas = <&dma 4>; -+ dma-names = "rx-tx"; -+ -+ status = "okay"; -+}; -+ -+smi_pins: smi_pins { -+ brcm,pins = <2 3 4 5 6 7 8 9 10 11 12 13 14 15>; -+ /* Alt 1: SMI */ -+ brcm,function = <5 5 5 5 5 5 5 5 5 5 5 5 5 5>; -+ /* /CS, /WE and /OE are pulled high, as they are -+ generally active low signals */ -+ brcm,pull = <2 2 2 2 2 2 0 0 0 0 0 0 0 0>; -+}; -+ -diff -Nur linux-4.1.13.orig/Documentation/devicetree/bindings/mtd/brcm,bcm2835-smi-nand.txt linux-rpi/Documentation/devicetree/bindings/mtd/brcm,bcm2835-smi-nand.txt ---- linux-4.1.13.orig/Documentation/devicetree/bindings/mtd/brcm,bcm2835-smi-nand.txt 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/Documentation/devicetree/bindings/mtd/brcm,bcm2835-smi-nand.txt 2015-11-29 09:42:34.211477936 +0100 -@@ -0,0 +1,42 @@ -+* BCM2835 SMI NAND flash -+ -+This driver is a shim between the BCM2835 SMI driver (SMI is a peripheral for -+talking to parallel register interfaces) and Linux's MTD layer. -+ -+Required properties: -+- compatible: "brcm,bcm2835-smi-nand" -+- status: "okay" -+ -+Optional properties: -+- partition@n, where n is an integer from a consecutive sequence starting at 0 -+ - Difficult to store partition table on NAND device - normally put it -+ in the source code, kernel bootparams, or device tree (the best way!) -+ - Sub-properties: -+ - label: the partition name, as shown by mtdinfo /dev/mtd* -+ - reg: the size and offset of this partition. -+ - (optional) read-only: an empty property flagging as read only -+ -+Example: -+ -+nand: flash@0 { -+ compatible = "brcm,bcm2835-smi-nand"; -+ status = "okay"; -+ -+ partition@0 { -+ label = "stage2"; -+ // 128k -+ reg = <0 0x20000>; -+ read-only; -+ }; -+ partition@1 { -+ label = "firmware"; -+ // 16M -+ reg = <0x20000 0x1000000>; -+ read-only; -+ }; -+ partition@2 { -+ label = "root"; -+ // 2G -+ reg = <0x1020000 0x80000000>; -+ }; -+}; -\ No newline at end of file -diff -Nur linux-4.1.13.orig/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt linux-rpi/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt ---- linux-4.1.13.orig/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt 2015-11-29 09:42:34.251475279 +0100 -@@ -16,8 +16,8 @@ - - bcm2835_i2s: i2s@7e203000 { - compatible = "brcm,bcm2835-i2s"; -- reg = <0x7e203000 0x20>, -- <0x7e101098 0x02>; -+ reg = <0x7e203000 0x24>, -+ <0x7e101098 0x08>; - - dmas = <&dma 2>, - <&dma 3>; -diff -Nur linux-4.1.13.orig/Documentation/devicetree/bindings/vendor-prefixes.txt linux-rpi/Documentation/devicetree/bindings/vendor-prefixes.txt ---- linux-4.1.13.orig/Documentation/devicetree/bindings/vendor-prefixes.txt 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/Documentation/devicetree/bindings/vendor-prefixes.txt 2015-11-29 09:42:34.263474481 +0100 -@@ -76,6 +76,7 @@ - excito Excito - fcs Fairchild Semiconductor - firefly Firefly -+focaltech FocalTech Systems Co.,Ltd - fsl Freescale Semiconductor - GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc. - gef GE Fanuc Intelligent Platforms Embedded Systems, Inc. -diff -Nur linux-4.1.13.orig/Documentation/video4linux/bcm2835-v4l2.txt linux-rpi/Documentation/video4linux/bcm2835-v4l2.txt ---- linux-4.1.13.orig/Documentation/video4linux/bcm2835-v4l2.txt 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/Documentation/video4linux/bcm2835-v4l2.txt 2015-11-29 09:42:34.479460130 +0100 -@@ -0,0 +1,60 @@ -+ -+BCM2835 (aka Raspberry Pi) V4L2 driver -+====================================== -+ -+1. Copyright -+============ -+ -+Copyright © 2013 Raspberry Pi (Trading) Ltd. -+ -+2. License -+========== -+ -+This program is free software; you can redistribute it and/or modify -+it under the terms of the GNU General Public License as published by -+the Free Software Foundation; either version 2 of the License, or -+(at your option) any later version. -+ -+This program is distributed in the hope that it will be useful, -+but WITHOUT ANY WARRANTY; without even the implied warranty of -+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+GNU General Public License for more details. -+ -+You should have received a copy of the GNU General Public License -+along with this program; if not, write to the Free Software -+Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ -+3. Quick Start -+============== -+ -+You need a version 1.0 or later of v4l2-ctl, available from: -+ git://git.linuxtv.org/v4l-utils.git -+ -+$ sudo modprobe bcm2835-v4l2 -+ -+Turn on the overlay: -+ -+$ v4l2-ctl --overlay=1 -+ -+Turn off the overlay: -+ -+$ v4l2-ctl --overlay=0 -+ -+Set the capture format for video: -+ -+$ v4l2-ctl --set-fmt-video=width=1920,height=1088,pixelformat=4 -+ -+(Note: 1088 not 1080). -+ -+Capture: -+ -+$ v4l2-ctl --stream-mmap=3 --stream-count=100 --stream-to=somefile.h264 -+ -+Stills capture: -+ -+$ v4l2-ctl --set-fmt-video=width=2592,height=1944,pixelformat=3 -+$ v4l2-ctl --stream-mmap=3 --stream-count=1 --stream-to=somefile.jpg -+ -+List of available formats: -+ -+$ v4l2-ctl --list-formats -diff -Nur linux-4.1.13.orig/Documentation/w1/slaves/w1_therm linux-rpi/Documentation/w1/slaves/w1_therm ---- linux-4.1.13.orig/Documentation/w1/slaves/w1_therm 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/Documentation/w1/slaves/w1_therm 2015-11-29 09:42:34.491459333 +0100 -@@ -11,12 +11,14 @@ - Description - ----------- - --w1_therm provides basic temperature conversion for ds18*20 devices. -+w1_therm provides basic temperature conversion for ds18*20 devices, and the -+ds28ea00 device. - supported family codes: - W1_THERM_DS18S20 0x10 - W1_THERM_DS1822 0x22 - W1_THERM_DS18B20 0x28 - W1_THERM_DS1825 0x3B -+W1_THERM_DS28EA00 0x42 - - Support is provided through the sysfs w1_slave file. Each open and - read sequence will initiate a temperature conversion then provide two -@@ -48,3 +50,10 @@ - maximum current draw of 1.5mA and that a 5k pullup resistor is not - sufficient. The strong pullup is designed to provide the additional - current required. -+ -+The DS28EA00 provides an additional two pins for implementing a sequence -+detection algorithm. This feature allows you to determine the physical -+location of the chip in the 1-wire bus without needing pre-existing -+knowledge of the bus ordering. Support is provided through the sysfs -+w1_seq file. The file will contain a single line with an integer value -+representing the device index in the bus starting at 0. -diff -Nur linux-4.1.13.orig/drivers/char/broadcom/bcm2835-gpiomem.c linux-rpi/drivers/char/broadcom/bcm2835-gpiomem.c ---- linux-4.1.13.orig/drivers/char/broadcom/bcm2835-gpiomem.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/char/broadcom/bcm2835-gpiomem.c 2015-11-29 09:42:36.703312367 +0100 -@@ -0,0 +1,260 @@ -+/** -+ * GPIO memory device driver -+ * -+ * Creates a chardev /dev/gpiomem which will provide user access to -+ * the BCM2835's GPIO registers when it is mmap()'d. -+ * No longer need root for user GPIO access, but without relaxing permissions -+ * on /dev/mem. -+ * -+ * Written by Luke Wren -+ * Copyright (c) 2015, Raspberry Pi (Trading) Ltd. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define DEVICE_NAME "bcm2835-gpiomem" -+#define DRIVER_NAME "gpiomem-bcm2835" -+#define DEVICE_MINOR 0 -+ -+struct bcm2835_gpiomem_instance { -+ unsigned long gpio_regs_phys; -+ struct device *dev; -+}; -+ -+static struct cdev bcm2835_gpiomem_cdev; -+static dev_t bcm2835_gpiomem_devid; -+static struct class *bcm2835_gpiomem_class; -+static struct device *bcm2835_gpiomem_dev; -+static struct bcm2835_gpiomem_instance *inst; -+ -+ -+/**************************************************************************** -+* -+* GPIO mem chardev file ops -+* -+***************************************************************************/ -+ -+static int bcm2835_gpiomem_open(struct inode *inode, struct file *file) -+{ -+ int dev = iminor(inode); -+ int ret = 0; -+ -+ dev_info(inst->dev, "gpiomem device opened."); -+ -+ if (dev != DEVICE_MINOR) { -+ dev_err(inst->dev, "Unknown minor device: %d", dev); -+ ret = -ENXIO; -+ } -+ return ret; -+} -+ -+static int bcm2835_gpiomem_release(struct inode *inode, struct file *file) -+{ -+ int dev = iminor(inode); -+ int ret = 0; -+ -+ if (dev != DEVICE_MINOR) { -+ dev_err(inst->dev, "Unknown minor device %d", dev); -+ ret = -ENXIO; -+ } -+ return ret; -+} -+ -+static const struct vm_operations_struct bcm2835_gpiomem_vm_ops = { -+#ifdef CONFIG_HAVE_IOREMAP_PROT -+ .access = generic_access_phys -+#endif -+}; -+ -+static int bcm2835_gpiomem_mmap(struct file *file, struct vm_area_struct *vma) -+{ -+ /* Ignore what the user says - they're getting the GPIO regs -+ whether they like it or not! */ -+ unsigned long gpio_page = inst->gpio_regs_phys >> PAGE_SHIFT; -+ -+ vma->vm_page_prot = phys_mem_access_prot(file, gpio_page, -+ PAGE_SIZE, -+ vma->vm_page_prot); -+ vma->vm_ops = &bcm2835_gpiomem_vm_ops; -+ if (remap_pfn_range(vma, vma->vm_start, -+ gpio_page, -+ PAGE_SIZE, -+ vma->vm_page_prot)) { -+ return -EAGAIN; -+ } -+ return 0; -+} -+ -+static const struct file_operations -+bcm2835_gpiomem_fops = { -+ .owner = THIS_MODULE, -+ .open = bcm2835_gpiomem_open, -+ .release = bcm2835_gpiomem_release, -+ .mmap = bcm2835_gpiomem_mmap, -+}; -+ -+ -+ /**************************************************************************** -+* -+* Probe and remove functions -+* -+***************************************************************************/ -+ -+ -+static int bcm2835_gpiomem_probe(struct platform_device *pdev) -+{ -+ int err; -+ void *ptr_err; -+ struct device *dev = &pdev->dev; -+ struct resource *ioresource; -+ -+ /* Allocate buffers and instance data */ -+ -+ inst = kzalloc(sizeof(struct bcm2835_gpiomem_instance), GFP_KERNEL); -+ -+ if (!inst) { -+ err = -ENOMEM; -+ goto failed_inst_alloc; -+ } -+ -+ inst->dev = dev; -+ -+ ioresource = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (ioresource) { -+ inst->gpio_regs_phys = ioresource->start; -+ } else { -+ dev_err(inst->dev, "failed to get IO resource"); -+ err = -ENOENT; -+ goto failed_get_resource; -+ } -+ -+ /* Create character device entries */ -+ -+ err = alloc_chrdev_region(&bcm2835_gpiomem_devid, -+ DEVICE_MINOR, 1, DEVICE_NAME); -+ if (err != 0) { -+ dev_err(inst->dev, "unable to allocate device number"); -+ goto failed_alloc_chrdev; -+ } -+ cdev_init(&bcm2835_gpiomem_cdev, &bcm2835_gpiomem_fops); -+ bcm2835_gpiomem_cdev.owner = THIS_MODULE; -+ err = cdev_add(&bcm2835_gpiomem_cdev, bcm2835_gpiomem_devid, 1); -+ if (err != 0) { -+ dev_err(inst->dev, "unable to register device"); -+ goto failed_cdev_add; -+ } -+ -+ /* Create sysfs entries */ -+ -+ bcm2835_gpiomem_class = class_create(THIS_MODULE, DEVICE_NAME); -+ ptr_err = bcm2835_gpiomem_class; -+ if (IS_ERR(ptr_err)) -+ goto failed_class_create; -+ -+ bcm2835_gpiomem_dev = device_create(bcm2835_gpiomem_class, NULL, -+ bcm2835_gpiomem_devid, NULL, -+ "gpiomem"); -+ ptr_err = bcm2835_gpiomem_dev; -+ if (IS_ERR(ptr_err)) -+ goto failed_device_create; -+ -+ dev_info(inst->dev, "Initialised: Registers at 0x%08lx", -+ inst->gpio_regs_phys); -+ -+ return 0; -+ -+failed_device_create: -+ class_destroy(bcm2835_gpiomem_class); -+failed_class_create: -+ cdev_del(&bcm2835_gpiomem_cdev); -+ err = PTR_ERR(ptr_err); -+failed_cdev_add: -+ unregister_chrdev_region(bcm2835_gpiomem_devid, 1); -+failed_alloc_chrdev: -+failed_get_resource: -+ kfree(inst); -+failed_inst_alloc: -+ dev_err(inst->dev, "could not load bcm2835_gpiomem"); -+ return err; -+} -+ -+static int bcm2835_gpiomem_remove(struct platform_device *pdev) -+{ -+ struct device *dev = inst->dev; -+ -+ kfree(inst); -+ device_destroy(bcm2835_gpiomem_class, bcm2835_gpiomem_devid); -+ class_destroy(bcm2835_gpiomem_class); -+ cdev_del(&bcm2835_gpiomem_cdev); -+ unregister_chrdev_region(bcm2835_gpiomem_devid, 1); -+ -+ dev_info(dev, "GPIO mem driver removed - OK"); -+ return 0; -+} -+ -+ /**************************************************************************** -+* -+* Register the driver with device tree -+* -+***************************************************************************/ -+ -+static const struct of_device_id bcm2835_gpiomem_of_match[] = { -+ {.compatible = "brcm,bcm2835-gpiomem",}, -+ { /* sentinel */ }, -+}; -+ -+MODULE_DEVICE_TABLE(of, bcm2835_gpiomem_of_match); -+ -+static struct platform_driver bcm2835_gpiomem_driver = { -+ .probe = bcm2835_gpiomem_probe, -+ .remove = bcm2835_gpiomem_remove, -+ .driver = { -+ .name = DRIVER_NAME, -+ .owner = THIS_MODULE, -+ .of_match_table = bcm2835_gpiomem_of_match, -+ }, -+}; -+ -+module_platform_driver(bcm2835_gpiomem_driver); -+ -+MODULE_ALIAS("platform:gpiomem-bcm2835"); -+MODULE_LICENSE("GPL"); -+MODULE_DESCRIPTION("gpiomem driver for accessing GPIO from userspace"); -+MODULE_AUTHOR("Luke Wren "); -diff -Nur linux-4.1.13.orig/drivers/char/broadcom/bcm2835_smi_dev.c linux-rpi/drivers/char/broadcom/bcm2835_smi_dev.c ---- linux-4.1.13.orig/drivers/char/broadcom/bcm2835_smi_dev.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/char/broadcom/bcm2835_smi_dev.c 2015-11-29 09:42:36.703312367 +0100 -@@ -0,0 +1,402 @@ -+/** -+ * Character device driver for Broadcom Secondary Memory Interface -+ * -+ * Written by Luke Wren -+ * Copyright (c) 2015, Raspberry Pi (Trading) Ltd. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#define DEVICE_NAME "bcm2835-smi-dev" -+#define DRIVER_NAME "smi-dev-bcm2835" -+#define DEVICE_MINOR 0 -+ -+static struct cdev bcm2835_smi_cdev; -+static dev_t bcm2835_smi_devid; -+static struct class *bcm2835_smi_class; -+static struct device *bcm2835_smi_dev; -+ -+struct bcm2835_smi_dev_instance { -+ struct device *dev; -+}; -+ -+static struct bcm2835_smi_instance *smi_inst; -+static struct bcm2835_smi_dev_instance *inst; -+ -+static const char *const ioctl_names[] = { -+ "READ_SETTINGS", -+ "WRITE_SETTINGS", -+ "ADDRESS" -+}; -+ -+/**************************************************************************** -+* -+* SMI chardev file ops -+* -+***************************************************************************/ -+static long -+bcm2835_smi_ioctl(struct file *file, unsigned int cmd, unsigned long arg) -+{ -+ long ret = 0; -+ -+ dev_info(inst->dev, "serving ioctl..."); -+ -+ switch (cmd) { -+ case BCM2835_SMI_IOC_GET_SETTINGS:{ -+ struct smi_settings *settings; -+ -+ dev_info(inst->dev, "Reading SMI settings to user."); -+ settings = bcm2835_smi_get_settings_from_regs(smi_inst); -+ if (copy_to_user((void *)arg, settings, -+ sizeof(struct smi_settings))) -+ dev_err(inst->dev, "settings copy failed."); -+ break; -+ } -+ case BCM2835_SMI_IOC_WRITE_SETTINGS:{ -+ struct smi_settings *settings; -+ -+ dev_info(inst->dev, "Setting user's SMI settings."); -+ settings = bcm2835_smi_get_settings_from_regs(smi_inst); -+ if (copy_from_user(settings, (void *)arg, -+ sizeof(struct smi_settings))) -+ dev_err(inst->dev, "settings copy failed."); -+ else -+ bcm2835_smi_set_regs_from_settings(smi_inst); -+ break; -+ } -+ case BCM2835_SMI_IOC_ADDRESS: -+ dev_info(inst->dev, "SMI address set: 0x%02x", (int)arg); -+ bcm2835_smi_set_address(smi_inst, arg); -+ break; -+ default: -+ dev_err(inst->dev, "invalid ioctl cmd: %d", cmd); -+ ret = -ENOTTY; -+ break; -+ } -+ -+ return ret; -+} -+ -+static int bcm2835_smi_open(struct inode *inode, struct file *file) -+{ -+ int dev = iminor(inode); -+ -+ dev_dbg(inst->dev, "SMI device opened."); -+ -+ if (dev != DEVICE_MINOR) { -+ dev_err(inst->dev, -+ "bcm2835_smi_release: Unknown minor device: %d", -+ dev); -+ return -ENXIO; -+ } -+ -+ return 0; -+} -+ -+static int bcm2835_smi_release(struct inode *inode, struct file *file) -+{ -+ int dev = iminor(inode); -+ -+ if (dev != DEVICE_MINOR) { -+ dev_err(inst->dev, -+ "bcm2835_smi_release: Unknown minor device %d", dev); -+ return -ENXIO; -+ } -+ -+ return 0; -+} -+ -+static ssize_t dma_bounce_user( -+ enum dma_transfer_direction dma_dir, -+ char __user *user_ptr, -+ size_t count, -+ struct bcm2835_smi_bounce_info *bounce) -+{ -+ int chunk_size; -+ int chunk_no = 0; -+ int count_left = count; -+ -+ while (count_left) { -+ int rv; -+ void *buf; -+ -+ /* Wait for current chunk to complete: */ -+ if (down_timeout(&bounce->callback_sem, -+ msecs_to_jiffies(1000))) { -+ dev_err(inst->dev, "DMA bounce timed out"); -+ count -= (count_left); -+ break; -+ } -+ -+ if (bounce->callback_sem.count >= DMA_BOUNCE_BUFFER_COUNT - 1) -+ dev_err(inst->dev, "WARNING: Ring buffer overflow"); -+ chunk_size = count_left > DMA_BOUNCE_BUFFER_SIZE ? -+ DMA_BOUNCE_BUFFER_SIZE : count_left; -+ buf = bounce->buffer[chunk_no % DMA_BOUNCE_BUFFER_COUNT]; -+ if (dma_dir == DMA_DEV_TO_MEM) -+ rv = copy_to_user(user_ptr, buf, chunk_size); -+ else -+ rv = copy_from_user(buf, user_ptr, chunk_size); -+ if (rv) -+ dev_err(inst->dev, "copy_*_user() failed!: %d", rv); -+ user_ptr += chunk_size; -+ count_left -= chunk_size; -+ chunk_no++; -+ } -+ return count; -+} -+ -+static ssize_t -+bcm2835_read_file(struct file *f, char __user *user_ptr, -+ size_t count, loff_t *offs) -+{ -+ int odd_bytes; -+ -+ dev_dbg(inst->dev, "User reading %d bytes from SMI.", count); -+ /* We don't want to DMA a number of bytes % 4 != 0 (32 bit FIFO) */ -+ if (count > DMA_THRESHOLD_BYTES) -+ odd_bytes = count & 0x3; -+ else -+ odd_bytes = count; -+ count -= odd_bytes; -+ if (count) { -+ struct bcm2835_smi_bounce_info *bounce; -+ -+ count = bcm2835_smi_user_dma(smi_inst, -+ DMA_DEV_TO_MEM, user_ptr, count, -+ &bounce); -+ if (count) -+ count = dma_bounce_user(DMA_DEV_TO_MEM, user_ptr, -+ count, bounce); -+ } -+ if (odd_bytes) { -+ /* Read from FIFO directly if not using DMA */ -+ uint8_t buf[DMA_THRESHOLD_BYTES]; -+ -+ bcm2835_smi_read_buf(smi_inst, buf, odd_bytes); -+ if (copy_to_user(user_ptr, buf, odd_bytes)) -+ dev_err(inst->dev, "copy_to_user() failed."); -+ count += odd_bytes; -+ -+ } -+ return count; -+} -+ -+static ssize_t -+bcm2835_write_file(struct file *f, const char __user *user_ptr, -+ size_t count, loff_t *offs) -+{ -+ int odd_bytes; -+ -+ dev_dbg(inst->dev, "User writing %d bytes to SMI.", count); -+ if (count > DMA_THRESHOLD_BYTES) -+ odd_bytes = count & 0x3; -+ else -+ odd_bytes = count; -+ count -= odd_bytes; -+ if (count) { -+ struct bcm2835_smi_bounce_info *bounce; -+ -+ count = bcm2835_smi_user_dma(smi_inst, -+ DMA_MEM_TO_DEV, (char __user *)user_ptr, count, -+ &bounce); -+ if (count) -+ count = dma_bounce_user(DMA_MEM_TO_DEV, -+ (char __user *)user_ptr, -+ count, bounce); -+ } -+ if (odd_bytes) { -+ uint8_t buf[DMA_THRESHOLD_BYTES]; -+ -+ if (copy_from_user(buf, user_ptr, odd_bytes)) -+ dev_err(inst->dev, "copy_from_user() failed."); -+ else -+ bcm2835_smi_write_buf(smi_inst, buf, odd_bytes); -+ count += odd_bytes; -+ } -+ return count; -+} -+ -+static const struct file_operations -+bcm2835_smi_fops = { -+ .owner = THIS_MODULE, -+ .unlocked_ioctl = bcm2835_smi_ioctl, -+ .open = bcm2835_smi_open, -+ .release = bcm2835_smi_release, -+ .read = bcm2835_read_file, -+ .write = bcm2835_write_file, -+}; -+ -+ -+/**************************************************************************** -+* -+* bcm2835_smi_probe - called when the driver is loaded. -+* -+***************************************************************************/ -+ -+static int bcm2835_smi_dev_probe(struct platform_device *pdev) -+{ -+ int err; -+ void *ptr_err; -+ struct device *dev = &pdev->dev; -+ struct device_node *node = dev->of_node, *smi_node; -+ -+ if (!node) { -+ dev_err(dev, "No device tree node supplied!"); -+ return -EINVAL; -+ } -+ -+ smi_node = of_parse_phandle(node, "smi_handle", 0); -+ -+ if (!smi_node) { -+ dev_err(dev, "No such property: smi_handle"); -+ return -ENXIO; -+ } -+ -+ smi_inst = bcm2835_smi_get(smi_node); -+ -+ if (!smi_inst) -+ return -EPROBE_DEFER; -+ -+ /* Allocate buffers and instance data */ -+ -+ inst = devm_kzalloc(dev, sizeof(*inst), GFP_KERNEL); -+ -+ if (!inst) -+ return -ENOMEM; -+ -+ inst->dev = dev; -+ -+ /* Create character device entries */ -+ -+ err = alloc_chrdev_region(&bcm2835_smi_devid, -+ DEVICE_MINOR, 1, DEVICE_NAME); -+ if (err != 0) { -+ dev_err(inst->dev, "unable to allocate device number"); -+ return -ENOMEM; -+ } -+ cdev_init(&bcm2835_smi_cdev, &bcm2835_smi_fops); -+ bcm2835_smi_cdev.owner = THIS_MODULE; -+ err = cdev_add(&bcm2835_smi_cdev, bcm2835_smi_devid, 1); -+ if (err != 0) { -+ dev_err(inst->dev, "unable to register device"); -+ err = -ENOMEM; -+ goto failed_cdev_add; -+ } -+ -+ /* Create sysfs entries */ -+ -+ bcm2835_smi_class = class_create(THIS_MODULE, DEVICE_NAME); -+ ptr_err = bcm2835_smi_class; -+ if (IS_ERR(ptr_err)) -+ goto failed_class_create; -+ -+ bcm2835_smi_dev = device_create(bcm2835_smi_class, NULL, -+ bcm2835_smi_devid, NULL, -+ "smi"); -+ ptr_err = bcm2835_smi_dev; -+ if (IS_ERR(ptr_err)) -+ goto failed_device_create; -+ -+ dev_info(inst->dev, "initialised"); -+ -+ return 0; -+ -+failed_device_create: -+ class_destroy(bcm2835_smi_class); -+failed_class_create: -+ cdev_del(&bcm2835_smi_cdev); -+ err = PTR_ERR(ptr_err); -+failed_cdev_add: -+ unregister_chrdev_region(bcm2835_smi_devid, 1); -+ dev_err(dev, "could not load bcm2835_smi_dev"); -+ return err; -+} -+ -+/**************************************************************************** -+* -+* bcm2835_smi_remove - called when the driver is unloaded. -+* -+***************************************************************************/ -+ -+static int bcm2835_smi_dev_remove(struct platform_device *pdev) -+{ -+ device_destroy(bcm2835_smi_class, bcm2835_smi_devid); -+ class_destroy(bcm2835_smi_class); -+ cdev_del(&bcm2835_smi_cdev); -+ unregister_chrdev_region(bcm2835_smi_devid, 1); -+ -+ dev_info(inst->dev, "SMI character dev removed - OK"); -+ return 0; -+} -+ -+/**************************************************************************** -+* -+* Register the driver with device tree -+* -+***************************************************************************/ -+ -+static const struct of_device_id bcm2835_smi_dev_of_match[] = { -+ {.compatible = "brcm,bcm2835-smi-dev",}, -+ { /* sentinel */ }, -+}; -+ -+MODULE_DEVICE_TABLE(of, bcm2835_smi_dev_of_match); -+ -+static struct platform_driver bcm2835_smi_dev_driver = { -+ .probe = bcm2835_smi_dev_probe, -+ .remove = bcm2835_smi_dev_remove, -+ .driver = { -+ .name = DRIVER_NAME, -+ .owner = THIS_MODULE, -+ .of_match_table = bcm2835_smi_dev_of_match, -+ }, -+}; -+ -+module_platform_driver(bcm2835_smi_dev_driver); -+ -+MODULE_ALIAS("platform:smi-dev-bcm2835"); -+MODULE_LICENSE("GPL"); -+MODULE_DESCRIPTION( -+ "Character device driver for BCM2835's secondary memory interface"); -+MODULE_AUTHOR("Luke Wren "); -diff -Nur linux-4.1.13.orig/drivers/char/broadcom/Kconfig linux-rpi/drivers/char/broadcom/Kconfig ---- linux-4.1.13.orig/drivers/char/broadcom/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/char/broadcom/Kconfig 2015-11-29 09:42:36.703312367 +0100 -@@ -0,0 +1,57 @@ -+# -+# Broadcom char driver config -+# -+ -+menuconfig BRCM_CHAR_DRIVERS -+ bool "Broadcom Char Drivers" -+ help -+ Broadcom's char drivers -+ -+if BRCM_CHAR_DRIVERS -+ -+config BCM_VC_CMA -+ bool "Videocore CMA" -+ depends on CMA && BCM2708_VCHIQ -+ default n -+ help -+ Helper for videocore CMA access. -+ -+config BCM2708_VCMEM -+ bool "Videocore Memory" -+ default y -+ help -+ Helper for videocore memory access and total size allocation. -+ -+config BCM_VCIO -+ tristate "Mailbox userspace access" -+ depends on BCM2835_MBOX -+ help -+ Gives access to the mailbox property channel from userspace. -+ -+endif -+ -+config BCM_VC_SM -+ bool "VMCS Shared Memory" -+ depends on BCM2708_VCHIQ -+ select BCM2708_VCMEM -+ default n -+ help -+ Support for the VC shared memory on the Broadcom reference -+ design. Uses the VCHIQ stack. -+ -+config BCM2835_DEVGPIOMEM -+ tristate "/dev/gpiomem rootless GPIO access via mmap() on the BCM2835" -+ default m -+ help -+ Provides users with root-free access to the GPIO registers -+ on the 2835. Calling mmap(/dev/gpiomem) will map the GPIO -+ register page to the user's pointer. -+ -+config BCM2835_SMI_DEV -+ tristate "Character device driver for BCM2835 Secondary Memory Interface" -+ depends on (MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835) && BCM2835_SMI -+ default m -+ help -+ This driver provides a character device interface (ioctl + read/write) to -+ Broadcom's Secondary Memory interface. The low-level functionality is provided -+ by the SMI driver itself. -diff -Nur linux-4.1.13.orig/drivers/char/broadcom/Makefile linux-rpi/drivers/char/broadcom/Makefile ---- linux-4.1.13.orig/drivers/char/broadcom/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/char/broadcom/Makefile 2015-11-29 09:42:36.703312367 +0100 -@@ -0,0 +1,7 @@ -+obj-$(CONFIG_BCM_VC_CMA) += vc_cma/ -+obj-$(CONFIG_BCM2708_VCMEM) += vc_mem.o -+obj-$(CONFIG_BCM_VCIO) += vcio.o -+obj-$(CONFIG_BCM_VC_SM) += vc_sm/ -+ -+obj-$(CONFIG_BCM2835_DEVGPIOMEM)+= bcm2835-gpiomem.o -+obj-$(CONFIG_BCM2835_SMI_DEV) += bcm2835_smi_dev.o -diff -Nur linux-4.1.13.orig/drivers/char/broadcom/vc_cma/Makefile linux-rpi/drivers/char/broadcom/vc_cma/Makefile ---- linux-4.1.13.orig/drivers/char/broadcom/vc_cma/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/char/broadcom/vc_cma/Makefile 2015-11-29 09:42:36.703312367 +0100 -@@ -0,0 +1,14 @@ -+ccflags-y += -Wall -Wstrict-prototypes -Wno-trigraphs -+ccflags-y += -Werror -+ccflags-y += -Iinclude/linux/broadcom -+ccflags-y += -Idrivers/misc/vc04_services -+ccflags-y += -Idrivers/misc/vc04_services/interface/vchi -+ccflags-y += -Idrivers/misc/vc04_services/interface/vchiq_arm -+ -+ccflags-y += -D__KERNEL__ -+ccflags-y += -D__linux__ -+ccflags-y += -Werror -+ -+obj-$(CONFIG_BCM_VC_CMA) += vc-cma.o -+ -+vc-cma-objs := vc_cma.o -diff -Nur linux-4.1.13.orig/drivers/char/broadcom/vc_cma/vc_cma.c linux-rpi/drivers/char/broadcom/vc_cma/vc_cma.c ---- linux-4.1.13.orig/drivers/char/broadcom/vc_cma/vc_cma.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/char/broadcom/vc_cma/vc_cma.c 2015-11-29 09:42:36.703312367 +0100 -@@ -0,0 +1,1193 @@ -+/** -+ * Copyright (c) 2010-2012 Broadcom. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "vc_cma.h" -+ -+#include "vchiq_util.h" -+#include "vchiq_connected.h" -+//#include "debug_sym.h" -+//#include "vc_mem.h" -+ -+#define DRIVER_NAME "vc-cma" -+ -+#define LOG_DBG(fmt, ...) \ -+ if (vc_cma_debug) \ -+ printk(KERN_INFO fmt "\n", ##__VA_ARGS__) -+#define LOG_INFO(fmt, ...) \ -+ printk(KERN_INFO fmt "\n", ##__VA_ARGS__) -+#define LOG_ERR(fmt, ...) \ -+ printk(KERN_ERR fmt "\n", ##__VA_ARGS__) -+ -+#define VC_CMA_FOURCC VCHIQ_MAKE_FOURCC('C', 'M', 'A', ' ') -+#define VC_CMA_VERSION 2 -+ -+#define VC_CMA_CHUNK_ORDER 6 /* 256K */ -+#define VC_CMA_CHUNK_SIZE (4096 << VC_CMA_CHUNK_ORDER) -+#define VC_CMA_MAX_PARAMS_PER_MSG \ -+ ((VCHIQ_MAX_MSG_SIZE - sizeof(unsigned short))/sizeof(unsigned short)) -+#define VC_CMA_RESERVE_COUNT_MAX 16 -+ -+#define PAGES_PER_CHUNK (VC_CMA_CHUNK_SIZE / PAGE_SIZE) -+ -+#define VCADDR_TO_PHYSADDR(vcaddr) (mm_vc_mem_phys_addr + vcaddr) -+ -+#define loud_error(...) \ -+ LOG_ERR("===== " __VA_ARGS__) -+ -+enum { -+ VC_CMA_MSG_QUIT, -+ VC_CMA_MSG_OPEN, -+ VC_CMA_MSG_TICK, -+ VC_CMA_MSG_ALLOC, /* chunk count */ -+ VC_CMA_MSG_FREE, /* chunk, chunk, ... */ -+ VC_CMA_MSG_ALLOCATED, /* chunk, chunk, ... */ -+ VC_CMA_MSG_REQUEST_ALLOC, /* chunk count */ -+ VC_CMA_MSG_REQUEST_FREE, /* chunk count */ -+ VC_CMA_MSG_RESERVE, /* bytes lo, bytes hi */ -+ VC_CMA_MSG_UPDATE_RESERVE, -+ VC_CMA_MSG_MAX -+}; -+ -+struct cma_msg { -+ unsigned short type; -+ unsigned short params[VC_CMA_MAX_PARAMS_PER_MSG]; -+}; -+ -+struct vc_cma_reserve_user { -+ unsigned int pid; -+ unsigned int reserve; -+}; -+ -+/* Device (/dev) related variables */ -+static dev_t vc_cma_devnum; -+static struct class *vc_cma_class; -+static struct cdev vc_cma_cdev; -+static int vc_cma_inited; -+static int vc_cma_debug; -+ -+/* Proc entry */ -+static struct proc_dir_entry *vc_cma_proc_entry; -+ -+phys_addr_t vc_cma_base; -+struct page *vc_cma_base_page; -+unsigned int vc_cma_size; -+EXPORT_SYMBOL(vc_cma_size); -+unsigned int vc_cma_initial; -+unsigned int vc_cma_chunks; -+unsigned int vc_cma_chunks_used; -+unsigned int vc_cma_chunks_reserved; -+ -+ -+void *vc_cma_dma_alloc; -+unsigned int vc_cma_dma_size; -+ -+static int in_loud_error; -+ -+unsigned int vc_cma_reserve_total; -+unsigned int vc_cma_reserve_count; -+struct vc_cma_reserve_user vc_cma_reserve_users[VC_CMA_RESERVE_COUNT_MAX]; -+static DEFINE_SEMAPHORE(vc_cma_reserve_mutex); -+static DEFINE_SEMAPHORE(vc_cma_worker_queue_push_mutex); -+ -+static u64 vc_cma_dma_mask = DMA_BIT_MASK(32); -+static struct platform_device vc_cma_device = { -+ .name = "vc-cma", -+ .id = 0, -+ .dev = { -+ .dma_mask = &vc_cma_dma_mask, -+ .coherent_dma_mask = DMA_BIT_MASK(32), -+ }, -+}; -+ -+static VCHIQ_INSTANCE_T cma_instance; -+static VCHIQ_SERVICE_HANDLE_T cma_service; -+static VCHIU_QUEUE_T cma_msg_queue; -+static struct task_struct *cma_worker; -+ -+static int vc_cma_set_reserve(unsigned int reserve, unsigned int pid); -+static int vc_cma_alloc_chunks(int num_chunks, struct cma_msg *reply); -+static VCHIQ_STATUS_T cma_service_callback(VCHIQ_REASON_T reason, -+ VCHIQ_HEADER_T * header, -+ VCHIQ_SERVICE_HANDLE_T service, -+ void *bulk_userdata); -+static void send_vc_msg(unsigned short type, -+ unsigned short param1, unsigned short param2); -+static bool send_worker_msg(VCHIQ_HEADER_T * msg); -+ -+static int early_vc_cma_mem(char *p) -+{ -+ unsigned int new_size; -+ printk(KERN_NOTICE "early_vc_cma_mem(%s)", p); -+ vc_cma_size = memparse(p, &p); -+ vc_cma_initial = vc_cma_size; -+ if (*p == '/') -+ vc_cma_size = memparse(p + 1, &p); -+ if (*p == '@') -+ vc_cma_base = memparse(p + 1, &p); -+ -+ new_size = (vc_cma_size - ((-vc_cma_base) & (VC_CMA_CHUNK_SIZE - 1))) -+ & ~(VC_CMA_CHUNK_SIZE - 1); -+ if (new_size > vc_cma_size) -+ vc_cma_size = 0; -+ vc_cma_initial = (vc_cma_initial + VC_CMA_CHUNK_SIZE - 1) -+ & ~(VC_CMA_CHUNK_SIZE - 1); -+ if (vc_cma_initial > vc_cma_size) -+ vc_cma_initial = vc_cma_size; -+ vc_cma_base = (vc_cma_base + VC_CMA_CHUNK_SIZE - 1) -+ & ~(VC_CMA_CHUNK_SIZE - 1); -+ -+ printk(KERN_NOTICE " -> initial %x, size %x, base %x", vc_cma_initial, -+ vc_cma_size, (unsigned int)vc_cma_base); -+ -+ return 0; -+} -+ -+early_param("vc-cma-mem", early_vc_cma_mem); -+ -+void vc_cma_early_init(void) -+{ -+ LOG_DBG("vc_cma_early_init - vc_cma_chunks = %d", vc_cma_chunks); -+ if (vc_cma_size) { -+ int rc = platform_device_register(&vc_cma_device); -+ LOG_DBG("platform_device_register -> %d", rc); -+ } -+} -+ -+void vc_cma_reserve(void) -+{ -+ /* if vc_cma_size is set, then declare vc CMA area of the same -+ * size from the end of memory -+ */ -+ if (vc_cma_size) { -+ if (dma_declare_contiguous(&vc_cma_device.dev, vc_cma_size, -+ vc_cma_base, 0) == 0) { -+ if (!dev_get_cma_area(NULL)) { -+ /* There is no default CMA area - make this -+ the default */ -+ struct cma *vc_cma_area = dev_get_cma_area( -+ &vc_cma_device.dev); -+ dma_contiguous_set_default(vc_cma_area); -+ LOG_INFO("vc_cma_reserve - using vc_cma as " -+ "the default contiguous DMA area"); -+ } -+ } else { -+ LOG_ERR("vc_cma: dma_declare_contiguous(%x,%x) failed", -+ vc_cma_size, (unsigned int)vc_cma_base); -+ vc_cma_size = 0; -+ } -+ } -+ vc_cma_chunks = vc_cma_size / VC_CMA_CHUNK_SIZE; -+} -+ -+/**************************************************************************** -+* -+* vc_cma_open -+* -+***************************************************************************/ -+ -+static int vc_cma_open(struct inode *inode, struct file *file) -+{ -+ (void)inode; -+ (void)file; -+ -+ return 0; -+} -+ -+/**************************************************************************** -+* -+* vc_cma_release -+* -+***************************************************************************/ -+ -+static int vc_cma_release(struct inode *inode, struct file *file) -+{ -+ (void)inode; -+ (void)file; -+ -+ vc_cma_set_reserve(0, current->tgid); -+ -+ return 0; -+} -+ -+/**************************************************************************** -+* -+* vc_cma_ioctl -+* -+***************************************************************************/ -+ -+static long vc_cma_ioctl(struct file *file, unsigned int cmd, unsigned long arg) -+{ -+ int rc = 0; -+ -+ (void)cmd; -+ (void)arg; -+ -+ switch (cmd) { -+ case VC_CMA_IOC_RESERVE: -+ rc = vc_cma_set_reserve((unsigned int)arg, current->tgid); -+ if (rc >= 0) -+ rc = 0; -+ break; -+ default: -+ LOG_ERR("vc-cma: Unknown ioctl %x", cmd); -+ return -ENOTTY; -+ } -+ -+ return rc; -+} -+ -+/**************************************************************************** -+* -+* File Operations for the driver. -+* -+***************************************************************************/ -+ -+static const struct file_operations vc_cma_fops = { -+ .owner = THIS_MODULE, -+ .open = vc_cma_open, -+ .release = vc_cma_release, -+ .unlocked_ioctl = vc_cma_ioctl, -+}; -+ -+/**************************************************************************** -+* -+* vc_cma_proc_open -+* -+***************************************************************************/ -+ -+static int vc_cma_show_info(struct seq_file *m, void *v) -+{ -+ int i; -+ -+ seq_printf(m, "Videocore CMA:\n"); -+ seq_printf(m, " Base : %08x\n", (unsigned int)vc_cma_base); -+ seq_printf(m, " Length : %08x\n", vc_cma_size); -+ seq_printf(m, " Initial : %08x\n", vc_cma_initial); -+ seq_printf(m, " Chunk size : %08x\n", VC_CMA_CHUNK_SIZE); -+ seq_printf(m, " Chunks : %4d (%d bytes)\n", -+ (int)vc_cma_chunks, -+ (int)(vc_cma_chunks * VC_CMA_CHUNK_SIZE)); -+ seq_printf(m, " Used : %4d (%d bytes)\n", -+ (int)vc_cma_chunks_used, -+ (int)(vc_cma_chunks_used * VC_CMA_CHUNK_SIZE)); -+ seq_printf(m, " Reserved : %4d (%d bytes)\n", -+ (unsigned int)vc_cma_chunks_reserved, -+ (int)(vc_cma_chunks_reserved * VC_CMA_CHUNK_SIZE)); -+ -+ for (i = 0; i < vc_cma_reserve_count; i++) { -+ struct vc_cma_reserve_user *user = &vc_cma_reserve_users[i]; -+ seq_printf(m, " PID %5d: %d bytes\n", user->pid, -+ user->reserve); -+ } -+ seq_printf(m, " dma_alloc : %p (%d pages)\n", -+ vc_cma_dma_alloc ? page_address(vc_cma_dma_alloc) : 0, -+ vc_cma_dma_size); -+ -+ seq_printf(m, "\n"); -+ -+ return 0; -+} -+ -+static int vc_cma_proc_open(struct inode *inode, struct file *file) -+{ -+ return single_open(file, vc_cma_show_info, NULL); -+} -+ -+/**************************************************************************** -+* -+* vc_cma_proc_write -+* -+***************************************************************************/ -+ -+static int vc_cma_proc_write(struct file *file, -+ const char __user *buffer, -+ size_t size, loff_t *ppos) -+{ -+ int rc = -EFAULT; -+ char input_str[20]; -+ -+ memset(input_str, 0, sizeof(input_str)); -+ -+ if (size > sizeof(input_str)) { -+ LOG_ERR("%s: input string length too long", __func__); -+ goto out; -+ } -+ -+ if (copy_from_user(input_str, buffer, size - 1)) { -+ LOG_ERR("%s: failed to get input string", __func__); -+ goto out; -+ } -+#define ALLOC_STR "alloc" -+#define FREE_STR "free" -+#define DEBUG_STR "debug" -+#define RESERVE_STR "reserve" -+#define DMA_ALLOC_STR "dma_alloc" -+#define DMA_FREE_STR "dma_free" -+ if (strncmp(input_str, ALLOC_STR, strlen(ALLOC_STR)) == 0) { -+ int alloc_size; -+ char *p = input_str + strlen(ALLOC_STR); -+ -+ while (*p == ' ') -+ p++; -+ alloc_size = memparse(p, NULL); -+ LOG_INFO("/proc/vc-cma: alloc %d", alloc_size); -+ if (alloc_size) -+ send_vc_msg(VC_CMA_MSG_REQUEST_FREE, -+ alloc_size / VC_CMA_CHUNK_SIZE, 0); -+ else -+ LOG_ERR("invalid size '%s'", p); -+ rc = size; -+ } else if (strncmp(input_str, FREE_STR, strlen(FREE_STR)) == 0) { -+ int alloc_size; -+ char *p = input_str + strlen(FREE_STR); -+ -+ while (*p == ' ') -+ p++; -+ alloc_size = memparse(p, NULL); -+ LOG_INFO("/proc/vc-cma: free %d", alloc_size); -+ if (alloc_size) -+ send_vc_msg(VC_CMA_MSG_REQUEST_ALLOC, -+ alloc_size / VC_CMA_CHUNK_SIZE, 0); -+ else -+ LOG_ERR("invalid size '%s'", p); -+ rc = size; -+ } else if (strncmp(input_str, DEBUG_STR, strlen(DEBUG_STR)) == 0) { -+ char *p = input_str + strlen(DEBUG_STR); -+ while (*p == ' ') -+ p++; -+ if ((strcmp(p, "on") == 0) || (strcmp(p, "1") == 0)) -+ vc_cma_debug = 1; -+ else if ((strcmp(p, "off") == 0) || (strcmp(p, "0") == 0)) -+ vc_cma_debug = 0; -+ LOG_INFO("/proc/vc-cma: debug %s", vc_cma_debug ? "on" : "off"); -+ rc = size; -+ } else if (strncmp(input_str, RESERVE_STR, strlen(RESERVE_STR)) == 0) { -+ int alloc_size; -+ int reserved; -+ char *p = input_str + strlen(RESERVE_STR); -+ while (*p == ' ') -+ p++; -+ alloc_size = memparse(p, NULL); -+ -+ reserved = vc_cma_set_reserve(alloc_size, current->tgid); -+ rc = (reserved >= 0) ? size : reserved; -+ } else if (strncmp(input_str, DMA_ALLOC_STR, strlen(DMA_ALLOC_STR)) == 0) { -+ int alloc_size; -+ char *p = input_str + strlen(DMA_ALLOC_STR); -+ while (*p == ' ') -+ p++; -+ alloc_size = memparse(p, NULL); -+ -+ if (vc_cma_dma_alloc) { -+ dma_release_from_contiguous(NULL, vc_cma_dma_alloc, -+ vc_cma_dma_size); -+ vc_cma_dma_alloc = NULL; -+ vc_cma_dma_size = 0; -+ } -+ vc_cma_dma_alloc = dma_alloc_from_contiguous(NULL, alloc_size, 0); -+ vc_cma_dma_size = (vc_cma_dma_alloc ? alloc_size : 0); -+ if (vc_cma_dma_alloc) -+ LOG_INFO("dma_alloc(%d pages) -> %p", alloc_size, page_address(vc_cma_dma_alloc)); -+ else -+ LOG_ERR("dma_alloc(%d pages) failed", alloc_size); -+ rc = size; -+ } else if (strncmp(input_str, DMA_FREE_STR, strlen(DMA_FREE_STR)) == 0) { -+ if (vc_cma_dma_alloc) { -+ dma_release_from_contiguous(NULL, vc_cma_dma_alloc, -+ vc_cma_dma_size); -+ vc_cma_dma_alloc = NULL; -+ vc_cma_dma_size = 0; -+ } -+ rc = size; -+ } -+ -+out: -+ return rc; -+} -+ -+/**************************************************************************** -+* -+* File Operations for /proc interface. -+* -+***************************************************************************/ -+ -+static const struct file_operations vc_cma_proc_fops = { -+ .open = vc_cma_proc_open, -+ .read = seq_read, -+ .write = vc_cma_proc_write, -+ .llseek = seq_lseek, -+ .release = single_release -+}; -+ -+static int vc_cma_set_reserve(unsigned int reserve, unsigned int pid) -+{ -+ struct vc_cma_reserve_user *user = NULL; -+ int delta = 0; -+ int i; -+ -+ if (down_interruptible(&vc_cma_reserve_mutex)) -+ return -ERESTARTSYS; -+ -+ for (i = 0; i < vc_cma_reserve_count; i++) { -+ if (pid == vc_cma_reserve_users[i].pid) { -+ user = &vc_cma_reserve_users[i]; -+ delta = reserve - user->reserve; -+ if (reserve) -+ user->reserve = reserve; -+ else { -+ /* Remove this entry by copying downwards */ -+ while ((i + 1) < vc_cma_reserve_count) { -+ user[0].pid = user[1].pid; -+ user[0].reserve = user[1].reserve; -+ user++; -+ i++; -+ } -+ vc_cma_reserve_count--; -+ user = NULL; -+ } -+ break; -+ } -+ } -+ -+ if (reserve && !user) { -+ if (vc_cma_reserve_count == VC_CMA_RESERVE_COUNT_MAX) { -+ LOG_ERR("vc-cma: Too many reservations - " -+ "increase CMA_RESERVE_COUNT_MAX"); -+ up(&vc_cma_reserve_mutex); -+ return -EBUSY; -+ } -+ user = &vc_cma_reserve_users[vc_cma_reserve_count]; -+ user->pid = pid; -+ user->reserve = reserve; -+ delta = reserve; -+ vc_cma_reserve_count++; -+ } -+ -+ vc_cma_reserve_total += delta; -+ -+ send_vc_msg(VC_CMA_MSG_RESERVE, -+ vc_cma_reserve_total & 0xffff, vc_cma_reserve_total >> 16); -+ -+ send_worker_msg((VCHIQ_HEADER_T *) VC_CMA_MSG_UPDATE_RESERVE); -+ -+ LOG_DBG("/proc/vc-cma: reserve %d (PID %d) - total %u", -+ reserve, pid, vc_cma_reserve_total); -+ -+ up(&vc_cma_reserve_mutex); -+ -+ return vc_cma_reserve_total; -+} -+ -+static VCHIQ_STATUS_T cma_service_callback(VCHIQ_REASON_T reason, -+ VCHIQ_HEADER_T * header, -+ VCHIQ_SERVICE_HANDLE_T service, -+ void *bulk_userdata) -+{ -+ switch (reason) { -+ case VCHIQ_MESSAGE_AVAILABLE: -+ if (!send_worker_msg(header)) -+ return VCHIQ_RETRY; -+ break; -+ case VCHIQ_SERVICE_CLOSED: -+ LOG_DBG("CMA service closed"); -+ break; -+ default: -+ LOG_ERR("Unexpected CMA callback reason %d", reason); -+ break; -+ } -+ return VCHIQ_SUCCESS; -+} -+ -+static void send_vc_msg(unsigned short type, -+ unsigned short param1, unsigned short param2) -+{ -+ unsigned short msg[] = { type, param1, param2 }; -+ VCHIQ_ELEMENT_T elem = { &msg, sizeof(msg) }; -+ VCHIQ_STATUS_T ret; -+ vchiq_use_service(cma_service); -+ ret = vchiq_queue_message(cma_service, &elem, 1); -+ vchiq_release_service(cma_service); -+ if (ret != VCHIQ_SUCCESS) -+ LOG_ERR("vchiq_queue_message returned %x", ret); -+} -+ -+static bool send_worker_msg(VCHIQ_HEADER_T * msg) -+{ -+ if (down_interruptible(&vc_cma_worker_queue_push_mutex)) -+ return false; -+ vchiu_queue_push(&cma_msg_queue, msg); -+ up(&vc_cma_worker_queue_push_mutex); -+ return true; -+} -+ -+static int vc_cma_alloc_chunks(int num_chunks, struct cma_msg *reply) -+{ -+ int i; -+ for (i = 0; i < num_chunks; i++) { -+ struct page *chunk; -+ unsigned int chunk_num; -+ uint8_t *chunk_addr; -+ size_t chunk_size = PAGES_PER_CHUNK << PAGE_SHIFT; -+ -+ chunk = dma_alloc_from_contiguous(&vc_cma_device.dev, -+ PAGES_PER_CHUNK, -+ VC_CMA_CHUNK_ORDER); -+ if (!chunk) -+ break; -+ -+ chunk_addr = page_address(chunk); -+ dmac_flush_range(chunk_addr, chunk_addr + chunk_size); -+ outer_inv_range(__pa(chunk_addr), __pa(chunk_addr) + -+ chunk_size); -+ -+ chunk_num = -+ (page_to_phys(chunk) - vc_cma_base) / VC_CMA_CHUNK_SIZE; -+ BUG_ON(((page_to_phys(chunk) - vc_cma_base) % -+ VC_CMA_CHUNK_SIZE) != 0); -+ if (chunk_num >= vc_cma_chunks) { -+ phys_addr_t _pa = vc_cma_base + vc_cma_size - 1; -+ LOG_ERR("%s: ===============================", -+ __func__); -+ LOG_ERR("%s: chunk phys %x, vc_cma %pa-%pa - " -+ "bad SPARSEMEM configuration?", -+ __func__, (unsigned int)page_to_phys(chunk), -+ &vc_cma_base, &_pa); -+ LOG_ERR("%s: dev->cma_area = %p", __func__, -+ (void*)0/*vc_cma_device.dev.cma_area*/); -+ LOG_ERR("%s: ===============================", -+ __func__); -+ break; -+ } -+ reply->params[i] = chunk_num; -+ vc_cma_chunks_used++; -+ } -+ -+ if (i < num_chunks) { -+ LOG_ERR("%s: dma_alloc_from_contiguous failed " -+ "for %x bytes (alloc %d of %d, %d free)", -+ __func__, VC_CMA_CHUNK_SIZE, i, -+ num_chunks, vc_cma_chunks - vc_cma_chunks_used); -+ num_chunks = i; -+ } -+ -+ LOG_DBG("CMA allocated %d chunks -> %d used", -+ num_chunks, vc_cma_chunks_used); -+ reply->type = VC_CMA_MSG_ALLOCATED; -+ -+ { -+ VCHIQ_ELEMENT_T elem = { -+ reply, -+ offsetof(struct cma_msg, params[0]) + -+ num_chunks * sizeof(reply->params[0]) -+ }; -+ VCHIQ_STATUS_T ret; -+ vchiq_use_service(cma_service); -+ ret = vchiq_queue_message(cma_service, &elem, 1); -+ vchiq_release_service(cma_service); -+ if (ret != VCHIQ_SUCCESS) -+ LOG_ERR("vchiq_queue_message return " "%x", ret); -+ } -+ -+ return num_chunks; -+} -+ -+static int cma_worker_proc(void *param) -+{ -+ static struct cma_msg reply; -+ (void)param; -+ -+ while (1) { -+ VCHIQ_HEADER_T *msg; -+ static struct cma_msg msg_copy; -+ struct cma_msg *cma_msg = &msg_copy; -+ int type, msg_size; -+ -+ msg = vchiu_queue_pop(&cma_msg_queue); -+ if ((unsigned int)msg >= VC_CMA_MSG_MAX) { -+ msg_size = msg->size; -+ memcpy(&msg_copy, msg->data, msg_size); -+ type = cma_msg->type; -+ vchiq_release_message(cma_service, msg); -+ } else { -+ msg_size = 0; -+ type = (int)msg; -+ if (type == VC_CMA_MSG_QUIT) -+ break; -+ else if (type == VC_CMA_MSG_UPDATE_RESERVE) { -+ msg = NULL; -+ cma_msg = NULL; -+ } else { -+ BUG(); -+ continue; -+ } -+ } -+ -+ switch (type) { -+ case VC_CMA_MSG_ALLOC:{ -+ int num_chunks, free_chunks; -+ num_chunks = cma_msg->params[0]; -+ free_chunks = -+ vc_cma_chunks - vc_cma_chunks_used; -+ LOG_DBG("CMA_MSG_ALLOC(%d chunks)", num_chunks); -+ if (num_chunks > VC_CMA_MAX_PARAMS_PER_MSG) { -+ LOG_ERR -+ ("CMA_MSG_ALLOC - chunk count (%d) " -+ "exceeds VC_CMA_MAX_PARAMS_PER_MSG (%d)", -+ num_chunks, -+ VC_CMA_MAX_PARAMS_PER_MSG); -+ num_chunks = VC_CMA_MAX_PARAMS_PER_MSG; -+ } -+ -+ if (num_chunks > free_chunks) { -+ LOG_ERR -+ ("CMA_MSG_ALLOC - chunk count (%d) " -+ "exceeds free chunks (%d)", -+ num_chunks, free_chunks); -+ num_chunks = free_chunks; -+ } -+ -+ vc_cma_alloc_chunks(num_chunks, &reply); -+ } -+ break; -+ -+ case VC_CMA_MSG_FREE:{ -+ int chunk_count = -+ (msg_size - -+ offsetof(struct cma_msg, -+ params)) / -+ sizeof(cma_msg->params[0]); -+ int i; -+ BUG_ON(chunk_count <= 0); -+ -+ LOG_DBG("CMA_MSG_FREE(%d chunks - %x, ...)", -+ chunk_count, cma_msg->params[0]); -+ for (i = 0; i < chunk_count; i++) { -+ int chunk_num = cma_msg->params[i]; -+ struct page *page = vc_cma_base_page + -+ chunk_num * PAGES_PER_CHUNK; -+ if (chunk_num >= vc_cma_chunks) { -+ LOG_ERR -+ ("CMA_MSG_FREE - chunk %d of %d" -+ " (value %x) exceeds maximum " -+ "(%x)", i, chunk_count, -+ chunk_num, -+ vc_cma_chunks - 1); -+ break; -+ } -+ -+ if (!dma_release_from_contiguous -+ (&vc_cma_device.dev, page, -+ PAGES_PER_CHUNK)) { -+ phys_addr_t _pa = page_to_phys(page); -+ LOG_ERR -+ ("CMA_MSG_FREE - failed to " -+ "release chunk %d (phys %pa, " -+ "page %x)", chunk_num, -+ &_pa, -+ (unsigned int)page); -+ } -+ vc_cma_chunks_used--; -+ } -+ LOG_DBG("CMA released %d chunks -> %d used", -+ i, vc_cma_chunks_used); -+ } -+ break; -+ -+ case VC_CMA_MSG_UPDATE_RESERVE:{ -+ int chunks_needed = -+ ((vc_cma_reserve_total + VC_CMA_CHUNK_SIZE - -+ 1) -+ / VC_CMA_CHUNK_SIZE) - -+ vc_cma_chunks_reserved; -+ -+ LOG_DBG -+ ("CMA_MSG_UPDATE_RESERVE(%d chunks needed)", -+ chunks_needed); -+ -+ /* Cap the reservations to what is available */ -+ if (chunks_needed > 0) { -+ if (chunks_needed > -+ (vc_cma_chunks - -+ vc_cma_chunks_used)) -+ chunks_needed = -+ (vc_cma_chunks - -+ vc_cma_chunks_used); -+ -+ chunks_needed = -+ vc_cma_alloc_chunks(chunks_needed, -+ &reply); -+ } -+ -+ LOG_DBG -+ ("CMA_MSG_UPDATE_RESERVE(%d chunks allocated)", -+ chunks_needed); -+ vc_cma_chunks_reserved += chunks_needed; -+ } -+ break; -+ -+ default: -+ LOG_ERR("unexpected msg type %d", type); -+ break; -+ } -+ } -+ -+ LOG_DBG("quitting..."); -+ return 0; -+} -+ -+/**************************************************************************** -+* -+* vc_cma_connected_init -+* -+* This function is called once the videocore has been connected. -+* -+***************************************************************************/ -+ -+static void vc_cma_connected_init(void) -+{ -+ VCHIQ_SERVICE_PARAMS_T service_params; -+ -+ LOG_DBG("vc_cma_connected_init"); -+ -+ if (!vchiu_queue_init(&cma_msg_queue, 16)) { -+ LOG_ERR("could not create CMA msg queue"); -+ goto fail_queue; -+ } -+ -+ if (vchiq_initialise(&cma_instance) != VCHIQ_SUCCESS) -+ goto fail_vchiq_init; -+ -+ vchiq_connect(cma_instance); -+ -+ service_params.fourcc = VC_CMA_FOURCC; -+ service_params.callback = cma_service_callback; -+ service_params.userdata = NULL; -+ service_params.version = VC_CMA_VERSION; -+ service_params.version_min = VC_CMA_VERSION; -+ -+ if (vchiq_open_service(cma_instance, &service_params, -+ &cma_service) != VCHIQ_SUCCESS) { -+ LOG_ERR("failed to open service - already in use?"); -+ goto fail_vchiq_open; -+ } -+ -+ vchiq_release_service(cma_service); -+ -+ cma_worker = kthread_create(cma_worker_proc, NULL, "cma_worker"); -+ if (!cma_worker) { -+ LOG_ERR("could not create CMA worker thread"); -+ goto fail_worker; -+ } -+ set_user_nice(cma_worker, -20); -+ wake_up_process(cma_worker); -+ -+ return; -+ -+fail_worker: -+ vchiq_close_service(cma_service); -+fail_vchiq_open: -+ vchiq_shutdown(cma_instance); -+fail_vchiq_init: -+ vchiu_queue_delete(&cma_msg_queue); -+fail_queue: -+ return; -+} -+ -+void -+loud_error_header(void) -+{ -+ if (in_loud_error) -+ return; -+ -+ LOG_ERR("============================================================" -+ "================"); -+ LOG_ERR("============================================================" -+ "================"); -+ LOG_ERR("====="); -+ -+ in_loud_error = 1; -+} -+ -+void -+loud_error_footer(void) -+{ -+ if (!in_loud_error) -+ return; -+ -+ LOG_ERR("====="); -+ LOG_ERR("============================================================" -+ "================"); -+ LOG_ERR("============================================================" -+ "================"); -+ -+ in_loud_error = 0; -+} -+ -+#if 1 -+static int check_cma_config(void) { return 1; } -+#else -+static int -+read_vc_debug_var(VC_MEM_ACCESS_HANDLE_T handle, -+ const char *symbol, -+ void *buf, size_t bufsize) -+{ -+ VC_MEM_ADDR_T vcMemAddr; -+ size_t vcMemSize; -+ uint8_t *mapAddr; -+ off_t vcMapAddr; -+ -+ if (!LookupVideoCoreSymbol(handle, symbol, -+ &vcMemAddr, -+ &vcMemSize)) { -+ loud_error_header(); -+ loud_error( -+ "failed to find VC symbol \"%s\".", -+ symbol); -+ loud_error_footer(); -+ return 0; -+ } -+ -+ if (vcMemSize != bufsize) { -+ loud_error_header(); -+ loud_error( -+ "VC symbol \"%s\" is the wrong size.", -+ symbol); -+ loud_error_footer(); -+ return 0; -+ } -+ -+ vcMapAddr = (off_t)vcMemAddr & VC_MEM_TO_ARM_ADDR_MASK; -+ vcMapAddr += mm_vc_mem_phys_addr; -+ mapAddr = ioremap_nocache(vcMapAddr, vcMemSize); -+ if (mapAddr == 0) { -+ loud_error_header(); -+ loud_error( -+ "failed to ioremap \"%s\" @ 0x%x " -+ "(phys: 0x%x, size: %u).", -+ symbol, -+ (unsigned int)vcMapAddr, -+ (unsigned int)vcMemAddr, -+ (unsigned int)vcMemSize); -+ loud_error_footer(); -+ return 0; -+ } -+ -+ memcpy(buf, mapAddr, bufsize); -+ iounmap(mapAddr); -+ -+ return 1; -+} -+ -+ -+static int -+check_cma_config(void) -+{ -+ VC_MEM_ACCESS_HANDLE_T mem_hndl; -+ VC_MEM_ADDR_T mempool_start; -+ VC_MEM_ADDR_T mempool_end; -+ VC_MEM_ADDR_T mempool_offline_start; -+ VC_MEM_ADDR_T mempool_offline_end; -+ VC_MEM_ADDR_T cam_alloc_base; -+ VC_MEM_ADDR_T cam_alloc_size; -+ VC_MEM_ADDR_T cam_alloc_end; -+ int success = 0; -+ -+ if (OpenVideoCoreMemory(&mem_hndl) != 0) -+ goto out; -+ -+ /* Read the relevant VideoCore variables */ -+ if (!read_vc_debug_var(mem_hndl, "__MEMPOOL_START", -+ &mempool_start, -+ sizeof(mempool_start))) -+ goto close; -+ -+ if (!read_vc_debug_var(mem_hndl, "__MEMPOOL_END", -+ &mempool_end, -+ sizeof(mempool_end))) -+ goto close; -+ -+ if (!read_vc_debug_var(mem_hndl, "__MEMPOOL_OFFLINE_START", -+ &mempool_offline_start, -+ sizeof(mempool_offline_start))) -+ goto close; -+ -+ if (!read_vc_debug_var(mem_hndl, "__MEMPOOL_OFFLINE_END", -+ &mempool_offline_end, -+ sizeof(mempool_offline_end))) -+ goto close; -+ -+ if (!read_vc_debug_var(mem_hndl, "cam_alloc_base", -+ &cam_alloc_base, -+ sizeof(cam_alloc_base))) -+ goto close; -+ -+ if (!read_vc_debug_var(mem_hndl, "cam_alloc_size", -+ &cam_alloc_size, -+ sizeof(cam_alloc_size))) -+ goto close; -+ -+ cam_alloc_end = cam_alloc_base + cam_alloc_size; -+ -+ success = 1; -+ -+ /* Now the sanity checks */ -+ if (!mempool_offline_start) -+ mempool_offline_start = mempool_start; -+ if (!mempool_offline_end) -+ mempool_offline_end = mempool_end; -+ -+ if (VCADDR_TO_PHYSADDR(mempool_offline_start) != vc_cma_base) { -+ loud_error_header(); -+ loud_error( -+ "__MEMPOOL_OFFLINE_START(%x -> %lx) doesn't match " -+ "vc_cma_base(%x)", -+ mempool_offline_start, -+ VCADDR_TO_PHYSADDR(mempool_offline_start), -+ vc_cma_base); -+ success = 0; -+ } -+ -+ if (VCADDR_TO_PHYSADDR(mempool_offline_end) != -+ (vc_cma_base + vc_cma_size)) { -+ loud_error_header(); -+ loud_error( -+ "__MEMPOOL_OFFLINE_END(%x -> %lx) doesn't match " -+ "vc_cma_base(%x) + vc_cma_size(%x) = %x", -+ mempool_offline_start, -+ VCADDR_TO_PHYSADDR(mempool_offline_end), -+ vc_cma_base, vc_cma_size, vc_cma_base + vc_cma_size); -+ success = 0; -+ } -+ -+ if (mempool_end < mempool_start) { -+ loud_error_header(); -+ loud_error( -+ "__MEMPOOL_END(%x) must not be before " -+ "__MEMPOOL_START(%x)", -+ mempool_end, -+ mempool_start); -+ success = 0; -+ } -+ -+ if (mempool_offline_end < mempool_offline_start) { -+ loud_error_header(); -+ loud_error( -+ "__MEMPOOL_OFFLINE_END(%x) must not be before " -+ "__MEMPOOL_OFFLINE_START(%x)", -+ mempool_offline_end, -+ mempool_offline_start); -+ success = 0; -+ } -+ -+ if (mempool_offline_start < mempool_start) { -+ loud_error_header(); -+ loud_error( -+ "__MEMPOOL_OFFLINE_START(%x) must not be before " -+ "__MEMPOOL_START(%x)", -+ mempool_offline_start, -+ mempool_start); -+ success = 0; -+ } -+ -+ if (mempool_offline_end > mempool_end) { -+ loud_error_header(); -+ loud_error( -+ "__MEMPOOL_OFFLINE_END(%x) must not be after " -+ "__MEMPOOL_END(%x)", -+ mempool_offline_end, -+ mempool_end); -+ success = 0; -+ } -+ -+ if ((cam_alloc_base < mempool_end) && -+ (cam_alloc_end > mempool_start)) { -+ loud_error_header(); -+ loud_error( -+ "cam_alloc pool(%x-%x) overlaps " -+ "mempool(%x-%x)", -+ cam_alloc_base, cam_alloc_end, -+ mempool_start, mempool_end); -+ success = 0; -+ } -+ -+ loud_error_footer(); -+ -+close: -+ CloseVideoCoreMemory(mem_hndl); -+ -+out: -+ return success; -+} -+#endif -+ -+static int vc_cma_init(void) -+{ -+ int rc = -EFAULT; -+ struct device *dev; -+ -+ if (!check_cma_config()) -+ goto out_release; -+ -+ LOG_INFO("vc-cma: Videocore CMA driver"); -+ LOG_INFO("vc-cma: vc_cma_base = %pa", &vc_cma_base); -+ LOG_INFO("vc-cma: vc_cma_size = 0x%08x (%u MiB)", -+ vc_cma_size, vc_cma_size / (1024 * 1024)); -+ LOG_INFO("vc-cma: vc_cma_initial = 0x%08x (%u MiB)", -+ vc_cma_initial, vc_cma_initial / (1024 * 1024)); -+ -+ vc_cma_base_page = phys_to_page(vc_cma_base); -+ -+ if (vc_cma_chunks) { -+ int chunks_needed = vc_cma_initial / VC_CMA_CHUNK_SIZE; -+ -+ for (vc_cma_chunks_used = 0; -+ vc_cma_chunks_used < chunks_needed; vc_cma_chunks_used++) { -+ struct page *chunk; -+ chunk = dma_alloc_from_contiguous(&vc_cma_device.dev, -+ PAGES_PER_CHUNK, -+ VC_CMA_CHUNK_ORDER); -+ if (!chunk) -+ break; -+ BUG_ON(((page_to_phys(chunk) - vc_cma_base) % -+ VC_CMA_CHUNK_SIZE) != 0); -+ } -+ if (vc_cma_chunks_used != chunks_needed) { -+ LOG_ERR("%s: dma_alloc_from_contiguous failed (%d " -+ "bytes, allocation %d of %d)", -+ __func__, VC_CMA_CHUNK_SIZE, -+ vc_cma_chunks_used, chunks_needed); -+ goto out_release; -+ } -+ -+ vchiq_add_connected_callback(vc_cma_connected_init); -+ } -+ -+ rc = alloc_chrdev_region(&vc_cma_devnum, 0, 1, DRIVER_NAME); -+ if (rc < 0) { -+ LOG_ERR("%s: alloc_chrdev_region failed (rc=%d)", __func__, rc); -+ goto out_release; -+ } -+ -+ cdev_init(&vc_cma_cdev, &vc_cma_fops); -+ rc = cdev_add(&vc_cma_cdev, vc_cma_devnum, 1); -+ if (rc != 0) { -+ LOG_ERR("%s: cdev_add failed (rc=%d)", __func__, rc); -+ goto out_unregister; -+ } -+ -+ vc_cma_class = class_create(THIS_MODULE, DRIVER_NAME); -+ if (IS_ERR(vc_cma_class)) { -+ rc = PTR_ERR(vc_cma_class); -+ LOG_ERR("%s: class_create failed (rc=%d)", __func__, rc); -+ goto out_cdev_del; -+ } -+ -+ dev = device_create(vc_cma_class, NULL, vc_cma_devnum, NULL, -+ DRIVER_NAME); -+ if (IS_ERR(dev)) { -+ rc = PTR_ERR(dev); -+ LOG_ERR("%s: device_create failed (rc=%d)", __func__, rc); -+ goto out_class_destroy; -+ } -+ -+ vc_cma_proc_entry = proc_create(DRIVER_NAME, 0444, NULL, &vc_cma_proc_fops); -+ if (vc_cma_proc_entry == NULL) { -+ rc = -EFAULT; -+ LOG_ERR("%s: proc_create failed", __func__); -+ goto out_device_destroy; -+ } -+ -+ vc_cma_inited = 1; -+ return 0; -+ -+out_device_destroy: -+ device_destroy(vc_cma_class, vc_cma_devnum); -+ -+out_class_destroy: -+ class_destroy(vc_cma_class); -+ vc_cma_class = NULL; -+ -+out_cdev_del: -+ cdev_del(&vc_cma_cdev); -+ -+out_unregister: -+ unregister_chrdev_region(vc_cma_devnum, 1); -+ -+out_release: -+ /* It is tempting to try to clean up by calling -+ dma_release_from_contiguous for all allocated chunks, but it isn't -+ a very safe thing to do. If vc_cma_initial is non-zero it is because -+ VideoCore is already using that memory, so giving it back to Linux -+ is likely to be fatal. -+ */ -+ return -1; -+} -+ -+/**************************************************************************** -+* -+* vc_cma_exit -+* -+***************************************************************************/ -+ -+static void __exit vc_cma_exit(void) -+{ -+ LOG_DBG("%s: called", __func__); -+ -+ if (vc_cma_inited) { -+ remove_proc_entry(DRIVER_NAME, NULL); -+ device_destroy(vc_cma_class, vc_cma_devnum); -+ class_destroy(vc_cma_class); -+ cdev_del(&vc_cma_cdev); -+ unregister_chrdev_region(vc_cma_devnum, 1); -+ } -+} -+ -+module_init(vc_cma_init); -+module_exit(vc_cma_exit); -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Broadcom Corporation"); -diff -Nur linux-4.1.13.orig/drivers/char/broadcom/vcio.c linux-rpi/drivers/char/broadcom/vcio.c ---- linux-4.1.13.orig/drivers/char/broadcom/vcio.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/char/broadcom/vcio.c 2015-11-29 09:42:36.707312101 +0100 -@@ -0,0 +1,175 @@ -+/* -+ * Copyright (C) 2010 Broadcom -+ * Copyright (C) 2015 Noralf Trønnes -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+ -+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define MBOX_CHAN_PROPERTY 8 -+ -+#define VCIO_IOC_MAGIC 100 -+#define IOCTL_MBOX_PROPERTY _IOWR(VCIO_IOC_MAGIC, 0, char *) -+ -+static struct { -+ dev_t devt; -+ struct cdev cdev; -+ struct class *class; -+ struct rpi_firmware *fw; -+} vcio; -+ -+static int vcio_user_property_list(void *user) -+{ -+ u32 *buf, size; -+ int ret; -+ -+ /* The first 32-bit is the size of the buffer */ -+ if (copy_from_user(&size, user, sizeof(size))) -+ return -EFAULT; -+ -+ buf = kmalloc(size, GFP_KERNEL); -+ if (!buf) -+ return -ENOMEM; -+ -+ if (copy_from_user(buf, user, size)) { -+ kfree(buf); -+ return -EFAULT; -+ } -+ -+ /* Strip off protocol encapsulation */ -+ ret = rpi_firmware_property_list(vcio.fw, &buf[2], size - 12); -+ if (ret) { -+ kfree(buf); -+ return ret; -+ } -+ -+ buf[1] = RPI_FIRMWARE_STATUS_SUCCESS; -+ if (copy_to_user(user, buf, size)) -+ ret = -EFAULT; -+ -+ kfree(buf); -+ -+ return ret; -+} -+ -+static int vcio_device_open(struct inode *inode, struct file *file) -+{ -+ try_module_get(THIS_MODULE); -+ -+ return 0; -+} -+ -+static int vcio_device_release(struct inode *inode, struct file *file) -+{ -+ module_put(THIS_MODULE); -+ -+ return 0; -+} -+ -+static long vcio_device_ioctl(struct file *file, unsigned int ioctl_num, -+ unsigned long ioctl_param) -+{ -+ switch (ioctl_num) { -+ case IOCTL_MBOX_PROPERTY: -+ return vcio_user_property_list((void *)ioctl_param); -+ default: -+ pr_err("unknown ioctl: %d\n", ioctl_num); -+ return -EINVAL; -+ } -+} -+ -+const struct file_operations vcio_fops = { -+ .unlocked_ioctl = vcio_device_ioctl, -+ .open = vcio_device_open, -+ .release = vcio_device_release, -+}; -+ -+static int __init vcio_init(void) -+{ -+ struct device_node *np; -+ static struct device *dev; -+ int ret; -+ -+ np = of_find_compatible_node(NULL, NULL, -+ "raspberrypi,bcm2835-firmware"); -+/* Uncomment this when we only boot with Device Tree -+ if (!of_device_is_available(np)) -+ return -ENODEV; -+*/ -+ vcio.fw = rpi_firmware_get(np); -+ if (!vcio.fw) -+ return -ENODEV; -+ -+ ret = alloc_chrdev_region(&vcio.devt, 0, 1, "vcio"); -+ if (ret) { -+ pr_err("failed to allocate device number\n"); -+ return ret; -+ } -+ -+ cdev_init(&vcio.cdev, &vcio_fops); -+ vcio.cdev.owner = THIS_MODULE; -+ ret = cdev_add(&vcio.cdev, vcio.devt, 1); -+ if (ret) { -+ pr_err("failed to register device\n"); -+ goto err_unregister_chardev; -+ } -+ -+ /* -+ * Create sysfs entries -+ * 'bcm2708_vcio' is used for backwards compatibility so we don't break -+ * userspace. Raspian has a udev rule that changes the permissions. -+ */ -+ vcio.class = class_create(THIS_MODULE, "bcm2708_vcio"); -+ if (IS_ERR(vcio.class)) { -+ ret = PTR_ERR(vcio.class); -+ pr_err("failed to create class\n"); -+ goto err_cdev_del; -+ } -+ -+ dev = device_create(vcio.class, NULL, vcio.devt, NULL, "vcio"); -+ if (IS_ERR(dev)) { -+ ret = PTR_ERR(dev); -+ pr_err("failed to create device\n"); -+ goto err_class_destroy; -+ } -+ -+ return 0; -+ -+err_class_destroy: -+ class_destroy(vcio.class); -+err_cdev_del: -+ cdev_del(&vcio.cdev); -+err_unregister_chardev: -+ unregister_chrdev_region(vcio.devt, 1); -+ -+ return ret; -+} -+module_init(vcio_init); -+ -+static void __exit vcio_exit(void) -+{ -+ device_destroy(vcio.class, vcio.devt); -+ class_destroy(vcio.class); -+ cdev_del(&vcio.cdev); -+ unregister_chrdev_region(vcio.devt, 1); -+} -+module_exit(vcio_exit); -+ -+MODULE_AUTHOR("Gray Girling"); -+MODULE_AUTHOR("Noralf Trønnes"); -+MODULE_DESCRIPTION("Mailbox userspace access"); -+MODULE_LICENSE("GPL"); -diff -Nur linux-4.1.13.orig/drivers/char/broadcom/vc_mem.c linux-rpi/drivers/char/broadcom/vc_mem.c ---- linux-4.1.13.orig/drivers/char/broadcom/vc_mem.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/char/broadcom/vc_mem.c 2015-11-29 09:42:36.703312367 +0100 -@@ -0,0 +1,422 @@ -+/***************************************************************************** -+* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved. -+* -+* Unless you and Broadcom execute a separate written software license -+* agreement governing use of this software, this software is licensed to you -+* under the terms of the GNU General Public License version 2, available at -+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -+* -+* Notwithstanding the above, under no circumstances may you combine this -+* software in any way with any other Broadcom software provided under a -+* license other than the GPL, without Broadcom's express prior written -+* consent. -+*****************************************************************************/ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define DRIVER_NAME "vc-mem" -+ -+// Device (/dev) related variables -+static dev_t vc_mem_devnum = 0; -+static struct class *vc_mem_class = NULL; -+static struct cdev vc_mem_cdev; -+static int vc_mem_inited = 0; -+ -+#ifdef CONFIG_DEBUG_FS -+static struct dentry *vc_mem_debugfs_entry; -+#endif -+ -+/* -+ * Videocore memory addresses and size -+ * -+ * Drivers that wish to know the videocore memory addresses and sizes should -+ * use these variables instead of the MM_IO_BASE and MM_ADDR_IO defines in -+ * headers. This allows the other drivers to not be tied down to a a certain -+ * address/size at compile time. -+ * -+ * In the future, the goal is to have the videocore memory virtual address and -+ * size be calculated at boot time rather than at compile time. The decision of -+ * where the videocore memory resides and its size would be in the hands of the -+ * bootloader (and/or kernel). When that happens, the values of these variables -+ * would be calculated and assigned in the init function. -+ */ -+// in the 2835 VC in mapped above ARM, but ARM has full access to VC space -+unsigned long mm_vc_mem_phys_addr = 0x00000000; -+unsigned int mm_vc_mem_size = 0; -+unsigned int mm_vc_mem_base = 0; -+ -+EXPORT_SYMBOL(mm_vc_mem_phys_addr); -+EXPORT_SYMBOL(mm_vc_mem_size); -+EXPORT_SYMBOL(mm_vc_mem_base); -+ -+static uint phys_addr = 0; -+static uint mem_size = 0; -+static uint mem_base = 0; -+ -+ -+/**************************************************************************** -+* -+* vc_mem_open -+* -+***************************************************************************/ -+ -+static int -+vc_mem_open(struct inode *inode, struct file *file) -+{ -+ (void) inode; -+ (void) file; -+ -+ pr_debug("%s: called file = 0x%p\n", __func__, file); -+ -+ return 0; -+} -+ -+/**************************************************************************** -+* -+* vc_mem_release -+* -+***************************************************************************/ -+ -+static int -+vc_mem_release(struct inode *inode, struct file *file) -+{ -+ (void) inode; -+ (void) file; -+ -+ pr_debug("%s: called file = 0x%p\n", __func__, file); -+ -+ return 0; -+} -+ -+/**************************************************************************** -+* -+* vc_mem_get_size -+* -+***************************************************************************/ -+ -+static void -+vc_mem_get_size(void) -+{ -+} -+ -+/**************************************************************************** -+* -+* vc_mem_get_base -+* -+***************************************************************************/ -+ -+static void -+vc_mem_get_base(void) -+{ -+} -+ -+/**************************************************************************** -+* -+* vc_mem_get_current_size -+* -+***************************************************************************/ -+ -+int -+vc_mem_get_current_size(void) -+{ -+ return mm_vc_mem_size; -+} -+ -+EXPORT_SYMBOL_GPL(vc_mem_get_current_size); -+ -+/**************************************************************************** -+* -+* vc_mem_ioctl -+* -+***************************************************************************/ -+ -+static long -+vc_mem_ioctl(struct file *file, unsigned int cmd, unsigned long arg) -+{ -+ int rc = 0; -+ -+ (void) cmd; -+ (void) arg; -+ -+ pr_debug("%s: called file = 0x%p\n", __func__, file); -+ -+ switch (cmd) { -+ case VC_MEM_IOC_MEM_PHYS_ADDR: -+ { -+ pr_debug("%s: VC_MEM_IOC_MEM_PHYS_ADDR=0x%p\n", -+ __func__, (void *) mm_vc_mem_phys_addr); -+ -+ if (copy_to_user((void *) arg, &mm_vc_mem_phys_addr, -+ sizeof (mm_vc_mem_phys_addr)) != 0) { -+ rc = -EFAULT; -+ } -+ break; -+ } -+ case VC_MEM_IOC_MEM_SIZE: -+ { -+ // Get the videocore memory size first -+ vc_mem_get_size(); -+ -+ pr_debug("%s: VC_MEM_IOC_MEM_SIZE=%u\n", __func__, -+ mm_vc_mem_size); -+ -+ if (copy_to_user((void *) arg, &mm_vc_mem_size, -+ sizeof (mm_vc_mem_size)) != 0) { -+ rc = -EFAULT; -+ } -+ break; -+ } -+ case VC_MEM_IOC_MEM_BASE: -+ { -+ // Get the videocore memory base -+ vc_mem_get_base(); -+ -+ pr_debug("%s: VC_MEM_IOC_MEM_BASE=%u\n", __func__, -+ mm_vc_mem_base); -+ -+ if (copy_to_user((void *) arg, &mm_vc_mem_base, -+ sizeof (mm_vc_mem_base)) != 0) { -+ rc = -EFAULT; -+ } -+ break; -+ } -+ case VC_MEM_IOC_MEM_LOAD: -+ { -+ // Get the videocore memory base -+ vc_mem_get_base(); -+ -+ pr_debug("%s: VC_MEM_IOC_MEM_LOAD=%u\n", __func__, -+ mm_vc_mem_base); -+ -+ if (copy_to_user((void *) arg, &mm_vc_mem_base, -+ sizeof (mm_vc_mem_base)) != 0) { -+ rc = -EFAULT; -+ } -+ break; -+ } -+ default: -+ { -+ return -ENOTTY; -+ } -+ } -+ pr_debug("%s: file = 0x%p returning %d\n", __func__, file, rc); -+ -+ return rc; -+} -+ -+/**************************************************************************** -+* -+* vc_mem_mmap -+* -+***************************************************************************/ -+ -+static int -+vc_mem_mmap(struct file *filp, struct vm_area_struct *vma) -+{ -+ int rc = 0; -+ unsigned long length = vma->vm_end - vma->vm_start; -+ unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; -+ -+ pr_debug("%s: vm_start = 0x%08lx vm_end = 0x%08lx vm_pgoff = 0x%08lx\n", -+ __func__, (long) vma->vm_start, (long) vma->vm_end, -+ (long) vma->vm_pgoff); -+ -+ if (offset + length > mm_vc_mem_size) { -+ pr_err("%s: length %ld is too big\n", __func__, length); -+ return -EINVAL; -+ } -+ // Do not cache the memory map -+ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); -+ -+ rc = remap_pfn_range(vma, vma->vm_start, -+ (mm_vc_mem_phys_addr >> PAGE_SHIFT) + -+ vma->vm_pgoff, length, vma->vm_page_prot); -+ if (rc != 0) { -+ pr_err("%s: remap_pfn_range failed (rc=%d)\n", __func__, rc); -+ } -+ -+ return rc; -+} -+ -+/**************************************************************************** -+* -+* File Operations for the driver. -+* -+***************************************************************************/ -+ -+static const struct file_operations vc_mem_fops = { -+ .owner = THIS_MODULE, -+ .open = vc_mem_open, -+ .release = vc_mem_release, -+ .unlocked_ioctl = vc_mem_ioctl, -+ .mmap = vc_mem_mmap, -+}; -+ -+#ifdef CONFIG_DEBUG_FS -+static void vc_mem_debugfs_deinit(void) -+{ -+ debugfs_remove_recursive(vc_mem_debugfs_entry); -+ vc_mem_debugfs_entry = NULL; -+} -+ -+ -+static int vc_mem_debugfs_init( -+ struct device *dev) -+{ -+ vc_mem_debugfs_entry = debugfs_create_dir(DRIVER_NAME, NULL); -+ if (!vc_mem_debugfs_entry) { -+ dev_warn(dev, "could not create debugfs entry\n"); -+ return -EFAULT; -+ } -+ -+ if (!debugfs_create_x32("vc_mem_phys_addr", -+ 0444, -+ vc_mem_debugfs_entry, -+ (u32 *)&mm_vc_mem_phys_addr)) { -+ dev_warn(dev, "%s:could not create vc_mem_phys entry\n", -+ __func__); -+ goto fail; -+ } -+ -+ if (!debugfs_create_x32("vc_mem_size", -+ 0444, -+ vc_mem_debugfs_entry, -+ (u32 *)&mm_vc_mem_size)) { -+ dev_warn(dev, "%s:could not create vc_mem_size entry\n", -+ __func__); -+ goto fail; -+ } -+ -+ if (!debugfs_create_x32("vc_mem_base", -+ 0444, -+ vc_mem_debugfs_entry, -+ (u32 *)&mm_vc_mem_base)) { -+ dev_warn(dev, "%s:could not create vc_mem_base entry\n", -+ __func__); -+ goto fail; -+ } -+ -+ return 0; -+ -+fail: -+ vc_mem_debugfs_deinit(); -+ return -EFAULT; -+} -+ -+#endif /* CONFIG_DEBUG_FS */ -+ -+ -+/**************************************************************************** -+* -+* vc_mem_init -+* -+***************************************************************************/ -+ -+static int __init -+vc_mem_init(void) -+{ -+ int rc = -EFAULT; -+ struct device *dev; -+ -+ pr_debug("%s: called\n", __func__); -+ -+ mm_vc_mem_phys_addr = phys_addr; -+ mm_vc_mem_size = mem_size; -+ mm_vc_mem_base = mem_base; -+ -+ vc_mem_get_size(); -+ -+ pr_info("vc-mem: phys_addr:0x%08lx mem_base=0x%08x mem_size:0x%08x(%u MiB)\n", -+ mm_vc_mem_phys_addr, mm_vc_mem_base, mm_vc_mem_size, mm_vc_mem_size / (1024 * 1024)); -+ -+ if ((rc = alloc_chrdev_region(&vc_mem_devnum, 0, 1, DRIVER_NAME)) < 0) { -+ pr_err("%s: alloc_chrdev_region failed (rc=%d)\n", -+ __func__, rc); -+ goto out_err; -+ } -+ -+ cdev_init(&vc_mem_cdev, &vc_mem_fops); -+ if ((rc = cdev_add(&vc_mem_cdev, vc_mem_devnum, 1)) != 0) { -+ pr_err("%s: cdev_add failed (rc=%d)\n", __func__, rc); -+ goto out_unregister; -+ } -+ -+ vc_mem_class = class_create(THIS_MODULE, DRIVER_NAME); -+ if (IS_ERR(vc_mem_class)) { -+ rc = PTR_ERR(vc_mem_class); -+ pr_err("%s: class_create failed (rc=%d)\n", __func__, rc); -+ goto out_cdev_del; -+ } -+ -+ dev = device_create(vc_mem_class, NULL, vc_mem_devnum, NULL, -+ DRIVER_NAME); -+ if (IS_ERR(dev)) { -+ rc = PTR_ERR(dev); -+ pr_err("%s: device_create failed (rc=%d)\n", __func__, rc); -+ goto out_class_destroy; -+ } -+ -+#ifdef CONFIG_DEBUG_FS -+ /* don't fail if the debug entries cannot be created */ -+ vc_mem_debugfs_init(dev); -+#endif -+ -+ vc_mem_inited = 1; -+ return 0; -+ -+ device_destroy(vc_mem_class, vc_mem_devnum); -+ -+ out_class_destroy: -+ class_destroy(vc_mem_class); -+ vc_mem_class = NULL; -+ -+ out_cdev_del: -+ cdev_del(&vc_mem_cdev); -+ -+ out_unregister: -+ unregister_chrdev_region(vc_mem_devnum, 1); -+ -+ out_err: -+ return -1; -+} -+ -+/**************************************************************************** -+* -+* vc_mem_exit -+* -+***************************************************************************/ -+ -+static void __exit -+vc_mem_exit(void) -+{ -+ pr_debug("%s: called\n", __func__); -+ -+ if (vc_mem_inited) { -+#if CONFIG_DEBUG_FS -+ vc_mem_debugfs_deinit(); -+#endif -+ device_destroy(vc_mem_class, vc_mem_devnum); -+ class_destroy(vc_mem_class); -+ cdev_del(&vc_mem_cdev); -+ unregister_chrdev_region(vc_mem_devnum, 1); -+ } -+} -+ -+module_init(vc_mem_init); -+module_exit(vc_mem_exit); -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Broadcom Corporation"); -+ -+module_param(phys_addr, uint, 0644); -+module_param(mem_size, uint, 0644); -+module_param(mem_base, uint, 0644); -diff -Nur linux-4.1.13.orig/drivers/char/broadcom/vc_sm/Makefile linux-rpi/drivers/char/broadcom/vc_sm/Makefile ---- linux-4.1.13.orig/drivers/char/broadcom/vc_sm/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/char/broadcom/vc_sm/Makefile 2015-11-29 09:42:36.703312367 +0100 -@@ -0,0 +1,21 @@ -+EXTRA_CFLAGS += -Wall -Wstrict-prototypes -Wno-trigraphs -O2 -+ -+EXTRA_CFLAGS += -I"./arch/arm/mach-bcm2708/include/mach" -+EXTRA_CFLAGS += -I"drivers/misc/vc04_services" -+EXTRA_CFLAGS += -I"drivers/misc/vc04_services/interface/vchi" -+EXTRA_CFLAGS += -I"drivers/misc/vc04_services/interface/vchiq_arm" -+EXTRA_CFLAGS += -I"$(srctree)/fs/" -+ -+EXTRA_CFLAGS += -DOS_ASSERT_FAILURE -+EXTRA_CFLAGS += -D__STDC_VERSION=199901L -+EXTRA_CFLAGS += -D__STDC_VERSION__=199901L -+EXTRA_CFLAGS += -D__VCCOREVER__=0 -+EXTRA_CFLAGS += -D__KERNEL__ -+EXTRA_CFLAGS += -D__linux__ -+EXTRA_CFLAGS += -Werror -+ -+obj-$(CONFIG_BCM_VC_SM) := vc-sm.o -+ -+vc-sm-objs := \ -+ vmcs_sm.o \ -+ vc_vchi_sm.o -diff -Nur linux-4.1.13.orig/drivers/char/broadcom/vc_sm/vc_vchi_sm.c linux-rpi/drivers/char/broadcom/vc_sm/vc_vchi_sm.c ---- linux-4.1.13.orig/drivers/char/broadcom/vc_sm/vc_vchi_sm.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/char/broadcom/vc_sm/vc_vchi_sm.c 2015-11-29 09:42:36.703312367 +0100 -@@ -0,0 +1,492 @@ -+/***************************************************************************** -+* Copyright 2011-2012 Broadcom Corporation. All rights reserved. -+* -+* Unless you and Broadcom execute a separate written software license -+* agreement governing use of this software, this software is licensed to you -+* under the terms of the GNU General Public License version 2, available at -+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -+* -+* Notwithstanding the above, under no circumstances may you combine this -+* software in any way with any other Broadcom software provided under a -+* license other than the GPL, without Broadcom's express prior written -+* consent. -+*****************************************************************************/ -+ -+/* ---- Include Files ----------------------------------------------------- */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "vc_vchi_sm.h" -+ -+#define VC_SM_VER 1 -+#define VC_SM_MIN_VER 0 -+ -+/* ---- Private Constants and Types -------------------------------------- */ -+ -+/* Command blocks come from a pool */ -+#define SM_MAX_NUM_CMD_RSP_BLKS 32 -+ -+struct sm_cmd_rsp_blk { -+ struct list_head head; /* To create lists */ -+ struct semaphore sema; /* To be signaled when the response is there */ -+ -+ uint16_t id; -+ uint16_t length; -+ -+ uint8_t msg[VC_SM_MAX_MSG_LEN]; -+ -+ uint32_t wait:1; -+ uint32_t sent:1; -+ uint32_t alloc:1; -+ -+}; -+ -+struct sm_instance { -+ uint32_t num_connections; -+ VCHI_SERVICE_HANDLE_T vchi_handle[VCHI_MAX_NUM_CONNECTIONS]; -+ struct task_struct *io_thread; -+ struct semaphore io_sema; -+ -+ uint32_t trans_id; -+ -+ struct mutex lock; -+ struct list_head cmd_list; -+ struct list_head rsp_list; -+ struct list_head dead_list; -+ -+ struct sm_cmd_rsp_blk free_blk[SM_MAX_NUM_CMD_RSP_BLKS]; -+ struct list_head free_list; -+ struct mutex free_lock; -+ struct semaphore free_sema; -+ -+}; -+ -+/* ---- Private Variables ------------------------------------------------ */ -+ -+/* ---- Private Function Prototypes -------------------------------------- */ -+ -+/* ---- Private Functions ------------------------------------------------ */ -+static struct -+sm_cmd_rsp_blk *vc_vchi_cmd_create(struct sm_instance *instance, -+ VC_SM_MSG_TYPE id, void *msg, -+ uint32_t size, int wait) -+{ -+ struct sm_cmd_rsp_blk *blk; -+ VC_SM_MSG_HDR_T *hdr; -+ -+ if (down_interruptible(&instance->free_sema)) { -+ blk = kmalloc(sizeof(*blk), GFP_KERNEL); -+ if (!blk) -+ return NULL; -+ -+ blk->alloc = 1; -+ sema_init(&blk->sema, 0); -+ } else { -+ mutex_lock(&instance->free_lock); -+ blk = -+ list_first_entry(&instance->free_list, -+ struct sm_cmd_rsp_blk, head); -+ list_del(&blk->head); -+ mutex_unlock(&instance->free_lock); -+ } -+ -+ blk->sent = 0; -+ blk->wait = wait; -+ blk->length = sizeof(*hdr) + size; -+ -+ hdr = (VC_SM_MSG_HDR_T *) blk->msg; -+ hdr->type = id; -+ mutex_lock(&instance->lock); -+ hdr->trans_id = blk->id = ++instance->trans_id; -+ mutex_unlock(&instance->lock); -+ -+ if (size) -+ memcpy(hdr->body, msg, size); -+ -+ return blk; -+} -+ -+static void -+vc_vchi_cmd_delete(struct sm_instance *instance, struct sm_cmd_rsp_blk *blk) -+{ -+ if (blk->alloc) { -+ kfree(blk); -+ return; -+ } -+ -+ mutex_lock(&instance->free_lock); -+ list_add(&blk->head, &instance->free_list); -+ mutex_unlock(&instance->free_lock); -+ up(&instance->free_sema); -+} -+ -+static int vc_vchi_sm_videocore_io(void *arg) -+{ -+ struct sm_instance *instance = arg; -+ struct sm_cmd_rsp_blk *cmd = NULL, *cmd_tmp; -+ VC_SM_RESULT_T *reply; -+ uint32_t reply_len; -+ int32_t status; -+ int svc_use = 1; -+ -+ while (1) { -+ if (svc_use) -+ vchi_service_release(instance->vchi_handle[0]); -+ svc_use = 0; -+ if (!down_interruptible(&instance->io_sema)) { -+ vchi_service_use(instance->vchi_handle[0]); -+ svc_use = 1; -+ -+ do { -+ unsigned int flags; -+ /* -+ * Get new command and move it to response list -+ */ -+ mutex_lock(&instance->lock); -+ if (list_empty(&instance->cmd_list)) { -+ /* no more commands to process */ -+ mutex_unlock(&instance->lock); -+ break; -+ } -+ cmd = -+ list_first_entry(&instance->cmd_list, -+ struct sm_cmd_rsp_blk, -+ head); -+ list_move(&cmd->head, &instance->rsp_list); -+ cmd->sent = 1; -+ mutex_unlock(&instance->lock); -+ -+ /* Send the command */ -+ flags = VCHI_FLAGS_BLOCK_UNTIL_QUEUED; -+ status = vchi_msg_queue( -+ instance->vchi_handle[0], -+ cmd->msg, cmd->length, -+ flags, NULL); -+ if (status) { -+ pr_err("%s: failed to queue message (%d)", -+ __func__, status); -+ } -+ -+ /* If no reply is needed then we're done */ -+ if (!cmd->wait) { -+ mutex_lock(&instance->lock); -+ list_del(&cmd->head); -+ mutex_unlock(&instance->lock); -+ vc_vchi_cmd_delete(instance, cmd); -+ continue; -+ } -+ -+ if (status) { -+ up(&cmd->sema); -+ continue; -+ } -+ -+ } while (1); -+ -+ while (!vchi_msg_peek -+ (instance->vchi_handle[0], (void **)&reply, -+ &reply_len, VCHI_FLAGS_NONE)) { -+ mutex_lock(&instance->lock); -+ list_for_each_entry(cmd, &instance->rsp_list, -+ head) { -+ if (cmd->id == reply->trans_id) -+ break; -+ } -+ mutex_unlock(&instance->lock); -+ -+ if (&cmd->head == &instance->rsp_list) { -+ pr_debug("%s: received response %u, throw away...", -+ __func__, reply->trans_id); -+ } else if (reply_len > sizeof(cmd->msg)) { -+ pr_err("%s: reply too big (%u) %u, throw away...", -+ __func__, reply_len, -+ reply->trans_id); -+ } else { -+ memcpy(cmd->msg, reply, reply_len); -+ up(&cmd->sema); -+ } -+ -+ vchi_msg_remove(instance->vchi_handle[0]); -+ } -+ -+ /* Go through the dead list and free them */ -+ mutex_lock(&instance->lock); -+ list_for_each_entry_safe(cmd, cmd_tmp, -+ &instance->dead_list, head) { -+ list_del(&cmd->head); -+ vc_vchi_cmd_delete(instance, cmd); -+ } -+ mutex_unlock(&instance->lock); -+ } -+ } -+ -+ return 0; -+} -+ -+static void vc_sm_vchi_callback(void *param, -+ const VCHI_CALLBACK_REASON_T reason, -+ void *msg_handle) -+{ -+ struct sm_instance *instance = param; -+ -+ (void)msg_handle; -+ -+ switch (reason) { -+ case VCHI_CALLBACK_MSG_AVAILABLE: -+ up(&instance->io_sema); -+ break; -+ -+ case VCHI_CALLBACK_SERVICE_CLOSED: -+ pr_info("%s: service CLOSED!!", __func__); -+ default: -+ break; -+ } -+} -+ -+VC_VCHI_SM_HANDLE_T vc_vchi_sm_init(VCHI_INSTANCE_T vchi_instance, -+ VCHI_CONNECTION_T **vchi_connections, -+ uint32_t num_connections) -+{ -+ uint32_t i; -+ struct sm_instance *instance; -+ int status; -+ -+ pr_debug("%s: start", __func__); -+ -+ if (num_connections > VCHI_MAX_NUM_CONNECTIONS) { -+ pr_err("%s: unsupported number of connections %u (max=%u)", -+ __func__, num_connections, VCHI_MAX_NUM_CONNECTIONS); -+ -+ goto err_null; -+ } -+ /* Allocate memory for this instance */ -+ instance = kzalloc(sizeof(*instance), GFP_KERNEL); -+ -+ /* Misc initialisations */ -+ mutex_init(&instance->lock); -+ sema_init(&instance->io_sema, 0); -+ INIT_LIST_HEAD(&instance->cmd_list); -+ INIT_LIST_HEAD(&instance->rsp_list); -+ INIT_LIST_HEAD(&instance->dead_list); -+ INIT_LIST_HEAD(&instance->free_list); -+ sema_init(&instance->free_sema, SM_MAX_NUM_CMD_RSP_BLKS); -+ mutex_init(&instance->free_lock); -+ for (i = 0; i < SM_MAX_NUM_CMD_RSP_BLKS; i++) { -+ sema_init(&instance->free_blk[i].sema, 0); -+ list_add(&instance->free_blk[i].head, &instance->free_list); -+ } -+ -+ /* Open the VCHI service connections */ -+ instance->num_connections = num_connections; -+ for (i = 0; i < num_connections; i++) { -+ SERVICE_CREATION_T params = { -+ VCHI_VERSION_EX(VC_SM_VER, VC_SM_MIN_VER), -+ VC_SM_SERVER_NAME, -+ vchi_connections[i], -+ 0, -+ 0, -+ vc_sm_vchi_callback, -+ instance, -+ 0, -+ 0, -+ 0, -+ }; -+ -+ status = vchi_service_open(vchi_instance, -+ ¶ms, &instance->vchi_handle[i]); -+ if (status) { -+ pr_err("%s: failed to open VCHI service (%d)", -+ __func__, status); -+ -+ goto err_close_services; -+ } -+ } -+ -+ /* Create the thread which takes care of all io to/from videoocore. */ -+ instance->io_thread = kthread_create(&vc_vchi_sm_videocore_io, -+ (void *)instance, "SMIO"); -+ if (instance->io_thread == NULL) { -+ pr_err("%s: failed to create SMIO thread", __func__); -+ -+ goto err_close_services; -+ } -+ set_user_nice(instance->io_thread, -10); -+ wake_up_process(instance->io_thread); -+ -+ pr_debug("%s: success - instance 0x%x", __func__, (unsigned)instance); -+ return instance; -+ -+err_close_services: -+ for (i = 0; i < instance->num_connections; i++) { -+ if (instance->vchi_handle[i] != NULL) -+ vchi_service_close(instance->vchi_handle[i]); -+ } -+ kfree(instance); -+err_null: -+ pr_debug("%s: FAILED", __func__); -+ return NULL; -+} -+ -+int vc_vchi_sm_stop(VC_VCHI_SM_HANDLE_T *handle) -+{ -+ struct sm_instance *instance; -+ uint32_t i; -+ -+ if (handle == NULL) { -+ pr_err("%s: invalid pointer to handle %p", __func__, handle); -+ goto lock; -+ } -+ -+ if (*handle == NULL) { -+ pr_err("%s: invalid handle %p", __func__, *handle); -+ goto lock; -+ } -+ -+ instance = *handle; -+ -+ /* Close all VCHI service connections */ -+ for (i = 0; i < instance->num_connections; i++) { -+ int32_t success; -+ vchi_service_use(instance->vchi_handle[i]); -+ -+ success = vchi_service_close(instance->vchi_handle[i]); -+ } -+ -+ kfree(instance); -+ -+ *handle = NULL; -+ return 0; -+ -+lock: -+ return -EINVAL; -+} -+ -+int vc_vchi_sm_send_msg(VC_VCHI_SM_HANDLE_T handle, -+ VC_SM_MSG_TYPE msg_id, -+ void *msg, uint32_t msg_size, -+ void *result, uint32_t result_size, -+ uint32_t *cur_trans_id, uint8_t wait_reply) -+{ -+ int status = 0; -+ struct sm_instance *instance = handle; -+ struct sm_cmd_rsp_blk *cmd_blk; -+ -+ if (handle == NULL) { -+ pr_err("%s: invalid handle", __func__); -+ return -EINVAL; -+ } -+ if (msg == NULL) { -+ pr_err("%s: invalid msg pointer", __func__); -+ return -EINVAL; -+ } -+ -+ cmd_blk = -+ vc_vchi_cmd_create(instance, msg_id, msg, msg_size, wait_reply); -+ if (cmd_blk == NULL) { -+ pr_err("[%s]: failed to allocate global tracking resource", -+ __func__); -+ return -ENOMEM; -+ } -+ -+ if (cur_trans_id != NULL) -+ *cur_trans_id = cmd_blk->id; -+ -+ mutex_lock(&instance->lock); -+ list_add_tail(&cmd_blk->head, &instance->cmd_list); -+ mutex_unlock(&instance->lock); -+ up(&instance->io_sema); -+ -+ if (!wait_reply) -+ /* We're done */ -+ return 0; -+ -+ /* Wait for the response */ -+ if (down_interruptible(&cmd_blk->sema)) { -+ mutex_lock(&instance->lock); -+ if (!cmd_blk->sent) { -+ list_del(&cmd_blk->head); -+ mutex_unlock(&instance->lock); -+ vc_vchi_cmd_delete(instance, cmd_blk); -+ return -ENXIO; -+ } -+ mutex_unlock(&instance->lock); -+ -+ mutex_lock(&instance->lock); -+ list_move(&cmd_blk->head, &instance->dead_list); -+ mutex_unlock(&instance->lock); -+ up(&instance->io_sema); -+ return -EINTR; /* We're done */ -+ } -+ -+ if (result && result_size) { -+ memcpy(result, cmd_blk->msg, result_size); -+ } else { -+ VC_SM_RESULT_T *res = (VC_SM_RESULT_T *) cmd_blk->msg; -+ status = (res->success == 0) ? 0 : -ENXIO; -+ } -+ -+ mutex_lock(&instance->lock); -+ list_del(&cmd_blk->head); -+ mutex_unlock(&instance->lock); -+ vc_vchi_cmd_delete(instance, cmd_blk); -+ return status; -+} -+ -+int vc_vchi_sm_alloc(VC_VCHI_SM_HANDLE_T handle, VC_SM_ALLOC_T *msg, -+ VC_SM_ALLOC_RESULT_T *result, uint32_t *cur_trans_id) -+{ -+ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_ALLOC, -+ msg, sizeof(*msg), result, sizeof(*result), -+ cur_trans_id, 1); -+} -+ -+int vc_vchi_sm_free(VC_VCHI_SM_HANDLE_T handle, -+ VC_SM_FREE_T *msg, uint32_t *cur_trans_id) -+{ -+ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_FREE, -+ msg, sizeof(*msg), 0, 0, cur_trans_id, 0); -+} -+ -+int vc_vchi_sm_lock(VC_VCHI_SM_HANDLE_T handle, -+ VC_SM_LOCK_UNLOCK_T *msg, -+ VC_SM_LOCK_RESULT_T *result, uint32_t *cur_trans_id) -+{ -+ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_LOCK, -+ msg, sizeof(*msg), result, sizeof(*result), -+ cur_trans_id, 1); -+} -+ -+int vc_vchi_sm_unlock(VC_VCHI_SM_HANDLE_T handle, -+ VC_SM_LOCK_UNLOCK_T *msg, -+ uint32_t *cur_trans_id, uint8_t wait_reply) -+{ -+ return vc_vchi_sm_send_msg(handle, wait_reply ? -+ VC_SM_MSG_TYPE_UNLOCK : -+ VC_SM_MSG_TYPE_UNLOCK_NOANS, msg, -+ sizeof(*msg), 0, 0, cur_trans_id, -+ wait_reply); -+} -+ -+int vc_vchi_sm_resize(VC_VCHI_SM_HANDLE_T handle, VC_SM_RESIZE_T *msg, -+ uint32_t *cur_trans_id) -+{ -+ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_RESIZE, -+ msg, sizeof(*msg), 0, 0, cur_trans_id, 1); -+} -+ -+int vc_vchi_sm_walk_alloc(VC_VCHI_SM_HANDLE_T handle) -+{ -+ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_WALK_ALLOC, -+ 0, 0, 0, 0, 0, 0); -+} -+ -+int vc_vchi_sm_clean_up(VC_VCHI_SM_HANDLE_T handle, VC_SM_ACTION_CLEAN_T *msg) -+{ -+ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_ACTION_CLEAN, -+ msg, sizeof(*msg), 0, 0, 0, 0); -+} -diff -Nur linux-4.1.13.orig/drivers/char/broadcom/vc_sm/vmcs_sm.c linux-rpi/drivers/char/broadcom/vc_sm/vmcs_sm.c ---- linux-4.1.13.orig/drivers/char/broadcom/vc_sm/vmcs_sm.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/char/broadcom/vc_sm/vmcs_sm.c 2015-11-29 09:42:36.707312101 +0100 -@@ -0,0 +1,3211 @@ -+/***************************************************************************** -+* Copyright 2011-2012 Broadcom Corporation. All rights reserved. -+* -+* Unless you and Broadcom execute a separate written software license -+* agreement governing use of this software, this software is licensed to you -+* under the terms of the GNU General Public License version 2, available at -+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -+* -+* Notwithstanding the above, under no circumstances may you combine this -+* software in any way with any other Broadcom software provided under a -+* license other than the GPL, without Broadcom's express prior written -+* consent. -+*****************************************************************************/ -+ -+/* ---- Include Files ----------------------------------------------------- */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "vchiq_connected.h" -+#include "vc_vchi_sm.h" -+ -+#include -+#include "vc_sm_knl.h" -+ -+/* ---- Private Constants and Types --------------------------------------- */ -+ -+#define DEVICE_NAME "vcsm" -+#define DEVICE_MINOR 0 -+ -+#define VC_SM_DIR_ROOT_NAME "vc-smem" -+#define VC_SM_DIR_ALLOC_NAME "alloc" -+#define VC_SM_STATE "state" -+#define VC_SM_STATS "statistics" -+#define VC_SM_RESOURCES "resources" -+#define VC_SM_DEBUG "debug" -+#define VC_SM_WRITE_BUF_SIZE 128 -+ -+/* Statistics tracked per resource and globally. -+*/ -+enum SM_STATS_T { -+ /* Attempt. */ -+ ALLOC, -+ FREE, -+ LOCK, -+ UNLOCK, -+ MAP, -+ FLUSH, -+ INVALID, -+ -+ END_ATTEMPT, -+ -+ /* Failure. */ -+ ALLOC_FAIL, -+ FREE_FAIL, -+ LOCK_FAIL, -+ UNLOCK_FAIL, -+ MAP_FAIL, -+ FLUSH_FAIL, -+ INVALID_FAIL, -+ -+ END_ALL, -+ -+}; -+ -+static const char *const sm_stats_human_read[] = { -+ "Alloc", -+ "Free", -+ "Lock", -+ "Unlock", -+ "Map", -+ "Cache Flush", -+ "Cache Invalidate", -+}; -+ -+typedef int (*VC_SM_SHOW) (struct seq_file *s, void *v); -+struct SM_PDE_T { -+ VC_SM_SHOW show; /* Debug fs function hookup. */ -+ struct dentry *dir_entry; /* Debug fs directory entry. */ -+ void *priv_data; /* Private data */ -+ -+}; -+ -+/* Single resource allocation tracked for all devices. -+*/ -+struct sm_mmap { -+ struct list_head map_list; /* Linked list of maps. */ -+ -+ struct SM_RESOURCE_T *resource; /* Pointer to the resource. */ -+ -+ pid_t res_pid; /* PID owning that resource. */ -+ unsigned int res_vc_hdl; /* Resource handle (videocore). */ -+ unsigned int res_usr_hdl; /* Resource handle (user). */ -+ -+ long unsigned int res_addr; /* Mapped virtual address. */ -+ struct vm_area_struct *vma; /* VM area for this mapping. */ -+ unsigned int ref_count; /* Reference count to this vma. */ -+ -+ /* Used to link maps associated with a resource. */ -+ struct list_head resource_map_list; -+}; -+ -+/* Single resource allocation tracked for each opened device. -+*/ -+struct SM_RESOURCE_T { -+ struct list_head resource_list; /* List of resources. */ -+ struct list_head global_resource_list; /* Global list of resources. */ -+ -+ pid_t pid; /* PID owning that resource. */ -+ uint32_t res_guid; /* Unique identifier. */ -+ uint32_t lock_count; /* Lock count for this resource. */ -+ uint32_t ref_count; /* Ref count for this resource. */ -+ -+ uint32_t res_handle; /* Resource allocation handle. */ -+ void *res_base_mem; /* Resource base memory address. */ -+ uint32_t res_size; /* Resource size allocated. */ -+ enum vmcs_sm_cache_e res_cached; /* Resource cache type. */ -+ struct SM_RESOURCE_T *res_shared; /* Shared resource */ -+ -+ enum SM_STATS_T res_stats[END_ALL]; /* Resource statistics. */ -+ -+ uint8_t map_count; /* Counter of mappings for this resource. */ -+ struct list_head map_list; /* Maps associated with a resource. */ -+ -+ struct SM_PRIV_DATA_T *private; -+}; -+ -+/* Private file data associated with each opened device. -+*/ -+struct SM_PRIV_DATA_T { -+ struct list_head resource_list; /* List of resources. */ -+ -+ pid_t pid; /* PID of creator. */ -+ -+ struct dentry *dir_pid; /* Debug fs entries root. */ -+ struct SM_PDE_T dir_stats; /* Debug fs entries statistics sub-tree. */ -+ struct SM_PDE_T dir_res; /* Debug fs resource sub-tree. */ -+ -+ int restart_sys; /* Tracks restart on interrupt. */ -+ VC_SM_MSG_TYPE int_action; /* Interrupted action. */ -+ uint32_t int_trans_id; /* Interrupted transaction. */ -+ -+}; -+ -+/* Global state information. -+*/ -+struct SM_STATE_T { -+ VC_VCHI_SM_HANDLE_T sm_handle; /* Handle for videocore service. */ -+ struct dentry *dir_root; /* Debug fs entries root. */ -+ struct dentry *dir_alloc; /* Debug fs entries allocations. */ -+ struct SM_PDE_T dir_stats; /* Debug fs entries statistics sub-tree. */ -+ struct SM_PDE_T dir_state; /* Debug fs entries state sub-tree. */ -+ struct dentry *debug; /* Debug fs entries debug. */ -+ -+ struct mutex map_lock; /* Global map lock. */ -+ struct list_head map_list; /* List of maps. */ -+ struct list_head resource_list; /* List of resources. */ -+ -+ enum SM_STATS_T deceased[END_ALL]; /* Natural termination stats. */ -+ enum SM_STATS_T terminated[END_ALL]; /* Forced termination stats. */ -+ uint32_t res_deceased_cnt; /* Natural termination counter. */ -+ uint32_t res_terminated_cnt; /* Forced termination counter. */ -+ -+ struct cdev sm_cdev; /* Device. */ -+ dev_t sm_devid; /* Device identifier. */ -+ struct class *sm_class; /* Class. */ -+ struct device *sm_dev; /* Device. */ -+ -+ struct SM_PRIV_DATA_T *data_knl; /* Kernel internal data tracking. */ -+ -+ struct mutex lock; /* Global lock. */ -+ uint32_t guid; /* GUID (next) tracker. */ -+ -+}; -+ -+/* ---- Private Variables ----------------------------------------------- */ -+ -+static struct SM_STATE_T *sm_state; -+static int sm_inited; -+ -+static const char *const sm_cache_map_vector[] = { -+ "(null)", -+ "host", -+ "videocore", -+ "host+videocore", -+}; -+ -+/* ---- Private Function Prototypes -------------------------------------- */ -+ -+/* ---- Private Functions ------------------------------------------------ */ -+ -+static inline unsigned vcaddr_to_pfn(unsigned long vc_addr) -+{ -+ unsigned long pfn = vc_addr & 0x3FFFFFFF; -+ pfn += mm_vc_mem_phys_addr; -+ pfn >>= PAGE_SHIFT; -+ return pfn; -+} -+ -+/* Carries over to the state statistics the statistics once owned by a deceased -+** resource. -+*/ -+static void vc_sm_resource_deceased(struct SM_RESOURCE_T *p_res, int terminated) -+{ -+ if (sm_state != NULL) { -+ if (p_res != NULL) { -+ int ix; -+ -+ if (terminated) -+ sm_state->res_terminated_cnt++; -+ else -+ sm_state->res_deceased_cnt++; -+ -+ for (ix = 0; ix < END_ALL; ix++) { -+ if (terminated) -+ sm_state->terminated[ix] += -+ p_res->res_stats[ix]; -+ else -+ sm_state->deceased[ix] += -+ p_res->res_stats[ix]; -+ } -+ } -+ } -+} -+ -+/* Fetch a videocore handle corresponding to a mapping of the pid+address -+** returns 0 (ie NULL) if no such handle exists in the global map. -+*/ -+static unsigned int vmcs_sm_vc_handle_from_pid_and_address(unsigned int pid, -+ unsigned int addr) -+{ -+ struct sm_mmap *map = NULL; -+ unsigned int handle = 0; -+ -+ if (!sm_state || addr == 0) -+ goto out; -+ -+ mutex_lock(&(sm_state->map_lock)); -+ -+ /* Lookup the resource. -+ */ -+ if (!list_empty(&sm_state->map_list)) { -+ list_for_each_entry(map, &sm_state->map_list, map_list) { -+ if (map->res_pid != pid || map->res_addr != addr) -+ continue; -+ -+ pr_debug("[%s]: global map %p (pid %u, addr %lx) -> vc-hdl %x (usr-hdl %x)\n", -+ __func__, map, map->res_pid, map->res_addr, -+ map->res_vc_hdl, map->res_usr_hdl); -+ -+ handle = map->res_vc_hdl; -+ break; -+ } -+ } -+ -+ mutex_unlock(&(sm_state->map_lock)); -+ -+out: -+ /* Use a debug log here as it may be a valid situation that we query -+ ** for something that is not mapped, we do not want a kernel log each -+ ** time around. -+ ** -+ ** There are other error log that would pop up accordingly if someone -+ ** subsequently tries to use something invalid after being told not to -+ ** use it... -+ */ -+ if (handle == 0) { -+ pr_debug("[%s]: not a valid map (pid %u, addr %x)\n", -+ __func__, pid, addr); -+ } -+ -+ return handle; -+} -+ -+/* Fetch a user handle corresponding to a mapping of the pid+address -+** returns 0 (ie NULL) if no such handle exists in the global map. -+*/ -+static unsigned int vmcs_sm_usr_handle_from_pid_and_address(unsigned int pid, -+ unsigned int addr) -+{ -+ struct sm_mmap *map = NULL; -+ unsigned int handle = 0; -+ -+ if (!sm_state || addr == 0) -+ goto out; -+ -+ mutex_lock(&(sm_state->map_lock)); -+ -+ /* Lookup the resource. -+ */ -+ if (!list_empty(&sm_state->map_list)) { -+ list_for_each_entry(map, &sm_state->map_list, map_list) { -+ if (map->res_pid != pid || map->res_addr != addr) -+ continue; -+ -+ pr_debug("[%s]: global map %p (pid %u, addr %lx) -> usr-hdl %x (vc-hdl %x)\n", -+ __func__, map, map->res_pid, map->res_addr, -+ map->res_usr_hdl, map->res_vc_hdl); -+ -+ handle = map->res_usr_hdl; -+ break; -+ } -+ } -+ -+ mutex_unlock(&(sm_state->map_lock)); -+ -+out: -+ /* Use a debug log here as it may be a valid situation that we query -+ * for something that is not mapped yet. -+ * -+ * There are other error log that would pop up accordingly if someone -+ * subsequently tries to use something invalid after being told not to -+ * use it... -+ */ -+ if (handle == 0) -+ pr_debug("[%s]: not a valid map (pid %u, addr %x)\n", -+ __func__, pid, addr); -+ -+ return handle; -+} -+ -+#if defined(DO_NOT_USE) -+/* Fetch an address corresponding to a mapping of the pid+handle -+** returns 0 (ie NULL) if no such address exists in the global map. -+*/ -+static unsigned int vmcs_sm_usr_address_from_pid_and_vc_handle(unsigned int pid, -+ unsigned int hdl) -+{ -+ struct sm_mmap *map = NULL; -+ unsigned int addr = 0; -+ -+ if (sm_state == NULL || hdl == 0) -+ goto out; -+ -+ mutex_lock(&(sm_state->map_lock)); -+ -+ /* Lookup the resource. -+ */ -+ if (!list_empty(&sm_state->map_list)) { -+ list_for_each_entry(map, &sm_state->map_list, map_list) { -+ if (map->res_pid != pid || map->res_vc_hdl != hdl) -+ continue; -+ -+ pr_debug("[%s]: global map %p (pid %u, vc-hdl %x, usr-hdl %x) -> addr %lx\n", -+ __func__, map, map->res_pid, map->res_vc_hdl, -+ map->res_usr_hdl, map->res_addr); -+ -+ addr = map->res_addr; -+ break; -+ } -+ } -+ -+ mutex_unlock(&(sm_state->map_lock)); -+ -+out: -+ /* Use a debug log here as it may be a valid situation that we query -+ ** for something that is not mapped, we do not want a kernel log each -+ ** time around. -+ ** -+ ** There are other error log that would pop up accordingly if someone -+ ** subsequently tries to use something invalid after being told not to -+ ** use it... -+ */ -+ if (addr == 0) -+ pr_debug("[%s]: not a valid map (pid %u, hdl %x)\n", -+ __func__, pid, hdl); -+ -+ return addr; -+} -+#endif -+ -+/* Fetch an address corresponding to a mapping of the pid+handle -+** returns 0 (ie NULL) if no such address exists in the global map. -+*/ -+static unsigned int vmcs_sm_usr_address_from_pid_and_usr_handle(unsigned int -+ pid, -+ unsigned int -+ hdl) -+{ -+ struct sm_mmap *map = NULL; -+ unsigned int addr = 0; -+ -+ if (sm_state == NULL || hdl == 0) -+ goto out; -+ -+ mutex_lock(&(sm_state->map_lock)); -+ -+ /* Lookup the resource. -+ */ -+ if (!list_empty(&sm_state->map_list)) { -+ list_for_each_entry(map, &sm_state->map_list, map_list) { -+ if (map->res_pid != pid || map->res_usr_hdl != hdl) -+ continue; -+ -+ pr_debug("[%s]: global map %p (pid %u, vc-hdl %x, usr-hdl %x) -> addr %lx\n", -+ __func__, map, map->res_pid, map->res_vc_hdl, -+ map->res_usr_hdl, map->res_addr); -+ -+ addr = map->res_addr; -+ break; -+ } -+ } -+ -+ mutex_unlock(&(sm_state->map_lock)); -+ -+out: -+ /* Use a debug log here as it may be a valid situation that we query -+ * for something that is not mapped, we do not want a kernel log each -+ * time around. -+ * -+ * There are other error log that would pop up accordingly if someone -+ * subsequently tries to use something invalid after being told not to -+ * use it... -+ */ -+ if (addr == 0) -+ pr_debug("[%s]: not a valid map (pid %u, hdl %x)\n", __func__, -+ pid, hdl); -+ -+ return addr; -+} -+ -+/* Adds a resource mapping to the global data list. -+*/ -+static void vmcs_sm_add_map(struct SM_STATE_T *state, -+ struct SM_RESOURCE_T *resource, struct sm_mmap *map) -+{ -+ mutex_lock(&(state->map_lock)); -+ -+ /* Add to the global list of mappings -+ */ -+ list_add(&map->map_list, &state->map_list); -+ -+ /* Add to the list of mappings for this resource -+ */ -+ list_add(&map->resource_map_list, &resource->map_list); -+ resource->map_count++; -+ -+ mutex_unlock(&(state->map_lock)); -+ -+ pr_debug("[%s]: added map %p (pid %u, vc-hdl %x, usr-hdl %x, addr %lx)\n", -+ __func__, map, map->res_pid, map->res_vc_hdl, -+ map->res_usr_hdl, map->res_addr); -+} -+ -+/* Removes a resource mapping from the global data list. -+*/ -+static void vmcs_sm_remove_map(struct SM_STATE_T *state, -+ struct SM_RESOURCE_T *resource, -+ struct sm_mmap *map) -+{ -+ mutex_lock(&(state->map_lock)); -+ -+ /* Remove from the global list of mappings -+ */ -+ list_del(&map->map_list); -+ -+ /* Remove from the list of mapping for this resource -+ */ -+ list_del(&map->resource_map_list); -+ if (resource->map_count > 0) -+ resource->map_count--; -+ -+ mutex_unlock(&(state->map_lock)); -+ -+ pr_debug("[%s]: removed map %p (pid %d, vc-hdl %x, usr-hdl %x, addr %lx)\n", -+ __func__, map, map->res_pid, map->res_vc_hdl, map->res_usr_hdl, -+ map->res_addr); -+ -+ kfree(map); -+} -+ -+/* Read callback for the global state proc entry. -+*/ -+static int vc_sm_global_state_show(struct seq_file *s, void *v) -+{ -+ struct sm_mmap *map = NULL; -+ int map_count = 0; -+ -+ if (sm_state == NULL) -+ return 0; -+ -+ seq_printf(s, "\nVC-ServiceHandle 0x%x\n", -+ (unsigned int)sm_state->sm_handle); -+ -+ /* Log all applicable mapping(s). -+ */ -+ -+ mutex_lock(&(sm_state->map_lock)); -+ -+ if (!list_empty(&sm_state->map_list)) { -+ list_for_each_entry(map, &sm_state->map_list, map_list) { -+ map_count++; -+ -+ seq_printf(s, "\nMapping 0x%x\n", -+ (unsigned int)map); -+ seq_printf(s, " TGID %u\n", -+ map->res_pid); -+ seq_printf(s, " VC-HDL 0x%x\n", -+ map->res_vc_hdl); -+ seq_printf(s, " USR-HDL 0x%x\n", -+ map->res_usr_hdl); -+ seq_printf(s, " USR-ADDR 0x%lx\n", -+ map->res_addr); -+ } -+ } -+ -+ mutex_unlock(&(sm_state->map_lock)); -+ seq_printf(s, "\n\nTotal map count: %d\n\n", map_count); -+ -+ return 0; -+} -+ -+static int vc_sm_global_statistics_show(struct seq_file *s, void *v) -+{ -+ int ix; -+ -+ /* Global state tracked statistics. -+ */ -+ if (sm_state != NULL) { -+ seq_puts(s, "\nDeceased Resources Statistics\n"); -+ -+ seq_printf(s, "\nNatural Cause (%u occurences)\n", -+ sm_state->res_deceased_cnt); -+ for (ix = 0; ix < END_ATTEMPT; ix++) { -+ if (sm_state->deceased[ix] > 0) { -+ seq_printf(s, " %u\t%s\n", -+ sm_state->deceased[ix], -+ sm_stats_human_read[ix]); -+ } -+ } -+ seq_puts(s, "\n"); -+ for (ix = 0; ix < END_ATTEMPT; ix++) { -+ if (sm_state->deceased[ix + END_ATTEMPT] > 0) { -+ seq_printf(s, " %u\tFAILED %s\n", -+ sm_state->deceased[ix + END_ATTEMPT], -+ sm_stats_human_read[ix]); -+ } -+ } -+ -+ seq_printf(s, "\nForcefull (%u occurences)\n", -+ sm_state->res_terminated_cnt); -+ for (ix = 0; ix < END_ATTEMPT; ix++) { -+ if (sm_state->terminated[ix] > 0) { -+ seq_printf(s, " %u\t%s\n", -+ sm_state->terminated[ix], -+ sm_stats_human_read[ix]); -+ } -+ } -+ seq_puts(s, "\n"); -+ for (ix = 0; ix < END_ATTEMPT; ix++) { -+ if (sm_state->terminated[ix + END_ATTEMPT] > 0) { -+ seq_printf(s, " %u\tFAILED %s\n", -+ sm_state->terminated[ix + -+ END_ATTEMPT], -+ sm_stats_human_read[ix]); -+ } -+ } -+ } -+ -+ return 0; -+} -+ -+#if 0 -+/* Read callback for the statistics proc entry. -+*/ -+static int vc_sm_statistics_show(struct seq_file *s, void *v) -+{ -+ int ix; -+ struct SM_PRIV_DATA_T *file_data; -+ struct SM_RESOURCE_T *resource; -+ int res_count = 0; -+ struct SM_PDE_T *p_pde; -+ -+ p_pde = (struct SM_PDE_T *)(s->private); -+ file_data = (struct SM_PRIV_DATA_T *)(p_pde->priv_data); -+ -+ if (file_data == NULL) -+ return 0; -+ -+ /* Per process statistics. -+ */ -+ -+ seq_printf(s, "\nStatistics for TGID %d\n", file_data->pid); -+ -+ mutex_lock(&(sm_state->map_lock)); -+ -+ if (!list_empty(&file_data->resource_list)) { -+ list_for_each_entry(resource, &file_data->resource_list, -+ resource_list) { -+ res_count++; -+ -+ seq_printf(s, "\nGUID: 0x%x\n\n", -+ resource->res_guid); -+ for (ix = 0; ix < END_ATTEMPT; ix++) { -+ if (resource->res_stats[ix] > 0) { -+ seq_printf(s, -+ " %u\t%s\n", -+ resource->res_stats[ix], -+ sm_stats_human_read[ix]); -+ } -+ } -+ seq_puts(s, "\n"); -+ for (ix = 0; ix < END_ATTEMPT; ix++) { -+ if (resource->res_stats[ix + END_ATTEMPT] > 0) { -+ seq_printf(s, -+ " %u\tFAILED %s\n", -+ resource->res_stats[ -+ ix + END_ATTEMPT], -+ sm_stats_human_read[ix]); -+ } -+ } -+ } -+ } -+ -+ mutex_unlock(&(sm_state->map_lock)); -+ -+ seq_printf(s, "\nResources Count %d\n", res_count); -+ -+ return 0; -+} -+#endif -+ -+#if 0 -+/* Read callback for the allocation proc entry. */ -+static int vc_sm_alloc_show(struct seq_file *s, void *v) -+{ -+ struct SM_PRIV_DATA_T *file_data; -+ struct SM_RESOURCE_T *resource; -+ int alloc_count = 0; -+ struct SM_PDE_T *p_pde; -+ -+ p_pde = (struct SM_PDE_T *)(s->private); -+ file_data = (struct SM_PRIV_DATA_T *)(p_pde->priv_data); -+ -+ if (!file_data) -+ return 0; -+ -+ /* Per process statistics. */ -+ seq_printf(s, "\nAllocation for TGID %d\n", file_data->pid); -+ -+ mutex_lock(&(sm_state->map_lock)); -+ -+ if (!list_empty(&file_data->resource_list)) { -+ list_for_each_entry(resource, &file_data->resource_list, -+ resource_list) { -+ alloc_count++; -+ -+ seq_printf(s, "\nGUID: 0x%x\n", -+ resource->res_guid); -+ seq_printf(s, "Lock Count: %u\n", -+ resource->lock_count); -+ seq_printf(s, "Mapped: %s\n", -+ (resource->map_count ? "yes" : "no")); -+ seq_printf(s, "VC-handle: 0x%x\n", -+ resource->res_handle); -+ seq_printf(s, "VC-address: 0x%p\n", -+ resource->res_base_mem); -+ seq_printf(s, "VC-size (bytes): %u\n", -+ resource->res_size); -+ seq_printf(s, "Cache: %s\n", -+ sm_cache_map_vector[resource->res_cached]); -+ } -+ } -+ -+ mutex_unlock(&(sm_state->map_lock)); -+ -+ seq_printf(s, "\n\nTotal allocation count: %d\n\n", alloc_count); -+ -+ return 0; -+} -+#endif -+ -+static int vc_sm_seq_file_show(struct seq_file *s, void *v) -+{ -+ struct SM_PDE_T *sm_pde; -+ -+ sm_pde = (struct SM_PDE_T *)(s->private); -+ -+ if (sm_pde && sm_pde->show) -+ sm_pde->show(s, v); -+ -+ return 0; -+} -+ -+static int vc_sm_single_open(struct inode *inode, struct file *file) -+{ -+ return single_open(file, vc_sm_seq_file_show, inode->i_private); -+} -+ -+static const struct file_operations vc_sm_debug_fs_fops = { -+ .open = vc_sm_single_open, -+ .read = seq_read, -+ .llseek = seq_lseek, -+ .release = single_release, -+}; -+ -+/* Adds a resource to the private data list which tracks all the allocated -+** data. -+*/ -+static void vmcs_sm_add_resource(struct SM_PRIV_DATA_T *privdata, -+ struct SM_RESOURCE_T *resource) -+{ -+ mutex_lock(&(sm_state->map_lock)); -+ list_add(&resource->resource_list, &privdata->resource_list); -+ list_add(&resource->global_resource_list, &sm_state->resource_list); -+ mutex_unlock(&(sm_state->map_lock)); -+ -+ pr_debug("[%s]: added resource %p (base addr %p, hdl %x, size %u, cache %u)\n", -+ __func__, resource, resource->res_base_mem, -+ resource->res_handle, resource->res_size, resource->res_cached); -+} -+ -+/* Locates a resource and acquire a reference on it. -+** The resource won't be deleted while there is a reference on it. -+*/ -+static struct SM_RESOURCE_T *vmcs_sm_acquire_resource(struct SM_PRIV_DATA_T -+ *private, -+ unsigned int res_guid) -+{ -+ struct SM_RESOURCE_T *resource, *ret = NULL; -+ -+ mutex_lock(&(sm_state->map_lock)); -+ -+ list_for_each_entry(resource, &private->resource_list, resource_list) { -+ if (resource->res_guid != res_guid) -+ continue; -+ -+ pr_debug("[%s]: located resource %p (guid: %x, base addr %p, hdl %x, size %u, cache %u)\n", -+ __func__, resource, resource->res_guid, -+ resource->res_base_mem, resource->res_handle, -+ resource->res_size, resource->res_cached); -+ resource->ref_count++; -+ ret = resource; -+ break; -+ } -+ -+ mutex_unlock(&(sm_state->map_lock)); -+ -+ return ret; -+} -+ -+/* Locates a resource and acquire a reference on it. -+** The resource won't be deleted while there is a reference on it. -+*/ -+static struct SM_RESOURCE_T *vmcs_sm_acquire_first_resource( -+ struct SM_PRIV_DATA_T *private) -+{ -+ struct SM_RESOURCE_T *resource, *ret = NULL; -+ -+ mutex_lock(&(sm_state->map_lock)); -+ -+ list_for_each_entry(resource, &private->resource_list, resource_list) { -+ pr_debug("[%s]: located resource %p (guid: %x, base addr %p, hdl %x, size %u, cache %u)\n", -+ __func__, resource, resource->res_guid, -+ resource->res_base_mem, resource->res_handle, -+ resource->res_size, resource->res_cached); -+ resource->ref_count++; -+ ret = resource; -+ break; -+ } -+ -+ mutex_unlock(&(sm_state->map_lock)); -+ -+ return ret; -+} -+ -+/* Locates a resource and acquire a reference on it. -+** The resource won't be deleted while there is a reference on it. -+*/ -+static struct SM_RESOURCE_T *vmcs_sm_acquire_global_resource(unsigned int -+ res_guid) -+{ -+ struct SM_RESOURCE_T *resource, *ret = NULL; -+ -+ mutex_lock(&(sm_state->map_lock)); -+ -+ list_for_each_entry(resource, &sm_state->resource_list, -+ global_resource_list) { -+ if (resource->res_guid != res_guid) -+ continue; -+ -+ pr_debug("[%s]: located resource %p (guid: %x, base addr %p, hdl %x, size %u, cache %u)\n", -+ __func__, resource, resource->res_guid, -+ resource->res_base_mem, resource->res_handle, -+ resource->res_size, resource->res_cached); -+ resource->ref_count++; -+ ret = resource; -+ break; -+ } -+ -+ mutex_unlock(&(sm_state->map_lock)); -+ -+ return ret; -+} -+ -+/* Release a previously acquired resource. -+** The resource will be deleted when its refcount reaches 0. -+*/ -+static void vmcs_sm_release_resource(struct SM_RESOURCE_T *resource, int force) -+{ -+ struct SM_PRIV_DATA_T *private = resource->private; -+ struct sm_mmap *map, *map_tmp; -+ struct SM_RESOURCE_T *res_tmp; -+ int ret; -+ -+ mutex_lock(&(sm_state->map_lock)); -+ -+ if (--resource->ref_count) { -+ if (force) -+ pr_err("[%s]: resource %p in use\n", __func__, resource); -+ -+ mutex_unlock(&(sm_state->map_lock)); -+ return; -+ } -+ -+ /* Time to free the resource. Start by removing it from the list */ -+ list_del(&resource->resource_list); -+ list_del(&resource->global_resource_list); -+ -+ /* Walk the global resource list, find out if the resource is used -+ * somewhere else. In which case we don't want to delete it. -+ */ -+ list_for_each_entry(res_tmp, &sm_state->resource_list, -+ global_resource_list) { -+ if (res_tmp->res_handle == resource->res_handle) { -+ resource->res_handle = 0; -+ break; -+ } -+ } -+ -+ mutex_unlock(&(sm_state->map_lock)); -+ -+ pr_debug("[%s]: freeing data - guid %x, hdl %x, base address %p\n", -+ __func__, resource->res_guid, resource->res_handle, -+ resource->res_base_mem); -+ resource->res_stats[FREE]++; -+ -+ /* Make sure the resource we're removing is unmapped first */ -+ if (resource->map_count && !list_empty(&resource->map_list)) { -+ down_write(¤t->mm->mmap_sem); -+ list_for_each_entry_safe(map, map_tmp, &resource->map_list, -+ resource_map_list) { -+ ret = -+ do_munmap(current->mm, map->res_addr, -+ resource->res_size); -+ if (ret) { -+ pr_err("[%s]: could not unmap resource %p\n", -+ __func__, resource); -+ } -+ } -+ up_write(¤t->mm->mmap_sem); -+ } -+ -+ /* Free up the videocore allocated resource. -+ */ -+ if (resource->res_handle) { -+ VC_SM_FREE_T free = { -+ resource->res_handle, resource->res_base_mem -+ }; -+ int status = vc_vchi_sm_free(sm_state->sm_handle, &free, -+ &private->int_trans_id); -+ if (status != 0 && status != -EINTR) { -+ pr_err("[%s]: failed to free memory on videocore (status: %u, trans_id: %u)\n", -+ __func__, status, private->int_trans_id); -+ resource->res_stats[FREE_FAIL]++; -+ ret = -EPERM; -+ } -+ } -+ -+ /* Free up the shared resource. -+ */ -+ if (resource->res_shared) -+ vmcs_sm_release_resource(resource->res_shared, 0); -+ -+ /* Free up the local resource tracking this allocation. -+ */ -+ vc_sm_resource_deceased(resource, force); -+ kfree(resource); -+} -+ -+/* Dump the map table for the driver. If process is -1, dumps the whole table, -+** if process is a valid pid (non -1) dump only the entries associated with the -+** pid of interest. -+*/ -+static void vmcs_sm_host_walk_map_per_pid(int pid) -+{ -+ struct sm_mmap *map = NULL; -+ -+ /* Make sure the device was started properly. -+ */ -+ if (sm_state == NULL) { -+ pr_err("[%s]: invalid device\n", __func__); -+ return; -+ } -+ -+ mutex_lock(&(sm_state->map_lock)); -+ -+ /* Log all applicable mapping(s). -+ */ -+ if (!list_empty(&sm_state->map_list)) { -+ list_for_each_entry(map, &sm_state->map_list, map_list) { -+ if (pid == -1 || map->res_pid == pid) { -+ pr_info("[%s]: tgid: %u - vc-hdl: %x, usr-hdl: %x, usr-addr: %lx\n", -+ __func__, map->res_pid, map->res_vc_hdl, -+ map->res_usr_hdl, map->res_addr); -+ } -+ } -+ } -+ -+ mutex_unlock(&(sm_state->map_lock)); -+ -+ return; -+} -+ -+/* Dump the allocation table from host side point of view. This only dumps the -+** data allocated for this process/device referenced by the file_data. -+*/ -+static void vmcs_sm_host_walk_alloc(struct SM_PRIV_DATA_T *file_data) -+{ -+ struct SM_RESOURCE_T *resource = NULL; -+ -+ /* Make sure the device was started properly. -+ */ -+ if ((sm_state == NULL) || (file_data == NULL)) { -+ pr_err("[%s]: invalid device\n", __func__); -+ return; -+ } -+ -+ mutex_lock(&(sm_state->map_lock)); -+ -+ if (!list_empty(&file_data->resource_list)) { -+ list_for_each_entry(resource, &file_data->resource_list, -+ resource_list) { -+ pr_info("[%s]: guid: %x - hdl: %x, vc-mem: %p, size: %u, cache: %u\n", -+ __func__, resource->res_guid, resource->res_handle, -+ resource->res_base_mem, resource->res_size, -+ resource->res_cached); -+ } -+ } -+ -+ mutex_unlock(&(sm_state->map_lock)); -+ -+ return; -+} -+ -+/* Create support for private data tracking. -+*/ -+static struct SM_PRIV_DATA_T *vc_sm_create_priv_data(pid_t id) -+{ -+ char alloc_name[32]; -+ struct SM_PRIV_DATA_T *file_data = NULL; -+ -+ /* Allocate private structure. */ -+ file_data = kzalloc(sizeof(*file_data), GFP_KERNEL); -+ -+ if (!file_data) { -+ pr_err("[%s]: cannot allocate file data\n", __func__); -+ goto out; -+ } -+ -+ snprintf(alloc_name, sizeof(alloc_name), "%d", id); -+ -+ INIT_LIST_HEAD(&file_data->resource_list); -+ file_data->pid = id; -+ file_data->dir_pid = debugfs_create_dir(alloc_name, -+ sm_state->dir_alloc); -+#if 0 -+ /* TODO: fix this to support querying statistics per pid */ -+ -+ if (IS_ERR_OR_NULL(file_data->dir_pid)) { -+ file_data->dir_pid = NULL; -+ } else { -+ struct dentry *dir_entry; -+ -+ dir_entry = debugfs_create_file(VC_SM_RESOURCES, S_IRUGO, -+ file_data->dir_pid, file_data, -+ vc_sm_debug_fs_fops); -+ -+ file_data->dir_res.dir_entry = dir_entry; -+ file_data->dir_res.priv_data = file_data; -+ file_data->dir_res.show = &vc_sm_alloc_show; -+ -+ dir_entry = debugfs_create_file(VC_SM_STATS, S_IRUGO, -+ file_data->dir_pid, file_data, -+ vc_sm_debug_fs_fops); -+ -+ file_data->dir_res.dir_entry = dir_entry; -+ file_data->dir_res.priv_data = file_data; -+ file_data->dir_res.show = &vc_sm_statistics_show; -+ } -+ pr_debug("[%s]: private data allocated %p\n", __func__, file_data); -+ -+#endif -+out: -+ return file_data; -+} -+ -+/* Open the device. Creates a private state to help track all allocation -+** associated with this device. -+*/ -+static int vc_sm_open(struct inode *inode, struct file *file) -+{ -+ int ret = 0; -+ -+ /* Make sure the device was started properly. -+ */ -+ if (!sm_state) { -+ pr_err("[%s]: invalid device\n", __func__); -+ ret = -EPERM; -+ goto out; -+ } -+ -+ file->private_data = vc_sm_create_priv_data(current->tgid); -+ if (file->private_data == NULL) { -+ pr_err("[%s]: failed to create data tracker\n", __func__); -+ -+ ret = -ENOMEM; -+ goto out; -+ } -+ -+out: -+ return ret; -+} -+ -+/* Close the device. Free up all resources still associated with this device -+** at the time. -+*/ -+static int vc_sm_release(struct inode *inode, struct file *file) -+{ -+ struct SM_PRIV_DATA_T *file_data = -+ (struct SM_PRIV_DATA_T *)file->private_data; -+ struct SM_RESOURCE_T *resource; -+ int ret = 0; -+ -+ /* Make sure the device was started properly. -+ */ -+ if (sm_state == NULL || file_data == NULL) { -+ pr_err("[%s]: invalid device\n", __func__); -+ ret = -EPERM; -+ goto out; -+ } -+ -+ pr_debug("[%s]: using private data %p\n", __func__, file_data); -+ -+ if (file_data->restart_sys == -EINTR) { -+ VC_SM_ACTION_CLEAN_T action_clean; -+ -+ pr_debug("[%s]: releasing following EINTR on %u (trans_id: %u) (likely due to signal)...\n", -+ __func__, file_data->int_action, -+ file_data->int_trans_id); -+ -+ action_clean.res_action = file_data->int_action; -+ action_clean.action_trans_id = file_data->int_trans_id; -+ -+ vc_vchi_sm_clean_up(sm_state->sm_handle, &action_clean); -+ } -+ -+ while ((resource = vmcs_sm_acquire_first_resource(file_data)) != NULL) { -+ vmcs_sm_release_resource(resource, 0); -+ vmcs_sm_release_resource(resource, 1); -+ } -+ -+ /* Remove the corresponding proc entry. */ -+ debugfs_remove_recursive(file_data->dir_pid); -+ -+ /* Terminate the private data. -+ */ -+ kfree(file_data); -+ -+out: -+ return ret; -+} -+ -+static void vcsm_vma_open(struct vm_area_struct *vma) -+{ -+ struct sm_mmap *map = (struct sm_mmap *)vma->vm_private_data; -+ -+ pr_debug("[%s]: virt %lx-%lx, pid %i, pfn %i\n", -+ __func__, vma->vm_start, vma->vm_end, (int)current->tgid, -+ (int)vma->vm_pgoff); -+ -+ map->ref_count++; -+} -+ -+static void vcsm_vma_close(struct vm_area_struct *vma) -+{ -+ struct sm_mmap *map = (struct sm_mmap *)vma->vm_private_data; -+ -+ pr_debug("[%s]: virt %lx-%lx, pid %i, pfn %i\n", -+ __func__, vma->vm_start, vma->vm_end, (int)current->tgid, -+ (int)vma->vm_pgoff); -+ -+ map->ref_count--; -+ -+ /* Remove from the map table. -+ */ -+ if (map->ref_count == 0) -+ vmcs_sm_remove_map(sm_state, map->resource, map); -+} -+ -+static int vcsm_vma_fault(struct vm_area_struct *vma, struct vm_fault *vmf) -+{ -+ struct sm_mmap *map = (struct sm_mmap *)vma->vm_private_data; -+ struct SM_RESOURCE_T *resource = map->resource; -+ pgoff_t page_offset; -+ unsigned long pfn; -+ int ret = 0; -+ -+ /* Lock the resource if necessary. -+ */ -+ if (!resource->lock_count) { -+ VC_SM_LOCK_UNLOCK_T lock_unlock; -+ VC_SM_LOCK_RESULT_T lock_result; -+ int status; -+ -+ lock_unlock.res_handle = resource->res_handle; -+ lock_unlock.res_mem = resource->res_base_mem; -+ -+ pr_debug("[%s]: attempt to lock data - hdl %x, base address %p\n", -+ __func__, lock_unlock.res_handle, lock_unlock.res_mem); -+ -+ /* Lock the videocore allocated resource. -+ */ -+ status = vc_vchi_sm_lock(sm_state->sm_handle, -+ &lock_unlock, &lock_result, 0); -+ if ((status != 0) || -+ ((status == 0) && (lock_result.res_mem == NULL))) { -+ pr_err("[%s]: failed to lock memory on videocore (status: %u)\n", -+ __func__, status); -+ resource->res_stats[LOCK_FAIL]++; -+ return VM_FAULT_SIGBUS; -+ } -+ -+ pfn = vcaddr_to_pfn((unsigned long)resource->res_base_mem); -+ outer_inv_range(__pfn_to_phys(pfn), -+ __pfn_to_phys(pfn) + resource->res_size); -+ -+ resource->res_stats[LOCK]++; -+ resource->lock_count++; -+ -+ /* Keep track of the new base memory. -+ */ -+ if ((lock_result.res_mem != NULL) && -+ (lock_result.res_old_mem != NULL) && -+ (lock_result.res_mem != lock_result.res_old_mem)) { -+ resource->res_base_mem = lock_result.res_mem; -+ } -+ } -+ -+ /* We don't use vmf->pgoff since that has the fake offset */ -+ page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start); -+ pfn = (uint32_t)resource->res_base_mem & 0x3FFFFFFF; -+ pfn += mm_vc_mem_phys_addr; -+ pfn += page_offset; -+ pfn >>= PAGE_SHIFT; -+ -+ /* Finally, remap it */ -+ ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); -+ -+ switch (ret) { -+ case 0: -+ case -ERESTARTSYS: -+ return VM_FAULT_NOPAGE; -+ case -ENOMEM: -+ case -EAGAIN: -+ return VM_FAULT_OOM; -+ default: -+ return VM_FAULT_SIGBUS; -+ } -+} -+ -+static struct vm_operations_struct vcsm_vm_ops = { -+ .open = vcsm_vma_open, -+ .close = vcsm_vma_close, -+ .fault = vcsm_vma_fault, -+}; -+ -+/* Walks a VMA and clean each valid page from the cache */ -+static void vcsm_vma_cache_clean_page_range(unsigned long addr, -+ unsigned long end) -+{ -+ pgd_t *pgd; -+ pud_t *pud; -+ pmd_t *pmd; -+ pte_t *pte; -+ unsigned long pgd_next, pud_next, pmd_next; -+ -+ if (addr >= end) -+ return; -+ -+ /* Walk PGD */ -+ pgd = pgd_offset(current->mm, addr); -+ do { -+ pgd_next = pgd_addr_end(addr, end); -+ -+ if (pgd_none(*pgd) || pgd_bad(*pgd)) -+ continue; -+ -+ /* Walk PUD */ -+ pud = pud_offset(pgd, addr); -+ do { -+ pud_next = pud_addr_end(addr, pgd_next); -+ if (pud_none(*pud) || pud_bad(*pud)) -+ continue; -+ -+ /* Walk PMD */ -+ pmd = pmd_offset(pud, addr); -+ do { -+ pmd_next = pmd_addr_end(addr, pud_next); -+ if (pmd_none(*pmd) || pmd_bad(*pmd)) -+ continue; -+ -+ /* Walk PTE */ -+ pte = pte_offset_map(pmd, addr); -+ do { -+ if (pte_none(*pte) -+ || !pte_present(*pte)) -+ continue; -+ -+ /* Clean + invalidate */ -+ dmac_flush_range((const void *) addr, -+ (const void *) -+ (addr + PAGE_SIZE)); -+ -+ } while (pte++, addr += -+ PAGE_SIZE, addr != pmd_next); -+ pte_unmap(pte); -+ -+ } while (pmd++, addr = pmd_next, addr != pud_next); -+ -+ } while (pud++, addr = pud_next, addr != pgd_next); -+ } while (pgd++, addr = pgd_next, addr != end); -+} -+ -+/* Map an allocated data into something that the user space. -+*/ -+static int vc_sm_mmap(struct file *file, struct vm_area_struct *vma) -+{ -+ int ret = 0; -+ struct SM_PRIV_DATA_T *file_data = -+ (struct SM_PRIV_DATA_T *)file->private_data; -+ struct SM_RESOURCE_T *resource = NULL; -+ struct sm_mmap *map = NULL; -+ -+ /* Make sure the device was started properly. -+ */ -+ if ((sm_state == NULL) || (file_data == NULL)) { -+ pr_err("[%s]: invalid device\n", __func__); -+ return -EPERM; -+ } -+ -+ pr_debug("[%s]: private data %p, guid %x\n", __func__, file_data, -+ ((unsigned int)vma->vm_pgoff << PAGE_SHIFT)); -+ -+ /* We lookup to make sure that the data we are being asked to mmap is -+ ** something that we allocated. -+ ** -+ ** We use the offset information as the key to tell us which resource -+ ** we are mapping. -+ */ -+ resource = vmcs_sm_acquire_resource(file_data, -+ ((unsigned int)vma->vm_pgoff << -+ PAGE_SHIFT)); -+ if (resource == NULL) { -+ pr_err("[%s]: failed to locate resource for guid %x\n", __func__, -+ ((unsigned int)vma->vm_pgoff << PAGE_SHIFT)); -+ return -ENOMEM; -+ } -+ -+ pr_debug("[%s]: guid %x, tgid %u, %u, %u\n", -+ __func__, resource->res_guid, current->tgid, resource->pid, -+ file_data->pid); -+ -+ /* Check permissions. -+ */ -+ if (resource->pid && (resource->pid != current->tgid)) { -+ pr_err("[%s]: current tgid %u != %u owner\n", -+ __func__, current->tgid, resource->pid); -+ ret = -EPERM; -+ goto error; -+ } -+ -+ /* Verify that what we are asked to mmap is proper. -+ */ -+ if (resource->res_size != (unsigned int)(vma->vm_end - vma->vm_start)) { -+ pr_err("[%s]: size inconsistency (resource: %u - mmap: %u)\n", -+ __func__, -+ resource->res_size, -+ (unsigned int)(vma->vm_end - vma->vm_start)); -+ -+ ret = -EINVAL; -+ goto error; -+ } -+ -+ /* Keep track of the tuple in the global resource list such that one -+ * can do a mapping lookup for address/memory handle. -+ */ -+ map = kzalloc(sizeof(*map), GFP_KERNEL); -+ if (map == NULL) { -+ pr_err("[%s]: failed to allocate global tracking resource\n", -+ __func__); -+ ret = -ENOMEM; -+ goto error; -+ } -+ -+ map->res_pid = current->tgid; -+ map->res_vc_hdl = resource->res_handle; -+ map->res_usr_hdl = resource->res_guid; -+ map->res_addr = (long unsigned int)vma->vm_start; -+ map->resource = resource; -+ map->vma = vma; -+ vmcs_sm_add_map(sm_state, resource, map); -+ -+ /* We are not actually mapping the pages, we just provide a fault -+ ** handler to allow pages to be mapped when accessed -+ */ -+ vma->vm_flags |= -+ VM_IO | VM_PFNMAP | VM_DONTCOPY | VM_DONTEXPAND; -+ vma->vm_ops = &vcsm_vm_ops; -+ vma->vm_private_data = map; -+ -+ /* vm_pgoff is the first PFN of the mapped memory */ -+ vma->vm_pgoff = (unsigned long)resource->res_base_mem & 0x3FFFFFFF; -+ vma->vm_pgoff += mm_vc_mem_phys_addr; -+ vma->vm_pgoff >>= PAGE_SHIFT; -+ -+ if ((resource->res_cached == VMCS_SM_CACHE_NONE) || -+ (resource->res_cached == VMCS_SM_CACHE_VC)) { -+ /* Allocated non host cached memory, honour it. -+ */ -+ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); -+ } -+ -+ pr_debug("[%s]: resource %p (guid %x) - cnt %u, base address %p, handle %x, size %u (%u), cache %u\n", -+ __func__, -+ resource, resource->res_guid, resource->lock_count, -+ resource->res_base_mem, resource->res_handle, -+ resource->res_size, (unsigned int)(vma->vm_end - vma->vm_start), -+ resource->res_cached); -+ -+ pr_debug("[%s]: resource %p (base address %p, handle %x) - map-count %d, usr-addr %x\n", -+ __func__, resource, resource->res_base_mem, -+ resource->res_handle, resource->map_count, -+ (unsigned int)vma->vm_start); -+ -+ vcsm_vma_open(vma); -+ resource->res_stats[MAP]++; -+ vmcs_sm_release_resource(resource, 0); -+ return 0; -+ -+error: -+ resource->res_stats[MAP_FAIL]++; -+ vmcs_sm_release_resource(resource, 0); -+ return ret; -+} -+ -+/* Allocate a shared memory handle and block. -+*/ -+int vc_sm_ioctl_alloc(struct SM_PRIV_DATA_T *private, -+ struct vmcs_sm_ioctl_alloc *ioparam) -+{ -+ int ret = 0; -+ int status; -+ struct SM_RESOURCE_T *resource; -+ VC_SM_ALLOC_T alloc = { 0 }; -+ VC_SM_ALLOC_RESULT_T result = { 0 }; -+ -+ /* Setup our allocation parameters */ -+ alloc.type = ((ioparam->cached == VMCS_SM_CACHE_VC) -+ || (ioparam->cached == -+ VMCS_SM_CACHE_BOTH)) ? VC_SM_ALLOC_CACHED : -+ VC_SM_ALLOC_NON_CACHED; -+ alloc.base_unit = ioparam->size; -+ alloc.num_unit = ioparam->num; -+ alloc.allocator = current->tgid; -+ /* Align to kernel page size */ -+ alloc.alignement = 4096; -+ /* Align the size to the kernel page size */ -+ alloc.base_unit = -+ (alloc.base_unit + alloc.alignement - 1) & ~(alloc.alignement - 1); -+ if (*ioparam->name) { -+ memcpy(alloc.name, ioparam->name, sizeof(alloc.name) - 1); -+ } else { -+ memcpy(alloc.name, VMCS_SM_RESOURCE_NAME_DEFAULT, -+ sizeof(VMCS_SM_RESOURCE_NAME_DEFAULT)); -+ } -+ -+ pr_debug("[%s]: attempt to allocate \"%s\" data - type %u, base %u (%u), num %u, alignement %u\n", -+ __func__, alloc.name, alloc.type, ioparam->size, -+ alloc.base_unit, alloc.num_unit, alloc.alignement); -+ -+ /* Allocate local resource to track this allocation. -+ */ -+ resource = kzalloc(sizeof(*resource), GFP_KERNEL); -+ if (!resource) { -+ ret = -ENOMEM; -+ goto error; -+ } -+ INIT_LIST_HEAD(&resource->map_list); -+ resource->ref_count++; -+ resource->pid = current->tgid; -+ -+ /* Allocate the videocore resource. -+ */ -+ status = vc_vchi_sm_alloc(sm_state->sm_handle, &alloc, &result, -+ &private->int_trans_id); -+ if (status == -EINTR) { -+ pr_debug("[%s]: requesting allocate memory action restart (trans_id: %u)\n", -+ __func__, private->int_trans_id); -+ ret = -ERESTARTSYS; -+ private->restart_sys = -EINTR; -+ private->int_action = VC_SM_MSG_TYPE_ALLOC; -+ goto error; -+ } else if (status != 0 || (status == 0 && result.res_mem == NULL)) { -+ pr_err("[%s]: failed to allocate memory on videocore (status: %u, trans_id: %u)\n", -+ __func__, status, private->int_trans_id); -+ ret = -ENOMEM; -+ resource->res_stats[ALLOC_FAIL]++; -+ goto error; -+ } -+ -+ /* Keep track of the resource we created. -+ */ -+ resource->private = private; -+ resource->res_handle = result.res_handle; -+ resource->res_base_mem = result.res_mem; -+ resource->res_size = alloc.base_unit * alloc.num_unit; -+ resource->res_cached = ioparam->cached; -+ -+ /* Kernel/user GUID. This global identifier is used for mmap'ing the -+ * allocated region from user space, it is passed as the mmap'ing -+ * offset, we use it to 'hide' the videocore handle/address. -+ */ -+ mutex_lock(&sm_state->lock); -+ resource->res_guid = ++sm_state->guid; -+ mutex_unlock(&sm_state->lock); -+ resource->res_guid <<= PAGE_SHIFT; -+ -+ vmcs_sm_add_resource(private, resource); -+ -+ pr_debug("[%s]: allocated data - guid %x, hdl %x, base address %p, size %d, cache %d\n", -+ __func__, resource->res_guid, resource->res_handle, -+ resource->res_base_mem, resource->res_size, -+ resource->res_cached); -+ -+ /* We're done */ -+ resource->res_stats[ALLOC]++; -+ ioparam->handle = resource->res_guid; -+ return 0; -+ -+error: -+ pr_err("[%s]: failed to allocate \"%s\" data (%i) - type %u, base %u (%u), num %u, alignment %u\n", -+ __func__, alloc.name, ret, alloc.type, ioparam->size, -+ alloc.base_unit, alloc.num_unit, alloc.alignement); -+ if (resource != NULL) { -+ vc_sm_resource_deceased(resource, 1); -+ kfree(resource); -+ } -+ return ret; -+} -+ -+/* Share an allocate memory handle and block. -+*/ -+int vc_sm_ioctl_alloc_share(struct SM_PRIV_DATA_T *private, -+ struct vmcs_sm_ioctl_alloc_share *ioparam) -+{ -+ struct SM_RESOURCE_T *resource, *shared_resource; -+ int ret = 0; -+ -+ pr_debug("[%s]: attempt to share resource %u\n", __func__, -+ ioparam->handle); -+ -+ shared_resource = vmcs_sm_acquire_global_resource(ioparam->handle); -+ if (shared_resource == NULL) { -+ ret = -ENOMEM; -+ goto error; -+ } -+ -+ /* Allocate local resource to track this allocation. -+ */ -+ resource = kzalloc(sizeof(*resource), GFP_KERNEL); -+ if (resource == NULL) { -+ pr_err("[%s]: failed to allocate local tracking resource\n", -+ __func__); -+ ret = -ENOMEM; -+ goto error; -+ } -+ INIT_LIST_HEAD(&resource->map_list); -+ resource->ref_count++; -+ resource->pid = current->tgid; -+ -+ /* Keep track of the resource we created. -+ */ -+ resource->private = private; -+ resource->res_handle = shared_resource->res_handle; -+ resource->res_base_mem = shared_resource->res_base_mem; -+ resource->res_size = shared_resource->res_size; -+ resource->res_cached = shared_resource->res_cached; -+ resource->res_shared = shared_resource; -+ -+ mutex_lock(&sm_state->lock); -+ resource->res_guid = ++sm_state->guid; -+ mutex_unlock(&sm_state->lock); -+ resource->res_guid <<= PAGE_SHIFT; -+ -+ vmcs_sm_add_resource(private, resource); -+ -+ pr_debug("[%s]: allocated data - guid %x, hdl %x, base address %p, size %d, cache %d\n", -+ __func__, resource->res_guid, resource->res_handle, -+ resource->res_base_mem, resource->res_size, -+ resource->res_cached); -+ -+ /* We're done */ -+ resource->res_stats[ALLOC]++; -+ ioparam->handle = resource->res_guid; -+ ioparam->size = resource->res_size; -+ return 0; -+ -+error: -+ pr_err("[%s]: failed to share %u\n", __func__, ioparam->handle); -+ if (shared_resource != NULL) -+ vmcs_sm_release_resource(shared_resource, 0); -+ -+ return ret; -+} -+ -+/* Free a previously allocated shared memory handle and block. -+*/ -+static int vc_sm_ioctl_free(struct SM_PRIV_DATA_T *private, -+ struct vmcs_sm_ioctl_free *ioparam) -+{ -+ struct SM_RESOURCE_T *resource = -+ vmcs_sm_acquire_resource(private, ioparam->handle); -+ -+ if (resource == NULL) { -+ pr_err("[%s]: resource for guid %u does not exist\n", __func__, -+ ioparam->handle); -+ return -EINVAL; -+ } -+ -+ /* Check permissions. -+ */ -+ if (resource->pid && (resource->pid != current->tgid)) { -+ pr_err("[%s]: current tgid %u != %u owner\n", -+ __func__, current->tgid, resource->pid); -+ vmcs_sm_release_resource(resource, 0); -+ return -EPERM; -+ } -+ -+ vmcs_sm_release_resource(resource, 0); -+ vmcs_sm_release_resource(resource, 0); -+ return 0; -+} -+ -+/* Resize a previously allocated shared memory handle and block. -+*/ -+static int vc_sm_ioctl_resize(struct SM_PRIV_DATA_T *private, -+ struct vmcs_sm_ioctl_resize *ioparam) -+{ -+ int ret = 0; -+ int status; -+ VC_SM_RESIZE_T resize; -+ struct SM_RESOURCE_T *resource; -+ -+ /* Locate resource from GUID. -+ */ -+ resource = vmcs_sm_acquire_resource(private, ioparam->handle); -+ if (!resource) { -+ pr_err("[%s]: failed resource - guid %x\n", -+ __func__, ioparam->handle); -+ ret = -EFAULT; -+ goto error; -+ } -+ -+ /* If the resource is locked, its reference count will be not NULL, -+ ** in which case we will not be allowed to resize it anyways, so -+ ** reject the attempt here. -+ */ -+ if (resource->lock_count != 0) { -+ pr_err("[%s]: cannot resize - guid %x, ref-cnt %d\n", -+ __func__, ioparam->handle, resource->lock_count); -+ ret = -EFAULT; -+ goto error; -+ } -+ -+ /* Check permissions. -+ */ -+ if (resource->pid && (resource->pid != current->tgid)) { -+ pr_err("[%s]: current tgid %u != %u owner\n", __func__, -+ current->tgid, resource->pid); -+ ret = -EPERM; -+ goto error; -+ } -+ -+ if (resource->map_count != 0) { -+ pr_err("[%s]: cannot resize - guid %x, ref-cnt %d\n", -+ __func__, ioparam->handle, resource->map_count); -+ ret = -EFAULT; -+ goto error; -+ } -+ -+ resize.res_handle = resource->res_handle; -+ resize.res_mem = resource->res_base_mem; -+ resize.res_new_size = ioparam->new_size; -+ -+ pr_debug("[%s]: attempt to resize data - guid %x, hdl %x, base address %p\n", -+ __func__, ioparam->handle, resize.res_handle, resize.res_mem); -+ -+ /* Resize the videocore allocated resource. -+ */ -+ status = vc_vchi_sm_resize(sm_state->sm_handle, &resize, -+ &private->int_trans_id); -+ if (status == -EINTR) { -+ pr_debug("[%s]: requesting resize memory action restart (trans_id: %u)\n", -+ __func__, private->int_trans_id); -+ ret = -ERESTARTSYS; -+ private->restart_sys = -EINTR; -+ private->int_action = VC_SM_MSG_TYPE_RESIZE; -+ goto error; -+ } else if (status != 0) { -+ pr_err("[%s]: failed to resize memory on videocore (status: %u, trans_id: %u)\n", -+ __func__, status, private->int_trans_id); -+ ret = -EPERM; -+ goto error; -+ } -+ -+ pr_debug("[%s]: success to resize data - hdl %x, size %d -> %d\n", -+ __func__, resize.res_handle, resource->res_size, -+ resize.res_new_size); -+ -+ /* Successfully resized, save the information and inform the user. -+ */ -+ ioparam->old_size = resource->res_size; -+ resource->res_size = resize.res_new_size; -+ -+error: -+ if (resource) -+ vmcs_sm_release_resource(resource, 0); -+ -+ return ret; -+} -+ -+/* Lock a previously allocated shared memory handle and block. -+*/ -+static int vc_sm_ioctl_lock(struct SM_PRIV_DATA_T *private, -+ struct vmcs_sm_ioctl_lock_unlock *ioparam, -+ int change_cache, enum vmcs_sm_cache_e cache_type, -+ unsigned int vc_addr) -+{ -+ int status; -+ VC_SM_LOCK_UNLOCK_T lock; -+ VC_SM_LOCK_RESULT_T result; -+ struct SM_RESOURCE_T *resource; -+ int ret = 0; -+ struct sm_mmap *map, *map_tmp; -+ long unsigned int phys_addr; -+ -+ map = NULL; -+ -+ /* Locate resource from GUID. -+ */ -+ resource = vmcs_sm_acquire_resource(private, ioparam->handle); -+ if (resource == NULL) { -+ ret = -EINVAL; -+ goto error; -+ } -+ -+ /* Check permissions. -+ */ -+ if (resource->pid && (resource->pid != current->tgid)) { -+ pr_err("[%s]: current tgid %u != %u owner\n", __func__, -+ current->tgid, resource->pid); -+ ret = -EPERM; -+ goto error; -+ } -+ -+ lock.res_handle = resource->res_handle; -+ lock.res_mem = resource->res_base_mem; -+ -+ /* Take the lock and get the address to be mapped. -+ */ -+ if (vc_addr == 0) { -+ pr_debug("[%s]: attempt to lock data - guid %x, hdl %x, base address %p\n", -+ __func__, ioparam->handle, lock.res_handle, -+ lock.res_mem); -+ -+ /* Lock the videocore allocated resource. -+ */ -+ status = vc_vchi_sm_lock(sm_state->sm_handle, &lock, &result, -+ &private->int_trans_id); -+ if (status == -EINTR) { -+ pr_debug("[%s]: requesting lock memory action restart (trans_id: %u)\n", -+ __func__, private->int_trans_id); -+ ret = -ERESTARTSYS; -+ private->restart_sys = -EINTR; -+ private->int_action = VC_SM_MSG_TYPE_LOCK; -+ goto error; -+ } else if (status != 0 || -+ (status == 0 && result.res_mem == NULL)) { -+ pr_err("[%s]: failed to lock memory on videocore (status: %u, trans_id: %u)\n", -+ __func__, status, private->int_trans_id); -+ ret = -EPERM; -+ resource->res_stats[LOCK_FAIL]++; -+ goto error; -+ } -+ -+ pr_debug("[%s]: succeed to lock data - hdl %x, base address %p (%p), ref-cnt %d\n", -+ __func__, lock.res_handle, result.res_mem, -+ lock.res_mem, resource->lock_count); -+ } -+ /* Lock assumed taken already, address to be mapped is known. -+ */ -+ else -+ resource->res_base_mem = (void *)vc_addr; -+ -+ resource->res_stats[LOCK]++; -+ resource->lock_count++; -+ -+ /* Keep track of the new base memory allocation if it has changed. -+ */ -+ if ((vc_addr == 0) && -+ (result.res_mem != NULL) && -+ (result.res_old_mem != NULL) && -+ (result.res_mem != result.res_old_mem)) { -+ resource->res_base_mem = result.res_mem; -+ -+ /* Kernel allocated resources. -+ */ -+ if (resource->pid == 0) { -+ if (!list_empty(&resource->map_list)) { -+ list_for_each_entry_safe(map, map_tmp, -+ &resource->map_list, -+ resource_map_list) { -+ if (map->res_addr) { -+ iounmap((void *)map->res_addr); -+ map->res_addr = 0; -+ -+ vmcs_sm_remove_map(sm_state, -+ map->resource, -+ map); -+ break; -+ } -+ } -+ } -+ } -+ } -+ -+ if (change_cache) -+ resource->res_cached = cache_type; -+ -+ if (resource->map_count) { -+ ioparam->addr = -+ vmcs_sm_usr_address_from_pid_and_usr_handle( -+ current->tgid, ioparam->handle); -+ -+ pr_debug("[%s] map_count %d private->pid %d current->tgid %d hnd %x addr %u\n", -+ __func__, resource->map_count, private->pid, -+ current->tgid, ioparam->handle, ioparam->addr); -+ } else { -+ /* Kernel allocated resources. -+ */ -+ if (resource->pid == 0) { -+ pr_debug("[%s]: attempt mapping kernel resource - guid %x, hdl %x\n", -+ __func__, ioparam->handle, lock.res_handle); -+ -+ ioparam->addr = 0; -+ -+ map = kzalloc(sizeof(*map), GFP_KERNEL); -+ if (map == NULL) { -+ pr_err("[%s]: failed allocating tracker\n", -+ __func__); -+ ret = -ENOMEM; -+ goto error; -+ } else { -+ phys_addr = (uint32_t)resource->res_base_mem & -+ 0x3FFFFFFF; -+ phys_addr += mm_vc_mem_phys_addr; -+ if (resource->res_cached -+ == VMCS_SM_CACHE_HOST) { -+ ioparam->addr = (long unsigned int) -+ /* TODO - make cached work */ -+ ioremap_nocache(phys_addr, -+ resource->res_size); -+ -+ pr_debug("[%s]: mapping kernel - guid %x, hdl %x - cached mapping %u\n", -+ __func__, ioparam->handle, -+ lock.res_handle, ioparam->addr); -+ } else { -+ ioparam->addr = (long unsigned int) -+ ioremap_nocache(phys_addr, -+ resource->res_size); -+ -+ pr_debug("[%s]: mapping kernel- guid %x, hdl %x - non cached mapping %u\n", -+ __func__, ioparam->handle, -+ lock.res_handle, ioparam->addr); -+ } -+ -+ map->res_pid = 0; -+ map->res_vc_hdl = resource->res_handle; -+ map->res_usr_hdl = resource->res_guid; -+ map->res_addr = ioparam->addr; -+ map->resource = resource; -+ map->vma = NULL; -+ -+ vmcs_sm_add_map(sm_state, resource, map); -+ } -+ } else -+ ioparam->addr = 0; -+ } -+ -+error: -+ if (resource) -+ vmcs_sm_release_resource(resource, 0); -+ -+ return ret; -+} -+ -+/* Unlock a previously allocated shared memory handle and block. -+*/ -+static int vc_sm_ioctl_unlock(struct SM_PRIV_DATA_T *private, -+ struct vmcs_sm_ioctl_lock_unlock *ioparam, -+ int flush, int wait_reply, int no_vc_unlock) -+{ -+ int status; -+ VC_SM_LOCK_UNLOCK_T unlock; -+ struct sm_mmap *map, *map_tmp; -+ struct SM_RESOURCE_T *resource; -+ int ret = 0; -+ -+ map = NULL; -+ -+ /* Locate resource from GUID. -+ */ -+ resource = vmcs_sm_acquire_resource(private, ioparam->handle); -+ if (resource == NULL) { -+ ret = -EINVAL; -+ goto error; -+ } -+ -+ /* Check permissions. -+ */ -+ if (resource->pid && (resource->pid != current->tgid)) { -+ pr_err("[%s]: current tgid %u != %u owner\n", -+ __func__, current->tgid, resource->pid); -+ ret = -EPERM; -+ goto error; -+ } -+ -+ unlock.res_handle = resource->res_handle; -+ unlock.res_mem = resource->res_base_mem; -+ -+ pr_debug("[%s]: attempt to unlock data - guid %x, hdl %x, base address %p\n", -+ __func__, ioparam->handle, unlock.res_handle, unlock.res_mem); -+ -+ /* User space allocated resources. -+ */ -+ if (resource->pid) { -+ /* Flush if requested */ -+ if (resource->res_cached && flush) { -+ dma_addr_t phys_addr = 0; -+ resource->res_stats[FLUSH]++; -+ -+ phys_addr = -+ (dma_addr_t)((uint32_t)resource->res_base_mem & -+ 0x3FFFFFFF); -+ phys_addr += (dma_addr_t)mm_vc_mem_phys_addr; -+ -+ /* L1 cache flush */ -+ down_read(¤t->mm->mmap_sem); -+ list_for_each_entry(map, &resource->map_list, -+ resource_map_list) { -+ if (map->vma) { -+ unsigned long start; -+ unsigned long end; -+ start = map->vma->vm_start; -+ end = map->vma->vm_end; -+ -+ vcsm_vma_cache_clean_page_range( -+ start, end); -+ } -+ } -+ up_read(¤t->mm->mmap_sem); -+ -+ /* L2 cache flush */ -+ outer_clean_range(phys_addr, -+ phys_addr + -+ (size_t) resource->res_size); -+ } -+ -+ /* We need to zap all the vmas associated with this resource */ -+ if (resource->lock_count == 1) { -+ down_read(¤t->mm->mmap_sem); -+ list_for_each_entry(map, &resource->map_list, -+ resource_map_list) { -+ if (map->vma) { -+ zap_vma_ptes(map->vma, -+ map->vma->vm_start, -+ map->vma->vm_end - -+ map->vma->vm_start); -+ } -+ } -+ up_read(¤t->mm->mmap_sem); -+ } -+ } -+ /* Kernel allocated resources. */ -+ else { -+ /* Global + Taken in this context */ -+ if (resource->ref_count == 2) { -+ if (!list_empty(&resource->map_list)) { -+ list_for_each_entry_safe(map, map_tmp, -+ &resource->map_list, -+ resource_map_list) { -+ if (map->res_addr) { -+ if (flush && -+ (resource->res_cached == -+ VMCS_SM_CACHE_HOST)) { -+ long unsigned int -+ phys_addr; -+ phys_addr = (uint32_t) -+ resource->res_base_mem & 0x3FFFFFFF; -+ phys_addr += -+ mm_vc_mem_phys_addr; -+ -+ /* L1 cache flush */ -+ dmac_flush_range((const -+ void -+ *) -+ map->res_addr, (const void *) -+ (map->res_addr + resource->res_size)); -+ -+ /* L2 cache flush */ -+ outer_clean_range -+ (phys_addr, -+ phys_addr + -+ (size_t) -+ resource->res_size); -+ } -+ -+ iounmap((void *)map->res_addr); -+ map->res_addr = 0; -+ -+ vmcs_sm_remove_map(sm_state, -+ map->resource, -+ map); -+ break; -+ } -+ } -+ } -+ } -+ } -+ -+ if (resource->lock_count) { -+ /* Bypass the videocore unlock. -+ */ -+ if (no_vc_unlock) -+ status = 0; -+ /* Unlock the videocore allocated resource. -+ */ -+ else { -+ status = -+ vc_vchi_sm_unlock(sm_state->sm_handle, &unlock, -+ &private->int_trans_id, -+ wait_reply); -+ if (status == -EINTR) { -+ pr_debug("[%s]: requesting unlock memory action restart (trans_id: %u)\n", -+ __func__, private->int_trans_id); -+ -+ ret = -ERESTARTSYS; -+ resource->res_stats[UNLOCK]--; -+ private->restart_sys = -EINTR; -+ private->int_action = VC_SM_MSG_TYPE_UNLOCK; -+ goto error; -+ } else if (status != 0) { -+ pr_err("[%s]: failed to unlock vc mem (status: %u, trans_id: %u)\n", -+ __func__, status, private->int_trans_id); -+ -+ ret = -EPERM; -+ resource->res_stats[UNLOCK_FAIL]++; -+ goto error; -+ } -+ } -+ -+ resource->res_stats[UNLOCK]++; -+ resource->lock_count--; -+ } -+ -+ pr_debug("[%s]: success to unlock data - hdl %x, base address %p, ref-cnt %d\n", -+ __func__, unlock.res_handle, unlock.res_mem, -+ resource->lock_count); -+ -+error: -+ if (resource) -+ vmcs_sm_release_resource(resource, 0); -+ -+ return ret; -+} -+ -+/* Handle control from host. */ -+static long vc_sm_ioctl(struct file *file, unsigned int cmd, unsigned long arg) -+{ -+ int ret = 0; -+ unsigned int cmdnr = _IOC_NR(cmd); -+ struct SM_PRIV_DATA_T *file_data = -+ (struct SM_PRIV_DATA_T *)file->private_data; -+ struct SM_RESOURCE_T *resource = NULL; -+ -+ /* Validate we can work with this device. */ -+ if ((sm_state == NULL) || (file_data == NULL)) { -+ pr_err("[%s]: invalid device\n", __func__); -+ ret = -EPERM; -+ goto out; -+ } -+ -+ pr_debug("[%s]: cmd %x tgid %u, owner %u\n", __func__, cmdnr, -+ current->tgid, file_data->pid); -+ -+ /* Action is a re-post of a previously interrupted action? */ -+ if (file_data->restart_sys == -EINTR) { -+ VC_SM_ACTION_CLEAN_T action_clean; -+ -+ pr_debug("[%s]: clean up of action %u (trans_id: %u) following EINTR\n", -+ __func__, file_data->int_action, -+ file_data->int_trans_id); -+ -+ action_clean.res_action = file_data->int_action; -+ action_clean.action_trans_id = file_data->int_trans_id; -+ -+ vc_vchi_sm_clean_up(sm_state->sm_handle, &action_clean); -+ -+ file_data->restart_sys = 0; -+ } -+ -+ /* Now process the command. -+ */ -+ switch (cmdnr) { -+ /* New memory allocation. -+ */ -+ case VMCS_SM_CMD_ALLOC: -+ { -+ struct vmcs_sm_ioctl_alloc ioparam; -+ -+ /* Get the parameter data. -+ */ -+ if (copy_from_user -+ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) { -+ pr_err("[%s]: failed to copy-from-user for cmd %x\n", -+ __func__, cmdnr); -+ ret = -EFAULT; -+ goto out; -+ } -+ -+ ret = vc_sm_ioctl_alloc(file_data, &ioparam); -+ if (!ret && -+ (copy_to_user((void *)arg, -+ &ioparam, sizeof(ioparam)) != 0)) { -+ struct vmcs_sm_ioctl_free freeparam = { -+ ioparam.handle -+ }; -+ pr_err("[%s]: failed to copy-to-user for cmd %x\n", -+ __func__, cmdnr); -+ vc_sm_ioctl_free(file_data, &freeparam); -+ ret = -EFAULT; -+ } -+ -+ /* Done. -+ */ -+ goto out; -+ } -+ break; -+ -+ /* Share existing memory allocation. -+ */ -+ case VMCS_SM_CMD_ALLOC_SHARE: -+ { -+ struct vmcs_sm_ioctl_alloc_share ioparam; -+ -+ /* Get the parameter data. -+ */ -+ if (copy_from_user -+ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) { -+ pr_err("[%s]: failed to copy-from-user for cmd %x\n", -+ __func__, cmdnr); -+ ret = -EFAULT; -+ goto out; -+ } -+ -+ ret = vc_sm_ioctl_alloc_share(file_data, &ioparam); -+ -+ /* Copy result back to user. -+ */ -+ if (!ret -+ && copy_to_user((void *)arg, &ioparam, -+ sizeof(ioparam)) != 0) { -+ struct vmcs_sm_ioctl_free freeparam = { -+ ioparam.handle -+ }; -+ pr_err("[%s]: failed to copy-to-user for cmd %x\n", -+ __func__, cmdnr); -+ vc_sm_ioctl_free(file_data, &freeparam); -+ ret = -EFAULT; -+ } -+ -+ /* Done. -+ */ -+ goto out; -+ } -+ break; -+ -+ /* Lock (attempt to) *and* register a cache behavior change. -+ */ -+ case VMCS_SM_CMD_LOCK_CACHE: -+ { -+ struct vmcs_sm_ioctl_lock_cache ioparam; -+ struct vmcs_sm_ioctl_lock_unlock lock; -+ -+ /* Get parameter data. -+ */ -+ if (copy_from_user -+ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) { -+ pr_err("[%s]: failed to copy-from-user for cmd %x\n", -+ __func__, cmdnr); -+ ret = -EFAULT; -+ goto out; -+ } -+ -+ lock.handle = ioparam.handle; -+ ret = -+ vc_sm_ioctl_lock(file_data, &lock, 1, -+ ioparam.cached, 0); -+ -+ /* Done. -+ */ -+ goto out; -+ } -+ break; -+ -+ /* Lock (attempt to) existing memory allocation. -+ */ -+ case VMCS_SM_CMD_LOCK: -+ { -+ struct vmcs_sm_ioctl_lock_unlock ioparam; -+ -+ /* Get parameter data. -+ */ -+ if (copy_from_user -+ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) { -+ pr_err("[%s]: failed to copy-from-user for cmd %x\n", -+ __func__, cmdnr); -+ ret = -EFAULT; -+ goto out; -+ } -+ -+ ret = vc_sm_ioctl_lock(file_data, &ioparam, 0, 0, 0); -+ -+ /* Copy result back to user. -+ */ -+ if (copy_to_user((void *)arg, &ioparam, sizeof(ioparam)) -+ != 0) { -+ pr_err("[%s]: failed to copy-to-user for cmd %x\n", -+ __func__, cmdnr); -+ ret = -EFAULT; -+ } -+ -+ /* Done. -+ */ -+ goto out; -+ } -+ break; -+ -+ /* Unlock (attempt to) existing memory allocation. -+ */ -+ case VMCS_SM_CMD_UNLOCK: -+ { -+ struct vmcs_sm_ioctl_lock_unlock ioparam; -+ -+ /* Get parameter data. -+ */ -+ if (copy_from_user -+ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) { -+ pr_err("[%s]: failed to copy-from-user for cmd %x\n", -+ __func__, cmdnr); -+ ret = -EFAULT; -+ goto out; -+ } -+ -+ ret = vc_sm_ioctl_unlock(file_data, &ioparam, 0, 1, 0); -+ -+ /* Done. -+ */ -+ goto out; -+ } -+ break; -+ -+ /* Resize (attempt to) existing memory allocation. -+ */ -+ case VMCS_SM_CMD_RESIZE: -+ { -+ struct vmcs_sm_ioctl_resize ioparam; -+ -+ /* Get parameter data. -+ */ -+ if (copy_from_user -+ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) { -+ pr_err("[%s]: failed to copy-from-user for cmd %x\n", -+ __func__, cmdnr); -+ ret = -EFAULT; -+ goto out; -+ } -+ -+ ret = vc_sm_ioctl_resize(file_data, &ioparam); -+ -+ /* Copy result back to user. -+ */ -+ if (copy_to_user((void *)arg, &ioparam, sizeof(ioparam)) -+ != 0) { -+ pr_err("[%s]: failed to copy-to-user for cmd %x\n", -+ __func__, cmdnr); -+ ret = -EFAULT; -+ } -+ -+ /* Done. -+ */ -+ goto out; -+ } -+ break; -+ -+ /* Terminate existing memory allocation. -+ */ -+ case VMCS_SM_CMD_FREE: -+ { -+ struct vmcs_sm_ioctl_free ioparam; -+ -+ /* Get parameter data. -+ */ -+ if (copy_from_user -+ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) { -+ pr_err("[%s]: failed to copy-from-user for cmd %x\n", -+ __func__, cmdnr); -+ ret = -EFAULT; -+ goto out; -+ } -+ -+ ret = vc_sm_ioctl_free(file_data, &ioparam); -+ -+ /* Done. -+ */ -+ goto out; -+ } -+ break; -+ -+ /* Walk allocation on videocore, information shows up in the -+ ** videocore log. -+ */ -+ case VMCS_SM_CMD_VC_WALK_ALLOC: -+ { -+ pr_debug("[%s]: invoking walk alloc\n", __func__); -+ -+ if (vc_vchi_sm_walk_alloc(sm_state->sm_handle) != 0) -+ pr_err("[%s]: failed to walk-alloc on videocore\n", -+ __func__); -+ -+ /* Done. -+ */ -+ goto out; -+ } -+ break; -+/* Walk mapping table on host, information shows up in the -+ ** kernel log. -+ */ -+ case VMCS_SM_CMD_HOST_WALK_MAP: -+ { -+ /* Use pid of -1 to tell to walk the whole map. */ -+ vmcs_sm_host_walk_map_per_pid(-1); -+ -+ /* Done. */ -+ goto out; -+ } -+ break; -+ -+ /* Walk mapping table per process on host. */ -+ case VMCS_SM_CMD_HOST_WALK_PID_ALLOC: -+ { -+ struct vmcs_sm_ioctl_walk ioparam; -+ -+ /* Get parameter data. */ -+ if (copy_from_user(&ioparam, -+ (void *)arg, sizeof(ioparam)) != 0) { -+ pr_err("[%s]: failed to copy-from-user for cmd %x\n", -+ __func__, cmdnr); -+ ret = -EFAULT; -+ goto out; -+ } -+ -+ vmcs_sm_host_walk_alloc(file_data); -+ -+ /* Done. */ -+ goto out; -+ } -+ break; -+ -+ /* Walk allocation per process on host. */ -+ case VMCS_SM_CMD_HOST_WALK_PID_MAP: -+ { -+ struct vmcs_sm_ioctl_walk ioparam; -+ -+ /* Get parameter data. */ -+ if (copy_from_user(&ioparam, -+ (void *)arg, sizeof(ioparam)) != 0) { -+ pr_err("[%s]: failed to copy-from-user for cmd %x\n", -+ __func__, cmdnr); -+ ret = -EFAULT; -+ goto out; -+ } -+ -+ vmcs_sm_host_walk_map_per_pid(ioparam.pid); -+ -+ /* Done. */ -+ goto out; -+ } -+ break; -+ -+ /* Gets the size of the memory associated with a user handle. */ -+ case VMCS_SM_CMD_SIZE_USR_HANDLE: -+ { -+ struct vmcs_sm_ioctl_size ioparam; -+ -+ /* Get parameter data. */ -+ if (copy_from_user(&ioparam, -+ (void *)arg, sizeof(ioparam)) != 0) { -+ pr_err("[%s]: failed to copy-from-user for cmd %x\n", -+ __func__, cmdnr); -+ ret = -EFAULT; -+ goto out; -+ } -+ -+ /* Locate resource from GUID. */ -+ resource = -+ vmcs_sm_acquire_resource(file_data, ioparam.handle); -+ if (resource != NULL) { -+ ioparam.size = resource->res_size; -+ vmcs_sm_release_resource(resource, 0); -+ } else { -+ ioparam.size = 0; -+ } -+ -+ if (copy_to_user((void *)arg, -+ &ioparam, sizeof(ioparam)) != 0) { -+ pr_err("[%s]: failed to copy-to-user for cmd %x\n", -+ __func__, cmdnr); -+ ret = -EFAULT; -+ } -+ -+ /* Done. */ -+ goto out; -+ } -+ break; -+ -+ /* Verify we are dealing with a valid resource. */ -+ case VMCS_SM_CMD_CHK_USR_HANDLE: -+ { -+ struct vmcs_sm_ioctl_chk ioparam; -+ -+ /* Get parameter data. -+ */ -+ if (copy_from_user(&ioparam, -+ (void *)arg, sizeof(ioparam)) != 0) { -+ pr_err("[%s]: failed to copy-from-user for cmd %x\n", -+ __func__, cmdnr); -+ -+ ret = -EFAULT; -+ goto out; -+ } -+ -+ /* Locate resource from GUID. */ -+ resource = -+ vmcs_sm_acquire_resource(file_data, ioparam.handle); -+ if (resource == NULL) -+ ret = -EINVAL; -+ /* If the resource is cacheable, return additional -+ * information that may be needed to flush the cache. -+ */ -+ else if ((resource->res_cached == VMCS_SM_CACHE_HOST) || -+ (resource->res_cached == VMCS_SM_CACHE_BOTH)) { -+ ioparam.addr = -+ vmcs_sm_usr_address_from_pid_and_usr_handle -+ (current->tgid, ioparam.handle); -+ ioparam.size = resource->res_size; -+ ioparam.cache = resource->res_cached; -+ } else { -+ ioparam.addr = 0; -+ ioparam.size = 0; -+ ioparam.cache = resource->res_cached; -+ } -+ -+ if (resource) -+ vmcs_sm_release_resource(resource, 0); -+ -+ if (copy_to_user((void *)arg, -+ &ioparam, sizeof(ioparam)) != 0) { -+ pr_err("[%s]: failed to copy-to-user for cmd %x\n", -+ __func__, cmdnr); -+ ret = -EFAULT; -+ } -+ -+ /* Done. -+ */ -+ goto out; -+ } -+ break; -+ -+ /* -+ * Maps a user handle given the process and the virtual address. -+ */ -+ case VMCS_SM_CMD_MAPPED_USR_HANDLE: -+ { -+ struct vmcs_sm_ioctl_map ioparam; -+ -+ /* Get parameter data. */ -+ if (copy_from_user(&ioparam, -+ (void *)arg, sizeof(ioparam)) != 0) { -+ pr_err("[%s]: failed to copy-from-user for cmd %x\n", -+ __func__, cmdnr); -+ -+ ret = -EFAULT; -+ goto out; -+ } -+ -+ ioparam.handle = -+ vmcs_sm_usr_handle_from_pid_and_address( -+ ioparam.pid, ioparam.addr); -+ -+ resource = -+ vmcs_sm_acquire_resource(file_data, ioparam.handle); -+ if ((resource != NULL) -+ && ((resource->res_cached == VMCS_SM_CACHE_HOST) -+ || (resource->res_cached == -+ VMCS_SM_CACHE_BOTH))) { -+ ioparam.size = resource->res_size; -+ } else { -+ ioparam.size = 0; -+ } -+ -+ if (resource) -+ vmcs_sm_release_resource(resource, 0); -+ -+ if (copy_to_user((void *)arg, -+ &ioparam, sizeof(ioparam)) != 0) { -+ pr_err("[%s]: failed to copy-to-user for cmd %x\n", -+ __func__, cmdnr); -+ ret = -EFAULT; -+ } -+ -+ /* Done. */ -+ goto out; -+ } -+ break; -+ -+ /* -+ * Maps a videocore handle given process and virtual address. -+ */ -+ case VMCS_SM_CMD_MAPPED_VC_HDL_FROM_ADDR: -+ { -+ struct vmcs_sm_ioctl_map ioparam; -+ -+ /* Get parameter data. */ -+ if (copy_from_user(&ioparam, -+ (void *)arg, sizeof(ioparam)) != 0) { -+ pr_err("[%s]: failed to copy-from-user for cmd %x\n", -+ __func__, cmdnr); -+ ret = -EFAULT; -+ goto out; -+ } -+ -+ ioparam.handle = vmcs_sm_vc_handle_from_pid_and_address( -+ ioparam.pid, ioparam.addr); -+ -+ if (copy_to_user((void *)arg, -+ &ioparam, sizeof(ioparam)) != 0) { -+ pr_err("[%s]: failed to copy-to-user for cmd %x\n", -+ __func__, cmdnr); -+ -+ ret = -EFAULT; -+ } -+ -+ /* Done. -+ */ -+ goto out; -+ } -+ break; -+ -+ /* Maps a videocore handle given process and user handle. */ -+ case VMCS_SM_CMD_MAPPED_VC_HDL_FROM_HDL: -+ { -+ struct vmcs_sm_ioctl_map ioparam; -+ -+ /* Get parameter data. */ -+ if (copy_from_user(&ioparam, -+ (void *)arg, sizeof(ioparam)) != 0) { -+ pr_err("[%s]: failed to copy-from-user for cmd %x\n", -+ __func__, cmdnr); -+ ret = -EFAULT; -+ goto out; -+ } -+ -+ /* Locate resource from GUID. */ -+ resource = -+ vmcs_sm_acquire_resource(file_data, ioparam.handle); -+ if (resource != NULL) { -+ ioparam.handle = resource->res_handle; -+ vmcs_sm_release_resource(resource, 0); -+ } else { -+ ioparam.handle = 0; -+ } -+ -+ if (copy_to_user((void *)arg, -+ &ioparam, sizeof(ioparam)) != 0) { -+ pr_err("[%s]: failed to copy-to-user for cmd %x\n", -+ __func__, cmdnr); -+ -+ ret = -EFAULT; -+ } -+ -+ /* Done. */ -+ goto out; -+ } -+ break; -+ -+ /* -+ * Maps a videocore address given process and videocore handle. -+ */ -+ case VMCS_SM_CMD_MAPPED_VC_ADDR_FROM_HDL: -+ { -+ struct vmcs_sm_ioctl_map ioparam; -+ -+ /* Get parameter data. */ -+ if (copy_from_user(&ioparam, -+ (void *)arg, sizeof(ioparam)) != 0) { -+ pr_err("[%s]: failed to copy-from-user for cmd %x\n", -+ __func__, cmdnr); -+ -+ ret = -EFAULT; -+ goto out; -+ } -+ -+ /* Locate resource from GUID. */ -+ resource = -+ vmcs_sm_acquire_resource(file_data, ioparam.handle); -+ if (resource != NULL) { -+ ioparam.addr = -+ (unsigned int)resource->res_base_mem; -+ vmcs_sm_release_resource(resource, 0); -+ } else { -+ ioparam.addr = 0; -+ } -+ -+ if (copy_to_user((void *)arg, -+ &ioparam, sizeof(ioparam)) != 0) { -+ pr_err("[%s]: failed to copy-to-user for cmd %x\n", -+ __func__, cmdnr); -+ ret = -EFAULT; -+ } -+ -+ /* Done. */ -+ goto out; -+ } -+ break; -+ -+ /* Maps a user address given process and vc handle. -+ */ -+ case VMCS_SM_CMD_MAPPED_USR_ADDRESS: -+ { -+ struct vmcs_sm_ioctl_map ioparam; -+ -+ /* Get parameter data. */ -+ if (copy_from_user(&ioparam, -+ (void *)arg, sizeof(ioparam)) != 0) { -+ pr_err("[%s]: failed to copy-from-user for cmd %x\n", -+ __func__, cmdnr); -+ ret = -EFAULT; -+ goto out; -+ } -+ -+ /* -+ * Return the address information from the mapping, -+ * 0 (ie NULL) if it cannot locate the actual mapping. -+ */ -+ ioparam.addr = -+ vmcs_sm_usr_address_from_pid_and_usr_handle -+ (ioparam.pid, ioparam.handle); -+ -+ if (copy_to_user((void *)arg, -+ &ioparam, sizeof(ioparam)) != 0) { -+ pr_err("[%s]: failed to copy-to-user for cmd %x\n", -+ __func__, cmdnr); -+ ret = -EFAULT; -+ } -+ -+ /* Done. */ -+ goto out; -+ } -+ break; -+ -+ /* Flush the cache for a given mapping. */ -+ case VMCS_SM_CMD_FLUSH: -+ { -+ struct vmcs_sm_ioctl_cache ioparam; -+ -+ /* Get parameter data. */ -+ if (copy_from_user(&ioparam, -+ (void *)arg, sizeof(ioparam)) != 0) { -+ pr_err("[%s]: failed to copy-from-user for cmd %x\n", -+ __func__, cmdnr); -+ ret = -EFAULT; -+ goto out; -+ } -+ -+ /* Locate resource from GUID. */ -+ resource = -+ vmcs_sm_acquire_resource(file_data, ioparam.handle); -+ -+ if ((resource != NULL) && resource->res_cached) { -+ dma_addr_t phys_addr = 0; -+ -+ resource->res_stats[FLUSH]++; -+ -+ phys_addr = -+ (dma_addr_t)((uint32_t) -+ resource->res_base_mem & -+ 0x3FFFFFFF); -+ phys_addr += (dma_addr_t)mm_vc_mem_phys_addr; -+ -+ /* L1 cache flush */ -+ down_read(¤t->mm->mmap_sem); -+ vcsm_vma_cache_clean_page_range((unsigned long) -+ ioparam.addr, -+ (unsigned long) -+ ioparam.addr + -+ ioparam.size); -+ up_read(¤t->mm->mmap_sem); -+ -+ /* L2 cache flush */ -+ outer_clean_range(phys_addr, -+ phys_addr + -+ (size_t) ioparam.size); -+ } else if (resource == NULL) { -+ ret = -EINVAL; -+ goto out; -+ } -+ -+ if (resource) -+ vmcs_sm_release_resource(resource, 0); -+ -+ /* Done. */ -+ goto out; -+ } -+ break; -+ -+ /* Invalidate the cache for a given mapping. */ -+ case VMCS_SM_CMD_INVALID: -+ { -+ struct vmcs_sm_ioctl_cache ioparam; -+ -+ /* Get parameter data. */ -+ if (copy_from_user(&ioparam, -+ (void *)arg, sizeof(ioparam)) != 0) { -+ pr_err("[%s]: failed to copy-from-user for cmd %x\n", -+ __func__, cmdnr); -+ ret = -EFAULT; -+ goto out; -+ } -+ -+ /* Locate resource from GUID. -+ */ -+ resource = -+ vmcs_sm_acquire_resource(file_data, ioparam.handle); -+ -+ if ((resource != NULL) && resource->res_cached) { -+ dma_addr_t phys_addr = 0; -+ -+ resource->res_stats[INVALID]++; -+ -+ phys_addr = -+ (dma_addr_t)((uint32_t) -+ resource->res_base_mem & -+ 0x3FFFFFFF); -+ phys_addr += (dma_addr_t)mm_vc_mem_phys_addr; -+ -+ /* L2 cache invalidate */ -+ outer_inv_range(phys_addr, -+ phys_addr + -+ (size_t) ioparam.size); -+ -+ /* L1 cache invalidate */ -+ down_read(¤t->mm->mmap_sem); -+ vcsm_vma_cache_clean_page_range((unsigned long) -+ ioparam.addr, -+ (unsigned long) -+ ioparam.addr + -+ ioparam.size); -+ up_read(¤t->mm->mmap_sem); -+ } else if (resource == NULL) { -+ ret = -EINVAL; -+ goto out; -+ } -+ -+ if (resource) -+ vmcs_sm_release_resource(resource, 0); -+ -+ /* Done. -+ */ -+ goto out; -+ } -+ break; -+ -+ /* Flush/Invalidate the cache for a given mapping. */ -+ case VMCS_SM_CMD_CLEAN_INVALID: -+ { -+ int i; -+ struct vmcs_sm_ioctl_clean_invalid ioparam; -+ -+ /* Get parameter data. */ -+ if (copy_from_user(&ioparam, -+ (void *)arg, sizeof(ioparam)) != 0) { -+ pr_err("[%s]: failed to copy-from-user for cmd %x\n", -+ __func__, cmdnr); -+ ret = -EFAULT; -+ goto out; -+ } -+ for (i=0; ires_cached) { -+ unsigned long base = ioparam.s[i].addr & ~(PAGE_SIZE-1); -+ unsigned long end = (ioparam.s[i].addr + ioparam.s[i].size + PAGE_SIZE-1) & ~(PAGE_SIZE-1); -+ resource->res_stats[ioparam.s[i].cmd == 1 ? INVALID:FLUSH]++; -+ -+ /* L1/L2 cache flush */ -+ down_read(¤t->mm->mmap_sem); -+ vcsm_vma_cache_clean_page_range(base, end); -+ up_read(¤t->mm->mmap_sem); -+ } else if (resource == NULL) { -+ ret = -EINVAL; -+ goto out; -+ } -+ -+ if (resource) -+ vmcs_sm_release_resource(resource, 0); -+ } -+ break; -+ } -+ } -+ } -+ break; -+ -+ default: -+ { -+ ret = -EINVAL; -+ goto out; -+ } -+ break; -+ } -+ -+out: -+ return ret; -+} -+ -+/* Device operations that we managed in this driver. -+*/ -+static const struct file_operations vmcs_sm_ops = { -+ .owner = THIS_MODULE, -+ .unlocked_ioctl = vc_sm_ioctl, -+ .open = vc_sm_open, -+ .release = vc_sm_release, -+ .mmap = vc_sm_mmap, -+}; -+ -+/* Creation of device. -+*/ -+static int vc_sm_create_sharedmemory(void) -+{ -+ int ret; -+ -+ if (sm_state == NULL) { -+ ret = -ENOMEM; -+ goto out; -+ } -+ -+ /* Create a device class for creating dev nodes. -+ */ -+ sm_state->sm_class = class_create(THIS_MODULE, "vc-sm"); -+ if (IS_ERR(sm_state->sm_class)) { -+ pr_err("[%s]: unable to create device class\n", __func__); -+ ret = PTR_ERR(sm_state->sm_class); -+ goto out; -+ } -+ -+ /* Create a character driver. -+ */ -+ ret = alloc_chrdev_region(&sm_state->sm_devid, -+ DEVICE_MINOR, 1, DEVICE_NAME); -+ if (ret != 0) { -+ pr_err("[%s]: unable to allocate device number\n", __func__); -+ goto out_dev_class_destroy; -+ } -+ -+ cdev_init(&sm_state->sm_cdev, &vmcs_sm_ops); -+ ret = cdev_add(&sm_state->sm_cdev, sm_state->sm_devid, 1); -+ if (ret != 0) { -+ pr_err("[%s]: unable to register device\n", __func__); -+ goto out_chrdev_unreg; -+ } -+ -+ /* Create a device node. -+ */ -+ sm_state->sm_dev = device_create(sm_state->sm_class, -+ NULL, -+ MKDEV(MAJOR(sm_state->sm_devid), -+ DEVICE_MINOR), NULL, -+ DEVICE_NAME); -+ if (IS_ERR(sm_state->sm_dev)) { -+ pr_err("[%s]: unable to create device node\n", __func__); -+ ret = PTR_ERR(sm_state->sm_dev); -+ goto out_chrdev_del; -+ } -+ -+ goto out; -+ -+out_chrdev_del: -+ cdev_del(&sm_state->sm_cdev); -+out_chrdev_unreg: -+ unregister_chrdev_region(sm_state->sm_devid, 1); -+out_dev_class_destroy: -+ class_destroy(sm_state->sm_class); -+ sm_state->sm_class = NULL; -+out: -+ return ret; -+} -+ -+/* Termination of the device. -+*/ -+static int vc_sm_remove_sharedmemory(void) -+{ -+ int ret; -+ -+ if (sm_state == NULL) { -+ /* Nothing to do. -+ */ -+ ret = 0; -+ goto out; -+ } -+ -+ /* Remove the sharedmemory character driver. -+ */ -+ cdev_del(&sm_state->sm_cdev); -+ -+ /* Unregister region. -+ */ -+ unregister_chrdev_region(sm_state->sm_devid, 1); -+ -+ ret = 0; -+ goto out; -+ -+out: -+ return ret; -+} -+ -+/* Videocore connected. */ -+static void vc_sm_connected_init(void) -+{ -+ int ret; -+ VCHI_INSTANCE_T vchi_instance; -+ VCHI_CONNECTION_T *vchi_connection = NULL; -+ -+ pr_info("[%s]: start\n", __func__); -+ -+ /* Allocate memory for the state structure. -+ */ -+ sm_state = kzalloc(sizeof(struct SM_STATE_T), GFP_KERNEL); -+ if (sm_state == NULL) { -+ pr_err("[%s]: failed to allocate memory\n", __func__); -+ ret = -ENOMEM; -+ goto out; -+ } -+ -+ mutex_init(&sm_state->lock); -+ mutex_init(&sm_state->map_lock); -+ -+ /* Initialize and create a VCHI connection for the shared memory service -+ ** running on videocore. -+ */ -+ ret = vchi_initialise(&vchi_instance); -+ if (ret != 0) { -+ pr_err("[%s]: failed to initialise VCHI instance (ret=%d)\n", -+ __func__, ret); -+ -+ ret = -EIO; -+ goto err_free_mem; -+ } -+ -+ ret = vchi_connect(NULL, 0, vchi_instance); -+ if (ret != 0) { -+ pr_err("[%s]: failed to connect VCHI instance (ret=%d)\n", -+ __func__, ret); -+ -+ ret = -EIO; -+ goto err_free_mem; -+ } -+ -+ /* Initialize an instance of the shared memory service. */ -+ sm_state->sm_handle = -+ vc_vchi_sm_init(vchi_instance, &vchi_connection, 1); -+ if (sm_state->sm_handle == NULL) { -+ pr_err("[%s]: failed to initialize shared memory service\n", -+ __func__); -+ -+ ret = -EPERM; -+ goto err_free_mem; -+ } -+ -+ /* Create a debug fs directory entry (root). */ -+ sm_state->dir_root = debugfs_create_dir(VC_SM_DIR_ROOT_NAME, NULL); -+ if (!sm_state->dir_root) { -+ pr_err("[%s]: failed to create \'%s\' directory entry\n", -+ __func__, VC_SM_DIR_ROOT_NAME); -+ -+ ret = -EPERM; -+ goto err_stop_sm_service; -+ } -+ -+ sm_state->dir_state.show = &vc_sm_global_state_show; -+ sm_state->dir_state.dir_entry = debugfs_create_file(VC_SM_STATE, -+ S_IRUGO, sm_state->dir_root, &sm_state->dir_state, -+ &vc_sm_debug_fs_fops); -+ -+ sm_state->dir_stats.show = &vc_sm_global_statistics_show; -+ sm_state->dir_stats.dir_entry = debugfs_create_file(VC_SM_STATS, -+ S_IRUGO, sm_state->dir_root, &sm_state->dir_stats, -+ &vc_sm_debug_fs_fops); -+ -+ /* Create the proc entry children. */ -+ sm_state->dir_alloc = debugfs_create_dir(VC_SM_DIR_ALLOC_NAME, -+ sm_state->dir_root); -+ -+ /* Create a shared memory device. */ -+ ret = vc_sm_create_sharedmemory(); -+ if (ret != 0) { -+ pr_err("[%s]: failed to create shared memory device\n", -+ __func__); -+ goto err_remove_debugfs; -+ } -+ -+ INIT_LIST_HEAD(&sm_state->map_list); -+ INIT_LIST_HEAD(&sm_state->resource_list); -+ -+ sm_state->data_knl = vc_sm_create_priv_data(0); -+ if (sm_state->data_knl == NULL) { -+ pr_err("[%s]: failed to create kernel private data tracker\n", -+ __func__); -+ goto err_remove_shared_memory; -+ } -+ -+ /* Done! -+ */ -+ sm_inited = 1; -+ goto out; -+ -+err_remove_shared_memory: -+ vc_sm_remove_sharedmemory(); -+err_remove_debugfs: -+ debugfs_remove_recursive(sm_state->dir_root); -+err_stop_sm_service: -+ vc_vchi_sm_stop(&sm_state->sm_handle); -+err_free_mem: -+ kfree(sm_state); -+out: -+ pr_info("[%s]: end - returning %d\n", __func__, ret); -+} -+ -+/* Driver loading. */ -+static int __init vc_sm_init(void) -+{ -+ pr_info("vc-sm: Videocore shared memory driver\n"); -+ vchiq_add_connected_callback(vc_sm_connected_init); -+ return 0; -+} -+ -+/* Driver unloading. */ -+static void __exit vc_sm_exit(void) -+{ -+ pr_debug("[%s]: start\n", __func__); -+ if (sm_inited) { -+ /* Remove shared memory device. -+ */ -+ vc_sm_remove_sharedmemory(); -+ -+ /* Remove all proc entries. -+ */ -+ debugfs_remove_recursive(sm_state->dir_root); -+ -+ /* Stop the videocore shared memory service. -+ */ -+ vc_vchi_sm_stop(&sm_state->sm_handle); -+ -+ /* Free the memory for the state structure. -+ */ -+ mutex_destroy(&(sm_state->map_lock)); -+ kfree(sm_state); -+ } -+ -+ pr_debug("[%s]: end\n", __func__); -+} -+ -+#if defined(__KERNEL__) -+/* Allocate a shared memory handle and block. */ -+int vc_sm_alloc(VC_SM_ALLOC_T *alloc, int *handle) -+{ -+ struct vmcs_sm_ioctl_alloc ioparam = { 0 }; -+ int ret; -+ struct SM_RESOURCE_T *resource; -+ -+ /* Validate we can work with this device. -+ */ -+ if (sm_state == NULL || alloc == NULL || handle == NULL) { -+ pr_err("[%s]: invalid input\n", __func__); -+ return -EPERM; -+ } -+ -+ ioparam.size = alloc->base_unit; -+ ioparam.num = alloc->num_unit; -+ ioparam.cached = -+ alloc->type == VC_SM_ALLOC_CACHED ? VMCS_SM_CACHE_VC : 0; -+ -+ ret = vc_sm_ioctl_alloc(sm_state->data_knl, &ioparam); -+ -+ if (ret == 0) { -+ resource = -+ vmcs_sm_acquire_resource(sm_state->data_knl, -+ ioparam.handle); -+ if (resource) { -+ resource->pid = 0; -+ vmcs_sm_release_resource(resource, 0); -+ -+ /* Assign valid handle at this time. -+ */ -+ *handle = ioparam.handle; -+ } else { -+ ret = -ENOMEM; -+ } -+ } -+ -+ return ret; -+} -+EXPORT_SYMBOL_GPL(vc_sm_alloc); -+ -+/* Get an internal resource handle mapped from the external one. -+*/ -+int vc_sm_int_handle(int handle) -+{ -+ struct SM_RESOURCE_T *resource; -+ int ret = 0; -+ -+ /* Validate we can work with this device. -+ */ -+ if (sm_state == NULL || handle == 0) { -+ pr_err("[%s]: invalid input\n", __func__); -+ return 0; -+ } -+ -+ /* Locate resource from GUID. -+ */ -+ resource = vmcs_sm_acquire_resource(sm_state->data_knl, handle); -+ if (resource) { -+ ret = resource->res_handle; -+ vmcs_sm_release_resource(resource, 0); -+ } -+ -+ return ret; -+} -+EXPORT_SYMBOL_GPL(vc_sm_int_handle); -+ -+/* Free a previously allocated shared memory handle and block. -+*/ -+int vc_sm_free(int handle) -+{ -+ struct vmcs_sm_ioctl_free ioparam = { handle }; -+ -+ /* Validate we can work with this device. -+ */ -+ if (sm_state == NULL || handle == 0) { -+ pr_err("[%s]: invalid input\n", __func__); -+ return -EPERM; -+ } -+ -+ return vc_sm_ioctl_free(sm_state->data_knl, &ioparam); -+} -+EXPORT_SYMBOL_GPL(vc_sm_free); -+ -+/* Lock a memory handle for use by kernel. -+*/ -+int vc_sm_lock(int handle, VC_SM_LOCK_CACHE_MODE_T mode, -+ long unsigned int *data) -+{ -+ struct vmcs_sm_ioctl_lock_unlock ioparam; -+ int ret; -+ -+ /* Validate we can work with this device. -+ */ -+ if (sm_state == NULL || handle == 0 || data == NULL) { -+ pr_err("[%s]: invalid input\n", __func__); -+ return -EPERM; -+ } -+ -+ *data = 0; -+ -+ ioparam.handle = handle; -+ ret = vc_sm_ioctl_lock(sm_state->data_knl, -+ &ioparam, -+ 1, -+ ((mode == -+ VC_SM_LOCK_CACHED) ? VMCS_SM_CACHE_HOST : -+ VMCS_SM_CACHE_NONE), 0); -+ -+ *data = ioparam.addr; -+ return ret; -+} -+EXPORT_SYMBOL_GPL(vc_sm_lock); -+ -+/* Unlock a memory handle in use by kernel. -+*/ -+int vc_sm_unlock(int handle, int flush, int no_vc_unlock) -+{ -+ struct vmcs_sm_ioctl_lock_unlock ioparam; -+ -+ /* Validate we can work with this device. -+ */ -+ if (sm_state == NULL || handle == 0) { -+ pr_err("[%s]: invalid input\n", __func__); -+ return -EPERM; -+ } -+ -+ ioparam.handle = handle; -+ return vc_sm_ioctl_unlock(sm_state->data_knl, -+ &ioparam, flush, 0, no_vc_unlock); -+} -+EXPORT_SYMBOL_GPL(vc_sm_unlock); -+ -+/* Map a shared memory region for use by kernel. -+*/ -+int vc_sm_map(int handle, unsigned int sm_addr, VC_SM_LOCK_CACHE_MODE_T mode, -+ long unsigned int *data) -+{ -+ struct vmcs_sm_ioctl_lock_unlock ioparam; -+ int ret; -+ -+ /* Validate we can work with this device. -+ */ -+ if (sm_state == NULL || handle == 0 || data == NULL || sm_addr == 0) { -+ pr_err("[%s]: invalid input\n", __func__); -+ return -EPERM; -+ } -+ -+ *data = 0; -+ -+ ioparam.handle = handle; -+ ret = vc_sm_ioctl_lock(sm_state->data_knl, -+ &ioparam, -+ 1, -+ ((mode == -+ VC_SM_LOCK_CACHED) ? VMCS_SM_CACHE_HOST : -+ VMCS_SM_CACHE_NONE), sm_addr); -+ -+ *data = ioparam.addr; -+ return ret; -+} -+EXPORT_SYMBOL_GPL(vc_sm_map); -+#endif -+ -+late_initcall(vc_sm_init); -+module_exit(vc_sm_exit); -+ -+MODULE_AUTHOR("Broadcom"); -+MODULE_DESCRIPTION("VideoCore SharedMemory Driver"); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-4.1.13.orig/drivers/char/hw_random/bcm2708-rng.c linux-rpi/drivers/char/hw_random/bcm2708-rng.c ---- linux-4.1.13.orig/drivers/char/hw_random/bcm2708-rng.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/char/hw_random/bcm2708-rng.c 2015-11-29 09:42:36.707312101 +0100 -@@ -0,0 +1,118 @@ -+/** -+ * Copyright (c) 2010-2012 Broadcom. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#define RNG_CTRL (0x0) -+#define RNG_STATUS (0x4) -+#define RNG_DATA (0x8) -+#define RNG_FF_THRESHOLD (0xc) -+ -+/* enable rng */ -+#define RNG_RBGEN 0x1 -+/* double speed, less random mode */ -+#define RNG_RBG2X 0x2 -+ -+/* the initial numbers generated are "less random" so will be discarded */ -+#define RNG_WARMUP_COUNT 0x40000 -+ -+static int bcm2708_rng_data_read(struct hwrng *rng, u32 *buffer) -+{ -+ void __iomem *rng_base = (void __iomem *)rng->priv; -+ unsigned words; -+ /* wait for a random number to be in fifo */ -+ do { -+ words = __raw_readl(rng_base + RNG_STATUS)>>24; -+ } -+ while (words == 0); -+ /* read the random number */ -+ *buffer = __raw_readl(rng_base + RNG_DATA); -+ return 4; -+} -+ -+static struct hwrng bcm2708_rng_ops = { -+ .name = "bcm2708", -+ .data_read = bcm2708_rng_data_read, -+}; -+ -+static int __init bcm2708_rng_init(void) -+{ -+ void __iomem *rng_base; -+ int err; -+ -+ /* map peripheral */ -+ rng_base = ioremap(RNG_BASE, 0x10); -+ pr_info("bcm2708_rng_init=%p\n", rng_base); -+ if (!rng_base) { -+ pr_err("bcm2708_rng_init failed to ioremap\n"); -+ return -ENOMEM; -+ } -+ bcm2708_rng_ops.priv = (unsigned long)rng_base; -+ -+ /* set warm-up count & enable */ -+ __raw_writel(RNG_WARMUP_COUNT, rng_base + RNG_STATUS); -+ __raw_writel(RNG_RBGEN, rng_base + RNG_CTRL); -+ -+ /* register driver */ -+ err = hwrng_register(&bcm2708_rng_ops); -+ if (err) { -+ pr_err("bcm2708_rng_init hwrng_register()=%d\n", err); -+ iounmap(rng_base); -+ } -+ return err; -+} -+ -+static void __exit bcm2708_rng_exit(void) -+{ -+ void __iomem *rng_base = (void __iomem *)bcm2708_rng_ops.priv; -+ pr_info("bcm2708_rng_exit\n"); -+ /* disable rng hardware */ -+ __raw_writel(0, rng_base + RNG_CTRL); -+ /* unregister driver */ -+ hwrng_unregister(&bcm2708_rng_ops); -+ iounmap(rng_base); -+} -+ -+module_init(bcm2708_rng_init); -+module_exit(bcm2708_rng_exit); -+ -+MODULE_DESCRIPTION("BCM2708 H/W Random Number Generator (RNG) driver"); -+MODULE_LICENSE("GPL and additional rights"); -diff -Nur linux-4.1.13.orig/drivers/char/hw_random/Kconfig linux-rpi/drivers/char/hw_random/Kconfig ---- linux-4.1.13.orig/drivers/char/hw_random/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/char/hw_random/Kconfig 2015-11-29 09:42:36.707312101 +0100 -@@ -90,7 +90,7 @@ - - config HW_RANDOM_BCM2835 - tristate "Broadcom BCM2835 Random Number Generator support" -- depends on ARCH_BCM2835 -+ depends on ARCH_BCM2835 || ARCH_BCM2708 || ARCH_BCM2709 - default HW_RANDOM - ---help--- - This driver provides kernel-side support for the Random Number -@@ -333,6 +333,17 @@ - - If unsure, say Y. - -+config HW_RANDOM_BCM2708 -+ tristate "BCM2708 generic true random number generator support" -+ depends on HW_RANDOM && (ARCH_BCM2708 || ARCH_BCM2709) -+ ---help--- -+ This driver provides the kernel-side support for the BCM2708 hardware. -+ -+ To compile this driver as a module, choose M here: the -+ module will be called bcm2708-rng. -+ -+ If unsure, say N. -+ - config HW_RANDOM_MSM - tristate "Qualcomm SoCs Random Number Generator support" - depends on HW_RANDOM && ARCH_QCOM -diff -Nur linux-4.1.13.orig/drivers/char/hw_random/Makefile linux-rpi/drivers/char/hw_random/Makefile ---- linux-4.1.13.orig/drivers/char/hw_random/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/char/hw_random/Makefile 2015-11-29 09:42:36.707312101 +0100 -@@ -4,6 +4,7 @@ - - obj-$(CONFIG_HW_RANDOM) += rng-core.o - rng-core-y := core.o -+obj-$(CONFIG_HW_RANDOM_BCM2708) += bcm2708-rng.o - obj-$(CONFIG_HW_RANDOM_TIMERIOMEM) += timeriomem-rng.o - obj-$(CONFIG_HW_RANDOM_INTEL) += intel-rng.o - obj-$(CONFIG_HW_RANDOM_AMD) += amd-rng.o -diff -Nur linux-4.1.13.orig/drivers/char/Kconfig linux-rpi/drivers/char/Kconfig ---- linux-4.1.13.orig/drivers/char/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/char/Kconfig 2015-11-29 09:42:36.687313430 +0100 -@@ -590,6 +590,8 @@ - - source "drivers/s390/char/Kconfig" - -+source "drivers/char/broadcom/Kconfig" -+ - config MSM_SMD_PKT - bool "Enable device interface for some SMD packet ports" - default n -diff -Nur linux-4.1.13.orig/drivers/char/Makefile linux-rpi/drivers/char/Makefile ---- linux-4.1.13.orig/drivers/char/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/char/Makefile 2015-11-29 09:42:36.687313430 +0100 -@@ -62,3 +62,4 @@ - - obj-$(CONFIG_TILE_SROM) += tile-srom.o - obj-$(CONFIG_XILLYBUS) += xillybus/ -+obj-$(CONFIG_BRCM_CHAR_DRIVERS) += broadcom/ -diff -Nur linux-4.1.13.orig/drivers/clk/clk-hifiberry-dacpro.c linux-rpi/drivers/clk/clk-hifiberry-dacpro.c ---- linux-4.1.13.orig/drivers/clk/clk-hifiberry-dacpro.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/clk/clk-hifiberry-dacpro.c 2015-11-29 09:42:36.751309177 +0100 -@@ -0,0 +1,160 @@ -+/* -+ * Clock Driver for HiFiBerry DAC Pro -+ * -+ * Author: Stuart MacLean -+ * Copyright 2015 -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* Clock rate of CLK44EN attached to GPIO6 pin */ -+#define CLK_44EN_RATE 22579200UL -+/* Clock rate of CLK48EN attached to GPIO3 pin */ -+#define CLK_48EN_RATE 24576000UL -+ -+/** -+ * struct hifiberry_dacpro_clk - Common struct to the HiFiBerry DAC Pro -+ * @hw: clk_hw for the common clk framework -+ * @mode: 0 => CLK44EN, 1 => CLK48EN -+ */ -+struct clk_hifiberry_hw { -+ struct clk_hw hw; -+ uint8_t mode; -+}; -+ -+#define to_hifiberry_clk(_hw) container_of(_hw, struct clk_hifiberry_hw, hw) -+ -+static const struct of_device_id clk_hifiberry_dacpro_dt_ids[] = { -+ { .compatible = "hifiberry,dacpro-clk",}, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, clk_hifiberry_dacpro_dt_ids); -+ -+static unsigned long clk_hifiberry_dacpro_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ return (to_hifiberry_clk(hw)->mode == 0) ? CLK_44EN_RATE : -+ CLK_48EN_RATE; -+} -+ -+static long clk_hifiberry_dacpro_round_rate(struct clk_hw *hw, -+ unsigned long rate, unsigned long *parent_rate) -+{ -+ long actual_rate; -+ -+ if (rate <= CLK_44EN_RATE) { -+ actual_rate = (long)CLK_44EN_RATE; -+ } else if (rate >= CLK_48EN_RATE) { -+ actual_rate = (long)CLK_48EN_RATE; -+ } else { -+ long diff44Rate = (long)(rate - CLK_44EN_RATE); -+ long diff48Rate = (long)(CLK_48EN_RATE - rate); -+ -+ if (diff44Rate < diff48Rate) -+ actual_rate = (long)CLK_44EN_RATE; -+ else -+ actual_rate = (long)CLK_48EN_RATE; -+ } -+ return actual_rate; -+} -+ -+ -+static int clk_hifiberry_dacpro_set_rate(struct clk_hw *hw, -+ unsigned long rate, unsigned long parent_rate) -+{ -+ unsigned long actual_rate; -+ struct clk_hifiberry_hw *clk = to_hifiberry_clk(hw); -+ -+ actual_rate = (unsigned long)clk_hifiberry_dacpro_round_rate(hw, rate, -+ &parent_rate); -+ clk->mode = (actual_rate == CLK_44EN_RATE) ? 0 : 1; -+ return 0; -+} -+ -+ -+const struct clk_ops clk_hifiberry_dacpro_rate_ops = { -+ .recalc_rate = clk_hifiberry_dacpro_recalc_rate, -+ .round_rate = clk_hifiberry_dacpro_round_rate, -+ .set_rate = clk_hifiberry_dacpro_set_rate, -+}; -+ -+static int clk_hifiberry_dacpro_probe(struct platform_device *pdev) -+{ -+ int ret; -+ struct clk_hifiberry_hw *proclk; -+ struct clk *clk; -+ struct device *dev; -+ struct clk_init_data init; -+ -+ dev = &pdev->dev; -+ -+ proclk = kzalloc(sizeof(struct clk_hifiberry_hw), GFP_KERNEL); -+ if (!proclk) -+ return -ENOMEM; -+ -+ init.name = "clk-hifiberry-dacpro"; -+ init.ops = &clk_hifiberry_dacpro_rate_ops; -+ init.flags = CLK_IS_ROOT | CLK_IS_BASIC; -+ init.parent_names = NULL; -+ init.num_parents = 0; -+ -+ proclk->mode = 0; -+ proclk->hw.init = &init; -+ -+ clk = devm_clk_register(dev, &proclk->hw); -+ if (!IS_ERR(clk)) { -+ ret = of_clk_add_provider(dev->of_node, of_clk_src_simple_get, -+ clk); -+ } else { -+ dev_err(dev, "Fail to register clock driver\n"); -+ kfree(proclk); -+ ret = PTR_ERR(clk); -+ } -+ return ret; -+} -+ -+static int clk_hifiberry_dacpro_remove(struct platform_device *pdev) -+{ -+ of_clk_del_provider(pdev->dev.of_node); -+ return 0; -+} -+ -+static struct platform_driver clk_hifiberry_dacpro_driver = { -+ .probe = clk_hifiberry_dacpro_probe, -+ .remove = clk_hifiberry_dacpro_remove, -+ .driver = { -+ .name = "clk-hifiberry-dacpro", -+ .of_match_table = clk_hifiberry_dacpro_dt_ids, -+ }, -+}; -+ -+static int __init clk_hifiberry_dacpro_init(void) -+{ -+ return platform_driver_register(&clk_hifiberry_dacpro_driver); -+} -+core_initcall(clk_hifiberry_dacpro_init); -+ -+static void __exit clk_hifiberry_dacpro_exit(void) -+{ -+ platform_driver_unregister(&clk_hifiberry_dacpro_driver); -+} -+module_exit(clk_hifiberry_dacpro_exit); -+ -+MODULE_DESCRIPTION("HiFiBerry DAC Pro clock driver"); -+MODULE_LICENSE("GPL v2"); -+MODULE_ALIAS("platform:clk-hifiberry-dacpro"); -diff -Nur linux-4.1.13.orig/drivers/clk/Makefile linux-rpi/drivers/clk/Makefile ---- linux-4.1.13.orig/drivers/clk/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/clk/Makefile 2015-11-29 09:42:36.747309443 +0100 -@@ -24,6 +24,7 @@ - obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o - obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o - obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o -+obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) += clk-hifiberry-dacpro.o - obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o - obj-$(CONFIG_COMMON_CLK_MAX_GEN) += clk-max-gen.o - obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o -diff -Nur linux-4.1.13.orig/drivers/clocksource/arm_arch_timer.c linux-rpi/drivers/clocksource/arm_arch_timer.c ---- linux-4.1.13.orig/drivers/clocksource/arm_arch_timer.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/clocksource/arm_arch_timer.c 2015-11-29 09:42:36.779307317 +0100 -@@ -882,3 +882,39 @@ - acpi_table_parse(ACPI_SIG_GTDT, arch_timer_acpi_init); - } - #endif -+ -+int __init dc4_arch_timer_init(void) -+{ -+ if (arch_timers_present & ARCH_CP15_TIMER) { -+ pr_warn("arch_timer: multiple nodes in dt, skipping\n"); -+ return -1; -+ } -+ -+ arch_timers_present |= ARCH_CP15_TIMER; -+ -+ /* Try to determine the frequency from the device tree or CNTFRQ */ -+ arch_timer_rate = 19200000; -+ -+ arch_timer_ppi[PHYS_SECURE_PPI] = IRQ_ARM_LOCAL_CNTPSIRQ; -+ arch_timer_ppi[PHYS_NONSECURE_PPI] = IRQ_ARM_LOCAL_CNTPNSIRQ; -+ arch_timer_ppi[VIRT_PPI] = IRQ_ARM_LOCAL_CNTVIRQ; -+ arch_timer_ppi[HYP_PPI] = IRQ_ARM_LOCAL_CNTHPIRQ; -+ -+ /* -+ * If HYP mode is available, we know that the physical timer -+ * has been configured to be accessible from PL1. Use it, so -+ * that a guest can use the virtual timer instead. -+ * -+ * If no interrupt provided for virtual timer, we'll have to -+ * stick to the physical timer. It'd better be accessible... -+ */ -+ if (is_hyp_mode_available() || !arch_timer_ppi[VIRT_PPI]) { -+ arch_timer_use_virtual = false; -+ } -+ -+ arch_timer_c3stop = 0; -+ -+ arch_timer_register(); -+ arch_timer_common_init(); -+ return 0; -+} -diff -Nur linux-4.1.13.orig/drivers/cpufreq/bcm2835-cpufreq.c linux-rpi/drivers/cpufreq/bcm2835-cpufreq.c ---- linux-4.1.13.orig/drivers/cpufreq/bcm2835-cpufreq.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/cpufreq/bcm2835-cpufreq.c 2015-11-29 09:42:36.783307051 +0100 -@@ -0,0 +1,213 @@ -+/***************************************************************************** -+* Copyright 2011 Broadcom Corporation. All rights reserved. -+* -+* Unless you and Broadcom execute a separate written software license -+* agreement governing use of this software, this software is licensed to you -+* under the terms of the GNU General Public License version 2, available at -+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -+* -+* Notwithstanding the above, under no circumstances may you combine this -+* software in any way with any other Broadcom software provided under a -+* license other than the GPL, without Broadcom's express prior written -+* consent. -+*****************************************************************************/ -+ -+/***************************************************************************** -+* FILENAME: bcm2835-cpufreq.h -+* DESCRIPTION: This driver dynamically manages the CPU Frequency of the ARM -+* processor. Messages are sent to Videocore either setting or requesting the -+* frequency of the ARM in order to match an appropiate frequency to the current -+* usage of the processor. The policy which selects the frequency to use is -+* defined in the kernel .config file, but can be changed during runtime. -+*****************************************************************************/ -+ -+/* ---------- INCLUDES ---------- */ -+#include -+#include -+#include -+#include -+#include -+ -+/* ---------- DEFINES ---------- */ -+/*#define CPUFREQ_DEBUG_ENABLE*/ /* enable debugging */ -+#define MODULE_NAME "bcm2835-cpufreq" -+ -+#define VCMSG_ID_ARM_CLOCK 0x000000003 /* Clock/Voltage ID's */ -+ -+/* debug printk macros */ -+#ifdef CPUFREQ_DEBUG_ENABLE -+#define print_debug(fmt,...) pr_debug("%s:%s:%d: "fmt, MODULE_NAME, __func__, __LINE__, ##__VA_ARGS__) -+#else -+#define print_debug(fmt,...) -+#endif -+#define print_err(fmt,...) pr_err("%s:%s:%d: "fmt, MODULE_NAME, __func__,__LINE__, ##__VA_ARGS__) -+#define print_info(fmt,...) pr_info("%s: "fmt, MODULE_NAME, ##__VA_ARGS__) -+ -+/* ---------- GLOBALS ---------- */ -+static struct cpufreq_driver bcm2835_cpufreq_driver; /* the cpufreq driver global */ -+ -+static struct cpufreq_frequency_table bcm2835_freq_table[] = { -+ {0, 0, 0}, -+ {0, 0, 0}, -+ {0, 0, CPUFREQ_TABLE_END}, -+}; -+ -+/* -+ =============================================== -+ clk_rate either gets or sets the clock rates. -+ =============================================== -+*/ -+ -+static int bcm2835_cpufreq_clock_property(u32 tag, u32 id, u32 *val) -+{ -+ struct rpi_firmware *fw = rpi_firmware_get(NULL); -+ struct { -+ u32 id; -+ u32 val; -+ } packet; -+ int ret; -+ -+ packet.id = id; -+ packet.val = *val; -+ ret = rpi_firmware_property(fw, tag, &packet, sizeof(packet)); -+ if (ret) -+ return ret; -+ -+ *val = packet.val; -+ -+ return 0; -+} -+ -+static uint32_t bcm2835_cpufreq_set_clock(int cur_rate, int arm_rate) -+{ -+ u32 rate = arm_rate * 1000; -+ int ret; -+ -+ ret = bcm2835_cpufreq_clock_property(RPI_FIRMWARE_SET_CLOCK_RATE, VCMSG_ID_ARM_CLOCK, &rate); -+ if (ret) { -+ print_err("Failed to set clock: %d (%d)\n", arm_rate, ret); -+ return 0; -+ } -+ -+ rate /= 1000; -+ print_debug("Setting new frequency = %d -> %d (actual %d)\n", cur_rate, arm_rate, rate); -+ -+ return rate; -+} -+ -+static uint32_t bcm2835_cpufreq_get_clock(int tag) -+{ -+ u32 rate; -+ int ret; -+ -+ ret = bcm2835_cpufreq_clock_property(tag, VCMSG_ID_ARM_CLOCK, &rate); -+ if (ret) { -+ print_err("Failed to get clock (%d)\n", ret); -+ return 0; -+ } -+ -+ rate /= 1000; -+ print_debug("%s frequency = %u\n", -+ tag == RPI_FIRMWARE_GET_CLOCK_RATE ? "Current": -+ tag == RPI_FIRMWARE_GET_MIN_CLOCK_RATE ? "Min": -+ tag == RPI_FIRMWARE_GET_MAX_CLOCK_RATE ? "Max": -+ "Unexpected", rate); -+ -+ return rate; -+} -+ -+/* -+ ==================================================== -+ Module Initialisation registers the cpufreq driver -+ ==================================================== -+*/ -+static int __init bcm2835_cpufreq_module_init(void) -+{ -+ print_debug("IN\n"); -+ return cpufreq_register_driver(&bcm2835_cpufreq_driver); -+} -+ -+/* -+ ============= -+ Module exit -+ ============= -+*/ -+static void __exit bcm2835_cpufreq_module_exit(void) -+{ -+ print_debug("IN\n"); -+ cpufreq_unregister_driver(&bcm2835_cpufreq_driver); -+ return; -+} -+ -+/* -+ ============================================================== -+ Initialisation function sets up the CPU policy for first use -+ ============================================================== -+*/ -+static int bcm2835_cpufreq_driver_init(struct cpufreq_policy *policy) -+{ -+ /* measured value of how long it takes to change frequency */ -+ const unsigned int transition_latency = 355000; /* ns */ -+ -+ if (!rpi_firmware_get(NULL)) { -+ print_err("Firmware is not available\n"); -+ return -ENODEV; -+ } -+ -+ /* now find out what the maximum and minimum frequencies are */ -+ bcm2835_freq_table[0].frequency = bcm2835_cpufreq_get_clock(RPI_FIRMWARE_GET_MIN_CLOCK_RATE); -+ bcm2835_freq_table[1].frequency = bcm2835_cpufreq_get_clock(RPI_FIRMWARE_GET_MAX_CLOCK_RATE); -+ -+ print_info("min=%d max=%d\n", bcm2835_freq_table[0].frequency, bcm2835_freq_table[1].frequency); -+ return cpufreq_generic_init(policy, bcm2835_freq_table, transition_latency); -+} -+ -+/* -+ ===================================================================== -+ Target index function chooses the requested frequency from the table -+ ===================================================================== -+*/ -+ -+static int bcm2835_cpufreq_driver_target_index(struct cpufreq_policy *policy, unsigned int state) -+{ -+ unsigned int target_freq = bcm2835_freq_table[state].frequency; -+ unsigned int cur = bcm2835_cpufreq_set_clock(policy->cur, target_freq); -+ -+ if (!cur) -+ { -+ print_err("Error occurred setting a new frequency (%d)\n", target_freq); -+ return -EINVAL; -+ } -+ print_debug("%s: %i: freq %d->%d\n", policy->governor->name, state, policy->cur, cur); -+ return 0; -+} -+ -+/* -+ ====================================================== -+ Get function returns the current frequency from table -+ ====================================================== -+*/ -+ -+static unsigned int bcm2835_cpufreq_driver_get(unsigned int cpu) -+{ -+ unsigned int actual_rate = bcm2835_cpufreq_get_clock(RPI_FIRMWARE_GET_CLOCK_RATE); -+ print_debug("cpu%d: freq=%d\n", cpu, actual_rate); -+ return actual_rate <= bcm2835_freq_table[0].frequency ? bcm2835_freq_table[0].frequency : bcm2835_freq_table[1].frequency; -+} -+ -+/* the CPUFreq driver */ -+static struct cpufreq_driver bcm2835_cpufreq_driver = { -+ .name = "BCM2835 CPUFreq", -+ .init = bcm2835_cpufreq_driver_init, -+ .verify = cpufreq_generic_frequency_table_verify, -+ .target_index = bcm2835_cpufreq_driver_target_index, -+ .get = bcm2835_cpufreq_driver_get, -+ .attr = cpufreq_generic_attr, -+}; -+ -+MODULE_AUTHOR("Dorian Peake and Dom Cobley"); -+MODULE_DESCRIPTION("CPU frequency driver for BCM2835 chip"); -+MODULE_LICENSE("GPL"); -+ -+module_init(bcm2835_cpufreq_module_init); -+module_exit(bcm2835_cpufreq_module_exit); -diff -Nur linux-4.1.13.orig/drivers/cpufreq/Kconfig.arm linux-rpi/drivers/cpufreq/Kconfig.arm ---- linux-4.1.13.orig/drivers/cpufreq/Kconfig.arm 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/cpufreq/Kconfig.arm 2015-11-29 09:42:36.783307051 +0100 -@@ -258,6 +258,15 @@ - help - This adds the CPUFreq driver support for SPEAr SOCs. - -+config ARM_BCM2835_CPUFREQ -+ depends on RASPBERRYPI_FIRMWARE -+ bool "BCM2835 Driver" -+ default y -+ help -+ This adds the CPUFreq driver for BCM2835 -+ -+ If in doubt, say N. -+ - config ARM_TEGRA_CPUFREQ - bool "TEGRA CPUFreq support" - depends on ARCH_TEGRA -diff -Nur linux-4.1.13.orig/drivers/cpufreq/Makefile linux-rpi/drivers/cpufreq/Makefile ---- linux-4.1.13.orig/drivers/cpufreq/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/cpufreq/Makefile 2015-11-29 09:42:36.783307051 +0100 -@@ -77,6 +77,7 @@ - obj-$(CONFIG_ARM_SA1100_CPUFREQ) += sa1100-cpufreq.o - obj-$(CONFIG_ARM_SA1110_CPUFREQ) += sa1110-cpufreq.o - obj-$(CONFIG_ARM_SPEAR_CPUFREQ) += spear-cpufreq.o -+obj-$(CONFIG_ARM_BCM2835_CPUFREQ) += bcm2835-cpufreq.o - obj-$(CONFIG_ARM_TEGRA_CPUFREQ) += tegra-cpufreq.o - obj-$(CONFIG_ARM_VEXPRESS_SPC_CPUFREQ) += vexpress-spc-cpufreq.o - -diff -Nur linux-4.1.13.orig/drivers/dma/bcm2708-dmaengine.c linux-rpi/drivers/dma/bcm2708-dmaengine.c ---- linux-4.1.13.orig/drivers/dma/bcm2708-dmaengine.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/dma/bcm2708-dmaengine.c 2015-11-29 09:42:36.815304925 +0100 -@@ -0,0 +1,1314 @@ -+/* -+ * BCM2835 DMA engine support -+ * -+ * This driver supports cyclic and scatter/gather DMA transfers. -+ * -+ * Author: Florian Meier -+ * Gellert Weisz -+ * Copyright 2013-2014 -+ * -+ * Based on -+ * OMAP DMAengine support by Russell King -+ * -+ * BCM2708 DMA Driver -+ * Copyright (C) 2010 Broadcom -+ * -+ * Raspberry Pi PCM I2S ALSA Driver -+ * Copyright (c) by Phil Poole 2013 -+ * -+ * MARVELL MMP Peripheral DMA Driver -+ * Copyright 2012 Marvell International Ltd. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "virt-dma.h" -+ -+static unsigned dma_debug; -+ -+/* -+ * Legacy DMA API -+ */ -+ -+#ifdef CONFIG_DMA_BCM2708_LEGACY -+ -+#define CACHE_LINE_MASK 31 -+#define DEFAULT_DMACHAN_BITMAP 0x10 /* channel 4 only */ -+ -+/* valid only for channels 0 - 14, 15 has its own base address */ -+#define BCM2708_DMA_CHAN(n) ((n) << 8) /* base address */ -+#define BCM2708_DMA_CHANIO(dma_base, n) \ -+ ((void __iomem *)((char *)(dma_base) + BCM2708_DMA_CHAN(n))) -+ -+struct vc_dmaman { -+ void __iomem *dma_base; -+ u32 chan_available; /* bitmap of available channels */ -+ u32 has_feature[BCM_DMA_FEATURE_COUNT]; /* bitmap of feature presence */ -+ struct mutex lock; -+}; -+ -+static struct device *dmaman_dev; /* we assume there's only one! */ -+static struct vc_dmaman *g_dmaman; /* DMA manager */ -+static int dmachans = -1; /* module parameter */ -+ -+/* DMA Auxiliary Functions */ -+ -+/* A DMA buffer on an arbitrary boundary may separate a cache line into a -+ section inside the DMA buffer and another section outside it. -+ Even if we flush DMA buffers from the cache there is always the chance that -+ during a DMA someone will access the part of a cache line that is outside -+ the DMA buffer - which will then bring in unwelcome data. -+ Without being able to dictate our own buffer pools we must insist that -+ DMA buffers consist of a whole number of cache lines. -+*/ -+extern int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len) -+{ -+ int i; -+ -+ for (i = 0; i < sg_len; i++) { -+ if (sg_ptr[i].offset & CACHE_LINE_MASK || -+ sg_ptr[i].length & CACHE_LINE_MASK) -+ return 0; -+ } -+ -+ return 1; -+} -+EXPORT_SYMBOL_GPL(bcm_sg_suitable_for_dma); -+ -+extern void bcm_dma_start(void __iomem *dma_chan_base, -+ dma_addr_t control_block) -+{ -+ dsb(); /* ARM data synchronization (push) operation */ -+ -+ writel(control_block, dma_chan_base + BCM2708_DMA_ADDR); -+ writel(BCM2708_DMA_ACTIVE, dma_chan_base + BCM2708_DMA_CS); -+} -+EXPORT_SYMBOL_GPL(bcm_dma_start); -+ -+extern void bcm_dma_wait_idle(void __iomem *dma_chan_base) -+{ -+ dsb(); -+ -+ /* ugly busy wait only option for now */ -+ while (readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE) -+ cpu_relax(); -+} -+EXPORT_SYMBOL_GPL(bcm_dma_wait_idle); -+ -+extern bool bcm_dma_is_busy(void __iomem *dma_chan_base) -+{ -+ dsb(); -+ -+ return readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE; -+} -+EXPORT_SYMBOL_GPL(bcm_dma_is_busy); -+ -+/* Complete an ongoing DMA (assuming its results are to be ignored) -+ Does nothing if there is no DMA in progress. -+ This routine waits for the current AXI transfer to complete before -+ terminating the current DMA. If the current transfer is hung on a DREQ used -+ by an uncooperative peripheral the AXI transfer may never complete. In this -+ case the routine times out and return a non-zero error code. -+ Use of this routine doesn't guarantee that the ongoing or aborted DMA -+ does not produce an interrupt. -+*/ -+extern int bcm_dma_abort(void __iomem *dma_chan_base) -+{ -+ unsigned long int cs; -+ int rc = 0; -+ -+ cs = readl(dma_chan_base + BCM2708_DMA_CS); -+ -+ if (BCM2708_DMA_ACTIVE & cs) { -+ long int timeout = 10000; -+ -+ /* write 0 to the active bit - pause the DMA */ -+ writel(0, dma_chan_base + BCM2708_DMA_CS); -+ -+ /* wait for any current AXI transfer to complete */ -+ while (0 != (cs & BCM2708_DMA_ISPAUSED) && --timeout >= 0) -+ cs = readl(dma_chan_base + BCM2708_DMA_CS); -+ -+ if (0 != (cs & BCM2708_DMA_ISPAUSED)) { -+ /* we'll un-pause when we set of our next DMA */ -+ rc = -ETIMEDOUT; -+ -+ } else if (BCM2708_DMA_ACTIVE & cs) { -+ /* terminate the control block chain */ -+ writel(0, dma_chan_base + BCM2708_DMA_NEXTCB); -+ -+ /* abort the whole DMA */ -+ writel(BCM2708_DMA_ABORT | BCM2708_DMA_ACTIVE, -+ dma_chan_base + BCM2708_DMA_CS); -+ } -+ } -+ -+ return rc; -+} -+EXPORT_SYMBOL_GPL(bcm_dma_abort); -+ -+ /* DMA Manager Device Methods */ -+ -+static void vc_dmaman_init(struct vc_dmaman *dmaman, void __iomem *dma_base, -+ u32 chans_available) -+{ -+ dmaman->dma_base = dma_base; -+ dmaman->chan_available = chans_available; -+ dmaman->has_feature[BCM_DMA_FEATURE_FAST_ORD] = 0x0c; /* 2 & 3 */ -+ dmaman->has_feature[BCM_DMA_FEATURE_BULK_ORD] = 0x01; /* 0 */ -+ dmaman->has_feature[BCM_DMA_FEATURE_NORMAL_ORD] = 0xfe; /* 1 to 7 */ -+ dmaman->has_feature[BCM_DMA_FEATURE_LITE_ORD] = 0x7f00; /* 8 to 14 */ -+} -+ -+static int vc_dmaman_chan_alloc(struct vc_dmaman *dmaman, -+ unsigned required_feature_set) -+{ -+ u32 chans; -+ int chan = 0; -+ int feature; -+ -+ chans = dmaman->chan_available; -+ for (feature = 0; feature < BCM_DMA_FEATURE_COUNT; feature++) -+ /* select the subset of available channels with the desired -+ features */ -+ if (required_feature_set & (1 << feature)) -+ chans &= dmaman->has_feature[feature]; -+ -+ if (!chans) -+ return -ENOENT; -+ -+ /* return the ordinal of the first channel in the bitmap */ -+ while (chans != 0 && (chans & 1) == 0) { -+ chans >>= 1; -+ chan++; -+ } -+ /* claim the channel */ -+ dmaman->chan_available &= ~(1 << chan); -+ -+ return chan; -+} -+ -+static int vc_dmaman_chan_free(struct vc_dmaman *dmaman, int chan) -+{ -+ if (chan < 0) -+ return -EINVAL; -+ -+ if ((1 << chan) & dmaman->chan_available) -+ return -EIDRM; -+ -+ dmaman->chan_available |= (1 << chan); -+ -+ return 0; -+} -+ -+/* DMA Manager Monitor */ -+ -+extern int bcm_dma_chan_alloc(unsigned required_feature_set, -+ void __iomem **out_dma_base, int *out_dma_irq) -+{ -+ struct vc_dmaman *dmaman = g_dmaman; -+ struct platform_device *pdev = to_platform_device(dmaman_dev); -+ struct resource *r; -+ int chan; -+ -+ if (!dmaman_dev) -+ return -ENODEV; -+ -+ mutex_lock(&dmaman->lock); -+ chan = vc_dmaman_chan_alloc(dmaman, required_feature_set); -+ if (chan < 0) -+ goto out; -+ -+ r = platform_get_resource(pdev, IORESOURCE_IRQ, (unsigned int)chan); -+ if (!r) { -+ dev_err(dmaman_dev, "failed to get irq for DMA channel %d\n", -+ chan); -+ vc_dmaman_chan_free(dmaman, chan); -+ chan = -ENOENT; -+ goto out; -+ } -+ -+ *out_dma_base = BCM2708_DMA_CHANIO(dmaman->dma_base, chan); -+ *out_dma_irq = r->start; -+ dev_dbg(dmaman_dev, -+ "Legacy API allocated channel=%d, base=%p, irq=%i\n", -+ chan, *out_dma_base, *out_dma_irq); -+ -+out: -+ mutex_unlock(&dmaman->lock); -+ -+ return chan; -+} -+EXPORT_SYMBOL_GPL(bcm_dma_chan_alloc); -+ -+extern int bcm_dma_chan_free(int channel) -+{ -+ struct vc_dmaman *dmaman = g_dmaman; -+ int rc; -+ -+ if (!dmaman_dev) -+ return -ENODEV; -+ -+ mutex_lock(&dmaman->lock); -+ rc = vc_dmaman_chan_free(dmaman, channel); -+ mutex_unlock(&dmaman->lock); -+ -+ return rc; -+} -+EXPORT_SYMBOL_GPL(bcm_dma_chan_free); -+ -+static int bcm_dmaman_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct vc_dmaman *dmaman; -+ struct resource *r; -+ void __iomem *dma_base; -+ uint32_t val; -+ -+ if (!of_property_read_u32(dev->of_node, -+ "brcm,dma-channel-mask", &val)) -+ dmachans = val; -+ else if (dmachans == -1) -+ dmachans = DEFAULT_DMACHAN_BITMAP; -+ -+ dmaman = devm_kzalloc(dev, sizeof(*dmaman), GFP_KERNEL); -+ if (!dmaman) -+ return -ENOMEM; -+ -+ mutex_init(&dmaman->lock); -+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ dma_base = devm_ioremap_resource(dev, r); -+ if (IS_ERR(dma_base)) -+ return PTR_ERR(dma_base); -+ -+ vc_dmaman_init(dmaman, dma_base, dmachans); -+ g_dmaman = dmaman; -+ dmaman_dev = dev; -+ -+ dev_info(dev, "DMA legacy API manager at %p, dmachans=0x%x\n", -+ dma_base, dmachans); -+ -+ return 0; -+} -+ -+static int bcm_dmaman_remove(struct platform_device *pdev) -+{ -+ dmaman_dev = NULL; -+ -+ return 0; -+} -+ -+#else /* CONFIG_DMA_BCM2708_LEGACY */ -+ -+static int bcm_dmaman_remove(struct platform_device *pdev) -+{ -+ return 0; -+} -+ -+#endif /* CONFIG_DMA_BCM2708_LEGACY */ -+ -+/* -+ * DMA engine -+ */ -+ -+struct bcm2835_dmadev { -+ struct dma_device ddev; -+ spinlock_t lock; -+ void __iomem *base; -+ struct device_dma_parameters dma_parms; -+}; -+ -+struct bcm2835_dma_cb { -+ uint32_t info; -+ uint32_t src; -+ uint32_t dst; -+ uint32_t length; -+ uint32_t stride; -+ uint32_t next; -+ uint32_t pad[2]; -+}; -+ -+struct bcm2835_chan { -+ struct virt_dma_chan vc; -+ struct list_head node; -+ -+ struct dma_slave_config cfg; -+ bool cyclic; -+ -+ int ch; -+ struct bcm2835_desc *desc; -+ -+ void __iomem *chan_base; -+ int irq_number; -+ -+ unsigned int dreq; -+}; -+ -+struct bcm2835_desc { -+ struct virt_dma_desc vd; -+ enum dma_transfer_direction dir; -+ -+ unsigned int control_block_size; -+ struct bcm2835_dma_cb *control_block_base; -+ dma_addr_t control_block_base_phys; -+ -+ unsigned int frames; -+ size_t size; -+}; -+ -+#define BCM2835_DMA_CS 0x00 -+#define BCM2835_DMA_ADDR 0x04 -+#define BCM2835_DMA_SOURCE_AD 0x0c -+#define BCM2835_DMA_DEST_AD 0x10 -+#define BCM2835_DMA_NEXTCB 0x1C -+ -+/* DMA CS Control and Status bits */ -+#define BCM2835_DMA_ACTIVE BIT(0) -+#define BCM2835_DMA_INT BIT(2) -+#define BCM2835_DMA_ISPAUSED BIT(4) /* Pause requested or not active */ -+#define BCM2835_DMA_ISHELD BIT(5) /* Is held by DREQ flow control */ -+#define BCM2835_DMA_ERR BIT(8) -+#define BCM2835_DMA_ABORT BIT(30) /* Stop current CB, go to next, WO */ -+#define BCM2835_DMA_RESET BIT(31) /* WO, self clearing */ -+ -+#define BCM2835_DMA_INT_EN BIT(0) -+#define BCM2835_DMA_WAIT_RESP BIT(3) -+#define BCM2835_DMA_D_INC BIT(4) -+#define BCM2835_DMA_D_WIDTH BIT(5) -+#define BCM2835_DMA_D_DREQ BIT(6) -+#define BCM2835_DMA_S_INC BIT(8) -+#define BCM2835_DMA_S_WIDTH BIT(9) -+#define BCM2835_DMA_S_DREQ BIT(10) -+ -+#define BCM2835_DMA_PER_MAP(x) ((x) << 16) -+#define BCM2835_DMA_WAITS(x) (((x)&0x1f) << 21) -+ -+#define SDHCI_BCM_DMA_WAITS 0 /* delays slowing DMA transfers: 0-31 */ -+ -+#define BCM2835_DMA_DATA_TYPE_S8 1 -+#define BCM2835_DMA_DATA_TYPE_S16 2 -+#define BCM2835_DMA_DATA_TYPE_S32 4 -+#define BCM2835_DMA_DATA_TYPE_S128 16 -+ -+#define BCM2835_DMA_BULK_MASK BIT(0) -+#define BCM2835_DMA_FIQ_MASK (BIT(2) | BIT(3)) -+ -+ -+/* Valid only for channels 0 - 14, 15 has its own base address */ -+#define BCM2835_DMA_CHAN(n) ((n) << 8) /* Base address */ -+#define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n)) -+ -+#define MAX_LITE_TRANSFER 32768 -+#define MAX_NORMAL_TRANSFER 1073741824 -+ -+static inline struct bcm2835_dmadev *to_bcm2835_dma_dev(struct dma_device *d) -+{ -+ return container_of(d, struct bcm2835_dmadev, ddev); -+} -+ -+static inline struct bcm2835_chan *to_bcm2835_dma_chan(struct dma_chan *c) -+{ -+ return container_of(c, struct bcm2835_chan, vc.chan); -+} -+ -+static inline struct bcm2835_desc *to_bcm2835_dma_desc( -+ struct dma_async_tx_descriptor *t) -+{ -+ return container_of(t, struct bcm2835_desc, vd.tx); -+} -+ -+#if 0 -+static void dma_dumpregs(struct bcm2835_chan *c) -+{ -+ pr_debug("-------------DMA DUMPREGS-------------\n"); -+ pr_debug("CS= %u\n", -+ readl(c->chan_base + BCM2835_DMA_CS)); -+ pr_debug("ADDR= %u\n", -+ readl(c->chan_base + BCM2835_DMA_ADDR)); -+ pr_debug("SOURCE_ADDR= %u\n", -+ readl(c->chan_base + BCM2835_DMA_SOURCE_AD)); -+ pr_debug("DEST_AD= %u\n", -+ readl(c->chan_base + BCM2835_DMA_DEST_AD)); -+ pr_debug("NEXTCB= %u\n", -+ readl(c->chan_base + BCM2835_DMA_NEXTCB)); -+ pr_debug("--------------------------------------\n"); -+} -+#endif -+ -+static void bcm2835_dma_desc_free(struct virt_dma_desc *vd) -+{ -+ struct bcm2835_desc *desc = container_of(vd, struct bcm2835_desc, vd); -+ dma_free_coherent(desc->vd.tx.chan->device->dev, -+ desc->control_block_size, -+ desc->control_block_base, -+ desc->control_block_base_phys); -+ kfree(desc); -+} -+ -+static int bcm2835_dma_abort(void __iomem *chan_base) -+{ -+ unsigned long cs; -+ long int timeout = 10000; -+ -+ cs = readl(chan_base + BCM2835_DMA_CS); -+ if (!(cs & BCM2835_DMA_ACTIVE)) -+ return 0; -+ -+ /* Write 0 to the active bit - Pause the DMA */ -+ writel(0, chan_base + BCM2835_DMA_CS); -+ -+ /* Wait for any current AXI transfer to complete */ -+ while ((cs & BCM2835_DMA_ISPAUSED) && --timeout) { -+ cpu_relax(); -+ cs = readl(chan_base + BCM2835_DMA_CS); -+ } -+ -+ /* We'll un-pause when we set of our next DMA */ -+ if (!timeout) -+ return -ETIMEDOUT; -+ -+ if (!(cs & BCM2835_DMA_ACTIVE)) -+ return 0; -+ -+ /* Terminate the control block chain */ -+ writel(0, chan_base + BCM2835_DMA_NEXTCB); -+ -+ /* Abort the whole DMA */ -+ writel(BCM2835_DMA_ABORT | BCM2835_DMA_ACTIVE, -+ chan_base + BCM2835_DMA_CS); -+ -+ return 0; -+} -+ -+ -+static void bcm2835_dma_start_desc(struct bcm2835_chan *c) -+{ -+ struct virt_dma_desc *vd = vchan_next_desc(&c->vc); -+ struct bcm2835_desc *d; -+ -+ if (!vd) { -+ c->desc = NULL; -+ return; -+ } -+ -+ list_del(&vd->node); -+ -+ c->desc = d = to_bcm2835_dma_desc(&vd->tx); -+ -+ writel(d->control_block_base_phys, c->chan_base + BCM2835_DMA_ADDR); -+ writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS); -+ -+} -+ -+static irqreturn_t bcm2835_dma_callback(int irq, void *data) -+{ -+ struct bcm2835_chan *c = data; -+ struct bcm2835_desc *d; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&c->vc.lock, flags); -+ -+ /* Acknowledge interrupt */ -+ writel(BCM2835_DMA_INT, c->chan_base + BCM2835_DMA_CS); -+ -+ d = c->desc; -+ -+ if (d) { -+ if (c->cyclic) { -+ vchan_cyclic_callback(&d->vd); -+ -+ /* Keep the DMA engine running */ -+ writel(BCM2835_DMA_ACTIVE, -+ c->chan_base + BCM2835_DMA_CS); -+ -+ } else { -+ vchan_cookie_complete(&c->desc->vd); -+ bcm2835_dma_start_desc(c); -+ } -+ } -+ -+ spin_unlock_irqrestore(&c->vc.lock, flags); -+ -+ return IRQ_HANDLED; -+} -+ -+static int bcm2835_dma_alloc_chan_resources(struct dma_chan *chan) -+{ -+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); -+ int ret; -+ -+ dev_dbg(c->vc.chan.device->dev, -+ "Allocating DMA channel %d\n", c->ch); -+ -+ ret = request_irq(c->irq_number, -+ bcm2835_dma_callback, 0, "DMA IRQ", c); -+ -+ return ret; -+} -+ -+static void bcm2835_dma_free_chan_resources(struct dma_chan *chan) -+{ -+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); -+ -+ vchan_free_chan_resources(&c->vc); -+ free_irq(c->irq_number, c); -+ -+ dev_dbg(c->vc.chan.device->dev, "Freeing DMA channel %u\n", c->ch); -+} -+ -+static size_t bcm2835_dma_desc_size(struct bcm2835_desc *d) -+{ -+ return d->size; -+} -+ -+static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr) -+{ -+ unsigned int i; -+ size_t size; -+ -+ for (size = i = 0; i < d->frames; i++) { -+ struct bcm2835_dma_cb *control_block = -+ &d->control_block_base[i]; -+ size_t this_size = control_block->length; -+ dma_addr_t dma; -+ -+ if (d->dir == DMA_DEV_TO_MEM) -+ dma = control_block->dst; -+ else -+ dma = control_block->src; -+ -+ if (size) -+ size += this_size; -+ else if (addr >= dma && addr < dma + this_size) -+ size += dma + this_size - addr; -+ } -+ -+ return size; -+} -+ -+static enum dma_status bcm2835_dma_tx_status(struct dma_chan *chan, -+ dma_cookie_t cookie, struct dma_tx_state *txstate) -+{ -+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); -+ struct bcm2835_desc *d; -+ struct virt_dma_desc *vd; -+ enum dma_status ret; -+ unsigned long flags; -+ dma_addr_t pos; -+ -+ ret = dma_cookie_status(chan, cookie, txstate); -+ if (ret == DMA_COMPLETE || !txstate) -+ return ret; -+ -+ spin_lock_irqsave(&c->vc.lock, flags); -+ vd = vchan_find_desc(&c->vc, cookie); -+ if (vd) { -+ txstate->residue = -+ bcm2835_dma_desc_size(to_bcm2835_dma_desc(&vd->tx)); -+ } else if (c->desc && c->desc->vd.tx.cookie == cookie) { -+ d = c->desc; -+ -+ if (d->dir == DMA_MEM_TO_DEV) -+ pos = readl(c->chan_base + BCM2835_DMA_SOURCE_AD); -+ else if (d->dir == DMA_DEV_TO_MEM) -+ pos = readl(c->chan_base + BCM2835_DMA_DEST_AD); -+ else -+ pos = 0; -+ -+ txstate->residue = bcm2835_dma_desc_size_pos(d, pos); -+ } else { -+ txstate->residue = 0; -+ } -+ -+ spin_unlock_irqrestore(&c->vc.lock, flags); -+ -+ return ret; -+} -+ -+static void bcm2835_dma_issue_pending(struct dma_chan *chan) -+{ -+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); -+ unsigned long flags; -+ -+ spin_lock_irqsave(&c->vc.lock, flags); -+ if (vchan_issue_pending(&c->vc) && !c->desc) -+ bcm2835_dma_start_desc(c); -+ -+ spin_unlock_irqrestore(&c->vc.lock, flags); -+} -+ -+static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic( -+ struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, -+ size_t period_len, enum dma_transfer_direction direction, -+ unsigned long flags) -+{ -+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); -+ enum dma_slave_buswidth dev_width; -+ struct bcm2835_desc *d; -+ dma_addr_t dev_addr; -+ unsigned int es, sync_type; -+ unsigned int frame, max_size; -+ -+ /* Grab configuration */ -+ if (!is_slave_direction(direction)) { -+ dev_err(chan->device->dev, "%s: bad direction?\n", __func__); -+ return NULL; -+ } -+ -+ if (direction == DMA_DEV_TO_MEM) { -+ dev_addr = c->cfg.src_addr; -+ dev_width = c->cfg.src_addr_width; -+ sync_type = BCM2835_DMA_S_DREQ; -+ } else { -+ dev_addr = c->cfg.dst_addr; -+ dev_width = c->cfg.dst_addr_width; -+ sync_type = BCM2835_DMA_D_DREQ; -+ } -+ -+ /* Bus width translates to the element size (ES) */ -+ switch (dev_width) { -+ case DMA_SLAVE_BUSWIDTH_4_BYTES: -+ es = BCM2835_DMA_DATA_TYPE_S32; -+ break; -+ default: -+ return NULL; -+ } -+ -+ /* Now allocate and setup the descriptor. */ -+ d = kzalloc(sizeof(*d), GFP_NOWAIT); -+ if (!d) -+ return NULL; -+ -+ d->dir = direction; -+ -+ if (c->ch >= 8) /* we have a LITE channel */ -+ max_size = MAX_LITE_TRANSFER; -+ else -+ max_size = MAX_NORMAL_TRANSFER; -+ period_len = min(period_len, max_size); -+ -+ d->frames = (buf_len-1) / period_len + 1; -+ -+ /* Allocate memory for control blocks */ -+ d->control_block_size = d->frames * sizeof(struct bcm2835_dma_cb); -+ d->control_block_base = dma_zalloc_coherent(chan->device->dev, -+ d->control_block_size, &d->control_block_base_phys, -+ GFP_NOWAIT); -+ -+ if (!d->control_block_base) { -+ kfree(d); -+ return NULL; -+ } -+ -+ /* -+ * Iterate over all frames, create a control block -+ * for each frame and link them together. -+ */ -+ for (frame = 0; frame < d->frames; frame++) { -+ struct bcm2835_dma_cb *control_block = -+ &d->control_block_base[frame]; -+ -+ /* Setup adresses */ -+ if (d->dir == DMA_DEV_TO_MEM) { -+ control_block->info = BCM2835_DMA_D_INC; -+ control_block->src = dev_addr; -+ control_block->dst = buf_addr + frame * period_len; -+ } else { -+ control_block->info = BCM2835_DMA_S_INC; -+ control_block->src = buf_addr + frame * period_len; -+ control_block->dst = dev_addr; -+ } -+ -+ /* Enable interrupt */ -+ control_block->info |= BCM2835_DMA_INT_EN; -+ -+ /* Setup synchronization */ -+ if (sync_type != 0) -+ control_block->info |= sync_type; -+ -+ /* Setup DREQ channel */ -+ if (c->cfg.slave_id != 0) -+ control_block->info |= -+ BCM2835_DMA_PER_MAP(c->cfg.slave_id); -+ -+ /* Length of a frame */ -+ if (frame != d->frames-1) -+ control_block->length = period_len; -+ else -+ control_block->length = buf_len - (d->frames - 1) * period_len; -+ -+ d->size += control_block->length; -+ -+ /* -+ * Next block is the next frame. -+ * This function is called on cyclic DMA transfers. -+ * Therefore, wrap around at number of frames. -+ */ -+ control_block->next = d->control_block_base_phys + -+ sizeof(struct bcm2835_dma_cb) -+ * ((frame + 1) % d->frames); -+ } -+ -+ c->cyclic = true; -+ -+ return vchan_tx_prep(&c->vc, &d->vd, flags); -+} -+ -+ -+static struct dma_async_tx_descriptor *bcm2835_dma_prep_slave_sg( -+ struct dma_chan *chan, struct scatterlist *sgl, -+ unsigned int sg_len, enum dma_transfer_direction direction, -+ unsigned long flags, void *context) -+{ -+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); -+ enum dma_slave_buswidth dev_width; -+ struct bcm2835_desc *d; -+ dma_addr_t dev_addr; -+ struct scatterlist *sgent; -+ unsigned int es, sync_type; -+ unsigned int i, j, splitct, max_size; -+ -+ if (!is_slave_direction(direction)) { -+ dev_err(chan->device->dev, "%s: bad direction?\n", __func__); -+ return NULL; -+ } -+ -+ if (direction == DMA_DEV_TO_MEM) { -+ dev_addr = c->cfg.src_addr; -+ dev_width = c->cfg.src_addr_width; -+ sync_type = BCM2835_DMA_S_DREQ; -+ } else { -+ dev_addr = c->cfg.dst_addr; -+ dev_width = c->cfg.dst_addr_width; -+ sync_type = BCM2835_DMA_D_DREQ; -+ } -+ -+ /* Bus width translates to the element size (ES) */ -+ switch (dev_width) { -+ case DMA_SLAVE_BUSWIDTH_4_BYTES: -+ es = BCM2835_DMA_DATA_TYPE_S32; -+ break; -+ default: -+ return NULL; -+ } -+ -+ /* Now allocate and setup the descriptor. */ -+ d = kzalloc(sizeof(*d), GFP_NOWAIT); -+ if (!d) -+ return NULL; -+ -+ d->dir = direction; -+ -+ if (c->ch >= 8) /* we have a LITE channel */ -+ max_size = MAX_LITE_TRANSFER; -+ else -+ max_size = MAX_NORMAL_TRANSFER; -+ -+ /* We store the length of the SG list in d->frames -+ taking care to account for splitting up transfers -+ too large for a LITE channel */ -+ -+ d->frames = 0; -+ for_each_sg(sgl, sgent, sg_len, i) { -+ uint32_t len = sg_dma_len(sgent); -+ d->frames += 1 + len / max_size; -+ } -+ -+ /* Allocate memory for control blocks */ -+ d->control_block_size = d->frames * sizeof(struct bcm2835_dma_cb); -+ d->control_block_base = dma_zalloc_coherent(chan->device->dev, -+ d->control_block_size, &d->control_block_base_phys, -+ GFP_NOWAIT); -+ -+ if (!d->control_block_base) { -+ kfree(d); -+ return NULL; -+ } -+ -+ /* -+ * Iterate over all SG entries, create a control block -+ * for each frame and link them together. -+ */ -+ -+ /* we count the number of times an SG entry had to be splitct -+ as a result of using a LITE channel */ -+ splitct = 0; -+ -+ for_each_sg(sgl, sgent, sg_len, i) { -+ dma_addr_t addr = sg_dma_address(sgent); -+ uint32_t len = sg_dma_len(sgent); -+ -+ for (j = 0; j < len; j += max_size) { -+ u32 waits; -+ struct bcm2835_dma_cb *control_block = -+ &d->control_block_base[i+splitct]; -+ -+ /* Setup adresses */ -+ if (d->dir == DMA_DEV_TO_MEM) { -+ control_block->info = BCM2835_DMA_D_INC | -+ BCM2835_DMA_D_WIDTH | BCM2835_DMA_S_DREQ; -+ control_block->src = dev_addr; -+ control_block->dst = addr + (dma_addr_t)j; -+ } else { -+ control_block->info = BCM2835_DMA_S_INC | -+ BCM2835_DMA_S_WIDTH | BCM2835_DMA_D_DREQ; -+ control_block->src = addr + (dma_addr_t)j; -+ control_block->dst = dev_addr; -+ } -+ -+ /* Common part */ -+ waits = SDHCI_BCM_DMA_WAITS; -+ if ((dma_debug >> 0) & 0x1f) -+ waits = (dma_debug >> 0) & 0x1f; -+ control_block->info |= BCM2835_DMA_WAITS(waits); -+ control_block->info |= BCM2835_DMA_WAIT_RESP; -+ -+ /* Enable */ -+ if (i == sg_len-1 && len-j <= max_size) -+ control_block->info |= BCM2835_DMA_INT_EN; -+ -+ /* Setup synchronization */ -+ if (sync_type != 0) -+ control_block->info |= sync_type; -+ -+ /* Setup DREQ channel */ -+ if (c->dreq != 0) -+ control_block->info |= -+ BCM2835_DMA_PER_MAP(c->dreq); -+ -+ /* Length of a frame */ -+ control_block->length = min(len-j, max_size); -+ d->size += control_block->length; -+ -+ /* -+ * Next block is the next frame. -+ */ -+ if (i < sg_len-1 || len-j > max_size) { -+ /* next block is the next frame. */ -+ control_block->next = d->control_block_base_phys + -+ sizeof(struct bcm2835_dma_cb) * (i + splitct + 1); -+ } else { -+ /* next block is empty. */ -+ control_block->next = 0; -+ } -+ -+ if (len-j > max_size) -+ splitct++; -+ } -+ } -+ -+ c->cyclic = false; -+ -+ return vchan_tx_prep(&c->vc, &d->vd, flags); -+} -+ -+static int bcm2835_dma_slave_config(struct dma_chan *chan, -+ struct dma_slave_config *cfg) -+{ -+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); -+ if ((cfg->direction == DMA_DEV_TO_MEM && -+ cfg->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) || -+ (cfg->direction == DMA_MEM_TO_DEV && -+ cfg->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) || -+ !is_slave_direction(cfg->direction)) { -+ return -EINVAL; -+ } -+ -+ c->cfg = *cfg; -+ if (!c->dreq) -+ c->dreq = cfg->slave_id; -+ -+ return 0; -+} -+ -+static int bcm2835_dma_terminate_all(struct dma_chan *chan) -+{ -+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); -+ struct bcm2835_dmadev *d = to_bcm2835_dma_dev(c->vc.chan.device); -+ unsigned long flags; -+ int timeout = 10000; -+ LIST_HEAD(head); -+ -+ spin_lock_irqsave(&c->vc.lock, flags); -+ -+ /* Prevent this channel being scheduled */ -+ spin_lock(&d->lock); -+ list_del_init(&c->node); -+ spin_unlock(&d->lock); -+ -+ /* -+ * Stop DMA activity: we assume the callback will not be called -+ * after bcm_dma_abort() returns (even if it does, it will see -+ * c->desc is NULL and exit.) -+ */ -+ if (c->desc) { -+ bcm2835_dma_desc_free(&c->desc->vd); -+ c->desc = NULL; -+ bcm2835_dma_abort(c->chan_base); -+ -+ /* Wait for stopping */ -+ while (--timeout) { -+ if (!(readl(c->chan_base + BCM2835_DMA_CS) & -+ BCM2835_DMA_ACTIVE)) -+ break; -+ -+ cpu_relax(); -+ } -+ -+ if (!timeout) -+ dev_err(d->ddev.dev, "DMA transfer could not be terminated\n"); -+ } -+ -+ vchan_get_all_descriptors(&c->vc, &head); -+ spin_unlock_irqrestore(&c->vc.lock, flags); -+ vchan_dma_desc_free_list(&c->vc, &head); -+ -+ return 0; -+} -+ -+#ifndef CONFIG_DMA_BCM2708_LEGACY -+static int bcm2835_dma_chan_init(struct bcm2835_dmadev *d, int chan_id, int irq) -+{ -+ struct bcm2835_chan *c; -+ -+ c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL); -+ if (!c) -+ return -ENOMEM; -+ -+ c->vc.desc_free = bcm2835_dma_desc_free; -+ vchan_init(&c->vc, &d->ddev); -+ INIT_LIST_HEAD(&c->node); -+ -+ c->chan_base = BCM2835_DMA_CHANIO(d->base, chan_id); -+ c->ch = chan_id; -+ c->irq_number = irq; -+ -+ return 0; -+} -+#endif -+ -+static int bcm2708_dma_chan_init(struct bcm2835_dmadev *d, -+ void __iomem *chan_base, int chan_id, int irq) -+{ -+ struct bcm2835_chan *c; -+ -+ c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL); -+ if (!c) -+ return -ENOMEM; -+ -+ c->vc.desc_free = bcm2835_dma_desc_free; -+ vchan_init(&c->vc, &d->ddev); -+ INIT_LIST_HEAD(&c->node); -+ -+ c->chan_base = chan_base; -+ c->ch = chan_id; -+ c->irq_number = irq; -+ -+ return 0; -+} -+ -+ -+static void bcm2835_dma_free(struct bcm2835_dmadev *od) -+{ -+ struct bcm2835_chan *c, *next; -+ -+ list_for_each_entry_safe(c, next, &od->ddev.channels, -+ vc.chan.device_node) { -+ list_del(&c->vc.chan.device_node); -+ tasklet_kill(&c->vc.task); -+ } -+} -+ -+static const struct of_device_id bcm2835_dma_of_match[] = { -+ { .compatible = "brcm,bcm2835-dma", }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, bcm2835_dma_of_match); -+ -+static struct dma_chan *bcm2835_dma_xlate(struct of_phandle_args *spec, -+ struct of_dma *ofdma) -+{ -+ struct bcm2835_dmadev *d = ofdma->of_dma_data; -+ struct dma_chan *chan; -+ -+ chan = dma_get_any_slave_channel(&d->ddev); -+ if (!chan) -+ return NULL; -+ -+ /* Set DREQ from param */ -+ to_bcm2835_dma_chan(chan)->dreq = spec->args[0]; -+ -+ return chan; -+} -+ -+static int bcm2835_dma_probe(struct platform_device *pdev) -+{ -+ struct bcm2835_dmadev *od; -+#ifndef CONFIG_DMA_BCM2708_LEGACY -+ struct resource *res; -+ void __iomem *base; -+ uint32_t chans_available; -+#endif -+ int rc; -+ int i; -+ int irq; -+#ifdef CONFIG_DMA_BCM2708_LEGACY -+ static const u32 wanted_features[] = { -+ BCM_DMA_FEATURE_FAST, -+ BCM_DMA_FEATURE_NORMAL, -+ BCM_DMA_FEATURE_LITE -+ }; -+ int j; -+#endif -+ -+ -+ if (!pdev->dev.dma_mask) -+ pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; -+ -+#ifdef CONFIG_DMA_BCM2708_LEGACY -+ -+ rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); -+ if (rc) -+ return rc; -+ dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); -+ -+ -+ od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL); -+ if (!od) -+ return -ENOMEM; -+ -+ rc = bcm_dmaman_probe(pdev); -+ if (rc) -+ return rc; -+ -+ pdev->dev.dma_parms = &od->dma_parms; -+ dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF); -+ -+ -+ dma_cap_set(DMA_SLAVE, od->ddev.cap_mask); -+ dma_cap_set(DMA_PRIVATE, od->ddev.cap_mask); -+ dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask); -+ od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources; -+ od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources; -+ od->ddev.device_tx_status = bcm2835_dma_tx_status; -+ od->ddev.device_issue_pending = bcm2835_dma_issue_pending; -+ od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic; -+ od->ddev.device_prep_slave_sg = bcm2835_dma_prep_slave_sg; -+ od->ddev.device_terminate_all = bcm2835_dma_terminate_all; -+ od->ddev.device_config = bcm2835_dma_slave_config; -+ od->ddev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); -+ od->ddev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); -+ od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); -+ od->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; -+ od->ddev.dev = &pdev->dev; -+ INIT_LIST_HEAD(&od->ddev.channels); -+ spin_lock_init(&od->lock); -+ -+ platform_set_drvdata(pdev, od); -+ -+ for (i = 0, j = 0; j < ARRAY_SIZE(wanted_features);) { -+ -+ void __iomem *chan_base; -+ int chan_id; -+ -+ chan_id = bcm_dma_chan_alloc(wanted_features[j], -+ &chan_base, -+ &irq); -+ -+ if (chan_id < 0) { -+ j++; -+ continue; -+ } -+ -+ rc = bcm2708_dma_chan_init(od, chan_base, chan_id, irq); -+ if (rc) -+ goto err_no_dma; -+ i++; -+ } -+ -+ if (pdev->dev.of_node) { -+ rc = of_dma_controller_register(pdev->dev.of_node, -+ bcm2835_dma_xlate, od); -+ if (rc) { -+ dev_err(&pdev->dev, -+ "Failed to register DMA controller\n"); -+ goto err_no_dma; -+ } -+ } -+ -+ dev_info(&pdev->dev, "Initialized %i DMA channels (+ 1 legacy)\n", i); -+ -+#else -+ rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); -+ if (rc) -+ return rc; -+ -+ -+ od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL); -+ if (!od) -+ return -ENOMEM; -+ -+ pdev->dev.dma_parms = &od->dma_parms; -+ dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF); -+ -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ base = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(base)) -+ return PTR_ERR(base); -+ -+ od->base = base; -+ -+ -+ dma_cap_set(DMA_SLAVE, od->ddev.cap_mask); -+ dma_cap_set(DMA_PRIVATE, od->ddev.cap_mask); -+ dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask); -+ od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources; -+ od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources; -+ od->ddev.device_tx_status = bcm2835_dma_tx_status; -+ od->ddev.device_issue_pending = bcm2835_dma_issue_pending; -+ od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic; -+ od->ddev.device_prep_slave_sg = bcm2835_dma_prep_slave_sg; -+ od->ddev.device_terminate_all = bcm2835_dma_terminate_all; -+ od->ddev.device_config = bcm2835_dma_slave_config; -+ od->ddev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); -+ od->ddev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); -+ od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); -+ od->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; -+ od->ddev.dev = &pdev->dev; -+ INIT_LIST_HEAD(&od->ddev.channels); -+ spin_lock_init(&od->lock); -+ -+ platform_set_drvdata(pdev, od); -+ -+ -+ /* Request DMA channel mask from device tree */ -+ if (of_property_read_u32(pdev->dev.of_node, -+ "brcm,dma-channel-mask", -+ &chans_available)) { -+ dev_err(&pdev->dev, "Failed to get channel mask\n"); -+ rc = -EINVAL; -+ goto err_no_dma; -+ } -+ -+ -+ /* -+ * Do not use the FIQ and BULK channels, -+ * because they are used by the GPU. -+ */ -+ chans_available &= ~(BCM2835_DMA_FIQ_MASK | BCM2835_DMA_BULK_MASK); -+ -+ -+ for (i = 0; i < pdev->num_resources; i++) { -+ irq = platform_get_irq(pdev, i); -+ if (irq < 0) -+ break; -+ -+ if (chans_available & (1 << i)) { -+ rc = bcm2835_dma_chan_init(od, i, irq); -+ if (rc) -+ goto err_no_dma; -+ } -+ } -+ -+ dev_dbg(&pdev->dev, "Initialized %i DMA channels\n", i); -+ -+ /* Device-tree DMA controller registration */ -+ rc = of_dma_controller_register(pdev->dev.of_node, -+ bcm2835_dma_xlate, od); -+ if (rc) { -+ dev_err(&pdev->dev, "Failed to register DMA controller\n"); -+ goto err_no_dma; -+ } -+#endif -+ -+ rc = dma_async_device_register(&od->ddev); -+ if (rc) { -+ dev_err(&pdev->dev, -+ "Failed to register slave DMA engine device: %d\n", rc); -+ goto err_no_dma; -+ } -+ -+ dev_info(&pdev->dev, "Load BCM2835 DMA engine driver\n"); -+ dev_info(&pdev->dev, "dma_debug:%x\n", dma_debug); -+ -+ return 0; -+ -+err_no_dma: -+ bcm2835_dma_free(od); -+ return rc; -+} -+ -+static int bcm2835_dma_remove(struct platform_device *pdev) -+{ -+ struct bcm2835_dmadev *od = platform_get_drvdata(pdev); -+ -+ dma_async_device_unregister(&od->ddev); -+ bcm2835_dma_free(od); -+ bcm_dmaman_remove(pdev); -+ -+ return 0; -+} -+ -+static struct platform_driver bcm2835_dma_driver = { -+ .probe = bcm2835_dma_probe, -+ .remove = bcm2835_dma_remove, -+ .driver = { -+ .name = "bcm2708-dmaengine", -+ .owner = THIS_MODULE, -+ .of_match_table = of_match_ptr(bcm2835_dma_of_match), -+ }, -+}; -+ -+static int bcm2835_init(void) -+{ -+ return platform_driver_register(&bcm2835_dma_driver); -+} -+ -+static void bcm2835_exit(void) -+{ -+ platform_driver_unregister(&bcm2835_dma_driver); -+} -+ -+/* -+ * Load after serial driver (arch_initcall) so we see the messages if it fails, -+ * but before drivers (module_init) that need a DMA channel. -+ */ -+subsys_initcall(bcm2835_init); -+module_exit(bcm2835_exit); -+ -+module_param(dma_debug, uint, 0644); -+#ifdef CONFIG_DMA_BCM2708_LEGACY -+/* Keep backward compatibility: dma.dmachans= */ -+#undef MODULE_PARAM_PREFIX -+#define MODULE_PARAM_PREFIX "dma." -+module_param(dmachans, int, 0644); -+#endif -+MODULE_ALIAS("platform:bcm2835-dma"); -+MODULE_DESCRIPTION("BCM2835 DMA engine driver"); -+MODULE_AUTHOR("Florian Meier "); -+MODULE_AUTHOR("Gellert Weisz "); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-4.1.13.orig/drivers/dma/Kconfig linux-rpi/drivers/dma/Kconfig ---- linux-4.1.13.orig/drivers/dma/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/dma/Kconfig 2015-11-29 09:42:36.815304925 +0100 -@@ -337,6 +337,17 @@ - select DMA_ENGINE - select DMA_VIRTUAL_CHANNELS - -+config DMA_BCM2708 -+ tristate "BCM2708 DMA engine support" -+ depends on MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835 -+ select DMA_ENGINE -+ select DMA_VIRTUAL_CHANNELS -+ -+config DMA_BCM2708_LEGACY -+ bool "BCM2708 DMA legacy API support" -+ depends on DMA_BCM2708 -+ default y -+ - config TI_CPPI41 - tristate "AM33xx CPPI41 DMA support" - depends on ARCH_OMAP -@@ -385,7 +396,7 @@ - select DMA_VIRTUAL_CHANNELS - help - Enable support for the MOXA ART SoC DMA controller. -- -+ - config FSL_EDMA - tristate "Freescale eDMA engine support" - depends on OF -diff -Nur linux-4.1.13.orig/drivers/dma/Makefile linux-rpi/drivers/dma/Makefile ---- linux-4.1.13.orig/drivers/dma/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/dma/Makefile 2015-11-29 09:42:36.815304925 +0100 -@@ -39,6 +39,7 @@ - obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o - obj-$(CONFIG_DMA_OMAP) += omap-dma.o - obj-$(CONFIG_DMA_BCM2835) += bcm2835-dma.o -+obj-$(CONFIG_DMA_BCM2708) += bcm2708-dmaengine.o - obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o - obj-$(CONFIG_DMA_JZ4740) += dma-jz4740.o - obj-$(CONFIG_DMA_JZ4780) += dma-jz4780.o -diff -Nur linux-4.1.13.orig/drivers/firmware/Kconfig linux-rpi/drivers/firmware/Kconfig ---- linux-4.1.13.orig/drivers/firmware/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/firmware/Kconfig 2015-11-29 09:42:36.883300407 +0100 -@@ -136,6 +136,13 @@ - bool - depends on ARM || ARM64 - -+config RASPBERRYPI_FIRMWARE -+ tristate "Raspberry Pi Firmware Driver" -+ depends on BCM2835_MBOX -+ help -+ This option enables support for communicating with the firmware on the -+ Raspberry Pi. -+ - source "drivers/firmware/google/Kconfig" - source "drivers/firmware/efi/Kconfig" - -diff -Nur linux-4.1.13.orig/drivers/firmware/Makefile linux-rpi/drivers/firmware/Makefile ---- linux-4.1.13.orig/drivers/firmware/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/firmware/Makefile 2015-11-29 09:42:36.883300407 +0100 -@@ -13,6 +13,7 @@ - obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o - obj-$(CONFIG_QCOM_SCM) += qcom_scm.o - CFLAGS_qcom_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1) -+obj-$(CONFIG_RASPBERRYPI_FIRMWARE) += raspberrypi.o - - obj-$(CONFIG_GOOGLE_FIRMWARE) += google/ - obj-$(CONFIG_EFI) += efi/ -diff -Nur linux-4.1.13.orig/drivers/firmware/raspberrypi.c linux-rpi/drivers/firmware/raspberrypi.c ---- linux-4.1.13.orig/drivers/firmware/raspberrypi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/firmware/raspberrypi.c 2015-11-29 09:42:36.887300142 +0100 -@@ -0,0 +1,297 @@ -+/* -+ * Defines interfaces for interacting wtih the Raspberry Pi firmware's -+ * property channel. -+ * -+ * Copyright © 2015 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define MBOX_MSG(chan, data28) (((data28) & ~0xf) | ((chan) & 0xf)) -+#define MBOX_CHAN(msg) ((msg) & 0xf) -+#define MBOX_DATA28(msg) ((msg) & ~0xf) -+#define MBOX_CHAN_PROPERTY 8 -+ -+struct rpi_firmware { -+ struct mbox_client cl; -+ struct mbox_chan *chan; /* The property channel. */ -+ struct completion c; -+ u32 enabled; -+}; -+ -+static struct platform_device *g_pdev; -+ -+static DEFINE_MUTEX(transaction_lock); -+ -+static void response_callback(struct mbox_client *cl, void *msg) -+{ -+ struct rpi_firmware *fw = container_of(cl, struct rpi_firmware, cl); -+ complete(&fw->c); -+} -+ -+/* -+ * Sends a request to the firmware through the BCM2835 mailbox driver, -+ * and synchronously waits for the reply. -+ */ -+static int -+rpi_firmware_transaction(struct rpi_firmware *fw, u32 chan, u32 data) -+{ -+ u32 message = MBOX_MSG(chan, data); -+ int ret; -+ -+ WARN_ON(data & 0xf); -+ -+ mutex_lock(&transaction_lock); -+ reinit_completion(&fw->c); -+ ret = mbox_send_message(fw->chan, &message); -+ if (ret >= 0) { -+ wait_for_completion(&fw->c); -+ ret = 0; -+ } else { -+ dev_err(fw->cl.dev, "mbox_send_message returned %d\n", ret); -+ } -+ mutex_unlock(&transaction_lock); -+ -+ return ret; -+} -+ -+/** -+ * rpi_firmware_property_list - Submit firmware property list -+ * @fw: Pointer to firmware structure from rpi_firmware_get(). -+ * @data: Buffer holding tags. -+ * @tag_size: Size of tags buffer. -+ * -+ * Submits a set of concatenated tags to the VPU firmware through the -+ * mailbox property interface. -+ * -+ * The buffer header and the ending tag are added by this function and -+ * don't need to be supplied, just the actual tags for your operation. -+ * See struct rpi_firmware_property_tag_header for the per-tag -+ * structure. -+ */ -+int rpi_firmware_property_list(struct rpi_firmware *fw, -+ void *data, size_t tag_size) -+{ -+ size_t size = tag_size + 12; -+ u32 *buf; -+ dma_addr_t bus_addr; -+ int ret; -+ -+ /* Packets are processed a dword at a time. */ -+ if (size & 3) -+ return -EINVAL; -+ -+ buf = dma_alloc_coherent(fw->cl.dev, PAGE_ALIGN(size), &bus_addr, -+ GFP_ATOMIC); -+ if (!buf) -+ return -ENOMEM; -+ -+ /* The firmware will error out without parsing in this case. */ -+ WARN_ON(size >= 1024 * 1024); -+ -+ buf[0] = size; -+ buf[1] = RPI_FIRMWARE_STATUS_REQUEST; -+ memcpy(&buf[2], data, tag_size); -+ buf[size / 4 - 1] = RPI_FIRMWARE_PROPERTY_END; -+ wmb(); -+ -+ ret = rpi_firmware_transaction(fw, MBOX_CHAN_PROPERTY, bus_addr); -+ -+ rmb(); -+ memcpy(data, &buf[2], tag_size); -+ if (ret == 0 && buf[1] != RPI_FIRMWARE_STATUS_SUCCESS) { -+ /* -+ * The tag name here might not be the one causing the -+ * error, if there were multiple tags in the request. -+ * But single-tag is the most common, so go with it. -+ */ -+ dev_err(fw->cl.dev, "Request 0x%08x returned status 0x%08x\n", -+ buf[2], buf[1]); -+ ret = -EINVAL; -+ } -+ -+ dma_free_coherent(fw->cl.dev, PAGE_ALIGN(size), buf, bus_addr); -+ -+ return ret; -+} -+EXPORT_SYMBOL_GPL(rpi_firmware_property_list); -+ -+/** -+ * rpi_firmware_property - Submit single firmware property -+ * @fw: Pointer to firmware structure from rpi_firmware_get(). -+ * @tag: One of enum_mbox_property_tag. -+ * @tag_data: Tag data buffer. -+ * @buf_size: Buffer size. -+ * -+ * Submits a single tag to the VPU firmware through the mailbox -+ * property interface. -+ * -+ * This is a convenience wrapper around -+ * rpi_firmware_property_list() to avoid some of the -+ * boilerplate in property calls. -+ */ -+int rpi_firmware_property(struct rpi_firmware *fw, -+ u32 tag, void *tag_data, size_t buf_size) -+{ -+ /* Single tags are very small (generally 8 bytes), so the -+ * stack should be safe. -+ */ -+ u8 data[buf_size + sizeof(struct rpi_firmware_property_tag_header)]; -+ struct rpi_firmware_property_tag_header *header = -+ (struct rpi_firmware_property_tag_header *)data; -+ int ret; -+ -+ header->tag = tag; -+ header->buf_size = buf_size; -+ header->req_resp_size = 0; -+ memcpy(data + sizeof(struct rpi_firmware_property_tag_header), -+ tag_data, buf_size); -+ -+ ret = rpi_firmware_property_list(fw, &data, sizeof(data)); -+ memcpy(tag_data, -+ data + sizeof(struct rpi_firmware_property_tag_header), -+ buf_size); -+ -+ return ret; -+} -+EXPORT_SYMBOL_GPL(rpi_firmware_property); -+ -+static void -+rpi_firmware_print_firmware_revision(struct rpi_firmware *fw) -+{ -+ u32 packet; -+ int ret = rpi_firmware_property(fw, -+ RPI_FIRMWARE_GET_FIRMWARE_REVISION, -+ &packet, sizeof(packet)); -+ -+ if (ret == 0) { -+ struct tm tm; -+ -+ time_to_tm(packet, 0, &tm); -+ -+ dev_info(fw->cl.dev, -+ "Attached to firmware from %04ld-%02d-%02d %02d:%02d\n", -+ tm.tm_year + 1900, tm.tm_mon + 1, tm.tm_mday, -+ tm.tm_hour, tm.tm_min); -+ } -+} -+ -+static int raspberrypi_firmware_set_power(struct rpi_firmware *fw, -+ u32 domain, bool on) -+{ -+ struct { -+ u32 domain; -+ u32 on; -+ } packet; -+ int ret; -+ -+ packet.domain = domain; -+ packet.on = on; -+ ret = rpi_firmware_property(fw, RPI_FIRMWARE_SET_POWER_STATE, -+ &packet, sizeof(packet)); -+ if (!ret && packet.on != on) -+ ret = -EINVAL; -+ -+ return ret; -+} -+ -+static int rpi_firmware_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct rpi_firmware *fw; -+ -+ fw = devm_kzalloc(dev, sizeof(*fw), GFP_KERNEL); -+ if (!fw) -+ return -ENOMEM; -+ -+ fw->cl.dev = dev; -+ fw->cl.rx_callback = response_callback; -+ fw->cl.tx_block = true; -+ -+ fw->chan = mbox_request_channel(&fw->cl, 0); -+ if (IS_ERR(fw->chan)) { -+ int ret = PTR_ERR(fw->chan); -+ if (ret != -EPROBE_DEFER) -+ dev_err(dev, "Failed to get mbox channel: %d\n", ret); -+ return ret; -+ } -+ -+ init_completion(&fw->c); -+ -+ platform_set_drvdata(pdev, fw); -+ g_pdev = pdev; -+ -+ rpi_firmware_print_firmware_revision(fw); -+ -+ if (raspberrypi_firmware_set_power(fw, 3, true)) -+ dev_err(dev, "failed to turn on USB power\n"); -+ -+ return 0; -+} -+ -+static int rpi_firmware_remove(struct platform_device *pdev) -+{ -+ struct rpi_firmware *fw = platform_get_drvdata(pdev); -+ -+ mbox_free_channel(fw->chan); -+ g_pdev = NULL; -+ -+ return 0; -+} -+ -+/** -+ * rpi_firmware_get - Get pointer to rpi_firmware structure. -+ * @firmware_node: Pointer to the firmware Device Tree node. -+ * -+ * Returns NULL is the firmware device is not ready. -+ */ -+struct rpi_firmware *rpi_firmware_get(struct device_node *firmware_node) -+{ -+ struct platform_device *pdev = g_pdev; -+ -+ if (!pdev) -+ return NULL; -+ -+ return platform_get_drvdata(pdev); -+} -+EXPORT_SYMBOL_GPL(rpi_firmware_get); -+ -+static const struct of_device_id rpi_firmware_of_match[] = { -+ { .compatible = "raspberrypi,bcm2835-firmware", }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, rpi_firmware_of_match); -+ -+static struct platform_driver rpi_firmware_driver = { -+ .driver = { -+ .name = "raspberrypi-firmware", -+ .of_match_table = rpi_firmware_of_match, -+ }, -+ .probe = rpi_firmware_probe, -+ .remove = rpi_firmware_remove, -+}; -+ -+static int __init rpi_firmware_init(void) -+{ -+ return platform_driver_register(&rpi_firmware_driver); -+} -+subsys_initcall(rpi_firmware_init); -+ -+static void __init rpi_firmware_exit(void) -+{ -+ platform_driver_unregister(&rpi_firmware_driver); -+} -+module_exit(rpi_firmware_exit); -+ -+MODULE_AUTHOR("Eric Anholt "); -+MODULE_DESCRIPTION("Raspberry Pi firmware driver"); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-4.1.13.orig/drivers/hid/usbhid/hid-core.c linux-rpi/drivers/hid/usbhid/hid-core.c ---- linux-4.1.13.orig/drivers/hid/usbhid/hid-core.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/hid/usbhid/hid-core.c 2015-11-29 09:42:37.327270908 +0100 -@@ -49,7 +49,7 @@ - * Module parameters. - */ - --static unsigned int hid_mousepoll_interval; -+static unsigned int hid_mousepoll_interval = ~0; - module_param_named(mousepoll, hid_mousepoll_interval, uint, 0644); - MODULE_PARM_DESC(mousepoll, "Polling interval of mice"); - -@@ -1090,8 +1090,12 @@ - } - - /* Change the polling interval of mice. */ -- if (hid->collection->usage == HID_GD_MOUSE && hid_mousepoll_interval > 0) -- interval = hid_mousepoll_interval; -+ if (hid->collection->usage == HID_GD_MOUSE) { -+ if (hid_mousepoll_interval == ~0 && interval < 16) -+ interval = 16; -+ else if (hid_mousepoll_interval != ~0 && hid_mousepoll_interval != 0) -+ interval = hid_mousepoll_interval; -+ } - - ret = -ENOMEM; - if (usb_endpoint_dir_in(endpoint)) { -diff -Nur linux-4.1.13.orig/drivers/i2c/busses/i2c-bcm2708.c linux-rpi/drivers/i2c/busses/i2c-bcm2708.c ---- linux-4.1.13.orig/drivers/i2c/busses/i2c-bcm2708.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/i2c/busses/i2c-bcm2708.c 2015-11-29 09:42:37.375267719 +0100 -@@ -0,0 +1,524 @@ -+/* -+ * Driver for Broadcom BCM2708 BSC Controllers -+ * -+ * Copyright (C) 2012 Chris Boot & Frank Buss -+ * -+ * This driver is inspired by: -+ * i2c-ocores.c, by Peter Korsgaard -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* BSC register offsets */ -+#define BSC_C 0x00 -+#define BSC_S 0x04 -+#define BSC_DLEN 0x08 -+#define BSC_A 0x0c -+#define BSC_FIFO 0x10 -+#define BSC_DIV 0x14 -+#define BSC_DEL 0x18 -+#define BSC_CLKT 0x1c -+ -+/* Bitfields in BSC_C */ -+#define BSC_C_I2CEN 0x00008000 -+#define BSC_C_INTR 0x00000400 -+#define BSC_C_INTT 0x00000200 -+#define BSC_C_INTD 0x00000100 -+#define BSC_C_ST 0x00000080 -+#define BSC_C_CLEAR_1 0x00000020 -+#define BSC_C_CLEAR_2 0x00000010 -+#define BSC_C_READ 0x00000001 -+ -+/* Bitfields in BSC_S */ -+#define BSC_S_CLKT 0x00000200 -+#define BSC_S_ERR 0x00000100 -+#define BSC_S_RXF 0x00000080 -+#define BSC_S_TXE 0x00000040 -+#define BSC_S_RXD 0x00000020 -+#define BSC_S_TXD 0x00000010 -+#define BSC_S_RXR 0x00000008 -+#define BSC_S_TXW 0x00000004 -+#define BSC_S_DONE 0x00000002 -+#define BSC_S_TA 0x00000001 -+ -+#define I2C_WAIT_LOOP_COUNT 200 -+ -+#define DRV_NAME "bcm2708_i2c" -+ -+static unsigned int baudrate = CONFIG_I2C_BCM2708_BAUDRATE; -+module_param(baudrate, uint, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP); -+MODULE_PARM_DESC(baudrate, "The I2C baudrate"); -+ -+static bool combined = false; -+module_param(combined, bool, 0644); -+MODULE_PARM_DESC(combined, "Use combined transactions"); -+ -+struct bcm2708_i2c { -+ struct i2c_adapter adapter; -+ -+ spinlock_t lock; -+ void __iomem *base; -+ int irq; -+ struct clk *clk; -+ u32 cdiv; -+ -+ struct completion done; -+ -+ struct i2c_msg *msg; -+ int pos; -+ int nmsgs; -+ bool error; -+}; -+ -+/* -+ * This function sets the ALT mode on the I2C pins so that we can use them with -+ * the BSC hardware. -+ * -+ * FIXME: This is a hack. Use pinmux / pinctrl. -+ */ -+static void bcm2708_i2c_init_pinmode(int id) -+{ -+#define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3)) -+#define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3)) -+ -+ int pin; -+ u32 *gpio = ioremap(GPIO_BASE, SZ_16K); -+ -+ BUG_ON(id != 0 && id != 1); -+ /* BSC0 is on GPIO 0 & 1, BSC1 is on GPIO 2 & 3 */ -+ for (pin = id*2+0; pin <= id*2+1; pin++) { -+ printk("bcm2708_i2c_init_pinmode(%d,%d)\n", id, pin); -+ INP_GPIO(pin); /* set mode to GPIO input first */ -+ SET_GPIO_ALT(pin, 0); /* set mode to ALT 0 */ -+ } -+ -+ iounmap(gpio); -+ -+#undef INP_GPIO -+#undef SET_GPIO_ALT -+} -+ -+static inline u32 bcm2708_rd(struct bcm2708_i2c *bi, unsigned reg) -+{ -+ return readl(bi->base + reg); -+} -+ -+static inline void bcm2708_wr(struct bcm2708_i2c *bi, unsigned reg, u32 val) -+{ -+ writel(val, bi->base + reg); -+} -+ -+static inline void bcm2708_bsc_reset(struct bcm2708_i2c *bi) -+{ -+ bcm2708_wr(bi, BSC_C, 0); -+ bcm2708_wr(bi, BSC_S, BSC_S_CLKT | BSC_S_ERR | BSC_S_DONE); -+} -+ -+static inline void bcm2708_bsc_fifo_drain(struct bcm2708_i2c *bi) -+{ -+ while ((bcm2708_rd(bi, BSC_S) & BSC_S_RXD) && (bi->pos < bi->msg->len)) -+ bi->msg->buf[bi->pos++] = bcm2708_rd(bi, BSC_FIFO); -+} -+ -+static inline void bcm2708_bsc_fifo_fill(struct bcm2708_i2c *bi) -+{ -+ while ((bcm2708_rd(bi, BSC_S) & BSC_S_TXD) && (bi->pos < bi->msg->len)) -+ bcm2708_wr(bi, BSC_FIFO, bi->msg->buf[bi->pos++]); -+} -+ -+static inline int bcm2708_bsc_setup(struct bcm2708_i2c *bi) -+{ -+ u32 cdiv, s; -+ u32 c = BSC_C_I2CEN | BSC_C_INTD | BSC_C_ST | BSC_C_CLEAR_1; -+ int wait_loops = I2C_WAIT_LOOP_COUNT; -+ -+ /* Can't call clk_get_rate as it locks a mutex and here we are spinlocked. -+ * Use the value that we cached in the probe. -+ */ -+ cdiv = bi->cdiv; -+ -+ if (bi->msg->flags & I2C_M_RD) -+ c |= BSC_C_INTR | BSC_C_READ; -+ else -+ c |= BSC_C_INTT; -+ -+ bcm2708_wr(bi, BSC_DIV, cdiv); -+ bcm2708_wr(bi, BSC_A, bi->msg->addr); -+ bcm2708_wr(bi, BSC_DLEN, bi->msg->len); -+ if (combined) -+ { -+ /* Do the next two messages meet combined transaction criteria? -+ - Current message is a write, next message is a read -+ - Both messages to same slave address -+ - Write message can fit inside FIFO (16 bytes or less) */ -+ if ( (bi->nmsgs > 1) && -+ !(bi->msg[0].flags & I2C_M_RD) && (bi->msg[1].flags & I2C_M_RD) && -+ (bi->msg[0].addr == bi->msg[1].addr) && (bi->msg[0].len <= 16)) { -+ /* Fill FIFO with entire write message (16 byte FIFO) */ -+ while (bi->pos < bi->msg->len) { -+ bcm2708_wr(bi, BSC_FIFO, bi->msg->buf[bi->pos++]); -+ } -+ /* Start write transfer (no interrupts, don't clear FIFO) */ -+ bcm2708_wr(bi, BSC_C, BSC_C_I2CEN | BSC_C_ST); -+ -+ /* poll for transfer start bit (should only take 1-20 polls) */ -+ do { -+ s = bcm2708_rd(bi, BSC_S); -+ } while (!(s & (BSC_S_TA | BSC_S_ERR | BSC_S_CLKT | BSC_S_DONE)) && --wait_loops >= 0); -+ -+ /* did we time out or some error occured? */ -+ if (wait_loops < 0 || (s & (BSC_S_ERR | BSC_S_CLKT))) { -+ return -1; -+ } -+ -+ /* Send next read message before the write transfer finishes. */ -+ bi->nmsgs--; -+ bi->msg++; -+ bi->pos = 0; -+ bcm2708_wr(bi, BSC_DLEN, bi->msg->len); -+ c = BSC_C_I2CEN | BSC_C_INTD | BSC_C_INTR | BSC_C_ST | BSC_C_READ; -+ } -+ } -+ bcm2708_wr(bi, BSC_C, c); -+ -+ return 0; -+} -+ -+static irqreturn_t bcm2708_i2c_interrupt(int irq, void *dev_id) -+{ -+ struct bcm2708_i2c *bi = dev_id; -+ bool handled = true; -+ u32 s; -+ int ret; -+ -+ spin_lock(&bi->lock); -+ -+ /* we may see camera interrupts on the "other" I2C channel -+ Just return if we've not sent anything */ -+ if (!bi->nmsgs || !bi->msg) { -+ goto early_exit; -+ } -+ -+ s = bcm2708_rd(bi, BSC_S); -+ -+ if (s & (BSC_S_CLKT | BSC_S_ERR)) { -+ bcm2708_bsc_reset(bi); -+ bi->error = true; -+ -+ bi->msg = 0; /* to inform the that all work is done */ -+ bi->nmsgs = 0; -+ /* wake up our bh */ -+ complete(&bi->done); -+ } else if (s & BSC_S_DONE) { -+ bi->nmsgs--; -+ -+ if (bi->msg->flags & I2C_M_RD) { -+ bcm2708_bsc_fifo_drain(bi); -+ } -+ -+ bcm2708_bsc_reset(bi); -+ -+ if (bi->nmsgs) { -+ /* advance to next message */ -+ bi->msg++; -+ bi->pos = 0; -+ ret = bcm2708_bsc_setup(bi); -+ if (ret < 0) { -+ bcm2708_bsc_reset(bi); -+ bi->error = true; -+ bi->msg = 0; /* to inform the that all work is done */ -+ bi->nmsgs = 0; -+ /* wake up our bh */ -+ complete(&bi->done); -+ goto early_exit; -+ } -+ } else { -+ bi->msg = 0; /* to inform the that all work is done */ -+ bi->nmsgs = 0; -+ /* wake up our bh */ -+ complete(&bi->done); -+ } -+ } else if (s & BSC_S_TXW) { -+ bcm2708_bsc_fifo_fill(bi); -+ } else if (s & BSC_S_RXR) { -+ bcm2708_bsc_fifo_drain(bi); -+ } else { -+ handled = false; -+ } -+ -+early_exit: -+ spin_unlock(&bi->lock); -+ -+ return handled ? IRQ_HANDLED : IRQ_NONE; -+} -+ -+static int bcm2708_i2c_master_xfer(struct i2c_adapter *adap, -+ struct i2c_msg *msgs, int num) -+{ -+ struct bcm2708_i2c *bi = adap->algo_data; -+ unsigned long flags; -+ int ret; -+ -+ spin_lock_irqsave(&bi->lock, flags); -+ -+ reinit_completion(&bi->done); -+ bi->msg = msgs; -+ bi->pos = 0; -+ bi->nmsgs = num; -+ bi->error = false; -+ -+ ret = bcm2708_bsc_setup(bi); -+ -+ spin_unlock_irqrestore(&bi->lock, flags); -+ -+ /* check the result of the setup */ -+ if (ret < 0) -+ { -+ dev_err(&adap->dev, "transfer setup timed out\n"); -+ goto error_timeout; -+ } -+ -+ ret = wait_for_completion_timeout(&bi->done, adap->timeout); -+ if (ret == 0) { -+ dev_err(&adap->dev, "transfer timed out\n"); -+ goto error_timeout; -+ } -+ -+ ret = bi->error ? -EIO : num; -+ return ret; -+ -+error_timeout: -+ spin_lock_irqsave(&bi->lock, flags); -+ bcm2708_bsc_reset(bi); -+ bi->msg = 0; /* to inform the interrupt handler that there's nothing else to be done */ -+ bi->nmsgs = 0; -+ spin_unlock_irqrestore(&bi->lock, flags); -+ return -ETIMEDOUT; -+} -+ -+static u32 bcm2708_i2c_functionality(struct i2c_adapter *adap) -+{ -+ return I2C_FUNC_I2C | /*I2C_FUNC_10BIT_ADDR |*/ I2C_FUNC_SMBUS_EMUL; -+} -+ -+static struct i2c_algorithm bcm2708_i2c_algorithm = { -+ .master_xfer = bcm2708_i2c_master_xfer, -+ .functionality = bcm2708_i2c_functionality, -+}; -+ -+static int bcm2708_i2c_probe(struct platform_device *pdev) -+{ -+ struct resource *regs; -+ int irq, err = -ENOMEM; -+ struct clk *clk; -+ struct bcm2708_i2c *bi; -+ struct i2c_adapter *adap; -+ unsigned long bus_hz; -+ u32 cdiv; -+ -+ if (pdev->dev.of_node) { -+ u32 bus_clk_rate; -+ pdev->id = of_alias_get_id(pdev->dev.of_node, "i2c"); -+ if (pdev->id < 0) { -+ dev_err(&pdev->dev, "alias is missing\n"); -+ return -EINVAL; -+ } -+ if (!of_property_read_u32(pdev->dev.of_node, -+ "clock-frequency", &bus_clk_rate)) -+ baudrate = bus_clk_rate; -+ else -+ dev_warn(&pdev->dev, -+ "Could not read clock-frequency property\n"); -+ } -+ -+ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!regs) { -+ dev_err(&pdev->dev, "could not get IO memory\n"); -+ return -ENXIO; -+ } -+ -+ irq = platform_get_irq(pdev, 0); -+ if (irq < 0) { -+ dev_err(&pdev->dev, "could not get IRQ\n"); -+ return irq; -+ } -+ -+ clk = clk_get(&pdev->dev, NULL); -+ if (IS_ERR(clk)) { -+ dev_err(&pdev->dev, "could not find clk: %ld\n", PTR_ERR(clk)); -+ return PTR_ERR(clk); -+ } -+ -+ err = clk_prepare_enable(clk); -+ if (err) { -+ dev_err(&pdev->dev, "could not enable clk: %d\n", err); -+ goto out_clk_put; -+ } -+ -+ if (!pdev->dev.of_node) -+ bcm2708_i2c_init_pinmode(pdev->id); -+ -+ bi = kzalloc(sizeof(*bi), GFP_KERNEL); -+ if (!bi) -+ goto out_clk_disable; -+ -+ platform_set_drvdata(pdev, bi); -+ -+ adap = &bi->adapter; -+ adap->class = I2C_CLASS_HWMON | I2C_CLASS_DDC; -+ adap->algo = &bcm2708_i2c_algorithm; -+ adap->algo_data = bi; -+ adap->dev.parent = &pdev->dev; -+ adap->nr = pdev->id; -+ strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name)); -+ adap->dev.of_node = pdev->dev.of_node; -+ -+ switch (pdev->id) { -+ case 0: -+ adap->class = I2C_CLASS_HWMON; -+ break; -+ case 1: -+ adap->class = I2C_CLASS_DDC; -+ break; -+ case 2: -+ adap->class = I2C_CLASS_DDC; -+ break; -+ default: -+ dev_err(&pdev->dev, "can only bind to BSC 0, 1 or 2\n"); -+ err = -ENXIO; -+ goto out_free_bi; -+ } -+ -+ spin_lock_init(&bi->lock); -+ init_completion(&bi->done); -+ -+ bi->base = ioremap(regs->start, resource_size(regs)); -+ if (!bi->base) { -+ dev_err(&pdev->dev, "could not remap memory\n"); -+ goto out_free_bi; -+ } -+ -+ bi->irq = irq; -+ bi->clk = clk; -+ -+ err = request_irq(irq, bcm2708_i2c_interrupt, IRQF_SHARED, -+ dev_name(&pdev->dev), bi); -+ if (err) { -+ dev_err(&pdev->dev, "could not request IRQ: %d\n", err); -+ goto out_iounmap; -+ } -+ -+ bcm2708_bsc_reset(bi); -+ -+ err = i2c_add_numbered_adapter(adap); -+ if (err < 0) { -+ dev_err(&pdev->dev, "could not add I2C adapter: %d\n", err); -+ goto out_free_irq; -+ } -+ -+ bus_hz = clk_get_rate(bi->clk); -+ cdiv = bus_hz / baudrate; -+ if (cdiv > 0xffff) { -+ cdiv = 0xffff; -+ baudrate = bus_hz / cdiv; -+ } -+ bi->cdiv = cdiv; -+ -+ dev_info(&pdev->dev, "BSC%d Controller at 0x%08lx (irq %d) (baudrate %d)\n", -+ pdev->id, (unsigned long)regs->start, irq, baudrate); -+ -+ return 0; -+ -+out_free_irq: -+ free_irq(bi->irq, bi); -+out_iounmap: -+ iounmap(bi->base); -+out_free_bi: -+ kfree(bi); -+out_clk_disable: -+ clk_disable_unprepare(clk); -+out_clk_put: -+ clk_put(clk); -+ return err; -+} -+ -+static int bcm2708_i2c_remove(struct platform_device *pdev) -+{ -+ struct bcm2708_i2c *bi = platform_get_drvdata(pdev); -+ -+ platform_set_drvdata(pdev, NULL); -+ -+ i2c_del_adapter(&bi->adapter); -+ free_irq(bi->irq, bi); -+ iounmap(bi->base); -+ clk_disable_unprepare(bi->clk); -+ clk_put(bi->clk); -+ kfree(bi); -+ -+ return 0; -+} -+ -+static const struct of_device_id bcm2708_i2c_of_match[] = { -+ { .compatible = "brcm,bcm2708-i2c" }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, bcm2708_i2c_of_match); -+ -+static struct platform_driver bcm2708_i2c_driver = { -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ .of_match_table = bcm2708_i2c_of_match, -+ }, -+ .probe = bcm2708_i2c_probe, -+ .remove = bcm2708_i2c_remove, -+}; -+ -+// module_platform_driver(bcm2708_i2c_driver); -+ -+ -+static int __init bcm2708_i2c_init(void) -+{ -+ return platform_driver_register(&bcm2708_i2c_driver); -+} -+ -+static void __exit bcm2708_i2c_exit(void) -+{ -+ platform_driver_unregister(&bcm2708_i2c_driver); -+} -+ -+module_init(bcm2708_i2c_init); -+module_exit(bcm2708_i2c_exit); -+ -+ -+ -+MODULE_DESCRIPTION("BSC controller driver for Broadcom BCM2708"); -+MODULE_AUTHOR("Chris Boot "); -+MODULE_LICENSE("GPL v2"); -+MODULE_ALIAS("platform:" DRV_NAME); -diff -Nur linux-4.1.13.orig/drivers/i2c/busses/Kconfig linux-rpi/drivers/i2c/busses/Kconfig ---- linux-4.1.13.orig/drivers/i2c/busses/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/i2c/busses/Kconfig 2015-11-29 09:42:37.371267984 +0100 -@@ -8,6 +8,25 @@ - comment "PC SMBus host controller drivers" - depends on PCI - -+config I2C_BCM2708 -+ tristate "BCM2708 BSC" -+ depends on MACH_BCM2708 || MACH_BCM2709 -+ help -+ Enabling this option will add BSC (Broadcom Serial Controller) -+ support for the BCM2708. BSC is a Broadcom proprietary bus compatible -+ with I2C/TWI/SMBus. -+ -+config I2C_BCM2708_BAUDRATE -+ prompt "BCM2708 I2C baudrate" -+ depends on I2C_BCM2708 -+ int -+ default 100000 -+ help -+ Set the I2C baudrate. This will alter the default value. A -+ different baudrate can be set by using a module parameter as well. If -+ no parameter is provided when loading, this is the value that will be -+ used. -+ - config I2C_ALI1535 - tristate "ALI 1535" - depends on PCI -@@ -362,7 +381,7 @@ - - config I2C_BCM2835 - tristate "Broadcom BCM2835 I2C controller" -- depends on ARCH_BCM2835 -+ depends on ARCH_BCM2835 || ARCH_BCM2708 || ARCH_BCM2709 - help - If you say yes to this option, support will be included for the - BCM2835 I2C controller. -diff -Nur linux-4.1.13.orig/drivers/i2c/busses/Makefile linux-rpi/drivers/i2c/busses/Makefile ---- linux-4.1.13.orig/drivers/i2c/busses/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/i2c/busses/Makefile 2015-11-29 09:42:37.371267984 +0100 -@@ -2,6 +2,8 @@ - # Makefile for the i2c bus drivers. - # - -+obj-$(CONFIG_I2C_BCM2708) += i2c-bcm2708.o -+ - # ACPI drivers - obj-$(CONFIG_I2C_SCMI) += i2c-scmi.o - -diff -Nur linux-4.1.13.orig/drivers/input/joystick/Kconfig linux-rpi/drivers/input/joystick/Kconfig ---- linux-4.1.13.orig/drivers/input/joystick/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/input/joystick/Kconfig 2015-11-29 09:42:37.515258417 +0100 -@@ -329,4 +329,12 @@ - To compile this as a module choose M here: the module will be called - maplecontrol. - -+config JOYSTICK_RPISENSE -+ tristate "Raspberry Pi Sense HAT joystick" -+ depends on GPIOLIB && INPUT -+ select MFD_RPISENSE_CORE -+ -+ help -+ This is the joystick driver for the Raspberry Pi Sense HAT -+ - endif -diff -Nur linux-4.1.13.orig/drivers/input/joystick/Makefile linux-rpi/drivers/input/joystick/Makefile ---- linux-4.1.13.orig/drivers/input/joystick/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/input/joystick/Makefile 2015-11-29 09:42:37.515258417 +0100 -@@ -32,4 +32,5 @@ - obj-$(CONFIG_JOYSTICK_XPAD) += xpad.o - obj-$(CONFIG_JOYSTICK_ZHENHUA) += zhenhua.o - obj-$(CONFIG_JOYSTICK_WALKERA0701) += walkera0701.o -+obj-$(CONFIG_JOYSTICK_RPISENSE) += rpisense-js.o - -diff -Nur linux-4.1.13.orig/drivers/input/joystick/rpisense-js.c linux-rpi/drivers/input/joystick/rpisense-js.c ---- linux-4.1.13.orig/drivers/input/joystick/rpisense-js.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/input/joystick/rpisense-js.c 2015-11-29 09:42:37.515258417 +0100 -@@ -0,0 +1,153 @@ -+/* -+ * Raspberry Pi Sense HAT joystick driver -+ * http://raspberrypi.org -+ * -+ * Copyright (C) 2015 Raspberry Pi -+ * -+ * Author: Serge Schneider -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ */ -+ -+#include -+ -+#include -+#include -+ -+struct rpisense *rpisense; -+unsigned char keymap[5] = {KEY_DOWN, KEY_RIGHT, KEY_UP, KEY_ENTER, KEY_LEFT,}; -+ -+static void keys_work_fn(struct work_struct *work) -+{ -+ int i; -+ static s32 prev_keys; -+ struct rpisense_js *rpisense_js = &rpisense->joystick; -+ s32 keys = rpisense_reg_read(rpisense, RPISENSE_KEYS); -+ s32 changes = keys ^ prev_keys; -+ -+ prev_keys = keys; -+ for (i = 0; i < 5; i++) { -+ if (changes & 1) { -+ input_report_key(rpisense_js->keys_dev, -+ keymap[i], keys & 1); -+ } -+ changes >>= 1; -+ keys >>= 1; -+ } -+ input_sync(rpisense_js->keys_dev); -+} -+ -+static irqreturn_t keys_irq_handler(int irq, void *pdev) -+{ -+ struct rpisense_js *rpisense_js = &rpisense->joystick; -+ -+ schedule_work(&rpisense_js->keys_work_s); -+ return IRQ_HANDLED; -+} -+ -+static int rpisense_js_probe(struct platform_device *pdev) -+{ -+ int ret; -+ int i; -+ struct rpisense_js *rpisense_js; -+ -+ rpisense = rpisense_get_dev(); -+ rpisense_js = &rpisense->joystick; -+ -+ INIT_WORK(&rpisense_js->keys_work_s, keys_work_fn); -+ -+ rpisense_js->keys_dev = input_allocate_device(); -+ if (!rpisense_js->keys_dev) { -+ dev_err(&pdev->dev, "Could not allocate input device.\n"); -+ return -ENOMEM; -+ } -+ -+ rpisense_js->keys_dev->evbit[0] = BIT_MASK(EV_KEY); -+ for (i = 0; i < ARRAY_SIZE(keymap); i++) { -+ set_bit(keymap[i], -+ rpisense_js->keys_dev->keybit); -+ } -+ -+ rpisense_js->keys_dev->name = "Raspberry Pi Sense HAT Joystick"; -+ rpisense_js->keys_dev->phys = "rpi-sense-joy/input0"; -+ rpisense_js->keys_dev->id.bustype = BUS_I2C; -+ rpisense_js->keys_dev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_REP); -+ rpisense_js->keys_dev->keycode = keymap; -+ rpisense_js->keys_dev->keycodesize = sizeof(unsigned char); -+ rpisense_js->keys_dev->keycodemax = ARRAY_SIZE(keymap); -+ -+ ret = input_register_device(rpisense_js->keys_dev); -+ if (ret) { -+ dev_err(&pdev->dev, "Could not register input device.\n"); -+ goto err_keys_alloc; -+ } -+ -+ ret = gpiod_direction_input(rpisense_js->keys_desc); -+ if (ret) { -+ dev_err(&pdev->dev, "Could not set keys-int direction.\n"); -+ goto err_keys_reg; -+ } -+ -+ rpisense_js->keys_irq = gpiod_to_irq(rpisense_js->keys_desc); -+ if (rpisense_js->keys_irq < 0) { -+ dev_err(&pdev->dev, "Could not determine keys-int IRQ.\n"); -+ ret = rpisense_js->keys_irq; -+ goto err_keys_reg; -+ } -+ -+ ret = devm_request_irq(&pdev->dev, rpisense_js->keys_irq, -+ keys_irq_handler, IRQF_TRIGGER_RISING, -+ "keys", &pdev->dev); -+ if (ret) { -+ dev_err(&pdev->dev, "IRQ request failed.\n"); -+ goto err_keys_reg; -+ } -+ return 0; -+err_keys_reg: -+ input_unregister_device(rpisense_js->keys_dev); -+err_keys_alloc: -+ input_free_device(rpisense_js->keys_dev); -+ return ret; -+} -+ -+static int rpisense_js_remove(struct platform_device *pdev) -+{ -+ struct rpisense_js *rpisense_js = &rpisense->joystick; -+ -+ input_unregister_device(rpisense_js->keys_dev); -+ input_free_device(rpisense_js->keys_dev); -+ return 0; -+} -+ -+#ifdef CONFIG_OF -+static const struct of_device_id rpisense_js_id[] = { -+ { .compatible = "rpi,rpi-sense-js" }, -+ { }, -+}; -+MODULE_DEVICE_TABLE(of, rpisense_js_id); -+#endif -+ -+static struct platform_device_id rpisense_js_device_id[] = { -+ { .name = "rpi-sense-js" }, -+ { }, -+}; -+MODULE_DEVICE_TABLE(platform, rpisense_js_device_id); -+ -+static struct platform_driver rpisense_js_driver = { -+ .probe = rpisense_js_probe, -+ .remove = rpisense_js_remove, -+ .driver = { -+ .name = "rpi-sense-js", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+module_platform_driver(rpisense_js_driver); -+ -+MODULE_DESCRIPTION("Raspberry Pi Sense HAT joystick driver"); -+MODULE_AUTHOR("Serge Schneider "); -+MODULE_LICENSE("GPL"); -diff -Nur linux-4.1.13.orig/drivers/input/touchscreen/ft6236.c linux-rpi/drivers/input/touchscreen/ft6236.c ---- linux-4.1.13.orig/drivers/input/touchscreen/ft6236.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/input/touchscreen/ft6236.c 2015-11-29 09:42:37.567254962 +0100 -@@ -0,0 +1,326 @@ -+/* -+ * FocalTech FT6236 TouchScreen driver. -+ * -+ * Copyright (c) 2010 Focal tech Ltd. -+ * -+ * This software is licensed under the terms of the GNU General Public -+ * License version 2, as published by the Free Software Foundation, and -+ * may be copied, distributed, and modified under those terms. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define FT6236_MAX_TOUCH_POINTS 2 -+ -+#define FT6236_REG_TH_GROUP 0x80 -+#define FT6236_REG_PERIODACTIVE 0x88 -+#define FT6236_REG_LIB_VER_H 0xa1 -+#define FT6236_REG_LIB_VER_L 0xa2 -+#define FT6236_REG_CIPHER 0xa3 -+#define FT6236_REG_FIRMID 0xa6 -+#define FT6236_REG_FOCALTECH_ID 0xa8 -+#define FT6236_REG_RELEASE_CODE_ID 0xaf -+ -+#define FT6236_EVENT_PRESS_DOWN 0 -+#define FT6236_EVENT_LIFT_UP 1 -+#define FT6236_EVENT_CONTACT 2 -+#define FT6236_EVENT_NO_EVENT 3 -+ -+struct ft6236_data { -+ struct i2c_client *client; -+ struct input_dev *input; -+ struct gpio_desc *reset_gpio; -+ u32 max_x; -+ u32 max_y; -+ bool invert_x; -+ bool invert_y; -+ bool swap_xy; -+}; -+ -+/* -+ * This struct is a touchpoint as stored in hardware. Note that the id, -+ * as well as the event, are stored in the upper nybble of the hi byte. -+ */ -+struct ft6236_touchpoint { -+ union { -+ u8 xhi; -+ u8 event; -+ }; -+ u8 xlo; -+ union { -+ u8 yhi; -+ u8 id; -+ }; -+ u8 ylo; -+ u8 weight; -+ u8 misc; -+} __packed; -+ -+/* This packet represents the register map as read from offset 0 */ -+struct ft6236_packet { -+ u8 dev_mode; -+ u8 gest_id; -+ u8 touches; -+ struct ft6236_touchpoint points[FT6236_MAX_TOUCH_POINTS]; -+} __packed; -+ -+static int ft6236_read(struct i2c_client *client, u8 reg, u8 len, void *data) -+{ -+ int error; -+ -+ error = i2c_smbus_read_i2c_block_data(client, reg, len, data); -+ if (error < 0) -+ return error; -+ -+ if (error != len) -+ return -EIO; -+ -+ return 0; -+} -+ -+static irqreturn_t ft6236_interrupt(int irq, void *dev_id) -+{ -+ struct ft6236_data *ft6236 = dev_id; -+ struct device *dev = &ft6236->client->dev; -+ struct input_dev *input = ft6236->input; -+ struct ft6236_packet buf; -+ u8 touches; -+ int i, error; -+ -+ error = ft6236_read(ft6236->client, 0, sizeof(buf), &buf); -+ if (error) { -+ dev_err(dev, "read touchdata failed %d\n", error); -+ return IRQ_HANDLED; -+ } -+ -+ touches = buf.touches & 0xf; -+ if (touches > FT6236_MAX_TOUCH_POINTS) { -+ dev_dbg(dev, -+ "%d touch points reported, only %d are supported\n", -+ touches, FT6236_MAX_TOUCH_POINTS); -+ touches = FT6236_MAX_TOUCH_POINTS; -+ } -+ -+ for (i = 0; i < touches; i++) { -+ struct ft6236_touchpoint *point = &buf.points[i]; -+ u16 x = ((point->xhi & 0xf) << 8) | buf.points[i].xlo; -+ u16 y = ((point->yhi & 0xf) << 8) | buf.points[i].ylo; -+ u8 event = point->event >> 6; -+ u8 id = point->id >> 4; -+ bool act = (event == FT6236_EVENT_PRESS_DOWN || -+ event == FT6236_EVENT_CONTACT); -+ -+ input_mt_slot(input, id); -+ input_mt_report_slot_state(input, MT_TOOL_FINGER, act); -+ if (!act) -+ continue; -+ -+ if (ft6236->invert_x) -+ x = ft6236->max_x - x; -+ -+ if (ft6236->invert_y) -+ y = ft6236->max_y - y; -+ -+ if (ft6236->swap_xy) { -+ input_report_abs(input, ABS_MT_POSITION_X, y); -+ input_report_abs(input, ABS_MT_POSITION_Y, x); -+ } else { -+ input_report_abs(input, ABS_MT_POSITION_X, x); -+ input_report_abs(input, ABS_MT_POSITION_Y, y); -+ } -+ } -+ -+ input_mt_sync_frame(input); -+ input_sync(input); -+ -+ return IRQ_HANDLED; -+} -+ -+static u8 ft6236_debug_read_byte(struct ft6236_data *ft6236, u8 reg) -+{ -+ struct i2c_client *client = ft6236->client; -+ u8 val = 0; -+ int error; -+ -+ error = ft6236_read(client, reg, 1, &val); -+ if (error) -+ dev_dbg(&client->dev, -+ "error reading register 0x%02x: %d\n", reg, error); -+ -+ return val; -+} -+ -+static void ft6236_debug_info(struct ft6236_data *ft6236) -+{ -+ struct device *dev = &ft6236->client->dev; -+ -+ dev_dbg(dev, "Touch threshold is %d\n", -+ ft6236_debug_read_byte(ft6236, FT6236_REG_TH_GROUP) * 4); -+ dev_dbg(dev, "Report rate is %dHz\n", -+ ft6236_debug_read_byte(ft6236, FT6236_REG_PERIODACTIVE) * 10); -+ dev_dbg(dev, "Firmware library version 0x%02x%02x\n", -+ ft6236_debug_read_byte(ft6236, FT6236_REG_LIB_VER_H), -+ ft6236_debug_read_byte(ft6236, FT6236_REG_LIB_VER_L)); -+ dev_dbg(dev, "Firmware version 0x%02x\n", -+ ft6236_debug_read_byte(ft6236, FT6236_REG_FIRMID)); -+ dev_dbg(dev, "Chip vendor ID 0x%02x\n", -+ ft6236_debug_read_byte(ft6236, FT6236_REG_CIPHER)); -+ dev_dbg(dev, "CTPM vendor ID 0x%02x\n", -+ ft6236_debug_read_byte(ft6236, FT6236_REG_FOCALTECH_ID)); -+ dev_dbg(dev, "Release code version 0x%02x\n", -+ ft6236_debug_read_byte(ft6236, FT6236_REG_RELEASE_CODE_ID)); -+} -+ -+static void ft6236_reset(struct ft6236_data *ft6236) -+{ -+ if (!ft6236->reset_gpio) -+ return; -+ -+ gpiod_set_value_cansleep(ft6236->reset_gpio, 1); -+ usleep_range(5000, 20000); -+ gpiod_set_value_cansleep(ft6236->reset_gpio, 0); -+ msleep(300); -+} -+ -+static int ft6236_probe(struct i2c_client *client, -+ const struct i2c_device_id *id) -+{ -+ struct device *dev = &client->dev; -+ struct ft6236_data *ft6236; -+ struct input_dev *input; -+ u32 fuzz_x = 0, fuzz_y = 0; -+ u8 val; -+ int error; -+ -+ if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) -+ return -ENXIO; -+ -+ if (!client->irq) { -+ dev_err(dev, "irq is missing\n"); -+ return -EINVAL; -+ } -+ -+ ft6236 = devm_kzalloc(dev, sizeof(*ft6236), GFP_KERNEL); -+ if (!ft6236) -+ return -ENOMEM; -+ -+ ft6236->client = client; -+ ft6236->reset_gpio = devm_gpiod_get_optional(dev, "reset", -+ GPIOD_OUT_LOW); -+ if (IS_ERR(ft6236->reset_gpio)) { -+ error = PTR_ERR(ft6236->reset_gpio); -+ if (error != -EPROBE_DEFER) -+ dev_err(dev, "error getting reset gpio: %d\n", error); -+ return error; -+ } -+ -+ ft6236_reset(ft6236); -+ -+ /* verify that the controller is present */ -+ error = ft6236_read(client, 0x00, 1, &val); -+ if (error) { -+ dev_err(dev, "failed to read from controller: %d\n", error); -+ return error; -+ } -+ -+ ft6236_debug_info(ft6236); -+ -+ input = devm_input_allocate_device(dev); -+ if (!input) -+ return -ENOMEM; -+ -+ ft6236->input = input; -+ input->name = client->name; -+ input->id.bustype = BUS_I2C; -+ -+ if (device_property_read_u32(dev, "touchscreen-size-x", -+ &ft6236->max_x) || -+ device_property_read_u32(dev, "touchscreen-size-y", -+ &ft6236->max_y)) { -+ dev_err(dev, "touchscreen-size-x and/or -y missing\n"); -+ return -EINVAL; -+ } -+ -+ device_property_read_u32(dev, "touchscreen-fuzz-x", &fuzz_x); -+ device_property_read_u32(dev, "touchscreen-fuzz-y", &fuzz_y); -+ ft6236->invert_x = device_property_read_bool(dev, -+ "touchscreen-inverted-x"); -+ ft6236->invert_y = device_property_read_bool(dev, -+ "touchscreen-inverted-y"); -+ ft6236->swap_xy = device_property_read_bool(dev, -+ "touchscreen-swapped-x-y"); -+ -+ if (ft6236->swap_xy) { -+ input_set_abs_params(input, ABS_MT_POSITION_X, 0, -+ ft6236->max_y, fuzz_y, 0); -+ input_set_abs_params(input, ABS_MT_POSITION_Y, 0, -+ ft6236->max_x, fuzz_x, 0); -+ } else { -+ input_set_abs_params(input, ABS_MT_POSITION_X, 0, -+ ft6236->max_x, fuzz_x, 0); -+ input_set_abs_params(input, ABS_MT_POSITION_Y, 0, -+ ft6236->max_y, fuzz_y, 0); -+ } -+ -+ error = input_mt_init_slots(input, FT6236_MAX_TOUCH_POINTS, -+ INPUT_MT_DIRECT | INPUT_MT_DROP_UNUSED); -+ if (error) -+ return error; -+ -+ error = devm_request_threaded_irq(dev, client->irq, NULL, -+ ft6236_interrupt, IRQF_ONESHOT, -+ client->name, ft6236); -+ if (error) { -+ dev_err(dev, "request irq %d failed: %d\n", client->irq, error); -+ return error; -+ } -+ -+ error = input_register_device(input); -+ if (error) { -+ dev_err(dev, "failed to register input device: %d\n", error); -+ return error; -+ } -+ -+ return 0; -+} -+ -+#ifdef CONFIG_OF -+static const struct of_device_id ft6236_of_match[] = { -+ { .compatible = "focaltech,ft6236", }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, ft6236_of_match); -+#endif -+ -+static const struct i2c_device_id ft6236_id[] = { -+ { "ft6236", }, -+ { } -+}; -+MODULE_DEVICE_TABLE(i2c, ft6236_id); -+ -+static struct i2c_driver ft6236_driver = { -+ .driver = { -+ .name = "ft6236", -+ .of_match_table = of_match_ptr(ft6236_of_match), -+ }, -+ .probe = ft6236_probe, -+ .id_table = ft6236_id, -+}; -+module_i2c_driver(ft6236_driver); -+ -+MODULE_AUTHOR("Sean Cross "); -+MODULE_AUTHOR("Noralf Trønnes "); -+MODULE_DESCRIPTION("FocalTech FT6236 TouchScreen driver"); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-4.1.13.orig/drivers/input/touchscreen/Kconfig linux-rpi/drivers/input/touchscreen/Kconfig ---- linux-4.1.13.orig/drivers/input/touchscreen/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/input/touchscreen/Kconfig 2015-11-29 09:42:37.563255228 +0100 -@@ -295,6 +295,19 @@ - To compile this driver as a module, choose M here: the - module will be called egalax_ts. - -+config TOUCHSCREEN_FT6236 -+ tristate "FT6236 I2C touchscreen" -+ depends on I2C -+ depends on GPIOLIB || COMPILE_TEST -+ help -+ Say Y here to enable support for the I2C connected FT6x06 and -+ FT6x36 family of capacitive touchscreen drivers. -+ -+ If unsure, say N. -+ -+ To compile this driver as a module, choose M here: the -+ module will be called ft6236. -+ - config TOUCHSCREEN_FUJITSU - tristate "Fujitsu serial touchscreen" - select SERIO -@@ -583,6 +596,13 @@ - To compile this driver as a module, choose M here: the - module will be called edt-ft5x06. - -+config TOUCHSCREEN_RPI_FT5406 -+ tristate "Raspberry Pi FT5406 driver" -+ depends on RASPBERRYPI_FIRMWARE -+ help -+ Say Y here to enable the Raspberry Pi memory based FT5406 device -+ -+ - config TOUCHSCREEN_MIGOR - tristate "Renesas MIGO-R touchscreen" - depends on SH_MIGOR && I2C -diff -Nur linux-4.1.13.orig/drivers/input/touchscreen/Makefile linux-rpi/drivers/input/touchscreen/Makefile ---- linux-4.1.13.orig/drivers/input/touchscreen/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/input/touchscreen/Makefile 2015-11-29 09:42:37.563255228 +0100 -@@ -29,12 +29,14 @@ - obj-$(CONFIG_TOUCHSCREEN_DA9052) += da9052_tsi.o - obj-$(CONFIG_TOUCHSCREEN_DYNAPRO) += dynapro.o - obj-$(CONFIG_TOUCHSCREEN_EDT_FT5X06) += edt-ft5x06.o -+obj-$(CONFIG_TOUCHSCREEN_RPI_FT5406) += rpi-ft5406.o - obj-$(CONFIG_TOUCHSCREEN_HAMPSHIRE) += hampshire.o - obj-$(CONFIG_TOUCHSCREEN_GUNZE) += gunze.o - obj-$(CONFIG_TOUCHSCREEN_EETI) += eeti_ts.o - obj-$(CONFIG_TOUCHSCREEN_ELAN) += elants_i2c.o - obj-$(CONFIG_TOUCHSCREEN_ELO) += elo.o - obj-$(CONFIG_TOUCHSCREEN_EGALAX) += egalax_ts.o -+obj-$(CONFIG_TOUCHSCREEN_FT6236) += ft6236.o - obj-$(CONFIG_TOUCHSCREEN_FUJITSU) += fujitsu_ts.o - obj-$(CONFIG_TOUCHSCREEN_GOODIX) += goodix.o - obj-$(CONFIG_TOUCHSCREEN_ILI210X) += ili210x.o -diff -Nur linux-4.1.13.orig/drivers/input/touchscreen/rpi-ft5406.c linux-rpi/drivers/input/touchscreen/rpi-ft5406.c ---- linux-4.1.13.orig/drivers/input/touchscreen/rpi-ft5406.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/input/touchscreen/rpi-ft5406.c 2015-11-29 09:42:37.571254696 +0100 -@@ -0,0 +1,246 @@ -+/* -+ * Driver for memory based ft5406 touchscreen -+ * -+ * Copyright (C) 2015 Raspberry Pi -+ * -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define MAXIMUM_SUPPORTED_POINTS 10 -+struct ft5406_regs { -+ uint8_t device_mode; -+ uint8_t gesture_id; -+ uint8_t num_points; -+ struct ft5406_touch { -+ uint8_t xh; -+ uint8_t xl; -+ uint8_t yh; -+ uint8_t yl; -+ uint8_t res1; -+ uint8_t res2; -+ } point[MAXIMUM_SUPPORTED_POINTS]; -+}; -+ -+#define SCREEN_WIDTH 800 -+#define SCREEN_HEIGHT 480 -+ -+struct ft5406 { -+ struct platform_device * pdev; -+ struct input_dev * input_dev; -+ void __iomem * ts_base; -+ struct ft5406_regs * regs; -+ struct task_struct * thread; -+}; -+ -+/* Thread to poll for touchscreen events -+ * -+ * This thread polls the memory based register copy of the ft5406 registers -+ * using the number of points register to know whether the copy has been -+ * updated (we write 99 to the memory copy, the GPU will write between -+ * 0 - 10 points) -+ */ -+static int ft5406_thread(void *arg) -+{ -+ struct ft5406 *ts = (struct ft5406 *) arg; -+ struct ft5406_regs regs; -+ int known_ids = 0; -+ -+ while(!kthread_should_stop()) -+ { -+ // 60fps polling -+ msleep_interruptible(17); -+ memcpy_fromio(®s, ts->regs, sizeof(*ts->regs)); -+ writel(99, &ts->regs->num_points); -+ // Do not output if theres no new information (num_points is 99) -+ // or we have no touch points and don't need to release any -+ if(!(regs.num_points == 99 || (regs.num_points == 0 && known_ids == 0))) -+ { -+ int i; -+ int modified_ids = 0, released_ids; -+ for(i = 0; i < regs.num_points; i++) -+ { -+ int x = (((int) regs.point[i].xh & 0xf) << 8) + regs.point[i].xl; -+ int y = (((int) regs.point[i].yh & 0xf) << 8) + regs.point[i].yl; -+ int touchid = (regs.point[i].yh >> 4) & 0xf; -+ -+ modified_ids |= 1 << touchid; -+ -+ if(!((1 << touchid) & known_ids)) -+ dev_dbg(&ts->pdev->dev, "x = %d, y = %d, touchid = %d\n", x, y, touchid); -+ -+ input_mt_slot(ts->input_dev, touchid); -+ input_mt_report_slot_state(ts->input_dev, MT_TOOL_FINGER, 1); -+ -+ input_report_abs(ts->input_dev, ABS_MT_POSITION_X, x); -+ input_report_abs(ts->input_dev, ABS_MT_POSITION_Y, y); -+ -+ } -+ -+ released_ids = known_ids & ~modified_ids; -+ for(i = 0; released_ids && i < MAXIMUM_SUPPORTED_POINTS; i++) -+ { -+ if(released_ids & (1<pdev->dev, "Released %d, known = %x modified = %x\n", i, known_ids, modified_ids); -+ input_mt_slot(ts->input_dev, i); -+ input_mt_report_slot_state(ts->input_dev, MT_TOOL_FINGER, 0); -+ modified_ids &= ~(1 << i); -+ } -+ } -+ known_ids = modified_ids; -+ -+ input_mt_report_pointer_emulation(ts->input_dev, true); -+ input_sync(ts->input_dev); -+ } -+ -+ } -+ -+ return 0; -+} -+ -+static int ft5406_probe(struct platform_device *pdev) -+{ -+ int ret; -+ struct input_dev * input_dev = input_allocate_device(); -+ struct ft5406 * ts; -+ struct device_node *fw_node; -+ struct rpi_firmware *fw; -+ u32 touchbuf; -+ -+ dev_info(&pdev->dev, "Probing device\n"); -+ -+ fw_node = of_parse_phandle(pdev->dev.of_node, "firmware", 0); -+ if (!fw_node) { -+ dev_err(&pdev->dev, "Missing firmware node\n"); -+ return -ENOENT; -+ } -+ -+ fw = rpi_firmware_get(fw_node); -+ if (!fw) -+ return -EPROBE_DEFER; -+ -+ ret = rpi_firmware_property(fw, RPI_FIRMWARE_FRAMEBUFFER_GET_TOUCHBUF, -+ &touchbuf, sizeof(touchbuf)); -+ if (ret) { -+ dev_err(&pdev->dev, "Failed to get touch buffer\n"); -+ return ret; -+ } -+ -+ if (!touchbuf) { -+ dev_err(&pdev->dev, "Touchscreen not detected\n"); -+ return -ENODEV; -+ } -+ -+ dev_dbg(&pdev->dev, "Got TS buffer 0x%x\n", touchbuf); -+ -+ ts = kzalloc(sizeof(struct ft5406), GFP_KERNEL); -+ -+ if (!ts || !input_dev) { -+ ret = -ENOMEM; -+ dev_err(&pdev->dev, "Failed to allocate memory\n"); -+ return ret; -+ } -+ ts->input_dev = input_dev; -+ platform_set_drvdata(pdev, ts); -+ ts->pdev = pdev; -+ -+ input_dev->name = "FT5406 memory based driver"; -+ -+ __set_bit(EV_KEY, input_dev->evbit); -+ __set_bit(EV_SYN, input_dev->evbit); -+ __set_bit(EV_ABS, input_dev->evbit); -+ -+ input_set_abs_params(input_dev, ABS_MT_POSITION_X, 0, -+ SCREEN_WIDTH, 0, 0); -+ input_set_abs_params(input_dev, ABS_MT_POSITION_Y, 0, -+ SCREEN_HEIGHT, 0, 0); -+ -+ input_mt_init_slots(input_dev, MAXIMUM_SUPPORTED_POINTS, INPUT_MT_DIRECT); -+ -+ input_set_drvdata(input_dev, ts); -+ -+ ret = input_register_device(input_dev); -+ if (ret) { -+ dev_err(&pdev->dev, "could not register input device, %d\n", -+ ret); -+ return ret; -+ } -+ -+ // mmap the physical memory -+ touchbuf &= ~0xc0000000; -+ ts->ts_base = ioremap(touchbuf, sizeof(*ts->regs)); -+ if(ts->ts_base == NULL) -+ { -+ dev_err(&pdev->dev, "Failed to map physical address\n"); -+ input_unregister_device(input_dev); -+ kzfree(ts); -+ return -ENOMEM; -+ } -+ -+ ts->regs = (struct ft5406_regs *) ts->ts_base; -+ -+ // create thread to poll the touch events -+ ts->thread = kthread_run(ft5406_thread, ts, "ft5406"); -+ if(ts->thread == NULL) -+ { -+ dev_err(&pdev->dev, "Failed to create kernel thread"); -+ iounmap(ts->ts_base); -+ input_unregister_device(input_dev); -+ kzfree(ts); -+ } -+ -+ return 0; -+} -+ -+static int ft5406_remove(struct platform_device *pdev) -+{ -+ struct ft5406 *ts = (struct ft5406 *) platform_get_drvdata(pdev); -+ -+ dev_info(&pdev->dev, "Removing rpi-ft5406\n"); -+ -+ kthread_stop(ts->thread); -+ iounmap(ts->ts_base); -+ input_unregister_device(ts->input_dev); -+ kzfree(ts); -+ -+ return 0; -+} -+ -+static const struct of_device_id ft5406_match[] = { -+ { .compatible = "rpi,rpi-ft5406", }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, ft5406_match); -+ -+static struct platform_driver ft5406_driver = { -+ .driver = { -+ .name = "rpi-ft5406", -+ .owner = THIS_MODULE, -+ .of_match_table = ft5406_match, -+ }, -+ .probe = ft5406_probe, -+ .remove = ft5406_remove, -+}; -+ -+module_platform_driver(ft5406_driver); -+ -+MODULE_AUTHOR("Gordon Hollingworth"); -+MODULE_DESCRIPTION("Touchscreen driver for memory based FT5406"); -+MODULE_LICENSE("GPL"); -diff -Nur linux-4.1.13.orig/drivers/irqchip/irq-bcm2835.c linux-rpi/drivers/irqchip/irq-bcm2835.c ---- linux-4.1.13.orig/drivers/irqchip/irq-bcm2835.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/irqchip/irq-bcm2835.c 2015-11-29 09:42:37.583253899 +0100 -@@ -56,7 +56,7 @@ - #include "irqchip.h" - - /* Put the bank and irq (32 bits) into the hwirq */ --#define MAKE_HWIRQ(b, n) ((b << 5) | (n)) -+#define MAKE_HWIRQ(b, n) (((b) << 5) | (n)) - #define HWIRQ_BANK(i) (i >> 5) - #define HWIRQ_BIT(i) BIT(i & 0x1f) - -@@ -72,9 +72,13 @@ - | SHORTCUT1_MASK | SHORTCUT2_MASK) - - #define REG_FIQ_CONTROL 0x0c -+#define REG_FIQ_ENABLE 0x80 -+#define REG_FIQ_DISABLE 0 - - #define NR_BANKS 3 - #define IRQS_PER_BANK 32 -+#define NUMBER_IRQS MAKE_HWIRQ(NR_BANKS, 0) -+#define FIQ_START (NR_IRQS_BANK0 + MAKE_HWIRQ(NR_BANKS - 1, 0)) - - static int reg_pending[] __initconst = { 0x00, 0x04, 0x08 }; - static int reg_enable[] __initconst = { 0x18, 0x10, 0x14 }; -@@ -98,14 +102,38 @@ - static void __exception_irq_entry bcm2835_handle_irq( - struct pt_regs *regs); - -+static inline unsigned int hwirq_to_fiq(unsigned long hwirq) -+{ -+ hwirq -= NUMBER_IRQS; -+ /* -+ * The hwirq numbering used in this driver is: -+ * BASE (0-7) GPU1 (32-63) GPU2 (64-95). -+ * This differ from the one used in the FIQ register: -+ * GPU1 (0-31) GPU2 (32-63) BASE (64-71) -+ */ -+ if (hwirq >= 32) -+ return hwirq - 32; -+ -+ return hwirq + 64; -+} -+ - static void armctrl_mask_irq(struct irq_data *d) - { -- writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]); -+ if (d->hwirq >= NUMBER_IRQS) -+ writel_relaxed(REG_FIQ_DISABLE, intc.base + REG_FIQ_CONTROL); -+ else -+ writel_relaxed(HWIRQ_BIT(d->hwirq), -+ intc.disable[HWIRQ_BANK(d->hwirq)]); - } - - static void armctrl_unmask_irq(struct irq_data *d) - { -- writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]); -+ if (d->hwirq >= NUMBER_IRQS) -+ writel_relaxed(REG_FIQ_ENABLE | hwirq_to_fiq(d->hwirq), -+ intc.base + REG_FIQ_CONTROL); -+ else -+ writel_relaxed(HWIRQ_BIT(d->hwirq), -+ intc.enable[HWIRQ_BANK(d->hwirq)]); - } - - static struct irq_chip armctrl_chip = { -@@ -150,8 +178,9 @@ - panic("%s: unable to map IC registers\n", - node->full_name); - -- intc.domain = irq_domain_add_linear(node, MAKE_HWIRQ(NR_BANKS, 0), -- &armctrl_ops, NULL); -+ intc.base = base; -+ intc.domain = irq_domain_add_linear(node, NUMBER_IRQS * 2, -+ &armctrl_ops, NULL); - if (!intc.domain) - panic("%s: unable to create IRQ domain\n", node->full_name); - -@@ -168,8 +197,20 @@ - set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); - } - } -- - set_handle_irq(bcm2835_handle_irq); -+ -+ /* Make a duplicate irq range which is used to enable FIQ */ -+ for (b = 0; b < NR_BANKS; b++) { -+ for (i = 0; i < bank_irqs[b]; i++) { -+ irq = irq_create_mapping(intc.domain, -+ MAKE_HWIRQ(b, i) + NUMBER_IRQS); -+ BUG_ON(irq <= 0); -+ irq_set_chip(irq, &armctrl_chip); -+ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); -+ } -+ } -+ init_FIQ(FIQ_START); -+ - return 0; - } - -diff -Nur linux-4.1.13.orig/drivers/leds/leds-gpio.c linux-rpi/drivers/leds/leds-gpio.c ---- linux-4.1.13.orig/drivers/leds/leds-gpio.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/leds/leds-gpio.c 2015-11-29 09:42:37.639250178 +0100 -@@ -41,6 +41,13 @@ - led_dat->platform_gpio_blink_set(led_dat->gpiod, - led_dat->new_level, NULL, NULL); - led_dat->blinking = 0; -+ } else if (led_dat->cdev.flags & SET_GPIO_INPUT) { -+ gpiod_direction_input(led_dat->gpiod); -+ led_dat->cdev.flags &= ~SET_GPIO_INPUT; -+ } -+ else if (led_dat->cdev.flags & SET_GPIO_OUTPUT) { -+ gpiod_direction_output(led_dat->gpiod, led_dat->new_level); -+ led_dat->cdev.flags &= ~SET_GPIO_OUTPUT; - } else - gpiod_set_value_cansleep(led_dat->gpiod, led_dat->new_level); - } -@@ -61,7 +68,8 @@ - * seem to have a reliable way to know if we're already in one; so - * let's just assume the worst. - */ -- if (led_dat->can_sleep) { -+ if (led_dat->can_sleep || -+ (led_dat->cdev.flags & (SET_GPIO_INPUT | SET_GPIO_OUTPUT) )) { - led_dat->new_level = level; - schedule_work(&led_dat->work); - } else { -@@ -74,6 +82,13 @@ - } - } - -+static enum led_brightness gpio_led_get(struct led_classdev *led_cdev) -+{ -+ struct gpio_led_data *led_dat = -+ container_of(led_cdev, struct gpio_led_data, cdev); -+ return gpiod_get_value_cansleep(led_dat->gpiod) ? LED_FULL : LED_OFF; -+} -+ - static int gpio_blink_set(struct led_classdev *led_cdev, - unsigned long *delay_on, unsigned long *delay_off) - { -@@ -130,6 +145,7 @@ - led_dat->cdev.blink_set = gpio_blink_set; - } - led_dat->cdev.brightness_set = gpio_led_set; -+ led_dat->cdev.brightness_get = gpio_led_get; - if (template->default_state == LEDS_GPIO_DEFSTATE_KEEP) - state = !!gpiod_get_value_cansleep(led_dat->gpiod); - else -diff -Nur linux-4.1.13.orig/drivers/leds/trigger/Kconfig linux-rpi/drivers/leds/trigger/Kconfig ---- linux-4.1.13.orig/drivers/leds/trigger/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/leds/trigger/Kconfig 2015-11-29 09:42:37.643249912 +0100 -@@ -108,4 +108,11 @@ - This enables direct flash/torch on/off by the driver, kernel space. - If unsure, say Y. - -+config LEDS_TRIGGER_INPUT -+ tristate "LED Input Trigger" -+ depends on LEDS_TRIGGERS -+ help -+ This allows the GPIOs assigned to be LEDs to be initialised to inputs. -+ If unsure, say Y. -+ - endif # LEDS_TRIGGERS -diff -Nur linux-4.1.13.orig/drivers/leds/trigger/ledtrig-input.c linux-rpi/drivers/leds/trigger/ledtrig-input.c ---- linux-4.1.13.orig/drivers/leds/trigger/ledtrig-input.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/leds/trigger/ledtrig-input.c 2015-11-29 09:42:37.643249912 +0100 -@@ -0,0 +1,54 @@ -+/* -+ * Set LED GPIO to Input "Trigger" -+ * -+ * Copyright 2015 Phil Elwell -+ * -+ * Based on Nick Forbes's ledtrig-default-on.c. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "../leds.h" -+ -+static void input_trig_activate(struct led_classdev *led_cdev) -+{ -+ led_cdev->flags |= SET_GPIO_INPUT; -+ led_set_brightness_async(led_cdev, 0); -+} -+ -+static void input_trig_deactivate(struct led_classdev *led_cdev) -+{ -+ led_cdev->flags |= SET_GPIO_OUTPUT; -+ led_set_brightness_async(led_cdev, 0); -+} -+ -+static struct led_trigger input_led_trigger = { -+ .name = "input", -+ .activate = input_trig_activate, -+ .deactivate = input_trig_deactivate, -+}; -+ -+static int __init input_trig_init(void) -+{ -+ return led_trigger_register(&input_led_trigger); -+} -+ -+static void __exit input_trig_exit(void) -+{ -+ led_trigger_unregister(&input_led_trigger); -+} -+ -+module_init(input_trig_init); -+module_exit(input_trig_exit); -+ -+MODULE_AUTHOR("Phil Elwell "); -+MODULE_DESCRIPTION("Set LED GPIO to Input \"trigger\""); -+MODULE_LICENSE("GPL"); -diff -Nur linux-4.1.13.orig/drivers/leds/trigger/Makefile linux-rpi/drivers/leds/trigger/Makefile ---- linux-4.1.13.orig/drivers/leds/trigger/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/leds/trigger/Makefile 2015-11-29 09:42:37.643249912 +0100 -@@ -8,3 +8,4 @@ - obj-$(CONFIG_LEDS_TRIGGER_DEFAULT_ON) += ledtrig-default-on.o - obj-$(CONFIG_LEDS_TRIGGER_TRANSIENT) += ledtrig-transient.o - obj-$(CONFIG_LEDS_TRIGGER_CAMERA) += ledtrig-camera.o -+obj-$(CONFIG_LEDS_TRIGGER_INPUT) += ledtrig-input.o -diff -Nur linux-4.1.13.orig/drivers/mailbox/bcm2835-mailbox.c linux-rpi/drivers/mailbox/bcm2835-mailbox.c ---- linux-4.1.13.orig/drivers/mailbox/bcm2835-mailbox.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/mailbox/bcm2835-mailbox.c 2015-11-29 09:42:37.651249381 +0100 -@@ -0,0 +1,231 @@ -+/* -+ * Copyright (C) 2010,2015 Broadcom -+ * Copyright (C) 2013-2014 Lubomir Rintel -+ * Copyright (C) 2013 Craig McGeachie -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * This device provides a mechanism for writing to the mailboxes, -+ * that are shared between the ARM and the VideoCore processor -+ * -+ * Parts of the driver are based on: -+ * - arch/arm/mach-bcm2708/vcio.c file written by Gray Girling that was -+ * obtained from branch "rpi-3.6.y" of git://github.com/raspberrypi/ -+ * linux.git -+ * - drivers/mailbox/bcm2835-ipc.c by Lubomir Rintel at -+ * https://github.com/hackerspace/rpi-linux/blob/lr-raspberry-pi/drivers/ -+ * mailbox/bcm2835-ipc.c -+ * - documentation available on the following web site: -+ * https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* Mailboxes */ -+#define ARM_0_MAIL0 0x00 -+#define ARM_0_MAIL1 0x20 -+ -+/* -+ * Mailbox registers. We basically only support mailbox 0 & 1. We -+ * deliver to the VC in mailbox 1, it delivers to us in mailbox 0. See -+ * BCM2835-ARM-Peripherals.pdf section 1.3 for an explanation about -+ * the placement of memory barriers. -+ */ -+#define MAIL0_RD (ARM_0_MAIL0 + 0x00) -+#define MAIL0_POL (ARM_0_MAIL0 + 0x10) -+#define MAIL0_STA (ARM_0_MAIL0 + 0x18) -+#define MAIL0_CNF (ARM_0_MAIL0 + 0x1C) -+#define MAIL1_WRT (ARM_0_MAIL1 + 0x00) -+#define MAIL1_STA (ARM_0_MAIL1 + 0x18) -+ -+/* On ARCH_BCM270x these come through (arm_control.h ) */ -+#ifndef ARM_MS_FULL -+/* Status register: FIFO state. */ -+#define ARM_MS_FULL BIT(31) -+#define ARM_MS_EMPTY BIT(30) -+ -+/* Configuration register: Enable interrupts. */ -+#define ARM_MC_IHAVEDATAIRQEN BIT(0) -+#endif -+ -+struct bcm2835_mbox { -+ void __iomem *regs; -+ spinlock_t lock; -+ struct mbox_controller controller; -+}; -+ -+static struct bcm2835_mbox *bcm2835_link_mbox(struct mbox_chan *link) -+{ -+ return container_of(link->mbox, struct bcm2835_mbox, controller); -+} -+ -+static irqreturn_t bcm2835_mbox_irq(int irq, void *dev_id) -+{ -+ struct bcm2835_mbox *mbox = dev_id; -+ struct device *dev = mbox->controller.dev; -+ struct mbox_chan *link = &mbox->controller.chans[0]; -+ -+ while (!(readl(mbox->regs + MAIL0_STA) & ARM_MS_EMPTY)) { -+ u32 msg = readl(mbox->regs + MAIL0_RD); -+ dev_dbg(dev, "Reply 0x%08X\n", msg); -+ mbox_chan_received_data(link, &msg); -+ } -+ return IRQ_HANDLED; -+} -+ -+static int bcm2835_send_data(struct mbox_chan *link, void *data) -+{ -+ struct bcm2835_mbox *mbox = bcm2835_link_mbox(link); -+ u32 msg = *(u32 *)data; -+ -+ spin_lock(&mbox->lock); -+ writel(msg, mbox->regs + MAIL1_WRT); -+ dev_dbg(mbox->controller.dev, "Request 0x%08X\n", msg); -+ spin_unlock(&mbox->lock); -+ return 0; -+} -+ -+static int bcm2835_startup(struct mbox_chan *link) -+{ -+ struct bcm2835_mbox *mbox = bcm2835_link_mbox(link); -+ -+ /* Enable the interrupt on data reception */ -+ writel(ARM_MC_IHAVEDATAIRQEN, mbox->regs + MAIL0_CNF); -+ -+ return 0; -+} -+ -+static void bcm2835_shutdown(struct mbox_chan *link) -+{ -+ struct bcm2835_mbox *mbox = bcm2835_link_mbox(link); -+ -+ writel(0, mbox->regs + MAIL0_CNF); -+} -+ -+static bool bcm2835_last_tx_done(struct mbox_chan *link) -+{ -+ struct bcm2835_mbox *mbox = bcm2835_link_mbox(link); -+ bool ret; -+ -+ spin_lock(&mbox->lock); -+ ret = !(readl(mbox->regs + MAIL1_STA) & ARM_MS_FULL); -+ spin_unlock(&mbox->lock); -+ return ret; -+} -+ -+static const struct mbox_chan_ops bcm2835_mbox_chan_ops = { -+ .send_data = bcm2835_send_data, -+ .startup = bcm2835_startup, -+ .shutdown = bcm2835_shutdown, -+ .last_tx_done = bcm2835_last_tx_done -+}; -+ -+static struct mbox_chan *bcm2835_mbox_index_xlate(struct mbox_controller *mbox, -+ const struct of_phandle_args *sp) -+{ -+ if (sp->args_count != 0) -+ return NULL; -+ -+ return &mbox->chans[0]; -+} -+ -+static int bcm2835_mbox_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ int ret = 0; -+ struct resource *iomem; -+ struct bcm2835_mbox *mbox; -+ -+ mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL); -+ if (mbox == NULL) -+ return -ENOMEM; -+ spin_lock_init(&mbox->lock); -+ -+ ret = devm_request_irq(dev, platform_get_irq(pdev, 0), -+ bcm2835_mbox_irq, 0, dev_name(dev), mbox); -+ if (ret) { -+ dev_err(dev, "Failed to register a mailbox IRQ handler: %d\n", -+ ret); -+ return -ENODEV; -+ } -+ -+ iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ mbox->regs = devm_ioremap_resource(&pdev->dev, iomem); -+ if (IS_ERR(mbox->regs)) { -+ ret = PTR_ERR(mbox->regs); -+ dev_err(&pdev->dev, "Failed to remap mailbox regs: %d\n", ret); -+ return ret; -+ } -+ -+ mbox->controller.txdone_poll = true; -+ mbox->controller.txpoll_period = 5; -+ mbox->controller.ops = &bcm2835_mbox_chan_ops; -+ mbox->controller.of_xlate = &bcm2835_mbox_index_xlate; -+ mbox->controller.dev = dev; -+ mbox->controller.num_chans = 1; -+ mbox->controller.chans = devm_kzalloc(dev, -+ sizeof(*mbox->controller.chans), GFP_KERNEL); -+ if (!mbox->controller.chans) -+ return -ENOMEM; -+ -+ ret = mbox_controller_register(&mbox->controller); -+ if (ret) -+ return ret; -+ -+ platform_set_drvdata(pdev, mbox); -+ dev_info(dev, "mailbox enabled\n"); -+ -+ return ret; -+} -+ -+static int bcm2835_mbox_remove(struct platform_device *pdev) -+{ -+ struct bcm2835_mbox *mbox = platform_get_drvdata(pdev); -+ mbox_controller_unregister(&mbox->controller); -+ return 0; -+} -+ -+static const struct of_device_id bcm2835_mbox_of_match[] = { -+ { .compatible = "brcm,bcm2835-mbox", }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, bcm2835_mbox_of_match); -+ -+static struct platform_driver bcm2835_mbox_driver = { -+ .driver = { -+ .name = "bcm2835-mbox", -+ .owner = THIS_MODULE, -+ .of_match_table = bcm2835_mbox_of_match, -+ }, -+ .probe = bcm2835_mbox_probe, -+ .remove = bcm2835_mbox_remove, -+}; -+ -+static int __init bcm2835_mbox_init(void) -+{ -+ return platform_driver_register(&bcm2835_mbox_driver); -+} -+arch_initcall(bcm2835_mbox_init); -+ -+static void __init bcm2835_mbox_exit(void) -+{ -+ platform_driver_unregister(&bcm2835_mbox_driver); -+} -+module_exit(bcm2835_mbox_exit); -+ -+MODULE_AUTHOR("Lubomir Rintel "); -+MODULE_DESCRIPTION("BCM2835 mailbox IPC driver"); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-4.1.13.orig/drivers/mailbox/Kconfig linux-rpi/drivers/mailbox/Kconfig ---- linux-4.1.13.orig/drivers/mailbox/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/mailbox/Kconfig 2015-11-29 09:42:37.651249381 +0100 -@@ -60,4 +60,13 @@ - An implementation of the Altera Mailbox soft core. It is used - to send message between processors. Say Y here if you want to use the - Altera mailbox support. -+ -+config BCM2835_MBOX -+ tristate "BCM2835 Mailbox" -+ depends on ARCH_BCM2835 || ARCH_BCM2708 || ARCH_BCM2709 -+ help -+ An implementation of the BCM2385 Mailbox. It is used to invoke -+ the services of the Videocore. Say Y here if you want to use the -+ BCM2835 Mailbox. -+ - endif -diff -Nur linux-4.1.13.orig/drivers/mailbox/mailbox.c linux-rpi/drivers/mailbox/mailbox.c ---- linux-4.1.13.orig/drivers/mailbox/mailbox.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/mailbox/mailbox.c 2015-11-29 09:42:37.651249381 +0100 -@@ -304,13 +304,23 @@ - unsigned long flags; - int ret; - -- if (!dev || !dev->of_node) { -+ if (!dev) { - pr_debug("%s: No owner device node\n", __func__); - return ERR_PTR(-ENODEV); - } - - mutex_lock(&con_mutex); - -+ if (!dev->of_node) { -+ chan = NULL; -+ /* pick the first controller in the list */ -+ list_for_each_entry(mbox, &mbox_cons, node) { -+ chan = &mbox->chans[0]; -+ break; -+ } -+ goto skip_dt; -+ } -+ - if (of_parse_phandle_with_args(dev->of_node, "mboxes", - "#mbox-cells", index, &spec)) { - dev_dbg(dev, "%s: can't parse \"mboxes\" property\n", __func__); -@@ -327,6 +337,7 @@ - - of_node_put(spec.np); - -+skip_dt: - if (!chan || chan->cl || !try_module_get(mbox->dev->driver->owner)) { - dev_dbg(dev, "%s: mailbox not free\n", __func__); - mutex_unlock(&con_mutex); -diff -Nur linux-4.1.13.orig/drivers/mailbox/Makefile linux-rpi/drivers/mailbox/Makefile ---- linux-4.1.13.orig/drivers/mailbox/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/mailbox/Makefile 2015-11-29 09:42:37.651249381 +0100 -@@ -11,3 +11,5 @@ - obj-$(CONFIG_PCC) += pcc.o - - obj-$(CONFIG_ALTERA_MBOX) += mailbox-altera.o -+ -+obj-$(CONFIG_BCM2835_MBOX) += bcm2835-mailbox.o -diff -Nur linux-4.1.13.orig/drivers/media/platform/bcm2835/bcm2835-camera.c linux-rpi/drivers/media/platform/bcm2835/bcm2835-camera.c ---- linux-4.1.13.orig/drivers/media/platform/bcm2835/bcm2835-camera.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/media/platform/bcm2835/bcm2835-camera.c 2015-11-29 09:42:37.835237156 +0100 -@@ -0,0 +1,1843 @@ -+/* -+ * Broadcom BM2835 V4L2 driver -+ * -+ * Copyright © 2013 Raspberry Pi (Trading) Ltd. -+ * -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file COPYING in the main directory of this archive -+ * for more details. -+ * -+ * Authors: Vincent Sanders -+ * Dave Stevenson -+ * Simon Mellor -+ * Luke Diamand -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "mmal-common.h" -+#include "mmal-encodings.h" -+#include "mmal-vchiq.h" -+#include "mmal-msg.h" -+#include "mmal-parameters.h" -+#include "bcm2835-camera.h" -+ -+#define BM2835_MMAL_VERSION "0.0.2" -+#define BM2835_MMAL_MODULE_NAME "bcm2835-v4l2" -+#define MIN_WIDTH 16 -+#define MIN_HEIGHT 16 -+#define MAX_WIDTH 2592 -+#define MAX_HEIGHT 1944 -+#define MIN_BUFFER_SIZE (80*1024) -+ -+#define MAX_VIDEO_MODE_WIDTH 1280 -+#define MAX_VIDEO_MODE_HEIGHT 720 -+ -+MODULE_DESCRIPTION("Broadcom 2835 MMAL video capture"); -+MODULE_AUTHOR("Vincent Sanders"); -+MODULE_LICENSE("GPL"); -+MODULE_VERSION(BM2835_MMAL_VERSION); -+ -+int bcm2835_v4l2_debug; -+module_param_named(debug, bcm2835_v4l2_debug, int, 0644); -+MODULE_PARM_DESC(bcm2835_v4l2_debug, "Debug level 0-2"); -+ -+int max_video_width = MAX_VIDEO_MODE_WIDTH; -+int max_video_height = MAX_VIDEO_MODE_HEIGHT; -+module_param(max_video_width, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); -+MODULE_PARM_DESC(max_video_width, "Threshold for video mode"); -+module_param(max_video_height, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); -+MODULE_PARM_DESC(max_video_height, "Threshold for video mode"); -+ -+/* Gstreamer bug https://bugzilla.gnome.org/show_bug.cgi?id=726521 -+ * v4l2src does bad (and actually wrong) things when the vidioc_enum_framesizes -+ * function says type V4L2_FRMSIZE_TYPE_STEPWISE, which we do by default. -+ * It's happier if we just don't say anything at all, when it then -+ * sets up a load of defaults that it thinks might work. -+ * If gst_v4l2src_is_broken is non-zero, then we remove the function from -+ * our function table list (actually switch to an alternate set, but same -+ * result). -+ */ -+int gst_v4l2src_is_broken = 0; -+module_param(gst_v4l2src_is_broken, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); -+MODULE_PARM_DESC(gst_v4l2src_is_broken, "If non-zero, enable workaround for Gstreamer"); -+ -+static struct bm2835_mmal_dev *gdev; /* global device data */ -+ -+#define FPS_MIN 1 -+#define FPS_MAX 90 -+ -+/* timeperframe: min/max and default */ -+static const struct v4l2_fract -+ tpf_min = {.numerator = 1, .denominator = FPS_MAX}, -+ tpf_max = {.numerator = 1, .denominator = FPS_MIN}, -+ tpf_default = {.numerator = 1000, .denominator = 30000}; -+ -+/* video formats */ -+static struct mmal_fmt formats[] = { -+ { -+ .name = "4:2:0, planar, YUV", -+ .fourcc = V4L2_PIX_FMT_YUV420, -+ .flags = 0, -+ .mmal = MMAL_ENCODING_I420, -+ .depth = 12, -+ .mmal_component = MMAL_COMPONENT_CAMERA, -+ .ybbp = 1, -+ }, -+ { -+ .name = "4:2:2, packed, YUYV", -+ .fourcc = V4L2_PIX_FMT_YUYV, -+ .flags = 0, -+ .mmal = MMAL_ENCODING_YUYV, -+ .depth = 16, -+ .mmal_component = MMAL_COMPONENT_CAMERA, -+ .ybbp = 2, -+ }, -+ { -+ .name = "RGB24 (LE)", -+ .fourcc = V4L2_PIX_FMT_RGB24, -+ .flags = 0, -+ .mmal = MMAL_ENCODING_BGR24, -+ .depth = 24, -+ .mmal_component = MMAL_COMPONENT_CAMERA, -+ .ybbp = 3, -+ }, -+ { -+ .name = "JPEG", -+ .fourcc = V4L2_PIX_FMT_JPEG, -+ .flags = V4L2_FMT_FLAG_COMPRESSED, -+ .mmal = MMAL_ENCODING_JPEG, -+ .depth = 8, -+ .mmal_component = MMAL_COMPONENT_IMAGE_ENCODE, -+ .ybbp = 0, -+ }, -+ { -+ .name = "H264", -+ .fourcc = V4L2_PIX_FMT_H264, -+ .flags = V4L2_FMT_FLAG_COMPRESSED, -+ .mmal = MMAL_ENCODING_H264, -+ .depth = 8, -+ .mmal_component = MMAL_COMPONENT_VIDEO_ENCODE, -+ .ybbp = 0, -+ }, -+ { -+ .name = "MJPEG", -+ .fourcc = V4L2_PIX_FMT_MJPEG, -+ .flags = V4L2_FMT_FLAG_COMPRESSED, -+ .mmal = MMAL_ENCODING_MJPEG, -+ .depth = 8, -+ .mmal_component = MMAL_COMPONENT_VIDEO_ENCODE, -+ .ybbp = 0, -+ }, -+ { -+ .name = "4:2:2, packed, YVYU", -+ .fourcc = V4L2_PIX_FMT_YVYU, -+ .flags = 0, -+ .mmal = MMAL_ENCODING_YVYU, -+ .depth = 16, -+ .mmal_component = MMAL_COMPONENT_CAMERA, -+ .ybbp = 2, -+ }, -+ { -+ .name = "4:2:2, packed, VYUY", -+ .fourcc = V4L2_PIX_FMT_VYUY, -+ .flags = 0, -+ .mmal = MMAL_ENCODING_VYUY, -+ .depth = 16, -+ .mmal_component = MMAL_COMPONENT_CAMERA, -+ .ybbp = 2, -+ }, -+ { -+ .name = "4:2:2, packed, UYVY", -+ .fourcc = V4L2_PIX_FMT_UYVY, -+ .flags = 0, -+ .mmal = MMAL_ENCODING_UYVY, -+ .depth = 16, -+ .mmal_component = MMAL_COMPONENT_CAMERA, -+ .ybbp = 2, -+ }, -+ { -+ .name = "4:2:0, planar, NV12", -+ .fourcc = V4L2_PIX_FMT_NV12, -+ .flags = 0, -+ .mmal = MMAL_ENCODING_NV12, -+ .depth = 12, -+ .mmal_component = MMAL_COMPONENT_CAMERA, -+ .ybbp = 1, -+ }, -+ { -+ .name = "RGB24 (BE)", -+ .fourcc = V4L2_PIX_FMT_BGR24, -+ .flags = 0, -+ .mmal = MMAL_ENCODING_RGB24, -+ .depth = 24, -+ .mmal_component = MMAL_COMPONENT_CAMERA, -+ .ybbp = 3, -+ }, -+ { -+ .name = "4:2:0, planar, YVU", -+ .fourcc = V4L2_PIX_FMT_YVU420, -+ .flags = 0, -+ .mmal = MMAL_ENCODING_YV12, -+ .depth = 12, -+ .mmal_component = MMAL_COMPONENT_CAMERA, -+ .ybbp = 1, -+ }, -+ { -+ .name = "4:2:0, planar, NV21", -+ .fourcc = V4L2_PIX_FMT_NV21, -+ .flags = 0, -+ .mmal = MMAL_ENCODING_NV21, -+ .depth = 12, -+ .mmal_component = MMAL_COMPONENT_CAMERA, -+ .ybbp = 1, -+ }, -+ { -+ .name = "RGB32 (BE)", -+ .fourcc = V4L2_PIX_FMT_BGR32, -+ .flags = 0, -+ .mmal = MMAL_ENCODING_BGRA, -+ .depth = 32, -+ .mmal_component = MMAL_COMPONENT_CAMERA, -+ .ybbp = 4, -+ }, -+}; -+ -+static struct mmal_fmt *get_format(struct v4l2_format *f) -+{ -+ struct mmal_fmt *fmt; -+ unsigned int k; -+ -+ for (k = 0; k < ARRAY_SIZE(formats); k++) { -+ fmt = &formats[k]; -+ if (fmt->fourcc == f->fmt.pix.pixelformat) -+ break; -+ } -+ -+ if (k == ARRAY_SIZE(formats)) -+ return NULL; -+ -+ return &formats[k]; -+} -+ -+/* ------------------------------------------------------------------ -+ Videobuf queue operations -+ ------------------------------------------------------------------*/ -+ -+static int queue_setup(struct vb2_queue *vq, const struct v4l2_format *fmt, -+ unsigned int *nbuffers, unsigned int *nplanes, -+ unsigned int sizes[], void *alloc_ctxs[]) -+{ -+ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vq); -+ unsigned long size; -+ -+ /* refuse queue setup if port is not configured */ -+ if (dev->capture.port == NULL) { -+ v4l2_err(&dev->v4l2_dev, -+ "%s: capture port not configured\n", __func__); -+ return -EINVAL; -+ } -+ -+ size = dev->capture.port->current_buffer.size; -+ if (size == 0) { -+ v4l2_err(&dev->v4l2_dev, -+ "%s: capture port buffer size is zero\n", __func__); -+ return -EINVAL; -+ } -+ -+ if (*nbuffers < (dev->capture.port->current_buffer.num + 2)) -+ *nbuffers = (dev->capture.port->current_buffer.num + 2); -+ -+ *nplanes = 1; -+ -+ sizes[0] = size; -+ -+ /* -+ * videobuf2-vmalloc allocator is context-less so no need to set -+ * alloc_ctxs array. -+ */ -+ -+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "%s: dev:%p\n", -+ __func__, dev); -+ -+ return 0; -+} -+ -+static int buffer_prepare(struct vb2_buffer *vb) -+{ -+ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vb->vb2_queue); -+ unsigned long size; -+ -+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "%s: dev:%p\n", -+ __func__, dev); -+ -+ BUG_ON(dev->capture.port == NULL); -+ BUG_ON(dev->capture.fmt == NULL); -+ -+ size = dev->capture.stride * dev->capture.height; -+ if (vb2_plane_size(vb, 0) < size) { -+ v4l2_err(&dev->v4l2_dev, -+ "%s data will not fit into plane (%lu < %lu)\n", -+ __func__, vb2_plane_size(vb, 0), size); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static inline bool is_capturing(struct bm2835_mmal_dev *dev) -+{ -+ return dev->capture.camera_port == -+ &dev-> -+ component[MMAL_COMPONENT_CAMERA]->output[MMAL_CAMERA_PORT_CAPTURE]; -+} -+ -+static void buffer_cb(struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_port *port, -+ int status, -+ struct mmal_buffer *buf, -+ unsigned long length, u32 mmal_flags, s64 dts, s64 pts) -+{ -+ struct bm2835_mmal_dev *dev = port->cb_ctx; -+ -+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, -+ "%s: status:%d, buf:%p, length:%lu, flags %u, pts %lld\n", -+ __func__, status, buf, length, mmal_flags, pts); -+ -+ if (status != 0) { -+ /* error in transfer */ -+ if (buf != NULL) { -+ /* there was a buffer with the error so return it */ -+ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); -+ } -+ return; -+ } else if (length == 0) { -+ /* stream ended */ -+ if (buf != NULL) { -+ /* this should only ever happen if the port is -+ * disabled and there are buffers still queued -+ */ -+ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); -+ pr_debug("Empty buffer"); -+ } else if (dev->capture.frame_count) { -+ /* grab another frame */ -+ if (is_capturing(dev)) { -+ pr_debug("Grab another frame"); -+ vchiq_mmal_port_parameter_set( -+ instance, -+ dev->capture. -+ camera_port, -+ MMAL_PARAMETER_CAPTURE, -+ &dev->capture. -+ frame_count, -+ sizeof(dev->capture.frame_count)); -+ } -+ } else { -+ /* signal frame completion */ -+ complete(&dev->capture.frame_cmplt); -+ } -+ } else { -+ if (dev->capture.frame_count) { -+ if (dev->capture.vc_start_timestamp != -1 && -+ pts != 0) { -+ s64 runtime_us = pts - -+ dev->capture.vc_start_timestamp; -+ u32 div = 0; -+ u32 rem = 0; -+ -+ div = -+ div_u64_rem(runtime_us, USEC_PER_SEC, &rem); -+ buf->vb.v4l2_buf.timestamp.tv_sec = -+ dev->capture.kernel_start_ts.tv_sec - 1 + -+ div; -+ buf->vb.v4l2_buf.timestamp.tv_usec = -+ dev->capture.kernel_start_ts.tv_usec + rem; -+ -+ if (buf->vb.v4l2_buf.timestamp.tv_usec >= -+ USEC_PER_SEC) { -+ buf->vb.v4l2_buf.timestamp.tv_sec++; -+ buf->vb.v4l2_buf.timestamp.tv_usec -= -+ USEC_PER_SEC; -+ } -+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, -+ "Convert start time %d.%06d and %llu " -+ "with offset %llu to %d.%06d\n", -+ (int)dev->capture.kernel_start_ts. -+ tv_sec, -+ (int)dev->capture.kernel_start_ts. -+ tv_usec, -+ dev->capture.vc_start_timestamp, pts, -+ (int)buf->vb.v4l2_buf.timestamp.tv_sec, -+ (int)buf->vb.v4l2_buf.timestamp. -+ tv_usec); -+ } else { -+ v4l2_get_timestamp(&buf->vb.v4l2_buf.timestamp); -+ } -+ -+ vb2_set_plane_payload(&buf->vb, 0, length); -+ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_DONE); -+ -+ if (mmal_flags & MMAL_BUFFER_HEADER_FLAG_EOS && -+ is_capturing(dev)) { -+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, -+ "Grab another frame as buffer has EOS"); -+ vchiq_mmal_port_parameter_set( -+ instance, -+ dev->capture. -+ camera_port, -+ MMAL_PARAMETER_CAPTURE, -+ &dev->capture. -+ frame_count, -+ sizeof(dev->capture.frame_count)); -+ } -+ } else { -+ /* signal frame completion */ -+ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); -+ complete(&dev->capture.frame_cmplt); -+ } -+ } -+} -+ -+static int enable_camera(struct bm2835_mmal_dev *dev) -+{ -+ int ret; -+ if (!dev->camera_use_count) { -+ ret = vchiq_mmal_component_enable( -+ dev->instance, -+ dev->component[MMAL_COMPONENT_CAMERA]); -+ if (ret < 0) { -+ v4l2_err(&dev->v4l2_dev, -+ "Failed enabling camera, ret %d\n", ret); -+ return -EINVAL; -+ } -+ } -+ dev->camera_use_count++; -+ v4l2_dbg(1, bcm2835_v4l2_debug, -+ &dev->v4l2_dev, "enabled camera (refcount %d)\n", -+ dev->camera_use_count); -+ return 0; -+} -+ -+static int disable_camera(struct bm2835_mmal_dev *dev) -+{ -+ int ret; -+ if (!dev->camera_use_count) { -+ v4l2_err(&dev->v4l2_dev, -+ "Disabled the camera when already disabled\n"); -+ return -EINVAL; -+ } -+ dev->camera_use_count--; -+ if (!dev->camera_use_count) { -+ unsigned int i = 0xFFFFFFFF; -+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, -+ "Disabling camera\n"); -+ ret = -+ vchiq_mmal_component_disable( -+ dev->instance, -+ dev->component[MMAL_COMPONENT_CAMERA]); -+ if (ret < 0) { -+ v4l2_err(&dev->v4l2_dev, -+ "Failed disabling camera, ret %d\n", ret); -+ return -EINVAL; -+ } -+ vchiq_mmal_port_parameter_set( -+ dev->instance, -+ &dev->component[MMAL_COMPONENT_CAMERA]->control, -+ MMAL_PARAMETER_CAMERA_NUM, &i, -+ sizeof(i)); -+ } -+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, -+ "Camera refcount now %d\n", dev->camera_use_count); -+ return 0; -+} -+ -+static void buffer_queue(struct vb2_buffer *vb) -+{ -+ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vb->vb2_queue); -+ struct mmal_buffer *buf = container_of(vb, struct mmal_buffer, vb); -+ int ret; -+ -+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, -+ "%s: dev:%p buf:%p\n", __func__, dev, buf); -+ -+ buf->buffer = vb2_plane_vaddr(&buf->vb, 0); -+ buf->buffer_size = vb2_plane_size(&buf->vb, 0); -+ -+ ret = vchiq_mmal_submit_buffer(dev->instance, dev->capture.port, buf); -+ if (ret < 0) -+ v4l2_err(&dev->v4l2_dev, "%s: error submitting buffer\n", -+ __func__); -+} -+ -+static int start_streaming(struct vb2_queue *vq, unsigned int count) -+{ -+ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vq); -+ int ret; -+ int parameter_size; -+ -+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "%s: dev:%p\n", -+ __func__, dev); -+ -+ /* ensure a format has actually been set */ -+ if (dev->capture.port == NULL) -+ return -EINVAL; -+ -+ if (enable_camera(dev) < 0) { -+ v4l2_err(&dev->v4l2_dev, "Failed to enable camera\n"); -+ return -EINVAL; -+ } -+ -+ /*init_completion(&dev->capture.frame_cmplt); */ -+ -+ /* enable frame capture */ -+ dev->capture.frame_count = 1; -+ -+ /* if the preview is not already running, wait for a few frames for AGC -+ * to settle down. -+ */ -+ if (!dev->component[MMAL_COMPONENT_PREVIEW]->enabled) -+ msleep(300); -+ -+ /* enable the connection from camera to encoder (if applicable) */ -+ if (dev->capture.camera_port != dev->capture.port -+ && dev->capture.camera_port) { -+ ret = vchiq_mmal_port_enable(dev->instance, -+ dev->capture.camera_port, NULL); -+ if (ret) { -+ v4l2_err(&dev->v4l2_dev, -+ "Failed to enable encode tunnel - error %d\n", -+ ret); -+ return -1; -+ } -+ } -+ -+ /* Get VC timestamp at this point in time */ -+ parameter_size = sizeof(dev->capture.vc_start_timestamp); -+ if (vchiq_mmal_port_parameter_get(dev->instance, -+ dev->capture.camera_port, -+ MMAL_PARAMETER_SYSTEM_TIME, -+ &dev->capture.vc_start_timestamp, -+ ¶meter_size)) { -+ v4l2_err(&dev->v4l2_dev, -+ "Failed to get VC start time - update your VC f/w\n"); -+ -+ /* Flag to indicate just to rely on kernel timestamps */ -+ dev->capture.vc_start_timestamp = -1; -+ } else -+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, -+ "Start time %lld size %d\n", -+ dev->capture.vc_start_timestamp, parameter_size); -+ -+ v4l2_get_timestamp(&dev->capture.kernel_start_ts); -+ -+ /* enable the camera port */ -+ dev->capture.port->cb_ctx = dev; -+ ret = -+ vchiq_mmal_port_enable(dev->instance, dev->capture.port, buffer_cb); -+ if (ret) { -+ v4l2_err(&dev->v4l2_dev, -+ "Failed to enable capture port - error %d. " -+ "Disabling camera port again\n", ret); -+ -+ vchiq_mmal_port_disable(dev->instance, -+ dev->capture.camera_port); -+ if (disable_camera(dev) < 0) { -+ v4l2_err(&dev->v4l2_dev, "Failed to disable camera\n"); -+ return -EINVAL; -+ } -+ return -1; -+ } -+ -+ /* capture the first frame */ -+ vchiq_mmal_port_parameter_set(dev->instance, -+ dev->capture.camera_port, -+ MMAL_PARAMETER_CAPTURE, -+ &dev->capture.frame_count, -+ sizeof(dev->capture.frame_count)); -+ return 0; -+} -+ -+/* abort streaming and wait for last buffer */ -+static void stop_streaming(struct vb2_queue *vq) -+{ -+ int ret; -+ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vq); -+ -+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "%s: dev:%p\n", -+ __func__, dev); -+ -+ init_completion(&dev->capture.frame_cmplt); -+ dev->capture.frame_count = 0; -+ -+ /* ensure a format has actually been set */ -+ if (dev->capture.port == NULL) { -+ v4l2_err(&dev->v4l2_dev, -+ "no capture port - stream not started?\n"); -+ return; -+ } -+ -+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "stopping capturing\n"); -+ -+ /* stop capturing frames */ -+ vchiq_mmal_port_parameter_set(dev->instance, -+ dev->capture.camera_port, -+ MMAL_PARAMETER_CAPTURE, -+ &dev->capture.frame_count, -+ sizeof(dev->capture.frame_count)); -+ -+ /* wait for last frame to complete */ -+ ret = wait_for_completion_timeout(&dev->capture.frame_cmplt, HZ); -+ if (ret <= 0) -+ v4l2_err(&dev->v4l2_dev, -+ "error %d waiting for frame completion\n", ret); -+ -+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, -+ "disabling connection\n"); -+ -+ /* disable the connection from camera to encoder */ -+ ret = vchiq_mmal_port_disable(dev->instance, dev->capture.camera_port); -+ if (!ret && dev->capture.camera_port != dev->capture.port) { -+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, -+ "disabling port\n"); -+ ret = vchiq_mmal_port_disable(dev->instance, dev->capture.port); -+ } else if (dev->capture.camera_port != dev->capture.port) { -+ v4l2_err(&dev->v4l2_dev, "port_disable failed, error %d\n", -+ ret); -+ } -+ -+ if (disable_camera(dev) < 0) -+ v4l2_err(&dev->v4l2_dev, "Failed to disable camera\n"); -+} -+ -+static void bm2835_mmal_lock(struct vb2_queue *vq) -+{ -+ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vq); -+ mutex_lock(&dev->mutex); -+} -+ -+static void bm2835_mmal_unlock(struct vb2_queue *vq) -+{ -+ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vq); -+ mutex_unlock(&dev->mutex); -+} -+ -+static struct vb2_ops bm2835_mmal_video_qops = { -+ .queue_setup = queue_setup, -+ .buf_prepare = buffer_prepare, -+ .buf_queue = buffer_queue, -+ .start_streaming = start_streaming, -+ .stop_streaming = stop_streaming, -+ .wait_prepare = bm2835_mmal_unlock, -+ .wait_finish = bm2835_mmal_lock, -+}; -+ -+/* ------------------------------------------------------------------ -+ IOCTL operations -+ ------------------------------------------------------------------*/ -+ -+/* overlay ioctl */ -+static int vidioc_enum_fmt_vid_overlay(struct file *file, void *priv, -+ struct v4l2_fmtdesc *f) -+{ -+ struct mmal_fmt *fmt; -+ -+ if (f->index >= ARRAY_SIZE(formats)) -+ return -EINVAL; -+ -+ fmt = &formats[f->index]; -+ -+ strlcpy(f->description, fmt->name, sizeof(f->description)); -+ f->pixelformat = fmt->fourcc; -+ f->flags = fmt->flags; -+ -+ return 0; -+} -+ -+static int vidioc_g_fmt_vid_overlay(struct file *file, void *priv, -+ struct v4l2_format *f) -+{ -+ struct bm2835_mmal_dev *dev = video_drvdata(file); -+ -+ f->fmt.win = dev->overlay; -+ -+ return 0; -+} -+ -+static int vidioc_try_fmt_vid_overlay(struct file *file, void *priv, -+ struct v4l2_format *f) -+{ -+ /* Only support one format so get the current one. */ -+ vidioc_g_fmt_vid_overlay(file, priv, f); -+ -+ /* todo: allow the size and/or offset to be changed. */ -+ return 0; -+} -+ -+static int vidioc_s_fmt_vid_overlay(struct file *file, void *priv, -+ struct v4l2_format *f) -+{ -+ struct bm2835_mmal_dev *dev = video_drvdata(file); -+ -+ vidioc_try_fmt_vid_overlay(file, priv, f); -+ -+ dev->overlay = f->fmt.win; -+ -+ /* todo: program the preview port parameters */ -+ return 0; -+} -+ -+static int vidioc_overlay(struct file *file, void *f, unsigned int on) -+{ -+ int ret; -+ struct bm2835_mmal_dev *dev = video_drvdata(file); -+ struct vchiq_mmal_port *src; -+ struct vchiq_mmal_port *dst; -+ struct mmal_parameter_displayregion prev_config = { -+ .set = MMAL_DISPLAY_SET_LAYER | MMAL_DISPLAY_SET_ALPHA | -+ MMAL_DISPLAY_SET_DEST_RECT | MMAL_DISPLAY_SET_FULLSCREEN, -+ .layer = PREVIEW_LAYER, -+ .alpha = 255, -+ .fullscreen = 0, -+ .dest_rect = { -+ .x = dev->overlay.w.left, -+ .y = dev->overlay.w.top, -+ .width = dev->overlay.w.width, -+ .height = dev->overlay.w.height, -+ }, -+ }; -+ -+ if ((on && dev->component[MMAL_COMPONENT_PREVIEW]->enabled) || -+ (!on && !dev->component[MMAL_COMPONENT_PREVIEW]->enabled)) -+ return 0; /* already in requested state */ -+ -+ src = -+ &dev->component[MMAL_COMPONENT_CAMERA]-> -+ output[MMAL_CAMERA_PORT_PREVIEW]; -+ -+ if (!on) { -+ /* disconnect preview ports and disable component */ -+ ret = vchiq_mmal_port_disable(dev->instance, src); -+ if (!ret) -+ ret = -+ vchiq_mmal_port_connect_tunnel(dev->instance, src, -+ NULL); -+ if (ret >= 0) -+ ret = vchiq_mmal_component_disable( -+ dev->instance, -+ dev->component[MMAL_COMPONENT_PREVIEW]); -+ -+ disable_camera(dev); -+ return ret; -+ } -+ -+ /* set preview port format and connect it to output */ -+ dst = &dev->component[MMAL_COMPONENT_PREVIEW]->input[0]; -+ -+ ret = vchiq_mmal_port_set_format(dev->instance, src); -+ if (ret < 0) -+ goto error; -+ -+ ret = vchiq_mmal_port_parameter_set(dev->instance, dst, -+ MMAL_PARAMETER_DISPLAYREGION, -+ &prev_config, sizeof(prev_config)); -+ if (ret < 0) -+ goto error; -+ -+ if (enable_camera(dev) < 0) -+ goto error; -+ -+ ret = vchiq_mmal_component_enable( -+ dev->instance, -+ dev->component[MMAL_COMPONENT_PREVIEW]); -+ if (ret < 0) -+ goto error; -+ -+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "connecting %p to %p\n", -+ src, dst); -+ ret = vchiq_mmal_port_connect_tunnel(dev->instance, src, dst); -+ if (!ret) -+ ret = vchiq_mmal_port_enable(dev->instance, src, NULL); -+error: -+ return ret; -+} -+ -+static int vidioc_g_fbuf(struct file *file, void *fh, -+ struct v4l2_framebuffer *a) -+{ -+ /* The video overlay must stay within the framebuffer and can't be -+ positioned independently. */ -+ struct bm2835_mmal_dev *dev = video_drvdata(file); -+ struct vchiq_mmal_port *preview_port = -+ &dev->component[MMAL_COMPONENT_CAMERA]-> -+ output[MMAL_CAMERA_PORT_PREVIEW]; -+ a->flags = V4L2_FBUF_FLAG_OVERLAY; -+ a->fmt.width = preview_port->es.video.width; -+ a->fmt.height = preview_port->es.video.height; -+ a->fmt.pixelformat = V4L2_PIX_FMT_YUV420; -+ a->fmt.bytesperline = preview_port->es.video.width; -+ a->fmt.sizeimage = (preview_port->es.video.width * -+ preview_port->es.video.height * 3)>>1; -+ a->fmt.colorspace = V4L2_COLORSPACE_SMPTE170M; -+ -+ return 0; -+} -+ -+/* input ioctls */ -+static int vidioc_enum_input(struct file *file, void *priv, -+ struct v4l2_input *inp) -+{ -+ /* only a single camera input */ -+ if (inp->index != 0) -+ return -EINVAL; -+ -+ inp->type = V4L2_INPUT_TYPE_CAMERA; -+ sprintf(inp->name, "Camera %u", inp->index); -+ return 0; -+} -+ -+static int vidioc_g_input(struct file *file, void *priv, unsigned int *i) -+{ -+ *i = 0; -+ return 0; -+} -+ -+static int vidioc_s_input(struct file *file, void *priv, unsigned int i) -+{ -+ if (i != 0) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+/* capture ioctls */ -+static int vidioc_querycap(struct file *file, void *priv, -+ struct v4l2_capability *cap) -+{ -+ struct bm2835_mmal_dev *dev = video_drvdata(file); -+ u32 major; -+ u32 minor; -+ -+ vchiq_mmal_version(dev->instance, &major, &minor); -+ -+ strcpy(cap->driver, "bm2835 mmal"); -+ snprintf(cap->card, sizeof(cap->card), "mmal service %d.%d", -+ major, minor); -+ -+ snprintf(cap->bus_info, sizeof(cap->bus_info), -+ "platform:%s", dev->v4l2_dev.name); -+ cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OVERLAY | -+ V4L2_CAP_STREAMING | V4L2_CAP_READWRITE; -+ cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS; -+ -+ return 0; -+} -+ -+static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv, -+ struct v4l2_fmtdesc *f) -+{ -+ struct mmal_fmt *fmt; -+ -+ if (f->index >= ARRAY_SIZE(formats)) -+ return -EINVAL; -+ -+ fmt = &formats[f->index]; -+ -+ strlcpy(f->description, fmt->name, sizeof(f->description)); -+ f->pixelformat = fmt->fourcc; -+ f->flags = fmt->flags; -+ -+ return 0; -+} -+ -+static int vidioc_g_fmt_vid_cap(struct file *file, void *priv, -+ struct v4l2_format *f) -+{ -+ struct bm2835_mmal_dev *dev = video_drvdata(file); -+ -+ f->fmt.pix.width = dev->capture.width; -+ f->fmt.pix.height = dev->capture.height; -+ f->fmt.pix.field = V4L2_FIELD_NONE; -+ f->fmt.pix.pixelformat = dev->capture.fmt->fourcc; -+ f->fmt.pix.bytesperline = dev->capture.stride; -+ f->fmt.pix.sizeimage = dev->capture.buffersize; -+ -+ if (dev->capture.fmt->fourcc == V4L2_PIX_FMT_RGB24) -+ f->fmt.pix.colorspace = V4L2_COLORSPACE_SRGB; -+ else if (dev->capture.fmt->fourcc == V4L2_PIX_FMT_JPEG) -+ f->fmt.pix.colorspace = V4L2_COLORSPACE_JPEG; -+ else -+ f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; -+ f->fmt.pix.priv = 0; -+ -+ v4l2_dump_pix_format(1, bcm2835_v4l2_debug, &dev->v4l2_dev, &f->fmt.pix, -+ __func__); -+ return 0; -+} -+ -+static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, -+ struct v4l2_format *f) -+{ -+ struct bm2835_mmal_dev *dev = video_drvdata(file); -+ struct mmal_fmt *mfmt; -+ -+ mfmt = get_format(f); -+ if (!mfmt) { -+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, -+ "Fourcc format (0x%08x) unknown.\n", -+ f->fmt.pix.pixelformat); -+ f->fmt.pix.pixelformat = formats[0].fourcc; -+ mfmt = get_format(f); -+ } -+ -+ f->fmt.pix.field = V4L2_FIELD_NONE; -+ -+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, -+ "Clipping/aligning %dx%d format %08X\n", -+ f->fmt.pix.width, f->fmt.pix.height, f->fmt.pix.pixelformat); -+ -+ v4l_bound_align_image(&f->fmt.pix.width, MIN_WIDTH, MAX_WIDTH, 1, -+ &f->fmt.pix.height, MIN_HEIGHT, MAX_HEIGHT, 1, 0); -+ f->fmt.pix.bytesperline = f->fmt.pix.width * mfmt->ybbp; -+ -+ /* Image buffer has to be padded to allow for alignment, even though -+ * we then remove that padding before delivering the buffer. -+ */ -+ f->fmt.pix.sizeimage = ((f->fmt.pix.height+15)&~15) * -+ (((f->fmt.pix.width+31)&~31) * mfmt->depth) >> 3; -+ -+ if ((mfmt->flags & V4L2_FMT_FLAG_COMPRESSED) && -+ f->fmt.pix.sizeimage < MIN_BUFFER_SIZE) -+ f->fmt.pix.sizeimage = MIN_BUFFER_SIZE; -+ -+ if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_RGB24) -+ f->fmt.pix.colorspace = V4L2_COLORSPACE_SRGB; -+ else if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_JPEG) -+ f->fmt.pix.colorspace = V4L2_COLORSPACE_JPEG; -+ else -+ f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; -+ f->fmt.pix.priv = 0; -+ -+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, -+ "Now %dx%d format %08X\n", -+ f->fmt.pix.width, f->fmt.pix.height, f->fmt.pix.pixelformat); -+ -+ v4l2_dump_pix_format(1, bcm2835_v4l2_debug, &dev->v4l2_dev, &f->fmt.pix, -+ __func__); -+ return 0; -+} -+ -+static int mmal_setup_components(struct bm2835_mmal_dev *dev, -+ struct v4l2_format *f) -+{ -+ int ret; -+ struct vchiq_mmal_port *port = NULL, *camera_port = NULL; -+ struct vchiq_mmal_component *encode_component = NULL; -+ struct mmal_fmt *mfmt = get_format(f); -+ -+ BUG_ON(!mfmt); -+ -+ if (dev->capture.encode_component) { -+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, -+ "vid_cap - disconnect previous tunnel\n"); -+ -+ /* Disconnect any previous connection */ -+ vchiq_mmal_port_connect_tunnel(dev->instance, -+ dev->capture.camera_port, NULL); -+ dev->capture.camera_port = NULL; -+ ret = vchiq_mmal_component_disable(dev->instance, -+ dev->capture. -+ encode_component); -+ if (ret) -+ v4l2_err(&dev->v4l2_dev, -+ "Failed to disable encode component %d\n", -+ ret); -+ -+ dev->capture.encode_component = NULL; -+ } -+ /* format dependant port setup */ -+ switch (mfmt->mmal_component) { -+ case MMAL_COMPONENT_CAMERA: -+ /* Make a further decision on port based on resolution */ -+ if (f->fmt.pix.width <= max_video_width -+ && f->fmt.pix.height <= max_video_height) -+ camera_port = port = -+ &dev->component[MMAL_COMPONENT_CAMERA]-> -+ output[MMAL_CAMERA_PORT_VIDEO]; -+ else -+ camera_port = port = -+ &dev->component[MMAL_COMPONENT_CAMERA]-> -+ output[MMAL_CAMERA_PORT_CAPTURE]; -+ break; -+ case MMAL_COMPONENT_IMAGE_ENCODE: -+ encode_component = dev->component[MMAL_COMPONENT_IMAGE_ENCODE]; -+ port = &dev->component[MMAL_COMPONENT_IMAGE_ENCODE]->output[0]; -+ camera_port = -+ &dev->component[MMAL_COMPONENT_CAMERA]-> -+ output[MMAL_CAMERA_PORT_CAPTURE]; -+ break; -+ case MMAL_COMPONENT_VIDEO_ENCODE: -+ encode_component = dev->component[MMAL_COMPONENT_VIDEO_ENCODE]; -+ port = &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0]; -+ camera_port = -+ &dev->component[MMAL_COMPONENT_CAMERA]-> -+ output[MMAL_CAMERA_PORT_VIDEO]; -+ break; -+ default: -+ break; -+ } -+ -+ if (!port) -+ return -EINVAL; -+ -+ if (encode_component) -+ camera_port->format.encoding = MMAL_ENCODING_OPAQUE; -+ else -+ camera_port->format.encoding = mfmt->mmal; -+ -+ camera_port->format.encoding_variant = 0; -+ camera_port->es.video.width = f->fmt.pix.width; -+ camera_port->es.video.height = f->fmt.pix.height; -+ camera_port->es.video.crop.x = 0; -+ camera_port->es.video.crop.y = 0; -+ camera_port->es.video.crop.width = f->fmt.pix.width; -+ camera_port->es.video.crop.height = f->fmt.pix.height; -+ camera_port->es.video.frame_rate.num = 0; -+ camera_port->es.video.frame_rate.den = 1; -+ camera_port->es.video.color_space = MMAL_COLOR_SPACE_JPEG_JFIF; -+ -+ ret = vchiq_mmal_port_set_format(dev->instance, camera_port); -+ -+ if (!ret -+ && camera_port == -+ &dev->component[MMAL_COMPONENT_CAMERA]-> -+ output[MMAL_CAMERA_PORT_VIDEO]) { -+ bool overlay_enabled = -+ !!dev->component[MMAL_COMPONENT_PREVIEW]->enabled; -+ struct vchiq_mmal_port *preview_port = -+ &dev->component[MMAL_COMPONENT_CAMERA]-> -+ output[MMAL_CAMERA_PORT_PREVIEW]; -+ /* Preview and encode ports need to match on resolution */ -+ if (overlay_enabled) { -+ /* Need to disable the overlay before we can update -+ * the resolution -+ */ -+ ret = -+ vchiq_mmal_port_disable(dev->instance, -+ preview_port); -+ if (!ret) -+ ret = -+ vchiq_mmal_port_connect_tunnel( -+ dev->instance, -+ preview_port, -+ NULL); -+ } -+ preview_port->es.video.width = f->fmt.pix.width; -+ preview_port->es.video.height = f->fmt.pix.height; -+ preview_port->es.video.crop.x = 0; -+ preview_port->es.video.crop.y = 0; -+ preview_port->es.video.crop.width = f->fmt.pix.width; -+ preview_port->es.video.crop.height = f->fmt.pix.height; -+ preview_port->es.video.frame_rate.num = -+ dev->capture.timeperframe.denominator; -+ preview_port->es.video.frame_rate.den = -+ dev->capture.timeperframe.numerator; -+ ret = vchiq_mmal_port_set_format(dev->instance, preview_port); -+ if (overlay_enabled) { -+ ret = vchiq_mmal_port_connect_tunnel( -+ dev->instance, -+ preview_port, -+ &dev->component[MMAL_COMPONENT_PREVIEW]->input[0]); -+ if (!ret) -+ ret = vchiq_mmal_port_enable(dev->instance, -+ preview_port, -+ NULL); -+ } -+ } -+ -+ if (ret) { -+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, -+ "%s failed to set format %dx%d %08X\n", __func__, -+ f->fmt.pix.width, f->fmt.pix.height, -+ f->fmt.pix.pixelformat); -+ /* ensure capture is not going to be tried */ -+ dev->capture.port = NULL; -+ } else { -+ if (encode_component) { -+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, -+ "vid_cap - set up encode comp\n"); -+ -+ /* configure buffering */ -+ camera_port->current_buffer.size = -+ camera_port->recommended_buffer.size; -+ camera_port->current_buffer.num = -+ camera_port->recommended_buffer.num; -+ -+ ret = -+ vchiq_mmal_port_connect_tunnel( -+ dev->instance, -+ camera_port, -+ &encode_component->input[0]); -+ if (ret) { -+ v4l2_dbg(1, bcm2835_v4l2_debug, -+ &dev->v4l2_dev, -+ "%s failed to create connection\n", -+ __func__); -+ /* ensure capture is not going to be tried */ -+ dev->capture.port = NULL; -+ } else { -+ port->es.video.width = f->fmt.pix.width; -+ port->es.video.height = f->fmt.pix.height; -+ port->es.video.crop.x = 0; -+ port->es.video.crop.y = 0; -+ port->es.video.crop.width = f->fmt.pix.width; -+ port->es.video.crop.height = f->fmt.pix.height; -+ port->es.video.frame_rate.num = -+ dev->capture.timeperframe.denominator; -+ port->es.video.frame_rate.den = -+ dev->capture.timeperframe.numerator; -+ -+ port->format.encoding = mfmt->mmal; -+ port->format.encoding_variant = 0; -+ /* Set any encoding specific parameters */ -+ switch (mfmt->mmal_component) { -+ case MMAL_COMPONENT_VIDEO_ENCODE: -+ port->format.bitrate = -+ dev->capture.encode_bitrate; -+ break; -+ case MMAL_COMPONENT_IMAGE_ENCODE: -+ /* Could set EXIF parameters here */ -+ break; -+ default: -+ break; -+ } -+ ret = vchiq_mmal_port_set_format(dev->instance, -+ port); -+ if (ret) -+ v4l2_dbg(1, bcm2835_v4l2_debug, -+ &dev->v4l2_dev, -+ "%s failed to set format %dx%d fmt %08X\n", -+ __func__, -+ f->fmt.pix.width, -+ f->fmt.pix.height, -+ f->fmt.pix.pixelformat -+ ); -+ } -+ -+ if (!ret) { -+ ret = vchiq_mmal_component_enable( -+ dev->instance, -+ encode_component); -+ if (ret) { -+ v4l2_dbg(1, bcm2835_v4l2_debug, -+ &dev->v4l2_dev, -+ "%s Failed to enable encode components\n", -+ __func__); -+ } -+ } -+ if (!ret) { -+ /* configure buffering */ -+ port->current_buffer.num = 1; -+ port->current_buffer.size = -+ f->fmt.pix.sizeimage; -+ if (port->format.encoding == -+ MMAL_ENCODING_JPEG) { -+ v4l2_dbg(1, bcm2835_v4l2_debug, -+ &dev->v4l2_dev, -+ "JPG - buf size now %d was %d\n", -+ f->fmt.pix.sizeimage, -+ port->current_buffer.size); -+ port->current_buffer.size = -+ (f->fmt.pix.sizeimage < -+ (100 << 10)) -+ ? (100 << 10) : f->fmt.pix. -+ sizeimage; -+ } -+ v4l2_dbg(1, bcm2835_v4l2_debug, -+ &dev->v4l2_dev, -+ "vid_cap - cur_buf.size set to %d\n", -+ f->fmt.pix.sizeimage); -+ port->current_buffer.alignment = 0; -+ } -+ } else { -+ /* configure buffering */ -+ camera_port->current_buffer.num = 1; -+ camera_port->current_buffer.size = f->fmt.pix.sizeimage; -+ camera_port->current_buffer.alignment = 0; -+ } -+ -+ if (!ret) { -+ dev->capture.fmt = mfmt; -+ dev->capture.stride = f->fmt.pix.bytesperline; -+ dev->capture.width = camera_port->es.video.crop.width; -+ dev->capture.height = camera_port->es.video.crop.height; -+ dev->capture.buffersize = port->current_buffer.size; -+ -+ /* select port for capture */ -+ dev->capture.port = port; -+ dev->capture.camera_port = camera_port; -+ dev->capture.encode_component = encode_component; -+ v4l2_dbg(1, bcm2835_v4l2_debug, -+ &dev->v4l2_dev, -+ "Set dev->capture.fmt %08X, %dx%d, stride %d, size %d", -+ port->format.encoding, -+ dev->capture.width, dev->capture.height, -+ dev->capture.stride, dev->capture.buffersize); -+ } -+ } -+ -+ /* todo: Need to convert the vchiq/mmal error into a v4l2 error. */ -+ return ret; -+} -+ -+static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, -+ struct v4l2_format *f) -+{ -+ int ret; -+ struct bm2835_mmal_dev *dev = video_drvdata(file); -+ struct mmal_fmt *mfmt; -+ -+ /* try the format to set valid parameters */ -+ ret = vidioc_try_fmt_vid_cap(file, priv, f); -+ if (ret) { -+ v4l2_err(&dev->v4l2_dev, -+ "vid_cap - vidioc_try_fmt_vid_cap failed\n"); -+ return ret; -+ } -+ -+ /* if a capture is running refuse to set format */ -+ if (vb2_is_busy(&dev->capture.vb_vidq)) { -+ v4l2_info(&dev->v4l2_dev, "%s device busy\n", __func__); -+ return -EBUSY; -+ } -+ -+ /* If the format is unsupported v4l2 says we should switch to -+ * a supported one and not return an error. */ -+ mfmt = get_format(f); -+ if (!mfmt) { -+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, -+ "Fourcc format (0x%08x) unknown.\n", -+ f->fmt.pix.pixelformat); -+ f->fmt.pix.pixelformat = formats[0].fourcc; -+ mfmt = get_format(f); -+ } -+ -+ ret = mmal_setup_components(dev, f); -+ if (ret != 0) { -+ v4l2_err(&dev->v4l2_dev, -+ "%s: failed to setup mmal components: %d\n", -+ __func__, ret); -+ ret = -EINVAL; -+ } -+ -+ return ret; -+} -+ -+int vidioc_enum_framesizes(struct file *file, void *fh, -+ struct v4l2_frmsizeenum *fsize) -+{ -+ static const struct v4l2_frmsize_stepwise sizes = { -+ MIN_WIDTH, MAX_WIDTH, 2, -+ MIN_HEIGHT, MAX_HEIGHT, 2 -+ }; -+ int i; -+ -+ if (fsize->index) -+ return -EINVAL; -+ for (i = 0; i < ARRAY_SIZE(formats); i++) -+ if (formats[i].fourcc == fsize->pixel_format) -+ break; -+ if (i == ARRAY_SIZE(formats)) -+ return -EINVAL; -+ fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE; -+ fsize->stepwise = sizes; -+ return 0; -+} -+ -+/* timeperframe is arbitrary and continous */ -+static int vidioc_enum_frameintervals(struct file *file, void *priv, -+ struct v4l2_frmivalenum *fival) -+{ -+ int i; -+ -+ if (fival->index) -+ return -EINVAL; -+ -+ for (i = 0; i < ARRAY_SIZE(formats); i++) -+ if (formats[i].fourcc == fival->pixel_format) -+ break; -+ if (i == ARRAY_SIZE(formats)) -+ return -EINVAL; -+ -+ /* regarding width & height - we support any within range */ -+ if (fival->width < MIN_WIDTH || fival->width > MAX_WIDTH || -+ fival->height < MIN_HEIGHT || fival->height > MAX_HEIGHT) -+ return -EINVAL; -+ -+ fival->type = V4L2_FRMIVAL_TYPE_CONTINUOUS; -+ -+ /* fill in stepwise (step=1.0 is requred by V4L2 spec) */ -+ fival->stepwise.min = tpf_min; -+ fival->stepwise.max = tpf_max; -+ fival->stepwise.step = (struct v4l2_fract) {1, 1}; -+ -+ return 0; -+} -+ -+static int vidioc_g_parm(struct file *file, void *priv, -+ struct v4l2_streamparm *parm) -+{ -+ struct bm2835_mmal_dev *dev = video_drvdata(file); -+ -+ if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) -+ return -EINVAL; -+ -+ parm->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; -+ parm->parm.capture.timeperframe = dev->capture.timeperframe; -+ parm->parm.capture.readbuffers = 1; -+ return 0; -+} -+ -+#define FRACT_CMP(a, OP, b) \ -+ ((u64)(a).numerator * (b).denominator OP \ -+ (u64)(b).numerator * (a).denominator) -+ -+static int vidioc_s_parm(struct file *file, void *priv, -+ struct v4l2_streamparm *parm) -+{ -+ struct bm2835_mmal_dev *dev = video_drvdata(file); -+ struct v4l2_fract tpf; -+ struct mmal_parameter_rational fps_param; -+ -+ if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) -+ return -EINVAL; -+ -+ tpf = parm->parm.capture.timeperframe; -+ -+ /* tpf: {*, 0} resets timing; clip to [min, max]*/ -+ tpf = tpf.denominator ? tpf : tpf_default; -+ tpf = FRACT_CMP(tpf, <, tpf_min) ? tpf_min : tpf; -+ tpf = FRACT_CMP(tpf, >, tpf_max) ? tpf_max : tpf; -+ -+ dev->capture.timeperframe = tpf; -+ parm->parm.capture.timeperframe = tpf; -+ parm->parm.capture.readbuffers = 1; -+ -+ fps_param.num = 0; /* Select variable fps, and then use -+ * FPS_RANGE to select the actual limits. -+ */ -+ fps_param.den = 1; -+ set_framerate_params(dev); -+ -+ return 0; -+} -+ -+static const struct v4l2_ioctl_ops camera0_ioctl_ops = { -+ /* overlay */ -+ .vidioc_enum_fmt_vid_overlay = vidioc_enum_fmt_vid_overlay, -+ .vidioc_g_fmt_vid_overlay = vidioc_g_fmt_vid_overlay, -+ .vidioc_try_fmt_vid_overlay = vidioc_try_fmt_vid_overlay, -+ .vidioc_s_fmt_vid_overlay = vidioc_s_fmt_vid_overlay, -+ .vidioc_overlay = vidioc_overlay, -+ .vidioc_g_fbuf = vidioc_g_fbuf, -+ -+ /* inputs */ -+ .vidioc_enum_input = vidioc_enum_input, -+ .vidioc_g_input = vidioc_g_input, -+ .vidioc_s_input = vidioc_s_input, -+ -+ /* capture */ -+ .vidioc_querycap = vidioc_querycap, -+ .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, -+ .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, -+ .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, -+ .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, -+ -+ /* buffer management */ -+ .vidioc_reqbufs = vb2_ioctl_reqbufs, -+ .vidioc_create_bufs = vb2_ioctl_create_bufs, -+ .vidioc_prepare_buf = vb2_ioctl_prepare_buf, -+ .vidioc_querybuf = vb2_ioctl_querybuf, -+ .vidioc_qbuf = vb2_ioctl_qbuf, -+ .vidioc_dqbuf = vb2_ioctl_dqbuf, -+ .vidioc_enum_framesizes = vidioc_enum_framesizes, -+ .vidioc_enum_frameintervals = vidioc_enum_frameintervals, -+ .vidioc_g_parm = vidioc_g_parm, -+ .vidioc_s_parm = vidioc_s_parm, -+ .vidioc_streamon = vb2_ioctl_streamon, -+ .vidioc_streamoff = vb2_ioctl_streamoff, -+ -+ .vidioc_log_status = v4l2_ctrl_log_status, -+ .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, -+ .vidioc_unsubscribe_event = v4l2_event_unsubscribe, -+}; -+ -+static const struct v4l2_ioctl_ops camera0_ioctl_ops_gstreamer = { -+ /* overlay */ -+ .vidioc_enum_fmt_vid_overlay = vidioc_enum_fmt_vid_overlay, -+ .vidioc_g_fmt_vid_overlay = vidioc_g_fmt_vid_overlay, -+ .vidioc_try_fmt_vid_overlay = vidioc_try_fmt_vid_overlay, -+ .vidioc_s_fmt_vid_overlay = vidioc_s_fmt_vid_overlay, -+ .vidioc_overlay = vidioc_overlay, -+ .vidioc_g_fbuf = vidioc_g_fbuf, -+ -+ /* inputs */ -+ .vidioc_enum_input = vidioc_enum_input, -+ .vidioc_g_input = vidioc_g_input, -+ .vidioc_s_input = vidioc_s_input, -+ -+ /* capture */ -+ .vidioc_querycap = vidioc_querycap, -+ .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, -+ .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, -+ .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, -+ .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, -+ -+ /* buffer management */ -+ .vidioc_reqbufs = vb2_ioctl_reqbufs, -+ .vidioc_create_bufs = vb2_ioctl_create_bufs, -+ .vidioc_prepare_buf = vb2_ioctl_prepare_buf, -+ .vidioc_querybuf = vb2_ioctl_querybuf, -+ .vidioc_qbuf = vb2_ioctl_qbuf, -+ .vidioc_dqbuf = vb2_ioctl_dqbuf, -+ /* Remove this function ptr to fix gstreamer bug -+ .vidioc_enum_framesizes = vidioc_enum_framesizes, */ -+ .vidioc_enum_frameintervals = vidioc_enum_frameintervals, -+ .vidioc_g_parm = vidioc_g_parm, -+ .vidioc_s_parm = vidioc_s_parm, -+ .vidioc_streamon = vb2_ioctl_streamon, -+ .vidioc_streamoff = vb2_ioctl_streamoff, -+ -+ .vidioc_log_status = v4l2_ctrl_log_status, -+ .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, -+ .vidioc_unsubscribe_event = v4l2_event_unsubscribe, -+}; -+ -+/* ------------------------------------------------------------------ -+ Driver init/finalise -+ ------------------------------------------------------------------*/ -+ -+static const struct v4l2_file_operations camera0_fops = { -+ .owner = THIS_MODULE, -+ .open = v4l2_fh_open, -+ .release = vb2_fop_release, -+ .read = vb2_fop_read, -+ .poll = vb2_fop_poll, -+ .unlocked_ioctl = video_ioctl2, /* V4L2 ioctl handler */ -+ .mmap = vb2_fop_mmap, -+}; -+ -+static struct video_device vdev_template = { -+ .name = "camera0", -+ .fops = &camera0_fops, -+ .ioctl_ops = &camera0_ioctl_ops, -+ .release = video_device_release_empty, -+}; -+ -+static int set_camera_parameters(struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_component *camera) -+{ -+ int ret; -+ struct mmal_parameter_camera_config cam_config = { -+ .max_stills_w = MAX_WIDTH, -+ .max_stills_h = MAX_HEIGHT, -+ .stills_yuv422 = 1, -+ .one_shot_stills = 1, -+ .max_preview_video_w = (max_video_width > 1920) ? -+ max_video_width : 1920, -+ .max_preview_video_h = (max_video_height > 1088) ? -+ max_video_height : 1088, -+ .num_preview_video_frames = 3, -+ .stills_capture_circular_buffer_height = 0, -+ .fast_preview_resume = 0, -+ .use_stc_timestamp = MMAL_PARAM_TIMESTAMP_MODE_RAW_STC -+ }; -+ -+ ret = vchiq_mmal_port_parameter_set(instance, &camera->control, -+ MMAL_PARAMETER_CAMERA_CONFIG, -+ &cam_config, sizeof(cam_config)); -+ return ret; -+} -+ -+/* MMAL instance and component init */ -+static int __init mmal_init(struct bm2835_mmal_dev *dev) -+{ -+ int ret; -+ struct mmal_es_format *format; -+ u32 bool_true = 1; -+ -+ ret = vchiq_mmal_init(&dev->instance); -+ if (ret < 0) -+ return ret; -+ -+ /* get the camera component ready */ -+ ret = vchiq_mmal_component_init(dev->instance, "ril.camera", -+ &dev->component[MMAL_COMPONENT_CAMERA]); -+ if (ret < 0) -+ goto unreg_mmal; -+ -+ if (dev->component[MMAL_COMPONENT_CAMERA]->outputs < -+ MMAL_CAMERA_PORT_COUNT) { -+ ret = -EINVAL; -+ goto unreg_camera; -+ } -+ -+ ret = set_camera_parameters(dev->instance, -+ dev->component[MMAL_COMPONENT_CAMERA]); -+ if (ret < 0) -+ goto unreg_camera; -+ -+ format = -+ &dev->component[MMAL_COMPONENT_CAMERA]-> -+ output[MMAL_CAMERA_PORT_PREVIEW].format; -+ -+ format->encoding = MMAL_ENCODING_OPAQUE; -+ format->encoding_variant = MMAL_ENCODING_I420; -+ -+ format->es->video.width = 1024; -+ format->es->video.height = 768; -+ format->es->video.crop.x = 0; -+ format->es->video.crop.y = 0; -+ format->es->video.crop.width = 1024; -+ format->es->video.crop.height = 768; -+ format->es->video.frame_rate.num = 0; /* Rely on fps_range */ -+ format->es->video.frame_rate.den = 1; -+ -+ format = -+ &dev->component[MMAL_COMPONENT_CAMERA]-> -+ output[MMAL_CAMERA_PORT_VIDEO].format; -+ -+ format->encoding = MMAL_ENCODING_OPAQUE; -+ format->encoding_variant = MMAL_ENCODING_I420; -+ -+ format->es->video.width = 1024; -+ format->es->video.height = 768; -+ format->es->video.crop.x = 0; -+ format->es->video.crop.y = 0; -+ format->es->video.crop.width = 1024; -+ format->es->video.crop.height = 768; -+ format->es->video.frame_rate.num = 0; /* Rely on fps_range */ -+ format->es->video.frame_rate.den = 1; -+ -+ vchiq_mmal_port_parameter_set(dev->instance, -+ &dev->component[MMAL_COMPONENT_CAMERA]-> -+ output[MMAL_CAMERA_PORT_VIDEO], -+ MMAL_PARAMETER_NO_IMAGE_PADDING, -+ &bool_true, sizeof(bool_true)); -+ -+ format = -+ &dev->component[MMAL_COMPONENT_CAMERA]-> -+ output[MMAL_CAMERA_PORT_CAPTURE].format; -+ -+ format->encoding = MMAL_ENCODING_OPAQUE; -+ -+ format->es->video.width = 2592; -+ format->es->video.height = 1944; -+ format->es->video.crop.x = 0; -+ format->es->video.crop.y = 0; -+ format->es->video.crop.width = 2592; -+ format->es->video.crop.height = 1944; -+ format->es->video.frame_rate.num = 0; /* Rely on fps_range */ -+ format->es->video.frame_rate.den = 1; -+ -+ dev->capture.width = format->es->video.width; -+ dev->capture.height = format->es->video.height; -+ dev->capture.fmt = &formats[0]; -+ dev->capture.encode_component = NULL; -+ dev->capture.timeperframe = tpf_default; -+ dev->capture.enc_profile = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH; -+ dev->capture.enc_level = V4L2_MPEG_VIDEO_H264_LEVEL_4_0; -+ -+ vchiq_mmal_port_parameter_set(dev->instance, -+ &dev->component[MMAL_COMPONENT_CAMERA]-> -+ output[MMAL_CAMERA_PORT_CAPTURE], -+ MMAL_PARAMETER_NO_IMAGE_PADDING, -+ &bool_true, sizeof(bool_true)); -+ -+ /* get the preview component ready */ -+ ret = vchiq_mmal_component_init( -+ dev->instance, "ril.video_render", -+ &dev->component[MMAL_COMPONENT_PREVIEW]); -+ if (ret < 0) -+ goto unreg_camera; -+ -+ if (dev->component[MMAL_COMPONENT_PREVIEW]->inputs < 1) { -+ ret = -EINVAL; -+ pr_debug("too few input ports %d needed %d\n", -+ dev->component[MMAL_COMPONENT_PREVIEW]->inputs, 1); -+ goto unreg_preview; -+ } -+ -+ /* get the image encoder component ready */ -+ ret = vchiq_mmal_component_init( -+ dev->instance, "ril.image_encode", -+ &dev->component[MMAL_COMPONENT_IMAGE_ENCODE]); -+ if (ret < 0) -+ goto unreg_preview; -+ -+ if (dev->component[MMAL_COMPONENT_IMAGE_ENCODE]->inputs < 1) { -+ ret = -EINVAL; -+ v4l2_err(&dev->v4l2_dev, "too few input ports %d needed %d\n", -+ dev->component[MMAL_COMPONENT_IMAGE_ENCODE]->inputs, -+ 1); -+ goto unreg_image_encoder; -+ } -+ -+ /* get the video encoder component ready */ -+ ret = vchiq_mmal_component_init(dev->instance, "ril.video_encode", -+ &dev-> -+ component[MMAL_COMPONENT_VIDEO_ENCODE]); -+ if (ret < 0) -+ goto unreg_image_encoder; -+ -+ if (dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->inputs < 1) { -+ ret = -EINVAL; -+ v4l2_err(&dev->v4l2_dev, "too few input ports %d needed %d\n", -+ dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->inputs, -+ 1); -+ goto unreg_vid_encoder; -+ } -+ -+ { -+ struct vchiq_mmal_port *encoder_port = -+ &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0]; -+ encoder_port->format.encoding = MMAL_ENCODING_H264; -+ ret = vchiq_mmal_port_set_format(dev->instance, -+ encoder_port); -+ } -+ -+ { -+ unsigned int enable = 1; -+ vchiq_mmal_port_parameter_set( -+ dev->instance, -+ &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->control, -+ MMAL_PARAMETER_VIDEO_IMMUTABLE_INPUT, -+ &enable, sizeof(enable)); -+ -+ vchiq_mmal_port_parameter_set(dev->instance, -+ &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->control, -+ MMAL_PARAMETER_MINIMISE_FRAGMENTATION, -+ &enable, -+ sizeof(enable)); -+ } -+ ret = bm2835_mmal_set_all_camera_controls(dev); -+ if (ret < 0) -+ goto unreg_vid_encoder; -+ -+ return 0; -+ -+unreg_vid_encoder: -+ pr_err("Cleanup: Destroy video encoder\n"); -+ vchiq_mmal_component_finalise( -+ dev->instance, -+ dev->component[MMAL_COMPONENT_VIDEO_ENCODE]); -+ -+unreg_image_encoder: -+ pr_err("Cleanup: Destroy image encoder\n"); -+ vchiq_mmal_component_finalise( -+ dev->instance, -+ dev->component[MMAL_COMPONENT_IMAGE_ENCODE]); -+ -+unreg_preview: -+ pr_err("Cleanup: Destroy video render\n"); -+ vchiq_mmal_component_finalise(dev->instance, -+ dev->component[MMAL_COMPONENT_PREVIEW]); -+ -+unreg_camera: -+ pr_err("Cleanup: Destroy camera\n"); -+ vchiq_mmal_component_finalise(dev->instance, -+ dev->component[MMAL_COMPONENT_CAMERA]); -+ -+unreg_mmal: -+ vchiq_mmal_finalise(dev->instance); -+ return ret; -+} -+ -+static int __init bm2835_mmal_init_device(struct bm2835_mmal_dev *dev, -+ struct video_device *vfd) -+{ -+ int ret; -+ -+ *vfd = vdev_template; -+ if (gst_v4l2src_is_broken) { -+ v4l2_info(&dev->v4l2_dev, -+ "Work-around for gstreamer issue is active.\n"); -+ vfd->ioctl_ops = &camera0_ioctl_ops_gstreamer; -+ } -+ -+ vfd->v4l2_dev = &dev->v4l2_dev; -+ -+ vfd->lock = &dev->mutex; -+ -+ vfd->queue = &dev->capture.vb_vidq; -+ -+ /* video device needs to be able to access instance data */ -+ video_set_drvdata(vfd, dev); -+ -+ ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1); -+ if (ret < 0) -+ return ret; -+ -+ v4l2_info(vfd->v4l2_dev, -+ "V4L2 device registered as %s - stills mode > %dx%d\n", -+ video_device_node_name(vfd), max_video_width, max_video_height); -+ -+ return 0; -+} -+ -+static struct v4l2_format default_v4l2_format = { -+ .fmt.pix.pixelformat = V4L2_PIX_FMT_JPEG, -+ .fmt.pix.width = 1024, -+ .fmt.pix.bytesperline = 1024, -+ .fmt.pix.height = 768, -+ .fmt.pix.sizeimage = 1024*768, -+}; -+ -+static int __init bm2835_mmal_init(void) -+{ -+ int ret; -+ struct bm2835_mmal_dev *dev; -+ struct vb2_queue *q; -+ -+ dev = kzalloc(sizeof(*gdev), GFP_KERNEL); -+ if (!dev) -+ return -ENOMEM; -+ -+ /* setup device defaults */ -+ dev->overlay.w.left = 150; -+ dev->overlay.w.top = 50; -+ dev->overlay.w.width = 1024; -+ dev->overlay.w.height = 768; -+ dev->overlay.clipcount = 0; -+ dev->overlay.field = V4L2_FIELD_NONE; -+ -+ dev->capture.fmt = &formats[3]; /* JPEG */ -+ -+ /* v4l device registration */ -+ snprintf(dev->v4l2_dev.name, sizeof(dev->v4l2_dev.name), -+ "%s", BM2835_MMAL_MODULE_NAME); -+ ret = v4l2_device_register(NULL, &dev->v4l2_dev); -+ if (ret) -+ goto free_dev; -+ -+ /* setup v4l controls */ -+ ret = bm2835_mmal_init_controls(dev, &dev->ctrl_handler); -+ if (ret < 0) -+ goto unreg_dev; -+ dev->v4l2_dev.ctrl_handler = &dev->ctrl_handler; -+ -+ /* mmal init */ -+ ret = mmal_init(dev); -+ if (ret < 0) -+ goto unreg_dev; -+ -+ /* initialize queue */ -+ q = &dev->capture.vb_vidq; -+ memset(q, 0, sizeof(*q)); -+ q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; -+ q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_READ; -+ q->drv_priv = dev; -+ q->buf_struct_size = sizeof(struct mmal_buffer); -+ q->ops = &bm2835_mmal_video_qops; -+ q->mem_ops = &vb2_vmalloc_memops; -+ q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; -+ ret = vb2_queue_init(q); -+ if (ret < 0) -+ goto unreg_dev; -+ -+ /* v4l2 core mutex used to protect all fops and v4l2 ioctls. */ -+ mutex_init(&dev->mutex); -+ -+ /* initialise video devices */ -+ ret = bm2835_mmal_init_device(dev, &dev->vdev); -+ if (ret < 0) -+ goto unreg_dev; -+ -+ /* Really want to call vidioc_s_fmt_vid_cap with the default -+ * format, but currently the APIs don't join up. -+ */ -+ ret = mmal_setup_components(dev, &default_v4l2_format); -+ if (ret < 0) { -+ v4l2_err(&dev->v4l2_dev, -+ "%s: could not setup components\n", __func__); -+ goto unreg_dev; -+ } -+ -+ v4l2_info(&dev->v4l2_dev, -+ "Broadcom 2835 MMAL video capture ver %s loaded.\n", -+ BM2835_MMAL_VERSION); -+ -+ gdev = dev; -+ return 0; -+ -+unreg_dev: -+ v4l2_ctrl_handler_free(&dev->ctrl_handler); -+ v4l2_device_unregister(&dev->v4l2_dev); -+ -+free_dev: -+ kfree(dev); -+ -+ v4l2_err(&dev->v4l2_dev, -+ "%s: error %d while loading driver\n", -+ BM2835_MMAL_MODULE_NAME, ret); -+ -+ return ret; -+} -+ -+static void __exit bm2835_mmal_exit(void) -+{ -+ if (!gdev) -+ return; -+ -+ v4l2_info(&gdev->v4l2_dev, "unregistering %s\n", -+ video_device_node_name(&gdev->vdev)); -+ -+ video_unregister_device(&gdev->vdev); -+ -+ if (gdev->capture.encode_component) { -+ v4l2_dbg(1, bcm2835_v4l2_debug, &gdev->v4l2_dev, -+ "mmal_exit - disconnect tunnel\n"); -+ vchiq_mmal_port_connect_tunnel(gdev->instance, -+ gdev->capture.camera_port, NULL); -+ vchiq_mmal_component_disable(gdev->instance, -+ gdev->capture.encode_component); -+ } -+ vchiq_mmal_component_disable(gdev->instance, -+ gdev->component[MMAL_COMPONENT_CAMERA]); -+ -+ vchiq_mmal_component_finalise(gdev->instance, -+ gdev-> -+ component[MMAL_COMPONENT_VIDEO_ENCODE]); -+ -+ vchiq_mmal_component_finalise(gdev->instance, -+ gdev-> -+ component[MMAL_COMPONENT_IMAGE_ENCODE]); -+ -+ vchiq_mmal_component_finalise(gdev->instance, -+ gdev->component[MMAL_COMPONENT_PREVIEW]); -+ -+ vchiq_mmal_component_finalise(gdev->instance, -+ gdev->component[MMAL_COMPONENT_CAMERA]); -+ -+ vchiq_mmal_finalise(gdev->instance); -+ -+ v4l2_ctrl_handler_free(&gdev->ctrl_handler); -+ -+ v4l2_device_unregister(&gdev->v4l2_dev); -+ -+ kfree(gdev); -+} -+ -+module_init(bm2835_mmal_init); -+module_exit(bm2835_mmal_exit); -diff -Nur linux-4.1.13.orig/drivers/media/platform/bcm2835/bcm2835-camera.h linux-rpi/drivers/media/platform/bcm2835/bcm2835-camera.h ---- linux-4.1.13.orig/drivers/media/platform/bcm2835/bcm2835-camera.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/media/platform/bcm2835/bcm2835-camera.h 2015-11-29 09:42:37.835237156 +0100 -@@ -0,0 +1,126 @@ -+/* -+ * Broadcom BM2835 V4L2 driver -+ * -+ * Copyright © 2013 Raspberry Pi (Trading) Ltd. -+ * -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file COPYING in the main directory of this archive -+ * for more details. -+ * -+ * Authors: Vincent Sanders -+ * Dave Stevenson -+ * Simon Mellor -+ * Luke Diamand -+ * -+ * core driver device -+ */ -+ -+#define V4L2_CTRL_COUNT 28 /* number of v4l controls */ -+ -+enum { -+ MMAL_COMPONENT_CAMERA = 0, -+ MMAL_COMPONENT_PREVIEW, -+ MMAL_COMPONENT_IMAGE_ENCODE, -+ MMAL_COMPONENT_VIDEO_ENCODE, -+ MMAL_COMPONENT_COUNT -+}; -+ -+enum { -+ MMAL_CAMERA_PORT_PREVIEW = 0, -+ MMAL_CAMERA_PORT_VIDEO, -+ MMAL_CAMERA_PORT_CAPTURE, -+ MMAL_CAMERA_PORT_COUNT -+}; -+ -+#define PREVIEW_LAYER 2 -+ -+extern int bcm2835_v4l2_debug; -+ -+struct bm2835_mmal_dev { -+ /* v4l2 devices */ -+ struct v4l2_device v4l2_dev; -+ struct video_device vdev; -+ struct mutex mutex; -+ -+ /* controls */ -+ struct v4l2_ctrl_handler ctrl_handler; -+ struct v4l2_ctrl *ctrls[V4L2_CTRL_COUNT]; -+ enum v4l2_scene_mode scene_mode; -+ struct mmal_colourfx colourfx; -+ int hflip; -+ int vflip; -+ int red_gain; -+ int blue_gain; -+ enum mmal_parameter_exposuremode exposure_mode_user; -+ enum v4l2_exposure_auto_type exposure_mode_v4l2_user; -+ /* active exposure mode may differ if selected via a scene mode */ -+ enum mmal_parameter_exposuremode exposure_mode_active; -+ enum mmal_parameter_exposuremeteringmode metering_mode; -+ unsigned int manual_shutter_speed; -+ bool exp_auto_priority; -+ -+ /* allocated mmal instance and components */ -+ struct vchiq_mmal_instance *instance; -+ struct vchiq_mmal_component *component[MMAL_COMPONENT_COUNT]; -+ int camera_use_count; -+ -+ struct v4l2_window overlay; -+ -+ struct { -+ unsigned int width; /* width */ -+ unsigned int height; /* height */ -+ unsigned int stride; /* stride */ -+ unsigned int buffersize; /* buffer size with padding */ -+ struct mmal_fmt *fmt; -+ struct v4l2_fract timeperframe; -+ -+ /* H264 encode bitrate */ -+ int encode_bitrate; -+ /* H264 bitrate mode. CBR/VBR */ -+ int encode_bitrate_mode; -+ /* H264 profile */ -+ enum v4l2_mpeg_video_h264_profile enc_profile; -+ /* H264 level */ -+ enum v4l2_mpeg_video_h264_level enc_level; -+ /* JPEG Q-factor */ -+ int q_factor; -+ -+ struct vb2_queue vb_vidq; -+ -+ /* VC start timestamp for streaming */ -+ s64 vc_start_timestamp; -+ /* Kernel start timestamp for streaming */ -+ struct timeval kernel_start_ts; -+ -+ struct vchiq_mmal_port *port; /* port being used for capture */ -+ /* camera port being used for capture */ -+ struct vchiq_mmal_port *camera_port; -+ /* component being used for encode */ -+ struct vchiq_mmal_component *encode_component; -+ /* number of frames remaining which driver should capture */ -+ unsigned int frame_count; -+ /* last frame completion */ -+ struct completion frame_cmplt; -+ -+ } capture; -+ -+}; -+ -+int bm2835_mmal_init_controls( -+ struct bm2835_mmal_dev *dev, -+ struct v4l2_ctrl_handler *hdl); -+ -+int bm2835_mmal_set_all_camera_controls(struct bm2835_mmal_dev *dev); -+int set_framerate_params(struct bm2835_mmal_dev *dev); -+ -+/* Debug helpers */ -+ -+#define v4l2_dump_pix_format(level, debug, dev, pix_fmt, desc) \ -+{ \ -+ v4l2_dbg(level, debug, dev, \ -+"%s: w %u h %u field %u pfmt 0x%x bpl %u sz_img %u colorspace 0x%x priv %u\n", \ -+ desc == NULL ? "" : desc, \ -+ (pix_fmt)->width, (pix_fmt)->height, (pix_fmt)->field, \ -+ (pix_fmt)->pixelformat, (pix_fmt)->bytesperline, \ -+ (pix_fmt)->sizeimage, (pix_fmt)->colorspace, (pix_fmt)->priv); \ -+} -diff -Nur linux-4.1.13.orig/drivers/media/platform/bcm2835/controls.c linux-rpi/drivers/media/platform/bcm2835/controls.c ---- linux-4.1.13.orig/drivers/media/platform/bcm2835/controls.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/media/platform/bcm2835/controls.c 2015-11-29 09:42:37.835237156 +0100 -@@ -0,0 +1,1324 @@ -+/* -+ * Broadcom BM2835 V4L2 driver -+ * -+ * Copyright © 2013 Raspberry Pi (Trading) Ltd. -+ * -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file COPYING in the main directory of this archive -+ * for more details. -+ * -+ * Authors: Vincent Sanders -+ * Dave Stevenson -+ * Simon Mellor -+ * Luke Diamand -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "mmal-common.h" -+#include "mmal-vchiq.h" -+#include "mmal-parameters.h" -+#include "bcm2835-camera.h" -+ -+/* The supported V4L2_CID_AUTO_EXPOSURE_BIAS values are from -4.0 to +4.0. -+ * MMAL values are in 1/6th increments so the MMAL range is -24 to +24. -+ * V4L2 docs say value "is expressed in terms of EV, drivers should interpret -+ * the values as 0.001 EV units, where the value 1000 stands for +1 EV." -+ * V4L2 is limited to a max of 32 values in a menu, so count in 1/3rds from -+ * -4 to +4 -+ */ -+static const s64 ev_bias_qmenu[] = { -+ -4000, -3667, -3333, -+ -3000, -2667, -2333, -+ -2000, -1667, -1333, -+ -1000, -667, -333, -+ 0, 333, 667, -+ 1000, 1333, 1667, -+ 2000, 2333, 2667, -+ 3000, 3333, 3667, -+ 4000 -+}; -+ -+/* Supported ISO values -+ * ISOO = auto ISO -+ */ -+static const s64 iso_qmenu[] = { -+ 0, 100, 200, 400, 800, -+}; -+ -+static const s64 mains_freq_qmenu[] = { -+ V4L2_CID_POWER_LINE_FREQUENCY_DISABLED, -+ V4L2_CID_POWER_LINE_FREQUENCY_50HZ, -+ V4L2_CID_POWER_LINE_FREQUENCY_60HZ, -+ V4L2_CID_POWER_LINE_FREQUENCY_AUTO -+}; -+ -+/* Supported video encode modes */ -+static const s64 bitrate_mode_qmenu[] = { -+ (s64)V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, -+ (s64)V4L2_MPEG_VIDEO_BITRATE_MODE_CBR, -+}; -+ -+enum bm2835_mmal_ctrl_type { -+ MMAL_CONTROL_TYPE_STD, -+ MMAL_CONTROL_TYPE_STD_MENU, -+ MMAL_CONTROL_TYPE_INT_MENU, -+ MMAL_CONTROL_TYPE_CLUSTER, /* special cluster entry */ -+}; -+ -+struct bm2835_mmal_v4l2_ctrl; -+ -+typedef int(bm2835_mmal_v4l2_ctrl_cb)( -+ struct bm2835_mmal_dev *dev, -+ struct v4l2_ctrl *ctrl, -+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl); -+ -+struct bm2835_mmal_v4l2_ctrl { -+ u32 id; /* v4l2 control identifier */ -+ enum bm2835_mmal_ctrl_type type; -+ /* control minimum value or -+ * mask for MMAL_CONTROL_TYPE_STD_MENU */ -+ s32 min; -+ s32 max; /* maximum value of control */ -+ s32 def; /* default value of control */ -+ s32 step; /* step size of the control */ -+ const s64 *imenu; /* integer menu array */ -+ u32 mmal_id; /* mmal parameter id */ -+ bm2835_mmal_v4l2_ctrl_cb *setter; -+ bool ignore_errors; -+}; -+ -+struct v4l2_to_mmal_effects_setting { -+ u32 v4l2_effect; -+ u32 mmal_effect; -+ s32 col_fx_enable; -+ s32 col_fx_fixed_cbcr; -+ u32 u; -+ u32 v; -+ u32 num_effect_params; -+ u32 effect_params[MMAL_MAX_IMAGEFX_PARAMETERS]; -+}; -+ -+static const struct v4l2_to_mmal_effects_setting -+ v4l2_to_mmal_effects_values[] = { -+ { V4L2_COLORFX_NONE, MMAL_PARAM_IMAGEFX_NONE, -+ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} }, -+ { V4L2_COLORFX_BW, MMAL_PARAM_IMAGEFX_NONE, -+ 1, 0, 128, 128, 0, {0, 0, 0, 0, 0} }, -+ { V4L2_COLORFX_SEPIA, MMAL_PARAM_IMAGEFX_NONE, -+ 1, 0, 87, 151, 0, {0, 0, 0, 0, 0} }, -+ { V4L2_COLORFX_NEGATIVE, MMAL_PARAM_IMAGEFX_NEGATIVE, -+ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} }, -+ { V4L2_COLORFX_EMBOSS, MMAL_PARAM_IMAGEFX_EMBOSS, -+ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} }, -+ { V4L2_COLORFX_SKETCH, MMAL_PARAM_IMAGEFX_SKETCH, -+ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} }, -+ { V4L2_COLORFX_SKY_BLUE, MMAL_PARAM_IMAGEFX_PASTEL, -+ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} }, -+ { V4L2_COLORFX_GRASS_GREEN, MMAL_PARAM_IMAGEFX_WATERCOLOUR, -+ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} }, -+ { V4L2_COLORFX_SKIN_WHITEN, MMAL_PARAM_IMAGEFX_WASHEDOUT, -+ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} }, -+ { V4L2_COLORFX_VIVID, MMAL_PARAM_IMAGEFX_SATURATION, -+ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} }, -+ { V4L2_COLORFX_AQUA, MMAL_PARAM_IMAGEFX_NONE, -+ 1, 0, 171, 121, 0, {0, 0, 0, 0, 0} }, -+ { V4L2_COLORFX_ART_FREEZE, MMAL_PARAM_IMAGEFX_HATCH, -+ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} }, -+ { V4L2_COLORFX_SILHOUETTE, MMAL_PARAM_IMAGEFX_FILM, -+ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} }, -+ { V4L2_COLORFX_SOLARIZATION, MMAL_PARAM_IMAGEFX_SOLARIZE, -+ 0, 0, 0, 0, 5, {1, 128, 160, 160, 48} }, -+ { V4L2_COLORFX_ANTIQUE, MMAL_PARAM_IMAGEFX_COLOURBALANCE, -+ 0, 0, 0, 0, 3, {108, 274, 238, 0, 0} }, -+ { V4L2_COLORFX_SET_CBCR, MMAL_PARAM_IMAGEFX_NONE, -+ 1, 1, 0, 0, 0, {0, 0, 0, 0, 0} } -+}; -+ -+struct v4l2_mmal_scene_config { -+ enum v4l2_scene_mode v4l2_scene; -+ enum mmal_parameter_exposuremode exposure_mode; -+ enum mmal_parameter_exposuremeteringmode metering_mode; -+}; -+ -+static const struct v4l2_mmal_scene_config scene_configs[] = { -+ /* V4L2_SCENE_MODE_NONE automatically added */ -+ { -+ V4L2_SCENE_MODE_NIGHT, -+ MMAL_PARAM_EXPOSUREMODE_NIGHT, -+ MMAL_PARAM_EXPOSUREMETERINGMODE_AVERAGE -+ }, -+ { -+ V4L2_SCENE_MODE_SPORTS, -+ MMAL_PARAM_EXPOSUREMODE_SPORTS, -+ MMAL_PARAM_EXPOSUREMETERINGMODE_AVERAGE -+ }, -+}; -+ -+/* control handlers*/ -+ -+static int ctrl_set_rational(struct bm2835_mmal_dev *dev, -+ struct v4l2_ctrl *ctrl, -+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) -+{ -+ struct mmal_parameter_rational rational_value; -+ struct vchiq_mmal_port *control; -+ -+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; -+ -+ rational_value.num = ctrl->val; -+ rational_value.den = 100; -+ -+ return vchiq_mmal_port_parameter_set(dev->instance, control, -+ mmal_ctrl->mmal_id, -+ &rational_value, -+ sizeof(rational_value)); -+} -+ -+static int ctrl_set_value(struct bm2835_mmal_dev *dev, -+ struct v4l2_ctrl *ctrl, -+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) -+{ -+ u32 u32_value; -+ struct vchiq_mmal_port *control; -+ -+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; -+ -+ u32_value = ctrl->val; -+ -+ return vchiq_mmal_port_parameter_set(dev->instance, control, -+ mmal_ctrl->mmal_id, -+ &u32_value, sizeof(u32_value)); -+} -+ -+static int ctrl_set_value_menu(struct bm2835_mmal_dev *dev, -+ struct v4l2_ctrl *ctrl, -+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) -+{ -+ u32 u32_value; -+ struct vchiq_mmal_port *control; -+ -+ if (ctrl->val > mmal_ctrl->max || ctrl->val < mmal_ctrl->min) -+ return 1; -+ -+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; -+ -+ u32_value = mmal_ctrl->imenu[ctrl->val]; -+ -+ return vchiq_mmal_port_parameter_set(dev->instance, control, -+ mmal_ctrl->mmal_id, -+ &u32_value, sizeof(u32_value)); -+} -+ -+static int ctrl_set_value_ev(struct bm2835_mmal_dev *dev, -+ struct v4l2_ctrl *ctrl, -+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) -+{ -+ s32 s32_value; -+ struct vchiq_mmal_port *control; -+ -+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; -+ -+ s32_value = (ctrl->val-12)*2; /* Convert from index to 1/6ths */ -+ -+ return vchiq_mmal_port_parameter_set(dev->instance, control, -+ mmal_ctrl->mmal_id, -+ &s32_value, sizeof(s32_value)); -+} -+ -+static int ctrl_set_rotate(struct bm2835_mmal_dev *dev, -+ struct v4l2_ctrl *ctrl, -+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) -+{ -+ int ret; -+ u32 u32_value; -+ struct vchiq_mmal_component *camera; -+ -+ camera = dev->component[MMAL_COMPONENT_CAMERA]; -+ -+ u32_value = ((ctrl->val % 360) / 90) * 90; -+ -+ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[0], -+ mmal_ctrl->mmal_id, -+ &u32_value, sizeof(u32_value)); -+ if (ret < 0) -+ return ret; -+ -+ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[1], -+ mmal_ctrl->mmal_id, -+ &u32_value, sizeof(u32_value)); -+ if (ret < 0) -+ return ret; -+ -+ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[2], -+ mmal_ctrl->mmal_id, -+ &u32_value, sizeof(u32_value)); -+ -+ return ret; -+} -+ -+static int ctrl_set_flip(struct bm2835_mmal_dev *dev, -+ struct v4l2_ctrl *ctrl, -+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) -+{ -+ int ret; -+ u32 u32_value; -+ struct vchiq_mmal_component *camera; -+ -+ if (ctrl->id == V4L2_CID_HFLIP) -+ dev->hflip = ctrl->val; -+ else -+ dev->vflip = ctrl->val; -+ -+ camera = dev->component[MMAL_COMPONENT_CAMERA]; -+ -+ if (dev->hflip && dev->vflip) -+ u32_value = MMAL_PARAM_MIRROR_BOTH; -+ else if (dev->hflip) -+ u32_value = MMAL_PARAM_MIRROR_HORIZONTAL; -+ else if (dev->vflip) -+ u32_value = MMAL_PARAM_MIRROR_VERTICAL; -+ else -+ u32_value = MMAL_PARAM_MIRROR_NONE; -+ -+ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[0], -+ mmal_ctrl->mmal_id, -+ &u32_value, sizeof(u32_value)); -+ if (ret < 0) -+ return ret; -+ -+ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[1], -+ mmal_ctrl->mmal_id, -+ &u32_value, sizeof(u32_value)); -+ if (ret < 0) -+ return ret; -+ -+ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[2], -+ mmal_ctrl->mmal_id, -+ &u32_value, sizeof(u32_value)); -+ -+ return ret; -+ -+} -+ -+static int ctrl_set_exposure(struct bm2835_mmal_dev *dev, -+ struct v4l2_ctrl *ctrl, -+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) -+{ -+ enum mmal_parameter_exposuremode exp_mode = dev->exposure_mode_user; -+ u32 shutter_speed = 0; -+ struct vchiq_mmal_port *control; -+ int ret = 0; -+ -+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; -+ -+ if (mmal_ctrl->mmal_id == MMAL_PARAMETER_SHUTTER_SPEED) { -+ /* V4L2 is in 100usec increments. -+ * MMAL is 1usec. -+ */ -+ dev->manual_shutter_speed = ctrl->val * 100; -+ } else if (mmal_ctrl->mmal_id == MMAL_PARAMETER_EXPOSURE_MODE) { -+ switch (ctrl->val) { -+ case V4L2_EXPOSURE_AUTO: -+ exp_mode = MMAL_PARAM_EXPOSUREMODE_AUTO; -+ break; -+ -+ case V4L2_EXPOSURE_MANUAL: -+ exp_mode = MMAL_PARAM_EXPOSUREMODE_OFF; -+ break; -+ } -+ dev->exposure_mode_user = exp_mode; -+ dev->exposure_mode_v4l2_user = ctrl->val; -+ } else if (mmal_ctrl->id == V4L2_CID_EXPOSURE_AUTO_PRIORITY) { -+ dev->exp_auto_priority = ctrl->val; -+ } -+ -+ if (dev->scene_mode == V4L2_SCENE_MODE_NONE) { -+ if (exp_mode == MMAL_PARAM_EXPOSUREMODE_OFF) -+ shutter_speed = dev->manual_shutter_speed; -+ -+ ret = vchiq_mmal_port_parameter_set(dev->instance, -+ control, -+ MMAL_PARAMETER_SHUTTER_SPEED, -+ &shutter_speed, -+ sizeof(shutter_speed)); -+ ret += vchiq_mmal_port_parameter_set(dev->instance, -+ control, -+ MMAL_PARAMETER_EXPOSURE_MODE, -+ &exp_mode, -+ sizeof(u32)); -+ dev->exposure_mode_active = exp_mode; -+ } -+ /* exposure_dynamic_framerate (V4L2_CID_EXPOSURE_AUTO_PRIORITY) should -+ * always apply irrespective of scene mode. -+ */ -+ ret += set_framerate_params(dev); -+ -+ return ret; -+} -+ -+static int ctrl_set_metering_mode(struct bm2835_mmal_dev *dev, -+ struct v4l2_ctrl *ctrl, -+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) -+{ -+ switch (ctrl->val) { -+ case V4L2_EXPOSURE_METERING_AVERAGE: -+ dev->metering_mode = MMAL_PARAM_EXPOSUREMETERINGMODE_AVERAGE; -+ break; -+ -+ case V4L2_EXPOSURE_METERING_CENTER_WEIGHTED: -+ dev->metering_mode = MMAL_PARAM_EXPOSUREMETERINGMODE_BACKLIT; -+ break; -+ -+ case V4L2_EXPOSURE_METERING_SPOT: -+ dev->metering_mode = MMAL_PARAM_EXPOSUREMETERINGMODE_SPOT; -+ break; -+ -+ /* todo matrix weighting not added to Linux API till 3.9 -+ case V4L2_EXPOSURE_METERING_MATRIX: -+ dev->metering_mode = MMAL_PARAM_EXPOSUREMETERINGMODE_MATRIX; -+ break; -+ */ -+ -+ } -+ -+ if (dev->scene_mode == V4L2_SCENE_MODE_NONE) { -+ struct vchiq_mmal_port *control; -+ u32 u32_value = dev->metering_mode; -+ -+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; -+ -+ return vchiq_mmal_port_parameter_set(dev->instance, control, -+ mmal_ctrl->mmal_id, -+ &u32_value, sizeof(u32_value)); -+ } else -+ return 0; -+} -+ -+static int ctrl_set_flicker_avoidance(struct bm2835_mmal_dev *dev, -+ struct v4l2_ctrl *ctrl, -+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) -+{ -+ u32 u32_value; -+ struct vchiq_mmal_port *control; -+ -+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; -+ -+ switch (ctrl->val) { -+ case V4L2_CID_POWER_LINE_FREQUENCY_DISABLED: -+ u32_value = MMAL_PARAM_FLICKERAVOID_OFF; -+ break; -+ case V4L2_CID_POWER_LINE_FREQUENCY_50HZ: -+ u32_value = MMAL_PARAM_FLICKERAVOID_50HZ; -+ break; -+ case V4L2_CID_POWER_LINE_FREQUENCY_60HZ: -+ u32_value = MMAL_PARAM_FLICKERAVOID_60HZ; -+ break; -+ case V4L2_CID_POWER_LINE_FREQUENCY_AUTO: -+ u32_value = MMAL_PARAM_FLICKERAVOID_AUTO; -+ break; -+ } -+ -+ return vchiq_mmal_port_parameter_set(dev->instance, control, -+ mmal_ctrl->mmal_id, -+ &u32_value, sizeof(u32_value)); -+} -+ -+static int ctrl_set_awb_mode(struct bm2835_mmal_dev *dev, -+ struct v4l2_ctrl *ctrl, -+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) -+{ -+ u32 u32_value; -+ struct vchiq_mmal_port *control; -+ -+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; -+ -+ switch (ctrl->val) { -+ case V4L2_WHITE_BALANCE_MANUAL: -+ u32_value = MMAL_PARAM_AWBMODE_OFF; -+ break; -+ -+ case V4L2_WHITE_BALANCE_AUTO: -+ u32_value = MMAL_PARAM_AWBMODE_AUTO; -+ break; -+ -+ case V4L2_WHITE_BALANCE_INCANDESCENT: -+ u32_value = MMAL_PARAM_AWBMODE_INCANDESCENT; -+ break; -+ -+ case V4L2_WHITE_BALANCE_FLUORESCENT: -+ u32_value = MMAL_PARAM_AWBMODE_FLUORESCENT; -+ break; -+ -+ case V4L2_WHITE_BALANCE_FLUORESCENT_H: -+ u32_value = MMAL_PARAM_AWBMODE_TUNGSTEN; -+ break; -+ -+ case V4L2_WHITE_BALANCE_HORIZON: -+ u32_value = MMAL_PARAM_AWBMODE_HORIZON; -+ break; -+ -+ case V4L2_WHITE_BALANCE_DAYLIGHT: -+ u32_value = MMAL_PARAM_AWBMODE_SUNLIGHT; -+ break; -+ -+ case V4L2_WHITE_BALANCE_FLASH: -+ u32_value = MMAL_PARAM_AWBMODE_FLASH; -+ break; -+ -+ case V4L2_WHITE_BALANCE_CLOUDY: -+ u32_value = MMAL_PARAM_AWBMODE_CLOUDY; -+ break; -+ -+ case V4L2_WHITE_BALANCE_SHADE: -+ u32_value = MMAL_PARAM_AWBMODE_SHADE; -+ break; -+ -+ } -+ -+ return vchiq_mmal_port_parameter_set(dev->instance, control, -+ mmal_ctrl->mmal_id, -+ &u32_value, sizeof(u32_value)); -+} -+ -+static int ctrl_set_awb_gains(struct bm2835_mmal_dev *dev, -+ struct v4l2_ctrl *ctrl, -+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) -+{ -+ struct vchiq_mmal_port *control; -+ struct mmal_parameter_awbgains gains; -+ -+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; -+ -+ if (ctrl->id == V4L2_CID_RED_BALANCE) -+ dev->red_gain = ctrl->val; -+ else if (ctrl->id == V4L2_CID_BLUE_BALANCE) -+ dev->blue_gain = ctrl->val; -+ -+ gains.r_gain.num = dev->red_gain; -+ gains.b_gain.num = dev->blue_gain; -+ gains.r_gain.den = gains.b_gain.den = 1000; -+ -+ return vchiq_mmal_port_parameter_set(dev->instance, control, -+ mmal_ctrl->mmal_id, -+ &gains, sizeof(gains)); -+} -+ -+static int ctrl_set_image_effect(struct bm2835_mmal_dev *dev, -+ struct v4l2_ctrl *ctrl, -+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) -+{ -+ int ret = -EINVAL; -+ int i, j; -+ struct vchiq_mmal_port *control; -+ struct mmal_parameter_imagefx_parameters imagefx; -+ -+ for (i = 0; i < ARRAY_SIZE(v4l2_to_mmal_effects_values); i++) { -+ if (ctrl->val == v4l2_to_mmal_effects_values[i].v4l2_effect) { -+ -+ imagefx.effect = -+ v4l2_to_mmal_effects_values[i].mmal_effect; -+ imagefx.num_effect_params = -+ v4l2_to_mmal_effects_values[i].num_effect_params; -+ -+ if (imagefx.num_effect_params > MMAL_MAX_IMAGEFX_PARAMETERS) -+ imagefx.num_effect_params = MMAL_MAX_IMAGEFX_PARAMETERS; -+ -+ for (j = 0; j < imagefx.num_effect_params; j++) -+ imagefx.effect_parameter[j] = -+ v4l2_to_mmal_effects_values[i].effect_params[j]; -+ -+ dev->colourfx.enable = -+ v4l2_to_mmal_effects_values[i].col_fx_enable; -+ if (!v4l2_to_mmal_effects_values[i].col_fx_fixed_cbcr) { -+ dev->colourfx.u = -+ v4l2_to_mmal_effects_values[i].u; -+ dev->colourfx.v = -+ v4l2_to_mmal_effects_values[i].v; -+ } -+ -+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; -+ -+ ret = vchiq_mmal_port_parameter_set( -+ dev->instance, control, -+ MMAL_PARAMETER_IMAGE_EFFECT_PARAMETERS, -+ &imagefx, sizeof(imagefx)); -+ if (ret) -+ goto exit; -+ -+ ret = vchiq_mmal_port_parameter_set( -+ dev->instance, control, -+ MMAL_PARAMETER_COLOUR_EFFECT, -+ &dev->colourfx, sizeof(dev->colourfx)); -+ } -+ } -+ -+exit: -+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, -+ "mmal_ctrl:%p ctrl id:0x%x ctrl val:%d imagefx:0x%x color_effect:%s u:%d v:%d ret %d(%d)\n", -+ mmal_ctrl, ctrl->id, ctrl->val, imagefx.effect, -+ dev->colourfx.enable ? "true" : "false", -+ dev->colourfx.u, dev->colourfx.v, -+ ret, (ret == 0 ? 0 : -EINVAL)); -+ return (ret == 0 ? 0 : EINVAL); -+} -+ -+static int ctrl_set_colfx(struct bm2835_mmal_dev *dev, -+ struct v4l2_ctrl *ctrl, -+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) -+{ -+ int ret = -EINVAL; -+ struct vchiq_mmal_port *control; -+ -+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; -+ -+ dev->colourfx.enable = (ctrl->val & 0xff00) >> 8; -+ dev->colourfx.enable = ctrl->val & 0xff; -+ -+ ret = vchiq_mmal_port_parameter_set(dev->instance, control, -+ MMAL_PARAMETER_COLOUR_EFFECT, -+ &dev->colourfx, sizeof(dev->colourfx)); -+ -+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, -+ "%s: After: mmal_ctrl:%p ctrl id:0x%x ctrl val:%d ret %d(%d)\n", -+ __func__, mmal_ctrl, ctrl->id, ctrl->val, ret, -+ (ret == 0 ? 0 : -EINVAL)); -+ return (ret == 0 ? 0 : EINVAL); -+} -+ -+static int ctrl_set_bitrate(struct bm2835_mmal_dev *dev, -+ struct v4l2_ctrl *ctrl, -+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) -+{ -+ int ret; -+ struct vchiq_mmal_port *encoder_out; -+ -+ dev->capture.encode_bitrate = ctrl->val; -+ -+ encoder_out = &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0]; -+ -+ ret = vchiq_mmal_port_parameter_set(dev->instance, encoder_out, -+ mmal_ctrl->mmal_id, -+ &ctrl->val, sizeof(ctrl->val)); -+ ret = 0; -+ return ret; -+} -+ -+static int ctrl_set_bitrate_mode(struct bm2835_mmal_dev *dev, -+ struct v4l2_ctrl *ctrl, -+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) -+{ -+ u32 bitrate_mode; -+ struct vchiq_mmal_port *encoder_out; -+ -+ encoder_out = &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0]; -+ -+ dev->capture.encode_bitrate_mode = ctrl->val; -+ switch (ctrl->val) { -+ default: -+ case V4L2_MPEG_VIDEO_BITRATE_MODE_VBR: -+ bitrate_mode = MMAL_VIDEO_RATECONTROL_VARIABLE; -+ break; -+ case V4L2_MPEG_VIDEO_BITRATE_MODE_CBR: -+ bitrate_mode = MMAL_VIDEO_RATECONTROL_CONSTANT; -+ break; -+ } -+ -+ vchiq_mmal_port_parameter_set(dev->instance, encoder_out, -+ mmal_ctrl->mmal_id, -+ &bitrate_mode, -+ sizeof(bitrate_mode)); -+ return 0; -+} -+ -+static int ctrl_set_image_encode_output(struct bm2835_mmal_dev *dev, -+ struct v4l2_ctrl *ctrl, -+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) -+{ -+ u32 u32_value; -+ struct vchiq_mmal_port *jpeg_out; -+ -+ jpeg_out = &dev->component[MMAL_COMPONENT_IMAGE_ENCODE]->output[0]; -+ -+ u32_value = ctrl->val; -+ -+ return vchiq_mmal_port_parameter_set(dev->instance, jpeg_out, -+ mmal_ctrl->mmal_id, -+ &u32_value, sizeof(u32_value)); -+} -+ -+static int ctrl_set_video_encode_param_output(struct bm2835_mmal_dev *dev, -+ struct v4l2_ctrl *ctrl, -+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) -+{ -+ u32 u32_value; -+ struct vchiq_mmal_port *vid_enc_ctl; -+ -+ vid_enc_ctl = &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0]; -+ -+ u32_value = ctrl->val; -+ -+ return vchiq_mmal_port_parameter_set(dev->instance, vid_enc_ctl, -+ mmal_ctrl->mmal_id, -+ &u32_value, sizeof(u32_value)); -+} -+ -+static int ctrl_set_video_encode_profile_level(struct bm2835_mmal_dev *dev, -+ struct v4l2_ctrl *ctrl, -+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) -+{ -+ struct mmal_parameter_video_profile param; -+ int ret = 0; -+ -+ if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_PROFILE) { -+ switch (ctrl->val) { -+ case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE: -+ case V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE: -+ case V4L2_MPEG_VIDEO_H264_PROFILE_MAIN: -+ case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH: -+ dev->capture.enc_profile = ctrl->val; -+ break; -+ default: -+ ret = -EINVAL; -+ break; -+ } -+ } else if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_LEVEL) { -+ switch (ctrl->val) { -+ case V4L2_MPEG_VIDEO_H264_LEVEL_1_0: -+ case V4L2_MPEG_VIDEO_H264_LEVEL_1B: -+ case V4L2_MPEG_VIDEO_H264_LEVEL_1_1: -+ case V4L2_MPEG_VIDEO_H264_LEVEL_1_2: -+ case V4L2_MPEG_VIDEO_H264_LEVEL_1_3: -+ case V4L2_MPEG_VIDEO_H264_LEVEL_2_0: -+ case V4L2_MPEG_VIDEO_H264_LEVEL_2_1: -+ case V4L2_MPEG_VIDEO_H264_LEVEL_2_2: -+ case V4L2_MPEG_VIDEO_H264_LEVEL_3_0: -+ case V4L2_MPEG_VIDEO_H264_LEVEL_3_1: -+ case V4L2_MPEG_VIDEO_H264_LEVEL_3_2: -+ case V4L2_MPEG_VIDEO_H264_LEVEL_4_0: -+ dev->capture.enc_level = ctrl->val; -+ break; -+ default: -+ ret = -EINVAL; -+ break; -+ } -+ } -+ -+ if (!ret) { -+ switch (dev->capture.enc_profile) { -+ case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE: -+ param.profile = MMAL_VIDEO_PROFILE_H264_BASELINE; -+ break; -+ case V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE: -+ param.profile = -+ MMAL_VIDEO_PROFILE_H264_CONSTRAINED_BASELINE; -+ break; -+ case V4L2_MPEG_VIDEO_H264_PROFILE_MAIN: -+ param.profile = MMAL_VIDEO_PROFILE_H264_MAIN; -+ break; -+ case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH: -+ param.profile = MMAL_VIDEO_PROFILE_H264_HIGH; -+ break; -+ default: -+ /* Should never get here */ -+ break; -+ } -+ -+ switch (dev->capture.enc_level) { -+ case V4L2_MPEG_VIDEO_H264_LEVEL_1_0: -+ param.level = MMAL_VIDEO_LEVEL_H264_1; -+ break; -+ case V4L2_MPEG_VIDEO_H264_LEVEL_1B: -+ param.level = MMAL_VIDEO_LEVEL_H264_1b; -+ break; -+ case V4L2_MPEG_VIDEO_H264_LEVEL_1_1: -+ param.level = MMAL_VIDEO_LEVEL_H264_11; -+ break; -+ case V4L2_MPEG_VIDEO_H264_LEVEL_1_2: -+ param.level = MMAL_VIDEO_LEVEL_H264_12; -+ break; -+ case V4L2_MPEG_VIDEO_H264_LEVEL_1_3: -+ param.level = MMAL_VIDEO_LEVEL_H264_13; -+ break; -+ case V4L2_MPEG_VIDEO_H264_LEVEL_2_0: -+ param.level = MMAL_VIDEO_LEVEL_H264_2; -+ break; -+ case V4L2_MPEG_VIDEO_H264_LEVEL_2_1: -+ param.level = MMAL_VIDEO_LEVEL_H264_21; -+ break; -+ case V4L2_MPEG_VIDEO_H264_LEVEL_2_2: -+ param.level = MMAL_VIDEO_LEVEL_H264_22; -+ break; -+ case V4L2_MPEG_VIDEO_H264_LEVEL_3_0: -+ param.level = MMAL_VIDEO_LEVEL_H264_3; -+ break; -+ case V4L2_MPEG_VIDEO_H264_LEVEL_3_1: -+ param.level = MMAL_VIDEO_LEVEL_H264_31; -+ break; -+ case V4L2_MPEG_VIDEO_H264_LEVEL_3_2: -+ param.level = MMAL_VIDEO_LEVEL_H264_32; -+ break; -+ case V4L2_MPEG_VIDEO_H264_LEVEL_4_0: -+ param.level = MMAL_VIDEO_LEVEL_H264_4; -+ break; -+ default: -+ /* Should never get here */ -+ break; -+ } -+ -+ ret = vchiq_mmal_port_parameter_set(dev->instance, -+ &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0], -+ mmal_ctrl->mmal_id, -+ ¶m, sizeof(param)); -+ } -+ return ret; -+} -+ -+static int ctrl_set_scene_mode(struct bm2835_mmal_dev *dev, -+ struct v4l2_ctrl *ctrl, -+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) -+{ -+ int ret = 0; -+ int shutter_speed; -+ struct vchiq_mmal_port *control; -+ -+ v4l2_dbg(0, bcm2835_v4l2_debug, &dev->v4l2_dev, -+ "scene mode selected %d, was %d\n", ctrl->val, -+ dev->scene_mode); -+ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; -+ -+ if (ctrl->val == dev->scene_mode) -+ return 0; -+ -+ if (ctrl->val == V4L2_SCENE_MODE_NONE) { -+ /* Restore all user selections */ -+ dev->scene_mode = V4L2_SCENE_MODE_NONE; -+ -+ if (dev->exposure_mode_user == MMAL_PARAM_EXPOSUREMODE_OFF) -+ shutter_speed = dev->manual_shutter_speed; -+ else -+ shutter_speed = 0; -+ -+ v4l2_dbg(0, bcm2835_v4l2_debug, &dev->v4l2_dev, -+ "%s: scene mode none: shut_speed %d, exp_mode %d, metering %d\n", -+ __func__, shutter_speed, dev->exposure_mode_user, -+ dev->metering_mode); -+ ret = vchiq_mmal_port_parameter_set(dev->instance, -+ control, -+ MMAL_PARAMETER_SHUTTER_SPEED, -+ &shutter_speed, -+ sizeof(shutter_speed)); -+ ret += vchiq_mmal_port_parameter_set(dev->instance, -+ control, -+ MMAL_PARAMETER_EXPOSURE_MODE, -+ &dev->exposure_mode_user, -+ sizeof(u32)); -+ dev->exposure_mode_active = dev->exposure_mode_user; -+ ret += vchiq_mmal_port_parameter_set(dev->instance, -+ control, -+ MMAL_PARAMETER_EXP_METERING_MODE, -+ &dev->metering_mode, -+ sizeof(u32)); -+ ret += set_framerate_params(dev); -+ } else { -+ /* Set up scene mode */ -+ int i; -+ const struct v4l2_mmal_scene_config *scene = NULL; -+ int shutter_speed; -+ enum mmal_parameter_exposuremode exposure_mode; -+ enum mmal_parameter_exposuremeteringmode metering_mode; -+ -+ for (i = 0; i < ARRAY_SIZE(scene_configs); i++) { -+ if (scene_configs[i].v4l2_scene == -+ ctrl->val) { -+ scene = &scene_configs[i]; -+ break; -+ } -+ } -+ if (!scene) -+ return -EINVAL; -+ if (i >= ARRAY_SIZE(scene_configs)) -+ return -EINVAL; -+ -+ /* Set all the values */ -+ dev->scene_mode = ctrl->val; -+ -+ if (scene->exposure_mode == MMAL_PARAM_EXPOSUREMODE_OFF) -+ shutter_speed = dev->manual_shutter_speed; -+ else -+ shutter_speed = 0; -+ exposure_mode = scene->exposure_mode; -+ metering_mode = scene->metering_mode; -+ -+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, -+ "%s: scene mode none: shut_speed %d, exp_mode %d, metering %d\n", -+ __func__, shutter_speed, exposure_mode, metering_mode); -+ -+ ret = vchiq_mmal_port_parameter_set(dev->instance, control, -+ MMAL_PARAMETER_SHUTTER_SPEED, -+ &shutter_speed, -+ sizeof(shutter_speed)); -+ ret += vchiq_mmal_port_parameter_set(dev->instance, -+ control, -+ MMAL_PARAMETER_EXPOSURE_MODE, -+ &exposure_mode, -+ sizeof(u32)); -+ dev->exposure_mode_active = exposure_mode; -+ ret += vchiq_mmal_port_parameter_set(dev->instance, control, -+ MMAL_PARAMETER_EXPOSURE_MODE, -+ &exposure_mode, -+ sizeof(u32)); -+ ret += vchiq_mmal_port_parameter_set(dev->instance, control, -+ MMAL_PARAMETER_EXP_METERING_MODE, -+ &metering_mode, -+ sizeof(u32)); -+ ret += set_framerate_params(dev); -+ } -+ if (ret) { -+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, -+ "%s: Setting scene to %d, ret=%d\n", -+ __func__, ctrl->val, ret); -+ ret = -EINVAL; -+ } -+ return 0; -+} -+ -+static int bm2835_mmal_s_ctrl(struct v4l2_ctrl *ctrl) -+{ -+ struct bm2835_mmal_dev *dev = -+ container_of(ctrl->handler, struct bm2835_mmal_dev, -+ ctrl_handler); -+ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl = ctrl->priv; -+ int ret; -+ -+ if ((mmal_ctrl == NULL) || -+ (mmal_ctrl->id != ctrl->id) || -+ (mmal_ctrl->setter == NULL)) { -+ pr_warn("mmal_ctrl:%p ctrl id:%d\n", mmal_ctrl, ctrl->id); -+ return -EINVAL; -+ } -+ -+ ret = mmal_ctrl->setter(dev, ctrl, mmal_ctrl); -+ if (ret) -+ pr_warn("ctrl id:%d/MMAL param %08X- returned ret %d\n", -+ ctrl->id, mmal_ctrl->mmal_id, ret); -+ if (mmal_ctrl->ignore_errors) -+ ret = 0; -+ return ret; -+} -+ -+static const struct v4l2_ctrl_ops bm2835_mmal_ctrl_ops = { -+ .s_ctrl = bm2835_mmal_s_ctrl, -+}; -+ -+ -+ -+static const struct bm2835_mmal_v4l2_ctrl v4l2_ctrls[V4L2_CTRL_COUNT] = { -+ { -+ V4L2_CID_SATURATION, MMAL_CONTROL_TYPE_STD, -+ -100, 100, 0, 1, NULL, -+ MMAL_PARAMETER_SATURATION, -+ &ctrl_set_rational, -+ false -+ }, -+ { -+ V4L2_CID_SHARPNESS, MMAL_CONTROL_TYPE_STD, -+ -100, 100, 0, 1, NULL, -+ MMAL_PARAMETER_SHARPNESS, -+ &ctrl_set_rational, -+ false -+ }, -+ { -+ V4L2_CID_CONTRAST, MMAL_CONTROL_TYPE_STD, -+ -100, 100, 0, 1, NULL, -+ MMAL_PARAMETER_CONTRAST, -+ &ctrl_set_rational, -+ false -+ }, -+ { -+ V4L2_CID_BRIGHTNESS, MMAL_CONTROL_TYPE_STD, -+ 0, 100, 50, 1, NULL, -+ MMAL_PARAMETER_BRIGHTNESS, -+ &ctrl_set_rational, -+ false -+ }, -+ { -+ V4L2_CID_ISO_SENSITIVITY, MMAL_CONTROL_TYPE_INT_MENU, -+ 0, ARRAY_SIZE(iso_qmenu) - 1, 0, 1, iso_qmenu, -+ MMAL_PARAMETER_ISO, -+ &ctrl_set_value_menu, -+ false -+ }, -+ { -+ V4L2_CID_IMAGE_STABILIZATION, MMAL_CONTROL_TYPE_STD, -+ 0, 1, 0, 1, NULL, -+ MMAL_PARAMETER_VIDEO_STABILISATION, -+ &ctrl_set_value, -+ false -+ }, -+/* { -+ 0, MMAL_CONTROL_TYPE_CLUSTER, 3, 1, 0, NULL, 0, NULL -+ }, */ -+ { -+ V4L2_CID_EXPOSURE_AUTO, MMAL_CONTROL_TYPE_STD_MENU, -+ ~0x03, 3, V4L2_EXPOSURE_AUTO, 0, NULL, -+ MMAL_PARAMETER_EXPOSURE_MODE, -+ &ctrl_set_exposure, -+ false -+ }, -+/* todo this needs mixing in with set exposure -+ { -+ V4L2_CID_SCENE_MODE, MMAL_CONTROL_TYPE_STD_MENU, -+ }, -+ */ -+ { -+ V4L2_CID_EXPOSURE_ABSOLUTE, MMAL_CONTROL_TYPE_STD, -+ /* Units of 100usecs */ -+ 1, 1*1000*10, 100*10, 1, NULL, -+ MMAL_PARAMETER_SHUTTER_SPEED, -+ &ctrl_set_exposure, -+ false -+ }, -+ { -+ V4L2_CID_AUTO_EXPOSURE_BIAS, MMAL_CONTROL_TYPE_INT_MENU, -+ 0, ARRAY_SIZE(ev_bias_qmenu) - 1, -+ (ARRAY_SIZE(ev_bias_qmenu)+1)/2 - 1, 0, ev_bias_qmenu, -+ MMAL_PARAMETER_EXPOSURE_COMP, -+ &ctrl_set_value_ev, -+ false -+ }, -+ { -+ V4L2_CID_EXPOSURE_AUTO_PRIORITY, MMAL_CONTROL_TYPE_STD, -+ 0, 1, -+ 0, 1, NULL, -+ 0, /* Dummy MMAL ID as it gets mapped into FPS range*/ -+ &ctrl_set_exposure, -+ false -+ }, -+ { -+ V4L2_CID_EXPOSURE_METERING, -+ MMAL_CONTROL_TYPE_STD_MENU, -+ ~0x7, 2, V4L2_EXPOSURE_METERING_AVERAGE, 0, NULL, -+ MMAL_PARAMETER_EXP_METERING_MODE, -+ &ctrl_set_metering_mode, -+ false -+ }, -+ { -+ V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE, -+ MMAL_CONTROL_TYPE_STD_MENU, -+ ~0x3ff, 9, V4L2_WHITE_BALANCE_AUTO, 0, NULL, -+ MMAL_PARAMETER_AWB_MODE, -+ &ctrl_set_awb_mode, -+ false -+ }, -+ { -+ V4L2_CID_RED_BALANCE, MMAL_CONTROL_TYPE_STD, -+ 1, 7999, 1000, 1, NULL, -+ MMAL_PARAMETER_CUSTOM_AWB_GAINS, -+ &ctrl_set_awb_gains, -+ false -+ }, -+ { -+ V4L2_CID_BLUE_BALANCE, MMAL_CONTROL_TYPE_STD, -+ 1, 7999, 1000, 1, NULL, -+ MMAL_PARAMETER_CUSTOM_AWB_GAINS, -+ &ctrl_set_awb_gains, -+ false -+ }, -+ { -+ V4L2_CID_COLORFX, MMAL_CONTROL_TYPE_STD_MENU, -+ 0, 15, V4L2_COLORFX_NONE, 0, NULL, -+ MMAL_PARAMETER_IMAGE_EFFECT, -+ &ctrl_set_image_effect, -+ false -+ }, -+ { -+ V4L2_CID_COLORFX_CBCR, MMAL_CONTROL_TYPE_STD, -+ 0, 0xffff, 0x8080, 1, NULL, -+ MMAL_PARAMETER_COLOUR_EFFECT, -+ &ctrl_set_colfx, -+ false -+ }, -+ { -+ V4L2_CID_ROTATE, MMAL_CONTROL_TYPE_STD, -+ 0, 360, 0, 90, NULL, -+ MMAL_PARAMETER_ROTATION, -+ &ctrl_set_rotate, -+ false -+ }, -+ { -+ V4L2_CID_HFLIP, MMAL_CONTROL_TYPE_STD, -+ 0, 1, 0, 1, NULL, -+ MMAL_PARAMETER_MIRROR, -+ &ctrl_set_flip, -+ false -+ }, -+ { -+ V4L2_CID_VFLIP, MMAL_CONTROL_TYPE_STD, -+ 0, 1, 0, 1, NULL, -+ MMAL_PARAMETER_MIRROR, -+ &ctrl_set_flip, -+ false -+ }, -+ { -+ V4L2_CID_MPEG_VIDEO_BITRATE_MODE, MMAL_CONTROL_TYPE_STD_MENU, -+ 0, ARRAY_SIZE(bitrate_mode_qmenu) - 1, -+ 0, 0, bitrate_mode_qmenu, -+ MMAL_PARAMETER_RATECONTROL, -+ &ctrl_set_bitrate_mode, -+ false -+ }, -+ { -+ V4L2_CID_MPEG_VIDEO_BITRATE, MMAL_CONTROL_TYPE_STD, -+ 25*1000, 25*1000*1000, 10*1000*1000, 25*1000, NULL, -+ MMAL_PARAMETER_VIDEO_BIT_RATE, -+ &ctrl_set_bitrate, -+ false -+ }, -+ { -+ V4L2_CID_JPEG_COMPRESSION_QUALITY, MMAL_CONTROL_TYPE_STD, -+ 1, 100, -+ 30, 1, NULL, -+ MMAL_PARAMETER_JPEG_Q_FACTOR, -+ &ctrl_set_image_encode_output, -+ false -+ }, -+ { -+ V4L2_CID_POWER_LINE_FREQUENCY, MMAL_CONTROL_TYPE_STD_MENU, -+ 0, ARRAY_SIZE(mains_freq_qmenu) - 1, -+ 1, 1, NULL, -+ MMAL_PARAMETER_FLICKER_AVOID, -+ &ctrl_set_flicker_avoidance, -+ false -+ }, -+ { -+ V4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER, MMAL_CONTROL_TYPE_STD, -+ 0, 1, -+ 0, 1, NULL, -+ MMAL_PARAMETER_VIDEO_ENCODE_INLINE_HEADER, -+ &ctrl_set_video_encode_param_output, -+ true /* Errors ignored as requires latest firmware to work */ -+ }, -+ { -+ V4L2_CID_MPEG_VIDEO_H264_PROFILE, -+ MMAL_CONTROL_TYPE_STD_MENU, -+ ~((1<ctrls[c]) && (v4l2_ctrls[c].setter)) { -+ ret = v4l2_ctrls[c].setter(dev, dev->ctrls[c], -+ &v4l2_ctrls[c]); -+ if (!v4l2_ctrls[c].ignore_errors && ret) { -+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, -+ "Failed when setting default values for ctrl %d\n", -+ c); -+ break; -+ } -+ } -+ } -+ return ret; -+} -+ -+int set_framerate_params(struct bm2835_mmal_dev *dev) -+{ -+ struct mmal_parameter_fps_range fps_range; -+ int ret; -+ -+ if ((dev->exposure_mode_active != MMAL_PARAM_EXPOSUREMODE_OFF) && -+ (dev->exp_auto_priority)) { -+ /* Variable FPS. Define min FPS as 1fps. -+ * Max as max defined FPS. -+ */ -+ fps_range.fps_low.num = 1; -+ fps_range.fps_low.den = 1; -+ fps_range.fps_high.num = dev->capture.timeperframe.denominator; -+ fps_range.fps_high.den = dev->capture.timeperframe.numerator; -+ } else { -+ /* Fixed FPS - set min and max to be the same */ -+ fps_range.fps_low.num = fps_range.fps_high.num = -+ dev->capture.timeperframe.denominator; -+ fps_range.fps_low.den = fps_range.fps_high.den = -+ dev->capture.timeperframe.numerator; -+ } -+ -+ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, -+ "Set fps range to %d/%d to %d/%d\n", -+ fps_range.fps_low.num, -+ fps_range.fps_low.den, -+ fps_range.fps_high.num, -+ fps_range.fps_high.den -+ ); -+ -+ ret = vchiq_mmal_port_parameter_set(dev->instance, -+ &dev->component[MMAL_COMPONENT_CAMERA]-> -+ output[MMAL_CAMERA_PORT_PREVIEW], -+ MMAL_PARAMETER_FPS_RANGE, -+ &fps_range, sizeof(fps_range)); -+ ret += vchiq_mmal_port_parameter_set(dev->instance, -+ &dev->component[MMAL_COMPONENT_CAMERA]-> -+ output[MMAL_CAMERA_PORT_VIDEO], -+ MMAL_PARAMETER_FPS_RANGE, -+ &fps_range, sizeof(fps_range)); -+ ret += vchiq_mmal_port_parameter_set(dev->instance, -+ &dev->component[MMAL_COMPONENT_CAMERA]-> -+ output[MMAL_CAMERA_PORT_CAPTURE], -+ MMAL_PARAMETER_FPS_RANGE, -+ &fps_range, sizeof(fps_range)); -+ if (ret) -+ v4l2_dbg(0, bcm2835_v4l2_debug, &dev->v4l2_dev, -+ "Failed to set fps ret %d\n", -+ ret); -+ -+ return ret; -+ -+} -+ -+int bm2835_mmal_init_controls(struct bm2835_mmal_dev *dev, -+ struct v4l2_ctrl_handler *hdl) -+{ -+ int c; -+ const struct bm2835_mmal_v4l2_ctrl *ctrl; -+ -+ v4l2_ctrl_handler_init(hdl, V4L2_CTRL_COUNT); -+ -+ for (c = 0; c < V4L2_CTRL_COUNT; c++) { -+ ctrl = &v4l2_ctrls[c]; -+ -+ switch (ctrl->type) { -+ case MMAL_CONTROL_TYPE_STD: -+ dev->ctrls[c] = v4l2_ctrl_new_std(hdl, -+ &bm2835_mmal_ctrl_ops, ctrl->id, -+ ctrl->min, ctrl->max, ctrl->step, ctrl->def); -+ break; -+ -+ case MMAL_CONTROL_TYPE_STD_MENU: -+ { -+ int mask = ctrl->min; -+ -+ if (ctrl->id == V4L2_CID_SCENE_MODE) { -+ /* Special handling to work out the mask -+ * value based on the scene_configs array -+ * at runtime. Reduces the chance of -+ * mismatches. -+ */ -+ int i; -+ mask = 1<ctrls[c] = v4l2_ctrl_new_std_menu(hdl, -+ &bm2835_mmal_ctrl_ops, ctrl->id, -+ ctrl->max, mask, ctrl->def); -+ break; -+ } -+ -+ case MMAL_CONTROL_TYPE_INT_MENU: -+ dev->ctrls[c] = v4l2_ctrl_new_int_menu(hdl, -+ &bm2835_mmal_ctrl_ops, ctrl->id, -+ ctrl->max, ctrl->def, ctrl->imenu); -+ break; -+ -+ case MMAL_CONTROL_TYPE_CLUSTER: -+ /* skip this entry when constructing controls */ -+ continue; -+ } -+ -+ if (hdl->error) -+ break; -+ -+ dev->ctrls[c]->priv = (void *)ctrl; -+ } -+ -+ if (hdl->error) { -+ pr_err("error adding control %d/%d id 0x%x\n", c, -+ V4L2_CTRL_COUNT, ctrl->id); -+ return hdl->error; -+ } -+ -+ for (c = 0; c < V4L2_CTRL_COUNT; c++) { -+ ctrl = &v4l2_ctrls[c]; -+ -+ switch (ctrl->type) { -+ case MMAL_CONTROL_TYPE_CLUSTER: -+ v4l2_ctrl_auto_cluster(ctrl->min, -+ &dev->ctrls[c+1], -+ ctrl->max, -+ ctrl->def); -+ break; -+ -+ case MMAL_CONTROL_TYPE_STD: -+ case MMAL_CONTROL_TYPE_STD_MENU: -+ case MMAL_CONTROL_TYPE_INT_MENU: -+ break; -+ } -+ -+ } -+ -+ return 0; -+} -diff -Nur linux-4.1.13.orig/drivers/media/platform/bcm2835/Kconfig linux-rpi/drivers/media/platform/bcm2835/Kconfig ---- linux-4.1.13.orig/drivers/media/platform/bcm2835/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/media/platform/bcm2835/Kconfig 2015-11-29 09:42:37.835237156 +0100 -@@ -0,0 +1,25 @@ -+# Broadcom VideoCore IV v4l2 camera support -+ -+config VIDEO_BCM2835 -+ bool "Broadcom BCM2835 camera interface driver" -+ depends on VIDEO_V4L2 && (ARCH_BCM2708 || ARCH_BCM2709 || ARCH_BCM2835) -+ ---help--- -+ Say Y here to enable camera host interface devices for -+ Broadcom BCM2835 SoC. This operates over the VCHIQ interface -+ to a service running on VideoCore. -+ -+ -+if VIDEO_BCM2835 -+ -+config VIDEO_BCM2835_MMAL -+ tristate "Broadcom BM2835 MMAL camera interface driver" -+ depends on BCM2708_VCHIQ -+ select VIDEOBUF2_VMALLOC -+ ---help--- -+ This is a V4L2 driver for the Broadcom BCM2835 MMAL camera host interface -+ -+ To compile this driver as a module, choose M here: the -+ module will be called bcm2835-v4l2.o -+ -+ -+endif # VIDEO_BM2835 -diff -Nur linux-4.1.13.orig/drivers/media/platform/bcm2835/Makefile linux-rpi/drivers/media/platform/bcm2835/Makefile ---- linux-4.1.13.orig/drivers/media/platform/bcm2835/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/media/platform/bcm2835/Makefile 2015-11-29 09:42:37.835237156 +0100 -@@ -0,0 +1,5 @@ -+bcm2835-v4l2-objs := bcm2835-camera.o controls.o mmal-vchiq.o -+ -+obj-$(CONFIG_VIDEO_BCM2835_MMAL) += bcm2835-v4l2.o -+ -+ccflags-$(CONFIG_VIDEO_BCM2835) += -Idrivers/misc/vc04_services -Idrivers/misc/vc04_services/interface/vcos/linuxkernel -D__VCCOREVER__=0x04000000 -diff -Nur linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-common.h linux-rpi/drivers/media/platform/bcm2835/mmal-common.h ---- linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-common.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/media/platform/bcm2835/mmal-common.h 2015-11-29 09:42:37.835237156 +0100 -@@ -0,0 +1,53 @@ -+/* -+ * Broadcom BM2835 V4L2 driver -+ * -+ * Copyright © 2013 Raspberry Pi (Trading) Ltd. -+ * -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file COPYING in the main directory of this archive -+ * for more details. -+ * -+ * Authors: Vincent Sanders -+ * Dave Stevenson -+ * Simon Mellor -+ * Luke Diamand -+ * -+ * MMAL structures -+ * -+ */ -+ -+#define MMAL_FOURCC(a, b, c, d) ((a) | (b << 8) | (c << 16) | (d << 24)) -+#define MMAL_MAGIC MMAL_FOURCC('m', 'm', 'a', 'l') -+ -+/** Special value signalling that time is not known */ -+#define MMAL_TIME_UNKNOWN (1LL<<63) -+ -+/* mapping between v4l and mmal video modes */ -+struct mmal_fmt { -+ char *name; -+ u32 fourcc; /* v4l2 format id */ -+ int flags; /* v4l2 flags field */ -+ u32 mmal; -+ int depth; -+ u32 mmal_component; /* MMAL component index to be used to encode */ -+ u32 ybbp; /* depth of first Y plane for planar formats */ -+}; -+ -+/* buffer for one video frame */ -+struct mmal_buffer { -+ /* v4l buffer data -- must be first */ -+ struct vb2_buffer vb; -+ -+ /* list of buffers available */ -+ struct list_head list; -+ -+ void *buffer; /* buffer pointer */ -+ unsigned long buffer_size; /* size of allocated buffer */ -+}; -+ -+/* */ -+struct mmal_colourfx { -+ s32 enable; -+ u32 u; -+ u32 v; -+}; -diff -Nur linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-encodings.h linux-rpi/drivers/media/platform/bcm2835/mmal-encodings.h ---- linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-encodings.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/media/platform/bcm2835/mmal-encodings.h 2015-11-29 09:42:37.835237156 +0100 -@@ -0,0 +1,127 @@ -+/* -+ * Broadcom BM2835 V4L2 driver -+ * -+ * Copyright © 2013 Raspberry Pi (Trading) Ltd. -+ * -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file COPYING in the main directory of this archive -+ * for more details. -+ * -+ * Authors: Vincent Sanders -+ * Dave Stevenson -+ * Simon Mellor -+ * Luke Diamand -+ */ -+#ifndef MMAL_ENCODINGS_H -+#define MMAL_ENCODINGS_H -+ -+#define MMAL_ENCODING_H264 MMAL_FOURCC('H', '2', '6', '4') -+#define MMAL_ENCODING_H263 MMAL_FOURCC('H', '2', '6', '3') -+#define MMAL_ENCODING_MP4V MMAL_FOURCC('M', 'P', '4', 'V') -+#define MMAL_ENCODING_MP2V MMAL_FOURCC('M', 'P', '2', 'V') -+#define MMAL_ENCODING_MP1V MMAL_FOURCC('M', 'P', '1', 'V') -+#define MMAL_ENCODING_WMV3 MMAL_FOURCC('W', 'M', 'V', '3') -+#define MMAL_ENCODING_WMV2 MMAL_FOURCC('W', 'M', 'V', '2') -+#define MMAL_ENCODING_WMV1 MMAL_FOURCC('W', 'M', 'V', '1') -+#define MMAL_ENCODING_WVC1 MMAL_FOURCC('W', 'V', 'C', '1') -+#define MMAL_ENCODING_VP8 MMAL_FOURCC('V', 'P', '8', ' ') -+#define MMAL_ENCODING_VP7 MMAL_FOURCC('V', 'P', '7', ' ') -+#define MMAL_ENCODING_VP6 MMAL_FOURCC('V', 'P', '6', ' ') -+#define MMAL_ENCODING_THEORA MMAL_FOURCC('T', 'H', 'E', 'O') -+#define MMAL_ENCODING_SPARK MMAL_FOURCC('S', 'P', 'R', 'K') -+#define MMAL_ENCODING_MJPEG MMAL_FOURCC('M', 'J', 'P', 'G') -+ -+#define MMAL_ENCODING_JPEG MMAL_FOURCC('J', 'P', 'E', 'G') -+#define MMAL_ENCODING_GIF MMAL_FOURCC('G', 'I', 'F', ' ') -+#define MMAL_ENCODING_PNG MMAL_FOURCC('P', 'N', 'G', ' ') -+#define MMAL_ENCODING_PPM MMAL_FOURCC('P', 'P', 'M', ' ') -+#define MMAL_ENCODING_TGA MMAL_FOURCC('T', 'G', 'A', ' ') -+#define MMAL_ENCODING_BMP MMAL_FOURCC('B', 'M', 'P', ' ') -+ -+#define MMAL_ENCODING_I420 MMAL_FOURCC('I', '4', '2', '0') -+#define MMAL_ENCODING_I420_SLICE MMAL_FOURCC('S', '4', '2', '0') -+#define MMAL_ENCODING_YV12 MMAL_FOURCC('Y', 'V', '1', '2') -+#define MMAL_ENCODING_I422 MMAL_FOURCC('I', '4', '2', '2') -+#define MMAL_ENCODING_I422_SLICE MMAL_FOURCC('S', '4', '2', '2') -+#define MMAL_ENCODING_YUYV MMAL_FOURCC('Y', 'U', 'Y', 'V') -+#define MMAL_ENCODING_YVYU MMAL_FOURCC('Y', 'V', 'Y', 'U') -+#define MMAL_ENCODING_UYVY MMAL_FOURCC('U', 'Y', 'V', 'Y') -+#define MMAL_ENCODING_VYUY MMAL_FOURCC('V', 'Y', 'U', 'Y') -+#define MMAL_ENCODING_NV12 MMAL_FOURCC('N', 'V', '1', '2') -+#define MMAL_ENCODING_NV21 MMAL_FOURCC('N', 'V', '2', '1') -+#define MMAL_ENCODING_ARGB MMAL_FOURCC('A', 'R', 'G', 'B') -+#define MMAL_ENCODING_RGBA MMAL_FOURCC('R', 'G', 'B', 'A') -+#define MMAL_ENCODING_ABGR MMAL_FOURCC('A', 'B', 'G', 'R') -+#define MMAL_ENCODING_BGRA MMAL_FOURCC('B', 'G', 'R', 'A') -+#define MMAL_ENCODING_RGB16 MMAL_FOURCC('R', 'G', 'B', '2') -+#define MMAL_ENCODING_RGB24 MMAL_FOURCC('R', 'G', 'B', '3') -+#define MMAL_ENCODING_RGB32 MMAL_FOURCC('R', 'G', 'B', '4') -+#define MMAL_ENCODING_BGR16 MMAL_FOURCC('B', 'G', 'R', '2') -+#define MMAL_ENCODING_BGR24 MMAL_FOURCC('B', 'G', 'R', '3') -+#define MMAL_ENCODING_BGR32 MMAL_FOURCC('B', 'G', 'R', '4') -+ -+/** SAND Video (YUVUV128) format, native format understood by VideoCore. -+ * This format is *not* opaque - if requested you will receive full frames -+ * of YUV_UV video. -+ */ -+#define MMAL_ENCODING_YUVUV128 MMAL_FOURCC('S', 'A', 'N', 'D') -+ -+/** VideoCore opaque image format, image handles are returned to -+ * the host but not the actual image data. -+ */ -+#define MMAL_ENCODING_OPAQUE MMAL_FOURCC('O', 'P', 'Q', 'V') -+ -+/** An EGL image handle -+ */ -+#define MMAL_ENCODING_EGL_IMAGE MMAL_FOURCC('E', 'G', 'L', 'I') -+ -+/* }@ */ -+ -+/** \name Pre-defined audio encodings */ -+/* @{ */ -+#define MMAL_ENCODING_PCM_UNSIGNED_BE MMAL_FOURCC('P', 'C', 'M', 'U') -+#define MMAL_ENCODING_PCM_UNSIGNED_LE MMAL_FOURCC('p', 'c', 'm', 'u') -+#define MMAL_ENCODING_PCM_SIGNED_BE MMAL_FOURCC('P', 'C', 'M', 'S') -+#define MMAL_ENCODING_PCM_SIGNED_LE MMAL_FOURCC('p', 'c', 'm', 's') -+#define MMAL_ENCODING_PCM_FLOAT_BE MMAL_FOURCC('P', 'C', 'M', 'F') -+#define MMAL_ENCODING_PCM_FLOAT_LE MMAL_FOURCC('p', 'c', 'm', 'f') -+ -+/* Pre-defined H264 encoding variants */ -+ -+/** ISO 14496-10 Annex B byte stream format */ -+#define MMAL_ENCODING_VARIANT_H264_DEFAULT 0 -+/** ISO 14496-15 AVC stream format */ -+#define MMAL_ENCODING_VARIANT_H264_AVC1 MMAL_FOURCC('A', 'V', 'C', '1') -+/** Implicitly delineated NAL units without emulation prevention */ -+#define MMAL_ENCODING_VARIANT_H264_RAW MMAL_FOURCC('R', 'A', 'W', ' ') -+ -+ -+/** \defgroup MmalColorSpace List of pre-defined video color spaces -+ * This defines a list of common color spaces. This list isn't exhaustive and -+ * is only provided as a convenience to avoid clients having to use FourCC -+ * codes directly. However components are allowed to define and use their own -+ * FourCC codes. -+ */ -+/* @{ */ -+ -+/** Unknown color space */ -+#define MMAL_COLOR_SPACE_UNKNOWN 0 -+/** ITU-R BT.601-5 [SDTV] */ -+#define MMAL_COLOR_SPACE_ITUR_BT601 MMAL_FOURCC('Y', '6', '0', '1') -+/** ITU-R BT.709-3 [HDTV] */ -+#define MMAL_COLOR_SPACE_ITUR_BT709 MMAL_FOURCC('Y', '7', '0', '9') -+/** JPEG JFIF */ -+#define MMAL_COLOR_SPACE_JPEG_JFIF MMAL_FOURCC('Y', 'J', 'F', 'I') -+/** Title 47 Code of Federal Regulations (2003) 73.682 (a) (20) */ -+#define MMAL_COLOR_SPACE_FCC MMAL_FOURCC('Y', 'F', 'C', 'C') -+/** Society of Motion Picture and Television Engineers 240M (1999) */ -+#define MMAL_COLOR_SPACE_SMPTE240M MMAL_FOURCC('Y', '2', '4', '0') -+/** ITU-R BT.470-2 System M */ -+#define MMAL_COLOR_SPACE_BT470_2_M MMAL_FOURCC('Y', '_', '_', 'M') -+/** ITU-R BT.470-2 System BG */ -+#define MMAL_COLOR_SPACE_BT470_2_BG MMAL_FOURCC('Y', '_', 'B', 'G') -+/** JPEG JFIF, but with 16..255 luma */ -+#define MMAL_COLOR_SPACE_JFIF_Y16_255 MMAL_FOURCC('Y', 'Y', '1', '6') -+/* @} MmalColorSpace List */ -+ -+#endif /* MMAL_ENCODINGS_H */ -diff -Nur linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-msg-common.h linux-rpi/drivers/media/platform/bcm2835/mmal-msg-common.h ---- linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-msg-common.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/media/platform/bcm2835/mmal-msg-common.h 2015-11-29 09:42:37.835237156 +0100 -@@ -0,0 +1,50 @@ -+/* -+ * Broadcom BM2835 V4L2 driver -+ * -+ * Copyright © 2013 Raspberry Pi (Trading) Ltd. -+ * -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file COPYING in the main directory of this archive -+ * for more details. -+ * -+ * Authors: Vincent Sanders -+ * Dave Stevenson -+ * Simon Mellor -+ * Luke Diamand -+ */ -+ -+#ifndef MMAL_MSG_COMMON_H -+#define MMAL_MSG_COMMON_H -+ -+enum mmal_msg_status { -+ MMAL_MSG_STATUS_SUCCESS = 0, /**< Success */ -+ MMAL_MSG_STATUS_ENOMEM, /**< Out of memory */ -+ MMAL_MSG_STATUS_ENOSPC, /**< Out of resources other than memory */ -+ MMAL_MSG_STATUS_EINVAL, /**< Argument is invalid */ -+ MMAL_MSG_STATUS_ENOSYS, /**< Function not implemented */ -+ MMAL_MSG_STATUS_ENOENT, /**< No such file or directory */ -+ MMAL_MSG_STATUS_ENXIO, /**< No such device or address */ -+ MMAL_MSG_STATUS_EIO, /**< I/O error */ -+ MMAL_MSG_STATUS_ESPIPE, /**< Illegal seek */ -+ MMAL_MSG_STATUS_ECORRUPT, /**< Data is corrupt \attention */ -+ MMAL_MSG_STATUS_ENOTREADY, /**< Component is not ready */ -+ MMAL_MSG_STATUS_ECONFIG, /**< Component is not configured */ -+ MMAL_MSG_STATUS_EISCONN, /**< Port is already connected */ -+ MMAL_MSG_STATUS_ENOTCONN, /**< Port is disconnected */ -+ MMAL_MSG_STATUS_EAGAIN, /**< Resource temporarily unavailable. */ -+ MMAL_MSG_STATUS_EFAULT, /**< Bad address */ -+}; -+ -+struct mmal_rect { -+ s32 x; /**< x coordinate (from left) */ -+ s32 y; /**< y coordinate (from top) */ -+ s32 width; /**< width */ -+ s32 height; /**< height */ -+}; -+ -+struct mmal_rational { -+ s32 num; /**< Numerator */ -+ s32 den; /**< Denominator */ -+}; -+ -+#endif /* MMAL_MSG_COMMON_H */ -diff -Nur linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-msg-format.h linux-rpi/drivers/media/platform/bcm2835/mmal-msg-format.h ---- linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-msg-format.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/media/platform/bcm2835/mmal-msg-format.h 2015-11-29 09:42:37.835237156 +0100 -@@ -0,0 +1,81 @@ -+/* -+ * Broadcom BM2835 V4L2 driver -+ * -+ * Copyright © 2013 Raspberry Pi (Trading) Ltd. -+ * -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file COPYING in the main directory of this archive -+ * for more details. -+ * -+ * Authors: Vincent Sanders -+ * Dave Stevenson -+ * Simon Mellor -+ * Luke Diamand -+ */ -+ -+#ifndef MMAL_MSG_FORMAT_H -+#define MMAL_MSG_FORMAT_H -+ -+#include "mmal-msg-common.h" -+ -+/* MMAL_ES_FORMAT_T */ -+ -+ -+struct mmal_audio_format { -+ u32 channels; /**< Number of audio channels */ -+ u32 sample_rate; /**< Sample rate */ -+ -+ u32 bits_per_sample; /**< Bits per sample */ -+ u32 block_align; /**< Size of a block of data */ -+}; -+ -+struct mmal_video_format { -+ u32 width; /**< Width of frame in pixels */ -+ u32 height; /**< Height of frame in rows of pixels */ -+ struct mmal_rect crop; /**< Visible region of the frame */ -+ struct mmal_rational frame_rate; /**< Frame rate */ -+ struct mmal_rational par; /**< Pixel aspect ratio */ -+ -+ /* FourCC specifying the color space of the video stream. See the -+ * \ref MmalColorSpace "pre-defined color spaces" for some examples. -+ */ -+ u32 color_space; -+}; -+ -+struct mmal_subpicture_format { -+ u32 x_offset; -+ u32 y_offset; -+}; -+ -+union mmal_es_specific_format { -+ struct mmal_audio_format audio; -+ struct mmal_video_format video; -+ struct mmal_subpicture_format subpicture; -+}; -+ -+/** Definition of an elementary stream format (MMAL_ES_FORMAT_T) */ -+struct mmal_es_format { -+ u32 type; /* enum mmal_es_type */ -+ -+ u32 encoding; /* FourCC specifying encoding of the elementary stream.*/ -+ u32 encoding_variant; /* FourCC specifying the specific -+ * encoding variant of the elementary -+ * stream. -+ */ -+ -+ union mmal_es_specific_format *es; /* TODO: pointers in -+ * message serialisation?!? -+ */ -+ /* Type specific -+ * information for the -+ * elementary stream -+ */ -+ -+ u32 bitrate; /**< Bitrate in bits per second */ -+ u32 flags; /**< Flags describing properties of the elementary stream. */ -+ -+ u32 extradata_size; /**< Size of the codec specific data */ -+ u8 *extradata; /**< Codec specific data */ -+}; -+ -+#endif /* MMAL_MSG_FORMAT_H */ -diff -Nur linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-msg.h linux-rpi/drivers/media/platform/bcm2835/mmal-msg.h ---- linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-msg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/media/platform/bcm2835/mmal-msg.h 2015-11-29 09:42:37.835237156 +0100 -@@ -0,0 +1,404 @@ -+/* -+ * Broadcom BM2835 V4L2 driver -+ * -+ * Copyright © 2013 Raspberry Pi (Trading) Ltd. -+ * -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file COPYING in the main directory of this archive -+ * for more details. -+ * -+ * Authors: Vincent Sanders -+ * Dave Stevenson -+ * Simon Mellor -+ * Luke Diamand -+ */ -+ -+/* all the data structures which serialise the MMAL protocol. note -+ * these are directly mapped onto the recived message data. -+ * -+ * BEWARE: They seem to *assume* pointers are u32 and that there is no -+ * structure padding! -+ * -+ * NOTE: this implementation uses kernel types to ensure sizes. Rather -+ * than assigning values to enums to force their size the -+ * implementation uses fixed size types and not the enums (though the -+ * comments have the actual enum type -+ */ -+ -+#define VC_MMAL_VER 15 -+#define VC_MMAL_MIN_VER 10 -+#define VC_MMAL_SERVER_NAME MAKE_FOURCC("mmal") -+ -+/* max total message size is 512 bytes */ -+#define MMAL_MSG_MAX_SIZE 512 -+/* with six 32bit header elements max payload is therefore 488 bytes */ -+#define MMAL_MSG_MAX_PAYLOAD 488 -+ -+#include "mmal-msg-common.h" -+#include "mmal-msg-format.h" -+#include "mmal-msg-port.h" -+ -+enum mmal_msg_type { -+ MMAL_MSG_TYPE_QUIT = 1, -+ MMAL_MSG_TYPE_SERVICE_CLOSED, -+ MMAL_MSG_TYPE_GET_VERSION, -+ MMAL_MSG_TYPE_COMPONENT_CREATE, -+ MMAL_MSG_TYPE_COMPONENT_DESTROY, /* 5 */ -+ MMAL_MSG_TYPE_COMPONENT_ENABLE, -+ MMAL_MSG_TYPE_COMPONENT_DISABLE, -+ MMAL_MSG_TYPE_PORT_INFO_GET, -+ MMAL_MSG_TYPE_PORT_INFO_SET, -+ MMAL_MSG_TYPE_PORT_ACTION, /* 10 */ -+ MMAL_MSG_TYPE_BUFFER_FROM_HOST, -+ MMAL_MSG_TYPE_BUFFER_TO_HOST, -+ MMAL_MSG_TYPE_GET_STATS, -+ MMAL_MSG_TYPE_PORT_PARAMETER_SET, -+ MMAL_MSG_TYPE_PORT_PARAMETER_GET, /* 15 */ -+ MMAL_MSG_TYPE_EVENT_TO_HOST, -+ MMAL_MSG_TYPE_GET_CORE_STATS_FOR_PORT, -+ MMAL_MSG_TYPE_OPAQUE_ALLOCATOR, -+ MMAL_MSG_TYPE_CONSUME_MEM, -+ MMAL_MSG_TYPE_LMK, /* 20 */ -+ MMAL_MSG_TYPE_OPAQUE_ALLOCATOR_DESC, -+ MMAL_MSG_TYPE_DRM_GET_LHS32, -+ MMAL_MSG_TYPE_DRM_GET_TIME, -+ MMAL_MSG_TYPE_BUFFER_FROM_HOST_ZEROLEN, -+ MMAL_MSG_TYPE_PORT_FLUSH, /* 25 */ -+ MMAL_MSG_TYPE_HOST_LOG, -+ MMAL_MSG_TYPE_MSG_LAST -+}; -+ -+/* port action request messages differ depending on the action type */ -+enum mmal_msg_port_action_type { -+ MMAL_MSG_PORT_ACTION_TYPE_UNKNOWN = 0, /* Unkown action */ -+ MMAL_MSG_PORT_ACTION_TYPE_ENABLE, /* Enable a port */ -+ MMAL_MSG_PORT_ACTION_TYPE_DISABLE, /* Disable a port */ -+ MMAL_MSG_PORT_ACTION_TYPE_FLUSH, /* Flush a port */ -+ MMAL_MSG_PORT_ACTION_TYPE_CONNECT, /* Connect ports */ -+ MMAL_MSG_PORT_ACTION_TYPE_DISCONNECT, /* Disconnect ports */ -+ MMAL_MSG_PORT_ACTION_TYPE_SET_REQUIREMENTS, /* Set buffer requirements*/ -+}; -+ -+struct mmal_msg_header { -+ u32 magic; -+ u32 type; /** enum mmal_msg_type */ -+ -+ /* Opaque handle to the control service */ -+ struct mmal_control_service *control_service; -+ -+ struct mmal_msg_context *context; /** a u32 per message context */ -+ u32 status; /** The status of the vchiq operation */ -+ u32 padding; -+}; -+ -+/* Send from VC to host to report version */ -+struct mmal_msg_version { -+ u32 flags; -+ u32 major; -+ u32 minor; -+ u32 minimum; -+}; -+ -+/* request to VC to create component */ -+struct mmal_msg_component_create { -+ void *client_component; /* component context */ -+ char name[128]; -+ u32 pid; /* For debug */ -+}; -+ -+/* reply from VC to component creation request */ -+struct mmal_msg_component_create_reply { -+ u32 status; /** enum mmal_msg_status - how does this differ to -+ * the one in the header? -+ */ -+ u32 component_handle; /* VideoCore handle for component */ -+ u32 input_num; /* Number of input ports */ -+ u32 output_num; /* Number of output ports */ -+ u32 clock_num; /* Number of clock ports */ -+}; -+ -+/* request to VC to destroy a component */ -+struct mmal_msg_component_destroy { -+ u32 component_handle; -+}; -+ -+struct mmal_msg_component_destroy_reply { -+ u32 status; /** The component destruction status */ -+}; -+ -+ -+/* request and reply to VC to enable a component */ -+struct mmal_msg_component_enable { -+ u32 component_handle; -+}; -+ -+struct mmal_msg_component_enable_reply { -+ u32 status; /** The component enable status */ -+}; -+ -+ -+/* request and reply to VC to disable a component */ -+struct mmal_msg_component_disable { -+ u32 component_handle; -+}; -+ -+struct mmal_msg_component_disable_reply { -+ u32 status; /** The component disable status */ -+}; -+ -+/* request to VC to get port information */ -+struct mmal_msg_port_info_get { -+ u32 component_handle; /* component handle port is associated with */ -+ u32 port_type; /* enum mmal_msg_port_type */ -+ u32 index; /* port index to query */ -+}; -+ -+/* reply from VC to get port info request */ -+struct mmal_msg_port_info_get_reply { -+ u32 status; /** enum mmal_msg_status */ -+ u32 component_handle; /* component handle port is associated with */ -+ u32 port_type; /* enum mmal_msg_port_type */ -+ u32 port_index; /* port indexed in query */ -+ s32 found; /* unused */ -+ u32 port_handle; /**< Handle to use for this port */ -+ struct mmal_port port; -+ struct mmal_es_format format; /* elementry stream format */ -+ union mmal_es_specific_format es; /* es type specific data */ -+ u8 extradata[MMAL_FORMAT_EXTRADATA_MAX_SIZE]; /* es extra data */ -+}; -+ -+/* request to VC to set port information */ -+struct mmal_msg_port_info_set { -+ u32 component_handle; -+ u32 port_type; /* enum mmal_msg_port_type */ -+ u32 port_index; /* port indexed in query */ -+ struct mmal_port port; -+ struct mmal_es_format format; -+ union mmal_es_specific_format es; -+ u8 extradata[MMAL_FORMAT_EXTRADATA_MAX_SIZE]; -+}; -+ -+/* reply from VC to port info set request */ -+struct mmal_msg_port_info_set_reply { -+ u32 status; -+ u32 component_handle; /* component handle port is associated with */ -+ u32 port_type; /* enum mmal_msg_port_type */ -+ u32 index; /* port indexed in query */ -+ s32 found; /* unused */ -+ u32 port_handle; /**< Handle to use for this port */ -+ struct mmal_port port; -+ struct mmal_es_format format; -+ union mmal_es_specific_format es; -+ u8 extradata[MMAL_FORMAT_EXTRADATA_MAX_SIZE]; -+}; -+ -+ -+/* port action requests that take a mmal_port as a parameter */ -+struct mmal_msg_port_action_port { -+ u32 component_handle; -+ u32 port_handle; -+ u32 action; /* enum mmal_msg_port_action_type */ -+ struct mmal_port port; -+}; -+ -+/* port action requests that take handles as a parameter */ -+struct mmal_msg_port_action_handle { -+ u32 component_handle; -+ u32 port_handle; -+ u32 action; /* enum mmal_msg_port_action_type */ -+ u32 connect_component_handle; -+ u32 connect_port_handle; -+}; -+ -+struct mmal_msg_port_action_reply { -+ u32 status; /** The port action operation status */ -+}; -+ -+ -+ -+ -+/* MMAL buffer transfer */ -+ -+/** Size of space reserved in a buffer message for short messages. */ -+#define MMAL_VC_SHORT_DATA 128 -+ -+/** Signals that the current payload is the end of the stream of data */ -+#define MMAL_BUFFER_HEADER_FLAG_EOS (1<<0) -+/** Signals that the start of the current payload starts a frame */ -+#define MMAL_BUFFER_HEADER_FLAG_FRAME_START (1<<1) -+/** Signals that the end of the current payload ends a frame */ -+#define MMAL_BUFFER_HEADER_FLAG_FRAME_END (1<<2) -+/** Signals that the current payload contains only complete frames (>1) */ -+#define MMAL_BUFFER_HEADER_FLAG_FRAME \ -+ (MMAL_BUFFER_HEADER_FLAG_FRAME_START|MMAL_BUFFER_HEADER_FLAG_FRAME_END) -+/** Signals that the current payload is a keyframe (i.e. self decodable) */ -+#define MMAL_BUFFER_HEADER_FLAG_KEYFRAME (1<<3) -+/** Signals a discontinuity in the stream of data (e.g. after a seek). -+ * Can be used for instance by a decoder to reset its state */ -+#define MMAL_BUFFER_HEADER_FLAG_DISCONTINUITY (1<<4) -+/** Signals a buffer containing some kind of config data for the component -+ * (e.g. codec config data) */ -+#define MMAL_BUFFER_HEADER_FLAG_CONFIG (1<<5) -+/** Signals an encrypted payload */ -+#define MMAL_BUFFER_HEADER_FLAG_ENCRYPTED (1<<6) -+/** Signals a buffer containing side information */ -+#define MMAL_BUFFER_HEADER_FLAG_CODECSIDEINFO (1<<7) -+/** Signals a buffer which is the snapshot/postview image from a stills -+ * capture -+ */ -+#define MMAL_BUFFER_HEADER_FLAGS_SNAPSHOT (1<<8) -+/** Signals a buffer which contains data known to be corrupted */ -+#define MMAL_BUFFER_HEADER_FLAG_CORRUPTED (1<<9) -+/** Signals that a buffer failed to be transmitted */ -+#define MMAL_BUFFER_HEADER_FLAG_TRANSMISSION_FAILED (1<<10) -+ -+struct mmal_driver_buffer { -+ u32 magic; -+ u32 component_handle; -+ u32 port_handle; -+ void *client_context; -+}; -+ -+/* buffer header */ -+struct mmal_buffer_header { -+ struct mmal_buffer_header *next; /* next header */ -+ void *priv; /* framework private data */ -+ u32 cmd; -+ void *data; -+ u32 alloc_size; -+ u32 length; -+ u32 offset; -+ u32 flags; -+ s64 pts; -+ s64 dts; -+ void *type; -+ void *user_data; -+}; -+ -+struct mmal_buffer_header_type_specific { -+ union { -+ struct { -+ u32 planes; -+ u32 offset[4]; -+ u32 pitch[4]; -+ u32 flags; -+ } video; -+ } u; -+}; -+ -+struct mmal_msg_buffer_from_host { -+ /* The front 32 bytes of the buffer header are copied -+ * back to us in the reply to allow for context. This -+ * area is used to store two mmal_driver_buffer structures to -+ * allow for multiple concurrent service users. -+ */ -+ /* control data */ -+ struct mmal_driver_buffer drvbuf; -+ -+ /* referenced control data for passthrough buffer management */ -+ struct mmal_driver_buffer drvbuf_ref; -+ struct mmal_buffer_header buffer_header; /* buffer header itself */ -+ struct mmal_buffer_header_type_specific buffer_header_type_specific; -+ s32 is_zero_copy; -+ s32 has_reference; -+ -+ /** allows short data to be xfered in control message */ -+ u32 payload_in_message; -+ u8 short_data[MMAL_VC_SHORT_DATA]; -+}; -+ -+ -+/* port parameter setting */ -+ -+#define MMAL_WORKER_PORT_PARAMETER_SPACE 96 -+ -+struct mmal_msg_port_parameter_set { -+ u32 component_handle; /* component */ -+ u32 port_handle; /* port */ -+ u32 id; /* Parameter ID */ -+ u32 size; /* Parameter size */ -+ uint32_t value[MMAL_WORKER_PORT_PARAMETER_SPACE]; -+}; -+ -+struct mmal_msg_port_parameter_set_reply { -+ u32 status; /** enum mmal_msg_status todo: how does this -+ * differ to the one in the header? -+ */ -+}; -+ -+/* port parameter getting */ -+ -+struct mmal_msg_port_parameter_get { -+ u32 component_handle; /* component */ -+ u32 port_handle; /* port */ -+ u32 id; /* Parameter ID */ -+ u32 size; /* Parameter size */ -+}; -+ -+struct mmal_msg_port_parameter_get_reply { -+ u32 status; /* Status of mmal_port_parameter_get call */ -+ u32 id; /* Parameter ID */ -+ u32 size; /* Parameter size */ -+ uint32_t value[MMAL_WORKER_PORT_PARAMETER_SPACE]; -+}; -+ -+/* event messages */ -+#define MMAL_WORKER_EVENT_SPACE 256 -+ -+struct mmal_msg_event_to_host { -+ void *client_component; /* component context */ -+ -+ u32 port_type; -+ u32 port_num; -+ -+ u32 cmd; -+ u32 length; -+ u8 data[MMAL_WORKER_EVENT_SPACE]; -+ struct mmal_buffer_header *delayed_buffer; -+}; -+ -+/* all mmal messages are serialised through this structure */ -+struct mmal_msg { -+ /* header */ -+ struct mmal_msg_header h; -+ /* payload */ -+ union { -+ struct mmal_msg_version version; -+ -+ struct mmal_msg_component_create component_create; -+ struct mmal_msg_component_create_reply component_create_reply; -+ -+ struct mmal_msg_component_destroy component_destroy; -+ struct mmal_msg_component_destroy_reply component_destroy_reply; -+ -+ struct mmal_msg_component_enable component_enable; -+ struct mmal_msg_component_enable_reply component_enable_reply; -+ -+ struct mmal_msg_component_disable component_disable; -+ struct mmal_msg_component_disable_reply component_disable_reply; -+ -+ struct mmal_msg_port_info_get port_info_get; -+ struct mmal_msg_port_info_get_reply port_info_get_reply; -+ -+ struct mmal_msg_port_info_set port_info_set; -+ struct mmal_msg_port_info_set_reply port_info_set_reply; -+ -+ struct mmal_msg_port_action_port port_action_port; -+ struct mmal_msg_port_action_handle port_action_handle; -+ struct mmal_msg_port_action_reply port_action_reply; -+ -+ struct mmal_msg_buffer_from_host buffer_from_host; -+ -+ struct mmal_msg_port_parameter_set port_parameter_set; -+ struct mmal_msg_port_parameter_set_reply -+ port_parameter_set_reply; -+ struct mmal_msg_port_parameter_get -+ port_parameter_get; -+ struct mmal_msg_port_parameter_get_reply -+ port_parameter_get_reply; -+ -+ struct mmal_msg_event_to_host event_to_host; -+ -+ u8 payload[MMAL_MSG_MAX_PAYLOAD]; -+ } u; -+}; -diff -Nur linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-msg-port.h linux-rpi/drivers/media/platform/bcm2835/mmal-msg-port.h ---- linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-msg-port.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/media/platform/bcm2835/mmal-msg-port.h 2015-11-29 09:42:37.835237156 +0100 -@@ -0,0 +1,107 @@ -+/* -+ * Broadcom BM2835 V4L2 driver -+ * -+ * Copyright © 2013 Raspberry Pi (Trading) Ltd. -+ * -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file COPYING in the main directory of this archive -+ * for more details. -+ * -+ * Authors: Vincent Sanders -+ * Dave Stevenson -+ * Simon Mellor -+ * Luke Diamand -+ */ -+ -+/* MMAL_PORT_TYPE_T */ -+enum mmal_port_type { -+ MMAL_PORT_TYPE_UNKNOWN = 0, /**< Unknown port type */ -+ MMAL_PORT_TYPE_CONTROL, /**< Control port */ -+ MMAL_PORT_TYPE_INPUT, /**< Input port */ -+ MMAL_PORT_TYPE_OUTPUT, /**< Output port */ -+ MMAL_PORT_TYPE_CLOCK, /**< Clock port */ -+}; -+ -+/** The port is pass-through and doesn't need buffer headers allocated */ -+#define MMAL_PORT_CAPABILITY_PASSTHROUGH 0x01 -+/** The port wants to allocate the buffer payloads. -+ * This signals a preference that payload allocation should be done -+ * on this port for efficiency reasons. */ -+#define MMAL_PORT_CAPABILITY_ALLOCATION 0x02 -+/** The port supports format change events. -+ * This applies to input ports and is used to let the client know -+ * whether the port supports being reconfigured via a format -+ * change event (i.e. without having to disable the port). */ -+#define MMAL_PORT_CAPABILITY_SUPPORTS_EVENT_FORMAT_CHANGE 0x04 -+ -+/* mmal port structure (MMAL_PORT_T) -+ * -+ * most elements are informational only, the pointer values for -+ * interogation messages are generally provided as additional -+ * strucures within the message. When used to set values only teh -+ * buffer_num, buffer_size and userdata parameters are writable. -+ */ -+struct mmal_port { -+ void *priv; /* Private member used by the framework */ -+ const char *name; /* Port name. Used for debugging purposes (RO) */ -+ -+ u32 type; /* Type of the port (RO) enum mmal_port_type */ -+ u16 index; /* Index of the port in its type list (RO) */ -+ u16 index_all; /* Index of the port in the list of all ports (RO) */ -+ -+ u32 is_enabled; /* Indicates whether the port is enabled or not (RO) */ -+ struct mmal_es_format *format; /* Format of the elementary stream */ -+ -+ u32 buffer_num_min; /* Minimum number of buffers the port -+ * requires (RO). This is set by the -+ * component. -+ */ -+ -+ u32 buffer_size_min; /* Minimum size of buffers the port -+ * requires (RO). This is set by the -+ * component. -+ */ -+ -+ u32 buffer_alignment_min; /* Minimum alignment requirement for -+ * the buffers (RO). A value of -+ * zero means no special alignment -+ * requirements. This is set by the -+ * component. -+ */ -+ -+ u32 buffer_num_recommended; /* Number of buffers the port -+ * recommends for optimal -+ * performance (RO). A value of -+ * zero means no special -+ * recommendation. This is set -+ * by the component. -+ */ -+ -+ u32 buffer_size_recommended; /* Size of buffers the port -+ * recommends for optimal -+ * performance (RO). A value of -+ * zero means no special -+ * recommendation. This is set -+ * by the component. -+ */ -+ -+ u32 buffer_num; /* Actual number of buffers the port will use. -+ * This is set by the client. -+ */ -+ -+ u32 buffer_size; /* Actual maximum size of the buffers that -+ * will be sent to the port. This is set by -+ * the client. -+ */ -+ -+ void *component; /* Component this port belongs to (Read Only) */ -+ -+ void *userdata; /* Field reserved for use by the client */ -+ -+ u32 capabilities; /* Flags describing the capabilities of a -+ * port (RO). Bitwise combination of \ref -+ * portcapabilities "Port capabilities" -+ * values. -+ */ -+ -+}; -diff -Nur linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-parameters.h linux-rpi/drivers/media/platform/bcm2835/mmal-parameters.h ---- linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-parameters.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/media/platform/bcm2835/mmal-parameters.h 2015-11-29 09:42:37.835237156 +0100 -@@ -0,0 +1,656 @@ -+/* -+ * Broadcom BM2835 V4L2 driver -+ * -+ * Copyright © 2013 Raspberry Pi (Trading) Ltd. -+ * -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file COPYING in the main directory of this archive -+ * for more details. -+ * -+ * Authors: Vincent Sanders -+ * Dave Stevenson -+ * Simon Mellor -+ * Luke Diamand -+ */ -+ -+/* common parameters */ -+ -+/** @name Parameter groups -+ * Parameters are divided into groups, and then allocated sequentially within -+ * a group using an enum. -+ * @{ -+ */ -+ -+/** Common parameter ID group, used with many types of component. */ -+#define MMAL_PARAMETER_GROUP_COMMON (0<<16) -+/** Camera-specific parameter ID group. */ -+#define MMAL_PARAMETER_GROUP_CAMERA (1<<16) -+/** Video-specific parameter ID group. */ -+#define MMAL_PARAMETER_GROUP_VIDEO (2<<16) -+/** Audio-specific parameter ID group. */ -+#define MMAL_PARAMETER_GROUP_AUDIO (3<<16) -+/** Clock-specific parameter ID group. */ -+#define MMAL_PARAMETER_GROUP_CLOCK (4<<16) -+/** Miracast-specific parameter ID group. */ -+#define MMAL_PARAMETER_GROUP_MIRACAST (5<<16) -+ -+/* Common parameters */ -+enum mmal_parameter_common_type { -+ MMAL_PARAMETER_UNUSED /**< Never a valid parameter ID */ -+ = MMAL_PARAMETER_GROUP_COMMON, -+ MMAL_PARAMETER_SUPPORTED_ENCODINGS, /**< MMAL_PARAMETER_ENCODING_T */ -+ MMAL_PARAMETER_URI, /**< MMAL_PARAMETER_URI_T */ -+ -+ /** MMAL_PARAMETER_CHANGE_EVENT_REQUEST_T */ -+ MMAL_PARAMETER_CHANGE_EVENT_REQUEST, -+ -+ /** MMAL_PARAMETER_BOOLEAN_T */ -+ MMAL_PARAMETER_ZERO_COPY, -+ -+ /**< MMAL_PARAMETER_BUFFER_REQUIREMENTS_T */ -+ MMAL_PARAMETER_BUFFER_REQUIREMENTS, -+ -+ MMAL_PARAMETER_STATISTICS, /**< MMAL_PARAMETER_STATISTICS_T */ -+ MMAL_PARAMETER_CORE_STATISTICS, /**< MMAL_PARAMETER_CORE_STATISTICS_T */ -+ MMAL_PARAMETER_MEM_USAGE, /**< MMAL_PARAMETER_MEM_USAGE_T */ -+ MMAL_PARAMETER_BUFFER_FLAG_FILTER, /**< MMAL_PARAMETER_UINT32_T */ -+ MMAL_PARAMETER_SEEK, /**< MMAL_PARAMETER_SEEK_T */ -+ MMAL_PARAMETER_POWERMON_ENABLE, /**< MMAL_PARAMETER_BOOLEAN_T */ -+ MMAL_PARAMETER_LOGGING, /**< MMAL_PARAMETER_LOGGING_T */ -+ MMAL_PARAMETER_SYSTEM_TIME, /**< MMAL_PARAMETER_UINT64_T */ -+ MMAL_PARAMETER_NO_IMAGE_PADDING /**< MMAL_PARAMETER_BOOLEAN_T */ -+}; -+ -+/* camera parameters */ -+ -+enum mmal_parameter_camera_type { -+ /* 0 */ -+ /** @ref MMAL_PARAMETER_THUMBNAIL_CONFIG_T */ -+ MMAL_PARAMETER_THUMBNAIL_CONFIGURATION -+ = MMAL_PARAMETER_GROUP_CAMERA, -+ MMAL_PARAMETER_CAPTURE_QUALITY, /**< Unused? */ -+ MMAL_PARAMETER_ROTATION, /**< @ref MMAL_PARAMETER_INT32_T */ -+ MMAL_PARAMETER_EXIF_DISABLE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ -+ MMAL_PARAMETER_EXIF, /**< @ref MMAL_PARAMETER_EXIF_T */ -+ MMAL_PARAMETER_AWB_MODE, /**< @ref MMAL_PARAM_AWBMODE_T */ -+ MMAL_PARAMETER_IMAGE_EFFECT, /**< @ref MMAL_PARAMETER_IMAGEFX_T */ -+ MMAL_PARAMETER_COLOUR_EFFECT, /**< @ref MMAL_PARAMETER_COLOURFX_T */ -+ MMAL_PARAMETER_FLICKER_AVOID, /**< @ref MMAL_PARAMETER_FLICKERAVOID_T */ -+ MMAL_PARAMETER_FLASH, /**< @ref MMAL_PARAMETER_FLASH_T */ -+ MMAL_PARAMETER_REDEYE, /**< @ref MMAL_PARAMETER_REDEYE_T */ -+ MMAL_PARAMETER_FOCUS, /**< @ref MMAL_PARAMETER_FOCUS_T */ -+ MMAL_PARAMETER_FOCAL_LENGTHS, /**< Unused? */ -+ MMAL_PARAMETER_EXPOSURE_COMP, /**< @ref MMAL_PARAMETER_INT32_T */ -+ MMAL_PARAMETER_ZOOM, /**< @ref MMAL_PARAMETER_SCALEFACTOR_T */ -+ MMAL_PARAMETER_MIRROR, /**< @ref MMAL_PARAMETER_MIRROR_T */ -+ -+ /* 0x10 */ -+ MMAL_PARAMETER_CAMERA_NUM, /**< @ref MMAL_PARAMETER_UINT32_T */ -+ MMAL_PARAMETER_CAPTURE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ -+ MMAL_PARAMETER_EXPOSURE_MODE, /**< @ref MMAL_PARAMETER_EXPOSUREMODE_T */ -+ MMAL_PARAMETER_EXP_METERING_MODE, /**< @ref MMAL_PARAMETER_EXPOSUREMETERINGMODE_T */ -+ MMAL_PARAMETER_FOCUS_STATUS, /**< @ref MMAL_PARAMETER_FOCUS_STATUS_T */ -+ MMAL_PARAMETER_CAMERA_CONFIG, /**< @ref MMAL_PARAMETER_CAMERA_CONFIG_T */ -+ MMAL_PARAMETER_CAPTURE_STATUS, /**< @ref MMAL_PARAMETER_CAPTURE_STATUS_T */ -+ MMAL_PARAMETER_FACE_TRACK, /**< @ref MMAL_PARAMETER_FACE_TRACK_T */ -+ MMAL_PARAMETER_DRAW_BOX_FACES_AND_FOCUS, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ -+ MMAL_PARAMETER_JPEG_Q_FACTOR, /**< @ref MMAL_PARAMETER_UINT32_T */ -+ MMAL_PARAMETER_FRAME_RATE, /**< @ref MMAL_PARAMETER_FRAME_RATE_T */ -+ MMAL_PARAMETER_USE_STC, /**< @ref MMAL_PARAMETER_CAMERA_STC_MODE_T */ -+ MMAL_PARAMETER_CAMERA_INFO, /**< @ref MMAL_PARAMETER_CAMERA_INFO_T */ -+ MMAL_PARAMETER_VIDEO_STABILISATION, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ -+ MMAL_PARAMETER_FACE_TRACK_RESULTS, /**< @ref MMAL_PARAMETER_FACE_TRACK_RESULTS_T */ -+ MMAL_PARAMETER_ENABLE_RAW_CAPTURE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ -+ -+ /* 0x20 */ -+ MMAL_PARAMETER_DPF_FILE, /**< @ref MMAL_PARAMETER_URI_T */ -+ MMAL_PARAMETER_ENABLE_DPF_FILE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ -+ MMAL_PARAMETER_DPF_FAIL_IS_FATAL, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ -+ MMAL_PARAMETER_CAPTURE_MODE, /**< @ref MMAL_PARAMETER_CAPTUREMODE_T */ -+ MMAL_PARAMETER_FOCUS_REGIONS, /**< @ref MMAL_PARAMETER_FOCUS_REGIONS_T */ -+ MMAL_PARAMETER_INPUT_CROP, /**< @ref MMAL_PARAMETER_INPUT_CROP_T */ -+ MMAL_PARAMETER_SENSOR_INFORMATION, /**< @ref MMAL_PARAMETER_SENSOR_INFORMATION_T */ -+ MMAL_PARAMETER_FLASH_SELECT, /**< @ref MMAL_PARAMETER_FLASH_SELECT_T */ -+ MMAL_PARAMETER_FIELD_OF_VIEW, /**< @ref MMAL_PARAMETER_FIELD_OF_VIEW_T */ -+ MMAL_PARAMETER_HIGH_DYNAMIC_RANGE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ -+ MMAL_PARAMETER_DYNAMIC_RANGE_COMPRESSION, /**< @ref MMAL_PARAMETER_DRC_T */ -+ MMAL_PARAMETER_ALGORITHM_CONTROL, /**< @ref MMAL_PARAMETER_ALGORITHM_CONTROL_T */ -+ MMAL_PARAMETER_SHARPNESS, /**< @ref MMAL_PARAMETER_RATIONAL_T */ -+ MMAL_PARAMETER_CONTRAST, /**< @ref MMAL_PARAMETER_RATIONAL_T */ -+ MMAL_PARAMETER_BRIGHTNESS, /**< @ref MMAL_PARAMETER_RATIONAL_T */ -+ MMAL_PARAMETER_SATURATION, /**< @ref MMAL_PARAMETER_RATIONAL_T */ -+ -+ /* 0x30 */ -+ MMAL_PARAMETER_ISO, /**< @ref MMAL_PARAMETER_UINT32_T */ -+ MMAL_PARAMETER_ANTISHAKE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ -+ -+ /** @ref MMAL_PARAMETER_IMAGEFX_PARAMETERS_T */ -+ MMAL_PARAMETER_IMAGE_EFFECT_PARAMETERS, -+ -+ /** @ref MMAL_PARAMETER_BOOLEAN_T */ -+ MMAL_PARAMETER_CAMERA_BURST_CAPTURE, -+ -+ /** @ref MMAL_PARAMETER_UINT32_T */ -+ MMAL_PARAMETER_CAMERA_MIN_ISO, -+ -+ /** @ref MMAL_PARAMETER_CAMERA_USE_CASE_T */ -+ MMAL_PARAMETER_CAMERA_USE_CASE, -+ -+ /**< @ref MMAL_PARAMETER_BOOLEAN_T */ -+ MMAL_PARAMETER_CAPTURE_STATS_PASS, -+ -+ /** @ref MMAL_PARAMETER_UINT32_T */ -+ MMAL_PARAMETER_CAMERA_CUSTOM_SENSOR_CONFIG, -+ -+ /** @ref MMAL_PARAMETER_BOOLEAN_T */ -+ MMAL_PARAMETER_ENABLE_REGISTER_FILE, -+ -+ /** @ref MMAL_PARAMETER_BOOLEAN_T */ -+ MMAL_PARAMETER_REGISTER_FAIL_IS_FATAL, -+ -+ /** @ref MMAL_PARAMETER_CONFIGFILE_T */ -+ MMAL_PARAMETER_CONFIGFILE_REGISTERS, -+ -+ /** @ref MMAL_PARAMETER_CONFIGFILE_CHUNK_T */ -+ MMAL_PARAMETER_CONFIGFILE_CHUNK_REGISTERS, -+ MMAL_PARAMETER_JPEG_ATTACH_LOG, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ -+ MMAL_PARAMETER_ZERO_SHUTTER_LAG, /**< @ref MMAL_PARAMETER_ZEROSHUTTERLAG_T */ -+ MMAL_PARAMETER_FPS_RANGE, /**< @ref MMAL_PARAMETER_FPS_RANGE_T */ -+ MMAL_PARAMETER_CAPTURE_EXPOSURE_COMP, /**< @ref MMAL_PARAMETER_INT32_T */ -+ -+ /* 0x40 */ -+ MMAL_PARAMETER_SW_SHARPEN_DISABLE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ -+ MMAL_PARAMETER_FLASH_REQUIRED, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ -+ MMAL_PARAMETER_SW_SATURATION_DISABLE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ -+ MMAL_PARAMETER_SHUTTER_SPEED, /**< Takes a @ref MMAL_PARAMETER_UINT32_T */ -+ MMAL_PARAMETER_CUSTOM_AWB_GAINS, /**< Takes a @ref MMAL_PARAMETER_AWB_GAINS_T */ -+}; -+ -+struct mmal_parameter_rational { -+ s32 num; /**< Numerator */ -+ s32 den; /**< Denominator */ -+}; -+ -+enum mmal_parameter_camera_config_timestamp_mode { -+ MMAL_PARAM_TIMESTAMP_MODE_ZERO = 0, /* Always timestamp frames as 0 */ -+ MMAL_PARAM_TIMESTAMP_MODE_RAW_STC, /* Use the raw STC value -+ * for the frame timestamp -+ */ -+ MMAL_PARAM_TIMESTAMP_MODE_RESET_STC, /* Use the STC timestamp -+ * but subtract the -+ * timestamp of the first -+ * frame sent to give a -+ * zero based timestamp. -+ */ -+}; -+ -+struct mmal_parameter_fps_range { -+ /**< Low end of the permitted framerate range */ -+ struct mmal_parameter_rational fps_low; -+ /**< High end of the permitted framerate range */ -+ struct mmal_parameter_rational fps_high; -+}; -+ -+ -+/* camera configuration parameter */ -+struct mmal_parameter_camera_config { -+ /* Parameters for setting up the image pools */ -+ u32 max_stills_w; /* Max size of stills capture */ -+ u32 max_stills_h; -+ u32 stills_yuv422; /* Allow YUV422 stills capture */ -+ u32 one_shot_stills; /* Continuous or one shot stills captures. */ -+ -+ u32 max_preview_video_w; /* Max size of the preview or video -+ * capture frames -+ */ -+ u32 max_preview_video_h; -+ u32 num_preview_video_frames; -+ -+ /** Sets the height of the circular buffer for stills capture. */ -+ u32 stills_capture_circular_buffer_height; -+ -+ /** Allows preview/encode to resume as fast as possible after the stills -+ * input frame has been received, and then processes the still frame in -+ * the background whilst preview/encode has resumed. -+ * Actual mode is controlled by MMAL_PARAMETER_CAPTURE_MODE. -+ */ -+ u32 fast_preview_resume; -+ -+ /** Selects algorithm for timestamping frames if -+ * there is no clock component connected. -+ * enum mmal_parameter_camera_config_timestamp_mode -+ */ -+ s32 use_stc_timestamp; -+}; -+ -+ -+enum mmal_parameter_exposuremode { -+ MMAL_PARAM_EXPOSUREMODE_OFF, -+ MMAL_PARAM_EXPOSUREMODE_AUTO, -+ MMAL_PARAM_EXPOSUREMODE_NIGHT, -+ MMAL_PARAM_EXPOSUREMODE_NIGHTPREVIEW, -+ MMAL_PARAM_EXPOSUREMODE_BACKLIGHT, -+ MMAL_PARAM_EXPOSUREMODE_SPOTLIGHT, -+ MMAL_PARAM_EXPOSUREMODE_SPORTS, -+ MMAL_PARAM_EXPOSUREMODE_SNOW, -+ MMAL_PARAM_EXPOSUREMODE_BEACH, -+ MMAL_PARAM_EXPOSUREMODE_VERYLONG, -+ MMAL_PARAM_EXPOSUREMODE_FIXEDFPS, -+ MMAL_PARAM_EXPOSUREMODE_ANTISHAKE, -+ MMAL_PARAM_EXPOSUREMODE_FIREWORKS, -+}; -+ -+enum mmal_parameter_exposuremeteringmode { -+ MMAL_PARAM_EXPOSUREMETERINGMODE_AVERAGE, -+ MMAL_PARAM_EXPOSUREMETERINGMODE_SPOT, -+ MMAL_PARAM_EXPOSUREMETERINGMODE_BACKLIT, -+ MMAL_PARAM_EXPOSUREMETERINGMODE_MATRIX, -+}; -+ -+enum mmal_parameter_awbmode { -+ MMAL_PARAM_AWBMODE_OFF, -+ MMAL_PARAM_AWBMODE_AUTO, -+ MMAL_PARAM_AWBMODE_SUNLIGHT, -+ MMAL_PARAM_AWBMODE_CLOUDY, -+ MMAL_PARAM_AWBMODE_SHADE, -+ MMAL_PARAM_AWBMODE_TUNGSTEN, -+ MMAL_PARAM_AWBMODE_FLUORESCENT, -+ MMAL_PARAM_AWBMODE_INCANDESCENT, -+ MMAL_PARAM_AWBMODE_FLASH, -+ MMAL_PARAM_AWBMODE_HORIZON, -+}; -+ -+enum mmal_parameter_imagefx { -+ MMAL_PARAM_IMAGEFX_NONE, -+ MMAL_PARAM_IMAGEFX_NEGATIVE, -+ MMAL_PARAM_IMAGEFX_SOLARIZE, -+ MMAL_PARAM_IMAGEFX_POSTERIZE, -+ MMAL_PARAM_IMAGEFX_WHITEBOARD, -+ MMAL_PARAM_IMAGEFX_BLACKBOARD, -+ MMAL_PARAM_IMAGEFX_SKETCH, -+ MMAL_PARAM_IMAGEFX_DENOISE, -+ MMAL_PARAM_IMAGEFX_EMBOSS, -+ MMAL_PARAM_IMAGEFX_OILPAINT, -+ MMAL_PARAM_IMAGEFX_HATCH, -+ MMAL_PARAM_IMAGEFX_GPEN, -+ MMAL_PARAM_IMAGEFX_PASTEL, -+ MMAL_PARAM_IMAGEFX_WATERCOLOUR, -+ MMAL_PARAM_IMAGEFX_FILM, -+ MMAL_PARAM_IMAGEFX_BLUR, -+ MMAL_PARAM_IMAGEFX_SATURATION, -+ MMAL_PARAM_IMAGEFX_COLOURSWAP, -+ MMAL_PARAM_IMAGEFX_WASHEDOUT, -+ MMAL_PARAM_IMAGEFX_POSTERISE, -+ MMAL_PARAM_IMAGEFX_COLOURPOINT, -+ MMAL_PARAM_IMAGEFX_COLOURBALANCE, -+ MMAL_PARAM_IMAGEFX_CARTOON, -+}; -+ -+enum MMAL_PARAM_FLICKERAVOID_T { -+ MMAL_PARAM_FLICKERAVOID_OFF, -+ MMAL_PARAM_FLICKERAVOID_AUTO, -+ MMAL_PARAM_FLICKERAVOID_50HZ, -+ MMAL_PARAM_FLICKERAVOID_60HZ, -+ MMAL_PARAM_FLICKERAVOID_MAX = 0x7FFFFFFF -+}; -+ -+struct mmal_parameter_awbgains { -+ struct mmal_parameter_rational r_gain; /**< Red gain */ -+ struct mmal_parameter_rational b_gain; /**< Blue gain */ -+}; -+ -+/** Manner of video rate control */ -+enum mmal_parameter_rate_control_mode { -+ MMAL_VIDEO_RATECONTROL_DEFAULT, -+ MMAL_VIDEO_RATECONTROL_VARIABLE, -+ MMAL_VIDEO_RATECONTROL_CONSTANT, -+ MMAL_VIDEO_RATECONTROL_VARIABLE_SKIP_FRAMES, -+ MMAL_VIDEO_RATECONTROL_CONSTANT_SKIP_FRAMES -+}; -+ -+enum mmal_video_profile { -+ MMAL_VIDEO_PROFILE_H263_BASELINE, -+ MMAL_VIDEO_PROFILE_H263_H320CODING, -+ MMAL_VIDEO_PROFILE_H263_BACKWARDCOMPATIBLE, -+ MMAL_VIDEO_PROFILE_H263_ISWV2, -+ MMAL_VIDEO_PROFILE_H263_ISWV3, -+ MMAL_VIDEO_PROFILE_H263_HIGHCOMPRESSION, -+ MMAL_VIDEO_PROFILE_H263_INTERNET, -+ MMAL_VIDEO_PROFILE_H263_INTERLACE, -+ MMAL_VIDEO_PROFILE_H263_HIGHLATENCY, -+ MMAL_VIDEO_PROFILE_MP4V_SIMPLE, -+ MMAL_VIDEO_PROFILE_MP4V_SIMPLESCALABLE, -+ MMAL_VIDEO_PROFILE_MP4V_CORE, -+ MMAL_VIDEO_PROFILE_MP4V_MAIN, -+ MMAL_VIDEO_PROFILE_MP4V_NBIT, -+ MMAL_VIDEO_PROFILE_MP4V_SCALABLETEXTURE, -+ MMAL_VIDEO_PROFILE_MP4V_SIMPLEFACE, -+ MMAL_VIDEO_PROFILE_MP4V_SIMPLEFBA, -+ MMAL_VIDEO_PROFILE_MP4V_BASICANIMATED, -+ MMAL_VIDEO_PROFILE_MP4V_HYBRID, -+ MMAL_VIDEO_PROFILE_MP4V_ADVANCEDREALTIME, -+ MMAL_VIDEO_PROFILE_MP4V_CORESCALABLE, -+ MMAL_VIDEO_PROFILE_MP4V_ADVANCEDCODING, -+ MMAL_VIDEO_PROFILE_MP4V_ADVANCEDCORE, -+ MMAL_VIDEO_PROFILE_MP4V_ADVANCEDSCALABLE, -+ MMAL_VIDEO_PROFILE_MP4V_ADVANCEDSIMPLE, -+ MMAL_VIDEO_PROFILE_H264_BASELINE, -+ MMAL_VIDEO_PROFILE_H264_MAIN, -+ MMAL_VIDEO_PROFILE_H264_EXTENDED, -+ MMAL_VIDEO_PROFILE_H264_HIGH, -+ MMAL_VIDEO_PROFILE_H264_HIGH10, -+ MMAL_VIDEO_PROFILE_H264_HIGH422, -+ MMAL_VIDEO_PROFILE_H264_HIGH444, -+ MMAL_VIDEO_PROFILE_H264_CONSTRAINED_BASELINE, -+ MMAL_VIDEO_PROFILE_DUMMY = 0x7FFFFFFF -+}; -+ -+enum mmal_video_level { -+ MMAL_VIDEO_LEVEL_H263_10, -+ MMAL_VIDEO_LEVEL_H263_20, -+ MMAL_VIDEO_LEVEL_H263_30, -+ MMAL_VIDEO_LEVEL_H263_40, -+ MMAL_VIDEO_LEVEL_H263_45, -+ MMAL_VIDEO_LEVEL_H263_50, -+ MMAL_VIDEO_LEVEL_H263_60, -+ MMAL_VIDEO_LEVEL_H263_70, -+ MMAL_VIDEO_LEVEL_MP4V_0, -+ MMAL_VIDEO_LEVEL_MP4V_0b, -+ MMAL_VIDEO_LEVEL_MP4V_1, -+ MMAL_VIDEO_LEVEL_MP4V_2, -+ MMAL_VIDEO_LEVEL_MP4V_3, -+ MMAL_VIDEO_LEVEL_MP4V_4, -+ MMAL_VIDEO_LEVEL_MP4V_4a, -+ MMAL_VIDEO_LEVEL_MP4V_5, -+ MMAL_VIDEO_LEVEL_MP4V_6, -+ MMAL_VIDEO_LEVEL_H264_1, -+ MMAL_VIDEO_LEVEL_H264_1b, -+ MMAL_VIDEO_LEVEL_H264_11, -+ MMAL_VIDEO_LEVEL_H264_12, -+ MMAL_VIDEO_LEVEL_H264_13, -+ MMAL_VIDEO_LEVEL_H264_2, -+ MMAL_VIDEO_LEVEL_H264_21, -+ MMAL_VIDEO_LEVEL_H264_22, -+ MMAL_VIDEO_LEVEL_H264_3, -+ MMAL_VIDEO_LEVEL_H264_31, -+ MMAL_VIDEO_LEVEL_H264_32, -+ MMAL_VIDEO_LEVEL_H264_4, -+ MMAL_VIDEO_LEVEL_H264_41, -+ MMAL_VIDEO_LEVEL_H264_42, -+ MMAL_VIDEO_LEVEL_H264_5, -+ MMAL_VIDEO_LEVEL_H264_51, -+ MMAL_VIDEO_LEVEL_DUMMY = 0x7FFFFFFF -+}; -+ -+struct mmal_parameter_video_profile { -+ enum mmal_video_profile profile; -+ enum mmal_video_level level; -+}; -+ -+/* video parameters */ -+ -+enum mmal_parameter_video_type { -+ /** @ref MMAL_DISPLAYREGION_T */ -+ MMAL_PARAMETER_DISPLAYREGION = MMAL_PARAMETER_GROUP_VIDEO, -+ -+ /** @ref MMAL_PARAMETER_VIDEO_PROFILE_T */ -+ MMAL_PARAMETER_SUPPORTED_PROFILES, -+ -+ /** @ref MMAL_PARAMETER_VIDEO_PROFILE_T */ -+ MMAL_PARAMETER_PROFILE, -+ -+ /** @ref MMAL_PARAMETER_UINT32_T */ -+ MMAL_PARAMETER_INTRAPERIOD, -+ -+ /** @ref MMAL_PARAMETER_VIDEO_RATECONTROL_T */ -+ MMAL_PARAMETER_RATECONTROL, -+ -+ /** @ref MMAL_PARAMETER_VIDEO_NALUNITFORMAT_T */ -+ MMAL_PARAMETER_NALUNITFORMAT, -+ -+ /** @ref MMAL_PARAMETER_BOOLEAN_T */ -+ MMAL_PARAMETER_MINIMISE_FRAGMENTATION, -+ -+ /** @ref MMAL_PARAMETER_UINT32_T. -+ * Setting the value to zero resets to the default (one slice per frame). -+ */ -+ MMAL_PARAMETER_MB_ROWS_PER_SLICE, -+ -+ /** @ref MMAL_PARAMETER_VIDEO_LEVEL_EXTENSION_T */ -+ MMAL_PARAMETER_VIDEO_LEVEL_EXTENSION, -+ -+ /** @ref MMAL_PARAMETER_VIDEO_EEDE_ENABLE_T */ -+ MMAL_PARAMETER_VIDEO_EEDE_ENABLE, -+ -+ /** @ref MMAL_PARAMETER_VIDEO_EEDE_LOSSRATE_T */ -+ MMAL_PARAMETER_VIDEO_EEDE_LOSSRATE, -+ -+ /** @ref MMAL_PARAMETER_BOOLEAN_T. Request an I-frame. */ -+ MMAL_PARAMETER_VIDEO_REQUEST_I_FRAME, -+ /** @ref MMAL_PARAMETER_VIDEO_INTRA_REFRESH_T */ -+ MMAL_PARAMETER_VIDEO_INTRA_REFRESH, -+ -+ /** @ref MMAL_PARAMETER_BOOLEAN_T. */ -+ MMAL_PARAMETER_VIDEO_IMMUTABLE_INPUT, -+ -+ /** @ref MMAL_PARAMETER_UINT32_T. Run-time bit rate control */ -+ MMAL_PARAMETER_VIDEO_BIT_RATE, -+ -+ /** @ref MMAL_PARAMETER_FRAME_RATE_T */ -+ MMAL_PARAMETER_VIDEO_FRAME_RATE, -+ -+ /** @ref MMAL_PARAMETER_UINT32_T. */ -+ MMAL_PARAMETER_VIDEO_ENCODE_MIN_QUANT, -+ -+ /** @ref MMAL_PARAMETER_UINT32_T. */ -+ MMAL_PARAMETER_VIDEO_ENCODE_MAX_QUANT, -+ -+ /** @ref MMAL_PARAMETER_VIDEO_ENCODE_RC_MODEL_T. */ -+ MMAL_PARAMETER_VIDEO_ENCODE_RC_MODEL, -+ -+ MMAL_PARAMETER_EXTRA_BUFFERS, /**< @ref MMAL_PARAMETER_UINT32_T. */ -+ /** @ref MMAL_PARAMETER_UINT32_T. -+ * Changing this parameter from the default can reduce frame rate -+ * because image buffers need to be re-pitched. -+ */ -+ MMAL_PARAMETER_VIDEO_ALIGN_HORIZ, -+ -+ /** @ref MMAL_PARAMETER_UINT32_T. -+ * Changing this parameter from the default can reduce frame rate -+ * because image buffers need to be re-pitched. -+ */ -+ MMAL_PARAMETER_VIDEO_ALIGN_VERT, -+ -+ /** @ref MMAL_PARAMETER_BOOLEAN_T. */ -+ MMAL_PARAMETER_VIDEO_DROPPABLE_PFRAMES, -+ -+ /** @ref MMAL_PARAMETER_UINT32_T. */ -+ MMAL_PARAMETER_VIDEO_ENCODE_INITIAL_QUANT, -+ -+ /**< @ref MMAL_PARAMETER_UINT32_T. */ -+ MMAL_PARAMETER_VIDEO_ENCODE_QP_P, -+ -+ /**< @ref MMAL_PARAMETER_UINT32_T. */ -+ MMAL_PARAMETER_VIDEO_ENCODE_RC_SLICE_DQUANT, -+ -+ /** @ref MMAL_PARAMETER_UINT32_T */ -+ MMAL_PARAMETER_VIDEO_ENCODE_FRAME_LIMIT_BITS, -+ -+ /** @ref MMAL_PARAMETER_UINT32_T. */ -+ MMAL_PARAMETER_VIDEO_ENCODE_PEAK_RATE, -+ -+ /* H264 specific parameters */ -+ -+ /** @ref MMAL_PARAMETER_BOOLEAN_T. */ -+ MMAL_PARAMETER_VIDEO_ENCODE_H264_DISABLE_CABAC, -+ -+ /** @ref MMAL_PARAMETER_BOOLEAN_T. */ -+ MMAL_PARAMETER_VIDEO_ENCODE_H264_LOW_LATENCY, -+ -+ /** @ref MMAL_PARAMETER_BOOLEAN_T. */ -+ MMAL_PARAMETER_VIDEO_ENCODE_H264_AU_DELIMITERS, -+ -+ /** @ref MMAL_PARAMETER_UINT32_T. */ -+ MMAL_PARAMETER_VIDEO_ENCODE_H264_DEBLOCK_IDC, -+ -+ /** @ref MMAL_PARAMETER_VIDEO_ENCODER_H264_MB_INTRA_MODES_T. */ -+ MMAL_PARAMETER_VIDEO_ENCODE_H264_MB_INTRA_MODE, -+ -+ /** @ref MMAL_PARAMETER_BOOLEAN_T */ -+ MMAL_PARAMETER_VIDEO_ENCODE_HEADER_ON_OPEN, -+ -+ /** @ref MMAL_PARAMETER_BOOLEAN_T */ -+ MMAL_PARAMETER_VIDEO_ENCODE_PRECODE_FOR_QP, -+ -+ /** @ref MMAL_PARAMETER_VIDEO_DRM_INIT_INFO_T. */ -+ MMAL_PARAMETER_VIDEO_DRM_INIT_INFO, -+ -+ /** @ref MMAL_PARAMETER_BOOLEAN_T */ -+ MMAL_PARAMETER_VIDEO_TIMESTAMP_FIFO, -+ -+ /** @ref MMAL_PARAMETER_BOOLEAN_T */ -+ MMAL_PARAMETER_VIDEO_DECODE_ERROR_CONCEALMENT, -+ -+ /** @ref MMAL_PARAMETER_VIDEO_DRM_PROTECT_BUFFER_T. */ -+ MMAL_PARAMETER_VIDEO_DRM_PROTECT_BUFFER, -+ -+ /** @ref MMAL_PARAMETER_BYTES_T */ -+ MMAL_PARAMETER_VIDEO_DECODE_CONFIG_VD3, -+ -+ /**< @ref MMAL_PARAMETER_BOOLEAN_T */ -+ MMAL_PARAMETER_VIDEO_ENCODE_H264_VCL_HRD_PARAMETERS, -+ -+ /**< @ref MMAL_PARAMETER_BOOLEAN_T */ -+ MMAL_PARAMETER_VIDEO_ENCODE_H264_LOW_DELAY_HRD_FLAG, -+ -+ /**< @ref MMAL_PARAMETER_BOOLEAN_T */ -+ MMAL_PARAMETER_VIDEO_ENCODE_INLINE_HEADER -+}; -+ -+/** Valid mirror modes */ -+enum mmal_parameter_mirror { -+ MMAL_PARAM_MIRROR_NONE, -+ MMAL_PARAM_MIRROR_VERTICAL, -+ MMAL_PARAM_MIRROR_HORIZONTAL, -+ MMAL_PARAM_MIRROR_BOTH, -+}; -+ -+enum mmal_parameter_displaytransform { -+ MMAL_DISPLAY_ROT0 = 0, -+ MMAL_DISPLAY_MIRROR_ROT0 = 1, -+ MMAL_DISPLAY_MIRROR_ROT180 = 2, -+ MMAL_DISPLAY_ROT180 = 3, -+ MMAL_DISPLAY_MIRROR_ROT90 = 4, -+ MMAL_DISPLAY_ROT270 = 5, -+ MMAL_DISPLAY_ROT90 = 6, -+ MMAL_DISPLAY_MIRROR_ROT270 = 7, -+}; -+ -+enum mmal_parameter_displaymode { -+ MMAL_DISPLAY_MODE_FILL = 0, -+ MMAL_DISPLAY_MODE_LETTERBOX = 1, -+}; -+ -+enum mmal_parameter_displayset { -+ MMAL_DISPLAY_SET_NONE = 0, -+ MMAL_DISPLAY_SET_NUM = 1, -+ MMAL_DISPLAY_SET_FULLSCREEN = 2, -+ MMAL_DISPLAY_SET_TRANSFORM = 4, -+ MMAL_DISPLAY_SET_DEST_RECT = 8, -+ MMAL_DISPLAY_SET_SRC_RECT = 0x10, -+ MMAL_DISPLAY_SET_MODE = 0x20, -+ MMAL_DISPLAY_SET_PIXEL = 0x40, -+ MMAL_DISPLAY_SET_NOASPECT = 0x80, -+ MMAL_DISPLAY_SET_LAYER = 0x100, -+ MMAL_DISPLAY_SET_COPYPROTECT = 0x200, -+ MMAL_DISPLAY_SET_ALPHA = 0x400, -+}; -+ -+struct mmal_parameter_displayregion { -+ /** Bitfield that indicates which fields are set and should be -+ * used. All other fields will maintain their current value. -+ * \ref MMAL_DISPLAYSET_T defines the bits that can be -+ * combined. -+ */ -+ u32 set; -+ -+ /** Describes the display output device, with 0 typically -+ * being a directly connected LCD display. The actual values -+ * will depend on the hardware. Code using hard-wired numbers -+ * (e.g. 2) is certain to fail. -+ */ -+ -+ u32 display_num; -+ /** Indicates that we are using the full device screen area, -+ * rather than a window of the display. If zero, then -+ * dest_rect is used to specify a region of the display to -+ * use. -+ */ -+ -+ s32 fullscreen; -+ /** Indicates any rotation or flipping used to map frames onto -+ * the natural display orientation. -+ */ -+ u32 transform; /* enum mmal_parameter_displaytransform */ -+ -+ /** Where to display the frame within the screen, if -+ * fullscreen is zero. -+ */ -+ struct vchiq_mmal_rect dest_rect; -+ -+ /** Indicates which area of the frame to display. If all -+ * values are zero, the whole frame will be used. -+ */ -+ struct vchiq_mmal_rect src_rect; -+ -+ /** If set to non-zero, indicates that any display scaling -+ * should disregard the aspect ratio of the frame region being -+ * displayed. -+ */ -+ s32 noaspect; -+ -+ /** Indicates how the image should be scaled to fit the -+ * display. \code MMAL_DISPLAY_MODE_FILL \endcode indicates -+ * that the image should fill the screen by potentially -+ * cropping the frames. Setting \code mode \endcode to \code -+ * MMAL_DISPLAY_MODE_LETTERBOX \endcode indicates that all the -+ * source region should be displayed and black bars added if -+ * necessary. -+ */ -+ u32 mode; /* enum mmal_parameter_displaymode */ -+ -+ /** If non-zero, defines the width of a source pixel relative -+ * to \code pixel_y \endcode. If zero, then pixels default to -+ * being square. -+ */ -+ u32 pixel_x; -+ -+ /** If non-zero, defines the height of a source pixel relative -+ * to \code pixel_x \endcode. If zero, then pixels default to -+ * being square. -+ */ -+ u32 pixel_y; -+ -+ /** Sets the relative depth of the images, with greater values -+ * being in front of smaller values. -+ */ -+ u32 layer; -+ -+ /** Set to non-zero to ensure copy protection is used on -+ * output. -+ */ -+ s32 copyprotect_required; -+ -+ /** Level of opacity of the layer, where zero is fully -+ * transparent and 255 is fully opaque. -+ */ -+ u32 alpha; -+}; -+ -+#define MMAL_MAX_IMAGEFX_PARAMETERS 5 -+ -+struct mmal_parameter_imagefx_parameters { -+ enum mmal_parameter_imagefx effect; -+ u32 num_effect_params; -+ u32 effect_parameter[MMAL_MAX_IMAGEFX_PARAMETERS]; -+}; -diff -Nur linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-vchiq.c linux-rpi/drivers/media/platform/bcm2835/mmal-vchiq.c ---- linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-vchiq.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/media/platform/bcm2835/mmal-vchiq.c 2015-11-29 09:42:37.835237156 +0100 -@@ -0,0 +1,1916 @@ -+/* -+ * Broadcom BM2835 V4L2 driver -+ * -+ * Copyright © 2013 Raspberry Pi (Trading) Ltd. -+ * -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file COPYING in the main directory of this archive -+ * for more details. -+ * -+ * Authors: Vincent Sanders -+ * Dave Stevenson -+ * Simon Mellor -+ * Luke Diamand -+ * -+ * V4L2 driver MMAL vchiq interface code -+ */ -+ -+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "mmal-common.h" -+#include "mmal-vchiq.h" -+#include "mmal-msg.h" -+ -+#define USE_VCHIQ_ARM -+#include "interface/vchi/vchi.h" -+ -+/* maximum number of components supported */ -+#define VCHIQ_MMAL_MAX_COMPONENTS 4 -+ -+/*#define FULL_MSG_DUMP 1*/ -+ -+#ifdef DEBUG -+static const char *const msg_type_names[] = { -+ "UNKNOWN", -+ "QUIT", -+ "SERVICE_CLOSED", -+ "GET_VERSION", -+ "COMPONENT_CREATE", -+ "COMPONENT_DESTROY", -+ "COMPONENT_ENABLE", -+ "COMPONENT_DISABLE", -+ "PORT_INFO_GET", -+ "PORT_INFO_SET", -+ "PORT_ACTION", -+ "BUFFER_FROM_HOST", -+ "BUFFER_TO_HOST", -+ "GET_STATS", -+ "PORT_PARAMETER_SET", -+ "PORT_PARAMETER_GET", -+ "EVENT_TO_HOST", -+ "GET_CORE_STATS_FOR_PORT", -+ "OPAQUE_ALLOCATOR", -+ "CONSUME_MEM", -+ "LMK", -+ "OPAQUE_ALLOCATOR_DESC", -+ "DRM_GET_LHS32", -+ "DRM_GET_TIME", -+ "BUFFER_FROM_HOST_ZEROLEN", -+ "PORT_FLUSH", -+ "HOST_LOG", -+}; -+#endif -+ -+static const char *const port_action_type_names[] = { -+ "UNKNOWN", -+ "ENABLE", -+ "DISABLE", -+ "FLUSH", -+ "CONNECT", -+ "DISCONNECT", -+ "SET_REQUIREMENTS", -+}; -+ -+#if defined(DEBUG) -+#if defined(FULL_MSG_DUMP) -+#define DBG_DUMP_MSG(MSG, MSG_LEN, TITLE) \ -+ do { \ -+ pr_debug(TITLE" type:%s(%d) length:%d\n", \ -+ msg_type_names[(MSG)->h.type], \ -+ (MSG)->h.type, (MSG_LEN)); \ -+ print_hex_dump(KERN_DEBUG, "<h.type], \ -+ (MSG)->h.type, (MSG_LEN)); \ -+ } -+#endif -+#else -+#define DBG_DUMP_MSG(MSG, MSG_LEN, TITLE) -+#endif -+ -+/* normal message context */ -+struct mmal_msg_context { -+ union { -+ struct { -+ /* work struct for defered callback - must come first */ -+ struct work_struct work; -+ /* mmal instance */ -+ struct vchiq_mmal_instance *instance; -+ /* mmal port */ -+ struct vchiq_mmal_port *port; -+ /* actual buffer used to store bulk reply */ -+ struct mmal_buffer *buffer; -+ /* amount of buffer used */ -+ unsigned long buffer_used; -+ /* MMAL buffer flags */ -+ u32 mmal_flags; -+ /* Presentation and Decode timestamps */ -+ s64 pts; -+ s64 dts; -+ -+ int status; /* context status */ -+ -+ } bulk; /* bulk data */ -+ -+ struct { -+ /* message handle to release */ -+ VCHI_HELD_MSG_T msg_handle; -+ /* pointer to received message */ -+ struct mmal_msg *msg; -+ /* received message length */ -+ u32 msg_len; -+ /* completion upon reply */ -+ struct completion cmplt; -+ } sync; /* synchronous response */ -+ } u; -+ -+}; -+ -+struct vchiq_mmal_instance { -+ VCHI_SERVICE_HANDLE_T handle; -+ -+ /* ensure serialised access to service */ -+ struct mutex vchiq_mutex; -+ -+ /* ensure serialised access to bulk operations */ -+ struct mutex bulk_mutex; -+ -+ /* vmalloc page to receive scratch bulk xfers into */ -+ void *bulk_scratch; -+ -+ /* component to use next */ -+ int component_idx; -+ struct vchiq_mmal_component component[VCHIQ_MMAL_MAX_COMPONENTS]; -+}; -+ -+static struct mmal_msg_context *get_msg_context(struct vchiq_mmal_instance -+ *instance) -+{ -+ struct mmal_msg_context *msg_context; -+ -+ /* todo: should this be allocated from a pool to avoid kmalloc */ -+ msg_context = kmalloc(sizeof(*msg_context), GFP_KERNEL); -+ memset(msg_context, 0, sizeof(*msg_context)); -+ -+ return msg_context; -+} -+ -+static void release_msg_context(struct mmal_msg_context *msg_context) -+{ -+ kfree(msg_context); -+} -+ -+/* deals with receipt of event to host message */ -+static void event_to_host_cb(struct vchiq_mmal_instance *instance, -+ struct mmal_msg *msg, u32 msg_len) -+{ -+ pr_debug("unhandled event\n"); -+ pr_debug("component:%p port type:%d num:%d cmd:0x%x length:%d\n", -+ msg->u.event_to_host.client_component, -+ msg->u.event_to_host.port_type, -+ msg->u.event_to_host.port_num, -+ msg->u.event_to_host.cmd, msg->u.event_to_host.length); -+} -+ -+/* workqueue scheduled callback -+ * -+ * we do this because it is important we do not call any other vchiq -+ * sync calls from witin the message delivery thread -+ */ -+static void buffer_work_cb(struct work_struct *work) -+{ -+ struct mmal_msg_context *msg_context = (struct mmal_msg_context *)work; -+ -+ msg_context->u.bulk.port->buffer_cb(msg_context->u.bulk.instance, -+ msg_context->u.bulk.port, -+ msg_context->u.bulk.status, -+ msg_context->u.bulk.buffer, -+ msg_context->u.bulk.buffer_used, -+ msg_context->u.bulk.mmal_flags, -+ msg_context->u.bulk.dts, -+ msg_context->u.bulk.pts); -+ -+ /* release message context */ -+ release_msg_context(msg_context); -+} -+ -+/* enqueue a bulk receive for a given message context */ -+static int bulk_receive(struct vchiq_mmal_instance *instance, -+ struct mmal_msg *msg, -+ struct mmal_msg_context *msg_context) -+{ -+ unsigned long rd_len; -+ unsigned long flags = 0; -+ int ret; -+ -+ /* bulk mutex stops other bulk operations while we have a -+ * receive in progress - released in callback -+ */ -+ ret = mutex_lock_interruptible(&instance->bulk_mutex); -+ if (ret != 0) -+ return ret; -+ -+ rd_len = msg->u.buffer_from_host.buffer_header.length; -+ -+ /* take buffer from queue */ -+ spin_lock_irqsave(&msg_context->u.bulk.port->slock, flags); -+ if (list_empty(&msg_context->u.bulk.port->buffers)) { -+ spin_unlock_irqrestore(&msg_context->u.bulk.port->slock, flags); -+ pr_err("buffer list empty trying to submit bulk receive\n"); -+ -+ /* todo: this is a serious error, we should never have -+ * commited a buffer_to_host operation to the mmal -+ * port without the buffer to back it up (underflow -+ * handling) and there is no obvious way to deal with -+ * this - how is the mmal servie going to react when -+ * we fail to do the xfer and reschedule a buffer when -+ * it arrives? perhaps a starved flag to indicate a -+ * waiting bulk receive? -+ */ -+ -+ mutex_unlock(&instance->bulk_mutex); -+ -+ return -EINVAL; -+ } -+ -+ msg_context->u.bulk.buffer = -+ list_entry(msg_context->u.bulk.port->buffers.next, -+ struct mmal_buffer, list); -+ list_del(&msg_context->u.bulk.buffer->list); -+ -+ spin_unlock_irqrestore(&msg_context->u.bulk.port->slock, flags); -+ -+ /* ensure we do not overrun the available buffer */ -+ if (rd_len > msg_context->u.bulk.buffer->buffer_size) { -+ rd_len = msg_context->u.bulk.buffer->buffer_size; -+ pr_warn("short read as not enough receive buffer space\n"); -+ /* todo: is this the correct response, what happens to -+ * the rest of the message data? -+ */ -+ } -+ -+ /* store length */ -+ msg_context->u.bulk.buffer_used = rd_len; -+ msg_context->u.bulk.mmal_flags = -+ msg->u.buffer_from_host.buffer_header.flags; -+ msg_context->u.bulk.dts = msg->u.buffer_from_host.buffer_header.dts; -+ msg_context->u.bulk.pts = msg->u.buffer_from_host.buffer_header.pts; -+ -+ // only need to flush L1 cache here, as VCHIQ takes care of the L2 -+ // cache. -+ __cpuc_flush_dcache_area(msg_context->u.bulk.buffer->buffer, rd_len); -+ -+ /* queue the bulk submission */ -+ vchi_service_use(instance->handle); -+ ret = vchi_bulk_queue_receive(instance->handle, -+ msg_context->u.bulk.buffer->buffer, -+ /* Actual receive needs to be a multiple -+ * of 4 bytes -+ */ -+ (rd_len + 3) & ~3, -+ VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE | -+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, -+ msg_context); -+ -+ vchi_service_release(instance->handle); -+ -+ if (ret != 0) { -+ /* callback will not be clearing the mutex */ -+ mutex_unlock(&instance->bulk_mutex); -+ } -+ -+ return ret; -+} -+ -+/* enque a dummy bulk receive for a given message context */ -+static int dummy_bulk_receive(struct vchiq_mmal_instance *instance, -+ struct mmal_msg_context *msg_context) -+{ -+ int ret; -+ -+ /* bulk mutex stops other bulk operations while we have a -+ * receive in progress - released in callback -+ */ -+ ret = mutex_lock_interruptible(&instance->bulk_mutex); -+ if (ret != 0) -+ return ret; -+ -+ /* zero length indicates this was a dummy transfer */ -+ msg_context->u.bulk.buffer_used = 0; -+ -+ /* queue the bulk submission */ -+ vchi_service_use(instance->handle); -+ -+ ret = vchi_bulk_queue_receive(instance->handle, -+ instance->bulk_scratch, -+ 8, -+ VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE | -+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, -+ msg_context); -+ -+ vchi_service_release(instance->handle); -+ -+ if (ret != 0) { -+ /* callback will not be clearing the mutex */ -+ mutex_unlock(&instance->bulk_mutex); -+ } -+ -+ return ret; -+} -+ -+/* data in message, memcpy from packet into output buffer */ -+static int inline_receive(struct vchiq_mmal_instance *instance, -+ struct mmal_msg *msg, -+ struct mmal_msg_context *msg_context) -+{ -+ unsigned long flags = 0; -+ -+ /* take buffer from queue */ -+ spin_lock_irqsave(&msg_context->u.bulk.port->slock, flags); -+ if (list_empty(&msg_context->u.bulk.port->buffers)) { -+ spin_unlock_irqrestore(&msg_context->u.bulk.port->slock, flags); -+ pr_err("buffer list empty trying to receive inline\n"); -+ -+ /* todo: this is a serious error, we should never have -+ * commited a buffer_to_host operation to the mmal -+ * port without the buffer to back it up (with -+ * underflow handling) and there is no obvious way to -+ * deal with this. Less bad than the bulk case as we -+ * can just drop this on the floor but...unhelpful -+ */ -+ return -EINVAL; -+ } -+ -+ msg_context->u.bulk.buffer = -+ list_entry(msg_context->u.bulk.port->buffers.next, -+ struct mmal_buffer, list); -+ list_del(&msg_context->u.bulk.buffer->list); -+ -+ spin_unlock_irqrestore(&msg_context->u.bulk.port->slock, flags); -+ -+ memcpy(msg_context->u.bulk.buffer->buffer, -+ msg->u.buffer_from_host.short_data, -+ msg->u.buffer_from_host.payload_in_message); -+ -+ msg_context->u.bulk.buffer_used = -+ msg->u.buffer_from_host.payload_in_message; -+ -+ return 0; -+} -+ -+/* queue the buffer availability with MMAL_MSG_TYPE_BUFFER_FROM_HOST */ -+static int -+buffer_from_host(struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_port *port, struct mmal_buffer *buf) -+{ -+ struct mmal_msg_context *msg_context; -+ struct mmal_msg m; -+ int ret; -+ -+ pr_debug("instance:%p buffer:%p\n", instance->handle, buf); -+ -+ /* bulk mutex stops other bulk operations while we -+ * have a receive in progress -+ */ -+ if (mutex_lock_interruptible(&instance->bulk_mutex)) -+ return -EINTR; -+ -+ /* get context */ -+ msg_context = get_msg_context(instance); -+ if (msg_context == NULL) -+ return -ENOMEM; -+ -+ /* store bulk message context for when data arrives */ -+ msg_context->u.bulk.instance = instance; -+ msg_context->u.bulk.port = port; -+ msg_context->u.bulk.buffer = NULL; /* not valid until bulk xfer */ -+ msg_context->u.bulk.buffer_used = 0; -+ -+ /* initialise work structure ready to schedule callback */ -+ INIT_WORK(&msg_context->u.bulk.work, buffer_work_cb); -+ -+ /* prep the buffer from host message */ -+ memset(&m, 0xbc, sizeof(m)); /* just to make debug clearer */ -+ -+ m.h.type = MMAL_MSG_TYPE_BUFFER_FROM_HOST; -+ m.h.magic = MMAL_MAGIC; -+ m.h.context = msg_context; -+ m.h.status = 0; -+ -+ /* drvbuf is our private data passed back */ -+ m.u.buffer_from_host.drvbuf.magic = MMAL_MAGIC; -+ m.u.buffer_from_host.drvbuf.component_handle = port->component->handle; -+ m.u.buffer_from_host.drvbuf.port_handle = port->handle; -+ m.u.buffer_from_host.drvbuf.client_context = msg_context; -+ -+ /* buffer header */ -+ m.u.buffer_from_host.buffer_header.cmd = 0; -+ m.u.buffer_from_host.buffer_header.data = buf->buffer; -+ m.u.buffer_from_host.buffer_header.alloc_size = buf->buffer_size; -+ m.u.buffer_from_host.buffer_header.length = 0; /* nothing used yet */ -+ m.u.buffer_from_host.buffer_header.offset = 0; /* no offset */ -+ m.u.buffer_from_host.buffer_header.flags = 0; /* no flags */ -+ m.u.buffer_from_host.buffer_header.pts = MMAL_TIME_UNKNOWN; -+ m.u.buffer_from_host.buffer_header.dts = MMAL_TIME_UNKNOWN; -+ -+ /* clear buffer type sepecific data */ -+ memset(&m.u.buffer_from_host.buffer_header_type_specific, 0, -+ sizeof(m.u.buffer_from_host.buffer_header_type_specific)); -+ -+ /* no payload in message */ -+ m.u.buffer_from_host.payload_in_message = 0; -+ -+ vchi_service_use(instance->handle); -+ -+ ret = vchi_msg_queue(instance->handle, &m, -+ sizeof(struct mmal_msg_header) + -+ sizeof(m.u.buffer_from_host), -+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); -+ -+ if (ret != 0) { -+ release_msg_context(msg_context); -+ /* todo: is this correct error value? */ -+ } -+ -+ vchi_service_release(instance->handle); -+ -+ mutex_unlock(&instance->bulk_mutex); -+ -+ return ret; -+} -+ -+/* submit a buffer to the mmal sevice -+ * -+ * the buffer_from_host uses size data from the ports next available -+ * mmal_buffer and deals with there being no buffer available by -+ * incrementing the underflow for later -+ */ -+static int port_buffer_from_host(struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_port *port) -+{ -+ int ret; -+ struct mmal_buffer *buf; -+ unsigned long flags = 0; -+ -+ if (!port->enabled) -+ return -EINVAL; -+ -+ /* peek buffer from queue */ -+ spin_lock_irqsave(&port->slock, flags); -+ if (list_empty(&port->buffers)) { -+ port->buffer_underflow++; -+ spin_unlock_irqrestore(&port->slock, flags); -+ return -ENOSPC; -+ } -+ -+ buf = list_entry(port->buffers.next, struct mmal_buffer, list); -+ -+ spin_unlock_irqrestore(&port->slock, flags); -+ -+ /* issue buffer to mmal service */ -+ ret = buffer_from_host(instance, port, buf); -+ if (ret) { -+ pr_err("adding buffer header failed\n"); -+ /* todo: how should this be dealt with */ -+ } -+ -+ return ret; -+} -+ -+/* deals with receipt of buffer to host message */ -+static void buffer_to_host_cb(struct vchiq_mmal_instance *instance, -+ struct mmal_msg *msg, u32 msg_len) -+{ -+ struct mmal_msg_context *msg_context; -+ -+ pr_debug("buffer_to_host_cb: instance:%p msg:%p msg_len:%d\n", -+ instance, msg, msg_len); -+ -+ if (msg->u.buffer_from_host.drvbuf.magic == MMAL_MAGIC) { -+ msg_context = msg->u.buffer_from_host.drvbuf.client_context; -+ } else { -+ pr_err("MMAL_MSG_TYPE_BUFFER_TO_HOST with bad magic\n"); -+ return; -+ } -+ -+ if (msg->h.status != MMAL_MSG_STATUS_SUCCESS) { -+ /* message reception had an error */ -+ pr_warn("error %d in reply\n", msg->h.status); -+ -+ msg_context->u.bulk.status = msg->h.status; -+ -+ } else if (msg->u.buffer_from_host.buffer_header.length == 0) { -+ /* empty buffer */ -+ if (msg->u.buffer_from_host.buffer_header.flags & -+ MMAL_BUFFER_HEADER_FLAG_EOS) { -+ msg_context->u.bulk.status = -+ dummy_bulk_receive(instance, msg_context); -+ if (msg_context->u.bulk.status == 0) -+ return; /* successful bulk submission, bulk -+ * completion will trigger callback -+ */ -+ } else { -+ /* do callback with empty buffer - not EOS though */ -+ msg_context->u.bulk.status = 0; -+ msg_context->u.bulk.buffer_used = 0; -+ } -+ } else if (msg->u.buffer_from_host.payload_in_message == 0) { -+ /* data is not in message, queue a bulk receive */ -+ msg_context->u.bulk.status = -+ bulk_receive(instance, msg, msg_context); -+ if (msg_context->u.bulk.status == 0) -+ return; /* successful bulk submission, bulk -+ * completion will trigger callback -+ */ -+ -+ /* failed to submit buffer, this will end badly */ -+ pr_err("error %d on bulk submission\n", -+ msg_context->u.bulk.status); -+ -+ } else if (msg->u.buffer_from_host.payload_in_message <= -+ MMAL_VC_SHORT_DATA) { -+ /* data payload within message */ -+ msg_context->u.bulk.status = inline_receive(instance, msg, -+ msg_context); -+ } else { -+ pr_err("message with invalid short payload\n"); -+ -+ /* signal error */ -+ msg_context->u.bulk.status = -EINVAL; -+ msg_context->u.bulk.buffer_used = -+ msg->u.buffer_from_host.payload_in_message; -+ } -+ -+ /* replace the buffer header */ -+ port_buffer_from_host(instance, msg_context->u.bulk.port); -+ -+ /* schedule the port callback */ -+ schedule_work(&msg_context->u.bulk.work); -+} -+ -+static void bulk_receive_cb(struct vchiq_mmal_instance *instance, -+ struct mmal_msg_context *msg_context) -+{ -+ /* bulk receive operation complete */ -+ mutex_unlock(&msg_context->u.bulk.instance->bulk_mutex); -+ -+ /* replace the buffer header */ -+ port_buffer_from_host(msg_context->u.bulk.instance, -+ msg_context->u.bulk.port); -+ -+ msg_context->u.bulk.status = 0; -+ -+ /* schedule the port callback */ -+ schedule_work(&msg_context->u.bulk.work); -+} -+ -+static void bulk_abort_cb(struct vchiq_mmal_instance *instance, -+ struct mmal_msg_context *msg_context) -+{ -+ pr_err("%s: bulk ABORTED msg_context:%p\n", __func__, msg_context); -+ -+ /* bulk receive operation complete */ -+ mutex_unlock(&msg_context->u.bulk.instance->bulk_mutex); -+ -+ /* replace the buffer header */ -+ port_buffer_from_host(msg_context->u.bulk.instance, -+ msg_context->u.bulk.port); -+ -+ msg_context->u.bulk.status = -EINTR; -+ -+ schedule_work(&msg_context->u.bulk.work); -+} -+ -+/* incoming event service callback */ -+static void service_callback(void *param, -+ const VCHI_CALLBACK_REASON_T reason, -+ void *bulk_ctx) -+{ -+ struct vchiq_mmal_instance *instance = param; -+ int status; -+ u32 msg_len; -+ struct mmal_msg *msg; -+ VCHI_HELD_MSG_T msg_handle; -+ -+ if (!instance) { -+ pr_err("Message callback passed NULL instance\n"); -+ return; -+ } -+ -+ switch (reason) { -+ case VCHI_CALLBACK_MSG_AVAILABLE: -+ status = vchi_msg_hold(instance->handle, (void **)&msg, -+ &msg_len, VCHI_FLAGS_NONE, &msg_handle); -+ if (status) { -+ pr_err("Unable to dequeue a message (%d)\n", status); -+ break; -+ } -+ -+ DBG_DUMP_MSG(msg, msg_len, "<<< reply message"); -+ -+ /* handling is different for buffer messages */ -+ switch (msg->h.type) { -+ -+ case MMAL_MSG_TYPE_BUFFER_FROM_HOST: -+ vchi_held_msg_release(&msg_handle); -+ break; -+ -+ case MMAL_MSG_TYPE_EVENT_TO_HOST: -+ event_to_host_cb(instance, msg, msg_len); -+ vchi_held_msg_release(&msg_handle); -+ -+ break; -+ -+ case MMAL_MSG_TYPE_BUFFER_TO_HOST: -+ buffer_to_host_cb(instance, msg, msg_len); -+ vchi_held_msg_release(&msg_handle); -+ break; -+ -+ default: -+ /* messages dependant on header context to complete */ -+ -+ /* todo: the msg.context really ought to be sanity -+ * checked before we just use it, afaict it comes back -+ * and is used raw from the videocore. Perhaps it -+ * should be verified the address lies in the kernel -+ * address space. -+ */ -+ if (msg->h.context == NULL) { -+ pr_err("received message context was null!\n"); -+ vchi_held_msg_release(&msg_handle); -+ break; -+ } -+ -+ /* fill in context values */ -+ msg->h.context->u.sync.msg_handle = msg_handle; -+ msg->h.context->u.sync.msg = msg; -+ msg->h.context->u.sync.msg_len = msg_len; -+ -+ /* todo: should this check (completion_done() -+ * == 1) for no one waiting? or do we need a -+ * flag to tell us the completion has been -+ * interrupted so we can free the message and -+ * its context. This probably also solves the -+ * message arriving after interruption todo -+ * below -+ */ -+ -+ /* complete message so caller knows it happened */ -+ complete(&msg->h.context->u.sync.cmplt); -+ break; -+ } -+ -+ break; -+ -+ case VCHI_CALLBACK_BULK_RECEIVED: -+ bulk_receive_cb(instance, bulk_ctx); -+ break; -+ -+ case VCHI_CALLBACK_BULK_RECEIVE_ABORTED: -+ bulk_abort_cb(instance, bulk_ctx); -+ break; -+ -+ case VCHI_CALLBACK_SERVICE_CLOSED: -+ /* TODO: consider if this requires action if received when -+ * driver is not explicitly closing the service -+ */ -+ break; -+ -+ default: -+ pr_err("Received unhandled message reason %d\n", reason); -+ break; -+ } -+} -+ -+static int send_synchronous_mmal_msg(struct vchiq_mmal_instance *instance, -+ struct mmal_msg *msg, -+ unsigned int payload_len, -+ struct mmal_msg **msg_out, -+ VCHI_HELD_MSG_T *msg_handle_out) -+{ -+ struct mmal_msg_context msg_context; -+ int ret; -+ -+ /* payload size must not cause message to exceed max size */ -+ if (payload_len > -+ (MMAL_MSG_MAX_SIZE - sizeof(struct mmal_msg_header))) { -+ pr_err("payload length %d exceeds max:%d\n", payload_len, -+ (MMAL_MSG_MAX_SIZE - sizeof(struct mmal_msg_header))); -+ return -EINVAL; -+ } -+ -+ init_completion(&msg_context.u.sync.cmplt); -+ -+ msg->h.magic = MMAL_MAGIC; -+ msg->h.context = &msg_context; -+ msg->h.status = 0; -+ -+ DBG_DUMP_MSG(msg, (sizeof(struct mmal_msg_header) + payload_len), -+ ">>> sync message"); -+ -+ vchi_service_use(instance->handle); -+ -+ ret = vchi_msg_queue(instance->handle, -+ msg, -+ sizeof(struct mmal_msg_header) + payload_len, -+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); -+ -+ vchi_service_release(instance->handle); -+ -+ if (ret) { -+ pr_err("error %d queuing message\n", ret); -+ return ret; -+ } -+ -+ ret = wait_for_completion_timeout(&msg_context.u.sync.cmplt, 3*HZ); -+ if (ret <= 0) { -+ pr_err("error %d waiting for sync completion\n", ret); -+ if (ret == 0) -+ ret = -ETIME; -+ /* todo: what happens if the message arrives after aborting */ -+ return ret; -+ } -+ -+ *msg_out = msg_context.u.sync.msg; -+ *msg_handle_out = msg_context.u.sync.msg_handle; -+ -+ return 0; -+} -+ -+static void dump_port_info(struct vchiq_mmal_port *port) -+{ -+ pr_debug("port handle:0x%x enabled:%d\n", port->handle, port->enabled); -+ -+ pr_debug("buffer minimum num:%d size:%d align:%d\n", -+ port->minimum_buffer.num, -+ port->minimum_buffer.size, port->minimum_buffer.alignment); -+ -+ pr_debug("buffer recommended num:%d size:%d align:%d\n", -+ port->recommended_buffer.num, -+ port->recommended_buffer.size, -+ port->recommended_buffer.alignment); -+ -+ pr_debug("buffer current values num:%d size:%d align:%d\n", -+ port->current_buffer.num, -+ port->current_buffer.size, port->current_buffer.alignment); -+ -+ pr_debug("elementry stream: type:%d encoding:0x%x varient:0x%x\n", -+ port->format.type, -+ port->format.encoding, port->format.encoding_variant); -+ -+ pr_debug(" bitrate:%d flags:0x%x\n", -+ port->format.bitrate, port->format.flags); -+ -+ if (port->format.type == MMAL_ES_TYPE_VIDEO) { -+ pr_debug -+ ("es video format: width:%d height:%d colourspace:0x%x\n", -+ port->es.video.width, port->es.video.height, -+ port->es.video.color_space); -+ -+ pr_debug(" : crop xywh %d,%d,%d,%d\n", -+ port->es.video.crop.x, -+ port->es.video.crop.y, -+ port->es.video.crop.width, port->es.video.crop.height); -+ pr_debug(" : framerate %d/%d aspect %d/%d\n", -+ port->es.video.frame_rate.num, -+ port->es.video.frame_rate.den, -+ port->es.video.par.num, port->es.video.par.den); -+ } -+} -+ -+static void port_to_mmal_msg(struct vchiq_mmal_port *port, struct mmal_port *p) -+{ -+ -+ /* todo do readonly fields need setting at all? */ -+ p->type = port->type; -+ p->index = port->index; -+ p->index_all = 0; -+ p->is_enabled = port->enabled; -+ p->buffer_num_min = port->minimum_buffer.num; -+ p->buffer_size_min = port->minimum_buffer.size; -+ p->buffer_alignment_min = port->minimum_buffer.alignment; -+ p->buffer_num_recommended = port->recommended_buffer.num; -+ p->buffer_size_recommended = port->recommended_buffer.size; -+ -+ /* only three writable fields in a port */ -+ p->buffer_num = port->current_buffer.num; -+ p->buffer_size = port->current_buffer.size; -+ p->userdata = port; -+} -+ -+static int port_info_set(struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_port *port) -+{ -+ int ret; -+ struct mmal_msg m; -+ struct mmal_msg *rmsg; -+ VCHI_HELD_MSG_T rmsg_handle; -+ -+ pr_debug("setting port info port %p\n", port); -+ if (!port) -+ return -1; -+ dump_port_info(port); -+ -+ m.h.type = MMAL_MSG_TYPE_PORT_INFO_SET; -+ -+ m.u.port_info_set.component_handle = port->component->handle; -+ m.u.port_info_set.port_type = port->type; -+ m.u.port_info_set.port_index = port->index; -+ -+ port_to_mmal_msg(port, &m.u.port_info_set.port); -+ -+ /* elementry stream format setup */ -+ m.u.port_info_set.format.type = port->format.type; -+ m.u.port_info_set.format.encoding = port->format.encoding; -+ m.u.port_info_set.format.encoding_variant = -+ port->format.encoding_variant; -+ m.u.port_info_set.format.bitrate = port->format.bitrate; -+ m.u.port_info_set.format.flags = port->format.flags; -+ -+ memcpy(&m.u.port_info_set.es, &port->es, -+ sizeof(union mmal_es_specific_format)); -+ -+ m.u.port_info_set.format.extradata_size = port->format.extradata_size; -+ memcpy(&m.u.port_info_set.extradata, port->format.extradata, -+ port->format.extradata_size); -+ -+ ret = send_synchronous_mmal_msg(instance, &m, -+ sizeof(m.u.port_info_set), -+ &rmsg, &rmsg_handle); -+ if (ret) -+ return ret; -+ -+ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_INFO_SET) { -+ /* got an unexpected message type in reply */ -+ ret = -EINVAL; -+ goto release_msg; -+ } -+ -+ /* return operation status */ -+ ret = -rmsg->u.port_info_get_reply.status; -+ -+ pr_debug("%s:result:%d component:0x%x port:%d\n", __func__, ret, -+ port->component->handle, port->handle); -+ -+release_msg: -+ vchi_held_msg_release(&rmsg_handle); -+ -+ return ret; -+ -+} -+ -+/* use port info get message to retrive port information */ -+static int port_info_get(struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_port *port) -+{ -+ int ret; -+ struct mmal_msg m; -+ struct mmal_msg *rmsg; -+ VCHI_HELD_MSG_T rmsg_handle; -+ -+ /* port info time */ -+ m.h.type = MMAL_MSG_TYPE_PORT_INFO_GET; -+ m.u.port_info_get.component_handle = port->component->handle; -+ m.u.port_info_get.port_type = port->type; -+ m.u.port_info_get.index = port->index; -+ -+ ret = send_synchronous_mmal_msg(instance, &m, -+ sizeof(m.u.port_info_get), -+ &rmsg, &rmsg_handle); -+ if (ret) -+ return ret; -+ -+ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_INFO_GET) { -+ /* got an unexpected message type in reply */ -+ ret = -EINVAL; -+ goto release_msg; -+ } -+ -+ /* return operation status */ -+ ret = -rmsg->u.port_info_get_reply.status; -+ if (ret != MMAL_MSG_STATUS_SUCCESS) -+ goto release_msg; -+ -+ if (rmsg->u.port_info_get_reply.port.is_enabled == 0) -+ port->enabled = false; -+ else -+ port->enabled = true; -+ -+ /* copy the values out of the message */ -+ port->handle = rmsg->u.port_info_get_reply.port_handle; -+ -+ /* port type and index cached to use on port info set becuase -+ * it does not use a port handle -+ */ -+ port->type = rmsg->u.port_info_get_reply.port_type; -+ port->index = rmsg->u.port_info_get_reply.port_index; -+ -+ port->minimum_buffer.num = -+ rmsg->u.port_info_get_reply.port.buffer_num_min; -+ port->minimum_buffer.size = -+ rmsg->u.port_info_get_reply.port.buffer_size_min; -+ port->minimum_buffer.alignment = -+ rmsg->u.port_info_get_reply.port.buffer_alignment_min; -+ -+ port->recommended_buffer.alignment = -+ rmsg->u.port_info_get_reply.port.buffer_alignment_min; -+ port->recommended_buffer.num = -+ rmsg->u.port_info_get_reply.port.buffer_num_recommended; -+ -+ port->current_buffer.num = rmsg->u.port_info_get_reply.port.buffer_num; -+ port->current_buffer.size = -+ rmsg->u.port_info_get_reply.port.buffer_size; -+ -+ /* stream format */ -+ port->format.type = rmsg->u.port_info_get_reply.format.type; -+ port->format.encoding = rmsg->u.port_info_get_reply.format.encoding; -+ port->format.encoding_variant = -+ rmsg->u.port_info_get_reply.format.encoding_variant; -+ port->format.bitrate = rmsg->u.port_info_get_reply.format.bitrate; -+ port->format.flags = rmsg->u.port_info_get_reply.format.flags; -+ -+ /* elementry stream format */ -+ memcpy(&port->es, -+ &rmsg->u.port_info_get_reply.es, -+ sizeof(union mmal_es_specific_format)); -+ port->format.es = &port->es; -+ -+ port->format.extradata_size = -+ rmsg->u.port_info_get_reply.format.extradata_size; -+ memcpy(port->format.extradata, -+ rmsg->u.port_info_get_reply.extradata, -+ port->format.extradata_size); -+ -+ pr_debug("received port info\n"); -+ dump_port_info(port); -+ -+release_msg: -+ -+ pr_debug("%s:result:%d component:0x%x port:%d\n", -+ __func__, ret, port->component->handle, port->handle); -+ -+ vchi_held_msg_release(&rmsg_handle); -+ -+ return ret; -+} -+ -+/* create comonent on vc */ -+static int create_component(struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_component *component, -+ const char *name) -+{ -+ int ret; -+ struct mmal_msg m; -+ struct mmal_msg *rmsg; -+ VCHI_HELD_MSG_T rmsg_handle; -+ -+ /* build component create message */ -+ m.h.type = MMAL_MSG_TYPE_COMPONENT_CREATE; -+ m.u.component_create.client_component = component; -+ strncpy(m.u.component_create.name, name, -+ sizeof(m.u.component_create.name)); -+ -+ ret = send_synchronous_mmal_msg(instance, &m, -+ sizeof(m.u.component_create), -+ &rmsg, &rmsg_handle); -+ if (ret) -+ return ret; -+ -+ if (rmsg->h.type != m.h.type) { -+ /* got an unexpected message type in reply */ -+ ret = -EINVAL; -+ goto release_msg; -+ } -+ -+ ret = -rmsg->u.component_create_reply.status; -+ if (ret != MMAL_MSG_STATUS_SUCCESS) -+ goto release_msg; -+ -+ /* a valid component response received */ -+ component->handle = rmsg->u.component_create_reply.component_handle; -+ component->inputs = rmsg->u.component_create_reply.input_num; -+ component->outputs = rmsg->u.component_create_reply.output_num; -+ component->clocks = rmsg->u.component_create_reply.clock_num; -+ -+ pr_debug("Component handle:0x%x in:%d out:%d clock:%d\n", -+ component->handle, -+ component->inputs, component->outputs, component->clocks); -+ -+release_msg: -+ vchi_held_msg_release(&rmsg_handle); -+ -+ return ret; -+} -+ -+/* destroys a component on vc */ -+static int destroy_component(struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_component *component) -+{ -+ int ret; -+ struct mmal_msg m; -+ struct mmal_msg *rmsg; -+ VCHI_HELD_MSG_T rmsg_handle; -+ -+ m.h.type = MMAL_MSG_TYPE_COMPONENT_DESTROY; -+ m.u.component_destroy.component_handle = component->handle; -+ -+ ret = send_synchronous_mmal_msg(instance, &m, -+ sizeof(m.u.component_destroy), -+ &rmsg, &rmsg_handle); -+ if (ret) -+ return ret; -+ -+ if (rmsg->h.type != m.h.type) { -+ /* got an unexpected message type in reply */ -+ ret = -EINVAL; -+ goto release_msg; -+ } -+ -+ ret = -rmsg->u.component_destroy_reply.status; -+ -+release_msg: -+ -+ vchi_held_msg_release(&rmsg_handle); -+ -+ return ret; -+} -+ -+/* enable a component on vc */ -+static int enable_component(struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_component *component) -+{ -+ int ret; -+ struct mmal_msg m; -+ struct mmal_msg *rmsg; -+ VCHI_HELD_MSG_T rmsg_handle; -+ -+ m.h.type = MMAL_MSG_TYPE_COMPONENT_ENABLE; -+ m.u.component_enable.component_handle = component->handle; -+ -+ ret = send_synchronous_mmal_msg(instance, &m, -+ sizeof(m.u.component_enable), -+ &rmsg, &rmsg_handle); -+ if (ret) -+ return ret; -+ -+ if (rmsg->h.type != m.h.type) { -+ /* got an unexpected message type in reply */ -+ ret = -EINVAL; -+ goto release_msg; -+ } -+ -+ ret = -rmsg->u.component_enable_reply.status; -+ -+release_msg: -+ vchi_held_msg_release(&rmsg_handle); -+ -+ return ret; -+} -+ -+/* disable a component on vc */ -+static int disable_component(struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_component *component) -+{ -+ int ret; -+ struct mmal_msg m; -+ struct mmal_msg *rmsg; -+ VCHI_HELD_MSG_T rmsg_handle; -+ -+ m.h.type = MMAL_MSG_TYPE_COMPONENT_DISABLE; -+ m.u.component_disable.component_handle = component->handle; -+ -+ ret = send_synchronous_mmal_msg(instance, &m, -+ sizeof(m.u.component_disable), -+ &rmsg, &rmsg_handle); -+ if (ret) -+ return ret; -+ -+ if (rmsg->h.type != m.h.type) { -+ /* got an unexpected message type in reply */ -+ ret = -EINVAL; -+ goto release_msg; -+ } -+ -+ ret = -rmsg->u.component_disable_reply.status; -+ -+release_msg: -+ -+ vchi_held_msg_release(&rmsg_handle); -+ -+ return ret; -+} -+ -+/* get version of mmal implementation */ -+static int get_version(struct vchiq_mmal_instance *instance, -+ u32 *major_out, u32 *minor_out) -+{ -+ int ret; -+ struct mmal_msg m; -+ struct mmal_msg *rmsg; -+ VCHI_HELD_MSG_T rmsg_handle; -+ -+ m.h.type = MMAL_MSG_TYPE_GET_VERSION; -+ -+ ret = send_synchronous_mmal_msg(instance, &m, -+ sizeof(m.u.version), -+ &rmsg, &rmsg_handle); -+ if (ret) -+ return ret; -+ -+ if (rmsg->h.type != m.h.type) { -+ /* got an unexpected message type in reply */ -+ ret = -EINVAL; -+ goto release_msg; -+ } -+ -+ *major_out = rmsg->u.version.major; -+ *minor_out = rmsg->u.version.minor; -+ -+release_msg: -+ vchi_held_msg_release(&rmsg_handle); -+ -+ return ret; -+} -+ -+/* do a port action with a port as a parameter */ -+static int port_action_port(struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_port *port, -+ enum mmal_msg_port_action_type action_type) -+{ -+ int ret; -+ struct mmal_msg m; -+ struct mmal_msg *rmsg; -+ VCHI_HELD_MSG_T rmsg_handle; -+ -+ m.h.type = MMAL_MSG_TYPE_PORT_ACTION; -+ m.u.port_action_port.component_handle = port->component->handle; -+ m.u.port_action_port.port_handle = port->handle; -+ m.u.port_action_port.action = action_type; -+ -+ port_to_mmal_msg(port, &m.u.port_action_port.port); -+ -+ ret = send_synchronous_mmal_msg(instance, &m, -+ sizeof(m.u.port_action_port), -+ &rmsg, &rmsg_handle); -+ if (ret) -+ return ret; -+ -+ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_ACTION) { -+ /* got an unexpected message type in reply */ -+ ret = -EINVAL; -+ goto release_msg; -+ } -+ -+ ret = -rmsg->u.port_action_reply.status; -+ -+ pr_debug("%s:result:%d component:0x%x port:%d action:%s(%d)\n", -+ __func__, -+ ret, port->component->handle, port->handle, -+ port_action_type_names[action_type], action_type); -+ -+release_msg: -+ vchi_held_msg_release(&rmsg_handle); -+ -+ return ret; -+} -+ -+/* do a port action with handles as parameters */ -+static int port_action_handle(struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_port *port, -+ enum mmal_msg_port_action_type action_type, -+ u32 connect_component_handle, -+ u32 connect_port_handle) -+{ -+ int ret; -+ struct mmal_msg m; -+ struct mmal_msg *rmsg; -+ VCHI_HELD_MSG_T rmsg_handle; -+ -+ m.h.type = MMAL_MSG_TYPE_PORT_ACTION; -+ -+ m.u.port_action_handle.component_handle = port->component->handle; -+ m.u.port_action_handle.port_handle = port->handle; -+ m.u.port_action_handle.action = action_type; -+ -+ m.u.port_action_handle.connect_component_handle = -+ connect_component_handle; -+ m.u.port_action_handle.connect_port_handle = connect_port_handle; -+ -+ ret = send_synchronous_mmal_msg(instance, &m, -+ sizeof(m.u.port_action_handle), -+ &rmsg, &rmsg_handle); -+ if (ret) -+ return ret; -+ -+ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_ACTION) { -+ /* got an unexpected message type in reply */ -+ ret = -EINVAL; -+ goto release_msg; -+ } -+ -+ ret = -rmsg->u.port_action_reply.status; -+ -+ pr_debug("%s:result:%d component:0x%x port:%d action:%s(%d)" \ -+ " connect component:0x%x connect port:%d\n", -+ __func__, -+ ret, port->component->handle, port->handle, -+ port_action_type_names[action_type], -+ action_type, connect_component_handle, connect_port_handle); -+ -+release_msg: -+ vchi_held_msg_release(&rmsg_handle); -+ -+ return ret; -+} -+ -+static int port_parameter_set(struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_port *port, -+ u32 parameter_id, void *value, u32 value_size) -+{ -+ int ret; -+ struct mmal_msg m; -+ struct mmal_msg *rmsg; -+ VCHI_HELD_MSG_T rmsg_handle; -+ -+ m.h.type = MMAL_MSG_TYPE_PORT_PARAMETER_SET; -+ -+ m.u.port_parameter_set.component_handle = port->component->handle; -+ m.u.port_parameter_set.port_handle = port->handle; -+ m.u.port_parameter_set.id = parameter_id; -+ m.u.port_parameter_set.size = (2 * sizeof(u32)) + value_size; -+ memcpy(&m.u.port_parameter_set.value, value, value_size); -+ -+ ret = send_synchronous_mmal_msg(instance, &m, -+ (4 * sizeof(u32)) + value_size, -+ &rmsg, &rmsg_handle); -+ if (ret) -+ return ret; -+ -+ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_PARAMETER_SET) { -+ /* got an unexpected message type in reply */ -+ ret = -EINVAL; -+ goto release_msg; -+ } -+ -+ ret = -rmsg->u.port_parameter_set_reply.status; -+ -+ pr_debug("%s:result:%d component:0x%x port:%d parameter:%d\n", -+ __func__, -+ ret, port->component->handle, port->handle, parameter_id); -+ -+release_msg: -+ vchi_held_msg_release(&rmsg_handle); -+ -+ return ret; -+} -+ -+static int port_parameter_get(struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_port *port, -+ u32 parameter_id, void *value, u32 *value_size) -+{ -+ int ret; -+ struct mmal_msg m; -+ struct mmal_msg *rmsg; -+ VCHI_HELD_MSG_T rmsg_handle; -+ -+ m.h.type = MMAL_MSG_TYPE_PORT_PARAMETER_GET; -+ -+ m.u.port_parameter_get.component_handle = port->component->handle; -+ m.u.port_parameter_get.port_handle = port->handle; -+ m.u.port_parameter_get.id = parameter_id; -+ m.u.port_parameter_get.size = (2 * sizeof(u32)) + *value_size; -+ -+ ret = send_synchronous_mmal_msg(instance, &m, -+ sizeof(struct -+ mmal_msg_port_parameter_get), -+ &rmsg, &rmsg_handle); -+ if (ret) -+ return ret; -+ -+ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_PARAMETER_GET) { -+ /* got an unexpected message type in reply */ -+ pr_err("Incorrect reply type %d\n", rmsg->h.type); -+ ret = -EINVAL; -+ goto release_msg; -+ } -+ -+ ret = -rmsg->u.port_parameter_get_reply.status; -+ if (ret) { -+ /* Copy only as much as we have space for -+ * but report true size of parameter -+ */ -+ memcpy(value, &rmsg->u.port_parameter_get_reply.value, -+ *value_size); -+ *value_size = rmsg->u.port_parameter_get_reply.size; -+ } else -+ memcpy(value, &rmsg->u.port_parameter_get_reply.value, -+ rmsg->u.port_parameter_get_reply.size); -+ -+ pr_debug("%s:result:%d component:0x%x port:%d parameter:%d\n", __func__, -+ ret, port->component->handle, port->handle, parameter_id); -+ -+release_msg: -+ vchi_held_msg_release(&rmsg_handle); -+ -+ return ret; -+} -+ -+/* disables a port and drains buffers from it */ -+static int port_disable(struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_port *port) -+{ -+ int ret; -+ struct list_head *q, *buf_head; -+ unsigned long flags = 0; -+ -+ if (!port->enabled) -+ return 0; -+ -+ port->enabled = false; -+ -+ ret = port_action_port(instance, port, -+ MMAL_MSG_PORT_ACTION_TYPE_DISABLE); -+ if (ret == 0) { -+ -+ /* drain all queued buffers on port */ -+ spin_lock_irqsave(&port->slock, flags); -+ -+ list_for_each_safe(buf_head, q, &port->buffers) { -+ struct mmal_buffer *mmalbuf; -+ mmalbuf = list_entry(buf_head, struct mmal_buffer, -+ list); -+ list_del(buf_head); -+ if (port->buffer_cb) -+ port->buffer_cb(instance, -+ port, 0, mmalbuf, 0, 0, -+ MMAL_TIME_UNKNOWN, -+ MMAL_TIME_UNKNOWN); -+ } -+ -+ spin_unlock_irqrestore(&port->slock, flags); -+ -+ ret = port_info_get(instance, port); -+ } -+ -+ return ret; -+} -+ -+/* enable a port */ -+static int port_enable(struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_port *port) -+{ -+ unsigned int hdr_count; -+ struct list_head *buf_head; -+ int ret; -+ -+ if (port->enabled) -+ return 0; -+ -+ /* ensure there are enough buffers queued to cover the buffer headers */ -+ if (port->buffer_cb != NULL) { -+ hdr_count = 0; -+ list_for_each(buf_head, &port->buffers) { -+ hdr_count++; -+ } -+ if (hdr_count < port->current_buffer.num) -+ return -ENOSPC; -+ } -+ -+ ret = port_action_port(instance, port, -+ MMAL_MSG_PORT_ACTION_TYPE_ENABLE); -+ if (ret) -+ goto done; -+ -+ port->enabled = true; -+ -+ if (port->buffer_cb) { -+ /* send buffer headers to videocore */ -+ hdr_count = 1; -+ list_for_each(buf_head, &port->buffers) { -+ struct mmal_buffer *mmalbuf; -+ mmalbuf = list_entry(buf_head, struct mmal_buffer, -+ list); -+ ret = buffer_from_host(instance, port, mmalbuf); -+ if (ret) -+ goto done; -+ -+ hdr_count++; -+ if (hdr_count > port->current_buffer.num) -+ break; -+ } -+ } -+ -+ ret = port_info_get(instance, port); -+ -+done: -+ return ret; -+} -+ -+/* ------------------------------------------------------------------ -+ * Exported API -+ *------------------------------------------------------------------*/ -+ -+int vchiq_mmal_port_set_format(struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_port *port) -+{ -+ int ret; -+ -+ if (mutex_lock_interruptible(&instance->vchiq_mutex)) -+ return -EINTR; -+ -+ ret = port_info_set(instance, port); -+ if (ret) -+ goto release_unlock; -+ -+ /* read what has actually been set */ -+ ret = port_info_get(instance, port); -+ -+release_unlock: -+ mutex_unlock(&instance->vchiq_mutex); -+ -+ return ret; -+ -+} -+ -+int vchiq_mmal_port_parameter_set(struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_port *port, -+ u32 parameter, void *value, u32 value_size) -+{ -+ int ret; -+ -+ if (mutex_lock_interruptible(&instance->vchiq_mutex)) -+ return -EINTR; -+ -+ ret = port_parameter_set(instance, port, parameter, value, value_size); -+ -+ mutex_unlock(&instance->vchiq_mutex); -+ -+ return ret; -+} -+ -+int vchiq_mmal_port_parameter_get(struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_port *port, -+ u32 parameter, void *value, u32 *value_size) -+{ -+ int ret; -+ -+ if (mutex_lock_interruptible(&instance->vchiq_mutex)) -+ return -EINTR; -+ -+ ret = port_parameter_get(instance, port, parameter, value, value_size); -+ -+ mutex_unlock(&instance->vchiq_mutex); -+ -+ return ret; -+} -+ -+/* enable a port -+ * -+ * enables a port and queues buffers for satisfying callbacks if we -+ * provide a callback handler -+ */ -+int vchiq_mmal_port_enable(struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_port *port, -+ vchiq_mmal_buffer_cb buffer_cb) -+{ -+ int ret; -+ -+ if (mutex_lock_interruptible(&instance->vchiq_mutex)) -+ return -EINTR; -+ -+ /* already enabled - noop */ -+ if (port->enabled) { -+ ret = 0; -+ goto unlock; -+ } -+ -+ port->buffer_cb = buffer_cb; -+ -+ ret = port_enable(instance, port); -+ -+unlock: -+ mutex_unlock(&instance->vchiq_mutex); -+ -+ return ret; -+} -+ -+int vchiq_mmal_port_disable(struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_port *port) -+{ -+ int ret; -+ -+ if (mutex_lock_interruptible(&instance->vchiq_mutex)) -+ return -EINTR; -+ -+ if (!port->enabled) { -+ mutex_unlock(&instance->vchiq_mutex); -+ return 0; -+ } -+ -+ ret = port_disable(instance, port); -+ -+ mutex_unlock(&instance->vchiq_mutex); -+ -+ return ret; -+} -+ -+/* ports will be connected in a tunneled manner so data buffers -+ * are not handled by client. -+ */ -+int vchiq_mmal_port_connect_tunnel(struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_port *src, -+ struct vchiq_mmal_port *dst) -+{ -+ int ret; -+ -+ if (mutex_lock_interruptible(&instance->vchiq_mutex)) -+ return -EINTR; -+ -+ /* disconnect ports if connected */ -+ if (src->connected != NULL) { -+ ret = port_disable(instance, src); -+ if (ret) { -+ pr_err("failed disabling src port(%d)\n", ret); -+ goto release_unlock; -+ } -+ -+ /* do not need to disable the destination port as they -+ * are connected and it is done automatically -+ */ -+ -+ ret = port_action_handle(instance, src, -+ MMAL_MSG_PORT_ACTION_TYPE_DISCONNECT, -+ src->connected->component->handle, -+ src->connected->handle); -+ if (ret < 0) { -+ pr_err("failed disconnecting src port\n"); -+ goto release_unlock; -+ } -+ src->connected->enabled = false; -+ src->connected = NULL; -+ } -+ -+ if (dst == NULL) { -+ /* do not make new connection */ -+ ret = 0; -+ pr_debug("not making new connection\n"); -+ goto release_unlock; -+ } -+ -+ /* copy src port format to dst */ -+ dst->format.encoding = src->format.encoding; -+ dst->es.video.width = src->es.video.width; -+ dst->es.video.height = src->es.video.height; -+ dst->es.video.crop.x = src->es.video.crop.x; -+ dst->es.video.crop.y = src->es.video.crop.y; -+ dst->es.video.crop.width = src->es.video.crop.width; -+ dst->es.video.crop.height = src->es.video.crop.height; -+ dst->es.video.frame_rate.num = src->es.video.frame_rate.num; -+ dst->es.video.frame_rate.den = src->es.video.frame_rate.den; -+ -+ /* set new format */ -+ ret = port_info_set(instance, dst); -+ if (ret) { -+ pr_debug("setting port info failed\n"); -+ goto release_unlock; -+ } -+ -+ /* read what has actually been set */ -+ ret = port_info_get(instance, dst); -+ if (ret) { -+ pr_debug("read back port info failed\n"); -+ goto release_unlock; -+ } -+ -+ /* connect two ports together */ -+ ret = port_action_handle(instance, src, -+ MMAL_MSG_PORT_ACTION_TYPE_CONNECT, -+ dst->component->handle, dst->handle); -+ if (ret < 0) { -+ pr_debug("connecting port %d:%d to %d:%d failed\n", -+ src->component->handle, src->handle, -+ dst->component->handle, dst->handle); -+ goto release_unlock; -+ } -+ src->connected = dst; -+ -+release_unlock: -+ -+ mutex_unlock(&instance->vchiq_mutex); -+ -+ return ret; -+} -+ -+int vchiq_mmal_submit_buffer(struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_port *port, -+ struct mmal_buffer *buffer) -+{ -+ unsigned long flags = 0; -+ -+ spin_lock_irqsave(&port->slock, flags); -+ list_add_tail(&buffer->list, &port->buffers); -+ spin_unlock_irqrestore(&port->slock, flags); -+ -+ /* the port previously underflowed because it was missing a -+ * mmal_buffer which has just been added, submit that buffer -+ * to the mmal service. -+ */ -+ if (port->buffer_underflow) { -+ port_buffer_from_host(instance, port); -+ port->buffer_underflow--; -+ } -+ -+ return 0; -+} -+ -+/* Initialise a mmal component and its ports -+ * -+ */ -+int vchiq_mmal_component_init(struct vchiq_mmal_instance *instance, -+ const char *name, -+ struct vchiq_mmal_component **component_out) -+{ -+ int ret; -+ int idx; /* port index */ -+ struct vchiq_mmal_component *component; -+ -+ if (mutex_lock_interruptible(&instance->vchiq_mutex)) -+ return -EINTR; -+ -+ if (instance->component_idx == VCHIQ_MMAL_MAX_COMPONENTS) { -+ ret = -EINVAL; /* todo is this correct error? */ -+ goto unlock; -+ } -+ -+ component = &instance->component[instance->component_idx]; -+ -+ ret = create_component(instance, component, name); -+ if (ret < 0) -+ goto unlock; -+ -+ /* ports info needs gathering */ -+ component->control.type = MMAL_PORT_TYPE_CONTROL; -+ component->control.index = 0; -+ component->control.component = component; -+ spin_lock_init(&component->control.slock); -+ INIT_LIST_HEAD(&component->control.buffers); -+ ret = port_info_get(instance, &component->control); -+ if (ret < 0) -+ goto release_component; -+ -+ for (idx = 0; idx < component->inputs; idx++) { -+ component->input[idx].type = MMAL_PORT_TYPE_INPUT; -+ component->input[idx].index = idx; -+ component->input[idx].component = component; -+ spin_lock_init(&component->input[idx].slock); -+ INIT_LIST_HEAD(&component->input[idx].buffers); -+ ret = port_info_get(instance, &component->input[idx]); -+ if (ret < 0) -+ goto release_component; -+ } -+ -+ for (idx = 0; idx < component->outputs; idx++) { -+ component->output[idx].type = MMAL_PORT_TYPE_OUTPUT; -+ component->output[idx].index = idx; -+ component->output[idx].component = component; -+ spin_lock_init(&component->output[idx].slock); -+ INIT_LIST_HEAD(&component->output[idx].buffers); -+ ret = port_info_get(instance, &component->output[idx]); -+ if (ret < 0) -+ goto release_component; -+ } -+ -+ for (idx = 0; idx < component->clocks; idx++) { -+ component->clock[idx].type = MMAL_PORT_TYPE_CLOCK; -+ component->clock[idx].index = idx; -+ component->clock[idx].component = component; -+ spin_lock_init(&component->clock[idx].slock); -+ INIT_LIST_HEAD(&component->clock[idx].buffers); -+ ret = port_info_get(instance, &component->clock[idx]); -+ if (ret < 0) -+ goto release_component; -+ } -+ -+ instance->component_idx++; -+ -+ *component_out = component; -+ -+ mutex_unlock(&instance->vchiq_mutex); -+ -+ return 0; -+ -+release_component: -+ destroy_component(instance, component); -+unlock: -+ mutex_unlock(&instance->vchiq_mutex); -+ -+ return ret; -+} -+ -+/* -+ * cause a mmal component to be destroyed -+ */ -+int vchiq_mmal_component_finalise(struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_component *component) -+{ -+ int ret; -+ -+ if (mutex_lock_interruptible(&instance->vchiq_mutex)) -+ return -EINTR; -+ -+ if (component->enabled) -+ ret = disable_component(instance, component); -+ -+ ret = destroy_component(instance, component); -+ -+ mutex_unlock(&instance->vchiq_mutex); -+ -+ return ret; -+} -+ -+/* -+ * cause a mmal component to be enabled -+ */ -+int vchiq_mmal_component_enable(struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_component *component) -+{ -+ int ret; -+ -+ if (mutex_lock_interruptible(&instance->vchiq_mutex)) -+ return -EINTR; -+ -+ if (component->enabled) { -+ mutex_unlock(&instance->vchiq_mutex); -+ return 0; -+ } -+ -+ ret = enable_component(instance, component); -+ if (ret == 0) -+ component->enabled = true; -+ -+ mutex_unlock(&instance->vchiq_mutex); -+ -+ return ret; -+} -+ -+/* -+ * cause a mmal component to be enabled -+ */ -+int vchiq_mmal_component_disable(struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_component *component) -+{ -+ int ret; -+ -+ if (mutex_lock_interruptible(&instance->vchiq_mutex)) -+ return -EINTR; -+ -+ if (!component->enabled) { -+ mutex_unlock(&instance->vchiq_mutex); -+ return 0; -+ } -+ -+ ret = disable_component(instance, component); -+ if (ret == 0) -+ component->enabled = false; -+ -+ mutex_unlock(&instance->vchiq_mutex); -+ -+ return ret; -+} -+ -+int vchiq_mmal_version(struct vchiq_mmal_instance *instance, -+ u32 *major_out, u32 *minor_out) -+{ -+ int ret; -+ -+ if (mutex_lock_interruptible(&instance->vchiq_mutex)) -+ return -EINTR; -+ -+ ret = get_version(instance, major_out, minor_out); -+ -+ mutex_unlock(&instance->vchiq_mutex); -+ -+ return ret; -+} -+ -+int vchiq_mmal_finalise(struct vchiq_mmal_instance *instance) -+{ -+ int status = 0; -+ -+ if (instance == NULL) -+ return -EINVAL; -+ -+ if (mutex_lock_interruptible(&instance->vchiq_mutex)) -+ return -EINTR; -+ -+ vchi_service_use(instance->handle); -+ -+ status = vchi_service_close(instance->handle); -+ if (status != 0) -+ pr_err("mmal-vchiq: VCHIQ close failed"); -+ -+ mutex_unlock(&instance->vchiq_mutex); -+ -+ vfree(instance->bulk_scratch); -+ -+ kfree(instance); -+ -+ return status; -+} -+ -+int vchiq_mmal_init(struct vchiq_mmal_instance **out_instance) -+{ -+ int status; -+ struct vchiq_mmal_instance *instance; -+ static VCHI_CONNECTION_T *vchi_connection; -+ static VCHI_INSTANCE_T vchi_instance; -+ SERVICE_CREATION_T params = { -+ VCHI_VERSION_EX(VC_MMAL_VER, VC_MMAL_MIN_VER), -+ VC_MMAL_SERVER_NAME, -+ vchi_connection, -+ 0, /* rx fifo size (unused) */ -+ 0, /* tx fifo size (unused) */ -+ service_callback, -+ NULL, /* service callback parameter */ -+ 1, /* unaligned bulk receives */ -+ 1, /* unaligned bulk transmits */ -+ 0 /* want crc check on bulk transfers */ -+ }; -+ -+ /* compile time checks to ensure structure size as they are -+ * directly (de)serialised from memory. -+ */ -+ -+ /* ensure the header structure has packed to the correct size */ -+ BUILD_BUG_ON(sizeof(struct mmal_msg_header) != 24); -+ -+ /* ensure message structure does not exceed maximum length */ -+ BUILD_BUG_ON(sizeof(struct mmal_msg) > MMAL_MSG_MAX_SIZE); -+ -+ /* mmal port struct is correct size */ -+ BUILD_BUG_ON(sizeof(struct mmal_port) != 64); -+ -+ /* create a vchi instance */ -+ status = vchi_initialise(&vchi_instance); -+ if (status) { -+ pr_err("Failed to initialise VCHI instance (status=%d)\n", -+ status); -+ return -EIO; -+ } -+ -+ status = vchi_connect(NULL, 0, vchi_instance); -+ if (status) { -+ pr_err("Failed to connect VCHI instance (status=%d)\n", status); -+ return -EIO; -+ } -+ -+ instance = kmalloc(sizeof(*instance), GFP_KERNEL); -+ memset(instance, 0, sizeof(*instance)); -+ -+ mutex_init(&instance->vchiq_mutex); -+ mutex_init(&instance->bulk_mutex); -+ -+ instance->bulk_scratch = vmalloc(PAGE_SIZE); -+ -+ params.callback_param = instance; -+ -+ status = vchi_service_open(vchi_instance, ¶ms, &instance->handle); -+ if (status) { -+ pr_err("Failed to open VCHI service connection (status=%d)\n", -+ status); -+ goto err_close_services; -+ } -+ -+ vchi_service_release(instance->handle); -+ -+ *out_instance = instance; -+ -+ return 0; -+ -+err_close_services: -+ -+ vchi_service_close(instance->handle); -+ vfree(instance->bulk_scratch); -+ kfree(instance); -+ return -ENODEV; -+} -diff -Nur linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-vchiq.h linux-rpi/drivers/media/platform/bcm2835/mmal-vchiq.h ---- linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-vchiq.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/media/platform/bcm2835/mmal-vchiq.h 2015-11-29 09:42:37.835237156 +0100 -@@ -0,0 +1,178 @@ -+/* -+ * Broadcom BM2835 V4L2 driver -+ * -+ * Copyright © 2013 Raspberry Pi (Trading) Ltd. -+ * -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file COPYING in the main directory of this archive -+ * for more details. -+ * -+ * Authors: Vincent Sanders -+ * Dave Stevenson -+ * Simon Mellor -+ * Luke Diamand -+ * -+ * MMAL interface to VCHIQ message passing -+ */ -+ -+#ifndef MMAL_VCHIQ_H -+#define MMAL_VCHIQ_H -+ -+#include "mmal-msg-format.h" -+ -+#define MAX_PORT_COUNT 4 -+ -+/* Maximum size of the format extradata. */ -+#define MMAL_FORMAT_EXTRADATA_MAX_SIZE 128 -+ -+struct vchiq_mmal_instance; -+ -+enum vchiq_mmal_es_type { -+ MMAL_ES_TYPE_UNKNOWN, /**< Unknown elementary stream type */ -+ MMAL_ES_TYPE_CONTROL, /**< Elementary stream of control commands */ -+ MMAL_ES_TYPE_AUDIO, /**< Audio elementary stream */ -+ MMAL_ES_TYPE_VIDEO, /**< Video elementary stream */ -+ MMAL_ES_TYPE_SUBPICTURE /**< Sub-picture elementary stream */ -+}; -+ -+/* rectangle, used lots so it gets its own struct */ -+struct vchiq_mmal_rect { -+ s32 x; -+ s32 y; -+ s32 width; -+ s32 height; -+}; -+ -+struct vchiq_mmal_port_buffer { -+ unsigned int num; /* number of buffers */ -+ u32 size; /* size of buffers */ -+ u32 alignment; /* alignment of buffers */ -+}; -+ -+struct vchiq_mmal_port; -+ -+typedef void (*vchiq_mmal_buffer_cb)( -+ struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_port *port, -+ int status, struct mmal_buffer *buffer, -+ unsigned long length, u32 mmal_flags, s64 dts, s64 pts); -+ -+struct vchiq_mmal_port { -+ bool enabled; -+ u32 handle; -+ u32 type; /* port type, cached to use on port info set */ -+ u32 index; /* port index, cached to use on port info set */ -+ -+ /* component port belongs to, allows simple deref */ -+ struct vchiq_mmal_component *component; -+ -+ struct vchiq_mmal_port *connected; /* port conencted to */ -+ -+ /* buffer info */ -+ struct vchiq_mmal_port_buffer minimum_buffer; -+ struct vchiq_mmal_port_buffer recommended_buffer; -+ struct vchiq_mmal_port_buffer current_buffer; -+ -+ /* stream format */ -+ struct mmal_es_format format; -+ /* elementry stream format */ -+ union mmal_es_specific_format es; -+ -+ /* data buffers to fill */ -+ struct list_head buffers; -+ /* lock to serialise adding and removing buffers from list */ -+ spinlock_t slock; -+ /* count of how many buffer header refils have failed because -+ * there was no buffer to satisfy them -+ */ -+ int buffer_underflow; -+ /* callback on buffer completion */ -+ vchiq_mmal_buffer_cb buffer_cb; -+ /* callback context */ -+ void *cb_ctx; -+}; -+ -+struct vchiq_mmal_component { -+ bool enabled; -+ u32 handle; /* VideoCore handle for component */ -+ u32 inputs; /* Number of input ports */ -+ u32 outputs; /* Number of output ports */ -+ u32 clocks; /* Number of clock ports */ -+ struct vchiq_mmal_port control; /* control port */ -+ struct vchiq_mmal_port input[MAX_PORT_COUNT]; /* input ports */ -+ struct vchiq_mmal_port output[MAX_PORT_COUNT]; /* output ports */ -+ struct vchiq_mmal_port clock[MAX_PORT_COUNT]; /* clock ports */ -+}; -+ -+ -+int vchiq_mmal_init(struct vchiq_mmal_instance **out_instance); -+int vchiq_mmal_finalise(struct vchiq_mmal_instance *instance); -+ -+/* Initialise a mmal component and its ports -+* -+*/ -+int vchiq_mmal_component_init( -+ struct vchiq_mmal_instance *instance, -+ const char *name, -+ struct vchiq_mmal_component **component_out); -+ -+int vchiq_mmal_component_finalise( -+ struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_component *component); -+ -+int vchiq_mmal_component_enable( -+ struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_component *component); -+ -+int vchiq_mmal_component_disable( -+ struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_component *component); -+ -+ -+ -+/* enable a mmal port -+ * -+ * enables a port and if a buffer callback provided enque buffer -+ * headers as apropriate for the port. -+ */ -+int vchiq_mmal_port_enable( -+ struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_port *port, -+ vchiq_mmal_buffer_cb buffer_cb); -+ -+/* disable a port -+ * -+ * disable a port will dequeue any pending buffers -+ */ -+int vchiq_mmal_port_disable(struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_port *port); -+ -+ -+int vchiq_mmal_port_parameter_set(struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_port *port, -+ u32 parameter, -+ void *value, -+ u32 value_size); -+ -+int vchiq_mmal_port_parameter_get(struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_port *port, -+ u32 parameter, -+ void *value, -+ u32 *value_size); -+ -+int vchiq_mmal_port_set_format(struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_port *port); -+ -+int vchiq_mmal_port_connect_tunnel(struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_port *src, -+ struct vchiq_mmal_port *dst); -+ -+int vchiq_mmal_version(struct vchiq_mmal_instance *instance, -+ u32 *major_out, -+ u32 *minor_out); -+ -+int vchiq_mmal_submit_buffer(struct vchiq_mmal_instance *instance, -+ struct vchiq_mmal_port *port, -+ struct mmal_buffer *buf); -+ -+#endif /* MMAL_VCHIQ_H */ -diff -Nur linux-4.1.13.orig/drivers/media/platform/Kconfig linux-rpi/drivers/media/platform/Kconfig ---- linux-4.1.13.orig/drivers/media/platform/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/media/platform/Kconfig 2015-11-29 09:42:37.835237156 +0100 -@@ -11,6 +11,8 @@ - - if V4L_PLATFORM_DRIVERS - -+source "drivers/media/platform/bcm2835/Kconfig" -+ - source "drivers/media/platform/marvell-ccic/Kconfig" - - config VIDEO_VIA_CAMERA -diff -Nur linux-4.1.13.orig/drivers/media/platform/Makefile linux-rpi/drivers/media/platform/Makefile ---- linux-4.1.13.orig/drivers/media/platform/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/media/platform/Makefile 2015-11-29 09:42:37.835237156 +0100 -@@ -2,6 +2,8 @@ - # Makefile for the video capture/playback device drivers. - # - -+obj-$(CONFIG_VIDEO_BCM2835) += bcm2835/ -+ - obj-$(CONFIG_VIDEO_TIMBERDALE) += timblogiw.o - obj-$(CONFIG_VIDEO_M32R_AR_M64278) += arv.o - -diff -Nur linux-4.1.13.orig/drivers/media/usb/dvb-usb-v2/rtl28xxu.c linux-rpi/drivers/media/usb/dvb-usb-v2/rtl28xxu.c ---- linux-4.1.13.orig/drivers/media/usb/dvb-usb-v2/rtl28xxu.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/media/usb/dvb-usb-v2/rtl28xxu.c 2015-11-29 09:42:37.915231841 +0100 -@@ -1755,6 +1755,10 @@ - &rtl28xxu_props, "Compro VideoMate U620F", NULL) }, - { DVB_USB_DEVICE(USB_VID_KWORLD_2, 0xd394, - &rtl28xxu_props, "MaxMedia HU394-T", NULL) }, -+ { DVB_USB_DEVICE(USB_VID_GTEK, 0xb803 /*USB_PID_AUGUST_DVBT205*/, -+ &rtl28xxu_props, "August DVB-T 205", NULL) }, -+ { DVB_USB_DEVICE(USB_VID_GTEK, 0xa803 /*USB_PID_AUGUST_DVBT205*/, -+ &rtl28xxu_props, "August DVB-T 205", NULL) }, - { DVB_USB_DEVICE(USB_VID_LEADTEK, 0x6a03, - &rtl28xxu_props, "Leadtek WinFast DTV Dongle mini", NULL) }, - { DVB_USB_DEVICE(USB_VID_GTEK, USB_PID_CPYTO_REDI_PC50A, -diff -Nur linux-4.1.13.orig/drivers/mfd/Kconfig linux-rpi/drivers/mfd/Kconfig ---- linux-4.1.13.orig/drivers/mfd/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/mfd/Kconfig 2015-11-29 09:42:37.991226791 +0100 -@@ -10,6 +10,14 @@ - select IRQ_DOMAIN - default n - -+config MFD_RPISENSE_CORE -+ tristate "Raspberry Pi Sense HAT core functions" -+ depends on I2C -+ select MFD_CORE -+ help -+ This is the core driver for the Raspberry Pi Sense HAT. This provides -+ the necessary functions to communicate with the hardware. -+ - config MFD_CS5535 - tristate "AMD CS5535 and CS5536 southbridge core functions" - select MFD_CORE -diff -Nur linux-4.1.13.orig/drivers/mfd/Makefile linux-rpi/drivers/mfd/Makefile ---- linux-4.1.13.orig/drivers/mfd/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/mfd/Makefile 2015-11-29 09:42:37.991226791 +0100 -@@ -185,3 +185,5 @@ - intel-soc-pmic-objs := intel_soc_pmic_core.o intel_soc_pmic_crc.o - obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o - obj-$(CONFIG_MFD_MT6397) += mt6397-core.o -+ -+obj-$(CONFIG_MFD_RPISENSE_CORE) += rpisense-core.o -diff -Nur linux-4.1.13.orig/drivers/mfd/rpisense-core.c linux-rpi/drivers/mfd/rpisense-core.c ---- linux-4.1.13.orig/drivers/mfd/rpisense-core.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/mfd/rpisense-core.c 2015-11-29 09:42:38.019224931 +0100 -@@ -0,0 +1,157 @@ -+/* -+ * Raspberry Pi Sense HAT core driver -+ * http://raspberrypi.org -+ * -+ * Copyright (C) 2015 Raspberry Pi -+ * -+ * Author: Serge Schneider -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ * This driver is based on wm8350 implementation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+struct rpisense *rpisense; -+ -+static void rpisense_client_dev_register(struct rpisense *rpisense, -+ const char *name, -+ struct platform_device **pdev) -+{ -+ int ret; -+ -+ *pdev = platform_device_alloc(name, -1); -+ if (*pdev == NULL) { -+ dev_err(rpisense->dev, "Failed to allocate %s\n", name); -+ return; -+ } -+ -+ (*pdev)->dev.parent = rpisense->dev; -+ platform_set_drvdata(*pdev, rpisense); -+ ret = platform_device_add(*pdev); -+ if (ret != 0) { -+ dev_err(rpisense->dev, "Failed to register %s: %d\n", -+ name, ret); -+ platform_device_put(*pdev); -+ *pdev = NULL; -+ } -+} -+ -+static int rpisense_probe(struct i2c_client *i2c, -+ const struct i2c_device_id *id) -+{ -+ int ret; -+ struct rpisense_js *rpisense_js; -+ -+ rpisense = devm_kzalloc(&i2c->dev, sizeof(struct rpisense), GFP_KERNEL); -+ if (rpisense == NULL) -+ return -ENOMEM; -+ -+ i2c_set_clientdata(i2c, rpisense); -+ rpisense->dev = &i2c->dev; -+ rpisense->i2c_client = i2c; -+ -+ ret = rpisense_reg_read(rpisense, RPISENSE_WAI); -+ if (ret > 0) { -+ if (ret != 's') -+ return -EINVAL; -+ } else { -+ return ret; -+ } -+ ret = rpisense_reg_read(rpisense, RPISENSE_VER); -+ if (ret < 0) -+ return ret; -+ -+ dev_info(rpisense->dev, -+ "Raspberry Pi Sense HAT firmware version %i\n", ret); -+ -+ rpisense_js = &rpisense->joystick; -+ rpisense_js->keys_desc = devm_gpiod_get(&i2c->dev, -+ "keys-int", GPIOD_IN); -+ if (IS_ERR(rpisense_js->keys_desc)) { -+ dev_warn(&i2c->dev, "Failed to get keys-int descriptor.\n"); -+ rpisense_js->keys_desc = gpio_to_desc(23); -+ if (rpisense_js->keys_desc == NULL) { -+ dev_err(&i2c->dev, "GPIO23 fallback failed.\n"); -+ return PTR_ERR(rpisense_js->keys_desc); -+ } -+ } -+ rpisense_client_dev_register(rpisense, "rpi-sense-js", -+ &(rpisense->joystick.pdev)); -+ rpisense_client_dev_register(rpisense, "rpi-sense-fb", -+ &(rpisense->framebuffer.pdev)); -+ -+ return 0; -+} -+ -+static int rpisense_remove(struct i2c_client *i2c) -+{ -+ struct rpisense *rpisense = i2c_get_clientdata(i2c); -+ -+ platform_device_unregister(rpisense->joystick.pdev); -+ return 0; -+} -+ -+struct rpisense *rpisense_get_dev(void) -+{ -+ return rpisense; -+} -+EXPORT_SYMBOL_GPL(rpisense_get_dev); -+ -+s32 rpisense_reg_read(struct rpisense *rpisense, int reg) -+{ -+ int ret = i2c_smbus_read_byte_data(rpisense->i2c_client, reg); -+ -+ if (ret < 0) -+ dev_err(rpisense->dev, "Read from reg %d failed\n", reg); -+ /* Due to the BCM270x I2C clock stretching bug, some values -+ * may have MSB set. Clear it to avoid incorrect values. -+ * */ -+ return ret & 0x7F; -+} -+EXPORT_SYMBOL_GPL(rpisense_reg_read); -+ -+int rpisense_block_write(struct rpisense *rpisense, const char *buf, int count) -+{ -+ int ret = i2c_master_send(rpisense->i2c_client, buf, count); -+ -+ if (ret < 0) -+ dev_err(rpisense->dev, "Block write failed\n"); -+ return ret; -+} -+EXPORT_SYMBOL_GPL(rpisense_block_write); -+ -+static const struct i2c_device_id rpisense_i2c_id[] = { -+ { "rpi-sense", 0 }, -+ { } -+}; -+MODULE_DEVICE_TABLE(i2c, rpisense_i2c_id); -+ -+ -+static struct i2c_driver rpisense_driver = { -+ .driver = { -+ .name = "rpi-sense", -+ .owner = THIS_MODULE, -+ }, -+ .probe = rpisense_probe, -+ .remove = rpisense_remove, -+ .id_table = rpisense_i2c_id, -+}; -+ -+module_i2c_driver(rpisense_driver); -+ -+MODULE_DESCRIPTION("Raspberry Pi Sense HAT core driver"); -+MODULE_AUTHOR("Serge Schneider "); -+MODULE_LICENSE("GPL"); -+ -diff -Nur linux-4.1.13.orig/drivers/misc/bcm2835_smi.c linux-rpi/drivers/misc/bcm2835_smi.c ---- linux-4.1.13.orig/drivers/misc/bcm2835_smi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/misc/bcm2835_smi.c 2015-11-29 09:42:38.035223868 +0100 -@@ -0,0 +1,985 @@ -+/** -+ * Broadcom Secondary Memory Interface driver -+ * -+ * Written by Luke Wren -+ * Copyright (c) 2015, Raspberry Pi (Trading) Ltd. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define BCM2835_SMI_IMPLEMENTATION -+#include -+ -+#define DRIVER_NAME "smi-bcm2835" -+ -+#define N_PAGES_FROM_BYTES(n) ((n + PAGE_SIZE-1) / PAGE_SIZE) -+ -+#define DMA_WRITE_TO_MEM true -+#define DMA_READ_FROM_MEM false -+ -+struct bcm2835_smi_instance { -+ struct device *dev; -+ struct smi_settings settings; -+ __iomem void *smi_regs_ptr, *cm_smi_regs_ptr; -+ dma_addr_t smi_regs_busaddr; -+ -+ struct dma_chan *dma_chan; -+ struct dma_slave_config dma_config; -+ -+ struct bcm2835_smi_bounce_info bounce; -+ -+ struct scatterlist buffer_sgl; -+ -+ int clock_source; -+ int clock_divisor; -+ -+ /* Sometimes we are called into in an atomic context (e.g. by -+ JFFS2 + MTD) so we can't use a mutex */ -+ spinlock_t transaction_lock; -+}; -+ -+/**************************************************************************** -+* -+* SMI clock manager setup -+* -+***************************************************************************/ -+ -+static inline void write_smi_cm_reg(struct bcm2835_smi_instance *inst, -+ u32 val, unsigned reg) -+{ -+ writel(CM_PWD | val, inst->cm_smi_regs_ptr + reg); -+} -+ -+static inline u32 read_smi_cm_reg(struct bcm2835_smi_instance *inst, -+ unsigned reg) -+{ -+ return readl(inst->cm_smi_regs_ptr + reg); -+} -+ -+static void smi_setup_clock(struct bcm2835_smi_instance *inst) -+{ -+ dev_dbg(inst->dev, "Setting up clock..."); -+ /* Disable SMI clock and wait for it to stop. */ -+ write_smi_cm_reg(inst, 0, CM_SMI_CTL); -+ while (read_smi_cm_reg(inst, CM_SMI_CTL) & CM_SMI_CTL_BUSY) -+ ; -+ -+ write_smi_cm_reg(inst, (inst->clock_divisor << CM_SMI_DIV_DIVI_OFFS), -+ CM_SMI_DIV); -+ write_smi_cm_reg(inst, (inst->clock_source << CM_SMI_CTL_SRC_OFFS), -+ CM_SMI_CTL); -+ -+ /* Enable the clock */ -+ write_smi_cm_reg(inst, (inst->clock_source << CM_SMI_CTL_SRC_OFFS) | -+ CM_SMI_CTL_ENAB, CM_SMI_CTL); -+} -+ -+/**************************************************************************** -+* -+* SMI peripheral setup -+* -+***************************************************************************/ -+ -+static inline void write_smi_reg(struct bcm2835_smi_instance *inst, -+ u32 val, unsigned reg) -+{ -+ writel(val, inst->smi_regs_ptr + reg); -+} -+ -+static inline u32 read_smi_reg(struct bcm2835_smi_instance *inst, unsigned reg) -+{ -+ return readl(inst->smi_regs_ptr + reg); -+} -+ -+/* Token-paste macro for e.g SMIDSR_RSTROBE -> value of SMIDSR_RSTROBE_MASK */ -+#define _CONCAT(x, y) x##y -+#define CONCAT(x, y) _CONCAT(x, y) -+ -+#define SET_BIT_FIELD(dest, field, bits) ((dest) = \ -+ ((dest) & ~CONCAT(field, _MASK)) | (((bits) << CONCAT(field, _OFFS))& \ -+ CONCAT(field, _MASK))) -+#define GET_BIT_FIELD(src, field) (((src) & \ -+ CONCAT(field, _MASK)) >> CONCAT(field, _OFFS)) -+ -+static void smi_dump_context_labelled(struct bcm2835_smi_instance *inst, -+ const char *label) -+{ -+ dev_err(inst->dev, "SMI context dump: %s", label); -+ dev_err(inst->dev, "SMICS: 0x%08x", read_smi_reg(inst, SMICS)); -+ dev_err(inst->dev, "SMIL: 0x%08x", read_smi_reg(inst, SMIL)); -+ dev_err(inst->dev, "SMIDSR: 0x%08x", read_smi_reg(inst, SMIDSR0)); -+ dev_err(inst->dev, "SMIDSW: 0x%08x", read_smi_reg(inst, SMIDSW0)); -+ dev_err(inst->dev, "SMIDC: 0x%08x", read_smi_reg(inst, SMIDC)); -+ dev_err(inst->dev, "SMIFD: 0x%08x", read_smi_reg(inst, SMIFD)); -+ dev_err(inst->dev, " "); -+} -+ -+static inline void smi_dump_context(struct bcm2835_smi_instance *inst) -+{ -+ smi_dump_context_labelled(inst, ""); -+} -+ -+static void smi_get_default_settings(struct bcm2835_smi_instance *inst) -+{ -+ struct smi_settings *settings = &inst->settings; -+ -+ settings->data_width = SMI_WIDTH_16BIT; -+ settings->pack_data = true; -+ -+ settings->read_setup_time = 1; -+ settings->read_hold_time = 1; -+ settings->read_pace_time = 1; -+ settings->read_strobe_time = 3; -+ -+ settings->write_setup_time = settings->read_setup_time; -+ settings->write_hold_time = settings->read_hold_time; -+ settings->write_pace_time = settings->read_pace_time; -+ settings->write_strobe_time = settings->read_strobe_time; -+ -+ settings->dma_enable = true; -+ settings->dma_passthrough_enable = false; -+ settings->dma_read_thresh = 0x01; -+ settings->dma_write_thresh = 0x3f; -+ settings->dma_panic_read_thresh = 0x20; -+ settings->dma_panic_write_thresh = 0x20; -+} -+ -+void bcm2835_smi_set_regs_from_settings(struct bcm2835_smi_instance *inst) -+{ -+ struct smi_settings *settings = &inst->settings; -+ int smidsr_temp = 0, smidsw_temp = 0, smics_temp, -+ smidcs_temp, smidc_temp = 0; -+ -+ spin_lock(&inst->transaction_lock); -+ -+ /* temporarily disable the peripheral: */ -+ smics_temp = read_smi_reg(inst, SMICS); -+ write_smi_reg(inst, 0, SMICS); -+ smidcs_temp = read_smi_reg(inst, SMIDCS); -+ write_smi_reg(inst, 0, SMIDCS); -+ -+ if (settings->pack_data) -+ smics_temp |= SMICS_PXLDAT; -+ else -+ smics_temp &= ~SMICS_PXLDAT; -+ -+ SET_BIT_FIELD(smidsr_temp, SMIDSR_RWIDTH, settings->data_width); -+ SET_BIT_FIELD(smidsr_temp, SMIDSR_RSETUP, settings->read_setup_time); -+ SET_BIT_FIELD(smidsr_temp, SMIDSR_RHOLD, settings->read_hold_time); -+ SET_BIT_FIELD(smidsr_temp, SMIDSR_RPACE, settings->read_pace_time); -+ SET_BIT_FIELD(smidsr_temp, SMIDSR_RSTROBE, settings->read_strobe_time); -+ write_smi_reg(inst, smidsr_temp, SMIDSR0); -+ -+ SET_BIT_FIELD(smidsw_temp, SMIDSW_WWIDTH, settings->data_width); -+ if (settings->data_width == SMI_WIDTH_8BIT) -+ smidsw_temp |= SMIDSW_WSWAP; -+ else -+ smidsw_temp &= ~SMIDSW_WSWAP; -+ SET_BIT_FIELD(smidsw_temp, SMIDSW_WSETUP, settings->write_setup_time); -+ SET_BIT_FIELD(smidsw_temp, SMIDSW_WHOLD, settings->write_hold_time); -+ SET_BIT_FIELD(smidsw_temp, SMIDSW_WPACE, settings->write_pace_time); -+ SET_BIT_FIELD(smidsw_temp, SMIDSW_WSTROBE, -+ settings->write_strobe_time); -+ write_smi_reg(inst, smidsw_temp, SMIDSW0); -+ -+ SET_BIT_FIELD(smidc_temp, SMIDC_REQR, settings->dma_read_thresh); -+ SET_BIT_FIELD(smidc_temp, SMIDC_REQW, settings->dma_write_thresh); -+ SET_BIT_FIELD(smidc_temp, SMIDC_PANICR, -+ settings->dma_panic_read_thresh); -+ SET_BIT_FIELD(smidc_temp, SMIDC_PANICW, -+ settings->dma_panic_write_thresh); -+ if (settings->dma_passthrough_enable) { -+ smidc_temp |= SMIDC_DMAP; -+ smidsr_temp |= SMIDSR_RDREQ; -+ write_smi_reg(inst, smidsr_temp, SMIDSR0); -+ smidsw_temp |= SMIDSW_WDREQ; -+ write_smi_reg(inst, smidsw_temp, SMIDSW0); -+ } else -+ smidc_temp &= ~SMIDC_DMAP; -+ if (settings->dma_enable) -+ smidc_temp |= SMIDC_DMAEN; -+ else -+ smidc_temp &= ~SMIDC_DMAEN; -+ -+ write_smi_reg(inst, smidc_temp, SMIDC); -+ -+ /* re-enable (if was previously enabled) */ -+ write_smi_reg(inst, smics_temp, SMICS); -+ write_smi_reg(inst, smidcs_temp, SMIDCS); -+ -+ spin_unlock(&inst->transaction_lock); -+} -+EXPORT_SYMBOL(bcm2835_smi_set_regs_from_settings); -+ -+struct smi_settings *bcm2835_smi_get_settings_from_regs -+ (struct bcm2835_smi_instance *inst) -+{ -+ struct smi_settings *settings = &inst->settings; -+ int smidsr, smidsw, smidc; -+ -+ spin_lock(&inst->transaction_lock); -+ -+ smidsr = read_smi_reg(inst, SMIDSR0); -+ smidsw = read_smi_reg(inst, SMIDSW0); -+ smidc = read_smi_reg(inst, SMIDC); -+ -+ settings->pack_data = (read_smi_reg(inst, SMICS) & SMICS_PXLDAT) ? -+ true : false; -+ -+ settings->data_width = GET_BIT_FIELD(smidsr, SMIDSR_RWIDTH); -+ settings->read_setup_time = GET_BIT_FIELD(smidsr, SMIDSR_RSETUP); -+ settings->read_hold_time = GET_BIT_FIELD(smidsr, SMIDSR_RHOLD); -+ settings->read_pace_time = GET_BIT_FIELD(smidsr, SMIDSR_RPACE); -+ settings->read_strobe_time = GET_BIT_FIELD(smidsr, SMIDSR_RSTROBE); -+ -+ settings->write_setup_time = GET_BIT_FIELD(smidsw, SMIDSW_WSETUP); -+ settings->write_hold_time = GET_BIT_FIELD(smidsw, SMIDSW_WHOLD); -+ settings->write_pace_time = GET_BIT_FIELD(smidsw, SMIDSW_WPACE); -+ settings->write_strobe_time = GET_BIT_FIELD(smidsw, SMIDSW_WSTROBE); -+ -+ settings->dma_read_thresh = GET_BIT_FIELD(smidc, SMIDC_REQR); -+ settings->dma_write_thresh = GET_BIT_FIELD(smidc, SMIDC_REQW); -+ settings->dma_panic_read_thresh = GET_BIT_FIELD(smidc, SMIDC_PANICR); -+ settings->dma_panic_write_thresh = GET_BIT_FIELD(smidc, SMIDC_PANICW); -+ settings->dma_passthrough_enable = (smidc & SMIDC_DMAP) ? true : false; -+ settings->dma_enable = (smidc & SMIDC_DMAEN) ? true : false; -+ -+ spin_unlock(&inst->transaction_lock); -+ -+ return settings; -+} -+EXPORT_SYMBOL(bcm2835_smi_get_settings_from_regs); -+ -+static inline void smi_set_address(struct bcm2835_smi_instance *inst, -+ unsigned int address) -+{ -+ int smia_temp = 0, smida_temp = 0; -+ -+ SET_BIT_FIELD(smia_temp, SMIA_ADDR, address); -+ SET_BIT_FIELD(smida_temp, SMIDA_ADDR, address); -+ -+ /* Write to both address registers - user doesn't care whether we're -+ doing programmed or direct transfers. */ -+ write_smi_reg(inst, smia_temp, SMIA); -+ write_smi_reg(inst, smida_temp, SMIDA); -+} -+ -+static void smi_setup_regs(struct bcm2835_smi_instance *inst) -+{ -+ -+ dev_dbg(inst->dev, "Initialising SMI registers..."); -+ /* Disable the peripheral if already enabled */ -+ write_smi_reg(inst, 0, SMICS); -+ write_smi_reg(inst, 0, SMIDCS); -+ -+ smi_get_default_settings(inst); -+ bcm2835_smi_set_regs_from_settings(inst); -+ smi_set_address(inst, 0); -+ -+ write_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_ENABLE, SMICS); -+ write_smi_reg(inst, read_smi_reg(inst, SMIDCS) | SMIDCS_ENABLE, -+ SMIDCS); -+} -+ -+/**************************************************************************** -+* -+* Low-level SMI access functions -+* Other modules should use the exported higher-level functions e.g. -+* bcm2835_smi_write_buf() unless they have a good reason to use these -+* -+***************************************************************************/ -+ -+static inline uint32_t smi_read_single_word(struct bcm2835_smi_instance *inst) -+{ -+ int timeout = 0; -+ -+ write_smi_reg(inst, SMIDCS_ENABLE, SMIDCS); -+ write_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_START, SMIDCS); -+ /* Make sure things happen in the right order...*/ -+ mb(); -+ while (!(read_smi_reg(inst, SMIDCS) & SMIDCS_DONE) && -+ ++timeout < 10000) -+ ; -+ if (timeout < 10000) -+ return read_smi_reg(inst, SMIDD); -+ -+ dev_err(inst->dev, -+ "SMI direct read timed out (is the clock set up correctly?)"); -+ return 0; -+} -+ -+static inline void smi_write_single_word(struct bcm2835_smi_instance *inst, -+ uint32_t data) -+{ -+ int timeout = 0; -+ -+ write_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_WRITE, SMIDCS); -+ write_smi_reg(inst, data, SMIDD); -+ write_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_WRITE | SMIDCS_START, -+ SMIDCS); -+ -+ while (!(read_smi_reg(inst, SMIDCS) & SMIDCS_DONE) && -+ ++timeout < 10000) -+ ; -+ if (timeout >= 10000) -+ dev_err(inst->dev, -+ "SMI direct write timed out (is the clock set up correctly?)"); -+} -+ -+/* Initiates a programmed read into the read FIFO. It is up to the caller to -+ * read data from the FIFO - either via paced DMA transfer, -+ * or polling SMICS_RXD to check whether data is available. -+ * SMICS_ACTIVE will go low upon completion. */ -+static void smi_init_programmed_read(struct bcm2835_smi_instance *inst, -+ int num_transfers) -+{ -+ int smics_temp; -+ -+ /* Disable the peripheral: */ -+ smics_temp = read_smi_reg(inst, SMICS) & ~(SMICS_ENABLE | SMICS_WRITE); -+ write_smi_reg(inst, smics_temp, SMICS); -+ while (read_smi_reg(inst, SMICS) & SMICS_ENABLE) -+ ; -+ -+ /* Program the transfer count: */ -+ write_smi_reg(inst, num_transfers, SMIL); -+ -+ /* re-enable and start: */ -+ smics_temp |= SMICS_ENABLE; -+ write_smi_reg(inst, smics_temp, SMICS); -+ smics_temp |= SMICS_CLEAR; -+ /* Just to be certain: */ -+ mb(); -+ while (read_smi_reg(inst, SMICS) & SMICS_ACTIVE) -+ ; -+ write_smi_reg(inst, smics_temp, SMICS); -+ smics_temp |= SMICS_START; -+ write_smi_reg(inst, smics_temp, SMICS); -+} -+ -+/* Initiates a programmed write sequence, using data from the write FIFO. -+ * It is up to the caller to initiate a DMA transfer before calling, -+ * or use another method to keep the write FIFO topped up. -+ * SMICS_ACTIVE will go low upon completion. -+ */ -+static void smi_init_programmed_write(struct bcm2835_smi_instance *inst, -+ int num_transfers) -+{ -+ int smics_temp; -+ -+ /* Disable the peripheral: */ -+ smics_temp = read_smi_reg(inst, SMICS) & ~SMICS_ENABLE; -+ write_smi_reg(inst, smics_temp, SMICS); -+ while (read_smi_reg(inst, SMICS) & SMICS_ENABLE) -+ ; -+ -+ /* Program the transfer count: */ -+ write_smi_reg(inst, num_transfers, SMIL); -+ -+ /* setup, re-enable and start: */ -+ smics_temp |= SMICS_WRITE | SMICS_ENABLE; -+ write_smi_reg(inst, smics_temp, SMICS); -+ smics_temp |= SMICS_START; -+ write_smi_reg(inst, smics_temp, SMICS); -+} -+ -+/* Initiate a read and then poll FIFO for data, reading out as it appears. */ -+static void smi_read_fifo(struct bcm2835_smi_instance *inst, -+ uint32_t *dest, int n_bytes) -+{ -+ if (read_smi_reg(inst, SMICS) & SMICS_RXD) { -+ smi_dump_context_labelled(inst, -+ "WARNING: read FIFO not empty at start of read call."); -+ while (read_smi_reg(inst, SMICS)) -+ ; -+ } -+ -+ /* Dispatch the read: */ -+ if (inst->settings.data_width == SMI_WIDTH_8BIT) -+ smi_init_programmed_read(inst, n_bytes); -+ else if (inst->settings.data_width == SMI_WIDTH_16BIT) -+ smi_init_programmed_read(inst, n_bytes / 2); -+ else { -+ dev_err(inst->dev, "Unsupported data width for read."); -+ return; -+ } -+ -+ /* Poll FIFO to keep it empty */ -+ while (!(read_smi_reg(inst, SMICS) & SMICS_DONE)) -+ if (read_smi_reg(inst, SMICS) & SMICS_RXD) -+ *dest++ = read_smi_reg(inst, SMID); -+ -+ /* Ensure that the FIFO is emptied */ -+ if (read_smi_reg(inst, SMICS) & SMICS_RXD) { -+ int fifo_count; -+ -+ fifo_count = GET_BIT_FIELD(read_smi_reg(inst, SMIFD), -+ SMIFD_FCNT); -+ while (fifo_count--) -+ *dest++ = read_smi_reg(inst, SMID); -+ } -+ -+ if (!(read_smi_reg(inst, SMICS) & SMICS_DONE)) -+ smi_dump_context_labelled(inst, -+ "WARNING: transaction finished but done bit not set."); -+ -+ if (read_smi_reg(inst, SMICS) & SMICS_RXD) -+ smi_dump_context_labelled(inst, -+ "WARNING: read FIFO not empty at end of read call."); -+ -+} -+ -+/* Initiate a write, and then keep the FIFO topped up. */ -+static void smi_write_fifo(struct bcm2835_smi_instance *inst, -+ uint32_t *src, int n_bytes) -+{ -+ int i, timeout = 0; -+ -+ /* Empty FIFOs if not already so */ -+ if (!(read_smi_reg(inst, SMICS) & SMICS_TXE)) { -+ smi_dump_context_labelled(inst, -+ "WARNING: write fifo not empty at start of write call."); -+ write_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_CLEAR, -+ SMICS); -+ } -+ -+ /* Initiate the transfer */ -+ if (inst->settings.data_width == SMI_WIDTH_8BIT) -+ smi_init_programmed_write(inst, n_bytes); -+ else if (inst->settings.data_width == SMI_WIDTH_16BIT) -+ smi_init_programmed_write(inst, n_bytes / 2); -+ else { -+ dev_err(inst->dev, "Unsupported data width for write."); -+ return; -+ } -+ /* Fill the FIFO: */ -+ for (i = 0; i < (n_bytes - 1) / 4 + 1; ++i) { -+ while (!(read_smi_reg(inst, SMICS) & SMICS_TXD)) -+ ; -+ write_smi_reg(inst, *src++, SMID); -+ } -+ /* Busy wait... */ -+ while (!(read_smi_reg(inst, SMICS) & SMICS_DONE) && ++timeout < -+ 1000000) -+ ; -+ if (timeout >= 1000000) -+ smi_dump_context_labelled(inst, -+ "Timed out on write operation!"); -+ if (!(read_smi_reg(inst, SMICS) & SMICS_TXE)) -+ smi_dump_context_labelled(inst, -+ "WARNING: FIFO not empty at end of write operation."); -+} -+ -+/**************************************************************************** -+* -+* SMI DMA operations -+* -+***************************************************************************/ -+ -+/* Disable SMI and put it into the correct direction before doing DMA setup. -+ Stops spurious DREQs during setup. Peripheral is re-enabled by init_*() */ -+static void smi_disable(struct bcm2835_smi_instance *inst, -+ enum dma_transfer_direction direction) -+{ -+ int smics_temp = read_smi_reg(inst, SMICS) & ~SMICS_ENABLE; -+ -+ if (direction == DMA_DEV_TO_MEM) -+ smics_temp &= ~SMICS_WRITE; -+ else -+ smics_temp |= SMICS_WRITE; -+ write_smi_reg(inst, smics_temp, SMICS); -+ while (read_smi_reg(inst, SMICS) & SMICS_ACTIVE) -+ ; -+} -+ -+static struct scatterlist *smi_scatterlist_from_buffer( -+ struct bcm2835_smi_instance *inst, -+ dma_addr_t buf, -+ size_t len, -+ struct scatterlist *sg) -+{ -+ sg_init_table(sg, 1); -+ sg_dma_address(sg) = buf; -+ sg_dma_len(sg) = len; -+ return sg; -+} -+ -+static void smi_dma_callback_user_copy(void *param) -+{ -+ /* Notify the bottom half that a chunk is ready for user copy */ -+ struct bcm2835_smi_instance *inst = -+ (struct bcm2835_smi_instance *)param; -+ -+ up(&inst->bounce.callback_sem); -+} -+ -+/* Creates a descriptor, assigns the given callback, and submits the -+ descriptor to dmaengine. Does not block - can queue up multiple -+ descriptors and then wait for them all to complete. -+ sg_len is the number of control blocks, NOT the number of bytes. -+ dir can be DMA_MEM_TO_DEV or DMA_DEV_TO_MEM. -+ callback can be NULL - in this case it is not called. */ -+static inline struct dma_async_tx_descriptor *smi_dma_submit_sgl( -+ struct bcm2835_smi_instance *inst, -+ struct scatterlist *sgl, -+ size_t sg_len, -+ enum dma_transfer_direction dir, -+ dma_async_tx_callback callback) -+{ -+ struct dma_async_tx_descriptor *desc; -+ -+ desc = dmaengine_prep_slave_sg(inst->dma_chan, -+ sgl, -+ sg_len, -+ dir, -+ DMA_PREP_INTERRUPT | DMA_CTRL_ACK | -+ DMA_PREP_FENCE); -+ if (!desc) { -+ dev_err(inst->dev, "read_sgl: dma slave preparation failed!"); -+ write_smi_reg(inst, read_smi_reg(inst, SMICS) & ~SMICS_ACTIVE, -+ SMICS); -+ while (read_smi_reg(inst, SMICS) & SMICS_ACTIVE) -+ cpu_relax(); -+ write_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_ACTIVE, -+ SMICS); -+ return NULL; -+ } -+ desc->callback = callback; -+ desc->callback_param = inst; -+ if (dmaengine_submit(desc) < 0) -+ return NULL; -+ return desc; -+} -+ -+/* NB this function blocks until the transfer is complete */ -+static void -+smi_dma_read_sgl(struct bcm2835_smi_instance *inst, -+ struct scatterlist *sgl, size_t sg_len, size_t n_bytes) -+{ -+ struct dma_async_tx_descriptor *desc; -+ -+ /* Disable SMI and set to read before dispatching DMA - if SMI is in -+ * write mode and TX fifo is empty, it will generate a DREQ which may -+ * cause the read DMA to complete before the SMI read command is even -+ * dispatched! We want to dispatch DMA before SMI read so that reading -+ * is gapless, for logic analyser. -+ */ -+ -+ smi_disable(inst, DMA_DEV_TO_MEM); -+ -+ desc = smi_dma_submit_sgl(inst, sgl, sg_len, DMA_DEV_TO_MEM, NULL); -+ dma_async_issue_pending(inst->dma_chan); -+ -+ if (inst->settings.data_width == SMI_WIDTH_8BIT) -+ smi_init_programmed_read(inst, n_bytes); -+ else -+ smi_init_programmed_read(inst, n_bytes / 2); -+ -+ if (dma_wait_for_async_tx(desc) == DMA_ERROR) -+ smi_dump_context_labelled(inst, "DMA timeout!"); -+} -+ -+static void -+smi_dma_write_sgl(struct bcm2835_smi_instance *inst, -+ struct scatterlist *sgl, size_t sg_len, size_t n_bytes) -+{ -+ struct dma_async_tx_descriptor *desc; -+ -+ if (inst->settings.data_width == SMI_WIDTH_8BIT) -+ smi_init_programmed_write(inst, n_bytes); -+ else -+ smi_init_programmed_write(inst, n_bytes / 2); -+ -+ desc = smi_dma_submit_sgl(inst, sgl, sg_len, DMA_MEM_TO_DEV, NULL); -+ dma_async_issue_pending(inst->dma_chan); -+ -+ if (dma_wait_for_async_tx(desc) == DMA_ERROR) -+ smi_dump_context_labelled(inst, "DMA timeout!"); -+ else -+ /* Wait for SMI to finish our writes */ -+ while (!(read_smi_reg(inst, SMICS) & SMICS_DONE)) -+ cpu_relax(); -+} -+ -+ssize_t bcm2835_smi_user_dma( -+ struct bcm2835_smi_instance *inst, -+ enum dma_transfer_direction dma_dir, -+ char __user *user_ptr, size_t count, -+ struct bcm2835_smi_bounce_info **bounce) -+{ -+ int chunk_no = 0, chunk_size, count_left = count; -+ struct scatterlist *sgl; -+ void (*init_trans_func)(struct bcm2835_smi_instance *, int); -+ -+ spin_lock(&inst->transaction_lock); -+ -+ if (dma_dir == DMA_DEV_TO_MEM) -+ init_trans_func = smi_init_programmed_read; -+ else -+ init_trans_func = smi_init_programmed_write; -+ -+ smi_disable(inst, dma_dir); -+ -+ sema_init(&inst->bounce.callback_sem, 0); -+ if (bounce) -+ *bounce = &inst->bounce; -+ while (count_left) { -+ chunk_size = count_left > DMA_BOUNCE_BUFFER_SIZE ? -+ DMA_BOUNCE_BUFFER_SIZE : count_left; -+ if (chunk_size == DMA_BOUNCE_BUFFER_SIZE) { -+ sgl = -+ &inst->bounce.sgl[chunk_no % DMA_BOUNCE_BUFFER_COUNT]; -+ } else { -+ sgl = smi_scatterlist_from_buffer( -+ inst, -+ inst->bounce.phys[ -+ chunk_no % DMA_BOUNCE_BUFFER_COUNT], -+ chunk_size, -+ &inst->buffer_sgl); -+ } -+ -+ if (!smi_dma_submit_sgl(inst, sgl, 1, dma_dir, -+ smi_dma_callback_user_copy -+ )) { -+ dev_err(inst->dev, "sgl submit failed"); -+ count = 0; -+ goto out; -+ } -+ count_left -= chunk_size; -+ chunk_no++; -+ } -+ dma_async_issue_pending(inst->dma_chan); -+ -+ if (inst->settings.data_width == SMI_WIDTH_8BIT) -+ init_trans_func(inst, count); -+ else if (inst->settings.data_width == SMI_WIDTH_16BIT) -+ init_trans_func(inst, count / 2); -+out: -+ spin_unlock(&inst->transaction_lock); -+ return count; -+} -+EXPORT_SYMBOL(bcm2835_smi_user_dma); -+ -+ -+/**************************************************************************** -+* -+* High level buffer transfer functions - for use by other drivers -+* -+***************************************************************************/ -+ -+/* Buffer must be physically contiguous - i.e. kmalloc, not vmalloc! */ -+void bcm2835_smi_write_buf( -+ struct bcm2835_smi_instance *inst, -+ const void *buf, size_t n_bytes) -+{ -+ int odd_bytes = n_bytes & 0x3; -+ -+ n_bytes -= odd_bytes; -+ -+ spin_lock(&inst->transaction_lock); -+ -+ if (n_bytes > DMA_THRESHOLD_BYTES) { -+ dma_addr_t phy_addr = dma_map_single( -+ inst->dev, -+ (void *)buf, -+ n_bytes, -+ DMA_MEM_TO_DEV); -+ struct scatterlist *sgl = -+ smi_scatterlist_from_buffer(inst, phy_addr, n_bytes, -+ &inst->buffer_sgl); -+ -+ if (!sgl) { -+ smi_dump_context_labelled(inst, -+ "Error: could not create scatterlist for write!"); -+ goto out; -+ } -+ smi_dma_write_sgl(inst, sgl, 1, n_bytes); -+ -+ dma_unmap_single -+ (inst->dev, phy_addr, n_bytes, DMA_MEM_TO_DEV); -+ } else if (n_bytes) { -+ smi_write_fifo(inst, (uint32_t *) buf, n_bytes); -+ } -+ buf += n_bytes; -+ -+ if (inst->settings.data_width == SMI_WIDTH_8BIT) { -+ while (odd_bytes--) -+ smi_write_single_word(inst, *(uint8_t *) (buf++)); -+ } else { -+ while (odd_bytes >= 2) { -+ smi_write_single_word(inst, *(uint16_t *)buf); -+ buf += 2; -+ odd_bytes -= 2; -+ } -+ if (odd_bytes) { -+ /* Reading an odd number of bytes on a 16 bit bus is -+ a user bug. It's kinder to fail early and tell them -+ than to e.g. transparently give them the bottom byte -+ of a 16 bit transfer. */ -+ dev_err(inst->dev, -+ "WARNING: odd number of bytes specified for wide transfer."); -+ dev_err(inst->dev, -+ "At least one byte dropped as a result."); -+ dump_stack(); -+ } -+ } -+out: -+ spin_unlock(&inst->transaction_lock); -+} -+EXPORT_SYMBOL(bcm2835_smi_write_buf); -+ -+void bcm2835_smi_read_buf(struct bcm2835_smi_instance *inst, -+ void *buf, size_t n_bytes) -+{ -+ -+ /* SMI is inherently 32-bit, which causes surprising amounts of mess -+ for bytes % 4 != 0. Easiest to avoid this mess altogether -+ by handling remainder separately. */ -+ int odd_bytes = n_bytes & 0x3; -+ -+ spin_lock(&inst->transaction_lock); -+ n_bytes -= odd_bytes; -+ if (n_bytes > DMA_THRESHOLD_BYTES) { -+ dma_addr_t phy_addr = dma_map_single(inst->dev, -+ buf, n_bytes, -+ DMA_DEV_TO_MEM); -+ struct scatterlist *sgl = smi_scatterlist_from_buffer( -+ inst, phy_addr, n_bytes, -+ &inst->buffer_sgl); -+ if (!sgl) { -+ smi_dump_context_labelled(inst, -+ "Error: could not create scatterlist for read!"); -+ goto out; -+ } -+ smi_dma_read_sgl(inst, sgl, 1, n_bytes); -+ dma_unmap_single(inst->dev, phy_addr, n_bytes, DMA_DEV_TO_MEM); -+ } else if (n_bytes) { -+ smi_read_fifo(inst, (uint32_t *)buf, n_bytes); -+ } -+ buf += n_bytes; -+ -+ if (inst->settings.data_width == SMI_WIDTH_8BIT) { -+ while (odd_bytes--) -+ *((uint8_t *) (buf++)) = smi_read_single_word(inst); -+ } else { -+ while (odd_bytes >= 2) { -+ *(uint16_t *) buf = smi_read_single_word(inst); -+ buf += 2; -+ odd_bytes -= 2; -+ } -+ if (odd_bytes) { -+ dev_err(inst->dev, -+ "WARNING: odd number of bytes specified for wide transfer."); -+ dev_err(inst->dev, -+ "At least one byte dropped as a result."); -+ dump_stack(); -+ } -+ } -+out: -+ spin_unlock(&inst->transaction_lock); -+} -+EXPORT_SYMBOL(bcm2835_smi_read_buf); -+ -+void bcm2835_smi_set_address(struct bcm2835_smi_instance *inst, -+ unsigned int address) -+{ -+ spin_lock(&inst->transaction_lock); -+ smi_set_address(inst, address); -+ spin_unlock(&inst->transaction_lock); -+} -+EXPORT_SYMBOL(bcm2835_smi_set_address); -+ -+struct bcm2835_smi_instance *bcm2835_smi_get(struct device_node *node) -+{ -+ struct platform_device *pdev; -+ -+ if (!node) -+ return NULL; -+ -+ pdev = of_find_device_by_node(node); -+ if (!pdev) -+ return NULL; -+ -+ return platform_get_drvdata(pdev); -+} -+EXPORT_SYMBOL(bcm2835_smi_get); -+ -+/**************************************************************************** -+* -+* bcm2835_smi_probe - called when the driver is loaded. -+* -+***************************************************************************/ -+ -+static int bcm2835_smi_dma_setup(struct bcm2835_smi_instance *inst) -+{ -+ int i, rv = 0; -+ -+ inst->dma_chan = dma_request_slave_channel(inst->dev, "rx-tx"); -+ -+ inst->dma_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; -+ inst->dma_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; -+ inst->dma_config.src_addr = inst->smi_regs_busaddr + SMID; -+ inst->dma_config.dst_addr = inst->dma_config.src_addr; -+ /* Direction unimportant - always overridden by prep_slave_sg */ -+ inst->dma_config.direction = DMA_DEV_TO_MEM; -+ dmaengine_slave_config(inst->dma_chan, &inst->dma_config); -+ /* Alloc and map bounce buffers */ -+ for (i = 0; i < DMA_BOUNCE_BUFFER_COUNT; ++i) { -+ inst->bounce.buffer[i] = -+ dmam_alloc_coherent(inst->dev, DMA_BOUNCE_BUFFER_SIZE, -+ &inst->bounce.phys[i], -+ GFP_KERNEL); -+ if (!inst->bounce.buffer[i]) { -+ dev_err(inst->dev, "Could not allocate buffer!"); -+ rv = -ENOMEM; -+ break; -+ } -+ smi_scatterlist_from_buffer( -+ inst, -+ inst->bounce.phys[i], -+ DMA_BOUNCE_BUFFER_SIZE, -+ &inst->bounce.sgl[i] -+ ); -+ } -+ -+ return rv; -+} -+ -+static int bcm2835_smi_probe(struct platform_device *pdev) -+{ -+ int err; -+ struct device *dev = &pdev->dev; -+ struct device_node *node = dev->of_node; -+ struct resource *ioresource; -+ struct bcm2835_smi_instance *inst; -+ -+ /* Allocate buffers and instance data */ -+ -+ inst = devm_kzalloc(dev, sizeof(struct bcm2835_smi_instance), -+ GFP_KERNEL); -+ -+ if (!inst) -+ return -ENOMEM; -+ -+ inst->dev = dev; -+ spin_lock_init(&inst->transaction_lock); -+ -+ /* We require device tree support */ -+ if (!node) -+ return -EINVAL; -+ -+ ioresource = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ inst->smi_regs_ptr = devm_ioremap_resource(dev, ioresource); -+ ioresource = platform_get_resource(pdev, IORESOURCE_MEM, 1); -+ inst->cm_smi_regs_ptr = devm_ioremap_resource(dev, ioresource); -+ inst->smi_regs_busaddr = be32_to_cpu( -+ *of_get_address(node, 0, NULL, NULL)); -+ of_property_read_u32(node, -+ "brcm,smi-clock-source", -+ &inst->clock_source); -+ of_property_read_u32(node, -+ "brcm,smi-clock-divisor", -+ &inst->clock_divisor); -+ -+ err = bcm2835_smi_dma_setup(inst); -+ if (err) -+ return err; -+ -+ /* Finally, do peripheral setup */ -+ -+ smi_setup_clock(inst); -+ smi_setup_regs(inst); -+ -+ platform_set_drvdata(pdev, inst); -+ -+ dev_info(inst->dev, "initialised"); -+ -+ return 0; -+} -+ -+/**************************************************************************** -+* -+* bcm2835_smi_remove - called when the driver is unloaded. -+* -+***************************************************************************/ -+ -+static int bcm2835_smi_remove(struct platform_device *pdev) -+{ -+ struct bcm2835_smi_instance *inst = platform_get_drvdata(pdev); -+ struct device *dev = inst->dev; -+ -+ dev_info(dev, "SMI device removed - OK"); -+ return 0; -+} -+ -+/**************************************************************************** -+* -+* Register the driver with device tree -+* -+***************************************************************************/ -+ -+static const struct of_device_id bcm2835_smi_of_match[] = { -+ {.compatible = "brcm,bcm2835-smi",}, -+ { /* sentinel */ }, -+}; -+ -+MODULE_DEVICE_TABLE(of, bcm2835_smi_of_match); -+ -+static struct platform_driver bcm2835_smi_driver = { -+ .probe = bcm2835_smi_probe, -+ .remove = bcm2835_smi_remove, -+ .driver = { -+ .name = DRIVER_NAME, -+ .owner = THIS_MODULE, -+ .of_match_table = bcm2835_smi_of_match, -+ }, -+}; -+ -+module_platform_driver(bcm2835_smi_driver); -+ -+MODULE_ALIAS("platform:smi-bcm2835"); -+MODULE_LICENSE("GPL"); -+MODULE_DESCRIPTION("Device driver for BCM2835's secondary memory interface"); -+MODULE_AUTHOR("Luke Wren "); -diff -Nur linux-4.1.13.orig/drivers/misc/Kconfig linux-rpi/drivers/misc/Kconfig ---- linux-4.1.13.orig/drivers/misc/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/misc/Kconfig 2015-11-29 09:42:38.035223868 +0100 -@@ -10,6 +10,14 @@ - select INPUT_POLLDEV - default n - -+config BCM2835_SMI -+ tristate "Broadcom 283x Secondary Memory Interface driver" -+ depends on MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835 -+ default m -+ help -+ Driver for enabling and using Broadcom's Secondary/Slow Memory Interface. -+ Appears as /dev/bcm2835_smi. For ioctl interface see drivers/misc/bcm2835_smi.h -+ - config AD525X_DPOT - tristate "Analog Devices Digital Potentiometers" - depends on (I2C || SPI) && SYSFS -@@ -524,6 +532,7 @@ - source "drivers/misc/altera-stapl/Kconfig" - source "drivers/misc/mei/Kconfig" - source "drivers/misc/vmw_vmci/Kconfig" -+source "drivers/misc/vc04_services/Kconfig" - source "drivers/misc/mic/Kconfig" - source "drivers/misc/genwqe/Kconfig" - source "drivers/misc/echo/Kconfig" -diff -Nur linux-4.1.13.orig/drivers/misc/Makefile linux-rpi/drivers/misc/Makefile ---- linux-4.1.13.orig/drivers/misc/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/misc/Makefile 2015-11-29 09:42:38.035223868 +0100 -@@ -9,6 +9,7 @@ - obj-$(CONFIG_INTEL_MID_PTI) += pti.o - obj-$(CONFIG_ATMEL_SSC) += atmel-ssc.o - obj-$(CONFIG_ATMEL_TCLIB) += atmel_tclib.o -+obj-$(CONFIG_BCM2835_SMI) += bcm2835_smi.o - obj-$(CONFIG_BMP085) += bmp085.o - obj-$(CONFIG_BMP085_I2C) += bmp085-i2c.o - obj-$(CONFIG_BMP085_SPI) += bmp085-spi.o -@@ -51,6 +52,7 @@ - obj-$(CONFIG_VMWARE_VMCI) += vmw_vmci/ - obj-$(CONFIG_LATTICE_ECP3_CONFIG) += lattice-ecp3-config.o - obj-$(CONFIG_SRAM) += sram.o -+obj-$(CONFIG_BCM2708_VCHIQ) += vc04_services/ - obj-y += mic/ - obj-$(CONFIG_GENWQE) += genwqe/ - obj-$(CONFIG_ECHO) += echo/ -diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchi/connections/connection.h linux-rpi/drivers/misc/vc04_services/interface/vchi/connections/connection.h ---- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchi/connections/connection.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/misc/vc04_services/interface/vchi/connections/connection.h 2015-11-29 09:42:38.059222273 +0100 -@@ -0,0 +1,328 @@ -+/** -+ * Copyright (c) 2010-2012 Broadcom. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef CONNECTION_H_ -+#define CONNECTION_H_ -+ -+#include -+#include -+#include -+ -+#include "interface/vchi/vchi_cfg_internal.h" -+#include "interface/vchi/vchi_common.h" -+#include "interface/vchi/message_drivers/message.h" -+ -+/****************************************************************************** -+ Global defs -+ *****************************************************************************/ -+ -+// Opaque handle for a connection / service pair -+typedef struct opaque_vchi_connection_connected_service_handle_t *VCHI_CONNECTION_SERVICE_HANDLE_T; -+ -+// opaque handle to the connection state information -+typedef struct opaque_vchi_connection_info_t VCHI_CONNECTION_STATE_T; -+ -+typedef struct vchi_connection_t VCHI_CONNECTION_T; -+ -+ -+/****************************************************************************** -+ API -+ *****************************************************************************/ -+ -+// Routine to init a connection with a particular low level driver -+typedef VCHI_CONNECTION_STATE_T * (*VCHI_CONNECTION_INIT_T)( struct vchi_connection_t * connection, -+ const VCHI_MESSAGE_DRIVER_T * driver ); -+ -+// Routine to control CRC enabling at a connection level -+typedef int32_t (*VCHI_CONNECTION_CRC_CONTROL_T)( VCHI_CONNECTION_STATE_T *state_handle, -+ VCHI_CRC_CONTROL_T control ); -+ -+// Routine to create a service -+typedef int32_t (*VCHI_CONNECTION_SERVICE_CONNECT_T)( VCHI_CONNECTION_STATE_T *state_handle, -+ int32_t service_id, -+ uint32_t rx_fifo_size, -+ uint32_t tx_fifo_size, -+ int server, -+ VCHI_CALLBACK_T callback, -+ void *callback_param, -+ int32_t want_crc, -+ int32_t want_unaligned_bulk_rx, -+ int32_t want_unaligned_bulk_tx, -+ VCHI_CONNECTION_SERVICE_HANDLE_T *service_handle ); -+ -+// Routine to close a service -+typedef int32_t (*VCHI_CONNECTION_SERVICE_DISCONNECT_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle ); -+ -+// Routine to queue a message -+typedef int32_t (*VCHI_CONNECTION_SERVICE_QUEUE_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, -+ const void *data, -+ uint32_t data_size, -+ VCHI_FLAGS_T flags, -+ void *msg_handle ); -+ -+// scatter-gather (vector) message queueing -+typedef int32_t (*VCHI_CONNECTION_SERVICE_QUEUE_MESSAGEV_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, -+ VCHI_MSG_VECTOR_T *vector, -+ uint32_t count, -+ VCHI_FLAGS_T flags, -+ void *msg_handle ); -+ -+// Routine to dequeue a message -+typedef int32_t (*VCHI_CONNECTION_SERVICE_DEQUEUE_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, -+ void *data, -+ uint32_t max_data_size_to_read, -+ uint32_t *actual_msg_size, -+ VCHI_FLAGS_T flags ); -+ -+// Routine to peek at a message -+typedef int32_t (*VCHI_CONNECTION_SERVICE_PEEK_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, -+ void **data, -+ uint32_t *msg_size, -+ VCHI_FLAGS_T flags ); -+ -+// Routine to hold a message -+typedef int32_t (*VCHI_CONNECTION_SERVICE_HOLD_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, -+ void **data, -+ uint32_t *msg_size, -+ VCHI_FLAGS_T flags, -+ void **message_handle ); -+ -+// Routine to initialise a received message iterator -+typedef int32_t (*VCHI_CONNECTION_SERVICE_LOOKAHEAD_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, -+ VCHI_MSG_ITER_T *iter, -+ VCHI_FLAGS_T flags ); -+ -+// Routine to release a held message -+typedef int32_t (*VCHI_CONNECTION_HELD_MSG_RELEASE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, -+ void *message_handle ); -+ -+// Routine to get info on a held message -+typedef int32_t (*VCHI_CONNECTION_HELD_MSG_INFO_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, -+ void *message_handle, -+ void **data, -+ int32_t *msg_size, -+ uint32_t *tx_timestamp, -+ uint32_t *rx_timestamp ); -+ -+// Routine to check whether the iterator has a next message -+typedef int32_t (*VCHI_CONNECTION_MSG_ITER_HAS_NEXT_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service, -+ const VCHI_MSG_ITER_T *iter ); -+ -+// Routine to advance the iterator -+typedef int32_t (*VCHI_CONNECTION_MSG_ITER_NEXT_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service, -+ VCHI_MSG_ITER_T *iter, -+ void **data, -+ uint32_t *msg_size ); -+ -+// Routine to remove the last message returned by the iterator -+typedef int32_t (*VCHI_CONNECTION_MSG_ITER_REMOVE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service, -+ VCHI_MSG_ITER_T *iter ); -+ -+// Routine to hold the last message returned by the iterator -+typedef int32_t (*VCHI_CONNECTION_MSG_ITER_HOLD_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service, -+ VCHI_MSG_ITER_T *iter, -+ void **msg_handle ); -+ -+// Routine to transmit bulk data -+typedef int32_t (*VCHI_CONNECTION_BULK_QUEUE_TRANSMIT_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, -+ const void *data_src, -+ uint32_t data_size, -+ VCHI_FLAGS_T flags, -+ void *bulk_handle ); -+ -+// Routine to receive data -+typedef int32_t (*VCHI_CONNECTION_BULK_QUEUE_RECEIVE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, -+ void *data_dst, -+ uint32_t data_size, -+ VCHI_FLAGS_T flags, -+ void *bulk_handle ); -+ -+// Routine to report if a server is available -+typedef int32_t (*VCHI_CONNECTION_SERVER_PRESENT)( VCHI_CONNECTION_STATE_T *state, int32_t service_id, int32_t peer_flags ); -+ -+// Routine to report the number of RX slots available -+typedef int (*VCHI_CONNECTION_RX_SLOTS_AVAILABLE)( const VCHI_CONNECTION_STATE_T *state ); -+ -+// Routine to report the RX slot size -+typedef uint32_t (*VCHI_CONNECTION_RX_SLOT_SIZE)( const VCHI_CONNECTION_STATE_T *state ); -+ -+// Callback to indicate that the other side has added a buffer to the rx bulk DMA FIFO -+typedef void (*VCHI_CONNECTION_RX_BULK_BUFFER_ADDED)(VCHI_CONNECTION_STATE_T *state, -+ int32_t service, -+ uint32_t length, -+ MESSAGE_TX_CHANNEL_T channel, -+ uint32_t channel_params, -+ uint32_t data_length, -+ uint32_t data_offset); -+ -+// Callback to inform a service that a Xon or Xoff message has been received -+typedef void (*VCHI_CONNECTION_FLOW_CONTROL)(VCHI_CONNECTION_STATE_T *state, int32_t service_id, int32_t xoff); -+ -+// Callback to inform a service that a server available reply message has been received -+typedef void (*VCHI_CONNECTION_SERVER_AVAILABLE_REPLY)(VCHI_CONNECTION_STATE_T *state, int32_t service_id, uint32_t flags); -+ -+// Callback to indicate that bulk auxiliary messages have arrived -+typedef void (*VCHI_CONNECTION_BULK_AUX_RECEIVED)(VCHI_CONNECTION_STATE_T *state); -+ -+// Callback to indicate that bulk auxiliary messages have arrived -+typedef void (*VCHI_CONNECTION_BULK_AUX_TRANSMITTED)(VCHI_CONNECTION_STATE_T *state, void *handle); -+ -+// Callback with all the connection info you require -+typedef void (*VCHI_CONNECTION_INFO)(VCHI_CONNECTION_STATE_T *state, uint32_t protocol_version, uint32_t slot_size, uint32_t num_slots, uint32_t min_bulk_size); -+ -+// Callback to inform of a disconnect -+typedef void (*VCHI_CONNECTION_DISCONNECT)(VCHI_CONNECTION_STATE_T *state, uint32_t flags); -+ -+// Callback to inform of a power control request -+typedef void (*VCHI_CONNECTION_POWER_CONTROL)(VCHI_CONNECTION_STATE_T *state, MESSAGE_TX_CHANNEL_T channel, int32_t enable); -+ -+// allocate memory suitably aligned for this connection -+typedef void * (*VCHI_BUFFER_ALLOCATE)(VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, uint32_t * length); -+ -+// free memory allocated by buffer_allocate -+typedef void (*VCHI_BUFFER_FREE)(VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, void * address); -+ -+ -+/****************************************************************************** -+ System driver struct -+ *****************************************************************************/ -+ -+struct opaque_vchi_connection_api_t -+{ -+ // Routine to init the connection -+ VCHI_CONNECTION_INIT_T init; -+ -+ // Connection-level CRC control -+ VCHI_CONNECTION_CRC_CONTROL_T crc_control; -+ -+ // Routine to connect to or create service -+ VCHI_CONNECTION_SERVICE_CONNECT_T service_connect; -+ -+ // Routine to disconnect from a service -+ VCHI_CONNECTION_SERVICE_DISCONNECT_T service_disconnect; -+ -+ // Routine to queue a message -+ VCHI_CONNECTION_SERVICE_QUEUE_MESSAGE_T service_queue_msg; -+ -+ // scatter-gather (vector) message queue -+ VCHI_CONNECTION_SERVICE_QUEUE_MESSAGEV_T service_queue_msgv; -+ -+ // Routine to dequeue a message -+ VCHI_CONNECTION_SERVICE_DEQUEUE_MESSAGE_T service_dequeue_msg; -+ -+ // Routine to peek at a message -+ VCHI_CONNECTION_SERVICE_PEEK_MESSAGE_T service_peek_msg; -+ -+ // Routine to hold a message -+ VCHI_CONNECTION_SERVICE_HOLD_MESSAGE_T service_hold_msg; -+ -+ // Routine to initialise a received message iterator -+ VCHI_CONNECTION_SERVICE_LOOKAHEAD_MESSAGE_T service_look_ahead_msg; -+ -+ // Routine to release a message -+ VCHI_CONNECTION_HELD_MSG_RELEASE_T held_msg_release; -+ -+ // Routine to get information on a held message -+ VCHI_CONNECTION_HELD_MSG_INFO_T held_msg_info; -+ -+ // Routine to check for next message on iterator -+ VCHI_CONNECTION_MSG_ITER_HAS_NEXT_T msg_iter_has_next; -+ -+ // Routine to get next message on iterator -+ VCHI_CONNECTION_MSG_ITER_NEXT_T msg_iter_next; -+ -+ // Routine to remove the last message returned by iterator -+ VCHI_CONNECTION_MSG_ITER_REMOVE_T msg_iter_remove; -+ -+ // Routine to hold the last message returned by iterator -+ VCHI_CONNECTION_MSG_ITER_HOLD_T msg_iter_hold; -+ -+ // Routine to transmit bulk data -+ VCHI_CONNECTION_BULK_QUEUE_TRANSMIT_T bulk_queue_transmit; -+ -+ // Routine to receive data -+ VCHI_CONNECTION_BULK_QUEUE_RECEIVE_T bulk_queue_receive; -+ -+ // Routine to report the available servers -+ VCHI_CONNECTION_SERVER_PRESENT server_present; -+ -+ // Routine to report the number of RX slots available -+ VCHI_CONNECTION_RX_SLOTS_AVAILABLE connection_rx_slots_available; -+ -+ // Routine to report the RX slot size -+ VCHI_CONNECTION_RX_SLOT_SIZE connection_rx_slot_size; -+ -+ // Callback to indicate that the other side has added a buffer to the rx bulk DMA FIFO -+ VCHI_CONNECTION_RX_BULK_BUFFER_ADDED rx_bulk_buffer_added; -+ -+ // Callback to inform a service that a Xon or Xoff message has been received -+ VCHI_CONNECTION_FLOW_CONTROL flow_control; -+ -+ // Callback to inform a service that a server available reply message has been received -+ VCHI_CONNECTION_SERVER_AVAILABLE_REPLY server_available_reply; -+ -+ // Callback to indicate that bulk auxiliary messages have arrived -+ VCHI_CONNECTION_BULK_AUX_RECEIVED bulk_aux_received; -+ -+ // Callback to indicate that a bulk auxiliary message has been transmitted -+ VCHI_CONNECTION_BULK_AUX_TRANSMITTED bulk_aux_transmitted; -+ -+ // Callback to provide information about the connection -+ VCHI_CONNECTION_INFO connection_info; -+ -+ // Callback to notify that peer has requested disconnect -+ VCHI_CONNECTION_DISCONNECT disconnect; -+ -+ // Callback to notify that peer has requested power change -+ VCHI_CONNECTION_POWER_CONTROL power_control; -+ -+ // allocate memory suitably aligned for this connection -+ VCHI_BUFFER_ALLOCATE buffer_allocate; -+ -+ // free memory allocated by buffer_allocate -+ VCHI_BUFFER_FREE buffer_free; -+ -+}; -+ -+struct vchi_connection_t { -+ const VCHI_CONNECTION_API_T *api; -+ VCHI_CONNECTION_STATE_T *state; -+#ifdef VCHI_COARSE_LOCKING -+ struct semaphore sem; -+#endif -+}; -+ -+ -+#endif /* CONNECTION_H_ */ -+ -+/****************************** End of file **********************************/ -diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchi/message_drivers/message.h linux-rpi/drivers/misc/vc04_services/interface/vchi/message_drivers/message.h ---- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchi/message_drivers/message.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/misc/vc04_services/interface/vchi/message_drivers/message.h 2015-11-29 09:42:38.059222273 +0100 -@@ -0,0 +1,204 @@ -+/** -+ * Copyright (c) 2010-2012 Broadcom. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef _VCHI_MESSAGE_H_ -+#define _VCHI_MESSAGE_H_ -+ -+#include -+#include -+#include -+ -+#include "interface/vchi/vchi_cfg_internal.h" -+#include "interface/vchi/vchi_common.h" -+ -+ -+typedef enum message_event_type { -+ MESSAGE_EVENT_NONE, -+ MESSAGE_EVENT_NOP, -+ MESSAGE_EVENT_MESSAGE, -+ MESSAGE_EVENT_SLOT_COMPLETE, -+ MESSAGE_EVENT_RX_BULK_PAUSED, -+ MESSAGE_EVENT_RX_BULK_COMPLETE, -+ MESSAGE_EVENT_TX_COMPLETE, -+ MESSAGE_EVENT_MSG_DISCARDED -+} MESSAGE_EVENT_TYPE_T; -+ -+typedef enum vchi_msg_flags -+{ -+ VCHI_MSG_FLAGS_NONE = 0x0, -+ VCHI_MSG_FLAGS_TERMINATE_DMA = 0x1 -+} VCHI_MSG_FLAGS_T; -+ -+typedef enum message_tx_channel -+{ -+ MESSAGE_TX_CHANNEL_MESSAGE = 0, -+ MESSAGE_TX_CHANNEL_BULK = 1 // drivers may provide multiple bulk channels, from 1 upwards -+} MESSAGE_TX_CHANNEL_T; -+ -+// Macros used for cycling through bulk channels -+#define MESSAGE_TX_CHANNEL_BULK_PREV(c) (MESSAGE_TX_CHANNEL_BULK+((c)-MESSAGE_TX_CHANNEL_BULK+VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION-1)%VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION) -+#define MESSAGE_TX_CHANNEL_BULK_NEXT(c) (MESSAGE_TX_CHANNEL_BULK+((c)-MESSAGE_TX_CHANNEL_BULK+1)%VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION) -+ -+typedef enum message_rx_channel -+{ -+ MESSAGE_RX_CHANNEL_MESSAGE = 0, -+ MESSAGE_RX_CHANNEL_BULK = 1 // drivers may provide multiple bulk channels, from 1 upwards -+} MESSAGE_RX_CHANNEL_T; -+ -+// Message receive slot information -+typedef struct rx_msg_slot_info { -+ -+ struct rx_msg_slot_info *next; -+ //struct slot_info *prev; -+#if !defined VCHI_COARSE_LOCKING -+ struct semaphore sem; -+#endif -+ -+ uint8_t *addr; // base address of slot -+ uint32_t len; // length of slot in bytes -+ -+ uint32_t write_ptr; // hardware causes this to advance -+ uint32_t read_ptr; // this module does the reading -+ int active; // is this slot in the hardware dma fifo? -+ uint32_t msgs_parsed; // count how many messages are in this slot -+ uint32_t msgs_released; // how many messages have been released -+ void *state; // connection state information -+ uint8_t ref_count[VCHI_MAX_SERVICES_PER_CONNECTION]; // reference count for slots held by services -+} RX_MSG_SLOTINFO_T; -+ -+// The message driver no longer needs to know about the fields of RX_BULK_SLOTINFO_T - sort this out. -+// In particular, it mustn't use addr and len - they're the client buffer, but the message -+// driver will be tasked with sending the aligned core section. -+typedef struct rx_bulk_slotinfo_t { -+ struct rx_bulk_slotinfo_t *next; -+ -+ struct semaphore *blocking; -+ -+ // needed by DMA -+ void *addr; -+ uint32_t len; -+ -+ // needed for the callback -+ void *service; -+ void *handle; -+ VCHI_FLAGS_T flags; -+} RX_BULK_SLOTINFO_T; -+ -+ -+/* ---------------------------------------------------------------------- -+ * each connection driver will have a pool of the following struct. -+ * -+ * the pool will be managed by vchi_qman_* -+ * this means there will be multiple queues (single linked lists) -+ * a given struct message_info will be on exactly one of these queues -+ * at any one time -+ * -------------------------------------------------------------------- */ -+typedef struct rx_message_info { -+ -+ struct message_info *next; -+ //struct message_info *prev; -+ -+ uint8_t *addr; -+ uint32_t len; -+ RX_MSG_SLOTINFO_T *slot; // points to whichever slot contains this message -+ uint32_t tx_timestamp; -+ uint32_t rx_timestamp; -+ -+} RX_MESSAGE_INFO_T; -+ -+typedef struct { -+ MESSAGE_EVENT_TYPE_T type; -+ -+ struct { -+ // for messages -+ void *addr; // address of message -+ uint16_t slot_delta; // whether this message indicated slot delta -+ uint32_t len; // length of message -+ RX_MSG_SLOTINFO_T *slot; // slot this message is in -+ int32_t service; // service id this message is destined for -+ uint32_t tx_timestamp; // timestamp from the header -+ uint32_t rx_timestamp; // timestamp when we parsed it -+ } message; -+ -+ // FIXME: cleanup slot reporting... -+ RX_MSG_SLOTINFO_T *rx_msg; -+ RX_BULK_SLOTINFO_T *rx_bulk; -+ void *tx_handle; -+ MESSAGE_TX_CHANNEL_T tx_channel; -+ -+} MESSAGE_EVENT_T; -+ -+ -+// callbacks -+typedef void VCHI_MESSAGE_DRIVER_EVENT_CALLBACK_T( void *state ); -+ -+typedef struct { -+ VCHI_MESSAGE_DRIVER_EVENT_CALLBACK_T *event_callback; -+} VCHI_MESSAGE_DRIVER_OPEN_T; -+ -+ -+// handle to this instance of message driver (as returned by ->open) -+typedef struct opaque_mhandle_t *VCHI_MDRIVER_HANDLE_T; -+ -+struct opaque_vchi_message_driver_t { -+ VCHI_MDRIVER_HANDLE_T *(*open)( VCHI_MESSAGE_DRIVER_OPEN_T *params, void *state ); -+ int32_t (*suspending)( VCHI_MDRIVER_HANDLE_T *handle ); -+ int32_t (*resumed)( VCHI_MDRIVER_HANDLE_T *handle ); -+ int32_t (*power_control)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T, int32_t enable ); -+ int32_t (*add_msg_rx_slot)( VCHI_MDRIVER_HANDLE_T *handle, RX_MSG_SLOTINFO_T *slot ); // rx message -+ int32_t (*add_bulk_rx)( VCHI_MDRIVER_HANDLE_T *handle, void *data, uint32_t len, RX_BULK_SLOTINFO_T *slot ); // rx data (bulk) -+ int32_t (*send)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel, const void *data, uint32_t len, VCHI_MSG_FLAGS_T flags, void *send_handle ); // tx (message & bulk) -+ void (*next_event)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_EVENT_T *event ); // get the next event from message_driver -+ int32_t (*enable)( VCHI_MDRIVER_HANDLE_T *handle ); -+ int32_t (*form_message)( VCHI_MDRIVER_HANDLE_T *handle, int32_t service_id, VCHI_MSG_VECTOR_T *vector, uint32_t count, void -+ *address, uint32_t length_avail, uint32_t max_total_length, int32_t pad_to_fill, int32_t allow_partial ); -+ -+ int32_t (*update_message)( VCHI_MDRIVER_HANDLE_T *handle, void *dest, int16_t *slot_count ); -+ int32_t (*buffer_aligned)( VCHI_MDRIVER_HANDLE_T *handle, int tx, int uncached, const void *address, const uint32_t length ); -+ void * (*allocate_buffer)( VCHI_MDRIVER_HANDLE_T *handle, uint32_t *length ); -+ void (*free_buffer)( VCHI_MDRIVER_HANDLE_T *handle, void *address ); -+ int (*rx_slot_size)( VCHI_MDRIVER_HANDLE_T *handle, int msg_size ); -+ int (*tx_slot_size)( VCHI_MDRIVER_HANDLE_T *handle, int msg_size ); -+ -+ int32_t (*tx_supports_terminate)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel ); -+ uint32_t (*tx_bulk_chunk_size)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel ); -+ int (*tx_alignment)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel ); -+ int (*rx_alignment)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_RX_CHANNEL_T channel ); -+ void (*form_bulk_aux)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel, const void *data, uint32_t len, uint32_t chunk_size, const void **aux_data, int32_t *aux_len ); -+ void (*debug)( VCHI_MDRIVER_HANDLE_T *handle ); -+}; -+ -+ -+#endif // _VCHI_MESSAGE_H_ -+ -+/****************************** End of file ***********************************/ -diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchi/vchi_cfg.h linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi_cfg.h ---- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchi/vchi_cfg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi_cfg.h 2015-11-29 09:42:38.059222273 +0100 -@@ -0,0 +1,224 @@ -+/** -+ * Copyright (c) 2010-2012 Broadcom. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef VCHI_CFG_H_ -+#define VCHI_CFG_H_ -+ -+/**************************************************************************************** -+ * Defines in this first section are part of the VCHI API and may be examined by VCHI -+ * services. -+ ***************************************************************************************/ -+ -+/* Required alignment of base addresses for bulk transfer, if unaligned transfers are not enabled */ -+/* Really determined by the message driver, and should be available from a run-time call. */ -+#ifndef VCHI_BULK_ALIGN -+# if __VCCOREVER__ >= 0x04000000 -+# define VCHI_BULK_ALIGN 32 // Allows for the need to do cache cleans -+# else -+# define VCHI_BULK_ALIGN 16 -+# endif -+#endif -+ -+/* Required length multiple for bulk transfers, if unaligned transfers are not enabled */ -+/* May be less than or greater than VCHI_BULK_ALIGN */ -+/* Really determined by the message driver, and should be available from a run-time call. */ -+#ifndef VCHI_BULK_GRANULARITY -+# if __VCCOREVER__ >= 0x04000000 -+# define VCHI_BULK_GRANULARITY 32 // Allows for the need to do cache cleans -+# else -+# define VCHI_BULK_GRANULARITY 16 -+# endif -+#endif -+ -+/* The largest possible message to be queued with vchi_msg_queue. */ -+#ifndef VCHI_MAX_MSG_SIZE -+# if defined VCHI_LOCAL_HOST_PORT -+# define VCHI_MAX_MSG_SIZE 16384 // makes file transfers fast, but should they be using bulk? -+# else -+# define VCHI_MAX_MSG_SIZE 4096 // NOTE: THIS MUST BE LARGER THAN OR EQUAL TO THE SIZE OF THE KHRONOS MERGE BUFFER!! -+# endif -+#endif -+ -+/****************************************************************************************** -+ * Defines below are system configuration options, and should not be used by VCHI services. -+ *****************************************************************************************/ -+ -+/* How many connections can we support? A localhost implementation uses 2 connections, -+ * 1 for host-app, 1 for VMCS, and these are hooked together by a loopback MPHI VCFW -+ * driver. */ -+#ifndef VCHI_MAX_NUM_CONNECTIONS -+# define VCHI_MAX_NUM_CONNECTIONS 3 -+#endif -+ -+/* How many services can we open per connection? Extending this doesn't cost processing time, just a small -+ * amount of static memory. */ -+#ifndef VCHI_MAX_SERVICES_PER_CONNECTION -+# define VCHI_MAX_SERVICES_PER_CONNECTION 36 -+#endif -+ -+/* Adjust if using a message driver that supports more logical TX channels */ -+#ifndef VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION -+# define VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION 9 // 1 MPHI + 8 CCP2 logical channels -+#endif -+ -+/* Adjust if using a message driver that supports more logical RX channels */ -+#ifndef VCHI_MAX_BULK_RX_CHANNELS_PER_CONNECTION -+# define VCHI_MAX_BULK_RX_CHANNELS_PER_CONNECTION 1 // 1 MPHI -+#endif -+ -+/* How many receive slots do we use. This times VCHI_MAX_MSG_SIZE gives the effective -+ * receive queue space, less message headers. */ -+#ifndef VCHI_NUM_READ_SLOTS -+# if defined(VCHI_LOCAL_HOST_PORT) -+# define VCHI_NUM_READ_SLOTS 4 -+# else -+# define VCHI_NUM_READ_SLOTS 48 -+# endif -+#endif -+ -+/* Do we utilise overrun facility for receive message slots? Can aid peer transmit -+ * performance. Only define on VideoCore end, talking to host. -+ */ -+//#define VCHI_MSG_RX_OVERRUN -+ -+/* How many transmit slots do we use. Generally don't need many, as the hardware driver -+ * underneath VCHI will usually have its own buffering. */ -+#ifndef VCHI_NUM_WRITE_SLOTS -+# define VCHI_NUM_WRITE_SLOTS 4 -+#endif -+ -+/* If a service has held or queued received messages in VCHI_XOFF_THRESHOLD or more slots, -+ * then it's taking up too much buffer space, and the peer service will be told to stop -+ * transmitting with an XOFF message. For this to be effective, the VCHI_NUM_READ_SLOTS -+ * needs to be considerably bigger than VCHI_NUM_WRITE_SLOTS, or the transmit latency -+ * is too high. */ -+#ifndef VCHI_XOFF_THRESHOLD -+# define VCHI_XOFF_THRESHOLD (VCHI_NUM_READ_SLOTS / 2) -+#endif -+ -+/* After we've sent an XOFF, the peer will be told to resume transmission once the local -+ * service has dequeued/released enough messages that it's now occupying -+ * VCHI_XON_THRESHOLD slots or fewer. */ -+#ifndef VCHI_XON_THRESHOLD -+# define VCHI_XON_THRESHOLD (VCHI_NUM_READ_SLOTS / 4) -+#endif -+ -+/* A size below which a bulk transfer omits the handshake completely and always goes -+ * via the message channel, if bulk auxiliary is being sent on that service. (The user -+ * can guarantee this by enabling unaligned transmits). -+ * Not API. */ -+#ifndef VCHI_MIN_BULK_SIZE -+# define VCHI_MIN_BULK_SIZE ( VCHI_MAX_MSG_SIZE / 2 < 4096 ? VCHI_MAX_MSG_SIZE / 2 : 4096 ) -+#endif -+ -+/* Maximum size of bulk transmission chunks, for each interface type. A trade-off between -+ * speed and latency; the smaller the chunk size the better change of messages and other -+ * bulk transmissions getting in when big bulk transfers are happening. Set to 0 to not -+ * break transmissions into chunks. -+ */ -+#ifndef VCHI_MAX_BULK_CHUNK_SIZE_MPHI -+# define VCHI_MAX_BULK_CHUNK_SIZE_MPHI (16 * 1024) -+#endif -+ -+/* NB Chunked CCP2 transmissions violate the letter of the CCP2 spec by using "JPEG8" mode -+ * with multiple-line frames. Only use if the receiver can cope. */ -+#ifndef VCHI_MAX_BULK_CHUNK_SIZE_CCP2 -+# define VCHI_MAX_BULK_CHUNK_SIZE_CCP2 0 -+#endif -+ -+/* How many TX messages can we have pending in our transmit slots. Once exhausted, -+ * vchi_msg_queue will be blocked. */ -+#ifndef VCHI_TX_MSG_QUEUE_SIZE -+# define VCHI_TX_MSG_QUEUE_SIZE 256 -+#endif -+ -+/* How many RX messages can we have parsed in the receive slots. Once exhausted, parsing -+ * will be suspended until older messages are dequeued/released. */ -+#ifndef VCHI_RX_MSG_QUEUE_SIZE -+# define VCHI_RX_MSG_QUEUE_SIZE 256 -+#endif -+ -+/* Really should be able to cope if we run out of received message descriptors, by -+ * suspending parsing as the comment above says, but we don't. This sweeps the issue -+ * under the carpet. */ -+#if VCHI_RX_MSG_QUEUE_SIZE < (VCHI_MAX_MSG_SIZE/16 + 1) * VCHI_NUM_READ_SLOTS -+# undef VCHI_RX_MSG_QUEUE_SIZE -+# define VCHI_RX_MSG_QUEUE_SIZE (VCHI_MAX_MSG_SIZE/16 + 1) * VCHI_NUM_READ_SLOTS -+#endif -+ -+/* How many bulk transmits can we have pending. Once exhausted, vchi_bulk_queue_transmit -+ * will be blocked. */ -+#ifndef VCHI_TX_BULK_QUEUE_SIZE -+# define VCHI_TX_BULK_QUEUE_SIZE 64 -+#endif -+ -+/* How many bulk receives can we have pending. Once exhausted, vchi_bulk_queue_receive -+ * will be blocked. */ -+#ifndef VCHI_RX_BULK_QUEUE_SIZE -+# define VCHI_RX_BULK_QUEUE_SIZE 64 -+#endif -+ -+/* A limit on how many outstanding bulk requests we expect the peer to give us. If -+ * the peer asks for more than this, VCHI will fail and assert. The number is determined -+ * by the peer's hardware - it's the number of outstanding requests that can be queued -+ * on all bulk channels. VC3's MPHI peripheral allows 16. */ -+#ifndef VCHI_MAX_PEER_BULK_REQUESTS -+# define VCHI_MAX_PEER_BULK_REQUESTS 32 -+#endif -+ -+/* Define VCHI_CCP2TX_MANUAL_POWER if the host tells us when to turn the CCP2 -+ * transmitter on and off. -+ */ -+/*#define VCHI_CCP2TX_MANUAL_POWER*/ -+ -+#ifndef VCHI_CCP2TX_MANUAL_POWER -+ -+/* Timeout (in milliseconds) for putting the CCP2TX interface into IDLE state. Set -+ * negative for no IDLE. -+ */ -+# ifndef VCHI_CCP2TX_IDLE_TIMEOUT -+# define VCHI_CCP2TX_IDLE_TIMEOUT 5 -+# endif -+ -+/* Timeout (in milliseconds) for putting the CCP2TX interface into OFF state. Set -+ * negative for no OFF. -+ */ -+# ifndef VCHI_CCP2TX_OFF_TIMEOUT -+# define VCHI_CCP2TX_OFF_TIMEOUT 1000 -+# endif -+ -+#endif /* VCHI_CCP2TX_MANUAL_POWER */ -+ -+#endif /* VCHI_CFG_H_ */ -+ -+/****************************** End of file **********************************/ -diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchi/vchi_cfg_internal.h linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi_cfg_internal.h ---- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchi/vchi_cfg_internal.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi_cfg_internal.h 2015-11-29 09:42:38.059222273 +0100 -@@ -0,0 +1,71 @@ -+/** -+ * Copyright (c) 2010-2012 Broadcom. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef VCHI_CFG_INTERNAL_H_ -+#define VCHI_CFG_INTERNAL_H_ -+ -+/**************************************************************************************** -+ * Control optimisation attempts. -+ ***************************************************************************************/ -+ -+// Don't use lots of short-term locks - use great long ones, reducing the overall locks-per-second -+#define VCHI_COARSE_LOCKING -+ -+// Avoid lock then unlock on exit from blocking queue operations (msg tx, bulk rx/tx) -+// (only relevant if VCHI_COARSE_LOCKING) -+#define VCHI_ELIDE_BLOCK_EXIT_LOCK -+ -+// Avoid lock on non-blocking peek -+// (only relevant if VCHI_COARSE_LOCKING) -+#define VCHI_AVOID_PEEK_LOCK -+ -+// Use one slot-handler thread per connection, rather than 1 thread dealing with all connections in rotation. -+#define VCHI_MULTIPLE_HANDLER_THREADS -+ -+// Put free descriptors onto the head of the free queue, rather than the tail, so that we don't thrash -+// our way through the pool of descriptors. -+#define VCHI_PUSH_FREE_DESCRIPTORS_ONTO_HEAD -+ -+// Don't issue a MSG_AVAILABLE callback for every single message. Possibly only safe if VCHI_COARSE_LOCKING. -+#define VCHI_FEWER_MSG_AVAILABLE_CALLBACKS -+ -+// Don't use message descriptors for TX messages that don't need them -+#define VCHI_MINIMISE_TX_MSG_DESCRIPTORS -+ -+// Nano-locks for multiqueue -+//#define VCHI_MQUEUE_NANOLOCKS -+ -+// Lock-free(er) dequeuing -+//#define VCHI_RX_NANOLOCKS -+ -+#endif /*VCHI_CFG_INTERNAL_H_*/ -diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchi/vchi_common.h linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi_common.h ---- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchi/vchi_common.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi_common.h 2015-11-29 09:42:38.059222273 +0100 -@@ -0,0 +1,175 @@ -+/** -+ * Copyright (c) 2010-2012 Broadcom. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef VCHI_COMMON_H_ -+#define VCHI_COMMON_H_ -+ -+ -+//flags used when sending messages (must be bitmapped) -+typedef enum -+{ -+ VCHI_FLAGS_NONE = 0x0, -+ VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE = 0x1, // waits for message to be received, or sent (NB. not the same as being seen on other side) -+ VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE = 0x2, // run a callback when message sent -+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED = 0x4, // return once the transfer is in a queue ready to go -+ VCHI_FLAGS_ALLOW_PARTIAL = 0x8, -+ VCHI_FLAGS_BLOCK_UNTIL_DATA_READ = 0x10, -+ VCHI_FLAGS_CALLBACK_WHEN_DATA_READ = 0x20, -+ -+ VCHI_FLAGS_ALIGN_SLOT = 0x000080, // internal use only -+ VCHI_FLAGS_BULK_AUX_QUEUED = 0x010000, // internal use only -+ VCHI_FLAGS_BULK_AUX_COMPLETE = 0x020000, // internal use only -+ VCHI_FLAGS_BULK_DATA_QUEUED = 0x040000, // internal use only -+ VCHI_FLAGS_BULK_DATA_COMPLETE = 0x080000, // internal use only -+ VCHI_FLAGS_INTERNAL = 0xFF0000 -+} VCHI_FLAGS_T; -+ -+// constants for vchi_crc_control() -+typedef enum { -+ VCHI_CRC_NOTHING = -1, -+ VCHI_CRC_PER_SERVICE = 0, -+ VCHI_CRC_EVERYTHING = 1, -+} VCHI_CRC_CONTROL_T; -+ -+//callback reasons when an event occurs on a service -+typedef enum -+{ -+ VCHI_CALLBACK_REASON_MIN, -+ -+ //This indicates that there is data available -+ //handle is the msg id that was transmitted with the data -+ // When a message is received and there was no FULL message available previously, send callback -+ // Tasks get kicked by the callback, reset their event and try and read from the fifo until it fails -+ VCHI_CALLBACK_MSG_AVAILABLE, -+ VCHI_CALLBACK_MSG_SENT, -+ VCHI_CALLBACK_MSG_SPACE_AVAILABLE, // XXX not yet implemented -+ -+ // This indicates that a transfer from the other side has completed -+ VCHI_CALLBACK_BULK_RECEIVED, -+ //This indicates that data queued up to be sent has now gone -+ //handle is the msg id that was used when sending the data -+ VCHI_CALLBACK_BULK_SENT, -+ VCHI_CALLBACK_BULK_RX_SPACE_AVAILABLE, // XXX not yet implemented -+ VCHI_CALLBACK_BULK_TX_SPACE_AVAILABLE, // XXX not yet implemented -+ -+ VCHI_CALLBACK_SERVICE_CLOSED, -+ -+ // this side has sent XOFF to peer due to lack of data consumption by service -+ // (suggests the service may need to take some recovery action if it has -+ // been deliberately holding off consuming data) -+ VCHI_CALLBACK_SENT_XOFF, -+ VCHI_CALLBACK_SENT_XON, -+ -+ // indicates that a bulk transfer has finished reading the source buffer -+ VCHI_CALLBACK_BULK_DATA_READ, -+ -+ // power notification events (currently host side only) -+ VCHI_CALLBACK_PEER_OFF, -+ VCHI_CALLBACK_PEER_SUSPENDED, -+ VCHI_CALLBACK_PEER_ON, -+ VCHI_CALLBACK_PEER_RESUMED, -+ VCHI_CALLBACK_FORCED_POWER_OFF, -+ -+#ifdef USE_VCHIQ_ARM -+ // some extra notifications provided by vchiq_arm -+ VCHI_CALLBACK_SERVICE_OPENED, -+ VCHI_CALLBACK_BULK_RECEIVE_ABORTED, -+ VCHI_CALLBACK_BULK_TRANSMIT_ABORTED, -+#endif -+ -+ VCHI_CALLBACK_REASON_MAX -+} VCHI_CALLBACK_REASON_T; -+ -+// service control options -+typedef enum -+{ -+ VCHI_SERVICE_OPTION_MIN, -+ -+ VCHI_SERVICE_OPTION_TRACE, -+ VCHI_SERVICE_OPTION_SYNCHRONOUS, -+ -+ VCHI_SERVICE_OPTION_MAX -+} VCHI_SERVICE_OPTION_T; -+ -+ -+//Callback used by all services / bulk transfers -+typedef void (*VCHI_CALLBACK_T)( void *callback_param, //my service local param -+ VCHI_CALLBACK_REASON_T reason, -+ void *handle ); //for transmitting msg's only -+ -+ -+ -+/* -+ * Define vector struct for scatter-gather (vector) operations -+ * Vectors can be nested - if a vector element has negative length, then -+ * the data pointer is treated as pointing to another vector array, with -+ * '-vec_len' elements. Thus to append a header onto an existing vector, -+ * you can do this: -+ * -+ * void foo(const VCHI_MSG_VECTOR_T *v, int n) -+ * { -+ * VCHI_MSG_VECTOR_T nv[2]; -+ * nv[0].vec_base = my_header; -+ * nv[0].vec_len = sizeof my_header; -+ * nv[1].vec_base = v; -+ * nv[1].vec_len = -n; -+ * ... -+ * -+ */ -+typedef struct vchi_msg_vector { -+ const void *vec_base; -+ int32_t vec_len; -+} VCHI_MSG_VECTOR_T; -+ -+// Opaque type for a connection API -+typedef struct opaque_vchi_connection_api_t VCHI_CONNECTION_API_T; -+ -+// Opaque type for a message driver -+typedef struct opaque_vchi_message_driver_t VCHI_MESSAGE_DRIVER_T; -+ -+ -+// Iterator structure for reading ahead through received message queue. Allocated by client, -+// initialised by vchi_msg_look_ahead. Fields are for internal VCHI use only. -+// Iterates over messages in queue at the instant of the call to vchi_msg_lookahead - -+// will not proceed to messages received since. Behaviour is undefined if an iterator -+// is used again after messages for that service are removed/dequeued by any -+// means other than vchi_msg_iter_... calls on the iterator itself. -+typedef struct { -+ struct opaque_vchi_service_t *service; -+ void *last; -+ void *next; -+ void *remove; -+} VCHI_MSG_ITER_T; -+ -+ -+#endif // VCHI_COMMON_H_ -diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchi/vchi.h linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi.h ---- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchi/vchi.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi.h 2015-11-29 09:42:38.059222273 +0100 -@@ -0,0 +1,378 @@ -+/** -+ * Copyright (c) 2010-2012 Broadcom. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef VCHI_H_ -+#define VCHI_H_ -+ -+#include "interface/vchi/vchi_cfg.h" -+#include "interface/vchi/vchi_common.h" -+#include "interface/vchi/connections/connection.h" -+#include "vchi_mh.h" -+ -+ -+/****************************************************************************** -+ Global defs -+ *****************************************************************************/ -+ -+#define VCHI_BULK_ROUND_UP(x) ((((unsigned long)(x))+VCHI_BULK_ALIGN-1) & ~(VCHI_BULK_ALIGN-1)) -+#define VCHI_BULK_ROUND_DOWN(x) (((unsigned long)(x)) & ~(VCHI_BULK_ALIGN-1)) -+#define VCHI_BULK_ALIGN_NBYTES(x) (VCHI_BULK_ALIGNED(x) ? 0 : (VCHI_BULK_ALIGN - ((unsigned long)(x) & (VCHI_BULK_ALIGN-1)))) -+ -+#ifdef USE_VCHIQ_ARM -+#define VCHI_BULK_ALIGNED(x) 1 -+#else -+#define VCHI_BULK_ALIGNED(x) (((unsigned long)(x) & (VCHI_BULK_ALIGN-1)) == 0) -+#endif -+ -+struct vchi_version { -+ uint32_t version; -+ uint32_t version_min; -+}; -+#define VCHI_VERSION(v_) { v_, v_ } -+#define VCHI_VERSION_EX(v_, m_) { v_, m_ } -+ -+typedef enum -+{ -+ VCHI_VEC_POINTER, -+ VCHI_VEC_HANDLE, -+ VCHI_VEC_LIST -+} VCHI_MSG_VECTOR_TYPE_T; -+ -+typedef struct vchi_msg_vector_ex { -+ -+ VCHI_MSG_VECTOR_TYPE_T type; -+ union -+ { -+ // a memory handle -+ struct -+ { -+ VCHI_MEM_HANDLE_T handle; -+ uint32_t offset; -+ int32_t vec_len; -+ } handle; -+ -+ // an ordinary data pointer -+ struct -+ { -+ const void *vec_base; -+ int32_t vec_len; -+ } ptr; -+ -+ // a nested vector list -+ struct -+ { -+ struct vchi_msg_vector_ex *vec; -+ uint32_t vec_len; -+ } list; -+ } u; -+} VCHI_MSG_VECTOR_EX_T; -+ -+ -+// Construct an entry in a msg vector for a pointer (p) of length (l) -+#define VCHI_VEC_POINTER(p,l) VCHI_VEC_POINTER, { { (VCHI_MEM_HANDLE_T)(p), (l) } } -+ -+// Construct an entry in a msg vector for a message handle (h), starting at offset (o) of length (l) -+#define VCHI_VEC_HANDLE(h,o,l) VCHI_VEC_HANDLE, { { (h), (o), (l) } } -+ -+// Macros to manipulate 'FOURCC' values -+#define MAKE_FOURCC(x) ((int32_t)( (x[0] << 24) | (x[1] << 16) | (x[2] << 8) | x[3] )) -+#define FOURCC_TO_CHAR(x) (x >> 24) & 0xFF,(x >> 16) & 0xFF,(x >> 8) & 0xFF, x & 0xFF -+ -+ -+// Opaque service information -+struct opaque_vchi_service_t; -+ -+// Descriptor for a held message. Allocated by client, initialised by vchi_msg_hold, -+// vchi_msg_iter_hold or vchi_msg_iter_hold_next. Fields are for internal VCHI use only. -+typedef struct -+{ -+ struct opaque_vchi_service_t *service; -+ void *message; -+} VCHI_HELD_MSG_T; -+ -+ -+ -+// structure used to provide the information needed to open a server or a client -+typedef struct { -+ struct vchi_version version; -+ int32_t service_id; -+ VCHI_CONNECTION_T *connection; -+ uint32_t rx_fifo_size; -+ uint32_t tx_fifo_size; -+ VCHI_CALLBACK_T callback; -+ void *callback_param; -+ /* client intends to receive bulk transfers of -+ odd lengths or into unaligned buffers */ -+ int32_t want_unaligned_bulk_rx; -+ /* client intends to transmit bulk transfers of -+ odd lengths or out of unaligned buffers */ -+ int32_t want_unaligned_bulk_tx; -+ /* client wants to check CRCs on (bulk) xfers. -+ Only needs to be set at 1 end - will do both directions. */ -+ int32_t want_crc; -+} SERVICE_CREATION_T; -+ -+// Opaque handle for a VCHI instance -+typedef struct opaque_vchi_instance_handle_t *VCHI_INSTANCE_T; -+ -+// Opaque handle for a server or client -+typedef struct opaque_vchi_service_handle_t *VCHI_SERVICE_HANDLE_T; -+ -+// Service registration & startup -+typedef void (*VCHI_SERVICE_INIT)(VCHI_INSTANCE_T initialise_instance, VCHI_CONNECTION_T **connections, uint32_t num_connections); -+ -+typedef struct service_info_tag { -+ const char * const vll_filename; /* VLL to load to start this service. This is an empty string if VLL is "static" */ -+ VCHI_SERVICE_INIT init; /* Service initialisation function */ -+ void *vll_handle; /* VLL handle; NULL when unloaded or a "static VLL" in build */ -+} SERVICE_INFO_T; -+ -+/****************************************************************************** -+ Global funcs - implementation is specific to which side you are on (local / remote) -+ *****************************************************************************/ -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+extern /*@observer@*/ VCHI_CONNECTION_T * vchi_create_connection( const VCHI_CONNECTION_API_T * function_table, -+ const VCHI_MESSAGE_DRIVER_T * low_level); -+ -+ -+// Routine used to initialise the vchi on both local + remote connections -+extern int32_t vchi_initialise( VCHI_INSTANCE_T *instance_handle ); -+ -+extern int32_t vchi_exit( void ); -+ -+extern int32_t vchi_connect( VCHI_CONNECTION_T **connections, -+ const uint32_t num_connections, -+ VCHI_INSTANCE_T instance_handle ); -+ -+//When this is called, ensure that all services have no data pending. -+//Bulk transfers can remain 'queued' -+extern int32_t vchi_disconnect( VCHI_INSTANCE_T instance_handle ); -+ -+// Global control over bulk CRC checking -+extern int32_t vchi_crc_control( VCHI_CONNECTION_T *connection, -+ VCHI_CRC_CONTROL_T control ); -+ -+// helper functions -+extern void * vchi_allocate_buffer(VCHI_SERVICE_HANDLE_T handle, uint32_t *length); -+extern void vchi_free_buffer(VCHI_SERVICE_HANDLE_T handle, void *address); -+extern uint32_t vchi_current_time(VCHI_INSTANCE_T instance_handle); -+ -+ -+/****************************************************************************** -+ Global service API -+ *****************************************************************************/ -+// Routine to create a named service -+extern int32_t vchi_service_create( VCHI_INSTANCE_T instance_handle, -+ SERVICE_CREATION_T *setup, -+ VCHI_SERVICE_HANDLE_T *handle ); -+ -+// Routine to destory a service -+extern int32_t vchi_service_destroy( const VCHI_SERVICE_HANDLE_T handle ); -+ -+// Routine to open a named service -+extern int32_t vchi_service_open( VCHI_INSTANCE_T instance_handle, -+ SERVICE_CREATION_T *setup, -+ VCHI_SERVICE_HANDLE_T *handle); -+ -+extern int32_t vchi_get_peer_version( const VCHI_SERVICE_HANDLE_T handle, -+ short *peer_version ); -+ -+// Routine to close a named service -+extern int32_t vchi_service_close( const VCHI_SERVICE_HANDLE_T handle ); -+ -+// Routine to increment ref count on a named service -+extern int32_t vchi_service_use( const VCHI_SERVICE_HANDLE_T handle ); -+ -+// Routine to decrement ref count on a named service -+extern int32_t vchi_service_release( const VCHI_SERVICE_HANDLE_T handle ); -+ -+// Routine to set a control option for a named service -+extern int32_t vchi_service_set_option( const VCHI_SERVICE_HANDLE_T handle, -+ VCHI_SERVICE_OPTION_T option, -+ int value); -+ -+// Routine to send a message across a service -+extern int32_t vchi_msg_queue( VCHI_SERVICE_HANDLE_T handle, -+ const void *data, -+ uint32_t data_size, -+ VCHI_FLAGS_T flags, -+ void *msg_handle ); -+ -+// scatter-gather (vector) and send message -+int32_t vchi_msg_queuev_ex( VCHI_SERVICE_HANDLE_T handle, -+ VCHI_MSG_VECTOR_EX_T *vector, -+ uint32_t count, -+ VCHI_FLAGS_T flags, -+ void *msg_handle ); -+ -+// legacy scatter-gather (vector) and send message, only handles pointers -+int32_t vchi_msg_queuev( VCHI_SERVICE_HANDLE_T handle, -+ VCHI_MSG_VECTOR_T *vector, -+ uint32_t count, -+ VCHI_FLAGS_T flags, -+ void *msg_handle ); -+ -+// Routine to receive a msg from a service -+// Dequeue is equivalent to hold, copy into client buffer, release -+extern int32_t vchi_msg_dequeue( VCHI_SERVICE_HANDLE_T handle, -+ void *data, -+ uint32_t max_data_size_to_read, -+ uint32_t *actual_msg_size, -+ VCHI_FLAGS_T flags ); -+ -+// Routine to look at a message in place. -+// The message is not dequeued, so a subsequent call to peek or dequeue -+// will return the same message. -+extern int32_t vchi_msg_peek( VCHI_SERVICE_HANDLE_T handle, -+ void **data, -+ uint32_t *msg_size, -+ VCHI_FLAGS_T flags ); -+ -+// Routine to remove a message after it has been read in place with peek -+// The first message on the queue is dequeued. -+extern int32_t vchi_msg_remove( VCHI_SERVICE_HANDLE_T handle ); -+ -+// Routine to look at a message in place. -+// The message is dequeued, so the caller is left holding it; the descriptor is -+// filled in and must be released when the user has finished with the message. -+extern int32_t vchi_msg_hold( VCHI_SERVICE_HANDLE_T handle, -+ void **data, // } may be NULL, as info can be -+ uint32_t *msg_size, // } obtained from HELD_MSG_T -+ VCHI_FLAGS_T flags, -+ VCHI_HELD_MSG_T *message_descriptor ); -+ -+// Initialise an iterator to look through messages in place -+extern int32_t vchi_msg_look_ahead( VCHI_SERVICE_HANDLE_T handle, -+ VCHI_MSG_ITER_T *iter, -+ VCHI_FLAGS_T flags ); -+ -+/****************************************************************************** -+ Global service support API - operations on held messages and message iterators -+ *****************************************************************************/ -+ -+// Routine to get the address of a held message -+extern void *vchi_held_msg_ptr( const VCHI_HELD_MSG_T *message ); -+ -+// Routine to get the size of a held message -+extern int32_t vchi_held_msg_size( const VCHI_HELD_MSG_T *message ); -+ -+// Routine to get the transmit timestamp as written into the header by the peer -+extern uint32_t vchi_held_msg_tx_timestamp( const VCHI_HELD_MSG_T *message ); -+ -+// Routine to get the reception timestamp, written as we parsed the header -+extern uint32_t vchi_held_msg_rx_timestamp( const VCHI_HELD_MSG_T *message ); -+ -+// Routine to release a held message after it has been processed -+extern int32_t vchi_held_msg_release( VCHI_HELD_MSG_T *message ); -+ -+// Indicates whether the iterator has a next message. -+extern int32_t vchi_msg_iter_has_next( const VCHI_MSG_ITER_T *iter ); -+ -+// Return the pointer and length for the next message and advance the iterator. -+extern int32_t vchi_msg_iter_next( VCHI_MSG_ITER_T *iter, -+ void **data, -+ uint32_t *msg_size ); -+ -+// Remove the last message returned by vchi_msg_iter_next. -+// Can only be called once after each call to vchi_msg_iter_next. -+extern int32_t vchi_msg_iter_remove( VCHI_MSG_ITER_T *iter ); -+ -+// Hold the last message returned by vchi_msg_iter_next. -+// Can only be called once after each call to vchi_msg_iter_next. -+extern int32_t vchi_msg_iter_hold( VCHI_MSG_ITER_T *iter, -+ VCHI_HELD_MSG_T *message ); -+ -+// Return information for the next message, and hold it, advancing the iterator. -+extern int32_t vchi_msg_iter_hold_next( VCHI_MSG_ITER_T *iter, -+ void **data, // } may be NULL -+ uint32_t *msg_size, // } -+ VCHI_HELD_MSG_T *message ); -+ -+ -+/****************************************************************************** -+ Global bulk API -+ *****************************************************************************/ -+ -+// Routine to prepare interface for a transfer from the other side -+extern int32_t vchi_bulk_queue_receive( VCHI_SERVICE_HANDLE_T handle, -+ void *data_dst, -+ uint32_t data_size, -+ VCHI_FLAGS_T flags, -+ void *transfer_handle ); -+ -+ -+// Prepare interface for a transfer from the other side into relocatable memory. -+int32_t vchi_bulk_queue_receive_reloc( const VCHI_SERVICE_HANDLE_T handle, -+ VCHI_MEM_HANDLE_T h_dst, -+ uint32_t offset, -+ uint32_t data_size, -+ const VCHI_FLAGS_T flags, -+ void * const bulk_handle ); -+ -+// Routine to queue up data ready for transfer to the other (once they have signalled they are ready) -+extern int32_t vchi_bulk_queue_transmit( VCHI_SERVICE_HANDLE_T handle, -+ const void *data_src, -+ uint32_t data_size, -+ VCHI_FLAGS_T flags, -+ void *transfer_handle ); -+ -+ -+/****************************************************************************** -+ Configuration plumbing -+ *****************************************************************************/ -+ -+// function prototypes for the different mid layers (the state info gives the different physical connections) -+extern const VCHI_CONNECTION_API_T *single_get_func_table( void ); -+//extern const VCHI_CONNECTION_API_T *local_server_get_func_table( void ); -+//extern const VCHI_CONNECTION_API_T *local_client_get_func_table( void ); -+ -+// declare all message drivers here -+const VCHI_MESSAGE_DRIVER_T *vchi_mphi_message_driver_func_table( void ); -+ -+#ifdef __cplusplus -+} -+#endif -+ -+extern int32_t vchi_bulk_queue_transmit_reloc( VCHI_SERVICE_HANDLE_T handle, -+ VCHI_MEM_HANDLE_T h_src, -+ uint32_t offset, -+ uint32_t data_size, -+ VCHI_FLAGS_T flags, -+ void *transfer_handle ); -+#endif /* VCHI_H_ */ -+ -+/****************************** End of file **********************************/ -diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchi/vchi_mh.h linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi_mh.h ---- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchi/vchi_mh.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi_mh.h 2015-11-29 09:42:38.059222273 +0100 -@@ -0,0 +1,42 @@ -+/** -+ * Copyright (c) 2010-2012 Broadcom. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef VCHI_MH_H_ -+#define VCHI_MH_H_ -+ -+#include -+ -+typedef int32_t VCHI_MEM_HANDLE_T; -+#define VCHI_MEM_HANDLE_INVALID 0 -+ -+#endif -diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c ---- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c 2015-11-29 09:42:38.059222273 +0100 -@@ -0,0 +1,580 @@ -+/** -+ * Copyright (c) 2010-2012 Broadcom. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define TOTAL_SLOTS (VCHIQ_SLOT_ZERO_SLOTS + 2 * 32) -+ -+#define VCHIQ_ARM_ADDRESS(x) ((void *)((char *)x + g_virt_to_bus_offset)) -+ -+#include "vchiq_arm.h" -+#include "vchiq_2835.h" -+#include "vchiq_connected.h" -+#include "vchiq_killable.h" -+ -+#define MAX_FRAGMENTS (VCHIQ_NUM_CURRENT_BULKS * 2) -+ -+#define BELL0 0x00 -+#define BELL2 0x08 -+ -+typedef struct vchiq_2835_state_struct { -+ int inited; -+ VCHIQ_ARM_STATE_T arm_state; -+} VCHIQ_2835_ARM_STATE_T; -+ -+static void __iomem *g_regs; -+static unsigned int g_cache_line_size = sizeof(CACHE_LINE_SIZE); -+static unsigned int g_fragments_size; -+static char *g_fragments_base; -+static char *g_free_fragments; -+static struct semaphore g_free_fragments_sema; -+static unsigned long g_virt_to_bus_offset; -+ -+extern int vchiq_arm_log_level; -+ -+static DEFINE_SEMAPHORE(g_free_fragments_mutex); -+ -+static irqreturn_t -+vchiq_doorbell_irq(int irq, void *dev_id); -+ -+static int -+create_pagelist(char __user *buf, size_t count, unsigned short type, -+ struct task_struct *task, PAGELIST_T ** ppagelist); -+ -+static void -+free_pagelist(PAGELIST_T *pagelist, int actual); -+ -+int vchiq_platform_init(struct platform_device *pdev, VCHIQ_STATE_T *state) -+{ -+ struct device *dev = &pdev->dev; -+ struct rpi_firmware *fw = platform_get_drvdata(pdev); -+ VCHIQ_SLOT_ZERO_T *vchiq_slot_zero; -+ struct resource *res; -+ void *slot_mem; -+ dma_addr_t slot_phys; -+ u32 channelbase; -+ int slot_mem_size, frag_mem_size; -+ int err, irq, i; -+ -+ g_virt_to_bus_offset = virt_to_dma(dev, (void *)0); -+ -+ (void)of_property_read_u32(dev->of_node, "cache-line-size", -+ &g_cache_line_size); -+ g_fragments_size = 2 * g_cache_line_size; -+ -+ /* Allocate space for the channels in coherent memory */ -+ slot_mem_size = PAGE_ALIGN(TOTAL_SLOTS * VCHIQ_SLOT_SIZE); -+ frag_mem_size = PAGE_ALIGN(g_fragments_size * MAX_FRAGMENTS); -+ -+ slot_mem = dmam_alloc_coherent(dev, slot_mem_size + frag_mem_size, -+ &slot_phys, GFP_KERNEL); -+ if (!slot_mem) { -+ dev_err(dev, "could not allocate DMA memory\n"); -+ return -ENOMEM; -+ } -+ -+ WARN_ON(((int)slot_mem & (PAGE_SIZE - 1)) != 0); -+ -+ vchiq_slot_zero = vchiq_init_slots(slot_mem, slot_mem_size); -+ if (!vchiq_slot_zero) -+ return -EINVAL; -+ -+ vchiq_slot_zero->platform_data[VCHIQ_PLATFORM_FRAGMENTS_OFFSET_IDX] = -+ (int)slot_phys + slot_mem_size; -+ vchiq_slot_zero->platform_data[VCHIQ_PLATFORM_FRAGMENTS_COUNT_IDX] = -+ MAX_FRAGMENTS; -+ -+ g_fragments_base = (char *)slot_mem + slot_mem_size; -+ slot_mem_size += frag_mem_size; -+ -+ g_free_fragments = g_fragments_base; -+ for (i = 0; i < (MAX_FRAGMENTS - 1); i++) { -+ *(char **)&g_fragments_base[i*g_fragments_size] = -+ &g_fragments_base[(i + 1)*g_fragments_size]; -+ } -+ *(char **)&g_fragments_base[i * g_fragments_size] = NULL; -+ sema_init(&g_free_fragments_sema, MAX_FRAGMENTS); -+ -+ if (vchiq_init_state(state, vchiq_slot_zero, 0) != VCHIQ_SUCCESS) -+ return -EINVAL; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ g_regs = devm_ioremap_resource(&pdev->dev, res); -+ if (IS_ERR(g_regs)) -+ return PTR_ERR(g_regs); -+ -+ irq = platform_get_irq(pdev, 0); -+ if (irq <= 0) { -+ dev_err(dev, "failed to get IRQ\n"); -+ return irq; -+ } -+ -+ err = devm_request_irq(dev, irq, vchiq_doorbell_irq, IRQF_IRQPOLL, -+ "VCHIQ doorbell", state); -+ if (err) { -+ dev_err(dev, "failed to register irq=%d\n", irq); -+ return err; -+ } -+ -+ /* Send the base address of the slots to VideoCore */ -+ channelbase = slot_phys; -+ err = rpi_firmware_property(fw, RPI_FIRMWARE_VCHIQ_INIT, -+ &channelbase, sizeof(channelbase)); -+ if (err || channelbase) { -+ dev_err(dev, "failed to set channelbase\n"); -+ return err ? : -ENXIO; -+ } -+ -+ vchiq_log_info(vchiq_arm_log_level, -+ "vchiq_init - done (slots %x, phys %pad)", -+ (unsigned int)vchiq_slot_zero, &slot_phys); -+ -+ vchiq_call_connected_callbacks(); -+ -+ return 0; -+} -+ -+VCHIQ_STATUS_T -+vchiq_platform_init_state(VCHIQ_STATE_T *state) -+{ -+ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; -+ state->platform_state = kzalloc(sizeof(VCHIQ_2835_ARM_STATE_T), GFP_KERNEL); -+ ((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->inited = 1; -+ status = vchiq_arm_init_state(state, &((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->arm_state); -+ if(status != VCHIQ_SUCCESS) -+ { -+ ((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->inited = 0; -+ } -+ return status; -+} -+ -+VCHIQ_ARM_STATE_T* -+vchiq_platform_get_arm_state(VCHIQ_STATE_T *state) -+{ -+ if(!((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->inited) -+ { -+ BUG(); -+ } -+ return &((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->arm_state; -+} -+ -+void -+remote_event_signal(REMOTE_EVENT_T *event) -+{ -+ wmb(); -+ -+ event->fired = 1; -+ -+ dsb(); /* data barrier operation */ -+ -+ if (event->armed) -+ writel(0, g_regs + BELL2); /* trigger vc interrupt */ -+} -+ -+int -+vchiq_copy_from_user(void *dst, const void *src, int size) -+{ -+ if ((uint32_t)src < TASK_SIZE) { -+ return copy_from_user(dst, src, size); -+ } else { -+ memcpy(dst, src, size); -+ return 0; -+ } -+} -+ -+VCHIQ_STATUS_T -+vchiq_prepare_bulk_data(VCHIQ_BULK_T *bulk, VCHI_MEM_HANDLE_T memhandle, -+ void *offset, int size, int dir) -+{ -+ PAGELIST_T *pagelist; -+ int ret; -+ -+ WARN_ON(memhandle != VCHI_MEM_HANDLE_INVALID); -+ -+ ret = create_pagelist((char __user *)offset, size, -+ (dir == VCHIQ_BULK_RECEIVE) -+ ? PAGELIST_READ -+ : PAGELIST_WRITE, -+ current, -+ &pagelist); -+ if (ret != 0) -+ return VCHIQ_ERROR; -+ -+ bulk->handle = memhandle; -+ bulk->data = VCHIQ_ARM_ADDRESS(pagelist); -+ -+ /* Store the pagelist address in remote_data, which isn't used by the -+ slave. */ -+ bulk->remote_data = pagelist; -+ -+ return VCHIQ_SUCCESS; -+} -+ -+void -+vchiq_complete_bulk(VCHIQ_BULK_T *bulk) -+{ -+ if (bulk && bulk->remote_data && bulk->actual) -+ free_pagelist((PAGELIST_T *)bulk->remote_data, bulk->actual); -+} -+ -+void -+vchiq_transfer_bulk(VCHIQ_BULK_T *bulk) -+{ -+ /* -+ * This should only be called on the master (VideoCore) side, but -+ * provide an implementation to avoid the need for ifdefery. -+ */ -+ BUG(); -+} -+ -+void -+vchiq_dump_platform_state(void *dump_context) -+{ -+ char buf[80]; -+ int len; -+ len = snprintf(buf, sizeof(buf), -+ " Platform: 2835 (VC master)"); -+ vchiq_dump(dump_context, buf, len + 1); -+} -+ -+VCHIQ_STATUS_T -+vchiq_platform_suspend(VCHIQ_STATE_T *state) -+{ -+ return VCHIQ_ERROR; -+} -+ -+VCHIQ_STATUS_T -+vchiq_platform_resume(VCHIQ_STATE_T *state) -+{ -+ return VCHIQ_SUCCESS; -+} -+ -+void -+vchiq_platform_paused(VCHIQ_STATE_T *state) -+{ -+} -+ -+void -+vchiq_platform_resumed(VCHIQ_STATE_T *state) -+{ -+} -+ -+int -+vchiq_platform_videocore_wanted(VCHIQ_STATE_T* state) -+{ -+ return 1; // autosuspend not supported - videocore always wanted -+} -+ -+int -+vchiq_platform_use_suspend_timer(void) -+{ -+ return 0; -+} -+void -+vchiq_dump_platform_use_state(VCHIQ_STATE_T *state) -+{ -+ vchiq_log_info(vchiq_arm_log_level, "Suspend timer not in use"); -+} -+void -+vchiq_platform_handle_timeout(VCHIQ_STATE_T *state) -+{ -+ (void)state; -+} -+/* -+ * Local functions -+ */ -+ -+static irqreturn_t -+vchiq_doorbell_irq(int irq, void *dev_id) -+{ -+ VCHIQ_STATE_T *state = dev_id; -+ irqreturn_t ret = IRQ_NONE; -+ unsigned int status; -+ -+ /* Read (and clear) the doorbell */ -+ status = readl(g_regs + BELL0); -+ -+ if (status & 0x4) { /* Was the doorbell rung? */ -+ remote_event_pollall(state); -+ ret = IRQ_HANDLED; -+ } -+ -+ return ret; -+} -+ -+/* There is a potential problem with partial cache lines (pages?) -+** at the ends of the block when reading. If the CPU accessed anything in -+** the same line (page?) then it may have pulled old data into the cache, -+** obscuring the new data underneath. We can solve this by transferring the -+** partial cache lines separately, and allowing the ARM to copy into the -+** cached area. -+ -+** N.B. This implementation plays slightly fast and loose with the Linux -+** driver programming rules, e.g. its use of dmac_map_area instead of -+** dma_map_single, but it isn't a multi-platform driver and it benefits -+** from increased speed as a result. -+*/ -+ -+static int -+create_pagelist(char __user *buf, size_t count, unsigned short type, -+ struct task_struct *task, PAGELIST_T ** ppagelist) -+{ -+ PAGELIST_T *pagelist; -+ struct page **pages; -+ unsigned long *addrs; -+ unsigned int num_pages, offset, i; -+ char *addr, *base_addr, *next_addr; -+ int run, addridx, actual_pages; -+ unsigned long *need_release; -+ -+ offset = (unsigned int)buf & (PAGE_SIZE - 1); -+ num_pages = (count + offset + PAGE_SIZE - 1) / PAGE_SIZE; -+ -+ *ppagelist = NULL; -+ -+ /* Allocate enough storage to hold the page pointers and the page -+ ** list -+ */ -+ pagelist = kmalloc(sizeof(PAGELIST_T) + -+ (num_pages * sizeof(unsigned long)) + -+ sizeof(unsigned long) + -+ (num_pages * sizeof(pages[0])), -+ GFP_KERNEL); -+ -+ vchiq_log_trace(vchiq_arm_log_level, -+ "create_pagelist - %x", (unsigned int)pagelist); -+ if (!pagelist) -+ return -ENOMEM; -+ -+ addrs = pagelist->addrs; -+ need_release = (unsigned long *)(addrs + num_pages); -+ pages = (struct page **)(addrs + num_pages + 1); -+ -+ if (is_vmalloc_addr(buf)) { -+ int dir = (type == PAGELIST_WRITE) ? -+ DMA_TO_DEVICE : DMA_FROM_DEVICE; -+ unsigned long length = count; -+ unsigned int off = offset; -+ -+ for (actual_pages = 0; actual_pages < num_pages; -+ actual_pages++) { -+ struct page *pg = vmalloc_to_page(buf + (actual_pages * -+ PAGE_SIZE)); -+ size_t bytes = PAGE_SIZE - off; -+ -+ if (bytes > length) -+ bytes = length; -+ pages[actual_pages] = pg; -+ dmac_map_area(page_address(pg) + off, bytes, dir); -+ length -= bytes; -+ off = 0; -+ } -+ *need_release = 0; /* do not try and release vmalloc pages */ -+ } else { -+ down_read(&task->mm->mmap_sem); -+ actual_pages = get_user_pages(task, task->mm, -+ (unsigned long)buf & ~(PAGE_SIZE - 1), -+ num_pages, -+ (type == PAGELIST_READ) /*Write */ , -+ 0 /*Force */ , -+ pages, -+ NULL /*vmas */); -+ up_read(&task->mm->mmap_sem); -+ -+ if (actual_pages != num_pages) { -+ vchiq_log_info(vchiq_arm_log_level, -+ "create_pagelist - only %d/%d pages locked", -+ actual_pages, -+ num_pages); -+ -+ /* This is probably due to the process being killed */ -+ while (actual_pages > 0) -+ { -+ actual_pages--; -+ page_cache_release(pages[actual_pages]); -+ } -+ kfree(pagelist); -+ if (actual_pages == 0) -+ actual_pages = -ENOMEM; -+ return actual_pages; -+ } -+ *need_release = 1; /* release user pages */ -+ } -+ -+ pagelist->length = count; -+ pagelist->type = type; -+ pagelist->offset = offset; -+ -+ /* Group the pages into runs of contiguous pages */ -+ -+ base_addr = VCHIQ_ARM_ADDRESS(page_address(pages[0])); -+ next_addr = base_addr + PAGE_SIZE; -+ addridx = 0; -+ run = 0; -+ -+ for (i = 1; i < num_pages; i++) { -+ addr = VCHIQ_ARM_ADDRESS(page_address(pages[i])); -+ if ((addr == next_addr) && (run < (PAGE_SIZE - 1))) { -+ next_addr += PAGE_SIZE; -+ run++; -+ } else { -+ addrs[addridx] = (unsigned long)base_addr + run; -+ addridx++; -+ base_addr = addr; -+ next_addr = addr + PAGE_SIZE; -+ run = 0; -+ } -+ } -+ -+ addrs[addridx] = (unsigned long)base_addr + run; -+ addridx++; -+ -+ /* Partial cache lines (fragments) require special measures */ -+ if ((type == PAGELIST_READ) && -+ ((pagelist->offset & (g_cache_line_size - 1)) || -+ ((pagelist->offset + pagelist->length) & -+ (g_cache_line_size - 1)))) { -+ char *fragments; -+ -+ if (down_interruptible(&g_free_fragments_sema) != 0) { -+ kfree(pagelist); -+ return -EINTR; -+ } -+ -+ WARN_ON(g_free_fragments == NULL); -+ -+ down(&g_free_fragments_mutex); -+ fragments = g_free_fragments; -+ WARN_ON(fragments == NULL); -+ g_free_fragments = *(char **) g_free_fragments; -+ up(&g_free_fragments_mutex); -+ pagelist->type = PAGELIST_READ_WITH_FRAGMENTS + -+ (fragments - g_fragments_base) / g_fragments_size; -+ } -+ -+ dmac_flush_range(pagelist, addrs + num_pages); -+ -+ *ppagelist = pagelist; -+ -+ return 0; -+} -+ -+static void -+free_pagelist(PAGELIST_T *pagelist, int actual) -+{ -+ unsigned long *need_release; -+ struct page **pages; -+ unsigned int num_pages, i; -+ -+ vchiq_log_trace(vchiq_arm_log_level, -+ "free_pagelist - %x, %d", (unsigned int)pagelist, actual); -+ -+ num_pages = -+ (pagelist->length + pagelist->offset + PAGE_SIZE - 1) / -+ PAGE_SIZE; -+ -+ need_release = (unsigned long *)(pagelist->addrs + num_pages); -+ pages = (struct page **)(pagelist->addrs + num_pages + 1); -+ -+ /* Deal with any partial cache lines (fragments) */ -+ if (pagelist->type >= PAGELIST_READ_WITH_FRAGMENTS) { -+ char *fragments = g_fragments_base + -+ (pagelist->type - PAGELIST_READ_WITH_FRAGMENTS) * -+ g_fragments_size; -+ int head_bytes, tail_bytes; -+ head_bytes = (g_cache_line_size - pagelist->offset) & -+ (g_cache_line_size - 1); -+ tail_bytes = (pagelist->offset + actual) & -+ (g_cache_line_size - 1); -+ -+ if ((actual >= 0) && (head_bytes != 0)) { -+ if (head_bytes > actual) -+ head_bytes = actual; -+ -+ memcpy((char *)page_address(pages[0]) + -+ pagelist->offset, -+ fragments, -+ head_bytes); -+ } -+ if ((actual >= 0) && (head_bytes < actual) && -+ (tail_bytes != 0)) { -+ memcpy((char *)page_address(pages[num_pages - 1]) + -+ ((pagelist->offset + actual) & -+ (PAGE_SIZE - 1) & ~(g_cache_line_size - 1)), -+ fragments + g_cache_line_size, -+ tail_bytes); -+ } -+ -+ down(&g_free_fragments_mutex); -+ *(char **)fragments = g_free_fragments; -+ g_free_fragments = fragments; -+ up(&g_free_fragments_mutex); -+ up(&g_free_fragments_sema); -+ } -+ -+ if (*need_release) { -+ unsigned int length = pagelist->length; -+ unsigned int offset = pagelist->offset; -+ -+ for (i = 0; i < num_pages; i++) { -+ struct page *pg = pages[i]; -+ -+ if (pagelist->type != PAGELIST_WRITE) { -+ unsigned int bytes = PAGE_SIZE - offset; -+ -+ if (bytes > length) -+ bytes = length; -+ dmac_unmap_area(page_address(pg) + offset, -+ bytes, DMA_FROM_DEVICE); -+ length -= bytes; -+ offset = 0; -+ set_page_dirty(pg); -+ } -+ page_cache_release(pg); -+ } -+ } -+ -+ kfree(pagelist); -+} -diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835.h ---- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835.h 2015-11-29 09:42:38.059222273 +0100 -@@ -0,0 +1,42 @@ -+/** -+ * Copyright (c) 2010-2012 Broadcom. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef VCHIQ_2835_H -+#define VCHIQ_2835_H -+ -+#include "vchiq_pagelist.h" -+ -+#define VCHIQ_PLATFORM_FRAGMENTS_OFFSET_IDX 0 -+#define VCHIQ_PLATFORM_FRAGMENTS_COUNT_IDX 1 -+ -+#endif /* VCHIQ_2835_H */ -diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c ---- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c 2015-11-29 09:42:38.071221476 +0100 -@@ -0,0 +1,2903 @@ -+/** -+ * Copyright (c) 2014 Raspberry Pi (Trading) Ltd. All rights reserved. -+ * Copyright (c) 2010-2012 Broadcom. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "vchiq_core.h" -+#include "vchiq_ioctl.h" -+#include "vchiq_arm.h" -+#include "vchiq_debugfs.h" -+#include "vchiq_killable.h" -+ -+#define DEVICE_NAME "vchiq" -+ -+/* Override the default prefix, which would be vchiq_arm (from the filename) */ -+#undef MODULE_PARAM_PREFIX -+#define MODULE_PARAM_PREFIX DEVICE_NAME "." -+ -+#define VCHIQ_MINOR 0 -+ -+/* Some per-instance constants */ -+#define MAX_COMPLETIONS 16 -+#define MAX_SERVICES 64 -+#define MAX_ELEMENTS 8 -+#define MSG_QUEUE_SIZE 64 -+ -+#define KEEPALIVE_VER 1 -+#define KEEPALIVE_VER_MIN KEEPALIVE_VER -+ -+/* Run time control of log level, based on KERN_XXX level. */ -+int vchiq_arm_log_level = VCHIQ_LOG_DEFAULT; -+int vchiq_susp_log_level = VCHIQ_LOG_ERROR; -+ -+#define SUSPEND_TIMER_TIMEOUT_MS 100 -+#define SUSPEND_RETRY_TIMER_TIMEOUT_MS 1000 -+ -+#define VC_SUSPEND_NUM_OFFSET 3 /* number of values before idle which are -ve */ -+static const char *const suspend_state_names[] = { -+ "VC_SUSPEND_FORCE_CANCELED", -+ "VC_SUSPEND_REJECTED", -+ "VC_SUSPEND_FAILED", -+ "VC_SUSPEND_IDLE", -+ "VC_SUSPEND_REQUESTED", -+ "VC_SUSPEND_IN_PROGRESS", -+ "VC_SUSPEND_SUSPENDED" -+}; -+#define VC_RESUME_NUM_OFFSET 1 /* number of values before idle which are -ve */ -+static const char *const resume_state_names[] = { -+ "VC_RESUME_FAILED", -+ "VC_RESUME_IDLE", -+ "VC_RESUME_REQUESTED", -+ "VC_RESUME_IN_PROGRESS", -+ "VC_RESUME_RESUMED" -+}; -+/* The number of times we allow force suspend to timeout before actually -+** _forcing_ suspend. This is to cater for SW which fails to release vchiq -+** correctly - we don't want to prevent ARM suspend indefinitely in this case. -+*/ -+#define FORCE_SUSPEND_FAIL_MAX 8 -+ -+/* The time in ms allowed for videocore to go idle when force suspend has been -+ * requested */ -+#define FORCE_SUSPEND_TIMEOUT_MS 200 -+ -+ -+static void suspend_timer_callback(unsigned long context); -+ -+ -+typedef struct user_service_struct { -+ VCHIQ_SERVICE_T *service; -+ void *userdata; -+ VCHIQ_INSTANCE_T instance; -+ char is_vchi; -+ char dequeue_pending; -+ char close_pending; -+ int message_available_pos; -+ int msg_insert; -+ int msg_remove; -+ struct semaphore insert_event; -+ struct semaphore remove_event; -+ struct semaphore close_event; -+ VCHIQ_HEADER_T * msg_queue[MSG_QUEUE_SIZE]; -+} USER_SERVICE_T; -+ -+struct bulk_waiter_node { -+ struct bulk_waiter bulk_waiter; -+ int pid; -+ struct list_head list; -+}; -+ -+struct vchiq_instance_struct { -+ VCHIQ_STATE_T *state; -+ VCHIQ_COMPLETION_DATA_T completions[MAX_COMPLETIONS]; -+ int completion_insert; -+ int completion_remove; -+ struct semaphore insert_event; -+ struct semaphore remove_event; -+ struct mutex completion_mutex; -+ -+ int connected; -+ int closing; -+ int pid; -+ int mark; -+ int use_close_delivered; -+ int trace; -+ -+ struct list_head bulk_waiter_list; -+ struct mutex bulk_waiter_list_mutex; -+ -+ VCHIQ_DEBUGFS_NODE_T debugfs_node; -+}; -+ -+typedef struct dump_context_struct { -+ char __user *buf; -+ size_t actual; -+ size_t space; -+ loff_t offset; -+} DUMP_CONTEXT_T; -+ -+static struct cdev vchiq_cdev; -+static dev_t vchiq_devid; -+static VCHIQ_STATE_T g_state; -+static struct class *vchiq_class; -+static struct device *vchiq_dev; -+static DEFINE_SPINLOCK(msg_queue_spinlock); -+ -+static const char *const ioctl_names[] = { -+ "CONNECT", -+ "SHUTDOWN", -+ "CREATE_SERVICE", -+ "REMOVE_SERVICE", -+ "QUEUE_MESSAGE", -+ "QUEUE_BULK_TRANSMIT", -+ "QUEUE_BULK_RECEIVE", -+ "AWAIT_COMPLETION", -+ "DEQUEUE_MESSAGE", -+ "GET_CLIENT_ID", -+ "GET_CONFIG", -+ "CLOSE_SERVICE", -+ "USE_SERVICE", -+ "RELEASE_SERVICE", -+ "SET_SERVICE_OPTION", -+ "DUMP_PHYS_MEM", -+ "LIB_VERSION", -+ "CLOSE_DELIVERED" -+}; -+ -+vchiq_static_assert((sizeof(ioctl_names)/sizeof(ioctl_names[0])) == -+ (VCHIQ_IOC_MAX + 1)); -+ -+static void -+dump_phys_mem(void *virt_addr, uint32_t num_bytes); -+ -+/**************************************************************************** -+* -+* add_completion -+* -+***************************************************************************/ -+ -+static VCHIQ_STATUS_T -+add_completion(VCHIQ_INSTANCE_T instance, VCHIQ_REASON_T reason, -+ VCHIQ_HEADER_T *header, USER_SERVICE_T *user_service, -+ void *bulk_userdata) -+{ -+ VCHIQ_COMPLETION_DATA_T *completion; -+ DEBUG_INITIALISE(g_state.local) -+ -+ while (instance->completion_insert == -+ (instance->completion_remove + MAX_COMPLETIONS)) { -+ /* Out of space - wait for the client */ -+ DEBUG_TRACE(SERVICE_CALLBACK_LINE); -+ vchiq_log_trace(vchiq_arm_log_level, -+ "add_completion - completion queue full"); -+ DEBUG_COUNT(COMPLETION_QUEUE_FULL_COUNT); -+ if (down_interruptible(&instance->remove_event) != 0) { -+ vchiq_log_info(vchiq_arm_log_level, -+ "service_callback interrupted"); -+ return VCHIQ_RETRY; -+ } else if (instance->closing) { -+ vchiq_log_info(vchiq_arm_log_level, -+ "service_callback closing"); -+ return VCHIQ_ERROR; -+ } -+ DEBUG_TRACE(SERVICE_CALLBACK_LINE); -+ } -+ -+ completion = -+ &instance->completions[instance->completion_insert & -+ (MAX_COMPLETIONS - 1)]; -+ -+ completion->header = header; -+ completion->reason = reason; -+ /* N.B. service_userdata is updated while processing AWAIT_COMPLETION */ -+ completion->service_userdata = user_service->service; -+ completion->bulk_userdata = bulk_userdata; -+ -+ if (reason == VCHIQ_SERVICE_CLOSED) { -+ /* Take an extra reference, to be held until -+ this CLOSED notification is delivered. */ -+ lock_service(user_service->service); -+ if (instance->use_close_delivered) -+ user_service->close_pending = 1; -+ } -+ -+ /* A write barrier is needed here to ensure that the entire completion -+ record is written out before the insert point. */ -+ wmb(); -+ -+ if (reason == VCHIQ_MESSAGE_AVAILABLE) -+ user_service->message_available_pos = -+ instance->completion_insert; -+ instance->completion_insert++; -+ -+ up(&instance->insert_event); -+ -+ return VCHIQ_SUCCESS; -+} -+ -+/**************************************************************************** -+* -+* service_callback -+* -+***************************************************************************/ -+ -+static VCHIQ_STATUS_T -+service_callback(VCHIQ_REASON_T reason, VCHIQ_HEADER_T *header, -+ VCHIQ_SERVICE_HANDLE_T handle, void *bulk_userdata) -+{ -+ /* How do we ensure the callback goes to the right client? -+ ** The service_user data points to a USER_SERVICE_T record containing -+ ** the original callback and the user state structure, which contains a -+ ** circular buffer for completion records. -+ */ -+ USER_SERVICE_T *user_service; -+ VCHIQ_SERVICE_T *service; -+ VCHIQ_INSTANCE_T instance; -+ DEBUG_INITIALISE(g_state.local) -+ -+ DEBUG_TRACE(SERVICE_CALLBACK_LINE); -+ -+ service = handle_to_service(handle); -+ BUG_ON(!service); -+ user_service = (USER_SERVICE_T *)service->base.userdata; -+ instance = user_service->instance; -+ -+ if (!instance || instance->closing) -+ return VCHIQ_SUCCESS; -+ -+ vchiq_log_trace(vchiq_arm_log_level, -+ "service_callback - service %lx(%d,%p), reason %d, header %lx, " -+ "instance %lx, bulk_userdata %lx", -+ (unsigned long)user_service, -+ service->localport, user_service->userdata, -+ reason, (unsigned long)header, -+ (unsigned long)instance, (unsigned long)bulk_userdata); -+ -+ if (header && user_service->is_vchi) { -+ spin_lock(&msg_queue_spinlock); -+ while (user_service->msg_insert == -+ (user_service->msg_remove + MSG_QUEUE_SIZE)) { -+ spin_unlock(&msg_queue_spinlock); -+ DEBUG_TRACE(SERVICE_CALLBACK_LINE); -+ DEBUG_COUNT(MSG_QUEUE_FULL_COUNT); -+ vchiq_log_trace(vchiq_arm_log_level, -+ "service_callback - msg queue full"); -+ /* If there is no MESSAGE_AVAILABLE in the completion -+ ** queue, add one -+ */ -+ if ((user_service->message_available_pos - -+ instance->completion_remove) < 0) { -+ VCHIQ_STATUS_T status; -+ vchiq_log_info(vchiq_arm_log_level, -+ "Inserting extra MESSAGE_AVAILABLE"); -+ DEBUG_TRACE(SERVICE_CALLBACK_LINE); -+ status = add_completion(instance, reason, -+ NULL, user_service, bulk_userdata); -+ if (status != VCHIQ_SUCCESS) { -+ DEBUG_TRACE(SERVICE_CALLBACK_LINE); -+ return status; -+ } -+ } -+ -+ DEBUG_TRACE(SERVICE_CALLBACK_LINE); -+ if (down_interruptible(&user_service->remove_event) -+ != 0) { -+ vchiq_log_info(vchiq_arm_log_level, -+ "service_callback interrupted"); -+ DEBUG_TRACE(SERVICE_CALLBACK_LINE); -+ return VCHIQ_RETRY; -+ } else if (instance->closing) { -+ vchiq_log_info(vchiq_arm_log_level, -+ "service_callback closing"); -+ DEBUG_TRACE(SERVICE_CALLBACK_LINE); -+ return VCHIQ_ERROR; -+ } -+ DEBUG_TRACE(SERVICE_CALLBACK_LINE); -+ spin_lock(&msg_queue_spinlock); -+ } -+ -+ user_service->msg_queue[user_service->msg_insert & -+ (MSG_QUEUE_SIZE - 1)] = header; -+ user_service->msg_insert++; -+ spin_unlock(&msg_queue_spinlock); -+ -+ up(&user_service->insert_event); -+ -+ /* If there is a thread waiting in DEQUEUE_MESSAGE, or if -+ ** there is a MESSAGE_AVAILABLE in the completion queue then -+ ** bypass the completion queue. -+ */ -+ if (((user_service->message_available_pos - -+ instance->completion_remove) >= 0) || -+ user_service->dequeue_pending) { -+ DEBUG_TRACE(SERVICE_CALLBACK_LINE); -+ user_service->dequeue_pending = 0; -+ return VCHIQ_SUCCESS; -+ } -+ -+ header = NULL; -+ } -+ DEBUG_TRACE(SERVICE_CALLBACK_LINE); -+ -+ return add_completion(instance, reason, header, user_service, -+ bulk_userdata); -+} -+ -+/**************************************************************************** -+* -+* user_service_free -+* -+***************************************************************************/ -+static void -+user_service_free(void *userdata) -+{ -+ kfree(userdata); -+} -+ -+/**************************************************************************** -+* -+* close_delivered -+* -+***************************************************************************/ -+static void close_delivered(USER_SERVICE_T *user_service) -+{ -+ vchiq_log_info(vchiq_arm_log_level, -+ "close_delivered(handle=%x)", -+ user_service->service->handle); -+ -+ if (user_service->close_pending) { -+ /* Allow the underlying service to be culled */ -+ unlock_service(user_service->service); -+ -+ /* Wake the user-thread blocked in close_ or remove_service */ -+ up(&user_service->close_event); -+ -+ user_service->close_pending = 0; -+ } -+} -+ -+/**************************************************************************** -+* -+* vchiq_ioctl -+* -+***************************************************************************/ -+static long -+vchiq_ioctl(struct file *file, unsigned int cmd, unsigned long arg) -+{ -+ VCHIQ_INSTANCE_T instance = file->private_data; -+ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; -+ VCHIQ_SERVICE_T *service = NULL; -+ long ret = 0; -+ int i, rc; -+ DEBUG_INITIALISE(g_state.local) -+ -+ vchiq_log_trace(vchiq_arm_log_level, -+ "vchiq_ioctl - instance %x, cmd %s, arg %lx", -+ (unsigned int)instance, -+ ((_IOC_TYPE(cmd) == VCHIQ_IOC_MAGIC) && -+ (_IOC_NR(cmd) <= VCHIQ_IOC_MAX)) ? -+ ioctl_names[_IOC_NR(cmd)] : "", arg); -+ -+ switch (cmd) { -+ case VCHIQ_IOC_SHUTDOWN: -+ if (!instance->connected) -+ break; -+ -+ /* Remove all services */ -+ i = 0; -+ while ((service = next_service_by_instance(instance->state, -+ instance, &i)) != NULL) { -+ status = vchiq_remove_service(service->handle); -+ unlock_service(service); -+ if (status != VCHIQ_SUCCESS) -+ break; -+ } -+ service = NULL; -+ -+ if (status == VCHIQ_SUCCESS) { -+ /* Wake the completion thread and ask it to exit */ -+ instance->closing = 1; -+ up(&instance->insert_event); -+ } -+ -+ break; -+ -+ case VCHIQ_IOC_CONNECT: -+ if (instance->connected) { -+ ret = -EINVAL; -+ break; -+ } -+ rc = mutex_lock_interruptible(&instance->state->mutex); -+ if (rc != 0) { -+ vchiq_log_error(vchiq_arm_log_level, -+ "vchiq: connect: could not lock mutex for " -+ "state %d: %d", -+ instance->state->id, rc); -+ ret = -EINTR; -+ break; -+ } -+ status = vchiq_connect_internal(instance->state, instance); -+ mutex_unlock(&instance->state->mutex); -+ -+ if (status == VCHIQ_SUCCESS) -+ instance->connected = 1; -+ else -+ vchiq_log_error(vchiq_arm_log_level, -+ "vchiq: could not connect: %d", status); -+ break; -+ -+ case VCHIQ_IOC_CREATE_SERVICE: { -+ VCHIQ_CREATE_SERVICE_T args; -+ USER_SERVICE_T *user_service = NULL; -+ void *userdata; -+ int srvstate; -+ -+ if (copy_from_user -+ (&args, (const void __user *)arg, -+ sizeof(args)) != 0) { -+ ret = -EFAULT; -+ break; -+ } -+ -+ user_service = kmalloc(sizeof(USER_SERVICE_T), GFP_KERNEL); -+ if (!user_service) { -+ ret = -ENOMEM; -+ break; -+ } -+ -+ if (args.is_open) { -+ if (!instance->connected) { -+ ret = -ENOTCONN; -+ kfree(user_service); -+ break; -+ } -+ srvstate = VCHIQ_SRVSTATE_OPENING; -+ } else { -+ srvstate = -+ instance->connected ? -+ VCHIQ_SRVSTATE_LISTENING : -+ VCHIQ_SRVSTATE_HIDDEN; -+ } -+ -+ userdata = args.params.userdata; -+ args.params.callback = service_callback; -+ args.params.userdata = user_service; -+ service = vchiq_add_service_internal( -+ instance->state, -+ &args.params, srvstate, -+ instance, user_service_free); -+ -+ if (service != NULL) { -+ user_service->service = service; -+ user_service->userdata = userdata; -+ user_service->instance = instance; -+ user_service->is_vchi = (args.is_vchi != 0); -+ user_service->dequeue_pending = 0; -+ user_service->close_pending = 0; -+ user_service->message_available_pos = -+ instance->completion_remove - 1; -+ user_service->msg_insert = 0; -+ user_service->msg_remove = 0; -+ sema_init(&user_service->insert_event, 0); -+ sema_init(&user_service->remove_event, 0); -+ sema_init(&user_service->close_event, 0); -+ -+ if (args.is_open) { -+ status = vchiq_open_service_internal -+ (service, instance->pid); -+ if (status != VCHIQ_SUCCESS) { -+ vchiq_remove_service(service->handle); -+ service = NULL; -+ ret = (status == VCHIQ_RETRY) ? -+ -EINTR : -EIO; -+ break; -+ } -+ } -+ -+ if (copy_to_user((void __user *) -+ &(((VCHIQ_CREATE_SERVICE_T __user *) -+ arg)->handle), -+ (const void *)&service->handle, -+ sizeof(service->handle)) != 0) { -+ ret = -EFAULT; -+ vchiq_remove_service(service->handle); -+ } -+ -+ service = NULL; -+ } else { -+ ret = -EEXIST; -+ kfree(user_service); -+ } -+ } break; -+ -+ case VCHIQ_IOC_CLOSE_SERVICE: { -+ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg; -+ -+ service = find_service_for_instance(instance, handle); -+ if (service != NULL) { -+ USER_SERVICE_T *user_service = -+ (USER_SERVICE_T *)service->base.userdata; -+ /* close_pending is false on first entry, and when the -+ wait in vchiq_close_service has been interrupted. */ -+ if (!user_service->close_pending) { -+ status = vchiq_close_service(service->handle); -+ if (status != VCHIQ_SUCCESS) -+ break; -+ } -+ -+ /* close_pending is true once the underlying service -+ has been closed until the client library calls the -+ CLOSE_DELIVERED ioctl, signalling close_event. */ -+ if (user_service->close_pending && -+ down_interruptible(&user_service->close_event)) -+ status = VCHIQ_RETRY; -+ } -+ else -+ ret = -EINVAL; -+ } break; -+ -+ case VCHIQ_IOC_REMOVE_SERVICE: { -+ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg; -+ -+ service = find_service_for_instance(instance, handle); -+ if (service != NULL) { -+ USER_SERVICE_T *user_service = -+ (USER_SERVICE_T *)service->base.userdata; -+ /* close_pending is false on first entry, and when the -+ wait in vchiq_close_service has been interrupted. */ -+ if (!user_service->close_pending) { -+ status = vchiq_remove_service(service->handle); -+ if (status != VCHIQ_SUCCESS) -+ break; -+ } -+ -+ /* close_pending is true once the underlying service -+ has been closed until the client library calls the -+ CLOSE_DELIVERED ioctl, signalling close_event. */ -+ if (user_service->close_pending && -+ down_interruptible(&user_service->close_event)) -+ status = VCHIQ_RETRY; -+ } -+ else -+ ret = -EINVAL; -+ } break; -+ -+ case VCHIQ_IOC_USE_SERVICE: -+ case VCHIQ_IOC_RELEASE_SERVICE: { -+ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg; -+ -+ service = find_service_for_instance(instance, handle); -+ if (service != NULL) { -+ status = (cmd == VCHIQ_IOC_USE_SERVICE) ? -+ vchiq_use_service_internal(service) : -+ vchiq_release_service_internal(service); -+ if (status != VCHIQ_SUCCESS) { -+ vchiq_log_error(vchiq_susp_log_level, -+ "%s: cmd %s returned error %d for " -+ "service %c%c%c%c:%03d", -+ __func__, -+ (cmd == VCHIQ_IOC_USE_SERVICE) ? -+ "VCHIQ_IOC_USE_SERVICE" : -+ "VCHIQ_IOC_RELEASE_SERVICE", -+ status, -+ VCHIQ_FOURCC_AS_4CHARS( -+ service->base.fourcc), -+ service->client_id); -+ ret = -EINVAL; -+ } -+ } else -+ ret = -EINVAL; -+ } break; -+ -+ case VCHIQ_IOC_QUEUE_MESSAGE: { -+ VCHIQ_QUEUE_MESSAGE_T args; -+ if (copy_from_user -+ (&args, (const void __user *)arg, -+ sizeof(args)) != 0) { -+ ret = -EFAULT; -+ break; -+ } -+ -+ service = find_service_for_instance(instance, args.handle); -+ -+ if ((service != NULL) && (args.count <= MAX_ELEMENTS)) { -+ /* Copy elements into kernel space */ -+ VCHIQ_ELEMENT_T elements[MAX_ELEMENTS]; -+ if (copy_from_user(elements, args.elements, -+ args.count * sizeof(VCHIQ_ELEMENT_T)) == 0) -+ status = vchiq_queue_message -+ (args.handle, -+ elements, args.count); -+ else -+ ret = -EFAULT; -+ } else { -+ ret = -EINVAL; -+ } -+ } break; -+ -+ case VCHIQ_IOC_QUEUE_BULK_TRANSMIT: -+ case VCHIQ_IOC_QUEUE_BULK_RECEIVE: { -+ VCHIQ_QUEUE_BULK_TRANSFER_T args; -+ struct bulk_waiter_node *waiter = NULL; -+ VCHIQ_BULK_DIR_T dir = -+ (cmd == VCHIQ_IOC_QUEUE_BULK_TRANSMIT) ? -+ VCHIQ_BULK_TRANSMIT : VCHIQ_BULK_RECEIVE; -+ -+ if (copy_from_user -+ (&args, (const void __user *)arg, -+ sizeof(args)) != 0) { -+ ret = -EFAULT; -+ break; -+ } -+ -+ service = find_service_for_instance(instance, args.handle); -+ if (!service) { -+ ret = -EINVAL; -+ break; -+ } -+ -+ if (args.mode == VCHIQ_BULK_MODE_BLOCKING) { -+ waiter = kzalloc(sizeof(struct bulk_waiter_node), -+ GFP_KERNEL); -+ if (!waiter) { -+ ret = -ENOMEM; -+ break; -+ } -+ args.userdata = &waiter->bulk_waiter; -+ } else if (args.mode == VCHIQ_BULK_MODE_WAITING) { -+ struct list_head *pos; -+ mutex_lock(&instance->bulk_waiter_list_mutex); -+ list_for_each(pos, &instance->bulk_waiter_list) { -+ if (list_entry(pos, struct bulk_waiter_node, -+ list)->pid == current->pid) { -+ waiter = list_entry(pos, -+ struct bulk_waiter_node, -+ list); -+ list_del(pos); -+ break; -+ } -+ -+ } -+ mutex_unlock(&instance->bulk_waiter_list_mutex); -+ if (!waiter) { -+ vchiq_log_error(vchiq_arm_log_level, -+ "no bulk_waiter found for pid %d", -+ current->pid); -+ ret = -ESRCH; -+ break; -+ } -+ vchiq_log_info(vchiq_arm_log_level, -+ "found bulk_waiter %x for pid %d", -+ (unsigned int)waiter, current->pid); -+ args.userdata = &waiter->bulk_waiter; -+ } -+ status = vchiq_bulk_transfer -+ (args.handle, -+ VCHI_MEM_HANDLE_INVALID, -+ args.data, args.size, -+ args.userdata, args.mode, -+ dir); -+ if (!waiter) -+ break; -+ if ((status != VCHIQ_RETRY) || fatal_signal_pending(current) || -+ !waiter->bulk_waiter.bulk) { -+ if (waiter->bulk_waiter.bulk) { -+ /* Cancel the signal when the transfer -+ ** completes. */ -+ spin_lock(&bulk_waiter_spinlock); -+ waiter->bulk_waiter.bulk->userdata = NULL; -+ spin_unlock(&bulk_waiter_spinlock); -+ } -+ kfree(waiter); -+ } else { -+ const VCHIQ_BULK_MODE_T mode_waiting = -+ VCHIQ_BULK_MODE_WAITING; -+ waiter->pid = current->pid; -+ mutex_lock(&instance->bulk_waiter_list_mutex); -+ list_add(&waiter->list, &instance->bulk_waiter_list); -+ mutex_unlock(&instance->bulk_waiter_list_mutex); -+ vchiq_log_info(vchiq_arm_log_level, -+ "saved bulk_waiter %x for pid %d", -+ (unsigned int)waiter, current->pid); -+ -+ if (copy_to_user((void __user *) -+ &(((VCHIQ_QUEUE_BULK_TRANSFER_T __user *) -+ arg)->mode), -+ (const void *)&mode_waiting, -+ sizeof(mode_waiting)) != 0) -+ ret = -EFAULT; -+ } -+ } break; -+ -+ case VCHIQ_IOC_AWAIT_COMPLETION: { -+ VCHIQ_AWAIT_COMPLETION_T args; -+ -+ DEBUG_TRACE(AWAIT_COMPLETION_LINE); -+ if (!instance->connected) { -+ ret = -ENOTCONN; -+ break; -+ } -+ -+ if (copy_from_user(&args, (const void __user *)arg, -+ sizeof(args)) != 0) { -+ ret = -EFAULT; -+ break; -+ } -+ -+ mutex_lock(&instance->completion_mutex); -+ -+ DEBUG_TRACE(AWAIT_COMPLETION_LINE); -+ while ((instance->completion_remove == -+ instance->completion_insert) -+ && !instance->closing) { -+ int rc; -+ DEBUG_TRACE(AWAIT_COMPLETION_LINE); -+ mutex_unlock(&instance->completion_mutex); -+ rc = down_interruptible(&instance->insert_event); -+ mutex_lock(&instance->completion_mutex); -+ if (rc != 0) { -+ DEBUG_TRACE(AWAIT_COMPLETION_LINE); -+ vchiq_log_info(vchiq_arm_log_level, -+ "AWAIT_COMPLETION interrupted"); -+ ret = -EINTR; -+ break; -+ } -+ } -+ DEBUG_TRACE(AWAIT_COMPLETION_LINE); -+ -+ /* A read memory barrier is needed to stop prefetch of a stale -+ ** completion record -+ */ -+ rmb(); -+ -+ if (ret == 0) { -+ int msgbufcount = args.msgbufcount; -+ for (ret = 0; ret < args.count; ret++) { -+ VCHIQ_COMPLETION_DATA_T *completion; -+ VCHIQ_SERVICE_T *service; -+ USER_SERVICE_T *user_service; -+ VCHIQ_HEADER_T *header; -+ if (instance->completion_remove == -+ instance->completion_insert) -+ break; -+ completion = &instance->completions[ -+ instance->completion_remove & -+ (MAX_COMPLETIONS - 1)]; -+ -+ service = completion->service_userdata; -+ user_service = service->base.userdata; -+ completion->service_userdata = -+ user_service->userdata; -+ -+ header = completion->header; -+ if (header) { -+ void __user *msgbuf; -+ int msglen; -+ -+ msglen = header->size + -+ sizeof(VCHIQ_HEADER_T); -+ /* This must be a VCHIQ-style service */ -+ if (args.msgbufsize < msglen) { -+ vchiq_log_error( -+ vchiq_arm_log_level, -+ "header %x: msgbufsize" -+ " %x < msglen %x", -+ (unsigned int)header, -+ args.msgbufsize, -+ msglen); -+ WARN(1, "invalid message " -+ "size\n"); -+ if (ret == 0) -+ ret = -EMSGSIZE; -+ break; -+ } -+ if (msgbufcount <= 0) -+ /* Stall here for lack of a -+ ** buffer for the message. */ -+ break; -+ /* Get the pointer from user space */ -+ msgbufcount--; -+ if (copy_from_user(&msgbuf, -+ (const void __user *) -+ &args.msgbufs[msgbufcount], -+ sizeof(msgbuf)) != 0) { -+ if (ret == 0) -+ ret = -EFAULT; -+ break; -+ } -+ -+ /* Copy the message to user space */ -+ if (copy_to_user(msgbuf, header, -+ msglen) != 0) { -+ if (ret == 0) -+ ret = -EFAULT; -+ break; -+ } -+ -+ /* Now it has been copied, the message -+ ** can be released. */ -+ vchiq_release_message(service->handle, -+ header); -+ -+ /* The completion must point to the -+ ** msgbuf. */ -+ completion->header = msgbuf; -+ } -+ -+ if ((completion->reason == -+ VCHIQ_SERVICE_CLOSED) && -+ !instance->use_close_delivered) -+ unlock_service(service); -+ -+ if (copy_to_user((void __user *)( -+ (size_t)args.buf + -+ ret * sizeof(VCHIQ_COMPLETION_DATA_T)), -+ completion, -+ sizeof(VCHIQ_COMPLETION_DATA_T)) != 0) { -+ if (ret == 0) -+ ret = -EFAULT; -+ break; -+ } -+ -+ instance->completion_remove++; -+ } -+ -+ if (msgbufcount != args.msgbufcount) { -+ if (copy_to_user((void __user *) -+ &((VCHIQ_AWAIT_COMPLETION_T *)arg)-> -+ msgbufcount, -+ &msgbufcount, -+ sizeof(msgbufcount)) != 0) { -+ ret = -EFAULT; -+ } -+ } -+ } -+ -+ if (ret != 0) -+ up(&instance->remove_event); -+ mutex_unlock(&instance->completion_mutex); -+ DEBUG_TRACE(AWAIT_COMPLETION_LINE); -+ } break; -+ -+ case VCHIQ_IOC_DEQUEUE_MESSAGE: { -+ VCHIQ_DEQUEUE_MESSAGE_T args; -+ USER_SERVICE_T *user_service; -+ VCHIQ_HEADER_T *header; -+ -+ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE); -+ if (copy_from_user -+ (&args, (const void __user *)arg, -+ sizeof(args)) != 0) { -+ ret = -EFAULT; -+ break; -+ } -+ service = find_service_for_instance(instance, args.handle); -+ if (!service) { -+ ret = -EINVAL; -+ break; -+ } -+ user_service = (USER_SERVICE_T *)service->base.userdata; -+ if (user_service->is_vchi == 0) { -+ ret = -EINVAL; -+ break; -+ } -+ -+ spin_lock(&msg_queue_spinlock); -+ if (user_service->msg_remove == user_service->msg_insert) { -+ if (!args.blocking) { -+ spin_unlock(&msg_queue_spinlock); -+ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE); -+ ret = -EWOULDBLOCK; -+ break; -+ } -+ user_service->dequeue_pending = 1; -+ do { -+ spin_unlock(&msg_queue_spinlock); -+ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE); -+ if (down_interruptible( -+ &user_service->insert_event) != 0) { -+ vchiq_log_info(vchiq_arm_log_level, -+ "DEQUEUE_MESSAGE interrupted"); -+ ret = -EINTR; -+ break; -+ } -+ spin_lock(&msg_queue_spinlock); -+ } while (user_service->msg_remove == -+ user_service->msg_insert); -+ -+ if (ret) -+ break; -+ } -+ -+ BUG_ON((int)(user_service->msg_insert - -+ user_service->msg_remove) < 0); -+ -+ header = user_service->msg_queue[user_service->msg_remove & -+ (MSG_QUEUE_SIZE - 1)]; -+ user_service->msg_remove++; -+ spin_unlock(&msg_queue_spinlock); -+ -+ up(&user_service->remove_event); -+ if (header == NULL) -+ ret = -ENOTCONN; -+ else if (header->size <= args.bufsize) { -+ /* Copy to user space if msgbuf is not NULL */ -+ if ((args.buf == NULL) || -+ (copy_to_user((void __user *)args.buf, -+ header->data, -+ header->size) == 0)) { -+ ret = header->size; -+ vchiq_release_message( -+ service->handle, -+ header); -+ } else -+ ret = -EFAULT; -+ } else { -+ vchiq_log_error(vchiq_arm_log_level, -+ "header %x: bufsize %x < size %x", -+ (unsigned int)header, args.bufsize, -+ header->size); -+ WARN(1, "invalid size\n"); -+ ret = -EMSGSIZE; -+ } -+ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE); -+ } break; -+ -+ case VCHIQ_IOC_GET_CLIENT_ID: { -+ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg; -+ -+ ret = vchiq_get_client_id(handle); -+ } break; -+ -+ case VCHIQ_IOC_GET_CONFIG: { -+ VCHIQ_GET_CONFIG_T args; -+ VCHIQ_CONFIG_T config; -+ -+ if (copy_from_user(&args, (const void __user *)arg, -+ sizeof(args)) != 0) { -+ ret = -EFAULT; -+ break; -+ } -+ if (args.config_size > sizeof(config)) { -+ ret = -EINVAL; -+ break; -+ } -+ status = vchiq_get_config(instance, args.config_size, &config); -+ if (status == VCHIQ_SUCCESS) { -+ if (copy_to_user((void __user *)args.pconfig, -+ &config, args.config_size) != 0) { -+ ret = -EFAULT; -+ break; -+ } -+ } -+ } break; -+ -+ case VCHIQ_IOC_SET_SERVICE_OPTION: { -+ VCHIQ_SET_SERVICE_OPTION_T args; -+ -+ if (copy_from_user( -+ &args, (const void __user *)arg, -+ sizeof(args)) != 0) { -+ ret = -EFAULT; -+ break; -+ } -+ -+ service = find_service_for_instance(instance, args.handle); -+ if (!service) { -+ ret = -EINVAL; -+ break; -+ } -+ -+ status = vchiq_set_service_option( -+ args.handle, args.option, args.value); -+ } break; -+ -+ case VCHIQ_IOC_DUMP_PHYS_MEM: { -+ VCHIQ_DUMP_MEM_T args; -+ -+ if (copy_from_user -+ (&args, (const void __user *)arg, -+ sizeof(args)) != 0) { -+ ret = -EFAULT; -+ break; -+ } -+ dump_phys_mem(args.virt_addr, args.num_bytes); -+ } break; -+ -+ case VCHIQ_IOC_LIB_VERSION: { -+ unsigned int lib_version = (unsigned int)arg; -+ -+ if (lib_version < VCHIQ_VERSION_MIN) -+ ret = -EINVAL; -+ else if (lib_version >= VCHIQ_VERSION_CLOSE_DELIVERED) -+ instance->use_close_delivered = 1; -+ } break; -+ -+ case VCHIQ_IOC_CLOSE_DELIVERED: { -+ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg; -+ -+ service = find_closed_service_for_instance(instance, handle); -+ if (service != NULL) { -+ USER_SERVICE_T *user_service = -+ (USER_SERVICE_T *)service->base.userdata; -+ close_delivered(user_service); -+ } -+ else -+ ret = -EINVAL; -+ } break; -+ -+ default: -+ ret = -ENOTTY; -+ break; -+ } -+ -+ if (service) -+ unlock_service(service); -+ -+ if (ret == 0) { -+ if (status == VCHIQ_ERROR) -+ ret = -EIO; -+ else if (status == VCHIQ_RETRY) -+ ret = -EINTR; -+ } -+ -+ if ((status == VCHIQ_SUCCESS) && (ret < 0) && (ret != -EINTR) && -+ (ret != -EWOULDBLOCK)) -+ vchiq_log_info(vchiq_arm_log_level, -+ " ioctl instance %lx, cmd %s -> status %d, %ld", -+ (unsigned long)instance, -+ (_IOC_NR(cmd) <= VCHIQ_IOC_MAX) ? -+ ioctl_names[_IOC_NR(cmd)] : -+ "", -+ status, ret); -+ else -+ vchiq_log_trace(vchiq_arm_log_level, -+ " ioctl instance %lx, cmd %s -> status %d, %ld", -+ (unsigned long)instance, -+ (_IOC_NR(cmd) <= VCHIQ_IOC_MAX) ? -+ ioctl_names[_IOC_NR(cmd)] : -+ "", -+ status, ret); -+ -+ return ret; -+} -+ -+/**************************************************************************** -+* -+* vchiq_open -+* -+***************************************************************************/ -+ -+static int -+vchiq_open(struct inode *inode, struct file *file) -+{ -+ int dev = iminor(inode) & 0x0f; -+ vchiq_log_info(vchiq_arm_log_level, "vchiq_open"); -+ switch (dev) { -+ case VCHIQ_MINOR: { -+ int ret; -+ VCHIQ_STATE_T *state = vchiq_get_state(); -+ VCHIQ_INSTANCE_T instance; -+ -+ if (!state) { -+ vchiq_log_error(vchiq_arm_log_level, -+ "vchiq has no connection to VideoCore"); -+ return -ENOTCONN; -+ } -+ -+ instance = kzalloc(sizeof(*instance), GFP_KERNEL); -+ if (!instance) -+ return -ENOMEM; -+ -+ instance->state = state; -+ instance->pid = current->tgid; -+ -+ ret = vchiq_debugfs_add_instance(instance); -+ if (ret != 0) { -+ kfree(instance); -+ return ret; -+ } -+ -+ sema_init(&instance->insert_event, 0); -+ sema_init(&instance->remove_event, 0); -+ mutex_init(&instance->completion_mutex); -+ mutex_init(&instance->bulk_waiter_list_mutex); -+ INIT_LIST_HEAD(&instance->bulk_waiter_list); -+ -+ file->private_data = instance; -+ } break; -+ -+ default: -+ vchiq_log_error(vchiq_arm_log_level, -+ "Unknown minor device: %d", dev); -+ return -ENXIO; -+ } -+ -+ return 0; -+} -+ -+/**************************************************************************** -+* -+* vchiq_release -+* -+***************************************************************************/ -+ -+static int -+vchiq_release(struct inode *inode, struct file *file) -+{ -+ int dev = iminor(inode) & 0x0f; -+ int ret = 0; -+ switch (dev) { -+ case VCHIQ_MINOR: { -+ VCHIQ_INSTANCE_T instance = file->private_data; -+ VCHIQ_STATE_T *state = vchiq_get_state(); -+ VCHIQ_SERVICE_T *service; -+ int i; -+ -+ vchiq_log_info(vchiq_arm_log_level, -+ "vchiq_release: instance=%lx", -+ (unsigned long)instance); -+ -+ if (!state) { -+ ret = -EPERM; -+ goto out; -+ } -+ -+ /* Ensure videocore is awake to allow termination. */ -+ vchiq_use_internal(instance->state, NULL, -+ USE_TYPE_VCHIQ); -+ -+ mutex_lock(&instance->completion_mutex); -+ -+ /* Wake the completion thread and ask it to exit */ -+ instance->closing = 1; -+ up(&instance->insert_event); -+ -+ mutex_unlock(&instance->completion_mutex); -+ -+ /* Wake the slot handler if the completion queue is full. */ -+ up(&instance->remove_event); -+ -+ /* Mark all services for termination... */ -+ i = 0; -+ while ((service = next_service_by_instance(state, instance, -+ &i)) != NULL) { -+ USER_SERVICE_T *user_service = service->base.userdata; -+ -+ /* Wake the slot handler if the msg queue is full. */ -+ up(&user_service->remove_event); -+ -+ vchiq_terminate_service_internal(service); -+ unlock_service(service); -+ } -+ -+ /* ...and wait for them to die */ -+ i = 0; -+ while ((service = next_service_by_instance(state, instance, &i)) -+ != NULL) { -+ USER_SERVICE_T *user_service = service->base.userdata; -+ -+ down(&service->remove_event); -+ -+ BUG_ON(service->srvstate != VCHIQ_SRVSTATE_FREE); -+ -+ spin_lock(&msg_queue_spinlock); -+ -+ while (user_service->msg_remove != -+ user_service->msg_insert) { -+ VCHIQ_HEADER_T *header = user_service-> -+ msg_queue[user_service->msg_remove & -+ (MSG_QUEUE_SIZE - 1)]; -+ user_service->msg_remove++; -+ spin_unlock(&msg_queue_spinlock); -+ -+ if (header) -+ vchiq_release_message( -+ service->handle, -+ header); -+ spin_lock(&msg_queue_spinlock); -+ } -+ -+ spin_unlock(&msg_queue_spinlock); -+ -+ unlock_service(service); -+ } -+ -+ /* Release any closed services */ -+ while (instance->completion_remove != -+ instance->completion_insert) { -+ VCHIQ_COMPLETION_DATA_T *completion; -+ VCHIQ_SERVICE_T *service; -+ completion = &instance->completions[ -+ instance->completion_remove & -+ (MAX_COMPLETIONS - 1)]; -+ service = completion->service_userdata; -+ if (completion->reason == VCHIQ_SERVICE_CLOSED) -+ { -+ USER_SERVICE_T *user_service = -+ service->base.userdata; -+ -+ /* Wake any blocked user-thread */ -+ if (instance->use_close_delivered) -+ up(&user_service->close_event); -+ unlock_service(service); -+ } -+ instance->completion_remove++; -+ } -+ -+ /* Release the PEER service count. */ -+ vchiq_release_internal(instance->state, NULL); -+ -+ { -+ struct list_head *pos, *next; -+ list_for_each_safe(pos, next, -+ &instance->bulk_waiter_list) { -+ struct bulk_waiter_node *waiter; -+ waiter = list_entry(pos, -+ struct bulk_waiter_node, -+ list); -+ list_del(pos); -+ vchiq_log_info(vchiq_arm_log_level, -+ "bulk_waiter - cleaned up %x " -+ "for pid %d", -+ (unsigned int)waiter, waiter->pid); -+ kfree(waiter); -+ } -+ } -+ -+ vchiq_debugfs_remove_instance(instance); -+ -+ kfree(instance); -+ file->private_data = NULL; -+ } break; -+ -+ default: -+ vchiq_log_error(vchiq_arm_log_level, -+ "Unknown minor device: %d", dev); -+ ret = -ENXIO; -+ } -+ -+out: -+ return ret; -+} -+ -+/**************************************************************************** -+* -+* vchiq_dump -+* -+***************************************************************************/ -+ -+void -+vchiq_dump(void *dump_context, const char *str, int len) -+{ -+ DUMP_CONTEXT_T *context = (DUMP_CONTEXT_T *)dump_context; -+ -+ if (context->actual < context->space) { -+ int copy_bytes; -+ if (context->offset > 0) { -+ int skip_bytes = min(len, (int)context->offset); -+ str += skip_bytes; -+ len -= skip_bytes; -+ context->offset -= skip_bytes; -+ if (context->offset > 0) -+ return; -+ } -+ copy_bytes = min(len, (int)(context->space - context->actual)); -+ if (copy_bytes == 0) -+ return; -+ if (copy_to_user(context->buf + context->actual, str, -+ copy_bytes)) -+ context->actual = -EFAULT; -+ context->actual += copy_bytes; -+ len -= copy_bytes; -+ -+ /* If tne terminating NUL is included in the length, then it -+ ** marks the end of a line and should be replaced with a -+ ** carriage return. */ -+ if ((len == 0) && (str[copy_bytes - 1] == '\0')) { -+ char cr = '\n'; -+ if (copy_to_user(context->buf + context->actual - 1, -+ &cr, 1)) -+ context->actual = -EFAULT; -+ } -+ } -+} -+ -+/**************************************************************************** -+* -+* vchiq_dump_platform_instance_state -+* -+***************************************************************************/ -+ -+void -+vchiq_dump_platform_instances(void *dump_context) -+{ -+ VCHIQ_STATE_T *state = vchiq_get_state(); -+ char buf[80]; -+ int len; -+ int i; -+ -+ /* There is no list of instances, so instead scan all services, -+ marking those that have been dumped. */ -+ -+ for (i = 0; i < state->unused_service; i++) { -+ VCHIQ_SERVICE_T *service = state->services[i]; -+ VCHIQ_INSTANCE_T instance; -+ -+ if (service && (service->base.callback == service_callback)) { -+ instance = service->instance; -+ if (instance) -+ instance->mark = 0; -+ } -+ } -+ -+ for (i = 0; i < state->unused_service; i++) { -+ VCHIQ_SERVICE_T *service = state->services[i]; -+ VCHIQ_INSTANCE_T instance; -+ -+ if (service && (service->base.callback == service_callback)) { -+ instance = service->instance; -+ if (instance && !instance->mark) { -+ len = snprintf(buf, sizeof(buf), -+ "Instance %x: pid %d,%s completions " -+ "%d/%d", -+ (unsigned int)instance, instance->pid, -+ instance->connected ? " connected, " : -+ "", -+ instance->completion_insert - -+ instance->completion_remove, -+ MAX_COMPLETIONS); -+ -+ vchiq_dump(dump_context, buf, len + 1); -+ -+ instance->mark = 1; -+ } -+ } -+ } -+} -+ -+/**************************************************************************** -+* -+* vchiq_dump_platform_service_state -+* -+***************************************************************************/ -+ -+void -+vchiq_dump_platform_service_state(void *dump_context, VCHIQ_SERVICE_T *service) -+{ -+ USER_SERVICE_T *user_service = (USER_SERVICE_T *)service->base.userdata; -+ char buf[80]; -+ int len; -+ -+ len = snprintf(buf, sizeof(buf), " instance %x", -+ (unsigned int)service->instance); -+ -+ if ((service->base.callback == service_callback) && -+ user_service->is_vchi) { -+ len += snprintf(buf + len, sizeof(buf) - len, -+ ", %d/%d messages", -+ user_service->msg_insert - user_service->msg_remove, -+ MSG_QUEUE_SIZE); -+ -+ if (user_service->dequeue_pending) -+ len += snprintf(buf + len, sizeof(buf) - len, -+ " (dequeue pending)"); -+ } -+ -+ vchiq_dump(dump_context, buf, len + 1); -+} -+ -+/**************************************************************************** -+* -+* dump_user_mem -+* -+***************************************************************************/ -+ -+static void -+dump_phys_mem(void *virt_addr, uint32_t num_bytes) -+{ -+ int rc; -+ uint8_t *end_virt_addr = virt_addr + num_bytes; -+ int num_pages; -+ int offset; -+ int end_offset; -+ int page_idx; -+ int prev_idx; -+ struct page *page; -+ struct page **pages; -+ uint8_t *kmapped_virt_ptr; -+ -+ /* Align virtAddr and endVirtAddr to 16 byte boundaries. */ -+ -+ virt_addr = (void *)((unsigned long)virt_addr & ~0x0fuL); -+ end_virt_addr = (void *)(((unsigned long)end_virt_addr + 15uL) & -+ ~0x0fuL); -+ -+ offset = (int)(long)virt_addr & (PAGE_SIZE - 1); -+ end_offset = (int)(long)end_virt_addr & (PAGE_SIZE - 1); -+ -+ num_pages = (offset + num_bytes + PAGE_SIZE - 1) / PAGE_SIZE; -+ -+ pages = kmalloc(sizeof(struct page *) * num_pages, GFP_KERNEL); -+ if (pages == NULL) { -+ vchiq_log_error(vchiq_arm_log_level, -+ "Unable to allocation memory for %d pages\n", -+ num_pages); -+ return; -+ } -+ -+ down_read(¤t->mm->mmap_sem); -+ rc = get_user_pages(current, /* task */ -+ current->mm, /* mm */ -+ (unsigned long)virt_addr, /* start */ -+ num_pages, /* len */ -+ 0, /* write */ -+ 0, /* force */ -+ pages, /* pages (array of page pointers) */ -+ NULL); /* vmas */ -+ up_read(¤t->mm->mmap_sem); -+ -+ prev_idx = -1; -+ page = NULL; -+ -+ while (offset < end_offset) { -+ -+ int page_offset = offset % PAGE_SIZE; -+ page_idx = offset / PAGE_SIZE; -+ -+ if (page_idx != prev_idx) { -+ -+ if (page != NULL) -+ kunmap(page); -+ page = pages[page_idx]; -+ kmapped_virt_ptr = kmap(page); -+ -+ prev_idx = page_idx; -+ } -+ -+ if (vchiq_arm_log_level >= VCHIQ_LOG_TRACE) -+ vchiq_log_dump_mem("ph", -+ (uint32_t)(unsigned long)&kmapped_virt_ptr[ -+ page_offset], -+ &kmapped_virt_ptr[page_offset], 16); -+ -+ offset += 16; -+ } -+ if (page != NULL) -+ kunmap(page); -+ -+ for (page_idx = 0; page_idx < num_pages; page_idx++) -+ page_cache_release(pages[page_idx]); -+ -+ kfree(pages); -+} -+ -+/**************************************************************************** -+* -+* vchiq_read -+* -+***************************************************************************/ -+ -+static ssize_t -+vchiq_read(struct file *file, char __user *buf, -+ size_t count, loff_t *ppos) -+{ -+ DUMP_CONTEXT_T context; -+ context.buf = buf; -+ context.actual = 0; -+ context.space = count; -+ context.offset = *ppos; -+ -+ vchiq_dump_state(&context, &g_state); -+ -+ *ppos += context.actual; -+ -+ return context.actual; -+} -+ -+VCHIQ_STATE_T * -+vchiq_get_state(void) -+{ -+ -+ if (g_state.remote == NULL) -+ printk(KERN_ERR "%s: g_state.remote == NULL\n", __func__); -+ else if (g_state.remote->initialised != 1) -+ printk(KERN_NOTICE "%s: g_state.remote->initialised != 1 (%d)\n", -+ __func__, g_state.remote->initialised); -+ -+ return ((g_state.remote != NULL) && -+ (g_state.remote->initialised == 1)) ? &g_state : NULL; -+} -+ -+static const struct file_operations -+vchiq_fops = { -+ .owner = THIS_MODULE, -+ .unlocked_ioctl = vchiq_ioctl, -+ .open = vchiq_open, -+ .release = vchiq_release, -+ .read = vchiq_read -+}; -+ -+/* -+ * Autosuspend related functionality -+ */ -+ -+int -+vchiq_videocore_wanted(VCHIQ_STATE_T *state) -+{ -+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); -+ if (!arm_state) -+ /* autosuspend not supported - always return wanted */ -+ return 1; -+ else if (arm_state->blocked_count) -+ return 1; -+ else if (!arm_state->videocore_use_count) -+ /* usage count zero - check for override unless we're forcing */ -+ if (arm_state->resume_blocked) -+ return 0; -+ else -+ return vchiq_platform_videocore_wanted(state); -+ else -+ /* non-zero usage count - videocore still required */ -+ return 1; -+} -+ -+static VCHIQ_STATUS_T -+vchiq_keepalive_vchiq_callback(VCHIQ_REASON_T reason, -+ VCHIQ_HEADER_T *header, -+ VCHIQ_SERVICE_HANDLE_T service_user, -+ void *bulk_user) -+{ -+ vchiq_log_error(vchiq_susp_log_level, -+ "%s callback reason %d", __func__, reason); -+ return 0; -+} -+ -+static int -+vchiq_keepalive_thread_func(void *v) -+{ -+ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v; -+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); -+ -+ VCHIQ_STATUS_T status; -+ VCHIQ_INSTANCE_T instance; -+ VCHIQ_SERVICE_HANDLE_T ka_handle; -+ -+ VCHIQ_SERVICE_PARAMS_T params = { -+ .fourcc = VCHIQ_MAKE_FOURCC('K', 'E', 'E', 'P'), -+ .callback = vchiq_keepalive_vchiq_callback, -+ .version = KEEPALIVE_VER, -+ .version_min = KEEPALIVE_VER_MIN -+ }; -+ -+ status = vchiq_initialise(&instance); -+ if (status != VCHIQ_SUCCESS) { -+ vchiq_log_error(vchiq_susp_log_level, -+ "%s vchiq_initialise failed %d", __func__, status); -+ goto exit; -+ } -+ -+ status = vchiq_connect(instance); -+ if (status != VCHIQ_SUCCESS) { -+ vchiq_log_error(vchiq_susp_log_level, -+ "%s vchiq_connect failed %d", __func__, status); -+ goto shutdown; -+ } -+ -+ status = vchiq_add_service(instance, ¶ms, &ka_handle); -+ if (status != VCHIQ_SUCCESS) { -+ vchiq_log_error(vchiq_susp_log_level, -+ "%s vchiq_open_service failed %d", __func__, status); -+ goto shutdown; -+ } -+ -+ while (1) { -+ long rc = 0, uc = 0; -+ if (wait_for_completion_interruptible(&arm_state->ka_evt) -+ != 0) { -+ vchiq_log_error(vchiq_susp_log_level, -+ "%s interrupted", __func__); -+ flush_signals(current); -+ continue; -+ } -+ -+ /* read and clear counters. Do release_count then use_count to -+ * prevent getting more releases than uses */ -+ rc = atomic_xchg(&arm_state->ka_release_count, 0); -+ uc = atomic_xchg(&arm_state->ka_use_count, 0); -+ -+ /* Call use/release service the requisite number of times. -+ * Process use before release so use counts don't go negative */ -+ while (uc--) { -+ atomic_inc(&arm_state->ka_use_ack_count); -+ status = vchiq_use_service(ka_handle); -+ if (status != VCHIQ_SUCCESS) { -+ vchiq_log_error(vchiq_susp_log_level, -+ "%s vchiq_use_service error %d", -+ __func__, status); -+ } -+ } -+ while (rc--) { -+ status = vchiq_release_service(ka_handle); -+ if (status != VCHIQ_SUCCESS) { -+ vchiq_log_error(vchiq_susp_log_level, -+ "%s vchiq_release_service error %d", -+ __func__, status); -+ } -+ } -+ } -+ -+shutdown: -+ vchiq_shutdown(instance); -+exit: -+ return 0; -+} -+ -+ -+ -+VCHIQ_STATUS_T -+vchiq_arm_init_state(VCHIQ_STATE_T *state, VCHIQ_ARM_STATE_T *arm_state) -+{ -+ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; -+ -+ if (arm_state) { -+ rwlock_init(&arm_state->susp_res_lock); -+ -+ init_completion(&arm_state->ka_evt); -+ atomic_set(&arm_state->ka_use_count, 0); -+ atomic_set(&arm_state->ka_use_ack_count, 0); -+ atomic_set(&arm_state->ka_release_count, 0); -+ -+ init_completion(&arm_state->vc_suspend_complete); -+ -+ init_completion(&arm_state->vc_resume_complete); -+ /* Initialise to 'done' state. We only want to block on resume -+ * completion while videocore is suspended. */ -+ set_resume_state(arm_state, VC_RESUME_RESUMED); -+ -+ init_completion(&arm_state->resume_blocker); -+ /* Initialise to 'done' state. We only want to block on this -+ * completion while resume is blocked */ -+ complete_all(&arm_state->resume_blocker); -+ -+ init_completion(&arm_state->blocked_blocker); -+ /* Initialise to 'done' state. We only want to block on this -+ * completion while things are waiting on the resume blocker */ -+ complete_all(&arm_state->blocked_blocker); -+ -+ arm_state->suspend_timer_timeout = SUSPEND_TIMER_TIMEOUT_MS; -+ arm_state->suspend_timer_running = 0; -+ init_timer(&arm_state->suspend_timer); -+ arm_state->suspend_timer.data = (unsigned long)(state); -+ arm_state->suspend_timer.function = suspend_timer_callback; -+ -+ arm_state->first_connect = 0; -+ -+ } -+ return status; -+} -+ -+/* -+** Functions to modify the state variables; -+** set_suspend_state -+** set_resume_state -+** -+** There are more state variables than we might like, so ensure they remain in -+** step. Suspend and resume state are maintained separately, since most of -+** these state machines can operate independently. However, there are a few -+** states where state transitions in one state machine cause a reset to the -+** other state machine. In addition, there are some completion events which -+** need to occur on state machine reset and end-state(s), so these are also -+** dealt with in these functions. -+** -+** In all states we set the state variable according to the input, but in some -+** cases we perform additional steps outlined below; -+** -+** VC_SUSPEND_IDLE - Initialise the suspend completion at the same time. -+** The suspend completion is completed after any suspend -+** attempt. When we reset the state machine we also reset -+** the completion. This reset occurs when videocore is -+** resumed, and also if we initiate suspend after a suspend -+** failure. -+** -+** VC_SUSPEND_IN_PROGRESS - This state is considered the point of no return for -+** suspend - ie from this point on we must try to suspend -+** before resuming can occur. We therefore also reset the -+** resume state machine to VC_RESUME_IDLE in this state. -+** -+** VC_SUSPEND_SUSPENDED - Suspend has completed successfully. Also call -+** complete_all on the suspend completion to notify -+** anything waiting for suspend to happen. -+** -+** VC_SUSPEND_REJECTED - Videocore rejected suspend. Videocore will also -+** initiate resume, so no need to alter resume state. -+** We call complete_all on the suspend completion to notify -+** of suspend rejection. -+** -+** VC_SUSPEND_FAILED - We failed to initiate videocore suspend. We notify the -+** suspend completion and reset the resume state machine. -+** -+** VC_RESUME_IDLE - Initialise the resume completion at the same time. The -+** resume completion is in it's 'done' state whenever -+** videcore is running. Therfore, the VC_RESUME_IDLE state -+** implies that videocore is suspended. -+** Hence, any thread which needs to wait until videocore is -+** running can wait on this completion - it will only block -+** if videocore is suspended. -+** -+** VC_RESUME_RESUMED - Resume has completed successfully. Videocore is running. -+** Call complete_all on the resume completion to unblock -+** any threads waiting for resume. Also reset the suspend -+** state machine to it's idle state. -+** -+** VC_RESUME_FAILED - Currently unused - no mechanism to fail resume exists. -+*/ -+ -+void -+set_suspend_state(VCHIQ_ARM_STATE_T *arm_state, -+ enum vc_suspend_status new_state) -+{ -+ /* set the state in all cases */ -+ arm_state->vc_suspend_state = new_state; -+ -+ /* state specific additional actions */ -+ switch (new_state) { -+ case VC_SUSPEND_FORCE_CANCELED: -+ complete_all(&arm_state->vc_suspend_complete); -+ break; -+ case VC_SUSPEND_REJECTED: -+ complete_all(&arm_state->vc_suspend_complete); -+ break; -+ case VC_SUSPEND_FAILED: -+ complete_all(&arm_state->vc_suspend_complete); -+ arm_state->vc_resume_state = VC_RESUME_RESUMED; -+ complete_all(&arm_state->vc_resume_complete); -+ break; -+ case VC_SUSPEND_IDLE: -+ reinit_completion(&arm_state->vc_suspend_complete); -+ break; -+ case VC_SUSPEND_REQUESTED: -+ break; -+ case VC_SUSPEND_IN_PROGRESS: -+ set_resume_state(arm_state, VC_RESUME_IDLE); -+ break; -+ case VC_SUSPEND_SUSPENDED: -+ complete_all(&arm_state->vc_suspend_complete); -+ break; -+ default: -+ BUG(); -+ break; -+ } -+} -+ -+void -+set_resume_state(VCHIQ_ARM_STATE_T *arm_state, -+ enum vc_resume_status new_state) -+{ -+ /* set the state in all cases */ -+ arm_state->vc_resume_state = new_state; -+ -+ /* state specific additional actions */ -+ switch (new_state) { -+ case VC_RESUME_FAILED: -+ break; -+ case VC_RESUME_IDLE: -+ reinit_completion(&arm_state->vc_resume_complete); -+ break; -+ case VC_RESUME_REQUESTED: -+ break; -+ case VC_RESUME_IN_PROGRESS: -+ break; -+ case VC_RESUME_RESUMED: -+ complete_all(&arm_state->vc_resume_complete); -+ set_suspend_state(arm_state, VC_SUSPEND_IDLE); -+ break; -+ default: -+ BUG(); -+ break; -+ } -+} -+ -+ -+/* should be called with the write lock held */ -+inline void -+start_suspend_timer(VCHIQ_ARM_STATE_T *arm_state) -+{ -+ del_timer(&arm_state->suspend_timer); -+ arm_state->suspend_timer.expires = jiffies + -+ msecs_to_jiffies(arm_state-> -+ suspend_timer_timeout); -+ add_timer(&arm_state->suspend_timer); -+ arm_state->suspend_timer_running = 1; -+} -+ -+/* should be called with the write lock held */ -+static inline void -+stop_suspend_timer(VCHIQ_ARM_STATE_T *arm_state) -+{ -+ if (arm_state->suspend_timer_running) { -+ del_timer(&arm_state->suspend_timer); -+ arm_state->suspend_timer_running = 0; -+ } -+} -+ -+static inline int -+need_resume(VCHIQ_STATE_T *state) -+{ -+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); -+ return (arm_state->vc_suspend_state > VC_SUSPEND_IDLE) && -+ (arm_state->vc_resume_state < VC_RESUME_REQUESTED) && -+ vchiq_videocore_wanted(state); -+} -+ -+static int -+block_resume(VCHIQ_ARM_STATE_T *arm_state) -+{ -+ int status = VCHIQ_SUCCESS; -+ const unsigned long timeout_val = -+ msecs_to_jiffies(FORCE_SUSPEND_TIMEOUT_MS); -+ int resume_count = 0; -+ -+ /* Allow any threads which were blocked by the last force suspend to -+ * complete if they haven't already. Only give this one shot; if -+ * blocked_count is incremented after blocked_blocker is completed -+ * (which only happens when blocked_count hits 0) then those threads -+ * will have to wait until next time around */ -+ if (arm_state->blocked_count) { -+ reinit_completion(&arm_state->blocked_blocker); -+ write_unlock_bh(&arm_state->susp_res_lock); -+ vchiq_log_info(vchiq_susp_log_level, "%s wait for previously " -+ "blocked clients", __func__); -+ if (wait_for_completion_interruptible_timeout( -+ &arm_state->blocked_blocker, timeout_val) -+ <= 0) { -+ vchiq_log_error(vchiq_susp_log_level, "%s wait for " -+ "previously blocked clients failed" , __func__); -+ status = VCHIQ_ERROR; -+ write_lock_bh(&arm_state->susp_res_lock); -+ goto out; -+ } -+ vchiq_log_info(vchiq_susp_log_level, "%s previously blocked " -+ "clients resumed", __func__); -+ write_lock_bh(&arm_state->susp_res_lock); -+ } -+ -+ /* We need to wait for resume to complete if it's in process */ -+ while (arm_state->vc_resume_state != VC_RESUME_RESUMED && -+ arm_state->vc_resume_state > VC_RESUME_IDLE) { -+ if (resume_count > 1) { -+ status = VCHIQ_ERROR; -+ vchiq_log_error(vchiq_susp_log_level, "%s waited too " -+ "many times for resume" , __func__); -+ goto out; -+ } -+ write_unlock_bh(&arm_state->susp_res_lock); -+ vchiq_log_info(vchiq_susp_log_level, "%s wait for resume", -+ __func__); -+ if (wait_for_completion_interruptible_timeout( -+ &arm_state->vc_resume_complete, timeout_val) -+ <= 0) { -+ vchiq_log_error(vchiq_susp_log_level, "%s wait for " -+ "resume failed (%s)", __func__, -+ resume_state_names[arm_state->vc_resume_state + -+ VC_RESUME_NUM_OFFSET]); -+ status = VCHIQ_ERROR; -+ write_lock_bh(&arm_state->susp_res_lock); -+ goto out; -+ } -+ vchiq_log_info(vchiq_susp_log_level, "%s resumed", __func__); -+ write_lock_bh(&arm_state->susp_res_lock); -+ resume_count++; -+ } -+ reinit_completion(&arm_state->resume_blocker); -+ arm_state->resume_blocked = 1; -+ -+out: -+ return status; -+} -+ -+static inline void -+unblock_resume(VCHIQ_ARM_STATE_T *arm_state) -+{ -+ complete_all(&arm_state->resume_blocker); -+ arm_state->resume_blocked = 0; -+} -+ -+/* Initiate suspend via slot handler. Should be called with the write lock -+ * held */ -+VCHIQ_STATUS_T -+vchiq_arm_vcsuspend(VCHIQ_STATE_T *state) -+{ -+ VCHIQ_STATUS_T status = VCHIQ_ERROR; -+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); -+ -+ if (!arm_state) -+ goto out; -+ -+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); -+ status = VCHIQ_SUCCESS; -+ -+ -+ switch (arm_state->vc_suspend_state) { -+ case VC_SUSPEND_REQUESTED: -+ vchiq_log_info(vchiq_susp_log_level, "%s: suspend already " -+ "requested", __func__); -+ break; -+ case VC_SUSPEND_IN_PROGRESS: -+ vchiq_log_info(vchiq_susp_log_level, "%s: suspend already in " -+ "progress", __func__); -+ break; -+ -+ default: -+ /* We don't expect to be in other states, so log but continue -+ * anyway */ -+ vchiq_log_error(vchiq_susp_log_level, -+ "%s unexpected suspend state %s", __func__, -+ suspend_state_names[arm_state->vc_suspend_state + -+ VC_SUSPEND_NUM_OFFSET]); -+ /* fall through */ -+ case VC_SUSPEND_REJECTED: -+ case VC_SUSPEND_FAILED: -+ /* Ensure any idle state actions have been run */ -+ set_suspend_state(arm_state, VC_SUSPEND_IDLE); -+ /* fall through */ -+ case VC_SUSPEND_IDLE: -+ vchiq_log_info(vchiq_susp_log_level, -+ "%s: suspending", __func__); -+ set_suspend_state(arm_state, VC_SUSPEND_REQUESTED); -+ /* kick the slot handler thread to initiate suspend */ -+ request_poll(state, NULL, 0); -+ break; -+ } -+ -+out: -+ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, status); -+ return status; -+} -+ -+void -+vchiq_platform_check_suspend(VCHIQ_STATE_T *state) -+{ -+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); -+ int susp = 0; -+ -+ if (!arm_state) -+ goto out; -+ -+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); -+ -+ write_lock_bh(&arm_state->susp_res_lock); -+ if (arm_state->vc_suspend_state == VC_SUSPEND_REQUESTED && -+ arm_state->vc_resume_state == VC_RESUME_RESUMED) { -+ set_suspend_state(arm_state, VC_SUSPEND_IN_PROGRESS); -+ susp = 1; -+ } -+ write_unlock_bh(&arm_state->susp_res_lock); -+ -+ if (susp) -+ vchiq_platform_suspend(state); -+ -+out: -+ vchiq_log_trace(vchiq_susp_log_level, "%s exit", __func__); -+ return; -+} -+ -+ -+static void -+output_timeout_error(VCHIQ_STATE_T *state) -+{ -+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); -+ char service_err[50] = ""; -+ int vc_use_count = arm_state->videocore_use_count; -+ int active_services = state->unused_service; -+ int i; -+ -+ if (!arm_state->videocore_use_count) { -+ snprintf(service_err, 50, " Videocore usecount is 0"); -+ goto output_msg; -+ } -+ for (i = 0; i < active_services; i++) { -+ VCHIQ_SERVICE_T *service_ptr = state->services[i]; -+ if (service_ptr && service_ptr->service_use_count && -+ (service_ptr->srvstate != VCHIQ_SRVSTATE_FREE)) { -+ snprintf(service_err, 50, " %c%c%c%c(%d) service has " -+ "use count %d%s", VCHIQ_FOURCC_AS_4CHARS( -+ service_ptr->base.fourcc), -+ service_ptr->client_id, -+ service_ptr->service_use_count, -+ service_ptr->service_use_count == -+ vc_use_count ? "" : " (+ more)"); -+ break; -+ } -+ } -+ -+output_msg: -+ vchiq_log_error(vchiq_susp_log_level, -+ "timed out waiting for vc suspend (%d).%s", -+ arm_state->autosuspend_override, service_err); -+ -+} -+ -+/* Try to get videocore into suspended state, regardless of autosuspend state. -+** We don't actually force suspend, since videocore may get into a bad state -+** if we force suspend at a bad time. Instead, we wait for autosuspend to -+** determine a good point to suspend. If this doesn't happen within 100ms we -+** report failure. -+** -+** Returns VCHIQ_SUCCESS if videocore suspended successfully, VCHIQ_RETRY if -+** videocore failed to suspend in time or VCHIQ_ERROR if interrupted. -+*/ -+VCHIQ_STATUS_T -+vchiq_arm_force_suspend(VCHIQ_STATE_T *state) -+{ -+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); -+ VCHIQ_STATUS_T status = VCHIQ_ERROR; -+ long rc = 0; -+ int repeat = -1; -+ -+ if (!arm_state) -+ goto out; -+ -+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); -+ -+ write_lock_bh(&arm_state->susp_res_lock); -+ -+ status = block_resume(arm_state); -+ if (status != VCHIQ_SUCCESS) -+ goto unlock; -+ if (arm_state->vc_suspend_state == VC_SUSPEND_SUSPENDED) { -+ /* Already suspended - just block resume and exit */ -+ vchiq_log_info(vchiq_susp_log_level, "%s already suspended", -+ __func__); -+ status = VCHIQ_SUCCESS; -+ goto unlock; -+ } else if (arm_state->vc_suspend_state <= VC_SUSPEND_IDLE) { -+ /* initiate suspend immediately in the case that we're waiting -+ * for the timeout */ -+ stop_suspend_timer(arm_state); -+ if (!vchiq_videocore_wanted(state)) { -+ vchiq_log_info(vchiq_susp_log_level, "%s videocore " -+ "idle, initiating suspend", __func__); -+ status = vchiq_arm_vcsuspend(state); -+ } else if (arm_state->autosuspend_override < -+ FORCE_SUSPEND_FAIL_MAX) { -+ vchiq_log_info(vchiq_susp_log_level, "%s letting " -+ "videocore go idle", __func__); -+ status = VCHIQ_SUCCESS; -+ } else { -+ vchiq_log_warning(vchiq_susp_log_level, "%s failed too " -+ "many times - attempting suspend", __func__); -+ status = vchiq_arm_vcsuspend(state); -+ } -+ } else { -+ vchiq_log_info(vchiq_susp_log_level, "%s videocore suspend " -+ "in progress - wait for completion", __func__); -+ status = VCHIQ_SUCCESS; -+ } -+ -+ /* Wait for suspend to happen due to system idle (not forced..) */ -+ if (status != VCHIQ_SUCCESS) -+ goto unblock_resume; -+ -+ do { -+ write_unlock_bh(&arm_state->susp_res_lock); -+ -+ rc = wait_for_completion_interruptible_timeout( -+ &arm_state->vc_suspend_complete, -+ msecs_to_jiffies(FORCE_SUSPEND_TIMEOUT_MS)); -+ -+ write_lock_bh(&arm_state->susp_res_lock); -+ if (rc < 0) { -+ vchiq_log_warning(vchiq_susp_log_level, "%s " -+ "interrupted waiting for suspend", __func__); -+ status = VCHIQ_ERROR; -+ goto unblock_resume; -+ } else if (rc == 0) { -+ if (arm_state->vc_suspend_state > VC_SUSPEND_IDLE) { -+ /* Repeat timeout once if in progress */ -+ if (repeat < 0) { -+ repeat = 1; -+ continue; -+ } -+ } -+ arm_state->autosuspend_override++; -+ output_timeout_error(state); -+ -+ status = VCHIQ_RETRY; -+ goto unblock_resume; -+ } -+ } while (0 < (repeat--)); -+ -+ /* Check and report state in case we need to abort ARM suspend */ -+ if (arm_state->vc_suspend_state != VC_SUSPEND_SUSPENDED) { -+ status = VCHIQ_RETRY; -+ vchiq_log_error(vchiq_susp_log_level, -+ "%s videocore suspend failed (state %s)", __func__, -+ suspend_state_names[arm_state->vc_suspend_state + -+ VC_SUSPEND_NUM_OFFSET]); -+ /* Reset the state only if it's still in an error state. -+ * Something could have already initiated another suspend. */ -+ if (arm_state->vc_suspend_state < VC_SUSPEND_IDLE) -+ set_suspend_state(arm_state, VC_SUSPEND_IDLE); -+ -+ goto unblock_resume; -+ } -+ -+ /* successfully suspended - unlock and exit */ -+ goto unlock; -+ -+unblock_resume: -+ /* all error states need to unblock resume before exit */ -+ unblock_resume(arm_state); -+ -+unlock: -+ write_unlock_bh(&arm_state->susp_res_lock); -+ -+out: -+ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, status); -+ return status; -+} -+ -+void -+vchiq_check_suspend(VCHIQ_STATE_T *state) -+{ -+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); -+ -+ if (!arm_state) -+ goto out; -+ -+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); -+ -+ write_lock_bh(&arm_state->susp_res_lock); -+ if (arm_state->vc_suspend_state != VC_SUSPEND_SUSPENDED && -+ arm_state->first_connect && -+ !vchiq_videocore_wanted(state)) { -+ vchiq_arm_vcsuspend(state); -+ } -+ write_unlock_bh(&arm_state->susp_res_lock); -+ -+out: -+ vchiq_log_trace(vchiq_susp_log_level, "%s exit", __func__); -+ return; -+} -+ -+ -+int -+vchiq_arm_allow_resume(VCHIQ_STATE_T *state) -+{ -+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); -+ int resume = 0; -+ int ret = -1; -+ -+ if (!arm_state) -+ goto out; -+ -+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); -+ -+ write_lock_bh(&arm_state->susp_res_lock); -+ unblock_resume(arm_state); -+ resume = vchiq_check_resume(state); -+ write_unlock_bh(&arm_state->susp_res_lock); -+ -+ if (resume) { -+ if (wait_for_completion_interruptible( -+ &arm_state->vc_resume_complete) < 0) { -+ vchiq_log_error(vchiq_susp_log_level, -+ "%s interrupted", __func__); -+ /* failed, cannot accurately derive suspend -+ * state, so exit early. */ -+ goto out; -+ } -+ } -+ -+ read_lock_bh(&arm_state->susp_res_lock); -+ if (arm_state->vc_suspend_state == VC_SUSPEND_SUSPENDED) { -+ vchiq_log_info(vchiq_susp_log_level, -+ "%s: Videocore remains suspended", __func__); -+ } else { -+ vchiq_log_info(vchiq_susp_log_level, -+ "%s: Videocore resumed", __func__); -+ ret = 0; -+ } -+ read_unlock_bh(&arm_state->susp_res_lock); -+out: -+ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, ret); -+ return ret; -+} -+ -+/* This function should be called with the write lock held */ -+int -+vchiq_check_resume(VCHIQ_STATE_T *state) -+{ -+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); -+ int resume = 0; -+ -+ if (!arm_state) -+ goto out; -+ -+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); -+ -+ if (need_resume(state)) { -+ set_resume_state(arm_state, VC_RESUME_REQUESTED); -+ request_poll(state, NULL, 0); -+ resume = 1; -+ } -+ -+out: -+ vchiq_log_trace(vchiq_susp_log_level, "%s exit", __func__); -+ return resume; -+} -+ -+void -+vchiq_platform_check_resume(VCHIQ_STATE_T *state) -+{ -+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); -+ int res = 0; -+ -+ if (!arm_state) -+ goto out; -+ -+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); -+ -+ write_lock_bh(&arm_state->susp_res_lock); -+ if (arm_state->wake_address == 0) { -+ vchiq_log_info(vchiq_susp_log_level, -+ "%s: already awake", __func__); -+ goto unlock; -+ } -+ if (arm_state->vc_resume_state == VC_RESUME_IN_PROGRESS) { -+ vchiq_log_info(vchiq_susp_log_level, -+ "%s: already resuming", __func__); -+ goto unlock; -+ } -+ -+ if (arm_state->vc_resume_state == VC_RESUME_REQUESTED) { -+ set_resume_state(arm_state, VC_RESUME_IN_PROGRESS); -+ res = 1; -+ } else -+ vchiq_log_trace(vchiq_susp_log_level, -+ "%s: not resuming (resume state %s)", __func__, -+ resume_state_names[arm_state->vc_resume_state + -+ VC_RESUME_NUM_OFFSET]); -+ -+unlock: -+ write_unlock_bh(&arm_state->susp_res_lock); -+ -+ if (res) -+ vchiq_platform_resume(state); -+ -+out: -+ vchiq_log_trace(vchiq_susp_log_level, "%s exit", __func__); -+ return; -+ -+} -+ -+ -+ -+VCHIQ_STATUS_T -+vchiq_use_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, -+ enum USE_TYPE_E use_type) -+{ -+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); -+ VCHIQ_STATUS_T ret = VCHIQ_SUCCESS; -+ char entity[16]; -+ int *entity_uc; -+ int local_uc, local_entity_uc; -+ -+ if (!arm_state) -+ goto out; -+ -+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); -+ -+ if (use_type == USE_TYPE_VCHIQ) { -+ sprintf(entity, "VCHIQ: "); -+ entity_uc = &arm_state->peer_use_count; -+ } else if (service) { -+ sprintf(entity, "%c%c%c%c:%03d", -+ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), -+ service->client_id); -+ entity_uc = &service->service_use_count; -+ } else { -+ vchiq_log_error(vchiq_susp_log_level, "%s null service " -+ "ptr", __func__); -+ ret = VCHIQ_ERROR; -+ goto out; -+ } -+ -+ write_lock_bh(&arm_state->susp_res_lock); -+ while (arm_state->resume_blocked) { -+ /* If we call 'use' while force suspend is waiting for suspend, -+ * then we're about to block the thread which the force is -+ * waiting to complete, so we're bound to just time out. In this -+ * case, set the suspend state such that the wait will be -+ * canceled, so we can complete as quickly as possible. */ -+ if (arm_state->resume_blocked && arm_state->vc_suspend_state == -+ VC_SUSPEND_IDLE) { -+ set_suspend_state(arm_state, VC_SUSPEND_FORCE_CANCELED); -+ break; -+ } -+ /* If suspend is already in progress then we need to block */ -+ if (!try_wait_for_completion(&arm_state->resume_blocker)) { -+ /* Indicate that there are threads waiting on the resume -+ * blocker. These need to be allowed to complete before -+ * a _second_ call to force suspend can complete, -+ * otherwise low priority threads might never actually -+ * continue */ -+ arm_state->blocked_count++; -+ write_unlock_bh(&arm_state->susp_res_lock); -+ vchiq_log_info(vchiq_susp_log_level, "%s %s resume " -+ "blocked - waiting...", __func__, entity); -+ if (wait_for_completion_killable( -+ &arm_state->resume_blocker) != 0) { -+ vchiq_log_error(vchiq_susp_log_level, "%s %s " -+ "wait for resume blocker interrupted", -+ __func__, entity); -+ ret = VCHIQ_ERROR; -+ write_lock_bh(&arm_state->susp_res_lock); -+ arm_state->blocked_count--; -+ write_unlock_bh(&arm_state->susp_res_lock); -+ goto out; -+ } -+ vchiq_log_info(vchiq_susp_log_level, "%s %s resume " -+ "unblocked", __func__, entity); -+ write_lock_bh(&arm_state->susp_res_lock); -+ if (--arm_state->blocked_count == 0) -+ complete_all(&arm_state->blocked_blocker); -+ } -+ } -+ -+ stop_suspend_timer(arm_state); -+ -+ local_uc = ++arm_state->videocore_use_count; -+ local_entity_uc = ++(*entity_uc); -+ -+ /* If there's a pending request which hasn't yet been serviced then -+ * just clear it. If we're past VC_SUSPEND_REQUESTED state then -+ * vc_resume_complete will block until we either resume or fail to -+ * suspend */ -+ if (arm_state->vc_suspend_state <= VC_SUSPEND_REQUESTED) -+ set_suspend_state(arm_state, VC_SUSPEND_IDLE); -+ -+ if ((use_type != USE_TYPE_SERVICE_NO_RESUME) && need_resume(state)) { -+ set_resume_state(arm_state, VC_RESUME_REQUESTED); -+ vchiq_log_info(vchiq_susp_log_level, -+ "%s %s count %d, state count %d", -+ __func__, entity, local_entity_uc, local_uc); -+ request_poll(state, NULL, 0); -+ } else -+ vchiq_log_trace(vchiq_susp_log_level, -+ "%s %s count %d, state count %d", -+ __func__, entity, *entity_uc, local_uc); -+ -+ -+ write_unlock_bh(&arm_state->susp_res_lock); -+ -+ /* Completion is in a done state when we're not suspended, so this won't -+ * block for the non-suspended case. */ -+ if (!try_wait_for_completion(&arm_state->vc_resume_complete)) { -+ vchiq_log_info(vchiq_susp_log_level, "%s %s wait for resume", -+ __func__, entity); -+ if (wait_for_completion_killable( -+ &arm_state->vc_resume_complete) != 0) { -+ vchiq_log_error(vchiq_susp_log_level, "%s %s wait for " -+ "resume interrupted", __func__, entity); -+ ret = VCHIQ_ERROR; -+ goto out; -+ } -+ vchiq_log_info(vchiq_susp_log_level, "%s %s resumed", __func__, -+ entity); -+ } -+ -+ if (ret == VCHIQ_SUCCESS) { -+ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; -+ long ack_cnt = atomic_xchg(&arm_state->ka_use_ack_count, 0); -+ while (ack_cnt && (status == VCHIQ_SUCCESS)) { -+ /* Send the use notify to videocore */ -+ status = vchiq_send_remote_use_active(state); -+ if (status == VCHIQ_SUCCESS) -+ ack_cnt--; -+ else -+ atomic_add(ack_cnt, -+ &arm_state->ka_use_ack_count); -+ } -+ } -+ -+out: -+ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, ret); -+ return ret; -+} -+ -+VCHIQ_STATUS_T -+vchiq_release_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service) -+{ -+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); -+ VCHIQ_STATUS_T ret = VCHIQ_SUCCESS; -+ char entity[16]; -+ int *entity_uc; -+ int local_uc, local_entity_uc; -+ -+ if (!arm_state) -+ goto out; -+ -+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); -+ -+ if (service) { -+ sprintf(entity, "%c%c%c%c:%03d", -+ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), -+ service->client_id); -+ entity_uc = &service->service_use_count; -+ } else { -+ sprintf(entity, "PEER: "); -+ entity_uc = &arm_state->peer_use_count; -+ } -+ -+ write_lock_bh(&arm_state->susp_res_lock); -+ if (!arm_state->videocore_use_count || !(*entity_uc)) { -+ /* Don't use BUG_ON - don't allow user thread to crash kernel */ -+ WARN_ON(!arm_state->videocore_use_count); -+ WARN_ON(!(*entity_uc)); -+ ret = VCHIQ_ERROR; -+ goto unlock; -+ } -+ local_uc = --arm_state->videocore_use_count; -+ local_entity_uc = --(*entity_uc); -+ -+ if (!vchiq_videocore_wanted(state)) { -+ if (vchiq_platform_use_suspend_timer() && -+ !arm_state->resume_blocked) { -+ /* Only use the timer if we're not trying to force -+ * suspend (=> resume_blocked) */ -+ start_suspend_timer(arm_state); -+ } else { -+ vchiq_log_info(vchiq_susp_log_level, -+ "%s %s count %d, state count %d - suspending", -+ __func__, entity, *entity_uc, -+ arm_state->videocore_use_count); -+ vchiq_arm_vcsuspend(state); -+ } -+ } else -+ vchiq_log_trace(vchiq_susp_log_level, -+ "%s %s count %d, state count %d", -+ __func__, entity, *entity_uc, -+ arm_state->videocore_use_count); -+ -+unlock: -+ write_unlock_bh(&arm_state->susp_res_lock); -+ -+out: -+ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, ret); -+ return ret; -+} -+ -+void -+vchiq_on_remote_use(VCHIQ_STATE_T *state) -+{ -+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); -+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); -+ atomic_inc(&arm_state->ka_use_count); -+ complete(&arm_state->ka_evt); -+} -+ -+void -+vchiq_on_remote_release(VCHIQ_STATE_T *state) -+{ -+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); -+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); -+ atomic_inc(&arm_state->ka_release_count); -+ complete(&arm_state->ka_evt); -+} -+ -+VCHIQ_STATUS_T -+vchiq_use_service_internal(VCHIQ_SERVICE_T *service) -+{ -+ return vchiq_use_internal(service->state, service, USE_TYPE_SERVICE); -+} -+ -+VCHIQ_STATUS_T -+vchiq_release_service_internal(VCHIQ_SERVICE_T *service) -+{ -+ return vchiq_release_internal(service->state, service); -+} -+ -+VCHIQ_DEBUGFS_NODE_T * -+vchiq_instance_get_debugfs_node(VCHIQ_INSTANCE_T instance) -+{ -+ return &instance->debugfs_node; -+} -+ -+int -+vchiq_instance_get_use_count(VCHIQ_INSTANCE_T instance) -+{ -+ VCHIQ_SERVICE_T *service; -+ int use_count = 0, i; -+ i = 0; -+ while ((service = next_service_by_instance(instance->state, -+ instance, &i)) != NULL) { -+ use_count += service->service_use_count; -+ unlock_service(service); -+ } -+ return use_count; -+} -+ -+int -+vchiq_instance_get_pid(VCHIQ_INSTANCE_T instance) -+{ -+ return instance->pid; -+} -+ -+int -+vchiq_instance_get_trace(VCHIQ_INSTANCE_T instance) -+{ -+ return instance->trace; -+} -+ -+void -+vchiq_instance_set_trace(VCHIQ_INSTANCE_T instance, int trace) -+{ -+ VCHIQ_SERVICE_T *service; -+ int i; -+ i = 0; -+ while ((service = next_service_by_instance(instance->state, -+ instance, &i)) != NULL) { -+ service->trace = trace; -+ unlock_service(service); -+ } -+ instance->trace = (trace != 0); -+} -+ -+static void suspend_timer_callback(unsigned long context) -+{ -+ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *)context; -+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); -+ if (!arm_state) -+ goto out; -+ vchiq_log_info(vchiq_susp_log_level, -+ "%s - suspend timer expired - check suspend", __func__); -+ vchiq_check_suspend(state); -+out: -+ return; -+} -+ -+VCHIQ_STATUS_T -+vchiq_use_service_no_resume(VCHIQ_SERVICE_HANDLE_T handle) -+{ -+ VCHIQ_STATUS_T ret = VCHIQ_ERROR; -+ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); -+ if (service) { -+ ret = vchiq_use_internal(service->state, service, -+ USE_TYPE_SERVICE_NO_RESUME); -+ unlock_service(service); -+ } -+ return ret; -+} -+ -+VCHIQ_STATUS_T -+vchiq_use_service(VCHIQ_SERVICE_HANDLE_T handle) -+{ -+ VCHIQ_STATUS_T ret = VCHIQ_ERROR; -+ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); -+ if (service) { -+ ret = vchiq_use_internal(service->state, service, -+ USE_TYPE_SERVICE); -+ unlock_service(service); -+ } -+ return ret; -+} -+ -+VCHIQ_STATUS_T -+vchiq_release_service(VCHIQ_SERVICE_HANDLE_T handle) -+{ -+ VCHIQ_STATUS_T ret = VCHIQ_ERROR; -+ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); -+ if (service) { -+ ret = vchiq_release_internal(service->state, service); -+ unlock_service(service); -+ } -+ return ret; -+} -+ -+void -+vchiq_dump_service_use_state(VCHIQ_STATE_T *state) -+{ -+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); -+ int i, j = 0; -+ /* Only dump 64 services */ -+ static const int local_max_services = 64; -+ /* If there's more than 64 services, only dump ones with -+ * non-zero counts */ -+ int only_nonzero = 0; -+ static const char *nz = "<-- preventing suspend"; -+ -+ enum vc_suspend_status vc_suspend_state; -+ enum vc_resume_status vc_resume_state; -+ int peer_count; -+ int vc_use_count; -+ int active_services; -+ struct service_data_struct { -+ int fourcc; -+ int clientid; -+ int use_count; -+ } service_data[local_max_services]; -+ -+ if (!arm_state) -+ return; -+ -+ read_lock_bh(&arm_state->susp_res_lock); -+ vc_suspend_state = arm_state->vc_suspend_state; -+ vc_resume_state = arm_state->vc_resume_state; -+ peer_count = arm_state->peer_use_count; -+ vc_use_count = arm_state->videocore_use_count; -+ active_services = state->unused_service; -+ if (active_services > local_max_services) -+ only_nonzero = 1; -+ -+ for (i = 0; (i < active_services) && (j < local_max_services); i++) { -+ VCHIQ_SERVICE_T *service_ptr = state->services[i]; -+ if (!service_ptr) -+ continue; -+ -+ if (only_nonzero && !service_ptr->service_use_count) -+ continue; -+ -+ if (service_ptr->srvstate != VCHIQ_SRVSTATE_FREE) { -+ service_data[j].fourcc = service_ptr->base.fourcc; -+ service_data[j].clientid = service_ptr->client_id; -+ service_data[j++].use_count = service_ptr-> -+ service_use_count; -+ } -+ } -+ -+ read_unlock_bh(&arm_state->susp_res_lock); -+ -+ vchiq_log_warning(vchiq_susp_log_level, -+ "-- Videcore suspend state: %s --", -+ suspend_state_names[vc_suspend_state + VC_SUSPEND_NUM_OFFSET]); -+ vchiq_log_warning(vchiq_susp_log_level, -+ "-- Videcore resume state: %s --", -+ resume_state_names[vc_resume_state + VC_RESUME_NUM_OFFSET]); -+ -+ if (only_nonzero) -+ vchiq_log_warning(vchiq_susp_log_level, "Too many active " -+ "services (%d). Only dumping up to first %d services " -+ "with non-zero use-count", active_services, -+ local_max_services); -+ -+ for (i = 0; i < j; i++) { -+ vchiq_log_warning(vchiq_susp_log_level, -+ "----- %c%c%c%c:%d service count %d %s", -+ VCHIQ_FOURCC_AS_4CHARS(service_data[i].fourcc), -+ service_data[i].clientid, -+ service_data[i].use_count, -+ service_data[i].use_count ? nz : ""); -+ } -+ vchiq_log_warning(vchiq_susp_log_level, -+ "----- VCHIQ use count count %d", peer_count); -+ vchiq_log_warning(vchiq_susp_log_level, -+ "--- Overall vchiq instance use count %d", vc_use_count); -+ -+ vchiq_dump_platform_use_state(state); -+} -+ -+VCHIQ_STATUS_T -+vchiq_check_service(VCHIQ_SERVICE_T *service) -+{ -+ VCHIQ_ARM_STATE_T *arm_state; -+ VCHIQ_STATUS_T ret = VCHIQ_ERROR; -+ -+ if (!service || !service->state) -+ goto out; -+ -+ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); -+ -+ arm_state = vchiq_platform_get_arm_state(service->state); -+ -+ read_lock_bh(&arm_state->susp_res_lock); -+ if (service->service_use_count) -+ ret = VCHIQ_SUCCESS; -+ read_unlock_bh(&arm_state->susp_res_lock); -+ -+ if (ret == VCHIQ_ERROR) { -+ vchiq_log_error(vchiq_susp_log_level, -+ "%s ERROR - %c%c%c%c:%d service count %d, " -+ "state count %d, videocore suspend state %s", __func__, -+ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), -+ service->client_id, service->service_use_count, -+ arm_state->videocore_use_count, -+ suspend_state_names[arm_state->vc_suspend_state + -+ VC_SUSPEND_NUM_OFFSET]); -+ vchiq_dump_service_use_state(service->state); -+ } -+out: -+ return ret; -+} -+ -+/* stub functions */ -+void vchiq_on_remote_use_active(VCHIQ_STATE_T *state) -+{ -+ (void)state; -+} -+ -+void vchiq_platform_conn_state_changed(VCHIQ_STATE_T *state, -+ VCHIQ_CONNSTATE_T oldstate, VCHIQ_CONNSTATE_T newstate) -+{ -+ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); -+ vchiq_log_info(vchiq_susp_log_level, "%d: %s->%s", state->id, -+ get_conn_state_name(oldstate), get_conn_state_name(newstate)); -+ if (state->conn_state == VCHIQ_CONNSTATE_CONNECTED) { -+ write_lock_bh(&arm_state->susp_res_lock); -+ if (!arm_state->first_connect) { -+ char threadname[10]; -+ arm_state->first_connect = 1; -+ write_unlock_bh(&arm_state->susp_res_lock); -+ snprintf(threadname, sizeof(threadname), "VCHIQka-%d", -+ state->id); -+ arm_state->ka_thread = kthread_create( -+ &vchiq_keepalive_thread_func, -+ (void *)state, -+ threadname); -+ if (arm_state->ka_thread == NULL) { -+ vchiq_log_error(vchiq_susp_log_level, -+ "vchiq: FATAL: couldn't create thread %s", -+ threadname); -+ } else { -+ wake_up_process(arm_state->ka_thread); -+ } -+ } else -+ write_unlock_bh(&arm_state->susp_res_lock); -+ } -+} -+ -+static int vchiq_probe(struct platform_device *pdev) -+{ -+ struct device_node *fw_node; -+ struct rpi_firmware *fw; -+ int err; -+ void *ptr_err; -+ -+ fw_node = of_parse_phandle(pdev->dev.of_node, "firmware", 0); -+/* Remove comment when booting without Device Tree is no longer supported -+ if (!fw_node) { -+ dev_err(&pdev->dev, "Missing firmware node\n"); -+ return -ENOENT; -+ } -+*/ -+ fw = rpi_firmware_get(fw_node); -+ if (!fw) -+ return -EPROBE_DEFER; -+ -+ platform_set_drvdata(pdev, fw); -+ -+ /* create debugfs entries */ -+ err = vchiq_debugfs_init(); -+ if (err != 0) -+ goto failed_debugfs_init; -+ -+ err = alloc_chrdev_region(&vchiq_devid, VCHIQ_MINOR, 1, DEVICE_NAME); -+ if (err != 0) { -+ vchiq_log_error(vchiq_arm_log_level, -+ "Unable to allocate device number"); -+ goto failed_alloc_chrdev; -+ } -+ cdev_init(&vchiq_cdev, &vchiq_fops); -+ vchiq_cdev.owner = THIS_MODULE; -+ err = cdev_add(&vchiq_cdev, vchiq_devid, 1); -+ if (err != 0) { -+ vchiq_log_error(vchiq_arm_log_level, -+ "Unable to register device"); -+ goto failed_cdev_add; -+ } -+ -+ /* create sysfs entries */ -+ vchiq_class = class_create(THIS_MODULE, DEVICE_NAME); -+ ptr_err = vchiq_class; -+ if (IS_ERR(ptr_err)) -+ goto failed_class_create; -+ -+ vchiq_dev = device_create(vchiq_class, NULL, -+ vchiq_devid, NULL, "vchiq"); -+ ptr_err = vchiq_dev; -+ if (IS_ERR(ptr_err)) -+ goto failed_device_create; -+ -+ err = vchiq_platform_init(pdev, &g_state); -+ if (err != 0) -+ goto failed_platform_init; -+ -+ vchiq_log_info(vchiq_arm_log_level, -+ "vchiq: initialised - version %d (min %d), device %d.%d", -+ VCHIQ_VERSION, VCHIQ_VERSION_MIN, -+ MAJOR(vchiq_devid), MINOR(vchiq_devid)); -+ -+ return 0; -+ -+failed_platform_init: -+ device_destroy(vchiq_class, vchiq_devid); -+failed_device_create: -+ class_destroy(vchiq_class); -+failed_class_create: -+ cdev_del(&vchiq_cdev); -+ err = PTR_ERR(ptr_err); -+failed_cdev_add: -+ unregister_chrdev_region(vchiq_devid, 1); -+failed_alloc_chrdev: -+ vchiq_debugfs_deinit(); -+failed_debugfs_init: -+ vchiq_log_warning(vchiq_arm_log_level, "could not load vchiq"); -+ return err; -+} -+ -+static int vchiq_remove(struct platform_device *pdev) -+{ -+ device_destroy(vchiq_class, vchiq_devid); -+ class_destroy(vchiq_class); -+ cdev_del(&vchiq_cdev); -+ unregister_chrdev_region(vchiq_devid, 1); -+ -+ return 0; -+} -+ -+static const struct of_device_id vchiq_of_match[] = { -+ { .compatible = "brcm,bcm2835-vchiq", }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, vchiq_of_match); -+ -+static struct platform_driver vchiq_driver = { -+ .driver = { -+ .name = "bcm2835_vchiq", -+ .owner = THIS_MODULE, -+ .of_match_table = vchiq_of_match, -+ }, -+ .probe = vchiq_probe, -+ .remove = vchiq_remove, -+}; -+module_platform_driver(vchiq_driver); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Broadcom Corporation"); -diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h ---- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h 2015-11-29 09:42:38.071221476 +0100 -@@ -0,0 +1,220 @@ -+/** -+ * Copyright (c) 2014 Raspberry Pi (Trading) Ltd. All rights reserved. -+ * Copyright (c) 2010-2012 Broadcom. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef VCHIQ_ARM_H -+#define VCHIQ_ARM_H -+ -+#include -+#include -+#include -+#include -+#include "vchiq_core.h" -+#include "vchiq_debugfs.h" -+ -+ -+enum vc_suspend_status { -+ VC_SUSPEND_FORCE_CANCELED = -3, /* Force suspend canceled, too busy */ -+ VC_SUSPEND_REJECTED = -2, /* Videocore rejected suspend request */ -+ VC_SUSPEND_FAILED = -1, /* Videocore suspend failed */ -+ VC_SUSPEND_IDLE = 0, /* VC active, no suspend actions */ -+ VC_SUSPEND_REQUESTED, /* User has requested suspend */ -+ VC_SUSPEND_IN_PROGRESS, /* Slot handler has recvd suspend request */ -+ VC_SUSPEND_SUSPENDED /* Videocore suspend succeeded */ -+}; -+ -+enum vc_resume_status { -+ VC_RESUME_FAILED = -1, /* Videocore resume failed */ -+ VC_RESUME_IDLE = 0, /* VC suspended, no resume actions */ -+ VC_RESUME_REQUESTED, /* User has requested resume */ -+ VC_RESUME_IN_PROGRESS, /* Slot handler has received resume request */ -+ VC_RESUME_RESUMED /* Videocore resumed successfully (active) */ -+}; -+ -+ -+enum USE_TYPE_E { -+ USE_TYPE_SERVICE, -+ USE_TYPE_SERVICE_NO_RESUME, -+ USE_TYPE_VCHIQ -+}; -+ -+ -+ -+typedef struct vchiq_arm_state_struct { -+ /* Keepalive-related data */ -+ struct task_struct *ka_thread; -+ struct completion ka_evt; -+ atomic_t ka_use_count; -+ atomic_t ka_use_ack_count; -+ atomic_t ka_release_count; -+ -+ struct completion vc_suspend_complete; -+ struct completion vc_resume_complete; -+ -+ rwlock_t susp_res_lock; -+ enum vc_suspend_status vc_suspend_state; -+ enum vc_resume_status vc_resume_state; -+ -+ unsigned int wake_address; -+ -+ struct timer_list suspend_timer; -+ int suspend_timer_timeout; -+ int suspend_timer_running; -+ -+ /* Global use count for videocore. -+ ** This is equal to the sum of the use counts for all services. When -+ ** this hits zero the videocore suspend procedure will be initiated. -+ */ -+ int videocore_use_count; -+ -+ /* Use count to track requests from videocore peer. -+ ** This use count is not associated with a service, so needs to be -+ ** tracked separately with the state. -+ */ -+ int peer_use_count; -+ -+ /* Flag to indicate whether resume is blocked. This happens when the -+ ** ARM is suspending -+ */ -+ struct completion resume_blocker; -+ int resume_blocked; -+ struct completion blocked_blocker; -+ int blocked_count; -+ -+ int autosuspend_override; -+ -+ /* Flag to indicate that the first vchiq connect has made it through. -+ ** This means that both sides should be fully ready, and we should -+ ** be able to suspend after this point. -+ */ -+ int first_connect; -+ -+ unsigned long long suspend_start_time; -+ unsigned long long sleep_start_time; -+ unsigned long long resume_start_time; -+ unsigned long long last_wake_time; -+ -+} VCHIQ_ARM_STATE_T; -+ -+extern int vchiq_arm_log_level; -+extern int vchiq_susp_log_level; -+ -+int vchiq_platform_init(struct platform_device *pdev, VCHIQ_STATE_T *state); -+ -+extern VCHIQ_STATE_T * -+vchiq_get_state(void); -+ -+extern VCHIQ_STATUS_T -+vchiq_arm_vcsuspend(VCHIQ_STATE_T *state); -+ -+extern VCHIQ_STATUS_T -+vchiq_arm_force_suspend(VCHIQ_STATE_T *state); -+ -+extern int -+vchiq_arm_allow_resume(VCHIQ_STATE_T *state); -+ -+extern VCHIQ_STATUS_T -+vchiq_arm_vcresume(VCHIQ_STATE_T *state); -+ -+extern VCHIQ_STATUS_T -+vchiq_arm_init_state(VCHIQ_STATE_T *state, VCHIQ_ARM_STATE_T *arm_state); -+ -+extern int -+vchiq_check_resume(VCHIQ_STATE_T *state); -+ -+extern void -+vchiq_check_suspend(VCHIQ_STATE_T *state); -+ VCHIQ_STATUS_T -+vchiq_use_service(VCHIQ_SERVICE_HANDLE_T handle); -+ -+extern VCHIQ_STATUS_T -+vchiq_release_service(VCHIQ_SERVICE_HANDLE_T handle); -+ -+extern VCHIQ_STATUS_T -+vchiq_check_service(VCHIQ_SERVICE_T *service); -+ -+extern VCHIQ_STATUS_T -+vchiq_platform_suspend(VCHIQ_STATE_T *state); -+ -+extern int -+vchiq_platform_videocore_wanted(VCHIQ_STATE_T *state); -+ -+extern int -+vchiq_platform_use_suspend_timer(void); -+ -+extern void -+vchiq_dump_platform_use_state(VCHIQ_STATE_T *state); -+ -+extern void -+vchiq_dump_service_use_state(VCHIQ_STATE_T *state); -+ -+extern VCHIQ_ARM_STATE_T* -+vchiq_platform_get_arm_state(VCHIQ_STATE_T *state); -+ -+extern int -+vchiq_videocore_wanted(VCHIQ_STATE_T *state); -+ -+extern VCHIQ_STATUS_T -+vchiq_use_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, -+ enum USE_TYPE_E use_type); -+extern VCHIQ_STATUS_T -+vchiq_release_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service); -+ -+extern VCHIQ_DEBUGFS_NODE_T * -+vchiq_instance_get_debugfs_node(VCHIQ_INSTANCE_T instance); -+ -+extern int -+vchiq_instance_get_use_count(VCHIQ_INSTANCE_T instance); -+ -+extern int -+vchiq_instance_get_pid(VCHIQ_INSTANCE_T instance); -+ -+extern int -+vchiq_instance_get_trace(VCHIQ_INSTANCE_T instance); -+ -+extern void -+vchiq_instance_set_trace(VCHIQ_INSTANCE_T instance, int trace); -+ -+extern void -+set_suspend_state(VCHIQ_ARM_STATE_T *arm_state, -+ enum vc_suspend_status new_state); -+ -+extern void -+set_resume_state(VCHIQ_ARM_STATE_T *arm_state, -+ enum vc_resume_status new_state); -+ -+extern void -+start_suspend_timer(VCHIQ_ARM_STATE_T *arm_state); -+ -+ -+#endif /* VCHIQ_ARM_H */ -diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_build_info.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_build_info.h ---- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_build_info.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_build_info.h 2015-11-29 09:42:38.071221476 +0100 -@@ -0,0 +1,37 @@ -+/** -+ * Copyright (c) 2010-2012 Broadcom. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+const char *vchiq_get_build_hostname(void); -+const char *vchiq_get_build_version(void); -+const char *vchiq_get_build_time(void); -+const char *vchiq_get_build_date(void); -diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h ---- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h 2015-11-29 09:42:38.071221476 +0100 -@@ -0,0 +1,69 @@ -+/** -+ * Copyright (c) 2010-2014 Broadcom. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef VCHIQ_CFG_H -+#define VCHIQ_CFG_H -+ -+#define VCHIQ_MAGIC VCHIQ_MAKE_FOURCC('V', 'C', 'H', 'I') -+/* The version of VCHIQ - change with any non-trivial change */ -+#define VCHIQ_VERSION 8 -+/* The minimum compatible version - update to match VCHIQ_VERSION with any -+** incompatible change */ -+#define VCHIQ_VERSION_MIN 3 -+ -+/* The version that introduced the VCHIQ_IOC_LIB_VERSION ioctl */ -+#define VCHIQ_VERSION_LIB_VERSION 7 -+ -+/* The version that introduced the VCHIQ_IOC_CLOSE_DELIVERED ioctl */ -+#define VCHIQ_VERSION_CLOSE_DELIVERED 7 -+ -+/* The version that made it safe to use SYNCHRONOUS mode */ -+#define VCHIQ_VERSION_SYNCHRONOUS_MODE 8 -+ -+#define VCHIQ_MAX_STATES 1 -+#define VCHIQ_MAX_SERVICES 4096 -+#define VCHIQ_MAX_SLOTS 128 -+#define VCHIQ_MAX_SLOTS_PER_SIDE 64 -+ -+#define VCHIQ_NUM_CURRENT_BULKS 32 -+#define VCHIQ_NUM_SERVICE_BULKS 4 -+ -+#ifndef VCHIQ_ENABLE_DEBUG -+#define VCHIQ_ENABLE_DEBUG 1 -+#endif -+ -+#ifndef VCHIQ_ENABLE_STATS -+#define VCHIQ_ENABLE_STATS 1 -+#endif -+ -+#endif /* VCHIQ_CFG_H */ -diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.c ---- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.c 2015-11-29 09:42:38.071221476 +0100 -@@ -0,0 +1,120 @@ -+/** -+ * Copyright (c) 2010-2012 Broadcom. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include "vchiq_connected.h" -+#include "vchiq_core.h" -+#include "vchiq_killable.h" -+#include -+#include -+ -+#define MAX_CALLBACKS 10 -+ -+static int g_connected; -+static int g_num_deferred_callbacks; -+static VCHIQ_CONNECTED_CALLBACK_T g_deferred_callback[MAX_CALLBACKS]; -+static int g_once_init; -+static struct mutex g_connected_mutex; -+ -+/**************************************************************************** -+* -+* Function to initialize our lock. -+* -+***************************************************************************/ -+ -+static void connected_init(void) -+{ -+ if (!g_once_init) { -+ mutex_init(&g_connected_mutex); -+ g_once_init = 1; -+ } -+} -+ -+/**************************************************************************** -+* -+* This function is used to defer initialization until the vchiq stack is -+* initialized. If the stack is already initialized, then the callback will -+* be made immediately, otherwise it will be deferred until -+* vchiq_call_connected_callbacks is called. -+* -+***************************************************************************/ -+ -+void vchiq_add_connected_callback(VCHIQ_CONNECTED_CALLBACK_T callback) -+{ -+ connected_init(); -+ -+ if (mutex_lock_interruptible(&g_connected_mutex) != 0) -+ return; -+ -+ if (g_connected) -+ /* We're already connected. Call the callback immediately. */ -+ -+ callback(); -+ else { -+ if (g_num_deferred_callbacks >= MAX_CALLBACKS) -+ vchiq_log_error(vchiq_core_log_level, -+ "There already %d callback registered - " -+ "please increase MAX_CALLBACKS", -+ g_num_deferred_callbacks); -+ else { -+ g_deferred_callback[g_num_deferred_callbacks] = -+ callback; -+ g_num_deferred_callbacks++; -+ } -+ } -+ mutex_unlock(&g_connected_mutex); -+} -+ -+/**************************************************************************** -+* -+* This function is called by the vchiq stack once it has been connected to -+* the videocore and clients can start to use the stack. -+* -+***************************************************************************/ -+ -+void vchiq_call_connected_callbacks(void) -+{ -+ int i; -+ -+ connected_init(); -+ -+ if (mutex_lock_interruptible(&g_connected_mutex) != 0) -+ return; -+ -+ for (i = 0; i < g_num_deferred_callbacks; i++) -+ g_deferred_callback[i](); -+ -+ g_num_deferred_callbacks = 0; -+ g_connected = 1; -+ mutex_unlock(&g_connected_mutex); -+} -+EXPORT_SYMBOL(vchiq_add_connected_callback); -diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.h ---- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.h 2015-11-29 09:42:38.075221210 +0100 -@@ -0,0 +1,50 @@ -+/** -+ * Copyright (c) 2010-2012 Broadcom. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef VCHIQ_CONNECTED_H -+#define VCHIQ_CONNECTED_H -+ -+/* ---- Include Files ----------------------------------------------------- */ -+ -+/* ---- Constants and Types ---------------------------------------------- */ -+ -+typedef void (*VCHIQ_CONNECTED_CALLBACK_T)(void); -+ -+/* ---- Variable Externs ------------------------------------------------- */ -+ -+/* ---- Function Prototypes ---------------------------------------------- */ -+ -+void vchiq_add_connected_callback(VCHIQ_CONNECTED_CALLBACK_T callback); -+void vchiq_call_connected_callbacks(void); -+ -+#endif /* VCHIQ_CONNECTED_H */ -diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c ---- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c 2015-11-29 09:42:38.075221210 +0100 -@@ -0,0 +1,3934 @@ -+/** -+ * Copyright (c) 2010-2012 Broadcom. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include "vchiq_core.h" -+#include "vchiq_killable.h" -+ -+#define VCHIQ_SLOT_HANDLER_STACK 8192 -+ -+#define HANDLE_STATE_SHIFT 12 -+ -+#define SLOT_INFO_FROM_INDEX(state, index) (state->slot_info + (index)) -+#define SLOT_DATA_FROM_INDEX(state, index) (state->slot_data + (index)) -+#define SLOT_INDEX_FROM_DATA(state, data) \ -+ (((unsigned int)((char *)data - (char *)state->slot_data)) / \ -+ VCHIQ_SLOT_SIZE) -+#define SLOT_INDEX_FROM_INFO(state, info) \ -+ ((unsigned int)(info - state->slot_info)) -+#define SLOT_QUEUE_INDEX_FROM_POS(pos) \ -+ ((int)((unsigned int)(pos) / VCHIQ_SLOT_SIZE)) -+ -+#define BULK_INDEX(x) (x & (VCHIQ_NUM_SERVICE_BULKS - 1)) -+ -+#define SRVTRACE_LEVEL(srv) \ -+ (((srv) && (srv)->trace) ? VCHIQ_LOG_TRACE : vchiq_core_msg_log_level) -+#define SRVTRACE_ENABLED(srv, lev) \ -+ (((srv) && (srv)->trace) || (vchiq_core_msg_log_level >= (lev))) -+ -+struct vchiq_open_payload { -+ int fourcc; -+ int client_id; -+ short version; -+ short version_min; -+}; -+ -+struct vchiq_openack_payload { -+ short version; -+}; -+ -+enum -+{ -+ QMFLAGS_IS_BLOCKING = (1 << 0), -+ QMFLAGS_NO_MUTEX_LOCK = (1 << 1), -+ QMFLAGS_NO_MUTEX_UNLOCK = (1 << 2) -+}; -+ -+/* we require this for consistency between endpoints */ -+vchiq_static_assert(sizeof(VCHIQ_HEADER_T) == 8); -+vchiq_static_assert(IS_POW2(sizeof(VCHIQ_HEADER_T))); -+vchiq_static_assert(IS_POW2(VCHIQ_NUM_CURRENT_BULKS)); -+vchiq_static_assert(IS_POW2(VCHIQ_NUM_SERVICE_BULKS)); -+vchiq_static_assert(IS_POW2(VCHIQ_MAX_SERVICES)); -+vchiq_static_assert(VCHIQ_VERSION >= VCHIQ_VERSION_MIN); -+ -+/* Run time control of log level, based on KERN_XXX level. */ -+int vchiq_core_log_level = VCHIQ_LOG_DEFAULT; -+int vchiq_core_msg_log_level = VCHIQ_LOG_DEFAULT; -+int vchiq_sync_log_level = VCHIQ_LOG_DEFAULT; -+ -+static atomic_t pause_bulks_count = ATOMIC_INIT(0); -+ -+static DEFINE_SPINLOCK(service_spinlock); -+DEFINE_SPINLOCK(bulk_waiter_spinlock); -+DEFINE_SPINLOCK(quota_spinlock); -+ -+VCHIQ_STATE_T *vchiq_states[VCHIQ_MAX_STATES]; -+static unsigned int handle_seq; -+ -+static const char *const srvstate_names[] = { -+ "FREE", -+ "HIDDEN", -+ "LISTENING", -+ "OPENING", -+ "OPEN", -+ "OPENSYNC", -+ "CLOSESENT", -+ "CLOSERECVD", -+ "CLOSEWAIT", -+ "CLOSED" -+}; -+ -+static const char *const reason_names[] = { -+ "SERVICE_OPENED", -+ "SERVICE_CLOSED", -+ "MESSAGE_AVAILABLE", -+ "BULK_TRANSMIT_DONE", -+ "BULK_RECEIVE_DONE", -+ "BULK_TRANSMIT_ABORTED", -+ "BULK_RECEIVE_ABORTED" -+}; -+ -+static const char *const conn_state_names[] = { -+ "DISCONNECTED", -+ "CONNECTING", -+ "CONNECTED", -+ "PAUSING", -+ "PAUSE_SENT", -+ "PAUSED", -+ "RESUMING", -+ "PAUSE_TIMEOUT", -+ "RESUME_TIMEOUT" -+}; -+ -+ -+static void -+release_message_sync(VCHIQ_STATE_T *state, VCHIQ_HEADER_T *header); -+ -+static const char *msg_type_str(unsigned int msg_type) -+{ -+ switch (msg_type) { -+ case VCHIQ_MSG_PADDING: return "PADDING"; -+ case VCHIQ_MSG_CONNECT: return "CONNECT"; -+ case VCHIQ_MSG_OPEN: return "OPEN"; -+ case VCHIQ_MSG_OPENACK: return "OPENACK"; -+ case VCHIQ_MSG_CLOSE: return "CLOSE"; -+ case VCHIQ_MSG_DATA: return "DATA"; -+ case VCHIQ_MSG_BULK_RX: return "BULK_RX"; -+ case VCHIQ_MSG_BULK_TX: return "BULK_TX"; -+ case VCHIQ_MSG_BULK_RX_DONE: return "BULK_RX_DONE"; -+ case VCHIQ_MSG_BULK_TX_DONE: return "BULK_TX_DONE"; -+ case VCHIQ_MSG_PAUSE: return "PAUSE"; -+ case VCHIQ_MSG_RESUME: return "RESUME"; -+ case VCHIQ_MSG_REMOTE_USE: return "REMOTE_USE"; -+ case VCHIQ_MSG_REMOTE_RELEASE: return "REMOTE_RELEASE"; -+ case VCHIQ_MSG_REMOTE_USE_ACTIVE: return "REMOTE_USE_ACTIVE"; -+ } -+ return "???"; -+} -+ -+static inline void -+vchiq_set_service_state(VCHIQ_SERVICE_T *service, int newstate) -+{ -+ vchiq_log_info(vchiq_core_log_level, "%d: srv:%d %s->%s", -+ service->state->id, service->localport, -+ srvstate_names[service->srvstate], -+ srvstate_names[newstate]); -+ service->srvstate = newstate; -+} -+ -+VCHIQ_SERVICE_T * -+find_service_by_handle(VCHIQ_SERVICE_HANDLE_T handle) -+{ -+ VCHIQ_SERVICE_T *service; -+ -+ spin_lock(&service_spinlock); -+ service = handle_to_service(handle); -+ if (service && (service->srvstate != VCHIQ_SRVSTATE_FREE) && -+ (service->handle == handle)) { -+ BUG_ON(service->ref_count == 0); -+ service->ref_count++; -+ } else -+ service = NULL; -+ spin_unlock(&service_spinlock); -+ -+ if (!service) -+ vchiq_log_info(vchiq_core_log_level, -+ "Invalid service handle 0x%x", handle); -+ -+ return service; -+} -+ -+VCHIQ_SERVICE_T * -+find_service_by_port(VCHIQ_STATE_T *state, int localport) -+{ -+ VCHIQ_SERVICE_T *service = NULL; -+ if ((unsigned int)localport <= VCHIQ_PORT_MAX) { -+ spin_lock(&service_spinlock); -+ service = state->services[localport]; -+ if (service && (service->srvstate != VCHIQ_SRVSTATE_FREE)) { -+ BUG_ON(service->ref_count == 0); -+ service->ref_count++; -+ } else -+ service = NULL; -+ spin_unlock(&service_spinlock); -+ } -+ -+ if (!service) -+ vchiq_log_info(vchiq_core_log_level, -+ "Invalid port %d", localport); -+ -+ return service; -+} -+ -+VCHIQ_SERVICE_T * -+find_service_for_instance(VCHIQ_INSTANCE_T instance, -+ VCHIQ_SERVICE_HANDLE_T handle) { -+ VCHIQ_SERVICE_T *service; -+ -+ spin_lock(&service_spinlock); -+ service = handle_to_service(handle); -+ if (service && (service->srvstate != VCHIQ_SRVSTATE_FREE) && -+ (service->handle == handle) && -+ (service->instance == instance)) { -+ BUG_ON(service->ref_count == 0); -+ service->ref_count++; -+ } else -+ service = NULL; -+ spin_unlock(&service_spinlock); -+ -+ if (!service) -+ vchiq_log_info(vchiq_core_log_level, -+ "Invalid service handle 0x%x", handle); -+ -+ return service; -+} -+ -+VCHIQ_SERVICE_T * -+find_closed_service_for_instance(VCHIQ_INSTANCE_T instance, -+ VCHIQ_SERVICE_HANDLE_T handle) { -+ VCHIQ_SERVICE_T *service; -+ -+ spin_lock(&service_spinlock); -+ service = handle_to_service(handle); -+ if (service && -+ ((service->srvstate == VCHIQ_SRVSTATE_FREE) || -+ (service->srvstate == VCHIQ_SRVSTATE_CLOSED)) && -+ (service->handle == handle) && -+ (service->instance == instance)) { -+ BUG_ON(service->ref_count == 0); -+ service->ref_count++; -+ } else -+ service = NULL; -+ spin_unlock(&service_spinlock); -+ -+ if (!service) -+ vchiq_log_info(vchiq_core_log_level, -+ "Invalid service handle 0x%x", handle); -+ -+ return service; -+} -+ -+VCHIQ_SERVICE_T * -+next_service_by_instance(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance, -+ int *pidx) -+{ -+ VCHIQ_SERVICE_T *service = NULL; -+ int idx = *pidx; -+ -+ spin_lock(&service_spinlock); -+ while (idx < state->unused_service) { -+ VCHIQ_SERVICE_T *srv = state->services[idx++]; -+ if (srv && (srv->srvstate != VCHIQ_SRVSTATE_FREE) && -+ (srv->instance == instance)) { -+ service = srv; -+ BUG_ON(service->ref_count == 0); -+ service->ref_count++; -+ break; -+ } -+ } -+ spin_unlock(&service_spinlock); -+ -+ *pidx = idx; -+ -+ return service; -+} -+ -+void -+lock_service(VCHIQ_SERVICE_T *service) -+{ -+ spin_lock(&service_spinlock); -+ BUG_ON(!service || (service->ref_count == 0)); -+ if (service) -+ service->ref_count++; -+ spin_unlock(&service_spinlock); -+} -+ -+void -+unlock_service(VCHIQ_SERVICE_T *service) -+{ -+ VCHIQ_STATE_T *state = service->state; -+ spin_lock(&service_spinlock); -+ BUG_ON(!service || (service->ref_count == 0)); -+ if (service && service->ref_count) { -+ service->ref_count--; -+ if (!service->ref_count) { -+ BUG_ON(service->srvstate != VCHIQ_SRVSTATE_FREE); -+ state->services[service->localport] = NULL; -+ } else -+ service = NULL; -+ } -+ spin_unlock(&service_spinlock); -+ -+ if (service && service->userdata_term) -+ service->userdata_term(service->base.userdata); -+ -+ kfree(service); -+} -+ -+int -+vchiq_get_client_id(VCHIQ_SERVICE_HANDLE_T handle) -+{ -+ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); -+ int id; -+ -+ id = service ? service->client_id : 0; -+ if (service) -+ unlock_service(service); -+ -+ return id; -+} -+ -+void * -+vchiq_get_service_userdata(VCHIQ_SERVICE_HANDLE_T handle) -+{ -+ VCHIQ_SERVICE_T *service = handle_to_service(handle); -+ -+ return service ? service->base.userdata : NULL; -+} -+ -+int -+vchiq_get_service_fourcc(VCHIQ_SERVICE_HANDLE_T handle) -+{ -+ VCHIQ_SERVICE_T *service = handle_to_service(handle); -+ -+ return service ? service->base.fourcc : 0; -+} -+ -+static void -+mark_service_closing_internal(VCHIQ_SERVICE_T *service, int sh_thread) -+{ -+ VCHIQ_STATE_T *state = service->state; -+ VCHIQ_SERVICE_QUOTA_T *service_quota; -+ -+ service->closing = 1; -+ -+ /* Synchronise with other threads. */ -+ mutex_lock(&state->recycle_mutex); -+ mutex_unlock(&state->recycle_mutex); -+ if (!sh_thread || (state->conn_state != VCHIQ_CONNSTATE_PAUSE_SENT)) { -+ /* If we're pausing then the slot_mutex is held until resume -+ * by the slot handler. Therefore don't try to acquire this -+ * mutex if we're the slot handler and in the pause sent state. -+ * We don't need to in this case anyway. */ -+ mutex_lock(&state->slot_mutex); -+ mutex_unlock(&state->slot_mutex); -+ } -+ -+ /* Unblock any sending thread. */ -+ service_quota = &state->service_quotas[service->localport]; -+ up(&service_quota->quota_event); -+} -+ -+static void -+mark_service_closing(VCHIQ_SERVICE_T *service) -+{ -+ mark_service_closing_internal(service, 0); -+} -+ -+static inline VCHIQ_STATUS_T -+make_service_callback(VCHIQ_SERVICE_T *service, VCHIQ_REASON_T reason, -+ VCHIQ_HEADER_T *header, void *bulk_userdata) -+{ -+ VCHIQ_STATUS_T status; -+ vchiq_log_trace(vchiq_core_log_level, "%d: callback:%d (%s, %x, %x)", -+ service->state->id, service->localport, reason_names[reason], -+ (unsigned int)header, (unsigned int)bulk_userdata); -+ status = service->base.callback(reason, header, service->handle, -+ bulk_userdata); -+ if (status == VCHIQ_ERROR) { -+ vchiq_log_warning(vchiq_core_log_level, -+ "%d: ignoring ERROR from callback to service %x", -+ service->state->id, service->handle); -+ status = VCHIQ_SUCCESS; -+ } -+ return status; -+} -+ -+inline void -+vchiq_set_conn_state(VCHIQ_STATE_T *state, VCHIQ_CONNSTATE_T newstate) -+{ -+ VCHIQ_CONNSTATE_T oldstate = state->conn_state; -+ vchiq_log_info(vchiq_core_log_level, "%d: %s->%s", state->id, -+ conn_state_names[oldstate], -+ conn_state_names[newstate]); -+ state->conn_state = newstate; -+ vchiq_platform_conn_state_changed(state, oldstate, newstate); -+} -+ -+static inline void -+remote_event_create(REMOTE_EVENT_T *event) -+{ -+ event->armed = 0; -+ /* Don't clear the 'fired' flag because it may already have been set -+ ** by the other side. */ -+ sema_init(event->event, 0); -+} -+ -+static inline void -+remote_event_destroy(REMOTE_EVENT_T *event) -+{ -+ (void)event; -+} -+ -+static inline int -+remote_event_wait(REMOTE_EVENT_T *event) -+{ -+ if (!event->fired) { -+ event->armed = 1; -+ dsb(); -+ if (!event->fired) { -+ if (down_interruptible(event->event) != 0) { -+ event->armed = 0; -+ return 0; -+ } -+ } -+ event->armed = 0; -+ wmb(); -+ } -+ -+ event->fired = 0; -+ return 1; -+} -+ -+static inline void -+remote_event_signal_local(REMOTE_EVENT_T *event) -+{ -+ event->armed = 0; -+ up(event->event); -+} -+ -+static inline void -+remote_event_poll(REMOTE_EVENT_T *event) -+{ -+ if (event->fired && event->armed) -+ remote_event_signal_local(event); -+} -+ -+void -+remote_event_pollall(VCHIQ_STATE_T *state) -+{ -+ remote_event_poll(&state->local->sync_trigger); -+ remote_event_poll(&state->local->sync_release); -+ remote_event_poll(&state->local->trigger); -+ remote_event_poll(&state->local->recycle); -+} -+ -+/* Round up message sizes so that any space at the end of a slot is always big -+** enough for a header. This relies on header size being a power of two, which -+** has been verified earlier by a static assertion. */ -+ -+static inline unsigned int -+calc_stride(unsigned int size) -+{ -+ /* Allow room for the header */ -+ size += sizeof(VCHIQ_HEADER_T); -+ -+ /* Round up */ -+ return (size + sizeof(VCHIQ_HEADER_T) - 1) & ~(sizeof(VCHIQ_HEADER_T) -+ - 1); -+} -+ -+/* Called by the slot handler thread */ -+static VCHIQ_SERVICE_T * -+get_listening_service(VCHIQ_STATE_T *state, int fourcc) -+{ -+ int i; -+ -+ WARN_ON(fourcc == VCHIQ_FOURCC_INVALID); -+ -+ for (i = 0; i < state->unused_service; i++) { -+ VCHIQ_SERVICE_T *service = state->services[i]; -+ if (service && -+ (service->public_fourcc == fourcc) && -+ ((service->srvstate == VCHIQ_SRVSTATE_LISTENING) || -+ ((service->srvstate == VCHIQ_SRVSTATE_OPEN) && -+ (service->remoteport == VCHIQ_PORT_FREE)))) { -+ lock_service(service); -+ return service; -+ } -+ } -+ -+ return NULL; -+} -+ -+/* Called by the slot handler thread */ -+static VCHIQ_SERVICE_T * -+get_connected_service(VCHIQ_STATE_T *state, unsigned int port) -+{ -+ int i; -+ for (i = 0; i < state->unused_service; i++) { -+ VCHIQ_SERVICE_T *service = state->services[i]; -+ if (service && (service->srvstate == VCHIQ_SRVSTATE_OPEN) -+ && (service->remoteport == port)) { -+ lock_service(service); -+ return service; -+ } -+ } -+ return NULL; -+} -+ -+inline void -+request_poll(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, int poll_type) -+{ -+ uint32_t value; -+ -+ if (service) { -+ do { -+ value = atomic_read(&service->poll_flags); -+ } while (atomic_cmpxchg(&service->poll_flags, value, -+ value | (1 << poll_type)) != value); -+ -+ do { -+ value = atomic_read(&state->poll_services[ -+ service->localport>>5]); -+ } while (atomic_cmpxchg( -+ &state->poll_services[service->localport>>5], -+ value, value | (1 << (service->localport & 0x1f))) -+ != value); -+ } -+ -+ state->poll_needed = 1; -+ wmb(); -+ -+ /* ... and ensure the slot handler runs. */ -+ remote_event_signal_local(&state->local->trigger); -+} -+ -+/* Called from queue_message, by the slot handler and application threads, -+** with slot_mutex held */ -+static VCHIQ_HEADER_T * -+reserve_space(VCHIQ_STATE_T *state, int space, int is_blocking) -+{ -+ VCHIQ_SHARED_STATE_T *local = state->local; -+ int tx_pos = state->local_tx_pos; -+ int slot_space = VCHIQ_SLOT_SIZE - (tx_pos & VCHIQ_SLOT_MASK); -+ -+ if (space > slot_space) { -+ VCHIQ_HEADER_T *header; -+ /* Fill the remaining space with padding */ -+ WARN_ON(state->tx_data == NULL); -+ header = (VCHIQ_HEADER_T *) -+ (state->tx_data + (tx_pos & VCHIQ_SLOT_MASK)); -+ header->msgid = VCHIQ_MSGID_PADDING; -+ header->size = slot_space - sizeof(VCHIQ_HEADER_T); -+ -+ tx_pos += slot_space; -+ } -+ -+ /* If necessary, get the next slot. */ -+ if ((tx_pos & VCHIQ_SLOT_MASK) == 0) { -+ int slot_index; -+ -+ /* If there is no free slot... */ -+ -+ if (down_trylock(&state->slot_available_event) != 0) { -+ /* ...wait for one. */ -+ -+ VCHIQ_STATS_INC(state, slot_stalls); -+ -+ /* But first, flush through the last slot. */ -+ state->local_tx_pos = tx_pos; -+ local->tx_pos = tx_pos; -+ remote_event_signal(&state->remote->trigger); -+ -+ if (!is_blocking || -+ (down_interruptible( -+ &state->slot_available_event) != 0)) -+ return NULL; /* No space available */ -+ } -+ -+ BUG_ON(tx_pos == -+ (state->slot_queue_available * VCHIQ_SLOT_SIZE)); -+ -+ slot_index = local->slot_queue[ -+ SLOT_QUEUE_INDEX_FROM_POS(tx_pos) & -+ VCHIQ_SLOT_QUEUE_MASK]; -+ state->tx_data = -+ (char *)SLOT_DATA_FROM_INDEX(state, slot_index); -+ } -+ -+ state->local_tx_pos = tx_pos + space; -+ -+ return (VCHIQ_HEADER_T *)(state->tx_data + (tx_pos & VCHIQ_SLOT_MASK)); -+} -+ -+/* Called by the recycle thread. */ -+static void -+process_free_queue(VCHIQ_STATE_T *state) -+{ -+ VCHIQ_SHARED_STATE_T *local = state->local; -+ BITSET_T service_found[BITSET_SIZE(VCHIQ_MAX_SERVICES)]; -+ int slot_queue_available; -+ -+ /* Use a read memory barrier to ensure that any state that may have -+ ** been modified by another thread is not masked by stale prefetched -+ ** values. */ -+ rmb(); -+ -+ /* Find slots which have been freed by the other side, and return them -+ ** to the available queue. */ -+ slot_queue_available = state->slot_queue_available; -+ -+ while (slot_queue_available != local->slot_queue_recycle) { -+ unsigned int pos; -+ int slot_index = local->slot_queue[slot_queue_available++ & -+ VCHIQ_SLOT_QUEUE_MASK]; -+ char *data = (char *)SLOT_DATA_FROM_INDEX(state, slot_index); -+ int data_found = 0; -+ -+ vchiq_log_trace(vchiq_core_log_level, "%d: pfq %d=%x %x %x", -+ state->id, slot_index, (unsigned int)data, -+ local->slot_queue_recycle, slot_queue_available); -+ -+ /* Initialise the bitmask for services which have used this -+ ** slot */ -+ BITSET_ZERO(service_found); -+ -+ pos = 0; -+ -+ while (pos < VCHIQ_SLOT_SIZE) { -+ VCHIQ_HEADER_T *header = -+ (VCHIQ_HEADER_T *)(data + pos); -+ int msgid = header->msgid; -+ if (VCHIQ_MSG_TYPE(msgid) == VCHIQ_MSG_DATA) { -+ int port = VCHIQ_MSG_SRCPORT(msgid); -+ VCHIQ_SERVICE_QUOTA_T *service_quota = -+ &state->service_quotas[port]; -+ int count; -+ spin_lock("a_spinlock); -+ count = service_quota->message_use_count; -+ if (count > 0) -+ service_quota->message_use_count = -+ count - 1; -+ spin_unlock("a_spinlock); -+ -+ if (count == service_quota->message_quota) -+ /* Signal the service that it -+ ** has dropped below its quota -+ */ -+ up(&service_quota->quota_event); -+ else if (count == 0) { -+ vchiq_log_error(vchiq_core_log_level, -+ "service %d " -+ "message_use_count=%d " -+ "(header %x, msgid %x, " -+ "header->msgid %x, " -+ "header->size %x)", -+ port, -+ service_quota-> -+ message_use_count, -+ (unsigned int)header, msgid, -+ header->msgid, -+ header->size); -+ WARN(1, "invalid message use count\n"); -+ } -+ if (!BITSET_IS_SET(service_found, port)) { -+ /* Set the found bit for this service */ -+ BITSET_SET(service_found, port); -+ -+ spin_lock("a_spinlock); -+ count = service_quota->slot_use_count; -+ if (count > 0) -+ service_quota->slot_use_count = -+ count - 1; -+ spin_unlock("a_spinlock); -+ -+ if (count > 0) { -+ /* Signal the service in case -+ ** it has dropped below its -+ ** quota */ -+ up(&service_quota->quota_event); -+ vchiq_log_trace( -+ vchiq_core_log_level, -+ "%d: pfq:%d %x@%x - " -+ "slot_use->%d", -+ state->id, port, -+ header->size, -+ (unsigned int)header, -+ count - 1); -+ } else { -+ vchiq_log_error( -+ vchiq_core_log_level, -+ "service %d " -+ "slot_use_count" -+ "=%d (header %x" -+ ", msgid %x, " -+ "header->msgid" -+ " %x, header->" -+ "size %x)", -+ port, count, -+ (unsigned int)header, -+ msgid, -+ header->msgid, -+ header->size); -+ WARN(1, "bad slot use count\n"); -+ } -+ } -+ -+ data_found = 1; -+ } -+ -+ pos += calc_stride(header->size); -+ if (pos > VCHIQ_SLOT_SIZE) { -+ vchiq_log_error(vchiq_core_log_level, -+ "pfq - pos %x: header %x, msgid %x, " -+ "header->msgid %x, header->size %x", -+ pos, (unsigned int)header, msgid, -+ header->msgid, header->size); -+ WARN(1, "invalid slot position\n"); -+ } -+ } -+ -+ if (data_found) { -+ int count; -+ spin_lock("a_spinlock); -+ count = state->data_use_count; -+ if (count > 0) -+ state->data_use_count = -+ count - 1; -+ spin_unlock("a_spinlock); -+ if (count == state->data_quota) -+ up(&state->data_quota_event); -+ } -+ -+ state->slot_queue_available = slot_queue_available; -+ up(&state->slot_available_event); -+ } -+} -+ -+/* Called by the slot handler and application threads */ -+static VCHIQ_STATUS_T -+queue_message(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, -+ int msgid, const VCHIQ_ELEMENT_T *elements, -+ int count, int size, int flags) -+{ -+ VCHIQ_SHARED_STATE_T *local; -+ VCHIQ_SERVICE_QUOTA_T *service_quota = NULL; -+ VCHIQ_HEADER_T *header; -+ int type = VCHIQ_MSG_TYPE(msgid); -+ -+ unsigned int stride; -+ -+ local = state->local; -+ -+ stride = calc_stride(size); -+ -+ WARN_ON(!(stride <= VCHIQ_SLOT_SIZE)); -+ -+ if (!(flags & QMFLAGS_NO_MUTEX_LOCK) && -+ (mutex_lock_interruptible(&state->slot_mutex) != 0)) -+ return VCHIQ_RETRY; -+ -+ if (type == VCHIQ_MSG_DATA) { -+ int tx_end_index; -+ -+ BUG_ON(!service); -+ BUG_ON((flags & (QMFLAGS_NO_MUTEX_LOCK | -+ QMFLAGS_NO_MUTEX_UNLOCK)) != 0); -+ -+ if (service->closing) { -+ /* The service has been closed */ -+ mutex_unlock(&state->slot_mutex); -+ return VCHIQ_ERROR; -+ } -+ -+ service_quota = &state->service_quotas[service->localport]; -+ -+ spin_lock("a_spinlock); -+ -+ /* Ensure this service doesn't use more than its quota of -+ ** messages or slots */ -+ tx_end_index = SLOT_QUEUE_INDEX_FROM_POS( -+ state->local_tx_pos + stride - 1); -+ -+ /* Ensure data messages don't use more than their quota of -+ ** slots */ -+ while ((tx_end_index != state->previous_data_index) && -+ (state->data_use_count == state->data_quota)) { -+ VCHIQ_STATS_INC(state, data_stalls); -+ spin_unlock("a_spinlock); -+ mutex_unlock(&state->slot_mutex); -+ -+ if (down_interruptible(&state->data_quota_event) -+ != 0) -+ return VCHIQ_RETRY; -+ -+ mutex_lock(&state->slot_mutex); -+ spin_lock("a_spinlock); -+ tx_end_index = SLOT_QUEUE_INDEX_FROM_POS( -+ state->local_tx_pos + stride - 1); -+ if ((tx_end_index == state->previous_data_index) || -+ (state->data_use_count < state->data_quota)) { -+ /* Pass the signal on to other waiters */ -+ up(&state->data_quota_event); -+ break; -+ } -+ } -+ -+ while ((service_quota->message_use_count == -+ service_quota->message_quota) || -+ ((tx_end_index != service_quota->previous_tx_index) && -+ (service_quota->slot_use_count == -+ service_quota->slot_quota))) { -+ spin_unlock("a_spinlock); -+ vchiq_log_trace(vchiq_core_log_level, -+ "%d: qm:%d %s,%x - quota stall " -+ "(msg %d, slot %d)", -+ state->id, service->localport, -+ msg_type_str(type), size, -+ service_quota->message_use_count, -+ service_quota->slot_use_count); -+ VCHIQ_SERVICE_STATS_INC(service, quota_stalls); -+ mutex_unlock(&state->slot_mutex); -+ if (down_interruptible(&service_quota->quota_event) -+ != 0) -+ return VCHIQ_RETRY; -+ if (service->closing) -+ return VCHIQ_ERROR; -+ if (mutex_lock_interruptible(&state->slot_mutex) != 0) -+ return VCHIQ_RETRY; -+ if (service->srvstate != VCHIQ_SRVSTATE_OPEN) { -+ /* The service has been closed */ -+ mutex_unlock(&state->slot_mutex); -+ return VCHIQ_ERROR; -+ } -+ spin_lock("a_spinlock); -+ tx_end_index = SLOT_QUEUE_INDEX_FROM_POS( -+ state->local_tx_pos + stride - 1); -+ } -+ -+ spin_unlock("a_spinlock); -+ } -+ -+ header = reserve_space(state, stride, flags & QMFLAGS_IS_BLOCKING); -+ -+ if (!header) { -+ if (service) -+ VCHIQ_SERVICE_STATS_INC(service, slot_stalls); -+ /* In the event of a failure, return the mutex to the -+ state it was in */ -+ if (!(flags & QMFLAGS_NO_MUTEX_LOCK)) -+ mutex_unlock(&state->slot_mutex); -+ return VCHIQ_RETRY; -+ } -+ -+ if (type == VCHIQ_MSG_DATA) { -+ int i, pos; -+ int tx_end_index; -+ int slot_use_count; -+ -+ vchiq_log_info(vchiq_core_log_level, -+ "%d: qm %s@%x,%x (%d->%d)", -+ state->id, -+ msg_type_str(VCHIQ_MSG_TYPE(msgid)), -+ (unsigned int)header, size, -+ VCHIQ_MSG_SRCPORT(msgid), -+ VCHIQ_MSG_DSTPORT(msgid)); -+ -+ BUG_ON(!service); -+ BUG_ON((flags & (QMFLAGS_NO_MUTEX_LOCK | -+ QMFLAGS_NO_MUTEX_UNLOCK)) != 0); -+ -+ for (i = 0, pos = 0; i < (unsigned int)count; -+ pos += elements[i++].size) -+ if (elements[i].size) { -+ if (vchiq_copy_from_user -+ (header->data + pos, elements[i].data, -+ (size_t) elements[i].size) != -+ VCHIQ_SUCCESS) { -+ mutex_unlock(&state->slot_mutex); -+ VCHIQ_SERVICE_STATS_INC(service, -+ error_count); -+ return VCHIQ_ERROR; -+ } -+ if (i == 0) { -+ if (SRVTRACE_ENABLED(service, -+ VCHIQ_LOG_INFO)) -+ vchiq_log_dump_mem("Sent", 0, -+ header->data + pos, -+ min(64u, -+ elements[0].size)); -+ } -+ } -+ -+ spin_lock("a_spinlock); -+ service_quota->message_use_count++; -+ -+ tx_end_index = -+ SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos - 1); -+ -+ /* If this transmission can't fit in the last slot used by any -+ ** service, the data_use_count must be increased. */ -+ if (tx_end_index != state->previous_data_index) { -+ state->previous_data_index = tx_end_index; -+ state->data_use_count++; -+ } -+ -+ /* If this isn't the same slot last used by this service, -+ ** the service's slot_use_count must be increased. */ -+ if (tx_end_index != service_quota->previous_tx_index) { -+ service_quota->previous_tx_index = tx_end_index; -+ slot_use_count = ++service_quota->slot_use_count; -+ } else { -+ slot_use_count = 0; -+ } -+ -+ spin_unlock("a_spinlock); -+ -+ if (slot_use_count) -+ vchiq_log_trace(vchiq_core_log_level, -+ "%d: qm:%d %s,%x - slot_use->%d (hdr %p)", -+ state->id, service->localport, -+ msg_type_str(VCHIQ_MSG_TYPE(msgid)), size, -+ slot_use_count, header); -+ -+ VCHIQ_SERVICE_STATS_INC(service, ctrl_tx_count); -+ VCHIQ_SERVICE_STATS_ADD(service, ctrl_tx_bytes, size); -+ } else { -+ vchiq_log_info(vchiq_core_log_level, -+ "%d: qm %s@%x,%x (%d->%d)", state->id, -+ msg_type_str(VCHIQ_MSG_TYPE(msgid)), -+ (unsigned int)header, size, -+ VCHIQ_MSG_SRCPORT(msgid), -+ VCHIQ_MSG_DSTPORT(msgid)); -+ if (size != 0) { -+ WARN_ON(!((count == 1) && (size == elements[0].size))); -+ memcpy(header->data, elements[0].data, -+ elements[0].size); -+ } -+ VCHIQ_STATS_INC(state, ctrl_tx_count); -+ } -+ -+ header->msgid = msgid; -+ header->size = size; -+ -+ { -+ int svc_fourcc; -+ -+ svc_fourcc = service -+ ? service->base.fourcc -+ : VCHIQ_MAKE_FOURCC('?', '?', '?', '?'); -+ -+ vchiq_log_info(SRVTRACE_LEVEL(service), -+ "Sent Msg %s(%u) to %c%c%c%c s:%u d:%d len:%d", -+ msg_type_str(VCHIQ_MSG_TYPE(msgid)), -+ VCHIQ_MSG_TYPE(msgid), -+ VCHIQ_FOURCC_AS_4CHARS(svc_fourcc), -+ VCHIQ_MSG_SRCPORT(msgid), -+ VCHIQ_MSG_DSTPORT(msgid), -+ size); -+ } -+ -+ /* Make sure the new header is visible to the peer. */ -+ wmb(); -+ -+ /* Make the new tx_pos visible to the peer. */ -+ local->tx_pos = state->local_tx_pos; -+ wmb(); -+ -+ if (service && (type == VCHIQ_MSG_CLOSE)) -+ vchiq_set_service_state(service, VCHIQ_SRVSTATE_CLOSESENT); -+ -+ if (!(flags & QMFLAGS_NO_MUTEX_UNLOCK)) -+ mutex_unlock(&state->slot_mutex); -+ -+ remote_event_signal(&state->remote->trigger); -+ -+ return VCHIQ_SUCCESS; -+} -+ -+/* Called by the slot handler and application threads */ -+static VCHIQ_STATUS_T -+queue_message_sync(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, -+ int msgid, const VCHIQ_ELEMENT_T *elements, -+ int count, int size, int is_blocking) -+{ -+ VCHIQ_SHARED_STATE_T *local; -+ VCHIQ_HEADER_T *header; -+ -+ local = state->local; -+ -+ if ((VCHIQ_MSG_TYPE(msgid) != VCHIQ_MSG_RESUME) && -+ (mutex_lock_interruptible(&state->sync_mutex) != 0)) -+ return VCHIQ_RETRY; -+ -+ remote_event_wait(&local->sync_release); -+ -+ rmb(); -+ -+ header = (VCHIQ_HEADER_T *)SLOT_DATA_FROM_INDEX(state, -+ local->slot_sync); -+ -+ { -+ int oldmsgid = header->msgid; -+ if (oldmsgid != VCHIQ_MSGID_PADDING) -+ vchiq_log_error(vchiq_core_log_level, -+ "%d: qms - msgid %x, not PADDING", -+ state->id, oldmsgid); -+ } -+ -+ if (service) { -+ int i, pos; -+ -+ vchiq_log_info(vchiq_sync_log_level, -+ "%d: qms %s@%x,%x (%d->%d)", state->id, -+ msg_type_str(VCHIQ_MSG_TYPE(msgid)), -+ (unsigned int)header, size, -+ VCHIQ_MSG_SRCPORT(msgid), -+ VCHIQ_MSG_DSTPORT(msgid)); -+ -+ for (i = 0, pos = 0; i < (unsigned int)count; -+ pos += elements[i++].size) -+ if (elements[i].size) { -+ if (vchiq_copy_from_user -+ (header->data + pos, elements[i].data, -+ (size_t) elements[i].size) != -+ VCHIQ_SUCCESS) { -+ mutex_unlock(&state->sync_mutex); -+ VCHIQ_SERVICE_STATS_INC(service, -+ error_count); -+ return VCHIQ_ERROR; -+ } -+ if (i == 0) { -+ if (vchiq_sync_log_level >= -+ VCHIQ_LOG_TRACE) -+ vchiq_log_dump_mem("Sent Sync", -+ 0, header->data + pos, -+ min(64u, -+ elements[0].size)); -+ } -+ } -+ -+ VCHIQ_SERVICE_STATS_INC(service, ctrl_tx_count); -+ VCHIQ_SERVICE_STATS_ADD(service, ctrl_tx_bytes, size); -+ } else { -+ vchiq_log_info(vchiq_sync_log_level, -+ "%d: qms %s@%x,%x (%d->%d)", state->id, -+ msg_type_str(VCHIQ_MSG_TYPE(msgid)), -+ (unsigned int)header, size, -+ VCHIQ_MSG_SRCPORT(msgid), -+ VCHIQ_MSG_DSTPORT(msgid)); -+ if (size != 0) { -+ WARN_ON(!((count == 1) && (size == elements[0].size))); -+ memcpy(header->data, elements[0].data, -+ elements[0].size); -+ } -+ VCHIQ_STATS_INC(state, ctrl_tx_count); -+ } -+ -+ header->size = size; -+ header->msgid = msgid; -+ -+ if (vchiq_sync_log_level >= VCHIQ_LOG_TRACE) { -+ int svc_fourcc; -+ -+ svc_fourcc = service -+ ? service->base.fourcc -+ : VCHIQ_MAKE_FOURCC('?', '?', '?', '?'); -+ -+ vchiq_log_trace(vchiq_sync_log_level, -+ "Sent Sync Msg %s(%u) to %c%c%c%c s:%u d:%d len:%d", -+ msg_type_str(VCHIQ_MSG_TYPE(msgid)), -+ VCHIQ_MSG_TYPE(msgid), -+ VCHIQ_FOURCC_AS_4CHARS(svc_fourcc), -+ VCHIQ_MSG_SRCPORT(msgid), -+ VCHIQ_MSG_DSTPORT(msgid), -+ size); -+ } -+ -+ /* Make sure the new header is visible to the peer. */ -+ wmb(); -+ -+ remote_event_signal(&state->remote->sync_trigger); -+ -+ if (VCHIQ_MSG_TYPE(msgid) != VCHIQ_MSG_PAUSE) -+ mutex_unlock(&state->sync_mutex); -+ -+ return VCHIQ_SUCCESS; -+} -+ -+static inline void -+claim_slot(VCHIQ_SLOT_INFO_T *slot) -+{ -+ slot->use_count++; -+} -+ -+static void -+release_slot(VCHIQ_STATE_T *state, VCHIQ_SLOT_INFO_T *slot_info, -+ VCHIQ_HEADER_T *header, VCHIQ_SERVICE_T *service) -+{ -+ int release_count; -+ -+ mutex_lock(&state->recycle_mutex); -+ -+ if (header) { -+ int msgid = header->msgid; -+ if (((msgid & VCHIQ_MSGID_CLAIMED) == 0) || -+ (service && service->closing)) { -+ mutex_unlock(&state->recycle_mutex); -+ return; -+ } -+ -+ /* Rewrite the message header to prevent a double -+ ** release */ -+ header->msgid = msgid & ~VCHIQ_MSGID_CLAIMED; -+ } -+ -+ release_count = slot_info->release_count; -+ slot_info->release_count = ++release_count; -+ -+ if (release_count == slot_info->use_count) { -+ int slot_queue_recycle; -+ /* Add to the freed queue */ -+ -+ /* A read barrier is necessary here to prevent speculative -+ ** fetches of remote->slot_queue_recycle from overtaking the -+ ** mutex. */ -+ rmb(); -+ -+ slot_queue_recycle = state->remote->slot_queue_recycle; -+ state->remote->slot_queue[slot_queue_recycle & -+ VCHIQ_SLOT_QUEUE_MASK] = -+ SLOT_INDEX_FROM_INFO(state, slot_info); -+ state->remote->slot_queue_recycle = slot_queue_recycle + 1; -+ vchiq_log_info(vchiq_core_log_level, -+ "%d: release_slot %d - recycle->%x", -+ state->id, SLOT_INDEX_FROM_INFO(state, slot_info), -+ state->remote->slot_queue_recycle); -+ -+ /* A write barrier is necessary, but remote_event_signal -+ ** contains one. */ -+ remote_event_signal(&state->remote->recycle); -+ } -+ -+ mutex_unlock(&state->recycle_mutex); -+} -+ -+/* Called by the slot handler - don't hold the bulk mutex */ -+static VCHIQ_STATUS_T -+notify_bulks(VCHIQ_SERVICE_T *service, VCHIQ_BULK_QUEUE_T *queue, -+ int retry_poll) -+{ -+ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; -+ -+ vchiq_log_trace(vchiq_core_log_level, -+ "%d: nb:%d %cx - p=%x rn=%x r=%x", -+ service->state->id, service->localport, -+ (queue == &service->bulk_tx) ? 't' : 'r', -+ queue->process, queue->remote_notify, queue->remove); -+ -+ if (service->state->is_master) { -+ while (queue->remote_notify != queue->process) { -+ VCHIQ_BULK_T *bulk = -+ &queue->bulks[BULK_INDEX(queue->remote_notify)]; -+ int msgtype = (bulk->dir == VCHIQ_BULK_TRANSMIT) ? -+ VCHIQ_MSG_BULK_RX_DONE : VCHIQ_MSG_BULK_TX_DONE; -+ int msgid = VCHIQ_MAKE_MSG(msgtype, service->localport, -+ service->remoteport); -+ VCHIQ_ELEMENT_T element = { &bulk->actual, 4 }; -+ /* Only reply to non-dummy bulk requests */ -+ if (bulk->remote_data) { -+ status = queue_message(service->state, NULL, -+ msgid, &element, 1, 4, 0); -+ if (status != VCHIQ_SUCCESS) -+ break; -+ } -+ queue->remote_notify++; -+ } -+ } else { -+ queue->remote_notify = queue->process; -+ } -+ -+ if (status == VCHIQ_SUCCESS) { -+ while (queue->remove != queue->remote_notify) { -+ VCHIQ_BULK_T *bulk = -+ &queue->bulks[BULK_INDEX(queue->remove)]; -+ -+ /* Only generate callbacks for non-dummy bulk -+ ** requests, and non-terminated services */ -+ if (bulk->data && service->instance) { -+ if (bulk->actual != VCHIQ_BULK_ACTUAL_ABORTED) { -+ if (bulk->dir == VCHIQ_BULK_TRANSMIT) { -+ VCHIQ_SERVICE_STATS_INC(service, -+ bulk_tx_count); -+ VCHIQ_SERVICE_STATS_ADD(service, -+ bulk_tx_bytes, -+ bulk->actual); -+ } else { -+ VCHIQ_SERVICE_STATS_INC(service, -+ bulk_rx_count); -+ VCHIQ_SERVICE_STATS_ADD(service, -+ bulk_rx_bytes, -+ bulk->actual); -+ } -+ } else { -+ VCHIQ_SERVICE_STATS_INC(service, -+ bulk_aborted_count); -+ } -+ if (bulk->mode == VCHIQ_BULK_MODE_BLOCKING) { -+ struct bulk_waiter *waiter; -+ spin_lock(&bulk_waiter_spinlock); -+ waiter = bulk->userdata; -+ if (waiter) { -+ waiter->actual = bulk->actual; -+ up(&waiter->event); -+ } -+ spin_unlock(&bulk_waiter_spinlock); -+ } else if (bulk->mode == -+ VCHIQ_BULK_MODE_CALLBACK) { -+ VCHIQ_REASON_T reason = (bulk->dir == -+ VCHIQ_BULK_TRANSMIT) ? -+ ((bulk->actual == -+ VCHIQ_BULK_ACTUAL_ABORTED) ? -+ VCHIQ_BULK_TRANSMIT_ABORTED : -+ VCHIQ_BULK_TRANSMIT_DONE) : -+ ((bulk->actual == -+ VCHIQ_BULK_ACTUAL_ABORTED) ? -+ VCHIQ_BULK_RECEIVE_ABORTED : -+ VCHIQ_BULK_RECEIVE_DONE); -+ status = make_service_callback(service, -+ reason, NULL, bulk->userdata); -+ if (status == VCHIQ_RETRY) -+ break; -+ } -+ } -+ -+ queue->remove++; -+ up(&service->bulk_remove_event); -+ } -+ if (!retry_poll) -+ status = VCHIQ_SUCCESS; -+ } -+ -+ if (status == VCHIQ_RETRY) -+ request_poll(service->state, service, -+ (queue == &service->bulk_tx) ? -+ VCHIQ_POLL_TXNOTIFY : VCHIQ_POLL_RXNOTIFY); -+ -+ return status; -+} -+ -+/* Called by the slot handler thread */ -+static void -+poll_services(VCHIQ_STATE_T *state) -+{ -+ int group, i; -+ -+ for (group = 0; group < BITSET_SIZE(state->unused_service); group++) { -+ uint32_t flags; -+ flags = atomic_xchg(&state->poll_services[group], 0); -+ for (i = 0; flags; i++) { -+ if (flags & (1 << i)) { -+ VCHIQ_SERVICE_T *service = -+ find_service_by_port(state, -+ (group<<5) + i); -+ uint32_t service_flags; -+ flags &= ~(1 << i); -+ if (!service) -+ continue; -+ service_flags = -+ atomic_xchg(&service->poll_flags, 0); -+ if (service_flags & -+ (1 << VCHIQ_POLL_REMOVE)) { -+ vchiq_log_info(vchiq_core_log_level, -+ "%d: ps - remove %d<->%d", -+ state->id, service->localport, -+ service->remoteport); -+ -+ /* Make it look like a client, because -+ it must be removed and not left in -+ the LISTENING state. */ -+ service->public_fourcc = -+ VCHIQ_FOURCC_INVALID; -+ -+ if (vchiq_close_service_internal( -+ service, 0/*!close_recvd*/) != -+ VCHIQ_SUCCESS) -+ request_poll(state, service, -+ VCHIQ_POLL_REMOVE); -+ } else if (service_flags & -+ (1 << VCHIQ_POLL_TERMINATE)) { -+ vchiq_log_info(vchiq_core_log_level, -+ "%d: ps - terminate %d<->%d", -+ state->id, service->localport, -+ service->remoteport); -+ if (vchiq_close_service_internal( -+ service, 0/*!close_recvd*/) != -+ VCHIQ_SUCCESS) -+ request_poll(state, service, -+ VCHIQ_POLL_TERMINATE); -+ } -+ if (service_flags & (1 << VCHIQ_POLL_TXNOTIFY)) -+ notify_bulks(service, -+ &service->bulk_tx, -+ 1/*retry_poll*/); -+ if (service_flags & (1 << VCHIQ_POLL_RXNOTIFY)) -+ notify_bulks(service, -+ &service->bulk_rx, -+ 1/*retry_poll*/); -+ unlock_service(service); -+ } -+ } -+ } -+} -+ -+/* Called by the slot handler or application threads, holding the bulk mutex. */ -+static int -+resolve_bulks(VCHIQ_SERVICE_T *service, VCHIQ_BULK_QUEUE_T *queue) -+{ -+ VCHIQ_STATE_T *state = service->state; -+ int resolved = 0; -+ int rc; -+ -+ while ((queue->process != queue->local_insert) && -+ (queue->process != queue->remote_insert)) { -+ VCHIQ_BULK_T *bulk = &queue->bulks[BULK_INDEX(queue->process)]; -+ -+ vchiq_log_trace(vchiq_core_log_level, -+ "%d: rb:%d %cx - li=%x ri=%x p=%x", -+ state->id, service->localport, -+ (queue == &service->bulk_tx) ? 't' : 'r', -+ queue->local_insert, queue->remote_insert, -+ queue->process); -+ -+ WARN_ON(!((int)(queue->local_insert - queue->process) > 0)); -+ WARN_ON(!((int)(queue->remote_insert - queue->process) > 0)); -+ -+ rc = mutex_lock_interruptible(&state->bulk_transfer_mutex); -+ if (rc != 0) -+ break; -+ -+ vchiq_transfer_bulk(bulk); -+ mutex_unlock(&state->bulk_transfer_mutex); -+ -+ if (SRVTRACE_ENABLED(service, VCHIQ_LOG_INFO)) { -+ const char *header = (queue == &service->bulk_tx) ? -+ "Send Bulk to" : "Recv Bulk from"; -+ if (bulk->actual != VCHIQ_BULK_ACTUAL_ABORTED) -+ vchiq_log_info(SRVTRACE_LEVEL(service), -+ "%s %c%c%c%c d:%d len:%d %x<->%x", -+ header, -+ VCHIQ_FOURCC_AS_4CHARS( -+ service->base.fourcc), -+ service->remoteport, -+ bulk->size, -+ (unsigned int)bulk->data, -+ (unsigned int)bulk->remote_data); -+ else -+ vchiq_log_info(SRVTRACE_LEVEL(service), -+ "%s %c%c%c%c d:%d ABORTED - tx len:%d," -+ " rx len:%d %x<->%x", -+ header, -+ VCHIQ_FOURCC_AS_4CHARS( -+ service->base.fourcc), -+ service->remoteport, -+ bulk->size, -+ bulk->remote_size, -+ (unsigned int)bulk->data, -+ (unsigned int)bulk->remote_data); -+ } -+ -+ vchiq_complete_bulk(bulk); -+ queue->process++; -+ resolved++; -+ } -+ return resolved; -+} -+ -+/* Called with the bulk_mutex held */ -+static void -+abort_outstanding_bulks(VCHIQ_SERVICE_T *service, VCHIQ_BULK_QUEUE_T *queue) -+{ -+ int is_tx = (queue == &service->bulk_tx); -+ vchiq_log_trace(vchiq_core_log_level, -+ "%d: aob:%d %cx - li=%x ri=%x p=%x", -+ service->state->id, service->localport, is_tx ? 't' : 'r', -+ queue->local_insert, queue->remote_insert, queue->process); -+ -+ WARN_ON(!((int)(queue->local_insert - queue->process) >= 0)); -+ WARN_ON(!((int)(queue->remote_insert - queue->process) >= 0)); -+ -+ while ((queue->process != queue->local_insert) || -+ (queue->process != queue->remote_insert)) { -+ VCHIQ_BULK_T *bulk = &queue->bulks[BULK_INDEX(queue->process)]; -+ -+ if (queue->process == queue->remote_insert) { -+ /* fabricate a matching dummy bulk */ -+ bulk->remote_data = NULL; -+ bulk->remote_size = 0; -+ queue->remote_insert++; -+ } -+ -+ if (queue->process != queue->local_insert) { -+ vchiq_complete_bulk(bulk); -+ -+ vchiq_log_info(SRVTRACE_LEVEL(service), -+ "%s %c%c%c%c d:%d ABORTED - tx len:%d, " -+ "rx len:%d", -+ is_tx ? "Send Bulk to" : "Recv Bulk from", -+ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), -+ service->remoteport, -+ bulk->size, -+ bulk->remote_size); -+ } else { -+ /* fabricate a matching dummy bulk */ -+ bulk->data = NULL; -+ bulk->size = 0; -+ bulk->actual = VCHIQ_BULK_ACTUAL_ABORTED; -+ bulk->dir = is_tx ? VCHIQ_BULK_TRANSMIT : -+ VCHIQ_BULK_RECEIVE; -+ queue->local_insert++; -+ } -+ -+ queue->process++; -+ } -+} -+ -+/* Called from the slot handler thread */ -+static void -+pause_bulks(VCHIQ_STATE_T *state) -+{ -+ if (unlikely(atomic_inc_return(&pause_bulks_count) != 1)) { -+ WARN_ON_ONCE(1); -+ atomic_set(&pause_bulks_count, 1); -+ return; -+ } -+ -+ /* Block bulk transfers from all services */ -+ mutex_lock(&state->bulk_transfer_mutex); -+} -+ -+/* Called from the slot handler thread */ -+static void -+resume_bulks(VCHIQ_STATE_T *state) -+{ -+ int i; -+ if (unlikely(atomic_dec_return(&pause_bulks_count) != 0)) { -+ WARN_ON_ONCE(1); -+ atomic_set(&pause_bulks_count, 0); -+ return; -+ } -+ -+ /* Allow bulk transfers from all services */ -+ mutex_unlock(&state->bulk_transfer_mutex); -+ -+ if (state->deferred_bulks == 0) -+ return; -+ -+ /* Deal with any bulks which had to be deferred due to being in -+ * paused state. Don't try to match up to number of deferred bulks -+ * in case we've had something come and close the service in the -+ * interim - just process all bulk queues for all services */ -+ vchiq_log_info(vchiq_core_log_level, "%s: processing %d deferred bulks", -+ __func__, state->deferred_bulks); -+ -+ for (i = 0; i < state->unused_service; i++) { -+ VCHIQ_SERVICE_T *service = state->services[i]; -+ int resolved_rx = 0; -+ int resolved_tx = 0; -+ if (!service || (service->srvstate != VCHIQ_SRVSTATE_OPEN)) -+ continue; -+ -+ mutex_lock(&service->bulk_mutex); -+ resolved_rx = resolve_bulks(service, &service->bulk_rx); -+ resolved_tx = resolve_bulks(service, &service->bulk_tx); -+ mutex_unlock(&service->bulk_mutex); -+ if (resolved_rx) -+ notify_bulks(service, &service->bulk_rx, 1); -+ if (resolved_tx) -+ notify_bulks(service, &service->bulk_tx, 1); -+ } -+ state->deferred_bulks = 0; -+} -+ -+static int -+parse_open(VCHIQ_STATE_T *state, VCHIQ_HEADER_T *header) -+{ -+ VCHIQ_SERVICE_T *service = NULL; -+ int msgid, size; -+ int type; -+ unsigned int localport, remoteport; -+ -+ msgid = header->msgid; -+ size = header->size; -+ type = VCHIQ_MSG_TYPE(msgid); -+ localport = VCHIQ_MSG_DSTPORT(msgid); -+ remoteport = VCHIQ_MSG_SRCPORT(msgid); -+ if (size >= sizeof(struct vchiq_open_payload)) { -+ const struct vchiq_open_payload *payload = -+ (struct vchiq_open_payload *)header->data; -+ unsigned int fourcc; -+ -+ fourcc = payload->fourcc; -+ vchiq_log_info(vchiq_core_log_level, -+ "%d: prs OPEN@%x (%d->'%c%c%c%c')", -+ state->id, (unsigned int)header, -+ localport, -+ VCHIQ_FOURCC_AS_4CHARS(fourcc)); -+ -+ service = get_listening_service(state, fourcc); -+ -+ if (service) { -+ /* A matching service exists */ -+ short version = payload->version; -+ short version_min = payload->version_min; -+ if ((service->version < version_min) || -+ (version < service->version_min)) { -+ /* Version mismatch */ -+ vchiq_loud_error_header(); -+ vchiq_loud_error("%d: service %d (%c%c%c%c) " -+ "version mismatch - local (%d, min %d)" -+ " vs. remote (%d, min %d)", -+ state->id, service->localport, -+ VCHIQ_FOURCC_AS_4CHARS(fourcc), -+ service->version, service->version_min, -+ version, version_min); -+ vchiq_loud_error_footer(); -+ unlock_service(service); -+ service = NULL; -+ goto fail_open; -+ } -+ service->peer_version = version; -+ -+ if (service->srvstate == VCHIQ_SRVSTATE_LISTENING) { -+ struct vchiq_openack_payload ack_payload = { -+ service->version -+ }; -+ VCHIQ_ELEMENT_T body = { -+ &ack_payload, -+ sizeof(ack_payload) -+ }; -+ -+ if (state->version_common < -+ VCHIQ_VERSION_SYNCHRONOUS_MODE) -+ service->sync = 0; -+ -+ /* Acknowledge the OPEN */ -+ if (service->sync && -+ (state->version_common >= -+ VCHIQ_VERSION_SYNCHRONOUS_MODE)) { -+ if (queue_message_sync(state, NULL, -+ VCHIQ_MAKE_MSG( -+ VCHIQ_MSG_OPENACK, -+ service->localport, -+ remoteport), -+ &body, 1, sizeof(ack_payload), -+ 0) == VCHIQ_RETRY) -+ goto bail_not_ready; -+ } else { -+ if (queue_message(state, NULL, -+ VCHIQ_MAKE_MSG( -+ VCHIQ_MSG_OPENACK, -+ service->localport, -+ remoteport), -+ &body, 1, sizeof(ack_payload), -+ 0) == VCHIQ_RETRY) -+ goto bail_not_ready; -+ } -+ -+ /* The service is now open */ -+ vchiq_set_service_state(service, -+ service->sync ? VCHIQ_SRVSTATE_OPENSYNC -+ : VCHIQ_SRVSTATE_OPEN); -+ } -+ -+ service->remoteport = remoteport; -+ service->client_id = ((int *)header->data)[1]; -+ if (make_service_callback(service, VCHIQ_SERVICE_OPENED, -+ NULL, NULL) == VCHIQ_RETRY) { -+ /* Bail out if not ready */ -+ service->remoteport = VCHIQ_PORT_FREE; -+ goto bail_not_ready; -+ } -+ -+ /* Success - the message has been dealt with */ -+ unlock_service(service); -+ return 1; -+ } -+ } -+ -+fail_open: -+ /* No available service, or an invalid request - send a CLOSE */ -+ if (queue_message(state, NULL, -+ VCHIQ_MAKE_MSG(VCHIQ_MSG_CLOSE, 0, VCHIQ_MSG_SRCPORT(msgid)), -+ NULL, 0, 0, 0) == VCHIQ_RETRY) -+ goto bail_not_ready; -+ -+ return 1; -+ -+bail_not_ready: -+ if (service) -+ unlock_service(service); -+ -+ return 0; -+} -+ -+/* Called by the slot handler thread */ -+static void -+parse_rx_slots(VCHIQ_STATE_T *state) -+{ -+ VCHIQ_SHARED_STATE_T *remote = state->remote; -+ VCHIQ_SERVICE_T *service = NULL; -+ int tx_pos; -+ DEBUG_INITIALISE(state->local) -+ -+ tx_pos = remote->tx_pos; -+ -+ while (state->rx_pos != tx_pos) { -+ VCHIQ_HEADER_T *header; -+ int msgid, size; -+ int type; -+ unsigned int localport, remoteport; -+ -+ DEBUG_TRACE(PARSE_LINE); -+ if (!state->rx_data) { -+ int rx_index; -+ WARN_ON(!((state->rx_pos & VCHIQ_SLOT_MASK) == 0)); -+ rx_index = remote->slot_queue[ -+ SLOT_QUEUE_INDEX_FROM_POS(state->rx_pos) & -+ VCHIQ_SLOT_QUEUE_MASK]; -+ state->rx_data = (char *)SLOT_DATA_FROM_INDEX(state, -+ rx_index); -+ state->rx_info = SLOT_INFO_FROM_INDEX(state, rx_index); -+ -+ /* Initialise use_count to one, and increment -+ ** release_count at the end of the slot to avoid -+ ** releasing the slot prematurely. */ -+ state->rx_info->use_count = 1; -+ state->rx_info->release_count = 0; -+ } -+ -+ header = (VCHIQ_HEADER_T *)(state->rx_data + -+ (state->rx_pos & VCHIQ_SLOT_MASK)); -+ DEBUG_VALUE(PARSE_HEADER, (int)header); -+ msgid = header->msgid; -+ DEBUG_VALUE(PARSE_MSGID, msgid); -+ size = header->size; -+ type = VCHIQ_MSG_TYPE(msgid); -+ localport = VCHIQ_MSG_DSTPORT(msgid); -+ remoteport = VCHIQ_MSG_SRCPORT(msgid); -+ -+ if (type != VCHIQ_MSG_DATA) -+ VCHIQ_STATS_INC(state, ctrl_rx_count); -+ -+ switch (type) { -+ case VCHIQ_MSG_OPENACK: -+ case VCHIQ_MSG_CLOSE: -+ case VCHIQ_MSG_DATA: -+ case VCHIQ_MSG_BULK_RX: -+ case VCHIQ_MSG_BULK_TX: -+ case VCHIQ_MSG_BULK_RX_DONE: -+ case VCHIQ_MSG_BULK_TX_DONE: -+ service = find_service_by_port(state, localport); -+ if ((!service || -+ ((service->remoteport != remoteport) && -+ (service->remoteport != VCHIQ_PORT_FREE))) && -+ (localport == 0) && -+ (type == VCHIQ_MSG_CLOSE)) { -+ /* This could be a CLOSE from a client which -+ hadn't yet received the OPENACK - look for -+ the connected service */ -+ if (service) -+ unlock_service(service); -+ service = get_connected_service(state, -+ remoteport); -+ if (service) -+ vchiq_log_warning(vchiq_core_log_level, -+ "%d: prs %s@%x (%d->%d) - " -+ "found connected service %d", -+ state->id, msg_type_str(type), -+ (unsigned int)header, -+ remoteport, localport, -+ service->localport); -+ } -+ -+ if (!service) { -+ vchiq_log_error(vchiq_core_log_level, -+ "%d: prs %s@%x (%d->%d) - " -+ "invalid/closed service %d", -+ state->id, msg_type_str(type), -+ (unsigned int)header, -+ remoteport, localport, localport); -+ goto skip_message; -+ } -+ break; -+ default: -+ break; -+ } -+ -+ if (SRVTRACE_ENABLED(service, VCHIQ_LOG_INFO)) { -+ int svc_fourcc; -+ -+ svc_fourcc = service -+ ? service->base.fourcc -+ : VCHIQ_MAKE_FOURCC('?', '?', '?', '?'); -+ vchiq_log_info(SRVTRACE_LEVEL(service), -+ "Rcvd Msg %s(%u) from %c%c%c%c s:%d d:%d " -+ "len:%d", -+ msg_type_str(type), type, -+ VCHIQ_FOURCC_AS_4CHARS(svc_fourcc), -+ remoteport, localport, size); -+ if (size > 0) -+ vchiq_log_dump_mem("Rcvd", 0, header->data, -+ min(64, size)); -+ } -+ -+ if (((unsigned int)header & VCHIQ_SLOT_MASK) + calc_stride(size) -+ > VCHIQ_SLOT_SIZE) { -+ vchiq_log_error(vchiq_core_log_level, -+ "header %x (msgid %x) - size %x too big for " -+ "slot", -+ (unsigned int)header, (unsigned int)msgid, -+ (unsigned int)size); -+ WARN(1, "oversized for slot\n"); -+ } -+ -+ switch (type) { -+ case VCHIQ_MSG_OPEN: -+ WARN_ON(!(VCHIQ_MSG_DSTPORT(msgid) == 0)); -+ if (!parse_open(state, header)) -+ goto bail_not_ready; -+ break; -+ case VCHIQ_MSG_OPENACK: -+ if (size >= sizeof(struct vchiq_openack_payload)) { -+ const struct vchiq_openack_payload *payload = -+ (struct vchiq_openack_payload *) -+ header->data; -+ service->peer_version = payload->version; -+ } -+ vchiq_log_info(vchiq_core_log_level, -+ "%d: prs OPENACK@%x,%x (%d->%d) v:%d", -+ state->id, (unsigned int)header, size, -+ remoteport, localport, service->peer_version); -+ if (service->srvstate == -+ VCHIQ_SRVSTATE_OPENING) { -+ service->remoteport = remoteport; -+ vchiq_set_service_state(service, -+ VCHIQ_SRVSTATE_OPEN); -+ up(&service->remove_event); -+ } else -+ vchiq_log_error(vchiq_core_log_level, -+ "OPENACK received in state %s", -+ srvstate_names[service->srvstate]); -+ break; -+ case VCHIQ_MSG_CLOSE: -+ WARN_ON(size != 0); /* There should be no data */ -+ -+ vchiq_log_info(vchiq_core_log_level, -+ "%d: prs CLOSE@%x (%d->%d)", -+ state->id, (unsigned int)header, -+ remoteport, localport); -+ -+ mark_service_closing_internal(service, 1); -+ -+ if (vchiq_close_service_internal(service, -+ 1/*close_recvd*/) == VCHIQ_RETRY) -+ goto bail_not_ready; -+ -+ vchiq_log_info(vchiq_core_log_level, -+ "Close Service %c%c%c%c s:%u d:%d", -+ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), -+ service->localport, -+ service->remoteport); -+ break; -+ case VCHIQ_MSG_DATA: -+ vchiq_log_info(vchiq_core_log_level, -+ "%d: prs DATA@%x,%x (%d->%d)", -+ state->id, (unsigned int)header, size, -+ remoteport, localport); -+ -+ if ((service->remoteport == remoteport) -+ && (service->srvstate == -+ VCHIQ_SRVSTATE_OPEN)) { -+ header->msgid = msgid | VCHIQ_MSGID_CLAIMED; -+ claim_slot(state->rx_info); -+ DEBUG_TRACE(PARSE_LINE); -+ if (make_service_callback(service, -+ VCHIQ_MESSAGE_AVAILABLE, header, -+ NULL) == VCHIQ_RETRY) { -+ DEBUG_TRACE(PARSE_LINE); -+ goto bail_not_ready; -+ } -+ VCHIQ_SERVICE_STATS_INC(service, ctrl_rx_count); -+ VCHIQ_SERVICE_STATS_ADD(service, ctrl_rx_bytes, -+ size); -+ } else { -+ VCHIQ_STATS_INC(state, error_count); -+ } -+ break; -+ case VCHIQ_MSG_CONNECT: -+ vchiq_log_info(vchiq_core_log_level, -+ "%d: prs CONNECT@%x", -+ state->id, (unsigned int)header); -+ state->version_common = ((VCHIQ_SLOT_ZERO_T *) -+ state->slot_data)->version; -+ up(&state->connect); -+ break; -+ case VCHIQ_MSG_BULK_RX: -+ case VCHIQ_MSG_BULK_TX: { -+ VCHIQ_BULK_QUEUE_T *queue; -+ WARN_ON(!state->is_master); -+ queue = (type == VCHIQ_MSG_BULK_RX) ? -+ &service->bulk_tx : &service->bulk_rx; -+ if ((service->remoteport == remoteport) -+ && (service->srvstate == -+ VCHIQ_SRVSTATE_OPEN)) { -+ VCHIQ_BULK_T *bulk; -+ int resolved = 0; -+ -+ DEBUG_TRACE(PARSE_LINE); -+ if (mutex_lock_interruptible( -+ &service->bulk_mutex) != 0) { -+ DEBUG_TRACE(PARSE_LINE); -+ goto bail_not_ready; -+ } -+ -+ WARN_ON(!(queue->remote_insert < queue->remove + -+ VCHIQ_NUM_SERVICE_BULKS)); -+ bulk = &queue->bulks[ -+ BULK_INDEX(queue->remote_insert)]; -+ bulk->remote_data = -+ (void *)((int *)header->data)[0]; -+ bulk->remote_size = ((int *)header->data)[1]; -+ wmb(); -+ -+ vchiq_log_info(vchiq_core_log_level, -+ "%d: prs %s@%x (%d->%d) %x@%x", -+ state->id, msg_type_str(type), -+ (unsigned int)header, -+ remoteport, localport, -+ bulk->remote_size, -+ (unsigned int)bulk->remote_data); -+ -+ queue->remote_insert++; -+ -+ if (atomic_read(&pause_bulks_count)) { -+ state->deferred_bulks++; -+ vchiq_log_info(vchiq_core_log_level, -+ "%s: deferring bulk (%d)", -+ __func__, -+ state->deferred_bulks); -+ if (state->conn_state != -+ VCHIQ_CONNSTATE_PAUSE_SENT) -+ vchiq_log_error( -+ vchiq_core_log_level, -+ "%s: bulks paused in " -+ "unexpected state %s", -+ __func__, -+ conn_state_names[ -+ state->conn_state]); -+ } else if (state->conn_state == -+ VCHIQ_CONNSTATE_CONNECTED) { -+ DEBUG_TRACE(PARSE_LINE); -+ resolved = resolve_bulks(service, -+ queue); -+ } -+ -+ mutex_unlock(&service->bulk_mutex); -+ if (resolved) -+ notify_bulks(service, queue, -+ 1/*retry_poll*/); -+ } -+ } break; -+ case VCHIQ_MSG_BULK_RX_DONE: -+ case VCHIQ_MSG_BULK_TX_DONE: -+ WARN_ON(state->is_master); -+ if ((service->remoteport == remoteport) -+ && (service->srvstate != -+ VCHIQ_SRVSTATE_FREE)) { -+ VCHIQ_BULK_QUEUE_T *queue; -+ VCHIQ_BULK_T *bulk; -+ -+ queue = (type == VCHIQ_MSG_BULK_RX_DONE) ? -+ &service->bulk_rx : &service->bulk_tx; -+ -+ DEBUG_TRACE(PARSE_LINE); -+ if (mutex_lock_interruptible( -+ &service->bulk_mutex) != 0) { -+ DEBUG_TRACE(PARSE_LINE); -+ goto bail_not_ready; -+ } -+ if ((int)(queue->remote_insert - -+ queue->local_insert) >= 0) { -+ vchiq_log_error(vchiq_core_log_level, -+ "%d: prs %s@%x (%d->%d) " -+ "unexpected (ri=%d,li=%d)", -+ state->id, msg_type_str(type), -+ (unsigned int)header, -+ remoteport, localport, -+ queue->remote_insert, -+ queue->local_insert); -+ mutex_unlock(&service->bulk_mutex); -+ break; -+ } -+ -+ BUG_ON(queue->process == queue->local_insert); -+ BUG_ON(queue->process != queue->remote_insert); -+ -+ bulk = &queue->bulks[ -+ BULK_INDEX(queue->remote_insert)]; -+ bulk->actual = *(int *)header->data; -+ queue->remote_insert++; -+ -+ vchiq_log_info(vchiq_core_log_level, -+ "%d: prs %s@%x (%d->%d) %x@%x", -+ state->id, msg_type_str(type), -+ (unsigned int)header, -+ remoteport, localport, -+ bulk->actual, (unsigned int)bulk->data); -+ -+ vchiq_log_trace(vchiq_core_log_level, -+ "%d: prs:%d %cx li=%x ri=%x p=%x", -+ state->id, localport, -+ (type == VCHIQ_MSG_BULK_RX_DONE) ? -+ 'r' : 't', -+ queue->local_insert, -+ queue->remote_insert, queue->process); -+ -+ DEBUG_TRACE(PARSE_LINE); -+ WARN_ON(queue->process == queue->local_insert); -+ vchiq_complete_bulk(bulk); -+ queue->process++; -+ mutex_unlock(&service->bulk_mutex); -+ DEBUG_TRACE(PARSE_LINE); -+ notify_bulks(service, queue, 1/*retry_poll*/); -+ DEBUG_TRACE(PARSE_LINE); -+ } -+ break; -+ case VCHIQ_MSG_PADDING: -+ vchiq_log_trace(vchiq_core_log_level, -+ "%d: prs PADDING@%x,%x", -+ state->id, (unsigned int)header, size); -+ break; -+ case VCHIQ_MSG_PAUSE: -+ /* If initiated, signal the application thread */ -+ vchiq_log_trace(vchiq_core_log_level, -+ "%d: prs PAUSE@%x,%x", -+ state->id, (unsigned int)header, size); -+ if (state->conn_state == VCHIQ_CONNSTATE_PAUSED) { -+ vchiq_log_error(vchiq_core_log_level, -+ "%d: PAUSE received in state PAUSED", -+ state->id); -+ break; -+ } -+ if (state->conn_state != VCHIQ_CONNSTATE_PAUSE_SENT) { -+ /* Send a PAUSE in response */ -+ if (queue_message(state, NULL, -+ VCHIQ_MAKE_MSG(VCHIQ_MSG_PAUSE, 0, 0), -+ NULL, 0, 0, QMFLAGS_NO_MUTEX_UNLOCK) -+ == VCHIQ_RETRY) -+ goto bail_not_ready; -+ if (state->is_master) -+ pause_bulks(state); -+ } -+ /* At this point slot_mutex is held */ -+ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_PAUSED); -+ vchiq_platform_paused(state); -+ break; -+ case VCHIQ_MSG_RESUME: -+ vchiq_log_trace(vchiq_core_log_level, -+ "%d: prs RESUME@%x,%x", -+ state->id, (unsigned int)header, size); -+ /* Release the slot mutex */ -+ mutex_unlock(&state->slot_mutex); -+ if (state->is_master) -+ resume_bulks(state); -+ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTED); -+ vchiq_platform_resumed(state); -+ break; -+ -+ case VCHIQ_MSG_REMOTE_USE: -+ vchiq_on_remote_use(state); -+ break; -+ case VCHIQ_MSG_REMOTE_RELEASE: -+ vchiq_on_remote_release(state); -+ break; -+ case VCHIQ_MSG_REMOTE_USE_ACTIVE: -+ vchiq_on_remote_use_active(state); -+ break; -+ -+ default: -+ vchiq_log_error(vchiq_core_log_level, -+ "%d: prs invalid msgid %x@%x,%x", -+ state->id, msgid, (unsigned int)header, size); -+ WARN(1, "invalid message\n"); -+ break; -+ } -+ -+skip_message: -+ if (service) { -+ unlock_service(service); -+ service = NULL; -+ } -+ -+ state->rx_pos += calc_stride(size); -+ -+ DEBUG_TRACE(PARSE_LINE); -+ /* Perform some housekeeping when the end of the slot is -+ ** reached. */ -+ if ((state->rx_pos & VCHIQ_SLOT_MASK) == 0) { -+ /* Remove the extra reference count. */ -+ release_slot(state, state->rx_info, NULL, NULL); -+ state->rx_data = NULL; -+ } -+ } -+ -+bail_not_ready: -+ if (service) -+ unlock_service(service); -+} -+ -+/* Called by the slot handler thread */ -+static int -+slot_handler_func(void *v) -+{ -+ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v; -+ VCHIQ_SHARED_STATE_T *local = state->local; -+ DEBUG_INITIALISE(local) -+ -+ while (1) { -+ DEBUG_COUNT(SLOT_HANDLER_COUNT); -+ DEBUG_TRACE(SLOT_HANDLER_LINE); -+ remote_event_wait(&local->trigger); -+ -+ rmb(); -+ -+ DEBUG_TRACE(SLOT_HANDLER_LINE); -+ if (state->poll_needed) { -+ /* Check if we need to suspend - may change our -+ * conn_state */ -+ vchiq_platform_check_suspend(state); -+ -+ state->poll_needed = 0; -+ -+ /* Handle service polling and other rare conditions here -+ ** out of the mainline code */ -+ switch (state->conn_state) { -+ case VCHIQ_CONNSTATE_CONNECTED: -+ /* Poll the services as requested */ -+ poll_services(state); -+ break; -+ -+ case VCHIQ_CONNSTATE_PAUSING: -+ if (state->is_master) -+ pause_bulks(state); -+ if (queue_message(state, NULL, -+ VCHIQ_MAKE_MSG(VCHIQ_MSG_PAUSE, 0, 0), -+ NULL, 0, 0, -+ QMFLAGS_NO_MUTEX_UNLOCK) -+ != VCHIQ_RETRY) { -+ vchiq_set_conn_state(state, -+ VCHIQ_CONNSTATE_PAUSE_SENT); -+ } else { -+ if (state->is_master) -+ resume_bulks(state); -+ /* Retry later */ -+ state->poll_needed = 1; -+ } -+ break; -+ -+ case VCHIQ_CONNSTATE_PAUSED: -+ vchiq_platform_resume(state); -+ break; -+ -+ case VCHIQ_CONNSTATE_RESUMING: -+ if (queue_message(state, NULL, -+ VCHIQ_MAKE_MSG(VCHIQ_MSG_RESUME, 0, 0), -+ NULL, 0, 0, QMFLAGS_NO_MUTEX_LOCK) -+ != VCHIQ_RETRY) { -+ if (state->is_master) -+ resume_bulks(state); -+ vchiq_set_conn_state(state, -+ VCHIQ_CONNSTATE_CONNECTED); -+ vchiq_platform_resumed(state); -+ } else { -+ /* This should really be impossible, -+ ** since the PAUSE should have flushed -+ ** through outstanding messages. */ -+ vchiq_log_error(vchiq_core_log_level, -+ "Failed to send RESUME " -+ "message"); -+ BUG(); -+ } -+ break; -+ -+ case VCHIQ_CONNSTATE_PAUSE_TIMEOUT: -+ case VCHIQ_CONNSTATE_RESUME_TIMEOUT: -+ vchiq_platform_handle_timeout(state); -+ break; -+ default: -+ break; -+ } -+ -+ -+ } -+ -+ DEBUG_TRACE(SLOT_HANDLER_LINE); -+ parse_rx_slots(state); -+ } -+ return 0; -+} -+ -+ -+/* Called by the recycle thread */ -+static int -+recycle_func(void *v) -+{ -+ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v; -+ VCHIQ_SHARED_STATE_T *local = state->local; -+ -+ while (1) { -+ remote_event_wait(&local->recycle); -+ -+ process_free_queue(state); -+ } -+ return 0; -+} -+ -+ -+/* Called by the sync thread */ -+static int -+sync_func(void *v) -+{ -+ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v; -+ VCHIQ_SHARED_STATE_T *local = state->local; -+ VCHIQ_HEADER_T *header = (VCHIQ_HEADER_T *)SLOT_DATA_FROM_INDEX(state, -+ state->remote->slot_sync); -+ -+ while (1) { -+ VCHIQ_SERVICE_T *service; -+ int msgid, size; -+ int type; -+ unsigned int localport, remoteport; -+ -+ remote_event_wait(&local->sync_trigger); -+ -+ rmb(); -+ -+ msgid = header->msgid; -+ size = header->size; -+ type = VCHIQ_MSG_TYPE(msgid); -+ localport = VCHIQ_MSG_DSTPORT(msgid); -+ remoteport = VCHIQ_MSG_SRCPORT(msgid); -+ -+ service = find_service_by_port(state, localport); -+ -+ if (!service) { -+ vchiq_log_error(vchiq_sync_log_level, -+ "%d: sf %s@%x (%d->%d) - " -+ "invalid/closed service %d", -+ state->id, msg_type_str(type), -+ (unsigned int)header, -+ remoteport, localport, localport); -+ release_message_sync(state, header); -+ continue; -+ } -+ -+ if (vchiq_sync_log_level >= VCHIQ_LOG_TRACE) { -+ int svc_fourcc; -+ -+ svc_fourcc = service -+ ? service->base.fourcc -+ : VCHIQ_MAKE_FOURCC('?', '?', '?', '?'); -+ vchiq_log_trace(vchiq_sync_log_level, -+ "Rcvd Msg %s from %c%c%c%c s:%d d:%d len:%d", -+ msg_type_str(type), -+ VCHIQ_FOURCC_AS_4CHARS(svc_fourcc), -+ remoteport, localport, size); -+ if (size > 0) -+ vchiq_log_dump_mem("Rcvd", 0, header->data, -+ min(64, size)); -+ } -+ -+ switch (type) { -+ case VCHIQ_MSG_OPENACK: -+ if (size >= sizeof(struct vchiq_openack_payload)) { -+ const struct vchiq_openack_payload *payload = -+ (struct vchiq_openack_payload *) -+ header->data; -+ service->peer_version = payload->version; -+ } -+ vchiq_log_info(vchiq_sync_log_level, -+ "%d: sf OPENACK@%x,%x (%d->%d) v:%d", -+ state->id, (unsigned int)header, size, -+ remoteport, localport, service->peer_version); -+ if (service->srvstate == VCHIQ_SRVSTATE_OPENING) { -+ service->remoteport = remoteport; -+ vchiq_set_service_state(service, -+ VCHIQ_SRVSTATE_OPENSYNC); -+ service->sync = 1; -+ up(&service->remove_event); -+ } -+ release_message_sync(state, header); -+ break; -+ -+ case VCHIQ_MSG_DATA: -+ vchiq_log_trace(vchiq_sync_log_level, -+ "%d: sf DATA@%x,%x (%d->%d)", -+ state->id, (unsigned int)header, size, -+ remoteport, localport); -+ -+ if ((service->remoteport == remoteport) && -+ (service->srvstate == -+ VCHIQ_SRVSTATE_OPENSYNC)) { -+ if (make_service_callback(service, -+ VCHIQ_MESSAGE_AVAILABLE, header, -+ NULL) == VCHIQ_RETRY) -+ vchiq_log_error(vchiq_sync_log_level, -+ "synchronous callback to " -+ "service %d returns " -+ "VCHIQ_RETRY", -+ localport); -+ } -+ break; -+ -+ default: -+ vchiq_log_error(vchiq_sync_log_level, -+ "%d: sf unexpected msgid %x@%x,%x", -+ state->id, msgid, (unsigned int)header, size); -+ release_message_sync(state, header); -+ break; -+ } -+ -+ unlock_service(service); -+ } -+ -+ return 0; -+} -+ -+ -+static void -+init_bulk_queue(VCHIQ_BULK_QUEUE_T *queue) -+{ -+ queue->local_insert = 0; -+ queue->remote_insert = 0; -+ queue->process = 0; -+ queue->remote_notify = 0; -+ queue->remove = 0; -+} -+ -+ -+inline const char * -+get_conn_state_name(VCHIQ_CONNSTATE_T conn_state) -+{ -+ return conn_state_names[conn_state]; -+} -+ -+ -+VCHIQ_SLOT_ZERO_T * -+vchiq_init_slots(void *mem_base, int mem_size) -+{ -+ int mem_align = (VCHIQ_SLOT_SIZE - (int)mem_base) & VCHIQ_SLOT_MASK; -+ VCHIQ_SLOT_ZERO_T *slot_zero = -+ (VCHIQ_SLOT_ZERO_T *)((char *)mem_base + mem_align); -+ int num_slots = (mem_size - mem_align)/VCHIQ_SLOT_SIZE; -+ int first_data_slot = VCHIQ_SLOT_ZERO_SLOTS; -+ -+ /* Ensure there is enough memory to run an absolutely minimum system */ -+ num_slots -= first_data_slot; -+ -+ if (num_slots < 4) { -+ vchiq_log_error(vchiq_core_log_level, -+ "vchiq_init_slots - insufficient memory %x bytes", -+ mem_size); -+ return NULL; -+ } -+ -+ memset(slot_zero, 0, sizeof(VCHIQ_SLOT_ZERO_T)); -+ -+ slot_zero->magic = VCHIQ_MAGIC; -+ slot_zero->version = VCHIQ_VERSION; -+ slot_zero->version_min = VCHIQ_VERSION_MIN; -+ slot_zero->slot_zero_size = sizeof(VCHIQ_SLOT_ZERO_T); -+ slot_zero->slot_size = VCHIQ_SLOT_SIZE; -+ slot_zero->max_slots = VCHIQ_MAX_SLOTS; -+ slot_zero->max_slots_per_side = VCHIQ_MAX_SLOTS_PER_SIDE; -+ -+ slot_zero->master.slot_sync = first_data_slot; -+ slot_zero->master.slot_first = first_data_slot + 1; -+ slot_zero->master.slot_last = first_data_slot + (num_slots/2) - 1; -+ slot_zero->slave.slot_sync = first_data_slot + (num_slots/2); -+ slot_zero->slave.slot_first = first_data_slot + (num_slots/2) + 1; -+ slot_zero->slave.slot_last = first_data_slot + num_slots - 1; -+ -+ return slot_zero; -+} -+ -+VCHIQ_STATUS_T -+vchiq_init_state(VCHIQ_STATE_T *state, VCHIQ_SLOT_ZERO_T *slot_zero, -+ int is_master) -+{ -+ VCHIQ_SHARED_STATE_T *local; -+ VCHIQ_SHARED_STATE_T *remote; -+ VCHIQ_STATUS_T status; -+ char threadname[10]; -+ static int id; -+ int i; -+ -+ vchiq_log_warning(vchiq_core_log_level, -+ "%s: slot_zero = 0x%08lx, is_master = %d", -+ __func__, (unsigned long)slot_zero, is_master); -+ -+ /* Check the input configuration */ -+ -+ if (slot_zero->magic != VCHIQ_MAGIC) { -+ vchiq_loud_error_header(); -+ vchiq_loud_error("Invalid VCHIQ magic value found."); -+ vchiq_loud_error("slot_zero=%x: magic=%x (expected %x)", -+ (unsigned int)slot_zero, slot_zero->magic, VCHIQ_MAGIC); -+ vchiq_loud_error_footer(); -+ return VCHIQ_ERROR; -+ } -+ -+ if (slot_zero->version < VCHIQ_VERSION_MIN) { -+ vchiq_loud_error_header(); -+ vchiq_loud_error("Incompatible VCHIQ versions found."); -+ vchiq_loud_error("slot_zero=%x: VideoCore version=%d " -+ "(minimum %d)", -+ (unsigned int)slot_zero, slot_zero->version, -+ VCHIQ_VERSION_MIN); -+ vchiq_loud_error("Restart with a newer VideoCore image."); -+ vchiq_loud_error_footer(); -+ return VCHIQ_ERROR; -+ } -+ -+ if (VCHIQ_VERSION < slot_zero->version_min) { -+ vchiq_loud_error_header(); -+ vchiq_loud_error("Incompatible VCHIQ versions found."); -+ vchiq_loud_error("slot_zero=%x: version=%d (VideoCore " -+ "minimum %d)", -+ (unsigned int)slot_zero, VCHIQ_VERSION, -+ slot_zero->version_min); -+ vchiq_loud_error("Restart with a newer kernel."); -+ vchiq_loud_error_footer(); -+ return VCHIQ_ERROR; -+ } -+ -+ if ((slot_zero->slot_zero_size != sizeof(VCHIQ_SLOT_ZERO_T)) || -+ (slot_zero->slot_size != VCHIQ_SLOT_SIZE) || -+ (slot_zero->max_slots != VCHIQ_MAX_SLOTS) || -+ (slot_zero->max_slots_per_side != VCHIQ_MAX_SLOTS_PER_SIDE)) { -+ vchiq_loud_error_header(); -+ if (slot_zero->slot_zero_size != sizeof(VCHIQ_SLOT_ZERO_T)) -+ vchiq_loud_error("slot_zero=%x: slot_zero_size=%x " -+ "(expected %x)", -+ (unsigned int)slot_zero, -+ slot_zero->slot_zero_size, -+ sizeof(VCHIQ_SLOT_ZERO_T)); -+ if (slot_zero->slot_size != VCHIQ_SLOT_SIZE) -+ vchiq_loud_error("slot_zero=%x: slot_size=%d " -+ "(expected %d", -+ (unsigned int)slot_zero, slot_zero->slot_size, -+ VCHIQ_SLOT_SIZE); -+ if (slot_zero->max_slots != VCHIQ_MAX_SLOTS) -+ vchiq_loud_error("slot_zero=%x: max_slots=%d " -+ "(expected %d)", -+ (unsigned int)slot_zero, slot_zero->max_slots, -+ VCHIQ_MAX_SLOTS); -+ if (slot_zero->max_slots_per_side != VCHIQ_MAX_SLOTS_PER_SIDE) -+ vchiq_loud_error("slot_zero=%x: max_slots_per_side=%d " -+ "(expected %d)", -+ (unsigned int)slot_zero, -+ slot_zero->max_slots_per_side, -+ VCHIQ_MAX_SLOTS_PER_SIDE); -+ vchiq_loud_error_footer(); -+ return VCHIQ_ERROR; -+ } -+ -+ if (VCHIQ_VERSION < slot_zero->version) -+ slot_zero->version = VCHIQ_VERSION; -+ -+ if (is_master) { -+ local = &slot_zero->master; -+ remote = &slot_zero->slave; -+ } else { -+ local = &slot_zero->slave; -+ remote = &slot_zero->master; -+ } -+ -+ if (local->initialised) { -+ vchiq_loud_error_header(); -+ if (remote->initialised) -+ vchiq_loud_error("local state has already been " -+ "initialised"); -+ else -+ vchiq_loud_error("master/slave mismatch - two %ss", -+ is_master ? "master" : "slave"); -+ vchiq_loud_error_footer(); -+ return VCHIQ_ERROR; -+ } -+ -+ memset(state, 0, sizeof(VCHIQ_STATE_T)); -+ -+ state->id = id++; -+ state->is_master = is_master; -+ -+ /* -+ initialize shared state pointers -+ */ -+ -+ state->local = local; -+ state->remote = remote; -+ state->slot_data = (VCHIQ_SLOT_T *)slot_zero; -+ -+ /* -+ initialize events and mutexes -+ */ -+ -+ sema_init(&state->connect, 0); -+ mutex_init(&state->mutex); -+ sema_init(&state->trigger_event, 0); -+ sema_init(&state->recycle_event, 0); -+ sema_init(&state->sync_trigger_event, 0); -+ sema_init(&state->sync_release_event, 0); -+ -+ mutex_init(&state->slot_mutex); -+ mutex_init(&state->recycle_mutex); -+ mutex_init(&state->sync_mutex); -+ mutex_init(&state->bulk_transfer_mutex); -+ -+ sema_init(&state->slot_available_event, 0); -+ sema_init(&state->slot_remove_event, 0); -+ sema_init(&state->data_quota_event, 0); -+ -+ state->slot_queue_available = 0; -+ -+ for (i = 0; i < VCHIQ_MAX_SERVICES; i++) { -+ VCHIQ_SERVICE_QUOTA_T *service_quota = -+ &state->service_quotas[i]; -+ sema_init(&service_quota->quota_event, 0); -+ } -+ -+ for (i = local->slot_first; i <= local->slot_last; i++) { -+ local->slot_queue[state->slot_queue_available++] = i; -+ up(&state->slot_available_event); -+ } -+ -+ state->default_slot_quota = state->slot_queue_available/2; -+ state->default_message_quota = -+ min((unsigned short)(state->default_slot_quota * 256), -+ (unsigned short)~0); -+ -+ state->previous_data_index = -1; -+ state->data_use_count = 0; -+ state->data_quota = state->slot_queue_available - 1; -+ -+ local->trigger.event = &state->trigger_event; -+ remote_event_create(&local->trigger); -+ local->tx_pos = 0; -+ -+ local->recycle.event = &state->recycle_event; -+ remote_event_create(&local->recycle); -+ local->slot_queue_recycle = state->slot_queue_available; -+ -+ local->sync_trigger.event = &state->sync_trigger_event; -+ remote_event_create(&local->sync_trigger); -+ -+ local->sync_release.event = &state->sync_release_event; -+ remote_event_create(&local->sync_release); -+ -+ /* At start-of-day, the slot is empty and available */ -+ ((VCHIQ_HEADER_T *)SLOT_DATA_FROM_INDEX(state, local->slot_sync))->msgid -+ = VCHIQ_MSGID_PADDING; -+ remote_event_signal_local(&local->sync_release); -+ -+ local->debug[DEBUG_ENTRIES] = DEBUG_MAX; -+ -+ status = vchiq_platform_init_state(state); -+ -+ /* -+ bring up slot handler thread -+ */ -+ snprintf(threadname, sizeof(threadname), "VCHIQ-%d", state->id); -+ state->slot_handler_thread = kthread_create(&slot_handler_func, -+ (void *)state, -+ threadname); -+ -+ if (state->slot_handler_thread == NULL) { -+ vchiq_loud_error_header(); -+ vchiq_loud_error("couldn't create thread %s", threadname); -+ vchiq_loud_error_footer(); -+ return VCHIQ_ERROR; -+ } -+ set_user_nice(state->slot_handler_thread, -19); -+ wake_up_process(state->slot_handler_thread); -+ -+ snprintf(threadname, sizeof(threadname), "VCHIQr-%d", state->id); -+ state->recycle_thread = kthread_create(&recycle_func, -+ (void *)state, -+ threadname); -+ if (state->recycle_thread == NULL) { -+ vchiq_loud_error_header(); -+ vchiq_loud_error("couldn't create thread %s", threadname); -+ vchiq_loud_error_footer(); -+ return VCHIQ_ERROR; -+ } -+ set_user_nice(state->recycle_thread, -19); -+ wake_up_process(state->recycle_thread); -+ -+ snprintf(threadname, sizeof(threadname), "VCHIQs-%d", state->id); -+ state->sync_thread = kthread_create(&sync_func, -+ (void *)state, -+ threadname); -+ if (state->sync_thread == NULL) { -+ vchiq_loud_error_header(); -+ vchiq_loud_error("couldn't create thread %s", threadname); -+ vchiq_loud_error_footer(); -+ return VCHIQ_ERROR; -+ } -+ set_user_nice(state->sync_thread, -20); -+ wake_up_process(state->sync_thread); -+ -+ BUG_ON(state->id >= VCHIQ_MAX_STATES); -+ vchiq_states[state->id] = state; -+ -+ /* Indicate readiness to the other side */ -+ local->initialised = 1; -+ -+ return status; -+} -+ -+/* Called from application thread when a client or server service is created. */ -+VCHIQ_SERVICE_T * -+vchiq_add_service_internal(VCHIQ_STATE_T *state, -+ const VCHIQ_SERVICE_PARAMS_T *params, int srvstate, -+ VCHIQ_INSTANCE_T instance, VCHIQ_USERDATA_TERM_T userdata_term) -+{ -+ VCHIQ_SERVICE_T *service; -+ -+ service = kmalloc(sizeof(VCHIQ_SERVICE_T), GFP_KERNEL); -+ if (service) { -+ service->base.fourcc = params->fourcc; -+ service->base.callback = params->callback; -+ service->base.userdata = params->userdata; -+ service->handle = VCHIQ_SERVICE_HANDLE_INVALID; -+ service->ref_count = 1; -+ service->srvstate = VCHIQ_SRVSTATE_FREE; -+ service->userdata_term = userdata_term; -+ service->localport = VCHIQ_PORT_FREE; -+ service->remoteport = VCHIQ_PORT_FREE; -+ -+ service->public_fourcc = (srvstate == VCHIQ_SRVSTATE_OPENING) ? -+ VCHIQ_FOURCC_INVALID : params->fourcc; -+ service->client_id = 0; -+ service->auto_close = 1; -+ service->sync = 0; -+ service->closing = 0; -+ service->trace = 0; -+ atomic_set(&service->poll_flags, 0); -+ service->version = params->version; -+ service->version_min = params->version_min; -+ service->state = state; -+ service->instance = instance; -+ service->service_use_count = 0; -+ init_bulk_queue(&service->bulk_tx); -+ init_bulk_queue(&service->bulk_rx); -+ sema_init(&service->remove_event, 0); -+ sema_init(&service->bulk_remove_event, 0); -+ mutex_init(&service->bulk_mutex); -+ memset(&service->stats, 0, sizeof(service->stats)); -+ } else { -+ vchiq_log_error(vchiq_core_log_level, -+ "Out of memory"); -+ } -+ -+ if (service) { -+ VCHIQ_SERVICE_T **pservice = NULL; -+ int i; -+ -+ /* Although it is perfectly possible to use service_spinlock -+ ** to protect the creation of services, it is overkill as it -+ ** disables interrupts while the array is searched. -+ ** The only danger is of another thread trying to create a -+ ** service - service deletion is safe. -+ ** Therefore it is preferable to use state->mutex which, -+ ** although slower to claim, doesn't block interrupts while -+ ** it is held. -+ */ -+ -+ mutex_lock(&state->mutex); -+ -+ /* Prepare to use a previously unused service */ -+ if (state->unused_service < VCHIQ_MAX_SERVICES) -+ pservice = &state->services[state->unused_service]; -+ -+ if (srvstate == VCHIQ_SRVSTATE_OPENING) { -+ for (i = 0; i < state->unused_service; i++) { -+ VCHIQ_SERVICE_T *srv = state->services[i]; -+ if (!srv) { -+ pservice = &state->services[i]; -+ break; -+ } -+ } -+ } else { -+ for (i = (state->unused_service - 1); i >= 0; i--) { -+ VCHIQ_SERVICE_T *srv = state->services[i]; -+ if (!srv) -+ pservice = &state->services[i]; -+ else if ((srv->public_fourcc == params->fourcc) -+ && ((srv->instance != instance) || -+ (srv->base.callback != -+ params->callback))) { -+ /* There is another server using this -+ ** fourcc which doesn't match. */ -+ pservice = NULL; -+ break; -+ } -+ } -+ } -+ -+ if (pservice) { -+ service->localport = (pservice - state->services); -+ if (!handle_seq) -+ handle_seq = VCHIQ_MAX_STATES * -+ VCHIQ_MAX_SERVICES; -+ service->handle = handle_seq | -+ (state->id * VCHIQ_MAX_SERVICES) | -+ service->localport; -+ handle_seq += VCHIQ_MAX_STATES * VCHIQ_MAX_SERVICES; -+ *pservice = service; -+ if (pservice == &state->services[state->unused_service]) -+ state->unused_service++; -+ } -+ -+ mutex_unlock(&state->mutex); -+ -+ if (!pservice) { -+ kfree(service); -+ service = NULL; -+ } -+ } -+ -+ if (service) { -+ VCHIQ_SERVICE_QUOTA_T *service_quota = -+ &state->service_quotas[service->localport]; -+ service_quota->slot_quota = state->default_slot_quota; -+ service_quota->message_quota = state->default_message_quota; -+ if (service_quota->slot_use_count == 0) -+ service_quota->previous_tx_index = -+ SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos) -+ - 1; -+ -+ /* Bring this service online */ -+ vchiq_set_service_state(service, srvstate); -+ -+ vchiq_log_info(vchiq_core_msg_log_level, -+ "%s Service %c%c%c%c SrcPort:%d", -+ (srvstate == VCHIQ_SRVSTATE_OPENING) -+ ? "Open" : "Add", -+ VCHIQ_FOURCC_AS_4CHARS(params->fourcc), -+ service->localport); -+ } -+ -+ /* Don't unlock the service - leave it with a ref_count of 1. */ -+ -+ return service; -+} -+ -+VCHIQ_STATUS_T -+vchiq_open_service_internal(VCHIQ_SERVICE_T *service, int client_id) -+{ -+ struct vchiq_open_payload payload = { -+ service->base.fourcc, -+ client_id, -+ service->version, -+ service->version_min -+ }; -+ VCHIQ_ELEMENT_T body = { &payload, sizeof(payload) }; -+ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; -+ -+ service->client_id = client_id; -+ vchiq_use_service_internal(service); -+ status = queue_message(service->state, NULL, -+ VCHIQ_MAKE_MSG(VCHIQ_MSG_OPEN, service->localport, 0), -+ &body, 1, sizeof(payload), QMFLAGS_IS_BLOCKING); -+ if (status == VCHIQ_SUCCESS) { -+ /* Wait for the ACK/NAK */ -+ if (down_interruptible(&service->remove_event) != 0) { -+ status = VCHIQ_RETRY; -+ vchiq_release_service_internal(service); -+ } else if ((service->srvstate != VCHIQ_SRVSTATE_OPEN) && -+ (service->srvstate != VCHIQ_SRVSTATE_OPENSYNC)) { -+ if (service->srvstate != VCHIQ_SRVSTATE_CLOSEWAIT) -+ vchiq_log_error(vchiq_core_log_level, -+ "%d: osi - srvstate = %s (ref %d)", -+ service->state->id, -+ srvstate_names[service->srvstate], -+ service->ref_count); -+ status = VCHIQ_ERROR; -+ VCHIQ_SERVICE_STATS_INC(service, error_count); -+ vchiq_release_service_internal(service); -+ } -+ } -+ return status; -+} -+ -+static void -+release_service_messages(VCHIQ_SERVICE_T *service) -+{ -+ VCHIQ_STATE_T *state = service->state; -+ int slot_last = state->remote->slot_last; -+ int i; -+ -+ /* Release any claimed messages aimed at this service */ -+ -+ if (service->sync) { -+ VCHIQ_HEADER_T *header = -+ (VCHIQ_HEADER_T *)SLOT_DATA_FROM_INDEX(state, -+ state->remote->slot_sync); -+ if (VCHIQ_MSG_DSTPORT(header->msgid) == service->localport) -+ release_message_sync(state, header); -+ -+ return; -+ } -+ -+ for (i = state->remote->slot_first; i <= slot_last; i++) { -+ VCHIQ_SLOT_INFO_T *slot_info = -+ SLOT_INFO_FROM_INDEX(state, i); -+ if (slot_info->release_count != slot_info->use_count) { -+ char *data = -+ (char *)SLOT_DATA_FROM_INDEX(state, i); -+ unsigned int pos, end; -+ -+ end = VCHIQ_SLOT_SIZE; -+ if (data == state->rx_data) -+ /* This buffer is still being read from - stop -+ ** at the current read position */ -+ end = state->rx_pos & VCHIQ_SLOT_MASK; -+ -+ pos = 0; -+ -+ while (pos < end) { -+ VCHIQ_HEADER_T *header = -+ (VCHIQ_HEADER_T *)(data + pos); -+ int msgid = header->msgid; -+ int port = VCHIQ_MSG_DSTPORT(msgid); -+ if ((port == service->localport) && -+ (msgid & VCHIQ_MSGID_CLAIMED)) { -+ vchiq_log_info(vchiq_core_log_level, -+ " fsi - hdr %x", -+ (unsigned int)header); -+ release_slot(state, slot_info, header, -+ NULL); -+ } -+ pos += calc_stride(header->size); -+ if (pos > VCHIQ_SLOT_SIZE) { -+ vchiq_log_error(vchiq_core_log_level, -+ "fsi - pos %x: header %x, " -+ "msgid %x, header->msgid %x, " -+ "header->size %x", -+ pos, (unsigned int)header, -+ msgid, header->msgid, -+ header->size); -+ WARN(1, "invalid slot position\n"); -+ } -+ } -+ } -+ } -+} -+ -+static int -+do_abort_bulks(VCHIQ_SERVICE_T *service) -+{ -+ VCHIQ_STATUS_T status; -+ -+ /* Abort any outstanding bulk transfers */ -+ if (mutex_lock_interruptible(&service->bulk_mutex) != 0) -+ return 0; -+ abort_outstanding_bulks(service, &service->bulk_tx); -+ abort_outstanding_bulks(service, &service->bulk_rx); -+ mutex_unlock(&service->bulk_mutex); -+ -+ status = notify_bulks(service, &service->bulk_tx, 0/*!retry_poll*/); -+ if (status == VCHIQ_SUCCESS) -+ status = notify_bulks(service, &service->bulk_rx, -+ 0/*!retry_poll*/); -+ return (status == VCHIQ_SUCCESS); -+} -+ -+static VCHIQ_STATUS_T -+close_service_complete(VCHIQ_SERVICE_T *service, int failstate) -+{ -+ VCHIQ_STATUS_T status; -+ int is_server = (service->public_fourcc != VCHIQ_FOURCC_INVALID); -+ int newstate; -+ -+ switch (service->srvstate) { -+ case VCHIQ_SRVSTATE_OPEN: -+ case VCHIQ_SRVSTATE_CLOSESENT: -+ case VCHIQ_SRVSTATE_CLOSERECVD: -+ if (is_server) { -+ if (service->auto_close) { -+ service->client_id = 0; -+ service->remoteport = VCHIQ_PORT_FREE; -+ newstate = VCHIQ_SRVSTATE_LISTENING; -+ } else -+ newstate = VCHIQ_SRVSTATE_CLOSEWAIT; -+ } else -+ newstate = VCHIQ_SRVSTATE_CLOSED; -+ vchiq_set_service_state(service, newstate); -+ break; -+ case VCHIQ_SRVSTATE_LISTENING: -+ break; -+ default: -+ vchiq_log_error(vchiq_core_log_level, -+ "close_service_complete(%x) called in state %s", -+ service->handle, srvstate_names[service->srvstate]); -+ WARN(1, "close_service_complete in unexpected state\n"); -+ return VCHIQ_ERROR; -+ } -+ -+ status = make_service_callback(service, -+ VCHIQ_SERVICE_CLOSED, NULL, NULL); -+ -+ if (status != VCHIQ_RETRY) { -+ int uc = service->service_use_count; -+ int i; -+ /* Complete the close process */ -+ for (i = 0; i < uc; i++) -+ /* cater for cases where close is forced and the -+ ** client may not close all it's handles */ -+ vchiq_release_service_internal(service); -+ -+ service->client_id = 0; -+ service->remoteport = VCHIQ_PORT_FREE; -+ -+ if (service->srvstate == VCHIQ_SRVSTATE_CLOSED) -+ vchiq_free_service_internal(service); -+ else if (service->srvstate != VCHIQ_SRVSTATE_CLOSEWAIT) { -+ if (is_server) -+ service->closing = 0; -+ -+ up(&service->remove_event); -+ } -+ } else -+ vchiq_set_service_state(service, failstate); -+ -+ return status; -+} -+ -+/* Called by the slot handler */ -+VCHIQ_STATUS_T -+vchiq_close_service_internal(VCHIQ_SERVICE_T *service, int close_recvd) -+{ -+ VCHIQ_STATE_T *state = service->state; -+ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; -+ int is_server = (service->public_fourcc != VCHIQ_FOURCC_INVALID); -+ -+ vchiq_log_info(vchiq_core_log_level, "%d: csi:%d,%d (%s)", -+ service->state->id, service->localport, close_recvd, -+ srvstate_names[service->srvstate]); -+ -+ switch (service->srvstate) { -+ case VCHIQ_SRVSTATE_CLOSED: -+ case VCHIQ_SRVSTATE_HIDDEN: -+ case VCHIQ_SRVSTATE_LISTENING: -+ case VCHIQ_SRVSTATE_CLOSEWAIT: -+ if (close_recvd) -+ vchiq_log_error(vchiq_core_log_level, -+ "vchiq_close_service_internal(1) called " -+ "in state %s", -+ srvstate_names[service->srvstate]); -+ else if (is_server) { -+ if (service->srvstate == VCHIQ_SRVSTATE_LISTENING) { -+ status = VCHIQ_ERROR; -+ } else { -+ service->client_id = 0; -+ service->remoteport = VCHIQ_PORT_FREE; -+ if (service->srvstate == -+ VCHIQ_SRVSTATE_CLOSEWAIT) -+ vchiq_set_service_state(service, -+ VCHIQ_SRVSTATE_LISTENING); -+ } -+ up(&service->remove_event); -+ } else -+ vchiq_free_service_internal(service); -+ break; -+ case VCHIQ_SRVSTATE_OPENING: -+ if (close_recvd) { -+ /* The open was rejected - tell the user */ -+ vchiq_set_service_state(service, -+ VCHIQ_SRVSTATE_CLOSEWAIT); -+ up(&service->remove_event); -+ } else { -+ /* Shutdown mid-open - let the other side know */ -+ status = queue_message(state, service, -+ VCHIQ_MAKE_MSG -+ (VCHIQ_MSG_CLOSE, -+ service->localport, -+ VCHIQ_MSG_DSTPORT(service->remoteport)), -+ NULL, 0, 0, 0); -+ } -+ break; -+ -+ case VCHIQ_SRVSTATE_OPENSYNC: -+ mutex_lock(&state->sync_mutex); -+ /* Drop through */ -+ -+ case VCHIQ_SRVSTATE_OPEN: -+ if (state->is_master || close_recvd) { -+ if (!do_abort_bulks(service)) -+ status = VCHIQ_RETRY; -+ } -+ -+ release_service_messages(service); -+ -+ if (status == VCHIQ_SUCCESS) -+ status = queue_message(state, service, -+ VCHIQ_MAKE_MSG -+ (VCHIQ_MSG_CLOSE, -+ service->localport, -+ VCHIQ_MSG_DSTPORT(service->remoteport)), -+ NULL, 0, 0, QMFLAGS_NO_MUTEX_UNLOCK); -+ -+ if (status == VCHIQ_SUCCESS) { -+ if (!close_recvd) { -+ /* Change the state while the mutex is -+ still held */ -+ vchiq_set_service_state(service, -+ VCHIQ_SRVSTATE_CLOSESENT); -+ mutex_unlock(&state->slot_mutex); -+ if (service->sync) -+ mutex_unlock(&state->sync_mutex); -+ break; -+ } -+ } else if (service->srvstate == VCHIQ_SRVSTATE_OPENSYNC) { -+ mutex_unlock(&state->sync_mutex); -+ break; -+ } else -+ break; -+ -+ /* Change the state while the mutex is still held */ -+ vchiq_set_service_state(service, VCHIQ_SRVSTATE_CLOSERECVD); -+ mutex_unlock(&state->slot_mutex); -+ if (service->sync) -+ mutex_unlock(&state->sync_mutex); -+ -+ status = close_service_complete(service, -+ VCHIQ_SRVSTATE_CLOSERECVD); -+ break; -+ -+ case VCHIQ_SRVSTATE_CLOSESENT: -+ if (!close_recvd) -+ /* This happens when a process is killed mid-close */ -+ break; -+ -+ if (!state->is_master) { -+ if (!do_abort_bulks(service)) { -+ status = VCHIQ_RETRY; -+ break; -+ } -+ } -+ -+ if (status == VCHIQ_SUCCESS) -+ status = close_service_complete(service, -+ VCHIQ_SRVSTATE_CLOSERECVD); -+ break; -+ -+ case VCHIQ_SRVSTATE_CLOSERECVD: -+ if (!close_recvd && is_server) -+ /* Force into LISTENING mode */ -+ vchiq_set_service_state(service, -+ VCHIQ_SRVSTATE_LISTENING); -+ status = close_service_complete(service, -+ VCHIQ_SRVSTATE_CLOSERECVD); -+ break; -+ -+ default: -+ vchiq_log_error(vchiq_core_log_level, -+ "vchiq_close_service_internal(%d) called in state %s", -+ close_recvd, srvstate_names[service->srvstate]); -+ break; -+ } -+ -+ return status; -+} -+ -+/* Called from the application process upon process death */ -+void -+vchiq_terminate_service_internal(VCHIQ_SERVICE_T *service) -+{ -+ VCHIQ_STATE_T *state = service->state; -+ -+ vchiq_log_info(vchiq_core_log_level, "%d: tsi - (%d<->%d)", -+ state->id, service->localport, service->remoteport); -+ -+ mark_service_closing(service); -+ -+ /* Mark the service for removal by the slot handler */ -+ request_poll(state, service, VCHIQ_POLL_REMOVE); -+} -+ -+/* Called from the slot handler */ -+void -+vchiq_free_service_internal(VCHIQ_SERVICE_T *service) -+{ -+ VCHIQ_STATE_T *state = service->state; -+ -+ vchiq_log_info(vchiq_core_log_level, "%d: fsi - (%d)", -+ state->id, service->localport); -+ -+ switch (service->srvstate) { -+ case VCHIQ_SRVSTATE_OPENING: -+ case VCHIQ_SRVSTATE_CLOSED: -+ case VCHIQ_SRVSTATE_HIDDEN: -+ case VCHIQ_SRVSTATE_LISTENING: -+ case VCHIQ_SRVSTATE_CLOSEWAIT: -+ break; -+ default: -+ vchiq_log_error(vchiq_core_log_level, -+ "%d: fsi - (%d) in state %s", -+ state->id, service->localport, -+ srvstate_names[service->srvstate]); -+ return; -+ } -+ -+ vchiq_set_service_state(service, VCHIQ_SRVSTATE_FREE); -+ -+ up(&service->remove_event); -+ -+ /* Release the initial lock */ -+ unlock_service(service); -+} -+ -+VCHIQ_STATUS_T -+vchiq_connect_internal(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance) -+{ -+ VCHIQ_SERVICE_T *service; -+ int i; -+ -+ /* Find all services registered to this client and enable them. */ -+ i = 0; -+ while ((service = next_service_by_instance(state, instance, -+ &i)) != NULL) { -+ if (service->srvstate == VCHIQ_SRVSTATE_HIDDEN) -+ vchiq_set_service_state(service, -+ VCHIQ_SRVSTATE_LISTENING); -+ unlock_service(service); -+ } -+ -+ if (state->conn_state == VCHIQ_CONNSTATE_DISCONNECTED) { -+ if (queue_message(state, NULL, -+ VCHIQ_MAKE_MSG(VCHIQ_MSG_CONNECT, 0, 0), NULL, 0, -+ 0, QMFLAGS_IS_BLOCKING) == VCHIQ_RETRY) -+ return VCHIQ_RETRY; -+ -+ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTING); -+ } -+ -+ if (state->conn_state == VCHIQ_CONNSTATE_CONNECTING) { -+ if (down_interruptible(&state->connect) != 0) -+ return VCHIQ_RETRY; -+ -+ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTED); -+ up(&state->connect); -+ } -+ -+ return VCHIQ_SUCCESS; -+} -+ -+VCHIQ_STATUS_T -+vchiq_shutdown_internal(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance) -+{ -+ VCHIQ_SERVICE_T *service; -+ int i; -+ -+ /* Find all services registered to this client and enable them. */ -+ i = 0; -+ while ((service = next_service_by_instance(state, instance, -+ &i)) != NULL) { -+ (void)vchiq_remove_service(service->handle); -+ unlock_service(service); -+ } -+ -+ return VCHIQ_SUCCESS; -+} -+ -+VCHIQ_STATUS_T -+vchiq_pause_internal(VCHIQ_STATE_T *state) -+{ -+ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; -+ -+ switch (state->conn_state) { -+ case VCHIQ_CONNSTATE_CONNECTED: -+ /* Request a pause */ -+ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_PAUSING); -+ request_poll(state, NULL, 0); -+ break; -+ default: -+ vchiq_log_error(vchiq_core_log_level, -+ "vchiq_pause_internal in state %s\n", -+ conn_state_names[state->conn_state]); -+ status = VCHIQ_ERROR; -+ VCHIQ_STATS_INC(state, error_count); -+ break; -+ } -+ -+ return status; -+} -+ -+VCHIQ_STATUS_T -+vchiq_resume_internal(VCHIQ_STATE_T *state) -+{ -+ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; -+ -+ if (state->conn_state == VCHIQ_CONNSTATE_PAUSED) { -+ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_RESUMING); -+ request_poll(state, NULL, 0); -+ } else { -+ status = VCHIQ_ERROR; -+ VCHIQ_STATS_INC(state, error_count); -+ } -+ -+ return status; -+} -+ -+VCHIQ_STATUS_T -+vchiq_close_service(VCHIQ_SERVICE_HANDLE_T handle) -+{ -+ /* Unregister the service */ -+ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); -+ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; -+ -+ if (!service) -+ return VCHIQ_ERROR; -+ -+ vchiq_log_info(vchiq_core_log_level, -+ "%d: close_service:%d", -+ service->state->id, service->localport); -+ -+ if ((service->srvstate == VCHIQ_SRVSTATE_FREE) || -+ (service->srvstate == VCHIQ_SRVSTATE_LISTENING) || -+ (service->srvstate == VCHIQ_SRVSTATE_HIDDEN)) { -+ unlock_service(service); -+ return VCHIQ_ERROR; -+ } -+ -+ mark_service_closing(service); -+ -+ if (current == service->state->slot_handler_thread) { -+ status = vchiq_close_service_internal(service, -+ 0/*!close_recvd*/); -+ BUG_ON(status == VCHIQ_RETRY); -+ } else { -+ /* Mark the service for termination by the slot handler */ -+ request_poll(service->state, service, VCHIQ_POLL_TERMINATE); -+ } -+ -+ while (1) { -+ if (down_interruptible(&service->remove_event) != 0) { -+ status = VCHIQ_RETRY; -+ break; -+ } -+ -+ if ((service->srvstate == VCHIQ_SRVSTATE_FREE) || -+ (service->srvstate == VCHIQ_SRVSTATE_LISTENING) || -+ (service->srvstate == VCHIQ_SRVSTATE_OPEN)) -+ break; -+ -+ vchiq_log_warning(vchiq_core_log_level, -+ "%d: close_service:%d - waiting in state %s", -+ service->state->id, service->localport, -+ srvstate_names[service->srvstate]); -+ } -+ -+ if ((status == VCHIQ_SUCCESS) && -+ (service->srvstate != VCHIQ_SRVSTATE_FREE) && -+ (service->srvstate != VCHIQ_SRVSTATE_LISTENING)) -+ status = VCHIQ_ERROR; -+ -+ unlock_service(service); -+ -+ return status; -+} -+ -+VCHIQ_STATUS_T -+vchiq_remove_service(VCHIQ_SERVICE_HANDLE_T handle) -+{ -+ /* Unregister the service */ -+ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); -+ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; -+ -+ if (!service) -+ return VCHIQ_ERROR; -+ -+ vchiq_log_info(vchiq_core_log_level, -+ "%d: remove_service:%d", -+ service->state->id, service->localport); -+ -+ if (service->srvstate == VCHIQ_SRVSTATE_FREE) { -+ unlock_service(service); -+ return VCHIQ_ERROR; -+ } -+ -+ mark_service_closing(service); -+ -+ if ((service->srvstate == VCHIQ_SRVSTATE_HIDDEN) || -+ (current == service->state->slot_handler_thread)) { -+ /* Make it look like a client, because it must be removed and -+ not left in the LISTENING state. */ -+ service->public_fourcc = VCHIQ_FOURCC_INVALID; -+ -+ status = vchiq_close_service_internal(service, -+ 0/*!close_recvd*/); -+ BUG_ON(status == VCHIQ_RETRY); -+ } else { -+ /* Mark the service for removal by the slot handler */ -+ request_poll(service->state, service, VCHIQ_POLL_REMOVE); -+ } -+ while (1) { -+ if (down_interruptible(&service->remove_event) != 0) { -+ status = VCHIQ_RETRY; -+ break; -+ } -+ -+ if ((service->srvstate == VCHIQ_SRVSTATE_FREE) || -+ (service->srvstate == VCHIQ_SRVSTATE_OPEN)) -+ break; -+ -+ vchiq_log_warning(vchiq_core_log_level, -+ "%d: remove_service:%d - waiting in state %s", -+ service->state->id, service->localport, -+ srvstate_names[service->srvstate]); -+ } -+ -+ if ((status == VCHIQ_SUCCESS) && -+ (service->srvstate != VCHIQ_SRVSTATE_FREE)) -+ status = VCHIQ_ERROR; -+ -+ unlock_service(service); -+ -+ return status; -+} -+ -+ -+/* This function may be called by kernel threads or user threads. -+ * User threads may receive VCHIQ_RETRY to indicate that a signal has been -+ * received and the call should be retried after being returned to user -+ * context. -+ * When called in blocking mode, the userdata field points to a bulk_waiter -+ * structure. -+ */ -+VCHIQ_STATUS_T -+vchiq_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle, -+ VCHI_MEM_HANDLE_T memhandle, void *offset, int size, void *userdata, -+ VCHIQ_BULK_MODE_T mode, VCHIQ_BULK_DIR_T dir) -+{ -+ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); -+ VCHIQ_BULK_QUEUE_T *queue; -+ VCHIQ_BULK_T *bulk; -+ VCHIQ_STATE_T *state; -+ struct bulk_waiter *bulk_waiter = NULL; -+ const char dir_char = (dir == VCHIQ_BULK_TRANSMIT) ? 't' : 'r'; -+ const int dir_msgtype = (dir == VCHIQ_BULK_TRANSMIT) ? -+ VCHIQ_MSG_BULK_TX : VCHIQ_MSG_BULK_RX; -+ VCHIQ_STATUS_T status = VCHIQ_ERROR; -+ -+ if (!service || -+ (service->srvstate != VCHIQ_SRVSTATE_OPEN) || -+ ((memhandle == VCHI_MEM_HANDLE_INVALID) && (offset == NULL)) || -+ (vchiq_check_service(service) != VCHIQ_SUCCESS)) -+ goto error_exit; -+ -+ switch (mode) { -+ case VCHIQ_BULK_MODE_NOCALLBACK: -+ case VCHIQ_BULK_MODE_CALLBACK: -+ break; -+ case VCHIQ_BULK_MODE_BLOCKING: -+ bulk_waiter = (struct bulk_waiter *)userdata; -+ sema_init(&bulk_waiter->event, 0); -+ bulk_waiter->actual = 0; -+ bulk_waiter->bulk = NULL; -+ break; -+ case VCHIQ_BULK_MODE_WAITING: -+ bulk_waiter = (struct bulk_waiter *)userdata; -+ bulk = bulk_waiter->bulk; -+ goto waiting; -+ default: -+ goto error_exit; -+ } -+ -+ state = service->state; -+ -+ queue = (dir == VCHIQ_BULK_TRANSMIT) ? -+ &service->bulk_tx : &service->bulk_rx; -+ -+ if (mutex_lock_interruptible(&service->bulk_mutex) != 0) { -+ status = VCHIQ_RETRY; -+ goto error_exit; -+ } -+ -+ if (queue->local_insert == queue->remove + VCHIQ_NUM_SERVICE_BULKS) { -+ VCHIQ_SERVICE_STATS_INC(service, bulk_stalls); -+ do { -+ mutex_unlock(&service->bulk_mutex); -+ if (down_interruptible(&service->bulk_remove_event) -+ != 0) { -+ status = VCHIQ_RETRY; -+ goto error_exit; -+ } -+ if (mutex_lock_interruptible(&service->bulk_mutex) -+ != 0) { -+ status = VCHIQ_RETRY; -+ goto error_exit; -+ } -+ } while (queue->local_insert == queue->remove + -+ VCHIQ_NUM_SERVICE_BULKS); -+ } -+ -+ bulk = &queue->bulks[BULK_INDEX(queue->local_insert)]; -+ -+ bulk->mode = mode; -+ bulk->dir = dir; -+ bulk->userdata = userdata; -+ bulk->size = size; -+ bulk->actual = VCHIQ_BULK_ACTUAL_ABORTED; -+ -+ if (vchiq_prepare_bulk_data(bulk, memhandle, offset, size, dir) != -+ VCHIQ_SUCCESS) -+ goto unlock_error_exit; -+ -+ wmb(); -+ -+ vchiq_log_info(vchiq_core_log_level, -+ "%d: bt (%d->%d) %cx %x@%x %x", -+ state->id, -+ service->localport, service->remoteport, dir_char, -+ size, (unsigned int)bulk->data, (unsigned int)userdata); -+ -+ /* The slot mutex must be held when the service is being closed, so -+ claim it here to ensure that isn't happening */ -+ if (mutex_lock_interruptible(&state->slot_mutex) != 0) { -+ status = VCHIQ_RETRY; -+ goto cancel_bulk_error_exit; -+ } -+ -+ if (service->srvstate != VCHIQ_SRVSTATE_OPEN) -+ goto unlock_both_error_exit; -+ -+ if (state->is_master) { -+ queue->local_insert++; -+ if (resolve_bulks(service, queue)) -+ request_poll(state, service, -+ (dir == VCHIQ_BULK_TRANSMIT) ? -+ VCHIQ_POLL_TXNOTIFY : VCHIQ_POLL_RXNOTIFY); -+ } else { -+ int payload[2] = { (int)bulk->data, bulk->size }; -+ VCHIQ_ELEMENT_T element = { payload, sizeof(payload) }; -+ -+ status = queue_message(state, NULL, -+ VCHIQ_MAKE_MSG(dir_msgtype, -+ service->localport, service->remoteport), -+ &element, 1, sizeof(payload), -+ QMFLAGS_IS_BLOCKING | -+ QMFLAGS_NO_MUTEX_LOCK | -+ QMFLAGS_NO_MUTEX_UNLOCK); -+ if (status != VCHIQ_SUCCESS) { -+ goto unlock_both_error_exit; -+ } -+ queue->local_insert++; -+ } -+ -+ mutex_unlock(&state->slot_mutex); -+ mutex_unlock(&service->bulk_mutex); -+ -+ vchiq_log_trace(vchiq_core_log_level, -+ "%d: bt:%d %cx li=%x ri=%x p=%x", -+ state->id, -+ service->localport, dir_char, -+ queue->local_insert, queue->remote_insert, queue->process); -+ -+waiting: -+ unlock_service(service); -+ -+ status = VCHIQ_SUCCESS; -+ -+ if (bulk_waiter) { -+ bulk_waiter->bulk = bulk; -+ if (down_interruptible(&bulk_waiter->event) != 0) -+ status = VCHIQ_RETRY; -+ else if (bulk_waiter->actual == VCHIQ_BULK_ACTUAL_ABORTED) -+ status = VCHIQ_ERROR; -+ } -+ -+ return status; -+ -+unlock_both_error_exit: -+ mutex_unlock(&state->slot_mutex); -+cancel_bulk_error_exit: -+ vchiq_complete_bulk(bulk); -+unlock_error_exit: -+ mutex_unlock(&service->bulk_mutex); -+ -+error_exit: -+ if (service) -+ unlock_service(service); -+ return status; -+} -+ -+VCHIQ_STATUS_T -+vchiq_queue_message(VCHIQ_SERVICE_HANDLE_T handle, -+ const VCHIQ_ELEMENT_T *elements, unsigned int count) -+{ -+ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); -+ VCHIQ_STATUS_T status = VCHIQ_ERROR; -+ -+ unsigned int size = 0; -+ unsigned int i; -+ -+ if (!service || -+ (vchiq_check_service(service) != VCHIQ_SUCCESS)) -+ goto error_exit; -+ -+ for (i = 0; i < (unsigned int)count; i++) { -+ if (elements[i].size) { -+ if (elements[i].data == NULL) { -+ VCHIQ_SERVICE_STATS_INC(service, error_count); -+ goto error_exit; -+ } -+ size += elements[i].size; -+ } -+ } -+ -+ if (size > VCHIQ_MAX_MSG_SIZE) { -+ VCHIQ_SERVICE_STATS_INC(service, error_count); -+ goto error_exit; -+ } -+ -+ switch (service->srvstate) { -+ case VCHIQ_SRVSTATE_OPEN: -+ status = queue_message(service->state, service, -+ VCHIQ_MAKE_MSG(VCHIQ_MSG_DATA, -+ service->localport, -+ service->remoteport), -+ elements, count, size, 1); -+ break; -+ case VCHIQ_SRVSTATE_OPENSYNC: -+ status = queue_message_sync(service->state, service, -+ VCHIQ_MAKE_MSG(VCHIQ_MSG_DATA, -+ service->localport, -+ service->remoteport), -+ elements, count, size, 1); -+ break; -+ default: -+ status = VCHIQ_ERROR; -+ break; -+ } -+ -+error_exit: -+ if (service) -+ unlock_service(service); -+ -+ return status; -+} -+ -+void -+vchiq_release_message(VCHIQ_SERVICE_HANDLE_T handle, VCHIQ_HEADER_T *header) -+{ -+ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); -+ VCHIQ_SHARED_STATE_T *remote; -+ VCHIQ_STATE_T *state; -+ int slot_index; -+ -+ if (!service) -+ return; -+ -+ state = service->state; -+ remote = state->remote; -+ -+ slot_index = SLOT_INDEX_FROM_DATA(state, (void *)header); -+ -+ if ((slot_index >= remote->slot_first) && -+ (slot_index <= remote->slot_last)) { -+ int msgid = header->msgid; -+ if (msgid & VCHIQ_MSGID_CLAIMED) { -+ VCHIQ_SLOT_INFO_T *slot_info = -+ SLOT_INFO_FROM_INDEX(state, slot_index); -+ -+ release_slot(state, slot_info, header, service); -+ } -+ } else if (slot_index == remote->slot_sync) -+ release_message_sync(state, header); -+ -+ unlock_service(service); -+} -+ -+static void -+release_message_sync(VCHIQ_STATE_T *state, VCHIQ_HEADER_T *header) -+{ -+ header->msgid = VCHIQ_MSGID_PADDING; -+ wmb(); -+ remote_event_signal(&state->remote->sync_release); -+} -+ -+VCHIQ_STATUS_T -+vchiq_get_peer_version(VCHIQ_SERVICE_HANDLE_T handle, short *peer_version) -+{ -+ VCHIQ_STATUS_T status = VCHIQ_ERROR; -+ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); -+ -+ if (!service || -+ (vchiq_check_service(service) != VCHIQ_SUCCESS) || -+ !peer_version) -+ goto exit; -+ *peer_version = service->peer_version; -+ status = VCHIQ_SUCCESS; -+ -+exit: -+ if (service) -+ unlock_service(service); -+ return status; -+} -+ -+VCHIQ_STATUS_T -+vchiq_get_config(VCHIQ_INSTANCE_T instance, -+ int config_size, VCHIQ_CONFIG_T *pconfig) -+{ -+ VCHIQ_CONFIG_T config; -+ -+ (void)instance; -+ -+ config.max_msg_size = VCHIQ_MAX_MSG_SIZE; -+ config.bulk_threshold = VCHIQ_MAX_MSG_SIZE; -+ config.max_outstanding_bulks = VCHIQ_NUM_SERVICE_BULKS; -+ config.max_services = VCHIQ_MAX_SERVICES; -+ config.version = VCHIQ_VERSION; -+ config.version_min = VCHIQ_VERSION_MIN; -+ -+ if (config_size > sizeof(VCHIQ_CONFIG_T)) -+ return VCHIQ_ERROR; -+ -+ memcpy(pconfig, &config, -+ min(config_size, (int)(sizeof(VCHIQ_CONFIG_T)))); -+ -+ return VCHIQ_SUCCESS; -+} -+ -+VCHIQ_STATUS_T -+vchiq_set_service_option(VCHIQ_SERVICE_HANDLE_T handle, -+ VCHIQ_SERVICE_OPTION_T option, int value) -+{ -+ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); -+ VCHIQ_STATUS_T status = VCHIQ_ERROR; -+ -+ if (service) { -+ switch (option) { -+ case VCHIQ_SERVICE_OPTION_AUTOCLOSE: -+ service->auto_close = value; -+ status = VCHIQ_SUCCESS; -+ break; -+ -+ case VCHIQ_SERVICE_OPTION_SLOT_QUOTA: { -+ VCHIQ_SERVICE_QUOTA_T *service_quota = -+ &service->state->service_quotas[ -+ service->localport]; -+ if (value == 0) -+ value = service->state->default_slot_quota; -+ if ((value >= service_quota->slot_use_count) && -+ (value < (unsigned short)~0)) { -+ service_quota->slot_quota = value; -+ if ((value >= service_quota->slot_use_count) && -+ (service_quota->message_quota >= -+ service_quota->message_use_count)) { -+ /* Signal the service that it may have -+ ** dropped below its quota */ -+ up(&service_quota->quota_event); -+ } -+ status = VCHIQ_SUCCESS; -+ } -+ } break; -+ -+ case VCHIQ_SERVICE_OPTION_MESSAGE_QUOTA: { -+ VCHIQ_SERVICE_QUOTA_T *service_quota = -+ &service->state->service_quotas[ -+ service->localport]; -+ if (value == 0) -+ value = service->state->default_message_quota; -+ if ((value >= service_quota->message_use_count) && -+ (value < (unsigned short)~0)) { -+ service_quota->message_quota = value; -+ if ((value >= -+ service_quota->message_use_count) && -+ (service_quota->slot_quota >= -+ service_quota->slot_use_count)) -+ /* Signal the service that it may have -+ ** dropped below its quota */ -+ up(&service_quota->quota_event); -+ status = VCHIQ_SUCCESS; -+ } -+ } break; -+ -+ case VCHIQ_SERVICE_OPTION_SYNCHRONOUS: -+ if ((service->srvstate == VCHIQ_SRVSTATE_HIDDEN) || -+ (service->srvstate == -+ VCHIQ_SRVSTATE_LISTENING)) { -+ service->sync = value; -+ status = VCHIQ_SUCCESS; -+ } -+ break; -+ -+ case VCHIQ_SERVICE_OPTION_TRACE: -+ service->trace = value; -+ status = VCHIQ_SUCCESS; -+ break; -+ -+ default: -+ break; -+ } -+ unlock_service(service); -+ } -+ -+ return status; -+} -+ -+void -+vchiq_dump_shared_state(void *dump_context, VCHIQ_STATE_T *state, -+ VCHIQ_SHARED_STATE_T *shared, const char *label) -+{ -+ static const char *const debug_names[] = { -+ "", -+ "SLOT_HANDLER_COUNT", -+ "SLOT_HANDLER_LINE", -+ "PARSE_LINE", -+ "PARSE_HEADER", -+ "PARSE_MSGID", -+ "AWAIT_COMPLETION_LINE", -+ "DEQUEUE_MESSAGE_LINE", -+ "SERVICE_CALLBACK_LINE", -+ "MSG_QUEUE_FULL_COUNT", -+ "COMPLETION_QUEUE_FULL_COUNT" -+ }; -+ int i; -+ -+ char buf[80]; -+ int len; -+ len = snprintf(buf, sizeof(buf), -+ " %s: slots %d-%d tx_pos=%x recycle=%x", -+ label, shared->slot_first, shared->slot_last, -+ shared->tx_pos, shared->slot_queue_recycle); -+ vchiq_dump(dump_context, buf, len + 1); -+ -+ len = snprintf(buf, sizeof(buf), -+ " Slots claimed:"); -+ vchiq_dump(dump_context, buf, len + 1); -+ -+ for (i = shared->slot_first; i <= shared->slot_last; i++) { -+ VCHIQ_SLOT_INFO_T slot_info = *SLOT_INFO_FROM_INDEX(state, i); -+ if (slot_info.use_count != slot_info.release_count) { -+ len = snprintf(buf, sizeof(buf), -+ " %d: %d/%d", i, slot_info.use_count, -+ slot_info.release_count); -+ vchiq_dump(dump_context, buf, len + 1); -+ } -+ } -+ -+ for (i = 1; i < shared->debug[DEBUG_ENTRIES]; i++) { -+ len = snprintf(buf, sizeof(buf), " DEBUG: %s = %d(%x)", -+ debug_names[i], shared->debug[i], shared->debug[i]); -+ vchiq_dump(dump_context, buf, len + 1); -+ } -+} -+ -+void -+vchiq_dump_state(void *dump_context, VCHIQ_STATE_T *state) -+{ -+ char buf[80]; -+ int len; -+ int i; -+ -+ len = snprintf(buf, sizeof(buf), "State %d: %s", state->id, -+ conn_state_names[state->conn_state]); -+ vchiq_dump(dump_context, buf, len + 1); -+ -+ len = snprintf(buf, sizeof(buf), -+ " tx_pos=%x(@%x), rx_pos=%x(@%x)", -+ state->local->tx_pos, -+ (uint32_t)state->tx_data + -+ (state->local_tx_pos & VCHIQ_SLOT_MASK), -+ state->rx_pos, -+ (uint32_t)state->rx_data + -+ (state->rx_pos & VCHIQ_SLOT_MASK)); -+ vchiq_dump(dump_context, buf, len + 1); -+ -+ len = snprintf(buf, sizeof(buf), -+ " Version: %d (min %d)", -+ VCHIQ_VERSION, VCHIQ_VERSION_MIN); -+ vchiq_dump(dump_context, buf, len + 1); -+ -+ if (VCHIQ_ENABLE_STATS) { -+ len = snprintf(buf, sizeof(buf), -+ " Stats: ctrl_tx_count=%d, ctrl_rx_count=%d, " -+ "error_count=%d", -+ state->stats.ctrl_tx_count, state->stats.ctrl_rx_count, -+ state->stats.error_count); -+ vchiq_dump(dump_context, buf, len + 1); -+ } -+ -+ len = snprintf(buf, sizeof(buf), -+ " Slots: %d available (%d data), %d recyclable, %d stalls " -+ "(%d data)", -+ ((state->slot_queue_available * VCHIQ_SLOT_SIZE) - -+ state->local_tx_pos) / VCHIQ_SLOT_SIZE, -+ state->data_quota - state->data_use_count, -+ state->local->slot_queue_recycle - state->slot_queue_available, -+ state->stats.slot_stalls, state->stats.data_stalls); -+ vchiq_dump(dump_context, buf, len + 1); -+ -+ vchiq_dump_platform_state(dump_context); -+ -+ vchiq_dump_shared_state(dump_context, state, state->local, "Local"); -+ vchiq_dump_shared_state(dump_context, state, state->remote, "Remote"); -+ -+ vchiq_dump_platform_instances(dump_context); -+ -+ for (i = 0; i < state->unused_service; i++) { -+ VCHIQ_SERVICE_T *service = find_service_by_port(state, i); -+ -+ if (service) { -+ vchiq_dump_service_state(dump_context, service); -+ unlock_service(service); -+ } -+ } -+} -+ -+void -+vchiq_dump_service_state(void *dump_context, VCHIQ_SERVICE_T *service) -+{ -+ char buf[80]; -+ int len; -+ -+ len = snprintf(buf, sizeof(buf), "Service %d: %s (ref %u)", -+ service->localport, srvstate_names[service->srvstate], -+ service->ref_count - 1); /*Don't include the lock just taken*/ -+ -+ if (service->srvstate != VCHIQ_SRVSTATE_FREE) { -+ char remoteport[30]; -+ VCHIQ_SERVICE_QUOTA_T *service_quota = -+ &service->state->service_quotas[service->localport]; -+ int fourcc = service->base.fourcc; -+ int tx_pending, rx_pending; -+ if (service->remoteport != VCHIQ_PORT_FREE) { -+ int len2 = snprintf(remoteport, sizeof(remoteport), -+ "%d", service->remoteport); -+ if (service->public_fourcc != VCHIQ_FOURCC_INVALID) -+ snprintf(remoteport + len2, -+ sizeof(remoteport) - len2, -+ " (client %x)", service->client_id); -+ } else -+ strcpy(remoteport, "n/a"); -+ -+ len += snprintf(buf + len, sizeof(buf) - len, -+ " '%c%c%c%c' remote %s (msg use %d/%d, slot use %d/%d)", -+ VCHIQ_FOURCC_AS_4CHARS(fourcc), -+ remoteport, -+ service_quota->message_use_count, -+ service_quota->message_quota, -+ service_quota->slot_use_count, -+ service_quota->slot_quota); -+ -+ vchiq_dump(dump_context, buf, len + 1); -+ -+ tx_pending = service->bulk_tx.local_insert - -+ service->bulk_tx.remote_insert; -+ -+ rx_pending = service->bulk_rx.local_insert - -+ service->bulk_rx.remote_insert; -+ -+ len = snprintf(buf, sizeof(buf), -+ " Bulk: tx_pending=%d (size %d)," -+ " rx_pending=%d (size %d)", -+ tx_pending, -+ tx_pending ? service->bulk_tx.bulks[ -+ BULK_INDEX(service->bulk_tx.remove)].size : 0, -+ rx_pending, -+ rx_pending ? service->bulk_rx.bulks[ -+ BULK_INDEX(service->bulk_rx.remove)].size : 0); -+ -+ if (VCHIQ_ENABLE_STATS) { -+ vchiq_dump(dump_context, buf, len + 1); -+ -+ len = snprintf(buf, sizeof(buf), -+ " Ctrl: tx_count=%d, tx_bytes=%llu, " -+ "rx_count=%d, rx_bytes=%llu", -+ service->stats.ctrl_tx_count, -+ service->stats.ctrl_tx_bytes, -+ service->stats.ctrl_rx_count, -+ service->stats.ctrl_rx_bytes); -+ vchiq_dump(dump_context, buf, len + 1); -+ -+ len = snprintf(buf, sizeof(buf), -+ " Bulk: tx_count=%d, tx_bytes=%llu, " -+ "rx_count=%d, rx_bytes=%llu", -+ service->stats.bulk_tx_count, -+ service->stats.bulk_tx_bytes, -+ service->stats.bulk_rx_count, -+ service->stats.bulk_rx_bytes); -+ vchiq_dump(dump_context, buf, len + 1); -+ -+ len = snprintf(buf, sizeof(buf), -+ " %d quota stalls, %d slot stalls, " -+ "%d bulk stalls, %d aborted, %d errors", -+ service->stats.quota_stalls, -+ service->stats.slot_stalls, -+ service->stats.bulk_stalls, -+ service->stats.bulk_aborted_count, -+ service->stats.error_count); -+ } -+ } -+ -+ vchiq_dump(dump_context, buf, len + 1); -+ -+ if (service->srvstate != VCHIQ_SRVSTATE_FREE) -+ vchiq_dump_platform_service_state(dump_context, service); -+} -+ -+ -+void -+vchiq_loud_error_header(void) -+{ -+ vchiq_log_error(vchiq_core_log_level, -+ "============================================================" -+ "================"); -+ vchiq_log_error(vchiq_core_log_level, -+ "============================================================" -+ "================"); -+ vchiq_log_error(vchiq_core_log_level, "====="); -+} -+ -+void -+vchiq_loud_error_footer(void) -+{ -+ vchiq_log_error(vchiq_core_log_level, "====="); -+ vchiq_log_error(vchiq_core_log_level, -+ "============================================================" -+ "================"); -+ vchiq_log_error(vchiq_core_log_level, -+ "============================================================" -+ "================"); -+} -+ -+ -+VCHIQ_STATUS_T vchiq_send_remote_use(VCHIQ_STATE_T *state) -+{ -+ VCHIQ_STATUS_T status = VCHIQ_RETRY; -+ if (state->conn_state != VCHIQ_CONNSTATE_DISCONNECTED) -+ status = queue_message(state, NULL, -+ VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_USE, 0, 0), -+ NULL, 0, 0, 0); -+ return status; -+} -+ -+VCHIQ_STATUS_T vchiq_send_remote_release(VCHIQ_STATE_T *state) -+{ -+ VCHIQ_STATUS_T status = VCHIQ_RETRY; -+ if (state->conn_state != VCHIQ_CONNSTATE_DISCONNECTED) -+ status = queue_message(state, NULL, -+ VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_RELEASE, 0, 0), -+ NULL, 0, 0, 0); -+ return status; -+} -+ -+VCHIQ_STATUS_T vchiq_send_remote_use_active(VCHIQ_STATE_T *state) -+{ -+ VCHIQ_STATUS_T status = VCHIQ_RETRY; -+ if (state->conn_state != VCHIQ_CONNSTATE_DISCONNECTED) -+ status = queue_message(state, NULL, -+ VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_USE_ACTIVE, 0, 0), -+ NULL, 0, 0, 0); -+ return status; -+} -+ -+void vchiq_log_dump_mem(const char *label, uint32_t addr, const void *voidMem, -+ size_t numBytes) -+{ -+ const uint8_t *mem = (const uint8_t *)voidMem; -+ size_t offset; -+ char lineBuf[100]; -+ char *s; -+ -+ while (numBytes > 0) { -+ s = lineBuf; -+ -+ for (offset = 0; offset < 16; offset++) { -+ if (offset < numBytes) -+ s += snprintf(s, 4, "%02x ", mem[offset]); -+ else -+ s += snprintf(s, 4, " "); -+ } -+ -+ for (offset = 0; offset < 16; offset++) { -+ if (offset < numBytes) { -+ uint8_t ch = mem[offset]; -+ -+ if ((ch < ' ') || (ch > '~')) -+ ch = '.'; -+ *s++ = (char)ch; -+ } -+ } -+ *s++ = '\0'; -+ -+ if ((label != NULL) && (*label != '\0')) -+ vchiq_log_trace(VCHIQ_LOG_TRACE, -+ "%s: %08x: %s", label, addr, lineBuf); -+ else -+ vchiq_log_trace(VCHIQ_LOG_TRACE, -+ "%08x: %s", addr, lineBuf); -+ -+ addr += 16; -+ mem += 16; -+ if (numBytes > 16) -+ numBytes -= 16; -+ else -+ numBytes = 0; -+ } -+} -diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h ---- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h 2015-11-29 09:42:38.075221210 +0100 -@@ -0,0 +1,712 @@ -+/** -+ * Copyright (c) 2010-2012 Broadcom. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef VCHIQ_CORE_H -+#define VCHIQ_CORE_H -+ -+#include -+#include -+#include -+ -+#include "vchiq_cfg.h" -+ -+#include "vchiq.h" -+ -+/* Run time control of log level, based on KERN_XXX level. */ -+#define VCHIQ_LOG_DEFAULT 4 -+#define VCHIQ_LOG_ERROR 3 -+#define VCHIQ_LOG_WARNING 4 -+#define VCHIQ_LOG_INFO 6 -+#define VCHIQ_LOG_TRACE 7 -+ -+#define VCHIQ_LOG_PREFIX KERN_INFO "vchiq: " -+ -+#ifndef vchiq_log_error -+#define vchiq_log_error(cat, fmt, ...) \ -+ do { if (cat >= VCHIQ_LOG_ERROR) \ -+ printk(VCHIQ_LOG_PREFIX fmt "\n", ##__VA_ARGS__); } while (0) -+#endif -+#ifndef vchiq_log_warning -+#define vchiq_log_warning(cat, fmt, ...) \ -+ do { if (cat >= VCHIQ_LOG_WARNING) \ -+ printk(VCHIQ_LOG_PREFIX fmt "\n", ##__VA_ARGS__); } while (0) -+#endif -+#ifndef vchiq_log_info -+#define vchiq_log_info(cat, fmt, ...) \ -+ do { if (cat >= VCHIQ_LOG_INFO) \ -+ printk(VCHIQ_LOG_PREFIX fmt "\n", ##__VA_ARGS__); } while (0) -+#endif -+#ifndef vchiq_log_trace -+#define vchiq_log_trace(cat, fmt, ...) \ -+ do { if (cat >= VCHIQ_LOG_TRACE) \ -+ printk(VCHIQ_LOG_PREFIX fmt "\n", ##__VA_ARGS__); } while (0) -+#endif -+ -+#define vchiq_loud_error(...) \ -+ vchiq_log_error(vchiq_core_log_level, "===== " __VA_ARGS__) -+ -+#ifndef vchiq_static_assert -+#define vchiq_static_assert(cond) __attribute__((unused)) \ -+ extern int vchiq_static_assert[(cond) ? 1 : -1] -+#endif -+ -+#define IS_POW2(x) (x && ((x & (x - 1)) == 0)) -+ -+/* Ensure that the slot size and maximum number of slots are powers of 2 */ -+vchiq_static_assert(IS_POW2(VCHIQ_SLOT_SIZE)); -+vchiq_static_assert(IS_POW2(VCHIQ_MAX_SLOTS)); -+vchiq_static_assert(IS_POW2(VCHIQ_MAX_SLOTS_PER_SIDE)); -+ -+#define VCHIQ_SLOT_MASK (VCHIQ_SLOT_SIZE - 1) -+#define VCHIQ_SLOT_QUEUE_MASK (VCHIQ_MAX_SLOTS_PER_SIDE - 1) -+#define VCHIQ_SLOT_ZERO_SLOTS ((sizeof(VCHIQ_SLOT_ZERO_T) + \ -+ VCHIQ_SLOT_SIZE - 1) / VCHIQ_SLOT_SIZE) -+ -+#define VCHIQ_MSG_PADDING 0 /* - */ -+#define VCHIQ_MSG_CONNECT 1 /* - */ -+#define VCHIQ_MSG_OPEN 2 /* + (srcport, -), fourcc, client_id */ -+#define VCHIQ_MSG_OPENACK 3 /* + (srcport, dstport) */ -+#define VCHIQ_MSG_CLOSE 4 /* + (srcport, dstport) */ -+#define VCHIQ_MSG_DATA 5 /* + (srcport, dstport) */ -+#define VCHIQ_MSG_BULK_RX 6 /* + (srcport, dstport), data, size */ -+#define VCHIQ_MSG_BULK_TX 7 /* + (srcport, dstport), data, size */ -+#define VCHIQ_MSG_BULK_RX_DONE 8 /* + (srcport, dstport), actual */ -+#define VCHIQ_MSG_BULK_TX_DONE 9 /* + (srcport, dstport), actual */ -+#define VCHIQ_MSG_PAUSE 10 /* - */ -+#define VCHIQ_MSG_RESUME 11 /* - */ -+#define VCHIQ_MSG_REMOTE_USE 12 /* - */ -+#define VCHIQ_MSG_REMOTE_RELEASE 13 /* - */ -+#define VCHIQ_MSG_REMOTE_USE_ACTIVE 14 /* - */ -+ -+#define VCHIQ_PORT_MAX (VCHIQ_MAX_SERVICES - 1) -+#define VCHIQ_PORT_FREE 0x1000 -+#define VCHIQ_PORT_IS_VALID(port) (port < VCHIQ_PORT_FREE) -+#define VCHIQ_MAKE_MSG(type, srcport, dstport) \ -+ ((type<<24) | (srcport<<12) | (dstport<<0)) -+#define VCHIQ_MSG_TYPE(msgid) ((unsigned int)msgid >> 24) -+#define VCHIQ_MSG_SRCPORT(msgid) \ -+ (unsigned short)(((unsigned int)msgid >> 12) & 0xfff) -+#define VCHIQ_MSG_DSTPORT(msgid) \ -+ ((unsigned short)msgid & 0xfff) -+ -+#define VCHIQ_FOURCC_AS_4CHARS(fourcc) \ -+ ((fourcc) >> 24) & 0xff, \ -+ ((fourcc) >> 16) & 0xff, \ -+ ((fourcc) >> 8) & 0xff, \ -+ (fourcc) & 0xff -+ -+/* Ensure the fields are wide enough */ -+vchiq_static_assert(VCHIQ_MSG_SRCPORT(VCHIQ_MAKE_MSG(0, 0, VCHIQ_PORT_MAX)) -+ == 0); -+vchiq_static_assert(VCHIQ_MSG_TYPE(VCHIQ_MAKE_MSG(0, VCHIQ_PORT_MAX, 0)) == 0); -+vchiq_static_assert((unsigned int)VCHIQ_PORT_MAX < -+ (unsigned int)VCHIQ_PORT_FREE); -+ -+#define VCHIQ_MSGID_PADDING VCHIQ_MAKE_MSG(VCHIQ_MSG_PADDING, 0, 0) -+#define VCHIQ_MSGID_CLAIMED 0x40000000 -+ -+#define VCHIQ_FOURCC_INVALID 0x00000000 -+#define VCHIQ_FOURCC_IS_LEGAL(fourcc) (fourcc != VCHIQ_FOURCC_INVALID) -+ -+#define VCHIQ_BULK_ACTUAL_ABORTED -1 -+ -+typedef uint32_t BITSET_T; -+ -+vchiq_static_assert((sizeof(BITSET_T) * 8) == 32); -+ -+#define BITSET_SIZE(b) ((b + 31) >> 5) -+#define BITSET_WORD(b) (b >> 5) -+#define BITSET_BIT(b) (1 << (b & 31)) -+#define BITSET_ZERO(bs) memset(bs, 0, sizeof(bs)) -+#define BITSET_IS_SET(bs, b) (bs[BITSET_WORD(b)] & BITSET_BIT(b)) -+#define BITSET_SET(bs, b) (bs[BITSET_WORD(b)] |= BITSET_BIT(b)) -+#define BITSET_CLR(bs, b) (bs[BITSET_WORD(b)] &= ~BITSET_BIT(b)) -+ -+#if VCHIQ_ENABLE_STATS -+#define VCHIQ_STATS_INC(state, stat) (state->stats. stat++) -+#define VCHIQ_SERVICE_STATS_INC(service, stat) (service->stats. stat++) -+#define VCHIQ_SERVICE_STATS_ADD(service, stat, addend) \ -+ (service->stats. stat += addend) -+#else -+#define VCHIQ_STATS_INC(state, stat) ((void)0) -+#define VCHIQ_SERVICE_STATS_INC(service, stat) ((void)0) -+#define VCHIQ_SERVICE_STATS_ADD(service, stat, addend) ((void)0) -+#endif -+ -+enum { -+ DEBUG_ENTRIES, -+#if VCHIQ_ENABLE_DEBUG -+ DEBUG_SLOT_HANDLER_COUNT, -+ DEBUG_SLOT_HANDLER_LINE, -+ DEBUG_PARSE_LINE, -+ DEBUG_PARSE_HEADER, -+ DEBUG_PARSE_MSGID, -+ DEBUG_AWAIT_COMPLETION_LINE, -+ DEBUG_DEQUEUE_MESSAGE_LINE, -+ DEBUG_SERVICE_CALLBACK_LINE, -+ DEBUG_MSG_QUEUE_FULL_COUNT, -+ DEBUG_COMPLETION_QUEUE_FULL_COUNT, -+#endif -+ DEBUG_MAX -+}; -+ -+#if VCHIQ_ENABLE_DEBUG -+ -+#define DEBUG_INITIALISE(local) int *debug_ptr = (local)->debug; -+#define DEBUG_TRACE(d) \ -+ do { debug_ptr[DEBUG_ ## d] = __LINE__; dsb(); } while (0) -+#define DEBUG_VALUE(d, v) \ -+ do { debug_ptr[DEBUG_ ## d] = (v); dsb(); } while (0) -+#define DEBUG_COUNT(d) \ -+ do { debug_ptr[DEBUG_ ## d]++; dsb(); } while (0) -+ -+#else /* VCHIQ_ENABLE_DEBUG */ -+ -+#define DEBUG_INITIALISE(local) -+#define DEBUG_TRACE(d) -+#define DEBUG_VALUE(d, v) -+#define DEBUG_COUNT(d) -+ -+#endif /* VCHIQ_ENABLE_DEBUG */ -+ -+typedef enum { -+ VCHIQ_CONNSTATE_DISCONNECTED, -+ VCHIQ_CONNSTATE_CONNECTING, -+ VCHIQ_CONNSTATE_CONNECTED, -+ VCHIQ_CONNSTATE_PAUSING, -+ VCHIQ_CONNSTATE_PAUSE_SENT, -+ VCHIQ_CONNSTATE_PAUSED, -+ VCHIQ_CONNSTATE_RESUMING, -+ VCHIQ_CONNSTATE_PAUSE_TIMEOUT, -+ VCHIQ_CONNSTATE_RESUME_TIMEOUT -+} VCHIQ_CONNSTATE_T; -+ -+enum { -+ VCHIQ_SRVSTATE_FREE, -+ VCHIQ_SRVSTATE_HIDDEN, -+ VCHIQ_SRVSTATE_LISTENING, -+ VCHIQ_SRVSTATE_OPENING, -+ VCHIQ_SRVSTATE_OPEN, -+ VCHIQ_SRVSTATE_OPENSYNC, -+ VCHIQ_SRVSTATE_CLOSESENT, -+ VCHIQ_SRVSTATE_CLOSERECVD, -+ VCHIQ_SRVSTATE_CLOSEWAIT, -+ VCHIQ_SRVSTATE_CLOSED -+}; -+ -+enum { -+ VCHIQ_POLL_TERMINATE, -+ VCHIQ_POLL_REMOVE, -+ VCHIQ_POLL_TXNOTIFY, -+ VCHIQ_POLL_RXNOTIFY, -+ VCHIQ_POLL_COUNT -+}; -+ -+typedef enum { -+ VCHIQ_BULK_TRANSMIT, -+ VCHIQ_BULK_RECEIVE -+} VCHIQ_BULK_DIR_T; -+ -+typedef void (*VCHIQ_USERDATA_TERM_T)(void *userdata); -+ -+typedef struct vchiq_bulk_struct { -+ short mode; -+ short dir; -+ void *userdata; -+ VCHI_MEM_HANDLE_T handle; -+ void *data; -+ int size; -+ void *remote_data; -+ int remote_size; -+ int actual; -+} VCHIQ_BULK_T; -+ -+typedef struct vchiq_bulk_queue_struct { -+ int local_insert; /* Where to insert the next local bulk */ -+ int remote_insert; /* Where to insert the next remote bulk (master) */ -+ int process; /* Bulk to transfer next */ -+ int remote_notify; /* Bulk to notify the remote client of next (mstr) */ -+ int remove; /* Bulk to notify the local client of, and remove, -+ ** next */ -+ VCHIQ_BULK_T bulks[VCHIQ_NUM_SERVICE_BULKS]; -+} VCHIQ_BULK_QUEUE_T; -+ -+typedef struct remote_event_struct { -+ int armed; -+ int fired; -+ struct semaphore *event; -+} REMOTE_EVENT_T; -+ -+typedef struct opaque_platform_state_t *VCHIQ_PLATFORM_STATE_T; -+ -+typedef struct vchiq_state_struct VCHIQ_STATE_T; -+ -+typedef struct vchiq_slot_struct { -+ char data[VCHIQ_SLOT_SIZE]; -+} VCHIQ_SLOT_T; -+ -+typedef struct vchiq_slot_info_struct { -+ /* Use two counters rather than one to avoid the need for a mutex. */ -+ short use_count; -+ short release_count; -+} VCHIQ_SLOT_INFO_T; -+ -+typedef struct vchiq_service_struct { -+ VCHIQ_SERVICE_BASE_T base; -+ VCHIQ_SERVICE_HANDLE_T handle; -+ unsigned int ref_count; -+ int srvstate; -+ VCHIQ_USERDATA_TERM_T userdata_term; -+ unsigned int localport; -+ unsigned int remoteport; -+ int public_fourcc; -+ int client_id; -+ char auto_close; -+ char sync; -+ char closing; -+ char trace; -+ atomic_t poll_flags; -+ short version; -+ short version_min; -+ short peer_version; -+ -+ VCHIQ_STATE_T *state; -+ VCHIQ_INSTANCE_T instance; -+ -+ int service_use_count; -+ -+ VCHIQ_BULK_QUEUE_T bulk_tx; -+ VCHIQ_BULK_QUEUE_T bulk_rx; -+ -+ struct semaphore remove_event; -+ struct semaphore bulk_remove_event; -+ struct mutex bulk_mutex; -+ -+ struct service_stats_struct { -+ int quota_stalls; -+ int slot_stalls; -+ int bulk_stalls; -+ int error_count; -+ int ctrl_tx_count; -+ int ctrl_rx_count; -+ int bulk_tx_count; -+ int bulk_rx_count; -+ int bulk_aborted_count; -+ uint64_t ctrl_tx_bytes; -+ uint64_t ctrl_rx_bytes; -+ uint64_t bulk_tx_bytes; -+ uint64_t bulk_rx_bytes; -+ } stats; -+} VCHIQ_SERVICE_T; -+ -+/* The quota information is outside VCHIQ_SERVICE_T so that it can be -+ statically allocated, since for accounting reasons a service's slot -+ usage is carried over between users of the same port number. -+ */ -+typedef struct vchiq_service_quota_struct { -+ unsigned short slot_quota; -+ unsigned short slot_use_count; -+ unsigned short message_quota; -+ unsigned short message_use_count; -+ struct semaphore quota_event; -+ int previous_tx_index; -+} VCHIQ_SERVICE_QUOTA_T; -+ -+typedef struct vchiq_shared_state_struct { -+ -+ /* A non-zero value here indicates that the content is valid. */ -+ int initialised; -+ -+ /* The first and last (inclusive) slots allocated to the owner. */ -+ int slot_first; -+ int slot_last; -+ -+ /* The slot allocated to synchronous messages from the owner. */ -+ int slot_sync; -+ -+ /* Signalling this event indicates that owner's slot handler thread -+ ** should run. */ -+ REMOTE_EVENT_T trigger; -+ -+ /* Indicates the byte position within the stream where the next message -+ ** will be written. The least significant bits are an index into the -+ ** slot. The next bits are the index of the slot in slot_queue. */ -+ int tx_pos; -+ -+ /* This event should be signalled when a slot is recycled. */ -+ REMOTE_EVENT_T recycle; -+ -+ /* The slot_queue index where the next recycled slot will be written. */ -+ int slot_queue_recycle; -+ -+ /* This event should be signalled when a synchronous message is sent. */ -+ REMOTE_EVENT_T sync_trigger; -+ -+ /* This event should be signalled when a synchronous message has been -+ ** released. */ -+ REMOTE_EVENT_T sync_release; -+ -+ /* A circular buffer of slot indexes. */ -+ int slot_queue[VCHIQ_MAX_SLOTS_PER_SIDE]; -+ -+ /* Debugging state */ -+ int debug[DEBUG_MAX]; -+} VCHIQ_SHARED_STATE_T; -+ -+typedef struct vchiq_slot_zero_struct { -+ int magic; -+ short version; -+ short version_min; -+ int slot_zero_size; -+ int slot_size; -+ int max_slots; -+ int max_slots_per_side; -+ int platform_data[2]; -+ VCHIQ_SHARED_STATE_T master; -+ VCHIQ_SHARED_STATE_T slave; -+ VCHIQ_SLOT_INFO_T slots[VCHIQ_MAX_SLOTS]; -+} VCHIQ_SLOT_ZERO_T; -+ -+struct vchiq_state_struct { -+ int id; -+ int initialised; -+ VCHIQ_CONNSTATE_T conn_state; -+ int is_master; -+ short version_common; -+ -+ VCHIQ_SHARED_STATE_T *local; -+ VCHIQ_SHARED_STATE_T *remote; -+ VCHIQ_SLOT_T *slot_data; -+ -+ unsigned short default_slot_quota; -+ unsigned short default_message_quota; -+ -+ /* Event indicating connect message received */ -+ struct semaphore connect; -+ -+ /* Mutex protecting services */ -+ struct mutex mutex; -+ VCHIQ_INSTANCE_T *instance; -+ -+ /* Processes incoming messages */ -+ struct task_struct *slot_handler_thread; -+ -+ /* Processes recycled slots */ -+ struct task_struct *recycle_thread; -+ -+ /* Processes synchronous messages */ -+ struct task_struct *sync_thread; -+ -+ /* Local implementation of the trigger remote event */ -+ struct semaphore trigger_event; -+ -+ /* Local implementation of the recycle remote event */ -+ struct semaphore recycle_event; -+ -+ /* Local implementation of the sync trigger remote event */ -+ struct semaphore sync_trigger_event; -+ -+ /* Local implementation of the sync release remote event */ -+ struct semaphore sync_release_event; -+ -+ char *tx_data; -+ char *rx_data; -+ VCHIQ_SLOT_INFO_T *rx_info; -+ -+ struct mutex slot_mutex; -+ -+ struct mutex recycle_mutex; -+ -+ struct mutex sync_mutex; -+ -+ struct mutex bulk_transfer_mutex; -+ -+ /* Indicates the byte position within the stream from where the next -+ ** message will be read. The least significant bits are an index into -+ ** the slot.The next bits are the index of the slot in -+ ** remote->slot_queue. */ -+ int rx_pos; -+ -+ /* A cached copy of local->tx_pos. Only write to local->tx_pos, and read -+ from remote->tx_pos. */ -+ int local_tx_pos; -+ -+ /* The slot_queue index of the slot to become available next. */ -+ int slot_queue_available; -+ -+ /* A flag to indicate if any poll has been requested */ -+ int poll_needed; -+ -+ /* Ths index of the previous slot used for data messages. */ -+ int previous_data_index; -+ -+ /* The number of slots occupied by data messages. */ -+ unsigned short data_use_count; -+ -+ /* The maximum number of slots to be occupied by data messages. */ -+ unsigned short data_quota; -+ -+ /* An array of bit sets indicating which services must be polled. */ -+ atomic_t poll_services[BITSET_SIZE(VCHIQ_MAX_SERVICES)]; -+ -+ /* The number of the first unused service */ -+ int unused_service; -+ -+ /* Signalled when a free slot becomes available. */ -+ struct semaphore slot_available_event; -+ -+ struct semaphore slot_remove_event; -+ -+ /* Signalled when a free data slot becomes available. */ -+ struct semaphore data_quota_event; -+ -+ /* Incremented when there are bulk transfers which cannot be processed -+ * whilst paused and must be processed on resume */ -+ int deferred_bulks; -+ -+ struct state_stats_struct { -+ int slot_stalls; -+ int data_stalls; -+ int ctrl_tx_count; -+ int ctrl_rx_count; -+ int error_count; -+ } stats; -+ -+ VCHIQ_SERVICE_T * services[VCHIQ_MAX_SERVICES]; -+ VCHIQ_SERVICE_QUOTA_T service_quotas[VCHIQ_MAX_SERVICES]; -+ VCHIQ_SLOT_INFO_T slot_info[VCHIQ_MAX_SLOTS]; -+ -+ VCHIQ_PLATFORM_STATE_T platform_state; -+}; -+ -+struct bulk_waiter { -+ VCHIQ_BULK_T *bulk; -+ struct semaphore event; -+ int actual; -+}; -+ -+extern spinlock_t bulk_waiter_spinlock; -+ -+extern int vchiq_core_log_level; -+extern int vchiq_core_msg_log_level; -+extern int vchiq_sync_log_level; -+ -+extern VCHIQ_STATE_T *vchiq_states[VCHIQ_MAX_STATES]; -+ -+extern const char * -+get_conn_state_name(VCHIQ_CONNSTATE_T conn_state); -+ -+extern VCHIQ_SLOT_ZERO_T * -+vchiq_init_slots(void *mem_base, int mem_size); -+ -+extern VCHIQ_STATUS_T -+vchiq_init_state(VCHIQ_STATE_T *state, VCHIQ_SLOT_ZERO_T *slot_zero, -+ int is_master); -+ -+extern VCHIQ_STATUS_T -+vchiq_connect_internal(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance); -+ -+extern VCHIQ_SERVICE_T * -+vchiq_add_service_internal(VCHIQ_STATE_T *state, -+ const VCHIQ_SERVICE_PARAMS_T *params, int srvstate, -+ VCHIQ_INSTANCE_T instance, VCHIQ_USERDATA_TERM_T userdata_term); -+ -+extern VCHIQ_STATUS_T -+vchiq_open_service_internal(VCHIQ_SERVICE_T *service, int client_id); -+ -+extern VCHIQ_STATUS_T -+vchiq_close_service_internal(VCHIQ_SERVICE_T *service, int close_recvd); -+ -+extern void -+vchiq_terminate_service_internal(VCHIQ_SERVICE_T *service); -+ -+extern void -+vchiq_free_service_internal(VCHIQ_SERVICE_T *service); -+ -+extern VCHIQ_STATUS_T -+vchiq_shutdown_internal(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance); -+ -+extern VCHIQ_STATUS_T -+vchiq_pause_internal(VCHIQ_STATE_T *state); -+ -+extern VCHIQ_STATUS_T -+vchiq_resume_internal(VCHIQ_STATE_T *state); -+ -+extern void -+remote_event_pollall(VCHIQ_STATE_T *state); -+ -+extern VCHIQ_STATUS_T -+vchiq_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle, -+ VCHI_MEM_HANDLE_T memhandle, void *offset, int size, void *userdata, -+ VCHIQ_BULK_MODE_T mode, VCHIQ_BULK_DIR_T dir); -+ -+extern void -+vchiq_dump_state(void *dump_context, VCHIQ_STATE_T *state); -+ -+extern void -+vchiq_dump_service_state(void *dump_context, VCHIQ_SERVICE_T *service); -+ -+extern void -+vchiq_loud_error_header(void); -+ -+extern void -+vchiq_loud_error_footer(void); -+ -+extern void -+request_poll(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, int poll_type); -+ -+static inline VCHIQ_SERVICE_T * -+handle_to_service(VCHIQ_SERVICE_HANDLE_T handle) -+{ -+ VCHIQ_STATE_T *state = vchiq_states[(handle / VCHIQ_MAX_SERVICES) & -+ (VCHIQ_MAX_STATES - 1)]; -+ if (!state) -+ return NULL; -+ -+ return state->services[handle & (VCHIQ_MAX_SERVICES - 1)]; -+} -+ -+extern VCHIQ_SERVICE_T * -+find_service_by_handle(VCHIQ_SERVICE_HANDLE_T handle); -+ -+extern VCHIQ_SERVICE_T * -+find_service_by_port(VCHIQ_STATE_T *state, int localport); -+ -+extern VCHIQ_SERVICE_T * -+find_service_for_instance(VCHIQ_INSTANCE_T instance, -+ VCHIQ_SERVICE_HANDLE_T handle); -+ -+extern VCHIQ_SERVICE_T * -+find_closed_service_for_instance(VCHIQ_INSTANCE_T instance, -+ VCHIQ_SERVICE_HANDLE_T handle); -+ -+extern VCHIQ_SERVICE_T * -+next_service_by_instance(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance, -+ int *pidx); -+ -+extern void -+lock_service(VCHIQ_SERVICE_T *service); -+ -+extern void -+unlock_service(VCHIQ_SERVICE_T *service); -+ -+/* The following functions are called from vchiq_core, and external -+** implementations must be provided. */ -+ -+extern VCHIQ_STATUS_T -+vchiq_prepare_bulk_data(VCHIQ_BULK_T *bulk, -+ VCHI_MEM_HANDLE_T memhandle, void *offset, int size, int dir); -+ -+extern void -+vchiq_transfer_bulk(VCHIQ_BULK_T *bulk); -+ -+extern void -+vchiq_complete_bulk(VCHIQ_BULK_T *bulk); -+ -+extern VCHIQ_STATUS_T -+vchiq_copy_from_user(void *dst, const void *src, int size); -+ -+extern void -+remote_event_signal(REMOTE_EVENT_T *event); -+ -+void -+vchiq_platform_check_suspend(VCHIQ_STATE_T *state); -+ -+extern void -+vchiq_platform_paused(VCHIQ_STATE_T *state); -+ -+extern VCHIQ_STATUS_T -+vchiq_platform_resume(VCHIQ_STATE_T *state); -+ -+extern void -+vchiq_platform_resumed(VCHIQ_STATE_T *state); -+ -+extern void -+vchiq_dump(void *dump_context, const char *str, int len); -+ -+extern void -+vchiq_dump_platform_state(void *dump_context); -+ -+extern void -+vchiq_dump_platform_instances(void *dump_context); -+ -+extern void -+vchiq_dump_platform_service_state(void *dump_context, -+ VCHIQ_SERVICE_T *service); -+ -+extern VCHIQ_STATUS_T -+vchiq_use_service_internal(VCHIQ_SERVICE_T *service); -+ -+extern VCHIQ_STATUS_T -+vchiq_release_service_internal(VCHIQ_SERVICE_T *service); -+ -+extern void -+vchiq_on_remote_use(VCHIQ_STATE_T *state); -+ -+extern void -+vchiq_on_remote_release(VCHIQ_STATE_T *state); -+ -+extern VCHIQ_STATUS_T -+vchiq_platform_init_state(VCHIQ_STATE_T *state); -+ -+extern VCHIQ_STATUS_T -+vchiq_check_service(VCHIQ_SERVICE_T *service); -+ -+extern void -+vchiq_on_remote_use_active(VCHIQ_STATE_T *state); -+ -+extern VCHIQ_STATUS_T -+vchiq_send_remote_use(VCHIQ_STATE_T *state); -+ -+extern VCHIQ_STATUS_T -+vchiq_send_remote_release(VCHIQ_STATE_T *state); -+ -+extern VCHIQ_STATUS_T -+vchiq_send_remote_use_active(VCHIQ_STATE_T *state); -+ -+extern void -+vchiq_platform_conn_state_changed(VCHIQ_STATE_T *state, -+ VCHIQ_CONNSTATE_T oldstate, VCHIQ_CONNSTATE_T newstate); -+ -+extern void -+vchiq_platform_handle_timeout(VCHIQ_STATE_T *state); -+ -+extern void -+vchiq_set_conn_state(VCHIQ_STATE_T *state, VCHIQ_CONNSTATE_T newstate); -+ -+ -+extern void -+vchiq_log_dump_mem(const char *label, uint32_t addr, const void *voidMem, -+ size_t numBytes); -+ -+#endif -diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.c ---- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.c 2015-11-29 09:42:38.075221210 +0100 -@@ -0,0 +1,383 @@ -+/** -+ * Copyright (c) 2014 Raspberry Pi (Trading) Ltd. All rights reserved. -+ * Copyright (c) 2010-2012 Broadcom. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+#include -+#include "vchiq_core.h" -+#include "vchiq_arm.h" -+#include "vchiq_debugfs.h" -+ -+#ifdef CONFIG_DEBUG_FS -+ -+/**************************************************************************** -+* -+* log category entries -+* -+***************************************************************************/ -+#define DEBUGFS_WRITE_BUF_SIZE 256 -+ -+#define VCHIQ_LOG_ERROR_STR "error" -+#define VCHIQ_LOG_WARNING_STR "warning" -+#define VCHIQ_LOG_INFO_STR "info" -+#define VCHIQ_LOG_TRACE_STR "trace" -+ -+ -+/* Top-level debug info */ -+struct vchiq_debugfs_info { -+ /* Global 'vchiq' debugfs entry used by all instances */ -+ struct dentry *vchiq_cfg_dir; -+ -+ /* one entry per client process */ -+ struct dentry *clients; -+ -+ /* log categories */ -+ struct dentry *log_categories; -+}; -+ -+static struct vchiq_debugfs_info debugfs_info; -+ -+/* Log category debugfs entries */ -+struct vchiq_debugfs_log_entry { -+ const char *name; -+ int *plevel; -+ struct dentry *dir; -+}; -+ -+static struct vchiq_debugfs_log_entry vchiq_debugfs_log_entries[] = { -+ { "core", &vchiq_core_log_level }, -+ { "msg", &vchiq_core_msg_log_level }, -+ { "sync", &vchiq_sync_log_level }, -+ { "susp", &vchiq_susp_log_level }, -+ { "arm", &vchiq_arm_log_level }, -+}; -+static int n_log_entries = -+ sizeof(vchiq_debugfs_log_entries)/sizeof(vchiq_debugfs_log_entries[0]); -+ -+ -+static struct dentry *vchiq_clients_top(void); -+static struct dentry *vchiq_debugfs_top(void); -+ -+static int debugfs_log_show(struct seq_file *f, void *offset) -+{ -+ int *levp = f->private; -+ char *log_value = NULL; -+ -+ switch (*levp) { -+ case VCHIQ_LOG_ERROR: -+ log_value = VCHIQ_LOG_ERROR_STR; -+ break; -+ case VCHIQ_LOG_WARNING: -+ log_value = VCHIQ_LOG_WARNING_STR; -+ break; -+ case VCHIQ_LOG_INFO: -+ log_value = VCHIQ_LOG_INFO_STR; -+ break; -+ case VCHIQ_LOG_TRACE: -+ log_value = VCHIQ_LOG_TRACE_STR; -+ break; -+ default: -+ break; -+ } -+ -+ seq_printf(f, "%s\n", log_value ? log_value : "(null)"); -+ -+ return 0; -+} -+ -+static int debugfs_log_open(struct inode *inode, struct file *file) -+{ -+ return single_open(file, debugfs_log_show, inode->i_private); -+} -+ -+static int debugfs_log_write(struct file *file, -+ const char __user *buffer, -+ size_t count, loff_t *ppos) -+{ -+ struct seq_file *f = (struct seq_file *)file->private_data; -+ int *levp = f->private; -+ char kbuf[DEBUGFS_WRITE_BUF_SIZE + 1]; -+ -+ memset(kbuf, 0, DEBUGFS_WRITE_BUF_SIZE + 1); -+ if (count >= DEBUGFS_WRITE_BUF_SIZE) -+ count = DEBUGFS_WRITE_BUF_SIZE; -+ -+ if (copy_from_user(kbuf, buffer, count) != 0) -+ return -EFAULT; -+ kbuf[count - 1] = 0; -+ -+ if (strncmp("error", kbuf, strlen("error")) == 0) -+ *levp = VCHIQ_LOG_ERROR; -+ else if (strncmp("warning", kbuf, strlen("warning")) == 0) -+ *levp = VCHIQ_LOG_WARNING; -+ else if (strncmp("info", kbuf, strlen("info")) == 0) -+ *levp = VCHIQ_LOG_INFO; -+ else if (strncmp("trace", kbuf, strlen("trace")) == 0) -+ *levp = VCHIQ_LOG_TRACE; -+ else -+ *levp = VCHIQ_LOG_DEFAULT; -+ -+ *ppos += count; -+ -+ return count; -+} -+ -+static const struct file_operations debugfs_log_fops = { -+ .owner = THIS_MODULE, -+ .open = debugfs_log_open, -+ .write = debugfs_log_write, -+ .read = seq_read, -+ .llseek = seq_lseek, -+ .release = single_release, -+}; -+ -+/* create an entry under /vchiq/log for each log category */ -+static int vchiq_debugfs_create_log_entries(struct dentry *top) -+{ -+ struct dentry *dir; -+ size_t i; -+ int ret = 0; -+ dir = debugfs_create_dir("log", vchiq_debugfs_top()); -+ if (!dir) -+ return -ENOMEM; -+ debugfs_info.log_categories = dir; -+ -+ for (i = 0; i < n_log_entries; i++) { -+ void *levp = (void *)vchiq_debugfs_log_entries[i].plevel; -+ dir = debugfs_create_file(vchiq_debugfs_log_entries[i].name, -+ 0644, -+ debugfs_info.log_categories, -+ levp, -+ &debugfs_log_fops); -+ if (!dir) { -+ ret = -ENOMEM; -+ break; -+ } -+ -+ vchiq_debugfs_log_entries[i].dir = dir; -+ } -+ return ret; -+} -+ -+static int debugfs_usecount_show(struct seq_file *f, void *offset) -+{ -+ VCHIQ_INSTANCE_T instance = f->private; -+ int use_count; -+ -+ use_count = vchiq_instance_get_use_count(instance); -+ seq_printf(f, "%d\n", use_count); -+ -+ return 0; -+} -+ -+static int debugfs_usecount_open(struct inode *inode, struct file *file) -+{ -+ return single_open(file, debugfs_usecount_show, inode->i_private); -+} -+ -+static const struct file_operations debugfs_usecount_fops = { -+ .owner = THIS_MODULE, -+ .open = debugfs_usecount_open, -+ .read = seq_read, -+ .llseek = seq_lseek, -+ .release = single_release, -+}; -+ -+static int debugfs_trace_show(struct seq_file *f, void *offset) -+{ -+ VCHIQ_INSTANCE_T instance = f->private; -+ int trace; -+ -+ trace = vchiq_instance_get_trace(instance); -+ seq_printf(f, "%s\n", trace ? "Y" : "N"); -+ -+ return 0; -+} -+ -+static int debugfs_trace_open(struct inode *inode, struct file *file) -+{ -+ return single_open(file, debugfs_trace_show, inode->i_private); -+} -+ -+static int debugfs_trace_write(struct file *file, -+ const char __user *buffer, -+ size_t count, loff_t *ppos) -+{ -+ struct seq_file *f = (struct seq_file *)file->private_data; -+ VCHIQ_INSTANCE_T instance = f->private; -+ char firstchar; -+ -+ if (copy_from_user(&firstchar, buffer, 1) != 0) -+ return -EFAULT; -+ -+ switch (firstchar) { -+ case 'Y': -+ case 'y': -+ case '1': -+ vchiq_instance_set_trace(instance, 1); -+ break; -+ case 'N': -+ case 'n': -+ case '0': -+ vchiq_instance_set_trace(instance, 0); -+ break; -+ default: -+ break; -+ } -+ -+ *ppos += count; -+ -+ return count; -+} -+ -+static const struct file_operations debugfs_trace_fops = { -+ .owner = THIS_MODULE, -+ .open = debugfs_trace_open, -+ .write = debugfs_trace_write, -+ .read = seq_read, -+ .llseek = seq_lseek, -+ .release = single_release, -+}; -+ -+/* add an instance (process) to the debugfs entries */ -+int vchiq_debugfs_add_instance(VCHIQ_INSTANCE_T instance) -+{ -+ char pidstr[16]; -+ struct dentry *top, *use_count, *trace; -+ struct dentry *clients = vchiq_clients_top(); -+ -+ snprintf(pidstr, sizeof(pidstr), "%d", -+ vchiq_instance_get_pid(instance)); -+ -+ top = debugfs_create_dir(pidstr, clients); -+ if (!top) -+ goto fail_top; -+ -+ use_count = debugfs_create_file("use_count", -+ 0444, top, -+ instance, -+ &debugfs_usecount_fops); -+ if (!use_count) -+ goto fail_use_count; -+ -+ trace = debugfs_create_file("trace", -+ 0644, top, -+ instance, -+ &debugfs_trace_fops); -+ if (!trace) -+ goto fail_trace; -+ -+ vchiq_instance_get_debugfs_node(instance)->dentry = top; -+ -+ return 0; -+ -+fail_trace: -+ debugfs_remove(use_count); -+fail_use_count: -+ debugfs_remove(top); -+fail_top: -+ return -ENOMEM; -+} -+ -+void vchiq_debugfs_remove_instance(VCHIQ_INSTANCE_T instance) -+{ -+ VCHIQ_DEBUGFS_NODE_T *node = vchiq_instance_get_debugfs_node(instance); -+ debugfs_remove_recursive(node->dentry); -+} -+ -+ -+int vchiq_debugfs_init(void) -+{ -+ BUG_ON(debugfs_info.vchiq_cfg_dir != NULL); -+ -+ debugfs_info.vchiq_cfg_dir = debugfs_create_dir("vchiq", NULL); -+ if (debugfs_info.vchiq_cfg_dir == NULL) -+ goto fail; -+ -+ debugfs_info.clients = debugfs_create_dir("clients", -+ vchiq_debugfs_top()); -+ if (!debugfs_info.clients) -+ goto fail; -+ -+ if (vchiq_debugfs_create_log_entries(vchiq_debugfs_top()) != 0) -+ goto fail; -+ -+ return 0; -+ -+fail: -+ vchiq_debugfs_deinit(); -+ vchiq_log_error(vchiq_arm_log_level, -+ "%s: failed to create debugfs directory", -+ __func__); -+ -+ return -ENOMEM; -+} -+ -+/* remove all the debugfs entries */ -+void vchiq_debugfs_deinit(void) -+{ -+ debugfs_remove_recursive(vchiq_debugfs_top()); -+} -+ -+static struct dentry *vchiq_clients_top(void) -+{ -+ return debugfs_info.clients; -+} -+ -+static struct dentry *vchiq_debugfs_top(void) -+{ -+ BUG_ON(debugfs_info.vchiq_cfg_dir == NULL); -+ return debugfs_info.vchiq_cfg_dir; -+} -+ -+#else /* CONFIG_DEBUG_FS */ -+ -+int vchiq_debugfs_init(void) -+{ -+ return 0; -+} -+ -+void vchiq_debugfs_deinit(void) -+{ -+} -+ -+int vchiq_debugfs_add_instance(VCHIQ_INSTANCE_T instance) -+{ -+ return 0; -+} -+ -+void vchiq_debugfs_remove_instance(VCHIQ_INSTANCE_T instance) -+{ -+} -+ -+#endif /* CONFIG_DEBUG_FS */ -diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.h ---- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.h 2015-11-29 09:42:38.075221210 +0100 -@@ -0,0 +1,52 @@ -+/** -+ * Copyright (c) 2014 Raspberry Pi (Trading) Ltd. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef VCHIQ_DEBUGFS_H -+#define VCHIQ_DEBUGFS_H -+ -+#include "vchiq_core.h" -+ -+typedef struct vchiq_debugfs_node_struct -+{ -+ struct dentry *dentry; -+} VCHIQ_DEBUGFS_NODE_T; -+ -+int vchiq_debugfs_init(void); -+ -+void vchiq_debugfs_deinit(void); -+ -+int vchiq_debugfs_add_instance(VCHIQ_INSTANCE_T instance); -+ -+void vchiq_debugfs_remove_instance(VCHIQ_INSTANCE_T instance); -+ -+#endif /* VCHIQ_DEBUGFS_H */ -diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_genversion linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_genversion ---- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_genversion 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_genversion 2015-11-29 09:42:38.075221210 +0100 -@@ -0,0 +1,87 @@ -+#!/usr/bin/perl -w -+ -+use strict; -+ -+# -+# Generate a version from available information -+# -+ -+my $prefix = shift @ARGV; -+my $root = shift @ARGV; -+ -+ -+if ( not defined $root ) { -+ die "usage: $0 prefix root-dir\n"; -+} -+ -+if ( ! -d $root ) { -+ die "root directory $root not found\n"; -+} -+ -+my $version = "unknown"; -+my $tainted = ""; -+ -+if ( -d "$root/.git" ) { -+ # attempt to work out git version. only do so -+ # on a linux build host, as cygwin builds are -+ # already slow enough -+ -+ if ( -f "/usr/bin/git" || -f "/usr/local/bin/git" ) { -+ if (not open(F, "git --git-dir $root/.git rev-parse --verify HEAD|")) { -+ $version = "no git version"; -+ } -+ else { -+ $version = ; -+ $version =~ s/[ \r\n]*$//; # chomp may not be enough (cygwin). -+ $version =~ s/^[ \r\n]*//; # chomp may not be enough (cygwin). -+ } -+ -+ if (open(G, "git --git-dir $root/.git status --porcelain|")) { -+ $tainted = ; -+ $tainted =~ s/[ \r\n]*$//; # chomp may not be enough (cygwin). -+ $tainted =~ s/^[ \r\n]*//; # chomp may not be enough (cygwin). -+ if (length $tainted) { -+ $version = join ' ', $version, "(tainted)"; -+ } -+ else { -+ $version = join ' ', $version, "(clean)"; -+ } -+ } -+ } -+} -+ -+my $hostname = `hostname`; -+$hostname =~ s/[ \r\n]*$//; # chomp may not be enough (cygwin). -+$hostname =~ s/^[ \r\n]*//; # chomp may not be enough (cygwin). -+ -+ -+print STDERR "Version $version\n"; -+print < -+ -+VC_DEBUG_DECLARE_STRING_VAR( ${prefix}_build_hostname, "$hostname" ); -+VC_DEBUG_DECLARE_STRING_VAR( ${prefix}_build_version, "$version" ); -+VC_DEBUG_DECLARE_STRING_VAR( ${prefix}_build_time, __TIME__ ); -+VC_DEBUG_DECLARE_STRING_VAR( ${prefix}_build_date, __DATE__ ); -+ -+const char *vchiq_get_build_hostname( void ) -+{ -+ return vchiq_build_hostname; -+} -+ -+const char *vchiq_get_build_version( void ) -+{ -+ return vchiq_build_version; -+} -+ -+const char *vchiq_get_build_date( void ) -+{ -+ return vchiq_build_date; -+} -+ -+const char *vchiq_get_build_time( void ) -+{ -+ return vchiq_build_time; -+} -+EOF -diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq.h ---- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq.h 2015-11-29 09:42:38.059222273 +0100 -@@ -0,0 +1,40 @@ -+/** -+ * Copyright (c) 2010-2012 Broadcom. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef VCHIQ_VCHIQ_H -+#define VCHIQ_VCHIQ_H -+ -+#include "vchiq_if.h" -+#include "vchiq_util.h" -+ -+#endif -diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h ---- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h 2015-11-29 09:42:38.075221210 +0100 -@@ -0,0 +1,189 @@ -+/** -+ * Copyright (c) 2010-2012 Broadcom. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef VCHIQ_IF_H -+#define VCHIQ_IF_H -+ -+#include "interface/vchi/vchi_mh.h" -+ -+#define VCHIQ_SERVICE_HANDLE_INVALID 0 -+ -+#define VCHIQ_SLOT_SIZE 4096 -+#define VCHIQ_MAX_MSG_SIZE (VCHIQ_SLOT_SIZE - sizeof(VCHIQ_HEADER_T)) -+#define VCHIQ_CHANNEL_SIZE VCHIQ_MAX_MSG_SIZE /* For backwards compatibility */ -+ -+#define VCHIQ_MAKE_FOURCC(x0, x1, x2, x3) \ -+ (((x0) << 24) | ((x1) << 16) | ((x2) << 8) | (x3)) -+#define VCHIQ_GET_SERVICE_USERDATA(service) vchiq_get_service_userdata(service) -+#define VCHIQ_GET_SERVICE_FOURCC(service) vchiq_get_service_fourcc(service) -+ -+typedef enum { -+ VCHIQ_SERVICE_OPENED, /* service, -, - */ -+ VCHIQ_SERVICE_CLOSED, /* service, -, - */ -+ VCHIQ_MESSAGE_AVAILABLE, /* service, header, - */ -+ VCHIQ_BULK_TRANSMIT_DONE, /* service, -, bulk_userdata */ -+ VCHIQ_BULK_RECEIVE_DONE, /* service, -, bulk_userdata */ -+ VCHIQ_BULK_TRANSMIT_ABORTED, /* service, -, bulk_userdata */ -+ VCHIQ_BULK_RECEIVE_ABORTED /* service, -, bulk_userdata */ -+} VCHIQ_REASON_T; -+ -+typedef enum { -+ VCHIQ_ERROR = -1, -+ VCHIQ_SUCCESS = 0, -+ VCHIQ_RETRY = 1 -+} VCHIQ_STATUS_T; -+ -+typedef enum { -+ VCHIQ_BULK_MODE_CALLBACK, -+ VCHIQ_BULK_MODE_BLOCKING, -+ VCHIQ_BULK_MODE_NOCALLBACK, -+ VCHIQ_BULK_MODE_WAITING /* Reserved for internal use */ -+} VCHIQ_BULK_MODE_T; -+ -+typedef enum { -+ VCHIQ_SERVICE_OPTION_AUTOCLOSE, -+ VCHIQ_SERVICE_OPTION_SLOT_QUOTA, -+ VCHIQ_SERVICE_OPTION_MESSAGE_QUOTA, -+ VCHIQ_SERVICE_OPTION_SYNCHRONOUS, -+ VCHIQ_SERVICE_OPTION_TRACE -+} VCHIQ_SERVICE_OPTION_T; -+ -+typedef struct vchiq_header_struct { -+ /* The message identifier - opaque to applications. */ -+ int msgid; -+ -+ /* Size of message data. */ -+ unsigned int size; -+ -+ char data[0]; /* message */ -+} VCHIQ_HEADER_T; -+ -+typedef struct { -+ const void *data; -+ unsigned int size; -+} VCHIQ_ELEMENT_T; -+ -+typedef unsigned int VCHIQ_SERVICE_HANDLE_T; -+ -+typedef VCHIQ_STATUS_T (*VCHIQ_CALLBACK_T)(VCHIQ_REASON_T, VCHIQ_HEADER_T *, -+ VCHIQ_SERVICE_HANDLE_T, void *); -+ -+typedef struct vchiq_service_base_struct { -+ int fourcc; -+ VCHIQ_CALLBACK_T callback; -+ void *userdata; -+} VCHIQ_SERVICE_BASE_T; -+ -+typedef struct vchiq_service_params_struct { -+ int fourcc; -+ VCHIQ_CALLBACK_T callback; -+ void *userdata; -+ short version; /* Increment for non-trivial changes */ -+ short version_min; /* Update for incompatible changes */ -+} VCHIQ_SERVICE_PARAMS_T; -+ -+typedef struct vchiq_config_struct { -+ unsigned int max_msg_size; -+ unsigned int bulk_threshold; /* The message size above which it -+ is better to use a bulk transfer -+ (<= max_msg_size) */ -+ unsigned int max_outstanding_bulks; -+ unsigned int max_services; -+ short version; /* The version of VCHIQ */ -+ short version_min; /* The minimum compatible version of VCHIQ */ -+} VCHIQ_CONFIG_T; -+ -+typedef struct vchiq_instance_struct *VCHIQ_INSTANCE_T; -+typedef void (*VCHIQ_REMOTE_USE_CALLBACK_T)(void *cb_arg); -+ -+extern VCHIQ_STATUS_T vchiq_initialise(VCHIQ_INSTANCE_T *pinstance); -+extern VCHIQ_STATUS_T vchiq_shutdown(VCHIQ_INSTANCE_T instance); -+extern VCHIQ_STATUS_T vchiq_connect(VCHIQ_INSTANCE_T instance); -+extern VCHIQ_STATUS_T vchiq_add_service(VCHIQ_INSTANCE_T instance, -+ const VCHIQ_SERVICE_PARAMS_T *params, -+ VCHIQ_SERVICE_HANDLE_T *pservice); -+extern VCHIQ_STATUS_T vchiq_open_service(VCHIQ_INSTANCE_T instance, -+ const VCHIQ_SERVICE_PARAMS_T *params, -+ VCHIQ_SERVICE_HANDLE_T *pservice); -+extern VCHIQ_STATUS_T vchiq_close_service(VCHIQ_SERVICE_HANDLE_T service); -+extern VCHIQ_STATUS_T vchiq_remove_service(VCHIQ_SERVICE_HANDLE_T service); -+extern VCHIQ_STATUS_T vchiq_use_service(VCHIQ_SERVICE_HANDLE_T service); -+extern VCHIQ_STATUS_T vchiq_use_service_no_resume( -+ VCHIQ_SERVICE_HANDLE_T service); -+extern VCHIQ_STATUS_T vchiq_release_service(VCHIQ_SERVICE_HANDLE_T service); -+ -+extern VCHIQ_STATUS_T vchiq_queue_message(VCHIQ_SERVICE_HANDLE_T service, -+ const VCHIQ_ELEMENT_T *elements, unsigned int count); -+extern void vchiq_release_message(VCHIQ_SERVICE_HANDLE_T service, -+ VCHIQ_HEADER_T *header); -+extern VCHIQ_STATUS_T vchiq_queue_bulk_transmit(VCHIQ_SERVICE_HANDLE_T service, -+ const void *data, unsigned int size, void *userdata); -+extern VCHIQ_STATUS_T vchiq_queue_bulk_receive(VCHIQ_SERVICE_HANDLE_T service, -+ void *data, unsigned int size, void *userdata); -+extern VCHIQ_STATUS_T vchiq_queue_bulk_transmit_handle( -+ VCHIQ_SERVICE_HANDLE_T service, VCHI_MEM_HANDLE_T handle, -+ const void *offset, unsigned int size, void *userdata); -+extern VCHIQ_STATUS_T vchiq_queue_bulk_receive_handle( -+ VCHIQ_SERVICE_HANDLE_T service, VCHI_MEM_HANDLE_T handle, -+ void *offset, unsigned int size, void *userdata); -+extern VCHIQ_STATUS_T vchiq_bulk_transmit(VCHIQ_SERVICE_HANDLE_T service, -+ const void *data, unsigned int size, void *userdata, -+ VCHIQ_BULK_MODE_T mode); -+extern VCHIQ_STATUS_T vchiq_bulk_receive(VCHIQ_SERVICE_HANDLE_T service, -+ void *data, unsigned int size, void *userdata, -+ VCHIQ_BULK_MODE_T mode); -+extern VCHIQ_STATUS_T vchiq_bulk_transmit_handle(VCHIQ_SERVICE_HANDLE_T service, -+ VCHI_MEM_HANDLE_T handle, const void *offset, unsigned int size, -+ void *userdata, VCHIQ_BULK_MODE_T mode); -+extern VCHIQ_STATUS_T vchiq_bulk_receive_handle(VCHIQ_SERVICE_HANDLE_T service, -+ VCHI_MEM_HANDLE_T handle, void *offset, unsigned int size, -+ void *userdata, VCHIQ_BULK_MODE_T mode); -+extern int vchiq_get_client_id(VCHIQ_SERVICE_HANDLE_T service); -+extern void *vchiq_get_service_userdata(VCHIQ_SERVICE_HANDLE_T service); -+extern int vchiq_get_service_fourcc(VCHIQ_SERVICE_HANDLE_T service); -+extern VCHIQ_STATUS_T vchiq_get_config(VCHIQ_INSTANCE_T instance, -+ int config_size, VCHIQ_CONFIG_T *pconfig); -+extern VCHIQ_STATUS_T vchiq_set_service_option(VCHIQ_SERVICE_HANDLE_T service, -+ VCHIQ_SERVICE_OPTION_T option, int value); -+ -+extern VCHIQ_STATUS_T vchiq_remote_use(VCHIQ_INSTANCE_T instance, -+ VCHIQ_REMOTE_USE_CALLBACK_T callback, void *cb_arg); -+extern VCHIQ_STATUS_T vchiq_remote_release(VCHIQ_INSTANCE_T instance); -+ -+extern VCHIQ_STATUS_T vchiq_dump_phys_mem(VCHIQ_SERVICE_HANDLE_T service, -+ void *ptr, size_t num_bytes); -+ -+extern VCHIQ_STATUS_T vchiq_get_peer_version(VCHIQ_SERVICE_HANDLE_T handle, -+ short *peer_version); -+ -+#endif /* VCHIQ_IF_H */ -diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h ---- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h 2015-11-29 09:42:38.075221210 +0100 -@@ -0,0 +1,131 @@ -+/** -+ * Copyright (c) 2010-2012 Broadcom. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef VCHIQ_IOCTLS_H -+#define VCHIQ_IOCTLS_H -+ -+#include -+#include "vchiq_if.h" -+ -+#define VCHIQ_IOC_MAGIC 0xc4 -+#define VCHIQ_INVALID_HANDLE (~0) -+ -+typedef struct { -+ VCHIQ_SERVICE_PARAMS_T params; -+ int is_open; -+ int is_vchi; -+ unsigned int handle; /* OUT */ -+} VCHIQ_CREATE_SERVICE_T; -+ -+typedef struct { -+ unsigned int handle; -+ unsigned int count; -+ const VCHIQ_ELEMENT_T *elements; -+} VCHIQ_QUEUE_MESSAGE_T; -+ -+typedef struct { -+ unsigned int handle; -+ void *data; -+ unsigned int size; -+ void *userdata; -+ VCHIQ_BULK_MODE_T mode; -+} VCHIQ_QUEUE_BULK_TRANSFER_T; -+ -+typedef struct { -+ VCHIQ_REASON_T reason; -+ VCHIQ_HEADER_T *header; -+ void *service_userdata; -+ void *bulk_userdata; -+} VCHIQ_COMPLETION_DATA_T; -+ -+typedef struct { -+ unsigned int count; -+ VCHIQ_COMPLETION_DATA_T *buf; -+ unsigned int msgbufsize; -+ unsigned int msgbufcount; /* IN/OUT */ -+ void **msgbufs; -+} VCHIQ_AWAIT_COMPLETION_T; -+ -+typedef struct { -+ unsigned int handle; -+ int blocking; -+ unsigned int bufsize; -+ void *buf; -+} VCHIQ_DEQUEUE_MESSAGE_T; -+ -+typedef struct { -+ unsigned int config_size; -+ VCHIQ_CONFIG_T *pconfig; -+} VCHIQ_GET_CONFIG_T; -+ -+typedef struct { -+ unsigned int handle; -+ VCHIQ_SERVICE_OPTION_T option; -+ int value; -+} VCHIQ_SET_SERVICE_OPTION_T; -+ -+typedef struct { -+ void *virt_addr; -+ size_t num_bytes; -+} VCHIQ_DUMP_MEM_T; -+ -+#define VCHIQ_IOC_CONNECT _IO(VCHIQ_IOC_MAGIC, 0) -+#define VCHIQ_IOC_SHUTDOWN _IO(VCHIQ_IOC_MAGIC, 1) -+#define VCHIQ_IOC_CREATE_SERVICE \ -+ _IOWR(VCHIQ_IOC_MAGIC, 2, VCHIQ_CREATE_SERVICE_T) -+#define VCHIQ_IOC_REMOVE_SERVICE _IO(VCHIQ_IOC_MAGIC, 3) -+#define VCHIQ_IOC_QUEUE_MESSAGE \ -+ _IOW(VCHIQ_IOC_MAGIC, 4, VCHIQ_QUEUE_MESSAGE_T) -+#define VCHIQ_IOC_QUEUE_BULK_TRANSMIT \ -+ _IOWR(VCHIQ_IOC_MAGIC, 5, VCHIQ_QUEUE_BULK_TRANSFER_T) -+#define VCHIQ_IOC_QUEUE_BULK_RECEIVE \ -+ _IOWR(VCHIQ_IOC_MAGIC, 6, VCHIQ_QUEUE_BULK_TRANSFER_T) -+#define VCHIQ_IOC_AWAIT_COMPLETION \ -+ _IOWR(VCHIQ_IOC_MAGIC, 7, VCHIQ_AWAIT_COMPLETION_T) -+#define VCHIQ_IOC_DEQUEUE_MESSAGE \ -+ _IOWR(VCHIQ_IOC_MAGIC, 8, VCHIQ_DEQUEUE_MESSAGE_T) -+#define VCHIQ_IOC_GET_CLIENT_ID _IO(VCHIQ_IOC_MAGIC, 9) -+#define VCHIQ_IOC_GET_CONFIG \ -+ _IOWR(VCHIQ_IOC_MAGIC, 10, VCHIQ_GET_CONFIG_T) -+#define VCHIQ_IOC_CLOSE_SERVICE _IO(VCHIQ_IOC_MAGIC, 11) -+#define VCHIQ_IOC_USE_SERVICE _IO(VCHIQ_IOC_MAGIC, 12) -+#define VCHIQ_IOC_RELEASE_SERVICE _IO(VCHIQ_IOC_MAGIC, 13) -+#define VCHIQ_IOC_SET_SERVICE_OPTION \ -+ _IOW(VCHIQ_IOC_MAGIC, 14, VCHIQ_SET_SERVICE_OPTION_T) -+#define VCHIQ_IOC_DUMP_PHYS_MEM \ -+ _IOW(VCHIQ_IOC_MAGIC, 15, VCHIQ_DUMP_MEM_T) -+#define VCHIQ_IOC_LIB_VERSION _IO(VCHIQ_IOC_MAGIC, 16) -+#define VCHIQ_IOC_CLOSE_DELIVERED _IO(VCHIQ_IOC_MAGIC, 17) -+#define VCHIQ_IOC_MAX 17 -+ -+#endif -diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c ---- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c 2015-11-29 09:42:38.075221210 +0100 -@@ -0,0 +1,458 @@ -+/** -+ * Copyright (c) 2010-2012 Broadcom. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/* ---- Include Files ---------------------------------------------------- */ -+ -+#include -+#include -+#include -+ -+#include "vchiq_core.h" -+#include "vchiq_arm.h" -+#include "vchiq_killable.h" -+ -+/* ---- Public Variables ------------------------------------------------- */ -+ -+/* ---- Private Constants and Types -------------------------------------- */ -+ -+struct bulk_waiter_node { -+ struct bulk_waiter bulk_waiter; -+ int pid; -+ struct list_head list; -+}; -+ -+struct vchiq_instance_struct { -+ VCHIQ_STATE_T *state; -+ -+ int connected; -+ -+ struct list_head bulk_waiter_list; -+ struct mutex bulk_waiter_list_mutex; -+}; -+ -+static VCHIQ_STATUS_T -+vchiq_blocking_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle, void *data, -+ unsigned int size, VCHIQ_BULK_DIR_T dir); -+ -+/**************************************************************************** -+* -+* vchiq_initialise -+* -+***************************************************************************/ -+#define VCHIQ_INIT_RETRIES 10 -+VCHIQ_STATUS_T vchiq_initialise(VCHIQ_INSTANCE_T *instanceOut) -+{ -+ VCHIQ_STATUS_T status = VCHIQ_ERROR; -+ VCHIQ_STATE_T *state; -+ VCHIQ_INSTANCE_T instance = NULL; -+ int i; -+ -+ vchiq_log_trace(vchiq_core_log_level, "%s called", __func__); -+ -+ /* VideoCore may not be ready due to boot up timing. -+ It may never be ready if kernel and firmware are mismatched, so don't block forever. */ -+ for (i=0; i0) { -+ vchiq_log_warning(vchiq_core_log_level, -+ "%s: videocore initialized after %d retries\n", __func__, i); -+ } -+ -+ instance = kzalloc(sizeof(*instance), GFP_KERNEL); -+ if (!instance) { -+ vchiq_log_error(vchiq_core_log_level, -+ "%s: error allocating vchiq instance\n", __func__); -+ goto failed; -+ } -+ -+ instance->connected = 0; -+ instance->state = state; -+ mutex_init(&instance->bulk_waiter_list_mutex); -+ INIT_LIST_HEAD(&instance->bulk_waiter_list); -+ -+ *instanceOut = instance; -+ -+ status = VCHIQ_SUCCESS; -+ -+failed: -+ vchiq_log_trace(vchiq_core_log_level, -+ "%s(%p): returning %d", __func__, instance, status); -+ -+ return status; -+} -+EXPORT_SYMBOL(vchiq_initialise); -+ -+/**************************************************************************** -+* -+* vchiq_shutdown -+* -+***************************************************************************/ -+ -+VCHIQ_STATUS_T vchiq_shutdown(VCHIQ_INSTANCE_T instance) -+{ -+ VCHIQ_STATUS_T status; -+ VCHIQ_STATE_T *state = instance->state; -+ -+ vchiq_log_trace(vchiq_core_log_level, -+ "%s(%p) called", __func__, instance); -+ -+ if (mutex_lock_interruptible(&state->mutex) != 0) -+ return VCHIQ_RETRY; -+ -+ /* Remove all services */ -+ status = vchiq_shutdown_internal(state, instance); -+ -+ mutex_unlock(&state->mutex); -+ -+ vchiq_log_trace(vchiq_core_log_level, -+ "%s(%p): returning %d", __func__, instance, status); -+ -+ if (status == VCHIQ_SUCCESS) { -+ struct list_head *pos, *next; -+ list_for_each_safe(pos, next, -+ &instance->bulk_waiter_list) { -+ struct bulk_waiter_node *waiter; -+ waiter = list_entry(pos, -+ struct bulk_waiter_node, -+ list); -+ list_del(pos); -+ vchiq_log_info(vchiq_arm_log_level, -+ "bulk_waiter - cleaned up %x " -+ "for pid %d", -+ (unsigned int)waiter, waiter->pid); -+ kfree(waiter); -+ } -+ kfree(instance); -+ } -+ -+ return status; -+} -+EXPORT_SYMBOL(vchiq_shutdown); -+ -+/**************************************************************************** -+* -+* vchiq_is_connected -+* -+***************************************************************************/ -+ -+int vchiq_is_connected(VCHIQ_INSTANCE_T instance) -+{ -+ return instance->connected; -+} -+ -+/**************************************************************************** -+* -+* vchiq_connect -+* -+***************************************************************************/ -+ -+VCHIQ_STATUS_T vchiq_connect(VCHIQ_INSTANCE_T instance) -+{ -+ VCHIQ_STATUS_T status; -+ VCHIQ_STATE_T *state = instance->state; -+ -+ vchiq_log_trace(vchiq_core_log_level, -+ "%s(%p) called", __func__, instance); -+ -+ if (mutex_lock_interruptible(&state->mutex) != 0) { -+ vchiq_log_trace(vchiq_core_log_level, -+ "%s: call to mutex_lock failed", __func__); -+ status = VCHIQ_RETRY; -+ goto failed; -+ } -+ status = vchiq_connect_internal(state, instance); -+ -+ if (status == VCHIQ_SUCCESS) -+ instance->connected = 1; -+ -+ mutex_unlock(&state->mutex); -+ -+failed: -+ vchiq_log_trace(vchiq_core_log_level, -+ "%s(%p): returning %d", __func__, instance, status); -+ -+ return status; -+} -+EXPORT_SYMBOL(vchiq_connect); -+ -+/**************************************************************************** -+* -+* vchiq_add_service -+* -+***************************************************************************/ -+ -+VCHIQ_STATUS_T vchiq_add_service( -+ VCHIQ_INSTANCE_T instance, -+ const VCHIQ_SERVICE_PARAMS_T *params, -+ VCHIQ_SERVICE_HANDLE_T *phandle) -+{ -+ VCHIQ_STATUS_T status; -+ VCHIQ_STATE_T *state = instance->state; -+ VCHIQ_SERVICE_T *service = NULL; -+ int srvstate; -+ -+ vchiq_log_trace(vchiq_core_log_level, -+ "%s(%p) called", __func__, instance); -+ -+ *phandle = VCHIQ_SERVICE_HANDLE_INVALID; -+ -+ srvstate = vchiq_is_connected(instance) -+ ? VCHIQ_SRVSTATE_LISTENING -+ : VCHIQ_SRVSTATE_HIDDEN; -+ -+ service = vchiq_add_service_internal( -+ state, -+ params, -+ srvstate, -+ instance, -+ NULL); -+ -+ if (service) { -+ *phandle = service->handle; -+ status = VCHIQ_SUCCESS; -+ } else -+ status = VCHIQ_ERROR; -+ -+ vchiq_log_trace(vchiq_core_log_level, -+ "%s(%p): returning %d", __func__, instance, status); -+ -+ return status; -+} -+EXPORT_SYMBOL(vchiq_add_service); -+ -+/**************************************************************************** -+* -+* vchiq_open_service -+* -+***************************************************************************/ -+ -+VCHIQ_STATUS_T vchiq_open_service( -+ VCHIQ_INSTANCE_T instance, -+ const VCHIQ_SERVICE_PARAMS_T *params, -+ VCHIQ_SERVICE_HANDLE_T *phandle) -+{ -+ VCHIQ_STATUS_T status = VCHIQ_ERROR; -+ VCHIQ_STATE_T *state = instance->state; -+ VCHIQ_SERVICE_T *service = NULL; -+ -+ vchiq_log_trace(vchiq_core_log_level, -+ "%s(%p) called", __func__, instance); -+ -+ *phandle = VCHIQ_SERVICE_HANDLE_INVALID; -+ -+ if (!vchiq_is_connected(instance)) -+ goto failed; -+ -+ service = vchiq_add_service_internal(state, -+ params, -+ VCHIQ_SRVSTATE_OPENING, -+ instance, -+ NULL); -+ -+ if (service) { -+ *phandle = service->handle; -+ status = vchiq_open_service_internal(service, current->pid); -+ if (status != VCHIQ_SUCCESS) { -+ vchiq_remove_service(service->handle); -+ *phandle = VCHIQ_SERVICE_HANDLE_INVALID; -+ } -+ } -+ -+failed: -+ vchiq_log_trace(vchiq_core_log_level, -+ "%s(%p): returning %d", __func__, instance, status); -+ -+ return status; -+} -+EXPORT_SYMBOL(vchiq_open_service); -+ -+VCHIQ_STATUS_T -+vchiq_queue_bulk_transmit(VCHIQ_SERVICE_HANDLE_T handle, -+ const void *data, unsigned int size, void *userdata) -+{ -+ return vchiq_bulk_transfer(handle, -+ VCHI_MEM_HANDLE_INVALID, (void *)data, size, userdata, -+ VCHIQ_BULK_MODE_CALLBACK, VCHIQ_BULK_TRANSMIT); -+} -+EXPORT_SYMBOL(vchiq_queue_bulk_transmit); -+ -+VCHIQ_STATUS_T -+vchiq_queue_bulk_receive(VCHIQ_SERVICE_HANDLE_T handle, void *data, -+ unsigned int size, void *userdata) -+{ -+ return vchiq_bulk_transfer(handle, -+ VCHI_MEM_HANDLE_INVALID, data, size, userdata, -+ VCHIQ_BULK_MODE_CALLBACK, VCHIQ_BULK_RECEIVE); -+} -+EXPORT_SYMBOL(vchiq_queue_bulk_receive); -+ -+VCHIQ_STATUS_T -+vchiq_bulk_transmit(VCHIQ_SERVICE_HANDLE_T handle, const void *data, -+ unsigned int size, void *userdata, VCHIQ_BULK_MODE_T mode) -+{ -+ VCHIQ_STATUS_T status; -+ -+ switch (mode) { -+ case VCHIQ_BULK_MODE_NOCALLBACK: -+ case VCHIQ_BULK_MODE_CALLBACK: -+ status = vchiq_bulk_transfer(handle, -+ VCHI_MEM_HANDLE_INVALID, (void *)data, size, userdata, -+ mode, VCHIQ_BULK_TRANSMIT); -+ break; -+ case VCHIQ_BULK_MODE_BLOCKING: -+ status = vchiq_blocking_bulk_transfer(handle, -+ (void *)data, size, VCHIQ_BULK_TRANSMIT); -+ break; -+ default: -+ return VCHIQ_ERROR; -+ } -+ -+ return status; -+} -+EXPORT_SYMBOL(vchiq_bulk_transmit); -+ -+VCHIQ_STATUS_T -+vchiq_bulk_receive(VCHIQ_SERVICE_HANDLE_T handle, void *data, -+ unsigned int size, void *userdata, VCHIQ_BULK_MODE_T mode) -+{ -+ VCHIQ_STATUS_T status; -+ -+ switch (mode) { -+ case VCHIQ_BULK_MODE_NOCALLBACK: -+ case VCHIQ_BULK_MODE_CALLBACK: -+ status = vchiq_bulk_transfer(handle, -+ VCHI_MEM_HANDLE_INVALID, data, size, userdata, -+ mode, VCHIQ_BULK_RECEIVE); -+ break; -+ case VCHIQ_BULK_MODE_BLOCKING: -+ status = vchiq_blocking_bulk_transfer(handle, -+ (void *)data, size, VCHIQ_BULK_RECEIVE); -+ break; -+ default: -+ return VCHIQ_ERROR; -+ } -+ -+ return status; -+} -+EXPORT_SYMBOL(vchiq_bulk_receive); -+ -+static VCHIQ_STATUS_T -+vchiq_blocking_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle, void *data, -+ unsigned int size, VCHIQ_BULK_DIR_T dir) -+{ -+ VCHIQ_INSTANCE_T instance; -+ VCHIQ_SERVICE_T *service; -+ VCHIQ_STATUS_T status; -+ struct bulk_waiter_node *waiter = NULL; -+ struct list_head *pos; -+ -+ service = find_service_by_handle(handle); -+ if (!service) -+ return VCHIQ_ERROR; -+ -+ instance = service->instance; -+ -+ unlock_service(service); -+ -+ mutex_lock(&instance->bulk_waiter_list_mutex); -+ list_for_each(pos, &instance->bulk_waiter_list) { -+ if (list_entry(pos, struct bulk_waiter_node, -+ list)->pid == current->pid) { -+ waiter = list_entry(pos, -+ struct bulk_waiter_node, -+ list); -+ list_del(pos); -+ break; -+ } -+ } -+ mutex_unlock(&instance->bulk_waiter_list_mutex); -+ -+ if (waiter) { -+ VCHIQ_BULK_T *bulk = waiter->bulk_waiter.bulk; -+ if (bulk) { -+ /* This thread has an outstanding bulk transfer. */ -+ if ((bulk->data != data) || -+ (bulk->size != size)) { -+ /* This is not a retry of the previous one. -+ ** Cancel the signal when the transfer -+ ** completes. */ -+ spin_lock(&bulk_waiter_spinlock); -+ bulk->userdata = NULL; -+ spin_unlock(&bulk_waiter_spinlock); -+ } -+ } -+ } -+ -+ if (!waiter) { -+ waiter = kzalloc(sizeof(struct bulk_waiter_node), GFP_KERNEL); -+ if (!waiter) { -+ vchiq_log_error(vchiq_core_log_level, -+ "%s - out of memory", __func__); -+ return VCHIQ_ERROR; -+ } -+ } -+ -+ status = vchiq_bulk_transfer(handle, VCHI_MEM_HANDLE_INVALID, -+ data, size, &waiter->bulk_waiter, VCHIQ_BULK_MODE_BLOCKING, -+ dir); -+ if ((status != VCHIQ_RETRY) || fatal_signal_pending(current) || -+ !waiter->bulk_waiter.bulk) { -+ VCHIQ_BULK_T *bulk = waiter->bulk_waiter.bulk; -+ if (bulk) { -+ /* Cancel the signal when the transfer -+ ** completes. */ -+ spin_lock(&bulk_waiter_spinlock); -+ bulk->userdata = NULL; -+ spin_unlock(&bulk_waiter_spinlock); -+ } -+ kfree(waiter); -+ } else { -+ waiter->pid = current->pid; -+ mutex_lock(&instance->bulk_waiter_list_mutex); -+ list_add(&waiter->list, &instance->bulk_waiter_list); -+ mutex_unlock(&instance->bulk_waiter_list_mutex); -+ vchiq_log_info(vchiq_arm_log_level, -+ "saved bulk_waiter %x for pid %d", -+ (unsigned int)waiter, current->pid); -+ } -+ -+ return status; -+} -diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_killable.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_killable.h ---- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_killable.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_killable.h 2015-11-29 09:42:38.075221210 +0100 -@@ -0,0 +1,69 @@ -+/** -+ * Copyright (c) 2010-2012 Broadcom. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef VCHIQ_KILLABLE_H -+#define VCHIQ_KILLABLE_H -+ -+#include -+#include -+ -+#define SHUTDOWN_SIGS (sigmask(SIGKILL) | sigmask(SIGINT) | sigmask(SIGQUIT) | sigmask(SIGTRAP) | sigmask(SIGSTOP) | sigmask(SIGCONT)) -+ -+static inline int __must_check down_interruptible_killable(struct semaphore *sem) -+{ -+ /* Allow interception of killable signals only. We don't want to be interrupted by harmless signals like SIGALRM */ -+ int ret; -+ sigset_t blocked, oldset; -+ siginitsetinv(&blocked, SHUTDOWN_SIGS); -+ sigprocmask(SIG_SETMASK, &blocked, &oldset); -+ ret = down_interruptible(sem); -+ sigprocmask(SIG_SETMASK, &oldset, NULL); -+ return ret; -+} -+#define down_interruptible down_interruptible_killable -+ -+ -+static inline int __must_check mutex_lock_interruptible_killable(struct mutex *lock) -+{ -+ /* Allow interception of killable signals only. We don't want to be interrupted by harmless signals like SIGALRM */ -+ int ret; -+ sigset_t blocked, oldset; -+ siginitsetinv(&blocked, SHUTDOWN_SIGS); -+ sigprocmask(SIG_SETMASK, &blocked, &oldset); -+ ret = mutex_lock_interruptible(lock); -+ sigprocmask(SIG_SETMASK, &oldset, NULL); -+ return ret; -+} -+#define mutex_lock_interruptible mutex_lock_interruptible_killable -+ -+#endif -diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_memdrv.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_memdrv.h ---- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_memdrv.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_memdrv.h 2015-11-29 09:42:38.075221210 +0100 -@@ -0,0 +1,71 @@ -+/** -+ * Copyright (c) 2010-2012 Broadcom. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef VCHIQ_MEMDRV_H -+#define VCHIQ_MEMDRV_H -+ -+/* ---- Include Files ----------------------------------------------------- */ -+ -+#include -+#include "vchiq_if.h" -+ -+/* ---- Constants and Types ---------------------------------------------- */ -+ -+typedef struct { -+ void *armSharedMemVirt; -+ dma_addr_t armSharedMemPhys; -+ size_t armSharedMemSize; -+ -+ void *vcSharedMemVirt; -+ dma_addr_t vcSharedMemPhys; -+ size_t vcSharedMemSize; -+} VCHIQ_SHARED_MEM_INFO_T; -+ -+/* ---- Variable Externs ------------------------------------------------- */ -+ -+/* ---- Function Prototypes ---------------------------------------------- */ -+ -+void vchiq_get_shared_mem_info(VCHIQ_SHARED_MEM_INFO_T *info); -+ -+VCHIQ_STATUS_T vchiq_memdrv_initialise(void); -+ -+VCHIQ_STATUS_T vchiq_userdrv_create_instance( -+ const VCHIQ_PLATFORM_DATA_T * platform_data); -+ -+VCHIQ_STATUS_T vchiq_userdrv_suspend( -+ const VCHIQ_PLATFORM_DATA_T * platform_data); -+ -+VCHIQ_STATUS_T vchiq_userdrv_resume( -+ const VCHIQ_PLATFORM_DATA_T * platform_data); -+ -+#endif -diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_pagelist.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_pagelist.h ---- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_pagelist.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_pagelist.h 2015-11-29 09:42:38.075221210 +0100 -@@ -0,0 +1,58 @@ -+/** -+ * Copyright (c) 2010-2012 Broadcom. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef VCHIQ_PAGELIST_H -+#define VCHIQ_PAGELIST_H -+ -+#ifndef PAGE_SIZE -+#define PAGE_SIZE 4096 -+#endif -+#define CACHE_LINE_SIZE 32 -+#define PAGELIST_WRITE 0 -+#define PAGELIST_READ 1 -+#define PAGELIST_READ_WITH_FRAGMENTS 2 -+ -+typedef struct pagelist_struct { -+ unsigned long length; -+ unsigned short type; -+ unsigned short offset; -+ unsigned long addrs[1]; /* N.B. 12 LSBs hold the number of following -+ pages at consecutive addresses. */ -+} PAGELIST_T; -+ -+typedef struct fragments_struct { -+ char headbuf[CACHE_LINE_SIZE]; -+ char tailbuf[CACHE_LINE_SIZE]; -+} FRAGMENTS_T; -+ -+#endif /* VCHIQ_PAGELIST_H */ -diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c ---- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c 2015-11-29 09:42:38.075221210 +0100 -@@ -0,0 +1,860 @@ -+/** -+ * Copyright (c) 2010-2012 Broadcom. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+#include -+#include -+ -+#include "interface/vchi/vchi.h" -+#include "vchiq.h" -+#include "vchiq_core.h" -+ -+#include "vchiq_util.h" -+ -+#include -+ -+#define vchiq_status_to_vchi(status) ((int32_t)status) -+ -+typedef struct { -+ VCHIQ_SERVICE_HANDLE_T handle; -+ -+ VCHIU_QUEUE_T queue; -+ -+ VCHI_CALLBACK_T callback; -+ void *callback_param; -+} SHIM_SERVICE_T; -+ -+/* ---------------------------------------------------------------------- -+ * return pointer to the mphi message driver function table -+ * -------------------------------------------------------------------- */ -+const VCHI_MESSAGE_DRIVER_T * -+vchi_mphi_message_driver_func_table(void) -+{ -+ return NULL; -+} -+ -+/* ---------------------------------------------------------------------- -+ * return a pointer to the 'single' connection driver fops -+ * -------------------------------------------------------------------- */ -+const VCHI_CONNECTION_API_T * -+single_get_func_table(void) -+{ -+ return NULL; -+} -+ -+VCHI_CONNECTION_T *vchi_create_connection( -+ const VCHI_CONNECTION_API_T *function_table, -+ const VCHI_MESSAGE_DRIVER_T *low_level) -+{ -+ (void)function_table; -+ (void)low_level; -+ return NULL; -+} -+ -+/*********************************************************** -+ * Name: vchi_msg_peek -+ * -+ * Arguments: const VCHI_SERVICE_HANDLE_T handle, -+ * void **data, -+ * uint32_t *msg_size, -+ -+ -+ * VCHI_FLAGS_T flags -+ * -+ * Description: Routine to return a pointer to the current message (to allow in -+ * place processing). The message can be removed using -+ * vchi_msg_remove when you're finished -+ * -+ * Returns: int32_t - success == 0 -+ * -+ ***********************************************************/ -+int32_t vchi_msg_peek(VCHI_SERVICE_HANDLE_T handle, -+ void **data, -+ uint32_t *msg_size, -+ VCHI_FLAGS_T flags) -+{ -+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; -+ VCHIQ_HEADER_T *header; -+ -+ WARN_ON((flags != VCHI_FLAGS_NONE) && -+ (flags != VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE)); -+ -+ if (flags == VCHI_FLAGS_NONE) -+ if (vchiu_queue_is_empty(&service->queue)) -+ return -1; -+ -+ header = vchiu_queue_peek(&service->queue); -+ -+ *data = header->data; -+ *msg_size = header->size; -+ -+ return 0; -+} -+EXPORT_SYMBOL(vchi_msg_peek); -+ -+/*********************************************************** -+ * Name: vchi_msg_remove -+ * -+ * Arguments: const VCHI_SERVICE_HANDLE_T handle, -+ * -+ * Description: Routine to remove a message (after it has been read with -+ * vchi_msg_peek) -+ * -+ * Returns: int32_t - success == 0 -+ * -+ ***********************************************************/ -+int32_t vchi_msg_remove(VCHI_SERVICE_HANDLE_T handle) -+{ -+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; -+ VCHIQ_HEADER_T *header; -+ -+ header = vchiu_queue_pop(&service->queue); -+ -+ vchiq_release_message(service->handle, header); -+ -+ return 0; -+} -+EXPORT_SYMBOL(vchi_msg_remove); -+ -+/*********************************************************** -+ * Name: vchi_msg_queue -+ * -+ * Arguments: VCHI_SERVICE_HANDLE_T handle, -+ * const void *data, -+ * uint32_t data_size, -+ * VCHI_FLAGS_T flags, -+ * void *msg_handle, -+ * -+ * Description: Thin wrapper to queue a message onto a connection -+ * -+ * Returns: int32_t - success == 0 -+ * -+ ***********************************************************/ -+int32_t vchi_msg_queue(VCHI_SERVICE_HANDLE_T handle, -+ const void *data, -+ uint32_t data_size, -+ VCHI_FLAGS_T flags, -+ void *msg_handle) -+{ -+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; -+ VCHIQ_ELEMENT_T element = {data, data_size}; -+ VCHIQ_STATUS_T status; -+ -+ (void)msg_handle; -+ -+ WARN_ON(flags != VCHI_FLAGS_BLOCK_UNTIL_QUEUED); -+ -+ status = vchiq_queue_message(service->handle, &element, 1); -+ -+ /* vchiq_queue_message() may return VCHIQ_RETRY, so we need to -+ ** implement a retry mechanism since this function is supposed -+ ** to block until queued -+ */ -+ while (status == VCHIQ_RETRY) { -+ msleep(1); -+ status = vchiq_queue_message(service->handle, &element, 1); -+ } -+ -+ return vchiq_status_to_vchi(status); -+} -+EXPORT_SYMBOL(vchi_msg_queue); -+ -+/*********************************************************** -+ * Name: vchi_bulk_queue_receive -+ * -+ * Arguments: VCHI_BULK_HANDLE_T handle, -+ * void *data_dst, -+ * const uint32_t data_size, -+ * VCHI_FLAGS_T flags -+ * void *bulk_handle -+ * -+ * Description: Routine to setup a rcv buffer -+ * -+ * Returns: int32_t - success == 0 -+ * -+ ***********************************************************/ -+int32_t vchi_bulk_queue_receive(VCHI_SERVICE_HANDLE_T handle, -+ void *data_dst, -+ uint32_t data_size, -+ VCHI_FLAGS_T flags, -+ void *bulk_handle) -+{ -+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; -+ VCHIQ_BULK_MODE_T mode; -+ VCHIQ_STATUS_T status; -+ -+ switch ((int)flags) { -+ case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE -+ | VCHI_FLAGS_BLOCK_UNTIL_QUEUED: -+ WARN_ON(!service->callback); -+ mode = VCHIQ_BULK_MODE_CALLBACK; -+ break; -+ case VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE: -+ mode = VCHIQ_BULK_MODE_BLOCKING; -+ break; -+ case VCHI_FLAGS_BLOCK_UNTIL_QUEUED: -+ case VCHI_FLAGS_NONE: -+ mode = VCHIQ_BULK_MODE_NOCALLBACK; -+ break; -+ default: -+ WARN(1, "unsupported message\n"); -+ return vchiq_status_to_vchi(VCHIQ_ERROR); -+ } -+ -+ status = vchiq_bulk_receive(service->handle, data_dst, data_size, -+ bulk_handle, mode); -+ -+ /* vchiq_bulk_receive() may return VCHIQ_RETRY, so we need to -+ ** implement a retry mechanism since this function is supposed -+ ** to block until queued -+ */ -+ while (status == VCHIQ_RETRY) { -+ msleep(1); -+ status = vchiq_bulk_receive(service->handle, data_dst, -+ data_size, bulk_handle, mode); -+ } -+ -+ return vchiq_status_to_vchi(status); -+} -+EXPORT_SYMBOL(vchi_bulk_queue_receive); -+ -+/*********************************************************** -+ * Name: vchi_bulk_queue_transmit -+ * -+ * Arguments: VCHI_BULK_HANDLE_T handle, -+ * const void *data_src, -+ * uint32_t data_size, -+ * VCHI_FLAGS_T flags, -+ * void *bulk_handle -+ * -+ * Description: Routine to transmit some data -+ * -+ * Returns: int32_t - success == 0 -+ * -+ ***********************************************************/ -+int32_t vchi_bulk_queue_transmit(VCHI_SERVICE_HANDLE_T handle, -+ const void *data_src, -+ uint32_t data_size, -+ VCHI_FLAGS_T flags, -+ void *bulk_handle) -+{ -+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; -+ VCHIQ_BULK_MODE_T mode; -+ VCHIQ_STATUS_T status; -+ -+ switch ((int)flags) { -+ case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE -+ | VCHI_FLAGS_BLOCK_UNTIL_QUEUED: -+ WARN_ON(!service->callback); -+ mode = VCHIQ_BULK_MODE_CALLBACK; -+ break; -+ case VCHI_FLAGS_BLOCK_UNTIL_DATA_READ: -+ case VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE: -+ mode = VCHIQ_BULK_MODE_BLOCKING; -+ break; -+ case VCHI_FLAGS_BLOCK_UNTIL_QUEUED: -+ case VCHI_FLAGS_NONE: -+ mode = VCHIQ_BULK_MODE_NOCALLBACK; -+ break; -+ default: -+ WARN(1, "unsupported message\n"); -+ return vchiq_status_to_vchi(VCHIQ_ERROR); -+ } -+ -+ status = vchiq_bulk_transmit(service->handle, data_src, data_size, -+ bulk_handle, mode); -+ -+ /* vchiq_bulk_transmit() may return VCHIQ_RETRY, so we need to -+ ** implement a retry mechanism since this function is supposed -+ ** to block until queued -+ */ -+ while (status == VCHIQ_RETRY) { -+ msleep(1); -+ status = vchiq_bulk_transmit(service->handle, data_src, -+ data_size, bulk_handle, mode); -+ } -+ -+ return vchiq_status_to_vchi(status); -+} -+EXPORT_SYMBOL(vchi_bulk_queue_transmit); -+ -+/*********************************************************** -+ * Name: vchi_msg_dequeue -+ * -+ * Arguments: VCHI_SERVICE_HANDLE_T handle, -+ * void *data, -+ * uint32_t max_data_size_to_read, -+ * uint32_t *actual_msg_size -+ * VCHI_FLAGS_T flags -+ * -+ * Description: Routine to dequeue a message into the supplied buffer -+ * -+ * Returns: int32_t - success == 0 -+ * -+ ***********************************************************/ -+int32_t vchi_msg_dequeue(VCHI_SERVICE_HANDLE_T handle, -+ void *data, -+ uint32_t max_data_size_to_read, -+ uint32_t *actual_msg_size, -+ VCHI_FLAGS_T flags) -+{ -+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; -+ VCHIQ_HEADER_T *header; -+ -+ WARN_ON((flags != VCHI_FLAGS_NONE) && -+ (flags != VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE)); -+ -+ if (flags == VCHI_FLAGS_NONE) -+ if (vchiu_queue_is_empty(&service->queue)) -+ return -1; -+ -+ header = vchiu_queue_pop(&service->queue); -+ -+ memcpy(data, header->data, header->size < max_data_size_to_read ? -+ header->size : max_data_size_to_read); -+ -+ *actual_msg_size = header->size; -+ -+ vchiq_release_message(service->handle, header); -+ -+ return 0; -+} -+EXPORT_SYMBOL(vchi_msg_dequeue); -+ -+/*********************************************************** -+ * Name: vchi_msg_queuev -+ * -+ * Arguments: VCHI_SERVICE_HANDLE_T handle, -+ * VCHI_MSG_VECTOR_T *vector, -+ * uint32_t count, -+ * VCHI_FLAGS_T flags, -+ * void *msg_handle -+ * -+ * Description: Thin wrapper to queue a message onto a connection -+ * -+ * Returns: int32_t - success == 0 -+ * -+ ***********************************************************/ -+ -+vchiq_static_assert(sizeof(VCHI_MSG_VECTOR_T) == sizeof(VCHIQ_ELEMENT_T)); -+vchiq_static_assert(offsetof(VCHI_MSG_VECTOR_T, vec_base) == -+ offsetof(VCHIQ_ELEMENT_T, data)); -+vchiq_static_assert(offsetof(VCHI_MSG_VECTOR_T, vec_len) == -+ offsetof(VCHIQ_ELEMENT_T, size)); -+ -+int32_t vchi_msg_queuev(VCHI_SERVICE_HANDLE_T handle, -+ VCHI_MSG_VECTOR_T *vector, -+ uint32_t count, -+ VCHI_FLAGS_T flags, -+ void *msg_handle) -+{ -+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; -+ -+ (void)msg_handle; -+ -+ WARN_ON(flags != VCHI_FLAGS_BLOCK_UNTIL_QUEUED); -+ -+ return vchiq_status_to_vchi(vchiq_queue_message(service->handle, -+ (const VCHIQ_ELEMENT_T *)vector, count)); -+} -+EXPORT_SYMBOL(vchi_msg_queuev); -+ -+/*********************************************************** -+ * Name: vchi_held_msg_release -+ * -+ * Arguments: VCHI_HELD_MSG_T *message -+ * -+ * Description: Routine to release a held message (after it has been read with -+ * vchi_msg_hold) -+ * -+ * Returns: int32_t - success == 0 -+ * -+ ***********************************************************/ -+int32_t vchi_held_msg_release(VCHI_HELD_MSG_T *message) -+{ -+ vchiq_release_message((VCHIQ_SERVICE_HANDLE_T)message->service, -+ (VCHIQ_HEADER_T *)message->message); -+ -+ return 0; -+} -+EXPORT_SYMBOL(vchi_held_msg_release); -+ -+/*********************************************************** -+ * Name: vchi_msg_hold -+ * -+ * Arguments: VCHI_SERVICE_HANDLE_T handle, -+ * void **data, -+ * uint32_t *msg_size, -+ * VCHI_FLAGS_T flags, -+ * VCHI_HELD_MSG_T *message_handle -+ * -+ * Description: Routine to return a pointer to the current message (to allow -+ * in place processing). The message is dequeued - don't forget -+ * to release the message using vchi_held_msg_release when you're -+ * finished. -+ * -+ * Returns: int32_t - success == 0 -+ * -+ ***********************************************************/ -+int32_t vchi_msg_hold(VCHI_SERVICE_HANDLE_T handle, -+ void **data, -+ uint32_t *msg_size, -+ VCHI_FLAGS_T flags, -+ VCHI_HELD_MSG_T *message_handle) -+{ -+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; -+ VCHIQ_HEADER_T *header; -+ -+ WARN_ON((flags != VCHI_FLAGS_NONE) && -+ (flags != VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE)); -+ -+ if (flags == VCHI_FLAGS_NONE) -+ if (vchiu_queue_is_empty(&service->queue)) -+ return -1; -+ -+ header = vchiu_queue_pop(&service->queue); -+ -+ *data = header->data; -+ *msg_size = header->size; -+ -+ message_handle->service = -+ (struct opaque_vchi_service_t *)service->handle; -+ message_handle->message = header; -+ -+ return 0; -+} -+EXPORT_SYMBOL(vchi_msg_hold); -+ -+/*********************************************************** -+ * Name: vchi_initialise -+ * -+ * Arguments: VCHI_INSTANCE_T *instance_handle -+ * -+ * Description: Initialises the hardware but does not transmit anything -+ * When run as a Host App this will be called twice hence the need -+ * to malloc the state information -+ * -+ * Returns: 0 if successful, failure otherwise -+ * -+ ***********************************************************/ -+ -+int32_t vchi_initialise(VCHI_INSTANCE_T *instance_handle) -+{ -+ VCHIQ_INSTANCE_T instance; -+ VCHIQ_STATUS_T status; -+ -+ status = vchiq_initialise(&instance); -+ -+ *instance_handle = (VCHI_INSTANCE_T)instance; -+ -+ return vchiq_status_to_vchi(status); -+} -+EXPORT_SYMBOL(vchi_initialise); -+ -+/*********************************************************** -+ * Name: vchi_connect -+ * -+ * Arguments: VCHI_CONNECTION_T **connections -+ * const uint32_t num_connections -+ * VCHI_INSTANCE_T instance_handle) -+ * -+ * Description: Starts the command service on each connection, -+ * causing INIT messages to be pinged back and forth -+ * -+ * Returns: 0 if successful, failure otherwise -+ * -+ ***********************************************************/ -+int32_t vchi_connect(VCHI_CONNECTION_T **connections, -+ const uint32_t num_connections, -+ VCHI_INSTANCE_T instance_handle) -+{ -+ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle; -+ -+ (void)connections; -+ (void)num_connections; -+ -+ return vchiq_connect(instance); -+} -+EXPORT_SYMBOL(vchi_connect); -+ -+ -+/*********************************************************** -+ * Name: vchi_disconnect -+ * -+ * Arguments: VCHI_INSTANCE_T instance_handle -+ * -+ * Description: Stops the command service on each connection, -+ * causing DE-INIT messages to be pinged back and forth -+ * -+ * Returns: 0 if successful, failure otherwise -+ * -+ ***********************************************************/ -+int32_t vchi_disconnect(VCHI_INSTANCE_T instance_handle) -+{ -+ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle; -+ return vchiq_status_to_vchi(vchiq_shutdown(instance)); -+} -+EXPORT_SYMBOL(vchi_disconnect); -+ -+ -+/*********************************************************** -+ * Name: vchi_service_open -+ * Name: vchi_service_create -+ * -+ * Arguments: VCHI_INSTANCE_T *instance_handle -+ * SERVICE_CREATION_T *setup, -+ * VCHI_SERVICE_HANDLE_T *handle -+ * -+ * Description: Routine to open a service -+ * -+ * Returns: int32_t - success == 0 -+ * -+ ***********************************************************/ -+ -+static VCHIQ_STATUS_T shim_callback(VCHIQ_REASON_T reason, -+ VCHIQ_HEADER_T *header, VCHIQ_SERVICE_HANDLE_T handle, void *bulk_user) -+{ -+ SHIM_SERVICE_T *service = -+ (SHIM_SERVICE_T *)VCHIQ_GET_SERVICE_USERDATA(handle); -+ -+ if (!service->callback) -+ goto release; -+ -+ switch (reason) { -+ case VCHIQ_MESSAGE_AVAILABLE: -+ vchiu_queue_push(&service->queue, header); -+ -+ service->callback(service->callback_param, -+ VCHI_CALLBACK_MSG_AVAILABLE, NULL); -+ -+ goto done; -+ break; -+ -+ case VCHIQ_BULK_TRANSMIT_DONE: -+ service->callback(service->callback_param, -+ VCHI_CALLBACK_BULK_SENT, bulk_user); -+ break; -+ -+ case VCHIQ_BULK_RECEIVE_DONE: -+ service->callback(service->callback_param, -+ VCHI_CALLBACK_BULK_RECEIVED, bulk_user); -+ break; -+ -+ case VCHIQ_SERVICE_CLOSED: -+ service->callback(service->callback_param, -+ VCHI_CALLBACK_SERVICE_CLOSED, NULL); -+ break; -+ -+ case VCHIQ_SERVICE_OPENED: -+ /* No equivalent VCHI reason */ -+ break; -+ -+ case VCHIQ_BULK_TRANSMIT_ABORTED: -+ service->callback(service->callback_param, -+ VCHI_CALLBACK_BULK_TRANSMIT_ABORTED, -+ bulk_user); -+ break; -+ -+ case VCHIQ_BULK_RECEIVE_ABORTED: -+ service->callback(service->callback_param, -+ VCHI_CALLBACK_BULK_RECEIVE_ABORTED, -+ bulk_user); -+ break; -+ -+ default: -+ WARN(1, "not supported\n"); -+ break; -+ } -+ -+release: -+ vchiq_release_message(service->handle, header); -+done: -+ return VCHIQ_SUCCESS; -+} -+ -+static SHIM_SERVICE_T *service_alloc(VCHIQ_INSTANCE_T instance, -+ SERVICE_CREATION_T *setup) -+{ -+ SHIM_SERVICE_T *service = kzalloc(sizeof(SHIM_SERVICE_T), GFP_KERNEL); -+ -+ (void)instance; -+ -+ if (service) { -+ if (vchiu_queue_init(&service->queue, 64)) { -+ service->callback = setup->callback; -+ service->callback_param = setup->callback_param; -+ } else { -+ kfree(service); -+ service = NULL; -+ } -+ } -+ -+ return service; -+} -+ -+static void service_free(SHIM_SERVICE_T *service) -+{ -+ if (service) { -+ vchiu_queue_delete(&service->queue); -+ kfree(service); -+ } -+} -+ -+int32_t vchi_service_open(VCHI_INSTANCE_T instance_handle, -+ SERVICE_CREATION_T *setup, -+ VCHI_SERVICE_HANDLE_T *handle) -+{ -+ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle; -+ SHIM_SERVICE_T *service = service_alloc(instance, setup); -+ -+ *handle = (VCHI_SERVICE_HANDLE_T)service; -+ -+ if (service) { -+ VCHIQ_SERVICE_PARAMS_T params; -+ VCHIQ_STATUS_T status; -+ -+ memset(¶ms, 0, sizeof(params)); -+ params.fourcc = setup->service_id; -+ params.callback = shim_callback; -+ params.userdata = service; -+ params.version = setup->version.version; -+ params.version_min = setup->version.version_min; -+ -+ status = vchiq_open_service(instance, ¶ms, -+ &service->handle); -+ if (status != VCHIQ_SUCCESS) { -+ service_free(service); -+ service = NULL; -+ *handle = NULL; -+ } -+ } -+ -+ return (service != NULL) ? 0 : -1; -+} -+EXPORT_SYMBOL(vchi_service_open); -+ -+int32_t vchi_service_create(VCHI_INSTANCE_T instance_handle, -+ SERVICE_CREATION_T *setup, -+ VCHI_SERVICE_HANDLE_T *handle) -+{ -+ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle; -+ SHIM_SERVICE_T *service = service_alloc(instance, setup); -+ -+ *handle = (VCHI_SERVICE_HANDLE_T)service; -+ -+ if (service) { -+ VCHIQ_SERVICE_PARAMS_T params; -+ VCHIQ_STATUS_T status; -+ -+ memset(¶ms, 0, sizeof(params)); -+ params.fourcc = setup->service_id; -+ params.callback = shim_callback; -+ params.userdata = service; -+ params.version = setup->version.version; -+ params.version_min = setup->version.version_min; -+ status = vchiq_add_service(instance, ¶ms, &service->handle); -+ -+ if (status != VCHIQ_SUCCESS) { -+ service_free(service); -+ service = NULL; -+ *handle = NULL; -+ } -+ } -+ -+ return (service != NULL) ? 0 : -1; -+} -+EXPORT_SYMBOL(vchi_service_create); -+ -+int32_t vchi_service_close(const VCHI_SERVICE_HANDLE_T handle) -+{ -+ int32_t ret = -1; -+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; -+ if (service) { -+ VCHIQ_STATUS_T status = vchiq_close_service(service->handle); -+ if (status == VCHIQ_SUCCESS) { -+ service_free(service); -+ service = NULL; -+ } -+ -+ ret = vchiq_status_to_vchi(status); -+ } -+ return ret; -+} -+EXPORT_SYMBOL(vchi_service_close); -+ -+int32_t vchi_service_destroy(const VCHI_SERVICE_HANDLE_T handle) -+{ -+ int32_t ret = -1; -+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; -+ if (service) { -+ VCHIQ_STATUS_T status = vchiq_remove_service(service->handle); -+ if (status == VCHIQ_SUCCESS) { -+ service_free(service); -+ service = NULL; -+ } -+ -+ ret = vchiq_status_to_vchi(status); -+ } -+ return ret; -+} -+EXPORT_SYMBOL(vchi_service_destroy); -+ -+int32_t vchi_service_set_option(const VCHI_SERVICE_HANDLE_T handle, -+ VCHI_SERVICE_OPTION_T option, -+ int value) -+{ -+ int32_t ret = -1; -+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; -+ VCHIQ_SERVICE_OPTION_T vchiq_option; -+ switch (option) { -+ case VCHI_SERVICE_OPTION_TRACE: -+ vchiq_option = VCHIQ_SERVICE_OPTION_TRACE; -+ break; -+ case VCHI_SERVICE_OPTION_SYNCHRONOUS: -+ vchiq_option = VCHIQ_SERVICE_OPTION_SYNCHRONOUS; -+ break; -+ default: -+ service = NULL; -+ break; -+ } -+ if (service) { -+ VCHIQ_STATUS_T status = -+ vchiq_set_service_option(service->handle, -+ vchiq_option, -+ value); -+ -+ ret = vchiq_status_to_vchi(status); -+ } -+ return ret; -+} -+EXPORT_SYMBOL(vchi_service_set_option); -+ -+int32_t vchi_get_peer_version( const VCHI_SERVICE_HANDLE_T handle, short *peer_version ) -+{ -+ int32_t ret = -1; -+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; -+ if(service) -+ { -+ VCHIQ_STATUS_T status = vchiq_get_peer_version(service->handle, peer_version); -+ ret = vchiq_status_to_vchi( status ); -+ } -+ return ret; -+} -+EXPORT_SYMBOL(vchi_get_peer_version); -+ -+/* ---------------------------------------------------------------------- -+ * read a uint32_t from buffer. -+ * network format is defined to be little endian -+ * -------------------------------------------------------------------- */ -+uint32_t -+vchi_readbuf_uint32(const void *_ptr) -+{ -+ const unsigned char *ptr = _ptr; -+ return ptr[0] | (ptr[1] << 8) | (ptr[2] << 16) | (ptr[3] << 24); -+} -+ -+/* ---------------------------------------------------------------------- -+ * write a uint32_t to buffer. -+ * network format is defined to be little endian -+ * -------------------------------------------------------------------- */ -+void -+vchi_writebuf_uint32(void *_ptr, uint32_t value) -+{ -+ unsigned char *ptr = _ptr; -+ ptr[0] = (unsigned char)((value >> 0) & 0xFF); -+ ptr[1] = (unsigned char)((value >> 8) & 0xFF); -+ ptr[2] = (unsigned char)((value >> 16) & 0xFF); -+ ptr[3] = (unsigned char)((value >> 24) & 0xFF); -+} -+ -+/* ---------------------------------------------------------------------- -+ * read a uint16_t from buffer. -+ * network format is defined to be little endian -+ * -------------------------------------------------------------------- */ -+uint16_t -+vchi_readbuf_uint16(const void *_ptr) -+{ -+ const unsigned char *ptr = _ptr; -+ return ptr[0] | (ptr[1] << 8); -+} -+ -+/* ---------------------------------------------------------------------- -+ * write a uint16_t into the buffer. -+ * network format is defined to be little endian -+ * -------------------------------------------------------------------- */ -+void -+vchi_writebuf_uint16(void *_ptr, uint16_t value) -+{ -+ unsigned char *ptr = _ptr; -+ ptr[0] = (value >> 0) & 0xFF; -+ ptr[1] = (value >> 8) & 0xFF; -+} -+ -+/*********************************************************** -+ * Name: vchi_service_use -+ * -+ * Arguments: const VCHI_SERVICE_HANDLE_T handle -+ * -+ * Description: Routine to increment refcount on a service -+ * -+ * Returns: void -+ * -+ ***********************************************************/ -+int32_t vchi_service_use(const VCHI_SERVICE_HANDLE_T handle) -+{ -+ int32_t ret = -1; -+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; -+ if (service) -+ ret = vchiq_status_to_vchi(vchiq_use_service(service->handle)); -+ return ret; -+} -+EXPORT_SYMBOL(vchi_service_use); -+ -+/*********************************************************** -+ * Name: vchi_service_release -+ * -+ * Arguments: const VCHI_SERVICE_HANDLE_T handle -+ * -+ * Description: Routine to decrement refcount on a service -+ * -+ * Returns: void -+ * -+ ***********************************************************/ -+int32_t vchi_service_release(const VCHI_SERVICE_HANDLE_T handle) -+{ -+ int32_t ret = -1; -+ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; -+ if (service) -+ ret = vchiq_status_to_vchi( -+ vchiq_release_service(service->handle)); -+ return ret; -+} -+EXPORT_SYMBOL(vchi_service_release); -diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c ---- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c 2015-11-29 09:42:38.075221210 +0100 -@@ -0,0 +1,156 @@ -+/** -+ * Copyright (c) 2010-2012 Broadcom. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include "vchiq_util.h" -+#include "vchiq_killable.h" -+ -+static inline int is_pow2(int i) -+{ -+ return i && !(i & (i - 1)); -+} -+ -+int vchiu_queue_init(VCHIU_QUEUE_T *queue, int size) -+{ -+ WARN_ON(!is_pow2(size)); -+ -+ queue->size = size; -+ queue->read = 0; -+ queue->write = 0; -+ queue->initialized = 1; -+ -+ sema_init(&queue->pop, 0); -+ sema_init(&queue->push, 0); -+ -+ queue->storage = kzalloc(size * sizeof(VCHIQ_HEADER_T *), GFP_KERNEL); -+ if (queue->storage == NULL) { -+ vchiu_queue_delete(queue); -+ return 0; -+ } -+ return 1; -+} -+ -+void vchiu_queue_delete(VCHIU_QUEUE_T *queue) -+{ -+ if (queue->storage != NULL) -+ kfree(queue->storage); -+} -+ -+int vchiu_queue_is_empty(VCHIU_QUEUE_T *queue) -+{ -+ return queue->read == queue->write; -+} -+ -+int vchiu_queue_is_full(VCHIU_QUEUE_T *queue) -+{ -+ return queue->write == queue->read + queue->size; -+} -+ -+void vchiu_queue_push(VCHIU_QUEUE_T *queue, VCHIQ_HEADER_T *header) -+{ -+ if (!queue->initialized) -+ return; -+ -+ while (queue->write == queue->read + queue->size) { -+ if (down_interruptible(&queue->pop) != 0) { -+ flush_signals(current); -+ } -+ } -+ -+ /* -+ * Write to queue->storage must be visible after read from -+ * queue->read -+ */ -+ smp_mb(); -+ -+ queue->storage[queue->write & (queue->size - 1)] = header; -+ -+ /* -+ * Write to queue->storage must be visible before write to -+ * queue->write -+ */ -+ smp_wmb(); -+ -+ queue->write++; -+ -+ up(&queue->push); -+} -+ -+VCHIQ_HEADER_T *vchiu_queue_peek(VCHIU_QUEUE_T *queue) -+{ -+ while (queue->write == queue->read) { -+ if (down_interruptible(&queue->push) != 0) { -+ flush_signals(current); -+ } -+ } -+ -+ up(&queue->push); // We haven't removed anything from the queue. -+ -+ /* -+ * Read from queue->storage must be visible after read from -+ * queue->write -+ */ -+ smp_rmb(); -+ -+ return queue->storage[queue->read & (queue->size - 1)]; -+} -+ -+VCHIQ_HEADER_T *vchiu_queue_pop(VCHIU_QUEUE_T *queue) -+{ -+ VCHIQ_HEADER_T *header; -+ -+ while (queue->write == queue->read) { -+ if (down_interruptible(&queue->push) != 0) { -+ flush_signals(current); -+ } -+ } -+ -+ /* -+ * Read from queue->storage must be visible after read from -+ * queue->write -+ */ -+ smp_rmb(); -+ -+ header = queue->storage[queue->read & (queue->size - 1)]; -+ -+ /* -+ * Read from queue->storage must be visible before write to -+ * queue->read -+ */ -+ smp_mb(); -+ -+ queue->read++; -+ -+ up(&queue->pop); -+ -+ return header; -+} -diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.h ---- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.h 2015-11-29 09:42:38.075221210 +0100 -@@ -0,0 +1,82 @@ -+/** -+ * Copyright (c) 2010-2012 Broadcom. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef VCHIQ_UTIL_H -+#define VCHIQ_UTIL_H -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include /* for time_t */ -+#include -+#include -+ -+#include "vchiq_if.h" -+ -+typedef struct { -+ int size; -+ int read; -+ int write; -+ int initialized; -+ -+ struct semaphore pop; -+ struct semaphore push; -+ -+ VCHIQ_HEADER_T **storage; -+} VCHIU_QUEUE_T; -+ -+extern int vchiu_queue_init(VCHIU_QUEUE_T *queue, int size); -+extern void vchiu_queue_delete(VCHIU_QUEUE_T *queue); -+ -+extern int vchiu_queue_is_empty(VCHIU_QUEUE_T *queue); -+extern int vchiu_queue_is_full(VCHIU_QUEUE_T *queue); -+ -+extern void vchiu_queue_push(VCHIU_QUEUE_T *queue, VCHIQ_HEADER_T *header); -+ -+extern VCHIQ_HEADER_T *vchiu_queue_peek(VCHIU_QUEUE_T *queue); -+extern VCHIQ_HEADER_T *vchiu_queue_pop(VCHIU_QUEUE_T *queue); -+ -+#endif -diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_version.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_version.c ---- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_version.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_version.c 2015-11-29 09:42:38.075221210 +0100 -@@ -0,0 +1,59 @@ -+/** -+ * Copyright (c) 2010-2012 Broadcom. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+#include "vchiq_build_info.h" -+#include -+ -+VC_DEBUG_DECLARE_STRING_VAR( vchiq_build_hostname, "dc4-arm-01" ); -+VC_DEBUG_DECLARE_STRING_VAR( vchiq_build_version, "9245b4c35b99b3870e1f7dc598c5692b3c66a6f0 (tainted)" ); -+VC_DEBUG_DECLARE_STRING_VAR( vchiq_build_time, __TIME__ ); -+VC_DEBUG_DECLARE_STRING_VAR( vchiq_build_date, __DATE__ ); -+ -+const char *vchiq_get_build_hostname( void ) -+{ -+ return vchiq_build_hostname; -+} -+ -+const char *vchiq_get_build_version( void ) -+{ -+ return vchiq_build_version; -+} -+ -+const char *vchiq_get_build_date( void ) -+{ -+ return vchiq_build_date; -+} -+ -+const char *vchiq_get_build_time( void ) -+{ -+ return vchiq_build_time; -+} -diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/Kconfig linux-rpi/drivers/misc/vc04_services/Kconfig ---- linux-4.1.13.orig/drivers/misc/vc04_services/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/misc/vc04_services/Kconfig 2015-11-29 09:42:38.059222273 +0100 -@@ -0,0 +1,9 @@ -+config BCM2708_VCHIQ -+ tristate "Videocore VCHIQ" -+ depends on RASPBERRYPI_FIRMWARE -+ default y -+ help -+ Kernel to VideoCore communication interface for the -+ BCM2708 family of products. -+ Defaults to Y when the Broadcom Videocore services -+ are included in the build, N otherwise. -diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/Makefile linux-rpi/drivers/misc/vc04_services/Makefile ---- linux-4.1.13.orig/drivers/misc/vc04_services/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/misc/vc04_services/Makefile 2015-11-29 09:42:38.059222273 +0100 -@@ -0,0 +1,14 @@ -+obj-$(CONFIG_BCM2708_VCHIQ) += vchiq.o -+ -+vchiq-objs := \ -+ interface/vchiq_arm/vchiq_core.o \ -+ interface/vchiq_arm/vchiq_arm.o \ -+ interface/vchiq_arm/vchiq_kern_lib.o \ -+ interface/vchiq_arm/vchiq_2835_arm.o \ -+ interface/vchiq_arm/vchiq_debugfs.o \ -+ interface/vchiq_arm/vchiq_shim.o \ -+ interface/vchiq_arm/vchiq_util.o \ -+ interface/vchiq_arm/vchiq_connected.o \ -+ -+ccflags-y += -DVCOS_VERIFY_BKPTS=1 -Idrivers/misc/vc04_services -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -+ -diff -Nur linux-4.1.13.orig/drivers/mmc/card/block.c linux-rpi/drivers/mmc/card/block.c ---- linux-4.1.13.orig/drivers/mmc/card/block.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/mmc/card/block.c 2015-11-29 09:42:38.079220944 +0100 -@@ -1415,6 +1415,7 @@ - brq->data.blocks = card->host->ops->multi_io_quirk(card, - (rq_data_dir(req) == READ) ? - MMC_DATA_READ : MMC_DATA_WRITE, -+ blk_rq_pos(req), - brq->data.blocks); - } - -diff -Nur linux-4.1.13.orig/drivers/mmc/core/quirks.c linux-rpi/drivers/mmc/core/quirks.c ---- linux-4.1.13.orig/drivers/mmc/core/quirks.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/mmc/core/quirks.c 2015-11-29 09:42:38.083220679 +0100 -@@ -71,6 +71,7 @@ - - void mmc_fixup_device(struct mmc_card *card, const struct mmc_fixup *table) - { -+ extern unsigned mmc_debug; - const struct mmc_fixup *f; - u64 rev = cid_rev_card(card); - -@@ -95,5 +96,10 @@ - f->vendor_fixup(card, f->data); - } - } -+ /* SDHCI on BCM2708 - bug causes a certain sequence of CMD23 operations to fail. -+ * Disable this flag for all cards (fall-back to CMD25/CMD18 multi-block transfers). -+ */ -+ if (mmc_debug & (1<<13)) -+ card->quirks |= MMC_QUIRK_BLK_NO_CMD23; - } - EXPORT_SYMBOL(mmc_fixup_device); -diff -Nur linux-4.1.13.orig/drivers/mmc/host/bcm2835-mmc.c linux-rpi/drivers/mmc/host/bcm2835-mmc.c ---- linux-4.1.13.orig/drivers/mmc/host/bcm2835-mmc.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/mmc/host/bcm2835-mmc.c 2015-11-29 09:42:38.087220413 +0100 -@@ -0,0 +1,1559 @@ -+/* -+ * BCM2835 MMC host driver. -+ * -+ * Author: Gellert Weisz -+ * Copyright 2014 -+ * -+ * Based on -+ * sdhci-bcm2708.c by Broadcom -+ * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko -+ * sdhci.c and sdhci-pci.c by Pierre Ossman -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms and conditions of the GNU General Public License, -+ * version 2, as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "sdhci.h" -+ -+ -+#define DRIVER_NAME "mmc-bcm2835" -+ -+#define DBG(f, x...) \ -+pr_debug(DRIVER_NAME " [%s()]: " f, __func__, ## x) -+ -+#ifndef CONFIG_MMC_BCM2835_DMA -+ #define FORCE_PIO -+#endif -+ -+ -+/* the inclusive limit in bytes under which PIO will be used instead of DMA */ -+#ifdef CONFIG_MMC_BCM2835_PIO_DMA_BARRIER -+#define PIO_DMA_BARRIER CONFIG_MMC_BCM2835_PIO_DMA_BARRIER -+#else -+#define PIO_DMA_BARRIER 00 -+#endif -+ -+#define MIN_FREQ 400000 -+#define TIMEOUT_VAL 0xE -+#define BCM2835_SDHCI_WRITE_DELAY(f) (((2 * 1000000) / f) + 1) -+ -+#ifndef BCM2708_PERI_BASE -+ #define BCM2708_PERI_BASE 0x20000000 -+#endif -+ -+/* FIXME: Needs IOMMU support */ -+#define BCM2835_VCMMU_SHIFT (0x7E000000 - BCM2708_PERI_BASE) -+ -+ -+unsigned mmc_debug; -+unsigned mmc_debug2; -+ -+struct bcm2835_host { -+ spinlock_t lock; -+ -+ void __iomem *ioaddr; -+ u32 phys_addr; -+ -+ struct mmc_host *mmc; -+ -+ u32 timeout; -+ -+ int clock; /* Current clock speed */ -+ u8 pwr; /* Current voltage */ -+ -+ unsigned int max_clk; /* Max possible freq */ -+ unsigned int timeout_clk; /* Timeout freq (KHz) */ -+ unsigned int clk_mul; /* Clock Muliplier value */ -+ -+ struct tasklet_struct finish_tasklet; /* Tasklet structures */ -+ -+ struct timer_list timer; /* Timer for timeouts */ -+ -+ struct sg_mapping_iter sg_miter; /* SG state for PIO */ -+ unsigned int blocks; /* remaining PIO blocks */ -+ -+ int irq; /* Device IRQ */ -+ -+ -+ u32 ier; /* cached registers */ -+ -+ struct mmc_request *mrq; /* Current request */ -+ struct mmc_command *cmd; /* Current command */ -+ struct mmc_data *data; /* Current data request */ -+ unsigned int data_early:1; /* Data finished before cmd */ -+ -+ wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */ -+ -+ u32 thread_isr; -+ -+ u32 shadow; -+ -+ /*DMA part*/ -+ struct dma_chan *dma_chan_rx; /* DMA channel for reads */ -+ struct dma_chan *dma_chan_tx; /* DMA channel for writes */ -+ struct dma_async_tx_descriptor *tx_desc; /* descriptor */ -+ -+ bool have_dma; -+ bool use_dma; -+ /*end of DMA part*/ -+ -+ int max_delay; /* maximum length of time spent waiting */ -+ -+ int flags; /* Host attributes */ -+#define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */ -+#define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */ -+#define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */ -+#define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */ -+#define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */ -+ -+ u32 overclock_50; /* frequency to use when 50MHz is requested (in MHz) */ -+ u32 max_overclock; /* Highest reported */ -+}; -+ -+ -+static inline void bcm2835_mmc_writel(struct bcm2835_host *host, u32 val, int reg, int from) -+{ -+ unsigned delay; -+ lockdep_assert_held_once(&host->lock); -+ writel(val, host->ioaddr + reg); -+ udelay(BCM2835_SDHCI_WRITE_DELAY(max(host->clock, MIN_FREQ))); -+ -+ delay = ((mmc_debug >> 16) & 0xf) << ((mmc_debug >> 20) & 0xf); -+ if (delay && !((1<lock); -+ writel(val, host->ioaddr + reg); -+ -+ delay = ((mmc_debug >> 24) & 0xf) << ((mmc_debug >> 28) & 0xf); -+ if (delay) -+ udelay(delay); -+} -+ -+static inline u32 bcm2835_mmc_readl(struct bcm2835_host *host, int reg) -+{ -+ lockdep_assert_held_once(&host->lock); -+ return readl(host->ioaddr + reg); -+} -+ -+static inline void bcm2835_mmc_writew(struct bcm2835_host *host, u16 val, int reg) -+{ -+ u32 oldval = (reg == SDHCI_COMMAND) ? host->shadow : -+ bcm2835_mmc_readl(host, reg & ~3); -+ u32 word_num = (reg >> 1) & 1; -+ u32 word_shift = word_num * 16; -+ u32 mask = 0xffff << word_shift; -+ u32 newval = (oldval & ~mask) | (val << word_shift); -+ -+ if (reg == SDHCI_TRANSFER_MODE) -+ host->shadow = newval; -+ else -+ bcm2835_mmc_writel(host, newval, reg & ~3, 0); -+ -+} -+ -+static inline void bcm2835_mmc_writeb(struct bcm2835_host *host, u8 val, int reg) -+{ -+ u32 oldval = bcm2835_mmc_readl(host, reg & ~3); -+ u32 byte_num = reg & 3; -+ u32 byte_shift = byte_num * 8; -+ u32 mask = 0xff << byte_shift; -+ u32 newval = (oldval & ~mask) | (val << byte_shift); -+ -+ bcm2835_mmc_writel(host, newval, reg & ~3, 1); -+} -+ -+ -+static inline u16 bcm2835_mmc_readw(struct bcm2835_host *host, int reg) -+{ -+ u32 val = bcm2835_mmc_readl(host, (reg & ~3)); -+ u32 word_num = (reg >> 1) & 1; -+ u32 word_shift = word_num * 16; -+ u32 word = (val >> word_shift) & 0xffff; -+ -+ return word; -+} -+ -+static inline u8 bcm2835_mmc_readb(struct bcm2835_host *host, int reg) -+{ -+ u32 val = bcm2835_mmc_readl(host, (reg & ~3)); -+ u32 byte_num = reg & 3; -+ u32 byte_shift = byte_num * 8; -+ u32 byte = (val >> byte_shift) & 0xff; -+ -+ return byte; -+} -+ -+static void bcm2835_mmc_unsignal_irqs(struct bcm2835_host *host, u32 clear) -+{ -+ u32 ier; -+ -+ ier = bcm2835_mmc_readl(host, SDHCI_SIGNAL_ENABLE); -+ ier &= ~clear; -+ /* change which requests generate IRQs - makes no difference to -+ the content of SDHCI_INT_STATUS, or the need to acknowledge IRQs */ -+ bcm2835_mmc_writel(host, ier, SDHCI_SIGNAL_ENABLE, 2); -+} -+ -+ -+static void bcm2835_mmc_dumpregs(struct bcm2835_host *host) -+{ -+ pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", -+ mmc_hostname(host->mmc)); -+ -+ pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", -+ bcm2835_mmc_readl(host, SDHCI_DMA_ADDRESS), -+ bcm2835_mmc_readw(host, SDHCI_HOST_VERSION)); -+ pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", -+ bcm2835_mmc_readw(host, SDHCI_BLOCK_SIZE), -+ bcm2835_mmc_readw(host, SDHCI_BLOCK_COUNT)); -+ pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", -+ bcm2835_mmc_readl(host, SDHCI_ARGUMENT), -+ bcm2835_mmc_readw(host, SDHCI_TRANSFER_MODE)); -+ pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", -+ bcm2835_mmc_readl(host, SDHCI_PRESENT_STATE), -+ bcm2835_mmc_readb(host, SDHCI_HOST_CONTROL)); -+ pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", -+ bcm2835_mmc_readb(host, SDHCI_POWER_CONTROL), -+ bcm2835_mmc_readb(host, SDHCI_BLOCK_GAP_CONTROL)); -+ pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", -+ bcm2835_mmc_readb(host, SDHCI_WAKE_UP_CONTROL), -+ bcm2835_mmc_readw(host, SDHCI_CLOCK_CONTROL)); -+ pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", -+ bcm2835_mmc_readb(host, SDHCI_TIMEOUT_CONTROL), -+ bcm2835_mmc_readl(host, SDHCI_INT_STATUS)); -+ pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", -+ bcm2835_mmc_readl(host, SDHCI_INT_ENABLE), -+ bcm2835_mmc_readl(host, SDHCI_SIGNAL_ENABLE)); -+ pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", -+ bcm2835_mmc_readw(host, SDHCI_ACMD12_ERR), -+ bcm2835_mmc_readw(host, SDHCI_SLOT_INT_STATUS)); -+ pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", -+ bcm2835_mmc_readl(host, SDHCI_CAPABILITIES), -+ bcm2835_mmc_readl(host, SDHCI_CAPABILITIES_1)); -+ pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", -+ bcm2835_mmc_readw(host, SDHCI_COMMAND), -+ bcm2835_mmc_readl(host, SDHCI_MAX_CURRENT)); -+ pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n", -+ bcm2835_mmc_readw(host, SDHCI_HOST_CONTROL2)); -+ -+ pr_debug(DRIVER_NAME ": ===========================================\n"); -+} -+ -+ -+static void bcm2835_mmc_reset(struct bcm2835_host *host, u8 mask) -+{ -+ unsigned long timeout; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&host->lock, flags); -+ bcm2835_mmc_writeb(host, mask, SDHCI_SOFTWARE_RESET); -+ -+ if (mask & SDHCI_RESET_ALL) -+ host->clock = 0; -+ -+ /* Wait max 100 ms */ -+ timeout = 100; -+ -+ /* hw clears the bit when it's done */ -+ while (bcm2835_mmc_readb(host, SDHCI_SOFTWARE_RESET) & mask) { -+ if (timeout == 0) { -+ pr_err("%s: Reset 0x%x never completed.\n", -+ mmc_hostname(host->mmc), (int)mask); -+ bcm2835_mmc_dumpregs(host); -+ return; -+ } -+ timeout--; -+ spin_unlock_irqrestore(&host->lock, flags); -+ mdelay(1); -+ spin_lock_irqsave(&host->lock, flags); -+ } -+ -+ if (100-timeout > 10 && 100-timeout > host->max_delay) { -+ host->max_delay = 100-timeout; -+ pr_warning("Warning: MMC controller hung for %d ms\n", host->max_delay); -+ } -+ spin_unlock_irqrestore(&host->lock, flags); -+} -+ -+static void bcm2835_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); -+ -+static void bcm2835_mmc_init(struct bcm2835_host *host, int soft) -+{ -+ unsigned long flags; -+ if (soft) -+ bcm2835_mmc_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); -+ else -+ bcm2835_mmc_reset(host, SDHCI_RESET_ALL); -+ -+ host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | -+ SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | -+ SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | -+ SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END | -+ SDHCI_INT_RESPONSE; -+ -+ spin_lock_irqsave(&host->lock, flags); -+ bcm2835_mmc_writel(host, host->ier, SDHCI_INT_ENABLE, 3); -+ bcm2835_mmc_writel(host, host->ier, SDHCI_SIGNAL_ENABLE, 3); -+ spin_unlock_irqrestore(&host->lock, flags); -+ -+ if (soft) { -+ /* force clock reconfiguration */ -+ host->clock = 0; -+ bcm2835_mmc_set_ios(host->mmc, &host->mmc->ios); -+ } -+} -+ -+ -+ -+static void bcm2835_mmc_finish_data(struct bcm2835_host *host); -+ -+static void bcm2835_mmc_dma_complete(void *param) -+{ -+ struct bcm2835_host *host = param; -+ struct dma_chan *dma_chan; -+ unsigned long flags; -+ u32 dir_data; -+ -+ spin_lock_irqsave(&host->lock, flags); -+ -+ if (host->data && !(host->data->flags & MMC_DATA_WRITE)) { -+ /* otherwise handled in SDHCI IRQ */ -+ dma_chan = host->dma_chan_rx; -+ dir_data = DMA_FROM_DEVICE; -+ -+ dma_unmap_sg(dma_chan->device->dev, -+ host->data->sg, host->data->sg_len, -+ dir_data); -+ -+ bcm2835_mmc_finish_data(host); -+ } -+ -+ spin_unlock_irqrestore(&host->lock, flags); -+} -+ -+static void bcm2835_bcm2835_mmc_read_block_pio(struct bcm2835_host *host) -+{ -+ unsigned long flags; -+ size_t blksize, len, chunk; -+ -+ u32 uninitialized_var(scratch); -+ u8 *buf; -+ -+ blksize = host->data->blksz; -+ chunk = 0; -+ -+ local_irq_save(flags); -+ -+ while (blksize) { -+ if (!sg_miter_next(&host->sg_miter)) -+ BUG(); -+ -+ len = min(host->sg_miter.length, blksize); -+ -+ blksize -= len; -+ host->sg_miter.consumed = len; -+ -+ buf = host->sg_miter.addr; -+ -+ while (len) { -+ if (chunk == 0) { -+ scratch = bcm2835_mmc_readl(host, SDHCI_BUFFER); -+ chunk = 4; -+ } -+ -+ *buf = scratch & 0xFF; -+ -+ buf++; -+ scratch >>= 8; -+ chunk--; -+ len--; -+ } -+ } -+ -+ sg_miter_stop(&host->sg_miter); -+ -+ local_irq_restore(flags); -+} -+ -+static void bcm2835_bcm2835_mmc_write_block_pio(struct bcm2835_host *host) -+{ -+ unsigned long flags; -+ size_t blksize, len, chunk; -+ u32 scratch; -+ u8 *buf; -+ -+ blksize = host->data->blksz; -+ chunk = 0; -+ chunk = 0; -+ scratch = 0; -+ -+ local_irq_save(flags); -+ -+ while (blksize) { -+ if (!sg_miter_next(&host->sg_miter)) -+ BUG(); -+ -+ len = min(host->sg_miter.length, blksize); -+ -+ blksize -= len; -+ host->sg_miter.consumed = len; -+ -+ buf = host->sg_miter.addr; -+ -+ while (len) { -+ scratch |= (u32)*buf << (chunk * 8); -+ -+ buf++; -+ chunk++; -+ len--; -+ -+ if ((chunk == 4) || ((len == 0) && (blksize == 0))) { -+ mmc_raw_writel(host, scratch, SDHCI_BUFFER); -+ chunk = 0; -+ scratch = 0; -+ } -+ } -+ } -+ -+ sg_miter_stop(&host->sg_miter); -+ -+ local_irq_restore(flags); -+} -+ -+ -+static void bcm2835_mmc_transfer_pio(struct bcm2835_host *host) -+{ -+ u32 mask; -+ -+ BUG_ON(!host->data); -+ -+ if (host->blocks == 0) -+ return; -+ -+ if (host->data->flags & MMC_DATA_READ) -+ mask = SDHCI_DATA_AVAILABLE; -+ else -+ mask = SDHCI_SPACE_AVAILABLE; -+ -+ while (bcm2835_mmc_readl(host, SDHCI_PRESENT_STATE) & mask) { -+ -+ if (host->data->flags & MMC_DATA_READ) -+ bcm2835_bcm2835_mmc_read_block_pio(host); -+ else -+ bcm2835_bcm2835_mmc_write_block_pio(host); -+ -+ host->blocks--; -+ -+ /* QUIRK used in sdhci.c removes the 'if' */ -+ /* but it seems this is unnecessary */ -+ if (host->blocks == 0) -+ break; -+ -+ -+ } -+} -+ -+ -+static void bcm2835_mmc_transfer_dma(struct bcm2835_host *host) -+{ -+ u32 len, dir_data, dir_slave; -+ struct dma_async_tx_descriptor *desc = NULL; -+ struct dma_chan *dma_chan; -+ -+ -+ WARN_ON(!host->data); -+ -+ if (!host->data) -+ return; -+ -+ if (host->blocks == 0) -+ return; -+ -+ if (host->data->flags & MMC_DATA_READ) { -+ dma_chan = host->dma_chan_rx; -+ dir_data = DMA_FROM_DEVICE; -+ dir_slave = DMA_DEV_TO_MEM; -+ } else { -+ dma_chan = host->dma_chan_tx; -+ dir_data = DMA_TO_DEVICE; -+ dir_slave = DMA_MEM_TO_DEV; -+ } -+ -+ BUG_ON(!dma_chan->device); -+ BUG_ON(!dma_chan->device->dev); -+ BUG_ON(!host->data->sg); -+ -+ len = dma_map_sg(dma_chan->device->dev, host->data->sg, -+ host->data->sg_len, dir_data); -+ if (len > 0) { -+ desc = dmaengine_prep_slave_sg(dma_chan, host->data->sg, -+ len, dir_slave, -+ DMA_PREP_INTERRUPT | DMA_CTRL_ACK); -+ } else { -+ dev_err(mmc_dev(host->mmc), "dma_map_sg returned zero length\n"); -+ } -+ if (desc) { -+ unsigned long flags; -+ spin_lock_irqsave(&host->lock, flags); -+ bcm2835_mmc_unsignal_irqs(host, SDHCI_INT_DATA_AVAIL | -+ SDHCI_INT_SPACE_AVAIL); -+ host->tx_desc = desc; -+ desc->callback = bcm2835_mmc_dma_complete; -+ desc->callback_param = host; -+ spin_unlock_irqrestore(&host->lock, flags); -+ dmaengine_submit(desc); -+ dma_async_issue_pending(dma_chan); -+ } -+ -+} -+ -+ -+ -+static void bcm2835_mmc_set_transfer_irqs(struct bcm2835_host *host) -+{ -+ u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; -+ u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; -+ -+ if (host->use_dma) -+ host->ier = (host->ier & ~pio_irqs) | dma_irqs; -+ else -+ host->ier = (host->ier & ~dma_irqs) | pio_irqs; -+ -+ bcm2835_mmc_writel(host, host->ier, SDHCI_INT_ENABLE, 4); -+ bcm2835_mmc_writel(host, host->ier, SDHCI_SIGNAL_ENABLE, 4); -+} -+ -+ -+static void bcm2835_mmc_prepare_data(struct bcm2835_host *host, struct mmc_command *cmd) -+{ -+ u8 count; -+ struct mmc_data *data = cmd->data; -+ -+ WARN_ON(host->data); -+ -+ if (data || (cmd->flags & MMC_RSP_BUSY)) { -+ count = TIMEOUT_VAL; -+ bcm2835_mmc_writeb(host, count, SDHCI_TIMEOUT_CONTROL); -+ } -+ -+ if (!data) -+ return; -+ -+ /* Sanity checks */ -+ BUG_ON(data->blksz * data->blocks > 524288); -+ BUG_ON(data->blksz > host->mmc->max_blk_size); -+ BUG_ON(data->blocks > 65535); -+ -+ host->data = data; -+ host->data_early = 0; -+ host->data->bytes_xfered = 0; -+ -+ -+ if (!(host->flags & SDHCI_REQ_USE_DMA)) { -+ int flags; -+ -+ flags = SG_MITER_ATOMIC; -+ if (host->data->flags & MMC_DATA_READ) -+ flags |= SG_MITER_TO_SG; -+ else -+ flags |= SG_MITER_FROM_SG; -+ sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); -+ host->blocks = data->blocks; -+ } -+ -+ host->use_dma = host->have_dma && data->blocks > PIO_DMA_BARRIER; -+ -+ bcm2835_mmc_set_transfer_irqs(host); -+ -+ /* Set the DMA boundary value and block size */ -+ bcm2835_mmc_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, -+ data->blksz), SDHCI_BLOCK_SIZE); -+ bcm2835_mmc_writew(host, data->blocks, SDHCI_BLOCK_COUNT); -+ -+ BUG_ON(!host->data); -+} -+ -+static void bcm2835_mmc_set_transfer_mode(struct bcm2835_host *host, -+ struct mmc_command *cmd) -+{ -+ u16 mode; -+ struct mmc_data *data = cmd->data; -+ -+ if (data == NULL) { -+ /* clear Auto CMD settings for no data CMDs */ -+ mode = bcm2835_mmc_readw(host, SDHCI_TRANSFER_MODE); -+ bcm2835_mmc_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 | -+ SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE); -+ return; -+ } -+ -+ WARN_ON(!host->data); -+ -+ mode = SDHCI_TRNS_BLK_CNT_EN; -+ -+ if ((mmc_op_multi(cmd->opcode) || data->blocks > 1)) { -+ mode |= SDHCI_TRNS_MULTI; -+ -+ /* -+ * If we are sending CMD23, CMD12 never gets sent -+ * on successful completion (so no Auto-CMD12). -+ */ -+ if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) -+ mode |= SDHCI_TRNS_AUTO_CMD12; -+ else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { -+ mode |= SDHCI_TRNS_AUTO_CMD23; -+ bcm2835_mmc_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2, 5); -+ } -+ } -+ -+ if (data->flags & MMC_DATA_READ) -+ mode |= SDHCI_TRNS_READ; -+ if (host->flags & SDHCI_REQ_USE_DMA) -+ mode |= SDHCI_TRNS_DMA; -+ -+ bcm2835_mmc_writew(host, mode, SDHCI_TRANSFER_MODE); -+} -+ -+void bcm2835_mmc_send_command(struct bcm2835_host *host, struct mmc_command *cmd) -+{ -+ int flags; -+ u32 mask; -+ unsigned long timeout; -+ -+ WARN_ON(host->cmd); -+ -+ /* Wait max 10 ms */ -+ timeout = 1000; -+ -+ mask = SDHCI_CMD_INHIBIT; -+ if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) -+ mask |= SDHCI_DATA_INHIBIT; -+ -+ /* We shouldn't wait for data inihibit for stop commands, even -+ though they might use busy signaling */ -+ if (host->mrq->data && (cmd == host->mrq->data->stop)) -+ mask &= ~SDHCI_DATA_INHIBIT; -+ -+ while (bcm2835_mmc_readl(host, SDHCI_PRESENT_STATE) & mask) { -+ if (timeout == 0) { -+ pr_err("%s: Controller never released inhibit bit(s).\n", -+ mmc_hostname(host->mmc)); -+ bcm2835_mmc_dumpregs(host); -+ cmd->error = -EIO; -+ tasklet_schedule(&host->finish_tasklet); -+ return; -+ } -+ timeout--; -+ udelay(10); -+ } -+ -+ if ((1000-timeout)/100 > 1 && (1000-timeout)/100 > host->max_delay) { -+ host->max_delay = (1000-timeout)/100; -+ pr_warning("Warning: MMC controller hung for %d ms\n", host->max_delay); -+ } -+ -+ timeout = jiffies; -+#ifdef CONFIG_ARCH_BCM2835 -+ if (!cmd->data && cmd->busy_timeout > 9000) -+ timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; -+ else -+#endif -+ timeout += 10 * HZ; -+ mod_timer(&host->timer, timeout); -+ -+ host->cmd = cmd; -+ -+ bcm2835_mmc_prepare_data(host, cmd); -+ -+ bcm2835_mmc_writel(host, cmd->arg, SDHCI_ARGUMENT, 6); -+ -+ bcm2835_mmc_set_transfer_mode(host, cmd); -+ -+ if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { -+ pr_err("%s: Unsupported response type!\n", -+ mmc_hostname(host->mmc)); -+ cmd->error = -EINVAL; -+ tasklet_schedule(&host->finish_tasklet); -+ return; -+ } -+ -+ if (!(cmd->flags & MMC_RSP_PRESENT)) -+ flags = SDHCI_CMD_RESP_NONE; -+ else if (cmd->flags & MMC_RSP_136) -+ flags = SDHCI_CMD_RESP_LONG; -+ else if (cmd->flags & MMC_RSP_BUSY) -+ flags = SDHCI_CMD_RESP_SHORT_BUSY; -+ else -+ flags = SDHCI_CMD_RESP_SHORT; -+ -+ if (cmd->flags & MMC_RSP_CRC) -+ flags |= SDHCI_CMD_CRC; -+ if (cmd->flags & MMC_RSP_OPCODE) -+ flags |= SDHCI_CMD_INDEX; -+ -+ if (cmd->data) -+ flags |= SDHCI_CMD_DATA; -+ -+ bcm2835_mmc_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); -+} -+ -+ -+static void bcm2835_mmc_finish_data(struct bcm2835_host *host) -+{ -+ struct mmc_data *data; -+ -+ BUG_ON(!host->data); -+ -+ data = host->data; -+ host->data = NULL; -+ -+ if (data->error) -+ data->bytes_xfered = 0; -+ else -+ data->bytes_xfered = data->blksz * data->blocks; -+ -+ /* -+ * Need to send CMD12 if - -+ * a) open-ended multiblock transfer (no CMD23) -+ * b) error in multiblock transfer -+ */ -+ if (data->stop && -+ (data->error || -+ !host->mrq->sbc)) { -+ -+ /* -+ * The controller needs a reset of internal state machines -+ * upon error conditions. -+ */ -+ if (data->error) { -+ bcm2835_mmc_reset(host, SDHCI_RESET_CMD); -+ bcm2835_mmc_reset(host, SDHCI_RESET_DATA); -+ } -+ -+ bcm2835_mmc_send_command(host, data->stop); -+ } else -+ tasklet_schedule(&host->finish_tasklet); -+} -+ -+static void bcm2835_mmc_finish_command(struct bcm2835_host *host) -+{ -+ int i; -+ -+ BUG_ON(host->cmd == NULL); -+ -+ if (host->cmd->flags & MMC_RSP_PRESENT) { -+ if (host->cmd->flags & MMC_RSP_136) { -+ /* CRC is stripped so we need to do some shifting. */ -+ for (i = 0; i < 4; i++) { -+ host->cmd->resp[i] = bcm2835_mmc_readl(host, -+ SDHCI_RESPONSE + (3-i)*4) << 8; -+ if (i != 3) -+ host->cmd->resp[i] |= -+ bcm2835_mmc_readb(host, -+ SDHCI_RESPONSE + (3-i)*4-1); -+ } -+ } else { -+ host->cmd->resp[0] = bcm2835_mmc_readl(host, SDHCI_RESPONSE); -+ } -+ } -+ -+ host->cmd->error = 0; -+ -+ /* Finished CMD23, now send actual command. */ -+ if (host->cmd == host->mrq->sbc) { -+ host->cmd = NULL; -+ bcm2835_mmc_send_command(host, host->mrq->cmd); -+ -+ if (host->mrq->cmd->data && host->use_dma) { -+ /* DMA transfer starts now, PIO starts after interrupt */ -+ bcm2835_mmc_transfer_dma(host); -+ } -+ } else { -+ -+ /* Processed actual command. */ -+ if (host->data && host->data_early) -+ bcm2835_mmc_finish_data(host); -+ -+ if (!host->cmd->data) -+ tasklet_schedule(&host->finish_tasklet); -+ -+ host->cmd = NULL; -+ } -+} -+ -+ -+static void bcm2835_mmc_timeout_timer(unsigned long data) -+{ -+ struct bcm2835_host *host; -+ unsigned long flags; -+ -+ host = (struct bcm2835_host *)data; -+ -+ spin_lock_irqsave(&host->lock, flags); -+ -+ if (host->mrq) { -+ pr_err("%s: Timeout waiting for hardware interrupt.\n", -+ mmc_hostname(host->mmc)); -+ bcm2835_mmc_dumpregs(host); -+ -+ if (host->data) { -+ host->data->error = -ETIMEDOUT; -+ bcm2835_mmc_finish_data(host); -+ } else { -+ if (host->cmd) -+ host->cmd->error = -ETIMEDOUT; -+ else -+ host->mrq->cmd->error = -ETIMEDOUT; -+ -+ tasklet_schedule(&host->finish_tasklet); -+ } -+ } -+ -+ mmiowb(); -+ spin_unlock_irqrestore(&host->lock, flags); -+} -+ -+ -+static void bcm2835_mmc_enable_sdio_irq_nolock(struct bcm2835_host *host, int enable) -+{ -+ if (!(host->flags & SDHCI_DEVICE_DEAD)) { -+ if (enable) -+ host->ier |= SDHCI_INT_CARD_INT; -+ else -+ host->ier &= ~SDHCI_INT_CARD_INT; -+ -+ bcm2835_mmc_writel(host, host->ier, SDHCI_INT_ENABLE, 7); -+ bcm2835_mmc_writel(host, host->ier, SDHCI_SIGNAL_ENABLE, 7); -+ mmiowb(); -+ } -+} -+ -+static void bcm2835_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) -+{ -+ struct bcm2835_host *host = mmc_priv(mmc); -+ unsigned long flags; -+ -+ spin_lock_irqsave(&host->lock, flags); -+ if (enable) -+ host->flags |= SDHCI_SDIO_IRQ_ENABLED; -+ else -+ host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; -+ -+ bcm2835_mmc_enable_sdio_irq_nolock(host, enable); -+ spin_unlock_irqrestore(&host->lock, flags); -+} -+ -+static void bcm2835_mmc_cmd_irq(struct bcm2835_host *host, u32 intmask) -+{ -+ -+ BUG_ON(intmask == 0); -+ -+ if (!host->cmd) { -+ pr_err("%s: Got command interrupt 0x%08x even " -+ "though no command operation was in progress.\n", -+ mmc_hostname(host->mmc), (unsigned)intmask); -+ bcm2835_mmc_dumpregs(host); -+ return; -+ } -+ -+ if (intmask & SDHCI_INT_TIMEOUT) -+ host->cmd->error = -ETIMEDOUT; -+ else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT | -+ SDHCI_INT_INDEX)) { -+ host->cmd->error = -EILSEQ; -+ } -+ -+ if (host->cmd->error) { -+ tasklet_schedule(&host->finish_tasklet); -+ return; -+ } -+ -+ if (intmask & SDHCI_INT_RESPONSE) -+ bcm2835_mmc_finish_command(host); -+ -+} -+ -+static void bcm2835_mmc_data_irq(struct bcm2835_host *host, u32 intmask) -+{ -+ struct dma_chan *dma_chan; -+ u32 dir_data; -+ -+ BUG_ON(intmask == 0); -+ -+ if (!host->data) { -+ /* -+ * The "data complete" interrupt is also used to -+ * indicate that a busy state has ended. See comment -+ * above in sdhci_cmd_irq(). -+ */ -+ if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { -+ if (intmask & SDHCI_INT_DATA_END) { -+ bcm2835_mmc_finish_command(host); -+ return; -+ } -+ } -+ -+ pr_debug("%s: Got data interrupt 0x%08x even " -+ "though no data operation was in progress.\n", -+ mmc_hostname(host->mmc), (unsigned)intmask); -+ bcm2835_mmc_dumpregs(host); -+ -+ return; -+ } -+ -+ if (intmask & SDHCI_INT_DATA_TIMEOUT) -+ host->data->error = -ETIMEDOUT; -+ else if (intmask & SDHCI_INT_DATA_END_BIT) -+ host->data->error = -EILSEQ; -+ else if ((intmask & SDHCI_INT_DATA_CRC) && -+ SDHCI_GET_CMD(bcm2835_mmc_readw(host, SDHCI_COMMAND)) -+ != MMC_BUS_TEST_R) -+ host->data->error = -EILSEQ; -+ -+ if (host->use_dma) { -+ if (host->data->flags & MMC_DATA_WRITE) { -+ /* IRQ handled here */ -+ -+ dma_chan = host->dma_chan_tx; -+ dir_data = DMA_TO_DEVICE; -+ dma_unmap_sg(dma_chan->device->dev, -+ host->data->sg, host->data->sg_len, -+ dir_data); -+ -+ bcm2835_mmc_finish_data(host); -+ } -+ -+ } else { -+ if (host->data->error) -+ bcm2835_mmc_finish_data(host); -+ else { -+ if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) -+ bcm2835_mmc_transfer_pio(host); -+ -+ if (intmask & SDHCI_INT_DATA_END) { -+ if (host->cmd) { -+ /* -+ * Data managed to finish before the -+ * command completed. Make sure we do -+ * things in the proper order. -+ */ -+ host->data_early = 1; -+ } else { -+ bcm2835_mmc_finish_data(host); -+ } -+ } -+ } -+ } -+} -+ -+ -+static irqreturn_t bcm2835_mmc_irq(int irq, void *dev_id) -+{ -+ irqreturn_t result = IRQ_NONE; -+ struct bcm2835_host *host = dev_id; -+ u32 intmask, mask, unexpected = 0; -+ int max_loops = 16; -+#ifndef CONFIG_ARCH_BCM2835 -+ int cardint = 0; -+#endif -+ -+ spin_lock(&host->lock); -+ -+ intmask = bcm2835_mmc_readl(host, SDHCI_INT_STATUS); -+ -+ if (!intmask || intmask == 0xffffffff) { -+ result = IRQ_NONE; -+ goto out; -+ } -+ -+ do { -+ /* Clear selected interrupts. */ -+ mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | -+ SDHCI_INT_BUS_POWER); -+ bcm2835_mmc_writel(host, mask, SDHCI_INT_STATUS, 8); -+ -+ -+ if (intmask & SDHCI_INT_CMD_MASK) -+ bcm2835_mmc_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); -+ -+ if (intmask & SDHCI_INT_DATA_MASK) -+ bcm2835_mmc_data_irq(host, intmask & SDHCI_INT_DATA_MASK); -+ -+ if (intmask & SDHCI_INT_BUS_POWER) -+ pr_err("%s: Card is consuming too much power!\n", -+ mmc_hostname(host->mmc)); -+ -+ if (intmask & SDHCI_INT_CARD_INT) { -+#ifndef CONFIG_ARCH_BCM2835 -+ cardint = 1; -+#else -+ bcm2835_mmc_enable_sdio_irq_nolock(host, false); -+ host->thread_isr |= SDHCI_INT_CARD_INT; -+ result = IRQ_WAKE_THREAD; -+#endif -+ } -+ -+ intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | -+ SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | -+ SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER | -+ SDHCI_INT_CARD_INT); -+ -+ if (intmask) { -+ unexpected |= intmask; -+ bcm2835_mmc_writel(host, intmask, SDHCI_INT_STATUS, 9); -+ } -+ -+ if (result == IRQ_NONE) -+ result = IRQ_HANDLED; -+ -+ intmask = bcm2835_mmc_readl(host, SDHCI_INT_STATUS); -+ } while (intmask && --max_loops); -+out: -+ spin_unlock(&host->lock); -+ -+ if (unexpected) { -+ pr_err("%s: Unexpected interrupt 0x%08x.\n", -+ mmc_hostname(host->mmc), unexpected); -+ bcm2835_mmc_dumpregs(host); -+ } -+ -+#ifndef CONFIG_ARCH_BCM2835 -+ if (cardint) -+ mmc_signal_sdio_irq(host->mmc); -+#endif -+ -+ return result; -+} -+ -+#ifdef CONFIG_ARCH_BCM2835 -+static irqreturn_t bcm2835_mmc_thread_irq(int irq, void *dev_id) -+{ -+ struct bcm2835_host *host = dev_id; -+ unsigned long flags; -+ u32 isr; -+ -+ spin_lock_irqsave(&host->lock, flags); -+ isr = host->thread_isr; -+ host->thread_isr = 0; -+ spin_unlock_irqrestore(&host->lock, flags); -+ -+ if (isr & SDHCI_INT_CARD_INT) { -+ sdio_run_irqs(host->mmc); -+ -+ spin_lock_irqsave(&host->lock, flags); -+ if (host->flags & SDHCI_SDIO_IRQ_ENABLED) -+ bcm2835_mmc_enable_sdio_irq_nolock(host, true); -+ spin_unlock_irqrestore(&host->lock, flags); -+ } -+ -+ return isr ? IRQ_HANDLED : IRQ_NONE; -+} -+#endif -+ -+ -+ -+void bcm2835_mmc_set_clock(struct bcm2835_host *host, unsigned int clock) -+{ -+ int div = 0; /* Initialized for compiler warning */ -+ int real_div = div, clk_mul = 1; -+ u16 clk = 0; -+ unsigned long timeout; -+ unsigned int input_clock = clock; -+ -+ if (host->overclock_50 && (clock == 50000000)) -+ clock = host->overclock_50 * 1000000 + 999999; -+ -+ host->mmc->actual_clock = 0; -+ -+ bcm2835_mmc_writew(host, 0, SDHCI_CLOCK_CONTROL); -+ -+ if (clock == 0) -+ return; -+ -+ /* Version 3.00 divisors must be a multiple of 2. */ -+ if (host->max_clk <= clock) -+ div = 1; -+ else { -+ for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; -+ div += 2) { -+ if ((host->max_clk / div) <= clock) -+ break; -+ } -+ } -+ -+ real_div = div; -+ div >>= 1; -+ -+ if (real_div) -+ clock = (host->max_clk * clk_mul) / real_div; -+ host->mmc->actual_clock = clock; -+ -+ if ((clock > input_clock) && (clock > host->max_overclock)) { -+ pr_warn("%s: Overclocking to %dHz\n", -+ mmc_hostname(host->mmc), clock); -+ host->max_overclock = clock; -+ } -+ -+ clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; -+ clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) -+ << SDHCI_DIVIDER_HI_SHIFT; -+ clk |= SDHCI_CLOCK_INT_EN; -+ bcm2835_mmc_writew(host, clk, SDHCI_CLOCK_CONTROL); -+ -+ /* Wait max 20 ms */ -+ timeout = 20; -+ while (!((clk = bcm2835_mmc_readw(host, SDHCI_CLOCK_CONTROL)) -+ & SDHCI_CLOCK_INT_STABLE)) { -+ if (timeout == 0) { -+ pr_err("%s: Internal clock never " -+ "stabilised.\n", mmc_hostname(host->mmc)); -+ bcm2835_mmc_dumpregs(host); -+ return; -+ } -+ timeout--; -+ mdelay(1); -+ } -+ -+ if (20-timeout > 10 && 20-timeout > host->max_delay) { -+ host->max_delay = 20-timeout; -+ pr_warning("Warning: MMC controller hung for %d ms\n", host->max_delay); -+ } -+ -+ clk |= SDHCI_CLOCK_CARD_EN; -+ bcm2835_mmc_writew(host, clk, SDHCI_CLOCK_CONTROL); -+} -+ -+static void bcm2835_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) -+{ -+ struct bcm2835_host *host; -+ unsigned long flags; -+ -+ host = mmc_priv(mmc); -+ -+ spin_lock_irqsave(&host->lock, flags); -+ -+ WARN_ON(host->mrq != NULL); -+ -+ host->mrq = mrq; -+ -+ if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) -+ bcm2835_mmc_send_command(host, mrq->sbc); -+ else -+ bcm2835_mmc_send_command(host, mrq->cmd); -+ -+ mmiowb(); -+ spin_unlock_irqrestore(&host->lock, flags); -+ -+ if (!(mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) && mrq->cmd->data && host->use_dma) { -+ /* DMA transfer starts now, PIO starts after interrupt */ -+ bcm2835_mmc_transfer_dma(host); -+ } -+} -+ -+ -+static void bcm2835_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) -+{ -+ -+ struct bcm2835_host *host = mmc_priv(mmc); -+ unsigned long flags; -+ u8 ctrl; -+ u16 clk, ctrl_2; -+ -+ pr_debug("bcm2835_mmc_set_ios: clock %d, pwr %d, bus_width %d, timing %d, vdd %d, drv_type %d\n", -+ ios->clock, ios->power_mode, ios->bus_width, -+ ios->timing, ios->signal_voltage, ios->drv_type); -+ -+ spin_lock_irqsave(&host->lock, flags); -+ -+ if (!ios->clock || ios->clock != host->clock) { -+ bcm2835_mmc_set_clock(host, ios->clock); -+ host->clock = ios->clock; -+ } -+ -+ if (host->pwr != SDHCI_POWER_330) { -+ host->pwr = SDHCI_POWER_330; -+ bcm2835_mmc_writeb(host, SDHCI_POWER_330 | SDHCI_POWER_ON, SDHCI_POWER_CONTROL); -+ } -+ -+ ctrl = bcm2835_mmc_readb(host, SDHCI_HOST_CONTROL); -+ -+ /* set bus width */ -+ ctrl &= ~SDHCI_CTRL_8BITBUS; -+ if (ios->bus_width == MMC_BUS_WIDTH_4) -+ ctrl |= SDHCI_CTRL_4BITBUS; -+ else -+ ctrl &= ~SDHCI_CTRL_4BITBUS; -+ -+ ctrl &= ~SDHCI_CTRL_HISPD; /* NO_HISPD_BIT */ -+ -+ -+ bcm2835_mmc_writeb(host, ctrl, SDHCI_HOST_CONTROL); -+ /* -+ * We only need to set Driver Strength if the -+ * preset value enable is not set. -+ */ -+ ctrl_2 = bcm2835_mmc_readw(host, SDHCI_HOST_CONTROL2); -+ ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; -+ if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) -+ ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; -+ else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) -+ ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; -+ -+ bcm2835_mmc_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); -+ -+ /* Reset SD Clock Enable */ -+ clk = bcm2835_mmc_readw(host, SDHCI_CLOCK_CONTROL); -+ clk &= ~SDHCI_CLOCK_CARD_EN; -+ bcm2835_mmc_writew(host, clk, SDHCI_CLOCK_CONTROL); -+ -+ /* Re-enable SD Clock */ -+ bcm2835_mmc_set_clock(host, host->clock); -+ bcm2835_mmc_writeb(host, ctrl, SDHCI_HOST_CONTROL); -+ -+ mmiowb(); -+ -+ spin_unlock_irqrestore(&host->lock, flags); -+} -+ -+ -+static struct mmc_host_ops bcm2835_ops = { -+ .request = bcm2835_mmc_request, -+ .set_ios = bcm2835_mmc_set_ios, -+ .enable_sdio_irq = bcm2835_mmc_enable_sdio_irq, -+}; -+ -+ -+static void bcm2835_mmc_tasklet_finish(unsigned long param) -+{ -+ struct bcm2835_host *host; -+ unsigned long flags; -+ struct mmc_request *mrq; -+ -+ host = (struct bcm2835_host *)param; -+ -+ spin_lock_irqsave(&host->lock, flags); -+ -+ /* -+ * If this tasklet gets rescheduled while running, it will -+ * be run again afterwards but without any active request. -+ */ -+ if (!host->mrq) { -+ spin_unlock_irqrestore(&host->lock, flags); -+ return; -+ } -+ -+ del_timer(&host->timer); -+ -+ mrq = host->mrq; -+ -+ /* -+ * The controller needs a reset of internal state machines -+ * upon error conditions. -+ */ -+ if (!(host->flags & SDHCI_DEVICE_DEAD) && -+ ((mrq->cmd && mrq->cmd->error) || -+ (mrq->data && (mrq->data->error || -+ (mrq->data->stop && mrq->data->stop->error))))) { -+ -+ spin_unlock_irqrestore(&host->lock, flags); -+ bcm2835_mmc_reset(host, SDHCI_RESET_CMD); -+ bcm2835_mmc_reset(host, SDHCI_RESET_DATA); -+ spin_lock_irqsave(&host->lock, flags); -+ } -+ -+ host->mrq = NULL; -+ host->cmd = NULL; -+ host->data = NULL; -+ -+ mmiowb(); -+ -+ spin_unlock_irqrestore(&host->lock, flags); -+ mmc_request_done(host->mmc, mrq); -+} -+ -+ -+ -+static int bcm2835_mmc_add_host(struct bcm2835_host *host) -+{ -+ struct mmc_host *mmc = host->mmc; -+ struct device *dev = mmc->parent; -+#ifndef FORCE_PIO -+ struct dma_slave_config cfg; -+#endif -+ int ret; -+ -+ bcm2835_mmc_reset(host, SDHCI_RESET_ALL); -+ -+ host->clk_mul = 0; -+ -+ mmc->f_max = host->max_clk; -+ mmc->f_max = host->max_clk; -+ mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; -+ -+ /* SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK */ -+ host->timeout_clk = mmc->f_max / 1000; -+#ifdef CONFIG_ARCH_BCM2835 -+ mmc->max_busy_timeout = (1 << 27) / host->timeout_clk; -+#endif -+ /* host controller capabilities */ -+ mmc->caps |= MMC_CAP_CMD23 | MMC_CAP_ERASE | MMC_CAP_NEEDS_POLL | -+ MMC_CAP_SDIO_IRQ | MMC_CAP_SD_HIGHSPEED | -+ MMC_CAP_MMC_HIGHSPEED | MMC_CAP_4_BIT_DATA; -+ -+ host->flags = SDHCI_AUTO_CMD23; -+ -+ dev_info(dev, "mmc_debug:%x mmc_debug2:%x\n", mmc_debug, mmc_debug2); -+#ifdef FORCE_PIO -+ dev_info(dev, "Forcing PIO mode\n"); -+ host->have_dma = false; -+#else -+ if (IS_ERR_OR_NULL(host->dma_chan_tx) || -+ IS_ERR_OR_NULL(host->dma_chan_rx)) { -+ dev_err(dev, "%s: Unable to initialise DMA channels. Falling back to PIO\n", -+ DRIVER_NAME); -+ host->have_dma = false; -+ } else { -+ dev_info(dev, "DMA channels allocated"); -+ host->have_dma = true; -+ -+ cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; -+ cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; -+ cfg.slave_id = 11; /* DREQ channel */ -+ -+ cfg.direction = DMA_MEM_TO_DEV; -+ cfg.src_addr = 0; -+ cfg.dst_addr = host->phys_addr + SDHCI_BUFFER; -+ ret = dmaengine_slave_config(host->dma_chan_tx, &cfg); -+ -+ cfg.direction = DMA_DEV_TO_MEM; -+ cfg.src_addr = host->phys_addr + SDHCI_BUFFER; -+ cfg.dst_addr = 0; -+ ret = dmaengine_slave_config(host->dma_chan_rx, &cfg); -+ } -+#endif -+ mmc->max_segs = 128; -+ mmc->max_req_size = 524288; -+ mmc->max_seg_size = mmc->max_req_size; -+ mmc->max_blk_size = 512; -+ mmc->max_blk_count = 65535; -+ -+ /* report supported voltage ranges */ -+ mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; -+ -+ tasklet_init(&host->finish_tasklet, -+ bcm2835_mmc_tasklet_finish, (unsigned long)host); -+ -+ setup_timer(&host->timer, bcm2835_mmc_timeout_timer, (unsigned long)host); -+ init_waitqueue_head(&host->buf_ready_int); -+ -+ bcm2835_mmc_init(host, 0); -+#ifndef CONFIG_ARCH_BCM2835 -+ ret = devm_request_irq(dev, host->irq, bcm2835_mmc_irq, 0, -+ mmc_hostname(mmc), host); -+#else -+ ret = devm_request_threaded_irq(dev, host->irq, bcm2835_mmc_irq, -+ bcm2835_mmc_thread_irq, IRQF_SHARED, -+ mmc_hostname(mmc), host); -+#endif -+ if (ret) { -+ dev_err(dev, "Failed to request IRQ %d: %d\n", host->irq, ret); -+ goto untasklet; -+ } -+ -+ mmiowb(); -+ mmc_add_host(mmc); -+ -+ return 0; -+ -+untasklet: -+ tasklet_kill(&host->finish_tasklet); -+ -+ return ret; -+} -+ -+static int bcm2835_mmc_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct device_node *node = dev->of_node; -+ struct clk *clk; -+ struct resource *iomem; -+ struct bcm2835_host *host; -+ struct mmc_host *mmc; -+ int ret; -+ -+ mmc = mmc_alloc_host(sizeof(*host), dev); -+ if (!mmc) -+ return -ENOMEM; -+ -+ mmc->ops = &bcm2835_ops; -+ host = mmc_priv(mmc); -+ host->mmc = mmc; -+ host->timeout = msecs_to_jiffies(1000); -+ spin_lock_init(&host->lock); -+ -+ iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ host->ioaddr = devm_ioremap_resource(dev, iomem); -+ if (IS_ERR(host->ioaddr)) { -+ ret = PTR_ERR(host->ioaddr); -+ goto err; -+ } -+ -+ host->phys_addr = iomem->start + BCM2835_VCMMU_SHIFT; -+ -+#ifndef FORCE_PIO -+ if (node) { -+ host->dma_chan_tx = dma_request_slave_channel(dev, "tx"); -+ host->dma_chan_rx = dma_request_slave_channel(dev, "rx"); -+ } else { -+ dma_cap_mask_t mask; -+ -+ dma_cap_zero(mask); -+ /* we don't care about the channel, any would work */ -+ dma_cap_set(DMA_SLAVE, mask); -+ host->dma_chan_tx = dma_request_channel(mask, NULL, NULL); -+ host->dma_chan_rx = dma_request_channel(mask, NULL, NULL); -+ } -+#endif -+ clk = devm_clk_get(dev, NULL); -+ if (IS_ERR(clk)) { -+ dev_err(dev, "could not get clk\n"); -+ ret = PTR_ERR(clk); -+ goto err; -+ } -+ -+ host->max_clk = clk_get_rate(clk); -+ -+ host->irq = platform_get_irq(pdev, 0); -+ if (host->irq <= 0) { -+ dev_err(dev, "get IRQ failed\n"); -+ ret = -EINVAL; -+ goto err; -+ } -+ -+ if (node) { -+ mmc_of_parse(mmc); -+ -+ /* Read any custom properties */ -+ of_property_read_u32(node, -+ "brcm,overclock-50", -+ &host->overclock_50); -+ } else { -+ mmc->caps |= MMC_CAP_4_BIT_DATA; -+ } -+ -+ ret = bcm2835_mmc_add_host(host); -+ if (ret) -+ goto err; -+ -+ platform_set_drvdata(pdev, host); -+ -+ return 0; -+err: -+ mmc_free_host(mmc); -+ -+ return ret; -+} -+ -+static int bcm2835_mmc_remove(struct platform_device *pdev) -+{ -+ struct bcm2835_host *host = platform_get_drvdata(pdev); -+ unsigned long flags; -+ int dead; -+ u32 scratch; -+ -+ dead = 0; -+ scratch = bcm2835_mmc_readl(host, SDHCI_INT_STATUS); -+ if (scratch == (u32)-1) -+ dead = 1; -+ -+ -+ if (dead) { -+ spin_lock_irqsave(&host->lock, flags); -+ -+ host->flags |= SDHCI_DEVICE_DEAD; -+ -+ if (host->mrq) { -+ pr_err("%s: Controller removed during " -+ " transfer!\n", mmc_hostname(host->mmc)); -+ -+ host->mrq->cmd->error = -ENOMEDIUM; -+ tasklet_schedule(&host->finish_tasklet); -+ } -+ -+ spin_unlock_irqrestore(&host->lock, flags); -+ } -+ -+ mmc_remove_host(host->mmc); -+ -+ if (!dead) -+ bcm2835_mmc_reset(host, SDHCI_RESET_ALL); -+ -+ free_irq(host->irq, host); -+ -+ del_timer_sync(&host->timer); -+ -+ tasklet_kill(&host->finish_tasklet); -+ -+ mmc_free_host(host->mmc); -+ platform_set_drvdata(pdev, NULL); -+ -+ return 0; -+} -+ -+ -+static const struct of_device_id bcm2835_mmc_match[] = { -+ { .compatible = "brcm,bcm2835-mmc" }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, bcm2835_mmc_match); -+ -+ -+ -+static struct platform_driver bcm2835_mmc_driver = { -+ .probe = bcm2835_mmc_probe, -+ .remove = bcm2835_mmc_remove, -+ .driver = { -+ .name = DRIVER_NAME, -+ .owner = THIS_MODULE, -+ .of_match_table = bcm2835_mmc_match, -+ }, -+}; -+module_platform_driver(bcm2835_mmc_driver); -+ -+module_param(mmc_debug, uint, 0644); -+module_param(mmc_debug2, uint, 0644); -+MODULE_ALIAS("platform:mmc-bcm2835"); -+MODULE_DESCRIPTION("BCM2835 SDHCI driver"); -+MODULE_LICENSE("GPL v2"); -+MODULE_AUTHOR("Gellert Weisz"); -diff -Nur linux-4.1.13.orig/drivers/mmc/host/bcm2835-sdhost.c linux-rpi/drivers/mmc/host/bcm2835-sdhost.c ---- linux-4.1.13.orig/drivers/mmc/host/bcm2835-sdhost.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/mmc/host/bcm2835-sdhost.c 2015-11-29 09:42:38.087220413 +0100 -@@ -0,0 +1,1930 @@ -+/* -+ * BCM2835 SD host driver. -+ * -+ * Author: Phil Elwell -+ * Copyright 2015 -+ * -+ * Based on -+ * mmc-bcm2835.c by Gellert Weisz -+ * which is, in turn, based on -+ * sdhci-bcm2708.c by Broadcom -+ * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko -+ * sdhci.c and sdhci-pci.c by Pierre Ossman -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms and conditions of the GNU General Public License, -+ * version 2, as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -+ * more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program. If not, see . -+ */ -+ -+#define SAFE_READ_THRESHOLD 4 -+#define SAFE_WRITE_THRESHOLD 4 -+#define ALLOW_DMA 1 -+#define ALLOW_CMD23 0 -+#define ALLOW_FAST 1 -+#define USE_BLOCK_IRQ 1 -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define DRIVER_NAME "sdhost-bcm2835" -+ -+#define SDCMD 0x00 /* Command to SD card - 16 R/W */ -+#define SDARG 0x04 /* Argument to SD card - 32 R/W */ -+#define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */ -+#define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */ -+#define SDRSP0 0x10 /* SD card response (31:0) - 32 R */ -+#define SDRSP1 0x14 /* SD card response (63:32) - 32 R */ -+#define SDRSP2 0x18 /* SD card response (95:64) - 32 R */ -+#define SDRSP3 0x1c /* SD card response (127:96) - 32 R */ -+#define SDHSTS 0x20 /* SD host status - 11 R */ -+#define SDVDD 0x30 /* SD card power control - 1 R/W */ -+#define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */ -+#define SDHCFG 0x38 /* Host configuration - 2 R/W */ -+#define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */ -+#define SDDATA 0x40 /* Data to/from SD card - 32 R/W */ -+#define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */ -+ -+#define SDCMD_NEW_FLAG 0x8000 -+#define SDCMD_FAIL_FLAG 0x4000 -+#define SDCMD_BUSYWAIT 0x800 -+#define SDCMD_NO_RESPONSE 0x400 -+#define SDCMD_LONG_RESPONSE 0x200 -+#define SDCMD_WRITE_CMD 0x80 -+#define SDCMD_READ_CMD 0x40 -+#define SDCMD_CMD_MASK 0x3f -+ -+#define SDCDIV_MAX_CDIV 0x7ff -+ -+#define SDHSTS_BUSY_IRPT 0x400 -+#define SDHSTS_BLOCK_IRPT 0x200 -+#define SDHSTS_SDIO_IRPT 0x100 -+#define SDHSTS_REW_TIME_OUT 0x80 -+#define SDHSTS_CMD_TIME_OUT 0x40 -+#define SDHSTS_CRC16_ERROR 0x20 -+#define SDHSTS_CRC7_ERROR 0x10 -+#define SDHSTS_FIFO_ERROR 0x08 -+/* Reserved */ -+/* Reserved */ -+#define SDHSTS_DATA_FLAG 0x01 -+ -+#define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR|SDHSTS_CRC16_ERROR|SDHSTS_REW_TIME_OUT|SDHSTS_FIFO_ERROR) -+#define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT|SDHSTS_TRANSFER_ERROR_MASK) -+ -+#define SDHCFG_BUSY_IRPT_EN (1<<10) -+#define SDHCFG_BLOCK_IRPT_EN (1<<8) -+#define SDHCFG_SDIO_IRPT_EN (1<<5) -+#define SDHCFG_DATA_IRPT_EN (1<<4) -+#define SDHCFG_SLOW_CARD (1<<3) -+#define SDHCFG_WIDE_EXT_BUS (1<<2) -+#define SDHCFG_WIDE_INT_BUS (1<<1) -+#define SDHCFG_REL_CMD_LINE (1<<0) -+ -+#define SDEDM_FORCE_DATA_MODE (1<<19) -+#define SDEDM_CLOCK_PULSE (1<<20) -+#define SDEDM_BYPASS (1<<21) -+ -+#define SDEDM_WRITE_THRESHOLD_SHIFT 9 -+#define SDEDM_READ_THRESHOLD_SHIFT 14 -+#define SDEDM_THRESHOLD_MASK 0x1f -+ -+#define MHZ 1000000 -+ -+#ifndef BCM2708_PERI_BASE -+ #define BCM2708_PERI_BASE 0x20000000 -+#endif -+ -+/* FIXME: Needs IOMMU support */ -+#define BCM2835_VCMMU_SHIFT (0x7E000000 - BCM2708_PERI_BASE) -+ -+ -+struct bcm2835_host { -+ spinlock_t lock; -+ -+ void __iomem *ioaddr; -+ u32 phys_addr; -+ -+ struct mmc_host *mmc; -+ -+ u32 pio_timeout; /* In jiffies */ -+ -+ int clock; /* Current clock speed */ -+ -+ bool slow_card; /* Force 11-bit divisor */ -+ -+ unsigned int max_clk; /* Max possible freq */ -+ -+ struct tasklet_struct finish_tasklet; /* Tasklet structures */ -+ -+ struct timer_list timer; /* Timer for timeouts */ -+ -+ struct timer_list pio_timer; /* PIO error detection timer */ -+ -+ struct sg_mapping_iter sg_miter; /* SG state for PIO */ -+ unsigned int blocks; /* remaining PIO blocks */ -+ -+ int irq; /* Device IRQ */ -+ -+ -+ /* cached registers */ -+ u32 hcfg; -+ u32 cdiv; -+ -+ struct mmc_request *mrq; /* Current request */ -+ struct mmc_command *cmd; /* Current command */ -+ struct mmc_data *data; /* Current data request */ -+ unsigned int data_complete:1; /* Data finished before cmd */ -+ -+ unsigned int flush_fifo:1; /* Drain the fifo when finishing */ -+ -+ unsigned int use_busy:1; /* Wait for busy interrupt */ -+ -+ unsigned int debug:1; /* Enable debug output */ -+ -+ u32 thread_isr; -+ -+ /*DMA part*/ -+ struct dma_chan *dma_chan_rx; /* DMA channel for reads */ -+ struct dma_chan *dma_chan_tx; /* DMA channel for writes */ -+ -+ bool allow_dma; -+ bool have_dma; -+ bool use_dma; -+ /*end of DMA part*/ -+ -+ int max_delay; /* maximum length of time spent waiting */ -+ struct timeval stop_time; /* when the last stop was issued */ -+ u32 delay_after_stop; /* minimum time between stop and subsequent data transfer */ -+ u32 overclock_50; /* frequency to use when 50MHz is requested (in MHz) */ -+ u32 overclock; /* Current frequency if overclocked, else zero */ -+ u32 pio_limit; /* Maximum block count for PIO (0 = always DMA) */ -+}; -+ -+ -+static inline void bcm2835_sdhost_write(struct bcm2835_host *host, u32 val, int reg) -+{ -+ writel(val, host->ioaddr + reg); -+} -+ -+static inline u32 bcm2835_sdhost_read(struct bcm2835_host *host, int reg) -+{ -+ return readl(host->ioaddr + reg); -+} -+ -+static inline u32 bcm2835_sdhost_read_relaxed(struct bcm2835_host *host, int reg) -+{ -+ return readl_relaxed(host->ioaddr + reg); -+} -+ -+static void bcm2835_sdhost_dumpcmd(struct bcm2835_host *host, -+ struct mmc_command *cmd, -+ const char *label) -+{ -+ if (cmd) -+ pr_info("%s:%c%s op %d arg 0x%x flags 0x%x - resp %08x %08x %08x %08x, err %d\n", -+ mmc_hostname(host->mmc), -+ (cmd == host->cmd) ? '>' : ' ', -+ label, cmd->opcode, cmd->arg, cmd->flags, -+ cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3], -+ cmd->error); -+} -+ -+static void bcm2835_sdhost_dumpregs(struct bcm2835_host *host) -+{ -+ bcm2835_sdhost_dumpcmd(host, host->mrq->sbc, "sbc"); -+ bcm2835_sdhost_dumpcmd(host, host->mrq->cmd, "cmd"); -+ if (host->mrq->data) -+ pr_err("%s: data blocks %x blksz %x - err %d\n", -+ mmc_hostname(host->mmc), -+ host->mrq->data->blocks, -+ host->mrq->data->blksz, -+ host->mrq->data->error); -+ bcm2835_sdhost_dumpcmd(host, host->mrq->stop, "stop"); -+ -+ pr_info("%s: =========== REGISTER DUMP ===========\n", -+ mmc_hostname(host->mmc)); -+ -+ pr_info("%s: SDCMD 0x%08x\n", -+ mmc_hostname(host->mmc), -+ bcm2835_sdhost_read(host, SDCMD)); -+ pr_info("%s: SDARG 0x%08x\n", -+ mmc_hostname(host->mmc), -+ bcm2835_sdhost_read(host, SDARG)); -+ pr_info("%s: SDTOUT 0x%08x\n", -+ mmc_hostname(host->mmc), -+ bcm2835_sdhost_read(host, SDTOUT)); -+ pr_info("%s: SDCDIV 0x%08x\n", -+ mmc_hostname(host->mmc), -+ bcm2835_sdhost_read(host, SDCDIV)); -+ pr_info("%s: SDRSP0 0x%08x\n", -+ mmc_hostname(host->mmc), -+ bcm2835_sdhost_read(host, SDRSP0)); -+ pr_info("%s: SDRSP1 0x%08x\n", -+ mmc_hostname(host->mmc), -+ bcm2835_sdhost_read(host, SDRSP1)); -+ pr_info("%s: SDRSP2 0x%08x\n", -+ mmc_hostname(host->mmc), -+ bcm2835_sdhost_read(host, SDRSP2)); -+ pr_info("%s: SDRSP3 0x%08x\n", -+ mmc_hostname(host->mmc), -+ bcm2835_sdhost_read(host, SDRSP3)); -+ pr_info("%s: SDHSTS 0x%08x\n", -+ mmc_hostname(host->mmc), -+ bcm2835_sdhost_read(host, SDHSTS)); -+ pr_info("%s: SDVDD 0x%08x\n", -+ mmc_hostname(host->mmc), -+ bcm2835_sdhost_read(host, SDVDD)); -+ pr_info("%s: SDEDM 0x%08x\n", -+ mmc_hostname(host->mmc), -+ bcm2835_sdhost_read(host, SDEDM)); -+ pr_info("%s: SDHCFG 0x%08x\n", -+ mmc_hostname(host->mmc), -+ bcm2835_sdhost_read(host, SDHCFG)); -+ pr_info("%s: SDHBCT 0x%08x\n", -+ mmc_hostname(host->mmc), -+ bcm2835_sdhost_read(host, SDHBCT)); -+ pr_info("%s: SDHBLC 0x%08x\n", -+ mmc_hostname(host->mmc), -+ bcm2835_sdhost_read(host, SDHBLC)); -+ -+ pr_info("%s: ===========================================\n", -+ mmc_hostname(host->mmc)); -+} -+ -+ -+static void bcm2835_sdhost_set_power(struct bcm2835_host *host, bool on) -+{ -+ bcm2835_sdhost_write(host, on ? 1 : 0, SDVDD); -+} -+ -+ -+static void bcm2835_sdhost_reset_internal(struct bcm2835_host *host) -+{ -+ u32 temp; -+ -+ bcm2835_sdhost_set_power(host, false); -+ -+ bcm2835_sdhost_write(host, 0, SDCMD); -+ bcm2835_sdhost_write(host, 0, SDARG); -+ bcm2835_sdhost_write(host, 0xf00000, SDTOUT); -+ bcm2835_sdhost_write(host, 0, SDCDIV); -+ bcm2835_sdhost_write(host, 0x7f8, SDHSTS); /* Write 1s to clear */ -+ bcm2835_sdhost_write(host, 0, SDHCFG); -+ bcm2835_sdhost_write(host, 0, SDHBCT); -+ bcm2835_sdhost_write(host, 0, SDHBLC); -+ -+ /* Limit fifo usage due to silicon bug */ -+ temp = bcm2835_sdhost_read(host, SDEDM); -+ temp &= ~((SDEDM_THRESHOLD_MASK<clock = 0; -+ bcm2835_sdhost_write(host, host->hcfg, SDHCFG); -+ bcm2835_sdhost_write(host, host->cdiv, SDCDIV); -+ mmiowb(); -+} -+ -+ -+static void bcm2835_sdhost_reset(struct mmc_host *mmc) -+{ -+ struct bcm2835_host *host = mmc_priv(mmc); -+ unsigned long flags; -+ if (host->debug) -+ pr_info("%s: reset\n", mmc_hostname(mmc)); -+ spin_lock_irqsave(&host->lock, flags); -+ -+ bcm2835_sdhost_reset_internal(host); -+ -+ spin_unlock_irqrestore(&host->lock, flags); -+} -+ -+static void bcm2835_sdhost_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); -+ -+static void bcm2835_sdhost_init(struct bcm2835_host *host, int soft) -+{ -+ pr_debug("bcm2835_sdhost_init(%d)\n", soft); -+ -+ /* Set interrupt enables */ -+ host->hcfg = SDHCFG_BUSY_IRPT_EN; -+ -+ bcm2835_sdhost_reset_internal(host); -+ -+ if (soft) { -+ /* force clock reconfiguration */ -+ host->clock = 0; -+ bcm2835_sdhost_set_ios(host->mmc, &host->mmc->ios); -+ } -+} -+ -+static bool bcm2835_sdhost_is_write_complete(struct bcm2835_host *host) -+{ -+ bool write_complete = ((bcm2835_sdhost_read(host, SDEDM) & 0xf) == 1); -+ -+ if (!write_complete) { -+ /* Request an IRQ for the last block */ -+ host->hcfg |= SDHCFG_BLOCK_IRPT_EN; -+ bcm2835_sdhost_write(host, host->hcfg, SDHCFG); -+ if ((bcm2835_sdhost_read(host, SDEDM) & 0xf) == 1) { -+ /* The write has now completed. Disable the interrupt -+ and clear the status flag */ -+ host->hcfg &= ~SDHCFG_BLOCK_IRPT_EN; -+ bcm2835_sdhost_write(host, host->hcfg, SDHCFG); -+ bcm2835_sdhost_write(host, SDHSTS_BLOCK_IRPT, SDHSTS); -+ write_complete = true; -+ } -+ } -+ -+ return write_complete; -+} -+ -+static void bcm2835_sdhost_wait_write_complete(struct bcm2835_host *host) -+{ -+ int timediff; -+#ifdef DEBUG -+ static struct timeval start_time; -+ static int max_stall_time = 0; -+ static int total_stall_time = 0; -+ struct timeval before, after; -+ -+ do_gettimeofday(&before); -+ if (max_stall_time == 0) -+ start_time = before; -+#endif -+ -+ timediff = 0; -+ -+ while (1) { -+ u32 edm = bcm2835_sdhost_read(host, SDEDM); -+ if ((edm & 0xf) == 1) -+ break; -+ timediff++; -+ if (timediff > 5000000) { -+#ifdef DEBUG -+ do_gettimeofday(&after); -+ timediff = (after.tv_sec - before.tv_sec)*1000000 + -+ (after.tv_usec - before.tv_usec); -+ -+ pr_err(" wait_write_complete - still waiting after %dus\n", -+ timediff); -+#else -+ pr_err(" wait_write_complete - still waiting after %d retries\n", -+ timediff); -+#endif -+ bcm2835_sdhost_dumpregs(host); -+ host->data->error = -ETIMEDOUT; -+ return; -+ } -+ } -+ -+#ifdef DEBUG -+ do_gettimeofday(&after); -+ timediff = (after.tv_sec - before.tv_sec)*1000000 + (after.tv_usec - before.tv_usec); -+ -+ total_stall_time += timediff; -+ if (timediff > max_stall_time) -+ max_stall_time = timediff; -+ -+ if ((after.tv_sec - start_time.tv_sec) > 10) { -+ pr_debug(" wait_write_complete - max wait %dus, total %dus\n", -+ max_stall_time, total_stall_time); -+ start_time = after; -+ max_stall_time = 0; -+ total_stall_time = 0; -+ } -+#endif -+} -+ -+static void bcm2835_sdhost_finish_data(struct bcm2835_host *host); -+ -+static void bcm2835_sdhost_dma_complete(void *param) -+{ -+ struct bcm2835_host *host = param; -+ struct dma_chan *dma_chan; -+ unsigned long flags; -+ u32 dir_data; -+ -+ spin_lock_irqsave(&host->lock, flags); -+ -+ if (host->data) { -+ bool write_complete; -+ if (USE_BLOCK_IRQ) -+ write_complete = bcm2835_sdhost_is_write_complete(host); -+ else { -+ bcm2835_sdhost_wait_write_complete(host); -+ write_complete = true; -+ } -+ pr_debug("dma_complete() - write_complete=%d\n", -+ write_complete); -+ -+ if (write_complete || (host->data->flags & MMC_DATA_READ)) -+ { -+ if (write_complete) { -+ dma_chan = host->dma_chan_tx; -+ dir_data = DMA_TO_DEVICE; -+ } else { -+ dma_chan = host->dma_chan_rx; -+ dir_data = DMA_FROM_DEVICE; -+ } -+ -+ dma_unmap_sg(dma_chan->device->dev, -+ host->data->sg, host->data->sg_len, -+ dir_data); -+ -+ bcm2835_sdhost_finish_data(host); -+ } -+ } -+ -+ spin_unlock_irqrestore(&host->lock, flags); -+} -+ -+static bool data_transfer_wait(struct bcm2835_host *host) -+{ -+ unsigned long timeout = 1000000; -+ while (timeout) -+ { -+ u32 sdhsts = bcm2835_sdhost_read(host, SDHSTS); -+ if (sdhsts & SDHSTS_DATA_FLAG) { -+ bcm2835_sdhost_write(host, SDHSTS_DATA_FLAG, SDHSTS); -+ break; -+ } -+ timeout--; -+ } -+ if (timeout == 0) { -+ pr_err("%s: Data %s timeout\n", -+ mmc_hostname(host->mmc), -+ (host->data->flags & MMC_DATA_READ) ? "read" : "write"); -+ bcm2835_sdhost_dumpregs(host); -+ host->data->error = -ETIMEDOUT; -+ return false; -+ } -+ return true; -+} -+ -+static void bcm2835_sdhost_read_block_pio(struct bcm2835_host *host) -+{ -+ unsigned long flags; -+ size_t blksize, len; -+ u32 *buf; -+ -+ blksize = host->data->blksz; -+ -+ local_irq_save(flags); -+ -+ while (blksize) { -+ if (!sg_miter_next(&host->sg_miter)) -+ BUG(); -+ -+ len = min(host->sg_miter.length, blksize); -+ BUG_ON(len % 4); -+ -+ blksize -= len; -+ host->sg_miter.consumed = len; -+ -+ buf = (u32 *)host->sg_miter.addr; -+ -+ while (len) { -+ if (!data_transfer_wait(host)) -+ break; -+ -+ *(buf++) = bcm2835_sdhost_read(host, SDDATA); -+ len -= 4; -+ } -+ -+ if (host->data->error) -+ break; -+ } -+ -+ sg_miter_stop(&host->sg_miter); -+ -+ local_irq_restore(flags); -+} -+ -+static void bcm2835_sdhost_write_block_pio(struct bcm2835_host *host) -+{ -+ unsigned long flags; -+ size_t blksize, len; -+ u32 *buf; -+ -+ blksize = host->data->blksz; -+ -+ local_irq_save(flags); -+ -+ while (blksize) { -+ if (!sg_miter_next(&host->sg_miter)) -+ BUG(); -+ -+ len = min(host->sg_miter.length, blksize); -+ BUG_ON(len % 4); -+ -+ blksize -= len; -+ host->sg_miter.consumed = len; -+ -+ buf = host->sg_miter.addr; -+ -+ while (len) { -+ if (!data_transfer_wait(host)) -+ break; -+ -+ bcm2835_sdhost_write(host, *(buf++), SDDATA); -+ len -= 4; -+ } -+ -+ if (host->data->error) -+ break; -+ } -+ -+ sg_miter_stop(&host->sg_miter); -+ -+ local_irq_restore(flags); -+} -+ -+ -+static void bcm2835_sdhost_transfer_pio(struct bcm2835_host *host) -+{ -+ u32 sdhsts; -+ bool is_read; -+ BUG_ON(!host->data); -+ -+ is_read = (host->data->flags & MMC_DATA_READ) != 0; -+ if (is_read) -+ bcm2835_sdhost_read_block_pio(host); -+ else -+ bcm2835_sdhost_write_block_pio(host); -+ -+ sdhsts = bcm2835_sdhost_read(host, SDHSTS); -+ if (sdhsts & (SDHSTS_CRC16_ERROR | -+ SDHSTS_CRC7_ERROR | -+ SDHSTS_FIFO_ERROR)) { -+ pr_err("%s: %s transfer error - HSTS %x\n", -+ mmc_hostname(host->mmc), -+ is_read ? "read" : "write", -+ sdhsts); -+ host->data->error = -EILSEQ; -+ } else if ((sdhsts & (SDHSTS_CMD_TIME_OUT | -+ SDHSTS_REW_TIME_OUT))) { -+ pr_err("%s: %s timeout error - HSTS %x\n", -+ mmc_hostname(host->mmc), -+ is_read ? "read" : "write", -+ sdhsts); -+ host->data->error = -ETIMEDOUT; -+ } else if (!is_read && !host->data->error) { -+ /* Start a timer in case a transfer error occurs because -+ there is no error interrupt */ -+ mod_timer(&host->pio_timer, jiffies + host->pio_timeout); -+ } -+} -+ -+ -+static void bcm2835_sdhost_transfer_dma(struct bcm2835_host *host) -+{ -+ u32 len, dir_data, dir_slave; -+ struct dma_async_tx_descriptor *desc = NULL; -+ struct dma_chan *dma_chan; -+ -+ pr_debug("bcm2835_sdhost_transfer_dma()\n"); -+ -+ WARN_ON(!host->data); -+ -+ if (!host->data) -+ return; -+ -+ if (host->data->flags & MMC_DATA_READ) { -+ dma_chan = host->dma_chan_rx; -+ dir_data = DMA_FROM_DEVICE; -+ dir_slave = DMA_DEV_TO_MEM; -+ } else { -+ dma_chan = host->dma_chan_tx; -+ dir_data = DMA_TO_DEVICE; -+ dir_slave = DMA_MEM_TO_DEV; -+ } -+ -+ BUG_ON(!dma_chan->device); -+ BUG_ON(!dma_chan->device->dev); -+ BUG_ON(!host->data->sg); -+ -+ len = dma_map_sg(dma_chan->device->dev, host->data->sg, -+ host->data->sg_len, dir_data); -+ if (len > 0) { -+ desc = dmaengine_prep_slave_sg(dma_chan, host->data->sg, -+ len, dir_slave, -+ DMA_PREP_INTERRUPT | DMA_CTRL_ACK); -+ } else { -+ dev_err(mmc_dev(host->mmc), "dma_map_sg returned zero length\n"); -+ } -+ if (desc) { -+ desc->callback = bcm2835_sdhost_dma_complete; -+ desc->callback_param = host; -+ dmaengine_submit(desc); -+ dma_async_issue_pending(dma_chan); -+ } -+ -+} -+ -+ -+static void bcm2835_sdhost_set_transfer_irqs(struct bcm2835_host *host) -+{ -+ u32 all_irqs = SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN | -+ SDHCFG_BUSY_IRPT_EN; -+ if (host->use_dma) -+ host->hcfg = (host->hcfg & ~all_irqs) | -+ SDHCFG_BUSY_IRPT_EN; -+ else -+ host->hcfg = (host->hcfg & ~all_irqs) | -+ SDHCFG_DATA_IRPT_EN | -+ SDHCFG_BUSY_IRPT_EN; -+ -+ bcm2835_sdhost_write(host, host->hcfg, SDHCFG); -+} -+ -+ -+static void bcm2835_sdhost_prepare_data(struct bcm2835_host *host, struct mmc_command *cmd) -+{ -+ struct mmc_data *data = cmd->data; -+ -+ WARN_ON(host->data); -+ -+ if (!data) -+ return; -+ -+ /* Sanity checks */ -+ BUG_ON(data->blksz * data->blocks > 524288); -+ BUG_ON(data->blksz > host->mmc->max_blk_size); -+ BUG_ON(data->blocks > 65535); -+ -+ host->data = data; -+ host->data_complete = 0; -+ host->flush_fifo = 0; -+ host->data->bytes_xfered = 0; -+ -+ host->use_dma = host->have_dma && (data->blocks > host->pio_limit); -+ if (!host->use_dma) { -+ int flags; -+ -+ flags = SG_MITER_ATOMIC; -+ if (data->flags & MMC_DATA_READ) -+ flags |= SG_MITER_TO_SG; -+ else -+ flags |= SG_MITER_FROM_SG; -+ sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); -+ host->blocks = data->blocks; -+ } -+ -+ bcm2835_sdhost_set_transfer_irqs(host); -+ -+ bcm2835_sdhost_write(host, data->blksz, SDHBCT); -+ bcm2835_sdhost_write(host, host->use_dma ? data->blocks : 0, SDHBLC); -+ -+ BUG_ON(!host->data); -+} -+ -+ -+void bcm2835_sdhost_send_command(struct bcm2835_host *host, struct mmc_command *cmd) -+{ -+ u32 sdcmd, sdhsts; -+ unsigned long timeout; -+ int delay; -+ -+ WARN_ON(host->cmd); -+ -+ if (cmd->data) -+ pr_debug("%s: send_command %d 0x%x " -+ "(flags 0x%x) - %s %d*%d\n", -+ mmc_hostname(host->mmc), -+ cmd->opcode, cmd->arg, cmd->flags, -+ (cmd->data->flags & MMC_DATA_READ) ? -+ "read" : "write", cmd->data->blocks, -+ cmd->data->blksz); -+ else -+ pr_debug("%s: send_command %d 0x%x (flags 0x%x)\n", -+ mmc_hostname(host->mmc), -+ cmd->opcode, cmd->arg, cmd->flags); -+ -+ /* Wait max 100 ms */ -+ timeout = 10000; -+ -+ while (bcm2835_sdhost_read(host, SDCMD) & SDCMD_NEW_FLAG) { -+ if (timeout == 0) { -+ pr_err("%s: previous command never completed.\n", -+ mmc_hostname(host->mmc)); -+ bcm2835_sdhost_dumpregs(host); -+ cmd->error = -EIO; -+ tasklet_schedule(&host->finish_tasklet); -+ return; -+ } -+ timeout--; -+ udelay(10); -+ } -+ -+ delay = (10000 - timeout)/100; -+ if (delay > host->max_delay) { -+ host->max_delay = delay; -+ pr_warning("%s: controller hung for %d ms\n", -+ mmc_hostname(host->mmc), -+ host->max_delay); -+ } -+ -+ timeout = jiffies; -+ if (!cmd->data && cmd->busy_timeout > 9000) -+ timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; -+ else -+ timeout += 10 * HZ; -+ mod_timer(&host->timer, timeout); -+ -+ host->cmd = cmd; -+ -+ /* Clear any error flags */ -+ sdhsts = bcm2835_sdhost_read(host, SDHSTS); -+ if (sdhsts & SDHSTS_ERROR_MASK) -+ bcm2835_sdhost_write(host, sdhsts, SDHSTS); -+ -+ bcm2835_sdhost_prepare_data(host, cmd); -+ -+ bcm2835_sdhost_write(host, cmd->arg, SDARG); -+ -+ if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { -+ pr_err("%s: unsupported response type!\n", -+ mmc_hostname(host->mmc)); -+ cmd->error = -EINVAL; -+ tasklet_schedule(&host->finish_tasklet); -+ return; -+ } -+ -+ sdcmd = cmd->opcode & SDCMD_CMD_MASK; -+ -+ if (!(cmd->flags & MMC_RSP_PRESENT)) -+ sdcmd |= SDCMD_NO_RESPONSE; -+ else { -+ if (cmd->flags & MMC_RSP_136) -+ sdcmd |= SDCMD_LONG_RESPONSE; -+ if (cmd->flags & MMC_RSP_BUSY) { -+ sdcmd |= SDCMD_BUSYWAIT; -+ host->use_busy = 1; -+ } -+ } -+ -+ if (cmd->data) { -+ if (host->delay_after_stop) { -+ struct timeval now; -+ int time_since_stop; -+ do_gettimeofday(&now); -+ time_since_stop = (now.tv_sec - host->stop_time.tv_sec); -+ if (time_since_stop < 2) { -+ /* Possibly less than one second */ -+ time_since_stop = time_since_stop * 1000000 + -+ (now.tv_usec - host->stop_time.tv_usec); -+ if (time_since_stop < host->delay_after_stop) -+ udelay(host->delay_after_stop - -+ time_since_stop); -+ } -+ } -+ -+ if (cmd->data->flags & MMC_DATA_WRITE) -+ sdcmd |= SDCMD_WRITE_CMD; -+ if (cmd->data->flags & MMC_DATA_READ) -+ sdcmd |= SDCMD_READ_CMD; -+ } -+ -+ bcm2835_sdhost_write(host, sdcmd | SDCMD_NEW_FLAG, SDCMD); -+} -+ -+ -+static void bcm2835_sdhost_finish_command(struct bcm2835_host *host); -+static void bcm2835_sdhost_transfer_complete(struct bcm2835_host *host); -+ -+static void bcm2835_sdhost_finish_data(struct bcm2835_host *host) -+{ -+ struct mmc_data *data; -+ -+ data = host->data; -+ BUG_ON(!data); -+ -+ pr_debug("finish_data(error %d, stop %d, sbc %d)\n", -+ data->error, data->stop ? 1 : 0, -+ host->mrq->sbc ? 1 : 0); -+ -+ host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN); -+ bcm2835_sdhost_write(host, host->hcfg, SDHCFG); -+ -+ if (data->error) { -+ data->bytes_xfered = 0; -+ } else -+ data->bytes_xfered = data->blksz * data->blocks; -+ -+ host->data_complete = 1; -+ -+ if (host->cmd) { -+ /* -+ * Data managed to finish before the -+ * command completed. Make sure we do -+ * things in the proper order. -+ */ -+ pr_debug("Finished early - HSTS %x\n", -+ bcm2835_sdhost_read(host, SDHSTS)); -+ } -+ else -+ bcm2835_sdhost_transfer_complete(host); -+} -+ -+ -+static void bcm2835_sdhost_transfer_complete(struct bcm2835_host *host) -+{ -+ struct mmc_data *data; -+ -+ BUG_ON(host->cmd); -+ BUG_ON(!host->data); -+ BUG_ON(!host->data_complete); -+ -+ data = host->data; -+ host->data = NULL; -+ -+ pr_debug("transfer_complete(error %d, stop %d)\n", -+ data->error, data->stop ? 1 : 0); -+ -+ /* -+ * Need to send CMD12 if - -+ * a) open-ended multiblock transfer (no CMD23) -+ * b) error in multiblock transfer -+ */ -+ if (data->stop && -+ (data->error || -+ !host->mrq->sbc)) { -+ host->flush_fifo = 1; -+ bcm2835_sdhost_send_command(host, data->stop); -+ if (host->delay_after_stop) -+ do_gettimeofday(&host->stop_time); -+ if (!host->use_busy) -+ bcm2835_sdhost_finish_command(host); -+ } else { -+ tasklet_schedule(&host->finish_tasklet); -+ } -+} -+ -+static void bcm2835_sdhost_finish_command(struct bcm2835_host *host) -+{ -+ u32 sdcmd; -+ unsigned long timeout; -+#ifdef DEBUG -+ struct timeval before, after; -+ int timediff = 0; -+#endif -+ -+ pr_debug("finish_command(%x)\n", bcm2835_sdhost_read(host, SDCMD)); -+ -+ BUG_ON(!host->cmd || !host->mrq); -+ -+#ifdef DEBUG -+ do_gettimeofday(&before); -+#endif -+ /* Wait max 100 ms */ -+ timeout = 10000; -+ for (sdcmd = bcm2835_sdhost_read(host, SDCMD); -+ (sdcmd & SDCMD_NEW_FLAG) && timeout; -+ timeout--) { -+ if (host->flush_fifo) { -+ while (bcm2835_sdhost_read(host, SDHSTS) & -+ SDHSTS_DATA_FLAG) -+ (void)bcm2835_sdhost_read(host, SDDATA); -+ } -+ udelay(10); -+ sdcmd = bcm2835_sdhost_read(host, SDCMD); -+ } -+#ifdef DEBUG -+ do_gettimeofday(&after); -+ timediff = (after.tv_sec - before.tv_sec)*1000000 + -+ (after.tv_usec - before.tv_usec); -+ -+ pr_debug(" finish_command - waited %dus\n", timediff); -+#endif -+ -+ if (timeout == 0) { -+ pr_err("%s: command never completed.\n", -+ mmc_hostname(host->mmc)); -+ bcm2835_sdhost_dumpregs(host); -+ host->cmd->error = -EIO; -+ tasklet_schedule(&host->finish_tasklet); -+ return; -+ } -+ -+ if (host->flush_fifo) { -+ for (timeout = 100; -+ (bcm2835_sdhost_read(host, SDHSTS) & SDHSTS_DATA_FLAG) && timeout; -+ timeout--) { -+ (void)bcm2835_sdhost_read(host, SDDATA); -+ } -+ host->flush_fifo = 0; -+ if (timeout == 0) { -+ pr_err("%s: FIFO never drained.\n", -+ mmc_hostname(host->mmc)); -+ bcm2835_sdhost_dumpregs(host); -+ host->cmd->error = -EIO; -+ tasklet_schedule(&host->finish_tasklet); -+ return; -+ } -+ } -+ -+ /* Check for errors */ -+ if (sdcmd & SDCMD_FAIL_FLAG) -+ { -+ u32 sdhsts = bcm2835_sdhost_read(host, SDHSTS); -+ -+ if (host->debug) -+ pr_info("%s: error detected - CMD %x, HSTS %03x, EDM %x\n", -+ mmc_hostname(host->mmc), sdcmd, sdhsts, -+ bcm2835_sdhost_read(host, SDEDM)); -+ -+ if ((sdhsts & SDHSTS_CRC7_ERROR) && -+ (host->cmd->opcode == 1)) { -+ if (host->debug) -+ pr_info("%s: ignoring CRC7 error for CMD1\n", -+ mmc_hostname(host->mmc)); -+ } else { -+ if (sdhsts & SDHSTS_CMD_TIME_OUT) { -+ switch (host->cmd->opcode) { -+ case 5: case 52: case 53: -+ /* Don't warn about SDIO commands */ -+ break; -+ default: -+ pr_err("%s: command timeout\n", -+ mmc_hostname(host->mmc)); -+ break; -+ } -+ host->cmd->error = -ETIMEDOUT; -+ } else { -+ pr_err("%s: unexpected command error\n", -+ mmc_hostname(host->mmc)); -+ bcm2835_sdhost_dumpregs(host); -+ host->cmd->error = -EIO; -+ } -+ tasklet_schedule(&host->finish_tasklet); -+ return; -+ } -+ } -+ -+ if (host->cmd->flags & MMC_RSP_PRESENT) { -+ if (host->cmd->flags & MMC_RSP_136) { -+ int i; -+ for (i = 0; i < 4; i++) -+ host->cmd->resp[3 - i] = bcm2835_sdhost_read(host, SDRSP0 + i*4); -+ pr_debug("%s: finish_command %08x %08x %08x %08x\n", -+ mmc_hostname(host->mmc), -+ host->cmd->resp[0], host->cmd->resp[1], host->cmd->resp[2], host->cmd->resp[3]); -+ } else { -+ host->cmd->resp[0] = bcm2835_sdhost_read(host, SDRSP0); -+ pr_debug("%s: finish_command %08x\n", -+ mmc_hostname(host->mmc), -+ host->cmd->resp[0]); -+ } -+ } -+ -+ host->cmd->error = 0; -+ -+ if (host->cmd == host->mrq->sbc) { -+ /* Finished CMD23, now send actual command. */ -+ host->cmd = NULL; -+ bcm2835_sdhost_send_command(host, host->mrq->cmd); -+ -+ if (host->cmd->data && host->use_dma) -+ /* DMA transfer starts now, PIO starts after irq */ -+ bcm2835_sdhost_transfer_dma(host); -+ -+ if (!host->use_busy) -+ bcm2835_sdhost_finish_command(host); -+ } else if (host->cmd == host->mrq->stop) -+ /* Finished CMD12 */ -+ tasklet_schedule(&host->finish_tasklet); -+ else { -+ /* Processed actual command. */ -+ host->cmd = NULL; -+ if (!host->data) -+ tasklet_schedule(&host->finish_tasklet); -+ else if (host->data_complete) -+ bcm2835_sdhost_transfer_complete(host); -+ } -+} -+ -+static void bcm2835_sdhost_timeout(unsigned long data) -+{ -+ struct bcm2835_host *host; -+ unsigned long flags; -+ -+ host = (struct bcm2835_host *)data; -+ -+ spin_lock_irqsave(&host->lock, flags); -+ -+ if (host->mrq) { -+ pr_err("%s: timeout waiting for hardware interrupt.\n", -+ mmc_hostname(host->mmc)); -+ bcm2835_sdhost_dumpregs(host); -+ -+ if (host->data) { -+ host->data->error = -ETIMEDOUT; -+ bcm2835_sdhost_finish_data(host); -+ } else { -+ if (host->cmd) -+ host->cmd->error = -ETIMEDOUT; -+ else -+ host->mrq->cmd->error = -ETIMEDOUT; -+ -+ pr_debug("timeout_timer tasklet_schedule\n"); -+ tasklet_schedule(&host->finish_tasklet); -+ } -+ } -+ -+ mmiowb(); -+ spin_unlock_irqrestore(&host->lock, flags); -+} -+ -+static void bcm2835_sdhost_pio_timeout(unsigned long data) -+{ -+ struct bcm2835_host *host; -+ unsigned long flags; -+ -+ host = (struct bcm2835_host *)data; -+ -+ spin_lock_irqsave(&host->lock, flags); -+ -+ if (host->data) { -+ u32 sdhsts = bcm2835_sdhost_read(host, SDHSTS); -+ -+ if (sdhsts & SDHSTS_REW_TIME_OUT) { -+ pr_err("%s: transfer timeout\n", -+ mmc_hostname(host->mmc)); -+ if (host->debug) -+ bcm2835_sdhost_dumpregs(host); -+ } else { -+ pr_err("%s: unexpected transfer timeout\n", -+ mmc_hostname(host->mmc)); -+ bcm2835_sdhost_dumpregs(host); -+ } -+ -+ bcm2835_sdhost_write(host, SDHSTS_TRANSFER_ERROR_MASK, -+ SDHSTS); -+ -+ host->data->error = -ETIMEDOUT; -+ -+ bcm2835_sdhost_finish_data(host); -+ } -+ -+ mmiowb(); -+ spin_unlock_irqrestore(&host->lock, flags); -+} -+ -+static void bcm2835_sdhost_enable_sdio_irq_nolock(struct bcm2835_host *host, int enable) -+{ -+ if (enable) -+ host->hcfg |= SDHCFG_SDIO_IRPT_EN; -+ else -+ host->hcfg &= ~SDHCFG_SDIO_IRPT_EN; -+ bcm2835_sdhost_write(host, host->hcfg, SDHCFG); -+ mmiowb(); -+} -+ -+static void bcm2835_sdhost_enable_sdio_irq(struct mmc_host *mmc, int enable) -+{ -+ struct bcm2835_host *host = mmc_priv(mmc); -+ unsigned long flags; -+ -+ pr_debug("%s: enable_sdio_irq(%d)\n", mmc_hostname(mmc), enable); -+ spin_lock_irqsave(&host->lock, flags); -+ bcm2835_sdhost_enable_sdio_irq_nolock(host, enable); -+ spin_unlock_irqrestore(&host->lock, flags); -+} -+ -+static u32 bcm2835_sdhost_busy_irq(struct bcm2835_host *host, u32 intmask) -+{ -+ const u32 handled = (SDHSTS_REW_TIME_OUT | SDHSTS_CMD_TIME_OUT | -+ SDHSTS_CRC16_ERROR | SDHSTS_CRC7_ERROR | -+ SDHSTS_FIFO_ERROR); -+ -+ if (!host->cmd) { -+ pr_err("%s: got command busy interrupt 0x%08x even " -+ "though no command operation was in progress.\n", -+ mmc_hostname(host->mmc), (unsigned)intmask); -+ bcm2835_sdhost_dumpregs(host); -+ return 0; -+ } -+ -+ if (!host->use_busy) { -+ pr_err("%s: got command busy interrupt 0x%08x even " -+ "though not expecting one.\n", -+ mmc_hostname(host->mmc), (unsigned)intmask); -+ bcm2835_sdhost_dumpregs(host); -+ return 0; -+ } -+ host->use_busy = 0; -+ -+ if (intmask & SDHSTS_ERROR_MASK) -+ { -+ pr_err("sdhost_busy_irq: intmask %x, data %p\n", intmask, host->mrq->data); -+ if (intmask & SDHSTS_CRC7_ERROR) -+ host->cmd->error = -EILSEQ; -+ else if (intmask & (SDHSTS_CRC16_ERROR | -+ SDHSTS_FIFO_ERROR)) { -+ if (host->mrq->data) -+ host->mrq->data->error = -EILSEQ; -+ else -+ host->cmd->error = -EILSEQ; -+ } else if (intmask & SDHSTS_REW_TIME_OUT) { -+ if (host->mrq->data) -+ host->mrq->data->error = -ETIMEDOUT; -+ else -+ host->cmd->error = -ETIMEDOUT; -+ } else if (intmask & SDHSTS_CMD_TIME_OUT) -+ host->cmd->error = -ETIMEDOUT; -+ -+ bcm2835_sdhost_dumpregs(host); -+ tasklet_schedule(&host->finish_tasklet); -+ } -+ else -+ bcm2835_sdhost_finish_command(host); -+ -+ return handled; -+} -+ -+static u32 bcm2835_sdhost_data_irq(struct bcm2835_host *host, u32 intmask) -+{ -+ const u32 handled = (SDHSTS_REW_TIME_OUT | -+ SDHSTS_CRC16_ERROR | -+ SDHSTS_FIFO_ERROR); -+ -+ /* There are no dedicated data/space available interrupt -+ status bits, so it is necessary to use the single shared -+ data/space available FIFO status bits. It is therefore not -+ an error to get here when there is no data transfer in -+ progress. */ -+ if (!host->data) -+ return 0; -+ -+ if (intmask & (SDHSTS_CRC16_ERROR | -+ SDHSTS_FIFO_ERROR | -+ SDHSTS_REW_TIME_OUT)) { -+ if (intmask & (SDHSTS_CRC16_ERROR | -+ SDHSTS_FIFO_ERROR)) -+ host->data->error = -EILSEQ; -+ else -+ host->data->error = -ETIMEDOUT; -+ -+ bcm2835_sdhost_dumpregs(host); -+ tasklet_schedule(&host->finish_tasklet); -+ return handled; -+ } -+ -+ /* Use the block interrupt for writes after the first block */ -+ if (host->data->flags & MMC_DATA_WRITE) { -+ host->hcfg &= ~(SDHCFG_DATA_IRPT_EN); -+ host->hcfg |= SDHCFG_BLOCK_IRPT_EN; -+ bcm2835_sdhost_write(host, host->hcfg, SDHCFG); -+ if (host->data->error) -+ bcm2835_sdhost_finish_data(host); -+ else -+ bcm2835_sdhost_transfer_pio(host); -+ } else { -+ if (!host->data->error) { -+ bcm2835_sdhost_transfer_pio(host); -+ host->blocks--; -+ } -+ if ((host->blocks == 0) || host->data->error) -+ bcm2835_sdhost_finish_data(host); -+ } -+ -+ return handled; -+} -+ -+static u32 bcm2835_sdhost_block_irq(struct bcm2835_host *host, u32 intmask) -+{ -+ struct dma_chan *dma_chan; -+ u32 dir_data; -+ const u32 handled = (SDHSTS_REW_TIME_OUT | -+ SDHSTS_CRC16_ERROR | -+ SDHSTS_FIFO_ERROR); -+ -+ if (!host->data) { -+ pr_err("%s: got block interrupt 0x%08x even " -+ "though no data operation was in progress.\n", -+ mmc_hostname(host->mmc), (unsigned)intmask); -+ bcm2835_sdhost_dumpregs(host); -+ return handled; -+ } -+ -+ if (intmask & (SDHSTS_CRC16_ERROR | -+ SDHSTS_FIFO_ERROR | -+ SDHSTS_REW_TIME_OUT)) { -+ if (intmask & (SDHSTS_CRC16_ERROR | -+ SDHSTS_FIFO_ERROR)) -+ host->data->error = -EILSEQ; -+ else -+ host->data->error = -ETIMEDOUT; -+ -+ if (host->debug) -+ bcm2835_sdhost_dumpregs(host); -+ tasklet_schedule(&host->finish_tasklet); -+ return handled; -+ } -+ -+ if (!host->use_dma) { -+ BUG_ON(!host->blocks); -+ host->blocks--; -+ if ((host->blocks == 0) || host->data->error) { -+ /* Cancel the timer */ -+ del_timer(&host->pio_timer); -+ -+ bcm2835_sdhost_finish_data(host); -+ } else { -+ bcm2835_sdhost_transfer_pio(host); -+ -+ /* Reset the timer */ -+ mod_timer(&host->pio_timer, -+ jiffies + host->pio_timeout); -+ } -+ } else if (host->data->flags & MMC_DATA_WRITE) { -+ dma_chan = host->dma_chan_tx; -+ dir_data = DMA_TO_DEVICE; -+ dma_unmap_sg(dma_chan->device->dev, -+ host->data->sg, host->data->sg_len, -+ dir_data); -+ -+ bcm2835_sdhost_finish_data(host); -+ } -+ -+ return handled; -+} -+ -+ -+static irqreturn_t bcm2835_sdhost_irq(int irq, void *dev_id) -+{ -+ irqreturn_t result = IRQ_NONE; -+ struct bcm2835_host *host = dev_id; -+ u32 unexpected = 0, early = 0; -+ int loops = 0; -+#ifndef CONFIG_ARCH_BCM2835 -+ int cardint = 0; -+#endif -+ spin_lock(&host->lock); -+ -+ for (loops = 0; loops < 1; loops++) { -+ u32 intmask, handled; -+ -+ intmask = bcm2835_sdhost_read(host, SDHSTS); -+ handled = intmask & (SDHSTS_BUSY_IRPT | -+ SDHSTS_BLOCK_IRPT | -+ SDHSTS_SDIO_IRPT | -+ SDHSTS_DATA_FLAG); -+ if ((handled == SDHSTS_DATA_FLAG) && -+ (loops == 0) && !host->data) { -+ pr_err("%s: sdhost_irq data interrupt 0x%08x even " -+ "though no data operation was in progress.\n", -+ mmc_hostname(host->mmc), -+ (unsigned)intmask); -+ -+ bcm2835_sdhost_dumpregs(host); -+ } -+ -+ if (!handled) -+ break; -+ -+ if (loops) -+ early |= handled; -+ -+ result = IRQ_HANDLED; -+ -+ /* Clear all interrupts and notifications */ -+ bcm2835_sdhost_write(host, intmask, SDHSTS); -+ -+ if (intmask & SDHSTS_BUSY_IRPT) -+ handled |= bcm2835_sdhost_busy_irq(host, intmask); -+ -+ /* There is no true data interrupt status bit, so it is -+ necessary to qualify the data flag with the interrupt -+ enable bit */ -+ if ((intmask & SDHSTS_DATA_FLAG) && -+ (host->hcfg & SDHCFG_DATA_IRPT_EN)) -+ handled |= bcm2835_sdhost_data_irq(host, intmask); -+ -+ if (intmask & SDHSTS_BLOCK_IRPT) -+ handled |= bcm2835_sdhost_block_irq(host, intmask); -+ -+ if (intmask & SDHSTS_SDIO_IRPT) { -+#ifndef CONFIG_ARCH_BCM2835 -+ cardint = 1; -+#else -+ bcm2835_sdhost_enable_sdio_irq_nolock(host, false); -+ host->thread_isr |= SDHSTS_SDIO_IRPT; -+ result = IRQ_WAKE_THREAD; -+#endif -+ } -+ -+ unexpected |= (intmask & ~handled); -+ } -+ -+ mmiowb(); -+ -+ spin_unlock(&host->lock); -+ -+ if (early) -+ pr_debug("%s: early %x (loops %d)\n", -+ mmc_hostname(host->mmc), early, loops); -+ -+ if (unexpected) { -+ pr_err("%s: unexpected interrupt 0x%08x.\n", -+ mmc_hostname(host->mmc), unexpected); -+ bcm2835_sdhost_dumpregs(host); -+ } -+ -+#ifndef CONFIG_ARCH_BCM2835 -+ if (cardint) -+ mmc_signal_sdio_irq(host->mmc); -+#endif -+ -+ return result; -+} -+ -+#ifdef CONFIG_ARCH_BCM2835 -+static irqreturn_t bcm2835_sdhost_thread_irq(int irq, void *dev_id) -+{ -+ struct bcm2835_host *host = dev_id; -+ unsigned long flags; -+ u32 isr; -+ -+ spin_lock_irqsave(&host->lock, flags); -+ isr = host->thread_isr; -+ host->thread_isr = 0; -+ spin_unlock_irqrestore(&host->lock, flags); -+ -+ if (isr & SDHSTS_SDIO_IRPT) { -+ sdio_run_irqs(host->mmc); -+ -+/* Is this necessary? Why re-enable an interrupt which is enabled? -+ spin_lock_irqsave(&host->lock, flags); -+ if (host->flags & SDHSTS_SDIO_IRPT_ENABLED) -+ bcm2835_sdhost_enable_sdio_irq_nolock(host, true); -+ spin_unlock_irqrestore(&host->lock, flags); -+*/ -+ } -+ -+ return isr ? IRQ_HANDLED : IRQ_NONE; -+} -+#endif -+ -+ -+ -+void bcm2835_sdhost_set_clock(struct bcm2835_host *host, unsigned int clock) -+{ -+ int div = 0; /* Initialized for compiler warning */ -+ unsigned int input_clock = clock; -+ -+ if (host->debug) -+ pr_info("%s: set_clock(%d)\n", mmc_hostname(host->mmc), clock); -+ -+ if ((host->overclock_50 > 50) && -+ (clock == 50*MHZ)) { -+ clock = host->overclock_50 * MHZ + (MHZ - 1); -+ } -+ -+ /* The SDCDIV register has 11 bits, and holds (div - 2). -+ But in data mode the max is 50MHz wihout a minimum, and only the -+ bottom 3 bits are used. Since the switch over is automatic (unless -+ we have marked the card as slow...), chosen values have to make -+ sense in both modes. -+ Ident mode must be 100-400KHz, so can range check the requested -+ clock. CMD15 must be used to return to data mode, so this can be -+ monitored. -+ -+ clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz -+ 4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz -+ -+ 623->400KHz/27.8MHz -+ reset value (507)->491159/50MHz -+ -+ BUT, the 3-bit clock divisor in data mode is too small if the -+ core clock is higher than 250MHz, so instead use the SLOW_CARD -+ configuration bit to force the use of the ident clock divisor -+ at all times. -+ */ -+ -+ host->mmc->actual_clock = 0; -+ -+ if (clock < 100000) { -+ /* Can't stop the clock, but make it as slow as possible -+ * to show willing -+ */ -+ host->cdiv = SDCDIV_MAX_CDIV; -+ bcm2835_sdhost_write(host, host->cdiv, SDCDIV); -+ return; -+ } -+ -+ div = host->max_clk / clock; -+ if (div < 2) -+ div = 2; -+ if ((host->max_clk / div) > clock) -+ div++; -+ div -= 2; -+ -+ if (div > SDCDIV_MAX_CDIV) -+ div = SDCDIV_MAX_CDIV; -+ -+ clock = host->max_clk / (div + 2); -+ host->mmc->actual_clock = clock; -+ -+ if (clock > input_clock) { -+ /* Save the closest value, to make it easier -+ to reduce in the event of error */ -+ host->overclock_50 = (clock/MHZ); -+ -+ if (clock != host->overclock) { -+ pr_warn("%s: overclocking to %dHz\n", -+ mmc_hostname(host->mmc), clock); -+ host->overclock = clock; -+ } -+ } -+ else if (host->overclock) -+ { -+ host->overclock = 0; -+ if (clock == 50 * MHZ) -+ pr_warn("%s: cancelling overclock\n", -+ mmc_hostname(host->mmc)); -+ } -+ -+ host->cdiv = div; -+ bcm2835_sdhost_write(host, host->cdiv, SDCDIV); -+ -+ /* Set the timeout to 500ms */ -+ bcm2835_sdhost_write(host, host->mmc->actual_clock/2, SDTOUT); -+ -+ if (host->debug) -+ pr_info("%s: clock=%d -> max_clk=%d, cdiv=%x (actual clock %d)\n", -+ mmc_hostname(host->mmc), input_clock, -+ host->max_clk, host->cdiv, host->mmc->actual_clock); -+} -+ -+static void bcm2835_sdhost_request(struct mmc_host *mmc, struct mmc_request *mrq) -+{ -+ struct bcm2835_host *host; -+ unsigned long flags; -+ -+ host = mmc_priv(mmc); -+ -+ if (host->debug) { -+ struct mmc_command *cmd = mrq->cmd; -+ BUG_ON(!cmd); -+ if (cmd->data) -+ pr_info("%s: cmd %d 0x%x (flags 0x%x) - %s %d*%d\n", -+ mmc_hostname(mmc), -+ cmd->opcode, cmd->arg, cmd->flags, -+ (cmd->data->flags & MMC_DATA_READ) ? -+ "read" : "write", cmd->data->blocks, -+ cmd->data->blksz); -+ else -+ pr_info("%s: cmd %d 0x%x (flags 0x%x)\n", -+ mmc_hostname(mmc), -+ cmd->opcode, cmd->arg, cmd->flags); -+ } -+ -+ /* Reset the error statuses in case this is a retry */ -+ if (mrq->cmd) -+ mrq->cmd->error = 0; -+ if (mrq->data) -+ mrq->data->error = 0; -+ if (mrq->stop) -+ mrq->stop->error = 0; -+ -+ if (mrq->data && !is_power_of_2(mrq->data->blksz)) { -+ pr_err("%s: unsupported block size (%d bytes)\n", -+ mmc_hostname(mmc), mrq->data->blksz); -+ mrq->cmd->error = -EINVAL; -+ mmc_request_done(mmc, mrq); -+ return; -+ } -+ -+ spin_lock_irqsave(&host->lock, flags); -+ -+ WARN_ON(host->mrq != NULL); -+ -+ host->mrq = mrq; -+ -+ if (mrq->sbc) -+ bcm2835_sdhost_send_command(host, mrq->sbc); -+ else -+ bcm2835_sdhost_send_command(host, mrq->cmd); -+ -+ mmiowb(); -+ spin_unlock_irqrestore(&host->lock, flags); -+ -+ if (!mrq->sbc && mrq->cmd->data && host->use_dma) -+ /* DMA transfer starts now, PIO starts after irq */ -+ bcm2835_sdhost_transfer_dma(host); -+ -+ if (!host->use_busy) -+ bcm2835_sdhost_finish_command(host); -+} -+ -+ -+static void bcm2835_sdhost_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) -+{ -+ -+ struct bcm2835_host *host = mmc_priv(mmc); -+ unsigned long flags; -+ -+ if (host->debug) -+ pr_info("%s: ios clock %d, pwr %d, bus_width %d, " -+ "timing %d, vdd %d, drv_type %d\n", -+ mmc_hostname(mmc), -+ ios->clock, ios->power_mode, ios->bus_width, -+ ios->timing, ios->signal_voltage, ios->drv_type); -+ -+ spin_lock_irqsave(&host->lock, flags); -+ -+ if (!ios->clock || ios->clock != host->clock) { -+ bcm2835_sdhost_set_clock(host, ios->clock); -+ host->clock = ios->clock; -+ } -+ -+ /* set bus width */ -+ host->hcfg &= ~SDHCFG_WIDE_EXT_BUS; -+ if (ios->bus_width == MMC_BUS_WIDTH_4) -+ host->hcfg |= SDHCFG_WIDE_EXT_BUS; -+ -+ host->hcfg |= SDHCFG_WIDE_INT_BUS; -+ -+ /* Disable clever clock switching, to cope with fast core clocks */ -+ host->hcfg |= SDHCFG_SLOW_CARD; -+ -+ bcm2835_sdhost_write(host, host->hcfg, SDHCFG); -+ -+ mmiowb(); -+ -+ spin_unlock_irqrestore(&host->lock, flags); -+} -+ -+static int bcm2835_sdhost_multi_io_quirk(struct mmc_card *card, -+ unsigned int direction, -+ u32 blk_pos, int blk_size) -+{ -+ /* There is a bug in the host controller hardware that makes -+ reading the final sector of the card as part of a multiple read -+ problematic. Detect that case and shorten the read accordingly. -+ */ -+ /* csd.capacity is in weird units - convert to sectors */ -+ u32 card_sectors = (card->csd.capacity << (card->csd.read_blkbits - 9)); -+ -+ if ((direction == MMC_DATA_READ) && -+ ((blk_pos + blk_size) == card_sectors)) -+ blk_size--; -+ -+ return blk_size; -+} -+ -+ -+static struct mmc_host_ops bcm2835_sdhost_ops = { -+ .request = bcm2835_sdhost_request, -+ .set_ios = bcm2835_sdhost_set_ios, -+ .enable_sdio_irq = bcm2835_sdhost_enable_sdio_irq, -+ .hw_reset = bcm2835_sdhost_reset, -+ .multi_io_quirk = bcm2835_sdhost_multi_io_quirk, -+}; -+ -+ -+static void bcm2835_sdhost_tasklet_finish(unsigned long param) -+{ -+ struct bcm2835_host *host; -+ unsigned long flags; -+ struct mmc_request *mrq; -+ -+ host = (struct bcm2835_host *)param; -+ -+ spin_lock_irqsave(&host->lock, flags); -+ -+ /* -+ * If this tasklet gets rescheduled while running, it will -+ * be run again afterwards but without any active request. -+ */ -+ if (!host->mrq) { -+ spin_unlock_irqrestore(&host->lock, flags); -+ return; -+ } -+ -+ del_timer(&host->timer); -+ -+ mrq = host->mrq; -+ -+ /* Drop the overclock after any data corruption, or after any -+ error overclocked */ -+ if (host->overclock) { -+ if ((mrq->cmd && mrq->cmd->error) || -+ (mrq->data && mrq->data->error) || -+ (mrq->stop && mrq->stop->error)) { -+ host->overclock_50--; -+ pr_warn("%s: reducing overclock due to errors\n", -+ mmc_hostname(host->mmc)); -+ bcm2835_sdhost_set_clock(host,50*MHZ); -+ mrq->cmd->error = -EILSEQ; -+ mrq->cmd->retries = 1; -+ } -+ } -+ -+ host->mrq = NULL; -+ host->cmd = NULL; -+ host->data = NULL; -+ -+ mmiowb(); -+ -+ spin_unlock_irqrestore(&host->lock, flags); -+ mmc_request_done(host->mmc, mrq); -+} -+ -+ -+ -+int bcm2835_sdhost_add_host(struct bcm2835_host *host) -+{ -+ struct mmc_host *mmc; -+ struct dma_slave_config cfg; -+ char pio_limit_string[20]; -+ int ret; -+ -+ mmc = host->mmc; -+ -+ bcm2835_sdhost_reset_internal(host); -+ -+ mmc->f_max = host->max_clk; -+ mmc->f_min = host->max_clk / SDCDIV_MAX_CDIV; -+ -+ mmc->max_busy_timeout = (~(unsigned int)0)/(mmc->f_max/1000); -+ -+ pr_debug("f_max %d, f_min %d, max_busy_timeout %d\n", -+ mmc->f_max, mmc->f_min, mmc->max_busy_timeout); -+ -+ /* host controller capabilities */ -+ mmc->caps |= /* MMC_CAP_SDIO_IRQ |*/ MMC_CAP_4_BIT_DATA | -+ MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | -+ MMC_CAP_NEEDS_POLL | MMC_CAP_HW_RESET | MMC_CAP_ERASE | -+ (ALLOW_CMD23 * MMC_CAP_CMD23); -+ -+ spin_lock_init(&host->lock); -+ -+ if (host->allow_dma) { -+ if (IS_ERR_OR_NULL(host->dma_chan_tx) || -+ IS_ERR_OR_NULL(host->dma_chan_rx)) { -+ pr_err("%s: unable to initialise DMA channels. " -+ "Falling back to PIO\n", -+ mmc_hostname(mmc)); -+ host->have_dma = false; -+ } else { -+ host->have_dma = true; -+ -+ cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; -+ cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; -+ cfg.slave_id = 13; /* DREQ channel */ -+ -+ cfg.direction = DMA_MEM_TO_DEV; -+ cfg.src_addr = 0; -+ cfg.dst_addr = host->phys_addr + SDDATA; -+ ret = dmaengine_slave_config(host->dma_chan_tx, &cfg); -+ -+ cfg.direction = DMA_DEV_TO_MEM; -+ cfg.src_addr = host->phys_addr + SDDATA; -+ cfg.dst_addr = 0; -+ ret = dmaengine_slave_config(host->dma_chan_rx, &cfg); -+ } -+ } else { -+ host->have_dma = false; -+ } -+ -+ mmc->max_segs = 128; -+ mmc->max_req_size = 524288; -+ mmc->max_seg_size = mmc->max_req_size; -+ mmc->max_blk_size = 512; -+ mmc->max_blk_count = 65535; -+ -+ /* report supported voltage ranges */ -+ mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; -+ -+ tasklet_init(&host->finish_tasklet, -+ bcm2835_sdhost_tasklet_finish, (unsigned long)host); -+ -+ setup_timer(&host->timer, bcm2835_sdhost_timeout, -+ (unsigned long)host); -+ -+ setup_timer(&host->pio_timer, bcm2835_sdhost_pio_timeout, -+ (unsigned long)host); -+ -+ bcm2835_sdhost_init(host, 0); -+#ifndef CONFIG_ARCH_BCM2835 -+ ret = request_irq(host->irq, bcm2835_sdhost_irq, 0 /*IRQF_SHARED*/, -+ mmc_hostname(mmc), host); -+#else -+ ret = request_threaded_irq(host->irq, bcm2835_sdhost_irq, -+ bcm2835_sdhost_thread_irq, -+ IRQF_SHARED, mmc_hostname(mmc), host); -+#endif -+ if (ret) { -+ pr_err("%s: failed to request IRQ %d: %d\n", -+ mmc_hostname(mmc), host->irq, ret); -+ goto untasklet; -+ } -+ -+ mmiowb(); -+ mmc_add_host(mmc); -+ -+ pio_limit_string[0] = '\0'; -+ if (host->have_dma && (host->pio_limit > 0)) -+ sprintf(pio_limit_string, " (>%d)", host->pio_limit); -+ pr_info("%s: %s loaded - DMA %s%s\n", -+ mmc_hostname(mmc), DRIVER_NAME, -+ host->have_dma ? "enabled" : "disabled", -+ pio_limit_string); -+ -+ return 0; -+ -+untasklet: -+ tasklet_kill(&host->finish_tasklet); -+ -+ return ret; -+} -+ -+static int bcm2835_sdhost_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct device_node *node = dev->of_node; -+ struct clk *clk; -+ struct resource *iomem; -+ struct bcm2835_host *host; -+ struct mmc_host *mmc; -+ int ret; -+ -+ pr_debug("bcm2835_sdhost_probe\n"); -+ mmc = mmc_alloc_host(sizeof(*host), dev); -+ if (!mmc) -+ return -ENOMEM; -+ -+ mmc->ops = &bcm2835_sdhost_ops; -+ host = mmc_priv(mmc); -+ host->mmc = mmc; -+ host->pio_timeout = msecs_to_jiffies(500); -+ host->max_delay = 1; /* Warn if over 1ms */ -+ spin_lock_init(&host->lock); -+ -+ iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ host->ioaddr = devm_ioremap_resource(dev, iomem); -+ if (IS_ERR(host->ioaddr)) { -+ ret = PTR_ERR(host->ioaddr); -+ goto err; -+ } -+ -+ host->phys_addr = iomem->start + BCM2835_VCMMU_SHIFT; -+ pr_debug(" - ioaddr %lx, iomem->start %lx, phys_addr %lx\n", -+ (unsigned long)host->ioaddr, -+ (unsigned long)iomem->start, -+ (unsigned long)host->phys_addr); -+ -+ host->allow_dma = ALLOW_DMA; -+ -+ if (node) { -+ /* Read any custom properties */ -+ of_property_read_u32(node, -+ "brcm,delay-after-stop", -+ &host->delay_after_stop); -+ of_property_read_u32(node, -+ "brcm,overclock-50", -+ &host->overclock_50); -+ of_property_read_u32(node, -+ "brcm,pio-limit", -+ &host->pio_limit); -+ host->allow_dma = ALLOW_DMA && -+ !of_property_read_bool(node, "brcm,force-pio"); -+ host->debug = of_property_read_bool(node, "brcm,debug"); -+ } -+ -+ if (host->allow_dma) { -+ if (node) { -+ host->dma_chan_tx = -+ dma_request_slave_channel(dev, "tx"); -+ host->dma_chan_rx = -+ dma_request_slave_channel(dev, "rx"); -+ } else { -+ dma_cap_mask_t mask; -+ -+ dma_cap_zero(mask); -+ /* we don't care about the channel, any would work */ -+ dma_cap_set(DMA_SLAVE, mask); -+ host->dma_chan_tx = -+ dma_request_channel(mask, NULL, NULL); -+ host->dma_chan_rx = -+ dma_request_channel(mask, NULL, NULL); -+ } -+ } -+ -+ clk = devm_clk_get(dev, NULL); -+ if (IS_ERR(clk)) { -+ dev_err(dev, "could not get clk\n"); -+ ret = PTR_ERR(clk); -+ goto err; -+ } -+ -+ host->max_clk = clk_get_rate(clk); -+ -+ host->irq = platform_get_irq(pdev, 0); -+ if (host->irq <= 0) { -+ dev_err(dev, "get IRQ failed\n"); -+ ret = -EINVAL; -+ goto err; -+ } -+ -+ pr_debug(" - max_clk %lx, irq %d\n", -+ (unsigned long)host->max_clk, -+ (int)host->irq); -+ -+ if (node) -+ mmc_of_parse(mmc); -+ else -+ mmc->caps |= MMC_CAP_4_BIT_DATA; -+ -+ ret = bcm2835_sdhost_add_host(host); -+ if (ret) -+ goto err; -+ -+ platform_set_drvdata(pdev, host); -+ -+ pr_debug("bcm2835_sdhost_probe -> OK\n"); -+ -+ return 0; -+ -+err: -+ pr_debug("bcm2835_sdhost_probe -> err %d\n", ret); -+ mmc_free_host(mmc); -+ -+ return ret; -+} -+ -+static int bcm2835_sdhost_remove(struct platform_device *pdev) -+{ -+ struct bcm2835_host *host = platform_get_drvdata(pdev); -+ -+ pr_debug("bcm2835_sdhost_remove\n"); -+ -+ mmc_remove_host(host->mmc); -+ -+ bcm2835_sdhost_set_power(host, false); -+ -+ free_irq(host->irq, host); -+ -+ del_timer_sync(&host->timer); -+ -+ tasklet_kill(&host->finish_tasklet); -+ -+ mmc_free_host(host->mmc); -+ platform_set_drvdata(pdev, NULL); -+ -+ pr_debug("bcm2835_sdhost_remove - OK\n"); -+ return 0; -+} -+ -+ -+static const struct of_device_id bcm2835_sdhost_match[] = { -+ { .compatible = "brcm,bcm2835-sdhost" }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, bcm2835_sdhost_match); -+ -+ -+ -+static struct platform_driver bcm2835_sdhost_driver = { -+ .probe = bcm2835_sdhost_probe, -+ .remove = bcm2835_sdhost_remove, -+ .driver = { -+ .name = DRIVER_NAME, -+ .owner = THIS_MODULE, -+ .of_match_table = bcm2835_sdhost_match, -+ }, -+}; -+module_platform_driver(bcm2835_sdhost_driver); -+ -+MODULE_ALIAS("platform:sdhost-bcm2835"); -+MODULE_DESCRIPTION("BCM2835 SDHost driver"); -+MODULE_LICENSE("GPL v2"); -+MODULE_AUTHOR("Phil Elwell"); -diff -Nur linux-4.1.13.orig/drivers/mmc/host/Kconfig linux-rpi/drivers/mmc/host/Kconfig ---- linux-4.1.13.orig/drivers/mmc/host/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/mmc/host/Kconfig 2015-11-29 09:42:38.087220413 +0100 -@@ -4,6 +4,45 @@ - - comment "MMC/SD/SDIO Host Controller Drivers" - -+config MMC_BCM2835 -+ tristate "MMC support on BCM2835" -+ depends on MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835 -+ help -+ This selects the MMC Interface on BCM2835. -+ -+ If you have a controller with this interface, say Y or M here. -+ -+ If unsure, say N. -+ -+config MMC_BCM2835_DMA -+ bool "DMA support on BCM2835 Arasan controller" -+ depends on MMC_BCM2835 -+ help -+ Enable DMA support on the Arasan SDHCI controller in Broadcom 2708 -+ based chips. -+ -+ If unsure, say N. -+ -+config MMC_BCM2835_PIO_DMA_BARRIER -+ int "Block count limit for PIO transfers" -+ depends on MMC_BCM2835 && MMC_BCM2835_DMA -+ range 0 256 -+ default 2 -+ help -+ The inclusive limit in bytes under which PIO will be used instead of DMA -+ -+ If unsure, say 2 here. -+ -+config MMC_BCM2835_SDHOST -+ tristate "Support for the SDHost controller on BCM2708/9" -+ depends on MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835 -+ help -+ This selects the SDHost controller on BCM2835/6. -+ -+ If you have a controller with this interface, say Y or M here. -+ -+ If unsure, say N. -+ - config MMC_ARMMMCI - tristate "ARM AMBA Multimedia Card Interface support" - depends on ARM_AMBA -diff -Nur linux-4.1.13.orig/drivers/mmc/host/Makefile linux-rpi/drivers/mmc/host/Makefile ---- linux-4.1.13.orig/drivers/mmc/host/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/mmc/host/Makefile 2015-11-29 09:42:38.087220413 +0100 -@@ -18,6 +18,8 @@ - obj-$(CONFIG_MMC_SDHCI_SIRF) += sdhci-sirf.o - obj-$(CONFIG_MMC_SDHCI_F_SDH30) += sdhci_f_sdh30.o - obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o -+obj-$(CONFIG_MMC_BCM2835_SDHOST) += bcm2835-sdhost.o -+obj-$(CONFIG_MMC_BCM2835) += bcm2835-mmc.o - obj-$(CONFIG_MMC_WBSD) += wbsd.o - obj-$(CONFIG_MMC_AU1X) += au1xmmc.o - obj-$(CONFIG_MMC_OMAP) += omap.o -diff -Nur linux-4.1.13.orig/drivers/mmc/host/omap_hsmmc.c linux-rpi/drivers/mmc/host/omap_hsmmc.c ---- linux-4.1.13.orig/drivers/mmc/host/omap_hsmmc.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/mmc/host/omap_hsmmc.c 2015-11-29 09:42:38.095219881 +0100 -@@ -1749,7 +1749,9 @@ - } - - static int omap_hsmmc_multi_io_quirk(struct mmc_card *card, -- unsigned int direction, int blk_size) -+ unsigned int direction, -+ u32 blk_pos, -+ int blk_size) - { - /* This controller can't do multiblock reads due to hw bugs */ - if (direction == MMC_DATA_READ) -diff -Nur linux-4.1.13.orig/drivers/mmc/host/sh_mobile_sdhi.c linux-rpi/drivers/mmc/host/sh_mobile_sdhi.c ---- linux-4.1.13.orig/drivers/mmc/host/sh_mobile_sdhi.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/mmc/host/sh_mobile_sdhi.c 2015-11-29 09:42:38.099219616 +0100 -@@ -170,7 +170,9 @@ - } - - static int sh_mobile_sdhi_multi_io_quirk(struct mmc_card *card, -- unsigned int direction, int blk_size) -+ unsigned int direction, -+ u32 blk_pos, -+ int blk_size) - { - /* - * In Renesas controllers, when performing a -diff -Nur linux-4.1.13.orig/drivers/mmc/host/tmio_mmc_pio.c linux-rpi/drivers/mmc/host/tmio_mmc_pio.c ---- linux-4.1.13.orig/drivers/mmc/host/tmio_mmc_pio.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/mmc/host/tmio_mmc_pio.c 2015-11-29 09:42:38.103219350 +0100 -@@ -1001,7 +1001,9 @@ - } - - static int tmio_multi_io_quirk(struct mmc_card *card, -- unsigned int direction, int blk_size) -+ unsigned int direction, -+ u32 blk_pos, -+ int blk_size) - { - struct tmio_mmc_host *host = mmc_priv(card->host); - -diff -Nur linux-4.1.13.orig/drivers/mtd/nand/bcm2835_smi_nand.c linux-rpi/drivers/mtd/nand/bcm2835_smi_nand.c ---- linux-4.1.13.orig/drivers/mtd/nand/bcm2835_smi_nand.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/mtd/nand/bcm2835_smi_nand.c 2015-11-29 09:42:38.147216426 +0100 -@@ -0,0 +1,268 @@ -+/** -+ * NAND flash driver for Broadcom Secondary Memory Interface -+ * -+ * Written by Luke Wren -+ * Copyright (c) 2015, Raspberry Pi (Trading) Ltd. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#define DEVICE_NAME "bcm2835-smi-nand" -+#define DRIVER_NAME "smi-nand-bcm2835" -+ -+struct bcm2835_smi_nand_host { -+ struct bcm2835_smi_instance *smi_inst; -+ struct nand_chip nand_chip; -+ struct mtd_info mtd; -+ struct device *dev; -+}; -+ -+/**************************************************************************** -+* -+* NAND functionality implementation -+* -+****************************************************************************/ -+ -+#define SMI_NAND_CLE_PIN 0x01 -+#define SMI_NAND_ALE_PIN 0x02 -+ -+static inline void bcm2835_smi_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, -+ unsigned int ctrl) -+{ -+ uint32_t cmd32 = cmd; -+ uint32_t addr = ~(SMI_NAND_CLE_PIN | SMI_NAND_ALE_PIN); -+ struct bcm2835_smi_nand_host *host = dev_get_drvdata(mtd->dev.parent); -+ struct bcm2835_smi_instance *inst = host->smi_inst; -+ -+ if (ctrl & NAND_CLE) -+ addr |= SMI_NAND_CLE_PIN; -+ if (ctrl & NAND_ALE) -+ addr |= SMI_NAND_ALE_PIN; -+ /* Lower ALL the CS pins! */ -+ if (ctrl & NAND_NCE) -+ addr &= (SMI_NAND_CLE_PIN | SMI_NAND_ALE_PIN); -+ -+ bcm2835_smi_set_address(inst, addr); -+ -+ if (cmd != NAND_CMD_NONE) -+ bcm2835_smi_write_buf(inst, &cmd32, 1); -+} -+ -+static inline uint8_t bcm2835_smi_nand_read_byte(struct mtd_info *mtd) -+{ -+ uint8_t byte; -+ struct bcm2835_smi_nand_host *host = dev_get_drvdata(mtd->dev.parent); -+ struct bcm2835_smi_instance *inst = host->smi_inst; -+ -+ bcm2835_smi_read_buf(inst, &byte, 1); -+ return byte; -+} -+ -+static inline void bcm2835_smi_nand_write_byte(struct mtd_info *mtd, -+ uint8_t byte) -+{ -+ struct bcm2835_smi_nand_host *host = dev_get_drvdata(mtd->dev.parent); -+ struct bcm2835_smi_instance *inst = host->smi_inst; -+ -+ bcm2835_smi_write_buf(inst, &byte, 1); -+} -+ -+static inline void bcm2835_smi_nand_write_buf(struct mtd_info *mtd, -+ const uint8_t *buf, int len) -+{ -+ struct bcm2835_smi_nand_host *host = dev_get_drvdata(mtd->dev.parent); -+ struct bcm2835_smi_instance *inst = host->smi_inst; -+ -+ bcm2835_smi_write_buf(inst, buf, len); -+} -+ -+static inline void bcm2835_smi_nand_read_buf(struct mtd_info *mtd, -+ uint8_t *buf, int len) -+{ -+ struct bcm2835_smi_nand_host *host = dev_get_drvdata(mtd->dev.parent); -+ struct bcm2835_smi_instance *inst = host->smi_inst; -+ -+ bcm2835_smi_read_buf(inst, buf, len); -+} -+ -+/**************************************************************************** -+* -+* Probe and remove functions -+* -+***************************************************************************/ -+ -+static int bcm2835_smi_nand_probe(struct platform_device *pdev) -+{ -+ struct bcm2835_smi_nand_host *host; -+ struct nand_chip *this; -+ struct mtd_info *mtd; -+ struct device *dev = &pdev->dev; -+ struct device_node *node = dev->of_node, *smi_node; -+ struct mtd_part_parser_data ppdata; -+ struct smi_settings *smi_settings; -+ struct bcm2835_smi_instance *smi_inst; -+ int ret = -ENXIO; -+ -+ if (!node) { -+ dev_err(dev, "No device tree node supplied!"); -+ return -EINVAL; -+ } -+ -+ smi_node = of_parse_phandle(node, "smi_handle", 0); -+ -+ /* Request use of SMI peripheral: */ -+ smi_inst = bcm2835_smi_get(smi_node); -+ -+ if (!smi_inst) { -+ dev_err(dev, "Could not register with SMI."); -+ return -EPROBE_DEFER; -+ } -+ -+ /* Set SMI timing and bus width */ -+ -+ smi_settings = bcm2835_smi_get_settings_from_regs(smi_inst); -+ -+ smi_settings->data_width = SMI_WIDTH_8BIT; -+ smi_settings->read_setup_time = 2; -+ smi_settings->read_hold_time = 1; -+ smi_settings->read_pace_time = 1; -+ smi_settings->read_strobe_time = 3; -+ -+ smi_settings->write_setup_time = 2; -+ smi_settings->write_hold_time = 1; -+ smi_settings->write_pace_time = 1; -+ smi_settings->write_strobe_time = 3; -+ -+ bcm2835_smi_set_regs_from_settings(smi_inst); -+ -+ host = devm_kzalloc(dev, sizeof(struct bcm2835_smi_nand_host), -+ GFP_KERNEL); -+ if (!host) -+ return -ENOMEM; -+ -+ host->dev = dev; -+ host->smi_inst = smi_inst; -+ -+ platform_set_drvdata(pdev, host); -+ -+ /* Link the structures together */ -+ -+ this = &host->nand_chip; -+ mtd = &host->mtd; -+ mtd->priv = this; -+ mtd->owner = THIS_MODULE; -+ mtd->dev.parent = dev; -+ mtd->name = DRIVER_NAME; -+ ppdata.of_node = node; -+ -+ /* 20 us command delay time... */ -+ this->chip_delay = 20; -+ -+ this->priv = host; -+ this->cmd_ctrl = bcm2835_smi_nand_cmd_ctrl; -+ this->read_byte = bcm2835_smi_nand_read_byte; -+ this->write_byte = bcm2835_smi_nand_write_byte; -+ this->write_buf = bcm2835_smi_nand_write_buf; -+ this->read_buf = bcm2835_smi_nand_read_buf; -+ -+ this->ecc.mode = NAND_ECC_SOFT; -+ -+ /* Should never be accessed directly: */ -+ -+ this->IO_ADDR_R = (void *)0xdeadbeef; -+ this->IO_ADDR_W = (void *)0xdeadbeef; -+ -+ /* First scan to find the device and get the page size */ -+ -+ if (nand_scan_ident(mtd, 1, NULL)) -+ return -ENXIO; -+ -+ /* Second phase scan */ -+ -+ if (nand_scan_tail(mtd)) -+ return -ENXIO; -+ -+ ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0); -+ if (!ret) -+ return 0; -+ -+ nand_release(mtd); -+ return -EINVAL; -+} -+ -+static int bcm2835_smi_nand_remove(struct platform_device *pdev) -+{ -+ struct bcm2835_smi_nand_host *host = platform_get_drvdata(pdev); -+ -+ nand_release(&host->mtd); -+ -+ return 0; -+} -+ -+/**************************************************************************** -+* -+* Register the driver with device tree -+* -+***************************************************************************/ -+ -+static const struct of_device_id bcm2835_smi_nand_of_match[] = { -+ {.compatible = "brcm,bcm2835-smi-nand",}, -+ { /* sentinel */ } -+}; -+ -+MODULE_DEVICE_TABLE(of, bcm2835_smi_nand_of_match); -+ -+static struct platform_driver bcm2835_smi_nand_driver = { -+ .probe = bcm2835_smi_nand_probe, -+ .remove = bcm2835_smi_nand_remove, -+ .driver = { -+ .name = DRIVER_NAME, -+ .owner = THIS_MODULE, -+ .of_match_table = bcm2835_smi_nand_of_match, -+ }, -+}; -+ -+module_platform_driver(bcm2835_smi_nand_driver); -+ -+MODULE_ALIAS("platform:smi-nand-bcm2835"); -+MODULE_LICENSE("GPL"); -+MODULE_DESCRIPTION -+ ("Driver for NAND chips using Broadcom Secondary Memory Interface"); -+MODULE_AUTHOR("Luke Wren "); -diff -Nur linux-4.1.13.orig/drivers/mtd/nand/Kconfig linux-rpi/drivers/mtd/nand/Kconfig ---- linux-4.1.13.orig/drivers/mtd/nand/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/mtd/nand/Kconfig 2015-11-29 09:42:38.143216692 +0100 -@@ -41,6 +41,13 @@ - tristate - default n - -+config MTD_NAND_BCM2835_SMI -+ tristate "Use Broadcom's Secondary Memory Interface as a NAND controller (BCM283x)" -+ depends on (MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835) && BCM2835_SMI && MTD_NAND -+ default m -+ help -+ Uses the BCM2835's SMI peripheral as a NAND controller. -+ - config MTD_NAND_DENALI - tristate "Support Denali NAND controller" - depends on HAS_DMA -diff -Nur linux-4.1.13.orig/drivers/mtd/nand/Makefile linux-rpi/drivers/mtd/nand/Makefile ---- linux-4.1.13.orig/drivers/mtd/nand/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/mtd/nand/Makefile 2015-11-29 09:42:38.143216692 +0100 -@@ -14,6 +14,7 @@ - obj-$(CONFIG_MTD_NAND_DENALI_PCI) += denali_pci.o - obj-$(CONFIG_MTD_NAND_DENALI_DT) += denali_dt.o - obj-$(CONFIG_MTD_NAND_AU1550) += au1550nd.o -+obj-$(CONFIG_MTD_NAND_BCM2835_SMI) += bcm2835_smi_nand.o - obj-$(CONFIG_MTD_NAND_BF5XX) += bf5xx_nand.o - obj-$(CONFIG_MTD_NAND_S3C2410) += s3c2410.o - obj-$(CONFIG_MTD_NAND_DAVINCI) += davinci_nand.o -diff -Nur linux-4.1.13.orig/drivers/net/ethernet/microchip/enc28j60.c linux-rpi/drivers/net/ethernet/microchip/enc28j60.c ---- linux-4.1.13.orig/drivers/net/ethernet/microchip/enc28j60.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/net/ethernet/microchip/enc28j60.c 2015-11-29 09:42:38.431197557 +0100 -@@ -1630,10 +1630,21 @@ - return 0; - } - -+#ifdef CONFIG_OF -+static const struct of_device_id enc28j60_of_match[] = { -+ { .compatible = "microchip,enc28j60", }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, enc28j60_of_match); -+#endif -+ - static struct spi_driver enc28j60_driver = { - .driver = { - .name = DRV_NAME, - .owner = THIS_MODULE, -+#ifdef CONFIG_OF -+ .of_match_table = enc28j60_of_match, -+#endif - }, - .probe = enc28j60_probe, - .remove = enc28j60_remove, -diff -Nur linux-4.1.13.orig/drivers/net/usb/smsc95xx.c linux-rpi/drivers/net/usb/smsc95xx.c ---- linux-4.1.13.orig/drivers/net/usb/smsc95xx.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/net/usb/smsc95xx.c 2015-11-29 09:42:38.627184535 +0100 -@@ -59,6 +59,7 @@ - #define SUSPEND_SUSPEND3 (0x08) - #define SUSPEND_ALLMODES (SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \ - SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3) -+#define MAC_ADDR_LEN (6) - - struct smsc95xx_priv { - u32 mac_cr; -@@ -70,10 +71,14 @@ - u8 suspend_flags; - }; - --static bool turbo_mode = true; -+static bool turbo_mode = false; - module_param(turbo_mode, bool, 0644); - MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction"); - -+static char *macaddr = ":"; -+module_param(macaddr, charp, 0); -+MODULE_PARM_DESC(macaddr, "MAC address"); -+ - static int __must_check __smsc95xx_read_reg(struct usbnet *dev, u32 index, - u32 *data, int in_pm) - { -@@ -763,8 +768,59 @@ - return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); - } - -+/* Check the macaddr module parameter for a MAC address */ -+static int smsc95xx_is_macaddr_param(struct usbnet *dev, u8 *dev_mac) -+{ -+ int i, j, got_num, num; -+ u8 mtbl[MAC_ADDR_LEN]; -+ -+ if (macaddr[0] == ':') -+ return 0; -+ -+ i = 0; -+ j = 0; -+ num = 0; -+ got_num = 0; -+ while (j < MAC_ADDR_LEN) { -+ if (macaddr[i] && macaddr[i] != ':') { -+ got_num++; -+ if ('0' <= macaddr[i] && macaddr[i] <= '9') -+ num = num * 16 + macaddr[i] - '0'; -+ else if ('A' <= macaddr[i] && macaddr[i] <= 'F') -+ num = num * 16 + 10 + macaddr[i] - 'A'; -+ else if ('a' <= macaddr[i] && macaddr[i] <= 'f') -+ num = num * 16 + 10 + macaddr[i] - 'a'; -+ else -+ break; -+ i++; -+ } else if (got_num == 2) { -+ mtbl[j++] = (u8) num; -+ num = 0; -+ got_num = 0; -+ i++; -+ } else { -+ break; -+ } -+ } -+ -+ if (j == MAC_ADDR_LEN) { -+ netif_dbg(dev, ifup, dev->net, "Overriding MAC address with: " -+ "%02x:%02x:%02x:%02x:%02x:%02x\n", mtbl[0], mtbl[1], mtbl[2], -+ mtbl[3], mtbl[4], mtbl[5]); -+ for (i = 0; i < MAC_ADDR_LEN; i++) -+ dev_mac[i] = mtbl[i]; -+ return 1; -+ } else { -+ return 0; -+ } -+} -+ - static void smsc95xx_init_mac_address(struct usbnet *dev) - { -+ /* Check module parameters */ -+ if (smsc95xx_is_macaddr_param(dev, dev->net->dev_addr)) -+ return; -+ - /* try reading mac address from EEPROM */ - if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN, - dev->net->dev_addr) == 0) { -@@ -1785,7 +1841,6 @@ - if (dev->net->features & NETIF_F_RXCSUM) - smsc95xx_rx_csum_offload(skb); - skb_trim(skb, skb->len - 4); /* remove fcs */ -- skb->truesize = size + sizeof(struct sk_buff); - - return 1; - } -@@ -1803,7 +1858,6 @@ - if (dev->net->features & NETIF_F_RXCSUM) - smsc95xx_rx_csum_offload(ax_skb); - skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */ -- ax_skb->truesize = size + sizeof(struct sk_buff); - - usbnet_skb_return(dev, ax_skb); - } -diff -Nur linux-4.1.13.orig/drivers/net/wireless/Kconfig linux-rpi/drivers/net/wireless/Kconfig ---- linux-4.1.13.orig/drivers/net/wireless/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/net/wireless/Kconfig 2015-11-29 09:43:36.719324606 +0100 -@@ -277,6 +277,7 @@ - source "drivers/net/wireless/orinoco/Kconfig" - source "drivers/net/wireless/p54/Kconfig" - source "drivers/net/wireless/rt2x00/Kconfig" -+source "drivers/net/wireless/mediatek/Kconfig" - source "drivers/net/wireless/rtlwifi/Kconfig" - source "drivers/net/wireless/ti/Kconfig" - source "drivers/net/wireless/zd1211rw/Kconfig" -diff -Nur linux-4.1.13.orig/drivers/net/wireless/Makefile linux-rpi/drivers/net/wireless/Makefile ---- linux-4.1.13.orig/drivers/net/wireless/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/net/wireless/Makefile 2015-11-29 09:43:52.726261026 +0100 -@@ -45,6 +45,8 @@ - obj-$(CONFIG_IWLEGACY) += iwlegacy/ - obj-$(CONFIG_RT2X00) += rt2x00/ - -+obj-$(CONFIG_WL_MEDIATEK) += mediatek/ -+ - obj-$(CONFIG_P54_COMMON) += p54/ - - obj-$(CONFIG_ATH_CARDS) += ath/ -diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/Kconfig linux-rpi/drivers/net/wireless/mediatek/Kconfig ---- linux-4.1.13.orig/drivers/net/wireless/mediatek/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/net/wireless/mediatek/Kconfig 2015-11-29 09:42:38.887167260 +0100 -@@ -0,0 +1,10 @@ -+menuconfig WL_MEDIATEK -+ bool "Mediatek Wireless LAN support" -+ ---help--- -+ Enable community drivers for MediaTek WiFi devices. -+ Those drivers make use of the Linux mac80211 stack. -+ -+ -+if WL_MEDIATEK -+source "drivers/net/wireless/mediatek/mt7601u/Kconfig" -+endif # WL_MEDIATEK -diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/Makefile linux-rpi/drivers/net/wireless/mediatek/Makefile ---- linux-4.1.13.orig/drivers/net/wireless/mediatek/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/net/wireless/mediatek/Makefile 2015-11-29 09:42:38.887167260 +0100 -@@ -0,0 +1 @@ -+obj-$(CONFIG_MT7601U) += mt7601u/ -diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/core.c linux-rpi/drivers/net/wireless/mediatek/mt7601u/core.c ---- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/core.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/core.c 2015-11-29 09:42:38.887167260 +0100 -@@ -0,0 +1,78 @@ -+/* -+ * Copyright (C) 2014 Felix Fietkau -+ * Copyright (C) 2015 Jakub Kicinski -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 -+ * as published by the Free Software Foundation -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include "mt7601u.h" -+ -+int mt7601u_wait_asic_ready(struct mt7601u_dev *dev) -+{ -+ int i = 100; -+ u32 val; -+ -+ do { -+ if (test_bit(MT7601U_STATE_REMOVED, &dev->state)) -+ return -EIO; -+ -+ val = mt7601u_rr(dev, MT_MAC_CSR0); -+ if (val && ~val) -+ return 0; -+ -+ udelay(10); -+ } while (i--); -+ -+ return -EIO; -+} -+ -+bool mt76_poll(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val, -+ int timeout) -+{ -+ u32 cur; -+ -+ timeout /= 10; -+ do { -+ if (test_bit(MT7601U_STATE_REMOVED, &dev->state)) -+ return false; -+ -+ cur = mt7601u_rr(dev, offset) & mask; -+ if (cur == val) -+ return true; -+ -+ udelay(10); -+ } while (timeout-- > 0); -+ -+ dev_err(dev->dev, "Error: Time out with reg %08x\n", offset); -+ -+ return false; -+} -+ -+bool mt76_poll_msec(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val, -+ int timeout) -+{ -+ u32 cur; -+ -+ timeout /= 10; -+ do { -+ if (test_bit(MT7601U_STATE_REMOVED, &dev->state)) -+ return false; -+ -+ cur = mt7601u_rr(dev, offset) & mask; -+ if (cur == val) -+ return true; -+ -+ msleep(10); -+ } while (timeout-- > 0); -+ -+ dev_err(dev->dev, "Error: Time out with reg %08x\n", offset); -+ -+ return false; -+} -diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/debugfs.c linux-rpi/drivers/net/wireless/mediatek/mt7601u/debugfs.c ---- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/debugfs.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/debugfs.c 2015-11-29 09:42:38.887167260 +0100 -@@ -0,0 +1,172 @@ -+/* -+ * Copyright (C) 2014 Felix Fietkau -+ * Copyright (C) 2015 Jakub Kicinski -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 -+ * as published by the Free Software Foundation -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include -+ -+#include "mt7601u.h" -+#include "eeprom.h" -+ -+static int -+mt76_reg_set(void *data, u64 val) -+{ -+ struct mt7601u_dev *dev = data; -+ -+ mt76_wr(dev, dev->debugfs_reg, val); -+ return 0; -+} -+ -+static int -+mt76_reg_get(void *data, u64 *val) -+{ -+ struct mt7601u_dev *dev = data; -+ -+ *val = mt76_rr(dev, dev->debugfs_reg); -+ return 0; -+} -+ -+DEFINE_SIMPLE_ATTRIBUTE(fops_regval, mt76_reg_get, mt76_reg_set, "0x%08llx\n"); -+ -+static int -+mt7601u_ampdu_stat_read(struct seq_file *file, void *data) -+{ -+ struct mt7601u_dev *dev = file->private; -+ int i, j; -+ -+#define stat_printf(grp, off, name) \ -+ seq_printf(file, #name ":\t%llu\n", dev->stats.grp[off]) -+ -+ stat_printf(rx_stat, 0, rx_crc_err); -+ stat_printf(rx_stat, 1, rx_phy_err); -+ stat_printf(rx_stat, 2, rx_false_cca); -+ stat_printf(rx_stat, 3, rx_plcp_err); -+ stat_printf(rx_stat, 4, rx_fifo_overflow); -+ stat_printf(rx_stat, 5, rx_duplicate); -+ -+ stat_printf(tx_stat, 0, tx_fail_cnt); -+ stat_printf(tx_stat, 1, tx_bcn_cnt); -+ stat_printf(tx_stat, 2, tx_success); -+ stat_printf(tx_stat, 3, tx_retransmit); -+ stat_printf(tx_stat, 4, tx_zero_len); -+ stat_printf(tx_stat, 5, tx_underflow); -+ -+ stat_printf(aggr_stat, 0, non_aggr_tx); -+ stat_printf(aggr_stat, 1, aggr_tx); -+ -+ stat_printf(zero_len_del, 0, tx_zero_len_del); -+ stat_printf(zero_len_del, 1, rx_zero_len_del); -+#undef stat_printf -+ -+ seq_puts(file, "Aggregations stats:\n"); -+ for (i = 0; i < 4; i++) { -+ for (j = 0; j < 8; j++) -+ seq_printf(file, "%08llx ", -+ dev->stats.aggr_n[i * 8 + j]); -+ seq_putc(file, '\n'); -+ } -+ -+ seq_printf(file, "recent average AMPDU len: %d\n", -+ atomic_read(&dev->avg_ampdu_len)); -+ -+ return 0; -+} -+ -+static int -+mt7601u_ampdu_stat_open(struct inode *inode, struct file *f) -+{ -+ return single_open(f, mt7601u_ampdu_stat_read, inode->i_private); -+} -+ -+static const struct file_operations fops_ampdu_stat = { -+ .open = mt7601u_ampdu_stat_open, -+ .read = seq_read, -+ .llseek = seq_lseek, -+ .release = single_release, -+}; -+ -+static int -+mt7601u_eeprom_param_read(struct seq_file *file, void *data) -+{ -+ struct mt7601u_dev *dev = file->private; -+ struct mt7601u_rate_power *rp = &dev->ee->power_rate_table; -+ struct tssi_data *td = &dev->ee->tssi_data; -+ int i; -+ -+ seq_printf(file, "RF freq offset: %hhx\n", dev->ee->rf_freq_off); -+ seq_printf(file, "RSSI offset: %hhx %hhx\n", -+ dev->ee->rssi_offset[0], dev->ee->rssi_offset[1]); -+ seq_printf(file, "Reference temp: %hhx\n", dev->ee->ref_temp); -+ seq_printf(file, "LNA gain: %hhx\n", dev->ee->lna_gain); -+ seq_printf(file, "Reg channels: %hhu-%hhu\n", dev->ee->reg.start, -+ dev->ee->reg.start + dev->ee->reg.num - 1); -+ -+ seq_puts(file, "Per rate power:\n"); -+ for (i = 0; i < 2; i++) -+ seq_printf(file, "\t raw:%02hhx bw20:%02hhx bw40:%02hhx\n", -+ rp->cck[i].raw, rp->cck[i].bw20, rp->cck[i].bw40); -+ for (i = 0; i < 4; i++) -+ seq_printf(file, "\t raw:%02hhx bw20:%02hhx bw40:%02hhx\n", -+ rp->ofdm[i].raw, rp->ofdm[i].bw20, rp->ofdm[i].bw40); -+ for (i = 0; i < 4; i++) -+ seq_printf(file, "\t raw:%02hhx bw20:%02hhx bw40:%02hhx\n", -+ rp->ht[i].raw, rp->ht[i].bw20, rp->ht[i].bw40); -+ -+ seq_puts(file, "Per channel power:\n"); -+ for (i = 0; i < 7; i++) -+ seq_printf(file, "\t tx_power ch%u:%02hhx ch%u:%02hhx\n", -+ i * 2 + 1, dev->ee->chan_pwr[i * 2], -+ i * 2 + 2, dev->ee->chan_pwr[i * 2 + 1]); -+ -+ if (!dev->ee->tssi_enabled) -+ return 0; -+ -+ seq_puts(file, "TSSI:\n"); -+ seq_printf(file, "\t slope:%02hhx\n", td->slope); -+ seq_printf(file, "\t offset=%02hhx %02hhx %02hhx\n", -+ td->offset[0], td->offset[1], td->offset[2]); -+ seq_printf(file, "\t delta_off:%08x\n", td->tx0_delta_offset); -+ -+ return 0; -+} -+ -+static int -+mt7601u_eeprom_param_open(struct inode *inode, struct file *f) -+{ -+ return single_open(f, mt7601u_eeprom_param_read, inode->i_private); -+} -+ -+static const struct file_operations fops_eeprom_param = { -+ .open = mt7601u_eeprom_param_open, -+ .read = seq_read, -+ .llseek = seq_lseek, -+ .release = single_release, -+}; -+ -+void mt7601u_init_debugfs(struct mt7601u_dev *dev) -+{ -+ struct dentry *dir; -+ -+ dir = debugfs_create_dir("mt7601u", dev->hw->wiphy->debugfsdir); -+ if (!dir) -+ return; -+ -+ debugfs_create_u8("temperature", S_IRUSR, dir, &dev->raw_temp); -+ debugfs_create_u32("temp_mode", S_IRUSR, dir, &dev->temp_mode); -+ -+ debugfs_create_u32("regidx", S_IRUSR | S_IWUSR, dir, &dev->debugfs_reg); -+ debugfs_create_file("regval", S_IRUSR | S_IWUSR, dir, dev, -+ &fops_regval); -+ debugfs_create_file("ampdu_stat", S_IRUSR, dir, dev, &fops_ampdu_stat); -+ debugfs_create_file("eeprom_param", S_IRUSR, dir, dev, -+ &fops_eeprom_param); -+} -diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/dma.c linux-rpi/drivers/net/wireless/mediatek/mt7601u/dma.c ---- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/dma.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/dma.c 2015-11-29 09:42:38.887167260 +0100 -@@ -0,0 +1,529 @@ -+/* -+ * Copyright (C) 2015 Jakub Kicinski -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 -+ * as published by the Free Software Foundation -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include "mt7601u.h" -+#include "dma.h" -+#include "usb.h" -+#include "trace.h" -+ -+static int mt7601u_submit_rx_buf(struct mt7601u_dev *dev, -+ struct mt7601u_dma_buf_rx *e, gfp_t gfp); -+ -+static unsigned int ieee80211_get_hdrlen_from_buf(const u8 *data, unsigned len) -+{ -+ const struct ieee80211_hdr *hdr = (const struct ieee80211_hdr *)data; -+ unsigned int hdrlen; -+ -+ if (unlikely(len < 10)) -+ return 0; -+ hdrlen = ieee80211_hdrlen(hdr->frame_control); -+ if (unlikely(hdrlen > len)) -+ return 0; -+ return hdrlen; -+} -+ -+static struct sk_buff * -+mt7601u_rx_skb_from_seg(struct mt7601u_dev *dev, struct mt7601u_rxwi *rxwi, -+ void *data, u32 seg_len, u32 truesize, struct page *p) -+{ -+ struct sk_buff *skb; -+ u32 true_len, hdr_len = 0, copy, frag; -+ -+ skb = alloc_skb(p ? 128 : seg_len, GFP_ATOMIC); -+ if (!skb) -+ return NULL; -+ -+ true_len = mt76_mac_process_rx(dev, skb, data, rxwi); -+ if (!true_len || true_len > seg_len) -+ goto bad_frame; -+ -+ hdr_len = ieee80211_get_hdrlen_from_buf(data, true_len); -+ if (!hdr_len) -+ goto bad_frame; -+ -+ if (rxwi->rxinfo & cpu_to_le32(MT_RXINFO_L2PAD)) { -+ memcpy(skb_put(skb, hdr_len), data, hdr_len); -+ -+ data += hdr_len + 2; -+ true_len -= hdr_len; -+ hdr_len = 0; -+ } -+ -+ /* If not doing paged RX allocated skb will always have enough space */ -+ copy = (true_len <= skb_tailroom(skb)) ? true_len : hdr_len + 8; -+ frag = true_len - copy; -+ -+ memcpy(skb_put(skb, copy), data, copy); -+ data += copy; -+ -+ if (frag) { -+ skb_add_rx_frag(skb, 0, p, data - page_address(p), -+ frag, truesize); -+ get_page(p); -+ } -+ -+ return skb; -+ -+bad_frame: -+ dev_err_ratelimited(dev->dev, "Error: incorrect frame len:%u hdr:%u\n", -+ true_len, hdr_len); -+ dev_kfree_skb(skb); -+ return NULL; -+} -+ -+static void mt7601u_rx_process_seg(struct mt7601u_dev *dev, u8 *data, -+ u32 seg_len, struct page *p) -+{ -+ struct sk_buff *skb; -+ struct mt7601u_rxwi *rxwi; -+ u32 fce_info, truesize = seg_len; -+ -+ /* DMA_INFO field at the beginning of the segment contains only some of -+ * the information, we need to read the FCE descriptor from the end. -+ */ -+ fce_info = get_unaligned_le32(data + seg_len - MT_FCE_INFO_LEN); -+ seg_len -= MT_FCE_INFO_LEN; -+ -+ data += MT_DMA_HDR_LEN; -+ seg_len -= MT_DMA_HDR_LEN; -+ -+ rxwi = (struct mt7601u_rxwi *) data; -+ data += sizeof(struct mt7601u_rxwi); -+ seg_len -= sizeof(struct mt7601u_rxwi); -+ -+ if (unlikely(rxwi->zero[0] || rxwi->zero[1] || rxwi->zero[2])) -+ dev_err_once(dev->dev, "Error: RXWI zero fields are set\n"); -+ if (unlikely(MT76_GET(MT_RXD_INFO_TYPE, fce_info))) -+ dev_err_once(dev->dev, "Error: RX path seen a non-pkt urb\n"); -+ -+ trace_mt_rx(dev, rxwi, fce_info); -+ -+ skb = mt7601u_rx_skb_from_seg(dev, rxwi, data, seg_len, truesize, p); -+ if (!skb) -+ return; -+ -+ spin_lock(&dev->mac_lock); -+ ieee80211_rx(dev->hw, skb); -+ spin_unlock(&dev->mac_lock); -+} -+ -+static u16 mt7601u_rx_next_seg_len(u8 *data, u32 data_len) -+{ -+ u32 min_seg_len = MT_DMA_HDR_LEN + MT_RX_INFO_LEN + -+ sizeof(struct mt7601u_rxwi) + MT_FCE_INFO_LEN; -+ u16 dma_len = get_unaligned_le16(data); -+ -+ if (data_len < min_seg_len || -+ WARN_ON(!dma_len) || -+ WARN_ON(dma_len + MT_DMA_HDRS > data_len) || -+ WARN_ON(dma_len & 0x3)) -+ return 0; -+ -+ return MT_DMA_HDRS + dma_len; -+} -+ -+static void -+mt7601u_rx_process_entry(struct mt7601u_dev *dev, struct mt7601u_dma_buf_rx *e) -+{ -+ u32 seg_len, data_len = e->urb->actual_length; -+ u8 *data = page_address(e->p); -+ struct page *new_p = NULL; -+ int cnt = 0; -+ -+ if (!test_bit(MT7601U_STATE_INITIALIZED, &dev->state)) -+ return; -+ -+ /* Copy if there is very little data in the buffer. */ -+ if (data_len > 512) -+ new_p = dev_alloc_pages(MT_RX_ORDER); -+ -+ while ((seg_len = mt7601u_rx_next_seg_len(data, data_len))) { -+ mt7601u_rx_process_seg(dev, data, seg_len, new_p ? e->p : NULL); -+ -+ data_len -= seg_len; -+ data += seg_len; -+ cnt++; -+ } -+ -+ if (cnt > 1) -+ trace_mt_rx_dma_aggr(dev, cnt, !!new_p); -+ -+ if (new_p) { -+ /* we have one extra ref from the allocator */ -+ __free_pages(e->p, MT_RX_ORDER); -+ -+ e->p = new_p; -+ } -+} -+ -+static struct mt7601u_dma_buf_rx * -+mt7601u_rx_get_pending_entry(struct mt7601u_dev *dev) -+{ -+ struct mt7601u_rx_queue *q = &dev->rx_q; -+ struct mt7601u_dma_buf_rx *buf = NULL; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&dev->rx_lock, flags); -+ -+ if (!q->pending) -+ goto out; -+ -+ buf = &q->e[q->start]; -+ q->pending--; -+ q->start = (q->start + 1) % q->entries; -+out: -+ spin_unlock_irqrestore(&dev->rx_lock, flags); -+ -+ return buf; -+} -+ -+static void mt7601u_complete_rx(struct urb *urb) -+{ -+ struct mt7601u_dev *dev = urb->context; -+ struct mt7601u_rx_queue *q = &dev->rx_q; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&dev->rx_lock, flags); -+ -+ if (mt7601u_urb_has_error(urb)) -+ dev_err(dev->dev, "Error: RX urb failed:%d\n", urb->status); -+ if (WARN_ONCE(q->e[q->end].urb != urb, "RX urb mismatch")) -+ goto out; -+ -+ q->end = (q->end + 1) % q->entries; -+ q->pending++; -+ tasklet_schedule(&dev->rx_tasklet); -+out: -+ spin_unlock_irqrestore(&dev->rx_lock, flags); -+} -+ -+static void mt7601u_rx_tasklet(unsigned long data) -+{ -+ struct mt7601u_dev *dev = (struct mt7601u_dev *) data; -+ struct mt7601u_dma_buf_rx *e; -+ -+ while ((e = mt7601u_rx_get_pending_entry(dev))) { -+ if (e->urb->status) -+ continue; -+ -+ mt7601u_rx_process_entry(dev, e); -+ mt7601u_submit_rx_buf(dev, e, GFP_ATOMIC); -+ } -+} -+ -+static void mt7601u_complete_tx(struct urb *urb) -+{ -+ struct mt7601u_tx_queue *q = urb->context; -+ struct mt7601u_dev *dev = q->dev; -+ struct sk_buff *skb; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&dev->tx_lock, flags); -+ -+ if (mt7601u_urb_has_error(urb)) -+ dev_err(dev->dev, "Error: TX urb failed:%d\n", urb->status); -+ if (WARN_ONCE(q->e[q->start].urb != urb, "TX urb mismatch")) -+ goto out; -+ -+ skb = q->e[q->start].skb; -+ trace_mt_tx_dma_done(dev, skb); -+ -+ __skb_queue_tail(&dev->tx_skb_done, skb); -+ tasklet_schedule(&dev->tx_tasklet); -+ -+ if (q->used == q->entries - q->entries / 8) -+ ieee80211_wake_queue(dev->hw, skb_get_queue_mapping(skb)); -+ -+ q->start = (q->start + 1) % q->entries; -+ q->used--; -+out: -+ spin_unlock_irqrestore(&dev->tx_lock, flags); -+} -+ -+static void mt7601u_tx_tasklet(unsigned long data) -+{ -+ struct mt7601u_dev *dev = (struct mt7601u_dev *) data; -+ struct sk_buff_head skbs; -+ unsigned long flags; -+ -+ __skb_queue_head_init(&skbs); -+ -+ spin_lock_irqsave(&dev->tx_lock, flags); -+ -+ set_bit(MT7601U_STATE_MORE_STATS, &dev->state); -+ if (!test_and_set_bit(MT7601U_STATE_READING_STATS, &dev->state)) -+ queue_delayed_work(dev->stat_wq, &dev->stat_work, -+ msecs_to_jiffies(10)); -+ -+ skb_queue_splice_init(&dev->tx_skb_done, &skbs); -+ -+ spin_unlock_irqrestore(&dev->tx_lock, flags); -+ -+ while (!skb_queue_empty(&skbs)) { -+ struct sk_buff *skb = __skb_dequeue(&skbs); -+ -+ mt7601u_tx_status(dev, skb); -+ } -+} -+ -+static int mt7601u_dma_submit_tx(struct mt7601u_dev *dev, -+ struct sk_buff *skb, u8 ep) -+{ -+ struct usb_device *usb_dev = mt7601u_to_usb_dev(dev); -+ unsigned snd_pipe = usb_sndbulkpipe(usb_dev, dev->out_eps[ep]); -+ struct mt7601u_dma_buf_tx *e; -+ struct mt7601u_tx_queue *q = &dev->tx_q[ep]; -+ unsigned long flags; -+ int ret; -+ -+ spin_lock_irqsave(&dev->tx_lock, flags); -+ -+ if (WARN_ON(q->entries <= q->used)) { -+ ret = -ENOSPC; -+ goto out; -+ } -+ -+ e = &q->e[q->end]; -+ e->skb = skb; -+ usb_fill_bulk_urb(e->urb, usb_dev, snd_pipe, skb->data, skb->len, -+ mt7601u_complete_tx, q); -+ ret = usb_submit_urb(e->urb, GFP_ATOMIC); -+ if (ret) { -+ /* Special-handle ENODEV from TX urb submission because it will -+ * often be the first ENODEV we see after device is removed. -+ */ -+ if (ret == -ENODEV) -+ set_bit(MT7601U_STATE_REMOVED, &dev->state); -+ else -+ dev_err(dev->dev, "Error: TX urb submit failed:%d\n", -+ ret); -+ goto out; -+ } -+ -+ q->end = (q->end + 1) % q->entries; -+ q->used++; -+ -+ if (q->used >= q->entries) -+ ieee80211_stop_queue(dev->hw, skb_get_queue_mapping(skb)); -+out: -+ spin_unlock_irqrestore(&dev->tx_lock, flags); -+ -+ return ret; -+} -+ -+/* Map hardware Q to USB endpoint number */ -+static u8 q2ep(u8 qid) -+{ -+ /* TODO: take management packets to queue 5 */ -+ return qid + 1; -+} -+ -+/* Map USB endpoint number to Q id in the DMA engine */ -+static enum mt76_qsel ep2dmaq(u8 ep) -+{ -+ if (ep == 5) -+ return MT_QSEL_MGMT; -+ return MT_QSEL_EDCA; -+} -+ -+int mt7601u_dma_enqueue_tx(struct mt7601u_dev *dev, struct sk_buff *skb, -+ struct mt76_wcid *wcid, int hw_q) -+{ -+ u8 ep = q2ep(hw_q); -+ u32 dma_flags; -+ int ret; -+ -+ dma_flags = MT_TXD_PKT_INFO_80211; -+ if (wcid->hw_key_idx == 0xff) -+ dma_flags |= MT_TXD_PKT_INFO_WIV; -+ -+ ret = mt7601u_dma_skb_wrap_pkt(skb, ep2dmaq(ep), dma_flags); -+ if (ret) -+ return ret; -+ -+ ret = mt7601u_dma_submit_tx(dev, skb, ep); -+ if (ret) { -+ ieee80211_free_txskb(dev->hw, skb); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static void mt7601u_kill_rx(struct mt7601u_dev *dev) -+{ -+ int i; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&dev->rx_lock, flags); -+ -+ for (i = 0; i < dev->rx_q.entries; i++) { -+ int next = dev->rx_q.end; -+ -+ spin_unlock_irqrestore(&dev->rx_lock, flags); -+ usb_poison_urb(dev->rx_q.e[next].urb); -+ spin_lock_irqsave(&dev->rx_lock, flags); -+ } -+ -+ spin_unlock_irqrestore(&dev->rx_lock, flags); -+} -+ -+static int mt7601u_submit_rx_buf(struct mt7601u_dev *dev, -+ struct mt7601u_dma_buf_rx *e, gfp_t gfp) -+{ -+ struct usb_device *usb_dev = mt7601u_to_usb_dev(dev); -+ u8 *buf = page_address(e->p); -+ unsigned pipe; -+ int ret; -+ -+ pipe = usb_rcvbulkpipe(usb_dev, dev->in_eps[MT_EP_IN_PKT_RX]); -+ -+ usb_fill_bulk_urb(e->urb, usb_dev, pipe, buf, MT_RX_URB_SIZE, -+ mt7601u_complete_rx, dev); -+ -+ trace_mt_submit_urb(dev, e->urb); -+ ret = usb_submit_urb(e->urb, gfp); -+ if (ret) -+ dev_err(dev->dev, "Error: submit RX URB failed:%d\n", ret); -+ -+ return ret; -+} -+ -+static int mt7601u_submit_rx(struct mt7601u_dev *dev) -+{ -+ int i, ret; -+ -+ for (i = 0; i < dev->rx_q.entries; i++) { -+ ret = mt7601u_submit_rx_buf(dev, &dev->rx_q.e[i], GFP_KERNEL); -+ if (ret) -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static void mt7601u_free_rx(struct mt7601u_dev *dev) -+{ -+ int i; -+ -+ for (i = 0; i < dev->rx_q.entries; i++) { -+ __free_pages(dev->rx_q.e[i].p, MT_RX_ORDER); -+ usb_free_urb(dev->rx_q.e[i].urb); -+ } -+} -+ -+static int mt7601u_alloc_rx(struct mt7601u_dev *dev) -+{ -+ int i; -+ -+ memset(&dev->rx_q, 0, sizeof(dev->rx_q)); -+ dev->rx_q.dev = dev; -+ dev->rx_q.entries = N_RX_ENTRIES; -+ -+ for (i = 0; i < N_RX_ENTRIES; i++) { -+ dev->rx_q.e[i].urb = usb_alloc_urb(0, GFP_KERNEL); -+ dev->rx_q.e[i].p = dev_alloc_pages(MT_RX_ORDER); -+ -+ if (!dev->rx_q.e[i].urb || !dev->rx_q.e[i].p) -+ return -ENOMEM; -+ } -+ -+ return 0; -+} -+ -+static void mt7601u_free_tx_queue(struct mt7601u_tx_queue *q) -+{ -+ int i; -+ -+ WARN_ON(q->used); -+ -+ for (i = 0; i < q->entries; i++) { -+ usb_poison_urb(q->e[i].urb); -+ usb_free_urb(q->e[i].urb); -+ } -+} -+ -+static void mt7601u_free_tx(struct mt7601u_dev *dev) -+{ -+ int i; -+ -+ for (i = 0; i < __MT_EP_OUT_MAX; i++) -+ mt7601u_free_tx_queue(&dev->tx_q[i]); -+} -+ -+static int mt7601u_alloc_tx_queue(struct mt7601u_dev *dev, -+ struct mt7601u_tx_queue *q) -+{ -+ int i; -+ -+ q->dev = dev; -+ q->entries = N_TX_ENTRIES; -+ -+ for (i = 0; i < N_TX_ENTRIES; i++) { -+ q->e[i].urb = usb_alloc_urb(0, GFP_KERNEL); -+ if (!q->e[i].urb) -+ return -ENOMEM; -+ } -+ -+ return 0; -+} -+ -+static int mt7601u_alloc_tx(struct mt7601u_dev *dev) -+{ -+ int i; -+ -+ dev->tx_q = devm_kcalloc(dev->dev, __MT_EP_OUT_MAX, -+ sizeof(*dev->tx_q), GFP_KERNEL); -+ -+ for (i = 0; i < __MT_EP_OUT_MAX; i++) -+ if (mt7601u_alloc_tx_queue(dev, &dev->tx_q[i])) -+ return -ENOMEM; -+ -+ return 0; -+} -+ -+int mt7601u_dma_init(struct mt7601u_dev *dev) -+{ -+ int ret = -ENOMEM; -+ -+ tasklet_init(&dev->tx_tasklet, mt7601u_tx_tasklet, (unsigned long) dev); -+ tasklet_init(&dev->rx_tasklet, mt7601u_rx_tasklet, (unsigned long) dev); -+ -+ ret = mt7601u_alloc_tx(dev); -+ if (ret) -+ goto err; -+ ret = mt7601u_alloc_rx(dev); -+ if (ret) -+ goto err; -+ -+ ret = mt7601u_submit_rx(dev); -+ if (ret) -+ goto err; -+ -+ return 0; -+err: -+ mt7601u_dma_cleanup(dev); -+ return ret; -+} -+ -+void mt7601u_dma_cleanup(struct mt7601u_dev *dev) -+{ -+ mt7601u_kill_rx(dev); -+ -+ tasklet_kill(&dev->rx_tasklet); -+ -+ mt7601u_free_rx(dev); -+ mt7601u_free_tx(dev); -+ -+ tasklet_kill(&dev->tx_tasklet); -+} -diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/dma.h linux-rpi/drivers/net/wireless/mediatek/mt7601u/dma.h ---- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/dma.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/dma.h 2015-11-29 09:42:38.887167260 +0100 -@@ -0,0 +1,127 @@ -+/* -+ * Copyright (C) 2014 Felix Fietkau -+ * Copyright (C) 2015 Jakub Kicinski -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 -+ * as published by the Free Software Foundation -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#ifndef __MT7601U_DMA_H -+#define __MT7601U_DMA_H -+ -+#include -+#include -+ -+#include "util.h" -+ -+#define MT_DMA_HDR_LEN 4 -+#define MT_RX_INFO_LEN 4 -+#define MT_FCE_INFO_LEN 4 -+#define MT_DMA_HDRS (MT_DMA_HDR_LEN + MT_RX_INFO_LEN) -+ -+/* Common Tx DMA descriptor fields */ -+#define MT_TXD_INFO_LEN GENMASK(15, 0) -+#define MT_TXD_INFO_D_PORT GENMASK(29, 27) -+#define MT_TXD_INFO_TYPE GENMASK(31, 30) -+ -+enum mt76_msg_port { -+ WLAN_PORT, -+ CPU_RX_PORT, -+ CPU_TX_PORT, -+ HOST_PORT, -+ VIRTUAL_CPU_RX_PORT, -+ VIRTUAL_CPU_TX_PORT, -+ DISCARD, -+}; -+ -+enum mt76_info_type { -+ DMA_PACKET, -+ DMA_COMMAND, -+}; -+ -+/* Tx DMA packet specific flags */ -+#define MT_TXD_PKT_INFO_NEXT_VLD BIT(16) -+#define MT_TXD_PKT_INFO_TX_BURST BIT(17) -+#define MT_TXD_PKT_INFO_80211 BIT(19) -+#define MT_TXD_PKT_INFO_TSO BIT(20) -+#define MT_TXD_PKT_INFO_CSO BIT(21) -+#define MT_TXD_PKT_INFO_WIV BIT(24) -+#define MT_TXD_PKT_INFO_QSEL GENMASK(26, 25) -+ -+enum mt76_qsel { -+ MT_QSEL_MGMT, -+ MT_QSEL_HCCA, -+ MT_QSEL_EDCA, -+ MT_QSEL_EDCA_2, -+}; -+ -+/* Tx DMA MCU command specific flags */ -+#define MT_TXD_CMD_INFO_SEQ GENMASK(19, 16) -+#define MT_TXD_CMD_INFO_TYPE GENMASK(26, 20) -+ -+static inline int mt7601u_dma_skb_wrap(struct sk_buff *skb, -+ enum mt76_msg_port d_port, -+ enum mt76_info_type type, u32 flags) -+{ -+ u32 info; -+ -+ /* Buffer layout: -+ * | 4B | xfer len | pad | 4B | -+ * | TXINFO | pkt/cmd | zero pad to 4B | zero | -+ * -+ * length field of TXINFO should be set to 'xfer len'. -+ */ -+ -+ info = flags | -+ MT76_SET(MT_TXD_INFO_LEN, round_up(skb->len, 4)) | -+ MT76_SET(MT_TXD_INFO_D_PORT, d_port) | -+ MT76_SET(MT_TXD_INFO_TYPE, type); -+ -+ put_unaligned_le32(info, skb_push(skb, sizeof(info))); -+ return skb_put_padto(skb, round_up(skb->len, 4) + 4); -+} -+ -+static inline int -+mt7601u_dma_skb_wrap_pkt(struct sk_buff *skb, enum mt76_qsel qsel, u32 flags) -+{ -+ flags |= MT76_SET(MT_TXD_PKT_INFO_QSEL, qsel); -+ return mt7601u_dma_skb_wrap(skb, WLAN_PORT, DMA_PACKET, flags); -+} -+ -+/* Common Rx DMA descriptor fields */ -+#define MT_RXD_INFO_LEN GENMASK(13, 0) -+#define MT_RXD_INFO_PCIE_INTR BIT(24) -+#define MT_RXD_INFO_QSEL GENMASK(26, 25) -+#define MT_RXD_INFO_PORT GENMASK(29, 27) -+#define MT_RXD_INFO_TYPE GENMASK(31, 30) -+ -+/* Rx DMA packet specific flags */ -+#define MT_RXD_PKT_INFO_UDP_ERR BIT(16) -+#define MT_RXD_PKT_INFO_TCP_ERR BIT(17) -+#define MT_RXD_PKT_INFO_IP_ERR BIT(18) -+#define MT_RXD_PKT_INFO_PKT_80211 BIT(19) -+#define MT_RXD_PKT_INFO_L3L4_DONE BIT(20) -+#define MT_RXD_PKT_INFO_MAC_LEN GENMASK(23, 21) -+ -+/* Rx DMA MCU command specific flags */ -+#define MT_RXD_CMD_INFO_SELF_GEN BIT(15) -+#define MT_RXD_CMD_INFO_CMD_SEQ GENMASK(19, 16) -+#define MT_RXD_CMD_INFO_EVT_TYPE GENMASK(23, 20) -+ -+enum mt76_evt_type { -+ CMD_DONE, -+ CMD_ERROR, -+ CMD_RETRY, -+ EVENT_PWR_RSP, -+ EVENT_WOW_RSP, -+ EVENT_CARRIER_DETECT_RSP, -+ EVENT_DFS_DETECT_RSP, -+}; -+ -+#endif -diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/eeprom.c linux-rpi/drivers/net/wireless/mediatek/mt7601u/eeprom.c ---- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/eeprom.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/eeprom.c 2015-11-29 09:42:38.887167260 +0100 -@@ -0,0 +1,418 @@ -+/* -+ * Copyright (C) 2014 Felix Fietkau -+ * Copyright (C) 2015 Jakub Kicinski -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 -+ * as published by the Free Software Foundation -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "mt7601u.h" -+#include "eeprom.h" -+ -+static bool -+field_valid(u8 val) -+{ -+ return val != 0xff; -+} -+ -+static s8 -+field_validate(u8 val) -+{ -+ if (!field_valid(val)) -+ return 0; -+ -+ return val; -+} -+ -+static int -+mt7601u_efuse_read(struct mt7601u_dev *dev, u16 addr, u8 *data, -+ enum mt7601u_eeprom_access_modes mode) -+{ -+ u32 val; -+ int i; -+ -+ val = mt76_rr(dev, MT_EFUSE_CTRL); -+ val &= ~(MT_EFUSE_CTRL_AIN | -+ MT_EFUSE_CTRL_MODE); -+ val |= MT76_SET(MT_EFUSE_CTRL_AIN, addr & ~0xf) | -+ MT76_SET(MT_EFUSE_CTRL_MODE, mode) | -+ MT_EFUSE_CTRL_KICK; -+ mt76_wr(dev, MT_EFUSE_CTRL, val); -+ -+ if (!mt76_poll(dev, MT_EFUSE_CTRL, MT_EFUSE_CTRL_KICK, 0, 1000)) -+ return -ETIMEDOUT; -+ -+ val = mt76_rr(dev, MT_EFUSE_CTRL); -+ if ((val & MT_EFUSE_CTRL_AOUT) == MT_EFUSE_CTRL_AOUT) { -+ /* Parts of eeprom not in the usage map (0x80-0xc0,0xf0) -+ * will not return valid data but it's ok. -+ */ -+ memset(data, 0xff, 16); -+ return 0; -+ } -+ -+ for (i = 0; i < 4; i++) { -+ val = mt76_rr(dev, MT_EFUSE_DATA(i)); -+ put_unaligned_le32(val, data + 4 * i); -+ } -+ -+ return 0; -+} -+ -+static int -+mt7601u_efuse_physical_size_check(struct mt7601u_dev *dev) -+{ -+ const int map_reads = DIV_ROUND_UP(MT_EFUSE_USAGE_MAP_SIZE, 16); -+ u8 data[map_reads * 16]; -+ int ret, i; -+ u32 start = 0, end = 0, cnt_free; -+ -+ for (i = 0; i < map_reads; i++) { -+ ret = mt7601u_efuse_read(dev, MT_EE_USAGE_MAP_START + i * 16, -+ data + i * 16, MT_EE_PHYSICAL_READ); -+ if (ret) -+ return ret; -+ } -+ -+ for (i = 0; i < MT_EFUSE_USAGE_MAP_SIZE; i++) -+ if (!data[i]) { -+ if (!start) -+ start = MT_EE_USAGE_MAP_START + i; -+ end = MT_EE_USAGE_MAP_START + i; -+ } -+ cnt_free = end - start + 1; -+ -+ if (MT_EFUSE_USAGE_MAP_SIZE - cnt_free < 5) { -+ dev_err(dev->dev, "Error: your device needs default EEPROM file and this driver doesn't support it!\n"); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static bool -+mt7601u_has_tssi(struct mt7601u_dev *dev, u8 *eeprom) -+{ -+ u16 nic_conf1 = get_unaligned_le16(eeprom + MT_EE_NIC_CONF_1); -+ -+ return ~nic_conf1 && (nic_conf1 & MT_EE_NIC_CONF_1_TX_ALC_EN); -+} -+ -+static void -+mt7601u_set_chip_cap(struct mt7601u_dev *dev, u8 *eeprom) -+{ -+ u16 nic_conf0 = get_unaligned_le16(eeprom + MT_EE_NIC_CONF_0); -+ u16 nic_conf1 = get_unaligned_le16(eeprom + MT_EE_NIC_CONF_1); -+ -+ if (!field_valid(nic_conf1 & 0xff)) -+ nic_conf1 &= 0xff00; -+ -+ dev->ee->tssi_enabled = mt7601u_has_tssi(dev, eeprom) && -+ !(nic_conf1 & MT_EE_NIC_CONF_1_TEMP_TX_ALC); -+ -+ if (nic_conf1 & MT_EE_NIC_CONF_1_HW_RF_CTRL) -+ dev_err(dev->dev, -+ "Error: this driver does not support HW RF ctrl\n"); -+ -+ if (!field_valid(nic_conf0 >> 8)) -+ return; -+ -+ if (MT76_GET(MT_EE_NIC_CONF_0_RX_PATH, nic_conf0) > 1 || -+ MT76_GET(MT_EE_NIC_CONF_0_TX_PATH, nic_conf0) > 1) -+ dev_err(dev->dev, -+ "Error: device has more than 1 RX/TX stream!\n"); -+} -+ -+static int -+mt7601u_set_macaddr(struct mt7601u_dev *dev, const u8 *eeprom) -+{ -+ const void *src = eeprom + MT_EE_MAC_ADDR; -+ -+ ether_addr_copy(dev->macaddr, src); -+ -+ if (!is_valid_ether_addr(dev->macaddr)) { -+ eth_random_addr(dev->macaddr); -+ dev_info(dev->dev, -+ "Invalid MAC address, using random address %pM\n", -+ dev->macaddr); -+ } -+ -+ mt76_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(dev->macaddr)); -+ mt76_wr(dev, MT_MAC_ADDR_DW1, get_unaligned_le16(dev->macaddr + 4) | -+ MT76_SET(MT_MAC_ADDR_DW1_U2ME_MASK, 0xff)); -+ -+ return 0; -+} -+ -+static void mt7601u_set_channel_target_power(struct mt7601u_dev *dev, -+ u8 *eeprom, u8 max_pwr) -+{ -+ u8 trgt_pwr = eeprom[MT_EE_TX_TSSI_TARGET_POWER]; -+ -+ if (trgt_pwr > max_pwr || !trgt_pwr) { -+ dev_warn(dev->dev, "Error: EEPROM trgt power invalid %hhx!\n", -+ trgt_pwr); -+ trgt_pwr = 0x20; -+ } -+ -+ memset(dev->ee->chan_pwr, trgt_pwr, sizeof(dev->ee->chan_pwr)); -+} -+ -+static void -+mt7601u_set_channel_power(struct mt7601u_dev *dev, u8 *eeprom) -+{ -+ u32 i, val; -+ u8 max_pwr; -+ -+ val = mt7601u_rr(dev, MT_TX_ALC_CFG_0); -+ max_pwr = MT76_GET(MT_TX_ALC_CFG_0_LIMIT_0, val); -+ -+ if (mt7601u_has_tssi(dev, eeprom)) { -+ mt7601u_set_channel_target_power(dev, eeprom, max_pwr); -+ return; -+ } -+ -+ for (i = 0; i < 14; i++) { -+ s8 power = field_validate(eeprom[MT_EE_TX_POWER_OFFSET + i]); -+ -+ if (power > max_pwr || power < 0) -+ power = MT7601U_DEFAULT_TX_POWER; -+ -+ dev->ee->chan_pwr[i] = power; -+ } -+} -+ -+static void -+mt7601u_set_country_reg(struct mt7601u_dev *dev, u8 *eeprom) -+{ -+ /* Note: - region 31 is not valid for mt7601u (see rtmp_init.c) -+ * - comments in rtmp_def.h are incorrect (see rt_channel.c) -+ */ -+ static const struct reg_channel_bounds chan_bounds[] = { -+ /* EEPROM country regions 0 - 7 */ -+ { 1, 11 }, { 1, 13 }, { 10, 2 }, { 10, 4 }, -+ { 14, 1 }, { 1, 14 }, { 3, 7 }, { 5, 9 }, -+ /* EEPROM country regions 32 - 33 */ -+ { 1, 11 }, { 1, 14 } -+ }; -+ u8 val = eeprom[MT_EE_COUNTRY_REGION]; -+ int idx = -1; -+ -+ if (val < 8) -+ idx = val; -+ if (val > 31 && val < 33) -+ idx = val - 32 + 8; -+ -+ if (idx != -1) -+ dev_info(dev->dev, -+ "EEPROM country region %02hhx (channels %hhd-%hhd)\n", -+ val, chan_bounds[idx].start, -+ chan_bounds[idx].start + chan_bounds[idx].num - 1); -+ else -+ idx = 5; /* channels 1 - 14 */ -+ -+ dev->ee->reg = chan_bounds[idx]; -+ -+ /* TODO: country region 33 is special - phy should be set to B-mode -+ * before entering channel 14 (see sta/connect.c) -+ */ -+} -+ -+static void -+mt7601u_set_rf_freq_off(struct mt7601u_dev *dev, u8 *eeprom) -+{ -+ u8 comp; -+ -+ dev->ee->rf_freq_off = field_validate(eeprom[MT_EE_FREQ_OFFSET]); -+ comp = field_validate(eeprom[MT_EE_FREQ_OFFSET_COMPENSATION]); -+ -+ if (comp & BIT(7)) -+ dev->ee->rf_freq_off -= comp & 0x7f; -+ else -+ dev->ee->rf_freq_off += comp; -+} -+ -+static void -+mt7601u_set_rssi_offset(struct mt7601u_dev *dev, u8 *eeprom) -+{ -+ int i; -+ s8 *rssi_offset = dev->ee->rssi_offset; -+ -+ for (i = 0; i < 2; i++) { -+ rssi_offset[i] = eeprom[MT_EE_RSSI_OFFSET + i]; -+ -+ if (rssi_offset[i] < -10 || rssi_offset[i] > 10) { -+ dev_warn(dev->dev, -+ "Warning: EEPROM RSSI is invalid %02hhx\n", -+ rssi_offset[i]); -+ rssi_offset[i] = 0; -+ } -+ } -+} -+ -+static void -+mt7601u_extra_power_over_mac(struct mt7601u_dev *dev) -+{ -+ u32 val; -+ -+ val = ((mt7601u_rr(dev, MT_TX_PWR_CFG_1) & 0x0000ff00) >> 8); -+ val |= ((mt7601u_rr(dev, MT_TX_PWR_CFG_2) & 0x0000ff00) << 8); -+ mt7601u_wr(dev, MT_TX_PWR_CFG_7, val); -+ -+ val = ((mt7601u_rr(dev, MT_TX_PWR_CFG_4) & 0x0000ff00) >> 8); -+ mt7601u_wr(dev, MT_TX_PWR_CFG_9, val); -+} -+ -+static void -+mt7601u_set_power_rate(struct power_per_rate *rate, s8 delta, u8 value) -+{ -+ /* Invalid? Note: vendor driver does not handle this */ -+ if (value == 0xff) -+ return; -+ -+ rate->raw = s6_validate(value); -+ rate->bw20 = s6_to_int(value); -+ /* Note: vendor driver does cap the value to s6 right away */ -+ rate->bw40 = rate->bw20 + delta; -+} -+ -+static void -+mt7601u_save_power_rate(struct mt7601u_dev *dev, s8 delta, u32 val, int i) -+{ -+ struct mt7601u_rate_power *t = &dev->ee->power_rate_table; -+ -+ switch (i) { -+ case 0: -+ mt7601u_set_power_rate(&t->cck[0], delta, (val >> 0) & 0xff); -+ mt7601u_set_power_rate(&t->cck[1], delta, (val >> 8) & 0xff); -+ /* Save cck bw20 for fixups of channel 14 */ -+ dev->ee->real_cck_bw20[0] = t->cck[0].bw20; -+ dev->ee->real_cck_bw20[1] = t->cck[1].bw20; -+ -+ mt7601u_set_power_rate(&t->ofdm[0], delta, (val >> 16) & 0xff); -+ mt7601u_set_power_rate(&t->ofdm[1], delta, (val >> 24) & 0xff); -+ break; -+ case 1: -+ mt7601u_set_power_rate(&t->ofdm[2], delta, (val >> 0) & 0xff); -+ mt7601u_set_power_rate(&t->ofdm[3], delta, (val >> 8) & 0xff); -+ mt7601u_set_power_rate(&t->ht[0], delta, (val >> 16) & 0xff); -+ mt7601u_set_power_rate(&t->ht[1], delta, (val >> 24) & 0xff); -+ break; -+ case 2: -+ mt7601u_set_power_rate(&t->ht[2], delta, (val >> 0) & 0xff); -+ mt7601u_set_power_rate(&t->ht[3], delta, (val >> 8) & 0xff); -+ break; -+ } -+} -+ -+static s8 -+get_delta(u8 val) -+{ -+ s8 ret; -+ -+ if (!field_valid(val) || !(val & BIT(7))) -+ return 0; -+ -+ ret = val & 0x1f; -+ if (ret > 8) -+ ret = 8; -+ if (val & BIT(6)) -+ ret = -ret; -+ -+ return ret; -+} -+ -+static void -+mt7601u_config_tx_power_per_rate(struct mt7601u_dev *dev, u8 *eeprom) -+{ -+ u32 val; -+ s8 bw40_delta; -+ int i; -+ -+ bw40_delta = get_delta(eeprom[MT_EE_TX_POWER_DELTA_BW40]); -+ -+ for (i = 0; i < 5; i++) { -+ val = get_unaligned_le32(eeprom + MT_EE_TX_POWER_BYRATE(i)); -+ -+ mt7601u_save_power_rate(dev, bw40_delta, val, i); -+ -+ if (~val) -+ mt7601u_wr(dev, MT_TX_PWR_CFG_0 + i * 4, val); -+ } -+ -+ mt7601u_extra_power_over_mac(dev); -+} -+ -+static void -+mt7601u_init_tssi_params(struct mt7601u_dev *dev, u8 *eeprom) -+{ -+ struct tssi_data *d = &dev->ee->tssi_data; -+ -+ if (!dev->ee->tssi_enabled) -+ return; -+ -+ d->slope = eeprom[MT_EE_TX_TSSI_SLOPE]; -+ d->tx0_delta_offset = eeprom[MT_EE_TX_TSSI_OFFSET] * 1024; -+ d->offset[0] = eeprom[MT_EE_TX_TSSI_OFFSET_GROUP]; -+ d->offset[1] = eeprom[MT_EE_TX_TSSI_OFFSET_GROUP + 1]; -+ d->offset[2] = eeprom[MT_EE_TX_TSSI_OFFSET_GROUP + 2]; -+} -+ -+int -+mt7601u_eeprom_init(struct mt7601u_dev *dev) -+{ -+ u8 *eeprom; -+ int i, ret; -+ -+ ret = mt7601u_efuse_physical_size_check(dev); -+ if (ret) -+ return ret; -+ -+ dev->ee = devm_kzalloc(dev->dev, sizeof(*dev->ee), GFP_KERNEL); -+ if (!dev->ee) -+ return -ENOMEM; -+ -+ eeprom = kmalloc(MT7601U_EEPROM_SIZE, GFP_KERNEL); -+ if (!eeprom) -+ return -ENOMEM; -+ -+ for (i = 0; i + 16 <= MT7601U_EEPROM_SIZE; i += 16) { -+ ret = mt7601u_efuse_read(dev, i, eeprom + i, MT_EE_READ); -+ if (ret) -+ goto out; -+ } -+ -+ if (eeprom[MT_EE_VERSION_EE] > MT7601U_EE_MAX_VER) -+ dev_warn(dev->dev, -+ "Warning: unsupported EEPROM version %02hhx\n", -+ eeprom[MT_EE_VERSION_EE]); -+ dev_info(dev->dev, "EEPROM ver:%02hhx fae:%02hhx\n", -+ eeprom[MT_EE_VERSION_EE], eeprom[MT_EE_VERSION_FAE]); -+ -+ mt7601u_set_macaddr(dev, eeprom); -+ mt7601u_set_chip_cap(dev, eeprom); -+ mt7601u_set_channel_power(dev, eeprom); -+ mt7601u_set_country_reg(dev, eeprom); -+ mt7601u_set_rf_freq_off(dev, eeprom); -+ mt7601u_set_rssi_offset(dev, eeprom); -+ dev->ee->ref_temp = eeprom[MT_EE_REF_TEMP]; -+ dev->ee->lna_gain = eeprom[MT_EE_LNA_GAIN]; -+ -+ mt7601u_config_tx_power_per_rate(dev, eeprom); -+ -+ mt7601u_init_tssi_params(dev, eeprom); -+out: -+ kfree(eeprom); -+ return ret; -+} -diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/eeprom.h linux-rpi/drivers/net/wireless/mediatek/mt7601u/eeprom.h ---- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/eeprom.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/eeprom.h 2015-11-29 09:42:38.887167260 +0100 -@@ -0,0 +1,151 @@ -+/* -+ * Copyright (C) 2014 Felix Fietkau -+ * Copyright (C) 2015 Jakub Kicinski -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 -+ * as published by the Free Software Foundation -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#ifndef __MT7601U_EEPROM_H -+#define __MT7601U_EEPROM_H -+ -+struct mt7601u_dev; -+ -+#define MT7601U_EE_MAX_VER 0x0c -+#define MT7601U_EEPROM_SIZE 256 -+ -+#define MT7601U_DEFAULT_TX_POWER 6 -+ -+enum mt76_eeprom_field { -+ MT_EE_CHIP_ID = 0x00, -+ MT_EE_VERSION_FAE = 0x02, -+ MT_EE_VERSION_EE = 0x03, -+ MT_EE_MAC_ADDR = 0x04, -+ MT_EE_NIC_CONF_0 = 0x34, -+ MT_EE_NIC_CONF_1 = 0x36, -+ MT_EE_COUNTRY_REGION = 0x39, -+ MT_EE_FREQ_OFFSET = 0x3a, -+ MT_EE_NIC_CONF_2 = 0x42, -+ -+ MT_EE_LNA_GAIN = 0x44, -+ MT_EE_RSSI_OFFSET = 0x46, -+ -+ MT_EE_TX_POWER_DELTA_BW40 = 0x50, -+ MT_EE_TX_POWER_OFFSET = 0x52, -+ -+ MT_EE_TX_TSSI_SLOPE = 0x6e, -+ MT_EE_TX_TSSI_OFFSET_GROUP = 0x6f, -+ MT_EE_TX_TSSI_OFFSET = 0x76, -+ -+ MT_EE_TX_TSSI_TARGET_POWER = 0xd0, -+ MT_EE_REF_TEMP = 0xd1, -+ MT_EE_FREQ_OFFSET_COMPENSATION = 0xdb, -+ MT_EE_TX_POWER_BYRATE_BASE = 0xde, -+ -+ MT_EE_USAGE_MAP_START = 0x1e0, -+ MT_EE_USAGE_MAP_END = 0x1fc, -+}; -+ -+#define MT_EE_NIC_CONF_0_RX_PATH GENMASK(3, 0) -+#define MT_EE_NIC_CONF_0_TX_PATH GENMASK(7, 4) -+#define MT_EE_NIC_CONF_0_BOARD_TYPE GENMASK(13, 12) -+ -+#define MT_EE_NIC_CONF_1_HW_RF_CTRL BIT(0) -+#define MT_EE_NIC_CONF_1_TEMP_TX_ALC BIT(1) -+#define MT_EE_NIC_CONF_1_LNA_EXT_2G BIT(2) -+#define MT_EE_NIC_CONF_1_LNA_EXT_5G BIT(3) -+#define MT_EE_NIC_CONF_1_TX_ALC_EN BIT(13) -+ -+#define MT_EE_NIC_CONF_2_RX_STREAM GENMASK(3, 0) -+#define MT_EE_NIC_CONF_2_TX_STREAM GENMASK(7, 4) -+#define MT_EE_NIC_CONF_2_HW_ANTDIV BIT(8) -+#define MT_EE_NIC_CONF_2_XTAL_OPTION GENMASK(10, 9) -+#define MT_EE_NIC_CONF_2_TEMP_DISABLE BIT(11) -+#define MT_EE_NIC_CONF_2_COEX_METHOD GENMASK(15, 13) -+ -+#define MT_EE_TX_POWER_BYRATE(i) (MT_EE_TX_POWER_BYRATE_BASE + \ -+ (i) * 4) -+ -+#define MT_EFUSE_USAGE_MAP_SIZE (MT_EE_USAGE_MAP_END - \ -+ MT_EE_USAGE_MAP_START + 1) -+ -+enum mt7601u_eeprom_access_modes { -+ MT_EE_READ = 0, -+ MT_EE_PHYSICAL_READ = 1, -+}; -+ -+struct power_per_rate { -+ u8 raw; /* validated s6 value */ -+ s8 bw20; /* sign-extended int */ -+ s8 bw40; /* sign-extended int */ -+}; -+ -+/* Power per rate - one value per two rates */ -+struct mt7601u_rate_power { -+ struct power_per_rate cck[2]; -+ struct power_per_rate ofdm[4]; -+ struct power_per_rate ht[4]; -+}; -+ -+struct reg_channel_bounds { -+ u8 start; -+ u8 num; -+}; -+ -+struct mt7601u_eeprom_params { -+ bool tssi_enabled; -+ u8 rf_freq_off; -+ s8 rssi_offset[2]; -+ s8 ref_temp; -+ s8 lna_gain; -+ -+ u8 chan_pwr[14]; -+ struct mt7601u_rate_power power_rate_table; -+ s8 real_cck_bw20[2]; -+ -+ /* TSSI stuff - only with internal TX ALC */ -+ struct tssi_data { -+ int tx0_delta_offset; -+ u8 slope; -+ u8 offset[3]; -+ } tssi_data; -+ -+ struct reg_channel_bounds reg; -+}; -+ -+int mt7601u_eeprom_init(struct mt7601u_dev *dev); -+ -+static inline u32 s6_validate(u32 reg) -+{ -+ WARN_ON(reg & ~GENMASK(5, 0)); -+ return reg & GENMASK(5, 0); -+} -+ -+static inline int s6_to_int(u32 reg) -+{ -+ int s6; -+ -+ s6 = s6_validate(reg); -+ if (s6 & BIT(5)) -+ s6 -= BIT(6); -+ -+ return s6; -+} -+ -+static inline u32 int_to_s6(int val) -+{ -+ if (val < -0x20) -+ return 0x20; -+ if (val > 0x1f) -+ return 0x1f; -+ -+ return val & 0x3f; -+} -+ -+#endif -diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/init.c linux-rpi/drivers/net/wireless/mediatek/mt7601u/init.c ---- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/init.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/init.c 2015-11-29 09:42:38.887167260 +0100 -@@ -0,0 +1,630 @@ -+/* -+ * (c) Copyright 2002-2010, Ralink Technology, Inc. -+ * Copyright (C) 2014 Felix Fietkau -+ * Copyright (C) 2015 Jakub Kicinski -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 -+ * as published by the Free Software Foundation -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include "mt7601u.h" -+#include "eeprom.h" -+#include "trace.h" -+#include "mcu.h" -+ -+#include "initvals.h" -+ -+static void -+mt7601u_set_wlan_state(struct mt7601u_dev *dev, u32 val, bool enable) -+{ -+ int i; -+ -+ /* Note: we don't turn off WLAN_CLK because that makes the device -+ * not respond properly on the probe path. -+ * In case anyone (PSM?) wants to use this function we can -+ * bring the clock stuff back and fixup the probe path. -+ */ -+ -+ if (enable) -+ val |= (MT_WLAN_FUN_CTRL_WLAN_EN | -+ MT_WLAN_FUN_CTRL_WLAN_CLK_EN); -+ else -+ val &= ~(MT_WLAN_FUN_CTRL_WLAN_EN); -+ -+ mt7601u_wr(dev, MT_WLAN_FUN_CTRL, val); -+ udelay(20); -+ -+ if (enable) { -+ set_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state); -+ } else { -+ clear_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state); -+ return; -+ } -+ -+ for (i = 200; i; i--) { -+ val = mt7601u_rr(dev, MT_CMB_CTRL); -+ -+ if (val & MT_CMB_CTRL_XTAL_RDY && val & MT_CMB_CTRL_PLL_LD) -+ break; -+ -+ udelay(20); -+ } -+ -+ /* Note: vendor driver tries to disable/enable wlan here and retry -+ * but the code which does it is so buggy it must have never -+ * triggered, so don't bother. -+ */ -+ if (!i) -+ dev_err(dev->dev, "Error: PLL and XTAL check failed!\n"); -+} -+ -+static void mt7601u_chip_onoff(struct mt7601u_dev *dev, bool enable, bool reset) -+{ -+ u32 val; -+ -+ mutex_lock(&dev->hw_atomic_mutex); -+ -+ val = mt7601u_rr(dev, MT_WLAN_FUN_CTRL); -+ -+ if (reset) { -+ val |= MT_WLAN_FUN_CTRL_GPIO_OUT_EN; -+ val &= ~MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL; -+ -+ if (val & MT_WLAN_FUN_CTRL_WLAN_EN) { -+ val |= (MT_WLAN_FUN_CTRL_WLAN_RESET | -+ MT_WLAN_FUN_CTRL_WLAN_RESET_RF); -+ mt7601u_wr(dev, MT_WLAN_FUN_CTRL, val); -+ udelay(20); -+ -+ val &= ~(MT_WLAN_FUN_CTRL_WLAN_RESET | -+ MT_WLAN_FUN_CTRL_WLAN_RESET_RF); -+ } -+ } -+ -+ mt7601u_wr(dev, MT_WLAN_FUN_CTRL, val); -+ udelay(20); -+ -+ mt7601u_set_wlan_state(dev, val, enable); -+ -+ mutex_unlock(&dev->hw_atomic_mutex); -+} -+ -+static void mt7601u_reset_csr_bbp(struct mt7601u_dev *dev) -+{ -+ mt7601u_wr(dev, MT_MAC_SYS_CTRL, (MT_MAC_SYS_CTRL_RESET_CSR | -+ MT_MAC_SYS_CTRL_RESET_BBP)); -+ mt7601u_wr(dev, MT_USB_DMA_CFG, 0); -+ msleep(1); -+ mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0); -+} -+ -+static void mt7601u_init_usb_dma(struct mt7601u_dev *dev) -+{ -+ u32 val; -+ -+ val = MT76_SET(MT_USB_DMA_CFG_RX_BULK_AGG_TOUT, MT_USB_AGGR_TIMEOUT) | -+ MT76_SET(MT_USB_DMA_CFG_RX_BULK_AGG_LMT, MT_USB_AGGR_SIZE_LIMIT) | -+ MT_USB_DMA_CFG_RX_BULK_EN | -+ MT_USB_DMA_CFG_TX_BULK_EN; -+ if (dev->in_max_packet == 512) -+ val |= MT_USB_DMA_CFG_RX_BULK_AGG_EN; -+ mt7601u_wr(dev, MT_USB_DMA_CFG, val); -+ -+ val |= MT_USB_DMA_CFG_UDMA_RX_WL_DROP; -+ mt7601u_wr(dev, MT_USB_DMA_CFG, val); -+ val &= ~MT_USB_DMA_CFG_UDMA_RX_WL_DROP; -+ mt7601u_wr(dev, MT_USB_DMA_CFG, val); -+} -+ -+static int mt7601u_init_bbp(struct mt7601u_dev *dev) -+{ -+ int ret; -+ -+ ret = mt7601u_wait_bbp_ready(dev); -+ if (ret) -+ return ret; -+ -+ ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, bbp_common_vals, -+ ARRAY_SIZE(bbp_common_vals)); -+ if (ret) -+ return ret; -+ -+ return mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, bbp_chip_vals, -+ ARRAY_SIZE(bbp_chip_vals)); -+} -+ -+static void -+mt76_init_beacon_offsets(struct mt7601u_dev *dev) -+{ -+ u16 base = MT_BEACON_BASE; -+ u32 regs[4] = {}; -+ int i; -+ -+ for (i = 0; i < 16; i++) { -+ u16 addr = dev->beacon_offsets[i]; -+ -+ regs[i / 4] |= ((addr - base) / 64) << (8 * (i % 4)); -+ } -+ -+ for (i = 0; i < 4; i++) -+ mt7601u_wr(dev, MT_BCN_OFFSET(i), regs[i]); -+} -+ -+static int mt7601u_write_mac_initvals(struct mt7601u_dev *dev) -+{ -+ int ret; -+ -+ ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_WLAN, mac_common_vals, -+ ARRAY_SIZE(mac_common_vals)); -+ if (ret) -+ return ret; -+ ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_WLAN, -+ mac_chip_vals, ARRAY_SIZE(mac_chip_vals)); -+ if (ret) -+ return ret; -+ -+ mt76_init_beacon_offsets(dev); -+ -+ mt7601u_wr(dev, MT_AUX_CLK_CFG, 0); -+ -+ return 0; -+} -+ -+static int mt7601u_init_wcid_mem(struct mt7601u_dev *dev) -+{ -+ u32 *vals; -+ int i, ret; -+ -+ vals = kmalloc(sizeof(*vals) * N_WCIDS * 2, GFP_KERNEL); -+ if (!vals) -+ return -ENOMEM; -+ -+ for (i = 0; i < N_WCIDS; i++) { -+ vals[i * 2] = 0xffffffff; -+ vals[i * 2 + 1] = 0x00ffffff; -+ } -+ -+ ret = mt7601u_burst_write_regs(dev, MT_WCID_ADDR_BASE, -+ vals, N_WCIDS * 2); -+ kfree(vals); -+ -+ return ret; -+} -+ -+static int mt7601u_init_key_mem(struct mt7601u_dev *dev) -+{ -+ u32 vals[4] = {}; -+ -+ return mt7601u_burst_write_regs(dev, MT_SKEY_MODE_BASE_0, -+ vals, ARRAY_SIZE(vals)); -+} -+ -+static int mt7601u_init_wcid_attr_mem(struct mt7601u_dev *dev) -+{ -+ u32 *vals; -+ int i, ret; -+ -+ vals = kmalloc(sizeof(*vals) * N_WCIDS * 2, GFP_KERNEL); -+ if (!vals) -+ return -ENOMEM; -+ -+ for (i = 0; i < N_WCIDS * 2; i++) -+ vals[i] = 1; -+ -+ ret = mt7601u_burst_write_regs(dev, MT_WCID_ATTR_BASE, -+ vals, N_WCIDS * 2); -+ kfree(vals); -+ -+ return ret; -+} -+ -+static void mt7601u_reset_counters(struct mt7601u_dev *dev) -+{ -+ mt7601u_rr(dev, MT_RX_STA_CNT0); -+ mt7601u_rr(dev, MT_RX_STA_CNT1); -+ mt7601u_rr(dev, MT_RX_STA_CNT2); -+ mt7601u_rr(dev, MT_TX_STA_CNT0); -+ mt7601u_rr(dev, MT_TX_STA_CNT1); -+ mt7601u_rr(dev, MT_TX_STA_CNT2); -+} -+ -+int mt7601u_mac_start(struct mt7601u_dev *dev) -+{ -+ mt7601u_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX); -+ -+ if (!mt76_poll(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_DMA_BUSY | -+ MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 200000)) -+ return -ETIMEDOUT; -+ -+ dev->rxfilter = MT_RX_FILTR_CFG_CRC_ERR | -+ MT_RX_FILTR_CFG_PHY_ERR | MT_RX_FILTR_CFG_PROMISC | -+ MT_RX_FILTR_CFG_VER_ERR | MT_RX_FILTR_CFG_DUP | -+ MT_RX_FILTR_CFG_CFACK | MT_RX_FILTR_CFG_CFEND | -+ MT_RX_FILTR_CFG_ACK | MT_RX_FILTR_CFG_CTS | -+ MT_RX_FILTR_CFG_RTS | MT_RX_FILTR_CFG_PSPOLL | -+ MT_RX_FILTR_CFG_BA | MT_RX_FILTR_CFG_CTRL_RSV; -+ mt7601u_wr(dev, MT_RX_FILTR_CFG, dev->rxfilter); -+ -+ mt7601u_wr(dev, MT_MAC_SYS_CTRL, -+ MT_MAC_SYS_CTRL_ENABLE_TX | MT_MAC_SYS_CTRL_ENABLE_RX); -+ -+ if (!mt76_poll(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_DMA_BUSY | -+ MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 50)) -+ return -ETIMEDOUT; -+ -+ return 0; -+} -+ -+static void mt7601u_mac_stop_hw(struct mt7601u_dev *dev) -+{ -+ int i, ok; -+ -+ if (test_bit(MT7601U_STATE_REMOVED, &dev->state)) -+ return; -+ -+ mt76_clear(dev, MT_BEACON_TIME_CFG, MT_BEACON_TIME_CFG_TIMER_EN | -+ MT_BEACON_TIME_CFG_SYNC_MODE | MT_BEACON_TIME_CFG_TBTT_EN | -+ MT_BEACON_TIME_CFG_BEACON_TX); -+ -+ if (!mt76_poll(dev, MT_USB_DMA_CFG, MT_USB_DMA_CFG_TX_BUSY, 0, 1000)) -+ dev_warn(dev->dev, "Warning: TX DMA did not stop!\n"); -+ -+ /* Page count on TxQ */ -+ i = 200; -+ while (i-- && ((mt76_rr(dev, 0x0438) & 0xffffffff) || -+ (mt76_rr(dev, 0x0a30) & 0x000000ff) || -+ (mt76_rr(dev, 0x0a34) & 0x00ff00ff))) -+ msleep(10); -+ -+ if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_TX, 0, 1000)) -+ dev_warn(dev->dev, "Warning: MAC TX did not stop!\n"); -+ -+ mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX | -+ MT_MAC_SYS_CTRL_ENABLE_TX); -+ -+ /* Page count on RxQ */ -+ ok = 0; -+ i = 200; -+ while (i--) { -+ if ((mt76_rr(dev, 0x0430) & 0x00ff0000) || -+ (mt76_rr(dev, 0x0a30) & 0xffffffff) || -+ (mt76_rr(dev, 0x0a34) & 0xffffffff)) -+ ok++; -+ if (ok > 6) -+ break; -+ -+ msleep(1); -+ } -+ -+ if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_RX, 0, 1000)) -+ dev_warn(dev->dev, "Warning: MAC RX did not stop!\n"); -+ -+ if (!mt76_poll(dev, MT_USB_DMA_CFG, MT_USB_DMA_CFG_RX_BUSY, 0, 1000)) -+ dev_warn(dev->dev, "Warning: RX DMA did not stop!\n"); -+} -+ -+void mt7601u_mac_stop(struct mt7601u_dev *dev) -+{ -+ mt7601u_mac_stop_hw(dev); -+ flush_delayed_work(&dev->stat_work); -+ cancel_delayed_work_sync(&dev->stat_work); -+} -+ -+static void mt7601u_stop_hardware(struct mt7601u_dev *dev) -+{ -+ mt7601u_chip_onoff(dev, false, false); -+} -+ -+int mt7601u_init_hardware(struct mt7601u_dev *dev) -+{ -+ static const u16 beacon_offsets[16] = { -+ /* 512 byte per beacon */ -+ 0xc000, 0xc200, 0xc400, 0xc600, -+ 0xc800, 0xca00, 0xcc00, 0xce00, -+ 0xd000, 0xd200, 0xd400, 0xd600, -+ 0xd800, 0xda00, 0xdc00, 0xde00 -+ }; -+ int ret; -+ -+ dev->beacon_offsets = beacon_offsets; -+ -+ mt7601u_chip_onoff(dev, true, false); -+ -+ ret = mt7601u_wait_asic_ready(dev); -+ if (ret) -+ goto err; -+ ret = mt7601u_mcu_init(dev); -+ if (ret) -+ goto err; -+ -+ if (!mt76_poll_msec(dev, MT_WPDMA_GLO_CFG, -+ MT_WPDMA_GLO_CFG_TX_DMA_BUSY | -+ MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 100)) { -+ ret = -EIO; -+ goto err; -+ } -+ -+ /* Wait for ASIC ready after FW load. */ -+ ret = mt7601u_wait_asic_ready(dev); -+ if (ret) -+ goto err; -+ -+ mt7601u_reset_csr_bbp(dev); -+ mt7601u_init_usb_dma(dev); -+ -+ ret = mt7601u_mcu_cmd_init(dev); -+ if (ret) -+ goto err; -+ ret = mt7601u_dma_init(dev); -+ if (ret) -+ goto err_mcu; -+ ret = mt7601u_write_mac_initvals(dev); -+ if (ret) -+ goto err_rx; -+ -+ if (!mt76_poll_msec(dev, MT_MAC_STATUS, -+ MT_MAC_STATUS_TX | MT_MAC_STATUS_RX, 0, 100)) { -+ ret = -EIO; -+ goto err_rx; -+ } -+ -+ ret = mt7601u_init_bbp(dev); -+ if (ret) -+ goto err_rx; -+ ret = mt7601u_init_wcid_mem(dev); -+ if (ret) -+ goto err_rx; -+ ret = mt7601u_init_key_mem(dev); -+ if (ret) -+ goto err_rx; -+ ret = mt7601u_init_wcid_attr_mem(dev); -+ if (ret) -+ goto err_rx; -+ -+ mt76_clear(dev, MT_BEACON_TIME_CFG, (MT_BEACON_TIME_CFG_TIMER_EN | -+ MT_BEACON_TIME_CFG_SYNC_MODE | -+ MT_BEACON_TIME_CFG_TBTT_EN | -+ MT_BEACON_TIME_CFG_BEACON_TX)); -+ -+ mt7601u_reset_counters(dev); -+ -+ mt7601u_rmw(dev, MT_US_CYC_CFG, MT_US_CYC_CNT, 0x1e); -+ -+ mt7601u_wr(dev, MT_TXOP_CTRL_CFG, MT76_SET(MT_TXOP_TRUN_EN, 0x3f) | -+ MT76_SET(MT_TXOP_EXT_CCA_DLY, 0x58)); -+ -+ ret = mt7601u_eeprom_init(dev); -+ if (ret) -+ goto err_rx; -+ -+ ret = mt7601u_phy_init(dev); -+ if (ret) -+ goto err_rx; -+ -+ mt7601u_set_rx_path(dev, 0); -+ mt7601u_set_tx_dac(dev, 0); -+ -+ mt7601u_mac_set_ctrlch(dev, false); -+ mt7601u_bbp_set_ctrlch(dev, false); -+ mt7601u_bbp_set_bw(dev, MT_BW_20); -+ -+ return 0; -+ -+err_rx: -+ mt7601u_dma_cleanup(dev); -+err_mcu: -+ mt7601u_mcu_cmd_deinit(dev); -+err: -+ mt7601u_chip_onoff(dev, false, false); -+ return ret; -+} -+ -+void mt7601u_cleanup(struct mt7601u_dev *dev) -+{ -+ if (!test_and_clear_bit(MT7601U_STATE_INITIALIZED, &dev->state)) -+ return; -+ -+ mt7601u_stop_hardware(dev); -+ mt7601u_dma_cleanup(dev); -+ mt7601u_mcu_cmd_deinit(dev); -+} -+ -+struct mt7601u_dev *mt7601u_alloc_device(struct device *pdev) -+{ -+ struct ieee80211_hw *hw; -+ struct mt7601u_dev *dev; -+ -+ hw = ieee80211_alloc_hw(sizeof(*dev), &mt7601u_ops); -+ if (!hw) -+ return NULL; -+ -+ dev = hw->priv; -+ dev->dev = pdev; -+ dev->hw = hw; -+ mutex_init(&dev->vendor_req_mutex); -+ mutex_init(&dev->reg_atomic_mutex); -+ mutex_init(&dev->hw_atomic_mutex); -+ mutex_init(&dev->mutex); -+ spin_lock_init(&dev->tx_lock); -+ spin_lock_init(&dev->rx_lock); -+ spin_lock_init(&dev->lock); -+ spin_lock_init(&dev->mac_lock); -+ spin_lock_init(&dev->con_mon_lock); -+ atomic_set(&dev->avg_ampdu_len, 1); -+ skb_queue_head_init(&dev->tx_skb_done); -+ -+ dev->stat_wq = alloc_workqueue("mt7601u", WQ_UNBOUND, 0); -+ if (!dev->stat_wq) { -+ ieee80211_free_hw(hw); -+ return NULL; -+ } -+ -+ return dev; -+} -+ -+#define CHAN2G(_idx, _freq) { \ -+ .band = IEEE80211_BAND_2GHZ, \ -+ .center_freq = (_freq), \ -+ .hw_value = (_idx), \ -+ .max_power = 30, \ -+} -+ -+static const struct ieee80211_channel mt76_channels_2ghz[] = { -+ CHAN2G(1, 2412), -+ CHAN2G(2, 2417), -+ CHAN2G(3, 2422), -+ CHAN2G(4, 2427), -+ CHAN2G(5, 2432), -+ CHAN2G(6, 2437), -+ CHAN2G(7, 2442), -+ CHAN2G(8, 2447), -+ CHAN2G(9, 2452), -+ CHAN2G(10, 2457), -+ CHAN2G(11, 2462), -+ CHAN2G(12, 2467), -+ CHAN2G(13, 2472), -+ CHAN2G(14, 2484), -+}; -+ -+#define CCK_RATE(_idx, _rate) { \ -+ .bitrate = _rate, \ -+ .flags = IEEE80211_RATE_SHORT_PREAMBLE, \ -+ .hw_value = (MT_PHY_TYPE_CCK << 8) | _idx, \ -+ .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (8 + _idx), \ -+} -+ -+#define OFDM_RATE(_idx, _rate) { \ -+ .bitrate = _rate, \ -+ .hw_value = (MT_PHY_TYPE_OFDM << 8) | _idx, \ -+ .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | _idx, \ -+} -+ -+static struct ieee80211_rate mt76_rates[] = { -+ CCK_RATE(0, 10), -+ CCK_RATE(1, 20), -+ CCK_RATE(2, 55), -+ CCK_RATE(3, 110), -+ OFDM_RATE(0, 60), -+ OFDM_RATE(1, 90), -+ OFDM_RATE(2, 120), -+ OFDM_RATE(3, 180), -+ OFDM_RATE(4, 240), -+ OFDM_RATE(5, 360), -+ OFDM_RATE(6, 480), -+ OFDM_RATE(7, 540), -+}; -+ -+static int -+mt76_init_sband(struct mt7601u_dev *dev, struct ieee80211_supported_band *sband, -+ const struct ieee80211_channel *chan, int n_chan, -+ struct ieee80211_rate *rates, int n_rates) -+{ -+ struct ieee80211_sta_ht_cap *ht_cap; -+ void *chanlist; -+ int size; -+ -+ size = n_chan * sizeof(*chan); -+ chanlist = devm_kmemdup(dev->dev, chan, size, GFP_KERNEL); -+ if (!chanlist) -+ return -ENOMEM; -+ -+ sband->channels = chanlist; -+ sband->n_channels = n_chan; -+ sband->bitrates = rates; -+ sband->n_bitrates = n_rates; -+ -+ ht_cap = &sband->ht_cap; -+ ht_cap->ht_supported = true; -+ ht_cap->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | -+ IEEE80211_HT_CAP_GRN_FLD | -+ IEEE80211_HT_CAP_SGI_20 | -+ IEEE80211_HT_CAP_SGI_40 | -+ (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); -+ -+ ht_cap->mcs.rx_mask[0] = 0xff; -+ ht_cap->mcs.rx_mask[4] = 0x1; -+ ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; -+ ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; -+ ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_2; -+ -+ dev->chandef.chan = &sband->channels[0]; -+ -+ return 0; -+} -+ -+static int -+mt76_init_sband_2g(struct mt7601u_dev *dev) -+{ -+ dev->sband_2g = devm_kzalloc(dev->dev, sizeof(*dev->sband_2g), -+ GFP_KERNEL); -+ dev->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = dev->sband_2g; -+ -+ WARN_ON(dev->ee->reg.start - 1 + dev->ee->reg.num > -+ ARRAY_SIZE(mt76_channels_2ghz)); -+ -+ return mt76_init_sband(dev, dev->sband_2g, -+ &mt76_channels_2ghz[dev->ee->reg.start - 1], -+ dev->ee->reg.num, -+ mt76_rates, ARRAY_SIZE(mt76_rates)); -+} -+ -+int mt7601u_register_device(struct mt7601u_dev *dev) -+{ -+ struct ieee80211_hw *hw = dev->hw; -+ struct wiphy *wiphy = hw->wiphy; -+ int ret; -+ -+ /* Reserve WCID 0 for mcast - thanks to this APs WCID will go to -+ * entry no. 1 like it does in the vendor driver. -+ */ -+ dev->wcid_mask[0] |= 1; -+ -+ /* init fake wcid for monitor interfaces */ -+ dev->mon_wcid = devm_kmalloc(dev->dev, sizeof(*dev->mon_wcid), -+ GFP_KERNEL); -+ if (!dev->mon_wcid) -+ return -ENOMEM; -+ dev->mon_wcid->idx = 0xff; -+ dev->mon_wcid->hw_key_idx = -1; -+ -+ SET_IEEE80211_DEV(hw, dev->dev); -+ -+ hw->queues = 4; -+ hw->flags = IEEE80211_HW_SIGNAL_DBM | -+ IEEE80211_HW_PS_NULLFUNC_STACK | -+ IEEE80211_HW_SUPPORTS_HT_CCK_RATES | -+ IEEE80211_HW_AMPDU_AGGREGATION | -+ IEEE80211_HW_SUPPORTS_RC_TABLE; -+ hw->max_rates = 1; -+ hw->max_report_rates = 7; -+ hw->max_rate_tries = 1; -+ -+ hw->sta_data_size = sizeof(struct mt76_sta); -+ hw->vif_data_size = sizeof(struct mt76_vif); -+ -+ SET_IEEE80211_PERM_ADDR(hw, dev->macaddr); -+ -+ wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR; -+ wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); -+ -+ ret = mt76_init_sband_2g(dev); -+ if (ret) -+ return ret; -+ -+ INIT_DELAYED_WORK(&dev->mac_work, mt7601u_mac_work); -+ INIT_DELAYED_WORK(&dev->stat_work, mt7601u_tx_stat); -+ -+ ret = ieee80211_register_hw(hw); -+ if (ret) -+ return ret; -+ -+ mt7601u_init_debugfs(dev); -+ -+ return 0; -+} -diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/initvals.h linux-rpi/drivers/net/wireless/mediatek/mt7601u/initvals.h ---- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/initvals.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/initvals.h 2015-11-29 09:42:38.887167260 +0100 -@@ -0,0 +1,164 @@ -+/* -+ * (c) Copyright 2002-2010, Ralink Technology, Inc. -+ * Copyright (C) 2015 Jakub Kicinski -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 -+ * as published by the Free Software Foundation -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#ifndef __MT7601U_INITVALS_H -+#define __MT7601U_INITVALS_H -+ -+static const struct mt76_reg_pair bbp_common_vals[] = { -+ { 65, 0x2c }, -+ { 66, 0x38 }, -+ { 68, 0x0b }, -+ { 69, 0x12 }, -+ { 70, 0x0a }, -+ { 73, 0x10 }, -+ { 81, 0x37 }, -+ { 82, 0x62 }, -+ { 83, 0x6a }, -+ { 84, 0x99 }, -+ { 86, 0x00 }, -+ { 91, 0x04 }, -+ { 92, 0x00 }, -+ { 103, 0x00 }, -+ { 105, 0x05 }, -+ { 106, 0x35 }, -+}; -+ -+static const struct mt76_reg_pair bbp_chip_vals[] = { -+ { 1, 0x04 }, { 4, 0x40 }, { 20, 0x06 }, { 31, 0x08 }, -+ /* CCK Tx Control */ -+ { 178, 0xff }, -+ /* AGC/Sync controls */ -+ { 66, 0x14 }, { 68, 0x8b }, { 69, 0x12 }, { 70, 0x09 }, -+ { 73, 0x11 }, { 75, 0x60 }, { 76, 0x44 }, { 84, 0x9a }, -+ { 86, 0x38 }, { 91, 0x07 }, { 92, 0x02 }, -+ /* Rx Path Controls */ -+ { 99, 0x50 }, { 101, 0x00 }, { 103, 0xc0 }, { 104, 0x92 }, -+ { 105, 0x3c }, { 106, 0x03 }, { 128, 0x12 }, -+ /* Change RXWI content: Gain Report */ -+ { 142, 0x04 }, { 143, 0x37 }, -+ /* Change RXWI content: Antenna Report */ -+ { 142, 0x03 }, { 143, 0x99 }, -+ /* Calibration Index Register */ -+ /* CCK Receiver Control */ -+ { 160, 0xeb }, { 161, 0xc4 }, { 162, 0x77 }, { 163, 0xf9 }, -+ { 164, 0x88 }, { 165, 0x80 }, { 166, 0xff }, { 167, 0xe4 }, -+ /* Added AGC controls - these AGC/GLRT registers are accessed -+ * through R195 and R196. -+ */ -+ { 195, 0x00 }, { 196, 0x00 }, -+ { 195, 0x01 }, { 196, 0x04 }, -+ { 195, 0x02 }, { 196, 0x20 }, -+ { 195, 0x03 }, { 196, 0x0a }, -+ { 195, 0x06 }, { 196, 0x16 }, -+ { 195, 0x07 }, { 196, 0x05 }, -+ { 195, 0x08 }, { 196, 0x37 }, -+ { 195, 0x0a }, { 196, 0x15 }, -+ { 195, 0x0b }, { 196, 0x17 }, -+ { 195, 0x0c }, { 196, 0x06 }, -+ { 195, 0x0d }, { 196, 0x09 }, -+ { 195, 0x0e }, { 196, 0x05 }, -+ { 195, 0x0f }, { 196, 0x09 }, -+ { 195, 0x10 }, { 196, 0x20 }, -+ { 195, 0x20 }, { 196, 0x17 }, -+ { 195, 0x21 }, { 196, 0x06 }, -+ { 195, 0x22 }, { 196, 0x09 }, -+ { 195, 0x23 }, { 196, 0x17 }, -+ { 195, 0x24 }, { 196, 0x06 }, -+ { 195, 0x25 }, { 196, 0x09 }, -+ { 195, 0x26 }, { 196, 0x17 }, -+ { 195, 0x27 }, { 196, 0x06 }, -+ { 195, 0x28 }, { 196, 0x09 }, -+ { 195, 0x29 }, { 196, 0x05 }, -+ { 195, 0x2a }, { 196, 0x09 }, -+ { 195, 0x80 }, { 196, 0x8b }, -+ { 195, 0x81 }, { 196, 0x12 }, -+ { 195, 0x82 }, { 196, 0x09 }, -+ { 195, 0x83 }, { 196, 0x17 }, -+ { 195, 0x84 }, { 196, 0x11 }, -+ { 195, 0x85 }, { 196, 0x00 }, -+ { 195, 0x86 }, { 196, 0x00 }, -+ { 195, 0x87 }, { 196, 0x18 }, -+ { 195, 0x88 }, { 196, 0x60 }, -+ { 195, 0x89 }, { 196, 0x44 }, -+ { 195, 0x8a }, { 196, 0x8b }, -+ { 195, 0x8b }, { 196, 0x8b }, -+ { 195, 0x8c }, { 196, 0x8b }, -+ { 195, 0x8d }, { 196, 0x8b }, -+ { 195, 0x8e }, { 196, 0x09 }, -+ { 195, 0x8f }, { 196, 0x09 }, -+ { 195, 0x90 }, { 196, 0x09 }, -+ { 195, 0x91 }, { 196, 0x09 }, -+ { 195, 0x92 }, { 196, 0x11 }, -+ { 195, 0x93 }, { 196, 0x11 }, -+ { 195, 0x94 }, { 196, 0x11 }, -+ { 195, 0x95 }, { 196, 0x11 }, -+ /* PPAD */ -+ { 47, 0x80 }, { 60, 0x80 }, { 150, 0xd2 }, { 151, 0x32 }, -+ { 152, 0x23 }, { 153, 0x41 }, { 154, 0x00 }, { 155, 0x4f }, -+ { 253, 0x7e }, { 195, 0x30 }, { 196, 0x32 }, { 195, 0x31 }, -+ { 196, 0x23 }, { 195, 0x32 }, { 196, 0x45 }, { 195, 0x35 }, -+ { 196, 0x4a }, { 195, 0x36 }, { 196, 0x5a }, { 195, 0x37 }, -+ { 196, 0x5a }, -+}; -+ -+static const struct mt76_reg_pair mac_common_vals[] = { -+ { MT_LEGACY_BASIC_RATE, 0x0000013f }, -+ { MT_HT_BASIC_RATE, 0x00008003 }, -+ { MT_MAC_SYS_CTRL, 0x00000000 }, -+ { MT_RX_FILTR_CFG, 0x00017f97 }, -+ { MT_BKOFF_SLOT_CFG, 0x00000209 }, -+ { MT_TX_SW_CFG0, 0x00000000 }, -+ { MT_TX_SW_CFG1, 0x00080606 }, -+ { MT_TX_LINK_CFG, 0x00001020 }, -+ { MT_TX_TIMEOUT_CFG, 0x000a2090 }, -+ { MT_MAX_LEN_CFG, 0x00003fff }, -+ { MT_PBF_TX_MAX_PCNT, 0x1fbf1f1f }, -+ { MT_PBF_RX_MAX_PCNT, 0x0000009f }, -+ { MT_TX_RETRY_CFG, 0x47d01f0f }, -+ { MT_AUTO_RSP_CFG, 0x00000013 }, -+ { MT_CCK_PROT_CFG, 0x05740003 }, -+ { MT_OFDM_PROT_CFG, 0x05740003 }, -+ { MT_MM40_PROT_CFG, 0x03f44084 }, -+ { MT_GF20_PROT_CFG, 0x01744004 }, -+ { MT_GF40_PROT_CFG, 0x03f44084 }, -+ { MT_MM20_PROT_CFG, 0x01744004 }, -+ { MT_TXOP_CTRL_CFG, 0x0000583f }, -+ { MT_TX_RTS_CFG, 0x01092b20 }, -+ { MT_EXP_ACK_TIME, 0x002400ca }, -+ { MT_TXOP_HLDR_ET, 0x00000002 }, -+ { MT_XIFS_TIME_CFG, 0x33a41010 }, -+ { MT_PWR_PIN_CFG, 0x00000000 }, -+}; -+ -+static const struct mt76_reg_pair mac_chip_vals[] = { -+ { MT_TSO_CTRL, 0x00006050 }, -+ { MT_BCN_OFFSET(0), 0x18100800 }, -+ { MT_BCN_OFFSET(1), 0x38302820 }, -+ { MT_PBF_SYS_CTRL, 0x00080c00 }, -+ { MT_PBF_CFG, 0x7f723c1f }, -+ { MT_FCE_PSE_CTRL, 0x00000001 }, -+ { MT_PAUSE_ENABLE_CONTROL1, 0x00000000 }, -+ { MT_TX0_RF_GAIN_CORR, 0x003b0005 }, -+ { MT_TX0_RF_GAIN_ATTEN, 0x00006900 }, -+ { MT_TX0_BB_GAIN_ATTEN, 0x00000400 }, -+ { MT_TX_ALC_VGA3, 0x00060006 }, -+ { MT_TX_SW_CFG0, 0x00000402 }, -+ { MT_TX_SW_CFG1, 0x00000000 }, -+ { MT_TX_SW_CFG2, 0x00000000 }, -+ { MT_HEADER_TRANS_CTRL_REG, 0x00000000 }, -+ { MT_FCE_CSO, 0x0000030f }, -+ { MT_FCE_PARAMETERS, 0x00256f0f }, -+}; -+ -+#endif -diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/initvals_phy.h linux-rpi/drivers/net/wireless/mediatek/mt7601u/initvals_phy.h ---- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/initvals_phy.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/initvals_phy.h 2015-11-29 09:42:38.887167260 +0100 -@@ -0,0 +1,291 @@ -+/* -+ * (c) Copyright 2002-2010, Ralink Technology, Inc. -+ * Copyright (C) 2015 Jakub Kicinski -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 -+ * as published by the Free Software Foundation -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#ifndef __MT7601U_PHY_INITVALS_H -+#define __MT7601U_PHY_INITVALS_H -+ -+#define RF_REG_PAIR(bank, reg, value) \ -+ { MT_MCU_MEMMAP_RF | (bank) << 16 | (reg), value } -+ -+static const struct mt76_reg_pair rf_central[] = { -+ /* Bank 0 - for central blocks: BG, PLL, XTAL, LO, ADC/DAC */ -+ RF_REG_PAIR(0, 0, 0x02), -+ RF_REG_PAIR(0, 1, 0x01), -+ RF_REG_PAIR(0, 2, 0x11), -+ RF_REG_PAIR(0, 3, 0xff), -+ RF_REG_PAIR(0, 4, 0x0a), -+ RF_REG_PAIR(0, 5, 0x20), -+ RF_REG_PAIR(0, 6, 0x00), -+ /* B/G */ -+ RF_REG_PAIR(0, 7, 0x00), -+ RF_REG_PAIR(0, 8, 0x00), -+ RF_REG_PAIR(0, 9, 0x00), -+ RF_REG_PAIR(0, 10, 0x00), -+ RF_REG_PAIR(0, 11, 0x21), -+ /* XO */ -+ RF_REG_PAIR(0, 13, 0x00), /* 40mhz xtal */ -+ /* RF_REG_PAIR(0, 13, 0x13), */ /* 20mhz xtal */ -+ RF_REG_PAIR(0, 14, 0x7c), -+ RF_REG_PAIR(0, 15, 0x22), -+ RF_REG_PAIR(0, 16, 0x80), -+ /* PLL */ -+ RF_REG_PAIR(0, 17, 0x99), -+ RF_REG_PAIR(0, 18, 0x99), -+ RF_REG_PAIR(0, 19, 0x09), -+ RF_REG_PAIR(0, 20, 0x50), -+ RF_REG_PAIR(0, 21, 0xb0), -+ RF_REG_PAIR(0, 22, 0x00), -+ RF_REG_PAIR(0, 23, 0xc5), -+ RF_REG_PAIR(0, 24, 0xfc), -+ RF_REG_PAIR(0, 25, 0x40), -+ RF_REG_PAIR(0, 26, 0x4d), -+ RF_REG_PAIR(0, 27, 0x02), -+ RF_REG_PAIR(0, 28, 0x72), -+ RF_REG_PAIR(0, 29, 0x01), -+ RF_REG_PAIR(0, 30, 0x00), -+ RF_REG_PAIR(0, 31, 0x00), -+ /* test ports */ -+ RF_REG_PAIR(0, 32, 0x00), -+ RF_REG_PAIR(0, 33, 0x00), -+ RF_REG_PAIR(0, 34, 0x23), -+ RF_REG_PAIR(0, 35, 0x01), /* change setting to reduce spurs */ -+ RF_REG_PAIR(0, 36, 0x00), -+ RF_REG_PAIR(0, 37, 0x00), -+ /* ADC/DAC */ -+ RF_REG_PAIR(0, 38, 0x00), -+ RF_REG_PAIR(0, 39, 0x20), -+ RF_REG_PAIR(0, 40, 0x00), -+ RF_REG_PAIR(0, 41, 0xd0), -+ RF_REG_PAIR(0, 42, 0x1b), -+ RF_REG_PAIR(0, 43, 0x02), -+ RF_REG_PAIR(0, 44, 0x00), -+}; -+ -+static const struct mt76_reg_pair rf_channel[] = { -+ RF_REG_PAIR(4, 0, 0x01), -+ RF_REG_PAIR(4, 1, 0x00), -+ RF_REG_PAIR(4, 2, 0x00), -+ RF_REG_PAIR(4, 3, 0x00), -+ /* LDO */ -+ RF_REG_PAIR(4, 4, 0x00), -+ RF_REG_PAIR(4, 5, 0x08), -+ RF_REG_PAIR(4, 6, 0x00), -+ /* RX */ -+ RF_REG_PAIR(4, 7, 0x5b), -+ RF_REG_PAIR(4, 8, 0x52), -+ RF_REG_PAIR(4, 9, 0xb6), -+ RF_REG_PAIR(4, 10, 0x57), -+ RF_REG_PAIR(4, 11, 0x33), -+ RF_REG_PAIR(4, 12, 0x22), -+ RF_REG_PAIR(4, 13, 0x3d), -+ RF_REG_PAIR(4, 14, 0x3e), -+ RF_REG_PAIR(4, 15, 0x13), -+ RF_REG_PAIR(4, 16, 0x22), -+ RF_REG_PAIR(4, 17, 0x23), -+ RF_REG_PAIR(4, 18, 0x02), -+ RF_REG_PAIR(4, 19, 0xa4), -+ RF_REG_PAIR(4, 20, 0x01), -+ RF_REG_PAIR(4, 21, 0x12), -+ RF_REG_PAIR(4, 22, 0x80), -+ RF_REG_PAIR(4, 23, 0xb3), -+ RF_REG_PAIR(4, 24, 0x00), /* reserved */ -+ RF_REG_PAIR(4, 25, 0x00), /* reserved */ -+ RF_REG_PAIR(4, 26, 0x00), /* reserved */ -+ RF_REG_PAIR(4, 27, 0x00), /* reserved */ -+ /* LOGEN */ -+ RF_REG_PAIR(4, 28, 0x18), -+ RF_REG_PAIR(4, 29, 0xee), -+ RF_REG_PAIR(4, 30, 0x6b), -+ RF_REG_PAIR(4, 31, 0x31), -+ RF_REG_PAIR(4, 32, 0x5d), -+ RF_REG_PAIR(4, 33, 0x00), /* reserved */ -+ /* TX */ -+ RF_REG_PAIR(4, 34, 0x96), -+ RF_REG_PAIR(4, 35, 0x55), -+ RF_REG_PAIR(4, 36, 0x08), -+ RF_REG_PAIR(4, 37, 0xbb), -+ RF_REG_PAIR(4, 38, 0xb3), -+ RF_REG_PAIR(4, 39, 0xb3), -+ RF_REG_PAIR(4, 40, 0x03), -+ RF_REG_PAIR(4, 41, 0x00), /* reserved */ -+ RF_REG_PAIR(4, 42, 0x00), /* reserved */ -+ RF_REG_PAIR(4, 43, 0xc5), -+ RF_REG_PAIR(4, 44, 0xc5), -+ RF_REG_PAIR(4, 45, 0xc5), -+ RF_REG_PAIR(4, 46, 0x07), -+ RF_REG_PAIR(4, 47, 0xa8), -+ RF_REG_PAIR(4, 48, 0xef), -+ RF_REG_PAIR(4, 49, 0x1a), -+ /* PA */ -+ RF_REG_PAIR(4, 54, 0x07), -+ RF_REG_PAIR(4, 55, 0xa7), -+ RF_REG_PAIR(4, 56, 0xcc), -+ RF_REG_PAIR(4, 57, 0x14), -+ RF_REG_PAIR(4, 58, 0x07), -+ RF_REG_PAIR(4, 59, 0xa8), -+ RF_REG_PAIR(4, 60, 0xd7), -+ RF_REG_PAIR(4, 61, 0x10), -+ RF_REG_PAIR(4, 62, 0x1c), -+ RF_REG_PAIR(4, 63, 0x00), /* reserved */ -+}; -+ -+static const struct mt76_reg_pair rf_vga[] = { -+ RF_REG_PAIR(5, 0, 0x47), -+ RF_REG_PAIR(5, 1, 0x00), -+ RF_REG_PAIR(5, 2, 0x00), -+ RF_REG_PAIR(5, 3, 0x08), -+ RF_REG_PAIR(5, 4, 0x04), -+ RF_REG_PAIR(5, 5, 0x20), -+ RF_REG_PAIR(5, 6, 0x3a), -+ RF_REG_PAIR(5, 7, 0x3a), -+ RF_REG_PAIR(5, 8, 0x00), -+ RF_REG_PAIR(5, 9, 0x00), -+ RF_REG_PAIR(5, 10, 0x10), -+ RF_REG_PAIR(5, 11, 0x10), -+ RF_REG_PAIR(5, 12, 0x10), -+ RF_REG_PAIR(5, 13, 0x10), -+ RF_REG_PAIR(5, 14, 0x10), -+ RF_REG_PAIR(5, 15, 0x20), -+ RF_REG_PAIR(5, 16, 0x22), -+ RF_REG_PAIR(5, 17, 0x7c), -+ RF_REG_PAIR(5, 18, 0x00), -+ RF_REG_PAIR(5, 19, 0x00), -+ RF_REG_PAIR(5, 20, 0x00), -+ RF_REG_PAIR(5, 21, 0xf1), -+ RF_REG_PAIR(5, 22, 0x11), -+ RF_REG_PAIR(5, 23, 0x02), -+ RF_REG_PAIR(5, 24, 0x41), -+ RF_REG_PAIR(5, 25, 0x20), -+ RF_REG_PAIR(5, 26, 0x00), -+ RF_REG_PAIR(5, 27, 0xd7), -+ RF_REG_PAIR(5, 28, 0xa2), -+ RF_REG_PAIR(5, 29, 0x20), -+ RF_REG_PAIR(5, 30, 0x49), -+ RF_REG_PAIR(5, 31, 0x20), -+ RF_REG_PAIR(5, 32, 0x04), -+ RF_REG_PAIR(5, 33, 0xf1), -+ RF_REG_PAIR(5, 34, 0xa1), -+ RF_REG_PAIR(5, 35, 0x01), -+ RF_REG_PAIR(5, 41, 0x00), -+ RF_REG_PAIR(5, 42, 0x00), -+ RF_REG_PAIR(5, 43, 0x00), -+ RF_REG_PAIR(5, 44, 0x00), -+ RF_REG_PAIR(5, 45, 0x00), -+ RF_REG_PAIR(5, 46, 0x00), -+ RF_REG_PAIR(5, 47, 0x00), -+ RF_REG_PAIR(5, 48, 0x00), -+ RF_REG_PAIR(5, 49, 0x00), -+ RF_REG_PAIR(5, 50, 0x00), -+ RF_REG_PAIR(5, 51, 0x00), -+ RF_REG_PAIR(5, 52, 0x00), -+ RF_REG_PAIR(5, 53, 0x00), -+ RF_REG_PAIR(5, 54, 0x00), -+ RF_REG_PAIR(5, 55, 0x00), -+ RF_REG_PAIR(5, 56, 0x00), -+ RF_REG_PAIR(5, 57, 0x00), -+ RF_REG_PAIR(5, 58, 0x31), -+ RF_REG_PAIR(5, 59, 0x31), -+ RF_REG_PAIR(5, 60, 0x0a), -+ RF_REG_PAIR(5, 61, 0x02), -+ RF_REG_PAIR(5, 62, 0x00), -+ RF_REG_PAIR(5, 63, 0x00), -+}; -+ -+/* TODO: BBP178 is set to 0xff for "CCK CH14 OBW" which overrides the settings -+ * from channel switching. Seems stupid at best. -+ */ -+static const struct mt76_reg_pair bbp_high_temp[] = { -+ { 75, 0x60 }, -+ { 92, 0x02 }, -+ { 178, 0xff }, /* For CCK CH14 OBW */ -+ { 195, 0x88 }, { 196, 0x60 }, -+}, bbp_high_temp_bw20[] = { -+ { 69, 0x12 }, -+ { 91, 0x07 }, -+ { 195, 0x23 }, { 196, 0x17 }, -+ { 195, 0x24 }, { 196, 0x06 }, -+ { 195, 0x81 }, { 196, 0x12 }, -+ { 195, 0x83 }, { 196, 0x17 }, -+}, bbp_high_temp_bw40[] = { -+ { 69, 0x15 }, -+ { 91, 0x04 }, -+ { 195, 0x23 }, { 196, 0x12 }, -+ { 195, 0x24 }, { 196, 0x08 }, -+ { 195, 0x81 }, { 196, 0x15 }, -+ { 195, 0x83 }, { 196, 0x16 }, -+}, bbp_low_temp[] = { -+ { 178, 0xff }, /* For CCK CH14 OBW */ -+}, bbp_low_temp_bw20[] = { -+ { 69, 0x12 }, -+ { 75, 0x5e }, -+ { 91, 0x07 }, -+ { 92, 0x02 }, -+ { 195, 0x23 }, { 196, 0x17 }, -+ { 195, 0x24 }, { 196, 0x06 }, -+ { 195, 0x81 }, { 196, 0x12 }, -+ { 195, 0x83 }, { 196, 0x17 }, -+ { 195, 0x88 }, { 196, 0x5e }, -+}, bbp_low_temp_bw40[] = { -+ { 69, 0x15 }, -+ { 75, 0x5c }, -+ { 91, 0x04 }, -+ { 92, 0x03 }, -+ { 195, 0x23 }, { 196, 0x10 }, -+ { 195, 0x24 }, { 196, 0x08 }, -+ { 195, 0x81 }, { 196, 0x15 }, -+ { 195, 0x83 }, { 196, 0x16 }, -+ { 195, 0x88 }, { 196, 0x5b }, -+}, bbp_normal_temp[] = { -+ { 75, 0x60 }, -+ { 92, 0x02 }, -+ { 178, 0xff }, /* For CCK CH14 OBW */ -+ { 195, 0x88 }, { 196, 0x60 }, -+}, bbp_normal_temp_bw20[] = { -+ { 69, 0x12 }, -+ { 91, 0x07 }, -+ { 195, 0x23 }, { 196, 0x17 }, -+ { 195, 0x24 }, { 196, 0x06 }, -+ { 195, 0x81 }, { 196, 0x12 }, -+ { 195, 0x83 }, { 196, 0x17 }, -+}, bbp_normal_temp_bw40[] = { -+ { 69, 0x15 }, -+ { 91, 0x04 }, -+ { 195, 0x23 }, { 196, 0x12 }, -+ { 195, 0x24 }, { 196, 0x08 }, -+ { 195, 0x81 }, { 196, 0x15 }, -+ { 195, 0x83 }, { 196, 0x16 }, -+}; -+ -+#define BBP_TABLE(arr) { arr, ARRAY_SIZE(arr), } -+ -+static const struct reg_table { -+ const struct mt76_reg_pair *regs; -+ size_t n; -+} bbp_mode_table[3][3] = { -+ { -+ BBP_TABLE(bbp_normal_temp_bw20), -+ BBP_TABLE(bbp_normal_temp_bw40), -+ BBP_TABLE(bbp_normal_temp), -+ }, { -+ BBP_TABLE(bbp_high_temp_bw20), -+ BBP_TABLE(bbp_high_temp_bw40), -+ BBP_TABLE(bbp_high_temp), -+ }, { -+ BBP_TABLE(bbp_low_temp_bw20), -+ BBP_TABLE(bbp_low_temp_bw40), -+ BBP_TABLE(bbp_low_temp), -+ } -+}; -+ -+#endif -diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/Kconfig linux-rpi/drivers/net/wireless/mediatek/mt7601u/Kconfig ---- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/Kconfig 2015-11-29 09:42:38.887167260 +0100 -@@ -0,0 +1,6 @@ -+config MT7601U -+ tristate "MediaTek MT7601U (USB) support" -+ depends on MAC80211 -+ depends on USB -+ ---help--- -+ This adds support for MT7601U-based wireless USB dongles. -diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/mac.c linux-rpi/drivers/net/wireless/mediatek/mt7601u/mac.c ---- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/mac.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/mac.c 2015-11-29 09:42:38.887167260 +0100 -@@ -0,0 +1,577 @@ -+/* -+ * Copyright (C) 2014 Felix Fietkau -+ * Copyright (C) 2015 Jakub Kicinski -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 -+ * as published by the Free Software Foundation -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include "mt7601u.h" -+#include "trace.h" -+#include -+ -+static void -+mt76_mac_process_tx_rate(struct ieee80211_tx_rate *txrate, u16 rate) -+{ -+ u8 idx = MT76_GET(MT_TXWI_RATE_MCS, rate); -+ -+ txrate->idx = 0; -+ txrate->flags = 0; -+ txrate->count = 1; -+ -+ switch (MT76_GET(MT_TXWI_RATE_PHY_MODE, rate)) { -+ case MT_PHY_TYPE_OFDM: -+ txrate->idx = idx + 4; -+ return; -+ case MT_PHY_TYPE_CCK: -+ if (idx >= 8) -+ idx -= 8; -+ -+ txrate->idx = idx; -+ return; -+ case MT_PHY_TYPE_HT_GF: -+ txrate->flags |= IEEE80211_TX_RC_GREEN_FIELD; -+ /* fall through */ -+ case MT_PHY_TYPE_HT: -+ txrate->flags |= IEEE80211_TX_RC_MCS; -+ txrate->idx = idx; -+ break; -+ default: -+ WARN_ON(1); -+ return; -+ } -+ -+ if (MT76_GET(MT_TXWI_RATE_BW, rate) == MT_PHY_BW_40) -+ txrate->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH; -+ -+ if (rate & MT_TXWI_RATE_SGI) -+ txrate->flags |= IEEE80211_TX_RC_SHORT_GI; -+} -+ -+static void -+mt76_mac_fill_tx_status(struct mt7601u_dev *dev, struct ieee80211_tx_info *info, -+ struct mt76_tx_status *st) -+{ -+ struct ieee80211_tx_rate *rate = info->status.rates; -+ int cur_idx, last_rate; -+ int i; -+ -+ last_rate = min_t(int, st->retry, IEEE80211_TX_MAX_RATES - 1); -+ mt76_mac_process_tx_rate(&rate[last_rate], st->rate); -+ if (last_rate < IEEE80211_TX_MAX_RATES - 1) -+ rate[last_rate + 1].idx = -1; -+ -+ cur_idx = rate[last_rate].idx + st->retry; -+ for (i = 0; i <= last_rate; i++) { -+ rate[i].flags = rate[last_rate].flags; -+ rate[i].idx = max_t(int, 0, cur_idx - i); -+ rate[i].count = 1; -+ } -+ -+ if (last_rate > 0) -+ rate[last_rate - 1].count = st->retry + 1 - last_rate; -+ -+ info->status.ampdu_len = 1; -+ info->status.ampdu_ack_len = st->success; -+ -+ if (st->is_probe) -+ info->flags |= IEEE80211_TX_CTL_RATE_CTRL_PROBE; -+ -+ if (st->aggr) -+ info->flags |= IEEE80211_TX_CTL_AMPDU | -+ IEEE80211_TX_STAT_AMPDU; -+ -+ if (!st->ack_req) -+ info->flags |= IEEE80211_TX_CTL_NO_ACK; -+ else if (st->success) -+ info->flags |= IEEE80211_TX_STAT_ACK; -+} -+ -+u16 mt76_mac_tx_rate_val(struct mt7601u_dev *dev, -+ const struct ieee80211_tx_rate *rate, u8 *nss_val) -+{ -+ u16 rateval; -+ u8 phy, rate_idx; -+ u8 nss = 1; -+ u8 bw = 0; -+ -+ if (rate->flags & IEEE80211_TX_RC_MCS) { -+ rate_idx = rate->idx; -+ nss = 1 + (rate->idx >> 3); -+ phy = MT_PHY_TYPE_HT; -+ if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD) -+ phy = MT_PHY_TYPE_HT_GF; -+ if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) -+ bw = 1; -+ } else { -+ const struct ieee80211_rate *r; -+ int band = dev->chandef.chan->band; -+ u16 val; -+ -+ r = &dev->hw->wiphy->bands[band]->bitrates[rate->idx]; -+ if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) -+ val = r->hw_value_short; -+ else -+ val = r->hw_value; -+ -+ phy = val >> 8; -+ rate_idx = val & 0xff; -+ bw = 0; -+ } -+ -+ rateval = MT76_SET(MT_RXWI_RATE_MCS, rate_idx); -+ rateval |= MT76_SET(MT_RXWI_RATE_PHY, phy); -+ rateval |= MT76_SET(MT_RXWI_RATE_BW, bw); -+ if (rate->flags & IEEE80211_TX_RC_SHORT_GI) -+ rateval |= MT_RXWI_RATE_SGI; -+ -+ *nss_val = nss; -+ return rateval; -+} -+ -+void mt76_mac_wcid_set_rate(struct mt7601u_dev *dev, struct mt76_wcid *wcid, -+ const struct ieee80211_tx_rate *rate) -+{ -+ unsigned long flags; -+ -+ spin_lock_irqsave(&dev->lock, flags); -+ wcid->tx_rate = mt76_mac_tx_rate_val(dev, rate, &wcid->tx_rate_nss); -+ wcid->tx_rate_set = true; -+ spin_unlock_irqrestore(&dev->lock, flags); -+} -+ -+struct mt76_tx_status mt7601u_mac_fetch_tx_status(struct mt7601u_dev *dev) -+{ -+ struct mt76_tx_status stat = {}; -+ u32 val; -+ -+ val = mt7601u_rr(dev, MT_TX_STAT_FIFO); -+ stat.valid = !!(val & MT_TX_STAT_FIFO_VALID); -+ stat.success = !!(val & MT_TX_STAT_FIFO_SUCCESS); -+ stat.aggr = !!(val & MT_TX_STAT_FIFO_AGGR); -+ stat.ack_req = !!(val & MT_TX_STAT_FIFO_ACKREQ); -+ stat.pktid = MT76_GET(MT_TX_STAT_FIFO_PID_TYPE, val); -+ stat.wcid = MT76_GET(MT_TX_STAT_FIFO_WCID, val); -+ stat.rate = MT76_GET(MT_TX_STAT_FIFO_RATE, val); -+ -+ return stat; -+} -+ -+void mt76_send_tx_status(struct mt7601u_dev *dev, struct mt76_tx_status *stat) -+{ -+ struct ieee80211_tx_info info = {}; -+ struct ieee80211_sta *sta = NULL; -+ struct mt76_wcid *wcid = NULL; -+ void *msta; -+ -+ rcu_read_lock(); -+ if (stat->wcid < ARRAY_SIZE(dev->wcid)) -+ wcid = rcu_dereference(dev->wcid[stat->wcid]); -+ -+ if (wcid) { -+ msta = container_of(wcid, struct mt76_sta, wcid); -+ sta = container_of(msta, struct ieee80211_sta, -+ drv_priv); -+ } -+ -+ mt76_mac_fill_tx_status(dev, &info, stat); -+ -+ spin_lock_bh(&dev->mac_lock); -+ ieee80211_tx_status_noskb(dev->hw, sta, &info); -+ spin_unlock_bh(&dev->mac_lock); -+ -+ rcu_read_unlock(); -+} -+ -+void mt7601u_mac_set_protection(struct mt7601u_dev *dev, bool legacy_prot, -+ int ht_mode) -+{ -+ int mode = ht_mode & IEEE80211_HT_OP_MODE_PROTECTION; -+ bool non_gf = !!(ht_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT); -+ u32 prot[6]; -+ bool ht_rts[4] = {}; -+ int i; -+ -+ prot[0] = MT_PROT_NAV_SHORT | -+ MT_PROT_TXOP_ALLOW_ALL | -+ MT_PROT_RTS_THR_EN; -+ prot[1] = prot[0]; -+ if (legacy_prot) -+ prot[1] |= MT_PROT_CTRL_CTS2SELF; -+ -+ prot[2] = prot[4] = MT_PROT_NAV_SHORT | MT_PROT_TXOP_ALLOW_BW20; -+ prot[3] = prot[5] = MT_PROT_NAV_SHORT | MT_PROT_TXOP_ALLOW_ALL; -+ -+ if (legacy_prot) { -+ prot[2] |= MT_PROT_RATE_CCK_11; -+ prot[3] |= MT_PROT_RATE_CCK_11; -+ prot[4] |= MT_PROT_RATE_CCK_11; -+ prot[5] |= MT_PROT_RATE_CCK_11; -+ } else { -+ prot[2] |= MT_PROT_RATE_OFDM_24; -+ prot[3] |= MT_PROT_RATE_DUP_OFDM_24; -+ prot[4] |= MT_PROT_RATE_OFDM_24; -+ prot[5] |= MT_PROT_RATE_DUP_OFDM_24; -+ } -+ -+ switch (mode) { -+ case IEEE80211_HT_OP_MODE_PROTECTION_NONE: -+ break; -+ -+ case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER: -+ ht_rts[0] = ht_rts[1] = ht_rts[2] = ht_rts[3] = true; -+ break; -+ -+ case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ: -+ ht_rts[1] = ht_rts[3] = true; -+ break; -+ -+ case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED: -+ ht_rts[0] = ht_rts[1] = ht_rts[2] = ht_rts[3] = true; -+ break; -+ } -+ -+ if (non_gf) -+ ht_rts[2] = ht_rts[3] = true; -+ -+ for (i = 0; i < 4; i++) -+ if (ht_rts[i]) -+ prot[i + 2] |= MT_PROT_CTRL_RTS_CTS; -+ -+ for (i = 0; i < 6; i++) -+ mt7601u_wr(dev, MT_CCK_PROT_CFG + i * 4, prot[i]); -+} -+ -+void mt7601u_mac_set_short_preamble(struct mt7601u_dev *dev, bool short_preamb) -+{ -+ if (short_preamb) -+ mt76_set(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_PREAMB_SHORT); -+ else -+ mt76_clear(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_PREAMB_SHORT); -+} -+ -+void mt7601u_mac_config_tsf(struct mt7601u_dev *dev, bool enable, int interval) -+{ -+ u32 val = mt7601u_rr(dev, MT_BEACON_TIME_CFG); -+ -+ val &= ~(MT_BEACON_TIME_CFG_TIMER_EN | -+ MT_BEACON_TIME_CFG_SYNC_MODE | -+ MT_BEACON_TIME_CFG_TBTT_EN); -+ -+ if (!enable) { -+ mt7601u_wr(dev, MT_BEACON_TIME_CFG, val); -+ return; -+ } -+ -+ val &= ~MT_BEACON_TIME_CFG_INTVAL; -+ val |= MT76_SET(MT_BEACON_TIME_CFG_INTVAL, interval << 4) | -+ MT_BEACON_TIME_CFG_TIMER_EN | -+ MT_BEACON_TIME_CFG_SYNC_MODE | -+ MT_BEACON_TIME_CFG_TBTT_EN; -+} -+ -+static void mt7601u_check_mac_err(struct mt7601u_dev *dev) -+{ -+ u32 val = mt7601u_rr(dev, 0x10f4); -+ -+ if (!(val & BIT(29)) || !(val & (BIT(7) | BIT(5)))) -+ return; -+ -+ dev_err(dev->dev, "Error: MAC specific condition occurred\n"); -+ -+ mt76_set(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_RESET_CSR); -+ udelay(10); -+ mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_RESET_CSR); -+} -+ -+void mt7601u_mac_work(struct work_struct *work) -+{ -+ struct mt7601u_dev *dev = container_of(work, struct mt7601u_dev, -+ mac_work.work); -+ struct { -+ u32 addr_base; -+ u32 span; -+ u64 *stat_base; -+ } spans[] = { -+ { MT_RX_STA_CNT0, 3, dev->stats.rx_stat }, -+ { MT_TX_STA_CNT0, 3, dev->stats.tx_stat }, -+ { MT_TX_AGG_STAT, 1, dev->stats.aggr_stat }, -+ { MT_MPDU_DENSITY_CNT, 1, dev->stats.zero_len_del }, -+ { MT_TX_AGG_CNT_BASE0, 8, &dev->stats.aggr_n[0] }, -+ { MT_TX_AGG_CNT_BASE1, 8, &dev->stats.aggr_n[16] }, -+ }; -+ u32 sum, n; -+ int i, j, k; -+ -+ /* Note: using MCU_RANDOM_READ is actually slower then reading all the -+ * registers by hand. MCU takes ca. 20ms to complete read of 24 -+ * registers while reading them one by one will takes roughly -+ * 24*200us =~ 5ms. -+ */ -+ -+ k = 0; -+ n = 0; -+ sum = 0; -+ for (i = 0; i < ARRAY_SIZE(spans); i++) -+ for (j = 0; j < spans[i].span; j++) { -+ u32 val = mt7601u_rr(dev, spans[i].addr_base + j * 4); -+ -+ spans[i].stat_base[j * 2] += val & 0xffff; -+ spans[i].stat_base[j * 2 + 1] += val >> 16; -+ -+ /* Calculate average AMPDU length */ -+ if (spans[i].addr_base != MT_TX_AGG_CNT_BASE0 && -+ spans[i].addr_base != MT_TX_AGG_CNT_BASE1) -+ continue; -+ -+ n += (val >> 16) + (val & 0xffff); -+ sum += (val & 0xffff) * (1 + k * 2) + -+ (val >> 16) * (2 + k * 2); -+ k++; -+ } -+ -+ atomic_set(&dev->avg_ampdu_len, n ? DIV_ROUND_CLOSEST(sum, n) : 1); -+ -+ mt7601u_check_mac_err(dev); -+ -+ ieee80211_queue_delayed_work(dev->hw, &dev->mac_work, 10 * HZ); -+} -+ -+void -+mt7601u_mac_wcid_setup(struct mt7601u_dev *dev, u8 idx, u8 vif_idx, u8 *mac) -+{ -+ u8 zmac[ETH_ALEN] = {}; -+ u32 attr; -+ -+ attr = MT76_SET(MT_WCID_ATTR_BSS_IDX, vif_idx & 7) | -+ MT76_SET(MT_WCID_ATTR_BSS_IDX_EXT, !!(vif_idx & 8)); -+ -+ mt76_wr(dev, MT_WCID_ATTR(idx), attr); -+ -+ if (mac) -+ memcpy(zmac, mac, sizeof(zmac)); -+ -+ mt7601u_addr_wr(dev, MT_WCID_ADDR(idx), zmac); -+} -+ -+void mt7601u_mac_set_ampdu_factor(struct mt7601u_dev *dev) -+{ -+ struct ieee80211_sta *sta; -+ struct mt76_wcid *wcid; -+ void *msta; -+ u8 min_factor = 3; -+ int i; -+ -+ rcu_read_lock(); -+ for (i = 0; i < ARRAY_SIZE(dev->wcid); i++) { -+ wcid = rcu_dereference(dev->wcid[i]); -+ if (!wcid) -+ continue; -+ -+ msta = container_of(wcid, struct mt76_sta, wcid); -+ sta = container_of(msta, struct ieee80211_sta, drv_priv); -+ -+ min_factor = min(min_factor, sta->ht_cap.ampdu_factor); -+ } -+ rcu_read_unlock(); -+ -+ mt7601u_wr(dev, MT_MAX_LEN_CFG, 0xa0fff | -+ MT76_SET(MT_MAX_LEN_CFG_AMPDU, min_factor)); -+} -+ -+static void -+mt76_mac_process_rate(struct ieee80211_rx_status *status, u16 rate) -+{ -+ u8 idx = MT76_GET(MT_RXWI_RATE_MCS, rate); -+ -+ switch (MT76_GET(MT_RXWI_RATE_PHY, rate)) { -+ case MT_PHY_TYPE_OFDM: -+ if (WARN_ON(idx >= 8)) -+ idx = 0; -+ idx += 4; -+ -+ status->rate_idx = idx; -+ return; -+ case MT_PHY_TYPE_CCK: -+ if (idx >= 8) { -+ idx -= 8; -+ status->flag |= RX_FLAG_SHORTPRE; -+ } -+ -+ if (WARN_ON(idx >= 4)) -+ idx = 0; -+ -+ status->rate_idx = idx; -+ return; -+ case MT_PHY_TYPE_HT_GF: -+ status->flag |= RX_FLAG_HT_GF; -+ /* fall through */ -+ case MT_PHY_TYPE_HT: -+ status->flag |= RX_FLAG_HT; -+ status->rate_idx = idx; -+ break; -+ default: -+ WARN_ON(1); -+ return; -+ } -+ -+ if (rate & MT_RXWI_RATE_SGI) -+ status->flag |= RX_FLAG_SHORT_GI; -+ -+ if (rate & MT_RXWI_RATE_STBC) -+ status->flag |= 1 << RX_FLAG_STBC_SHIFT; -+ -+ if (rate & MT_RXWI_RATE_BW) -+ status->flag |= RX_FLAG_40MHZ; -+} -+ -+static void -+mt7601u_rx_monitor_beacon(struct mt7601u_dev *dev, struct mt7601u_rxwi *rxwi, -+ u16 rate, int rssi) -+{ -+ dev->bcn_freq_off = rxwi->freq_off; -+ dev->bcn_phy_mode = MT76_GET(MT_RXWI_RATE_PHY, rate); -+ dev->avg_rssi = (dev->avg_rssi * 15) / 16 + (rssi << 8); -+} -+ -+static int -+mt7601u_rx_is_our_beacon(struct mt7601u_dev *dev, u8 *data) -+{ -+ struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)data; -+ -+ return ieee80211_is_beacon(hdr->frame_control) && -+ ether_addr_equal(hdr->addr2, dev->ap_bssid); -+} -+ -+u32 mt76_mac_process_rx(struct mt7601u_dev *dev, struct sk_buff *skb, -+ u8 *data, void *rxi) -+{ -+ struct ieee80211_rx_status *status = IEEE80211_SKB_RXCB(skb); -+ struct mt7601u_rxwi *rxwi = rxi; -+ u32 len, ctl = le32_to_cpu(rxwi->ctl); -+ u16 rate = le16_to_cpu(rxwi->rate); -+ int rssi; -+ -+ len = MT76_GET(MT_RXWI_CTL_MPDU_LEN, ctl); -+ if (len < 10) -+ return 0; -+ -+ if (rxwi->rxinfo & cpu_to_le32(MT_RXINFO_DECRYPT)) { -+ status->flag |= RX_FLAG_DECRYPTED; -+ status->flag |= RX_FLAG_IV_STRIPPED | RX_FLAG_MMIC_STRIPPED; -+ } -+ -+ status->chains = BIT(0); -+ rssi = mt7601u_phy_get_rssi(dev, rxwi, rate); -+ status->chain_signal[0] = status->signal = rssi; -+ status->freq = dev->chandef.chan->center_freq; -+ status->band = dev->chandef.chan->band; -+ -+ mt76_mac_process_rate(status, rate); -+ -+ spin_lock_bh(&dev->con_mon_lock); -+ if (mt7601u_rx_is_our_beacon(dev, data)) -+ mt7601u_rx_monitor_beacon(dev, rxwi, rate, rssi); -+ else if (rxwi->rxinfo & cpu_to_le32(MT_RXINFO_U2M)) -+ dev->avg_rssi = (dev->avg_rssi * 15) / 16 + (rssi << 8); -+ spin_unlock_bh(&dev->con_mon_lock); -+ -+ return len; -+} -+ -+static enum mt76_cipher_type -+mt76_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data) -+{ -+ memset(key_data, 0, 32); -+ if (!key) -+ return MT_CIPHER_NONE; -+ -+ if (key->keylen > 32) -+ return MT_CIPHER_NONE; -+ -+ memcpy(key_data, key->key, key->keylen); -+ -+ switch (key->cipher) { -+ case WLAN_CIPHER_SUITE_WEP40: -+ return MT_CIPHER_WEP40; -+ case WLAN_CIPHER_SUITE_WEP104: -+ return MT_CIPHER_WEP104; -+ case WLAN_CIPHER_SUITE_TKIP: -+ return MT_CIPHER_TKIP; -+ case WLAN_CIPHER_SUITE_CCMP: -+ return MT_CIPHER_AES_CCMP; -+ default: -+ return MT_CIPHER_NONE; -+ } -+} -+ -+int mt76_mac_wcid_set_key(struct mt7601u_dev *dev, u8 idx, -+ struct ieee80211_key_conf *key) -+{ -+ enum mt76_cipher_type cipher; -+ u8 key_data[32]; -+ u8 iv_data[8]; -+ u32 val; -+ -+ cipher = mt76_mac_get_key_info(key, key_data); -+ if (cipher == MT_CIPHER_NONE && key) -+ return -EINVAL; -+ -+ trace_set_key(dev, idx); -+ -+ mt7601u_wr_copy(dev, MT_WCID_KEY(idx), key_data, sizeof(key_data)); -+ -+ memset(iv_data, 0, sizeof(iv_data)); -+ if (key) { -+ iv_data[3] = key->keyidx << 6; -+ if (cipher >= MT_CIPHER_TKIP) { -+ /* Note: start with 1 to comply with spec, -+ * (see comment on common/cmm_wpa.c:4291). -+ */ -+ iv_data[0] |= 1; -+ iv_data[3] |= 0x20; -+ } -+ } -+ mt7601u_wr_copy(dev, MT_WCID_IV(idx), iv_data, sizeof(iv_data)); -+ -+ val = mt7601u_rr(dev, MT_WCID_ATTR(idx)); -+ val &= ~MT_WCID_ATTR_PKEY_MODE & ~MT_WCID_ATTR_PKEY_MODE_EXT; -+ val |= MT76_SET(MT_WCID_ATTR_PKEY_MODE, cipher & 7) | -+ MT76_SET(MT_WCID_ATTR_PKEY_MODE_EXT, cipher >> 3); -+ val &= ~MT_WCID_ATTR_PAIRWISE; -+ val |= MT_WCID_ATTR_PAIRWISE * -+ !!(key && key->flags & IEEE80211_KEY_FLAG_PAIRWISE); -+ mt7601u_wr(dev, MT_WCID_ATTR(idx), val); -+ -+ return 0; -+} -+ -+int mt76_mac_shared_key_setup(struct mt7601u_dev *dev, u8 vif_idx, u8 key_idx, -+ struct ieee80211_key_conf *key) -+{ -+ enum mt76_cipher_type cipher; -+ u8 key_data[32]; -+ u32 val; -+ -+ cipher = mt76_mac_get_key_info(key, key_data); -+ if (cipher == MT_CIPHER_NONE && key) -+ return -EINVAL; -+ -+ trace_set_shared_key(dev, vif_idx, key_idx); -+ -+ mt7601u_wr_copy(dev, MT_SKEY(vif_idx, key_idx), -+ key_data, sizeof(key_data)); -+ -+ val = mt76_rr(dev, MT_SKEY_MODE(vif_idx)); -+ val &= ~(MT_SKEY_MODE_MASK << MT_SKEY_MODE_SHIFT(vif_idx, key_idx)); -+ val |= cipher << MT_SKEY_MODE_SHIFT(vif_idx, key_idx); -+ mt76_wr(dev, MT_SKEY_MODE(vif_idx), val); -+ -+ return 0; -+} -diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/mac.h linux-rpi/drivers/net/wireless/mediatek/mt7601u/mac.h ---- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/mac.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/mac.h 2015-11-29 09:42:38.887167260 +0100 -@@ -0,0 +1,178 @@ -+/* -+ * Copyright (C) 2014 Felix Fietkau -+ * Copyright (C) 2015 Jakub Kicinski -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 -+ * as published by the Free Software Foundation -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#ifndef __MT76_MAC_H -+#define __MT76_MAC_H -+ -+struct mt76_tx_status { -+ u8 valid:1; -+ u8 success:1; -+ u8 aggr:1; -+ u8 ack_req:1; -+ u8 is_probe:1; -+ u8 wcid; -+ u8 pktid; -+ u8 retry; -+ u16 rate; -+} __packed __aligned(2); -+ -+/* Note: values in original "RSSI" and "SNR" fields are not actually what they -+ * are called for MT7601U, names used by this driver are educated guesses -+ * (see vendor mac/ral_omac.c). -+ */ -+struct mt7601u_rxwi { -+ __le32 rxinfo; -+ -+ __le32 ctl; -+ -+ __le16 frag_sn; -+ __le16 rate; -+ -+ u8 unknown; -+ u8 zero[3]; -+ -+ u8 snr; -+ u8 ant; -+ u8 gain; -+ u8 freq_off; -+ -+ __le32 resv2; -+ __le32 expert_ant; -+} __packed __aligned(4); -+ -+#define MT_RXINFO_BA BIT(0) -+#define MT_RXINFO_DATA BIT(1) -+#define MT_RXINFO_NULL BIT(2) -+#define MT_RXINFO_FRAG BIT(3) -+#define MT_RXINFO_U2M BIT(4) -+#define MT_RXINFO_MULTICAST BIT(5) -+#define MT_RXINFO_BROADCAST BIT(6) -+#define MT_RXINFO_MYBSS BIT(7) -+#define MT_RXINFO_CRCERR BIT(8) -+#define MT_RXINFO_ICVERR BIT(9) -+#define MT_RXINFO_MICERR BIT(10) -+#define MT_RXINFO_AMSDU BIT(11) -+#define MT_RXINFO_HTC BIT(12) -+#define MT_RXINFO_RSSI BIT(13) -+#define MT_RXINFO_L2PAD BIT(14) -+#define MT_RXINFO_AMPDU BIT(15) -+#define MT_RXINFO_DECRYPT BIT(16) -+#define MT_RXINFO_BSSIDX3 BIT(17) -+#define MT_RXINFO_WAPI_KEY BIT(18) -+#define MT_RXINFO_PN_LEN GENMASK(21, 19) -+#define MT_RXINFO_SW_PKT_80211 BIT(22) -+#define MT_RXINFO_TCP_SUM_BYPASS BIT(28) -+#define MT_RXINFO_IP_SUM_BYPASS BIT(29) -+#define MT_RXINFO_TCP_SUM_ERR BIT(30) -+#define MT_RXINFO_IP_SUM_ERR BIT(31) -+ -+#define MT_RXWI_CTL_WCID GENMASK(7, 0) -+#define MT_RXWI_CTL_KEY_IDX GENMASK(9, 8) -+#define MT_RXWI_CTL_BSS_IDX GENMASK(12, 10) -+#define MT_RXWI_CTL_UDF GENMASK(15, 13) -+#define MT_RXWI_CTL_MPDU_LEN GENMASK(27, 16) -+#define MT_RXWI_CTL_TID GENMASK(31, 28) -+ -+#define MT_RXWI_FRAG GENMASK(3, 0) -+#define MT_RXWI_SN GENMASK(15, 4) -+ -+#define MT_RXWI_RATE_MCS GENMASK(6, 0) -+#define MT_RXWI_RATE_BW BIT(7) -+#define MT_RXWI_RATE_SGI BIT(8) -+#define MT_RXWI_RATE_STBC GENMASK(10, 9) -+#define MT_RXWI_RATE_ETXBF BIT(11) -+#define MT_RXWI_RATE_SND BIT(12) -+#define MT_RXWI_RATE_ITXBF BIT(13) -+#define MT_RXWI_RATE_PHY GENMASK(15, 14) -+ -+#define MT_RXWI_GAIN_RSSI_VAL GENMASK(5, 0) -+#define MT_RXWI_GAIN_RSSI_LNA_ID GENMASK(7, 6) -+#define MT_RXWI_ANT_AUX_LNA BIT(7) -+ -+#define MT_RXWI_EANT_ENC_ANT_ID GENMASK(7, 0) -+ -+enum mt76_phy_type { -+ MT_PHY_TYPE_CCK, -+ MT_PHY_TYPE_OFDM, -+ MT_PHY_TYPE_HT, -+ MT_PHY_TYPE_HT_GF, -+}; -+ -+enum mt76_phy_bandwidth { -+ MT_PHY_BW_20, -+ MT_PHY_BW_40, -+}; -+ -+struct mt76_txwi { -+ __le16 flags; -+ __le16 rate_ctl; -+ -+ u8 ack_ctl; -+ u8 wcid; -+ __le16 len_ctl; -+ -+ __le32 iv; -+ -+ __le32 eiv; -+ -+ u8 aid; -+ u8 txstream; -+ __le16 ctl; -+} __packed __aligned(4); -+ -+#define MT_TXWI_FLAGS_FRAG BIT(0) -+#define MT_TXWI_FLAGS_MMPS BIT(1) -+#define MT_TXWI_FLAGS_CFACK BIT(2) -+#define MT_TXWI_FLAGS_TS BIT(3) -+#define MT_TXWI_FLAGS_AMPDU BIT(4) -+#define MT_TXWI_FLAGS_MPDU_DENSITY GENMASK(7, 5) -+#define MT_TXWI_FLAGS_TXOP GENMASK(9, 8) -+#define MT_TXWI_FLAGS_CWMIN GENMASK(12, 10) -+#define MT_TXWI_FLAGS_NO_RATE_FALLBACK BIT(13) -+#define MT_TXWI_FLAGS_TX_RPT BIT(14) -+#define MT_TXWI_FLAGS_TX_RATE_LUT BIT(15) -+ -+#define MT_TXWI_RATE_MCS GENMASK(6, 0) -+#define MT_TXWI_RATE_BW BIT(7) -+#define MT_TXWI_RATE_SGI BIT(8) -+#define MT_TXWI_RATE_STBC GENMASK(10, 9) -+#define MT_TXWI_RATE_PHY_MODE GENMASK(15, 14) -+ -+#define MT_TXWI_ACK_CTL_REQ BIT(0) -+#define MT_TXWI_ACK_CTL_NSEQ BIT(1) -+#define MT_TXWI_ACK_CTL_BA_WINDOW GENMASK(7, 2) -+ -+#define MT_TXWI_LEN_BYTE_CNT GENMASK(11, 0) -+#define MT_TXWI_LEN_PKTID GENMASK(15, 12) -+ -+#define MT_TXWI_CTL_TX_POWER_ADJ GENMASK(3, 0) -+#define MT_TXWI_CTL_CHAN_CHECK_PKT BIT(4) -+#define MT_TXWI_CTL_PIFS_REV BIT(6) -+ -+u32 mt76_mac_process_rx(struct mt7601u_dev *dev, struct sk_buff *skb, -+ u8 *data, void *rxi); -+int mt76_mac_wcid_set_key(struct mt7601u_dev *dev, u8 idx, -+ struct ieee80211_key_conf *key); -+void mt76_mac_wcid_set_rate(struct mt7601u_dev *dev, struct mt76_wcid *wcid, -+ const struct ieee80211_tx_rate *rate); -+ -+int mt76_mac_shared_key_setup(struct mt7601u_dev *dev, u8 vif_idx, u8 key_idx, -+ struct ieee80211_key_conf *key); -+u16 mt76_mac_tx_rate_val(struct mt7601u_dev *dev, -+ const struct ieee80211_tx_rate *rate, u8 *nss_val); -+struct mt76_tx_status -+mt7601u_mac_fetch_tx_status(struct mt7601u_dev *dev); -+void mt76_send_tx_status(struct mt7601u_dev *dev, struct mt76_tx_status *stat); -+ -+#endif -diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/main.c linux-rpi/drivers/net/wireless/mediatek/mt7601u/main.c ---- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/main.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/main.c 2015-11-29 09:42:38.887167260 +0100 -@@ -0,0 +1,413 @@ -+/* -+ * Copyright (C) 2014 Felix Fietkau -+ * Copyright (C) 2015 Jakub Kicinski -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 -+ * as published by the Free Software Foundation -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include "mt7601u.h" -+#include "mac.h" -+#include -+#include -+ -+static int mt7601u_start(struct ieee80211_hw *hw) -+{ -+ struct mt7601u_dev *dev = hw->priv; -+ int ret; -+ -+ mutex_lock(&dev->mutex); -+ -+ ret = mt7601u_mac_start(dev); -+ if (ret) -+ goto out; -+ -+ ieee80211_queue_delayed_work(dev->hw, &dev->mac_work, -+ MT_CALIBRATE_INTERVAL); -+ ieee80211_queue_delayed_work(dev->hw, &dev->cal_work, -+ MT_CALIBRATE_INTERVAL); -+out: -+ mutex_unlock(&dev->mutex); -+ return ret; -+} -+ -+static void mt7601u_stop(struct ieee80211_hw *hw) -+{ -+ struct mt7601u_dev *dev = hw->priv; -+ -+ mutex_lock(&dev->mutex); -+ -+ cancel_delayed_work_sync(&dev->cal_work); -+ cancel_delayed_work_sync(&dev->mac_work); -+ mt7601u_mac_stop(dev); -+ -+ mutex_unlock(&dev->mutex); -+} -+ -+static int mt7601u_add_interface(struct ieee80211_hw *hw, -+ struct ieee80211_vif *vif) -+{ -+ struct mt7601u_dev *dev = hw->priv; -+ struct mt76_vif *mvif = (struct mt76_vif *) vif->drv_priv; -+ unsigned int idx = 0; -+ unsigned int wcid = GROUP_WCID(idx); -+ -+ /* Note: for AP do the AP-STA things mt76 does: -+ * - beacon offsets -+ * - do mac address tricks -+ * - shift vif idx -+ */ -+ mvif->idx = idx; -+ -+ if (dev->wcid_mask[wcid / BITS_PER_LONG] & BIT(wcid % BITS_PER_LONG)) -+ return -ENOSPC; -+ dev->wcid_mask[wcid / BITS_PER_LONG] |= BIT(wcid % BITS_PER_LONG); -+ mvif->group_wcid.idx = wcid; -+ mvif->group_wcid.hw_key_idx = -1; -+ -+ return 0; -+} -+ -+static void mt7601u_remove_interface(struct ieee80211_hw *hw, -+ struct ieee80211_vif *vif) -+{ -+ struct mt7601u_dev *dev = hw->priv; -+ struct mt76_vif *mvif = (struct mt76_vif *) vif->drv_priv; -+ unsigned int wcid = mvif->group_wcid.idx; -+ -+ dev->wcid_mask[wcid / BITS_PER_LONG] &= ~BIT(wcid % BITS_PER_LONG); -+} -+ -+static int mt7601u_config(struct ieee80211_hw *hw, u32 changed) -+{ -+ struct mt7601u_dev *dev = hw->priv; -+ int ret = 0; -+ -+ mutex_lock(&dev->mutex); -+ -+ if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { -+ ieee80211_stop_queues(hw); -+ ret = mt7601u_phy_set_channel(dev, &hw->conf.chandef); -+ ieee80211_wake_queues(hw); -+ } -+ -+ mutex_unlock(&dev->mutex); -+ -+ return ret; -+} -+ -+static void -+mt76_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags, -+ unsigned int *total_flags, u64 multicast) -+{ -+ struct mt7601u_dev *dev = hw->priv; -+ u32 flags = 0; -+ -+#define MT76_FILTER(_flag, _hw) do { \ -+ flags |= *total_flags & FIF_##_flag; \ -+ dev->rxfilter &= ~(_hw); \ -+ dev->rxfilter |= !(flags & FIF_##_flag) * (_hw); \ -+ } while (0) -+ -+ mutex_lock(&dev->mutex); -+ -+ dev->rxfilter &= ~MT_RX_FILTR_CFG_OTHER_BSS; -+ -+ MT76_FILTER(OTHER_BSS, MT_RX_FILTR_CFG_PROMISC); -+ MT76_FILTER(FCSFAIL, MT_RX_FILTR_CFG_CRC_ERR); -+ MT76_FILTER(PLCPFAIL, MT_RX_FILTR_CFG_PHY_ERR); -+ MT76_FILTER(CONTROL, MT_RX_FILTR_CFG_ACK | -+ MT_RX_FILTR_CFG_CTS | -+ MT_RX_FILTR_CFG_CFEND | -+ MT_RX_FILTR_CFG_CFACK | -+ MT_RX_FILTR_CFG_BA | -+ MT_RX_FILTR_CFG_CTRL_RSV); -+ MT76_FILTER(PSPOLL, MT_RX_FILTR_CFG_PSPOLL); -+ -+ *total_flags = flags; -+ mt76_wr(dev, MT_RX_FILTR_CFG, dev->rxfilter); -+ -+ mutex_unlock(&dev->mutex); -+} -+ -+static void -+mt7601u_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif, -+ struct ieee80211_bss_conf *info, u32 changed) -+{ -+ struct mt7601u_dev *dev = hw->priv; -+ -+ mutex_lock(&dev->mutex); -+ -+ if (changed & BSS_CHANGED_ASSOC) -+ mt7601u_phy_con_cal_onoff(dev, info); -+ -+ if (changed & BSS_CHANGED_BSSID) { -+ mt7601u_addr_wr(dev, MT_MAC_BSSID_DW0, info->bssid); -+ -+ /* Note: this is a hack because beacon_int is not changed -+ * on leave nor is any more appropriate event generated. -+ * rt2x00 doesn't seem to be bothered though. -+ */ -+ if (is_zero_ether_addr(info->bssid)) -+ mt7601u_mac_config_tsf(dev, false, 0); -+ } -+ -+ if (changed & BSS_CHANGED_BASIC_RATES) { -+ mt7601u_wr(dev, MT_LEGACY_BASIC_RATE, info->basic_rates); -+ mt7601u_wr(dev, MT_HT_FBK_CFG0, 0x65432100); -+ mt7601u_wr(dev, MT_HT_FBK_CFG1, 0xedcba980); -+ mt7601u_wr(dev, MT_LG_FBK_CFG0, 0xedcba988); -+ mt7601u_wr(dev, MT_LG_FBK_CFG1, 0x00002100); -+ } -+ -+ if (changed & BSS_CHANGED_BEACON_INT) -+ mt7601u_mac_config_tsf(dev, true, info->beacon_int); -+ -+ if (changed & BSS_CHANGED_HT || changed & BSS_CHANGED_ERP_CTS_PROT) -+ mt7601u_mac_set_protection(dev, info->use_cts_prot, -+ info->ht_operation_mode); -+ -+ if (changed & BSS_CHANGED_ERP_PREAMBLE) -+ mt7601u_mac_set_short_preamble(dev, info->use_short_preamble); -+ -+ if (changed & BSS_CHANGED_ERP_SLOT) { -+ int slottime = info->use_short_slot ? 9 : 20; -+ -+ mt76_rmw_field(dev, MT_BKOFF_SLOT_CFG, -+ MT_BKOFF_SLOT_CFG_SLOTTIME, slottime); -+ } -+ -+ if (changed & BSS_CHANGED_ASSOC) -+ mt7601u_phy_recalibrate_after_assoc(dev); -+ -+ mutex_unlock(&dev->mutex); -+} -+ -+static int -+mt76_wcid_alloc(struct mt7601u_dev *dev) -+{ -+ int i, idx = 0; -+ -+ for (i = 0; i < ARRAY_SIZE(dev->wcid_mask); i++) { -+ idx = ffs(~dev->wcid_mask[i]); -+ if (!idx) -+ continue; -+ -+ idx--; -+ dev->wcid_mask[i] |= BIT(idx); -+ break; -+ } -+ -+ idx = i * BITS_PER_LONG + idx; -+ if (idx > 119) -+ return -1; -+ -+ return idx; -+} -+ -+static int -+mt7601u_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif, -+ struct ieee80211_sta *sta) -+{ -+ struct mt7601u_dev *dev = hw->priv; -+ struct mt76_sta *msta = (struct mt76_sta *) sta->drv_priv; -+ struct mt76_vif *mvif = (struct mt76_vif *) vif->drv_priv; -+ int ret = 0; -+ int idx = 0; -+ -+ mutex_lock(&dev->mutex); -+ -+ idx = mt76_wcid_alloc(dev); -+ if (idx < 0) { -+ ret = -ENOSPC; -+ goto out; -+ } -+ -+ msta->wcid.idx = idx; -+ msta->wcid.hw_key_idx = -1; -+ mt7601u_mac_wcid_setup(dev, idx, mvif->idx, sta->addr); -+ mt76_clear(dev, MT_WCID_DROP(idx), MT_WCID_DROP_MASK(idx)); -+ rcu_assign_pointer(dev->wcid[idx], &msta->wcid); -+ mt7601u_mac_set_ampdu_factor(dev); -+ -+out: -+ mutex_unlock(&dev->mutex); -+ -+ return ret; -+} -+ -+static int -+mt7601u_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, -+ struct ieee80211_sta *sta) -+{ -+ struct mt7601u_dev *dev = hw->priv; -+ struct mt76_sta *msta = (struct mt76_sta *) sta->drv_priv; -+ int idx = msta->wcid.idx; -+ -+ mutex_lock(&dev->mutex); -+ rcu_assign_pointer(dev->wcid[idx], NULL); -+ mt76_set(dev, MT_WCID_DROP(idx), MT_WCID_DROP_MASK(idx)); -+ dev->wcid_mask[idx / BITS_PER_LONG] &= ~BIT(idx % BITS_PER_LONG); -+ mt7601u_mac_wcid_setup(dev, idx, 0, NULL); -+ mt7601u_mac_set_ampdu_factor(dev); -+ mutex_unlock(&dev->mutex); -+ -+ return 0; -+} -+ -+static void -+mt7601u_sta_notify(struct ieee80211_hw *hw, struct ieee80211_vif *vif, -+ enum sta_notify_cmd cmd, struct ieee80211_sta *sta) -+{ -+} -+ -+static void -+mt7601u_sw_scan(struct ieee80211_hw *hw, -+ struct ieee80211_vif *vif, -+ const u8 *mac_addr) -+{ -+ struct mt7601u_dev *dev = hw->priv; -+ -+ mt7601u_agc_save(dev); -+ set_bit(MT7601U_STATE_SCANNING, &dev->state); -+} -+ -+static void -+mt7601u_sw_scan_complete(struct ieee80211_hw *hw, -+ struct ieee80211_vif *vif) -+{ -+ struct mt7601u_dev *dev = hw->priv; -+ -+ mt7601u_agc_restore(dev); -+ clear_bit(MT7601U_STATE_SCANNING, &dev->state); -+} -+ -+static int -+mt7601u_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, -+ struct ieee80211_vif *vif, struct ieee80211_sta *sta, -+ struct ieee80211_key_conf *key) -+{ -+ struct mt7601u_dev *dev = hw->priv; -+ struct mt76_vif *mvif = (struct mt76_vif *) vif->drv_priv; -+ struct mt76_sta *msta = sta ? (struct mt76_sta *) sta->drv_priv : NULL; -+ struct mt76_wcid *wcid = msta ? &msta->wcid : &mvif->group_wcid; -+ int idx = key->keyidx; -+ int ret; -+ -+ if (cmd == SET_KEY) { -+ key->hw_key_idx = wcid->idx; -+ wcid->hw_key_idx = idx; -+ } else { -+ if (idx == wcid->hw_key_idx) -+ wcid->hw_key_idx = -1; -+ -+ key = NULL; -+ } -+ -+ if (!msta) { -+ if (key || wcid->hw_key_idx == idx) { -+ ret = mt76_mac_wcid_set_key(dev, wcid->idx, key); -+ if (ret) -+ return ret; -+ } -+ -+ return mt76_mac_shared_key_setup(dev, mvif->idx, idx, key); -+ } -+ -+ return mt76_mac_wcid_set_key(dev, msta->wcid.idx, key); -+} -+ -+static int mt7601u_set_rts_threshold(struct ieee80211_hw *hw, u32 value) -+{ -+ struct mt7601u_dev *dev = hw->priv; -+ -+ mt76_rmw_field(dev, MT_TX_RTS_CFG, MT_TX_RTS_CFG_THRESH, value); -+ -+ return 0; -+} -+ -+static int -+mt76_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, -+ enum ieee80211_ampdu_mlme_action action, -+ struct ieee80211_sta *sta, u16 tid, u16 *ssn, u8 buf_size) -+{ -+ struct mt7601u_dev *dev = hw->priv; -+ struct mt76_sta *msta = (struct mt76_sta *) sta->drv_priv; -+ -+ WARN_ON(msta->wcid.idx > GROUP_WCID(0)); -+ -+ switch (action) { -+ case IEEE80211_AMPDU_RX_START: -+ mt76_set(dev, MT_WCID_ADDR(msta->wcid.idx) + 4, BIT(16 + tid)); -+ break; -+ case IEEE80211_AMPDU_RX_STOP: -+ mt76_clear(dev, MT_WCID_ADDR(msta->wcid.idx) + 4, -+ BIT(16 + tid)); -+ break; -+ case IEEE80211_AMPDU_TX_OPERATIONAL: -+ ieee80211_send_bar(vif, sta->addr, tid, msta->agg_ssn[tid]); -+ break; -+ case IEEE80211_AMPDU_TX_STOP_FLUSH: -+ case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: -+ break; -+ case IEEE80211_AMPDU_TX_START: -+ msta->agg_ssn[tid] = *ssn << 4; -+ ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); -+ break; -+ case IEEE80211_AMPDU_TX_STOP_CONT: -+ ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); -+ break; -+ } -+ -+ return 0; -+} -+ -+static void -+mt76_sta_rate_tbl_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif, -+ struct ieee80211_sta *sta) -+{ -+ struct mt7601u_dev *dev = hw->priv; -+ struct mt76_sta *msta = (struct mt76_sta *) sta->drv_priv; -+ struct ieee80211_sta_rates *rates; -+ struct ieee80211_tx_rate rate = {}; -+ -+ rcu_read_lock(); -+ rates = rcu_dereference(sta->rates); -+ -+ if (!rates) -+ goto out; -+ -+ rate.idx = rates->rate[0].idx; -+ rate.flags = rates->rate[0].flags; -+ mt76_mac_wcid_set_rate(dev, &msta->wcid, &rate); -+ -+out: -+ rcu_read_unlock(); -+} -+ -+const struct ieee80211_ops mt7601u_ops = { -+ .tx = mt7601u_tx, -+ .start = mt7601u_start, -+ .stop = mt7601u_stop, -+ .add_interface = mt7601u_add_interface, -+ .remove_interface = mt7601u_remove_interface, -+ .config = mt7601u_config, -+ .configure_filter = mt76_configure_filter, -+ .bss_info_changed = mt7601u_bss_info_changed, -+ .sta_add = mt7601u_sta_add, -+ .sta_remove = mt7601u_sta_remove, -+ .sta_notify = mt7601u_sta_notify, -+ .set_key = mt7601u_set_key, -+ .conf_tx = mt7601u_conf_tx, -+ .sw_scan_start = mt7601u_sw_scan, -+ .sw_scan_complete = mt7601u_sw_scan_complete, -+ .ampdu_action = mt76_ampdu_action, -+ .sta_rate_tbl_update = mt76_sta_rate_tbl_update, -+ .set_rts_threshold = mt7601u_set_rts_threshold, -+}; -diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/Makefile linux-rpi/drivers/net/wireless/mediatek/mt7601u/Makefile ---- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/Makefile 2015-11-29 09:42:38.887167260 +0100 -@@ -0,0 +1,9 @@ -+ccflags-y += -D__CHECK_ENDIAN__ -+ -+obj-$(CONFIG_MT7601U) += mt7601u.o -+ -+mt7601u-objs = \ -+ usb.o init.o main.o mcu.o trace.o dma.o core.o eeprom.o phy.o \ -+ mac.o util.o debugfs.o tx.o -+ -+CFLAGS_trace.o := -I$(src) -diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/mcu.c linux-rpi/drivers/net/wireless/mediatek/mt7601u/mcu.c ---- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/mcu.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/mcu.c 2015-11-29 09:42:38.887167260 +0100 -@@ -0,0 +1,534 @@ -+/* -+ * (c) Copyright 2002-2010, Ralink Technology, Inc. -+ * Copyright (C) 2014 Felix Fietkau -+ * Copyright (C) 2015 Jakub Kicinski -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 -+ * as published by the Free Software Foundation -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "mt7601u.h" -+#include "dma.h" -+#include "mcu.h" -+#include "usb.h" -+#include "trace.h" -+ -+#define MCU_FW_URB_MAX_PAYLOAD 0x3800 -+#define MCU_FW_URB_SIZE (MCU_FW_URB_MAX_PAYLOAD + 12) -+#define MCU_RESP_URB_SIZE 1024 -+ -+static inline int firmware_running(struct mt7601u_dev *dev) -+{ -+ return mt7601u_rr(dev, MT_MCU_COM_REG0) == 1; -+} -+ -+static inline void skb_put_le32(struct sk_buff *skb, u32 val) -+{ -+ put_unaligned_le32(val, skb_put(skb, 4)); -+} -+ -+static inline void mt7601u_dma_skb_wrap_cmd(struct sk_buff *skb, -+ u8 seq, enum mcu_cmd cmd) -+{ -+ WARN_ON(mt7601u_dma_skb_wrap(skb, CPU_TX_PORT, DMA_COMMAND, -+ MT76_SET(MT_TXD_CMD_INFO_SEQ, seq) | -+ MT76_SET(MT_TXD_CMD_INFO_TYPE, cmd))); -+} -+ -+static inline void trace_mt_mcu_msg_send_cs(struct mt7601u_dev *dev, -+ struct sk_buff *skb, bool need_resp) -+{ -+ u32 i, csum = 0; -+ -+ for (i = 0; i < skb->len / 4; i++) -+ csum ^= get_unaligned_le32(skb->data + i * 4); -+ -+ trace_mt_mcu_msg_send(dev, skb, csum, need_resp); -+} -+ -+static struct sk_buff * -+mt7601u_mcu_msg_alloc(struct mt7601u_dev *dev, const void *data, int len) -+{ -+ struct sk_buff *skb; -+ -+ WARN_ON(len % 4); /* if length is not divisible by 4 we need to pad */ -+ -+ skb = alloc_skb(len + MT_DMA_HDR_LEN + 4, GFP_KERNEL); -+ skb_reserve(skb, MT_DMA_HDR_LEN); -+ memcpy(skb_put(skb, len), data, len); -+ -+ return skb; -+} -+ -+static int mt7601u_mcu_wait_resp(struct mt7601u_dev *dev, u8 seq) -+{ -+ struct urb *urb = dev->mcu.resp.urb; -+ u32 rxfce; -+ int urb_status, ret, i = 5; -+ -+ while (i--) { -+ if (!wait_for_completion_timeout(&dev->mcu.resp_cmpl, -+ msecs_to_jiffies(300))) { -+ dev_warn(dev->dev, "Warning: %s retrying\n", __func__); -+ continue; -+ } -+ -+ /* Make copies of important data before reusing the urb */ -+ rxfce = get_unaligned_le32(dev->mcu.resp.buf); -+ urb_status = urb->status * mt7601u_urb_has_error(urb); -+ -+ ret = mt7601u_usb_submit_buf(dev, USB_DIR_IN, MT_EP_IN_CMD_RESP, -+ &dev->mcu.resp, GFP_KERNEL, -+ mt7601u_complete_urb, -+ &dev->mcu.resp_cmpl); -+ if (ret) -+ return ret; -+ -+ if (urb_status) -+ dev_err(dev->dev, "Error: MCU resp urb failed:%d\n", -+ urb_status); -+ -+ if (MT76_GET(MT_RXD_CMD_INFO_CMD_SEQ, rxfce) == seq && -+ MT76_GET(MT_RXD_CMD_INFO_EVT_TYPE, rxfce) == CMD_DONE) -+ return 0; -+ -+ dev_err(dev->dev, "Error: MCU resp evt:%hhx seq:%hhx-%hhx!\n", -+ MT76_GET(MT_RXD_CMD_INFO_EVT_TYPE, rxfce), -+ seq, MT76_GET(MT_RXD_CMD_INFO_CMD_SEQ, rxfce)); -+ } -+ -+ dev_err(dev->dev, "Error: %s timed out\n", __func__); -+ return -ETIMEDOUT; -+} -+ -+static int -+mt7601u_mcu_msg_send(struct mt7601u_dev *dev, struct sk_buff *skb, -+ enum mcu_cmd cmd, bool wait_resp) -+{ -+ struct usb_device *usb_dev = mt7601u_to_usb_dev(dev); -+ unsigned cmd_pipe = usb_sndbulkpipe(usb_dev, -+ dev->out_eps[MT_EP_OUT_INBAND_CMD]); -+ int sent, ret; -+ u8 seq = 0; -+ -+ if (test_bit(MT7601U_STATE_REMOVED, &dev->state)) -+ return 0; -+ -+ mutex_lock(&dev->mcu.mutex); -+ -+ if (wait_resp) -+ while (!seq) -+ seq = ++dev->mcu.msg_seq & 0xf; -+ -+ mt7601u_dma_skb_wrap_cmd(skb, seq, cmd); -+ -+ if (dev->mcu.resp_cmpl.done) -+ dev_err(dev->dev, "Error: MCU response pre-completed!\n"); -+ -+ trace_mt_mcu_msg_send_cs(dev, skb, wait_resp); -+ trace_mt_submit_urb_sync(dev, cmd_pipe, skb->len); -+ ret = usb_bulk_msg(usb_dev, cmd_pipe, skb->data, skb->len, &sent, 500); -+ if (ret) { -+ dev_err(dev->dev, "Error: send MCU cmd failed:%d\n", ret); -+ goto out; -+ } -+ if (sent != skb->len) -+ dev_err(dev->dev, "Error: %s sent != skb->len\n", __func__); -+ -+ if (wait_resp) -+ ret = mt7601u_mcu_wait_resp(dev, seq); -+out: -+ mutex_unlock(&dev->mcu.mutex); -+ -+ consume_skb(skb); -+ -+ return ret; -+} -+ -+static int mt7601u_mcu_function_select(struct mt7601u_dev *dev, -+ enum mcu_function func, u32 val) -+{ -+ struct sk_buff *skb; -+ struct { -+ __le32 id; -+ __le32 value; -+ } __packed __aligned(4) msg = { -+ .id = cpu_to_le32(func), -+ .value = cpu_to_le32(val), -+ }; -+ -+ skb = mt7601u_mcu_msg_alloc(dev, &msg, sizeof(msg)); -+ return mt7601u_mcu_msg_send(dev, skb, CMD_FUN_SET_OP, func == 5); -+} -+ -+int mt7601u_mcu_tssi_read_kick(struct mt7601u_dev *dev, int use_hvga) -+{ -+ int ret; -+ -+ if (!test_bit(MT7601U_STATE_MCU_RUNNING, &dev->state)) -+ return 0; -+ -+ ret = mt7601u_mcu_function_select(dev, ATOMIC_TSSI_SETTING, -+ use_hvga); -+ if (ret) { -+ dev_warn(dev->dev, "Warning: MCU TSSI read kick failed\n"); -+ return ret; -+ } -+ -+ dev->tssi_read_trig = true; -+ -+ return 0; -+} -+ -+int -+mt7601u_mcu_calibrate(struct mt7601u_dev *dev, enum mcu_calibrate cal, u32 val) -+{ -+ struct sk_buff *skb; -+ struct { -+ __le32 id; -+ __le32 value; -+ } __packed __aligned(4) msg = { -+ .id = cpu_to_le32(cal), -+ .value = cpu_to_le32(val), -+ }; -+ -+ skb = mt7601u_mcu_msg_alloc(dev, &msg, sizeof(msg)); -+ return mt7601u_mcu_msg_send(dev, skb, CMD_CALIBRATION_OP, true); -+} -+ -+int mt7601u_write_reg_pairs(struct mt7601u_dev *dev, u32 base, -+ const struct mt76_reg_pair *data, int n) -+{ -+ const int max_vals_per_cmd = INBAND_PACKET_MAX_LEN / 8; -+ struct sk_buff *skb; -+ int cnt, i, ret; -+ -+ if (!n) -+ return 0; -+ -+ cnt = min(max_vals_per_cmd, n); -+ -+ skb = alloc_skb(cnt * 8 + MT_DMA_HDR_LEN + 4, GFP_KERNEL); -+ if (!skb) -+ return -ENOMEM; -+ skb_reserve(skb, MT_DMA_HDR_LEN); -+ -+ for (i = 0; i < cnt; i++) { -+ skb_put_le32(skb, base + data[i].reg); -+ skb_put_le32(skb, data[i].value); -+ } -+ -+ ret = mt7601u_mcu_msg_send(dev, skb, CMD_RANDOM_WRITE, cnt == n); -+ if (ret) -+ return ret; -+ -+ return mt7601u_write_reg_pairs(dev, base, data + cnt, n - cnt); -+} -+ -+int mt7601u_burst_write_regs(struct mt7601u_dev *dev, u32 offset, -+ const u32 *data, int n) -+{ -+ const int max_regs_per_cmd = INBAND_PACKET_MAX_LEN / 4 - 1; -+ struct sk_buff *skb; -+ int cnt, i, ret; -+ -+ if (!n) -+ return 0; -+ -+ cnt = min(max_regs_per_cmd, n); -+ -+ skb = alloc_skb(cnt * 4 + MT_DMA_HDR_LEN + 4, GFP_KERNEL); -+ if (!skb) -+ return -ENOMEM; -+ skb_reserve(skb, MT_DMA_HDR_LEN); -+ -+ skb_put_le32(skb, MT_MCU_MEMMAP_WLAN + offset); -+ for (i = 0; i < cnt; i++) -+ skb_put_le32(skb, data[i]); -+ -+ ret = mt7601u_mcu_msg_send(dev, skb, CMD_BURST_WRITE, cnt == n); -+ if (ret) -+ return ret; -+ -+ return mt7601u_burst_write_regs(dev, offset + cnt * 4, -+ data + cnt, n - cnt); -+} -+ -+struct mt76_fw_header { -+ __le32 ilm_len; -+ __le32 dlm_len; -+ __le16 build_ver; -+ __le16 fw_ver; -+ u8 pad[4]; -+ char build_time[16]; -+}; -+ -+struct mt76_fw { -+ struct mt76_fw_header hdr; -+ u8 ivb[MT_MCU_IVB_SIZE]; -+ u8 ilm[]; -+}; -+ -+static int __mt7601u_dma_fw(struct mt7601u_dev *dev, -+ const struct mt7601u_dma_buf *dma_buf, -+ const void *data, u32 len, u32 dst_addr) -+{ -+ DECLARE_COMPLETION_ONSTACK(cmpl); -+ struct mt7601u_dma_buf buf = *dma_buf; /* we need to fake length */ -+ __le32 reg; -+ u32 val; -+ int ret; -+ -+ reg = cpu_to_le32(MT76_SET(MT_TXD_INFO_TYPE, DMA_PACKET) | -+ MT76_SET(MT_TXD_INFO_D_PORT, CPU_TX_PORT) | -+ MT76_SET(MT_TXD_INFO_LEN, len)); -+ memcpy(buf.buf, ®, sizeof(reg)); -+ memcpy(buf.buf + sizeof(reg), data, len); -+ memset(buf.buf + sizeof(reg) + len, 0, 8); -+ -+ ret = mt7601u_vendor_single_wr(dev, MT_VEND_WRITE_FCE, -+ MT_FCE_DMA_ADDR, dst_addr); -+ if (ret) -+ return ret; -+ len = roundup(len, 4); -+ ret = mt7601u_vendor_single_wr(dev, MT_VEND_WRITE_FCE, -+ MT_FCE_DMA_LEN, len << 16); -+ if (ret) -+ return ret; -+ -+ buf.len = MT_DMA_HDR_LEN + len + 4; -+ ret = mt7601u_usb_submit_buf(dev, USB_DIR_OUT, MT_EP_OUT_INBAND_CMD, -+ &buf, GFP_KERNEL, -+ mt7601u_complete_urb, &cmpl); -+ if (ret) -+ return ret; -+ -+ if (!wait_for_completion_timeout(&cmpl, msecs_to_jiffies(1000))) { -+ dev_err(dev->dev, "Error: firmware upload timed out\n"); -+ usb_kill_urb(buf.urb); -+ return -ETIMEDOUT; -+ } -+ if (mt7601u_urb_has_error(buf.urb)) { -+ dev_err(dev->dev, "Error: firmware upload urb failed:%d\n", -+ buf.urb->status); -+ return buf.urb->status; -+ } -+ -+ val = mt7601u_rr(dev, MT_TX_CPU_FROM_FCE_CPU_DESC_IDX); -+ val++; -+ mt7601u_wr(dev, MT_TX_CPU_FROM_FCE_CPU_DESC_IDX, val); -+ -+ return 0; -+} -+ -+static int -+mt7601u_dma_fw(struct mt7601u_dev *dev, struct mt7601u_dma_buf *dma_buf, -+ const void *data, int len, u32 dst_addr) -+{ -+ int n, ret; -+ -+ if (len == 0) -+ return 0; -+ -+ n = min(MCU_FW_URB_MAX_PAYLOAD, len); -+ ret = __mt7601u_dma_fw(dev, dma_buf, data, n, dst_addr); -+ if (ret) -+ return ret; -+ -+ if (!mt76_poll_msec(dev, MT_MCU_COM_REG1, BIT(31), BIT(31), 500)) -+ return -ETIMEDOUT; -+ -+ return mt7601u_dma_fw(dev, dma_buf, data + n, len - n, dst_addr + n); -+} -+ -+static int -+mt7601u_upload_firmware(struct mt7601u_dev *dev, const struct mt76_fw *fw) -+{ -+ struct mt7601u_dma_buf dma_buf; -+ void *ivb; -+ u32 ilm_len, dlm_len; -+ int i, ret; -+ -+ ivb = kmemdup(fw->ivb, sizeof(fw->ivb), GFP_KERNEL); -+ if (!ivb || mt7601u_usb_alloc_buf(dev, MCU_FW_URB_SIZE, &dma_buf)) { -+ ret = -ENOMEM; -+ goto error; -+ } -+ -+ ilm_len = le32_to_cpu(fw->hdr.ilm_len) - sizeof(fw->ivb); -+ dev_dbg(dev->dev, "loading FW - ILM %u + IVB %zu\n", -+ ilm_len, sizeof(fw->ivb)); -+ ret = mt7601u_dma_fw(dev, &dma_buf, fw->ilm, ilm_len, sizeof(fw->ivb)); -+ if (ret) -+ goto error; -+ -+ dlm_len = le32_to_cpu(fw->hdr.dlm_len); -+ dev_dbg(dev->dev, "loading FW - DLM %u\n", dlm_len); -+ ret = mt7601u_dma_fw(dev, &dma_buf, fw->ilm + ilm_len, -+ dlm_len, MT_MCU_DLM_OFFSET); -+ if (ret) -+ goto error; -+ -+ ret = mt7601u_vendor_request(dev, MT_VEND_DEV_MODE, USB_DIR_OUT, -+ 0x12, 0, ivb, sizeof(fw->ivb)); -+ if (ret < 0) -+ goto error; -+ ret = 0; -+ -+ for (i = 100; i && !firmware_running(dev); i--) -+ msleep(10); -+ if (!i) { -+ ret = -ETIMEDOUT; -+ goto error; -+ } -+ -+ dev_dbg(dev->dev, "Firmware running!\n"); -+error: -+ kfree(ivb); -+ mt7601u_usb_free_buf(dev, &dma_buf); -+ -+ return ret; -+} -+ -+static int mt7601u_load_firmware(struct mt7601u_dev *dev) -+{ -+ const struct firmware *fw; -+ const struct mt76_fw_header *hdr; -+ int len, ret; -+ u32 val; -+ -+ mt7601u_wr(dev, MT_USB_DMA_CFG, (MT_USB_DMA_CFG_RX_BULK_EN | -+ MT_USB_DMA_CFG_TX_BULK_EN)); -+ -+ if (firmware_running(dev)) -+ return 0; -+ -+ ret = request_firmware(&fw, MT7601U_FIRMWARE, dev->dev); -+ if (ret) -+ return ret; -+ -+ if (!fw || !fw->data || fw->size < sizeof(*hdr)) -+ goto err_inv_fw; -+ -+ hdr = (const struct mt76_fw_header *) fw->data; -+ -+ if (le32_to_cpu(hdr->ilm_len) <= MT_MCU_IVB_SIZE) -+ goto err_inv_fw; -+ -+ len = sizeof(*hdr); -+ len += le32_to_cpu(hdr->ilm_len); -+ len += le32_to_cpu(hdr->dlm_len); -+ -+ if (fw->size != len) -+ goto err_inv_fw; -+ -+ val = le16_to_cpu(hdr->fw_ver); -+ dev_info(dev->dev, -+ "Firmware Version: %d.%d.%02d Build: %x Build time: %.16s\n", -+ (val >> 12) & 0xf, (val >> 8) & 0xf, val & 0xf, -+ le16_to_cpu(hdr->build_ver), hdr->build_time); -+ -+ len = le32_to_cpu(hdr->ilm_len); -+ -+ mt7601u_wr(dev, 0x94c, 0); -+ mt7601u_wr(dev, MT_FCE_PSE_CTRL, 0); -+ -+ mt7601u_vendor_reset(dev); -+ msleep(5); -+ -+ mt7601u_wr(dev, 0xa44, 0); -+ mt7601u_wr(dev, 0x230, 0x84210); -+ mt7601u_wr(dev, 0x400, 0x80c00); -+ mt7601u_wr(dev, 0x800, 1); -+ -+ mt7601u_rmw(dev, MT_PBF_CFG, 0, (MT_PBF_CFG_TX0Q_EN | -+ MT_PBF_CFG_TX1Q_EN | -+ MT_PBF_CFG_TX2Q_EN | -+ MT_PBF_CFG_TX3Q_EN)); -+ -+ mt7601u_wr(dev, MT_FCE_PSE_CTRL, 1); -+ -+ mt7601u_wr(dev, MT_USB_DMA_CFG, (MT_USB_DMA_CFG_RX_BULK_EN | -+ MT_USB_DMA_CFG_TX_BULK_EN)); -+ val = mt76_set(dev, MT_USB_DMA_CFG, MT_USB_DMA_CFG_TX_CLR); -+ val &= ~MT_USB_DMA_CFG_TX_CLR; -+ mt7601u_wr(dev, MT_USB_DMA_CFG, val); -+ -+ /* FCE tx_fs_base_ptr */ -+ mt7601u_wr(dev, MT_TX_CPU_FROM_FCE_BASE_PTR, 0x400230); -+ /* FCE tx_fs_max_cnt */ -+ mt7601u_wr(dev, MT_TX_CPU_FROM_FCE_MAX_COUNT, 1); -+ /* FCE pdma enable */ -+ mt7601u_wr(dev, MT_FCE_PDMA_GLOBAL_CONF, 0x44); -+ /* FCE skip_fs_en */ -+ mt7601u_wr(dev, MT_FCE_SKIP_FS, 3); -+ -+ ret = mt7601u_upload_firmware(dev, (const struct mt76_fw *)fw->data); -+ -+ release_firmware(fw); -+ -+ return ret; -+ -+err_inv_fw: -+ dev_err(dev->dev, "Invalid firmware image\n"); -+ release_firmware(fw); -+ return -ENOENT; -+} -+ -+int mt7601u_mcu_init(struct mt7601u_dev *dev) -+{ -+ int ret; -+ -+ mutex_init(&dev->mcu.mutex); -+ -+ ret = mt7601u_load_firmware(dev); -+ if (ret) -+ return ret; -+ -+ set_bit(MT7601U_STATE_MCU_RUNNING, &dev->state); -+ -+ return 0; -+} -+ -+int mt7601u_mcu_cmd_init(struct mt7601u_dev *dev) -+{ -+ int ret; -+ -+ ret = mt7601u_mcu_function_select(dev, Q_SELECT, 1); -+ if (ret) -+ return ret; -+ -+ init_completion(&dev->mcu.resp_cmpl); -+ if (mt7601u_usb_alloc_buf(dev, MCU_RESP_URB_SIZE, &dev->mcu.resp)) { -+ mt7601u_usb_free_buf(dev, &dev->mcu.resp); -+ return -ENOMEM; -+ } -+ -+ ret = mt7601u_usb_submit_buf(dev, USB_DIR_IN, MT_EP_IN_CMD_RESP, -+ &dev->mcu.resp, GFP_KERNEL, -+ mt7601u_complete_urb, &dev->mcu.resp_cmpl); -+ if (ret) { -+ mt7601u_usb_free_buf(dev, &dev->mcu.resp); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+void mt7601u_mcu_cmd_deinit(struct mt7601u_dev *dev) -+{ -+ usb_kill_urb(dev->mcu.resp.urb); -+ mt7601u_usb_free_buf(dev, &dev->mcu.resp); -+} -diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/mcu.h linux-rpi/drivers/net/wireless/mediatek/mt7601u/mcu.h ---- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/mcu.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/mcu.h 2015-11-29 09:42:38.887167260 +0100 -@@ -0,0 +1,94 @@ -+/* -+ * Copyright (C) 2014 Felix Fietkau -+ * Copyright (C) 2015 Jakub Kicinski -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 -+ * as published by the Free Software Foundation -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#ifndef __MT7601U_MCU_H -+#define __MT7601U_MCU_H -+ -+struct mt7601u_dev; -+ -+/* Register definitions */ -+#define MT_MCU_RESET_CTL 0x070C -+#define MT_MCU_INT_LEVEL 0x0718 -+#define MT_MCU_COM_REG0 0x0730 -+#define MT_MCU_COM_REG1 0x0734 -+#define MT_MCU_COM_REG2 0x0738 -+#define MT_MCU_COM_REG3 0x073C -+ -+#define MT_MCU_IVB_SIZE 0x40 -+#define MT_MCU_DLM_OFFSET 0x80000 -+ -+#define MT_MCU_MEMMAP_WLAN 0x00410000 -+#define MT_MCU_MEMMAP_BBP 0x40000000 -+#define MT_MCU_MEMMAP_RF 0x80000000 -+ -+#define INBAND_PACKET_MAX_LEN 192 -+ -+enum mcu_cmd { -+ CMD_FUN_SET_OP = 1, -+ CMD_LOAD_CR = 2, -+ CMD_INIT_GAIN_OP = 3, -+ CMD_DYNC_VGA_OP = 6, -+ CMD_TDLS_CH_SW = 7, -+ CMD_BURST_WRITE = 8, -+ CMD_READ_MODIFY_WRITE = 9, -+ CMD_RANDOM_READ = 10, -+ CMD_BURST_READ = 11, -+ CMD_RANDOM_WRITE = 12, -+ CMD_LED_MODE_OP = 16, -+ CMD_POWER_SAVING_OP = 20, -+ CMD_WOW_CONFIG = 21, -+ CMD_WOW_QUERY = 22, -+ CMD_WOW_FEATURE = 24, -+ CMD_CARRIER_DETECT_OP = 28, -+ CMD_RADOR_DETECT_OP = 29, -+ CMD_SWITCH_CHANNEL_OP = 30, -+ CMD_CALIBRATION_OP = 31, -+ CMD_BEACON_OP = 32, -+ CMD_ANTENNA_OP = 33, -+}; -+ -+enum mcu_function { -+ Q_SELECT = 1, -+ ATOMIC_TSSI_SETTING = 5, -+}; -+ -+enum mcu_power_mode { -+ RADIO_OFF = 0x30, -+ RADIO_ON = 0x31, -+ RADIO_OFF_AUTO_WAKEUP = 0x32, -+ RADIO_OFF_ADVANCE = 0x33, -+ RADIO_ON_ADVANCE = 0x34, -+}; -+ -+enum mcu_calibrate { -+ MCU_CAL_R = 1, -+ MCU_CAL_DCOC, -+ MCU_CAL_LC, -+ MCU_CAL_LOFT, -+ MCU_CAL_TXIQ, -+ MCU_CAL_BW, -+ MCU_CAL_DPD, -+ MCU_CAL_RXIQ, -+ MCU_CAL_TXDCOC, -+}; -+ -+int mt7601u_mcu_init(struct mt7601u_dev *dev); -+int mt7601u_mcu_cmd_init(struct mt7601u_dev *dev); -+void mt7601u_mcu_cmd_deinit(struct mt7601u_dev *dev); -+ -+int -+mt7601u_mcu_calibrate(struct mt7601u_dev *dev, enum mcu_calibrate cal, u32 val); -+int mt7601u_mcu_tssi_read_kick(struct mt7601u_dev *dev, int use_hvga); -+ -+#endif -diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/mt7601u.h linux-rpi/drivers/net/wireless/mediatek/mt7601u/mt7601u.h ---- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/mt7601u.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/mt7601u.h 2015-11-29 09:42:38.887167260 +0100 -@@ -0,0 +1,396 @@ -+/* -+ * Copyright (C) 2014 Felix Fietkau -+ * Copyright (C) 2015 Jakub Kicinski -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 -+ * as published by the Free Software Foundation -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#ifndef MT7601U_H -+#define MT7601U_H -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "regs.h" -+#include "util.h" -+ -+#define MT_CALIBRATE_INTERVAL (4 * HZ) -+ -+#define MT_FREQ_CAL_INIT_DELAY (30 * HZ) -+#define MT_FREQ_CAL_CHECK_INTERVAL (10 * HZ) -+#define MT_FREQ_CAL_ADJ_INTERVAL (HZ / 2) -+ -+#define MT_BBP_REG_VERSION 0x00 -+ -+#define MT_USB_AGGR_SIZE_LIMIT 28 /* * 1024B */ -+#define MT_USB_AGGR_TIMEOUT 0x80 /* * 33ns */ -+#define MT_RX_ORDER 3 -+#define MT_RX_URB_SIZE (PAGE_SIZE << MT_RX_ORDER) -+ -+struct mt7601u_dma_buf { -+ struct urb *urb; -+ void *buf; -+ dma_addr_t dma; -+ size_t len; -+}; -+ -+struct mt7601u_mcu { -+ struct mutex mutex; -+ -+ u8 msg_seq; -+ -+ struct mt7601u_dma_buf resp; -+ struct completion resp_cmpl; -+}; -+ -+struct mt7601u_freq_cal { -+ struct delayed_work work; -+ u8 freq; -+ bool enabled; -+ bool adjusting; -+}; -+ -+struct mac_stats { -+ u64 rx_stat[6]; -+ u64 tx_stat[6]; -+ u64 aggr_stat[2]; -+ u64 aggr_n[32]; -+ u64 zero_len_del[2]; -+}; -+ -+#define N_RX_ENTRIES 16 -+struct mt7601u_rx_queue { -+ struct mt7601u_dev *dev; -+ -+ struct mt7601u_dma_buf_rx { -+ struct urb *urb; -+ struct page *p; -+ } e[N_RX_ENTRIES]; -+ -+ unsigned int start; -+ unsigned int end; -+ unsigned int entries; -+ unsigned int pending; -+}; -+ -+#define N_TX_ENTRIES 64 -+ -+struct mt7601u_tx_queue { -+ struct mt7601u_dev *dev; -+ -+ struct mt7601u_dma_buf_tx { -+ struct urb *urb; -+ struct sk_buff *skb; -+ } e[N_TX_ENTRIES]; -+ -+ unsigned int start; -+ unsigned int end; -+ unsigned int entries; -+ unsigned int used; -+ unsigned int fifo_seq; -+}; -+ -+/* WCID allocation: -+ * 0: mcast wcid -+ * 1: bssid wcid -+ * 1...: STAs -+ * ...7e: group wcids -+ * 7f: reserved -+ */ -+#define N_WCIDS 128 -+#define GROUP_WCID(idx) (N_WCIDS - 2 - idx) -+ -+struct mt7601u_eeprom_params; -+ -+#define MT_EE_TEMPERATURE_SLOPE 39 -+#define MT_FREQ_OFFSET_INVALID -128 -+ -+enum mt_temp_mode { -+ MT_TEMP_MODE_NORMAL, -+ MT_TEMP_MODE_HIGH, -+ MT_TEMP_MODE_LOW, -+}; -+ -+enum mt_bw { -+ MT_BW_20, -+ MT_BW_40, -+}; -+ -+enum { -+ MT7601U_STATE_INITIALIZED, -+ MT7601U_STATE_REMOVED, -+ MT7601U_STATE_WLAN_RUNNING, -+ MT7601U_STATE_MCU_RUNNING, -+ MT7601U_STATE_SCANNING, -+ MT7601U_STATE_READING_STATS, -+ MT7601U_STATE_MORE_STATS, -+}; -+ -+/** -+ * struct mt7601u_dev - adapter structure -+ * @lock: protects @wcid->tx_rate. -+ * @mac_lock: locks out mac80211's tx status and rx paths. -+ * @tx_lock: protects @tx_q and changes of MT7601U_STATE_*_STATS -+ * flags in @state. -+ * @rx_lock: protects @rx_q. -+ * @con_mon_lock: protects @ap_bssid, @bcn_*, @avg_rssi. -+ * @mutex: ensures exclusive access from mac80211 callbacks. -+ * @vendor_req_mutex: protects @vend_buf, ensures atomicity of split writes. -+ * @reg_atomic_mutex: ensures atomicity of indirect register accesses -+ * (accesses to RF and BBP). -+ * @hw_atomic_mutex: ensures exclusive access to HW during critical -+ * operations (power management, channel switch). -+ */ -+struct mt7601u_dev { -+ struct ieee80211_hw *hw; -+ struct device *dev; -+ -+ unsigned long state; -+ -+ struct mutex mutex; -+ -+ unsigned long wcid_mask[N_WCIDS / BITS_PER_LONG]; -+ -+ struct cfg80211_chan_def chandef; -+ struct ieee80211_supported_band *sband_2g; -+ -+ struct mt7601u_mcu mcu; -+ -+ struct delayed_work cal_work; -+ struct delayed_work mac_work; -+ -+ struct workqueue_struct *stat_wq; -+ struct delayed_work stat_work; -+ -+ struct mt76_wcid *mon_wcid; -+ struct mt76_wcid __rcu *wcid[N_WCIDS]; -+ -+ spinlock_t lock; -+ spinlock_t mac_lock; -+ -+ const u16 *beacon_offsets; -+ -+ u8 macaddr[ETH_ALEN]; -+ struct mt7601u_eeprom_params *ee; -+ -+ struct mutex vendor_req_mutex; -+ void *vend_buf; -+ -+ struct mutex reg_atomic_mutex; -+ struct mutex hw_atomic_mutex; -+ -+ u32 rxfilter; -+ u32 debugfs_reg; -+ -+ u8 out_eps[8]; -+ u8 in_eps[8]; -+ u16 out_max_packet; -+ u16 in_max_packet; -+ -+ /* TX */ -+ spinlock_t tx_lock; -+ struct tasklet_struct tx_tasklet; -+ struct mt7601u_tx_queue *tx_q; -+ struct sk_buff_head tx_skb_done; -+ -+ atomic_t avg_ampdu_len; -+ -+ /* RX */ -+ spinlock_t rx_lock; -+ struct tasklet_struct rx_tasklet; -+ struct mt7601u_rx_queue rx_q; -+ -+ /* Connection monitoring things */ -+ spinlock_t con_mon_lock; -+ u8 ap_bssid[ETH_ALEN]; -+ -+ s8 bcn_freq_off; -+ u8 bcn_phy_mode; -+ -+ int avg_rssi; /* starts at 0 and converges */ -+ -+ u8 agc_save; -+ -+ struct mt7601u_freq_cal freq_cal; -+ -+ bool tssi_read_trig; -+ -+ s8 tssi_init; -+ s8 tssi_init_hvga; -+ s16 tssi_init_hvga_offset_db; -+ -+ int prev_pwr_diff; -+ -+ enum mt_temp_mode temp_mode; -+ int curr_temp; -+ int dpd_temp; -+ s8 raw_temp; -+ bool pll_lock_protect; -+ -+ u8 bw; -+ bool chan_ext_below; -+ -+ /* PA mode */ -+ u32 rf_pa_mode[2]; -+ -+ struct mac_stats stats; -+}; -+ -+struct mt7601u_tssi_params { -+ char tssi0; -+ int trgt_power; -+}; -+ -+struct mt76_wcid { -+ u8 idx; -+ u8 hw_key_idx; -+ -+ u16 tx_rate; -+ bool tx_rate_set; -+ u8 tx_rate_nss; -+}; -+ -+struct mt76_vif { -+ u8 idx; -+ -+ struct mt76_wcid group_wcid; -+}; -+ -+struct mt76_sta { -+ struct mt76_wcid wcid; -+ u16 agg_ssn[IEEE80211_NUM_TIDS]; -+}; -+ -+struct mt76_reg_pair { -+ u32 reg; -+ u32 value; -+}; -+ -+struct mt7601u_rxwi; -+ -+extern const struct ieee80211_ops mt7601u_ops; -+ -+void mt7601u_init_debugfs(struct mt7601u_dev *dev); -+ -+u32 mt7601u_rr(struct mt7601u_dev *dev, u32 offset); -+void mt7601u_wr(struct mt7601u_dev *dev, u32 offset, u32 val); -+u32 mt7601u_rmw(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val); -+u32 mt7601u_rmc(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val); -+void mt7601u_wr_copy(struct mt7601u_dev *dev, u32 offset, -+ const void *data, int len); -+ -+int mt7601u_wait_asic_ready(struct mt7601u_dev *dev); -+bool mt76_poll(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val, -+ int timeout); -+bool mt76_poll_msec(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val, -+ int timeout); -+ -+/* Compatibility with mt76 */ -+#define mt76_rmw_field(_dev, _reg, _field, _val) \ -+ mt76_rmw(_dev, _reg, _field, MT76_SET(_field, _val)) -+ -+static inline u32 mt76_rr(struct mt7601u_dev *dev, u32 offset) -+{ -+ return mt7601u_rr(dev, offset); -+} -+ -+static inline void mt76_wr(struct mt7601u_dev *dev, u32 offset, u32 val) -+{ -+ return mt7601u_wr(dev, offset, val); -+} -+ -+static inline u32 -+mt76_rmw(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val) -+{ -+ return mt7601u_rmw(dev, offset, mask, val); -+} -+ -+static inline u32 mt76_set(struct mt7601u_dev *dev, u32 offset, u32 val) -+{ -+ return mt76_rmw(dev, offset, 0, val); -+} -+ -+static inline u32 mt76_clear(struct mt7601u_dev *dev, u32 offset, u32 val) -+{ -+ return mt76_rmw(dev, offset, val, 0); -+} -+ -+int mt7601u_write_reg_pairs(struct mt7601u_dev *dev, u32 base, -+ const struct mt76_reg_pair *data, int len); -+int mt7601u_burst_write_regs(struct mt7601u_dev *dev, u32 offset, -+ const u32 *data, int n); -+void mt7601u_addr_wr(struct mt7601u_dev *dev, const u32 offset, const u8 *addr); -+ -+/* Init */ -+struct mt7601u_dev *mt7601u_alloc_device(struct device *dev); -+int mt7601u_init_hardware(struct mt7601u_dev *dev); -+int mt7601u_register_device(struct mt7601u_dev *dev); -+void mt7601u_cleanup(struct mt7601u_dev *dev); -+ -+int mt7601u_mac_start(struct mt7601u_dev *dev); -+void mt7601u_mac_stop(struct mt7601u_dev *dev); -+ -+/* PHY */ -+int mt7601u_phy_init(struct mt7601u_dev *dev); -+int mt7601u_wait_bbp_ready(struct mt7601u_dev *dev); -+void mt7601u_set_rx_path(struct mt7601u_dev *dev, u8 path); -+void mt7601u_set_tx_dac(struct mt7601u_dev *dev, u8 path); -+int mt7601u_bbp_set_bw(struct mt7601u_dev *dev, int bw); -+void mt7601u_agc_save(struct mt7601u_dev *dev); -+void mt7601u_agc_restore(struct mt7601u_dev *dev); -+int mt7601u_phy_set_channel(struct mt7601u_dev *dev, -+ struct cfg80211_chan_def *chandef); -+void mt7601u_phy_recalibrate_after_assoc(struct mt7601u_dev *dev); -+int mt7601u_phy_get_rssi(struct mt7601u_dev *dev, -+ struct mt7601u_rxwi *rxwi, u16 rate); -+void mt7601u_phy_con_cal_onoff(struct mt7601u_dev *dev, -+ struct ieee80211_bss_conf *info); -+ -+/* MAC */ -+void mt7601u_mac_work(struct work_struct *work); -+void mt7601u_mac_set_protection(struct mt7601u_dev *dev, bool legacy_prot, -+ int ht_mode); -+void mt7601u_mac_set_short_preamble(struct mt7601u_dev *dev, bool short_preamb); -+void mt7601u_mac_config_tsf(struct mt7601u_dev *dev, bool enable, int interval); -+void -+mt7601u_mac_wcid_setup(struct mt7601u_dev *dev, u8 idx, u8 vif_idx, u8 *mac); -+void mt7601u_mac_set_ampdu_factor(struct mt7601u_dev *dev); -+ -+/* TX */ -+void mt7601u_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control, -+ struct sk_buff *skb); -+int mt7601u_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, -+ u16 queue, const struct ieee80211_tx_queue_params *params); -+void mt7601u_tx_status(struct mt7601u_dev *dev, struct sk_buff *skb); -+void mt7601u_tx_stat(struct work_struct *work); -+ -+/* util */ -+void mt76_remove_hdr_pad(struct sk_buff *skb); -+int mt76_insert_hdr_pad(struct sk_buff *skb); -+ -+u32 mt7601u_bbp_set_ctrlch(struct mt7601u_dev *dev, bool below); -+ -+static inline u32 mt7601u_mac_set_ctrlch(struct mt7601u_dev *dev, bool below) -+{ -+ return mt7601u_rmc(dev, MT_TX_BAND_CFG, 1, below); -+} -+ -+int mt7601u_dma_init(struct mt7601u_dev *dev); -+void mt7601u_dma_cleanup(struct mt7601u_dev *dev); -+ -+int mt7601u_dma_enqueue_tx(struct mt7601u_dev *dev, struct sk_buff *skb, -+ struct mt76_wcid *wcid, int hw_q); -+ -+#endif -diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/phy.c linux-rpi/drivers/net/wireless/mediatek/mt7601u/phy.c ---- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/phy.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/phy.c 2015-11-29 09:42:38.887167260 +0100 -@@ -0,0 +1,1251 @@ -+/* -+ * (c) Copyright 2002-2010, Ralink Technology, Inc. -+ * Copyright (C) 2014 Felix Fietkau -+ * Copyright (C) 2015 Jakub Kicinski -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 -+ * as published by the Free Software Foundation -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include "mt7601u.h" -+#include "mcu.h" -+#include "eeprom.h" -+#include "trace.h" -+#include "initvals_phy.h" -+ -+#include -+ -+static void mt7601u_agc_reset(struct mt7601u_dev *dev); -+ -+static int -+mt7601u_rf_wr(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 value) -+{ -+ int ret = 0; -+ -+ if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state)) || -+ WARN_ON(offset > 63)) -+ return -EINVAL; -+ if (test_bit(MT7601U_STATE_REMOVED, &dev->state)) -+ return 0; -+ -+ mutex_lock(&dev->reg_atomic_mutex); -+ -+ if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100)) { -+ ret = -ETIMEDOUT; -+ goto out; -+ } -+ -+ mt7601u_wr(dev, MT_RF_CSR_CFG, MT76_SET(MT_RF_CSR_CFG_DATA, value) | -+ MT76_SET(MT_RF_CSR_CFG_REG_BANK, bank) | -+ MT76_SET(MT_RF_CSR_CFG_REG_ID, offset) | -+ MT_RF_CSR_CFG_WR | -+ MT_RF_CSR_CFG_KICK); -+ trace_rf_write(dev, bank, offset, value); -+out: -+ mutex_unlock(&dev->reg_atomic_mutex); -+ -+ if (ret < 0) -+ dev_err(dev->dev, "Error: RF write %02hhx:%02hhx failed:%d!!\n", -+ bank, offset, ret); -+ -+ return ret; -+} -+ -+static int -+mt7601u_rf_rr(struct mt7601u_dev *dev, u8 bank, u8 offset) -+{ -+ int ret = -ETIMEDOUT; -+ u32 val; -+ -+ if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state)) || -+ WARN_ON(offset > 63)) -+ return -EINVAL; -+ if (test_bit(MT7601U_STATE_REMOVED, &dev->state)) -+ return 0xff; -+ -+ mutex_lock(&dev->reg_atomic_mutex); -+ -+ if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100)) -+ goto out; -+ -+ mt7601u_wr(dev, MT_RF_CSR_CFG, MT76_SET(MT_RF_CSR_CFG_REG_BANK, bank) | -+ MT76_SET(MT_RF_CSR_CFG_REG_ID, offset) | -+ MT_RF_CSR_CFG_KICK); -+ -+ if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100)) -+ goto out; -+ -+ val = mt7601u_rr(dev, MT_RF_CSR_CFG); -+ if (MT76_GET(MT_RF_CSR_CFG_REG_ID, val) == offset && -+ MT76_GET(MT_RF_CSR_CFG_REG_BANK, val) == bank) { -+ ret = MT76_GET(MT_RF_CSR_CFG_DATA, val); -+ trace_rf_read(dev, bank, offset, ret); -+ } -+out: -+ mutex_unlock(&dev->reg_atomic_mutex); -+ -+ if (ret < 0) -+ dev_err(dev->dev, "Error: RF read %02hhx:%02hhx failed:%d!!\n", -+ bank, offset, ret); -+ -+ return ret; -+} -+ -+static int -+mt7601u_rf_rmw(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 mask, u8 val) -+{ -+ int ret; -+ -+ ret = mt7601u_rf_rr(dev, bank, offset); -+ if (ret < 0) -+ return ret; -+ val |= ret & ~mask; -+ ret = mt7601u_rf_wr(dev, bank, offset, val); -+ if (ret) -+ return ret; -+ -+ return val; -+} -+ -+static int -+mt7601u_rf_set(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 val) -+{ -+ return mt7601u_rf_rmw(dev, bank, offset, 0, val); -+} -+ -+static int -+mt7601u_rf_clear(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 mask) -+{ -+ return mt7601u_rf_rmw(dev, bank, offset, mask, 0); -+} -+ -+static void mt7601u_bbp_wr(struct mt7601u_dev *dev, u8 offset, u8 val) -+{ -+ if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state)) || -+ test_bit(MT7601U_STATE_REMOVED, &dev->state)) -+ return; -+ -+ mutex_lock(&dev->reg_atomic_mutex); -+ -+ if (!mt76_poll(dev, MT_BBP_CSR_CFG, MT_BBP_CSR_CFG_BUSY, 0, 1000)) { -+ dev_err(dev->dev, "Error: BBP write %02hhx failed!!\n", offset); -+ goto out; -+ } -+ -+ mt7601u_wr(dev, MT_BBP_CSR_CFG, -+ MT76_SET(MT_BBP_CSR_CFG_VAL, val) | -+ MT76_SET(MT_BBP_CSR_CFG_REG_NUM, offset) | -+ MT_BBP_CSR_CFG_RW_MODE | MT_BBP_CSR_CFG_BUSY); -+ trace_bbp_write(dev, offset, val); -+out: -+ mutex_unlock(&dev->reg_atomic_mutex); -+} -+ -+static int mt7601u_bbp_rr(struct mt7601u_dev *dev, u8 offset) -+{ -+ u32 val; -+ int ret = -ETIMEDOUT; -+ -+ if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state))) -+ return -EINVAL; -+ if (test_bit(MT7601U_STATE_REMOVED, &dev->state)) -+ return 0xff; -+ -+ mutex_lock(&dev->reg_atomic_mutex); -+ -+ if (!mt76_poll(dev, MT_BBP_CSR_CFG, MT_BBP_CSR_CFG_BUSY, 0, 1000)) -+ goto out; -+ -+ mt7601u_wr(dev, MT_BBP_CSR_CFG, -+ MT76_SET(MT_BBP_CSR_CFG_REG_NUM, offset) | -+ MT_BBP_CSR_CFG_RW_MODE | MT_BBP_CSR_CFG_BUSY | -+ MT_BBP_CSR_CFG_READ); -+ -+ if (!mt76_poll(dev, MT_BBP_CSR_CFG, MT_BBP_CSR_CFG_BUSY, 0, 1000)) -+ goto out; -+ -+ val = mt7601u_rr(dev, MT_BBP_CSR_CFG); -+ if (MT76_GET(MT_BBP_CSR_CFG_REG_NUM, val) == offset) { -+ ret = MT76_GET(MT_BBP_CSR_CFG_VAL, val); -+ trace_bbp_read(dev, offset, ret); -+ } -+out: -+ mutex_unlock(&dev->reg_atomic_mutex); -+ -+ if (ret < 0) -+ dev_err(dev->dev, "Error: BBP read %02hhx failed:%d!!\n", -+ offset, ret); -+ -+ return ret; -+} -+ -+static int mt7601u_bbp_rmw(struct mt7601u_dev *dev, u8 offset, u8 mask, u8 val) -+{ -+ int ret; -+ -+ ret = mt7601u_bbp_rr(dev, offset); -+ if (ret < 0) -+ return ret; -+ val |= ret & ~mask; -+ mt7601u_bbp_wr(dev, offset, val); -+ -+ return val; -+} -+ -+static u8 mt7601u_bbp_rmc(struct mt7601u_dev *dev, u8 offset, u8 mask, u8 val) -+{ -+ int ret; -+ -+ ret = mt7601u_bbp_rr(dev, offset); -+ if (ret < 0) -+ return ret; -+ val |= ret & ~mask; -+ if (ret != val) -+ mt7601u_bbp_wr(dev, offset, val); -+ -+ return val; -+} -+ -+int mt7601u_wait_bbp_ready(struct mt7601u_dev *dev) -+{ -+ int i = 20; -+ u8 val; -+ -+ do { -+ val = mt7601u_bbp_rr(dev, MT_BBP_REG_VERSION); -+ if (val && ~val) -+ break; -+ } while (--i); -+ -+ if (!i) { -+ dev_err(dev->dev, "Error: BBP is not ready\n"); -+ return -EIO; -+ } -+ -+ return 0; -+} -+ -+u32 mt7601u_bbp_set_ctrlch(struct mt7601u_dev *dev, bool below) -+{ -+ return mt7601u_bbp_rmc(dev, 3, 0x20, below ? 0x20 : 0); -+} -+ -+int mt7601u_phy_get_rssi(struct mt7601u_dev *dev, -+ struct mt7601u_rxwi *rxwi, u16 rate) -+{ -+ static const s8 lna[2][2][3] = { -+ /* main LNA */ { -+ /* bw20 */ { -2, 15, 33 }, -+ /* bw40 */ { 0, 16, 34 } -+ }, -+ /* aux LNA */ { -+ /* bw20 */ { -2, 15, 33 }, -+ /* bw40 */ { -2, 16, 34 } -+ } -+ }; -+ int bw = MT76_GET(MT_RXWI_RATE_BW, rate); -+ int aux_lna = MT76_GET(MT_RXWI_ANT_AUX_LNA, rxwi->ant); -+ int lna_id = MT76_GET(MT_RXWI_GAIN_RSSI_LNA_ID, rxwi->gain); -+ int val; -+ -+ if (lna_id) /* LNA id can be 0, 2, 3. */ -+ lna_id--; -+ -+ val = 8; -+ val -= lna[aux_lna][bw][lna_id]; -+ val -= MT76_GET(MT_RXWI_GAIN_RSSI_VAL, rxwi->gain); -+ val -= dev->ee->lna_gain; -+ val -= dev->ee->rssi_offset[0]; -+ -+ return val; -+} -+ -+static void mt7601u_vco_cal(struct mt7601u_dev *dev) -+{ -+ mt7601u_rf_wr(dev, 0, 4, 0x0a); -+ mt7601u_rf_wr(dev, 0, 5, 0x20); -+ mt7601u_rf_set(dev, 0, 4, BIT(7)); -+ msleep(2); -+} -+ -+static int mt7601u_set_bw_filter(struct mt7601u_dev *dev, bool cal) -+{ -+ u32 filter = 0; -+ int ret; -+ -+ if (!cal) -+ filter |= 0x10000; -+ if (dev->bw != MT_BW_20) -+ filter |= 0x00100; -+ -+ /* TX */ -+ ret = mt7601u_mcu_calibrate(dev, MCU_CAL_BW, filter | 1); -+ if (ret) -+ return ret; -+ /* RX */ -+ return mt7601u_mcu_calibrate(dev, MCU_CAL_BW, filter); -+} -+ -+static int mt7601u_load_bbp_temp_table_bw(struct mt7601u_dev *dev) -+{ -+ const struct reg_table *t; -+ -+ if (WARN_ON(dev->temp_mode > MT_TEMP_MODE_LOW)) -+ return -EINVAL; -+ -+ t = &bbp_mode_table[dev->temp_mode][dev->bw]; -+ -+ return mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, t->regs, t->n); -+} -+ -+static int mt7601u_bbp_temp(struct mt7601u_dev *dev, int mode, const char *name) -+{ -+ const struct reg_table *t; -+ int ret; -+ -+ if (dev->temp_mode == mode) -+ return 0; -+ -+ dev->temp_mode = mode; -+ trace_temp_mode(dev, mode); -+ -+ t = bbp_mode_table[dev->temp_mode]; -+ ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, -+ t[2].regs, t[2].n); -+ if (ret) -+ return ret; -+ -+ return mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, -+ t[dev->bw].regs, t[dev->bw].n); -+} -+ -+static void mt7601u_apply_ch14_fixup(struct mt7601u_dev *dev, int hw_chan) -+{ -+ struct mt7601u_rate_power *t = &dev->ee->power_rate_table; -+ -+ if (hw_chan != 14 || dev->bw != MT_BW_20) { -+ mt7601u_bbp_rmw(dev, 4, 0x20, 0); -+ mt7601u_bbp_wr(dev, 178, 0xff); -+ -+ t->cck[0].bw20 = dev->ee->real_cck_bw20[0]; -+ t->cck[1].bw20 = dev->ee->real_cck_bw20[1]; -+ } else { /* Apply CH14 OBW fixup */ -+ mt7601u_bbp_wr(dev, 4, 0x60); -+ mt7601u_bbp_wr(dev, 178, 0); -+ -+ /* Note: vendor code is buggy here for negative values */ -+ t->cck[0].bw20 = dev->ee->real_cck_bw20[0] - 2; -+ t->cck[1].bw20 = dev->ee->real_cck_bw20[1] - 2; -+ } -+} -+ -+static int __mt7601u_phy_set_channel(struct mt7601u_dev *dev, -+ struct cfg80211_chan_def *chandef) -+{ -+#define FREQ_PLAN_REGS 4 -+ static const u8 freq_plan[14][FREQ_PLAN_REGS] = { -+ { 0x99, 0x99, 0x09, 0x50 }, -+ { 0x46, 0x44, 0x0a, 0x50 }, -+ { 0xec, 0xee, 0x0a, 0x50 }, -+ { 0x99, 0x99, 0x0b, 0x50 }, -+ { 0x46, 0x44, 0x08, 0x51 }, -+ { 0xec, 0xee, 0x08, 0x51 }, -+ { 0x99, 0x99, 0x09, 0x51 }, -+ { 0x46, 0x44, 0x0a, 0x51 }, -+ { 0xec, 0xee, 0x0a, 0x51 }, -+ { 0x99, 0x99, 0x0b, 0x51 }, -+ { 0x46, 0x44, 0x08, 0x52 }, -+ { 0xec, 0xee, 0x08, 0x52 }, -+ { 0x99, 0x99, 0x09, 0x52 }, -+ { 0x33, 0x33, 0x0b, 0x52 }, -+ }; -+ struct mt76_reg_pair channel_freq_plan[FREQ_PLAN_REGS] = { -+ { 17, 0 }, { 18, 0 }, { 19, 0 }, { 20, 0 }, -+ }; -+ struct mt76_reg_pair bbp_settings[3] = { -+ { 62, 0x37 - dev->ee->lna_gain }, -+ { 63, 0x37 - dev->ee->lna_gain }, -+ { 64, 0x37 - dev->ee->lna_gain }, -+ }; -+ -+ struct ieee80211_channel *chan = chandef->chan; -+ enum nl80211_channel_type chan_type = -+ cfg80211_get_chandef_type(chandef); -+ struct mt7601u_rate_power *t = &dev->ee->power_rate_table; -+ int chan_idx; -+ bool chan_ext_below; -+ u8 bw; -+ int i, ret; -+ -+ bw = MT_BW_20; -+ chan_ext_below = (chan_type == NL80211_CHAN_HT40MINUS); -+ chan_idx = chan->hw_value - 1; -+ -+ if (chandef->width == NL80211_CHAN_WIDTH_40) { -+ bw = MT_BW_40; -+ -+ if (chan_idx > 1 && chan_type == NL80211_CHAN_HT40MINUS) -+ chan_idx -= 2; -+ else if (chan_idx < 12 && chan_type == NL80211_CHAN_HT40PLUS) -+ chan_idx += 2; -+ else -+ dev_err(dev->dev, "Error: invalid 40MHz channel!!\n"); -+ } -+ -+ if (bw != dev->bw || chan_ext_below != dev->chan_ext_below) { -+ dev_dbg(dev->dev, "Info: switching HT mode bw:%d below:%d\n", -+ bw, chan_ext_below); -+ -+ mt7601u_bbp_set_bw(dev, bw); -+ -+ mt7601u_bbp_set_ctrlch(dev, chan_ext_below); -+ mt7601u_mac_set_ctrlch(dev, chan_ext_below); -+ dev->chan_ext_below = chan_ext_below; -+ } -+ -+ for (i = 0; i < FREQ_PLAN_REGS; i++) -+ channel_freq_plan[i].value = freq_plan[chan_idx][i]; -+ -+ ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_RF, -+ channel_freq_plan, FREQ_PLAN_REGS); -+ if (ret) -+ return ret; -+ -+ mt7601u_rmw(dev, MT_TX_ALC_CFG_0, 0x3f3f, -+ dev->ee->chan_pwr[chan_idx] & 0x3f); -+ -+ ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, -+ bbp_settings, ARRAY_SIZE(bbp_settings)); -+ if (ret) -+ return ret; -+ -+ mt7601u_vco_cal(dev); -+ mt7601u_bbp_set_bw(dev, bw); -+ ret = mt7601u_set_bw_filter(dev, false); -+ if (ret) -+ return ret; -+ -+ mt7601u_apply_ch14_fixup(dev, chan->hw_value); -+ mt7601u_wr(dev, MT_TX_PWR_CFG_0, int_to_s6(t->ofdm[1].bw20) << 24 | -+ int_to_s6(t->ofdm[0].bw20) << 16 | -+ int_to_s6(t->cck[1].bw20) << 8 | -+ int_to_s6(t->cck[0].bw20)); -+ -+ if (test_bit(MT7601U_STATE_SCANNING, &dev->state)) -+ mt7601u_agc_reset(dev); -+ -+ dev->chandef = *chandef; -+ -+ return 0; -+} -+ -+int mt7601u_phy_set_channel(struct mt7601u_dev *dev, -+ struct cfg80211_chan_def *chandef) -+{ -+ int ret; -+ -+ cancel_delayed_work_sync(&dev->cal_work); -+ cancel_delayed_work_sync(&dev->freq_cal.work); -+ -+ mutex_lock(&dev->hw_atomic_mutex); -+ ret = __mt7601u_phy_set_channel(dev, chandef); -+ mutex_unlock(&dev->hw_atomic_mutex); -+ if (ret) -+ return ret; -+ -+ if (test_bit(MT7601U_STATE_SCANNING, &dev->state)) -+ return 0; -+ -+ ieee80211_queue_delayed_work(dev->hw, &dev->cal_work, -+ MT_CALIBRATE_INTERVAL); -+ if (dev->freq_cal.enabled) -+ ieee80211_queue_delayed_work(dev->hw, &dev->freq_cal.work, -+ MT_FREQ_CAL_INIT_DELAY); -+ return 0; -+} -+ -+#define BBP_R47_FLAG GENMASK(2, 0) -+#define BBP_R47_F_TSSI 0 -+#define BBP_R47_F_PKT_T 1 -+#define BBP_R47_F_TX_RATE 2 -+#define BBP_R47_F_TEMP 4 -+/** -+ * mt7601u_bbp_r47_get - read value through BBP R47/R49 pair -+ * @dev: pointer to adapter structure -+ * @reg: value of BBP R47 before the operation -+ * @flag: one of the BBP_R47_F_* flags -+ * -+ * Convenience helper for reading values through BBP R47/R49 pair. -+ * Takes old value of BBP R47 as @reg, because callers usually have it -+ * cached already. -+ * -+ * Return: value of BBP R49. -+ */ -+static u8 mt7601u_bbp_r47_get(struct mt7601u_dev *dev, u8 reg, u8 flag) -+{ -+ flag |= reg & ~BBP_R47_FLAG; -+ mt7601u_bbp_wr(dev, 47, flag); -+ usleep_range(500, 700); -+ return mt7601u_bbp_rr(dev, 49); -+} -+ -+static s8 mt7601u_read_bootup_temp(struct mt7601u_dev *dev) -+{ -+ u8 bbp_val, temp; -+ u32 rf_bp, rf_set; -+ int i; -+ -+ rf_set = mt7601u_rr(dev, MT_RF_SETTING_0); -+ rf_bp = mt7601u_rr(dev, MT_RF_BYPASS_0); -+ -+ mt7601u_wr(dev, MT_RF_BYPASS_0, 0); -+ mt7601u_wr(dev, MT_RF_SETTING_0, 0x00000010); -+ mt7601u_wr(dev, MT_RF_BYPASS_0, 0x00000010); -+ -+ bbp_val = mt7601u_bbp_rmw(dev, 47, 0, 0x10); -+ -+ mt7601u_bbp_wr(dev, 22, 0x40); -+ -+ for (i = 100; i && (bbp_val & 0x10); i--) -+ bbp_val = mt7601u_bbp_rr(dev, 47); -+ -+ temp = mt7601u_bbp_r47_get(dev, bbp_val, BBP_R47_F_TEMP); -+ -+ mt7601u_bbp_wr(dev, 22, 0); -+ -+ bbp_val = mt7601u_bbp_rr(dev, 21); -+ bbp_val |= 0x02; -+ mt7601u_bbp_wr(dev, 21, bbp_val); -+ bbp_val &= ~0x02; -+ mt7601u_bbp_wr(dev, 21, bbp_val); -+ -+ mt7601u_wr(dev, MT_RF_BYPASS_0, 0); -+ mt7601u_wr(dev, MT_RF_SETTING_0, rf_set); -+ mt7601u_wr(dev, MT_RF_BYPASS_0, rf_bp); -+ -+ trace_read_temp(dev, temp); -+ return temp; -+} -+ -+static s8 mt7601u_read_temp(struct mt7601u_dev *dev) -+{ -+ int i; -+ u8 val; -+ s8 temp; -+ -+ val = mt7601u_bbp_rmw(dev, 47, 0x7f, 0x10); -+ -+ /* Note: this rarely succeeds, temp can change even if it fails. */ -+ for (i = 100; i && (val & 0x10); i--) -+ val = mt7601u_bbp_rr(dev, 47); -+ -+ temp = mt7601u_bbp_r47_get(dev, val, BBP_R47_F_TEMP); -+ -+ trace_read_temp(dev, temp); -+ return temp; -+} -+ -+static void mt7601u_rxdc_cal(struct mt7601u_dev *dev) -+{ -+ static const struct mt76_reg_pair intro[] = { -+ { 158, 0x8d }, { 159, 0xfc }, -+ { 158, 0x8c }, { 159, 0x4c }, -+ }, outro[] = { -+ { 158, 0x8d }, { 159, 0xe0 }, -+ }; -+ u32 mac_ctrl; -+ int i, ret; -+ -+ mac_ctrl = mt7601u_rr(dev, MT_MAC_SYS_CTRL); -+ mt7601u_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX); -+ -+ ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, -+ intro, ARRAY_SIZE(intro)); -+ if (ret) -+ dev_err(dev->dev, "%s intro failed:%d\n", __func__, ret); -+ -+ for (i = 20; i; i--) { -+ usleep_range(300, 500); -+ -+ mt7601u_bbp_wr(dev, 158, 0x8c); -+ if (mt7601u_bbp_rr(dev, 159) == 0x0c) -+ break; -+ } -+ if (!i) -+ dev_err(dev->dev, "%s timed out\n", __func__); -+ -+ mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0); -+ -+ ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, -+ outro, ARRAY_SIZE(outro)); -+ if (ret) -+ dev_err(dev->dev, "%s outro failed:%d\n", __func__, ret); -+ -+ mt7601u_wr(dev, MT_MAC_SYS_CTRL, mac_ctrl); -+} -+ -+void mt7601u_phy_recalibrate_after_assoc(struct mt7601u_dev *dev) -+{ -+ mt7601u_mcu_calibrate(dev, MCU_CAL_DPD, dev->curr_temp); -+ -+ mt7601u_rxdc_cal(dev); -+} -+ -+/* Note: function copied from vendor driver */ -+static s16 lin2dBd(u16 linear) -+{ -+ short exp = 0; -+ unsigned int mantisa; -+ int app, dBd; -+ -+ if (WARN_ON(!linear)) -+ return -10000; -+ -+ mantisa = linear; -+ -+ exp = fls(mantisa) - 16; -+ if (exp > 0) -+ mantisa >>= exp; -+ else -+ mantisa <<= abs(exp); -+ -+ if (mantisa <= 0xb800) -+ app = (mantisa + (mantisa >> 3) + (mantisa >> 4) - 0x9600); -+ else -+ app = (mantisa - (mantisa >> 3) - (mantisa >> 6) - 0x5a00); -+ if (app < 0) -+ app = 0; -+ -+ dBd = ((15 + exp) << 15) + app; -+ dBd = (dBd << 2) + (dBd << 1) + (dBd >> 6) + (dBd >> 7); -+ dBd = (dBd >> 10); -+ -+ return dBd; -+} -+ -+static void -+mt7601u_set_initial_tssi(struct mt7601u_dev *dev, s16 tssi_db, s16 tssi_hvga_db) -+{ -+ struct tssi_data *d = &dev->ee->tssi_data; -+ int init_offset; -+ -+ init_offset = -((tssi_db * d->slope + d->offset[1]) / 4096) + 10; -+ -+ mt76_rmw(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP, -+ int_to_s6(init_offset) & MT_TX_ALC_CFG_1_TEMP_COMP); -+} -+ -+static void mt7601u_tssi_dc_gain_cal(struct mt7601u_dev *dev) -+{ -+ u8 rf_vga, rf_mixer, bbp_r47; -+ int i, j; -+ s8 res[4]; -+ s16 tssi_init_db, tssi_init_hvga_db; -+ -+ mt7601u_wr(dev, MT_RF_SETTING_0, 0x00000030); -+ mt7601u_wr(dev, MT_RF_BYPASS_0, 0x000c0030); -+ mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0); -+ -+ mt7601u_bbp_wr(dev, 58, 0); -+ mt7601u_bbp_wr(dev, 241, 0x2); -+ mt7601u_bbp_wr(dev, 23, 0x8); -+ bbp_r47 = mt7601u_bbp_rr(dev, 47); -+ -+ /* Set VGA gain */ -+ rf_vga = mt7601u_rf_rr(dev, 5, 3); -+ mt7601u_rf_wr(dev, 5, 3, 8); -+ -+ /* Mixer disable */ -+ rf_mixer = mt7601u_rf_rr(dev, 4, 39); -+ mt7601u_rf_wr(dev, 4, 39, 0); -+ -+ for (i = 0; i < 4; i++) { -+ mt7601u_rf_wr(dev, 4, 39, (i & 1) ? rf_mixer : 0); -+ -+ mt7601u_bbp_wr(dev, 23, (i < 2) ? 0x08 : 0x02); -+ mt7601u_rf_wr(dev, 5, 3, (i < 2) ? 0x08 : 0x11); -+ -+ /* BBP TSSI initial and soft reset */ -+ mt7601u_bbp_wr(dev, 22, 0); -+ mt7601u_bbp_wr(dev, 244, 0); -+ -+ mt7601u_bbp_wr(dev, 21, 1); -+ udelay(1); -+ mt7601u_bbp_wr(dev, 21, 0); -+ -+ /* TSSI measurement */ -+ mt7601u_bbp_wr(dev, 47, 0x50); -+ mt7601u_bbp_wr(dev, (i & 1) ? 244 : 22, (i & 1) ? 0x31 : 0x40); -+ -+ for (j = 20; j; j--) -+ if (!(mt7601u_bbp_rr(dev, 47) & 0x10)) -+ break; -+ if (!j) -+ dev_err(dev->dev, "%s timed out\n", __func__); -+ -+ /* TSSI read */ -+ mt7601u_bbp_wr(dev, 47, 0x40); -+ res[i] = mt7601u_bbp_rr(dev, 49); -+ } -+ -+ tssi_init_db = lin2dBd((short)res[1] - res[0]); -+ tssi_init_hvga_db = lin2dBd(((short)res[3] - res[2]) * 4); -+ dev->tssi_init = res[0]; -+ dev->tssi_init_hvga = res[2]; -+ dev->tssi_init_hvga_offset_db = tssi_init_hvga_db - tssi_init_db; -+ -+ dev_dbg(dev->dev, -+ "TSSI_init:%hhx db:%hx hvga:%hhx hvga_db:%hx off_db:%hx\n", -+ dev->tssi_init, tssi_init_db, dev->tssi_init_hvga, -+ tssi_init_hvga_db, dev->tssi_init_hvga_offset_db); -+ -+ mt7601u_bbp_wr(dev, 22, 0); -+ mt7601u_bbp_wr(dev, 244, 0); -+ -+ mt7601u_bbp_wr(dev, 21, 1); -+ udelay(1); -+ mt7601u_bbp_wr(dev, 21, 0); -+ -+ mt7601u_wr(dev, MT_RF_BYPASS_0, 0); -+ mt7601u_wr(dev, MT_RF_SETTING_0, 0); -+ -+ mt7601u_rf_wr(dev, 5, 3, rf_vga); -+ mt7601u_rf_wr(dev, 4, 39, rf_mixer); -+ mt7601u_bbp_wr(dev, 47, bbp_r47); -+ -+ mt7601u_set_initial_tssi(dev, tssi_init_db, tssi_init_hvga_db); -+} -+ -+static int mt7601u_temp_comp(struct mt7601u_dev *dev, bool on) -+{ -+ int ret, temp, hi_temp = 400, lo_temp = -200; -+ -+ temp = (dev->raw_temp - dev->ee->ref_temp) * MT_EE_TEMPERATURE_SLOPE; -+ dev->curr_temp = temp; -+ -+ /* DPD Calibration */ -+ if (temp - dev->dpd_temp > 450 || temp - dev->dpd_temp < -450) { -+ dev->dpd_temp = temp; -+ -+ ret = mt7601u_mcu_calibrate(dev, MCU_CAL_DPD, dev->dpd_temp); -+ if (ret) -+ return ret; -+ -+ mt7601u_vco_cal(dev); -+ -+ dev_dbg(dev->dev, "Recalibrate DPD\n"); -+ } -+ -+ /* PLL Lock Protect */ -+ if (temp < -50 && !dev->pll_lock_protect) { /* < 20C */ -+ dev->pll_lock_protect = true; -+ -+ mt7601u_rf_wr(dev, 4, 4, 6); -+ mt7601u_rf_clear(dev, 4, 10, 0x30); -+ -+ dev_dbg(dev->dev, "PLL lock protect on - too cold\n"); -+ } else if (temp > 50 && dev->pll_lock_protect) { /* > 30C */ -+ dev->pll_lock_protect = false; -+ -+ mt7601u_rf_wr(dev, 4, 4, 0); -+ mt7601u_rf_rmw(dev, 4, 10, 0x30, 0x10); -+ -+ dev_dbg(dev->dev, "PLL lock protect off\n"); -+ } -+ -+ if (on) { -+ hi_temp -= 50; -+ lo_temp -= 50; -+ } -+ -+ /* BBP CR for H, L, N temperature */ -+ if (temp > hi_temp) -+ return mt7601u_bbp_temp(dev, MT_TEMP_MODE_HIGH, "high"); -+ else if (temp > lo_temp) -+ return mt7601u_bbp_temp(dev, MT_TEMP_MODE_NORMAL, "normal"); -+ else -+ return mt7601u_bbp_temp(dev, MT_TEMP_MODE_LOW, "low"); -+} -+ -+/* Note: this is used only with TSSI, we can just use trgt_pwr from eeprom. */ -+static int mt7601u_current_tx_power(struct mt7601u_dev *dev) -+{ -+ return dev->ee->chan_pwr[dev->chandef.chan->hw_value - 1]; -+} -+ -+static bool mt7601u_use_hvga(struct mt7601u_dev *dev) -+{ -+ return !(mt7601u_current_tx_power(dev) > 20); -+} -+ -+static s16 -+mt7601u_phy_rf_pa_mode_val(struct mt7601u_dev *dev, int phy_mode, int tx_rate) -+{ -+ static const s16 decode_tb[] = { 0, 8847, -5734, -5734 }; -+ u32 reg; -+ -+ switch (phy_mode) { -+ case MT_PHY_TYPE_OFDM: -+ tx_rate += 4; -+ case MT_PHY_TYPE_CCK: -+ reg = dev->rf_pa_mode[0]; -+ break; -+ default: -+ reg = dev->rf_pa_mode[1]; -+ break; -+ } -+ -+ return decode_tb[(reg >> (tx_rate * 2)) & 0x3]; -+} -+ -+static struct mt7601u_tssi_params -+mt7601u_tssi_params_get(struct mt7601u_dev *dev) -+{ -+ static const u8 ofdm_pkt2rate[8] = { 6, 4, 2, 0, 7, 5, 3, 1 }; -+ static const int static_power[4] = { 0, -49152, -98304, 49152 }; -+ struct mt7601u_tssi_params p; -+ u8 bbp_r47, pkt_type, tx_rate; -+ struct power_per_rate *rate_table; -+ -+ bbp_r47 = mt7601u_bbp_rr(dev, 47); -+ -+ p.tssi0 = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_TSSI); -+ dev->raw_temp = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_TEMP); -+ pkt_type = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_PKT_T); -+ -+ p.trgt_power = mt7601u_current_tx_power(dev); -+ -+ switch (pkt_type & 0x03) { -+ case MT_PHY_TYPE_CCK: -+ tx_rate = (pkt_type >> 4) & 0x03; -+ rate_table = dev->ee->power_rate_table.cck; -+ break; -+ -+ case MT_PHY_TYPE_OFDM: -+ tx_rate = ofdm_pkt2rate[(pkt_type >> 4) & 0x07]; -+ rate_table = dev->ee->power_rate_table.ofdm; -+ break; -+ -+ default: -+ tx_rate = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_TX_RATE); -+ tx_rate &= 0x7f; -+ rate_table = dev->ee->power_rate_table.ht; -+ break; -+ } -+ -+ if (dev->bw == MT_BW_20) -+ p.trgt_power += rate_table[tx_rate / 2].bw20; -+ else -+ p.trgt_power += rate_table[tx_rate / 2].bw40; -+ -+ p.trgt_power <<= 12; -+ -+ dev_dbg(dev->dev, "tx_rate:%02hhx pwr:%08x\n", tx_rate, p.trgt_power); -+ -+ p.trgt_power += mt7601u_phy_rf_pa_mode_val(dev, pkt_type & 0x03, -+ tx_rate); -+ -+ /* Channel 14, cck, bw20 */ -+ if ((pkt_type & 0x03) == MT_PHY_TYPE_CCK) { -+ if (mt7601u_bbp_rr(dev, 4) & 0x20) -+ p.trgt_power += mt7601u_bbp_rr(dev, 178) ? 18022 : 9830; -+ else -+ p.trgt_power += mt7601u_bbp_rr(dev, 178) ? 819 : 24576; -+ } -+ -+ p.trgt_power += static_power[mt7601u_bbp_rr(dev, 1) & 0x03]; -+ -+ p.trgt_power += dev->ee->tssi_data.tx0_delta_offset; -+ -+ dev_dbg(dev->dev, -+ "tssi:%02hhx t_power:%08x temp:%02hhx pkt_type:%02hhx\n", -+ p.tssi0, p.trgt_power, dev->raw_temp, pkt_type); -+ -+ return p; -+} -+ -+static bool mt7601u_tssi_read_ready(struct mt7601u_dev *dev) -+{ -+ return !(mt7601u_bbp_rr(dev, 47) & 0x10); -+} -+ -+static int mt7601u_tssi_cal(struct mt7601u_dev *dev) -+{ -+ struct mt7601u_tssi_params params; -+ int curr_pwr, diff_pwr; -+ char tssi_offset; -+ s8 tssi_init; -+ s16 tssi_m_dc, tssi_db; -+ bool hvga; -+ u32 val; -+ -+ if (!dev->ee->tssi_enabled) -+ return 0; -+ -+ hvga = mt7601u_use_hvga(dev); -+ if (!dev->tssi_read_trig) -+ return mt7601u_mcu_tssi_read_kick(dev, hvga); -+ -+ if (!mt7601u_tssi_read_ready(dev)) -+ return 0; -+ -+ params = mt7601u_tssi_params_get(dev); -+ -+ tssi_init = (hvga ? dev->tssi_init_hvga : dev->tssi_init); -+ tssi_m_dc = params.tssi0 - tssi_init; -+ tssi_db = lin2dBd(tssi_m_dc); -+ dev_dbg(dev->dev, "tssi dc:%04hx db:%04hx hvga:%d\n", -+ tssi_m_dc, tssi_db, hvga); -+ -+ if (dev->chandef.chan->hw_value < 5) -+ tssi_offset = dev->ee->tssi_data.offset[0]; -+ else if (dev->chandef.chan->hw_value < 9) -+ tssi_offset = dev->ee->tssi_data.offset[1]; -+ else -+ tssi_offset = dev->ee->tssi_data.offset[2]; -+ -+ if (hvga) -+ tssi_db -= dev->tssi_init_hvga_offset_db; -+ -+ curr_pwr = tssi_db * dev->ee->tssi_data.slope + (tssi_offset << 9); -+ diff_pwr = params.trgt_power - curr_pwr; -+ dev_dbg(dev->dev, "Power curr:%08x diff:%08x\n", curr_pwr, diff_pwr); -+ -+ if (params.tssi0 > 126 && diff_pwr > 0) { -+ dev_err(dev->dev, "Error: TSSI upper saturation\n"); -+ diff_pwr = 0; -+ } -+ if (params.tssi0 - tssi_init < 1 && diff_pwr < 0) { -+ dev_err(dev->dev, "Error: TSSI lower saturation\n"); -+ diff_pwr = 0; -+ } -+ -+ if ((dev->prev_pwr_diff ^ diff_pwr) < 0 && abs(diff_pwr) < 4096 && -+ (abs(diff_pwr) > abs(dev->prev_pwr_diff) || -+ (diff_pwr > 0 && diff_pwr == -dev->prev_pwr_diff))) -+ diff_pwr = 0; -+ else -+ dev->prev_pwr_diff = diff_pwr; -+ -+ diff_pwr += (diff_pwr > 0) ? 2048 : -2048; -+ diff_pwr /= 4096; -+ -+ dev_dbg(dev->dev, "final diff: %08x\n", diff_pwr); -+ -+ val = mt7601u_rr(dev, MT_TX_ALC_CFG_1); -+ curr_pwr = s6_to_int(MT76_GET(MT_TX_ALC_CFG_1_TEMP_COMP, val)); -+ diff_pwr += curr_pwr; -+ val = (val & ~MT_TX_ALC_CFG_1_TEMP_COMP) | int_to_s6(diff_pwr); -+ mt7601u_wr(dev, MT_TX_ALC_CFG_1, val); -+ -+ return mt7601u_mcu_tssi_read_kick(dev, hvga); -+} -+ -+static u8 mt7601u_agc_default(struct mt7601u_dev *dev) -+{ -+ return (dev->ee->lna_gain - 8) * 2 + 0x34; -+} -+ -+static void mt7601u_agc_reset(struct mt7601u_dev *dev) -+{ -+ u8 agc = mt7601u_agc_default(dev); -+ -+ mt7601u_bbp_wr(dev, 66, agc); -+} -+ -+void mt7601u_agc_save(struct mt7601u_dev *dev) -+{ -+ dev->agc_save = mt7601u_bbp_rr(dev, 66); -+} -+ -+void mt7601u_agc_restore(struct mt7601u_dev *dev) -+{ -+ mt7601u_bbp_wr(dev, 66, dev->agc_save); -+} -+ -+static void mt7601u_agc_tune(struct mt7601u_dev *dev) -+{ -+ u8 val = mt7601u_agc_default(dev); -+ -+ if (test_bit(MT7601U_STATE_SCANNING, &dev->state)) -+ return; -+ -+ /* Note: only in STA mode and not dozing; perhaps do this only if -+ * there is enough rssi updates since last run? -+ * Rssi updates are only on beacons and U2M so should work... -+ */ -+ spin_lock_bh(&dev->con_mon_lock); -+ if (dev->avg_rssi <= -70) -+ val -= 0x20; -+ else if (dev->avg_rssi <= -60) -+ val -= 0x10; -+ spin_unlock_bh(&dev->con_mon_lock); -+ -+ if (val != mt7601u_bbp_rr(dev, 66)) -+ mt7601u_bbp_wr(dev, 66, val); -+ -+ /* TODO: also if lost a lot of beacons try resetting -+ * (see RTMPSetAGCInitValue() call in mlme.c). -+ */ -+} -+ -+static void mt7601u_phy_calibrate(struct work_struct *work) -+{ -+ struct mt7601u_dev *dev = container_of(work, struct mt7601u_dev, -+ cal_work.work); -+ -+ mt7601u_agc_tune(dev); -+ mt7601u_tssi_cal(dev); -+ /* If TSSI calibration was run it already updated temperature. */ -+ if (!dev->ee->tssi_enabled) -+ dev->raw_temp = mt7601u_read_temp(dev); -+ mt7601u_temp_comp(dev, true); /* TODO: find right value for @on */ -+ -+ ieee80211_queue_delayed_work(dev->hw, &dev->cal_work, -+ MT_CALIBRATE_INTERVAL); -+} -+ -+static unsigned long -+__mt7601u_phy_freq_cal(struct mt7601u_dev *dev, s8 last_offset, u8 phy_mode) -+{ -+ u8 activate_threshold, deactivate_threshold; -+ -+ trace_freq_cal_offset(dev, phy_mode, last_offset); -+ -+ /* No beacons received - reschedule soon */ -+ if (last_offset == MT_FREQ_OFFSET_INVALID) -+ return MT_FREQ_CAL_ADJ_INTERVAL; -+ -+ switch (phy_mode) { -+ case MT_PHY_TYPE_CCK: -+ activate_threshold = 19; -+ deactivate_threshold = 5; -+ break; -+ case MT_PHY_TYPE_OFDM: -+ activate_threshold = 102; -+ deactivate_threshold = 32; -+ break; -+ case MT_PHY_TYPE_HT: -+ case MT_PHY_TYPE_HT_GF: -+ activate_threshold = 82; -+ deactivate_threshold = 20; -+ break; -+ default: -+ WARN_ON(1); -+ return MT_FREQ_CAL_CHECK_INTERVAL; -+ } -+ -+ if (abs(last_offset) >= activate_threshold) -+ dev->freq_cal.adjusting = true; -+ else if (abs(last_offset) <= deactivate_threshold) -+ dev->freq_cal.adjusting = false; -+ -+ if (!dev->freq_cal.adjusting) -+ return MT_FREQ_CAL_CHECK_INTERVAL; -+ -+ if (last_offset > deactivate_threshold) { -+ if (dev->freq_cal.freq > 0) -+ dev->freq_cal.freq--; -+ else -+ dev->freq_cal.adjusting = false; -+ } else if (last_offset < -deactivate_threshold) { -+ if (dev->freq_cal.freq < 0xbf) -+ dev->freq_cal.freq++; -+ else -+ dev->freq_cal.adjusting = false; -+ } -+ -+ trace_freq_cal_adjust(dev, dev->freq_cal.freq); -+ mt7601u_rf_wr(dev, 0, 12, dev->freq_cal.freq); -+ mt7601u_vco_cal(dev); -+ -+ return dev->freq_cal.adjusting ? MT_FREQ_CAL_ADJ_INTERVAL : -+ MT_FREQ_CAL_CHECK_INTERVAL; -+} -+ -+static void mt7601u_phy_freq_cal(struct work_struct *work) -+{ -+ struct mt7601u_dev *dev = container_of(work, struct mt7601u_dev, -+ freq_cal.work.work); -+ s8 last_offset; -+ u8 phy_mode; -+ unsigned long delay; -+ -+ spin_lock_bh(&dev->con_mon_lock); -+ last_offset = dev->bcn_freq_off; -+ phy_mode = dev->bcn_phy_mode; -+ spin_unlock_bh(&dev->con_mon_lock); -+ -+ delay = __mt7601u_phy_freq_cal(dev, last_offset, phy_mode); -+ ieee80211_queue_delayed_work(dev->hw, &dev->freq_cal.work, delay); -+ -+ spin_lock_bh(&dev->con_mon_lock); -+ dev->bcn_freq_off = MT_FREQ_OFFSET_INVALID; -+ spin_unlock_bh(&dev->con_mon_lock); -+} -+ -+void mt7601u_phy_con_cal_onoff(struct mt7601u_dev *dev, -+ struct ieee80211_bss_conf *info) -+{ -+ if (!info->assoc) -+ cancel_delayed_work_sync(&dev->freq_cal.work); -+ -+ /* Start/stop collecting beacon data */ -+ spin_lock_bh(&dev->con_mon_lock); -+ ether_addr_copy(dev->ap_bssid, info->bssid); -+ dev->avg_rssi = 0; -+ dev->bcn_freq_off = MT_FREQ_OFFSET_INVALID; -+ spin_unlock_bh(&dev->con_mon_lock); -+ -+ dev->freq_cal.freq = dev->ee->rf_freq_off; -+ dev->freq_cal.enabled = info->assoc; -+ dev->freq_cal.adjusting = false; -+ -+ if (info->assoc) -+ ieee80211_queue_delayed_work(dev->hw, &dev->freq_cal.work, -+ MT_FREQ_CAL_INIT_DELAY); -+} -+ -+static int mt7601u_init_cal(struct mt7601u_dev *dev) -+{ -+ u32 mac_ctrl; -+ int ret; -+ -+ dev->raw_temp = mt7601u_read_bootup_temp(dev); -+ dev->curr_temp = (dev->raw_temp - dev->ee->ref_temp) * -+ MT_EE_TEMPERATURE_SLOPE; -+ dev->dpd_temp = dev->curr_temp; -+ -+ mac_ctrl = mt7601u_rr(dev, MT_MAC_SYS_CTRL); -+ -+ ret = mt7601u_mcu_calibrate(dev, MCU_CAL_R, 0); -+ if (ret) -+ return ret; -+ -+ ret = mt7601u_rf_rr(dev, 0, 4); -+ if (ret < 0) -+ return ret; -+ ret |= 0x80; -+ ret = mt7601u_rf_wr(dev, 0, 4, ret); -+ if (ret) -+ return ret; -+ msleep(2); -+ -+ ret = mt7601u_mcu_calibrate(dev, MCU_CAL_TXDCOC, 0); -+ if (ret) -+ return ret; -+ -+ mt7601u_rxdc_cal(dev); -+ -+ ret = mt7601u_set_bw_filter(dev, true); -+ if (ret) -+ return ret; -+ ret = mt7601u_mcu_calibrate(dev, MCU_CAL_LOFT, 0); -+ if (ret) -+ return ret; -+ ret = mt7601u_mcu_calibrate(dev, MCU_CAL_TXIQ, 0); -+ if (ret) -+ return ret; -+ ret = mt7601u_mcu_calibrate(dev, MCU_CAL_RXIQ, 0); -+ if (ret) -+ return ret; -+ ret = mt7601u_mcu_calibrate(dev, MCU_CAL_DPD, dev->dpd_temp); -+ if (ret) -+ return ret; -+ -+ mt7601u_rxdc_cal(dev); -+ -+ mt7601u_tssi_dc_gain_cal(dev); -+ -+ mt7601u_wr(dev, MT_MAC_SYS_CTRL, mac_ctrl); -+ -+ mt7601u_temp_comp(dev, true); -+ -+ return 0; -+} -+ -+int mt7601u_bbp_set_bw(struct mt7601u_dev *dev, int bw) -+{ -+ u32 val, old; -+ -+ if (bw == dev->bw) { -+ /* Vendor driver does the rmc even when no change is needed. */ -+ mt7601u_bbp_rmc(dev, 4, 0x18, bw == MT_BW_20 ? 0 : 0x10); -+ -+ return 0; -+ } -+ dev->bw = bw; -+ -+ /* Stop MAC for the time of bw change */ -+ old = mt7601u_rr(dev, MT_MAC_SYS_CTRL); -+ val = old & ~(MT_MAC_SYS_CTRL_ENABLE_TX | MT_MAC_SYS_CTRL_ENABLE_RX); -+ mt7601u_wr(dev, MT_MAC_SYS_CTRL, val); -+ mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_TX | MT_MAC_STATUS_RX, -+ 0, 500000); -+ -+ mt7601u_bbp_rmc(dev, 4, 0x18, bw == MT_BW_20 ? 0 : 0x10); -+ -+ mt7601u_wr(dev, MT_MAC_SYS_CTRL, old); -+ -+ return mt7601u_load_bbp_temp_table_bw(dev); -+} -+ -+/** -+ * mt7601u_set_rx_path - set rx path in BBP -+ * @dev: pointer to adapter structure -+ * @path: rx path to set values are 0-based -+ */ -+void mt7601u_set_rx_path(struct mt7601u_dev *dev, u8 path) -+{ -+ mt7601u_bbp_rmw(dev, 3, 0x18, path << 3); -+} -+ -+/** -+ * mt7601u_set_tx_dac - set which tx DAC to use -+ * @dev: pointer to adapter structure -+ * @path: DAC index, values are 0-based -+ */ -+void mt7601u_set_tx_dac(struct mt7601u_dev *dev, u8 dac) -+{ -+ mt7601u_bbp_rmc(dev, 1, 0x18, dac << 3); -+} -+ -+int mt7601u_phy_init(struct mt7601u_dev *dev) -+{ -+ int ret; -+ -+ dev->rf_pa_mode[0] = mt7601u_rr(dev, MT_RF_PA_MODE_CFG0); -+ dev->rf_pa_mode[1] = mt7601u_rr(dev, MT_RF_PA_MODE_CFG1); -+ -+ ret = mt7601u_rf_wr(dev, 0, 12, dev->ee->rf_freq_off); -+ if (ret) -+ return ret; -+ ret = mt7601u_write_reg_pairs(dev, 0, rf_central, -+ ARRAY_SIZE(rf_central)); -+ if (ret) -+ return ret; -+ ret = mt7601u_write_reg_pairs(dev, 0, rf_channel, -+ ARRAY_SIZE(rf_channel)); -+ if (ret) -+ return ret; -+ ret = mt7601u_write_reg_pairs(dev, 0, rf_vga, ARRAY_SIZE(rf_vga)); -+ if (ret) -+ return ret; -+ -+ ret = mt7601u_init_cal(dev); -+ if (ret) -+ return ret; -+ -+ dev->prev_pwr_diff = 100; -+ -+ INIT_DELAYED_WORK(&dev->cal_work, mt7601u_phy_calibrate); -+ INIT_DELAYED_WORK(&dev->freq_cal.work, mt7601u_phy_freq_cal); -+ -+ return 0; -+} -diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/regs.h linux-rpi/drivers/net/wireless/mediatek/mt7601u/regs.h ---- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/regs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/regs.h 2015-11-29 09:42:38.887167260 +0100 -@@ -0,0 +1,636 @@ -+/* -+ * Copyright (C) 2014 Felix Fietkau -+ * Copyright (C) 2015 Jakub Kicinski -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 -+ * as published by the Free Software Foundation -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#ifndef __MT76_REGS_H -+#define __MT76_REGS_H -+ -+#include -+ -+#ifndef GENMASK -+#define GENMASK(h, l) (((U32_C(1) << ((h) - (l) + 1)) - 1) << (l)) -+#endif -+ -+#define MT_ASIC_VERSION 0x0000 -+ -+#define MT76XX_REV_E3 0x22 -+#define MT76XX_REV_E4 0x33 -+ -+#define MT_CMB_CTRL 0x0020 -+#define MT_CMB_CTRL_XTAL_RDY BIT(22) -+#define MT_CMB_CTRL_PLL_LD BIT(23) -+ -+#define MT_EFUSE_CTRL 0x0024 -+#define MT_EFUSE_CTRL_AOUT GENMASK(5, 0) -+#define MT_EFUSE_CTRL_MODE GENMASK(7, 6) -+#define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8) -+#define MT_EFUSE_CTRL_LDO_ON_TIME GENMASK(15, 14) -+#define MT_EFUSE_CTRL_AIN GENMASK(25, 16) -+#define MT_EFUSE_CTRL_KICK BIT(30) -+#define MT_EFUSE_CTRL_SEL BIT(31) -+ -+#define MT_EFUSE_DATA_BASE 0x0028 -+#define MT_EFUSE_DATA(_n) (MT_EFUSE_DATA_BASE + ((_n) << 2)) -+ -+#define MT_COEXCFG0 0x0040 -+#define MT_COEXCFG0_COEX_EN BIT(0) -+ -+#define MT_WLAN_FUN_CTRL 0x0080 -+#define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0) -+#define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1) -+#define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2) -+ -+#define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3) /* MT76x0 */ -+#define MT_WLAN_FUN_CTRL_CSR_F20M_CKEN BIT(3) /* MT76x2 */ -+ -+#define MT_WLAN_FUN_CTRL_PCIE_CLK_REQ BIT(4) -+#define MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL BIT(5) -+#define MT_WLAN_FUN_CTRL_INV_ANT_SEL BIT(6) -+#define MT_WLAN_FUN_CTRL_WAKE_HOST BIT(7) -+ -+#define MT_WLAN_FUN_CTRL_THERM_RST BIT(8) /* MT76x2 */ -+#define MT_WLAN_FUN_CTRL_THERM_CKEN BIT(9) /* MT76x2 */ -+ -+#define MT_WLAN_FUN_CTRL_GPIO_IN GENMASK(15, 8) /* MT76x0 */ -+#define MT_WLAN_FUN_CTRL_GPIO_OUT GENMASK(23, 16) /* MT76x0 */ -+#define MT_WLAN_FUN_CTRL_GPIO_OUT_EN GENMASK(31, 24) /* MT76x0 */ -+ -+#define MT_XO_CTRL0 0x0100 -+#define MT_XO_CTRL1 0x0104 -+#define MT_XO_CTRL2 0x0108 -+#define MT_XO_CTRL3 0x010c -+#define MT_XO_CTRL4 0x0110 -+ -+#define MT_XO_CTRL5 0x0114 -+#define MT_XO_CTRL5_C2_VAL GENMASK(14, 8) -+ -+#define MT_XO_CTRL6 0x0118 -+#define MT_XO_CTRL6_C2_CTRL GENMASK(14, 8) -+ -+#define MT_XO_CTRL7 0x011c -+ -+#define MT_WLAN_MTC_CTRL 0x10148 -+#define MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP BIT(0) -+#define MT_WLAN_MTC_CTRL_PWR_ACK BIT(12) -+#define MT_WLAN_MTC_CTRL_PWR_ACK_S BIT(13) -+#define MT_WLAN_MTC_CTRL_BBP_MEM_PD GENMASK(19, 16) -+#define MT_WLAN_MTC_CTRL_PBF_MEM_PD BIT(20) -+#define MT_WLAN_MTC_CTRL_FCE_MEM_PD BIT(21) -+#define MT_WLAN_MTC_CTRL_TSO_MEM_PD BIT(22) -+#define MT_WLAN_MTC_CTRL_BBP_MEM_RB BIT(24) -+#define MT_WLAN_MTC_CTRL_PBF_MEM_RB BIT(25) -+#define MT_WLAN_MTC_CTRL_FCE_MEM_RB BIT(26) -+#define MT_WLAN_MTC_CTRL_TSO_MEM_RB BIT(27) -+#define MT_WLAN_MTC_CTRL_STATE_UP BIT(28) -+ -+#define MT_INT_SOURCE_CSR 0x0200 -+#define MT_INT_MASK_CSR 0x0204 -+ -+#define MT_INT_RX_DONE(_n) BIT(_n) -+#define MT_INT_RX_DONE_ALL GENMASK(1, 0) -+#define MT_INT_TX_DONE_ALL GENMASK(13, 4) -+#define MT_INT_TX_DONE(_n) BIT(_n + 4) -+#define MT_INT_RX_COHERENT BIT(16) -+#define MT_INT_TX_COHERENT BIT(17) -+#define MT_INT_ANY_COHERENT BIT(18) -+#define MT_INT_MCU_CMD BIT(19) -+#define MT_INT_TBTT BIT(20) -+#define MT_INT_PRE_TBTT BIT(21) -+#define MT_INT_TX_STAT BIT(22) -+#define MT_INT_AUTO_WAKEUP BIT(23) -+#define MT_INT_GPTIMER BIT(24) -+#define MT_INT_RXDELAYINT BIT(26) -+#define MT_INT_TXDELAYINT BIT(27) -+ -+#define MT_WPDMA_GLO_CFG 0x0208 -+#define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0) -+#define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1) -+#define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2) -+#define MT_WPDMA_GLO_CFG_RX_DMA_BUSY BIT(3) -+#define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4) -+#define MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE BIT(6) -+#define MT_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7) -+#define MT_WPDMA_GLO_CFG_HDR_SEG_LEN GENMASK(15, 8) -+#define MT_WPDMA_GLO_CFG_CLK_GATE_DIS BIT(30) -+#define MT_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31) -+ -+#define MT_WPDMA_RST_IDX 0x020c -+ -+#define MT_WPDMA_DELAY_INT_CFG 0x0210 -+ -+#define MT_WMM_AIFSN 0x0214 -+#define MT_WMM_AIFSN_MASK GENMASK(3, 0) -+#define MT_WMM_AIFSN_SHIFT(_n) ((_n) * 4) -+ -+#define MT_WMM_CWMIN 0x0218 -+#define MT_WMM_CWMIN_MASK GENMASK(3, 0) -+#define MT_WMM_CWMIN_SHIFT(_n) ((_n) * 4) -+ -+#define MT_WMM_CWMAX 0x021c -+#define MT_WMM_CWMAX_MASK GENMASK(3, 0) -+#define MT_WMM_CWMAX_SHIFT(_n) ((_n) * 4) -+ -+#define MT_WMM_TXOP_BASE 0x0220 -+#define MT_WMM_TXOP(_n) (MT_WMM_TXOP_BASE + (((_n) / 2) << 2)) -+#define MT_WMM_TXOP_SHIFT(_n) ((_n & 1) * 16) -+#define MT_WMM_TXOP_MASK GENMASK(15, 0) -+ -+#define MT_FCE_DMA_ADDR 0x0230 -+#define MT_FCE_DMA_LEN 0x0234 -+ -+#define MT_USB_DMA_CFG 0x238 -+#define MT_USB_DMA_CFG_RX_BULK_AGG_TOUT GENMASK(7, 0) -+#define MT_USB_DMA_CFG_RX_BULK_AGG_LMT GENMASK(15, 8) -+#define MT_USB_DMA_CFG_PHY_CLR BIT(16) -+#define MT_USB_DMA_CFG_TX_CLR BIT(19) -+#define MT_USB_DMA_CFG_TXOP_HALT BIT(20) -+#define MT_USB_DMA_CFG_RX_BULK_AGG_EN BIT(21) -+#define MT_USB_DMA_CFG_RX_BULK_EN BIT(22) -+#define MT_USB_DMA_CFG_TX_BULK_EN BIT(23) -+#define MT_USB_DMA_CFG_UDMA_RX_WL_DROP BIT(25) -+#define MT_USB_DMA_CFG_EP_OUT_VALID GENMASK(29, 27) -+#define MT_USB_DMA_CFG_RX_BUSY BIT(30) -+#define MT_USB_DMA_CFG_TX_BUSY BIT(31) -+ -+#define MT_TSO_CTRL 0x0250 -+#define MT_HEADER_TRANS_CTRL_REG 0x0260 -+ -+#define MT_US_CYC_CFG 0x02a4 -+#define MT_US_CYC_CNT GENMASK(7, 0) -+ -+#define MT_TX_RING_BASE 0x0300 -+#define MT_RX_RING_BASE 0x03c0 -+#define MT_RING_SIZE 0x10 -+ -+#define MT_TX_HW_QUEUE_MCU 8 -+#define MT_TX_HW_QUEUE_MGMT 9 -+ -+#define MT_PBF_SYS_CTRL 0x0400 -+#define MT_PBF_SYS_CTRL_MCU_RESET BIT(0) -+#define MT_PBF_SYS_CTRL_DMA_RESET BIT(1) -+#define MT_PBF_SYS_CTRL_MAC_RESET BIT(2) -+#define MT_PBF_SYS_CTRL_PBF_RESET BIT(3) -+#define MT_PBF_SYS_CTRL_ASY_RESET BIT(4) -+ -+#define MT_PBF_CFG 0x0404 -+#define MT_PBF_CFG_TX0Q_EN BIT(0) -+#define MT_PBF_CFG_TX1Q_EN BIT(1) -+#define MT_PBF_CFG_TX2Q_EN BIT(2) -+#define MT_PBF_CFG_TX3Q_EN BIT(3) -+#define MT_PBF_CFG_RX0Q_EN BIT(4) -+#define MT_PBF_CFG_RX_DROP_EN BIT(8) -+ -+#define MT_PBF_TX_MAX_PCNT 0x0408 -+#define MT_PBF_RX_MAX_PCNT 0x040c -+ -+#define MT_BCN_OFFSET_BASE 0x041c -+#define MT_BCN_OFFSET(_n) (MT_BCN_OFFSET_BASE + ((_n) << 2)) -+ -+#define MT_RF_CSR_CFG 0x0500 -+#define MT_RF_CSR_CFG_DATA GENMASK(7, 0) -+#define MT_RF_CSR_CFG_REG_ID GENMASK(13, 8) -+#define MT_RF_CSR_CFG_REG_BANK GENMASK(17, 14) -+#define MT_RF_CSR_CFG_WR BIT(30) -+#define MT_RF_CSR_CFG_KICK BIT(31) -+ -+#define MT_RF_BYPASS_0 0x0504 -+#define MT_RF_BYPASS_1 0x0508 -+#define MT_RF_SETTING_0 0x050c -+ -+#define MT_RF_DATA_WRITE 0x0524 -+ -+#define MT_RF_CTRL 0x0528 -+#define MT_RF_CTRL_ADDR GENMASK(11, 0) -+#define MT_RF_CTRL_WRITE BIT(12) -+#define MT_RF_CTRL_BUSY BIT(13) -+#define MT_RF_CTRL_IDX BIT(16) -+ -+#define MT_RF_DATA_READ 0x052c -+ -+#define MT_FCE_PSE_CTRL 0x0800 -+#define MT_FCE_PARAMETERS 0x0804 -+#define MT_FCE_CSO 0x0808 -+ -+#define MT_FCE_L2_STUFF 0x080c -+#define MT_FCE_L2_STUFF_HT_L2_EN BIT(0) -+#define MT_FCE_L2_STUFF_QOS_L2_EN BIT(1) -+#define MT_FCE_L2_STUFF_RX_STUFF_EN BIT(2) -+#define MT_FCE_L2_STUFF_TX_STUFF_EN BIT(3) -+#define MT_FCE_L2_STUFF_WR_MPDU_LEN_EN BIT(4) -+#define MT_FCE_L2_STUFF_MVINV_BSWAP BIT(5) -+#define MT_FCE_L2_STUFF_TS_CMD_QSEL_EN GENMASK(15, 8) -+#define MT_FCE_L2_STUFF_TS_LEN_EN GENMASK(23, 16) -+#define MT_FCE_L2_STUFF_OTHER_PORT GENMASK(25, 24) -+ -+#define MT_FCE_WLAN_FLOW_CONTROL1 0x0824 -+ -+#define MT_TX_CPU_FROM_FCE_BASE_PTR 0x09a0 -+#define MT_TX_CPU_FROM_FCE_MAX_COUNT 0x09a4 -+#define MT_TX_CPU_FROM_FCE_CPU_DESC_IDX 0x09a8 -+ -+#define MT_FCE_PDMA_GLOBAL_CONF 0x09c4 -+ -+#define MT_PAUSE_ENABLE_CONTROL1 0x0a38 -+ -+#define MT_FCE_SKIP_FS 0x0a6c -+ -+#define MT_MAC_CSR0 0x1000 -+ -+#define MT_MAC_SYS_CTRL 0x1004 -+#define MT_MAC_SYS_CTRL_RESET_CSR BIT(0) -+#define MT_MAC_SYS_CTRL_RESET_BBP BIT(1) -+#define MT_MAC_SYS_CTRL_ENABLE_TX BIT(2) -+#define MT_MAC_SYS_CTRL_ENABLE_RX BIT(3) -+ -+#define MT_MAC_ADDR_DW0 0x1008 -+#define MT_MAC_ADDR_DW1 0x100c -+#define MT_MAC_ADDR_DW1_U2ME_MASK GENMASK(23, 16) -+ -+#define MT_MAC_BSSID_DW0 0x1010 -+#define MT_MAC_BSSID_DW1 0x1014 -+#define MT_MAC_BSSID_DW1_ADDR GENMASK(15, 0) -+#define MT_MAC_BSSID_DW1_MBSS_MODE GENMASK(17, 16) -+#define MT_MAC_BSSID_DW1_MBEACON_N GENMASK(20, 18) -+#define MT_MAC_BSSID_DW1_MBSS_LOCAL_BIT BIT(21) -+#define MT_MAC_BSSID_DW1_MBSS_MODE_B2 BIT(22) -+#define MT_MAC_BSSID_DW1_MBEACON_N_B3 BIT(23) -+#define MT_MAC_BSSID_DW1_MBSS_IDX_BYTE GENMASK(26, 24) -+ -+#define MT_MAX_LEN_CFG 0x1018 -+#define MT_MAX_LEN_CFG_AMPDU GENMASK(13, 12) -+ -+#define MT_BBP_CSR_CFG 0x101c -+#define MT_BBP_CSR_CFG_VAL GENMASK(7, 0) -+#define MT_BBP_CSR_CFG_REG_NUM GENMASK(15, 8) -+#define MT_BBP_CSR_CFG_READ BIT(16) -+#define MT_BBP_CSR_CFG_BUSY BIT(17) -+#define MT_BBP_CSR_CFG_PAR_DUR BIT(18) -+#define MT_BBP_CSR_CFG_RW_MODE BIT(19) -+ -+#define MT_AMPDU_MAX_LEN_20M1S 0x1030 -+#define MT_AMPDU_MAX_LEN_20M2S 0x1034 -+#define MT_AMPDU_MAX_LEN_40M1S 0x1038 -+#define MT_AMPDU_MAX_LEN_40M2S 0x103c -+#define MT_AMPDU_MAX_LEN 0x1040 -+ -+#define MT_WCID_DROP_BASE 0x106c -+#define MT_WCID_DROP(_n) (MT_WCID_DROP_BASE + ((_n) >> 5) * 4) -+#define MT_WCID_DROP_MASK(_n) BIT((_n) % 32) -+ -+#define MT_BCN_BYPASS_MASK 0x108c -+ -+#define MT_MAC_APC_BSSID_BASE 0x1090 -+#define MT_MAC_APC_BSSID_L(_n) (MT_MAC_APC_BSSID_BASE + ((_n) * 8)) -+#define MT_MAC_APC_BSSID_H(_n) (MT_MAC_APC_BSSID_BASE + ((_n) * 8 + 4)) -+#define MT_MAC_APC_BSSID_H_ADDR GENMASK(15, 0) -+#define MT_MAC_APC_BSSID0_H_EN BIT(16) -+ -+#define MT_XIFS_TIME_CFG 0x1100 -+#define MT_XIFS_TIME_CFG_CCK_SIFS GENMASK(7, 0) -+#define MT_XIFS_TIME_CFG_OFDM_SIFS GENMASK(15, 8) -+#define MT_XIFS_TIME_CFG_OFDM_XIFS GENMASK(19, 16) -+#define MT_XIFS_TIME_CFG_EIFS GENMASK(28, 20) -+#define MT_XIFS_TIME_CFG_BB_RXEND_EN BIT(29) -+ -+#define MT_BKOFF_SLOT_CFG 0x1104 -+#define MT_BKOFF_SLOT_CFG_SLOTTIME GENMASK(7, 0) -+#define MT_BKOFF_SLOT_CFG_CC_DELAY GENMASK(11, 8) -+ -+#define MT_BEACON_TIME_CFG 0x1114 -+#define MT_BEACON_TIME_CFG_INTVAL GENMASK(15, 0) -+#define MT_BEACON_TIME_CFG_TIMER_EN BIT(16) -+#define MT_BEACON_TIME_CFG_SYNC_MODE GENMASK(18, 17) -+#define MT_BEACON_TIME_CFG_TBTT_EN BIT(19) -+#define MT_BEACON_TIME_CFG_BEACON_TX BIT(20) -+#define MT_BEACON_TIME_CFG_TSF_COMP GENMASK(31, 24) -+ -+#define MT_TBTT_SYNC_CFG 0x1118 -+#define MT_TBTT_TIMER_CFG 0x1124 -+ -+#define MT_INT_TIMER_CFG 0x1128 -+#define MT_INT_TIMER_CFG_PRE_TBTT GENMASK(15, 0) -+#define MT_INT_TIMER_CFG_GP_TIMER GENMASK(31, 16) -+ -+#define MT_INT_TIMER_EN 0x112c -+#define MT_INT_TIMER_EN_PRE_TBTT_EN BIT(0) -+#define MT_INT_TIMER_EN_GP_TIMER_EN BIT(1) -+ -+#define MT_MAC_STATUS 0x1200 -+#define MT_MAC_STATUS_TX BIT(0) -+#define MT_MAC_STATUS_RX BIT(1) -+ -+#define MT_PWR_PIN_CFG 0x1204 -+#define MT_AUX_CLK_CFG 0x120c -+ -+#define MT_BB_PA_MODE_CFG0 0x1214 -+#define MT_BB_PA_MODE_CFG1 0x1218 -+#define MT_RF_PA_MODE_CFG0 0x121c -+#define MT_RF_PA_MODE_CFG1 0x1220 -+ -+#define MT_RF_PA_MODE_ADJ0 0x1228 -+#define MT_RF_PA_MODE_ADJ1 0x122c -+ -+#define MT_DACCLK_EN_DLY_CFG 0x1264 -+ -+#define MT_EDCA_CFG_BASE 0x1300 -+#define MT_EDCA_CFG_AC(_n) (MT_EDCA_CFG_BASE + ((_n) << 2)) -+#define MT_EDCA_CFG_TXOP GENMASK(7, 0) -+#define MT_EDCA_CFG_AIFSN GENMASK(11, 8) -+#define MT_EDCA_CFG_CWMIN GENMASK(15, 12) -+#define MT_EDCA_CFG_CWMAX GENMASK(19, 16) -+ -+#define MT_TX_PWR_CFG_0 0x1314 -+#define MT_TX_PWR_CFG_1 0x1318 -+#define MT_TX_PWR_CFG_2 0x131c -+#define MT_TX_PWR_CFG_3 0x1320 -+#define MT_TX_PWR_CFG_4 0x1324 -+ -+#define MT_TX_BAND_CFG 0x132c -+#define MT_TX_BAND_CFG_UPPER_40M BIT(0) -+#define MT_TX_BAND_CFG_5G BIT(1) -+#define MT_TX_BAND_CFG_2G BIT(2) -+ -+#define MT_HT_FBK_TO_LEGACY 0x1384 -+#define MT_TX_MPDU_ADJ_INT 0x1388 -+ -+#define MT_TX_PWR_CFG_7 0x13d4 -+#define MT_TX_PWR_CFG_8 0x13d8 -+#define MT_TX_PWR_CFG_9 0x13dc -+ -+#define MT_TX_SW_CFG0 0x1330 -+#define MT_TX_SW_CFG1 0x1334 -+#define MT_TX_SW_CFG2 0x1338 -+ -+#define MT_TXOP_CTRL_CFG 0x1340 -+#define MT_TXOP_TRUN_EN GENMASK(5, 0) -+#define MT_TXOP_EXT_CCA_DLY GENMASK(15, 8) -+#define MT_TXOP_CTRL -+ -+#define MT_TX_RTS_CFG 0x1344 -+#define MT_TX_RTS_CFG_RETRY_LIMIT GENMASK(7, 0) -+#define MT_TX_RTS_CFG_THRESH GENMASK(23, 8) -+#define MT_TX_RTS_FALLBACK BIT(24) -+ -+#define MT_TX_TIMEOUT_CFG 0x1348 -+#define MT_TX_RETRY_CFG 0x134c -+#define MT_TX_LINK_CFG 0x1350 -+#define MT_HT_FBK_CFG0 0x1354 -+#define MT_HT_FBK_CFG1 0x1358 -+#define MT_LG_FBK_CFG0 0x135c -+#define MT_LG_FBK_CFG1 0x1360 -+ -+#define MT_CCK_PROT_CFG 0x1364 -+#define MT_OFDM_PROT_CFG 0x1368 -+#define MT_MM20_PROT_CFG 0x136c -+#define MT_MM40_PROT_CFG 0x1370 -+#define MT_GF20_PROT_CFG 0x1374 -+#define MT_GF40_PROT_CFG 0x1378 -+ -+#define MT_PROT_RATE GENMASK(15, 0) -+#define MT_PROT_CTRL_RTS_CTS BIT(16) -+#define MT_PROT_CTRL_CTS2SELF BIT(17) -+#define MT_PROT_NAV_SHORT BIT(18) -+#define MT_PROT_NAV_LONG BIT(19) -+#define MT_PROT_TXOP_ALLOW_CCK BIT(20) -+#define MT_PROT_TXOP_ALLOW_OFDM BIT(21) -+#define MT_PROT_TXOP_ALLOW_MM20 BIT(22) -+#define MT_PROT_TXOP_ALLOW_MM40 BIT(23) -+#define MT_PROT_TXOP_ALLOW_GF20 BIT(24) -+#define MT_PROT_TXOP_ALLOW_GF40 BIT(25) -+#define MT_PROT_RTS_THR_EN BIT(26) -+#define MT_PROT_RATE_CCK_11 0x0003 -+#define MT_PROT_RATE_OFDM_6 0x4000 -+#define MT_PROT_RATE_OFDM_24 0x4004 -+#define MT_PROT_RATE_DUP_OFDM_24 0x4084 -+#define MT_PROT_TXOP_ALLOW_ALL GENMASK(25, 20) -+#define MT_PROT_TXOP_ALLOW_BW20 (MT_PROT_TXOP_ALLOW_ALL & \ -+ ~MT_PROT_TXOP_ALLOW_MM40 & \ -+ ~MT_PROT_TXOP_ALLOW_GF40) -+ -+#define MT_EXP_ACK_TIME 0x1380 -+ -+#define MT_TX_PWR_CFG_0_EXT 0x1390 -+#define MT_TX_PWR_CFG_1_EXT 0x1394 -+ -+#define MT_TX_FBK_LIMIT 0x1398 -+#define MT_TX_FBK_LIMIT_MPDU_FBK GENMASK(7, 0) -+#define MT_TX_FBK_LIMIT_AMPDU_FBK GENMASK(15, 8) -+#define MT_TX_FBK_LIMIT_MPDU_UP_CLEAR BIT(16) -+#define MT_TX_FBK_LIMIT_AMPDU_UP_CLEAR BIT(17) -+#define MT_TX_FBK_LIMIT_RATE_LUT BIT(18) -+ -+#define MT_TX0_RF_GAIN_CORR 0x13a0 -+#define MT_TX1_RF_GAIN_CORR 0x13a4 -+#define MT_TX0_RF_GAIN_ATTEN 0x13a8 -+ -+#define MT_TX_ALC_CFG_0 0x13b0 -+#define MT_TX_ALC_CFG_0_CH_INIT_0 GENMASK(5, 0) -+#define MT_TX_ALC_CFG_0_CH_INIT_1 GENMASK(13, 8) -+#define MT_TX_ALC_CFG_0_LIMIT_0 GENMASK(21, 16) -+#define MT_TX_ALC_CFG_0_LIMIT_1 GENMASK(29, 24) -+ -+#define MT_TX_ALC_CFG_1 0x13b4 -+#define MT_TX_ALC_CFG_1_TEMP_COMP GENMASK(5, 0) -+ -+#define MT_TX_ALC_CFG_2 0x13a8 -+#define MT_TX_ALC_CFG_2_TEMP_COMP GENMASK(5, 0) -+ -+#define MT_TX0_BB_GAIN_ATTEN 0x13c0 -+ -+#define MT_TX_ALC_VGA3 0x13c8 -+ -+#define MT_TX_PROT_CFG6 0x13e0 -+#define MT_TX_PROT_CFG7 0x13e4 -+#define MT_TX_PROT_CFG8 0x13e8 -+ -+#define MT_PIFS_TX_CFG 0x13ec -+ -+#define MT_RX_FILTR_CFG 0x1400 -+ -+#define MT_RX_FILTR_CFG_CRC_ERR BIT(0) -+#define MT_RX_FILTR_CFG_PHY_ERR BIT(1) -+#define MT_RX_FILTR_CFG_PROMISC BIT(2) -+#define MT_RX_FILTR_CFG_OTHER_BSS BIT(3) -+#define MT_RX_FILTR_CFG_VER_ERR BIT(4) -+#define MT_RX_FILTR_CFG_MCAST BIT(5) -+#define MT_RX_FILTR_CFG_BCAST BIT(6) -+#define MT_RX_FILTR_CFG_DUP BIT(7) -+#define MT_RX_FILTR_CFG_CFACK BIT(8) -+#define MT_RX_FILTR_CFG_CFEND BIT(9) -+#define MT_RX_FILTR_CFG_ACK BIT(10) -+#define MT_RX_FILTR_CFG_CTS BIT(11) -+#define MT_RX_FILTR_CFG_RTS BIT(12) -+#define MT_RX_FILTR_CFG_PSPOLL BIT(13) -+#define MT_RX_FILTR_CFG_BA BIT(14) -+#define MT_RX_FILTR_CFG_BAR BIT(15) -+#define MT_RX_FILTR_CFG_CTRL_RSV BIT(16) -+ -+#define MT_AUTO_RSP_CFG 0x1404 -+ -+#define MT_AUTO_RSP_PREAMB_SHORT BIT(4) -+ -+#define MT_LEGACY_BASIC_RATE 0x1408 -+#define MT_HT_BASIC_RATE 0x140c -+ -+#define MT_RX_PARSER_CFG 0x1418 -+#define MT_RX_PARSER_RX_SET_NAV_ALL BIT(0) -+ -+#define MT_EXT_CCA_CFG 0x141c -+#define MT_EXT_CCA_CFG_CCA0 GENMASK(1, 0) -+#define MT_EXT_CCA_CFG_CCA1 GENMASK(3, 2) -+#define MT_EXT_CCA_CFG_CCA2 GENMASK(5, 4) -+#define MT_EXT_CCA_CFG_CCA3 GENMASK(7, 6) -+#define MT_EXT_CCA_CFG_CCA_MASK GENMASK(11, 8) -+#define MT_EXT_CCA_CFG_ED_CCA_MASK GENMASK(15, 12) -+ -+#define MT_TX_SW_CFG3 0x1478 -+ -+#define MT_PN_PAD_MODE 0x150c -+ -+#define MT_TXOP_HLDR_ET 0x1608 -+ -+#define MT_PROT_AUTO_TX_CFG 0x1648 -+ -+#define MT_RX_STA_CNT0 0x1700 -+#define MT_RX_STA_CNT1 0x1704 -+#define MT_RX_STA_CNT2 0x1708 -+#define MT_TX_STA_CNT0 0x170c -+#define MT_TX_STA_CNT1 0x1710 -+#define MT_TX_STA_CNT2 0x1714 -+ -+/* Vendor driver defines content of the second word of STAT_FIFO as follows: -+ * MT_TX_STAT_FIFO_RATE GENMASK(26, 16) -+ * MT_TX_STAT_FIFO_ETXBF BIT(27) -+ * MT_TX_STAT_FIFO_SND BIT(28) -+ * MT_TX_STAT_FIFO_ITXBF BIT(29) -+ * However, tests show that b16-31 have the same layout as TXWI rate_ctl -+ * with rate set to rate at which frame was acked. -+ */ -+#define MT_TX_STAT_FIFO 0x1718 -+#define MT_TX_STAT_FIFO_VALID BIT(0) -+#define MT_TX_STAT_FIFO_PID_TYPE GENMASK(4, 1) -+#define MT_TX_STAT_FIFO_SUCCESS BIT(5) -+#define MT_TX_STAT_FIFO_AGGR BIT(6) -+#define MT_TX_STAT_FIFO_ACKREQ BIT(7) -+#define MT_TX_STAT_FIFO_WCID GENMASK(15, 8) -+#define MT_TX_STAT_FIFO_RATE GENMASK(31, 16) -+ -+#define MT_TX_AGG_STAT 0x171c -+ -+#define MT_TX_AGG_CNT_BASE0 0x1720 -+ -+#define MT_MPDU_DENSITY_CNT 0x1740 -+ -+#define MT_TX_AGG_CNT_BASE1 0x174c -+ -+#define MT_TX_AGG_CNT(_id) ((_id) < 8 ? \ -+ MT_TX_AGG_CNT_BASE0 + ((_id) << 2) : \ -+ MT_TX_AGG_CNT_BASE1 + ((_id - 8) << 2)) -+ -+#define MT_TX_STAT_FIFO_EXT 0x1798 -+#define MT_TX_STAT_FIFO_EXT_RETRY GENMASK(7, 0) -+ -+#define MT_BBP_CORE_BASE 0x2000 -+#define MT_BBP_IBI_BASE 0x2100 -+#define MT_BBP_AGC_BASE 0x2300 -+#define MT_BBP_TXC_BASE 0x2400 -+#define MT_BBP_RXC_BASE 0x2500 -+#define MT_BBP_TXO_BASE 0x2600 -+#define MT_BBP_TXBE_BASE 0x2700 -+#define MT_BBP_RXFE_BASE 0x2800 -+#define MT_BBP_RXO_BASE 0x2900 -+#define MT_BBP_DFS_BASE 0x2a00 -+#define MT_BBP_TR_BASE 0x2b00 -+#define MT_BBP_CAL_BASE 0x2c00 -+#define MT_BBP_DSC_BASE 0x2e00 -+#define MT_BBP_PFMU_BASE 0x2f00 -+ -+#define MT_BBP(_type, _n) (MT_BBP_##_type##_BASE + ((_n) << 2)) -+ -+#define MT_BBP_CORE_R1_BW GENMASK(4, 3) -+ -+#define MT_BBP_AGC_R0_CTRL_CHAN GENMASK(9, 8) -+#define MT_BBP_AGC_R0_BW GENMASK(14, 12) -+ -+/* AGC, R4/R5 */ -+#define MT_BBP_AGC_LNA_GAIN GENMASK(21, 16) -+ -+/* AGC, R8/R9 */ -+#define MT_BBP_AGC_GAIN GENMASK(14, 8) -+ -+#define MT_BBP_AGC20_RSSI0 GENMASK(7, 0) -+#define MT_BBP_AGC20_RSSI1 GENMASK(15, 8) -+ -+#define MT_BBP_TXBE_R0_CTRL_CHAN GENMASK(1, 0) -+ -+#define MT_WCID_ADDR_BASE 0x1800 -+#define MT_WCID_ADDR(_n) (MT_WCID_ADDR_BASE + (_n) * 8) -+ -+#define MT_SRAM_BASE 0x4000 -+ -+#define MT_WCID_KEY_BASE 0x8000 -+#define MT_WCID_KEY(_n) (MT_WCID_KEY_BASE + (_n) * 32) -+ -+#define MT_WCID_IV_BASE 0xa000 -+#define MT_WCID_IV(_n) (MT_WCID_IV_BASE + (_n) * 8) -+ -+#define MT_WCID_ATTR_BASE 0xa800 -+#define MT_WCID_ATTR(_n) (MT_WCID_ATTR_BASE + (_n) * 4) -+ -+#define MT_WCID_ATTR_PAIRWISE BIT(0) -+#define MT_WCID_ATTR_PKEY_MODE GENMASK(3, 1) -+#define MT_WCID_ATTR_BSS_IDX GENMASK(6, 4) -+#define MT_WCID_ATTR_RXWI_UDF GENMASK(9, 7) -+#define MT_WCID_ATTR_PKEY_MODE_EXT BIT(10) -+#define MT_WCID_ATTR_BSS_IDX_EXT BIT(11) -+#define MT_WCID_ATTR_WAPI_MCBC BIT(15) -+#define MT_WCID_ATTR_WAPI_KEYID GENMASK(31, 24) -+ -+#define MT_SKEY_BASE_0 0xac00 -+#define MT_SKEY_BASE_1 0xb400 -+#define MT_SKEY_0(_bss, _idx) \ -+ (MT_SKEY_BASE_0 + (4 * (_bss) + _idx) * 32) -+#define MT_SKEY_1(_bss, _idx) \ -+ (MT_SKEY_BASE_1 + (4 * ((_bss) & 7) + _idx) * 32) -+#define MT_SKEY(_bss, _idx) \ -+ ((_bss & 8) ? MT_SKEY_1(_bss, _idx) : MT_SKEY_0(_bss, _idx)) -+ -+#define MT_SKEY_MODE_BASE_0 0xb000 -+#define MT_SKEY_MODE_BASE_1 0xb3f0 -+#define MT_SKEY_MODE_0(_bss) \ -+ (MT_SKEY_MODE_BASE_0 + ((_bss / 2) << 2)) -+#define MT_SKEY_MODE_1(_bss) \ -+ (MT_SKEY_MODE_BASE_1 + ((((_bss) & 7) / 2) << 2)) -+#define MT_SKEY_MODE(_bss) \ -+ ((_bss & 8) ? MT_SKEY_MODE_1(_bss) : MT_SKEY_MODE_0(_bss)) -+#define MT_SKEY_MODE_MASK GENMASK(3, 0) -+#define MT_SKEY_MODE_SHIFT(_bss, _idx) (4 * ((_idx) + 4 * (_bss & 1))) -+ -+#define MT_BEACON_BASE 0xc000 -+ -+#define MT_TEMP_SENSOR 0x1d000 -+#define MT_TEMP_SENSOR_VAL GENMASK(6, 0) -+ -+enum mt76_cipher_type { -+ MT_CIPHER_NONE, -+ MT_CIPHER_WEP40, -+ MT_CIPHER_WEP104, -+ MT_CIPHER_TKIP, -+ MT_CIPHER_AES_CCMP, -+ MT_CIPHER_CKIP40, -+ MT_CIPHER_CKIP104, -+ MT_CIPHER_CKIP128, -+ MT_CIPHER_WAPI, -+}; -+ -+#endif -diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/trace.c linux-rpi/drivers/net/wireless/mediatek/mt7601u/trace.c ---- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/trace.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/trace.c 2015-11-29 09:42:38.887167260 +0100 -@@ -0,0 +1,21 @@ -+/* -+ * Copyright (C) 2014 Felix Fietkau -+ * Copyright (C) 2015 Jakub Kicinski -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 -+ * as published by the Free Software Foundation -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include -+ -+#ifndef __CHECKER__ -+#define CREATE_TRACE_POINTS -+#include "trace.h" -+ -+#endif -diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/trace.h linux-rpi/drivers/net/wireless/mediatek/mt7601u/trace.h ---- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/trace.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/trace.h 2015-11-29 09:42:38.887167260 +0100 -@@ -0,0 +1,400 @@ -+/* -+ * Copyright (C) 2014 Felix Fietkau -+ * Copyright (C) 2015 Jakub Kicinski -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 -+ * as published by the Free Software Foundation -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#if !defined(__MT7601U_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) -+#define __MT7601U_TRACE_H -+ -+#include -+#include "mt7601u.h" -+#include "mac.h" -+ -+#undef TRACE_SYSTEM -+#define TRACE_SYSTEM mt7601u -+ -+#define MAXNAME 32 -+#define DEV_ENTRY __array(char, wiphy_name, 32) -+#define DEV_ASSIGN strlcpy(__entry->wiphy_name, \ -+ wiphy_name(dev->hw->wiphy), MAXNAME) -+#define DEV_PR_FMT "%s " -+#define DEV_PR_ARG __entry->wiphy_name -+ -+#define REG_ENTRY __field(u32, reg) __field(u32, val) -+#define REG_ASSIGN __entry->reg = reg; __entry->val = val -+#define REG_PR_FMT "%04x=%08x" -+#define REG_PR_ARG __entry->reg, __entry->val -+ -+DECLARE_EVENT_CLASS(dev_reg_evt, -+ TP_PROTO(struct mt7601u_dev *dev, u32 reg, u32 val), -+ TP_ARGS(dev, reg, val), -+ TP_STRUCT__entry( -+ DEV_ENTRY -+ REG_ENTRY -+ ), -+ TP_fast_assign( -+ DEV_ASSIGN; -+ REG_ASSIGN; -+ ), -+ TP_printk( -+ DEV_PR_FMT REG_PR_FMT, -+ DEV_PR_ARG, REG_PR_ARG -+ ) -+); -+ -+DEFINE_EVENT(dev_reg_evt, reg_read, -+ TP_PROTO(struct mt7601u_dev *dev, u32 reg, u32 val), -+ TP_ARGS(dev, reg, val) -+); -+ -+DEFINE_EVENT(dev_reg_evt, reg_write, -+ TP_PROTO(struct mt7601u_dev *dev, u32 reg, u32 val), -+ TP_ARGS(dev, reg, val) -+); -+ -+TRACE_EVENT(mt_submit_urb, -+ TP_PROTO(struct mt7601u_dev *dev, struct urb *u), -+ TP_ARGS(dev, u), -+ TP_STRUCT__entry( -+ DEV_ENTRY __field(unsigned, pipe) __field(u32, len) -+ ), -+ TP_fast_assign( -+ DEV_ASSIGN; -+ __entry->pipe = u->pipe; -+ __entry->len = u->transfer_buffer_length; -+ ), -+ TP_printk(DEV_PR_FMT "p:%08x len:%u", -+ DEV_PR_ARG, __entry->pipe, __entry->len) -+); -+ -+#define trace_mt_submit_urb_sync(__dev, __pipe, __len) ({ \ -+ struct urb u; \ -+ u.pipe = __pipe; \ -+ u.transfer_buffer_length = __len; \ -+ trace_mt_submit_urb(__dev, &u); \ -+}) -+ -+TRACE_EVENT(mt_mcu_msg_send, -+ TP_PROTO(struct mt7601u_dev *dev, -+ struct sk_buff *skb, u32 csum, bool resp), -+ TP_ARGS(dev, skb, csum, resp), -+ TP_STRUCT__entry( -+ DEV_ENTRY -+ __field(u32, info) -+ __field(u32, csum) -+ __field(bool, resp) -+ ), -+ TP_fast_assign( -+ DEV_ASSIGN; -+ __entry->info = *(u32 *)skb->data; -+ __entry->csum = csum; -+ __entry->resp = resp; -+ ), -+ TP_printk(DEV_PR_FMT "i:%08x c:%08x r:%d", -+ DEV_PR_ARG, __entry->info, __entry->csum, __entry->resp) -+); -+ -+TRACE_EVENT(mt_vend_req, -+ TP_PROTO(struct mt7601u_dev *dev, unsigned pipe, u8 req, u8 req_type, -+ u16 val, u16 offset, void *buf, size_t buflen, int ret), -+ TP_ARGS(dev, pipe, req, req_type, val, offset, buf, buflen, ret), -+ TP_STRUCT__entry( -+ DEV_ENTRY -+ __field(unsigned, pipe) __field(u8, req) __field(u8, req_type) -+ __field(u16, val) __field(u16, offset) __field(void*, buf) -+ __field(int, buflen) __field(int, ret) -+ ), -+ TP_fast_assign( -+ DEV_ASSIGN; -+ __entry->pipe = pipe; -+ __entry->req = req; -+ __entry->req_type = req_type; -+ __entry->val = val; -+ __entry->offset = offset; -+ __entry->buf = buf; -+ __entry->buflen = buflen; -+ __entry->ret = ret; -+ ), -+ TP_printk(DEV_PR_FMT -+ "%d p:%08x req:%02hhx %02hhx val:%04hx %04hx buf:%d %d", -+ DEV_PR_ARG, __entry->ret, __entry->pipe, __entry->req, -+ __entry->req_type, __entry->val, __entry->offset, -+ !!__entry->buf, __entry->buflen) -+); -+ -+TRACE_EVENT(ee_read, -+ TP_PROTO(struct mt7601u_dev *dev, int offset, u16 val), -+ TP_ARGS(dev, offset, val), -+ TP_STRUCT__entry( -+ DEV_ENTRY -+ __field(int, o) __field(u16, v) -+ ), -+ TP_fast_assign( -+ DEV_ASSIGN; -+ __entry->o = offset; -+ __entry->v = val; -+ ), -+ TP_printk(DEV_PR_FMT "%04x=%04x", DEV_PR_ARG, __entry->o, __entry->v) -+); -+ -+DECLARE_EVENT_CLASS(dev_rf_reg_evt, -+ TP_PROTO(struct mt7601u_dev *dev, u8 bank, u8 reg, u8 val), -+ TP_ARGS(dev, bank, reg, val), -+ TP_STRUCT__entry( -+ DEV_ENTRY -+ __field(u8, bank) -+ __field(u8, reg) -+ __field(u8, val) -+ ), -+ TP_fast_assign( -+ DEV_ASSIGN; -+ REG_ASSIGN; -+ __entry->bank = bank; -+ ), -+ TP_printk( -+ DEV_PR_FMT "%02hhx:%02hhx=%02hhx", -+ DEV_PR_ARG, __entry->bank, __entry->reg, __entry->val -+ ) -+); -+ -+DEFINE_EVENT(dev_rf_reg_evt, rf_read, -+ TP_PROTO(struct mt7601u_dev *dev, u8 bank, u8 reg, u8 val), -+ TP_ARGS(dev, bank, reg, val) -+); -+ -+DEFINE_EVENT(dev_rf_reg_evt, rf_write, -+ TP_PROTO(struct mt7601u_dev *dev, u8 bank, u8 reg, u8 val), -+ TP_ARGS(dev, bank, reg, val) -+); -+ -+DECLARE_EVENT_CLASS(dev_bbp_reg_evt, -+ TP_PROTO(struct mt7601u_dev *dev, u8 reg, u8 val), -+ TP_ARGS(dev, reg, val), -+ TP_STRUCT__entry( -+ DEV_ENTRY -+ __field(u8, reg) -+ __field(u8, val) -+ ), -+ TP_fast_assign( -+ DEV_ASSIGN; -+ REG_ASSIGN; -+ ), -+ TP_printk( -+ DEV_PR_FMT "%02hhx=%02hhx", -+ DEV_PR_ARG, __entry->reg, __entry->val -+ ) -+); -+ -+DEFINE_EVENT(dev_bbp_reg_evt, bbp_read, -+ TP_PROTO(struct mt7601u_dev *dev, u8 reg, u8 val), -+ TP_ARGS(dev, reg, val) -+); -+ -+DEFINE_EVENT(dev_bbp_reg_evt, bbp_write, -+ TP_PROTO(struct mt7601u_dev *dev, u8 reg, u8 val), -+ TP_ARGS(dev, reg, val) -+); -+ -+DECLARE_EVENT_CLASS(dev_simple_evt, -+ TP_PROTO(struct mt7601u_dev *dev, u8 val), -+ TP_ARGS(dev, val), -+ TP_STRUCT__entry( -+ DEV_ENTRY -+ __field(u8, val) -+ ), -+ TP_fast_assign( -+ DEV_ASSIGN; -+ __entry->val = val; -+ ), -+ TP_printk( -+ DEV_PR_FMT "%02hhx", DEV_PR_ARG, __entry->val -+ ) -+); -+ -+DEFINE_EVENT(dev_simple_evt, temp_mode, -+ TP_PROTO(struct mt7601u_dev *dev, u8 val), -+ TP_ARGS(dev, val) -+); -+ -+DEFINE_EVENT(dev_simple_evt, read_temp, -+ TP_PROTO(struct mt7601u_dev *dev, u8 val), -+ TP_ARGS(dev, val) -+); -+ -+DEFINE_EVENT(dev_simple_evt, freq_cal_adjust, -+ TP_PROTO(struct mt7601u_dev *dev, u8 val), -+ TP_ARGS(dev, val) -+); -+ -+TRACE_EVENT(freq_cal_offset, -+ TP_PROTO(struct mt7601u_dev *dev, u8 phy_mode, s8 freq_off), -+ TP_ARGS(dev, phy_mode, freq_off), -+ TP_STRUCT__entry( -+ DEV_ENTRY -+ __field(u8, phy_mode) -+ __field(s8, freq_off) -+ ), -+ TP_fast_assign( -+ DEV_ASSIGN; -+ __entry->phy_mode = phy_mode; -+ __entry->freq_off = freq_off; -+ ), -+ TP_printk(DEV_PR_FMT "phy:%02hhx off:%02hhx", -+ DEV_PR_ARG, __entry->phy_mode, __entry->freq_off) -+); -+ -+TRACE_EVENT(mt_rx, -+ TP_PROTO(struct mt7601u_dev *dev, struct mt7601u_rxwi *rxwi, u32 f), -+ TP_ARGS(dev, rxwi, f), -+ TP_STRUCT__entry( -+ DEV_ENTRY -+ __field_struct(struct mt7601u_rxwi, rxwi) -+ __field(u32, fce_info) -+ ), -+ TP_fast_assign( -+ DEV_ASSIGN; -+ __entry->rxwi = *rxwi; -+ __entry->fce_info = f; -+ ), -+ TP_printk(DEV_PR_FMT "rxi:%08x ctl:%08x frag_sn:%04hx rate:%04hx " -+ "uknw:%02hhx z:%02hhx%02hhx%02hhx snr:%02hhx " -+ "ant:%02hhx gain:%02hhx freq_o:%02hhx " -+ "r:%08x ea:%08x fce:%08x", DEV_PR_ARG, -+ le32_to_cpu(__entry->rxwi.rxinfo), -+ le32_to_cpu(__entry->rxwi.ctl), -+ le16_to_cpu(__entry->rxwi.frag_sn), -+ le16_to_cpu(__entry->rxwi.rate), -+ __entry->rxwi.unknown, -+ __entry->rxwi.zero[0], __entry->rxwi.zero[1], -+ __entry->rxwi.zero[2], -+ __entry->rxwi.snr, __entry->rxwi.ant, -+ __entry->rxwi.gain, __entry->rxwi.freq_off, -+ __entry->rxwi.resv2, __entry->rxwi.expert_ant, -+ __entry->fce_info) -+); -+ -+TRACE_EVENT(mt_tx, -+ TP_PROTO(struct mt7601u_dev *dev, struct sk_buff *skb, -+ struct mt76_sta *sta, struct mt76_txwi *h), -+ TP_ARGS(dev, skb, sta, h), -+ TP_STRUCT__entry( -+ DEV_ENTRY -+ __field_struct(struct mt76_txwi, h) -+ __field(struct sk_buff *, skb) -+ __field(struct mt76_sta *, sta) -+ ), -+ TP_fast_assign( -+ DEV_ASSIGN; -+ __entry->h = *h; -+ __entry->skb = skb; -+ __entry->sta = sta; -+ ), -+ TP_printk(DEV_PR_FMT "skb:%p sta:%p flg:%04hx rate_ctl:%04hx " -+ "ack:%02hhx wcid:%02hhx len_ctl:%05hx", DEV_PR_ARG, -+ __entry->skb, __entry->sta, -+ le16_to_cpu(__entry->h.flags), -+ le16_to_cpu(__entry->h.rate_ctl), -+ __entry->h.ack_ctl, __entry->h.wcid, -+ le16_to_cpu(__entry->h.len_ctl)) -+); -+ -+TRACE_EVENT(mt_tx_dma_done, -+ TP_PROTO(struct mt7601u_dev *dev, struct sk_buff *skb), -+ TP_ARGS(dev, skb), -+ TP_STRUCT__entry( -+ DEV_ENTRY -+ __field(struct sk_buff *, skb) -+ ), -+ TP_fast_assign( -+ DEV_ASSIGN; -+ __entry->skb = skb; -+ ), -+ TP_printk(DEV_PR_FMT "%p", DEV_PR_ARG, __entry->skb) -+); -+ -+TRACE_EVENT(mt_tx_status_cleaned, -+ TP_PROTO(struct mt7601u_dev *dev, int cleaned), -+ TP_ARGS(dev, cleaned), -+ TP_STRUCT__entry( -+ DEV_ENTRY -+ __field(int, cleaned) -+ ), -+ TP_fast_assign( -+ DEV_ASSIGN; -+ __entry->cleaned = cleaned; -+ ), -+ TP_printk(DEV_PR_FMT "%d", DEV_PR_ARG, __entry->cleaned) -+); -+ -+TRACE_EVENT(mt_tx_status, -+ TP_PROTO(struct mt7601u_dev *dev, u32 stat1, u32 stat2), -+ TP_ARGS(dev, stat1, stat2), -+ TP_STRUCT__entry( -+ DEV_ENTRY -+ __field(u32, stat1) __field(u32, stat2) -+ ), -+ TP_fast_assign( -+ DEV_ASSIGN; -+ __entry->stat1 = stat1; -+ __entry->stat2 = stat2; -+ ), -+ TP_printk(DEV_PR_FMT "%08x %08x", -+ DEV_PR_ARG, __entry->stat1, __entry->stat2) -+); -+ -+TRACE_EVENT(mt_rx_dma_aggr, -+ TP_PROTO(struct mt7601u_dev *dev, int cnt, bool paged), -+ TP_ARGS(dev, cnt, paged), -+ TP_STRUCT__entry( -+ DEV_ENTRY -+ __field(u8, cnt) -+ __field(bool, paged) -+ ), -+ TP_fast_assign( -+ DEV_ASSIGN; -+ __entry->cnt = cnt; -+ __entry->paged = paged; -+ ), -+ TP_printk(DEV_PR_FMT "cnt:%d paged:%d", -+ DEV_PR_ARG, __entry->cnt, __entry->paged) -+); -+ -+DEFINE_EVENT(dev_simple_evt, set_key, -+ TP_PROTO(struct mt7601u_dev *dev, u8 val), -+ TP_ARGS(dev, val) -+); -+ -+TRACE_EVENT(set_shared_key, -+ TP_PROTO(struct mt7601u_dev *dev, u8 vid, u8 key), -+ TP_ARGS(dev, vid, key), -+ TP_STRUCT__entry( -+ DEV_ENTRY -+ __field(u8, vid) -+ __field(u8, key) -+ ), -+ TP_fast_assign( -+ DEV_ASSIGN; -+ __entry->vid = vid; -+ __entry->key = key; -+ ), -+ TP_printk(DEV_PR_FMT "phy:%02hhx off:%02hhx", -+ DEV_PR_ARG, __entry->vid, __entry->key) -+); -+ -+#endif -+ -+#undef TRACE_INCLUDE_PATH -+#define TRACE_INCLUDE_PATH . -+#undef TRACE_INCLUDE_FILE -+#define TRACE_INCLUDE_FILE trace -+ -+#include -diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/tx.c linux-rpi/drivers/net/wireless/mediatek/mt7601u/tx.c ---- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/tx.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/tx.c 2015-11-29 09:42:38.887167260 +0100 -@@ -0,0 +1,322 @@ -+/* -+ * Copyright (C) 2014 Felix Fietkau -+ * Copyright (C) 2015 Jakub Kicinski -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 -+ * as published by the Free Software Foundation -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include "mt7601u.h" -+#include "trace.h" -+ -+enum mt76_txq_id { -+ MT_TXQ_VO = IEEE80211_AC_VO, -+ MT_TXQ_VI = IEEE80211_AC_VI, -+ MT_TXQ_BE = IEEE80211_AC_BE, -+ MT_TXQ_BK = IEEE80211_AC_BK, -+ MT_TXQ_PSD, -+ MT_TXQ_MCU, -+ __MT_TXQ_MAX -+}; -+ -+/* Hardware uses mirrored order of queues with Q0 having the highest priority */ -+static u8 q2hwq(u8 q) -+{ -+ return q ^ 0x3; -+} -+ -+/* Take mac80211 Q id from the skb and translate it to hardware Q id */ -+static u8 skb2q(struct sk_buff *skb) -+{ -+ int qid = skb_get_queue_mapping(skb); -+ -+ if (WARN_ON(qid >= MT_TXQ_PSD)) { -+ qid = MT_TXQ_BE; -+ skb_set_queue_mapping(skb, qid); -+ } -+ -+ return q2hwq(qid); -+} -+ -+/* Note: TX retry reporting is a bit broken. -+ * Retries are reported only once per AMPDU and often come a frame early -+ * i.e. they are reported in the last status preceding the AMPDU. Apart -+ * from the fact that it's hard to know the length of the AMPDU (which is -+ * required to know to how many consecutive frames retries should be -+ * applied), if status comes early on full FIFO it gets lost and retries -+ * of the whole AMPDU become invisible. -+ * As a work-around encode the desired rate in PKT_ID of TX descriptor -+ * and based on that guess the retries (every rate is tried once). -+ * Only downside here is that for MCS0 we have to rely solely on -+ * transmission failures as no retries can ever be reported. -+ * Not having to read EXT_FIFO has a nice effect of doubling the number -+ * of reports which can be fetched. -+ * Also the vendor driver never uses the EXT_FIFO register so it may be -+ * undertested. -+ */ -+static u8 mt7601u_tx_pktid_enc(struct mt7601u_dev *dev, u8 rate, bool is_probe) -+{ -+ u8 encoded = (rate + 1) + is_probe * 8; -+ -+ /* Because PKT_ID 0 disables status reporting only 15 values are -+ * available but 16 are needed (8 MCS * 2 for encoding is_probe) -+ * - we need to cram together two rates. MCS0 and MCS7 with is_probe -+ * share PKT_ID 9. -+ */ -+ if (is_probe && rate == 7) -+ return encoded - 7; -+ -+ return encoded; -+} -+ -+static void -+mt7601u_tx_pktid_dec(struct mt7601u_dev *dev, struct mt76_tx_status *stat) -+{ -+ u8 req_rate = stat->pktid; -+ u8 eff_rate = stat->rate & 0x7; -+ -+ req_rate -= 1; -+ -+ if (req_rate > 7) { -+ stat->is_probe = true; -+ req_rate -= 8; -+ -+ /* Decide between MCS0 and MCS7 which share pktid 9 */ -+ if (!req_rate && eff_rate) -+ req_rate = 7; -+ } -+ -+ stat->retry = req_rate - eff_rate; -+} -+ -+static void mt7601u_tx_skb_remove_dma_overhead(struct sk_buff *skb, -+ struct ieee80211_tx_info *info) -+{ -+ int pkt_len = (unsigned long)info->status.status_driver_data[0]; -+ -+ skb_pull(skb, sizeof(struct mt76_txwi) + 4); -+ if (ieee80211_get_hdrlen_from_skb(skb) % 4) -+ mt76_remove_hdr_pad(skb); -+ -+ skb_trim(skb, pkt_len); -+} -+ -+void mt7601u_tx_status(struct mt7601u_dev *dev, struct sk_buff *skb) -+{ -+ struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); -+ -+ mt7601u_tx_skb_remove_dma_overhead(skb, info); -+ -+ ieee80211_tx_info_clear_status(info); -+ info->status.rates[0].idx = -1; -+ info->flags |= IEEE80211_TX_STAT_ACK; -+ -+ spin_lock(&dev->mac_lock); -+ ieee80211_tx_status(dev->hw, skb); -+ spin_unlock(&dev->mac_lock); -+} -+ -+static int mt7601u_skb_rooms(struct mt7601u_dev *dev, struct sk_buff *skb) -+{ -+ int hdr_len = ieee80211_get_hdrlen_from_skb(skb); -+ u32 need_head; -+ -+ need_head = sizeof(struct mt76_txwi) + 4; -+ if (hdr_len % 4) -+ need_head += 2; -+ -+ return skb_cow(skb, need_head); -+} -+ -+static struct mt76_txwi * -+mt7601u_push_txwi(struct mt7601u_dev *dev, struct sk_buff *skb, -+ struct ieee80211_sta *sta, struct mt76_wcid *wcid, -+ int pkt_len) -+{ -+ struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); -+ struct ieee80211_tx_rate *rate = &info->control.rates[0]; -+ struct mt76_txwi *txwi; -+ unsigned long flags; -+ bool is_probe; -+ u32 pkt_id; -+ u16 rate_ctl; -+ u8 nss; -+ -+ txwi = (struct mt76_txwi *)skb_push(skb, sizeof(struct mt76_txwi)); -+ memset(txwi, 0, sizeof(*txwi)); -+ -+ if (!wcid->tx_rate_set) -+ ieee80211_get_tx_rates(info->control.vif, sta, skb, -+ info->control.rates, 1); -+ -+ spin_lock_irqsave(&dev->lock, flags); -+ if (rate->idx < 0 || !rate->count) -+ rate_ctl = wcid->tx_rate; -+ else -+ rate_ctl = mt76_mac_tx_rate_val(dev, rate, &nss); -+ spin_unlock_irqrestore(&dev->lock, flags); -+ txwi->rate_ctl = cpu_to_le16(rate_ctl); -+ -+ if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) -+ txwi->ack_ctl |= MT_TXWI_ACK_CTL_REQ; -+ if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) -+ txwi->ack_ctl |= MT_TXWI_ACK_CTL_NSEQ; -+ -+ if ((info->flags & IEEE80211_TX_CTL_AMPDU) && sta) { -+ u8 ba_size = IEEE80211_MIN_AMPDU_BUF; -+ -+ ba_size <<= sta->ht_cap.ampdu_factor; -+ ba_size = min_t(int, 63, ba_size); -+ if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) -+ ba_size = 0; -+ txwi->ack_ctl |= MT76_SET(MT_TXWI_ACK_CTL_BA_WINDOW, ba_size); -+ -+ txwi->flags = cpu_to_le16(MT_TXWI_FLAGS_AMPDU | -+ MT76_SET(MT_TXWI_FLAGS_MPDU_DENSITY, -+ sta->ht_cap.ampdu_density)); -+ if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) -+ txwi->flags = 0; -+ } -+ -+ txwi->wcid = wcid->idx; -+ -+ is_probe = !!(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE); -+ pkt_id = mt7601u_tx_pktid_enc(dev, rate_ctl & 0x7, is_probe); -+ pkt_len |= MT76_SET(MT_TXWI_LEN_PKTID, pkt_id); -+ txwi->len_ctl = cpu_to_le16(pkt_len); -+ -+ return txwi; -+} -+ -+void mt7601u_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control, -+ struct sk_buff *skb) -+{ -+ struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); -+ struct mt7601u_dev *dev = hw->priv; -+ struct ieee80211_vif *vif = info->control.vif; -+ struct ieee80211_sta *sta = control->sta; -+ struct mt76_sta *msta = NULL; -+ struct mt76_wcid *wcid = dev->mon_wcid; -+ struct mt76_txwi *txwi; -+ int pkt_len = skb->len; -+ int hw_q = skb2q(skb); -+ -+ BUILD_BUG_ON(ARRAY_SIZE(info->status.status_driver_data) < 1); -+ info->status.status_driver_data[0] = (void *)(unsigned long)pkt_len; -+ -+ if (mt7601u_skb_rooms(dev, skb) || mt76_insert_hdr_pad(skb)) { -+ ieee80211_free_txskb(dev->hw, skb); -+ return; -+ } -+ -+ if (sta) { -+ msta = (struct mt76_sta *) sta->drv_priv; -+ wcid = &msta->wcid; -+ } else if (vif) { -+ struct mt76_vif *mvif = (struct mt76_vif *)vif->drv_priv; -+ -+ wcid = &mvif->group_wcid; -+ } -+ -+ txwi = mt7601u_push_txwi(dev, skb, sta, wcid, pkt_len); -+ -+ if (mt7601u_dma_enqueue_tx(dev, skb, wcid, hw_q)) -+ return; -+ -+ trace_mt_tx(dev, skb, msta, txwi); -+} -+ -+void mt7601u_tx_stat(struct work_struct *work) -+{ -+ struct mt7601u_dev *dev = container_of(work, struct mt7601u_dev, -+ stat_work.work); -+ struct mt76_tx_status stat; -+ unsigned long flags; -+ int cleaned = 0; -+ -+ while (!test_bit(MT7601U_STATE_REMOVED, &dev->state)) { -+ stat = mt7601u_mac_fetch_tx_status(dev); -+ if (!stat.valid) -+ break; -+ -+ mt7601u_tx_pktid_dec(dev, &stat); -+ mt76_send_tx_status(dev, &stat); -+ -+ cleaned++; -+ } -+ trace_mt_tx_status_cleaned(dev, cleaned); -+ -+ spin_lock_irqsave(&dev->tx_lock, flags); -+ if (cleaned) -+ queue_delayed_work(dev->stat_wq, &dev->stat_work, -+ msecs_to_jiffies(10)); -+ else if (test_and_clear_bit(MT7601U_STATE_MORE_STATS, &dev->state)) -+ queue_delayed_work(dev->stat_wq, &dev->stat_work, -+ msecs_to_jiffies(20)); -+ else -+ clear_bit(MT7601U_STATE_READING_STATS, &dev->state); -+ spin_unlock_irqrestore(&dev->tx_lock, flags); -+} -+ -+int mt7601u_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, -+ u16 queue, const struct ieee80211_tx_queue_params *params) -+{ -+ struct mt7601u_dev *dev = hw->priv; -+ u8 cw_min = 5, cw_max = 10, hw_q = q2hwq(queue); -+ u32 val; -+ -+ /* TODO: should we do funny things with the parameters? -+ * See what mt7601u_set_default_edca() used to do in init.c. -+ */ -+ -+ if (params->cw_min) -+ cw_min = fls(params->cw_min); -+ if (params->cw_max) -+ cw_max = fls(params->cw_max); -+ -+ WARN_ON(params->txop > 0xff); -+ WARN_ON(params->aifs > 0xf); -+ WARN_ON(cw_min > 0xf); -+ WARN_ON(cw_max > 0xf); -+ -+ val = MT76_SET(MT_EDCA_CFG_AIFSN, params->aifs) | -+ MT76_SET(MT_EDCA_CFG_CWMIN, cw_min) | -+ MT76_SET(MT_EDCA_CFG_CWMAX, cw_max); -+ /* TODO: based on user-controlled EnableTxBurst var vendor drv sets -+ * a really long txop on AC0 (see connect.c:2009) but only on -+ * connect? When not connected should be 0. -+ */ -+ if (!hw_q) -+ val |= 0x60; -+ else -+ val |= MT76_SET(MT_EDCA_CFG_TXOP, params->txop); -+ mt76_wr(dev, MT_EDCA_CFG_AC(hw_q), val); -+ -+ val = mt76_rr(dev, MT_WMM_TXOP(hw_q)); -+ val &= ~(MT_WMM_TXOP_MASK << MT_WMM_TXOP_SHIFT(hw_q)); -+ val |= params->txop << MT_WMM_TXOP_SHIFT(hw_q); -+ mt76_wr(dev, MT_WMM_TXOP(hw_q), val); -+ -+ val = mt76_rr(dev, MT_WMM_AIFSN); -+ val &= ~(MT_WMM_AIFSN_MASK << MT_WMM_AIFSN_SHIFT(hw_q)); -+ val |= params->aifs << MT_WMM_AIFSN_SHIFT(hw_q); -+ mt76_wr(dev, MT_WMM_AIFSN, val); -+ -+ val = mt76_rr(dev, MT_WMM_CWMIN); -+ val &= ~(MT_WMM_CWMIN_MASK << MT_WMM_CWMIN_SHIFT(hw_q)); -+ val |= cw_min << MT_WMM_CWMIN_SHIFT(hw_q); -+ mt76_wr(dev, MT_WMM_CWMIN, val); -+ -+ val = mt76_rr(dev, MT_WMM_CWMAX); -+ val &= ~(MT_WMM_CWMAX_MASK << MT_WMM_CWMAX_SHIFT(hw_q)); -+ val |= cw_max << MT_WMM_CWMAX_SHIFT(hw_q); -+ mt76_wr(dev, MT_WMM_CWMAX, val); -+ -+ return 0; -+} -diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/usb.c linux-rpi/drivers/net/wireless/mediatek/mt7601u/usb.c ---- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/usb.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/usb.c 2015-11-29 09:42:38.887167260 +0100 -@@ -0,0 +1,362 @@ -+/* -+ * Copyright (C) 2015 Jakub Kicinski -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 -+ * as published by the Free Software Foundation -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include -+#include -+#include -+ -+#include "mt7601u.h" -+#include "usb.h" -+#include "trace.h" -+ -+static struct usb_device_id mt7601u_device_table[] = { -+ { USB_DEVICE(0x0b05, 0x17d3) }, -+ { USB_DEVICE(0x0e8d, 0x760a) }, -+ { USB_DEVICE(0x0e8d, 0x760b) }, -+ { USB_DEVICE(0x13d3, 0x3431) }, -+ { USB_DEVICE(0x13d3, 0x3434) }, -+ { USB_DEVICE(0x148f, 0x7601) }, -+ { USB_DEVICE(0x148f, 0x760a) }, -+ { USB_DEVICE(0x148f, 0x760b) }, -+ { USB_DEVICE(0x148f, 0x760c) }, -+ { USB_DEVICE(0x148f, 0x760d) }, -+ { USB_DEVICE(0x2001, 0x3d04) }, -+ { USB_DEVICE(0x2717, 0x4106) }, -+ { USB_DEVICE(0x2955, 0x0001) }, -+ { USB_DEVICE(0x2955, 0x1001) }, -+ { USB_DEVICE(0x2a5f, 0x1000) }, -+ { USB_DEVICE(0x7392, 0x7710) }, -+ { 0, } -+}; -+ -+bool mt7601u_usb_alloc_buf(struct mt7601u_dev *dev, size_t len, -+ struct mt7601u_dma_buf *buf) -+{ -+ struct usb_device *usb_dev = mt7601u_to_usb_dev(dev); -+ -+ buf->len = len; -+ buf->urb = usb_alloc_urb(0, GFP_KERNEL); -+ buf->buf = usb_alloc_coherent(usb_dev, buf->len, GFP_KERNEL, &buf->dma); -+ -+ return !buf->urb || !buf->buf; -+} -+ -+void mt7601u_usb_free_buf(struct mt7601u_dev *dev, struct mt7601u_dma_buf *buf) -+{ -+ struct usb_device *usb_dev = mt7601u_to_usb_dev(dev); -+ -+ usb_free_coherent(usb_dev, buf->len, buf->buf, buf->dma); -+ usb_free_urb(buf->urb); -+} -+ -+int mt7601u_usb_submit_buf(struct mt7601u_dev *dev, int dir, int ep_idx, -+ struct mt7601u_dma_buf *buf, gfp_t gfp, -+ usb_complete_t complete_fn, void *context) -+{ -+ struct usb_device *usb_dev = mt7601u_to_usb_dev(dev); -+ unsigned pipe; -+ int ret; -+ -+ if (dir == USB_DIR_IN) -+ pipe = usb_rcvbulkpipe(usb_dev, dev->in_eps[ep_idx]); -+ else -+ pipe = usb_sndbulkpipe(usb_dev, dev->out_eps[ep_idx]); -+ -+ usb_fill_bulk_urb(buf->urb, usb_dev, pipe, buf->buf, buf->len, -+ complete_fn, context); -+ buf->urb->transfer_dma = buf->dma; -+ buf->urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; -+ -+ trace_mt_submit_urb(dev, buf->urb); -+ ret = usb_submit_urb(buf->urb, gfp); -+ if (ret) -+ dev_err(dev->dev, "Error: submit URB dir:%d ep:%d failed:%d\n", -+ dir, ep_idx, ret); -+ return ret; -+} -+ -+void mt7601u_complete_urb(struct urb *urb) -+{ -+ struct completion *cmpl = urb->context; -+ -+ complete(cmpl); -+} -+ -+int mt7601u_vendor_request(struct mt7601u_dev *dev, const u8 req, -+ const u8 direction, const u16 val, const u16 offset, -+ void *buf, const size_t buflen) -+{ -+ int i, ret; -+ struct usb_device *usb_dev = mt7601u_to_usb_dev(dev); -+ const u8 req_type = direction | USB_TYPE_VENDOR | USB_RECIP_DEVICE; -+ const unsigned int pipe = (direction == USB_DIR_IN) ? -+ usb_rcvctrlpipe(usb_dev, 0) : usb_sndctrlpipe(usb_dev, 0); -+ -+ for (i = 0; i < MT_VEND_REQ_MAX_RETRY; i++) { -+ ret = usb_control_msg(usb_dev, pipe, req, req_type, -+ val, offset, buf, buflen, -+ MT_VEND_REQ_TOUT_MS); -+ trace_mt_vend_req(dev, pipe, req, req_type, val, offset, -+ buf, buflen, ret); -+ -+ if (ret == -ENODEV) -+ set_bit(MT7601U_STATE_REMOVED, &dev->state); -+ if (ret >= 0 || ret == -ENODEV) -+ return ret; -+ -+ msleep(5); -+ } -+ -+ dev_err(dev->dev, "Vendor request req:%02x off:%04x failed:%d\n", -+ req, offset, ret); -+ -+ return ret; -+} -+ -+void mt7601u_vendor_reset(struct mt7601u_dev *dev) -+{ -+ mt7601u_vendor_request(dev, MT_VEND_DEV_MODE, USB_DIR_OUT, -+ MT_VEND_DEV_MODE_RESET, 0, NULL, 0); -+} -+ -+u32 mt7601u_rr(struct mt7601u_dev *dev, u32 offset) -+{ -+ int ret; -+ u32 val = ~0; -+ -+ WARN_ONCE(offset > USHRT_MAX, "read high off:%08x", offset); -+ -+ mutex_lock(&dev->vendor_req_mutex); -+ -+ ret = mt7601u_vendor_request(dev, MT_VEND_MULTI_READ, USB_DIR_IN, -+ 0, offset, dev->vend_buf, MT_VEND_BUF); -+ if (ret == MT_VEND_BUF) -+ val = get_unaligned_le32(dev->vend_buf); -+ else if (ret > 0) -+ dev_err(dev->dev, "Error: wrong size read:%d off:%08x\n", -+ ret, offset); -+ -+ mutex_unlock(&dev->vendor_req_mutex); -+ -+ trace_reg_read(dev, offset, val); -+ return val; -+} -+ -+int mt7601u_vendor_single_wr(struct mt7601u_dev *dev, const u8 req, -+ const u16 offset, const u32 val) -+{ -+ int ret; -+ -+ mutex_lock(&dev->vendor_req_mutex); -+ -+ ret = mt7601u_vendor_request(dev, req, USB_DIR_OUT, -+ val & 0xffff, offset, NULL, 0); -+ if (!ret) -+ ret = mt7601u_vendor_request(dev, req, USB_DIR_OUT, -+ val >> 16, offset + 2, NULL, 0); -+ -+ mutex_unlock(&dev->vendor_req_mutex); -+ -+ return ret; -+} -+ -+void mt7601u_wr(struct mt7601u_dev *dev, u32 offset, u32 val) -+{ -+ WARN_ONCE(offset > USHRT_MAX, "write high off:%08x", offset); -+ -+ mt7601u_vendor_single_wr(dev, MT_VEND_WRITE, offset, val); -+ trace_reg_write(dev, offset, val); -+} -+ -+u32 mt7601u_rmw(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val) -+{ -+ val |= mt7601u_rr(dev, offset) & ~mask; -+ mt7601u_wr(dev, offset, val); -+ return val; -+} -+ -+u32 mt7601u_rmc(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val) -+{ -+ u32 reg = mt7601u_rr(dev, offset); -+ -+ val |= reg & ~mask; -+ if (reg != val) -+ mt7601u_wr(dev, offset, val); -+ return val; -+} -+ -+void mt7601u_wr_copy(struct mt7601u_dev *dev, u32 offset, -+ const void *data, int len) -+{ -+ WARN_ONCE(offset & 3, "unaligned write copy off:%08x", offset); -+ WARN_ONCE(len & 3, "short write copy off:%08x", offset); -+ -+ mt7601u_burst_write_regs(dev, offset, data, len / 4); -+} -+ -+void mt7601u_addr_wr(struct mt7601u_dev *dev, const u32 offset, const u8 *addr) -+{ -+ mt7601u_wr(dev, offset, get_unaligned_le32(addr)); -+ mt7601u_wr(dev, offset + 4, addr[4] | addr[5] << 8); -+} -+ -+static int mt7601u_assign_pipes(struct usb_interface *usb_intf, -+ struct mt7601u_dev *dev) -+{ -+ struct usb_endpoint_descriptor *ep_desc; -+ struct usb_host_interface *intf_desc = usb_intf->cur_altsetting; -+ unsigned i, ep_i = 0, ep_o = 0; -+ -+ BUILD_BUG_ON(sizeof(dev->in_eps) < __MT_EP_IN_MAX); -+ BUILD_BUG_ON(sizeof(dev->out_eps) < __MT_EP_OUT_MAX); -+ -+ for (i = 0; i < intf_desc->desc.bNumEndpoints; i++) { -+ ep_desc = &intf_desc->endpoint[i].desc; -+ -+ if (usb_endpoint_is_bulk_in(ep_desc) && -+ ep_i++ < __MT_EP_IN_MAX) { -+ dev->in_eps[ep_i - 1] = usb_endpoint_num(ep_desc); -+ dev->in_max_packet = usb_endpoint_maxp(ep_desc); -+ /* Note: this is ignored by usb sub-system but vendor -+ * code does it. We can drop this at some point. -+ */ -+ dev->in_eps[ep_i - 1] |= USB_DIR_IN; -+ } else if (usb_endpoint_is_bulk_out(ep_desc) && -+ ep_o++ < __MT_EP_OUT_MAX) { -+ dev->out_eps[ep_o - 1] = usb_endpoint_num(ep_desc); -+ dev->out_max_packet = usb_endpoint_maxp(ep_desc); -+ } -+ } -+ -+ if (ep_i != __MT_EP_IN_MAX || ep_o != __MT_EP_OUT_MAX) { -+ dev_err(dev->dev, "Error: wrong pipe number in:%d out:%d\n", -+ ep_i, ep_o); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static int mt7601u_probe(struct usb_interface *usb_intf, -+ const struct usb_device_id *id) -+{ -+ struct usb_device *usb_dev = interface_to_usbdev(usb_intf); -+ struct mt7601u_dev *dev; -+ u32 asic_rev, mac_rev; -+ int ret; -+ -+ dev = mt7601u_alloc_device(&usb_intf->dev); -+ if (!dev) -+ return -ENOMEM; -+ -+ usb_dev = usb_get_dev(usb_dev); -+ usb_reset_device(usb_dev); -+ -+ usb_set_intfdata(usb_intf, dev); -+ -+ dev->vend_buf = devm_kmalloc(dev->dev, MT_VEND_BUF, GFP_KERNEL); -+ if (!dev->vend_buf) { -+ ret = -ENOMEM; -+ goto err; -+ } -+ -+ ret = mt7601u_assign_pipes(usb_intf, dev); -+ if (ret) -+ goto err; -+ ret = mt7601u_wait_asic_ready(dev); -+ if (ret) -+ goto err; -+ -+ asic_rev = mt7601u_rr(dev, MT_ASIC_VERSION); -+ mac_rev = mt7601u_rr(dev, MT_MAC_CSR0); -+ dev_info(dev->dev, "ASIC revision: %08x MAC revision: %08x\n", -+ asic_rev, mac_rev); -+ -+ /* Note: vendor driver skips this check for MT7601U */ -+ if (!(mt7601u_rr(dev, MT_EFUSE_CTRL) & MT_EFUSE_CTRL_SEL)) -+ dev_warn(dev->dev, "Warning: eFUSE not present\n"); -+ -+ ret = mt7601u_init_hardware(dev); -+ if (ret) -+ goto err; -+ ret = mt7601u_register_device(dev); -+ if (ret) -+ goto err_hw; -+ -+ set_bit(MT7601U_STATE_INITIALIZED, &dev->state); -+ -+ return 0; -+err_hw: -+ mt7601u_cleanup(dev); -+err: -+ usb_set_intfdata(usb_intf, NULL); -+ usb_put_dev(interface_to_usbdev(usb_intf)); -+ -+ destroy_workqueue(dev->stat_wq); -+ ieee80211_free_hw(dev->hw); -+ return ret; -+} -+ -+static void mt7601u_disconnect(struct usb_interface *usb_intf) -+{ -+ struct mt7601u_dev *dev = usb_get_intfdata(usb_intf); -+ -+ ieee80211_unregister_hw(dev->hw); -+ mt7601u_cleanup(dev); -+ -+ usb_set_intfdata(usb_intf, NULL); -+ usb_put_dev(interface_to_usbdev(usb_intf)); -+ -+ destroy_workqueue(dev->stat_wq); -+ ieee80211_free_hw(dev->hw); -+} -+ -+static int mt7601u_suspend(struct usb_interface *usb_intf, pm_message_t state) -+{ -+ struct mt7601u_dev *dev = usb_get_intfdata(usb_intf); -+ -+ mt7601u_cleanup(dev); -+ -+ return 0; -+} -+ -+static int mt7601u_resume(struct usb_interface *usb_intf) -+{ -+ struct mt7601u_dev *dev = usb_get_intfdata(usb_intf); -+ int ret; -+ -+ ret = mt7601u_init_hardware(dev); -+ if (ret) -+ return ret; -+ -+ set_bit(MT7601U_STATE_INITIALIZED, &dev->state); -+ -+ return 0; -+} -+ -+MODULE_DEVICE_TABLE(usb, mt7601u_device_table); -+MODULE_FIRMWARE(MT7601U_FIRMWARE); -+MODULE_LICENSE("GPL"); -+ -+static struct usb_driver mt7601u_driver = { -+ .name = KBUILD_MODNAME, -+ .id_table = mt7601u_device_table, -+ .probe = mt7601u_probe, -+ .disconnect = mt7601u_disconnect, -+ .suspend = mt7601u_suspend, -+ .resume = mt7601u_resume, -+ .reset_resume = mt7601u_resume, -+ .soft_unbind = 1, -+ .disable_hub_initiated_lpm = 1, -+}; -+module_usb_driver(mt7601u_driver); -diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/usb.h linux-rpi/drivers/net/wireless/mediatek/mt7601u/usb.h ---- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/usb.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/usb.h 2015-11-29 09:42:38.887167260 +0100 -@@ -0,0 +1,79 @@ -+/* -+ * Copyright (C) 2015 Jakub Kicinski -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 -+ * as published by the Free Software Foundation -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#ifndef __MT7601U_USB_H -+#define __MT7601U_USB_H -+ -+#include "mt7601u.h" -+ -+#define MT7601U_FIRMWARE "mt7601u.bin" -+ -+#define MT_VEND_REQ_MAX_RETRY 10 -+#define MT_VEND_REQ_TOUT_MS 300 -+ -+#define MT_VEND_DEV_MODE_RESET 1 -+ -+#define MT_VEND_BUF sizeof(__le32) -+ -+enum mt_vendor_req { -+ MT_VEND_DEV_MODE = 1, -+ MT_VEND_WRITE = 2, -+ MT_VEND_MULTI_READ = 7, -+ MT_VEND_WRITE_FCE = 0x42, -+}; -+ -+enum mt_usb_ep_in { -+ MT_EP_IN_PKT_RX, -+ MT_EP_IN_CMD_RESP, -+ __MT_EP_IN_MAX, -+}; -+ -+enum mt_usb_ep_out { -+ MT_EP_OUT_INBAND_CMD, -+ MT_EP_OUT_AC_BK, -+ MT_EP_OUT_AC_BE, -+ MT_EP_OUT_AC_VI, -+ MT_EP_OUT_AC_VO, -+ MT_EP_OUT_HCCA, -+ __MT_EP_OUT_MAX, -+}; -+ -+static inline struct usb_device *mt7601u_to_usb_dev(struct mt7601u_dev *mt7601u) -+{ -+ return interface_to_usbdev(to_usb_interface(mt7601u->dev)); -+} -+ -+static inline bool mt7601u_urb_has_error(struct urb *urb) -+{ -+ return urb->status && -+ urb->status != -ENOENT && -+ urb->status != -ECONNRESET && -+ urb->status != -ESHUTDOWN; -+} -+ -+bool mt7601u_usb_alloc_buf(struct mt7601u_dev *dev, size_t len, -+ struct mt7601u_dma_buf *buf); -+void mt7601u_usb_free_buf(struct mt7601u_dev *dev, struct mt7601u_dma_buf *buf); -+int mt7601u_usb_submit_buf(struct mt7601u_dev *dev, int dir, int ep_idx, -+ struct mt7601u_dma_buf *buf, gfp_t gfp, -+ usb_complete_t complete_fn, void *context); -+void mt7601u_complete_urb(struct urb *urb); -+ -+int mt7601u_vendor_request(struct mt7601u_dev *dev, const u8 req, -+ const u8 direction, const u16 val, const u16 offset, -+ void *buf, const size_t buflen); -+void mt7601u_vendor_reset(struct mt7601u_dev *dev); -+int mt7601u_vendor_single_wr(struct mt7601u_dev *dev, const u8 req, -+ const u16 offset, const u32 val); -+ -+#endif -diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/util.c linux-rpi/drivers/net/wireless/mediatek/mt7601u/util.c ---- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/util.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/util.c 2015-11-29 09:42:38.887167260 +0100 -@@ -0,0 +1,42 @@ -+/* -+ * Copyright (C) 2014 Felix Fietkau -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 -+ * as published by the Free Software Foundation -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#include "mt7601u.h" -+ -+void mt76_remove_hdr_pad(struct sk_buff *skb) -+{ -+ int len = ieee80211_get_hdrlen_from_skb(skb); -+ -+ memmove(skb->data + 2, skb->data, len); -+ skb_pull(skb, 2); -+} -+ -+int mt76_insert_hdr_pad(struct sk_buff *skb) -+{ -+ int len = ieee80211_get_hdrlen_from_skb(skb); -+ int ret; -+ -+ if (len % 4 == 0) -+ return 0; -+ -+ ret = skb_cow(skb, 2); -+ if (ret) -+ return ret; -+ -+ skb_push(skb, 2); -+ memmove(skb->data, skb->data + 2, len); -+ -+ skb->data[len] = 0; -+ skb->data[len + 1] = 0; -+ return 0; -+} -diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/util.h linux-rpi/drivers/net/wireless/mediatek/mt7601u/util.h ---- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/util.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/util.h 2015-11-29 09:42:38.887167260 +0100 -@@ -0,0 +1,77 @@ -+/* -+ * Copyright (C) 2014 Felix Fietkau -+ * Copyright (C) 2004 - 2009 Ivo van Doorn -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 -+ * as published by the Free Software Foundation -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ -+#ifndef __MT76_UTIL_H -+#define __MT76_UTIL_H -+ -+/* -+ * Power of two check, this will check -+ * if the mask that has been given contains and contiguous set of bits. -+ * Note that we cannot use the is_power_of_2() function since this -+ * check must be done at compile-time. -+ */ -+#define is_power_of_two(x) ( !((x) & ((x)-1)) ) -+#define low_bit_mask(x) ( ((x)-1) & ~(x) ) -+#define is_valid_mask(x) is_power_of_two(1LU + (x) + low_bit_mask(x)) -+ -+/* -+ * Macros to find first set bit in a variable. -+ * These macros behave the same as the __ffs() functions but -+ * the most important difference that this is done during -+ * compile-time rather then run-time. -+ */ -+#define compile_ffs2(__x) \ -+ __builtin_choose_expr(((__x) & 0x1), 0, 1) -+ -+#define compile_ffs4(__x) \ -+ __builtin_choose_expr(((__x) & 0x3), \ -+ (compile_ffs2((__x))), \ -+ (compile_ffs2((__x) >> 2) + 2)) -+ -+#define compile_ffs8(__x) \ -+ __builtin_choose_expr(((__x) & 0xf), \ -+ (compile_ffs4((__x))), \ -+ (compile_ffs4((__x) >> 4) + 4)) -+ -+#define compile_ffs16(__x) \ -+ __builtin_choose_expr(((__x) & 0xff), \ -+ (compile_ffs8((__x))), \ -+ (compile_ffs8((__x) >> 8) + 8)) -+ -+#define compile_ffs32(__x) \ -+ __builtin_choose_expr(((__x) & 0xffff), \ -+ (compile_ffs16((__x))), \ -+ (compile_ffs16((__x) >> 16) + 16)) -+ -+/* -+ * This macro will check the requirements for the FIELD{8,16,32} macros -+ * The mask should be a constant non-zero contiguous set of bits which -+ * does not exceed the given typelimit. -+ */ -+#define FIELD_CHECK(__mask) \ -+ BUILD_BUG_ON(!(__mask) || !is_valid_mask(__mask)) -+ -+#define MT76_SET(_mask, _val) \ -+ ({ \ -+ FIELD_CHECK(_mask); \ -+ (((u32) (_val)) << compile_ffs32(_mask)) & _mask; \ -+ }) -+ -+#define MT76_GET(_mask, _val) \ -+ ({ \ -+ FIELD_CHECK(_mask); \ -+ (u32) (((_val) & _mask) >> compile_ffs32(_mask)); \ -+ }) -+ -+#endif -diff -Nur linux-4.1.13.orig/drivers/of/fdt.c linux-rpi/drivers/of/fdt.c ---- linux-4.1.13.orig/drivers/of/fdt.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/of/fdt.c 2015-11-29 09:42:39.031157693 +0100 -@@ -933,19 +933,38 @@ - - /* Retrieve command line */ - p = of_get_flat_dt_prop(node, "bootargs", &l); -- if (p != NULL && l > 0) -- strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE)); - - /* - * CONFIG_CMDLINE is meant to be a default in case nothing else - * managed to set the command line, unless CONFIG_CMDLINE_FORCE - * is set in which case we override whatever was found earlier. -+ * -+ * However, it can be useful to be able to treat the default as -+ * a starting point to be extended using CONFIG_CMDLINE_EXTEND. - */ -+ ((char *)data)[0] = '\0'; -+ - #ifdef CONFIG_CMDLINE --#ifndef CONFIG_CMDLINE_FORCE -- if (!((char *)data)[0]) -+ strlcpy(data, CONFIG_CMDLINE, COMMAND_LINE_SIZE); -+ -+ if (p != NULL && l > 0) { -+#if defined(CONFIG_CMDLINE_EXTEND) -+ int len = strlen(data); -+ if (len > 0) { -+ strlcat(data, " ", COMMAND_LINE_SIZE); -+ len++; -+ } -+ strlcpy((char *)data + len, p, min((int)l, COMMAND_LINE_SIZE - len)); -+#elif defined(CONFIG_CMDLINE_FORCE) -+ pr_warning("Ignoring bootargs property (using the default kernel command line)\n"); -+#else -+ /* Neither extend nor force - just override */ -+ strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE)); - #endif -- strlcpy(data, CONFIG_CMDLINE, COMMAND_LINE_SIZE); -+ } -+#else /* CONFIG_CMDLINE */ -+ if (p != NULL && l > 0) { -+ strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE)); - #endif /* CONFIG_CMDLINE */ - - pr_debug("Command line is: %s\n", (char*)data); -diff -Nur linux-4.1.13.orig/drivers/pinctrl/bcm/pinctrl-bcm2835.c linux-rpi/drivers/pinctrl/bcm/pinctrl-bcm2835.c ---- linux-4.1.13.orig/drivers/pinctrl/bcm/pinctrl-bcm2835.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/pinctrl/bcm/pinctrl-bcm2835.c 2015-11-29 09:42:39.071155035 +0100 -@@ -47,6 +47,7 @@ - #define MODULE_NAME "pinctrl-bcm2835" - #define BCM2835_NUM_GPIOS 54 - #define BCM2835_NUM_BANKS 2 -+#define BCM2835_NUM_IRQS 3 - - #define BCM2835_PIN_BITMAP_SZ \ - DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8) -@@ -88,13 +89,13 @@ - - struct bcm2835_gpio_irqdata { - struct bcm2835_pinctrl *pc; -- int bank; -+ int irqgroup; - }; - - struct bcm2835_pinctrl { - struct device *dev; - void __iomem *base; -- int irq[BCM2835_NUM_BANKS]; -+ int irq[BCM2835_NUM_IRQS]; - - /* note: locking assumes each bank will have its own unsigned long */ - unsigned long enabled_irq_map[BCM2835_NUM_BANKS]; -@@ -105,7 +106,7 @@ - struct gpio_chip gpio_chip; - struct pinctrl_gpio_range gpio_range; - -- struct bcm2835_gpio_irqdata irq_data[BCM2835_NUM_BANKS]; -+ struct bcm2835_gpio_irqdata irq_data[BCM2835_NUM_IRQS]; - spinlock_t irq_lock[BCM2835_NUM_BANKS]; - }; - -@@ -355,7 +356,14 @@ - static int bcm2835_gpio_direction_output(struct gpio_chip *chip, - unsigned offset, int value) - { -- return pinctrl_gpio_direction_output(chip->base + offset); -+ struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev); -+ int ret; -+ -+ ret = pinctrl_gpio_direction_output(chip->base + offset); -+ if (ret >= 0) -+ bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset); -+ -+ return ret; - } - - static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value) -@@ -382,22 +390,21 @@ - .get = bcm2835_gpio_get, - .set = bcm2835_gpio_set, - .to_irq = bcm2835_gpio_to_irq, -- .base = -1, -+ .base = 0, - .ngpio = BCM2835_NUM_GPIOS, - .can_sleep = false, - }; - --static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id) -+static int bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc, -+ unsigned int bank, u32 mask) - { -- struct bcm2835_gpio_irqdata *irqdata = dev_id; -- struct bcm2835_pinctrl *pc = irqdata->pc; -- int bank = irqdata->bank; - unsigned long events; - unsigned offset; - unsigned gpio; - unsigned int type; - - events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4); -+ events &= mask; - events &= pc->enabled_irq_map[bank]; - for_each_set_bit(offset, &events, 32) { - gpio = (32 * bank) + offset; -@@ -405,7 +412,30 @@ - - generic_handle_irq(irq_linear_revmap(pc->irq_domain, gpio)); - } -- return events ? IRQ_HANDLED : IRQ_NONE; -+ -+ return (events != 0); -+} -+ -+static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id) -+{ -+ struct bcm2835_gpio_irqdata *irqdata = dev_id; -+ struct bcm2835_pinctrl *pc = irqdata->pc; -+ int handled = 0; -+ -+ switch (irqdata->irqgroup) { -+ case 0: /* IRQ0 covers GPIOs 0-27 */ -+ handled = bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff); -+ break; -+ case 1: /* IRQ1 covers GPIOs 28-45 */ -+ handled = bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000) | -+ bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff); -+ break; -+ case 2: /* IRQ2 covers GPIOs 46-53 */ -+ handled = bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000); -+ break; -+ } -+ -+ return handled ? IRQ_HANDLED : IRQ_NONE; - } - - static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc, -@@ -473,6 +503,8 @@ - - spin_lock_irqsave(&pc->irq_lock[bank], flags); - bcm2835_gpio_irq_config(pc, gpio, false); -+ /* Clear events that were latched prior to clearing event sources */ -+ bcm2835_gpio_set_bit(pc, GPEDS0, gpio); - clear_bit(offset, &pc->enabled_irq_map[bank]); - spin_unlock_irqrestore(&pc->irq_lock[bank], flags); - } -@@ -993,8 +1025,6 @@ - for (i = 0; i < BCM2835_NUM_BANKS; i++) { - unsigned long events; - unsigned offset; -- int len; -- char *name; - - /* clear event detection flags */ - bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0); -@@ -1009,10 +1039,17 @@ - for_each_set_bit(offset, &events, 32) - bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset)); - -+ spin_lock_init(&pc->irq_lock[i]); -+ } -+ -+ for (i = 0; i < BCM2835_NUM_IRQS; i++) { -+ int len; -+ char *name; - pc->irq[i] = irq_of_parse_and_map(np, i); -+ if (pc->irq[i] == 0) -+ break; - pc->irq_data[i].pc = pc; -- pc->irq_data[i].bank = i; -- spin_lock_init(&pc->irq_lock[i]); -+ pc->irq_data[i].irqgroup = i; - - len = strlen(dev_name(pc->dev)) + 16; - name = devm_kzalloc(pc->dev, len, GFP_KERNEL); -@@ -1070,6 +1107,7 @@ - .remove = bcm2835_pinctrl_remove, - .driver = { - .name = MODULE_NAME, -+ .owner = THIS_MODULE, - .of_match_table = bcm2835_pinctrl_match, - }, - }; -diff -Nur linux-4.1.13.orig/drivers/pinctrl/Makefile linux-rpi/drivers/pinctrl/Makefile ---- linux-4.1.13.orig/drivers/pinctrl/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/pinctrl/Makefile 2015-11-29 09:42:39.071155035 +0100 -@@ -38,6 +38,7 @@ - obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o - obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o - -+obj-$(CONFIG_ARCH_BCM2708)$(CONFIG_ARCH_BCM2709) += bcm/ - obj-$(CONFIG_ARCH_BCM) += bcm/ - obj-$(CONFIG_ARCH_BERLIN) += berlin/ - obj-y += freescale/ -diff -Nur linux-4.1.13.orig/drivers/power/reset/gpio-poweroff.c linux-rpi/drivers/power/reset/gpio-poweroff.c ---- linux-4.1.13.orig/drivers/power/reset/gpio-poweroff.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/power/reset/gpio-poweroff.c 2015-11-29 09:42:39.131151049 +0100 -@@ -48,9 +48,11 @@ - static int gpio_poweroff_probe(struct platform_device *pdev) - { - bool input = false; -+ bool force = false; - - /* If a pm_power_off function has already been added, leave it alone */ -- if (pm_power_off != NULL) { -+ force = of_property_read_bool(pdev->dev.of_node, "force"); -+ if (!force && (pm_power_off != NULL)) { - dev_err(&pdev->dev, - "%s: pm_power_off function already registered", - __func__); -diff -Nur linux-4.1.13.orig/drivers/pwm/Kconfig linux-rpi/drivers/pwm/Kconfig ---- linux-4.1.13.orig/drivers/pwm/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/pwm/Kconfig 2015-11-29 09:42:39.139150517 +0100 -@@ -85,7 +85,7 @@ - - config PWM_BCM2835 - tristate "BCM2835 PWM support" -- depends on ARCH_BCM2835 -+ depends on ARCH_BCM2835 || ARCH_BCM2708 || ARCH_BCM2709 - help - PWM framework driver for BCM2835 controller (Raspberry Pi) - -diff -Nur linux-4.1.13.orig/drivers/rtc/rtc-ds1307.c linux-rpi/drivers/rtc/rtc-ds1307.c ---- linux-4.1.13.orig/drivers/rtc/rtc-ds1307.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/rtc/rtc-ds1307.c 2015-11-29 09:42:39.163148923 +0100 -@@ -1242,6 +1242,14 @@ - return 0; - } - -+#ifdef CONFIG_OF -+static const struct of_device_id ds1307_of_match[] = { -+ { .compatible = "maxim,ds1307" }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, ds1307_of_match); -+#endif -+ - static struct i2c_driver ds1307_driver = { - .driver = { - .name = "rtc-ds1307", -diff -Nur linux-4.1.13.orig/drivers/spi/Kconfig linux-rpi/drivers/spi/Kconfig ---- linux-4.1.13.orig/drivers/spi/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/spi/Kconfig 2015-11-29 09:42:39.435130851 +0100 -@@ -77,7 +77,7 @@ - - config SPI_BCM2835 - tristate "BCM2835 SPI controller" -- depends on ARCH_BCM2835 || COMPILE_TEST -+ depends on ARCH_BCM2835 || ARCH_BCM2708 || ARCH_BCM2709 || COMPILE_TEST - depends on GPIOLIB - help - This selects a driver for the Broadcom BCM2835 SPI master. -@@ -87,6 +87,14 @@ - is for the regular SPI controller. Slave mode operation is not also - not supported. - -+config SPI_BCM2708 -+ tristate "BCM2708 SPI controller driver (SPI0)" -+ depends on MACH_BCM2708 || MACH_BCM2709 -+ help -+ This selects a driver for the Broadcom BCM2708 SPI master (SPI0). This -+ driver is not compatible with the "Universal SPI Master" or the SPI slave -+ device. -+ - config SPI_BFIN5XX - tristate "SPI controller driver for ADI Blackfin5xx" - depends on BLACKFIN && !BF60x -diff -Nur linux-4.1.13.orig/drivers/spi/Makefile linux-rpi/drivers/spi/Makefile ---- linux-4.1.13.orig/drivers/spi/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/spi/Makefile 2015-11-29 09:42:39.435130851 +0100 -@@ -20,6 +20,7 @@ - obj-$(CONFIG_SPI_BCM63XX_HSSPI) += spi-bcm63xx-hsspi.o - obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o - obj-$(CONFIG_SPI_ADI_V3) += spi-adi-v3.o -+obj-$(CONFIG_SPI_BCM2708) += spi-bcm2708.o - obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o - obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o - obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o -diff -Nur linux-4.1.13.orig/drivers/spi/spi-bcm2708.c linux-rpi/drivers/spi/spi-bcm2708.c ---- linux-4.1.13.orig/drivers/spi/spi-bcm2708.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/spi/spi-bcm2708.c 2015-11-29 09:42:39.435130851 +0100 -@@ -0,0 +1,628 @@ -+/* -+ * Driver for Broadcom BCM2708 SPI Controllers -+ * -+ * Copyright (C) 2012 Chris Boot -+ * -+ * This driver is inspired by: -+ * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos -+ * spi-atmel.c, Copyright (C) 2006 Atmel Corporation -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* SPI register offsets */ -+#define SPI_CS 0x00 -+#define SPI_FIFO 0x04 -+#define SPI_CLK 0x08 -+#define SPI_DLEN 0x0c -+#define SPI_LTOH 0x10 -+#define SPI_DC 0x14 -+ -+/* Bitfields in CS */ -+#define SPI_CS_LEN_LONG 0x02000000 -+#define SPI_CS_DMA_LEN 0x01000000 -+#define SPI_CS_CSPOL2 0x00800000 -+#define SPI_CS_CSPOL1 0x00400000 -+#define SPI_CS_CSPOL0 0x00200000 -+#define SPI_CS_RXF 0x00100000 -+#define SPI_CS_RXR 0x00080000 -+#define SPI_CS_TXD 0x00040000 -+#define SPI_CS_RXD 0x00020000 -+#define SPI_CS_DONE 0x00010000 -+#define SPI_CS_LEN 0x00002000 -+#define SPI_CS_REN 0x00001000 -+#define SPI_CS_ADCS 0x00000800 -+#define SPI_CS_INTR 0x00000400 -+#define SPI_CS_INTD 0x00000200 -+#define SPI_CS_DMAEN 0x00000100 -+#define SPI_CS_TA 0x00000080 -+#define SPI_CS_CSPOL 0x00000040 -+#define SPI_CS_CLEAR_RX 0x00000020 -+#define SPI_CS_CLEAR_TX 0x00000010 -+#define SPI_CS_CPOL 0x00000008 -+#define SPI_CS_CPHA 0x00000004 -+#define SPI_CS_CS_10 0x00000002 -+#define SPI_CS_CS_01 0x00000001 -+ -+#define SPI_TIMEOUT_MS 1000 -+ -+#define DRV_NAME "bcm2708_spi" -+ -+struct bcm2708_spi { -+ spinlock_t lock; -+ void __iomem *base; -+ int irq; -+ struct clk *clk; -+ bool stopping; -+ -+ struct list_head queue; -+ struct workqueue_struct *workq; -+ struct work_struct work; -+ struct completion done; -+ -+ const u8 *tx_buf; -+ u8 *rx_buf; -+ int len; -+}; -+ -+struct bcm2708_spi_state { -+ u32 cs; -+ u16 cdiv; -+}; -+ -+/* -+ * This function sets the ALT mode on the SPI pins so that we can use them with -+ * the SPI hardware. -+ * -+ * FIXME: This is a hack. Use pinmux / pinctrl. -+ */ -+static void bcm2708_init_pinmode(void) -+{ -+#define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3)) -+#define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3)) -+ -+ int pin; -+ u32 *gpio = ioremap(GPIO_BASE, SZ_16K); -+ -+ /* SPI is on GPIO 7..11 */ -+ for (pin = 7; pin <= 11; pin++) { -+ INP_GPIO(pin); /* set mode to GPIO input first */ -+ SET_GPIO_ALT(pin, 0); /* set mode to ALT 0 */ -+ } -+ -+ iounmap(gpio); -+ -+#undef INP_GPIO -+#undef SET_GPIO_ALT -+} -+ -+static inline u32 bcm2708_rd(struct bcm2708_spi *bs, unsigned reg) -+{ -+ return readl(bs->base + reg); -+} -+ -+static inline void bcm2708_wr(struct bcm2708_spi *bs, unsigned reg, u32 val) -+{ -+ writel(val, bs->base + reg); -+} -+ -+static inline void bcm2708_rd_fifo(struct bcm2708_spi *bs, int len) -+{ -+ u8 byte; -+ -+ while (len--) { -+ byte = bcm2708_rd(bs, SPI_FIFO); -+ if (bs->rx_buf) -+ *bs->rx_buf++ = byte; -+ } -+} -+ -+static inline void bcm2708_wr_fifo(struct bcm2708_spi *bs, int len) -+{ -+ u8 byte; -+ u16 val; -+ -+ if (len > bs->len) -+ len = bs->len; -+ -+ if (unlikely(bcm2708_rd(bs, SPI_CS) & SPI_CS_LEN)) { -+ /* LoSSI mode */ -+ if (unlikely(len % 2)) { -+ printk(KERN_ERR"bcm2708_wr_fifo: length must be even, skipping.\n"); -+ bs->len = 0; -+ return; -+ } -+ while (len) { -+ if (bs->tx_buf) { -+ val = *(const u16 *)bs->tx_buf; -+ bs->tx_buf += 2; -+ } else -+ val = 0; -+ bcm2708_wr(bs, SPI_FIFO, val); -+ bs->len -= 2; -+ len -= 2; -+ } -+ return; -+ } -+ -+ while (len--) { -+ byte = bs->tx_buf ? *bs->tx_buf++ : 0; -+ bcm2708_wr(bs, SPI_FIFO, byte); -+ bs->len--; -+ } -+} -+ -+static irqreturn_t bcm2708_spi_interrupt(int irq, void *dev_id) -+{ -+ struct spi_master *master = dev_id; -+ struct bcm2708_spi *bs = spi_master_get_devdata(master); -+ u32 cs; -+ -+ spin_lock(&bs->lock); -+ -+ cs = bcm2708_rd(bs, SPI_CS); -+ -+ if (cs & SPI_CS_DONE) { -+ if (bs->len) { /* first interrupt in a transfer */ -+ /* fill the TX fifo with up to 16 bytes */ -+ bcm2708_wr_fifo(bs, 16); -+ } else { /* transfer complete */ -+ /* disable interrupts */ -+ cs &= ~(SPI_CS_INTR | SPI_CS_INTD); -+ bcm2708_wr(bs, SPI_CS, cs); -+ -+ /* drain RX FIFO */ -+ while (cs & SPI_CS_RXD) { -+ bcm2708_rd_fifo(bs, 1); -+ cs = bcm2708_rd(bs, SPI_CS); -+ } -+ -+ /* wake up our bh */ -+ complete(&bs->done); -+ } -+ } else if (cs & SPI_CS_RXR) { -+ /* read 12 bytes of data */ -+ bcm2708_rd_fifo(bs, 12); -+ -+ /* write up to 12 bytes */ -+ bcm2708_wr_fifo(bs, 12); -+ } -+ -+ spin_unlock(&bs->lock); -+ -+ return IRQ_HANDLED; -+} -+ -+static int bcm2708_setup_state(struct spi_master *master, -+ struct device *dev, struct bcm2708_spi_state *state, -+ u32 hz, u8 csel, u8 mode, u8 bpw) -+{ -+ struct bcm2708_spi *bs = spi_master_get_devdata(master); -+ int cdiv; -+ unsigned long bus_hz; -+ u32 cs = 0; -+ -+ bus_hz = clk_get_rate(bs->clk); -+ -+ if (hz >= bus_hz) { -+ cdiv = 2; /* bus_hz / 2 is as fast as we can go */ -+ } else if (hz) { -+ cdiv = DIV_ROUND_UP(bus_hz, hz); -+ -+ /* CDIV must be a power of 2, so round up */ -+ cdiv = roundup_pow_of_two(cdiv); -+ -+ if (cdiv > 65536) { -+ dev_dbg(dev, -+ "setup: %d Hz too slow, cdiv %u; min %ld Hz\n", -+ hz, cdiv, bus_hz / 65536); -+ return -EINVAL; -+ } else if (cdiv == 65536) { -+ cdiv = 0; -+ } else if (cdiv == 1) { -+ cdiv = 2; /* 1 gets rounded down to 0; == 65536 */ -+ } -+ } else { -+ cdiv = 0; -+ } -+ -+ switch (bpw) { -+ case 8: -+ break; -+ case 9: -+ /* Reading in LoSSI mode is a special case. See 'BCM2835 ARM Peripherals' datasheet */ -+ cs |= SPI_CS_LEN; -+ break; -+ default: -+ dev_dbg(dev, "setup: invalid bits_per_word %u (must be 8 or 9)\n", -+ bpw); -+ return -EINVAL; -+ } -+ -+ if (mode & SPI_CPOL) -+ cs |= SPI_CS_CPOL; -+ if (mode & SPI_CPHA) -+ cs |= SPI_CS_CPHA; -+ -+ if (!(mode & SPI_NO_CS)) { -+ if (mode & SPI_CS_HIGH) { -+ cs |= SPI_CS_CSPOL; -+ cs |= SPI_CS_CSPOL0 << csel; -+ } -+ -+ cs |= csel; -+ } else { -+ cs |= SPI_CS_CS_10 | SPI_CS_CS_01; -+ } -+ -+ if (state) { -+ state->cs = cs; -+ state->cdiv = cdiv; -+ dev_dbg(dev, "setup: want %d Hz; " -+ "bus_hz=%lu / cdiv=%u == %lu Hz; " -+ "mode %u: cs 0x%08X\n", -+ hz, bus_hz, cdiv, bus_hz/cdiv, mode, cs); -+ } -+ -+ return 0; -+} -+ -+static int bcm2708_process_transfer(struct bcm2708_spi *bs, -+ struct spi_message *msg, struct spi_transfer *xfer) -+{ -+ struct spi_device *spi = msg->spi; -+ struct bcm2708_spi_state state, *stp; -+ int ret; -+ u32 cs; -+ -+ if (bs->stopping) -+ return -ESHUTDOWN; -+ -+ if (xfer->bits_per_word || xfer->speed_hz) { -+ ret = bcm2708_setup_state(spi->master, &spi->dev, &state, -+ xfer->speed_hz ? xfer->speed_hz : spi->max_speed_hz, -+ spi->chip_select, spi->mode, -+ xfer->bits_per_word ? xfer->bits_per_word : -+ spi->bits_per_word); -+ if (ret) -+ return ret; -+ -+ stp = &state; -+ } else { -+ stp = spi->controller_state; -+ } -+ -+ reinit_completion(&bs->done); -+ bs->tx_buf = xfer->tx_buf; -+ bs->rx_buf = xfer->rx_buf; -+ bs->len = xfer->len; -+ -+ cs = stp->cs | SPI_CS_INTR | SPI_CS_INTD | SPI_CS_TA; -+ -+ bcm2708_wr(bs, SPI_CLK, stp->cdiv); -+ bcm2708_wr(bs, SPI_CS, cs); -+ -+ ret = wait_for_completion_timeout(&bs->done, -+ msecs_to_jiffies(SPI_TIMEOUT_MS)); -+ if (ret == 0) { -+ dev_err(&spi->dev, "transfer timed out\n"); -+ return -ETIMEDOUT; -+ } -+ -+ if (xfer->delay_usecs) -+ udelay(xfer->delay_usecs); -+ -+ if (list_is_last(&xfer->transfer_list, &msg->transfers) || -+ xfer->cs_change) { -+ /* clear TA and interrupt flags */ -+ bcm2708_wr(bs, SPI_CS, stp->cs); -+ } -+ -+ msg->actual_length += (xfer->len - bs->len); -+ -+ return 0; -+} -+ -+static void bcm2708_work(struct work_struct *work) -+{ -+ struct bcm2708_spi *bs = container_of(work, struct bcm2708_spi, work); -+ unsigned long flags; -+ struct spi_message *msg; -+ struct spi_transfer *xfer; -+ int status = 0; -+ -+ spin_lock_irqsave(&bs->lock, flags); -+ while (!list_empty(&bs->queue)) { -+ msg = list_first_entry(&bs->queue, struct spi_message, queue); -+ list_del_init(&msg->queue); -+ spin_unlock_irqrestore(&bs->lock, flags); -+ -+ list_for_each_entry(xfer, &msg->transfers, transfer_list) { -+ status = bcm2708_process_transfer(bs, msg, xfer); -+ if (status) -+ break; -+ } -+ -+ msg->status = status; -+ msg->complete(msg->context); -+ -+ spin_lock_irqsave(&bs->lock, flags); -+ } -+ spin_unlock_irqrestore(&bs->lock, flags); -+} -+ -+static int bcm2708_spi_setup(struct spi_device *spi) -+{ -+ struct bcm2708_spi *bs = spi_master_get_devdata(spi->master); -+ struct bcm2708_spi_state *state; -+ int ret; -+ -+ if (bs->stopping) -+ return -ESHUTDOWN; -+ -+ state = spi->controller_state; -+ if (!state) { -+ state = kzalloc(sizeof(*state), GFP_KERNEL); -+ if (!state) -+ return -ENOMEM; -+ -+ spi->controller_state = state; -+ } -+ -+ ret = bcm2708_setup_state(spi->master, &spi->dev, state, -+ spi->max_speed_hz, spi->chip_select, spi->mode, -+ spi->bits_per_word); -+ if (ret < 0) { -+ kfree(state); -+ spi->controller_state = NULL; -+ return ret; -+ } -+ -+ dev_dbg(&spi->dev, -+ "setup: cd %d: %d Hz, bpw %u, mode 0x%x -> CS=%08x CDIV=%04x\n", -+ spi->chip_select, spi->max_speed_hz, spi->bits_per_word, -+ spi->mode, state->cs, state->cdiv); -+ -+ return 0; -+} -+ -+static int bcm2708_spi_transfer(struct spi_device *spi, struct spi_message *msg) -+{ -+ struct bcm2708_spi *bs = spi_master_get_devdata(spi->master); -+ struct spi_transfer *xfer; -+ int ret; -+ unsigned long flags; -+ -+ if (unlikely(list_empty(&msg->transfers))) -+ return -EINVAL; -+ -+ if (bs->stopping) -+ return -ESHUTDOWN; -+ -+ list_for_each_entry(xfer, &msg->transfers, transfer_list) { -+ if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) { -+ dev_dbg(&spi->dev, "missing rx or tx buf\n"); -+ return -EINVAL; -+ } -+ -+ if (!xfer->bits_per_word || xfer->speed_hz) -+ continue; -+ -+ ret = bcm2708_setup_state(spi->master, &spi->dev, NULL, -+ xfer->speed_hz ? xfer->speed_hz : spi->max_speed_hz, -+ spi->chip_select, spi->mode, -+ xfer->bits_per_word ? xfer->bits_per_word : -+ spi->bits_per_word); -+ if (ret) -+ return ret; -+ } -+ -+ msg->status = -EINPROGRESS; -+ msg->actual_length = 0; -+ -+ spin_lock_irqsave(&bs->lock, flags); -+ list_add_tail(&msg->queue, &bs->queue); -+ queue_work(bs->workq, &bs->work); -+ spin_unlock_irqrestore(&bs->lock, flags); -+ -+ return 0; -+} -+ -+static void bcm2708_spi_cleanup(struct spi_device *spi) -+{ -+ if (spi->controller_state) { -+ kfree(spi->controller_state); -+ spi->controller_state = NULL; -+ } -+} -+ -+static int bcm2708_spi_probe(struct platform_device *pdev) -+{ -+ struct resource *regs; -+ int irq, err = -ENOMEM; -+ struct clk *clk; -+ struct spi_master *master; -+ struct bcm2708_spi *bs; -+ -+ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!regs) { -+ dev_err(&pdev->dev, "could not get IO memory\n"); -+ return -ENXIO; -+ } -+ -+ irq = platform_get_irq(pdev, 0); -+ if (irq < 0) { -+ dev_err(&pdev->dev, "could not get IRQ\n"); -+ return irq; -+ } -+ -+ clk = clk_get(&pdev->dev, NULL); -+ if (IS_ERR(clk)) { -+ dev_err(&pdev->dev, "could not find clk: %ld\n", PTR_ERR(clk)); -+ return PTR_ERR(clk); -+ } -+ -+ if (!pdev->dev.of_node) -+ bcm2708_init_pinmode(); -+ -+ master = spi_alloc_master(&pdev->dev, sizeof(*bs)); -+ if (!master) { -+ dev_err(&pdev->dev, "spi_alloc_master() failed\n"); -+ goto out_clk_put; -+ } -+ -+ /* the spi->mode bits understood by this driver: */ -+ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS; -+ -+ master->bus_num = pdev->id; -+ master->num_chipselect = 3; -+ master->setup = bcm2708_spi_setup; -+ master->transfer = bcm2708_spi_transfer; -+ master->cleanup = bcm2708_spi_cleanup; -+ master->dev.of_node = pdev->dev.of_node; -+ platform_set_drvdata(pdev, master); -+ -+ bs = spi_master_get_devdata(master); -+ -+ spin_lock_init(&bs->lock); -+ INIT_LIST_HEAD(&bs->queue); -+ init_completion(&bs->done); -+ INIT_WORK(&bs->work, bcm2708_work); -+ -+ bs->base = ioremap(regs->start, resource_size(regs)); -+ if (!bs->base) { -+ dev_err(&pdev->dev, "could not remap memory\n"); -+ goto out_master_put; -+ } -+ -+ bs->workq = create_singlethread_workqueue(dev_name(&pdev->dev)); -+ if (!bs->workq) { -+ dev_err(&pdev->dev, "could not create workqueue\n"); -+ goto out_iounmap; -+ } -+ -+ bs->irq = irq; -+ bs->clk = clk; -+ bs->stopping = false; -+ -+ err = request_irq(irq, bcm2708_spi_interrupt, 0, dev_name(&pdev->dev), -+ master); -+ if (err) { -+ dev_err(&pdev->dev, "could not request IRQ: %d\n", err); -+ goto out_workqueue; -+ } -+ -+ /* initialise the hardware */ -+ clk_prepare_enable(clk); -+ bcm2708_wr(bs, SPI_CS, SPI_CS_REN | SPI_CS_CLEAR_RX | SPI_CS_CLEAR_TX); -+ -+ err = spi_register_master(master); -+ if (err) { -+ dev_err(&pdev->dev, "could not register SPI master: %d\n", err); -+ goto out_free_irq; -+ } -+ -+ dev_info(&pdev->dev, "SPI Controller at 0x%08lx (irq %d)\n", -+ (unsigned long)regs->start, irq); -+ -+ return 0; -+ -+out_free_irq: -+ free_irq(bs->irq, master); -+ clk_disable_unprepare(bs->clk); -+out_workqueue: -+ destroy_workqueue(bs->workq); -+out_iounmap: -+ iounmap(bs->base); -+out_master_put: -+ spi_master_put(master); -+out_clk_put: -+ clk_put(clk); -+ return err; -+} -+ -+static int bcm2708_spi_remove(struct platform_device *pdev) -+{ -+ struct spi_master *master = platform_get_drvdata(pdev); -+ struct bcm2708_spi *bs = spi_master_get_devdata(master); -+ -+ /* reset the hardware and block queue progress */ -+ spin_lock_irq(&bs->lock); -+ bs->stopping = true; -+ bcm2708_wr(bs, SPI_CS, SPI_CS_CLEAR_RX | SPI_CS_CLEAR_TX); -+ spin_unlock_irq(&bs->lock); -+ -+ flush_work(&bs->work); -+ -+ clk_disable_unprepare(bs->clk); -+ clk_put(bs->clk); -+ free_irq(bs->irq, master); -+ iounmap(bs->base); -+ -+ spi_unregister_master(master); -+ -+ return 0; -+} -+ -+static const struct of_device_id bcm2708_spi_match[] = { -+ { .compatible = "brcm,bcm2708-spi", }, -+ {} -+}; -+MODULE_DEVICE_TABLE(of, bcm2708_spi_match); -+ -+static struct platform_driver bcm2708_spi_driver = { -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ .of_match_table = bcm2708_spi_match, -+ }, -+ .probe = bcm2708_spi_probe, -+ .remove = bcm2708_spi_remove, -+}; -+ -+ -+static int __init bcm2708_spi_init(void) -+{ -+ return platform_driver_probe(&bcm2708_spi_driver, bcm2708_spi_probe); -+} -+module_init(bcm2708_spi_init); -+ -+static void __exit bcm2708_spi_exit(void) -+{ -+ platform_driver_unregister(&bcm2708_spi_driver); -+} -+module_exit(bcm2708_spi_exit); -+ -+ -+//module_platform_driver(bcm2708_spi_driver); -+ -+MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2708"); -+MODULE_AUTHOR("Chris Boot "); -+MODULE_LICENSE("GPL v2"); -+MODULE_ALIAS("platform:" DRV_NAME); -diff -Nur linux-4.1.13.orig/drivers/spi/spi-bcm2835.c linux-rpi/drivers/spi/spi-bcm2835.c ---- linux-4.1.13.orig/drivers/spi/spi-bcm2835.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/spi/spi-bcm2835.c 2015-11-29 09:42:39.435130851 +0100 -@@ -20,18 +20,22 @@ - * GNU General Public License for more details. - */ - -+#include - #include - #include - #include -+#include -+#include - #include - #include - #include - #include - #include - #include --#include --#include -+#include - #include -+#include -+#include - #include - - /* SPI register offsets */ -@@ -69,7 +73,8 @@ - #define BCM2835_SPI_CS_CS_01 0x00000001 - - #define BCM2835_SPI_POLLING_LIMIT_US 30 --#define BCM2835_SPI_TIMEOUT_MS 30000 -+#define BCM2835_SPI_POLLING_JIFFIES 2 -+#define BCM2835_SPI_DMA_MIN_LENGTH 96 - #define BCM2835_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \ - | SPI_NO_CS | SPI_3WIRE) - -@@ -83,6 +88,7 @@ - u8 *rx_buf; - int tx_len; - int rx_len; -+ bool dma_pending; - }; - - static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg) -@@ -128,12 +134,15 @@ - /* Disable SPI interrupts and transfer */ - cs &= ~(BCM2835_SPI_CS_INTR | - BCM2835_SPI_CS_INTD | -+ BCM2835_SPI_CS_DMAEN | - BCM2835_SPI_CS_TA); - /* and reset RX/TX FIFOS */ - cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX; - - /* and reset the SPI_HW */ - bcm2835_wr(bs, BCM2835_SPI_CS, cs); -+ /* as well as DLEN */ -+ bcm2835_wr(bs, BCM2835_SPI_DLEN, 0); - } - - static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id) -@@ -157,42 +166,6 @@ - return IRQ_HANDLED; - } - --static int bcm2835_spi_transfer_one_poll(struct spi_master *master, -- struct spi_device *spi, -- struct spi_transfer *tfr, -- u32 cs, -- unsigned long xfer_time_us) --{ -- struct bcm2835_spi *bs = spi_master_get_devdata(master); -- /* set timeout to 1 second of maximum polling */ -- unsigned long timeout = jiffies + HZ; -- -- /* enable HW block without interrupts */ -- bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA); -- -- /* loop until finished the transfer */ -- while (bs->rx_len) { -- /* read from fifo as much as possible */ -- bcm2835_rd_fifo(bs); -- /* fill in tx fifo as much as possible */ -- bcm2835_wr_fifo(bs); -- /* if we still expect some data after the read, -- * check for a possible timeout -- */ -- if (bs->rx_len && time_after(jiffies, timeout)) { -- /* Transfer complete - reset SPI HW */ -- bcm2835_spi_reset_hw(master); -- /* and return timeout */ -- return -ETIMEDOUT; -- } -- } -- -- /* Transfer complete - reset SPI HW */ -- bcm2835_spi_reset_hw(master); -- /* and return without waiting for completion */ -- return 0; --} -- - static int bcm2835_spi_transfer_one_irq(struct spi_master *master, - struct spi_device *spi, - struct spi_transfer *tfr, -@@ -229,13 +202,337 @@ - return 1; - } - -+/* -+ * DMA support -+ * -+ * this implementation has currently a few issues in so far as it does -+ * not work arrount limitations of the HW. -+ * -+ * the main one being that DMA transfers are limited to 16 bit -+ * (so 0 to 65535 bytes) by the SPI HW due to BCM2835_SPI_DLEN -+ * -+ * also we currently assume that the scatter-gather fragments are -+ * all multiple of 4 (except the last) - otherwise we would need -+ * to reset the FIFO before subsequent transfers... -+ * this also means that tx/rx transfers sg's need to be of equal size! -+ * -+ * there may be a few more border-cases we may need to address as well -+ * but unfortunately this would mean splitting up the scatter-gather -+ * list making it slightly unpractical... -+ */ -+static void bcm2835_spi_dma_done(void *data) -+{ -+ struct spi_master *master = data; -+ struct bcm2835_spi *bs = spi_master_get_devdata(master); -+ -+ /* reset fifo and HW */ -+ bcm2835_spi_reset_hw(master); -+ -+ /* and terminate tx-dma as we do not have an irq for it -+ * because when the rx dma will terminate and this callback -+ * is called the tx-dma must have finished - can't get to this -+ * situation otherwise... -+ */ -+ dmaengine_terminate_all(master->dma_tx); -+ -+ /* mark as no longer pending */ -+ bs->dma_pending = 0; -+ -+ /* and mark as completed */; -+ complete(&master->xfer_completion); -+} -+ -+static int bcm2835_spi_prepare_sg(struct spi_master *master, -+ struct spi_transfer *tfr, -+ bool is_tx) -+{ -+ struct dma_chan *chan; -+ struct scatterlist *sgl; -+ unsigned int nents; -+ enum dma_transfer_direction dir; -+ unsigned long flags; -+ -+ struct dma_async_tx_descriptor *desc; -+ dma_cookie_t cookie; -+ -+ if (is_tx) { -+ dir = DMA_MEM_TO_DEV; -+ chan = master->dma_tx; -+ nents = tfr->tx_sg.nents; -+ sgl = tfr->tx_sg.sgl; -+ flags = 0 /* no tx interrupt */; -+ -+ } else { -+ dir = DMA_DEV_TO_MEM; -+ chan = master->dma_rx; -+ nents = tfr->rx_sg.nents; -+ sgl = tfr->rx_sg.sgl; -+ flags = DMA_PREP_INTERRUPT; -+ } -+ /* prepare the channel */ -+ desc = dmaengine_prep_slave_sg(chan, sgl, nents, dir, flags); -+ if (!desc) -+ return -EINVAL; -+ -+ /* set callback for rx */ -+ if (!is_tx) { -+ desc->callback = bcm2835_spi_dma_done; -+ desc->callback_param = master; -+ } -+ -+ /* submit it to DMA-engine */ -+ cookie = dmaengine_submit(desc); -+ -+ return dma_submit_error(cookie); -+} -+ -+static inline int bcm2835_check_sg_length(struct sg_table *sgt) -+{ -+ int i; -+ struct scatterlist *sgl; -+ -+ /* check that the sg entries are word-sized (except for last) */ -+ for_each_sg(sgt->sgl, sgl, (int)sgt->nents - 1, i) { -+ if (sg_dma_len(sgl) % 4) -+ return -EFAULT; -+ } -+ -+ return 0; -+} -+ -+static int bcm2835_spi_transfer_one_dma(struct spi_master *master, -+ struct spi_device *spi, -+ struct spi_transfer *tfr, -+ u32 cs) -+{ -+ struct bcm2835_spi *bs = spi_master_get_devdata(master); -+ int ret; -+ -+ /* check that the scatter gather segments are all a multiple of 4 */ -+ if (bcm2835_check_sg_length(&tfr->tx_sg) || -+ bcm2835_check_sg_length(&tfr->rx_sg)) { -+ dev_warn_once(&spi->dev, -+ "scatter gather segment length is not a multiple of 4 - falling back to interrupt mode\n"); -+ return bcm2835_spi_transfer_one_irq(master, spi, tfr, cs); -+ } -+ -+ /* setup tx-DMA */ -+ ret = bcm2835_spi_prepare_sg(master, tfr, true); -+ if (ret) -+ return ret; -+ -+ /* start TX early */ -+ dma_async_issue_pending(master->dma_tx); -+ -+ /* mark as dma pending */ -+ bs->dma_pending = 1; -+ -+ /* set the DMA length */ -+ bcm2835_wr(bs, BCM2835_SPI_DLEN, tfr->len); -+ -+ /* start the HW */ -+ bcm2835_wr(bs, BCM2835_SPI_CS, -+ cs | BCM2835_SPI_CS_TA | BCM2835_SPI_CS_DMAEN); -+ -+ /* setup rx-DMA late - to run transfers while -+ * mapping of the rx buffers still takes place -+ * this saves 10us or more. -+ */ -+ ret = bcm2835_spi_prepare_sg(master, tfr, false); -+ if (ret) { -+ /* need to reset on errors */ -+ dmaengine_terminate_all(master->dma_tx); -+ bcm2835_spi_reset_hw(master); -+ return ret; -+ } -+ -+ /* start rx dma late */ -+ dma_async_issue_pending(master->dma_rx); -+ -+ /* wait for wakeup in framework */ -+ return 1; -+} -+ -+static bool bcm2835_spi_can_dma(struct spi_master *master, -+ struct spi_device *spi, -+ struct spi_transfer *tfr) -+{ -+ /* only run for gpio_cs */ -+ if (!gpio_is_valid(spi->cs_gpio)) -+ return false; -+ -+ /* we start DMA efforts only on bigger transfers */ -+ if (tfr->len < BCM2835_SPI_DMA_MIN_LENGTH) -+ return false; -+ -+ /* BCM2835_SPI_DLEN has defined a max transfer size as -+ * 16 bit, so max is 65535 -+ * we can revisit this by using an alternative transfer -+ * method - ideally this would get done without any more -+ * interaction... -+ */ -+ if (tfr->len > 65535) { -+ dev_warn_once(&spi->dev, -+ "transfer size of %d too big for dma-transfer\n", -+ tfr->len); -+ return false; -+ } -+ -+ /* if we run rx/tx_buf with word aligned addresses then we are OK */ -+ if ((((size_t)tfr->rx_buf & 3) == 0) && -+ (((size_t)tfr->tx_buf & 3) == 0)) -+ return true; -+ -+ /* otherwise we only allow transfers within the same page -+ * to avoid wasting time on dma_mapping when it is not practical -+ */ -+ if (((size_t)tfr->tx_buf & (PAGE_SIZE - 1)) + tfr->len > PAGE_SIZE) { -+ dev_warn_once(&spi->dev, -+ "Unaligned spi tx-transfer bridging page\n"); -+ return false; -+ } -+ if (((size_t)tfr->rx_buf & (PAGE_SIZE - 1)) + tfr->len > PAGE_SIZE) { -+ dev_warn_once(&spi->dev, -+ "Unaligned spi rx-transfer bridging page\n"); -+ return false; -+ } -+ -+ /* return OK */ -+ return true; -+} -+ -+static void bcm2835_dma_release(struct spi_master *master) -+{ -+ if (master->dma_tx) { -+ dmaengine_terminate_all(master->dma_tx); -+ dma_release_channel(master->dma_tx); -+ master->dma_tx = NULL; -+ } -+ if (master->dma_rx) { -+ dmaengine_terminate_all(master->dma_rx); -+ dma_release_channel(master->dma_rx); -+ master->dma_rx = NULL; -+ } -+} -+ -+static void bcm2835_dma_init(struct spi_master *master, struct device *dev) -+{ -+ struct dma_slave_config slave_config; -+ const __be32 *addr; -+ dma_addr_t dma_reg_base; -+ int ret; -+ -+ /* base address in dma-space */ -+ addr = of_get_address(master->dev.of_node, 0, NULL, NULL); -+ if (!addr) { -+ dev_err(dev, "could not get DMA-register address - not using dma mode\n"); -+ goto err; -+ } -+ dma_reg_base = be32_to_cpup(addr); -+ -+ /* get tx/rx dma */ -+ master->dma_tx = dma_request_slave_channel(dev, "tx"); -+ if (!master->dma_tx) { -+ dev_err(dev, "no tx-dma configuration found - not using dma mode\n"); -+ goto err; -+ } -+ master->dma_rx = dma_request_slave_channel(dev, "rx"); -+ if (!master->dma_rx) { -+ dev_err(dev, "no rx-dma configuration found - not using dma mode\n"); -+ goto err_release; -+ } -+ -+ /* configure DMAs */ -+ slave_config.direction = DMA_MEM_TO_DEV; -+ slave_config.dst_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO); -+ slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; -+ -+ ret = dmaengine_slave_config(master->dma_tx, &slave_config); -+ if (ret) -+ goto err_config; -+ -+ slave_config.direction = DMA_DEV_TO_MEM; -+ slave_config.src_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO); -+ slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; -+ -+ ret = dmaengine_slave_config(master->dma_rx, &slave_config); -+ if (ret) -+ goto err_config; -+ -+ /* all went well, so set can_dma */ -+ master->can_dma = bcm2835_spi_can_dma; -+ master->max_dma_len = 65535; /* limitation by BCM2835_SPI_DLEN */ -+ /* need to do TX AND RX DMA, so we need dummy buffers */ -+ master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX; -+ -+ return; -+ -+err_config: -+ dev_err(dev, "issue configuring dma: %d - not using DMA mode\n", -+ ret); -+err_release: -+ bcm2835_dma_release(master); -+err: -+ return; -+} -+ -+static int bcm2835_spi_transfer_one_poll(struct spi_master *master, -+ struct spi_device *spi, -+ struct spi_transfer *tfr, -+ u32 cs, -+ unsigned long long xfer_time_us) -+{ -+ struct bcm2835_spi *bs = spi_master_get_devdata(master); -+ unsigned long timeout; -+ -+ /* enable HW block without interrupts */ -+ bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA); -+ -+ /* fill in the fifo before timeout calculations -+ * if we are interrupted here, then the data is -+ * getting transferred by the HW while we are interrupted -+ */ -+ bcm2835_wr_fifo(bs); -+ -+ /* set the timeout */ -+ timeout = jiffies + BCM2835_SPI_POLLING_JIFFIES; -+ -+ /* loop until finished the transfer */ -+ while (bs->rx_len) { -+ /* fill in tx fifo with remaining data */ -+ bcm2835_wr_fifo(bs); -+ -+ /* read from fifo as much as possible */ -+ bcm2835_rd_fifo(bs); -+ -+ /* if there is still data pending to read -+ * then check the timeout -+ */ -+ if (bs->rx_len && time_after(jiffies, timeout)) { -+ dev_dbg_ratelimited(&spi->dev, -+ "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n", -+ jiffies - timeout, -+ bs->tx_len, bs->rx_len); -+ /* fall back to interrupt mode */ -+ return bcm2835_spi_transfer_one_irq(master, spi, -+ tfr, cs); -+ } -+ } -+ -+ /* Transfer complete - reset SPI HW */ -+ bcm2835_spi_reset_hw(master); -+ /* and return without waiting for completion */ -+ return 0; -+} -+ - static int bcm2835_spi_transfer_one(struct spi_master *master, - struct spi_device *spi, - struct spi_transfer *tfr) - { - struct bcm2835_spi *bs = spi_master_get_devdata(master); - unsigned long spi_hz, clk_hz, cdiv; -- unsigned long spi_used_hz, xfer_time_us; -+ unsigned long spi_used_hz; -+ unsigned long long xfer_time_us; - u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); - - /* set clock */ -@@ -277,15 +574,21 @@ - bs->rx_len = tfr->len; - - /* calculate the estimated time in us the transfer runs */ -- xfer_time_us = tfr->len -+ xfer_time_us = (unsigned long long)tfr->len - * 9 /* clocks/byte - SPI-HW waits 1 clock after each byte */ -- * 1000000 / spi_used_hz; -+ * 1000000; -+ do_div(xfer_time_us, spi_used_hz); - - /* for short requests run polling*/ - if (xfer_time_us <= BCM2835_SPI_POLLING_LIMIT_US) - return bcm2835_spi_transfer_one_poll(master, spi, tfr, - cs, xfer_time_us); - -+ /* run in dma mode if conditions are right */ -+ if (master->can_dma && bcm2835_spi_can_dma(master, spi, tfr)) -+ return bcm2835_spi_transfer_one_dma(master, spi, tfr, cs); -+ -+ /* run in interrupt-mode */ - return bcm2835_spi_transfer_one_irq(master, spi, tfr, cs); - } - -@@ -311,6 +614,15 @@ - static void bcm2835_spi_handle_err(struct spi_master *master, - struct spi_message *msg) - { -+ struct bcm2835_spi *bs = spi_master_get_devdata(master); -+ -+ /* if an error occurred and we have an active dma, then terminate */ -+ if (bs->dma_pending) { -+ dmaengine_terminate_all(master->dma_tx); -+ dmaengine_terminate_all(master->dma_rx); -+ bs->dma_pending = 0; -+ } -+ /* and reset */ - bcm2835_spi_reset_hw(master); - } - -@@ -376,6 +688,8 @@ - { - int err; - struct gpio_chip *chip; -+ struct device_node *pins; -+ u32 pingroup_index; - /* - * sanity checking the native-chipselects - */ -@@ -392,15 +706,42 @@ - "setup: only two native chip-selects are supported\n"); - return -EINVAL; - } -- /* now translate native cs to GPIO */ - -- /* get the gpio chip for the base */ -- chip = gpiochip_find("pinctrl-bcm2835", chip_match_name); -- if (!chip) -- return 0; -+ /* now translate native cs to GPIO */ -+ /* first look for chip select pins in the devices pin groups */ -+ for (pingroup_index = 0; -+ (pins = of_parse_phandle(spi->master->dev.of_node, -+ "pinctrl-0", -+ pingroup_index)) != 0; -+ pingroup_index++) { -+ u32 pin; -+ u32 pin_index; -+ for (pin_index = 0; -+ of_property_read_u32_index(pins, -+ "brcm,pins", -+ pin_index, -+ &pin) == 0; -+ pin_index++) { -+ if (((spi->chip_select == 0) && -+ ((pin == 8) || (pin == 36) || (pin == 46))) || -+ ((spi->chip_select == 1) && -+ ((pin == 7) || (pin == 35)))) { -+ spi->cs_gpio = pin; -+ break; -+ } -+ } -+ of_node_put(pins); -+ } -+ /* if that fails, assume GPIOs 7-11 are used */ -+ if (!gpio_is_valid(spi->cs_gpio) ) { -+ /* get the gpio chip for the base */ -+ chip = gpiochip_find("pinctrl-bcm2835", chip_match_name); -+ if (!chip) -+ return 0; - -- /* and calculate the real CS */ -- spi->cs_gpio = chip->base + 8 - spi->chip_select; -+ /* and calculate the real CS */ -+ spi->cs_gpio = chip->base + 8 - spi->chip_select; -+ } - - /* and set up the "mode" and level */ - dev_info(&spi->dev, "setting up native-CS%i as GPIO %i\n", -@@ -481,6 +822,8 @@ - goto out_clk_disable; - } - -+ bcm2835_dma_init(master, &pdev->dev); -+ - /* initialise the hardware with the default polarities */ - bcm2835_wr(bs, BCM2835_SPI_CS, - BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX); -@@ -511,6 +854,8 @@ - - clk_disable_unprepare(bs->clk); - -+ bcm2835_dma_release(master); -+ - return 0; - } - -diff -Nur linux-4.1.13.orig/drivers/spi/spidev.c linux-rpi/drivers/spi/spidev.c ---- linux-4.1.13.orig/drivers/spi/spidev.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/spi/spidev.c 2015-11-29 09:42:39.447130054 +0100 -@@ -707,6 +707,7 @@ - #ifdef CONFIG_OF - static const struct of_device_id spidev_dt_ids[] = { - { .compatible = "rohm,dh2228fv" }, -+ { .compatible = "spidev" }, - {}, - }; - MODULE_DEVICE_TABLE(of, spidev_dt_ids); -diff -Nur linux-4.1.13.orig/drivers/staging/fbtft/fbtft-core.c linux-rpi/drivers/staging/fbtft/fbtft-core.c ---- linux-4.1.13.orig/drivers/staging/fbtft/fbtft-core.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/staging/fbtft/fbtft-core.c 2015-11-29 09:42:39.491127130 +0100 -@@ -1074,6 +1074,11 @@ - p = of_prop_next_u32(prop, NULL, &val); - if (!p) - return -EINVAL; -+ -+ par->fbtftops.reset(par); -+ if (par->gpio.cs != -1) -+ gpio_set_value(par->gpio.cs, 0); /* Activate chip */ -+ - while (p) { - if (val & FBTFT_OF_INIT_CMD) { - val &= 0xFFFF; -diff -Nur linux-4.1.13.orig/drivers/staging/media/lirc/Kconfig linux-rpi/drivers/staging/media/lirc/Kconfig ---- linux-4.1.13.orig/drivers/staging/media/lirc/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/staging/media/lirc/Kconfig 2015-11-29 09:42:39.643117031 +0100 -@@ -32,6 +32,12 @@ - help - Driver for Homebrew Parallel Port Receivers - -+config LIRC_RPI -+ tristate "Homebrew GPIO Port Receiver/Transmitter for the RaspberryPi" -+ depends on LIRC -+ help -+ Driver for Homebrew GPIO Port Receiver/Transmitter for the RaspberryPi -+ - config LIRC_SASEM - tristate "Sasem USB IR Remote" - depends on LIRC && USB -diff -Nur linux-4.1.13.orig/drivers/staging/media/lirc/lirc_rpi.c linux-rpi/drivers/staging/media/lirc/lirc_rpi.c ---- linux-4.1.13.orig/drivers/staging/media/lirc/lirc_rpi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/staging/media/lirc/lirc_rpi.c 2015-11-29 09:42:39.643117031 +0100 -@@ -0,0 +1,765 @@ -+/* -+ * lirc_rpi.c -+ * -+ * lirc_rpi - Device driver that records pulse- and pause-lengths -+ * (space-lengths) (just like the lirc_serial driver does) -+ * between GPIO interrupt events on the Raspberry Pi. -+ * Lots of code has been taken from the lirc_serial module, -+ * so I would like say thanks to the authors. -+ * -+ * Copyright (C) 2012 Aron Robert Szabo , -+ * Michael Bishop -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#define LIRC_DRIVER_NAME "lirc_rpi" -+#define RBUF_LEN 256 -+#define LIRC_TRANSMITTER_LATENCY 50 -+ -+#ifndef MAX_UDELAY_MS -+#define MAX_UDELAY_US 5000 -+#else -+#define MAX_UDELAY_US (MAX_UDELAY_MS*1000) -+#endif -+ -+#define dprintk(fmt, args...) \ -+ do { \ -+ if (debug) \ -+ printk(KERN_DEBUG LIRC_DRIVER_NAME ": " \ -+ fmt, ## args); \ -+ } while (0) -+ -+/* module parameters */ -+ -+/* set the default GPIO input pin */ -+static int gpio_in_pin = 18; -+/* set the default pull behaviour for input pin */ -+static int gpio_in_pull = BCM2708_PULL_DOWN; -+/* set the default GPIO output pin */ -+static int gpio_out_pin = 17; -+/* enable debugging messages */ -+static bool debug; -+/* -1 = auto, 0 = active high, 1 = active low */ -+static int sense = -1; -+/* use softcarrier by default */ -+static bool softcarrier = 1; -+/* 0 = do not invert output, 1 = invert output */ -+static bool invert = 0; -+ -+struct gpio_chip *gpiochip; -+static int irq_num; -+ -+/* forward declarations */ -+static long send_pulse(unsigned long length); -+static void send_space(long length); -+static void lirc_rpi_exit(void); -+ -+static struct platform_device *lirc_rpi_dev; -+static struct timeval lasttv = { 0, 0 }; -+static struct lirc_buffer rbuf; -+static spinlock_t lock; -+ -+/* initialized/set in init_timing_params() */ -+static unsigned int freq = 38000; -+static unsigned int duty_cycle = 50; -+static unsigned long period; -+static unsigned long pulse_width; -+static unsigned long space_width; -+ -+static void safe_udelay(unsigned long usecs) -+{ -+ while (usecs > MAX_UDELAY_US) { -+ udelay(MAX_UDELAY_US); -+ usecs -= MAX_UDELAY_US; -+ } -+ udelay(usecs); -+} -+ -+static unsigned long read_current_us(void) -+{ -+ struct timespec now; -+ getnstimeofday(&now); -+ return (now.tv_sec * 1000000) + (now.tv_nsec/1000); -+} -+ -+static int init_timing_params(unsigned int new_duty_cycle, -+ unsigned int new_freq) -+{ -+ if (1000 * 1000000L / new_freq * new_duty_cycle / 100 <= -+ LIRC_TRANSMITTER_LATENCY) -+ return -EINVAL; -+ if (1000 * 1000000L / new_freq * (100 - new_duty_cycle) / 100 <= -+ LIRC_TRANSMITTER_LATENCY) -+ return -EINVAL; -+ duty_cycle = new_duty_cycle; -+ freq = new_freq; -+ period = 1000 * 1000000L / freq; -+ pulse_width = period * duty_cycle / 100; -+ space_width = period - pulse_width; -+ dprintk("in init_timing_params, freq=%d pulse=%ld, " -+ "space=%ld\n", freq, pulse_width, space_width); -+ return 0; -+} -+ -+static long send_pulse_softcarrier(unsigned long length) -+{ -+ int flag; -+ unsigned long actual, target; -+ unsigned long actual_us, initial_us, target_us; -+ -+ length *= 1000; -+ -+ actual = 0; target = 0; flag = 0; -+ actual_us = read_current_us(); -+ -+ while (actual < length) { -+ if (flag) { -+ gpiochip->set(gpiochip, gpio_out_pin, invert); -+ target += space_width; -+ } else { -+ gpiochip->set(gpiochip, gpio_out_pin, !invert); -+ target += pulse_width; -+ } -+ initial_us = actual_us; -+ target_us = actual_us + (target - actual) / 1000; -+ /* -+ * Note - we've checked in ioctl that the pulse/space -+ * widths are big enough so that d is > 0 -+ */ -+ if ((int)(target_us - actual_us) > 0) -+ udelay(target_us - actual_us); -+ actual_us = read_current_us(); -+ actual += (actual_us - initial_us) * 1000; -+ flag = !flag; -+ } -+ return (actual-length) / 1000; -+} -+ -+static long send_pulse(unsigned long length) -+{ -+ if (length <= 0) -+ return 0; -+ -+ if (softcarrier) { -+ return send_pulse_softcarrier(length); -+ } else { -+ gpiochip->set(gpiochip, gpio_out_pin, !invert); -+ safe_udelay(length); -+ return 0; -+ } -+} -+ -+static void send_space(long length) -+{ -+ gpiochip->set(gpiochip, gpio_out_pin, invert); -+ if (length <= 0) -+ return; -+ safe_udelay(length); -+} -+ -+static void rbwrite(int l) -+{ -+ if (lirc_buffer_full(&rbuf)) { -+ /* no new signals will be accepted */ -+ dprintk("Buffer overrun\n"); -+ return; -+ } -+ lirc_buffer_write(&rbuf, (void *)&l); -+} -+ -+static void frbwrite(int l) -+{ -+ /* simple noise filter */ -+ static int pulse, space; -+ static unsigned int ptr; -+ -+ if (ptr > 0 && (l & PULSE_BIT)) { -+ pulse += l & PULSE_MASK; -+ if (pulse > 250) { -+ rbwrite(space); -+ rbwrite(pulse | PULSE_BIT); -+ ptr = 0; -+ pulse = 0; -+ } -+ return; -+ } -+ if (!(l & PULSE_BIT)) { -+ if (ptr == 0) { -+ if (l > 20000) { -+ space = l; -+ ptr++; -+ return; -+ } -+ } else { -+ if (l > 20000) { -+ space += pulse; -+ if (space > PULSE_MASK) -+ space = PULSE_MASK; -+ space += l; -+ if (space > PULSE_MASK) -+ space = PULSE_MASK; -+ pulse = 0; -+ return; -+ } -+ rbwrite(space); -+ rbwrite(pulse | PULSE_BIT); -+ ptr = 0; -+ pulse = 0; -+ } -+ } -+ rbwrite(l); -+} -+ -+static irqreturn_t irq_handler(int i, void *blah, struct pt_regs *regs) -+{ -+ struct timeval tv; -+ long deltv; -+ int data; -+ int signal; -+ -+ /* use the GPIO signal level */ -+ signal = gpiochip->get(gpiochip, gpio_in_pin); -+ -+ if (sense != -1) { -+ /* get current time */ -+ do_gettimeofday(&tv); -+ -+ /* calc time since last interrupt in microseconds */ -+ deltv = tv.tv_sec-lasttv.tv_sec; -+ if (tv.tv_sec < lasttv.tv_sec || -+ (tv.tv_sec == lasttv.tv_sec && -+ tv.tv_usec < lasttv.tv_usec)) { -+ printk(KERN_WARNING LIRC_DRIVER_NAME -+ ": AIEEEE: your clock just jumped backwards\n"); -+ printk(KERN_WARNING LIRC_DRIVER_NAME -+ ": %d %d %lx %lx %lx %lx\n", signal, sense, -+ tv.tv_sec, lasttv.tv_sec, -+ tv.tv_usec, lasttv.tv_usec); -+ data = PULSE_MASK; -+ } else if (deltv > 15) { -+ data = PULSE_MASK; /* really long time */ -+ if (!(signal^sense)) { -+ /* sanity check */ -+ printk(KERN_WARNING LIRC_DRIVER_NAME -+ ": AIEEEE: %d %d %lx %lx %lx %lx\n", -+ signal, sense, tv.tv_sec, lasttv.tv_sec, -+ tv.tv_usec, lasttv.tv_usec); -+ /* -+ * detecting pulse while this -+ * MUST be a space! -+ */ -+ sense = sense ? 0 : 1; -+ } -+ } else { -+ data = (int) (deltv*1000000 + -+ (tv.tv_usec - lasttv.tv_usec)); -+ } -+ frbwrite(signal^sense ? data : (data|PULSE_BIT)); -+ lasttv = tv; -+ wake_up_interruptible(&rbuf.wait_poll); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+static int is_right_chip(struct gpio_chip *chip, void *data) -+{ -+ dprintk("is_right_chip %s %d\n", chip->label, strcmp(data, chip->label)); -+ -+ if (strcmp(data, chip->label) == 0) -+ return 1; -+ return 0; -+} -+ -+static inline int read_bool_property(const struct device_node *np, -+ const char *propname, -+ bool *out_value) -+{ -+ u32 value = 0; -+ int err = of_property_read_u32(np, propname, &value); -+ if (err == 0) -+ *out_value = (value != 0); -+ return err; -+} -+ -+static void read_pin_settings(struct device_node *node) -+{ -+ u32 pin; -+ int index; -+ -+ for (index = 0; -+ of_property_read_u32_index( -+ node, -+ "brcm,pins", -+ index, -+ &pin) == 0; -+ index++) { -+ u32 function; -+ int err; -+ err = of_property_read_u32_index( -+ node, -+ "brcm,function", -+ index, -+ &function); -+ if (err == 0) { -+ if (function == 1) /* Output */ -+ gpio_out_pin = pin; -+ else if (function == 0) /* Input */ -+ gpio_in_pin = pin; -+ } -+ } -+} -+ -+static int init_port(void) -+{ -+ int i, nlow, nhigh, ret; -+ struct device_node *node; -+ -+ node = lirc_rpi_dev->dev.of_node; -+ -+ gpiochip = gpiochip_find("bcm2708_gpio", is_right_chip); -+ -+ /* -+ * Because of the lack of a setpull function, only support -+ * pinctrl-bcm2835 if using device tree. -+ */ -+ if (!gpiochip && node) -+ gpiochip = gpiochip_find("pinctrl-bcm2835", is_right_chip); -+ -+ if (!gpiochip) { -+ pr_err(LIRC_DRIVER_NAME ": gpio chip not found!\n"); -+ return -ENODEV; -+ } -+ -+ if (node) { -+ struct device_node *pins_node; -+ -+ pins_node = of_parse_phandle(node, "pinctrl-0", 0); -+ if (!pins_node) { -+ printk(KERN_ERR LIRC_DRIVER_NAME -+ ": pinctrl settings not found!\n"); -+ ret = -EINVAL; -+ goto exit_init_port; -+ } -+ -+ read_pin_settings(pins_node); -+ -+ of_property_read_u32(node, "rpi,sense", &sense); -+ -+ read_bool_property(node, "rpi,softcarrier", &softcarrier); -+ -+ read_bool_property(node, "rpi,invert", &invert); -+ -+ read_bool_property(node, "rpi,debug", &debug); -+ -+ } -+ else -+ { -+ if (gpio_in_pin >= BCM2708_NR_GPIOS || -+ gpio_out_pin >= BCM2708_NR_GPIOS) { -+ ret = -EINVAL; -+ printk(KERN_ERR LIRC_DRIVER_NAME -+ ": invalid GPIO pin(s) specified!\n"); -+ goto exit_init_port; -+ } -+ -+ if (gpio_request(gpio_out_pin, LIRC_DRIVER_NAME " ir/out")) { -+ printk(KERN_ALERT LIRC_DRIVER_NAME -+ ": cant claim gpio pin %d\n", gpio_out_pin); -+ ret = -ENODEV; -+ goto exit_init_port; -+ } -+ -+ if (gpio_request(gpio_in_pin, LIRC_DRIVER_NAME " ir/in")) { -+ printk(KERN_ALERT LIRC_DRIVER_NAME -+ ": cant claim gpio pin %d\n", gpio_in_pin); -+ ret = -ENODEV; -+ goto exit_gpio_free_out_pin; -+ } -+ -+ bcm2708_gpio_setpull(gpiochip, gpio_in_pin, gpio_in_pull); -+ gpiochip->direction_input(gpiochip, gpio_in_pin); -+ gpiochip->direction_output(gpiochip, gpio_out_pin, 1); -+ } -+ -+ gpiochip->set(gpiochip, gpio_out_pin, invert); -+ -+ irq_num = gpiochip->to_irq(gpiochip, gpio_in_pin); -+ dprintk("to_irq %d\n", irq_num); -+ -+ /* if pin is high, then this must be an active low receiver. */ -+ if (sense == -1) { -+ /* wait 1/2 sec for the power supply */ -+ msleep(500); -+ -+ /* -+ * probe 9 times every 0.04s, collect "votes" for -+ * active high/low -+ */ -+ nlow = 0; -+ nhigh = 0; -+ for (i = 0; i < 9; i++) { -+ if (gpiochip->get(gpiochip, gpio_in_pin)) -+ nlow++; -+ else -+ nhigh++; -+ msleep(40); -+ } -+ sense = (nlow >= nhigh ? 1 : 0); -+ printk(KERN_INFO LIRC_DRIVER_NAME -+ ": auto-detected active %s receiver on GPIO pin %d\n", -+ sense ? "low" : "high", gpio_in_pin); -+ } else { -+ printk(KERN_INFO LIRC_DRIVER_NAME -+ ": manually using active %s receiver on GPIO pin %d\n", -+ sense ? "low" : "high", gpio_in_pin); -+ } -+ -+ return 0; -+ -+ exit_gpio_free_out_pin: -+ gpio_free(gpio_out_pin); -+ -+ exit_init_port: -+ return ret; -+} -+ -+// called when the character device is opened -+static int set_use_inc(void *data) -+{ -+ int result; -+ -+ /* initialize timestamp */ -+ do_gettimeofday(&lasttv); -+ -+ result = request_irq(irq_num, -+ (irq_handler_t) irq_handler, -+ IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING, -+ LIRC_DRIVER_NAME, (void*) 0); -+ -+ switch (result) { -+ case -EBUSY: -+ printk(KERN_ERR LIRC_DRIVER_NAME -+ ": IRQ %d is busy\n", -+ irq_num); -+ return -EBUSY; -+ case -EINVAL: -+ printk(KERN_ERR LIRC_DRIVER_NAME -+ ": Bad irq number or handler\n"); -+ return -EINVAL; -+ default: -+ dprintk("Interrupt %d obtained\n", -+ irq_num); -+ break; -+ }; -+ -+ /* initialize pulse/space widths */ -+ init_timing_params(duty_cycle, freq); -+ -+ return 0; -+} -+ -+static void set_use_dec(void *data) -+{ -+ /* GPIO Pin Falling/Rising Edge Detect Disable */ -+ irq_set_irq_type(irq_num, 0); -+ disable_irq(irq_num); -+ -+ free_irq(irq_num, (void *) 0); -+ -+ dprintk(KERN_INFO LIRC_DRIVER_NAME -+ ": freed IRQ %d\n", irq_num); -+} -+ -+static ssize_t lirc_write(struct file *file, const char *buf, -+ size_t n, loff_t *ppos) -+{ -+ int i, count; -+ unsigned long flags; -+ long delta = 0; -+ int *wbuf; -+ -+ count = n / sizeof(int); -+ if (n % sizeof(int) || count % 2 == 0) -+ return -EINVAL; -+ wbuf = memdup_user(buf, n); -+ if (IS_ERR(wbuf)) -+ return PTR_ERR(wbuf); -+ spin_lock_irqsave(&lock, flags); -+ -+ for (i = 0; i < count; i++) { -+ if (i%2) -+ send_space(wbuf[i] - delta); -+ else -+ delta = send_pulse(wbuf[i]); -+ } -+ gpiochip->set(gpiochip, gpio_out_pin, invert); -+ -+ spin_unlock_irqrestore(&lock, flags); -+ kfree(wbuf); -+ return n; -+} -+ -+static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) -+{ -+ int result; -+ __u32 value; -+ -+ switch (cmd) { -+ case LIRC_GET_SEND_MODE: -+ return -ENOIOCTLCMD; -+ break; -+ -+ case LIRC_SET_SEND_MODE: -+ result = get_user(value, (__u32 *) arg); -+ if (result) -+ return result; -+ /* only LIRC_MODE_PULSE supported */ -+ if (value != LIRC_MODE_PULSE) -+ return -ENOSYS; -+ break; -+ -+ case LIRC_GET_LENGTH: -+ return -ENOSYS; -+ break; -+ -+ case LIRC_SET_SEND_DUTY_CYCLE: -+ dprintk("SET_SEND_DUTY_CYCLE\n"); -+ result = get_user(value, (__u32 *) arg); -+ if (result) -+ return result; -+ if (value <= 0 || value > 100) -+ return -EINVAL; -+ return init_timing_params(value, freq); -+ break; -+ -+ case LIRC_SET_SEND_CARRIER: -+ dprintk("SET_SEND_CARRIER\n"); -+ result = get_user(value, (__u32 *) arg); -+ if (result) -+ return result; -+ if (value > 500000 || value < 20000) -+ return -EINVAL; -+ return init_timing_params(duty_cycle, value); -+ break; -+ -+ default: -+ return lirc_dev_fop_ioctl(filep, cmd, arg); -+ } -+ return 0; -+} -+ -+static const struct file_operations lirc_fops = { -+ .owner = THIS_MODULE, -+ .write = lirc_write, -+ .unlocked_ioctl = lirc_ioctl, -+ .read = lirc_dev_fop_read, -+ .poll = lirc_dev_fop_poll, -+ .open = lirc_dev_fop_open, -+ .release = lirc_dev_fop_close, -+ .llseek = no_llseek, -+}; -+ -+static struct lirc_driver driver = { -+ .name = LIRC_DRIVER_NAME, -+ .minor = -1, -+ .code_length = 1, -+ .sample_rate = 0, -+ .data = NULL, -+ .add_to_buf = NULL, -+ .rbuf = &rbuf, -+ .set_use_inc = set_use_inc, -+ .set_use_dec = set_use_dec, -+ .fops = &lirc_fops, -+ .dev = NULL, -+ .owner = THIS_MODULE, -+}; -+ -+static const struct of_device_id lirc_rpi_of_match[] = { -+ { .compatible = "rpi,lirc-rpi", }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, lirc_rpi_of_match); -+ -+static struct platform_driver lirc_rpi_driver = { -+ .driver = { -+ .name = LIRC_DRIVER_NAME, -+ .owner = THIS_MODULE, -+ .of_match_table = of_match_ptr(lirc_rpi_of_match), -+ }, -+}; -+ -+static int __init lirc_rpi_init(void) -+{ -+ struct device_node *node; -+ int result; -+ -+ /* Init read buffer. */ -+ result = lirc_buffer_init(&rbuf, sizeof(int), RBUF_LEN); -+ if (result < 0) -+ return -ENOMEM; -+ -+ result = platform_driver_register(&lirc_rpi_driver); -+ if (result) { -+ printk(KERN_ERR LIRC_DRIVER_NAME -+ ": lirc register returned %d\n", result); -+ goto exit_buffer_free; -+ } -+ -+ node = of_find_compatible_node(NULL, NULL, -+ lirc_rpi_of_match[0].compatible); -+ -+ if (node) { -+ /* DT-enabled */ -+ lirc_rpi_dev = of_find_device_by_node(node); -+ WARN_ON(lirc_rpi_dev->dev.of_node != node); -+ of_node_put(node); -+ } -+ else { -+ lirc_rpi_dev = platform_device_alloc(LIRC_DRIVER_NAME, 0); -+ if (!lirc_rpi_dev) { -+ result = -ENOMEM; -+ goto exit_driver_unregister; -+ } -+ -+ result = platform_device_add(lirc_rpi_dev); -+ if (result) -+ goto exit_device_put; -+ } -+ -+ return 0; -+ -+ exit_device_put: -+ platform_device_put(lirc_rpi_dev); -+ -+ exit_driver_unregister: -+ platform_driver_unregister(&lirc_rpi_driver); -+ -+ exit_buffer_free: -+ lirc_buffer_free(&rbuf); -+ -+ return result; -+} -+ -+static void lirc_rpi_exit(void) -+{ -+ if (!lirc_rpi_dev->dev.of_node) -+ platform_device_unregister(lirc_rpi_dev); -+ platform_driver_unregister(&lirc_rpi_driver); -+ lirc_buffer_free(&rbuf); -+} -+ -+static int __init lirc_rpi_init_module(void) -+{ -+ int result; -+ -+ result = lirc_rpi_init(); -+ if (result) -+ return result; -+ -+ result = init_port(); -+ if (result < 0) -+ goto exit_rpi; -+ -+ driver.features = LIRC_CAN_SET_SEND_DUTY_CYCLE | -+ LIRC_CAN_SET_SEND_CARRIER | -+ LIRC_CAN_SEND_PULSE | -+ LIRC_CAN_REC_MODE2; -+ -+ driver.dev = &lirc_rpi_dev->dev; -+ driver.minor = lirc_register_driver(&driver); -+ -+ if (driver.minor < 0) { -+ printk(KERN_ERR LIRC_DRIVER_NAME -+ ": device registration failed with %d\n", result); -+ result = -EIO; -+ goto exit_rpi; -+ } -+ -+ printk(KERN_INFO LIRC_DRIVER_NAME ": driver registered!\n"); -+ -+ return 0; -+ -+ exit_rpi: -+ lirc_rpi_exit(); -+ -+ return result; -+} -+ -+static void __exit lirc_rpi_exit_module(void) -+{ -+ lirc_unregister_driver(driver.minor); -+ -+ gpio_free(gpio_out_pin); -+ gpio_free(gpio_in_pin); -+ -+ lirc_rpi_exit(); -+ -+ printk(KERN_INFO LIRC_DRIVER_NAME ": cleaned up module\n"); -+} -+ -+module_init(lirc_rpi_init_module); -+module_exit(lirc_rpi_exit_module); -+ -+MODULE_DESCRIPTION("Infra-red receiver and blaster driver for Raspberry Pi GPIO."); -+MODULE_AUTHOR("Aron Robert Szabo "); -+MODULE_AUTHOR("Michael Bishop "); -+MODULE_LICENSE("GPL"); -+ -+module_param(gpio_out_pin, int, S_IRUGO); -+MODULE_PARM_DESC(gpio_out_pin, "GPIO output/transmitter pin number of the BCM" -+ " processor. (default 17"); -+ -+module_param(gpio_in_pin, int, S_IRUGO); -+MODULE_PARM_DESC(gpio_in_pin, "GPIO input pin number of the BCM processor." -+ " (default 18"); -+ -+module_param(gpio_in_pull, int, S_IRUGO); -+MODULE_PARM_DESC(gpio_in_pull, "GPIO input pin pull configuration." -+ " (0 = off, 1 = up, 2 = down, default down)"); -+ -+module_param(sense, int, S_IRUGO); -+MODULE_PARM_DESC(sense, "Override autodetection of IR receiver circuit" -+ " (0 = active high, 1 = active low )"); -+ -+module_param(softcarrier, bool, S_IRUGO); -+MODULE_PARM_DESC(softcarrier, "Software carrier (0 = off, 1 = on, default on)"); -+ -+module_param(invert, bool, S_IRUGO); -+MODULE_PARM_DESC(invert, "Invert output (0 = off, 1 = on, default off"); -+ -+module_param(debug, bool, S_IRUGO | S_IWUSR); -+MODULE_PARM_DESC(debug, "Enable debugging messages"); -diff -Nur linux-4.1.13.orig/drivers/staging/media/lirc/Makefile linux-rpi/drivers/staging/media/lirc/Makefile ---- linux-4.1.13.orig/drivers/staging/media/lirc/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/staging/media/lirc/Makefile 2015-11-29 09:42:39.643117031 +0100 -@@ -6,6 +6,7 @@ - obj-$(CONFIG_LIRC_BT829) += lirc_bt829.o - obj-$(CONFIG_LIRC_IMON) += lirc_imon.o - obj-$(CONFIG_LIRC_PARALLEL) += lirc_parallel.o -+obj-$(CONFIG_LIRC_RPI) += lirc_rpi.o - obj-$(CONFIG_LIRC_SASEM) += lirc_sasem.o - obj-$(CONFIG_LIRC_SERIAL) += lirc_serial.o - obj-$(CONFIG_LIRC_SIR) += lirc_sir.o -diff -Nur linux-4.1.13.orig/drivers/thermal/bcm2835-thermal.c linux-rpi/drivers/thermal/bcm2835-thermal.c ---- linux-4.1.13.orig/drivers/thermal/bcm2835-thermal.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/thermal/bcm2835-thermal.c 2015-11-29 09:42:39.795106932 +0100 -@@ -0,0 +1,141 @@ -+/***************************************************************************** -+* Copyright 2011 Broadcom Corporation. All rights reserved. -+* -+* Unless you and Broadcom execute a separate written software license -+* agreement governing use of this software, this software is licensed to you -+* under the terms of the GNU General Public License version 2, available at -+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -+* -+* Notwithstanding the above, under no circumstances may you combine this -+* software in any way with any other Broadcom software provided under a -+* license other than the GPL, without Broadcom's express prior written -+* consent. -+*****************************************************************************/ -+ -+#include -+#include -+#include -+#include -+ -+static int bcm2835_thermal_get_property(struct thermal_zone_device *tz, -+ unsigned long *temp, u32 tag) -+{ -+ struct rpi_firmware *fw = tz->devdata; -+ struct { -+ u32 id; -+ u32 val; -+ } packet; -+ int ret; -+ -+ *temp = 0; -+ packet.id = 0; -+ ret = rpi_firmware_property(fw, tag, &packet, sizeof(packet)); -+ if (ret) { -+ dev_err(&tz->device, "Failed to get temperature\n"); -+ return ret; -+ } -+ -+ *temp = packet.val; -+ dev_dbg(&tz->device, "%stemp=%lu\n", -+ tag == RPI_FIRMWARE_GET_MAX_TEMPERATURE ? "max" : "", *temp); -+ -+ return 0; -+} -+ -+static int bcm2835_thermal_get_temp(struct thermal_zone_device *tz, -+ unsigned long *temp) -+{ -+ return bcm2835_thermal_get_property(tz, temp, -+ RPI_FIRMWARE_GET_TEMPERATURE); -+} -+ -+static int bcm2835_thermal_get_max_temp(struct thermal_zone_device *tz, -+ int trip, unsigned long *temp) -+{ -+ /* -+ * The maximum safe temperature of the SoC. -+ * Overclock may be disabled above this temperature. -+ */ -+ return bcm2835_thermal_get_property(tz, temp, -+ RPI_FIRMWARE_GET_MAX_TEMPERATURE); -+} -+ -+static int bcm2835_thermal_get_trip_type(struct thermal_zone_device *tz, -+ int trip, enum thermal_trip_type *type) -+{ -+ *type = THERMAL_TRIP_HOT; -+ -+ return 0; -+} -+ -+static int bcm2835_thermal_get_mode(struct thermal_zone_device *tz, -+ enum thermal_device_mode *mode) -+{ -+ *mode = THERMAL_DEVICE_ENABLED; -+ -+ return 0; -+} -+ -+static struct thermal_zone_device_ops ops = { -+ .get_temp = bcm2835_thermal_get_temp, -+ .get_trip_temp = bcm2835_thermal_get_max_temp, -+ .get_trip_type = bcm2835_thermal_get_trip_type, -+ .get_mode = bcm2835_thermal_get_mode, -+}; -+ -+static int bcm2835_thermal_probe(struct platform_device *pdev) -+{ -+ struct device_node *fw_np; -+ struct rpi_firmware *fw; -+ struct thermal_zone_device *tz; -+ -+ fw_np = of_parse_phandle(pdev->dev.of_node, "firmware", 0); -+/* Remove comment when booting without Device Tree is no longer supported -+ if (!fw_np) { -+ dev_err(&pdev->dev, "Missing firmware node\n"); -+ return -ENOENT; -+ } -+*/ -+ fw = rpi_firmware_get(fw_np); -+ if (!fw) -+ return -EPROBE_DEFER; -+ -+ tz = thermal_zone_device_register("bcm2835_thermal", 1, 0, fw, &ops, -+ NULL, 0, 0); -+ if (IS_ERR(tz)) { -+ dev_err(&pdev->dev, "Failed to register the thermal device\n"); -+ return PTR_ERR(tz); -+ } -+ -+ platform_set_drvdata(pdev, tz); -+ -+ return 0; -+} -+ -+static int bcm2835_thermal_remove(struct platform_device *pdev) -+{ -+ thermal_zone_device_unregister(platform_get_drvdata(pdev)); -+ -+ return 0; -+} -+ -+static const struct of_device_id bcm2835_thermal_of_match_table[] = { -+ { .compatible = "brcm,bcm2835-thermal", }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, bcm2835_thermal_of_match_table); -+ -+static struct platform_driver bcm2835_thermal_driver = { -+ .probe = bcm2835_thermal_probe, -+ .remove = bcm2835_thermal_remove, -+ .driver = { -+ .name = "bcm2835_thermal", -+ .of_match_table = bcm2835_thermal_of_match_table, -+ }, -+}; -+module_platform_driver(bcm2835_thermal_driver); -+ -+MODULE_AUTHOR("Dorian Peake"); -+MODULE_AUTHOR("Noralf Trønnes"); -+MODULE_DESCRIPTION("Thermal driver for bcm2835 chip"); -+MODULE_LICENSE("GPL"); -diff -Nur linux-4.1.13.orig/drivers/thermal/Kconfig linux-rpi/drivers/thermal/Kconfig ---- linux-4.1.13.orig/drivers/thermal/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/thermal/Kconfig 2015-11-29 09:42:39.795106932 +0100 -@@ -238,6 +238,13 @@ - enforce idle time which results in more package C-state residency. The - user interface is exposed via generic thermal framework. - -+config THERMAL_BCM2835 -+ depends on RASPBERRYPI_FIRMWARE -+ tristate "BCM2835 Thermal Driver" -+ help -+ This will enable temperature monitoring for the Broadcom BCM2835 -+ chip. If built as a module, it will be called 'bcm2835-thermal'. -+ - config X86_PKG_TEMP_THERMAL - tristate "X86 package temperature thermal driver" - depends on X86_THERMAL_VECTOR -diff -Nur linux-4.1.13.orig/drivers/thermal/Makefile linux-rpi/drivers/thermal/Makefile ---- linux-4.1.13.orig/drivers/thermal/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/thermal/Makefile 2015-11-29 09:42:39.795106932 +0100 -@@ -33,6 +33,7 @@ - obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o - obj-$(CONFIG_DB8500_CPUFREQ_COOLING) += db8500_cpufreq_cooling.o - obj-$(CONFIG_INTEL_POWERCLAMP) += intel_powerclamp.o -+obj-$(CONFIG_THERMAL_BCM2835) += bcm2835-thermal.o - obj-$(CONFIG_X86_PKG_TEMP_THERMAL) += x86_pkg_temp_thermal.o - obj-$(CONFIG_INTEL_SOC_DTS_THERMAL) += intel_soc_dts_thermal.o - obj-$(CONFIG_TI_SOC_THERMAL) += ti-soc-thermal/ -diff -Nur linux-4.1.13.orig/drivers/tty/serial/8250/8250_core.c linux-rpi/drivers/tty/serial/8250/8250_core.c ---- linux-4.1.13.orig/drivers/tty/serial/8250/8250_core.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/tty/serial/8250/8250_core.c 2015-11-29 09:42:39.811105869 +0100 -@@ -3270,6 +3270,8 @@ - - if (nr_uarts > UART_NR) - nr_uarts = UART_NR; -+ if (!nr_uarts) -+ return; - - for (i = 0; i < nr_uarts; i++) { - struct uart_8250_port *up = &serial8250_ports[i]; -diff -Nur linux-4.1.13.orig/drivers/tty/serial/amba-pl011.c linux-rpi/drivers/tty/serial/amba-pl011.c ---- linux-4.1.13.orig/drivers/tty/serial/amba-pl011.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/tty/serial/amba-pl011.c 2015-11-29 09:42:39.815105604 +0100 -@@ -85,7 +85,7 @@ - - static unsigned int get_fifosize_arm(struct amba_device *dev) - { -- return amba_rev(dev) < 3 ? 16 : 32; -+ return 16; //TODO: fix: amba_rev(dev) < 3 ? 16 : 32; - } - - static struct vendor_data vendor_arm = { -diff -Nur linux-4.1.13.orig/drivers/usb/core/generic.c linux-rpi/drivers/usb/core/generic.c ---- linux-4.1.13.orig/drivers/usb/core/generic.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/usb/core/generic.c 2015-11-29 09:42:39.871101883 +0100 -@@ -152,6 +152,7 @@ - dev_warn(&udev->dev, - "no configuration chosen from %d choice%s\n", - num_configs, plural(num_configs)); -+ dev_warn(&udev->dev, "No support over %dmA\n", udev->bus_mA); - } - return i; - } -diff -Nur linux-4.1.13.orig/drivers/usb/core/hub.c linux-rpi/drivers/usb/core/hub.c ---- linux-4.1.13.orig/drivers/usb/core/hub.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/usb/core/hub.c 2015-11-29 09:42:39.875101617 +0100 -@@ -4906,7 +4906,7 @@ - if (portchange & USB_PORT_STAT_C_OVERCURRENT) { - u16 status = 0, unused; - -- dev_dbg(&port_dev->dev, "over-current change\n"); -+ dev_notice(&port_dev->dev, "over-current change\n"); - usb_clear_port_feature(hdev, port1, - USB_PORT_FEAT_C_OVER_CURRENT); - msleep(100); /* Cool down */ -diff -Nur linux-4.1.13.orig/drivers/usb/core/message.c linux-rpi/drivers/usb/core/message.c ---- linux-4.1.13.orig/drivers/usb/core/message.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/usb/core/message.c 2015-11-29 09:42:39.875101617 +0100 -@@ -1872,6 +1872,85 @@ - if (cp->string == NULL && - !(dev->quirks & USB_QUIRK_CONFIG_INTF_STRINGS)) - cp->string = usb_cache_string(dev, cp->desc.iConfiguration); -+/* Uncomment this define to enable the HS Electrical Test support */ -+#define DWC_HS_ELECT_TST 1 -+#ifdef DWC_HS_ELECT_TST -+ /* Here we implement the HS Electrical Test support. The -+ * tester uses a vendor ID of 0x1A0A to indicate we should -+ * run a special test sequence. The product ID tells us -+ * which sequence to run. We invoke the test sequence by -+ * sending a non-standard SetFeature command to our root -+ * hub port. Our dwc_otg_hcd_hub_control() routine will -+ * recognize the command and perform the desired test -+ * sequence. -+ */ -+ if (dev->descriptor.idVendor == 0x1A0A) { -+ /* HSOTG Electrical Test */ -+ dev_warn(&dev->dev, "VID from HSOTG Electrical Test Fixture\n"); -+ -+ if (dev->bus && dev->bus->root_hub) { -+ struct usb_device *hdev = dev->bus->root_hub; -+ dev_warn(&dev->dev, "Got PID 0x%x\n", dev->descriptor.idProduct); -+ -+ switch (dev->descriptor.idProduct) { -+ case 0x0101: /* TEST_SE0_NAK */ -+ dev_warn(&dev->dev, "TEST_SE0_NAK\n"); -+ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0), -+ USB_REQ_SET_FEATURE, USB_RT_PORT, -+ USB_PORT_FEAT_TEST, 0x300, NULL, 0, HZ); -+ break; -+ -+ case 0x0102: /* TEST_J */ -+ dev_warn(&dev->dev, "TEST_J\n"); -+ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0), -+ USB_REQ_SET_FEATURE, USB_RT_PORT, -+ USB_PORT_FEAT_TEST, 0x100, NULL, 0, HZ); -+ break; -+ -+ case 0x0103: /* TEST_K */ -+ dev_warn(&dev->dev, "TEST_K\n"); -+ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0), -+ USB_REQ_SET_FEATURE, USB_RT_PORT, -+ USB_PORT_FEAT_TEST, 0x200, NULL, 0, HZ); -+ break; -+ -+ case 0x0104: /* TEST_PACKET */ -+ dev_warn(&dev->dev, "TEST_PACKET\n"); -+ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0), -+ USB_REQ_SET_FEATURE, USB_RT_PORT, -+ USB_PORT_FEAT_TEST, 0x400, NULL, 0, HZ); -+ break; -+ -+ case 0x0105: /* TEST_FORCE_ENABLE */ -+ dev_warn(&dev->dev, "TEST_FORCE_ENABLE\n"); -+ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0), -+ USB_REQ_SET_FEATURE, USB_RT_PORT, -+ USB_PORT_FEAT_TEST, 0x500, NULL, 0, HZ); -+ break; -+ -+ case 0x0106: /* HS_HOST_PORT_SUSPEND_RESUME */ -+ dev_warn(&dev->dev, "HS_HOST_PORT_SUSPEND_RESUME\n"); -+ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0), -+ USB_REQ_SET_FEATURE, USB_RT_PORT, -+ USB_PORT_FEAT_TEST, 0x600, NULL, 0, 40 * HZ); -+ break; -+ -+ case 0x0107: /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */ -+ dev_warn(&dev->dev, "SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup\n"); -+ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0), -+ USB_REQ_SET_FEATURE, USB_RT_PORT, -+ USB_PORT_FEAT_TEST, 0x700, NULL, 0, 40 * HZ); -+ break; -+ -+ case 0x0108: /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */ -+ dev_warn(&dev->dev, "SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute\n"); -+ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0), -+ USB_REQ_SET_FEATURE, USB_RT_PORT, -+ USB_PORT_FEAT_TEST, 0x800, NULL, 0, 40 * HZ); -+ } -+ } -+ } -+#endif /* DWC_HS_ELECT_TST */ - - /* Now that the interfaces are installed, re-enable LPM. */ - usb_unlocked_enable_lpm(dev); -diff -Nur linux-4.1.13.orig/drivers/usb/core/otg_whitelist.h linux-rpi/drivers/usb/core/otg_whitelist.h ---- linux-4.1.13.orig/drivers/usb/core/otg_whitelist.h 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/usb/core/otg_whitelist.h 2015-11-29 09:42:39.875101617 +0100 -@@ -19,33 +19,82 @@ - static struct usb_device_id whitelist_table [] = { - - /* hubs are optional in OTG, but very handy ... */ -+#define CERT_WITHOUT_HUBS -+#if defined(CERT_WITHOUT_HUBS) -+{ USB_DEVICE( 0x0000, 0x0000 ), }, /* Root HUB Only*/ -+#else - { USB_DEVICE_INFO(USB_CLASS_HUB, 0, 0), }, - { USB_DEVICE_INFO(USB_CLASS_HUB, 0, 1), }, -+{ USB_DEVICE_INFO(USB_CLASS_HUB, 0, 2), }, -+#endif - - #ifdef CONFIG_USB_PRINTER /* ignoring nonstatic linkage! */ - /* FIXME actually, printers are NOT supposed to use device classes; - * they're supposed to use interface classes... - */ --{ USB_DEVICE_INFO(7, 1, 1) }, --{ USB_DEVICE_INFO(7, 1, 2) }, --{ USB_DEVICE_INFO(7, 1, 3) }, -+//{ USB_DEVICE_INFO(7, 1, 1) }, -+//{ USB_DEVICE_INFO(7, 1, 2) }, -+//{ USB_DEVICE_INFO(7, 1, 3) }, - #endif - - #ifdef CONFIG_USB_NET_CDCETHER - /* Linux-USB CDC Ethernet gadget */ --{ USB_DEVICE(0x0525, 0xa4a1), }, -+//{ USB_DEVICE(0x0525, 0xa4a1), }, - /* Linux-USB CDC Ethernet + RNDIS gadget */ --{ USB_DEVICE(0x0525, 0xa4a2), }, -+//{ USB_DEVICE(0x0525, 0xa4a2), }, - #endif - - #if defined(CONFIG_USB_TEST) || defined(CONFIG_USB_TEST_MODULE) - /* gadget zero, for testing */ --{ USB_DEVICE(0x0525, 0xa4a0), }, -+//{ USB_DEVICE(0x0525, 0xa4a0), }, - #endif - -+/* OPT Tester */ -+{ USB_DEVICE( 0x1a0a, 0x0101 ), }, /* TEST_SE0_NAK */ -+{ USB_DEVICE( 0x1a0a, 0x0102 ), }, /* Test_J */ -+{ USB_DEVICE( 0x1a0a, 0x0103 ), }, /* Test_K */ -+{ USB_DEVICE( 0x1a0a, 0x0104 ), }, /* Test_PACKET */ -+{ USB_DEVICE( 0x1a0a, 0x0105 ), }, /* Test_FORCE_ENABLE */ -+{ USB_DEVICE( 0x1a0a, 0x0106 ), }, /* HS_PORT_SUSPEND_RESUME */ -+{ USB_DEVICE( 0x1a0a, 0x0107 ), }, /* SINGLE_STEP_GET_DESCRIPTOR setup */ -+{ USB_DEVICE( 0x1a0a, 0x0108 ), }, /* SINGLE_STEP_GET_DESCRIPTOR execute */ -+ -+/* Sony cameras */ -+{ USB_DEVICE_VER(0x054c,0x0010,0x0410, 0x0500), }, -+ -+/* Memory Devices */ -+//{ USB_DEVICE( 0x0781, 0x5150 ), }, /* SanDisk */ -+//{ USB_DEVICE( 0x05DC, 0x0080 ), }, /* Lexar */ -+//{ USB_DEVICE( 0x4146, 0x9281 ), }, /* IOMEGA */ -+//{ USB_DEVICE( 0x067b, 0x2507 ), }, /* Hammer 20GB External HD */ -+{ USB_DEVICE( 0x0EA0, 0x2168 ), }, /* Ours Technology Inc. (BUFFALO ClipDrive)*/ -+//{ USB_DEVICE( 0x0457, 0x0150 ), }, /* Silicon Integrated Systems Corp. */ -+ -+/* HP Printers */ -+//{ USB_DEVICE( 0x03F0, 0x1102 ), }, /* HP Photosmart 245 */ -+//{ USB_DEVICE( 0x03F0, 0x1302 ), }, /* HP Photosmart 370 Series */ -+ -+/* Speakers */ -+//{ USB_DEVICE( 0x0499, 0x3002 ), }, /* YAMAHA YST-MS35D USB Speakers */ -+//{ USB_DEVICE( 0x0672, 0x1041 ), }, /* Labtec USB Headset */ -+ - { } /* Terminating entry */ - }; - -+static inline void report_errors(struct usb_device *dev) -+{ -+ /* OTG MESSAGE: report errors here, customize to match your product */ -+ dev_info(&dev->dev, "device Vendor:%04x Product:%04x is not supported\n", -+ le16_to_cpu(dev->descriptor.idVendor), -+ le16_to_cpu(dev->descriptor.idProduct)); -+ if (USB_CLASS_HUB == dev->descriptor.bDeviceClass){ -+ dev_printk(KERN_CRIT, &dev->dev, "Unsupported Hub Topology\n"); -+ } else { -+ dev_printk(KERN_CRIT, &dev->dev, "Attached Device is not Supported\n"); -+ } -+} -+ -+ - static int is_targeted(struct usb_device *dev) - { - struct usb_device_id *id = whitelist_table; -@@ -95,16 +144,57 @@ - continue; - - return 1; -- } -+ /* NOTE: can't use usb_match_id() since interface caches -+ * aren't set up yet. this is cut/paste from that code. -+ */ -+ for (id = whitelist_table; id->match_flags; id++) { -+#ifdef DEBUG -+ dev_dbg(&dev->dev, -+ "ID: V:%04x P:%04x DC:%04x SC:%04x PR:%04x \n", -+ id->idVendor, -+ id->idProduct, -+ id->bDeviceClass, -+ id->bDeviceSubClass, -+ id->bDeviceProtocol); -+#endif - -- /* add other match criteria here ... */ -+ if ((id->match_flags & USB_DEVICE_ID_MATCH_VENDOR) && -+ id->idVendor != le16_to_cpu(dev->descriptor.idVendor)) -+ continue; -+ -+ if ((id->match_flags & USB_DEVICE_ID_MATCH_PRODUCT) && -+ id->idProduct != le16_to_cpu(dev->descriptor.idProduct)) -+ continue; -+ -+ /* No need to test id->bcdDevice_lo != 0, since 0 is never -+ greater than any unsigned number. */ -+ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_LO) && -+ (id->bcdDevice_lo > le16_to_cpu(dev->descriptor.bcdDevice))) -+ continue; -+ -+ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_HI) && -+ (id->bcdDevice_hi < le16_to_cpu(dev->descriptor.bcdDevice))) -+ continue; -+ -+ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_CLASS) && -+ (id->bDeviceClass != dev->descriptor.bDeviceClass)) -+ continue; -+ -+ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_SUBCLASS) && -+ (id->bDeviceSubClass != dev->descriptor.bDeviceSubClass)) -+ continue; -+ -+ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_PROTOCOL) && -+ (id->bDeviceProtocol != dev->descriptor.bDeviceProtocol)) -+ continue; - -+ return 1; -+ } -+ } - -- /* OTG MESSAGE: report errors here, customize to match your product */ -- dev_err(&dev->dev, "device v%04x p%04x is not supported\n", -- le16_to_cpu(dev->descriptor.idVendor), -- le16_to_cpu(dev->descriptor.idProduct)); -+ /* add other match criteria here ... */ - -+ report_errors(dev); - return 0; - } - -diff -Nur linux-4.1.13.orig/drivers/usb/gadget/file_storage.c linux-rpi/drivers/usb/gadget/file_storage.c ---- linux-4.1.13.orig/drivers/usb/gadget/file_storage.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/gadget/file_storage.c 2015-11-29 09:42:39.887100820 +0100 -@@ -0,0 +1,3676 @@ -+/* -+ * file_storage.c -- File-backed USB Storage Gadget, for USB development -+ * -+ * Copyright (C) 2003-2008 Alan Stern -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/* -+ * The File-backed Storage Gadget acts as a USB Mass Storage device, -+ * appearing to the host as a disk drive or as a CD-ROM drive. In addition -+ * to providing an example of a genuinely useful gadget driver for a USB -+ * device, it also illustrates a technique of double-buffering for increased -+ * throughput. Last but not least, it gives an easy way to probe the -+ * behavior of the Mass Storage drivers in a USB host. -+ * -+ * Backing storage is provided by a regular file or a block device, specified -+ * by the "file" module parameter. Access can be limited to read-only by -+ * setting the optional "ro" module parameter. (For CD-ROM emulation, -+ * access is always read-only.) The gadget will indicate that it has -+ * removable media if the optional "removable" module parameter is set. -+ * -+ * The gadget supports the Control-Bulk (CB), Control-Bulk-Interrupt (CBI), -+ * and Bulk-Only (also known as Bulk-Bulk-Bulk or BBB) transports, selected -+ * by the optional "transport" module parameter. It also supports the -+ * following protocols: RBC (0x01), ATAPI or SFF-8020i (0x02), QIC-157 (0c03), -+ * UFI (0x04), SFF-8070i (0x05), and transparent SCSI (0x06), selected by -+ * the optional "protocol" module parameter. In addition, the default -+ * Vendor ID, Product ID, release number and serial number can be overridden. -+ * -+ * There is support for multiple logical units (LUNs), each of which has -+ * its own backing file. The number of LUNs can be set using the optional -+ * "luns" module parameter (anywhere from 1 to 8), and the corresponding -+ * files are specified using comma-separated lists for "file" and "ro". -+ * The default number of LUNs is taken from the number of "file" elements; -+ * it is 1 if "file" is not given. If "removable" is not set then a backing -+ * file must be specified for each LUN. If it is set, then an unspecified -+ * or empty backing filename means the LUN's medium is not loaded. Ideally -+ * each LUN would be settable independently as a disk drive or a CD-ROM -+ * drive, but currently all LUNs have to be the same type. The CD-ROM -+ * emulation includes a single data track and no audio tracks; hence there -+ * need be only one backing file per LUN. -+ * -+ * Requirements are modest; only a bulk-in and a bulk-out endpoint are -+ * needed (an interrupt-out endpoint is also needed for CBI). The memory -+ * requirement amounts to two 16K buffers, size configurable by a parameter. -+ * Support is included for both full-speed and high-speed operation. -+ * -+ * Note that the driver is slightly non-portable in that it assumes a -+ * single memory/DMA buffer will be useable for bulk-in, bulk-out, and -+ * interrupt-in endpoints. With most device controllers this isn't an -+ * issue, but there may be some with hardware restrictions that prevent -+ * a buffer from being used by more than one endpoint. -+ * -+ * Module options: -+ * -+ * file=filename[,filename...] -+ * Required if "removable" is not set, names of -+ * the files or block devices used for -+ * backing storage -+ * serial=HHHH... Required serial number (string of hex chars) -+ * ro=b[,b...] Default false, booleans for read-only access -+ * removable Default false, boolean for removable media -+ * luns=N Default N = number of filenames, number of -+ * LUNs to support -+ * nofua=b[,b...] Default false, booleans for ignore FUA flag -+ * in SCSI WRITE(10,12) commands -+ * stall Default determined according to the type of -+ * USB device controller (usually true), -+ * boolean to permit the driver to halt -+ * bulk endpoints -+ * cdrom Default false, boolean for whether to emulate -+ * a CD-ROM drive -+ * transport=XXX Default BBB, transport name (CB, CBI, or BBB) -+ * protocol=YYY Default SCSI, protocol name (RBC, 8020 or -+ * ATAPI, QIC, UFI, 8070, or SCSI; -+ * also 1 - 6) -+ * vendor=0xVVVV Default 0x0525 (NetChip), USB Vendor ID -+ * product=0xPPPP Default 0xa4a5 (FSG), USB Product ID -+ * release=0xRRRR Override the USB release number (bcdDevice) -+ * buflen=N Default N=16384, buffer size used (will be -+ * rounded down to a multiple of -+ * PAGE_CACHE_SIZE) -+ * -+ * If CONFIG_USB_FILE_STORAGE_TEST is not set, only the "file", "serial", "ro", -+ * "removable", "luns", "nofua", "stall", and "cdrom" options are available; -+ * default values are used for everything else. -+ * -+ * The pathnames of the backing files and the ro settings are available in -+ * the attribute files "file", "nofua", and "ro" in the lun subdirectory of -+ * the gadget's sysfs directory. If the "removable" option is set, writing to -+ * these files will simulate ejecting/loading the medium (writing an empty -+ * line means eject) and adjusting a write-enable tab. Changes to the ro -+ * setting are not allowed when the medium is loaded or if CD-ROM emulation -+ * is being used. -+ * -+ * This gadget driver is heavily based on "Gadget Zero" by David Brownell. -+ * The driver's SCSI command interface was based on the "Information -+ * technology - Small Computer System Interface - 2" document from -+ * X3T9.2 Project 375D, Revision 10L, 7-SEP-93, available at -+ * . The single exception -+ * is opcode 0x23 (READ FORMAT CAPACITIES), which was based on the -+ * "Universal Serial Bus Mass Storage Class UFI Command Specification" -+ * document, Revision 1.0, December 14, 1998, available at -+ * . -+ */ -+ -+ -+/* -+ * Driver Design -+ * -+ * The FSG driver is fairly straightforward. There is a main kernel -+ * thread that handles most of the work. Interrupt routines field -+ * callbacks from the controller driver: bulk- and interrupt-request -+ * completion notifications, endpoint-0 events, and disconnect events. -+ * Completion events are passed to the main thread by wakeup calls. Many -+ * ep0 requests are handled at interrupt time, but SetInterface, -+ * SetConfiguration, and device reset requests are forwarded to the -+ * thread in the form of "exceptions" using SIGUSR1 signals (since they -+ * should interrupt any ongoing file I/O operations). -+ * -+ * The thread's main routine implements the standard command/data/status -+ * parts of a SCSI interaction. It and its subroutines are full of tests -+ * for pending signals/exceptions -- all this polling is necessary since -+ * the kernel has no setjmp/longjmp equivalents. (Maybe this is an -+ * indication that the driver really wants to be running in userspace.) -+ * An important point is that so long as the thread is alive it keeps an -+ * open reference to the backing file. This will prevent unmounting -+ * the backing file's underlying filesystem and could cause problems -+ * during system shutdown, for example. To prevent such problems, the -+ * thread catches INT, TERM, and KILL signals and converts them into -+ * an EXIT exception. -+ * -+ * In normal operation the main thread is started during the gadget's -+ * fsg_bind() callback and stopped during fsg_unbind(). But it can also -+ * exit when it receives a signal, and there's no point leaving the -+ * gadget running when the thread is dead. So just before the thread -+ * exits, it deregisters the gadget driver. This makes things a little -+ * tricky: The driver is deregistered at two places, and the exiting -+ * thread can indirectly call fsg_unbind() which in turn can tell the -+ * thread to exit. The first problem is resolved through the use of the -+ * REGISTERED atomic bitflag; the driver will only be deregistered once. -+ * The second problem is resolved by having fsg_unbind() check -+ * fsg->state; it won't try to stop the thread if the state is already -+ * FSG_STATE_TERMINATED. -+ * -+ * To provide maximum throughput, the driver uses a circular pipeline of -+ * buffer heads (struct fsg_buffhd). In principle the pipeline can be -+ * arbitrarily long; in practice the benefits don't justify having more -+ * than 2 stages (i.e., double buffering). But it helps to think of the -+ * pipeline as being a long one. Each buffer head contains a bulk-in and -+ * a bulk-out request pointer (since the buffer can be used for both -+ * output and input -- directions always are given from the host's -+ * point of view) as well as a pointer to the buffer and various state -+ * variables. -+ * -+ * Use of the pipeline follows a simple protocol. There is a variable -+ * (fsg->next_buffhd_to_fill) that points to the next buffer head to use. -+ * At any time that buffer head may still be in use from an earlier -+ * request, so each buffer head has a state variable indicating whether -+ * it is EMPTY, FULL, or BUSY. Typical use involves waiting for the -+ * buffer head to be EMPTY, filling the buffer either by file I/O or by -+ * USB I/O (during which the buffer head is BUSY), and marking the buffer -+ * head FULL when the I/O is complete. Then the buffer will be emptied -+ * (again possibly by USB I/O, during which it is marked BUSY) and -+ * finally marked EMPTY again (possibly by a completion routine). -+ * -+ * A module parameter tells the driver to avoid stalling the bulk -+ * endpoints wherever the transport specification allows. This is -+ * necessary for some UDCs like the SuperH, which cannot reliably clear a -+ * halt on a bulk endpoint. However, under certain circumstances the -+ * Bulk-only specification requires a stall. In such cases the driver -+ * will halt the endpoint and set a flag indicating that it should clear -+ * the halt in software during the next device reset. Hopefully this -+ * will permit everything to work correctly. Furthermore, although the -+ * specification allows the bulk-out endpoint to halt when the host sends -+ * too much data, implementing this would cause an unavoidable race. -+ * The driver will always use the "no-stall" approach for OUT transfers. -+ * -+ * One subtle point concerns sending status-stage responses for ep0 -+ * requests. Some of these requests, such as device reset, can involve -+ * interrupting an ongoing file I/O operation, which might take an -+ * arbitrarily long time. During that delay the host might give up on -+ * the original ep0 request and issue a new one. When that happens the -+ * driver should not notify the host about completion of the original -+ * request, as the host will no longer be waiting for it. So the driver -+ * assigns to each ep0 request a unique tag, and it keeps track of the -+ * tag value of the request associated with a long-running exception -+ * (device-reset, interface-change, or configuration-change). When the -+ * exception handler is finished, the status-stage response is submitted -+ * only if the current ep0 request tag is equal to the exception request -+ * tag. Thus only the most recently received ep0 request will get a -+ * status-stage response. -+ * -+ * Warning: This driver source file is too long. It ought to be split up -+ * into a header file plus about 3 separate .c files, to handle the details -+ * of the Gadget, USB Mass Storage, and SCSI protocols. -+ */ -+ -+ -+/* #define VERBOSE_DEBUG */ -+/* #define DUMP_MSGS */ -+ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include "gadget_chips.h" -+ -+ -+ -+/* -+ * Kbuild is not very cooperative with respect to linking separately -+ * compiled library objects into one module. So for now we won't use -+ * separate compilation ... ensuring init/exit sections work to shrink -+ * the runtime footprint, and giving us at least some parts of what -+ * a "gcc --combine ... part1.c part2.c part3.c ... " build would. -+ */ -+#include "usbstring.c" -+#include "config.c" -+#include "epautoconf.c" -+ -+/*-------------------------------------------------------------------------*/ -+ -+#define DRIVER_DESC "File-backed Storage Gadget" -+#define DRIVER_NAME "g_file_storage" -+#define DRIVER_VERSION "1 September 2010" -+ -+static char fsg_string_manufacturer[64]; -+static const char fsg_string_product[] = DRIVER_DESC; -+static const char fsg_string_config[] = "Self-powered"; -+static const char fsg_string_interface[] = "Mass Storage"; -+ -+ -+#include "storage_common.c" -+ -+ -+MODULE_DESCRIPTION(DRIVER_DESC); -+MODULE_AUTHOR("Alan Stern"); -+MODULE_LICENSE("Dual BSD/GPL"); -+ -+/* -+ * This driver assumes self-powered hardware and has no way for users to -+ * trigger remote wakeup. It uses autoconfiguration to select endpoints -+ * and endpoint addresses. -+ */ -+ -+ -+/*-------------------------------------------------------------------------*/ -+ -+ -+/* Encapsulate the module parameter settings */ -+ -+static struct { -+ char *file[FSG_MAX_LUNS]; -+ char *serial; -+ bool ro[FSG_MAX_LUNS]; -+ bool nofua[FSG_MAX_LUNS]; -+ unsigned int num_filenames; -+ unsigned int num_ros; -+ unsigned int num_nofuas; -+ unsigned int nluns; -+ -+ bool removable; -+ bool can_stall; -+ bool cdrom; -+ -+ char *transport_parm; -+ char *protocol_parm; -+ unsigned short vendor; -+ unsigned short product; -+ unsigned short release; -+ unsigned int buflen; -+ -+ int transport_type; -+ char *transport_name; -+ int protocol_type; -+ char *protocol_name; -+ -+} mod_data = { // Default values -+ .transport_parm = "BBB", -+ .protocol_parm = "SCSI", -+ .removable = 0, -+ .can_stall = 1, -+ .cdrom = 0, -+ .vendor = FSG_VENDOR_ID, -+ .product = FSG_PRODUCT_ID, -+ .release = 0xffff, // Use controller chip type -+ .buflen = 16384, -+ }; -+ -+ -+module_param_array_named(file, mod_data.file, charp, &mod_data.num_filenames, -+ S_IRUGO); -+MODULE_PARM_DESC(file, "names of backing files or devices"); -+ -+module_param_named(serial, mod_data.serial, charp, S_IRUGO); -+MODULE_PARM_DESC(serial, "USB serial number"); -+ -+module_param_array_named(ro, mod_data.ro, bool, &mod_data.num_ros, S_IRUGO); -+MODULE_PARM_DESC(ro, "true to force read-only"); -+ -+module_param_array_named(nofua, mod_data.nofua, bool, &mod_data.num_nofuas, -+ S_IRUGO); -+MODULE_PARM_DESC(nofua, "true to ignore SCSI WRITE(10,12) FUA bit"); -+ -+module_param_named(luns, mod_data.nluns, uint, S_IRUGO); -+MODULE_PARM_DESC(luns, "number of LUNs"); -+ -+module_param_named(removable, mod_data.removable, bool, S_IRUGO); -+MODULE_PARM_DESC(removable, "true to simulate removable media"); -+ -+module_param_named(stall, mod_data.can_stall, bool, S_IRUGO); -+MODULE_PARM_DESC(stall, "false to prevent bulk stalls"); -+ -+module_param_named(cdrom, mod_data.cdrom, bool, S_IRUGO); -+MODULE_PARM_DESC(cdrom, "true to emulate cdrom instead of disk"); -+ -+/* In the non-TEST version, only the module parameters listed above -+ * are available. */ -+#ifdef CONFIG_USB_FILE_STORAGE_TEST -+ -+module_param_named(transport, mod_data.transport_parm, charp, S_IRUGO); -+MODULE_PARM_DESC(transport, "type of transport (BBB, CBI, or CB)"); -+ -+module_param_named(protocol, mod_data.protocol_parm, charp, S_IRUGO); -+MODULE_PARM_DESC(protocol, "type of protocol (RBC, 8020, QIC, UFI, " -+ "8070, or SCSI)"); -+ -+module_param_named(vendor, mod_data.vendor, ushort, S_IRUGO); -+MODULE_PARM_DESC(vendor, "USB Vendor ID"); -+ -+module_param_named(product, mod_data.product, ushort, S_IRUGO); -+MODULE_PARM_DESC(product, "USB Product ID"); -+ -+module_param_named(release, mod_data.release, ushort, S_IRUGO); -+MODULE_PARM_DESC(release, "USB release number"); -+ -+module_param_named(buflen, mod_data.buflen, uint, S_IRUGO); -+MODULE_PARM_DESC(buflen, "I/O buffer size"); -+ -+#endif /* CONFIG_USB_FILE_STORAGE_TEST */ -+ -+ -+/* -+ * These definitions will permit the compiler to avoid generating code for -+ * parts of the driver that aren't used in the non-TEST version. Even gcc -+ * can recognize when a test of a constant expression yields a dead code -+ * path. -+ */ -+ -+#ifdef CONFIG_USB_FILE_STORAGE_TEST -+ -+#define transport_is_bbb() (mod_data.transport_type == USB_PR_BULK) -+#define transport_is_cbi() (mod_data.transport_type == USB_PR_CBI) -+#define protocol_is_scsi() (mod_data.protocol_type == USB_SC_SCSI) -+ -+#else -+ -+#define transport_is_bbb() 1 -+#define transport_is_cbi() 0 -+#define protocol_is_scsi() 1 -+ -+#endif /* CONFIG_USB_FILE_STORAGE_TEST */ -+ -+ -+/*-------------------------------------------------------------------------*/ -+ -+ -+struct fsg_dev { -+ /* lock protects: state, all the req_busy's, and cbbuf_cmnd */ -+ spinlock_t lock; -+ struct usb_gadget *gadget; -+ -+ /* filesem protects: backing files in use */ -+ struct rw_semaphore filesem; -+ -+ /* reference counting: wait until all LUNs are released */ -+ struct kref ref; -+ -+ struct usb_ep *ep0; // Handy copy of gadget->ep0 -+ struct usb_request *ep0req; // For control responses -+ unsigned int ep0_req_tag; -+ const char *ep0req_name; -+ -+ struct usb_request *intreq; // For interrupt responses -+ int intreq_busy; -+ struct fsg_buffhd *intr_buffhd; -+ -+ unsigned int bulk_out_maxpacket; -+ enum fsg_state state; // For exception handling -+ unsigned int exception_req_tag; -+ -+ u8 config, new_config; -+ -+ unsigned int running : 1; -+ unsigned int bulk_in_enabled : 1; -+ unsigned int bulk_out_enabled : 1; -+ unsigned int intr_in_enabled : 1; -+ unsigned int phase_error : 1; -+ unsigned int short_packet_received : 1; -+ unsigned int bad_lun_okay : 1; -+ -+ unsigned long atomic_bitflags; -+#define REGISTERED 0 -+#define IGNORE_BULK_OUT 1 -+#define SUSPENDED 2 -+ -+ struct usb_ep *bulk_in; -+ struct usb_ep *bulk_out; -+ struct usb_ep *intr_in; -+ -+ struct fsg_buffhd *next_buffhd_to_fill; -+ struct fsg_buffhd *next_buffhd_to_drain; -+ -+ int thread_wakeup_needed; -+ struct completion thread_notifier; -+ struct task_struct *thread_task; -+ -+ int cmnd_size; -+ u8 cmnd[MAX_COMMAND_SIZE]; -+ enum data_direction data_dir; -+ u32 data_size; -+ u32 data_size_from_cmnd; -+ u32 tag; -+ unsigned int lun; -+ u32 residue; -+ u32 usb_amount_left; -+ -+ /* The CB protocol offers no way for a host to know when a command -+ * has completed. As a result the next command may arrive early, -+ * and we will still have to handle it. For that reason we need -+ * a buffer to store new commands when using CB (or CBI, which -+ * does not oblige a host to wait for command completion either). */ -+ int cbbuf_cmnd_size; -+ u8 cbbuf_cmnd[MAX_COMMAND_SIZE]; -+ -+ unsigned int nluns; -+ struct fsg_lun *luns; -+ struct fsg_lun *curlun; -+ /* Must be the last entry */ -+ struct fsg_buffhd buffhds[]; -+}; -+ -+typedef void (*fsg_routine_t)(struct fsg_dev *); -+ -+static int exception_in_progress(struct fsg_dev *fsg) -+{ -+ return (fsg->state > FSG_STATE_IDLE); -+} -+ -+/* Make bulk-out requests be divisible by the maxpacket size */ -+static void set_bulk_out_req_length(struct fsg_dev *fsg, -+ struct fsg_buffhd *bh, unsigned int length) -+{ -+ unsigned int rem; -+ -+ bh->bulk_out_intended_length = length; -+ rem = length % fsg->bulk_out_maxpacket; -+ if (rem > 0) -+ length += fsg->bulk_out_maxpacket - rem; -+ bh->outreq->length = length; -+} -+ -+static struct fsg_dev *the_fsg; -+static struct usb_gadget_driver fsg_driver; -+ -+ -+/*-------------------------------------------------------------------------*/ -+ -+static int fsg_set_halt(struct fsg_dev *fsg, struct usb_ep *ep) -+{ -+ const char *name; -+ -+ if (ep == fsg->bulk_in) -+ name = "bulk-in"; -+ else if (ep == fsg->bulk_out) -+ name = "bulk-out"; -+ else -+ name = ep->name; -+ DBG(fsg, "%s set halt\n", name); -+ return usb_ep_set_halt(ep); -+} -+ -+ -+/*-------------------------------------------------------------------------*/ -+ -+/* -+ * DESCRIPTORS ... most are static, but strings and (full) configuration -+ * descriptors are built on demand. Also the (static) config and interface -+ * descriptors are adjusted during fsg_bind(). -+ */ -+ -+/* There is only one configuration. */ -+#define CONFIG_VALUE 1 -+ -+static struct usb_device_descriptor -+device_desc = { -+ .bLength = sizeof device_desc, -+ .bDescriptorType = USB_DT_DEVICE, -+ -+ .bcdUSB = cpu_to_le16(0x0200), -+ .bDeviceClass = USB_CLASS_PER_INTERFACE, -+ -+ /* The next three values can be overridden by module parameters */ -+ .idVendor = cpu_to_le16(FSG_VENDOR_ID), -+ .idProduct = cpu_to_le16(FSG_PRODUCT_ID), -+ .bcdDevice = cpu_to_le16(0xffff), -+ -+ .iManufacturer = FSG_STRING_MANUFACTURER, -+ .iProduct = FSG_STRING_PRODUCT, -+ .iSerialNumber = FSG_STRING_SERIAL, -+ .bNumConfigurations = 1, -+}; -+ -+static struct usb_config_descriptor -+config_desc = { -+ .bLength = sizeof config_desc, -+ .bDescriptorType = USB_DT_CONFIG, -+ -+ /* wTotalLength computed by usb_gadget_config_buf() */ -+ .bNumInterfaces = 1, -+ .bConfigurationValue = CONFIG_VALUE, -+ .iConfiguration = FSG_STRING_CONFIG, -+ .bmAttributes = USB_CONFIG_ATT_ONE | USB_CONFIG_ATT_SELFPOWER, -+ .bMaxPower = CONFIG_USB_GADGET_VBUS_DRAW / 2, -+}; -+ -+ -+static struct usb_qualifier_descriptor -+dev_qualifier = { -+ .bLength = sizeof dev_qualifier, -+ .bDescriptorType = USB_DT_DEVICE_QUALIFIER, -+ -+ .bcdUSB = cpu_to_le16(0x0200), -+ .bDeviceClass = USB_CLASS_PER_INTERFACE, -+ -+ .bNumConfigurations = 1, -+}; -+ -+static int populate_bos(struct fsg_dev *fsg, u8 *buf) -+{ -+ memcpy(buf, &fsg_bos_desc, USB_DT_BOS_SIZE); -+ buf += USB_DT_BOS_SIZE; -+ -+ memcpy(buf, &fsg_ext_cap_desc, USB_DT_USB_EXT_CAP_SIZE); -+ buf += USB_DT_USB_EXT_CAP_SIZE; -+ -+ memcpy(buf, &fsg_ss_cap_desc, USB_DT_USB_SS_CAP_SIZE); -+ -+ return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE -+ + USB_DT_USB_EXT_CAP_SIZE; -+} -+ -+/* -+ * Config descriptors must agree with the code that sets configurations -+ * and with code managing interfaces and their altsettings. They must -+ * also handle different speeds and other-speed requests. -+ */ -+static int populate_config_buf(struct usb_gadget *gadget, -+ u8 *buf, u8 type, unsigned index) -+{ -+ enum usb_device_speed speed = gadget->speed; -+ int len; -+ const struct usb_descriptor_header **function; -+ -+ if (index > 0) -+ return -EINVAL; -+ -+ if (gadget_is_dualspeed(gadget) && type == USB_DT_OTHER_SPEED_CONFIG) -+ speed = (USB_SPEED_FULL + USB_SPEED_HIGH) - speed; -+ function = gadget_is_dualspeed(gadget) && speed == USB_SPEED_HIGH -+ ? (const struct usb_descriptor_header **)fsg_hs_function -+ : (const struct usb_descriptor_header **)fsg_fs_function; -+ -+ /* for now, don't advertise srp-only devices */ -+ if (!gadget_is_otg(gadget)) -+ function++; -+ -+ len = usb_gadget_config_buf(&config_desc, buf, EP0_BUFSIZE, function); -+ ((struct usb_config_descriptor *) buf)->bDescriptorType = type; -+ return len; -+} -+ -+ -+/*-------------------------------------------------------------------------*/ -+ -+/* These routines may be called in process context or in_irq */ -+ -+/* Caller must hold fsg->lock */ -+static void wakeup_thread(struct fsg_dev *fsg) -+{ -+ /* Tell the main thread that something has happened */ -+ fsg->thread_wakeup_needed = 1; -+ if (fsg->thread_task) -+ wake_up_process(fsg->thread_task); -+} -+ -+ -+static void raise_exception(struct fsg_dev *fsg, enum fsg_state new_state) -+{ -+ unsigned long flags; -+ -+ /* Do nothing if a higher-priority exception is already in progress. -+ * If a lower-or-equal priority exception is in progress, preempt it -+ * and notify the main thread by sending it a signal. */ -+ spin_lock_irqsave(&fsg->lock, flags); -+ if (fsg->state <= new_state) { -+ fsg->exception_req_tag = fsg->ep0_req_tag; -+ fsg->state = new_state; -+ if (fsg->thread_task) -+ send_sig_info(SIGUSR1, SEND_SIG_FORCED, -+ fsg->thread_task); -+ } -+ spin_unlock_irqrestore(&fsg->lock, flags); -+} -+ -+ -+/*-------------------------------------------------------------------------*/ -+ -+/* The disconnect callback and ep0 routines. These always run in_irq, -+ * except that ep0_queue() is called in the main thread to acknowledge -+ * completion of various requests: set config, set interface, and -+ * Bulk-only device reset. */ -+ -+static void fsg_disconnect(struct usb_gadget *gadget) -+{ -+ struct fsg_dev *fsg = get_gadget_data(gadget); -+ -+ DBG(fsg, "disconnect or port reset\n"); -+ raise_exception(fsg, FSG_STATE_DISCONNECT); -+} -+ -+ -+static int ep0_queue(struct fsg_dev *fsg) -+{ -+ int rc; -+ -+ rc = usb_ep_queue(fsg->ep0, fsg->ep0req, GFP_ATOMIC); -+ if (rc != 0 && rc != -ESHUTDOWN) { -+ -+ /* We can't do much more than wait for a reset */ -+ WARNING(fsg, "error in submission: %s --> %d\n", -+ fsg->ep0->name, rc); -+ } -+ return rc; -+} -+ -+static void ep0_complete(struct usb_ep *ep, struct usb_request *req) -+{ -+ struct fsg_dev *fsg = ep->driver_data; -+ -+ if (req->actual > 0) -+ dump_msg(fsg, fsg->ep0req_name, req->buf, req->actual); -+ if (req->status || req->actual != req->length) -+ DBG(fsg, "%s --> %d, %u/%u\n", __func__, -+ req->status, req->actual, req->length); -+ if (req->status == -ECONNRESET) // Request was cancelled -+ usb_ep_fifo_flush(ep); -+ -+ if (req->status == 0 && req->context) -+ ((fsg_routine_t) (req->context))(fsg); -+} -+ -+ -+/*-------------------------------------------------------------------------*/ -+ -+/* Bulk and interrupt endpoint completion handlers. -+ * These always run in_irq. */ -+ -+static void bulk_in_complete(struct usb_ep *ep, struct usb_request *req) -+{ -+ struct fsg_dev *fsg = ep->driver_data; -+ struct fsg_buffhd *bh = req->context; -+ -+ if (req->status || req->actual != req->length) -+ DBG(fsg, "%s --> %d, %u/%u\n", __func__, -+ req->status, req->actual, req->length); -+ if (req->status == -ECONNRESET) // Request was cancelled -+ usb_ep_fifo_flush(ep); -+ -+ /* Hold the lock while we update the request and buffer states */ -+ smp_wmb(); -+ spin_lock(&fsg->lock); -+ bh->inreq_busy = 0; -+ bh->state = BUF_STATE_EMPTY; -+ wakeup_thread(fsg); -+ spin_unlock(&fsg->lock); -+} -+ -+static void bulk_out_complete(struct usb_ep *ep, struct usb_request *req) -+{ -+ struct fsg_dev *fsg = ep->driver_data; -+ struct fsg_buffhd *bh = req->context; -+ -+ dump_msg(fsg, "bulk-out", req->buf, req->actual); -+ if (req->status || req->actual != bh->bulk_out_intended_length) -+ DBG(fsg, "%s --> %d, %u/%u\n", __func__, -+ req->status, req->actual, -+ bh->bulk_out_intended_length); -+ if (req->status == -ECONNRESET) // Request was cancelled -+ usb_ep_fifo_flush(ep); -+ -+ /* Hold the lock while we update the request and buffer states */ -+ smp_wmb(); -+ spin_lock(&fsg->lock); -+ bh->outreq_busy = 0; -+ bh->state = BUF_STATE_FULL; -+ wakeup_thread(fsg); -+ spin_unlock(&fsg->lock); -+} -+ -+ -+#ifdef CONFIG_USB_FILE_STORAGE_TEST -+static void intr_in_complete(struct usb_ep *ep, struct usb_request *req) -+{ -+ struct fsg_dev *fsg = ep->driver_data; -+ struct fsg_buffhd *bh = req->context; -+ -+ if (req->status || req->actual != req->length) -+ DBG(fsg, "%s --> %d, %u/%u\n", __func__, -+ req->status, req->actual, req->length); -+ if (req->status == -ECONNRESET) // Request was cancelled -+ usb_ep_fifo_flush(ep); -+ -+ /* Hold the lock while we update the request and buffer states */ -+ smp_wmb(); -+ spin_lock(&fsg->lock); -+ fsg->intreq_busy = 0; -+ bh->state = BUF_STATE_EMPTY; -+ wakeup_thread(fsg); -+ spin_unlock(&fsg->lock); -+} -+ -+#else -+static void intr_in_complete(struct usb_ep *ep, struct usb_request *req) -+{} -+#endif /* CONFIG_USB_FILE_STORAGE_TEST */ -+ -+ -+/*-------------------------------------------------------------------------*/ -+ -+/* Ep0 class-specific handlers. These always run in_irq. */ -+ -+#ifdef CONFIG_USB_FILE_STORAGE_TEST -+static void received_cbi_adsc(struct fsg_dev *fsg, struct fsg_buffhd *bh) -+{ -+ struct usb_request *req = fsg->ep0req; -+ static u8 cbi_reset_cmnd[6] = { -+ SEND_DIAGNOSTIC, 4, 0xff, 0xff, 0xff, 0xff}; -+ -+ /* Error in command transfer? */ -+ if (req->status || req->length != req->actual || -+ req->actual < 6 || req->actual > MAX_COMMAND_SIZE) { -+ -+ /* Not all controllers allow a protocol stall after -+ * receiving control-out data, but we'll try anyway. */ -+ fsg_set_halt(fsg, fsg->ep0); -+ return; // Wait for reset -+ } -+ -+ /* Is it the special reset command? */ -+ if (req->actual >= sizeof cbi_reset_cmnd && -+ memcmp(req->buf, cbi_reset_cmnd, -+ sizeof cbi_reset_cmnd) == 0) { -+ -+ /* Raise an exception to stop the current operation -+ * and reinitialize our state. */ -+ DBG(fsg, "cbi reset request\n"); -+ raise_exception(fsg, FSG_STATE_RESET); -+ return; -+ } -+ -+ VDBG(fsg, "CB[I] accept device-specific command\n"); -+ spin_lock(&fsg->lock); -+ -+ /* Save the command for later */ -+ if (fsg->cbbuf_cmnd_size) -+ WARNING(fsg, "CB[I] overwriting previous command\n"); -+ fsg->cbbuf_cmnd_size = req->actual; -+ memcpy(fsg->cbbuf_cmnd, req->buf, fsg->cbbuf_cmnd_size); -+ -+ wakeup_thread(fsg); -+ spin_unlock(&fsg->lock); -+} -+ -+#else -+static void received_cbi_adsc(struct fsg_dev *fsg, struct fsg_buffhd *bh) -+{} -+#endif /* CONFIG_USB_FILE_STORAGE_TEST */ -+ -+ -+static int class_setup_req(struct fsg_dev *fsg, -+ const struct usb_ctrlrequest *ctrl) -+{ -+ struct usb_request *req = fsg->ep0req; -+ int value = -EOPNOTSUPP; -+ u16 w_index = le16_to_cpu(ctrl->wIndex); -+ u16 w_value = le16_to_cpu(ctrl->wValue); -+ u16 w_length = le16_to_cpu(ctrl->wLength); -+ -+ if (!fsg->config) -+ return value; -+ -+ /* Handle Bulk-only class-specific requests */ -+ if (transport_is_bbb()) { -+ switch (ctrl->bRequest) { -+ -+ case US_BULK_RESET_REQUEST: -+ if (ctrl->bRequestType != (USB_DIR_OUT | -+ USB_TYPE_CLASS | USB_RECIP_INTERFACE)) -+ break; -+ if (w_index != 0 || w_value != 0 || w_length != 0) { -+ value = -EDOM; -+ break; -+ } -+ -+ /* Raise an exception to stop the current operation -+ * and reinitialize our state. */ -+ DBG(fsg, "bulk reset request\n"); -+ raise_exception(fsg, FSG_STATE_RESET); -+ value = DELAYED_STATUS; -+ break; -+ -+ case US_BULK_GET_MAX_LUN: -+ if (ctrl->bRequestType != (USB_DIR_IN | -+ USB_TYPE_CLASS | USB_RECIP_INTERFACE)) -+ break; -+ if (w_index != 0 || w_value != 0 || w_length != 1) { -+ value = -EDOM; -+ break; -+ } -+ VDBG(fsg, "get max LUN\n"); -+ *(u8 *) req->buf = fsg->nluns - 1; -+ value = 1; -+ break; -+ } -+ } -+ -+ /* Handle CBI class-specific requests */ -+ else { -+ switch (ctrl->bRequest) { -+ -+ case USB_CBI_ADSC_REQUEST: -+ if (ctrl->bRequestType != (USB_DIR_OUT | -+ USB_TYPE_CLASS | USB_RECIP_INTERFACE)) -+ break; -+ if (w_index != 0 || w_value != 0) { -+ value = -EDOM; -+ break; -+ } -+ if (w_length > MAX_COMMAND_SIZE) { -+ value = -EOVERFLOW; -+ break; -+ } -+ value = w_length; -+ fsg->ep0req->context = received_cbi_adsc; -+ break; -+ } -+ } -+ -+ if (value == -EOPNOTSUPP) -+ VDBG(fsg, -+ "unknown class-specific control req " -+ "%02x.%02x v%04x i%04x l%u\n", -+ ctrl->bRequestType, ctrl->bRequest, -+ le16_to_cpu(ctrl->wValue), w_index, w_length); -+ return value; -+} -+ -+ -+/*-------------------------------------------------------------------------*/ -+ -+/* Ep0 standard request handlers. These always run in_irq. */ -+ -+static int standard_setup_req(struct fsg_dev *fsg, -+ const struct usb_ctrlrequest *ctrl) -+{ -+ struct usb_request *req = fsg->ep0req; -+ int value = -EOPNOTSUPP; -+ u16 w_index = le16_to_cpu(ctrl->wIndex); -+ u16 w_value = le16_to_cpu(ctrl->wValue); -+ -+ /* Usually this just stores reply data in the pre-allocated ep0 buffer, -+ * but config change events will also reconfigure hardware. */ -+ switch (ctrl->bRequest) { -+ -+ case USB_REQ_GET_DESCRIPTOR: -+ if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD | -+ USB_RECIP_DEVICE)) -+ break; -+ switch (w_value >> 8) { -+ -+ case USB_DT_DEVICE: -+ VDBG(fsg, "get device descriptor\n"); -+ device_desc.bMaxPacketSize0 = fsg->ep0->maxpacket; -+ value = sizeof device_desc; -+ memcpy(req->buf, &device_desc, value); -+ break; -+ case USB_DT_DEVICE_QUALIFIER: -+ VDBG(fsg, "get device qualifier\n"); -+ if (!gadget_is_dualspeed(fsg->gadget) || -+ fsg->gadget->speed == USB_SPEED_SUPER) -+ break; -+ /* -+ * Assume ep0 uses the same maxpacket value for both -+ * speeds -+ */ -+ dev_qualifier.bMaxPacketSize0 = fsg->ep0->maxpacket; -+ value = sizeof dev_qualifier; -+ memcpy(req->buf, &dev_qualifier, value); -+ break; -+ -+ case USB_DT_OTHER_SPEED_CONFIG: -+ VDBG(fsg, "get other-speed config descriptor\n"); -+ if (!gadget_is_dualspeed(fsg->gadget) || -+ fsg->gadget->speed == USB_SPEED_SUPER) -+ break; -+ goto get_config; -+ case USB_DT_CONFIG: -+ VDBG(fsg, "get configuration descriptor\n"); -+get_config: -+ value = populate_config_buf(fsg->gadget, -+ req->buf, -+ w_value >> 8, -+ w_value & 0xff); -+ break; -+ -+ case USB_DT_STRING: -+ VDBG(fsg, "get string descriptor\n"); -+ -+ /* wIndex == language code */ -+ value = usb_gadget_get_string(&fsg_stringtab, -+ w_value & 0xff, req->buf); -+ break; -+ -+ case USB_DT_BOS: -+ VDBG(fsg, "get bos descriptor\n"); -+ -+ if (gadget_is_superspeed(fsg->gadget)) -+ value = populate_bos(fsg, req->buf); -+ break; -+ } -+ -+ break; -+ -+ /* One config, two speeds */ -+ case USB_REQ_SET_CONFIGURATION: -+ if (ctrl->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD | -+ USB_RECIP_DEVICE)) -+ break; -+ VDBG(fsg, "set configuration\n"); -+ if (w_value == CONFIG_VALUE || w_value == 0) { -+ fsg->new_config = w_value; -+ -+ /* Raise an exception to wipe out previous transaction -+ * state (queued bufs, etc) and set the new config. */ -+ raise_exception(fsg, FSG_STATE_CONFIG_CHANGE); -+ value = DELAYED_STATUS; -+ } -+ break; -+ case USB_REQ_GET_CONFIGURATION: -+ if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD | -+ USB_RECIP_DEVICE)) -+ break; -+ VDBG(fsg, "get configuration\n"); -+ *(u8 *) req->buf = fsg->config; -+ value = 1; -+ break; -+ -+ case USB_REQ_SET_INTERFACE: -+ if (ctrl->bRequestType != (USB_DIR_OUT| USB_TYPE_STANDARD | -+ USB_RECIP_INTERFACE)) -+ break; -+ if (fsg->config && w_index == 0) { -+ -+ /* Raise an exception to wipe out previous transaction -+ * state (queued bufs, etc) and install the new -+ * interface altsetting. */ -+ raise_exception(fsg, FSG_STATE_INTERFACE_CHANGE); -+ value = DELAYED_STATUS; -+ } -+ break; -+ case USB_REQ_GET_INTERFACE: -+ if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD | -+ USB_RECIP_INTERFACE)) -+ break; -+ if (!fsg->config) -+ break; -+ if (w_index != 0) { -+ value = -EDOM; -+ break; -+ } -+ VDBG(fsg, "get interface\n"); -+ *(u8 *) req->buf = 0; -+ value = 1; -+ break; -+ -+ default: -+ VDBG(fsg, -+ "unknown control req %02x.%02x v%04x i%04x l%u\n", -+ ctrl->bRequestType, ctrl->bRequest, -+ w_value, w_index, le16_to_cpu(ctrl->wLength)); -+ } -+ -+ return value; -+} -+ -+ -+static int fsg_setup(struct usb_gadget *gadget, -+ const struct usb_ctrlrequest *ctrl) -+{ -+ struct fsg_dev *fsg = get_gadget_data(gadget); -+ int rc; -+ int w_length = le16_to_cpu(ctrl->wLength); -+ -+ ++fsg->ep0_req_tag; // Record arrival of a new request -+ fsg->ep0req->context = NULL; -+ fsg->ep0req->length = 0; -+ dump_msg(fsg, "ep0-setup", (u8 *) ctrl, sizeof(*ctrl)); -+ -+ if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_CLASS) -+ rc = class_setup_req(fsg, ctrl); -+ else -+ rc = standard_setup_req(fsg, ctrl); -+ -+ /* Respond with data/status or defer until later? */ -+ if (rc >= 0 && rc != DELAYED_STATUS) { -+ rc = min(rc, w_length); -+ fsg->ep0req->length = rc; -+ fsg->ep0req->zero = rc < w_length; -+ fsg->ep0req_name = (ctrl->bRequestType & USB_DIR_IN ? -+ "ep0-in" : "ep0-out"); -+ rc = ep0_queue(fsg); -+ } -+ -+ /* Device either stalls (rc < 0) or reports success */ -+ return rc; -+} -+ -+ -+/*-------------------------------------------------------------------------*/ -+ -+/* All the following routines run in process context */ -+ -+ -+/* Use this for bulk or interrupt transfers, not ep0 */ -+static void start_transfer(struct fsg_dev *fsg, struct usb_ep *ep, -+ struct usb_request *req, int *pbusy, -+ enum fsg_buffer_state *state) -+{ -+ int rc; -+ -+ if (ep == fsg->bulk_in) -+ dump_msg(fsg, "bulk-in", req->buf, req->length); -+ else if (ep == fsg->intr_in) -+ dump_msg(fsg, "intr-in", req->buf, req->length); -+ -+ spin_lock_irq(&fsg->lock); -+ *pbusy = 1; -+ *state = BUF_STATE_BUSY; -+ spin_unlock_irq(&fsg->lock); -+ rc = usb_ep_queue(ep, req, GFP_KERNEL); -+ if (rc != 0) { -+ *pbusy = 0; -+ *state = BUF_STATE_EMPTY; -+ -+ /* We can't do much more than wait for a reset */ -+ -+ /* Note: currently the net2280 driver fails zero-length -+ * submissions if DMA is enabled. */ -+ if (rc != -ESHUTDOWN && !(rc == -EOPNOTSUPP && -+ req->length == 0)) -+ WARNING(fsg, "error in submission: %s --> %d\n", -+ ep->name, rc); -+ } -+} -+ -+ -+static int sleep_thread(struct fsg_dev *fsg) -+{ -+ int rc = 0; -+ -+ /* Wait until a signal arrives or we are woken up */ -+ for (;;) { -+ try_to_freeze(); -+ set_current_state(TASK_INTERRUPTIBLE); -+ if (signal_pending(current)) { -+ rc = -EINTR; -+ break; -+ } -+ if (fsg->thread_wakeup_needed) -+ break; -+ schedule(); -+ } -+ __set_current_state(TASK_RUNNING); -+ fsg->thread_wakeup_needed = 0; -+ return rc; -+} -+ -+ -+/*-------------------------------------------------------------------------*/ -+ -+static int do_read(struct fsg_dev *fsg) -+{ -+ struct fsg_lun *curlun = fsg->curlun; -+ u32 lba; -+ struct fsg_buffhd *bh; -+ int rc; -+ u32 amount_left; -+ loff_t file_offset, file_offset_tmp; -+ unsigned int amount; -+ ssize_t nread; -+ -+ /* Get the starting Logical Block Address and check that it's -+ * not too big */ -+ if (fsg->cmnd[0] == READ_6) -+ lba = get_unaligned_be24(&fsg->cmnd[1]); -+ else { -+ lba = get_unaligned_be32(&fsg->cmnd[2]); -+ -+ /* We allow DPO (Disable Page Out = don't save data in the -+ * cache) and FUA (Force Unit Access = don't read from the -+ * cache), but we don't implement them. */ -+ if ((fsg->cmnd[1] & ~0x18) != 0) { -+ curlun->sense_data = SS_INVALID_FIELD_IN_CDB; -+ return -EINVAL; -+ } -+ } -+ if (lba >= curlun->num_sectors) { -+ curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; -+ return -EINVAL; -+ } -+ file_offset = ((loff_t) lba) << curlun->blkbits; -+ -+ /* Carry out the file reads */ -+ amount_left = fsg->data_size_from_cmnd; -+ if (unlikely(amount_left == 0)) -+ return -EIO; // No default reply -+ -+ for (;;) { -+ -+ /* Figure out how much we need to read: -+ * Try to read the remaining amount. -+ * But don't read more than the buffer size. -+ * And don't try to read past the end of the file. -+ */ -+ amount = min((unsigned int) amount_left, mod_data.buflen); -+ amount = min((loff_t) amount, -+ curlun->file_length - file_offset); -+ -+ /* Wait for the next buffer to become available */ -+ bh = fsg->next_buffhd_to_fill; -+ while (bh->state != BUF_STATE_EMPTY) { -+ rc = sleep_thread(fsg); -+ if (rc) -+ return rc; -+ } -+ -+ /* If we were asked to read past the end of file, -+ * end with an empty buffer. */ -+ if (amount == 0) { -+ curlun->sense_data = -+ SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; -+ curlun->sense_data_info = file_offset >> curlun->blkbits; -+ curlun->info_valid = 1; -+ bh->inreq->length = 0; -+ bh->state = BUF_STATE_FULL; -+ break; -+ } -+ -+ /* Perform the read */ -+ file_offset_tmp = file_offset; -+ nread = vfs_read(curlun->filp, -+ (char __user *) bh->buf, -+ amount, &file_offset_tmp); -+ VLDBG(curlun, "file read %u @ %llu -> %d\n", amount, -+ (unsigned long long) file_offset, -+ (int) nread); -+ if (signal_pending(current)) -+ return -EINTR; -+ -+ if (nread < 0) { -+ LDBG(curlun, "error in file read: %d\n", -+ (int) nread); -+ nread = 0; -+ } else if (nread < amount) { -+ LDBG(curlun, "partial file read: %d/%u\n", -+ (int) nread, amount); -+ nread = round_down(nread, curlun->blksize); -+ } -+ file_offset += nread; -+ amount_left -= nread; -+ fsg->residue -= nread; -+ -+ /* Except at the end of the transfer, nread will be -+ * equal to the buffer size, which is divisible by the -+ * bulk-in maxpacket size. -+ */ -+ bh->inreq->length = nread; -+ bh->state = BUF_STATE_FULL; -+ -+ /* If an error occurred, report it and its position */ -+ if (nread < amount) { -+ curlun->sense_data = SS_UNRECOVERED_READ_ERROR; -+ curlun->sense_data_info = file_offset >> curlun->blkbits; -+ curlun->info_valid = 1; -+ break; -+ } -+ -+ if (amount_left == 0) -+ break; // No more left to read -+ -+ /* Send this buffer and go read some more */ -+ bh->inreq->zero = 0; -+ start_transfer(fsg, fsg->bulk_in, bh->inreq, -+ &bh->inreq_busy, &bh->state); -+ fsg->next_buffhd_to_fill = bh->next; -+ } -+ -+ return -EIO; // No default reply -+} -+ -+ -+/*-------------------------------------------------------------------------*/ -+ -+static int do_write(struct fsg_dev *fsg) -+{ -+ struct fsg_lun *curlun = fsg->curlun; -+ u32 lba; -+ struct fsg_buffhd *bh; -+ int get_some_more; -+ u32 amount_left_to_req, amount_left_to_write; -+ loff_t usb_offset, file_offset, file_offset_tmp; -+ unsigned int amount; -+ ssize_t nwritten; -+ int rc; -+ -+ if (curlun->ro) { -+ curlun->sense_data = SS_WRITE_PROTECTED; -+ return -EINVAL; -+ } -+ spin_lock(&curlun->filp->f_lock); -+ curlun->filp->f_flags &= ~O_SYNC; // Default is not to wait -+ spin_unlock(&curlun->filp->f_lock); -+ -+ /* Get the starting Logical Block Address and check that it's -+ * not too big */ -+ if (fsg->cmnd[0] == WRITE_6) -+ lba = get_unaligned_be24(&fsg->cmnd[1]); -+ else { -+ lba = get_unaligned_be32(&fsg->cmnd[2]); -+ -+ /* We allow DPO (Disable Page Out = don't save data in the -+ * cache) and FUA (Force Unit Access = write directly to the -+ * medium). We don't implement DPO; we implement FUA by -+ * performing synchronous output. */ -+ if ((fsg->cmnd[1] & ~0x18) != 0) { -+ curlun->sense_data = SS_INVALID_FIELD_IN_CDB; -+ return -EINVAL; -+ } -+ /* FUA */ -+ if (!curlun->nofua && (fsg->cmnd[1] & 0x08)) { -+ spin_lock(&curlun->filp->f_lock); -+ curlun->filp->f_flags |= O_DSYNC; -+ spin_unlock(&curlun->filp->f_lock); -+ } -+ } -+ if (lba >= curlun->num_sectors) { -+ curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; -+ return -EINVAL; -+ } -+ -+ /* Carry out the file writes */ -+ get_some_more = 1; -+ file_offset = usb_offset = ((loff_t) lba) << curlun->blkbits; -+ amount_left_to_req = amount_left_to_write = fsg->data_size_from_cmnd; -+ -+ while (amount_left_to_write > 0) { -+ -+ /* Queue a request for more data from the host */ -+ bh = fsg->next_buffhd_to_fill; -+ if (bh->state == BUF_STATE_EMPTY && get_some_more) { -+ -+ /* Figure out how much we want to get: -+ * Try to get the remaining amount, -+ * but not more than the buffer size. -+ */ -+ amount = min(amount_left_to_req, mod_data.buflen); -+ -+ /* Beyond the end of the backing file? */ -+ if (usb_offset >= curlun->file_length) { -+ get_some_more = 0; -+ curlun->sense_data = -+ SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; -+ curlun->sense_data_info = usb_offset >> curlun->blkbits; -+ curlun->info_valid = 1; -+ continue; -+ } -+ -+ /* Get the next buffer */ -+ usb_offset += amount; -+ fsg->usb_amount_left -= amount; -+ amount_left_to_req -= amount; -+ if (amount_left_to_req == 0) -+ get_some_more = 0; -+ -+ /* Except at the end of the transfer, amount will be -+ * equal to the buffer size, which is divisible by -+ * the bulk-out maxpacket size. -+ */ -+ set_bulk_out_req_length(fsg, bh, amount); -+ start_transfer(fsg, fsg->bulk_out, bh->outreq, -+ &bh->outreq_busy, &bh->state); -+ fsg->next_buffhd_to_fill = bh->next; -+ continue; -+ } -+ -+ /* Write the received data to the backing file */ -+ bh = fsg->next_buffhd_to_drain; -+ if (bh->state == BUF_STATE_EMPTY && !get_some_more) -+ break; // We stopped early -+ if (bh->state == BUF_STATE_FULL) { -+ smp_rmb(); -+ fsg->next_buffhd_to_drain = bh->next; -+ bh->state = BUF_STATE_EMPTY; -+ -+ /* Did something go wrong with the transfer? */ -+ if (bh->outreq->status != 0) { -+ curlun->sense_data = SS_COMMUNICATION_FAILURE; -+ curlun->sense_data_info = file_offset >> curlun->blkbits; -+ curlun->info_valid = 1; -+ break; -+ } -+ -+ amount = bh->outreq->actual; -+ if (curlun->file_length - file_offset < amount) { -+ LERROR(curlun, -+ "write %u @ %llu beyond end %llu\n", -+ amount, (unsigned long long) file_offset, -+ (unsigned long long) curlun->file_length); -+ amount = curlun->file_length - file_offset; -+ } -+ -+ /* Don't accept excess data. The spec doesn't say -+ * what to do in this case. We'll ignore the error. -+ */ -+ amount = min(amount, bh->bulk_out_intended_length); -+ -+ /* Don't write a partial block */ -+ amount = round_down(amount, curlun->blksize); -+ if (amount == 0) -+ goto empty_write; -+ -+ /* Perform the write */ -+ file_offset_tmp = file_offset; -+ nwritten = vfs_write(curlun->filp, -+ (char __user *) bh->buf, -+ amount, &file_offset_tmp); -+ VLDBG(curlun, "file write %u @ %llu -> %d\n", amount, -+ (unsigned long long) file_offset, -+ (int) nwritten); -+ if (signal_pending(current)) -+ return -EINTR; // Interrupted! -+ -+ if (nwritten < 0) { -+ LDBG(curlun, "error in file write: %d\n", -+ (int) nwritten); -+ nwritten = 0; -+ } else if (nwritten < amount) { -+ LDBG(curlun, "partial file write: %d/%u\n", -+ (int) nwritten, amount); -+ nwritten = round_down(nwritten, curlun->blksize); -+ } -+ file_offset += nwritten; -+ amount_left_to_write -= nwritten; -+ fsg->residue -= nwritten; -+ -+ /* If an error occurred, report it and its position */ -+ if (nwritten < amount) { -+ curlun->sense_data = SS_WRITE_ERROR; -+ curlun->sense_data_info = file_offset >> curlun->blkbits; -+ curlun->info_valid = 1; -+ break; -+ } -+ -+ empty_write: -+ /* Did the host decide to stop early? */ -+ if (bh->outreq->actual < bh->bulk_out_intended_length) { -+ fsg->short_packet_received = 1; -+ break; -+ } -+ continue; -+ } -+ -+ /* Wait for something to happen */ -+ rc = sleep_thread(fsg); -+ if (rc) -+ return rc; -+ } -+ -+ return -EIO; // No default reply -+} -+ -+ -+/*-------------------------------------------------------------------------*/ -+ -+static int do_synchronize_cache(struct fsg_dev *fsg) -+{ -+ struct fsg_lun *curlun = fsg->curlun; -+ int rc; -+ -+ /* We ignore the requested LBA and write out all file's -+ * dirty data buffers. */ -+ rc = fsg_lun_fsync_sub(curlun); -+ if (rc) -+ curlun->sense_data = SS_WRITE_ERROR; -+ return 0; -+} -+ -+ -+/*-------------------------------------------------------------------------*/ -+ -+static void invalidate_sub(struct fsg_lun *curlun) -+{ -+ struct file *filp = curlun->filp; -+ struct inode *inode = filp->f_path.dentry->d_inode; -+ unsigned long rc; -+ -+ rc = invalidate_mapping_pages(inode->i_mapping, 0, -1); -+ VLDBG(curlun, "invalidate_mapping_pages -> %ld\n", rc); -+} -+ -+static int do_verify(struct fsg_dev *fsg) -+{ -+ struct fsg_lun *curlun = fsg->curlun; -+ u32 lba; -+ u32 verification_length; -+ struct fsg_buffhd *bh = fsg->next_buffhd_to_fill; -+ loff_t file_offset, file_offset_tmp; -+ u32 amount_left; -+ unsigned int amount; -+ ssize_t nread; -+ -+ /* Get the starting Logical Block Address and check that it's -+ * not too big */ -+ lba = get_unaligned_be32(&fsg->cmnd[2]); -+ if (lba >= curlun->num_sectors) { -+ curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; -+ return -EINVAL; -+ } -+ -+ /* We allow DPO (Disable Page Out = don't save data in the -+ * cache) but we don't implement it. */ -+ if ((fsg->cmnd[1] & ~0x10) != 0) { -+ curlun->sense_data = SS_INVALID_FIELD_IN_CDB; -+ return -EINVAL; -+ } -+ -+ verification_length = get_unaligned_be16(&fsg->cmnd[7]); -+ if (unlikely(verification_length == 0)) -+ return -EIO; // No default reply -+ -+ /* Prepare to carry out the file verify */ -+ amount_left = verification_length << curlun->blkbits; -+ file_offset = ((loff_t) lba) << curlun->blkbits; -+ -+ /* Write out all the dirty buffers before invalidating them */ -+ fsg_lun_fsync_sub(curlun); -+ if (signal_pending(current)) -+ return -EINTR; -+ -+ invalidate_sub(curlun); -+ if (signal_pending(current)) -+ return -EINTR; -+ -+ /* Just try to read the requested blocks */ -+ while (amount_left > 0) { -+ -+ /* Figure out how much we need to read: -+ * Try to read the remaining amount, but not more than -+ * the buffer size. -+ * And don't try to read past the end of the file. -+ */ -+ amount = min((unsigned int) amount_left, mod_data.buflen); -+ amount = min((loff_t) amount, -+ curlun->file_length - file_offset); -+ if (amount == 0) { -+ curlun->sense_data = -+ SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; -+ curlun->sense_data_info = file_offset >> curlun->blkbits; -+ curlun->info_valid = 1; -+ break; -+ } -+ -+ /* Perform the read */ -+ file_offset_tmp = file_offset; -+ nread = vfs_read(curlun->filp, -+ (char __user *) bh->buf, -+ amount, &file_offset_tmp); -+ VLDBG(curlun, "file read %u @ %llu -> %d\n", amount, -+ (unsigned long long) file_offset, -+ (int) nread); -+ if (signal_pending(current)) -+ return -EINTR; -+ -+ if (nread < 0) { -+ LDBG(curlun, "error in file verify: %d\n", -+ (int) nread); -+ nread = 0; -+ } else if (nread < amount) { -+ LDBG(curlun, "partial file verify: %d/%u\n", -+ (int) nread, amount); -+ nread = round_down(nread, curlun->blksize); -+ } -+ if (nread == 0) { -+ curlun->sense_data = SS_UNRECOVERED_READ_ERROR; -+ curlun->sense_data_info = file_offset >> curlun->blkbits; -+ curlun->info_valid = 1; -+ break; -+ } -+ file_offset += nread; -+ amount_left -= nread; -+ } -+ return 0; -+} -+ -+ -+/*-------------------------------------------------------------------------*/ -+ -+static int do_inquiry(struct fsg_dev *fsg, struct fsg_buffhd *bh) -+{ -+ u8 *buf = (u8 *) bh->buf; -+ -+ static char vendor_id[] = "Linux "; -+ static char product_disk_id[] = "File-Stor Gadget"; -+ static char product_cdrom_id[] = "File-CD Gadget "; -+ -+ if (!fsg->curlun) { // Unsupported LUNs are okay -+ fsg->bad_lun_okay = 1; -+ memset(buf, 0, 36); -+ buf[0] = 0x7f; // Unsupported, no device-type -+ buf[4] = 31; // Additional length -+ return 36; -+ } -+ -+ memset(buf, 0, 8); -+ buf[0] = (mod_data.cdrom ? TYPE_ROM : TYPE_DISK); -+ if (mod_data.removable) -+ buf[1] = 0x80; -+ buf[2] = 2; // ANSI SCSI level 2 -+ buf[3] = 2; // SCSI-2 INQUIRY data format -+ buf[4] = 31; // Additional length -+ // No special options -+ sprintf(buf + 8, "%-8s%-16s%04x", vendor_id, -+ (mod_data.cdrom ? product_cdrom_id : -+ product_disk_id), -+ mod_data.release); -+ return 36; -+} -+ -+ -+static int do_request_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh) -+{ -+ struct fsg_lun *curlun = fsg->curlun; -+ u8 *buf = (u8 *) bh->buf; -+ u32 sd, sdinfo; -+ int valid; -+ -+ /* -+ * From the SCSI-2 spec., section 7.9 (Unit attention condition): -+ * -+ * If a REQUEST SENSE command is received from an initiator -+ * with a pending unit attention condition (before the target -+ * generates the contingent allegiance condition), then the -+ * target shall either: -+ * a) report any pending sense data and preserve the unit -+ * attention condition on the logical unit, or, -+ * b) report the unit attention condition, may discard any -+ * pending sense data, and clear the unit attention -+ * condition on the logical unit for that initiator. -+ * -+ * FSG normally uses option a); enable this code to use option b). -+ */ -+#if 0 -+ if (curlun && curlun->unit_attention_data != SS_NO_SENSE) { -+ curlun->sense_data = curlun->unit_attention_data; -+ curlun->unit_attention_data = SS_NO_SENSE; -+ } -+#endif -+ -+ if (!curlun) { // Unsupported LUNs are okay -+ fsg->bad_lun_okay = 1; -+ sd = SS_LOGICAL_UNIT_NOT_SUPPORTED; -+ sdinfo = 0; -+ valid = 0; -+ } else { -+ sd = curlun->sense_data; -+ sdinfo = curlun->sense_data_info; -+ valid = curlun->info_valid << 7; -+ curlun->sense_data = SS_NO_SENSE; -+ curlun->sense_data_info = 0; -+ curlun->info_valid = 0; -+ } -+ -+ memset(buf, 0, 18); -+ buf[0] = valid | 0x70; // Valid, current error -+ buf[2] = SK(sd); -+ put_unaligned_be32(sdinfo, &buf[3]); /* Sense information */ -+ buf[7] = 18 - 8; // Additional sense length -+ buf[12] = ASC(sd); -+ buf[13] = ASCQ(sd); -+ return 18; -+} -+ -+ -+static int do_read_capacity(struct fsg_dev *fsg, struct fsg_buffhd *bh) -+{ -+ struct fsg_lun *curlun = fsg->curlun; -+ u32 lba = get_unaligned_be32(&fsg->cmnd[2]); -+ int pmi = fsg->cmnd[8]; -+ u8 *buf = (u8 *) bh->buf; -+ -+ /* Check the PMI and LBA fields */ -+ if (pmi > 1 || (pmi == 0 && lba != 0)) { -+ curlun->sense_data = SS_INVALID_FIELD_IN_CDB; -+ return -EINVAL; -+ } -+ -+ put_unaligned_be32(curlun->num_sectors - 1, &buf[0]); -+ /* Max logical block */ -+ put_unaligned_be32(curlun->blksize, &buf[4]); /* Block length */ -+ return 8; -+} -+ -+ -+static int do_read_header(struct fsg_dev *fsg, struct fsg_buffhd *bh) -+{ -+ struct fsg_lun *curlun = fsg->curlun; -+ int msf = fsg->cmnd[1] & 0x02; -+ u32 lba = get_unaligned_be32(&fsg->cmnd[2]); -+ u8 *buf = (u8 *) bh->buf; -+ -+ if ((fsg->cmnd[1] & ~0x02) != 0) { /* Mask away MSF */ -+ curlun->sense_data = SS_INVALID_FIELD_IN_CDB; -+ return -EINVAL; -+ } -+ if (lba >= curlun->num_sectors) { -+ curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; -+ return -EINVAL; -+ } -+ -+ memset(buf, 0, 8); -+ buf[0] = 0x01; /* 2048 bytes of user data, rest is EC */ -+ store_cdrom_address(&buf[4], msf, lba); -+ return 8; -+} -+ -+ -+static int do_read_toc(struct fsg_dev *fsg, struct fsg_buffhd *bh) -+{ -+ struct fsg_lun *curlun = fsg->curlun; -+ int msf = fsg->cmnd[1] & 0x02; -+ int start_track = fsg->cmnd[6]; -+ u8 *buf = (u8 *) bh->buf; -+ -+ if ((fsg->cmnd[1] & ~0x02) != 0 || /* Mask away MSF */ -+ start_track > 1) { -+ curlun->sense_data = SS_INVALID_FIELD_IN_CDB; -+ return -EINVAL; -+ } -+ -+ memset(buf, 0, 20); -+ buf[1] = (20-2); /* TOC data length */ -+ buf[2] = 1; /* First track number */ -+ buf[3] = 1; /* Last track number */ -+ buf[5] = 0x16; /* Data track, copying allowed */ -+ buf[6] = 0x01; /* Only track is number 1 */ -+ store_cdrom_address(&buf[8], msf, 0); -+ -+ buf[13] = 0x16; /* Lead-out track is data */ -+ buf[14] = 0xAA; /* Lead-out track number */ -+ store_cdrom_address(&buf[16], msf, curlun->num_sectors); -+ return 20; -+} -+ -+ -+static int do_mode_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh) -+{ -+ struct fsg_lun *curlun = fsg->curlun; -+ int mscmnd = fsg->cmnd[0]; -+ u8 *buf = (u8 *) bh->buf; -+ u8 *buf0 = buf; -+ int pc, page_code; -+ int changeable_values, all_pages; -+ int valid_page = 0; -+ int len, limit; -+ -+ if ((fsg->cmnd[1] & ~0x08) != 0) { // Mask away DBD -+ curlun->sense_data = SS_INVALID_FIELD_IN_CDB; -+ return -EINVAL; -+ } -+ pc = fsg->cmnd[2] >> 6; -+ page_code = fsg->cmnd[2] & 0x3f; -+ if (pc == 3) { -+ curlun->sense_data = SS_SAVING_PARAMETERS_NOT_SUPPORTED; -+ return -EINVAL; -+ } -+ changeable_values = (pc == 1); -+ all_pages = (page_code == 0x3f); -+ -+ /* Write the mode parameter header. Fixed values are: default -+ * medium type, no cache control (DPOFUA), and no block descriptors. -+ * The only variable value is the WriteProtect bit. We will fill in -+ * the mode data length later. */ -+ memset(buf, 0, 8); -+ if (mscmnd == MODE_SENSE) { -+ buf[2] = (curlun->ro ? 0x80 : 0x00); // WP, DPOFUA -+ buf += 4; -+ limit = 255; -+ } else { // MODE_SENSE_10 -+ buf[3] = (curlun->ro ? 0x80 : 0x00); // WP, DPOFUA -+ buf += 8; -+ limit = 65535; // Should really be mod_data.buflen -+ } -+ -+ /* No block descriptors */ -+ -+ /* The mode pages, in numerical order. The only page we support -+ * is the Caching page. */ -+ if (page_code == 0x08 || all_pages) { -+ valid_page = 1; -+ buf[0] = 0x08; // Page code -+ buf[1] = 10; // Page length -+ memset(buf+2, 0, 10); // None of the fields are changeable -+ -+ if (!changeable_values) { -+ buf[2] = 0x04; // Write cache enable, -+ // Read cache not disabled -+ // No cache retention priorities -+ put_unaligned_be16(0xffff, &buf[4]); -+ /* Don't disable prefetch */ -+ /* Minimum prefetch = 0 */ -+ put_unaligned_be16(0xffff, &buf[8]); -+ /* Maximum prefetch */ -+ put_unaligned_be16(0xffff, &buf[10]); -+ /* Maximum prefetch ceiling */ -+ } -+ buf += 12; -+ } -+ -+ /* Check that a valid page was requested and the mode data length -+ * isn't too long. */ -+ len = buf - buf0; -+ if (!valid_page || len > limit) { -+ curlun->sense_data = SS_INVALID_FIELD_IN_CDB; -+ return -EINVAL; -+ } -+ -+ /* Store the mode data length */ -+ if (mscmnd == MODE_SENSE) -+ buf0[0] = len - 1; -+ else -+ put_unaligned_be16(len - 2, buf0); -+ return len; -+} -+ -+ -+static int do_start_stop(struct fsg_dev *fsg) -+{ -+ struct fsg_lun *curlun = fsg->curlun; -+ int loej, start; -+ -+ if (!mod_data.removable) { -+ curlun->sense_data = SS_INVALID_COMMAND; -+ return -EINVAL; -+ } -+ -+ // int immed = fsg->cmnd[1] & 0x01; -+ loej = fsg->cmnd[4] & 0x02; -+ start = fsg->cmnd[4] & 0x01; -+ -+#ifdef CONFIG_USB_FILE_STORAGE_TEST -+ if ((fsg->cmnd[1] & ~0x01) != 0 || // Mask away Immed -+ (fsg->cmnd[4] & ~0x03) != 0) { // Mask LoEj, Start -+ curlun->sense_data = SS_INVALID_FIELD_IN_CDB; -+ return -EINVAL; -+ } -+ -+ if (!start) { -+ -+ /* Are we allowed to unload the media? */ -+ if (curlun->prevent_medium_removal) { -+ LDBG(curlun, "unload attempt prevented\n"); -+ curlun->sense_data = SS_MEDIUM_REMOVAL_PREVENTED; -+ return -EINVAL; -+ } -+ if (loej) { // Simulate an unload/eject -+ up_read(&fsg->filesem); -+ down_write(&fsg->filesem); -+ fsg_lun_close(curlun); -+ up_write(&fsg->filesem); -+ down_read(&fsg->filesem); -+ } -+ } else { -+ -+ /* Our emulation doesn't support mounting; the medium is -+ * available for use as soon as it is loaded. */ -+ if (!fsg_lun_is_open(curlun)) { -+ curlun->sense_data = SS_MEDIUM_NOT_PRESENT; -+ return -EINVAL; -+ } -+ } -+#endif -+ return 0; -+} -+ -+ -+static int do_prevent_allow(struct fsg_dev *fsg) -+{ -+ struct fsg_lun *curlun = fsg->curlun; -+ int prevent; -+ -+ if (!mod_data.removable) { -+ curlun->sense_data = SS_INVALID_COMMAND; -+ return -EINVAL; -+ } -+ -+ prevent = fsg->cmnd[4] & 0x01; -+ if ((fsg->cmnd[4] & ~0x01) != 0) { // Mask away Prevent -+ curlun->sense_data = SS_INVALID_FIELD_IN_CDB; -+ return -EINVAL; -+ } -+ -+ if (curlun->prevent_medium_removal && !prevent) -+ fsg_lun_fsync_sub(curlun); -+ curlun->prevent_medium_removal = prevent; -+ return 0; -+} -+ -+ -+static int do_read_format_capacities(struct fsg_dev *fsg, -+ struct fsg_buffhd *bh) -+{ -+ struct fsg_lun *curlun = fsg->curlun; -+ u8 *buf = (u8 *) bh->buf; -+ -+ buf[0] = buf[1] = buf[2] = 0; -+ buf[3] = 8; // Only the Current/Maximum Capacity Descriptor -+ buf += 4; -+ -+ put_unaligned_be32(curlun->num_sectors, &buf[0]); -+ /* Number of blocks */ -+ put_unaligned_be32(curlun->blksize, &buf[4]); /* Block length */ -+ buf[4] = 0x02; /* Current capacity */ -+ return 12; -+} -+ -+ -+static int do_mode_select(struct fsg_dev *fsg, struct fsg_buffhd *bh) -+{ -+ struct fsg_lun *curlun = fsg->curlun; -+ -+ /* We don't support MODE SELECT */ -+ curlun->sense_data = SS_INVALID_COMMAND; -+ return -EINVAL; -+} -+ -+ -+/*-------------------------------------------------------------------------*/ -+ -+static int halt_bulk_in_endpoint(struct fsg_dev *fsg) -+{ -+ int rc; -+ -+ rc = fsg_set_halt(fsg, fsg->bulk_in); -+ if (rc == -EAGAIN) -+ VDBG(fsg, "delayed bulk-in endpoint halt\n"); -+ while (rc != 0) { -+ if (rc != -EAGAIN) { -+ WARNING(fsg, "usb_ep_set_halt -> %d\n", rc); -+ rc = 0; -+ break; -+ } -+ -+ /* Wait for a short time and then try again */ -+ if (msleep_interruptible(100) != 0) -+ return -EINTR; -+ rc = usb_ep_set_halt(fsg->bulk_in); -+ } -+ return rc; -+} -+ -+static int wedge_bulk_in_endpoint(struct fsg_dev *fsg) -+{ -+ int rc; -+ -+ DBG(fsg, "bulk-in set wedge\n"); -+ rc = usb_ep_set_wedge(fsg->bulk_in); -+ if (rc == -EAGAIN) -+ VDBG(fsg, "delayed bulk-in endpoint wedge\n"); -+ while (rc != 0) { -+ if (rc != -EAGAIN) { -+ WARNING(fsg, "usb_ep_set_wedge -> %d\n", rc); -+ rc = 0; -+ break; -+ } -+ -+ /* Wait for a short time and then try again */ -+ if (msleep_interruptible(100) != 0) -+ return -EINTR; -+ rc = usb_ep_set_wedge(fsg->bulk_in); -+ } -+ return rc; -+} -+ -+static int throw_away_data(struct fsg_dev *fsg) -+{ -+ struct fsg_buffhd *bh; -+ u32 amount; -+ int rc; -+ -+ while ((bh = fsg->next_buffhd_to_drain)->state != BUF_STATE_EMPTY || -+ fsg->usb_amount_left > 0) { -+ -+ /* Throw away the data in a filled buffer */ -+ if (bh->state == BUF_STATE_FULL) { -+ smp_rmb(); -+ bh->state = BUF_STATE_EMPTY; -+ fsg->next_buffhd_to_drain = bh->next; -+ -+ /* A short packet or an error ends everything */ -+ if (bh->outreq->actual < bh->bulk_out_intended_length || -+ bh->outreq->status != 0) { -+ raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT); -+ return -EINTR; -+ } -+ continue; -+ } -+ -+ /* Try to submit another request if we need one */ -+ bh = fsg->next_buffhd_to_fill; -+ if (bh->state == BUF_STATE_EMPTY && fsg->usb_amount_left > 0) { -+ amount = min(fsg->usb_amount_left, -+ (u32) mod_data.buflen); -+ -+ /* Except at the end of the transfer, amount will be -+ * equal to the buffer size, which is divisible by -+ * the bulk-out maxpacket size. -+ */ -+ set_bulk_out_req_length(fsg, bh, amount); -+ start_transfer(fsg, fsg->bulk_out, bh->outreq, -+ &bh->outreq_busy, &bh->state); -+ fsg->next_buffhd_to_fill = bh->next; -+ fsg->usb_amount_left -= amount; -+ continue; -+ } -+ -+ /* Otherwise wait for something to happen */ -+ rc = sleep_thread(fsg); -+ if (rc) -+ return rc; -+ } -+ return 0; -+} -+ -+ -+static int finish_reply(struct fsg_dev *fsg) -+{ -+ struct fsg_buffhd *bh = fsg->next_buffhd_to_fill; -+ int rc = 0; -+ -+ switch (fsg->data_dir) { -+ case DATA_DIR_NONE: -+ break; // Nothing to send -+ -+ /* If we don't know whether the host wants to read or write, -+ * this must be CB or CBI with an unknown command. We mustn't -+ * try to send or receive any data. So stall both bulk pipes -+ * if we can and wait for a reset. */ -+ case DATA_DIR_UNKNOWN: -+ if (mod_data.can_stall) { -+ fsg_set_halt(fsg, fsg->bulk_out); -+ rc = halt_bulk_in_endpoint(fsg); -+ } -+ break; -+ -+ /* All but the last buffer of data must have already been sent */ -+ case DATA_DIR_TO_HOST: -+ if (fsg->data_size == 0) -+ ; // Nothing to send -+ -+ /* If there's no residue, simply send the last buffer */ -+ else if (fsg->residue == 0) { -+ bh->inreq->zero = 0; -+ start_transfer(fsg, fsg->bulk_in, bh->inreq, -+ &bh->inreq_busy, &bh->state); -+ fsg->next_buffhd_to_fill = bh->next; -+ } -+ -+ /* There is a residue. For CB and CBI, simply mark the end -+ * of the data with a short packet. However, if we are -+ * allowed to stall, there was no data at all (residue == -+ * data_size), and the command failed (invalid LUN or -+ * sense data is set), then halt the bulk-in endpoint -+ * instead. */ -+ else if (!transport_is_bbb()) { -+ if (mod_data.can_stall && -+ fsg->residue == fsg->data_size && -+ (!fsg->curlun || fsg->curlun->sense_data != SS_NO_SENSE)) { -+ bh->state = BUF_STATE_EMPTY; -+ rc = halt_bulk_in_endpoint(fsg); -+ } else { -+ bh->inreq->zero = 1; -+ start_transfer(fsg, fsg->bulk_in, bh->inreq, -+ &bh->inreq_busy, &bh->state); -+ fsg->next_buffhd_to_fill = bh->next; -+ } -+ } -+ -+ /* -+ * For Bulk-only, mark the end of the data with a short -+ * packet. If we are allowed to stall, halt the bulk-in -+ * endpoint. (Note: This violates the Bulk-Only Transport -+ * specification, which requires us to pad the data if we -+ * don't halt the endpoint. Presumably nobody will mind.) -+ */ -+ else { -+ bh->inreq->zero = 1; -+ start_transfer(fsg, fsg->bulk_in, bh->inreq, -+ &bh->inreq_busy, &bh->state); -+ fsg->next_buffhd_to_fill = bh->next; -+ if (mod_data.can_stall) -+ rc = halt_bulk_in_endpoint(fsg); -+ } -+ break; -+ -+ /* We have processed all we want from the data the host has sent. -+ * There may still be outstanding bulk-out requests. */ -+ case DATA_DIR_FROM_HOST: -+ if (fsg->residue == 0) -+ ; // Nothing to receive -+ -+ /* Did the host stop sending unexpectedly early? */ -+ else if (fsg->short_packet_received) { -+ raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT); -+ rc = -EINTR; -+ } -+ -+ /* We haven't processed all the incoming data. Even though -+ * we may be allowed to stall, doing so would cause a race. -+ * The controller may already have ACK'ed all the remaining -+ * bulk-out packets, in which case the host wouldn't see a -+ * STALL. Not realizing the endpoint was halted, it wouldn't -+ * clear the halt -- leading to problems later on. */ -+#if 0 -+ else if (mod_data.can_stall) { -+ fsg_set_halt(fsg, fsg->bulk_out); -+ raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT); -+ rc = -EINTR; -+ } -+#endif -+ -+ /* We can't stall. Read in the excess data and throw it -+ * all away. */ -+ else -+ rc = throw_away_data(fsg); -+ break; -+ } -+ return rc; -+} -+ -+ -+static int send_status(struct fsg_dev *fsg) -+{ -+ struct fsg_lun *curlun = fsg->curlun; -+ struct fsg_buffhd *bh; -+ int rc; -+ u8 status = US_BULK_STAT_OK; -+ u32 sd, sdinfo = 0; -+ -+ /* Wait for the next buffer to become available */ -+ bh = fsg->next_buffhd_to_fill; -+ while (bh->state != BUF_STATE_EMPTY) { -+ rc = sleep_thread(fsg); -+ if (rc) -+ return rc; -+ } -+ -+ if (curlun) { -+ sd = curlun->sense_data; -+ sdinfo = curlun->sense_data_info; -+ } else if (fsg->bad_lun_okay) -+ sd = SS_NO_SENSE; -+ else -+ sd = SS_LOGICAL_UNIT_NOT_SUPPORTED; -+ -+ if (fsg->phase_error) { -+ DBG(fsg, "sending phase-error status\n"); -+ status = US_BULK_STAT_PHASE; -+ sd = SS_INVALID_COMMAND; -+ } else if (sd != SS_NO_SENSE) { -+ DBG(fsg, "sending command-failure status\n"); -+ status = US_BULK_STAT_FAIL; -+ VDBG(fsg, " sense data: SK x%02x, ASC x%02x, ASCQ x%02x;" -+ " info x%x\n", -+ SK(sd), ASC(sd), ASCQ(sd), sdinfo); -+ } -+ -+ if (transport_is_bbb()) { -+ struct bulk_cs_wrap *csw = bh->buf; -+ -+ /* Store and send the Bulk-only CSW */ -+ csw->Signature = cpu_to_le32(US_BULK_CS_SIGN); -+ csw->Tag = fsg->tag; -+ csw->Residue = cpu_to_le32(fsg->residue); -+ csw->Status = status; -+ -+ bh->inreq->length = US_BULK_CS_WRAP_LEN; -+ bh->inreq->zero = 0; -+ start_transfer(fsg, fsg->bulk_in, bh->inreq, -+ &bh->inreq_busy, &bh->state); -+ -+ } else if (mod_data.transport_type == USB_PR_CB) { -+ -+ /* Control-Bulk transport has no status phase! */ -+ return 0; -+ -+ } else { // USB_PR_CBI -+ struct interrupt_data *buf = bh->buf; -+ -+ /* Store and send the Interrupt data. UFI sends the ASC -+ * and ASCQ bytes. Everything else sends a Type (which -+ * is always 0) and the status Value. */ -+ if (mod_data.protocol_type == USB_SC_UFI) { -+ buf->bType = ASC(sd); -+ buf->bValue = ASCQ(sd); -+ } else { -+ buf->bType = 0; -+ buf->bValue = status; -+ } -+ fsg->intreq->length = CBI_INTERRUPT_DATA_LEN; -+ -+ fsg->intr_buffhd = bh; // Point to the right buffhd -+ fsg->intreq->buf = bh->inreq->buf; -+ fsg->intreq->context = bh; -+ start_transfer(fsg, fsg->intr_in, fsg->intreq, -+ &fsg->intreq_busy, &bh->state); -+ } -+ -+ fsg->next_buffhd_to_fill = bh->next; -+ return 0; -+} -+ -+ -+/*-------------------------------------------------------------------------*/ -+ -+/* Check whether the command is properly formed and whether its data size -+ * and direction agree with the values we already have. */ -+static int check_command(struct fsg_dev *fsg, int cmnd_size, -+ enum data_direction data_dir, unsigned int mask, -+ int needs_medium, const char *name) -+{ -+ int i; -+ int lun = fsg->cmnd[1] >> 5; -+ static const char dirletter[4] = {'u', 'o', 'i', 'n'}; -+ char hdlen[20]; -+ struct fsg_lun *curlun; -+ -+ /* Adjust the expected cmnd_size for protocol encapsulation padding. -+ * Transparent SCSI doesn't pad. */ -+ if (protocol_is_scsi()) -+ ; -+ -+ /* There's some disagreement as to whether RBC pads commands or not. -+ * We'll play it safe and accept either form. */ -+ else if (mod_data.protocol_type == USB_SC_RBC) { -+ if (fsg->cmnd_size == 12) -+ cmnd_size = 12; -+ -+ /* All the other protocols pad to 12 bytes */ -+ } else -+ cmnd_size = 12; -+ -+ hdlen[0] = 0; -+ if (fsg->data_dir != DATA_DIR_UNKNOWN) -+ sprintf(hdlen, ", H%c=%u", dirletter[(int) fsg->data_dir], -+ fsg->data_size); -+ VDBG(fsg, "SCSI command: %s; Dc=%d, D%c=%u; Hc=%d%s\n", -+ name, cmnd_size, dirletter[(int) data_dir], -+ fsg->data_size_from_cmnd, fsg->cmnd_size, hdlen); -+ -+ /* We can't reply at all until we know the correct data direction -+ * and size. */ -+ if (fsg->data_size_from_cmnd == 0) -+ data_dir = DATA_DIR_NONE; -+ if (fsg->data_dir == DATA_DIR_UNKNOWN) { // CB or CBI -+ fsg->data_dir = data_dir; -+ fsg->data_size = fsg->data_size_from_cmnd; -+ -+ } else { // Bulk-only -+ if (fsg->data_size < fsg->data_size_from_cmnd) { -+ -+ /* Host data size < Device data size is a phase error. -+ * Carry out the command, but only transfer as much -+ * as we are allowed. */ -+ fsg->data_size_from_cmnd = fsg->data_size; -+ fsg->phase_error = 1; -+ } -+ } -+ fsg->residue = fsg->usb_amount_left = fsg->data_size; -+ -+ /* Conflicting data directions is a phase error */ -+ if (fsg->data_dir != data_dir && fsg->data_size_from_cmnd > 0) { -+ fsg->phase_error = 1; -+ return -EINVAL; -+ } -+ -+ /* Verify the length of the command itself */ -+ if (cmnd_size != fsg->cmnd_size) { -+ -+ /* Special case workaround: There are plenty of buggy SCSI -+ * implementations. Many have issues with cbw->Length -+ * field passing a wrong command size. For those cases we -+ * always try to work around the problem by using the length -+ * sent by the host side provided it is at least as large -+ * as the correct command length. -+ * Examples of such cases would be MS-Windows, which issues -+ * REQUEST SENSE with cbw->Length == 12 where it should -+ * be 6, and xbox360 issuing INQUIRY, TEST UNIT READY and -+ * REQUEST SENSE with cbw->Length == 10 where it should -+ * be 6 as well. -+ */ -+ if (cmnd_size <= fsg->cmnd_size) { -+ DBG(fsg, "%s is buggy! Expected length %d " -+ "but we got %d\n", name, -+ cmnd_size, fsg->cmnd_size); -+ cmnd_size = fsg->cmnd_size; -+ } else { -+ fsg->phase_error = 1; -+ return -EINVAL; -+ } -+ } -+ -+ /* Check that the LUN values are consistent */ -+ if (transport_is_bbb()) { -+ if (fsg->lun != lun) -+ DBG(fsg, "using LUN %d from CBW, " -+ "not LUN %d from CDB\n", -+ fsg->lun, lun); -+ } -+ -+ /* Check the LUN */ -+ curlun = fsg->curlun; -+ if (curlun) { -+ if (fsg->cmnd[0] != REQUEST_SENSE) { -+ curlun->sense_data = SS_NO_SENSE; -+ curlun->sense_data_info = 0; -+ curlun->info_valid = 0; -+ } -+ } else { -+ fsg->bad_lun_okay = 0; -+ -+ /* INQUIRY and REQUEST SENSE commands are explicitly allowed -+ * to use unsupported LUNs; all others may not. */ -+ if (fsg->cmnd[0] != INQUIRY && -+ fsg->cmnd[0] != REQUEST_SENSE) { -+ DBG(fsg, "unsupported LUN %d\n", fsg->lun); -+ return -EINVAL; -+ } -+ } -+ -+ /* If a unit attention condition exists, only INQUIRY and -+ * REQUEST SENSE commands are allowed; anything else must fail. */ -+ if (curlun && curlun->unit_attention_data != SS_NO_SENSE && -+ fsg->cmnd[0] != INQUIRY && -+ fsg->cmnd[0] != REQUEST_SENSE) { -+ curlun->sense_data = curlun->unit_attention_data; -+ curlun->unit_attention_data = SS_NO_SENSE; -+ return -EINVAL; -+ } -+ -+ /* Check that only command bytes listed in the mask are non-zero */ -+ fsg->cmnd[1] &= 0x1f; // Mask away the LUN -+ for (i = 1; i < cmnd_size; ++i) { -+ if (fsg->cmnd[i] && !(mask & (1 << i))) { -+ if (curlun) -+ curlun->sense_data = SS_INVALID_FIELD_IN_CDB; -+ return -EINVAL; -+ } -+ } -+ -+ /* If the medium isn't mounted and the command needs to access -+ * it, return an error. */ -+ if (curlun && !fsg_lun_is_open(curlun) && needs_medium) { -+ curlun->sense_data = SS_MEDIUM_NOT_PRESENT; -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+/* wrapper of check_command for data size in blocks handling */ -+static int check_command_size_in_blocks(struct fsg_dev *fsg, int cmnd_size, -+ enum data_direction data_dir, unsigned int mask, -+ int needs_medium, const char *name) -+{ -+ if (fsg->curlun) -+ fsg->data_size_from_cmnd <<= fsg->curlun->blkbits; -+ return check_command(fsg, cmnd_size, data_dir, -+ mask, needs_medium, name); -+} -+ -+static int do_scsi_command(struct fsg_dev *fsg) -+{ -+ struct fsg_buffhd *bh; -+ int rc; -+ int reply = -EINVAL; -+ int i; -+ static char unknown[16]; -+ -+ dump_cdb(fsg); -+ -+ /* Wait for the next buffer to become available for data or status */ -+ bh = fsg->next_buffhd_to_drain = fsg->next_buffhd_to_fill; -+ while (bh->state != BUF_STATE_EMPTY) { -+ rc = sleep_thread(fsg); -+ if (rc) -+ return rc; -+ } -+ fsg->phase_error = 0; -+ fsg->short_packet_received = 0; -+ -+ down_read(&fsg->filesem); // We're using the backing file -+ switch (fsg->cmnd[0]) { -+ -+ case INQUIRY: -+ fsg->data_size_from_cmnd = fsg->cmnd[4]; -+ if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST, -+ (1<<4), 0, -+ "INQUIRY")) == 0) -+ reply = do_inquiry(fsg, bh); -+ break; -+ -+ case MODE_SELECT: -+ fsg->data_size_from_cmnd = fsg->cmnd[4]; -+ if ((reply = check_command(fsg, 6, DATA_DIR_FROM_HOST, -+ (1<<1) | (1<<4), 0, -+ "MODE SELECT(6)")) == 0) -+ reply = do_mode_select(fsg, bh); -+ break; -+ -+ case MODE_SELECT_10: -+ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]); -+ if ((reply = check_command(fsg, 10, DATA_DIR_FROM_HOST, -+ (1<<1) | (3<<7), 0, -+ "MODE SELECT(10)")) == 0) -+ reply = do_mode_select(fsg, bh); -+ break; -+ -+ case MODE_SENSE: -+ fsg->data_size_from_cmnd = fsg->cmnd[4]; -+ if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST, -+ (1<<1) | (1<<2) | (1<<4), 0, -+ "MODE SENSE(6)")) == 0) -+ reply = do_mode_sense(fsg, bh); -+ break; -+ -+ case MODE_SENSE_10: -+ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]); -+ if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST, -+ (1<<1) | (1<<2) | (3<<7), 0, -+ "MODE SENSE(10)")) == 0) -+ reply = do_mode_sense(fsg, bh); -+ break; -+ -+ case ALLOW_MEDIUM_REMOVAL: -+ fsg->data_size_from_cmnd = 0; -+ if ((reply = check_command(fsg, 6, DATA_DIR_NONE, -+ (1<<4), 0, -+ "PREVENT-ALLOW MEDIUM REMOVAL")) == 0) -+ reply = do_prevent_allow(fsg); -+ break; -+ -+ case READ_6: -+ i = fsg->cmnd[4]; -+ fsg->data_size_from_cmnd = (i == 0) ? 256 : i; -+ if ((reply = check_command_size_in_blocks(fsg, 6, -+ DATA_DIR_TO_HOST, -+ (7<<1) | (1<<4), 1, -+ "READ(6)")) == 0) -+ reply = do_read(fsg); -+ break; -+ -+ case READ_10: -+ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]); -+ if ((reply = check_command_size_in_blocks(fsg, 10, -+ DATA_DIR_TO_HOST, -+ (1<<1) | (0xf<<2) | (3<<7), 1, -+ "READ(10)")) == 0) -+ reply = do_read(fsg); -+ break; -+ -+ case READ_12: -+ fsg->data_size_from_cmnd = get_unaligned_be32(&fsg->cmnd[6]); -+ if ((reply = check_command_size_in_blocks(fsg, 12, -+ DATA_DIR_TO_HOST, -+ (1<<1) | (0xf<<2) | (0xf<<6), 1, -+ "READ(12)")) == 0) -+ reply = do_read(fsg); -+ break; -+ -+ case READ_CAPACITY: -+ fsg->data_size_from_cmnd = 8; -+ if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST, -+ (0xf<<2) | (1<<8), 1, -+ "READ CAPACITY")) == 0) -+ reply = do_read_capacity(fsg, bh); -+ break; -+ -+ case READ_HEADER: -+ if (!mod_data.cdrom) -+ goto unknown_cmnd; -+ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]); -+ if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST, -+ (3<<7) | (0x1f<<1), 1, -+ "READ HEADER")) == 0) -+ reply = do_read_header(fsg, bh); -+ break; -+ -+ case READ_TOC: -+ if (!mod_data.cdrom) -+ goto unknown_cmnd; -+ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]); -+ if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST, -+ (7<<6) | (1<<1), 1, -+ "READ TOC")) == 0) -+ reply = do_read_toc(fsg, bh); -+ break; -+ -+ case READ_FORMAT_CAPACITIES: -+ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]); -+ if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST, -+ (3<<7), 1, -+ "READ FORMAT CAPACITIES")) == 0) -+ reply = do_read_format_capacities(fsg, bh); -+ break; -+ -+ case REQUEST_SENSE: -+ fsg->data_size_from_cmnd = fsg->cmnd[4]; -+ if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST, -+ (1<<4), 0, -+ "REQUEST SENSE")) == 0) -+ reply = do_request_sense(fsg, bh); -+ break; -+ -+ case START_STOP: -+ fsg->data_size_from_cmnd = 0; -+ if ((reply = check_command(fsg, 6, DATA_DIR_NONE, -+ (1<<1) | (1<<4), 0, -+ "START-STOP UNIT")) == 0) -+ reply = do_start_stop(fsg); -+ break; -+ -+ case SYNCHRONIZE_CACHE: -+ fsg->data_size_from_cmnd = 0; -+ if ((reply = check_command(fsg, 10, DATA_DIR_NONE, -+ (0xf<<2) | (3<<7), 1, -+ "SYNCHRONIZE CACHE")) == 0) -+ reply = do_synchronize_cache(fsg); -+ break; -+ -+ case TEST_UNIT_READY: -+ fsg->data_size_from_cmnd = 0; -+ reply = check_command(fsg, 6, DATA_DIR_NONE, -+ 0, 1, -+ "TEST UNIT READY"); -+ break; -+ -+ /* Although optional, this command is used by MS-Windows. We -+ * support a minimal version: BytChk must be 0. */ -+ case VERIFY: -+ fsg->data_size_from_cmnd = 0; -+ if ((reply = check_command(fsg, 10, DATA_DIR_NONE, -+ (1<<1) | (0xf<<2) | (3<<7), 1, -+ "VERIFY")) == 0) -+ reply = do_verify(fsg); -+ break; -+ -+ case WRITE_6: -+ i = fsg->cmnd[4]; -+ fsg->data_size_from_cmnd = (i == 0) ? 256 : i; -+ if ((reply = check_command_size_in_blocks(fsg, 6, -+ DATA_DIR_FROM_HOST, -+ (7<<1) | (1<<4), 1, -+ "WRITE(6)")) == 0) -+ reply = do_write(fsg); -+ break; -+ -+ case WRITE_10: -+ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]); -+ if ((reply = check_command_size_in_blocks(fsg, 10, -+ DATA_DIR_FROM_HOST, -+ (1<<1) | (0xf<<2) | (3<<7), 1, -+ "WRITE(10)")) == 0) -+ reply = do_write(fsg); -+ break; -+ -+ case WRITE_12: -+ fsg->data_size_from_cmnd = get_unaligned_be32(&fsg->cmnd[6]); -+ if ((reply = check_command_size_in_blocks(fsg, 12, -+ DATA_DIR_FROM_HOST, -+ (1<<1) | (0xf<<2) | (0xf<<6), 1, -+ "WRITE(12)")) == 0) -+ reply = do_write(fsg); -+ break; -+ -+ /* Some mandatory commands that we recognize but don't implement. -+ * They don't mean much in this setting. It's left as an exercise -+ * for anyone interested to implement RESERVE and RELEASE in terms -+ * of Posix locks. */ -+ case FORMAT_UNIT: -+ case RELEASE: -+ case RESERVE: -+ case SEND_DIAGNOSTIC: -+ // Fall through -+ -+ default: -+ unknown_cmnd: -+ fsg->data_size_from_cmnd = 0; -+ sprintf(unknown, "Unknown x%02x", fsg->cmnd[0]); -+ if ((reply = check_command(fsg, fsg->cmnd_size, -+ DATA_DIR_UNKNOWN, ~0, 0, unknown)) == 0) { -+ fsg->curlun->sense_data = SS_INVALID_COMMAND; -+ reply = -EINVAL; -+ } -+ break; -+ } -+ up_read(&fsg->filesem); -+ -+ if (reply == -EINTR || signal_pending(current)) -+ return -EINTR; -+ -+ /* Set up the single reply buffer for finish_reply() */ -+ if (reply == -EINVAL) -+ reply = 0; // Error reply length -+ if (reply >= 0 && fsg->data_dir == DATA_DIR_TO_HOST) { -+ reply = min((u32) reply, fsg->data_size_from_cmnd); -+ bh->inreq->length = reply; -+ bh->state = BUF_STATE_FULL; -+ fsg->residue -= reply; -+ } // Otherwise it's already set -+ -+ return 0; -+} -+ -+ -+/*-------------------------------------------------------------------------*/ -+ -+static int received_cbw(struct fsg_dev *fsg, struct fsg_buffhd *bh) -+{ -+ struct usb_request *req = bh->outreq; -+ struct bulk_cb_wrap *cbw = req->buf; -+ -+ /* Was this a real packet? Should it be ignored? */ -+ if (req->status || test_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags)) -+ return -EINVAL; -+ -+ /* Is the CBW valid? */ -+ if (req->actual != US_BULK_CB_WRAP_LEN || -+ cbw->Signature != cpu_to_le32( -+ US_BULK_CB_SIGN)) { -+ DBG(fsg, "invalid CBW: len %u sig 0x%x\n", -+ req->actual, -+ le32_to_cpu(cbw->Signature)); -+ -+ /* The Bulk-only spec says we MUST stall the IN endpoint -+ * (6.6.1), so it's unavoidable. It also says we must -+ * retain this state until the next reset, but there's -+ * no way to tell the controller driver it should ignore -+ * Clear-Feature(HALT) requests. -+ * -+ * We aren't required to halt the OUT endpoint; instead -+ * we can simply accept and discard any data received -+ * until the next reset. */ -+ wedge_bulk_in_endpoint(fsg); -+ set_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags); -+ return -EINVAL; -+ } -+ -+ /* Is the CBW meaningful? */ -+ if (cbw->Lun >= FSG_MAX_LUNS || cbw->Flags & ~US_BULK_FLAG_IN || -+ cbw->Length <= 0 || cbw->Length > MAX_COMMAND_SIZE) { -+ DBG(fsg, "non-meaningful CBW: lun = %u, flags = 0x%x, " -+ "cmdlen %u\n", -+ cbw->Lun, cbw->Flags, cbw->Length); -+ -+ /* We can do anything we want here, so let's stall the -+ * bulk pipes if we are allowed to. */ -+ if (mod_data.can_stall) { -+ fsg_set_halt(fsg, fsg->bulk_out); -+ halt_bulk_in_endpoint(fsg); -+ } -+ return -EINVAL; -+ } -+ -+ /* Save the command for later */ -+ fsg->cmnd_size = cbw->Length; -+ memcpy(fsg->cmnd, cbw->CDB, fsg->cmnd_size); -+ if (cbw->Flags & US_BULK_FLAG_IN) -+ fsg->data_dir = DATA_DIR_TO_HOST; -+ else -+ fsg->data_dir = DATA_DIR_FROM_HOST; -+ fsg->data_size = le32_to_cpu(cbw->DataTransferLength); -+ if (fsg->data_size == 0) -+ fsg->data_dir = DATA_DIR_NONE; -+ fsg->lun = cbw->Lun; -+ fsg->tag = cbw->Tag; -+ return 0; -+} -+ -+ -+static int get_next_command(struct fsg_dev *fsg) -+{ -+ struct fsg_buffhd *bh; -+ int rc = 0; -+ -+ if (transport_is_bbb()) { -+ -+ /* Wait for the next buffer to become available */ -+ bh = fsg->next_buffhd_to_fill; -+ while (bh->state != BUF_STATE_EMPTY) { -+ rc = sleep_thread(fsg); -+ if (rc) -+ return rc; -+ } -+ -+ /* Queue a request to read a Bulk-only CBW */ -+ set_bulk_out_req_length(fsg, bh, US_BULK_CB_WRAP_LEN); -+ start_transfer(fsg, fsg->bulk_out, bh->outreq, -+ &bh->outreq_busy, &bh->state); -+ -+ /* We will drain the buffer in software, which means we -+ * can reuse it for the next filling. No need to advance -+ * next_buffhd_to_fill. */ -+ -+ /* Wait for the CBW to arrive */ -+ while (bh->state != BUF_STATE_FULL) { -+ rc = sleep_thread(fsg); -+ if (rc) -+ return rc; -+ } -+ smp_rmb(); -+ rc = received_cbw(fsg, bh); -+ bh->state = BUF_STATE_EMPTY; -+ -+ } else { // USB_PR_CB or USB_PR_CBI -+ -+ /* Wait for the next command to arrive */ -+ while (fsg->cbbuf_cmnd_size == 0) { -+ rc = sleep_thread(fsg); -+ if (rc) -+ return rc; -+ } -+ -+ /* Is the previous status interrupt request still busy? -+ * The host is allowed to skip reading the status, -+ * so we must cancel it. */ -+ if (fsg->intreq_busy) -+ usb_ep_dequeue(fsg->intr_in, fsg->intreq); -+ -+ /* Copy the command and mark the buffer empty */ -+ fsg->data_dir = DATA_DIR_UNKNOWN; -+ spin_lock_irq(&fsg->lock); -+ fsg->cmnd_size = fsg->cbbuf_cmnd_size; -+ memcpy(fsg->cmnd, fsg->cbbuf_cmnd, fsg->cmnd_size); -+ fsg->cbbuf_cmnd_size = 0; -+ spin_unlock_irq(&fsg->lock); -+ -+ /* Use LUN from the command */ -+ fsg->lun = fsg->cmnd[1] >> 5; -+ } -+ -+ /* Update current lun */ -+ if (fsg->lun >= 0 && fsg->lun < fsg->nluns) -+ fsg->curlun = &fsg->luns[fsg->lun]; -+ else -+ fsg->curlun = NULL; -+ -+ return rc; -+} -+ -+ -+/*-------------------------------------------------------------------------*/ -+ -+static int enable_endpoint(struct fsg_dev *fsg, struct usb_ep *ep, -+ const struct usb_endpoint_descriptor *d) -+{ -+ int rc; -+ -+ ep->driver_data = fsg; -+ ep->desc = d; -+ rc = usb_ep_enable(ep); -+ if (rc) -+ ERROR(fsg, "can't enable %s, result %d\n", ep->name, rc); -+ return rc; -+} -+ -+static int alloc_request(struct fsg_dev *fsg, struct usb_ep *ep, -+ struct usb_request **preq) -+{ -+ *preq = usb_ep_alloc_request(ep, GFP_ATOMIC); -+ if (*preq) -+ return 0; -+ ERROR(fsg, "can't allocate request for %s\n", ep->name); -+ return -ENOMEM; -+} -+ -+/* -+ * Reset interface setting and re-init endpoint state (toggle etc). -+ * Call with altsetting < 0 to disable the interface. The only other -+ * available altsetting is 0, which enables the interface. -+ */ -+static int do_set_interface(struct fsg_dev *fsg, int altsetting) -+{ -+ int rc = 0; -+ int i; -+ const struct usb_endpoint_descriptor *d; -+ -+ if (fsg->running) -+ DBG(fsg, "reset interface\n"); -+ -+reset: -+ /* Deallocate the requests */ -+ for (i = 0; i < fsg_num_buffers; ++i) { -+ struct fsg_buffhd *bh = &fsg->buffhds[i]; -+ -+ if (bh->inreq) { -+ usb_ep_free_request(fsg->bulk_in, bh->inreq); -+ bh->inreq = NULL; -+ } -+ if (bh->outreq) { -+ usb_ep_free_request(fsg->bulk_out, bh->outreq); -+ bh->outreq = NULL; -+ } -+ } -+ if (fsg->intreq) { -+ usb_ep_free_request(fsg->intr_in, fsg->intreq); -+ fsg->intreq = NULL; -+ } -+ -+ /* Disable the endpoints */ -+ if (fsg->bulk_in_enabled) { -+ usb_ep_disable(fsg->bulk_in); -+ fsg->bulk_in_enabled = 0; -+ } -+ if (fsg->bulk_out_enabled) { -+ usb_ep_disable(fsg->bulk_out); -+ fsg->bulk_out_enabled = 0; -+ } -+ if (fsg->intr_in_enabled) { -+ usb_ep_disable(fsg->intr_in); -+ fsg->intr_in_enabled = 0; -+ } -+ -+ fsg->running = 0; -+ if (altsetting < 0 || rc != 0) -+ return rc; -+ -+ DBG(fsg, "set interface %d\n", altsetting); -+ -+ /* Enable the endpoints */ -+ d = fsg_ep_desc(fsg->gadget, -+ &fsg_fs_bulk_in_desc, &fsg_hs_bulk_in_desc, -+ &fsg_ss_bulk_in_desc); -+ if ((rc = enable_endpoint(fsg, fsg->bulk_in, d)) != 0) -+ goto reset; -+ fsg->bulk_in_enabled = 1; -+ -+ d = fsg_ep_desc(fsg->gadget, -+ &fsg_fs_bulk_out_desc, &fsg_hs_bulk_out_desc, -+ &fsg_ss_bulk_out_desc); -+ if ((rc = enable_endpoint(fsg, fsg->bulk_out, d)) != 0) -+ goto reset; -+ fsg->bulk_out_enabled = 1; -+ fsg->bulk_out_maxpacket = usb_endpoint_maxp(d); -+ clear_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags); -+ -+ if (transport_is_cbi()) { -+ d = fsg_ep_desc(fsg->gadget, -+ &fsg_fs_intr_in_desc, &fsg_hs_intr_in_desc, -+ &fsg_ss_intr_in_desc); -+ if ((rc = enable_endpoint(fsg, fsg->intr_in, d)) != 0) -+ goto reset; -+ fsg->intr_in_enabled = 1; -+ } -+ -+ /* Allocate the requests */ -+ for (i = 0; i < fsg_num_buffers; ++i) { -+ struct fsg_buffhd *bh = &fsg->buffhds[i]; -+ -+ if ((rc = alloc_request(fsg, fsg->bulk_in, &bh->inreq)) != 0) -+ goto reset; -+ if ((rc = alloc_request(fsg, fsg->bulk_out, &bh->outreq)) != 0) -+ goto reset; -+ bh->inreq->buf = bh->outreq->buf = bh->buf; -+ bh->inreq->context = bh->outreq->context = bh; -+ bh->inreq->complete = bulk_in_complete; -+ bh->outreq->complete = bulk_out_complete; -+ } -+ if (transport_is_cbi()) { -+ if ((rc = alloc_request(fsg, fsg->intr_in, &fsg->intreq)) != 0) -+ goto reset; -+ fsg->intreq->complete = intr_in_complete; -+ } -+ -+ fsg->running = 1; -+ for (i = 0; i < fsg->nluns; ++i) -+ fsg->luns[i].unit_attention_data = SS_RESET_OCCURRED; -+ return rc; -+} -+ -+ -+/* -+ * Change our operational configuration. This code must agree with the code -+ * that returns config descriptors, and with interface altsetting code. -+ * -+ * It's also responsible for power management interactions. Some -+ * configurations might not work with our current power sources. -+ * For now we just assume the gadget is always self-powered. -+ */ -+static int do_set_config(struct fsg_dev *fsg, u8 new_config) -+{ -+ int rc = 0; -+ -+ /* Disable the single interface */ -+ if (fsg->config != 0) { -+ DBG(fsg, "reset config\n"); -+ fsg->config = 0; -+ rc = do_set_interface(fsg, -1); -+ } -+ -+ /* Enable the interface */ -+ if (new_config != 0) { -+ fsg->config = new_config; -+ if ((rc = do_set_interface(fsg, 0)) != 0) -+ fsg->config = 0; // Reset on errors -+ else -+ INFO(fsg, "%s config #%d\n", -+ usb_speed_string(fsg->gadget->speed), -+ fsg->config); -+ } -+ return rc; -+} -+ -+ -+/*-------------------------------------------------------------------------*/ -+ -+static void handle_exception(struct fsg_dev *fsg) -+{ -+ siginfo_t info; -+ int sig; -+ int i; -+ int num_active; -+ struct fsg_buffhd *bh; -+ enum fsg_state old_state; -+ u8 new_config; -+ struct fsg_lun *curlun; -+ unsigned int exception_req_tag; -+ int rc; -+ -+ /* Clear the existing signals. Anything but SIGUSR1 is converted -+ * into a high-priority EXIT exception. */ -+ for (;;) { -+ sig = dequeue_signal_lock(current, ¤t->blocked, &info); -+ if (!sig) -+ break; -+ if (sig != SIGUSR1) { -+ if (fsg->state < FSG_STATE_EXIT) -+ DBG(fsg, "Main thread exiting on signal\n"); -+ raise_exception(fsg, FSG_STATE_EXIT); -+ } -+ } -+ -+ /* Cancel all the pending transfers */ -+ if (fsg->intreq_busy) -+ usb_ep_dequeue(fsg->intr_in, fsg->intreq); -+ for (i = 0; i < fsg_num_buffers; ++i) { -+ bh = &fsg->buffhds[i]; -+ if (bh->inreq_busy) -+ usb_ep_dequeue(fsg->bulk_in, bh->inreq); -+ if (bh->outreq_busy) -+ usb_ep_dequeue(fsg->bulk_out, bh->outreq); -+ } -+ -+ /* Wait until everything is idle */ -+ for (;;) { -+ num_active = fsg->intreq_busy; -+ for (i = 0; i < fsg_num_buffers; ++i) { -+ bh = &fsg->buffhds[i]; -+ num_active += bh->inreq_busy + bh->outreq_busy; -+ } -+ if (num_active == 0) -+ break; -+ if (sleep_thread(fsg)) -+ return; -+ } -+ -+ /* Clear out the controller's fifos */ -+ if (fsg->bulk_in_enabled) -+ usb_ep_fifo_flush(fsg->bulk_in); -+ if (fsg->bulk_out_enabled) -+ usb_ep_fifo_flush(fsg->bulk_out); -+ if (fsg->intr_in_enabled) -+ usb_ep_fifo_flush(fsg->intr_in); -+ -+ /* Reset the I/O buffer states and pointers, the SCSI -+ * state, and the exception. Then invoke the handler. */ -+ spin_lock_irq(&fsg->lock); -+ -+ for (i = 0; i < fsg_num_buffers; ++i) { -+ bh = &fsg->buffhds[i]; -+ bh->state = BUF_STATE_EMPTY; -+ } -+ fsg->next_buffhd_to_fill = fsg->next_buffhd_to_drain = -+ &fsg->buffhds[0]; -+ -+ exception_req_tag = fsg->exception_req_tag; -+ new_config = fsg->new_config; -+ old_state = fsg->state; -+ -+ if (old_state == FSG_STATE_ABORT_BULK_OUT) -+ fsg->state = FSG_STATE_STATUS_PHASE; -+ else { -+ for (i = 0; i < fsg->nluns; ++i) { -+ curlun = &fsg->luns[i]; -+ curlun->prevent_medium_removal = 0; -+ curlun->sense_data = curlun->unit_attention_data = -+ SS_NO_SENSE; -+ curlun->sense_data_info = 0; -+ curlun->info_valid = 0; -+ } -+ fsg->state = FSG_STATE_IDLE; -+ } -+ spin_unlock_irq(&fsg->lock); -+ -+ /* Carry out any extra actions required for the exception */ -+ switch (old_state) { -+ default: -+ break; -+ -+ case FSG_STATE_ABORT_BULK_OUT: -+ send_status(fsg); -+ spin_lock_irq(&fsg->lock); -+ if (fsg->state == FSG_STATE_STATUS_PHASE) -+ fsg->state = FSG_STATE_IDLE; -+ spin_unlock_irq(&fsg->lock); -+ break; -+ -+ case FSG_STATE_RESET: -+ /* In case we were forced against our will to halt a -+ * bulk endpoint, clear the halt now. (The SuperH UDC -+ * requires this.) */ -+ if (test_and_clear_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags)) -+ usb_ep_clear_halt(fsg->bulk_in); -+ -+ if (transport_is_bbb()) { -+ if (fsg->ep0_req_tag == exception_req_tag) -+ ep0_queue(fsg); // Complete the status stage -+ -+ } else if (transport_is_cbi()) -+ send_status(fsg); // Status by interrupt pipe -+ -+ /* Technically this should go here, but it would only be -+ * a waste of time. Ditto for the INTERFACE_CHANGE and -+ * CONFIG_CHANGE cases. */ -+ // for (i = 0; i < fsg->nluns; ++i) -+ // fsg->luns[i].unit_attention_data = SS_RESET_OCCURRED; -+ break; -+ -+ case FSG_STATE_INTERFACE_CHANGE: -+ rc = do_set_interface(fsg, 0); -+ if (fsg->ep0_req_tag != exception_req_tag) -+ break; -+ if (rc != 0) // STALL on errors -+ fsg_set_halt(fsg, fsg->ep0); -+ else // Complete the status stage -+ ep0_queue(fsg); -+ break; -+ -+ case FSG_STATE_CONFIG_CHANGE: -+ rc = do_set_config(fsg, new_config); -+ if (fsg->ep0_req_tag != exception_req_tag) -+ break; -+ if (rc != 0) // STALL on errors -+ fsg_set_halt(fsg, fsg->ep0); -+ else // Complete the status stage -+ ep0_queue(fsg); -+ break; -+ -+ case FSG_STATE_DISCONNECT: -+ for (i = 0; i < fsg->nluns; ++i) -+ fsg_lun_fsync_sub(fsg->luns + i); -+ do_set_config(fsg, 0); // Unconfigured state -+ break; -+ -+ case FSG_STATE_EXIT: -+ case FSG_STATE_TERMINATED: -+ do_set_config(fsg, 0); // Free resources -+ spin_lock_irq(&fsg->lock); -+ fsg->state = FSG_STATE_TERMINATED; // Stop the thread -+ spin_unlock_irq(&fsg->lock); -+ break; -+ } -+} -+ -+ -+/*-------------------------------------------------------------------------*/ -+ -+static int fsg_main_thread(void *fsg_) -+{ -+ struct fsg_dev *fsg = fsg_; -+ -+ /* Allow the thread to be killed by a signal, but set the signal mask -+ * to block everything but INT, TERM, KILL, and USR1. */ -+ allow_signal(SIGINT); -+ allow_signal(SIGTERM); -+ allow_signal(SIGKILL); -+ allow_signal(SIGUSR1); -+ -+ /* Allow the thread to be frozen */ -+ set_freezable(); -+ -+ /* Arrange for userspace references to be interpreted as kernel -+ * pointers. That way we can pass a kernel pointer to a routine -+ * that expects a __user pointer and it will work okay. */ -+ set_fs(get_ds()); -+ -+ /* The main loop */ -+ while (fsg->state != FSG_STATE_TERMINATED) { -+ if (exception_in_progress(fsg) || signal_pending(current)) { -+ handle_exception(fsg); -+ continue; -+ } -+ -+ if (!fsg->running) { -+ sleep_thread(fsg); -+ continue; -+ } -+ -+ if (get_next_command(fsg)) -+ continue; -+ -+ spin_lock_irq(&fsg->lock); -+ if (!exception_in_progress(fsg)) -+ fsg->state = FSG_STATE_DATA_PHASE; -+ spin_unlock_irq(&fsg->lock); -+ -+ if (do_scsi_command(fsg) || finish_reply(fsg)) -+ continue; -+ -+ spin_lock_irq(&fsg->lock); -+ if (!exception_in_progress(fsg)) -+ fsg->state = FSG_STATE_STATUS_PHASE; -+ spin_unlock_irq(&fsg->lock); -+ -+ if (send_status(fsg)) -+ continue; -+ -+ spin_lock_irq(&fsg->lock); -+ if (!exception_in_progress(fsg)) -+ fsg->state = FSG_STATE_IDLE; -+ spin_unlock_irq(&fsg->lock); -+ } -+ -+ spin_lock_irq(&fsg->lock); -+ fsg->thread_task = NULL; -+ spin_unlock_irq(&fsg->lock); -+ -+ /* If we are exiting because of a signal, unregister the -+ * gadget driver. */ -+ if (test_and_clear_bit(REGISTERED, &fsg->atomic_bitflags)) -+ usb_gadget_unregister_driver(&fsg_driver); -+ -+ /* Let the unbind and cleanup routines know the thread has exited */ -+ complete_and_exit(&fsg->thread_notifier, 0); -+} -+ -+ -+/*-------------------------------------------------------------------------*/ -+ -+ -+/* The write permissions and store_xxx pointers are set in fsg_bind() */ -+static DEVICE_ATTR(ro, 0444, fsg_show_ro, NULL); -+static DEVICE_ATTR(nofua, 0644, fsg_show_nofua, NULL); -+static DEVICE_ATTR(file, 0444, fsg_show_file, NULL); -+ -+ -+/*-------------------------------------------------------------------------*/ -+ -+static void fsg_release(struct kref *ref) -+{ -+ struct fsg_dev *fsg = container_of(ref, struct fsg_dev, ref); -+ -+ kfree(fsg->luns); -+ kfree(fsg); -+} -+ -+static void lun_release(struct device *dev) -+{ -+ struct rw_semaphore *filesem = dev_get_drvdata(dev); -+ struct fsg_dev *fsg = -+ container_of(filesem, struct fsg_dev, filesem); -+ -+ kref_put(&fsg->ref, fsg_release); -+} -+ -+static void /* __init_or_exit */ fsg_unbind(struct usb_gadget *gadget) -+{ -+ struct fsg_dev *fsg = get_gadget_data(gadget); -+ int i; -+ struct fsg_lun *curlun; -+ struct usb_request *req = fsg->ep0req; -+ -+ DBG(fsg, "unbind\n"); -+ clear_bit(REGISTERED, &fsg->atomic_bitflags); -+ -+ /* If the thread isn't already dead, tell it to exit now */ -+ if (fsg->state != FSG_STATE_TERMINATED) { -+ raise_exception(fsg, FSG_STATE_EXIT); -+ wait_for_completion(&fsg->thread_notifier); -+ -+ /* The cleanup routine waits for this completion also */ -+ complete(&fsg->thread_notifier); -+ } -+ -+ /* Unregister the sysfs attribute files and the LUNs */ -+ for (i = 0; i < fsg->nluns; ++i) { -+ curlun = &fsg->luns[i]; -+ if (curlun->registered) { -+ device_remove_file(&curlun->dev, &dev_attr_nofua); -+ device_remove_file(&curlun->dev, &dev_attr_ro); -+ device_remove_file(&curlun->dev, &dev_attr_file); -+ fsg_lun_close(curlun); -+ device_unregister(&curlun->dev); -+ curlun->registered = 0; -+ } -+ } -+ -+ /* Free the data buffers */ -+ for (i = 0; i < fsg_num_buffers; ++i) -+ kfree(fsg->buffhds[i].buf); -+ -+ /* Free the request and buffer for endpoint 0 */ -+ if (req) { -+ kfree(req->buf); -+ usb_ep_free_request(fsg->ep0, req); -+ } -+ -+ set_gadget_data(gadget, NULL); -+} -+ -+ -+static int __init check_parameters(struct fsg_dev *fsg) -+{ -+ int prot; -+ int gcnum; -+ -+ /* Store the default values */ -+ mod_data.transport_type = USB_PR_BULK; -+ mod_data.transport_name = "Bulk-only"; -+ mod_data.protocol_type = USB_SC_SCSI; -+ mod_data.protocol_name = "Transparent SCSI"; -+ -+ /* Some peripheral controllers are known not to be able to -+ * halt bulk endpoints correctly. If one of them is present, -+ * disable stalls. -+ */ -+ if (gadget_is_at91(fsg->gadget)) -+ mod_data.can_stall = 0; -+ -+ if (mod_data.release == 0xffff) { // Parameter wasn't set -+ gcnum = usb_gadget_controller_number(fsg->gadget); -+ if (gcnum >= 0) -+ mod_data.release = 0x0300 + gcnum; -+ else { -+ WARNING(fsg, "controller '%s' not recognized\n", -+ fsg->gadget->name); -+ mod_data.release = 0x0399; -+ } -+ } -+ -+ prot = simple_strtol(mod_data.protocol_parm, NULL, 0); -+ -+#ifdef CONFIG_USB_FILE_STORAGE_TEST -+ if (strnicmp(mod_data.transport_parm, "BBB", 10) == 0) { -+ ; // Use default setting -+ } else if (strnicmp(mod_data.transport_parm, "CB", 10) == 0) { -+ mod_data.transport_type = USB_PR_CB; -+ mod_data.transport_name = "Control-Bulk"; -+ } else if (strnicmp(mod_data.transport_parm, "CBI", 10) == 0) { -+ mod_data.transport_type = USB_PR_CBI; -+ mod_data.transport_name = "Control-Bulk-Interrupt"; -+ } else { -+ ERROR(fsg, "invalid transport: %s\n", mod_data.transport_parm); -+ return -EINVAL; -+ } -+ -+ if (strnicmp(mod_data.protocol_parm, "SCSI", 10) == 0 || -+ prot == USB_SC_SCSI) { -+ ; // Use default setting -+ } else if (strnicmp(mod_data.protocol_parm, "RBC", 10) == 0 || -+ prot == USB_SC_RBC) { -+ mod_data.protocol_type = USB_SC_RBC; -+ mod_data.protocol_name = "RBC"; -+ } else if (strnicmp(mod_data.protocol_parm, "8020", 4) == 0 || -+ strnicmp(mod_data.protocol_parm, "ATAPI", 10) == 0 || -+ prot == USB_SC_8020) { -+ mod_data.protocol_type = USB_SC_8020; -+ mod_data.protocol_name = "8020i (ATAPI)"; -+ } else if (strnicmp(mod_data.protocol_parm, "QIC", 3) == 0 || -+ prot == USB_SC_QIC) { -+ mod_data.protocol_type = USB_SC_QIC; -+ mod_data.protocol_name = "QIC-157"; -+ } else if (strnicmp(mod_data.protocol_parm, "UFI", 10) == 0 || -+ prot == USB_SC_UFI) { -+ mod_data.protocol_type = USB_SC_UFI; -+ mod_data.protocol_name = "UFI"; -+ } else if (strnicmp(mod_data.protocol_parm, "8070", 4) == 0 || -+ prot == USB_SC_8070) { -+ mod_data.protocol_type = USB_SC_8070; -+ mod_data.protocol_name = "8070i"; -+ } else { -+ ERROR(fsg, "invalid protocol: %s\n", mod_data.protocol_parm); -+ return -EINVAL; -+ } -+ -+ mod_data.buflen &= PAGE_CACHE_MASK; -+ if (mod_data.buflen <= 0) { -+ ERROR(fsg, "invalid buflen\n"); -+ return -ETOOSMALL; -+ } -+ -+#endif /* CONFIG_USB_FILE_STORAGE_TEST */ -+ -+ /* Serial string handling. -+ * On a real device, the serial string would be loaded -+ * from permanent storage. */ -+ if (mod_data.serial) { -+ const char *ch; -+ unsigned len = 0; -+ -+ /* Sanity check : -+ * The CB[I] specification limits the serial string to -+ * 12 uppercase hexadecimal characters. -+ * BBB need at least 12 uppercase hexadecimal characters, -+ * with a maximum of 126. */ -+ for (ch = mod_data.serial; *ch; ++ch) { -+ ++len; -+ if ((*ch < '0' || *ch > '9') && -+ (*ch < 'A' || *ch > 'F')) { /* not uppercase hex */ -+ WARNING(fsg, -+ "Invalid serial string character: %c\n", -+ *ch); -+ goto no_serial; -+ } -+ } -+ if (len > 126 || -+ (mod_data.transport_type == USB_PR_BULK && len < 12) || -+ (mod_data.transport_type != USB_PR_BULK && len > 12)) { -+ WARNING(fsg, "Invalid serial string length!\n"); -+ goto no_serial; -+ } -+ fsg_strings[FSG_STRING_SERIAL - 1].s = mod_data.serial; -+ } else { -+ WARNING(fsg, "No serial-number string provided!\n"); -+ no_serial: -+ device_desc.iSerialNumber = 0; -+ } -+ -+ return 0; -+} -+ -+ -+static int __init fsg_bind(struct usb_gadget *gadget) -+{ -+ struct fsg_dev *fsg = the_fsg; -+ int rc; -+ int i; -+ struct fsg_lun *curlun; -+ struct usb_ep *ep; -+ struct usb_request *req; -+ char *pathbuf, *p; -+ -+ fsg->gadget = gadget; -+ set_gadget_data(gadget, fsg); -+ fsg->ep0 = gadget->ep0; -+ fsg->ep0->driver_data = fsg; -+ -+ if ((rc = check_parameters(fsg)) != 0) -+ goto out; -+ -+ if (mod_data.removable) { // Enable the store_xxx attributes -+ dev_attr_file.attr.mode = 0644; -+ dev_attr_file.store = fsg_store_file; -+ if (!mod_data.cdrom) { -+ dev_attr_ro.attr.mode = 0644; -+ dev_attr_ro.store = fsg_store_ro; -+ } -+ } -+ -+ /* Only for removable media? */ -+ dev_attr_nofua.attr.mode = 0644; -+ dev_attr_nofua.store = fsg_store_nofua; -+ -+ /* Find out how many LUNs there should be */ -+ i = mod_data.nluns; -+ if (i == 0) -+ i = max(mod_data.num_filenames, 1u); -+ if (i > FSG_MAX_LUNS) { -+ ERROR(fsg, "invalid number of LUNs: %d\n", i); -+ rc = -EINVAL; -+ goto out; -+ } -+ -+ /* Create the LUNs, open their backing files, and register the -+ * LUN devices in sysfs. */ -+ fsg->luns = kzalloc(i * sizeof(struct fsg_lun), GFP_KERNEL); -+ if (!fsg->luns) { -+ rc = -ENOMEM; -+ goto out; -+ } -+ fsg->nluns = i; -+ -+ for (i = 0; i < fsg->nluns; ++i) { -+ curlun = &fsg->luns[i]; -+ curlun->cdrom = !!mod_data.cdrom; -+ curlun->ro = mod_data.cdrom || mod_data.ro[i]; -+ curlun->initially_ro = curlun->ro; -+ curlun->removable = mod_data.removable; -+ curlun->nofua = mod_data.nofua[i]; -+ curlun->dev.release = lun_release; -+ curlun->dev.parent = &gadget->dev; -+ curlun->dev.driver = &fsg_driver.driver; -+ dev_set_drvdata(&curlun->dev, &fsg->filesem); -+ dev_set_name(&curlun->dev,"%s-lun%d", -+ dev_name(&gadget->dev), i); -+ -+ kref_get(&fsg->ref); -+ rc = device_register(&curlun->dev); -+ if (rc) { -+ INFO(fsg, "failed to register LUN%d: %d\n", i, rc); -+ put_device(&curlun->dev); -+ goto out; -+ } -+ curlun->registered = 1; -+ -+ rc = device_create_file(&curlun->dev, &dev_attr_ro); -+ if (rc) -+ goto out; -+ rc = device_create_file(&curlun->dev, &dev_attr_nofua); -+ if (rc) -+ goto out; -+ rc = device_create_file(&curlun->dev, &dev_attr_file); -+ if (rc) -+ goto out; -+ -+ if (mod_data.file[i] && *mod_data.file[i]) { -+ rc = fsg_lun_open(curlun, mod_data.file[i]); -+ if (rc) -+ goto out; -+ } else if (!mod_data.removable) { -+ ERROR(fsg, "no file given for LUN%d\n", i); -+ rc = -EINVAL; -+ goto out; -+ } -+ } -+ -+ /* Find all the endpoints we will use */ -+ usb_ep_autoconfig_reset(gadget); -+ ep = usb_ep_autoconfig(gadget, &fsg_fs_bulk_in_desc); -+ if (!ep) -+ goto autoconf_fail; -+ ep->driver_data = fsg; // claim the endpoint -+ fsg->bulk_in = ep; -+ -+ ep = usb_ep_autoconfig(gadget, &fsg_fs_bulk_out_desc); -+ if (!ep) -+ goto autoconf_fail; -+ ep->driver_data = fsg; // claim the endpoint -+ fsg->bulk_out = ep; -+ -+ if (transport_is_cbi()) { -+ ep = usb_ep_autoconfig(gadget, &fsg_fs_intr_in_desc); -+ if (!ep) -+ goto autoconf_fail; -+ ep->driver_data = fsg; // claim the endpoint -+ fsg->intr_in = ep; -+ } -+ -+ /* Fix up the descriptors */ -+ device_desc.idVendor = cpu_to_le16(mod_data.vendor); -+ device_desc.idProduct = cpu_to_le16(mod_data.product); -+ device_desc.bcdDevice = cpu_to_le16(mod_data.release); -+ -+ i = (transport_is_cbi() ? 3 : 2); // Number of endpoints -+ fsg_intf_desc.bNumEndpoints = i; -+ fsg_intf_desc.bInterfaceSubClass = mod_data.protocol_type; -+ fsg_intf_desc.bInterfaceProtocol = mod_data.transport_type; -+ fsg_fs_function[i + FSG_FS_FUNCTION_PRE_EP_ENTRIES] = NULL; -+ -+ if (gadget_is_dualspeed(gadget)) { -+ fsg_hs_function[i + FSG_HS_FUNCTION_PRE_EP_ENTRIES] = NULL; -+ -+ /* Assume endpoint addresses are the same for both speeds */ -+ fsg_hs_bulk_in_desc.bEndpointAddress = -+ fsg_fs_bulk_in_desc.bEndpointAddress; -+ fsg_hs_bulk_out_desc.bEndpointAddress = -+ fsg_fs_bulk_out_desc.bEndpointAddress; -+ fsg_hs_intr_in_desc.bEndpointAddress = -+ fsg_fs_intr_in_desc.bEndpointAddress; -+ } -+ -+ if (gadget_is_superspeed(gadget)) { -+ unsigned max_burst; -+ -+ fsg_ss_function[i + FSG_SS_FUNCTION_PRE_EP_ENTRIES] = NULL; -+ -+ /* Calculate bMaxBurst, we know packet size is 1024 */ -+ max_burst = min_t(unsigned, mod_data.buflen / 1024, 15); -+ -+ /* Assume endpoint addresses are the same for both speeds */ -+ fsg_ss_bulk_in_desc.bEndpointAddress = -+ fsg_fs_bulk_in_desc.bEndpointAddress; -+ fsg_ss_bulk_in_comp_desc.bMaxBurst = max_burst; -+ -+ fsg_ss_bulk_out_desc.bEndpointAddress = -+ fsg_fs_bulk_out_desc.bEndpointAddress; -+ fsg_ss_bulk_out_comp_desc.bMaxBurst = max_burst; -+ } -+ -+ if (gadget_is_otg(gadget)) -+ fsg_otg_desc.bmAttributes |= USB_OTG_HNP; -+ -+ rc = -ENOMEM; -+ -+ /* Allocate the request and buffer for endpoint 0 */ -+ fsg->ep0req = req = usb_ep_alloc_request(fsg->ep0, GFP_KERNEL); -+ if (!req) -+ goto out; -+ req->buf = kmalloc(EP0_BUFSIZE, GFP_KERNEL); -+ if (!req->buf) -+ goto out; -+ req->complete = ep0_complete; -+ -+ /* Allocate the data buffers */ -+ for (i = 0; i < fsg_num_buffers; ++i) { -+ struct fsg_buffhd *bh = &fsg->buffhds[i]; -+ -+ /* Allocate for the bulk-in endpoint. We assume that -+ * the buffer will also work with the bulk-out (and -+ * interrupt-in) endpoint. */ -+ bh->buf = kmalloc(mod_data.buflen, GFP_KERNEL); -+ if (!bh->buf) -+ goto out; -+ bh->next = bh + 1; -+ } -+ fsg->buffhds[fsg_num_buffers - 1].next = &fsg->buffhds[0]; -+ -+ /* This should reflect the actual gadget power source */ -+ usb_gadget_set_selfpowered(gadget); -+ -+ snprintf(fsg_string_manufacturer, sizeof fsg_string_manufacturer, -+ "%s %s with %s", -+ init_utsname()->sysname, init_utsname()->release, -+ gadget->name); -+ -+ fsg->thread_task = kthread_create(fsg_main_thread, fsg, -+ "file-storage-gadget"); -+ if (IS_ERR(fsg->thread_task)) { -+ rc = PTR_ERR(fsg->thread_task); -+ goto out; -+ } -+ -+ INFO(fsg, DRIVER_DESC ", version: " DRIVER_VERSION "\n"); -+ INFO(fsg, "NOTE: This driver is deprecated. " -+ "Consider using g_mass_storage instead.\n"); -+ INFO(fsg, "Number of LUNs=%d\n", fsg->nluns); -+ -+ pathbuf = kmalloc(PATH_MAX, GFP_KERNEL); -+ for (i = 0; i < fsg->nluns; ++i) { -+ curlun = &fsg->luns[i]; -+ if (fsg_lun_is_open(curlun)) { -+ p = NULL; -+ if (pathbuf) { -+ p = d_path(&curlun->filp->f_path, -+ pathbuf, PATH_MAX); -+ if (IS_ERR(p)) -+ p = NULL; -+ } -+ LINFO(curlun, "ro=%d, nofua=%d, file: %s\n", -+ curlun->ro, curlun->nofua, (p ? p : "(error)")); -+ } -+ } -+ kfree(pathbuf); -+ -+ DBG(fsg, "transport=%s (x%02x)\n", -+ mod_data.transport_name, mod_data.transport_type); -+ DBG(fsg, "protocol=%s (x%02x)\n", -+ mod_data.protocol_name, mod_data.protocol_type); -+ DBG(fsg, "VendorID=x%04x, ProductID=x%04x, Release=x%04x\n", -+ mod_data.vendor, mod_data.product, mod_data.release); -+ DBG(fsg, "removable=%d, stall=%d, cdrom=%d, buflen=%u\n", -+ mod_data.removable, mod_data.can_stall, -+ mod_data.cdrom, mod_data.buflen); -+ DBG(fsg, "I/O thread pid: %d\n", task_pid_nr(fsg->thread_task)); -+ -+ set_bit(REGISTERED, &fsg->atomic_bitflags); -+ -+ /* Tell the thread to start working */ -+ wake_up_process(fsg->thread_task); -+ return 0; -+ -+autoconf_fail: -+ ERROR(fsg, "unable to autoconfigure all endpoints\n"); -+ rc = -ENOTSUPP; -+ -+out: -+ fsg->state = FSG_STATE_TERMINATED; // The thread is dead -+ fsg_unbind(gadget); -+ complete(&fsg->thread_notifier); -+ return rc; -+} -+ -+ -+/*-------------------------------------------------------------------------*/ -+ -+static void fsg_suspend(struct usb_gadget *gadget) -+{ -+ struct fsg_dev *fsg = get_gadget_data(gadget); -+ -+ DBG(fsg, "suspend\n"); -+ set_bit(SUSPENDED, &fsg->atomic_bitflags); -+} -+ -+static void fsg_resume(struct usb_gadget *gadget) -+{ -+ struct fsg_dev *fsg = get_gadget_data(gadget); -+ -+ DBG(fsg, "resume\n"); -+ clear_bit(SUSPENDED, &fsg->atomic_bitflags); -+} -+ -+ -+/*-------------------------------------------------------------------------*/ -+ -+static struct usb_gadget_driver fsg_driver = { -+ .max_speed = USB_SPEED_SUPER, -+ .function = (char *) fsg_string_product, -+ .unbind = fsg_unbind, -+ .disconnect = fsg_disconnect, -+ .setup = fsg_setup, -+ .suspend = fsg_suspend, -+ .resume = fsg_resume, -+ -+ .driver = { -+ .name = DRIVER_NAME, -+ .owner = THIS_MODULE, -+ // .release = ... -+ // .suspend = ... -+ // .resume = ... -+ }, -+}; -+ -+ -+static int __init fsg_alloc(void) -+{ -+ struct fsg_dev *fsg; -+ -+ fsg = kzalloc(sizeof *fsg + -+ fsg_num_buffers * sizeof *(fsg->buffhds), GFP_KERNEL); -+ -+ if (!fsg) -+ return -ENOMEM; -+ spin_lock_init(&fsg->lock); -+ init_rwsem(&fsg->filesem); -+ kref_init(&fsg->ref); -+ init_completion(&fsg->thread_notifier); -+ -+ the_fsg = fsg; -+ return 0; -+} -+ -+ -+static int __init fsg_init(void) -+{ -+ int rc; -+ struct fsg_dev *fsg; -+ -+ rc = fsg_num_buffers_validate(); -+ if (rc != 0) -+ return rc; -+ -+ if ((rc = fsg_alloc()) != 0) -+ return rc; -+ fsg = the_fsg; -+ if ((rc = usb_gadget_probe_driver(&fsg_driver, fsg_bind)) != 0) -+ kref_put(&fsg->ref, fsg_release); -+ return rc; -+} -+module_init(fsg_init); -+ -+ -+static void __exit fsg_cleanup(void) -+{ -+ struct fsg_dev *fsg = the_fsg; -+ -+ /* Unregister the driver iff the thread hasn't already done so */ -+ if (test_and_clear_bit(REGISTERED, &fsg->atomic_bitflags)) -+ usb_gadget_unregister_driver(&fsg_driver); -+ -+ /* Wait for the thread to finish up */ -+ wait_for_completion(&fsg->thread_notifier); -+ -+ kref_put(&fsg->ref, fsg_release); -+} -+module_exit(fsg_cleanup); -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/changes.txt linux-rpi/drivers/usb/host/dwc_common_port/changes.txt ---- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/changes.txt 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_common_port/changes.txt 2015-11-29 09:42:39.915098960 +0100 -@@ -0,0 +1,174 @@ -+ -+dwc_read_reg32() and friends now take an additional parameter, a pointer to an -+IO context struct. The IO context struct should live in an os-dependent struct -+in your driver. As an example, the dwc_usb3 driver has an os-dependent struct -+named 'os_dep' embedded in the main device struct. So there these calls look -+like this: -+ -+ dwc_read_reg32(&usb3_dev->os_dep.ioctx, &pcd->dev_global_regs->dcfg); -+ -+ dwc_write_reg32(&usb3_dev->os_dep.ioctx, -+ &pcd->dev_global_regs->dcfg, 0); -+ -+Note that for the existing Linux driver ports, it is not necessary to actually -+define the 'ioctx' member in the os-dependent struct. Since Linux does not -+require an IO context, its macros for dwc_read_reg32() and friends do not -+use the context pointer, so it is optimized away by the compiler. But it is -+necessary to add the pointer parameter to all of the call sites, to be ready -+for any future ports (such as FreeBSD) which do require an IO context. -+ -+ -+Similarly, dwc_alloc(), dwc_alloc_atomic(), dwc_strdup(), and dwc_free() now -+take an additional parameter, a pointer to a memory context. Examples: -+ -+ addr = dwc_alloc(&usb3_dev->os_dep.memctx, size); -+ -+ dwc_free(&usb3_dev->os_dep.memctx, addr); -+ -+Again, for the Linux ports, it is not necessary to actually define the memctx -+member, but it is necessary to add the pointer parameter to all of the call -+sites. -+ -+ -+Same for dwc_dma_alloc() and dwc_dma_free(). Examples: -+ -+ virt_addr = dwc_dma_alloc(&usb3_dev->os_dep.dmactx, size, &phys_addr); -+ -+ dwc_dma_free(&usb3_dev->os_dep.dmactx, size, virt_addr, phys_addr); -+ -+ -+Same for dwc_mutex_alloc() and dwc_mutex_free(). Examples: -+ -+ mutex = dwc_mutex_alloc(&usb3_dev->os_dep.mtxctx); -+ -+ dwc_mutex_free(&usb3_dev->os_dep.mtxctx, mutex); -+ -+ -+Same for dwc_spinlock_alloc() and dwc_spinlock_free(). Examples: -+ -+ lock = dwc_spinlock_alloc(&usb3_dev->osdep.splctx); -+ -+ dwc_spinlock_free(&usb3_dev->osdep.splctx, lock); -+ -+ -+Same for dwc_timer_alloc(). Example: -+ -+ timer = dwc_timer_alloc(&usb3_dev->os_dep.tmrctx, "dwc_usb3_tmr1", -+ cb_func, cb_data); -+ -+ -+Same for dwc_waitq_alloc(). Example: -+ -+ waitq = dwc_waitq_alloc(&usb3_dev->os_dep.wtqctx); -+ -+ -+Same for dwc_thread_run(). Example: -+ -+ thread = dwc_thread_run(&usb3_dev->os_dep.thdctx, func, -+ "dwc_usb3_thd1", data); -+ -+ -+Same for dwc_workq_alloc(). Example: -+ -+ workq = dwc_workq_alloc(&usb3_dev->osdep.wkqctx, "dwc_usb3_wkq1"); -+ -+ -+Same for dwc_task_alloc(). Example: -+ -+ task = dwc_task_alloc(&usb3_dev->os_dep.tskctx, "dwc_usb3_tsk1", -+ cb_func, cb_data); -+ -+ -+In addition to the context pointer additions, a few core functions have had -+other changes made to their parameters: -+ -+The 'flags' parameter to dwc_spinlock_irqsave() and dwc_spinunlock_irqrestore() -+has been changed from a uint64_t to a dwc_irqflags_t. -+ -+dwc_thread_should_stop() now takes a 'dwc_thread_t *' parameter, because the -+FreeBSD equivalent of that function requires it. -+ -+And, in addition to the context pointer, dwc_task_alloc() also adds a -+'char *name' parameter, to be consistent with dwc_thread_run() and -+dwc_workq_alloc(), and because the FreeBSD equivalent of that function -+requires a unique name. -+ -+ -+Here is a complete list of the core functions that now take a pointer to a -+context as their first parameter: -+ -+ dwc_read_reg32 -+ dwc_read_reg64 -+ dwc_write_reg32 -+ dwc_write_reg64 -+ dwc_modify_reg32 -+ dwc_modify_reg64 -+ dwc_alloc -+ dwc_alloc_atomic -+ dwc_strdup -+ dwc_free -+ dwc_dma_alloc -+ dwc_dma_free -+ dwc_mutex_alloc -+ dwc_mutex_free -+ dwc_spinlock_alloc -+ dwc_spinlock_free -+ dwc_timer_alloc -+ dwc_waitq_alloc -+ dwc_thread_run -+ dwc_workq_alloc -+ dwc_task_alloc Also adds a 'char *name' as its 2nd parameter -+ -+And here are the core functions that have other changes to their parameters: -+ -+ dwc_spinlock_irqsave 'flags' param is now a 'dwc_irqflags_t *' -+ dwc_spinunlock_irqrestore 'flags' param is now a 'dwc_irqflags_t' -+ dwc_thread_should_stop Adds a 'dwc_thread_t *' parameter -+ -+ -+ -+The changes to the core functions also require some of the other library -+functions to change: -+ -+ dwc_cc_if_alloc() and dwc_cc_if_free() now take a 'void *memctx' -+ (for memory allocation) as the 1st param and a 'void *mtxctx' -+ (for mutex allocation) as the 2nd param. -+ -+ dwc_cc_clear(), dwc_cc_add(), dwc_cc_change(), dwc_cc_remove(), -+ dwc_cc_data_for_save(), and dwc_cc_restore_from_data() now take a -+ 'void *memctx' as the 1st param. -+ -+ dwc_dh_modpow(), dwc_dh_pk(), and dwc_dh_derive_keys() now take a -+ 'void *memctx' as the 1st param. -+ -+ dwc_modpow() now takes a 'void *memctx' as the 1st param. -+ -+ dwc_alloc_notification_manager() now takes a 'void *memctx' as the -+ 1st param and a 'void *wkqctx' (for work queue allocation) as the 2nd -+ param, and also now returns an integer value that is non-zero if -+ allocation of its data structures or work queue fails. -+ -+ dwc_register_notifier() now takes a 'void *memctx' as the 1st param. -+ -+ dwc_memory_debug_start() now takes a 'void *mem_ctx' as the first -+ param, and also now returns an integer value that is non-zero if -+ allocation of its data structures fails. -+ -+ -+ -+Other miscellaneous changes: -+ -+The DEBUG_MEMORY and DEBUG_REGS #define's have been renamed to -+DWC_DEBUG_MEMORY and DWC_DEBUG_REGS. -+ -+The following #define's have been added to allow selectively compiling library -+features: -+ -+ DWC_CCLIB -+ DWC_CRYPTOLIB -+ DWC_NOTIFYLIB -+ DWC_UTFLIB -+ -+A DWC_LIBMODULE #define has also been added. If this is not defined, then the -+module code in dwc_common_linux.c is not compiled in. This allows linking the -+library code directly into a driver module, instead of as a standalone module. -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/doc/doxygen.cfg linux-rpi/drivers/usb/host/dwc_common_port/doc/doxygen.cfg ---- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/doc/doxygen.cfg 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_common_port/doc/doxygen.cfg 2015-11-29 09:42:39.915098960 +0100 -@@ -0,0 +1,270 @@ -+# Doxyfile 1.4.5 -+ -+#--------------------------------------------------------------------------- -+# Project related configuration options -+#--------------------------------------------------------------------------- -+PROJECT_NAME = "Synopsys DWC Portability and Common Library for UWB" -+PROJECT_NUMBER = -+OUTPUT_DIRECTORY = doc -+CREATE_SUBDIRS = NO -+OUTPUT_LANGUAGE = English -+BRIEF_MEMBER_DESC = YES -+REPEAT_BRIEF = YES -+ABBREVIATE_BRIEF = "The $name class" \ -+ "The $name widget" \ -+ "The $name file" \ -+ is \ -+ provides \ -+ specifies \ -+ contains \ -+ represents \ -+ a \ -+ an \ -+ the -+ALWAYS_DETAILED_SEC = YES -+INLINE_INHERITED_MEMB = NO -+FULL_PATH_NAMES = NO -+STRIP_FROM_PATH = .. -+STRIP_FROM_INC_PATH = -+SHORT_NAMES = NO -+JAVADOC_AUTOBRIEF = YES -+MULTILINE_CPP_IS_BRIEF = NO -+DETAILS_AT_TOP = YES -+INHERIT_DOCS = YES -+SEPARATE_MEMBER_PAGES = NO -+TAB_SIZE = 8 -+ALIASES = -+OPTIMIZE_OUTPUT_FOR_C = YES -+OPTIMIZE_OUTPUT_JAVA = NO -+BUILTIN_STL_SUPPORT = NO -+DISTRIBUTE_GROUP_DOC = NO -+SUBGROUPING = NO -+#--------------------------------------------------------------------------- -+# Build related configuration options -+#--------------------------------------------------------------------------- -+EXTRACT_ALL = NO -+EXTRACT_PRIVATE = NO -+EXTRACT_STATIC = YES -+EXTRACT_LOCAL_CLASSES = NO -+EXTRACT_LOCAL_METHODS = NO -+HIDE_UNDOC_MEMBERS = NO -+HIDE_UNDOC_CLASSES = NO -+HIDE_FRIEND_COMPOUNDS = NO -+HIDE_IN_BODY_DOCS = NO -+INTERNAL_DOCS = NO -+CASE_SENSE_NAMES = YES -+HIDE_SCOPE_NAMES = NO -+SHOW_INCLUDE_FILES = NO -+INLINE_INFO = YES -+SORT_MEMBER_DOCS = NO -+SORT_BRIEF_DOCS = NO -+SORT_BY_SCOPE_NAME = NO -+GENERATE_TODOLIST = YES -+GENERATE_TESTLIST = YES -+GENERATE_BUGLIST = YES -+GENERATE_DEPRECATEDLIST= YES -+ENABLED_SECTIONS = -+MAX_INITIALIZER_LINES = 30 -+SHOW_USED_FILES = YES -+SHOW_DIRECTORIES = YES -+FILE_VERSION_FILTER = -+#--------------------------------------------------------------------------- -+# configuration options related to warning and progress messages -+#--------------------------------------------------------------------------- -+QUIET = YES -+WARNINGS = YES -+WARN_IF_UNDOCUMENTED = NO -+WARN_IF_DOC_ERROR = YES -+WARN_NO_PARAMDOC = YES -+WARN_FORMAT = "$file:$line: $text" -+WARN_LOGFILE = -+#--------------------------------------------------------------------------- -+# configuration options related to the input files -+#--------------------------------------------------------------------------- -+INPUT = . -+FILE_PATTERNS = *.c \ -+ *.cc \ -+ *.cxx \ -+ *.cpp \ -+ *.c++ \ -+ *.d \ -+ *.java \ -+ *.ii \ -+ *.ixx \ -+ *.ipp \ -+ *.i++ \ -+ *.inl \ -+ *.h \ -+ *.hh \ -+ *.hxx \ -+ *.hpp \ -+ *.h++ \ -+ *.idl \ -+ *.odl \ -+ *.cs \ -+ *.php \ -+ *.php3 \ -+ *.inc \ -+ *.m \ -+ *.mm \ -+ *.dox \ -+ *.py \ -+ *.C \ -+ *.CC \ -+ *.C++ \ -+ *.II \ -+ *.I++ \ -+ *.H \ -+ *.HH \ -+ *.H++ \ -+ *.CS \ -+ *.PHP \ -+ *.PHP3 \ -+ *.M \ -+ *.MM \ -+ *.PY -+RECURSIVE = NO -+EXCLUDE = -+EXCLUDE_SYMLINKS = NO -+EXCLUDE_PATTERNS = -+EXAMPLE_PATH = -+EXAMPLE_PATTERNS = * -+EXAMPLE_RECURSIVE = NO -+IMAGE_PATH = -+INPUT_FILTER = -+FILTER_PATTERNS = -+FILTER_SOURCE_FILES = NO -+#--------------------------------------------------------------------------- -+# configuration options related to source browsing -+#--------------------------------------------------------------------------- -+SOURCE_BROWSER = NO -+INLINE_SOURCES = NO -+STRIP_CODE_COMMENTS = YES -+REFERENCED_BY_RELATION = YES -+REFERENCES_RELATION = YES -+USE_HTAGS = NO -+VERBATIM_HEADERS = NO -+#--------------------------------------------------------------------------- -+# configuration options related to the alphabetical class index -+#--------------------------------------------------------------------------- -+ALPHABETICAL_INDEX = NO -+COLS_IN_ALPHA_INDEX = 5 -+IGNORE_PREFIX = -+#--------------------------------------------------------------------------- -+# configuration options related to the HTML output -+#--------------------------------------------------------------------------- -+GENERATE_HTML = YES -+HTML_OUTPUT = html -+HTML_FILE_EXTENSION = .html -+HTML_HEADER = -+HTML_FOOTER = -+HTML_STYLESHEET = -+HTML_ALIGN_MEMBERS = YES -+GENERATE_HTMLHELP = NO -+CHM_FILE = -+HHC_LOCATION = -+GENERATE_CHI = NO -+BINARY_TOC = NO -+TOC_EXPAND = NO -+DISABLE_INDEX = NO -+ENUM_VALUES_PER_LINE = 4 -+GENERATE_TREEVIEW = YES -+TREEVIEW_WIDTH = 250 -+#--------------------------------------------------------------------------- -+# configuration options related to the LaTeX output -+#--------------------------------------------------------------------------- -+GENERATE_LATEX = NO -+LATEX_OUTPUT = latex -+LATEX_CMD_NAME = latex -+MAKEINDEX_CMD_NAME = makeindex -+COMPACT_LATEX = NO -+PAPER_TYPE = a4wide -+EXTRA_PACKAGES = -+LATEX_HEADER = -+PDF_HYPERLINKS = NO -+USE_PDFLATEX = NO -+LATEX_BATCHMODE = NO -+LATEX_HIDE_INDICES = NO -+#--------------------------------------------------------------------------- -+# configuration options related to the RTF output -+#--------------------------------------------------------------------------- -+GENERATE_RTF = NO -+RTF_OUTPUT = rtf -+COMPACT_RTF = NO -+RTF_HYPERLINKS = NO -+RTF_STYLESHEET_FILE = -+RTF_EXTENSIONS_FILE = -+#--------------------------------------------------------------------------- -+# configuration options related to the man page output -+#--------------------------------------------------------------------------- -+GENERATE_MAN = NO -+MAN_OUTPUT = man -+MAN_EXTENSION = .3 -+MAN_LINKS = NO -+#--------------------------------------------------------------------------- -+# configuration options related to the XML output -+#--------------------------------------------------------------------------- -+GENERATE_XML = NO -+XML_OUTPUT = xml -+XML_SCHEMA = -+XML_DTD = -+XML_PROGRAMLISTING = YES -+#--------------------------------------------------------------------------- -+# configuration options for the AutoGen Definitions output -+#--------------------------------------------------------------------------- -+GENERATE_AUTOGEN_DEF = NO -+#--------------------------------------------------------------------------- -+# configuration options related to the Perl module output -+#--------------------------------------------------------------------------- -+GENERATE_PERLMOD = NO -+PERLMOD_LATEX = NO -+PERLMOD_PRETTY = YES -+PERLMOD_MAKEVAR_PREFIX = -+#--------------------------------------------------------------------------- -+# Configuration options related to the preprocessor -+#--------------------------------------------------------------------------- -+ENABLE_PREPROCESSING = YES -+MACRO_EXPANSION = NO -+EXPAND_ONLY_PREDEF = NO -+SEARCH_INCLUDES = YES -+INCLUDE_PATH = -+INCLUDE_FILE_PATTERNS = -+PREDEFINED = DEBUG DEBUG_MEMORY -+EXPAND_AS_DEFINED = -+SKIP_FUNCTION_MACROS = YES -+#--------------------------------------------------------------------------- -+# Configuration::additions related to external references -+#--------------------------------------------------------------------------- -+TAGFILES = -+GENERATE_TAGFILE = -+ALLEXTERNALS = NO -+EXTERNAL_GROUPS = YES -+PERL_PATH = /usr/bin/perl -+#--------------------------------------------------------------------------- -+# Configuration options related to the dot tool -+#--------------------------------------------------------------------------- -+CLASS_DIAGRAMS = YES -+HIDE_UNDOC_RELATIONS = YES -+HAVE_DOT = NO -+CLASS_GRAPH = YES -+COLLABORATION_GRAPH = YES -+GROUP_GRAPHS = YES -+UML_LOOK = NO -+TEMPLATE_RELATIONS = NO -+INCLUDE_GRAPH = NO -+INCLUDED_BY_GRAPH = YES -+CALL_GRAPH = NO -+GRAPHICAL_HIERARCHY = YES -+DIRECTORY_GRAPH = YES -+DOT_IMAGE_FORMAT = png -+DOT_PATH = -+DOTFILE_DIRS = -+MAX_DOT_GRAPH_DEPTH = 1000 -+DOT_TRANSPARENT = NO -+DOT_MULTI_TARGETS = NO -+GENERATE_LEGEND = YES -+DOT_CLEANUP = YES -+#--------------------------------------------------------------------------- -+# Configuration::additions related to the search engine -+#--------------------------------------------------------------------------- -+SEARCHENGINE = NO -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_cc.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_cc.c ---- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_cc.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_cc.c 2015-11-29 09:42:39.915098960 +0100 -@@ -0,0 +1,532 @@ -+/* ========================================================================= -+ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_cc.c $ -+ * $Revision: #4 $ -+ * $Date: 2010/11/04 $ -+ * $Change: 1621692 $ -+ * -+ * Synopsys Portability Library Software and documentation -+ * (hereinafter, "Software") is an Unsupported proprietary work of -+ * Synopsys, Inc. unless otherwise expressly agreed to in writing -+ * between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product -+ * under any End User Software License Agreement or Agreement for -+ * Licensed Product with Synopsys or any supplement thereto. You are -+ * permitted to use and redistribute this Software in source and binary -+ * forms, with or without modification, provided that redistributions -+ * of source code must retain this notice. You may not view, use, -+ * disclose, copy or distribute this file or any information contained -+ * herein except pursuant to this license grant from Synopsys. If you -+ * do not agree with this notice, including the disclaimer below, then -+ * you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" -+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL -+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY -+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================= */ -+#ifdef DWC_CCLIB -+ -+#include "dwc_cc.h" -+ -+typedef struct dwc_cc -+{ -+ uint32_t uid; -+ uint8_t chid[16]; -+ uint8_t cdid[16]; -+ uint8_t ck[16]; -+ uint8_t *name; -+ uint8_t length; -+ DWC_CIRCLEQ_ENTRY(dwc_cc) list_entry; -+} dwc_cc_t; -+ -+DWC_CIRCLEQ_HEAD(context_list, dwc_cc); -+ -+/** The main structure for CC management. */ -+struct dwc_cc_if -+{ -+ dwc_mutex_t *mutex; -+ char *filename; -+ -+ unsigned is_host:1; -+ -+ dwc_notifier_t *notifier; -+ -+ struct context_list list; -+}; -+ -+#ifdef DEBUG -+static inline void dump_bytes(char *name, uint8_t *bytes, int len) -+{ -+ int i; -+ DWC_PRINTF("%s: ", name); -+ for (i=0; ilength = length; -+ cc->name = dwc_alloc(mem_ctx, length); -+ if (!cc->name) { -+ dwc_free(mem_ctx, cc); -+ return NULL; -+ } -+ -+ DWC_MEMCPY(cc->name, name, length); -+ } -+ -+ return cc; -+} -+ -+static void free_cc(void *mem_ctx, dwc_cc_t *cc) -+{ -+ if (cc->name) { -+ dwc_free(mem_ctx, cc->name); -+ } -+ dwc_free(mem_ctx, cc); -+} -+ -+static uint32_t next_uid(dwc_cc_if_t *cc_if) -+{ -+ uint32_t uid = 0; -+ dwc_cc_t *cc; -+ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) { -+ if (cc->uid > uid) { -+ uid = cc->uid; -+ } -+ } -+ -+ if (uid == 0) { -+ uid = 255; -+ } -+ -+ return uid + 1; -+} -+ -+static dwc_cc_t *cc_find(dwc_cc_if_t *cc_if, uint32_t uid) -+{ -+ dwc_cc_t *cc; -+ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) { -+ if (cc->uid == uid) { -+ return cc; -+ } -+ } -+ return NULL; -+} -+ -+static unsigned int cc_data_size(dwc_cc_if_t *cc_if) -+{ -+ unsigned int size = 0; -+ dwc_cc_t *cc; -+ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) { -+ size += (48 + 1); -+ if (cc->name) { -+ size += cc->length; -+ } -+ } -+ return size; -+} -+ -+static uint32_t cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid) -+{ -+ uint32_t uid = 0; -+ dwc_cc_t *cc; -+ -+ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) { -+ if (DWC_MEMCMP(cc->chid, chid, 16) == 0) { -+ uid = cc->uid; -+ break; -+ } -+ } -+ return uid; -+} -+static uint32_t cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid) -+{ -+ uint32_t uid = 0; -+ dwc_cc_t *cc; -+ -+ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) { -+ if (DWC_MEMCMP(cc->cdid, cdid, 16) == 0) { -+ uid = cc->uid; -+ break; -+ } -+ } -+ return uid; -+} -+ -+/* Internal cc_add */ -+static int32_t cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid, -+ uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length) -+{ -+ dwc_cc_t *cc; -+ uint32_t uid; -+ -+ if (cc_if->is_host) { -+ uid = cc_match_cdid(cc_if, cdid); -+ } -+ else { -+ uid = cc_match_chid(cc_if, chid); -+ } -+ -+ if (uid) { -+ DWC_DEBUGC("Replacing previous connection context id=%d name=%p name_len=%d", uid, name, length); -+ cc = cc_find(cc_if, uid); -+ } -+ else { -+ cc = alloc_cc(mem_ctx, name, length); -+ cc->uid = next_uid(cc_if); -+ DWC_CIRCLEQ_INSERT_TAIL(&cc_if->list, cc, list_entry); -+ } -+ -+ DWC_MEMCPY(&(cc->chid[0]), chid, 16); -+ DWC_MEMCPY(&(cc->cdid[0]), cdid, 16); -+ DWC_MEMCPY(&(cc->ck[0]), ck, 16); -+ -+ DWC_DEBUGC("Added connection context id=%d name=%p name_len=%d", cc->uid, name, length); -+ dump_bytes("CHID", cc->chid, 16); -+ dump_bytes("CDID", cc->cdid, 16); -+ dump_bytes("CK", cc->ck, 16); -+ return cc->uid; -+} -+ -+/* Internal cc_clear */ -+static void cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if) -+{ -+ while (!DWC_CIRCLEQ_EMPTY(&cc_if->list)) { -+ dwc_cc_t *cc = DWC_CIRCLEQ_FIRST(&cc_if->list); -+ DWC_CIRCLEQ_REMOVE_INIT(&cc_if->list, cc, list_entry); -+ free_cc(mem_ctx, cc); -+ } -+} -+ -+dwc_cc_if_t *dwc_cc_if_alloc(void *mem_ctx, void *mtx_ctx, -+ dwc_notifier_t *notifier, unsigned is_host) -+{ -+ dwc_cc_if_t *cc_if = NULL; -+ -+ /* Allocate a common_cc_if structure */ -+ cc_if = dwc_alloc(mem_ctx, sizeof(dwc_cc_if_t)); -+ -+ if (!cc_if) -+ return NULL; -+ -+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)) -+ DWC_MUTEX_ALLOC_LINUX_DEBUG(cc_if->mutex); -+#else -+ cc_if->mutex = dwc_mutex_alloc(mtx_ctx); -+#endif -+ if (!cc_if->mutex) { -+ dwc_free(mem_ctx, cc_if); -+ return NULL; -+ } -+ -+ DWC_CIRCLEQ_INIT(&cc_if->list); -+ cc_if->is_host = is_host; -+ cc_if->notifier = notifier; -+ return cc_if; -+} -+ -+void dwc_cc_if_free(void *mem_ctx, void *mtx_ctx, dwc_cc_if_t *cc_if) -+{ -+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)) -+ DWC_MUTEX_FREE(cc_if->mutex); -+#else -+ dwc_mutex_free(mtx_ctx, cc_if->mutex); -+#endif -+ cc_clear(mem_ctx, cc_if); -+ dwc_free(mem_ctx, cc_if); -+} -+ -+static void cc_changed(dwc_cc_if_t *cc_if) -+{ -+ if (cc_if->notifier) { -+ dwc_notify(cc_if->notifier, DWC_CC_LIST_CHANGED_NOTIFICATION, cc_if); -+ } -+} -+ -+void dwc_cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if) -+{ -+ DWC_MUTEX_LOCK(cc_if->mutex); -+ cc_clear(mem_ctx, cc_if); -+ DWC_MUTEX_UNLOCK(cc_if->mutex); -+ cc_changed(cc_if); -+} -+ -+int32_t dwc_cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid, -+ uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length) -+{ -+ uint32_t uid; -+ -+ DWC_MUTEX_LOCK(cc_if->mutex); -+ uid = cc_add(mem_ctx, cc_if, chid, cdid, ck, name, length); -+ DWC_MUTEX_UNLOCK(cc_if->mutex); -+ cc_changed(cc_if); -+ -+ return uid; -+} -+ -+void dwc_cc_change(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id, uint8_t *chid, -+ uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length) -+{ -+ dwc_cc_t* cc; -+ -+ DWC_DEBUGC("Change connection context %d", id); -+ -+ DWC_MUTEX_LOCK(cc_if->mutex); -+ cc = cc_find(cc_if, id); -+ if (!cc) { -+ DWC_ERROR("Uid %d not found in cc list\n", id); -+ DWC_MUTEX_UNLOCK(cc_if->mutex); -+ return; -+ } -+ -+ if (chid) { -+ DWC_MEMCPY(&(cc->chid[0]), chid, 16); -+ } -+ if (cdid) { -+ DWC_MEMCPY(&(cc->cdid[0]), cdid, 16); -+ } -+ if (ck) { -+ DWC_MEMCPY(&(cc->ck[0]), ck, 16); -+ } -+ -+ if (name) { -+ if (cc->name) { -+ dwc_free(mem_ctx, cc->name); -+ } -+ cc->name = dwc_alloc(mem_ctx, length); -+ if (!cc->name) { -+ DWC_ERROR("Out of memory in dwc_cc_change()\n"); -+ DWC_MUTEX_UNLOCK(cc_if->mutex); -+ return; -+ } -+ cc->length = length; -+ DWC_MEMCPY(cc->name, name, length); -+ } -+ -+ DWC_MUTEX_UNLOCK(cc_if->mutex); -+ -+ cc_changed(cc_if); -+ -+ DWC_DEBUGC("Changed connection context id=%d\n", id); -+ dump_bytes("New CHID", cc->chid, 16); -+ dump_bytes("New CDID", cc->cdid, 16); -+ dump_bytes("New CK", cc->ck, 16); -+} -+ -+void dwc_cc_remove(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id) -+{ -+ dwc_cc_t *cc; -+ -+ DWC_DEBUGC("Removing connection context %d", id); -+ -+ DWC_MUTEX_LOCK(cc_if->mutex); -+ cc = cc_find(cc_if, id); -+ if (!cc) { -+ DWC_ERROR("Uid %d not found in cc list\n", id); -+ DWC_MUTEX_UNLOCK(cc_if->mutex); -+ return; -+ } -+ -+ DWC_CIRCLEQ_REMOVE_INIT(&cc_if->list, cc, list_entry); -+ DWC_MUTEX_UNLOCK(cc_if->mutex); -+ free_cc(mem_ctx, cc); -+ -+ cc_changed(cc_if); -+} -+ -+uint8_t *dwc_cc_data_for_save(void *mem_ctx, dwc_cc_if_t *cc_if, unsigned int *length) -+{ -+ uint8_t *buf, *x; -+ uint8_t zero = 0; -+ dwc_cc_t *cc; -+ -+ DWC_MUTEX_LOCK(cc_if->mutex); -+ *length = cc_data_size(cc_if); -+ if (!(*length)) { -+ DWC_MUTEX_UNLOCK(cc_if->mutex); -+ return NULL; -+ } -+ -+ DWC_DEBUGC("Creating data for saving (length=%d)", *length); -+ -+ buf = dwc_alloc(mem_ctx, *length); -+ if (!buf) { -+ *length = 0; -+ DWC_MUTEX_UNLOCK(cc_if->mutex); -+ return NULL; -+ } -+ -+ x = buf; -+ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) { -+ DWC_MEMCPY(x, cc->chid, 16); -+ x += 16; -+ DWC_MEMCPY(x, cc->cdid, 16); -+ x += 16; -+ DWC_MEMCPY(x, cc->ck, 16); -+ x += 16; -+ if (cc->name) { -+ DWC_MEMCPY(x, &cc->length, 1); -+ x += 1; -+ DWC_MEMCPY(x, cc->name, cc->length); -+ x += cc->length; -+ } -+ else { -+ DWC_MEMCPY(x, &zero, 1); -+ x += 1; -+ } -+ } -+ DWC_MUTEX_UNLOCK(cc_if->mutex); -+ -+ return buf; -+} -+ -+void dwc_cc_restore_from_data(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *data, uint32_t length) -+{ -+ uint8_t name_length; -+ uint8_t *name; -+ uint8_t *chid; -+ uint8_t *cdid; -+ uint8_t *ck; -+ uint32_t i = 0; -+ -+ DWC_MUTEX_LOCK(cc_if->mutex); -+ cc_clear(mem_ctx, cc_if); -+ -+ while (i < length) { -+ chid = &data[i]; -+ i += 16; -+ cdid = &data[i]; -+ i += 16; -+ ck = &data[i]; -+ i += 16; -+ -+ name_length = data[i]; -+ i ++; -+ -+ if (name_length) { -+ name = &data[i]; -+ i += name_length; -+ } -+ else { -+ name = NULL; -+ } -+ -+ /* check to see if we haven't overflown the buffer */ -+ if (i > length) { -+ DWC_ERROR("Data format error while attempting to load CCs " -+ "(nlen=%d, iter=%d, buflen=%d).\n", name_length, i, length); -+ break; -+ } -+ -+ cc_add(mem_ctx, cc_if, chid, cdid, ck, name, name_length); -+ } -+ DWC_MUTEX_UNLOCK(cc_if->mutex); -+ -+ cc_changed(cc_if); -+} -+ -+uint32_t dwc_cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid) -+{ -+ uint32_t uid = 0; -+ -+ DWC_MUTEX_LOCK(cc_if->mutex); -+ uid = cc_match_chid(cc_if, chid); -+ DWC_MUTEX_UNLOCK(cc_if->mutex); -+ return uid; -+} -+uint32_t dwc_cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid) -+{ -+ uint32_t uid = 0; -+ -+ DWC_MUTEX_LOCK(cc_if->mutex); -+ uid = cc_match_cdid(cc_if, cdid); -+ DWC_MUTEX_UNLOCK(cc_if->mutex); -+ return uid; -+} -+ -+uint8_t *dwc_cc_ck(dwc_cc_if_t *cc_if, int32_t id) -+{ -+ uint8_t *ck = NULL; -+ dwc_cc_t *cc; -+ -+ DWC_MUTEX_LOCK(cc_if->mutex); -+ cc = cc_find(cc_if, id); -+ if (cc) { -+ ck = cc->ck; -+ } -+ DWC_MUTEX_UNLOCK(cc_if->mutex); -+ -+ return ck; -+ -+} -+ -+uint8_t *dwc_cc_chid(dwc_cc_if_t *cc_if, int32_t id) -+{ -+ uint8_t *retval = NULL; -+ dwc_cc_t *cc; -+ -+ DWC_MUTEX_LOCK(cc_if->mutex); -+ cc = cc_find(cc_if, id); -+ if (cc) { -+ retval = cc->chid; -+ } -+ DWC_MUTEX_UNLOCK(cc_if->mutex); -+ -+ return retval; -+} -+ -+uint8_t *dwc_cc_cdid(dwc_cc_if_t *cc_if, int32_t id) -+{ -+ uint8_t *retval = NULL; -+ dwc_cc_t *cc; -+ -+ DWC_MUTEX_LOCK(cc_if->mutex); -+ cc = cc_find(cc_if, id); -+ if (cc) { -+ retval = cc->cdid; -+ } -+ DWC_MUTEX_UNLOCK(cc_if->mutex); -+ -+ return retval; -+} -+ -+uint8_t *dwc_cc_name(dwc_cc_if_t *cc_if, int32_t id, uint8_t *length) -+{ -+ uint8_t *retval = NULL; -+ dwc_cc_t *cc; -+ -+ DWC_MUTEX_LOCK(cc_if->mutex); -+ *length = 0; -+ cc = cc_find(cc_if, id); -+ if (cc) { -+ *length = cc->length; -+ retval = cc->name; -+ } -+ DWC_MUTEX_UNLOCK(cc_if->mutex); -+ -+ return retval; -+} -+ -+#endif /* DWC_CCLIB */ -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_cc.h linux-rpi/drivers/usb/host/dwc_common_port/dwc_cc.h ---- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_cc.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_cc.h 2015-11-29 09:42:39.915098960 +0100 -@@ -0,0 +1,224 @@ -+/* ========================================================================= -+ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_cc.h $ -+ * $Revision: #4 $ -+ * $Date: 2010/09/28 $ -+ * $Change: 1596182 $ -+ * -+ * Synopsys Portability Library Software and documentation -+ * (hereinafter, "Software") is an Unsupported proprietary work of -+ * Synopsys, Inc. unless otherwise expressly agreed to in writing -+ * between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product -+ * under any End User Software License Agreement or Agreement for -+ * Licensed Product with Synopsys or any supplement thereto. You are -+ * permitted to use and redistribute this Software in source and binary -+ * forms, with or without modification, provided that redistributions -+ * of source code must retain this notice. You may not view, use, -+ * disclose, copy or distribute this file or any information contained -+ * herein except pursuant to this license grant from Synopsys. If you -+ * do not agree with this notice, including the disclaimer below, then -+ * you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" -+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL -+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY -+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================= */ -+#ifndef _DWC_CC_H_ -+#define _DWC_CC_H_ -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+/** @file -+ * -+ * This file defines the Context Context library. -+ * -+ * The main data structure is dwc_cc_if_t which is returned by either the -+ * dwc_cc_if_alloc function or returned by the module to the user via a provided -+ * function. The data structure is opaque and should only be manipulated via the -+ * functions provied in this API. -+ * -+ * It manages a list of connection contexts and operations can be performed to -+ * add, remove, query, search, and change, those contexts. Additionally, -+ * a dwc_notifier_t object can be requested from the manager so that -+ * the user can be notified whenever the context list has changed. -+ */ -+ -+#include "dwc_os.h" -+#include "dwc_list.h" -+#include "dwc_notifier.h" -+ -+ -+/* Notifications */ -+#define DWC_CC_LIST_CHANGED_NOTIFICATION "DWC_CC_LIST_CHANGED_NOTIFICATION" -+ -+struct dwc_cc_if; -+typedef struct dwc_cc_if dwc_cc_if_t; -+ -+ -+/** @name Connection Context Operations */ -+/** @{ */ -+ -+/** This function allocates memory for a dwc_cc_if_t structure, initializes -+ * fields to default values, and returns a pointer to the structure or NULL on -+ * error. */ -+extern dwc_cc_if_t *dwc_cc_if_alloc(void *mem_ctx, void *mtx_ctx, -+ dwc_notifier_t *notifier, unsigned is_host); -+ -+/** Frees the memory for the specified CC structure allocated from -+ * dwc_cc_if_alloc(). */ -+extern void dwc_cc_if_free(void *mem_ctx, void *mtx_ctx, dwc_cc_if_t *cc_if); -+ -+/** Removes all contexts from the connection context list */ -+extern void dwc_cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if); -+ -+/** Adds a connection context (CHID, CK, CDID, Name) to the connection context list. -+ * If a CHID already exists, the CK and name are overwritten. Statistics are -+ * not overwritten. -+ * -+ * @param cc_if The cc_if structure. -+ * @param chid A pointer to the 16-byte CHID. This value will be copied. -+ * @param ck A pointer to the 16-byte CK. This value will be copied. -+ * @param cdid A pointer to the 16-byte CDID. This value will be copied. -+ * @param name An optional host friendly name as defined in the association model -+ * spec. Must be a UTF16-LE unicode string. Can be NULL to indicated no name. -+ * @param length The length othe unicode string. -+ * @return A unique identifier used to refer to this context that is valid for -+ * as long as this context is still in the list. */ -+extern int32_t dwc_cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid, -+ uint8_t *cdid, uint8_t *ck, uint8_t *name, -+ uint8_t length); -+ -+/** Changes the CHID, CK, CDID, or Name values of a connection context in the -+ * list, preserving any accumulated statistics. This would typically be called -+ * if the host decideds to change the context with a SET_CONNECTION request. -+ * -+ * @param cc_if The cc_if structure. -+ * @param id The identifier of the connection context. -+ * @param chid A pointer to the 16-byte CHID. This value will be copied. NULL -+ * indicates no change. -+ * @param cdid A pointer to the 16-byte CDID. This value will be copied. NULL -+ * indicates no change. -+ * @param ck A pointer to the 16-byte CK. This value will be copied. NULL -+ * indicates no change. -+ * @param name Host friendly name UTF16-LE. NULL indicates no change. -+ * @param length Length of name. */ -+extern void dwc_cc_change(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id, -+ uint8_t *chid, uint8_t *cdid, uint8_t *ck, -+ uint8_t *name, uint8_t length); -+ -+/** Remove the specified connection context. -+ * @param cc_if The cc_if structure. -+ * @param id The identifier of the connection context to remove. */ -+extern void dwc_cc_remove(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id); -+ -+/** Get a binary block of data for the connection context list and attributes. -+ * This data can be used by the OS specific driver to save the connection -+ * context list into non-volatile memory. -+ * -+ * @param cc_if The cc_if structure. -+ * @param length Return the length of the data buffer. -+ * @return A pointer to the data buffer. The memory for this buffer should be -+ * freed with DWC_FREE() after use. */ -+extern uint8_t *dwc_cc_data_for_save(void *mem_ctx, dwc_cc_if_t *cc_if, -+ unsigned int *length); -+ -+/** Restore the connection context list from the binary data that was previously -+ * returned from a call to dwc_cc_data_for_save. This can be used by the OS specific -+ * driver to load a connection context list from non-volatile memory. -+ * -+ * @param cc_if The cc_if structure. -+ * @param data The data bytes as returned from dwc_cc_data_for_save. -+ * @param length The length of the data. */ -+extern void dwc_cc_restore_from_data(void *mem_ctx, dwc_cc_if_t *cc_if, -+ uint8_t *data, unsigned int length); -+ -+/** Find the connection context from the specified CHID. -+ * -+ * @param cc_if The cc_if structure. -+ * @param chid A pointer to the CHID data. -+ * @return A non-zero identifier of the connection context if the CHID matches. -+ * Otherwise returns 0. */ -+extern uint32_t dwc_cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid); -+ -+/** Find the connection context from the specified CDID. -+ * -+ * @param cc_if The cc_if structure. -+ * @param cdid A pointer to the CDID data. -+ * @return A non-zero identifier of the connection context if the CHID matches. -+ * Otherwise returns 0. */ -+extern uint32_t dwc_cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid); -+ -+/** Retrieve the CK from the specified connection context. -+ * -+ * @param cc_if The cc_if structure. -+ * @param id The identifier of the connection context. -+ * @return A pointer to the CK data. The memory does not need to be freed. */ -+extern uint8_t *dwc_cc_ck(dwc_cc_if_t *cc_if, int32_t id); -+ -+/** Retrieve the CHID from the specified connection context. -+ * -+ * @param cc_if The cc_if structure. -+ * @param id The identifier of the connection context. -+ * @return A pointer to the CHID data. The memory does not need to be freed. */ -+extern uint8_t *dwc_cc_chid(dwc_cc_if_t *cc_if, int32_t id); -+ -+/** Retrieve the CDID from the specified connection context. -+ * -+ * @param cc_if The cc_if structure. -+ * @param id The identifier of the connection context. -+ * @return A pointer to the CDID data. The memory does not need to be freed. */ -+extern uint8_t *dwc_cc_cdid(dwc_cc_if_t *cc_if, int32_t id); -+ -+extern uint8_t *dwc_cc_name(dwc_cc_if_t *cc_if, int32_t id, uint8_t *length); -+ -+/** Checks a buffer for non-zero. -+ * @param id A pointer to a 16 byte buffer. -+ * @return true if the 16 byte value is non-zero. */ -+static inline unsigned dwc_assoc_is_not_zero_id(uint8_t *id) { -+ int i; -+ for (i=0; i<16; i++) { -+ if (id[i]) return 1; -+ } -+ return 0; -+} -+ -+/** Checks a buffer for zero. -+ * @param id A pointer to a 16 byte buffer. -+ * @return true if the 16 byte value is zero. */ -+static inline unsigned dwc_assoc_is_zero_id(uint8_t *id) { -+ return !dwc_assoc_is_not_zero_id(id); -+} -+ -+/** Prints an ASCII representation for the 16-byte chid, cdid, or ck, into -+ * buffer. */ -+static inline int dwc_print_id_string(char *buffer, uint8_t *id) { -+ char *ptr = buffer; -+ int i; -+ for (i=0; i<16; i++) { -+ ptr += DWC_SPRINTF(ptr, "%02x", id[i]); -+ if (i < 15) { -+ ptr += DWC_SPRINTF(ptr, " "); -+ } -+ } -+ return ptr - buffer; -+} -+ -+/** @} */ -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* _DWC_CC_H_ */ -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_common_fbsd.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_common_fbsd.c ---- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_common_fbsd.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_common_fbsd.c 2015-11-29 09:42:39.915098960 +0100 -@@ -0,0 +1,1308 @@ -+#include "dwc_os.h" -+#include "dwc_list.h" -+ -+#ifdef DWC_CCLIB -+# include "dwc_cc.h" -+#endif -+ -+#ifdef DWC_CRYPTOLIB -+# include "dwc_modpow.h" -+# include "dwc_dh.h" -+# include "dwc_crypto.h" -+#endif -+ -+#ifdef DWC_NOTIFYLIB -+# include "dwc_notifier.h" -+#endif -+ -+/* OS-Level Implementations */ -+ -+/* This is the FreeBSD 7.0 kernel implementation of the DWC platform library. */ -+ -+ -+/* MISC */ -+ -+void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size) -+{ -+ return memset(dest, byte, size); -+} -+ -+void *DWC_MEMCPY(void *dest, void const *src, uint32_t size) -+{ -+ return memcpy(dest, src, size); -+} -+ -+void *DWC_MEMMOVE(void *dest, void *src, uint32_t size) -+{ -+ bcopy(src, dest, size); -+ return dest; -+} -+ -+int DWC_MEMCMP(void *m1, void *m2, uint32_t size) -+{ -+ return memcmp(m1, m2, size); -+} -+ -+int DWC_STRNCMP(void *s1, void *s2, uint32_t size) -+{ -+ return strncmp(s1, s2, size); -+} -+ -+int DWC_STRCMP(void *s1, void *s2) -+{ -+ return strcmp(s1, s2); -+} -+ -+int DWC_STRLEN(char const *str) -+{ -+ return strlen(str); -+} -+ -+char *DWC_STRCPY(char *to, char const *from) -+{ -+ return strcpy(to, from); -+} -+ -+char *DWC_STRDUP(char const *str) -+{ -+ int len = DWC_STRLEN(str) + 1; -+ char *new = DWC_ALLOC_ATOMIC(len); -+ -+ if (!new) { -+ return NULL; -+ } -+ -+ DWC_MEMCPY(new, str, len); -+ return new; -+} -+ -+int DWC_ATOI(char *str, int32_t *value) -+{ -+ char *end = NULL; -+ -+ *value = strtol(str, &end, 0); -+ if (*end == '\0') { -+ return 0; -+ } -+ -+ return -1; -+} -+ -+int DWC_ATOUI(char *str, uint32_t *value) -+{ -+ char *end = NULL; -+ -+ *value = strtoul(str, &end, 0); -+ if (*end == '\0') { -+ return 0; -+ } -+ -+ return -1; -+} -+ -+ -+#ifdef DWC_UTFLIB -+/* From usbstring.c */ -+ -+int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len) -+{ -+ int count = 0; -+ u8 c; -+ u16 uchar; -+ -+ /* this insists on correct encodings, though not minimal ones. -+ * BUT it currently rejects legit 4-byte UTF-8 code points, -+ * which need surrogate pairs. (Unicode 3.1 can use them.) -+ */ -+ while (len != 0 && (c = (u8) *s++) != 0) { -+ if (unlikely(c & 0x80)) { -+ // 2-byte sequence: -+ // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx -+ if ((c & 0xe0) == 0xc0) { -+ uchar = (c & 0x1f) << 6; -+ -+ c = (u8) *s++; -+ if ((c & 0xc0) != 0xc0) -+ goto fail; -+ c &= 0x3f; -+ uchar |= c; -+ -+ // 3-byte sequence (most CJKV characters): -+ // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx -+ } else if ((c & 0xf0) == 0xe0) { -+ uchar = (c & 0x0f) << 12; -+ -+ c = (u8) *s++; -+ if ((c & 0xc0) != 0xc0) -+ goto fail; -+ c &= 0x3f; -+ uchar |= c << 6; -+ -+ c = (u8) *s++; -+ if ((c & 0xc0) != 0xc0) -+ goto fail; -+ c &= 0x3f; -+ uchar |= c; -+ -+ /* no bogus surrogates */ -+ if (0xd800 <= uchar && uchar <= 0xdfff) -+ goto fail; -+ -+ // 4-byte sequence (surrogate pairs, currently rare): -+ // 11101110wwwwzzzzyy + 110111yyyyxxxxxx -+ // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx -+ // (uuuuu = wwww + 1) -+ // FIXME accept the surrogate code points (only) -+ } else -+ goto fail; -+ } else -+ uchar = c; -+ put_unaligned (cpu_to_le16 (uchar), cp++); -+ count++; -+ len--; -+ } -+ return count; -+fail: -+ return -1; -+} -+ -+#endif /* DWC_UTFLIB */ -+ -+ -+/* dwc_debug.h */ -+ -+dwc_bool_t DWC_IN_IRQ(void) -+{ -+// return in_irq(); -+ return 0; -+} -+ -+dwc_bool_t DWC_IN_BH(void) -+{ -+// return in_softirq(); -+ return 0; -+} -+ -+void DWC_VPRINTF(char *format, va_list args) -+{ -+ vprintf(format, args); -+} -+ -+int DWC_VSNPRINTF(char *str, int size, char *format, va_list args) -+{ -+ return vsnprintf(str, size, format, args); -+} -+ -+void DWC_PRINTF(char *format, ...) -+{ -+ va_list args; -+ -+ va_start(args, format); -+ DWC_VPRINTF(format, args); -+ va_end(args); -+} -+ -+int DWC_SPRINTF(char *buffer, char *format, ...) -+{ -+ int retval; -+ va_list args; -+ -+ va_start(args, format); -+ retval = vsprintf(buffer, format, args); -+ va_end(args); -+ return retval; -+} -+ -+int DWC_SNPRINTF(char *buffer, int size, char *format, ...) -+{ -+ int retval; -+ va_list args; -+ -+ va_start(args, format); -+ retval = vsnprintf(buffer, size, format, args); -+ va_end(args); -+ return retval; -+} -+ -+void __DWC_WARN(char *format, ...) -+{ -+ va_list args; -+ -+ va_start(args, format); -+ DWC_VPRINTF(format, args); -+ va_end(args); -+} -+ -+void __DWC_ERROR(char *format, ...) -+{ -+ va_list args; -+ -+ va_start(args, format); -+ DWC_VPRINTF(format, args); -+ va_end(args); -+} -+ -+void DWC_EXCEPTION(char *format, ...) -+{ -+ va_list args; -+ -+ va_start(args, format); -+ DWC_VPRINTF(format, args); -+ va_end(args); -+// BUG_ON(1); ??? -+} -+ -+#ifdef DEBUG -+void __DWC_DEBUG(char *format, ...) -+{ -+ va_list args; -+ -+ va_start(args, format); -+ DWC_VPRINTF(format, args); -+ va_end(args); -+} -+#endif -+ -+ -+/* dwc_mem.h */ -+ -+#if 0 -+dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size, -+ uint32_t align, -+ uint32_t alloc) -+{ -+ struct dma_pool *pool = dma_pool_create("Pool", NULL, -+ size, align, alloc); -+ return (dwc_pool_t *)pool; -+} -+ -+void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool) -+{ -+ dma_pool_destroy((struct dma_pool *)pool); -+} -+ -+void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr) -+{ -+// return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr); -+ return dma_pool_alloc((struct dma_pool *)pool, M_WAITOK, dma_addr); -+} -+ -+void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr) -+{ -+ void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr); -+ memset(..); -+} -+ -+void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr) -+{ -+ dma_pool_free(pool, vaddr, daddr); -+} -+#endif -+ -+static void dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) -+{ -+ if (error) -+ return; -+ *(bus_addr_t *)arg = segs[0].ds_addr; -+} -+ -+void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr) -+{ -+ dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx; -+ int error; -+ -+ error = bus_dma_tag_create( -+#if __FreeBSD_version >= 700000 -+ bus_get_dma_tag(dma->dev), /* parent */ -+#else -+ NULL, /* parent */ -+#endif -+ 4, 0, /* alignment, bounds */ -+ BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ -+ BUS_SPACE_MAXADDR, /* highaddr */ -+ NULL, NULL, /* filter, filterarg */ -+ size, /* maxsize */ -+ 1, /* nsegments */ -+ size, /* maxsegsize */ -+ 0, /* flags */ -+ NULL, /* lockfunc */ -+ NULL, /* lockarg */ -+ &dma->dma_tag); -+ if (error) { -+ device_printf(dma->dev, "%s: bus_dma_tag_create failed: %d\n", -+ __func__, error); -+ goto fail_0; -+ } -+ -+ error = bus_dmamem_alloc(dma->dma_tag, &dma->dma_vaddr, -+ BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map); -+ if (error) { -+ device_printf(dma->dev, "%s: bus_dmamem_alloc(%ju) failed: %d\n", -+ __func__, (uintmax_t)size, error); -+ goto fail_1; -+ } -+ -+ dma->dma_paddr = 0; -+ error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, size, -+ dmamap_cb, &dma->dma_paddr, BUS_DMA_NOWAIT); -+ if (error || dma->dma_paddr == 0) { -+ device_printf(dma->dev, "%s: bus_dmamap_load failed: %d\n", -+ __func__, error); -+ goto fail_2; -+ } -+ -+ *dma_addr = dma->dma_paddr; -+ return dma->dma_vaddr; -+ -+fail_2: -+ bus_dmamap_unload(dma->dma_tag, dma->dma_map); -+fail_1: -+ bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); -+ bus_dma_tag_destroy(dma->dma_tag); -+fail_0: -+ dma->dma_map = NULL; -+ dma->dma_tag = NULL; -+ -+ return NULL; -+} -+ -+void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr) -+{ -+ dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx; -+ -+ if (dma->dma_tag == NULL) -+ return; -+ if (dma->dma_map != NULL) { -+ bus_dmamap_sync(dma->dma_tag, dma->dma_map, -+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); -+ bus_dmamap_unload(dma->dma_tag, dma->dma_map); -+ bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); -+ dma->dma_map = NULL; -+ } -+ -+ bus_dma_tag_destroy(dma->dma_tag); -+ dma->dma_tag = NULL; -+} -+ -+void *__DWC_ALLOC(void *mem_ctx, uint32_t size) -+{ -+ return malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); -+} -+ -+void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size) -+{ -+ return malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO); -+} -+ -+void __DWC_FREE(void *mem_ctx, void *addr) -+{ -+ free(addr, M_DEVBUF); -+} -+ -+ -+#ifdef DWC_CRYPTOLIB -+/* dwc_crypto.h */ -+ -+void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length) -+{ -+ get_random_bytes(buffer, length); -+} -+ -+int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out) -+{ -+ struct crypto_blkcipher *tfm; -+ struct blkcipher_desc desc; -+ struct scatterlist sgd; -+ struct scatterlist sgs; -+ -+ tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC); -+ if (tfm == NULL) { -+ printk("failed to load transform for aes CBC\n"); -+ return -1; -+ } -+ -+ crypto_blkcipher_setkey(tfm, key, keylen); -+ crypto_blkcipher_set_iv(tfm, iv, 16); -+ -+ sg_init_one(&sgd, out, messagelen); -+ sg_init_one(&sgs, message, messagelen); -+ -+ desc.tfm = tfm; -+ desc.flags = 0; -+ -+ if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) { -+ crypto_free_blkcipher(tfm); -+ DWC_ERROR("AES CBC encryption failed"); -+ return -1; -+ } -+ -+ crypto_free_blkcipher(tfm); -+ return 0; -+} -+ -+int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out) -+{ -+ struct crypto_hash *tfm; -+ struct hash_desc desc; -+ struct scatterlist sg; -+ -+ tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC); -+ if (IS_ERR(tfm)) { -+ DWC_ERROR("Failed to load transform for sha256: %ld", PTR_ERR(tfm)); -+ return 0; -+ } -+ desc.tfm = tfm; -+ desc.flags = 0; -+ -+ sg_init_one(&sg, message, len); -+ crypto_hash_digest(&desc, &sg, len, out); -+ crypto_free_hash(tfm); -+ -+ return 1; -+} -+ -+int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen, -+ uint8_t *key, uint32_t keylen, uint8_t *out) -+{ -+ struct crypto_hash *tfm; -+ struct hash_desc desc; -+ struct scatterlist sg; -+ -+ tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC); -+ if (IS_ERR(tfm)) { -+ DWC_ERROR("Failed to load transform for hmac(sha256): %ld", PTR_ERR(tfm)); -+ return 0; -+ } -+ desc.tfm = tfm; -+ desc.flags = 0; -+ -+ sg_init_one(&sg, message, messagelen); -+ crypto_hash_setkey(tfm, key, keylen); -+ crypto_hash_digest(&desc, &sg, messagelen, out); -+ crypto_free_hash(tfm); -+ -+ return 1; -+} -+ -+#endif /* DWC_CRYPTOLIB */ -+ -+ -+/* Byte Ordering Conversions */ -+ -+uint32_t DWC_CPU_TO_LE32(uint32_t *p) -+{ -+#ifdef __LITTLE_ENDIAN -+ return *p; -+#else -+ uint8_t *u_p = (uint8_t *)p; -+ -+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); -+#endif -+} -+ -+uint32_t DWC_CPU_TO_BE32(uint32_t *p) -+{ -+#ifdef __BIG_ENDIAN -+ return *p; -+#else -+ uint8_t *u_p = (uint8_t *)p; -+ -+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); -+#endif -+} -+ -+uint32_t DWC_LE32_TO_CPU(uint32_t *p) -+{ -+#ifdef __LITTLE_ENDIAN -+ return *p; -+#else -+ uint8_t *u_p = (uint8_t *)p; -+ -+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); -+#endif -+} -+ -+uint32_t DWC_BE32_TO_CPU(uint32_t *p) -+{ -+#ifdef __BIG_ENDIAN -+ return *p; -+#else -+ uint8_t *u_p = (uint8_t *)p; -+ -+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); -+#endif -+} -+ -+uint16_t DWC_CPU_TO_LE16(uint16_t *p) -+{ -+#ifdef __LITTLE_ENDIAN -+ return *p; -+#else -+ uint8_t *u_p = (uint8_t *)p; -+ return (u_p[1] | (u_p[0] << 8)); -+#endif -+} -+ -+uint16_t DWC_CPU_TO_BE16(uint16_t *p) -+{ -+#ifdef __BIG_ENDIAN -+ return *p; -+#else -+ uint8_t *u_p = (uint8_t *)p; -+ return (u_p[1] | (u_p[0] << 8)); -+#endif -+} -+ -+uint16_t DWC_LE16_TO_CPU(uint16_t *p) -+{ -+#ifdef __LITTLE_ENDIAN -+ return *p; -+#else -+ uint8_t *u_p = (uint8_t *)p; -+ return (u_p[1] | (u_p[0] << 8)); -+#endif -+} -+ -+uint16_t DWC_BE16_TO_CPU(uint16_t *p) -+{ -+#ifdef __BIG_ENDIAN -+ return *p; -+#else -+ uint8_t *u_p = (uint8_t *)p; -+ return (u_p[1] | (u_p[0] << 8)); -+#endif -+} -+ -+ -+/* Registers */ -+ -+uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg) -+{ -+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; -+ bus_size_t ior = (bus_size_t)reg; -+ -+ return bus_space_read_4(io->iot, io->ioh, ior); -+} -+ -+#if 0 -+uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg) -+{ -+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; -+ bus_size_t ior = (bus_size_t)reg; -+ -+ return bus_space_read_8(io->iot, io->ioh, ior); -+} -+#endif -+ -+void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value) -+{ -+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; -+ bus_size_t ior = (bus_size_t)reg; -+ -+ bus_space_write_4(io->iot, io->ioh, ior, value); -+} -+ -+#if 0 -+void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value) -+{ -+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; -+ bus_size_t ior = (bus_size_t)reg; -+ -+ bus_space_write_8(io->iot, io->ioh, ior, value); -+} -+#endif -+ -+void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask, -+ uint32_t set_mask) -+{ -+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; -+ bus_size_t ior = (bus_size_t)reg; -+ -+ bus_space_write_4(io->iot, io->ioh, ior, -+ (bus_space_read_4(io->iot, io->ioh, ior) & -+ ~clear_mask) | set_mask); -+} -+ -+#if 0 -+void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask, -+ uint64_t set_mask) -+{ -+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; -+ bus_size_t ior = (bus_size_t)reg; -+ -+ bus_space_write_8(io->iot, io->ioh, ior, -+ (bus_space_read_8(io->iot, io->ioh, ior) & -+ ~clear_mask) | set_mask); -+} -+#endif -+ -+ -+/* Locking */ -+ -+dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void) -+{ -+ struct mtx *sl = DWC_ALLOC(sizeof(*sl)); -+ -+ if (!sl) { -+ DWC_ERROR("Cannot allocate memory for spinlock"); -+ return NULL; -+ } -+ -+ mtx_init(sl, "dw3spn", NULL, MTX_SPIN); -+ return (dwc_spinlock_t *)sl; -+} -+ -+void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock) -+{ -+ struct mtx *sl = (struct mtx *)lock; -+ -+ mtx_destroy(sl); -+ DWC_FREE(sl); -+} -+ -+void DWC_SPINLOCK(dwc_spinlock_t *lock) -+{ -+ mtx_lock_spin((struct mtx *)lock); // ??? -+} -+ -+void DWC_SPINUNLOCK(dwc_spinlock_t *lock) -+{ -+ mtx_unlock_spin((struct mtx *)lock); // ??? -+} -+ -+void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags) -+{ -+ mtx_lock_spin((struct mtx *)lock); -+} -+ -+void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags) -+{ -+ mtx_unlock_spin((struct mtx *)lock); -+} -+ -+dwc_mutex_t *DWC_MUTEX_ALLOC(void) -+{ -+ struct mtx *m; -+ dwc_mutex_t *mutex = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mtx)); -+ -+ if (!mutex) { -+ DWC_ERROR("Cannot allocate memory for mutex"); -+ return NULL; -+ } -+ -+ m = (struct mtx *)mutex; -+ mtx_init(m, "dw3mtx", NULL, MTX_DEF); -+ return mutex; -+} -+ -+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)) -+#else -+void DWC_MUTEX_FREE(dwc_mutex_t *mutex) -+{ -+ mtx_destroy((struct mtx *)mutex); -+ DWC_FREE(mutex); -+} -+#endif -+ -+void DWC_MUTEX_LOCK(dwc_mutex_t *mutex) -+{ -+ struct mtx *m = (struct mtx *)mutex; -+ -+ mtx_lock(m); -+} -+ -+int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex) -+{ -+ struct mtx *m = (struct mtx *)mutex; -+ -+ return mtx_trylock(m); -+} -+ -+void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex) -+{ -+ struct mtx *m = (struct mtx *)mutex; -+ -+ mtx_unlock(m); -+} -+ -+ -+/* Timing */ -+ -+void DWC_UDELAY(uint32_t usecs) -+{ -+ DELAY(usecs); -+} -+ -+void DWC_MDELAY(uint32_t msecs) -+{ -+ do { -+ DELAY(1000); -+ } while (--msecs); -+} -+ -+void DWC_MSLEEP(uint32_t msecs) -+{ -+ struct timeval tv; -+ -+ tv.tv_sec = msecs / 1000; -+ tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000; -+ pause("dw3slp", tvtohz(&tv)); -+} -+ -+uint32_t DWC_TIME(void) -+{ -+ struct timeval tv; -+ -+ microuptime(&tv); // or getmicrouptime? (less precise, but faster) -+ return tv.tv_sec * 1000 + tv.tv_usec / 1000; -+} -+ -+ -+/* Timers */ -+ -+struct dwc_timer { -+ struct callout t; -+ char *name; -+ dwc_spinlock_t *lock; -+ dwc_timer_callback_t cb; -+ void *data; -+}; -+ -+dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data) -+{ -+ dwc_timer_t *t = DWC_ALLOC(sizeof(*t)); -+ -+ if (!t) { -+ DWC_ERROR("Cannot allocate memory for timer"); -+ return NULL; -+ } -+ -+ callout_init(&t->t, 1); -+ -+ t->name = DWC_STRDUP(name); -+ if (!t->name) { -+ DWC_ERROR("Cannot allocate memory for timer->name"); -+ goto no_name; -+ } -+ -+ t->lock = DWC_SPINLOCK_ALLOC(); -+ if (!t->lock) { -+ DWC_ERROR("Cannot allocate memory for lock"); -+ goto no_lock; -+ } -+ -+ t->cb = cb; -+ t->data = data; -+ -+ return t; -+ -+ no_lock: -+ DWC_FREE(t->name); -+ no_name: -+ DWC_FREE(t); -+ -+ return NULL; -+} -+ -+void DWC_TIMER_FREE(dwc_timer_t *timer) -+{ -+ callout_stop(&timer->t); -+ DWC_SPINLOCK_FREE(timer->lock); -+ DWC_FREE(timer->name); -+ DWC_FREE(timer); -+} -+ -+void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time) -+{ -+ struct timeval tv; -+ -+ tv.tv_sec = time / 1000; -+ tv.tv_usec = (time - tv.tv_sec * 1000) * 1000; -+ callout_reset(&timer->t, tvtohz(&tv), timer->cb, timer->data); -+} -+ -+void DWC_TIMER_CANCEL(dwc_timer_t *timer) -+{ -+ callout_stop(&timer->t); -+} -+ -+ -+/* Wait Queues */ -+ -+struct dwc_waitq { -+ struct mtx lock; -+ int abort; -+}; -+ -+dwc_waitq_t *DWC_WAITQ_ALLOC(void) -+{ -+ dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq)); -+ -+ if (!wq) { -+ DWC_ERROR("Cannot allocate memory for waitqueue"); -+ return NULL; -+ } -+ -+ mtx_init(&wq->lock, "dw3wtq", NULL, MTX_DEF); -+ wq->abort = 0; -+ -+ return wq; -+} -+ -+void DWC_WAITQ_FREE(dwc_waitq_t *wq) -+{ -+ mtx_destroy(&wq->lock); -+ DWC_FREE(wq); -+} -+ -+int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data) -+{ -+// intrmask_t ipl; -+ int result = 0; -+ -+ mtx_lock(&wq->lock); -+// ipl = splbio(); -+ -+ /* Skip the sleep if already aborted or triggered */ -+ if (!wq->abort && !cond(data)) { -+// splx(ipl); -+ result = msleep(wq, &wq->lock, PCATCH, "dw3wat", 0); // infinite timeout -+// ipl = splbio(); -+ } -+ -+ if (result == ERESTART) { // signaled - restart -+ result = -DWC_E_RESTART; -+ -+ } else if (result == EINTR) { // signaled - interrupt -+ result = -DWC_E_ABORT; -+ -+ } else if (wq->abort) { -+ result = -DWC_E_ABORT; -+ -+ } else { -+ result = 0; -+ } -+ -+ wq->abort = 0; -+// splx(ipl); -+ mtx_unlock(&wq->lock); -+ return result; -+} -+ -+int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, -+ void *data, int32_t msecs) -+{ -+ struct timeval tv, tv1, tv2; -+// intrmask_t ipl; -+ int result = 0; -+ -+ tv.tv_sec = msecs / 1000; -+ tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000; -+ -+ mtx_lock(&wq->lock); -+// ipl = splbio(); -+ -+ /* Skip the sleep if already aborted or triggered */ -+ if (!wq->abort && !cond(data)) { -+// splx(ipl); -+ getmicrouptime(&tv1); -+ result = msleep(wq, &wq->lock, PCATCH, "dw3wto", tvtohz(&tv)); -+ getmicrouptime(&tv2); -+// ipl = splbio(); -+ } -+ -+ if (result == 0) { // awoken -+ if (wq->abort) { -+ result = -DWC_E_ABORT; -+ } else { -+ tv2.tv_usec -= tv1.tv_usec; -+ if (tv2.tv_usec < 0) { -+ tv2.tv_usec += 1000000; -+ tv2.tv_sec--; -+ } -+ -+ tv2.tv_sec -= tv1.tv_sec; -+ result = tv2.tv_sec * 1000 + tv2.tv_usec / 1000; -+ result = msecs - result; -+ if (result <= 0) -+ result = 1; -+ } -+ } else if (result == ERESTART) { // signaled - restart -+ result = -DWC_E_RESTART; -+ -+ } else if (result == EINTR) { // signaled - interrupt -+ result = -DWC_E_ABORT; -+ -+ } else { // timed out -+ result = -DWC_E_TIMEOUT; -+ } -+ -+ wq->abort = 0; -+// splx(ipl); -+ mtx_unlock(&wq->lock); -+ return result; -+} -+ -+void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq) -+{ -+ wakeup(wq); -+} -+ -+void DWC_WAITQ_ABORT(dwc_waitq_t *wq) -+{ -+// intrmask_t ipl; -+ -+ mtx_lock(&wq->lock); -+// ipl = splbio(); -+ wq->abort = 1; -+ wakeup(wq); -+// splx(ipl); -+ mtx_unlock(&wq->lock); -+} -+ -+ -+/* Threading */ -+ -+struct dwc_thread { -+ struct proc *proc; -+ int abort; -+}; -+ -+dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data) -+{ -+ int retval; -+ dwc_thread_t *thread = DWC_ALLOC(sizeof(*thread)); -+ -+ if (!thread) { -+ return NULL; -+ } -+ -+ thread->abort = 0; -+ retval = kthread_create((void (*)(void *))func, data, &thread->proc, -+ RFPROC | RFNOWAIT, 0, "%s", name); -+ if (retval) { -+ DWC_FREE(thread); -+ return NULL; -+ } -+ -+ return thread; -+} -+ -+int DWC_THREAD_STOP(dwc_thread_t *thread) -+{ -+ int retval; -+ -+ thread->abort = 1; -+ retval = tsleep(&thread->abort, 0, "dw3stp", 60 * hz); -+ -+ if (retval == 0) { -+ /* DWC_THREAD_EXIT() will free the thread struct */ -+ return 0; -+ } -+ -+ /* NOTE: We leak the thread struct if thread doesn't die */ -+ -+ if (retval == EWOULDBLOCK) { -+ return -DWC_E_TIMEOUT; -+ } -+ -+ return -DWC_E_UNKNOWN; -+} -+ -+dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread) -+{ -+ return thread->abort; -+} -+ -+void DWC_THREAD_EXIT(dwc_thread_t *thread) -+{ -+ wakeup(&thread->abort); -+ DWC_FREE(thread); -+ kthread_exit(0); -+} -+ -+ -+/* tasklets -+ - Runs in interrupt context (cannot sleep) -+ - Each tasklet runs on a single CPU [ How can we ensure this on FreeBSD? Does it matter? ] -+ - Different tasklets can be running simultaneously on different CPUs [ shouldn't matter ] -+ */ -+struct dwc_tasklet { -+ struct task t; -+ dwc_tasklet_callback_t cb; -+ void *data; -+}; -+ -+static void tasklet_callback(void *data, int pending) // what to do with pending ??? -+{ -+ dwc_tasklet_t *task = (dwc_tasklet_t *)data; -+ -+ task->cb(task->data); -+} -+ -+dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data) -+{ -+ dwc_tasklet_t *task = DWC_ALLOC(sizeof(*task)); -+ -+ if (task) { -+ task->cb = cb; -+ task->data = data; -+ TASK_INIT(&task->t, 0, tasklet_callback, task); -+ } else { -+ DWC_ERROR("Cannot allocate memory for tasklet"); -+ } -+ -+ return task; -+} -+ -+void DWC_TASK_FREE(dwc_tasklet_t *task) -+{ -+ taskqueue_drain(taskqueue_fast, &task->t); // ??? -+ DWC_FREE(task); -+} -+ -+void DWC_TASK_SCHEDULE(dwc_tasklet_t *task) -+{ -+ /* Uses predefined system queue */ -+ taskqueue_enqueue_fast(taskqueue_fast, &task->t); -+} -+ -+ -+/* workqueues -+ - Runs in process context (can sleep) -+ */ -+typedef struct work_container { -+ dwc_work_callback_t cb; -+ void *data; -+ dwc_workq_t *wq; -+ char *name; -+ int hz; -+ -+#ifdef DEBUG -+ DWC_CIRCLEQ_ENTRY(work_container) entry; -+#endif -+ struct task task; -+} work_container_t; -+ -+#ifdef DEBUG -+DWC_CIRCLEQ_HEAD(work_container_queue, work_container); -+#endif -+ -+struct dwc_workq { -+ struct taskqueue *taskq; -+ dwc_spinlock_t *lock; -+ dwc_waitq_t *waitq; -+ int pending; -+ -+#ifdef DEBUG -+ struct work_container_queue entries; -+#endif -+}; -+ -+static void do_work(void *data, int pending) // what to do with pending ??? -+{ -+ work_container_t *container = (work_container_t *)data; -+ dwc_workq_t *wq = container->wq; -+ dwc_irqflags_t flags; -+ -+ if (container->hz) { -+ pause("dw3wrk", container->hz); -+ } -+ -+ container->cb(container->data); -+ DWC_DEBUG("Work done: %s, container=%p", container->name, container); -+ -+ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); -+ -+#ifdef DEBUG -+ DWC_CIRCLEQ_REMOVE(&wq->entries, container, entry); -+#endif -+ if (container->name) -+ DWC_FREE(container->name); -+ DWC_FREE(container); -+ wq->pending--; -+ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); -+ DWC_WAITQ_TRIGGER(wq->waitq); -+} -+ -+static int work_done(void *data) -+{ -+ dwc_workq_t *workq = (dwc_workq_t *)data; -+ -+ return workq->pending == 0; -+} -+ -+int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout) -+{ -+ return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout); -+} -+ -+dwc_workq_t *DWC_WORKQ_ALLOC(char *name) -+{ -+ dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq)); -+ -+ if (!wq) { -+ DWC_ERROR("Cannot allocate memory for workqueue"); -+ return NULL; -+ } -+ -+ wq->taskq = taskqueue_create(name, M_NOWAIT, taskqueue_thread_enqueue, &wq->taskq); -+ if (!wq->taskq) { -+ DWC_ERROR("Cannot allocate memory for taskqueue"); -+ goto no_taskq; -+ } -+ -+ wq->pending = 0; -+ -+ wq->lock = DWC_SPINLOCK_ALLOC(); -+ if (!wq->lock) { -+ DWC_ERROR("Cannot allocate memory for spinlock"); -+ goto no_lock; -+ } -+ -+ wq->waitq = DWC_WAITQ_ALLOC(); -+ if (!wq->waitq) { -+ DWC_ERROR("Cannot allocate memory for waitqueue"); -+ goto no_waitq; -+ } -+ -+ taskqueue_start_threads(&wq->taskq, 1, PWAIT, "%s taskq", "dw3tsk"); -+ -+#ifdef DEBUG -+ DWC_CIRCLEQ_INIT(&wq->entries); -+#endif -+ return wq; -+ -+ no_waitq: -+ DWC_SPINLOCK_FREE(wq->lock); -+ no_lock: -+ taskqueue_free(wq->taskq); -+ no_taskq: -+ DWC_FREE(wq); -+ -+ return NULL; -+} -+ -+void DWC_WORKQ_FREE(dwc_workq_t *wq) -+{ -+#ifdef DEBUG -+ dwc_irqflags_t flags; -+ -+ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); -+ -+ if (wq->pending != 0) { -+ struct work_container *container; -+ -+ DWC_ERROR("Destroying work queue with pending work"); -+ -+ DWC_CIRCLEQ_FOREACH(container, &wq->entries, entry) { -+ DWC_ERROR("Work %s still pending", container->name); -+ } -+ } -+ -+ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); -+#endif -+ DWC_WAITQ_FREE(wq->waitq); -+ DWC_SPINLOCK_FREE(wq->lock); -+ taskqueue_free(wq->taskq); -+ DWC_FREE(wq); -+} -+ -+void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data, -+ char *format, ...) -+{ -+ dwc_irqflags_t flags; -+ work_container_t *container; -+ static char name[128]; -+ va_list args; -+ -+ va_start(args, format); -+ DWC_VSNPRINTF(name, 128, format, args); -+ va_end(args); -+ -+ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); -+ wq->pending++; -+ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); -+ DWC_WAITQ_TRIGGER(wq->waitq); -+ -+ container = DWC_ALLOC_ATOMIC(sizeof(*container)); -+ if (!container) { -+ DWC_ERROR("Cannot allocate memory for container"); -+ return; -+ } -+ -+ container->name = DWC_STRDUP(name); -+ if (!container->name) { -+ DWC_ERROR("Cannot allocate memory for container->name"); -+ DWC_FREE(container); -+ return; -+ } -+ -+ container->cb = cb; -+ container->data = data; -+ container->wq = wq; -+ container->hz = 0; -+ -+ DWC_DEBUG("Queueing work: %s, container=%p", container->name, container); -+ -+ TASK_INIT(&container->task, 0, do_work, container); -+ -+#ifdef DEBUG -+ DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry); -+#endif -+ taskqueue_enqueue_fast(wq->taskq, &container->task); -+} -+ -+void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb, -+ void *data, uint32_t time, char *format, ...) -+{ -+ dwc_irqflags_t flags; -+ work_container_t *container; -+ static char name[128]; -+ struct timeval tv; -+ va_list args; -+ -+ va_start(args, format); -+ DWC_VSNPRINTF(name, 128, format, args); -+ va_end(args); -+ -+ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); -+ wq->pending++; -+ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); -+ DWC_WAITQ_TRIGGER(wq->waitq); -+ -+ container = DWC_ALLOC_ATOMIC(sizeof(*container)); -+ if (!container) { -+ DWC_ERROR("Cannot allocate memory for container"); -+ return; -+ } -+ -+ container->name = DWC_STRDUP(name); -+ if (!container->name) { -+ DWC_ERROR("Cannot allocate memory for container->name"); -+ DWC_FREE(container); -+ return; -+ } -+ -+ container->cb = cb; -+ container->data = data; -+ container->wq = wq; -+ -+ tv.tv_sec = time / 1000; -+ tv.tv_usec = (time - tv.tv_sec * 1000) * 1000; -+ container->hz = tvtohz(&tv); -+ -+ DWC_DEBUG("Queueing work: %s, container=%p", container->name, container); -+ -+ TASK_INIT(&container->task, 0, do_work, container); -+ -+#ifdef DEBUG -+ DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry); -+#endif -+ taskqueue_enqueue_fast(wq->taskq, &container->task); -+} -+ -+int DWC_WORKQ_PENDING(dwc_workq_t *wq) -+{ -+ return wq->pending; -+} -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_common_linux.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_common_linux.c ---- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_common_linux.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_common_linux.c 2015-11-29 09:42:39.915098960 +0100 -@@ -0,0 +1,1434 @@ -+#include -+#include -+#include -+#include -+ -+#ifdef DWC_CCLIB -+# include "dwc_cc.h" -+#endif -+ -+#ifdef DWC_CRYPTOLIB -+# include "dwc_modpow.h" -+# include "dwc_dh.h" -+# include "dwc_crypto.h" -+#endif -+ -+#ifdef DWC_NOTIFYLIB -+# include "dwc_notifier.h" -+#endif -+ -+/* OS-Level Implementations */ -+ -+/* This is the Linux kernel implementation of the DWC platform library. */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24) -+# include -+#else -+# include -+#endif -+ -+#include -+#include -+#include -+#include -+ -+#include "dwc_os.h" -+#include "dwc_list.h" -+ -+ -+/* MISC */ -+ -+void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size) -+{ -+ return memset(dest, byte, size); -+} -+ -+void *DWC_MEMCPY(void *dest, void const *src, uint32_t size) -+{ -+ return memcpy(dest, src, size); -+} -+ -+void *DWC_MEMMOVE(void *dest, void *src, uint32_t size) -+{ -+ return memmove(dest, src, size); -+} -+ -+int DWC_MEMCMP(void *m1, void *m2, uint32_t size) -+{ -+ return memcmp(m1, m2, size); -+} -+ -+int DWC_STRNCMP(void *s1, void *s2, uint32_t size) -+{ -+ return strncmp(s1, s2, size); -+} -+ -+int DWC_STRCMP(void *s1, void *s2) -+{ -+ return strcmp(s1, s2); -+} -+ -+int DWC_STRLEN(char const *str) -+{ -+ return strlen(str); -+} -+ -+char *DWC_STRCPY(char *to, char const *from) -+{ -+ return strcpy(to, from); -+} -+ -+char *DWC_STRDUP(char const *str) -+{ -+ int len = DWC_STRLEN(str) + 1; -+ char *new = DWC_ALLOC_ATOMIC(len); -+ -+ if (!new) { -+ return NULL; -+ } -+ -+ DWC_MEMCPY(new, str, len); -+ return new; -+} -+ -+int DWC_ATOI(const char *str, int32_t *value) -+{ -+ char *end = NULL; -+ -+ *value = simple_strtol(str, &end, 0); -+ if (*end == '\0') { -+ return 0; -+ } -+ -+ return -1; -+} -+ -+int DWC_ATOUI(const char *str, uint32_t *value) -+{ -+ char *end = NULL; -+ -+ *value = simple_strtoul(str, &end, 0); -+ if (*end == '\0') { -+ return 0; -+ } -+ -+ return -1; -+} -+ -+ -+#ifdef DWC_UTFLIB -+/* From usbstring.c */ -+ -+int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len) -+{ -+ int count = 0; -+ u8 c; -+ u16 uchar; -+ -+ /* this insists on correct encodings, though not minimal ones. -+ * BUT it currently rejects legit 4-byte UTF-8 code points, -+ * which need surrogate pairs. (Unicode 3.1 can use them.) -+ */ -+ while (len != 0 && (c = (u8) *s++) != 0) { -+ if (unlikely(c & 0x80)) { -+ // 2-byte sequence: -+ // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx -+ if ((c & 0xe0) == 0xc0) { -+ uchar = (c & 0x1f) << 6; -+ -+ c = (u8) *s++; -+ if ((c & 0xc0) != 0xc0) -+ goto fail; -+ c &= 0x3f; -+ uchar |= c; -+ -+ // 3-byte sequence (most CJKV characters): -+ // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx -+ } else if ((c & 0xf0) == 0xe0) { -+ uchar = (c & 0x0f) << 12; -+ -+ c = (u8) *s++; -+ if ((c & 0xc0) != 0xc0) -+ goto fail; -+ c &= 0x3f; -+ uchar |= c << 6; -+ -+ c = (u8) *s++; -+ if ((c & 0xc0) != 0xc0) -+ goto fail; -+ c &= 0x3f; -+ uchar |= c; -+ -+ /* no bogus surrogates */ -+ if (0xd800 <= uchar && uchar <= 0xdfff) -+ goto fail; -+ -+ // 4-byte sequence (surrogate pairs, currently rare): -+ // 11101110wwwwzzzzyy + 110111yyyyxxxxxx -+ // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx -+ // (uuuuu = wwww + 1) -+ // FIXME accept the surrogate code points (only) -+ } else -+ goto fail; -+ } else -+ uchar = c; -+ put_unaligned (cpu_to_le16 (uchar), cp++); -+ count++; -+ len--; -+ } -+ return count; -+fail: -+ return -1; -+} -+#endif /* DWC_UTFLIB */ -+ -+ -+/* dwc_debug.h */ -+ -+dwc_bool_t DWC_IN_IRQ(void) -+{ -+ return in_irq(); -+} -+ -+dwc_bool_t DWC_IN_BH(void) -+{ -+ return in_softirq(); -+} -+ -+void DWC_VPRINTF(char *format, va_list args) -+{ -+ vprintk(format, args); -+} -+ -+int DWC_VSNPRINTF(char *str, int size, char *format, va_list args) -+{ -+ return vsnprintf(str, size, format, args); -+} -+ -+void DWC_PRINTF(char *format, ...) -+{ -+ va_list args; -+ -+ va_start(args, format); -+ DWC_VPRINTF(format, args); -+ va_end(args); -+} -+ -+int DWC_SPRINTF(char *buffer, char *format, ...) -+{ -+ int retval; -+ va_list args; -+ -+ va_start(args, format); -+ retval = vsprintf(buffer, format, args); -+ va_end(args); -+ return retval; -+} -+ -+int DWC_SNPRINTF(char *buffer, int size, char *format, ...) -+{ -+ int retval; -+ va_list args; -+ -+ va_start(args, format); -+ retval = vsnprintf(buffer, size, format, args); -+ va_end(args); -+ return retval; -+} -+ -+void __DWC_WARN(char *format, ...) -+{ -+ va_list args; -+ -+ va_start(args, format); -+ DWC_PRINTF(KERN_WARNING); -+ DWC_VPRINTF(format, args); -+ va_end(args); -+} -+ -+void __DWC_ERROR(char *format, ...) -+{ -+ va_list args; -+ -+ va_start(args, format); -+ DWC_PRINTF(KERN_ERR); -+ DWC_VPRINTF(format, args); -+ va_end(args); -+} -+ -+void DWC_EXCEPTION(char *format, ...) -+{ -+ va_list args; -+ -+ va_start(args, format); -+ DWC_PRINTF(KERN_ERR); -+ DWC_VPRINTF(format, args); -+ va_end(args); -+ BUG_ON(1); -+} -+ -+#ifdef DEBUG -+void __DWC_DEBUG(char *format, ...) -+{ -+ va_list args; -+ -+ va_start(args, format); -+ DWC_PRINTF(KERN_DEBUG); -+ DWC_VPRINTF(format, args); -+ va_end(args); -+} -+#endif -+ -+ -+/* dwc_mem.h */ -+ -+#if 0 -+dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size, -+ uint32_t align, -+ uint32_t alloc) -+{ -+ struct dma_pool *pool = dma_pool_create("Pool", NULL, -+ size, align, alloc); -+ return (dwc_pool_t *)pool; -+} -+ -+void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool) -+{ -+ dma_pool_destroy((struct dma_pool *)pool); -+} -+ -+void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr) -+{ -+ return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr); -+} -+ -+void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr) -+{ -+ void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr); -+ memset(..); -+} -+ -+void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr) -+{ -+ dma_pool_free(pool, vaddr, daddr); -+} -+#endif -+ -+void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr) -+{ -+#ifdef xxCOSIM /* Only works for 32-bit cosim */ -+ void *buf = dma_alloc_coherent(dma_ctx, (size_t)size, dma_addr, GFP_KERNEL); -+#else -+ void *buf = dma_alloc_coherent(dma_ctx, (size_t)size, dma_addr, GFP_KERNEL | GFP_DMA32); -+#endif -+ if (!buf) { -+ return NULL; -+ } -+ -+ memset(buf, 0, (size_t)size); -+ return buf; -+} -+ -+void *__DWC_DMA_ALLOC_ATOMIC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr) -+{ -+ void *buf = dma_alloc_coherent(NULL, (size_t)size, dma_addr, GFP_ATOMIC); -+ if (!buf) { -+ return NULL; -+ } -+ memset(buf, 0, (size_t)size); -+ return buf; -+} -+ -+void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr) -+{ -+ dma_free_coherent(dma_ctx, size, virt_addr, dma_addr); -+} -+ -+void *__DWC_ALLOC(void *mem_ctx, uint32_t size) -+{ -+ return kzalloc(size, GFP_KERNEL); -+} -+ -+void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size) -+{ -+ return kzalloc(size, GFP_ATOMIC); -+} -+ -+void __DWC_FREE(void *mem_ctx, void *addr) -+{ -+ kfree(addr); -+} -+ -+ -+#ifdef DWC_CRYPTOLIB -+/* dwc_crypto.h */ -+ -+void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length) -+{ -+ get_random_bytes(buffer, length); -+} -+ -+int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out) -+{ -+ struct crypto_blkcipher *tfm; -+ struct blkcipher_desc desc; -+ struct scatterlist sgd; -+ struct scatterlist sgs; -+ -+ tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC); -+ if (tfm == NULL) { -+ printk("failed to load transform for aes CBC\n"); -+ return -1; -+ } -+ -+ crypto_blkcipher_setkey(tfm, key, keylen); -+ crypto_blkcipher_set_iv(tfm, iv, 16); -+ -+ sg_init_one(&sgd, out, messagelen); -+ sg_init_one(&sgs, message, messagelen); -+ -+ desc.tfm = tfm; -+ desc.flags = 0; -+ -+ if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) { -+ crypto_free_blkcipher(tfm); -+ DWC_ERROR("AES CBC encryption failed"); -+ return -1; -+ } -+ -+ crypto_free_blkcipher(tfm); -+ return 0; -+} -+ -+int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out) -+{ -+ struct crypto_hash *tfm; -+ struct hash_desc desc; -+ struct scatterlist sg; -+ -+ tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC); -+ if (IS_ERR(tfm)) { -+ DWC_ERROR("Failed to load transform for sha256: %ld\n", PTR_ERR(tfm)); -+ return 0; -+ } -+ desc.tfm = tfm; -+ desc.flags = 0; -+ -+ sg_init_one(&sg, message, len); -+ crypto_hash_digest(&desc, &sg, len, out); -+ crypto_free_hash(tfm); -+ -+ return 1; -+} -+ -+int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen, -+ uint8_t *key, uint32_t keylen, uint8_t *out) -+{ -+ struct crypto_hash *tfm; -+ struct hash_desc desc; -+ struct scatterlist sg; -+ -+ tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC); -+ if (IS_ERR(tfm)) { -+ DWC_ERROR("Failed to load transform for hmac(sha256): %ld\n", PTR_ERR(tfm)); -+ return 0; -+ } -+ desc.tfm = tfm; -+ desc.flags = 0; -+ -+ sg_init_one(&sg, message, messagelen); -+ crypto_hash_setkey(tfm, key, keylen); -+ crypto_hash_digest(&desc, &sg, messagelen, out); -+ crypto_free_hash(tfm); -+ -+ return 1; -+} -+#endif /* DWC_CRYPTOLIB */ -+ -+ -+/* Byte Ordering Conversions */ -+ -+uint32_t DWC_CPU_TO_LE32(uint32_t *p) -+{ -+#ifdef __LITTLE_ENDIAN -+ return *p; -+#else -+ uint8_t *u_p = (uint8_t *)p; -+ -+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); -+#endif -+} -+ -+uint32_t DWC_CPU_TO_BE32(uint32_t *p) -+{ -+#ifdef __BIG_ENDIAN -+ return *p; -+#else -+ uint8_t *u_p = (uint8_t *)p; -+ -+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); -+#endif -+} -+ -+uint32_t DWC_LE32_TO_CPU(uint32_t *p) -+{ -+#ifdef __LITTLE_ENDIAN -+ return *p; -+#else -+ uint8_t *u_p = (uint8_t *)p; -+ -+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); -+#endif -+} -+ -+uint32_t DWC_BE32_TO_CPU(uint32_t *p) -+{ -+#ifdef __BIG_ENDIAN -+ return *p; -+#else -+ uint8_t *u_p = (uint8_t *)p; -+ -+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); -+#endif -+} -+ -+uint16_t DWC_CPU_TO_LE16(uint16_t *p) -+{ -+#ifdef __LITTLE_ENDIAN -+ return *p; -+#else -+ uint8_t *u_p = (uint8_t *)p; -+ return (u_p[1] | (u_p[0] << 8)); -+#endif -+} -+ -+uint16_t DWC_CPU_TO_BE16(uint16_t *p) -+{ -+#ifdef __BIG_ENDIAN -+ return *p; -+#else -+ uint8_t *u_p = (uint8_t *)p; -+ return (u_p[1] | (u_p[0] << 8)); -+#endif -+} -+ -+uint16_t DWC_LE16_TO_CPU(uint16_t *p) -+{ -+#ifdef __LITTLE_ENDIAN -+ return *p; -+#else -+ uint8_t *u_p = (uint8_t *)p; -+ return (u_p[1] | (u_p[0] << 8)); -+#endif -+} -+ -+uint16_t DWC_BE16_TO_CPU(uint16_t *p) -+{ -+#ifdef __BIG_ENDIAN -+ return *p; -+#else -+ uint8_t *u_p = (uint8_t *)p; -+ return (u_p[1] | (u_p[0] << 8)); -+#endif -+} -+ -+ -+/* Registers */ -+ -+uint32_t DWC_READ_REG32(uint32_t volatile *reg) -+{ -+ return readl(reg); -+} -+ -+#if 0 -+uint64_t DWC_READ_REG64(uint64_t volatile *reg) -+{ -+} -+#endif -+ -+void DWC_WRITE_REG32(uint32_t volatile *reg, uint32_t value) -+{ -+ writel(value, reg); -+} -+ -+#if 0 -+void DWC_WRITE_REG64(uint64_t volatile *reg, uint64_t value) -+{ -+} -+#endif -+ -+void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask) -+{ -+ writel((readl(reg) & ~clear_mask) | set_mask, reg); -+} -+ -+#if 0 -+void DWC_MODIFY_REG64(uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask) -+{ -+} -+#endif -+ -+ -+/* Locking */ -+ -+dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void) -+{ -+ spinlock_t *sl = (spinlock_t *)1; -+ -+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) -+ sl = DWC_ALLOC(sizeof(*sl)); -+ if (!sl) { -+ DWC_ERROR("Cannot allocate memory for spinlock\n"); -+ return NULL; -+ } -+ -+ spin_lock_init(sl); -+#endif -+ return (dwc_spinlock_t *)sl; -+} -+ -+void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock) -+{ -+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) -+ DWC_FREE(lock); -+#endif -+} -+ -+void DWC_SPINLOCK(dwc_spinlock_t *lock) -+{ -+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) -+ spin_lock((spinlock_t *)lock); -+#endif -+} -+ -+void DWC_SPINUNLOCK(dwc_spinlock_t *lock) -+{ -+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) -+ spin_unlock((spinlock_t *)lock); -+#endif -+} -+ -+void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags) -+{ -+ dwc_irqflags_t f; -+ -+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) -+ spin_lock_irqsave((spinlock_t *)lock, f); -+#else -+ local_irq_save(f); -+#endif -+ *flags = f; -+} -+ -+void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags) -+{ -+#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) -+ spin_unlock_irqrestore((spinlock_t *)lock, flags); -+#else -+ local_irq_restore(flags); -+#endif -+} -+ -+dwc_mutex_t *DWC_MUTEX_ALLOC(void) -+{ -+ struct mutex *m; -+ dwc_mutex_t *mutex = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mutex)); -+ -+ if (!mutex) { -+ DWC_ERROR("Cannot allocate memory for mutex\n"); -+ return NULL; -+ } -+ -+ m = (struct mutex *)mutex; -+ mutex_init(m); -+ return mutex; -+} -+ -+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)) -+#else -+void DWC_MUTEX_FREE(dwc_mutex_t *mutex) -+{ -+ mutex_destroy((struct mutex *)mutex); -+ DWC_FREE(mutex); -+} -+#endif -+ -+void DWC_MUTEX_LOCK(dwc_mutex_t *mutex) -+{ -+ struct mutex *m = (struct mutex *)mutex; -+ mutex_lock(m); -+} -+ -+int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex) -+{ -+ struct mutex *m = (struct mutex *)mutex; -+ return mutex_trylock(m); -+} -+ -+void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex) -+{ -+ struct mutex *m = (struct mutex *)mutex; -+ mutex_unlock(m); -+} -+ -+ -+/* Timing */ -+ -+void DWC_UDELAY(uint32_t usecs) -+{ -+ udelay(usecs); -+} -+ -+void DWC_MDELAY(uint32_t msecs) -+{ -+ mdelay(msecs); -+} -+ -+void DWC_MSLEEP(uint32_t msecs) -+{ -+ msleep(msecs); -+} -+ -+uint32_t DWC_TIME(void) -+{ -+ return jiffies_to_msecs(jiffies); -+} -+ -+ -+/* Timers */ -+ -+struct dwc_timer { -+ struct timer_list *t; -+ char *name; -+ dwc_timer_callback_t cb; -+ void *data; -+ uint8_t scheduled; -+ dwc_spinlock_t *lock; -+}; -+ -+static void timer_callback(unsigned long data) -+{ -+ dwc_timer_t *timer = (dwc_timer_t *)data; -+ dwc_irqflags_t flags; -+ -+ DWC_SPINLOCK_IRQSAVE(timer->lock, &flags); -+ timer->scheduled = 0; -+ DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags); -+ DWC_DEBUGC("Timer %s callback", timer->name); -+ timer->cb(timer->data); -+} -+ -+dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data) -+{ -+ dwc_timer_t *t = DWC_ALLOC(sizeof(*t)); -+ -+ if (!t) { -+ DWC_ERROR("Cannot allocate memory for timer"); -+ return NULL; -+ } -+ -+ t->t = DWC_ALLOC(sizeof(*t->t)); -+ if (!t->t) { -+ DWC_ERROR("Cannot allocate memory for timer->t"); -+ goto no_timer; -+ } -+ -+ t->name = DWC_STRDUP(name); -+ if (!t->name) { -+ DWC_ERROR("Cannot allocate memory for timer->name"); -+ goto no_name; -+ } -+ -+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK)) -+ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(t->lock); -+#else -+ t->lock = DWC_SPINLOCK_ALLOC(); -+#endif -+ if (!t->lock) { -+ DWC_ERROR("Cannot allocate memory for lock"); -+ goto no_lock; -+ } -+ -+ t->scheduled = 0; -+ t->t->base = &boot_tvec_bases; -+ t->t->expires = jiffies; -+ setup_timer(t->t, timer_callback, (unsigned long)t); -+ -+ t->cb = cb; -+ t->data = data; -+ -+ return t; -+ -+ no_lock: -+ DWC_FREE(t->name); -+ no_name: -+ DWC_FREE(t->t); -+ no_timer: -+ DWC_FREE(t); -+ return NULL; -+} -+ -+void DWC_TIMER_FREE(dwc_timer_t *timer) -+{ -+ dwc_irqflags_t flags; -+ -+ DWC_SPINLOCK_IRQSAVE(timer->lock, &flags); -+ -+ if (timer->scheduled) { -+ del_timer(timer->t); -+ timer->scheduled = 0; -+ } -+ -+ DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags); -+ DWC_SPINLOCK_FREE(timer->lock); -+ DWC_FREE(timer->t); -+ DWC_FREE(timer->name); -+ DWC_FREE(timer); -+} -+ -+void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time) -+{ -+ dwc_irqflags_t flags; -+ -+ DWC_SPINLOCK_IRQSAVE(timer->lock, &flags); -+ -+ if (!timer->scheduled) { -+ timer->scheduled = 1; -+ DWC_DEBUGC("Scheduling timer %s to expire in +%d msec", timer->name, time); -+ timer->t->expires = jiffies + msecs_to_jiffies(time); -+ add_timer(timer->t); -+ } else { -+ DWC_DEBUGC("Modifying timer %s to expire in +%d msec", timer->name, time); -+ mod_timer(timer->t, jiffies + msecs_to_jiffies(time)); -+ } -+ -+ DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags); -+} -+ -+void DWC_TIMER_CANCEL(dwc_timer_t *timer) -+{ -+ del_timer(timer->t); -+} -+ -+ -+/* Wait Queues */ -+ -+struct dwc_waitq { -+ wait_queue_head_t queue; -+ int abort; -+}; -+ -+dwc_waitq_t *DWC_WAITQ_ALLOC(void) -+{ -+ dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq)); -+ -+ if (!wq) { -+ DWC_ERROR("Cannot allocate memory for waitqueue\n"); -+ return NULL; -+ } -+ -+ init_waitqueue_head(&wq->queue); -+ wq->abort = 0; -+ return wq; -+} -+ -+void DWC_WAITQ_FREE(dwc_waitq_t *wq) -+{ -+ DWC_FREE(wq); -+} -+ -+int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data) -+{ -+ int result = wait_event_interruptible(wq->queue, -+ cond(data) || wq->abort); -+ if (result == -ERESTARTSYS) { -+ wq->abort = 0; -+ return -DWC_E_RESTART; -+ } -+ -+ if (wq->abort == 1) { -+ wq->abort = 0; -+ return -DWC_E_ABORT; -+ } -+ -+ wq->abort = 0; -+ -+ if (result == 0) { -+ return 0; -+ } -+ -+ return -DWC_E_UNKNOWN; -+} -+ -+int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, -+ void *data, int32_t msecs) -+{ -+ int32_t tmsecs; -+ int result = wait_event_interruptible_timeout(wq->queue, -+ cond(data) || wq->abort, -+ msecs_to_jiffies(msecs)); -+ if (result == -ERESTARTSYS) { -+ wq->abort = 0; -+ return -DWC_E_RESTART; -+ } -+ -+ if (wq->abort == 1) { -+ wq->abort = 0; -+ return -DWC_E_ABORT; -+ } -+ -+ wq->abort = 0; -+ -+ if (result > 0) { -+ tmsecs = jiffies_to_msecs(result); -+ if (!tmsecs) { -+ return 1; -+ } -+ -+ return tmsecs; -+ } -+ -+ if (result == 0) { -+ return -DWC_E_TIMEOUT; -+ } -+ -+ return -DWC_E_UNKNOWN; -+} -+ -+void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq) -+{ -+ wq->abort = 0; -+ wake_up_interruptible(&wq->queue); -+} -+ -+void DWC_WAITQ_ABORT(dwc_waitq_t *wq) -+{ -+ wq->abort = 1; -+ wake_up_interruptible(&wq->queue); -+} -+ -+ -+/* Threading */ -+ -+dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data) -+{ -+ struct task_struct *thread = kthread_run(func, data, name); -+ -+ if (thread == ERR_PTR(-ENOMEM)) { -+ return NULL; -+ } -+ -+ return (dwc_thread_t *)thread; -+} -+ -+int DWC_THREAD_STOP(dwc_thread_t *thread) -+{ -+ return kthread_stop((struct task_struct *)thread); -+} -+ -+dwc_bool_t DWC_THREAD_SHOULD_STOP(void) -+{ -+ return kthread_should_stop(); -+} -+ -+ -+/* tasklets -+ - run in interrupt context (cannot sleep) -+ - each tasklet runs on a single CPU -+ - different tasklets can be running simultaneously on different CPUs -+ */ -+struct dwc_tasklet { -+ struct tasklet_struct t; -+ dwc_tasklet_callback_t cb; -+ void *data; -+}; -+ -+static void tasklet_callback(unsigned long data) -+{ -+ dwc_tasklet_t *t = (dwc_tasklet_t *)data; -+ t->cb(t->data); -+} -+ -+dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data) -+{ -+ dwc_tasklet_t *t = DWC_ALLOC(sizeof(*t)); -+ -+ if (t) { -+ t->cb = cb; -+ t->data = data; -+ tasklet_init(&t->t, tasklet_callback, (unsigned long)t); -+ } else { -+ DWC_ERROR("Cannot allocate memory for tasklet\n"); -+ } -+ -+ return t; -+} -+ -+void DWC_TASK_FREE(dwc_tasklet_t *task) -+{ -+ DWC_FREE(task); -+} -+ -+void DWC_TASK_SCHEDULE(dwc_tasklet_t *task) -+{ -+ tasklet_schedule(&task->t); -+} -+ -+void DWC_TASK_HI_SCHEDULE(dwc_tasklet_t *task) -+{ -+ tasklet_hi_schedule(&task->t); -+} -+ -+ -+/* workqueues -+ - run in process context (can sleep) -+ */ -+typedef struct work_container { -+ dwc_work_callback_t cb; -+ void *data; -+ dwc_workq_t *wq; -+ char *name; -+ -+#ifdef DEBUG -+ DWC_CIRCLEQ_ENTRY(work_container) entry; -+#endif -+ struct delayed_work work; -+} work_container_t; -+ -+#ifdef DEBUG -+DWC_CIRCLEQ_HEAD(work_container_queue, work_container); -+#endif -+ -+struct dwc_workq { -+ struct workqueue_struct *wq; -+ dwc_spinlock_t *lock; -+ dwc_waitq_t *waitq; -+ int pending; -+ -+#ifdef DEBUG -+ struct work_container_queue entries; -+#endif -+}; -+ -+static void do_work(struct work_struct *work) -+{ -+ dwc_irqflags_t flags; -+ struct delayed_work *dw = container_of(work, struct delayed_work, work); -+ work_container_t *container = container_of(dw, struct work_container, work); -+ dwc_workq_t *wq = container->wq; -+ -+ container->cb(container->data); -+ -+#ifdef DEBUG -+ DWC_CIRCLEQ_REMOVE(&wq->entries, container, entry); -+#endif -+ DWC_DEBUGC("Work done: %s, container=%p", container->name, container); -+ if (container->name) { -+ DWC_FREE(container->name); -+ } -+ DWC_FREE(container); -+ -+ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); -+ wq->pending--; -+ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); -+ DWC_WAITQ_TRIGGER(wq->waitq); -+} -+ -+static int work_done(void *data) -+{ -+ dwc_workq_t *workq = (dwc_workq_t *)data; -+ return workq->pending == 0; -+} -+ -+int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout) -+{ -+ return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout); -+} -+ -+dwc_workq_t *DWC_WORKQ_ALLOC(char *name) -+{ -+ dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq)); -+ -+ if (!wq) { -+ return NULL; -+ } -+ -+ wq->wq = create_singlethread_workqueue(name); -+ if (!wq->wq) { -+ goto no_wq; -+ } -+ -+ wq->pending = 0; -+ -+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK)) -+ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(wq->lock); -+#else -+ wq->lock = DWC_SPINLOCK_ALLOC(); -+#endif -+ if (!wq->lock) { -+ goto no_lock; -+ } -+ -+ wq->waitq = DWC_WAITQ_ALLOC(); -+ if (!wq->waitq) { -+ goto no_waitq; -+ } -+ -+#ifdef DEBUG -+ DWC_CIRCLEQ_INIT(&wq->entries); -+#endif -+ return wq; -+ -+ no_waitq: -+ DWC_SPINLOCK_FREE(wq->lock); -+ no_lock: -+ destroy_workqueue(wq->wq); -+ no_wq: -+ DWC_FREE(wq); -+ -+ return NULL; -+} -+ -+void DWC_WORKQ_FREE(dwc_workq_t *wq) -+{ -+#ifdef DEBUG -+ if (wq->pending != 0) { -+ struct work_container *wc; -+ DWC_ERROR("Destroying work queue with pending work"); -+ DWC_CIRCLEQ_FOREACH(wc, &wq->entries, entry) { -+ DWC_ERROR("Work %s still pending", wc->name); -+ } -+ } -+#endif -+ destroy_workqueue(wq->wq); -+ DWC_SPINLOCK_FREE(wq->lock); -+ DWC_WAITQ_FREE(wq->waitq); -+ DWC_FREE(wq); -+} -+ -+void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data, -+ char *format, ...) -+{ -+ dwc_irqflags_t flags; -+ work_container_t *container; -+ static char name[128]; -+ va_list args; -+ -+ va_start(args, format); -+ DWC_VSNPRINTF(name, 128, format, args); -+ va_end(args); -+ -+ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); -+ wq->pending++; -+ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); -+ DWC_WAITQ_TRIGGER(wq->waitq); -+ -+ container = DWC_ALLOC_ATOMIC(sizeof(*container)); -+ if (!container) { -+ DWC_ERROR("Cannot allocate memory for container\n"); -+ return; -+ } -+ -+ container->name = DWC_STRDUP(name); -+ if (!container->name) { -+ DWC_ERROR("Cannot allocate memory for container->name\n"); -+ DWC_FREE(container); -+ return; -+ } -+ -+ container->cb = cb; -+ container->data = data; -+ container->wq = wq; -+ DWC_DEBUGC("Queueing work: %s, container=%p", container->name, container); -+ INIT_WORK(&container->work.work, do_work); -+ -+#ifdef DEBUG -+ DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry); -+#endif -+ queue_work(wq->wq, &container->work.work); -+} -+ -+void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb, -+ void *data, uint32_t time, char *format, ...) -+{ -+ dwc_irqflags_t flags; -+ work_container_t *container; -+ static char name[128]; -+ va_list args; -+ -+ va_start(args, format); -+ DWC_VSNPRINTF(name, 128, format, args); -+ va_end(args); -+ -+ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); -+ wq->pending++; -+ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); -+ DWC_WAITQ_TRIGGER(wq->waitq); -+ -+ container = DWC_ALLOC_ATOMIC(sizeof(*container)); -+ if (!container) { -+ DWC_ERROR("Cannot allocate memory for container\n"); -+ return; -+ } -+ -+ container->name = DWC_STRDUP(name); -+ if (!container->name) { -+ DWC_ERROR("Cannot allocate memory for container->name\n"); -+ DWC_FREE(container); -+ return; -+ } -+ -+ container->cb = cb; -+ container->data = data; -+ container->wq = wq; -+ DWC_DEBUGC("Queueing work: %s, container=%p", container->name, container); -+ INIT_DELAYED_WORK(&container->work, do_work); -+ -+#ifdef DEBUG -+ DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry); -+#endif -+ queue_delayed_work(wq->wq, &container->work, msecs_to_jiffies(time)); -+} -+ -+int DWC_WORKQ_PENDING(dwc_workq_t *wq) -+{ -+ return wq->pending; -+} -+ -+ -+#ifdef DWC_LIBMODULE -+ -+#ifdef DWC_CCLIB -+/* CC */ -+EXPORT_SYMBOL(dwc_cc_if_alloc); -+EXPORT_SYMBOL(dwc_cc_if_free); -+EXPORT_SYMBOL(dwc_cc_clear); -+EXPORT_SYMBOL(dwc_cc_add); -+EXPORT_SYMBOL(dwc_cc_remove); -+EXPORT_SYMBOL(dwc_cc_change); -+EXPORT_SYMBOL(dwc_cc_data_for_save); -+EXPORT_SYMBOL(dwc_cc_restore_from_data); -+EXPORT_SYMBOL(dwc_cc_match_chid); -+EXPORT_SYMBOL(dwc_cc_match_cdid); -+EXPORT_SYMBOL(dwc_cc_ck); -+EXPORT_SYMBOL(dwc_cc_chid); -+EXPORT_SYMBOL(dwc_cc_cdid); -+EXPORT_SYMBOL(dwc_cc_name); -+#endif /* DWC_CCLIB */ -+ -+#ifdef DWC_CRYPTOLIB -+# ifndef CONFIG_MACH_IPMATE -+/* Modpow */ -+EXPORT_SYMBOL(dwc_modpow); -+ -+/* DH */ -+EXPORT_SYMBOL(dwc_dh_modpow); -+EXPORT_SYMBOL(dwc_dh_derive_keys); -+EXPORT_SYMBOL(dwc_dh_pk); -+# endif /* CONFIG_MACH_IPMATE */ -+ -+/* Crypto */ -+EXPORT_SYMBOL(dwc_wusb_aes_encrypt); -+EXPORT_SYMBOL(dwc_wusb_cmf); -+EXPORT_SYMBOL(dwc_wusb_prf); -+EXPORT_SYMBOL(dwc_wusb_fill_ccm_nonce); -+EXPORT_SYMBOL(dwc_wusb_gen_nonce); -+EXPORT_SYMBOL(dwc_wusb_gen_key); -+EXPORT_SYMBOL(dwc_wusb_gen_mic); -+#endif /* DWC_CRYPTOLIB */ -+ -+/* Notification */ -+#ifdef DWC_NOTIFYLIB -+EXPORT_SYMBOL(dwc_alloc_notification_manager); -+EXPORT_SYMBOL(dwc_free_notification_manager); -+EXPORT_SYMBOL(dwc_register_notifier); -+EXPORT_SYMBOL(dwc_unregister_notifier); -+EXPORT_SYMBOL(dwc_add_observer); -+EXPORT_SYMBOL(dwc_remove_observer); -+EXPORT_SYMBOL(dwc_notify); -+#endif -+ -+/* Memory Debugging Routines */ -+#ifdef DWC_DEBUG_MEMORY -+EXPORT_SYMBOL(dwc_alloc_debug); -+EXPORT_SYMBOL(dwc_alloc_atomic_debug); -+EXPORT_SYMBOL(dwc_free_debug); -+EXPORT_SYMBOL(dwc_dma_alloc_debug); -+EXPORT_SYMBOL(dwc_dma_free_debug); -+#endif -+ -+EXPORT_SYMBOL(DWC_MEMSET); -+EXPORT_SYMBOL(DWC_MEMCPY); -+EXPORT_SYMBOL(DWC_MEMMOVE); -+EXPORT_SYMBOL(DWC_MEMCMP); -+EXPORT_SYMBOL(DWC_STRNCMP); -+EXPORT_SYMBOL(DWC_STRCMP); -+EXPORT_SYMBOL(DWC_STRLEN); -+EXPORT_SYMBOL(DWC_STRCPY); -+EXPORT_SYMBOL(DWC_STRDUP); -+EXPORT_SYMBOL(DWC_ATOI); -+EXPORT_SYMBOL(DWC_ATOUI); -+ -+#ifdef DWC_UTFLIB -+EXPORT_SYMBOL(DWC_UTF8_TO_UTF16LE); -+#endif /* DWC_UTFLIB */ -+ -+EXPORT_SYMBOL(DWC_IN_IRQ); -+EXPORT_SYMBOL(DWC_IN_BH); -+EXPORT_SYMBOL(DWC_VPRINTF); -+EXPORT_SYMBOL(DWC_VSNPRINTF); -+EXPORT_SYMBOL(DWC_PRINTF); -+EXPORT_SYMBOL(DWC_SPRINTF); -+EXPORT_SYMBOL(DWC_SNPRINTF); -+EXPORT_SYMBOL(__DWC_WARN); -+EXPORT_SYMBOL(__DWC_ERROR); -+EXPORT_SYMBOL(DWC_EXCEPTION); -+ -+#ifdef DEBUG -+EXPORT_SYMBOL(__DWC_DEBUG); -+#endif -+ -+EXPORT_SYMBOL(__DWC_DMA_ALLOC); -+EXPORT_SYMBOL(__DWC_DMA_ALLOC_ATOMIC); -+EXPORT_SYMBOL(__DWC_DMA_FREE); -+EXPORT_SYMBOL(__DWC_ALLOC); -+EXPORT_SYMBOL(__DWC_ALLOC_ATOMIC); -+EXPORT_SYMBOL(__DWC_FREE); -+ -+#ifdef DWC_CRYPTOLIB -+EXPORT_SYMBOL(DWC_RANDOM_BYTES); -+EXPORT_SYMBOL(DWC_AES_CBC); -+EXPORT_SYMBOL(DWC_SHA256); -+EXPORT_SYMBOL(DWC_HMAC_SHA256); -+#endif -+ -+EXPORT_SYMBOL(DWC_CPU_TO_LE32); -+EXPORT_SYMBOL(DWC_CPU_TO_BE32); -+EXPORT_SYMBOL(DWC_LE32_TO_CPU); -+EXPORT_SYMBOL(DWC_BE32_TO_CPU); -+EXPORT_SYMBOL(DWC_CPU_TO_LE16); -+EXPORT_SYMBOL(DWC_CPU_TO_BE16); -+EXPORT_SYMBOL(DWC_LE16_TO_CPU); -+EXPORT_SYMBOL(DWC_BE16_TO_CPU); -+EXPORT_SYMBOL(DWC_READ_REG32); -+EXPORT_SYMBOL(DWC_WRITE_REG32); -+EXPORT_SYMBOL(DWC_MODIFY_REG32); -+ -+#if 0 -+EXPORT_SYMBOL(DWC_READ_REG64); -+EXPORT_SYMBOL(DWC_WRITE_REG64); -+EXPORT_SYMBOL(DWC_MODIFY_REG64); -+#endif -+ -+EXPORT_SYMBOL(DWC_SPINLOCK_ALLOC); -+EXPORT_SYMBOL(DWC_SPINLOCK_FREE); -+EXPORT_SYMBOL(DWC_SPINLOCK); -+EXPORT_SYMBOL(DWC_SPINUNLOCK); -+EXPORT_SYMBOL(DWC_SPINLOCK_IRQSAVE); -+EXPORT_SYMBOL(DWC_SPINUNLOCK_IRQRESTORE); -+EXPORT_SYMBOL(DWC_MUTEX_ALLOC); -+ -+#if (!defined(DWC_LINUX) || !defined(CONFIG_DEBUG_MUTEXES)) -+EXPORT_SYMBOL(DWC_MUTEX_FREE); -+#endif -+ -+EXPORT_SYMBOL(DWC_MUTEX_LOCK); -+EXPORT_SYMBOL(DWC_MUTEX_TRYLOCK); -+EXPORT_SYMBOL(DWC_MUTEX_UNLOCK); -+EXPORT_SYMBOL(DWC_UDELAY); -+EXPORT_SYMBOL(DWC_MDELAY); -+EXPORT_SYMBOL(DWC_MSLEEP); -+EXPORT_SYMBOL(DWC_TIME); -+EXPORT_SYMBOL(DWC_TIMER_ALLOC); -+EXPORT_SYMBOL(DWC_TIMER_FREE); -+EXPORT_SYMBOL(DWC_TIMER_SCHEDULE); -+EXPORT_SYMBOL(DWC_TIMER_CANCEL); -+EXPORT_SYMBOL(DWC_WAITQ_ALLOC); -+EXPORT_SYMBOL(DWC_WAITQ_FREE); -+EXPORT_SYMBOL(DWC_WAITQ_WAIT); -+EXPORT_SYMBOL(DWC_WAITQ_WAIT_TIMEOUT); -+EXPORT_SYMBOL(DWC_WAITQ_TRIGGER); -+EXPORT_SYMBOL(DWC_WAITQ_ABORT); -+EXPORT_SYMBOL(DWC_THREAD_RUN); -+EXPORT_SYMBOL(DWC_THREAD_STOP); -+EXPORT_SYMBOL(DWC_THREAD_SHOULD_STOP); -+EXPORT_SYMBOL(DWC_TASK_ALLOC); -+EXPORT_SYMBOL(DWC_TASK_FREE); -+EXPORT_SYMBOL(DWC_TASK_SCHEDULE); -+EXPORT_SYMBOL(DWC_WORKQ_WAIT_WORK_DONE); -+EXPORT_SYMBOL(DWC_WORKQ_ALLOC); -+EXPORT_SYMBOL(DWC_WORKQ_FREE); -+EXPORT_SYMBOL(DWC_WORKQ_SCHEDULE); -+EXPORT_SYMBOL(DWC_WORKQ_SCHEDULE_DELAYED); -+EXPORT_SYMBOL(DWC_WORKQ_PENDING); -+ -+static int dwc_common_port_init_module(void) -+{ -+ int result = 0; -+ -+ printk(KERN_DEBUG "Module dwc_common_port init\n" ); -+ -+#ifdef DWC_DEBUG_MEMORY -+ result = dwc_memory_debug_start(NULL); -+ if (result) { -+ printk(KERN_ERR -+ "dwc_memory_debug_start() failed with error %d\n", -+ result); -+ return result; -+ } -+#endif -+ -+#ifdef DWC_NOTIFYLIB -+ result = dwc_alloc_notification_manager(NULL, NULL); -+ if (result) { -+ printk(KERN_ERR -+ "dwc_alloc_notification_manager() failed with error %d\n", -+ result); -+ return result; -+ } -+#endif -+ return result; -+} -+ -+static void dwc_common_port_exit_module(void) -+{ -+ printk(KERN_DEBUG "Module dwc_common_port exit\n" ); -+ -+#ifdef DWC_NOTIFYLIB -+ dwc_free_notification_manager(); -+#endif -+ -+#ifdef DWC_DEBUG_MEMORY -+ dwc_memory_debug_stop(); -+#endif -+} -+ -+module_init(dwc_common_port_init_module); -+module_exit(dwc_common_port_exit_module); -+ -+MODULE_DESCRIPTION("DWC Common Library - Portable version"); -+MODULE_AUTHOR("Synopsys Inc."); -+MODULE_LICENSE ("GPL"); -+ -+#endif /* DWC_LIBMODULE */ -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_common_nbsd.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_common_nbsd.c ---- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_common_nbsd.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_common_nbsd.c 2015-11-29 09:42:39.915098960 +0100 -@@ -0,0 +1,1275 @@ -+#include "dwc_os.h" -+#include "dwc_list.h" -+ -+#ifdef DWC_CCLIB -+# include "dwc_cc.h" -+#endif -+ -+#ifdef DWC_CRYPTOLIB -+# include "dwc_modpow.h" -+# include "dwc_dh.h" -+# include "dwc_crypto.h" -+#endif -+ -+#ifdef DWC_NOTIFYLIB -+# include "dwc_notifier.h" -+#endif -+ -+/* OS-Level Implementations */ -+ -+/* This is the NetBSD 4.0.1 kernel implementation of the DWC platform library. */ -+ -+ -+/* MISC */ -+ -+void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size) -+{ -+ return memset(dest, byte, size); -+} -+ -+void *DWC_MEMCPY(void *dest, void const *src, uint32_t size) -+{ -+ return memcpy(dest, src, size); -+} -+ -+void *DWC_MEMMOVE(void *dest, void *src, uint32_t size) -+{ -+ bcopy(src, dest, size); -+ return dest; -+} -+ -+int DWC_MEMCMP(void *m1, void *m2, uint32_t size) -+{ -+ return memcmp(m1, m2, size); -+} -+ -+int DWC_STRNCMP(void *s1, void *s2, uint32_t size) -+{ -+ return strncmp(s1, s2, size); -+} -+ -+int DWC_STRCMP(void *s1, void *s2) -+{ -+ return strcmp(s1, s2); -+} -+ -+int DWC_STRLEN(char const *str) -+{ -+ return strlen(str); -+} -+ -+char *DWC_STRCPY(char *to, char const *from) -+{ -+ return strcpy(to, from); -+} -+ -+char *DWC_STRDUP(char const *str) -+{ -+ int len = DWC_STRLEN(str) + 1; -+ char *new = DWC_ALLOC_ATOMIC(len); -+ -+ if (!new) { -+ return NULL; -+ } -+ -+ DWC_MEMCPY(new, str, len); -+ return new; -+} -+ -+int DWC_ATOI(char *str, int32_t *value) -+{ -+ char *end = NULL; -+ -+ /* NetBSD doesn't have 'strtol' in the kernel, but 'strtoul' -+ * should be equivalent on 2's complement machines -+ */ -+ *value = strtoul(str, &end, 0); -+ if (*end == '\0') { -+ return 0; -+ } -+ -+ return -1; -+} -+ -+int DWC_ATOUI(char *str, uint32_t *value) -+{ -+ char *end = NULL; -+ -+ *value = strtoul(str, &end, 0); -+ if (*end == '\0') { -+ return 0; -+ } -+ -+ return -1; -+} -+ -+ -+#ifdef DWC_UTFLIB -+/* From usbstring.c */ -+ -+int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len) -+{ -+ int count = 0; -+ u8 c; -+ u16 uchar; -+ -+ /* this insists on correct encodings, though not minimal ones. -+ * BUT it currently rejects legit 4-byte UTF-8 code points, -+ * which need surrogate pairs. (Unicode 3.1 can use them.) -+ */ -+ while (len != 0 && (c = (u8) *s++) != 0) { -+ if (unlikely(c & 0x80)) { -+ // 2-byte sequence: -+ // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx -+ if ((c & 0xe0) == 0xc0) { -+ uchar = (c & 0x1f) << 6; -+ -+ c = (u8) *s++; -+ if ((c & 0xc0) != 0xc0) -+ goto fail; -+ c &= 0x3f; -+ uchar |= c; -+ -+ // 3-byte sequence (most CJKV characters): -+ // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx -+ } else if ((c & 0xf0) == 0xe0) { -+ uchar = (c & 0x0f) << 12; -+ -+ c = (u8) *s++; -+ if ((c & 0xc0) != 0xc0) -+ goto fail; -+ c &= 0x3f; -+ uchar |= c << 6; -+ -+ c = (u8) *s++; -+ if ((c & 0xc0) != 0xc0) -+ goto fail; -+ c &= 0x3f; -+ uchar |= c; -+ -+ /* no bogus surrogates */ -+ if (0xd800 <= uchar && uchar <= 0xdfff) -+ goto fail; -+ -+ // 4-byte sequence (surrogate pairs, currently rare): -+ // 11101110wwwwzzzzyy + 110111yyyyxxxxxx -+ // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx -+ // (uuuuu = wwww + 1) -+ // FIXME accept the surrogate code points (only) -+ } else -+ goto fail; -+ } else -+ uchar = c; -+ put_unaligned (cpu_to_le16 (uchar), cp++); -+ count++; -+ len--; -+ } -+ return count; -+fail: -+ return -1; -+} -+ -+#endif /* DWC_UTFLIB */ -+ -+ -+/* dwc_debug.h */ -+ -+dwc_bool_t DWC_IN_IRQ(void) -+{ -+// return in_irq(); -+ return 0; -+} -+ -+dwc_bool_t DWC_IN_BH(void) -+{ -+// return in_softirq(); -+ return 0; -+} -+ -+void DWC_VPRINTF(char *format, va_list args) -+{ -+ vprintf(format, args); -+} -+ -+int DWC_VSNPRINTF(char *str, int size, char *format, va_list args) -+{ -+ return vsnprintf(str, size, format, args); -+} -+ -+void DWC_PRINTF(char *format, ...) -+{ -+ va_list args; -+ -+ va_start(args, format); -+ DWC_VPRINTF(format, args); -+ va_end(args); -+} -+ -+int DWC_SPRINTF(char *buffer, char *format, ...) -+{ -+ int retval; -+ va_list args; -+ -+ va_start(args, format); -+ retval = vsprintf(buffer, format, args); -+ va_end(args); -+ return retval; -+} -+ -+int DWC_SNPRINTF(char *buffer, int size, char *format, ...) -+{ -+ int retval; -+ va_list args; -+ -+ va_start(args, format); -+ retval = vsnprintf(buffer, size, format, args); -+ va_end(args); -+ return retval; -+} -+ -+void __DWC_WARN(char *format, ...) -+{ -+ va_list args; -+ -+ va_start(args, format); -+ DWC_VPRINTF(format, args); -+ va_end(args); -+} -+ -+void __DWC_ERROR(char *format, ...) -+{ -+ va_list args; -+ -+ va_start(args, format); -+ DWC_VPRINTF(format, args); -+ va_end(args); -+} -+ -+void DWC_EXCEPTION(char *format, ...) -+{ -+ va_list args; -+ -+ va_start(args, format); -+ DWC_VPRINTF(format, args); -+ va_end(args); -+// BUG_ON(1); ??? -+} -+ -+#ifdef DEBUG -+void __DWC_DEBUG(char *format, ...) -+{ -+ va_list args; -+ -+ va_start(args, format); -+ DWC_VPRINTF(format, args); -+ va_end(args); -+} -+#endif -+ -+ -+/* dwc_mem.h */ -+ -+#if 0 -+dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size, -+ uint32_t align, -+ uint32_t alloc) -+{ -+ struct dma_pool *pool = dma_pool_create("Pool", NULL, -+ size, align, alloc); -+ return (dwc_pool_t *)pool; -+} -+ -+void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool) -+{ -+ dma_pool_destroy((struct dma_pool *)pool); -+} -+ -+void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr) -+{ -+// return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr); -+ return dma_pool_alloc((struct dma_pool *)pool, M_WAITOK, dma_addr); -+} -+ -+void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr) -+{ -+ void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr); -+ memset(..); -+} -+ -+void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr) -+{ -+ dma_pool_free(pool, vaddr, daddr); -+} -+#endif -+ -+void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr) -+{ -+ dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx; -+ int error; -+ -+ error = bus_dmamem_alloc(dma->dma_tag, size, 1, size, dma->segs, -+ sizeof(dma->segs) / sizeof(dma->segs[0]), -+ &dma->nsegs, BUS_DMA_NOWAIT); -+ if (error) { -+ printf("%s: bus_dmamem_alloc(%ju) failed: %d\n", __func__, -+ (uintmax_t)size, error); -+ goto fail_0; -+ } -+ -+ error = bus_dmamem_map(dma->dma_tag, dma->segs, dma->nsegs, size, -+ (caddr_t *)&dma->dma_vaddr, -+ BUS_DMA_NOWAIT | BUS_DMA_COHERENT); -+ if (error) { -+ printf("%s: bus_dmamem_map failed: %d\n", __func__, error); -+ goto fail_1; -+ } -+ -+ error = bus_dmamap_create(dma->dma_tag, size, 1, size, 0, -+ BUS_DMA_NOWAIT, &dma->dma_map); -+ if (error) { -+ printf("%s: bus_dmamap_create failed: %d\n", __func__, error); -+ goto fail_2; -+ } -+ -+ error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, -+ size, NULL, BUS_DMA_NOWAIT); -+ if (error) { -+ printf("%s: bus_dmamap_load failed: %d\n", __func__, error); -+ goto fail_3; -+ } -+ -+ dma->dma_paddr = (bus_addr_t)dma->segs[0].ds_addr; -+ *dma_addr = dma->dma_paddr; -+ return dma->dma_vaddr; -+ -+fail_3: -+ bus_dmamap_destroy(dma->dma_tag, dma->dma_map); -+fail_2: -+ bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size); -+fail_1: -+ bus_dmamem_free(dma->dma_tag, dma->segs, dma->nsegs); -+fail_0: -+ dma->dma_map = NULL; -+ dma->dma_vaddr = NULL; -+ dma->nsegs = 0; -+ -+ return NULL; -+} -+ -+void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr) -+{ -+ dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx; -+ -+ if (dma->dma_map != NULL) { -+ bus_dmamap_sync(dma->dma_tag, dma->dma_map, 0, size, -+ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); -+ bus_dmamap_unload(dma->dma_tag, dma->dma_map); -+ bus_dmamap_destroy(dma->dma_tag, dma->dma_map); -+ bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size); -+ bus_dmamem_free(dma->dma_tag, dma->segs, dma->nsegs); -+ dma->dma_paddr = 0; -+ dma->dma_map = NULL; -+ dma->dma_vaddr = NULL; -+ dma->nsegs = 0; -+ } -+} -+ -+void *__DWC_ALLOC(void *mem_ctx, uint32_t size) -+{ -+ return malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); -+} -+ -+void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size) -+{ -+ return malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO); -+} -+ -+void __DWC_FREE(void *mem_ctx, void *addr) -+{ -+ free(addr, M_DEVBUF); -+} -+ -+ -+#ifdef DWC_CRYPTOLIB -+/* dwc_crypto.h */ -+ -+void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length) -+{ -+ get_random_bytes(buffer, length); -+} -+ -+int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out) -+{ -+ struct crypto_blkcipher *tfm; -+ struct blkcipher_desc desc; -+ struct scatterlist sgd; -+ struct scatterlist sgs; -+ -+ tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC); -+ if (tfm == NULL) { -+ printk("failed to load transform for aes CBC\n"); -+ return -1; -+ } -+ -+ crypto_blkcipher_setkey(tfm, key, keylen); -+ crypto_blkcipher_set_iv(tfm, iv, 16); -+ -+ sg_init_one(&sgd, out, messagelen); -+ sg_init_one(&sgs, message, messagelen); -+ -+ desc.tfm = tfm; -+ desc.flags = 0; -+ -+ if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) { -+ crypto_free_blkcipher(tfm); -+ DWC_ERROR("AES CBC encryption failed"); -+ return -1; -+ } -+ -+ crypto_free_blkcipher(tfm); -+ return 0; -+} -+ -+int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out) -+{ -+ struct crypto_hash *tfm; -+ struct hash_desc desc; -+ struct scatterlist sg; -+ -+ tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC); -+ if (IS_ERR(tfm)) { -+ DWC_ERROR("Failed to load transform for sha256: %ld", PTR_ERR(tfm)); -+ return 0; -+ } -+ desc.tfm = tfm; -+ desc.flags = 0; -+ -+ sg_init_one(&sg, message, len); -+ crypto_hash_digest(&desc, &sg, len, out); -+ crypto_free_hash(tfm); -+ -+ return 1; -+} -+ -+int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen, -+ uint8_t *key, uint32_t keylen, uint8_t *out) -+{ -+ struct crypto_hash *tfm; -+ struct hash_desc desc; -+ struct scatterlist sg; -+ -+ tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC); -+ if (IS_ERR(tfm)) { -+ DWC_ERROR("Failed to load transform for hmac(sha256): %ld", PTR_ERR(tfm)); -+ return 0; -+ } -+ desc.tfm = tfm; -+ desc.flags = 0; -+ -+ sg_init_one(&sg, message, messagelen); -+ crypto_hash_setkey(tfm, key, keylen); -+ crypto_hash_digest(&desc, &sg, messagelen, out); -+ crypto_free_hash(tfm); -+ -+ return 1; -+} -+ -+#endif /* DWC_CRYPTOLIB */ -+ -+ -+/* Byte Ordering Conversions */ -+ -+uint32_t DWC_CPU_TO_LE32(uint32_t *p) -+{ -+#ifdef __LITTLE_ENDIAN -+ return *p; -+#else -+ uint8_t *u_p = (uint8_t *)p; -+ -+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); -+#endif -+} -+ -+uint32_t DWC_CPU_TO_BE32(uint32_t *p) -+{ -+#ifdef __BIG_ENDIAN -+ return *p; -+#else -+ uint8_t *u_p = (uint8_t *)p; -+ -+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); -+#endif -+} -+ -+uint32_t DWC_LE32_TO_CPU(uint32_t *p) -+{ -+#ifdef __LITTLE_ENDIAN -+ return *p; -+#else -+ uint8_t *u_p = (uint8_t *)p; -+ -+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); -+#endif -+} -+ -+uint32_t DWC_BE32_TO_CPU(uint32_t *p) -+{ -+#ifdef __BIG_ENDIAN -+ return *p; -+#else -+ uint8_t *u_p = (uint8_t *)p; -+ -+ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); -+#endif -+} -+ -+uint16_t DWC_CPU_TO_LE16(uint16_t *p) -+{ -+#ifdef __LITTLE_ENDIAN -+ return *p; -+#else -+ uint8_t *u_p = (uint8_t *)p; -+ return (u_p[1] | (u_p[0] << 8)); -+#endif -+} -+ -+uint16_t DWC_CPU_TO_BE16(uint16_t *p) -+{ -+#ifdef __BIG_ENDIAN -+ return *p; -+#else -+ uint8_t *u_p = (uint8_t *)p; -+ return (u_p[1] | (u_p[0] << 8)); -+#endif -+} -+ -+uint16_t DWC_LE16_TO_CPU(uint16_t *p) -+{ -+#ifdef __LITTLE_ENDIAN -+ return *p; -+#else -+ uint8_t *u_p = (uint8_t *)p; -+ return (u_p[1] | (u_p[0] << 8)); -+#endif -+} -+ -+uint16_t DWC_BE16_TO_CPU(uint16_t *p) -+{ -+#ifdef __BIG_ENDIAN -+ return *p; -+#else -+ uint8_t *u_p = (uint8_t *)p; -+ return (u_p[1] | (u_p[0] << 8)); -+#endif -+} -+ -+ -+/* Registers */ -+ -+uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg) -+{ -+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; -+ bus_size_t ior = (bus_size_t)reg; -+ -+ return bus_space_read_4(io->iot, io->ioh, ior); -+} -+ -+#if 0 -+uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg) -+{ -+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; -+ bus_size_t ior = (bus_size_t)reg; -+ -+ return bus_space_read_8(io->iot, io->ioh, ior); -+} -+#endif -+ -+void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value) -+{ -+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; -+ bus_size_t ior = (bus_size_t)reg; -+ -+ bus_space_write_4(io->iot, io->ioh, ior, value); -+} -+ -+#if 0 -+void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value) -+{ -+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; -+ bus_size_t ior = (bus_size_t)reg; -+ -+ bus_space_write_8(io->iot, io->ioh, ior, value); -+} -+#endif -+ -+void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask, -+ uint32_t set_mask) -+{ -+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; -+ bus_size_t ior = (bus_size_t)reg; -+ -+ bus_space_write_4(io->iot, io->ioh, ior, -+ (bus_space_read_4(io->iot, io->ioh, ior) & -+ ~clear_mask) | set_mask); -+} -+ -+#if 0 -+void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask, -+ uint64_t set_mask) -+{ -+ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; -+ bus_size_t ior = (bus_size_t)reg; -+ -+ bus_space_write_8(io->iot, io->ioh, ior, -+ (bus_space_read_8(io->iot, io->ioh, ior) & -+ ~clear_mask) | set_mask); -+} -+#endif -+ -+ -+/* Locking */ -+ -+dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void) -+{ -+ struct simplelock *sl = DWC_ALLOC(sizeof(*sl)); -+ -+ if (!sl) { -+ DWC_ERROR("Cannot allocate memory for spinlock"); -+ return NULL; -+ } -+ -+ simple_lock_init(sl); -+ return (dwc_spinlock_t *)sl; -+} -+ -+void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock) -+{ -+ struct simplelock *sl = (struct simplelock *)lock; -+ -+ DWC_FREE(sl); -+} -+ -+void DWC_SPINLOCK(dwc_spinlock_t *lock) -+{ -+ simple_lock((struct simplelock *)lock); -+} -+ -+void DWC_SPINUNLOCK(dwc_spinlock_t *lock) -+{ -+ simple_unlock((struct simplelock *)lock); -+} -+ -+void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags) -+{ -+ simple_lock((struct simplelock *)lock); -+ *flags = splbio(); -+} -+ -+void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags) -+{ -+ splx(flags); -+ simple_unlock((struct simplelock *)lock); -+} -+ -+dwc_mutex_t *DWC_MUTEX_ALLOC(void) -+{ -+ dwc_mutex_t *mutex = DWC_ALLOC(sizeof(struct lock)); -+ -+ if (!mutex) { -+ DWC_ERROR("Cannot allocate memory for mutex"); -+ return NULL; -+ } -+ -+ lockinit((struct lock *)mutex, 0, "dw3mtx", 0, 0); -+ return mutex; -+} -+ -+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)) -+#else -+void DWC_MUTEX_FREE(dwc_mutex_t *mutex) -+{ -+ DWC_FREE(mutex); -+} -+#endif -+ -+void DWC_MUTEX_LOCK(dwc_mutex_t *mutex) -+{ -+ lockmgr((struct lock *)mutex, LK_EXCLUSIVE, NULL); -+} -+ -+int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex) -+{ -+ int status; -+ -+ status = lockmgr((struct lock *)mutex, LK_EXCLUSIVE | LK_NOWAIT, NULL); -+ return status == 0; -+} -+ -+void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex) -+{ -+ lockmgr((struct lock *)mutex, LK_RELEASE, NULL); -+} -+ -+ -+/* Timing */ -+ -+void DWC_UDELAY(uint32_t usecs) -+{ -+ DELAY(usecs); -+} -+ -+void DWC_MDELAY(uint32_t msecs) -+{ -+ do { -+ DELAY(1000); -+ } while (--msecs); -+} -+ -+void DWC_MSLEEP(uint32_t msecs) -+{ -+ struct timeval tv; -+ -+ tv.tv_sec = msecs / 1000; -+ tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000; -+ tsleep(&tv, 0, "dw3slp", tvtohz(&tv)); -+} -+ -+uint32_t DWC_TIME(void) -+{ -+ struct timeval tv; -+ -+ microuptime(&tv); // or getmicrouptime? (less precise, but faster) -+ return tv.tv_sec * 1000 + tv.tv_usec / 1000; -+} -+ -+ -+/* Timers */ -+ -+struct dwc_timer { -+ struct callout t; -+ char *name; -+ dwc_spinlock_t *lock; -+ dwc_timer_callback_t cb; -+ void *data; -+}; -+ -+dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data) -+{ -+ dwc_timer_t *t = DWC_ALLOC(sizeof(*t)); -+ -+ if (!t) { -+ DWC_ERROR("Cannot allocate memory for timer"); -+ return NULL; -+ } -+ -+ callout_init(&t->t); -+ -+ t->name = DWC_STRDUP(name); -+ if (!t->name) { -+ DWC_ERROR("Cannot allocate memory for timer->name"); -+ goto no_name; -+ } -+ -+ t->lock = DWC_SPINLOCK_ALLOC(); -+ if (!t->lock) { -+ DWC_ERROR("Cannot allocate memory for timer->lock"); -+ goto no_lock; -+ } -+ -+ t->cb = cb; -+ t->data = data; -+ -+ return t; -+ -+ no_lock: -+ DWC_FREE(t->name); -+ no_name: -+ DWC_FREE(t); -+ -+ return NULL; -+} -+ -+void DWC_TIMER_FREE(dwc_timer_t *timer) -+{ -+ callout_stop(&timer->t); -+ DWC_SPINLOCK_FREE(timer->lock); -+ DWC_FREE(timer->name); -+ DWC_FREE(timer); -+} -+ -+void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time) -+{ -+ struct timeval tv; -+ -+ tv.tv_sec = time / 1000; -+ tv.tv_usec = (time - tv.tv_sec * 1000) * 1000; -+ callout_reset(&timer->t, tvtohz(&tv), timer->cb, timer->data); -+} -+ -+void DWC_TIMER_CANCEL(dwc_timer_t *timer) -+{ -+ callout_stop(&timer->t); -+} -+ -+ -+/* Wait Queues */ -+ -+struct dwc_waitq { -+ struct simplelock lock; -+ int abort; -+}; -+ -+dwc_waitq_t *DWC_WAITQ_ALLOC(void) -+{ -+ dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq)); -+ -+ if (!wq) { -+ DWC_ERROR("Cannot allocate memory for waitqueue"); -+ return NULL; -+ } -+ -+ simple_lock_init(&wq->lock); -+ wq->abort = 0; -+ -+ return wq; -+} -+ -+void DWC_WAITQ_FREE(dwc_waitq_t *wq) -+{ -+ DWC_FREE(wq); -+} -+ -+int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data) -+{ -+ int ipl; -+ int result = 0; -+ -+ simple_lock(&wq->lock); -+ ipl = splbio(); -+ -+ /* Skip the sleep if already aborted or triggered */ -+ if (!wq->abort && !cond(data)) { -+ splx(ipl); -+ result = ltsleep(wq, PCATCH, "dw3wat", 0, &wq->lock); // infinite timeout -+ ipl = splbio(); -+ } -+ -+ if (result == 0) { // awoken -+ if (wq->abort) { -+ wq->abort = 0; -+ result = -DWC_E_ABORT; -+ } else { -+ result = 0; -+ } -+ -+ splx(ipl); -+ simple_unlock(&wq->lock); -+ } else { -+ wq->abort = 0; -+ splx(ipl); -+ simple_unlock(&wq->lock); -+ -+ if (result == ERESTART) { // signaled - restart -+ result = -DWC_E_RESTART; -+ } else { // signaled - must be EINTR -+ result = -DWC_E_ABORT; -+ } -+ } -+ -+ return result; -+} -+ -+int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, -+ void *data, int32_t msecs) -+{ -+ struct timeval tv, tv1, tv2; -+ int ipl; -+ int result = 0; -+ -+ tv.tv_sec = msecs / 1000; -+ tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000; -+ -+ simple_lock(&wq->lock); -+ ipl = splbio(); -+ -+ /* Skip the sleep if already aborted or triggered */ -+ if (!wq->abort && !cond(data)) { -+ splx(ipl); -+ getmicrouptime(&tv1); -+ result = ltsleep(wq, PCATCH, "dw3wto", tvtohz(&tv), &wq->lock); -+ getmicrouptime(&tv2); -+ ipl = splbio(); -+ } -+ -+ if (result == 0) { // awoken -+ if (wq->abort) { -+ wq->abort = 0; -+ splx(ipl); -+ simple_unlock(&wq->lock); -+ result = -DWC_E_ABORT; -+ } else { -+ splx(ipl); -+ simple_unlock(&wq->lock); -+ -+ tv2.tv_usec -= tv1.tv_usec; -+ if (tv2.tv_usec < 0) { -+ tv2.tv_usec += 1000000; -+ tv2.tv_sec--; -+ } -+ -+ tv2.tv_sec -= tv1.tv_sec; -+ result = tv2.tv_sec * 1000 + tv2.tv_usec / 1000; -+ result = msecs - result; -+ if (result <= 0) -+ result = 1; -+ } -+ } else { -+ wq->abort = 0; -+ splx(ipl); -+ simple_unlock(&wq->lock); -+ -+ if (result == ERESTART) { // signaled - restart -+ result = -DWC_E_RESTART; -+ -+ } else if (result == EINTR) { // signaled - interrupt -+ result = -DWC_E_ABORT; -+ -+ } else { // timed out -+ result = -DWC_E_TIMEOUT; -+ } -+ } -+ -+ return result; -+} -+ -+void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq) -+{ -+ wakeup(wq); -+} -+ -+void DWC_WAITQ_ABORT(dwc_waitq_t *wq) -+{ -+ int ipl; -+ -+ simple_lock(&wq->lock); -+ ipl = splbio(); -+ wq->abort = 1; -+ wakeup(wq); -+ splx(ipl); -+ simple_unlock(&wq->lock); -+} -+ -+ -+/* Threading */ -+ -+struct dwc_thread { -+ struct proc *proc; -+ int abort; -+}; -+ -+dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data) -+{ -+ int retval; -+ dwc_thread_t *thread = DWC_ALLOC(sizeof(*thread)); -+ -+ if (!thread) { -+ return NULL; -+ } -+ -+ thread->abort = 0; -+ retval = kthread_create1((void (*)(void *))func, data, &thread->proc, -+ "%s", name); -+ if (retval) { -+ DWC_FREE(thread); -+ return NULL; -+ } -+ -+ return thread; -+} -+ -+int DWC_THREAD_STOP(dwc_thread_t *thread) -+{ -+ int retval; -+ -+ thread->abort = 1; -+ retval = tsleep(&thread->abort, 0, "dw3stp", 60 * hz); -+ -+ if (retval == 0) { -+ /* DWC_THREAD_EXIT() will free the thread struct */ -+ return 0; -+ } -+ -+ /* NOTE: We leak the thread struct if thread doesn't die */ -+ -+ if (retval == EWOULDBLOCK) { -+ return -DWC_E_TIMEOUT; -+ } -+ -+ return -DWC_E_UNKNOWN; -+} -+ -+dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread) -+{ -+ return thread->abort; -+} -+ -+void DWC_THREAD_EXIT(dwc_thread_t *thread) -+{ -+ wakeup(&thread->abort); -+ DWC_FREE(thread); -+ kthread_exit(0); -+} -+ -+/* tasklets -+ - Runs in interrupt context (cannot sleep) -+ - Each tasklet runs on a single CPU -+ - Different tasklets can be running simultaneously on different CPUs -+ [ On NetBSD there is no corresponding mechanism, drivers don't have bottom- -+ halves. So we just call the callback directly from DWC_TASK_SCHEDULE() ] -+ */ -+struct dwc_tasklet { -+ dwc_tasklet_callback_t cb; -+ void *data; -+}; -+ -+static void tasklet_callback(void *data) -+{ -+ dwc_tasklet_t *task = (dwc_tasklet_t *)data; -+ -+ task->cb(task->data); -+} -+ -+dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data) -+{ -+ dwc_tasklet_t *task = DWC_ALLOC(sizeof(*task)); -+ -+ if (task) { -+ task->cb = cb; -+ task->data = data; -+ } else { -+ DWC_ERROR("Cannot allocate memory for tasklet"); -+ } -+ -+ return task; -+} -+ -+void DWC_TASK_FREE(dwc_tasklet_t *task) -+{ -+ DWC_FREE(task); -+} -+ -+void DWC_TASK_SCHEDULE(dwc_tasklet_t *task) -+{ -+ tasklet_callback(task); -+} -+ -+ -+/* workqueues -+ - Runs in process context (can sleep) -+ */ -+typedef struct work_container { -+ dwc_work_callback_t cb; -+ void *data; -+ dwc_workq_t *wq; -+ char *name; -+ int hz; -+ struct work task; -+} work_container_t; -+ -+struct dwc_workq { -+ struct workqueue *taskq; -+ dwc_spinlock_t *lock; -+ dwc_waitq_t *waitq; -+ int pending; -+ struct work_container *container; -+}; -+ -+static void do_work(struct work *task, void *data) -+{ -+ dwc_workq_t *wq = (dwc_workq_t *)data; -+ work_container_t *container = wq->container; -+ dwc_irqflags_t flags; -+ -+ if (container->hz) { -+ tsleep(container, 0, "dw3wrk", container->hz); -+ } -+ -+ container->cb(container->data); -+ DWC_DEBUG("Work done: %s, container=%p", container->name, container); -+ -+ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); -+ if (container->name) -+ DWC_FREE(container->name); -+ DWC_FREE(container); -+ wq->pending--; -+ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); -+ DWC_WAITQ_TRIGGER(wq->waitq); -+} -+ -+static int work_done(void *data) -+{ -+ dwc_workq_t *workq = (dwc_workq_t *)data; -+ -+ return workq->pending == 0; -+} -+ -+int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout) -+{ -+ return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout); -+} -+ -+dwc_workq_t *DWC_WORKQ_ALLOC(char *name) -+{ -+ int result; -+ dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq)); -+ -+ if (!wq) { -+ DWC_ERROR("Cannot allocate memory for workqueue"); -+ return NULL; -+ } -+ -+ result = workqueue_create(&wq->taskq, name, do_work, wq, 0 /*PWAIT*/, -+ IPL_BIO, 0); -+ if (result) { -+ DWC_ERROR("Cannot create workqueue"); -+ goto no_taskq; -+ } -+ -+ wq->pending = 0; -+ -+ wq->lock = DWC_SPINLOCK_ALLOC(); -+ if (!wq->lock) { -+ DWC_ERROR("Cannot allocate memory for spinlock"); -+ goto no_lock; -+ } -+ -+ wq->waitq = DWC_WAITQ_ALLOC(); -+ if (!wq->waitq) { -+ DWC_ERROR("Cannot allocate memory for waitqueue"); -+ goto no_waitq; -+ } -+ -+ return wq; -+ -+ no_waitq: -+ DWC_SPINLOCK_FREE(wq->lock); -+ no_lock: -+ workqueue_destroy(wq->taskq); -+ no_taskq: -+ DWC_FREE(wq); -+ -+ return NULL; -+} -+ -+void DWC_WORKQ_FREE(dwc_workq_t *wq) -+{ -+#ifdef DEBUG -+ dwc_irqflags_t flags; -+ -+ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); -+ -+ if (wq->pending != 0) { -+ struct work_container *container = wq->container; -+ -+ DWC_ERROR("Destroying work queue with pending work"); -+ -+ if (container && container->name) { -+ DWC_ERROR("Work %s still pending", container->name); -+ } -+ } -+ -+ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); -+#endif -+ DWC_WAITQ_FREE(wq->waitq); -+ DWC_SPINLOCK_FREE(wq->lock); -+ workqueue_destroy(wq->taskq); -+ DWC_FREE(wq); -+} -+ -+void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data, -+ char *format, ...) -+{ -+ dwc_irqflags_t flags; -+ work_container_t *container; -+ static char name[128]; -+ va_list args; -+ -+ va_start(args, format); -+ DWC_VSNPRINTF(name, 128, format, args); -+ va_end(args); -+ -+ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); -+ wq->pending++; -+ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); -+ DWC_WAITQ_TRIGGER(wq->waitq); -+ -+ container = DWC_ALLOC_ATOMIC(sizeof(*container)); -+ if (!container) { -+ DWC_ERROR("Cannot allocate memory for container"); -+ return; -+ } -+ -+ container->name = DWC_STRDUP(name); -+ if (!container->name) { -+ DWC_ERROR("Cannot allocate memory for container->name"); -+ DWC_FREE(container); -+ return; -+ } -+ -+ container->cb = cb; -+ container->data = data; -+ container->wq = wq; -+ container->hz = 0; -+ wq->container = container; -+ -+ DWC_DEBUG("Queueing work: %s, container=%p", container->name, container); -+ workqueue_enqueue(wq->taskq, &container->task); -+} -+ -+void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb, -+ void *data, uint32_t time, char *format, ...) -+{ -+ dwc_irqflags_t flags; -+ work_container_t *container; -+ static char name[128]; -+ struct timeval tv; -+ va_list args; -+ -+ va_start(args, format); -+ DWC_VSNPRINTF(name, 128, format, args); -+ va_end(args); -+ -+ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); -+ wq->pending++; -+ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); -+ DWC_WAITQ_TRIGGER(wq->waitq); -+ -+ container = DWC_ALLOC_ATOMIC(sizeof(*container)); -+ if (!container) { -+ DWC_ERROR("Cannot allocate memory for container"); -+ return; -+ } -+ -+ container->name = DWC_STRDUP(name); -+ if (!container->name) { -+ DWC_ERROR("Cannot allocate memory for container->name"); -+ DWC_FREE(container); -+ return; -+ } -+ -+ container->cb = cb; -+ container->data = data; -+ container->wq = wq; -+ tv.tv_sec = time / 1000; -+ tv.tv_usec = (time - tv.tv_sec * 1000) * 1000; -+ container->hz = tvtohz(&tv); -+ wq->container = container; -+ -+ DWC_DEBUG("Queueing work: %s, container=%p", container->name, container); -+ workqueue_enqueue(wq->taskq, &container->task); -+} -+ -+int DWC_WORKQ_PENDING(dwc_workq_t *wq) -+{ -+ return wq->pending; -+} -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_crypto.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_crypto.c ---- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_crypto.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_crypto.c 2015-11-29 09:42:39.915098960 +0100 -@@ -0,0 +1,308 @@ -+/* ========================================================================= -+ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_crypto.c $ -+ * $Revision: #5 $ -+ * $Date: 2010/09/28 $ -+ * $Change: 1596182 $ -+ * -+ * Synopsys Portability Library Software and documentation -+ * (hereinafter, "Software") is an Unsupported proprietary work of -+ * Synopsys, Inc. unless otherwise expressly agreed to in writing -+ * between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product -+ * under any End User Software License Agreement or Agreement for -+ * Licensed Product with Synopsys or any supplement thereto. You are -+ * permitted to use and redistribute this Software in source and binary -+ * forms, with or without modification, provided that redistributions -+ * of source code must retain this notice. You may not view, use, -+ * disclose, copy or distribute this file or any information contained -+ * herein except pursuant to this license grant from Synopsys. If you -+ * do not agree with this notice, including the disclaimer below, then -+ * you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" -+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL -+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY -+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================= */ -+ -+/** @file -+ * This file contains the WUSB cryptographic routines. -+ */ -+ -+#ifdef DWC_CRYPTOLIB -+ -+#include "dwc_crypto.h" -+#include "usb.h" -+ -+#ifdef DEBUG -+static inline void dump_bytes(char *name, uint8_t *bytes, int len) -+{ -+ int i; -+ DWC_PRINTF("%s: ", name); -+ for (i=0; idst == src, then the bytes will be encrypted -+ * in-place. -+ * -+ * @return 0 on success, negative error code on error. -+ */ -+int dwc_wusb_aes_encrypt(u8 *src, u8 *key, u8 *dst) -+{ -+ u8 block_t[16]; -+ DWC_MEMSET(block_t, 0, 16); -+ -+ return DWC_AES_CBC(src, 16, key, 16, block_t, dst); -+} -+ -+/** -+ * The CCM-MAC-FUNCTION described in section 6.5 of the WUSB spec. -+ * This function takes a data string and returns the encrypted CBC -+ * Counter-mode MIC. -+ * -+ * @param key The 128-bit symmetric key. -+ * @param nonce The CCM nonce. -+ * @param label The unique 14-byte ASCII text label. -+ * @param bytes The byte array to be encrypted. -+ * @param len Length of the byte array. -+ * @param result Byte array to receive the 8-byte encrypted MIC. -+ */ -+void dwc_wusb_cmf(u8 *key, u8 *nonce, -+ char *label, u8 *bytes, int len, u8 *result) -+{ -+ u8 block_m[16]; -+ u8 block_x[16]; -+ u8 block_t[8]; -+ int idx, blkNum; -+ u16 la = (u16)(len + 14); -+ -+ /* Set the AES-128 key */ -+ //dwc_aes_setkey(tfm, key, 16); -+ -+ /* Fill block B0 from flags = 0x59, N, and l(m) = 0 */ -+ block_m[0] = 0x59; -+ for (idx = 0; idx < 13; idx++) -+ block_m[idx + 1] = nonce[idx]; -+ block_m[14] = 0; -+ block_m[15] = 0; -+ -+ /* Produce the CBC IV */ -+ dwc_wusb_aes_encrypt(block_m, key, block_x); -+ show_block(block_m, "CBC IV in: ", "\n", 0); -+ show_block(block_x, "CBC IV out:", "\n", 0); -+ -+ /* Fill block B1 from l(a) = Blen + 14, and A */ -+ block_x[0] ^= (u8)(la >> 8); -+ block_x[1] ^= (u8)la; -+ for (idx = 0; idx < 14; idx++) -+ block_x[idx + 2] ^= label[idx]; -+ show_block(block_x, "After xor: ", "b1\n", 16); -+ -+ dwc_wusb_aes_encrypt(block_x, key, block_x); -+ show_block(block_x, "After AES: ", "b1\n", 16); -+ -+ idx = 0; -+ blkNum = 0; -+ -+ /* Fill remaining blocks with B */ -+ while (len-- > 0) { -+ block_x[idx] ^= *bytes++; -+ if (++idx >= 16) { -+ idx = 0; -+ show_block(block_x, "After xor: ", "\n", blkNum); -+ dwc_wusb_aes_encrypt(block_x, key, block_x); -+ show_block(block_x, "After AES: ", "\n", blkNum); -+ blkNum++; -+ } -+ } -+ -+ /* Handle partial last block */ -+ if (idx > 0) { -+ show_block(block_x, "After xor: ", "\n", blkNum); -+ dwc_wusb_aes_encrypt(block_x, key, block_x); -+ show_block(block_x, "After AES: ", "\n", blkNum); -+ } -+ -+ /* Save the MIC tag */ -+ DWC_MEMCPY(block_t, block_x, 8); -+ show_block(block_t, "MIC tag : ", NULL, 8); -+ -+ /* Fill block A0 from flags = 0x01, N, and counter = 0 */ -+ block_m[0] = 0x01; -+ block_m[14] = 0; -+ block_m[15] = 0; -+ -+ /* Encrypt the counter */ -+ dwc_wusb_aes_encrypt(block_m, key, block_x); -+ show_block(block_x, "CTR[MIC] : ", NULL, 8); -+ -+ /* XOR with MIC tag */ -+ for (idx = 0; idx < 8; idx++) { -+ block_t[idx] ^= block_x[idx]; -+ } -+ -+ /* Return result to caller */ -+ DWC_MEMCPY(result, block_t, 8); -+ show_block(result, "CCM-MIC : ", NULL, 8); -+ -+} -+ -+/** -+ * The PRF function described in section 6.5 of the WUSB spec. This function -+ * concatenates MIC values returned from dwc_cmf() to create a value of -+ * the requested length. -+ * -+ * @param prf_len Length of the PRF function in bits (64, 128, or 256). -+ * @param key, nonce, label, bytes, len Same as for dwc_cmf(). -+ * @param result Byte array to receive the result. -+ */ -+void dwc_wusb_prf(int prf_len, u8 *key, -+ u8 *nonce, char *label, u8 *bytes, int len, u8 *result) -+{ -+ int i; -+ -+ nonce[0] = 0; -+ for (i = 0; i < prf_len >> 6; i++, nonce[0]++) { -+ dwc_wusb_cmf(key, nonce, label, bytes, len, result); -+ result += 8; -+ } -+} -+ -+/** -+ * Fills in CCM Nonce per the WUSB spec. -+ * -+ * @param[in] haddr Host address. -+ * @param[in] daddr Device address. -+ * @param[in] tkid Session Key(PTK) identifier. -+ * @param[out] nonce Pointer to where the CCM Nonce output is to be written. -+ */ -+void dwc_wusb_fill_ccm_nonce(uint16_t haddr, uint16_t daddr, uint8_t *tkid, -+ uint8_t *nonce) -+{ -+ -+ DWC_DEBUG("%s %x %x\n", __func__, daddr, haddr); -+ -+ DWC_MEMSET(&nonce[0], 0, 16); -+ -+ DWC_MEMCPY(&nonce[6], tkid, 3); -+ nonce[9] = daddr & 0xFF; -+ nonce[10] = (daddr >> 8) & 0xFF; -+ nonce[11] = haddr & 0xFF; -+ nonce[12] = (haddr >> 8) & 0xFF; -+ -+ dump_bytes("CCM nonce", nonce, 16); -+} -+ -+/** -+ * Generates a 16-byte cryptographic-grade random number for the Host/Device -+ * Nonce. -+ */ -+void dwc_wusb_gen_nonce(uint16_t addr, uint8_t *nonce) -+{ -+ uint8_t inonce[16]; -+ uint32_t temp[4]; -+ -+ /* Fill in the Nonce */ -+ DWC_MEMSET(&inonce[0], 0, sizeof(inonce)); -+ inonce[9] = addr & 0xFF; -+ inonce[10] = (addr >> 8) & 0xFF; -+ inonce[11] = inonce[9]; -+ inonce[12] = inonce[10]; -+ -+ /* Collect "randomness samples" */ -+ DWC_RANDOM_BYTES((uint8_t *)temp, 16); -+ -+ dwc_wusb_prf_128((uint8_t *)temp, nonce, -+ "Random Numbers", (uint8_t *)temp, sizeof(temp), -+ nonce); -+} -+ -+/** -+ * Generates the Session Key (PTK) and Key Confirmation Key (KCK) per the -+ * WUSB spec. -+ * -+ * @param[in] ccm_nonce Pointer to CCM Nonce. -+ * @param[in] mk Master Key to derive the session from -+ * @param[in] hnonce Pointer to Host Nonce. -+ * @param[in] dnonce Pointer to Device Nonce. -+ * @param[out] kck Pointer to where the KCK output is to be written. -+ * @param[out] ptk Pointer to where the PTK output is to be written. -+ */ -+void dwc_wusb_gen_key(uint8_t *ccm_nonce, uint8_t *mk, uint8_t *hnonce, -+ uint8_t *dnonce, uint8_t *kck, uint8_t *ptk) -+{ -+ uint8_t idata[32]; -+ uint8_t odata[32]; -+ -+ dump_bytes("ck", mk, 16); -+ dump_bytes("hnonce", hnonce, 16); -+ dump_bytes("dnonce", dnonce, 16); -+ -+ /* The data is the HNonce and DNonce concatenated */ -+ DWC_MEMCPY(&idata[0], hnonce, 16); -+ DWC_MEMCPY(&idata[16], dnonce, 16); -+ -+ dwc_wusb_prf_256(mk, ccm_nonce, "Pair-wise keys", idata, 32, odata); -+ -+ /* Low 16 bytes of the result is the KCK, high 16 is the PTK */ -+ DWC_MEMCPY(kck, &odata[0], 16); -+ DWC_MEMCPY(ptk, &odata[16], 16); -+ -+ dump_bytes("kck", kck, 16); -+ dump_bytes("ptk", ptk, 16); -+} -+ -+/** -+ * Generates the Message Integrity Code over the Handshake data per the -+ * WUSB spec. -+ * -+ * @param ccm_nonce Pointer to CCM Nonce. -+ * @param kck Pointer to Key Confirmation Key. -+ * @param data Pointer to Handshake data to be checked. -+ * @param mic Pointer to where the MIC output is to be written. -+ */ -+void dwc_wusb_gen_mic(uint8_t *ccm_nonce, uint8_t *kck, -+ uint8_t *data, uint8_t *mic) -+{ -+ -+ dwc_wusb_prf_64(kck, ccm_nonce, "out-of-bandMIC", -+ data, WUSB_HANDSHAKE_LEN_FOR_MIC, mic); -+} -+ -+#endif /* DWC_CRYPTOLIB */ -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_crypto.h linux-rpi/drivers/usb/host/dwc_common_port/dwc_crypto.h ---- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_crypto.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_crypto.h 2015-11-29 09:42:39.915098960 +0100 -@@ -0,0 +1,111 @@ -+/* ========================================================================= -+ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_crypto.h $ -+ * $Revision: #3 $ -+ * $Date: 2010/09/28 $ -+ * $Change: 1596182 $ -+ * -+ * Synopsys Portability Library Software and documentation -+ * (hereinafter, "Software") is an Unsupported proprietary work of -+ * Synopsys, Inc. unless otherwise expressly agreed to in writing -+ * between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product -+ * under any End User Software License Agreement or Agreement for -+ * Licensed Product with Synopsys or any supplement thereto. You are -+ * permitted to use and redistribute this Software in source and binary -+ * forms, with or without modification, provided that redistributions -+ * of source code must retain this notice. You may not view, use, -+ * disclose, copy or distribute this file or any information contained -+ * herein except pursuant to this license grant from Synopsys. If you -+ * do not agree with this notice, including the disclaimer below, then -+ * you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" -+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL -+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY -+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================= */ -+ -+#ifndef _DWC_CRYPTO_H_ -+#define _DWC_CRYPTO_H_ -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+/** @file -+ * -+ * This file contains declarations for the WUSB Cryptographic routines as -+ * defined in the WUSB spec. They are only to be used internally by the DWC UWB -+ * modules. -+ */ -+ -+#include "dwc_os.h" -+ -+int dwc_wusb_aes_encrypt(u8 *src, u8 *key, u8 *dst); -+ -+void dwc_wusb_cmf(u8 *key, u8 *nonce, -+ char *label, u8 *bytes, int len, u8 *result); -+void dwc_wusb_prf(int prf_len, u8 *key, -+ u8 *nonce, char *label, u8 *bytes, int len, u8 *result); -+ -+/** -+ * The PRF-64 function described in section 6.5 of the WUSB spec. -+ * -+ * @param key, nonce, label, bytes, len, result Same as for dwc_prf(). -+ */ -+static inline void dwc_wusb_prf_64(u8 *key, u8 *nonce, -+ char *label, u8 *bytes, int len, u8 *result) -+{ -+ dwc_wusb_prf(64, key, nonce, label, bytes, len, result); -+} -+ -+/** -+ * The PRF-128 function described in section 6.5 of the WUSB spec. -+ * -+ * @param key, nonce, label, bytes, len, result Same as for dwc_prf(). -+ */ -+static inline void dwc_wusb_prf_128(u8 *key, u8 *nonce, -+ char *label, u8 *bytes, int len, u8 *result) -+{ -+ dwc_wusb_prf(128, key, nonce, label, bytes, len, result); -+} -+ -+/** -+ * The PRF-256 function described in section 6.5 of the WUSB spec. -+ * -+ * @param key, nonce, label, bytes, len, result Same as for dwc_prf(). -+ */ -+static inline void dwc_wusb_prf_256(u8 *key, u8 *nonce, -+ char *label, u8 *bytes, int len, u8 *result) -+{ -+ dwc_wusb_prf(256, key, nonce, label, bytes, len, result); -+} -+ -+ -+void dwc_wusb_fill_ccm_nonce(uint16_t haddr, uint16_t daddr, uint8_t *tkid, -+ uint8_t *nonce); -+void dwc_wusb_gen_nonce(uint16_t addr, -+ uint8_t *nonce); -+ -+void dwc_wusb_gen_key(uint8_t *ccm_nonce, uint8_t *mk, -+ uint8_t *hnonce, uint8_t *dnonce, -+ uint8_t *kck, uint8_t *ptk); -+ -+ -+void dwc_wusb_gen_mic(uint8_t *ccm_nonce, uint8_t -+ *kck, uint8_t *data, uint8_t *mic); -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* _DWC_CRYPTO_H_ */ -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_dh.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_dh.c ---- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_dh.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_dh.c 2015-11-29 09:42:39.915098960 +0100 -@@ -0,0 +1,291 @@ -+/* ========================================================================= -+ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_dh.c $ -+ * $Revision: #3 $ -+ * $Date: 2010/09/28 $ -+ * $Change: 1596182 $ -+ * -+ * Synopsys Portability Library Software and documentation -+ * (hereinafter, "Software") is an Unsupported proprietary work of -+ * Synopsys, Inc. unless otherwise expressly agreed to in writing -+ * between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product -+ * under any End User Software License Agreement or Agreement for -+ * Licensed Product with Synopsys or any supplement thereto. You are -+ * permitted to use and redistribute this Software in source and binary -+ * forms, with or without modification, provided that redistributions -+ * of source code must retain this notice. You may not view, use, -+ * disclose, copy or distribute this file or any information contained -+ * herein except pursuant to this license grant from Synopsys. If you -+ * do not agree with this notice, including the disclaimer below, then -+ * you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" -+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL -+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY -+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================= */ -+#ifdef DWC_CRYPTOLIB -+ -+#ifndef CONFIG_MACH_IPMATE -+ -+#include "dwc_dh.h" -+#include "dwc_modpow.h" -+ -+#ifdef DEBUG -+/* This function prints out a buffer in the format described in the Association -+ * Model specification. */ -+static void dh_dump(char *str, void *_num, int len) -+{ -+ uint8_t *num = _num; -+ int i; -+ DWC_PRINTF("%s\n", str); -+ for (i = 0; i < len; i ++) { -+ DWC_PRINTF("%02x", num[i]); -+ if (((i + 1) % 2) == 0) DWC_PRINTF(" "); -+ if (((i + 1) % 26) == 0) DWC_PRINTF("\n"); -+ } -+ -+ DWC_PRINTF("\n"); -+} -+#else -+#define dh_dump(_x...) do {; } while(0) -+#endif -+ -+/* Constant g value */ -+static __u32 dh_g[] = { -+ 0x02000000, -+}; -+ -+/* Constant p value */ -+static __u32 dh_p[] = { -+ 0xFFFFFFFF, 0xFFFFFFFF, 0xA2DA0FC9, 0x34C26821, 0x8B62C6C4, 0xD11CDC80, 0x084E0229, 0x74CC678A, -+ 0xA6BE0B02, 0x229B133B, 0x79084A51, 0xDD04348E, 0xB31995EF, 0x1B433ACD, 0x6D0A2B30, 0x37145FF2, -+ 0x6D35E14F, 0x45C2516D, 0x76B585E4, 0xC67E5E62, 0xE9424CF4, 0x6BED37A6, 0xB65CFF0B, 0xEDB706F4, -+ 0xFB6B38EE, 0xA59F895A, 0x11249FAE, 0xE61F4B7C, 0x51662849, 0x3D5BE4EC, 0xB87C00C2, 0x05BF63A1, -+ 0x3648DA98, 0x9AD3551C, 0xA83F1669, 0x5FCF24FD, 0x235D6583, 0x96ADA3DC, 0x56F3621C, 0xBB528520, -+ 0x0729D59E, 0x6D969670, 0x4E350C67, 0x0498BC4A, 0x086C74F1, 0x7C2118CA, 0x465E9032, 0x3BCE362E, -+ 0x2C779EE3, 0x03860E18, 0xA283279B, 0x8FA207EC, 0xF05DC5B5, 0xC9524C6F, 0xF6CB2BDE, 0x18175895, -+ 0x7C499539, 0xE56A95EA, 0x1826D215, 0x1005FA98, 0x5A8E7215, 0x2DC4AA8A, 0x0D1733AD, 0x337A5004, -+ 0xAB2155A8, 0x64BA1CDF, 0x0485FBEC, 0x0AEFDB58, 0x5771EA8A, 0x7D0C065D, 0x850F97B3, 0xC7E4E1A6, -+ 0x8CAEF5AB, 0xD73309DB, 0xE0948C1E, 0x9D61254A, 0x26D2E3CE, 0x6BEED21A, 0x06FA2FF1, 0x64088AD9, -+ 0x730276D8, 0x646AC83E, 0x182B1F52, 0x0C207B17, 0x5717E1BB, 0x6C5D617A, 0xC0880977, 0xE246D9BA, -+ 0xA04FE208, 0x31ABE574, 0xFC5BDB43, 0x8E10FDE0, 0x20D1824B, 0xCAD23AA9, 0xFFFFFFFF, 0xFFFFFFFF, -+}; -+ -+static void dh_swap_bytes(void *_in, void *_out, uint32_t len) -+{ -+ uint8_t *in = _in; -+ uint8_t *out = _out; -+ int i; -+ for (i=0; inext = (link); \ -+ (link)->prev = (link); \ -+} while (0) -+ -+#define DWC_LIST_FIRST(link) ((link)->next) -+#define DWC_LIST_LAST(link) ((link)->prev) -+#define DWC_LIST_END(link) (link) -+#define DWC_LIST_NEXT(link) ((link)->next) -+#define DWC_LIST_PREV(link) ((link)->prev) -+#define DWC_LIST_EMPTY(link) \ -+ (DWC_LIST_FIRST(link) == DWC_LIST_END(link)) -+#define DWC_LIST_ENTRY(link, type, field) \ -+ (type *)((uint8_t *)(link) - (size_t)(&((type *)0)->field)) -+ -+#if 0 -+#define DWC_LIST_INSERT_HEAD(list, link) do { \ -+ (link)->next = (list)->next; \ -+ (link)->prev = (list); \ -+ (list)->next->prev = (link); \ -+ (list)->next = (link); \ -+} while (0) -+ -+#define DWC_LIST_INSERT_TAIL(list, link) do { \ -+ (link)->next = (list); \ -+ (link)->prev = (list)->prev; \ -+ (list)->prev->next = (link); \ -+ (list)->prev = (link); \ -+} while (0) -+#else -+#define DWC_LIST_INSERT_HEAD(list, link) do { \ -+ dwc_list_link_t *__next__ = (list)->next; \ -+ __next__->prev = (link); \ -+ (link)->next = __next__; \ -+ (link)->prev = (list); \ -+ (list)->next = (link); \ -+} while (0) -+ -+#define DWC_LIST_INSERT_TAIL(list, link) do { \ -+ dwc_list_link_t *__prev__ = (list)->prev; \ -+ (list)->prev = (link); \ -+ (link)->next = (list); \ -+ (link)->prev = __prev__; \ -+ __prev__->next = (link); \ -+} while (0) -+#endif -+ -+#if 0 -+static inline void __list_add(struct list_head *new, -+ struct list_head *prev, -+ struct list_head *next) -+{ -+ next->prev = new; -+ new->next = next; -+ new->prev = prev; -+ prev->next = new; -+} -+ -+static inline void list_add(struct list_head *new, struct list_head *head) -+{ -+ __list_add(new, head, head->next); -+} -+ -+static inline void list_add_tail(struct list_head *new, struct list_head *head) -+{ -+ __list_add(new, head->prev, head); -+} -+ -+static inline void __list_del(struct list_head * prev, struct list_head * next) -+{ -+ next->prev = prev; -+ prev->next = next; -+} -+ -+static inline void list_del(struct list_head *entry) -+{ -+ __list_del(entry->prev, entry->next); -+ entry->next = LIST_POISON1; -+ entry->prev = LIST_POISON2; -+} -+#endif -+ -+#define DWC_LIST_REMOVE(link) do { \ -+ (link)->next->prev = (link)->prev; \ -+ (link)->prev->next = (link)->next; \ -+} while (0) -+ -+#define DWC_LIST_REMOVE_INIT(link) do { \ -+ DWC_LIST_REMOVE(link); \ -+ DWC_LIST_INIT(link); \ -+} while (0) -+ -+#define DWC_LIST_MOVE_HEAD(list, link) do { \ -+ DWC_LIST_REMOVE(link); \ -+ DWC_LIST_INSERT_HEAD(list, link); \ -+} while (0) -+ -+#define DWC_LIST_MOVE_TAIL(list, link) do { \ -+ DWC_LIST_REMOVE(link); \ -+ DWC_LIST_INSERT_TAIL(list, link); \ -+} while (0) -+ -+#define DWC_LIST_FOREACH(var, list) \ -+ for((var) = DWC_LIST_FIRST(list); \ -+ (var) != DWC_LIST_END(list); \ -+ (var) = DWC_LIST_NEXT(var)) -+ -+#define DWC_LIST_FOREACH_SAFE(var, var2, list) \ -+ for((var) = DWC_LIST_FIRST(list), (var2) = DWC_LIST_NEXT(var); \ -+ (var) != DWC_LIST_END(list); \ -+ (var) = (var2), (var2) = DWC_LIST_NEXT(var2)) -+ -+#define DWC_LIST_FOREACH_REVERSE(var, list) \ -+ for((var) = DWC_LIST_LAST(list); \ -+ (var) != DWC_LIST_END(list); \ -+ (var) = DWC_LIST_PREV(var)) -+ -+/* -+ * Singly-linked List definitions. -+ */ -+#define DWC_SLIST_HEAD(name, type) \ -+struct name { \ -+ struct type *slh_first; /* first element */ \ -+} -+ -+#define DWC_SLIST_HEAD_INITIALIZER(head) \ -+ { NULL } -+ -+#define DWC_SLIST_ENTRY(type) \ -+struct { \ -+ struct type *sle_next; /* next element */ \ -+} -+ -+/* -+ * Singly-linked List access methods. -+ */ -+#define DWC_SLIST_FIRST(head) ((head)->slh_first) -+#define DWC_SLIST_END(head) NULL -+#define DWC_SLIST_EMPTY(head) (SLIST_FIRST(head) == SLIST_END(head)) -+#define DWC_SLIST_NEXT(elm, field) ((elm)->field.sle_next) -+ -+#define DWC_SLIST_FOREACH(var, head, field) \ -+ for((var) = SLIST_FIRST(head); \ -+ (var) != SLIST_END(head); \ -+ (var) = SLIST_NEXT(var, field)) -+ -+#define DWC_SLIST_FOREACH_PREVPTR(var, varp, head, field) \ -+ for((varp) = &SLIST_FIRST((head)); \ -+ ((var) = *(varp)) != SLIST_END(head); \ -+ (varp) = &SLIST_NEXT((var), field)) -+ -+/* -+ * Singly-linked List functions. -+ */ -+#define DWC_SLIST_INIT(head) { \ -+ SLIST_FIRST(head) = SLIST_END(head); \ -+} -+ -+#define DWC_SLIST_INSERT_AFTER(slistelm, elm, field) do { \ -+ (elm)->field.sle_next = (slistelm)->field.sle_next; \ -+ (slistelm)->field.sle_next = (elm); \ -+} while (0) -+ -+#define DWC_SLIST_INSERT_HEAD(head, elm, field) do { \ -+ (elm)->field.sle_next = (head)->slh_first; \ -+ (head)->slh_first = (elm); \ -+} while (0) -+ -+#define DWC_SLIST_REMOVE_NEXT(head, elm, field) do { \ -+ (elm)->field.sle_next = (elm)->field.sle_next->field.sle_next; \ -+} while (0) -+ -+#define DWC_SLIST_REMOVE_HEAD(head, field) do { \ -+ (head)->slh_first = (head)->slh_first->field.sle_next; \ -+} while (0) -+ -+#define DWC_SLIST_REMOVE(head, elm, type, field) do { \ -+ if ((head)->slh_first == (elm)) { \ -+ SLIST_REMOVE_HEAD((head), field); \ -+ } \ -+ else { \ -+ struct type *curelm = (head)->slh_first; \ -+ while( curelm->field.sle_next != (elm) ) \ -+ curelm = curelm->field.sle_next; \ -+ curelm->field.sle_next = \ -+ curelm->field.sle_next->field.sle_next; \ -+ } \ -+} while (0) -+ -+/* -+ * Simple queue definitions. -+ */ -+#define DWC_SIMPLEQ_HEAD(name, type) \ -+struct name { \ -+ struct type *sqh_first; /* first element */ \ -+ struct type **sqh_last; /* addr of last next element */ \ -+} -+ -+#define DWC_SIMPLEQ_HEAD_INITIALIZER(head) \ -+ { NULL, &(head).sqh_first } -+ -+#define DWC_SIMPLEQ_ENTRY(type) \ -+struct { \ -+ struct type *sqe_next; /* next element */ \ -+} -+ -+/* -+ * Simple queue access methods. -+ */ -+#define DWC_SIMPLEQ_FIRST(head) ((head)->sqh_first) -+#define DWC_SIMPLEQ_END(head) NULL -+#define DWC_SIMPLEQ_EMPTY(head) (SIMPLEQ_FIRST(head) == SIMPLEQ_END(head)) -+#define DWC_SIMPLEQ_NEXT(elm, field) ((elm)->field.sqe_next) -+ -+#define DWC_SIMPLEQ_FOREACH(var, head, field) \ -+ for((var) = SIMPLEQ_FIRST(head); \ -+ (var) != SIMPLEQ_END(head); \ -+ (var) = SIMPLEQ_NEXT(var, field)) -+ -+/* -+ * Simple queue functions. -+ */ -+#define DWC_SIMPLEQ_INIT(head) do { \ -+ (head)->sqh_first = NULL; \ -+ (head)->sqh_last = &(head)->sqh_first; \ -+} while (0) -+ -+#define DWC_SIMPLEQ_INSERT_HEAD(head, elm, field) do { \ -+ if (((elm)->field.sqe_next = (head)->sqh_first) == NULL) \ -+ (head)->sqh_last = &(elm)->field.sqe_next; \ -+ (head)->sqh_first = (elm); \ -+} while (0) -+ -+#define DWC_SIMPLEQ_INSERT_TAIL(head, elm, field) do { \ -+ (elm)->field.sqe_next = NULL; \ -+ *(head)->sqh_last = (elm); \ -+ (head)->sqh_last = &(elm)->field.sqe_next; \ -+} while (0) -+ -+#define DWC_SIMPLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ -+ if (((elm)->field.sqe_next = (listelm)->field.sqe_next) == NULL)\ -+ (head)->sqh_last = &(elm)->field.sqe_next; \ -+ (listelm)->field.sqe_next = (elm); \ -+} while (0) -+ -+#define DWC_SIMPLEQ_REMOVE_HEAD(head, field) do { \ -+ if (((head)->sqh_first = (head)->sqh_first->field.sqe_next) == NULL) \ -+ (head)->sqh_last = &(head)->sqh_first; \ -+} while (0) -+ -+/* -+ * Tail queue definitions. -+ */ -+#define DWC_TAILQ_HEAD(name, type) \ -+struct name { \ -+ struct type *tqh_first; /* first element */ \ -+ struct type **tqh_last; /* addr of last next element */ \ -+} -+ -+#define DWC_TAILQ_HEAD_INITIALIZER(head) \ -+ { NULL, &(head).tqh_first } -+ -+#define DWC_TAILQ_ENTRY(type) \ -+struct { \ -+ struct type *tqe_next; /* next element */ \ -+ struct type **tqe_prev; /* address of previous next element */ \ -+} -+ -+/* -+ * tail queue access methods -+ */ -+#define DWC_TAILQ_FIRST(head) ((head)->tqh_first) -+#define DWC_TAILQ_END(head) NULL -+#define DWC_TAILQ_NEXT(elm, field) ((elm)->field.tqe_next) -+#define DWC_TAILQ_LAST(head, headname) \ -+ (*(((struct headname *)((head)->tqh_last))->tqh_last)) -+/* XXX */ -+#define DWC_TAILQ_PREV(elm, headname, field) \ -+ (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last)) -+#define DWC_TAILQ_EMPTY(head) \ -+ (DWC_TAILQ_FIRST(head) == DWC_TAILQ_END(head)) -+ -+#define DWC_TAILQ_FOREACH(var, head, field) \ -+ for ((var) = DWC_TAILQ_FIRST(head); \ -+ (var) != DWC_TAILQ_END(head); \ -+ (var) = DWC_TAILQ_NEXT(var, field)) -+ -+#define DWC_TAILQ_FOREACH_REVERSE(var, head, headname, field) \ -+ for ((var) = DWC_TAILQ_LAST(head, headname); \ -+ (var) != DWC_TAILQ_END(head); \ -+ (var) = DWC_TAILQ_PREV(var, headname, field)) -+ -+/* -+ * Tail queue functions. -+ */ -+#define DWC_TAILQ_INIT(head) do { \ -+ (head)->tqh_first = NULL; \ -+ (head)->tqh_last = &(head)->tqh_first; \ -+} while (0) -+ -+#define DWC_TAILQ_INSERT_HEAD(head, elm, field) do { \ -+ if (((elm)->field.tqe_next = (head)->tqh_first) != NULL) \ -+ (head)->tqh_first->field.tqe_prev = \ -+ &(elm)->field.tqe_next; \ -+ else \ -+ (head)->tqh_last = &(elm)->field.tqe_next; \ -+ (head)->tqh_first = (elm); \ -+ (elm)->field.tqe_prev = &(head)->tqh_first; \ -+} while (0) -+ -+#define DWC_TAILQ_INSERT_TAIL(head, elm, field) do { \ -+ (elm)->field.tqe_next = NULL; \ -+ (elm)->field.tqe_prev = (head)->tqh_last; \ -+ *(head)->tqh_last = (elm); \ -+ (head)->tqh_last = &(elm)->field.tqe_next; \ -+} while (0) -+ -+#define DWC_TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \ -+ if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL)\ -+ (elm)->field.tqe_next->field.tqe_prev = \ -+ &(elm)->field.tqe_next; \ -+ else \ -+ (head)->tqh_last = &(elm)->field.tqe_next; \ -+ (listelm)->field.tqe_next = (elm); \ -+ (elm)->field.tqe_prev = &(listelm)->field.tqe_next; \ -+} while (0) -+ -+#define DWC_TAILQ_INSERT_BEFORE(listelm, elm, field) do { \ -+ (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \ -+ (elm)->field.tqe_next = (listelm); \ -+ *(listelm)->field.tqe_prev = (elm); \ -+ (listelm)->field.tqe_prev = &(elm)->field.tqe_next; \ -+} while (0) -+ -+#define DWC_TAILQ_REMOVE(head, elm, field) do { \ -+ if (((elm)->field.tqe_next) != NULL) \ -+ (elm)->field.tqe_next->field.tqe_prev = \ -+ (elm)->field.tqe_prev; \ -+ else \ -+ (head)->tqh_last = (elm)->field.tqe_prev; \ -+ *(elm)->field.tqe_prev = (elm)->field.tqe_next; \ -+} while (0) -+ -+#define DWC_TAILQ_REPLACE(head, elm, elm2, field) do { \ -+ if (((elm2)->field.tqe_next = (elm)->field.tqe_next) != NULL) \ -+ (elm2)->field.tqe_next->field.tqe_prev = \ -+ &(elm2)->field.tqe_next; \ -+ else \ -+ (head)->tqh_last = &(elm2)->field.tqe_next; \ -+ (elm2)->field.tqe_prev = (elm)->field.tqe_prev; \ -+ *(elm2)->field.tqe_prev = (elm2); \ -+} while (0) -+ -+/* -+ * Circular queue definitions. -+ */ -+#define DWC_CIRCLEQ_HEAD(name, type) \ -+struct name { \ -+ struct type *cqh_first; /* first element */ \ -+ struct type *cqh_last; /* last element */ \ -+} -+ -+#define DWC_CIRCLEQ_HEAD_INITIALIZER(head) \ -+ { DWC_CIRCLEQ_END(&head), DWC_CIRCLEQ_END(&head) } -+ -+#define DWC_CIRCLEQ_ENTRY(type) \ -+struct { \ -+ struct type *cqe_next; /* next element */ \ -+ struct type *cqe_prev; /* previous element */ \ -+} -+ -+/* -+ * Circular queue access methods -+ */ -+#define DWC_CIRCLEQ_FIRST(head) ((head)->cqh_first) -+#define DWC_CIRCLEQ_LAST(head) ((head)->cqh_last) -+#define DWC_CIRCLEQ_END(head) ((void *)(head)) -+#define DWC_CIRCLEQ_NEXT(elm, field) ((elm)->field.cqe_next) -+#define DWC_CIRCLEQ_PREV(elm, field) ((elm)->field.cqe_prev) -+#define DWC_CIRCLEQ_EMPTY(head) \ -+ (DWC_CIRCLEQ_FIRST(head) == DWC_CIRCLEQ_END(head)) -+ -+#define DWC_CIRCLEQ_EMPTY_ENTRY(elm, field) (((elm)->field.cqe_next == NULL) && ((elm)->field.cqe_prev == NULL)) -+ -+#define DWC_CIRCLEQ_FOREACH(var, head, field) \ -+ for((var) = DWC_CIRCLEQ_FIRST(head); \ -+ (var) != DWC_CIRCLEQ_END(head); \ -+ (var) = DWC_CIRCLEQ_NEXT(var, field)) -+ -+#define DWC_CIRCLEQ_FOREACH_SAFE(var, var2, head, field) \ -+ for((var) = DWC_CIRCLEQ_FIRST(head), var2 = DWC_CIRCLEQ_NEXT(var, field); \ -+ (var) != DWC_CIRCLEQ_END(head); \ -+ (var) = var2, var2 = DWC_CIRCLEQ_NEXT(var, field)) -+ -+#define DWC_CIRCLEQ_FOREACH_REVERSE(var, head, field) \ -+ for((var) = DWC_CIRCLEQ_LAST(head); \ -+ (var) != DWC_CIRCLEQ_END(head); \ -+ (var) = DWC_CIRCLEQ_PREV(var, field)) -+ -+/* -+ * Circular queue functions. -+ */ -+#define DWC_CIRCLEQ_INIT(head) do { \ -+ (head)->cqh_first = DWC_CIRCLEQ_END(head); \ -+ (head)->cqh_last = DWC_CIRCLEQ_END(head); \ -+} while (0) -+ -+#define DWC_CIRCLEQ_INIT_ENTRY(elm, field) do { \ -+ (elm)->field.cqe_next = NULL; \ -+ (elm)->field.cqe_prev = NULL; \ -+} while (0) -+ -+#define DWC_CIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ -+ (elm)->field.cqe_next = (listelm)->field.cqe_next; \ -+ (elm)->field.cqe_prev = (listelm); \ -+ if ((listelm)->field.cqe_next == DWC_CIRCLEQ_END(head)) \ -+ (head)->cqh_last = (elm); \ -+ else \ -+ (listelm)->field.cqe_next->field.cqe_prev = (elm); \ -+ (listelm)->field.cqe_next = (elm); \ -+} while (0) -+ -+#define DWC_CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do { \ -+ (elm)->field.cqe_next = (listelm); \ -+ (elm)->field.cqe_prev = (listelm)->field.cqe_prev; \ -+ if ((listelm)->field.cqe_prev == DWC_CIRCLEQ_END(head)) \ -+ (head)->cqh_first = (elm); \ -+ else \ -+ (listelm)->field.cqe_prev->field.cqe_next = (elm); \ -+ (listelm)->field.cqe_prev = (elm); \ -+} while (0) -+ -+#define DWC_CIRCLEQ_INSERT_HEAD(head, elm, field) do { \ -+ (elm)->field.cqe_next = (head)->cqh_first; \ -+ (elm)->field.cqe_prev = DWC_CIRCLEQ_END(head); \ -+ if ((head)->cqh_last == DWC_CIRCLEQ_END(head)) \ -+ (head)->cqh_last = (elm); \ -+ else \ -+ (head)->cqh_first->field.cqe_prev = (elm); \ -+ (head)->cqh_first = (elm); \ -+} while (0) -+ -+#define DWC_CIRCLEQ_INSERT_TAIL(head, elm, field) do { \ -+ (elm)->field.cqe_next = DWC_CIRCLEQ_END(head); \ -+ (elm)->field.cqe_prev = (head)->cqh_last; \ -+ if ((head)->cqh_first == DWC_CIRCLEQ_END(head)) \ -+ (head)->cqh_first = (elm); \ -+ else \ -+ (head)->cqh_last->field.cqe_next = (elm); \ -+ (head)->cqh_last = (elm); \ -+} while (0) -+ -+#define DWC_CIRCLEQ_REMOVE(head, elm, field) do { \ -+ if ((elm)->field.cqe_next == DWC_CIRCLEQ_END(head)) \ -+ (head)->cqh_last = (elm)->field.cqe_prev; \ -+ else \ -+ (elm)->field.cqe_next->field.cqe_prev = \ -+ (elm)->field.cqe_prev; \ -+ if ((elm)->field.cqe_prev == DWC_CIRCLEQ_END(head)) \ -+ (head)->cqh_first = (elm)->field.cqe_next; \ -+ else \ -+ (elm)->field.cqe_prev->field.cqe_next = \ -+ (elm)->field.cqe_next; \ -+} while (0) -+ -+#define DWC_CIRCLEQ_REMOVE_INIT(head, elm, field) do { \ -+ DWC_CIRCLEQ_REMOVE(head, elm, field); \ -+ DWC_CIRCLEQ_INIT_ENTRY(elm, field); \ -+} while (0) -+ -+#define DWC_CIRCLEQ_REPLACE(head, elm, elm2, field) do { \ -+ if (((elm2)->field.cqe_next = (elm)->field.cqe_next) == \ -+ DWC_CIRCLEQ_END(head)) \ -+ (head).cqh_last = (elm2); \ -+ else \ -+ (elm2)->field.cqe_next->field.cqe_prev = (elm2); \ -+ if (((elm2)->field.cqe_prev = (elm)->field.cqe_prev) == \ -+ DWC_CIRCLEQ_END(head)) \ -+ (head).cqh_first = (elm2); \ -+ else \ -+ (elm2)->field.cqe_prev->field.cqe_next = (elm2); \ -+} while (0) -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* _DWC_LIST_H_ */ -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_mem.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_mem.c ---- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_mem.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_mem.c 2015-11-29 09:42:39.915098960 +0100 -@@ -0,0 +1,245 @@ -+/* Memory Debugging */ -+#ifdef DWC_DEBUG_MEMORY -+ -+#include "dwc_os.h" -+#include "dwc_list.h" -+ -+struct allocation { -+ void *addr; -+ void *ctx; -+ char *func; -+ int line; -+ uint32_t size; -+ int dma; -+ DWC_CIRCLEQ_ENTRY(allocation) entry; -+}; -+ -+DWC_CIRCLEQ_HEAD(allocation_queue, allocation); -+ -+struct allocation_manager { -+ void *mem_ctx; -+ struct allocation_queue allocations; -+ -+ /* statistics */ -+ int num; -+ int num_freed; -+ int num_active; -+ uint32_t total; -+ uint32_t cur; -+ uint32_t max; -+}; -+ -+static struct allocation_manager *manager = NULL; -+ -+static int add_allocation(void *ctx, uint32_t size, char const *func, int line, void *addr, -+ int dma) -+{ -+ struct allocation *a; -+ -+ DWC_ASSERT(manager != NULL, "manager not allocated"); -+ -+ a = __DWC_ALLOC_ATOMIC(manager->mem_ctx, sizeof(*a)); -+ if (!a) { -+ return -DWC_E_NO_MEMORY; -+ } -+ -+ a->func = __DWC_ALLOC_ATOMIC(manager->mem_ctx, DWC_STRLEN(func) + 1); -+ if (!a->func) { -+ __DWC_FREE(manager->mem_ctx, a); -+ return -DWC_E_NO_MEMORY; -+ } -+ -+ DWC_MEMCPY(a->func, func, DWC_STRLEN(func) + 1); -+ a->addr = addr; -+ a->ctx = ctx; -+ a->line = line; -+ a->size = size; -+ a->dma = dma; -+ DWC_CIRCLEQ_INSERT_TAIL(&manager->allocations, a, entry); -+ -+ /* Update stats */ -+ manager->num++; -+ manager->num_active++; -+ manager->total += size; -+ manager->cur += size; -+ -+ if (manager->max < manager->cur) { -+ manager->max = manager->cur; -+ } -+ -+ return 0; -+} -+ -+static struct allocation *find_allocation(void *ctx, void *addr) -+{ -+ struct allocation *a; -+ -+ DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) { -+ if (a->ctx == ctx && a->addr == addr) { -+ return a; -+ } -+ } -+ -+ return NULL; -+} -+ -+static void free_allocation(void *ctx, void *addr, char const *func, int line) -+{ -+ struct allocation *a = find_allocation(ctx, addr); -+ -+ if (!a) { -+ DWC_ASSERT(0, -+ "Free of address %p that was never allocated or already freed %s:%d", -+ addr, func, line); -+ return; -+ } -+ -+ DWC_CIRCLEQ_REMOVE(&manager->allocations, a, entry); -+ -+ manager->num_active--; -+ manager->num_freed++; -+ manager->cur -= a->size; -+ __DWC_FREE(manager->mem_ctx, a->func); -+ __DWC_FREE(manager->mem_ctx, a); -+} -+ -+int dwc_memory_debug_start(void *mem_ctx) -+{ -+ DWC_ASSERT(manager == NULL, "Memory debugging has already started\n"); -+ -+ if (manager) { -+ return -DWC_E_BUSY; -+ } -+ -+ manager = __DWC_ALLOC(mem_ctx, sizeof(*manager)); -+ if (!manager) { -+ return -DWC_E_NO_MEMORY; -+ } -+ -+ DWC_CIRCLEQ_INIT(&manager->allocations); -+ manager->mem_ctx = mem_ctx; -+ manager->num = 0; -+ manager->num_freed = 0; -+ manager->num_active = 0; -+ manager->total = 0; -+ manager->cur = 0; -+ manager->max = 0; -+ -+ return 0; -+} -+ -+void dwc_memory_debug_stop(void) -+{ -+ struct allocation *a; -+ -+ dwc_memory_debug_report(); -+ -+ DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) { -+ DWC_ERROR("Memory leaked from %s:%d\n", a->func, a->line); -+ free_allocation(a->ctx, a->addr, NULL, -1); -+ } -+ -+ __DWC_FREE(manager->mem_ctx, manager); -+} -+ -+void dwc_memory_debug_report(void) -+{ -+ struct allocation *a; -+ -+ DWC_PRINTF("\n\n\n----------------- Memory Debugging Report -----------------\n\n"); -+ DWC_PRINTF("Num Allocations = %d\n", manager->num); -+ DWC_PRINTF("Freed = %d\n", manager->num_freed); -+ DWC_PRINTF("Active = %d\n", manager->num_active); -+ DWC_PRINTF("Current Memory Used = %d\n", manager->cur); -+ DWC_PRINTF("Total Memory Used = %d\n", manager->total); -+ DWC_PRINTF("Maximum Memory Used at Once = %d\n", manager->max); -+ DWC_PRINTF("Unfreed allocations:\n"); -+ -+ DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) { -+ DWC_PRINTF(" addr=%p, size=%d from %s:%d, DMA=%d\n", -+ a->addr, a->size, a->func, a->line, a->dma); -+ } -+} -+ -+/* The replacement functions */ -+void *dwc_alloc_debug(void *mem_ctx, uint32_t size, char const *func, int line) -+{ -+ void *addr = __DWC_ALLOC(mem_ctx, size); -+ -+ if (!addr) { -+ return NULL; -+ } -+ -+ if (add_allocation(mem_ctx, size, func, line, addr, 0)) { -+ __DWC_FREE(mem_ctx, addr); -+ return NULL; -+ } -+ -+ return addr; -+} -+ -+void *dwc_alloc_atomic_debug(void *mem_ctx, uint32_t size, char const *func, -+ int line) -+{ -+ void *addr = __DWC_ALLOC_ATOMIC(mem_ctx, size); -+ -+ if (!addr) { -+ return NULL; -+ } -+ -+ if (add_allocation(mem_ctx, size, func, line, addr, 0)) { -+ __DWC_FREE(mem_ctx, addr); -+ return NULL; -+ } -+ -+ return addr; -+} -+ -+void dwc_free_debug(void *mem_ctx, void *addr, char const *func, int line) -+{ -+ free_allocation(mem_ctx, addr, func, line); -+ __DWC_FREE(mem_ctx, addr); -+} -+ -+void *dwc_dma_alloc_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr, -+ char const *func, int line) -+{ -+ void *addr = __DWC_DMA_ALLOC(dma_ctx, size, dma_addr); -+ -+ if (!addr) { -+ return NULL; -+ } -+ -+ if (add_allocation(dma_ctx, size, func, line, addr, 1)) { -+ __DWC_DMA_FREE(dma_ctx, size, addr, *dma_addr); -+ return NULL; -+ } -+ -+ return addr; -+} -+ -+void *dwc_dma_alloc_atomic_debug(void *dma_ctx, uint32_t size, -+ dwc_dma_t *dma_addr, char const *func, int line) -+{ -+ void *addr = __DWC_DMA_ALLOC_ATOMIC(dma_ctx, size, dma_addr); -+ -+ if (!addr) { -+ return NULL; -+ } -+ -+ if (add_allocation(dma_ctx, size, func, line, addr, 1)) { -+ __DWC_DMA_FREE(dma_ctx, size, addr, *dma_addr); -+ return NULL; -+ } -+ -+ return addr; -+} -+ -+void dwc_dma_free_debug(void *dma_ctx, uint32_t size, void *virt_addr, -+ dwc_dma_t dma_addr, char const *func, int line) -+{ -+ free_allocation(dma_ctx, virt_addr, func, line); -+ __DWC_DMA_FREE(dma_ctx, size, virt_addr, dma_addr); -+} -+ -+#endif /* DWC_DEBUG_MEMORY */ -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_modpow.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_modpow.c ---- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_modpow.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_modpow.c 2015-11-29 09:42:39.915098960 +0100 -@@ -0,0 +1,636 @@ -+/* Bignum routines adapted from PUTTY sources. PuTTY copyright notice follows. -+ * -+ * PuTTY is copyright 1997-2007 Simon Tatham. -+ * -+ * Portions copyright Robert de Bath, Joris van Rantwijk, Delian -+ * Delchev, Andreas Schultz, Jeroen Massar, Wez Furlong, Nicolas Barry, -+ * Justin Bradford, Ben Harris, Malcolm Smith, Ahmad Khalifa, Markus -+ * Kuhn, and CORE SDI S.A. -+ * -+ * Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation files -+ * (the "Software"), to deal in the Software without restriction, -+ * including without limitation the rights to use, copy, modify, merge, -+ * publish, distribute, sublicense, and/or sell copies of the Software, -+ * and to permit persons to whom the Software is furnished to do so, -+ * subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE -+ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF -+ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -+ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -+ * -+ */ -+#ifdef DWC_CRYPTOLIB -+ -+#ifndef CONFIG_MACH_IPMATE -+ -+#include "dwc_modpow.h" -+ -+#define BIGNUM_INT_MASK 0xFFFFFFFFUL -+#define BIGNUM_TOP_BIT 0x80000000UL -+#define BIGNUM_INT_BITS 32 -+ -+ -+static void *snmalloc(void *mem_ctx, size_t n, size_t size) -+{ -+ void *p; -+ size *= n; -+ if (size == 0) size = 1; -+ p = dwc_alloc(mem_ctx, size); -+ return p; -+} -+ -+#define snewn(ctx, n, type) ((type *)snmalloc((ctx), (n), sizeof(type))) -+#define sfree dwc_free -+ -+/* -+ * Usage notes: -+ * * Do not call the DIVMOD_WORD macro with expressions such as array -+ * subscripts, as some implementations object to this (see below). -+ * * Note that none of the division methods below will cope if the -+ * quotient won't fit into BIGNUM_INT_BITS. Callers should be careful -+ * to avoid this case. -+ * If this condition occurs, in the case of the x86 DIV instruction, -+ * an overflow exception will occur, which (according to a correspondent) -+ * will manifest on Windows as something like -+ * 0xC0000095: Integer overflow -+ * The C variant won't give the right answer, either. -+ */ -+ -+#define MUL_WORD(w1, w2) ((BignumDblInt)w1 * w2) -+ -+#if defined __GNUC__ && defined __i386__ -+#define DIVMOD_WORD(q, r, hi, lo, w) \ -+ __asm__("div %2" : \ -+ "=d" (r), "=a" (q) : \ -+ "r" (w), "d" (hi), "a" (lo)) -+#else -+#define DIVMOD_WORD(q, r, hi, lo, w) do { \ -+ BignumDblInt n = (((BignumDblInt)hi) << BIGNUM_INT_BITS) | lo; \ -+ q = n / w; \ -+ r = n % w; \ -+} while (0) -+#endif -+ -+// q = n / w; -+// r = n % w; -+ -+#define BIGNUM_INT_BYTES (BIGNUM_INT_BITS / 8) -+ -+#define BIGNUM_INTERNAL -+ -+static Bignum newbn(void *mem_ctx, int length) -+{ -+ Bignum b = snewn(mem_ctx, length + 1, BignumInt); -+ //if (!b) -+ //abort(); /* FIXME */ -+ DWC_MEMSET(b, 0, (length + 1) * sizeof(*b)); -+ b[0] = length; -+ return b; -+} -+ -+void freebn(void *mem_ctx, Bignum b) -+{ -+ /* -+ * Burn the evidence, just in case. -+ */ -+ DWC_MEMSET(b, 0, sizeof(b[0]) * (b[0] + 1)); -+ sfree(mem_ctx, b); -+} -+ -+/* -+ * Compute c = a * b. -+ * Input is in the first len words of a and b. -+ * Result is returned in the first 2*len words of c. -+ */ -+static void internal_mul(BignumInt *a, BignumInt *b, -+ BignumInt *c, int len) -+{ -+ int i, j; -+ BignumDblInt t; -+ -+ for (j = 0; j < 2 * len; j++) -+ c[j] = 0; -+ -+ for (i = len - 1; i >= 0; i--) { -+ t = 0; -+ for (j = len - 1; j >= 0; j--) { -+ t += MUL_WORD(a[i], (BignumDblInt) b[j]); -+ t += (BignumDblInt) c[i + j + 1]; -+ c[i + j + 1] = (BignumInt) t; -+ t = t >> BIGNUM_INT_BITS; -+ } -+ c[i] = (BignumInt) t; -+ } -+} -+ -+static void internal_add_shifted(BignumInt *number, -+ unsigned n, int shift) -+{ -+ int word = 1 + (shift / BIGNUM_INT_BITS); -+ int bshift = shift % BIGNUM_INT_BITS; -+ BignumDblInt addend; -+ -+ addend = (BignumDblInt)n << bshift; -+ -+ while (addend) { -+ addend += number[word]; -+ number[word] = (BignumInt) addend & BIGNUM_INT_MASK; -+ addend >>= BIGNUM_INT_BITS; -+ word++; -+ } -+} -+ -+/* -+ * Compute a = a % m. -+ * Input in first alen words of a and first mlen words of m. -+ * Output in first alen words of a -+ * (of which first alen-mlen words will be zero). -+ * The MSW of m MUST have its high bit set. -+ * Quotient is accumulated in the `quotient' array, which is a Bignum -+ * rather than the internal bigendian format. Quotient parts are shifted -+ * left by `qshift' before adding into quot. -+ */ -+static void internal_mod(BignumInt *a, int alen, -+ BignumInt *m, int mlen, -+ BignumInt *quot, int qshift) -+{ -+ BignumInt m0, m1; -+ unsigned int h; -+ int i, k; -+ -+ m0 = m[0]; -+ if (mlen > 1) -+ m1 = m[1]; -+ else -+ m1 = 0; -+ -+ for (i = 0; i <= alen - mlen; i++) { -+ BignumDblInt t; -+ unsigned int q, r, c, ai1; -+ -+ if (i == 0) { -+ h = 0; -+ } else { -+ h = a[i - 1]; -+ a[i - 1] = 0; -+ } -+ -+ if (i == alen - 1) -+ ai1 = 0; -+ else -+ ai1 = a[i + 1]; -+ -+ /* Find q = h:a[i] / m0 */ -+ if (h >= m0) { -+ /* -+ * Special case. -+ * -+ * To illustrate it, suppose a BignumInt is 8 bits, and -+ * we are dividing (say) A1:23:45:67 by A1:B2:C3. Then -+ * our initial division will be 0xA123 / 0xA1, which -+ * will give a quotient of 0x100 and a divide overflow. -+ * However, the invariants in this division algorithm -+ * are not violated, since the full number A1:23:... is -+ * _less_ than the quotient prefix A1:B2:... and so the -+ * following correction loop would have sorted it out. -+ * -+ * In this situation we set q to be the largest -+ * quotient we _can_ stomach (0xFF, of course). -+ */ -+ q = BIGNUM_INT_MASK; -+ } else { -+ /* Macro doesn't want an array subscript expression passed -+ * into it (see definition), so use a temporary. */ -+ BignumInt tmplo = a[i]; -+ DIVMOD_WORD(q, r, h, tmplo, m0); -+ -+ /* Refine our estimate of q by looking at -+ h:a[i]:a[i+1] / m0:m1 */ -+ t = MUL_WORD(m1, q); -+ if (t > ((BignumDblInt) r << BIGNUM_INT_BITS) + ai1) { -+ q--; -+ t -= m1; -+ r = (r + m0) & BIGNUM_INT_MASK; /* overflow? */ -+ if (r >= (BignumDblInt) m0 && -+ t > ((BignumDblInt) r << BIGNUM_INT_BITS) + ai1) q--; -+ } -+ } -+ -+ /* Subtract q * m from a[i...] */ -+ c = 0; -+ for (k = mlen - 1; k >= 0; k--) { -+ t = MUL_WORD(q, m[k]); -+ t += c; -+ c = (unsigned)(t >> BIGNUM_INT_BITS); -+ if ((BignumInt) t > a[i + k]) -+ c++; -+ a[i + k] -= (BignumInt) t; -+ } -+ -+ /* Add back m in case of borrow */ -+ if (c != h) { -+ t = 0; -+ for (k = mlen - 1; k >= 0; k--) { -+ t += m[k]; -+ t += a[i + k]; -+ a[i + k] = (BignumInt) t; -+ t = t >> BIGNUM_INT_BITS; -+ } -+ q--; -+ } -+ if (quot) -+ internal_add_shifted(quot, q, qshift + BIGNUM_INT_BITS * (alen - mlen - i)); -+ } -+} -+ -+/* -+ * Compute p % mod. -+ * The most significant word of mod MUST be non-zero. -+ * We assume that the result array is the same size as the mod array. -+ * We optionally write out a quotient if `quotient' is non-NULL. -+ * We can avoid writing out the result if `result' is NULL. -+ */ -+void bigdivmod(void *mem_ctx, Bignum p, Bignum mod, Bignum result, Bignum quotient) -+{ -+ BignumInt *n, *m; -+ int mshift; -+ int plen, mlen, i, j; -+ -+ /* Allocate m of size mlen, copy mod to m */ -+ /* We use big endian internally */ -+ mlen = mod[0]; -+ m = snewn(mem_ctx, mlen, BignumInt); -+ //if (!m) -+ //abort(); /* FIXME */ -+ for (j = 0; j < mlen; j++) -+ m[j] = mod[mod[0] - j]; -+ -+ /* Shift m left to make msb bit set */ -+ for (mshift = 0; mshift < BIGNUM_INT_BITS-1; mshift++) -+ if ((m[0] << mshift) & BIGNUM_TOP_BIT) -+ break; -+ if (mshift) { -+ for (i = 0; i < mlen - 1; i++) -+ m[i] = (m[i] << mshift) | (m[i + 1] >> (BIGNUM_INT_BITS - mshift)); -+ m[mlen - 1] = m[mlen - 1] << mshift; -+ } -+ -+ plen = p[0]; -+ /* Ensure plen > mlen */ -+ if (plen <= mlen) -+ plen = mlen + 1; -+ -+ /* Allocate n of size plen, copy p to n */ -+ n = snewn(mem_ctx, plen, BignumInt); -+ //if (!n) -+ //abort(); /* FIXME */ -+ for (j = 0; j < plen; j++) -+ n[j] = 0; -+ for (j = 1; j <= (int)p[0]; j++) -+ n[plen - j] = p[j]; -+ -+ /* Main computation */ -+ internal_mod(n, plen, m, mlen, quotient, mshift); -+ -+ /* Fixup result in case the modulus was shifted */ -+ if (mshift) { -+ for (i = plen - mlen - 1; i < plen - 1; i++) -+ n[i] = (n[i] << mshift) | (n[i + 1] >> (BIGNUM_INT_BITS - mshift)); -+ n[plen - 1] = n[plen - 1] << mshift; -+ internal_mod(n, plen, m, mlen, quotient, 0); -+ for (i = plen - 1; i >= plen - mlen; i--) -+ n[i] = (n[i] >> mshift) | (n[i - 1] << (BIGNUM_INT_BITS - mshift)); -+ } -+ -+ /* Copy result to buffer */ -+ if (result) { -+ for (i = 1; i <= (int)result[0]; i++) { -+ int j = plen - i; -+ result[i] = j >= 0 ? n[j] : 0; -+ } -+ } -+ -+ /* Free temporary arrays */ -+ for (i = 0; i < mlen; i++) -+ m[i] = 0; -+ sfree(mem_ctx, m); -+ for (i = 0; i < plen; i++) -+ n[i] = 0; -+ sfree(mem_ctx, n); -+} -+ -+/* -+ * Simple remainder. -+ */ -+Bignum bigmod(void *mem_ctx, Bignum a, Bignum b) -+{ -+ Bignum r = newbn(mem_ctx, b[0]); -+ bigdivmod(mem_ctx, a, b, r, NULL); -+ return r; -+} -+ -+/* -+ * Compute (base ^ exp) % mod. -+ */ -+Bignum dwc_modpow(void *mem_ctx, Bignum base_in, Bignum exp, Bignum mod) -+{ -+ BignumInt *a, *b, *n, *m; -+ int mshift; -+ int mlen, i, j; -+ Bignum base, result; -+ -+ /* -+ * The most significant word of mod needs to be non-zero. It -+ * should already be, but let's make sure. -+ */ -+ //assert(mod[mod[0]] != 0); -+ -+ /* -+ * Make sure the base is smaller than the modulus, by reducing -+ * it modulo the modulus if not. -+ */ -+ base = bigmod(mem_ctx, base_in, mod); -+ -+ /* Allocate m of size mlen, copy mod to m */ -+ /* We use big endian internally */ -+ mlen = mod[0]; -+ m = snewn(mem_ctx, mlen, BignumInt); -+ //if (!m) -+ //abort(); /* FIXME */ -+ for (j = 0; j < mlen; j++) -+ m[j] = mod[mod[0] - j]; -+ -+ /* Shift m left to make msb bit set */ -+ for (mshift = 0; mshift < BIGNUM_INT_BITS - 1; mshift++) -+ if ((m[0] << mshift) & BIGNUM_TOP_BIT) -+ break; -+ if (mshift) { -+ for (i = 0; i < mlen - 1; i++) -+ m[i] = -+ (m[i] << mshift) | (m[i + 1] >> -+ (BIGNUM_INT_BITS - mshift)); -+ m[mlen - 1] = m[mlen - 1] << mshift; -+ } -+ -+ /* Allocate n of size mlen, copy base to n */ -+ n = snewn(mem_ctx, mlen, BignumInt); -+ //if (!n) -+ //abort(); /* FIXME */ -+ i = mlen - base[0]; -+ for (j = 0; j < i; j++) -+ n[j] = 0; -+ for (j = 0; j < base[0]; j++) -+ n[i + j] = base[base[0] - j]; -+ -+ /* Allocate a and b of size 2*mlen. Set a = 1 */ -+ a = snewn(mem_ctx, 2 * mlen, BignumInt); -+ //if (!a) -+ //abort(); /* FIXME */ -+ b = snewn(mem_ctx, 2 * mlen, BignumInt); -+ //if (!b) -+ //abort(); /* FIXME */ -+ for (i = 0; i < 2 * mlen; i++) -+ a[i] = 0; -+ a[2 * mlen - 1] = 1; -+ -+ /* Skip leading zero bits of exp. */ -+ i = 0; -+ j = BIGNUM_INT_BITS - 1; -+ while (i < exp[0] && (exp[exp[0] - i] & (1 << j)) == 0) { -+ j--; -+ if (j < 0) { -+ i++; -+ j = BIGNUM_INT_BITS - 1; -+ } -+ } -+ -+ /* Main computation */ -+ while (i < exp[0]) { -+ while (j >= 0) { -+ internal_mul(a + mlen, a + mlen, b, mlen); -+ internal_mod(b, mlen * 2, m, mlen, NULL, 0); -+ if ((exp[exp[0] - i] & (1 << j)) != 0) { -+ internal_mul(b + mlen, n, a, mlen); -+ internal_mod(a, mlen * 2, m, mlen, NULL, 0); -+ } else { -+ BignumInt *t; -+ t = a; -+ a = b; -+ b = t; -+ } -+ j--; -+ } -+ i++; -+ j = BIGNUM_INT_BITS - 1; -+ } -+ -+ /* Fixup result in case the modulus was shifted */ -+ if (mshift) { -+ for (i = mlen - 1; i < 2 * mlen - 1; i++) -+ a[i] = -+ (a[i] << mshift) | (a[i + 1] >> -+ (BIGNUM_INT_BITS - mshift)); -+ a[2 * mlen - 1] = a[2 * mlen - 1] << mshift; -+ internal_mod(a, mlen * 2, m, mlen, NULL, 0); -+ for (i = 2 * mlen - 1; i >= mlen; i--) -+ a[i] = -+ (a[i] >> mshift) | (a[i - 1] << -+ (BIGNUM_INT_BITS - mshift)); -+ } -+ -+ /* Copy result to buffer */ -+ result = newbn(mem_ctx, mod[0]); -+ for (i = 0; i < mlen; i++) -+ result[result[0] - i] = a[i + mlen]; -+ while (result[0] > 1 && result[result[0]] == 0) -+ result[0]--; -+ -+ /* Free temporary arrays */ -+ for (i = 0; i < 2 * mlen; i++) -+ a[i] = 0; -+ sfree(mem_ctx, a); -+ for (i = 0; i < 2 * mlen; i++) -+ b[i] = 0; -+ sfree(mem_ctx, b); -+ for (i = 0; i < mlen; i++) -+ m[i] = 0; -+ sfree(mem_ctx, m); -+ for (i = 0; i < mlen; i++) -+ n[i] = 0; -+ sfree(mem_ctx, n); -+ -+ freebn(mem_ctx, base); -+ -+ return result; -+} -+ -+ -+#ifdef UNITTEST -+ -+static __u32 dh_p[] = { -+ 96, -+ 0xFFFFFFFF, -+ 0xFFFFFFFF, -+ 0xA93AD2CA, -+ 0x4B82D120, -+ 0xE0FD108E, -+ 0x43DB5BFC, -+ 0x74E5AB31, -+ 0x08E24FA0, -+ 0xBAD946E2, -+ 0x770988C0, -+ 0x7A615D6C, -+ 0xBBE11757, -+ 0x177B200C, -+ 0x521F2B18, -+ 0x3EC86A64, -+ 0xD8760273, -+ 0xD98A0864, -+ 0xF12FFA06, -+ 0x1AD2EE6B, -+ 0xCEE3D226, -+ 0x4A25619D, -+ 0x1E8C94E0, -+ 0xDB0933D7, -+ 0xABF5AE8C, -+ 0xA6E1E4C7, -+ 0xB3970F85, -+ 0x5D060C7D, -+ 0x8AEA7157, -+ 0x58DBEF0A, -+ 0xECFB8504, -+ 0xDF1CBA64, -+ 0xA85521AB, -+ 0x04507A33, -+ 0xAD33170D, -+ 0x8AAAC42D, -+ 0x15728E5A, -+ 0x98FA0510, -+ 0x15D22618, -+ 0xEA956AE5, -+ 0x3995497C, -+ 0x95581718, -+ 0xDE2BCBF6, -+ 0x6F4C52C9, -+ 0xB5C55DF0, -+ 0xEC07A28F, -+ 0x9B2783A2, -+ 0x180E8603, -+ 0xE39E772C, -+ 0x2E36CE3B, -+ 0x32905E46, -+ 0xCA18217C, -+ 0xF1746C08, -+ 0x4ABC9804, -+ 0x670C354E, -+ 0x7096966D, -+ 0x9ED52907, -+ 0x208552BB, -+ 0x1C62F356, -+ 0xDCA3AD96, -+ 0x83655D23, -+ 0xFD24CF5F, -+ 0x69163FA8, -+ 0x1C55D39A, -+ 0x98DA4836, -+ 0xA163BF05, -+ 0xC2007CB8, -+ 0xECE45B3D, -+ 0x49286651, -+ 0x7C4B1FE6, -+ 0xAE9F2411, -+ 0x5A899FA5, -+ 0xEE386BFB, -+ 0xF406B7ED, -+ 0x0BFF5CB6, -+ 0xA637ED6B, -+ 0xF44C42E9, -+ 0x625E7EC6, -+ 0xE485B576, -+ 0x6D51C245, -+ 0x4FE1356D, -+ 0xF25F1437, -+ 0x302B0A6D, -+ 0xCD3A431B, -+ 0xEF9519B3, -+ 0x8E3404DD, -+ 0x514A0879, -+ 0x3B139B22, -+ 0x020BBEA6, -+ 0x8A67CC74, -+ 0x29024E08, -+ 0x80DC1CD1, -+ 0xC4C6628B, -+ 0x2168C234, -+ 0xC90FDAA2, -+ 0xFFFFFFFF, -+ 0xFFFFFFFF, -+}; -+ -+static __u32 dh_a[] = { -+ 8, -+ 0xdf367516, -+ 0x86459caa, -+ 0xe2d459a4, -+ 0xd910dae0, -+ 0x8a8b5e37, -+ 0x67ab31c6, -+ 0xf0b55ea9, -+ 0x440051d6, -+}; -+ -+static __u32 dh_b[] = { -+ 8, -+ 0xded92656, -+ 0xe07a048a, -+ 0x6fa452cd, -+ 0x2df89d30, -+ 0xc75f1b0f, -+ 0x8ce3578f, -+ 0x7980a324, -+ 0x5daec786, -+}; -+ -+static __u32 dh_g[] = { -+ 1, -+ 2, -+}; -+ -+int main(void) -+{ -+ int i; -+ __u32 *k; -+ k = dwc_modpow(NULL, dh_g, dh_a, dh_p); -+ -+ printf("\n\n"); -+ for (i=0; i> 16; -+ printf("%04x %04x ", m, l); -+ if (!((i + 1)%13)) printf("\n"); -+ } -+ printf("\n\n"); -+ -+ if ((k[0] == 0x60) && (k[1] == 0x28e490e5) && (k[0x60] == 0x5a0d3d4e)) { -+ printf("PASS\n\n"); -+ } -+ else { -+ printf("FAIL\n\n"); -+ } -+ -+} -+ -+#endif /* UNITTEST */ -+ -+#endif /* CONFIG_MACH_IPMATE */ -+ -+#endif /*DWC_CRYPTOLIB */ -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_modpow.h linux-rpi/drivers/usb/host/dwc_common_port/dwc_modpow.h ---- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_modpow.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_modpow.h 2015-11-29 09:42:39.915098960 +0100 -@@ -0,0 +1,34 @@ -+/* -+ * dwc_modpow.h -+ * See dwc_modpow.c for license and changes -+ */ -+#ifndef _DWC_MODPOW_H -+#define _DWC_MODPOW_H -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+#include "dwc_os.h" -+ -+/** @file -+ * -+ * This file defines the module exponentiation function which is only used -+ * internally by the DWC UWB modules for calculation of PKs during numeric -+ * association. The routine is taken from the PUTTY, an open source terminal -+ * emulator. The PUTTY License is preserved in the dwc_modpow.c file. -+ * -+ */ -+ -+typedef uint32_t BignumInt; -+typedef uint64_t BignumDblInt; -+typedef BignumInt *Bignum; -+ -+/* Compute modular exponentiaion */ -+extern Bignum dwc_modpow(void *mem_ctx, Bignum base_in, Bignum exp, Bignum mod); -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* _LINUX_BIGNUM_H */ -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_notifier.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_notifier.c ---- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_notifier.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_notifier.c 2015-11-29 09:42:39.915098960 +0100 -@@ -0,0 +1,319 @@ -+#ifdef DWC_NOTIFYLIB -+ -+#include "dwc_notifier.h" -+#include "dwc_list.h" -+ -+typedef struct dwc_observer { -+ void *observer; -+ dwc_notifier_callback_t callback; -+ void *data; -+ char *notification; -+ DWC_CIRCLEQ_ENTRY(dwc_observer) list_entry; -+} observer_t; -+ -+DWC_CIRCLEQ_HEAD(observer_queue, dwc_observer); -+ -+typedef struct dwc_notifier { -+ void *mem_ctx; -+ void *object; -+ struct observer_queue observers; -+ DWC_CIRCLEQ_ENTRY(dwc_notifier) list_entry; -+} notifier_t; -+ -+DWC_CIRCLEQ_HEAD(notifier_queue, dwc_notifier); -+ -+typedef struct manager { -+ void *mem_ctx; -+ void *wkq_ctx; -+ dwc_workq_t *wq; -+// dwc_mutex_t *mutex; -+ struct notifier_queue notifiers; -+} manager_t; -+ -+static manager_t *manager = NULL; -+ -+static int create_manager(void *mem_ctx, void *wkq_ctx) -+{ -+ manager = dwc_alloc(mem_ctx, sizeof(manager_t)); -+ if (!manager) { -+ return -DWC_E_NO_MEMORY; -+ } -+ -+ DWC_CIRCLEQ_INIT(&manager->notifiers); -+ -+ manager->wq = dwc_workq_alloc(wkq_ctx, "DWC Notification WorkQ"); -+ if (!manager->wq) { -+ return -DWC_E_NO_MEMORY; -+ } -+ -+ return 0; -+} -+ -+static void free_manager(void) -+{ -+ dwc_workq_free(manager->wq); -+ -+ /* All notifiers must have unregistered themselves before this module -+ * can be removed. Hitting this assertion indicates a programmer -+ * error. */ -+ DWC_ASSERT(DWC_CIRCLEQ_EMPTY(&manager->notifiers), -+ "Notification manager being freed before all notifiers have been removed"); -+ dwc_free(manager->mem_ctx, manager); -+} -+ -+#ifdef DEBUG -+static void dump_manager(void) -+{ -+ notifier_t *n; -+ observer_t *o; -+ -+ DWC_ASSERT(manager, "Notification manager not found"); -+ -+ DWC_DEBUG("List of all notifiers and observers:\n"); -+ DWC_CIRCLEQ_FOREACH(n, &manager->notifiers, list_entry) { -+ DWC_DEBUG("Notifier %p has observers:\n", n->object); -+ DWC_CIRCLEQ_FOREACH(o, &n->observers, list_entry) { -+ DWC_DEBUG(" %p watching %s\n", o->observer, o->notification); -+ } -+ } -+} -+#else -+#define dump_manager(...) -+#endif -+ -+static observer_t *alloc_observer(void *mem_ctx, void *observer, char *notification, -+ dwc_notifier_callback_t callback, void *data) -+{ -+ observer_t *new_observer = dwc_alloc(mem_ctx, sizeof(observer_t)); -+ -+ if (!new_observer) { -+ return NULL; -+ } -+ -+ DWC_CIRCLEQ_INIT_ENTRY(new_observer, list_entry); -+ new_observer->observer = observer; -+ new_observer->notification = notification; -+ new_observer->callback = callback; -+ new_observer->data = data; -+ return new_observer; -+} -+ -+static void free_observer(void *mem_ctx, observer_t *observer) -+{ -+ dwc_free(mem_ctx, observer); -+} -+ -+static notifier_t *alloc_notifier(void *mem_ctx, void *object) -+{ -+ notifier_t *notifier; -+ -+ if (!object) { -+ return NULL; -+ } -+ -+ notifier = dwc_alloc(mem_ctx, sizeof(notifier_t)); -+ if (!notifier) { -+ return NULL; -+ } -+ -+ DWC_CIRCLEQ_INIT(¬ifier->observers); -+ DWC_CIRCLEQ_INIT_ENTRY(notifier, list_entry); -+ -+ notifier->mem_ctx = mem_ctx; -+ notifier->object = object; -+ return notifier; -+} -+ -+static void free_notifier(notifier_t *notifier) -+{ -+ observer_t *observer; -+ -+ DWC_CIRCLEQ_FOREACH(observer, ¬ifier->observers, list_entry) { -+ free_observer(notifier->mem_ctx, observer); -+ } -+ -+ dwc_free(notifier->mem_ctx, notifier); -+} -+ -+static notifier_t *find_notifier(void *object) -+{ -+ notifier_t *notifier; -+ -+ DWC_ASSERT(manager, "Notification manager not found"); -+ -+ if (!object) { -+ return NULL; -+ } -+ -+ DWC_CIRCLEQ_FOREACH(notifier, &manager->notifiers, list_entry) { -+ if (notifier->object == object) { -+ return notifier; -+ } -+ } -+ -+ return NULL; -+} -+ -+int dwc_alloc_notification_manager(void *mem_ctx, void *wkq_ctx) -+{ -+ return create_manager(mem_ctx, wkq_ctx); -+} -+ -+void dwc_free_notification_manager(void) -+{ -+ free_manager(); -+} -+ -+dwc_notifier_t *dwc_register_notifier(void *mem_ctx, void *object) -+{ -+ notifier_t *notifier; -+ -+ DWC_ASSERT(manager, "Notification manager not found"); -+ -+ notifier = find_notifier(object); -+ if (notifier) { -+ DWC_ERROR("Notifier %p is already registered\n", object); -+ return NULL; -+ } -+ -+ notifier = alloc_notifier(mem_ctx, object); -+ if (!notifier) { -+ return NULL; -+ } -+ -+ DWC_CIRCLEQ_INSERT_TAIL(&manager->notifiers, notifier, list_entry); -+ -+ DWC_INFO("Notifier %p registered", object); -+ dump_manager(); -+ -+ return notifier; -+} -+ -+void dwc_unregister_notifier(dwc_notifier_t *notifier) -+{ -+ DWC_ASSERT(manager, "Notification manager not found"); -+ -+ if (!DWC_CIRCLEQ_EMPTY(¬ifier->observers)) { -+ observer_t *o; -+ -+ DWC_ERROR("Notifier %p has active observers when removing\n", notifier->object); -+ DWC_CIRCLEQ_FOREACH(o, ¬ifier->observers, list_entry) { -+ DWC_DEBUGC(" %p watching %s\n", o->observer, o->notification); -+ } -+ -+ DWC_ASSERT(DWC_CIRCLEQ_EMPTY(¬ifier->observers), -+ "Notifier %p has active observers when removing", notifier); -+ } -+ -+ DWC_CIRCLEQ_REMOVE_INIT(&manager->notifiers, notifier, list_entry); -+ free_notifier(notifier); -+ -+ DWC_INFO("Notifier unregistered"); -+ dump_manager(); -+} -+ -+/* Add an observer to observe the notifier for a particular state, event, or notification. */ -+int dwc_add_observer(void *observer, void *object, char *notification, -+ dwc_notifier_callback_t callback, void *data) -+{ -+ notifier_t *notifier = find_notifier(object); -+ observer_t *new_observer; -+ -+ if (!notifier) { -+ DWC_ERROR("Notifier %p is not found when adding observer\n", object); -+ return -DWC_E_INVALID; -+ } -+ -+ new_observer = alloc_observer(notifier->mem_ctx, observer, notification, callback, data); -+ if (!new_observer) { -+ return -DWC_E_NO_MEMORY; -+ } -+ -+ DWC_CIRCLEQ_INSERT_TAIL(¬ifier->observers, new_observer, list_entry); -+ -+ DWC_INFO("Added observer %p to notifier %p observing notification %s, callback=%p, data=%p", -+ observer, object, notification, callback, data); -+ -+ dump_manager(); -+ return 0; -+} -+ -+int dwc_remove_observer(void *observer) -+{ -+ notifier_t *n; -+ -+ DWC_ASSERT(manager, "Notification manager not found"); -+ -+ DWC_CIRCLEQ_FOREACH(n, &manager->notifiers, list_entry) { -+ observer_t *o; -+ observer_t *o2; -+ -+ DWC_CIRCLEQ_FOREACH_SAFE(o, o2, &n->observers, list_entry) { -+ if (o->observer == observer) { -+ DWC_CIRCLEQ_REMOVE_INIT(&n->observers, o, list_entry); -+ DWC_INFO("Removing observer %p from notifier %p watching notification %s:", -+ o->observer, n->object, o->notification); -+ free_observer(n->mem_ctx, o); -+ } -+ } -+ } -+ -+ dump_manager(); -+ return 0; -+} -+ -+typedef struct callback_data { -+ void *mem_ctx; -+ dwc_notifier_callback_t cb; -+ void *observer; -+ void *data; -+ void *object; -+ char *notification; -+ void *notification_data; -+} cb_data_t; -+ -+static void cb_task(void *data) -+{ -+ cb_data_t *cb = (cb_data_t *)data; -+ -+ cb->cb(cb->object, cb->notification, cb->observer, cb->notification_data, cb->data); -+ dwc_free(cb->mem_ctx, cb); -+} -+ -+void dwc_notify(dwc_notifier_t *notifier, char *notification, void *notification_data) -+{ -+ observer_t *o; -+ -+ DWC_ASSERT(manager, "Notification manager not found"); -+ -+ DWC_CIRCLEQ_FOREACH(o, ¬ifier->observers, list_entry) { -+ int len = DWC_STRLEN(notification); -+ -+ if (DWC_STRLEN(o->notification) != len) { -+ continue; -+ } -+ -+ if (DWC_STRNCMP(o->notification, notification, len) == 0) { -+ cb_data_t *cb_data = dwc_alloc(notifier->mem_ctx, sizeof(cb_data_t)); -+ -+ if (!cb_data) { -+ DWC_ERROR("Failed to allocate callback data\n"); -+ return; -+ } -+ -+ cb_data->mem_ctx = notifier->mem_ctx; -+ cb_data->cb = o->callback; -+ cb_data->observer = o->observer; -+ cb_data->data = o->data; -+ cb_data->object = notifier->object; -+ cb_data->notification = notification; -+ cb_data->notification_data = notification_data; -+ DWC_DEBUGC("Observer found %p for notification %s\n", o->observer, notification); -+ DWC_WORKQ_SCHEDULE(manager->wq, cb_task, cb_data, -+ "Notify callback from %p for Notification %s, to observer %p", -+ cb_data->object, notification, cb_data->observer); -+ } -+ } -+} -+ -+#endif /* DWC_NOTIFYLIB */ -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_notifier.h linux-rpi/drivers/usb/host/dwc_common_port/dwc_notifier.h ---- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_notifier.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_notifier.h 2015-11-29 09:42:39.915098960 +0100 -@@ -0,0 +1,122 @@ -+ -+#ifndef __DWC_NOTIFIER_H__ -+#define __DWC_NOTIFIER_H__ -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+#include "dwc_os.h" -+ -+/** @file -+ * -+ * A simple implementation of the Observer pattern. Any "module" can -+ * register as an observer or notifier. The notion of "module" is abstract and -+ * can mean anything used to identify either an observer or notifier. Usually -+ * it will be a pointer to a data structure which contains some state, ie an -+ * object. -+ * -+ * Before any notifiers can be added, the global notification manager must be -+ * brought up with dwc_alloc_notification_manager(). -+ * dwc_free_notification_manager() will bring it down and free all resources. -+ * These would typically be called upon module load and unload. The -+ * notification manager is a single global instance that handles all registered -+ * observable modules and observers so this should be done only once. -+ * -+ * A module can be observable by using Notifications to publicize some general -+ * information about it's state or operation. It does not care who listens, or -+ * even if anyone listens, or what they do with the information. The observable -+ * modules do not need to know any information about it's observers or their -+ * interface, or their state or data. -+ * -+ * Any module can register to emit Notifications. It should publish a list of -+ * notifications that it can emit and their behavior, such as when they will get -+ * triggered, and what information will be provided to the observer. Then it -+ * should register itself as an observable module. See dwc_register_notifier(). -+ * -+ * Any module can observe any observable, registered module, provided it has a -+ * handle to the other module and knows what notifications to observe. See -+ * dwc_add_observer(). -+ * -+ * A function of type dwc_notifier_callback_t is called whenever a notification -+ * is triggered with one or more observers observing it. This function is -+ * called in it's own process so it may sleep or block if needed. It is -+ * guaranteed to be called sometime after the notification has occurred and will -+ * be called once per each time the notification is triggered. It will NOT be -+ * called in the same process context used to trigger the notification. -+ * -+ * @section Limitiations -+ * -+ * Keep in mind that Notifications that can be triggered in rapid sucession may -+ * schedule too many processes too handle. Be aware of this limitation when -+ * designing to use notifications, and only add notifications for appropriate -+ * observable information. -+ * -+ * Also Notification callbacks are not synchronous. If you need to synchronize -+ * the behavior between module/observer you must use other means. And perhaps -+ * that will mean Notifications are not the proper solution. -+ */ -+ -+struct dwc_notifier; -+typedef struct dwc_notifier dwc_notifier_t; -+ -+/** The callback function must be of this type. -+ * -+ * @param object This is the object that is being observed. -+ * @param notification This is the notification that was triggered. -+ * @param observer This is the observer -+ * @param notification_data This is notification-specific data that the notifier -+ * has included in this notification. The value of this should be published in -+ * the documentation of the observable module with the notifications. -+ * @param user_data This is any custom data that the observer provided when -+ * adding itself as an observer to the notification. */ -+typedef void (*dwc_notifier_callback_t)(void *object, char *notification, void *observer, -+ void *notification_data, void *user_data); -+ -+/** Brings up the notification manager. */ -+extern int dwc_alloc_notification_manager(void *mem_ctx, void *wkq_ctx); -+/** Brings down the notification manager. */ -+extern void dwc_free_notification_manager(void); -+ -+/** This function registers an observable module. A dwc_notifier_t object is -+ * returned to the observable module. This is an opaque object that is used by -+ * the observable module to trigger notifications. This object should only be -+ * accessible to functions that are authorized to trigger notifications for this -+ * module. Observers do not need this object. */ -+extern dwc_notifier_t *dwc_register_notifier(void *mem_ctx, void *object); -+ -+/** This function unregisters an observable module. All observers have to be -+ * removed prior to unregistration. */ -+extern void dwc_unregister_notifier(dwc_notifier_t *notifier); -+ -+/** Add a module as an observer to the observable module. The observable module -+ * needs to have previously registered with the notification manager. -+ * -+ * @param observer The observer module -+ * @param object The module to observe -+ * @param notification The notification to observe -+ * @param callback The callback function to call -+ * @param user_data Any additional user data to pass into the callback function */ -+extern int dwc_add_observer(void *observer, void *object, char *notification, -+ dwc_notifier_callback_t callback, void *user_data); -+ -+/** Removes the specified observer from all notifications that it is currently -+ * observing. */ -+extern int dwc_remove_observer(void *observer); -+ -+/** This function triggers a Notification. It should be called by the -+ * observable module, or any module or library which the observable module -+ * allows to trigger notification on it's behalf. Such as the dwc_cc_t. -+ * -+ * dwc_notify is a non-blocking function. Callbacks are scheduled called in -+ * their own process context for each trigger. Callbacks can be blocking. -+ * dwc_notify can be called from interrupt context if needed. -+ * -+ */ -+void dwc_notify(dwc_notifier_t *notifier, char *notification, void *notification_data); -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* __DWC_NOTIFIER_H__ */ -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_os.h linux-rpi/drivers/usb/host/dwc_common_port/dwc_os.h ---- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_os.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_os.h 2015-11-29 09:42:39.915098960 +0100 -@@ -0,0 +1,1276 @@ -+/* ========================================================================= -+ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_os.h $ -+ * $Revision: #14 $ -+ * $Date: 2010/11/04 $ -+ * $Change: 1621695 $ -+ * -+ * Synopsys Portability Library Software and documentation -+ * (hereinafter, "Software") is an Unsupported proprietary work of -+ * Synopsys, Inc. unless otherwise expressly agreed to in writing -+ * between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product -+ * under any End User Software License Agreement or Agreement for -+ * Licensed Product with Synopsys or any supplement thereto. You are -+ * permitted to use and redistribute this Software in source and binary -+ * forms, with or without modification, provided that redistributions -+ * of source code must retain this notice. You may not view, use, -+ * disclose, copy or distribute this file or any information contained -+ * herein except pursuant to this license grant from Synopsys. If you -+ * do not agree with this notice, including the disclaimer below, then -+ * you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" -+ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -+ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL -+ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY -+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE -+ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================= */ -+#ifndef _DWC_OS_H_ -+#define _DWC_OS_H_ -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+/** @file -+ * -+ * DWC portability library, low level os-wrapper functions -+ * -+ */ -+ -+/* These basic types need to be defined by some OS header file or custom header -+ * file for your specific target architecture. -+ * -+ * uint8_t, int8_t, uint16_t, int16_t, uint32_t, int32_t, uint64_t, int64_t -+ * -+ * Any custom or alternate header file must be added and enabled here. -+ */ -+ -+#ifdef DWC_LINUX -+# include -+# ifdef CONFIG_DEBUG_MUTEXES -+# include -+# endif -+# include -+# include -+# include -+#endif -+ -+#if defined(DWC_FREEBSD) || defined(DWC_NETBSD) -+# include -+#endif -+ -+ -+/** @name Primitive Types and Values */ -+ -+/** We define a boolean type for consistency. Can be either YES or NO */ -+typedef uint8_t dwc_bool_t; -+#define YES 1 -+#define NO 0 -+ -+#ifdef DWC_LINUX -+ -+/** @name Error Codes */ -+#define DWC_E_INVALID EINVAL -+#define DWC_E_NO_MEMORY ENOMEM -+#define DWC_E_NO_DEVICE ENODEV -+#define DWC_E_NOT_SUPPORTED EOPNOTSUPP -+#define DWC_E_TIMEOUT ETIMEDOUT -+#define DWC_E_BUSY EBUSY -+#define DWC_E_AGAIN EAGAIN -+#define DWC_E_RESTART ERESTART -+#define DWC_E_ABORT ECONNABORTED -+#define DWC_E_SHUTDOWN ESHUTDOWN -+#define DWC_E_NO_DATA ENODATA -+#define DWC_E_DISCONNECT ECONNRESET -+#define DWC_E_UNKNOWN EINVAL -+#define DWC_E_NO_STREAM_RES ENOSR -+#define DWC_E_COMMUNICATION ECOMM -+#define DWC_E_OVERFLOW EOVERFLOW -+#define DWC_E_PROTOCOL EPROTO -+#define DWC_E_IN_PROGRESS EINPROGRESS -+#define DWC_E_PIPE EPIPE -+#define DWC_E_IO EIO -+#define DWC_E_NO_SPACE ENOSPC -+ -+#else -+ -+/** @name Error Codes */ -+#define DWC_E_INVALID 1001 -+#define DWC_E_NO_MEMORY 1002 -+#define DWC_E_NO_DEVICE 1003 -+#define DWC_E_NOT_SUPPORTED 1004 -+#define DWC_E_TIMEOUT 1005 -+#define DWC_E_BUSY 1006 -+#define DWC_E_AGAIN 1007 -+#define DWC_E_RESTART 1008 -+#define DWC_E_ABORT 1009 -+#define DWC_E_SHUTDOWN 1010 -+#define DWC_E_NO_DATA 1011 -+#define DWC_E_DISCONNECT 2000 -+#define DWC_E_UNKNOWN 3000 -+#define DWC_E_NO_STREAM_RES 4001 -+#define DWC_E_COMMUNICATION 4002 -+#define DWC_E_OVERFLOW 4003 -+#define DWC_E_PROTOCOL 4004 -+#define DWC_E_IN_PROGRESS 4005 -+#define DWC_E_PIPE 4006 -+#define DWC_E_IO 4007 -+#define DWC_E_NO_SPACE 4008 -+ -+#endif -+ -+ -+/** @name Tracing/Logging Functions -+ * -+ * These function provide the capability to add tracing, debugging, and error -+ * messages, as well exceptions as assertions. The WUDEV uses these -+ * extensively. These could be logged to the main console, the serial port, an -+ * internal buffer, etc. These functions could also be no-op if they are too -+ * expensive on your system. By default undefining the DEBUG macro already -+ * no-ops some of these functions. */ -+ -+/** Returns non-zero if in interrupt context. */ -+extern dwc_bool_t DWC_IN_IRQ(void); -+#define dwc_in_irq DWC_IN_IRQ -+ -+/** Returns "IRQ" if DWC_IN_IRQ is true. */ -+static inline char *dwc_irq(void) { -+ return DWC_IN_IRQ() ? "IRQ" : ""; -+} -+ -+/** Returns non-zero if in bottom-half context. */ -+extern dwc_bool_t DWC_IN_BH(void); -+#define dwc_in_bh DWC_IN_BH -+ -+/** Returns "BH" if DWC_IN_BH is true. */ -+static inline char *dwc_bh(void) { -+ return DWC_IN_BH() ? "BH" : ""; -+} -+ -+/** -+ * A vprintf() clone. Just call vprintf if you've got it. -+ */ -+extern void DWC_VPRINTF(char *format, va_list args); -+#define dwc_vprintf DWC_VPRINTF -+ -+/** -+ * A vsnprintf() clone. Just call vprintf if you've got it. -+ */ -+extern int DWC_VSNPRINTF(char *str, int size, char *format, va_list args); -+#define dwc_vsnprintf DWC_VSNPRINTF -+ -+/** -+ * printf() clone. Just call printf if you've go it. -+ */ -+extern void DWC_PRINTF(char *format, ...) -+/* This provides compiler level static checking of the parameters if you're -+ * using GCC. */ -+#ifdef __GNUC__ -+ __attribute__ ((format(printf, 1, 2))); -+#else -+ ; -+#endif -+#define dwc_printf DWC_PRINTF -+ -+/** -+ * sprintf() clone. Just call sprintf if you've got it. -+ */ -+extern int DWC_SPRINTF(char *string, char *format, ...) -+#ifdef __GNUC__ -+ __attribute__ ((format(printf, 2, 3))); -+#else -+ ; -+#endif -+#define dwc_sprintf DWC_SPRINTF -+ -+/** -+ * snprintf() clone. Just call snprintf if you've got it. -+ */ -+extern int DWC_SNPRINTF(char *string, int size, char *format, ...) -+#ifdef __GNUC__ -+ __attribute__ ((format(printf, 3, 4))); -+#else -+ ; -+#endif -+#define dwc_snprintf DWC_SNPRINTF -+ -+/** -+ * Prints a WARNING message. On systems that don't differentiate between -+ * warnings and regular log messages, just print it. Indicates that something -+ * may be wrong with the driver. Works like printf(). -+ * -+ * Use the DWC_WARN macro to call this function. -+ */ -+extern void __DWC_WARN(char *format, ...) -+#ifdef __GNUC__ -+ __attribute__ ((format(printf, 1, 2))); -+#else -+ ; -+#endif -+ -+/** -+ * Prints an error message. On systems that don't differentiate between errors -+ * and regular log messages, just print it. Indicates that something went wrong -+ * with the driver. Works like printf(). -+ * -+ * Use the DWC_ERROR macro to call this function. -+ */ -+extern void __DWC_ERROR(char *format, ...) -+#ifdef __GNUC__ -+ __attribute__ ((format(printf, 1, 2))); -+#else -+ ; -+#endif -+ -+/** -+ * Prints an exception error message and takes some user-defined action such as -+ * print out a backtrace or trigger a breakpoint. Indicates that something went -+ * abnormally wrong with the driver such as programmer error, or other -+ * exceptional condition. It should not be ignored so even on systems without -+ * printing capability, some action should be taken to notify the developer of -+ * it. Works like printf(). -+ */ -+extern void DWC_EXCEPTION(char *format, ...) -+#ifdef __GNUC__ -+ __attribute__ ((format(printf, 1, 2))); -+#else -+ ; -+#endif -+#define dwc_exception DWC_EXCEPTION -+ -+#ifndef DWC_OTG_DEBUG_LEV -+#define DWC_OTG_DEBUG_LEV 0 -+#endif -+ -+#ifdef DEBUG -+/** -+ * Prints out a debug message. Used for logging/trace messages. -+ * -+ * Use the DWC_DEBUG macro to call this function -+ */ -+extern void __DWC_DEBUG(char *format, ...) -+#ifdef __GNUC__ -+ __attribute__ ((format(printf, 1, 2))); -+#else -+ ; -+#endif -+#else -+#define __DWC_DEBUG printk -+#endif -+ -+/** -+ * Prints out a Debug message. -+ */ -+#define DWC_DEBUG(_format, _args...) __DWC_DEBUG("DEBUG:%s:%s: " _format "\n", \ -+ __func__, dwc_irq(), ## _args) -+#define dwc_debug DWC_DEBUG -+/** -+ * Prints out a Debug message if enabled at compile time. -+ */ -+#if DWC_OTG_DEBUG_LEV > 0 -+#define DWC_DEBUGC(_format, _args...) DWC_DEBUG(_format, ##_args ) -+#else -+#define DWC_DEBUGC(_format, _args...) -+#endif -+#define dwc_debugc DWC_DEBUGC -+/** -+ * Prints out an informative message. -+ */ -+#define DWC_INFO(_format, _args...) DWC_PRINTF("INFO:%s: " _format "\n", \ -+ dwc_irq(), ## _args) -+#define dwc_info DWC_INFO -+/** -+ * Prints out an informative message if enabled at compile time. -+ */ -+#if DWC_OTG_DEBUG_LEV > 1 -+#define DWC_INFOC(_format, _args...) DWC_INFO(_format, ##_args ) -+#else -+#define DWC_INFOC(_format, _args...) -+#endif -+#define dwc_infoc DWC_INFOC -+/** -+ * Prints out a warning message. -+ */ -+#define DWC_WARN(_format, _args...) __DWC_WARN("WARN:%s:%s:%d: " _format "\n", \ -+ dwc_irq(), __func__, __LINE__, ## _args) -+#define dwc_warn DWC_WARN -+/** -+ * Prints out an error message. -+ */ -+#define DWC_ERROR(_format, _args...) __DWC_ERROR("ERROR:%s:%s:%d: " _format "\n", \ -+ dwc_irq(), __func__, __LINE__, ## _args) -+#define dwc_error DWC_ERROR -+ -+#define DWC_PROTO_ERROR(_format, _args...) __DWC_WARN("ERROR:%s:%s:%d: " _format "\n", \ -+ dwc_irq(), __func__, __LINE__, ## _args) -+#define dwc_proto_error DWC_PROTO_ERROR -+ -+#ifdef DEBUG -+/** Prints out a exception error message if the _expr expression fails. Disabled -+ * if DEBUG is not enabled. */ -+#define DWC_ASSERT(_expr, _format, _args...) do { \ -+ if (!(_expr)) { DWC_EXCEPTION("%s:%s:%d: " _format "\n", dwc_irq(), \ -+ __FILE__, __LINE__, ## _args); } \ -+ } while (0) -+#else -+#define DWC_ASSERT(_x...) -+#endif -+#define dwc_assert DWC_ASSERT -+ -+ -+/** @name Byte Ordering -+ * The following functions are for conversions between processor's byte ordering -+ * and specific ordering you want. -+ */ -+ -+/** Converts 32 bit data in CPU byte ordering to little endian. */ -+extern uint32_t DWC_CPU_TO_LE32(uint32_t *p); -+#define dwc_cpu_to_le32 DWC_CPU_TO_LE32 -+ -+/** Converts 32 bit data in CPU byte orderint to big endian. */ -+extern uint32_t DWC_CPU_TO_BE32(uint32_t *p); -+#define dwc_cpu_to_be32 DWC_CPU_TO_BE32 -+ -+/** Converts 32 bit little endian data to CPU byte ordering. */ -+extern uint32_t DWC_LE32_TO_CPU(uint32_t *p); -+#define dwc_le32_to_cpu DWC_LE32_TO_CPU -+ -+/** Converts 32 bit big endian data to CPU byte ordering. */ -+extern uint32_t DWC_BE32_TO_CPU(uint32_t *p); -+#define dwc_be32_to_cpu DWC_BE32_TO_CPU -+ -+/** Converts 16 bit data in CPU byte ordering to little endian. */ -+extern uint16_t DWC_CPU_TO_LE16(uint16_t *p); -+#define dwc_cpu_to_le16 DWC_CPU_TO_LE16 -+ -+/** Converts 16 bit data in CPU byte orderint to big endian. */ -+extern uint16_t DWC_CPU_TO_BE16(uint16_t *p); -+#define dwc_cpu_to_be16 DWC_CPU_TO_BE16 -+ -+/** Converts 16 bit little endian data to CPU byte ordering. */ -+extern uint16_t DWC_LE16_TO_CPU(uint16_t *p); -+#define dwc_le16_to_cpu DWC_LE16_TO_CPU -+ -+/** Converts 16 bit bi endian data to CPU byte ordering. */ -+extern uint16_t DWC_BE16_TO_CPU(uint16_t *p); -+#define dwc_be16_to_cpu DWC_BE16_TO_CPU -+ -+ -+/** @name Register Read/Write -+ * -+ * The following six functions should be implemented to read/write registers of -+ * 32-bit and 64-bit sizes. All modules use this to read/write register values. -+ * The reg value is a pointer to the register calculated from the void *base -+ * variable passed into the driver when it is started. */ -+ -+#ifdef DWC_LINUX -+/* Linux doesn't need any extra parameters for register read/write, so we -+ * just throw away the IO context parameter. -+ */ -+/** Reads the content of a 32-bit register. */ -+extern uint32_t DWC_READ_REG32(uint32_t volatile *reg); -+#define dwc_read_reg32(_ctx_,_reg_) DWC_READ_REG32(_reg_) -+ -+/** Reads the content of a 64-bit register. */ -+extern uint64_t DWC_READ_REG64(uint64_t volatile *reg); -+#define dwc_read_reg64(_ctx_,_reg_) DWC_READ_REG64(_reg_) -+ -+/** Writes to a 32-bit register. */ -+extern void DWC_WRITE_REG32(uint32_t volatile *reg, uint32_t value); -+#define dwc_write_reg32(_ctx_,_reg_,_val_) DWC_WRITE_REG32(_reg_, _val_) -+ -+/** Writes to a 64-bit register. */ -+extern void DWC_WRITE_REG64(uint64_t volatile *reg, uint64_t value); -+#define dwc_write_reg64(_ctx_,_reg_,_val_) DWC_WRITE_REG64(_reg_, _val_) -+ -+/** -+ * Modify bit values in a register. Using the -+ * algorithm: (reg_contents & ~clear_mask) | set_mask. -+ */ -+extern void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask); -+#define dwc_modify_reg32(_ctx_,_reg_,_cmsk_,_smsk_) DWC_MODIFY_REG32(_reg_,_cmsk_,_smsk_) -+extern void DWC_MODIFY_REG64(uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask); -+#define dwc_modify_reg64(_ctx_,_reg_,_cmsk_,_smsk_) DWC_MODIFY_REG64(_reg_,_cmsk_,_smsk_) -+ -+#endif /* DWC_LINUX */ -+ -+#if defined(DWC_FREEBSD) || defined(DWC_NETBSD) -+typedef struct dwc_ioctx { -+ struct device *dev; -+ bus_space_tag_t iot; -+ bus_space_handle_t ioh; -+} dwc_ioctx_t; -+ -+/** BSD needs two extra parameters for register read/write, so we pass -+ * them in using the IO context parameter. -+ */ -+/** Reads the content of a 32-bit register. */ -+extern uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg); -+#define dwc_read_reg32 DWC_READ_REG32 -+ -+/** Reads the content of a 64-bit register. */ -+extern uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg); -+#define dwc_read_reg64 DWC_READ_REG64 -+ -+/** Writes to a 32-bit register. */ -+extern void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value); -+#define dwc_write_reg32 DWC_WRITE_REG32 -+ -+/** Writes to a 64-bit register. */ -+extern void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value); -+#define dwc_write_reg64 DWC_WRITE_REG64 -+ -+/** -+ * Modify bit values in a register. Using the -+ * algorithm: (reg_contents & ~clear_mask) | set_mask. -+ */ -+extern void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask); -+#define dwc_modify_reg32 DWC_MODIFY_REG32 -+extern void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask); -+#define dwc_modify_reg64 DWC_MODIFY_REG64 -+ -+#endif /* DWC_FREEBSD || DWC_NETBSD */ -+ -+/** @cond */ -+ -+/** @name Some convenience MACROS used internally. Define DWC_DEBUG_REGS to log the -+ * register writes. */ -+ -+#ifdef DWC_LINUX -+ -+# ifdef DWC_DEBUG_REGS -+ -+#define dwc_define_read_write_reg_n(_reg,_container_type) \ -+static inline uint32_t dwc_read_##_reg##_n(_container_type *container, int num) { \ -+ return DWC_READ_REG32(&container->regs->_reg[num]); \ -+} \ -+static inline void dwc_write_##_reg##_n(_container_type *container, int num, uint32_t data) { \ -+ DWC_DEBUG("WRITING %8s[%d]: %p: %08x", #_reg, num, \ -+ &(((uint32_t*)container->regs->_reg)[num]), data); \ -+ DWC_WRITE_REG32(&(((uint32_t*)container->regs->_reg)[num]), data); \ -+} -+ -+#define dwc_define_read_write_reg(_reg,_container_type) \ -+static inline uint32_t dwc_read_##_reg(_container_type *container) { \ -+ return DWC_READ_REG32(&container->regs->_reg); \ -+} \ -+static inline void dwc_write_##_reg(_container_type *container, uint32_t data) { \ -+ DWC_DEBUG("WRITING %11s: %p: %08x", #_reg, &container->regs->_reg, data); \ -+ DWC_WRITE_REG32(&container->regs->_reg, data); \ -+} -+ -+# else /* DWC_DEBUG_REGS */ -+ -+#define dwc_define_read_write_reg_n(_reg,_container_type) \ -+static inline uint32_t dwc_read_##_reg##_n(_container_type *container, int num) { \ -+ return DWC_READ_REG32(&container->regs->_reg[num]); \ -+} \ -+static inline void dwc_write_##_reg##_n(_container_type *container, int num, uint32_t data) { \ -+ DWC_WRITE_REG32(&(((uint32_t*)container->regs->_reg)[num]), data); \ -+} -+ -+#define dwc_define_read_write_reg(_reg,_container_type) \ -+static inline uint32_t dwc_read_##_reg(_container_type *container) { \ -+ return DWC_READ_REG32(&container->regs->_reg); \ -+} \ -+static inline void dwc_write_##_reg(_container_type *container, uint32_t data) { \ -+ DWC_WRITE_REG32(&container->regs->_reg, data); \ -+} -+ -+# endif /* DWC_DEBUG_REGS */ -+ -+#endif /* DWC_LINUX */ -+ -+#if defined(DWC_FREEBSD) || defined(DWC_NETBSD) -+ -+# ifdef DWC_DEBUG_REGS -+ -+#define dwc_define_read_write_reg_n(_reg,_container_type) \ -+static inline uint32_t dwc_read_##_reg##_n(void *io_ctx, _container_type *container, int num) { \ -+ return DWC_READ_REG32(io_ctx, &container->regs->_reg[num]); \ -+} \ -+static inline void dwc_write_##_reg##_n(void *io_ctx, _container_type *container, int num, uint32_t data) { \ -+ DWC_DEBUG("WRITING %8s[%d]: %p: %08x", #_reg, num, \ -+ &(((uint32_t*)container->regs->_reg)[num]), data); \ -+ DWC_WRITE_REG32(io_ctx, &(((uint32_t*)container->regs->_reg)[num]), data); \ -+} -+ -+#define dwc_define_read_write_reg(_reg,_container_type) \ -+static inline uint32_t dwc_read_##_reg(void *io_ctx, _container_type *container) { \ -+ return DWC_READ_REG32(io_ctx, &container->regs->_reg); \ -+} \ -+static inline void dwc_write_##_reg(void *io_ctx, _container_type *container, uint32_t data) { \ -+ DWC_DEBUG("WRITING %11s: %p: %08x", #_reg, &container->regs->_reg, data); \ -+ DWC_WRITE_REG32(io_ctx, &container->regs->_reg, data); \ -+} -+ -+# else /* DWC_DEBUG_REGS */ -+ -+#define dwc_define_read_write_reg_n(_reg,_container_type) \ -+static inline uint32_t dwc_read_##_reg##_n(void *io_ctx, _container_type *container, int num) { \ -+ return DWC_READ_REG32(io_ctx, &container->regs->_reg[num]); \ -+} \ -+static inline void dwc_write_##_reg##_n(void *io_ctx, _container_type *container, int num, uint32_t data) { \ -+ DWC_WRITE_REG32(io_ctx, &(((uint32_t*)container->regs->_reg)[num]), data); \ -+} -+ -+#define dwc_define_read_write_reg(_reg,_container_type) \ -+static inline uint32_t dwc_read_##_reg(void *io_ctx, _container_type *container) { \ -+ return DWC_READ_REG32(io_ctx, &container->regs->_reg); \ -+} \ -+static inline void dwc_write_##_reg(void *io_ctx, _container_type *container, uint32_t data) { \ -+ DWC_WRITE_REG32(io_ctx, &container->regs->_reg, data); \ -+} -+ -+# endif /* DWC_DEBUG_REGS */ -+ -+#endif /* DWC_FREEBSD || DWC_NETBSD */ -+ -+/** @endcond */ -+ -+ -+#ifdef DWC_CRYPTOLIB -+/** @name Crypto Functions -+ * -+ * These are the low-level cryptographic functions used by the driver. */ -+ -+/** Perform AES CBC */ -+extern int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out); -+#define dwc_aes_cbc DWC_AES_CBC -+ -+/** Fill the provided buffer with random bytes. These should be cryptographic grade random numbers. */ -+extern void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length); -+#define dwc_random_bytes DWC_RANDOM_BYTES -+ -+/** Perform the SHA-256 hash function */ -+extern int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out); -+#define dwc_sha256 DWC_SHA256 -+ -+/** Calculated the HMAC-SHA256 */ -+extern int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t *out); -+#define dwc_hmac_sha256 DWC_HMAC_SHA256 -+ -+#endif /* DWC_CRYPTOLIB */ -+ -+ -+/** @name Memory Allocation -+ * -+ * These function provide access to memory allocation. There are only 2 DMA -+ * functions and 3 Regular memory functions that need to be implemented. None -+ * of the memory debugging routines need to be implemented. The allocation -+ * routines all ZERO the contents of the memory. -+ * -+ * Defining DWC_DEBUG_MEMORY turns on memory debugging and statistic gathering. -+ * This checks for memory leaks, keeping track of alloc/free pairs. It also -+ * keeps track of how much memory the driver is using at any given time. */ -+ -+#define DWC_PAGE_SIZE 4096 -+#define DWC_PAGE_OFFSET(addr) (((uint32_t)addr) & 0xfff) -+#define DWC_PAGE_ALIGNED(addr) ((((uint32_t)addr) & 0xfff) == 0) -+ -+#define DWC_INVALID_DMA_ADDR 0x0 -+ -+#ifdef DWC_LINUX -+/** Type for a DMA address */ -+typedef dma_addr_t dwc_dma_t; -+#endif -+ -+#if defined(DWC_FREEBSD) || defined(DWC_NETBSD) -+typedef bus_addr_t dwc_dma_t; -+#endif -+ -+#ifdef DWC_FREEBSD -+typedef struct dwc_dmactx { -+ struct device *dev; -+ bus_dma_tag_t dma_tag; -+ bus_dmamap_t dma_map; -+ bus_addr_t dma_paddr; -+ void *dma_vaddr; -+} dwc_dmactx_t; -+#endif -+ -+#ifdef DWC_NETBSD -+typedef struct dwc_dmactx { -+ struct device *dev; -+ bus_dma_tag_t dma_tag; -+ bus_dmamap_t dma_map; -+ bus_dma_segment_t segs[1]; -+ int nsegs; -+ bus_addr_t dma_paddr; -+ void *dma_vaddr; -+} dwc_dmactx_t; -+#endif -+ -+/* @todo these functions will be added in the future */ -+#if 0 -+/** -+ * Creates a DMA pool from which you can allocate DMA buffers. Buffers -+ * allocated from this pool will be guaranteed to meet the size, alignment, and -+ * boundary requirements specified. -+ * -+ * @param[in] size Specifies the size of the buffers that will be allocated from -+ * this pool. -+ * @param[in] align Specifies the byte alignment requirements of the buffers -+ * allocated from this pool. Must be a power of 2. -+ * @param[in] boundary Specifies the N-byte boundary that buffers allocated from -+ * this pool must not cross. -+ * -+ * @returns A pointer to an internal opaque structure which is not to be -+ * accessed outside of these library functions. Use this handle to specify -+ * which pools to allocate/free DMA buffers from and also to destroy the pool, -+ * when you are done with it. -+ */ -+extern dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size, uint32_t align, uint32_t boundary); -+ -+/** -+ * Destroy a DMA pool. All buffers allocated from that pool must be freed first. -+ */ -+extern void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool); -+ -+/** -+ * Allocate a buffer from the specified DMA pool and zeros its contents. -+ */ -+extern void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr); -+ -+/** -+ * Free a previously allocated buffer from the DMA pool. -+ */ -+extern void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr); -+#endif -+ -+/** Allocates a DMA capable buffer and zeroes its contents. */ -+extern void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr); -+ -+/** Allocates a DMA capable buffer and zeroes its contents in atomic contest */ -+extern void *__DWC_DMA_ALLOC_ATOMIC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr); -+ -+/** Frees a previously allocated buffer. */ -+extern void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr); -+ -+/** Allocates a block of memory and zeroes its contents. */ -+extern void *__DWC_ALLOC(void *mem_ctx, uint32_t size); -+ -+/** Allocates a block of memory and zeroes its contents, in an atomic manner -+ * which can be used inside interrupt context. The size should be sufficiently -+ * small, a few KB at most, such that failures are not likely to occur. Can just call -+ * __DWC_ALLOC if it is atomic. */ -+extern void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size); -+ -+/** Frees a previously allocated buffer. */ -+extern void __DWC_FREE(void *mem_ctx, void *addr); -+ -+#ifndef DWC_DEBUG_MEMORY -+ -+#define DWC_ALLOC(_size_) __DWC_ALLOC(NULL, _size_) -+#define DWC_ALLOC_ATOMIC(_size_) __DWC_ALLOC_ATOMIC(NULL, _size_) -+#define DWC_FREE(_addr_) __DWC_FREE(NULL, _addr_) -+ -+# ifdef DWC_LINUX -+#define DWC_DMA_ALLOC(_size_,_dma_) __DWC_DMA_ALLOC(NULL, _size_, _dma_) -+#define DWC_DMA_ALLOC_ATOMIC(_size_,_dma_) __DWC_DMA_ALLOC_ATOMIC(NULL, _size_,_dma_) -+#define DWC_DMA_FREE(_size_,_virt_,_dma_) __DWC_DMA_FREE(NULL, _size_, _virt_, _dma_) -+# endif -+ -+# if defined(DWC_FREEBSD) || defined(DWC_NETBSD) -+#define DWC_DMA_ALLOC __DWC_DMA_ALLOC -+#define DWC_DMA_FREE __DWC_DMA_FREE -+# endif -+extern void *dwc_dma_alloc_atomic_debug(uint32_t size, dwc_dma_t *dma_addr, char const *func, int line); -+ -+#else /* DWC_DEBUG_MEMORY */ -+ -+extern void *dwc_alloc_debug(void *mem_ctx, uint32_t size, char const *func, int line); -+extern void *dwc_alloc_atomic_debug(void *mem_ctx, uint32_t size, char const *func, int line); -+extern void dwc_free_debug(void *mem_ctx, void *addr, char const *func, int line); -+extern void *dwc_dma_alloc_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr, -+ char const *func, int line); -+extern void *dwc_dma_alloc_atomic_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr, -+ char const *func, int line); -+extern void dwc_dma_free_debug(void *dma_ctx, uint32_t size, void *virt_addr, -+ dwc_dma_t dma_addr, char const *func, int line); -+ -+extern int dwc_memory_debug_start(void *mem_ctx); -+extern void dwc_memory_debug_stop(void); -+extern void dwc_memory_debug_report(void); -+ -+#define DWC_ALLOC(_size_) dwc_alloc_debug(NULL, _size_, __func__, __LINE__) -+#define DWC_ALLOC_ATOMIC(_size_) dwc_alloc_atomic_debug(NULL, _size_, \ -+ __func__, __LINE__) -+#define DWC_FREE(_addr_) dwc_free_debug(NULL, _addr_, __func__, __LINE__) -+ -+# ifdef DWC_LINUX -+#define DWC_DMA_ALLOC(_size_,_dma_) dwc_dma_alloc_debug(NULL, _size_, \ -+ _dma_, __func__, __LINE__) -+#define DWC_DMA_ALLOC_ATOMIC(_size_,_dma_) dwc_dma_alloc_atomic_debug(NULL, _size_, \ -+ _dma_, __func__, __LINE__) -+#define DWC_DMA_FREE(_size_,_virt_,_dma_) dwc_dma_free_debug(NULL, _size_, \ -+ _virt_, _dma_, __func__, __LINE__) -+# endif -+ -+# if defined(DWC_FREEBSD) || defined(DWC_NETBSD) -+#define DWC_DMA_ALLOC(_ctx_,_size_,_dma_) dwc_dma_alloc_debug(_ctx_, _size_, \ -+ _dma_, __func__, __LINE__) -+#define DWC_DMA_FREE(_ctx_,_size_,_virt_,_dma_) dwc_dma_free_debug(_ctx_, _size_, \ -+ _virt_, _dma_, __func__, __LINE__) -+# endif -+ -+#endif /* DWC_DEBUG_MEMORY */ -+ -+#define dwc_alloc(_ctx_,_size_) DWC_ALLOC(_size_) -+#define dwc_alloc_atomic(_ctx_,_size_) DWC_ALLOC_ATOMIC(_size_) -+#define dwc_free(_ctx_,_addr_) DWC_FREE(_addr_) -+ -+#ifdef DWC_LINUX -+/* Linux doesn't need any extra parameters for DMA buffer allocation, so we -+ * just throw away the DMA context parameter. -+ */ -+#define dwc_dma_alloc(_ctx_,_size_,_dma_) DWC_DMA_ALLOC(_size_, _dma_) -+#define dwc_dma_alloc_atomic(_ctx_,_size_,_dma_) DWC_DMA_ALLOC_ATOMIC(_size_, _dma_) -+#define dwc_dma_free(_ctx_,_size_,_virt_,_dma_) DWC_DMA_FREE(_size_, _virt_, _dma_) -+#endif -+ -+#if defined(DWC_FREEBSD) || defined(DWC_NETBSD) -+/** BSD needs several extra parameters for DMA buffer allocation, so we pass -+ * them in using the DMA context parameter. -+ */ -+#define dwc_dma_alloc DWC_DMA_ALLOC -+#define dwc_dma_free DWC_DMA_FREE -+#endif -+ -+ -+/** @name Memory and String Processing */ -+ -+/** memset() clone */ -+extern void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size); -+#define dwc_memset DWC_MEMSET -+ -+/** memcpy() clone */ -+extern void *DWC_MEMCPY(void *dest, void const *src, uint32_t size); -+#define dwc_memcpy DWC_MEMCPY -+ -+/** memmove() clone */ -+extern void *DWC_MEMMOVE(void *dest, void *src, uint32_t size); -+#define dwc_memmove DWC_MEMMOVE -+ -+/** memcmp() clone */ -+extern int DWC_MEMCMP(void *m1, void *m2, uint32_t size); -+#define dwc_memcmp DWC_MEMCMP -+ -+/** strcmp() clone */ -+extern int DWC_STRCMP(void *s1, void *s2); -+#define dwc_strcmp DWC_STRCMP -+ -+/** strncmp() clone */ -+extern int DWC_STRNCMP(void *s1, void *s2, uint32_t size); -+#define dwc_strncmp DWC_STRNCMP -+ -+/** strlen() clone, for NULL terminated ASCII strings */ -+extern int DWC_STRLEN(char const *str); -+#define dwc_strlen DWC_STRLEN -+ -+/** strcpy() clone, for NULL terminated ASCII strings */ -+extern char *DWC_STRCPY(char *to, const char *from); -+#define dwc_strcpy DWC_STRCPY -+ -+/** strdup() clone. If you wish to use memory allocation debugging, this -+ * implementation of strdup should use the DWC_* memory routines instead of -+ * calling a predefined strdup. Otherwise the memory allocated by this routine -+ * will not be seen by the debugging routines. */ -+extern char *DWC_STRDUP(char const *str); -+#define dwc_strdup(_ctx_,_str_) DWC_STRDUP(_str_) -+ -+/** NOT an atoi() clone. Read the description carefully. Returns an integer -+ * converted from the string str in base 10 unless the string begins with a "0x" -+ * in which case it is base 16. String must be a NULL terminated sequence of -+ * ASCII characters and may optionally begin with whitespace, a + or -, and a -+ * "0x" prefix if base 16. The remaining characters must be valid digits for -+ * the number and end with a NULL character. If any invalid characters are -+ * encountered or it returns with a negative error code and the results of the -+ * conversion are undefined. On sucess it returns 0. Overflow conditions are -+ * undefined. An example implementation using atoi() can be referenced from the -+ * Linux implementation. */ -+extern int DWC_ATOI(const char *str, int32_t *value); -+#define dwc_atoi DWC_ATOI -+ -+/** Same as above but for unsigned. */ -+extern int DWC_ATOUI(const char *str, uint32_t *value); -+#define dwc_atoui DWC_ATOUI -+ -+#ifdef DWC_UTFLIB -+/** This routine returns a UTF16LE unicode encoded string from a UTF8 string. */ -+extern int DWC_UTF8_TO_UTF16LE(uint8_t const *utf8string, uint16_t *utf16string, unsigned len); -+#define dwc_utf8_to_utf16le DWC_UTF8_TO_UTF16LE -+#endif -+ -+ -+/** @name Wait queues -+ * -+ * Wait queues provide a means of synchronizing between threads or processes. A -+ * process can block on a waitq if some condition is not true, waiting for it to -+ * become true. When the waitq is triggered all waiting process will get -+ * unblocked and the condition will be check again. Waitqs should be triggered -+ * every time a condition can potentially change.*/ -+struct dwc_waitq; -+ -+/** Type for a waitq */ -+typedef struct dwc_waitq dwc_waitq_t; -+ -+/** The type of waitq condition callback function. This is called every time -+ * condition is evaluated. */ -+typedef int (*dwc_waitq_condition_t)(void *data); -+ -+/** Allocate a waitq */ -+extern dwc_waitq_t *DWC_WAITQ_ALLOC(void); -+#define dwc_waitq_alloc(_ctx_) DWC_WAITQ_ALLOC() -+ -+/** Free a waitq */ -+extern void DWC_WAITQ_FREE(dwc_waitq_t *wq); -+#define dwc_waitq_free DWC_WAITQ_FREE -+ -+/** Check the condition and if it is false, block on the waitq. When unblocked, check the -+ * condition again. The function returns when the condition becomes true. The return value -+ * is 0 on condition true, DWC_WAITQ_ABORTED on abort or killed, or DWC_WAITQ_UNKNOWN on error. */ -+extern int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data); -+#define dwc_waitq_wait DWC_WAITQ_WAIT -+ -+/** Check the condition and if it is false, block on the waitq. When unblocked, -+ * check the condition again. The function returns when the condition become -+ * true or the timeout has passed. The return value is 0 on condition true or -+ * DWC_TIMED_OUT on timeout, or DWC_WAITQ_ABORTED, or DWC_WAITQ_UNKNOWN on -+ * error. */ -+extern int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, -+ void *data, int32_t msecs); -+#define dwc_waitq_wait_timeout DWC_WAITQ_WAIT_TIMEOUT -+ -+/** Trigger a waitq, unblocking all processes. This should be called whenever a condition -+ * has potentially changed. */ -+extern void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq); -+#define dwc_waitq_trigger DWC_WAITQ_TRIGGER -+ -+/** Unblock all processes waiting on the waitq with an ABORTED result. */ -+extern void DWC_WAITQ_ABORT(dwc_waitq_t *wq); -+#define dwc_waitq_abort DWC_WAITQ_ABORT -+ -+ -+/** @name Threads -+ * -+ * A thread must be explicitly stopped. It must check DWC_THREAD_SHOULD_STOP -+ * whenever it is woken up, and then return. The DWC_THREAD_STOP function -+ * returns the value from the thread. -+ */ -+ -+struct dwc_thread; -+ -+/** Type for a thread */ -+typedef struct dwc_thread dwc_thread_t; -+ -+/** The thread function */ -+typedef int (*dwc_thread_function_t)(void *data); -+ -+/** Create a thread and start it running the thread_function. Returns a handle -+ * to the thread */ -+extern dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data); -+#define dwc_thread_run(_ctx_,_func_,_name_,_data_) DWC_THREAD_RUN(_func_, _name_, _data_) -+ -+/** Stops a thread. Return the value returned by the thread. Or will return -+ * DWC_ABORT if the thread never started. */ -+extern int DWC_THREAD_STOP(dwc_thread_t *thread); -+#define dwc_thread_stop DWC_THREAD_STOP -+ -+/** Signifies to the thread that it must stop. */ -+#ifdef DWC_LINUX -+/* Linux doesn't need any parameters for kthread_should_stop() */ -+extern dwc_bool_t DWC_THREAD_SHOULD_STOP(void); -+#define dwc_thread_should_stop(_thrd_) DWC_THREAD_SHOULD_STOP() -+ -+/* No thread_exit function in Linux */ -+#define dwc_thread_exit(_thrd_) -+#endif -+ -+#if defined(DWC_FREEBSD) || defined(DWC_NETBSD) -+/** BSD needs the thread pointer for kthread_suspend_check() */ -+extern dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread); -+#define dwc_thread_should_stop DWC_THREAD_SHOULD_STOP -+ -+/** The thread must call this to exit. */ -+extern void DWC_THREAD_EXIT(dwc_thread_t *thread); -+#define dwc_thread_exit DWC_THREAD_EXIT -+#endif -+ -+ -+/** @name Work queues -+ * -+ * Workqs are used to queue a callback function to be called at some later time, -+ * in another thread. */ -+struct dwc_workq; -+ -+/** Type for a workq */ -+typedef struct dwc_workq dwc_workq_t; -+ -+/** The type of the callback function to be called. */ -+typedef void (*dwc_work_callback_t)(void *data); -+ -+/** Allocate a workq */ -+extern dwc_workq_t *DWC_WORKQ_ALLOC(char *name); -+#define dwc_workq_alloc(_ctx_,_name_) DWC_WORKQ_ALLOC(_name_) -+ -+/** Free a workq. All work must be completed before being freed. */ -+extern void DWC_WORKQ_FREE(dwc_workq_t *workq); -+#define dwc_workq_free DWC_WORKQ_FREE -+ -+/** Schedule a callback on the workq, passing in data. The function will be -+ * scheduled at some later time. */ -+extern void DWC_WORKQ_SCHEDULE(dwc_workq_t *workq, dwc_work_callback_t cb, -+ void *data, char *format, ...) -+#ifdef __GNUC__ -+ __attribute__ ((format(printf, 4, 5))); -+#else -+ ; -+#endif -+#define dwc_workq_schedule DWC_WORKQ_SCHEDULE -+ -+/** Schedule a callback on the workq, that will be called until at least -+ * given number miliseconds have passed. */ -+extern void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *workq, dwc_work_callback_t cb, -+ void *data, uint32_t time, char *format, ...) -+#ifdef __GNUC__ -+ __attribute__ ((format(printf, 5, 6))); -+#else -+ ; -+#endif -+#define dwc_workq_schedule_delayed DWC_WORKQ_SCHEDULE_DELAYED -+ -+/** The number of processes in the workq */ -+extern int DWC_WORKQ_PENDING(dwc_workq_t *workq); -+#define dwc_workq_pending DWC_WORKQ_PENDING -+ -+/** Blocks until all the work in the workq is complete or timed out. Returns < -+ * 0 on timeout. */ -+extern int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout); -+#define dwc_workq_wait_work_done DWC_WORKQ_WAIT_WORK_DONE -+ -+ -+/** @name Tasklets -+ * -+ */ -+struct dwc_tasklet; -+ -+/** Type for a tasklet */ -+typedef struct dwc_tasklet dwc_tasklet_t; -+ -+/** The type of the callback function to be called */ -+typedef void (*dwc_tasklet_callback_t)(void *data); -+ -+/** Allocates a tasklet */ -+extern dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data); -+#define dwc_task_alloc(_ctx_,_name_,_cb_,_data_) DWC_TASK_ALLOC(_name_, _cb_, _data_) -+ -+/** Frees a tasklet */ -+extern void DWC_TASK_FREE(dwc_tasklet_t *task); -+#define dwc_task_free DWC_TASK_FREE -+ -+/** Schedules a tasklet to run */ -+extern void DWC_TASK_SCHEDULE(dwc_tasklet_t *task); -+#define dwc_task_schedule DWC_TASK_SCHEDULE -+ -+extern void DWC_TASK_HI_SCHEDULE(dwc_tasklet_t *task); -+#define dwc_task_hi_schedule DWC_TASK_HI_SCHEDULE -+ -+/** @name Timer -+ * -+ * Callbacks must be small and atomic. -+ */ -+struct dwc_timer; -+ -+/** Type for a timer */ -+typedef struct dwc_timer dwc_timer_t; -+ -+/** The type of the callback function to be called */ -+typedef void (*dwc_timer_callback_t)(void *data); -+ -+/** Allocates a timer */ -+extern dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data); -+#define dwc_timer_alloc(_ctx_,_name_,_cb_,_data_) DWC_TIMER_ALLOC(_name_,_cb_,_data_) -+ -+/** Frees a timer */ -+extern void DWC_TIMER_FREE(dwc_timer_t *timer); -+#define dwc_timer_free DWC_TIMER_FREE -+ -+/** Schedules the timer to run at time ms from now. And will repeat at every -+ * repeat_interval msec therafter -+ * -+ * Modifies a timer that is still awaiting execution to a new expiration time. -+ * The mod_time is added to the old time. */ -+extern void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time); -+#define dwc_timer_schedule DWC_TIMER_SCHEDULE -+ -+/** Disables the timer from execution. */ -+extern void DWC_TIMER_CANCEL(dwc_timer_t *timer); -+#define dwc_timer_cancel DWC_TIMER_CANCEL -+ -+ -+/** @name Spinlocks -+ * -+ * These locks are used when the work between the lock/unlock is atomic and -+ * short. Interrupts are also disabled during the lock/unlock and thus they are -+ * suitable to lock between interrupt/non-interrupt context. They also lock -+ * between processes if you have multiple CPUs or Preemption. If you don't have -+ * multiple CPUS or Preemption, then the you can simply implement the -+ * DWC_SPINLOCK and DWC_SPINUNLOCK to disable and enable interrupts. Because -+ * the work between the lock/unlock is atomic, the process context will never -+ * change, and so you never have to lock between processes. */ -+ -+struct dwc_spinlock; -+ -+/** Type for a spinlock */ -+typedef struct dwc_spinlock dwc_spinlock_t; -+ -+/** Type for the 'flags' argument to spinlock funtions */ -+typedef unsigned long dwc_irqflags_t; -+ -+/** Returns an initialized lock variable. This function should allocate and -+ * initialize the OS-specific data structure used for locking. This data -+ * structure is to be used for the DWC_LOCK and DWC_UNLOCK functions and should -+ * be freed by the DWC_FREE_LOCK when it is no longer used. -+ * -+ * For Linux Spinlock Debugging make it macro because the debugging routines use -+ * the symbol name to determine recursive locking. Using a wrapper function -+ * makes it falsely think recursive locking occurs. */ -+#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK) -+#define DWC_SPINLOCK_ALLOC_LINUX_DEBUG(lock) ({ \ -+ lock = DWC_ALLOC(sizeof(spinlock_t)); \ -+ if (lock) { \ -+ spin_lock_init((spinlock_t *)lock); \ -+ } \ -+}) -+#else -+extern dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void); -+#define dwc_spinlock_alloc(_ctx_) DWC_SPINLOCK_ALLOC() -+#endif -+ -+/** Frees an initialized lock variable. */ -+extern void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock); -+#define dwc_spinlock_free(_ctx_,_lock_) DWC_SPINLOCK_FREE(_lock_) -+ -+/** Disables interrupts and blocks until it acquires the lock. -+ * -+ * @param lock Pointer to the spinlock. -+ * @param flags Unsigned long for irq flags storage. -+ */ -+extern void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags); -+#define dwc_spinlock_irqsave DWC_SPINLOCK_IRQSAVE -+ -+/** Re-enables the interrupt and releases the lock. -+ * -+ * @param lock Pointer to the spinlock. -+ * @param flags Unsigned long for irq flags storage. Must be the same as was -+ * passed into DWC_LOCK. -+ */ -+extern void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags); -+#define dwc_spinunlock_irqrestore DWC_SPINUNLOCK_IRQRESTORE -+ -+/** Blocks until it acquires the lock. -+ * -+ * @param lock Pointer to the spinlock. -+ */ -+extern void DWC_SPINLOCK(dwc_spinlock_t *lock); -+#define dwc_spinlock DWC_SPINLOCK -+ -+/** Releases the lock. -+ * -+ * @param lock Pointer to the spinlock. -+ */ -+extern void DWC_SPINUNLOCK(dwc_spinlock_t *lock); -+#define dwc_spinunlock DWC_SPINUNLOCK -+ -+ -+/** @name Mutexes -+ * -+ * Unlike spinlocks Mutexes lock only between processes and the work between the -+ * lock/unlock CAN block, therefore it CANNOT be called from interrupt context. -+ */ -+ -+struct dwc_mutex; -+ -+/** Type for a mutex */ -+typedef struct dwc_mutex dwc_mutex_t; -+ -+/* For Linux Mutex Debugging make it inline because the debugging routines use -+ * the symbol to determine recursive locking. This makes it falsely think -+ * recursive locking occurs. */ -+#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES) -+#define DWC_MUTEX_ALLOC_LINUX_DEBUG(__mutexp) ({ \ -+ __mutexp = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mutex)); \ -+ mutex_init((struct mutex *)__mutexp); \ -+}) -+#endif -+ -+/** Allocate a mutex */ -+extern dwc_mutex_t *DWC_MUTEX_ALLOC(void); -+#define dwc_mutex_alloc(_ctx_) DWC_MUTEX_ALLOC() -+ -+/* For memory leak debugging when using Linux Mutex Debugging */ -+#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES) -+#define DWC_MUTEX_FREE(__mutexp) do { \ -+ mutex_destroy((struct mutex *)__mutexp); \ -+ DWC_FREE(__mutexp); \ -+} while(0) -+#else -+/** Free a mutex */ -+extern void DWC_MUTEX_FREE(dwc_mutex_t *mutex); -+#define dwc_mutex_free(_ctx_,_mutex_) DWC_MUTEX_FREE(_mutex_) -+#endif -+ -+/** Lock a mutex */ -+extern void DWC_MUTEX_LOCK(dwc_mutex_t *mutex); -+#define dwc_mutex_lock DWC_MUTEX_LOCK -+ -+/** Non-blocking lock returns 1 on successful lock. */ -+extern int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex); -+#define dwc_mutex_trylock DWC_MUTEX_TRYLOCK -+ -+/** Unlock a mutex */ -+extern void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex); -+#define dwc_mutex_unlock DWC_MUTEX_UNLOCK -+ -+ -+/** @name Time */ -+ -+/** Microsecond delay. -+ * -+ * @param usecs Microseconds to delay. -+ */ -+extern void DWC_UDELAY(uint32_t usecs); -+#define dwc_udelay DWC_UDELAY -+ -+/** Millisecond delay. -+ * -+ * @param msecs Milliseconds to delay. -+ */ -+extern void DWC_MDELAY(uint32_t msecs); -+#define dwc_mdelay DWC_MDELAY -+ -+/** Non-busy waiting. -+ * Sleeps for specified number of milliseconds. -+ * -+ * @param msecs Milliseconds to sleep. -+ */ -+extern void DWC_MSLEEP(uint32_t msecs); -+#define dwc_msleep DWC_MSLEEP -+ -+/** -+ * Returns number of milliseconds since boot. -+ */ -+extern uint32_t DWC_TIME(void); -+#define dwc_time DWC_TIME -+ -+ -+ -+ -+/* @mainpage DWC Portability and Common Library -+ * -+ * This is the documentation for the DWC Portability and Common Library. -+ * -+ * @section intro Introduction -+ * -+ * The DWC Portability library consists of wrapper calls and data structures to -+ * all low-level functions which are typically provided by the OS. The WUDEV -+ * driver uses only these functions. In order to port the WUDEV driver, only -+ * the functions in this library need to be re-implemented, with the same -+ * behavior as documented here. -+ * -+ * The Common library consists of higher level functions, which rely only on -+ * calling the functions from the DWC Portability library. These common -+ * routines are shared across modules. Some of the common libraries need to be -+ * used directly by the driver programmer when porting WUDEV. Such as the -+ * parameter and notification libraries. -+ * -+ * @section low Portability Library OS Wrapper Functions -+ * -+ * Any function starting with DWC and in all CAPS is a low-level OS-wrapper that -+ * needs to be implemented when porting, for example DWC_MUTEX_ALLOC(). All of -+ * these functions are included in the dwc_os.h file. -+ * -+ * There are many functions here covering a wide array of OS services. Please -+ * see dwc_os.h for details, and implementation notes for each function. -+ * -+ * @section common Common Library Functions -+ * -+ * Any function starting with dwc and in all lowercase is a common library -+ * routine. These functions have a portable implementation and do not need to -+ * be reimplemented when porting. The common routines can be used by any -+ * driver, and some must be used by the end user to control the drivers. For -+ * example, you must use the Parameter common library in order to set the -+ * parameters in the WUDEV module. -+ * -+ * The common libraries consist of the following: -+ * -+ * - Connection Contexts - Used internally and can be used by end-user. See dwc_cc.h -+ * - Parameters - Used internally and can be used by end-user. See dwc_params.h -+ * - Notifications - Used internally and can be used by end-user. See dwc_notifier.h -+ * - Lists - Used internally and can be used by end-user. See dwc_list.h -+ * - Memory Debugging - Used internally and can be used by end-user. See dwc_os.h -+ * - Modpow - Used internally only. See dwc_modpow.h -+ * - DH - Used internally only. See dwc_dh.h -+ * - Crypto - Used internally only. See dwc_crypto.h -+ * -+ * -+ * @section prereq Prerequistes For dwc_os.h -+ * @subsection types Data Types -+ * -+ * The dwc_os.h file assumes that several low-level data types are pre defined for the -+ * compilation environment. These data types are: -+ * -+ * - uint8_t - unsigned 8-bit data type -+ * - int8_t - signed 8-bit data type -+ * - uint16_t - unsigned 16-bit data type -+ * - int16_t - signed 16-bit data type -+ * - uint32_t - unsigned 32-bit data type -+ * - int32_t - signed 32-bit data type -+ * - uint64_t - unsigned 64-bit data type -+ * - int64_t - signed 64-bit data type -+ * -+ * Ensure that these are defined before using dwc_os.h. The easiest way to do -+ * that is to modify the top of the file to include the appropriate header. -+ * This is already done for the Linux environment. If the DWC_LINUX macro is -+ * defined, the correct header will be added. A standard header is -+ * also used for environments where standard C headers are available. -+ * -+ * @subsection stdarg Variable Arguments -+ * -+ * Variable arguments are provided by a standard C header . it is -+ * available in Both the Linux and ANSI C enviornment. An equivalent must be -+ * provided in your enviornment in order to use dwc_os.h with the debug and -+ * tracing message functionality. -+ * -+ * @subsection thread Threading -+ * -+ * WUDEV Core must be run on an operating system that provides for multiple -+ * threads/processes. Threading can be implemented in many ways, even in -+ * embedded systems without an operating system. At the bare minimum, the -+ * system should be able to start any number of processes at any time to handle -+ * special work. It need not be a pre-emptive system. Process context can -+ * change upon a call to a blocking function. The hardware interrupt context -+ * that calls the module's ISR() function must be differentiable from process -+ * context, even if your processes are impemented via a hardware interrupt. -+ * Further locking mechanism between process must exist (or be implemented), and -+ * process context must have a way to disable interrupts for a period of time to -+ * lock them out. If all of this exists, the functions in dwc_os.h related to -+ * threading should be able to be implemented with the defined behavior. -+ * -+ */ -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* _DWC_OS_H_ */ -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/Makefile linux-rpi/drivers/usb/host/dwc_common_port/Makefile ---- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_common_port/Makefile 2015-11-29 09:42:39.915098960 +0100 -@@ -0,0 +1,58 @@ -+# -+# Makefile for DWC_common library -+# -+ -+ifneq ($(KERNELRELEASE),) -+ -+ccflags-y += -DDWC_LINUX -+#ccflags-y += -DDEBUG -+#ccflags-y += -DDWC_DEBUG_REGS -+#ccflags-y += -DDWC_DEBUG_MEMORY -+ -+ccflags-y += -DDWC_LIBMODULE -+ccflags-y += -DDWC_CCLIB -+#ccflags-y += -DDWC_CRYPTOLIB -+ccflags-y += -DDWC_NOTIFYLIB -+ccflags-y += -DDWC_UTFLIB -+ -+obj-$(CONFIG_USB_DWCOTG) += dwc_common_port_lib.o -+dwc_common_port_lib-objs := dwc_cc.o dwc_modpow.o dwc_dh.o \ -+ dwc_crypto.o dwc_notifier.o \ -+ dwc_common_linux.o dwc_mem.o -+ -+kernrelwd := $(subst ., ,$(KERNELRELEASE)) -+kernrel3 := $(word 1,$(kernrelwd)).$(word 2,$(kernrelwd)).$(word 3,$(kernrelwd)) -+ -+ifneq ($(kernrel3),2.6.20) -+# grayg - I only know that we use ccflags-y in 2.6.31 actually -+ccflags-y += $(CPPFLAGS) -+endif -+ -+else -+ -+#ifeq ($(KDIR),) -+#$(error Must give "KDIR=/path/to/kernel/source" on command line or in environment) -+#endif -+ -+ifeq ($(ARCH),) -+$(error Must give "ARCH=" on command line or in environment. Also, if \ -+ cross-compiling, must give "CROSS_COMPILE=/path/to/compiler/plus/tool-prefix-") -+endif -+ -+ifeq ($(DOXYGEN),) -+DOXYGEN := doxygen -+endif -+ -+default: -+ $(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules -+ -+docs: $(wildcard *.[hc]) doc/doxygen.cfg -+ $(DOXYGEN) doc/doxygen.cfg -+ -+tags: $(wildcard *.[hc]) -+ $(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h) -+ -+endif -+ -+clean: -+ rm -rf *.o *.ko .*.cmd *.mod.c .*.o.d .*.o.tmp modules.order Module.markers Module.symvers .tmp_versions/ -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/Makefile.fbsd linux-rpi/drivers/usb/host/dwc_common_port/Makefile.fbsd ---- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/Makefile.fbsd 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_common_port/Makefile.fbsd 2015-11-29 09:42:39.915098960 +0100 -@@ -0,0 +1,17 @@ -+CFLAGS += -I/sys/i386/compile/GENERIC -I/sys/i386/include -I/usr/include -+CFLAGS += -DDWC_FREEBSD -+CFLAGS += -DDEBUG -+#CFLAGS += -DDWC_DEBUG_REGS -+#CFLAGS += -DDWC_DEBUG_MEMORY -+ -+#CFLAGS += -DDWC_LIBMODULE -+#CFLAGS += -DDWC_CCLIB -+#CFLAGS += -DDWC_CRYPTOLIB -+#CFLAGS += -DDWC_NOTIFYLIB -+#CFLAGS += -DDWC_UTFLIB -+ -+KMOD = dwc_common_port_lib -+SRCS = dwc_cc.c dwc_modpow.c dwc_dh.c dwc_crypto.c dwc_notifier.c \ -+ dwc_common_fbsd.c dwc_mem.c -+ -+.include -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/Makefile.linux linux-rpi/drivers/usb/host/dwc_common_port/Makefile.linux ---- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/Makefile.linux 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_common_port/Makefile.linux 2015-11-29 09:42:39.915098960 +0100 -@@ -0,0 +1,49 @@ -+# -+# Makefile for DWC_common library -+# -+ifneq ($(KERNELRELEASE),) -+ -+ccflags-y += -DDWC_LINUX -+#ccflags-y += -DDEBUG -+#ccflags-y += -DDWC_DEBUG_REGS -+#ccflags-y += -DDWC_DEBUG_MEMORY -+ -+ccflags-y += -DDWC_LIBMODULE -+ccflags-y += -DDWC_CCLIB -+ccflags-y += -DDWC_CRYPTOLIB -+ccflags-y += -DDWC_NOTIFYLIB -+ccflags-y += -DDWC_UTFLIB -+ -+obj-m := dwc_common_port_lib.o -+dwc_common_port_lib-objs := dwc_cc.o dwc_modpow.o dwc_dh.o \ -+ dwc_crypto.o dwc_notifier.o \ -+ dwc_common_linux.o dwc_mem.o -+ -+else -+ -+ifeq ($(KDIR),) -+$(error Must give "KDIR=/path/to/kernel/source" on command line or in environment) -+endif -+ -+ifeq ($(ARCH),) -+$(error Must give "ARCH=" on command line or in environment. Also, if \ -+ cross-compiling, must give "CROSS_COMPILE=/path/to/compiler/plus/tool-prefix-") -+endif -+ -+ifeq ($(DOXYGEN),) -+DOXYGEN := doxygen -+endif -+ -+default: -+ $(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules -+ -+docs: $(wildcard *.[hc]) doc/doxygen.cfg -+ $(DOXYGEN) doc/doxygen.cfg -+ -+tags: $(wildcard *.[hc]) -+ $(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h) -+ -+endif -+ -+clean: -+ rm -rf *.o *.ko .*.cmd *.mod.c .*.o.d .*.o.tmp modules.order Module.markers Module.symvers .tmp_versions/ -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/usb.h linux-rpi/drivers/usb/host/dwc_common_port/usb.h ---- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/usb.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_common_port/usb.h 2015-11-29 09:42:39.915098960 +0100 -@@ -0,0 +1,946 @@ -+/* -+ * Copyright (c) 1998 The NetBSD Foundation, Inc. -+ * All rights reserved. -+ * -+ * This code is derived from software contributed to The NetBSD Foundation -+ * by Lennart Augustsson (lennart@augustsson.net) at -+ * Carlstedt Research & Technology. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. All advertising materials mentioning features or use of this software -+ * must display the following acknowledgement: -+ * This product includes software developed by the NetBSD -+ * Foundation, Inc. and its contributors. -+ * 4. Neither the name of The NetBSD Foundation nor the names of its -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS -+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS -+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+/* Modified by Synopsys, Inc, 12/12/2007 */ -+ -+ -+#ifndef _USB_H_ -+#define _USB_H_ -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+/* -+ * The USB records contain some unaligned little-endian word -+ * components. The U[SG]ETW macros take care of both the alignment -+ * and endian problem and should always be used to access non-byte -+ * values. -+ */ -+typedef u_int8_t uByte; -+typedef u_int8_t uWord[2]; -+typedef u_int8_t uDWord[4]; -+ -+#define USETW2(w,h,l) ((w)[0] = (u_int8_t)(l), (w)[1] = (u_int8_t)(h)) -+#define UCONSTW(x) { (x) & 0xff, ((x) >> 8) & 0xff } -+#define UCONSTDW(x) { (x) & 0xff, ((x) >> 8) & 0xff, \ -+ ((x) >> 16) & 0xff, ((x) >> 24) & 0xff } -+ -+#if 1 -+#define UGETW(w) ((w)[0] | ((w)[1] << 8)) -+#define USETW(w,v) ((w)[0] = (u_int8_t)(v), (w)[1] = (u_int8_t)((v) >> 8)) -+#define UGETDW(w) ((w)[0] | ((w)[1] << 8) | ((w)[2] << 16) | ((w)[3] << 24)) -+#define USETDW(w,v) ((w)[0] = (u_int8_t)(v), \ -+ (w)[1] = (u_int8_t)((v) >> 8), \ -+ (w)[2] = (u_int8_t)((v) >> 16), \ -+ (w)[3] = (u_int8_t)((v) >> 24)) -+#else -+/* -+ * On little-endian machines that can handle unanliged accesses -+ * (e.g. i386) these macros can be replaced by the following. -+ */ -+#define UGETW(w) (*(u_int16_t *)(w)) -+#define USETW(w,v) (*(u_int16_t *)(w) = (v)) -+#define UGETDW(w) (*(u_int32_t *)(w)) -+#define USETDW(w,v) (*(u_int32_t *)(w) = (v)) -+#endif -+ -+/* -+ * Macros for accessing UAS IU fields, which are big-endian -+ */ -+#define IUSETW2(w,h,l) ((w)[0] = (u_int8_t)(h), (w)[1] = (u_int8_t)(l)) -+#define IUCONSTW(x) { ((x) >> 8) & 0xff, (x) & 0xff } -+#define IUCONSTDW(x) { ((x) >> 24) & 0xff, ((x) >> 16) & 0xff, \ -+ ((x) >> 8) & 0xff, (x) & 0xff } -+#define IUGETW(w) (((w)[0] << 8) | (w)[1]) -+#define IUSETW(w,v) ((w)[0] = (u_int8_t)((v) >> 8), (w)[1] = (u_int8_t)(v)) -+#define IUGETDW(w) (((w)[0] << 24) | ((w)[1] << 16) | ((w)[2] << 8) | (w)[3]) -+#define IUSETDW(w,v) ((w)[0] = (u_int8_t)((v) >> 24), \ -+ (w)[1] = (u_int8_t)((v) >> 16), \ -+ (w)[2] = (u_int8_t)((v) >> 8), \ -+ (w)[3] = (u_int8_t)(v)) -+ -+#define UPACKED __attribute__((__packed__)) -+ -+typedef struct { -+ uByte bmRequestType; -+ uByte bRequest; -+ uWord wValue; -+ uWord wIndex; -+ uWord wLength; -+} UPACKED usb_device_request_t; -+ -+#define UT_GET_DIR(a) ((a) & 0x80) -+#define UT_WRITE 0x00 -+#define UT_READ 0x80 -+ -+#define UT_GET_TYPE(a) ((a) & 0x60) -+#define UT_STANDARD 0x00 -+#define UT_CLASS 0x20 -+#define UT_VENDOR 0x40 -+ -+#define UT_GET_RECIPIENT(a) ((a) & 0x1f) -+#define UT_DEVICE 0x00 -+#define UT_INTERFACE 0x01 -+#define UT_ENDPOINT 0x02 -+#define UT_OTHER 0x03 -+ -+#define UT_READ_DEVICE (UT_READ | UT_STANDARD | UT_DEVICE) -+#define UT_READ_INTERFACE (UT_READ | UT_STANDARD | UT_INTERFACE) -+#define UT_READ_ENDPOINT (UT_READ | UT_STANDARD | UT_ENDPOINT) -+#define UT_WRITE_DEVICE (UT_WRITE | UT_STANDARD | UT_DEVICE) -+#define UT_WRITE_INTERFACE (UT_WRITE | UT_STANDARD | UT_INTERFACE) -+#define UT_WRITE_ENDPOINT (UT_WRITE | UT_STANDARD | UT_ENDPOINT) -+#define UT_READ_CLASS_DEVICE (UT_READ | UT_CLASS | UT_DEVICE) -+#define UT_READ_CLASS_INTERFACE (UT_READ | UT_CLASS | UT_INTERFACE) -+#define UT_READ_CLASS_OTHER (UT_READ | UT_CLASS | UT_OTHER) -+#define UT_READ_CLASS_ENDPOINT (UT_READ | UT_CLASS | UT_ENDPOINT) -+#define UT_WRITE_CLASS_DEVICE (UT_WRITE | UT_CLASS | UT_DEVICE) -+#define UT_WRITE_CLASS_INTERFACE (UT_WRITE | UT_CLASS | UT_INTERFACE) -+#define UT_WRITE_CLASS_OTHER (UT_WRITE | UT_CLASS | UT_OTHER) -+#define UT_WRITE_CLASS_ENDPOINT (UT_WRITE | UT_CLASS | UT_ENDPOINT) -+#define UT_READ_VENDOR_DEVICE (UT_READ | UT_VENDOR | UT_DEVICE) -+#define UT_READ_VENDOR_INTERFACE (UT_READ | UT_VENDOR | UT_INTERFACE) -+#define UT_READ_VENDOR_OTHER (UT_READ | UT_VENDOR | UT_OTHER) -+#define UT_READ_VENDOR_ENDPOINT (UT_READ | UT_VENDOR | UT_ENDPOINT) -+#define UT_WRITE_VENDOR_DEVICE (UT_WRITE | UT_VENDOR | UT_DEVICE) -+#define UT_WRITE_VENDOR_INTERFACE (UT_WRITE | UT_VENDOR | UT_INTERFACE) -+#define UT_WRITE_VENDOR_OTHER (UT_WRITE | UT_VENDOR | UT_OTHER) -+#define UT_WRITE_VENDOR_ENDPOINT (UT_WRITE | UT_VENDOR | UT_ENDPOINT) -+ -+/* Requests */ -+#define UR_GET_STATUS 0x00 -+#define USTAT_STANDARD_STATUS 0x00 -+#define WUSTAT_WUSB_FEATURE 0x01 -+#define WUSTAT_CHANNEL_INFO 0x02 -+#define WUSTAT_RECEIVED_DATA 0x03 -+#define WUSTAT_MAS_AVAILABILITY 0x04 -+#define WUSTAT_CURRENT_TRANSMIT_POWER 0x05 -+#define UR_CLEAR_FEATURE 0x01 -+#define UR_SET_FEATURE 0x03 -+#define UR_SET_AND_TEST_FEATURE 0x0c -+#define UR_SET_ADDRESS 0x05 -+#define UR_GET_DESCRIPTOR 0x06 -+#define UDESC_DEVICE 0x01 -+#define UDESC_CONFIG 0x02 -+#define UDESC_STRING 0x03 -+#define UDESC_INTERFACE 0x04 -+#define UDESC_ENDPOINT 0x05 -+#define UDESC_SS_USB_COMPANION 0x30 -+#define UDESC_DEVICE_QUALIFIER 0x06 -+#define UDESC_OTHER_SPEED_CONFIGURATION 0x07 -+#define UDESC_INTERFACE_POWER 0x08 -+#define UDESC_OTG 0x09 -+#define WUDESC_SECURITY 0x0c -+#define WUDESC_KEY 0x0d -+#define WUD_GET_KEY_INDEX(_wValue_) ((_wValue_) & 0xf) -+#define WUD_GET_KEY_TYPE(_wValue_) (((_wValue_) & 0x30) >> 4) -+#define WUD_KEY_TYPE_ASSOC 0x01 -+#define WUD_KEY_TYPE_GTK 0x02 -+#define WUD_GET_KEY_ORIGIN(_wValue_) (((_wValue_) & 0x40) >> 6) -+#define WUD_KEY_ORIGIN_HOST 0x00 -+#define WUD_KEY_ORIGIN_DEVICE 0x01 -+#define WUDESC_ENCRYPTION_TYPE 0x0e -+#define WUDESC_BOS 0x0f -+#define WUDESC_DEVICE_CAPABILITY 0x10 -+#define WUDESC_WIRELESS_ENDPOINT_COMPANION 0x11 -+#define UDESC_BOS 0x0f -+#define UDESC_DEVICE_CAPABILITY 0x10 -+#define UDESC_CS_DEVICE 0x21 /* class specific */ -+#define UDESC_CS_CONFIG 0x22 -+#define UDESC_CS_STRING 0x23 -+#define UDESC_CS_INTERFACE 0x24 -+#define UDESC_CS_ENDPOINT 0x25 -+#define UDESC_HUB 0x29 -+#define UR_SET_DESCRIPTOR 0x07 -+#define UR_GET_CONFIG 0x08 -+#define UR_SET_CONFIG 0x09 -+#define UR_GET_INTERFACE 0x0a -+#define UR_SET_INTERFACE 0x0b -+#define UR_SYNCH_FRAME 0x0c -+#define WUR_SET_ENCRYPTION 0x0d -+#define WUR_GET_ENCRYPTION 0x0e -+#define WUR_SET_HANDSHAKE 0x0f -+#define WUR_GET_HANDSHAKE 0x10 -+#define WUR_SET_CONNECTION 0x11 -+#define WUR_SET_SECURITY_DATA 0x12 -+#define WUR_GET_SECURITY_DATA 0x13 -+#define WUR_SET_WUSB_DATA 0x14 -+#define WUDATA_DRPIE_INFO 0x01 -+#define WUDATA_TRANSMIT_DATA 0x02 -+#define WUDATA_TRANSMIT_PARAMS 0x03 -+#define WUDATA_RECEIVE_PARAMS 0x04 -+#define WUDATA_TRANSMIT_POWER 0x05 -+#define WUR_LOOPBACK_DATA_WRITE 0x15 -+#define WUR_LOOPBACK_DATA_READ 0x16 -+#define WUR_SET_INTERFACE_DS 0x17 -+ -+/* Feature numbers */ -+#define UF_ENDPOINT_HALT 0 -+#define UF_DEVICE_REMOTE_WAKEUP 1 -+#define UF_TEST_MODE 2 -+#define UF_DEVICE_B_HNP_ENABLE 3 -+#define UF_DEVICE_A_HNP_SUPPORT 4 -+#define UF_DEVICE_A_ALT_HNP_SUPPORT 5 -+#define WUF_WUSB 3 -+#define WUF_TX_DRPIE 0x0 -+#define WUF_DEV_XMIT_PACKET 0x1 -+#define WUF_COUNT_PACKETS 0x2 -+#define WUF_CAPTURE_PACKETS 0x3 -+#define UF_FUNCTION_SUSPEND 0 -+#define UF_U1_ENABLE 48 -+#define UF_U2_ENABLE 49 -+#define UF_LTM_ENABLE 50 -+ -+/* Class requests from the USB 2.0 hub spec, table 11-15 */ -+#define UCR_CLEAR_HUB_FEATURE (0x2000 | UR_CLEAR_FEATURE) -+#define UCR_CLEAR_PORT_FEATURE (0x2300 | UR_CLEAR_FEATURE) -+#define UCR_GET_HUB_DESCRIPTOR (0xa000 | UR_GET_DESCRIPTOR) -+#define UCR_GET_HUB_STATUS (0xa000 | UR_GET_STATUS) -+#define UCR_GET_PORT_STATUS (0xa300 | UR_GET_STATUS) -+#define UCR_SET_HUB_FEATURE (0x2000 | UR_SET_FEATURE) -+#define UCR_SET_PORT_FEATURE (0x2300 | UR_SET_FEATURE) -+#define UCR_SET_AND_TEST_PORT_FEATURE (0xa300 | UR_SET_AND_TEST_FEATURE) -+ -+#ifdef _MSC_VER -+#include -+#endif -+ -+typedef struct { -+ uByte bLength; -+ uByte bDescriptorType; -+ uByte bDescriptorSubtype; -+} UPACKED usb_descriptor_t; -+ -+typedef struct { -+ uByte bLength; -+ uByte bDescriptorType; -+} UPACKED usb_descriptor_header_t; -+ -+typedef struct { -+ uByte bLength; -+ uByte bDescriptorType; -+ uWord bcdUSB; -+#define UD_USB_2_0 0x0200 -+#define UD_IS_USB2(d) (UGETW((d)->bcdUSB) >= UD_USB_2_0) -+ uByte bDeviceClass; -+ uByte bDeviceSubClass; -+ uByte bDeviceProtocol; -+ uByte bMaxPacketSize; -+ /* The fields below are not part of the initial descriptor. */ -+ uWord idVendor; -+ uWord idProduct; -+ uWord bcdDevice; -+ uByte iManufacturer; -+ uByte iProduct; -+ uByte iSerialNumber; -+ uByte bNumConfigurations; -+} UPACKED usb_device_descriptor_t; -+#define USB_DEVICE_DESCRIPTOR_SIZE 18 -+ -+typedef struct { -+ uByte bLength; -+ uByte bDescriptorType; -+ uWord wTotalLength; -+ uByte bNumInterface; -+ uByte bConfigurationValue; -+ uByte iConfiguration; -+#define UC_ATT_ONE (1 << 7) /* must be set */ -+#define UC_ATT_SELFPOWER (1 << 6) /* self powered */ -+#define UC_ATT_WAKEUP (1 << 5) /* can wakeup */ -+#define UC_ATT_BATTERY (1 << 4) /* battery powered */ -+ uByte bmAttributes; -+#define UC_BUS_POWERED 0x80 -+#define UC_SELF_POWERED 0x40 -+#define UC_REMOTE_WAKEUP 0x20 -+ uByte bMaxPower; /* max current in 2 mA units */ -+#define UC_POWER_FACTOR 2 -+} UPACKED usb_config_descriptor_t; -+#define USB_CONFIG_DESCRIPTOR_SIZE 9 -+ -+typedef struct { -+ uByte bLength; -+ uByte bDescriptorType; -+ uByte bInterfaceNumber; -+ uByte bAlternateSetting; -+ uByte bNumEndpoints; -+ uByte bInterfaceClass; -+ uByte bInterfaceSubClass; -+ uByte bInterfaceProtocol; -+ uByte iInterface; -+} UPACKED usb_interface_descriptor_t; -+#define USB_INTERFACE_DESCRIPTOR_SIZE 9 -+ -+typedef struct { -+ uByte bLength; -+ uByte bDescriptorType; -+ uByte bEndpointAddress; -+#define UE_GET_DIR(a) ((a) & 0x80) -+#define UE_SET_DIR(a,d) ((a) | (((d)&1) << 7)) -+#define UE_DIR_IN 0x80 -+#define UE_DIR_OUT 0x00 -+#define UE_ADDR 0x0f -+#define UE_GET_ADDR(a) ((a) & UE_ADDR) -+ uByte bmAttributes; -+#define UE_XFERTYPE 0x03 -+#define UE_CONTROL 0x00 -+#define UE_ISOCHRONOUS 0x01 -+#define UE_BULK 0x02 -+#define UE_INTERRUPT 0x03 -+#define UE_GET_XFERTYPE(a) ((a) & UE_XFERTYPE) -+#define UE_ISO_TYPE 0x0c -+#define UE_ISO_ASYNC 0x04 -+#define UE_ISO_ADAPT 0x08 -+#define UE_ISO_SYNC 0x0c -+#define UE_GET_ISO_TYPE(a) ((a) & UE_ISO_TYPE) -+ uWord wMaxPacketSize; -+ uByte bInterval; -+} UPACKED usb_endpoint_descriptor_t; -+#define USB_ENDPOINT_DESCRIPTOR_SIZE 7 -+ -+typedef struct ss_endpoint_companion_descriptor { -+ uByte bLength; -+ uByte bDescriptorType; -+ uByte bMaxBurst; -+#define USSE_GET_MAX_STREAMS(a) ((a) & 0x1f) -+#define USSE_SET_MAX_STREAMS(a, b) ((a) | ((b) & 0x1f)) -+#define USSE_GET_MAX_PACKET_NUM(a) ((a) & 0x03) -+#define USSE_SET_MAX_PACKET_NUM(a, b) ((a) | ((b) & 0x03)) -+ uByte bmAttributes; -+ uWord wBytesPerInterval; -+} UPACKED ss_endpoint_companion_descriptor_t; -+#define USB_SS_ENDPOINT_COMPANION_DESCRIPTOR_SIZE 6 -+ -+typedef struct { -+ uByte bLength; -+ uByte bDescriptorType; -+ uWord bString[127]; -+} UPACKED usb_string_descriptor_t; -+#define USB_MAX_STRING_LEN 128 -+#define USB_LANGUAGE_TABLE 0 /* # of the string language id table */ -+ -+/* Hub specific request */ -+#define UR_GET_BUS_STATE 0x02 -+#define UR_CLEAR_TT_BUFFER 0x08 -+#define UR_RESET_TT 0x09 -+#define UR_GET_TT_STATE 0x0a -+#define UR_STOP_TT 0x0b -+ -+/* Hub features */ -+#define UHF_C_HUB_LOCAL_POWER 0 -+#define UHF_C_HUB_OVER_CURRENT 1 -+#define UHF_PORT_CONNECTION 0 -+#define UHF_PORT_ENABLE 1 -+#define UHF_PORT_SUSPEND 2 -+#define UHF_PORT_OVER_CURRENT 3 -+#define UHF_PORT_RESET 4 -+#define UHF_PORT_L1 5 -+#define UHF_PORT_POWER 8 -+#define UHF_PORT_LOW_SPEED 9 -+#define UHF_PORT_HIGH_SPEED 10 -+#define UHF_C_PORT_CONNECTION 16 -+#define UHF_C_PORT_ENABLE 17 -+#define UHF_C_PORT_SUSPEND 18 -+#define UHF_C_PORT_OVER_CURRENT 19 -+#define UHF_C_PORT_RESET 20 -+#define UHF_C_PORT_L1 23 -+#define UHF_PORT_TEST 21 -+#define UHF_PORT_INDICATOR 22 -+ -+typedef struct { -+ uByte bDescLength; -+ uByte bDescriptorType; -+ uByte bNbrPorts; -+ uWord wHubCharacteristics; -+#define UHD_PWR 0x0003 -+#define UHD_PWR_GANGED 0x0000 -+#define UHD_PWR_INDIVIDUAL 0x0001 -+#define UHD_PWR_NO_SWITCH 0x0002 -+#define UHD_COMPOUND 0x0004 -+#define UHD_OC 0x0018 -+#define UHD_OC_GLOBAL 0x0000 -+#define UHD_OC_INDIVIDUAL 0x0008 -+#define UHD_OC_NONE 0x0010 -+#define UHD_TT_THINK 0x0060 -+#define UHD_TT_THINK_8 0x0000 -+#define UHD_TT_THINK_16 0x0020 -+#define UHD_TT_THINK_24 0x0040 -+#define UHD_TT_THINK_32 0x0060 -+#define UHD_PORT_IND 0x0080 -+ uByte bPwrOn2PwrGood; /* delay in 2 ms units */ -+#define UHD_PWRON_FACTOR 2 -+ uByte bHubContrCurrent; -+ uByte DeviceRemovable[32]; /* max 255 ports */ -+#define UHD_NOT_REMOV(desc, i) \ -+ (((desc)->DeviceRemovable[(i)/8] >> ((i) % 8)) & 1) -+ /* deprecated */ uByte PortPowerCtrlMask[1]; -+} UPACKED usb_hub_descriptor_t; -+#define USB_HUB_DESCRIPTOR_SIZE 9 /* includes deprecated PortPowerCtrlMask */ -+ -+typedef struct { -+ uByte bLength; -+ uByte bDescriptorType; -+ uWord bcdUSB; -+ uByte bDeviceClass; -+ uByte bDeviceSubClass; -+ uByte bDeviceProtocol; -+ uByte bMaxPacketSize0; -+ uByte bNumConfigurations; -+ uByte bReserved; -+} UPACKED usb_device_qualifier_t; -+#define USB_DEVICE_QUALIFIER_SIZE 10 -+ -+typedef struct { -+ uByte bLength; -+ uByte bDescriptorType; -+ uByte bmAttributes; -+#define UOTG_SRP 0x01 -+#define UOTG_HNP 0x02 -+} UPACKED usb_otg_descriptor_t; -+ -+/* OTG feature selectors */ -+#define UOTG_B_HNP_ENABLE 3 -+#define UOTG_A_HNP_SUPPORT 4 -+#define UOTG_A_ALT_HNP_SUPPORT 5 -+ -+typedef struct { -+ uWord wStatus; -+/* Device status flags */ -+#define UDS_SELF_POWERED 0x0001 -+#define UDS_REMOTE_WAKEUP 0x0002 -+/* Endpoint status flags */ -+#define UES_HALT 0x0001 -+} UPACKED usb_status_t; -+ -+typedef struct { -+ uWord wHubStatus; -+#define UHS_LOCAL_POWER 0x0001 -+#define UHS_OVER_CURRENT 0x0002 -+ uWord wHubChange; -+} UPACKED usb_hub_status_t; -+ -+typedef struct { -+ uWord wPortStatus; -+#define UPS_CURRENT_CONNECT_STATUS 0x0001 -+#define UPS_PORT_ENABLED 0x0002 -+#define UPS_SUSPEND 0x0004 -+#define UPS_OVERCURRENT_INDICATOR 0x0008 -+#define UPS_RESET 0x0010 -+#define UPS_PORT_POWER 0x0100 -+#define UPS_LOW_SPEED 0x0200 -+#define UPS_HIGH_SPEED 0x0400 -+#define UPS_PORT_TEST 0x0800 -+#define UPS_PORT_INDICATOR 0x1000 -+ uWord wPortChange; -+#define UPS_C_CONNECT_STATUS 0x0001 -+#define UPS_C_PORT_ENABLED 0x0002 -+#define UPS_C_SUSPEND 0x0004 -+#define UPS_C_OVERCURRENT_INDICATOR 0x0008 -+#define UPS_C_PORT_RESET 0x0010 -+} UPACKED usb_port_status_t; -+ -+#ifdef _MSC_VER -+#include -+#endif -+ -+/* Device class codes */ -+#define UDCLASS_IN_INTERFACE 0x00 -+#define UDCLASS_COMM 0x02 -+#define UDCLASS_HUB 0x09 -+#define UDSUBCLASS_HUB 0x00 -+#define UDPROTO_FSHUB 0x00 -+#define UDPROTO_HSHUBSTT 0x01 -+#define UDPROTO_HSHUBMTT 0x02 -+#define UDCLASS_DIAGNOSTIC 0xdc -+#define UDCLASS_WIRELESS 0xe0 -+#define UDSUBCLASS_RF 0x01 -+#define UDPROTO_BLUETOOTH 0x01 -+#define UDCLASS_VENDOR 0xff -+ -+/* Interface class codes */ -+#define UICLASS_UNSPEC 0x00 -+ -+#define UICLASS_AUDIO 0x01 -+#define UISUBCLASS_AUDIOCONTROL 1 -+#define UISUBCLASS_AUDIOSTREAM 2 -+#define UISUBCLASS_MIDISTREAM 3 -+ -+#define UICLASS_CDC 0x02 /* communication */ -+#define UISUBCLASS_DIRECT_LINE_CONTROL_MODEL 1 -+#define UISUBCLASS_ABSTRACT_CONTROL_MODEL 2 -+#define UISUBCLASS_TELEPHONE_CONTROL_MODEL 3 -+#define UISUBCLASS_MULTICHANNEL_CONTROL_MODEL 4 -+#define UISUBCLASS_CAPI_CONTROLMODEL 5 -+#define UISUBCLASS_ETHERNET_NETWORKING_CONTROL_MODEL 6 -+#define UISUBCLASS_ATM_NETWORKING_CONTROL_MODEL 7 -+#define UIPROTO_CDC_AT 1 -+ -+#define UICLASS_HID 0x03 -+#define UISUBCLASS_BOOT 1 -+#define UIPROTO_BOOT_KEYBOARD 1 -+ -+#define UICLASS_PHYSICAL 0x05 -+ -+#define UICLASS_IMAGE 0x06 -+ -+#define UICLASS_PRINTER 0x07 -+#define UISUBCLASS_PRINTER 1 -+#define UIPROTO_PRINTER_UNI 1 -+#define UIPROTO_PRINTER_BI 2 -+#define UIPROTO_PRINTER_1284 3 -+ -+#define UICLASS_MASS 0x08 -+#define UISUBCLASS_RBC 1 -+#define UISUBCLASS_SFF8020I 2 -+#define UISUBCLASS_QIC157 3 -+#define UISUBCLASS_UFI 4 -+#define UISUBCLASS_SFF8070I 5 -+#define UISUBCLASS_SCSI 6 -+#define UIPROTO_MASS_CBI_I 0 -+#define UIPROTO_MASS_CBI 1 -+#define UIPROTO_MASS_BBB_OLD 2 /* Not in the spec anymore */ -+#define UIPROTO_MASS_BBB 80 /* 'P' for the Iomega Zip drive */ -+ -+#define UICLASS_HUB 0x09 -+#define UISUBCLASS_HUB 0 -+#define UIPROTO_FSHUB 0 -+#define UIPROTO_HSHUBSTT 0 /* Yes, same as previous */ -+#define UIPROTO_HSHUBMTT 1 -+ -+#define UICLASS_CDC_DATA 0x0a -+#define UISUBCLASS_DATA 0 -+#define UIPROTO_DATA_ISDNBRI 0x30 /* Physical iface */ -+#define UIPROTO_DATA_HDLC 0x31 /* HDLC */ -+#define UIPROTO_DATA_TRANSPARENT 0x32 /* Transparent */ -+#define UIPROTO_DATA_Q921M 0x50 /* Management for Q921 */ -+#define UIPROTO_DATA_Q921 0x51 /* Data for Q921 */ -+#define UIPROTO_DATA_Q921TM 0x52 /* TEI multiplexer for Q921 */ -+#define UIPROTO_DATA_V42BIS 0x90 /* Data compression */ -+#define UIPROTO_DATA_Q931 0x91 /* Euro-ISDN */ -+#define UIPROTO_DATA_V120 0x92 /* V.24 rate adaption */ -+#define UIPROTO_DATA_CAPI 0x93 /* CAPI 2.0 commands */ -+#define UIPROTO_DATA_HOST_BASED 0xfd /* Host based driver */ -+#define UIPROTO_DATA_PUF 0xfe /* see Prot. Unit Func. Desc.*/ -+#define UIPROTO_DATA_VENDOR 0xff /* Vendor specific */ -+ -+#define UICLASS_SMARTCARD 0x0b -+ -+/*#define UICLASS_FIRM_UPD 0x0c*/ -+ -+#define UICLASS_SECURITY 0x0d -+ -+#define UICLASS_DIAGNOSTIC 0xdc -+ -+#define UICLASS_WIRELESS 0xe0 -+#define UISUBCLASS_RF 0x01 -+#define UIPROTO_BLUETOOTH 0x01 -+ -+#define UICLASS_APPL_SPEC 0xfe -+#define UISUBCLASS_FIRMWARE_DOWNLOAD 1 -+#define UISUBCLASS_IRDA 2 -+#define UIPROTO_IRDA 0 -+ -+#define UICLASS_VENDOR 0xff -+ -+#define USB_HUB_MAX_DEPTH 5 -+ -+/* -+ * Minimum time a device needs to be powered down to go through -+ * a power cycle. XXX Are these time in the spec? -+ */ -+#define USB_POWER_DOWN_TIME 200 /* ms */ -+#define USB_PORT_POWER_DOWN_TIME 100 /* ms */ -+ -+#if 0 -+/* These are the values from the spec. */ -+#define USB_PORT_RESET_DELAY 10 /* ms */ -+#define USB_PORT_ROOT_RESET_DELAY 50 /* ms */ -+#define USB_PORT_RESET_RECOVERY 10 /* ms */ -+#define USB_PORT_POWERUP_DELAY 100 /* ms */ -+#define USB_SET_ADDRESS_SETTLE 2 /* ms */ -+#define USB_RESUME_DELAY (20*5) /* ms */ -+#define USB_RESUME_WAIT 10 /* ms */ -+#define USB_RESUME_RECOVERY 10 /* ms */ -+#define USB_EXTRA_POWER_UP_TIME 0 /* ms */ -+#else -+/* Allow for marginal (i.e. non-conforming) devices. */ -+#define USB_PORT_RESET_DELAY 50 /* ms */ -+#define USB_PORT_ROOT_RESET_DELAY 250 /* ms */ -+#define USB_PORT_RESET_RECOVERY 250 /* ms */ -+#define USB_PORT_POWERUP_DELAY 300 /* ms */ -+#define USB_SET_ADDRESS_SETTLE 10 /* ms */ -+#define USB_RESUME_DELAY (50*5) /* ms */ -+#define USB_RESUME_WAIT 50 /* ms */ -+#define USB_RESUME_RECOVERY 50 /* ms */ -+#define USB_EXTRA_POWER_UP_TIME 20 /* ms */ -+#endif -+ -+#define USB_MIN_POWER 100 /* mA */ -+#define USB_MAX_POWER 500 /* mA */ -+ -+#define USB_BUS_RESET_DELAY 100 /* ms XXX?*/ -+ -+#define USB_UNCONFIG_NO 0 -+#define USB_UNCONFIG_INDEX (-1) -+ -+/*** ioctl() related stuff ***/ -+ -+struct usb_ctl_request { -+ int ucr_addr; -+ usb_device_request_t ucr_request; -+ void *ucr_data; -+ int ucr_flags; -+#define USBD_SHORT_XFER_OK 0x04 /* allow short reads */ -+ int ucr_actlen; /* actual length transferred */ -+}; -+ -+struct usb_alt_interface { -+ int uai_config_index; -+ int uai_interface_index; -+ int uai_alt_no; -+}; -+ -+#define USB_CURRENT_CONFIG_INDEX (-1) -+#define USB_CURRENT_ALT_INDEX (-1) -+ -+struct usb_config_desc { -+ int ucd_config_index; -+ usb_config_descriptor_t ucd_desc; -+}; -+ -+struct usb_interface_desc { -+ int uid_config_index; -+ int uid_interface_index; -+ int uid_alt_index; -+ usb_interface_descriptor_t uid_desc; -+}; -+ -+struct usb_endpoint_desc { -+ int ued_config_index; -+ int ued_interface_index; -+ int ued_alt_index; -+ int ued_endpoint_index; -+ usb_endpoint_descriptor_t ued_desc; -+}; -+ -+struct usb_full_desc { -+ int ufd_config_index; -+ u_int ufd_size; -+ u_char *ufd_data; -+}; -+ -+struct usb_string_desc { -+ int usd_string_index; -+ int usd_language_id; -+ usb_string_descriptor_t usd_desc; -+}; -+ -+struct usb_ctl_report_desc { -+ int ucrd_size; -+ u_char ucrd_data[1024]; /* filled data size will vary */ -+}; -+ -+typedef struct { u_int32_t cookie; } usb_event_cookie_t; -+ -+#define USB_MAX_DEVNAMES 4 -+#define USB_MAX_DEVNAMELEN 16 -+struct usb_device_info { -+ u_int8_t udi_bus; -+ u_int8_t udi_addr; /* device address */ -+ usb_event_cookie_t udi_cookie; -+ char udi_product[USB_MAX_STRING_LEN]; -+ char udi_vendor[USB_MAX_STRING_LEN]; -+ char udi_release[8]; -+ u_int16_t udi_productNo; -+ u_int16_t udi_vendorNo; -+ u_int16_t udi_releaseNo; -+ u_int8_t udi_class; -+ u_int8_t udi_subclass; -+ u_int8_t udi_protocol; -+ u_int8_t udi_config; -+ u_int8_t udi_speed; -+#define USB_SPEED_UNKNOWN 0 -+#define USB_SPEED_LOW 1 -+#define USB_SPEED_FULL 2 -+#define USB_SPEED_HIGH 3 -+#define USB_SPEED_VARIABLE 4 -+#define USB_SPEED_SUPER 5 -+ int udi_power; /* power consumption in mA, 0 if selfpowered */ -+ int udi_nports; -+ char udi_devnames[USB_MAX_DEVNAMES][USB_MAX_DEVNAMELEN]; -+ u_int8_t udi_ports[16];/* hub only: addresses of devices on ports */ -+#define USB_PORT_ENABLED 0xff -+#define USB_PORT_SUSPENDED 0xfe -+#define USB_PORT_POWERED 0xfd -+#define USB_PORT_DISABLED 0xfc -+}; -+ -+struct usb_ctl_report { -+ int ucr_report; -+ u_char ucr_data[1024]; /* filled data size will vary */ -+}; -+ -+struct usb_device_stats { -+ u_long uds_requests[4]; /* indexed by transfer type UE_* */ -+}; -+ -+#define WUSB_MIN_IE 0x80 -+#define WUSB_WCTA_IE 0x80 -+#define WUSB_WCONNECTACK_IE 0x81 -+#define WUSB_WHOSTINFO_IE 0x82 -+#define WUHI_GET_CA(_bmAttributes_) ((_bmAttributes_) & 0x3) -+#define WUHI_CA_RECONN 0x00 -+#define WUHI_CA_LIMITED 0x01 -+#define WUHI_CA_ALL 0x03 -+#define WUHI_GET_MLSI(_bmAttributes_) (((_bmAttributes_) & 0x38) >> 3) -+#define WUSB_WCHCHANGEANNOUNCE_IE 0x83 -+#define WUSB_WDEV_DISCONNECT_IE 0x84 -+#define WUSB_WHOST_DISCONNECT_IE 0x85 -+#define WUSB_WRELEASE_CHANNEL_IE 0x86 -+#define WUSB_WWORK_IE 0x87 -+#define WUSB_WCHANNEL_STOP_IE 0x88 -+#define WUSB_WDEV_KEEPALIVE_IE 0x89 -+#define WUSB_WISOCH_DISCARD_IE 0x8A -+#define WUSB_WRESETDEVICE_IE 0x8B -+#define WUSB_WXMIT_PACKET_ADJUST_IE 0x8C -+#define WUSB_MAX_IE 0x8C -+ -+/* Device Notification Types */ -+ -+#define WUSB_DN_MIN 0x01 -+#define WUSB_DN_CONNECT 0x01 -+# define WUSB_DA_OLDCONN 0x00 -+# define WUSB_DA_NEWCONN 0x01 -+# define WUSB_DA_SELF_BEACON 0x02 -+# define WUSB_DA_DIR_BEACON 0x04 -+# define WUSB_DA_NO_BEACON 0x06 -+#define WUSB_DN_DISCONNECT 0x02 -+#define WUSB_DN_EPRDY 0x03 -+#define WUSB_DN_MASAVAILCHANGED 0x04 -+#define WUSB_DN_REMOTEWAKEUP 0x05 -+#define WUSB_DN_SLEEP 0x06 -+#define WUSB_DN_ALIVE 0x07 -+#define WUSB_DN_MAX 0x07 -+ -+#ifdef _MSC_VER -+#include -+#endif -+ -+/* WUSB Handshake Data. Used during the SET/GET HANDSHAKE requests */ -+typedef struct wusb_hndshk_data { -+ uByte bMessageNumber; -+ uByte bStatus; -+ uByte tTKID[3]; -+ uByte bReserved; -+ uByte CDID[16]; -+ uByte Nonce[16]; -+ uByte MIC[8]; -+} UPACKED wusb_hndshk_data_t; -+#define WUSB_HANDSHAKE_LEN_FOR_MIC 38 -+ -+/* WUSB Connection Context */ -+typedef struct wusb_conn_context { -+ uByte CHID [16]; -+ uByte CDID [16]; -+ uByte CK [16]; -+} UPACKED wusb_conn_context_t; -+ -+/* WUSB Security Descriptor */ -+typedef struct wusb_security_desc { -+ uByte bLength; -+ uByte bDescriptorType; -+ uWord wTotalLength; -+ uByte bNumEncryptionTypes; -+} UPACKED wusb_security_desc_t; -+ -+/* WUSB Encryption Type Descriptor */ -+typedef struct wusb_encrypt_type_desc { -+ uByte bLength; -+ uByte bDescriptorType; -+ -+ uByte bEncryptionType; -+#define WUETD_UNSECURE 0 -+#define WUETD_WIRED 1 -+#define WUETD_CCM_1 2 -+#define WUETD_RSA_1 3 -+ -+ uByte bEncryptionValue; -+ uByte bAuthKeyIndex; -+} UPACKED wusb_encrypt_type_desc_t; -+ -+/* WUSB Key Descriptor */ -+typedef struct wusb_key_desc { -+ uByte bLength; -+ uByte bDescriptorType; -+ uByte tTKID[3]; -+ uByte bReserved; -+ uByte KeyData[1]; /* variable length */ -+} UPACKED wusb_key_desc_t; -+ -+/* WUSB BOS Descriptor (Binary device Object Store) */ -+typedef struct wusb_bos_desc { -+ uByte bLength; -+ uByte bDescriptorType; -+ uWord wTotalLength; -+ uByte bNumDeviceCaps; -+} UPACKED wusb_bos_desc_t; -+ -+#define USB_DEVICE_CAPABILITY_20_EXTENSION 0x02 -+typedef struct usb_dev_cap_20_ext_desc { -+ uByte bLength; -+ uByte bDescriptorType; -+ uByte bDevCapabilityType; -+#define USB_20_EXT_LPM 0x02 -+ uDWord bmAttributes; -+} UPACKED usb_dev_cap_20_ext_desc_t; -+ -+#define USB_DEVICE_CAPABILITY_SS_USB 0x03 -+typedef struct usb_dev_cap_ss_usb { -+ uByte bLength; -+ uByte bDescriptorType; -+ uByte bDevCapabilityType; -+#define USB_DC_SS_USB_LTM_CAPABLE 0x02 -+ uByte bmAttributes; -+#define USB_DC_SS_USB_SPEED_SUPPORT_LOW 0x01 -+#define USB_DC_SS_USB_SPEED_SUPPORT_FULL 0x02 -+#define USB_DC_SS_USB_SPEED_SUPPORT_HIGH 0x04 -+#define USB_DC_SS_USB_SPEED_SUPPORT_SS 0x08 -+ uWord wSpeedsSupported; -+ uByte bFunctionalitySupport; -+ uByte bU1DevExitLat; -+ uWord wU2DevExitLat; -+} UPACKED usb_dev_cap_ss_usb_t; -+ -+#define USB_DEVICE_CAPABILITY_CONTAINER_ID 0x04 -+typedef struct usb_dev_cap_container_id { -+ uByte bLength; -+ uByte bDescriptorType; -+ uByte bDevCapabilityType; -+ uByte bReserved; -+ uByte containerID[16]; -+} UPACKED usb_dev_cap_container_id_t; -+ -+/* Device Capability Type Codes */ -+#define WUSB_DEVICE_CAPABILITY_WIRELESS_USB 0x01 -+ -+/* Device Capability Descriptor */ -+typedef struct wusb_dev_cap_desc { -+ uByte bLength; -+ uByte bDescriptorType; -+ uByte bDevCapabilityType; -+ uByte caps[1]; /* Variable length */ -+} UPACKED wusb_dev_cap_desc_t; -+ -+/* Device Capability Descriptor */ -+typedef struct wusb_dev_cap_uwb_desc { -+ uByte bLength; -+ uByte bDescriptorType; -+ uByte bDevCapabilityType; -+ uByte bmAttributes; -+ uWord wPHYRates; /* Bitmap */ -+ uByte bmTFITXPowerInfo; -+ uByte bmFFITXPowerInfo; -+ uWord bmBandGroup; -+ uByte bReserved; -+} UPACKED wusb_dev_cap_uwb_desc_t; -+ -+/* Wireless USB Endpoint Companion Descriptor */ -+typedef struct wusb_endpoint_companion_desc { -+ uByte bLength; -+ uByte bDescriptorType; -+ uByte bMaxBurst; -+ uByte bMaxSequence; -+ uWord wMaxStreamDelay; -+ uWord wOverTheAirPacketSize; -+ uByte bOverTheAirInterval; -+ uByte bmCompAttributes; -+} UPACKED wusb_endpoint_companion_desc_t; -+ -+/* Wireless USB Numeric Association M1 Data Structure */ -+typedef struct wusb_m1_data { -+ uByte version; -+ uWord langId; -+ uByte deviceFriendlyNameLength; -+ uByte sha_256_m3[32]; -+ uByte deviceFriendlyName[256]; -+} UPACKED wusb_m1_data_t; -+ -+typedef struct wusb_m2_data { -+ uByte version; -+ uWord langId; -+ uByte hostFriendlyNameLength; -+ uByte pkh[384]; -+ uByte hostFriendlyName[256]; -+} UPACKED wusb_m2_data_t; -+ -+typedef struct wusb_m3_data { -+ uByte pkd[384]; -+ uByte nd; -+} UPACKED wusb_m3_data_t; -+ -+typedef struct wusb_m4_data { -+ uDWord _attributeTypeIdAndLength_1; -+ uWord associationTypeId; -+ -+ uDWord _attributeTypeIdAndLength_2; -+ uWord associationSubTypeId; -+ -+ uDWord _attributeTypeIdAndLength_3; -+ uDWord length; -+ -+ uDWord _attributeTypeIdAndLength_4; -+ uDWord associationStatus; -+ -+ uDWord _attributeTypeIdAndLength_5; -+ uByte chid[16]; -+ -+ uDWord _attributeTypeIdAndLength_6; -+ uByte cdid[16]; -+ -+ uDWord _attributeTypeIdAndLength_7; -+ uByte bandGroups[2]; -+} UPACKED wusb_m4_data_t; -+ -+#ifdef _MSC_VER -+#include -+#endif -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* _USB_H_ */ -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/doc/doxygen.cfg linux-rpi/drivers/usb/host/dwc_otg/doc/doxygen.cfg ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/doc/doxygen.cfg 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/doc/doxygen.cfg 2015-11-29 09:42:39.915098960 +0100 -@@ -0,0 +1,224 @@ -+# Doxyfile 1.3.9.1 -+ -+#--------------------------------------------------------------------------- -+# Project related configuration options -+#--------------------------------------------------------------------------- -+PROJECT_NAME = "DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver" -+PROJECT_NUMBER = v3.00a -+OUTPUT_DIRECTORY = ./doc/ -+CREATE_SUBDIRS = NO -+OUTPUT_LANGUAGE = English -+BRIEF_MEMBER_DESC = YES -+REPEAT_BRIEF = YES -+ABBREVIATE_BRIEF = "The $name class" \ -+ "The $name widget" \ -+ "The $name file" \ -+ is \ -+ provides \ -+ specifies \ -+ contains \ -+ represents \ -+ a \ -+ an \ -+ the -+ALWAYS_DETAILED_SEC = NO -+INLINE_INHERITED_MEMB = NO -+FULL_PATH_NAMES = NO -+STRIP_FROM_PATH = -+STRIP_FROM_INC_PATH = -+SHORT_NAMES = NO -+JAVADOC_AUTOBRIEF = YES -+MULTILINE_CPP_IS_BRIEF = NO -+INHERIT_DOCS = YES -+DISTRIBUTE_GROUP_DOC = NO -+TAB_SIZE = 8 -+ALIASES = -+OPTIMIZE_OUTPUT_FOR_C = YES -+OPTIMIZE_OUTPUT_JAVA = NO -+SUBGROUPING = YES -+#--------------------------------------------------------------------------- -+# Build related configuration options -+#--------------------------------------------------------------------------- -+EXTRACT_ALL = NO -+EXTRACT_PRIVATE = YES -+EXTRACT_STATIC = YES -+EXTRACT_LOCAL_CLASSES = YES -+EXTRACT_LOCAL_METHODS = NO -+HIDE_UNDOC_MEMBERS = NO -+HIDE_UNDOC_CLASSES = NO -+HIDE_FRIEND_COMPOUNDS = NO -+HIDE_IN_BODY_DOCS = NO -+INTERNAL_DOCS = NO -+CASE_SENSE_NAMES = NO -+HIDE_SCOPE_NAMES = NO -+SHOW_INCLUDE_FILES = YES -+INLINE_INFO = YES -+SORT_MEMBER_DOCS = NO -+SORT_BRIEF_DOCS = NO -+SORT_BY_SCOPE_NAME = NO -+GENERATE_TODOLIST = YES -+GENERATE_TESTLIST = YES -+GENERATE_BUGLIST = YES -+GENERATE_DEPRECATEDLIST= YES -+ENABLED_SECTIONS = -+MAX_INITIALIZER_LINES = 30 -+SHOW_USED_FILES = YES -+SHOW_DIRECTORIES = YES -+#--------------------------------------------------------------------------- -+# configuration options related to warning and progress messages -+#--------------------------------------------------------------------------- -+QUIET = YES -+WARNINGS = YES -+WARN_IF_UNDOCUMENTED = NO -+WARN_IF_DOC_ERROR = YES -+WARN_FORMAT = "$file:$line: $text" -+WARN_LOGFILE = -+#--------------------------------------------------------------------------- -+# configuration options related to the input files -+#--------------------------------------------------------------------------- -+INPUT = . -+FILE_PATTERNS = *.c \ -+ *.h \ -+ ./linux/*.c \ -+ ./linux/*.h -+RECURSIVE = NO -+EXCLUDE = ./test/ \ -+ ./dwc_otg/.AppleDouble/ -+EXCLUDE_SYMLINKS = YES -+EXCLUDE_PATTERNS = *.mod.* -+EXAMPLE_PATH = -+EXAMPLE_PATTERNS = * -+EXAMPLE_RECURSIVE = NO -+IMAGE_PATH = -+INPUT_FILTER = -+FILTER_PATTERNS = -+FILTER_SOURCE_FILES = NO -+#--------------------------------------------------------------------------- -+# configuration options related to source browsing -+#--------------------------------------------------------------------------- -+SOURCE_BROWSER = YES -+INLINE_SOURCES = NO -+STRIP_CODE_COMMENTS = YES -+REFERENCED_BY_RELATION = NO -+REFERENCES_RELATION = NO -+VERBATIM_HEADERS = NO -+#--------------------------------------------------------------------------- -+# configuration options related to the alphabetical class index -+#--------------------------------------------------------------------------- -+ALPHABETICAL_INDEX = NO -+COLS_IN_ALPHA_INDEX = 5 -+IGNORE_PREFIX = -+#--------------------------------------------------------------------------- -+# configuration options related to the HTML output -+#--------------------------------------------------------------------------- -+GENERATE_HTML = YES -+HTML_OUTPUT = html -+HTML_FILE_EXTENSION = .html -+HTML_HEADER = -+HTML_FOOTER = -+HTML_STYLESHEET = -+HTML_ALIGN_MEMBERS = YES -+GENERATE_HTMLHELP = NO -+CHM_FILE = -+HHC_LOCATION = -+GENERATE_CHI = NO -+BINARY_TOC = NO -+TOC_EXPAND = NO -+DISABLE_INDEX = NO -+ENUM_VALUES_PER_LINE = 4 -+GENERATE_TREEVIEW = YES -+TREEVIEW_WIDTH = 250 -+#--------------------------------------------------------------------------- -+# configuration options related to the LaTeX output -+#--------------------------------------------------------------------------- -+GENERATE_LATEX = NO -+LATEX_OUTPUT = latex -+LATEX_CMD_NAME = latex -+MAKEINDEX_CMD_NAME = makeindex -+COMPACT_LATEX = NO -+PAPER_TYPE = a4wide -+EXTRA_PACKAGES = -+LATEX_HEADER = -+PDF_HYPERLINKS = NO -+USE_PDFLATEX = NO -+LATEX_BATCHMODE = NO -+LATEX_HIDE_INDICES = NO -+#--------------------------------------------------------------------------- -+# configuration options related to the RTF output -+#--------------------------------------------------------------------------- -+GENERATE_RTF = NO -+RTF_OUTPUT = rtf -+COMPACT_RTF = NO -+RTF_HYPERLINKS = NO -+RTF_STYLESHEET_FILE = -+RTF_EXTENSIONS_FILE = -+#--------------------------------------------------------------------------- -+# configuration options related to the man page output -+#--------------------------------------------------------------------------- -+GENERATE_MAN = NO -+MAN_OUTPUT = man -+MAN_EXTENSION = .3 -+MAN_LINKS = NO -+#--------------------------------------------------------------------------- -+# configuration options related to the XML output -+#--------------------------------------------------------------------------- -+GENERATE_XML = NO -+XML_OUTPUT = xml -+XML_SCHEMA = -+XML_DTD = -+XML_PROGRAMLISTING = YES -+#--------------------------------------------------------------------------- -+# configuration options for the AutoGen Definitions output -+#--------------------------------------------------------------------------- -+GENERATE_AUTOGEN_DEF = NO -+#--------------------------------------------------------------------------- -+# configuration options related to the Perl module output -+#--------------------------------------------------------------------------- -+GENERATE_PERLMOD = NO -+PERLMOD_LATEX = NO -+PERLMOD_PRETTY = YES -+PERLMOD_MAKEVAR_PREFIX = -+#--------------------------------------------------------------------------- -+# Configuration options related to the preprocessor -+#--------------------------------------------------------------------------- -+ENABLE_PREPROCESSING = YES -+MACRO_EXPANSION = YES -+EXPAND_ONLY_PREDEF = YES -+SEARCH_INCLUDES = YES -+INCLUDE_PATH = -+INCLUDE_FILE_PATTERNS = -+PREDEFINED = DEVICE_ATTR DWC_EN_ISOC -+EXPAND_AS_DEFINED = DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW DWC_OTG_DEVICE_ATTR_BITFIELD_STORE DWC_OTG_DEVICE_ATTR_BITFIELD_RW DWC_OTG_DEVICE_ATTR_BITFIELD_RO DWC_OTG_DEVICE_ATTR_REG_SHOW DWC_OTG_DEVICE_ATTR_REG_STORE DWC_OTG_DEVICE_ATTR_REG32_RW DWC_OTG_DEVICE_ATTR_REG32_RO DWC_EN_ISOC -+SKIP_FUNCTION_MACROS = NO -+#--------------------------------------------------------------------------- -+# Configuration::additions related to external references -+#--------------------------------------------------------------------------- -+TAGFILES = -+GENERATE_TAGFILE = -+ALLEXTERNALS = NO -+EXTERNAL_GROUPS = YES -+PERL_PATH = /usr/bin/perl -+#--------------------------------------------------------------------------- -+# Configuration options related to the dot tool -+#--------------------------------------------------------------------------- -+CLASS_DIAGRAMS = YES -+HIDE_UNDOC_RELATIONS = YES -+HAVE_DOT = NO -+CLASS_GRAPH = YES -+COLLABORATION_GRAPH = YES -+UML_LOOK = NO -+TEMPLATE_RELATIONS = NO -+INCLUDE_GRAPH = YES -+INCLUDED_BY_GRAPH = YES -+CALL_GRAPH = NO -+GRAPHICAL_HIERARCHY = YES -+DOT_IMAGE_FORMAT = png -+DOT_PATH = -+DOTFILE_DIRS = -+MAX_DOT_GRAPH_DEPTH = 1000 -+GENERATE_LEGEND = YES -+DOT_CLEANUP = YES -+#--------------------------------------------------------------------------- -+# Configuration::additions related to the search engine -+#--------------------------------------------------------------------------- -+SEARCHENGINE = NO -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dummy_audio.c linux-rpi/drivers/usb/host/dwc_otg/dummy_audio.c ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dummy_audio.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/dummy_audio.c 2015-11-29 09:42:39.915098960 +0100 -@@ -0,0 +1,1575 @@ -+/* -+ * zero.c -- Gadget Zero, for USB development -+ * -+ * Copyright (C) 2003-2004 David Brownell -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+/* -+ * Gadget Zero only needs two bulk endpoints, and is an example of how you -+ * can write a hardware-agnostic gadget driver running inside a USB device. -+ * -+ * Hardware details are visible (see CONFIG_USB_ZERO_* below) but don't -+ * affect most of the driver. -+ * -+ * Use it with the Linux host/master side "usbtest" driver to get a basic -+ * functional test of your device-side usb stack, or with "usb-skeleton". -+ * -+ * It supports two similar configurations. One sinks whatever the usb host -+ * writes, and in return sources zeroes. The other loops whatever the host -+ * writes back, so the host can read it. Module options include: -+ * -+ * buflen=N default N=4096, buffer size used -+ * qlen=N default N=32, how many buffers in the loopback queue -+ * loopdefault default false, list loopback config first -+ * -+ * Many drivers will only have one configuration, letting them be much -+ * simpler if they also don't support high speed operation (like this -+ * driver does). -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21) -+# include -+#else -+# include -+#endif -+ -+#include -+ -+ -+/*-------------------------------------------------------------------------*/ -+/*-------------------------------------------------------------------------*/ -+ -+ -+static int utf8_to_utf16le(const char *s, u16 *cp, unsigned len) -+{ -+ int count = 0; -+ u8 c; -+ u16 uchar; -+ -+ /* this insists on correct encodings, though not minimal ones. -+ * BUT it currently rejects legit 4-byte UTF-8 code points, -+ * which need surrogate pairs. (Unicode 3.1 can use them.) -+ */ -+ while (len != 0 && (c = (u8) *s++) != 0) { -+ if (unlikely(c & 0x80)) { -+ // 2-byte sequence: -+ // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx -+ if ((c & 0xe0) == 0xc0) { -+ uchar = (c & 0x1f) << 6; -+ -+ c = (u8) *s++; -+ if ((c & 0xc0) != 0xc0) -+ goto fail; -+ c &= 0x3f; -+ uchar |= c; -+ -+ // 3-byte sequence (most CJKV characters): -+ // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx -+ } else if ((c & 0xf0) == 0xe0) { -+ uchar = (c & 0x0f) << 12; -+ -+ c = (u8) *s++; -+ if ((c & 0xc0) != 0xc0) -+ goto fail; -+ c &= 0x3f; -+ uchar |= c << 6; -+ -+ c = (u8) *s++; -+ if ((c & 0xc0) != 0xc0) -+ goto fail; -+ c &= 0x3f; -+ uchar |= c; -+ -+ /* no bogus surrogates */ -+ if (0xd800 <= uchar && uchar <= 0xdfff) -+ goto fail; -+ -+ // 4-byte sequence (surrogate pairs, currently rare): -+ // 11101110wwwwzzzzyy + 110111yyyyxxxxxx -+ // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx -+ // (uuuuu = wwww + 1) -+ // FIXME accept the surrogate code points (only) -+ -+ } else -+ goto fail; -+ } else -+ uchar = c; -+ put_unaligned (cpu_to_le16 (uchar), cp++); -+ count++; -+ len--; -+ } -+ return count; -+fail: -+ return -1; -+} -+ -+ -+/** -+ * usb_gadget_get_string - fill out a string descriptor -+ * @table: of c strings encoded using UTF-8 -+ * @id: string id, from low byte of wValue in get string descriptor -+ * @buf: at least 256 bytes -+ * -+ * Finds the UTF-8 string matching the ID, and converts it into a -+ * string descriptor in utf16-le. -+ * Returns length of descriptor (always even) or negative errno -+ * -+ * If your driver needs stings in multiple languages, you'll probably -+ * "switch (wIndex) { ... }" in your ep0 string descriptor logic, -+ * using this routine after choosing which set of UTF-8 strings to use. -+ * Note that US-ASCII is a strict subset of UTF-8; any string bytes with -+ * the eighth bit set will be multibyte UTF-8 characters, not ISO-8859/1 -+ * characters (which are also widely used in C strings). -+ */ -+int -+usb_gadget_get_string (struct usb_gadget_strings *table, int id, u8 *buf) -+{ -+ struct usb_string *s; -+ int len; -+ -+ /* descriptor 0 has the language id */ -+ if (id == 0) { -+ buf [0] = 4; -+ buf [1] = USB_DT_STRING; -+ buf [2] = (u8) table->language; -+ buf [3] = (u8) (table->language >> 8); -+ return 4; -+ } -+ for (s = table->strings; s && s->s; s++) -+ if (s->id == id) -+ break; -+ -+ /* unrecognized: stall. */ -+ if (!s || !s->s) -+ return -EINVAL; -+ -+ /* string descriptors have length, tag, then UTF16-LE text */ -+ len = min ((size_t) 126, strlen (s->s)); -+ memset (buf + 2, 0, 2 * len); /* zero all the bytes */ -+ len = utf8_to_utf16le(s->s, (u16 *)&buf[2], len); -+ if (len < 0) -+ return -EINVAL; -+ buf [0] = (len + 1) * 2; -+ buf [1] = USB_DT_STRING; -+ return buf [0]; -+} -+ -+ -+/*-------------------------------------------------------------------------*/ -+/*-------------------------------------------------------------------------*/ -+ -+ -+/** -+ * usb_descriptor_fillbuf - fill buffer with descriptors -+ * @buf: Buffer to be filled -+ * @buflen: Size of buf -+ * @src: Array of descriptor pointers, terminated by null pointer. -+ * -+ * Copies descriptors into the buffer, returning the length or a -+ * negative error code if they can't all be copied. Useful when -+ * assembling descriptors for an associated set of interfaces used -+ * as part of configuring a composite device; or in other cases where -+ * sets of descriptors need to be marshaled. -+ */ -+int -+usb_descriptor_fillbuf(void *buf, unsigned buflen, -+ const struct usb_descriptor_header **src) -+{ -+ u8 *dest = buf; -+ -+ if (!src) -+ return -EINVAL; -+ -+ /* fill buffer from src[] until null descriptor ptr */ -+ for (; 0 != *src; src++) { -+ unsigned len = (*src)->bLength; -+ -+ if (len > buflen) -+ return -EINVAL; -+ memcpy(dest, *src, len); -+ buflen -= len; -+ dest += len; -+ } -+ return dest - (u8 *)buf; -+} -+ -+ -+/** -+ * usb_gadget_config_buf - builts a complete configuration descriptor -+ * @config: Header for the descriptor, including characteristics such -+ * as power requirements and number of interfaces. -+ * @desc: Null-terminated vector of pointers to the descriptors (interface, -+ * endpoint, etc) defining all functions in this device configuration. -+ * @buf: Buffer for the resulting configuration descriptor. -+ * @length: Length of buffer. If this is not big enough to hold the -+ * entire configuration descriptor, an error code will be returned. -+ * -+ * This copies descriptors into the response buffer, building a descriptor -+ * for that configuration. It returns the buffer length or a negative -+ * status code. The config.wTotalLength field is set to match the length -+ * of the result, but other descriptor fields (including power usage and -+ * interface count) must be set by the caller. -+ * -+ * Gadget drivers could use this when constructing a config descriptor -+ * in response to USB_REQ_GET_DESCRIPTOR. They will need to patch the -+ * resulting bDescriptorType value if USB_DT_OTHER_SPEED_CONFIG is needed. -+ */ -+int usb_gadget_config_buf( -+ const struct usb_config_descriptor *config, -+ void *buf, -+ unsigned length, -+ const struct usb_descriptor_header **desc -+) -+{ -+ struct usb_config_descriptor *cp = buf; -+ int len; -+ -+ /* config descriptor first */ -+ if (length < USB_DT_CONFIG_SIZE || !desc) -+ return -EINVAL; -+ *cp = *config; -+ -+ /* then interface/endpoint/class/vendor/... */ -+ len = usb_descriptor_fillbuf(USB_DT_CONFIG_SIZE + (u8*)buf, -+ length - USB_DT_CONFIG_SIZE, desc); -+ if (len < 0) -+ return len; -+ len += USB_DT_CONFIG_SIZE; -+ if (len > 0xffff) -+ return -EINVAL; -+ -+ /* patch up the config descriptor */ -+ cp->bLength = USB_DT_CONFIG_SIZE; -+ cp->bDescriptorType = USB_DT_CONFIG; -+ cp->wTotalLength = cpu_to_le16(len); -+ cp->bmAttributes |= USB_CONFIG_ATT_ONE; -+ return len; -+} -+ -+/*-------------------------------------------------------------------------*/ -+/*-------------------------------------------------------------------------*/ -+ -+ -+#define RBUF_LEN (1024*1024) -+static int rbuf_start; -+static int rbuf_len; -+static __u8 rbuf[RBUF_LEN]; -+ -+/*-------------------------------------------------------------------------*/ -+ -+#define DRIVER_VERSION "St Patrick's Day 2004" -+ -+static const char shortname [] = "zero"; -+static const char longname [] = "YAMAHA YST-MS35D USB Speaker "; -+ -+static const char source_sink [] = "source and sink data"; -+static const char loopback [] = "loop input to output"; -+ -+/*-------------------------------------------------------------------------*/ -+ -+/* -+ * driver assumes self-powered hardware, and -+ * has no way for users to trigger remote wakeup. -+ * -+ * this version autoconfigures as much as possible, -+ * which is reasonable for most "bulk-only" drivers. -+ */ -+static const char *EP_IN_NAME; /* source */ -+static const char *EP_OUT_NAME; /* sink */ -+ -+/*-------------------------------------------------------------------------*/ -+ -+/* big enough to hold our biggest descriptor */ -+#define USB_BUFSIZ 512 -+ -+struct zero_dev { -+ spinlock_t lock; -+ struct usb_gadget *gadget; -+ struct usb_request *req; /* for control responses */ -+ -+ /* when configured, we have one of two configs: -+ * - source data (in to host) and sink it (out from host) -+ * - or loop it back (out from host back in to host) -+ */ -+ u8 config; -+ struct usb_ep *in_ep, *out_ep; -+ -+ /* autoresume timer */ -+ struct timer_list resume; -+}; -+ -+#define xprintk(d,level,fmt,args...) \ -+ dev_printk(level , &(d)->gadget->dev , fmt , ## args) -+ -+#ifdef DEBUG -+#define DBG(dev,fmt,args...) \ -+ xprintk(dev , KERN_DEBUG , fmt , ## args) -+#else -+#define DBG(dev,fmt,args...) \ -+ do { } while (0) -+#endif /* DEBUG */ -+ -+#ifdef VERBOSE -+#define VDBG DBG -+#else -+#define VDBG(dev,fmt,args...) \ -+ do { } while (0) -+#endif /* VERBOSE */ -+ -+#define ERROR(dev,fmt,args...) \ -+ xprintk(dev , KERN_ERR , fmt , ## args) -+#define WARN(dev,fmt,args...) \ -+ xprintk(dev , KERN_WARNING , fmt , ## args) -+#define INFO(dev,fmt,args...) \ -+ xprintk(dev , KERN_INFO , fmt , ## args) -+ -+/*-------------------------------------------------------------------------*/ -+ -+static unsigned buflen = 4096; -+static unsigned qlen = 32; -+static unsigned pattern = 0; -+ -+module_param (buflen, uint, S_IRUGO|S_IWUSR); -+module_param (qlen, uint, S_IRUGO|S_IWUSR); -+module_param (pattern, uint, S_IRUGO|S_IWUSR); -+ -+/* -+ * if it's nonzero, autoresume says how many seconds to wait -+ * before trying to wake up the host after suspend. -+ */ -+static unsigned autoresume = 0; -+module_param (autoresume, uint, 0); -+ -+/* -+ * Normally the "loopback" configuration is second (index 1) so -+ * it's not the default. Here's where to change that order, to -+ * work better with hosts where config changes are problematic. -+ * Or controllers (like superh) that only support one config. -+ */ -+static int loopdefault = 0; -+ -+module_param (loopdefault, bool, S_IRUGO|S_IWUSR); -+ -+/*-------------------------------------------------------------------------*/ -+ -+/* Thanks to NetChip Technologies for donating this product ID. -+ * -+ * DO NOT REUSE THESE IDs with a protocol-incompatible driver!! Ever!! -+ * Instead: allocate your own, using normal USB-IF procedures. -+ */ -+#ifndef CONFIG_USB_ZERO_HNPTEST -+#define DRIVER_VENDOR_NUM 0x0525 /* NetChip */ -+#define DRIVER_PRODUCT_NUM 0xa4a0 /* Linux-USB "Gadget Zero" */ -+#else -+#define DRIVER_VENDOR_NUM 0x1a0a /* OTG test device IDs */ -+#define DRIVER_PRODUCT_NUM 0xbadd -+#endif -+ -+/*-------------------------------------------------------------------------*/ -+ -+/* -+ * DESCRIPTORS ... most are static, but strings and (full) -+ * configuration descriptors are built on demand. -+ */ -+ -+/* -+#define STRING_MANUFACTURER 25 -+#define STRING_PRODUCT 42 -+#define STRING_SERIAL 101 -+*/ -+#define STRING_MANUFACTURER 1 -+#define STRING_PRODUCT 2 -+#define STRING_SERIAL 3 -+ -+#define STRING_SOURCE_SINK 250 -+#define STRING_LOOPBACK 251 -+ -+/* -+ * This device advertises two configurations; these numbers work -+ * on a pxa250 as well as more flexible hardware. -+ */ -+#define CONFIG_SOURCE_SINK 3 -+#define CONFIG_LOOPBACK 2 -+ -+/* -+static struct usb_device_descriptor -+device_desc = { -+ .bLength = sizeof device_desc, -+ .bDescriptorType = USB_DT_DEVICE, -+ -+ .bcdUSB = __constant_cpu_to_le16 (0x0200), -+ .bDeviceClass = USB_CLASS_VENDOR_SPEC, -+ -+ .idVendor = __constant_cpu_to_le16 (DRIVER_VENDOR_NUM), -+ .idProduct = __constant_cpu_to_le16 (DRIVER_PRODUCT_NUM), -+ .iManufacturer = STRING_MANUFACTURER, -+ .iProduct = STRING_PRODUCT, -+ .iSerialNumber = STRING_SERIAL, -+ .bNumConfigurations = 2, -+}; -+*/ -+static struct usb_device_descriptor -+device_desc = { -+ .bLength = sizeof device_desc, -+ .bDescriptorType = USB_DT_DEVICE, -+ .bcdUSB = __constant_cpu_to_le16 (0x0100), -+ .bDeviceClass = USB_CLASS_PER_INTERFACE, -+ .bDeviceSubClass = 0, -+ .bDeviceProtocol = 0, -+ .bMaxPacketSize0 = 64, -+ .bcdDevice = __constant_cpu_to_le16 (0x0100), -+ .idVendor = __constant_cpu_to_le16 (0x0499), -+ .idProduct = __constant_cpu_to_le16 (0x3002), -+ .iManufacturer = STRING_MANUFACTURER, -+ .iProduct = STRING_PRODUCT, -+ .iSerialNumber = STRING_SERIAL, -+ .bNumConfigurations = 1, -+}; -+ -+static struct usb_config_descriptor -+z_config = { -+ .bLength = sizeof z_config, -+ .bDescriptorType = USB_DT_CONFIG, -+ -+ /* compute wTotalLength on the fly */ -+ .bNumInterfaces = 2, -+ .bConfigurationValue = 1, -+ .iConfiguration = 0, -+ .bmAttributes = 0x40, -+ .bMaxPower = 0, /* self-powered */ -+}; -+ -+ -+static struct usb_otg_descriptor -+otg_descriptor = { -+ .bLength = sizeof otg_descriptor, -+ .bDescriptorType = USB_DT_OTG, -+ -+ .bmAttributes = USB_OTG_SRP, -+}; -+ -+/* one interface in each configuration */ -+#ifdef CONFIG_USB_GADGET_DUALSPEED -+ -+/* -+ * usb 2.0 devices need to expose both high speed and full speed -+ * descriptors, unless they only run at full speed. -+ * -+ * that means alternate endpoint descriptors (bigger packets) -+ * and a "device qualifier" ... plus more construction options -+ * for the config descriptor. -+ */ -+ -+static struct usb_qualifier_descriptor -+dev_qualifier = { -+ .bLength = sizeof dev_qualifier, -+ .bDescriptorType = USB_DT_DEVICE_QUALIFIER, -+ -+ .bcdUSB = __constant_cpu_to_le16 (0x0200), -+ .bDeviceClass = USB_CLASS_VENDOR_SPEC, -+ -+ .bNumConfigurations = 2, -+}; -+ -+ -+struct usb_cs_as_general_descriptor { -+ __u8 bLength; -+ __u8 bDescriptorType; -+ -+ __u8 bDescriptorSubType; -+ __u8 bTerminalLink; -+ __u8 bDelay; -+ __u16 wFormatTag; -+} __attribute__ ((packed)); -+ -+struct usb_cs_as_format_descriptor { -+ __u8 bLength; -+ __u8 bDescriptorType; -+ -+ __u8 bDescriptorSubType; -+ __u8 bFormatType; -+ __u8 bNrChannels; -+ __u8 bSubframeSize; -+ __u8 bBitResolution; -+ __u8 bSamfreqType; -+ __u8 tLowerSamFreq[3]; -+ __u8 tUpperSamFreq[3]; -+} __attribute__ ((packed)); -+ -+static const struct usb_interface_descriptor -+z_audio_control_if_desc = { -+ .bLength = sizeof z_audio_control_if_desc, -+ .bDescriptorType = USB_DT_INTERFACE, -+ .bInterfaceNumber = 0, -+ .bAlternateSetting = 0, -+ .bNumEndpoints = 0, -+ .bInterfaceClass = USB_CLASS_AUDIO, -+ .bInterfaceSubClass = 0x1, -+ .bInterfaceProtocol = 0, -+ .iInterface = 0, -+}; -+ -+static const struct usb_interface_descriptor -+z_audio_if_desc = { -+ .bLength = sizeof z_audio_if_desc, -+ .bDescriptorType = USB_DT_INTERFACE, -+ .bInterfaceNumber = 1, -+ .bAlternateSetting = 0, -+ .bNumEndpoints = 0, -+ .bInterfaceClass = USB_CLASS_AUDIO, -+ .bInterfaceSubClass = 0x2, -+ .bInterfaceProtocol = 0, -+ .iInterface = 0, -+}; -+ -+static const struct usb_interface_descriptor -+z_audio_if_desc2 = { -+ .bLength = sizeof z_audio_if_desc, -+ .bDescriptorType = USB_DT_INTERFACE, -+ .bInterfaceNumber = 1, -+ .bAlternateSetting = 1, -+ .bNumEndpoints = 1, -+ .bInterfaceClass = USB_CLASS_AUDIO, -+ .bInterfaceSubClass = 0x2, -+ .bInterfaceProtocol = 0, -+ .iInterface = 0, -+}; -+ -+static const struct usb_cs_as_general_descriptor -+z_audio_cs_as_if_desc = { -+ .bLength = 7, -+ .bDescriptorType = 0x24, -+ -+ .bDescriptorSubType = 0x01, -+ .bTerminalLink = 0x01, -+ .bDelay = 0x0, -+ .wFormatTag = __constant_cpu_to_le16 (0x0001) -+}; -+ -+ -+static const struct usb_cs_as_format_descriptor -+z_audio_cs_as_format_desc = { -+ .bLength = 0xe, -+ .bDescriptorType = 0x24, -+ -+ .bDescriptorSubType = 2, -+ .bFormatType = 1, -+ .bNrChannels = 1, -+ .bSubframeSize = 1, -+ .bBitResolution = 8, -+ .bSamfreqType = 0, -+ .tLowerSamFreq = {0x7e, 0x13, 0x00}, -+ .tUpperSamFreq = {0xe2, 0xd6, 0x00}, -+}; -+ -+static const struct usb_endpoint_descriptor -+z_iso_ep = { -+ .bLength = 0x09, -+ .bDescriptorType = 0x05, -+ .bEndpointAddress = 0x04, -+ .bmAttributes = 0x09, -+ .wMaxPacketSize = 0x0038, -+ .bInterval = 0x01, -+ .bRefresh = 0x00, -+ .bSynchAddress = 0x00, -+}; -+ -+static char z_iso_ep2[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; -+ -+// 9 bytes -+static char z_ac_interface_header_desc[] = -+{ 0x09, 0x24, 0x01, 0x00, 0x01, 0x2b, 0x00, 0x01, 0x01 }; -+ -+// 12 bytes -+static char z_0[] = {0x0c, 0x24, 0x02, 0x01, 0x01, 0x01, 0x00, 0x02, -+ 0x03, 0x00, 0x00, 0x00}; -+// 13 bytes -+static char z_1[] = {0x0d, 0x24, 0x06, 0x02, 0x01, 0x02, 0x15, 0x00, -+ 0x02, 0x00, 0x02, 0x00, 0x00}; -+// 9 bytes -+static char z_2[] = {0x09, 0x24, 0x03, 0x03, 0x01, 0x03, 0x00, 0x02, -+ 0x00}; -+ -+static char za_0[] = {0x09, 0x04, 0x01, 0x02, 0x01, 0x01, 0x02, 0x00, -+ 0x00}; -+ -+static char za_1[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00}; -+ -+static char za_2[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x01, 0x08, 0x00, -+ 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00}; -+ -+static char za_3[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00, -+ 0x00}; -+ -+static char za_4[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; -+ -+static char za_5[] = {0x09, 0x04, 0x01, 0x03, 0x01, 0x01, 0x02, 0x00, -+ 0x00}; -+ -+static char za_6[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00}; -+ -+static char za_7[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x02, 0x10, 0x00, -+ 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00}; -+ -+static char za_8[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00, -+ 0x00}; -+ -+static char za_9[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; -+ -+static char za_10[] = {0x09, 0x04, 0x01, 0x04, 0x01, 0x01, 0x02, 0x00, -+ 0x00}; -+ -+static char za_11[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00}; -+ -+static char za_12[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x02, 0x10, 0x00, -+ 0x73, 0x13, 0x00, 0xe2, 0xd6, 0x00}; -+ -+static char za_13[] = {0x09, 0x05, 0x04, 0x09, 0xe0, 0x00, 0x01, 0x00, -+ 0x00}; -+ -+static char za_14[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; -+ -+static char za_15[] = {0x09, 0x04, 0x01, 0x05, 0x01, 0x01, 0x02, 0x00, -+ 0x00}; -+ -+static char za_16[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00}; -+ -+static char za_17[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x03, 0x14, 0x00, -+ 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00}; -+ -+static char za_18[] = {0x09, 0x05, 0x04, 0x09, 0xa8, 0x00, 0x01, 0x00, -+ 0x00}; -+ -+static char za_19[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; -+ -+static char za_20[] = {0x09, 0x04, 0x01, 0x06, 0x01, 0x01, 0x02, 0x00, -+ 0x00}; -+ -+static char za_21[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00}; -+ -+static char za_22[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x03, 0x14, 0x00, -+ 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00}; -+ -+static char za_23[] = {0x09, 0x05, 0x04, 0x09, 0x50, 0x01, 0x01, 0x00, -+ 0x00}; -+ -+static char za_24[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; -+ -+ -+ -+static const struct usb_descriptor_header *z_function [] = { -+ (struct usb_descriptor_header *) &z_audio_control_if_desc, -+ (struct usb_descriptor_header *) &z_ac_interface_header_desc, -+ (struct usb_descriptor_header *) &z_0, -+ (struct usb_descriptor_header *) &z_1, -+ (struct usb_descriptor_header *) &z_2, -+ (struct usb_descriptor_header *) &z_audio_if_desc, -+ (struct usb_descriptor_header *) &z_audio_if_desc2, -+ (struct usb_descriptor_header *) &z_audio_cs_as_if_desc, -+ (struct usb_descriptor_header *) &z_audio_cs_as_format_desc, -+ (struct usb_descriptor_header *) &z_iso_ep, -+ (struct usb_descriptor_header *) &z_iso_ep2, -+ (struct usb_descriptor_header *) &za_0, -+ (struct usb_descriptor_header *) &za_1, -+ (struct usb_descriptor_header *) &za_2, -+ (struct usb_descriptor_header *) &za_3, -+ (struct usb_descriptor_header *) &za_4, -+ (struct usb_descriptor_header *) &za_5, -+ (struct usb_descriptor_header *) &za_6, -+ (struct usb_descriptor_header *) &za_7, -+ (struct usb_descriptor_header *) &za_8, -+ (struct usb_descriptor_header *) &za_9, -+ (struct usb_descriptor_header *) &za_10, -+ (struct usb_descriptor_header *) &za_11, -+ (struct usb_descriptor_header *) &za_12, -+ (struct usb_descriptor_header *) &za_13, -+ (struct usb_descriptor_header *) &za_14, -+ (struct usb_descriptor_header *) &za_15, -+ (struct usb_descriptor_header *) &za_16, -+ (struct usb_descriptor_header *) &za_17, -+ (struct usb_descriptor_header *) &za_18, -+ (struct usb_descriptor_header *) &za_19, -+ (struct usb_descriptor_header *) &za_20, -+ (struct usb_descriptor_header *) &za_21, -+ (struct usb_descriptor_header *) &za_22, -+ (struct usb_descriptor_header *) &za_23, -+ (struct usb_descriptor_header *) &za_24, -+ NULL, -+}; -+ -+/* maxpacket and other transfer characteristics vary by speed. */ -+#define ep_desc(g,hs,fs) (((g)->speed==USB_SPEED_HIGH)?(hs):(fs)) -+ -+#else -+ -+/* if there's no high speed support, maxpacket doesn't change. */ -+#define ep_desc(g,hs,fs) fs -+ -+#endif /* !CONFIG_USB_GADGET_DUALSPEED */ -+ -+static char manufacturer [40]; -+//static char serial [40]; -+static char serial [] = "Ser 00 em"; -+ -+/* static strings, in UTF-8 */ -+static struct usb_string strings [] = { -+ { STRING_MANUFACTURER, manufacturer, }, -+ { STRING_PRODUCT, longname, }, -+ { STRING_SERIAL, serial, }, -+ { STRING_LOOPBACK, loopback, }, -+ { STRING_SOURCE_SINK, source_sink, }, -+ { } /* end of list */ -+}; -+ -+static struct usb_gadget_strings stringtab = { -+ .language = 0x0409, /* en-us */ -+ .strings = strings, -+}; -+ -+/* -+ * config descriptors are also handcrafted. these must agree with code -+ * that sets configurations, and with code managing interfaces and their -+ * altsettings. other complexity may come from: -+ * -+ * - high speed support, including "other speed config" rules -+ * - multiple configurations -+ * - interfaces with alternate settings -+ * - embedded class or vendor-specific descriptors -+ * -+ * this handles high speed, and has a second config that could as easily -+ * have been an alternate interface setting (on most hardware). -+ * -+ * NOTE: to demonstrate (and test) more USB capabilities, this driver -+ * should include an altsetting to test interrupt transfers, including -+ * high bandwidth modes at high speed. (Maybe work like Intel's test -+ * device?) -+ */ -+static int -+config_buf (struct usb_gadget *gadget, u8 *buf, u8 type, unsigned index) -+{ -+ int len; -+ const struct usb_descriptor_header **function; -+ -+ function = z_function; -+ len = usb_gadget_config_buf (&z_config, buf, USB_BUFSIZ, function); -+ if (len < 0) -+ return len; -+ ((struct usb_config_descriptor *) buf)->bDescriptorType = type; -+ return len; -+} -+ -+/*-------------------------------------------------------------------------*/ -+ -+static struct usb_request * -+alloc_ep_req (struct usb_ep *ep, unsigned length) -+{ -+ struct usb_request *req; -+ -+ req = usb_ep_alloc_request (ep, GFP_ATOMIC); -+ if (req) { -+ req->length = length; -+ req->buf = usb_ep_alloc_buffer (ep, length, -+ &req->dma, GFP_ATOMIC); -+ if (!req->buf) { -+ usb_ep_free_request (ep, req); -+ req = NULL; -+ } -+ } -+ return req; -+} -+ -+static void free_ep_req (struct usb_ep *ep, struct usb_request *req) -+{ -+ if (req->buf) -+ usb_ep_free_buffer (ep, req->buf, req->dma, req->length); -+ usb_ep_free_request (ep, req); -+} -+ -+/*-------------------------------------------------------------------------*/ -+ -+/* optionally require specific source/sink data patterns */ -+ -+static int -+check_read_data ( -+ struct zero_dev *dev, -+ struct usb_ep *ep, -+ struct usb_request *req -+) -+{ -+ unsigned i; -+ u8 *buf = req->buf; -+ -+ for (i = 0; i < req->actual; i++, buf++) { -+ switch (pattern) { -+ /* all-zeroes has no synchronization issues */ -+ case 0: -+ if (*buf == 0) -+ continue; -+ break; -+ /* mod63 stays in sync with short-terminated transfers, -+ * or otherwise when host and gadget agree on how large -+ * each usb transfer request should be. resync is done -+ * with set_interface or set_config. -+ */ -+ case 1: -+ if (*buf == (u8)(i % 63)) -+ continue; -+ break; -+ } -+ ERROR (dev, "bad OUT byte, buf [%d] = %d\n", i, *buf); -+ usb_ep_set_halt (ep); -+ return -EINVAL; -+ } -+ return 0; -+} -+ -+/*-------------------------------------------------------------------------*/ -+ -+static void zero_reset_config (struct zero_dev *dev) -+{ -+ if (dev->config == 0) -+ return; -+ -+ DBG (dev, "reset config\n"); -+ -+ /* just disable endpoints, forcing completion of pending i/o. -+ * all our completion handlers free their requests in this case. -+ */ -+ if (dev->in_ep) { -+ usb_ep_disable (dev->in_ep); -+ dev->in_ep = NULL; -+ } -+ if (dev->out_ep) { -+ usb_ep_disable (dev->out_ep); -+ dev->out_ep = NULL; -+ } -+ dev->config = 0; -+ del_timer (&dev->resume); -+} -+ -+#define _write(f, buf, sz) (f->f_op->write(f, buf, sz, &f->f_pos)) -+ -+static void -+zero_isoc_complete (struct usb_ep *ep, struct usb_request *req) -+{ -+ struct zero_dev *dev = ep->driver_data; -+ int status = req->status; -+ int i, j; -+ -+ switch (status) { -+ -+ case 0: /* normal completion? */ -+ //printk ("\nzero ---------------> isoc normal completion %d bytes\n", req->actual); -+ for (i=0, j=rbuf_start; iactual; i++) { -+ //printk ("%02x ", ((__u8*)req->buf)[i]); -+ rbuf[j] = ((__u8*)req->buf)[i]; -+ j++; -+ if (j >= RBUF_LEN) j=0; -+ } -+ rbuf_start = j; -+ //printk ("\n\n"); -+ -+ if (rbuf_len < RBUF_LEN) { -+ rbuf_len += req->actual; -+ if (rbuf_len > RBUF_LEN) { -+ rbuf_len = RBUF_LEN; -+ } -+ } -+ -+ break; -+ -+ /* this endpoint is normally active while we're configured */ -+ case -ECONNABORTED: /* hardware forced ep reset */ -+ case -ECONNRESET: /* request dequeued */ -+ case -ESHUTDOWN: /* disconnect from host */ -+ VDBG (dev, "%s gone (%d), %d/%d\n", ep->name, status, -+ req->actual, req->length); -+ if (ep == dev->out_ep) -+ check_read_data (dev, ep, req); -+ free_ep_req (ep, req); -+ return; -+ -+ case -EOVERFLOW: /* buffer overrun on read means that -+ * we didn't provide a big enough -+ * buffer. -+ */ -+ default: -+#if 1 -+ DBG (dev, "%s complete --> %d, %d/%d\n", ep->name, -+ status, req->actual, req->length); -+#endif -+ case -EREMOTEIO: /* short read */ -+ break; -+ } -+ -+ status = usb_ep_queue (ep, req, GFP_ATOMIC); -+ if (status) { -+ ERROR (dev, "kill %s: resubmit %d bytes --> %d\n", -+ ep->name, req->length, status); -+ usb_ep_set_halt (ep); -+ /* FIXME recover later ... somehow */ -+ } -+} -+ -+static struct usb_request * -+zero_start_isoc_ep (struct usb_ep *ep, int gfp_flags) -+{ -+ struct usb_request *req; -+ int status; -+ -+ req = alloc_ep_req (ep, 512); -+ if (!req) -+ return NULL; -+ -+ req->complete = zero_isoc_complete; -+ -+ status = usb_ep_queue (ep, req, gfp_flags); -+ if (status) { -+ struct zero_dev *dev = ep->driver_data; -+ -+ ERROR (dev, "start %s --> %d\n", ep->name, status); -+ free_ep_req (ep, req); -+ req = NULL; -+ } -+ -+ return req; -+} -+ -+/* change our operational config. this code must agree with the code -+ * that returns config descriptors, and altsetting code. -+ * -+ * it's also responsible for power management interactions. some -+ * configurations might not work with our current power sources. -+ * -+ * note that some device controller hardware will constrain what this -+ * code can do, perhaps by disallowing more than one configuration or -+ * by limiting configuration choices (like the pxa2xx). -+ */ -+static int -+zero_set_config (struct zero_dev *dev, unsigned number, int gfp_flags) -+{ -+ int result = 0; -+ struct usb_gadget *gadget = dev->gadget; -+ const struct usb_endpoint_descriptor *d; -+ struct usb_ep *ep; -+ -+ if (number == dev->config) -+ return 0; -+ -+ zero_reset_config (dev); -+ -+ gadget_for_each_ep (ep, gadget) { -+ -+ if (strcmp (ep->name, "ep4") == 0) { -+ -+ d = (struct usb_endpoint_descripter *)&za_23; // isoc ep desc for audio i/f alt setting 6 -+ result = usb_ep_enable (ep, d); -+ -+ if (result == 0) { -+ ep->driver_data = dev; -+ dev->in_ep = ep; -+ -+ if (zero_start_isoc_ep (ep, gfp_flags) != 0) { -+ -+ dev->in_ep = ep; -+ continue; -+ } -+ -+ usb_ep_disable (ep); -+ result = -EIO; -+ } -+ } -+ -+ } -+ -+ dev->config = number; -+ return result; -+} -+ -+/*-------------------------------------------------------------------------*/ -+ -+static void zero_setup_complete (struct usb_ep *ep, struct usb_request *req) -+{ -+ if (req->status || req->actual != req->length) -+ DBG ((struct zero_dev *) ep->driver_data, -+ "setup complete --> %d, %d/%d\n", -+ req->status, req->actual, req->length); -+} -+ -+/* -+ * The setup() callback implements all the ep0 functionality that's -+ * not handled lower down, in hardware or the hardware driver (like -+ * device and endpoint feature flags, and their status). It's all -+ * housekeeping for the gadget function we're implementing. Most of -+ * the work is in config-specific setup. -+ */ -+static int -+zero_setup (struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl) -+{ -+ struct zero_dev *dev = get_gadget_data (gadget); -+ struct usb_request *req = dev->req; -+ int value = -EOPNOTSUPP; -+ -+ /* usually this stores reply data in the pre-allocated ep0 buffer, -+ * but config change events will reconfigure hardware. -+ */ -+ req->zero = 0; -+ switch (ctrl->bRequest) { -+ -+ case USB_REQ_GET_DESCRIPTOR: -+ -+ switch (ctrl->wValue >> 8) { -+ -+ case USB_DT_DEVICE: -+ value = min (ctrl->wLength, (u16) sizeof device_desc); -+ memcpy (req->buf, &device_desc, value); -+ break; -+#ifdef CONFIG_USB_GADGET_DUALSPEED -+ case USB_DT_DEVICE_QUALIFIER: -+ if (!gadget->is_dualspeed) -+ break; -+ value = min (ctrl->wLength, (u16) sizeof dev_qualifier); -+ memcpy (req->buf, &dev_qualifier, value); -+ break; -+ -+ case USB_DT_OTHER_SPEED_CONFIG: -+ if (!gadget->is_dualspeed) -+ break; -+ // FALLTHROUGH -+#endif /* CONFIG_USB_GADGET_DUALSPEED */ -+ case USB_DT_CONFIG: -+ value = config_buf (gadget, req->buf, -+ ctrl->wValue >> 8, -+ ctrl->wValue & 0xff); -+ if (value >= 0) -+ value = min (ctrl->wLength, (u16) value); -+ break; -+ -+ case USB_DT_STRING: -+ /* wIndex == language code. -+ * this driver only handles one language, you can -+ * add string tables for other languages, using -+ * any UTF-8 characters -+ */ -+ value = usb_gadget_get_string (&stringtab, -+ ctrl->wValue & 0xff, req->buf); -+ if (value >= 0) { -+ value = min (ctrl->wLength, (u16) value); -+ } -+ break; -+ } -+ break; -+ -+ /* currently two configs, two speeds */ -+ case USB_REQ_SET_CONFIGURATION: -+ if (ctrl->bRequestType != 0) -+ goto unknown; -+ -+ spin_lock (&dev->lock); -+ value = zero_set_config (dev, ctrl->wValue, GFP_ATOMIC); -+ spin_unlock (&dev->lock); -+ break; -+ case USB_REQ_GET_CONFIGURATION: -+ if (ctrl->bRequestType != USB_DIR_IN) -+ goto unknown; -+ *(u8 *)req->buf = dev->config; -+ value = min (ctrl->wLength, (u16) 1); -+ break; -+ -+ /* until we add altsetting support, or other interfaces, -+ * only 0/0 are possible. pxa2xx only supports 0/0 (poorly) -+ * and already killed pending endpoint I/O. -+ */ -+ case USB_REQ_SET_INTERFACE: -+ -+ if (ctrl->bRequestType != USB_RECIP_INTERFACE) -+ goto unknown; -+ spin_lock (&dev->lock); -+ if (dev->config) { -+ u8 config = dev->config; -+ -+ /* resets interface configuration, forgets about -+ * previous transaction state (queued bufs, etc) -+ * and re-inits endpoint state (toggle etc) -+ * no response queued, just zero status == success. -+ * if we had more than one interface we couldn't -+ * use this "reset the config" shortcut. -+ */ -+ zero_reset_config (dev); -+ zero_set_config (dev, config, GFP_ATOMIC); -+ value = 0; -+ } -+ spin_unlock (&dev->lock); -+ break; -+ case USB_REQ_GET_INTERFACE: -+ if ((ctrl->bRequestType == 0x21) && (ctrl->wIndex == 0x02)) { -+ value = ctrl->wLength; -+ break; -+ } -+ else { -+ if (ctrl->bRequestType != (USB_DIR_IN|USB_RECIP_INTERFACE)) -+ goto unknown; -+ if (!dev->config) -+ break; -+ if (ctrl->wIndex != 0) { -+ value = -EDOM; -+ break; -+ } -+ *(u8 *)req->buf = 0; -+ value = min (ctrl->wLength, (u16) 1); -+ } -+ break; -+ -+ /* -+ * These are the same vendor-specific requests supported by -+ * Intel's USB 2.0 compliance test devices. We exceed that -+ * device spec by allowing multiple-packet requests. -+ */ -+ case 0x5b: /* control WRITE test -- fill the buffer */ -+ if (ctrl->bRequestType != (USB_DIR_OUT|USB_TYPE_VENDOR)) -+ goto unknown; -+ if (ctrl->wValue || ctrl->wIndex) -+ break; -+ /* just read that many bytes into the buffer */ -+ if (ctrl->wLength > USB_BUFSIZ) -+ break; -+ value = ctrl->wLength; -+ break; -+ case 0x5c: /* control READ test -- return the buffer */ -+ if (ctrl->bRequestType != (USB_DIR_IN|USB_TYPE_VENDOR)) -+ goto unknown; -+ if (ctrl->wValue || ctrl->wIndex) -+ break; -+ /* expect those bytes are still in the buffer; send back */ -+ if (ctrl->wLength > USB_BUFSIZ -+ || ctrl->wLength != req->length) -+ break; -+ value = ctrl->wLength; -+ break; -+ -+ case 0x01: // SET_CUR -+ case 0x02: -+ case 0x03: -+ case 0x04: -+ case 0x05: -+ value = ctrl->wLength; -+ break; -+ case 0x81: -+ switch (ctrl->wValue) { -+ case 0x0201: -+ case 0x0202: -+ ((u8*)req->buf)[0] = 0x00; -+ ((u8*)req->buf)[1] = 0xe3; -+ break; -+ case 0x0300: -+ case 0x0500: -+ ((u8*)req->buf)[0] = 0x00; -+ break; -+ } -+ //((u8*)req->buf)[0] = 0x81; -+ //((u8*)req->buf)[1] = 0x81; -+ value = ctrl->wLength; -+ break; -+ case 0x82: -+ switch (ctrl->wValue) { -+ case 0x0201: -+ case 0x0202: -+ ((u8*)req->buf)[0] = 0x00; -+ ((u8*)req->buf)[1] = 0xc3; -+ break; -+ case 0x0300: -+ case 0x0500: -+ ((u8*)req->buf)[0] = 0x00; -+ break; -+ } -+ //((u8*)req->buf)[0] = 0x82; -+ //((u8*)req->buf)[1] = 0x82; -+ value = ctrl->wLength; -+ break; -+ case 0x83: -+ switch (ctrl->wValue) { -+ case 0x0201: -+ case 0x0202: -+ ((u8*)req->buf)[0] = 0x00; -+ ((u8*)req->buf)[1] = 0x00; -+ break; -+ case 0x0300: -+ ((u8*)req->buf)[0] = 0x60; -+ break; -+ case 0x0500: -+ ((u8*)req->buf)[0] = 0x18; -+ break; -+ } -+ //((u8*)req->buf)[0] = 0x83; -+ //((u8*)req->buf)[1] = 0x83; -+ value = ctrl->wLength; -+ break; -+ case 0x84: -+ switch (ctrl->wValue) { -+ case 0x0201: -+ case 0x0202: -+ ((u8*)req->buf)[0] = 0x00; -+ ((u8*)req->buf)[1] = 0x01; -+ break; -+ case 0x0300: -+ case 0x0500: -+ ((u8*)req->buf)[0] = 0x08; -+ break; -+ } -+ //((u8*)req->buf)[0] = 0x84; -+ //((u8*)req->buf)[1] = 0x84; -+ value = ctrl->wLength; -+ break; -+ case 0x85: -+ ((u8*)req->buf)[0] = 0x85; -+ ((u8*)req->buf)[1] = 0x85; -+ value = ctrl->wLength; -+ break; -+ -+ -+ default: -+unknown: -+ printk("unknown control req%02x.%02x v%04x i%04x l%d\n", -+ ctrl->bRequestType, ctrl->bRequest, -+ ctrl->wValue, ctrl->wIndex, ctrl->wLength); -+ } -+ -+ /* respond with data transfer before status phase? */ -+ if (value >= 0) { -+ req->length = value; -+ req->zero = value < ctrl->wLength -+ && (value % gadget->ep0->maxpacket) == 0; -+ value = usb_ep_queue (gadget->ep0, req, GFP_ATOMIC); -+ if (value < 0) { -+ DBG (dev, "ep_queue < 0 --> %d\n", value); -+ req->status = 0; -+ zero_setup_complete (gadget->ep0, req); -+ } -+ } -+ -+ /* device either stalls (value < 0) or reports success */ -+ return value; -+} -+ -+static void -+zero_disconnect (struct usb_gadget *gadget) -+{ -+ struct zero_dev *dev = get_gadget_data (gadget); -+ unsigned long flags; -+ -+ spin_lock_irqsave (&dev->lock, flags); -+ zero_reset_config (dev); -+ -+ /* a more significant application might have some non-usb -+ * activities to quiesce here, saving resources like power -+ * or pushing the notification up a network stack. -+ */ -+ spin_unlock_irqrestore (&dev->lock, flags); -+ -+ /* next we may get setup() calls to enumerate new connections; -+ * or an unbind() during shutdown (including removing module). -+ */ -+} -+ -+static void -+zero_autoresume (unsigned long _dev) -+{ -+ struct zero_dev *dev = (struct zero_dev *) _dev; -+ int status; -+ -+ /* normally the host would be woken up for something -+ * more significant than just a timer firing... -+ */ -+ if (dev->gadget->speed != USB_SPEED_UNKNOWN) { -+ status = usb_gadget_wakeup (dev->gadget); -+ DBG (dev, "wakeup --> %d\n", status); -+ } -+} -+ -+/*-------------------------------------------------------------------------*/ -+ -+static void -+zero_unbind (struct usb_gadget *gadget) -+{ -+ struct zero_dev *dev = get_gadget_data (gadget); -+ -+ DBG (dev, "unbind\n"); -+ -+ /* we've already been disconnected ... no i/o is active */ -+ if (dev->req) -+ free_ep_req (gadget->ep0, dev->req); -+ del_timer_sync (&dev->resume); -+ kfree (dev); -+ set_gadget_data (gadget, NULL); -+} -+ -+static int -+zero_bind (struct usb_gadget *gadget) -+{ -+ struct zero_dev *dev; -+ //struct usb_ep *ep; -+ -+ printk("binding\n"); -+ /* -+ * DRIVER POLICY CHOICE: you may want to do this differently. -+ * One thing to avoid is reusing a bcdDevice revision code -+ * with different host-visible configurations or behavior -+ * restrictions -- using ep1in/ep2out vs ep1out/ep3in, etc -+ */ -+ //device_desc.bcdDevice = __constant_cpu_to_le16 (0x0201); -+ -+ -+ /* ok, we made sense of the hardware ... */ -+ dev = kmalloc (sizeof *dev, SLAB_KERNEL); -+ if (!dev) -+ return -ENOMEM; -+ memset (dev, 0, sizeof *dev); -+ spin_lock_init (&dev->lock); -+ dev->gadget = gadget; -+ set_gadget_data (gadget, dev); -+ -+ /* preallocate control response and buffer */ -+ dev->req = usb_ep_alloc_request (gadget->ep0, GFP_KERNEL); -+ if (!dev->req) -+ goto enomem; -+ dev->req->buf = usb_ep_alloc_buffer (gadget->ep0, USB_BUFSIZ, -+ &dev->req->dma, GFP_KERNEL); -+ if (!dev->req->buf) -+ goto enomem; -+ -+ dev->req->complete = zero_setup_complete; -+ -+ device_desc.bMaxPacketSize0 = gadget->ep0->maxpacket; -+ -+#ifdef CONFIG_USB_GADGET_DUALSPEED -+ /* assume ep0 uses the same value for both speeds ... */ -+ dev_qualifier.bMaxPacketSize0 = device_desc.bMaxPacketSize0; -+ -+ /* and that all endpoints are dual-speed */ -+ //hs_source_desc.bEndpointAddress = fs_source_desc.bEndpointAddress; -+ //hs_sink_desc.bEndpointAddress = fs_sink_desc.bEndpointAddress; -+#endif -+ -+ usb_gadget_set_selfpowered (gadget); -+ -+ init_timer (&dev->resume); -+ dev->resume.function = zero_autoresume; -+ dev->resume.data = (unsigned long) dev; -+ -+ gadget->ep0->driver_data = dev; -+ -+ INFO (dev, "%s, version: " DRIVER_VERSION "\n", longname); -+ INFO (dev, "using %s, OUT %s IN %s\n", gadget->name, -+ EP_OUT_NAME, EP_IN_NAME); -+ -+ snprintf (manufacturer, sizeof manufacturer, -+ UTS_SYSNAME " " UTS_RELEASE " with %s", -+ gadget->name); -+ -+ return 0; -+ -+enomem: -+ zero_unbind (gadget); -+ return -ENOMEM; -+} -+ -+/*-------------------------------------------------------------------------*/ -+ -+static void -+zero_suspend (struct usb_gadget *gadget) -+{ -+ struct zero_dev *dev = get_gadget_data (gadget); -+ -+ if (gadget->speed == USB_SPEED_UNKNOWN) -+ return; -+ -+ if (autoresume) { -+ mod_timer (&dev->resume, jiffies + (HZ * autoresume)); -+ DBG (dev, "suspend, wakeup in %d seconds\n", autoresume); -+ } else -+ DBG (dev, "suspend\n"); -+} -+ -+static void -+zero_resume (struct usb_gadget *gadget) -+{ -+ struct zero_dev *dev = get_gadget_data (gadget); -+ -+ DBG (dev, "resume\n"); -+ del_timer (&dev->resume); -+} -+ -+ -+/*-------------------------------------------------------------------------*/ -+ -+static struct usb_gadget_driver zero_driver = { -+#ifdef CONFIG_USB_GADGET_DUALSPEED -+ .speed = USB_SPEED_HIGH, -+#else -+ .speed = USB_SPEED_FULL, -+#endif -+ .function = (char *) longname, -+ .bind = zero_bind, -+ .unbind = zero_unbind, -+ -+ .setup = zero_setup, -+ .disconnect = zero_disconnect, -+ -+ .suspend = zero_suspend, -+ .resume = zero_resume, -+ -+ .driver = { -+ .name = (char *) shortname, -+ // .shutdown = ... -+ // .suspend = ... -+ // .resume = ... -+ }, -+}; -+ -+MODULE_AUTHOR ("David Brownell"); -+MODULE_LICENSE ("Dual BSD/GPL"); -+ -+static struct proc_dir_entry *pdir, *pfile; -+ -+static int isoc_read_data (char *page, char **start, -+ off_t off, int count, -+ int *eof, void *data) -+{ -+ int i; -+ static int c = 0; -+ static int done = 0; -+ static int s = 0; -+ -+/* -+ printk ("\ncount: %d\n", count); -+ printk ("rbuf_start: %d\n", rbuf_start); -+ printk ("rbuf_len: %d\n", rbuf_len); -+ printk ("off: %d\n", off); -+ printk ("start: %p\n\n", *start); -+*/ -+ if (done) { -+ c = 0; -+ done = 0; -+ *eof = 1; -+ return 0; -+ } -+ -+ if (c == 0) { -+ if (rbuf_len == RBUF_LEN) -+ s = rbuf_start; -+ else s = 0; -+ } -+ -+ for (i=0; i= rbuf_len) { -+ *eof = 1; -+ done = 1; -+ } -+ -+ -+ return i; -+} -+ -+static int __init init (void) -+{ -+ -+ int retval = 0; -+ -+ pdir = proc_mkdir("isoc_test", NULL); -+ if(pdir == NULL) { -+ retval = -ENOMEM; -+ printk("Error creating dir\n"); -+ goto done; -+ } -+ pdir->owner = THIS_MODULE; -+ -+ pfile = create_proc_read_entry("isoc_data", -+ 0444, pdir, -+ isoc_read_data, -+ NULL); -+ if (pfile == NULL) { -+ retval = -ENOMEM; -+ printk("Error creating file\n"); -+ goto no_file; -+ } -+ pfile->owner = THIS_MODULE; -+ -+ return usb_gadget_register_driver (&zero_driver); -+ -+ no_file: -+ remove_proc_entry("isoc_data", NULL); -+ done: -+ return retval; -+} -+module_init (init); -+ -+static void __exit cleanup (void) -+{ -+ -+ usb_gadget_unregister_driver (&zero_driver); -+ -+ remove_proc_entry("isoc_data", pdir); -+ remove_proc_entry("isoc_test", NULL); -+} -+module_exit (cleanup); -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_cfi_common.h linux-rpi/drivers/usb/host/dwc_otg/dwc_cfi_common.h ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_cfi_common.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_cfi_common.h 2015-11-29 09:42:39.915098960 +0100 -@@ -0,0 +1,142 @@ -+/* ========================================================================== -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+ -+#if !defined(__DWC_CFI_COMMON_H__) -+#define __DWC_CFI_COMMON_H__ -+ -+//#include -+ -+/** -+ * @file -+ * -+ * This file contains the CFI specific common constants, interfaces -+ * (functions and macros) and structures for Linux. No PCD specific -+ * data structure or definition is to be included in this file. -+ * -+ */ -+ -+/** This is a request for all Core Features */ -+#define VEN_CORE_GET_FEATURES 0xB1 -+ -+/** This is a request to get the value of a specific Core Feature */ -+#define VEN_CORE_GET_FEATURE 0xB2 -+ -+/** This command allows the host to set the value of a specific Core Feature */ -+#define VEN_CORE_SET_FEATURE 0xB3 -+ -+/** This command allows the host to set the default values of -+ * either all or any specific Core Feature -+ */ -+#define VEN_CORE_RESET_FEATURES 0xB4 -+ -+/** This command forces the PCD to write the deferred values of a Core Features */ -+#define VEN_CORE_ACTIVATE_FEATURES 0xB5 -+ -+/** This request reads a DWORD value from a register at the specified offset */ -+#define VEN_CORE_READ_REGISTER 0xB6 -+ -+/** This request writes a DWORD value into a register at the specified offset */ -+#define VEN_CORE_WRITE_REGISTER 0xB7 -+ -+/** This structure is the header of the Core Features dataset returned to -+ * the Host -+ */ -+struct cfi_all_features_header { -+/** The features header structure length is */ -+#define CFI_ALL_FEATURES_HDR_LEN 8 -+ /** -+ * The total length of the features dataset returned to the Host -+ */ -+ uint16_t wTotalLen; -+ -+ /** -+ * CFI version number inBinary-Coded Decimal (i.e., 1.00 is 100H). -+ * This field identifies the version of the CFI Specification with which -+ * the device is compliant. -+ */ -+ uint16_t wVersion; -+ -+ /** The ID of the Core */ -+ uint16_t wCoreID; -+#define CFI_CORE_ID_UDC 1 -+#define CFI_CORE_ID_OTG 2 -+#define CFI_CORE_ID_WUDEV 3 -+ -+ /** Number of features returned by VEN_CORE_GET_FEATURES request */ -+ uint16_t wNumFeatures; -+} UPACKED; -+ -+typedef struct cfi_all_features_header cfi_all_features_header_t; -+ -+/** This structure is a header of the Core Feature descriptor dataset returned to -+ * the Host after the VEN_CORE_GET_FEATURES request -+ */ -+struct cfi_feature_desc_header { -+#define CFI_FEATURE_DESC_HDR_LEN 8 -+ -+ /** The feature ID */ -+ uint16_t wFeatureID; -+ -+ /** Length of this feature descriptor in bytes - including the -+ * length of the feature name string -+ */ -+ uint16_t wLength; -+ -+ /** The data length of this feature in bytes */ -+ uint16_t wDataLength; -+ -+ /** -+ * Attributes of this features -+ * D0: Access rights -+ * 0 - Read/Write -+ * 1 - Read only -+ */ -+ uint8_t bmAttributes; -+#define CFI_FEATURE_ATTR_RO 1 -+#define CFI_FEATURE_ATTR_RW 0 -+ -+ /** Length of the feature name in bytes */ -+ uint8_t bNameLen; -+ -+ /** The feature name buffer */ -+ //uint8_t *name; -+} UPACKED; -+ -+typedef struct cfi_feature_desc_header cfi_feature_desc_header_t; -+ -+/** -+ * This structure describes a NULL terminated string referenced by its id field. -+ * It is very similar to usb_string structure but has the id field type set to 16-bit. -+ */ -+struct cfi_string { -+ uint16_t id; -+ const uint8_t *s; -+}; -+typedef struct cfi_string cfi_string_t; -+ -+#endif -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_adp.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_adp.c ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_adp.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_adp.c 2015-11-29 09:42:39.915098960 +0100 -@@ -0,0 +1,854 @@ -+/* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.c $ -+ * $Revision: #12 $ -+ * $Date: 2011/10/26 $ -+ * $Change: 1873028 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+ -+#include "dwc_os.h" -+#include "dwc_otg_regs.h" -+#include "dwc_otg_cil.h" -+#include "dwc_otg_adp.h" -+ -+/** @file -+ * -+ * This file contains the most of the Attach Detect Protocol implementation for -+ * the driver to support OTG Rev2.0. -+ * -+ */ -+ -+void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value) -+{ -+ adpctl_data_t adpctl; -+ -+ adpctl.d32 = value; -+ adpctl.b.ar = 0x2; -+ -+ DWC_WRITE_REG32(&core_if->core_global_regs->adpctl, adpctl.d32); -+ -+ while (adpctl.b.ar) { -+ adpctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->adpctl); -+ } -+ -+} -+ -+/** -+ * Function is called to read ADP registers -+ */ -+uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if) -+{ -+ adpctl_data_t adpctl; -+ -+ adpctl.d32 = 0; -+ adpctl.b.ar = 0x1; -+ -+ DWC_WRITE_REG32(&core_if->core_global_regs->adpctl, adpctl.d32); -+ -+ while (adpctl.b.ar) { -+ adpctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->adpctl); -+ } -+ -+ return adpctl.d32; -+} -+ -+/** -+ * Function is called to read ADPCTL register and filter Write-clear bits -+ */ -+uint32_t dwc_otg_adp_read_reg_filter(dwc_otg_core_if_t * core_if) -+{ -+ adpctl_data_t adpctl; -+ -+ adpctl.d32 = dwc_otg_adp_read_reg(core_if); -+ adpctl.b.adp_tmout_int = 0; -+ adpctl.b.adp_prb_int = 0; -+ adpctl.b.adp_tmout_int = 0; -+ -+ return adpctl.d32; -+} -+ -+/** -+ * Function is called to write ADP registers -+ */ -+void dwc_otg_adp_modify_reg(dwc_otg_core_if_t * core_if, uint32_t clr, -+ uint32_t set) -+{ -+ dwc_otg_adp_write_reg(core_if, -+ (dwc_otg_adp_read_reg(core_if) & (~clr)) | set); -+} -+ -+static void adp_sense_timeout(void *ptr) -+{ -+ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr; -+ core_if->adp.sense_timer_started = 0; -+ DWC_PRINTF("ADP SENSE TIMEOUT\n"); -+ if (core_if->adp_enable) { -+ dwc_otg_adp_sense_stop(core_if); -+ dwc_otg_adp_probe_start(core_if); -+ } -+} -+ -+/** -+ * This function is called when the ADP vbus timer expires. Timeout is 1.1s. -+ */ -+static void adp_vbuson_timeout(void *ptr) -+{ -+ gpwrdn_data_t gpwrdn; -+ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr; -+ hprt0_data_t hprt0 = {.d32 = 0 }; -+ pcgcctl_data_t pcgcctl = {.d32 = 0 }; -+ DWC_PRINTF("%s: 1.1 seconds expire after turning on VBUS\n",__FUNCTION__); -+ if (core_if) { -+ core_if->adp.vbuson_timer_started = 0; -+ /* Turn off vbus */ -+ hprt0.b.prtpwr = 1; -+ DWC_MODIFY_REG32(core_if->host_if->hprt0, hprt0.d32, 0); -+ gpwrdn.d32 = 0; -+ -+ /* Power off the core */ -+ if (core_if->power_down == 2) { -+ /* Enable Wakeup Logic */ -+// gpwrdn.b.wkupactiv = 1; -+ gpwrdn.b.pmuactv = 0; -+ gpwrdn.b.pwrdnrstn = 1; -+ gpwrdn.b.pwrdnclmp = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, -+ gpwrdn.d32); -+ -+ /* Suspend the Phy Clock */ -+ pcgcctl.b.stoppclk = 1; -+ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32); -+ -+ /* Switch on VDD */ -+// gpwrdn.b.wkupactiv = 1; -+ gpwrdn.b.pmuactv = 1; -+ gpwrdn.b.pwrdnrstn = 1; -+ gpwrdn.b.pwrdnclmp = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, -+ gpwrdn.d32); -+ } else { -+ /* Enable Power Down Logic */ -+ gpwrdn.b.pmuintsel = 1; -+ gpwrdn.b.pmuactv = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); -+ } -+ -+ /* Power off the core */ -+ if (core_if->power_down == 2) { -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pwrdnswtch = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, -+ gpwrdn.d32, 0); -+ } -+ -+ /* Unmask SRP detected interrupt from Power Down Logic */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.srp_det_msk = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); -+ -+ dwc_otg_adp_probe_start(core_if); -+ dwc_otg_dump_global_registers(core_if); -+ dwc_otg_dump_host_registers(core_if); -+ } -+ -+} -+ -+/** -+ * Start the ADP Initial Probe timer to detect if Port Connected interrupt is -+ * not asserted within 1.1 seconds. -+ * -+ * @param core_if the pointer to core_if strucure. -+ */ -+void dwc_otg_adp_vbuson_timer_start(dwc_otg_core_if_t * core_if) -+{ -+ core_if->adp.vbuson_timer_started = 1; -+ if (core_if->adp.vbuson_timer) -+ { -+ DWC_PRINTF("SCHEDULING VBUSON TIMER\n"); -+ /* 1.1 secs + 60ms necessary for cil_hcd_start*/ -+ DWC_TIMER_SCHEDULE(core_if->adp.vbuson_timer, 1160); -+ } else { -+ DWC_WARN("VBUSON_TIMER = %p\n",core_if->adp.vbuson_timer); -+ } -+} -+ -+#if 0 -+/** -+ * Masks all DWC OTG core interrupts -+ * -+ */ -+static void mask_all_interrupts(dwc_otg_core_if_t * core_if) -+{ -+ int i; -+ gahbcfg_data_t ahbcfg = {.d32 = 0 }; -+ -+ /* Mask Host Interrupts */ -+ -+ /* Clear and disable HCINTs */ -+ for (i = 0; i < core_if->core_params->host_channels; i++) { -+ DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk, 0); -+ DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcint, 0xFFFFFFFF); -+ -+ } -+ -+ /* Clear and disable HAINT */ -+ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk, 0x0000); -+ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haint, 0xFFFFFFFF); -+ -+ /* Mask Device Interrupts */ -+ if (!core_if->multiproc_int_enable) { -+ /* Clear and disable IN Endpoint interrupts */ -+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, 0); -+ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) { -+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]-> -+ diepint, 0xFFFFFFFF); -+ } -+ -+ /* Clear and disable OUT Endpoint interrupts */ -+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, 0); -+ for (i = 0; i <= core_if->dev_if->num_out_eps; i++) { -+ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]-> -+ doepint, 0xFFFFFFFF); -+ } -+ -+ /* Clear and disable DAINT */ -+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daint, -+ 0xFFFFFFFF); -+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, 0); -+ } else { -+ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) { -+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs-> -+ diepeachintmsk[i], 0); -+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]-> -+ diepint, 0xFFFFFFFF); -+ } -+ -+ for (i = 0; i < core_if->dev_if->num_out_eps; ++i) { -+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs-> -+ doepeachintmsk[i], 0); -+ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]-> -+ doepint, 0xFFFFFFFF); -+ } -+ -+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachintmsk, -+ 0); -+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachint, -+ 0xFFFFFFFF); -+ -+ } -+ -+ /* Disable interrupts */ -+ ahbcfg.b.glblintrmsk = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0); -+ -+ /* Disable all interrupts. */ -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0); -+ -+ /* Clear any pending interrupts */ -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); -+ -+ /* Clear any pending OTG Interrupts */ -+ DWC_WRITE_REG32(&core_if->core_global_regs->gotgint, 0xFFFFFFFF); -+} -+ -+/** -+ * Unmask Port Connection Detected interrupt -+ * -+ */ -+static void unmask_conn_det_intr(dwc_otg_core_if_t * core_if) -+{ -+ gintmsk_data_t gintmsk = {.d32 = 0,.b.portintr = 1 }; -+ -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32); -+} -+#endif -+ -+/** -+ * Starts the ADP Probing -+ * -+ * @param core_if the pointer to core_if structure. -+ */ -+uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if) -+{ -+ -+ adpctl_data_t adpctl = {.d32 = 0}; -+ gpwrdn_data_t gpwrdn; -+#if 0 -+ adpctl_data_t adpctl_int = {.d32 = 0, .b.adp_prb_int = 1, -+ .b.adp_sns_int = 1, b.adp_tmout_int}; -+#endif -+ dwc_otg_disable_global_interrupts(core_if); -+ DWC_PRINTF("ADP Probe Start\n"); -+ core_if->adp.probe_enabled = 1; -+ -+ adpctl.b.adpres = 1; -+ dwc_otg_adp_write_reg(core_if, adpctl.d32); -+ -+ while (adpctl.b.adpres) { -+ adpctl.d32 = dwc_otg_adp_read_reg(core_if); -+ } -+ -+ adpctl.d32 = 0; -+ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); -+ -+ /* In Host mode unmask SRP detected interrupt */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.sts_chngint_msk = 1; -+ if (!gpwrdn.b.idsts) { -+ gpwrdn.b.srp_det_msk = 1; -+ } -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); -+ -+ adpctl.b.adp_tmout_int_msk = 1; -+ adpctl.b.adp_prb_int_msk = 1; -+ adpctl.b.prb_dschg = 1; -+ adpctl.b.prb_delta = 1; -+ adpctl.b.prb_per = 1; -+ adpctl.b.adpen = 1; -+ adpctl.b.enaprb = 1; -+ -+ dwc_otg_adp_write_reg(core_if, adpctl.d32); -+ DWC_PRINTF("ADP Probe Finish\n"); -+ return 0; -+} -+ -+/** -+ * Starts the ADP Sense timer to detect if ADP Sense interrupt is not asserted -+ * within 3 seconds. -+ * -+ * @param core_if the pointer to core_if strucure. -+ */ -+void dwc_otg_adp_sense_timer_start(dwc_otg_core_if_t * core_if) -+{ -+ core_if->adp.sense_timer_started = 1; -+ DWC_TIMER_SCHEDULE(core_if->adp.sense_timer, 3000 /* 3 secs */ ); -+} -+ -+/** -+ * Starts the ADP Sense -+ * -+ * @param core_if the pointer to core_if strucure. -+ */ -+uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if) -+{ -+ adpctl_data_t adpctl; -+ -+ DWC_PRINTF("ADP Sense Start\n"); -+ -+ /* Unmask ADP sense interrupt and mask all other from the core */ -+ adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if); -+ adpctl.b.adp_sns_int_msk = 1; -+ dwc_otg_adp_write_reg(core_if, adpctl.d32); -+ dwc_otg_disable_global_interrupts(core_if); // vahrama -+ -+ /* Set ADP reset bit*/ -+ adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if); -+ adpctl.b.adpres = 1; -+ dwc_otg_adp_write_reg(core_if, adpctl.d32); -+ -+ while (adpctl.b.adpres) { -+ adpctl.d32 = dwc_otg_adp_read_reg(core_if); -+ } -+ -+ adpctl.b.adpres = 0; -+ adpctl.b.adpen = 1; -+ adpctl.b.enasns = 1; -+ dwc_otg_adp_write_reg(core_if, adpctl.d32); -+ -+ dwc_otg_adp_sense_timer_start(core_if); -+ -+ return 0; -+} -+ -+/** -+ * Stops the ADP Probing -+ * -+ * @param core_if the pointer to core_if strucure. -+ */ -+uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if) -+{ -+ -+ adpctl_data_t adpctl; -+ DWC_PRINTF("Stop ADP probe\n"); -+ core_if->adp.probe_enabled = 0; -+ core_if->adp.probe_counter = 0; -+ adpctl.d32 = dwc_otg_adp_read_reg(core_if); -+ -+ adpctl.b.adpen = 0; -+ adpctl.b.adp_prb_int = 1; -+ adpctl.b.adp_tmout_int = 1; -+ adpctl.b.adp_sns_int = 1; -+ dwc_otg_adp_write_reg(core_if, adpctl.d32); -+ -+ return 0; -+} -+ -+/** -+ * Stops the ADP Sensing -+ * -+ * @param core_if the pointer to core_if strucure. -+ */ -+uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if) -+{ -+ adpctl_data_t adpctl; -+ -+ core_if->adp.sense_enabled = 0; -+ -+ adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if); -+ adpctl.b.enasns = 0; -+ adpctl.b.adp_sns_int = 1; -+ dwc_otg_adp_write_reg(core_if, adpctl.d32); -+ -+ return 0; -+} -+ -+/** -+ * Called to turn on the VBUS after initial ADP probe in host mode. -+ * If port power was already enabled in cil_hcd_start function then -+ * only schedule a timer. -+ * -+ * @param core_if the pointer to core_if structure. -+ */ -+void dwc_otg_adp_turnon_vbus(dwc_otg_core_if_t * core_if) -+{ -+ hprt0_data_t hprt0 = {.d32 = 0 }; -+ hprt0.d32 = dwc_otg_read_hprt0(core_if); -+ DWC_PRINTF("Turn on VBUS for 1.1s, port power is %d\n", hprt0.b.prtpwr); -+ -+ if (hprt0.b.prtpwr == 0) { -+ hprt0.b.prtpwr = 1; -+ //DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); -+ } -+ -+ dwc_otg_adp_vbuson_timer_start(core_if); -+} -+ -+/** -+ * Called right after driver is loaded -+ * to perform initial actions for ADP -+ * -+ * @param core_if the pointer to core_if structure. -+ * @param is_host - flag for current mode of operation either from GINTSTS or GPWRDN -+ */ -+void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host) -+{ -+ gpwrdn_data_t gpwrdn; -+ -+ DWC_PRINTF("ADP Initial Start\n"); -+ core_if->adp.adp_started = 1; -+ -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); -+ dwc_otg_disable_global_interrupts(core_if); -+ if (is_host) { -+ DWC_PRINTF("HOST MODE\n"); -+ /* Enable Power Down Logic Interrupt*/ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pmuintsel = 1; -+ gpwrdn.b.pmuactv = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); -+ /* Initialize first ADP probe to obtain Ramp Time value */ -+ core_if->adp.initial_probe = 1; -+ dwc_otg_adp_probe_start(core_if); -+ } else { -+ gotgctl_data_t gotgctl; -+ gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl); -+ DWC_PRINTF("DEVICE MODE\n"); -+ if (gotgctl.b.bsesvld == 0) { -+ /* Enable Power Down Logic Interrupt*/ -+ gpwrdn.d32 = 0; -+ DWC_PRINTF("VBUS is not valid - start ADP probe\n"); -+ gpwrdn.b.pmuintsel = 1; -+ gpwrdn.b.pmuactv = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); -+ core_if->adp.initial_probe = 1; -+ dwc_otg_adp_probe_start(core_if); -+ } else { -+ DWC_PRINTF("VBUS is valid - initialize core as a Device\n"); -+ core_if->op_state = B_PERIPHERAL; -+ dwc_otg_core_init(core_if); -+ dwc_otg_enable_global_interrupts(core_if); -+ cil_pcd_start(core_if); -+ dwc_otg_dump_global_registers(core_if); -+ dwc_otg_dump_dev_registers(core_if); -+ } -+ } -+} -+ -+void dwc_otg_adp_init(dwc_otg_core_if_t * core_if) -+{ -+ core_if->adp.adp_started = 0; -+ core_if->adp.initial_probe = 0; -+ core_if->adp.probe_timer_values[0] = -1; -+ core_if->adp.probe_timer_values[1] = -1; -+ core_if->adp.probe_enabled = 0; -+ core_if->adp.sense_enabled = 0; -+ core_if->adp.sense_timer_started = 0; -+ core_if->adp.vbuson_timer_started = 0; -+ core_if->adp.probe_counter = 0; -+ core_if->adp.gpwrdn = 0; -+ core_if->adp.attached = DWC_OTG_ADP_UNKOWN; -+ /* Initialize timers */ -+ core_if->adp.sense_timer = -+ DWC_TIMER_ALLOC("ADP SENSE TIMER", adp_sense_timeout, core_if); -+ core_if->adp.vbuson_timer = -+ DWC_TIMER_ALLOC("ADP VBUS ON TIMER", adp_vbuson_timeout, core_if); -+ if (!core_if->adp.sense_timer || !core_if->adp.vbuson_timer) -+ { -+ DWC_ERROR("Could not allocate memory for ADP timers\n"); -+ } -+} -+ -+void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if) -+{ -+ gpwrdn_data_t gpwrdn = { .d32 = 0 }; -+ gpwrdn.b.pmuintsel = 1; -+ gpwrdn.b.pmuactv = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ -+ if (core_if->adp.probe_enabled) -+ dwc_otg_adp_probe_stop(core_if); -+ if (core_if->adp.sense_enabled) -+ dwc_otg_adp_sense_stop(core_if); -+ if (core_if->adp.sense_timer_started) -+ DWC_TIMER_CANCEL(core_if->adp.sense_timer); -+ if (core_if->adp.vbuson_timer_started) -+ DWC_TIMER_CANCEL(core_if->adp.vbuson_timer); -+ DWC_TIMER_FREE(core_if->adp.sense_timer); -+ DWC_TIMER_FREE(core_if->adp.vbuson_timer); -+} -+ -+///////////////////////////////////////////////////////////////////// -+////////////// ADP Interrupt Handlers /////////////////////////////// -+///////////////////////////////////////////////////////////////////// -+/** -+ * This function sets Ramp Timer values -+ */ -+static uint32_t set_timer_value(dwc_otg_core_if_t * core_if, uint32_t val) -+{ -+ if (core_if->adp.probe_timer_values[0] == -1) { -+ core_if->adp.probe_timer_values[0] = val; -+ core_if->adp.probe_timer_values[1] = -1; -+ return 1; -+ } else { -+ core_if->adp.probe_timer_values[1] = -+ core_if->adp.probe_timer_values[0]; -+ core_if->adp.probe_timer_values[0] = val; -+ return 0; -+ } -+} -+ -+/** -+ * This function compares Ramp Timer values -+ */ -+static uint32_t compare_timer_values(dwc_otg_core_if_t * core_if) -+{ -+ uint32_t diff; -+ if (core_if->adp.probe_timer_values[0]>=core_if->adp.probe_timer_values[1]) -+ diff = core_if->adp.probe_timer_values[0]-core_if->adp.probe_timer_values[1]; -+ else -+ diff = core_if->adp.probe_timer_values[1]-core_if->adp.probe_timer_values[0]; -+ if(diff < 2) { -+ return 0; -+ } else { -+ return 1; -+ } -+} -+ -+/** -+ * This function handles ADP Probe Interrupts -+ */ -+static int32_t dwc_otg_adp_handle_prb_intr(dwc_otg_core_if_t * core_if, -+ uint32_t val) -+{ -+ adpctl_data_t adpctl = {.d32 = 0 }; -+ gpwrdn_data_t gpwrdn, temp; -+ adpctl.d32 = val; -+ -+ temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); -+ core_if->adp.probe_counter++; -+ core_if->adp.gpwrdn = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); -+ if (adpctl.b.rtim == 0 && !temp.b.idsts){ -+ DWC_PRINTF("RTIM value is 0\n"); -+ goto exit; -+ } -+ if (set_timer_value(core_if, adpctl.b.rtim) && -+ core_if->adp.initial_probe) { -+ core_if->adp.initial_probe = 0; -+ dwc_otg_adp_probe_stop(core_if); -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pmuactv = 1; -+ gpwrdn.b.pmuintsel = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); -+ -+ /* check which value is for device mode and which for Host mode */ -+ if (!temp.b.idsts) { /* considered host mode value is 0 */ -+ /* -+ * Turn on VBUS after initial ADP probe. -+ */ -+ core_if->op_state = A_HOST; -+ dwc_otg_enable_global_interrupts(core_if); -+ DWC_SPINUNLOCK(core_if->lock); -+ cil_hcd_start(core_if); -+ dwc_otg_adp_turnon_vbus(core_if); -+ DWC_SPINLOCK(core_if->lock); -+ } else { -+ /* -+ * Initiate SRP after initial ADP probe. -+ */ -+ dwc_otg_enable_global_interrupts(core_if); -+ dwc_otg_initiate_srp(core_if); -+ } -+ } else if (core_if->adp.probe_counter > 2){ -+ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); -+ if (compare_timer_values(core_if)) { -+ DWC_PRINTF("Difference in timer values !!! \n"); -+// core_if->adp.attached = DWC_OTG_ADP_ATTACHED; -+ dwc_otg_adp_probe_stop(core_if); -+ -+ /* Power on the core */ -+ if (core_if->power_down == 2) { -+ gpwrdn.b.pwrdnswtch = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs-> -+ gpwrdn, 0, gpwrdn.d32); -+ } -+ -+ /* check which value is for device mode and which for Host mode */ -+ if (!temp.b.idsts) { /* considered host mode value is 0 */ -+ /* Disable Interrupt from Power Down Logic */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pmuintsel = 1; -+ gpwrdn.b.pmuactv = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs-> -+ gpwrdn, gpwrdn.d32, 0); -+ -+ /* -+ * Initialize the Core for Host mode. -+ */ -+ core_if->op_state = A_HOST; -+ dwc_otg_core_init(core_if); -+ dwc_otg_enable_global_interrupts(core_if); -+ cil_hcd_start(core_if); -+ } else { -+ gotgctl_data_t gotgctl; -+ /* Mask SRP detected interrupt from Power Down Logic */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.srp_det_msk = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs-> -+ gpwrdn, gpwrdn.d32, 0); -+ -+ /* Disable Power Down Logic */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pmuintsel = 1; -+ gpwrdn.b.pmuactv = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs-> -+ gpwrdn, gpwrdn.d32, 0); -+ -+ /* -+ * Initialize the Core for Device mode. -+ */ -+ core_if->op_state = B_PERIPHERAL; -+ dwc_otg_core_init(core_if); -+ dwc_otg_enable_global_interrupts(core_if); -+ cil_pcd_start(core_if); -+ -+ gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl); -+ if (!gotgctl.b.bsesvld) { -+ dwc_otg_initiate_srp(core_if); -+ } -+ } -+ } -+ if (core_if->power_down == 2) { -+ if (gpwrdn.b.bsessvld) { -+ /* Mask SRP detected interrupt from Power Down Logic */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.srp_det_msk = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ -+ /* Disable Power Down Logic */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pmuactv = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ -+ /* -+ * Initialize the Core for Device mode. -+ */ -+ core_if->op_state = B_PERIPHERAL; -+ dwc_otg_core_init(core_if); -+ dwc_otg_enable_global_interrupts(core_if); -+ cil_pcd_start(core_if); -+ } -+ } -+ } -+exit: -+ /* Clear interrupt */ -+ adpctl.d32 = dwc_otg_adp_read_reg(core_if); -+ adpctl.b.adp_prb_int = 1; -+ dwc_otg_adp_write_reg(core_if, adpctl.d32); -+ -+ return 0; -+} -+ -+/** -+ * This function hadles ADP Sense Interrupt -+ */ -+static int32_t dwc_otg_adp_handle_sns_intr(dwc_otg_core_if_t * core_if) -+{ -+ adpctl_data_t adpctl; -+ /* Stop ADP Sense timer */ -+ DWC_TIMER_CANCEL(core_if->adp.sense_timer); -+ -+ /* Restart ADP Sense timer */ -+ dwc_otg_adp_sense_timer_start(core_if); -+ -+ /* Clear interrupt */ -+ adpctl.d32 = dwc_otg_adp_read_reg(core_if); -+ adpctl.b.adp_sns_int = 1; -+ dwc_otg_adp_write_reg(core_if, adpctl.d32); -+ -+ return 0; -+} -+ -+/** -+ * This function handles ADP Probe Interrupts -+ */ -+static int32_t dwc_otg_adp_handle_prb_tmout_intr(dwc_otg_core_if_t * core_if, -+ uint32_t val) -+{ -+ adpctl_data_t adpctl = {.d32 = 0 }; -+ adpctl.d32 = val; -+ set_timer_value(core_if, adpctl.b.rtim); -+ -+ /* Clear interrupt */ -+ adpctl.d32 = dwc_otg_adp_read_reg(core_if); -+ adpctl.b.adp_tmout_int = 1; -+ dwc_otg_adp_write_reg(core_if, adpctl.d32); -+ -+ return 0; -+} -+ -+/** -+ * ADP Interrupt handler. -+ * -+ */ -+int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if) -+{ -+ int retval = 0; -+ adpctl_data_t adpctl = {.d32 = 0}; -+ -+ adpctl.d32 = dwc_otg_adp_read_reg(core_if); -+ DWC_PRINTF("ADPCTL = %08x\n",adpctl.d32); -+ -+ if (adpctl.b.adp_sns_int & adpctl.b.adp_sns_int_msk) { -+ DWC_PRINTF("ADP Sense interrupt\n"); -+ retval |= dwc_otg_adp_handle_sns_intr(core_if); -+ } -+ if (adpctl.b.adp_tmout_int & adpctl.b.adp_tmout_int_msk) { -+ DWC_PRINTF("ADP timeout interrupt\n"); -+ retval |= dwc_otg_adp_handle_prb_tmout_intr(core_if, adpctl.d32); -+ } -+ if (adpctl.b.adp_prb_int & adpctl.b.adp_prb_int_msk) { -+ DWC_PRINTF("ADP Probe interrupt\n"); -+ adpctl.b.adp_prb_int = 1; -+ retval |= dwc_otg_adp_handle_prb_intr(core_if, adpctl.d32); -+ } -+ -+// dwc_otg_adp_modify_reg(core_if, adpctl.d32, 0); -+ //dwc_otg_adp_write_reg(core_if, adpctl.d32); -+ DWC_PRINTF("RETURN FROM ADP ISR\n"); -+ -+ return retval; -+} -+ -+/** -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ */ -+int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if) -+{ -+ -+#ifndef DWC_HOST_ONLY -+ hprt0_data_t hprt0; -+ gpwrdn_data_t gpwrdn; -+ DWC_DEBUGPL(DBG_ANY, "++ Power Down Logic Session Request Interrupt++\n"); -+ -+ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); -+ /* check which value is for device mode and which for Host mode */ -+ if (!gpwrdn.b.idsts) { /* considered host mode value is 0 */ -+ DWC_PRINTF("SRP: Host mode\n"); -+ -+ if (core_if->adp_enable) { -+ dwc_otg_adp_probe_stop(core_if); -+ -+ /* Power on the core */ -+ if (core_if->power_down == 2) { -+ gpwrdn.b.pwrdnswtch = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs-> -+ gpwrdn, 0, gpwrdn.d32); -+ } -+ -+ core_if->op_state = A_HOST; -+ dwc_otg_core_init(core_if); -+ dwc_otg_enable_global_interrupts(core_if); -+ cil_hcd_start(core_if); -+ } -+ -+ /* Turn on the port power bit. */ -+ hprt0.d32 = dwc_otg_read_hprt0(core_if); -+ hprt0.b.prtpwr = 1; -+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); -+ -+ /* Start the Connection timer. So a message can be displayed -+ * if connect does not occur within 10 seconds. */ -+ cil_hcd_session_start(core_if); -+ } else { -+ DWC_PRINTF("SRP: Device mode %s\n", __FUNCTION__); -+ if (core_if->adp_enable) { -+ dwc_otg_adp_probe_stop(core_if); -+ -+ /* Power on the core */ -+ if (core_if->power_down == 2) { -+ gpwrdn.b.pwrdnswtch = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs-> -+ gpwrdn, 0, gpwrdn.d32); -+ } -+ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pmuactv = 0; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, -+ gpwrdn.d32); -+ -+ core_if->op_state = B_PERIPHERAL; -+ dwc_otg_core_init(core_if); -+ dwc_otg_enable_global_interrupts(core_if); -+ cil_pcd_start(core_if); -+ } -+ } -+#endif -+ return 1; -+} -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_adp.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_adp.h ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_adp.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_adp.h 2015-11-29 09:42:39.915098960 +0100 -@@ -0,0 +1,80 @@ -+/* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.h $ -+ * $Revision: #7 $ -+ * $Date: 2011/10/24 $ -+ * $Change: 1871159 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+ -+#ifndef __DWC_OTG_ADP_H__ -+#define __DWC_OTG_ADP_H__ -+ -+/** -+ * @file -+ * -+ * This file contains the Attach Detect Protocol interfaces and defines -+ * (functions) and structures for Linux. -+ * -+ */ -+ -+#define DWC_OTG_ADP_UNATTACHED 0 -+#define DWC_OTG_ADP_ATTACHED 1 -+#define DWC_OTG_ADP_UNKOWN 2 -+ -+typedef struct dwc_otg_adp { -+ uint32_t adp_started; -+ uint32_t initial_probe; -+ int32_t probe_timer_values[2]; -+ uint32_t probe_enabled; -+ uint32_t sense_enabled; -+ dwc_timer_t *sense_timer; -+ uint32_t sense_timer_started; -+ dwc_timer_t *vbuson_timer; -+ uint32_t vbuson_timer_started; -+ uint32_t attached; -+ uint32_t probe_counter; -+ uint32_t gpwrdn; -+} dwc_otg_adp_t; -+ -+/** -+ * Attach Detect Protocol functions -+ */ -+ -+extern void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value); -+extern uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if); -+extern uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if); -+extern uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if); -+extern uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if); -+extern uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if); -+extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host); -+extern void dwc_otg_adp_init(dwc_otg_core_if_t * core_if); -+extern void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if); -+extern int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if); -+extern int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if); -+ -+#endif //__DWC_OTG_ADP_H__ -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_attr.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_attr.c ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_attr.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_attr.c 2015-11-29 09:42:39.915098960 +0100 -@@ -0,0 +1,1210 @@ -+/* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.c $ -+ * $Revision: #44 $ -+ * $Date: 2010/11/29 $ -+ * $Change: 1636033 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+ -+/** @file -+ * -+ * The diagnostic interface will provide access to the controller for -+ * bringing up the hardware and testing. The Linux driver attributes -+ * feature will be used to provide the Linux Diagnostic -+ * Interface. These attributes are accessed through sysfs. -+ */ -+ -+/** @page "Linux Module Attributes" -+ * -+ * The Linux module attributes feature is used to provide the Linux -+ * Diagnostic Interface. These attributes are accessed through sysfs. -+ * The diagnostic interface will provide access to the controller for -+ * bringing up the hardware and testing. -+ -+ The following table shows the attributes. -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+
Name Description Access
mode Returns the current mode: 0 for device mode, 1 for host mode Read
hnpcapable Gets or sets the "HNP-capable" bit in the Core USB Configuraton Register. -+ Read returns the current value. Read/Write
srpcapable Gets or sets the "SRP-capable" bit in the Core USB Configuraton Register. -+ Read returns the current value. Read/Write
hsic_connect Gets or sets the "HSIC-Connect" bit in the GLPMCFG Register. -+ Read returns the current value. Read/Write
inv_sel_hsic Gets or sets the "Invert Select HSIC" bit in the GLPMFG Register. -+ Read returns the current value. Read/Write
hnp Initiates the Host Negotiation Protocol. Read returns the status. Read/Write
srp Initiates the Session Request Protocol. Read returns the status. Read/Write
buspower Gets or sets the Power State of the bus (0 - Off or 1 - On) Read/Write
bussuspend Suspends the USB bus. Read/Write
busconnected Gets the connection status of the bus Read
gotgctl Gets or sets the Core Control Status Register. Read/Write
gusbcfg Gets or sets the Core USB Configuration Register Read/Write
grxfsiz Gets or sets the Receive FIFO Size Register Read/Write
gnptxfsiz Gets or sets the non-periodic Transmit Size Register Read/Write
gpvndctl Gets or sets the PHY Vendor Control Register Read/Write
ggpio Gets the value in the lower 16-bits of the General Purpose IO Register -+ or sets the upper 16 bits. Read/Write
guid Gets or sets the value of the User ID Register Read/Write
gsnpsid Gets the value of the Synopsys ID Regester Read
devspeed Gets or sets the device speed setting in the DCFG register Read/Write
enumspeed Gets the device enumeration Speed. Read
hptxfsiz Gets the value of the Host Periodic Transmit FIFO Read
hprt0 Gets or sets the value in the Host Port Control and Status Register Read/Write
regoffset Sets the register offset for the next Register Access Read/Write
regvalue Gets or sets the value of the register at the offset in the regoffset attribute. Read/Write
remote_wakeup On read, shows the status of Remote Wakeup. On write, initiates a remote -+ wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote -+ Wakeup signalling bit in the Device Control Register is set for 1 -+ milli-second. Read/Write
rem_wakeup_pwrdn On read, shows the status core - hibernated or not. On write, initiates -+ a remote wakeup of the device from Hibernation. Read/Write
mode_ch_tim_en This bit is used to enable or disable the host core to wait for 200 PHY -+ clock cycles at the end of Resume to change the opmode signal to the PHY to 00 -+ after Suspend or LPM. Read/Write
fr_interval On read, shows the value of HFIR Frame Interval. On write, dynamically -+ reload HFIR register during runtime. The application can write a value to this -+ register only after the Port Enable bit of the Host Port Control and Status -+ register (HPRT.PrtEnaPort) has been set Read/Write
disconnect_us On read, shows the status of disconnect_device_us. On write, sets disconnect_us -+ which causes soft disconnect for 100us. Applicable only for device mode of operation. Read/Write
regdump Dumps the contents of core registers. Read
spramdump Dumps the contents of core registers. Read
hcddump Dumps the current HCD state. Read
hcd_frrem Shows the average value of the Frame Remaining -+ field in the Host Frame Number/Frame Remaining register when an SOF interrupt -+ occurs. This can be used to determine the average interrupt latency. Also -+ shows the average Frame Remaining value for start_transfer and the "a" and -+ "b" sample points. The "a" and "b" sample points may be used during debugging -+ bto determine how long it takes to execute a section of the HCD code. Read
rd_reg_test Displays the time required to read the GNPTXFSIZ register many times -+ (the output shows the number of times the register is read). -+ Read
wr_reg_test Displays the time required to write the GNPTXFSIZ register many times -+ (the output shows the number of times the register is written). -+ Read
lpm_response Gets or sets lpm_response mode. Applicable only in device mode. -+ Write
sleep_status Shows sleep status of device. -+ Read
-+ -+ Example usage: -+ To get the current mode: -+ cat /sys/devices/lm0/mode -+ -+ To power down the USB: -+ echo 0 > /sys/devices/lm0/buspower -+ */ -+ -+#include "dwc_otg_os_dep.h" -+#include "dwc_os.h" -+#include "dwc_otg_driver.h" -+#include "dwc_otg_attr.h" -+#include "dwc_otg_core_if.h" -+#include "dwc_otg_pcd_if.h" -+#include "dwc_otg_hcd_if.h" -+ -+/* -+ * MACROs for defining sysfs attribute -+ */ -+#ifdef LM_INTERFACE -+ -+#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \ -+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \ -+{ \ -+ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \ -+ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \ -+ uint32_t val; \ -+ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \ -+ return sprintf (buf, "%s = 0x%x\n", _string_, val); \ -+} -+#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \ -+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \ -+ const char *buf, size_t count) \ -+{ \ -+ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \ -+ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \ -+ uint32_t set = simple_strtoul(buf, NULL, 16); \ -+ dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\ -+ return count; \ -+} -+ -+#elif defined(PCI_INTERFACE) -+ -+#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \ -+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \ -+{ \ -+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \ -+ uint32_t val; \ -+ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \ -+ return sprintf (buf, "%s = 0x%x\n", _string_, val); \ -+} -+#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \ -+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \ -+ const char *buf, size_t count) \ -+{ \ -+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \ -+ uint32_t set = simple_strtoul(buf, NULL, 16); \ -+ dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\ -+ return count; \ -+} -+ -+#elif defined(PLATFORM_INTERFACE) -+ -+#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \ -+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \ -+{ \ -+ struct platform_device *platform_dev = \ -+ container_of(_dev, struct platform_device, dev); \ -+ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \ -+ uint32_t val; \ -+ DWC_PRINTF("%s(%p) -> platform_dev %p, otg_dev %p\n", \ -+ __func__, _dev, platform_dev, otg_dev); \ -+ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \ -+ return sprintf (buf, "%s = 0x%x\n", _string_, val); \ -+} -+#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \ -+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \ -+ const char *buf, size_t count) \ -+{ \ -+ struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \ -+ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \ -+ uint32_t set = simple_strtoul(buf, NULL, 16); \ -+ dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\ -+ return count; \ -+} -+#endif -+ -+/* -+ * MACROs for defining sysfs attribute for 32-bit registers -+ */ -+#ifdef LM_INTERFACE -+#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \ -+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \ -+{ \ -+ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \ -+ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \ -+ uint32_t val; \ -+ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \ -+ return sprintf (buf, "%s = 0x%08x\n", _string_, val); \ -+} -+#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \ -+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \ -+ const char *buf, size_t count) \ -+{ \ -+ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \ -+ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \ -+ uint32_t val = simple_strtoul(buf, NULL, 16); \ -+ dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \ -+ return count; \ -+} -+#elif defined(PCI_INTERFACE) -+#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \ -+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \ -+{ \ -+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \ -+ uint32_t val; \ -+ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \ -+ return sprintf (buf, "%s = 0x%08x\n", _string_, val); \ -+} -+#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \ -+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \ -+ const char *buf, size_t count) \ -+{ \ -+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \ -+ uint32_t val = simple_strtoul(buf, NULL, 16); \ -+ dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \ -+ return count; \ -+} -+ -+#elif defined(PLATFORM_INTERFACE) -+#include "dwc_otg_dbg.h" -+#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \ -+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \ -+{ \ -+ struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \ -+ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \ -+ uint32_t val; \ -+ DWC_PRINTF("%s(%p) -> platform_dev %p, otg_dev %p\n", \ -+ __func__, _dev, platform_dev, otg_dev); \ -+ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \ -+ return sprintf (buf, "%s = 0x%08x\n", _string_, val); \ -+} -+#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \ -+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \ -+ const char *buf, size_t count) \ -+{ \ -+ struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \ -+ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \ -+ uint32_t val = simple_strtoul(buf, NULL, 16); \ -+ dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \ -+ return count; \ -+} -+ -+#endif -+ -+#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_string_) \ -+DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \ -+DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \ -+DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store); -+ -+#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_string_) \ -+DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \ -+DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL); -+ -+#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \ -+DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \ -+DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \ -+DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store); -+ -+#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \ -+DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \ -+DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL); -+ -+/** @name Functions for Show/Store of Attributes */ -+/**@{*/ -+ -+/** -+ * Helper function returning the otg_device structure of the given device -+ */ -+static dwc_otg_device_t *dwc_otg_drvdev(struct device *_dev) -+{ -+ dwc_otg_device_t *otg_dev; -+ DWC_OTG_GETDRVDEV(otg_dev, _dev); -+ return otg_dev; -+} -+ -+/** -+ * Show the register offset of the Register Access. -+ */ -+static ssize_t regoffset_show(struct device *_dev, -+ struct device_attribute *attr, char *buf) -+{ -+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); -+ return snprintf(buf, sizeof("0xFFFFFFFF\n") + 1, "0x%08x\n", -+ otg_dev->os_dep.reg_offset); -+} -+ -+/** -+ * Set the register offset for the next Register Access Read/Write -+ */ -+static ssize_t regoffset_store(struct device *_dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); -+ uint32_t offset = simple_strtoul(buf, NULL, 16); -+#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE) -+ if (offset < SZ_256K) { -+#elif defined(PCI_INTERFACE) -+ if (offset < 0x00040000) { -+#endif -+ otg_dev->os_dep.reg_offset = offset; -+ } else { -+ dev_err(_dev, "invalid offset\n"); -+ } -+ -+ return count; -+} -+ -+DEVICE_ATTR(regoffset, S_IRUGO | S_IWUSR, regoffset_show, regoffset_store); -+ -+/** -+ * Show the value of the register at the offset in the reg_offset -+ * attribute. -+ */ -+static ssize_t regvalue_show(struct device *_dev, -+ struct device_attribute *attr, char *buf) -+{ -+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); -+ uint32_t val; -+ volatile uint32_t *addr; -+ -+ if (otg_dev->os_dep.reg_offset != 0xFFFFFFFF && 0 != otg_dev->os_dep.base) { -+ /* Calculate the address */ -+ addr = (uint32_t *) (otg_dev->os_dep.reg_offset + -+ (uint8_t *) otg_dev->os_dep.base); -+ val = DWC_READ_REG32(addr); -+ return snprintf(buf, -+ sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n") + 1, -+ "Reg@0x%06x = 0x%08x\n", otg_dev->os_dep.reg_offset, -+ val); -+ } else { -+ dev_err(_dev, "Invalid offset (0x%0x)\n", otg_dev->os_dep.reg_offset); -+ return sprintf(buf, "invalid offset\n"); -+ } -+} -+ -+/** -+ * Store the value in the register at the offset in the reg_offset -+ * attribute. -+ * -+ */ -+static ssize_t regvalue_store(struct device *_dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); -+ volatile uint32_t *addr; -+ uint32_t val = simple_strtoul(buf, NULL, 16); -+ //dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val); -+ if (otg_dev->os_dep.reg_offset != 0xFFFFFFFF && 0 != otg_dev->os_dep.base) { -+ /* Calculate the address */ -+ addr = (uint32_t *) (otg_dev->os_dep.reg_offset + -+ (uint8_t *) otg_dev->os_dep.base); -+ DWC_WRITE_REG32(addr, val); -+ } else { -+ dev_err(_dev, "Invalid Register Offset (0x%08x)\n", -+ otg_dev->os_dep.reg_offset); -+ } -+ return count; -+} -+ -+DEVICE_ATTR(regvalue, S_IRUGO | S_IWUSR, regvalue_show, regvalue_store); -+ -+/* -+ * Attributes -+ */ -+DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode, "Mode"); -+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable, "HNPCapable"); -+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable, "SRPCapable"); -+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hsic_connect, "HSIC Connect"); -+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(inv_sel_hsic, "Invert Select HSIC"); -+ -+//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode"); -+//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode"); -+DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected, "Bus Connected"); -+ -+DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl, 0, "GOTGCTL"); -+DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg, -+ &(otg_dev->core_if->core_global_regs->gusbcfg), -+ "GUSBCFG"); -+DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz, -+ &(otg_dev->core_if->core_global_regs->grxfsiz), -+ "GRXFSIZ"); -+DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz, -+ &(otg_dev->core_if->core_global_regs->gnptxfsiz), -+ "GNPTXFSIZ"); -+DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl, -+ &(otg_dev->core_if->core_global_regs->gpvndctl), -+ "GPVNDCTL"); -+DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio, -+ &(otg_dev->core_if->core_global_regs->ggpio), -+ "GGPIO"); -+DWC_OTG_DEVICE_ATTR_REG32_RW(guid, &(otg_dev->core_if->core_global_regs->guid), -+ "GUID"); -+DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid, -+ &(otg_dev->core_if->core_global_regs->gsnpsid), -+ "GSNPSID"); -+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed, "Device Speed"); -+DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed, "Device Enumeration Speed"); -+ -+DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz, -+ &(otg_dev->core_if->core_global_regs->hptxfsiz), -+ "HPTXFSIZ"); -+DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0, otg_dev->core_if->host_if->hprt0, "HPRT0"); -+ -+/** -+ * @todo Add code to initiate the HNP. -+ */ -+/** -+ * Show the HNP status bit -+ */ -+static ssize_t hnp_show(struct device *_dev, -+ struct device_attribute *attr, char *buf) -+{ -+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); -+ return sprintf(buf, "HstNegScs = 0x%x\n", -+ dwc_otg_get_hnpstatus(otg_dev->core_if)); -+} -+ -+/** -+ * Set the HNP Request bit -+ */ -+static ssize_t hnp_store(struct device *_dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); -+ uint32_t in = simple_strtoul(buf, NULL, 16); -+ dwc_otg_set_hnpreq(otg_dev->core_if, in); -+ return count; -+} -+ -+DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store); -+ -+/** -+ * @todo Add code to initiate the SRP. -+ */ -+/** -+ * Show the SRP status bit -+ */ -+static ssize_t srp_show(struct device *_dev, -+ struct device_attribute *attr, char *buf) -+{ -+#ifndef DWC_HOST_ONLY -+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); -+ return sprintf(buf, "SesReqScs = 0x%x\n", -+ dwc_otg_get_srpstatus(otg_dev->core_if)); -+#else -+ return sprintf(buf, "Host Only Mode!\n"); -+#endif -+} -+ -+/** -+ * Set the SRP Request bit -+ */ -+static ssize_t srp_store(struct device *_dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+#ifndef DWC_HOST_ONLY -+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); -+ dwc_otg_pcd_initiate_srp(otg_dev->pcd); -+#endif -+ return count; -+} -+ -+DEVICE_ATTR(srp, 0644, srp_show, srp_store); -+ -+/** -+ * @todo Need to do more for power on/off? -+ */ -+/** -+ * Show the Bus Power status -+ */ -+static ssize_t buspower_show(struct device *_dev, -+ struct device_attribute *attr, char *buf) -+{ -+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); -+ return sprintf(buf, "Bus Power = 0x%x\n", -+ dwc_otg_get_prtpower(otg_dev->core_if)); -+} -+ -+/** -+ * Set the Bus Power status -+ */ -+static ssize_t buspower_store(struct device *_dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); -+ uint32_t on = simple_strtoul(buf, NULL, 16); -+ dwc_otg_set_prtpower(otg_dev->core_if, on); -+ return count; -+} -+ -+DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store); -+ -+/** -+ * @todo Need to do more for suspend? -+ */ -+/** -+ * Show the Bus Suspend status -+ */ -+static ssize_t bussuspend_show(struct device *_dev, -+ struct device_attribute *attr, char *buf) -+{ -+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); -+ return sprintf(buf, "Bus Suspend = 0x%x\n", -+ dwc_otg_get_prtsuspend(otg_dev->core_if)); -+} -+ -+/** -+ * Set the Bus Suspend status -+ */ -+static ssize_t bussuspend_store(struct device *_dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); -+ uint32_t in = simple_strtoul(buf, NULL, 16); -+ dwc_otg_set_prtsuspend(otg_dev->core_if, in); -+ return count; -+} -+ -+DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store); -+ -+/** -+ * Show the Mode Change Ready Timer status -+ */ -+static ssize_t mode_ch_tim_en_show(struct device *_dev, -+ struct device_attribute *attr, char *buf) -+{ -+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); -+ return sprintf(buf, "Mode Change Ready Timer Enable = 0x%x\n", -+ dwc_otg_get_mode_ch_tim(otg_dev->core_if)); -+} -+ -+/** -+ * Set the Mode Change Ready Timer status -+ */ -+static ssize_t mode_ch_tim_en_store(struct device *_dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); -+ uint32_t in = simple_strtoul(buf, NULL, 16); -+ dwc_otg_set_mode_ch_tim(otg_dev->core_if, in); -+ return count; -+} -+ -+DEVICE_ATTR(mode_ch_tim_en, 0644, mode_ch_tim_en_show, mode_ch_tim_en_store); -+ -+/** -+ * Show the value of HFIR Frame Interval bitfield -+ */ -+static ssize_t fr_interval_show(struct device *_dev, -+ struct device_attribute *attr, char *buf) -+{ -+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); -+ return sprintf(buf, "Frame Interval = 0x%x\n", -+ dwc_otg_get_fr_interval(otg_dev->core_if)); -+} -+ -+/** -+ * Set the HFIR Frame Interval value -+ */ -+static ssize_t fr_interval_store(struct device *_dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); -+ uint32_t in = simple_strtoul(buf, NULL, 10); -+ dwc_otg_set_fr_interval(otg_dev->core_if, in); -+ return count; -+} -+ -+DEVICE_ATTR(fr_interval, 0644, fr_interval_show, fr_interval_store); -+ -+/** -+ * Show the status of Remote Wakeup. -+ */ -+static ssize_t remote_wakeup_show(struct device *_dev, -+ struct device_attribute *attr, char *buf) -+{ -+#ifndef DWC_HOST_ONLY -+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); -+ -+ return sprintf(buf, -+ "Remote Wakeup Sig = %d Enabled = %d LPM Remote Wakeup = %d\n", -+ dwc_otg_get_remotewakesig(otg_dev->core_if), -+ dwc_otg_pcd_get_rmwkup_enable(otg_dev->pcd), -+ dwc_otg_get_lpm_remotewakeenabled(otg_dev->core_if)); -+#else -+ return sprintf(buf, "Host Only Mode!\n"); -+#endif /* DWC_HOST_ONLY */ -+} -+ -+/** -+ * Initiate a remote wakeup of the host. The Device control register -+ * Remote Wakeup Signal bit is written if the PCD Remote wakeup enable -+ * flag is set. -+ * -+ */ -+static ssize_t remote_wakeup_store(struct device *_dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+#ifndef DWC_HOST_ONLY -+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); -+ uint32_t val = simple_strtoul(buf, NULL, 16); -+ -+ if (val & 1) { -+ dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1); -+ } else { -+ dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0); -+ } -+#endif /* DWC_HOST_ONLY */ -+ return count; -+} -+ -+DEVICE_ATTR(remote_wakeup, S_IRUGO | S_IWUSR, remote_wakeup_show, -+ remote_wakeup_store); -+ -+/** -+ * Show the whether core is hibernated or not. -+ */ -+static ssize_t rem_wakeup_pwrdn_show(struct device *_dev, -+ struct device_attribute *attr, char *buf) -+{ -+#ifndef DWC_HOST_ONLY -+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); -+ -+ if (dwc_otg_get_core_state(otg_dev->core_if)) { -+ DWC_PRINTF("Core is in hibernation\n"); -+ } else { -+ DWC_PRINTF("Core is not in hibernation\n"); -+ } -+#endif /* DWC_HOST_ONLY */ -+ return 0; -+} -+ -+extern int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if, -+ int rem_wakeup, int reset); -+ -+/** -+ * Initiate a remote wakeup of the device to exit from hibernation. -+ */ -+static ssize_t rem_wakeup_pwrdn_store(struct device *_dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+#ifndef DWC_HOST_ONLY -+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); -+ dwc_otg_device_hibernation_restore(otg_dev->core_if, 1, 0); -+#endif -+ return count; -+} -+ -+DEVICE_ATTR(rem_wakeup_pwrdn, S_IRUGO | S_IWUSR, rem_wakeup_pwrdn_show, -+ rem_wakeup_pwrdn_store); -+ -+static ssize_t disconnect_us(struct device *_dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ -+#ifndef DWC_HOST_ONLY -+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); -+ uint32_t val = simple_strtoul(buf, NULL, 16); -+ DWC_PRINTF("The Passed value is %04x\n", val); -+ -+ dwc_otg_pcd_disconnect_us(otg_dev->pcd, 50); -+ -+#endif /* DWC_HOST_ONLY */ -+ return count; -+} -+ -+DEVICE_ATTR(disconnect_us, S_IWUSR, 0, disconnect_us); -+ -+/** -+ * Dump global registers and either host or device registers (depending on the -+ * current mode of the core). -+ */ -+static ssize_t regdump_show(struct device *_dev, -+ struct device_attribute *attr, char *buf) -+{ -+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); -+ -+ dwc_otg_dump_global_registers(otg_dev->core_if); -+ if (dwc_otg_is_host_mode(otg_dev->core_if)) { -+ dwc_otg_dump_host_registers(otg_dev->core_if); -+ } else { -+ dwc_otg_dump_dev_registers(otg_dev->core_if); -+ -+ } -+ return sprintf(buf, "Register Dump\n"); -+} -+ -+DEVICE_ATTR(regdump, S_IRUGO, regdump_show, 0); -+ -+/** -+ * Dump global registers and either host or device registers (depending on the -+ * current mode of the core). -+ */ -+static ssize_t spramdump_show(struct device *_dev, -+ struct device_attribute *attr, char *buf) -+{ -+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); -+ -+ //dwc_otg_dump_spram(otg_dev->core_if); -+ -+ return sprintf(buf, "SPRAM Dump\n"); -+} -+ -+DEVICE_ATTR(spramdump, S_IRUGO, spramdump_show, 0); -+ -+/** -+ * Dump the current hcd state. -+ */ -+static ssize_t hcddump_show(struct device *_dev, -+ struct device_attribute *attr, char *buf) -+{ -+#ifndef DWC_DEVICE_ONLY -+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); -+ dwc_otg_hcd_dump_state(otg_dev->hcd); -+#endif /* DWC_DEVICE_ONLY */ -+ return sprintf(buf, "HCD Dump\n"); -+} -+ -+DEVICE_ATTR(hcddump, S_IRUGO, hcddump_show, 0); -+ -+/** -+ * Dump the average frame remaining at SOF. This can be used to -+ * determine average interrupt latency. Frame remaining is also shown for -+ * start transfer and two additional sample points. -+ */ -+static ssize_t hcd_frrem_show(struct device *_dev, -+ struct device_attribute *attr, char *buf) -+{ -+#ifndef DWC_DEVICE_ONLY -+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); -+ -+ dwc_otg_hcd_dump_frrem(otg_dev->hcd); -+#endif /* DWC_DEVICE_ONLY */ -+ return sprintf(buf, "HCD Dump Frame Remaining\n"); -+} -+ -+DEVICE_ATTR(hcd_frrem, S_IRUGO, hcd_frrem_show, 0); -+ -+/** -+ * Displays the time required to read the GNPTXFSIZ register many times (the -+ * output shows the number of times the register is read). -+ */ -+#define RW_REG_COUNT 10000000 -+#define MSEC_PER_JIFFIE 1000/HZ -+static ssize_t rd_reg_test_show(struct device *_dev, -+ struct device_attribute *attr, char *buf) -+{ -+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); -+ int i; -+ int time; -+ int start_jiffies; -+ -+ printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n", -+ HZ, MSEC_PER_JIFFIE, loops_per_jiffy); -+ start_jiffies = jiffies; -+ for (i = 0; i < RW_REG_COUNT; i++) { -+ dwc_otg_get_gnptxfsiz(otg_dev->core_if); -+ } -+ time = jiffies - start_jiffies; -+ return sprintf(buf, -+ "Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n", -+ RW_REG_COUNT, time * MSEC_PER_JIFFIE, time); -+} -+ -+DEVICE_ATTR(rd_reg_test, S_IRUGO, rd_reg_test_show, 0); -+ -+/** -+ * Displays the time required to write the GNPTXFSIZ register many times (the -+ * output shows the number of times the register is written). -+ */ -+static ssize_t wr_reg_test_show(struct device *_dev, -+ struct device_attribute *attr, char *buf) -+{ -+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); -+ uint32_t reg_val; -+ int i; -+ int time; -+ int start_jiffies; -+ -+ printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n", -+ HZ, MSEC_PER_JIFFIE, loops_per_jiffy); -+ reg_val = dwc_otg_get_gnptxfsiz(otg_dev->core_if); -+ start_jiffies = jiffies; -+ for (i = 0; i < RW_REG_COUNT; i++) { -+ dwc_otg_set_gnptxfsiz(otg_dev->core_if, reg_val); -+ } -+ time = jiffies - start_jiffies; -+ return sprintf(buf, -+ "Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n", -+ RW_REG_COUNT, time * MSEC_PER_JIFFIE, time); -+} -+ -+DEVICE_ATTR(wr_reg_test, S_IRUGO, wr_reg_test_show, 0); -+ -+#ifdef CONFIG_USB_DWC_OTG_LPM -+ -+/** -+* Show the lpm_response attribute. -+*/ -+static ssize_t lpmresp_show(struct device *_dev, -+ struct device_attribute *attr, char *buf) -+{ -+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); -+ -+ if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if)) -+ return sprintf(buf, "** LPM is DISABLED **\n"); -+ -+ if (!dwc_otg_is_device_mode(otg_dev->core_if)) { -+ return sprintf(buf, "** Current mode is not device mode\n"); -+ } -+ return sprintf(buf, "lpm_response = %d\n", -+ dwc_otg_get_lpmresponse(otg_dev->core_if)); -+} -+ -+/** -+* Store the lpm_response attribute. -+*/ -+static ssize_t lpmresp_store(struct device *_dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); -+ uint32_t val = simple_strtoul(buf, NULL, 16); -+ -+ if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if)) { -+ return 0; -+ } -+ -+ if (!dwc_otg_is_device_mode(otg_dev->core_if)) { -+ return 0; -+ } -+ -+ dwc_otg_set_lpmresponse(otg_dev->core_if, val); -+ return count; -+} -+ -+DEVICE_ATTR(lpm_response, S_IRUGO | S_IWUSR, lpmresp_show, lpmresp_store); -+ -+/** -+* Show the sleep_status attribute. -+*/ -+static ssize_t sleepstatus_show(struct device *_dev, -+ struct device_attribute *attr, char *buf) -+{ -+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); -+ return sprintf(buf, "Sleep Status = %d\n", -+ dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if)); -+} -+ -+/** -+ * Store the sleep_status attribure. -+ */ -+static ssize_t sleepstatus_store(struct device *_dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); -+ dwc_otg_core_if_t *core_if = otg_dev->core_if; -+ -+ if (dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if)) { -+ if (dwc_otg_is_host_mode(core_if)) { -+ -+ DWC_PRINTF("Host initiated resume\n"); -+ dwc_otg_set_prtresume(otg_dev->core_if, 1); -+ } -+ } -+ -+ return count; -+} -+ -+DEVICE_ATTR(sleep_status, S_IRUGO | S_IWUSR, sleepstatus_show, -+ sleepstatus_store); -+ -+#endif /* CONFIG_USB_DWC_OTG_LPM_ENABLE */ -+ -+/**@}*/ -+ -+/** -+ * Create the device files -+ */ -+void dwc_otg_attr_create( -+#ifdef LM_INTERFACE -+ struct lm_device *dev -+#elif defined(PCI_INTERFACE) -+ struct pci_dev *dev -+#elif defined(PLATFORM_INTERFACE) -+ struct platform_device *dev -+#endif -+ ) -+{ -+ int error; -+ -+ error = device_create_file(&dev->dev, &dev_attr_regoffset); -+ error = device_create_file(&dev->dev, &dev_attr_regvalue); -+ error = device_create_file(&dev->dev, &dev_attr_mode); -+ error = device_create_file(&dev->dev, &dev_attr_hnpcapable); -+ error = device_create_file(&dev->dev, &dev_attr_srpcapable); -+ error = device_create_file(&dev->dev, &dev_attr_hsic_connect); -+ error = device_create_file(&dev->dev, &dev_attr_inv_sel_hsic); -+ error = device_create_file(&dev->dev, &dev_attr_hnp); -+ error = device_create_file(&dev->dev, &dev_attr_srp); -+ error = device_create_file(&dev->dev, &dev_attr_buspower); -+ error = device_create_file(&dev->dev, &dev_attr_bussuspend); -+ error = device_create_file(&dev->dev, &dev_attr_mode_ch_tim_en); -+ error = device_create_file(&dev->dev, &dev_attr_fr_interval); -+ error = device_create_file(&dev->dev, &dev_attr_busconnected); -+ error = device_create_file(&dev->dev, &dev_attr_gotgctl); -+ error = device_create_file(&dev->dev, &dev_attr_gusbcfg); -+ error = device_create_file(&dev->dev, &dev_attr_grxfsiz); -+ error = device_create_file(&dev->dev, &dev_attr_gnptxfsiz); -+ error = device_create_file(&dev->dev, &dev_attr_gpvndctl); -+ error = device_create_file(&dev->dev, &dev_attr_ggpio); -+ error = device_create_file(&dev->dev, &dev_attr_guid); -+ error = device_create_file(&dev->dev, &dev_attr_gsnpsid); -+ error = device_create_file(&dev->dev, &dev_attr_devspeed); -+ error = device_create_file(&dev->dev, &dev_attr_enumspeed); -+ error = device_create_file(&dev->dev, &dev_attr_hptxfsiz); -+ error = device_create_file(&dev->dev, &dev_attr_hprt0); -+ error = device_create_file(&dev->dev, &dev_attr_remote_wakeup); -+ error = device_create_file(&dev->dev, &dev_attr_rem_wakeup_pwrdn); -+ error = device_create_file(&dev->dev, &dev_attr_disconnect_us); -+ error = device_create_file(&dev->dev, &dev_attr_regdump); -+ error = device_create_file(&dev->dev, &dev_attr_spramdump); -+ error = device_create_file(&dev->dev, &dev_attr_hcddump); -+ error = device_create_file(&dev->dev, &dev_attr_hcd_frrem); -+ error = device_create_file(&dev->dev, &dev_attr_rd_reg_test); -+ error = device_create_file(&dev->dev, &dev_attr_wr_reg_test); -+#ifdef CONFIG_USB_DWC_OTG_LPM -+ error = device_create_file(&dev->dev, &dev_attr_lpm_response); -+ error = device_create_file(&dev->dev, &dev_attr_sleep_status); -+#endif -+} -+ -+/** -+ * Remove the device files -+ */ -+void dwc_otg_attr_remove( -+#ifdef LM_INTERFACE -+ struct lm_device *dev -+#elif defined(PCI_INTERFACE) -+ struct pci_dev *dev -+#elif defined(PLATFORM_INTERFACE) -+ struct platform_device *dev -+#endif -+ ) -+{ -+ device_remove_file(&dev->dev, &dev_attr_regoffset); -+ device_remove_file(&dev->dev, &dev_attr_regvalue); -+ device_remove_file(&dev->dev, &dev_attr_mode); -+ device_remove_file(&dev->dev, &dev_attr_hnpcapable); -+ device_remove_file(&dev->dev, &dev_attr_srpcapable); -+ device_remove_file(&dev->dev, &dev_attr_hsic_connect); -+ device_remove_file(&dev->dev, &dev_attr_inv_sel_hsic); -+ device_remove_file(&dev->dev, &dev_attr_hnp); -+ device_remove_file(&dev->dev, &dev_attr_srp); -+ device_remove_file(&dev->dev, &dev_attr_buspower); -+ device_remove_file(&dev->dev, &dev_attr_bussuspend); -+ device_remove_file(&dev->dev, &dev_attr_mode_ch_tim_en); -+ device_remove_file(&dev->dev, &dev_attr_fr_interval); -+ device_remove_file(&dev->dev, &dev_attr_busconnected); -+ device_remove_file(&dev->dev, &dev_attr_gotgctl); -+ device_remove_file(&dev->dev, &dev_attr_gusbcfg); -+ device_remove_file(&dev->dev, &dev_attr_grxfsiz); -+ device_remove_file(&dev->dev, &dev_attr_gnptxfsiz); -+ device_remove_file(&dev->dev, &dev_attr_gpvndctl); -+ device_remove_file(&dev->dev, &dev_attr_ggpio); -+ device_remove_file(&dev->dev, &dev_attr_guid); -+ device_remove_file(&dev->dev, &dev_attr_gsnpsid); -+ device_remove_file(&dev->dev, &dev_attr_devspeed); -+ device_remove_file(&dev->dev, &dev_attr_enumspeed); -+ device_remove_file(&dev->dev, &dev_attr_hptxfsiz); -+ device_remove_file(&dev->dev, &dev_attr_hprt0); -+ device_remove_file(&dev->dev, &dev_attr_remote_wakeup); -+ device_remove_file(&dev->dev, &dev_attr_rem_wakeup_pwrdn); -+ device_remove_file(&dev->dev, &dev_attr_disconnect_us); -+ device_remove_file(&dev->dev, &dev_attr_regdump); -+ device_remove_file(&dev->dev, &dev_attr_spramdump); -+ device_remove_file(&dev->dev, &dev_attr_hcddump); -+ device_remove_file(&dev->dev, &dev_attr_hcd_frrem); -+ device_remove_file(&dev->dev, &dev_attr_rd_reg_test); -+ device_remove_file(&dev->dev, &dev_attr_wr_reg_test); -+#ifdef CONFIG_USB_DWC_OTG_LPM -+ device_remove_file(&dev->dev, &dev_attr_lpm_response); -+ device_remove_file(&dev->dev, &dev_attr_sleep_status); -+#endif -+} -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_attr.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_attr.h ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_attr.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_attr.h 2015-11-29 09:42:39.915098960 +0100 -@@ -0,0 +1,89 @@ -+/* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.h $ -+ * $Revision: #13 $ -+ * $Date: 2010/06/21 $ -+ * $Change: 1532021 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+ -+#if !defined(__DWC_OTG_ATTR_H__) -+#define __DWC_OTG_ATTR_H__ -+ -+/** @file -+ * This file contains the interface to the Linux device attributes. -+ */ -+extern struct device_attribute dev_attr_regoffset; -+extern struct device_attribute dev_attr_regvalue; -+ -+extern struct device_attribute dev_attr_mode; -+extern struct device_attribute dev_attr_hnpcapable; -+extern struct device_attribute dev_attr_srpcapable; -+extern struct device_attribute dev_attr_hnp; -+extern struct device_attribute dev_attr_srp; -+extern struct device_attribute dev_attr_buspower; -+extern struct device_attribute dev_attr_bussuspend; -+extern struct device_attribute dev_attr_mode_ch_tim_en; -+extern struct device_attribute dev_attr_fr_interval; -+extern struct device_attribute dev_attr_busconnected; -+extern struct device_attribute dev_attr_gotgctl; -+extern struct device_attribute dev_attr_gusbcfg; -+extern struct device_attribute dev_attr_grxfsiz; -+extern struct device_attribute dev_attr_gnptxfsiz; -+extern struct device_attribute dev_attr_gpvndctl; -+extern struct device_attribute dev_attr_ggpio; -+extern struct device_attribute dev_attr_guid; -+extern struct device_attribute dev_attr_gsnpsid; -+extern struct device_attribute dev_attr_devspeed; -+extern struct device_attribute dev_attr_enumspeed; -+extern struct device_attribute dev_attr_hptxfsiz; -+extern struct device_attribute dev_attr_hprt0; -+#ifdef CONFIG_USB_DWC_OTG_LPM -+extern struct device_attribute dev_attr_lpm_response; -+extern struct device_attribute devi_attr_sleep_status; -+#endif -+ -+void dwc_otg_attr_create( -+#ifdef LM_INTERFACE -+ struct lm_device *dev -+#elif defined(PCI_INTERFACE) -+ struct pci_dev *dev -+#elif defined(PLATFORM_INTERFACE) -+ struct platform_device *dev -+#endif -+ ); -+ -+void dwc_otg_attr_remove( -+#ifdef LM_INTERFACE -+ struct lm_device *dev -+#elif defined(PCI_INTERFACE) -+ struct pci_dev *dev -+#elif defined(PLATFORM_INTERFACE) -+ struct platform_device *dev -+#endif -+ ); -+#endif -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_cfi.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cfi.c ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_cfi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cfi.c 2015-11-29 09:42:39.915098960 +0100 -@@ -0,0 +1,1876 @@ -+/* ========================================================================== -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+ -+/** @file -+ * -+ * This file contains the most of the CFI(Core Feature Interface) -+ * implementation for the OTG. -+ */ -+ -+#ifdef DWC_UTE_CFI -+ -+#include "dwc_otg_pcd.h" -+#include "dwc_otg_cfi.h" -+ -+/** This definition should actually migrate to the Portability Library */ -+#define DWC_CONSTANT_CPU_TO_LE16(x) (x) -+ -+extern dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex); -+ -+static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen); -+static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen, -+ struct dwc_otg_pcd *pcd, -+ struct cfi_usb_ctrlrequest *ctrl_req); -+static int cfi_set_feature_value(struct dwc_otg_pcd *pcd); -+static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd, -+ struct cfi_usb_ctrlrequest *req); -+static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd, -+ struct cfi_usb_ctrlrequest *req); -+static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd, -+ struct cfi_usb_ctrlrequest *req); -+static int cfi_preproc_reset(struct dwc_otg_pcd *pcd, -+ struct cfi_usb_ctrlrequest *req); -+static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep); -+ -+static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if); -+static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue); -+static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue); -+ -+static uint8_t resize_fifos(dwc_otg_core_if_t * core_if); -+ -+/** This is the header of the all features descriptor */ -+static cfi_all_features_header_t all_props_desc_header = { -+ .wVersion = DWC_CONSTANT_CPU_TO_LE16(0x100), -+ .wCoreID = DWC_CONSTANT_CPU_TO_LE16(CFI_CORE_ID_OTG), -+ .wNumFeatures = DWC_CONSTANT_CPU_TO_LE16(9), -+}; -+ -+/** This is an array of statically allocated feature descriptors */ -+static cfi_feature_desc_header_t prop_descs[] = { -+ -+ /* FT_ID_DMA_MODE */ -+ { -+ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_MODE), -+ .bmAttributes = CFI_FEATURE_ATTR_RW, -+ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(1), -+ }, -+ -+ /* FT_ID_DMA_BUFFER_SETUP */ -+ { -+ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFFER_SETUP), -+ .bmAttributes = CFI_FEATURE_ATTR_RW, -+ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6), -+ }, -+ -+ /* FT_ID_DMA_BUFF_ALIGN */ -+ { -+ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFF_ALIGN), -+ .bmAttributes = CFI_FEATURE_ATTR_RW, -+ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2), -+ }, -+ -+ /* FT_ID_DMA_CONCAT_SETUP */ -+ { -+ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CONCAT_SETUP), -+ .bmAttributes = CFI_FEATURE_ATTR_RW, -+ //.wDataLength = DWC_CONSTANT_CPU_TO_LE16(6), -+ }, -+ -+ /* FT_ID_DMA_CIRCULAR */ -+ { -+ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CIRCULAR), -+ .bmAttributes = CFI_FEATURE_ATTR_RW, -+ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6), -+ }, -+ -+ /* FT_ID_THRESHOLD_SETUP */ -+ { -+ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_THRESHOLD_SETUP), -+ .bmAttributes = CFI_FEATURE_ATTR_RW, -+ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6), -+ }, -+ -+ /* FT_ID_DFIFO_DEPTH */ -+ { -+ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DFIFO_DEPTH), -+ .bmAttributes = CFI_FEATURE_ATTR_RO, -+ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2), -+ }, -+ -+ /* FT_ID_TX_FIFO_DEPTH */ -+ { -+ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_TX_FIFO_DEPTH), -+ .bmAttributes = CFI_FEATURE_ATTR_RW, -+ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2), -+ }, -+ -+ /* FT_ID_RX_FIFO_DEPTH */ -+ { -+ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_RX_FIFO_DEPTH), -+ .bmAttributes = CFI_FEATURE_ATTR_RW, -+ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2), -+ } -+}; -+ -+/** The table of feature names */ -+cfi_string_t prop_name_table[] = { -+ {FT_ID_DMA_MODE, "dma_mode"}, -+ {FT_ID_DMA_BUFFER_SETUP, "buffer_setup"}, -+ {FT_ID_DMA_BUFF_ALIGN, "buffer_align"}, -+ {FT_ID_DMA_CONCAT_SETUP, "concat_setup"}, -+ {FT_ID_DMA_CIRCULAR, "buffer_circular"}, -+ {FT_ID_THRESHOLD_SETUP, "threshold_setup"}, -+ {FT_ID_DFIFO_DEPTH, "dfifo_depth"}, -+ {FT_ID_TX_FIFO_DEPTH, "txfifo_depth"}, -+ {FT_ID_RX_FIFO_DEPTH, "rxfifo_depth"}, -+ {} -+}; -+ -+/************************************************************************/ -+ -+/** -+ * Returns the name of the feature by its ID -+ * or NULL if no featute ID matches. -+ * -+ */ -+const uint8_t *get_prop_name(uint16_t prop_id, int *len) -+{ -+ cfi_string_t *pstr; -+ *len = 0; -+ -+ for (pstr = prop_name_table; pstr && pstr->s; pstr++) { -+ if (pstr->id == prop_id) { -+ *len = DWC_STRLEN(pstr->s); -+ return pstr->s; -+ } -+ } -+ return NULL; -+} -+ -+/** -+ * This function handles all CFI specific control requests. -+ * -+ * Return a negative value to stall the DCE. -+ */ -+int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl) -+{ -+ int retval = 0; -+ dwc_otg_pcd_ep_t *ep = NULL; -+ cfiobject_t *cfi = pcd->cfi; -+ struct dwc_otg_core_if *coreif = GET_CORE_IF(pcd); -+ uint16_t wLen = DWC_LE16_TO_CPU(&ctrl->wLength); -+ uint16_t wValue = DWC_LE16_TO_CPU(&ctrl->wValue); -+ uint16_t wIndex = DWC_LE16_TO_CPU(&ctrl->wIndex); -+ uint32_t regaddr = 0; -+ uint32_t regval = 0; -+ -+ /* Save this Control Request in the CFI object. -+ * The data field will be assigned in the data stage completion CB function. -+ */ -+ cfi->ctrl_req = *ctrl; -+ cfi->ctrl_req.data = NULL; -+ -+ cfi->need_gadget_att = 0; -+ cfi->need_status_in_complete = 0; -+ -+ switch (ctrl->bRequest) { -+ case VEN_CORE_GET_FEATURES: -+ retval = cfi_core_features_buf(cfi->buf_in.buf, CFI_IN_BUF_LEN); -+ if (retval >= 0) { -+ //dump_msg(cfi->buf_in.buf, retval); -+ ep = &pcd->ep0; -+ -+ retval = min((uint16_t) retval, wLen); -+ /* Transfer this buffer to the host through the EP0-IN EP */ -+ ep->dwc_ep.dma_addr = cfi->buf_in.addr; -+ ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf; -+ ep->dwc_ep.xfer_buff = cfi->buf_in.buf; -+ ep->dwc_ep.xfer_len = retval; -+ ep->dwc_ep.xfer_count = 0; -+ ep->dwc_ep.sent_zlp = 0; -+ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len; -+ -+ pcd->ep0_pending = 1; -+ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep); -+ } -+ retval = 0; -+ break; -+ -+ case VEN_CORE_GET_FEATURE: -+ CFI_INFO("VEN_CORE_GET_FEATURE\n"); -+ retval = cfi_get_feature_value(cfi->buf_in.buf, CFI_IN_BUF_LEN, -+ pcd, ctrl); -+ if (retval >= 0) { -+ ep = &pcd->ep0; -+ -+ retval = min((uint16_t) retval, wLen); -+ /* Transfer this buffer to the host through the EP0-IN EP */ -+ ep->dwc_ep.dma_addr = cfi->buf_in.addr; -+ ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf; -+ ep->dwc_ep.xfer_buff = cfi->buf_in.buf; -+ ep->dwc_ep.xfer_len = retval; -+ ep->dwc_ep.xfer_count = 0; -+ ep->dwc_ep.sent_zlp = 0; -+ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len; -+ -+ pcd->ep0_pending = 1; -+ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep); -+ } -+ CFI_INFO("VEN_CORE_GET_FEATURE=%d\n", retval); -+ dump_msg(cfi->buf_in.buf, retval); -+ break; -+ -+ case VEN_CORE_SET_FEATURE: -+ CFI_INFO("VEN_CORE_SET_FEATURE\n"); -+ /* Set up an XFER to get the data stage of the control request, -+ * which is the new value of the feature to be modified. -+ */ -+ ep = &pcd->ep0; -+ ep->dwc_ep.is_in = 0; -+ ep->dwc_ep.dma_addr = cfi->buf_out.addr; -+ ep->dwc_ep.start_xfer_buff = cfi->buf_out.buf; -+ ep->dwc_ep.xfer_buff = cfi->buf_out.buf; -+ ep->dwc_ep.xfer_len = wLen; -+ ep->dwc_ep.xfer_count = 0; -+ ep->dwc_ep.sent_zlp = 0; -+ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len; -+ -+ pcd->ep0_pending = 1; -+ /* Read the control write's data stage */ -+ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep); -+ retval = 0; -+ break; -+ -+ case VEN_CORE_RESET_FEATURES: -+ CFI_INFO("VEN_CORE_RESET_FEATURES\n"); -+ cfi->need_gadget_att = 1; -+ cfi->need_status_in_complete = 1; -+ retval = cfi_preproc_reset(pcd, ctrl); -+ CFI_INFO("VEN_CORE_RESET_FEATURES = (%d)\n", retval); -+ break; -+ -+ case VEN_CORE_ACTIVATE_FEATURES: -+ CFI_INFO("VEN_CORE_ACTIVATE_FEATURES\n"); -+ break; -+ -+ case VEN_CORE_READ_REGISTER: -+ CFI_INFO("VEN_CORE_READ_REGISTER\n"); -+ /* wValue optionally contains the HI WORD of the register offset and -+ * wIndex contains the LOW WORD of the register offset -+ */ -+ if (wValue == 0) { -+ /* @TODO - MAS - fix the access to the base field */ -+ regaddr = 0; -+ //regaddr = (uint32_t) pcd->otg_dev->os_dep.base; -+ //GET_CORE_IF(pcd)->co -+ regaddr |= wIndex; -+ } else { -+ regaddr = (wValue << 16) | wIndex; -+ } -+ -+ /* Read a 32-bit value of the memory at the regaddr */ -+ regval = DWC_READ_REG32((uint32_t *) regaddr); -+ -+ ep = &pcd->ep0; -+ dwc_memcpy(cfi->buf_in.buf, ®val, sizeof(uint32_t)); -+ ep->dwc_ep.is_in = 1; -+ ep->dwc_ep.dma_addr = cfi->buf_in.addr; -+ ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf; -+ ep->dwc_ep.xfer_buff = cfi->buf_in.buf; -+ ep->dwc_ep.xfer_len = wLen; -+ ep->dwc_ep.xfer_count = 0; -+ ep->dwc_ep.sent_zlp = 0; -+ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len; -+ -+ pcd->ep0_pending = 1; -+ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep); -+ cfi->need_gadget_att = 0; -+ retval = 0; -+ break; -+ -+ case VEN_CORE_WRITE_REGISTER: -+ CFI_INFO("VEN_CORE_WRITE_REGISTER\n"); -+ /* Set up an XFER to get the data stage of the control request, -+ * which is the new value of the register to be modified. -+ */ -+ ep = &pcd->ep0; -+ ep->dwc_ep.is_in = 0; -+ ep->dwc_ep.dma_addr = cfi->buf_out.addr; -+ ep->dwc_ep.start_xfer_buff = cfi->buf_out.buf; -+ ep->dwc_ep.xfer_buff = cfi->buf_out.buf; -+ ep->dwc_ep.xfer_len = wLen; -+ ep->dwc_ep.xfer_count = 0; -+ ep->dwc_ep.sent_zlp = 0; -+ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len; -+ -+ pcd->ep0_pending = 1; -+ /* Read the control write's data stage */ -+ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep); -+ retval = 0; -+ break; -+ -+ default: -+ retval = -DWC_E_NOT_SUPPORTED; -+ break; -+ } -+ -+ return retval; -+} -+ -+/** -+ * This function prepares the core features descriptors and copies its -+ * raw representation into the buffer . -+ * -+ * The buffer structure is as follows: -+ * all_features_header (8 bytes) -+ * features_#1 (8 bytes + feature name string length) -+ * features_#2 (8 bytes + feature name string length) -+ * ..... -+ * features_#n - where n=the total count of feature descriptors -+ */ -+static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen) -+{ -+ cfi_feature_desc_header_t *prop_hdr = prop_descs; -+ cfi_feature_desc_header_t *prop; -+ cfi_all_features_header_t *all_props_hdr = &all_props_desc_header; -+ cfi_all_features_header_t *tmp; -+ uint8_t *tmpbuf = buf; -+ const uint8_t *pname = NULL; -+ int i, j, namelen = 0, totlen; -+ -+ /* Prepare and copy the core features into the buffer */ -+ CFI_INFO("%s:\n", __func__); -+ -+ tmp = (cfi_all_features_header_t *) tmpbuf; -+ *tmp = *all_props_hdr; -+ tmpbuf += CFI_ALL_FEATURES_HDR_LEN; -+ -+ j = sizeof(prop_descs) / sizeof(cfi_all_features_header_t); -+ for (i = 0; i < j; i++, prop_hdr++) { -+ pname = get_prop_name(prop_hdr->wFeatureID, &namelen); -+ prop = (cfi_feature_desc_header_t *) tmpbuf; -+ *prop = *prop_hdr; -+ -+ prop->bNameLen = namelen; -+ prop->wLength = -+ DWC_CONSTANT_CPU_TO_LE16(CFI_FEATURE_DESC_HDR_LEN + -+ namelen); -+ -+ tmpbuf += CFI_FEATURE_DESC_HDR_LEN; -+ dwc_memcpy(tmpbuf, pname, namelen); -+ tmpbuf += namelen; -+ } -+ -+ totlen = tmpbuf - buf; -+ -+ if (totlen > 0) { -+ tmp = (cfi_all_features_header_t *) buf; -+ tmp->wTotalLen = DWC_CONSTANT_CPU_TO_LE16(totlen); -+ } -+ -+ return totlen; -+} -+ -+/** -+ * This function releases all the dynamic memory in the CFI object. -+ */ -+static void cfi_release(cfiobject_t * cfiobj) -+{ -+ cfi_ep_t *cfiep; -+ dwc_list_link_t *tmp; -+ -+ CFI_INFO("%s\n", __func__); -+ -+ if (cfiobj->buf_in.buf) { -+ DWC_DMA_FREE(CFI_IN_BUF_LEN, cfiobj->buf_in.buf, -+ cfiobj->buf_in.addr); -+ cfiobj->buf_in.buf = NULL; -+ } -+ -+ if (cfiobj->buf_out.buf) { -+ DWC_DMA_FREE(CFI_OUT_BUF_LEN, cfiobj->buf_out.buf, -+ cfiobj->buf_out.addr); -+ cfiobj->buf_out.buf = NULL; -+ } -+ -+ /* Free the Buffer Setup values for each EP */ -+ //list_for_each_entry(cfiep, &cfiobj->active_eps, lh) { -+ DWC_LIST_FOREACH(tmp, &cfiobj->active_eps) { -+ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh); -+ cfi_free_ep_bs_dyn_data(cfiep); -+ } -+} -+ -+/** -+ * This function frees the dynamically allocated EP buffer setup data. -+ */ -+static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep) -+{ -+ if (cfiep->bm_sg) { -+ DWC_FREE(cfiep->bm_sg); -+ cfiep->bm_sg = NULL; -+ } -+ -+ if (cfiep->bm_align) { -+ DWC_FREE(cfiep->bm_align); -+ cfiep->bm_align = NULL; -+ } -+ -+ if (cfiep->bm_concat) { -+ if (NULL != cfiep->bm_concat->wTxBytes) { -+ DWC_FREE(cfiep->bm_concat->wTxBytes); -+ cfiep->bm_concat->wTxBytes = NULL; -+ } -+ DWC_FREE(cfiep->bm_concat); -+ cfiep->bm_concat = NULL; -+ } -+} -+ -+/** -+ * This function initializes the default values of the features -+ * for a specific endpoint and should be called only once when -+ * the EP is enabled first time. -+ */ -+static int cfi_ep_init_defaults(struct dwc_otg_pcd *pcd, cfi_ep_t * cfiep) -+{ -+ int retval = 0; -+ -+ cfiep->bm_sg = DWC_ALLOC(sizeof(ddma_sg_buffer_setup_t)); -+ if (NULL == cfiep->bm_sg) { -+ CFI_INFO("Failed to allocate memory for SG feature value\n"); -+ return -DWC_E_NO_MEMORY; -+ } -+ dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t)); -+ -+ /* For the Concatenation feature's default value we do not allocate -+ * memory for the wTxBytes field - it will be done in the set_feature_value -+ * request handler. -+ */ -+ cfiep->bm_concat = DWC_ALLOC(sizeof(ddma_concat_buffer_setup_t)); -+ if (NULL == cfiep->bm_concat) { -+ CFI_INFO -+ ("Failed to allocate memory for CONCATENATION feature value\n"); -+ DWC_FREE(cfiep->bm_sg); -+ return -DWC_E_NO_MEMORY; -+ } -+ dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t)); -+ -+ cfiep->bm_align = DWC_ALLOC(sizeof(ddma_align_buffer_setup_t)); -+ if (NULL == cfiep->bm_align) { -+ CFI_INFO -+ ("Failed to allocate memory for Alignment feature value\n"); -+ DWC_FREE(cfiep->bm_sg); -+ DWC_FREE(cfiep->bm_concat); -+ return -DWC_E_NO_MEMORY; -+ } -+ dwc_memset(cfiep->bm_align, 0, sizeof(ddma_align_buffer_setup_t)); -+ -+ return retval; -+} -+ -+/** -+ * The callback function that notifies the CFI on the activation of -+ * an endpoint in the PCD. The following steps are done in this function: -+ * -+ * Create a dynamically allocated cfi_ep_t object (a CFI wrapper to the PCD's -+ * active endpoint) -+ * Create MAX_DMA_DESCS_PER_EP count DMA Descriptors for the EP -+ * Set the Buffer Mode to standard -+ * Initialize the default values for all EP modes (SG, Circular, Concat, Align) -+ * Add the cfi_ep_t object to the list of active endpoints in the CFI object -+ */ -+static int cfi_ep_enable(struct cfiobject *cfi, struct dwc_otg_pcd *pcd, -+ struct dwc_otg_pcd_ep *ep) -+{ -+ cfi_ep_t *cfiep; -+ int retval = -DWC_E_NOT_SUPPORTED; -+ -+ CFI_INFO("%s: epname=%s; epnum=0x%02x\n", __func__, -+ "EP_" /*ep->ep.name */ , ep->desc->bEndpointAddress); -+ /* MAS - Check whether this endpoint already is in the list */ -+ cfiep = get_cfi_ep_by_pcd_ep(cfi, ep); -+ -+ if (NULL == cfiep) { -+ /* Allocate a cfi_ep_t object */ -+ cfiep = DWC_ALLOC(sizeof(cfi_ep_t)); -+ if (NULL == cfiep) { -+ CFI_INFO -+ ("Unable to allocate memory for in function %s\n", -+ __func__); -+ return -DWC_E_NO_MEMORY; -+ } -+ dwc_memset(cfiep, 0, sizeof(cfi_ep_t)); -+ -+ /* Save the dwc_otg_pcd_ep pointer in the cfiep object */ -+ cfiep->ep = ep; -+ -+ /* Allocate the DMA Descriptors chain of MAX_DMA_DESCS_PER_EP count */ -+ ep->dwc_ep.descs = -+ DWC_DMA_ALLOC(MAX_DMA_DESCS_PER_EP * -+ sizeof(dwc_otg_dma_desc_t), -+ &ep->dwc_ep.descs_dma_addr); -+ -+ if (NULL == ep->dwc_ep.descs) { -+ DWC_FREE(cfiep); -+ return -DWC_E_NO_MEMORY; -+ } -+ -+ DWC_LIST_INIT(&cfiep->lh); -+ -+ /* Set the buffer mode to BM_STANDARD. It will be modified -+ * when building descriptors for a specific buffer mode */ -+ ep->dwc_ep.buff_mode = BM_STANDARD; -+ -+ /* Create and initialize the default values for this EP's Buffer modes */ -+ if ((retval = cfi_ep_init_defaults(pcd, cfiep)) < 0) -+ return retval; -+ -+ /* Add the cfi_ep_t object to the CFI object's list of active endpoints */ -+ DWC_LIST_INSERT_TAIL(&cfi->active_eps, &cfiep->lh); -+ retval = 0; -+ } else { /* The sought EP already is in the list */ -+ CFI_INFO("%s: The sought EP already is in the list\n", -+ __func__); -+ } -+ -+ return retval; -+} -+ -+/** -+ * This function is called when the data stage of a 3-stage Control Write request -+ * is complete. -+ * -+ */ -+static int cfi_ctrl_write_complete(struct cfiobject *cfi, -+ struct dwc_otg_pcd *pcd) -+{ -+ uint32_t addr, reg_value; -+ uint16_t wIndex, wValue; -+ uint8_t bRequest; -+ uint8_t *buf = cfi->buf_out.buf; -+ //struct usb_ctrlrequest *ctrl_req = &cfi->ctrl_req_saved; -+ struct cfi_usb_ctrlrequest *ctrl_req = &cfi->ctrl_req; -+ int retval = -DWC_E_NOT_SUPPORTED; -+ -+ CFI_INFO("%s\n", __func__); -+ -+ bRequest = ctrl_req->bRequest; -+ wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex); -+ wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue); -+ -+ /* -+ * Save the pointer to the data stage in the ctrl_req's field. -+ * The request should be already saved in the command stage by now. -+ */ -+ ctrl_req->data = cfi->buf_out.buf; -+ cfi->need_status_in_complete = 0; -+ cfi->need_gadget_att = 0; -+ -+ switch (bRequest) { -+ case VEN_CORE_WRITE_REGISTER: -+ /* The buffer contains raw data of the new value for the register */ -+ reg_value = *((uint32_t *) buf); -+ if (wValue == 0) { -+ addr = 0; -+ //addr = (uint32_t) pcd->otg_dev->os_dep.base; -+ addr += wIndex; -+ } else { -+ addr = (wValue << 16) | wIndex; -+ } -+ -+ //writel(reg_value, addr); -+ -+ retval = 0; -+ cfi->need_status_in_complete = 1; -+ break; -+ -+ case VEN_CORE_SET_FEATURE: -+ /* The buffer contains raw data of the new value of the feature */ -+ retval = cfi_set_feature_value(pcd); -+ if (retval < 0) -+ return retval; -+ -+ cfi->need_status_in_complete = 1; -+ break; -+ -+ default: -+ break; -+ } -+ -+ return retval; -+} -+ -+/** -+ * This function builds the DMA descriptors for the SG buffer mode. -+ */ -+static void cfi_build_sg_descs(struct cfiobject *cfi, cfi_ep_t * cfiep, -+ dwc_otg_pcd_request_t * req) -+{ -+ struct dwc_otg_pcd_ep *ep = cfiep->ep; -+ ddma_sg_buffer_setup_t *sgval = cfiep->bm_sg; -+ struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs; -+ struct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs; -+ dma_addr_t buff_addr = req->dma; -+ int i; -+ uint32_t txsize, off; -+ -+ txsize = sgval->wSize; -+ off = sgval->bOffset; -+ -+// CFI_INFO("%s: %s TXSIZE=0x%08x; OFFSET=0x%08x\n", -+// __func__, cfiep->ep->ep.name, txsize, off); -+ -+ for (i = 0; i < sgval->bCount; i++) { -+ desc->status.b.bs = BS_HOST_BUSY; -+ desc->buf = buff_addr; -+ desc->status.b.l = 0; -+ desc->status.b.ioc = 0; -+ desc->status.b.sp = 0; -+ desc->status.b.bytes = txsize; -+ desc->status.b.bs = BS_HOST_READY; -+ -+ /* Set the next address of the buffer */ -+ buff_addr += txsize + off; -+ desc_last = desc; -+ desc++; -+ } -+ -+ /* Set the last, ioc and sp bits on the Last DMA Descriptor */ -+ desc_last->status.b.l = 1; -+ desc_last->status.b.ioc = 1; -+ desc_last->status.b.sp = ep->dwc_ep.sent_zlp; -+ /* Save the last DMA descriptor pointer */ -+ cfiep->dma_desc_last = desc_last; -+ cfiep->desc_count = sgval->bCount; -+} -+ -+/** -+ * This function builds the DMA descriptors for the Concatenation buffer mode. -+ */ -+static void cfi_build_concat_descs(struct cfiobject *cfi, cfi_ep_t * cfiep, -+ dwc_otg_pcd_request_t * req) -+{ -+ struct dwc_otg_pcd_ep *ep = cfiep->ep; -+ ddma_concat_buffer_setup_t *concatval = cfiep->bm_concat; -+ struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs; -+ struct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs; -+ dma_addr_t buff_addr = req->dma; -+ int i; -+ uint16_t *txsize; -+ -+ txsize = concatval->wTxBytes; -+ -+ for (i = 0; i < concatval->hdr.bDescCount; i++) { -+ desc->buf = buff_addr; -+ desc->status.b.bs = BS_HOST_BUSY; -+ desc->status.b.l = 0; -+ desc->status.b.ioc = 0; -+ desc->status.b.sp = 0; -+ desc->status.b.bytes = *txsize; -+ desc->status.b.bs = BS_HOST_READY; -+ -+ txsize++; -+ /* Set the next address of the buffer */ -+ buff_addr += UGETW(ep->desc->wMaxPacketSize); -+ desc_last = desc; -+ desc++; -+ } -+ -+ /* Set the last, ioc and sp bits on the Last DMA Descriptor */ -+ desc_last->status.b.l = 1; -+ desc_last->status.b.ioc = 1; -+ desc_last->status.b.sp = ep->dwc_ep.sent_zlp; -+ cfiep->dma_desc_last = desc_last; -+ cfiep->desc_count = concatval->hdr.bDescCount; -+} -+ -+/** -+ * This function builds the DMA descriptors for the Circular buffer mode -+ */ -+static void cfi_build_circ_descs(struct cfiobject *cfi, cfi_ep_t * cfiep, -+ dwc_otg_pcd_request_t * req) -+{ -+ /* @todo: MAS - add implementation when this feature needs to be tested */ -+} -+ -+/** -+ * This function builds the DMA descriptors for the Alignment buffer mode -+ */ -+static void cfi_build_align_descs(struct cfiobject *cfi, cfi_ep_t * cfiep, -+ dwc_otg_pcd_request_t * req) -+{ -+ struct dwc_otg_pcd_ep *ep = cfiep->ep; -+ ddma_align_buffer_setup_t *alignval = cfiep->bm_align; -+ struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs; -+ dma_addr_t buff_addr = req->dma; -+ -+ desc->status.b.bs = BS_HOST_BUSY; -+ desc->status.b.l = 1; -+ desc->status.b.ioc = 1; -+ desc->status.b.sp = ep->dwc_ep.sent_zlp; -+ desc->status.b.bytes = req->length; -+ /* Adjust the buffer alignment */ -+ desc->buf = (buff_addr + alignval->bAlign); -+ desc->status.b.bs = BS_HOST_READY; -+ cfiep->dma_desc_last = desc; -+ cfiep->desc_count = 1; -+} -+ -+/** -+ * This function builds the DMA descriptors chain for different modes of the -+ * buffer setup of an endpoint. -+ */ -+static void cfi_build_descriptors(struct cfiobject *cfi, -+ struct dwc_otg_pcd *pcd, -+ struct dwc_otg_pcd_ep *ep, -+ dwc_otg_pcd_request_t * req) -+{ -+ cfi_ep_t *cfiep; -+ -+ /* Get the cfiep by the dwc_otg_pcd_ep */ -+ cfiep = get_cfi_ep_by_pcd_ep(cfi, ep); -+ if (NULL == cfiep) { -+ CFI_INFO("%s: Unable to find a matching active endpoint\n", -+ __func__); -+ return; -+ } -+ -+ cfiep->xfer_len = req->length; -+ -+ /* Iterate through all the DMA descriptors */ -+ switch (cfiep->ep->dwc_ep.buff_mode) { -+ case BM_SG: -+ cfi_build_sg_descs(cfi, cfiep, req); -+ break; -+ -+ case BM_CONCAT: -+ cfi_build_concat_descs(cfi, cfiep, req); -+ break; -+ -+ case BM_CIRCULAR: -+ cfi_build_circ_descs(cfi, cfiep, req); -+ break; -+ -+ case BM_ALIGN: -+ cfi_build_align_descs(cfi, cfiep, req); -+ break; -+ -+ default: -+ break; -+ } -+} -+ -+/** -+ * Allocate DMA buffer for different Buffer modes. -+ */ -+static void *cfi_ep_alloc_buf(struct cfiobject *cfi, struct dwc_otg_pcd *pcd, -+ struct dwc_otg_pcd_ep *ep, dma_addr_t * dma, -+ unsigned size, gfp_t flags) -+{ -+ return DWC_DMA_ALLOC(size, dma); -+} -+ -+/** -+ * This function initializes the CFI object. -+ */ -+int init_cfi(cfiobject_t * cfiobj) -+{ -+ CFI_INFO("%s\n", __func__); -+ -+ /* Allocate a buffer for IN XFERs */ -+ cfiobj->buf_in.buf = -+ DWC_DMA_ALLOC(CFI_IN_BUF_LEN, &cfiobj->buf_in.addr); -+ if (NULL == cfiobj->buf_in.buf) { -+ CFI_INFO("Unable to allocate buffer for INs\n"); -+ return -DWC_E_NO_MEMORY; -+ } -+ -+ /* Allocate a buffer for OUT XFERs */ -+ cfiobj->buf_out.buf = -+ DWC_DMA_ALLOC(CFI_OUT_BUF_LEN, &cfiobj->buf_out.addr); -+ if (NULL == cfiobj->buf_out.buf) { -+ CFI_INFO("Unable to allocate buffer for OUT\n"); -+ return -DWC_E_NO_MEMORY; -+ } -+ -+ /* Initialize the callback function pointers */ -+ cfiobj->ops.release = cfi_release; -+ cfiobj->ops.ep_enable = cfi_ep_enable; -+ cfiobj->ops.ctrl_write_complete = cfi_ctrl_write_complete; -+ cfiobj->ops.build_descriptors = cfi_build_descriptors; -+ cfiobj->ops.ep_alloc_buf = cfi_ep_alloc_buf; -+ -+ /* Initialize the list of active endpoints in the CFI object */ -+ DWC_LIST_INIT(&cfiobj->active_eps); -+ -+ return 0; -+} -+ -+/** -+ * This function reads the required feature's current value into the buffer -+ * -+ * @retval: Returns negative as error, or the data length of the feature -+ */ -+static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen, -+ struct dwc_otg_pcd *pcd, -+ struct cfi_usb_ctrlrequest *ctrl_req) -+{ -+ int retval = -DWC_E_NOT_SUPPORTED; -+ struct dwc_otg_core_if *coreif = GET_CORE_IF(pcd); -+ uint16_t dfifo, rxfifo, txfifo; -+ -+ switch (ctrl_req->wIndex) { -+ /* Whether the DDMA is enabled or not */ -+ case FT_ID_DMA_MODE: -+ *buf = (coreif->dma_enable && coreif->dma_desc_enable) ? 1 : 0; -+ retval = 1; -+ break; -+ -+ case FT_ID_DMA_BUFFER_SETUP: -+ retval = cfi_ep_get_sg_val(buf, pcd, ctrl_req); -+ break; -+ -+ case FT_ID_DMA_BUFF_ALIGN: -+ retval = cfi_ep_get_align_val(buf, pcd, ctrl_req); -+ break; -+ -+ case FT_ID_DMA_CONCAT_SETUP: -+ retval = cfi_ep_get_concat_val(buf, pcd, ctrl_req); -+ break; -+ -+ case FT_ID_DMA_CIRCULAR: -+ CFI_INFO("GetFeature value (FT_ID_DMA_CIRCULAR)\n"); -+ break; -+ -+ case FT_ID_THRESHOLD_SETUP: -+ CFI_INFO("GetFeature value (FT_ID_THRESHOLD_SETUP)\n"); -+ break; -+ -+ case FT_ID_DFIFO_DEPTH: -+ dfifo = get_dfifo_size(coreif); -+ *((uint16_t *) buf) = dfifo; -+ retval = sizeof(uint16_t); -+ break; -+ -+ case FT_ID_TX_FIFO_DEPTH: -+ retval = get_txfifo_size(pcd, ctrl_req->wValue); -+ if (retval >= 0) { -+ txfifo = retval; -+ *((uint16_t *) buf) = txfifo; -+ retval = sizeof(uint16_t); -+ } -+ break; -+ -+ case FT_ID_RX_FIFO_DEPTH: -+ retval = get_rxfifo_size(coreif, ctrl_req->wValue); -+ if (retval >= 0) { -+ rxfifo = retval; -+ *((uint16_t *) buf) = rxfifo; -+ retval = sizeof(uint16_t); -+ } -+ break; -+ } -+ -+ return retval; -+} -+ -+/** -+ * This function resets the SG for the specified EP to its default value -+ */ -+static int cfi_reset_sg_val(cfi_ep_t * cfiep) -+{ -+ dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t)); -+ return 0; -+} -+ -+/** -+ * This function resets the Alignment for the specified EP to its default value -+ */ -+static int cfi_reset_align_val(cfi_ep_t * cfiep) -+{ -+ dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t)); -+ return 0; -+} -+ -+/** -+ * This function resets the Concatenation for the specified EP to its default value -+ * This function will also set the value of the wTxBytes field to NULL after -+ * freeing the memory previously allocated for this field. -+ */ -+static int cfi_reset_concat_val(cfi_ep_t * cfiep) -+{ -+ /* First we need to free the wTxBytes field */ -+ if (cfiep->bm_concat->wTxBytes) { -+ DWC_FREE(cfiep->bm_concat->wTxBytes); -+ cfiep->bm_concat->wTxBytes = NULL; -+ } -+ -+ dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t)); -+ return 0; -+} -+ -+/** -+ * This function resets all the buffer setups of the specified endpoint -+ */ -+static int cfi_ep_reset_all_setup_vals(cfi_ep_t * cfiep) -+{ -+ cfi_reset_sg_val(cfiep); -+ cfi_reset_align_val(cfiep); -+ cfi_reset_concat_val(cfiep); -+ return 0; -+} -+ -+static int cfi_handle_reset_fifo_val(struct dwc_otg_pcd *pcd, uint8_t ep_addr, -+ uint8_t rx_rst, uint8_t tx_rst) -+{ -+ int retval = -DWC_E_INVALID; -+ uint16_t tx_siz[15]; -+ uint16_t rx_siz = 0; -+ dwc_otg_pcd_ep_t *ep = NULL; -+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); -+ dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params; -+ -+ if (rx_rst) { -+ rx_siz = params->dev_rx_fifo_size; -+ params->dev_rx_fifo_size = GET_CORE_IF(pcd)->init_rxfsiz; -+ } -+ -+ if (tx_rst) { -+ if (ep_addr == 0) { -+ int i; -+ -+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { -+ tx_siz[i] = -+ core_if->core_params->dev_tx_fifo_size[i]; -+ core_if->core_params->dev_tx_fifo_size[i] = -+ core_if->init_txfsiz[i]; -+ } -+ } else { -+ -+ ep = get_ep_by_addr(pcd, ep_addr); -+ -+ if (NULL == ep) { -+ CFI_INFO -+ ("%s: Unable to get the endpoint addr=0x%02x\n", -+ __func__, ep_addr); -+ return -DWC_E_INVALID; -+ } -+ -+ tx_siz[0] = -+ params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - -+ 1]; -+ params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = -+ GET_CORE_IF(pcd)->init_txfsiz[ep-> -+ dwc_ep.tx_fifo_num - -+ 1]; -+ } -+ } -+ -+ if (resize_fifos(GET_CORE_IF(pcd))) { -+ retval = 0; -+ } else { -+ CFI_INFO -+ ("%s: Error resetting the feature Reset All(FIFO size)\n", -+ __func__); -+ if (rx_rst) { -+ params->dev_rx_fifo_size = rx_siz; -+ } -+ -+ if (tx_rst) { -+ if (ep_addr == 0) { -+ int i; -+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; -+ i++) { -+ core_if-> -+ core_params->dev_tx_fifo_size[i] = -+ tx_siz[i]; -+ } -+ } else { -+ params->dev_tx_fifo_size[ep-> -+ dwc_ep.tx_fifo_num - -+ 1] = tx_siz[0]; -+ } -+ } -+ retval = -DWC_E_INVALID; -+ } -+ return retval; -+} -+ -+static int cfi_handle_reset_all(struct dwc_otg_pcd *pcd, uint8_t addr) -+{ -+ int retval = 0; -+ cfi_ep_t *cfiep; -+ cfiobject_t *cfi = pcd->cfi; -+ dwc_list_link_t *tmp; -+ -+ retval = cfi_handle_reset_fifo_val(pcd, addr, 1, 1); -+ if (retval < 0) { -+ return retval; -+ } -+ -+ /* If the EP address is known then reset the features for only that EP */ -+ if (addr) { -+ cfiep = get_cfi_ep_by_addr(pcd->cfi, addr); -+ if (NULL == cfiep) { -+ CFI_INFO("%s: Error getting the EP address 0x%02x\n", -+ __func__, addr); -+ return -DWC_E_INVALID; -+ } -+ retval = cfi_ep_reset_all_setup_vals(cfiep); -+ cfiep->ep->dwc_ep.buff_mode = BM_STANDARD; -+ } -+ /* Otherwise (wValue == 0), reset all features of all EP's */ -+ else { -+ /* Traverse all the active EP's and reset the feature(s) value(s) */ -+ //list_for_each_entry(cfiep, &cfi->active_eps, lh) { -+ DWC_LIST_FOREACH(tmp, &cfi->active_eps) { -+ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh); -+ retval = cfi_ep_reset_all_setup_vals(cfiep); -+ cfiep->ep->dwc_ep.buff_mode = BM_STANDARD; -+ if (retval < 0) { -+ CFI_INFO -+ ("%s: Error resetting the feature Reset All\n", -+ __func__); -+ return retval; -+ } -+ } -+ } -+ return retval; -+} -+ -+static int cfi_handle_reset_dma_buff_setup(struct dwc_otg_pcd *pcd, -+ uint8_t addr) -+{ -+ int retval = 0; -+ cfi_ep_t *cfiep; -+ cfiobject_t *cfi = pcd->cfi; -+ dwc_list_link_t *tmp; -+ -+ /* If the EP address is known then reset the features for only that EP */ -+ if (addr) { -+ cfiep = get_cfi_ep_by_addr(pcd->cfi, addr); -+ if (NULL == cfiep) { -+ CFI_INFO("%s: Error getting the EP address 0x%02x\n", -+ __func__, addr); -+ return -DWC_E_INVALID; -+ } -+ retval = cfi_reset_sg_val(cfiep); -+ } -+ /* Otherwise (wValue == 0), reset all features of all EP's */ -+ else { -+ /* Traverse all the active EP's and reset the feature(s) value(s) */ -+ //list_for_each_entry(cfiep, &cfi->active_eps, lh) { -+ DWC_LIST_FOREACH(tmp, &cfi->active_eps) { -+ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh); -+ retval = cfi_reset_sg_val(cfiep); -+ if (retval < 0) { -+ CFI_INFO -+ ("%s: Error resetting the feature Buffer Setup\n", -+ __func__); -+ return retval; -+ } -+ } -+ } -+ return retval; -+} -+ -+static int cfi_handle_reset_concat_val(struct dwc_otg_pcd *pcd, uint8_t addr) -+{ -+ int retval = 0; -+ cfi_ep_t *cfiep; -+ cfiobject_t *cfi = pcd->cfi; -+ dwc_list_link_t *tmp; -+ -+ /* If the EP address is known then reset the features for only that EP */ -+ if (addr) { -+ cfiep = get_cfi_ep_by_addr(pcd->cfi, addr); -+ if (NULL == cfiep) { -+ CFI_INFO("%s: Error getting the EP address 0x%02x\n", -+ __func__, addr); -+ return -DWC_E_INVALID; -+ } -+ retval = cfi_reset_concat_val(cfiep); -+ } -+ /* Otherwise (wValue == 0), reset all features of all EP's */ -+ else { -+ /* Traverse all the active EP's and reset the feature(s) value(s) */ -+ //list_for_each_entry(cfiep, &cfi->active_eps, lh) { -+ DWC_LIST_FOREACH(tmp, &cfi->active_eps) { -+ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh); -+ retval = cfi_reset_concat_val(cfiep); -+ if (retval < 0) { -+ CFI_INFO -+ ("%s: Error resetting the feature Concatenation Value\n", -+ __func__); -+ return retval; -+ } -+ } -+ } -+ return retval; -+} -+ -+static int cfi_handle_reset_align_val(struct dwc_otg_pcd *pcd, uint8_t addr) -+{ -+ int retval = 0; -+ cfi_ep_t *cfiep; -+ cfiobject_t *cfi = pcd->cfi; -+ dwc_list_link_t *tmp; -+ -+ /* If the EP address is known then reset the features for only that EP */ -+ if (addr) { -+ cfiep = get_cfi_ep_by_addr(pcd->cfi, addr); -+ if (NULL == cfiep) { -+ CFI_INFO("%s: Error getting the EP address 0x%02x\n", -+ __func__, addr); -+ return -DWC_E_INVALID; -+ } -+ retval = cfi_reset_align_val(cfiep); -+ } -+ /* Otherwise (wValue == 0), reset all features of all EP's */ -+ else { -+ /* Traverse all the active EP's and reset the feature(s) value(s) */ -+ //list_for_each_entry(cfiep, &cfi->active_eps, lh) { -+ DWC_LIST_FOREACH(tmp, &cfi->active_eps) { -+ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh); -+ retval = cfi_reset_align_val(cfiep); -+ if (retval < 0) { -+ CFI_INFO -+ ("%s: Error resetting the feature Aliignment Value\n", -+ __func__); -+ return retval; -+ } -+ } -+ } -+ return retval; -+ -+} -+ -+static int cfi_preproc_reset(struct dwc_otg_pcd *pcd, -+ struct cfi_usb_ctrlrequest *req) -+{ -+ int retval = 0; -+ -+ switch (req->wIndex) { -+ case 0: -+ /* Reset all features */ -+ retval = cfi_handle_reset_all(pcd, req->wValue & 0xff); -+ break; -+ -+ case FT_ID_DMA_BUFFER_SETUP: -+ /* Reset the SG buffer setup */ -+ retval = -+ cfi_handle_reset_dma_buff_setup(pcd, req->wValue & 0xff); -+ break; -+ -+ case FT_ID_DMA_CONCAT_SETUP: -+ /* Reset the Concatenation buffer setup */ -+ retval = cfi_handle_reset_concat_val(pcd, req->wValue & 0xff); -+ break; -+ -+ case FT_ID_DMA_BUFF_ALIGN: -+ /* Reset the Alignment buffer setup */ -+ retval = cfi_handle_reset_align_val(pcd, req->wValue & 0xff); -+ break; -+ -+ case FT_ID_TX_FIFO_DEPTH: -+ retval = -+ cfi_handle_reset_fifo_val(pcd, req->wValue & 0xff, 0, 1); -+ pcd->cfi->need_gadget_att = 0; -+ break; -+ -+ case FT_ID_RX_FIFO_DEPTH: -+ retval = cfi_handle_reset_fifo_val(pcd, 0, 1, 0); -+ pcd->cfi->need_gadget_att = 0; -+ break; -+ default: -+ break; -+ } -+ return retval; -+} -+ -+/** -+ * This function sets a new value for the SG buffer setup. -+ */ -+static int cfi_ep_set_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd) -+{ -+ uint8_t inaddr, outaddr; -+ cfi_ep_t *epin, *epout; -+ ddma_sg_buffer_setup_t *psgval; -+ uint32_t desccount, size; -+ -+ CFI_INFO("%s\n", __func__); -+ -+ psgval = (ddma_sg_buffer_setup_t *) buf; -+ desccount = (uint32_t) psgval->bCount; -+ size = (uint32_t) psgval->wSize; -+ -+ /* Check the DMA descriptor count */ -+ if ((desccount > MAX_DMA_DESCS_PER_EP) || (desccount == 0)) { -+ CFI_INFO -+ ("%s: The count of DMA Descriptors should be between 1 and %d\n", -+ __func__, MAX_DMA_DESCS_PER_EP); -+ return -DWC_E_INVALID; -+ } -+ -+ /* Check the DMA descriptor count */ -+ -+ if (size == 0) { -+ -+ CFI_INFO("%s: The transfer size should be at least 1 byte\n", -+ __func__); -+ -+ return -DWC_E_INVALID; -+ -+ } -+ -+ inaddr = psgval->bInEndpointAddress; -+ outaddr = psgval->bOutEndpointAddress; -+ -+ epin = get_cfi_ep_by_addr(pcd->cfi, inaddr); -+ epout = get_cfi_ep_by_addr(pcd->cfi, outaddr); -+ -+ if (NULL == epin || NULL == epout) { -+ CFI_INFO -+ ("%s: Unable to get the endpoints inaddr=0x%02x outaddr=0x%02x\n", -+ __func__, inaddr, outaddr); -+ return -DWC_E_INVALID; -+ } -+ -+ epin->ep->dwc_ep.buff_mode = BM_SG; -+ dwc_memcpy(epin->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t)); -+ -+ epout->ep->dwc_ep.buff_mode = BM_SG; -+ dwc_memcpy(epout->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t)); -+ -+ return 0; -+} -+ -+/** -+ * This function sets a new value for the buffer Alignment setup. -+ */ -+static int cfi_ep_set_alignment_val(uint8_t * buf, struct dwc_otg_pcd *pcd) -+{ -+ cfi_ep_t *ep; -+ uint8_t addr; -+ ddma_align_buffer_setup_t *palignval; -+ -+ palignval = (ddma_align_buffer_setup_t *) buf; -+ addr = palignval->bEndpointAddress; -+ -+ ep = get_cfi_ep_by_addr(pcd->cfi, addr); -+ -+ if (NULL == ep) { -+ CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n", -+ __func__, addr); -+ return -DWC_E_INVALID; -+ } -+ -+ ep->ep->dwc_ep.buff_mode = BM_ALIGN; -+ dwc_memcpy(ep->bm_align, palignval, sizeof(ddma_align_buffer_setup_t)); -+ -+ return 0; -+} -+ -+/** -+ * This function sets a new value for the Concatenation buffer setup. -+ */ -+static int cfi_ep_set_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd) -+{ -+ uint8_t addr; -+ cfi_ep_t *ep; -+ struct _ddma_concat_buffer_setup_hdr *pConcatValHdr; -+ uint16_t *pVals; -+ uint32_t desccount; -+ int i; -+ uint16_t mps; -+ -+ pConcatValHdr = (struct _ddma_concat_buffer_setup_hdr *)buf; -+ desccount = (uint32_t) pConcatValHdr->bDescCount; -+ pVals = (uint16_t *) (buf + BS_CONCAT_VAL_HDR_LEN); -+ -+ /* Check the DMA descriptor count */ -+ if (desccount > MAX_DMA_DESCS_PER_EP) { -+ CFI_INFO("%s: Maximum DMA Descriptor count should be %d\n", -+ __func__, MAX_DMA_DESCS_PER_EP); -+ return -DWC_E_INVALID; -+ } -+ -+ addr = pConcatValHdr->bEndpointAddress; -+ ep = get_cfi_ep_by_addr(pcd->cfi, addr); -+ if (NULL == ep) { -+ CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n", -+ __func__, addr); -+ return -DWC_E_INVALID; -+ } -+ -+ mps = UGETW(ep->ep->desc->wMaxPacketSize); -+ -+#if 0 -+ for (i = 0; i < desccount; i++) { -+ CFI_INFO("%s: wTxSize[%d]=0x%04x\n", __func__, i, pVals[i]); -+ } -+ CFI_INFO("%s: epname=%s; mps=%d\n", __func__, ep->ep->ep.name, mps); -+#endif -+ -+ /* Check the wTxSizes to be less than or equal to the mps */ -+ for (i = 0; i < desccount; i++) { -+ if (pVals[i] > mps) { -+ CFI_INFO -+ ("%s: ERROR - the wTxSize[%d] should be <= MPS (wTxSize=%d)\n", -+ __func__, i, pVals[i]); -+ return -DWC_E_INVALID; -+ } -+ } -+ -+ ep->ep->dwc_ep.buff_mode = BM_CONCAT; -+ dwc_memcpy(ep->bm_concat, pConcatValHdr, BS_CONCAT_VAL_HDR_LEN); -+ -+ /* Free the previously allocated storage for the wTxBytes */ -+ if (ep->bm_concat->wTxBytes) { -+ DWC_FREE(ep->bm_concat->wTxBytes); -+ } -+ -+ /* Allocate a new storage for the wTxBytes field */ -+ ep->bm_concat->wTxBytes = -+ DWC_ALLOC(sizeof(uint16_t) * pConcatValHdr->bDescCount); -+ if (NULL == ep->bm_concat->wTxBytes) { -+ CFI_INFO("%s: Unable to allocate memory\n", __func__); -+ return -DWC_E_NO_MEMORY; -+ } -+ -+ /* Copy the new values into the wTxBytes filed */ -+ dwc_memcpy(ep->bm_concat->wTxBytes, buf + BS_CONCAT_VAL_HDR_LEN, -+ sizeof(uint16_t) * pConcatValHdr->bDescCount); -+ -+ return 0; -+} -+ -+/** -+ * This function calculates the total of all FIFO sizes -+ * -+ * @param core_if Programming view of DWC_otg controller -+ * -+ * @return The total of data FIFO sizes. -+ * -+ */ -+static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if) -+{ -+ dwc_otg_core_params_t *params = core_if->core_params; -+ uint16_t dfifo_total = 0; -+ int i; -+ -+ /* The shared RxFIFO size */ -+ dfifo_total = -+ params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size; -+ -+ /* Add up each TxFIFO size to the total */ -+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { -+ dfifo_total += params->dev_tx_fifo_size[i]; -+ } -+ -+ return dfifo_total; -+} -+ -+/** -+ * This function returns Rx FIFO size -+ * -+ * @param core_if Programming view of DWC_otg controller -+ * -+ * @return The total of data FIFO sizes. -+ * -+ */ -+static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue) -+{ -+ switch (wValue >> 8) { -+ case 0: -+ return (core_if->pwron_rxfsiz < -+ 32768) ? core_if->pwron_rxfsiz : 32768; -+ break; -+ case 1: -+ return core_if->core_params->dev_rx_fifo_size; -+ break; -+ default: -+ return -DWC_E_INVALID; -+ break; -+ } -+} -+ -+/** -+ * This function returns Tx FIFO size for IN EP -+ * -+ * @param core_if Programming view of DWC_otg controller -+ * -+ * @return The total of data FIFO sizes. -+ * -+ */ -+static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue) -+{ -+ dwc_otg_pcd_ep_t *ep; -+ -+ ep = get_ep_by_addr(pcd, wValue & 0xff); -+ -+ if (NULL == ep) { -+ CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n", -+ __func__, wValue & 0xff); -+ return -DWC_E_INVALID; -+ } -+ -+ if (!ep->dwc_ep.is_in) { -+ CFI_INFO -+ ("%s: No Tx FIFO assingned to the Out endpoint addr=0x%02x\n", -+ __func__, wValue & 0xff); -+ return -DWC_E_INVALID; -+ } -+ -+ switch (wValue >> 8) { -+ case 0: -+ return (GET_CORE_IF(pcd)->pwron_txfsiz -+ [ep->dwc_ep.tx_fifo_num - 1] < -+ 768) ? GET_CORE_IF(pcd)->pwron_txfsiz[ep-> -+ dwc_ep.tx_fifo_num -+ - 1] : 32768; -+ break; -+ case 1: -+ return GET_CORE_IF(pcd)->core_params-> -+ dev_tx_fifo_size[ep->dwc_ep.num - 1]; -+ break; -+ default: -+ return -DWC_E_INVALID; -+ break; -+ } -+} -+ -+/** -+ * This function checks if the submitted combination of -+ * device mode FIFO sizes is possible or not. -+ * -+ * @param core_if Programming view of DWC_otg controller -+ * -+ * @return 1 if possible, 0 otherwise. -+ * -+ */ -+static uint8_t check_fifo_sizes(dwc_otg_core_if_t * core_if) -+{ -+ uint16_t dfifo_actual = 0; -+ dwc_otg_core_params_t *params = core_if->core_params; -+ uint16_t start_addr = 0; -+ int i; -+ -+ dfifo_actual = -+ params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size; -+ -+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { -+ dfifo_actual += params->dev_tx_fifo_size[i]; -+ } -+ -+ if (dfifo_actual > core_if->total_fifo_size) { -+ return 0; -+ } -+ -+ if (params->dev_rx_fifo_size > 32768 || params->dev_rx_fifo_size < 16) -+ return 0; -+ -+ if (params->dev_nperio_tx_fifo_size > 32768 -+ || params->dev_nperio_tx_fifo_size < 16) -+ return 0; -+ -+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { -+ -+ if (params->dev_tx_fifo_size[i] > 768 -+ || params->dev_tx_fifo_size[i] < 4) -+ return 0; -+ } -+ -+ if (params->dev_rx_fifo_size > core_if->pwron_rxfsiz) -+ return 0; -+ start_addr = params->dev_rx_fifo_size; -+ -+ if (params->dev_nperio_tx_fifo_size > core_if->pwron_gnptxfsiz) -+ return 0; -+ start_addr += params->dev_nperio_tx_fifo_size; -+ -+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { -+ -+ if (params->dev_tx_fifo_size[i] > core_if->pwron_txfsiz[i]) -+ return 0; -+ start_addr += params->dev_tx_fifo_size[i]; -+ } -+ -+ return 1; -+} -+ -+/** -+ * This function resizes Device mode FIFOs -+ * -+ * @param core_if Programming view of DWC_otg controller -+ * -+ * @return 1 if successful, 0 otherwise -+ * -+ */ -+static uint8_t resize_fifos(dwc_otg_core_if_t * core_if) -+{ -+ int i = 0; -+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; -+ dwc_otg_core_params_t *params = core_if->core_params; -+ uint32_t rx_fifo_size; -+ fifosize_data_t nptxfifosize; -+ fifosize_data_t txfifosize[15]; -+ -+ uint32_t rx_fsz_bak; -+ uint32_t nptxfsz_bak; -+ uint32_t txfsz_bak[15]; -+ -+ uint16_t start_address; -+ uint8_t retval = 1; -+ -+ if (!check_fifo_sizes(core_if)) { -+ return 0; -+ } -+ -+ /* Configure data FIFO sizes */ -+ if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) { -+ rx_fsz_bak = DWC_READ_REG32(&global_regs->grxfsiz); -+ rx_fifo_size = params->dev_rx_fifo_size; -+ DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fifo_size); -+ -+ /* -+ * Tx FIFOs These FIFOs are numbered from 1 to 15. -+ * Indexes of the FIFO size module parameters in the -+ * dev_tx_fifo_size array and the FIFO size registers in -+ * the dtxfsiz array run from 0 to 14. -+ */ -+ -+ /* Non-periodic Tx FIFO */ -+ nptxfsz_bak = DWC_READ_REG32(&global_regs->gnptxfsiz); -+ nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size; -+ start_address = params->dev_rx_fifo_size; -+ nptxfifosize.b.startaddr = start_address; -+ -+ DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32); -+ -+ start_address += nptxfifosize.b.depth; -+ -+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { -+ txfsz_bak[i] = DWC_READ_REG32(&global_regs->dtxfsiz[i]); -+ -+ txfifosize[i].b.depth = params->dev_tx_fifo_size[i]; -+ txfifosize[i].b.startaddr = start_address; -+ DWC_WRITE_REG32(&global_regs->dtxfsiz[i], -+ txfifosize[i].d32); -+ -+ start_address += txfifosize[i].b.depth; -+ } -+ -+ /** Check if register values are set correctly */ -+ if (rx_fifo_size != DWC_READ_REG32(&global_regs->grxfsiz)) { -+ retval = 0; -+ } -+ -+ if (nptxfifosize.d32 != DWC_READ_REG32(&global_regs->gnptxfsiz)) { -+ retval = 0; -+ } -+ -+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { -+ if (txfifosize[i].d32 != -+ DWC_READ_REG32(&global_regs->dtxfsiz[i])) { -+ retval = 0; -+ } -+ } -+ -+ /** If register values are not set correctly, reset old values */ -+ if (retval == 0) { -+ DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fsz_bak); -+ -+ /* Non-periodic Tx FIFO */ -+ DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfsz_bak); -+ -+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { -+ DWC_WRITE_REG32(&global_regs->dtxfsiz[i], -+ txfsz_bak[i]); -+ } -+ } -+ } else { -+ return 0; -+ } -+ -+ /* Flush the FIFOs */ -+ dwc_otg_flush_tx_fifo(core_if, 0x10); /* all Tx FIFOs */ -+ dwc_otg_flush_rx_fifo(core_if); -+ -+ return retval; -+} -+ -+/** -+ * This function sets a new value for the buffer Alignment setup. -+ */ -+static int cfi_ep_set_tx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd) -+{ -+ int retval; -+ uint32_t fsiz; -+ uint16_t size; -+ uint16_t ep_addr; -+ dwc_otg_pcd_ep_t *ep; -+ dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params; -+ tx_fifo_size_setup_t *ptxfifoval; -+ -+ ptxfifoval = (tx_fifo_size_setup_t *) buf; -+ ep_addr = ptxfifoval->bEndpointAddress; -+ size = ptxfifoval->wDepth; -+ -+ ep = get_ep_by_addr(pcd, ep_addr); -+ -+ CFI_INFO -+ ("%s: Set Tx FIFO size: endpoint addr=0x%02x, depth=%d, FIFO Num=%d\n", -+ __func__, ep_addr, size, ep->dwc_ep.tx_fifo_num); -+ -+ if (NULL == ep) { -+ CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n", -+ __func__, ep_addr); -+ return -DWC_E_INVALID; -+ } -+ -+ fsiz = params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1]; -+ params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = size; -+ -+ if (resize_fifos(GET_CORE_IF(pcd))) { -+ retval = 0; -+ } else { -+ CFI_INFO -+ ("%s: Error setting the feature Tx FIFO Size for EP%d\n", -+ __func__, ep_addr); -+ params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = fsiz; -+ retval = -DWC_E_INVALID; -+ } -+ -+ return retval; -+} -+ -+/** -+ * This function sets a new value for the buffer Alignment setup. -+ */ -+static int cfi_set_rx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd) -+{ -+ int retval; -+ uint32_t fsiz; -+ uint16_t size; -+ dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params; -+ rx_fifo_size_setup_t *prxfifoval; -+ -+ prxfifoval = (rx_fifo_size_setup_t *) buf; -+ size = prxfifoval->wDepth; -+ -+ fsiz = params->dev_rx_fifo_size; -+ params->dev_rx_fifo_size = size; -+ -+ if (resize_fifos(GET_CORE_IF(pcd))) { -+ retval = 0; -+ } else { -+ CFI_INFO("%s: Error setting the feature Rx FIFO Size\n", -+ __func__); -+ params->dev_rx_fifo_size = fsiz; -+ retval = -DWC_E_INVALID; -+ } -+ -+ return retval; -+} -+ -+/** -+ * This function reads the SG of an EP's buffer setup into the buffer buf -+ */ -+static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd, -+ struct cfi_usb_ctrlrequest *req) -+{ -+ int retval = -DWC_E_INVALID; -+ uint8_t addr; -+ cfi_ep_t *ep; -+ -+ /* The Low Byte of the wValue contains a non-zero address of the endpoint */ -+ addr = req->wValue & 0xFF; -+ if (addr == 0) /* The address should be non-zero */ -+ return retval; -+ -+ ep = get_cfi_ep_by_addr(pcd->cfi, addr); -+ if (NULL == ep) { -+ CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n", -+ __func__, addr); -+ return retval; -+ } -+ -+ dwc_memcpy(buf, ep->bm_sg, BS_SG_VAL_DESC_LEN); -+ retval = BS_SG_VAL_DESC_LEN; -+ return retval; -+} -+ -+/** -+ * This function reads the Concatenation value of an EP's buffer mode into -+ * the buffer buf -+ */ -+static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd, -+ struct cfi_usb_ctrlrequest *req) -+{ -+ int retval = -DWC_E_INVALID; -+ uint8_t addr; -+ cfi_ep_t *ep; -+ uint8_t desc_count; -+ -+ /* The Low Byte of the wValue contains a non-zero address of the endpoint */ -+ addr = req->wValue & 0xFF; -+ if (addr == 0) /* The address should be non-zero */ -+ return retval; -+ -+ ep = get_cfi_ep_by_addr(pcd->cfi, addr); -+ if (NULL == ep) { -+ CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n", -+ __func__, addr); -+ return retval; -+ } -+ -+ /* Copy the header to the buffer */ -+ dwc_memcpy(buf, ep->bm_concat, BS_CONCAT_VAL_HDR_LEN); -+ /* Advance the buffer pointer by the header size */ -+ buf += BS_CONCAT_VAL_HDR_LEN; -+ -+ desc_count = ep->bm_concat->hdr.bDescCount; -+ /* Copy alll the wTxBytes to the buffer */ -+ dwc_memcpy(buf, ep->bm_concat->wTxBytes, sizeof(uid16_t) * desc_count); -+ -+ retval = BS_CONCAT_VAL_HDR_LEN + sizeof(uid16_t) * desc_count; -+ return retval; -+} -+ -+/** -+ * This function reads the buffer Alignment value of an EP's buffer mode into -+ * the buffer buf -+ * -+ * @return The total number of bytes copied to the buffer or negative error code. -+ */ -+static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd, -+ struct cfi_usb_ctrlrequest *req) -+{ -+ int retval = -DWC_E_INVALID; -+ uint8_t addr; -+ cfi_ep_t *ep; -+ -+ /* The Low Byte of the wValue contains a non-zero address of the endpoint */ -+ addr = req->wValue & 0xFF; -+ if (addr == 0) /* The address should be non-zero */ -+ return retval; -+ -+ ep = get_cfi_ep_by_addr(pcd->cfi, addr); -+ if (NULL == ep) { -+ CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n", -+ __func__, addr); -+ return retval; -+ } -+ -+ dwc_memcpy(buf, ep->bm_align, BS_ALIGN_VAL_HDR_LEN); -+ retval = BS_ALIGN_VAL_HDR_LEN; -+ -+ return retval; -+} -+ -+/** -+ * This function sets a new value for the specified feature -+ * -+ * @param pcd A pointer to the PCD object -+ * -+ * @return 0 if successful, negative error code otherwise to stall the DCE. -+ */ -+static int cfi_set_feature_value(struct dwc_otg_pcd *pcd) -+{ -+ int retval = -DWC_E_NOT_SUPPORTED; -+ uint16_t wIndex, wValue; -+ uint8_t bRequest; -+ struct dwc_otg_core_if *coreif; -+ cfiobject_t *cfi = pcd->cfi; -+ struct cfi_usb_ctrlrequest *ctrl_req; -+ uint8_t *buf; -+ ctrl_req = &cfi->ctrl_req; -+ -+ buf = pcd->cfi->ctrl_req.data; -+ -+ coreif = GET_CORE_IF(pcd); -+ bRequest = ctrl_req->bRequest; -+ wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex); -+ wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue); -+ -+ /* See which feature is to be modified */ -+ switch (wIndex) { -+ case FT_ID_DMA_BUFFER_SETUP: -+ /* Modify the feature */ -+ if ((retval = cfi_ep_set_sg_val(buf, pcd)) < 0) -+ return retval; -+ -+ /* And send this request to the gadget */ -+ cfi->need_gadget_att = 1; -+ break; -+ -+ case FT_ID_DMA_BUFF_ALIGN: -+ if ((retval = cfi_ep_set_alignment_val(buf, pcd)) < 0) -+ return retval; -+ cfi->need_gadget_att = 1; -+ break; -+ -+ case FT_ID_DMA_CONCAT_SETUP: -+ /* Modify the feature */ -+ if ((retval = cfi_ep_set_concat_val(buf, pcd)) < 0) -+ return retval; -+ cfi->need_gadget_att = 1; -+ break; -+ -+ case FT_ID_DMA_CIRCULAR: -+ CFI_INFO("FT_ID_DMA_CIRCULAR\n"); -+ break; -+ -+ case FT_ID_THRESHOLD_SETUP: -+ CFI_INFO("FT_ID_THRESHOLD_SETUP\n"); -+ break; -+ -+ case FT_ID_DFIFO_DEPTH: -+ CFI_INFO("FT_ID_DFIFO_DEPTH\n"); -+ break; -+ -+ case FT_ID_TX_FIFO_DEPTH: -+ CFI_INFO("FT_ID_TX_FIFO_DEPTH\n"); -+ if ((retval = cfi_ep_set_tx_fifo_val(buf, pcd)) < 0) -+ return retval; -+ cfi->need_gadget_att = 0; -+ break; -+ -+ case FT_ID_RX_FIFO_DEPTH: -+ CFI_INFO("FT_ID_RX_FIFO_DEPTH\n"); -+ if ((retval = cfi_set_rx_fifo_val(buf, pcd)) < 0) -+ return retval; -+ cfi->need_gadget_att = 0; -+ break; -+ } -+ -+ return retval; -+} -+ -+#endif //DWC_UTE_CFI -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_cfi.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cfi.h ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_cfi.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cfi.h 2015-11-29 09:42:39.915098960 +0100 -@@ -0,0 +1,320 @@ -+/* ========================================================================== -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+ -+#if !defined(__DWC_OTG_CFI_H__) -+#define __DWC_OTG_CFI_H__ -+ -+#include "dwc_otg_pcd.h" -+#include "dwc_cfi_common.h" -+ -+/** -+ * @file -+ * This file contains the CFI related OTG PCD specific common constants, -+ * interfaces(functions and macros) and data structures.The CFI Protocol is an -+ * optional interface for internal testing purposes that a DUT may implement to -+ * support testing of configurable features. -+ * -+ */ -+ -+struct dwc_otg_pcd; -+struct dwc_otg_pcd_ep; -+ -+/** OTG CFI Features (properties) ID constants */ -+/** This is a request for all Core Features */ -+#define FT_ID_DMA_MODE 0x0001 -+#define FT_ID_DMA_BUFFER_SETUP 0x0002 -+#define FT_ID_DMA_BUFF_ALIGN 0x0003 -+#define FT_ID_DMA_CONCAT_SETUP 0x0004 -+#define FT_ID_DMA_CIRCULAR 0x0005 -+#define FT_ID_THRESHOLD_SETUP 0x0006 -+#define FT_ID_DFIFO_DEPTH 0x0007 -+#define FT_ID_TX_FIFO_DEPTH 0x0008 -+#define FT_ID_RX_FIFO_DEPTH 0x0009 -+ -+/**********************************************************/ -+#define CFI_INFO_DEF -+ -+#ifdef CFI_INFO_DEF -+#define CFI_INFO(fmt...) DWC_PRINTF("CFI: " fmt); -+#else -+#define CFI_INFO(fmt...) -+#endif -+ -+#define min(x,y) ({ \ -+ x < y ? x : y; }) -+ -+#define max(x,y) ({ \ -+ x > y ? x : y; }) -+ -+/** -+ * Descriptor DMA SG Buffer setup structure (SG buffer). This structure is -+ * also used for setting up a buffer for Circular DDMA. -+ */ -+struct _ddma_sg_buffer_setup { -+#define BS_SG_VAL_DESC_LEN 6 -+ /* The OUT EP address */ -+ uint8_t bOutEndpointAddress; -+ /* The IN EP address */ -+ uint8_t bInEndpointAddress; -+ /* Number of bytes to put between transfer segments (must be DWORD boundaries) */ -+ uint8_t bOffset; -+ /* The number of transfer segments (a DMA descriptors per each segment) */ -+ uint8_t bCount; -+ /* Size (in byte) of each transfer segment */ -+ uint16_t wSize; -+} __attribute__ ((packed)); -+typedef struct _ddma_sg_buffer_setup ddma_sg_buffer_setup_t; -+ -+/** Descriptor DMA Concatenation Buffer setup structure */ -+struct _ddma_concat_buffer_setup_hdr { -+#define BS_CONCAT_VAL_HDR_LEN 4 -+ /* The endpoint for which the buffer is to be set up */ -+ uint8_t bEndpointAddress; -+ /* The count of descriptors to be used */ -+ uint8_t bDescCount; -+ /* The total size of the transfer */ -+ uint16_t wSize; -+} __attribute__ ((packed)); -+typedef struct _ddma_concat_buffer_setup_hdr ddma_concat_buffer_setup_hdr_t; -+ -+/** Descriptor DMA Concatenation Buffer setup structure */ -+struct _ddma_concat_buffer_setup { -+ /* The SG header */ -+ ddma_concat_buffer_setup_hdr_t hdr; -+ -+ /* The XFER sizes pointer (allocated dynamically) */ -+ uint16_t *wTxBytes; -+} __attribute__ ((packed)); -+typedef struct _ddma_concat_buffer_setup ddma_concat_buffer_setup_t; -+ -+/** Descriptor DMA Alignment Buffer setup structure */ -+struct _ddma_align_buffer_setup { -+#define BS_ALIGN_VAL_HDR_LEN 2 -+ uint8_t bEndpointAddress; -+ uint8_t bAlign; -+} __attribute__ ((packed)); -+typedef struct _ddma_align_buffer_setup ddma_align_buffer_setup_t; -+ -+/** Transmit FIFO Size setup structure */ -+struct _tx_fifo_size_setup { -+ uint8_t bEndpointAddress; -+ uint16_t wDepth; -+} __attribute__ ((packed)); -+typedef struct _tx_fifo_size_setup tx_fifo_size_setup_t; -+ -+/** Transmit FIFO Size setup structure */ -+struct _rx_fifo_size_setup { -+ uint16_t wDepth; -+} __attribute__ ((packed)); -+typedef struct _rx_fifo_size_setup rx_fifo_size_setup_t; -+ -+/** -+ * struct cfi_usb_ctrlrequest - the CFI implementation of the struct usb_ctrlrequest -+ * This structure encapsulates the standard usb_ctrlrequest and adds a pointer -+ * to the data returned in the data stage of a 3-stage Control Write requests. -+ */ -+struct cfi_usb_ctrlrequest { -+ uint8_t bRequestType; -+ uint8_t bRequest; -+ uint16_t wValue; -+ uint16_t wIndex; -+ uint16_t wLength; -+ uint8_t *data; -+} UPACKED; -+ -+/*---------------------------------------------------------------------------*/ -+ -+/** -+ * The CFI wrapper of the enabled and activated dwc_otg_pcd_ep structures. -+ * This structure is used to store the buffer setup data for any -+ * enabled endpoint in the PCD. -+ */ -+struct cfi_ep { -+ /* Entry for the list container */ -+ dwc_list_link_t lh; -+ /* Pointer to the active PCD endpoint structure */ -+ struct dwc_otg_pcd_ep *ep; -+ /* The last descriptor in the chain of DMA descriptors of the endpoint */ -+ struct dwc_otg_dma_desc *dma_desc_last; -+ /* The SG feature value */ -+ ddma_sg_buffer_setup_t *bm_sg; -+ /* The Circular feature value */ -+ ddma_sg_buffer_setup_t *bm_circ; -+ /* The Concatenation feature value */ -+ ddma_concat_buffer_setup_t *bm_concat; -+ /* The Alignment feature value */ -+ ddma_align_buffer_setup_t *bm_align; -+ /* XFER length */ -+ uint32_t xfer_len; -+ /* -+ * Count of DMA descriptors currently used. -+ * The total should not exceed the MAX_DMA_DESCS_PER_EP value -+ * defined in the dwc_otg_cil.h -+ */ -+ uint32_t desc_count; -+}; -+typedef struct cfi_ep cfi_ep_t; -+ -+typedef struct cfi_dma_buff { -+#define CFI_IN_BUF_LEN 1024 -+#define CFI_OUT_BUF_LEN 1024 -+ dma_addr_t addr; -+ uint8_t *buf; -+} cfi_dma_buff_t; -+ -+struct cfiobject; -+ -+/** -+ * This is the interface for the CFI operations. -+ * -+ * @param ep_enable Called when any endpoint is enabled and activated. -+ * @param release Called when the CFI object is released and it needs to correctly -+ * deallocate the dynamic memory -+ * @param ctrl_write_complete Called when the data stage of the request is complete -+ */ -+typedef struct cfi_ops { -+ int (*ep_enable) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd, -+ struct dwc_otg_pcd_ep * ep); -+ void *(*ep_alloc_buf) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd, -+ struct dwc_otg_pcd_ep * ep, dma_addr_t * dma, -+ unsigned size, gfp_t flags); -+ void (*release) (struct cfiobject * cfi); -+ int (*ctrl_write_complete) (struct cfiobject * cfi, -+ struct dwc_otg_pcd * pcd); -+ void (*build_descriptors) (struct cfiobject * cfi, -+ struct dwc_otg_pcd * pcd, -+ struct dwc_otg_pcd_ep * ep, -+ dwc_otg_pcd_request_t * req); -+} cfi_ops_t; -+ -+struct cfiobject { -+ cfi_ops_t ops; -+ struct dwc_otg_pcd *pcd; -+ struct usb_gadget *gadget; -+ -+ /* Buffers used to send/receive CFI-related request data */ -+ cfi_dma_buff_t buf_in; -+ cfi_dma_buff_t buf_out; -+ -+ /* CFI specific Control request wrapper */ -+ struct cfi_usb_ctrlrequest ctrl_req; -+ -+ /* The list of active EP's in the PCD of type cfi_ep_t */ -+ dwc_list_link_t active_eps; -+ -+ /* This flag shall control the propagation of a specific request -+ * to the gadget's processing routines. -+ * 0 - no gadget handling -+ * 1 - the gadget needs to know about this request (w/o completing a status -+ * phase - just return a 0 to the _setup callback) -+ */ -+ uint8_t need_gadget_att; -+ -+ /* Flag indicating whether the status IN phase needs to be -+ * completed by the PCD -+ */ -+ uint8_t need_status_in_complete; -+}; -+typedef struct cfiobject cfiobject_t; -+ -+#define DUMP_MSG -+ -+#if defined(DUMP_MSG) -+static inline void dump_msg(const u8 * buf, unsigned int length) -+{ -+ unsigned int start, num, i; -+ char line[52], *p; -+ -+ if (length >= 512) -+ return; -+ -+ start = 0; -+ while (length > 0) { -+ num = min(length, 16u); -+ p = line; -+ for (i = 0; i < num; ++i) { -+ if (i == 8) -+ *p++ = ' '; -+ DWC_SPRINTF(p, " %02x", buf[i]); -+ p += 3; -+ } -+ *p = 0; -+ DWC_DEBUG("%6x: %s\n", start, line); -+ buf += num; -+ start += num; -+ length -= num; -+ } -+} -+#else -+static inline void dump_msg(const u8 * buf, unsigned int length) -+{ -+} -+#endif -+ -+/** -+ * This function returns a pointer to cfi_ep_t object with the addr address. -+ */ -+static inline struct cfi_ep *get_cfi_ep_by_addr(struct cfiobject *cfi, -+ uint8_t addr) -+{ -+ struct cfi_ep *pcfiep; -+ dwc_list_link_t *tmp; -+ -+ DWC_LIST_FOREACH(tmp, &cfi->active_eps) { -+ pcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh); -+ -+ if (pcfiep->ep->desc->bEndpointAddress == addr) { -+ return pcfiep; -+ } -+ } -+ -+ return NULL; -+} -+ -+/** -+ * This function returns a pointer to cfi_ep_t object that matches -+ * the dwc_otg_pcd_ep object. -+ */ -+static inline struct cfi_ep *get_cfi_ep_by_pcd_ep(struct cfiobject *cfi, -+ struct dwc_otg_pcd_ep *ep) -+{ -+ struct cfi_ep *pcfiep = NULL; -+ dwc_list_link_t *tmp; -+ -+ DWC_LIST_FOREACH(tmp, &cfi->active_eps) { -+ pcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh); -+ if (pcfiep->ep == ep) { -+ return pcfiep; -+ } -+ } -+ return NULL; -+} -+ -+int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl); -+ -+#endif /* (__DWC_OTG_CFI_H__) */ -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_cil.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cil.c ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_cil.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cil.c 2015-11-29 09:42:39.919098694 +0100 -@@ -0,0 +1,7141 @@ -+/* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.c $ -+ * $Revision: #191 $ -+ * $Date: 2012/08/10 $ -+ * $Change: 2047372 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+ -+/** @file -+ * -+ * The Core Interface Layer provides basic services for accessing and -+ * managing the DWC_otg hardware. These services are used by both the -+ * Host Controller Driver and the Peripheral Controller Driver. -+ * -+ * The CIL manages the memory map for the core so that the HCD and PCD -+ * don't have to do this separately. It also handles basic tasks like -+ * reading/writing the registers and data FIFOs in the controller. -+ * Some of the data access functions provide encapsulation of several -+ * operations required to perform a task, such as writing multiple -+ * registers to start a transfer. Finally, the CIL performs basic -+ * services that are not specific to either the host or device modes -+ * of operation. These services include management of the OTG Host -+ * Negotiation Protocol (HNP) and Session Request Protocol (SRP). A -+ * Diagnostic API is also provided to allow testing of the controller -+ * hardware. -+ * -+ * The Core Interface Layer has the following requirements: -+ * - Provides basic controller operations. -+ * - Minimal use of OS services. -+ * - The OS services used will be abstracted by using inline functions -+ * or macros. -+ * -+ */ -+ -+#include "dwc_os.h" -+#include "dwc_otg_regs.h" -+#include "dwc_otg_cil.h" -+ -+static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if); -+ -+/** -+ * This function is called to initialize the DWC_otg CSR data -+ * structures. The register addresses in the device and host -+ * structures are initialized from the base address supplied by the -+ * caller. The calling function must make the OS calls to get the -+ * base address of the DWC_otg controller registers. The core_params -+ * argument holds the parameters that specify how the core should be -+ * configured. -+ * -+ * @param reg_base_addr Base address of DWC_otg core registers -+ * -+ */ -+dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * reg_base_addr) -+{ -+ dwc_otg_core_if_t *core_if = 0; -+ dwc_otg_dev_if_t *dev_if = 0; -+ dwc_otg_host_if_t *host_if = 0; -+ uint8_t *reg_base = (uint8_t *) reg_base_addr; -+ int i = 0; -+ -+ DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, reg_base_addr); -+ -+ core_if = DWC_ALLOC(sizeof(dwc_otg_core_if_t)); -+ -+ if (core_if == NULL) { -+ DWC_DEBUGPL(DBG_CIL, -+ "Allocation of dwc_otg_core_if_t failed\n"); -+ return 0; -+ } -+ core_if->core_global_regs = (dwc_otg_core_global_regs_t *) reg_base; -+ -+ /* -+ * Allocate the Device Mode structures. -+ */ -+ dev_if = DWC_ALLOC(sizeof(dwc_otg_dev_if_t)); -+ -+ if (dev_if == NULL) { -+ DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n"); -+ DWC_FREE(core_if); -+ return 0; -+ } -+ -+ dev_if->dev_global_regs = -+ (dwc_otg_device_global_regs_t *) (reg_base + -+ DWC_DEV_GLOBAL_REG_OFFSET); -+ -+ for (i = 0; i < MAX_EPS_CHANNELS; i++) { -+ dev_if->in_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *) -+ (reg_base + DWC_DEV_IN_EP_REG_OFFSET + -+ (i * DWC_EP_REG_OFFSET)); -+ -+ dev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *) -+ (reg_base + DWC_DEV_OUT_EP_REG_OFFSET + -+ (i * DWC_EP_REG_OFFSET)); -+ DWC_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p\n", -+ i, &dev_if->in_ep_regs[i]->diepctl); -+ DWC_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p\n", -+ i, &dev_if->out_ep_regs[i]->doepctl); -+ } -+ -+ dev_if->speed = 0; // unknown -+ -+ core_if->dev_if = dev_if; -+ -+ /* -+ * Allocate the Host Mode structures. -+ */ -+ host_if = DWC_ALLOC(sizeof(dwc_otg_host_if_t)); -+ -+ if (host_if == NULL) { -+ DWC_DEBUGPL(DBG_CIL, -+ "Allocation of dwc_otg_host_if_t failed\n"); -+ DWC_FREE(dev_if); -+ DWC_FREE(core_if); -+ return 0; -+ } -+ -+ host_if->host_global_regs = (dwc_otg_host_global_regs_t *) -+ (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET); -+ -+ host_if->hprt0 = -+ (uint32_t *) (reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET); -+ -+ for (i = 0; i < MAX_EPS_CHANNELS; i++) { -+ host_if->hc_regs[i] = (dwc_otg_hc_regs_t *) -+ (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET + -+ (i * DWC_OTG_CHAN_REGS_OFFSET)); -+ DWC_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n", -+ i, &host_if->hc_regs[i]->hcchar); -+ } -+ -+ host_if->num_host_channels = MAX_EPS_CHANNELS; -+ core_if->host_if = host_if; -+ -+ for (i = 0; i < MAX_EPS_CHANNELS; i++) { -+ core_if->data_fifo[i] = -+ (uint32_t *) (reg_base + DWC_OTG_DATA_FIFO_OFFSET + -+ (i * DWC_OTG_DATA_FIFO_SIZE)); -+ DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08lx\n", -+ i, (unsigned long)core_if->data_fifo[i]); -+ } -+ -+ core_if->pcgcctl = (uint32_t *) (reg_base + DWC_OTG_PCGCCTL_OFFSET); -+ -+ /* Initiate lx_state to L3 disconnected state */ -+ core_if->lx_state = DWC_OTG_L3; -+ /* -+ * Store the contents of the hardware configuration registers here for -+ * easy access later. -+ */ -+ core_if->hwcfg1.d32 = -+ DWC_READ_REG32(&core_if->core_global_regs->ghwcfg1); -+ core_if->hwcfg2.d32 = -+ DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2); -+ core_if->hwcfg3.d32 = -+ DWC_READ_REG32(&core_if->core_global_regs->ghwcfg3); -+ core_if->hwcfg4.d32 = -+ DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4); -+ -+ /* Force host mode to get HPTXFSIZ exact power on value */ -+ { -+ gusbcfg_data_t gusbcfg = {.d32 = 0 }; -+ gusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); -+ gusbcfg.b.force_host_mode = 1; -+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32); -+ dwc_mdelay(100); -+ core_if->hptxfsiz.d32 = -+ DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz); -+ gusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); -+ gusbcfg.b.force_host_mode = 1; -+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32); -+ dwc_mdelay(100); -+ } -+ -+ DWC_DEBUGPL(DBG_CILV, "hwcfg1=%08x\n", core_if->hwcfg1.d32); -+ DWC_DEBUGPL(DBG_CILV, "hwcfg2=%08x\n", core_if->hwcfg2.d32); -+ DWC_DEBUGPL(DBG_CILV, "hwcfg3=%08x\n", core_if->hwcfg3.d32); -+ DWC_DEBUGPL(DBG_CILV, "hwcfg4=%08x\n", core_if->hwcfg4.d32); -+ -+ core_if->hcfg.d32 = -+ DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg); -+ core_if->dcfg.d32 = -+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); -+ -+ DWC_DEBUGPL(DBG_CILV, "hcfg=%08x\n", core_if->hcfg.d32); -+ DWC_DEBUGPL(DBG_CILV, "dcfg=%08x\n", core_if->dcfg.d32); -+ -+ DWC_DEBUGPL(DBG_CILV, "op_mode=%0x\n", core_if->hwcfg2.b.op_mode); -+ DWC_DEBUGPL(DBG_CILV, "arch=%0x\n", core_if->hwcfg2.b.architecture); -+ DWC_DEBUGPL(DBG_CILV, "num_dev_ep=%d\n", core_if->hwcfg2.b.num_dev_ep); -+ DWC_DEBUGPL(DBG_CILV, "num_host_chan=%d\n", -+ core_if->hwcfg2.b.num_host_chan); -+ DWC_DEBUGPL(DBG_CILV, "nonperio_tx_q_depth=0x%0x\n", -+ core_if->hwcfg2.b.nonperio_tx_q_depth); -+ DWC_DEBUGPL(DBG_CILV, "host_perio_tx_q_depth=0x%0x\n", -+ core_if->hwcfg2.b.host_perio_tx_q_depth); -+ DWC_DEBUGPL(DBG_CILV, "dev_token_q_depth=0x%0x\n", -+ core_if->hwcfg2.b.dev_token_q_depth); -+ -+ DWC_DEBUGPL(DBG_CILV, "Total FIFO SZ=%d\n", -+ core_if->hwcfg3.b.dfifo_depth); -+ DWC_DEBUGPL(DBG_CILV, "xfer_size_cntr_width=%0x\n", -+ core_if->hwcfg3.b.xfer_size_cntr_width); -+ -+ /* -+ * Set the SRP sucess bit for FS-I2c -+ */ -+ core_if->srp_success = 0; -+ core_if->srp_timer_started = 0; -+ -+ /* -+ * Create new workqueue and init works -+ */ -+ core_if->wq_otg = DWC_WORKQ_ALLOC("dwc_otg"); -+ if (core_if->wq_otg == 0) { -+ DWC_WARN("DWC_WORKQ_ALLOC failed\n"); -+ DWC_FREE(host_if); -+ DWC_FREE(dev_if); -+ DWC_FREE(core_if); -+ return 0; -+ } -+ -+ core_if->snpsid = DWC_READ_REG32(&core_if->core_global_regs->gsnpsid); -+ -+ DWC_PRINTF("Core Release: %x.%x%x%x\n", -+ (core_if->snpsid >> 12 & 0xF), -+ (core_if->snpsid >> 8 & 0xF), -+ (core_if->snpsid >> 4 & 0xF), (core_if->snpsid & 0xF)); -+ -+ core_if->wkp_timer = DWC_TIMER_ALLOC("Wake Up Timer", -+ w_wakeup_detected, core_if); -+ if (core_if->wkp_timer == 0) { -+ DWC_WARN("DWC_TIMER_ALLOC failed\n"); -+ DWC_FREE(host_if); -+ DWC_FREE(dev_if); -+ DWC_WORKQ_FREE(core_if->wq_otg); -+ DWC_FREE(core_if); -+ return 0; -+ } -+ -+ if (dwc_otg_setup_params(core_if)) { -+ DWC_WARN("Error while setting core params\n"); -+ } -+ -+ core_if->hibernation_suspend = 0; -+ -+ /** ADP initialization */ -+ dwc_otg_adp_init(core_if); -+ -+ return core_if; -+} -+ -+/** -+ * This function frees the structures allocated by dwc_otg_cil_init(). -+ * -+ * @param core_if The core interface pointer returned from -+ * dwc_otg_cil_init(). -+ * -+ */ -+void dwc_otg_cil_remove(dwc_otg_core_if_t * core_if) -+{ -+ dctl_data_t dctl = {.d32 = 0 }; -+ DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if); -+ -+ /* Disable all interrupts */ -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 1, 0); -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0); -+ -+ dctl.b.sftdiscon = 1; -+ if (core_if->snpsid >= OTG_CORE_REV_3_00a) { -+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, -+ dctl.d32); -+ } -+ -+ if (core_if->wq_otg) { -+ DWC_WORKQ_WAIT_WORK_DONE(core_if->wq_otg, 500); -+ DWC_WORKQ_FREE(core_if->wq_otg); -+ } -+ if (core_if->dev_if) { -+ DWC_FREE(core_if->dev_if); -+ } -+ if (core_if->host_if) { -+ DWC_FREE(core_if->host_if); -+ } -+ -+ /** Remove ADP Stuff */ -+ dwc_otg_adp_remove(core_if); -+ if (core_if->core_params) { -+ DWC_FREE(core_if->core_params); -+ } -+ if (core_if->wkp_timer) { -+ DWC_TIMER_FREE(core_if->wkp_timer); -+ } -+ if (core_if->srp_timer) { -+ DWC_TIMER_FREE(core_if->srp_timer); -+ } -+ DWC_FREE(core_if); -+} -+ -+/** -+ * This function enables the controller's Global Interrupt in the AHB Config -+ * register. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ */ -+void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * core_if) -+{ -+ gahbcfg_data_t ahbcfg = {.d32 = 0 }; -+ ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32); -+} -+ -+/** -+ * This function disables the controller's Global Interrupt in the AHB Config -+ * register. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ */ -+void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * core_if) -+{ -+ gahbcfg_data_t ahbcfg = {.d32 = 0 }; -+ ahbcfg.b.glblintrmsk = 1; /* Disable interrupts */ -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0); -+} -+ -+/** -+ * This function initializes the commmon interrupts, used in both -+ * device and host modes. -+ * -+ * @param core_if Programming view of the DWC_otg controller -+ * -+ */ -+static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t * core_if) -+{ -+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; -+ gintmsk_data_t intr_mask = {.d32 = 0 }; -+ -+ /* Clear any pending OTG Interrupts */ -+ DWC_WRITE_REG32(&global_regs->gotgint, 0xFFFFFFFF); -+ -+ /* Clear any pending interrupts */ -+ DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF); -+ -+ /* -+ * Enable the interrupts in the GINTMSK. -+ */ -+ intr_mask.b.modemismatch = 1; -+ intr_mask.b.otgintr = 1; -+ -+ if (!core_if->dma_enable) { -+ intr_mask.b.rxstsqlvl = 1; -+ } -+ -+ intr_mask.b.conidstschng = 1; -+ intr_mask.b.wkupintr = 1; -+ intr_mask.b.disconnect = 0; -+ intr_mask.b.usbsuspend = 1; -+ intr_mask.b.sessreqintr = 1; -+#ifdef CONFIG_USB_DWC_OTG_LPM -+ if (core_if->core_params->lpm_enable) { -+ intr_mask.b.lpmtranrcvd = 1; -+ } -+#endif -+ DWC_WRITE_REG32(&global_regs->gintmsk, intr_mask.d32); -+} -+ -+/* -+ * The restore operation is modified to support Synopsys Emulated Powerdown and -+ * Hibernation. This function is for exiting from Device mode hibernation by -+ * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup. -+ * @param core_if Programming view of DWC_otg controller. -+ * @param rem_wakeup - indicates whether resume is initiated by Device or Host. -+ * @param reset - indicates whether resume is initiated by Reset. -+ */ -+int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if, -+ int rem_wakeup, int reset) -+{ -+ gpwrdn_data_t gpwrdn = {.d32 = 0 }; -+ pcgcctl_data_t pcgcctl = {.d32 = 0 }; -+ dctl_data_t dctl = {.d32 = 0 }; -+ -+ int timeout = 2000; -+ -+ if (!core_if->hibernation_suspend) { -+ DWC_PRINTF("Already exited from Hibernation\n"); -+ return 1; -+ } -+ -+ DWC_DEBUGPL(DBG_PCD, "%s called\n", __FUNCTION__); -+ /* Switch-on voltage to the core */ -+ gpwrdn.b.pwrdnswtch = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ dwc_udelay(10); -+ -+ /* Reset core */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pwrdnrstn = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ dwc_udelay(10); -+ -+ /* Assert Restore signal */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.restore = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); -+ dwc_udelay(10); -+ -+ /* Disable power clamps */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pwrdnclmp = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ -+ if (rem_wakeup) { -+ dwc_udelay(70); -+ } -+ -+ /* Deassert Reset core */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pwrdnrstn = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); -+ dwc_udelay(10); -+ -+ /* Disable PMU interrupt */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pmuintsel = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ -+ /* Mask interrupts from gpwrdn */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.connect_det_msk = 1; -+ gpwrdn.b.srp_det_msk = 1; -+ gpwrdn.b.disconn_det_msk = 1; -+ gpwrdn.b.rst_det_msk = 1; -+ gpwrdn.b.lnstchng_msk = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ -+ /* Indicates that we are going out from hibernation */ -+ core_if->hibernation_suspend = 0; -+ -+ /* -+ * Set Restore Essential Regs bit in PCGCCTL register, restore_mode = 1 -+ * indicates restore from remote_wakeup -+ */ -+ restore_essential_regs(core_if, rem_wakeup, 0); -+ -+ /* -+ * Wait a little for seeing new value of variable hibernation_suspend if -+ * Restore done interrupt received before polling -+ */ -+ dwc_udelay(10); -+ -+ if (core_if->hibernation_suspend == 0) { -+ /* -+ * Wait For Restore_done Interrupt. This mechanism of polling the -+ * interrupt is introduced to avoid any possible race conditions -+ */ -+ do { -+ gintsts_data_t gintsts; -+ gintsts.d32 = -+ DWC_READ_REG32(&core_if->core_global_regs->gintsts); -+ if (gintsts.b.restoredone) { -+ gintsts.d32 = 0; -+ gintsts.b.restoredone = 1; -+ DWC_WRITE_REG32(&core_if->core_global_regs-> -+ gintsts, gintsts.d32); -+ DWC_PRINTF("Restore Done Interrupt seen\n"); -+ break; -+ } -+ dwc_udelay(10); -+ } while (--timeout); -+ if (!timeout) { -+ DWC_PRINTF("Restore Done interrupt wasn't generated here\n"); -+ } -+ } -+ /* Clear all pending interupts */ -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); -+ -+ /* De-assert Restore */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.restore = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ dwc_udelay(10); -+ -+ if (!rem_wakeup) { -+ pcgcctl.d32 = 0; -+ pcgcctl.b.rstpdwnmodule = 1; -+ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0); -+ } -+ -+ /* Restore GUSBCFG and DCFG */ -+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, -+ core_if->gr_backup->gusbcfg_local); -+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, -+ core_if->dr_backup->dcfg); -+ -+ /* De-assert Wakeup Logic */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pmuactv = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ dwc_udelay(10); -+ -+ if (!rem_wakeup) { -+ /* Set Device programming done bit */ -+ dctl.b.pwronprgdone = 1; -+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32); -+ } else { -+ /* Start Remote Wakeup Signaling */ -+ dctl.d32 = core_if->dr_backup->dctl; -+ dctl.b.rmtwkupsig = 1; -+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32); -+ } -+ -+ dwc_mdelay(2); -+ /* Clear all pending interupts */ -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); -+ -+ /* Restore global registers */ -+ dwc_otg_restore_global_regs(core_if); -+ /* Restore device global registers */ -+ dwc_otg_restore_dev_regs(core_if, rem_wakeup); -+ -+ if (rem_wakeup) { -+ dwc_mdelay(7); -+ dctl.d32 = 0; -+ dctl.b.rmtwkupsig = 1; -+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0); -+ } -+ -+ core_if->hibernation_suspend = 0; -+ /* The core will be in ON STATE */ -+ core_if->lx_state = DWC_OTG_L0; -+ DWC_PRINTF("Hibernation recovery completes here\n"); -+ -+ return 1; -+} -+ -+/* -+ * The restore operation is modified to support Synopsys Emulated Powerdown and -+ * Hibernation. This function is for exiting from Host mode hibernation by -+ * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup. -+ * @param core_if Programming view of DWC_otg controller. -+ * @param rem_wakeup - indicates whether resume is initiated by Device or Host. -+ * @param reset - indicates whether resume is initiated by Reset. -+ */ -+int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if, -+ int rem_wakeup, int reset) -+{ -+ gpwrdn_data_t gpwrdn = {.d32 = 0 }; -+ hprt0_data_t hprt0 = {.d32 = 0 }; -+ -+ int timeout = 2000; -+ -+ DWC_DEBUGPL(DBG_HCD, "%s called\n", __FUNCTION__); -+ /* Switch-on voltage to the core */ -+ gpwrdn.b.pwrdnswtch = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ dwc_udelay(10); -+ -+ /* Reset core */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pwrdnrstn = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ dwc_udelay(10); -+ -+ /* Assert Restore signal */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.restore = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); -+ dwc_udelay(10); -+ -+ /* Disable power clamps */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pwrdnclmp = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ -+ if (!rem_wakeup) { -+ dwc_udelay(50); -+ } -+ -+ /* Deassert Reset core */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pwrdnrstn = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); -+ dwc_udelay(10); -+ -+ /* Disable PMU interrupt */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pmuintsel = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.connect_det_msk = 1; -+ gpwrdn.b.srp_det_msk = 1; -+ gpwrdn.b.disconn_det_msk = 1; -+ gpwrdn.b.rst_det_msk = 1; -+ gpwrdn.b.lnstchng_msk = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ -+ /* Indicates that we are going out from hibernation */ -+ core_if->hibernation_suspend = 0; -+ -+ /* Set Restore Essential Regs bit in PCGCCTL register */ -+ restore_essential_regs(core_if, rem_wakeup, 1); -+ -+ /* Wait a little for seeing new value of variable hibernation_suspend if -+ * Restore done interrupt received before polling */ -+ dwc_udelay(10); -+ -+ if (core_if->hibernation_suspend == 0) { -+ /* Wait For Restore_done Interrupt. This mechanism of polling the -+ * interrupt is introduced to avoid any possible race conditions -+ */ -+ do { -+ gintsts_data_t gintsts; -+ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts); -+ if (gintsts.b.restoredone) { -+ gintsts.d32 = 0; -+ gintsts.b.restoredone = 1; -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); -+ DWC_DEBUGPL(DBG_HCD,"Restore Done Interrupt seen\n"); -+ break; -+ } -+ dwc_udelay(10); -+ } while (--timeout); -+ if (!timeout) { -+ DWC_WARN("Restore Done interrupt wasn't generated\n"); -+ } -+ } -+ -+ /* Set the flag's value to 0 again after receiving restore done interrupt */ -+ core_if->hibernation_suspend = 0; -+ -+ /* This step is not described in functional spec but if not wait for this -+ * delay, mismatch interrupts occurred because just after restore core is -+ * in Device mode(gintsts.curmode == 0) */ -+ dwc_mdelay(100); -+ -+ /* Clear all pending interrupts */ -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); -+ -+ /* De-assert Restore */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.restore = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ dwc_udelay(10); -+ -+ /* Restore GUSBCFG and HCFG */ -+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, -+ core_if->gr_backup->gusbcfg_local); -+ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, -+ core_if->hr_backup->hcfg_local); -+ -+ /* De-assert Wakeup Logic */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pmuactv = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ dwc_udelay(10); -+ -+ /* Start the Resume operation by programming HPRT0 */ -+ hprt0.d32 = core_if->hr_backup->hprt0_local; -+ hprt0.b.prtpwr = 1; -+ hprt0.b.prtena = 0; -+ hprt0.b.prtsusp = 0; -+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); -+ -+ DWC_PRINTF("Resume Starts Now\n"); -+ if (!reset) { // Indicates it is Resume Operation -+ hprt0.d32 = core_if->hr_backup->hprt0_local; -+ hprt0.b.prtres = 1; -+ hprt0.b.prtpwr = 1; -+ hprt0.b.prtena = 0; -+ hprt0.b.prtsusp = 0; -+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); -+ -+ if (!rem_wakeup) -+ hprt0.b.prtres = 0; -+ /* Wait for Resume time and then program HPRT again */ -+ dwc_mdelay(100); -+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); -+ -+ } else { // Indicates it is Reset Operation -+ hprt0.d32 = core_if->hr_backup->hprt0_local; -+ hprt0.b.prtrst = 1; -+ hprt0.b.prtpwr = 1; -+ hprt0.b.prtena = 0; -+ hprt0.b.prtsusp = 0; -+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); -+ /* Wait for Reset time and then program HPRT again */ -+ dwc_mdelay(60); -+ hprt0.b.prtrst = 0; -+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); -+ } -+ /* Clear all interrupt status */ -+ hprt0.d32 = dwc_otg_read_hprt0(core_if); -+ hprt0.b.prtconndet = 1; -+ hprt0.b.prtenchng = 1; -+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); -+ -+ /* Clear all pending interupts */ -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); -+ -+ /* Restore global registers */ -+ dwc_otg_restore_global_regs(core_if); -+ /* Restore host global registers */ -+ dwc_otg_restore_host_regs(core_if, reset); -+ -+ /* The core will be in ON STATE */ -+ core_if->lx_state = DWC_OTG_L0; -+ DWC_PRINTF("Hibernation recovery is complete here\n"); -+ return 0; -+} -+ -+/** Saves some register values into system memory. */ -+int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if) -+{ -+ struct dwc_otg_global_regs_backup *gr; -+ int i; -+ -+ gr = core_if->gr_backup; -+ if (!gr) { -+ gr = DWC_ALLOC(sizeof(*gr)); -+ if (!gr) { -+ return -DWC_E_NO_MEMORY; -+ } -+ core_if->gr_backup = gr; -+ } -+ -+ gr->gotgctl_local = DWC_READ_REG32(&core_if->core_global_regs->gotgctl); -+ gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk); -+ gr->gahbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg); -+ gr->gusbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); -+ gr->grxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz); -+ gr->gnptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz); -+ gr->hptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz); -+#ifdef CONFIG_USB_DWC_OTG_LPM -+ gr->glpmcfg_local = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); -+#endif -+ gr->gi2cctl_local = DWC_READ_REG32(&core_if->core_global_regs->gi2cctl); -+ gr->pcgcctl_local = DWC_READ_REG32(core_if->pcgcctl); -+ gr->gdfifocfg_local = -+ DWC_READ_REG32(&core_if->core_global_regs->gdfifocfg); -+ for (i = 0; i < MAX_EPS_CHANNELS; i++) { -+ gr->dtxfsiz_local[i] = -+ DWC_READ_REG32(&(core_if->core_global_regs->dtxfsiz[i])); -+ } -+ -+ DWC_DEBUGPL(DBG_ANY, "===========Backing Global registers==========\n"); -+ DWC_DEBUGPL(DBG_ANY, "Backed up gotgctl = %08x\n", gr->gotgctl_local); -+ DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk = %08x\n", gr->gintmsk_local); -+ DWC_DEBUGPL(DBG_ANY, "Backed up gahbcfg = %08x\n", gr->gahbcfg_local); -+ DWC_DEBUGPL(DBG_ANY, "Backed up gusbcfg = %08x\n", gr->gusbcfg_local); -+ DWC_DEBUGPL(DBG_ANY, "Backed up grxfsiz = %08x\n", gr->grxfsiz_local); -+ DWC_DEBUGPL(DBG_ANY, "Backed up gnptxfsiz = %08x\n", -+ gr->gnptxfsiz_local); -+ DWC_DEBUGPL(DBG_ANY, "Backed up hptxfsiz = %08x\n", -+ gr->hptxfsiz_local); -+#ifdef CONFIG_USB_DWC_OTG_LPM -+ DWC_DEBUGPL(DBG_ANY, "Backed up glpmcfg = %08x\n", gr->glpmcfg_local); -+#endif -+ DWC_DEBUGPL(DBG_ANY, "Backed up gi2cctl = %08x\n", gr->gi2cctl_local); -+ DWC_DEBUGPL(DBG_ANY, "Backed up pcgcctl = %08x\n", gr->pcgcctl_local); -+ DWC_DEBUGPL(DBG_ANY,"Backed up gdfifocfg = %08x\n",gr->gdfifocfg_local); -+ -+ return 0; -+} -+ -+/** Saves GINTMSK register before setting the msk bits. */ -+int dwc_otg_save_gintmsk_reg(dwc_otg_core_if_t * core_if) -+{ -+ struct dwc_otg_global_regs_backup *gr; -+ -+ gr = core_if->gr_backup; -+ if (!gr) { -+ gr = DWC_ALLOC(sizeof(*gr)); -+ if (!gr) { -+ return -DWC_E_NO_MEMORY; -+ } -+ core_if->gr_backup = gr; -+ } -+ -+ gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk); -+ -+ DWC_DEBUGPL(DBG_ANY,"=============Backing GINTMSK registers============\n"); -+ DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk = %08x\n", gr->gintmsk_local); -+ -+ return 0; -+} -+ -+int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if) -+{ -+ struct dwc_otg_dev_regs_backup *dr; -+ int i; -+ -+ dr = core_if->dr_backup; -+ if (!dr) { -+ dr = DWC_ALLOC(sizeof(*dr)); -+ if (!dr) { -+ return -DWC_E_NO_MEMORY; -+ } -+ core_if->dr_backup = dr; -+ } -+ -+ dr->dcfg = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); -+ dr->dctl = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl); -+ dr->daintmsk = -+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk); -+ dr->diepmsk = -+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->diepmsk); -+ dr->doepmsk = -+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->doepmsk); -+ -+ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) { -+ dr->diepctl[i] = -+ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl); -+ dr->dieptsiz[i] = -+ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz); -+ dr->diepdma[i] = -+ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma); -+ } -+ -+ DWC_DEBUGPL(DBG_ANY, -+ "=============Backing Host registers==============\n"); -+ DWC_DEBUGPL(DBG_ANY, "Backed up dcfg = %08x\n", dr->dcfg); -+ DWC_DEBUGPL(DBG_ANY, "Backed up dctl = %08x\n", dr->dctl); -+ DWC_DEBUGPL(DBG_ANY, "Backed up daintmsk = %08x\n", -+ dr->daintmsk); -+ DWC_DEBUGPL(DBG_ANY, "Backed up diepmsk = %08x\n", dr->diepmsk); -+ DWC_DEBUGPL(DBG_ANY, "Backed up doepmsk = %08x\n", dr->doepmsk); -+ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) { -+ DWC_DEBUGPL(DBG_ANY, "Backed up diepctl[%d] = %08x\n", i, -+ dr->diepctl[i]); -+ DWC_DEBUGPL(DBG_ANY, "Backed up dieptsiz[%d] = %08x\n", -+ i, dr->dieptsiz[i]); -+ DWC_DEBUGPL(DBG_ANY, "Backed up diepdma[%d] = %08x\n", i, -+ dr->diepdma[i]); -+ } -+ -+ return 0; -+} -+ -+int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if) -+{ -+ struct dwc_otg_host_regs_backup *hr; -+ int i; -+ -+ hr = core_if->hr_backup; -+ if (!hr) { -+ hr = DWC_ALLOC(sizeof(*hr)); -+ if (!hr) { -+ return -DWC_E_NO_MEMORY; -+ } -+ core_if->hr_backup = hr; -+ } -+ -+ hr->hcfg_local = -+ DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg); -+ hr->haintmsk_local = -+ DWC_READ_REG32(&core_if->host_if->host_global_regs->haintmsk); -+ for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) { -+ hr->hcintmsk_local[i] = -+ DWC_READ_REG32(&core_if->host_if->hc_regs[i]->hcintmsk); -+ } -+ hr->hprt0_local = DWC_READ_REG32(core_if->host_if->hprt0); -+ hr->hfir_local = -+ DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir); -+ -+ DWC_DEBUGPL(DBG_ANY, -+ "=============Backing Host registers===============\n"); -+ DWC_DEBUGPL(DBG_ANY, "Backed up hcfg = %08x\n", -+ hr->hcfg_local); -+ DWC_DEBUGPL(DBG_ANY, "Backed up haintmsk = %08x\n", hr->haintmsk_local); -+ for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) { -+ DWC_DEBUGPL(DBG_ANY, "Backed up hcintmsk[%02d]=%08x\n", i, -+ hr->hcintmsk_local[i]); -+ } -+ DWC_DEBUGPL(DBG_ANY, "Backed up hprt0 = %08x\n", -+ hr->hprt0_local); -+ DWC_DEBUGPL(DBG_ANY, "Backed up hfir = %08x\n", -+ hr->hfir_local); -+ -+ return 0; -+} -+ -+int dwc_otg_restore_global_regs(dwc_otg_core_if_t *core_if) -+{ -+ struct dwc_otg_global_regs_backup *gr; -+ int i; -+ -+ gr = core_if->gr_backup; -+ if (!gr) { -+ return -DWC_E_INVALID; -+ } -+ -+ DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, gr->gotgctl_local); -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gr->gintmsk_local); -+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gr->gusbcfg_local); -+ DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gr->gahbcfg_local); -+ DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, gr->grxfsiz_local); -+ DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz, -+ gr->gnptxfsiz_local); -+ DWC_WRITE_REG32(&core_if->core_global_regs->hptxfsiz, -+ gr->hptxfsiz_local); -+ DWC_WRITE_REG32(&core_if->core_global_regs->gdfifocfg, -+ gr->gdfifocfg_local); -+ for (i = 0; i < MAX_EPS_CHANNELS; i++) { -+ DWC_WRITE_REG32(&core_if->core_global_regs->dtxfsiz[i], -+ gr->dtxfsiz_local[i]); -+ } -+ -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); -+ DWC_WRITE_REG32(core_if->host_if->hprt0, 0x0000100A); -+ DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, -+ (gr->gahbcfg_local)); -+ return 0; -+} -+ -+int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if, int rem_wakeup) -+{ -+ struct dwc_otg_dev_regs_backup *dr; -+ int i; -+ -+ dr = core_if->dr_backup; -+ -+ if (!dr) { -+ return -DWC_E_INVALID; -+ } -+ -+ if (!rem_wakeup) { -+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, -+ dr->dctl); -+ } -+ -+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, dr->daintmsk); -+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, dr->diepmsk); -+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, dr->doepmsk); -+ -+ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) { -+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz, dr->dieptsiz[i]); -+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma, dr->diepdma[i]); -+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl, dr->diepctl[i]); -+ } -+ -+ return 0; -+} -+ -+int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset) -+{ -+ struct dwc_otg_host_regs_backup *hr; -+ int i; -+ hr = core_if->hr_backup; -+ -+ if (!hr) { -+ return -DWC_E_INVALID; -+ } -+ -+ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hr->hcfg_local); -+ //if (!reset) -+ //{ -+ // DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hr->hfir_local); -+ //} -+ -+ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk, -+ hr->haintmsk_local); -+ for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) { -+ DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk, -+ hr->hcintmsk_local[i]); -+ } -+ -+ return 0; -+} -+ -+int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if) -+{ -+ struct dwc_otg_global_regs_backup *gr; -+ -+ gr = core_if->gr_backup; -+ -+ /* Restore values for LPM and I2C */ -+#ifdef CONFIG_USB_DWC_OTG_LPM -+ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, gr->glpmcfg_local); -+#endif -+ DWC_WRITE_REG32(&core_if->core_global_regs->gi2cctl, gr->gi2cctl_local); -+ -+ return 0; -+} -+ -+int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode, int is_host) -+{ -+ struct dwc_otg_global_regs_backup *gr; -+ pcgcctl_data_t pcgcctl = {.d32 = 0 }; -+ gahbcfg_data_t gahbcfg = {.d32 = 0 }; -+ gusbcfg_data_t gusbcfg = {.d32 = 0 }; -+ gintmsk_data_t gintmsk = {.d32 = 0 }; -+ -+ /* Restore LPM and I2C registers */ -+ restore_lpm_i2c_regs(core_if); -+ -+ /* Set PCGCCTL to 0 */ -+ DWC_WRITE_REG32(core_if->pcgcctl, 0x00000000); -+ -+ gr = core_if->gr_backup; -+ /* Load restore values for [31:14] bits */ -+ DWC_WRITE_REG32(core_if->pcgcctl, -+ ((gr->pcgcctl_local & 0xffffc000) | 0x00020000)); -+ -+ /* Umnask global Interrupt in GAHBCFG and restore it */ -+ gahbcfg.d32 = gr->gahbcfg_local; -+ gahbcfg.b.glblintrmsk = 1; -+ DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gahbcfg.d32); -+ -+ /* Clear all pending interupts */ -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); -+ -+ /* Unmask restore done interrupt */ -+ gintmsk.b.restoredone = 1; -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32); -+ -+ /* Restore GUSBCFG and HCFG/DCFG */ -+ gusbcfg.d32 = core_if->gr_backup->gusbcfg_local; -+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32); -+ -+ if (is_host) { -+ hcfg_data_t hcfg = {.d32 = 0 }; -+ hcfg.d32 = core_if->hr_backup->hcfg_local; -+ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, -+ hcfg.d32); -+ -+ /* Load restore values for [31:14] bits */ -+ pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000; -+ pcgcctl.d32 = gr->pcgcctl_local | 0x00020000; -+ -+ if (rmode) -+ pcgcctl.b.restoremode = 1; -+ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32); -+ dwc_udelay(10); -+ -+ /* Load restore values for [31:14] bits and set EssRegRestored bit */ -+ pcgcctl.d32 = gr->pcgcctl_local | 0xffffc000; -+ pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000; -+ pcgcctl.b.ess_reg_restored = 1; -+ if (rmode) -+ pcgcctl.b.restoremode = 1; -+ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32); -+ } else { -+ dcfg_data_t dcfg = {.d32 = 0 }; -+ dcfg.d32 = core_if->dr_backup->dcfg; -+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32); -+ -+ /* Load restore values for [31:14] bits */ -+ pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000; -+ pcgcctl.d32 = gr->pcgcctl_local | 0x00020000; -+ if (!rmode) { -+ pcgcctl.d32 |= 0x208; -+ } -+ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32); -+ dwc_udelay(10); -+ -+ /* Load restore values for [31:14] bits */ -+ pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000; -+ pcgcctl.d32 = gr->pcgcctl_local | 0x00020000; -+ pcgcctl.b.ess_reg_restored = 1; -+ if (!rmode) -+ pcgcctl.d32 |= 0x208; -+ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32); -+ } -+ -+ return 0; -+} -+ -+/** -+ * Initializes the FSLSPClkSel field of the HCFG register depending on the PHY -+ * type. -+ */ -+static void init_fslspclksel(dwc_otg_core_if_t * core_if) -+{ -+ uint32_t val; -+ hcfg_data_t hcfg; -+ -+ if (((core_if->hwcfg2.b.hs_phy_type == 2) && -+ (core_if->hwcfg2.b.fs_phy_type == 1) && -+ (core_if->core_params->ulpi_fs_ls)) || -+ (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) { -+ /* Full speed PHY */ -+ val = DWC_HCFG_48_MHZ; -+ } else { -+ /* High speed PHY running at full speed or high speed */ -+ val = DWC_HCFG_30_60_MHZ; -+ } -+ -+ DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val); -+ hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg); -+ hcfg.b.fslspclksel = val; -+ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32); -+} -+ -+/** -+ * Initializes the DevSpd field of the DCFG register depending on the PHY type -+ * and the enumeration speed of the device. -+ */ -+static void init_devspd(dwc_otg_core_if_t * core_if) -+{ -+ uint32_t val; -+ dcfg_data_t dcfg; -+ -+ if (((core_if->hwcfg2.b.hs_phy_type == 2) && -+ (core_if->hwcfg2.b.fs_phy_type == 1) && -+ (core_if->core_params->ulpi_fs_ls)) || -+ (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) { -+ /* Full speed PHY */ -+ val = 0x3; -+ } else if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) { -+ /* High speed PHY running at full speed */ -+ val = 0x1; -+ } else { -+ /* High speed PHY running at high speed */ -+ val = 0x0; -+ } -+ -+ DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val); -+ -+ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); -+ dcfg.b.devspd = val; -+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32); -+} -+ -+/** -+ * This function calculates the number of IN EPS -+ * using GHWCFG1 and GHWCFG2 registers values -+ * -+ * @param core_if Programming view of the DWC_otg controller -+ */ -+static uint32_t calc_num_in_eps(dwc_otg_core_if_t * core_if) -+{ -+ uint32_t num_in_eps = 0; -+ uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep; -+ uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 3; -+ uint32_t num_tx_fifos = core_if->hwcfg4.b.num_in_eps; -+ int i; -+ -+ for (i = 0; i < num_eps; ++i) { -+ if (!(hwcfg1 & 0x1)) -+ num_in_eps++; -+ -+ hwcfg1 >>= 2; -+ } -+ -+ if (core_if->hwcfg4.b.ded_fifo_en) { -+ num_in_eps = -+ (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps; -+ } -+ -+ return num_in_eps; -+} -+ -+/** -+ * This function calculates the number of OUT EPS -+ * using GHWCFG1 and GHWCFG2 registers values -+ * -+ * @param core_if Programming view of the DWC_otg controller -+ */ -+static uint32_t calc_num_out_eps(dwc_otg_core_if_t * core_if) -+{ -+ uint32_t num_out_eps = 0; -+ uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep; -+ uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 2; -+ int i; -+ -+ for (i = 0; i < num_eps; ++i) { -+ if (!(hwcfg1 & 0x1)) -+ num_out_eps++; -+ -+ hwcfg1 >>= 2; -+ } -+ return num_out_eps; -+} -+ -+/** -+ * This function initializes the DWC_otg controller registers and -+ * prepares the core for device mode or host mode operation. -+ * -+ * @param core_if Programming view of the DWC_otg controller -+ * -+ */ -+void dwc_otg_core_init(dwc_otg_core_if_t * core_if) -+{ -+ int i = 0; -+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; -+ dwc_otg_dev_if_t *dev_if = core_if->dev_if; -+ gahbcfg_data_t ahbcfg = {.d32 = 0 }; -+ gusbcfg_data_t usbcfg = {.d32 = 0 }; -+ gi2cctl_data_t i2cctl = {.d32 = 0 }; -+ -+ DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p) regs at %p\n", -+ core_if, global_regs); -+ -+ /* Common Initialization */ -+ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg); -+ -+ /* Program the ULPI External VBUS bit if needed */ -+ usbcfg.b.ulpi_ext_vbus_drv = -+ (core_if->core_params->phy_ulpi_ext_vbus == -+ DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0; -+ -+ /* Set external TS Dline pulsing */ -+ usbcfg.b.term_sel_dl_pulse = -+ (core_if->core_params->ts_dline == 1) ? 1 : 0; -+ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32); -+ -+ /* Reset the Controller */ -+ dwc_otg_core_reset(core_if); -+ -+ core_if->adp_enable = core_if->core_params->adp_supp_enable; -+ core_if->power_down = core_if->core_params->power_down; -+ core_if->otg_sts = 0; -+ -+ /* Initialize parameters from Hardware configuration registers. */ -+ dev_if->num_in_eps = calc_num_in_eps(core_if); -+ dev_if->num_out_eps = calc_num_out_eps(core_if); -+ -+ DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n", -+ core_if->hwcfg4.b.num_dev_perio_in_ep); -+ -+ for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) { -+ dev_if->perio_tx_fifo_size[i] = -+ DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16; -+ DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n", -+ i, dev_if->perio_tx_fifo_size[i]); -+ } -+ -+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { -+ dev_if->tx_fifo_size[i] = -+ DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16; -+ DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n", -+ i, dev_if->tx_fifo_size[i]); -+ } -+ -+ core_if->total_fifo_size = core_if->hwcfg3.b.dfifo_depth; -+ core_if->rx_fifo_size = DWC_READ_REG32(&global_regs->grxfsiz); -+ core_if->nperio_tx_fifo_size = -+ DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16; -+ -+ DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", core_if->total_fifo_size); -+ DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", core_if->rx_fifo_size); -+ DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n", -+ core_if->nperio_tx_fifo_size); -+ -+ /* This programming sequence needs to happen in FS mode before any other -+ * programming occurs */ -+ if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) && -+ (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) { -+ /* If FS mode with FS PHY */ -+ -+ /* core_init() is now called on every switch so only call the -+ * following for the first time through. */ -+ if (!core_if->phy_init_done) { -+ core_if->phy_init_done = 1; -+ DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n"); -+ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg); -+ usbcfg.b.physel = 1; -+ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32); -+ -+ /* Reset after a PHY select */ -+ dwc_otg_core_reset(core_if); -+ } -+ -+ /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also -+ * do this on HNP Dev/Host mode switches (done in dev_init and -+ * host_init). */ -+ if (dwc_otg_is_host_mode(core_if)) { -+ init_fslspclksel(core_if); -+ } else { -+ init_devspd(core_if); -+ } -+ -+ if (core_if->core_params->i2c_enable) { -+ DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n"); -+ /* Program GUSBCFG.OtgUtmifsSel to I2C */ -+ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg); -+ usbcfg.b.otgutmifssel = 1; -+ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32); -+ -+ /* Program GI2CCTL.I2CEn */ -+ i2cctl.d32 = DWC_READ_REG32(&global_regs->gi2cctl); -+ i2cctl.b.i2cdevaddr = 1; -+ i2cctl.b.i2cen = 0; -+ DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32); -+ i2cctl.b.i2cen = 1; -+ DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32); -+ } -+ -+ } /* endif speed == DWC_SPEED_PARAM_FULL */ -+ else { -+ /* High speed PHY. */ -+ if (!core_if->phy_init_done) { -+ core_if->phy_init_done = 1; -+ /* HS PHY parameters. These parameters are preserved -+ * during soft reset so only program the first time. Do -+ * a soft reset immediately after setting phyif. */ -+ -+ if (core_if->core_params->phy_type == 2) { -+ /* ULPI interface */ -+ usbcfg.b.ulpi_utmi_sel = 1; -+ usbcfg.b.phyif = 0; -+ usbcfg.b.ddrsel = -+ core_if->core_params->phy_ulpi_ddr; -+ } else if (core_if->core_params->phy_type == 1) { -+ /* UTMI+ interface */ -+ usbcfg.b.ulpi_utmi_sel = 0; -+ if (core_if->core_params->phy_utmi_width == 16) { -+ usbcfg.b.phyif = 1; -+ -+ } else { -+ usbcfg.b.phyif = 0; -+ } -+ } else { -+ DWC_ERROR("FS PHY TYPE\n"); -+ } -+ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32); -+ /* Reset after setting the PHY parameters */ -+ dwc_otg_core_reset(core_if); -+ } -+ } -+ -+ if ((core_if->hwcfg2.b.hs_phy_type == 2) && -+ (core_if->hwcfg2.b.fs_phy_type == 1) && -+ (core_if->core_params->ulpi_fs_ls)) { -+ DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n"); -+ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg); -+ usbcfg.b.ulpi_fsls = 1; -+ usbcfg.b.ulpi_clk_sus_m = 1; -+ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32); -+ } else { -+ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg); -+ usbcfg.b.ulpi_fsls = 0; -+ usbcfg.b.ulpi_clk_sus_m = 0; -+ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32); -+ } -+ -+ /* Program the GAHBCFG Register. */ -+ switch (core_if->hwcfg2.b.architecture) { -+ -+ case DWC_SLAVE_ONLY_ARCH: -+ DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n"); -+ ahbcfg.b.nptxfemplvl_txfemplvl = -+ DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY; -+ ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY; -+ core_if->dma_enable = 0; -+ core_if->dma_desc_enable = 0; -+ break; -+ -+ case DWC_EXT_DMA_ARCH: -+ DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n"); -+ { -+ uint8_t brst_sz = core_if->core_params->dma_burst_size; -+ ahbcfg.b.hburstlen = 0; -+ while (brst_sz > 1) { -+ ahbcfg.b.hburstlen++; -+ brst_sz >>= 1; -+ } -+ } -+ core_if->dma_enable = (core_if->core_params->dma_enable != 0); -+ core_if->dma_desc_enable = -+ (core_if->core_params->dma_desc_enable != 0); -+ break; -+ -+ case DWC_INT_DMA_ARCH: -+ DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n"); -+ /* Old value was DWC_GAHBCFG_INT_DMA_BURST_INCR - done for -+ Host mode ISOC in issue fix - vahrama */ -+ /* Broadcom had altered to (1<<3)|(0<<0) - WRESP=1, max 4 beats */ -+ ahbcfg.b.hburstlen = (1<<3)|(0<<0);//DWC_GAHBCFG_INT_DMA_BURST_INCR4; -+ core_if->dma_enable = (core_if->core_params->dma_enable != 0); -+ core_if->dma_desc_enable = -+ (core_if->core_params->dma_desc_enable != 0); -+ break; -+ -+ } -+ if (core_if->dma_enable) { -+ if (core_if->dma_desc_enable) { -+ DWC_PRINTF("Using Descriptor DMA mode\n"); -+ } else { -+ DWC_PRINTF("Using Buffer DMA mode\n"); -+ -+ } -+ } else { -+ DWC_PRINTF("Using Slave mode\n"); -+ core_if->dma_desc_enable = 0; -+ } -+ -+ if (core_if->core_params->ahb_single) { -+ ahbcfg.b.ahbsingle = 1; -+ } -+ -+ ahbcfg.b.dmaenable = core_if->dma_enable; -+ DWC_WRITE_REG32(&global_regs->gahbcfg, ahbcfg.d32); -+ -+ core_if->en_multiple_tx_fifo = core_if->hwcfg4.b.ded_fifo_en; -+ -+ core_if->pti_enh_enable = core_if->core_params->pti_enable != 0; -+ core_if->multiproc_int_enable = core_if->core_params->mpi_enable; -+ DWC_PRINTF("Periodic Transfer Interrupt Enhancement - %s\n", -+ ((core_if->pti_enh_enable) ? "enabled" : "disabled")); -+ DWC_PRINTF("Multiprocessor Interrupt Enhancement - %s\n", -+ ((core_if->multiproc_int_enable) ? "enabled" : "disabled")); -+ -+ /* -+ * Program the GUSBCFG register. -+ */ -+ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg); -+ -+ switch (core_if->hwcfg2.b.op_mode) { -+ case DWC_MODE_HNP_SRP_CAPABLE: -+ usbcfg.b.hnpcap = (core_if->core_params->otg_cap == -+ DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE); -+ usbcfg.b.srpcap = (core_if->core_params->otg_cap != -+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); -+ break; -+ -+ case DWC_MODE_SRP_ONLY_CAPABLE: -+ usbcfg.b.hnpcap = 0; -+ usbcfg.b.srpcap = (core_if->core_params->otg_cap != -+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); -+ break; -+ -+ case DWC_MODE_NO_HNP_SRP_CAPABLE: -+ usbcfg.b.hnpcap = 0; -+ usbcfg.b.srpcap = 0; -+ break; -+ -+ case DWC_MODE_SRP_CAPABLE_DEVICE: -+ usbcfg.b.hnpcap = 0; -+ usbcfg.b.srpcap = (core_if->core_params->otg_cap != -+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); -+ break; -+ -+ case DWC_MODE_NO_SRP_CAPABLE_DEVICE: -+ usbcfg.b.hnpcap = 0; -+ usbcfg.b.srpcap = 0; -+ break; -+ -+ case DWC_MODE_SRP_CAPABLE_HOST: -+ usbcfg.b.hnpcap = 0; -+ usbcfg.b.srpcap = (core_if->core_params->otg_cap != -+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); -+ break; -+ -+ case DWC_MODE_NO_SRP_CAPABLE_HOST: -+ usbcfg.b.hnpcap = 0; -+ usbcfg.b.srpcap = 0; -+ break; -+ } -+ -+ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32); -+ -+#ifdef CONFIG_USB_DWC_OTG_LPM -+ if (core_if->core_params->lpm_enable) { -+ glpmcfg_data_t lpmcfg = {.d32 = 0 }; -+ -+ /* To enable LPM support set lpm_cap_en bit */ -+ lpmcfg.b.lpm_cap_en = 1; -+ -+ /* Make AppL1Res ACK */ -+ lpmcfg.b.appl_resp = 1; -+ -+ /* Retry 3 times */ -+ lpmcfg.b.retry_count = 3; -+ -+ DWC_MODIFY_REG32(&core_if->core_global_regs->glpmcfg, -+ 0, lpmcfg.d32); -+ -+ } -+#endif -+ if (core_if->core_params->ic_usb_cap) { -+ gusbcfg_data_t gusbcfg = {.d32 = 0 }; -+ gusbcfg.b.ic_usb_cap = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gusbcfg, -+ 0, gusbcfg.d32); -+ } -+ { -+ gotgctl_data_t gotgctl = {.d32 = 0 }; -+ gotgctl.b.otgver = core_if->core_params->otg_ver; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl, 0, -+ gotgctl.d32); -+ /* Set OTG version supported */ -+ core_if->otg_ver = core_if->core_params->otg_ver; -+ DWC_PRINTF("OTG VER PARAM: %d, OTG VER FLAG: %d\n", -+ core_if->core_params->otg_ver, core_if->otg_ver); -+ } -+ -+ -+ /* Enable common interrupts */ -+ dwc_otg_enable_common_interrupts(core_if); -+ -+ /* Do device or host intialization based on mode during PCD -+ * and HCD initialization */ -+ if (dwc_otg_is_host_mode(core_if)) { -+ DWC_DEBUGPL(DBG_ANY, "Host Mode\n"); -+ core_if->op_state = A_HOST; -+ } else { -+ DWC_DEBUGPL(DBG_ANY, "Device Mode\n"); -+ core_if->op_state = B_PERIPHERAL; -+#ifdef DWC_DEVICE_ONLY -+ dwc_otg_core_dev_init(core_if); -+#endif -+ } -+} -+ -+/** -+ * This function enables the Device mode interrupts. -+ * -+ * @param core_if Programming view of DWC_otg controller -+ */ -+void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * core_if) -+{ -+ gintmsk_data_t intr_mask = {.d32 = 0 }; -+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; -+ -+ DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__); -+ -+ /* Disable all interrupts. */ -+ DWC_WRITE_REG32(&global_regs->gintmsk, 0); -+ -+ /* Clear any pending interrupts */ -+ DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF); -+ -+ /* Enable the common interrupts */ -+ dwc_otg_enable_common_interrupts(core_if); -+ -+ /* Enable interrupts */ -+ intr_mask.b.usbreset = 1; -+ intr_mask.b.enumdone = 1; -+ /* Disable Disconnect interrupt in Device mode */ -+ intr_mask.b.disconnect = 0; -+ -+ if (!core_if->multiproc_int_enable) { -+ intr_mask.b.inepintr = 1; -+ intr_mask.b.outepintr = 1; -+ } -+ -+ intr_mask.b.erlysuspend = 1; -+ -+ if (core_if->en_multiple_tx_fifo == 0) { -+ intr_mask.b.epmismatch = 1; -+ } -+ -+ //intr_mask.b.incomplisoout = 1; -+ intr_mask.b.incomplisoin = 1; -+ -+/* Enable the ignore frame number for ISOC xfers - MAS */ -+/* Disable to support high bandwith ISOC transfers - manukz */ -+#if 0 -+#ifdef DWC_UTE_PER_IO -+ if (core_if->dma_enable) { -+ if (core_if->dma_desc_enable) { -+ dctl_data_t dctl1 = {.d32 = 0 }; -+ dctl1.b.ifrmnum = 1; -+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> -+ dctl, 0, dctl1.d32); -+ DWC_DEBUG("----Enabled Ignore frame number (0x%08x)", -+ DWC_READ_REG32(&core_if->dev_if-> -+ dev_global_regs->dctl)); -+ } -+ } -+#endif -+#endif -+#ifdef DWC_EN_ISOC -+ if (core_if->dma_enable) { -+ if (core_if->dma_desc_enable == 0) { -+ if (core_if->pti_enh_enable) { -+ dctl_data_t dctl = {.d32 = 0 }; -+ dctl.b.ifrmnum = 1; -+ DWC_MODIFY_REG32(&core_if-> -+ dev_if->dev_global_regs->dctl, -+ 0, dctl.d32); -+ } else { -+ intr_mask.b.incomplisoin = 1; -+ intr_mask.b.incomplisoout = 1; -+ } -+ } -+ } else { -+ intr_mask.b.incomplisoin = 1; -+ intr_mask.b.incomplisoout = 1; -+ } -+#endif /* DWC_EN_ISOC */ -+ -+ /** @todo NGS: Should this be a module parameter? */ -+#ifdef USE_PERIODIC_EP -+ intr_mask.b.isooutdrop = 1; -+ intr_mask.b.eopframe = 1; -+ intr_mask.b.incomplisoin = 1; -+ intr_mask.b.incomplisoout = 1; -+#endif -+ -+ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32); -+ -+ DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__, -+ DWC_READ_REG32(&global_regs->gintmsk)); -+} -+ -+/** -+ * This function initializes the DWC_otg controller registers for -+ * device mode. -+ * -+ * @param core_if Programming view of DWC_otg controller -+ * -+ */ -+void dwc_otg_core_dev_init(dwc_otg_core_if_t * core_if) -+{ -+ int i; -+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; -+ dwc_otg_dev_if_t *dev_if = core_if->dev_if; -+ dwc_otg_core_params_t *params = core_if->core_params; -+ dcfg_data_t dcfg = {.d32 = 0 }; -+ depctl_data_t diepctl = {.d32 = 0 }; -+ grstctl_t resetctl = {.d32 = 0 }; -+ uint32_t rx_fifo_size; -+ fifosize_data_t nptxfifosize; -+ fifosize_data_t txfifosize; -+ dthrctl_data_t dthrctl; -+ fifosize_data_t ptxfifosize; -+ uint16_t rxfsiz, nptxfsiz; -+ gdfifocfg_data_t gdfifocfg = {.d32 = 0 }; -+ hwcfg3_data_t hwcfg3 = {.d32 = 0 }; -+ -+ /* Restart the Phy Clock */ -+ DWC_WRITE_REG32(core_if->pcgcctl, 0); -+ -+ /* Device configuration register */ -+ init_devspd(core_if); -+ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg); -+ dcfg.b.descdma = (core_if->dma_desc_enable) ? 1 : 0; -+ dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80; -+ /* Enable Device OUT NAK in case of DDMA mode*/ -+ if (core_if->core_params->dev_out_nak) { -+ dcfg.b.endevoutnak = 1; -+ } -+ -+ if (core_if->core_params->cont_on_bna) { -+ dctl_data_t dctl = {.d32 = 0 }; -+ dctl.b.encontonbna = 1; -+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32); -+ } -+ -+ -+ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32); -+ -+ /* Configure data FIFO sizes */ -+ if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) { -+ DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n", -+ core_if->total_fifo_size); -+ DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n", -+ params->dev_rx_fifo_size); -+ DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n", -+ params->dev_nperio_tx_fifo_size); -+ -+ /* Rx FIFO */ -+ DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n", -+ DWC_READ_REG32(&global_regs->grxfsiz)); -+ -+#ifdef DWC_UTE_CFI -+ core_if->pwron_rxfsiz = DWC_READ_REG32(&global_regs->grxfsiz); -+ core_if->init_rxfsiz = params->dev_rx_fifo_size; -+#endif -+ rx_fifo_size = params->dev_rx_fifo_size; -+ DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fifo_size); -+ -+ DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n", -+ DWC_READ_REG32(&global_regs->grxfsiz)); -+ -+ /** Set Periodic Tx FIFO Mask all bits 0 */ -+ core_if->p_tx_msk = 0; -+ -+ /** Set Tx FIFO Mask all bits 0 */ -+ core_if->tx_msk = 0; -+ -+ if (core_if->en_multiple_tx_fifo == 0) { -+ /* Non-periodic Tx FIFO */ -+ DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n", -+ DWC_READ_REG32(&global_regs->gnptxfsiz)); -+ -+ nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size; -+ nptxfifosize.b.startaddr = params->dev_rx_fifo_size; -+ -+ DWC_WRITE_REG32(&global_regs->gnptxfsiz, -+ nptxfifosize.d32); -+ -+ DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n", -+ DWC_READ_REG32(&global_regs->gnptxfsiz)); -+ -+ /**@todo NGS: Fix Periodic FIFO Sizing! */ -+ /* -+ * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15. -+ * Indexes of the FIFO size module parameters in the -+ * dev_perio_tx_fifo_size array and the FIFO size registers in -+ * the dptxfsiz array run from 0 to 14. -+ */ -+ /** @todo Finish debug of this */ -+ ptxfifosize.b.startaddr = -+ nptxfifosize.b.startaddr + nptxfifosize.b.depth; -+ for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) { -+ ptxfifosize.b.depth = -+ params->dev_perio_tx_fifo_size[i]; -+ DWC_DEBUGPL(DBG_CIL, -+ "initial dtxfsiz[%d]=%08x\n", i, -+ DWC_READ_REG32(&global_regs->dtxfsiz -+ [i])); -+ DWC_WRITE_REG32(&global_regs->dtxfsiz[i], -+ ptxfifosize.d32); -+ DWC_DEBUGPL(DBG_CIL, "new dtxfsiz[%d]=%08x\n", -+ i, -+ DWC_READ_REG32(&global_regs->dtxfsiz -+ [i])); -+ ptxfifosize.b.startaddr += ptxfifosize.b.depth; -+ } -+ } else { -+ /* -+ * Tx FIFOs These FIFOs are numbered from 1 to 15. -+ * Indexes of the FIFO size module parameters in the -+ * dev_tx_fifo_size array and the FIFO size registers in -+ * the dtxfsiz array run from 0 to 14. -+ */ -+ -+ /* Non-periodic Tx FIFO */ -+ DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n", -+ DWC_READ_REG32(&global_regs->gnptxfsiz)); -+ -+#ifdef DWC_UTE_CFI -+ core_if->pwron_gnptxfsiz = -+ (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16); -+ core_if->init_gnptxfsiz = -+ params->dev_nperio_tx_fifo_size; -+#endif -+ nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size; -+ nptxfifosize.b.startaddr = params->dev_rx_fifo_size; -+ -+ DWC_WRITE_REG32(&global_regs->gnptxfsiz, -+ nptxfifosize.d32); -+ -+ DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n", -+ DWC_READ_REG32(&global_regs->gnptxfsiz)); -+ -+ txfifosize.b.startaddr = -+ nptxfifosize.b.startaddr + nptxfifosize.b.depth; -+ -+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { -+ -+ txfifosize.b.depth = -+ params->dev_tx_fifo_size[i]; -+ -+ DWC_DEBUGPL(DBG_CIL, -+ "initial dtxfsiz[%d]=%08x\n", -+ i, -+ DWC_READ_REG32(&global_regs->dtxfsiz -+ [i])); -+ -+#ifdef DWC_UTE_CFI -+ core_if->pwron_txfsiz[i] = -+ (DWC_READ_REG32 -+ (&global_regs->dtxfsiz[i]) >> 16); -+ core_if->init_txfsiz[i] = -+ params->dev_tx_fifo_size[i]; -+#endif -+ DWC_WRITE_REG32(&global_regs->dtxfsiz[i], -+ txfifosize.d32); -+ -+ DWC_DEBUGPL(DBG_CIL, -+ "new dtxfsiz[%d]=%08x\n", -+ i, -+ DWC_READ_REG32(&global_regs->dtxfsiz -+ [i])); -+ -+ txfifosize.b.startaddr += txfifosize.b.depth; -+ } -+ if (core_if->snpsid <= OTG_CORE_REV_2_94a) { -+ /* Calculating DFIFOCFG for Device mode to include RxFIFO and NPTXFIFO */ -+ gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg); -+ hwcfg3.d32 = DWC_READ_REG32(&global_regs->ghwcfg3); -+ gdfifocfg.b.gdfifocfg = (DWC_READ_REG32(&global_regs->ghwcfg3) >> 16); -+ DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32); -+ rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff); -+ nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16); -+ gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz; -+ DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32); -+ } -+ } -+ -+ /* Flush the FIFOs */ -+ dwc_otg_flush_tx_fifo(core_if, 0x10); /* all Tx FIFOs */ -+ dwc_otg_flush_rx_fifo(core_if); -+ -+ /* Flush the Learning Queue. */ -+ resetctl.b.intknqflsh = 1; -+ DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32); -+ -+ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) { -+ core_if->start_predict = 0; -+ for (i = 0; i<= core_if->dev_if->num_in_eps; ++i) { -+ core_if->nextep_seq[i] = 0xff; // 0xff - EP not active -+ } -+ core_if->nextep_seq[0] = 0; -+ core_if->first_in_nextep_seq = 0; -+ diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl); -+ diepctl.b.nextep = 0; -+ DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32); -+ -+ /* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */ -+ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg); -+ dcfg.b.epmscnt = 2; -+ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32); -+ -+ DWC_DEBUGPL(DBG_CILV,"%s first_in_nextep_seq= %2d; nextep_seq[]:\n", -+ __func__, core_if->first_in_nextep_seq); -+ for (i=0; i <= core_if->dev_if->num_in_eps; i++) { -+ DWC_DEBUGPL(DBG_CILV, "%2d ", core_if->nextep_seq[i]); -+ } -+ DWC_DEBUGPL(DBG_CILV,"\n"); -+ } -+ -+ /* Clear all pending Device Interrupts */ -+ /** @todo - if the condition needed to be checked -+ * or in any case all pending interrutps should be cleared? -+ */ -+ if (core_if->multiproc_int_enable) { -+ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) { -+ DWC_WRITE_REG32(&dev_if-> -+ dev_global_regs->diepeachintmsk[i], 0); -+ } -+ } -+ -+ for (i = 0; i < core_if->dev_if->num_out_eps; ++i) { -+ DWC_WRITE_REG32(&dev_if-> -+ dev_global_regs->doepeachintmsk[i], 0); -+ } -+ -+ DWC_WRITE_REG32(&dev_if->dev_global_regs->deachint, 0xFFFFFFFF); -+ DWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk, 0); -+ } else { -+ DWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, 0); -+ DWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, 0); -+ DWC_WRITE_REG32(&dev_if->dev_global_regs->daint, 0xFFFFFFFF); -+ DWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk, 0); -+ } -+ -+ for (i = 0; i <= dev_if->num_in_eps; i++) { -+ depctl_data_t depctl; -+ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); -+ if (depctl.b.epena) { -+ depctl.d32 = 0; -+ depctl.b.epdis = 1; -+ depctl.b.snak = 1; -+ } else { -+ depctl.d32 = 0; -+ } -+ -+ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32); -+ -+ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, 0); -+ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, 0); -+ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepint, 0xFF); -+ } -+ -+ for (i = 0; i <= dev_if->num_out_eps; i++) { -+ depctl_data_t depctl; -+ depctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl); -+ if (depctl.b.epena) { -+ dctl_data_t dctl = {.d32 = 0 }; -+ gintmsk_data_t gintsts = {.d32 = 0 }; -+ doepint_data_t doepint = {.d32 = 0 }; -+ dctl.b.sgoutnak = 1; -+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32); -+ do { -+ dwc_udelay(10); -+ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts); -+ } while (!gintsts.b.goutnakeff); -+ gintsts.d32 = 0; -+ gintsts.b.goutnakeff = 1; -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); -+ -+ depctl.d32 = 0; -+ depctl.b.epdis = 1; -+ depctl.b.snak = 1; -+ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->doepctl, depctl.d32); -+ do { -+ dwc_udelay(10); -+ doepint.d32 = DWC_READ_REG32(&core_if->dev_if-> -+ out_ep_regs[i]->doepint); -+ } while (!doepint.b.epdisabled); -+ -+ doepint.b.epdisabled = 1; -+ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->doepint, doepint.d32); -+ -+ dctl.d32 = 0; -+ dctl.b.cgoutnak = 1; -+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32); -+ } else { -+ depctl.d32 = 0; -+ } -+ -+ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, depctl.d32); -+ -+ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doeptsiz, 0); -+ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepdma, 0); -+ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepint, 0xFF); -+ } -+ -+ if (core_if->en_multiple_tx_fifo && core_if->dma_enable) { -+ dev_if->non_iso_tx_thr_en = params->thr_ctl & 0x1; -+ dev_if->iso_tx_thr_en = (params->thr_ctl >> 1) & 0x1; -+ dev_if->rx_thr_en = (params->thr_ctl >> 2) & 0x1; -+ -+ dev_if->rx_thr_length = params->rx_thr_length; -+ dev_if->tx_thr_length = params->tx_thr_length; -+ -+ dev_if->setup_desc_index = 0; -+ -+ dthrctl.d32 = 0; -+ dthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en; -+ dthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en; -+ dthrctl.b.tx_thr_len = dev_if->tx_thr_length; -+ dthrctl.b.rx_thr_en = dev_if->rx_thr_en; -+ dthrctl.b.rx_thr_len = dev_if->rx_thr_length; -+ dthrctl.b.ahb_thr_ratio = params->ahb_thr_ratio; -+ -+ DWC_WRITE_REG32(&dev_if->dev_global_regs->dtknqr3_dthrctl, -+ dthrctl.d32); -+ -+ DWC_DEBUGPL(DBG_CIL, -+ "Non ISO Tx Thr - %d\nISO Tx Thr - %d\nRx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n", -+ dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en, -+ dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len, -+ dthrctl.b.rx_thr_len); -+ -+ } -+ -+ dwc_otg_enable_device_interrupts(core_if); -+ -+ { -+ diepmsk_data_t msk = {.d32 = 0 }; -+ msk.b.txfifoundrn = 1; -+ if (core_if->multiproc_int_enable) { -+ DWC_MODIFY_REG32(&dev_if->dev_global_regs-> -+ diepeachintmsk[0], msk.d32, msk.d32); -+ } else { -+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk, -+ msk.d32, msk.d32); -+ } -+ } -+ -+ if (core_if->multiproc_int_enable) { -+ /* Set NAK on Babble */ -+ dctl_data_t dctl = {.d32 = 0 }; -+ dctl.b.nakonbble = 1; -+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32); -+ } -+ -+ if (core_if->snpsid >= OTG_CORE_REV_2_94a) { -+ dctl_data_t dctl = {.d32 = 0 }; -+ dctl.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dctl); -+ dctl.b.sftdiscon = 0; -+ DWC_WRITE_REG32(&dev_if->dev_global_regs->dctl, dctl.d32); -+ } -+} -+ -+/** -+ * This function enables the Host mode interrupts. -+ * -+ * @param core_if Programming view of DWC_otg controller -+ */ -+void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * core_if) -+{ -+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; -+ gintmsk_data_t intr_mask = {.d32 = 0 }; -+ -+ DWC_DEBUGPL(DBG_CIL, "%s(%p)\n", __func__, core_if); -+ -+ /* Disable all interrupts. */ -+ DWC_WRITE_REG32(&global_regs->gintmsk, 0); -+ -+ /* Clear any pending interrupts. */ -+ DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF); -+ -+ /* Enable the common interrupts */ -+ dwc_otg_enable_common_interrupts(core_if); -+ -+ /* -+ * Enable host mode interrupts without disturbing common -+ * interrupts. -+ */ -+ -+ intr_mask.b.disconnect = 1; -+ intr_mask.b.portintr = 1; -+ intr_mask.b.hcintr = 1; -+ -+ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32); -+} -+ -+/** -+ * This function disables the Host Mode interrupts. -+ * -+ * @param core_if Programming view of DWC_otg controller -+ */ -+void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * core_if) -+{ -+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; -+ gintmsk_data_t intr_mask = {.d32 = 0 }; -+ -+ DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__); -+ -+ /* -+ * Disable host mode interrupts without disturbing common -+ * interrupts. -+ */ -+ intr_mask.b.sofintr = 1; -+ intr_mask.b.portintr = 1; -+ intr_mask.b.hcintr = 1; -+ intr_mask.b.ptxfempty = 1; -+ intr_mask.b.nptxfempty = 1; -+ -+ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, 0); -+} -+ -+/** -+ * This function initializes the DWC_otg controller registers for -+ * host mode. -+ * -+ * This function flushes the Tx and Rx FIFOs and it flushes any entries in the -+ * request queues. Host channels are reset to ensure that they are ready for -+ * performing transfers. -+ * -+ * @param core_if Programming view of DWC_otg controller -+ * -+ */ -+void dwc_otg_core_host_init(dwc_otg_core_if_t * core_if) -+{ -+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; -+ dwc_otg_host_if_t *host_if = core_if->host_if; -+ dwc_otg_core_params_t *params = core_if->core_params; -+ hprt0_data_t hprt0 = {.d32 = 0 }; -+ fifosize_data_t nptxfifosize; -+ fifosize_data_t ptxfifosize; -+ uint16_t rxfsiz, nptxfsiz, hptxfsiz; -+ gdfifocfg_data_t gdfifocfg = {.d32 = 0 }; -+ int i; -+ hcchar_data_t hcchar; -+ hcfg_data_t hcfg; -+ hfir_data_t hfir; -+ dwc_otg_hc_regs_t *hc_regs; -+ int num_channels; -+ gotgctl_data_t gotgctl = {.d32 = 0 }; -+ -+ DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if); -+ -+ /* Restart the Phy Clock */ -+ DWC_WRITE_REG32(core_if->pcgcctl, 0); -+ -+ /* Initialize Host Configuration Register */ -+ init_fslspclksel(core_if); -+ if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) { -+ hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg); -+ hcfg.b.fslssupp = 1; -+ DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32); -+ -+ } -+ -+ /* This bit allows dynamic reloading of the HFIR register -+ * during runtime. This bit needs to be programmed during -+ * initial configuration and its value must not be changed -+ * during runtime.*/ -+ if (core_if->core_params->reload_ctl == 1) { -+ hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir); -+ hfir.b.hfirrldctrl = 1; -+ DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32); -+ } -+ -+ if (core_if->core_params->dma_desc_enable) { -+ uint8_t op_mode = core_if->hwcfg2.b.op_mode; -+ if (! -+ (core_if->hwcfg4.b.desc_dma -+ && (core_if->snpsid >= OTG_CORE_REV_2_90a) -+ && ((op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) -+ || (op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) -+ || (op_mode == -+ DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG) -+ || (op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST) -+ || (op_mode == -+ DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST)))) { -+ -+ DWC_ERROR("Host can't operate in Descriptor DMA mode.\n" -+ "Either core version is below 2.90a or " -+ "GHWCFG2, GHWCFG4 registers' values do not allow Descriptor DMA in host mode.\n" -+ "To run the driver in Buffer DMA host mode set dma_desc_enable " -+ "module parameter to 0.\n"); -+ return; -+ } -+ hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg); -+ hcfg.b.descdma = 1; -+ DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32); -+ } -+ -+ /* Configure data FIFO sizes */ -+ if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) { -+ DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n", -+ core_if->total_fifo_size); -+ DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n", -+ params->host_rx_fifo_size); -+ DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n", -+ params->host_nperio_tx_fifo_size); -+ DWC_DEBUGPL(DBG_CIL, "P Tx FIFO Size=%d\n", -+ params->host_perio_tx_fifo_size); -+ -+ /* Rx FIFO */ -+ DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n", -+ DWC_READ_REG32(&global_regs->grxfsiz)); -+ DWC_WRITE_REG32(&global_regs->grxfsiz, -+ params->host_rx_fifo_size); -+ DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n", -+ DWC_READ_REG32(&global_regs->grxfsiz)); -+ -+ /* Non-periodic Tx FIFO */ -+ DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n", -+ DWC_READ_REG32(&global_regs->gnptxfsiz)); -+ nptxfifosize.b.depth = params->host_nperio_tx_fifo_size; -+ nptxfifosize.b.startaddr = params->host_rx_fifo_size; -+ DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32); -+ DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n", -+ DWC_READ_REG32(&global_regs->gnptxfsiz)); -+ -+ /* Periodic Tx FIFO */ -+ DWC_DEBUGPL(DBG_CIL, "initial hptxfsiz=%08x\n", -+ DWC_READ_REG32(&global_regs->hptxfsiz)); -+ ptxfifosize.b.depth = params->host_perio_tx_fifo_size; -+ ptxfifosize.b.startaddr = -+ nptxfifosize.b.startaddr + nptxfifosize.b.depth; -+ DWC_WRITE_REG32(&global_regs->hptxfsiz, ptxfifosize.d32); -+ DWC_DEBUGPL(DBG_CIL, "new hptxfsiz=%08x\n", -+ DWC_READ_REG32(&global_regs->hptxfsiz)); -+ -+ if (core_if->en_multiple_tx_fifo -+ && core_if->snpsid <= OTG_CORE_REV_2_94a) { -+ /* Global DFIFOCFG calculation for Host mode - include RxFIFO, NPTXFIFO and HPTXFIFO */ -+ gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg); -+ rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff); -+ nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16); -+ hptxfsiz = (DWC_READ_REG32(&global_regs->hptxfsiz) >> 16); -+ gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz + hptxfsiz; -+ DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32); -+ } -+ } -+ -+ /* TODO - check this */ -+ /* Clear Host Set HNP Enable in the OTG Control Register */ -+ gotgctl.b.hstsethnpen = 1; -+ DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0); -+ /* Make sure the FIFOs are flushed. */ -+ dwc_otg_flush_tx_fifo(core_if, 0x10 /* all TX FIFOs */ ); -+ dwc_otg_flush_rx_fifo(core_if); -+ -+ /* Clear Host Set HNP Enable in the OTG Control Register */ -+ gotgctl.b.hstsethnpen = 1; -+ DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0); -+ -+ if (!core_if->core_params->dma_desc_enable) { -+ /* Flush out any leftover queued requests. */ -+ num_channels = core_if->core_params->host_channels; -+ -+ for (i = 0; i < num_channels; i++) { -+ hc_regs = core_if->host_if->hc_regs[i]; -+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); -+ hcchar.b.chen = 0; -+ hcchar.b.chdis = 1; -+ hcchar.b.epdir = 0; -+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); -+ } -+ -+ /* Halt all channels to put them into a known state. */ -+ for (i = 0; i < num_channels; i++) { -+ int count = 0; -+ hc_regs = core_if->host_if->hc_regs[i]; -+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); -+ hcchar.b.chen = 1; -+ hcchar.b.chdis = 1; -+ hcchar.b.epdir = 0; -+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); -+ DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d regs %p\n", __func__, i, hc_regs); -+ do { -+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); -+ if (++count > 1000) { -+ DWC_ERROR -+ ("%s: Unable to clear halt on channel %d (timeout HCCHAR 0x%X @%p)\n", -+ __func__, i, hcchar.d32, &hc_regs->hcchar); -+ break; -+ } -+ dwc_udelay(1); -+ } while (hcchar.b.chen); -+ } -+ } -+ -+ /* Turn on the vbus power. */ -+ DWC_PRINTF("Init: Port Power? op_state=%d\n", core_if->op_state); -+ if (core_if->op_state == A_HOST) { -+ hprt0.d32 = dwc_otg_read_hprt0(core_if); -+ DWC_PRINTF("Init: Power Port (%d)\n", hprt0.b.prtpwr); -+ if (hprt0.b.prtpwr == 0) { -+ hprt0.b.prtpwr = 1; -+ DWC_WRITE_REG32(host_if->hprt0, hprt0.d32); -+ } -+ } -+ -+ dwc_otg_enable_host_interrupts(core_if); -+} -+ -+/** -+ * Prepares a host channel for transferring packets to/from a specific -+ * endpoint. The HCCHARn register is set up with the characteristics specified -+ * in _hc. Host channel interrupts that may need to be serviced while this -+ * transfer is in progress are enabled. -+ * -+ * @param core_if Programming view of DWC_otg controller -+ * @param hc Information needed to initialize the host channel -+ */ -+void dwc_otg_hc_init(dwc_otg_core_if_t * core_if, dwc_hc_t * hc) -+{ -+ hcintmsk_data_t hc_intr_mask; -+ hcchar_data_t hcchar; -+ hcsplt_data_t hcsplt; -+ -+ uint8_t hc_num = hc->hc_num; -+ dwc_otg_host_if_t *host_if = core_if->host_if; -+ dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num]; -+ -+ /* Clear old interrupt conditions for this host channel. */ -+ hc_intr_mask.d32 = 0xFFFFFFFF; -+ hc_intr_mask.b.reserved14_31 = 0; -+ DWC_WRITE_REG32(&hc_regs->hcint, hc_intr_mask.d32); -+ -+ /* Enable channel interrupts required for this transfer. */ -+ hc_intr_mask.d32 = 0; -+ hc_intr_mask.b.chhltd = 1; -+ if (core_if->dma_enable) { -+ /* For Descriptor DMA mode core halts the channel on AHB error. Interrupt is not required */ -+ if (!core_if->dma_desc_enable) -+ hc_intr_mask.b.ahberr = 1; -+ else { -+ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) -+ hc_intr_mask.b.xfercompl = 1; -+ } -+ -+ if (hc->error_state && !hc->do_split && -+ hc->ep_type != DWC_OTG_EP_TYPE_ISOC) { -+ hc_intr_mask.b.ack = 1; -+ if (hc->ep_is_in) { -+ hc_intr_mask.b.datatglerr = 1; -+ if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) { -+ hc_intr_mask.b.nak = 1; -+ } -+ } -+ } -+ } else { -+ switch (hc->ep_type) { -+ case DWC_OTG_EP_TYPE_CONTROL: -+ case DWC_OTG_EP_TYPE_BULK: -+ hc_intr_mask.b.xfercompl = 1; -+ hc_intr_mask.b.stall = 1; -+ hc_intr_mask.b.xacterr = 1; -+ hc_intr_mask.b.datatglerr = 1; -+ if (hc->ep_is_in) { -+ hc_intr_mask.b.bblerr = 1; -+ } else { -+ hc_intr_mask.b.nak = 1; -+ hc_intr_mask.b.nyet = 1; -+ if (hc->do_ping) { -+ hc_intr_mask.b.ack = 1; -+ } -+ } -+ -+ if (hc->do_split) { -+ hc_intr_mask.b.nak = 1; -+ if (hc->complete_split) { -+ hc_intr_mask.b.nyet = 1; -+ } else { -+ hc_intr_mask.b.ack = 1; -+ } -+ } -+ -+ if (hc->error_state) { -+ hc_intr_mask.b.ack = 1; -+ } -+ break; -+ case DWC_OTG_EP_TYPE_INTR: -+ hc_intr_mask.b.xfercompl = 1; -+ hc_intr_mask.b.nak = 1; -+ hc_intr_mask.b.stall = 1; -+ hc_intr_mask.b.xacterr = 1; -+ hc_intr_mask.b.datatglerr = 1; -+ hc_intr_mask.b.frmovrun = 1; -+ -+ if (hc->ep_is_in) { -+ hc_intr_mask.b.bblerr = 1; -+ } -+ if (hc->error_state) { -+ hc_intr_mask.b.ack = 1; -+ } -+ if (hc->do_split) { -+ if (hc->complete_split) { -+ hc_intr_mask.b.nyet = 1; -+ } else { -+ hc_intr_mask.b.ack = 1; -+ } -+ } -+ break; -+ case DWC_OTG_EP_TYPE_ISOC: -+ hc_intr_mask.b.xfercompl = 1; -+ hc_intr_mask.b.frmovrun = 1; -+ hc_intr_mask.b.ack = 1; -+ -+ if (hc->ep_is_in) { -+ hc_intr_mask.b.xacterr = 1; -+ hc_intr_mask.b.bblerr = 1; -+ } -+ break; -+ } -+ } -+ DWC_WRITE_REG32(&hc_regs->hcintmsk, hc_intr_mask.d32); -+ -+ /* -+ * Program the HCCHARn register with the endpoint characteristics for -+ * the current transfer. -+ */ -+ hcchar.d32 = 0; -+ hcchar.b.devaddr = hc->dev_addr; -+ hcchar.b.epnum = hc->ep_num; -+ hcchar.b.epdir = hc->ep_is_in; -+ hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW); -+ hcchar.b.eptype = hc->ep_type; -+ hcchar.b.mps = hc->max_packet; -+ -+ DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32); -+ -+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d, Dev Addr %d, EP #%d\n", -+ __func__, hc->hc_num, hcchar.b.devaddr, hcchar.b.epnum); -+ DWC_DEBUGPL(DBG_HCDV, " Is In %d, Is Low Speed %d, EP Type %d, " -+ "Max Pkt %d, Multi Cnt %d\n", -+ hcchar.b.epdir, hcchar.b.lspddev, hcchar.b.eptype, -+ hcchar.b.mps, hcchar.b.multicnt); -+ -+ /* -+ * Program the HCSPLIT register for SPLITs -+ */ -+ hcsplt.d32 = 0; -+ if (hc->do_split) { -+ DWC_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n", -+ hc->hc_num, -+ hc->complete_split ? "CSPLIT" : "SSPLIT"); -+ hcsplt.b.compsplt = hc->complete_split; -+ hcsplt.b.xactpos = hc->xact_pos; -+ hcsplt.b.hubaddr = hc->hub_addr; -+ hcsplt.b.prtaddr = hc->port_addr; -+ DWC_DEBUGPL(DBG_HCDV, "\t comp split %d\n", hc->complete_split); -+ DWC_DEBUGPL(DBG_HCDV, "\t xact pos %d\n", hc->xact_pos); -+ DWC_DEBUGPL(DBG_HCDV, "\t hub addr %d\n", hc->hub_addr); -+ DWC_DEBUGPL(DBG_HCDV, "\t port addr %d\n", hc->port_addr); -+ DWC_DEBUGPL(DBG_HCDV, "\t is_in %d\n", hc->ep_is_in); -+ DWC_DEBUGPL(DBG_HCDV, "\t Max Pkt: %d\n", hcchar.b.mps); -+ DWC_DEBUGPL(DBG_HCDV, "\t xferlen: %d\n", hc->xfer_len); -+ } -+ DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32); -+ -+} -+ -+/** -+ * Attempts to halt a host channel. This function should only be called in -+ * Slave mode or to abort a transfer in either Slave mode or DMA mode. Under -+ * normal circumstances in DMA mode, the controller halts the channel when the -+ * transfer is complete or a condition occurs that requires application -+ * intervention. -+ * -+ * In slave mode, checks for a free request queue entry, then sets the Channel -+ * Enable and Channel Disable bits of the Host Channel Characteristics -+ * register of the specified channel to intiate the halt. If there is no free -+ * request queue entry, sets only the Channel Disable bit of the HCCHARn -+ * register to flush requests for this channel. In the latter case, sets a -+ * flag to indicate that the host channel needs to be halted when a request -+ * queue slot is open. -+ * -+ * In DMA mode, always sets the Channel Enable and Channel Disable bits of the -+ * HCCHARn register. The controller ensures there is space in the request -+ * queue before submitting the halt request. -+ * -+ * Some time may elapse before the core flushes any posted requests for this -+ * host channel and halts. The Channel Halted interrupt handler completes the -+ * deactivation of the host channel. -+ * -+ * @param core_if Controller register interface. -+ * @param hc Host channel to halt. -+ * @param halt_status Reason for halting the channel. -+ */ -+void dwc_otg_hc_halt(dwc_otg_core_if_t * core_if, -+ dwc_hc_t * hc, dwc_otg_halt_status_e halt_status) -+{ -+ gnptxsts_data_t nptxsts; -+ hptxsts_data_t hptxsts; -+ hcchar_data_t hcchar; -+ dwc_otg_hc_regs_t *hc_regs; -+ dwc_otg_core_global_regs_t *global_regs; -+ dwc_otg_host_global_regs_t *host_global_regs; -+ -+ hc_regs = core_if->host_if->hc_regs[hc->hc_num]; -+ global_regs = core_if->core_global_regs; -+ host_global_regs = core_if->host_if->host_global_regs; -+ -+ DWC_ASSERT(!(halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS), -+ "halt_status = %d\n", halt_status); -+ -+ if (halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE || -+ halt_status == DWC_OTG_HC_XFER_AHB_ERR) { -+ /* -+ * Disable all channel interrupts except Ch Halted. The QTD -+ * and QH state associated with this transfer has been cleared -+ * (in the case of URB_DEQUEUE), so the channel needs to be -+ * shut down carefully to prevent crashes. -+ */ -+ hcintmsk_data_t hcintmsk; -+ hcintmsk.d32 = 0; -+ hcintmsk.b.chhltd = 1; -+ DWC_WRITE_REG32(&hc_regs->hcintmsk, hcintmsk.d32); -+ -+ /* -+ * Make sure no other interrupts besides halt are currently -+ * pending. Handling another interrupt could cause a crash due -+ * to the QTD and QH state. -+ */ -+ DWC_WRITE_REG32(&hc_regs->hcint, ~hcintmsk.d32); -+ -+ /* -+ * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR -+ * even if the channel was already halted for some other -+ * reason. -+ */ -+ hc->halt_status = halt_status; -+ -+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); -+ if (hcchar.b.chen == 0) { -+ /* -+ * The channel is either already halted or it hasn't -+ * started yet. In DMA mode, the transfer may halt if -+ * it finishes normally or a condition occurs that -+ * requires driver intervention. Don't want to halt -+ * the channel again. In either Slave or DMA mode, -+ * it's possible that the transfer has been assigned -+ * to a channel, but not started yet when an URB is -+ * dequeued. Don't want to halt a channel that hasn't -+ * started yet. -+ */ -+ return; -+ } -+ } -+ if (hc->halt_pending) { -+ /* -+ * A halt has already been issued for this channel. This might -+ * happen when a transfer is aborted by a higher level in -+ * the stack. -+ */ -+#ifdef DEBUG -+ DWC_PRINTF -+ ("*** %s: Channel %d, _hc->halt_pending already set ***\n", -+ __func__, hc->hc_num); -+ -+#endif -+ return; -+ } -+ -+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); -+ -+ /* No need to set the bit in DDMA for disabling the channel */ -+ //TODO check it everywhere channel is disabled -+ if (!core_if->core_params->dma_desc_enable) -+ hcchar.b.chen = 1; -+ hcchar.b.chdis = 1; -+ -+ if (!core_if->dma_enable) { -+ /* Check for space in the request queue to issue the halt. */ -+ if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL || -+ hc->ep_type == DWC_OTG_EP_TYPE_BULK) { -+ nptxsts.d32 = DWC_READ_REG32(&global_regs->gnptxsts); -+ if (nptxsts.b.nptxqspcavail == 0) { -+ hcchar.b.chen = 0; -+ } -+ } else { -+ hptxsts.d32 = -+ DWC_READ_REG32(&host_global_regs->hptxsts); -+ if ((hptxsts.b.ptxqspcavail == 0) -+ || (core_if->queuing_high_bandwidth)) { -+ hcchar.b.chen = 0; -+ } -+ } -+ } -+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); -+ -+ hc->halt_status = halt_status; -+ -+ if (hcchar.b.chen) { -+ hc->halt_pending = 1; -+ hc->halt_on_queue = 0; -+ } else { -+ hc->halt_on_queue = 1; -+ } -+ -+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num); -+ DWC_DEBUGPL(DBG_HCDV, " hcchar: 0x%08x\n", hcchar.d32); -+ DWC_DEBUGPL(DBG_HCDV, " halt_pending: %d\n", hc->halt_pending); -+ DWC_DEBUGPL(DBG_HCDV, " halt_on_queue: %d\n", hc->halt_on_queue); -+ DWC_DEBUGPL(DBG_HCDV, " halt_status: %d\n", hc->halt_status); -+ -+ return; -+} -+ -+/** -+ * Clears the transfer state for a host channel. This function is normally -+ * called after a transfer is done and the host channel is being released. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ * @param hc Identifies the host channel to clean up. -+ */ -+void dwc_otg_hc_cleanup(dwc_otg_core_if_t * core_if, dwc_hc_t * hc) -+{ -+ dwc_otg_hc_regs_t *hc_regs; -+ -+ hc->xfer_started = 0; -+ -+ /* -+ * Clear channel interrupt enables and any unhandled channel interrupt -+ * conditions. -+ */ -+ hc_regs = core_if->host_if->hc_regs[hc->hc_num]; -+ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0); -+ DWC_WRITE_REG32(&hc_regs->hcint, 0xFFFFFFFF); -+#ifdef DEBUG -+ DWC_TIMER_CANCEL(core_if->hc_xfer_timer[hc->hc_num]); -+#endif -+} -+ -+/** -+ * Sets the channel property that indicates in which frame a periodic transfer -+ * should occur. This is always set to the _next_ frame. This function has no -+ * effect on non-periodic transfers. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ * @param hc Identifies the host channel to set up and its properties. -+ * @param hcchar Current value of the HCCHAR register for the specified host -+ * channel. -+ */ -+static inline void hc_set_even_odd_frame(dwc_otg_core_if_t * core_if, -+ dwc_hc_t * hc, hcchar_data_t * hcchar) -+{ -+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || -+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { -+ hfnum_data_t hfnum; -+ hfnum.d32 = -+ DWC_READ_REG32(&core_if->host_if->host_global_regs->hfnum); -+ -+ /* 1 if _next_ frame is odd, 0 if it's even */ -+ hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1; -+#ifdef DEBUG -+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR && hc->do_split -+ && !hc->complete_split) { -+ switch (hfnum.b.frnum & 0x7) { -+ case 7: -+ core_if->hfnum_7_samples++; -+ core_if->hfnum_7_frrem_accum += hfnum.b.frrem; -+ break; -+ case 0: -+ core_if->hfnum_0_samples++; -+ core_if->hfnum_0_frrem_accum += hfnum.b.frrem; -+ break; -+ default: -+ core_if->hfnum_other_samples++; -+ core_if->hfnum_other_frrem_accum += -+ hfnum.b.frrem; -+ break; -+ } -+ } -+#endif -+ } -+} -+ -+#ifdef DEBUG -+void hc_xfer_timeout(void *ptr) -+{ -+ hc_xfer_info_t *xfer_info = NULL; -+ int hc_num = 0; -+ -+ if (ptr) -+ xfer_info = (hc_xfer_info_t *) ptr; -+ -+ if (!xfer_info->hc) { -+ DWC_ERROR("xfer_info->hc = %p\n", xfer_info->hc); -+ return; -+ } -+ -+ hc_num = xfer_info->hc->hc_num; -+ DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num); -+ DWC_WARN(" start_hcchar_val 0x%08x\n", -+ xfer_info->core_if->start_hcchar_val[hc_num]); -+} -+#endif -+ -+void ep_xfer_timeout(void *ptr) -+{ -+ ep_xfer_info_t *xfer_info = NULL; -+ int ep_num = 0; -+ dctl_data_t dctl = {.d32 = 0 }; -+ gintsts_data_t gintsts = {.d32 = 0 }; -+ gintmsk_data_t gintmsk = {.d32 = 0 }; -+ -+ if (ptr) -+ xfer_info = (ep_xfer_info_t *) ptr; -+ -+ if (!xfer_info->ep) { -+ DWC_ERROR("xfer_info->ep = %p\n", xfer_info->ep); -+ return; -+ } -+ -+ ep_num = xfer_info->ep->num; -+ DWC_WARN("%s: timeout on endpoit %d\n", __func__, ep_num); -+ /* Put the sate to 2 as it was time outed */ -+ xfer_info->state = 2; -+ -+ dctl.d32 = -+ DWC_READ_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl); -+ gintsts.d32 = -+ DWC_READ_REG32(&xfer_info->core_if->core_global_regs->gintsts); -+ gintmsk.d32 = -+ DWC_READ_REG32(&xfer_info->core_if->core_global_regs->gintmsk); -+ -+ if (!gintmsk.b.goutnakeff) { -+ /* Unmask it */ -+ gintmsk.b.goutnakeff = 1; -+ DWC_WRITE_REG32(&xfer_info->core_if->core_global_regs->gintmsk, -+ gintmsk.d32); -+ -+ } -+ -+ if (!gintsts.b.goutnakeff) { -+ dctl.b.sgoutnak = 1; -+ } -+ DWC_WRITE_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl, -+ dctl.d32); -+ -+} -+ -+void set_pid_isoc(dwc_hc_t * hc) -+{ -+ /* Set up the initial PID for the transfer. */ -+ if (hc->speed == DWC_OTG_EP_SPEED_HIGH) { -+ if (hc->ep_is_in) { -+ if (hc->multi_count == 1) { -+ hc->data_pid_start = DWC_OTG_HC_PID_DATA0; -+ } else if (hc->multi_count == 2) { -+ hc->data_pid_start = DWC_OTG_HC_PID_DATA1; -+ } else { -+ hc->data_pid_start = DWC_OTG_HC_PID_DATA2; -+ } -+ } else { -+ if (hc->multi_count == 1) { -+ hc->data_pid_start = DWC_OTG_HC_PID_DATA0; -+ } else { -+ hc->data_pid_start = DWC_OTG_HC_PID_MDATA; -+ } -+ } -+ } else { -+ hc->data_pid_start = DWC_OTG_HC_PID_DATA0; -+ } -+} -+ -+/** -+ * This function does the setup for a data transfer for a host channel and -+ * starts the transfer. May be called in either Slave mode or DMA mode. In -+ * Slave mode, the caller must ensure that there is sufficient space in the -+ * request queue and Tx Data FIFO. -+ * -+ * For an OUT transfer in Slave mode, it loads a data packet into the -+ * appropriate FIFO. If necessary, additional data packets will be loaded in -+ * the Host ISR. -+ * -+ * For an IN transfer in Slave mode, a data packet is requested. The data -+ * packets are unloaded from the Rx FIFO in the Host ISR. If necessary, -+ * additional data packets are requested in the Host ISR. -+ * -+ * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ -+ * register along with a packet count of 1 and the channel is enabled. This -+ * causes a single PING transaction to occur. Other fields in HCTSIZ are -+ * simply set to 0 since no data transfer occurs in this case. -+ * -+ * For a PING transfer in DMA mode, the HCTSIZ register is initialized with -+ * all the information required to perform the subsequent data transfer. In -+ * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the -+ * controller performs the entire PING protocol, then starts the data -+ * transfer. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ * @param hc Information needed to initialize the host channel. The xfer_len -+ * value may be reduced to accommodate the max widths of the XferSize and -+ * PktCnt fields in the HCTSIZn register. The multi_count value may be changed -+ * to reflect the final xfer_len value. -+ */ -+void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc) -+{ -+ hcchar_data_t hcchar; -+ hctsiz_data_t hctsiz; -+ uint16_t num_packets; -+ uint32_t max_hc_xfer_size = core_if->core_params->max_transfer_size; -+ uint16_t max_hc_pkt_count = core_if->core_params->max_packet_count; -+ dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num]; -+ -+ hctsiz.d32 = 0; -+ -+ if (hc->do_ping) { -+ if (!core_if->dma_enable) { -+ dwc_otg_hc_do_ping(core_if, hc); -+ hc->xfer_started = 1; -+ return; -+ } else { -+ hctsiz.b.dopng = 1; -+ } -+ } -+ -+ if (hc->do_split) { -+ num_packets = 1; -+ -+ if (hc->complete_split && !hc->ep_is_in) { -+ /* For CSPLIT OUT Transfer, set the size to 0 so the -+ * core doesn't expect any data written to the FIFO */ -+ hc->xfer_len = 0; -+ } else if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) { -+ hc->xfer_len = hc->max_packet; -+ } else if (!hc->ep_is_in && (hc->xfer_len > 188)) { -+ hc->xfer_len = 188; -+ } -+ -+ hctsiz.b.xfersize = hc->xfer_len; -+ } else { -+ /* -+ * Ensure that the transfer length and packet count will fit -+ * in the widths allocated for them in the HCTSIZn register. -+ */ -+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || -+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { -+ /* -+ * Make sure the transfer size is no larger than one -+ * (micro)frame's worth of data. (A check was done -+ * when the periodic transfer was accepted to ensure -+ * that a (micro)frame's worth of data can be -+ * programmed into a channel.) -+ */ -+ uint32_t max_periodic_len = -+ hc->multi_count * hc->max_packet; -+ if (hc->xfer_len > max_periodic_len) { -+ hc->xfer_len = max_periodic_len; -+ } else { -+ } -+ } else if (hc->xfer_len > max_hc_xfer_size) { -+ /* Make sure that xfer_len is a multiple of max packet size. */ -+ hc->xfer_len = max_hc_xfer_size - hc->max_packet + 1; -+ } -+ -+ if (hc->xfer_len > 0) { -+ num_packets = -+ (hc->xfer_len + hc->max_packet - -+ 1) / hc->max_packet; -+ if (num_packets > max_hc_pkt_count) { -+ num_packets = max_hc_pkt_count; -+ hc->xfer_len = num_packets * hc->max_packet; -+ } -+ } else { -+ /* Need 1 packet for transfer length of 0. */ -+ num_packets = 1; -+ } -+ -+ if (hc->ep_is_in) { -+ /* Always program an integral # of max packets for IN transfers. */ -+ hc->xfer_len = num_packets * hc->max_packet; -+ } -+ -+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || -+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { -+ /* -+ * Make sure that the multi_count field matches the -+ * actual transfer length. -+ */ -+ hc->multi_count = num_packets; -+ } -+ -+ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) -+ set_pid_isoc(hc); -+ -+ hctsiz.b.xfersize = hc->xfer_len; -+ } -+ -+ hc->start_pkt_count = num_packets; -+ hctsiz.b.pktcnt = num_packets; -+ hctsiz.b.pid = hc->data_pid_start; -+ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32); -+ -+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num); -+ DWC_DEBUGPL(DBG_HCDV, " Xfer Size: %d\n", hctsiz.b.xfersize); -+ DWC_DEBUGPL(DBG_HCDV, " Num Pkts: %d\n", hctsiz.b.pktcnt); -+ DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid); -+ -+ if (core_if->dma_enable) { -+ dwc_dma_t dma_addr; -+ if (hc->align_buff) { -+ dma_addr = hc->align_buff; -+ } else { -+ dma_addr = ((unsigned long)hc->xfer_buff & 0xffffffff); -+ } -+ DWC_WRITE_REG32(&hc_regs->hcdma, dma_addr); -+ } -+ -+ /* Start the split */ -+ if (hc->do_split) { -+ hcsplt_data_t hcsplt; -+ hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt); -+ hcsplt.b.spltena = 1; -+ DWC_WRITE_REG32(&hc_regs->hcsplt, hcsplt.d32); -+ } -+ -+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); -+ hcchar.b.multicnt = hc->multi_count; -+ hc_set_even_odd_frame(core_if, hc, &hcchar); -+#ifdef DEBUG -+ core_if->start_hcchar_val[hc->hc_num] = hcchar.d32; -+ if (hcchar.b.chdis) { -+ DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n", -+ __func__, hc->hc_num, hcchar.d32); -+ } -+#endif -+ -+ /* Set host channel enable after all other setup is complete. */ -+ hcchar.b.chen = 1; -+ hcchar.b.chdis = 0; -+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); -+ -+ hc->xfer_started = 1; -+ hc->requests++; -+ -+ if (!core_if->dma_enable && !hc->ep_is_in && hc->xfer_len > 0) { -+ /* Load OUT packet into the appropriate Tx FIFO. */ -+ dwc_otg_hc_write_packet(core_if, hc); -+ } -+#ifdef DEBUG -+ if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) { -+ DWC_DEBUGPL(DBG_HCDV, "transfer %d from core_if %p\n", -+ hc->hc_num, core_if);//GRAYG -+ core_if->hc_xfer_info[hc->hc_num].core_if = core_if; -+ core_if->hc_xfer_info[hc->hc_num].hc = hc; -+ -+ /* Start a timer for this transfer. */ -+ DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000); -+ } -+#endif -+} -+ -+/** -+ * This function does the setup for a data transfer for a host channel -+ * and starts the transfer in Descriptor DMA mode. -+ * -+ * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set. -+ * Sets PID and NTD values. For periodic transfers -+ * initializes SCHED_INFO field with micro-frame bitmap. -+ * -+ * Initializes HCDMA register with descriptor list address and CTD value -+ * then starts the transfer via enabling the channel. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ * @param hc Information needed to initialize the host channel. -+ */ -+void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if, dwc_hc_t * hc) -+{ -+ dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num]; -+ hcchar_data_t hcchar; -+ hctsiz_data_t hctsiz; -+ hcdma_data_t hcdma; -+ -+ hctsiz.d32 = 0; -+ -+ if (hc->do_ping) -+ hctsiz.b_ddma.dopng = 1; -+ -+ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) -+ set_pid_isoc(hc); -+ -+ /* Packet Count and Xfer Size are not used in Descriptor DMA mode */ -+ hctsiz.b_ddma.pid = hc->data_pid_start; -+ hctsiz.b_ddma.ntd = hc->ntd - 1; /* 0 - 1 descriptor, 1 - 2 descriptors, etc. */ -+ hctsiz.b_ddma.schinfo = hc->schinfo; /* Non-zero only for high-speed interrupt endpoints */ -+ -+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num); -+ DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid); -+ DWC_DEBUGPL(DBG_HCDV, " NTD: %d\n", hctsiz.b_ddma.ntd); -+ -+ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32); -+ -+ hcdma.d32 = 0; -+ hcdma.b.dma_addr = ((uint32_t) hc->desc_list_addr) >> 11; -+ -+ /* Always start from first descriptor. */ -+ hcdma.b.ctd = 0; -+ DWC_WRITE_REG32(&hc_regs->hcdma, hcdma.d32); -+ -+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); -+ hcchar.b.multicnt = hc->multi_count; -+ -+#ifdef DEBUG -+ core_if->start_hcchar_val[hc->hc_num] = hcchar.d32; -+ if (hcchar.b.chdis) { -+ DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n", -+ __func__, hc->hc_num, hcchar.d32); -+ } -+#endif -+ -+ /* Set host channel enable after all other setup is complete. */ -+ hcchar.b.chen = 1; -+ hcchar.b.chdis = 0; -+ -+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); -+ -+ hc->xfer_started = 1; -+ hc->requests++; -+ -+#ifdef DEBUG -+ if ((hc->ep_type != DWC_OTG_EP_TYPE_INTR) -+ && (hc->ep_type != DWC_OTG_EP_TYPE_ISOC)) { -+ DWC_DEBUGPL(DBG_HCDV, "DMA transfer %d from core_if %p\n", -+ hc->hc_num, core_if);//GRAYG -+ core_if->hc_xfer_info[hc->hc_num].core_if = core_if; -+ core_if->hc_xfer_info[hc->hc_num].hc = hc; -+ /* Start a timer for this transfer. */ -+ DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000); -+ } -+#endif -+ -+} -+ -+/** -+ * This function continues a data transfer that was started by previous call -+ * to dwc_otg_hc_start_transfer. The caller must ensure there is -+ * sufficient space in the request queue and Tx Data FIFO. This function -+ * should only be called in Slave mode. In DMA mode, the controller acts -+ * autonomously to complete transfers programmed to a host channel. -+ * -+ * For an OUT transfer, a new data packet is loaded into the appropriate FIFO -+ * if there is any data remaining to be queued. For an IN transfer, another -+ * data packet is always requested. For the SETUP phase of a control transfer, -+ * this function does nothing. -+ * -+ * @return 1 if a new request is queued, 0 if no more requests are required -+ * for this transfer. -+ */ -+int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc) -+{ -+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num); -+ -+ if (hc->do_split) { -+ /* SPLITs always queue just once per channel */ -+ return 0; -+ } else if (hc->data_pid_start == DWC_OTG_HC_PID_SETUP) { -+ /* SETUPs are queued only once since they can't be NAKed. */ -+ return 0; -+ } else if (hc->ep_is_in) { -+ /* -+ * Always queue another request for other IN transfers. If -+ * back-to-back INs are issued and NAKs are received for both, -+ * the driver may still be processing the first NAK when the -+ * second NAK is received. When the interrupt handler clears -+ * the NAK interrupt for the first NAK, the second NAK will -+ * not be seen. So we can't depend on the NAK interrupt -+ * handler to requeue a NAKed request. Instead, IN requests -+ * are issued each time this function is called. When the -+ * transfer completes, the extra requests for the channel will -+ * be flushed. -+ */ -+ hcchar_data_t hcchar; -+ dwc_otg_hc_regs_t *hc_regs = -+ core_if->host_if->hc_regs[hc->hc_num]; -+ -+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); -+ hc_set_even_odd_frame(core_if, hc, &hcchar); -+ hcchar.b.chen = 1; -+ hcchar.b.chdis = 0; -+ DWC_DEBUGPL(DBG_HCDV, " IN xfer: hcchar = 0x%08x\n", -+ hcchar.d32); -+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); -+ hc->requests++; -+ return 1; -+ } else { -+ /* OUT transfers. */ -+ if (hc->xfer_count < hc->xfer_len) { -+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || -+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { -+ hcchar_data_t hcchar; -+ dwc_otg_hc_regs_t *hc_regs; -+ hc_regs = core_if->host_if->hc_regs[hc->hc_num]; -+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); -+ hc_set_even_odd_frame(core_if, hc, &hcchar); -+ } -+ -+ /* Load OUT packet into the appropriate Tx FIFO. */ -+ dwc_otg_hc_write_packet(core_if, hc); -+ hc->requests++; -+ return 1; -+ } else { -+ return 0; -+ } -+ } -+} -+ -+/** -+ * Starts a PING transfer. This function should only be called in Slave mode. -+ * The Do Ping bit is set in the HCTSIZ register, then the channel is enabled. -+ */ -+void dwc_otg_hc_do_ping(dwc_otg_core_if_t * core_if, dwc_hc_t * hc) -+{ -+ hcchar_data_t hcchar; -+ hctsiz_data_t hctsiz; -+ dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num]; -+ -+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num); -+ -+ hctsiz.d32 = 0; -+ hctsiz.b.dopng = 1; -+ hctsiz.b.pktcnt = 1; -+ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32); -+ -+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); -+ hcchar.b.chen = 1; -+ hcchar.b.chdis = 0; -+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); -+} -+ -+/* -+ * This function writes a packet into the Tx FIFO associated with the Host -+ * Channel. For a channel associated with a non-periodic EP, the non-periodic -+ * Tx FIFO is written. For a channel associated with a periodic EP, the -+ * periodic Tx FIFO is written. This function should only be called in Slave -+ * mode. -+ * -+ * Upon return the xfer_buff and xfer_count fields in _hc are incremented by -+ * then number of bytes written to the Tx FIFO. -+ */ -+void dwc_otg_hc_write_packet(dwc_otg_core_if_t * core_if, dwc_hc_t * hc) -+{ -+ uint32_t i; -+ uint32_t remaining_count; -+ uint32_t byte_count; -+ uint32_t dword_count; -+ -+ uint32_t *data_buff = (uint32_t *) (hc->xfer_buff); -+ uint32_t *data_fifo = core_if->data_fifo[hc->hc_num]; -+ -+ remaining_count = hc->xfer_len - hc->xfer_count; -+ if (remaining_count > hc->max_packet) { -+ byte_count = hc->max_packet; -+ } else { -+ byte_count = remaining_count; -+ } -+ -+ dword_count = (byte_count + 3) / 4; -+ -+ if ((((unsigned long)data_buff) & 0x3) == 0) { -+ /* xfer_buff is DWORD aligned. */ -+ for (i = 0; i < dword_count; i++, data_buff++) { -+ DWC_WRITE_REG32(data_fifo, *data_buff); -+ } -+ } else { -+ /* xfer_buff is not DWORD aligned. */ -+ for (i = 0; i < dword_count; i++, data_buff++) { -+ uint32_t data; -+ data = -+ (data_buff[0] | data_buff[1] << 8 | data_buff[2] << -+ 16 | data_buff[3] << 24); -+ DWC_WRITE_REG32(data_fifo, data); -+ } -+ } -+ -+ hc->xfer_count += byte_count; -+ hc->xfer_buff += byte_count; -+} -+ -+/** -+ * Gets the current USB frame number. This is the frame number from the last -+ * SOF packet. -+ */ -+uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * core_if) -+{ -+ dsts_data_t dsts; -+ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); -+ -+ /* read current frame/microframe number from DSTS register */ -+ return dsts.b.soffn; -+} -+ -+/** -+ * Calculates and gets the frame Interval value of HFIR register according PHY -+ * type and speed.The application can modify a value of HFIR register only after -+ * the Port Enable bit of the Host Port Control and Status register -+ * (HPRT.PrtEnaPort) has been set. -+*/ -+ -+uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if) -+{ -+ gusbcfg_data_t usbcfg; -+ hwcfg2_data_t hwcfg2; -+ hprt0_data_t hprt0; -+ int clock = 60; // default value -+ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); -+ hwcfg2.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2); -+ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0); -+ if (!usbcfg.b.physel && usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif) -+ clock = 60; -+ if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 3) -+ clock = 48; -+ if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel && -+ !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif) -+ clock = 30; -+ if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel && -+ !usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif) -+ clock = 60; -+ if (usbcfg.b.phylpwrclksel && !usbcfg.b.physel && -+ !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif) -+ clock = 48; -+ if (usbcfg.b.physel && !usbcfg.b.phyif && hwcfg2.b.fs_phy_type == 2) -+ clock = 48; -+ if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 1) -+ clock = 48; -+ if (hprt0.b.prtspd == 0) -+ /* High speed case */ -+ return 125 * clock; -+ else -+ /* FS/LS case */ -+ return 1000 * clock; -+} -+ -+/** -+ * This function reads a setup packet from the Rx FIFO into the destination -+ * buffer. This function is called from the Rx Status Queue Level (RxStsQLvl) -+ * Interrupt routine when a SETUP packet has been received in Slave mode. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ * @param dest Destination buffer for packet data. -+ */ -+void dwc_otg_read_setup_packet(dwc_otg_core_if_t * core_if, uint32_t * dest) -+{ -+ device_grxsts_data_t status; -+ /* Get the 8 bytes of a setup transaction data */ -+ -+ /* Pop 2 DWORDS off the receive data FIFO into memory */ -+ dest[0] = DWC_READ_REG32(core_if->data_fifo[0]); -+ dest[1] = DWC_READ_REG32(core_if->data_fifo[0]); -+ if (core_if->snpsid >= OTG_CORE_REV_3_00a) { -+ status.d32 = -+ DWC_READ_REG32(&core_if->core_global_regs->grxstsp); -+ DWC_DEBUGPL(DBG_ANY, -+ "EP:%d BCnt:%d " "pktsts:%x Frame:%d(0x%0x)\n", -+ status.b.epnum, status.b.bcnt, status.b.pktsts, -+ status.b.fn, status.b.fn); -+ } -+} -+ -+/** -+ * This function enables EP0 OUT to receive SETUP packets and configures EP0 -+ * IN for transmitting packets. It is normally called when the -+ * "Enumeration Done" interrupt occurs. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ * @param ep The EP0 data. -+ */ -+void dwc_otg_ep0_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) -+{ -+ dwc_otg_dev_if_t *dev_if = core_if->dev_if; -+ dsts_data_t dsts; -+ depctl_data_t diepctl; -+ depctl_data_t doepctl; -+ dctl_data_t dctl = {.d32 = 0 }; -+ -+ ep->stp_rollover = 0; -+ /* Read the Device Status and Endpoint 0 Control registers */ -+ dsts.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dsts); -+ diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl); -+ doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl); -+ -+ /* Set the MPS of the IN EP based on the enumeration speed */ -+ switch (dsts.b.enumspd) { -+ case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: -+ case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: -+ case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ: -+ diepctl.b.mps = DWC_DEP0CTL_MPS_64; -+ break; -+ case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ: -+ diepctl.b.mps = DWC_DEP0CTL_MPS_8; -+ break; -+ } -+ -+ DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32); -+ -+ /* Enable OUT EP for receive */ -+ if (core_if->snpsid <= OTG_CORE_REV_2_94a) { -+ doepctl.b.epena = 1; -+ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32); -+ } -+#ifdef VERBOSE -+ DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n", -+ DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl)); -+ DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n", -+ DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl)); -+#endif -+ dctl.b.cgnpinnak = 1; -+ -+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); -+ DWC_DEBUGPL(DBG_PCDV, "dctl=%0x\n", -+ DWC_READ_REG32(&dev_if->dev_global_regs->dctl)); -+ -+} -+ -+/** -+ * This function activates an EP. The Device EP control register for -+ * the EP is configured as defined in the ep structure. Note: This -+ * function is not used for EP0. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ * @param ep The EP to activate. -+ */ -+void dwc_otg_ep_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) -+{ -+ dwc_otg_dev_if_t *dev_if = core_if->dev_if; -+ depctl_data_t depctl; -+ volatile uint32_t *addr; -+ daint_data_t daintmsk = {.d32 = 0 }; -+ dcfg_data_t dcfg; -+ uint8_t i; -+ -+ DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, ep->num, -+ (ep->is_in ? "IN" : "OUT")); -+ -+#ifdef DWC_UTE_PER_IO -+ ep->xiso_frame_num = 0xFFFFFFFF; -+ ep->xiso_active_xfers = 0; -+ ep->xiso_queued_xfers = 0; -+#endif -+ /* Read DEPCTLn register */ -+ if (ep->is_in == 1) { -+ addr = &dev_if->in_ep_regs[ep->num]->diepctl; -+ daintmsk.ep.in = 1 << ep->num; -+ } else { -+ addr = &dev_if->out_ep_regs[ep->num]->doepctl; -+ daintmsk.ep.out = 1 << ep->num; -+ } -+ -+ /* If the EP is already active don't change the EP Control -+ * register. */ -+ depctl.d32 = DWC_READ_REG32(addr); -+ if (!depctl.b.usbactep) { -+ depctl.b.mps = ep->maxpacket; -+ depctl.b.eptype = ep->type; -+ depctl.b.txfnum = ep->tx_fifo_num; -+ -+ if (ep->type == DWC_OTG_EP_TYPE_ISOC) { -+ depctl.b.setd0pid = 1; // ??? -+ } else { -+ depctl.b.setd0pid = 1; -+ } -+ depctl.b.usbactep = 1; -+ -+ /* Update nextep_seq array and EPMSCNT in DCFG*/ -+ if (!(depctl.b.eptype & 1) && (ep->is_in == 1)) { // NP IN EP -+ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) { -+ if (core_if->nextep_seq[i] == core_if->first_in_nextep_seq) -+ break; -+ } -+ core_if->nextep_seq[i] = ep->num; -+ core_if->nextep_seq[ep->num] = core_if->first_in_nextep_seq; -+ depctl.b.nextep = core_if->nextep_seq[ep->num]; -+ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg); -+ dcfg.b.epmscnt++; -+ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32); -+ -+ DWC_DEBUGPL(DBG_PCDV, -+ "%s first_in_nextep_seq= %2d; nextep_seq[]:\n", -+ __func__, core_if->first_in_nextep_seq); -+ for (i=0; i <= core_if->dev_if->num_in_eps; i++) { -+ DWC_DEBUGPL(DBG_PCDV, "%2d\n", -+ core_if->nextep_seq[i]); -+ } -+ -+ } -+ -+ -+ DWC_WRITE_REG32(addr, depctl.d32); -+ DWC_DEBUGPL(DBG_PCDV, "DEPCTL=%08x\n", DWC_READ_REG32(addr)); -+ } -+ -+ /* Enable the Interrupt for this EP */ -+ if (core_if->multiproc_int_enable) { -+ if (ep->is_in == 1) { -+ diepmsk_data_t diepmsk = {.d32 = 0 }; -+ diepmsk.b.xfercompl = 1; -+ diepmsk.b.timeout = 1; -+ diepmsk.b.epdisabled = 1; -+ diepmsk.b.ahberr = 1; -+ diepmsk.b.intknepmis = 1; -+ if (!core_if->en_multiple_tx_fifo && core_if->dma_enable) -+ diepmsk.b.intknepmis = 0; -+ diepmsk.b.txfifoundrn = 1; //????? -+ if (ep->type == DWC_OTG_EP_TYPE_ISOC) { -+ diepmsk.b.nak = 1; -+ } -+ -+ -+ -+/* -+ if (core_if->dma_desc_enable) { -+ diepmsk.b.bna = 1; -+ } -+*/ -+/* -+ if (core_if->dma_enable) { -+ doepmsk.b.nak = 1; -+ } -+*/ -+ DWC_WRITE_REG32(&dev_if->dev_global_regs-> -+ diepeachintmsk[ep->num], diepmsk.d32); -+ -+ } else { -+ doepmsk_data_t doepmsk = {.d32 = 0 }; -+ doepmsk.b.xfercompl = 1; -+ doepmsk.b.ahberr = 1; -+ doepmsk.b.epdisabled = 1; -+ if (ep->type == DWC_OTG_EP_TYPE_ISOC) -+ doepmsk.b.outtknepdis = 1; -+ -+/* -+ -+ if (core_if->dma_desc_enable) { -+ doepmsk.b.bna = 1; -+ } -+*/ -+/* -+ doepmsk.b.babble = 1; -+ doepmsk.b.nyet = 1; -+ doepmsk.b.nak = 1; -+*/ -+ DWC_WRITE_REG32(&dev_if->dev_global_regs-> -+ doepeachintmsk[ep->num], doepmsk.d32); -+ } -+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->deachintmsk, -+ 0, daintmsk.d32); -+ } else { -+ if (ep->type == DWC_OTG_EP_TYPE_ISOC) { -+ if (ep->is_in) { -+ diepmsk_data_t diepmsk = {.d32 = 0 }; -+ diepmsk.b.nak = 1; -+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk, 0, diepmsk.d32); -+ } else { -+ doepmsk_data_t doepmsk = {.d32 = 0 }; -+ doepmsk.b.outtknepdis = 1; -+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->doepmsk, 0, doepmsk.d32); -+ } -+ } -+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->daintmsk, -+ 0, daintmsk.d32); -+ } -+ -+ DWC_DEBUGPL(DBG_PCDV, "DAINTMSK=%0x\n", -+ DWC_READ_REG32(&dev_if->dev_global_regs->daintmsk)); -+ -+ ep->stall_clear_flag = 0; -+ -+ return; -+} -+ -+/** -+ * This function deactivates an EP. This is done by clearing the USB Active -+ * EP bit in the Device EP control register. Note: This function is not used -+ * for EP0. EP0 cannot be deactivated. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ * @param ep The EP to deactivate. -+ */ -+void dwc_otg_ep_deactivate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) -+{ -+ depctl_data_t depctl = {.d32 = 0 }; -+ volatile uint32_t *addr; -+ daint_data_t daintmsk = {.d32 = 0 }; -+ dcfg_data_t dcfg; -+ uint8_t i = 0; -+ -+#ifdef DWC_UTE_PER_IO -+ ep->xiso_frame_num = 0xFFFFFFFF; -+ ep->xiso_active_xfers = 0; -+ ep->xiso_queued_xfers = 0; -+#endif -+ -+ /* Read DEPCTLn register */ -+ if (ep->is_in == 1) { -+ addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl; -+ daintmsk.ep.in = 1 << ep->num; -+ } else { -+ addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl; -+ daintmsk.ep.out = 1 << ep->num; -+ } -+ -+ depctl.d32 = DWC_READ_REG32(addr); -+ -+ depctl.b.usbactep = 0; -+ -+ /* Update nextep_seq array and EPMSCNT in DCFG*/ -+ if (!(depctl.b.eptype & 1) && ep->is_in == 1) { // NP EP IN -+ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) { -+ if (core_if->nextep_seq[i] == ep->num) -+ break; -+ } -+ core_if->nextep_seq[i] = core_if->nextep_seq[ep->num]; -+ if (core_if->first_in_nextep_seq == ep->num) -+ core_if->first_in_nextep_seq = i; -+ core_if->nextep_seq[ep->num] = 0xff; -+ depctl.b.nextep = 0; -+ dcfg.d32 = -+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); -+ dcfg.b.epmscnt--; -+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, -+ dcfg.d32); -+ -+ DWC_DEBUGPL(DBG_PCDV, -+ "%s first_in_nextep_seq= %2d; nextep_seq[]:\n", -+ __func__, core_if->first_in_nextep_seq); -+ for (i=0; i <= core_if->dev_if->num_in_eps; i++) { -+ DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]); -+ } -+ } -+ -+ if (ep->is_in == 1) -+ depctl.b.txfnum = 0; -+ -+ if (core_if->dma_desc_enable) -+ depctl.b.epdis = 1; -+ -+ DWC_WRITE_REG32(addr, depctl.d32); -+ depctl.d32 = DWC_READ_REG32(addr); -+ if (core_if->dma_enable && ep->type == DWC_OTG_EP_TYPE_ISOC -+ && depctl.b.epena) { -+ depctl_data_t depctl = {.d32 = 0}; -+ if (ep->is_in) { -+ diepint_data_t diepint = {.d32 = 0}; -+ -+ depctl.b.snak = 1; -+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]-> -+ diepctl, depctl.d32); -+ do { -+ dwc_udelay(10); -+ diepint.d32 = -+ DWC_READ_REG32(&core_if-> -+ dev_if->in_ep_regs[ep->num]-> -+ diepint); -+ } while (!diepint.b.inepnakeff); -+ diepint.b.inepnakeff = 1; -+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]-> -+ diepint, diepint.d32); -+ depctl.d32 = 0; -+ depctl.b.epdis = 1; -+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]-> -+ diepctl, depctl.d32); -+ do { -+ dwc_udelay(10); -+ diepint.d32 = -+ DWC_READ_REG32(&core_if-> -+ dev_if->in_ep_regs[ep->num]-> -+ diepint); -+ } while (!diepint.b.epdisabled); -+ diepint.b.epdisabled = 1; -+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]-> -+ diepint, diepint.d32); -+ } else { -+ dctl_data_t dctl = {.d32 = 0}; -+ gintmsk_data_t gintsts = {.d32 = 0}; -+ doepint_data_t doepint = {.d32 = 0}; -+ dctl.b.sgoutnak = 1; -+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> -+ dctl, 0, dctl.d32); -+ do { -+ dwc_udelay(10); -+ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts); -+ } while (!gintsts.b.goutnakeff); -+ gintsts.d32 = 0; -+ gintsts.b.goutnakeff = 1; -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); -+ -+ depctl.d32 = 0; -+ depctl.b.epdis = 1; -+ depctl.b.snak = 1; -+ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepctl, depctl.d32); -+ do -+ { -+ dwc_udelay(10); -+ doepint.d32 = DWC_READ_REG32(&core_if->dev_if-> -+ out_ep_regs[ep->num]->doepint); -+ } while (!doepint.b.epdisabled); -+ -+ doepint.b.epdisabled = 1; -+ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepint, doepint.d32); -+ -+ dctl.d32 = 0; -+ dctl.b.cgoutnak = 1; -+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32); -+ } -+ } -+ -+ /* Disable the Interrupt for this EP */ -+ if (core_if->multiproc_int_enable) { -+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->deachintmsk, -+ daintmsk.d32, 0); -+ -+ if (ep->is_in == 1) { -+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs-> -+ diepeachintmsk[ep->num], 0); -+ } else { -+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs-> -+ doepeachintmsk[ep->num], 0); -+ } -+ } else { -+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->daintmsk, -+ daintmsk.d32, 0); -+ } -+ -+} -+ -+/** -+ * This function initializes dma descriptor chain. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ * @param ep The EP to start the transfer on. -+ */ -+static void init_dma_desc_chain(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) -+{ -+ dwc_otg_dev_dma_desc_t *dma_desc; -+ uint32_t offset; -+ uint32_t xfer_est; -+ int i; -+ unsigned maxxfer_local, total_len; -+ -+ if (!ep->is_in && ep->type == DWC_OTG_EP_TYPE_INTR && -+ (ep->maxpacket%4)) { -+ maxxfer_local = ep->maxpacket; -+ total_len = ep->xfer_len; -+ } else { -+ maxxfer_local = ep->maxxfer; -+ total_len = ep->total_len; -+ } -+ -+ ep->desc_cnt = (total_len / maxxfer_local) + -+ ((total_len % maxxfer_local) ? 1 : 0); -+ -+ if (!ep->desc_cnt) -+ ep->desc_cnt = 1; -+ -+ if (ep->desc_cnt > MAX_DMA_DESC_CNT) -+ ep->desc_cnt = MAX_DMA_DESC_CNT; -+ -+ dma_desc = ep->desc_addr; -+ if (maxxfer_local == ep->maxpacket) { -+ if ((total_len % maxxfer_local) && -+ (total_len/maxxfer_local < MAX_DMA_DESC_CNT)) { -+ xfer_est = (ep->desc_cnt - 1) * maxxfer_local + -+ (total_len % maxxfer_local); -+ } else -+ xfer_est = ep->desc_cnt * maxxfer_local; -+ } else -+ xfer_est = total_len; -+ offset = 0; -+ for (i = 0; i < ep->desc_cnt; ++i) { -+ /** DMA Descriptor Setup */ -+ if (xfer_est > maxxfer_local) { -+ dma_desc->status.b.bs = BS_HOST_BUSY; -+ dma_desc->status.b.l = 0; -+ dma_desc->status.b.ioc = 0; -+ dma_desc->status.b.sp = 0; -+ dma_desc->status.b.bytes = maxxfer_local; -+ dma_desc->buf = ep->dma_addr + offset; -+ dma_desc->status.b.sts = 0; -+ dma_desc->status.b.bs = BS_HOST_READY; -+ -+ xfer_est -= maxxfer_local; -+ offset += maxxfer_local; -+ } else { -+ dma_desc->status.b.bs = BS_HOST_BUSY; -+ dma_desc->status.b.l = 1; -+ dma_desc->status.b.ioc = 1; -+ if (ep->is_in) { -+ dma_desc->status.b.sp = -+ (xfer_est % -+ ep->maxpacket) ? 1 : ((ep-> -+ sent_zlp) ? 1 : 0); -+ dma_desc->status.b.bytes = xfer_est; -+ } else { -+ if (maxxfer_local == ep->maxpacket) -+ dma_desc->status.b.bytes = xfer_est; -+ else -+ dma_desc->status.b.bytes = -+ xfer_est + ((4 - (xfer_est & 0x3)) & 0x3); -+ } -+ -+ dma_desc->buf = ep->dma_addr + offset; -+ dma_desc->status.b.sts = 0; -+ dma_desc->status.b.bs = BS_HOST_READY; -+ } -+ dma_desc++; -+ } -+} -+/** -+ * This function is called when to write ISOC data into appropriate dedicated -+ * periodic FIFO. -+ */ -+static int32_t write_isoc_tx_fifo(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep) -+{ -+ dwc_otg_dev_if_t *dev_if = core_if->dev_if; -+ dwc_otg_dev_in_ep_regs_t *ep_regs; -+ dtxfsts_data_t txstatus = {.d32 = 0 }; -+ uint32_t len = 0; -+ int epnum = dwc_ep->num; -+ int dwords; -+ -+ DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum); -+ -+ ep_regs = core_if->dev_if->in_ep_regs[epnum]; -+ -+ len = dwc_ep->xfer_len - dwc_ep->xfer_count; -+ -+ if (len > dwc_ep->maxpacket) { -+ len = dwc_ep->maxpacket; -+ } -+ -+ dwords = (len + 3) / 4; -+ -+ /* While there is space in the queue and space in the FIFO and -+ * More data to tranfer, Write packets to the Tx FIFO */ -+ txstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts); -+ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32); -+ -+ while (txstatus.b.txfspcavail > dwords && -+ dwc_ep->xfer_count < dwc_ep->xfer_len && dwc_ep->xfer_len != 0) { -+ /* Write the FIFO */ -+ dwc_otg_ep_write_packet(core_if, dwc_ep, 0); -+ -+ len = dwc_ep->xfer_len - dwc_ep->xfer_count; -+ if (len > dwc_ep->maxpacket) { -+ len = dwc_ep->maxpacket; -+ } -+ -+ dwords = (len + 3) / 4; -+ txstatus.d32 = -+ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts); -+ DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum, -+ txstatus.d32); -+ } -+ -+ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, -+ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts)); -+ -+ return 1; -+} -+/** -+ * This function does the setup for a data transfer for an EP and -+ * starts the transfer. For an IN transfer, the packets will be -+ * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, -+ * the packets are unloaded from the Rx FIFO in the ISR. the ISR. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ * @param ep The EP to start the transfer on. -+ */ -+ -+void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) -+{ -+ depctl_data_t depctl; -+ deptsiz_data_t deptsiz; -+ gintmsk_data_t intr_mask = {.d32 = 0 }; -+ -+ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__); -+ DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d " -+ "xfer_buff=%p start_xfer_buff=%p, total_len = %d\n", -+ ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len, -+ ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff, -+ ep->total_len); -+ /* IN endpoint */ -+ if (ep->is_in == 1) { -+ dwc_otg_dev_in_ep_regs_t *in_regs = -+ core_if->dev_if->in_ep_regs[ep->num]; -+ -+ gnptxsts_data_t gtxstatus; -+ -+ gtxstatus.d32 = -+ DWC_READ_REG32(&core_if->core_global_regs->gnptxsts); -+ -+ if (core_if->en_multiple_tx_fifo == 0 -+ && gtxstatus.b.nptxqspcavail == 0 && !core_if->dma_enable) { -+#ifdef DEBUG -+ DWC_PRINTF("TX Queue Full (0x%0x)\n", gtxstatus.d32); -+#endif -+ return; -+ } -+ -+ depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl)); -+ deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz)); -+ -+ if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT) -+ ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ? -+ ep->maxxfer : (ep->total_len - ep->xfer_len); -+ else -+ ep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len - ep->xfer_len)) ? -+ MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len); -+ -+ -+ /* Zero Length Packet? */ -+ if ((ep->xfer_len - ep->xfer_count) == 0) { -+ deptsiz.b.xfersize = 0; -+ deptsiz.b.pktcnt = 1; -+ } else { -+ /* Program the transfer size and packet count -+ * as follows: xfersize = N * maxpacket + -+ * short_packet pktcnt = N + (short_packet -+ * exist ? 1 : 0) -+ */ -+ deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count; -+ deptsiz.b.pktcnt = -+ (ep->xfer_len - ep->xfer_count - 1 + -+ ep->maxpacket) / ep->maxpacket; -+ if (deptsiz.b.pktcnt > MAX_PKT_CNT) { -+ deptsiz.b.pktcnt = MAX_PKT_CNT; -+ deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket; -+ } -+ if (ep->type == DWC_OTG_EP_TYPE_ISOC) -+ deptsiz.b.mc = deptsiz.b.pktcnt; -+ } -+ -+ /* Write the DMA register */ -+ if (core_if->dma_enable) { -+ if (core_if->dma_desc_enable == 0) { -+ if (ep->type != DWC_OTG_EP_TYPE_ISOC) -+ deptsiz.b.mc = 1; -+ DWC_WRITE_REG32(&in_regs->dieptsiz, -+ deptsiz.d32); -+ DWC_WRITE_REG32(&(in_regs->diepdma), -+ (uint32_t) ep->dma_addr); -+ } else { -+#ifdef DWC_UTE_CFI -+ /* The descriptor chain should be already initialized by now */ -+ if (ep->buff_mode != BM_STANDARD) { -+ DWC_WRITE_REG32(&in_regs->diepdma, -+ ep->descs_dma_addr); -+ } else { -+#endif -+ init_dma_desc_chain(core_if, ep); -+ /** DIEPDMAn Register write */ -+ DWC_WRITE_REG32(&in_regs->diepdma, -+ ep->dma_desc_addr); -+#ifdef DWC_UTE_CFI -+ } -+#endif -+ } -+ } else { -+ DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32); -+ if (ep->type != DWC_OTG_EP_TYPE_ISOC) { -+ /** -+ * Enable the Non-Periodic Tx FIFO empty interrupt, -+ * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, -+ * the data will be written into the fifo by the ISR. -+ */ -+ if (core_if->en_multiple_tx_fifo == 0) { -+ intr_mask.b.nptxfempty = 1; -+ DWC_MODIFY_REG32 -+ (&core_if->core_global_regs->gintmsk, -+ intr_mask.d32, intr_mask.d32); -+ } else { -+ /* Enable the Tx FIFO Empty Interrupt for this EP */ -+ if (ep->xfer_len > 0) { -+ uint32_t fifoemptymsk = 0; -+ fifoemptymsk = 1 << ep->num; -+ DWC_MODIFY_REG32 -+ (&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk, -+ 0, fifoemptymsk); -+ -+ } -+ } -+ } else { -+ write_isoc_tx_fifo(core_if, ep); -+ } -+ } -+ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) -+ depctl.b.nextep = core_if->nextep_seq[ep->num]; -+ -+ if (ep->type == DWC_OTG_EP_TYPE_ISOC) { -+ dsts_data_t dsts = {.d32 = 0}; -+ if (ep->bInterval == 1) { -+ dsts.d32 = -+ DWC_READ_REG32(&core_if->dev_if-> -+ dev_global_regs->dsts); -+ ep->frame_num = dsts.b.soffn + ep->bInterval; -+ if (ep->frame_num > 0x3FFF) { -+ ep->frm_overrun = 1; -+ ep->frame_num &= 0x3FFF; -+ } else -+ ep->frm_overrun = 0; -+ if (ep->frame_num & 0x1) { -+ depctl.b.setd1pid = 1; -+ } else { -+ depctl.b.setd0pid = 1; -+ } -+ } -+ } -+ /* EP enable, IN data in FIFO */ -+ depctl.b.cnak = 1; -+ depctl.b.epena = 1; -+ DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32); -+ -+ } else { -+ /* OUT endpoint */ -+ dwc_otg_dev_out_ep_regs_t *out_regs = -+ core_if->dev_if->out_ep_regs[ep->num]; -+ -+ depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl)); -+ deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz)); -+ -+ if (!core_if->dma_desc_enable) { -+ if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT) -+ ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ? -+ ep->maxxfer : (ep->total_len - ep->xfer_len); -+ else -+ ep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len -+ - ep->xfer_len)) ? MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len); -+ } -+ -+ /* Program the transfer size and packet count as follows: -+ * -+ * pktcnt = N -+ * xfersize = N * maxpacket -+ */ -+ if ((ep->xfer_len - ep->xfer_count) == 0) { -+ /* Zero Length Packet */ -+ deptsiz.b.xfersize = ep->maxpacket; -+ deptsiz.b.pktcnt = 1; -+ } else { -+ deptsiz.b.pktcnt = -+ (ep->xfer_len - ep->xfer_count + -+ (ep->maxpacket - 1)) / ep->maxpacket; -+ if (deptsiz.b.pktcnt > MAX_PKT_CNT) { -+ deptsiz.b.pktcnt = MAX_PKT_CNT; -+ } -+ if (!core_if->dma_desc_enable) { -+ ep->xfer_len = -+ deptsiz.b.pktcnt * ep->maxpacket + ep->xfer_count; -+ } -+ deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count; -+ } -+ -+ DWC_DEBUGPL(DBG_PCDV, "ep%d xfersize=%d pktcnt=%d\n", -+ ep->num, deptsiz.b.xfersize, deptsiz.b.pktcnt); -+ -+ if (core_if->dma_enable) { -+ if (!core_if->dma_desc_enable) { -+ DWC_WRITE_REG32(&out_regs->doeptsiz, -+ deptsiz.d32); -+ -+ DWC_WRITE_REG32(&(out_regs->doepdma), -+ (uint32_t) ep->dma_addr); -+ } else { -+#ifdef DWC_UTE_CFI -+ /* The descriptor chain should be already initialized by now */ -+ if (ep->buff_mode != BM_STANDARD) { -+ DWC_WRITE_REG32(&out_regs->doepdma, -+ ep->descs_dma_addr); -+ } else { -+#endif -+ /** This is used for interrupt out transfers*/ -+ if (!ep->xfer_len) -+ ep->xfer_len = ep->total_len; -+ init_dma_desc_chain(core_if, ep); -+ -+ if (core_if->core_params->dev_out_nak) { -+ if (ep->type == DWC_OTG_EP_TYPE_BULK) { -+ deptsiz.b.pktcnt = (ep->total_len + -+ (ep->maxpacket - 1)) / ep->maxpacket; -+ deptsiz.b.xfersize = ep->total_len; -+ /* Remember initial value of doeptsiz */ -+ core_if->start_doeptsiz_val[ep->num] = deptsiz.d32; -+ DWC_WRITE_REG32(&out_regs->doeptsiz, -+ deptsiz.d32); -+ } -+ } -+ /** DOEPDMAn Register write */ -+ DWC_WRITE_REG32(&out_regs->doepdma, -+ ep->dma_desc_addr); -+#ifdef DWC_UTE_CFI -+ } -+#endif -+ } -+ } else { -+ DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32); -+ } -+ -+ if (ep->type == DWC_OTG_EP_TYPE_ISOC) { -+ dsts_data_t dsts = {.d32 = 0}; -+ if (ep->bInterval == 1) { -+ dsts.d32 = -+ DWC_READ_REG32(&core_if->dev_if-> -+ dev_global_regs->dsts); -+ ep->frame_num = dsts.b.soffn + ep->bInterval; -+ if (ep->frame_num > 0x3FFF) { -+ ep->frm_overrun = 1; -+ ep->frame_num &= 0x3FFF; -+ } else -+ ep->frm_overrun = 0; -+ -+ if (ep->frame_num & 0x1) { -+ depctl.b.setd1pid = 1; -+ } else { -+ depctl.b.setd0pid = 1; -+ } -+ } -+ } -+ -+ /* EP enable */ -+ depctl.b.cnak = 1; -+ depctl.b.epena = 1; -+ -+ DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32); -+ -+ DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n", -+ DWC_READ_REG32(&out_regs->doepctl), -+ DWC_READ_REG32(&out_regs->doeptsiz)); -+ DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n", -+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs-> -+ daintmsk), -+ DWC_READ_REG32(&core_if->core_global_regs-> -+ gintmsk)); -+ -+ /* Timer is scheduling only for out bulk transfers for -+ * "Device DDMA OUT NAK Enhancement" feature to inform user -+ * about received data payload in case of timeout -+ */ -+ if (core_if->core_params->dev_out_nak) { -+ if (ep->type == DWC_OTG_EP_TYPE_BULK) { -+ core_if->ep_xfer_info[ep->num].core_if = core_if; -+ core_if->ep_xfer_info[ep->num].ep = ep; -+ core_if->ep_xfer_info[ep->num].state = 1; -+ -+ /* Start a timer for this transfer. */ -+ DWC_TIMER_SCHEDULE(core_if->ep_xfer_timer[ep->num], 10000); -+ } -+ } -+ } -+} -+ -+/** -+ * This function setup a zero length transfer in Buffer DMA and -+ * Slave modes for usb requests with zero field set -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ * @param ep The EP to start the transfer on. -+ * -+ */ -+void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) -+{ -+ -+ depctl_data_t depctl; -+ deptsiz_data_t deptsiz; -+ gintmsk_data_t intr_mask = {.d32 = 0 }; -+ -+ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__); -+ DWC_PRINTF("zero length transfer is called\n"); -+ -+ /* IN endpoint */ -+ if (ep->is_in == 1) { -+ dwc_otg_dev_in_ep_regs_t *in_regs = -+ core_if->dev_if->in_ep_regs[ep->num]; -+ -+ depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl)); -+ deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz)); -+ -+ deptsiz.b.xfersize = 0; -+ deptsiz.b.pktcnt = 1; -+ -+ /* Write the DMA register */ -+ if (core_if->dma_enable) { -+ if (core_if->dma_desc_enable == 0) { -+ deptsiz.b.mc = 1; -+ DWC_WRITE_REG32(&in_regs->dieptsiz, -+ deptsiz.d32); -+ DWC_WRITE_REG32(&(in_regs->diepdma), -+ (uint32_t) ep->dma_addr); -+ } -+ } else { -+ DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32); -+ /** -+ * Enable the Non-Periodic Tx FIFO empty interrupt, -+ * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, -+ * the data will be written into the fifo by the ISR. -+ */ -+ if (core_if->en_multiple_tx_fifo == 0) { -+ intr_mask.b.nptxfempty = 1; -+ DWC_MODIFY_REG32(&core_if-> -+ core_global_regs->gintmsk, -+ intr_mask.d32, intr_mask.d32); -+ } else { -+ /* Enable the Tx FIFO Empty Interrupt for this EP */ -+ if (ep->xfer_len > 0) { -+ uint32_t fifoemptymsk = 0; -+ fifoemptymsk = 1 << ep->num; -+ DWC_MODIFY_REG32(&core_if-> -+ dev_if->dev_global_regs->dtknqr4_fifoemptymsk, -+ 0, fifoemptymsk); -+ } -+ } -+ } -+ -+ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) -+ depctl.b.nextep = core_if->nextep_seq[ep->num]; -+ /* EP enable, IN data in FIFO */ -+ depctl.b.cnak = 1; -+ depctl.b.epena = 1; -+ DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32); -+ -+ } else { -+ /* OUT endpoint */ -+ dwc_otg_dev_out_ep_regs_t *out_regs = -+ core_if->dev_if->out_ep_regs[ep->num]; -+ -+ depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl)); -+ deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz)); -+ -+ /* Zero Length Packet */ -+ deptsiz.b.xfersize = ep->maxpacket; -+ deptsiz.b.pktcnt = 1; -+ -+ if (core_if->dma_enable) { -+ if (!core_if->dma_desc_enable) { -+ DWC_WRITE_REG32(&out_regs->doeptsiz, -+ deptsiz.d32); -+ -+ DWC_WRITE_REG32(&(out_regs->doepdma), -+ (uint32_t) ep->dma_addr); -+ } -+ } else { -+ DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32); -+ } -+ -+ /* EP enable */ -+ depctl.b.cnak = 1; -+ depctl.b.epena = 1; -+ -+ DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32); -+ -+ } -+} -+ -+/** -+ * This function does the setup for a data transfer for EP0 and starts -+ * the transfer. For an IN transfer, the packets will be loaded into -+ * the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are -+ * unloaded from the Rx FIFO in the ISR. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ * @param ep The EP0 data. -+ */ -+void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) -+{ -+ depctl_data_t depctl; -+ deptsiz0_data_t deptsiz; -+ gintmsk_data_t intr_mask = {.d32 = 0 }; -+ dwc_otg_dev_dma_desc_t *dma_desc; -+ -+ DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d " -+ "xfer_buff=%p start_xfer_buff=%p \n", -+ ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len, -+ ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff); -+ -+ ep->total_len = ep->xfer_len; -+ -+ /* IN endpoint */ -+ if (ep->is_in == 1) { -+ dwc_otg_dev_in_ep_regs_t *in_regs = -+ core_if->dev_if->in_ep_regs[0]; -+ -+ gnptxsts_data_t gtxstatus; -+ -+ if (core_if->snpsid >= OTG_CORE_REV_3_00a) { -+ depctl.d32 = DWC_READ_REG32(&in_regs->diepctl); -+ if (depctl.b.epena) -+ return; -+ } -+ -+ gtxstatus.d32 = -+ DWC_READ_REG32(&core_if->core_global_regs->gnptxsts); -+ -+ /* If dedicated FIFO every time flush fifo before enable ep*/ -+ if (core_if->en_multiple_tx_fifo && core_if->snpsid >= OTG_CORE_REV_3_00a) -+ dwc_otg_flush_tx_fifo(core_if, ep->tx_fifo_num); -+ -+ if (core_if->en_multiple_tx_fifo == 0 -+ && gtxstatus.b.nptxqspcavail == 0 -+ && !core_if->dma_enable) { -+#ifdef DEBUG -+ deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz); -+ DWC_DEBUGPL(DBG_PCD, "DIEPCTL0=%0x\n", -+ DWC_READ_REG32(&in_regs->diepctl)); -+ DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n", -+ deptsiz.d32, -+ deptsiz.b.xfersize, deptsiz.b.pktcnt); -+ DWC_PRINTF("TX Queue or FIFO Full (0x%0x)\n", -+ gtxstatus.d32); -+#endif -+ return; -+ } -+ -+ depctl.d32 = DWC_READ_REG32(&in_regs->diepctl); -+ deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz); -+ -+ /* Zero Length Packet? */ -+ if (ep->xfer_len == 0) { -+ deptsiz.b.xfersize = 0; -+ deptsiz.b.pktcnt = 1; -+ } else { -+ /* Program the transfer size and packet count -+ * as follows: xfersize = N * maxpacket + -+ * short_packet pktcnt = N + (short_packet -+ * exist ? 1 : 0) -+ */ -+ if (ep->xfer_len > ep->maxpacket) { -+ ep->xfer_len = ep->maxpacket; -+ deptsiz.b.xfersize = ep->maxpacket; -+ } else { -+ deptsiz.b.xfersize = ep->xfer_len; -+ } -+ deptsiz.b.pktcnt = 1; -+ -+ } -+ DWC_DEBUGPL(DBG_PCDV, -+ "IN len=%d xfersize=%d pktcnt=%d [%08x]\n", -+ ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt, -+ deptsiz.d32); -+ -+ /* Write the DMA register */ -+ if (core_if->dma_enable) { -+ if (core_if->dma_desc_enable == 0) { -+ DWC_WRITE_REG32(&in_regs->dieptsiz, -+ deptsiz.d32); -+ -+ DWC_WRITE_REG32(&(in_regs->diepdma), -+ (uint32_t) ep->dma_addr); -+ } else { -+ dma_desc = core_if->dev_if->in_desc_addr; -+ -+ /** DMA Descriptor Setup */ -+ dma_desc->status.b.bs = BS_HOST_BUSY; -+ dma_desc->status.b.l = 1; -+ dma_desc->status.b.ioc = 1; -+ dma_desc->status.b.sp = -+ (ep->xfer_len == ep->maxpacket) ? 0 : 1; -+ dma_desc->status.b.bytes = ep->xfer_len; -+ dma_desc->buf = ep->dma_addr; -+ dma_desc->status.b.sts = 0; -+ dma_desc->status.b.bs = BS_HOST_READY; -+ -+ /** DIEPDMA0 Register write */ -+ DWC_WRITE_REG32(&in_regs->diepdma, -+ core_if-> -+ dev_if->dma_in_desc_addr); -+ } -+ } else { -+ DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32); -+ } -+ -+ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) -+ depctl.b.nextep = core_if->nextep_seq[ep->num]; -+ /* EP enable, IN data in FIFO */ -+ depctl.b.cnak = 1; -+ depctl.b.epena = 1; -+ DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32); -+ -+ /** -+ * Enable the Non-Periodic Tx FIFO empty interrupt, the -+ * data will be written into the fifo by the ISR. -+ */ -+ if (!core_if->dma_enable) { -+ if (core_if->en_multiple_tx_fifo == 0) { -+ intr_mask.b.nptxfempty = 1; -+ DWC_MODIFY_REG32(&core_if-> -+ core_global_regs->gintmsk, -+ intr_mask.d32, intr_mask.d32); -+ } else { -+ /* Enable the Tx FIFO Empty Interrupt for this EP */ -+ if (ep->xfer_len > 0) { -+ uint32_t fifoemptymsk = 0; -+ fifoemptymsk |= 1 << ep->num; -+ DWC_MODIFY_REG32(&core_if-> -+ dev_if->dev_global_regs->dtknqr4_fifoemptymsk, -+ 0, fifoemptymsk); -+ } -+ } -+ } -+ } else { -+ /* OUT endpoint */ -+ dwc_otg_dev_out_ep_regs_t *out_regs = -+ core_if->dev_if->out_ep_regs[0]; -+ -+ depctl.d32 = DWC_READ_REG32(&out_regs->doepctl); -+ deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz); -+ -+ /* Program the transfer size and packet count as follows: -+ * xfersize = N * (maxpacket + 4 - (maxpacket % 4)) -+ * pktcnt = N */ -+ /* Zero Length Packet */ -+ deptsiz.b.xfersize = ep->maxpacket; -+ deptsiz.b.pktcnt = 1; -+ if (core_if->snpsid >= OTG_CORE_REV_3_00a) -+ deptsiz.b.supcnt = 3; -+ -+ DWC_DEBUGPL(DBG_PCDV, "len=%d xfersize=%d pktcnt=%d\n", -+ ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt); -+ -+ if (core_if->dma_enable) { -+ if (!core_if->dma_desc_enable) { -+ DWC_WRITE_REG32(&out_regs->doeptsiz, -+ deptsiz.d32); -+ -+ DWC_WRITE_REG32(&(out_regs->doepdma), -+ (uint32_t) ep->dma_addr); -+ } else { -+ dma_desc = core_if->dev_if->out_desc_addr; -+ -+ /** DMA Descriptor Setup */ -+ dma_desc->status.b.bs = BS_HOST_BUSY; -+ if (core_if->snpsid >= OTG_CORE_REV_3_00a) { -+ dma_desc->status.b.mtrf = 0; -+ dma_desc->status.b.sr = 0; -+ } -+ dma_desc->status.b.l = 1; -+ dma_desc->status.b.ioc = 1; -+ dma_desc->status.b.bytes = ep->maxpacket; -+ dma_desc->buf = ep->dma_addr; -+ dma_desc->status.b.sts = 0; -+ dma_desc->status.b.bs = BS_HOST_READY; -+ -+ /** DOEPDMA0 Register write */ -+ DWC_WRITE_REG32(&out_regs->doepdma, -+ core_if->dev_if-> -+ dma_out_desc_addr); -+ } -+ } else { -+ DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32); -+ } -+ -+ /* EP enable */ -+ depctl.b.cnak = 1; -+ depctl.b.epena = 1; -+ DWC_WRITE_REG32(&(out_regs->doepctl), depctl.d32); -+ } -+} -+ -+/** -+ * This function continues control IN transfers started by -+ * dwc_otg_ep0_start_transfer, when the transfer does not fit in a -+ * single packet. NOTE: The DIEPCTL0/DOEPCTL0 registers only have one -+ * bit for the packet count. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ * @param ep The EP0 data. -+ */ -+void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) -+{ -+ depctl_data_t depctl; -+ deptsiz0_data_t deptsiz; -+ gintmsk_data_t intr_mask = {.d32 = 0 }; -+ dwc_otg_dev_dma_desc_t *dma_desc; -+ -+ if (ep->is_in == 1) { -+ dwc_otg_dev_in_ep_regs_t *in_regs = -+ core_if->dev_if->in_ep_regs[0]; -+ gnptxsts_data_t tx_status = {.d32 = 0 }; -+ -+ tx_status.d32 = -+ DWC_READ_REG32(&core_if->core_global_regs->gnptxsts); -+ /** @todo Should there be check for room in the Tx -+ * Status Queue. If not remove the code above this comment. */ -+ -+ depctl.d32 = DWC_READ_REG32(&in_regs->diepctl); -+ deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz); -+ -+ /* Program the transfer size and packet count -+ * as follows: xfersize = N * maxpacket + -+ * short_packet pktcnt = N + (short_packet -+ * exist ? 1 : 0) -+ */ -+ -+ if (core_if->dma_desc_enable == 0) { -+ deptsiz.b.xfersize = -+ (ep->total_len - ep->xfer_count) > -+ ep->maxpacket ? ep->maxpacket : (ep->total_len - -+ ep->xfer_count); -+ deptsiz.b.pktcnt = 1; -+ if (core_if->dma_enable == 0) { -+ ep->xfer_len += deptsiz.b.xfersize; -+ } else { -+ ep->xfer_len = deptsiz.b.xfersize; -+ } -+ DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32); -+ } else { -+ ep->xfer_len = -+ (ep->total_len - ep->xfer_count) > -+ ep->maxpacket ? ep->maxpacket : (ep->total_len - -+ ep->xfer_count); -+ -+ dma_desc = core_if->dev_if->in_desc_addr; -+ -+ /** DMA Descriptor Setup */ -+ dma_desc->status.b.bs = BS_HOST_BUSY; -+ dma_desc->status.b.l = 1; -+ dma_desc->status.b.ioc = 1; -+ dma_desc->status.b.sp = -+ (ep->xfer_len == ep->maxpacket) ? 0 : 1; -+ dma_desc->status.b.bytes = ep->xfer_len; -+ dma_desc->buf = ep->dma_addr; -+ dma_desc->status.b.sts = 0; -+ dma_desc->status.b.bs = BS_HOST_READY; -+ -+ /** DIEPDMA0 Register write */ -+ DWC_WRITE_REG32(&in_regs->diepdma, -+ core_if->dev_if->dma_in_desc_addr); -+ } -+ -+ DWC_DEBUGPL(DBG_PCDV, -+ "IN len=%d xfersize=%d pktcnt=%d [%08x]\n", -+ ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt, -+ deptsiz.d32); -+ -+ /* Write the DMA register */ -+ if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) { -+ if (core_if->dma_desc_enable == 0) -+ DWC_WRITE_REG32(&(in_regs->diepdma), -+ (uint32_t) ep->dma_addr); -+ } -+ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) -+ depctl.b.nextep = core_if->nextep_seq[ep->num]; -+ /* EP enable, IN data in FIFO */ -+ depctl.b.cnak = 1; -+ depctl.b.epena = 1; -+ DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32); -+ -+ /** -+ * Enable the Non-Periodic Tx FIFO empty interrupt, the -+ * data will be written into the fifo by the ISR. -+ */ -+ if (!core_if->dma_enable) { -+ if (core_if->en_multiple_tx_fifo == 0) { -+ /* First clear it from GINTSTS */ -+ intr_mask.b.nptxfempty = 1; -+ DWC_MODIFY_REG32(&core_if-> -+ core_global_regs->gintmsk, -+ intr_mask.d32, intr_mask.d32); -+ -+ } else { -+ /* Enable the Tx FIFO Empty Interrupt for this EP */ -+ if (ep->xfer_len > 0) { -+ uint32_t fifoemptymsk = 0; -+ fifoemptymsk |= 1 << ep->num; -+ DWC_MODIFY_REG32(&core_if-> -+ dev_if->dev_global_regs->dtknqr4_fifoemptymsk, -+ 0, fifoemptymsk); -+ } -+ } -+ } -+ } else { -+ dwc_otg_dev_out_ep_regs_t *out_regs = -+ core_if->dev_if->out_ep_regs[0]; -+ -+ depctl.d32 = DWC_READ_REG32(&out_regs->doepctl); -+ deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz); -+ -+ /* Program the transfer size and packet count -+ * as follows: xfersize = N * maxpacket + -+ * short_packet pktcnt = N + (short_packet -+ * exist ? 1 : 0) -+ */ -+ deptsiz.b.xfersize = ep->maxpacket; -+ deptsiz.b.pktcnt = 1; -+ -+ if (core_if->dma_desc_enable == 0) { -+ DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32); -+ } else { -+ dma_desc = core_if->dev_if->out_desc_addr; -+ -+ /** DMA Descriptor Setup */ -+ dma_desc->status.b.bs = BS_HOST_BUSY; -+ dma_desc->status.b.l = 1; -+ dma_desc->status.b.ioc = 1; -+ dma_desc->status.b.bytes = ep->maxpacket; -+ dma_desc->buf = ep->dma_addr; -+ dma_desc->status.b.sts = 0; -+ dma_desc->status.b.bs = BS_HOST_READY; -+ -+ /** DOEPDMA0 Register write */ -+ DWC_WRITE_REG32(&out_regs->doepdma, -+ core_if->dev_if->dma_out_desc_addr); -+ } -+ -+ DWC_DEBUGPL(DBG_PCDV, -+ "IN len=%d xfersize=%d pktcnt=%d [%08x]\n", -+ ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt, -+ deptsiz.d32); -+ -+ /* Write the DMA register */ -+ if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) { -+ if (core_if->dma_desc_enable == 0) -+ DWC_WRITE_REG32(&(out_regs->doepdma), -+ (uint32_t) ep->dma_addr); -+ -+ } -+ -+ /* EP enable, IN data in FIFO */ -+ depctl.b.cnak = 1; -+ depctl.b.epena = 1; -+ DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32); -+ -+ } -+} -+ -+#ifdef DEBUG -+void dump_msg(const u8 * buf, unsigned int length) -+{ -+ unsigned int start, num, i; -+ char line[52], *p; -+ -+ if (length >= 512) -+ return; -+ start = 0; -+ while (length > 0) { -+ num = length < 16u ? length : 16u; -+ p = line; -+ for (i = 0; i < num; ++i) { -+ if (i == 8) -+ *p++ = ' '; -+ DWC_SPRINTF(p, " %02x", buf[i]); -+ p += 3; -+ } -+ *p = 0; -+ DWC_PRINTF("%6x: %s\n", start, line); -+ buf += num; -+ start += num; -+ length -= num; -+ } -+} -+#else -+static inline void dump_msg(const u8 * buf, unsigned int length) -+{ -+} -+#endif -+ -+/** -+ * This function writes a packet into the Tx FIFO associated with the -+ * EP. For non-periodic EPs the non-periodic Tx FIFO is written. For -+ * periodic EPs the periodic Tx FIFO associated with the EP is written -+ * with all packets for the next micro-frame. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ * @param ep The EP to write packet for. -+ * @param dma Indicates if DMA is being used. -+ */ -+void dwc_otg_ep_write_packet(dwc_otg_core_if_t * core_if, dwc_ep_t * ep, -+ int dma) -+{ -+ /** -+ * The buffer is padded to DWORD on a per packet basis in -+ * slave/dma mode if the MPS is not DWORD aligned. The last -+ * packet, if short, is also padded to a multiple of DWORD. -+ * -+ * ep->xfer_buff always starts DWORD aligned in memory and is a -+ * multiple of DWORD in length -+ * -+ * ep->xfer_len can be any number of bytes -+ * -+ * ep->xfer_count is a multiple of ep->maxpacket until the last -+ * packet -+ * -+ * FIFO access is DWORD */ -+ -+ uint32_t i; -+ uint32_t byte_count; -+ uint32_t dword_count; -+ uint32_t *fifo; -+ uint32_t *data_buff = (uint32_t *) ep->xfer_buff; -+ -+ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p)\n", __func__, core_if, -+ ep); -+ if (ep->xfer_count >= ep->xfer_len) { -+ DWC_WARN("%s() No data for EP%d!!!\n", __func__, ep->num); -+ return; -+ } -+ -+ /* Find the byte length of the packet either short packet or MPS */ -+ if ((ep->xfer_len - ep->xfer_count) < ep->maxpacket) { -+ byte_count = ep->xfer_len - ep->xfer_count; -+ } else { -+ byte_count = ep->maxpacket; -+ } -+ -+ /* Find the DWORD length, padded by extra bytes as neccessary if MPS -+ * is not a multiple of DWORD */ -+ dword_count = (byte_count + 3) / 4; -+ -+#ifdef VERBOSE -+ dump_msg(ep->xfer_buff, byte_count); -+#endif -+ -+ /**@todo NGS Where are the Periodic Tx FIFO addresses -+ * intialized? What should this be? */ -+ -+ fifo = core_if->data_fifo[ep->num]; -+ -+ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "fifo=%p buff=%p *p=%08x bc=%d\n", -+ fifo, data_buff, *data_buff, byte_count); -+ -+ if (!dma) { -+ for (i = 0; i < dword_count; i++, data_buff++) { -+ DWC_WRITE_REG32(fifo, *data_buff); -+ } -+ } -+ -+ ep->xfer_count += byte_count; -+ ep->xfer_buff += byte_count; -+ ep->dma_addr += byte_count; -+} -+ -+/** -+ * Set the EP STALL. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ * @param ep The EP to set the stall on. -+ */ -+void dwc_otg_ep_set_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) -+{ -+ depctl_data_t depctl; -+ volatile uint32_t *depctl_addr; -+ -+ DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num, -+ (ep->is_in ? "IN" : "OUT")); -+ -+ if (ep->is_in == 1) { -+ depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl); -+ depctl.d32 = DWC_READ_REG32(depctl_addr); -+ -+ /* set the disable and stall bits */ -+ if (depctl.b.epena) { -+ depctl.b.epdis = 1; -+ } -+ depctl.b.stall = 1; -+ DWC_WRITE_REG32(depctl_addr, depctl.d32); -+ } else { -+ depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl); -+ depctl.d32 = DWC_READ_REG32(depctl_addr); -+ -+ /* set the stall bit */ -+ depctl.b.stall = 1; -+ DWC_WRITE_REG32(depctl_addr, depctl.d32); -+ } -+ -+ DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr)); -+ -+ return; -+} -+ -+/** -+ * Clear the EP STALL. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ * @param ep The EP to clear stall from. -+ */ -+void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) -+{ -+ depctl_data_t depctl; -+ volatile uint32_t *depctl_addr; -+ -+ DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num, -+ (ep->is_in ? "IN" : "OUT")); -+ -+ if (ep->is_in == 1) { -+ depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl); -+ } else { -+ depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl); -+ } -+ -+ depctl.d32 = DWC_READ_REG32(depctl_addr); -+ -+ /* clear the stall bits */ -+ depctl.b.stall = 0; -+ -+ /* -+ * USB Spec 9.4.5: For endpoints using data toggle, regardless -+ * of whether an endpoint has the Halt feature set, a -+ * ClearFeature(ENDPOINT_HALT) request always results in the -+ * data toggle being reinitialized to DATA0. -+ */ -+ if (ep->type == DWC_OTG_EP_TYPE_INTR || -+ ep->type == DWC_OTG_EP_TYPE_BULK) { -+ depctl.b.setd0pid = 1; /* DATA0 */ -+ } -+ -+ DWC_WRITE_REG32(depctl_addr, depctl.d32); -+ DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr)); -+ return; -+} -+ -+/** -+ * This function reads a packet from the Rx FIFO into the destination -+ * buffer. To read SETUP data use dwc_otg_read_setup_packet. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ * @param dest Destination buffer for the packet. -+ * @param bytes Number of bytes to copy to the destination. -+ */ -+void dwc_otg_read_packet(dwc_otg_core_if_t * core_if, -+ uint8_t * dest, uint16_t bytes) -+{ -+ int i; -+ int word_count = (bytes + 3) / 4; -+ -+ volatile uint32_t *fifo = core_if->data_fifo[0]; -+ uint32_t *data_buff = (uint32_t *) dest; -+ -+ /** -+ * @todo Account for the case where _dest is not dword aligned. This -+ * requires reading data from the FIFO into a uint32_t temp buffer, -+ * then moving it into the data buffer. -+ */ -+ -+ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__, -+ core_if, dest, bytes); -+ -+ for (i = 0; i < word_count; i++, data_buff++) { -+ *data_buff = DWC_READ_REG32(fifo); -+ } -+ -+ return; -+} -+ -+/** -+ * This functions reads the device registers and prints them -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ */ -+void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * core_if) -+{ -+ int i; -+ volatile uint32_t *addr; -+ -+ DWC_PRINTF("Device Global Registers\n"); -+ addr = &core_if->dev_if->dev_global_regs->dcfg; -+ DWC_PRINTF("DCFG @0x%08lX : 0x%08X\n", -+ (unsigned long)addr, DWC_READ_REG32(addr)); -+ addr = &core_if->dev_if->dev_global_regs->dctl; -+ DWC_PRINTF("DCTL @0x%08lX : 0x%08X\n", -+ (unsigned long)addr, DWC_READ_REG32(addr)); -+ addr = &core_if->dev_if->dev_global_regs->dsts; -+ DWC_PRINTF("DSTS @0x%08lX : 0x%08X\n", -+ (unsigned long)addr, DWC_READ_REG32(addr)); -+ addr = &core_if->dev_if->dev_global_regs->diepmsk; -+ DWC_PRINTF("DIEPMSK @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ addr = &core_if->dev_if->dev_global_regs->doepmsk; -+ DWC_PRINTF("DOEPMSK @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ addr = &core_if->dev_if->dev_global_regs->daint; -+ DWC_PRINTF("DAINT @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ addr = &core_if->dev_if->dev_global_regs->daintmsk; -+ DWC_PRINTF("DAINTMSK @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ addr = &core_if->dev_if->dev_global_regs->dtknqr1; -+ DWC_PRINTF("DTKNQR1 @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ if (core_if->hwcfg2.b.dev_token_q_depth > 6) { -+ addr = &core_if->dev_if->dev_global_regs->dtknqr2; -+ DWC_PRINTF("DTKNQR2 @0x%08lX : 0x%08X\n", -+ (unsigned long)addr, DWC_READ_REG32(addr)); -+ } -+ -+ addr = &core_if->dev_if->dev_global_regs->dvbusdis; -+ DWC_PRINTF("DVBUSID @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ -+ addr = &core_if->dev_if->dev_global_regs->dvbuspulse; -+ DWC_PRINTF("DVBUSPULSE @0x%08lX : 0x%08X\n", -+ (unsigned long)addr, DWC_READ_REG32(addr)); -+ -+ addr = &core_if->dev_if->dev_global_regs->dtknqr3_dthrctl; -+ DWC_PRINTF("DTKNQR3_DTHRCTL @0x%08lX : 0x%08X\n", -+ (unsigned long)addr, DWC_READ_REG32(addr)); -+ -+ if (core_if->hwcfg2.b.dev_token_q_depth > 22) { -+ addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk; -+ DWC_PRINTF("DTKNQR4 @0x%08lX : 0x%08X\n", -+ (unsigned long)addr, DWC_READ_REG32(addr)); -+ } -+ -+ addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk; -+ DWC_PRINTF("FIFOEMPMSK @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ -+ if (core_if->hwcfg2.b.multi_proc_int) { -+ -+ addr = &core_if->dev_if->dev_global_regs->deachint; -+ DWC_PRINTF("DEACHINT @0x%08lX : 0x%08X\n", -+ (unsigned long)addr, DWC_READ_REG32(addr)); -+ addr = &core_if->dev_if->dev_global_regs->deachintmsk; -+ DWC_PRINTF("DEACHINTMSK @0x%08lX : 0x%08X\n", -+ (unsigned long)addr, DWC_READ_REG32(addr)); -+ -+ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) { -+ addr = -+ &core_if->dev_if-> -+ dev_global_regs->diepeachintmsk[i]; -+ DWC_PRINTF("DIEPEACHINTMSK[%d] @0x%08lX : 0x%08X\n", -+ i, (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ } -+ -+ for (i = 0; i <= core_if->dev_if->num_out_eps; i++) { -+ addr = -+ &core_if->dev_if-> -+ dev_global_regs->doepeachintmsk[i]; -+ DWC_PRINTF("DOEPEACHINTMSK[%d] @0x%08lX : 0x%08X\n", -+ i, (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ } -+ } -+ -+ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) { -+ DWC_PRINTF("Device IN EP %d Registers\n", i); -+ addr = &core_if->dev_if->in_ep_regs[i]->diepctl; -+ DWC_PRINTF("DIEPCTL @0x%08lX : 0x%08X\n", -+ (unsigned long)addr, DWC_READ_REG32(addr)); -+ addr = &core_if->dev_if->in_ep_regs[i]->diepint; -+ DWC_PRINTF("DIEPINT @0x%08lX : 0x%08X\n", -+ (unsigned long)addr, DWC_READ_REG32(addr)); -+ addr = &core_if->dev_if->in_ep_regs[i]->dieptsiz; -+ DWC_PRINTF("DIETSIZ @0x%08lX : 0x%08X\n", -+ (unsigned long)addr, DWC_READ_REG32(addr)); -+ addr = &core_if->dev_if->in_ep_regs[i]->diepdma; -+ DWC_PRINTF("DIEPDMA @0x%08lX : 0x%08X\n", -+ (unsigned long)addr, DWC_READ_REG32(addr)); -+ addr = &core_if->dev_if->in_ep_regs[i]->dtxfsts; -+ DWC_PRINTF("DTXFSTS @0x%08lX : 0x%08X\n", -+ (unsigned long)addr, DWC_READ_REG32(addr)); -+ addr = &core_if->dev_if->in_ep_regs[i]->diepdmab; -+ DWC_PRINTF("DIEPDMAB @0x%08lX : 0x%08X\n", -+ (unsigned long)addr, 0 /*DWC_READ_REG32(addr) */ ); -+ } -+ -+ for (i = 0; i <= core_if->dev_if->num_out_eps; i++) { -+ DWC_PRINTF("Device OUT EP %d Registers\n", i); -+ addr = &core_if->dev_if->out_ep_regs[i]->doepctl; -+ DWC_PRINTF("DOEPCTL @0x%08lX : 0x%08X\n", -+ (unsigned long)addr, DWC_READ_REG32(addr)); -+ addr = &core_if->dev_if->out_ep_regs[i]->doepint; -+ DWC_PRINTF("DOEPINT @0x%08lX : 0x%08X\n", -+ (unsigned long)addr, DWC_READ_REG32(addr)); -+ addr = &core_if->dev_if->out_ep_regs[i]->doeptsiz; -+ DWC_PRINTF("DOETSIZ @0x%08lX : 0x%08X\n", -+ (unsigned long)addr, DWC_READ_REG32(addr)); -+ addr = &core_if->dev_if->out_ep_regs[i]->doepdma; -+ DWC_PRINTF("DOEPDMA @0x%08lX : 0x%08X\n", -+ (unsigned long)addr, DWC_READ_REG32(addr)); -+ if (core_if->dma_enable) { /* Don't access this register in SLAVE mode */ -+ addr = &core_if->dev_if->out_ep_regs[i]->doepdmab; -+ DWC_PRINTF("DOEPDMAB @0x%08lX : 0x%08X\n", -+ (unsigned long)addr, DWC_READ_REG32(addr)); -+ } -+ -+ } -+} -+ -+/** -+ * This functions reads the SPRAM and prints its content -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ */ -+void dwc_otg_dump_spram(dwc_otg_core_if_t * core_if) -+{ -+ volatile uint8_t *addr, *start_addr, *end_addr; -+ -+ DWC_PRINTF("SPRAM Data:\n"); -+ start_addr = (void *)core_if->core_global_regs; -+ DWC_PRINTF("Base Address: 0x%8lX\n", (unsigned long)start_addr); -+ start_addr += 0x00028000; -+ end_addr = (void *)core_if->core_global_regs; -+ end_addr += 0x000280e0; -+ -+ for (addr = start_addr; addr < end_addr; addr += 16) { -+ DWC_PRINTF -+ ("0x%8lX:\t%2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X\n", -+ (unsigned long)addr, addr[0], addr[1], addr[2], addr[3], -+ addr[4], addr[5], addr[6], addr[7], addr[8], addr[9], -+ addr[10], addr[11], addr[12], addr[13], addr[14], addr[15] -+ ); -+ } -+ -+ return; -+} -+ -+/** -+ * This function reads the host registers and prints them -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ */ -+void dwc_otg_dump_host_registers(dwc_otg_core_if_t * core_if) -+{ -+ int i; -+ volatile uint32_t *addr; -+ -+ DWC_PRINTF("Host Global Registers\n"); -+ addr = &core_if->host_if->host_global_regs->hcfg; -+ DWC_PRINTF("HCFG @0x%08lX : 0x%08X\n", -+ (unsigned long)addr, DWC_READ_REG32(addr)); -+ addr = &core_if->host_if->host_global_regs->hfir; -+ DWC_PRINTF("HFIR @0x%08lX : 0x%08X\n", -+ (unsigned long)addr, DWC_READ_REG32(addr)); -+ addr = &core_if->host_if->host_global_regs->hfnum; -+ DWC_PRINTF("HFNUM @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ addr = &core_if->host_if->host_global_regs->hptxsts; -+ DWC_PRINTF("HPTXSTS @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ addr = &core_if->host_if->host_global_regs->haint; -+ DWC_PRINTF("HAINT @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ addr = &core_if->host_if->host_global_regs->haintmsk; -+ DWC_PRINTF("HAINTMSK @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ if (core_if->dma_desc_enable) { -+ addr = &core_if->host_if->host_global_regs->hflbaddr; -+ DWC_PRINTF("HFLBADDR @0x%08lX : 0x%08X\n", -+ (unsigned long)addr, DWC_READ_REG32(addr)); -+ } -+ -+ addr = core_if->host_if->hprt0; -+ DWC_PRINTF("HPRT0 @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ -+ for (i = 0; i < core_if->core_params->host_channels; i++) { -+ DWC_PRINTF("Host Channel %d Specific Registers\n", i); -+ addr = &core_if->host_if->hc_regs[i]->hcchar; -+ DWC_PRINTF("HCCHAR @0x%08lX : 0x%08X\n", -+ (unsigned long)addr, DWC_READ_REG32(addr)); -+ addr = &core_if->host_if->hc_regs[i]->hcsplt; -+ DWC_PRINTF("HCSPLT @0x%08lX : 0x%08X\n", -+ (unsigned long)addr, DWC_READ_REG32(addr)); -+ addr = &core_if->host_if->hc_regs[i]->hcint; -+ DWC_PRINTF("HCINT @0x%08lX : 0x%08X\n", -+ (unsigned long)addr, DWC_READ_REG32(addr)); -+ addr = &core_if->host_if->hc_regs[i]->hcintmsk; -+ DWC_PRINTF("HCINTMSK @0x%08lX : 0x%08X\n", -+ (unsigned long)addr, DWC_READ_REG32(addr)); -+ addr = &core_if->host_if->hc_regs[i]->hctsiz; -+ DWC_PRINTF("HCTSIZ @0x%08lX : 0x%08X\n", -+ (unsigned long)addr, DWC_READ_REG32(addr)); -+ addr = &core_if->host_if->hc_regs[i]->hcdma; -+ DWC_PRINTF("HCDMA @0x%08lX : 0x%08X\n", -+ (unsigned long)addr, DWC_READ_REG32(addr)); -+ if (core_if->dma_desc_enable) { -+ addr = &core_if->host_if->hc_regs[i]->hcdmab; -+ DWC_PRINTF("HCDMAB @0x%08lX : 0x%08X\n", -+ (unsigned long)addr, DWC_READ_REG32(addr)); -+ } -+ -+ } -+ return; -+} -+ -+/** -+ * This function reads the core global registers and prints them -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ */ -+void dwc_otg_dump_global_registers(dwc_otg_core_if_t * core_if) -+{ -+ int i, ep_num; -+ volatile uint32_t *addr; -+ char *txfsiz; -+ -+ DWC_PRINTF("Core Global Registers\n"); -+ addr = &core_if->core_global_regs->gotgctl; -+ DWC_PRINTF("GOTGCTL @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ addr = &core_if->core_global_regs->gotgint; -+ DWC_PRINTF("GOTGINT @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ addr = &core_if->core_global_regs->gahbcfg; -+ DWC_PRINTF("GAHBCFG @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ addr = &core_if->core_global_regs->gusbcfg; -+ DWC_PRINTF("GUSBCFG @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ addr = &core_if->core_global_regs->grstctl; -+ DWC_PRINTF("GRSTCTL @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ addr = &core_if->core_global_regs->gintsts; -+ DWC_PRINTF("GINTSTS @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ addr = &core_if->core_global_regs->gintmsk; -+ DWC_PRINTF("GINTMSK @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ addr = &core_if->core_global_regs->grxstsr; -+ DWC_PRINTF("GRXSTSR @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ addr = &core_if->core_global_regs->grxfsiz; -+ DWC_PRINTF("GRXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ addr = &core_if->core_global_regs->gnptxfsiz; -+ DWC_PRINTF("GNPTXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ addr = &core_if->core_global_regs->gnptxsts; -+ DWC_PRINTF("GNPTXSTS @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ addr = &core_if->core_global_regs->gi2cctl; -+ DWC_PRINTF("GI2CCTL @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ addr = &core_if->core_global_regs->gpvndctl; -+ DWC_PRINTF("GPVNDCTL @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ addr = &core_if->core_global_regs->ggpio; -+ DWC_PRINTF("GGPIO @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ addr = &core_if->core_global_regs->guid; -+ DWC_PRINTF("GUID @0x%08lX : 0x%08X\n", -+ (unsigned long)addr, DWC_READ_REG32(addr)); -+ addr = &core_if->core_global_regs->gsnpsid; -+ DWC_PRINTF("GSNPSID @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ addr = &core_if->core_global_regs->ghwcfg1; -+ DWC_PRINTF("GHWCFG1 @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ addr = &core_if->core_global_regs->ghwcfg2; -+ DWC_PRINTF("GHWCFG2 @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ addr = &core_if->core_global_regs->ghwcfg3; -+ DWC_PRINTF("GHWCFG3 @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ addr = &core_if->core_global_regs->ghwcfg4; -+ DWC_PRINTF("GHWCFG4 @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ addr = &core_if->core_global_regs->glpmcfg; -+ DWC_PRINTF("GLPMCFG @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ addr = &core_if->core_global_regs->gpwrdn; -+ DWC_PRINTF("GPWRDN @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ addr = &core_if->core_global_regs->gdfifocfg; -+ DWC_PRINTF("GDFIFOCFG @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ addr = &core_if->core_global_regs->adpctl; -+ DWC_PRINTF("ADPCTL @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ dwc_otg_adp_read_reg(core_if)); -+ addr = &core_if->core_global_regs->hptxfsiz; -+ DWC_PRINTF("HPTXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+ -+ if (core_if->en_multiple_tx_fifo == 0) { -+ ep_num = core_if->hwcfg4.b.num_dev_perio_in_ep; -+ txfsiz = "DPTXFSIZ"; -+ } else { -+ ep_num = core_if->hwcfg4.b.num_in_eps; -+ txfsiz = "DIENPTXF"; -+ } -+ for (i = 0; i < ep_num; i++) { -+ addr = &core_if->core_global_regs->dtxfsiz[i]; -+ DWC_PRINTF("%s[%d] @0x%08lX : 0x%08X\n", txfsiz, i + 1, -+ (unsigned long)addr, DWC_READ_REG32(addr)); -+ } -+ addr = core_if->pcgcctl; -+ DWC_PRINTF("PCGCCTL @0x%08lX : 0x%08X\n", (unsigned long)addr, -+ DWC_READ_REG32(addr)); -+} -+ -+/** -+ * Flush a Tx FIFO. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ * @param num Tx FIFO to flush. -+ */ -+void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * core_if, const int num) -+{ -+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; -+ volatile grstctl_t greset = {.d32 = 0 }; -+ int count = 0; -+ -+ DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "Flush Tx FIFO %d\n", num); -+ -+ greset.b.txfflsh = 1; -+ greset.b.txfnum = num; -+ DWC_WRITE_REG32(&global_regs->grstctl, greset.d32); -+ -+ do { -+ greset.d32 = DWC_READ_REG32(&global_regs->grstctl); -+ if (++count > 10000) { -+ DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n", -+ __func__, greset.d32, -+ DWC_READ_REG32(&global_regs->gnptxsts)); -+ break; -+ } -+ dwc_udelay(1); -+ } while (greset.b.txfflsh == 1); -+ -+ /* Wait for 3 PHY Clocks */ -+ dwc_udelay(1); -+} -+ -+/** -+ * Flush Rx FIFO. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ */ -+void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * core_if) -+{ -+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; -+ volatile grstctl_t greset = {.d32 = 0 }; -+ int count = 0; -+ -+ DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "%s\n", __func__); -+ /* -+ * -+ */ -+ greset.b.rxfflsh = 1; -+ DWC_WRITE_REG32(&global_regs->grstctl, greset.d32); -+ -+ do { -+ greset.d32 = DWC_READ_REG32(&global_regs->grstctl); -+ if (++count > 10000) { -+ DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__, -+ greset.d32); -+ break; -+ } -+ dwc_udelay(1); -+ } while (greset.b.rxfflsh == 1); -+ -+ /* Wait for 3 PHY Clocks */ -+ dwc_udelay(1); -+} -+ -+/** -+ * Do core a soft reset of the core. Be careful with this because it -+ * resets all the internal state machines of the core. -+ */ -+void dwc_otg_core_reset(dwc_otg_core_if_t * core_if) -+{ -+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; -+ volatile grstctl_t greset = {.d32 = 0 }; -+ int count = 0; -+ -+ DWC_DEBUGPL(DBG_CILV, "%s\n", __func__); -+ /* Wait for AHB master IDLE state. */ -+ do { -+ dwc_udelay(10); -+ greset.d32 = DWC_READ_REG32(&global_regs->grstctl); -+ if (++count > 100000) { -+ DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x\n", __func__, -+ greset.d32); -+ return; -+ } -+ } -+ while (greset.b.ahbidle == 0); -+ -+ /* Core Soft Reset */ -+ count = 0; -+ greset.b.csftrst = 1; -+ DWC_WRITE_REG32(&global_regs->grstctl, greset.d32); -+ do { -+ greset.d32 = DWC_READ_REG32(&global_regs->grstctl); -+ if (++count > 10000) { -+ DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n", -+ __func__, greset.d32); -+ break; -+ } -+ dwc_udelay(1); -+ } -+ while (greset.b.csftrst == 1); -+ -+ /* Wait for 3 PHY Clocks */ -+ dwc_mdelay(100); -+} -+ -+uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if) -+{ -+ return (dwc_otg_mode(_core_if) != DWC_HOST_MODE); -+} -+ -+uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if) -+{ -+ return (dwc_otg_mode(_core_if) == DWC_HOST_MODE); -+} -+ -+/** -+ * Register HCD callbacks. The callbacks are used to start and stop -+ * the HCD for interrupt processing. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ * @param cb the HCD callback structure. -+ * @param p pointer to be passed to callback function (usb_hcd*). -+ */ -+void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * core_if, -+ dwc_otg_cil_callbacks_t * cb, void *p) -+{ -+ core_if->hcd_cb = cb; -+ cb->p = p; -+} -+ -+/** -+ * Register PCD callbacks. The callbacks are used to start and stop -+ * the PCD for interrupt processing. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ * @param cb the PCD callback structure. -+ * @param p pointer to be passed to callback function (pcd*). -+ */ -+void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * core_if, -+ dwc_otg_cil_callbacks_t * cb, void *p) -+{ -+ core_if->pcd_cb = cb; -+ cb->p = p; -+} -+ -+#ifdef DWC_EN_ISOC -+ -+/** -+ * This function writes isoc data per 1 (micro)frame into tx fifo -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ * @param ep The EP to start the transfer on. -+ * -+ */ -+void write_isoc_frame_data(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) -+{ -+ dwc_otg_dev_in_ep_regs_t *ep_regs; -+ dtxfsts_data_t txstatus = {.d32 = 0 }; -+ uint32_t len = 0; -+ uint32_t dwords; -+ -+ ep->xfer_len = ep->data_per_frame; -+ ep->xfer_count = 0; -+ -+ ep_regs = core_if->dev_if->in_ep_regs[ep->num]; -+ -+ len = ep->xfer_len - ep->xfer_count; -+ -+ if (len > ep->maxpacket) { -+ len = ep->maxpacket; -+ } -+ -+ dwords = (len + 3) / 4; -+ -+ /* While there is space in the queue and space in the FIFO and -+ * More data to tranfer, Write packets to the Tx FIFO */ -+ txstatus.d32 = -+ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts); -+ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", ep->num, txstatus.d32); -+ -+ while (txstatus.b.txfspcavail > dwords && -+ ep->xfer_count < ep->xfer_len && ep->xfer_len != 0) { -+ /* Write the FIFO */ -+ dwc_otg_ep_write_packet(core_if, ep, 0); -+ -+ len = ep->xfer_len - ep->xfer_count; -+ if (len > ep->maxpacket) { -+ len = ep->maxpacket; -+ } -+ -+ dwords = (len + 3) / 4; -+ txstatus.d32 = -+ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]-> -+ dtxfsts); -+ DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", ep->num, -+ txstatus.d32); -+ } -+} -+ -+/** -+ * This function initializes a descriptor chain for Isochronous transfer -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ * @param ep The EP to start the transfer on. -+ * -+ */ -+void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if, -+ dwc_ep_t * ep) -+{ -+ deptsiz_data_t deptsiz = {.d32 = 0 }; -+ depctl_data_t depctl = {.d32 = 0 }; -+ dsts_data_t dsts = {.d32 = 0 }; -+ volatile uint32_t *addr; -+ -+ if (ep->is_in) { -+ addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl; -+ } else { -+ addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl; -+ } -+ -+ ep->xfer_len = ep->data_per_frame; -+ ep->xfer_count = 0; -+ ep->xfer_buff = ep->cur_pkt_addr; -+ ep->dma_addr = ep->cur_pkt_dma_addr; -+ -+ if (ep->is_in) { -+ /* Program the transfer size and packet count -+ * as follows: xfersize = N * maxpacket + -+ * short_packet pktcnt = N + (short_packet -+ * exist ? 1 : 0) -+ */ -+ deptsiz.b.xfersize = ep->xfer_len; -+ deptsiz.b.pktcnt = -+ (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket; -+ deptsiz.b.mc = deptsiz.b.pktcnt; -+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz, -+ deptsiz.d32); -+ -+ /* Write the DMA register */ -+ if (core_if->dma_enable) { -+ DWC_WRITE_REG32(& -+ (core_if->dev_if->in_ep_regs[ep->num]-> -+ diepdma), (uint32_t) ep->dma_addr); -+ } -+ } else { -+ deptsiz.b.pktcnt = -+ (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket; -+ deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket; -+ -+ DWC_WRITE_REG32(&core_if->dev_if-> -+ out_ep_regs[ep->num]->doeptsiz, deptsiz.d32); -+ -+ if (core_if->dma_enable) { -+ DWC_WRITE_REG32(& -+ (core_if->dev_if-> -+ out_ep_regs[ep->num]->doepdma), -+ (uint32_t) ep->dma_addr); -+ } -+ } -+ -+ /** Enable endpoint, clear nak */ -+ -+ depctl.d32 = 0; -+ if (ep->bInterval == 1) { -+ dsts.d32 = -+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); -+ ep->next_frame = dsts.b.soffn + ep->bInterval; -+ -+ if (ep->next_frame & 0x1) { -+ depctl.b.setd1pid = 1; -+ } else { -+ depctl.b.setd0pid = 1; -+ } -+ } else { -+ ep->next_frame += ep->bInterval; -+ -+ if (ep->next_frame & 0x1) { -+ depctl.b.setd1pid = 1; -+ } else { -+ depctl.b.setd0pid = 1; -+ } -+ } -+ depctl.b.epena = 1; -+ depctl.b.cnak = 1; -+ -+ DWC_MODIFY_REG32(addr, 0, depctl.d32); -+ depctl.d32 = DWC_READ_REG32(addr); -+ -+ if (ep->is_in && core_if->dma_enable == 0) { -+ write_isoc_frame_data(core_if, ep); -+ } -+ -+} -+#endif /* DWC_EN_ISOC */ -+ -+static void dwc_otg_set_uninitialized(int32_t * p, int size) -+{ -+ int i; -+ for (i = 0; i < size; i++) { -+ p[i] = -1; -+ } -+} -+ -+static int dwc_otg_param_initialized(int32_t val) -+{ -+ return val != -1; -+} -+ -+static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if) -+{ -+ int i; -+ core_if->core_params = DWC_ALLOC(sizeof(*core_if->core_params)); -+ if (!core_if->core_params) { -+ return -DWC_E_NO_MEMORY; -+ } -+ dwc_otg_set_uninitialized((int32_t *) core_if->core_params, -+ sizeof(*core_if->core_params) / -+ sizeof(int32_t)); -+ DWC_PRINTF("Setting default values for core params\n"); -+ dwc_otg_set_param_otg_cap(core_if, dwc_param_otg_cap_default); -+ dwc_otg_set_param_dma_enable(core_if, dwc_param_dma_enable_default); -+ dwc_otg_set_param_dma_desc_enable(core_if, -+ dwc_param_dma_desc_enable_default); -+ dwc_otg_set_param_opt(core_if, dwc_param_opt_default); -+ dwc_otg_set_param_dma_burst_size(core_if, -+ dwc_param_dma_burst_size_default); -+ dwc_otg_set_param_host_support_fs_ls_low_power(core_if, -+ dwc_param_host_support_fs_ls_low_power_default); -+ dwc_otg_set_param_enable_dynamic_fifo(core_if, -+ dwc_param_enable_dynamic_fifo_default); -+ dwc_otg_set_param_data_fifo_size(core_if, -+ dwc_param_data_fifo_size_default); -+ dwc_otg_set_param_dev_rx_fifo_size(core_if, -+ dwc_param_dev_rx_fifo_size_default); -+ dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if, -+ dwc_param_dev_nperio_tx_fifo_size_default); -+ dwc_otg_set_param_host_rx_fifo_size(core_if, -+ dwc_param_host_rx_fifo_size_default); -+ dwc_otg_set_param_host_nperio_tx_fifo_size(core_if, -+ dwc_param_host_nperio_tx_fifo_size_default); -+ dwc_otg_set_param_host_perio_tx_fifo_size(core_if, -+ dwc_param_host_perio_tx_fifo_size_default); -+ dwc_otg_set_param_max_transfer_size(core_if, -+ dwc_param_max_transfer_size_default); -+ dwc_otg_set_param_max_packet_count(core_if, -+ dwc_param_max_packet_count_default); -+ dwc_otg_set_param_host_channels(core_if, -+ dwc_param_host_channels_default); -+ dwc_otg_set_param_dev_endpoints(core_if, -+ dwc_param_dev_endpoints_default); -+ dwc_otg_set_param_phy_type(core_if, dwc_param_phy_type_default); -+ dwc_otg_set_param_speed(core_if, dwc_param_speed_default); -+ dwc_otg_set_param_host_ls_low_power_phy_clk(core_if, -+ dwc_param_host_ls_low_power_phy_clk_default); -+ dwc_otg_set_param_phy_ulpi_ddr(core_if, dwc_param_phy_ulpi_ddr_default); -+ dwc_otg_set_param_phy_ulpi_ext_vbus(core_if, -+ dwc_param_phy_ulpi_ext_vbus_default); -+ dwc_otg_set_param_phy_utmi_width(core_if, -+ dwc_param_phy_utmi_width_default); -+ dwc_otg_set_param_ts_dline(core_if, dwc_param_ts_dline_default); -+ dwc_otg_set_param_i2c_enable(core_if, dwc_param_i2c_enable_default); -+ dwc_otg_set_param_ulpi_fs_ls(core_if, dwc_param_ulpi_fs_ls_default); -+ dwc_otg_set_param_en_multiple_tx_fifo(core_if, -+ dwc_param_en_multiple_tx_fifo_default); -+ for (i = 0; i < 15; i++) { -+ dwc_otg_set_param_dev_perio_tx_fifo_size(core_if, -+ dwc_param_dev_perio_tx_fifo_size_default, -+ i); -+ } -+ -+ for (i = 0; i < 15; i++) { -+ dwc_otg_set_param_dev_tx_fifo_size(core_if, -+ dwc_param_dev_tx_fifo_size_default, -+ i); -+ } -+ dwc_otg_set_param_thr_ctl(core_if, dwc_param_thr_ctl_default); -+ dwc_otg_set_param_mpi_enable(core_if, dwc_param_mpi_enable_default); -+ dwc_otg_set_param_pti_enable(core_if, dwc_param_pti_enable_default); -+ dwc_otg_set_param_lpm_enable(core_if, dwc_param_lpm_enable_default); -+ dwc_otg_set_param_ic_usb_cap(core_if, dwc_param_ic_usb_cap_default); -+ dwc_otg_set_param_tx_thr_length(core_if, -+ dwc_param_tx_thr_length_default); -+ dwc_otg_set_param_rx_thr_length(core_if, -+ dwc_param_rx_thr_length_default); -+ dwc_otg_set_param_ahb_thr_ratio(core_if, -+ dwc_param_ahb_thr_ratio_default); -+ dwc_otg_set_param_power_down(core_if, dwc_param_power_down_default); -+ dwc_otg_set_param_reload_ctl(core_if, dwc_param_reload_ctl_default); -+ dwc_otg_set_param_dev_out_nak(core_if, dwc_param_dev_out_nak_default); -+ dwc_otg_set_param_cont_on_bna(core_if, dwc_param_cont_on_bna_default); -+ dwc_otg_set_param_ahb_single(core_if, dwc_param_ahb_single_default); -+ dwc_otg_set_param_otg_ver(core_if, dwc_param_otg_ver_default); -+ dwc_otg_set_param_adp_enable(core_if, dwc_param_adp_enable_default); -+ DWC_PRINTF("Finished setting default values for core params\n"); -+ -+ return 0; -+} -+ -+uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->dma_enable; -+} -+ -+/* Checks if the parameter is outside of its valid range of values */ -+#define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \ -+ (((_param_) < (_low_)) || \ -+ ((_param_) > (_high_))) -+ -+/* Parameter access functions */ -+int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val) -+{ -+ int valid; -+ int retval = 0; -+ if (DWC_OTG_PARAM_TEST(val, 0, 2)) { -+ DWC_WARN("Wrong value for otg_cap parameter\n"); -+ DWC_WARN("otg_cap parameter must be 0,1 or 2\n"); -+ retval = -DWC_E_INVALID; -+ goto out; -+ } -+ -+ valid = 1; -+ switch (val) { -+ case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE: -+ if (core_if->hwcfg2.b.op_mode != -+ DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) -+ valid = 0; -+ break; -+ case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE: -+ if ((core_if->hwcfg2.b.op_mode != -+ DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) -+ && (core_if->hwcfg2.b.op_mode != -+ DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) -+ && (core_if->hwcfg2.b.op_mode != -+ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) -+ && (core_if->hwcfg2.b.op_mode != -+ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) { -+ valid = 0; -+ } -+ break; -+ case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE: -+ /* always valid */ -+ break; -+ } -+ if (!valid) { -+ if (dwc_otg_param_initialized(core_if->core_params->otg_cap)) { -+ DWC_ERROR -+ ("%d invalid for otg_cap paremter. Check HW configuration.\n", -+ val); -+ } -+ val = -+ (((core_if->hwcfg2.b.op_mode == -+ DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) -+ || (core_if->hwcfg2.b.op_mode == -+ DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) -+ || (core_if->hwcfg2.b.op_mode == -+ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) -+ || (core_if->hwcfg2.b.op_mode == -+ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ? -+ DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE : -+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); -+ retval = -DWC_E_INVALID; -+ } -+ -+ core_if->core_params->otg_cap = val; -+out: -+ return retval; -+} -+ -+int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->otg_cap; -+} -+ -+int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val) -+{ -+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { -+ DWC_WARN("Wrong value for opt parameter\n"); -+ return -DWC_E_INVALID; -+ } -+ core_if->core_params->opt = val; -+ return 0; -+} -+ -+int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->opt; -+} -+ -+int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if, int32_t val) -+{ -+ int retval = 0; -+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { -+ DWC_WARN("Wrong value for dma enable\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ if ((val == 1) && (core_if->hwcfg2.b.architecture == 0)) { -+ if (dwc_otg_param_initialized(core_if->core_params->dma_enable)) { -+ DWC_ERROR -+ ("%d invalid for dma_enable paremter. Check HW configuration.\n", -+ val); -+ } -+ val = 0; -+ retval = -DWC_E_INVALID; -+ } -+ -+ core_if->core_params->dma_enable = val; -+ if (val == 0) { -+ dwc_otg_set_param_dma_desc_enable(core_if, 0); -+ } -+ return retval; -+} -+ -+int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->dma_enable; -+} -+ -+int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if, int32_t val) -+{ -+ int retval = 0; -+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { -+ DWC_WARN("Wrong value for dma_enable\n"); -+ DWC_WARN("dma_desc_enable must be 0 or 1\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ if ((val == 1) -+ && ((dwc_otg_get_param_dma_enable(core_if) == 0) -+ || (core_if->hwcfg4.b.desc_dma == 0))) { -+ if (dwc_otg_param_initialized -+ (core_if->core_params->dma_desc_enable)) { -+ DWC_ERROR -+ ("%d invalid for dma_desc_enable paremter. Check HW configuration.\n", -+ val); -+ } -+ val = 0; -+ retval = -DWC_E_INVALID; -+ } -+ core_if->core_params->dma_desc_enable = val; -+ return retval; -+} -+ -+int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->dma_desc_enable; -+} -+ -+int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t * core_if, -+ int32_t val) -+{ -+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { -+ DWC_WARN("Wrong value for host_support_fs_low_power\n"); -+ DWC_WARN("host_support_fs_low_power must be 0 or 1\n"); -+ return -DWC_E_INVALID; -+ } -+ core_if->core_params->host_support_fs_ls_low_power = val; -+ return 0; -+} -+ -+int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t * -+ core_if) -+{ -+ return core_if->core_params->host_support_fs_ls_low_power; -+} -+ -+int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if, -+ int32_t val) -+{ -+ int retval = 0; -+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { -+ DWC_WARN("Wrong value for enable_dynamic_fifo\n"); -+ DWC_WARN("enable_dynamic_fifo must be 0 or 1\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ if ((val == 1) && (core_if->hwcfg2.b.dynamic_fifo == 0)) { -+ if (dwc_otg_param_initialized -+ (core_if->core_params->enable_dynamic_fifo)) { -+ DWC_ERROR -+ ("%d invalid for enable_dynamic_fifo paremter. Check HW configuration.\n", -+ val); -+ } -+ val = 0; -+ retval = -DWC_E_INVALID; -+ } -+ core_if->core_params->enable_dynamic_fifo = val; -+ return retval; -+} -+ -+int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->enable_dynamic_fifo; -+} -+ -+int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if, int32_t val) -+{ -+ int retval = 0; -+ if (DWC_OTG_PARAM_TEST(val, 32, 32768)) { -+ DWC_WARN("Wrong value for data_fifo_size\n"); -+ DWC_WARN("data_fifo_size must be 32-32768\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ if (val > core_if->hwcfg3.b.dfifo_depth) { -+ if (dwc_otg_param_initialized -+ (core_if->core_params->data_fifo_size)) { -+ DWC_ERROR -+ ("%d invalid for data_fifo_size parameter. Check HW configuration.\n", -+ val); -+ } -+ val = core_if->hwcfg3.b.dfifo_depth; -+ retval = -DWC_E_INVALID; -+ } -+ -+ core_if->core_params->data_fifo_size = val; -+ return retval; -+} -+ -+int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->data_fifo_size; -+} -+ -+int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val) -+{ -+ int retval = 0; -+ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) { -+ DWC_WARN("Wrong value for dev_rx_fifo_size\n"); -+ DWC_WARN("dev_rx_fifo_size must be 16-32768\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) { -+ if (dwc_otg_param_initialized(core_if->core_params->dev_rx_fifo_size)) { -+ DWC_WARN("%d invalid for dev_rx_fifo_size parameter\n", val); -+ } -+ val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz); -+ retval = -DWC_E_INVALID; -+ } -+ -+ core_if->core_params->dev_rx_fifo_size = val; -+ return retval; -+} -+ -+int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->dev_rx_fifo_size; -+} -+ -+int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if, -+ int32_t val) -+{ -+ int retval = 0; -+ -+ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) { -+ DWC_WARN("Wrong value for dev_nperio_tx_fifo\n"); -+ DWC_WARN("dev_nperio_tx_fifo must be 16-32768\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) { -+ if (dwc_otg_param_initialized -+ (core_if->core_params->dev_nperio_tx_fifo_size)) { -+ DWC_ERROR -+ ("%d invalid for dev_nperio_tx_fifo_size. Check HW configuration.\n", -+ val); -+ } -+ val = -+ (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> -+ 16); -+ retval = -DWC_E_INVALID; -+ } -+ -+ core_if->core_params->dev_nperio_tx_fifo_size = val; -+ return retval; -+} -+ -+int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->dev_nperio_tx_fifo_size; -+} -+ -+int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if, -+ int32_t val) -+{ -+ int retval = 0; -+ -+ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) { -+ DWC_WARN("Wrong value for host_rx_fifo_size\n"); -+ DWC_WARN("host_rx_fifo_size must be 16-32768\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) { -+ if (dwc_otg_param_initialized -+ (core_if->core_params->host_rx_fifo_size)) { -+ DWC_ERROR -+ ("%d invalid for host_rx_fifo_size. Check HW configuration.\n", -+ val); -+ } -+ val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz); -+ retval = -DWC_E_INVALID; -+ } -+ -+ core_if->core_params->host_rx_fifo_size = val; -+ return retval; -+ -+} -+ -+int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->host_rx_fifo_size; -+} -+ -+int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if, -+ int32_t val) -+{ -+ int retval = 0; -+ -+ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) { -+ DWC_WARN("Wrong value for host_nperio_tx_fifo_size\n"); -+ DWC_WARN("host_nperio_tx_fifo_size must be 16-32768\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) { -+ if (dwc_otg_param_initialized -+ (core_if->core_params->host_nperio_tx_fifo_size)) { -+ DWC_ERROR -+ ("%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n", -+ val); -+ } -+ val = -+ (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> -+ 16); -+ retval = -DWC_E_INVALID; -+ } -+ -+ core_if->core_params->host_nperio_tx_fifo_size = val; -+ return retval; -+} -+ -+int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->host_nperio_tx_fifo_size; -+} -+ -+int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if, -+ int32_t val) -+{ -+ int retval = 0; -+ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) { -+ DWC_WARN("Wrong value for host_perio_tx_fifo_size\n"); -+ DWC_WARN("host_perio_tx_fifo_size must be 16-32768\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ if (val > ((core_if->hptxfsiz.d32) >> 16)) { -+ if (dwc_otg_param_initialized -+ (core_if->core_params->host_perio_tx_fifo_size)) { -+ DWC_ERROR -+ ("%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n", -+ val); -+ } -+ val = (core_if->hptxfsiz.d32) >> 16; -+ retval = -DWC_E_INVALID; -+ } -+ -+ core_if->core_params->host_perio_tx_fifo_size = val; -+ return retval; -+} -+ -+int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->host_perio_tx_fifo_size; -+} -+ -+int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if, -+ int32_t val) -+{ -+ int retval = 0; -+ -+ if (DWC_OTG_PARAM_TEST(val, 2047, 524288)) { -+ DWC_WARN("Wrong value for max_transfer_size\n"); -+ DWC_WARN("max_transfer_size must be 2047-524288\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ if (val >= (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))) { -+ if (dwc_otg_param_initialized -+ (core_if->core_params->max_transfer_size)) { -+ DWC_ERROR -+ ("%d invalid for max_transfer_size. Check HW configuration.\n", -+ val); -+ } -+ val = -+ ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 11)) - -+ 1); -+ retval = -DWC_E_INVALID; -+ } -+ -+ core_if->core_params->max_transfer_size = val; -+ return retval; -+} -+ -+int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->max_transfer_size; -+} -+ -+int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if, int32_t val) -+{ -+ int retval = 0; -+ -+ if (DWC_OTG_PARAM_TEST(val, 15, 511)) { -+ DWC_WARN("Wrong value for max_packet_count\n"); -+ DWC_WARN("max_packet_count must be 15-511\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ if (val > (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))) { -+ if (dwc_otg_param_initialized -+ (core_if->core_params->max_packet_count)) { -+ DWC_ERROR -+ ("%d invalid for max_packet_count. Check HW configuration.\n", -+ val); -+ } -+ val = -+ ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1); -+ retval = -DWC_E_INVALID; -+ } -+ -+ core_if->core_params->max_packet_count = val; -+ return retval; -+} -+ -+int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->max_packet_count; -+} -+ -+int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if, int32_t val) -+{ -+ int retval = 0; -+ -+ if (DWC_OTG_PARAM_TEST(val, 1, 16)) { -+ DWC_WARN("Wrong value for host_channels\n"); -+ DWC_WARN("host_channels must be 1-16\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ if (val > (core_if->hwcfg2.b.num_host_chan + 1)) { -+ if (dwc_otg_param_initialized -+ (core_if->core_params->host_channels)) { -+ DWC_ERROR -+ ("%d invalid for host_channels. Check HW configurations.\n", -+ val); -+ } -+ val = (core_if->hwcfg2.b.num_host_chan + 1); -+ retval = -DWC_E_INVALID; -+ } -+ -+ core_if->core_params->host_channels = val; -+ return retval; -+} -+ -+int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->host_channels; -+} -+ -+int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if, int32_t val) -+{ -+ int retval = 0; -+ -+ if (DWC_OTG_PARAM_TEST(val, 1, 15)) { -+ DWC_WARN("Wrong value for dev_endpoints\n"); -+ DWC_WARN("dev_endpoints must be 1-15\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ if (val > (core_if->hwcfg2.b.num_dev_ep)) { -+ if (dwc_otg_param_initialized -+ (core_if->core_params->dev_endpoints)) { -+ DWC_ERROR -+ ("%d invalid for dev_endpoints. Check HW configurations.\n", -+ val); -+ } -+ val = core_if->hwcfg2.b.num_dev_ep; -+ retval = -DWC_E_INVALID; -+ } -+ -+ core_if->core_params->dev_endpoints = val; -+ return retval; -+} -+ -+int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->dev_endpoints; -+} -+ -+int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val) -+{ -+ int retval = 0; -+ int valid = 0; -+ -+ if (DWC_OTG_PARAM_TEST(val, 0, 2)) { -+ DWC_WARN("Wrong value for phy_type\n"); -+ DWC_WARN("phy_type must be 0,1 or 2\n"); -+ return -DWC_E_INVALID; -+ } -+#ifndef NO_FS_PHY_HW_CHECKS -+ if ((val == DWC_PHY_TYPE_PARAM_UTMI) && -+ ((core_if->hwcfg2.b.hs_phy_type == 1) || -+ (core_if->hwcfg2.b.hs_phy_type == 3))) { -+ valid = 1; -+ } else if ((val == DWC_PHY_TYPE_PARAM_ULPI) && -+ ((core_if->hwcfg2.b.hs_phy_type == 2) || -+ (core_if->hwcfg2.b.hs_phy_type == 3))) { -+ valid = 1; -+ } else if ((val == DWC_PHY_TYPE_PARAM_FS) && -+ (core_if->hwcfg2.b.fs_phy_type == 1)) { -+ valid = 1; -+ } -+ if (!valid) { -+ if (dwc_otg_param_initialized(core_if->core_params->phy_type)) { -+ DWC_ERROR -+ ("%d invalid for phy_type. Check HW configurations.\n", -+ val); -+ } -+ if (core_if->hwcfg2.b.hs_phy_type) { -+ if ((core_if->hwcfg2.b.hs_phy_type == 3) || -+ (core_if->hwcfg2.b.hs_phy_type == 1)) { -+ val = DWC_PHY_TYPE_PARAM_UTMI; -+ } else { -+ val = DWC_PHY_TYPE_PARAM_ULPI; -+ } -+ } -+ retval = -DWC_E_INVALID; -+ } -+#endif -+ core_if->core_params->phy_type = val; -+ return retval; -+} -+ -+int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->phy_type; -+} -+ -+int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val) -+{ -+ int retval = 0; -+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { -+ DWC_WARN("Wrong value for speed parameter\n"); -+ DWC_WARN("max_speed parameter must be 0 or 1\n"); -+ return -DWC_E_INVALID; -+ } -+ if ((val == 0) -+ && dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS) { -+ if (dwc_otg_param_initialized(core_if->core_params->speed)) { -+ DWC_ERROR -+ ("%d invalid for speed paremter. Check HW configuration.\n", -+ val); -+ } -+ val = -+ (dwc_otg_get_param_phy_type(core_if) == -+ DWC_PHY_TYPE_PARAM_FS ? 1 : 0); -+ retval = -DWC_E_INVALID; -+ } -+ core_if->core_params->speed = val; -+ return retval; -+} -+ -+int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->speed; -+} -+ -+int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if, -+ int32_t val) -+{ -+ int retval = 0; -+ -+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { -+ DWC_WARN -+ ("Wrong value for host_ls_low_power_phy_clk parameter\n"); -+ DWC_WARN("host_ls_low_power_phy_clk must be 0 or 1\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ if ((val == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ) -+ && (dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS)) { -+ if (dwc_otg_param_initialized -+ (core_if->core_params->host_ls_low_power_phy_clk)) { -+ DWC_ERROR -+ ("%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n", -+ val); -+ } -+ val = -+ (dwc_otg_get_param_phy_type(core_if) == -+ DWC_PHY_TYPE_PARAM_FS) ? -+ DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ : -+ DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ; -+ retval = -DWC_E_INVALID; -+ } -+ -+ core_if->core_params->host_ls_low_power_phy_clk = val; -+ return retval; -+} -+ -+int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->host_ls_low_power_phy_clk; -+} -+ -+int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if, int32_t val) -+{ -+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { -+ DWC_WARN("Wrong value for phy_ulpi_ddr\n"); -+ DWC_WARN("phy_upli_ddr must be 0 or 1\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ core_if->core_params->phy_ulpi_ddr = val; -+ return 0; -+} -+ -+int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->phy_ulpi_ddr; -+} -+ -+int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if, -+ int32_t val) -+{ -+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { -+ DWC_WARN("Wrong valaue for phy_ulpi_ext_vbus\n"); -+ DWC_WARN("phy_ulpi_ext_vbus must be 0 or 1\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ core_if->core_params->phy_ulpi_ext_vbus = val; -+ return 0; -+} -+ -+int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->phy_ulpi_ext_vbus; -+} -+ -+int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if, int32_t val) -+{ -+ if (DWC_OTG_PARAM_TEST(val, 8, 8) && DWC_OTG_PARAM_TEST(val, 16, 16)) { -+ DWC_WARN("Wrong valaue for phy_utmi_width\n"); -+ DWC_WARN("phy_utmi_width must be 8 or 16\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ core_if->core_params->phy_utmi_width = val; -+ return 0; -+} -+ -+int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->phy_utmi_width; -+} -+ -+int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if, int32_t val) -+{ -+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { -+ DWC_WARN("Wrong valaue for ulpi_fs_ls\n"); -+ DWC_WARN("ulpi_fs_ls must be 0 or 1\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ core_if->core_params->ulpi_fs_ls = val; -+ return 0; -+} -+ -+int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->ulpi_fs_ls; -+} -+ -+int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val) -+{ -+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { -+ DWC_WARN("Wrong valaue for ts_dline\n"); -+ DWC_WARN("ts_dline must be 0 or 1\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ core_if->core_params->ts_dline = val; -+ return 0; -+} -+ -+int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->ts_dline; -+} -+ -+int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if, int32_t val) -+{ -+ int retval = 0; -+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { -+ DWC_WARN("Wrong valaue for i2c_enable\n"); -+ DWC_WARN("i2c_enable must be 0 or 1\n"); -+ return -DWC_E_INVALID; -+ } -+#ifndef NO_FS_PHY_HW_CHECK -+ if (val == 1 && core_if->hwcfg3.b.i2c == 0) { -+ if (dwc_otg_param_initialized(core_if->core_params->i2c_enable)) { -+ DWC_ERROR -+ ("%d invalid for i2c_enable. Check HW configuration.\n", -+ val); -+ } -+ val = 0; -+ retval = -DWC_E_INVALID; -+ } -+#endif -+ -+ core_if->core_params->i2c_enable = val; -+ return retval; -+} -+ -+int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->i2c_enable; -+} -+ -+int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if, -+ int32_t val, int fifo_num) -+{ -+ int retval = 0; -+ -+ if (DWC_OTG_PARAM_TEST(val, 4, 768)) { -+ DWC_WARN("Wrong value for dev_perio_tx_fifo_size\n"); -+ DWC_WARN("dev_perio_tx_fifo_size must be 4-768\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ if (val > -+ (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]))) { -+ if (dwc_otg_param_initialized -+ (core_if->core_params->dev_perio_tx_fifo_size[fifo_num])) { -+ DWC_ERROR -+ ("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", -+ val, fifo_num); -+ } -+ val = (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num])); -+ retval = -DWC_E_INVALID; -+ } -+ -+ core_if->core_params->dev_perio_tx_fifo_size[fifo_num] = val; -+ return retval; -+} -+ -+int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if, -+ int fifo_num) -+{ -+ return core_if->core_params->dev_perio_tx_fifo_size[fifo_num]; -+} -+ -+int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if, -+ int32_t val) -+{ -+ int retval = 0; -+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { -+ DWC_WARN("Wrong valaue for en_multiple_tx_fifo,\n"); -+ DWC_WARN("en_multiple_tx_fifo must be 0 or 1\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ if (val == 1 && core_if->hwcfg4.b.ded_fifo_en == 0) { -+ if (dwc_otg_param_initialized -+ (core_if->core_params->en_multiple_tx_fifo)) { -+ DWC_ERROR -+ ("%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n", -+ val); -+ } -+ val = 0; -+ retval = -DWC_E_INVALID; -+ } -+ -+ core_if->core_params->en_multiple_tx_fifo = val; -+ return retval; -+} -+ -+int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->en_multiple_tx_fifo; -+} -+ -+int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val, -+ int fifo_num) -+{ -+ int retval = 0; -+ -+ if (DWC_OTG_PARAM_TEST(val, 4, 768)) { -+ DWC_WARN("Wrong value for dev_tx_fifo_size\n"); -+ DWC_WARN("dev_tx_fifo_size must be 4-768\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ if (val > -+ (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]))) { -+ if (dwc_otg_param_initialized -+ (core_if->core_params->dev_tx_fifo_size[fifo_num])) { -+ DWC_ERROR -+ ("`%d' invalid for parameter `dev_tx_fifo_size_%d'. Check HW configuration.\n", -+ val, fifo_num); -+ } -+ val = (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num])); -+ retval = -DWC_E_INVALID; -+ } -+ -+ core_if->core_params->dev_tx_fifo_size[fifo_num] = val; -+ return retval; -+} -+ -+int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, -+ int fifo_num) -+{ -+ return core_if->core_params->dev_tx_fifo_size[fifo_num]; -+} -+ -+int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val) -+{ -+ int retval = 0; -+ -+ if (DWC_OTG_PARAM_TEST(val, 0, 7)) { -+ DWC_WARN("Wrong value for thr_ctl\n"); -+ DWC_WARN("thr_ctl must be 0-7\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ if ((val != 0) && -+ (!dwc_otg_get_param_dma_enable(core_if) || -+ !core_if->hwcfg4.b.ded_fifo_en)) { -+ if (dwc_otg_param_initialized(core_if->core_params->thr_ctl)) { -+ DWC_ERROR -+ ("%d invalid for parameter thr_ctl. Check HW configuration.\n", -+ val); -+ } -+ val = 0; -+ retval = -DWC_E_INVALID; -+ } -+ -+ core_if->core_params->thr_ctl = val; -+ return retval; -+} -+ -+int32_t dwc_otg_get_param_thr_ctl(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->thr_ctl; -+} -+ -+int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if, int32_t val) -+{ -+ int retval = 0; -+ -+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { -+ DWC_WARN("Wrong value for lpm_enable\n"); -+ DWC_WARN("lpm_enable must be 0 or 1\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ if (val && !core_if->hwcfg3.b.otg_lpm_en) { -+ if (dwc_otg_param_initialized(core_if->core_params->lpm_enable)) { -+ DWC_ERROR -+ ("%d invalid for parameter lpm_enable. Check HW configuration.\n", -+ val); -+ } -+ val = 0; -+ retval = -DWC_E_INVALID; -+ } -+ -+ core_if->core_params->lpm_enable = val; -+ return retval; -+} -+ -+int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->lpm_enable; -+} -+ -+int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if, int32_t val) -+{ -+ if (DWC_OTG_PARAM_TEST(val, 8, 128)) { -+ DWC_WARN("Wrong valaue for tx_thr_length\n"); -+ DWC_WARN("tx_thr_length must be 8 - 128\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ core_if->core_params->tx_thr_length = val; -+ return 0; -+} -+ -+int32_t dwc_otg_get_param_tx_thr_length(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->tx_thr_length; -+} -+ -+int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if, int32_t val) -+{ -+ if (DWC_OTG_PARAM_TEST(val, 8, 128)) { -+ DWC_WARN("Wrong valaue for rx_thr_length\n"); -+ DWC_WARN("rx_thr_length must be 8 - 128\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ core_if->core_params->rx_thr_length = val; -+ return 0; -+} -+ -+int32_t dwc_otg_get_param_rx_thr_length(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->rx_thr_length; -+} -+ -+int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if, int32_t val) -+{ -+ if (DWC_OTG_PARAM_TEST(val, 1, 1) && -+ DWC_OTG_PARAM_TEST(val, 4, 4) && -+ DWC_OTG_PARAM_TEST(val, 8, 8) && -+ DWC_OTG_PARAM_TEST(val, 16, 16) && -+ DWC_OTG_PARAM_TEST(val, 32, 32) && -+ DWC_OTG_PARAM_TEST(val, 64, 64) && -+ DWC_OTG_PARAM_TEST(val, 128, 128) && -+ DWC_OTG_PARAM_TEST(val, 256, 256)) { -+ DWC_WARN("`%d' invalid for parameter `dma_burst_size'\n", val); -+ return -DWC_E_INVALID; -+ } -+ core_if->core_params->dma_burst_size = val; -+ return 0; -+} -+ -+int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->dma_burst_size; -+} -+ -+int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if, int32_t val) -+{ -+ int retval = 0; -+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { -+ DWC_WARN("`%d' invalid for parameter `pti_enable'\n", val); -+ return -DWC_E_INVALID; -+ } -+ if (val && (core_if->snpsid < OTG_CORE_REV_2_72a)) { -+ if (dwc_otg_param_initialized(core_if->core_params->pti_enable)) { -+ DWC_ERROR -+ ("%d invalid for parameter pti_enable. Check HW configuration.\n", -+ val); -+ } -+ retval = -DWC_E_INVALID; -+ val = 0; -+ } -+ core_if->core_params->pti_enable = val; -+ return retval; -+} -+ -+int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->pti_enable; -+} -+ -+int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if, int32_t val) -+{ -+ int retval = 0; -+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { -+ DWC_WARN("`%d' invalid for parameter `mpi_enable'\n", val); -+ return -DWC_E_INVALID; -+ } -+ if (val && (core_if->hwcfg2.b.multi_proc_int == 0)) { -+ if (dwc_otg_param_initialized(core_if->core_params->mpi_enable)) { -+ DWC_ERROR -+ ("%d invalid for parameter mpi_enable. Check HW configuration.\n", -+ val); -+ } -+ retval = -DWC_E_INVALID; -+ val = 0; -+ } -+ core_if->core_params->mpi_enable = val; -+ return retval; -+} -+ -+int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->mpi_enable; -+} -+ -+int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if, int32_t val) -+{ -+ int retval = 0; -+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { -+ DWC_WARN("`%d' invalid for parameter `adp_enable'\n", val); -+ return -DWC_E_INVALID; -+ } -+ if (val && (core_if->hwcfg3.b.adp_supp == 0)) { -+ if (dwc_otg_param_initialized -+ (core_if->core_params->adp_supp_enable)) { -+ DWC_ERROR -+ ("%d invalid for parameter adp_enable. Check HW configuration.\n", -+ val); -+ } -+ retval = -DWC_E_INVALID; -+ val = 0; -+ } -+ core_if->core_params->adp_supp_enable = val; -+ /*Set OTG version 2.0 in case of enabling ADP*/ -+ if (val) -+ dwc_otg_set_param_otg_ver(core_if, 1); -+ -+ return retval; -+} -+ -+int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->adp_supp_enable; -+} -+ -+int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if, int32_t val) -+{ -+ int retval = 0; -+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { -+ DWC_WARN("`%d' invalid for parameter `ic_usb_cap'\n", val); -+ DWC_WARN("ic_usb_cap must be 0 or 1\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ if (val && (core_if->hwcfg2.b.otg_enable_ic_usb == 0)) { -+ if (dwc_otg_param_initialized(core_if->core_params->ic_usb_cap)) { -+ DWC_ERROR -+ ("%d invalid for parameter ic_usb_cap. Check HW configuration.\n", -+ val); -+ } -+ retval = -DWC_E_INVALID; -+ val = 0; -+ } -+ core_if->core_params->ic_usb_cap = val; -+ return retval; -+} -+ -+int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->ic_usb_cap; -+} -+ -+int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if, int32_t val) -+{ -+ int retval = 0; -+ int valid = 1; -+ -+ if (DWC_OTG_PARAM_TEST(val, 0, 3)) { -+ DWC_WARN("`%d' invalid for parameter `ahb_thr_ratio'\n", val); -+ DWC_WARN("ahb_thr_ratio must be 0 - 3\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ if (val -+ && (core_if->snpsid < OTG_CORE_REV_2_81a -+ || !dwc_otg_get_param_thr_ctl(core_if))) { -+ valid = 0; -+ } else if (val -+ && ((dwc_otg_get_param_tx_thr_length(core_if) / (1 << val)) < -+ 4)) { -+ valid = 0; -+ } -+ if (valid == 0) { -+ if (dwc_otg_param_initialized -+ (core_if->core_params->ahb_thr_ratio)) { -+ DWC_ERROR -+ ("%d invalid for parameter ahb_thr_ratio. Check HW configuration.\n", -+ val); -+ } -+ retval = -DWC_E_INVALID; -+ val = 0; -+ } -+ -+ core_if->core_params->ahb_thr_ratio = val; -+ return retval; -+} -+ -+int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->ahb_thr_ratio; -+} -+ -+int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if, int32_t val) -+{ -+ int retval = 0; -+ int valid = 1; -+ hwcfg4_data_t hwcfg4 = {.d32 = 0 }; -+ hwcfg4.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4); -+ -+ if (DWC_OTG_PARAM_TEST(val, 0, 3)) { -+ DWC_WARN("`%d' invalid for parameter `power_down'\n", val); -+ DWC_WARN("power_down must be 0 - 2\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ if ((val == 2) && (core_if->snpsid < OTG_CORE_REV_2_91a)) { -+ valid = 0; -+ } -+ if ((val == 3) -+ && ((core_if->snpsid < OTG_CORE_REV_3_00a) -+ || (hwcfg4.b.xhiber == 0))) { -+ valid = 0; -+ } -+ if (valid == 0) { -+ if (dwc_otg_param_initialized(core_if->core_params->power_down)) { -+ DWC_ERROR -+ ("%d invalid for parameter power_down. Check HW configuration.\n", -+ val); -+ } -+ retval = -DWC_E_INVALID; -+ val = 0; -+ } -+ core_if->core_params->power_down = val; -+ return retval; -+} -+ -+int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->power_down; -+} -+ -+int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if, int32_t val) -+{ -+ int retval = 0; -+ int valid = 1; -+ -+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { -+ DWC_WARN("`%d' invalid for parameter `reload_ctl'\n", val); -+ DWC_WARN("reload_ctl must be 0 or 1\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_92a)) { -+ valid = 0; -+ } -+ if (valid == 0) { -+ if (dwc_otg_param_initialized(core_if->core_params->reload_ctl)) { -+ DWC_ERROR("%d invalid for parameter reload_ctl." -+ "Check HW configuration.\n", val); -+ } -+ retval = -DWC_E_INVALID; -+ val = 0; -+ } -+ core_if->core_params->reload_ctl = val; -+ return retval; -+} -+ -+int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->reload_ctl; -+} -+ -+int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if, int32_t val) -+{ -+ int retval = 0; -+ int valid = 1; -+ -+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { -+ DWC_WARN("`%d' invalid for parameter `dev_out_nak'\n", val); -+ DWC_WARN("dev_out_nak must be 0 or 1\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_93a) || -+ !(core_if->core_params->dma_desc_enable))) { -+ valid = 0; -+ } -+ if (valid == 0) { -+ if (dwc_otg_param_initialized(core_if->core_params->dev_out_nak)) { -+ DWC_ERROR("%d invalid for parameter dev_out_nak." -+ "Check HW configuration.\n", val); -+ } -+ retval = -DWC_E_INVALID; -+ val = 0; -+ } -+ core_if->core_params->dev_out_nak = val; -+ return retval; -+} -+ -+int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->dev_out_nak; -+} -+ -+int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if, int32_t val) -+{ -+ int retval = 0; -+ int valid = 1; -+ -+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { -+ DWC_WARN("`%d' invalid for parameter `cont_on_bna'\n", val); -+ DWC_WARN("cont_on_bna must be 0 or 1\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_94a) || -+ !(core_if->core_params->dma_desc_enable))) { -+ valid = 0; -+ } -+ if (valid == 0) { -+ if (dwc_otg_param_initialized(core_if->core_params->cont_on_bna)) { -+ DWC_ERROR("%d invalid for parameter cont_on_bna." -+ "Check HW configuration.\n", val); -+ } -+ retval = -DWC_E_INVALID; -+ val = 0; -+ } -+ core_if->core_params->cont_on_bna = val; -+ return retval; -+} -+ -+int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->cont_on_bna; -+} -+ -+int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if, int32_t val) -+{ -+ int retval = 0; -+ int valid = 1; -+ -+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { -+ DWC_WARN("`%d' invalid for parameter `ahb_single'\n", val); -+ DWC_WARN("ahb_single must be 0 or 1\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_94a)) { -+ valid = 0; -+ } -+ if (valid == 0) { -+ if (dwc_otg_param_initialized(core_if->core_params->ahb_single)) { -+ DWC_ERROR("%d invalid for parameter ahb_single." -+ "Check HW configuration.\n", val); -+ } -+ retval = -DWC_E_INVALID; -+ val = 0; -+ } -+ core_if->core_params->ahb_single = val; -+ return retval; -+} -+ -+int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->ahb_single; -+} -+ -+int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val) -+{ -+ int retval = 0; -+ -+ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { -+ DWC_WARN("`%d' invalid for parameter `otg_ver'\n", val); -+ DWC_WARN -+ ("otg_ver must be 0(for OTG 1.3 support) or 1(for OTG 2.0 support)\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ core_if->core_params->otg_ver = val; -+ return retval; -+} -+ -+int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->core_params->otg_ver; -+} -+ -+uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if) -+{ -+ gotgctl_data_t otgctl; -+ otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl); -+ return otgctl.b.hstnegscs; -+} -+ -+uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if) -+{ -+ gotgctl_data_t otgctl; -+ otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl); -+ return otgctl.b.sesreqscs; -+} -+ -+void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val) -+{ -+ if(core_if->otg_ver == 0) { -+ gotgctl_data_t otgctl; -+ otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl); -+ otgctl.b.hnpreq = val; -+ DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, otgctl.d32); -+ } else { -+ core_if->otg_sts = val; -+ } -+} -+ -+uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->snpsid; -+} -+ -+uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if) -+{ -+ gintsts_data_t gintsts; -+ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts); -+ return gintsts.b.curmode; -+} -+ -+uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if) -+{ -+ gusbcfg_data_t usbcfg; -+ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); -+ return usbcfg.b.hnpcap; -+} -+ -+void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val) -+{ -+ gusbcfg_data_t usbcfg; -+ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); -+ usbcfg.b.hnpcap = val; -+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32); -+} -+ -+uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if) -+{ -+ gusbcfg_data_t usbcfg; -+ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); -+ return usbcfg.b.srpcap; -+} -+ -+void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val) -+{ -+ gusbcfg_data_t usbcfg; -+ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); -+ usbcfg.b.srpcap = val; -+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32); -+} -+ -+uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if) -+{ -+ dcfg_data_t dcfg; -+ /* originally: dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); */ -+ -+ dcfg.d32 = -1; //GRAYG -+ DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)\n", __func__, core_if); -+ if (NULL == core_if) -+ DWC_ERROR("reg request with NULL core_if\n"); -+ DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)->dev_if(%p)\n", __func__, -+ core_if, core_if->dev_if); -+ if (NULL == core_if->dev_if) -+ DWC_ERROR("reg request with NULL dev_if\n"); -+ DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)->dev_if(%p)->" -+ "dev_global_regs(%p)\n", __func__, -+ core_if, core_if->dev_if, -+ core_if->dev_if->dev_global_regs); -+ if (NULL == core_if->dev_if->dev_global_regs) -+ DWC_ERROR("reg request with NULL dev_global_regs\n"); -+ else { -+ DWC_DEBUGPL(DBG_CILV, "%s - &core_if(%p)->dev_if(%p)->" -+ "dev_global_regs(%p)->dcfg = %p\n", __func__, -+ core_if, core_if->dev_if, -+ core_if->dev_if->dev_global_regs, -+ &core_if->dev_if->dev_global_regs->dcfg); -+ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); -+ } -+ return dcfg.b.devspd; -+} -+ -+void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val) -+{ -+ dcfg_data_t dcfg; -+ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); -+ dcfg.b.devspd = val; -+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32); -+} -+ -+uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if) -+{ -+ hprt0_data_t hprt0; -+ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0); -+ return hprt0.b.prtconnsts; -+} -+ -+uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if) -+{ -+ dsts_data_t dsts; -+ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); -+ return dsts.b.enumspd; -+} -+ -+uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if) -+{ -+ hprt0_data_t hprt0; -+ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0); -+ return hprt0.b.prtpwr; -+ -+} -+ -+uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if) -+{ -+ return core_if->hibernation_suspend; -+} -+ -+void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val) -+{ -+ hprt0_data_t hprt0; -+ hprt0.d32 = dwc_otg_read_hprt0(core_if); -+ hprt0.b.prtpwr = val; -+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); -+} -+ -+uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if) -+{ -+ hprt0_data_t hprt0; -+ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0); -+ return hprt0.b.prtsusp; -+ -+} -+ -+void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val) -+{ -+ hprt0_data_t hprt0; -+ hprt0.d32 = dwc_otg_read_hprt0(core_if); -+ hprt0.b.prtsusp = val; -+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); -+} -+ -+uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if) -+{ -+ hfir_data_t hfir; -+ hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir); -+ return hfir.b.frint; -+ -+} -+ -+void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val) -+{ -+ hfir_data_t hfir; -+ uint32_t fram_int; -+ fram_int = calc_frame_interval(core_if); -+ hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir); -+ if (!core_if->core_params->reload_ctl) { -+ DWC_WARN("\nCannot reload HFIR register.HFIR.HFIRRldCtrl bit is" -+ "not set to 1.\nShould load driver with reload_ctl=1" -+ " module parameter\n"); -+ return; -+ } -+ switch (fram_int) { -+ case 3750: -+ if ((val < 3350) || (val > 4150)) { -+ DWC_WARN("HFIR interval for HS core and 30 MHz" -+ "clock freq should be from 3350 to 4150\n"); -+ return; -+ } -+ break; -+ case 30000: -+ if ((val < 26820) || (val > 33180)) { -+ DWC_WARN("HFIR interval for FS/LS core and 30 MHz" -+ "clock freq should be from 26820 to 33180\n"); -+ return; -+ } -+ break; -+ case 6000: -+ if ((val < 5360) || (val > 6640)) { -+ DWC_WARN("HFIR interval for HS core and 48 MHz" -+ "clock freq should be from 5360 to 6640\n"); -+ return; -+ } -+ break; -+ case 48000: -+ if ((val < 42912) || (val > 53088)) { -+ DWC_WARN("HFIR interval for FS/LS core and 48 MHz" -+ "clock freq should be from 42912 to 53088\n"); -+ return; -+ } -+ break; -+ case 7500: -+ if ((val < 6700) || (val > 8300)) { -+ DWC_WARN("HFIR interval for HS core and 60 MHz" -+ "clock freq should be from 6700 to 8300\n"); -+ return; -+ } -+ break; -+ case 60000: -+ if ((val < 53640) || (val > 65536)) { -+ DWC_WARN("HFIR interval for FS/LS core and 60 MHz" -+ "clock freq should be from 53640 to 65536\n"); -+ return; -+ } -+ break; -+ default: -+ DWC_WARN("Unknown frame interval\n"); -+ return; -+ break; -+ -+ } -+ hfir.b.frint = val; -+ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hfir.d32); -+} -+ -+uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if) -+{ -+ hcfg_data_t hcfg; -+ hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg); -+ return hcfg.b.modechtimen; -+ -+} -+ -+void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val) -+{ -+ hcfg_data_t hcfg; -+ hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg); -+ hcfg.b.modechtimen = val; -+ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32); -+} -+ -+void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val) -+{ -+ hprt0_data_t hprt0; -+ hprt0.d32 = dwc_otg_read_hprt0(core_if); -+ hprt0.b.prtres = val; -+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); -+} -+ -+uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if) -+{ -+ dctl_data_t dctl; -+ dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl); -+ return dctl.b.rmtwkupsig; -+} -+ -+uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if) -+{ -+ glpmcfg_data_t lpmcfg; -+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); -+ -+ DWC_ASSERT(! -+ ((core_if->lx_state == DWC_OTG_L1) ^ lpmcfg.b.prt_sleep_sts), -+ "lx_state = %d, lmpcfg.prt_sleep_sts = %d\n", -+ core_if->lx_state, lpmcfg.b.prt_sleep_sts); -+ -+ return lpmcfg.b.prt_sleep_sts; -+} -+ -+uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if) -+{ -+ glpmcfg_data_t lpmcfg; -+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); -+ return lpmcfg.b.rem_wkup_en; -+} -+ -+uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if) -+{ -+ glpmcfg_data_t lpmcfg; -+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); -+ return lpmcfg.b.appl_resp; -+} -+ -+void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val) -+{ -+ glpmcfg_data_t lpmcfg; -+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); -+ lpmcfg.b.appl_resp = val; -+ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32); -+} -+ -+uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if) -+{ -+ glpmcfg_data_t lpmcfg; -+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); -+ return lpmcfg.b.hsic_connect; -+} -+ -+void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val) -+{ -+ glpmcfg_data_t lpmcfg; -+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); -+ lpmcfg.b.hsic_connect = val; -+ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32); -+} -+ -+uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if) -+{ -+ glpmcfg_data_t lpmcfg; -+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); -+ return lpmcfg.b.inv_sel_hsic; -+ -+} -+ -+void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val) -+{ -+ glpmcfg_data_t lpmcfg; -+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); -+ lpmcfg.b.inv_sel_hsic = val; -+ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32); -+} -+ -+uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if) -+{ -+ return DWC_READ_REG32(&core_if->core_global_regs->gotgctl); -+} -+ -+void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val) -+{ -+ DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, val); -+} -+ -+uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if) -+{ -+ return DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); -+} -+ -+void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val) -+{ -+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, val); -+} -+ -+uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if) -+{ -+ return DWC_READ_REG32(&core_if->core_global_regs->grxfsiz); -+} -+ -+void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val) -+{ -+ DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, val); -+} -+ -+uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if) -+{ -+ return DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz); -+} -+ -+void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val) -+{ -+ DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz, val); -+} -+ -+uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if) -+{ -+ return DWC_READ_REG32(&core_if->core_global_regs->gpvndctl); -+} -+ -+void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val) -+{ -+ DWC_WRITE_REG32(&core_if->core_global_regs->gpvndctl, val); -+} -+ -+uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if) -+{ -+ return DWC_READ_REG32(&core_if->core_global_regs->ggpio); -+} -+ -+void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val) -+{ -+ DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, val); -+} -+ -+uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if) -+{ -+ return DWC_READ_REG32(core_if->host_if->hprt0); -+ -+} -+ -+void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val) -+{ -+ DWC_WRITE_REG32(core_if->host_if->hprt0, val); -+} -+ -+uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if) -+{ -+ return DWC_READ_REG32(&core_if->core_global_regs->guid); -+} -+ -+void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val) -+{ -+ DWC_WRITE_REG32(&core_if->core_global_regs->guid, val); -+} -+ -+uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if) -+{ -+ return DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz); -+} -+ -+uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if) -+{ -+ return ((core_if->otg_ver == 1) ? (uint16_t)0x0200 : (uint16_t)0x0103); -+} -+ -+/** -+ * Start the SRP timer to detect when the SRP does not complete within -+ * 6 seconds. -+ * -+ * @param core_if the pointer to core_if strucure. -+ */ -+void dwc_otg_pcd_start_srp_timer(dwc_otg_core_if_t * core_if) -+{ -+ core_if->srp_timer_started = 1; -+ DWC_TIMER_SCHEDULE(core_if->srp_timer, 6000 /* 6 secs */ ); -+} -+ -+void dwc_otg_initiate_srp(dwc_otg_core_if_t * core_if) -+{ -+ uint32_t *addr = (uint32_t *) & (core_if->core_global_regs->gotgctl); -+ gotgctl_data_t mem; -+ gotgctl_data_t val; -+ -+ val.d32 = DWC_READ_REG32(addr); -+ if (val.b.sesreq) { -+ DWC_ERROR("Session Request Already active!\n"); -+ return; -+ } -+ -+ DWC_INFO("Session Request Initated\n"); //NOTICE -+ mem.d32 = DWC_READ_REG32(addr); -+ mem.b.sesreq = 1; -+ DWC_WRITE_REG32(addr, mem.d32); -+ -+ /* Start the SRP timer */ -+ dwc_otg_pcd_start_srp_timer(core_if); -+ return; -+} -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_cil.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cil.h ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_cil.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cil.h 2015-11-29 09:42:39.919098694 +0100 -@@ -0,0 +1,1464 @@ -+/* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $ -+ * $Revision: #123 $ -+ * $Date: 2012/08/10 $ -+ * $Change: 2047372 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+ -+#if !defined(__DWC_CIL_H__) -+#define __DWC_CIL_H__ -+ -+#include "dwc_list.h" -+#include "dwc_otg_dbg.h" -+#include "dwc_otg_regs.h" -+ -+#include "dwc_otg_core_if.h" -+#include "dwc_otg_adp.h" -+ -+/** -+ * @file -+ * This file contains the interface to the Core Interface Layer. -+ */ -+ -+#ifdef DWC_UTE_CFI -+ -+#define MAX_DMA_DESCS_PER_EP 256 -+ -+/** -+ * Enumeration for the data buffer mode -+ */ -+typedef enum _data_buffer_mode { -+ BM_STANDARD = 0, /* data buffer is in normal mode */ -+ BM_SG = 1, /* data buffer uses the scatter/gather mode */ -+ BM_CONCAT = 2, /* data buffer uses the concatenation mode */ -+ BM_CIRCULAR = 3, /* data buffer uses the circular DMA mode */ -+ BM_ALIGN = 4 /* data buffer is in buffer alignment mode */ -+} data_buffer_mode_e; -+#endif //DWC_UTE_CFI -+ -+/** Macros defined for DWC OTG HW Release version */ -+ -+#define OTG_CORE_REV_2_60a 0x4F54260A -+#define OTG_CORE_REV_2_71a 0x4F54271A -+#define OTG_CORE_REV_2_72a 0x4F54272A -+#define OTG_CORE_REV_2_80a 0x4F54280A -+#define OTG_CORE_REV_2_81a 0x4F54281A -+#define OTG_CORE_REV_2_90a 0x4F54290A -+#define OTG_CORE_REV_2_91a 0x4F54291A -+#define OTG_CORE_REV_2_92a 0x4F54292A -+#define OTG_CORE_REV_2_93a 0x4F54293A -+#define OTG_CORE_REV_2_94a 0x4F54294A -+#define OTG_CORE_REV_3_00a 0x4F54300A -+ -+/** -+ * Information for each ISOC packet. -+ */ -+typedef struct iso_pkt_info { -+ uint32_t offset; -+ uint32_t length; -+ int32_t status; -+} iso_pkt_info_t; -+ -+/** -+ * The dwc_ep structure represents the state of a single -+ * endpoint when acting in device mode. It contains the data items -+ * needed for an endpoint to be activated and transfer packets. -+ */ -+typedef struct dwc_ep { -+ /** EP number used for register address lookup */ -+ uint8_t num; -+ /** EP direction 0 = OUT */ -+ unsigned is_in:1; -+ /** EP active. */ -+ unsigned active:1; -+ -+ /** -+ * Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic -+ * Tx FIFO. If dedicated Tx FIFOs are enabled Tx FIFO # FOR IN EPs*/ -+ unsigned tx_fifo_num:4; -+ /** EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR */ -+ unsigned type:2; -+#define DWC_OTG_EP_TYPE_CONTROL 0 -+#define DWC_OTG_EP_TYPE_ISOC 1 -+#define DWC_OTG_EP_TYPE_BULK 2 -+#define DWC_OTG_EP_TYPE_INTR 3 -+ -+ /** DATA start PID for INTR and BULK EP */ -+ unsigned data_pid_start:1; -+ /** Frame (even/odd) for ISOC EP */ -+ unsigned even_odd_frame:1; -+ /** Max Packet bytes */ -+ unsigned maxpacket:11; -+ -+ /** Max Transfer size */ -+ uint32_t maxxfer; -+ -+ /** @name Transfer state */ -+ /** @{ */ -+ -+ /** -+ * Pointer to the beginning of the transfer buffer -- do not modify -+ * during transfer. -+ */ -+ -+ dwc_dma_t dma_addr; -+ -+ dwc_dma_t dma_desc_addr; -+ dwc_otg_dev_dma_desc_t *desc_addr; -+ -+ uint8_t *start_xfer_buff; -+ /** pointer to the transfer buffer */ -+ uint8_t *xfer_buff; -+ /** Number of bytes to transfer */ -+ unsigned xfer_len:19; -+ /** Number of bytes transferred. */ -+ unsigned xfer_count:19; -+ /** Sent ZLP */ -+ unsigned sent_zlp:1; -+ /** Total len for control transfer */ -+ unsigned total_len:19; -+ -+ /** stall clear flag */ -+ unsigned stall_clear_flag:1; -+ -+ /** SETUP pkt cnt rollover flag for EP0 out*/ -+ unsigned stp_rollover; -+ -+#ifdef DWC_UTE_CFI -+ /* The buffer mode */ -+ data_buffer_mode_e buff_mode; -+ -+ /* The chain of DMA descriptors. -+ * MAX_DMA_DESCS_PER_EP will be allocated for each active EP. -+ */ -+ dwc_otg_dma_desc_t *descs; -+ -+ /* The DMA address of the descriptors chain start */ -+ dma_addr_t descs_dma_addr; -+ /** This variable stores the length of the last enqueued request */ -+ uint32_t cfi_req_len; -+#endif //DWC_UTE_CFI -+ -+/** Max DMA Descriptor count for any EP */ -+#define MAX_DMA_DESC_CNT 256 -+ /** Allocated DMA Desc count */ -+ uint32_t desc_cnt; -+ -+ /** bInterval */ -+ uint32_t bInterval; -+ /** Next frame num to setup next ISOC transfer */ -+ uint32_t frame_num; -+ /** Indicates SOF number overrun in DSTS */ -+ uint8_t frm_overrun; -+ -+#ifdef DWC_UTE_PER_IO -+ /** Next frame num for which will be setup DMA Desc */ -+ uint32_t xiso_frame_num; -+ /** bInterval */ -+ uint32_t xiso_bInterval; -+ /** Count of currently active transfers - shall be either 0 or 1 */ -+ int xiso_active_xfers; -+ int xiso_queued_xfers; -+#endif -+#ifdef DWC_EN_ISOC -+ /** -+ * Variables specific for ISOC EPs -+ * -+ */ -+ /** DMA addresses of ISOC buffers */ -+ dwc_dma_t dma_addr0; -+ dwc_dma_t dma_addr1; -+ -+ dwc_dma_t iso_dma_desc_addr; -+ dwc_otg_dev_dma_desc_t *iso_desc_addr; -+ -+ /** pointer to the transfer buffers */ -+ uint8_t *xfer_buff0; -+ uint8_t *xfer_buff1; -+ -+ /** number of ISOC Buffer is processing */ -+ uint32_t proc_buf_num; -+ /** Interval of ISOC Buffer processing */ -+ uint32_t buf_proc_intrvl; -+ /** Data size for regular frame */ -+ uint32_t data_per_frame; -+ -+ /* todo - pattern data support is to be implemented in the future */ -+ /** Data size for pattern frame */ -+ uint32_t data_pattern_frame; -+ /** Frame number of pattern data */ -+ uint32_t sync_frame; -+ -+ /** bInterval */ -+ uint32_t bInterval; -+ /** ISO Packet number per frame */ -+ uint32_t pkt_per_frm; -+ /** Next frame num for which will be setup DMA Desc */ -+ uint32_t next_frame; -+ /** Number of packets per buffer processing */ -+ uint32_t pkt_cnt; -+ /** Info for all isoc packets */ -+ iso_pkt_info_t *pkt_info; -+ /** current pkt number */ -+ uint32_t cur_pkt; -+ /** current pkt number */ -+ uint8_t *cur_pkt_addr; -+ /** current pkt number */ -+ uint32_t cur_pkt_dma_addr; -+#endif /* DWC_EN_ISOC */ -+ -+/** @} */ -+} dwc_ep_t; -+ -+/* -+ * Reasons for halting a host channel. -+ */ -+typedef enum dwc_otg_halt_status { -+ DWC_OTG_HC_XFER_NO_HALT_STATUS, -+ DWC_OTG_HC_XFER_COMPLETE, -+ DWC_OTG_HC_XFER_URB_COMPLETE, -+ DWC_OTG_HC_XFER_ACK, -+ DWC_OTG_HC_XFER_NAK, -+ DWC_OTG_HC_XFER_NYET, -+ DWC_OTG_HC_XFER_STALL, -+ DWC_OTG_HC_XFER_XACT_ERR, -+ DWC_OTG_HC_XFER_FRAME_OVERRUN, -+ DWC_OTG_HC_XFER_BABBLE_ERR, -+ DWC_OTG_HC_XFER_DATA_TOGGLE_ERR, -+ DWC_OTG_HC_XFER_AHB_ERR, -+ DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE, -+ DWC_OTG_HC_XFER_URB_DEQUEUE -+} dwc_otg_halt_status_e; -+ -+/** -+ * Host channel descriptor. This structure represents the state of a single -+ * host channel when acting in host mode. It contains the data items needed to -+ * transfer packets to an endpoint via a host channel. -+ */ -+typedef struct dwc_hc { -+ /** Host channel number used for register address lookup */ -+ uint8_t hc_num; -+ -+ /** Device to access */ -+ unsigned dev_addr:7; -+ -+ /** EP to access */ -+ unsigned ep_num:4; -+ -+ /** EP direction. 0: OUT, 1: IN */ -+ unsigned ep_is_in:1; -+ -+ /** -+ * EP speed. -+ * One of the following values: -+ * - DWC_OTG_EP_SPEED_LOW -+ * - DWC_OTG_EP_SPEED_FULL -+ * - DWC_OTG_EP_SPEED_HIGH -+ */ -+ unsigned speed:2; -+#define DWC_OTG_EP_SPEED_LOW 0 -+#define DWC_OTG_EP_SPEED_FULL 1 -+#define DWC_OTG_EP_SPEED_HIGH 2 -+ -+ /** -+ * Endpoint type. -+ * One of the following values: -+ * - DWC_OTG_EP_TYPE_CONTROL: 0 -+ * - DWC_OTG_EP_TYPE_ISOC: 1 -+ * - DWC_OTG_EP_TYPE_BULK: 2 -+ * - DWC_OTG_EP_TYPE_INTR: 3 -+ */ -+ unsigned ep_type:2; -+ -+ /** Max packet size in bytes */ -+ unsigned max_packet:11; -+ -+ /** -+ * PID for initial transaction. -+ * 0: DATA0,
-+ * 1: DATA2,
-+ * 2: DATA1,
-+ * 3: MDATA (non-Control EP), -+ * SETUP (Control EP) -+ */ -+ unsigned data_pid_start:2; -+#define DWC_OTG_HC_PID_DATA0 0 -+#define DWC_OTG_HC_PID_DATA2 1 -+#define DWC_OTG_HC_PID_DATA1 2 -+#define DWC_OTG_HC_PID_MDATA 3 -+#define DWC_OTG_HC_PID_SETUP 3 -+ -+ /** Number of periodic transactions per (micro)frame */ -+ unsigned multi_count:2; -+ -+ /** @name Transfer State */ -+ /** @{ */ -+ -+ /** Pointer to the current transfer buffer position. */ -+ uint8_t *xfer_buff; -+ /** -+ * In Buffer DMA mode this buffer will be used -+ * if xfer_buff is not DWORD aligned. -+ */ -+ dwc_dma_t align_buff; -+ /** Total number of bytes to transfer. */ -+ uint32_t xfer_len; -+ /** Number of bytes transferred so far. */ -+ uint32_t xfer_count; -+ /** Packet count at start of transfer.*/ -+ uint16_t start_pkt_count; -+ -+ /** -+ * Flag to indicate whether the transfer has been started. Set to 1 if -+ * it has been started, 0 otherwise. -+ */ -+ uint8_t xfer_started; -+ -+ /** -+ * Set to 1 to indicate that a PING request should be issued on this -+ * channel. If 0, process normally. -+ */ -+ uint8_t do_ping; -+ -+ /** -+ * Set to 1 to indicate that the error count for this transaction is -+ * non-zero. Set to 0 if the error count is 0. -+ */ -+ uint8_t error_state; -+ -+ /** -+ * Set to 1 to indicate that this channel should be halted the next -+ * time a request is queued for the channel. This is necessary in -+ * slave mode if no request queue space is available when an attempt -+ * is made to halt the channel. -+ */ -+ uint8_t halt_on_queue; -+ -+ /** -+ * Set to 1 if the host channel has been halted, but the core is not -+ * finished flushing queued requests. Otherwise 0. -+ */ -+ uint8_t halt_pending; -+ -+ /** -+ * Reason for halting the host channel. -+ */ -+ dwc_otg_halt_status_e halt_status; -+ -+ /* -+ * Split settings for the host channel -+ */ -+ uint8_t do_split; /**< Enable split for the channel */ -+ uint8_t complete_split; /**< Enable complete split */ -+ uint8_t hub_addr; /**< Address of high speed hub */ -+ -+ uint8_t port_addr; /**< Port of the low/full speed device */ -+ /** Split transaction position -+ * One of the following values: -+ * - DWC_HCSPLIT_XACTPOS_MID -+ * - DWC_HCSPLIT_XACTPOS_BEGIN -+ * - DWC_HCSPLIT_XACTPOS_END -+ * - DWC_HCSPLIT_XACTPOS_ALL */ -+ uint8_t xact_pos; -+ -+ /** Set when the host channel does a short read. */ -+ uint8_t short_read; -+ -+ /** -+ * Number of requests issued for this channel since it was assigned to -+ * the current transfer (not counting PINGs). -+ */ -+ uint8_t requests; -+ -+ /** -+ * Queue Head for the transfer being processed by this channel. -+ */ -+ struct dwc_otg_qh *qh; -+ -+ /** @} */ -+ -+ /** Entry in list of host channels. */ -+ DWC_CIRCLEQ_ENTRY(dwc_hc) hc_list_entry; -+ -+ /** @name Descriptor DMA support */ -+ /** @{ */ -+ -+ /** Number of Transfer Descriptors */ -+ uint16_t ntd; -+ -+ /** Descriptor List DMA address */ -+ dwc_dma_t desc_list_addr; -+ -+ /** Scheduling micro-frame bitmap. */ -+ uint8_t schinfo; -+ -+ /** @} */ -+} dwc_hc_t; -+ -+/** -+ * The following parameters may be specified when starting the module. These -+ * parameters define how the DWC_otg controller should be configured. -+ */ -+typedef struct dwc_otg_core_params { -+ int32_t opt; -+ -+ /** -+ * Specifies the OTG capabilities. The driver will automatically -+ * detect the value for this parameter if none is specified. -+ * 0 - HNP and SRP capable (default) -+ * 1 - SRP Only capable -+ * 2 - No HNP/SRP capable -+ */ -+ int32_t otg_cap; -+ -+ /** -+ * Specifies whether to use slave or DMA mode for accessing the data -+ * FIFOs. The driver will automatically detect the value for this -+ * parameter if none is specified. -+ * 0 - Slave -+ * 1 - DMA (default, if available) -+ */ -+ int32_t dma_enable; -+ -+ /** -+ * When DMA mode is enabled specifies whether to use address DMA or DMA -+ * Descriptor mode for accessing the data FIFOs in device mode. The driver -+ * will automatically detect the value for this if none is specified. -+ * 0 - address DMA -+ * 1 - DMA Descriptor(default, if available) -+ */ -+ int32_t dma_desc_enable; -+ /** The DMA Burst size (applicable only for External DMA -+ * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32) -+ */ -+ int32_t dma_burst_size; /* Translate this to GAHBCFG values */ -+ -+ /** -+ * Specifies the maximum speed of operation in host and device mode. -+ * The actual speed depends on the speed of the attached device and -+ * the value of phy_type. The actual speed depends on the speed of the -+ * attached device. -+ * 0 - High Speed (default) -+ * 1 - Full Speed -+ */ -+ int32_t speed; -+ /** Specifies whether low power mode is supported when attached -+ * to a Full Speed or Low Speed device in host mode. -+ * 0 - Don't support low power mode (default) -+ * 1 - Support low power mode -+ */ -+ int32_t host_support_fs_ls_low_power; -+ -+ /** Specifies the PHY clock rate in low power mode when connected to a -+ * Low Speed device in host mode. This parameter is applicable only if -+ * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS -+ * then defaults to 6 MHZ otherwise 48 MHZ. -+ * -+ * 0 - 48 MHz -+ * 1 - 6 MHz -+ */ -+ int32_t host_ls_low_power_phy_clk; -+ -+ /** -+ * 0 - Use cC FIFO size parameters -+ * 1 - Allow dynamic FIFO sizing (default) -+ */ -+ int32_t enable_dynamic_fifo; -+ -+ /** Total number of 4-byte words in the data FIFO memory. This -+ * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic -+ * Tx FIFOs. -+ * 32 to 32768 (default 8192) -+ * Note: The total FIFO memory depth in the FPGA configuration is 8192. -+ */ -+ int32_t data_fifo_size; -+ -+ /** Number of 4-byte words in the Rx FIFO in device mode when dynamic -+ * FIFO sizing is enabled. -+ * 16 to 32768 (default 1064) -+ */ -+ int32_t dev_rx_fifo_size; -+ -+ /** Number of 4-byte words in the non-periodic Tx FIFO in device mode -+ * when dynamic FIFO sizing is enabled. -+ * 16 to 32768 (default 1024) -+ */ -+ int32_t dev_nperio_tx_fifo_size; -+ -+ /** Number of 4-byte words in each of the periodic Tx FIFOs in device -+ * mode when dynamic FIFO sizing is enabled. -+ * 4 to 768 (default 256) -+ */ -+ uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS]; -+ -+ /** Number of 4-byte words in the Rx FIFO in host mode when dynamic -+ * FIFO sizing is enabled. -+ * 16 to 32768 (default 1024) -+ */ -+ int32_t host_rx_fifo_size; -+ -+ /** Number of 4-byte words in the non-periodic Tx FIFO in host mode -+ * when Dynamic FIFO sizing is enabled in the core. -+ * 16 to 32768 (default 1024) -+ */ -+ int32_t host_nperio_tx_fifo_size; -+ -+ /** Number of 4-byte words in the host periodic Tx FIFO when dynamic -+ * FIFO sizing is enabled. -+ * 16 to 32768 (default 1024) -+ */ -+ int32_t host_perio_tx_fifo_size; -+ -+ /** The maximum transfer size supported in bytes. -+ * 2047 to 65,535 (default 65,535) -+ */ -+ int32_t max_transfer_size; -+ -+ /** The maximum number of packets in a transfer. -+ * 15 to 511 (default 511) -+ */ -+ int32_t max_packet_count; -+ -+ /** The number of host channel registers to use. -+ * 1 to 16 (default 12) -+ * Note: The FPGA configuration supports a maximum of 12 host channels. -+ */ -+ int32_t host_channels; -+ -+ /** The number of endpoints in addition to EP0 available for device -+ * mode operations. -+ * 1 to 15 (default 6 IN and OUT) -+ * Note: The FPGA configuration supports a maximum of 6 IN and OUT -+ * endpoints in addition to EP0. -+ */ -+ int32_t dev_endpoints; -+ -+ /** -+ * Specifies the type of PHY interface to use. By default, the driver -+ * will automatically detect the phy_type. -+ * -+ * 0 - Full Speed PHY -+ * 1 - UTMI+ (default) -+ * 2 - ULPI -+ */ -+ int32_t phy_type; -+ -+ /** -+ * Specifies the UTMI+ Data Width. This parameter is -+ * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI -+ * PHY_TYPE, this parameter indicates the data width between -+ * the MAC and the ULPI Wrapper.) Also, this parameter is -+ * applicable only if the OTG_HSPHY_WIDTH cC parameter was set -+ * to "8 and 16 bits", meaning that the core has been -+ * configured to work at either data path width. -+ * -+ * 8 or 16 bits (default 16) -+ */ -+ int32_t phy_utmi_width; -+ -+ /** -+ * Specifies whether the ULPI operates at double or single -+ * data rate. This parameter is only applicable if PHY_TYPE is -+ * ULPI. -+ * -+ * 0 - single data rate ULPI interface with 8 bit wide data -+ * bus (default) -+ * 1 - double data rate ULPI interface with 4 bit wide data -+ * bus -+ */ -+ int32_t phy_ulpi_ddr; -+ -+ /** -+ * Specifies whether to use the internal or external supply to -+ * drive the vbus with a ULPI phy. -+ */ -+ int32_t phy_ulpi_ext_vbus; -+ -+ /** -+ * Specifies whether to use the I2Cinterface for full speed PHY. This -+ * parameter is only applicable if PHY_TYPE is FS. -+ * 0 - No (default) -+ * 1 - Yes -+ */ -+ int32_t i2c_enable; -+ -+ int32_t ulpi_fs_ls; -+ -+ int32_t ts_dline; -+ -+ /** -+ * Specifies whether dedicated transmit FIFOs are -+ * enabled for non periodic IN endpoints in device mode -+ * 0 - No -+ * 1 - Yes -+ */ -+ int32_t en_multiple_tx_fifo; -+ -+ /** Number of 4-byte words in each of the Tx FIFOs in device -+ * mode when dynamic FIFO sizing is enabled. -+ * 4 to 768 (default 256) -+ */ -+ uint32_t dev_tx_fifo_size[MAX_TX_FIFOS]; -+ -+ /** Thresholding enable flag- -+ * bit 0 - enable non-ISO Tx thresholding -+ * bit 1 - enable ISO Tx thresholding -+ * bit 2 - enable Rx thresholding -+ */ -+ uint32_t thr_ctl; -+ -+ /** Thresholding length for Tx -+ * FIFOs in 32 bit DWORDs -+ */ -+ uint32_t tx_thr_length; -+ -+ /** Thresholding length for Rx -+ * FIFOs in 32 bit DWORDs -+ */ -+ uint32_t rx_thr_length; -+ -+ /** -+ * Specifies whether LPM (Link Power Management) support is enabled -+ */ -+ int32_t lpm_enable; -+ -+ /** Per Transfer Interrupt -+ * mode enable flag -+ * 1 - Enabled -+ * 0 - Disabled -+ */ -+ int32_t pti_enable; -+ -+ /** Multi Processor Interrupt -+ * mode enable flag -+ * 1 - Enabled -+ * 0 - Disabled -+ */ -+ int32_t mpi_enable; -+ -+ /** IS_USB Capability -+ * 1 - Enabled -+ * 0 - Disabled -+ */ -+ int32_t ic_usb_cap; -+ -+ /** AHB Threshold Ratio -+ * 2'b00 AHB Threshold = MAC Threshold -+ * 2'b01 AHB Threshold = 1/2 MAC Threshold -+ * 2'b10 AHB Threshold = 1/4 MAC Threshold -+ * 2'b11 AHB Threshold = 1/8 MAC Threshold -+ */ -+ int32_t ahb_thr_ratio; -+ -+ /** ADP Support -+ * 1 - Enabled -+ * 0 - Disabled -+ */ -+ int32_t adp_supp_enable; -+ -+ /** HFIR Reload Control -+ * 0 - The HFIR cannot be reloaded dynamically. -+ * 1 - Allow dynamic reloading of the HFIR register during runtime. -+ */ -+ int32_t reload_ctl; -+ -+ /** DCFG: Enable device Out NAK -+ * 0 - The core does not set NAK after Bulk Out transfer complete. -+ * 1 - The core sets NAK after Bulk OUT transfer complete. -+ */ -+ int32_t dev_out_nak; -+ -+ /** DCFG: Enable Continue on BNA -+ * After receiving BNA interrupt the core disables the endpoint,when the -+ * endpoint is re-enabled by the application the core starts processing -+ * 0 - from the DOEPDMA descriptor -+ * 1 - from the descriptor which received the BNA. -+ */ -+ int32_t cont_on_bna; -+ -+ /** GAHBCFG: AHB Single Support -+ * This bit when programmed supports SINGLE transfers for remainder -+ * data in a transfer for DMA mode of operation. -+ * 0 - in this case the remainder data will be sent using INCR burst size. -+ * 1 - in this case the remainder data will be sent using SINGLE burst size. -+ */ -+ int32_t ahb_single; -+ -+ /** Core Power down mode -+ * 0 - No Power Down is enabled -+ * 1 - Reserved -+ * 2 - Complete Power Down (Hibernation) -+ */ -+ int32_t power_down; -+ -+ /** OTG revision supported -+ * 0 - OTG 1.3 revision -+ * 1 - OTG 2.0 revision -+ */ -+ int32_t otg_ver; -+ -+} dwc_otg_core_params_t; -+ -+#ifdef DEBUG -+struct dwc_otg_core_if; -+typedef struct hc_xfer_info { -+ struct dwc_otg_core_if *core_if; -+ dwc_hc_t *hc; -+} hc_xfer_info_t; -+#endif -+ -+typedef struct ep_xfer_info { -+ struct dwc_otg_core_if *core_if; -+ dwc_ep_t *ep; -+ uint8_t state; -+} ep_xfer_info_t; -+/* -+ * Device States -+ */ -+typedef enum dwc_otg_lx_state { -+ /** On state */ -+ DWC_OTG_L0, -+ /** LPM sleep state*/ -+ DWC_OTG_L1, -+ /** USB suspend state*/ -+ DWC_OTG_L2, -+ /** Off state*/ -+ DWC_OTG_L3 -+} dwc_otg_lx_state_e; -+ -+struct dwc_otg_global_regs_backup { -+ uint32_t gotgctl_local; -+ uint32_t gintmsk_local; -+ uint32_t gahbcfg_local; -+ uint32_t gusbcfg_local; -+ uint32_t grxfsiz_local; -+ uint32_t gnptxfsiz_local; -+#ifdef CONFIG_USB_DWC_OTG_LPM -+ uint32_t glpmcfg_local; -+#endif -+ uint32_t gi2cctl_local; -+ uint32_t hptxfsiz_local; -+ uint32_t pcgcctl_local; -+ uint32_t gdfifocfg_local; -+ uint32_t dtxfsiz_local[MAX_EPS_CHANNELS]; -+ uint32_t gpwrdn_local; -+ uint32_t xhib_pcgcctl; -+ uint32_t xhib_gpwrdn; -+}; -+ -+struct dwc_otg_host_regs_backup { -+ uint32_t hcfg_local; -+ uint32_t haintmsk_local; -+ uint32_t hcintmsk_local[MAX_EPS_CHANNELS]; -+ uint32_t hprt0_local; -+ uint32_t hfir_local; -+}; -+ -+struct dwc_otg_dev_regs_backup { -+ uint32_t dcfg; -+ uint32_t dctl; -+ uint32_t daintmsk; -+ uint32_t diepmsk; -+ uint32_t doepmsk; -+ uint32_t diepctl[MAX_EPS_CHANNELS]; -+ uint32_t dieptsiz[MAX_EPS_CHANNELS]; -+ uint32_t diepdma[MAX_EPS_CHANNELS]; -+}; -+/** -+ * The dwc_otg_core_if structure contains information needed to manage -+ * the DWC_otg controller acting in either host or device mode. It -+ * represents the programming view of the controller as a whole. -+ */ -+struct dwc_otg_core_if { -+ /** Parameters that define how the core should be configured.*/ -+ dwc_otg_core_params_t *core_params; -+ -+ /** Core Global registers starting at offset 000h. */ -+ dwc_otg_core_global_regs_t *core_global_regs; -+ -+ /** Device-specific information */ -+ dwc_otg_dev_if_t *dev_if; -+ /** Host-specific information */ -+ dwc_otg_host_if_t *host_if; -+ -+ /** Value from SNPSID register */ -+ uint32_t snpsid; -+ -+ /* -+ * Set to 1 if the core PHY interface bits in USBCFG have been -+ * initialized. -+ */ -+ uint8_t phy_init_done; -+ -+ /* -+ * SRP Success flag, set by srp success interrupt in FS I2C mode -+ */ -+ uint8_t srp_success; -+ uint8_t srp_timer_started; -+ /** Timer for SRP. If it expires before SRP is successful -+ * clear the SRP. */ -+ dwc_timer_t *srp_timer; -+ -+#ifdef DWC_DEV_SRPCAP -+ /* This timer is needed to power on the hibernated host core if SRP is not -+ * initiated on connected SRP capable device for limited period of time -+ */ -+ uint8_t pwron_timer_started; -+ dwc_timer_t *pwron_timer; -+#endif -+ /* Common configuration information */ -+ /** Power and Clock Gating Control Register */ -+ volatile uint32_t *pcgcctl; -+#define DWC_OTG_PCGCCTL_OFFSET 0xE00 -+ -+ /** Push/pop addresses for endpoints or host channels.*/ -+ uint32_t *data_fifo[MAX_EPS_CHANNELS]; -+#define DWC_OTG_DATA_FIFO_OFFSET 0x1000 -+#define DWC_OTG_DATA_FIFO_SIZE 0x1000 -+ -+ /** Total RAM for FIFOs (Bytes) */ -+ uint16_t total_fifo_size; -+ /** Size of Rx FIFO (Bytes) */ -+ uint16_t rx_fifo_size; -+ /** Size of Non-periodic Tx FIFO (Bytes) */ -+ uint16_t nperio_tx_fifo_size; -+ -+ /** 1 if DMA is enabled, 0 otherwise. */ -+ uint8_t dma_enable; -+ -+ /** 1 if DMA descriptor is enabled, 0 otherwise. */ -+ uint8_t dma_desc_enable; -+ -+ /** 1 if PTI Enhancement mode is enabled, 0 otherwise. */ -+ uint8_t pti_enh_enable; -+ -+ /** 1 if MPI Enhancement mode is enabled, 0 otherwise. */ -+ uint8_t multiproc_int_enable; -+ -+ /** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */ -+ uint8_t en_multiple_tx_fifo; -+ -+ /** Set to 1 if multiple packets of a high-bandwidth transfer is in -+ * process of being queued */ -+ uint8_t queuing_high_bandwidth; -+ -+ /** Hardware Configuration -- stored here for convenience.*/ -+ hwcfg1_data_t hwcfg1; -+ hwcfg2_data_t hwcfg2; -+ hwcfg3_data_t hwcfg3; -+ hwcfg4_data_t hwcfg4; -+ fifosize_data_t hptxfsiz; -+ -+ /** Host and Device Configuration -- stored here for convenience.*/ -+ hcfg_data_t hcfg; -+ dcfg_data_t dcfg; -+ -+ /** The operational State, during transations -+ * (a_host>>a_peripherial and b_device=>b_host) this may not -+ * match the core but allows the software to determine -+ * transitions. -+ */ -+ uint8_t op_state; -+ -+ /** -+ * Set to 1 if the HCD needs to be restarted on a session request -+ * interrupt. This is required if no connector ID status change has -+ * occurred since the HCD was last disconnected. -+ */ -+ uint8_t restart_hcd_on_session_req; -+ -+ /** HCD callbacks */ -+ /** A-Device is a_host */ -+#define A_HOST (1) -+ /** A-Device is a_suspend */ -+#define A_SUSPEND (2) -+ /** A-Device is a_peripherial */ -+#define A_PERIPHERAL (3) -+ /** B-Device is operating as a Peripheral. */ -+#define B_PERIPHERAL (4) -+ /** B-Device is operating as a Host. */ -+#define B_HOST (5) -+ -+ /** HCD callbacks */ -+ struct dwc_otg_cil_callbacks *hcd_cb; -+ /** PCD callbacks */ -+ struct dwc_otg_cil_callbacks *pcd_cb; -+ -+ /** Device mode Periodic Tx FIFO Mask */ -+ uint32_t p_tx_msk; -+ /** Device mode Periodic Tx FIFO Mask */ -+ uint32_t tx_msk; -+ -+ /** Workqueue object used for handling several interrupts */ -+ dwc_workq_t *wq_otg; -+ -+ /** Timer object used for handling "Wakeup Detected" Interrupt */ -+ dwc_timer_t *wkp_timer; -+ /** This arrays used for debug purposes for DEV OUT NAK enhancement */ -+ uint32_t start_doeptsiz_val[MAX_EPS_CHANNELS]; -+ ep_xfer_info_t ep_xfer_info[MAX_EPS_CHANNELS]; -+ dwc_timer_t *ep_xfer_timer[MAX_EPS_CHANNELS]; -+#ifdef DEBUG -+ uint32_t start_hcchar_val[MAX_EPS_CHANNELS]; -+ -+ hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS]; -+ dwc_timer_t *hc_xfer_timer[MAX_EPS_CHANNELS]; -+ -+ uint32_t hfnum_7_samples; -+ uint64_t hfnum_7_frrem_accum; -+ uint32_t hfnum_0_samples; -+ uint64_t hfnum_0_frrem_accum; -+ uint32_t hfnum_other_samples; -+ uint64_t hfnum_other_frrem_accum; -+#endif -+ -+#ifdef DWC_UTE_CFI -+ uint16_t pwron_rxfsiz; -+ uint16_t pwron_gnptxfsiz; -+ uint16_t pwron_txfsiz[15]; -+ -+ uint16_t init_rxfsiz; -+ uint16_t init_gnptxfsiz; -+ uint16_t init_txfsiz[15]; -+#endif -+ -+ /** Lx state of device */ -+ dwc_otg_lx_state_e lx_state; -+ -+ /** Saved Core Global registers */ -+ struct dwc_otg_global_regs_backup *gr_backup; -+ /** Saved Host registers */ -+ struct dwc_otg_host_regs_backup *hr_backup; -+ /** Saved Device registers */ -+ struct dwc_otg_dev_regs_backup *dr_backup; -+ -+ /** Power Down Enable */ -+ uint32_t power_down; -+ -+ /** ADP support Enable */ -+ uint32_t adp_enable; -+ -+ /** ADP structure object */ -+ dwc_otg_adp_t adp; -+ -+ /** hibernation/suspend flag */ -+ int hibernation_suspend; -+ -+ /** Device mode extended hibernation flag */ -+ int xhib; -+ -+ /** OTG revision supported */ -+ uint32_t otg_ver; -+ -+ /** OTG status flag used for HNP polling */ -+ uint8_t otg_sts; -+ -+ /** Pointer to either hcd->lock or pcd->lock */ -+ dwc_spinlock_t *lock; -+ -+ /** Start predict NextEP based on Learning Queue if equal 1, -+ * also used as counter of disabled NP IN EP's */ -+ uint8_t start_predict; -+ -+ /** NextEp sequence, including EP0: nextep_seq[] = EP if non-periodic and -+ * active, 0xff otherwise */ -+ uint8_t nextep_seq[MAX_EPS_CHANNELS]; -+ -+ /** Index of fisrt EP in nextep_seq array which should be re-enabled **/ -+ uint8_t first_in_nextep_seq; -+ -+ /** Frame number while entering to ISR - needed for ISOCs **/ -+ uint32_t frame_num; -+ -+}; -+ -+#ifdef DEBUG -+/* -+ * This function is called when transfer is timed out. -+ */ -+extern void hc_xfer_timeout(void *ptr); -+#endif -+ -+/* -+ * This function is called when transfer is timed out on endpoint. -+ */ -+extern void ep_xfer_timeout(void *ptr); -+ -+/* -+ * The following functions are functions for works -+ * using during handling some interrupts -+ */ -+extern void w_conn_id_status_change(void *p); -+ -+extern void w_wakeup_detected(void *p); -+ -+/** Saves global register values into system memory. */ -+extern int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if); -+/** Saves device register values into system memory. */ -+extern int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if); -+/** Saves host register values into system memory. */ -+extern int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if); -+/** Restore global register values. */ -+extern int dwc_otg_restore_global_regs(dwc_otg_core_if_t * core_if); -+/** Restore host register values. */ -+extern int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset); -+/** Restore device register values. */ -+extern int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if, -+ int rem_wakeup); -+extern int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if); -+extern int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode, -+ int is_host); -+ -+extern int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if, -+ int restore_mode, int reset); -+extern int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if, -+ int rem_wakeup, int reset); -+ -+/* -+ * The following functions support initialization of the CIL driver component -+ * and the DWC_otg controller. -+ */ -+extern void dwc_otg_core_host_init(dwc_otg_core_if_t * _core_if); -+extern void dwc_otg_core_dev_init(dwc_otg_core_if_t * _core_if); -+ -+/** @name Device CIL Functions -+ * The following functions support managing the DWC_otg controller in device -+ * mode. -+ */ -+/**@{*/ -+extern void dwc_otg_wakeup(dwc_otg_core_if_t * _core_if); -+extern void dwc_otg_read_setup_packet(dwc_otg_core_if_t * _core_if, -+ uint32_t * _dest); -+extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * _core_if); -+extern void dwc_otg_ep0_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep); -+extern void dwc_otg_ep_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep); -+extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep); -+extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * _core_if, -+ dwc_ep_t * _ep); -+extern void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * _core_if, -+ dwc_ep_t * _ep); -+extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * _core_if, -+ dwc_ep_t * _ep); -+extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * _core_if, -+ dwc_ep_t * _ep); -+extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t * _core_if, -+ dwc_ep_t * _ep, int _dma); -+extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep); -+extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * _core_if, -+ dwc_ep_t * _ep); -+extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * _core_if); -+ -+#ifdef DWC_EN_ISOC -+extern void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if, -+ dwc_ep_t * ep); -+extern void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if, -+ dwc_ep_t * ep); -+#endif /* DWC_EN_ISOC */ -+/**@}*/ -+ -+/** @name Host CIL Functions -+ * The following functions support managing the DWC_otg controller in host -+ * mode. -+ */ -+/**@{*/ -+extern void dwc_otg_hc_init(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc); -+extern void dwc_otg_hc_halt(dwc_otg_core_if_t * _core_if, -+ dwc_hc_t * _hc, dwc_otg_halt_status_e _halt_status); -+extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc); -+extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * _core_if, -+ dwc_hc_t * _hc); -+extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * _core_if, -+ dwc_hc_t * _hc); -+extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc); -+extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t * _core_if, -+ dwc_hc_t * _hc); -+extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * _core_if); -+extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * _core_if); -+ -+extern void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if, -+ dwc_hc_t * hc); -+ -+extern uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if); -+ -+/* Macro used to clear one channel interrupt */ -+#define clear_hc_int(_hc_regs_, _intr_) \ -+do { \ -+ hcint_data_t hcint_clear = {.d32 = 0}; \ -+ hcint_clear.b._intr_ = 1; \ -+ DWC_WRITE_REG32(&(_hc_regs_)->hcint, hcint_clear.d32); \ -+} while (0) -+ -+/* -+ * Macro used to disable one channel interrupt. Channel interrupts are -+ * disabled when the channel is halted or released by the interrupt handler. -+ * There is no need to handle further interrupts of that type until the -+ * channel is re-assigned. In fact, subsequent handling may cause crashes -+ * because the channel structures are cleaned up when the channel is released. -+ */ -+#define disable_hc_int(_hc_regs_, _intr_) \ -+do { \ -+ hcintmsk_data_t hcintmsk = {.d32 = 0}; \ -+ hcintmsk.b._intr_ = 1; \ -+ DWC_MODIFY_REG32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \ -+} while (0) -+ -+/** -+ * This function Reads HPRT0 in preparation to modify. It keeps the -+ * WC bits 0 so that if they are read as 1, they won't clear when you -+ * write it back -+ */ -+static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t * _core_if) -+{ -+ hprt0_data_t hprt0; -+ hprt0.d32 = DWC_READ_REG32(_core_if->host_if->hprt0); -+ hprt0.b.prtena = 0; -+ hprt0.b.prtconndet = 0; -+ hprt0.b.prtenchng = 0; -+ hprt0.b.prtovrcurrchng = 0; -+ return hprt0.d32; -+} -+ -+/**@}*/ -+ -+/** @name Common CIL Functions -+ * The following functions support managing the DWC_otg controller in either -+ * device or host mode. -+ */ -+/**@{*/ -+ -+extern void dwc_otg_read_packet(dwc_otg_core_if_t * core_if, -+ uint8_t * dest, uint16_t bytes); -+ -+extern void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * _core_if, const int _num); -+extern void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * _core_if); -+extern void dwc_otg_core_reset(dwc_otg_core_if_t * _core_if); -+ -+/** -+ * This function returns the Core Interrupt register. -+ */ -+static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t * core_if) -+{ -+ return (DWC_READ_REG32(&core_if->core_global_regs->gintsts) & -+ DWC_READ_REG32(&core_if->core_global_regs->gintmsk)); -+} -+ -+/** -+ * This function returns the OTG Interrupt register. -+ */ -+static inline uint32_t dwc_otg_read_otg_intr(dwc_otg_core_if_t * core_if) -+{ -+ return (DWC_READ_REG32(&core_if->core_global_regs->gotgint)); -+} -+ -+/** -+ * This function reads the Device All Endpoints Interrupt register and -+ * returns the IN endpoint interrupt bits. -+ */ -+static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t * -+ core_if) -+{ -+ -+ uint32_t v; -+ -+ if (core_if->multiproc_int_enable) { -+ v = DWC_READ_REG32(&core_if->dev_if-> -+ dev_global_regs->deachint) & -+ DWC_READ_REG32(&core_if-> -+ dev_if->dev_global_regs->deachintmsk); -+ } else { -+ v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) & -+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk); -+ } -+ return (v & 0xffff); -+} -+ -+/** -+ * This function reads the Device All Endpoints Interrupt register and -+ * returns the OUT endpoint interrupt bits. -+ */ -+static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t * -+ core_if) -+{ -+ uint32_t v; -+ -+ if (core_if->multiproc_int_enable) { -+ v = DWC_READ_REG32(&core_if->dev_if-> -+ dev_global_regs->deachint) & -+ DWC_READ_REG32(&core_if-> -+ dev_if->dev_global_regs->deachintmsk); -+ } else { -+ v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) & -+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk); -+ } -+ -+ return ((v & 0xffff0000) >> 16); -+} -+ -+/** -+ * This function returns the Device IN EP Interrupt register -+ */ -+static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t * core_if, -+ dwc_ep_t * ep) -+{ -+ dwc_otg_dev_if_t *dev_if = core_if->dev_if; -+ uint32_t v, msk, emp; -+ -+ if (core_if->multiproc_int_enable) { -+ msk = -+ DWC_READ_REG32(&dev_if-> -+ dev_global_regs->diepeachintmsk[ep->num]); -+ emp = -+ DWC_READ_REG32(&dev_if-> -+ dev_global_regs->dtknqr4_fifoemptymsk); -+ msk |= ((emp >> ep->num) & 0x1) << 7; -+ v = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk; -+ } else { -+ msk = DWC_READ_REG32(&dev_if->dev_global_regs->diepmsk); -+ emp = -+ DWC_READ_REG32(&dev_if-> -+ dev_global_regs->dtknqr4_fifoemptymsk); -+ msk |= ((emp >> ep->num) & 0x1) << 7; -+ v = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk; -+ } -+ -+ return v; -+} -+ -+/** -+ * This function returns the Device OUT EP Interrupt register -+ */ -+static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t * -+ _core_if, dwc_ep_t * _ep) -+{ -+ dwc_otg_dev_if_t *dev_if = _core_if->dev_if; -+ uint32_t v; -+ doepmsk_data_t msk = {.d32 = 0 }; -+ -+ if (_core_if->multiproc_int_enable) { -+ msk.d32 = -+ DWC_READ_REG32(&dev_if-> -+ dev_global_regs->doepeachintmsk[_ep->num]); -+ if (_core_if->pti_enh_enable) { -+ msk.b.pktdrpsts = 1; -+ } -+ v = DWC_READ_REG32(&dev_if-> -+ out_ep_regs[_ep->num]->doepint) & msk.d32; -+ } else { -+ msk.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->doepmsk); -+ if (_core_if->pti_enh_enable) { -+ msk.b.pktdrpsts = 1; -+ } -+ v = DWC_READ_REG32(&dev_if-> -+ out_ep_regs[_ep->num]->doepint) & msk.d32; -+ } -+ return v; -+} -+ -+/** -+ * This function returns the Host All Channel Interrupt register -+ */ -+static inline uint32_t dwc_otg_read_host_all_channels_intr(dwc_otg_core_if_t * -+ _core_if) -+{ -+ return (DWC_READ_REG32(&_core_if->host_if->host_global_regs->haint)); -+} -+ -+static inline uint32_t dwc_otg_read_host_channel_intr(dwc_otg_core_if_t * -+ _core_if, dwc_hc_t * _hc) -+{ -+ return (DWC_READ_REG32 -+ (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint)); -+} -+ -+/** -+ * This function returns the mode of the operation, host or device. -+ * -+ * @return 0 - Device Mode, 1 - Host Mode -+ */ -+static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t * _core_if) -+{ -+ return (DWC_READ_REG32(&_core_if->core_global_regs->gintsts) & 0x1); -+} -+ -+/**@}*/ -+ -+/** -+ * DWC_otg CIL callback structure. This structure allows the HCD and -+ * PCD to register functions used for starting and stopping the PCD -+ * and HCD for role change on for a DRD. -+ */ -+typedef struct dwc_otg_cil_callbacks { -+ /** Start function for role change */ -+ int (*start) (void *_p); -+ /** Stop Function for role change */ -+ int (*stop) (void *_p); -+ /** Disconnect Function for role change */ -+ int (*disconnect) (void *_p); -+ /** Resume/Remote wakeup Function */ -+ int (*resume_wakeup) (void *_p); -+ /** Suspend function */ -+ int (*suspend) (void *_p); -+ /** Session Start (SRP) */ -+ int (*session_start) (void *_p); -+#ifdef CONFIG_USB_DWC_OTG_LPM -+ /** Sleep (switch to L0 state) */ -+ int (*sleep) (void *_p); -+#endif -+ /** Pointer passed to start() and stop() */ -+ void *p; -+} dwc_otg_cil_callbacks_t; -+ -+extern void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * _core_if, -+ dwc_otg_cil_callbacks_t * _cb, -+ void *_p); -+extern void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * _core_if, -+ dwc_otg_cil_callbacks_t * _cb, -+ void *_p); -+ -+void dwc_otg_initiate_srp(dwc_otg_core_if_t * core_if); -+ -+////////////////////////////////////////////////////////////////////// -+/** Start the HCD. Helper function for using the HCD callbacks. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ */ -+static inline void cil_hcd_start(dwc_otg_core_if_t * core_if) -+{ -+ if (core_if->hcd_cb && core_if->hcd_cb->start) { -+ core_if->hcd_cb->start(core_if->hcd_cb->p); -+ } -+} -+ -+/** Stop the HCD. Helper function for using the HCD callbacks. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ */ -+static inline void cil_hcd_stop(dwc_otg_core_if_t * core_if) -+{ -+ if (core_if->hcd_cb && core_if->hcd_cb->stop) { -+ core_if->hcd_cb->stop(core_if->hcd_cb->p); -+ } -+} -+ -+/** Disconnect the HCD. Helper function for using the HCD callbacks. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ */ -+static inline void cil_hcd_disconnect(dwc_otg_core_if_t * core_if) -+{ -+ if (core_if->hcd_cb && core_if->hcd_cb->disconnect) { -+ core_if->hcd_cb->disconnect(core_if->hcd_cb->p); -+ } -+} -+ -+/** Inform the HCD the a New Session has begun. Helper function for -+ * using the HCD callbacks. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ */ -+static inline void cil_hcd_session_start(dwc_otg_core_if_t * core_if) -+{ -+ if (core_if->hcd_cb && core_if->hcd_cb->session_start) { -+ core_if->hcd_cb->session_start(core_if->hcd_cb->p); -+ } -+} -+ -+#ifdef CONFIG_USB_DWC_OTG_LPM -+/** -+ * Inform the HCD about LPM sleep. -+ * Helper function for using the HCD callbacks. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ */ -+static inline void cil_hcd_sleep(dwc_otg_core_if_t * core_if) -+{ -+ if (core_if->hcd_cb && core_if->hcd_cb->sleep) { -+ core_if->hcd_cb->sleep(core_if->hcd_cb->p); -+ } -+} -+#endif -+ -+/** Resume the HCD. Helper function for using the HCD callbacks. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ */ -+static inline void cil_hcd_resume(dwc_otg_core_if_t * core_if) -+{ -+ if (core_if->hcd_cb && core_if->hcd_cb->resume_wakeup) { -+ core_if->hcd_cb->resume_wakeup(core_if->hcd_cb->p); -+ } -+} -+ -+/** Start the PCD. Helper function for using the PCD callbacks. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ */ -+static inline void cil_pcd_start(dwc_otg_core_if_t * core_if) -+{ -+ if (core_if->pcd_cb && core_if->pcd_cb->start) { -+ core_if->pcd_cb->start(core_if->pcd_cb->p); -+ } -+} -+ -+/** Stop the PCD. Helper function for using the PCD callbacks. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ */ -+static inline void cil_pcd_stop(dwc_otg_core_if_t * core_if) -+{ -+ if (core_if->pcd_cb && core_if->pcd_cb->stop) { -+ core_if->pcd_cb->stop(core_if->pcd_cb->p); -+ } -+} -+ -+/** Suspend the PCD. Helper function for using the PCD callbacks. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ */ -+static inline void cil_pcd_suspend(dwc_otg_core_if_t * core_if) -+{ -+ if (core_if->pcd_cb && core_if->pcd_cb->suspend) { -+ core_if->pcd_cb->suspend(core_if->pcd_cb->p); -+ } -+} -+ -+/** Resume the PCD. Helper function for using the PCD callbacks. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ */ -+static inline void cil_pcd_resume(dwc_otg_core_if_t * core_if) -+{ -+ if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) { -+ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p); -+ } -+} -+ -+////////////////////////////////////////////////////////////////////// -+ -+#endif -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c 2015-11-29 09:42:39.919098694 +0100 -@@ -0,0 +1,1594 @@ -+/* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil_intr.c $ -+ * $Revision: #32 $ -+ * $Date: 2012/08/10 $ -+ * $Change: 2047372 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+ -+/** @file -+ * -+ * The Core Interface Layer provides basic services for accessing and -+ * managing the DWC_otg hardware. These services are used by both the -+ * Host Controller Driver and the Peripheral Controller Driver. -+ * -+ * This file contains the Common Interrupt handlers. -+ */ -+#include "dwc_os.h" -+#include "dwc_otg_regs.h" -+#include "dwc_otg_cil.h" -+#include "dwc_otg_driver.h" -+#include "dwc_otg_pcd.h" -+#include "dwc_otg_hcd.h" -+ -+#ifdef DEBUG -+inline const char *op_state_str(dwc_otg_core_if_t * core_if) -+{ -+ return (core_if->op_state == A_HOST ? "a_host" : -+ (core_if->op_state == A_SUSPEND ? "a_suspend" : -+ (core_if->op_state == A_PERIPHERAL ? "a_peripheral" : -+ (core_if->op_state == B_PERIPHERAL ? "b_peripheral" : -+ (core_if->op_state == B_HOST ? "b_host" : "unknown"))))); -+} -+#endif -+ -+/** This function will log a debug message -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ */ -+int32_t dwc_otg_handle_mode_mismatch_intr(dwc_otg_core_if_t * core_if) -+{ -+ gintsts_data_t gintsts; -+ DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n", -+ dwc_otg_mode(core_if) ? "Host" : "Device"); -+ -+ /* Clear interrupt */ -+ gintsts.d32 = 0; -+ gintsts.b.modemismatch = 1; -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); -+ return 1; -+} -+ -+/** -+ * This function handles the OTG Interrupts. It reads the OTG -+ * Interrupt Register (GOTGINT) to determine what interrupt has -+ * occurred. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ */ -+int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t * core_if) -+{ -+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; -+ gotgint_data_t gotgint; -+ gotgctl_data_t gotgctl; -+ gintmsk_data_t gintmsk; -+ gpwrdn_data_t gpwrdn; -+ -+ gotgint.d32 = DWC_READ_REG32(&global_regs->gotgint); -+ gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl); -+ DWC_DEBUGPL(DBG_CIL, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint.d32, -+ op_state_str(core_if)); -+ -+ if (gotgint.b.sesenddet) { -+ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " -+ "Session End Detected++ (%s)\n", -+ op_state_str(core_if)); -+ gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl); -+ -+ if (core_if->op_state == B_HOST) { -+ cil_pcd_start(core_if); -+ core_if->op_state = B_PERIPHERAL; -+ } else { -+ /* If not B_HOST and Device HNP still set. HNP -+ * Did not succeed!*/ -+ if (gotgctl.b.devhnpen) { -+ DWC_DEBUGPL(DBG_ANY, "Session End Detected\n"); -+ __DWC_ERROR("Device Not Connected/Responding!\n"); -+ } -+ -+ /* If Session End Detected the B-Cable has -+ * been disconnected. */ -+ /* Reset PCD and Gadget driver to a -+ * clean state. */ -+ core_if->lx_state = DWC_OTG_L0; -+ DWC_SPINUNLOCK(core_if->lock); -+ cil_pcd_stop(core_if); -+ DWC_SPINLOCK(core_if->lock); -+ -+ if (core_if->adp_enable) { -+ if (core_if->power_down == 2) { -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pwrdnswtch = 1; -+ DWC_MODIFY_REG32(&core_if-> -+ core_global_regs-> -+ gpwrdn, gpwrdn.d32, 0); -+ } -+ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pmuintsel = 1; -+ gpwrdn.b.pmuactv = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs-> -+ gpwrdn, 0, gpwrdn.d32); -+ -+ dwc_otg_adp_sense_start(core_if); -+ } -+ } -+ -+ gotgctl.d32 = 0; -+ gotgctl.b.devhnpen = 1; -+ DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0); -+ } -+ if (gotgint.b.sesreqsucstschng) { -+ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " -+ "Session Reqeust Success Status Change++\n"); -+ gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl); -+ if (gotgctl.b.sesreqscs) { -+ -+ if ((core_if->core_params->phy_type == -+ DWC_PHY_TYPE_PARAM_FS) && (core_if->core_params->i2c_enable)) { -+ core_if->srp_success = 1; -+ } else { -+ DWC_SPINUNLOCK(core_if->lock); -+ cil_pcd_resume(core_if); -+ DWC_SPINLOCK(core_if->lock); -+ /* Clear Session Request */ -+ gotgctl.d32 = 0; -+ gotgctl.b.sesreq = 1; -+ DWC_MODIFY_REG32(&global_regs->gotgctl, -+ gotgctl.d32, 0); -+ } -+ } -+ } -+ if (gotgint.b.hstnegsucstschng) { -+ /* Print statements during the HNP interrupt handling -+ * can cause it to fail.*/ -+ gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl); -+ /* WA for 3.00a- HW is not setting cur_mode, even sometimes -+ * this does not help*/ -+ if (core_if->snpsid >= OTG_CORE_REV_3_00a) -+ dwc_udelay(100); -+ if (gotgctl.b.hstnegscs) { -+ if (dwc_otg_is_host_mode(core_if)) { -+ core_if->op_state = B_HOST; -+ /* -+ * Need to disable SOF interrupt immediately. -+ * When switching from device to host, the PCD -+ * interrupt handler won't handle the -+ * interrupt if host mode is already set. The -+ * HCD interrupt handler won't get called if -+ * the HCD state is HALT. This means that the -+ * interrupt does not get handled and Linux -+ * complains loudly. -+ */ -+ gintmsk.d32 = 0; -+ gintmsk.b.sofintr = 1; -+ DWC_MODIFY_REG32(&global_regs->gintmsk, -+ gintmsk.d32, 0); -+ /* Call callback function with spin lock released */ -+ DWC_SPINUNLOCK(core_if->lock); -+ cil_pcd_stop(core_if); -+ /* -+ * Initialize the Core for Host mode. -+ */ -+ cil_hcd_start(core_if); -+ DWC_SPINLOCK(core_if->lock); -+ core_if->op_state = B_HOST; -+ } -+ } else { -+ gotgctl.d32 = 0; -+ gotgctl.b.hnpreq = 1; -+ gotgctl.b.devhnpen = 1; -+ DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0); -+ DWC_DEBUGPL(DBG_ANY, "HNP Failed\n"); -+ __DWC_ERROR("Device Not Connected/Responding\n"); -+ } -+ } -+ if (gotgint.b.hstnegdet) { -+ /* The disconnect interrupt is set at the same time as -+ * Host Negotiation Detected. During the mode -+ * switch all interrupts are cleared so the disconnect -+ * interrupt handler will not get executed. -+ */ -+ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " -+ "Host Negotiation Detected++ (%s)\n", -+ (dwc_otg_is_host_mode(core_if) ? "Host" : -+ "Device")); -+ if (dwc_otg_is_device_mode(core_if)) { -+ DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n", -+ core_if->op_state); -+ DWC_SPINUNLOCK(core_if->lock); -+ cil_hcd_disconnect(core_if); -+ cil_pcd_start(core_if); -+ DWC_SPINLOCK(core_if->lock); -+ core_if->op_state = A_PERIPHERAL; -+ } else { -+ /* -+ * Need to disable SOF interrupt immediately. When -+ * switching from device to host, the PCD interrupt -+ * handler won't handle the interrupt if host mode is -+ * already set. The HCD interrupt handler won't get -+ * called if the HCD state is HALT. This means that -+ * the interrupt does not get handled and Linux -+ * complains loudly. -+ */ -+ gintmsk.d32 = 0; -+ gintmsk.b.sofintr = 1; -+ DWC_MODIFY_REG32(&global_regs->gintmsk, gintmsk.d32, 0); -+ DWC_SPINUNLOCK(core_if->lock); -+ cil_pcd_stop(core_if); -+ cil_hcd_start(core_if); -+ DWC_SPINLOCK(core_if->lock); -+ core_if->op_state = A_HOST; -+ } -+ } -+ if (gotgint.b.adevtoutchng) { -+ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " -+ "A-Device Timeout Change++\n"); -+ } -+ if (gotgint.b.debdone) { -+ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " "Debounce Done++\n"); -+ } -+ -+ /* Clear GOTGINT */ -+ DWC_WRITE_REG32(&core_if->core_global_regs->gotgint, gotgint.d32); -+ -+ return 1; -+} -+ -+void w_conn_id_status_change(void *p) -+{ -+ dwc_otg_core_if_t *core_if = p; -+ uint32_t count = 0; -+ gotgctl_data_t gotgctl = {.d32 = 0 }; -+ -+ gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl); -+ DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32); -+ DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts); -+ -+ /* B-Device connector (Device Mode) */ -+ if (gotgctl.b.conidsts) { -+ /* Wait for switch to device mode. */ -+ while (!dwc_otg_is_device_mode(core_if)) { -+ DWC_PRINTF("Waiting for Peripheral Mode, Mode=%s\n", -+ (dwc_otg_is_host_mode(core_if) ? "Host" : -+ "Peripheral")); -+ dwc_mdelay(100); -+ if (++count > 10000) -+ break; -+ } -+ DWC_ASSERT(++count < 10000, -+ "Connection id status change timed out"); -+ core_if->op_state = B_PERIPHERAL; -+ dwc_otg_core_init(core_if); -+ dwc_otg_enable_global_interrupts(core_if); -+ cil_pcd_start(core_if); -+ } else { -+ /* A-Device connector (Host Mode) */ -+ while (!dwc_otg_is_host_mode(core_if)) { -+ DWC_PRINTF("Waiting for Host Mode, Mode=%s\n", -+ (dwc_otg_is_host_mode(core_if) ? "Host" : -+ "Peripheral")); -+ dwc_mdelay(100); -+ if (++count > 10000) -+ break; -+ } -+ DWC_ASSERT(++count < 10000, -+ "Connection id status change timed out"); -+ core_if->op_state = A_HOST; -+ /* -+ * Initialize the Core for Host mode. -+ */ -+ dwc_otg_core_init(core_if); -+ dwc_otg_enable_global_interrupts(core_if); -+ cil_hcd_start(core_if); -+ } -+} -+ -+/** -+ * This function handles the Connector ID Status Change Interrupt. It -+ * reads the OTG Interrupt Register (GOTCTL) to determine whether this -+ * is a Device to Host Mode transition or a Host Mode to Device -+ * Transition. -+ * -+ * This only occurs when the cable is connected/removed from the PHY -+ * connector. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ */ -+int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t * core_if) -+{ -+ -+ /* -+ * Need to disable SOF interrupt immediately. If switching from device -+ * to host, the PCD interrupt handler won't handle the interrupt if -+ * host mode is already set. The HCD interrupt handler won't get -+ * called if the HCD state is HALT. This means that the interrupt does -+ * not get handled and Linux complains loudly. -+ */ -+ gintmsk_data_t gintmsk = {.d32 = 0 }; -+ gintsts_data_t gintsts = {.d32 = 0 }; -+ -+ gintmsk.b.sofintr = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0); -+ -+ DWC_DEBUGPL(DBG_CIL, -+ " ++Connector ID Status Change Interrupt++ (%s)\n", -+ (dwc_otg_is_host_mode(core_if) ? "Host" : "Device")); -+ -+ DWC_SPINUNLOCK(core_if->lock); -+ -+ /* -+ * Need to schedule a work, as there are possible DELAY function calls -+ * Release lock before scheduling workq as it holds spinlock during scheduling -+ */ -+ -+ DWC_WORKQ_SCHEDULE(core_if->wq_otg, w_conn_id_status_change, -+ core_if, "connection id status change"); -+ DWC_SPINLOCK(core_if->lock); -+ -+ /* Set flag and clear interrupt */ -+ gintsts.b.conidstschng = 1; -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); -+ -+ return 1; -+} -+ -+/** -+ * This interrupt indicates that a device is initiating the Session -+ * Request Protocol to request the host to turn on bus power so a new -+ * session can begin. The handler responds by turning on bus power. If -+ * the DWC_otg controller is in low power mode, the handler brings the -+ * controller out of low power mode before turning on bus power. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ */ -+int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t * core_if) -+{ -+ gintsts_data_t gintsts; -+ -+#ifndef DWC_HOST_ONLY -+ DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n"); -+ -+ if (dwc_otg_is_device_mode(core_if)) { -+ DWC_PRINTF("SRP: Device mode\n"); -+ } else { -+ hprt0_data_t hprt0; -+ DWC_PRINTF("SRP: Host mode\n"); -+ -+ /* Turn on the port power bit. */ -+ hprt0.d32 = dwc_otg_read_hprt0(core_if); -+ hprt0.b.prtpwr = 1; -+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); -+ -+ /* Start the Connection timer. So a message can be displayed -+ * if connect does not occur within 10 seconds. */ -+ cil_hcd_session_start(core_if); -+ } -+#endif -+ -+ /* Clear interrupt */ -+ gintsts.d32 = 0; -+ gintsts.b.sessreqintr = 1; -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); -+ -+ return 1; -+} -+ -+void w_wakeup_detected(void *p) -+{ -+ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) p; -+ /* -+ * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms -+ * so that OPT tests pass with all PHYs). -+ */ -+ hprt0_data_t hprt0 = {.d32 = 0 }; -+#if 0 -+ pcgcctl_data_t pcgcctl = {.d32 = 0 }; -+ /* Restart the Phy Clock */ -+ pcgcctl.b.stoppclk = 1; -+ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0); -+ dwc_udelay(10); -+#endif //0 -+ hprt0.d32 = dwc_otg_read_hprt0(core_if); -+ DWC_DEBUGPL(DBG_ANY, "Resume: HPRT0=%0x\n", hprt0.d32); -+// dwc_mdelay(70); -+ hprt0.b.prtres = 0; /* Resume */ -+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); -+ DWC_DEBUGPL(DBG_ANY, "Clear Resume: HPRT0=%0x\n", -+ DWC_READ_REG32(core_if->host_if->hprt0)); -+ -+ cil_hcd_resume(core_if); -+ -+ /** Change to L0 state*/ -+ core_if->lx_state = DWC_OTG_L0; -+} -+ -+/** -+ * This interrupt indicates that the DWC_otg controller has detected a -+ * resume or remote wakeup sequence. If the DWC_otg controller is in -+ * low power mode, the handler must brings the controller out of low -+ * power mode. The controller automatically begins resume -+ * signaling. The handler schedules a time to stop resume signaling. -+ */ -+int32_t dwc_otg_handle_wakeup_detected_intr(dwc_otg_core_if_t * core_if) -+{ -+ gintsts_data_t gintsts; -+ -+ DWC_DEBUGPL(DBG_ANY, -+ "++Resume and Remote Wakeup Detected Interrupt++\n"); -+ -+ DWC_PRINTF("%s lxstate = %d\n", __func__, core_if->lx_state); -+ -+ if (dwc_otg_is_device_mode(core_if)) { -+ dctl_data_t dctl = {.d32 = 0 }; -+ DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", -+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs-> -+ dsts)); -+ if (core_if->lx_state == DWC_OTG_L2) { -+#ifdef PARTIAL_POWER_DOWN -+ if (core_if->hwcfg4.b.power_optimiz) { -+ pcgcctl_data_t power = {.d32 = 0 }; -+ -+ power.d32 = DWC_READ_REG32(core_if->pcgcctl); -+ DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n", -+ power.d32); -+ -+ power.b.stoppclk = 0; -+ DWC_WRITE_REG32(core_if->pcgcctl, power.d32); -+ -+ power.b.pwrclmp = 0; -+ DWC_WRITE_REG32(core_if->pcgcctl, power.d32); -+ -+ power.b.rstpdwnmodule = 0; -+ DWC_WRITE_REG32(core_if->pcgcctl, power.d32); -+ } -+#endif -+ /* Clear the Remote Wakeup Signaling */ -+ dctl.b.rmtwkupsig = 1; -+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> -+ dctl, dctl.d32, 0); -+ -+ DWC_SPINUNLOCK(core_if->lock); -+ if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) { -+ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p); -+ } -+ DWC_SPINLOCK(core_if->lock); -+ } else { -+ glpmcfg_data_t lpmcfg; -+ lpmcfg.d32 = -+ DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); -+ lpmcfg.b.hird_thres &= (~(1 << 4)); -+ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, -+ lpmcfg.d32); -+ } -+ /** Change to L0 state*/ -+ core_if->lx_state = DWC_OTG_L0; -+ } else { -+ if (core_if->lx_state != DWC_OTG_L1) { -+ pcgcctl_data_t pcgcctl = {.d32 = 0 }; -+ -+ /* Restart the Phy Clock */ -+ pcgcctl.b.stoppclk = 1; -+ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0); -+ DWC_TIMER_SCHEDULE(core_if->wkp_timer, 71); -+ } else { -+ /** Change to L0 state*/ -+ core_if->lx_state = DWC_OTG_L0; -+ } -+ } -+ -+ /* Clear interrupt */ -+ gintsts.d32 = 0; -+ gintsts.b.wkupintr = 1; -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); -+ -+ return 1; -+} -+ -+/** -+ * This interrupt indicates that the Wakeup Logic has detected a -+ * Device disconnect. -+ */ -+static int32_t dwc_otg_handle_pwrdn_disconnect_intr(dwc_otg_core_if_t *core_if) -+{ -+ gpwrdn_data_t gpwrdn = { .d32 = 0 }; -+ gpwrdn_data_t gpwrdn_temp = { .d32 = 0 }; -+ gpwrdn_temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); -+ -+ DWC_PRINTF("%s called\n", __FUNCTION__); -+ -+ if (!core_if->hibernation_suspend) { -+ DWC_PRINTF("Already exited from Hibernation\n"); -+ return 1; -+ } -+ -+ /* Switch on the voltage to the core */ -+ gpwrdn.b.pwrdnswtch = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ dwc_udelay(10); -+ -+ /* Reset the core */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pwrdnrstn = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ dwc_udelay(10); -+ -+ /* Disable power clamps*/ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pwrdnclmp = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ -+ /* Remove reset the core signal */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pwrdnrstn = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); -+ dwc_udelay(10); -+ -+ /* Disable PMU interrupt */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pmuintsel = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ -+ core_if->hibernation_suspend = 0; -+ -+ /* Disable PMU */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pmuactv = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ dwc_udelay(10); -+ -+ if (gpwrdn_temp.b.idsts) { -+ core_if->op_state = B_PERIPHERAL; -+ dwc_otg_core_init(core_if); -+ dwc_otg_enable_global_interrupts(core_if); -+ cil_pcd_start(core_if); -+ } else { -+ core_if->op_state = A_HOST; -+ dwc_otg_core_init(core_if); -+ dwc_otg_enable_global_interrupts(core_if); -+ cil_hcd_start(core_if); -+ } -+ -+ return 1; -+} -+ -+/** -+ * This interrupt indicates that the Wakeup Logic has detected a -+ * remote wakeup sequence. -+ */ -+static int32_t dwc_otg_handle_pwrdn_wakeup_detected_intr(dwc_otg_core_if_t * core_if) -+{ -+ gpwrdn_data_t gpwrdn = {.d32 = 0 }; -+ DWC_DEBUGPL(DBG_ANY, -+ "++Powerdown Remote Wakeup Detected Interrupt++\n"); -+ -+ if (!core_if->hibernation_suspend) { -+ DWC_PRINTF("Already exited from Hibernation\n"); -+ return 1; -+ } -+ -+ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); -+ if (gpwrdn.b.idsts) { // Device Mode -+ if ((core_if->power_down == 2) -+ && (core_if->hibernation_suspend == 1)) { -+ dwc_otg_device_hibernation_restore(core_if, 0, 0); -+ } -+ } else { -+ if ((core_if->power_down == 2) -+ && (core_if->hibernation_suspend == 1)) { -+ dwc_otg_host_hibernation_restore(core_if, 1, 0); -+ } -+ } -+ return 1; -+} -+ -+static int32_t dwc_otg_handle_pwrdn_idsts_change(dwc_otg_device_t *otg_dev) -+{ -+ gpwrdn_data_t gpwrdn = {.d32 = 0 }; -+ gpwrdn_data_t gpwrdn_temp = {.d32 = 0 }; -+ dwc_otg_core_if_t *core_if = otg_dev->core_if; -+ -+ DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__); -+ gpwrdn_temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); -+ if (core_if->power_down == 2) { -+ if (!core_if->hibernation_suspend) { -+ DWC_PRINTF("Already exited from Hibernation\n"); -+ return 1; -+ } -+ DWC_DEBUGPL(DBG_ANY, "Exit from hibernation on ID sts change\n"); -+ /* Switch on the voltage to the core */ -+ gpwrdn.b.pwrdnswtch = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ dwc_udelay(10); -+ -+ /* Reset the core */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pwrdnrstn = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ dwc_udelay(10); -+ -+ /* Disable power clamps */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pwrdnclmp = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ -+ /* Remove reset the core signal */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pwrdnrstn = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); -+ dwc_udelay(10); -+ -+ /* Disable PMU interrupt */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pmuintsel = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ -+ /*Indicates that we are exiting from hibernation */ -+ core_if->hibernation_suspend = 0; -+ -+ /* Disable PMU */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pmuactv = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ dwc_udelay(10); -+ -+ gpwrdn.d32 = core_if->gr_backup->gpwrdn_local; -+ if (gpwrdn.b.dis_vbus == 1) { -+ gpwrdn.d32 = 0; -+ gpwrdn.b.dis_vbus = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ } -+ -+ if (gpwrdn_temp.b.idsts) { -+ core_if->op_state = B_PERIPHERAL; -+ dwc_otg_core_init(core_if); -+ dwc_otg_enable_global_interrupts(core_if); -+ cil_pcd_start(core_if); -+ } else { -+ core_if->op_state = A_HOST; -+ dwc_otg_core_init(core_if); -+ dwc_otg_enable_global_interrupts(core_if); -+ cil_hcd_start(core_if); -+ } -+ } -+ -+ if (core_if->adp_enable) { -+ uint8_t is_host = 0; -+ DWC_SPINUNLOCK(core_if->lock); -+ /* Change the core_if's lock to hcd/pcd lock depend on mode? */ -+#ifndef DWC_HOST_ONLY -+ if (gpwrdn_temp.b.idsts) -+ core_if->lock = otg_dev->pcd->lock; -+#endif -+#ifndef DWC_DEVICE_ONLY -+ if (!gpwrdn_temp.b.idsts) { -+ core_if->lock = otg_dev->hcd->lock; -+ is_host = 1; -+ } -+#endif -+ DWC_PRINTF("RESTART ADP\n"); -+ if (core_if->adp.probe_enabled) -+ dwc_otg_adp_probe_stop(core_if); -+ if (core_if->adp.sense_enabled) -+ dwc_otg_adp_sense_stop(core_if); -+ if (core_if->adp.sense_timer_started) -+ DWC_TIMER_CANCEL(core_if->adp.sense_timer); -+ if (core_if->adp.vbuson_timer_started) -+ DWC_TIMER_CANCEL(core_if->adp.vbuson_timer); -+ core_if->adp.probe_timer_values[0] = -1; -+ core_if->adp.probe_timer_values[1] = -1; -+ core_if->adp.sense_timer_started = 0; -+ core_if->adp.vbuson_timer_started = 0; -+ core_if->adp.probe_counter = 0; -+ core_if->adp.gpwrdn = 0; -+ -+ /* Disable PMU and restart ADP */ -+ gpwrdn_temp.d32 = 0; -+ gpwrdn_temp.b.pmuactv = 1; -+ gpwrdn_temp.b.pmuintsel = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ DWC_PRINTF("Check point 1\n"); -+ dwc_mdelay(110); -+ dwc_otg_adp_start(core_if, is_host); -+ DWC_SPINLOCK(core_if->lock); -+ } -+ -+ -+ return 1; -+} -+ -+static int32_t dwc_otg_handle_pwrdn_session_change(dwc_otg_core_if_t * core_if) -+{ -+ gpwrdn_data_t gpwrdn = {.d32 = 0 }; -+ int32_t otg_cap_param = core_if->core_params->otg_cap; -+ DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__); -+ -+ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); -+ if (core_if->power_down == 2) { -+ if (!core_if->hibernation_suspend) { -+ DWC_PRINTF("Already exited from Hibernation\n"); -+ return 1; -+ } -+ -+ if ((otg_cap_param != DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE || -+ otg_cap_param != DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE) && -+ gpwrdn.b.bsessvld == 0) { -+ /* Save gpwrdn register for further usage if stschng interrupt */ -+ core_if->gr_backup->gpwrdn_local = -+ DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); -+ /*Exit from ISR and wait for stschng interrupt with bsessvld = 1 */ -+ return 1; -+ } -+ -+ /* Switch on the voltage to the core */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pwrdnswtch = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ dwc_udelay(10); -+ -+ /* Reset the core */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pwrdnrstn = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ dwc_udelay(10); -+ -+ /* Disable power clamps */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pwrdnclmp = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ -+ /* Remove reset the core signal */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pwrdnrstn = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); -+ dwc_udelay(10); -+ -+ /* Disable PMU interrupt */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pmuintsel = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ dwc_udelay(10); -+ -+ /*Indicates that we are exiting from hibernation */ -+ core_if->hibernation_suspend = 0; -+ -+ /* Disable PMU */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pmuactv = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ dwc_udelay(10); -+ -+ core_if->op_state = B_PERIPHERAL; -+ dwc_otg_core_init(core_if); -+ dwc_otg_enable_global_interrupts(core_if); -+ cil_pcd_start(core_if); -+ -+ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE || -+ otg_cap_param == DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE) { -+ /* -+ * Initiate SRP after initial ADP probe. -+ */ -+ dwc_otg_initiate_srp(core_if); -+ } -+ } -+ -+ return 1; -+} -+/** -+ * This interrupt indicates that the Wakeup Logic has detected a -+ * status change either on IDDIG or BSessVld. -+ */ -+static uint32_t dwc_otg_handle_pwrdn_stschng_intr(dwc_otg_device_t *otg_dev) -+{ -+ int retval; -+ gpwrdn_data_t gpwrdn = {.d32 = 0 }; -+ gpwrdn_data_t gpwrdn_temp = {.d32 = 0 }; -+ dwc_otg_core_if_t *core_if = otg_dev->core_if; -+ -+ DWC_PRINTF("%s called\n", __FUNCTION__); -+ -+ if (core_if->power_down == 2) { -+ if (core_if->hibernation_suspend <= 0) { -+ DWC_PRINTF("Already exited from Hibernation\n"); -+ return 1; -+ } else -+ gpwrdn_temp.d32 = core_if->gr_backup->gpwrdn_local; -+ -+ } else { -+ gpwrdn_temp.d32 = core_if->adp.gpwrdn; -+ } -+ -+ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); -+ -+ if (gpwrdn.b.idsts ^ gpwrdn_temp.b.idsts) { -+ retval = dwc_otg_handle_pwrdn_idsts_change(otg_dev); -+ } else if (gpwrdn.b.bsessvld ^ gpwrdn_temp.b.bsessvld) { -+ retval = dwc_otg_handle_pwrdn_session_change(core_if); -+ } -+ -+ return retval; -+} -+ -+/** -+ * This interrupt indicates that the Wakeup Logic has detected a -+ * SRP. -+ */ -+static int32_t dwc_otg_handle_pwrdn_srp_intr(dwc_otg_core_if_t * core_if) -+{ -+ gpwrdn_data_t gpwrdn = {.d32 = 0 }; -+ -+ DWC_PRINTF("%s called\n", __FUNCTION__); -+ -+ if (!core_if->hibernation_suspend) { -+ DWC_PRINTF("Already exited from Hibernation\n"); -+ return 1; -+ } -+#ifdef DWC_DEV_SRPCAP -+ if (core_if->pwron_timer_started) { -+ core_if->pwron_timer_started = 0; -+ DWC_TIMER_CANCEL(core_if->pwron_timer); -+ } -+#endif -+ -+ /* Switch on the voltage to the core */ -+ gpwrdn.b.pwrdnswtch = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ dwc_udelay(10); -+ -+ /* Reset the core */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pwrdnrstn = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ dwc_udelay(10); -+ -+ /* Disable power clamps */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pwrdnclmp = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ -+ /* Remove reset the core signal */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pwrdnrstn = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); -+ dwc_udelay(10); -+ -+ /* Disable PMU interrupt */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pmuintsel = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ -+ /* Indicates that we are exiting from hibernation */ -+ core_if->hibernation_suspend = 0; -+ -+ /* Disable PMU */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pmuactv = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ dwc_udelay(10); -+ -+ /* Programm Disable VBUS to 0 */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.dis_vbus = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ -+ /*Initialize the core as Host */ -+ core_if->op_state = A_HOST; -+ dwc_otg_core_init(core_if); -+ dwc_otg_enable_global_interrupts(core_if); -+ cil_hcd_start(core_if); -+ -+ return 1; -+} -+ -+/** This interrupt indicates that restore command after Hibernation -+ * was completed by the core. */ -+int32_t dwc_otg_handle_restore_done_intr(dwc_otg_core_if_t * core_if) -+{ -+ pcgcctl_data_t pcgcctl; -+ DWC_DEBUGPL(DBG_ANY, "++Restore Done Interrupt++\n"); -+ -+ //TODO De-assert restore signal. 8.a -+ pcgcctl.d32 = DWC_READ_REG32(core_if->pcgcctl); -+ if (pcgcctl.b.restoremode == 1) { -+ gintmsk_data_t gintmsk = {.d32 = 0 }; -+ /* -+ * If restore mode is Remote Wakeup, -+ * unmask Remote Wakeup interrupt. -+ */ -+ gintmsk.b.wkupintr = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, -+ 0, gintmsk.d32); -+ } -+ -+ return 1; -+} -+ -+/** -+ * This interrupt indicates that a device has been disconnected from -+ * the root port. -+ */ -+int32_t dwc_otg_handle_disconnect_intr(dwc_otg_core_if_t * core_if) -+{ -+ gintsts_data_t gintsts; -+ -+ DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n", -+ (dwc_otg_is_host_mode(core_if) ? "Host" : "Device"), -+ op_state_str(core_if)); -+ -+/** @todo Consolidate this if statement. */ -+#ifndef DWC_HOST_ONLY -+ if (core_if->op_state == B_HOST) { -+ /* If in device mode Disconnect and stop the HCD, then -+ * start the PCD. */ -+ DWC_SPINUNLOCK(core_if->lock); -+ cil_hcd_disconnect(core_if); -+ cil_pcd_start(core_if); -+ DWC_SPINLOCK(core_if->lock); -+ core_if->op_state = B_PERIPHERAL; -+ } else if (dwc_otg_is_device_mode(core_if)) { -+ gotgctl_data_t gotgctl = {.d32 = 0 }; -+ gotgctl.d32 = -+ DWC_READ_REG32(&core_if->core_global_regs->gotgctl); -+ if (gotgctl.b.hstsethnpen == 1) { -+ /* Do nothing, if HNP in process the OTG -+ * interrupt "Host Negotiation Detected" -+ * interrupt will do the mode switch. -+ */ -+ } else if (gotgctl.b.devhnpen == 0) { -+ /* If in device mode Disconnect and stop the HCD, then -+ * start the PCD. */ -+ DWC_SPINUNLOCK(core_if->lock); -+ cil_hcd_disconnect(core_if); -+ cil_pcd_start(core_if); -+ DWC_SPINLOCK(core_if->lock); -+ core_if->op_state = B_PERIPHERAL; -+ } else { -+ DWC_DEBUGPL(DBG_ANY, "!a_peripheral && !devhnpen\n"); -+ } -+ } else { -+ if (core_if->op_state == A_HOST) { -+ /* A-Cable still connected but device disconnected. */ -+ cil_hcd_disconnect(core_if); -+ if (core_if->adp_enable) { -+ gpwrdn_data_t gpwrdn = { .d32 = 0 }; -+ cil_hcd_stop(core_if); -+ /* Enable Power Down Logic */ -+ gpwrdn.b.pmuintsel = 1; -+ gpwrdn.b.pmuactv = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs-> -+ gpwrdn, 0, gpwrdn.d32); -+ dwc_otg_adp_probe_start(core_if); -+ -+ /* Power off the core */ -+ if (core_if->power_down == 2) { -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pwrdnswtch = 1; -+ DWC_MODIFY_REG32 -+ (&core_if->core_global_regs->gpwrdn, -+ gpwrdn.d32, 0); -+ } -+ } -+ } -+ } -+#endif -+ /* Change to L3(OFF) state */ -+ core_if->lx_state = DWC_OTG_L3; -+ -+ gintsts.d32 = 0; -+ gintsts.b.disconnect = 1; -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); -+ return 1; -+} -+ -+/** -+ * This interrupt indicates that SUSPEND state has been detected on -+ * the USB. -+ * -+ * For HNP the USB Suspend interrupt signals the change from -+ * "a_peripheral" to "a_host". -+ * -+ * When power management is enabled the core will be put in low power -+ * mode. -+ */ -+int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t * core_if) -+{ -+ dsts_data_t dsts; -+ gintsts_data_t gintsts; -+ dcfg_data_t dcfg; -+ -+ DWC_DEBUGPL(DBG_ANY, "USB SUSPEND\n"); -+ -+ if (dwc_otg_is_device_mode(core_if)) { -+ /* Check the Device status register to determine if the Suspend -+ * state is active. */ -+ dsts.d32 = -+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); -+ DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32); -+ DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d " -+ "HWCFG4.power Optimize=%d\n", -+ dsts.b.suspsts, core_if->hwcfg4.b.power_optimiz); -+ -+#ifdef PARTIAL_POWER_DOWN -+/** @todo Add a module parameter for power management. */ -+ -+ if (dsts.b.suspsts && core_if->hwcfg4.b.power_optimiz) { -+ pcgcctl_data_t power = {.d32 = 0 }; -+ DWC_DEBUGPL(DBG_CIL, "suspend\n"); -+ -+ power.b.pwrclmp = 1; -+ DWC_WRITE_REG32(core_if->pcgcctl, power.d32); -+ -+ power.b.rstpdwnmodule = 1; -+ DWC_MODIFY_REG32(core_if->pcgcctl, 0, power.d32); -+ -+ power.b.stoppclk = 1; -+ DWC_MODIFY_REG32(core_if->pcgcctl, 0, power.d32); -+ -+ } else { -+ DWC_DEBUGPL(DBG_ANY, "disconnect?\n"); -+ } -+#endif -+ /* PCD callback for suspend. Release the lock inside of callback function */ -+ cil_pcd_suspend(core_if); -+ if (core_if->power_down == 2) -+ { -+ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); -+ DWC_DEBUGPL(DBG_ANY,"lx_state = %08x\n",core_if->lx_state); -+ DWC_DEBUGPL(DBG_ANY," device address = %08d\n",dcfg.b.devaddr); -+ -+ if (core_if->lx_state != DWC_OTG_L3 && dcfg.b.devaddr) { -+ pcgcctl_data_t pcgcctl = {.d32 = 0 }; -+ gpwrdn_data_t gpwrdn = {.d32 = 0 }; -+ gusbcfg_data_t gusbcfg = {.d32 = 0 }; -+ -+ /* Change to L2(suspend) state */ -+ core_if->lx_state = DWC_OTG_L2; -+ -+ /* Clear interrupt in gintsts */ -+ gintsts.d32 = 0; -+ gintsts.b.usbsuspend = 1; -+ DWC_WRITE_REG32(&core_if->core_global_regs-> -+ gintsts, gintsts.d32); -+ DWC_PRINTF("Start of hibernation completed\n"); -+ dwc_otg_save_global_regs(core_if); -+ dwc_otg_save_dev_regs(core_if); -+ -+ gusbcfg.d32 = -+ DWC_READ_REG32(&core_if->core_global_regs-> -+ gusbcfg); -+ if (gusbcfg.b.ulpi_utmi_sel == 1) { -+ /* ULPI interface */ -+ /* Suspend the Phy Clock */ -+ pcgcctl.d32 = 0; -+ pcgcctl.b.stoppclk = 1; -+ DWC_MODIFY_REG32(core_if->pcgcctl, 0, -+ pcgcctl.d32); -+ dwc_udelay(10); -+ gpwrdn.b.pmuactv = 1; -+ DWC_MODIFY_REG32(&core_if-> -+ core_global_regs-> -+ gpwrdn, 0, gpwrdn.d32); -+ } else { -+ /* UTMI+ Interface */ -+ gpwrdn.b.pmuactv = 1; -+ DWC_MODIFY_REG32(&core_if-> -+ core_global_regs-> -+ gpwrdn, 0, gpwrdn.d32); -+ dwc_udelay(10); -+ pcgcctl.b.stoppclk = 1; -+ DWC_MODIFY_REG32(core_if->pcgcctl, 0, -+ pcgcctl.d32); -+ dwc_udelay(10); -+ } -+ -+ /* Set flag to indicate that we are in hibernation */ -+ core_if->hibernation_suspend = 1; -+ /* Enable interrupts from wake up logic */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pmuintsel = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs-> -+ gpwrdn, 0, gpwrdn.d32); -+ dwc_udelay(10); -+ -+ /* Unmask device mode interrupts in GPWRDN */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.rst_det_msk = 1; -+ gpwrdn.b.lnstchng_msk = 1; -+ gpwrdn.b.sts_chngint_msk = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs-> -+ gpwrdn, 0, gpwrdn.d32); -+ dwc_udelay(10); -+ -+ /* Enable Power Down Clamp */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pwrdnclmp = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs-> -+ gpwrdn, 0, gpwrdn.d32); -+ dwc_udelay(10); -+ -+ /* Switch off VDD */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pwrdnswtch = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs-> -+ gpwrdn, 0, gpwrdn.d32); -+ -+ /* Save gpwrdn register for further usage if stschng interrupt */ -+ core_if->gr_backup->gpwrdn_local = -+ DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); -+ DWC_PRINTF("Hibernation completed\n"); -+ -+ return 1; -+ } -+ } else if (core_if->power_down == 3) { -+ pcgcctl_data_t pcgcctl = {.d32 = 0 }; -+ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); -+ DWC_DEBUGPL(DBG_ANY, "lx_state = %08x\n",core_if->lx_state); -+ DWC_DEBUGPL(DBG_ANY, " device address = %08d\n",dcfg.b.devaddr); -+ -+ if (core_if->lx_state != DWC_OTG_L3 && dcfg.b.devaddr) { -+ DWC_DEBUGPL(DBG_ANY, "Start entering to extended hibernation\n"); -+ core_if->xhib = 1; -+ -+ /* Clear interrupt in gintsts */ -+ gintsts.d32 = 0; -+ gintsts.b.usbsuspend = 1; -+ DWC_WRITE_REG32(&core_if->core_global_regs-> -+ gintsts, gintsts.d32); -+ -+ dwc_otg_save_global_regs(core_if); -+ dwc_otg_save_dev_regs(core_if); -+ -+ /* Wait for 10 PHY clocks */ -+ dwc_udelay(10); -+ -+ /* Program GPIO register while entering to xHib */ -+ DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, 0x1); -+ -+ pcgcctl.b.enbl_extnd_hiber = 1; -+ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32); -+ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32); -+ -+ pcgcctl.d32 = 0; -+ pcgcctl.b.extnd_hiber_pwrclmp = 1; -+ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32); -+ -+ pcgcctl.d32 = 0; -+ pcgcctl.b.extnd_hiber_switch = 1; -+ core_if->gr_backup->xhib_gpwrdn = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); -+ core_if->gr_backup->xhib_pcgcctl = DWC_READ_REG32(core_if->pcgcctl) | pcgcctl.d32; -+ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32); -+ -+ DWC_DEBUGPL(DBG_ANY, "Finished entering to extended hibernation\n"); -+ -+ return 1; -+ } -+ } -+ } else { -+ if (core_if->op_state == A_PERIPHERAL) { -+ DWC_DEBUGPL(DBG_ANY, "a_peripheral->a_host\n"); -+ /* Clear the a_peripheral flag, back to a_host. */ -+ DWC_SPINUNLOCK(core_if->lock); -+ cil_pcd_stop(core_if); -+ cil_hcd_start(core_if); -+ DWC_SPINLOCK(core_if->lock); -+ core_if->op_state = A_HOST; -+ } -+ } -+ -+ /* Change to L2(suspend) state */ -+ core_if->lx_state = DWC_OTG_L2; -+ -+ /* Clear interrupt */ -+ gintsts.d32 = 0; -+ gintsts.b.usbsuspend = 1; -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); -+ -+ return 1; -+} -+ -+static int32_t dwc_otg_handle_xhib_exit_intr(dwc_otg_core_if_t * core_if) -+{ -+ gpwrdn_data_t gpwrdn = {.d32 = 0 }; -+ pcgcctl_data_t pcgcctl = {.d32 = 0 }; -+ gahbcfg_data_t gahbcfg = {.d32 = 0 }; -+ -+ dwc_udelay(10); -+ -+ /* Program GPIO register while entering to xHib */ -+ DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, 0x0); -+ -+ pcgcctl.d32 = core_if->gr_backup->xhib_pcgcctl; -+ pcgcctl.b.extnd_hiber_pwrclmp = 0; -+ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32); -+ dwc_udelay(10); -+ -+ gpwrdn.d32 = core_if->gr_backup->xhib_gpwrdn; -+ gpwrdn.b.restore = 1; -+ DWC_WRITE_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32); -+ dwc_udelay(10); -+ -+ restore_lpm_i2c_regs(core_if); -+ -+ pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14); -+ pcgcctl.b.max_xcvrselect = 1; -+ pcgcctl.b.ess_reg_restored = 0; -+ pcgcctl.b.extnd_hiber_switch = 0; -+ pcgcctl.b.extnd_hiber_pwrclmp = 0; -+ pcgcctl.b.enbl_extnd_hiber = 1; -+ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32); -+ -+ gahbcfg.d32 = core_if->gr_backup->gahbcfg_local; -+ gahbcfg.b.glblintrmsk = 1; -+ DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gahbcfg.d32); -+ -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0x1 << 16); -+ -+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, -+ core_if->gr_backup->gusbcfg_local); -+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, -+ core_if->dr_backup->dcfg); -+ -+ pcgcctl.d32 = 0; -+ pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14); -+ pcgcctl.b.max_xcvrselect = 1; -+ pcgcctl.d32 |= 0x608; -+ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32); -+ dwc_udelay(10); -+ -+ pcgcctl.d32 = 0; -+ pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14); -+ pcgcctl.b.max_xcvrselect = 1; -+ pcgcctl.b.ess_reg_restored = 1; -+ pcgcctl.b.enbl_extnd_hiber = 1; -+ pcgcctl.b.rstpdwnmodule = 1; -+ pcgcctl.b.restoremode = 1; -+ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32); -+ -+ DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__); -+ -+ return 1; -+} -+ -+#ifdef CONFIG_USB_DWC_OTG_LPM -+/** -+ * This function hadles LPM transaction received interrupt. -+ */ -+static int32_t dwc_otg_handle_lpm_intr(dwc_otg_core_if_t * core_if) -+{ -+ glpmcfg_data_t lpmcfg; -+ gintsts_data_t gintsts; -+ -+ if (!core_if->core_params->lpm_enable) { -+ DWC_PRINTF("Unexpected LPM interrupt\n"); -+ } -+ -+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); -+ DWC_PRINTF("LPM config register = 0x%08x\n", lpmcfg.d32); -+ -+ if (dwc_otg_is_host_mode(core_if)) { -+ cil_hcd_sleep(core_if); -+ } else { -+ lpmcfg.b.hird_thres |= (1 << 4); -+ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, -+ lpmcfg.d32); -+ } -+ -+ /* Examine prt_sleep_sts after TL1TokenTetry period max (10 us) */ -+ dwc_udelay(10); -+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); -+ if (lpmcfg.b.prt_sleep_sts) { -+ /* Save the current state */ -+ core_if->lx_state = DWC_OTG_L1; -+ } -+ -+ /* Clear interrupt */ -+ gintsts.d32 = 0; -+ gintsts.b.lpmtranrcvd = 1; -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); -+ return 1; -+} -+#endif /* CONFIG_USB_DWC_OTG_LPM */ -+ -+/** -+ * This function returns the Core Interrupt register. -+ */ -+static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t * core_if, gintmsk_data_t *reenable_gintmsk, dwc_otg_hcd_t *hcd) -+{ -+ gahbcfg_data_t gahbcfg = {.d32 = 0 }; -+ gintsts_data_t gintsts; -+ gintmsk_data_t gintmsk; -+ gintmsk_data_t gintmsk_common = {.d32 = 0 }; -+ gintmsk_common.b.wkupintr = 1; -+ gintmsk_common.b.sessreqintr = 1; -+ gintmsk_common.b.conidstschng = 1; -+ gintmsk_common.b.otgintr = 1; -+ gintmsk_common.b.modemismatch = 1; -+ gintmsk_common.b.disconnect = 1; -+ gintmsk_common.b.usbsuspend = 1; -+#ifdef CONFIG_USB_DWC_OTG_LPM -+ gintmsk_common.b.lpmtranrcvd = 1; -+#endif -+ gintmsk_common.b.restoredone = 1; -+ if(dwc_otg_is_device_mode(core_if)) -+ { -+ /** @todo: The port interrupt occurs while in device -+ * mode. Added code to CIL to clear the interrupt for now! -+ */ -+ gintmsk_common.b.portintr = 1; -+ } -+ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts); -+ gintmsk.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk); -+ if(fiq_enable) { -+ local_fiq_disable(); -+ /* Pull in the interrupts that the FIQ has masked */ -+ gintmsk.d32 |= ~(hcd->fiq_state->gintmsk_saved.d32); -+ gintmsk.d32 |= gintmsk_common.d32; -+ /* for the upstairs function to reenable - have to read it here in case FIQ triggers again */ -+ reenable_gintmsk->d32 = gintmsk.d32; -+ local_fiq_enable(); -+ } -+ -+ gahbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg); -+ -+#ifdef DEBUG -+ /* if any common interrupts set */ -+ if (gintsts.d32 & gintmsk_common.d32) { -+ DWC_DEBUGPL(DBG_ANY, "common_intr: gintsts=%08x gintmsk=%08x\n", -+ gintsts.d32, gintmsk.d32); -+ } -+#endif -+ if (!fiq_enable){ -+ if (gahbcfg.b.glblintrmsk) -+ return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32); -+ else -+ return 0; -+ } else { -+ /* Our IRQ kicker is no longer the USB hardware, it's the MPHI interface. -+ * Can't trust the global interrupt mask bit in this case. -+ */ -+ return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32); -+ } -+ -+} -+ -+/* MACRO for clearing interupt bits in GPWRDN register */ -+#define CLEAR_GPWRDN_INTR(__core_if,__intr) \ -+do { \ -+ gpwrdn_data_t gpwrdn = {.d32=0}; \ -+ gpwrdn.b.__intr = 1; \ -+ DWC_MODIFY_REG32(&__core_if->core_global_regs->gpwrdn, \ -+ 0, gpwrdn.d32); \ -+} while (0) -+ -+/** -+ * Common interrupt handler. -+ * -+ * The common interrupts are those that occur in both Host and Device mode. -+ * This handler handles the following interrupts: -+ * - Mode Mismatch Interrupt -+ * - Disconnect Interrupt -+ * - OTG Interrupt -+ * - Connector ID Status Change Interrupt -+ * - Session Request Interrupt. -+ * - Resume / Remote Wakeup Detected Interrupt. -+ * - LPM Transaction Received Interrupt -+ * - ADP Transaction Received Interrupt -+ * -+ */ -+int32_t dwc_otg_handle_common_intr(void *dev) -+{ -+ int retval = 0; -+ gintsts_data_t gintsts; -+ gintmsk_data_t gintmsk_reenable = { .d32 = 0 }; -+ gpwrdn_data_t gpwrdn = {.d32 = 0 }; -+ dwc_otg_device_t *otg_dev = dev; -+ dwc_otg_core_if_t *core_if = otg_dev->core_if; -+ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); -+ if (dwc_otg_is_device_mode(core_if)) -+ core_if->frame_num = dwc_otg_get_frame_number(core_if); -+ -+ if (core_if->lock) -+ DWC_SPINLOCK(core_if->lock); -+ -+ if (core_if->power_down == 3 && core_if->xhib == 1) { -+ DWC_DEBUGPL(DBG_ANY, "Exiting from xHIB state\n"); -+ retval |= dwc_otg_handle_xhib_exit_intr(core_if); -+ core_if->xhib = 2; -+ if (core_if->lock) -+ DWC_SPINUNLOCK(core_if->lock); -+ -+ return retval; -+ } -+ -+ if (core_if->hibernation_suspend <= 0) { -+ /* read_common will have to poke the FIQ's saved mask. We must then clear this mask at the end -+ * of this handler - god only knows why it's done like this -+ */ -+ gintsts.d32 = dwc_otg_read_common_intr(core_if, &gintmsk_reenable, otg_dev->hcd); -+ -+ if (gintsts.b.modemismatch) { -+ retval |= dwc_otg_handle_mode_mismatch_intr(core_if); -+ } -+ if (gintsts.b.otgintr) { -+ retval |= dwc_otg_handle_otg_intr(core_if); -+ } -+ if (gintsts.b.conidstschng) { -+ retval |= -+ dwc_otg_handle_conn_id_status_change_intr(core_if); -+ } -+ if (gintsts.b.disconnect) { -+ retval |= dwc_otg_handle_disconnect_intr(core_if); -+ } -+ if (gintsts.b.sessreqintr) { -+ retval |= dwc_otg_handle_session_req_intr(core_if); -+ } -+ if (gintsts.b.wkupintr) { -+ retval |= dwc_otg_handle_wakeup_detected_intr(core_if); -+ } -+ if (gintsts.b.usbsuspend) { -+ retval |= dwc_otg_handle_usb_suspend_intr(core_if); -+ } -+#ifdef CONFIG_USB_DWC_OTG_LPM -+ if (gintsts.b.lpmtranrcvd) { -+ retval |= dwc_otg_handle_lpm_intr(core_if); -+ } -+#endif -+ if (gintsts.b.restoredone) { -+ gintsts.d32 = 0; -+ if (core_if->power_down == 2) -+ core_if->hibernation_suspend = -1; -+ else if (core_if->power_down == 3 && core_if->xhib == 2) { -+ gpwrdn_data_t gpwrdn = {.d32 = 0 }; -+ pcgcctl_data_t pcgcctl = {.d32 = 0 }; -+ dctl_data_t dctl = {.d32 = 0 }; -+ -+ DWC_WRITE_REG32(&core_if->core_global_regs-> -+ gintsts, 0xFFFFFFFF); -+ -+ DWC_DEBUGPL(DBG_ANY, -+ "RESTORE DONE generated\n"); -+ -+ gpwrdn.b.restore = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ dwc_udelay(10); -+ -+ pcgcctl.b.rstpdwnmodule = 1; -+ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0); -+ -+ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, core_if->gr_backup->gusbcfg_local); -+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, core_if->dr_backup->dcfg); -+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, core_if->dr_backup->dctl); -+ dwc_udelay(50); -+ -+ dctl.b.pwronprgdone = 1; -+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32); -+ dwc_udelay(10); -+ -+ dwc_otg_restore_global_regs(core_if); -+ dwc_otg_restore_dev_regs(core_if, 0); -+ -+ dctl.d32 = 0; -+ dctl.b.pwronprgdone = 1; -+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0); -+ dwc_udelay(10); -+ -+ pcgcctl.d32 = 0; -+ pcgcctl.b.enbl_extnd_hiber = 1; -+ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0); -+ -+ /* The core will be in ON STATE */ -+ core_if->lx_state = DWC_OTG_L0; -+ core_if->xhib = 0; -+ -+ DWC_SPINUNLOCK(core_if->lock); -+ if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) { -+ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p); -+ } -+ DWC_SPINLOCK(core_if->lock); -+ -+ } -+ -+ gintsts.b.restoredone = 1; -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32); -+ DWC_PRINTF(" --Restore done interrupt received-- \n"); -+ retval |= 1; -+ } -+ if (gintsts.b.portintr && dwc_otg_is_device_mode(core_if)) { -+ /* The port interrupt occurs while in device mode with HPRT0 -+ * Port Enable/Disable. -+ */ -+ gintsts.d32 = 0; -+ gintsts.b.portintr = 1; -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32); -+ retval |= 1; -+ gintmsk_reenable.b.portintr = 1; -+ -+ } -+ /* Did we actually handle anything? if so, unmask the interrupt */ -+// fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "CILOUT %1d", retval); -+// fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "%08x", gintsts.d32); -+// fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "%08x", gintmsk_reenable.d32); -+ if (retval && fiq_enable) { -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk_reenable.d32); -+ } -+ -+ } else { -+ DWC_DEBUGPL(DBG_ANY, "gpwrdn=%08x\n", gpwrdn.d32); -+ -+ if (gpwrdn.b.disconn_det && gpwrdn.b.disconn_det_msk) { -+ CLEAR_GPWRDN_INTR(core_if, disconn_det); -+ if (gpwrdn.b.linestate == 0) { -+ dwc_otg_handle_pwrdn_disconnect_intr(core_if); -+ } else { -+ DWC_PRINTF("Disconnect detected while linestate is not 0\n"); -+ } -+ -+ retval |= 1; -+ } -+ if (gpwrdn.b.lnstschng && gpwrdn.b.lnstchng_msk) { -+ CLEAR_GPWRDN_INTR(core_if, lnstschng); -+ /* remote wakeup from hibernation */ -+ if (gpwrdn.b.linestate == 2 || gpwrdn.b.linestate == 1) { -+ dwc_otg_handle_pwrdn_wakeup_detected_intr(core_if); -+ } else { -+ DWC_PRINTF("gpwrdn.linestate = %d\n", gpwrdn.b.linestate); -+ } -+ retval |= 1; -+ } -+ if (gpwrdn.b.rst_det && gpwrdn.b.rst_det_msk) { -+ CLEAR_GPWRDN_INTR(core_if, rst_det); -+ if (gpwrdn.b.linestate == 0) { -+ DWC_PRINTF("Reset detected\n"); -+ retval |= dwc_otg_device_hibernation_restore(core_if, 0, 1); -+ } -+ } -+ if (gpwrdn.b.srp_det && gpwrdn.b.srp_det_msk) { -+ CLEAR_GPWRDN_INTR(core_if, srp_det); -+ dwc_otg_handle_pwrdn_srp_intr(core_if); -+ retval |= 1; -+ } -+ } -+ /* Handle ADP interrupt here */ -+ if (gpwrdn.b.adp_int) { -+ DWC_PRINTF("ADP interrupt\n"); -+ CLEAR_GPWRDN_INTR(core_if, adp_int); -+ dwc_otg_adp_handle_intr(core_if); -+ retval |= 1; -+ } -+ if (gpwrdn.b.sts_chngint && gpwrdn.b.sts_chngint_msk) { -+ DWC_PRINTF("STS CHNG interrupt asserted\n"); -+ CLEAR_GPWRDN_INTR(core_if, sts_chngint); -+ dwc_otg_handle_pwrdn_stschng_intr(otg_dev); -+ -+ retval |= 1; -+ } -+ if (core_if->lock) -+ DWC_SPINUNLOCK(core_if->lock); -+ return retval; -+} -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_core_if.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_core_if.h ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_core_if.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_core_if.h 2015-11-29 09:42:39.919098694 +0100 -@@ -0,0 +1,705 @@ -+/* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_core_if.h $ -+ * $Revision: #13 $ -+ * $Date: 2012/08/10 $ -+ * $Change: 2047372 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+#if !defined(__DWC_CORE_IF_H__) -+#define __DWC_CORE_IF_H__ -+ -+#include "dwc_os.h" -+ -+/** @file -+ * This file defines DWC_OTG Core API -+ */ -+ -+struct dwc_otg_core_if; -+typedef struct dwc_otg_core_if dwc_otg_core_if_t; -+ -+/** Maximum number of Periodic FIFOs */ -+#define MAX_PERIO_FIFOS 15 -+/** Maximum number of Periodic FIFOs */ -+#define MAX_TX_FIFOS 15 -+ -+/** Maximum number of Endpoints/HostChannels */ -+#define MAX_EPS_CHANNELS 16 -+ -+extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * _reg_base_addr); -+extern void dwc_otg_core_init(dwc_otg_core_if_t * _core_if); -+extern void dwc_otg_cil_remove(dwc_otg_core_if_t * _core_if); -+ -+extern void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * _core_if); -+extern void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * _core_if); -+ -+extern uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if); -+extern uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if); -+ -+extern uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if); -+ -+/** This function should be called on every hardware interrupt. */ -+extern int32_t dwc_otg_handle_common_intr(void *otg_dev); -+ -+/** @name OTG Core Parameters */ -+/** @{ */ -+ -+/** -+ * Specifies the OTG capabilities. The driver will automatically -+ * detect the value for this parameter if none is specified. -+ * 0 - HNP and SRP capable (default) -+ * 1 - SRP Only capable -+ * 2 - No HNP/SRP capable -+ */ -+extern int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val); -+extern int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if); -+#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0 -+#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1 -+#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 -+#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE -+ -+extern int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val); -+extern int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if); -+#define dwc_param_opt_default 1 -+ -+/** -+ * Specifies whether to use slave or DMA mode for accessing the data -+ * FIFOs. The driver will automatically detect the value for this -+ * parameter if none is specified. -+ * 0 - Slave -+ * 1 - DMA (default, if available) -+ */ -+extern int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if, -+ int32_t val); -+extern int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if); -+#define dwc_param_dma_enable_default 1 -+ -+/** -+ * When DMA mode is enabled specifies whether to use -+ * address DMA or DMA Descritor mode for accessing the data -+ * FIFOs in device mode. The driver will automatically detect -+ * the value for this parameter if none is specified. -+ * 0 - address DMA -+ * 1 - DMA Descriptor(default, if available) -+ */ -+extern int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if, -+ int32_t val); -+extern int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if); -+//#define dwc_param_dma_desc_enable_default 1 -+#define dwc_param_dma_desc_enable_default 0 // Broadcom BCM2708 -+ -+/** The DMA Burst size (applicable only for External DMA -+ * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32) -+ */ -+extern int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if, -+ int32_t val); -+extern int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if); -+#define dwc_param_dma_burst_size_default 32 -+ -+/** -+ * Specifies the maximum speed of operation in host and device mode. -+ * The actual speed depends on the speed of the attached device and -+ * the value of phy_type. The actual speed depends on the speed of the -+ * attached device. -+ * 0 - High Speed (default) -+ * 1 - Full Speed -+ */ -+extern int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val); -+extern int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if); -+#define dwc_param_speed_default 0 -+#define DWC_SPEED_PARAM_HIGH 0 -+#define DWC_SPEED_PARAM_FULL 1 -+ -+/** Specifies whether low power mode is supported when attached -+ * to a Full Speed or Low Speed device in host mode. -+ * 0 - Don't support low power mode (default) -+ * 1 - Support low power mode -+ */ -+extern int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t * -+ core_if, int32_t val); -+extern int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t -+ * core_if); -+#define dwc_param_host_support_fs_ls_low_power_default 0 -+ -+/** Specifies the PHY clock rate in low power mode when connected to a -+ * Low Speed device in host mode. This parameter is applicable only if -+ * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS -+ * then defaults to 6 MHZ otherwise 48 MHZ. -+ * -+ * 0 - 48 MHz -+ * 1 - 6 MHz -+ */ -+extern int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * -+ core_if, int32_t val); -+extern int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * -+ core_if); -+#define dwc_param_host_ls_low_power_phy_clk_default 0 -+#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 -+#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 -+ -+/** -+ * 0 - Use cC FIFO size parameters -+ * 1 - Allow dynamic FIFO sizing (default) -+ */ -+extern int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if, -+ int32_t val); -+extern int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t * -+ core_if); -+#define dwc_param_enable_dynamic_fifo_default 1 -+ -+/** Total number of 4-byte words in the data FIFO memory. This -+ * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic -+ * Tx FIFOs. -+ * 32 to 32768 (default 8192) -+ * Note: The total FIFO memory depth in the FPGA configuration is 8192. -+ */ -+extern int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if, -+ int32_t val); -+extern int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if); -+//#define dwc_param_data_fifo_size_default 8192 -+#define dwc_param_data_fifo_size_default 0xFF0 // Broadcom BCM2708 -+ -+/** Number of 4-byte words in the Rx FIFO in device mode when dynamic -+ * FIFO sizing is enabled. -+ * 16 to 32768 (default 1064) -+ */ -+extern int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if, -+ int32_t val); -+extern int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if); -+#define dwc_param_dev_rx_fifo_size_default 1064 -+ -+/** Number of 4-byte words in the non-periodic Tx FIFO in device mode -+ * when dynamic FIFO sizing is enabled. -+ * 16 to 32768 (default 1024) -+ */ -+extern int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * -+ core_if, int32_t val); -+extern int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * -+ core_if); -+#define dwc_param_dev_nperio_tx_fifo_size_default 1024 -+ -+/** Number of 4-byte words in each of the periodic Tx FIFOs in device -+ * mode when dynamic FIFO sizing is enabled. -+ * 4 to 768 (default 256) -+ */ -+extern int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if, -+ int32_t val, int fifo_num); -+extern int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * -+ core_if, int fifo_num); -+#define dwc_param_dev_perio_tx_fifo_size_default 256 -+ -+/** Number of 4-byte words in the Rx FIFO in host mode when dynamic -+ * FIFO sizing is enabled. -+ * 16 to 32768 (default 1024) -+ */ -+extern int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if, -+ int32_t val); -+extern int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if); -+//#define dwc_param_host_rx_fifo_size_default 1024 -+#define dwc_param_host_rx_fifo_size_default 774 // Broadcom BCM2708 -+ -+/** Number of 4-byte words in the non-periodic Tx FIFO in host mode -+ * when Dynamic FIFO sizing is enabled in the core. -+ * 16 to 32768 (default 1024) -+ */ -+extern int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * -+ core_if, int32_t val); -+extern int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * -+ core_if); -+//#define dwc_param_host_nperio_tx_fifo_size_default 1024 -+#define dwc_param_host_nperio_tx_fifo_size_default 0x100 // Broadcom BCM2708 -+ -+/** Number of 4-byte words in the host periodic Tx FIFO when dynamic -+ * FIFO sizing is enabled. -+ * 16 to 32768 (default 1024) -+ */ -+extern int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * -+ core_if, int32_t val); -+extern int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * -+ core_if); -+//#define dwc_param_host_perio_tx_fifo_size_default 1024 -+#define dwc_param_host_perio_tx_fifo_size_default 0x200 // Broadcom BCM2708 -+ -+/** The maximum transfer size supported in bytes. -+ * 2047 to 65,535 (default 65,535) -+ */ -+extern int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if, -+ int32_t val); -+extern int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if); -+#define dwc_param_max_transfer_size_default 65535 -+ -+/** The maximum number of packets in a transfer. -+ * 15 to 511 (default 511) -+ */ -+extern int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if, -+ int32_t val); -+extern int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if); -+#define dwc_param_max_packet_count_default 511 -+ -+/** The number of host channel registers to use. -+ * 1 to 16 (default 12) -+ * Note: The FPGA configuration supports a maximum of 12 host channels. -+ */ -+extern int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if, -+ int32_t val); -+extern int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if); -+//#define dwc_param_host_channels_default 12 -+#define dwc_param_host_channels_default 8 // Broadcom BCM2708 -+ -+/** The number of endpoints in addition to EP0 available for device -+ * mode operations. -+ * 1 to 15 (default 6 IN and OUT) -+ * Note: The FPGA configuration supports a maximum of 6 IN and OUT -+ * endpoints in addition to EP0. -+ */ -+extern int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if, -+ int32_t val); -+extern int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if); -+#define dwc_param_dev_endpoints_default 6 -+ -+/** -+ * Specifies the type of PHY interface to use. By default, the driver -+ * will automatically detect the phy_type. -+ * -+ * 0 - Full Speed PHY -+ * 1 - UTMI+ (default) -+ * 2 - ULPI -+ */ -+extern int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val); -+extern int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if); -+#define DWC_PHY_TYPE_PARAM_FS 0 -+#define DWC_PHY_TYPE_PARAM_UTMI 1 -+#define DWC_PHY_TYPE_PARAM_ULPI 2 -+#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI -+ -+/** -+ * Specifies the UTMI+ Data Width. This parameter is -+ * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI -+ * PHY_TYPE, this parameter indicates the data width between -+ * the MAC and the ULPI Wrapper.) Also, this parameter is -+ * applicable only if the OTG_HSPHY_WIDTH cC parameter was set -+ * to "8 and 16 bits", meaning that the core has been -+ * configured to work at either data path width. -+ * -+ * 8 or 16 bits (default 16) -+ */ -+extern int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if, -+ int32_t val); -+extern int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if); -+//#define dwc_param_phy_utmi_width_default 16 -+#define dwc_param_phy_utmi_width_default 8 // Broadcom BCM2708 -+ -+/** -+ * Specifies whether the ULPI operates at double or single -+ * data rate. This parameter is only applicable if PHY_TYPE is -+ * ULPI. -+ * -+ * 0 - single data rate ULPI interface with 8 bit wide data -+ * bus (default) -+ * 1 - double data rate ULPI interface with 4 bit wide data -+ * bus -+ */ -+extern int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if, -+ int32_t val); -+extern int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if); -+#define dwc_param_phy_ulpi_ddr_default 0 -+ -+/** -+ * Specifies whether to use the internal or external supply to -+ * drive the vbus with a ULPI phy. -+ */ -+extern int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if, -+ int32_t val); -+extern int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if); -+#define DWC_PHY_ULPI_INTERNAL_VBUS 0 -+#define DWC_PHY_ULPI_EXTERNAL_VBUS 1 -+#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS -+ -+/** -+ * Specifies whether to use the I2Cinterface for full speed PHY. This -+ * parameter is only applicable if PHY_TYPE is FS. -+ * 0 - No (default) -+ * 1 - Yes -+ */ -+extern int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if, -+ int32_t val); -+extern int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if); -+#define dwc_param_i2c_enable_default 0 -+ -+extern int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if, -+ int32_t val); -+extern int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if); -+#define dwc_param_ulpi_fs_ls_default 0 -+ -+extern int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val); -+extern int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if); -+#define dwc_param_ts_dline_default 0 -+ -+/** -+ * Specifies whether dedicated transmit FIFOs are -+ * enabled for non periodic IN endpoints in device mode -+ * 0 - No -+ * 1 - Yes -+ */ -+extern int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if, -+ int32_t val); -+extern int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t * -+ core_if); -+#define dwc_param_en_multiple_tx_fifo_default 1 -+ -+/** Number of 4-byte words in each of the Tx FIFOs in device -+ * mode when dynamic FIFO sizing is enabled. -+ * 4 to 768 (default 256) -+ */ -+extern int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, -+ int fifo_num, int32_t val); -+extern int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, -+ int fifo_num); -+#define dwc_param_dev_tx_fifo_size_default 768 -+ -+/** Thresholding enable flag- -+ * bit 0 - enable non-ISO Tx thresholding -+ * bit 1 - enable ISO Tx thresholding -+ * bit 2 - enable Rx thresholding -+ */ -+extern int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val); -+extern int32_t dwc_otg_get_thr_ctl(dwc_otg_core_if_t * core_if, int fifo_num); -+#define dwc_param_thr_ctl_default 0 -+ -+/** Thresholding length for Tx -+ * FIFOs in 32 bit DWORDs -+ */ -+extern int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if, -+ int32_t val); -+extern int32_t dwc_otg_get_tx_thr_length(dwc_otg_core_if_t * core_if); -+#define dwc_param_tx_thr_length_default 64 -+ -+/** Thresholding length for Rx -+ * FIFOs in 32 bit DWORDs -+ */ -+extern int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if, -+ int32_t val); -+extern int32_t dwc_otg_get_rx_thr_length(dwc_otg_core_if_t * core_if); -+#define dwc_param_rx_thr_length_default 64 -+ -+/** -+ * Specifies whether LPM (Link Power Management) support is enabled -+ */ -+extern int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if, -+ int32_t val); -+extern int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if); -+#define dwc_param_lpm_enable_default 1 -+ -+/** -+ * Specifies whether PTI enhancement is enabled -+ */ -+extern int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if, -+ int32_t val); -+extern int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if); -+#define dwc_param_pti_enable_default 0 -+ -+/** -+ * Specifies whether MPI enhancement is enabled -+ */ -+extern int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if, -+ int32_t val); -+extern int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if); -+#define dwc_param_mpi_enable_default 0 -+ -+/** -+ * Specifies whether ADP capability is enabled -+ */ -+extern int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if, -+ int32_t val); -+extern int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if); -+#define dwc_param_adp_enable_default 0 -+ -+/** -+ * Specifies whether IC_USB capability is enabled -+ */ -+ -+extern int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if, -+ int32_t val); -+extern int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if); -+#define dwc_param_ic_usb_cap_default 0 -+ -+extern int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if, -+ int32_t val); -+extern int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if); -+#define dwc_param_ahb_thr_ratio_default 0 -+ -+extern int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if, -+ int32_t val); -+extern int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if); -+#define dwc_param_power_down_default 0 -+ -+extern int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if, -+ int32_t val); -+extern int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if); -+#define dwc_param_reload_ctl_default 0 -+ -+extern int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if, -+ int32_t val); -+extern int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if); -+#define dwc_param_dev_out_nak_default 0 -+ -+extern int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if, -+ int32_t val); -+extern int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if); -+#define dwc_param_cont_on_bna_default 0 -+ -+extern int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if, -+ int32_t val); -+extern int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if); -+#define dwc_param_ahb_single_default 0 -+ -+extern int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val); -+extern int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if); -+#define dwc_param_otg_ver_default 0 -+ -+/** @} */ -+ -+/** @name Access to registers and bit-fields */ -+ -+/** -+ * Dump core registers and SPRAM -+ */ -+extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * _core_if); -+extern void dwc_otg_dump_spram(dwc_otg_core_if_t * _core_if); -+extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t * _core_if); -+extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t * _core_if); -+ -+/** -+ * Get host negotiation status. -+ */ -+extern uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if); -+ -+/** -+ * Get srp status -+ */ -+extern uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if); -+ -+/** -+ * Set hnpreq bit in the GOTGCTL register. -+ */ -+extern void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val); -+ -+/** -+ * Get Content of SNPSID register. -+ */ -+extern uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if); -+ -+/** -+ * Get current mode. -+ * Returns 0 if in device mode, and 1 if in host mode. -+ */ -+extern uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if); -+ -+/** -+ * Get value of hnpcapable field in the GUSBCFG register -+ */ -+extern uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if); -+/** -+ * Set value of hnpcapable field in the GUSBCFG register -+ */ -+extern void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val); -+ -+/** -+ * Get value of srpcapable field in the GUSBCFG register -+ */ -+extern uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if); -+/** -+ * Set value of srpcapable field in the GUSBCFG register -+ */ -+extern void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val); -+ -+/** -+ * Get value of devspeed field in the DCFG register -+ */ -+extern uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if); -+/** -+ * Set value of devspeed field in the DCFG register -+ */ -+extern void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val); -+ -+/** -+ * Get the value of busconnected field from the HPRT0 register -+ */ -+extern uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if); -+ -+/** -+ * Gets the device enumeration Speed. -+ */ -+extern uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if); -+ -+/** -+ * Get value of prtpwr field from the HPRT0 register -+ */ -+extern uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if); -+ -+/** -+ * Get value of flag indicating core state - hibernated or not -+ */ -+extern uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if); -+ -+/** -+ * Set value of prtpwr field from the HPRT0 register -+ */ -+extern void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val); -+ -+/** -+ * Get value of prtsusp field from the HPRT0 regsiter -+ */ -+extern uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if); -+/** -+ * Set value of prtpwr field from the HPRT0 register -+ */ -+extern void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val); -+ -+/** -+ * Get value of ModeChTimEn field from the HCFG regsiter -+ */ -+extern uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if); -+/** -+ * Set value of ModeChTimEn field from the HCFG regsiter -+ */ -+extern void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val); -+ -+/** -+ * Get value of Fram Interval field from the HFIR regsiter -+ */ -+extern uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if); -+/** -+ * Set value of Frame Interval field from the HFIR regsiter -+ */ -+extern void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val); -+ -+/** -+ * Set value of prtres field from the HPRT0 register -+ *FIXME Remove? -+ */ -+extern void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val); -+ -+/** -+ * Get value of rmtwkupsig bit in DCTL register -+ */ -+extern uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if); -+ -+/** -+ * Get value of prt_sleep_sts field from the GLPMCFG register -+ */ -+extern uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if); -+ -+/** -+ * Get value of rem_wkup_en field from the GLPMCFG register -+ */ -+extern uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if); -+ -+/** -+ * Get value of appl_resp field from the GLPMCFG register -+ */ -+extern uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if); -+/** -+ * Set value of appl_resp field from the GLPMCFG register -+ */ -+extern void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val); -+ -+/** -+ * Get value of hsic_connect field from the GLPMCFG register -+ */ -+extern uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if); -+/** -+ * Set value of hsic_connect field from the GLPMCFG register -+ */ -+extern void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val); -+ -+/** -+ * Get value of inv_sel_hsic field from the GLPMCFG register. -+ */ -+extern uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if); -+/** -+ * Set value of inv_sel_hsic field from the GLPMFG register. -+ */ -+extern void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val); -+ -+/* -+ * Some functions for accessing registers -+ */ -+ -+/** -+ * GOTGCTL register -+ */ -+extern uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if); -+extern void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val); -+ -+/** -+ * GUSBCFG register -+ */ -+extern uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if); -+extern void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val); -+ -+/** -+ * GRXFSIZ register -+ */ -+extern uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if); -+extern void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val); -+ -+/** -+ * GNPTXFSIZ register -+ */ -+extern uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if); -+extern void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val); -+ -+extern uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if); -+extern void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val); -+ -+/** -+ * GGPIO register -+ */ -+extern uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if); -+extern void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val); -+ -+/** -+ * GUID register -+ */ -+extern uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if); -+extern void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val); -+ -+/** -+ * HPRT0 register -+ */ -+extern uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if); -+extern void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val); -+ -+/** -+ * GHPTXFSIZE -+ */ -+extern uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if); -+ -+/** @} */ -+ -+#endif /* __DWC_CORE_IF_H__ */ -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_dbg.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_dbg.h ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_dbg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_dbg.h 2015-11-29 09:42:39.919098694 +0100 -@@ -0,0 +1,117 @@ -+/* ========================================================================== -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+ -+#ifndef __DWC_OTG_DBG_H__ -+#define __DWC_OTG_DBG_H__ -+ -+/** @file -+ * This file defines debug levels. -+ * Debugging support vanishes in non-debug builds. -+ */ -+ -+/** -+ * The Debug Level bit-mask variable. -+ */ -+extern uint32_t g_dbg_lvl; -+/** -+ * Set the Debug Level variable. -+ */ -+static inline uint32_t SET_DEBUG_LEVEL(const uint32_t new) -+{ -+ uint32_t old = g_dbg_lvl; -+ g_dbg_lvl = new; -+ return old; -+} -+ -+#define DBG_USER (0x1) -+/** When debug level has the DBG_CIL bit set, display CIL Debug messages. */ -+#define DBG_CIL (0x2) -+/** When debug level has the DBG_CILV bit set, display CIL Verbose debug -+ * messages */ -+#define DBG_CILV (0x20) -+/** When debug level has the DBG_PCD bit set, display PCD (Device) debug -+ * messages */ -+#define DBG_PCD (0x4) -+/** When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug -+ * messages */ -+#define DBG_PCDV (0x40) -+/** When debug level has the DBG_HCD bit set, display Host debug messages */ -+#define DBG_HCD (0x8) -+/** When debug level has the DBG_HCDV bit set, display Verbose Host debug -+ * messages */ -+#define DBG_HCDV (0x80) -+/** When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host -+ * mode. */ -+#define DBG_HCD_URB (0x800) -+/** When debug level has the DBG_HCDI bit set, display host interrupt -+ * messages. */ -+#define DBG_HCDI (0x1000) -+ -+/** When debug level has any bit set, display debug messages */ -+#define DBG_ANY (0xFF) -+ -+/** All debug messages off */ -+#define DBG_OFF 0 -+ -+/** Prefix string for DWC_DEBUG print macros. */ -+#define USB_DWC "DWC_otg: " -+ -+/** -+ * Print a debug message when the Global debug level variable contains -+ * the bit defined in lvl. -+ * -+ * @param[in] lvl - Debug level, use one of the DBG_ constants above. -+ * @param[in] x - like printf -+ * -+ * Example:

-+ * -+ * DWC_DEBUGPL( DBG_ANY, "%s(%p)\n", __func__, _reg_base_addr); -+ * -+ *
-+ * results in:
-+ * -+ * usb-DWC_otg: dwc_otg_cil_init(ca867000) -+ * -+ */ -+#ifdef DEBUG -+ -+# define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)__DWC_DEBUG(USB_DWC x ); }while(0) -+# define DWC_DEBUGP(x...) DWC_DEBUGPL(DBG_ANY, x ) -+ -+# define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl) -+ -+#else -+ -+# define DWC_DEBUGPL(lvl, x...) do{}while(0) -+# define DWC_DEBUGP(x...) -+ -+# define CHK_DEBUG_LEVEL(level) (0) -+ -+#endif /*DEBUG*/ -+#endif -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_driver.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_driver.c ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_driver.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_driver.c 2015-11-29 09:42:39.919098694 +0100 -@@ -0,0 +1,1757 @@ -+/* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $ -+ * $Revision: #92 $ -+ * $Date: 2012/08/10 $ -+ * $Change: 2047372 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+ -+/** @file -+ * The dwc_otg_driver module provides the initialization and cleanup entry -+ * points for the DWC_otg driver. This module will be dynamically installed -+ * after Linux is booted using the insmod command. When the module is -+ * installed, the dwc_otg_driver_init function is called. When the module is -+ * removed (using rmmod), the dwc_otg_driver_cleanup function is called. -+ * -+ * This module also defines a data structure for the dwc_otg_driver, which is -+ * used in conjunction with the standard ARM lm_device structure. These -+ * structures allow the OTG driver to comply with the standard Linux driver -+ * model in which devices and drivers are registered with a bus driver. This -+ * has the benefit that Linux can expose attributes of the driver and device -+ * in its special sysfs file system. Users can then read or write files in -+ * this file system to perform diagnostics on the driver components or the -+ * device. -+ */ -+ -+#include "dwc_otg_os_dep.h" -+#include "dwc_os.h" -+#include "dwc_otg_dbg.h" -+#include "dwc_otg_driver.h" -+#include "dwc_otg_attr.h" -+#include "dwc_otg_core_if.h" -+#include "dwc_otg_pcd_if.h" -+#include "dwc_otg_hcd_if.h" -+#include "dwc_otg_fiq_fsm.h" -+ -+#define DWC_DRIVER_VERSION "3.00a 10-AUG-2012" -+#define DWC_DRIVER_DESC "HS OTG USB Controller driver" -+ -+bool microframe_schedule=true; -+ -+static const char dwc_driver_name[] = "dwc_otg"; -+ -+ -+extern int pcd_init( -+#ifdef LM_INTERFACE -+ struct lm_device *_dev -+#elif defined(PCI_INTERFACE) -+ struct pci_dev *_dev -+#elif defined(PLATFORM_INTERFACE) -+ struct platform_device *dev -+#endif -+ ); -+extern int hcd_init( -+#ifdef LM_INTERFACE -+ struct lm_device *_dev -+#elif defined(PCI_INTERFACE) -+ struct pci_dev *_dev -+#elif defined(PLATFORM_INTERFACE) -+ struct platform_device *dev -+#endif -+ ); -+ -+extern int pcd_remove( -+#ifdef LM_INTERFACE -+ struct lm_device *_dev -+#elif defined(PCI_INTERFACE) -+ struct pci_dev *_dev -+#elif defined(PLATFORM_INTERFACE) -+ struct platform_device *_dev -+#endif -+ ); -+ -+extern void hcd_remove( -+#ifdef LM_INTERFACE -+ struct lm_device *_dev -+#elif defined(PCI_INTERFACE) -+ struct pci_dev *_dev -+#elif defined(PLATFORM_INTERFACE) -+ struct platform_device *_dev -+#endif -+ ); -+ -+extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host); -+ -+/*-------------------------------------------------------------------------*/ -+/* Encapsulate the module parameter settings */ -+ -+struct dwc_otg_driver_module_params { -+ int32_t opt; -+ int32_t otg_cap; -+ int32_t dma_enable; -+ int32_t dma_desc_enable; -+ int32_t dma_burst_size; -+ int32_t speed; -+ int32_t host_support_fs_ls_low_power; -+ int32_t host_ls_low_power_phy_clk; -+ int32_t enable_dynamic_fifo; -+ int32_t data_fifo_size; -+ int32_t dev_rx_fifo_size; -+ int32_t dev_nperio_tx_fifo_size; -+ uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS]; -+ int32_t host_rx_fifo_size; -+ int32_t host_nperio_tx_fifo_size; -+ int32_t host_perio_tx_fifo_size; -+ int32_t max_transfer_size; -+ int32_t max_packet_count; -+ int32_t host_channels; -+ int32_t dev_endpoints; -+ int32_t phy_type; -+ int32_t phy_utmi_width; -+ int32_t phy_ulpi_ddr; -+ int32_t phy_ulpi_ext_vbus; -+ int32_t i2c_enable; -+ int32_t ulpi_fs_ls; -+ int32_t ts_dline; -+ int32_t en_multiple_tx_fifo; -+ uint32_t dev_tx_fifo_size[MAX_TX_FIFOS]; -+ uint32_t thr_ctl; -+ uint32_t tx_thr_length; -+ uint32_t rx_thr_length; -+ int32_t pti_enable; -+ int32_t mpi_enable; -+ int32_t lpm_enable; -+ int32_t ic_usb_cap; -+ int32_t ahb_thr_ratio; -+ int32_t power_down; -+ int32_t reload_ctl; -+ int32_t dev_out_nak; -+ int32_t cont_on_bna; -+ int32_t ahb_single; -+ int32_t otg_ver; -+ int32_t adp_enable; -+}; -+ -+static struct dwc_otg_driver_module_params dwc_otg_module_params = { -+ .opt = -1, -+ .otg_cap = -1, -+ .dma_enable = -1, -+ .dma_desc_enable = -1, -+ .dma_burst_size = -1, -+ .speed = -1, -+ .host_support_fs_ls_low_power = -1, -+ .host_ls_low_power_phy_clk = -1, -+ .enable_dynamic_fifo = -1, -+ .data_fifo_size = -1, -+ .dev_rx_fifo_size = -1, -+ .dev_nperio_tx_fifo_size = -1, -+ .dev_perio_tx_fifo_size = { -+ /* dev_perio_tx_fifo_size_1 */ -+ -1, -+ -1, -+ -1, -+ -1, -+ -1, -+ -1, -+ -1, -+ -1, -+ -1, -+ -1, -+ -1, -+ -1, -+ -1, -+ -1, -+ -1 -+ /* 15 */ -+ }, -+ .host_rx_fifo_size = -1, -+ .host_nperio_tx_fifo_size = -1, -+ .host_perio_tx_fifo_size = -1, -+ .max_transfer_size = -1, -+ .max_packet_count = -1, -+ .host_channels = -1, -+ .dev_endpoints = -1, -+ .phy_type = -1, -+ .phy_utmi_width = -1, -+ .phy_ulpi_ddr = -1, -+ .phy_ulpi_ext_vbus = -1, -+ .i2c_enable = -1, -+ .ulpi_fs_ls = -1, -+ .ts_dline = -1, -+ .en_multiple_tx_fifo = -1, -+ .dev_tx_fifo_size = { -+ /* dev_tx_fifo_size */ -+ -1, -+ -1, -+ -1, -+ -1, -+ -1, -+ -1, -+ -1, -+ -1, -+ -1, -+ -1, -+ -1, -+ -1, -+ -1, -+ -1, -+ -1 -+ /* 15 */ -+ }, -+ .thr_ctl = -1, -+ .tx_thr_length = -1, -+ .rx_thr_length = -1, -+ .pti_enable = -1, -+ .mpi_enable = -1, -+ .lpm_enable = 0, -+ .ic_usb_cap = -1, -+ .ahb_thr_ratio = -1, -+ .power_down = -1, -+ .reload_ctl = -1, -+ .dev_out_nak = -1, -+ .cont_on_bna = -1, -+ .ahb_single = -1, -+ .otg_ver = -1, -+ .adp_enable = -1, -+}; -+ -+//Global variable to switch the fiq fix on or off -+bool fiq_enable = 1; -+// Global variable to enable the split transaction fix -+bool fiq_fsm_enable = true; -+//Bulk split-transaction NAK holdoff in microframes -+uint16_t nak_holdoff = 8; -+ -+unsigned short fiq_fsm_mask = 0x07; -+ -+/** -+ * This function shows the Driver Version. -+ */ -+static ssize_t version_show(struct device_driver *dev, char *buf) -+{ -+ return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n", -+ DWC_DRIVER_VERSION); -+} -+ -+static DRIVER_ATTR(version, S_IRUGO, version_show, NULL); -+ -+/** -+ * Global Debug Level Mask. -+ */ -+uint32_t g_dbg_lvl = 0; /* OFF */ -+ -+/** -+ * This function shows the driver Debug Level. -+ */ -+static ssize_t dbg_level_show(struct device_driver *drv, char *buf) -+{ -+ return sprintf(buf, "0x%0x\n", g_dbg_lvl); -+} -+ -+/** -+ * This function stores the driver Debug Level. -+ */ -+static ssize_t dbg_level_store(struct device_driver *drv, const char *buf, -+ size_t count) -+{ -+ g_dbg_lvl = simple_strtoul(buf, NULL, 16); -+ return count; -+} -+ -+static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show, -+ dbg_level_store); -+ -+/** -+ * This function is called during module intialization -+ * to pass module parameters to the DWC_OTG CORE. -+ */ -+static int set_parameters(dwc_otg_core_if_t * core_if) -+{ -+ int retval = 0; -+ int i; -+ -+ if (dwc_otg_module_params.otg_cap != -1) { -+ retval += -+ dwc_otg_set_param_otg_cap(core_if, -+ dwc_otg_module_params.otg_cap); -+ } -+ if (dwc_otg_module_params.dma_enable != -1) { -+ retval += -+ dwc_otg_set_param_dma_enable(core_if, -+ dwc_otg_module_params. -+ dma_enable); -+ } -+ if (dwc_otg_module_params.dma_desc_enable != -1) { -+ retval += -+ dwc_otg_set_param_dma_desc_enable(core_if, -+ dwc_otg_module_params. -+ dma_desc_enable); -+ } -+ if (dwc_otg_module_params.opt != -1) { -+ retval += -+ dwc_otg_set_param_opt(core_if, dwc_otg_module_params.opt); -+ } -+ if (dwc_otg_module_params.dma_burst_size != -1) { -+ retval += -+ dwc_otg_set_param_dma_burst_size(core_if, -+ dwc_otg_module_params. -+ dma_burst_size); -+ } -+ if (dwc_otg_module_params.host_support_fs_ls_low_power != -1) { -+ retval += -+ dwc_otg_set_param_host_support_fs_ls_low_power(core_if, -+ dwc_otg_module_params. -+ host_support_fs_ls_low_power); -+ } -+ if (dwc_otg_module_params.enable_dynamic_fifo != -1) { -+ retval += -+ dwc_otg_set_param_enable_dynamic_fifo(core_if, -+ dwc_otg_module_params. -+ enable_dynamic_fifo); -+ } -+ if (dwc_otg_module_params.data_fifo_size != -1) { -+ retval += -+ dwc_otg_set_param_data_fifo_size(core_if, -+ dwc_otg_module_params. -+ data_fifo_size); -+ } -+ if (dwc_otg_module_params.dev_rx_fifo_size != -1) { -+ retval += -+ dwc_otg_set_param_dev_rx_fifo_size(core_if, -+ dwc_otg_module_params. -+ dev_rx_fifo_size); -+ } -+ if (dwc_otg_module_params.dev_nperio_tx_fifo_size != -1) { -+ retval += -+ dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if, -+ dwc_otg_module_params. -+ dev_nperio_tx_fifo_size); -+ } -+ if (dwc_otg_module_params.host_rx_fifo_size != -1) { -+ retval += -+ dwc_otg_set_param_host_rx_fifo_size(core_if, -+ dwc_otg_module_params.host_rx_fifo_size); -+ } -+ if (dwc_otg_module_params.host_nperio_tx_fifo_size != -1) { -+ retval += -+ dwc_otg_set_param_host_nperio_tx_fifo_size(core_if, -+ dwc_otg_module_params. -+ host_nperio_tx_fifo_size); -+ } -+ if (dwc_otg_module_params.host_perio_tx_fifo_size != -1) { -+ retval += -+ dwc_otg_set_param_host_perio_tx_fifo_size(core_if, -+ dwc_otg_module_params. -+ host_perio_tx_fifo_size); -+ } -+ if (dwc_otg_module_params.max_transfer_size != -1) { -+ retval += -+ dwc_otg_set_param_max_transfer_size(core_if, -+ dwc_otg_module_params. -+ max_transfer_size); -+ } -+ if (dwc_otg_module_params.max_packet_count != -1) { -+ retval += -+ dwc_otg_set_param_max_packet_count(core_if, -+ dwc_otg_module_params. -+ max_packet_count); -+ } -+ if (dwc_otg_module_params.host_channels != -1) { -+ retval += -+ dwc_otg_set_param_host_channels(core_if, -+ dwc_otg_module_params. -+ host_channels); -+ } -+ if (dwc_otg_module_params.dev_endpoints != -1) { -+ retval += -+ dwc_otg_set_param_dev_endpoints(core_if, -+ dwc_otg_module_params. -+ dev_endpoints); -+ } -+ if (dwc_otg_module_params.phy_type != -1) { -+ retval += -+ dwc_otg_set_param_phy_type(core_if, -+ dwc_otg_module_params.phy_type); -+ } -+ if (dwc_otg_module_params.speed != -1) { -+ retval += -+ dwc_otg_set_param_speed(core_if, -+ dwc_otg_module_params.speed); -+ } -+ if (dwc_otg_module_params.host_ls_low_power_phy_clk != -1) { -+ retval += -+ dwc_otg_set_param_host_ls_low_power_phy_clk(core_if, -+ dwc_otg_module_params. -+ host_ls_low_power_phy_clk); -+ } -+ if (dwc_otg_module_params.phy_ulpi_ddr != -1) { -+ retval += -+ dwc_otg_set_param_phy_ulpi_ddr(core_if, -+ dwc_otg_module_params. -+ phy_ulpi_ddr); -+ } -+ if (dwc_otg_module_params.phy_ulpi_ext_vbus != -1) { -+ retval += -+ dwc_otg_set_param_phy_ulpi_ext_vbus(core_if, -+ dwc_otg_module_params. -+ phy_ulpi_ext_vbus); -+ } -+ if (dwc_otg_module_params.phy_utmi_width != -1) { -+ retval += -+ dwc_otg_set_param_phy_utmi_width(core_if, -+ dwc_otg_module_params. -+ phy_utmi_width); -+ } -+ if (dwc_otg_module_params.ulpi_fs_ls != -1) { -+ retval += -+ dwc_otg_set_param_ulpi_fs_ls(core_if, -+ dwc_otg_module_params.ulpi_fs_ls); -+ } -+ if (dwc_otg_module_params.ts_dline != -1) { -+ retval += -+ dwc_otg_set_param_ts_dline(core_if, -+ dwc_otg_module_params.ts_dline); -+ } -+ if (dwc_otg_module_params.i2c_enable != -1) { -+ retval += -+ dwc_otg_set_param_i2c_enable(core_if, -+ dwc_otg_module_params. -+ i2c_enable); -+ } -+ if (dwc_otg_module_params.en_multiple_tx_fifo != -1) { -+ retval += -+ dwc_otg_set_param_en_multiple_tx_fifo(core_if, -+ dwc_otg_module_params. -+ en_multiple_tx_fifo); -+ } -+ for (i = 0; i < 15; i++) { -+ if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) { -+ retval += -+ dwc_otg_set_param_dev_perio_tx_fifo_size(core_if, -+ dwc_otg_module_params. -+ dev_perio_tx_fifo_size -+ [i], i); -+ } -+ } -+ -+ for (i = 0; i < 15; i++) { -+ if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) { -+ retval += dwc_otg_set_param_dev_tx_fifo_size(core_if, -+ dwc_otg_module_params. -+ dev_tx_fifo_size -+ [i], i); -+ } -+ } -+ if (dwc_otg_module_params.thr_ctl != -1) { -+ retval += -+ dwc_otg_set_param_thr_ctl(core_if, -+ dwc_otg_module_params.thr_ctl); -+ } -+ if (dwc_otg_module_params.mpi_enable != -1) { -+ retval += -+ dwc_otg_set_param_mpi_enable(core_if, -+ dwc_otg_module_params. -+ mpi_enable); -+ } -+ if (dwc_otg_module_params.pti_enable != -1) { -+ retval += -+ dwc_otg_set_param_pti_enable(core_if, -+ dwc_otg_module_params. -+ pti_enable); -+ } -+ if (dwc_otg_module_params.lpm_enable != -1) { -+ retval += -+ dwc_otg_set_param_lpm_enable(core_if, -+ dwc_otg_module_params. -+ lpm_enable); -+ } -+ if (dwc_otg_module_params.ic_usb_cap != -1) { -+ retval += -+ dwc_otg_set_param_ic_usb_cap(core_if, -+ dwc_otg_module_params. -+ ic_usb_cap); -+ } -+ if (dwc_otg_module_params.tx_thr_length != -1) { -+ retval += -+ dwc_otg_set_param_tx_thr_length(core_if, -+ dwc_otg_module_params.tx_thr_length); -+ } -+ if (dwc_otg_module_params.rx_thr_length != -1) { -+ retval += -+ dwc_otg_set_param_rx_thr_length(core_if, -+ dwc_otg_module_params. -+ rx_thr_length); -+ } -+ if (dwc_otg_module_params.ahb_thr_ratio != -1) { -+ retval += -+ dwc_otg_set_param_ahb_thr_ratio(core_if, -+ dwc_otg_module_params.ahb_thr_ratio); -+ } -+ if (dwc_otg_module_params.power_down != -1) { -+ retval += -+ dwc_otg_set_param_power_down(core_if, -+ dwc_otg_module_params.power_down); -+ } -+ if (dwc_otg_module_params.reload_ctl != -1) { -+ retval += -+ dwc_otg_set_param_reload_ctl(core_if, -+ dwc_otg_module_params.reload_ctl); -+ } -+ -+ if (dwc_otg_module_params.dev_out_nak != -1) { -+ retval += -+ dwc_otg_set_param_dev_out_nak(core_if, -+ dwc_otg_module_params.dev_out_nak); -+ } -+ -+ if (dwc_otg_module_params.cont_on_bna != -1) { -+ retval += -+ dwc_otg_set_param_cont_on_bna(core_if, -+ dwc_otg_module_params.cont_on_bna); -+ } -+ -+ if (dwc_otg_module_params.ahb_single != -1) { -+ retval += -+ dwc_otg_set_param_ahb_single(core_if, -+ dwc_otg_module_params.ahb_single); -+ } -+ -+ if (dwc_otg_module_params.otg_ver != -1) { -+ retval += -+ dwc_otg_set_param_otg_ver(core_if, -+ dwc_otg_module_params.otg_ver); -+ } -+ if (dwc_otg_module_params.adp_enable != -1) { -+ retval += -+ dwc_otg_set_param_adp_enable(core_if, -+ dwc_otg_module_params. -+ adp_enable); -+ } -+ return retval; -+} -+ -+/** -+ * This function is the top level interrupt handler for the Common -+ * (Device and host modes) interrupts. -+ */ -+static irqreturn_t dwc_otg_common_irq(int irq, void *dev) -+{ -+ int32_t retval = IRQ_NONE; -+ -+ retval = dwc_otg_handle_common_intr(dev); -+ if (retval != 0) { -+ S3C2410X_CLEAR_EINTPEND(); -+ } -+ return IRQ_RETVAL(retval); -+} -+ -+/** -+ * This function is called when a lm_device is unregistered with the -+ * dwc_otg_driver. This happens, for example, when the rmmod command is -+ * executed. The device may or may not be electrically present. If it is -+ * present, the driver stops device processing. Any resources used on behalf -+ * of this device are freed. -+ * -+ * @param _dev -+ */ -+#ifdef LM_INTERFACE -+#define REM_RETVAL(n) -+static void dwc_otg_driver_remove( struct lm_device *_dev ) -+{ dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev); -+#elif defined(PCI_INTERFACE) -+#define REM_RETVAL(n) -+static void dwc_otg_driver_remove( struct pci_dev *_dev ) -+{ dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev); -+#elif defined(PLATFORM_INTERFACE) -+#define REM_RETVAL(n) n -+static int dwc_otg_driver_remove( struct platform_device *_dev ) -+{ dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev); -+#endif -+ -+ DWC_DEBUGPL(DBG_ANY, "%s(%p) otg_dev %p\n", __func__, _dev, otg_dev); -+ -+ if (!otg_dev) { -+ /* Memory allocation for the dwc_otg_device failed. */ -+ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__); -+ return REM_RETVAL(-ENOMEM); -+ } -+#ifndef DWC_DEVICE_ONLY -+ if (otg_dev->hcd) { -+ hcd_remove(_dev); -+ } else { -+ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__); -+ return REM_RETVAL(-EINVAL); -+ } -+#endif -+ -+#ifndef DWC_HOST_ONLY -+ if (otg_dev->pcd) { -+ pcd_remove(_dev); -+ } else { -+ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__); -+ return REM_RETVAL(-EINVAL); -+ } -+#endif -+ /* -+ * Free the IRQ -+ */ -+ if (otg_dev->common_irq_installed) { -+#ifdef PLATFORM_INTERFACE -+ free_irq(platform_get_irq(_dev, 0), otg_dev); -+#else -+ free_irq(_dev->irq, otg_dev); -+#endif -+ } else { -+ DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n", __func__); -+ return REM_RETVAL(-ENXIO); -+ } -+ -+ if (otg_dev->core_if) { -+ dwc_otg_cil_remove(otg_dev->core_if); -+ } else { -+ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__); -+ return REM_RETVAL(-ENXIO); -+ } -+ -+ /* -+ * Remove the device attributes -+ */ -+ dwc_otg_attr_remove(_dev); -+ -+ /* -+ * Return the memory. -+ */ -+ if (otg_dev->os_dep.base) { -+ iounmap(otg_dev->os_dep.base); -+ } -+ DWC_FREE(otg_dev); -+ -+ /* -+ * Clear the drvdata pointer. -+ */ -+#ifdef LM_INTERFACE -+ lm_set_drvdata(_dev, 0); -+#elif defined(PCI_INTERFACE) -+ release_mem_region(otg_dev->os_dep.rsrc_start, -+ otg_dev->os_dep.rsrc_len); -+ pci_set_drvdata(_dev, 0); -+#elif defined(PLATFORM_INTERFACE) -+ platform_set_drvdata(_dev, 0); -+#endif -+ return REM_RETVAL(0); -+} -+ -+/** -+ * This function is called when an lm_device is bound to a -+ * dwc_otg_driver. It creates the driver components required to -+ * control the device (CIL, HCD, and PCD) and it initializes the -+ * device. The driver components are stored in a dwc_otg_device -+ * structure. A reference to the dwc_otg_device is saved in the -+ * lm_device. This allows the driver to access the dwc_otg_device -+ * structure on subsequent calls to driver methods for this device. -+ * -+ * @param _dev Bus device -+ */ -+static int dwc_otg_driver_probe( -+#ifdef LM_INTERFACE -+ struct lm_device *_dev -+#elif defined(PCI_INTERFACE) -+ struct pci_dev *_dev, -+ const struct pci_device_id *id -+#elif defined(PLATFORM_INTERFACE) -+ struct platform_device *_dev -+#endif -+ ) -+{ -+ int retval = 0; -+ dwc_otg_device_t *dwc_otg_device; -+ int devirq; -+ -+ dev_dbg(&_dev->dev, "dwc_otg_driver_probe(%p)\n", _dev); -+#ifdef LM_INTERFACE -+ dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)_dev->resource.start); -+#elif defined(PCI_INTERFACE) -+ if (!id) { -+ DWC_ERROR("Invalid pci_device_id %p", id); -+ return -EINVAL; -+ } -+ -+ if (!_dev || (pci_enable_device(_dev) < 0)) { -+ DWC_ERROR("Invalid pci_device %p", _dev); -+ return -ENODEV; -+ } -+ dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)pci_resource_start(_dev,0)); -+ /* other stuff needed as well? */ -+ -+#elif defined(PLATFORM_INTERFACE) -+ dev_dbg(&_dev->dev, "start=0x%08x (len 0x%x)\n", -+ (unsigned)_dev->resource->start, -+ (unsigned)(_dev->resource->end - _dev->resource->start)); -+#endif -+ -+ dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t)); -+ -+ if (!dwc_otg_device) { -+ dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n"); -+ return -ENOMEM; -+ } -+ -+ memset(dwc_otg_device, 0, sizeof(*dwc_otg_device)); -+ dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF; -+ dwc_otg_device->os_dep.platformdev = _dev; -+ -+ /* -+ * Map the DWC_otg Core memory into virtual address space. -+ */ -+#ifdef LM_INTERFACE -+ dwc_otg_device->os_dep.base = ioremap(_dev->resource.start, SZ_256K); -+ -+ if (!dwc_otg_device->os_dep.base) { -+ dev_err(&_dev->dev, "ioremap() failed\n"); -+ DWC_FREE(dwc_otg_device); -+ return -ENOMEM; -+ } -+ dev_dbg(&_dev->dev, "base=0x%08x\n", -+ (unsigned)dwc_otg_device->os_dep.base); -+#elif defined(PCI_INTERFACE) -+ _dev->current_state = PCI_D0; -+ _dev->dev.power.power_state = PMSG_ON; -+ -+ if (!_dev->irq) { -+ DWC_ERROR("Found HC with no IRQ. Check BIOS/PCI %s setup!", -+ pci_name(_dev)); -+ iounmap(dwc_otg_device->os_dep.base); -+ DWC_FREE(dwc_otg_device); -+ return -ENODEV; -+ } -+ -+ dwc_otg_device->os_dep.rsrc_start = pci_resource_start(_dev, 0); -+ dwc_otg_device->os_dep.rsrc_len = pci_resource_len(_dev, 0); -+ DWC_DEBUGPL(DBG_ANY, "PCI resource: start=%08x, len=%08x\n", -+ (unsigned)dwc_otg_device->os_dep.rsrc_start, -+ (unsigned)dwc_otg_device->os_dep.rsrc_len); -+ if (!request_mem_region -+ (dwc_otg_device->os_dep.rsrc_start, dwc_otg_device->os_dep.rsrc_len, -+ "dwc_otg")) { -+ dev_dbg(&_dev->dev, "error requesting memory\n"); -+ iounmap(dwc_otg_device->os_dep.base); -+ DWC_FREE(dwc_otg_device); -+ return -EFAULT; -+ } -+ -+ dwc_otg_device->os_dep.base = -+ ioremap_nocache(dwc_otg_device->os_dep.rsrc_start, -+ dwc_otg_device->os_dep.rsrc_len); -+ if (dwc_otg_device->os_dep.base == NULL) { -+ dev_dbg(&_dev->dev, "error mapping memory\n"); -+ release_mem_region(dwc_otg_device->os_dep.rsrc_start, -+ dwc_otg_device->os_dep.rsrc_len); -+ iounmap(dwc_otg_device->os_dep.base); -+ DWC_FREE(dwc_otg_device); -+ return -EFAULT; -+ } -+ dev_dbg(&_dev->dev, "base=0x%p (before adjust) \n", -+ dwc_otg_device->os_dep.base); -+ dwc_otg_device->os_dep.base = (char *)dwc_otg_device->os_dep.base; -+ dev_dbg(&_dev->dev, "base=0x%p (after adjust) \n", -+ dwc_otg_device->os_dep.base); -+ dev_dbg(&_dev->dev, "%s: mapped PA 0x%x to VA 0x%p\n", __func__, -+ (unsigned)dwc_otg_device->os_dep.rsrc_start, -+ dwc_otg_device->os_dep.base); -+ -+ pci_set_master(_dev); -+ pci_set_drvdata(_dev, dwc_otg_device); -+#elif defined(PLATFORM_INTERFACE) -+ DWC_DEBUGPL(DBG_ANY,"Platform resource: start=%08x, len=%08x\n", -+ _dev->resource->start, -+ _dev->resource->end - _dev->resource->start + 1); -+#if 1 -+ if (!request_mem_region(_dev->resource[0].start, -+ _dev->resource[0].end - _dev->resource[0].start + 1, -+ "dwc_otg")) { -+ dev_dbg(&_dev->dev, "error reserving mapped memory\n"); -+ retval = -EFAULT; -+ goto fail; -+ } -+ -+ dwc_otg_device->os_dep.base = ioremap_nocache(_dev->resource[0].start, -+ _dev->resource[0].end - -+ _dev->resource[0].start+1); -+ if (fiq_enable) -+ { -+ if (!request_mem_region(_dev->resource[1].start, -+ _dev->resource[1].end - _dev->resource[1].start + 1, -+ "dwc_otg")) { -+ dev_dbg(&_dev->dev, "error reserving mapped memory\n"); -+ retval = -EFAULT; -+ goto fail; -+ } -+ -+ dwc_otg_device->os_dep.mphi_base = ioremap_nocache(_dev->resource[1].start, -+ _dev->resource[1].end - -+ _dev->resource[1].start + 1); -+ } -+ -+#else -+ { -+ struct map_desc desc = { -+ .virtual = IO_ADDRESS((unsigned)_dev->resource->start), -+ .pfn = __phys_to_pfn((unsigned)_dev->resource->start), -+ .length = SZ_128K, -+ .type = MT_DEVICE -+ }; -+ iotable_init(&desc, 1); -+ dwc_otg_device->os_dep.base = (void *)desc.virtual; -+ } -+#endif -+ if (!dwc_otg_device->os_dep.base) { -+ dev_err(&_dev->dev, "ioremap() failed\n"); -+ retval = -ENOMEM; -+ goto fail; -+ } -+ dev_dbg(&_dev->dev, "base=0x%08x\n", -+ (unsigned)dwc_otg_device->os_dep.base); -+#endif -+ -+ /* -+ * Initialize driver data to point to the global DWC_otg -+ * Device structure. -+ */ -+#ifdef LM_INTERFACE -+ lm_set_drvdata(_dev, dwc_otg_device); -+#elif defined(PLATFORM_INTERFACE) -+ platform_set_drvdata(_dev, dwc_otg_device); -+#endif -+ dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device); -+ -+ dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base); -+ DWC_DEBUGPL(DBG_HCDV, "probe of device %p given core_if %p\n", -+ dwc_otg_device, dwc_otg_device->core_if);//GRAYG -+ -+ if (!dwc_otg_device->core_if) { -+ dev_err(&_dev->dev, "CIL initialization failed!\n"); -+ retval = -ENOMEM; -+ goto fail; -+ } -+ -+ dev_dbg(&_dev->dev, "Calling get_gsnpsid\n"); -+ /* -+ * Attempt to ensure this device is really a DWC_otg Controller. -+ * Read and verify the SNPSID register contents. The value should be -+ * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3", -+ * as in "OTG version 2.XX" or "OTG version 3.XX". -+ */ -+ -+ if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F542000) && -+ ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F543000)) { -+ dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n", -+ dwc_otg_get_gsnpsid(dwc_otg_device->core_if)); -+ retval = -EINVAL; -+ goto fail; -+ } -+ -+ /* -+ * Validate parameter values. -+ */ -+ dev_dbg(&_dev->dev, "Calling set_parameters\n"); -+ if (set_parameters(dwc_otg_device->core_if)) { -+ retval = -EINVAL; -+ goto fail; -+ } -+ -+ /* -+ * Create Device Attributes in sysfs -+ */ -+ dev_dbg(&_dev->dev, "Calling attr_create\n"); -+ dwc_otg_attr_create(_dev); -+ -+ /* -+ * Disable the global interrupt until all the interrupt -+ * handlers are installed. -+ */ -+ dev_dbg(&_dev->dev, "Calling disable_global_interrupts\n"); -+ dwc_otg_disable_global_interrupts(dwc_otg_device->core_if); -+ -+ /* -+ * Install the interrupt handler for the common interrupts before -+ * enabling common interrupts in core_init below. -+ */ -+ -+#if defined(PLATFORM_INTERFACE) -+ devirq = platform_get_irq(_dev, fiq_enable ? 0 : 1); -+#else -+ devirq = _dev->irq; -+#endif -+ DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", -+ devirq); -+ dev_dbg(&_dev->dev, "Calling request_irq(%d)\n", devirq); -+ retval = request_irq(devirq, dwc_otg_common_irq, -+ IRQF_SHARED, -+ "dwc_otg", dwc_otg_device); -+ if (retval) { -+ DWC_ERROR("request of irq%d failed\n", devirq); -+ retval = -EBUSY; -+ goto fail; -+ } else { -+ dwc_otg_device->common_irq_installed = 1; -+ } -+ -+#ifndef IRQF_TRIGGER_LOW -+#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE) -+ dev_dbg(&_dev->dev, "Calling set_irq_type\n"); -+ set_irq_type(devirq, -+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) -+ IRQT_LOW -+#else -+ IRQ_TYPE_LEVEL_LOW -+#endif -+ ); -+#endif -+#endif /*IRQF_TRIGGER_LOW*/ -+ -+ /* -+ * Initialize the DWC_otg core. -+ */ -+ dev_dbg(&_dev->dev, "Calling dwc_otg_core_init\n"); -+ dwc_otg_core_init(dwc_otg_device->core_if); -+ -+#ifndef DWC_HOST_ONLY -+ /* -+ * Initialize the PCD -+ */ -+ dev_dbg(&_dev->dev, "Calling pcd_init\n"); -+ retval = pcd_init(_dev); -+ if (retval != 0) { -+ DWC_ERROR("pcd_init failed\n"); -+ dwc_otg_device->pcd = NULL; -+ goto fail; -+ } -+#endif -+#ifndef DWC_DEVICE_ONLY -+ /* -+ * Initialize the HCD -+ */ -+ dev_dbg(&_dev->dev, "Calling hcd_init\n"); -+ retval = hcd_init(_dev); -+ if (retval != 0) { -+ DWC_ERROR("hcd_init failed\n"); -+ dwc_otg_device->hcd = NULL; -+ goto fail; -+ } -+#endif -+ /* Recover from drvdata having been overwritten by hcd_init() */ -+#ifdef LM_INTERFACE -+ lm_set_drvdata(_dev, dwc_otg_device); -+#elif defined(PLATFORM_INTERFACE) -+ platform_set_drvdata(_dev, dwc_otg_device); -+#elif defined(PCI_INTERFACE) -+ pci_set_drvdata(_dev, dwc_otg_device); -+ dwc_otg_device->os_dep.pcidev = _dev; -+#endif -+ -+ /* -+ * Enable the global interrupt after all the interrupt -+ * handlers are installed if there is no ADP support else -+ * perform initial actions required for Internal ADP logic. -+ */ -+ if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) { -+ dev_dbg(&_dev->dev, "Calling enable_global_interrupts\n"); -+ dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); -+ dev_dbg(&_dev->dev, "Done\n"); -+ } else -+ dwc_otg_adp_start(dwc_otg_device->core_if, -+ dwc_otg_is_host_mode(dwc_otg_device->core_if)); -+ -+ return 0; -+ -+fail: -+ dwc_otg_driver_remove(_dev); -+ return retval; -+} -+ -+/** -+ * This structure defines the methods to be called by a bus driver -+ * during the lifecycle of a device on that bus. Both drivers and -+ * devices are registered with a bus driver. The bus driver matches -+ * devices to drivers based on information in the device and driver -+ * structures. -+ * -+ * The probe function is called when the bus driver matches a device -+ * to this driver. The remove function is called when a device is -+ * unregistered with the bus driver. -+ */ -+#ifdef LM_INTERFACE -+static struct lm_driver dwc_otg_driver = { -+ .drv = {.name = (char *)dwc_driver_name,}, -+ .probe = dwc_otg_driver_probe, -+ .remove = dwc_otg_driver_remove, -+ // 'suspend' and 'resume' absent -+}; -+#elif defined(PCI_INTERFACE) -+static const struct pci_device_id pci_ids[] = { { -+ PCI_DEVICE(0x16c3, 0xabcd), -+ .driver_data = -+ (unsigned long)0xdeadbeef, -+ }, { /* end: all zeroes */ } -+}; -+ -+MODULE_DEVICE_TABLE(pci, pci_ids); -+ -+/* pci driver glue; this is a "new style" PCI driver module */ -+static struct pci_driver dwc_otg_driver = { -+ .name = "dwc_otg", -+ .id_table = pci_ids, -+ -+ .probe = dwc_otg_driver_probe, -+ .remove = dwc_otg_driver_remove, -+ -+ .driver = { -+ .name = (char *)dwc_driver_name, -+ }, -+}; -+#elif defined(PLATFORM_INTERFACE) -+static struct platform_device_id platform_ids[] = { -+ { -+ .name = "bcm2708_usb", -+ .driver_data = (kernel_ulong_t) 0xdeadbeef, -+ }, -+ { /* end: all zeroes */ } -+}; -+MODULE_DEVICE_TABLE(platform, platform_ids); -+ -+static const struct of_device_id dwc_otg_of_match_table[] = { -+ { .compatible = "brcm,bcm2708-usb", }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, dwc_otg_of_match_table); -+ -+static struct platform_driver dwc_otg_driver = { -+ .driver = { -+ .name = (char *)dwc_driver_name, -+ .of_match_table = dwc_otg_of_match_table, -+ }, -+ .id_table = platform_ids, -+ -+ .probe = dwc_otg_driver_probe, -+ .remove = dwc_otg_driver_remove, -+ // no 'shutdown', 'suspend', 'resume', 'suspend_late' or 'resume_early' -+}; -+#endif -+ -+/** -+ * This function is called when the dwc_otg_driver is installed with the -+ * insmod command. It registers the dwc_otg_driver structure with the -+ * appropriate bus driver. This will cause the dwc_otg_driver_probe function -+ * to be called. In addition, the bus driver will automatically expose -+ * attributes defined for the device and driver in the special sysfs file -+ * system. -+ * -+ * @return -+ */ -+static int __init dwc_otg_driver_init(void) -+{ -+ int retval = 0; -+ int error; -+ struct device_driver *drv; -+ -+ if(fiq_fsm_enable && !fiq_enable) { -+ printk(KERN_WARNING "dwc_otg: fiq_fsm_enable was set without fiq_enable! Correcting.\n"); -+ fiq_enable = 1; -+ } -+ -+ printk(KERN_INFO "%s: version %s (%s bus)\n", dwc_driver_name, -+ DWC_DRIVER_VERSION, -+#ifdef LM_INTERFACE -+ "logicmodule"); -+ retval = lm_driver_register(&dwc_otg_driver); -+ drv = &dwc_otg_driver.drv; -+#elif defined(PCI_INTERFACE) -+ "pci"); -+ retval = pci_register_driver(&dwc_otg_driver); -+ drv = &dwc_otg_driver.driver; -+#elif defined(PLATFORM_INTERFACE) -+ "platform"); -+ retval = platform_driver_register(&dwc_otg_driver); -+ drv = &dwc_otg_driver.driver; -+#endif -+ if (retval < 0) { -+ printk(KERN_ERR "%s retval=%d\n", __func__, retval); -+ return retval; -+ } -+ printk(KERN_DEBUG "dwc_otg: FIQ %s\n", fiq_enable ? "enabled":"disabled"); -+ printk(KERN_DEBUG "dwc_otg: NAK holdoff %s\n", nak_holdoff ? "enabled":"disabled"); -+ printk(KERN_DEBUG "dwc_otg: FIQ split-transaction FSM %s\n", fiq_fsm_enable ? "enabled":"disabled"); -+ -+ error = driver_create_file(drv, &driver_attr_version); -+#ifdef DEBUG -+ error = driver_create_file(drv, &driver_attr_debuglevel); -+#endif -+ return retval; -+} -+ -+module_init(dwc_otg_driver_init); -+ -+/** -+ * This function is called when the driver is removed from the kernel -+ * with the rmmod command. The driver unregisters itself with its bus -+ * driver. -+ * -+ */ -+static void __exit dwc_otg_driver_cleanup(void) -+{ -+ printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n"); -+ -+#ifdef LM_INTERFACE -+ driver_remove_file(&dwc_otg_driver.drv, &driver_attr_debuglevel); -+ driver_remove_file(&dwc_otg_driver.drv, &driver_attr_version); -+ lm_driver_unregister(&dwc_otg_driver); -+#elif defined(PCI_INTERFACE) -+ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel); -+ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version); -+ pci_unregister_driver(&dwc_otg_driver); -+#elif defined(PLATFORM_INTERFACE) -+ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel); -+ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version); -+ platform_driver_unregister(&dwc_otg_driver); -+#endif -+ -+ printk(KERN_INFO "%s module removed\n", dwc_driver_name); -+} -+ -+module_exit(dwc_otg_driver_cleanup); -+ -+MODULE_DESCRIPTION(DWC_DRIVER_DESC); -+MODULE_AUTHOR("Synopsys Inc."); -+MODULE_LICENSE("GPL"); -+ -+module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444); -+MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None"); -+module_param_named(opt, dwc_otg_module_params.opt, int, 0444); -+MODULE_PARM_DESC(opt, "OPT Mode"); -+module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444); -+MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled"); -+ -+module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int, -+ 0444); -+MODULE_PARM_DESC(dma_desc_enable, -+ "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled"); -+ -+module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int, -+ 0444); -+MODULE_PARM_DESC(dma_burst_size, -+ "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256"); -+module_param_named(speed, dwc_otg_module_params.speed, int, 0444); -+MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed"); -+module_param_named(host_support_fs_ls_low_power, -+ dwc_otg_module_params.host_support_fs_ls_low_power, int, -+ 0444); -+MODULE_PARM_DESC(host_support_fs_ls_low_power, -+ "Support Low Power w/FS or LS 0=Support 1=Don't Support"); -+module_param_named(host_ls_low_power_phy_clk, -+ dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444); -+MODULE_PARM_DESC(host_ls_low_power_phy_clk, -+ "Low Speed Low Power Clock 0=48Mhz 1=6Mhz"); -+module_param_named(enable_dynamic_fifo, -+ dwc_otg_module_params.enable_dynamic_fifo, int, 0444); -+MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing"); -+module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int, -+ 0444); -+MODULE_PARM_DESC(data_fifo_size, -+ "Total number of words in the data FIFO memory 32-32768"); -+module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size, -+ int, 0444); -+MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768"); -+module_param_named(dev_nperio_tx_fifo_size, -+ dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444); -+MODULE_PARM_DESC(dev_nperio_tx_fifo_size, -+ "Number of words in the non-periodic Tx FIFO 16-32768"); -+module_param_named(dev_perio_tx_fifo_size_1, -+ dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444); -+MODULE_PARM_DESC(dev_perio_tx_fifo_size_1, -+ "Number of words in the periodic Tx FIFO 4-768"); -+module_param_named(dev_perio_tx_fifo_size_2, -+ dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444); -+MODULE_PARM_DESC(dev_perio_tx_fifo_size_2, -+ "Number of words in the periodic Tx FIFO 4-768"); -+module_param_named(dev_perio_tx_fifo_size_3, -+ dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444); -+MODULE_PARM_DESC(dev_perio_tx_fifo_size_3, -+ "Number of words in the periodic Tx FIFO 4-768"); -+module_param_named(dev_perio_tx_fifo_size_4, -+ dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444); -+MODULE_PARM_DESC(dev_perio_tx_fifo_size_4, -+ "Number of words in the periodic Tx FIFO 4-768"); -+module_param_named(dev_perio_tx_fifo_size_5, -+ dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444); -+MODULE_PARM_DESC(dev_perio_tx_fifo_size_5, -+ "Number of words in the periodic Tx FIFO 4-768"); -+module_param_named(dev_perio_tx_fifo_size_6, -+ dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444); -+MODULE_PARM_DESC(dev_perio_tx_fifo_size_6, -+ "Number of words in the periodic Tx FIFO 4-768"); -+module_param_named(dev_perio_tx_fifo_size_7, -+ dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444); -+MODULE_PARM_DESC(dev_perio_tx_fifo_size_7, -+ "Number of words in the periodic Tx FIFO 4-768"); -+module_param_named(dev_perio_tx_fifo_size_8, -+ dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444); -+MODULE_PARM_DESC(dev_perio_tx_fifo_size_8, -+ "Number of words in the periodic Tx FIFO 4-768"); -+module_param_named(dev_perio_tx_fifo_size_9, -+ dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444); -+MODULE_PARM_DESC(dev_perio_tx_fifo_size_9, -+ "Number of words in the periodic Tx FIFO 4-768"); -+module_param_named(dev_perio_tx_fifo_size_10, -+ dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444); -+MODULE_PARM_DESC(dev_perio_tx_fifo_size_10, -+ "Number of words in the periodic Tx FIFO 4-768"); -+module_param_named(dev_perio_tx_fifo_size_11, -+ dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444); -+MODULE_PARM_DESC(dev_perio_tx_fifo_size_11, -+ "Number of words in the periodic Tx FIFO 4-768"); -+module_param_named(dev_perio_tx_fifo_size_12, -+ dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444); -+MODULE_PARM_DESC(dev_perio_tx_fifo_size_12, -+ "Number of words in the periodic Tx FIFO 4-768"); -+module_param_named(dev_perio_tx_fifo_size_13, -+ dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444); -+MODULE_PARM_DESC(dev_perio_tx_fifo_size_13, -+ "Number of words in the periodic Tx FIFO 4-768"); -+module_param_named(dev_perio_tx_fifo_size_14, -+ dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444); -+MODULE_PARM_DESC(dev_perio_tx_fifo_size_14, -+ "Number of words in the periodic Tx FIFO 4-768"); -+module_param_named(dev_perio_tx_fifo_size_15, -+ dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444); -+MODULE_PARM_DESC(dev_perio_tx_fifo_size_15, -+ "Number of words in the periodic Tx FIFO 4-768"); -+module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size, -+ int, 0444); -+MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768"); -+module_param_named(host_nperio_tx_fifo_size, -+ dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444); -+MODULE_PARM_DESC(host_nperio_tx_fifo_size, -+ "Number of words in the non-periodic Tx FIFO 16-32768"); -+module_param_named(host_perio_tx_fifo_size, -+ dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444); -+MODULE_PARM_DESC(host_perio_tx_fifo_size, -+ "Number of words in the host periodic Tx FIFO 16-32768"); -+module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size, -+ int, 0444); -+/** @todo Set the max to 512K, modify checks */ -+MODULE_PARM_DESC(max_transfer_size, -+ "The maximum transfer size supported in bytes 2047-65535"); -+module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count, -+ int, 0444); -+MODULE_PARM_DESC(max_packet_count, -+ "The maximum number of packets in a transfer 15-511"); -+module_param_named(host_channels, dwc_otg_module_params.host_channels, int, -+ 0444); -+MODULE_PARM_DESC(host_channels, -+ "The number of host channel registers to use 1-16"); -+module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int, -+ 0444); -+MODULE_PARM_DESC(dev_endpoints, -+ "The number of endpoints in addition to EP0 available for device mode 1-15"); -+module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444); -+MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI"); -+module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int, -+ 0444); -+MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits"); -+module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444); -+MODULE_PARM_DESC(phy_ulpi_ddr, -+ "ULPI at double or single data rate 0=Single 1=Double"); -+module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus, -+ int, 0444); -+MODULE_PARM_DESC(phy_ulpi_ext_vbus, -+ "ULPI PHY using internal or external vbus 0=Internal"); -+module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444); -+MODULE_PARM_DESC(i2c_enable, "FS PHY Interface"); -+module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444); -+MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only"); -+module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444); -+MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs"); -+module_param_named(debug, g_dbg_lvl, int, 0444); -+MODULE_PARM_DESC(debug, ""); -+ -+module_param_named(en_multiple_tx_fifo, -+ dwc_otg_module_params.en_multiple_tx_fifo, int, 0444); -+MODULE_PARM_DESC(en_multiple_tx_fifo, -+ "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled"); -+module_param_named(dev_tx_fifo_size_1, -+ dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444); -+MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768"); -+module_param_named(dev_tx_fifo_size_2, -+ dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444); -+MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768"); -+module_param_named(dev_tx_fifo_size_3, -+ dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444); -+MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768"); -+module_param_named(dev_tx_fifo_size_4, -+ dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444); -+MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768"); -+module_param_named(dev_tx_fifo_size_5, -+ dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444); -+MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768"); -+module_param_named(dev_tx_fifo_size_6, -+ dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444); -+MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768"); -+module_param_named(dev_tx_fifo_size_7, -+ dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444); -+MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768"); -+module_param_named(dev_tx_fifo_size_8, -+ dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444); -+MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768"); -+module_param_named(dev_tx_fifo_size_9, -+ dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444); -+MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768"); -+module_param_named(dev_tx_fifo_size_10, -+ dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444); -+MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768"); -+module_param_named(dev_tx_fifo_size_11, -+ dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444); -+MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768"); -+module_param_named(dev_tx_fifo_size_12, -+ dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444); -+MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768"); -+module_param_named(dev_tx_fifo_size_13, -+ dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444); -+MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768"); -+module_param_named(dev_tx_fifo_size_14, -+ dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444); -+MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768"); -+module_param_named(dev_tx_fifo_size_15, -+ dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444); -+MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768"); -+ -+module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444); -+MODULE_PARM_DESC(thr_ctl, -+ "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled"); -+module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int, -+ 0444); -+MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs"); -+module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int, -+ 0444); -+MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs"); -+ -+module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444); -+module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444); -+module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444); -+MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled"); -+module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444); -+MODULE_PARM_DESC(ic_usb_cap, -+ "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled"); -+module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int, -+ 0444); -+MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio"); -+module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444); -+MODULE_PARM_DESC(power_down, "Power Down Mode"); -+module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444); -+MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control"); -+module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444); -+MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK"); -+module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444); -+MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA"); -+module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444); -+MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support"); -+module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444); -+MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled"); -+module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444); -+MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0"); -+module_param(microframe_schedule, bool, 0444); -+MODULE_PARM_DESC(microframe_schedule, "Enable the microframe scheduler"); -+ -+module_param(fiq_enable, bool, 0444); -+MODULE_PARM_DESC(fiq_enable, "Enable the FIQ"); -+module_param(nak_holdoff, ushort, 0644); -+MODULE_PARM_DESC(nak_holdoff, "Throttle duration for bulk split-transaction endpoints on a NAK. Default 8"); -+module_param(fiq_fsm_enable, bool, 0444); -+MODULE_PARM_DESC(fiq_fsm_enable, "Enable the FIQ to perform split transactions as defined by fiq_fsm_mask"); -+module_param(fiq_fsm_mask, ushort, 0444); -+MODULE_PARM_DESC(fiq_fsm_mask, "Bitmask of transactions to perform in the FIQ.\n" -+ "Bit 0 : Non-periodic split transactions\n" -+ "Bit 1 : Periodic split transactions\n" -+ "Bit 2 : High-speed multi-transfer isochronous\n" -+ "All other bits should be set 0."); -+ -+ -+/** @page "Module Parameters" -+ * -+ * The following parameters may be specified when starting the module. -+ * These parameters define how the DWC_otg controller should be -+ * configured. Parameter values are passed to the CIL initialization -+ * function dwc_otg_cil_init -+ * -+ * Example: modprobe dwc_otg speed=1 otg_cap=1 -+ * -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+*/ -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_driver.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_driver.h ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_driver.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_driver.h 2015-11-29 09:42:39.919098694 +0100 -@@ -0,0 +1,86 @@ -+/* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.h $ -+ * $Revision: #19 $ -+ * $Date: 2010/11/15 $ -+ * $Change: 1627671 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+ -+#ifndef __DWC_OTG_DRIVER_H__ -+#define __DWC_OTG_DRIVER_H__ -+ -+/** @file -+ * This file contains the interface to the Linux driver. -+ */ -+#include "dwc_otg_os_dep.h" -+#include "dwc_otg_core_if.h" -+ -+/* Type declarations */ -+struct dwc_otg_pcd; -+struct dwc_otg_hcd; -+ -+/** -+ * This structure is a wrapper that encapsulates the driver components used to -+ * manage a single DWC_otg controller. -+ */ -+typedef struct dwc_otg_device { -+ /** Structure containing OS-dependent stuff. KEEP THIS STRUCT AT THE -+ * VERY BEGINNING OF THE DEVICE STRUCT. OSes such as FreeBSD and NetBSD -+ * require this. */ -+ struct os_dependent os_dep; -+ -+ /** Pointer to the core interface structure. */ -+ dwc_otg_core_if_t *core_if; -+ -+ /** Pointer to the PCD structure. */ -+ struct dwc_otg_pcd *pcd; -+ -+ /** Pointer to the HCD structure. */ -+ struct dwc_otg_hcd *hcd; -+ -+ /** Flag to indicate whether the common IRQ handler is installed. */ -+ uint8_t common_irq_installed; -+ -+} dwc_otg_device_t; -+ -+/*We must clear S3C24XX_EINTPEND external interrupt register -+ * because after clearing in this register trigerred IRQ from -+ * H/W core in kernel interrupt can be occured again before OTG -+ * handlers clear all IRQ sources of Core registers because of -+ * timing latencies and Low Level IRQ Type. -+ */ -+#ifdef CONFIG_MACH_IPMATE -+#define S3C2410X_CLEAR_EINTPEND() \ -+do { \ -+ __raw_writel(1UL << 11,S3C24XX_EINTPEND); \ -+} while (0) -+#else -+#define S3C2410X_CLEAR_EINTPEND() do { } while (0) -+#endif -+ -+#endif -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c 2015-11-29 09:42:39.919098694 +0100 -@@ -0,0 +1,1355 @@ -+/* -+ * dwc_otg_fiq_fsm.c - The finite state machine FIQ -+ * -+ * Copyright (c) 2013 Raspberry Pi Foundation -+ * -+ * Author: Jonathan Bell -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Raspberry Pi nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * This FIQ implements functionality that performs split transactions on -+ * the dwc_otg hardware without any outside intervention. A split transaction -+ * is "queued" by nominating a specific host channel to perform the entirety -+ * of a split transaction. This FIQ will then perform the microframe-precise -+ * scheduling required in each phase of the transaction until completion. -+ * -+ * The FIQ functionality is glued into the Synopsys driver via the entry point -+ * in the FSM enqueue function, and at the exit point in handling a HC interrupt -+ * for a FSM-enabled channel. -+ * -+ * NB: Large parts of this implementation have architecture-specific code. -+ * For porting this functionality to other ARM machines, the minimum is required: -+ * - An interrupt controller allowing the top-level dwc USB interrupt to be routed -+ * to the FIQ -+ * - A method of forcing a software generated interrupt from FIQ mode that then -+ * triggers an IRQ entry (with the dwc USB handler called by this IRQ number) -+ * - Guaranteed interrupt routing such that both the FIQ and SGI occur on the same -+ * processor core - there is no locking between the FIQ and IRQ (aside from -+ * local_fiq_disable) -+ * -+ */ -+ -+#include "dwc_otg_fiq_fsm.h" -+ -+ -+char buffer[1000*16]; -+int wptr; -+void notrace _fiq_print(enum fiq_debug_level dbg_lvl, volatile struct fiq_state *state, char *fmt, ...) -+{ -+ enum fiq_debug_level dbg_lvl_req = FIQDBG_ERR; -+ va_list args; -+ char text[17]; -+ hfnum_data_t hfnum = { .d32 = FIQ_READ(state->dwc_regs_base + 0x408) }; -+ -+ if((dbg_lvl & dbg_lvl_req) || dbg_lvl == FIQDBG_ERR) -+ { -+ snprintf(text, 9, " %4d:%1u ", hfnum.b.frnum/8, hfnum.b.frnum & 7); -+ va_start(args, fmt); -+ vsnprintf(text+8, 9, fmt, args); -+ va_end(args); -+ -+ memcpy(buffer + wptr, text, 16); -+ wptr = (wptr + 16) % sizeof(buffer); -+ } -+} -+ -+/** -+ * fiq_fsm_spin_lock() - ARMv6+ bare bones spinlock -+ * Must be called with local interrupts and FIQ disabled. -+ */ -+#if defined(CONFIG_ARCH_BCM2709) && defined(CONFIG_SMP) -+inline void fiq_fsm_spin_lock(fiq_lock_t *lock) -+{ -+ unsigned long tmp; -+ uint32_t newval; -+ fiq_lock_t lockval; -+ smp_mb__before_spinlock(); -+ /* Nested locking, yay. If we are on the same CPU as the fiq, then the disable -+ * will be sufficient. If we are on a different CPU, then the lock protects us. */ -+ prefetchw(&lock->slock); -+ asm volatile ( -+ "1: ldrex %0, [%3]\n" -+ " add %1, %0, %4\n" -+ " strex %2, %1, [%3]\n" -+ " teq %2, #0\n" -+ " bne 1b" -+ : "=&r" (lockval), "=&r" (newval), "=&r" (tmp) -+ : "r" (&lock->slock), "I" (1 << 16) -+ : "cc"); -+ -+ while (lockval.tickets.next != lockval.tickets.owner) { -+ wfe(); -+ lockval.tickets.owner = ACCESS_ONCE(lock->tickets.owner); -+ } -+ smp_mb(); -+} -+#else -+inline void fiq_fsm_spin_lock(fiq_lock_t *lock) { } -+#endif -+ -+/** -+ * fiq_fsm_spin_unlock() - ARMv6+ bare bones spinunlock -+ */ -+#if defined(CONFIG_ARCH_BCM2709) && defined(CONFIG_SMP) -+inline void fiq_fsm_spin_unlock(fiq_lock_t *lock) -+{ -+ smp_mb(); -+ lock->tickets.owner++; -+ dsb_sev(); -+} -+#else -+inline void fiq_fsm_spin_unlock(fiq_lock_t *lock) { } -+#endif -+ -+/** -+ * fiq_fsm_restart_channel() - Poke channel enable bit for a split transaction -+ * @channel: channel to re-enable -+ */ -+static void fiq_fsm_restart_channel(struct fiq_state *st, int n, int force) -+{ -+ hcchar_data_t hcchar = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR) }; -+ -+ hcchar.b.chen = 0; -+ if (st->channel[n].hcchar_copy.b.eptype & 0x1) { -+ hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) }; -+ /* Hardware bug workaround: update the ssplit index */ -+ if (st->channel[n].hcsplt_copy.b.spltena) -+ st->channel[n].expected_uframe = (hfnum.b.frnum + 1) & 0x3FFF; -+ -+ hcchar.b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1; -+ } -+ -+ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, hcchar.d32); -+ hcchar.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR); -+ hcchar.b.chen = 1; -+ -+ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, hcchar.d32); -+ fiq_print(FIQDBG_INT, st, "HCGO %01d %01d", n, force); -+} -+ -+/** -+ * fiq_fsm_setup_csplit() - Prepare a host channel for a CSplit transaction stage -+ * @st: Pointer to the channel's state -+ * @n : channel number -+ * -+ * Change host channel registers to perform a complete-split transaction. Being mindful of the -+ * endpoint direction, set control regs up correctly. -+ */ -+static void notrace fiq_fsm_setup_csplit(struct fiq_state *st, int n) -+{ -+ hcsplt_data_t hcsplt = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT) }; -+ hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) }; -+ -+ hcsplt.b.compsplt = 1; -+ if (st->channel[n].hcchar_copy.b.epdir == 1) { -+ // If IN, the CSPLIT result contains the data or a hub handshake. hctsiz = maxpacket. -+ hctsiz.b.xfersize = st->channel[n].hctsiz_copy.b.xfersize; -+ } else { -+ // If OUT, the CSPLIT result contains handshake only. -+ hctsiz.b.xfersize = 0; -+ } -+ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT, hcsplt.d32); -+ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32); -+ mb(); -+} -+ -+static inline int notrace fiq_get_xfer_len(struct fiq_state *st, int n) -+{ -+ /* The xfersize register is a bit wonky. For IN transfers, it decrements by the packet size. */ -+ hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) }; -+ -+ if (st->channel[n].hcchar_copy.b.epdir == 0) { -+ return st->channel[n].hctsiz_copy.b.xfersize; -+ } else { -+ return st->channel[n].hctsiz_copy.b.xfersize - hctsiz.b.xfersize; -+ } -+ -+} -+ -+ -+/** -+ * fiq_increment_dma_buf() - update DMA address for bounce buffers after a CSPLIT -+ * -+ * Of use only for IN periodic transfers. -+ */ -+static int notrace fiq_increment_dma_buf(struct fiq_state *st, int num_channels, int n) -+{ -+ hcdma_data_t hcdma; -+ int i = st->channel[n].dma_info.index; -+ int len; -+ struct fiq_dma_blob *blob = (struct fiq_dma_blob *) st->dma_base; -+ -+ len = fiq_get_xfer_len(st, n); -+ fiq_print(FIQDBG_INT, st, "LEN: %03d", len); -+ st->channel[n].dma_info.slot_len[i] = len; -+ i++; -+ if (i > 6) -+ BUG(); -+ -+ hcdma.d32 = (dma_addr_t) &blob->channel[n].index[i].buf[0]; -+ FIQ_WRITE(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32); -+ st->channel[n].dma_info.index = i; -+ return 0; -+} -+ -+/** -+ * fiq_reload_hctsiz() - for IN transactions, reset HCTSIZ -+ */ -+static void notrace fiq_fsm_reload_hctsiz(struct fiq_state *st, int n) -+{ -+ hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) }; -+ hctsiz.b.xfersize = st->channel[n].hctsiz_copy.b.xfersize; -+ hctsiz.b.pktcnt = 1; -+ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32); -+} -+ -+/** -+ * fiq_iso_out_advance() - update DMA address and split position bits -+ * for isochronous OUT transactions. -+ * -+ * Returns 1 if this is the last packet queued, 0 otherwise. Split-ALL and -+ * Split-BEGIN states are not handled - this is done when the transaction was queued. -+ * -+ * This function must only be called from the FIQ_ISO_OUT_ACTIVE state. -+ */ -+static int notrace fiq_iso_out_advance(struct fiq_state *st, int num_channels, int n) -+{ -+ hcsplt_data_t hcsplt; -+ hctsiz_data_t hctsiz; -+ hcdma_data_t hcdma; -+ struct fiq_dma_blob *blob = (struct fiq_dma_blob *) st->dma_base; -+ int last = 0; -+ int i = st->channel[n].dma_info.index; -+ -+ fiq_print(FIQDBG_INT, st, "ADV %01d %01d ", n, i); -+ i++; -+ if (i == 4) -+ last = 1; -+ if (st->channel[n].dma_info.slot_len[i+1] == 255) -+ last = 1; -+ -+ /* New DMA address - address of bounce buffer referred to in index */ -+ hcdma.d32 = (uint32_t) &blob->channel[n].index[i].buf[0]; -+ //hcdma.d32 = FIQ_READ(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n)); -+ //hcdma.d32 += st->channel[n].dma_info.slot_len[i]; -+ fiq_print(FIQDBG_INT, st, "LAST: %01d ", last); -+ fiq_print(FIQDBG_INT, st, "LEN: %03d", st->channel[n].dma_info.slot_len[i]); -+ hcsplt.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT); -+ hctsiz.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ); -+ hcsplt.b.xactpos = (last) ? ISOC_XACTPOS_END : ISOC_XACTPOS_MID; -+ /* Set up new packet length */ -+ hctsiz.b.pktcnt = 1; -+ hctsiz.b.xfersize = st->channel[n].dma_info.slot_len[i]; -+ fiq_print(FIQDBG_INT, st, "%08x", hctsiz.d32); -+ -+ st->channel[n].dma_info.index++; -+ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT, hcsplt.d32); -+ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32); -+ FIQ_WRITE(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32); -+ return last; -+} -+ -+/** -+ * fiq_fsm_tt_next_isoc() - queue next pending isochronous out start-split on a TT -+ * -+ * Despite the limitations of the DWC core, we can force a microframe pipeline of -+ * isochronous OUT start-split transactions while waiting for a corresponding other-type -+ * of endpoint to finish its CSPLITs. TTs have big periodic buffers therefore it -+ * is very unlikely that filling the start-split FIFO will cause data loss. -+ * This allows much better interleaving of transactions in an order-independent way- -+ * there is no requirement to prioritise isochronous, just a state-space search has -+ * to be performed on each periodic start-split complete interrupt. -+ */ -+static int notrace fiq_fsm_tt_next_isoc(struct fiq_state *st, int num_channels, int n) -+{ -+ int hub_addr = st->channel[n].hub_addr; -+ int port_addr = st->channel[n].port_addr; -+ int i, poked = 0; -+ for (i = 0; i < num_channels; i++) { -+ if (i == n || st->channel[i].fsm == FIQ_PASSTHROUGH) -+ continue; -+ if (st->channel[i].hub_addr == hub_addr && -+ st->channel[i].port_addr == port_addr) { -+ switch (st->channel[i].fsm) { -+ case FIQ_PER_ISO_OUT_PENDING: -+ if (st->channel[i].nrpackets == 1) { -+ st->channel[i].fsm = FIQ_PER_ISO_OUT_LAST; -+ } else { -+ st->channel[i].fsm = FIQ_PER_ISO_OUT_ACTIVE; -+ } -+ fiq_fsm_restart_channel(st, i, 0); -+ poked = 1; -+ break; -+ -+ default: -+ break; -+ } -+ } -+ if (poked) -+ break; -+ } -+ return poked; -+} -+ -+/** -+ * fiq_fsm_tt_in_use() - search for host channels using this TT -+ * @n: Channel to use as reference -+ * -+ */ -+int notrace noinline fiq_fsm_tt_in_use(struct fiq_state *st, int num_channels, int n) -+{ -+ int hub_addr = st->channel[n].hub_addr; -+ int port_addr = st->channel[n].port_addr; -+ int i, in_use = 0; -+ for (i = 0; i < num_channels; i++) { -+ if (i == n || st->channel[i].fsm == FIQ_PASSTHROUGH) -+ continue; -+ switch (st->channel[i].fsm) { -+ /* TT is reserved for channels that are in the middle of a periodic -+ * split transaction. -+ */ -+ case FIQ_PER_SSPLIT_STARTED: -+ case FIQ_PER_CSPLIT_WAIT: -+ case FIQ_PER_CSPLIT_NYET1: -+ //case FIQ_PER_CSPLIT_POLL: -+ case FIQ_PER_ISO_OUT_ACTIVE: -+ case FIQ_PER_ISO_OUT_LAST: -+ if (st->channel[i].hub_addr == hub_addr && -+ st->channel[i].port_addr == port_addr) { -+ in_use = 1; -+ } -+ break; -+ default: -+ break; -+ } -+ if (in_use) -+ break; -+ } -+ return in_use; -+} -+ -+/** -+ * fiq_fsm_more_csplits() - determine whether additional CSPLITs need -+ * to be issued for this IN transaction. -+ * -+ * We cannot tell the inbound PID of a data packet due to hardware limitations. -+ * we need to make an educated guess as to whether we need to queue another CSPLIT -+ * or not. A no-brainer is when we have received enough data to fill the endpoint -+ * size, but for endpoints that give variable-length data then we have to resort -+ * to heuristics. -+ * -+ * We also return whether this is the last CSPLIT to be queued, again based on -+ * heuristics. This is to allow a 1-uframe overlap of periodic split transactions. -+ * Note: requires at least 1 CSPLIT to have been performed prior to being called. -+ */ -+ -+/* -+ * We need some way of guaranteeing if a returned periodic packet of size X -+ * has a DATA0 PID. -+ * The heuristic value of 144 bytes assumes that the received data has maximal -+ * bit-stuffing and the clock frequency of the transmitting device is at the lowest -+ * permissible limit. If the transfer length results in a final packet size -+ * 144 < p <= 188, then an erroneous CSPLIT will be issued. -+ * Also used to ensure that an endpoint will nominally only return a single -+ * complete-split worth of data. -+ */ -+#define DATA0_PID_HEURISTIC 144 -+ -+static int notrace noinline fiq_fsm_more_csplits(struct fiq_state *state, int n, int *probably_last) -+{ -+ -+ int i; -+ int total_len = 0; -+ int more_needed = 1; -+ struct fiq_channel_state *st = &state->channel[n]; -+ -+ for (i = 0; i < st->dma_info.index; i++) { -+ total_len += st->dma_info.slot_len[i]; -+ } -+ -+ *probably_last = 0; -+ -+ if (st->hcchar_copy.b.eptype == 0x3) { -+ /* -+ * An interrupt endpoint will take max 2 CSPLITs. if we are receiving data -+ * then this is definitely the last CSPLIT. -+ */ -+ *probably_last = 1; -+ } else { -+ /* Isoc IN. This is a bit risky if we are the first transaction: -+ * we may have been held off slightly. */ -+ if (i > 1 && st->dma_info.slot_len[st->dma_info.index-1] <= DATA0_PID_HEURISTIC) { -+ more_needed = 0; -+ } -+ /* If in the next uframe we will receive enough data to fill the endpoint, -+ * then only issue 1 more csplit. -+ */ -+ if (st->hctsiz_copy.b.xfersize - total_len <= DATA0_PID_HEURISTIC) -+ *probably_last = 1; -+ } -+ -+ if (total_len >= st->hctsiz_copy.b.xfersize || -+ i == 6 || total_len == 0) -+ /* Note: due to bit stuffing it is possible to have > 6 CSPLITs for -+ * a single endpoint. Accepting more would completely break our scheduling mechanism though -+ * - in these extreme cases we will pass through a truncated packet. -+ */ -+ more_needed = 0; -+ -+ return more_needed; -+} -+ -+/** -+ * fiq_fsm_too_late() - Test transaction for lateness -+ * -+ * If a SSPLIT for a large IN transaction is issued too late in a frame, -+ * the hub will disable the port to the device and respond with ERR handshakes. -+ * The hub status endpoint will not reflect this change. -+ * Returns 1 if we will issue a SSPLIT that will result in a device babble. -+ */ -+int notrace fiq_fsm_too_late(struct fiq_state *st, int n) -+{ -+ int uframe; -+ hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) }; -+ uframe = hfnum.b.frnum & 0x7; -+ if ((uframe < 6) && (st->channel[n].nrpackets + 1 + uframe > 7)) { -+ return 1; -+ } else { -+ return 0; -+ } -+} -+ -+ -+/** -+ * fiq_fsm_start_next_periodic() - A half-arsed attempt at a microframe pipeline -+ * -+ * Search pending transactions in the start-split pending state and queue them. -+ * Don't queue packets in uframe .5 (comes out in .6) (USB2.0 11.18.4). -+ * Note: we specifically don't do isochronous OUT transactions first because better -+ * use of the TT's start-split fifo can be achieved by pipelining an IN before an OUT. -+ */ -+static void notrace noinline fiq_fsm_start_next_periodic(struct fiq_state *st, int num_channels) -+{ -+ int n; -+ hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) }; -+ if ((hfnum.b.frnum & 0x7) == 5) -+ return; -+ for (n = 0; n < num_channels; n++) { -+ if (st->channel[n].fsm == FIQ_PER_SSPLIT_QUEUED) { -+ /* Check to see if any other transactions are using this TT */ -+ if(!fiq_fsm_tt_in_use(st, num_channels, n)) { -+ if (!fiq_fsm_too_late(st, n)) { -+ st->channel[n].fsm = FIQ_PER_SSPLIT_STARTED; -+ fiq_print(FIQDBG_INT, st, "NEXTPER "); -+ fiq_fsm_restart_channel(st, n, 0); -+ } else { -+ st->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT; -+ } -+ break; -+ } -+ } -+ } -+ for (n = 0; n < num_channels; n++) { -+ if (st->channel[n].fsm == FIQ_PER_ISO_OUT_PENDING) { -+ if (!fiq_fsm_tt_in_use(st, num_channels, n)) { -+ fiq_print(FIQDBG_INT, st, "NEXTISO "); -+ st->channel[n].fsm = FIQ_PER_ISO_OUT_ACTIVE; -+ fiq_fsm_restart_channel(st, n, 0); -+ break; -+ } -+ } -+ } -+} -+ -+/** -+ * fiq_fsm_update_hs_isoc() - update isochronous frame and transfer data -+ * @state: Pointer to fiq_state -+ * @n: Channel transaction is active on -+ * @hcint: Copy of host channel interrupt register -+ * -+ * Returns 0 if there are no more transactions for this HC to do, 1 -+ * otherwise. -+ */ -+static int notrace noinline fiq_fsm_update_hs_isoc(struct fiq_state *state, int n, hcint_data_t hcint) -+{ -+ struct fiq_channel_state *st = &state->channel[n]; -+ int xfer_len = 0, nrpackets = 0; -+ hcdma_data_t hcdma; -+ fiq_print(FIQDBG_INT, state, "HSISO %02d", n); -+ -+ xfer_len = fiq_get_xfer_len(state, n); -+ st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].actual_length = xfer_len; -+ -+ st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].status = hcint.d32; -+ -+ st->hs_isoc_info.index++; -+ if (st->hs_isoc_info.index == st->hs_isoc_info.nrframes) { -+ return 0; -+ } -+ -+ /* grab the next DMA address offset from the array */ -+ hcdma.d32 = st->hcdma_copy.d32 + st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].offset; -+ FIQ_WRITE(state->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32); -+ -+ /* We need to set multi_count. This is a bit tricky - has to be set per-transaction as -+ * the core needs to be told to send the correct number. Caution: for IN transfers, -+ * this is always set to the maximum size of the endpoint. */ -+ xfer_len = st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].length; -+ /* Integer divide in a FIQ: fun. FIXME: make this not suck */ -+ nrpackets = (xfer_len + st->hcchar_copy.b.mps - 1) / st->hcchar_copy.b.mps; -+ if (nrpackets == 0) -+ nrpackets = 1; -+ st->hcchar_copy.b.multicnt = nrpackets; -+ st->hctsiz_copy.b.pktcnt = nrpackets; -+ -+ /* Initial PID also needs to be set */ -+ if (st->hcchar_copy.b.epdir == 0) { -+ st->hctsiz_copy.b.xfersize = xfer_len; -+ switch (st->hcchar_copy.b.multicnt) { -+ case 1: -+ st->hctsiz_copy.b.pid = DWC_PID_DATA0; -+ break; -+ case 2: -+ case 3: -+ st->hctsiz_copy.b.pid = DWC_PID_MDATA; -+ break; -+ } -+ -+ } else { -+ switch (st->hcchar_copy.b.multicnt) { -+ st->hctsiz_copy.b.xfersize = nrpackets * st->hcchar_copy.b.mps; -+ case 1: -+ st->hctsiz_copy.b.pid = DWC_PID_DATA0; -+ break; -+ case 2: -+ st->hctsiz_copy.b.pid = DWC_PID_DATA1; -+ break; -+ case 3: -+ st->hctsiz_copy.b.pid = DWC_PID_DATA2; -+ break; -+ } -+ } -+ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, st->hctsiz_copy.d32); -+ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, st->hcchar_copy.d32); -+ /* Channel is enabled on hcint handler exit */ -+ fiq_print(FIQDBG_INT, state, "HSISOOUT"); -+ return 1; -+} -+ -+ -+/** -+ * fiq_fsm_do_sof() - FSM start-of-frame interrupt handler -+ * @state: Pointer to the state struct passed from banked FIQ mode registers. -+ * @num_channels: set according to the DWC hardware configuration -+ * -+ * The SOF handler in FSM mode has two functions -+ * 1. Hold off SOF from causing schedule advancement in IRQ context if there's -+ * nothing to do -+ * 2. Advance certain FSM states that require either a microframe delay, or a microframe -+ * of holdoff. -+ * -+ * The second part is architecture-specific to mach-bcm2835 - -+ * a sane interrupt controller would have a mask register for ARM interrupt sources -+ * to be promoted to the nFIQ line, but it doesn't. Instead a single interrupt -+ * number (USB) can be enabled. This means that certain parts of the USB specification -+ * that require "wait a little while, then issue another packet" cannot be fulfilled with -+ * the timing granularity required to achieve optimal throughout. The workaround is to use -+ * the SOF "timer" (125uS) to perform this task. -+ */ -+static int notrace noinline fiq_fsm_do_sof(struct fiq_state *state, int num_channels) -+{ -+ hfnum_data_t hfnum = { .d32 = FIQ_READ(state->dwc_regs_base + HFNUM) }; -+ int n; -+ int kick_irq = 0; -+ -+ if ((hfnum.b.frnum & 0x7) == 1) { -+ /* We cannot issue csplits for transactions in the last frame past (n+1).1 -+ * Check to see if there are any transactions that are stale. -+ * Boot them out. -+ */ -+ for (n = 0; n < num_channels; n++) { -+ switch (state->channel[n].fsm) { -+ case FIQ_PER_CSPLIT_WAIT: -+ case FIQ_PER_CSPLIT_NYET1: -+ case FIQ_PER_CSPLIT_POLL: -+ case FIQ_PER_CSPLIT_LAST: -+ /* Check if we are no longer in the same full-speed frame. */ -+ if (((state->channel[n].expected_uframe & 0x3FFF) & ~0x7) < -+ (hfnum.b.frnum & ~0x7)) -+ state->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT; -+ break; -+ default: -+ break; -+ } -+ } -+ } -+ -+ for (n = 0; n < num_channels; n++) { -+ switch (state->channel[n].fsm) { -+ -+ case FIQ_NP_SSPLIT_RETRY: -+ case FIQ_NP_IN_CSPLIT_RETRY: -+ case FIQ_NP_OUT_CSPLIT_RETRY: -+ fiq_fsm_restart_channel(state, n, 0); -+ break; -+ -+ case FIQ_HS_ISOC_SLEEPING: -+ /* Is it time to wake this channel yet? */ -+ if (--state->channel[n].uframe_sleeps == 0) { -+ state->channel[n].fsm = FIQ_HS_ISOC_TURBO; -+ fiq_fsm_restart_channel(state, n, 0); -+ } -+ break; -+ -+ case FIQ_PER_SSPLIT_QUEUED: -+ if ((hfnum.b.frnum & 0x7) == 5) -+ break; -+ if(!fiq_fsm_tt_in_use(state, num_channels, n)) { -+ if (!fiq_fsm_too_late(state, n)) { -+ fiq_print(FIQDBG_INT, state, "SOF GO %01d", n); -+ fiq_fsm_restart_channel(state, n, 0); -+ state->channel[n].fsm = FIQ_PER_SSPLIT_STARTED; -+ } else { -+ /* Transaction cannot be started without risking a device babble error */ -+ state->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT; -+ state->haintmsk_saved.b2.chint &= ~(1 << n); -+ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, 0); -+ kick_irq |= 1; -+ } -+ } -+ break; -+ -+ case FIQ_PER_ISO_OUT_PENDING: -+ /* Ordinarily, this should be poked after the SSPLIT -+ * complete interrupt for a competing transfer on the same -+ * TT. Doesn't happen for aborted transactions though. -+ */ -+ if ((hfnum.b.frnum & 0x7) >= 5) -+ break; -+ if (!fiq_fsm_tt_in_use(state, num_channels, n)) { -+ /* Hardware bug. SOF can sometimes occur after the channel halt interrupt -+ * that caused this. -+ */ -+ fiq_fsm_restart_channel(state, n, 0); -+ fiq_print(FIQDBG_INT, state, "SOF ISOC"); -+ if (state->channel[n].nrpackets == 1) { -+ state->channel[n].fsm = FIQ_PER_ISO_OUT_LAST; -+ } else { -+ state->channel[n].fsm = FIQ_PER_ISO_OUT_ACTIVE; -+ } -+ } -+ break; -+ -+ case FIQ_PER_CSPLIT_WAIT: -+ /* we are guaranteed to be in this state if and only if the SSPLIT interrupt -+ * occurred when the bus transaction occurred. The SOF interrupt reversal bug -+ * will utterly bugger this up though. -+ */ -+ if (hfnum.b.frnum != state->channel[n].expected_uframe) { -+ fiq_print(FIQDBG_INT, state, "SOFCS %d ", n); -+ state->channel[n].fsm = FIQ_PER_CSPLIT_POLL; -+ fiq_fsm_restart_channel(state, n, 0); -+ fiq_fsm_start_next_periodic(state, num_channels); -+ -+ } -+ break; -+ -+ case FIQ_PER_SPLIT_TIMEOUT: -+ case FIQ_DEQUEUE_ISSUED: -+ /* Ugly: we have to force a HCD interrupt. -+ * Poke the mask for the channel in question. -+ * We will take a fake SOF because of this, but -+ * that's OK. -+ */ -+ state->haintmsk_saved.b2.chint &= ~(1 << n); -+ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, 0); -+ kick_irq |= 1; -+ break; -+ -+ default: -+ break; -+ } -+ } -+ -+ if (state->kick_np_queues || -+ dwc_frame_num_le(state->next_sched_frame, hfnum.b.frnum)) -+ kick_irq |= 1; -+ -+ return !kick_irq; -+} -+ -+ -+/** -+ * fiq_fsm_do_hcintr() - FSM host channel interrupt handler -+ * @state: Pointer to the FIQ state struct -+ * @num_channels: Number of channels as per hardware config -+ * @n: channel for which HAINT(i) was raised -+ * -+ * An important property is that only the CHHLT interrupt is unmasked. Unfortunately, AHBerr is as well. -+ */ -+static int notrace noinline fiq_fsm_do_hcintr(struct fiq_state *state, int num_channels, int n) -+{ -+ hcint_data_t hcint; -+ hcintmsk_data_t hcintmsk; -+ hcint_data_t hcint_probe; -+ hcchar_data_t hcchar; -+ int handled = 0; -+ int restart = 0; -+ int last_csplit = 0; -+ int start_next_periodic = 0; -+ struct fiq_channel_state *st = &state->channel[n]; -+ hfnum_data_t hfnum; -+ -+ hcint.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINT); -+ hcintmsk.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK); -+ hcint_probe.d32 = hcint.d32 & hcintmsk.d32; -+ -+ if (st->fsm != FIQ_PASSTHROUGH) { -+ fiq_print(FIQDBG_INT, state, "HC%01d ST%02d", n, st->fsm); -+ fiq_print(FIQDBG_INT, state, "%08x", hcint.d32); -+ } -+ -+ switch (st->fsm) { -+ -+ case FIQ_PASSTHROUGH: -+ case FIQ_DEQUEUE_ISSUED: -+ /* doesn't belong to us, kick it upstairs */ -+ break; -+ -+ case FIQ_PASSTHROUGH_ERRORSTATE: -+ /* We are here to emulate the error recovery mechanism of the dwc HCD. -+ * Several interrupts are unmasked if a previous transaction failed - it's -+ * death for the FIQ to attempt to handle them as the channel isn't halted. -+ * Emulate what the HCD does in this situation: mask and continue. -+ * The FSM has no other state setup so this has to be handled out-of-band. -+ */ -+ fiq_print(FIQDBG_ERR, state, "ERRST %02d", n); -+ if (hcint_probe.b.nak || hcint_probe.b.ack || hcint_probe.b.datatglerr) { -+ fiq_print(FIQDBG_ERR, state, "RESET %02d", n); -+ /* In some random cases we can get a NAK interrupt coincident with a Xacterr -+ * interrupt, after the device has disappeared. -+ */ -+ if (!hcint.b.xacterr) -+ st->nr_errors = 0; -+ hcintmsk.b.nak = 0; -+ hcintmsk.b.ack = 0; -+ hcintmsk.b.datatglerr = 0; -+ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, hcintmsk.d32); -+ return 1; -+ } -+ if (hcint_probe.b.chhltd) { -+ fiq_print(FIQDBG_ERR, state, "CHHLT %02d", n); -+ fiq_print(FIQDBG_ERR, state, "%08x", hcint.d32); -+ return 0; -+ } -+ break; -+ -+ /* Non-periodic state groups */ -+ case FIQ_NP_SSPLIT_STARTED: -+ case FIQ_NP_SSPLIT_RETRY: -+ /* Got a HCINT for a NP SSPLIT. Expected ACK / NAK / fail */ -+ if (hcint.b.ack) { -+ /* SSPLIT complete. For OUT, the data has been sent. For IN, the LS transaction -+ * will start shortly. SOF needs to kick the transaction to prevent a NYET flood. -+ */ -+ if(st->hcchar_copy.b.epdir == 1) -+ st->fsm = FIQ_NP_IN_CSPLIT_RETRY; -+ else -+ st->fsm = FIQ_NP_OUT_CSPLIT_RETRY; -+ st->nr_errors = 0; -+ handled = 1; -+ fiq_fsm_setup_csplit(state, n); -+ } else if (hcint.b.nak) { -+ // No buffer space in TT. Retry on a uframe boundary. -+ st->fsm = FIQ_NP_SSPLIT_RETRY; -+ handled = 1; -+ } else if (hcint.b.xacterr) { -+ // The only other one we care about is xacterr. This implies HS bus error - retry. -+ st->nr_errors++; -+ st->fsm = FIQ_NP_SSPLIT_RETRY; -+ if (st->nr_errors >= 3) { -+ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; -+ } else { -+ handled = 1; -+ restart = 1; -+ } -+ } else { -+ st->fsm = FIQ_NP_SPLIT_LS_ABORTED; -+ handled = 0; -+ restart = 0; -+ } -+ break; -+ -+ case FIQ_NP_IN_CSPLIT_RETRY: -+ /* Received a CSPLIT done interrupt. -+ * Expected Data/NAK/STALL/NYET for IN. -+ */ -+ if (hcint.b.xfercomp) { -+ /* For IN, data is present. */ -+ st->fsm = FIQ_NP_SPLIT_DONE; -+ } else if (hcint.b.nak) { -+ /* no endpoint data. Punt it upstairs */ -+ st->fsm = FIQ_NP_SPLIT_DONE; -+ } else if (hcint.b.nyet) { -+ /* CSPLIT NYET - retry on a uframe boundary. */ -+ handled = 1; -+ st->nr_errors = 0; -+ } else if (hcint.b.datatglerr) { -+ /* data toggle errors do not set the xfercomp bit. */ -+ st->fsm = FIQ_NP_SPLIT_LS_ABORTED; -+ } else if (hcint.b.xacterr) { -+ /* HS error. Retry immediate */ -+ st->fsm = FIQ_NP_IN_CSPLIT_RETRY; -+ st->nr_errors++; -+ if (st->nr_errors >= 3) { -+ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; -+ } else { -+ handled = 1; -+ restart = 1; -+ } -+ } else if (hcint.b.stall || hcint.b.bblerr) { -+ /* A STALL implies either a LS bus error or a genuine STALL. */ -+ st->fsm = FIQ_NP_SPLIT_LS_ABORTED; -+ } else { -+ /* Hardware bug. It's possible in some cases to -+ * get a channel halt with nothing else set when -+ * the response was a NYET. Treat as local 3-strikes retry. -+ */ -+ hcint_data_t hcint_test = hcint; -+ hcint_test.b.chhltd = 0; -+ if (!hcint_test.d32) { -+ st->nr_errors++; -+ if (st->nr_errors >= 3) { -+ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; -+ } else { -+ handled = 1; -+ } -+ } else { -+ /* Bail out if something unexpected happened */ -+ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; -+ } -+ } -+ break; -+ -+ case FIQ_NP_OUT_CSPLIT_RETRY: -+ /* Received a CSPLIT done interrupt. -+ * Expected ACK/NAK/STALL/NYET/XFERCOMP for OUT.*/ -+ if (hcint.b.xfercomp) { -+ st->fsm = FIQ_NP_SPLIT_DONE; -+ } else if (hcint.b.nak) { -+ // The HCD will implement the holdoff on frame boundaries. -+ st->fsm = FIQ_NP_SPLIT_DONE; -+ } else if (hcint.b.nyet) { -+ // Hub still processing. -+ st->fsm = FIQ_NP_OUT_CSPLIT_RETRY; -+ handled = 1; -+ st->nr_errors = 0; -+ //restart = 1; -+ } else if (hcint.b.xacterr) { -+ /* HS error. retry immediate */ -+ st->fsm = FIQ_NP_OUT_CSPLIT_RETRY; -+ st->nr_errors++; -+ if (st->nr_errors >= 3) { -+ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; -+ } else { -+ handled = 1; -+ restart = 1; -+ } -+ } else if (hcint.b.stall) { -+ /* LS bus error or genuine stall */ -+ st->fsm = FIQ_NP_SPLIT_LS_ABORTED; -+ } else { -+ /* -+ * Hardware bug. It's possible in some cases to get a -+ * channel halt with nothing else set when the response was a NYET. -+ * Treat as local 3-strikes retry. -+ */ -+ hcint_data_t hcint_test = hcint; -+ hcint_test.b.chhltd = 0; -+ if (!hcint_test.d32) { -+ st->nr_errors++; -+ if (st->nr_errors >= 3) { -+ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; -+ } else { -+ handled = 1; -+ } -+ } else { -+ // Something unexpected happened. AHBerror or babble perhaps. Let the IRQ deal with it. -+ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; -+ } -+ } -+ break; -+ -+ /* Periodic split states (except isoc out) */ -+ case FIQ_PER_SSPLIT_STARTED: -+ /* Expect an ACK or failure for SSPLIT */ -+ if (hcint.b.ack) { -+ /* -+ * SSPLIT transfer complete interrupt - the generation of this interrupt is fraught with bugs. -+ * For a packet queued in microframe n-3 to appear in n-2, if the channel is enabled near the EOF1 -+ * point for microframe n-3, the packet will not appear on the bus until microframe n. -+ * Additionally, the generation of the actual interrupt is dodgy. For a packet appearing on the bus -+ * in microframe n, sometimes the interrupt is generated immediately. Sometimes, it appears in n+1 -+ * coincident with SOF for n+1. -+ * SOF is also buggy. It can sometimes be raised AFTER the first bus transaction has taken place. -+ * These appear to be caused by timing/clock crossing bugs within the core itself. -+ * State machine workaround. -+ */ -+ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM); -+ hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR); -+ fiq_fsm_setup_csplit(state, n); -+ /* Poke the oddfrm bit. If we are equivalent, we received the interrupt at the correct -+ * time. If not, then we're in the next SOF. -+ */ -+ if ((hfnum.b.frnum & 0x1) == hcchar.b.oddfrm) { -+ fiq_print(FIQDBG_INT, state, "CSWAIT %01d", n); -+ st->expected_uframe = hfnum.b.frnum; -+ st->fsm = FIQ_PER_CSPLIT_WAIT; -+ } else { -+ fiq_print(FIQDBG_INT, state, "CSPOL %01d", n); -+ /* For isochronous IN endpoints, -+ * we need to hold off if we are expecting a lot of data */ -+ if (st->hcchar_copy.b.mps < DATA0_PID_HEURISTIC) { -+ start_next_periodic = 1; -+ } -+ /* Danger will robinson: we are in a broken state. If our first interrupt after -+ * this is a NYET, it will be delayed by 1 uframe and result in an unrecoverable -+ * lag. Unmask the NYET interrupt. -+ */ -+ st->expected_uframe = (hfnum.b.frnum + 1) & 0x3FFF; -+ st->fsm = FIQ_PER_CSPLIT_BROKEN_NYET1; -+ restart = 1; -+ } -+ handled = 1; -+ } else if (hcint.b.xacterr) { -+ /* 3-strikes retry is enabled, we have hit our max nr_errors */ -+ st->fsm = FIQ_PER_SPLIT_HS_ABORTED; -+ start_next_periodic = 1; -+ } else { -+ st->fsm = FIQ_PER_SPLIT_HS_ABORTED; -+ start_next_periodic = 1; -+ } -+ /* We can now queue the next isochronous OUT transaction, if one is pending. */ -+ if(fiq_fsm_tt_next_isoc(state, num_channels, n)) { -+ fiq_print(FIQDBG_INT, state, "NEXTISO "); -+ } -+ break; -+ -+ case FIQ_PER_CSPLIT_NYET1: -+ /* First CSPLIT attempt was a NYET. If we get a subsequent NYET, -+ * we are too late and the TT has dropped its CSPLIT fifo. -+ */ -+ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM); -+ hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR); -+ start_next_periodic = 1; -+ if (hcint.b.nak) { -+ st->fsm = FIQ_PER_SPLIT_DONE; -+ } else if (hcint.b.xfercomp) { -+ fiq_increment_dma_buf(state, num_channels, n); -+ st->fsm = FIQ_PER_CSPLIT_POLL; -+ st->nr_errors = 0; -+ if (fiq_fsm_more_csplits(state, n, &last_csplit)) { -+ handled = 1; -+ restart = 1; -+ if (!last_csplit) -+ start_next_periodic = 0; -+ } else { -+ st->fsm = FIQ_PER_SPLIT_DONE; -+ } -+ } else if (hcint.b.nyet) { -+ /* Doh. Data lost. */ -+ st->fsm = FIQ_PER_SPLIT_NYET_ABORTED; -+ } else if (hcint.b.xacterr || hcint.b.stall || hcint.b.bblerr) { -+ st->fsm = FIQ_PER_SPLIT_LS_ABORTED; -+ } else { -+ st->fsm = FIQ_PER_SPLIT_HS_ABORTED; -+ } -+ break; -+ -+ case FIQ_PER_CSPLIT_BROKEN_NYET1: -+ /* -+ * we got here because our host channel is in the delayed-interrupt -+ * state and we cannot take a NYET interrupt any later than when it -+ * occurred. Disable then re-enable the channel if this happens to force -+ * CSPLITs to occur at the right time. -+ */ -+ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM); -+ hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR); -+ fiq_print(FIQDBG_INT, state, "BROK: %01d ", n); -+ if (hcint.b.nak) { -+ st->fsm = FIQ_PER_SPLIT_DONE; -+ start_next_periodic = 1; -+ } else if (hcint.b.xfercomp) { -+ fiq_increment_dma_buf(state, num_channels, n); -+ if (fiq_fsm_more_csplits(state, n, &last_csplit)) { -+ st->fsm = FIQ_PER_CSPLIT_POLL; -+ handled = 1; -+ restart = 1; -+ start_next_periodic = 1; -+ /* Reload HCTSIZ for the next transfer */ -+ fiq_fsm_reload_hctsiz(state, n); -+ if (!last_csplit) -+ start_next_periodic = 0; -+ } else { -+ st->fsm = FIQ_PER_SPLIT_DONE; -+ } -+ } else if (hcint.b.nyet) { -+ st->fsm = FIQ_PER_SPLIT_NYET_ABORTED; -+ start_next_periodic = 1; -+ } else if (hcint.b.xacterr || hcint.b.stall || hcint.b.bblerr) { -+ /* Local 3-strikes retry is handled by the core. This is a ERR response.*/ -+ st->fsm = FIQ_PER_SPLIT_LS_ABORTED; -+ } else { -+ st->fsm = FIQ_PER_SPLIT_HS_ABORTED; -+ } -+ break; -+ -+ case FIQ_PER_CSPLIT_POLL: -+ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM); -+ hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR); -+ start_next_periodic = 1; -+ if (hcint.b.nak) { -+ st->fsm = FIQ_PER_SPLIT_DONE; -+ } else if (hcint.b.xfercomp) { -+ fiq_increment_dma_buf(state, num_channels, n); -+ if (fiq_fsm_more_csplits(state, n, &last_csplit)) { -+ handled = 1; -+ restart = 1; -+ /* Reload HCTSIZ for the next transfer */ -+ fiq_fsm_reload_hctsiz(state, n); -+ if (!last_csplit) -+ start_next_periodic = 0; -+ } else { -+ st->fsm = FIQ_PER_SPLIT_DONE; -+ } -+ } else if (hcint.b.nyet) { -+ /* Are we a NYET after the first data packet? */ -+ if (st->nrpackets == 0) { -+ st->fsm = FIQ_PER_CSPLIT_NYET1; -+ handled = 1; -+ restart = 1; -+ } else { -+ /* We got a NYET when polling CSPLITs. Can happen -+ * if our heuristic fails, or if someone disables us -+ * for any significant length of time. -+ */ -+ if (st->nr_errors >= 3) { -+ st->fsm = FIQ_PER_SPLIT_NYET_ABORTED; -+ } else { -+ st->fsm = FIQ_PER_SPLIT_DONE; -+ } -+ } -+ } else if (hcint.b.xacterr || hcint.b.stall || hcint.b.bblerr) { -+ /* For xacterr, Local 3-strikes retry is handled by the core. This is a ERR response.*/ -+ st->fsm = FIQ_PER_SPLIT_LS_ABORTED; -+ } else { -+ st->fsm = FIQ_PER_SPLIT_HS_ABORTED; -+ } -+ break; -+ -+ case FIQ_HS_ISOC_TURBO: -+ if (fiq_fsm_update_hs_isoc(state, n, hcint)) { -+ /* more transactions to come */ -+ handled = 1; -+ fiq_print(FIQDBG_INT, state, "HSISO M "); -+ /* For strided transfers, put ourselves to sleep */ -+ if (st->hs_isoc_info.stride > 1) { -+ st->uframe_sleeps = st->hs_isoc_info.stride - 1; -+ st->fsm = FIQ_HS_ISOC_SLEEPING; -+ } else { -+ restart = 1; -+ } -+ } else { -+ st->fsm = FIQ_HS_ISOC_DONE; -+ fiq_print(FIQDBG_INT, state, "HSISO F "); -+ } -+ break; -+ -+ case FIQ_HS_ISOC_ABORTED: -+ /* This abort is called by the driver rewriting the state mid-transaction -+ * which allows the dequeue mechanism to work more effectively. -+ */ -+ break; -+ -+ case FIQ_PER_ISO_OUT_ACTIVE: -+ if (hcint.b.ack) { -+ if(fiq_iso_out_advance(state, num_channels, n)) { -+ /* last OUT transfer */ -+ st->fsm = FIQ_PER_ISO_OUT_LAST; -+ /* -+ * Assuming the periodic FIFO in the dwc core -+ * actually does its job properly, we can queue -+ * the next ssplit now and in theory, the wire -+ * transactions will be in-order. -+ */ -+ // No it doesn't. It appears to process requests in host channel order. -+ //start_next_periodic = 1; -+ } -+ handled = 1; -+ restart = 1; -+ } else { -+ /* -+ * Isochronous transactions carry on regardless. Log the error -+ * and continue. -+ */ -+ //explode += 1; -+ st->nr_errors++; -+ if(fiq_iso_out_advance(state, num_channels, n)) { -+ st->fsm = FIQ_PER_ISO_OUT_LAST; -+ //start_next_periodic = 1; -+ } -+ handled = 1; -+ restart = 1; -+ } -+ break; -+ -+ case FIQ_PER_ISO_OUT_LAST: -+ if (hcint.b.ack) { -+ /* All done here */ -+ st->fsm = FIQ_PER_ISO_OUT_DONE; -+ } else { -+ st->fsm = FIQ_PER_ISO_OUT_DONE; -+ st->nr_errors++; -+ } -+ start_next_periodic = 1; -+ break; -+ -+ case FIQ_PER_SPLIT_TIMEOUT: -+ /* SOF kicked us because we overran. */ -+ start_next_periodic = 1; -+ break; -+ -+ default: -+ break; -+ } -+ -+ if (handled) { -+ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINT, hcint.d32); -+ } else { -+ /* Copy the regs into the state so the IRQ knows what to do */ -+ st->hcint_copy.d32 = hcint.d32; -+ } -+ -+ if (restart) { -+ /* Restart always implies handled. */ -+ if (restart == 2) { -+ /* For complete-split INs, the show must go on. -+ * Force a channel restart */ -+ fiq_fsm_restart_channel(state, n, 1); -+ } else { -+ fiq_fsm_restart_channel(state, n, 0); -+ } -+ } -+ if (start_next_periodic) { -+ fiq_fsm_start_next_periodic(state, num_channels); -+ } -+ if (st->fsm != FIQ_PASSTHROUGH) -+ fiq_print(FIQDBG_INT, state, "FSMOUT%02d", st->fsm); -+ -+ return handled; -+} -+ -+ -+/** -+ * dwc_otg_fiq_fsm() - Flying State Machine (monster) FIQ -+ * @state: pointer to state struct passed from the banked FIQ mode registers. -+ * @num_channels: set according to the DWC hardware configuration -+ * @dma: pointer to DMA bounce buffers for split transaction slots -+ * -+ * The FSM FIQ performs the low-level tasks that normally would be performed by the microcode -+ * inside an EHCI or similar host controller regarding split transactions. The DWC core -+ * interrupts each and every time a split transaction packet is received or sent successfully. -+ * This results in either an interrupt storm when everything is working "properly", or -+ * the interrupt latency of the system in general breaks time-sensitive periodic split -+ * transactions. Pushing the low-level, but relatively easy state machine work into the FIQ -+ * solves these problems. -+ * -+ * Return: void -+ */ -+void notrace dwc_otg_fiq_fsm(struct fiq_state *state, int num_channels) -+{ -+ gintsts_data_t gintsts, gintsts_handled; -+ gintmsk_data_t gintmsk; -+ //hfnum_data_t hfnum; -+ haint_data_t haint, haint_handled; -+ haintmsk_data_t haintmsk; -+ int kick_irq = 0; -+ -+ gintsts_handled.d32 = 0; -+ haint_handled.d32 = 0; -+ -+ fiq_fsm_spin_lock(&state->lock); -+ gintsts.d32 = FIQ_READ(state->dwc_regs_base + GINTSTS); -+ gintmsk.d32 = FIQ_READ(state->dwc_regs_base + GINTMSK); -+ gintsts.d32 &= gintmsk.d32; -+ -+ if (gintsts.b.sofintr) { -+ /* For FSM mode, SOF is required to keep the state machine advance for -+ * certain stages of the periodic pipeline. It's death to mask this -+ * interrupt in that case. -+ */ -+ -+ if (!fiq_fsm_do_sof(state, num_channels)) { -+ /* Kick IRQ once. Queue advancement means that all pending transactions -+ * will get serviced when the IRQ finally executes. -+ */ -+ if (state->gintmsk_saved.b.sofintr == 1) -+ kick_irq |= 1; -+ state->gintmsk_saved.b.sofintr = 0; -+ } -+ gintsts_handled.b.sofintr = 1; -+ } -+ -+ if (gintsts.b.hcintr) { -+ int i; -+ haint.d32 = FIQ_READ(state->dwc_regs_base + HAINT); -+ haintmsk.d32 = FIQ_READ(state->dwc_regs_base + HAINTMSK); -+ haint.d32 &= haintmsk.d32; -+ haint_handled.d32 = 0; -+ for (i=0; ihaintmsk_saved.b2.chint &= ~(1 << i); -+ } else { -+ /* do_hcintr cleaned up after itself, but clear haint */ -+ haint_handled.b2.chint |= (1 << i); -+ } -+ } -+ } -+ -+ if (haint_handled.b2.chint) { -+ FIQ_WRITE(state->dwc_regs_base + HAINT, haint_handled.d32); -+ } -+ -+ if (haintmsk.d32 != (haintmsk.d32 & state->haintmsk_saved.d32)) { -+ /* -+ * This is necessary to avoid multiple retriggers of the MPHI in the case -+ * where interrupts are held off and HCINTs start to pile up. -+ * Only wake up the IRQ if a new interrupt came in, was not handled and was -+ * masked. -+ */ -+ haintmsk.d32 &= state->haintmsk_saved.d32; -+ FIQ_WRITE(state->dwc_regs_base + HAINTMSK, haintmsk.d32); -+ kick_irq |= 1; -+ } -+ /* Top-Level interrupt - always handled because it's level-sensitive */ -+ gintsts_handled.b.hcintr = 1; -+ } -+ -+ -+ /* Clear the bits in the saved register that were not handled but were triggered. */ -+ state->gintmsk_saved.d32 &= ~(gintsts.d32 & ~gintsts_handled.d32); -+ -+ /* FIQ didn't handle something - mask has changed - write new mask */ -+ if (gintmsk.d32 != (gintmsk.d32 & state->gintmsk_saved.d32)) { -+ gintmsk.d32 &= state->gintmsk_saved.d32; -+ gintmsk.b.sofintr = 1; -+ FIQ_WRITE(state->dwc_regs_base + GINTMSK, gintmsk.d32); -+// fiq_print(FIQDBG_INT, state, "KICKGINT"); -+// fiq_print(FIQDBG_INT, state, "%08x", gintmsk.d32); -+// fiq_print(FIQDBG_INT, state, "%08x", state->gintmsk_saved.d32); -+ kick_irq |= 1; -+ } -+ -+ if (gintsts_handled.d32) { -+ /* Only applies to edge-sensitive bits in GINTSTS */ -+ FIQ_WRITE(state->dwc_regs_base + GINTSTS, gintsts_handled.d32); -+ } -+ -+ /* We got an interrupt, didn't handle it. */ -+ if (kick_irq) { -+ state->mphi_int_count++; -+ FIQ_WRITE(state->mphi_regs.outdda, (int) state->dummy_send); -+ FIQ_WRITE(state->mphi_regs.outddb, (1<<29)); -+ -+ } -+ state->fiq_done++; -+ mb(); -+ fiq_fsm_spin_unlock(&state->lock); -+} -+ -+ -+/** -+ * dwc_otg_fiq_nop() - FIQ "lite" -+ * @state: pointer to state struct passed from the banked FIQ mode registers. -+ * -+ * The "nop" handler does not intervene on any interrupts other than SOF. -+ * It is limited in scope to deciding at each SOF if the IRQ SOF handler (which deals -+ * with non-periodic/periodic queues) needs to be kicked. -+ * -+ * This is done to hold off the SOF interrupt, which occurs at a rate of 8000 per second. -+ * -+ * Return: void -+ */ -+void notrace dwc_otg_fiq_nop(struct fiq_state *state) -+{ -+ gintsts_data_t gintsts, gintsts_handled; -+ gintmsk_data_t gintmsk; -+ hfnum_data_t hfnum; -+ -+ fiq_fsm_spin_lock(&state->lock); -+ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM); -+ gintsts.d32 = FIQ_READ(state->dwc_regs_base + GINTSTS); -+ gintmsk.d32 = FIQ_READ(state->dwc_regs_base + GINTMSK); -+ gintsts.d32 &= gintmsk.d32; -+ gintsts_handled.d32 = 0; -+ -+ if (gintsts.b.sofintr) { -+ if (!state->kick_np_queues && -+ dwc_frame_num_gt(state->next_sched_frame, hfnum.b.frnum)) { -+ /* SOF handled, no work to do, just ACK interrupt */ -+ gintsts_handled.b.sofintr = 1; -+ } else { -+ /* Kick IRQ */ -+ state->gintmsk_saved.b.sofintr = 0; -+ } -+ } -+ -+ /* Reset handled interrupts */ -+ if(gintsts_handled.d32) { -+ FIQ_WRITE(state->dwc_regs_base + GINTSTS, gintsts_handled.d32); -+ } -+ -+ /* Clear the bits in the saved register that were not handled but were triggered. */ -+ state->gintmsk_saved.d32 &= ~(gintsts.d32 & ~gintsts_handled.d32); -+ -+ /* We got an interrupt, didn't handle it and want to mask it */ -+ if (~(state->gintmsk_saved.d32)) { -+ state->mphi_int_count++; -+ gintmsk.d32 &= state->gintmsk_saved.d32; -+ FIQ_WRITE(state->dwc_regs_base + GINTMSK, gintmsk.d32); -+ /* Force a clear before another dummy send */ -+ FIQ_WRITE(state->mphi_regs.intstat, (1<<29)); -+ FIQ_WRITE(state->mphi_regs.outdda, (int) state->dummy_send); -+ FIQ_WRITE(state->mphi_regs.outddb, (1<<29)); -+ -+ } -+ state->fiq_done++; -+ mb(); -+ fiq_fsm_spin_unlock(&state->lock); -+} -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h 2015-11-29 09:42:39.919098694 +0100 -@@ -0,0 +1,370 @@ -+/* -+ * dwc_otg_fiq_fsm.h - Finite state machine FIQ header definitions -+ * -+ * Copyright (c) 2013 Raspberry Pi Foundation -+ * -+ * Author: Jonathan Bell -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Raspberry Pi nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ * -+ * This FIQ implements functionality that performs split transactions on -+ * the dwc_otg hardware without any outside intervention. A split transaction -+ * is "queued" by nominating a specific host channel to perform the entirety -+ * of a split transaction. This FIQ will then perform the microframe-precise -+ * scheduling required in each phase of the transaction until completion. -+ * -+ * The FIQ functionality has been surgically implanted into the Synopsys -+ * vendor-provided driver. -+ * -+ */ -+ -+#ifndef DWC_OTG_FIQ_FSM_H_ -+#define DWC_OTG_FIQ_FSM_H_ -+ -+#include "dwc_otg_regs.h" -+#include "dwc_otg_cil.h" -+#include "dwc_otg_hcd.h" -+#include -+#include -+#include -+#include -+ -+#if 0 -+#define FLAME_ON(x) \ -+do { \ -+ int gpioreg; \ -+ \ -+ gpioreg = readl(__io_address(0x20200000+0x8)); \ -+ gpioreg &= ~(7 << (x-20)*3); \ -+ gpioreg |= 0x1 << (x-20)*3; \ -+ writel(gpioreg, __io_address(0x20200000+0x8)); \ -+ \ -+ writel(1< 1, SOF wakes up the isochronous FSM */ -+ FIQ_HS_ISOC_SLEEPING = 24, -+ FIQ_HS_ISOC_DONE = 25, -+ FIQ_HS_ISOC_ABORTED = 26, -+ FIQ_DEQUEUE_ISSUED = 30, -+ FIQ_TEST = 32, -+}; -+ -+struct fiq_stack { -+ int magic1; -+ uint8_t stack[2048]; -+ int magic2; -+}; -+ -+ -+/** -+ * struct fiq_dma_info - DMA bounce buffer utilisation information (per-channel) -+ * @index: Number of slots reported used for IN transactions / number of slots -+ * transmitted for an OUT transaction -+ * @slot_len[6]: Number of actual transfer bytes in each slot (255 if unused) -+ * -+ * Split transaction transfers can have variable length depending on other bus -+ * traffic. The OTG core DMA engine requires 4-byte aligned addresses therefore -+ * each transaction needs a guaranteed aligned address. A maximum of 6 split transfers -+ * can happen per-frame. -+ */ -+struct fiq_dma_info { -+ u8 index; -+ u8 slot_len[6]; -+}; -+ -+struct __attribute__((packed)) fiq_split_dma_slot { -+ u8 buf[188]; -+}; -+ -+struct fiq_dma_channel { -+ struct __attribute__((packed)) fiq_split_dma_slot index[6]; -+}; -+ -+struct fiq_dma_blob { -+ struct __attribute__((packed)) fiq_dma_channel channel[0]; -+}; -+ -+/** -+ * struct fiq_hs_isoc_info - USB2.0 isochronous data -+ * @iso_frame: Pointer to the array of OTG URB iso_frame_descs. -+ * @nrframes: Total length of iso_frame_desc array -+ * @index: Current index (FIQ-maintained) -+ * @stride: Interval in uframes between HS isoc transactions -+ */ -+struct fiq_hs_isoc_info { -+ struct dwc_otg_hcd_iso_packet_desc *iso_desc; -+ unsigned int nrframes; -+ unsigned int index; -+ unsigned int stride; -+}; -+ -+/** -+ * struct fiq_channel_state - FIQ state machine storage -+ * @fsm: Current state of the channel as understood by the FIQ -+ * @nr_errors: Number of transaction errors on this split-transaction -+ * @hub_addr: SSPLIT/CSPLIT destination hub -+ * @port_addr: SSPLIT/CSPLIT destination port - always 1 if single TT hub -+ * @nrpackets: For isoc OUT, the number of split-OUT packets to transmit. For -+ * split-IN, number of CSPLIT data packets that were received. -+ * @hcchar_copy: -+ * @hcsplt_copy: -+ * @hcintmsk_copy: -+ * @hctsiz_copy: Copies of the host channel registers. -+ * For use as scratch, or for returning state. -+ * -+ * The fiq_channel_state is state storage between interrupts for a host channel. The -+ * FSM state is stored here. Members of this structure must only be set up by the -+ * driver prior to enabling the FIQ for this host channel, and not touched until the FIQ -+ * has updated the state to either a COMPLETE state group or ABORT state group. -+ */ -+ -+struct fiq_channel_state { -+ enum fiq_fsm_state fsm; -+ unsigned int nr_errors; -+ unsigned int hub_addr; -+ unsigned int port_addr; -+ /* Hardware bug workaround: sometimes channel halt interrupts are -+ * delayed until the next SOF. Keep track of when we expected to get interrupted. */ -+ unsigned int expected_uframe; -+ /* number of uframes remaining (for interval > 1 HS isoc transfers) before next transfer */ -+ unsigned int uframe_sleeps; -+ /* in/out for communicating number of dma buffers used, or number of ISOC to do */ -+ unsigned int nrpackets; -+ struct fiq_dma_info dma_info; -+ struct fiq_hs_isoc_info hs_isoc_info; -+ /* Copies of HC registers - in/out communication from/to IRQ handler -+ * and for ease of channel setup. A bit of mungeing is performed - for -+ * example the hctsiz.b.maxp is _always_ the max packet size of the endpoint. -+ */ -+ hcchar_data_t hcchar_copy; -+ hcsplt_data_t hcsplt_copy; -+ hcint_data_t hcint_copy; -+ hcintmsk_data_t hcintmsk_copy; -+ hctsiz_data_t hctsiz_copy; -+ hcdma_data_t hcdma_copy; -+}; -+ -+/** -+ * struct fiq_state - top-level FIQ state machine storage -+ * @mphi_regs: virtual address of the MPHI peripheral register file -+ * @dwc_regs_base: virtual address of the base of the DWC core register file -+ * @dma_base: physical address for the base of the DMA bounce buffers -+ * @dummy_send: Scratch area for sending a fake message to the MPHI peripheral -+ * @gintmsk_saved: Top-level mask of interrupts that the FIQ has not handled. -+ * Used for determining which interrupts fired to set off the IRQ handler. -+ * @haintmsk_saved: Mask of interrupts from host channels that the FIQ did not handle internally. -+ * @np_count: Non-periodic transactions in the active queue -+ * @np_sent: Count of non-periodic transactions that have completed -+ * @next_sched_frame: For periodic transactions handled by the driver's SOF-driven queuing mechanism, -+ * this is the next frame on which a SOF interrupt is required. Used to hold off -+ * passing SOF through to the driver until necessary. -+ * @channel[n]: Per-channel FIQ state. Allocated during init depending on the number of host -+ * channels configured into the core logic. -+ * -+ * This is passed as the first argument to the dwc_otg_fiq_fsm top-level FIQ handler from the asm stub. -+ * It contains top-level state information. -+ */ -+struct fiq_state { -+ fiq_lock_t lock; -+ mphi_regs_t mphi_regs; -+ void *dwc_regs_base; -+ dma_addr_t dma_base; -+ struct fiq_dma_blob *fiq_dmab; -+ void *dummy_send; -+ gintmsk_data_t gintmsk_saved; -+ haintmsk_data_t haintmsk_saved; -+ int mphi_int_count; -+ unsigned int fiq_done; -+ unsigned int kick_np_queues; -+ unsigned int next_sched_frame; -+#ifdef FIQ_DEBUG -+ char * buffer; -+ unsigned int bufsiz; -+#endif -+ struct fiq_channel_state channel[0]; -+}; -+ -+extern void fiq_fsm_spin_lock(fiq_lock_t *lock); -+ -+extern void fiq_fsm_spin_unlock(fiq_lock_t *lock); -+ -+extern int fiq_fsm_too_late(struct fiq_state *st, int n); -+ -+extern int fiq_fsm_tt_in_use(struct fiq_state *st, int num_channels, int n); -+ -+extern void dwc_otg_fiq_fsm(struct fiq_state *state, int num_channels); -+ -+extern void dwc_otg_fiq_nop(struct fiq_state *state); -+ -+#endif /* DWC_OTG_FIQ_FSM_H_ */ -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S 2015-11-29 09:42:39.919098694 +0100 -@@ -0,0 +1,80 @@ -+/* -+ * dwc_otg_fiq_fsm.S - assembly stub for the FSM FIQ -+ * -+ * Copyright (c) 2013 Raspberry Pi Foundation -+ * -+ * Author: Jonathan Bell -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Raspberry Pi nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+ -+#include -+#include -+ -+ -+.text -+ -+.global _dwc_otg_fiq_stub_end; -+ -+/** -+ * _dwc_otg_fiq_stub() - entry copied to the FIQ vector page to allow -+ * a C-style function call with arguments from the FIQ banked registers. -+ * r0 = &hcd->fiq_state -+ * r1 = &hcd->num_channels -+ * r2 = &hcd->dma_buffers -+ * Tramples: r0, r1, r2, r4, fp, ip -+ */ -+ -+ENTRY(_dwc_otg_fiq_stub) -+ /* Stash unbanked regs - SP will have been set up for us */ -+ mov ip, sp; -+ stmdb sp!, {r0-r12, lr}; -+#ifdef FIQ_DEBUG -+ // Cycle profiling - read cycle counter at start -+ mrc p15, 0, r5, c15, c12, 1; -+#endif -+ /* r11 = fp, don't trample it */ -+ mov r4, fp; -+ /* set EABI frame size */ -+ sub fp, ip, #512; -+ -+ /* for fiq NOP mode - just need state */ -+ mov r0, r8; -+ /* r9 = num_channels */ -+ mov r1, r9; -+ /* r10 = struct *dma_bufs */ -+// mov r2, r10; -+ -+ /* r4 = &fiq_c_function */ -+ blx r4; -+#ifdef FIQ_DEBUG -+ mrc p15, 0, r4, c15, c12, 1; -+ subs r5, r5, r4; -+ // r5 is now the cycle count time for executing the FIQ. Store it somewhere? -+#endif -+ ldmia sp!, {r0-r12, lr}; -+ subs pc, lr, #4; -+_dwc_otg_fiq_stub_end: -+END(_dwc_otg_fiq_stub) -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd.c ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd.c 2015-11-29 09:42:39.919098694 +0100 -@@ -0,0 +1,4257 @@ -+ -+/* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $ -+ * $Revision: #104 $ -+ * $Date: 2011/10/24 $ -+ * $Change: 1871159 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+#ifndef DWC_DEVICE_ONLY -+ -+/** @file -+ * This file implements HCD Core. All code in this file is portable and doesn't -+ * use any OS specific functions. -+ * Interface provided by HCD Core is defined in -+ * header file. -+ */ -+ -+#include -+#include -+ -+#include "dwc_otg_hcd.h" -+#include "dwc_otg_regs.h" -+#include "dwc_otg_fiq_fsm.h" -+ -+extern bool microframe_schedule; -+extern uint16_t fiq_fsm_mask, nak_holdoff; -+ -+//#define DEBUG_HOST_CHANNELS -+#ifdef DEBUG_HOST_CHANNELS -+static int last_sel_trans_num_per_scheduled = 0; -+static int last_sel_trans_num_nonper_scheduled = 0; -+static int last_sel_trans_num_avail_hc_at_start = 0; -+static int last_sel_trans_num_avail_hc_at_end = 0; -+#endif /* DEBUG_HOST_CHANNELS */ -+ -+ -+dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void) -+{ -+ return DWC_ALLOC(sizeof(dwc_otg_hcd_t)); -+} -+ -+/** -+ * Connection timeout function. An OTG host is required to display a -+ * message if the device does not connect within 10 seconds. -+ */ -+void dwc_otg_hcd_connect_timeout(void *ptr) -+{ -+ DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, ptr); -+ DWC_PRINTF("Connect Timeout\n"); -+ __DWC_ERROR("Device Not Connected/Responding\n"); -+} -+ -+#if defined(DEBUG) -+static void dump_channel_info(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) -+{ -+ if (qh->channel != NULL) { -+ dwc_hc_t *hc = qh->channel; -+ dwc_list_link_t *item; -+ dwc_otg_qh_t *qh_item; -+ int num_channels = hcd->core_if->core_params->host_channels; -+ int i; -+ -+ dwc_otg_hc_regs_t *hc_regs; -+ hcchar_data_t hcchar; -+ hcsplt_data_t hcsplt; -+ hctsiz_data_t hctsiz; -+ uint32_t hcdma; -+ -+ hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num]; -+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); -+ hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt); -+ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz); -+ hcdma = DWC_READ_REG32(&hc_regs->hcdma); -+ -+ DWC_PRINTF(" Assigned to channel %p:\n", hc); -+ DWC_PRINTF(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, -+ hcsplt.d32); -+ DWC_PRINTF(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, -+ hcdma); -+ DWC_PRINTF(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n", -+ hc->dev_addr, hc->ep_num, hc->ep_is_in); -+ DWC_PRINTF(" ep_type: %d\n", hc->ep_type); -+ DWC_PRINTF(" max_packet: %d\n", hc->max_packet); -+ DWC_PRINTF(" data_pid_start: %d\n", hc->data_pid_start); -+ DWC_PRINTF(" xfer_started: %d\n", hc->xfer_started); -+ DWC_PRINTF(" halt_status: %d\n", hc->halt_status); -+ DWC_PRINTF(" xfer_buff: %p\n", hc->xfer_buff); -+ DWC_PRINTF(" xfer_len: %d\n", hc->xfer_len); -+ DWC_PRINTF(" qh: %p\n", hc->qh); -+ DWC_PRINTF(" NP inactive sched:\n"); -+ DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_inactive) { -+ qh_item = -+ DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry); -+ DWC_PRINTF(" %p\n", qh_item); -+ } -+ DWC_PRINTF(" NP active sched:\n"); -+ DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_active) { -+ qh_item = -+ DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry); -+ DWC_PRINTF(" %p\n", qh_item); -+ } -+ DWC_PRINTF(" Channels: \n"); -+ for (i = 0; i < num_channels; i++) { -+ dwc_hc_t *hc = hcd->hc_ptr_array[i]; -+ DWC_PRINTF(" %2d: %p\n", i, hc); -+ } -+ } -+} -+#else -+#define dump_channel_info(hcd, qh) -+#endif /* DEBUG */ -+ -+/** -+ * Work queue function for starting the HCD when A-Cable is connected. -+ * The hcd_start() must be called in a process context. -+ */ -+static void hcd_start_func(void *_vp) -+{ -+ dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) _vp; -+ -+ DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, hcd); -+ if (hcd) { -+ hcd->fops->start(hcd); -+ } -+} -+ -+static void del_xfer_timers(dwc_otg_hcd_t * hcd) -+{ -+#ifdef DEBUG -+ int i; -+ int num_channels = hcd->core_if->core_params->host_channels; -+ for (i = 0; i < num_channels; i++) { -+ DWC_TIMER_CANCEL(hcd->core_if->hc_xfer_timer[i]); -+ } -+#endif -+} -+ -+static void del_timers(dwc_otg_hcd_t * hcd) -+{ -+ del_xfer_timers(hcd); -+ DWC_TIMER_CANCEL(hcd->conn_timer); -+} -+ -+/** -+ * Processes all the URBs in a single list of QHs. Completes them with -+ * -ESHUTDOWN and frees the QTD. -+ */ -+static void kill_urbs_in_qh_list(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list) -+{ -+ dwc_list_link_t *qh_item, *qh_tmp; -+ dwc_otg_qh_t *qh; -+ dwc_otg_qtd_t *qtd, *qtd_tmp; -+ -+ DWC_LIST_FOREACH_SAFE(qh_item, qh_tmp, qh_list) { -+ qh = DWC_LIST_ENTRY(qh_item, dwc_otg_qh_t, qh_list_entry); -+ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, -+ &qh->qtd_list, qtd_list_entry) { -+ qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); -+ if (qtd->urb != NULL) { -+ hcd->fops->complete(hcd, qtd->urb->priv, -+ qtd->urb, -DWC_E_SHUTDOWN); -+ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh); -+ } -+ -+ } -+ if(qh->channel) { -+ /* Using hcchar.chen == 1 is not a reliable test. -+ * It is possible that the channel has already halted -+ * but not yet been through the IRQ handler. -+ */ -+ dwc_otg_hc_halt(hcd->core_if, qh->channel, -+ DWC_OTG_HC_XFER_URB_DEQUEUE); -+ if(microframe_schedule) -+ hcd->available_host_channels++; -+ qh->channel = NULL; -+ } -+ dwc_otg_hcd_qh_remove(hcd, qh); -+ } -+} -+ -+/** -+ * Responds with an error status of ESHUTDOWN to all URBs in the non-periodic -+ * and periodic schedules. The QTD associated with each URB is removed from -+ * the schedule and freed. This function may be called when a disconnect is -+ * detected or when the HCD is being stopped. -+ */ -+static void kill_all_urbs(dwc_otg_hcd_t * hcd) -+{ -+ kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive); -+ kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active); -+ kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive); -+ kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready); -+ kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned); -+ kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued); -+} -+ -+/** -+ * Start the connection timer. An OTG host is required to display a -+ * message if the device does not connect within 10 seconds. The -+ * timer is deleted if a port connect interrupt occurs before the -+ * timer expires. -+ */ -+static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t * hcd) -+{ -+ DWC_TIMER_SCHEDULE(hcd->conn_timer, 10000 /* 10 secs */ ); -+} -+ -+/** -+ * HCD Callback function for disconnect of the HCD. -+ * -+ * @param p void pointer to the struct usb_hcd -+ */ -+static int32_t dwc_otg_hcd_session_start_cb(void *p) -+{ -+ dwc_otg_hcd_t *dwc_otg_hcd; -+ DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p); -+ dwc_otg_hcd = p; -+ dwc_otg_hcd_start_connect_timer(dwc_otg_hcd); -+ return 1; -+} -+ -+/** -+ * HCD Callback function for starting the HCD when A-Cable is -+ * connected. -+ * -+ * @param p void pointer to the struct usb_hcd -+ */ -+static int32_t dwc_otg_hcd_start_cb(void *p) -+{ -+ dwc_otg_hcd_t *dwc_otg_hcd = p; -+ dwc_otg_core_if_t *core_if; -+ hprt0_data_t hprt0; -+ -+ core_if = dwc_otg_hcd->core_if; -+ -+ if (core_if->op_state == B_HOST) { -+ /* -+ * Reset the port. During a HNP mode switch the reset -+ * needs to occur within 1ms and have a duration of at -+ * least 50ms. -+ */ -+ hprt0.d32 = dwc_otg_read_hprt0(core_if); -+ hprt0.b.prtrst = 1; -+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); -+ } -+ DWC_WORKQ_SCHEDULE_DELAYED(core_if->wq_otg, -+ hcd_start_func, dwc_otg_hcd, 50, -+ "start hcd"); -+ -+ return 1; -+} -+ -+/** -+ * HCD Callback function for disconnect of the HCD. -+ * -+ * @param p void pointer to the struct usb_hcd -+ */ -+static int32_t dwc_otg_hcd_disconnect_cb(void *p) -+{ -+ gintsts_data_t intr; -+ dwc_otg_hcd_t *dwc_otg_hcd = p; -+ -+ /* -+ * Set status flags for the hub driver. -+ */ -+ dwc_otg_hcd->flags.b.port_connect_status_change = 1; -+ dwc_otg_hcd->flags.b.port_connect_status = 0; -+ if(fiq_enable) -+ local_fiq_disable(); -+ /* -+ * Shutdown any transfers in process by clearing the Tx FIFO Empty -+ * interrupt mask and status bits and disabling subsequent host -+ * channel interrupts. -+ */ -+ intr.d32 = 0; -+ intr.b.nptxfempty = 1; -+ intr.b.ptxfempty = 1; -+ intr.b.hcintr = 1; -+ DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, -+ intr.d32, 0); -+ DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintsts, -+ intr.d32, 0); -+ -+ del_timers(dwc_otg_hcd); -+ -+ /* -+ * Turn off the vbus power only if the core has transitioned to device -+ * mode. If still in host mode, need to keep power on to detect a -+ * reconnection. -+ */ -+ if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) { -+ if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) { -+ hprt0_data_t hprt0 = {.d32 = 0 }; -+ DWC_PRINTF("Disconnect: PortPower off\n"); -+ hprt0.b.prtpwr = 0; -+ DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, -+ hprt0.d32); -+ } -+ -+ dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if); -+ } -+ -+ /* Respond with an error status to all URBs in the schedule. */ -+ kill_all_urbs(dwc_otg_hcd); -+ -+ if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) { -+ /* Clean up any host channels that were in use. */ -+ int num_channels; -+ int i; -+ dwc_hc_t *channel; -+ dwc_otg_hc_regs_t *hc_regs; -+ hcchar_data_t hcchar; -+ -+ num_channels = dwc_otg_hcd->core_if->core_params->host_channels; -+ -+ if (!dwc_otg_hcd->core_if->dma_enable) { -+ /* Flush out any channel requests in slave mode. */ -+ for (i = 0; i < num_channels; i++) { -+ channel = dwc_otg_hcd->hc_ptr_array[i]; -+ if (DWC_CIRCLEQ_EMPTY_ENTRY -+ (channel, hc_list_entry)) { -+ hc_regs = -+ dwc_otg_hcd->core_if-> -+ host_if->hc_regs[i]; -+ hcchar.d32 = -+ DWC_READ_REG32(&hc_regs->hcchar); -+ if (hcchar.b.chen) { -+ hcchar.b.chen = 0; -+ hcchar.b.chdis = 1; -+ hcchar.b.epdir = 0; -+ DWC_WRITE_REG32 -+ (&hc_regs->hcchar, -+ hcchar.d32); -+ } -+ } -+ } -+ } -+ -+ for (i = 0; i < num_channels; i++) { -+ channel = dwc_otg_hcd->hc_ptr_array[i]; -+ if (DWC_CIRCLEQ_EMPTY_ENTRY(channel, hc_list_entry)) { -+ hc_regs = -+ dwc_otg_hcd->core_if->host_if->hc_regs[i]; -+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); -+ if (hcchar.b.chen) { -+ /* Halt the channel. */ -+ hcchar.b.chdis = 1; -+ DWC_WRITE_REG32(&hc_regs->hcchar, -+ hcchar.d32); -+ } -+ -+ dwc_otg_hc_cleanup(dwc_otg_hcd->core_if, -+ channel); -+ DWC_CIRCLEQ_INSERT_TAIL -+ (&dwc_otg_hcd->free_hc_list, channel, -+ hc_list_entry); -+ /* -+ * Added for Descriptor DMA to prevent channel double cleanup -+ * in release_channel_ddma(). Which called from ep_disable -+ * when device disconnect. -+ */ -+ channel->qh = NULL; -+ } -+ } -+ if(fiq_fsm_enable) { -+ for(i=0; i < 128; i++) { -+ dwc_otg_hcd->hub_port[i] = 0; -+ } -+ } -+ -+ } -+ -+ if(fiq_enable) -+ local_fiq_enable(); -+ -+ if (dwc_otg_hcd->fops->disconnect) { -+ dwc_otg_hcd->fops->disconnect(dwc_otg_hcd); -+ } -+ -+ return 1; -+} -+ -+/** -+ * HCD Callback function for stopping the HCD. -+ * -+ * @param p void pointer to the struct usb_hcd -+ */ -+static int32_t dwc_otg_hcd_stop_cb(void *p) -+{ -+ dwc_otg_hcd_t *dwc_otg_hcd = p; -+ -+ DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p); -+ dwc_otg_hcd_stop(dwc_otg_hcd); -+ return 1; -+} -+ -+#ifdef CONFIG_USB_DWC_OTG_LPM -+/** -+ * HCD Callback function for sleep of HCD. -+ * -+ * @param p void pointer to the struct usb_hcd -+ */ -+static int dwc_otg_hcd_sleep_cb(void *p) -+{ -+ dwc_otg_hcd_t *hcd = p; -+ -+ dwc_otg_hcd_free_hc_from_lpm(hcd); -+ -+ return 0; -+} -+#endif -+ -+ -+/** -+ * HCD Callback function for Remote Wakeup. -+ * -+ * @param p void pointer to the struct usb_hcd -+ */ -+static int dwc_otg_hcd_rem_wakeup_cb(void *p) -+{ -+ dwc_otg_hcd_t *hcd = p; -+ -+ if (hcd->core_if->lx_state == DWC_OTG_L2) { -+ hcd->flags.b.port_suspend_change = 1; -+ } -+#ifdef CONFIG_USB_DWC_OTG_LPM -+ else { -+ hcd->flags.b.port_l1_change = 1; -+ } -+#endif -+ return 0; -+} -+ -+/** -+ * Halts the DWC_otg host mode operations in a clean manner. USB transfers are -+ * stopped. -+ */ -+void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd) -+{ -+ hprt0_data_t hprt0 = {.d32 = 0 }; -+ -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n"); -+ -+ /* -+ * The root hub should be disconnected before this function is called. -+ * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) -+ * and the QH lists (via ..._hcd_endpoint_disable). -+ */ -+ -+ /* Turn off all host-specific interrupts. */ -+ dwc_otg_disable_host_interrupts(hcd->core_if); -+ -+ /* Turn off the vbus power */ -+ DWC_PRINTF("PortPower off\n"); -+ hprt0.b.prtpwr = 0; -+ DWC_WRITE_REG32(hcd->core_if->host_if->hprt0, hprt0.d32); -+ dwc_mdelay(1); -+} -+ -+int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * hcd, -+ dwc_otg_hcd_urb_t * dwc_otg_urb, void **ep_handle, -+ int atomic_alloc) -+{ -+ int retval = 0; -+ uint8_t needs_scheduling = 0; -+ dwc_otg_transaction_type_e tr_type; -+ dwc_otg_qtd_t *qtd; -+ gintmsk_data_t intr_mask = {.d32 = 0 }; -+ hprt0_data_t hprt0 = { .d32 = 0 }; -+ -+#ifdef DEBUG /* integrity checks (Broadcom) */ -+ if (NULL == hcd->core_if) { -+ DWC_ERROR("**** DWC OTG HCD URB Enqueue - HCD has NULL core_if\n"); -+ /* No longer connected. */ -+ return -DWC_E_INVALID; -+ } -+#endif -+ if (!hcd->flags.b.port_connect_status) { -+ /* No longer connected. */ -+ DWC_ERROR("Not connected\n"); -+ return -DWC_E_NO_DEVICE; -+ } -+ -+ /* Some core configurations cannot support LS traffic on a FS root port */ -+ if ((hcd->fops->speed(hcd, dwc_otg_urb->priv) == USB_SPEED_LOW) && -+ (hcd->core_if->hwcfg2.b.fs_phy_type == 1) && -+ (hcd->core_if->hwcfg2.b.hs_phy_type == 1)) { -+ hprt0.d32 = DWC_READ_REG32(hcd->core_if->host_if->hprt0); -+ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_FULL_SPEED) { -+ return -DWC_E_NO_DEVICE; -+ } -+ } -+ -+ qtd = dwc_otg_hcd_qtd_create(dwc_otg_urb, atomic_alloc); -+ if (qtd == NULL) { -+ DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n"); -+ return -DWC_E_NO_MEMORY; -+ } -+#ifdef DEBUG /* integrity checks (Broadcom) */ -+ if (qtd->urb == NULL) { -+ DWC_ERROR("**** DWC OTG HCD URB Enqueue created QTD with no URBs\n"); -+ return -DWC_E_NO_MEMORY; -+ } -+ if (qtd->urb->priv == NULL) { -+ DWC_ERROR("**** DWC OTG HCD URB Enqueue created QTD URB with no URB handle\n"); -+ return -DWC_E_NO_MEMORY; -+ } -+#endif -+ intr_mask.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->gintmsk); -+ if(!intr_mask.b.sofintr || fiq_enable) needs_scheduling = 1; -+ if((((dwc_otg_qh_t *)ep_handle)->ep_type == UE_BULK) && !(qtd->urb->flags & URB_GIVEBACK_ASAP)) -+ /* Do not schedule SG transactions until qtd has URB_GIVEBACK_ASAP set */ -+ needs_scheduling = 0; -+ -+ retval = dwc_otg_hcd_qtd_add(qtd, hcd, (dwc_otg_qh_t **) ep_handle, atomic_alloc); -+ // creates a new queue in ep_handle if it doesn't exist already -+ if (retval < 0) { -+ DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. " -+ "Error status %d\n", retval); -+ dwc_otg_hcd_qtd_free(qtd); -+ return retval; -+ } -+ -+ if(needs_scheduling) { -+ tr_type = dwc_otg_hcd_select_transactions(hcd); -+ if (tr_type != DWC_OTG_TRANSACTION_NONE) { -+ dwc_otg_hcd_queue_transactions(hcd, tr_type); -+ } -+ } -+ return retval; -+} -+ -+int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * hcd, -+ dwc_otg_hcd_urb_t * dwc_otg_urb) -+{ -+ dwc_otg_qh_t *qh; -+ dwc_otg_qtd_t *urb_qtd; -+ BUG_ON(!hcd); -+ BUG_ON(!dwc_otg_urb); -+ -+#ifdef DEBUG /* integrity checks (Broadcom) */ -+ -+ if (hcd == NULL) { -+ DWC_ERROR("**** DWC OTG HCD URB Dequeue has NULL HCD\n"); -+ return -DWC_E_INVALID; -+ } -+ if (dwc_otg_urb == NULL) { -+ DWC_ERROR("**** DWC OTG HCD URB Dequeue has NULL URB\n"); -+ return -DWC_E_INVALID; -+ } -+ if (dwc_otg_urb->qtd == NULL) { -+ DWC_ERROR("**** DWC OTG HCD URB Dequeue with NULL QTD\n"); -+ return -DWC_E_INVALID; -+ } -+ urb_qtd = dwc_otg_urb->qtd; -+ BUG_ON(!urb_qtd); -+ if (urb_qtd->qh == NULL) { -+ DWC_ERROR("**** DWC OTG HCD URB Dequeue with QTD with NULL Q handler\n"); -+ return -DWC_E_INVALID; -+ } -+#else -+ urb_qtd = dwc_otg_urb->qtd; -+ BUG_ON(!urb_qtd); -+#endif -+ qh = urb_qtd->qh; -+ BUG_ON(!qh); -+ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { -+ if (urb_qtd->in_process) { -+ dump_channel_info(hcd, qh); -+ } -+ } -+#ifdef DEBUG /* integrity checks (Broadcom) */ -+ if (hcd->core_if == NULL) { -+ DWC_ERROR("**** DWC OTG HCD URB Dequeue HCD has NULL core_if\n"); -+ return -DWC_E_INVALID; -+ } -+#endif -+ if (urb_qtd->in_process && qh->channel) { -+ /* The QTD is in process (it has been assigned to a channel). */ -+ if (hcd->flags.b.port_connect_status) { -+ int n = qh->channel->hc_num; -+ /* -+ * If still connected (i.e. in host mode), halt the -+ * channel so it can be used for other transfers. If -+ * no longer connected, the host registers can't be -+ * written to halt the channel since the core is in -+ * device mode. -+ */ -+ /* In FIQ FSM mode, we need to shut down carefully. -+ * The FIQ may attempt to restart a disabled channel */ -+ if (fiq_fsm_enable && (hcd->fiq_state->channel[n].fsm != FIQ_PASSTHROUGH)) { -+ qh->channel->halt_status = DWC_OTG_HC_XFER_URB_DEQUEUE; -+ qh->channel->halt_pending = 1; -+ hcd->fiq_state->channel[n].fsm = FIQ_DEQUEUE_ISSUED; -+ } else { -+ dwc_otg_hc_halt(hcd->core_if, qh->channel, -+ DWC_OTG_HC_XFER_URB_DEQUEUE); -+ } -+ } -+ } -+ -+ /* -+ * Free the QTD and clean up the associated QH. Leave the QH in the -+ * schedule if it has any remaining QTDs. -+ */ -+ -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue - " -+ "delete %sQueue handler\n", -+ hcd->core_if->dma_desc_enable?"DMA ":""); -+ if (!hcd->core_if->dma_desc_enable) { -+ uint8_t b = urb_qtd->in_process; -+ dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh); -+ if (b) { -+ dwc_otg_hcd_qh_deactivate(hcd, qh, 0); -+ qh->channel = NULL; -+ } else if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) { -+ dwc_otg_hcd_qh_remove(hcd, qh); -+ } -+ } else { -+ dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh); -+ } -+ return 0; -+} -+ -+int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle, -+ int retry) -+{ -+ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle; -+ int retval = 0; -+ dwc_irqflags_t flags; -+ -+ if (retry < 0) { -+ retval = -DWC_E_INVALID; -+ goto done; -+ } -+ -+ if (!qh) { -+ retval = -DWC_E_INVALID; -+ goto done; -+ } -+ -+ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); -+ -+ while (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list) && retry) { -+ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); -+ retry--; -+ dwc_msleep(5); -+ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); -+ } -+ -+ dwc_otg_hcd_qh_remove(hcd, qh); -+ -+ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); -+ /* -+ * Split dwc_otg_hcd_qh_remove_and_free() into qh_remove -+ * and qh_free to prevent stack dump on DWC_DMA_FREE() with -+ * irq_disabled (spinlock_irqsave) in dwc_otg_hcd_desc_list_free() -+ * and dwc_otg_hcd_frame_list_alloc(). -+ */ -+ dwc_otg_hcd_qh_free(hcd, qh); -+ -+done: -+ return retval; -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30) -+int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle) -+{ -+ int retval = 0; -+ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle; -+ if (!qh) -+ return -DWC_E_INVALID; -+ -+ qh->data_toggle = DWC_OTG_HC_PID_DATA0; -+ return retval; -+} -+#endif -+ -+/** -+ * HCD Callback structure for handling mode switching. -+ */ -+static dwc_otg_cil_callbacks_t hcd_cil_callbacks = { -+ .start = dwc_otg_hcd_start_cb, -+ .stop = dwc_otg_hcd_stop_cb, -+ .disconnect = dwc_otg_hcd_disconnect_cb, -+ .session_start = dwc_otg_hcd_session_start_cb, -+ .resume_wakeup = dwc_otg_hcd_rem_wakeup_cb, -+#ifdef CONFIG_USB_DWC_OTG_LPM -+ .sleep = dwc_otg_hcd_sleep_cb, -+#endif -+ .p = 0, -+}; -+ -+/** -+ * Reset tasklet function -+ */ -+static void reset_tasklet_func(void *data) -+{ -+ dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *) data; -+ dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; -+ hprt0_data_t hprt0; -+ -+ DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n"); -+ -+ hprt0.d32 = dwc_otg_read_hprt0(core_if); -+ hprt0.b.prtrst = 1; -+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); -+ dwc_mdelay(60); -+ -+ hprt0.b.prtrst = 0; -+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); -+ dwc_otg_hcd->flags.b.port_reset_change = 1; -+} -+ -+static void completion_tasklet_func(void *ptr) -+{ -+ dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) ptr; -+ struct urb *urb; -+ urb_tq_entry_t *item; -+ dwc_irqflags_t flags; -+ -+ /* This could just be spin_lock_irq */ -+ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); -+ while (!DWC_TAILQ_EMPTY(&hcd->completed_urb_list)) { -+ item = DWC_TAILQ_FIRST(&hcd->completed_urb_list); -+ urb = item->urb; -+ DWC_TAILQ_REMOVE(&hcd->completed_urb_list, item, -+ urb_tq_entries); -+ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); -+ DWC_FREE(item); -+ -+ usb_hcd_giveback_urb(hcd->priv, urb, urb->status); -+ -+ -+ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); -+ } -+ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); -+ return; -+} -+ -+static void qh_list_free(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list) -+{ -+ dwc_list_link_t *item; -+ dwc_otg_qh_t *qh; -+ dwc_irqflags_t flags; -+ -+ if (!qh_list->next) { -+ /* The list hasn't been initialized yet. */ -+ return; -+ } -+ /* -+ * Hold spinlock here. Not needed in that case if bellow -+ * function is being called from ISR -+ */ -+ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); -+ /* Ensure there are no QTDs or URBs left. */ -+ kill_urbs_in_qh_list(hcd, qh_list); -+ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); -+ -+ DWC_LIST_FOREACH(item, qh_list) { -+ qh = DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry); -+ dwc_otg_hcd_qh_remove_and_free(hcd, qh); -+ } -+} -+ -+/** -+ * Exit from Hibernation if Host did not detect SRP from connected SRP capable -+ * Device during SRP time by host power up. -+ */ -+void dwc_otg_hcd_power_up(void *ptr) -+{ -+ gpwrdn_data_t gpwrdn = {.d32 = 0 }; -+ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr; -+ -+ DWC_PRINTF("%s called\n", __FUNCTION__); -+ -+ if (!core_if->hibernation_suspend) { -+ DWC_PRINTF("Already exited from Hibernation\n"); -+ return; -+ } -+ -+ /* Switch on the voltage to the core */ -+ gpwrdn.b.pwrdnswtch = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ dwc_udelay(10); -+ -+ /* Reset the core */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pwrdnrstn = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ dwc_udelay(10); -+ -+ /* Disable power clamps */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pwrdnclmp = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ -+ /* Remove reset the core signal */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pwrdnrstn = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); -+ dwc_udelay(10); -+ -+ /* Disable PMU interrupt */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pmuintsel = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ -+ core_if->hibernation_suspend = 0; -+ -+ /* Disable PMU */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pmuactv = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ dwc_udelay(10); -+ -+ /* Enable VBUS */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.dis_vbus = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); -+ -+ core_if->op_state = A_HOST; -+ dwc_otg_core_init(core_if); -+ dwc_otg_enable_global_interrupts(core_if); -+ cil_hcd_start(core_if); -+} -+ -+void dwc_otg_cleanup_fiq_channel(dwc_otg_hcd_t *hcd, uint32_t num) -+{ -+ struct fiq_channel_state *st = &hcd->fiq_state->channel[num]; -+ struct fiq_dma_blob *blob = hcd->fiq_dmab; -+ int i; -+ -+ st->fsm = FIQ_PASSTHROUGH; -+ st->hcchar_copy.d32 = 0; -+ st->hcsplt_copy.d32 = 0; -+ st->hcint_copy.d32 = 0; -+ st->hcintmsk_copy.d32 = 0; -+ st->hctsiz_copy.d32 = 0; -+ st->hcdma_copy.d32 = 0; -+ st->nr_errors = 0; -+ st->hub_addr = 0; -+ st->port_addr = 0; -+ st->expected_uframe = 0; -+ st->nrpackets = 0; -+ st->dma_info.index = 0; -+ for (i = 0; i < 6; i++) -+ st->dma_info.slot_len[i] = 255; -+ st->hs_isoc_info.index = 0; -+ st->hs_isoc_info.iso_desc = NULL; -+ st->hs_isoc_info.nrframes = 0; -+ -+ DWC_MEMSET(&blob->channel[num].index[0], 0x6b, 1128); -+} -+ -+/** -+ * Frees secondary storage associated with the dwc_otg_hcd structure contained -+ * in the struct usb_hcd field. -+ */ -+static void dwc_otg_hcd_free(dwc_otg_hcd_t * dwc_otg_hcd) -+{ -+ int i; -+ -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n"); -+ -+ del_timers(dwc_otg_hcd); -+ -+ /* Free memory for QH/QTD lists */ -+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive); -+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active); -+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive); -+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready); -+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned); -+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued); -+ -+ /* Free memory for the host channels. */ -+ for (i = 0; i < MAX_EPS_CHANNELS; i++) { -+ dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i]; -+ -+#ifdef DEBUG -+ if (dwc_otg_hcd->core_if->hc_xfer_timer[i]) { -+ DWC_TIMER_FREE(dwc_otg_hcd->core_if->hc_xfer_timer[i]); -+ } -+#endif -+ if (hc != NULL) { -+ DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n", -+ i, hc); -+ DWC_FREE(hc); -+ } -+ } -+ -+ if (dwc_otg_hcd->core_if->dma_enable) { -+ if (dwc_otg_hcd->status_buf_dma) { -+ DWC_DMA_FREE(DWC_OTG_HCD_STATUS_BUF_SIZE, -+ dwc_otg_hcd->status_buf, -+ dwc_otg_hcd->status_buf_dma); -+ } -+ } else if (dwc_otg_hcd->status_buf != NULL) { -+ DWC_FREE(dwc_otg_hcd->status_buf); -+ } -+ DWC_SPINLOCK_FREE(dwc_otg_hcd->channel_lock); -+ DWC_SPINLOCK_FREE(dwc_otg_hcd->lock); -+ /* Set core_if's lock pointer to NULL */ -+ dwc_otg_hcd->core_if->lock = NULL; -+ -+ DWC_TIMER_FREE(dwc_otg_hcd->conn_timer); -+ DWC_TASK_FREE(dwc_otg_hcd->reset_tasklet); -+ DWC_TASK_FREE(dwc_otg_hcd->completion_tasklet); -+ DWC_FREE(dwc_otg_hcd->fiq_state); -+ -+#ifdef DWC_DEV_SRPCAP -+ if (dwc_otg_hcd->core_if->power_down == 2 && -+ dwc_otg_hcd->core_if->pwron_timer) { -+ DWC_TIMER_FREE(dwc_otg_hcd->core_if->pwron_timer); -+ } -+#endif -+ DWC_FREE(dwc_otg_hcd); -+} -+ -+int init_hcd_usecs(dwc_otg_hcd_t *_hcd); -+ -+int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if) -+{ -+ int retval = 0; -+ int num_channels; -+ int i; -+ dwc_hc_t *channel; -+ -+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK)) -+ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(hcd->lock); -+ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(hcd->channel_lock); -+#else -+ hcd->lock = DWC_SPINLOCK_ALLOC(); -+ hcd->channel_lock = DWC_SPINLOCK_ALLOC(); -+#endif -+ DWC_DEBUGPL(DBG_HCDV, "init of HCD %p given core_if %p\n", -+ hcd, core_if); -+ if (!hcd->lock) { -+ DWC_ERROR("Could not allocate lock for pcd"); -+ DWC_FREE(hcd); -+ retval = -DWC_E_NO_MEMORY; -+ goto out; -+ } -+ hcd->core_if = core_if; -+ -+ /* Register the HCD CIL Callbacks */ -+ dwc_otg_cil_register_hcd_callbacks(hcd->core_if, -+ &hcd_cil_callbacks, hcd); -+ -+ /* Initialize the non-periodic schedule. */ -+ DWC_LIST_INIT(&hcd->non_periodic_sched_inactive); -+ DWC_LIST_INIT(&hcd->non_periodic_sched_active); -+ -+ /* Initialize the periodic schedule. */ -+ DWC_LIST_INIT(&hcd->periodic_sched_inactive); -+ DWC_LIST_INIT(&hcd->periodic_sched_ready); -+ DWC_LIST_INIT(&hcd->periodic_sched_assigned); -+ DWC_LIST_INIT(&hcd->periodic_sched_queued); -+ DWC_TAILQ_INIT(&hcd->completed_urb_list); -+ /* -+ * Create a host channel descriptor for each host channel implemented -+ * in the controller. Initialize the channel descriptor array. -+ */ -+ DWC_CIRCLEQ_INIT(&hcd->free_hc_list); -+ num_channels = hcd->core_if->core_params->host_channels; -+ DWC_MEMSET(hcd->hc_ptr_array, 0, sizeof(hcd->hc_ptr_array)); -+ for (i = 0; i < num_channels; i++) { -+ channel = DWC_ALLOC(sizeof(dwc_hc_t)); -+ if (channel == NULL) { -+ retval = -DWC_E_NO_MEMORY; -+ DWC_ERROR("%s: host channel allocation failed\n", -+ __func__); -+ dwc_otg_hcd_free(hcd); -+ goto out; -+ } -+ channel->hc_num = i; -+ hcd->hc_ptr_array[i] = channel; -+#ifdef DEBUG -+ hcd->core_if->hc_xfer_timer[i] = -+ DWC_TIMER_ALLOC("hc timer", hc_xfer_timeout, -+ &hcd->core_if->hc_xfer_info[i]); -+#endif -+ DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, -+ channel); -+ } -+ -+ if (fiq_enable) { -+ hcd->fiq_state = DWC_ALLOC(sizeof(struct fiq_state) + (sizeof(struct fiq_channel_state) * num_channels)); -+ if (!hcd->fiq_state) { -+ retval = -DWC_E_NO_MEMORY; -+ DWC_ERROR("%s: cannot allocate fiq_state structure\n", __func__); -+ dwc_otg_hcd_free(hcd); -+ goto out; -+ } -+ DWC_MEMSET(hcd->fiq_state, 0, (sizeof(struct fiq_state) + (sizeof(struct fiq_channel_state) * num_channels))); -+ -+ for (i = 0; i < num_channels; i++) { -+ hcd->fiq_state->channel[i].fsm = FIQ_PASSTHROUGH; -+ } -+ hcd->fiq_state->dummy_send = DWC_ALLOC_ATOMIC(16); -+ -+ hcd->fiq_stack = DWC_ALLOC(sizeof(struct fiq_stack)); -+ if (!hcd->fiq_stack) { -+ retval = -DWC_E_NO_MEMORY; -+ DWC_ERROR("%s: cannot allocate fiq_stack structure\n", __func__); -+ dwc_otg_hcd_free(hcd); -+ goto out; -+ } -+ hcd->fiq_stack->magic1 = 0xDEADBEEF; -+ hcd->fiq_stack->magic2 = 0xD00DFEED; -+ hcd->fiq_state->gintmsk_saved.d32 = ~0; -+ hcd->fiq_state->haintmsk_saved.b2.chint = ~0; -+ -+ /* This bit is terrible and uses no API, but necessary. The FIQ has no concept of DMA pools -+ * (and if it did, would be a lot slower). This allocates a chunk of memory (~9kiB for 8 host channels) -+ * for use as transaction bounce buffers in a 2-D array. Our access into this chunk is done by some -+ * moderately readable array casts. -+ */ -+ hcd->fiq_dmab = DWC_DMA_ALLOC((sizeof(struct fiq_dma_channel) * num_channels), &hcd->fiq_state->dma_base); -+ DWC_WARN("FIQ DMA bounce buffers: virt = 0x%08x dma = 0x%08x len=%d", -+ (unsigned int)hcd->fiq_dmab, (unsigned int)hcd->fiq_state->dma_base, -+ sizeof(struct fiq_dma_channel) * num_channels); -+ -+ DWC_MEMSET(hcd->fiq_dmab, 0x6b, 9024); -+ -+ /* pointer for debug in fiq_print */ -+ hcd->fiq_state->fiq_dmab = hcd->fiq_dmab; -+ if (fiq_fsm_enable) { -+ int i; -+ for (i=0; i < hcd->core_if->core_params->host_channels; i++) { -+ dwc_otg_cleanup_fiq_channel(hcd, i); -+ } -+ DWC_PRINTF("FIQ FSM acceleration enabled for :\n%s%s%s%s", -+ (fiq_fsm_mask & 0x1) ? "Non-periodic Split Transactions\n" : "", -+ (fiq_fsm_mask & 0x2) ? "Periodic Split Transactions\n" : "", -+ (fiq_fsm_mask & 0x4) ? "High-Speed Isochronous Endpoints\n" : "", -+ (fiq_fsm_mask & 0x8) ? "Interrupt/Control Split Transaction hack enabled\n" : ""); -+ } -+ } -+ -+ /* Initialize the Connection timeout timer. */ -+ hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer", -+ dwc_otg_hcd_connect_timeout, 0); -+ -+ printk(KERN_DEBUG "dwc_otg: Microframe scheduler %s\n", microframe_schedule ? "enabled":"disabled"); -+ if (microframe_schedule) -+ init_hcd_usecs(hcd); -+ -+ /* Initialize reset tasklet. */ -+ hcd->reset_tasklet = DWC_TASK_ALLOC("reset_tasklet", reset_tasklet_func, hcd); -+ -+ hcd->completion_tasklet = DWC_TASK_ALLOC("completion_tasklet", -+ completion_tasklet_func, hcd); -+#ifdef DWC_DEV_SRPCAP -+ if (hcd->core_if->power_down == 2) { -+ /* Initialize Power on timer for Host power up in case hibernation */ -+ hcd->core_if->pwron_timer = DWC_TIMER_ALLOC("PWRON TIMER", -+ dwc_otg_hcd_power_up, core_if); -+ } -+#endif -+ -+ /* -+ * Allocate space for storing data on status transactions. Normally no -+ * data is sent, but this space acts as a bit bucket. This must be -+ * done after usb_add_hcd since that function allocates the DMA buffer -+ * pool. -+ */ -+ if (hcd->core_if->dma_enable) { -+ hcd->status_buf = -+ DWC_DMA_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE, -+ &hcd->status_buf_dma); -+ } else { -+ hcd->status_buf = DWC_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE); -+ } -+ if (!hcd->status_buf) { -+ retval = -DWC_E_NO_MEMORY; -+ DWC_ERROR("%s: status_buf allocation failed\n", __func__); -+ dwc_otg_hcd_free(hcd); -+ goto out; -+ } -+ -+ hcd->otg_port = 1; -+ hcd->frame_list = NULL; -+ hcd->frame_list_dma = 0; -+ hcd->periodic_qh_count = 0; -+ -+ DWC_MEMSET(hcd->hub_port, 0, sizeof(hcd->hub_port)); -+#ifdef FIQ_DEBUG -+ DWC_MEMSET(hcd->hub_port_alloc, -1, sizeof(hcd->hub_port_alloc)); -+#endif -+ -+out: -+ return retval; -+} -+ -+void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd) -+{ -+ /* Turn off all host-specific interrupts. */ -+ dwc_otg_disable_host_interrupts(hcd->core_if); -+ -+ dwc_otg_hcd_free(hcd); -+} -+ -+/** -+ * Initializes dynamic portions of the DWC_otg HCD state. -+ */ -+static void dwc_otg_hcd_reinit(dwc_otg_hcd_t * hcd) -+{ -+ int num_channels; -+ int i; -+ dwc_hc_t *channel; -+ dwc_hc_t *channel_tmp; -+ -+ hcd->flags.d32 = 0; -+ -+ hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active; -+ if (!microframe_schedule) { -+ hcd->non_periodic_channels = 0; -+ hcd->periodic_channels = 0; -+ } else { -+ hcd->available_host_channels = hcd->core_if->core_params->host_channels; -+ } -+ /* -+ * Put all channels in the free channel list and clean up channel -+ * states. -+ */ -+ DWC_CIRCLEQ_FOREACH_SAFE(channel, channel_tmp, -+ &hcd->free_hc_list, hc_list_entry) { -+ DWC_CIRCLEQ_REMOVE(&hcd->free_hc_list, channel, hc_list_entry); -+ } -+ -+ num_channels = hcd->core_if->core_params->host_channels; -+ for (i = 0; i < num_channels; i++) { -+ channel = hcd->hc_ptr_array[i]; -+ DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, channel, -+ hc_list_entry); -+ dwc_otg_hc_cleanup(hcd->core_if, channel); -+ } -+ -+ /* Initialize the DWC core for host mode operation. */ -+ dwc_otg_core_host_init(hcd->core_if); -+ -+ /* Set core_if's lock pointer to the hcd->lock */ -+ hcd->core_if->lock = hcd->lock; -+} -+ -+/** -+ * Assigns transactions from a QTD to a free host channel and initializes the -+ * host channel to perform the transactions. The host channel is removed from -+ * the free list. -+ * -+ * @param hcd The HCD state structure. -+ * @param qh Transactions from the first QTD for this QH are selected and -+ * assigned to a free host channel. -+ */ -+static void assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) -+{ -+ dwc_hc_t *hc; -+ dwc_otg_qtd_t *qtd; -+ dwc_otg_hcd_urb_t *urb; -+ void* ptr = NULL; -+ uint32_t intr_enable; -+ unsigned long flags; -+ gintmsk_data_t gintmsk = { .d32 = 0, }; -+ -+ qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); -+ -+ urb = qtd->urb; -+ -+ DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p) - urb %x, actual_length %d\n", __func__, hcd, qh, (unsigned int)urb, urb->actual_length); -+ -+ if (((urb->actual_length < 0) || (urb->actual_length > urb->length)) && !dwc_otg_hcd_is_pipe_in(&urb->pipe_info)) -+ urb->actual_length = urb->length; -+ -+ -+ hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list); -+ -+ /* Remove the host channel from the free list. */ -+ DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry); -+ -+ qh->channel = hc; -+ -+ qtd->in_process = 1; -+ -+ /* -+ * Use usb_pipedevice to determine device address. This address is -+ * 0 before the SET_ADDRESS command and the correct address afterward. -+ */ -+ hc->dev_addr = dwc_otg_hcd_get_dev_addr(&urb->pipe_info); -+ hc->ep_num = dwc_otg_hcd_get_ep_num(&urb->pipe_info); -+ hc->speed = qh->dev_speed; -+ hc->max_packet = dwc_max_packet(qh->maxp); -+ -+ hc->xfer_started = 0; -+ hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS; -+ hc->error_state = (qtd->error_count > 0); -+ hc->halt_on_queue = 0; -+ hc->halt_pending = 0; -+ hc->requests = 0; -+ -+ /* -+ * The following values may be modified in the transfer type section -+ * below. The xfer_len value may be reduced when the transfer is -+ * started to accommodate the max widths of the XferSize and PktCnt -+ * fields in the HCTSIZn register. -+ */ -+ -+ hc->ep_is_in = (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) != 0); -+ if (hc->ep_is_in) { -+ hc->do_ping = 0; -+ } else { -+ hc->do_ping = qh->ping_state; -+ } -+ -+ hc->data_pid_start = qh->data_toggle; -+ hc->multi_count = 1; -+ -+ if (hcd->core_if->dma_enable) { -+ hc->xfer_buff = (uint8_t *) urb->dma + urb->actual_length; -+ -+ /* For non-dword aligned case */ -+ if (((unsigned long)hc->xfer_buff & 0x3) -+ && !hcd->core_if->dma_desc_enable) { -+ ptr = (uint8_t *) urb->buf + urb->actual_length; -+ } -+ } else { -+ hc->xfer_buff = (uint8_t *) urb->buf + urb->actual_length; -+ } -+ hc->xfer_len = urb->length - urb->actual_length; -+ hc->xfer_count = 0; -+ -+ /* -+ * Set the split attributes -+ */ -+ hc->do_split = 0; -+ if (qh->do_split) { -+ uint32_t hub_addr, port_addr; -+ hc->do_split = 1; -+ hc->xact_pos = qtd->isoc_split_pos; -+ /* We don't need to do complete splits anymore */ -+// if(fiq_fsm_enable) -+ if (0) -+ hc->complete_split = qtd->complete_split = 0; -+ else -+ hc->complete_split = qtd->complete_split; -+ -+ hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &port_addr); -+ hc->hub_addr = (uint8_t) hub_addr; -+ hc->port_addr = (uint8_t) port_addr; -+ } -+ -+ switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) { -+ case UE_CONTROL: -+ hc->ep_type = DWC_OTG_EP_TYPE_CONTROL; -+ switch (qtd->control_phase) { -+ case DWC_OTG_CONTROL_SETUP: -+ DWC_DEBUGPL(DBG_HCDV, " Control setup transaction\n"); -+ hc->do_ping = 0; -+ hc->ep_is_in = 0; -+ hc->data_pid_start = DWC_OTG_HC_PID_SETUP; -+ if (hcd->core_if->dma_enable) { -+ hc->xfer_buff = (uint8_t *) urb->setup_dma; -+ } else { -+ hc->xfer_buff = (uint8_t *) urb->setup_packet; -+ } -+ hc->xfer_len = 8; -+ ptr = NULL; -+ break; -+ case DWC_OTG_CONTROL_DATA: -+ DWC_DEBUGPL(DBG_HCDV, " Control data transaction\n"); -+ hc->data_pid_start = qtd->data_toggle; -+ break; -+ case DWC_OTG_CONTROL_STATUS: -+ /* -+ * Direction is opposite of data direction or IN if no -+ * data. -+ */ -+ DWC_DEBUGPL(DBG_HCDV, " Control status transaction\n"); -+ if (urb->length == 0) { -+ hc->ep_is_in = 1; -+ } else { -+ hc->ep_is_in = -+ dwc_otg_hcd_is_pipe_out(&urb->pipe_info); -+ } -+ if (hc->ep_is_in) { -+ hc->do_ping = 0; -+ } -+ -+ hc->data_pid_start = DWC_OTG_HC_PID_DATA1; -+ -+ hc->xfer_len = 0; -+ if (hcd->core_if->dma_enable) { -+ hc->xfer_buff = (uint8_t *) hcd->status_buf_dma; -+ } else { -+ hc->xfer_buff = (uint8_t *) hcd->status_buf; -+ } -+ ptr = NULL; -+ break; -+ } -+ break; -+ case UE_BULK: -+ hc->ep_type = DWC_OTG_EP_TYPE_BULK; -+ break; -+ case UE_INTERRUPT: -+ hc->ep_type = DWC_OTG_EP_TYPE_INTR; -+ break; -+ case UE_ISOCHRONOUS: -+ { -+ struct dwc_otg_hcd_iso_packet_desc *frame_desc; -+ -+ hc->ep_type = DWC_OTG_EP_TYPE_ISOC; -+ -+ if (hcd->core_if->dma_desc_enable) -+ break; -+ -+ frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; -+ -+ frame_desc->status = 0; -+ -+ if (hcd->core_if->dma_enable) { -+ hc->xfer_buff = (uint8_t *) urb->dma; -+ } else { -+ hc->xfer_buff = (uint8_t *) urb->buf; -+ } -+ hc->xfer_buff += -+ frame_desc->offset + qtd->isoc_split_offset; -+ hc->xfer_len = -+ frame_desc->length - qtd->isoc_split_offset; -+ -+ /* For non-dword aligned buffers */ -+ if (((unsigned long)hc->xfer_buff & 0x3) -+ && hcd->core_if->dma_enable) { -+ ptr = -+ (uint8_t *) urb->buf + frame_desc->offset + -+ qtd->isoc_split_offset; -+ } else -+ ptr = NULL; -+ -+ if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) { -+ if (hc->xfer_len <= 188) { -+ hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL; -+ } else { -+ hc->xact_pos = -+ DWC_HCSPLIT_XACTPOS_BEGIN; -+ } -+ } -+ } -+ break; -+ } -+ /* non DWORD-aligned buffer case */ -+ if (ptr) { -+ uint32_t buf_size; -+ if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) { -+ buf_size = hcd->core_if->core_params->max_transfer_size; -+ } else { -+ buf_size = 4096; -+ } -+ if (!qh->dw_align_buf) { -+ qh->dw_align_buf = DWC_DMA_ALLOC_ATOMIC(buf_size, -+ &qh->dw_align_buf_dma); -+ if (!qh->dw_align_buf) { -+ DWC_ERROR -+ ("%s: Failed to allocate memory to handle " -+ "non-dword aligned buffer case\n", -+ __func__); -+ return; -+ } -+ } -+ if (!hc->ep_is_in) { -+ dwc_memcpy(qh->dw_align_buf, ptr, hc->xfer_len); -+ } -+ hc->align_buff = qh->dw_align_buf_dma; -+ } else { -+ hc->align_buff = 0; -+ } -+ -+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || -+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { -+ /* -+ * This value may be modified when the transfer is started to -+ * reflect the actual transfer length. -+ */ -+ hc->multi_count = dwc_hb_mult(qh->maxp); -+ } -+ -+ if (hcd->core_if->dma_desc_enable) -+ hc->desc_list_addr = qh->desc_list_dma; -+ -+ dwc_otg_hc_init(hcd->core_if, hc); -+ -+ local_irq_save(flags); -+ -+ if (fiq_enable) { -+ local_fiq_disable(); -+ fiq_fsm_spin_lock(&hcd->fiq_state->lock); -+ } -+ -+ /* Enable the top level host channel interrupt. */ -+ intr_enable = (1 << hc->hc_num); -+ DWC_MODIFY_REG32(&hcd->core_if->host_if->host_global_regs->haintmsk, 0, intr_enable); -+ -+ /* Make sure host channel interrupts are enabled. */ -+ gintmsk.b.hcintr = 1; -+ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32); -+ -+ if (fiq_enable) { -+ fiq_fsm_spin_unlock(&hcd->fiq_state->lock); -+ local_fiq_enable(); -+ } -+ -+ local_irq_restore(flags); -+ hc->qh = qh; -+} -+ -+ -+/** -+ * fiq_fsm_transaction_suitable() - Test a QH for compatibility with the FIQ -+ * @qh: pointer to the endpoint's queue head -+ * -+ * Transaction start/end control flow is grafted onto the existing dwc_otg -+ * mechanisms, to avoid spaghettifying the functions more than they already are. -+ * This function's eligibility check is altered by debug parameter. -+ * -+ * Returns: 0 for unsuitable, 1 implies the FIQ can be enabled for this transaction. -+ */ -+ -+int fiq_fsm_transaction_suitable(dwc_otg_qh_t *qh) -+{ -+ if (qh->do_split) { -+ switch (qh->ep_type) { -+ case UE_CONTROL: -+ case UE_BULK: -+ if (fiq_fsm_mask & (1 << 0)) -+ return 1; -+ break; -+ case UE_INTERRUPT: -+ case UE_ISOCHRONOUS: -+ if (fiq_fsm_mask & (1 << 1)) -+ return 1; -+ break; -+ default: -+ break; -+ } -+ } else if (qh->ep_type == UE_ISOCHRONOUS) { -+ if (fiq_fsm_mask & (1 << 2)) { -+ /* HS ISOCH support. We test for compatibility: -+ * - DWORD aligned buffers -+ * - Must be at least 2 transfers (otherwise pointless to use the FIQ) -+ * If yes, then the fsm enqueue function will handle the state machine setup. -+ */ -+ dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); -+ dwc_otg_hcd_urb_t *urb = qtd->urb; -+ struct dwc_otg_hcd_iso_packet_desc (*iso_descs)[0] = &urb->iso_descs; -+ int nr_iso_frames = urb->packet_count; -+ int i; -+ uint32_t ptr; -+ -+ if (nr_iso_frames < 2) -+ return 0; -+ for (i = 0; i < nr_iso_frames; i++) { -+ ptr = urb->dma + iso_descs[i]->offset; -+ if (ptr & 0x3) { -+ printk_ratelimited("%s: Non-Dword aligned isochronous frame offset." -+ " Cannot queue FIQ-accelerated transfer to device %d endpoint %d\n", -+ __FUNCTION__, qh->channel->dev_addr, qh->channel->ep_num); -+ return 0; -+ } -+ } -+ return 1; -+ } -+ } -+ return 0; -+} -+ -+/** -+ * fiq_fsm_setup_periodic_dma() - Set up DMA bounce buffers -+ * @hcd: Pointer to the dwc_otg_hcd struct -+ * @qh: Pointer to the endpoint's queue head -+ * -+ * Periodic split transactions are transmitted modulo 188 bytes. -+ * This necessitates slicing data up into buckets for isochronous out -+ * and fixing up the DMA address for all IN transfers. -+ * -+ * Returns 1 if the DMA bounce buffers have been used, 0 if the default -+ * HC buffer has been used. -+ */ -+int fiq_fsm_setup_periodic_dma(dwc_otg_hcd_t *hcd, struct fiq_channel_state *st, dwc_otg_qh_t *qh) -+ { -+ int frame_length, i = 0; -+ uint8_t *ptr = NULL; -+ dwc_hc_t *hc = qh->channel; -+ struct fiq_dma_blob *blob; -+ struct dwc_otg_hcd_iso_packet_desc *frame_desc; -+ -+ for (i = 0; i < 6; i++) { -+ st->dma_info.slot_len[i] = 255; -+ } -+ st->dma_info.index = 0; -+ i = 0; -+ if (hc->ep_is_in) { -+ /* -+ * Set dma_regs to bounce buffer. FIQ will update the -+ * state depending on transaction progress. -+ */ -+ blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base; -+ st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0]; -+ /* Calculate the max number of CSPLITS such that the FIQ can time out -+ * a transaction if it fails. -+ */ -+ frame_length = st->hcchar_copy.b.mps; -+ do { -+ i++; -+ frame_length -= 188; -+ } while (frame_length >= 0); -+ st->nrpackets = i; -+ return 1; -+ } else { -+ if (qh->ep_type == UE_ISOCHRONOUS) { -+ -+ dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); -+ -+ frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; -+ frame_length = frame_desc->length; -+ -+ /* Virtual address for bounce buffers */ -+ blob = hcd->fiq_dmab; -+ -+ ptr = qtd->urb->buf + frame_desc->offset; -+ if (frame_length == 0) { -+ /* -+ * for isochronous transactions, we must still transmit a packet -+ * even if the length is zero. -+ */ -+ st->dma_info.slot_len[0] = 0; -+ st->nrpackets = 1; -+ } else { -+ do { -+ if (frame_length <= 188) { -+ dwc_memcpy(&blob->channel[hc->hc_num].index[i].buf[0], ptr, frame_length); -+ st->dma_info.slot_len[i] = frame_length; -+ ptr += frame_length; -+ } else { -+ dwc_memcpy(&blob->channel[hc->hc_num].index[i].buf[0], ptr, 188); -+ st->dma_info.slot_len[i] = 188; -+ ptr += 188; -+ } -+ i++; -+ frame_length -= 188; -+ } while (frame_length > 0); -+ st->nrpackets = i; -+ } -+ ptr = qtd->urb->buf + frame_desc->offset; -+ /* Point the HC at the DMA address of the bounce buffers */ -+ blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base; -+ st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0]; -+ -+ /* fixup xfersize to the actual packet size */ -+ st->hctsiz_copy.b.pid = 0; -+ st->hctsiz_copy.b.xfersize = st->dma_info.slot_len[0]; -+ return 1; -+ } else { -+ /* For interrupt, single OUT packet required, goes in the SSPLIT from hc_buff. */ -+ return 0; -+ } -+ } -+} -+ -+/* -+ * Pushing a periodic request into the queue near the EOF1 point -+ * in a microframe causes erroneous behaviour (frmovrun) interrupt. -+ * Usually, the request goes out on the bus causing a transfer but -+ * the core does not transfer the data to memory. -+ * This guard interval (in number of 60MHz clocks) is required which -+ * must cater for CPU latency between reading the value and enabling -+ * the channel. -+ */ -+#define PERIODIC_FRREM_BACKOFF 1000 -+ -+int fiq_fsm_queue_isoc_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) -+{ -+ dwc_hc_t *hc = qh->channel; -+ dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num]; -+ dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); -+ int frame; -+ struct fiq_channel_state *st = &hcd->fiq_state->channel[hc->hc_num]; -+ int xfer_len, nrpackets; -+ hcdma_data_t hcdma; -+ hfnum_data_t hfnum; -+ -+ if (st->fsm != FIQ_PASSTHROUGH) -+ return 0; -+ -+ st->nr_errors = 0; -+ -+ st->hcchar_copy.d32 = 0; -+ st->hcchar_copy.b.mps = hc->max_packet; -+ st->hcchar_copy.b.epdir = hc->ep_is_in; -+ st->hcchar_copy.b.devaddr = hc->dev_addr; -+ st->hcchar_copy.b.epnum = hc->ep_num; -+ st->hcchar_copy.b.eptype = hc->ep_type; -+ -+ st->hcintmsk_copy.b.chhltd = 1; -+ -+ frame = dwc_otg_hcd_get_frame_number(hcd); -+ st->hcchar_copy.b.oddfrm = (frame & 0x1) ? 0 : 1; -+ -+ st->hcchar_copy.b.lspddev = 0; -+ /* Enable the channel later as a final register write. */ -+ -+ st->hcsplt_copy.d32 = 0; -+ -+ st->hs_isoc_info.iso_desc = (struct dwc_otg_hcd_iso_packet_desc *) &qtd->urb->iso_descs; -+ st->hs_isoc_info.nrframes = qtd->urb->packet_count; -+ /* grab the next DMA address offset from the array */ -+ st->hcdma_copy.d32 = qtd->urb->dma; -+ hcdma.d32 = st->hcdma_copy.d32 + st->hs_isoc_info.iso_desc[0].offset; -+ -+ /* We need to set multi_count. This is a bit tricky - has to be set per-transaction as -+ * the core needs to be told to send the correct number. Caution: for IN transfers, -+ * this is always set to the maximum size of the endpoint. */ -+ xfer_len = st->hs_isoc_info.iso_desc[0].length; -+ nrpackets = (xfer_len + st->hcchar_copy.b.mps - 1) / st->hcchar_copy.b.mps; -+ if (nrpackets == 0) -+ nrpackets = 1; -+ st->hcchar_copy.b.multicnt = nrpackets; -+ st->hctsiz_copy.b.pktcnt = nrpackets; -+ -+ /* Initial PID also needs to be set */ -+ if (st->hcchar_copy.b.epdir == 0) { -+ st->hctsiz_copy.b.xfersize = xfer_len; -+ switch (st->hcchar_copy.b.multicnt) { -+ case 1: -+ st->hctsiz_copy.b.pid = DWC_PID_DATA0; -+ break; -+ case 2: -+ case 3: -+ st->hctsiz_copy.b.pid = DWC_PID_MDATA; -+ break; -+ } -+ -+ } else { -+ st->hctsiz_copy.b.xfersize = nrpackets * st->hcchar_copy.b.mps; -+ switch (st->hcchar_copy.b.multicnt) { -+ case 1: -+ st->hctsiz_copy.b.pid = DWC_PID_DATA0; -+ break; -+ case 2: -+ st->hctsiz_copy.b.pid = DWC_PID_DATA1; -+ break; -+ case 3: -+ st->hctsiz_copy.b.pid = DWC_PID_DATA2; -+ break; -+ } -+ } -+ -+ st->hs_isoc_info.stride = qh->interval; -+ st->uframe_sleeps = 0; -+ -+ fiq_print(FIQDBG_INT, hcd->fiq_state, "FSMQ %01d ", hc->hc_num); -+ fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcchar_copy.d32); -+ fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hctsiz_copy.d32); -+ fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcdma_copy.d32); -+ hfnum.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum); -+ local_fiq_disable(); -+ fiq_fsm_spin_lock(&hcd->fiq_state->lock); -+ DWC_WRITE_REG32(&hc_regs->hctsiz, st->hctsiz_copy.d32); -+ DWC_WRITE_REG32(&hc_regs->hcsplt, st->hcsplt_copy.d32); -+ DWC_WRITE_REG32(&hc_regs->hcdma, st->hcdma_copy.d32); -+ DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32); -+ DWC_WRITE_REG32(&hc_regs->hcintmsk, st->hcintmsk_copy.d32); -+ if (hfnum.b.frrem < PERIODIC_FRREM_BACKOFF) { -+ /* Prevent queueing near EOF1. Bad things happen if a periodic -+ * split transaction is queued very close to EOF. SOF interrupt handler -+ * will wake this channel at the next interrupt. -+ */ -+ st->fsm = FIQ_HS_ISOC_SLEEPING; -+ st->uframe_sleeps = 1; -+ } else { -+ st->fsm = FIQ_HS_ISOC_TURBO; -+ st->hcchar_copy.b.chen = 1; -+ DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32); -+ } -+ mb(); -+ st->hcchar_copy.b.chen = 0; -+ fiq_fsm_spin_unlock(&hcd->fiq_state->lock); -+ local_fiq_enable(); -+ return 0; -+} -+ -+ -+/** -+ * fiq_fsm_queue_split_transaction() - Set up a host channel and FIQ state -+ * @hcd: Pointer to the dwc_otg_hcd struct -+ * @qh: Pointer to the endpoint's queue head -+ * -+ * This overrides the dwc_otg driver's normal method of queueing a transaction. -+ * Called from dwc_otg_hcd_queue_transactions(), this performs specific setup -+ * for the nominated host channel. -+ * -+ * For periodic transfers, it also peeks at the FIQ state to see if an immediate -+ * start is possible. If not, then the FIQ is left to start the transfer. -+ */ -+int fiq_fsm_queue_split_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) -+{ -+ int start_immediate = 1, i; -+ hfnum_data_t hfnum; -+ dwc_hc_t *hc = qh->channel; -+ dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num]; -+ /* Program HC registers, setup FIQ_state, examine FIQ if periodic, start transfer (not if uframe 5) */ -+ int hub_addr, port_addr, frame, uframe; -+ struct fiq_channel_state *st = &hcd->fiq_state->channel[hc->hc_num]; -+ -+ if (st->fsm != FIQ_PASSTHROUGH) -+ return 0; -+ st->nr_errors = 0; -+ -+ st->hcchar_copy.d32 = 0; -+ st->hcchar_copy.b.mps = hc->max_packet; -+ st->hcchar_copy.b.epdir = hc->ep_is_in; -+ st->hcchar_copy.b.devaddr = hc->dev_addr; -+ st->hcchar_copy.b.epnum = hc->ep_num; -+ st->hcchar_copy.b.eptype = hc->ep_type; -+ if (hc->ep_type & 0x1) { -+ if (hc->ep_is_in) -+ st->hcchar_copy.b.multicnt = 3; -+ else -+ /* Docs say set this to 1, but driver sets to 0! */ -+ st->hcchar_copy.b.multicnt = 0; -+ } else { -+ st->hcchar_copy.b.multicnt = 1; -+ st->hcchar_copy.b.oddfrm = 0; -+ } -+ st->hcchar_copy.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW) ? 1 : 0; -+ /* Enable the channel later as a final register write. */ -+ -+ st->hcsplt_copy.d32 = 0; -+ if(qh->do_split) { -+ hcd->fops->hub_info(hcd, DWC_CIRCLEQ_FIRST(&qh->qtd_list)->urb->priv, &hub_addr, &port_addr); -+ st->hcsplt_copy.b.compsplt = 0; -+ st->hcsplt_copy.b.spltena = 1; -+ // XACTPOS is for isoc-out only but needs initialising anyway. -+ st->hcsplt_copy.b.xactpos = ISOC_XACTPOS_ALL; -+ if((qh->ep_type == DWC_OTG_EP_TYPE_ISOC) && (!qh->ep_is_in)) { -+ /* For packetsize 0 < L < 188, ISOC_XACTPOS_ALL. -+ * for longer than this, ISOC_XACTPOS_BEGIN and the FIQ -+ * will update as necessary. -+ */ -+ if (hc->xfer_len > 188) { -+ st->hcsplt_copy.b.xactpos = ISOC_XACTPOS_BEGIN; -+ } -+ } -+ st->hcsplt_copy.b.hubaddr = (uint8_t) hub_addr; -+ st->hcsplt_copy.b.prtaddr = (uint8_t) port_addr; -+ st->hub_addr = hub_addr; -+ st->port_addr = port_addr; -+ } -+ -+ st->hctsiz_copy.d32 = 0; -+ st->hctsiz_copy.b.dopng = 0; -+ st->hctsiz_copy.b.pid = hc->data_pid_start; -+ -+ if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) { -+ hc->xfer_len = hc->max_packet; -+ } else if (!hc->ep_is_in && (hc->xfer_len > 188)) { -+ hc->xfer_len = 188; -+ } -+ st->hctsiz_copy.b.xfersize = hc->xfer_len; -+ -+ st->hctsiz_copy.b.pktcnt = 1; -+ -+ if (hc->ep_type & 0x1) { -+ /* -+ * For potentially multi-packet transfers, must use the DMA bounce buffers. For IN transfers, -+ * the DMA address is the address of the first 188byte slot buffer in the bounce buffer array. -+ * For multi-packet OUT transfers, we need to copy the data into the bounce buffer array so the FIQ can punt -+ * the right address out as necessary. hc->xfer_buff and hc->xfer_len have already been set -+ * in assign_and_init_hc(), but this is for the eventual transaction completion only. The FIQ -+ * must not touch internal driver state. -+ */ -+ if(!fiq_fsm_setup_periodic_dma(hcd, st, qh)) { -+ if (hc->align_buff) { -+ st->hcdma_copy.d32 = hc->align_buff; -+ } else { -+ st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF); -+ } -+ } -+ } else { -+ if (hc->align_buff) { -+ st->hcdma_copy.d32 = hc->align_buff; -+ } else { -+ st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF); -+ } -+ } -+ /* The FIQ depends upon no other interrupts being enabled except channel halt. -+ * Fixup channel interrupt mask. */ -+ st->hcintmsk_copy.d32 = 0; -+ st->hcintmsk_copy.b.chhltd = 1; -+ st->hcintmsk_copy.b.ahberr = 1; -+ -+ /* Hack courtesy of FreeBSD: apparently forcing Interrupt Split transactions -+ * as Control puts the transfer into the non-periodic request queue and the -+ * non-periodic handler in the hub. Makes things lots easier. -+ */ -+ if ((fiq_fsm_mask & 0x8) && hc->ep_type == UE_INTERRUPT) { -+ st->hcchar_copy.b.multicnt = 0; -+ st->hcchar_copy.b.oddfrm = 0; -+ st->hcchar_copy.b.eptype = UE_CONTROL; -+ if (hc->align_buff) { -+ st->hcdma_copy.d32 = hc->align_buff; -+ } else { -+ st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF); -+ } -+ } -+ DWC_WRITE_REG32(&hc_regs->hcdma, st->hcdma_copy.d32); -+ DWC_WRITE_REG32(&hc_regs->hctsiz, st->hctsiz_copy.d32); -+ DWC_WRITE_REG32(&hc_regs->hcsplt, st->hcsplt_copy.d32); -+ DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32); -+ DWC_WRITE_REG32(&hc_regs->hcintmsk, st->hcintmsk_copy.d32); -+ -+ local_fiq_disable(); -+ fiq_fsm_spin_lock(&hcd->fiq_state->lock); -+ -+ if (hc->ep_type & 0x1) { -+ hfnum.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum); -+ frame = (hfnum.b.frnum & ~0x7) >> 3; -+ uframe = hfnum.b.frnum & 0x7; -+ if (hfnum.b.frrem < PERIODIC_FRREM_BACKOFF) { -+ /* Prevent queueing near EOF1. Bad things happen if a periodic -+ * split transaction is queued very close to EOF. -+ */ -+ start_immediate = 0; -+ } else if (uframe == 5) { -+ start_immediate = 0; -+ } else if (hc->ep_type == UE_ISOCHRONOUS && !hc->ep_is_in) { -+ start_immediate = 0; -+ } else if (hc->ep_is_in && fiq_fsm_too_late(hcd->fiq_state, hc->hc_num)) { -+ start_immediate = 0; -+ } else { -+ /* Search through all host channels to determine if a transaction -+ * is currently in progress */ -+ for (i = 0; i < hcd->core_if->core_params->host_channels; i++) { -+ if (i == hc->hc_num || hcd->fiq_state->channel[i].fsm == FIQ_PASSTHROUGH) -+ continue; -+ switch (hcd->fiq_state->channel[i].fsm) { -+ /* TT is reserved for channels that are in the middle of a periodic -+ * split transaction. -+ */ -+ case FIQ_PER_SSPLIT_STARTED: -+ case FIQ_PER_CSPLIT_WAIT: -+ case FIQ_PER_CSPLIT_NYET1: -+ case FIQ_PER_CSPLIT_POLL: -+ case FIQ_PER_ISO_OUT_ACTIVE: -+ case FIQ_PER_ISO_OUT_LAST: -+ if (hcd->fiq_state->channel[i].hub_addr == hub_addr && -+ hcd->fiq_state->channel[i].port_addr == port_addr) { -+ start_immediate = 0; -+ } -+ break; -+ default: -+ break; -+ } -+ if (!start_immediate) -+ break; -+ } -+ } -+ } -+ if ((fiq_fsm_mask & 0x8) && hc->ep_type == UE_INTERRUPT) -+ start_immediate = 1; -+ -+ fiq_print(FIQDBG_INT, hcd->fiq_state, "FSMQ %01d %01d", hc->hc_num, start_immediate); -+ fiq_print(FIQDBG_INT, hcd->fiq_state, "%08d", hfnum.b.frrem); -+ //fiq_print(FIQDBG_INT, hcd->fiq_state, "H:%02dP:%02d", hub_addr, port_addr); -+ //fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hctsiz_copy.d32); -+ //fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcdma_copy.d32); -+ switch (hc->ep_type) { -+ case UE_CONTROL: -+ case UE_BULK: -+ st->fsm = FIQ_NP_SSPLIT_STARTED; -+ break; -+ case UE_ISOCHRONOUS: -+ if (hc->ep_is_in) { -+ if (start_immediate) { -+ st->fsm = FIQ_PER_SSPLIT_STARTED; -+ } else { -+ st->fsm = FIQ_PER_SSPLIT_QUEUED; -+ } -+ } else { -+ if (start_immediate) { -+ /* Single-isoc OUT packets don't require FIQ involvement */ -+ if (st->nrpackets == 1) { -+ st->fsm = FIQ_PER_ISO_OUT_LAST; -+ } else { -+ st->fsm = FIQ_PER_ISO_OUT_ACTIVE; -+ } -+ } else { -+ st->fsm = FIQ_PER_ISO_OUT_PENDING; -+ } -+ } -+ break; -+ case UE_INTERRUPT: -+ if (fiq_fsm_mask & 0x8) { -+ st->fsm = FIQ_NP_SSPLIT_STARTED; -+ } else if (start_immediate) { -+ st->fsm = FIQ_PER_SSPLIT_STARTED; -+ } else { -+ st->fsm = FIQ_PER_SSPLIT_QUEUED; -+ } -+ default: -+ break; -+ } -+ if (start_immediate) { -+ /* Set the oddfrm bit as close as possible to actual queueing */ -+ frame = dwc_otg_hcd_get_frame_number(hcd); -+ st->expected_uframe = (frame + 1) & 0x3FFF; -+ st->hcchar_copy.b.oddfrm = (frame & 0x1) ? 0 : 1; -+ st->hcchar_copy.b.chen = 1; -+ DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32); -+ } -+ mb(); -+ fiq_fsm_spin_unlock(&hcd->fiq_state->lock); -+ local_fiq_enable(); -+ return 0; -+} -+ -+ -+/** -+ * This function selects transactions from the HCD transfer schedule and -+ * assigns them to available host channels. It is called from HCD interrupt -+ * handler functions. -+ * -+ * @param hcd The HCD state structure. -+ * -+ * @return The types of new transactions that were assigned to host channels. -+ */ -+dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd) -+{ -+ dwc_list_link_t *qh_ptr; -+ dwc_otg_qh_t *qh; -+ int num_channels; -+ dwc_irqflags_t flags; -+ dwc_spinlock_t *channel_lock = hcd->channel_lock; -+ dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE; -+ -+#ifdef DEBUG_HOST_CHANNELS -+ last_sel_trans_num_per_scheduled = 0; -+ last_sel_trans_num_nonper_scheduled = 0; -+ last_sel_trans_num_avail_hc_at_start = hcd->available_host_channels; -+#endif /* DEBUG_HOST_CHANNELS */ -+ -+ /* Process entries in the periodic ready list. */ -+ qh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready); -+ -+ while (qh_ptr != &hcd->periodic_sched_ready && -+ !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) { -+ -+ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); -+ -+ if (microframe_schedule) { -+ // Make sure we leave one channel for non periodic transactions. -+ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags); -+ if (hcd->available_host_channels <= 1) { -+ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); -+ break; -+ } -+ hcd->available_host_channels--; -+ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); -+#ifdef DEBUG_HOST_CHANNELS -+ last_sel_trans_num_per_scheduled++; -+#endif /* DEBUG_HOST_CHANNELS */ -+ } -+ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); -+ assign_and_init_hc(hcd, qh); -+ -+ /* -+ * Move the QH from the periodic ready schedule to the -+ * periodic assigned schedule. -+ */ -+ qh_ptr = DWC_LIST_NEXT(qh_ptr); -+ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags); -+ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned, -+ &qh->qh_list_entry); -+ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); -+ } -+ -+ /* -+ * Process entries in the inactive portion of the non-periodic -+ * schedule. Some free host channels may not be used if they are -+ * reserved for periodic transfers. -+ */ -+ qh_ptr = hcd->non_periodic_sched_inactive.next; -+ num_channels = hcd->core_if->core_params->host_channels; -+ while (qh_ptr != &hcd->non_periodic_sched_inactive && -+ (microframe_schedule || hcd->non_periodic_channels < -+ num_channels - hcd->periodic_channels) && -+ !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) { -+ -+ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); -+ /* -+ * Check to see if this is a NAK'd retransmit, in which case ignore for retransmission -+ * we hold off on bulk retransmissions to reduce NAK interrupt overhead for full-speed -+ * cheeky devices that just hold off using NAKs -+ */ -+ if (fiq_enable && nak_holdoff && qh->do_split) { -+ if (qh->nak_frame != 0xffff) { -+ uint16_t next_frame = dwc_frame_num_inc(qh->nak_frame, (qh->ep_type == UE_BULK) ? nak_holdoff : 8); -+ uint16_t frame = dwc_otg_hcd_get_frame_number(hcd); -+ if (dwc_frame_num_le(frame, next_frame)) { -+ if(dwc_frame_num_le(next_frame, hcd->fiq_state->next_sched_frame)) { -+ hcd->fiq_state->next_sched_frame = next_frame; -+ } -+ qh_ptr = DWC_LIST_NEXT(qh_ptr); -+ continue; -+ } else { -+ qh->nak_frame = 0xFFFF; -+ } -+ } -+ } -+ -+ if (microframe_schedule) { -+ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags); -+ if (hcd->available_host_channels < 1) { -+ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); -+ break; -+ } -+ hcd->available_host_channels--; -+ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); -+#ifdef DEBUG_HOST_CHANNELS -+ last_sel_trans_num_nonper_scheduled++; -+#endif /* DEBUG_HOST_CHANNELS */ -+ } -+ -+ assign_and_init_hc(hcd, qh); -+ -+ /* -+ * Move the QH from the non-periodic inactive schedule to the -+ * non-periodic active schedule. -+ */ -+ qh_ptr = DWC_LIST_NEXT(qh_ptr); -+ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags); -+ DWC_LIST_MOVE_HEAD(&hcd->non_periodic_sched_active, -+ &qh->qh_list_entry); -+ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); -+ -+ -+ if (!microframe_schedule) -+ hcd->non_periodic_channels++; -+ } -+ /* we moved a non-periodic QH to the active schedule. If the inactive queue is empty, -+ * stop the FIQ from kicking us. We could potentially still have elements here if we -+ * ran out of host channels. -+ */ -+ if (fiq_enable) { -+ if (DWC_LIST_EMPTY(&hcd->non_periodic_sched_inactive)) { -+ hcd->fiq_state->kick_np_queues = 0; -+ } else { -+ /* For each entry remaining in the NP inactive queue, -+ * if this a NAK'd retransmit then don't set the kick flag. -+ */ -+ if(nak_holdoff) { -+ DWC_LIST_FOREACH(qh_ptr, &hcd->non_periodic_sched_inactive) { -+ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); -+ if (qh->nak_frame == 0xFFFF) { -+ hcd->fiq_state->kick_np_queues = 1; -+ } -+ } -+ } -+ } -+ } -+ if(!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) -+ ret_val |= DWC_OTG_TRANSACTION_PERIODIC; -+ -+ if(!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active)) -+ ret_val |= DWC_OTG_TRANSACTION_NON_PERIODIC; -+ -+ -+#ifdef DEBUG_HOST_CHANNELS -+ last_sel_trans_num_avail_hc_at_end = hcd->available_host_channels; -+#endif /* DEBUG_HOST_CHANNELS */ -+ return ret_val; -+} -+ -+/** -+ * Attempts to queue a single transaction request for a host channel -+ * associated with either a periodic or non-periodic transfer. This function -+ * assumes that there is space available in the appropriate request queue. For -+ * an OUT transfer or SETUP transaction in Slave mode, it checks whether space -+ * is available in the appropriate Tx FIFO. -+ * -+ * @param hcd The HCD state structure. -+ * @param hc Host channel descriptor associated with either a periodic or -+ * non-periodic transfer. -+ * @param fifo_dwords_avail Number of DWORDs available in the periodic Tx -+ * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic -+ * transfers. -+ * -+ * @return 1 if a request is queued and more requests may be needed to -+ * complete the transfer, 0 if no more requests are required for this -+ * transfer, -1 if there is insufficient space in the Tx FIFO. -+ */ -+static int queue_transaction(dwc_otg_hcd_t * hcd, -+ dwc_hc_t * hc, uint16_t fifo_dwords_avail) -+{ -+ int retval; -+ -+ if (hcd->core_if->dma_enable) { -+ if (hcd->core_if->dma_desc_enable) { -+ if (!hc->xfer_started -+ || (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) { -+ dwc_otg_hcd_start_xfer_ddma(hcd, hc->qh); -+ hc->qh->ping_state = 0; -+ } -+ } else if (!hc->xfer_started) { -+ if (fiq_fsm_enable && hc->error_state) { -+ hcd->fiq_state->channel[hc->hc_num].nr_errors = -+ DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list)->error_count; -+ hcd->fiq_state->channel[hc->hc_num].fsm = -+ FIQ_PASSTHROUGH_ERRORSTATE; -+ } -+ dwc_otg_hc_start_transfer(hcd->core_if, hc); -+ hc->qh->ping_state = 0; -+ } -+ retval = 0; -+ } else if (hc->halt_pending) { -+ /* Don't queue a request if the channel has been halted. */ -+ retval = 0; -+ } else if (hc->halt_on_queue) { -+ dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status); -+ retval = 0; -+ } else if (hc->do_ping) { -+ if (!hc->xfer_started) { -+ dwc_otg_hc_start_transfer(hcd->core_if, hc); -+ } -+ retval = 0; -+ } else if (!hc->ep_is_in || hc->data_pid_start == DWC_OTG_HC_PID_SETUP) { -+ if ((fifo_dwords_avail * 4) >= hc->max_packet) { -+ if (!hc->xfer_started) { -+ dwc_otg_hc_start_transfer(hcd->core_if, hc); -+ retval = 1; -+ } else { -+ retval = -+ dwc_otg_hc_continue_transfer(hcd->core_if, -+ hc); -+ } -+ } else { -+ retval = -1; -+ } -+ } else { -+ if (!hc->xfer_started) { -+ dwc_otg_hc_start_transfer(hcd->core_if, hc); -+ retval = 1; -+ } else { -+ retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc); -+ } -+ } -+ -+ return retval; -+} -+ -+/** -+ * Processes periodic channels for the next frame and queues transactions for -+ * these channels to the DWC_otg controller. After queueing transactions, the -+ * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions -+ * to queue as Periodic Tx FIFO or request queue space becomes available. -+ * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. -+ */ -+static void process_periodic_channels(dwc_otg_hcd_t * hcd) -+{ -+ hptxsts_data_t tx_status; -+ dwc_list_link_t *qh_ptr; -+ dwc_otg_qh_t *qh; -+ int status = 0; -+ int no_queue_space = 0; -+ int no_fifo_space = 0; -+ -+ dwc_otg_host_global_regs_t *host_regs; -+ host_regs = hcd->core_if->host_if->host_global_regs; -+ -+ DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n"); -+#ifdef DEBUG -+ tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts); -+ DWC_DEBUGPL(DBG_HCDV, -+ " P Tx Req Queue Space Avail (before queue): %d\n", -+ tx_status.b.ptxqspcavail); -+ DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (before queue): %d\n", -+ tx_status.b.ptxfspcavail); -+#endif -+ -+ qh_ptr = hcd->periodic_sched_assigned.next; -+ while (qh_ptr != &hcd->periodic_sched_assigned) { -+ tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts); -+ if (tx_status.b.ptxqspcavail == 0) { -+ no_queue_space = 1; -+ break; -+ } -+ -+ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); -+ -+ // Do not send a split start transaction any later than frame .6 -+ // Note, we have to schedule a periodic in .5 to make it go in .6 -+ if(fiq_fsm_enable && qh->do_split && ((dwc_otg_hcd_get_frame_number(hcd) + 1) & 7) > 6) -+ { -+ qh_ptr = qh_ptr->next; -+ hcd->fiq_state->next_sched_frame = dwc_otg_hcd_get_frame_number(hcd) | 7; -+ continue; -+ } -+ -+ if (fiq_fsm_enable && fiq_fsm_transaction_suitable(qh)) { -+ if (qh->do_split) -+ fiq_fsm_queue_split_transaction(hcd, qh); -+ else -+ fiq_fsm_queue_isoc_transaction(hcd, qh); -+ } else { -+ -+ /* -+ * Set a flag if we're queueing high-bandwidth in slave mode. -+ * The flag prevents any halts to get into the request queue in -+ * the middle of multiple high-bandwidth packets getting queued. -+ */ -+ if (!hcd->core_if->dma_enable && qh->channel->multi_count > 1) { -+ hcd->core_if->queuing_high_bandwidth = 1; -+ } -+ status = queue_transaction(hcd, qh->channel, -+ tx_status.b.ptxfspcavail); -+ if (status < 0) { -+ no_fifo_space = 1; -+ break; -+ } -+ } -+ -+ /* -+ * In Slave mode, stay on the current transfer until there is -+ * nothing more to do or the high-bandwidth request count is -+ * reached. In DMA mode, only need to queue one request. The -+ * controller automatically handles multiple packets for -+ * high-bandwidth transfers. -+ */ -+ if (hcd->core_if->dma_enable || status == 0 || -+ qh->channel->requests == qh->channel->multi_count) { -+ qh_ptr = qh_ptr->next; -+ /* -+ * Move the QH from the periodic assigned schedule to -+ * the periodic queued schedule. -+ */ -+ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_queued, -+ &qh->qh_list_entry); -+ -+ /* done queuing high bandwidth */ -+ hcd->core_if->queuing_high_bandwidth = 0; -+ } -+ } -+ -+ if (!hcd->core_if->dma_enable) { -+ dwc_otg_core_global_regs_t *global_regs; -+ gintmsk_data_t intr_mask = {.d32 = 0 }; -+ -+ global_regs = hcd->core_if->core_global_regs; -+ intr_mask.b.ptxfempty = 1; -+#ifdef DEBUG -+ tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts); -+ DWC_DEBUGPL(DBG_HCDV, -+ " P Tx Req Queue Space Avail (after queue): %d\n", -+ tx_status.b.ptxqspcavail); -+ DWC_DEBUGPL(DBG_HCDV, -+ " P Tx FIFO Space Avail (after queue): %d\n", -+ tx_status.b.ptxfspcavail); -+#endif -+ if (!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned) || -+ no_queue_space || no_fifo_space) { -+ /* -+ * May need to queue more transactions as the request -+ * queue or Tx FIFO empties. Enable the periodic Tx -+ * FIFO empty interrupt. (Always use the half-empty -+ * level to ensure that new requests are loaded as -+ * soon as possible.) -+ */ -+ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, -+ intr_mask.d32); -+ } else { -+ /* -+ * Disable the Tx FIFO empty interrupt since there are -+ * no more transactions that need to be queued right -+ * now. This function is called from interrupt -+ * handlers to queue more transactions as transfer -+ * states change. -+ */ -+ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, -+ 0); -+ } -+ } -+} -+ -+/** -+ * Processes active non-periodic channels and queues transactions for these -+ * channels to the DWC_otg controller. After queueing transactions, the NP Tx -+ * FIFO Empty interrupt is enabled if there are more transactions to queue as -+ * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx -+ * FIFO Empty interrupt is disabled. -+ */ -+static void process_non_periodic_channels(dwc_otg_hcd_t * hcd) -+{ -+ gnptxsts_data_t tx_status; -+ dwc_list_link_t *orig_qh_ptr; -+ dwc_otg_qh_t *qh; -+ int status; -+ int no_queue_space = 0; -+ int no_fifo_space = 0; -+ int more_to_do = 0; -+ -+ dwc_otg_core_global_regs_t *global_regs = -+ hcd->core_if->core_global_regs; -+ -+ DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n"); -+#ifdef DEBUG -+ tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts); -+ DWC_DEBUGPL(DBG_HCDV, -+ " NP Tx Req Queue Space Avail (before queue): %d\n", -+ tx_status.b.nptxqspcavail); -+ DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (before queue): %d\n", -+ tx_status.b.nptxfspcavail); -+#endif -+ /* -+ * Keep track of the starting point. Skip over the start-of-list -+ * entry. -+ */ -+ if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) { -+ hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next; -+ } -+ orig_qh_ptr = hcd->non_periodic_qh_ptr; -+ -+ /* -+ * Process once through the active list or until no more space is -+ * available in the request queue or the Tx FIFO. -+ */ -+ do { -+ tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts); -+ if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) { -+ no_queue_space = 1; -+ break; -+ } -+ -+ qh = DWC_LIST_ENTRY(hcd->non_periodic_qh_ptr, dwc_otg_qh_t, -+ qh_list_entry); -+ -+ if(fiq_fsm_enable && fiq_fsm_transaction_suitable(qh)) { -+ fiq_fsm_queue_split_transaction(hcd, qh); -+ } else { -+ status = queue_transaction(hcd, qh->channel, -+ tx_status.b.nptxfspcavail); -+ -+ if (status > 0) { -+ more_to_do = 1; -+ } else if (status < 0) { -+ no_fifo_space = 1; -+ break; -+ } -+ } -+ /* Advance to next QH, skipping start-of-list entry. */ -+ hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next; -+ if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) { -+ hcd->non_periodic_qh_ptr = -+ hcd->non_periodic_qh_ptr->next; -+ } -+ -+ } while (hcd->non_periodic_qh_ptr != orig_qh_ptr); -+ -+ if (!hcd->core_if->dma_enable) { -+ gintmsk_data_t intr_mask = {.d32 = 0 }; -+ intr_mask.b.nptxfempty = 1; -+ -+#ifdef DEBUG -+ tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts); -+ DWC_DEBUGPL(DBG_HCDV, -+ " NP Tx Req Queue Space Avail (after queue): %d\n", -+ tx_status.b.nptxqspcavail); -+ DWC_DEBUGPL(DBG_HCDV, -+ " NP Tx FIFO Space Avail (after queue): %d\n", -+ tx_status.b.nptxfspcavail); -+#endif -+ if (more_to_do || no_queue_space || no_fifo_space) { -+ /* -+ * May need to queue more transactions as the request -+ * queue or Tx FIFO empties. Enable the non-periodic -+ * Tx FIFO empty interrupt. (Always use the half-empty -+ * level to ensure that new requests are loaded as -+ * soon as possible.) -+ */ -+ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, -+ intr_mask.d32); -+ } else { -+ /* -+ * Disable the Tx FIFO empty interrupt since there are -+ * no more transactions that need to be queued right -+ * now. This function is called from interrupt -+ * handlers to queue more transactions as transfer -+ * states change. -+ */ -+ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, -+ 0); -+ } -+ } -+} -+ -+/** -+ * This function processes the currently active host channels and queues -+ * transactions for these channels to the DWC_otg controller. It is called -+ * from HCD interrupt handler functions. -+ * -+ * @param hcd The HCD state structure. -+ * @param tr_type The type(s) of transactions to queue (non-periodic, -+ * periodic, or both). -+ */ -+void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd, -+ dwc_otg_transaction_type_e tr_type) -+{ -+#ifdef DEBUG_SOF -+ DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n"); -+#endif -+ /* Process host channels associated with periodic transfers. */ -+ if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC || -+ tr_type == DWC_OTG_TRANSACTION_ALL) && -+ !DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) { -+ -+ process_periodic_channels(hcd); -+ } -+ -+ /* Process host channels associated with non-periodic transfers. */ -+ if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC || -+ tr_type == DWC_OTG_TRANSACTION_ALL) { -+ if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active)) { -+ process_non_periodic_channels(hcd); -+ } else { -+ /* -+ * Ensure NP Tx FIFO empty interrupt is disabled when -+ * there are no non-periodic transfers to process. -+ */ -+ gintmsk_data_t gintmsk = {.d32 = 0 }; -+ gintmsk.b.nptxfempty = 1; -+ -+ if (fiq_enable) { -+ local_fiq_disable(); -+ fiq_fsm_spin_lock(&hcd->fiq_state->lock); -+ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, gintmsk.d32, 0); -+ fiq_fsm_spin_unlock(&hcd->fiq_state->lock); -+ local_fiq_enable(); -+ } else { -+ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, gintmsk.d32, 0); -+ } -+ } -+ } -+} -+ -+#ifdef DWC_HS_ELECT_TST -+/* -+ * Quick and dirty hack to implement the HS Electrical Test -+ * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature. -+ * -+ * This code was copied from our userspace app "hset". It sends a -+ * Get Device Descriptor control sequence in two parts, first the -+ * Setup packet by itself, followed some time later by the In and -+ * Ack packets. Rather than trying to figure out how to add this -+ * functionality to the normal driver code, we just hijack the -+ * hardware, using these two function to drive the hardware -+ * directly. -+ */ -+ -+static dwc_otg_core_global_regs_t *global_regs; -+static dwc_otg_host_global_regs_t *hc_global_regs; -+static dwc_otg_hc_regs_t *hc_regs; -+static uint32_t *data_fifo; -+ -+static void do_setup(void) -+{ -+ gintsts_data_t gintsts; -+ hctsiz_data_t hctsiz; -+ hcchar_data_t hcchar; -+ haint_data_t haint; -+ hcint_data_t hcint; -+ -+ /* Enable HAINTs */ -+ DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001); -+ -+ /* Enable HCINTs */ -+ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3); -+ -+ /* Read GINTSTS */ -+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); -+ -+ /* Read HAINT */ -+ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); -+ -+ /* Read HCINT */ -+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); -+ -+ /* Read HCCHAR */ -+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); -+ -+ /* Clear HCINT */ -+ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); -+ -+ /* Clear HAINT */ -+ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); -+ -+ /* Clear GINTSTS */ -+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); -+ -+ /* Read GINTSTS */ -+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); -+ -+ /* -+ * Send Setup packet (Get Device Descriptor) -+ */ -+ -+ /* Make sure channel is disabled */ -+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); -+ if (hcchar.b.chen) { -+ hcchar.b.chdis = 1; -+// hcchar.b.chen = 1; -+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); -+ //sleep(1); -+ dwc_mdelay(1000); -+ -+ /* Read GINTSTS */ -+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); -+ -+ /* Read HAINT */ -+ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); -+ -+ /* Read HCINT */ -+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); -+ -+ /* Read HCCHAR */ -+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); -+ -+ /* Clear HCINT */ -+ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); -+ -+ /* Clear HAINT */ -+ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); -+ -+ /* Clear GINTSTS */ -+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); -+ -+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); -+ } -+ -+ /* Set HCTSIZ */ -+ hctsiz.d32 = 0; -+ hctsiz.b.xfersize = 8; -+ hctsiz.b.pktcnt = 1; -+ hctsiz.b.pid = DWC_OTG_HC_PID_SETUP; -+ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32); -+ -+ /* Set HCCHAR */ -+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); -+ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL; -+ hcchar.b.epdir = 0; -+ hcchar.b.epnum = 0; -+ hcchar.b.mps = 8; -+ hcchar.b.chen = 1; -+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); -+ -+ /* Fill FIFO with Setup data for Get Device Descriptor */ -+ data_fifo = (uint32_t *) ((char *)global_regs + 0x1000); -+ DWC_WRITE_REG32(data_fifo++, 0x01000680); -+ DWC_WRITE_REG32(data_fifo++, 0x00080000); -+ -+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); -+ -+ /* Wait for host channel interrupt */ -+ do { -+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); -+ } while (gintsts.b.hcintr == 0); -+ -+ /* Disable HCINTs */ -+ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000); -+ -+ /* Disable HAINTs */ -+ DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000); -+ -+ /* Read HAINT */ -+ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); -+ -+ /* Read HCINT */ -+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); -+ -+ /* Read HCCHAR */ -+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); -+ -+ /* Clear HCINT */ -+ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); -+ -+ /* Clear HAINT */ -+ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); -+ -+ /* Clear GINTSTS */ -+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); -+ -+ /* Read GINTSTS */ -+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); -+} -+ -+static void do_in_ack(void) -+{ -+ gintsts_data_t gintsts; -+ hctsiz_data_t hctsiz; -+ hcchar_data_t hcchar; -+ haint_data_t haint; -+ hcint_data_t hcint; -+ host_grxsts_data_t grxsts; -+ -+ /* Enable HAINTs */ -+ DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001); -+ -+ /* Enable HCINTs */ -+ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3); -+ -+ /* Read GINTSTS */ -+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); -+ -+ /* Read HAINT */ -+ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); -+ -+ /* Read HCINT */ -+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); -+ -+ /* Read HCCHAR */ -+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); -+ -+ /* Clear HCINT */ -+ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); -+ -+ /* Clear HAINT */ -+ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); -+ -+ /* Clear GINTSTS */ -+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); -+ -+ /* Read GINTSTS */ -+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); -+ -+ /* -+ * Receive Control In packet -+ */ -+ -+ /* Make sure channel is disabled */ -+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); -+ if (hcchar.b.chen) { -+ hcchar.b.chdis = 1; -+ hcchar.b.chen = 1; -+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); -+ //sleep(1); -+ dwc_mdelay(1000); -+ -+ /* Read GINTSTS */ -+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); -+ -+ /* Read HAINT */ -+ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); -+ -+ /* Read HCINT */ -+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); -+ -+ /* Read HCCHAR */ -+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); -+ -+ /* Clear HCINT */ -+ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); -+ -+ /* Clear HAINT */ -+ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); -+ -+ /* Clear GINTSTS */ -+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); -+ -+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); -+ } -+ -+ /* Set HCTSIZ */ -+ hctsiz.d32 = 0; -+ hctsiz.b.xfersize = 8; -+ hctsiz.b.pktcnt = 1; -+ hctsiz.b.pid = DWC_OTG_HC_PID_DATA1; -+ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32); -+ -+ /* Set HCCHAR */ -+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); -+ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL; -+ hcchar.b.epdir = 1; -+ hcchar.b.epnum = 0; -+ hcchar.b.mps = 8; -+ hcchar.b.chen = 1; -+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); -+ -+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); -+ -+ /* Wait for receive status queue interrupt */ -+ do { -+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); -+ } while (gintsts.b.rxstsqlvl == 0); -+ -+ /* Read RXSTS */ -+ grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp); -+ -+ /* Clear RXSTSQLVL in GINTSTS */ -+ gintsts.d32 = 0; -+ gintsts.b.rxstsqlvl = 1; -+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); -+ -+ switch (grxsts.b.pktsts) { -+ case DWC_GRXSTS_PKTSTS_IN: -+ /* Read the data into the host buffer */ -+ if (grxsts.b.bcnt > 0) { -+ int i; -+ int word_count = (grxsts.b.bcnt + 3) / 4; -+ -+ data_fifo = (uint32_t *) ((char *)global_regs + 0x1000); -+ -+ for (i = 0; i < word_count; i++) { -+ (void)DWC_READ_REG32(data_fifo++); -+ } -+ } -+ break; -+ -+ default: -+ break; -+ } -+ -+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); -+ -+ /* Wait for receive status queue interrupt */ -+ do { -+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); -+ } while (gintsts.b.rxstsqlvl == 0); -+ -+ /* Read RXSTS */ -+ grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp); -+ -+ /* Clear RXSTSQLVL in GINTSTS */ -+ gintsts.d32 = 0; -+ gintsts.b.rxstsqlvl = 1; -+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); -+ -+ switch (grxsts.b.pktsts) { -+ case DWC_GRXSTS_PKTSTS_IN_XFER_COMP: -+ break; -+ -+ default: -+ break; -+ } -+ -+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); -+ -+ /* Wait for host channel interrupt */ -+ do { -+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); -+ } while (gintsts.b.hcintr == 0); -+ -+ /* Read HAINT */ -+ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); -+ -+ /* Read HCINT */ -+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); -+ -+ /* Read HCCHAR */ -+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); -+ -+ /* Clear HCINT */ -+ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); -+ -+ /* Clear HAINT */ -+ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); -+ -+ /* Clear GINTSTS */ -+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); -+ -+ /* Read GINTSTS */ -+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); -+ -+// usleep(100000); -+// mdelay(100); -+ dwc_mdelay(1); -+ -+ /* -+ * Send handshake packet -+ */ -+ -+ /* Read HAINT */ -+ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); -+ -+ /* Read HCINT */ -+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); -+ -+ /* Read HCCHAR */ -+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); -+ -+ /* Clear HCINT */ -+ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); -+ -+ /* Clear HAINT */ -+ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); -+ -+ /* Clear GINTSTS */ -+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); -+ -+ /* Read GINTSTS */ -+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); -+ -+ /* Make sure channel is disabled */ -+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); -+ if (hcchar.b.chen) { -+ hcchar.b.chdis = 1; -+ hcchar.b.chen = 1; -+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); -+ //sleep(1); -+ dwc_mdelay(1000); -+ -+ /* Read GINTSTS */ -+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); -+ -+ /* Read HAINT */ -+ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); -+ -+ /* Read HCINT */ -+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); -+ -+ /* Read HCCHAR */ -+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); -+ -+ /* Clear HCINT */ -+ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); -+ -+ /* Clear HAINT */ -+ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); -+ -+ /* Clear GINTSTS */ -+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); -+ -+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); -+ } -+ -+ /* Set HCTSIZ */ -+ hctsiz.d32 = 0; -+ hctsiz.b.xfersize = 0; -+ hctsiz.b.pktcnt = 1; -+ hctsiz.b.pid = DWC_OTG_HC_PID_DATA1; -+ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32); -+ -+ /* Set HCCHAR */ -+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); -+ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL; -+ hcchar.b.epdir = 0; -+ hcchar.b.epnum = 0; -+ hcchar.b.mps = 8; -+ hcchar.b.chen = 1; -+ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); -+ -+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); -+ -+ /* Wait for host channel interrupt */ -+ do { -+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); -+ } while (gintsts.b.hcintr == 0); -+ -+ /* Disable HCINTs */ -+ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000); -+ -+ /* Disable HAINTs */ -+ DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000); -+ -+ /* Read HAINT */ -+ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); -+ -+ /* Read HCINT */ -+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); -+ -+ /* Read HCCHAR */ -+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); -+ -+ /* Clear HCINT */ -+ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); -+ -+ /* Clear HAINT */ -+ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); -+ -+ /* Clear GINTSTS */ -+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); -+ -+ /* Read GINTSTS */ -+ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); -+} -+#endif -+ -+/** Handles hub class-specific requests. */ -+int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd, -+ uint16_t typeReq, -+ uint16_t wValue, -+ uint16_t wIndex, uint8_t * buf, uint16_t wLength) -+{ -+ int retval = 0; -+ -+ dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; -+ usb_hub_descriptor_t *hub_desc; -+ hprt0_data_t hprt0 = {.d32 = 0 }; -+ -+ uint32_t port_status; -+ -+ switch (typeReq) { -+ case UCR_CLEAR_HUB_FEATURE: -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " -+ "ClearHubFeature 0x%x\n", wValue); -+ switch (wValue) { -+ case UHF_C_HUB_LOCAL_POWER: -+ case UHF_C_HUB_OVER_CURRENT: -+ /* Nothing required here */ -+ break; -+ default: -+ retval = -DWC_E_INVALID; -+ DWC_ERROR("DWC OTG HCD - " -+ "ClearHubFeature request %xh unknown\n", -+ wValue); -+ } -+ break; -+ case UCR_CLEAR_PORT_FEATURE: -+#ifdef CONFIG_USB_DWC_OTG_LPM -+ if (wValue != UHF_PORT_L1) -+#endif -+ if (!wIndex || wIndex > 1) -+ goto error; -+ -+ switch (wValue) { -+ case UHF_PORT_ENABLE: -+ DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - " -+ "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); -+ hprt0.d32 = dwc_otg_read_hprt0(core_if); -+ hprt0.b.prtena = 1; -+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); -+ break; -+ case UHF_PORT_SUSPEND: -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " -+ "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); -+ -+ if (core_if->power_down == 2) { -+ dwc_otg_host_hibernation_restore(core_if, 0, 0); -+ } else { -+ DWC_WRITE_REG32(core_if->pcgcctl, 0); -+ dwc_mdelay(5); -+ -+ hprt0.d32 = dwc_otg_read_hprt0(core_if); -+ hprt0.b.prtres = 1; -+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); -+ hprt0.b.prtsusp = 0; -+ /* Clear Resume bit */ -+ dwc_mdelay(100); -+ hprt0.b.prtres = 0; -+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); -+ } -+ break; -+#ifdef CONFIG_USB_DWC_OTG_LPM -+ case UHF_PORT_L1: -+ { -+ pcgcctl_data_t pcgcctl = {.d32 = 0 }; -+ glpmcfg_data_t lpmcfg = {.d32 = 0 }; -+ -+ lpmcfg.d32 = -+ DWC_READ_REG32(&core_if-> -+ core_global_regs->glpmcfg); -+ lpmcfg.b.en_utmi_sleep = 0; -+ lpmcfg.b.hird_thres &= (~(1 << 4)); -+ lpmcfg.b.prt_sleep_sts = 1; -+ DWC_WRITE_REG32(&core_if-> -+ core_global_regs->glpmcfg, -+ lpmcfg.d32); -+ -+ /* Clear Enbl_L1Gating bit. */ -+ pcgcctl.b.enbl_sleep_gating = 1; -+ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, -+ 0); -+ -+ dwc_mdelay(5); -+ -+ hprt0.d32 = dwc_otg_read_hprt0(core_if); -+ hprt0.b.prtres = 1; -+ DWC_WRITE_REG32(core_if->host_if->hprt0, -+ hprt0.d32); -+ /* This bit will be cleared in wakeup interrupt handle */ -+ break; -+ } -+#endif -+ case UHF_PORT_POWER: -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " -+ "ClearPortFeature USB_PORT_FEAT_POWER\n"); -+ hprt0.d32 = dwc_otg_read_hprt0(core_if); -+ hprt0.b.prtpwr = 0; -+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); -+ break; -+ case UHF_PORT_INDICATOR: -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " -+ "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); -+ /* Port inidicator not supported */ -+ break; -+ case UHF_C_PORT_CONNECTION: -+ /* Clears drivers internal connect status change -+ * flag */ -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " -+ "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); -+ dwc_otg_hcd->flags.b.port_connect_status_change = 0; -+ break; -+ case UHF_C_PORT_RESET: -+ /* Clears the driver's internal Port Reset Change -+ * flag */ -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " -+ "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); -+ dwc_otg_hcd->flags.b.port_reset_change = 0; -+ break; -+ case UHF_C_PORT_ENABLE: -+ /* Clears the driver's internal Port -+ * Enable/Disable Change flag */ -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " -+ "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); -+ dwc_otg_hcd->flags.b.port_enable_change = 0; -+ break; -+ case UHF_C_PORT_SUSPEND: -+ /* Clears the driver's internal Port Suspend -+ * Change flag, which is set when resume signaling on -+ * the host port is complete */ -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " -+ "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); -+ dwc_otg_hcd->flags.b.port_suspend_change = 0; -+ break; -+#ifdef CONFIG_USB_DWC_OTG_LPM -+ case UHF_C_PORT_L1: -+ dwc_otg_hcd->flags.b.port_l1_change = 0; -+ break; -+#endif -+ case UHF_C_PORT_OVER_CURRENT: -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " -+ "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); -+ dwc_otg_hcd->flags.b.port_over_current_change = 0; -+ break; -+ default: -+ retval = -DWC_E_INVALID; -+ DWC_ERROR("DWC OTG HCD - " -+ "ClearPortFeature request %xh " -+ "unknown or unsupported\n", wValue); -+ } -+ break; -+ case UCR_GET_HUB_DESCRIPTOR: -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " -+ "GetHubDescriptor\n"); -+ hub_desc = (usb_hub_descriptor_t *) buf; -+ hub_desc->bDescLength = 9; -+ hub_desc->bDescriptorType = 0x29; -+ hub_desc->bNbrPorts = 1; -+ USETW(hub_desc->wHubCharacteristics, 0x08); -+ hub_desc->bPwrOn2PwrGood = 1; -+ hub_desc->bHubContrCurrent = 0; -+ hub_desc->DeviceRemovable[0] = 0; -+ hub_desc->DeviceRemovable[1] = 0xff; -+ break; -+ case UCR_GET_HUB_STATUS: -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " -+ "GetHubStatus\n"); -+ DWC_MEMSET(buf, 0, 4); -+ break; -+ case UCR_GET_PORT_STATUS: -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " -+ "GetPortStatus wIndex = 0x%04x FLAGS=0x%08x\n", -+ wIndex, dwc_otg_hcd->flags.d32); -+ if (!wIndex || wIndex > 1) -+ goto error; -+ -+ port_status = 0; -+ -+ if (dwc_otg_hcd->flags.b.port_connect_status_change) -+ port_status |= (1 << UHF_C_PORT_CONNECTION); -+ -+ if (dwc_otg_hcd->flags.b.port_enable_change) -+ port_status |= (1 << UHF_C_PORT_ENABLE); -+ -+ if (dwc_otg_hcd->flags.b.port_suspend_change) -+ port_status |= (1 << UHF_C_PORT_SUSPEND); -+ -+ if (dwc_otg_hcd->flags.b.port_l1_change) -+ port_status |= (1 << UHF_C_PORT_L1); -+ -+ if (dwc_otg_hcd->flags.b.port_reset_change) { -+ port_status |= (1 << UHF_C_PORT_RESET); -+ } -+ -+ if (dwc_otg_hcd->flags.b.port_over_current_change) { -+ DWC_WARN("Overcurrent change detected\n"); -+ port_status |= (1 << UHF_C_PORT_OVER_CURRENT); -+ } -+ -+ if (!dwc_otg_hcd->flags.b.port_connect_status) { -+ /* -+ * The port is disconnected, which means the core is -+ * either in device mode or it soon will be. Just -+ * return 0's for the remainder of the port status -+ * since the port register can't be read if the core -+ * is in device mode. -+ */ -+ *((__le32 *) buf) = dwc_cpu_to_le32(&port_status); -+ break; -+ } -+ -+ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0); -+ DWC_DEBUGPL(DBG_HCDV, " HPRT0: 0x%08x\n", hprt0.d32); -+ -+ if (hprt0.b.prtconnsts) -+ port_status |= (1 << UHF_PORT_CONNECTION); -+ -+ if (hprt0.b.prtena) -+ port_status |= (1 << UHF_PORT_ENABLE); -+ -+ if (hprt0.b.prtsusp) -+ port_status |= (1 << UHF_PORT_SUSPEND); -+ -+ if (hprt0.b.prtovrcurract) -+ port_status |= (1 << UHF_PORT_OVER_CURRENT); -+ -+ if (hprt0.b.prtrst) -+ port_status |= (1 << UHF_PORT_RESET); -+ -+ if (hprt0.b.prtpwr) -+ port_status |= (1 << UHF_PORT_POWER); -+ -+ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) -+ port_status |= (1 << UHF_PORT_HIGH_SPEED); -+ else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED) -+ port_status |= (1 << UHF_PORT_LOW_SPEED); -+ -+ if (hprt0.b.prttstctl) -+ port_status |= (1 << UHF_PORT_TEST); -+ if (dwc_otg_get_lpm_portsleepstatus(dwc_otg_hcd->core_if)) { -+ port_status |= (1 << UHF_PORT_L1); -+ } -+ /* -+ For Synopsys HW emulation of Power down wkup_control asserts the -+ hreset_n and prst_n on suspned. This causes the HPRT0 to be zero. -+ We intentionally tell the software that port is in L2Suspend state. -+ Only for STE. -+ */ -+ if ((core_if->power_down == 2) -+ && (core_if->hibernation_suspend == 1)) { -+ port_status |= (1 << UHF_PORT_SUSPEND); -+ } -+ /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ -+ -+ *((__le32 *) buf) = dwc_cpu_to_le32(&port_status); -+ -+ break; -+ case UCR_SET_HUB_FEATURE: -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " -+ "SetHubFeature\n"); -+ /* No HUB features supported */ -+ break; -+ case UCR_SET_PORT_FEATURE: -+ if (wValue != UHF_PORT_TEST && (!wIndex || wIndex > 1)) -+ goto error; -+ -+ if (!dwc_otg_hcd->flags.b.port_connect_status) { -+ /* -+ * The port is disconnected, which means the core is -+ * either in device mode or it soon will be. Just -+ * return without doing anything since the port -+ * register can't be written if the core is in device -+ * mode. -+ */ -+ break; -+ } -+ -+ switch (wValue) { -+ case UHF_PORT_SUSPEND: -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " -+ "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); -+ if (dwc_otg_hcd_otg_port(dwc_otg_hcd) != wIndex) { -+ goto error; -+ } -+ if (core_if->power_down == 2) { -+ int timeout = 300; -+ dwc_irqflags_t flags; -+ pcgcctl_data_t pcgcctl = {.d32 = 0 }; -+ gpwrdn_data_t gpwrdn = {.d32 = 0 }; -+ gusbcfg_data_t gusbcfg = {.d32 = 0 }; -+#ifdef DWC_DEV_SRPCAP -+ int32_t otg_cap_param = core_if->core_params->otg_cap; -+#endif -+ DWC_PRINTF("Preparing for complete power-off\n"); -+ -+ /* Save registers before hibernation */ -+ dwc_otg_save_global_regs(core_if); -+ dwc_otg_save_host_regs(core_if); -+ -+ hprt0.d32 = dwc_otg_read_hprt0(core_if); -+ hprt0.b.prtsusp = 1; -+ hprt0.b.prtena = 0; -+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); -+ /* Spin hprt0.b.prtsusp to became 1 */ -+ do { -+ hprt0.d32 = dwc_otg_read_hprt0(core_if); -+ if (hprt0.b.prtsusp) { -+ break; -+ } -+ dwc_mdelay(1); -+ } while (--timeout); -+ if (!timeout) { -+ DWC_WARN("Suspend wasn't genereted\n"); -+ } -+ dwc_udelay(10); -+ -+ /* -+ * We need to disable interrupts to prevent servicing of any IRQ -+ * during going to hibernation -+ */ -+ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags); -+ core_if->lx_state = DWC_OTG_L2; -+#ifdef DWC_DEV_SRPCAP -+ hprt0.d32 = dwc_otg_read_hprt0(core_if); -+ hprt0.b.prtpwr = 0; -+ hprt0.b.prtena = 0; -+ DWC_WRITE_REG32(core_if->host_if->hprt0, -+ hprt0.d32); -+#endif -+ gusbcfg.d32 = -+ DWC_READ_REG32(&core_if->core_global_regs-> -+ gusbcfg); -+ if (gusbcfg.b.ulpi_utmi_sel == 1) { -+ /* ULPI interface */ -+ /* Suspend the Phy Clock */ -+ pcgcctl.d32 = 0; -+ pcgcctl.b.stoppclk = 1; -+ DWC_MODIFY_REG32(core_if->pcgcctl, 0, -+ pcgcctl.d32); -+ dwc_udelay(10); -+ gpwrdn.b.pmuactv = 1; -+ DWC_MODIFY_REG32(&core_if-> -+ core_global_regs-> -+ gpwrdn, 0, gpwrdn.d32); -+ } else { -+ /* UTMI+ Interface */ -+ gpwrdn.b.pmuactv = 1; -+ DWC_MODIFY_REG32(&core_if-> -+ core_global_regs-> -+ gpwrdn, 0, gpwrdn.d32); -+ dwc_udelay(10); -+ pcgcctl.b.stoppclk = 1; -+ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32); -+ dwc_udelay(10); -+ } -+#ifdef DWC_DEV_SRPCAP -+ gpwrdn.d32 = 0; -+ gpwrdn.b.dis_vbus = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs-> -+ gpwrdn, 0, gpwrdn.d32); -+#endif -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pmuintsel = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs-> -+ gpwrdn, 0, gpwrdn.d32); -+ dwc_udelay(10); -+ -+ gpwrdn.d32 = 0; -+#ifdef DWC_DEV_SRPCAP -+ gpwrdn.b.srp_det_msk = 1; -+#endif -+ gpwrdn.b.disconn_det_msk = 1; -+ gpwrdn.b.lnstchng_msk = 1; -+ gpwrdn.b.sts_chngint_msk = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs-> -+ gpwrdn, 0, gpwrdn.d32); -+ dwc_udelay(10); -+ -+ /* Enable Power Down Clamp and all interrupts in GPWRDN */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pwrdnclmp = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs-> -+ gpwrdn, 0, gpwrdn.d32); -+ dwc_udelay(10); -+ -+ /* Switch off VDD */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pwrdnswtch = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs-> -+ gpwrdn, 0, gpwrdn.d32); -+ -+#ifdef DWC_DEV_SRPCAP -+ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) -+ { -+ core_if->pwron_timer_started = 1; -+ DWC_TIMER_SCHEDULE(core_if->pwron_timer, 6000 /* 6 secs */ ); -+ } -+#endif -+ /* Save gpwrdn register for further usage if stschng interrupt */ -+ core_if->gr_backup->gpwrdn_local = -+ DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); -+ -+ /* Set flag to indicate that we are in hibernation */ -+ core_if->hibernation_suspend = 1; -+ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,flags); -+ -+ DWC_PRINTF("Host hibernation completed\n"); -+ // Exit from case statement -+ break; -+ -+ } -+ if (dwc_otg_hcd_otg_port(dwc_otg_hcd) == wIndex && -+ dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) { -+ gotgctl_data_t gotgctl = {.d32 = 0 }; -+ gotgctl.b.hstsethnpen = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs-> -+ gotgctl, 0, gotgctl.d32); -+ core_if->op_state = A_SUSPEND; -+ } -+ hprt0.d32 = dwc_otg_read_hprt0(core_if); -+ hprt0.b.prtsusp = 1; -+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); -+ { -+ dwc_irqflags_t flags; -+ /* Update lx_state */ -+ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags); -+ core_if->lx_state = DWC_OTG_L2; -+ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags); -+ } -+ /* Suspend the Phy Clock */ -+ { -+ pcgcctl_data_t pcgcctl = {.d32 = 0 }; -+ pcgcctl.b.stoppclk = 1; -+ DWC_MODIFY_REG32(core_if->pcgcctl, 0, -+ pcgcctl.d32); -+ dwc_udelay(10); -+ } -+ -+ /* For HNP the bus must be suspended for at least 200ms. */ -+ if (dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) { -+ pcgcctl_data_t pcgcctl = {.d32 = 0 }; -+ pcgcctl.b.stoppclk = 1; -+ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0); -+ dwc_mdelay(200); -+ } -+ -+ /** @todo - check how sw can wait for 1 sec to check asesvld??? */ -+#if 0 //vahrama !!!!!!!!!!!!!!!!!! -+ if (core_if->adp_enable) { -+ gotgctl_data_t gotgctl = {.d32 = 0 }; -+ gpwrdn_data_t gpwrdn; -+ -+ while (gotgctl.b.asesvld == 1) { -+ gotgctl.d32 = -+ DWC_READ_REG32(&core_if-> -+ core_global_regs-> -+ gotgctl); -+ dwc_mdelay(100); -+ } -+ -+ /* Enable Power Down Logic */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pmuactv = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs-> -+ gpwrdn, 0, gpwrdn.d32); -+ -+ /* Unmask SRP detected interrupt from Power Down Logic */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.srp_det_msk = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs-> -+ gpwrdn, 0, gpwrdn.d32); -+ -+ dwc_otg_adp_probe_start(core_if); -+ } -+#endif -+ break; -+ case UHF_PORT_POWER: -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " -+ "SetPortFeature - USB_PORT_FEAT_POWER\n"); -+ hprt0.d32 = dwc_otg_read_hprt0(core_if); -+ hprt0.b.prtpwr = 1; -+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); -+ break; -+ case UHF_PORT_RESET: -+ if ((core_if->power_down == 2) -+ && (core_if->hibernation_suspend == 1)) { -+ /* If we are going to exit from Hibernated -+ * state via USB RESET. -+ */ -+ dwc_otg_host_hibernation_restore(core_if, 0, 1); -+ } else { -+ hprt0.d32 = dwc_otg_read_hprt0(core_if); -+ -+ DWC_DEBUGPL(DBG_HCD, -+ "DWC OTG HCD HUB CONTROL - " -+ "SetPortFeature - USB_PORT_FEAT_RESET\n"); -+ { -+ pcgcctl_data_t pcgcctl = {.d32 = 0 }; -+ pcgcctl.b.enbl_sleep_gating = 1; -+ pcgcctl.b.stoppclk = 1; -+ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0); -+ DWC_WRITE_REG32(core_if->pcgcctl, 0); -+ } -+#ifdef CONFIG_USB_DWC_OTG_LPM -+ { -+ glpmcfg_data_t lpmcfg; -+ lpmcfg.d32 = -+ DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); -+ if (lpmcfg.b.prt_sleep_sts) { -+ lpmcfg.b.en_utmi_sleep = 0; -+ lpmcfg.b.hird_thres &= (~(1 << 4)); -+ DWC_WRITE_REG32 -+ (&core_if->core_global_regs->glpmcfg, -+ lpmcfg.d32); -+ dwc_mdelay(1); -+ } -+ } -+#endif -+ hprt0.d32 = dwc_otg_read_hprt0(core_if); -+ /* Clear suspend bit if resetting from suspended state. */ -+ hprt0.b.prtsusp = 0; -+ /* When B-Host the Port reset bit is set in -+ * the Start HCD Callback function, so that -+ * the reset is started within 1ms of the HNP -+ * success interrupt. */ -+ if (!dwc_otg_hcd_is_b_host(dwc_otg_hcd)) { -+ hprt0.b.prtpwr = 1; -+ hprt0.b.prtrst = 1; -+ DWC_PRINTF("Indeed it is in host mode hprt0 = %08x\n",hprt0.d32); -+ DWC_WRITE_REG32(core_if->host_if->hprt0, -+ hprt0.d32); -+ } -+ /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ -+ dwc_mdelay(60); -+ hprt0.b.prtrst = 0; -+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); -+ core_if->lx_state = DWC_OTG_L0; /* Now back to the on state */ -+ } -+ break; -+#ifdef DWC_HS_ELECT_TST -+ case UHF_PORT_TEST: -+ { -+ uint32_t t; -+ gintmsk_data_t gintmsk; -+ -+ t = (wIndex >> 8); /* MSB wIndex USB */ -+ DWC_DEBUGPL(DBG_HCD, -+ "DWC OTG HCD HUB CONTROL - " -+ "SetPortFeature - USB_PORT_FEAT_TEST %d\n", -+ t); -+ DWC_WARN("USB_PORT_FEAT_TEST %d\n", t); -+ if (t < 6) { -+ hprt0.d32 = dwc_otg_read_hprt0(core_if); -+ hprt0.b.prttstctl = t; -+ DWC_WRITE_REG32(core_if->host_if->hprt0, -+ hprt0.d32); -+ } else { -+ /* Setup global vars with reg addresses (quick and -+ * dirty hack, should be cleaned up) -+ */ -+ global_regs = core_if->core_global_regs; -+ hc_global_regs = -+ core_if->host_if->host_global_regs; -+ hc_regs = -+ (dwc_otg_hc_regs_t *) ((char *) -+ global_regs + -+ 0x500); -+ data_fifo = -+ (uint32_t *) ((char *)global_regs + -+ 0x1000); -+ -+ if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */ -+ /* Save current interrupt mask */ -+ gintmsk.d32 = -+ DWC_READ_REG32 -+ (&global_regs->gintmsk); -+ -+ /* Disable all interrupts while we muck with -+ * the hardware directly -+ */ -+ DWC_WRITE_REG32(&global_regs->gintmsk, 0); -+ -+ /* 15 second delay per the test spec */ -+ dwc_mdelay(15000); -+ -+ /* Drive suspend on the root port */ -+ hprt0.d32 = -+ dwc_otg_read_hprt0(core_if); -+ hprt0.b.prtsusp = 1; -+ hprt0.b.prtres = 0; -+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); -+ -+ /* 15 second delay per the test spec */ -+ dwc_mdelay(15000); -+ -+ /* Drive resume on the root port */ -+ hprt0.d32 = -+ dwc_otg_read_hprt0(core_if); -+ hprt0.b.prtsusp = 0; -+ hprt0.b.prtres = 1; -+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); -+ dwc_mdelay(100); -+ -+ /* Clear the resume bit */ -+ hprt0.b.prtres = 0; -+ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); -+ -+ /* Restore interrupts */ -+ DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32); -+ } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */ -+ /* Save current interrupt mask */ -+ gintmsk.d32 = -+ DWC_READ_REG32 -+ (&global_regs->gintmsk); -+ -+ /* Disable all interrupts while we muck with -+ * the hardware directly -+ */ -+ DWC_WRITE_REG32(&global_regs->gintmsk, 0); -+ -+ /* 15 second delay per the test spec */ -+ dwc_mdelay(15000); -+ -+ /* Send the Setup packet */ -+ do_setup(); -+ -+ /* 15 second delay so nothing else happens for awhile */ -+ dwc_mdelay(15000); -+ -+ /* Restore interrupts */ -+ DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32); -+ } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */ -+ /* Save current interrupt mask */ -+ gintmsk.d32 = -+ DWC_READ_REG32 -+ (&global_regs->gintmsk); -+ -+ /* Disable all interrupts while we muck with -+ * the hardware directly -+ */ -+ DWC_WRITE_REG32(&global_regs->gintmsk, 0); -+ -+ /* Send the Setup packet */ -+ do_setup(); -+ -+ /* 15 second delay so nothing else happens for awhile */ -+ dwc_mdelay(15000); -+ -+ /* Send the In and Ack packets */ -+ do_in_ack(); -+ -+ /* 15 second delay so nothing else happens for awhile */ -+ dwc_mdelay(15000); -+ -+ /* Restore interrupts */ -+ DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32); -+ } -+ } -+ break; -+ } -+#endif /* DWC_HS_ELECT_TST */ -+ -+ case UHF_PORT_INDICATOR: -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " -+ "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); -+ /* Not supported */ -+ break; -+ default: -+ retval = -DWC_E_INVALID; -+ DWC_ERROR("DWC OTG HCD - " -+ "SetPortFeature request %xh " -+ "unknown or unsupported\n", wValue); -+ break; -+ } -+ break; -+#ifdef CONFIG_USB_DWC_OTG_LPM -+ case UCR_SET_AND_TEST_PORT_FEATURE: -+ if (wValue != UHF_PORT_L1) { -+ goto error; -+ } -+ { -+ int portnum, hird, devaddr, remwake; -+ glpmcfg_data_t lpmcfg; -+ uint32_t time_usecs; -+ gintsts_data_t gintsts; -+ gintmsk_data_t gintmsk; -+ -+ if (!dwc_otg_get_param_lpm_enable(core_if)) { -+ goto error; -+ } -+ if (wValue != UHF_PORT_L1 || wLength != 1) { -+ goto error; -+ } -+ /* Check if the port currently is in SLEEP state */ -+ lpmcfg.d32 = -+ DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); -+ if (lpmcfg.b.prt_sleep_sts) { -+ DWC_INFO("Port is already in sleep mode\n"); -+ buf[0] = 0; /* Return success */ -+ break; -+ } -+ -+ portnum = wIndex & 0xf; -+ hird = (wIndex >> 4) & 0xf; -+ devaddr = (wIndex >> 8) & 0x7f; -+ remwake = (wIndex >> 15); -+ -+ if (portnum != 1) { -+ retval = -DWC_E_INVALID; -+ DWC_WARN -+ ("Wrong port number(%d) in SetandTestPortFeature request\n", -+ portnum); -+ break; -+ } -+ -+ DWC_PRINTF -+ ("SetandTestPortFeature request: portnum = %d, hird = %d, devaddr = %d, rewake = %d\n", -+ portnum, hird, devaddr, remwake); -+ /* Disable LPM interrupt */ -+ gintmsk.d32 = 0; -+ gintmsk.b.lpmtranrcvd = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, -+ gintmsk.d32, 0); -+ -+ if (dwc_otg_hcd_send_lpm -+ (dwc_otg_hcd, devaddr, hird, remwake)) { -+ retval = -DWC_E_INVALID; -+ break; -+ } -+ -+ time_usecs = 10 * (lpmcfg.b.retry_count + 1); -+ /* We will consider timeout if time_usecs microseconds pass, -+ * and we don't receive LPM transaction status. -+ * After receiving non-error responce(ACK/NYET/STALL) from device, -+ * core will set lpmtranrcvd bit. -+ */ -+ do { -+ gintsts.d32 = -+ DWC_READ_REG32(&core_if->core_global_regs->gintsts); -+ if (gintsts.b.lpmtranrcvd) { -+ break; -+ } -+ dwc_udelay(1); -+ } while (--time_usecs); -+ /* lpm_int bit will be cleared in LPM interrupt handler */ -+ -+ /* Now fill status -+ * 0x00 - Success -+ * 0x10 - NYET -+ * 0x11 - Timeout -+ */ -+ if (!gintsts.b.lpmtranrcvd) { -+ buf[0] = 0x3; /* Completion code is Timeout */ -+ dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd); -+ } else { -+ lpmcfg.d32 = -+ DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); -+ if (lpmcfg.b.lpm_resp == 0x3) { -+ /* ACK responce from the device */ -+ buf[0] = 0x00; /* Success */ -+ } else if (lpmcfg.b.lpm_resp == 0x2) { -+ /* NYET responce from the device */ -+ buf[0] = 0x2; -+ } else { -+ /* Otherwise responce with Timeout */ -+ buf[0] = 0x3; -+ } -+ } -+ DWC_PRINTF("Device responce to LPM trans is %x\n", -+ lpmcfg.b.lpm_resp); -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, -+ gintmsk.d32); -+ -+ break; -+ } -+#endif /* CONFIG_USB_DWC_OTG_LPM */ -+ default: -+error: -+ retval = -DWC_E_INVALID; -+ DWC_WARN("DWC OTG HCD - " -+ "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n", -+ typeReq, wIndex, wValue); -+ break; -+ } -+ -+ return retval; -+} -+ -+#ifdef CONFIG_USB_DWC_OTG_LPM -+/** Returns index of host channel to perform LPM transaction. */ -+int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd, uint8_t devaddr) -+{ -+ dwc_otg_core_if_t *core_if = hcd->core_if; -+ dwc_hc_t *hc; -+ hcchar_data_t hcchar; -+ gintmsk_data_t gintmsk = {.d32 = 0 }; -+ -+ if (DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) { -+ DWC_PRINTF("No free channel to select for LPM transaction\n"); -+ return -1; -+ } -+ -+ hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list); -+ -+ /* Mask host channel interrupts. */ -+ gintmsk.b.hcintr = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0); -+ -+ /* Fill fields that core needs for LPM transaction */ -+ hcchar.b.devaddr = devaddr; -+ hcchar.b.epnum = 0; -+ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL; -+ hcchar.b.mps = 64; -+ hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW); -+ hcchar.b.epdir = 0; /* OUT */ -+ DWC_WRITE_REG32(&core_if->host_if->hc_regs[hc->hc_num]->hcchar, -+ hcchar.d32); -+ -+ /* Remove the host channel from the free list. */ -+ DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry); -+ -+ DWC_PRINTF("hcnum = %d devaddr = %d\n", hc->hc_num, devaddr); -+ -+ return hc->hc_num; -+} -+ -+/** Release hc after performing LPM transaction */ -+void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd) -+{ -+ dwc_hc_t *hc; -+ glpmcfg_data_t lpmcfg; -+ uint8_t hc_num; -+ -+ lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg); -+ hc_num = lpmcfg.b.lpm_chan_index; -+ -+ hc = hcd->hc_ptr_array[hc_num]; -+ -+ DWC_PRINTF("Freeing channel %d after LPM\n", hc_num); -+ /* Return host channel to free list */ -+ DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry); -+} -+ -+int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr, uint8_t hird, -+ uint8_t bRemoteWake) -+{ -+ glpmcfg_data_t lpmcfg; -+ pcgcctl_data_t pcgcctl = {.d32 = 0 }; -+ int channel; -+ -+ channel = dwc_otg_hcd_get_hc_for_lpm_tran(hcd, devaddr); -+ if (channel < 0) { -+ return channel; -+ } -+ -+ pcgcctl.b.enbl_sleep_gating = 1; -+ DWC_MODIFY_REG32(hcd->core_if->pcgcctl, 0, pcgcctl.d32); -+ -+ /* Read LPM config register */ -+ lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg); -+ -+ /* Program LPM transaction fields */ -+ lpmcfg.b.rem_wkup_en = bRemoteWake; -+ lpmcfg.b.hird = hird; -+ lpmcfg.b.hird_thres = 0x1c; -+ lpmcfg.b.lpm_chan_index = channel; -+ lpmcfg.b.en_utmi_sleep = 1; -+ /* Program LPM config register */ -+ DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32); -+ -+ /* Send LPM transaction */ -+ lpmcfg.b.send_lpm = 1; -+ DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32); -+ -+ return 0; -+} -+ -+#endif /* CONFIG_USB_DWC_OTG_LPM */ -+ -+int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port) -+{ -+ int retval; -+ -+ if (port != 1) { -+ return -DWC_E_INVALID; -+ } -+ -+ retval = (hcd->flags.b.port_connect_status_change || -+ hcd->flags.b.port_reset_change || -+ hcd->flags.b.port_enable_change || -+ hcd->flags.b.port_suspend_change || -+ hcd->flags.b.port_over_current_change); -+#ifdef DEBUG -+ if (retval) { -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:" -+ " Root port status changed\n"); -+ DWC_DEBUGPL(DBG_HCDV, " port_connect_status_change: %d\n", -+ hcd->flags.b.port_connect_status_change); -+ DWC_DEBUGPL(DBG_HCDV, " port_reset_change: %d\n", -+ hcd->flags.b.port_reset_change); -+ DWC_DEBUGPL(DBG_HCDV, " port_enable_change: %d\n", -+ hcd->flags.b.port_enable_change); -+ DWC_DEBUGPL(DBG_HCDV, " port_suspend_change: %d\n", -+ hcd->flags.b.port_suspend_change); -+ DWC_DEBUGPL(DBG_HCDV, " port_over_current_change: %d\n", -+ hcd->flags.b.port_over_current_change); -+ } -+#endif -+ return retval; -+} -+ -+int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * dwc_otg_hcd) -+{ -+ hfnum_data_t hfnum; -+ hfnum.d32 = -+ DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->host_global_regs-> -+ hfnum); -+ -+#ifdef DEBUG_SOF -+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n", -+ hfnum.b.frnum); -+#endif -+ return hfnum.b.frnum; -+} -+ -+int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd, -+ struct dwc_otg_hcd_function_ops *fops) -+{ -+ int retval = 0; -+ -+ hcd->fops = fops; -+ if (!dwc_otg_is_device_mode(hcd->core_if) && -+ (!hcd->core_if->adp_enable || hcd->core_if->adp.adp_started)) { -+ dwc_otg_hcd_reinit(hcd); -+ } else { -+ retval = -DWC_E_NO_DEVICE; -+ } -+ -+ return retval; -+} -+ -+void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd) -+{ -+ return hcd->priv; -+} -+ -+void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data) -+{ -+ hcd->priv = priv_data; -+} -+ -+uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd) -+{ -+ return hcd->otg_port; -+} -+ -+uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd) -+{ -+ uint32_t is_b_host; -+ if (hcd->core_if->op_state == B_HOST) { -+ is_b_host = 1; -+ } else { -+ is_b_host = 0; -+ } -+ -+ return is_b_host; -+} -+ -+dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd, -+ int iso_desc_count, int atomic_alloc) -+{ -+ dwc_otg_hcd_urb_t *dwc_otg_urb; -+ uint32_t size; -+ -+ size = -+ sizeof(*dwc_otg_urb) + -+ iso_desc_count * sizeof(struct dwc_otg_hcd_iso_packet_desc); -+ if (atomic_alloc) -+ dwc_otg_urb = DWC_ALLOC_ATOMIC(size); -+ else -+ dwc_otg_urb = DWC_ALLOC(size); -+ -+ if (dwc_otg_urb) -+ dwc_otg_urb->packet_count = iso_desc_count; -+ else { -+ DWC_ERROR("**** DWC OTG HCD URB alloc - " -+ "%salloc of %db failed\n", -+ atomic_alloc?"atomic ":"", size); -+ } -+ return dwc_otg_urb; -+} -+ -+void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * dwc_otg_urb, -+ uint8_t dev_addr, uint8_t ep_num, -+ uint8_t ep_type, uint8_t ep_dir, uint16_t mps) -+{ -+ dwc_otg_hcd_fill_pipe(&dwc_otg_urb->pipe_info, dev_addr, ep_num, -+ ep_type, ep_dir, mps); -+#if 0 -+ DWC_PRINTF -+ ("addr = %d, ep_num = %d, ep_dir = 0x%x, ep_type = 0x%x, mps = %d\n", -+ dev_addr, ep_num, ep_dir, ep_type, mps); -+#endif -+} -+ -+void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * dwc_otg_urb, -+ void *urb_handle, void *buf, dwc_dma_t dma, -+ uint32_t buflen, void *setup_packet, -+ dwc_dma_t setup_dma, uint32_t flags, -+ uint16_t interval) -+{ -+ dwc_otg_urb->priv = urb_handle; -+ dwc_otg_urb->buf = buf; -+ dwc_otg_urb->dma = dma; -+ dwc_otg_urb->length = buflen; -+ dwc_otg_urb->setup_packet = setup_packet; -+ dwc_otg_urb->setup_dma = setup_dma; -+ dwc_otg_urb->flags = flags; -+ dwc_otg_urb->interval = interval; -+ dwc_otg_urb->status = -DWC_E_IN_PROGRESS; -+} -+ -+uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb) -+{ -+ return dwc_otg_urb->status; -+} -+ -+uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t * dwc_otg_urb) -+{ -+ return dwc_otg_urb->actual_length; -+} -+ -+uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t * dwc_otg_urb) -+{ -+ return dwc_otg_urb->error_count; -+} -+ -+void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb, -+ int desc_num, uint32_t offset, -+ uint32_t length) -+{ -+ dwc_otg_urb->iso_descs[desc_num].offset = offset; -+ dwc_otg_urb->iso_descs[desc_num].length = length; -+} -+ -+uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t * dwc_otg_urb, -+ int desc_num) -+{ -+ return dwc_otg_urb->iso_descs[desc_num].status; -+} -+ -+uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t * -+ dwc_otg_urb, int desc_num) -+{ -+ return dwc_otg_urb->iso_descs[desc_num].actual_length; -+} -+ -+int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd, void *ep_handle) -+{ -+ int allocated = 0; -+ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle; -+ -+ if (qh) { -+ if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) { -+ allocated = 1; -+ } -+ } -+ return allocated; -+} -+ -+int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle) -+{ -+ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle; -+ int freed = 0; -+ DWC_ASSERT(qh, "qh is not allocated\n"); -+ -+ if (DWC_LIST_EMPTY(&qh->qh_list_entry)) { -+ freed = 1; -+ } -+ -+ return freed; -+} -+ -+uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd, void *ep_handle) -+{ -+ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle; -+ DWC_ASSERT(qh, "qh is not allocated\n"); -+ return qh->usecs; -+} -+ -+void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd) -+{ -+#ifdef DEBUG -+ int num_channels; -+ int i; -+ gnptxsts_data_t np_tx_status; -+ hptxsts_data_t p_tx_status; -+ -+ num_channels = hcd->core_if->core_params->host_channels; -+ DWC_PRINTF("\n"); -+ DWC_PRINTF -+ ("************************************************************\n"); -+ DWC_PRINTF("HCD State:\n"); -+ DWC_PRINTF(" Num channels: %d\n", num_channels); -+ for (i = 0; i < num_channels; i++) { -+ dwc_hc_t *hc = hcd->hc_ptr_array[i]; -+ DWC_PRINTF(" Channel %d:\n", i); -+ DWC_PRINTF(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n", -+ hc->dev_addr, hc->ep_num, hc->ep_is_in); -+ DWC_PRINTF(" speed: %d\n", hc->speed); -+ DWC_PRINTF(" ep_type: %d\n", hc->ep_type); -+ DWC_PRINTF(" max_packet: %d\n", hc->max_packet); -+ DWC_PRINTF(" data_pid_start: %d\n", hc->data_pid_start); -+ DWC_PRINTF(" multi_count: %d\n", hc->multi_count); -+ DWC_PRINTF(" xfer_started: %d\n", hc->xfer_started); -+ DWC_PRINTF(" xfer_buff: %p\n", hc->xfer_buff); -+ DWC_PRINTF(" xfer_len: %d\n", hc->xfer_len); -+ DWC_PRINTF(" xfer_count: %d\n", hc->xfer_count); -+ DWC_PRINTF(" halt_on_queue: %d\n", hc->halt_on_queue); -+ DWC_PRINTF(" halt_pending: %d\n", hc->halt_pending); -+ DWC_PRINTF(" halt_status: %d\n", hc->halt_status); -+ DWC_PRINTF(" do_split: %d\n", hc->do_split); -+ DWC_PRINTF(" complete_split: %d\n", hc->complete_split); -+ DWC_PRINTF(" hub_addr: %d\n", hc->hub_addr); -+ DWC_PRINTF(" port_addr: %d\n", hc->port_addr); -+ DWC_PRINTF(" xact_pos: %d\n", hc->xact_pos); -+ DWC_PRINTF(" requests: %d\n", hc->requests); -+ DWC_PRINTF(" qh: %p\n", hc->qh); -+ if (hc->xfer_started) { -+ hfnum_data_t hfnum; -+ hcchar_data_t hcchar; -+ hctsiz_data_t hctsiz; -+ hcint_data_t hcint; -+ hcintmsk_data_t hcintmsk; -+ hfnum.d32 = -+ DWC_READ_REG32(&hcd->core_if-> -+ host_if->host_global_regs->hfnum); -+ hcchar.d32 = -+ DWC_READ_REG32(&hcd->core_if->host_if-> -+ hc_regs[i]->hcchar); -+ hctsiz.d32 = -+ DWC_READ_REG32(&hcd->core_if->host_if-> -+ hc_regs[i]->hctsiz); -+ hcint.d32 = -+ DWC_READ_REG32(&hcd->core_if->host_if-> -+ hc_regs[i]->hcint); -+ hcintmsk.d32 = -+ DWC_READ_REG32(&hcd->core_if->host_if-> -+ hc_regs[i]->hcintmsk); -+ DWC_PRINTF(" hfnum: 0x%08x\n", hfnum.d32); -+ DWC_PRINTF(" hcchar: 0x%08x\n", hcchar.d32); -+ DWC_PRINTF(" hctsiz: 0x%08x\n", hctsiz.d32); -+ DWC_PRINTF(" hcint: 0x%08x\n", hcint.d32); -+ DWC_PRINTF(" hcintmsk: 0x%08x\n", hcintmsk.d32); -+ } -+ if (hc->xfer_started && hc->qh) { -+ dwc_otg_qtd_t *qtd; -+ dwc_otg_hcd_urb_t *urb; -+ -+ DWC_CIRCLEQ_FOREACH(qtd, &hc->qh->qtd_list, qtd_list_entry) { -+ if (!qtd->in_process) -+ break; -+ -+ urb = qtd->urb; -+ DWC_PRINTF(" URB Info:\n"); -+ DWC_PRINTF(" qtd: %p, urb: %p\n", qtd, urb); -+ if (urb) { -+ DWC_PRINTF(" Dev: %d, EP: %d %s\n", -+ dwc_otg_hcd_get_dev_addr(&urb-> -+ pipe_info), -+ dwc_otg_hcd_get_ep_num(&urb-> -+ pipe_info), -+ dwc_otg_hcd_is_pipe_in(&urb-> -+ pipe_info) ? -+ "IN" : "OUT"); -+ DWC_PRINTF(" Max packet size: %d\n", -+ dwc_otg_hcd_get_mps(&urb-> -+ pipe_info)); -+ DWC_PRINTF(" transfer_buffer: %p\n", -+ urb->buf); -+ DWC_PRINTF(" transfer_dma: %p\n", -+ (void *)urb->dma); -+ DWC_PRINTF(" transfer_buffer_length: %d\n", -+ urb->length); -+ DWC_PRINTF(" actual_length: %d\n", -+ urb->actual_length); -+ } -+ } -+ } -+ } -+ DWC_PRINTF(" non_periodic_channels: %d\n", hcd->non_periodic_channels); -+ DWC_PRINTF(" periodic_channels: %d\n", hcd->periodic_channels); -+ DWC_PRINTF(" periodic_usecs: %d\n", hcd->periodic_usecs); -+ np_tx_status.d32 = -+ DWC_READ_REG32(&hcd->core_if->core_global_regs->gnptxsts); -+ DWC_PRINTF(" NP Tx Req Queue Space Avail: %d\n", -+ np_tx_status.b.nptxqspcavail); -+ DWC_PRINTF(" NP Tx FIFO Space Avail: %d\n", -+ np_tx_status.b.nptxfspcavail); -+ p_tx_status.d32 = -+ DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hptxsts); -+ DWC_PRINTF(" P Tx Req Queue Space Avail: %d\n", -+ p_tx_status.b.ptxqspcavail); -+ DWC_PRINTF(" P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail); -+ dwc_otg_hcd_dump_frrem(hcd); -+ dwc_otg_dump_global_registers(hcd->core_if); -+ dwc_otg_dump_host_registers(hcd->core_if); -+ DWC_PRINTF -+ ("************************************************************\n"); -+ DWC_PRINTF("\n"); -+#endif -+} -+ -+#ifdef DEBUG -+void dwc_print_setup_data(uint8_t * setup) -+{ -+ int i; -+ if (CHK_DEBUG_LEVEL(DBG_HCD)) { -+ DWC_PRINTF("Setup Data = MSB "); -+ for (i = 7; i >= 0; i--) -+ DWC_PRINTF("%02x ", setup[i]); -+ DWC_PRINTF("\n"); -+ DWC_PRINTF(" bmRequestType Tranfer = %s\n", -+ (setup[0] & 0x80) ? "Device-to-Host" : -+ "Host-to-Device"); -+ DWC_PRINTF(" bmRequestType Type = "); -+ switch ((setup[0] & 0x60) >> 5) { -+ case 0: -+ DWC_PRINTF("Standard\n"); -+ break; -+ case 1: -+ DWC_PRINTF("Class\n"); -+ break; -+ case 2: -+ DWC_PRINTF("Vendor\n"); -+ break; -+ case 3: -+ DWC_PRINTF("Reserved\n"); -+ break; -+ } -+ DWC_PRINTF(" bmRequestType Recipient = "); -+ switch (setup[0] & 0x1f) { -+ case 0: -+ DWC_PRINTF("Device\n"); -+ break; -+ case 1: -+ DWC_PRINTF("Interface\n"); -+ break; -+ case 2: -+ DWC_PRINTF("Endpoint\n"); -+ break; -+ case 3: -+ DWC_PRINTF("Other\n"); -+ break; -+ default: -+ DWC_PRINTF("Reserved\n"); -+ break; -+ } -+ DWC_PRINTF(" bRequest = 0x%0x\n", setup[1]); -+ DWC_PRINTF(" wValue = 0x%0x\n", *((uint16_t *) & setup[2])); -+ DWC_PRINTF(" wIndex = 0x%0x\n", *((uint16_t *) & setup[4])); -+ DWC_PRINTF(" wLength = 0x%0x\n\n", *((uint16_t *) & setup[6])); -+ } -+} -+#endif -+ -+void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd) -+{ -+#if 0 -+ DWC_PRINTF("Frame remaining at SOF:\n"); -+ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", -+ hcd->frrem_samples, hcd->frrem_accum, -+ (hcd->frrem_samples > 0) ? -+ hcd->frrem_accum / hcd->frrem_samples : 0); -+ -+ DWC_PRINTF("\n"); -+ DWC_PRINTF("Frame remaining at start_transfer (uframe 7):\n"); -+ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", -+ hcd->core_if->hfnum_7_samples, -+ hcd->core_if->hfnum_7_frrem_accum, -+ (hcd->core_if->hfnum_7_samples > -+ 0) ? hcd->core_if->hfnum_7_frrem_accum / -+ hcd->core_if->hfnum_7_samples : 0); -+ DWC_PRINTF("Frame remaining at start_transfer (uframe 0):\n"); -+ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", -+ hcd->core_if->hfnum_0_samples, -+ hcd->core_if->hfnum_0_frrem_accum, -+ (hcd->core_if->hfnum_0_samples > -+ 0) ? hcd->core_if->hfnum_0_frrem_accum / -+ hcd->core_if->hfnum_0_samples : 0); -+ DWC_PRINTF("Frame remaining at start_transfer (uframe 1-6):\n"); -+ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", -+ hcd->core_if->hfnum_other_samples, -+ hcd->core_if->hfnum_other_frrem_accum, -+ (hcd->core_if->hfnum_other_samples > -+ 0) ? hcd->core_if->hfnum_other_frrem_accum / -+ hcd->core_if->hfnum_other_samples : 0); -+ -+ DWC_PRINTF("\n"); -+ DWC_PRINTF("Frame remaining at sample point A (uframe 7):\n"); -+ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", -+ hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a, -+ (hcd->hfnum_7_samples_a > 0) ? -+ hcd->hfnum_7_frrem_accum_a / hcd->hfnum_7_samples_a : 0); -+ DWC_PRINTF("Frame remaining at sample point A (uframe 0):\n"); -+ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", -+ hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a, -+ (hcd->hfnum_0_samples_a > 0) ? -+ hcd->hfnum_0_frrem_accum_a / hcd->hfnum_0_samples_a : 0); -+ DWC_PRINTF("Frame remaining at sample point A (uframe 1-6):\n"); -+ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", -+ hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a, -+ (hcd->hfnum_other_samples_a > 0) ? -+ hcd->hfnum_other_frrem_accum_a / -+ hcd->hfnum_other_samples_a : 0); -+ -+ DWC_PRINTF("\n"); -+ DWC_PRINTF("Frame remaining at sample point B (uframe 7):\n"); -+ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", -+ hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b, -+ (hcd->hfnum_7_samples_b > 0) ? -+ hcd->hfnum_7_frrem_accum_b / hcd->hfnum_7_samples_b : 0); -+ DWC_PRINTF("Frame remaining at sample point B (uframe 0):\n"); -+ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", -+ hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b, -+ (hcd->hfnum_0_samples_b > 0) ? -+ hcd->hfnum_0_frrem_accum_b / hcd->hfnum_0_samples_b : 0); -+ DWC_PRINTF("Frame remaining at sample point B (uframe 1-6):\n"); -+ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", -+ hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b, -+ (hcd->hfnum_other_samples_b > 0) ? -+ hcd->hfnum_other_frrem_accum_b / -+ hcd->hfnum_other_samples_b : 0); -+#endif -+} -+ -+#endif /* DWC_DEVICE_ONLY */ -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c 2015-11-29 09:42:39.919098694 +0100 -@@ -0,0 +1,1132 @@ -+/*========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_ddma.c $ -+ * $Revision: #10 $ -+ * $Date: 2011/10/20 $ -+ * $Change: 1869464 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+#ifndef DWC_DEVICE_ONLY -+ -+/** @file -+ * This file contains Descriptor DMA support implementation for host mode. -+ */ -+ -+#include "dwc_otg_hcd.h" -+#include "dwc_otg_regs.h" -+ -+extern bool microframe_schedule; -+ -+static inline uint8_t frame_list_idx(uint16_t frame) -+{ -+ return (frame & (MAX_FRLIST_EN_NUM - 1)); -+} -+ -+static inline uint16_t desclist_idx_inc(uint16_t idx, uint16_t inc, uint8_t speed) -+{ -+ return (idx + inc) & -+ (((speed == -+ DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC : -+ MAX_DMA_DESC_NUM_GENERIC) - 1); -+} -+ -+static inline uint16_t desclist_idx_dec(uint16_t idx, uint16_t inc, uint8_t speed) -+{ -+ return (idx - inc) & -+ (((speed == -+ DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC : -+ MAX_DMA_DESC_NUM_GENERIC) - 1); -+} -+ -+static inline uint16_t max_desc_num(dwc_otg_qh_t * qh) -+{ -+ return (((qh->ep_type == UE_ISOCHRONOUS) -+ && (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH)) -+ ? MAX_DMA_DESC_NUM_HS_ISOC : MAX_DMA_DESC_NUM_GENERIC); -+} -+static inline uint16_t frame_incr_val(dwc_otg_qh_t * qh) -+{ -+ return ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) -+ ? ((qh->interval + 8 - 1) / 8) -+ : qh->interval); -+} -+ -+static int desc_list_alloc(dwc_otg_qh_t * qh) -+{ -+ int retval = 0; -+ -+ qh->desc_list = (dwc_otg_host_dma_desc_t *) -+ DWC_DMA_ALLOC(sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh), -+ &qh->desc_list_dma); -+ -+ if (!qh->desc_list) { -+ retval = -DWC_E_NO_MEMORY; -+ DWC_ERROR("%s: DMA descriptor list allocation failed\n", __func__); -+ -+ } -+ -+ dwc_memset(qh->desc_list, 0x00, -+ sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh)); -+ -+ qh->n_bytes = -+ (uint32_t *) DWC_ALLOC(sizeof(uint32_t) * max_desc_num(qh)); -+ -+ if (!qh->n_bytes) { -+ retval = -DWC_E_NO_MEMORY; -+ DWC_ERROR -+ ("%s: Failed to allocate array for descriptors' size actual values\n", -+ __func__); -+ -+ } -+ return retval; -+ -+} -+ -+static void desc_list_free(dwc_otg_qh_t * qh) -+{ -+ if (qh->desc_list) { -+ DWC_DMA_FREE(max_desc_num(qh), qh->desc_list, -+ qh->desc_list_dma); -+ qh->desc_list = NULL; -+ } -+ -+ if (qh->n_bytes) { -+ DWC_FREE(qh->n_bytes); -+ qh->n_bytes = NULL; -+ } -+} -+ -+static int frame_list_alloc(dwc_otg_hcd_t * hcd) -+{ -+ int retval = 0; -+ if (hcd->frame_list) -+ return 0; -+ -+ hcd->frame_list = DWC_DMA_ALLOC(4 * MAX_FRLIST_EN_NUM, -+ &hcd->frame_list_dma); -+ if (!hcd->frame_list) { -+ retval = -DWC_E_NO_MEMORY; -+ DWC_ERROR("%s: Frame List allocation failed\n", __func__); -+ } -+ -+ dwc_memset(hcd->frame_list, 0x00, 4 * MAX_FRLIST_EN_NUM); -+ -+ return retval; -+} -+ -+static void frame_list_free(dwc_otg_hcd_t * hcd) -+{ -+ if (!hcd->frame_list) -+ return; -+ -+ DWC_DMA_FREE(4 * MAX_FRLIST_EN_NUM, hcd->frame_list, hcd->frame_list_dma); -+ hcd->frame_list = NULL; -+} -+ -+static void per_sched_enable(dwc_otg_hcd_t * hcd, uint16_t fr_list_en) -+{ -+ -+ hcfg_data_t hcfg; -+ -+ hcfg.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hcfg); -+ -+ if (hcfg.b.perschedena) { -+ /* already enabled */ -+ return; -+ } -+ -+ DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hflbaddr, -+ hcd->frame_list_dma); -+ -+ switch (fr_list_en) { -+ case 64: -+ hcfg.b.frlisten = 3; -+ break; -+ case 32: -+ hcfg.b.frlisten = 2; -+ break; -+ case 16: -+ hcfg.b.frlisten = 1; -+ break; -+ case 8: -+ hcfg.b.frlisten = 0; -+ break; -+ default: -+ break; -+ } -+ -+ hcfg.b.perschedena = 1; -+ -+ DWC_DEBUGPL(DBG_HCD, "Enabling Periodic schedule\n"); -+ DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32); -+ -+} -+ -+static void per_sched_disable(dwc_otg_hcd_t * hcd) -+{ -+ hcfg_data_t hcfg; -+ -+ hcfg.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hcfg); -+ -+ if (!hcfg.b.perschedena) { -+ /* already disabled */ -+ return; -+ } -+ hcfg.b.perschedena = 0; -+ -+ DWC_DEBUGPL(DBG_HCD, "Disabling Periodic schedule\n"); -+ DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32); -+} -+ -+/* -+ * Activates/Deactivates FrameList entries for the channel -+ * based on endpoint servicing period. -+ */ -+void update_frame_list(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, uint8_t enable) -+{ -+ uint16_t i, j, inc; -+ dwc_hc_t *hc = NULL; -+ -+ if (!qh->channel) { -+ DWC_ERROR("qh->channel = %p", qh->channel); -+ return; -+ } -+ -+ if (!hcd) { -+ DWC_ERROR("------hcd = %p", hcd); -+ return; -+ } -+ -+ if (!hcd->frame_list) { -+ DWC_ERROR("-------hcd->frame_list = %p", hcd->frame_list); -+ return; -+ } -+ -+ hc = qh->channel; -+ inc = frame_incr_val(qh); -+ if (qh->ep_type == UE_ISOCHRONOUS) -+ i = frame_list_idx(qh->sched_frame); -+ else -+ i = 0; -+ -+ j = i; -+ do { -+ if (enable) -+ hcd->frame_list[j] |= (1 << hc->hc_num); -+ else -+ hcd->frame_list[j] &= ~(1 << hc->hc_num); -+ j = (j + inc) & (MAX_FRLIST_EN_NUM - 1); -+ } -+ while (j != i); -+ if (!enable) -+ return; -+ hc->schinfo = 0; -+ if (qh->channel->speed == DWC_OTG_EP_SPEED_HIGH) { -+ j = 1; -+ /* TODO - check this */ -+ inc = (8 + qh->interval - 1) / qh->interval; -+ for (i = 0; i < inc; i++) { -+ hc->schinfo |= j; -+ j = j << qh->interval; -+ } -+ } else { -+ hc->schinfo = 0xff; -+ } -+} -+ -+#if 1 -+void dump_frame_list(dwc_otg_hcd_t * hcd) -+{ -+ int i = 0; -+ DWC_PRINTF("--FRAME LIST (hex) --\n"); -+ for (i = 0; i < MAX_FRLIST_EN_NUM; i++) { -+ DWC_PRINTF("%x\t", hcd->frame_list[i]); -+ if (!(i % 8) && i) -+ DWC_PRINTF("\n"); -+ } -+ DWC_PRINTF("\n----\n"); -+ -+} -+#endif -+ -+static void release_channel_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) -+{ -+ dwc_irqflags_t flags; -+ dwc_spinlock_t *channel_lock = hcd->channel_lock; -+ -+ dwc_hc_t *hc = qh->channel; -+ if (dwc_qh_is_non_per(qh)) { -+ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags); -+ if (!microframe_schedule) -+ hcd->non_periodic_channels--; -+ else -+ hcd->available_host_channels++; -+ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); -+ } else -+ update_frame_list(hcd, qh, 0); -+ -+ /* -+ * The condition is added to prevent double cleanup try in case of device -+ * disconnect. See channel cleanup in dwc_otg_hcd_disconnect_cb(). -+ */ -+ if (hc->qh) { -+ dwc_otg_hc_cleanup(hcd->core_if, hc); -+ DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry); -+ hc->qh = NULL; -+ } -+ -+ qh->channel = NULL; -+ qh->ntd = 0; -+ -+ if (qh->desc_list) { -+ dwc_memset(qh->desc_list, 0x00, -+ sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh)); -+ } -+} -+ -+/** -+ * Initializes a QH structure's Descriptor DMA related members. -+ * Allocates memory for descriptor list. -+ * On first periodic QH, allocates memory for FrameList -+ * and enables periodic scheduling. -+ * -+ * @param hcd The HCD state structure for the DWC OTG controller. -+ * @param qh The QH to init. -+ * -+ * @return 0 if successful, negative error code otherwise. -+ */ -+int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) -+{ -+ int retval = 0; -+ -+ if (qh->do_split) { -+ DWC_ERROR("SPLIT Transfers are not supported in Descriptor DMA.\n"); -+ return -1; -+ } -+ -+ retval = desc_list_alloc(qh); -+ -+ if ((retval == 0) -+ && (qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT)) { -+ if (!hcd->frame_list) { -+ retval = frame_list_alloc(hcd); -+ /* Enable periodic schedule on first periodic QH */ -+ if (retval == 0) -+ per_sched_enable(hcd, MAX_FRLIST_EN_NUM); -+ } -+ } -+ -+ qh->ntd = 0; -+ -+ return retval; -+} -+ -+/** -+ * Frees descriptor list memory associated with the QH. -+ * If QH is periodic and the last, frees FrameList memory -+ * and disables periodic scheduling. -+ * -+ * @param hcd The HCD state structure for the DWC OTG controller. -+ * @param qh The QH to init. -+ */ -+void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) -+{ -+ desc_list_free(qh); -+ -+ /* -+ * Channel still assigned due to some reasons. -+ * Seen on Isoc URB dequeue. Channel halted but no subsequent -+ * ChHalted interrupt to release the channel. Afterwards -+ * when it comes here from endpoint disable routine -+ * channel remains assigned. -+ */ -+ if (qh->channel) -+ release_channel_ddma(hcd, qh); -+ -+ if ((qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT) -+ && (microframe_schedule || !hcd->periodic_channels) && hcd->frame_list) { -+ -+ per_sched_disable(hcd); -+ frame_list_free(hcd); -+ } -+} -+ -+static uint8_t frame_to_desc_idx(dwc_otg_qh_t * qh, uint16_t frame_idx) -+{ -+ if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) { -+ /* -+ * Descriptor set(8 descriptors) index -+ * which is 8-aligned. -+ */ -+ return (frame_idx & ((MAX_DMA_DESC_NUM_HS_ISOC / 8) - 1)) * 8; -+ } else { -+ return (frame_idx & (MAX_DMA_DESC_NUM_GENERIC - 1)); -+ } -+} -+ -+/* -+ * Determine starting frame for Isochronous transfer. -+ * Few frames skipped to prevent race condition with HC. -+ */ -+static uint8_t calc_starting_frame(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, -+ uint8_t * skip_frames) -+{ -+ uint16_t frame = 0; -+ hcd->frame_number = dwc_otg_hcd_get_frame_number(hcd); -+ -+ /* sched_frame is always frame number(not uFrame) both in FS and HS !! */ -+ -+ /* -+ * skip_frames is used to limit activated descriptors number -+ * to avoid the situation when HC services the last activated -+ * descriptor firstly. -+ * Example for FS: -+ * Current frame is 1, scheduled frame is 3. Since HC always fetches the descriptor -+ * corresponding to curr_frame+1, the descriptor corresponding to frame 2 -+ * will be fetched. If the number of descriptors is max=64 (or greather) the -+ * list will be fully programmed with Active descriptors and it is possible -+ * case(rare) that the latest descriptor(considering rollback) corresponding -+ * to frame 2 will be serviced first. HS case is more probable because, in fact, -+ * up to 11 uframes(16 in the code) may be skipped. -+ */ -+ if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) { -+ /* -+ * Consider uframe counter also, to start xfer asap. -+ * If half of the frame elapsed skip 2 frames otherwise -+ * just 1 frame. -+ * Starting descriptor index must be 8-aligned, so -+ * if the current frame is near to complete the next one -+ * is skipped as well. -+ */ -+ -+ if (dwc_micro_frame_num(hcd->frame_number) >= 5) { -+ *skip_frames = 2 * 8; -+ frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames); -+ } else { -+ *skip_frames = 1 * 8; -+ frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames); -+ } -+ -+ frame = dwc_full_frame_num(frame); -+ } else { -+ /* -+ * Two frames are skipped for FS - the current and the next. -+ * But for descriptor programming, 1 frame(descriptor) is enough, -+ * see example above. -+ */ -+ *skip_frames = 1; -+ frame = dwc_frame_num_inc(hcd->frame_number, 2); -+ } -+ -+ return frame; -+} -+ -+/* -+ * Calculate initial descriptor index for isochronous transfer -+ * based on scheduled frame. -+ */ -+static uint8_t recalc_initial_desc_idx(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) -+{ -+ uint16_t frame = 0, fr_idx, fr_idx_tmp; -+ uint8_t skip_frames = 0; -+ /* -+ * With current ISOC processing algorithm the channel is being -+ * released when no more QTDs in the list(qh->ntd == 0). -+ * Thus this function is called only when qh->ntd == 0 and qh->channel == 0. -+ * -+ * So qh->channel != NULL branch is not used and just not removed from the -+ * source file. It is required for another possible approach which is, -+ * do not disable and release the channel when ISOC session completed, -+ * just move QH to inactive schedule until new QTD arrives. -+ * On new QTD, the QH moved back to 'ready' schedule, -+ * starting frame and therefore starting desc_index are recalculated. -+ * In this case channel is released only on ep_disable. -+ */ -+ -+ /* Calculate starting descriptor index. For INTERRUPT endpoint it is always 0. */ -+ if (qh->channel) { -+ frame = calc_starting_frame(hcd, qh, &skip_frames); -+ /* -+ * Calculate initial descriptor index based on FrameList current bitmap -+ * and servicing period. -+ */ -+ fr_idx_tmp = frame_list_idx(frame); -+ fr_idx = -+ (MAX_FRLIST_EN_NUM + frame_list_idx(qh->sched_frame) - -+ fr_idx_tmp) -+ % frame_incr_val(qh); -+ fr_idx = (fr_idx + fr_idx_tmp) % MAX_FRLIST_EN_NUM; -+ } else { -+ qh->sched_frame = calc_starting_frame(hcd, qh, &skip_frames); -+ fr_idx = frame_list_idx(qh->sched_frame); -+ } -+ -+ qh->td_first = qh->td_last = frame_to_desc_idx(qh, fr_idx); -+ -+ return skip_frames; -+} -+ -+#define ISOC_URB_GIVEBACK_ASAP -+ -+#define MAX_ISOC_XFER_SIZE_FS 1023 -+#define MAX_ISOC_XFER_SIZE_HS 3072 -+#define DESCNUM_THRESHOLD 4 -+ -+static void init_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, -+ uint8_t skip_frames) -+{ -+ struct dwc_otg_hcd_iso_packet_desc *frame_desc; -+ dwc_otg_qtd_t *qtd; -+ dwc_otg_host_dma_desc_t *dma_desc; -+ uint16_t idx, inc, n_desc, ntd_max, max_xfer_size; -+ -+ idx = qh->td_last; -+ inc = qh->interval; -+ n_desc = 0; -+ -+ ntd_max = (max_desc_num(qh) + qh->interval - 1) / qh->interval; -+ if (skip_frames && !qh->channel) -+ ntd_max = ntd_max - skip_frames / qh->interval; -+ -+ max_xfer_size = -+ (qh->dev_speed == -+ DWC_OTG_EP_SPEED_HIGH) ? MAX_ISOC_XFER_SIZE_HS : -+ MAX_ISOC_XFER_SIZE_FS; -+ -+ DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) { -+ while ((qh->ntd < ntd_max) -+ && (qtd->isoc_frame_index_last < -+ qtd->urb->packet_count)) { -+ -+ dma_desc = &qh->desc_list[idx]; -+ dwc_memset(dma_desc, 0x00, sizeof(dwc_otg_host_dma_desc_t)); -+ -+ frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index_last]; -+ -+ if (frame_desc->length > max_xfer_size) -+ qh->n_bytes[idx] = max_xfer_size; -+ else -+ qh->n_bytes[idx] = frame_desc->length; -+ dma_desc->status.b_isoc.n_bytes = qh->n_bytes[idx]; -+ dma_desc->status.b_isoc.a = 1; -+ dma_desc->status.b_isoc.sts = 0; -+ -+ dma_desc->buf = qtd->urb->dma + frame_desc->offset; -+ -+ qh->ntd++; -+ -+ qtd->isoc_frame_index_last++; -+ -+#ifdef ISOC_URB_GIVEBACK_ASAP -+ /* -+ * Set IOC for each descriptor corresponding to the -+ * last frame of the URB. -+ */ -+ if (qtd->isoc_frame_index_last == -+ qtd->urb->packet_count) -+ dma_desc->status.b_isoc.ioc = 1; -+ -+#endif -+ idx = desclist_idx_inc(idx, inc, qh->dev_speed); -+ n_desc++; -+ -+ } -+ qtd->in_process = 1; -+ } -+ -+ qh->td_last = idx; -+ -+#ifdef ISOC_URB_GIVEBACK_ASAP -+ /* Set IOC for the last descriptor if descriptor list is full */ -+ if (qh->ntd == ntd_max) { -+ idx = desclist_idx_dec(qh->td_last, inc, qh->dev_speed); -+ qh->desc_list[idx].status.b_isoc.ioc = 1; -+ } -+#else -+ /* -+ * Set IOC bit only for one descriptor. -+ * Always try to be ahead of HW processing, -+ * i.e. on IOC generation driver activates next descriptors but -+ * core continues to process descriptors followed the one with IOC set. -+ */ -+ -+ if (n_desc > DESCNUM_THRESHOLD) { -+ /* -+ * Move IOC "up". Required even if there is only one QTD -+ * in the list, cause QTDs migth continue to be queued, -+ * but during the activation it was only one queued. -+ * Actually more than one QTD might be in the list if this function called -+ * from XferCompletion - QTDs was queued during HW processing of the previous -+ * descriptor chunk. -+ */ -+ idx = dwc_desclist_idx_dec(idx, inc * ((qh->ntd + 1) / 2), qh->dev_speed); -+ } else { -+ /* -+ * Set the IOC for the latest descriptor -+ * if either number of descriptor is not greather than threshold -+ * or no more new descriptors activated. -+ */ -+ idx = dwc_desclist_idx_dec(qh->td_last, inc, qh->dev_speed); -+ } -+ -+ qh->desc_list[idx].status.b_isoc.ioc = 1; -+#endif -+} -+ -+static void init_non_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) -+{ -+ -+ dwc_hc_t *hc; -+ dwc_otg_host_dma_desc_t *dma_desc; -+ dwc_otg_qtd_t *qtd; -+ int num_packets, len, n_desc = 0; -+ -+ hc = qh->channel; -+ -+ /* -+ * Start with hc->xfer_buff initialized in -+ * assign_and_init_hc(), then if SG transfer consists of multiple URBs, -+ * this pointer re-assigned to the buffer of the currently processed QTD. -+ * For non-SG request there is always one QTD active. -+ */ -+ -+ DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) { -+ -+ if (n_desc) { -+ /* SG request - more than 1 QTDs */ -+ hc->xfer_buff = (uint8_t *)qtd->urb->dma + qtd->urb->actual_length; -+ hc->xfer_len = qtd->urb->length - qtd->urb->actual_length; -+ } -+ -+ qtd->n_desc = 0; -+ -+ do { -+ dma_desc = &qh->desc_list[n_desc]; -+ len = hc->xfer_len; -+ -+ if (len > MAX_DMA_DESC_SIZE) -+ len = MAX_DMA_DESC_SIZE - hc->max_packet + 1; -+ -+ if (hc->ep_is_in) { -+ if (len > 0) { -+ num_packets = (len + hc->max_packet - 1) / hc->max_packet; -+ } else { -+ /* Need 1 packet for transfer length of 0. */ -+ num_packets = 1; -+ } -+ /* Always program an integral # of max packets for IN transfers. */ -+ len = num_packets * hc->max_packet; -+ } -+ -+ dma_desc->status.b.n_bytes = len; -+ -+ qh->n_bytes[n_desc] = len; -+ -+ if ((qh->ep_type == UE_CONTROL) -+ && (qtd->control_phase == DWC_OTG_CONTROL_SETUP)) -+ dma_desc->status.b.sup = 1; /* Setup Packet */ -+ -+ dma_desc->status.b.a = 1; /* Active descriptor */ -+ dma_desc->status.b.sts = 0; -+ -+ dma_desc->buf = -+ ((unsigned long)hc->xfer_buff & 0xffffffff); -+ -+ /* -+ * Last descriptor(or single) of IN transfer -+ * with actual size less than MaxPacket. -+ */ -+ if (len > hc->xfer_len) { -+ hc->xfer_len = 0; -+ } else { -+ hc->xfer_buff += len; -+ hc->xfer_len -= len; -+ } -+ -+ qtd->n_desc++; -+ n_desc++; -+ } -+ while ((hc->xfer_len > 0) && (n_desc != MAX_DMA_DESC_NUM_GENERIC)); -+ -+ -+ qtd->in_process = 1; -+ -+ if (qh->ep_type == UE_CONTROL) -+ break; -+ -+ if (n_desc == MAX_DMA_DESC_NUM_GENERIC) -+ break; -+ } -+ -+ if (n_desc) { -+ /* Request Transfer Complete interrupt for the last descriptor */ -+ qh->desc_list[n_desc - 1].status.b.ioc = 1; -+ /* End of List indicator */ -+ qh->desc_list[n_desc - 1].status.b.eol = 1; -+ -+ hc->ntd = n_desc; -+ } -+} -+ -+/** -+ * For Control and Bulk endpoints initializes descriptor list -+ * and starts the transfer. -+ * -+ * For Interrupt and Isochronous endpoints initializes descriptor list -+ * then updates FrameList, marking appropriate entries as active. -+ * In case of Isochronous, the starting descriptor index is calculated based -+ * on the scheduled frame, but only on the first transfer descriptor within a session. -+ * Then starts the transfer via enabling the channel. -+ * For Isochronous endpoint the channel is not halted on XferComplete -+ * interrupt so remains assigned to the endpoint(QH) until session is done. -+ * -+ * @param hcd The HCD state structure for the DWC OTG controller. -+ * @param qh The QH to init. -+ * -+ * @return 0 if successful, negative error code otherwise. -+ */ -+void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) -+{ -+ /* Channel is already assigned */ -+ dwc_hc_t *hc = qh->channel; -+ uint8_t skip_frames = 0; -+ -+ switch (hc->ep_type) { -+ case DWC_OTG_EP_TYPE_CONTROL: -+ case DWC_OTG_EP_TYPE_BULK: -+ init_non_isoc_dma_desc(hcd, qh); -+ -+ dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc); -+ break; -+ case DWC_OTG_EP_TYPE_INTR: -+ init_non_isoc_dma_desc(hcd, qh); -+ -+ update_frame_list(hcd, qh, 1); -+ -+ dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc); -+ break; -+ case DWC_OTG_EP_TYPE_ISOC: -+ -+ if (!qh->ntd) -+ skip_frames = recalc_initial_desc_idx(hcd, qh); -+ -+ init_isoc_dma_desc(hcd, qh, skip_frames); -+ -+ if (!hc->xfer_started) { -+ -+ update_frame_list(hcd, qh, 1); -+ -+ /* -+ * Always set to max, instead of actual size. -+ * Otherwise ntd will be changed with -+ * channel being enabled. Not recommended. -+ * -+ */ -+ hc->ntd = max_desc_num(qh); -+ /* Enable channel only once for ISOC */ -+ dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc); -+ } -+ -+ break; -+ default: -+ -+ break; -+ } -+} -+ -+static void complete_isoc_xfer_ddma(dwc_otg_hcd_t * hcd, -+ dwc_hc_t * hc, -+ dwc_otg_hc_regs_t * hc_regs, -+ dwc_otg_halt_status_e halt_status) -+{ -+ struct dwc_otg_hcd_iso_packet_desc *frame_desc; -+ dwc_otg_qtd_t *qtd, *qtd_tmp; -+ dwc_otg_qh_t *qh; -+ dwc_otg_host_dma_desc_t *dma_desc; -+ uint16_t idx, remain; -+ uint8_t urb_compl; -+ -+ qh = hc->qh; -+ idx = qh->td_first; -+ -+ if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) { -+ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) -+ qtd->in_process = 0; -+ return; -+ } else if ((halt_status == DWC_OTG_HC_XFER_AHB_ERR) || -+ (halt_status == DWC_OTG_HC_XFER_BABBLE_ERR)) { -+ /* -+ * Channel is halted in these error cases. -+ * Considered as serious issues. -+ * Complete all URBs marking all frames as failed, -+ * irrespective whether some of the descriptors(frames) succeeded or no. -+ * Pass error code to completion routine as well, to -+ * update urb->status, some of class drivers might use it to stop -+ * queing transfer requests. -+ */ -+ int err = (halt_status == DWC_OTG_HC_XFER_AHB_ERR) -+ ? (-DWC_E_IO) -+ : (-DWC_E_OVERFLOW); -+ -+ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) { -+ for (idx = 0; idx < qtd->urb->packet_count; idx++) { -+ frame_desc = &qtd->urb->iso_descs[idx]; -+ frame_desc->status = err; -+ } -+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, err); -+ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh); -+ } -+ return; -+ } -+ -+ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) { -+ -+ if (!qtd->in_process) -+ break; -+ -+ urb_compl = 0; -+ -+ do { -+ -+ dma_desc = &qh->desc_list[idx]; -+ -+ frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; -+ remain = hc->ep_is_in ? dma_desc->status.b_isoc.n_bytes : 0; -+ -+ if (dma_desc->status.b_isoc.sts == DMA_DESC_STS_PKTERR) { -+ /* -+ * XactError or, unable to complete all the transactions -+ * in the scheduled micro-frame/frame, -+ * both indicated by DMA_DESC_STS_PKTERR. -+ */ -+ qtd->urb->error_count++; -+ frame_desc->actual_length = qh->n_bytes[idx] - remain; -+ frame_desc->status = -DWC_E_PROTOCOL; -+ } else { -+ /* Success */ -+ -+ frame_desc->actual_length = qh->n_bytes[idx] - remain; -+ frame_desc->status = 0; -+ } -+ -+ if (++qtd->isoc_frame_index == qtd->urb->packet_count) { -+ /* -+ * urb->status is not used for isoc transfers here. -+ * The individual frame_desc status are used instead. -+ */ -+ -+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); -+ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh); -+ -+ /* -+ * This check is necessary because urb_dequeue can be called -+ * from urb complete callback(sound driver example). -+ * All pending URBs are dequeued there, so no need for -+ * further processing. -+ */ -+ if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) { -+ return; -+ } -+ -+ urb_compl = 1; -+ -+ } -+ -+ qh->ntd--; -+ -+ /* Stop if IOC requested descriptor reached */ -+ if (dma_desc->status.b_isoc.ioc) { -+ idx = desclist_idx_inc(idx, qh->interval, hc->speed); -+ goto stop_scan; -+ } -+ -+ idx = desclist_idx_inc(idx, qh->interval, hc->speed); -+ -+ if (urb_compl) -+ break; -+ } -+ while (idx != qh->td_first); -+ } -+stop_scan: -+ qh->td_first = idx; -+} -+ -+uint8_t update_non_isoc_urb_state_ddma(dwc_otg_hcd_t * hcd, -+ dwc_hc_t * hc, -+ dwc_otg_qtd_t * qtd, -+ dwc_otg_host_dma_desc_t * dma_desc, -+ dwc_otg_halt_status_e halt_status, -+ uint32_t n_bytes, uint8_t * xfer_done) -+{ -+ -+ uint16_t remain = hc->ep_is_in ? dma_desc->status.b.n_bytes : 0; -+ dwc_otg_hcd_urb_t *urb = qtd->urb; -+ -+ if (halt_status == DWC_OTG_HC_XFER_AHB_ERR) { -+ urb->status = -DWC_E_IO; -+ return 1; -+ } -+ if (dma_desc->status.b.sts == DMA_DESC_STS_PKTERR) { -+ switch (halt_status) { -+ case DWC_OTG_HC_XFER_STALL: -+ urb->status = -DWC_E_PIPE; -+ break; -+ case DWC_OTG_HC_XFER_BABBLE_ERR: -+ urb->status = -DWC_E_OVERFLOW; -+ break; -+ case DWC_OTG_HC_XFER_XACT_ERR: -+ urb->status = -DWC_E_PROTOCOL; -+ break; -+ default: -+ DWC_ERROR("%s: Unhandled descriptor error status (%d)\n", __func__, -+ halt_status); -+ break; -+ } -+ return 1; -+ } -+ -+ if (dma_desc->status.b.a == 1) { -+ DWC_DEBUGPL(DBG_HCDV, -+ "Active descriptor encountered on channel %d\n", -+ hc->hc_num); -+ return 0; -+ } -+ -+ if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL) { -+ if (qtd->control_phase == DWC_OTG_CONTROL_DATA) { -+ urb->actual_length += n_bytes - remain; -+ if (remain || urb->actual_length == urb->length) { -+ /* -+ * For Control Data stage do not set urb->status=0 to prevent -+ * URB callback. Set it when Status phase done. See below. -+ */ -+ *xfer_done = 1; -+ } -+ -+ } else if (qtd->control_phase == DWC_OTG_CONTROL_STATUS) { -+ urb->status = 0; -+ *xfer_done = 1; -+ } -+ /* No handling for SETUP stage */ -+ } else { -+ /* BULK and INTR */ -+ urb->actual_length += n_bytes - remain; -+ if (remain || urb->actual_length == urb->length) { -+ urb->status = 0; -+ *xfer_done = 1; -+ } -+ } -+ -+ return 0; -+} -+ -+static void complete_non_isoc_xfer_ddma(dwc_otg_hcd_t * hcd, -+ dwc_hc_t * hc, -+ dwc_otg_hc_regs_t * hc_regs, -+ dwc_otg_halt_status_e halt_status) -+{ -+ dwc_otg_hcd_urb_t *urb = NULL; -+ dwc_otg_qtd_t *qtd, *qtd_tmp; -+ dwc_otg_qh_t *qh; -+ dwc_otg_host_dma_desc_t *dma_desc; -+ uint32_t n_bytes, n_desc, i; -+ uint8_t failed = 0, xfer_done; -+ -+ n_desc = 0; -+ -+ qh = hc->qh; -+ -+ if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) { -+ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) { -+ qtd->in_process = 0; -+ } -+ return; -+ } -+ -+ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) { -+ -+ urb = qtd->urb; -+ -+ n_bytes = 0; -+ xfer_done = 0; -+ -+ for (i = 0; i < qtd->n_desc; i++) { -+ dma_desc = &qh->desc_list[n_desc]; -+ -+ n_bytes = qh->n_bytes[n_desc]; -+ -+ failed = -+ update_non_isoc_urb_state_ddma(hcd, hc, qtd, -+ dma_desc, -+ halt_status, n_bytes, -+ &xfer_done); -+ -+ if (failed -+ || (xfer_done -+ && (urb->status != -DWC_E_IN_PROGRESS))) { -+ -+ hcd->fops->complete(hcd, urb->priv, urb, -+ urb->status); -+ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh); -+ -+ if (failed) -+ goto stop_scan; -+ } else if (qh->ep_type == UE_CONTROL) { -+ if (qtd->control_phase == DWC_OTG_CONTROL_SETUP) { -+ if (urb->length > 0) { -+ qtd->control_phase = DWC_OTG_CONTROL_DATA; -+ } else { -+ qtd->control_phase = DWC_OTG_CONTROL_STATUS; -+ } -+ DWC_DEBUGPL(DBG_HCDV, " Control setup transaction done\n"); -+ } else if (qtd->control_phase == DWC_OTG_CONTROL_DATA) { -+ if (xfer_done) { -+ qtd->control_phase = DWC_OTG_CONTROL_STATUS; -+ DWC_DEBUGPL(DBG_HCDV, " Control data transfer done\n"); -+ } else if (i + 1 == qtd->n_desc) { -+ /* -+ * Last descriptor for Control data stage which is -+ * not completed yet. -+ */ -+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); -+ } -+ } -+ } -+ -+ n_desc++; -+ } -+ -+ } -+ -+stop_scan: -+ -+ if (qh->ep_type != UE_CONTROL) { -+ /* -+ * Resetting the data toggle for bulk -+ * and interrupt endpoints in case of stall. See handle_hc_stall_intr() -+ */ -+ if (halt_status == DWC_OTG_HC_XFER_STALL) -+ qh->data_toggle = DWC_OTG_HC_PID_DATA0; -+ else -+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); -+ } -+ -+ if (halt_status == DWC_OTG_HC_XFER_COMPLETE) { -+ hcint_data_t hcint; -+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); -+ if (hcint.b.nyet) { -+ /* -+ * Got a NYET on the last transaction of the transfer. It -+ * means that the endpoint should be in the PING state at the -+ * beginning of the next transfer. -+ */ -+ qh->ping_state = 1; -+ clear_hc_int(hc_regs, nyet); -+ } -+ -+ } -+ -+} -+ -+/** -+ * This function is called from interrupt handlers. -+ * Scans the descriptor list, updates URB's status and -+ * calls completion routine for the URB if it's done. -+ * Releases the channel to be used by other transfers. -+ * In case of Isochronous endpoint the channel is not halted until -+ * the end of the session, i.e. QTD list is empty. -+ * If periodic channel released the FrameList is updated accordingly. -+ * -+ * Calls transaction selection routines to activate pending transfers. -+ * -+ * @param hcd The HCD state structure for the DWC OTG controller. -+ * @param hc Host channel, the transfer is completed on. -+ * @param hc_regs Host channel registers. -+ * @param halt_status Reason the channel is being halted, -+ * or just XferComplete for isochronous transfer -+ */ -+void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd, -+ dwc_hc_t * hc, -+ dwc_otg_hc_regs_t * hc_regs, -+ dwc_otg_halt_status_e halt_status) -+{ -+ uint8_t continue_isoc_xfer = 0; -+ dwc_otg_transaction_type_e tr_type; -+ dwc_otg_qh_t *qh = hc->qh; -+ -+ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { -+ -+ complete_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status); -+ -+ /* Release the channel if halted or session completed */ -+ if (halt_status != DWC_OTG_HC_XFER_COMPLETE || -+ DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) { -+ -+ /* Halt the channel if session completed */ -+ if (halt_status == DWC_OTG_HC_XFER_COMPLETE) { -+ dwc_otg_hc_halt(hcd->core_if, hc, halt_status); -+ } -+ -+ release_channel_ddma(hcd, qh); -+ dwc_otg_hcd_qh_remove(hcd, qh); -+ } else { -+ /* Keep in assigned schedule to continue transfer */ -+ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned, -+ &qh->qh_list_entry); -+ continue_isoc_xfer = 1; -+ -+ } -+ /** @todo Consider the case when period exceeds FrameList size. -+ * Frame Rollover interrupt should be used. -+ */ -+ } else { -+ /* Scan descriptor list to complete the URB(s), then release the channel */ -+ complete_non_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status); -+ -+ release_channel_ddma(hcd, qh); -+ dwc_otg_hcd_qh_remove(hcd, qh); -+ -+ if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) { -+ /* Add back to inactive non-periodic schedule on normal completion */ -+ dwc_otg_hcd_qh_add(hcd, qh); -+ } -+ -+ } -+ tr_type = dwc_otg_hcd_select_transactions(hcd); -+ if (tr_type != DWC_OTG_TRANSACTION_NONE || continue_isoc_xfer) { -+ if (continue_isoc_xfer) { -+ if (tr_type == DWC_OTG_TRANSACTION_NONE) { -+ tr_type = DWC_OTG_TRANSACTION_PERIODIC; -+ } else if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC) { -+ tr_type = DWC_OTG_TRANSACTION_ALL; -+ } -+ } -+ dwc_otg_hcd_queue_transactions(hcd, tr_type); -+ } -+} -+ -+#endif /* DWC_DEVICE_ONLY */ -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd.h ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd.h 2015-11-29 09:42:39.919098694 +0100 -@@ -0,0 +1,862 @@ -+/* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $ -+ * $Revision: #58 $ -+ * $Date: 2011/09/15 $ -+ * $Change: 1846647 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+#ifndef DWC_DEVICE_ONLY -+#ifndef __DWC_HCD_H__ -+#define __DWC_HCD_H__ -+ -+#include "dwc_otg_os_dep.h" -+#include "usb.h" -+#include "dwc_otg_hcd_if.h" -+#include "dwc_otg_core_if.h" -+#include "dwc_list.h" -+#include "dwc_otg_cil.h" -+#include "dwc_otg_fiq_fsm.h" -+ -+ -+/** -+ * @file -+ * -+ * This file contains the structures, constants, and interfaces for -+ * the Host Contoller Driver (HCD). -+ * -+ * The Host Controller Driver (HCD) is responsible for translating requests -+ * from the USB Driver into the appropriate actions on the DWC_otg controller. -+ * It isolates the USBD from the specifics of the controller by providing an -+ * API to the USBD. -+ */ -+ -+struct dwc_otg_hcd_pipe_info { -+ uint8_t dev_addr; -+ uint8_t ep_num; -+ uint8_t pipe_type; -+ uint8_t pipe_dir; -+ uint16_t mps; -+}; -+ -+struct dwc_otg_hcd_iso_packet_desc { -+ uint32_t offset; -+ uint32_t length; -+ uint32_t actual_length; -+ uint32_t status; -+}; -+ -+struct dwc_otg_qtd; -+ -+struct dwc_otg_hcd_urb { -+ void *priv; -+ struct dwc_otg_qtd *qtd; -+ void *buf; -+ dwc_dma_t dma; -+ void *setup_packet; -+ dwc_dma_t setup_dma; -+ uint32_t length; -+ uint32_t actual_length; -+ uint32_t status; -+ uint32_t error_count; -+ uint32_t packet_count; -+ uint32_t flags; -+ uint16_t interval; -+ struct dwc_otg_hcd_pipe_info pipe_info; -+ struct dwc_otg_hcd_iso_packet_desc iso_descs[0]; -+}; -+ -+static inline uint8_t dwc_otg_hcd_get_ep_num(struct dwc_otg_hcd_pipe_info *pipe) -+{ -+ return pipe->ep_num; -+} -+ -+static inline uint8_t dwc_otg_hcd_get_pipe_type(struct dwc_otg_hcd_pipe_info -+ *pipe) -+{ -+ return pipe->pipe_type; -+} -+ -+static inline uint16_t dwc_otg_hcd_get_mps(struct dwc_otg_hcd_pipe_info *pipe) -+{ -+ return pipe->mps; -+} -+ -+static inline uint8_t dwc_otg_hcd_get_dev_addr(struct dwc_otg_hcd_pipe_info -+ *pipe) -+{ -+ return pipe->dev_addr; -+} -+ -+static inline uint8_t dwc_otg_hcd_is_pipe_isoc(struct dwc_otg_hcd_pipe_info -+ *pipe) -+{ -+ return (pipe->pipe_type == UE_ISOCHRONOUS); -+} -+ -+static inline uint8_t dwc_otg_hcd_is_pipe_int(struct dwc_otg_hcd_pipe_info -+ *pipe) -+{ -+ return (pipe->pipe_type == UE_INTERRUPT); -+} -+ -+static inline uint8_t dwc_otg_hcd_is_pipe_bulk(struct dwc_otg_hcd_pipe_info -+ *pipe) -+{ -+ return (pipe->pipe_type == UE_BULK); -+} -+ -+static inline uint8_t dwc_otg_hcd_is_pipe_control(struct dwc_otg_hcd_pipe_info -+ *pipe) -+{ -+ return (pipe->pipe_type == UE_CONTROL); -+} -+ -+static inline uint8_t dwc_otg_hcd_is_pipe_in(struct dwc_otg_hcd_pipe_info *pipe) -+{ -+ return (pipe->pipe_dir == UE_DIR_IN); -+} -+ -+static inline uint8_t dwc_otg_hcd_is_pipe_out(struct dwc_otg_hcd_pipe_info -+ *pipe) -+{ -+ return (!dwc_otg_hcd_is_pipe_in(pipe)); -+} -+ -+static inline void dwc_otg_hcd_fill_pipe(struct dwc_otg_hcd_pipe_info *pipe, -+ uint8_t devaddr, uint8_t ep_num, -+ uint8_t pipe_type, uint8_t pipe_dir, -+ uint16_t mps) -+{ -+ pipe->dev_addr = devaddr; -+ pipe->ep_num = ep_num; -+ pipe->pipe_type = pipe_type; -+ pipe->pipe_dir = pipe_dir; -+ pipe->mps = mps; -+} -+ -+/** -+ * Phases for control transfers. -+ */ -+typedef enum dwc_otg_control_phase { -+ DWC_OTG_CONTROL_SETUP, -+ DWC_OTG_CONTROL_DATA, -+ DWC_OTG_CONTROL_STATUS -+} dwc_otg_control_phase_e; -+ -+/** Transaction types. */ -+typedef enum dwc_otg_transaction_type { -+ DWC_OTG_TRANSACTION_NONE = 0, -+ DWC_OTG_TRANSACTION_PERIODIC = 1, -+ DWC_OTG_TRANSACTION_NON_PERIODIC = 2, -+ DWC_OTG_TRANSACTION_ALL = DWC_OTG_TRANSACTION_PERIODIC + DWC_OTG_TRANSACTION_NON_PERIODIC -+} dwc_otg_transaction_type_e; -+ -+struct dwc_otg_qh; -+ -+/** -+ * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, -+ * interrupt, or isochronous transfer. A single QTD is created for each URB -+ * (of one of these types) submitted to the HCD. The transfer associated with -+ * a QTD may require one or multiple transactions. -+ * -+ * A QTD is linked to a Queue Head, which is entered in either the -+ * non-periodic or periodic schedule for execution. When a QTD is chosen for -+ * execution, some or all of its transactions may be executed. After -+ * execution, the state of the QTD is updated. The QTD may be retired if all -+ * its transactions are complete or if an error occurred. Otherwise, it -+ * remains in the schedule so more transactions can be executed later. -+ */ -+typedef struct dwc_otg_qtd { -+ /** -+ * Determines the PID of the next data packet for the data phase of -+ * control transfers. Ignored for other transfer types.
-+ * One of the following values: -+ * - DWC_OTG_HC_PID_DATA0 -+ * - DWC_OTG_HC_PID_DATA1 -+ */ -+ uint8_t data_toggle; -+ -+ /** Current phase for control transfers (Setup, Data, or Status). */ -+ dwc_otg_control_phase_e control_phase; -+ -+ /** Keep track of the current split type -+ * for FS/LS endpoints on a HS Hub */ -+ uint8_t complete_split; -+ -+ /** How many bytes transferred during SSPLIT OUT */ -+ uint32_t ssplit_out_xfer_count; -+ -+ /** -+ * Holds the number of bus errors that have occurred for a transaction -+ * within this transfer. -+ */ -+ uint8_t error_count; -+ -+ /** -+ * Index of the next frame descriptor for an isochronous transfer. A -+ * frame descriptor describes the buffer position and length of the -+ * data to be transferred in the next scheduled (micro)frame of an -+ * isochronous transfer. It also holds status for that transaction. -+ * The frame index starts at 0. -+ */ -+ uint16_t isoc_frame_index; -+ -+ /** Position of the ISOC split on full/low speed */ -+ uint8_t isoc_split_pos; -+ -+ /** Position of the ISOC split in the buffer for the current frame */ -+ uint16_t isoc_split_offset; -+ -+ /** URB for this transfer */ -+ struct dwc_otg_hcd_urb *urb; -+ -+ struct dwc_otg_qh *qh; -+ -+ /** This list of QTDs */ -+ DWC_CIRCLEQ_ENTRY(dwc_otg_qtd) qtd_list_entry; -+ -+ /** Indicates if this QTD is currently processed by HW. */ -+ uint8_t in_process; -+ -+ /** Number of DMA descriptors for this QTD */ -+ uint8_t n_desc; -+ -+ /** -+ * Last activated frame(packet) index. -+ * Used in Descriptor DMA mode only. -+ */ -+ uint16_t isoc_frame_index_last; -+ -+} dwc_otg_qtd_t; -+ -+DWC_CIRCLEQ_HEAD(dwc_otg_qtd_list, dwc_otg_qtd); -+ -+/** -+ * A Queue Head (QH) holds the static characteristics of an endpoint and -+ * maintains a list of transfers (QTDs) for that endpoint. A QH structure may -+ * be entered in either the non-periodic or periodic schedule. -+ */ -+typedef struct dwc_otg_qh { -+ /** -+ * Endpoint type. -+ * One of the following values: -+ * - UE_CONTROL -+ * - UE_BULK -+ * - UE_INTERRUPT -+ * - UE_ISOCHRONOUS -+ */ -+ uint8_t ep_type; -+ uint8_t ep_is_in; -+ -+ /** wMaxPacketSize Field of Endpoint Descriptor. */ -+ uint16_t maxp; -+ -+ /** -+ * Device speed. -+ * One of the following values: -+ * - DWC_OTG_EP_SPEED_LOW -+ * - DWC_OTG_EP_SPEED_FULL -+ * - DWC_OTG_EP_SPEED_HIGH -+ */ -+ uint8_t dev_speed; -+ -+ /** -+ * Determines the PID of the next data packet for non-control -+ * transfers. Ignored for control transfers.
-+ * One of the following values: -+ * - DWC_OTG_HC_PID_DATA0 -+ * - DWC_OTG_HC_PID_DATA1 -+ */ -+ uint8_t data_toggle; -+ -+ /** Ping state if 1. */ -+ uint8_t ping_state; -+ -+ /** -+ * List of QTDs for this QH. -+ */ -+ struct dwc_otg_qtd_list qtd_list; -+ -+ /** Host channel currently processing transfers for this QH. */ -+ struct dwc_hc *channel; -+ -+ /** Full/low speed endpoint on high-speed hub requires split. */ -+ uint8_t do_split; -+ -+ /** @name Periodic schedule information */ -+ /** @{ */ -+ -+ /** Bandwidth in microseconds per (micro)frame. */ -+ uint16_t usecs; -+ -+ /** Interval between transfers in (micro)frames. */ -+ uint16_t interval; -+ -+ /** -+ * (micro)frame to initialize a periodic transfer. The transfer -+ * executes in the following (micro)frame. -+ */ -+ uint16_t sched_frame; -+ -+ /* -+ ** Frame a NAK was received on this queue head, used to minimise NAK retransmission -+ */ -+ uint16_t nak_frame; -+ -+ /** (micro)frame at which last start split was initialized. */ -+ uint16_t start_split_frame; -+ -+ /** @} */ -+ -+ /** -+ * Used instead of original buffer if -+ * it(physical address) is not dword-aligned. -+ */ -+ uint8_t *dw_align_buf; -+ dwc_dma_t dw_align_buf_dma; -+ -+ /** Entry for QH in either the periodic or non-periodic schedule. */ -+ dwc_list_link_t qh_list_entry; -+ -+ /** @name Descriptor DMA support */ -+ /** @{ */ -+ -+ /** Descriptor List. */ -+ dwc_otg_host_dma_desc_t *desc_list; -+ -+ /** Descriptor List physical address. */ -+ dwc_dma_t desc_list_dma; -+ -+ /** -+ * Xfer Bytes array. -+ * Each element corresponds to a descriptor and indicates -+ * original XferSize size value for the descriptor. -+ */ -+ uint32_t *n_bytes; -+ -+ /** Actual number of transfer descriptors in a list. */ -+ uint16_t ntd; -+ -+ /** First activated isochronous transfer descriptor index. */ -+ uint8_t td_first; -+ /** Last activated isochronous transfer descriptor index. */ -+ uint8_t td_last; -+ -+ /** @} */ -+ -+ -+ uint16_t speed; -+ uint16_t frame_usecs[8]; -+ -+ uint32_t skip_count; -+} dwc_otg_qh_t; -+ -+DWC_CIRCLEQ_HEAD(hc_list, dwc_hc); -+ -+typedef struct urb_tq_entry { -+ struct urb *urb; -+ DWC_TAILQ_ENTRY(urb_tq_entry) urb_tq_entries; -+} urb_tq_entry_t; -+ -+DWC_TAILQ_HEAD(urb_list, urb_tq_entry); -+ -+/** -+ * This structure holds the state of the HCD, including the non-periodic and -+ * periodic schedules. -+ */ -+struct dwc_otg_hcd { -+ /** The DWC otg device pointer */ -+ struct dwc_otg_device *otg_dev; -+ /** DWC OTG Core Interface Layer */ -+ dwc_otg_core_if_t *core_if; -+ -+ /** Function HCD driver callbacks */ -+ struct dwc_otg_hcd_function_ops *fops; -+ -+ /** Internal DWC HCD Flags */ -+ volatile union dwc_otg_hcd_internal_flags { -+ uint32_t d32; -+ struct { -+ unsigned port_connect_status_change:1; -+ unsigned port_connect_status:1; -+ unsigned port_reset_change:1; -+ unsigned port_enable_change:1; -+ unsigned port_suspend_change:1; -+ unsigned port_over_current_change:1; -+ unsigned port_l1_change:1; -+ unsigned reserved:26; -+ } b; -+ } flags; -+ -+ /** -+ * Inactive items in the non-periodic schedule. This is a list of -+ * Queue Heads. Transfers associated with these Queue Heads are not -+ * currently assigned to a host channel. -+ */ -+ dwc_list_link_t non_periodic_sched_inactive; -+ -+ /** -+ * Active items in the non-periodic schedule. This is a list of -+ * Queue Heads. Transfers associated with these Queue Heads are -+ * currently assigned to a host channel. -+ */ -+ dwc_list_link_t non_periodic_sched_active; -+ -+ /** -+ * Pointer to the next Queue Head to process in the active -+ * non-periodic schedule. -+ */ -+ dwc_list_link_t *non_periodic_qh_ptr; -+ -+ /** -+ * Inactive items in the periodic schedule. This is a list of QHs for -+ * periodic transfers that are _not_ scheduled for the next frame. -+ * Each QH in the list has an interval counter that determines when it -+ * needs to be scheduled for execution. This scheduling mechanism -+ * allows only a simple calculation for periodic bandwidth used (i.e. -+ * must assume that all periodic transfers may need to execute in the -+ * same frame). However, it greatly simplifies scheduling and should -+ * be sufficient for the vast majority of OTG hosts, which need to -+ * connect to a small number of peripherals at one time. -+ * -+ * Items move from this list to periodic_sched_ready when the QH -+ * interval counter is 0 at SOF. -+ */ -+ dwc_list_link_t periodic_sched_inactive; -+ -+ /** -+ * List of periodic QHs that are ready for execution in the next -+ * frame, but have not yet been assigned to host channels. -+ * -+ * Items move from this list to periodic_sched_assigned as host -+ * channels become available during the current frame. -+ */ -+ dwc_list_link_t periodic_sched_ready; -+ -+ /** -+ * List of periodic QHs to be executed in the next frame that are -+ * assigned to host channels. -+ * -+ * Items move from this list to periodic_sched_queued as the -+ * transactions for the QH are queued to the DWC_otg controller. -+ */ -+ dwc_list_link_t periodic_sched_assigned; -+ -+ /** -+ * List of periodic QHs that have been queued for execution. -+ * -+ * Items move from this list to either periodic_sched_inactive or -+ * periodic_sched_ready when the channel associated with the transfer -+ * is released. If the interval for the QH is 1, the item moves to -+ * periodic_sched_ready because it must be rescheduled for the next -+ * frame. Otherwise, the item moves to periodic_sched_inactive. -+ */ -+ dwc_list_link_t periodic_sched_queued; -+ -+ /** -+ * Total bandwidth claimed so far for periodic transfers. This value -+ * is in microseconds per (micro)frame. The assumption is that all -+ * periodic transfers may occur in the same (micro)frame. -+ */ -+ uint16_t periodic_usecs; -+ -+ /** -+ * Total bandwidth claimed so far for all periodic transfers -+ * in a frame. -+ * This will include a mixture of HS and FS transfers. -+ * Units are microseconds per (micro)frame. -+ * We have a budget per frame and have to schedule -+ * transactions accordingly. -+ * Watch out for the fact that things are actually scheduled for the -+ * "next frame". -+ */ -+ uint16_t frame_usecs[8]; -+ -+ -+ /** -+ * Frame number read from the core at SOF. The value ranges from 0 to -+ * DWC_HFNUM_MAX_FRNUM. -+ */ -+ uint16_t frame_number; -+ -+ /** -+ * Count of periodic QHs, if using several eps. For SOF enable/disable. -+ */ -+ uint16_t periodic_qh_count; -+ -+ /** -+ * Free host channels in the controller. This is a list of -+ * dwc_hc_t items. -+ */ -+ struct hc_list free_hc_list; -+ /** -+ * Number of host channels assigned to periodic transfers. Currently -+ * assuming that there is a dedicated host channel for each periodic -+ * transaction and at least one host channel available for -+ * non-periodic transactions. -+ */ -+ int periodic_channels; /* microframe_schedule==0 */ -+ -+ /** -+ * Number of host channels assigned to non-periodic transfers. -+ */ -+ int non_periodic_channels; /* microframe_schedule==0 */ -+ -+ /** -+ * Number of host channels assigned to non-periodic transfers. -+ */ -+ int available_host_channels; -+ -+ /** -+ * Array of pointers to the host channel descriptors. Allows accessing -+ * a host channel descriptor given the host channel number. This is -+ * useful in interrupt handlers. -+ */ -+ struct dwc_hc *hc_ptr_array[MAX_EPS_CHANNELS]; -+ -+ /** -+ * Buffer to use for any data received during the status phase of a -+ * control transfer. Normally no data is transferred during the status -+ * phase. This buffer is used as a bit bucket. -+ */ -+ uint8_t *status_buf; -+ -+ /** -+ * DMA address for status_buf. -+ */ -+ dma_addr_t status_buf_dma; -+#define DWC_OTG_HCD_STATUS_BUF_SIZE 64 -+ -+ /** -+ * Connection timer. An OTG host must display a message if the device -+ * does not connect. Started when the VBus power is turned on via -+ * sysfs attribute "buspower". -+ */ -+ dwc_timer_t *conn_timer; -+ -+ /* Tasket to do a reset */ -+ dwc_tasklet_t *reset_tasklet; -+ -+ dwc_tasklet_t *completion_tasklet; -+ struct urb_list completed_urb_list; -+ -+ /* */ -+ dwc_spinlock_t *lock; -+ dwc_spinlock_t *channel_lock; -+ /** -+ * Private data that could be used by OS wrapper. -+ */ -+ void *priv; -+ -+ uint8_t otg_port; -+ -+ /** Frame List */ -+ uint32_t *frame_list; -+ -+ /** Hub - Port assignment */ -+ int hub_port[128]; -+#ifdef FIQ_DEBUG -+ int hub_port_alloc[2048]; -+#endif -+ -+ /** Frame List DMA address */ -+ dma_addr_t frame_list_dma; -+ -+ struct fiq_stack *fiq_stack; -+ struct fiq_state *fiq_state; -+ -+ /** Virtual address for split transaction DMA bounce buffers */ -+ struct fiq_dma_blob *fiq_dmab; -+ -+#ifdef DEBUG -+ uint32_t frrem_samples; -+ uint64_t frrem_accum; -+ -+ uint32_t hfnum_7_samples_a; -+ uint64_t hfnum_7_frrem_accum_a; -+ uint32_t hfnum_0_samples_a; -+ uint64_t hfnum_0_frrem_accum_a; -+ uint32_t hfnum_other_samples_a; -+ uint64_t hfnum_other_frrem_accum_a; -+ -+ uint32_t hfnum_7_samples_b; -+ uint64_t hfnum_7_frrem_accum_b; -+ uint32_t hfnum_0_samples_b; -+ uint64_t hfnum_0_frrem_accum_b; -+ uint32_t hfnum_other_samples_b; -+ uint64_t hfnum_other_frrem_accum_b; -+#endif -+}; -+ -+/** @name Transaction Execution Functions */ -+/** @{ */ -+extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t -+ * hcd); -+extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd, -+ dwc_otg_transaction_type_e tr_type); -+ -+int dwc_otg_hcd_allocate_port(dwc_otg_hcd_t * hcd, dwc_otg_qh_t *qh); -+void dwc_otg_hcd_release_port(dwc_otg_hcd_t * dwc_otg_hcd, dwc_otg_qh_t *qh); -+ -+extern int fiq_fsm_queue_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh); -+extern int fiq_fsm_transaction_suitable(dwc_otg_qh_t *qh); -+extern void dwc_otg_cleanup_fiq_channel(dwc_otg_hcd_t *hcd, uint32_t num); -+ -+/** @} */ -+ -+/** @name Interrupt Handler Functions */ -+/** @{ */ -+extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd); -+extern int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * dwc_otg_hcd); -+extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t * -+ dwc_otg_hcd); -+extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t * -+ dwc_otg_hcd); -+extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t * -+ dwc_otg_hcd); -+extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t * -+ dwc_otg_hcd); -+extern int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd); -+extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr(dwc_otg_hcd_t * -+ dwc_otg_hcd); -+extern int32_t dwc_otg_hcd_handle_disconnect_intr(dwc_otg_hcd_t * dwc_otg_hcd); -+extern int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd); -+extern int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, -+ uint32_t num); -+extern int32_t dwc_otg_hcd_handle_session_req_intr(dwc_otg_hcd_t * dwc_otg_hcd); -+extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr(dwc_otg_hcd_t * -+ dwc_otg_hcd); -+/** @} */ -+ -+/** @name Schedule Queue Functions */ -+/** @{ */ -+ -+/* Implemented in dwc_otg_hcd_queue.c */ -+extern dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd, -+ dwc_otg_hcd_urb_t * urb, int atomic_alloc); -+extern void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); -+extern int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); -+extern void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); -+extern void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, -+ int sched_csplit); -+ -+/** Remove and free a QH */ -+static inline void dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd_t * hcd, -+ dwc_otg_qh_t * qh) -+{ -+ dwc_irqflags_t flags; -+ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); -+ dwc_otg_hcd_qh_remove(hcd, qh); -+ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); -+ dwc_otg_hcd_qh_free(hcd, qh); -+} -+ -+/** Allocates memory for a QH structure. -+ * @return Returns the memory allocate or NULL on error. */ -+static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(int atomic_alloc) -+{ -+ if (atomic_alloc) -+ return (dwc_otg_qh_t *) DWC_ALLOC_ATOMIC(sizeof(dwc_otg_qh_t)); -+ else -+ return (dwc_otg_qh_t *) DWC_ALLOC(sizeof(dwc_otg_qh_t)); -+} -+ -+extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb, -+ int atomic_alloc); -+extern void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb); -+extern int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, dwc_otg_hcd_t * dwc_otg_hcd, -+ dwc_otg_qh_t ** qh, int atomic_alloc); -+ -+/** Allocates memory for a QTD structure. -+ * @return Returns the memory allocate or NULL on error. */ -+static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(int atomic_alloc) -+{ -+ if (atomic_alloc) -+ return (dwc_otg_qtd_t *) DWC_ALLOC_ATOMIC(sizeof(dwc_otg_qtd_t)); -+ else -+ return (dwc_otg_qtd_t *) DWC_ALLOC(sizeof(dwc_otg_qtd_t)); -+} -+ -+/** Frees the memory for a QTD structure. QTD should already be removed from -+ * list. -+ * @param qtd QTD to free.*/ -+static inline void dwc_otg_hcd_qtd_free(dwc_otg_qtd_t * qtd) -+{ -+ DWC_FREE(qtd); -+} -+ -+/** Removes a QTD from list. -+ * @param hcd HCD instance. -+ * @param qtd QTD to remove from list. -+ * @param qh QTD belongs to. -+ */ -+static inline void dwc_otg_hcd_qtd_remove(dwc_otg_hcd_t * hcd, -+ dwc_otg_qtd_t * qtd, -+ dwc_otg_qh_t * qh) -+{ -+ DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry); -+} -+ -+/** Remove and free a QTD -+ * Need to disable IRQ and hold hcd lock while calling this function out of -+ * interrupt servicing chain */ -+static inline void dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd_t * hcd, -+ dwc_otg_qtd_t * qtd, -+ dwc_otg_qh_t * qh) -+{ -+ dwc_otg_hcd_qtd_remove(hcd, qtd, qh); -+ dwc_otg_hcd_qtd_free(qtd); -+} -+ -+/** @} */ -+ -+/** @name Descriptor DMA Supporting Functions */ -+/** @{ */ -+ -+extern void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); -+extern void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd, -+ dwc_hc_t * hc, -+ dwc_otg_hc_regs_t * hc_regs, -+ dwc_otg_halt_status_e halt_status); -+ -+extern int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); -+extern void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); -+ -+/** @} */ -+ -+/** @name Internal Functions */ -+/** @{ */ -+dwc_otg_qh_t *dwc_urb_to_qh(dwc_otg_hcd_urb_t * urb); -+/** @} */ -+ -+#ifdef CONFIG_USB_DWC_OTG_LPM -+extern int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd, -+ uint8_t devaddr); -+extern void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd); -+#endif -+ -+/** Gets the QH that contains the list_head */ -+#define dwc_list_to_qh(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry) -+ -+/** Gets the QTD that contains the list_head */ -+#define dwc_list_to_qtd(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry) -+ -+/** Check if QH is non-periodic */ -+#define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == UE_BULK) || \ -+ (_qh_ptr_->ep_type == UE_CONTROL)) -+ -+/** High bandwidth multiplier as encoded in highspeed endpoint descriptors */ -+#define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03)) -+ -+/** Packet size for any kind of endpoint descriptor */ -+#define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) -+ -+/** -+ * Returns true if _frame1 is less than or equal to _frame2. The comparison is -+ * done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the -+ * frame number when the max frame number is reached. -+ */ -+static inline int dwc_frame_num_le(uint16_t frame1, uint16_t frame2) -+{ -+ return ((frame2 - frame1) & DWC_HFNUM_MAX_FRNUM) <= -+ (DWC_HFNUM_MAX_FRNUM >> 1); -+} -+ -+/** -+ * Returns true if _frame1 is greater than _frame2. The comparison is done -+ * modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame -+ * number when the max frame number is reached. -+ */ -+static inline int dwc_frame_num_gt(uint16_t frame1, uint16_t frame2) -+{ -+ return (frame1 != frame2) && -+ (((frame1 - frame2) & DWC_HFNUM_MAX_FRNUM) < -+ (DWC_HFNUM_MAX_FRNUM >> 1)); -+} -+ -+/** -+ * Increments _frame by the amount specified by _inc. The addition is done -+ * modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value. -+ */ -+static inline uint16_t dwc_frame_num_inc(uint16_t frame, uint16_t inc) -+{ -+ return (frame + inc) & DWC_HFNUM_MAX_FRNUM; -+} -+ -+static inline uint16_t dwc_full_frame_num(uint16_t frame) -+{ -+ return (frame & DWC_HFNUM_MAX_FRNUM) >> 3; -+} -+ -+static inline uint16_t dwc_micro_frame_num(uint16_t frame) -+{ -+ return frame & 0x7; -+} -+ -+void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc, -+ dwc_otg_hc_regs_t * hc_regs, -+ dwc_otg_qtd_t * qtd); -+ -+#ifdef DEBUG -+/** -+ * Macro to sample the remaining PHY clocks left in the current frame. This -+ * may be used during debugging to determine the average time it takes to -+ * execute sections of code. There are two possible sample points, "a" and -+ * "b", so the _letter argument must be one of these values. -+ * -+ * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For -+ * example, "cat /sys/devices/lm0/hcd_frrem". -+ */ -+#define dwc_sample_frrem(_hcd, _qh, _letter) \ -+{ \ -+ hfnum_data_t hfnum; \ -+ dwc_otg_qtd_t *qtd; \ -+ qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \ -+ if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \ -+ hfnum.d32 = DWC_READ_REG32(&_hcd->core_if->host_if->host_global_regs->hfnum); \ -+ switch (hfnum.b.frnum & 0x7) { \ -+ case 7: \ -+ _hcd->hfnum_7_samples_##_letter++; \ -+ _hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \ -+ break; \ -+ case 0: \ -+ _hcd->hfnum_0_samples_##_letter++; \ -+ _hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \ -+ break; \ -+ default: \ -+ _hcd->hfnum_other_samples_##_letter++; \ -+ _hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \ -+ break; \ -+ } \ -+ } \ -+} -+#else -+#define dwc_sample_frrem(_hcd, _qh, _letter) -+#endif -+#endif -+#endif /* DWC_DEVICE_ONLY */ -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h 2015-11-29 09:42:39.919098694 +0100 -@@ -0,0 +1,417 @@ -+/* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_if.h $ -+ * $Revision: #12 $ -+ * $Date: 2011/10/26 $ -+ * $Change: 1873028 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+#ifndef DWC_DEVICE_ONLY -+#ifndef __DWC_HCD_IF_H__ -+#define __DWC_HCD_IF_H__ -+ -+#include "dwc_otg_core_if.h" -+ -+/** @file -+ * This file defines DWC_OTG HCD Core API. -+ */ -+ -+struct dwc_otg_hcd; -+typedef struct dwc_otg_hcd dwc_otg_hcd_t; -+ -+struct dwc_otg_hcd_urb; -+typedef struct dwc_otg_hcd_urb dwc_otg_hcd_urb_t; -+ -+/** @name HCD Function Driver Callbacks */ -+/** @{ */ -+ -+/** This function is called whenever core switches to host mode. */ -+typedef int (*dwc_otg_hcd_start_cb_t) (dwc_otg_hcd_t * hcd); -+ -+/** This function is called when device has been disconnected */ -+typedef int (*dwc_otg_hcd_disconnect_cb_t) (dwc_otg_hcd_t * hcd); -+ -+/** Wrapper provides this function to HCD to core, so it can get hub information to which device is connected */ -+typedef int (*dwc_otg_hcd_hub_info_from_urb_cb_t) (dwc_otg_hcd_t * hcd, -+ void *urb_handle, -+ uint32_t * hub_addr, -+ uint32_t * port_addr); -+/** Via this function HCD core gets device speed */ -+typedef int (*dwc_otg_hcd_speed_from_urb_cb_t) (dwc_otg_hcd_t * hcd, -+ void *urb_handle); -+ -+/** This function is called when urb is completed */ -+typedef int (*dwc_otg_hcd_complete_urb_cb_t) (dwc_otg_hcd_t * hcd, -+ void *urb_handle, -+ dwc_otg_hcd_urb_t * dwc_otg_urb, -+ int32_t status); -+ -+/** Via this function HCD core gets b_hnp_enable parameter */ -+typedef int (*dwc_otg_hcd_get_b_hnp_enable) (dwc_otg_hcd_t * hcd); -+ -+struct dwc_otg_hcd_function_ops { -+ dwc_otg_hcd_start_cb_t start; -+ dwc_otg_hcd_disconnect_cb_t disconnect; -+ dwc_otg_hcd_hub_info_from_urb_cb_t hub_info; -+ dwc_otg_hcd_speed_from_urb_cb_t speed; -+ dwc_otg_hcd_complete_urb_cb_t complete; -+ dwc_otg_hcd_get_b_hnp_enable get_b_hnp_enable; -+}; -+/** @} */ -+ -+/** @name HCD Core API */ -+/** @{ */ -+/** This function allocates dwc_otg_hcd structure and returns pointer on it. */ -+extern dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void); -+ -+/** This function should be called to initiate HCD Core. -+ * -+ * @param hcd The HCD -+ * @param core_if The DWC_OTG Core -+ * -+ * Returns -DWC_E_NO_MEMORY if no enough memory. -+ * Returns 0 on success -+ */ -+extern int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if); -+ -+/** Frees HCD -+ * -+ * @param hcd The HCD -+ */ -+extern void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd); -+ -+/** This function should be called on every hardware interrupt. -+ * -+ * @param dwc_otg_hcd The HCD -+ * -+ * Returns non zero if interrupt is handled -+ * Return 0 if interrupt is not handled -+ */ -+extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd); -+ -+/** This function is used to handle the fast interrupt -+ * -+ */ -+extern void __attribute__ ((naked)) dwc_otg_hcd_handle_fiq(void); -+ -+/** -+ * Returns private data set by -+ * dwc_otg_hcd_set_priv_data function. -+ * -+ * @param hcd The HCD -+ */ -+extern void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd); -+ -+/** -+ * Set private data. -+ * -+ * @param hcd The HCD -+ * @param priv_data pointer to be stored in private data -+ */ -+extern void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data); -+ -+/** -+ * This function initializes the HCD Core. -+ * -+ * @param hcd The HCD -+ * @param fops The Function Driver Operations data structure containing pointers to all callbacks. -+ * -+ * Returns -DWC_E_NO_DEVICE if Core is currently is in device mode. -+ * Returns 0 on success -+ */ -+extern int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd, -+ struct dwc_otg_hcd_function_ops *fops); -+ -+/** -+ * Halts the DWC_otg host mode operations in a clean manner. USB transfers are -+ * stopped. -+ * -+ * @param hcd The HCD -+ */ -+extern void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd); -+ -+/** -+ * Handles hub class-specific requests. -+ * -+ * @param dwc_otg_hcd The HCD -+ * @param typeReq Request Type -+ * @param wValue wValue from control request -+ * @param wIndex wIndex from control request -+ * @param buf data buffer -+ * @param wLength data buffer length -+ * -+ * Returns -DWC_E_INVALID if invalid argument is passed -+ * Returns 0 on success -+ */ -+extern int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd, -+ uint16_t typeReq, uint16_t wValue, -+ uint16_t wIndex, uint8_t * buf, -+ uint16_t wLength); -+ -+/** -+ * Returns otg port number. -+ * -+ * @param hcd The HCD -+ */ -+extern uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd); -+ -+/** -+ * Returns OTG version - either 1.3 or 2.0. -+ * -+ * @param core_if The core_if structure pointer -+ */ -+extern uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if); -+ -+/** -+ * Returns 1 if currently core is acting as B host, and 0 otherwise. -+ * -+ * @param hcd The HCD -+ */ -+extern uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd); -+ -+/** -+ * Returns current frame number. -+ * -+ * @param hcd The HCD -+ */ -+extern int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * hcd); -+ -+/** -+ * Dumps hcd state. -+ * -+ * @param hcd The HCD -+ */ -+extern void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd); -+ -+/** -+ * Dump the average frame remaining at SOF. This can be used to -+ * determine average interrupt latency. Frame remaining is also shown for -+ * start transfer and two additional sample points. -+ * Currently this function is not implemented. -+ * -+ * @param hcd The HCD -+ */ -+extern void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd); -+ -+/** -+ * Sends LPM transaction to the local device. -+ * -+ * @param hcd The HCD -+ * @param devaddr Device Address -+ * @param hird Host initiated resume duration -+ * @param bRemoteWake Value of bRemoteWake field in LPM transaction -+ * -+ * Returns negative value if sending LPM transaction was not succeeded. -+ * Returns 0 on success. -+ */ -+extern int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr, -+ uint8_t hird, uint8_t bRemoteWake); -+ -+/* URB interface */ -+ -+/** -+ * Allocates memory for dwc_otg_hcd_urb structure. -+ * Allocated memory should be freed by call of DWC_FREE. -+ * -+ * @param hcd The HCD -+ * @param iso_desc_count Count of ISOC descriptors -+ * @param atomic_alloc Specefies whether to perform atomic allocation. -+ */ -+extern dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd, -+ int iso_desc_count, -+ int atomic_alloc); -+ -+/** -+ * Set pipe information in URB. -+ * -+ * @param hcd_urb DWC_OTG URB -+ * @param devaddr Device Address -+ * @param ep_num Endpoint Number -+ * @param ep_type Endpoint Type -+ * @param ep_dir Endpoint Direction -+ * @param mps Max Packet Size -+ */ -+extern void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * hcd_urb, -+ uint8_t devaddr, uint8_t ep_num, -+ uint8_t ep_type, uint8_t ep_dir, -+ uint16_t mps); -+ -+/* Transfer flags */ -+#define URB_GIVEBACK_ASAP 0x1 -+#define URB_SEND_ZERO_PACKET 0x2 -+ -+/** -+ * Sets dwc_otg_hcd_urb parameters. -+ * -+ * @param urb DWC_OTG URB allocated by dwc_otg_hcd_urb_alloc function. -+ * @param urb_handle Unique handle for request, this will be passed back -+ * to function driver in completion callback. -+ * @param buf The buffer for the data -+ * @param dma The DMA buffer for the data -+ * @param buflen Transfer length -+ * @param sp Buffer for setup data -+ * @param sp_dma DMA address of setup data buffer -+ * @param flags Transfer flags -+ * @param interval Polling interval for interrupt or isochronous transfers. -+ */ -+extern void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * urb, -+ void *urb_handle, void *buf, -+ dwc_dma_t dma, uint32_t buflen, void *sp, -+ dwc_dma_t sp_dma, uint32_t flags, -+ uint16_t interval); -+ -+/** Gets status from dwc_otg_hcd_urb -+ * -+ * @param dwc_otg_urb DWC_OTG URB -+ */ -+extern uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb); -+ -+/** Gets actual length from dwc_otg_hcd_urb -+ * -+ * @param dwc_otg_urb DWC_OTG URB -+ */ -+extern uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t * -+ dwc_otg_urb); -+ -+/** Gets error count from dwc_otg_hcd_urb. Only for ISOC URBs -+ * -+ * @param dwc_otg_urb DWC_OTG URB -+ */ -+extern uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t * -+ dwc_otg_urb); -+ -+/** Set ISOC descriptor offset and length -+ * -+ * @param dwc_otg_urb DWC_OTG URB -+ * @param desc_num ISOC descriptor number -+ * @param offset Offset from beginig of buffer. -+ * @param length Transaction length -+ */ -+extern void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb, -+ int desc_num, uint32_t offset, -+ uint32_t length); -+ -+/** Get status of ISOC descriptor, specified by desc_num -+ * -+ * @param dwc_otg_urb DWC_OTG URB -+ * @param desc_num ISOC descriptor number -+ */ -+extern uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t * -+ dwc_otg_urb, int desc_num); -+ -+/** Get actual length of ISOC descriptor, specified by desc_num -+ * -+ * @param dwc_otg_urb DWC_OTG URB -+ * @param desc_num ISOC descriptor number -+ */ -+extern uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t * -+ dwc_otg_urb, -+ int desc_num); -+ -+/** Queue URB. After transfer is completes, the complete callback will be called with the URB status -+ * -+ * @param dwc_otg_hcd The HCD -+ * @param dwc_otg_urb DWC_OTG URB -+ * @param ep_handle Out parameter for returning endpoint handle -+ * @param atomic_alloc Flag to do atomic allocation if needed -+ * -+ * Returns -DWC_E_NO_DEVICE if no device is connected. -+ * Returns -DWC_E_NO_MEMORY if there is no enough memory. -+ * Returns 0 on success. -+ */ -+extern int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * dwc_otg_hcd, -+ dwc_otg_hcd_urb_t * dwc_otg_urb, -+ void **ep_handle, int atomic_alloc); -+ -+/** De-queue the specified URB -+ * -+ * @param dwc_otg_hcd The HCD -+ * @param dwc_otg_urb DWC_OTG URB -+ */ -+extern int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * dwc_otg_hcd, -+ dwc_otg_hcd_urb_t * dwc_otg_urb); -+ -+/** Frees resources in the DWC_otg controller related to a given endpoint. -+ * Any URBs for the endpoint must already be dequeued. -+ * -+ * @param hcd The HCD -+ * @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function -+ * @param retry Number of retries if there are queued transfers. -+ * -+ * Returns -DWC_E_INVALID if invalid arguments are passed. -+ * Returns 0 on success -+ */ -+extern int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle, -+ int retry); -+ -+/* Resets the data toggle in qh structure. This function can be called from -+ * usb_clear_halt routine. -+ * -+ * @param hcd The HCD -+ * @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function -+ * -+ * Returns -DWC_E_INVALID if invalid arguments are passed. -+ * Returns 0 on success -+ */ -+extern int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle); -+ -+/** Returns 1 if status of specified port is changed and 0 otherwise. -+ * -+ * @param hcd The HCD -+ * @param port Port number -+ */ -+extern int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port); -+ -+/** Call this function to check if bandwidth was allocated for specified endpoint. -+ * Only for ISOC and INTERRUPT endpoints. -+ * -+ * @param hcd The HCD -+ * @param ep_handle Endpoint handle -+ */ -+extern int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd, -+ void *ep_handle); -+ -+/** Call this function to check if bandwidth was freed for specified endpoint. -+ * -+ * @param hcd The HCD -+ * @param ep_handle Endpoint handle -+ */ -+extern int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle); -+ -+/** Returns bandwidth allocated for specified endpoint in microseconds. -+ * Only for ISOC and INTERRUPT endpoints. -+ * -+ * @param hcd The HCD -+ * @param ep_handle Endpoint handle -+ */ -+extern uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd, -+ void *ep_handle); -+ -+/** @} */ -+ -+#endif /* __DWC_HCD_IF_H__ */ -+#endif /* DWC_DEVICE_ONLY */ -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c 2015-11-29 09:42:39.919098694 +0100 -@@ -0,0 +1,2714 @@ -+/* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $ -+ * $Revision: #89 $ -+ * $Date: 2011/10/20 $ -+ * $Change: 1869487 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+#ifndef DWC_DEVICE_ONLY -+ -+#include "dwc_otg_hcd.h" -+#include "dwc_otg_regs.h" -+ -+#include -+#include -+ -+ -+extern bool microframe_schedule; -+ -+/** @file -+ * This file contains the implementation of the HCD Interrupt handlers. -+ */ -+ -+int fiq_done, int_done; -+ -+#ifdef FIQ_DEBUG -+char buffer[1000*16]; -+int wptr; -+void notrace _fiq_print(FIQDBG_T dbg_lvl, char *fmt, ...) -+{ -+ FIQDBG_T dbg_lvl_req = FIQDBG_PORTHUB; -+ va_list args; -+ char text[17]; -+ hfnum_data_t hfnum = { .d32 = FIQ_READ(dwc_regs_base + 0x408) }; -+ -+ if(dbg_lvl & dbg_lvl_req || dbg_lvl == FIQDBG_ERR) -+ { -+ local_fiq_disable(); -+ snprintf(text, 9, "%4d%d:%d ", hfnum.b.frnum/8, hfnum.b.frnum%8, 8 - hfnum.b.frrem/937); -+ va_start(args, fmt); -+ vsnprintf(text+8, 9, fmt, args); -+ va_end(args); -+ -+ memcpy(buffer + wptr, text, 16); -+ wptr = (wptr + 16) % sizeof(buffer); -+ local_fiq_enable(); -+ } -+} -+#endif -+ -+/** This function handles interrupts for the HCD. */ -+int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd) -+{ -+ int retval = 0; -+ static int last_time; -+ dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; -+ gintsts_data_t gintsts; -+ gintmsk_data_t gintmsk; -+ hfnum_data_t hfnum; -+ haintmsk_data_t haintmsk; -+ -+#ifdef DEBUG -+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; -+ -+#endif -+ -+ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts); -+ gintmsk.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk); -+ -+ /* Exit from ISR if core is hibernated */ -+ if (core_if->hibernation_suspend == 1) { -+ goto exit_handler_routine; -+ } -+ DWC_SPINLOCK(dwc_otg_hcd->lock); -+ /* Check if HOST Mode */ -+ if (dwc_otg_is_host_mode(core_if)) { -+ if (fiq_enable) { -+ local_fiq_disable(); -+ fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock); -+ /* Pull in from the FIQ's disabled mask */ -+ gintmsk.d32 = gintmsk.d32 | ~(dwc_otg_hcd->fiq_state->gintmsk_saved.d32); -+ dwc_otg_hcd->fiq_state->gintmsk_saved.d32 = ~0; -+ } -+ -+ if (fiq_fsm_enable && ( 0x0000FFFF & ~(dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint))) { -+ gintsts.b.hcintr = 1; -+ } -+ -+ /* Danger will robinson: fake a SOF if necessary */ -+ if (fiq_fsm_enable && (dwc_otg_hcd->fiq_state->gintmsk_saved.b.sofintr == 1)) { -+ gintsts.b.sofintr = 1; -+ } -+ gintsts.d32 &= gintmsk.d32; -+ -+ if (fiq_enable) { -+ fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock); -+ local_fiq_enable(); -+ } -+ -+ if (!gintsts.d32) { -+ goto exit_handler_routine; -+ } -+ -+#ifdef DEBUG -+ // We should be OK doing this because the common interrupts should already have been serviced -+ /* Don't print debug message in the interrupt handler on SOF */ -+#ifndef DEBUG_SOF -+ if (gintsts.d32 != DWC_SOF_INTR_MASK) -+#endif -+ DWC_DEBUGPL(DBG_HCDI, "\n"); -+#endif -+ -+#ifdef DEBUG -+#ifndef DEBUG_SOF -+ if (gintsts.d32 != DWC_SOF_INTR_MASK) -+#endif -+ DWC_DEBUGPL(DBG_HCDI, -+ "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x core_if=%p\n", -+ gintsts.d32, core_if); -+#endif -+ hfnum.d32 = DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->host_global_regs->hfnum); -+ if (gintsts.b.sofintr) { -+ retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd); -+ } -+ -+ if (gintsts.b.rxstsqlvl) { -+ retval |= -+ dwc_otg_hcd_handle_rx_status_q_level_intr -+ (dwc_otg_hcd); -+ } -+ if (gintsts.b.nptxfempty) { -+ retval |= -+ dwc_otg_hcd_handle_np_tx_fifo_empty_intr -+ (dwc_otg_hcd); -+ } -+ if (gintsts.b.i2cintr) { -+ /** @todo Implement i2cintr handler. */ -+ } -+ if (gintsts.b.portintr) { -+ -+ gintmsk_data_t gintmsk = { .b.portintr = 1}; -+ retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd); -+ if (fiq_enable) { -+ local_fiq_disable(); -+ fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock); -+ DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32); -+ fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock); -+ local_fiq_enable(); -+ } else { -+ DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32); -+ } -+ } -+ if (gintsts.b.hcintr) { -+ retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd); -+ } -+ if (gintsts.b.ptxfempty) { -+ retval |= -+ dwc_otg_hcd_handle_perio_tx_fifo_empty_intr -+ (dwc_otg_hcd); -+ } -+#ifdef DEBUG -+#ifndef DEBUG_SOF -+ if (gintsts.d32 != DWC_SOF_INTR_MASK) -+#endif -+ { -+ DWC_DEBUGPL(DBG_HCDI, -+ "DWC OTG HCD Finished Servicing Interrupts\n"); -+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n", -+ DWC_READ_REG32(&global_regs->gintsts)); -+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n", -+ DWC_READ_REG32(&global_regs->gintmsk)); -+ } -+#endif -+ -+#ifdef DEBUG -+#ifndef DEBUG_SOF -+ if (gintsts.d32 != DWC_SOF_INTR_MASK) -+#endif -+ DWC_DEBUGPL(DBG_HCDI, "\n"); -+#endif -+ -+ } -+ -+exit_handler_routine: -+ if (fiq_enable) { -+ gintmsk_data_t gintmsk_new; -+ haintmsk_data_t haintmsk_new; -+ local_fiq_disable(); -+ fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock); -+ gintmsk_new.d32 = *(volatile uint32_t *)&dwc_otg_hcd->fiq_state->gintmsk_saved.d32; -+ if(fiq_fsm_enable) -+ haintmsk_new.d32 = *(volatile uint32_t *)&dwc_otg_hcd->fiq_state->haintmsk_saved.d32; -+ else -+ haintmsk_new.d32 = 0x0000FFFF; -+ -+ /* The FIQ could have sneaked another interrupt in. If so, don't clear MPHI */ -+ if ((gintmsk_new.d32 == ~0) && (haintmsk_new.d32 == 0x0000FFFF)) { -+ DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.intstat, (1<<16)); -+ if (dwc_otg_hcd->fiq_state->mphi_int_count >= 50) { -+ fiq_print(FIQDBG_INT, dwc_otg_hcd->fiq_state, "MPHI CLR"); -+ DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl, ((1<<31) + (1<<16))); -+ while (!(DWC_READ_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl) & (1 << 17))) -+ ; -+ DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl, (1<<31)); -+ dwc_otg_hcd->fiq_state->mphi_int_count = 0; -+ } -+ int_done++; -+ } -+ haintmsk.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->haintmsk); -+ /* Re-enable interrupts that the FIQ masked (first time round) */ -+ FIQ_WRITE(dwc_otg_hcd->fiq_state->dwc_regs_base + GINTMSK, gintmsk.d32); -+ fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock); -+ local_fiq_enable(); -+ -+ if ((jiffies / HZ) > last_time) { -+ //dwc_otg_qh_t *qh; -+ //dwc_list_link_t *cur; -+ /* Once a second output the fiq and irq numbers, useful for debug */ -+ last_time = jiffies / HZ; -+ // DWC_WARN("np_kick=%d AHC=%d sched_frame=%d cur_frame=%d int_done=%d fiq_done=%d", -+ // dwc_otg_hcd->fiq_state->kick_np_queues, dwc_otg_hcd->available_host_channels, -+ // dwc_otg_hcd->fiq_state->next_sched_frame, hfnum.b.frnum, int_done, dwc_otg_hcd->fiq_state->fiq_done); -+ //printk(KERN_WARNING "Periodic queues:\n"); -+ } -+ } -+ -+ DWC_SPINUNLOCK(dwc_otg_hcd->lock); -+ return retval; -+} -+ -+#ifdef DWC_TRACK_MISSED_SOFS -+ -+#warning Compiling code to track missed SOFs -+#define FRAME_NUM_ARRAY_SIZE 1000 -+/** -+ * This function is for debug only. -+ */ -+static inline void track_missed_sofs(uint16_t curr_frame_number) -+{ -+ static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE]; -+ static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE]; -+ static int frame_num_idx = 0; -+ static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM; -+ static int dumped_frame_num_array = 0; -+ -+ if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) { -+ if (((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) != -+ curr_frame_number) { -+ frame_num_array[frame_num_idx] = curr_frame_number; -+ last_frame_num_array[frame_num_idx++] = last_frame_num; -+ } -+ } else if (!dumped_frame_num_array) { -+ int i; -+ DWC_PRINTF("Frame Last Frame\n"); -+ DWC_PRINTF("----- ----------\n"); -+ for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) { -+ DWC_PRINTF("0x%04x 0x%04x\n", -+ frame_num_array[i], last_frame_num_array[i]); -+ } -+ dumped_frame_num_array = 1; -+ } -+ last_frame_num = curr_frame_number; -+} -+#endif -+ -+/** -+ * Handles the start-of-frame interrupt in host mode. Non-periodic -+ * transactions may be queued to the DWC_otg controller for the current -+ * (micro)frame. Periodic transactions may be queued to the controller for the -+ * next (micro)frame. -+ */ -+int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * hcd) -+{ -+ hfnum_data_t hfnum; -+ gintsts_data_t gintsts = { .d32 = 0 }; -+ dwc_list_link_t *qh_entry; -+ dwc_otg_qh_t *qh; -+ dwc_otg_transaction_type_e tr_type; -+ int did_something = 0; -+ int32_t next_sched_frame = -1; -+ -+ hfnum.d32 = -+ DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum); -+ -+#ifdef DEBUG_SOF -+ DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n"); -+#endif -+ hcd->frame_number = hfnum.b.frnum; -+ -+#ifdef DEBUG -+ hcd->frrem_accum += hfnum.b.frrem; -+ hcd->frrem_samples++; -+#endif -+ -+#ifdef DWC_TRACK_MISSED_SOFS -+ track_missed_sofs(hcd->frame_number); -+#endif -+ /* Determine whether any periodic QHs should be executed. */ -+ qh_entry = DWC_LIST_FIRST(&hcd->periodic_sched_inactive); -+ while (qh_entry != &hcd->periodic_sched_inactive) { -+ qh = DWC_LIST_ENTRY(qh_entry, dwc_otg_qh_t, qh_list_entry); -+ qh_entry = qh_entry->next; -+ if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) { -+ -+ /* -+ * Move QH to the ready list to be executed next -+ * (micro)frame. -+ */ -+ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready, -+ &qh->qh_list_entry); -+ -+ did_something = 1; -+ } -+ else -+ { -+ if(next_sched_frame < 0 || dwc_frame_num_le(qh->sched_frame, next_sched_frame)) -+ { -+ next_sched_frame = qh->sched_frame; -+ } -+ } -+ } -+ if (fiq_enable) -+ hcd->fiq_state->next_sched_frame = next_sched_frame; -+ -+ tr_type = dwc_otg_hcd_select_transactions(hcd); -+ if (tr_type != DWC_OTG_TRANSACTION_NONE) { -+ dwc_otg_hcd_queue_transactions(hcd, tr_type); -+ did_something = 1; -+ } -+ -+ /* Clear interrupt - but do not trample on the FIQ sof */ -+ if (!fiq_fsm_enable) { -+ gintsts.b.sofintr = 1; -+ DWC_WRITE_REG32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32); -+ } -+ return 1; -+} -+ -+/** Handles the Rx Status Queue Level Interrupt, which indicates that there is at -+ * least one packet in the Rx FIFO. The packets are moved from the FIFO to -+ * memory if the DWC_otg controller is operating in Slave mode. */ -+int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t * dwc_otg_hcd) -+{ -+ host_grxsts_data_t grxsts; -+ dwc_hc_t *hc = NULL; -+ -+ DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n"); -+ -+ grxsts.d32 = -+ DWC_READ_REG32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp); -+ -+ hc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum]; -+ if (!hc) { -+ DWC_ERROR("Unable to get corresponding channel\n"); -+ return 0; -+ } -+ -+ /* Packet Status */ -+ DWC_DEBUGPL(DBG_HCDV, " Ch num = %d\n", grxsts.b.chnum); -+ DWC_DEBUGPL(DBG_HCDV, " Count = %d\n", grxsts.b.bcnt); -+ DWC_DEBUGPL(DBG_HCDV, " DPID = %d, hc.dpid = %d\n", grxsts.b.dpid, -+ hc->data_pid_start); -+ DWC_DEBUGPL(DBG_HCDV, " PStatus = %d\n", grxsts.b.pktsts); -+ -+ switch (grxsts.b.pktsts) { -+ case DWC_GRXSTS_PKTSTS_IN: -+ /* Read the data into the host buffer. */ -+ if (grxsts.b.bcnt > 0) { -+ dwc_otg_read_packet(dwc_otg_hcd->core_if, -+ hc->xfer_buff, grxsts.b.bcnt); -+ -+ /* Update the HC fields for the next packet received. */ -+ hc->xfer_count += grxsts.b.bcnt; -+ hc->xfer_buff += grxsts.b.bcnt; -+ } -+ -+ case DWC_GRXSTS_PKTSTS_IN_XFER_COMP: -+ case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR: -+ case DWC_GRXSTS_PKTSTS_CH_HALTED: -+ /* Handled in interrupt, just ignore data */ -+ break; -+ default: -+ DWC_ERROR("RX_STS_Q Interrupt: Unknown status %d\n", -+ grxsts.b.pktsts); -+ break; -+ } -+ -+ return 1; -+} -+ -+/** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More -+ * data packets may be written to the FIFO for OUT transfers. More requests -+ * may be written to the non-periodic request queue for IN transfers. This -+ * interrupt is enabled only in Slave mode. */ -+int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd) -+{ -+ DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n"); -+ dwc_otg_hcd_queue_transactions(dwc_otg_hcd, -+ DWC_OTG_TRANSACTION_NON_PERIODIC); -+ return 1; -+} -+ -+/** This interrupt occurs when the periodic Tx FIFO is half-empty. More data -+ * packets may be written to the FIFO for OUT transfers. More requests may be -+ * written to the periodic request queue for IN transfers. This interrupt is -+ * enabled only in Slave mode. */ -+int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd) -+{ -+ DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n"); -+ dwc_otg_hcd_queue_transactions(dwc_otg_hcd, -+ DWC_OTG_TRANSACTION_PERIODIC); -+ return 1; -+} -+ -+/** There are multiple conditions that can cause a port interrupt. This function -+ * determines which interrupt conditions have occurred and handles them -+ * appropriately. */ -+int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd) -+{ -+ int retval = 0; -+ hprt0_data_t hprt0; -+ hprt0_data_t hprt0_modify; -+ -+ hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0); -+ hprt0_modify.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0); -+ -+ /* Clear appropriate bits in HPRT0 to clear the interrupt bit in -+ * GINTSTS */ -+ -+ hprt0_modify.b.prtena = 0; -+ hprt0_modify.b.prtconndet = 0; -+ hprt0_modify.b.prtenchng = 0; -+ hprt0_modify.b.prtovrcurrchng = 0; -+ -+ /* Port Connect Detected -+ * Set flag and clear if detected */ -+ if (dwc_otg_hcd->core_if->hibernation_suspend == 1) { -+ // Dont modify port status if we are in hibernation state -+ hprt0_modify.b.prtconndet = 1; -+ hprt0_modify.b.prtenchng = 1; -+ DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32); -+ hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0); -+ return retval; -+ } -+ -+ if (hprt0.b.prtconndet) { -+ /** @todo - check if steps performed in 'else' block should be perfromed regardles adp */ -+ if (dwc_otg_hcd->core_if->adp_enable && -+ dwc_otg_hcd->core_if->adp.vbuson_timer_started == 1) { -+ DWC_PRINTF("PORT CONNECT DETECTED ----------------\n"); -+ DWC_TIMER_CANCEL(dwc_otg_hcd->core_if->adp.vbuson_timer); -+ dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0; -+ /* TODO - check if this is required, as -+ * host initialization was already performed -+ * after initial ADP probing -+ */ -+ /*dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0; -+ dwc_otg_core_init(dwc_otg_hcd->core_if); -+ dwc_otg_enable_global_interrupts(dwc_otg_hcd->core_if); -+ cil_hcd_start(dwc_otg_hcd->core_if);*/ -+ } else { -+ -+ DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x " -+ "Port Connect Detected--\n", hprt0.d32); -+ dwc_otg_hcd->flags.b.port_connect_status_change = 1; -+ dwc_otg_hcd->flags.b.port_connect_status = 1; -+ hprt0_modify.b.prtconndet = 1; -+ -+ /* B-Device has connected, Delete the connection timer. */ -+ DWC_TIMER_CANCEL(dwc_otg_hcd->conn_timer); -+ } -+ /* The Hub driver asserts a reset when it sees port connect -+ * status change flag */ -+ retval |= 1; -+ } -+ -+ /* Port Enable Changed -+ * Clear if detected - Set internal flag if disabled */ -+ if (hprt0.b.prtenchng) { -+ DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x " -+ "Port Enable Changed--\n", hprt0.d32); -+ hprt0_modify.b.prtenchng = 1; -+ if (hprt0.b.prtena == 1) { -+ hfir_data_t hfir; -+ int do_reset = 0; -+ dwc_otg_core_params_t *params = -+ dwc_otg_hcd->core_if->core_params; -+ dwc_otg_core_global_regs_t *global_regs = -+ dwc_otg_hcd->core_if->core_global_regs; -+ dwc_otg_host_if_t *host_if = -+ dwc_otg_hcd->core_if->host_if; -+ -+ /* Every time when port enables calculate -+ * HFIR.FrInterval -+ */ -+ hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir); -+ hfir.b.frint = calc_frame_interval(dwc_otg_hcd->core_if); -+ DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32); -+ -+ /* Check if we need to adjust the PHY clock speed for -+ * low power and adjust it */ -+ if (params->host_support_fs_ls_low_power) { -+ gusbcfg_data_t usbcfg; -+ -+ usbcfg.d32 = -+ DWC_READ_REG32(&global_regs->gusbcfg); -+ -+ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED -+ || hprt0.b.prtspd == -+ DWC_HPRT0_PRTSPD_FULL_SPEED) { -+ /* -+ * Low power -+ */ -+ hcfg_data_t hcfg; -+ if (usbcfg.b.phylpwrclksel == 0) { -+ /* Set PHY low power clock select for FS/LS devices */ -+ usbcfg.b.phylpwrclksel = 1; -+ DWC_WRITE_REG32 -+ (&global_regs->gusbcfg, -+ usbcfg.d32); -+ do_reset = 1; -+ } -+ -+ hcfg.d32 = -+ DWC_READ_REG32 -+ (&host_if->host_global_regs->hcfg); -+ -+ if (hprt0.b.prtspd == -+ DWC_HPRT0_PRTSPD_LOW_SPEED -+ && params->host_ls_low_power_phy_clk -+ == -+ DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ) -+ { -+ /* 6 MHZ */ -+ DWC_DEBUGPL(DBG_CIL, -+ "FS_PHY programming HCFG to 6 MHz (Low Power)\n"); -+ if (hcfg.b.fslspclksel != -+ DWC_HCFG_6_MHZ) { -+ hcfg.b.fslspclksel = -+ DWC_HCFG_6_MHZ; -+ DWC_WRITE_REG32 -+ (&host_if->host_global_regs->hcfg, -+ hcfg.d32); -+ do_reset = 1; -+ } -+ } else { -+ /* 48 MHZ */ -+ DWC_DEBUGPL(DBG_CIL, -+ "FS_PHY programming HCFG to 48 MHz ()\n"); -+ if (hcfg.b.fslspclksel != -+ DWC_HCFG_48_MHZ) { -+ hcfg.b.fslspclksel = -+ DWC_HCFG_48_MHZ; -+ DWC_WRITE_REG32 -+ (&host_if->host_global_regs->hcfg, -+ hcfg.d32); -+ do_reset = 1; -+ } -+ } -+ } else { -+ /* -+ * Not low power -+ */ -+ if (usbcfg.b.phylpwrclksel == 1) { -+ usbcfg.b.phylpwrclksel = 0; -+ DWC_WRITE_REG32 -+ (&global_regs->gusbcfg, -+ usbcfg.d32); -+ do_reset = 1; -+ } -+ } -+ -+ if (do_reset) { -+ DWC_TASK_SCHEDULE(dwc_otg_hcd->reset_tasklet); -+ } -+ } -+ -+ if (!do_reset) { -+ /* Port has been enabled set the reset change flag */ -+ dwc_otg_hcd->flags.b.port_reset_change = 1; -+ } -+ } else { -+ dwc_otg_hcd->flags.b.port_enable_change = 1; -+ } -+ retval |= 1; -+ } -+ -+ /** Overcurrent Change Interrupt */ -+ if (hprt0.b.prtovrcurrchng) { -+ DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x " -+ "Port Overcurrent Changed--\n", hprt0.d32); -+ dwc_otg_hcd->flags.b.port_over_current_change = 1; -+ hprt0_modify.b.prtovrcurrchng = 1; -+ retval |= 1; -+ } -+ -+ /* Clear Port Interrupts */ -+ DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32); -+ -+ return retval; -+} -+ -+/** This interrupt indicates that one or more host channels has a pending -+ * interrupt. There are multiple conditions that can cause each host channel -+ * interrupt. This function determines which conditions have occurred for each -+ * host channel interrupt and handles them appropriately. */ -+int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd) -+{ -+ int i; -+ int retval = 0; -+ haint_data_t haint = { .d32 = 0 } ; -+ -+ /* Clear appropriate bits in HCINTn to clear the interrupt bit in -+ * GINTSTS */ -+ -+ if (!fiq_fsm_enable) -+ haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if); -+ -+ // Overwrite with saved interrupts from fiq handler -+ if(fiq_fsm_enable) -+ { -+ /* check the mask? */ -+ local_fiq_disable(); -+ fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock); -+ haint.b2.chint |= ~(dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint); -+ dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint = ~0; -+ fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock); -+ local_fiq_enable(); -+ } -+ -+ for (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) { -+ if (haint.b2.chint & (1 << i)) { -+ retval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i); -+ } -+ } -+ -+ return retval; -+} -+ -+/** -+ * Gets the actual length of a transfer after the transfer halts. _halt_status -+ * holds the reason for the halt. -+ * -+ * For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE, -+ * *short_read is set to 1 upon return if less than the requested -+ * number of bytes were transferred. Otherwise, *short_read is set to 0 upon -+ * return. short_read may also be NULL on entry, in which case it remains -+ * unchanged. -+ */ -+static uint32_t get_actual_xfer_length(dwc_hc_t * hc, -+ dwc_otg_hc_regs_t * hc_regs, -+ dwc_otg_qtd_t * qtd, -+ dwc_otg_halt_status_e halt_status, -+ int *short_read) -+{ -+ hctsiz_data_t hctsiz; -+ uint32_t length; -+ -+ if (short_read != NULL) { -+ *short_read = 0; -+ } -+ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz); -+ -+ if (halt_status == DWC_OTG_HC_XFER_COMPLETE) { -+ if (hc->ep_is_in) { -+ length = hc->xfer_len - hctsiz.b.xfersize; -+ if (short_read != NULL) { -+ *short_read = (hctsiz.b.xfersize != 0); -+ } -+ } else if (hc->qh->do_split) { -+ //length = split_out_xfersize[hc->hc_num]; -+ length = qtd->ssplit_out_xfer_count; -+ } else { -+ length = hc->xfer_len; -+ } -+ } else { -+ /* -+ * Must use the hctsiz.pktcnt field to determine how much data -+ * has been transferred. This field reflects the number of -+ * packets that have been transferred via the USB. This is -+ * always an integral number of packets if the transfer was -+ * halted before its normal completion. (Can't use the -+ * hctsiz.xfersize field because that reflects the number of -+ * bytes transferred via the AHB, not the USB). -+ */ -+ length = -+ (hc->start_pkt_count - hctsiz.b.pktcnt) * hc->max_packet; -+ } -+ -+ return length; -+} -+ -+/** -+ * Updates the state of the URB after a Transfer Complete interrupt on the -+ * host channel. Updates the actual_length field of the URB based on the -+ * number of bytes transferred via the host channel. Sets the URB status -+ * if the data transfer is finished. -+ * -+ * @return 1 if the data transfer specified by the URB is completely finished, -+ * 0 otherwise. -+ */ -+static int update_urb_state_xfer_comp(dwc_hc_t * hc, -+ dwc_otg_hc_regs_t * hc_regs, -+ dwc_otg_hcd_urb_t * urb, -+ dwc_otg_qtd_t * qtd) -+{ -+ int xfer_done = 0; -+ int short_read = 0; -+ -+ int xfer_length; -+ -+ xfer_length = get_actual_xfer_length(hc, hc_regs, qtd, -+ DWC_OTG_HC_XFER_COMPLETE, -+ &short_read); -+ -+ /* non DWORD-aligned buffer case handling. */ -+ if (hc->align_buff && xfer_length && hc->ep_is_in) { -+ dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf, -+ xfer_length); -+ } -+ -+ urb->actual_length += xfer_length; -+ -+ if (xfer_length && (hc->ep_type == DWC_OTG_EP_TYPE_BULK) && -+ (urb->flags & URB_SEND_ZERO_PACKET) -+ && (urb->actual_length == urb->length) -+ && !(urb->length % hc->max_packet)) { -+ xfer_done = 0; -+ } else if (short_read || urb->actual_length >= urb->length) { -+ xfer_done = 1; -+ urb->status = 0; -+ } -+ -+#ifdef DEBUG -+ { -+ hctsiz_data_t hctsiz; -+ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz); -+ DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n", -+ __func__, (hc->ep_is_in ? "IN" : "OUT"), -+ hc->hc_num); -+ DWC_DEBUGPL(DBG_HCDV, " hc->xfer_len %d\n", hc->xfer_len); -+ DWC_DEBUGPL(DBG_HCDV, " hctsiz.xfersize %d\n", -+ hctsiz.b.xfersize); -+ DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n", -+ urb->length); -+ DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n", -+ urb->actual_length); -+ DWC_DEBUGPL(DBG_HCDV, " short_read %d, xfer_done %d\n", -+ short_read, xfer_done); -+ } -+#endif -+ -+ return xfer_done; -+} -+ -+/* -+ * Save the starting data toggle for the next transfer. The data toggle is -+ * saved in the QH for non-control transfers and it's saved in the QTD for -+ * control transfers. -+ */ -+void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc, -+ dwc_otg_hc_regs_t * hc_regs, dwc_otg_qtd_t * qtd) -+{ -+ hctsiz_data_t hctsiz; -+ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz); -+ -+ if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) { -+ dwc_otg_qh_t *qh = hc->qh; -+ if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) { -+ qh->data_toggle = DWC_OTG_HC_PID_DATA0; -+ } else { -+ qh->data_toggle = DWC_OTG_HC_PID_DATA1; -+ } -+ } else { -+ if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) { -+ qtd->data_toggle = DWC_OTG_HC_PID_DATA0; -+ } else { -+ qtd->data_toggle = DWC_OTG_HC_PID_DATA1; -+ } -+ } -+} -+ -+/** -+ * Updates the state of an Isochronous URB when the transfer is stopped for -+ * any reason. The fields of the current entry in the frame descriptor array -+ * are set based on the transfer state and the input _halt_status. Completes -+ * the Isochronous URB if all the URB frames have been completed. -+ * -+ * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be -+ * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE. -+ */ -+static dwc_otg_halt_status_e -+update_isoc_urb_state(dwc_otg_hcd_t * hcd, -+ dwc_hc_t * hc, -+ dwc_otg_hc_regs_t * hc_regs, -+ dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status) -+{ -+ dwc_otg_hcd_urb_t *urb = qtd->urb; -+ dwc_otg_halt_status_e ret_val = halt_status; -+ struct dwc_otg_hcd_iso_packet_desc *frame_desc; -+ -+ frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; -+ switch (halt_status) { -+ case DWC_OTG_HC_XFER_COMPLETE: -+ frame_desc->status = 0; -+ frame_desc->actual_length = -+ get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL); -+ -+ /* non DWORD-aligned buffer case handling. */ -+ if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) { -+ dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset, -+ hc->qh->dw_align_buf, frame_desc->actual_length); -+ } -+ -+ break; -+ case DWC_OTG_HC_XFER_FRAME_OVERRUN: -+ urb->error_count++; -+ if (hc->ep_is_in) { -+ frame_desc->status = -DWC_E_NO_STREAM_RES; -+ } else { -+ frame_desc->status = -DWC_E_COMMUNICATION; -+ } -+ frame_desc->actual_length = 0; -+ break; -+ case DWC_OTG_HC_XFER_BABBLE_ERR: -+ urb->error_count++; -+ frame_desc->status = -DWC_E_OVERFLOW; -+ /* Don't need to update actual_length in this case. */ -+ break; -+ case DWC_OTG_HC_XFER_XACT_ERR: -+ urb->error_count++; -+ frame_desc->status = -DWC_E_PROTOCOL; -+ frame_desc->actual_length = -+ get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL); -+ -+ /* non DWORD-aligned buffer case handling. */ -+ if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) { -+ dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset, -+ hc->qh->dw_align_buf, frame_desc->actual_length); -+ } -+ /* Skip whole frame */ -+ if (hc->qh->do_split && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && -+ hc->ep_is_in && hcd->core_if->dma_enable) { -+ qtd->complete_split = 0; -+ qtd->isoc_split_offset = 0; -+ } -+ -+ break; -+ default: -+ DWC_ASSERT(1, "Unhandled _halt_status (%d)\n", halt_status); -+ break; -+ } -+ if (++qtd->isoc_frame_index == urb->packet_count) { -+ /* -+ * urb->status is not used for isoc transfers. -+ * The individual frame_desc statuses are used instead. -+ */ -+ hcd->fops->complete(hcd, urb->priv, urb, 0); -+ ret_val = DWC_OTG_HC_XFER_URB_COMPLETE; -+ } else { -+ ret_val = DWC_OTG_HC_XFER_COMPLETE; -+ } -+ return ret_val; -+} -+ -+/** -+ * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic -+ * QHs, removes the QH from the active non-periodic schedule. If any QTDs are -+ * still linked to the QH, the QH is added to the end of the inactive -+ * non-periodic schedule. For periodic QHs, removes the QH from the periodic -+ * schedule if no more QTDs are linked to the QH. -+ */ -+static void deactivate_qh(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, int free_qtd) -+{ -+ int continue_split = 0; -+ dwc_otg_qtd_t *qtd; -+ -+ DWC_DEBUGPL(DBG_HCDV, " %s(%p,%p,%d)\n", __func__, hcd, qh, free_qtd); -+ -+ qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); -+ -+ if (qtd->complete_split) { -+ continue_split = 1; -+ } else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID || -+ qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END) { -+ continue_split = 1; -+ } -+ -+ if (free_qtd) { -+ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh); -+ continue_split = 0; -+ } -+ -+ qh->channel = NULL; -+ dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split); -+} -+ -+/** -+ * Releases a host channel for use by other transfers. Attempts to select and -+ * queue more transactions since at least one host channel is available. -+ * -+ * @param hcd The HCD state structure. -+ * @param hc The host channel to release. -+ * @param qtd The QTD associated with the host channel. This QTD may be freed -+ * if the transfer is complete or an error has occurred. -+ * @param halt_status Reason the channel is being released. This status -+ * determines the actions taken by this function. -+ */ -+static void release_channel(dwc_otg_hcd_t * hcd, -+ dwc_hc_t * hc, -+ dwc_otg_qtd_t * qtd, -+ dwc_otg_halt_status_e halt_status) -+{ -+ dwc_otg_transaction_type_e tr_type; -+ int free_qtd; -+ dwc_irqflags_t flags; -+ dwc_spinlock_t *channel_lock = hcd->channel_lock; -+ -+ int hog_port = 0; -+ -+ DWC_DEBUGPL(DBG_HCDV, " %s: channel %d, halt_status %d, xfer_len %d\n", -+ __func__, hc->hc_num, halt_status, hc->xfer_len); -+ -+ if(fiq_fsm_enable && hc->do_split) { -+ if(!hc->ep_is_in && hc->ep_type == UE_ISOCHRONOUS) { -+ if(hc->xact_pos == DWC_HCSPLIT_XACTPOS_MID || -+ hc->xact_pos == DWC_HCSPLIT_XACTPOS_BEGIN) { -+ hog_port = 0; -+ } -+ } -+ } -+ -+ switch (halt_status) { -+ case DWC_OTG_HC_XFER_URB_COMPLETE: -+ free_qtd = 1; -+ break; -+ case DWC_OTG_HC_XFER_AHB_ERR: -+ case DWC_OTG_HC_XFER_STALL: -+ case DWC_OTG_HC_XFER_BABBLE_ERR: -+ free_qtd = 1; -+ break; -+ case DWC_OTG_HC_XFER_XACT_ERR: -+ if (qtd->error_count >= 3) { -+ DWC_DEBUGPL(DBG_HCDV, -+ " Complete URB with transaction error\n"); -+ free_qtd = 1; -+ qtd->urb->status = -DWC_E_PROTOCOL; -+ hcd->fops->complete(hcd, qtd->urb->priv, -+ qtd->urb, -DWC_E_PROTOCOL); -+ } else { -+ free_qtd = 0; -+ } -+ break; -+ case DWC_OTG_HC_XFER_URB_DEQUEUE: -+ /* -+ * The QTD has already been removed and the QH has been -+ * deactivated. Don't want to do anything except release the -+ * host channel and try to queue more transfers. -+ */ -+ goto cleanup; -+ case DWC_OTG_HC_XFER_NO_HALT_STATUS: -+ free_qtd = 0; -+ break; -+ case DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE: -+ DWC_DEBUGPL(DBG_HCDV, -+ " Complete URB with I/O error\n"); -+ free_qtd = 1; -+ qtd->urb->status = -DWC_E_IO; -+ hcd->fops->complete(hcd, qtd->urb->priv, -+ qtd->urb, -DWC_E_IO); -+ break; -+ default: -+ free_qtd = 0; -+ break; -+ } -+ -+ deactivate_qh(hcd, hc->qh, free_qtd); -+ -+cleanup: -+ /* -+ * Release the host channel for use by other transfers. The cleanup -+ * function clears the channel interrupt enables and conditions, so -+ * there's no need to clear the Channel Halted interrupt separately. -+ */ -+ if (fiq_fsm_enable && hcd->fiq_state->channel[hc->hc_num].fsm != FIQ_PASSTHROUGH) -+ dwc_otg_cleanup_fiq_channel(hcd, hc->hc_num); -+ dwc_otg_hc_cleanup(hcd->core_if, hc); -+ DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry); -+ -+ if (!microframe_schedule) { -+ switch (hc->ep_type) { -+ case DWC_OTG_EP_TYPE_CONTROL: -+ case DWC_OTG_EP_TYPE_BULK: -+ hcd->non_periodic_channels--; -+ break; -+ -+ default: -+ /* -+ * Don't release reservations for periodic channels here. -+ * That's done when a periodic transfer is descheduled (i.e. -+ * when the QH is removed from the periodic schedule). -+ */ -+ break; -+ } -+ } else { -+ -+ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags); -+ hcd->available_host_channels++; -+ fiq_print(FIQDBG_INT, hcd->fiq_state, "AHC = %d ", hcd->available_host_channels); -+ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); -+ } -+ -+ /* Try to queue more transfers now that there's a free channel. */ -+ tr_type = dwc_otg_hcd_select_transactions(hcd); -+ if (tr_type != DWC_OTG_TRANSACTION_NONE) { -+ dwc_otg_hcd_queue_transactions(hcd, tr_type); -+ } -+} -+ -+/** -+ * Halts a host channel. If the channel cannot be halted immediately because -+ * the request queue is full, this function ensures that the FIFO empty -+ * interrupt for the appropriate queue is enabled so that the halt request can -+ * be queued when there is space in the request queue. -+ * -+ * This function may also be called in DMA mode. In that case, the channel is -+ * simply released since the core always halts the channel automatically in -+ * DMA mode. -+ */ -+static void halt_channel(dwc_otg_hcd_t * hcd, -+ dwc_hc_t * hc, -+ dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status) -+{ -+ if (hcd->core_if->dma_enable) { -+ release_channel(hcd, hc, qtd, halt_status); -+ return; -+ } -+ -+ /* Slave mode processing... */ -+ dwc_otg_hc_halt(hcd->core_if, hc, halt_status); -+ -+ if (hc->halt_on_queue) { -+ gintmsk_data_t gintmsk = {.d32 = 0 }; -+ dwc_otg_core_global_regs_t *global_regs; -+ global_regs = hcd->core_if->core_global_regs; -+ -+ if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL || -+ hc->ep_type == DWC_OTG_EP_TYPE_BULK) { -+ /* -+ * Make sure the Non-periodic Tx FIFO empty interrupt -+ * is enabled so that the non-periodic schedule will -+ * be processed. -+ */ -+ gintmsk.b.nptxfempty = 1; -+ if (fiq_enable) { -+ local_fiq_disable(); -+ fiq_fsm_spin_lock(&hcd->fiq_state->lock); -+ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32); -+ fiq_fsm_spin_unlock(&hcd->fiq_state->lock); -+ local_fiq_enable(); -+ } else { -+ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32); -+ } -+ } else { -+ /* -+ * Move the QH from the periodic queued schedule to -+ * the periodic assigned schedule. This allows the -+ * halt to be queued when the periodic schedule is -+ * processed. -+ */ -+ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned, -+ &hc->qh->qh_list_entry); -+ -+ /* -+ * Make sure the Periodic Tx FIFO Empty interrupt is -+ * enabled so that the periodic schedule will be -+ * processed. -+ */ -+ gintmsk.b.ptxfempty = 1; -+ if (fiq_enable) { -+ local_fiq_disable(); -+ fiq_fsm_spin_lock(&hcd->fiq_state->lock); -+ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32); -+ fiq_fsm_spin_unlock(&hcd->fiq_state->lock); -+ local_fiq_enable(); -+ } else { -+ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32); -+ } -+ } -+ } -+} -+ -+/** -+ * Performs common cleanup for non-periodic transfers after a Transfer -+ * Complete interrupt. This function should be called after any endpoint type -+ * specific handling is finished to release the host channel. -+ */ -+static void complete_non_periodic_xfer(dwc_otg_hcd_t * hcd, -+ dwc_hc_t * hc, -+ dwc_otg_hc_regs_t * hc_regs, -+ dwc_otg_qtd_t * qtd, -+ dwc_otg_halt_status_e halt_status) -+{ -+ hcint_data_t hcint; -+ -+ qtd->error_count = 0; -+ -+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); -+ if (hcint.b.nyet) { -+ /* -+ * Got a NYET on the last transaction of the transfer. This -+ * means that the endpoint should be in the PING state at the -+ * beginning of the next transfer. -+ */ -+ hc->qh->ping_state = 1; -+ clear_hc_int(hc_regs, nyet); -+ } -+ -+ /* -+ * Always halt and release the host channel to make it available for -+ * more transfers. There may still be more phases for a control -+ * transfer or more data packets for a bulk transfer at this point, -+ * but the host channel is still halted. A channel will be reassigned -+ * to the transfer when the non-periodic schedule is processed after -+ * the channel is released. This allows transactions to be queued -+ * properly via dwc_otg_hcd_queue_transactions, which also enables the -+ * Tx FIFO Empty interrupt if necessary. -+ */ -+ if (hc->ep_is_in) { -+ /* -+ * IN transfers in Slave mode require an explicit disable to -+ * halt the channel. (In DMA mode, this call simply releases -+ * the channel.) -+ */ -+ halt_channel(hcd, hc, qtd, halt_status); -+ } else { -+ /* -+ * The channel is automatically disabled by the core for OUT -+ * transfers in Slave mode. -+ */ -+ release_channel(hcd, hc, qtd, halt_status); -+ } -+} -+ -+/** -+ * Performs common cleanup for periodic transfers after a Transfer Complete -+ * interrupt. This function should be called after any endpoint type specific -+ * handling is finished to release the host channel. -+ */ -+static void complete_periodic_xfer(dwc_otg_hcd_t * hcd, -+ dwc_hc_t * hc, -+ dwc_otg_hc_regs_t * hc_regs, -+ dwc_otg_qtd_t * qtd, -+ dwc_otg_halt_status_e halt_status) -+{ -+ hctsiz_data_t hctsiz; -+ qtd->error_count = 0; -+ -+ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz); -+ if (!hc->ep_is_in || hctsiz.b.pktcnt == 0) { -+ /* Core halts channel in these cases. */ -+ release_channel(hcd, hc, qtd, halt_status); -+ } else { -+ /* Flush any outstanding requests from the Tx queue. */ -+ halt_channel(hcd, hc, qtd, halt_status); -+ } -+} -+ -+static int32_t handle_xfercomp_isoc_split_in(dwc_otg_hcd_t * hcd, -+ dwc_hc_t * hc, -+ dwc_otg_hc_regs_t * hc_regs, -+ dwc_otg_qtd_t * qtd) -+{ -+ uint32_t len; -+ struct dwc_otg_hcd_iso_packet_desc *frame_desc; -+ frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; -+ -+ len = get_actual_xfer_length(hc, hc_regs, qtd, -+ DWC_OTG_HC_XFER_COMPLETE, NULL); -+ -+ if (!len) { -+ qtd->complete_split = 0; -+ qtd->isoc_split_offset = 0; -+ return 0; -+ } -+ frame_desc->actual_length += len; -+ -+ if (hc->align_buff && len) -+ dwc_memcpy(qtd->urb->buf + frame_desc->offset + -+ qtd->isoc_split_offset, hc->qh->dw_align_buf, len); -+ qtd->isoc_split_offset += len; -+ -+ if (frame_desc->length == frame_desc->actual_length) { -+ frame_desc->status = 0; -+ qtd->isoc_frame_index++; -+ qtd->complete_split = 0; -+ qtd->isoc_split_offset = 0; -+ } -+ -+ if (qtd->isoc_frame_index == qtd->urb->packet_count) { -+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); -+ } else { -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS); -+ } -+ -+ return 1; /* Indicates that channel released */ -+} -+ -+/** -+ * Handles a host channel Transfer Complete interrupt. This handler may be -+ * called in either DMA mode or Slave mode. -+ */ -+static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t * hcd, -+ dwc_hc_t * hc, -+ dwc_otg_hc_regs_t * hc_regs, -+ dwc_otg_qtd_t * qtd) -+{ -+ int urb_xfer_done; -+ dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE; -+ dwc_otg_hcd_urb_t *urb = qtd->urb; -+ int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info); -+ -+ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " -+ "Transfer Complete--\n", hc->hc_num); -+ -+ if (hcd->core_if->dma_desc_enable) { -+ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, halt_status); -+ if (pipe_type == UE_ISOCHRONOUS) { -+ /* Do not disable the interrupt, just clear it */ -+ clear_hc_int(hc_regs, xfercomp); -+ return 1; -+ } -+ goto handle_xfercomp_done; -+ } -+ -+ /* -+ * Handle xfer complete on CSPLIT. -+ */ -+ -+ if (hc->qh->do_split) { -+ if ((hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && hc->ep_is_in -+ && hcd->core_if->dma_enable) { -+ if (qtd->complete_split -+ && handle_xfercomp_isoc_split_in(hcd, hc, hc_regs, -+ qtd)) -+ goto handle_xfercomp_done; -+ } else { -+ qtd->complete_split = 0; -+ } -+ } -+ -+ /* Update the QTD and URB states. */ -+ switch (pipe_type) { -+ case UE_CONTROL: -+ switch (qtd->control_phase) { -+ case DWC_OTG_CONTROL_SETUP: -+ if (urb->length > 0) { -+ qtd->control_phase = DWC_OTG_CONTROL_DATA; -+ } else { -+ qtd->control_phase = DWC_OTG_CONTROL_STATUS; -+ } -+ DWC_DEBUGPL(DBG_HCDV, -+ " Control setup transaction done\n"); -+ halt_status = DWC_OTG_HC_XFER_COMPLETE; -+ break; -+ case DWC_OTG_CONTROL_DATA:{ -+ urb_xfer_done = -+ update_urb_state_xfer_comp(hc, hc_regs, urb, -+ qtd); -+ if (urb_xfer_done) { -+ qtd->control_phase = -+ DWC_OTG_CONTROL_STATUS; -+ DWC_DEBUGPL(DBG_HCDV, -+ " Control data transfer done\n"); -+ } else { -+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); -+ } -+ halt_status = DWC_OTG_HC_XFER_COMPLETE; -+ break; -+ } -+ case DWC_OTG_CONTROL_STATUS: -+ DWC_DEBUGPL(DBG_HCDV, " Control transfer complete\n"); -+ if (urb->status == -DWC_E_IN_PROGRESS) { -+ urb->status = 0; -+ } -+ hcd->fops->complete(hcd, urb->priv, urb, urb->status); -+ halt_status = DWC_OTG_HC_XFER_URB_COMPLETE; -+ break; -+ } -+ -+ complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status); -+ break; -+ case UE_BULK: -+ DWC_DEBUGPL(DBG_HCDV, " Bulk transfer complete\n"); -+ urb_xfer_done = -+ update_urb_state_xfer_comp(hc, hc_regs, urb, qtd); -+ if (urb_xfer_done) { -+ hcd->fops->complete(hcd, urb->priv, urb, urb->status); -+ halt_status = DWC_OTG_HC_XFER_URB_COMPLETE; -+ } else { -+ halt_status = DWC_OTG_HC_XFER_COMPLETE; -+ } -+ -+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); -+ complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status); -+ break; -+ case UE_INTERRUPT: -+ DWC_DEBUGPL(DBG_HCDV, " Interrupt transfer complete\n"); -+ urb_xfer_done = -+ update_urb_state_xfer_comp(hc, hc_regs, urb, qtd); -+ -+ /* -+ * Interrupt URB is done on the first transfer complete -+ * interrupt. -+ */ -+ if (urb_xfer_done) { -+ hcd->fops->complete(hcd, urb->priv, urb, urb->status); -+ halt_status = DWC_OTG_HC_XFER_URB_COMPLETE; -+ } else { -+ halt_status = DWC_OTG_HC_XFER_COMPLETE; -+ } -+ -+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); -+ complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status); -+ break; -+ case UE_ISOCHRONOUS: -+ DWC_DEBUGPL(DBG_HCDV, " Isochronous transfer complete\n"); -+ if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) { -+ halt_status = -+ update_isoc_urb_state(hcd, hc, hc_regs, qtd, -+ DWC_OTG_HC_XFER_COMPLETE); -+ } -+ complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status); -+ break; -+ } -+ -+handle_xfercomp_done: -+ disable_hc_int(hc_regs, xfercompl); -+ -+ return 1; -+} -+ -+/** -+ * Handles a host channel STALL interrupt. This handler may be called in -+ * either DMA mode or Slave mode. -+ */ -+static int32_t handle_hc_stall_intr(dwc_otg_hcd_t * hcd, -+ dwc_hc_t * hc, -+ dwc_otg_hc_regs_t * hc_regs, -+ dwc_otg_qtd_t * qtd) -+{ -+ dwc_otg_hcd_urb_t *urb = qtd->urb; -+ int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info); -+ -+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " -+ "STALL Received--\n", hc->hc_num); -+ -+ if (hcd->core_if->dma_desc_enable) { -+ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_STALL); -+ goto handle_stall_done; -+ } -+ -+ if (pipe_type == UE_CONTROL) { -+ hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE); -+ } -+ -+ if (pipe_type == UE_BULK || pipe_type == UE_INTERRUPT) { -+ hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE); -+ /* -+ * USB protocol requires resetting the data toggle for bulk -+ * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT) -+ * setup command is issued to the endpoint. Anticipate the -+ * CLEAR_FEATURE command since a STALL has occurred and reset -+ * the data toggle now. -+ */ -+ hc->qh->data_toggle = 0; -+ } -+ -+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL); -+ -+handle_stall_done: -+ disable_hc_int(hc_regs, stall); -+ -+ return 1; -+} -+ -+/* -+ * Updates the state of the URB when a transfer has been stopped due to an -+ * abnormal condition before the transfer completes. Modifies the -+ * actual_length field of the URB to reflect the number of bytes that have -+ * actually been transferred via the host channel. -+ */ -+static void update_urb_state_xfer_intr(dwc_hc_t * hc, -+ dwc_otg_hc_regs_t * hc_regs, -+ dwc_otg_hcd_urb_t * urb, -+ dwc_otg_qtd_t * qtd, -+ dwc_otg_halt_status_e halt_status) -+{ -+ uint32_t bytes_transferred = get_actual_xfer_length(hc, hc_regs, qtd, -+ halt_status, NULL); -+ /* non DWORD-aligned buffer case handling. */ -+ if (hc->align_buff && bytes_transferred && hc->ep_is_in) { -+ dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf, -+ bytes_transferred); -+ } -+ -+ urb->actual_length += bytes_transferred; -+ -+#ifdef DEBUG -+ { -+ hctsiz_data_t hctsiz; -+ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz); -+ DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n", -+ __func__, (hc->ep_is_in ? "IN" : "OUT"), -+ hc->hc_num); -+ DWC_DEBUGPL(DBG_HCDV, " hc->start_pkt_count %d\n", -+ hc->start_pkt_count); -+ DWC_DEBUGPL(DBG_HCDV, " hctsiz.pktcnt %d\n", hctsiz.b.pktcnt); -+ DWC_DEBUGPL(DBG_HCDV, " hc->max_packet %d\n", hc->max_packet); -+ DWC_DEBUGPL(DBG_HCDV, " bytes_transferred %d\n", -+ bytes_transferred); -+ DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n", -+ urb->actual_length); -+ DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n", -+ urb->length); -+ } -+#endif -+} -+ -+/** -+ * Handles a host channel NAK interrupt. This handler may be called in either -+ * DMA mode or Slave mode. -+ */ -+static int32_t handle_hc_nak_intr(dwc_otg_hcd_t * hcd, -+ dwc_hc_t * hc, -+ dwc_otg_hc_regs_t * hc_regs, -+ dwc_otg_qtd_t * qtd) -+{ -+ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " -+ "NAK Received--\n", hc->hc_num); -+ -+ /* -+ * When we get bulk NAKs then remember this so we holdoff on this qh until -+ * the beginning of the next frame -+ */ -+ switch(dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) { -+ case UE_BULK: -+ case UE_CONTROL: -+ if (nak_holdoff && qtd->qh->do_split) -+ hc->qh->nak_frame = dwc_otg_hcd_get_frame_number(hcd); -+ } -+ -+ /* -+ * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and -+ * interrupt. Re-start the SSPLIT transfer. -+ */ -+ if (hc->do_split) { -+ if (hc->complete_split) { -+ qtd->error_count = 0; -+ } -+ qtd->complete_split = 0; -+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK); -+ goto handle_nak_done; -+ } -+ -+ switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) { -+ case UE_CONTROL: -+ case UE_BULK: -+ if (hcd->core_if->dma_enable && hc->ep_is_in) { -+ /* -+ * NAK interrupts are enabled on bulk/control IN -+ * transfers in DMA mode for the sole purpose of -+ * resetting the error count after a transaction error -+ * occurs. The core will continue transferring data. -+ * Disable other interrupts unmasked for the same -+ * reason. -+ */ -+ disable_hc_int(hc_regs, datatglerr); -+ disable_hc_int(hc_regs, ack); -+ qtd->error_count = 0; -+ goto handle_nak_done; -+ } -+ -+ /* -+ * NAK interrupts normally occur during OUT transfers in DMA -+ * or Slave mode. For IN transfers, more requests will be -+ * queued as request queue space is available. -+ */ -+ qtd->error_count = 0; -+ -+ if (!hc->qh->ping_state) { -+ update_urb_state_xfer_intr(hc, hc_regs, -+ qtd->urb, qtd, -+ DWC_OTG_HC_XFER_NAK); -+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); -+ -+ if (hc->speed == DWC_OTG_EP_SPEED_HIGH) -+ hc->qh->ping_state = 1; -+ } -+ -+ /* -+ * Halt the channel so the transfer can be re-started from -+ * the appropriate point or the PING protocol will -+ * start/continue. -+ */ -+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK); -+ break; -+ case UE_INTERRUPT: -+ qtd->error_count = 0; -+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK); -+ break; -+ case UE_ISOCHRONOUS: -+ /* Should never get called for isochronous transfers. */ -+ DWC_ASSERT(1, "NACK interrupt for ISOC transfer\n"); -+ break; -+ } -+ -+handle_nak_done: -+ disable_hc_int(hc_regs, nak); -+ -+ return 1; -+} -+ -+/** -+ * Handles a host channel ACK interrupt. This interrupt is enabled when -+ * performing the PING protocol in Slave mode, when errors occur during -+ * either Slave mode or DMA mode, and during Start Split transactions. -+ */ -+static int32_t handle_hc_ack_intr(dwc_otg_hcd_t * hcd, -+ dwc_hc_t * hc, -+ dwc_otg_hc_regs_t * hc_regs, -+ dwc_otg_qtd_t * qtd) -+{ -+ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " -+ "ACK Received--\n", hc->hc_num); -+ -+ if (hc->do_split) { -+ /* -+ * Handle ACK on SSPLIT. -+ * ACK should not occur in CSPLIT. -+ */ -+ if (!hc->ep_is_in && hc->data_pid_start != DWC_OTG_HC_PID_SETUP) { -+ qtd->ssplit_out_xfer_count = hc->xfer_len; -+ } -+ if (!(hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)) { -+ /* Don't need complete for isochronous out transfers. */ -+ qtd->complete_split = 1; -+ } -+ -+ /* ISOC OUT */ -+ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) { -+ switch (hc->xact_pos) { -+ case DWC_HCSPLIT_XACTPOS_ALL: -+ break; -+ case DWC_HCSPLIT_XACTPOS_END: -+ qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL; -+ qtd->isoc_split_offset = 0; -+ break; -+ case DWC_HCSPLIT_XACTPOS_BEGIN: -+ case DWC_HCSPLIT_XACTPOS_MID: -+ /* -+ * For BEGIN or MID, calculate the length for -+ * the next microframe to determine the correct -+ * SSPLIT token, either MID or END. -+ */ -+ { -+ struct dwc_otg_hcd_iso_packet_desc -+ *frame_desc; -+ -+ frame_desc = -+ &qtd->urb-> -+ iso_descs[qtd->isoc_frame_index]; -+ qtd->isoc_split_offset += 188; -+ -+ if ((frame_desc->length - -+ qtd->isoc_split_offset) <= 188) { -+ qtd->isoc_split_pos = -+ DWC_HCSPLIT_XACTPOS_END; -+ } else { -+ qtd->isoc_split_pos = -+ DWC_HCSPLIT_XACTPOS_MID; -+ } -+ -+ } -+ break; -+ } -+ } else { -+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK); -+ } -+ } else { -+ /* -+ * An unmasked ACK on a non-split DMA transaction is -+ * for the sole purpose of resetting error counts. Disable other -+ * interrupts unmasked for the same reason. -+ */ -+ if(hcd->core_if->dma_enable) { -+ disable_hc_int(hc_regs, datatglerr); -+ disable_hc_int(hc_regs, nak); -+ } -+ qtd->error_count = 0; -+ -+ if (hc->qh->ping_state) { -+ hc->qh->ping_state = 0; -+ /* -+ * Halt the channel so the transfer can be re-started -+ * from the appropriate point. This only happens in -+ * Slave mode. In DMA mode, the ping_state is cleared -+ * when the transfer is started because the core -+ * automatically executes the PING, then the transfer. -+ */ -+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK); -+ } -+ } -+ -+ /* -+ * If the ACK occurred when _not_ in the PING state, let the channel -+ * continue transferring data after clearing the error count. -+ */ -+ -+ disable_hc_int(hc_regs, ack); -+ -+ return 1; -+} -+ -+/** -+ * Handles a host channel NYET interrupt. This interrupt should only occur on -+ * Bulk and Control OUT endpoints and for complete split transactions. If a -+ * NYET occurs at the same time as a Transfer Complete interrupt, it is -+ * handled in the xfercomp interrupt handler, not here. This handler may be -+ * called in either DMA mode or Slave mode. -+ */ -+static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t * hcd, -+ dwc_hc_t * hc, -+ dwc_otg_hc_regs_t * hc_regs, -+ dwc_otg_qtd_t * qtd) -+{ -+ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " -+ "NYET Received--\n", hc->hc_num); -+ -+ /* -+ * NYET on CSPLIT -+ * re-do the CSPLIT immediately on non-periodic -+ */ -+ if (hc->do_split && hc->complete_split) { -+ if (hc->ep_is_in && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) -+ && hcd->core_if->dma_enable) { -+ qtd->complete_split = 0; -+ qtd->isoc_split_offset = 0; -+ if (++qtd->isoc_frame_index == qtd->urb->packet_count) { -+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); -+ } -+ else -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS); -+ goto handle_nyet_done; -+ } -+ -+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || -+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { -+ int frnum = dwc_otg_hcd_get_frame_number(hcd); -+ -+ // With the FIQ running we only ever see the failed NYET -+ if (dwc_full_frame_num(frnum) != -+ dwc_full_frame_num(hc->qh->sched_frame) || -+ fiq_fsm_enable) { -+ /* -+ * No longer in the same full speed frame. -+ * Treat this as a transaction error. -+ */ -+#if 0 -+ /** @todo Fix system performance so this can -+ * be treated as an error. Right now complete -+ * splits cannot be scheduled precisely enough -+ * due to other system activity, so this error -+ * occurs regularly in Slave mode. -+ */ -+ qtd->error_count++; -+#endif -+ qtd->complete_split = 0; -+ halt_channel(hcd, hc, qtd, -+ DWC_OTG_HC_XFER_XACT_ERR); -+ /** @todo add support for isoc release */ -+ goto handle_nyet_done; -+ } -+ } -+ -+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET); -+ goto handle_nyet_done; -+ } -+ -+ hc->qh->ping_state = 1; -+ qtd->error_count = 0; -+ -+ update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd, -+ DWC_OTG_HC_XFER_NYET); -+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); -+ -+ /* -+ * Halt the channel and re-start the transfer so the PING -+ * protocol will start. -+ */ -+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET); -+ -+handle_nyet_done: -+ disable_hc_int(hc_regs, nyet); -+ return 1; -+} -+ -+/** -+ * Handles a host channel babble interrupt. This handler may be called in -+ * either DMA mode or Slave mode. -+ */ -+static int32_t handle_hc_babble_intr(dwc_otg_hcd_t * hcd, -+ dwc_hc_t * hc, -+ dwc_otg_hc_regs_t * hc_regs, -+ dwc_otg_qtd_t * qtd) -+{ -+ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " -+ "Babble Error--\n", hc->hc_num); -+ -+ if (hcd->core_if->dma_desc_enable) { -+ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, -+ DWC_OTG_HC_XFER_BABBLE_ERR); -+ goto handle_babble_done; -+ } -+ -+ if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) { -+ hcd->fops->complete(hcd, qtd->urb->priv, -+ qtd->urb, -DWC_E_OVERFLOW); -+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR); -+ } else { -+ dwc_otg_halt_status_e halt_status; -+ halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd, -+ DWC_OTG_HC_XFER_BABBLE_ERR); -+ halt_channel(hcd, hc, qtd, halt_status); -+ } -+ -+handle_babble_done: -+ disable_hc_int(hc_regs, bblerr); -+ return 1; -+} -+ -+/** -+ * Handles a host channel AHB error interrupt. This handler is only called in -+ * DMA mode. -+ */ -+static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t * hcd, -+ dwc_hc_t * hc, -+ dwc_otg_hc_regs_t * hc_regs, -+ dwc_otg_qtd_t * qtd) -+{ -+ hcchar_data_t hcchar; -+ hcsplt_data_t hcsplt; -+ hctsiz_data_t hctsiz; -+ uint32_t hcdma; -+ char *pipetype, *speed; -+ -+ dwc_otg_hcd_urb_t *urb = qtd->urb; -+ -+ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " -+ "AHB Error--\n", hc->hc_num); -+ -+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); -+ hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt); -+ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz); -+ hcdma = DWC_READ_REG32(&hc_regs->hcdma); -+ -+ DWC_ERROR("AHB ERROR, Channel %d\n", hc->hc_num); -+ DWC_ERROR(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32); -+ DWC_ERROR(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma); -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n"); -+ DWC_ERROR(" Device address: %d\n", -+ dwc_otg_hcd_get_dev_addr(&urb->pipe_info)); -+ DWC_ERROR(" Endpoint: %d, %s\n", -+ dwc_otg_hcd_get_ep_num(&urb->pipe_info), -+ (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT")); -+ -+ switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) { -+ case UE_CONTROL: -+ pipetype = "CONTROL"; -+ break; -+ case UE_BULK: -+ pipetype = "BULK"; -+ break; -+ case UE_INTERRUPT: -+ pipetype = "INTERRUPT"; -+ break; -+ case UE_ISOCHRONOUS: -+ pipetype = "ISOCHRONOUS"; -+ break; -+ default: -+ pipetype = "UNKNOWN"; -+ break; -+ } -+ -+ DWC_ERROR(" Endpoint type: %s\n", pipetype); -+ -+ switch (hc->speed) { -+ case DWC_OTG_EP_SPEED_HIGH: -+ speed = "HIGH"; -+ break; -+ case DWC_OTG_EP_SPEED_FULL: -+ speed = "FULL"; -+ break; -+ case DWC_OTG_EP_SPEED_LOW: -+ speed = "LOW"; -+ break; -+ default: -+ speed = "UNKNOWN"; -+ break; -+ }; -+ -+ DWC_ERROR(" Speed: %s\n", speed); -+ -+ DWC_ERROR(" Max packet size: %d\n", -+ dwc_otg_hcd_get_mps(&urb->pipe_info)); -+ DWC_ERROR(" Data buffer length: %d\n", urb->length); -+ DWC_ERROR(" Transfer buffer: %p, Transfer DMA: %p\n", -+ urb->buf, (void *)urb->dma); -+ DWC_ERROR(" Setup buffer: %p, Setup DMA: %p\n", -+ urb->setup_packet, (void *)urb->setup_dma); -+ DWC_ERROR(" Interval: %d\n", urb->interval); -+ -+ /* Core haltes the channel for Descriptor DMA mode */ -+ if (hcd->core_if->dma_desc_enable) { -+ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, -+ DWC_OTG_HC_XFER_AHB_ERR); -+ goto handle_ahberr_done; -+ } -+ -+ hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_IO); -+ -+ /* -+ * Force a channel halt. Don't call halt_channel because that won't -+ * write to the HCCHARn register in DMA mode to force the halt. -+ */ -+ dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_AHB_ERR); -+handle_ahberr_done: -+ disable_hc_int(hc_regs, ahberr); -+ return 1; -+} -+ -+/** -+ * Handles a host channel transaction error interrupt. This handler may be -+ * called in either DMA mode or Slave mode. -+ */ -+static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t * hcd, -+ dwc_hc_t * hc, -+ dwc_otg_hc_regs_t * hc_regs, -+ dwc_otg_qtd_t * qtd) -+{ -+ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " -+ "Transaction Error--\n", hc->hc_num); -+ -+ if (hcd->core_if->dma_desc_enable) { -+ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, -+ DWC_OTG_HC_XFER_XACT_ERR); -+ goto handle_xacterr_done; -+ } -+ -+ switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) { -+ case UE_CONTROL: -+ case UE_BULK: -+ qtd->error_count++; -+ if (!hc->qh->ping_state) { -+ -+ update_urb_state_xfer_intr(hc, hc_regs, -+ qtd->urb, qtd, -+ DWC_OTG_HC_XFER_XACT_ERR); -+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); -+ if (!hc->ep_is_in && hc->speed == DWC_OTG_EP_SPEED_HIGH) { -+ hc->qh->ping_state = 1; -+ } -+ } -+ -+ /* -+ * Halt the channel so the transfer can be re-started from -+ * the appropriate point or the PING protocol will start. -+ */ -+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR); -+ break; -+ case UE_INTERRUPT: -+ qtd->error_count++; -+ if (hc->do_split && hc->complete_split) { -+ qtd->complete_split = 0; -+ } -+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR); -+ break; -+ case UE_ISOCHRONOUS: -+ { -+ dwc_otg_halt_status_e halt_status; -+ halt_status = -+ update_isoc_urb_state(hcd, hc, hc_regs, qtd, -+ DWC_OTG_HC_XFER_XACT_ERR); -+ -+ halt_channel(hcd, hc, qtd, halt_status); -+ } -+ break; -+ } -+handle_xacterr_done: -+ disable_hc_int(hc_regs, xacterr); -+ -+ return 1; -+} -+ -+/** -+ * Handles a host channel frame overrun interrupt. This handler may be called -+ * in either DMA mode or Slave mode. -+ */ -+static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t * hcd, -+ dwc_hc_t * hc, -+ dwc_otg_hc_regs_t * hc_regs, -+ dwc_otg_qtd_t * qtd) -+{ -+ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " -+ "Frame Overrun--\n", hc->hc_num); -+ -+ switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) { -+ case UE_CONTROL: -+ case UE_BULK: -+ break; -+ case UE_INTERRUPT: -+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN); -+ break; -+ case UE_ISOCHRONOUS: -+ { -+ dwc_otg_halt_status_e halt_status; -+ halt_status = -+ update_isoc_urb_state(hcd, hc, hc_regs, qtd, -+ DWC_OTG_HC_XFER_FRAME_OVERRUN); -+ -+ halt_channel(hcd, hc, qtd, halt_status); -+ } -+ break; -+ } -+ -+ disable_hc_int(hc_regs, frmovrun); -+ -+ return 1; -+} -+ -+/** -+ * Handles a host channel data toggle error interrupt. This handler may be -+ * called in either DMA mode or Slave mode. -+ */ -+static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t * hcd, -+ dwc_hc_t * hc, -+ dwc_otg_hc_regs_t * hc_regs, -+ dwc_otg_qtd_t * qtd) -+{ -+ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " -+ "Data Toggle Error on %s transfer--\n", -+ hc->hc_num, (hc->ep_is_in ? "IN" : "OUT")); -+ -+ /* Data toggles on split transactions cause the hc to halt. -+ * restart transfer */ -+ if(hc->qh->do_split) -+ { -+ qtd->error_count++; -+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); -+ update_urb_state_xfer_intr(hc, hc_regs, -+ qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR); -+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR); -+ } else if (hc->ep_is_in) { -+ /* An unmasked data toggle error on a non-split DMA transaction is -+ * for the sole purpose of resetting error counts. Disable other -+ * interrupts unmasked for the same reason. -+ */ -+ if(hcd->core_if->dma_enable) { -+ disable_hc_int(hc_regs, ack); -+ disable_hc_int(hc_regs, nak); -+ } -+ qtd->error_count = 0; -+ } -+ -+ disable_hc_int(hc_regs, datatglerr); -+ -+ return 1; -+} -+ -+#ifdef DEBUG -+/** -+ * This function is for debug only. It checks that a valid halt status is set -+ * and that HCCHARn.chdis is clear. If there's a problem, corrective action is -+ * taken and a warning is issued. -+ * @return 1 if halt status is ok, 0 otherwise. -+ */ -+static inline int halt_status_ok(dwc_otg_hcd_t * hcd, -+ dwc_hc_t * hc, -+ dwc_otg_hc_regs_t * hc_regs, -+ dwc_otg_qtd_t * qtd) -+{ -+ hcchar_data_t hcchar; -+ hctsiz_data_t hctsiz; -+ hcint_data_t hcint; -+ hcintmsk_data_t hcintmsk; -+ hcsplt_data_t hcsplt; -+ -+ if (hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) { -+ /* -+ * This code is here only as a check. This condition should -+ * never happen. Ignore the halt if it does occur. -+ */ -+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); -+ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz); -+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); -+ hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk); -+ hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt); -+ DWC_WARN -+ ("%s: hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, " -+ "channel %d, hcchar 0x%08x, hctsiz 0x%08x, " -+ "hcint 0x%08x, hcintmsk 0x%08x, " -+ "hcsplt 0x%08x, qtd->complete_split %d\n", __func__, -+ hc->hc_num, hcchar.d32, hctsiz.d32, hcint.d32, -+ hcintmsk.d32, hcsplt.d32, qtd->complete_split); -+ -+ DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n", -+ __func__, hc->hc_num); -+ DWC_WARN("\n"); -+ clear_hc_int(hc_regs, chhltd); -+ return 0; -+ } -+ -+ /* -+ * This code is here only as a check. hcchar.chdis should -+ * never be set when the halt interrupt occurs. Halt the -+ * channel again if it does occur. -+ */ -+ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); -+ if (hcchar.b.chdis) { -+ DWC_WARN("%s: hcchar.chdis set unexpectedly, " -+ "hcchar 0x%08x, trying to halt again\n", -+ __func__, hcchar.d32); -+ clear_hc_int(hc_regs, chhltd); -+ hc->halt_pending = 0; -+ halt_channel(hcd, hc, qtd, hc->halt_status); -+ return 0; -+ } -+ -+ return 1; -+} -+#endif -+ -+/** -+ * Handles a host Channel Halted interrupt in DMA mode. This handler -+ * determines the reason the channel halted and proceeds accordingly. -+ */ -+static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t * hcd, -+ dwc_hc_t * hc, -+ dwc_otg_hc_regs_t * hc_regs, -+ dwc_otg_qtd_t * qtd) -+{ -+ int out_nak_enh = 0; -+ hcint_data_t hcint; -+ hcintmsk_data_t hcintmsk; -+ /* For core with OUT NAK enhancement, the flow for high- -+ * speed CONTROL/BULK OUT is handled a little differently. -+ */ -+ if (hcd->core_if->snpsid >= OTG_CORE_REV_2_71a) { -+ if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in && -+ (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL || -+ hc->ep_type == DWC_OTG_EP_TYPE_BULK)) { -+ out_nak_enh = 1; -+ } -+ } -+ -+ if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE || -+ (hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR -+ && !hcd->core_if->dma_desc_enable)) { -+ /* -+ * Just release the channel. A dequeue can happen on a -+ * transfer timeout. In the case of an AHB Error, the channel -+ * was forced to halt because there's no way to gracefully -+ * recover. -+ */ -+ if (hcd->core_if->dma_desc_enable) -+ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, -+ hc->halt_status); -+ else -+ release_channel(hcd, hc, qtd, hc->halt_status); -+ return; -+ } -+ -+ /* Read the HCINTn register to determine the cause for the halt. */ -+ -+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); -+ hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk); -+ -+ if (hcint.b.xfercomp) { -+ /** @todo This is here because of a possible hardware bug. Spec -+ * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT -+ * interrupt w/ACK bit set should occur, but I only see the -+ * XFERCOMP bit, even with it masked out. This is a workaround -+ * for that behavior. Should fix this when hardware is fixed. -+ */ -+ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) { -+ handle_hc_ack_intr(hcd, hc, hc_regs, qtd); -+ } -+ handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd); -+ } else if (hcint.b.stall) { -+ handle_hc_stall_intr(hcd, hc, hc_regs, qtd); -+ } else if (hcint.b.xacterr && !hcd->core_if->dma_desc_enable) { -+ if (out_nak_enh) { -+ if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) { -+ DWC_DEBUGPL(DBG_HCD, "XactErr with NYET/NAK/ACK\n"); -+ qtd->error_count = 0; -+ } else { -+ DWC_DEBUGPL(DBG_HCD, "XactErr without NYET/NAK/ACK\n"); -+ } -+ } -+ -+ /* -+ * Must handle xacterr before nak or ack. Could get a xacterr -+ * at the same time as either of these on a BULK/CONTROL OUT -+ * that started with a PING. The xacterr takes precedence. -+ */ -+ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd); -+ } else if (hcint.b.xcs_xact && hcd->core_if->dma_desc_enable) { -+ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd); -+ } else if (hcint.b.ahberr && hcd->core_if->dma_desc_enable) { -+ handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd); -+ } else if (hcint.b.bblerr) { -+ handle_hc_babble_intr(hcd, hc, hc_regs, qtd); -+ } else if (hcint.b.frmovrun) { -+ handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd); -+ } else if (hcint.b.datatglerr) { -+ handle_hc_datatglerr_intr(hcd, hc, hc_regs, qtd); -+ } else if (!out_nak_enh) { -+ if (hcint.b.nyet) { -+ /* -+ * Must handle nyet before nak or ack. Could get a nyet at the -+ * same time as either of those on a BULK/CONTROL OUT that -+ * started with a PING. The nyet takes precedence. -+ */ -+ handle_hc_nyet_intr(hcd, hc, hc_regs, qtd); -+ } else if (hcint.b.nak && !hcintmsk.b.nak) { -+ /* -+ * If nak is not masked, it's because a non-split IN transfer -+ * is in an error state. In that case, the nak is handled by -+ * the nak interrupt handler, not here. Handle nak here for -+ * BULK/CONTROL OUT transfers, which halt on a NAK to allow -+ * rewinding the buffer pointer. -+ */ -+ handle_hc_nak_intr(hcd, hc, hc_regs, qtd); -+ } else if (hcint.b.ack && !hcintmsk.b.ack) { -+ /* -+ * If ack is not masked, it's because a non-split IN transfer -+ * is in an error state. In that case, the ack is handled by -+ * the ack interrupt handler, not here. Handle ack here for -+ * split transfers. Start splits halt on ACK. -+ */ -+ handle_hc_ack_intr(hcd, hc, hc_regs, qtd); -+ } else { -+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || -+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { -+ /* -+ * A periodic transfer halted with no other channel -+ * interrupts set. Assume it was halted by the core -+ * because it could not be completed in its scheduled -+ * (micro)frame. -+ */ -+#ifdef DEBUG -+ DWC_PRINTF -+ ("%s: Halt channel %d (assume incomplete periodic transfer)\n", -+ __func__, hc->hc_num); -+#endif -+ halt_channel(hcd, hc, qtd, -+ DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE); -+ } else { -+ DWC_ERROR -+ ("%s: Channel %d, DMA Mode -- ChHltd set, but reason " -+ "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n", -+ __func__, hc->hc_num, hcint.d32, -+ DWC_READ_REG32(&hcd-> -+ core_if->core_global_regs-> -+ gintsts)); -+ /* Failthrough: use 3-strikes rule */ -+ qtd->error_count++; -+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); -+ update_urb_state_xfer_intr(hc, hc_regs, -+ qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR); -+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR); -+ } -+ -+ } -+ } else { -+ DWC_PRINTF("NYET/NAK/ACK/other in non-error case, 0x%08x\n", -+ hcint.d32); -+ /* Failthrough: use 3-strikes rule */ -+ qtd->error_count++; -+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); -+ update_urb_state_xfer_intr(hc, hc_regs, -+ qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR); -+ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR); -+ } -+} -+ -+/** -+ * Handles a host channel Channel Halted interrupt. -+ * -+ * In slave mode, this handler is called only when the driver specifically -+ * requests a halt. This occurs during handling other host channel interrupts -+ * (e.g. nak, xacterr, stall, nyet, etc.). -+ * -+ * In DMA mode, this is the interrupt that occurs when the core has finished -+ * processing a transfer on a channel. Other host channel interrupts (except -+ * ahberr) are disabled in DMA mode. -+ */ -+static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t * hcd, -+ dwc_hc_t * hc, -+ dwc_otg_hc_regs_t * hc_regs, -+ dwc_otg_qtd_t * qtd) -+{ -+ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " -+ "Channel Halted--\n", hc->hc_num); -+ -+ if (hcd->core_if->dma_enable) { -+ handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd); -+ } else { -+#ifdef DEBUG -+ if (!halt_status_ok(hcd, hc, hc_regs, qtd)) { -+ return 1; -+ } -+#endif -+ release_channel(hcd, hc, qtd, hc->halt_status); -+ } -+ -+ return 1; -+} -+ -+ -+/** -+ * dwc_otg_fiq_unmangle_isoc() - Update the iso_frame_desc structure on -+ * FIQ transfer completion -+ * @hcd: Pointer to dwc_otg_hcd struct -+ * @num: Host channel number -+ * -+ * 1. Un-mangle the status as recorded in each iso_frame_desc status -+ * 2. Copy it from the dwc_otg_urb into the real URB -+ */ -+void dwc_otg_fiq_unmangle_isoc(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_qtd_t *qtd, uint32_t num) -+{ -+ struct dwc_otg_hcd_urb *dwc_urb = qtd->urb; -+ int nr_frames = dwc_urb->packet_count; -+ int i; -+ hcint_data_t frame_hcint; -+ -+ for (i = 0; i < nr_frames; i++) { -+ frame_hcint.d32 = dwc_urb->iso_descs[i].status; -+ if (frame_hcint.b.xfercomp) { -+ dwc_urb->iso_descs[i].status = 0; -+ dwc_urb->actual_length += dwc_urb->iso_descs[i].actual_length; -+ } else if (frame_hcint.b.frmovrun) { -+ if (qh->ep_is_in) -+ dwc_urb->iso_descs[i].status = -DWC_E_NO_STREAM_RES; -+ else -+ dwc_urb->iso_descs[i].status = -DWC_E_COMMUNICATION; -+ dwc_urb->error_count++; -+ dwc_urb->iso_descs[i].actual_length = 0; -+ } else if (frame_hcint.b.xacterr) { -+ dwc_urb->iso_descs[i].status = -DWC_E_PROTOCOL; -+ dwc_urb->error_count++; -+ dwc_urb->iso_descs[i].actual_length = 0; -+ } else if (frame_hcint.b.bblerr) { -+ dwc_urb->iso_descs[i].status = -DWC_E_OVERFLOW; -+ dwc_urb->error_count++; -+ dwc_urb->iso_descs[i].actual_length = 0; -+ } else { -+ /* Something went wrong */ -+ dwc_urb->iso_descs[i].status = -1; -+ dwc_urb->iso_descs[i].actual_length = 0; -+ dwc_urb->error_count++; -+ } -+ } -+ qh->sched_frame = dwc_frame_num_inc(qh->sched_frame, qh->interval * (nr_frames - 1)); -+ -+ //printk_ratelimited(KERN_INFO "%s: HS isochronous of %d/%d frames with %d errors complete\n", -+ // __FUNCTION__, i, dwc_urb->packet_count, dwc_urb->error_count); -+} -+ -+/** -+ * dwc_otg_fiq_unsetup_per_dma() - Remove data from bounce buffers for split transactions -+ * @hcd: Pointer to dwc_otg_hcd struct -+ * @num: Host channel number -+ * -+ * Copies data from the FIQ bounce buffers into the URB's transfer buffer. Does not modify URB state. -+ * Returns total length of data or -1 if the buffers were not used. -+ * -+ */ -+int dwc_otg_fiq_unsetup_per_dma(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_qtd_t *qtd, uint32_t num) -+{ -+ dwc_hc_t *hc = qh->channel; -+ struct fiq_dma_blob *blob = hcd->fiq_dmab; -+ struct fiq_channel_state *st = &hcd->fiq_state->channel[num]; -+ uint8_t *ptr = NULL; -+ int index = 0, len = 0; -+ int i = 0; -+ if (hc->ep_is_in) { -+ /* Copy data out of the DMA bounce buffers to the URB's buffer. -+ * The align_buf is ignored as this is ignored on FSM enqueue. */ -+ ptr = qtd->urb->buf; -+ if (qh->ep_type == UE_ISOCHRONOUS) { -+ /* Isoc IN transactions - grab the offset of the iso_frame_desc into the URB transfer buffer */ -+ index = qtd->isoc_frame_index; -+ ptr += qtd->urb->iso_descs[index].offset; -+ } else { -+ /* Need to increment by actual_length for interrupt IN */ -+ ptr += qtd->urb->actual_length; -+ } -+ -+ for (i = 0; i < st->dma_info.index; i++) { -+ len += st->dma_info.slot_len[i]; -+ dwc_memcpy(ptr, &blob->channel[num].index[i].buf[0], st->dma_info.slot_len[i]); -+ ptr += st->dma_info.slot_len[i]; -+ } -+ return len; -+ } else { -+ /* OUT endpoints - nothing to do. */ -+ return -1; -+ } -+ -+} -+/** -+ * dwc_otg_hcd_handle_hc_fsm() - handle an unmasked channel interrupt -+ * from a channel handled in the FIQ -+ * @hcd: Pointer to dwc_otg_hcd struct -+ * @num: Host channel number -+ * -+ * If a host channel interrupt was received by the IRQ and this was a channel -+ * used by the FIQ, the execution flow for transfer completion is substantially -+ * different from the normal (messy) path. This function and its friends handles -+ * channel cleanup and transaction completion from a FIQ transaction. -+ */ -+void dwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd_t *hcd, uint32_t num) -+{ -+ struct fiq_channel_state *st = &hcd->fiq_state->channel[num]; -+ dwc_hc_t *hc = hcd->hc_ptr_array[num]; -+ dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list); -+ dwc_otg_qh_t *qh = hc->qh; -+ dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[num]; -+ hcint_data_t hcint = hcd->fiq_state->channel[num].hcint_copy; -+ int hostchannels = 0; -+ fiq_print(FIQDBG_INT, hcd->fiq_state, "OUT %01d %01d ", num , st->fsm); -+ -+ hostchannels = hcd->available_host_channels; -+ switch (st->fsm) { -+ case FIQ_TEST: -+ break; -+ -+ case FIQ_DEQUEUE_ISSUED: -+ /* hc_halt was called. QTD no longer exists. */ -+ /* TODO: for a nonperiodic split transaction, need to issue a -+ * CLEAR_TT_BUFFER hub command if we were in the start-split phase. -+ */ -+ release_channel(hcd, hc, NULL, hc->halt_status); -+ break; -+ -+ case FIQ_NP_SPLIT_DONE: -+ /* Nonperiodic transaction complete. */ -+ if (!hc->ep_is_in) { -+ qtd->ssplit_out_xfer_count = hc->xfer_len; -+ } -+ if (hcint.b.xfercomp) { -+ handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd); -+ } else if (hcint.b.nak) { -+ handle_hc_nak_intr(hcd, hc, hc_regs, qtd); -+ } -+ break; -+ -+ case FIQ_NP_SPLIT_HS_ABORTED: -+ /* A HS abort is a 3-strikes on the HS bus at any point in the transaction. -+ * Normally a CLEAR_TT_BUFFER hub command would be required: we can't do that -+ * because there's no guarantee which order a non-periodic split happened in. -+ * We could end up clearing a perfectly good transaction out of the buffer. -+ */ -+ if (hcint.b.xacterr) { -+ qtd->error_count += st->nr_errors; -+ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd); -+ } else if (hcint.b.ahberr) { -+ handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd); -+ } else { -+ local_fiq_disable(); -+ BUG(); -+ } -+ break; -+ -+ case FIQ_NP_SPLIT_LS_ABORTED: -+ /* A few cases can cause this - either an unknown state on a SSPLIT or -+ * STALL/data toggle error response on a CSPLIT */ -+ if (hcint.b.stall) { -+ handle_hc_stall_intr(hcd, hc, hc_regs, qtd); -+ } else if (hcint.b.datatglerr) { -+ handle_hc_datatglerr_intr(hcd, hc, hc_regs, qtd); -+ } else if (hcint.b.bblerr) { -+ handle_hc_babble_intr(hcd, hc, hc_regs, qtd); -+ } else if (hcint.b.ahberr) { -+ handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd); -+ } else { -+ local_fiq_disable(); -+ BUG(); -+ } -+ break; -+ -+ case FIQ_PER_SPLIT_DONE: -+ /* Isoc IN or Interrupt IN/OUT */ -+ -+ /* Flow control here is different from the normal execution by the driver. -+ * We need to completely ignore most of the driver's method of handling -+ * split transactions and do it ourselves. -+ */ -+ if (hc->ep_type == UE_INTERRUPT) { -+ if (hcint.b.nak) { -+ handle_hc_nak_intr(hcd, hc, hc_regs, qtd); -+ } else if (hc->ep_is_in) { -+ int len; -+ len = dwc_otg_fiq_unsetup_per_dma(hcd, hc->qh, qtd, num); -+ //printk(KERN_NOTICE "FIQ Transaction: hc=%d len=%d urb_len = %d\n", num, len, qtd->urb->length); -+ qtd->urb->actual_length += len; -+ if (qtd->urb->actual_length >= qtd->urb->length) { -+ qtd->urb->status = 0; -+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status); -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); -+ } else { -+ /* Interrupt transfer not complete yet - is it a short read? */ -+ if (len < hc->max_packet) { -+ /* Interrupt transaction complete */ -+ qtd->urb->status = 0; -+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status); -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); -+ } else { -+ /* Further transactions required */ -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE); -+ } -+ } -+ } else { -+ /* Interrupt OUT complete. */ -+ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); -+ qtd->urb->actual_length += hc->xfer_len; -+ if (qtd->urb->actual_length >= qtd->urb->length) { -+ qtd->urb->status = 0; -+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status); -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); -+ } else { -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE); -+ } -+ } -+ } else { -+ /* ISOC IN complete. */ -+ struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; -+ int len = 0; -+ /* Record errors, update qtd. */ -+ if (st->nr_errors) { -+ frame_desc->actual_length = 0; -+ frame_desc->status = -DWC_E_PROTOCOL; -+ } else { -+ frame_desc->status = 0; -+ /* Unswizzle dma */ -+ len = dwc_otg_fiq_unsetup_per_dma(hcd, qh, qtd, num); -+ frame_desc->actual_length = len; -+ } -+ qtd->isoc_frame_index++; -+ if (qtd->isoc_frame_index == qtd->urb->packet_count) { -+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); -+ } else { -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE); -+ } -+ } -+ break; -+ -+ case FIQ_PER_ISO_OUT_DONE: { -+ struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; -+ /* Record errors, update qtd. */ -+ if (st->nr_errors) { -+ frame_desc->actual_length = 0; -+ frame_desc->status = -DWC_E_PROTOCOL; -+ } else { -+ frame_desc->status = 0; -+ frame_desc->actual_length = frame_desc->length; -+ } -+ qtd->isoc_frame_index++; -+ qtd->isoc_split_offset = 0; -+ if (qtd->isoc_frame_index == qtd->urb->packet_count) { -+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); -+ } else { -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE); -+ } -+ } -+ break; -+ -+ case FIQ_PER_SPLIT_NYET_ABORTED: -+ /* Doh. lost the data. */ -+ printk_ratelimited(KERN_INFO "Transfer to device %d endpoint 0x%x frame %d failed " -+ "- FIQ reported NYET. Data may have been lost.\n", -+ hc->dev_addr, hc->ep_num, dwc_otg_hcd_get_frame_number(hcd) >> 3); -+ if (hc->ep_type == UE_ISOCHRONOUS) { -+ struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; -+ /* Record errors, update qtd. */ -+ frame_desc->actual_length = 0; -+ frame_desc->status = -DWC_E_PROTOCOL; -+ qtd->isoc_frame_index++; -+ qtd->isoc_split_offset = 0; -+ if (qtd->isoc_frame_index == qtd->urb->packet_count) { -+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); -+ } else { -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE); -+ } -+ } else { -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS); -+ } -+ break; -+ -+ case FIQ_HS_ISOC_DONE: -+ /* The FIQ has performed a whole pile of isochronous transactions. -+ * The status is recorded as the interrupt state should the transaction -+ * fail. -+ */ -+ dwc_otg_fiq_unmangle_isoc(hcd, qh, qtd, num); -+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); -+ break; -+ -+ case FIQ_PER_SPLIT_LS_ABORTED: -+ if (hcint.b.xacterr) { -+ /* Hub has responded with an ERR packet. Device -+ * has been unplugged or the port has been disabled. -+ * TODO: need to issue a reset to the hub port. */ -+ qtd->error_count += 3; -+ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd); -+ } else if (hcint.b.stall) { -+ handle_hc_stall_intr(hcd, hc, hc_regs, qtd); -+ } else if (hcint.b.bblerr) { -+ handle_hc_babble_intr(hcd, hc, hc_regs, qtd); -+ } else { -+ printk_ratelimited(KERN_INFO "Transfer to device %d endpoint 0x%x failed " -+ "- FIQ reported FSM=%d. Data may have been lost.\n", -+ st->fsm, hc->dev_addr, hc->ep_num); -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS); -+ } -+ break; -+ -+ case FIQ_PER_SPLIT_HS_ABORTED: -+ /* Either the SSPLIT phase suffered transaction errors or something -+ * unexpected happened. -+ */ -+ qtd->error_count += 3; -+ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd); -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS); -+ break; -+ -+ case FIQ_PER_SPLIT_TIMEOUT: -+ /* Couldn't complete in the nominated frame */ -+ printk(KERN_INFO "Transfer to device %d endpoint 0x%x frame %d failed " -+ "- FIQ timed out. Data may have been lost.\n", -+ hc->dev_addr, hc->ep_num, dwc_otg_hcd_get_frame_number(hcd) >> 3); -+ if (hc->ep_type == UE_ISOCHRONOUS) { -+ struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; -+ /* Record errors, update qtd. */ -+ frame_desc->actual_length = 0; -+ if (hc->ep_is_in) { -+ frame_desc->status = -DWC_E_NO_STREAM_RES; -+ } else { -+ frame_desc->status = -DWC_E_COMMUNICATION; -+ } -+ qtd->isoc_frame_index++; -+ if (qtd->isoc_frame_index == qtd->urb->packet_count) { -+ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); -+ } else { -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE); -+ } -+ } else { -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS); -+ } -+ break; -+ -+ default: -+ DWC_WARN("Unexpected state received on hc=%d fsm=%d on transfer to device %d ep 0x%x", -+ hc->hc_num, st->fsm, hc->dev_addr, hc->ep_num); -+ qtd->error_count++; -+ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS); -+ } -+ return; -+} -+ -+/** Handles interrupt for a specific Host Channel */ -+int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, uint32_t num) -+{ -+ int retval = 0; -+ hcint_data_t hcint; -+ hcintmsk_data_t hcintmsk; -+ dwc_hc_t *hc; -+ dwc_otg_hc_regs_t *hc_regs; -+ dwc_otg_qtd_t *qtd; -+ -+ DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", num); -+ -+ hc = dwc_otg_hcd->hc_ptr_array[num]; -+ hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[num]; -+ if(hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) { -+ /* We are responding to a channel disable. Driver -+ * state is cleared - our qtd has gone away. -+ */ -+ release_channel(dwc_otg_hcd, hc, NULL, hc->halt_status); -+ return 1; -+ } -+ qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list); -+ -+ /* -+ * FSM mode: Check to see if this is a HC interrupt from a channel handled by the FIQ. -+ * Execution path is fundamentally different for the channels after a FIQ has completed -+ * a split transaction. -+ */ -+ if (fiq_fsm_enable) { -+ switch (dwc_otg_hcd->fiq_state->channel[num].fsm) { -+ case FIQ_PASSTHROUGH: -+ break; -+ case FIQ_PASSTHROUGH_ERRORSTATE: -+ /* Hook into the error count */ -+ fiq_print(FIQDBG_ERR, dwc_otg_hcd->fiq_state, "HCDERR%02d", num); -+ if (!dwc_otg_hcd->fiq_state->channel[num].nr_errors) { -+ qtd->error_count = 0; -+ fiq_print(FIQDBG_ERR, dwc_otg_hcd->fiq_state, "RESET "); -+ } -+ break; -+ default: -+ dwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd, num); -+ return 1; -+ } -+ } -+ -+ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); -+ hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk); -+ hcint.d32 = hcint.d32 & hcintmsk.d32; -+ if (!dwc_otg_hcd->core_if->dma_enable) { -+ if (hcint.b.chhltd && hcint.d32 != 0x2) { -+ hcint.b.chhltd = 0; -+ } -+ } -+ -+ if (hcint.b.xfercomp) { -+ retval |= -+ handle_hc_xfercomp_intr(dwc_otg_hcd, hc, hc_regs, qtd); -+ /* -+ * If NYET occurred at same time as Xfer Complete, the NYET is -+ * handled by the Xfer Complete interrupt handler. Don't want -+ * to call the NYET interrupt handler in this case. -+ */ -+ hcint.b.nyet = 0; -+ } -+ if (hcint.b.chhltd) { -+ retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd); -+ } -+ if (hcint.b.ahberr) { -+ retval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd); -+ } -+ if (hcint.b.stall) { -+ retval |= handle_hc_stall_intr(dwc_otg_hcd, hc, hc_regs, qtd); -+ } -+ if (hcint.b.nak) { -+ retval |= handle_hc_nak_intr(dwc_otg_hcd, hc, hc_regs, qtd); -+ } -+ if (hcint.b.ack) { -+ if(!hcint.b.chhltd) -+ retval |= handle_hc_ack_intr(dwc_otg_hcd, hc, hc_regs, qtd); -+ } -+ if (hcint.b.nyet) { -+ retval |= handle_hc_nyet_intr(dwc_otg_hcd, hc, hc_regs, qtd); -+ } -+ if (hcint.b.xacterr) { -+ retval |= handle_hc_xacterr_intr(dwc_otg_hcd, hc, hc_regs, qtd); -+ } -+ if (hcint.b.bblerr) { -+ retval |= handle_hc_babble_intr(dwc_otg_hcd, hc, hc_regs, qtd); -+ } -+ if (hcint.b.frmovrun) { -+ retval |= -+ handle_hc_frmovrun_intr(dwc_otg_hcd, hc, hc_regs, qtd); -+ } -+ if (hcint.b.datatglerr) { -+ retval |= -+ handle_hc_datatglerr_intr(dwc_otg_hcd, hc, hc_regs, qtd); -+ } -+ -+ return retval; -+} -+#endif /* DWC_DEVICE_ONLY */ -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c 2015-11-29 09:42:39.919098694 +0100 -@@ -0,0 +1,999 @@ -+ -+/* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_linux.c $ -+ * $Revision: #20 $ -+ * $Date: 2011/10/26 $ -+ * $Change: 1872981 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+#ifndef DWC_DEVICE_ONLY -+ -+/** -+ * @file -+ * -+ * This file contains the implementation of the HCD. In Linux, the HCD -+ * implements the hc_driver API. -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) -+#include <../drivers/usb/core/hcd.h> -+#else -+#include -+#endif -+#include -+ -+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)) -+#define USB_URB_EP_LINKING 1 -+#else -+#define USB_URB_EP_LINKING 0 -+#endif -+ -+#include "dwc_otg_hcd_if.h" -+#include "dwc_otg_dbg.h" -+#include "dwc_otg_driver.h" -+#include "dwc_otg_hcd.h" -+ -+extern unsigned char _dwc_otg_fiq_stub, _dwc_otg_fiq_stub_end; -+ -+/** -+ * Gets the endpoint number from a _bEndpointAddress argument. The endpoint is -+ * qualified with its direction (possible 32 endpoints per device). -+ */ -+#define dwc_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \ -+ ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4) -+ -+static const char dwc_otg_hcd_name[] = "dwc_otg_hcd"; -+ -+extern bool fiq_enable; -+ -+/** @name Linux HC Driver API Functions */ -+/** @{ */ -+/* manage i/o requests, device state */ -+static int dwc_otg_urb_enqueue(struct usb_hcd *hcd, -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) -+ struct usb_host_endpoint *ep, -+#endif -+ struct urb *urb, gfp_t mem_flags); -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) -+static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb); -+#endif -+#else /* kernels at or post 2.6.30 */ -+static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, -+ struct urb *urb, int status); -+#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) */ -+ -+static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30) -+static void endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep); -+#endif -+static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd); -+extern int hcd_start(struct usb_hcd *hcd); -+extern void hcd_stop(struct usb_hcd *hcd); -+static int get_frame_number(struct usb_hcd *hcd); -+extern int hub_status_data(struct usb_hcd *hcd, char *buf); -+extern int hub_control(struct usb_hcd *hcd, -+ u16 typeReq, -+ u16 wValue, u16 wIndex, char *buf, u16 wLength); -+ -+struct wrapper_priv_data { -+ dwc_otg_hcd_t *dwc_otg_hcd; -+}; -+ -+/** @} */ -+ -+static struct hc_driver dwc_otg_hc_driver = { -+ -+ .description = dwc_otg_hcd_name, -+ .product_desc = "DWC OTG Controller", -+ .hcd_priv_size = sizeof(struct wrapper_priv_data), -+ -+ .irq = dwc_otg_hcd_irq, -+ -+ .flags = HCD_MEMORY | HCD_USB2, -+ -+ //.reset = -+ .start = hcd_start, -+ //.suspend = -+ //.resume = -+ .stop = hcd_stop, -+ -+ .urb_enqueue = dwc_otg_urb_enqueue, -+ .urb_dequeue = dwc_otg_urb_dequeue, -+ .endpoint_disable = endpoint_disable, -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30) -+ .endpoint_reset = endpoint_reset, -+#endif -+ .get_frame_number = get_frame_number, -+ -+ .hub_status_data = hub_status_data, -+ .hub_control = hub_control, -+ //.bus_suspend = -+ //.bus_resume = -+}; -+ -+/** Gets the dwc_otg_hcd from a struct usb_hcd */ -+static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd) -+{ -+ struct wrapper_priv_data *p; -+ p = (struct wrapper_priv_data *)(hcd->hcd_priv); -+ return p->dwc_otg_hcd; -+} -+ -+/** Gets the struct usb_hcd that contains a dwc_otg_hcd_t. */ -+static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t * dwc_otg_hcd) -+{ -+ return dwc_otg_hcd_get_priv_data(dwc_otg_hcd); -+} -+ -+/** Gets the usb_host_endpoint associated with an URB. */ -+inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *urb) -+{ -+ struct usb_device *dev = urb->dev; -+ int ep_num = usb_pipeendpoint(urb->pipe); -+ -+ if (usb_pipein(urb->pipe)) -+ return dev->ep_in[ep_num]; -+ else -+ return dev->ep_out[ep_num]; -+} -+ -+static int _disconnect(dwc_otg_hcd_t * hcd) -+{ -+ struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd); -+ -+ usb_hcd->self.is_b_host = 0; -+ return 0; -+} -+ -+static int _start(dwc_otg_hcd_t * hcd) -+{ -+ struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd); -+ -+ usb_hcd->self.is_b_host = dwc_otg_hcd_is_b_host(hcd); -+ hcd_start(usb_hcd); -+ -+ return 0; -+} -+ -+static int _hub_info(dwc_otg_hcd_t * hcd, void *urb_handle, uint32_t * hub_addr, -+ uint32_t * port_addr) -+{ -+ struct urb *urb = (struct urb *)urb_handle; -+ struct usb_bus *bus; -+#if 1 //GRAYG - temporary -+ if (NULL == urb_handle) -+ DWC_ERROR("**** %s - NULL URB handle\n", __func__);//GRAYG -+ if (NULL == urb->dev) -+ DWC_ERROR("**** %s - URB has no device\n", __func__);//GRAYG -+ if (NULL == port_addr) -+ DWC_ERROR("**** %s - NULL port_address\n", __func__);//GRAYG -+#endif -+ if (urb->dev->tt) { -+ if (NULL == urb->dev->tt->hub) { -+ DWC_ERROR("**** %s - (URB's transactor has no TT - giving no hub)\n", -+ __func__); //GRAYG -+ //*hub_addr = (u8)usb_pipedevice(urb->pipe); //GRAYG -+ *hub_addr = 0; //GRAYG -+ // we probably shouldn't have a transaction translator if -+ // there's no associated hub? -+ } else { -+ bus = hcd_to_bus(dwc_otg_hcd_to_hcd(hcd)); -+ if (urb->dev->tt->hub == bus->root_hub) -+ *hub_addr = 0; -+ else -+ *hub_addr = urb->dev->tt->hub->devnum; -+ } -+ *port_addr = urb->dev->tt->multi ? urb->dev->ttport : 1; -+ } else { -+ *hub_addr = 0; -+ *port_addr = urb->dev->ttport; -+ } -+ return 0; -+} -+ -+static int _speed(dwc_otg_hcd_t * hcd, void *urb_handle) -+{ -+ struct urb *urb = (struct urb *)urb_handle; -+ return urb->dev->speed; -+} -+ -+static int _get_b_hnp_enable(dwc_otg_hcd_t * hcd) -+{ -+ struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd); -+ return usb_hcd->self.b_hnp_enable; -+} -+ -+static void allocate_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw, -+ struct urb *urb) -+{ -+ hcd_to_bus(hcd)->bandwidth_allocated += bw / urb->interval; -+ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { -+ hcd_to_bus(hcd)->bandwidth_isoc_reqs++; -+ } else { -+ hcd_to_bus(hcd)->bandwidth_int_reqs++; -+ } -+} -+ -+static void free_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw, -+ struct urb *urb) -+{ -+ hcd_to_bus(hcd)->bandwidth_allocated -= bw / urb->interval; -+ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { -+ hcd_to_bus(hcd)->bandwidth_isoc_reqs--; -+ } else { -+ hcd_to_bus(hcd)->bandwidth_int_reqs--; -+ } -+} -+ -+/** -+ * Sets the final status of an URB and returns it to the device driver. Any -+ * required cleanup of the URB is performed. The HCD lock should be held on -+ * entry. -+ */ -+static int _complete(dwc_otg_hcd_t * hcd, void *urb_handle, -+ dwc_otg_hcd_urb_t * dwc_otg_urb, int32_t status) -+{ -+ struct urb *urb = (struct urb *)urb_handle; -+ urb_tq_entry_t *new_entry; -+ int rc = 0; -+ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { -+ DWC_PRINTF("%s: urb %p, device %d, ep %d %s, status=%d\n", -+ __func__, urb, usb_pipedevice(urb->pipe), -+ usb_pipeendpoint(urb->pipe), -+ usb_pipein(urb->pipe) ? "IN" : "OUT", status); -+ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { -+ int i; -+ for (i = 0; i < urb->number_of_packets; i++) { -+ DWC_PRINTF(" ISO Desc %d status: %d\n", -+ i, urb->iso_frame_desc[i].status); -+ } -+ } -+ } -+ new_entry = DWC_ALLOC_ATOMIC(sizeof(urb_tq_entry_t)); -+ urb->actual_length = dwc_otg_hcd_urb_get_actual_length(dwc_otg_urb); -+ /* Convert status value. */ -+ switch (status) { -+ case -DWC_E_PROTOCOL: -+ status = -EPROTO; -+ break; -+ case -DWC_E_IN_PROGRESS: -+ status = -EINPROGRESS; -+ break; -+ case -DWC_E_PIPE: -+ status = -EPIPE; -+ break; -+ case -DWC_E_IO: -+ status = -EIO; -+ break; -+ case -DWC_E_TIMEOUT: -+ status = -ETIMEDOUT; -+ break; -+ case -DWC_E_OVERFLOW: -+ status = -EOVERFLOW; -+ break; -+ case -DWC_E_SHUTDOWN: -+ status = -ESHUTDOWN; -+ break; -+ default: -+ if (status) { -+ DWC_PRINTF("Uknown urb status %d\n", status); -+ -+ } -+ } -+ -+ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { -+ int i; -+ -+ urb->error_count = dwc_otg_hcd_urb_get_error_count(dwc_otg_urb); -+ for (i = 0; i < urb->number_of_packets; ++i) { -+ urb->iso_frame_desc[i].actual_length = -+ dwc_otg_hcd_urb_get_iso_desc_actual_length -+ (dwc_otg_urb, i); -+ urb->iso_frame_desc[i].status = -+ dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_urb, i); -+ } -+ } -+ -+ urb->status = status; -+ urb->hcpriv = NULL; -+ if (!status) { -+ if ((urb->transfer_flags & URB_SHORT_NOT_OK) && -+ (urb->actual_length < urb->transfer_buffer_length)) { -+ urb->status = -EREMOTEIO; -+ } -+ } -+ -+ if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) || -+ (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) { -+ struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb); -+ if (ep) { -+ free_bus_bandwidth(dwc_otg_hcd_to_hcd(hcd), -+ dwc_otg_hcd_get_ep_bandwidth(hcd, -+ ep->hcpriv), -+ urb); -+ } -+ } -+ DWC_FREE(dwc_otg_urb); -+ if (!new_entry) { -+ DWC_ERROR("dwc_otg_hcd: complete: cannot allocate URB TQ entry\n"); -+ urb->status = -EPROTO; -+ /* don't schedule the tasklet - -+ * directly return the packet here with error. */ -+#if USB_URB_EP_LINKING -+ usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(hcd), urb); -+#endif -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) -+ usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb); -+#else -+ usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb, urb->status); -+#endif -+ } else { -+ new_entry->urb = urb; -+#if USB_URB_EP_LINKING -+ rc = usb_hcd_check_unlink_urb(dwc_otg_hcd_to_hcd(hcd), urb, urb->status); -+ if(0 == rc) { -+ usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(hcd), urb); -+ } -+#endif -+ if(0 == rc) { -+ DWC_TAILQ_INSERT_TAIL(&hcd->completed_urb_list, new_entry, -+ urb_tq_entries); -+ DWC_TASK_HI_SCHEDULE(hcd->completion_tasklet); -+ } -+ } -+ return 0; -+} -+ -+static struct dwc_otg_hcd_function_ops hcd_fops = { -+ .start = _start, -+ .disconnect = _disconnect, -+ .hub_info = _hub_info, -+ .speed = _speed, -+ .complete = _complete, -+ .get_b_hnp_enable = _get_b_hnp_enable, -+}; -+ -+static struct fiq_handler fh = { -+ .name = "usb_fiq", -+}; -+ -+static void hcd_init_fiq(void *cookie) -+{ -+ dwc_otg_device_t *otg_dev = cookie; -+ dwc_otg_hcd_t *dwc_otg_hcd = otg_dev->hcd; -+ struct pt_regs regs; -+ -+ if (claim_fiq(&fh)) { -+ DWC_ERROR("Can't claim FIQ"); -+ BUG(); -+ } -+ DWC_WARN("FIQ on core %d at 0x%08x", -+ smp_processor_id(), -+ (fiq_fsm_enable ? (int)&dwc_otg_fiq_fsm : (int)&dwc_otg_fiq_nop)); -+ DWC_WARN("FIQ ASM at 0x%08x length %d", (int)&_dwc_otg_fiq_stub, (int)(&_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub)); -+ set_fiq_handler((void *) &_dwc_otg_fiq_stub, &_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub); -+ memset(®s,0,sizeof(regs)); -+ -+ regs.ARM_r8 = (long) dwc_otg_hcd->fiq_state; -+ if (fiq_fsm_enable) { -+ regs.ARM_r9 = dwc_otg_hcd->core_if->core_params->host_channels; -+ //regs.ARM_r10 = dwc_otg_hcd->dma; -+ regs.ARM_fp = (long) dwc_otg_fiq_fsm; -+ } else { -+ regs.ARM_fp = (long) dwc_otg_fiq_nop; -+ } -+ -+ regs.ARM_sp = (long) dwc_otg_hcd->fiq_stack + (sizeof(struct fiq_stack) - 4); -+ -+// __show_regs(®s); -+ set_fiq_regs(®s); -+ -+ //Set the mphi periph to the required registers -+ dwc_otg_hcd->fiq_state->mphi_regs.base = otg_dev->os_dep.mphi_base; -+ dwc_otg_hcd->fiq_state->mphi_regs.ctrl = otg_dev->os_dep.mphi_base + 0x4c; -+ dwc_otg_hcd->fiq_state->mphi_regs.outdda = otg_dev->os_dep.mphi_base + 0x28; -+ dwc_otg_hcd->fiq_state->mphi_regs.outddb = otg_dev->os_dep.mphi_base + 0x2c; -+ dwc_otg_hcd->fiq_state->mphi_regs.intstat = otg_dev->os_dep.mphi_base + 0x50; -+ dwc_otg_hcd->fiq_state->dwc_regs_base = otg_dev->os_dep.base; -+ DWC_WARN("MPHI regs_base at 0x%08x", (int)dwc_otg_hcd->fiq_state->mphi_regs.base); -+ //Enable mphi peripheral -+ writel((1<<31),dwc_otg_hcd->fiq_state->mphi_regs.ctrl); -+#ifdef DEBUG -+ if (readl(dwc_otg_hcd->fiq_state->mphi_regs.ctrl) & 0x80000000) -+ DWC_WARN("MPHI periph has been enabled"); -+ else -+ DWC_WARN("MPHI periph has NOT been enabled"); -+#endif -+ // Enable FIQ interrupt from USB peripheral -+#ifdef CONFIG_ARCH_BCM2835 -+ enable_fiq(platform_get_irq(otg_dev->os_dep.platformdev, 1)); -+#else -+ enable_fiq(INTERRUPT_VC_USB); -+#endif -+ local_fiq_enable(); -+} -+ -+/** -+ * Initializes the HCD. This function allocates memory for and initializes the -+ * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the -+ * USB bus with the core and calls the hc_driver->start() function. It returns -+ * a negative error on failure. -+ */ -+int hcd_init(dwc_bus_dev_t *_dev) -+{ -+ struct usb_hcd *hcd = NULL; -+ dwc_otg_hcd_t *dwc_otg_hcd = NULL; -+ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev); -+ int retval = 0; -+ u64 dmamask; -+ -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT otg_dev=%p\n", otg_dev); -+ -+ /* Set device flags indicating whether the HCD supports DMA. */ -+ if (dwc_otg_is_dma_enable(otg_dev->core_if)) -+ dmamask = DMA_BIT_MASK(32); -+ else -+ dmamask = 0; -+ -+#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE) -+ dma_set_mask(&_dev->dev, dmamask); -+ dma_set_coherent_mask(&_dev->dev, dmamask); -+#elif defined(PCI_INTERFACE) -+ pci_set_dma_mask(_dev, dmamask); -+ pci_set_consistent_dma_mask(_dev, dmamask); -+#endif -+ -+ /* -+ * Allocate memory for the base HCD plus the DWC OTG HCD. -+ * Initialize the base HCD. -+ */ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) -+ hcd = usb_create_hcd(&dwc_otg_hc_driver, &_dev->dev, _dev->dev.bus_id); -+#else -+ hcd = usb_create_hcd(&dwc_otg_hc_driver, &_dev->dev, dev_name(&_dev->dev)); -+ hcd->has_tt = 1; -+// hcd->uses_new_polling = 1; -+// hcd->poll_rh = 0; -+#endif -+ if (!hcd) { -+ retval = -ENOMEM; -+ goto error1; -+ } -+ -+ hcd->regs = otg_dev->os_dep.base; -+ -+ -+ /* Initialize the DWC OTG HCD. */ -+ dwc_otg_hcd = dwc_otg_hcd_alloc_hcd(); -+ if (!dwc_otg_hcd) { -+ goto error2; -+ } -+ ((struct wrapper_priv_data *)(hcd->hcd_priv))->dwc_otg_hcd = -+ dwc_otg_hcd; -+ otg_dev->hcd = dwc_otg_hcd; -+ -+ if (dwc_otg_hcd_init(dwc_otg_hcd, otg_dev->core_if)) { -+ goto error2; -+ } -+ -+ if (fiq_enable) { -+ if (num_online_cpus() > 1) { -+ /* bcm2709: can run the FIQ on a separate core to IRQs */ -+ smp_call_function_single(1, hcd_init_fiq, otg_dev, 1); -+ } else { -+ smp_call_function_single(0, hcd_init_fiq, otg_dev, 1); -+ } -+ } -+ -+ otg_dev->hcd->otg_dev = otg_dev; -+ hcd->self.otg_port = dwc_otg_hcd_otg_port(dwc_otg_hcd); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,33) //don't support for LM(with 2.6.20.1 kernel) -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) //version field absent later -+ hcd->self.otg_version = dwc_otg_get_otg_version(otg_dev->core_if); -+#endif -+ /* Don't support SG list at this point */ -+ hcd->self.sg_tablesize = 0; -+#endif -+ /* -+ * Finish generic HCD initialization and start the HCD. This function -+ * allocates the DMA buffer pool, registers the USB bus, requests the -+ * IRQ line, and calls hcd_start method. -+ */ -+#ifdef PLATFORM_INTERFACE -+ retval = usb_add_hcd(hcd, platform_get_irq(_dev, fiq_enable ? 0 : 1), IRQF_SHARED); -+#else -+ retval = usb_add_hcd(hcd, _dev->irq, IRQF_SHARED); -+#endif -+ if (retval < 0) { -+ goto error2; -+ } -+ -+ dwc_otg_hcd_set_priv_data(dwc_otg_hcd, hcd); -+ return 0; -+ -+error2: -+ usb_put_hcd(hcd); -+error1: -+ return retval; -+} -+ -+/** -+ * Removes the HCD. -+ * Frees memory and resources associated with the HCD and deregisters the bus. -+ */ -+void hcd_remove(dwc_bus_dev_t *_dev) -+{ -+ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev); -+ dwc_otg_hcd_t *dwc_otg_hcd; -+ struct usb_hcd *hcd; -+ -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE otg_dev=%p\n", otg_dev); -+ -+ if (!otg_dev) { -+ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__); -+ return; -+ } -+ -+ dwc_otg_hcd = otg_dev->hcd; -+ -+ if (!dwc_otg_hcd) { -+ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__); -+ return; -+ } -+ -+ hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd); -+ -+ if (!hcd) { -+ DWC_DEBUGPL(DBG_ANY, -+ "%s: dwc_otg_hcd_to_hcd(dwc_otg_hcd) NULL!\n", -+ __func__); -+ return; -+ } -+ usb_remove_hcd(hcd); -+ dwc_otg_hcd_set_priv_data(dwc_otg_hcd, NULL); -+ dwc_otg_hcd_remove(dwc_otg_hcd); -+ usb_put_hcd(hcd); -+} -+ -+/* ========================================================================= -+ * Linux HC Driver Functions -+ * ========================================================================= */ -+ -+/** Initializes the DWC_otg controller and its root hub and prepares it for host -+ * mode operation. Activates the root port. Returns 0 on success and a negative -+ * error code on failure. */ -+int hcd_start(struct usb_hcd *hcd) -+{ -+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); -+ struct usb_bus *bus; -+ -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n"); -+ bus = hcd_to_bus(hcd); -+ -+ hcd->state = HC_STATE_RUNNING; -+ if (dwc_otg_hcd_start(dwc_otg_hcd, &hcd_fops)) { -+ return 0; -+ } -+ -+ /* Initialize and connect root hub if one is not already attached */ -+ if (bus->root_hub) { -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n"); -+ /* Inform the HUB driver to resume. */ -+ usb_hcd_resume_root_hub(hcd); -+ } -+ -+ return 0; -+} -+ -+/** -+ * Halts the DWC_otg host mode operations in a clean manner. USB transfers are -+ * stopped. -+ */ -+void hcd_stop(struct usb_hcd *hcd) -+{ -+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); -+ -+ dwc_otg_hcd_stop(dwc_otg_hcd); -+} -+ -+/** Returns the current frame number. */ -+static int get_frame_number(struct usb_hcd *hcd) -+{ -+ hprt0_data_t hprt0; -+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); -+ hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0); -+ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) -+ return dwc_otg_hcd_get_frame_number(dwc_otg_hcd) >> 3; -+ else -+ return dwc_otg_hcd_get_frame_number(dwc_otg_hcd); -+} -+ -+#ifdef DEBUG -+static void dump_urb_info(struct urb *urb, char *fn_name) -+{ -+ DWC_PRINTF("%s, urb %p\n", fn_name, urb); -+ DWC_PRINTF(" Device address: %d\n", usb_pipedevice(urb->pipe)); -+ DWC_PRINTF(" Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe), -+ (usb_pipein(urb->pipe) ? "IN" : "OUT")); -+ DWC_PRINTF(" Endpoint type: %s\n", ( { -+ char *pipetype; -+ switch (usb_pipetype(urb->pipe)) { -+case PIPE_CONTROL: -+pipetype = "CONTROL"; break; case PIPE_BULK: -+pipetype = "BULK"; break; case PIPE_INTERRUPT: -+pipetype = "INTERRUPT"; break; case PIPE_ISOCHRONOUS: -+pipetype = "ISOCHRONOUS"; break; default: -+ pipetype = "UNKNOWN"; break;}; -+ pipetype;} -+ )) ; -+ DWC_PRINTF(" Speed: %s\n", ( { -+ char *speed; switch (urb->dev->speed) { -+case USB_SPEED_HIGH: -+speed = "HIGH"; break; case USB_SPEED_FULL: -+speed = "FULL"; break; case USB_SPEED_LOW: -+speed = "LOW"; break; default: -+ speed = "UNKNOWN"; break;}; -+ speed;} -+ )) ; -+ DWC_PRINTF(" Max packet size: %d\n", -+ usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); -+ DWC_PRINTF(" Data buffer length: %d\n", urb->transfer_buffer_length); -+ DWC_PRINTF(" Transfer buffer: %p, Transfer DMA: %p\n", -+ urb->transfer_buffer, (void *)urb->transfer_dma); -+ DWC_PRINTF(" Setup buffer: %p, Setup DMA: %p\n", -+ urb->setup_packet, (void *)urb->setup_dma); -+ DWC_PRINTF(" Interval: %d\n", urb->interval); -+ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { -+ int i; -+ for (i = 0; i < urb->number_of_packets; i++) { -+ DWC_PRINTF(" ISO Desc %d:\n", i); -+ DWC_PRINTF(" offset: %d, length %d\n", -+ urb->iso_frame_desc[i].offset, -+ urb->iso_frame_desc[i].length); -+ } -+ } -+} -+#endif -+ -+/** Starts processing a USB transfer request specified by a USB Request Block -+ * (URB). mem_flags indicates the type of memory allocation to use while -+ * processing this URB. */ -+static int dwc_otg_urb_enqueue(struct usb_hcd *hcd, -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) -+ struct usb_host_endpoint *ep, -+#endif -+ struct urb *urb, gfp_t mem_flags) -+{ -+ int retval = 0; -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28) -+ struct usb_host_endpoint *ep = urb->ep; -+#endif -+ dwc_irqflags_t irqflags; -+ void **ref_ep_hcpriv = &ep->hcpriv; -+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); -+ dwc_otg_hcd_urb_t *dwc_otg_urb; -+ int i; -+ int alloc_bandwidth = 0; -+ uint8_t ep_type = 0; -+ uint32_t flags = 0; -+ void *buf; -+ -+#ifdef DEBUG -+ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { -+ dump_urb_info(urb, "dwc_otg_urb_enqueue"); -+ } -+#endif -+ -+ if (!urb->transfer_buffer && urb->transfer_buffer_length) -+ return -EINVAL; -+ -+ if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) -+ || (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) { -+ if (!dwc_otg_hcd_is_bandwidth_allocated -+ (dwc_otg_hcd, ref_ep_hcpriv)) { -+ alloc_bandwidth = 1; -+ } -+ } -+ -+ switch (usb_pipetype(urb->pipe)) { -+ case PIPE_CONTROL: -+ ep_type = USB_ENDPOINT_XFER_CONTROL; -+ break; -+ case PIPE_ISOCHRONOUS: -+ ep_type = USB_ENDPOINT_XFER_ISOC; -+ break; -+ case PIPE_BULK: -+ ep_type = USB_ENDPOINT_XFER_BULK; -+ break; -+ case PIPE_INTERRUPT: -+ ep_type = USB_ENDPOINT_XFER_INT; -+ break; -+ default: -+ DWC_WARN("Wrong EP type - %d\n", usb_pipetype(urb->pipe)); -+ } -+ -+ /* # of packets is often 0 - do we really need to call this then? */ -+ dwc_otg_urb = dwc_otg_hcd_urb_alloc(dwc_otg_hcd, -+ urb->number_of_packets, -+ mem_flags == GFP_ATOMIC ? 1 : 0); -+ -+ if(dwc_otg_urb == NULL) -+ return -ENOMEM; -+ -+ if (!dwc_otg_urb && urb->number_of_packets) -+ return -ENOMEM; -+ -+ dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_urb, usb_pipedevice(urb->pipe), -+ usb_pipeendpoint(urb->pipe), ep_type, -+ usb_pipein(urb->pipe), -+ usb_maxpacket(urb->dev, urb->pipe, -+ !(usb_pipein(urb->pipe)))); -+ -+ buf = urb->transfer_buffer; -+ if (hcd->self.uses_dma && !buf && urb->transfer_buffer_length) { -+ /* -+ * Calculate virtual address from physical address, -+ * because some class driver may not fill transfer_buffer. -+ * In Buffer DMA mode virual address is used, -+ * when handling non DWORD aligned buffers. -+ */ -+ buf = (void *)__bus_to_virt((unsigned long)urb->transfer_dma); -+ dev_warn_once(&urb->dev->dev, -+ "USB transfer_buffer was NULL, will use __bus_to_virt(%pad)=%p\n", -+ &urb->transfer_dma, buf); -+ } -+ -+ if (!(urb->transfer_flags & URB_NO_INTERRUPT)) -+ flags |= URB_GIVEBACK_ASAP; -+ if (urb->transfer_flags & URB_ZERO_PACKET) -+ flags |= URB_SEND_ZERO_PACKET; -+ -+ dwc_otg_hcd_urb_set_params(dwc_otg_urb, urb, buf, -+ urb->transfer_dma, -+ urb->transfer_buffer_length, -+ urb->setup_packet, -+ urb->setup_dma, flags, urb->interval); -+ -+ for (i = 0; i < urb->number_of_packets; ++i) { -+ dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_urb, i, -+ urb-> -+ iso_frame_desc[i].offset, -+ urb-> -+ iso_frame_desc[i].length); -+ } -+ -+ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &irqflags); -+ urb->hcpriv = dwc_otg_urb; -+#if USB_URB_EP_LINKING -+ retval = usb_hcd_link_urb_to_ep(hcd, urb); -+ if (0 == retval) -+#endif -+ { -+ retval = dwc_otg_hcd_urb_enqueue(dwc_otg_hcd, dwc_otg_urb, -+ /*(dwc_otg_qh_t **)*/ -+ ref_ep_hcpriv, 1); -+ if (0 == retval) { -+ if (alloc_bandwidth) { -+ allocate_bus_bandwidth(hcd, -+ dwc_otg_hcd_get_ep_bandwidth( -+ dwc_otg_hcd, *ref_ep_hcpriv), -+ urb); -+ } -+ } else { -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG dwc_otg_hcd_urb_enqueue failed rc %d\n", retval); -+#if USB_URB_EP_LINKING -+ usb_hcd_unlink_urb_from_ep(hcd, urb); -+#endif -+ DWC_FREE(dwc_otg_urb); -+ urb->hcpriv = NULL; -+ if (retval == -DWC_E_NO_DEVICE) -+ retval = -ENODEV; -+ } -+ } -+#if USB_URB_EP_LINKING -+ else -+ { -+ DWC_FREE(dwc_otg_urb); -+ urb->hcpriv = NULL; -+ } -+#endif -+ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, irqflags); -+ return retval; -+} -+ -+/** Aborts/cancels a USB transfer request. Always returns 0 to indicate -+ * success. */ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) -+static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb) -+#else -+static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) -+#endif -+{ -+ dwc_irqflags_t flags; -+ dwc_otg_hcd_t *dwc_otg_hcd; -+ int rc; -+ -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n"); -+ -+ dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); -+ -+#ifdef DEBUG -+ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { -+ dump_urb_info(urb, "dwc_otg_urb_dequeue"); -+ } -+#endif -+ -+ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags); -+ rc = usb_hcd_check_unlink_urb(hcd, urb, status); -+ if (0 == rc) { -+ if(urb->hcpriv != NULL) { -+ dwc_otg_hcd_urb_dequeue(dwc_otg_hcd, -+ (dwc_otg_hcd_urb_t *)urb->hcpriv); -+ -+ DWC_FREE(urb->hcpriv); -+ urb->hcpriv = NULL; -+ } -+ } -+ -+ if (0 == rc) { -+ /* Higher layer software sets URB status. */ -+#if USB_URB_EP_LINKING -+ usb_hcd_unlink_urb_from_ep(hcd, urb); -+#endif -+ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags); -+ -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) -+ usb_hcd_giveback_urb(hcd, urb); -+#else -+ usb_hcd_giveback_urb(hcd, urb, status); -+#endif -+ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { -+ DWC_PRINTF("Called usb_hcd_giveback_urb() \n"); -+ DWC_PRINTF(" 1urb->status = %d\n", urb->status); -+ } -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue OK\n"); -+ } else { -+ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags); -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue failed - rc %d\n", -+ rc); -+ } -+ -+ return rc; -+} -+ -+/* Frees resources in the DWC_otg controller related to a given endpoint. Also -+ * clears state in the HCD related to the endpoint. Any URBs for the endpoint -+ * must already be dequeued. */ -+static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep) -+{ -+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); -+ -+ DWC_DEBUGPL(DBG_HCD, -+ "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, " -+ "endpoint=%d\n", ep->desc.bEndpointAddress, -+ dwc_ep_addr_to_endpoint(ep->desc.bEndpointAddress)); -+ dwc_otg_hcd_endpoint_disable(dwc_otg_hcd, ep->hcpriv, 250); -+ ep->hcpriv = NULL; -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30) -+/* Resets endpoint specific parameter values, in current version used to reset -+ * the data toggle(as a WA). This function can be called from usb_clear_halt routine */ -+static void endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep) -+{ -+ dwc_irqflags_t flags; -+ struct usb_device *udev = NULL; -+ int epnum = usb_endpoint_num(&ep->desc); -+ int is_out = usb_endpoint_dir_out(&ep->desc); -+ int is_control = usb_endpoint_xfer_control(&ep->desc); -+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); -+ struct device *dev = DWC_OTG_OS_GETDEV(dwc_otg_hcd->otg_dev->os_dep); -+ -+ if (dev) -+ udev = to_usb_device(dev); -+ else -+ return; -+ -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP RESET: Endpoint Num=0x%02d\n", epnum); -+ -+ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags); -+ usb_settoggle(udev, epnum, is_out, 0); -+ if (is_control) -+ usb_settoggle(udev, epnum, !is_out, 0); -+ -+ if (ep->hcpriv) { -+ dwc_otg_hcd_endpoint_reset(dwc_otg_hcd, ep->hcpriv); -+ } -+ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags); -+} -+#endif -+ -+/** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if -+ * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid -+ * interrupt. -+ * -+ * This function is called by the USB core when an interrupt occurs */ -+static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd) -+{ -+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); -+ int32_t retval = dwc_otg_hcd_handle_intr(dwc_otg_hcd); -+ if (retval != 0) { -+ S3C2410X_CLEAR_EINTPEND(); -+ } -+ return IRQ_RETVAL(retval); -+} -+ -+/** Creates Status Change bitmap for the root hub and root port. The bitmap is -+ * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 -+ * is the status change indicator for the single root port. Returns 1 if either -+ * change indicator is 1, otherwise returns 0. */ -+int hub_status_data(struct usb_hcd *hcd, char *buf) -+{ -+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); -+ -+ buf[0] = 0; -+ buf[0] |= (dwc_otg_hcd_is_status_changed(dwc_otg_hcd, 1)) << 1; -+ -+ return (buf[0] != 0); -+} -+ -+/** Handles hub class-specific requests. */ -+int hub_control(struct usb_hcd *hcd, -+ u16 typeReq, u16 wValue, u16 wIndex, char *buf, u16 wLength) -+{ -+ int retval; -+ -+ retval = dwc_otg_hcd_hub_control(hcd_to_dwc_otg_hcd(hcd), -+ typeReq, wValue, wIndex, buf, wLength); -+ -+ switch (retval) { -+ case -DWC_E_INVALID: -+ retval = -EINVAL; -+ break; -+ } -+ -+ return retval; -+} -+ -+#endif /* DWC_DEVICE_ONLY */ -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c 2015-11-29 09:42:39.919098694 +0100 -@@ -0,0 +1,957 @@ -+/* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_queue.c $ -+ * $Revision: #44 $ -+ * $Date: 2011/10/26 $ -+ * $Change: 1873028 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+#ifndef DWC_DEVICE_ONLY -+ -+/** -+ * @file -+ * -+ * This file contains the functions to manage Queue Heads and Queue -+ * Transfer Descriptors. -+ */ -+ -+#include "dwc_otg_hcd.h" -+#include "dwc_otg_regs.h" -+ -+extern bool microframe_schedule; -+ -+/** -+ * Free each QTD in the QH's QTD-list then free the QH. QH should already be -+ * removed from a list. QTD list should already be empty if called from URB -+ * Dequeue. -+ * -+ * @param hcd HCD instance. -+ * @param qh The QH to free. -+ */ -+void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) -+{ -+ dwc_otg_qtd_t *qtd, *qtd_tmp; -+ dwc_irqflags_t flags; -+ -+ /* Free each QTD in the QTD list */ -+ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); -+ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) { -+ DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry); -+ dwc_otg_hcd_qtd_free(qtd); -+ } -+ -+ if (hcd->core_if->dma_desc_enable) { -+ dwc_otg_hcd_qh_free_ddma(hcd, qh); -+ } else if (qh->dw_align_buf) { -+ uint32_t buf_size; -+ if (qh->ep_type == UE_ISOCHRONOUS) { -+ buf_size = 4096; -+ } else { -+ buf_size = hcd->core_if->core_params->max_transfer_size; -+ } -+ DWC_DMA_FREE(buf_size, qh->dw_align_buf, qh->dw_align_buf_dma); -+ } -+ -+ DWC_FREE(qh); -+ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); -+ return; -+} -+ -+#define BitStuffTime(bytecount) ((8 * 7* bytecount) / 6) -+#define HS_HOST_DELAY 5 /* nanoseconds */ -+#define FS_LS_HOST_DELAY 1000 /* nanoseconds */ -+#define HUB_LS_SETUP 333 /* nanoseconds */ -+#define NS_TO_US(ns) ((ns + 500) / 1000) -+ /* convert & round nanoseconds to microseconds */ -+ -+static uint32_t calc_bus_time(int speed, int is_in, int is_isoc, int bytecount) -+{ -+ unsigned long retval; -+ -+ switch (speed) { -+ case USB_SPEED_HIGH: -+ if (is_isoc) { -+ retval = -+ ((38 * 8 * 2083) + -+ (2083 * (3 + BitStuffTime(bytecount)))) / 1000 + -+ HS_HOST_DELAY; -+ } else { -+ retval = -+ ((55 * 8 * 2083) + -+ (2083 * (3 + BitStuffTime(bytecount)))) / 1000 + -+ HS_HOST_DELAY; -+ } -+ break; -+ case USB_SPEED_FULL: -+ if (is_isoc) { -+ retval = -+ (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000; -+ if (is_in) { -+ retval = 7268 + FS_LS_HOST_DELAY + retval; -+ } else { -+ retval = 6265 + FS_LS_HOST_DELAY + retval; -+ } -+ } else { -+ retval = -+ (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000; -+ retval = 9107 + FS_LS_HOST_DELAY + retval; -+ } -+ break; -+ case USB_SPEED_LOW: -+ if (is_in) { -+ retval = -+ (67667 * (31 + 10 * BitStuffTime(bytecount))) / -+ 1000; -+ retval = -+ 64060 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY + -+ retval; -+ } else { -+ retval = -+ (66700 * (31 + 10 * BitStuffTime(bytecount))) / -+ 1000; -+ retval = -+ 64107 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY + -+ retval; -+ } -+ break; -+ default: -+ DWC_WARN("Unknown device speed\n"); -+ retval = -1; -+ } -+ -+ return NS_TO_US(retval); -+} -+ -+/** -+ * Initializes a QH structure. -+ * -+ * @param hcd The HCD state structure for the DWC OTG controller. -+ * @param qh The QH to init. -+ * @param urb Holds the information about the device/endpoint that we need -+ * to initialize the QH. -+ */ -+#define SCHEDULE_SLOP 10 -+void qh_init(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, dwc_otg_hcd_urb_t * urb) -+{ -+ char *speed, *type; -+ int dev_speed; -+ uint32_t hub_addr, hub_port; -+ -+ dwc_memset(qh, 0, sizeof(dwc_otg_qh_t)); -+ -+ /* Initialize QH */ -+ qh->ep_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info); -+ qh->ep_is_in = dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0; -+ -+ qh->data_toggle = DWC_OTG_HC_PID_DATA0; -+ qh->maxp = dwc_otg_hcd_get_mps(&urb->pipe_info); -+ DWC_CIRCLEQ_INIT(&qh->qtd_list); -+ DWC_LIST_INIT(&qh->qh_list_entry); -+ qh->channel = NULL; -+ -+ /* FS/LS Enpoint on HS Hub -+ * NOT virtual root hub */ -+ dev_speed = hcd->fops->speed(hcd, urb->priv); -+ -+ hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &hub_port); -+ qh->do_split = 0; -+ if (microframe_schedule) -+ qh->speed = dev_speed; -+ -+ qh->nak_frame = 0xffff; -+ -+ if (((dev_speed == USB_SPEED_LOW) || -+ (dev_speed == USB_SPEED_FULL)) && -+ (hub_addr != 0 && hub_addr != 1)) { -+ DWC_DEBUGPL(DBG_HCD, -+ "QH init: EP %d: TT found at hub addr %d, for port %d\n", -+ dwc_otg_hcd_get_ep_num(&urb->pipe_info), hub_addr, -+ hub_port); -+ qh->do_split = 1; -+ qh->skip_count = 0; -+ } -+ -+ if (qh->ep_type == UE_INTERRUPT || qh->ep_type == UE_ISOCHRONOUS) { -+ /* Compute scheduling parameters once and save them. */ -+ hprt0_data_t hprt; -+ -+ /** @todo Account for split transfers in the bus time. */ -+ int bytecount = -+ dwc_hb_mult(qh->maxp) * dwc_max_packet(qh->maxp); -+ -+ qh->usecs = -+ calc_bus_time((qh->do_split ? USB_SPEED_HIGH : dev_speed), -+ qh->ep_is_in, (qh->ep_type == UE_ISOCHRONOUS), -+ bytecount); -+ /* Start in a slightly future (micro)frame. */ -+ qh->sched_frame = dwc_frame_num_inc(hcd->frame_number, -+ SCHEDULE_SLOP); -+ qh->interval = urb->interval; -+ -+#if 0 -+ /* Increase interrupt polling rate for debugging. */ -+ if (qh->ep_type == UE_INTERRUPT) { -+ qh->interval = 8; -+ } -+#endif -+ hprt.d32 = DWC_READ_REG32(hcd->core_if->host_if->hprt0); -+ if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) && -+ ((dev_speed == USB_SPEED_LOW) || -+ (dev_speed == USB_SPEED_FULL))) { -+ qh->interval *= 8; -+ qh->sched_frame |= 0x7; -+ qh->start_split_frame = qh->sched_frame; -+ } -+ -+ } -+ -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n"); -+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - qh = %p\n", qh); -+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Device Address = %d\n", -+ dwc_otg_hcd_get_dev_addr(&urb->pipe_info)); -+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Endpoint %d, %s\n", -+ dwc_otg_hcd_get_ep_num(&urb->pipe_info), -+ dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"); -+ switch (dev_speed) { -+ case USB_SPEED_LOW: -+ qh->dev_speed = DWC_OTG_EP_SPEED_LOW; -+ speed = "low"; -+ break; -+ case USB_SPEED_FULL: -+ qh->dev_speed = DWC_OTG_EP_SPEED_FULL; -+ speed = "full"; -+ break; -+ case USB_SPEED_HIGH: -+ qh->dev_speed = DWC_OTG_EP_SPEED_HIGH; -+ speed = "high"; -+ break; -+ default: -+ speed = "?"; -+ break; -+ } -+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Speed = %s\n", speed); -+ -+ switch (qh->ep_type) { -+ case UE_ISOCHRONOUS: -+ type = "isochronous"; -+ break; -+ case UE_INTERRUPT: -+ type = "interrupt"; -+ break; -+ case UE_CONTROL: -+ type = "control"; -+ break; -+ case UE_BULK: -+ type = "bulk"; -+ break; -+ default: -+ type = "?"; -+ break; -+ } -+ -+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Type = %s\n", type); -+ -+#ifdef DEBUG -+ if (qh->ep_type == UE_INTERRUPT) { -+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n", -+ qh->usecs); -+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n", -+ qh->interval); -+ } -+#endif -+ -+} -+ -+/** -+ * This function allocates and initializes a QH. -+ * -+ * @param hcd The HCD state structure for the DWC OTG controller. -+ * @param urb Holds the information about the device/endpoint that we need -+ * to initialize the QH. -+ * @param atomic_alloc Flag to do atomic allocation if needed -+ * -+ * @return Returns pointer to the newly allocated QH, or NULL on error. */ -+dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd, -+ dwc_otg_hcd_urb_t * urb, int atomic_alloc) -+{ -+ dwc_otg_qh_t *qh; -+ -+ /* Allocate memory */ -+ /** @todo add memflags argument */ -+ qh = dwc_otg_hcd_qh_alloc(atomic_alloc); -+ if (qh == NULL) { -+ DWC_ERROR("qh allocation failed"); -+ return NULL; -+ } -+ -+ qh_init(hcd, qh, urb); -+ -+ if (hcd->core_if->dma_desc_enable -+ && (dwc_otg_hcd_qh_init_ddma(hcd, qh) < 0)) { -+ dwc_otg_hcd_qh_free(hcd, qh); -+ return NULL; -+ } -+ -+ return qh; -+} -+ -+/* microframe_schedule=0 start */ -+ -+/** -+ * Checks that a channel is available for a periodic transfer. -+ * -+ * @return 0 if successful, negative error code otherise. -+ */ -+static int periodic_channel_available(dwc_otg_hcd_t * hcd) -+{ -+ /* -+ * Currently assuming that there is a dedicated host channnel for each -+ * periodic transaction plus at least one host channel for -+ * non-periodic transactions. -+ */ -+ int status; -+ int num_channels; -+ -+ num_channels = hcd->core_if->core_params->host_channels; -+ if ((hcd->periodic_channels + hcd->non_periodic_channels < num_channels) -+ && (hcd->periodic_channels < num_channels - 1)) { -+ status = 0; -+ } else { -+ DWC_INFO("%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n", -+ __func__, num_channels, hcd->periodic_channels, hcd->non_periodic_channels); //NOTICE -+ status = -DWC_E_NO_SPACE; -+ } -+ -+ return status; -+} -+ -+/** -+ * Checks that there is sufficient bandwidth for the specified QH in the -+ * periodic schedule. For simplicity, this calculation assumes that all the -+ * transfers in the periodic schedule may occur in the same (micro)frame. -+ * -+ * @param hcd The HCD state structure for the DWC OTG controller. -+ * @param qh QH containing periodic bandwidth required. -+ * -+ * @return 0 if successful, negative error code otherwise. -+ */ -+static int check_periodic_bandwidth(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) -+{ -+ int status; -+ int16_t max_claimed_usecs; -+ -+ status = 0; -+ -+ if ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) || qh->do_split) { -+ /* -+ * High speed mode. -+ * Max periodic usecs is 80% x 125 usec = 100 usec. -+ */ -+ -+ max_claimed_usecs = 100 - qh->usecs; -+ } else { -+ /* -+ * Full speed mode. -+ * Max periodic usecs is 90% x 1000 usec = 900 usec. -+ */ -+ max_claimed_usecs = 900 - qh->usecs; -+ } -+ -+ if (hcd->periodic_usecs > max_claimed_usecs) { -+ DWC_INFO("%s: already claimed usecs %d, required usecs %d\n", __func__, hcd->periodic_usecs, qh->usecs); //NOTICE -+ status = -DWC_E_NO_SPACE; -+ } -+ -+ return status; -+} -+ -+/* microframe_schedule=0 end */ -+ -+/** -+ * Microframe scheduler -+ * track the total use in hcd->frame_usecs -+ * keep each qh use in qh->frame_usecs -+ * when surrendering the qh then donate the time back -+ */ -+const unsigned short max_uframe_usecs[]={ 100, 100, 100, 100, 100, 100, 30, 0 }; -+ -+/* -+ * called from dwc_otg_hcd.c:dwc_otg_hcd_init -+ */ -+int init_hcd_usecs(dwc_otg_hcd_t *_hcd) -+{ -+ int i; -+ for (i=0; i<8; i++) { -+ _hcd->frame_usecs[i] = max_uframe_usecs[i]; -+ } -+ return 0; -+} -+ -+static int find_single_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh) -+{ -+ int i; -+ unsigned short utime; -+ int t_left; -+ int ret; -+ int done; -+ -+ ret = -1; -+ utime = _qh->usecs; -+ t_left = utime; -+ i = 0; -+ done = 0; -+ while (done == 0) { -+ /* At the start _hcd->frame_usecs[i] = max_uframe_usecs[i]; */ -+ if (utime <= _hcd->frame_usecs[i]) { -+ _hcd->frame_usecs[i] -= utime; -+ _qh->frame_usecs[i] += utime; -+ t_left -= utime; -+ ret = i; -+ done = 1; -+ return ret; -+ } else { -+ i++; -+ if (i == 8) { -+ done = 1; -+ ret = -1; -+ } -+ } -+ } -+ return ret; -+ } -+ -+/* -+ * use this for FS apps that can span multiple uframes -+ */ -+static int find_multi_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh) -+{ -+ int i; -+ int j; -+ unsigned short utime; -+ int t_left; -+ int ret; -+ int done; -+ unsigned short xtime; -+ -+ ret = -1; -+ utime = _qh->usecs; -+ t_left = utime; -+ i = 0; -+ done = 0; -+loop: -+ while (done == 0) { -+ if(_hcd->frame_usecs[i] <= 0) { -+ i++; -+ if (i == 8) { -+ done = 1; -+ ret = -1; -+ } -+ goto loop; -+ } -+ -+ /* -+ * we need n consecutive slots -+ * so use j as a start slot j plus j+1 must be enough time (for now) -+ */ -+ xtime= _hcd->frame_usecs[i]; -+ for (j = i+1 ; j < 8 ; j++ ) { -+ /* -+ * if we add this frame remaining time to xtime we may -+ * be OK, if not we need to test j for a complete frame -+ */ -+ if ((xtime+_hcd->frame_usecs[j]) < utime) { -+ if (_hcd->frame_usecs[j] < max_uframe_usecs[j]) { -+ j = 8; -+ ret = -1; -+ continue; -+ } -+ } -+ if (xtime >= utime) { -+ ret = i; -+ j = 8; /* stop loop with a good value ret */ -+ continue; -+ } -+ /* add the frame time to x time */ -+ xtime += _hcd->frame_usecs[j]; -+ /* we must have a fully available next frame or break */ -+ if ((xtime < utime) -+ && (_hcd->frame_usecs[j] == max_uframe_usecs[j])) { -+ ret = -1; -+ j = 8; /* stop loop with a bad value ret */ -+ continue; -+ } -+ } -+ if (ret >= 0) { -+ t_left = utime; -+ for (j = i; (t_left>0) && (j < 8); j++ ) { -+ t_left -= _hcd->frame_usecs[j]; -+ if ( t_left <= 0 ) { -+ _qh->frame_usecs[j] += _hcd->frame_usecs[j] + t_left; -+ _hcd->frame_usecs[j]= -t_left; -+ ret = i; -+ done = 1; -+ } else { -+ _qh->frame_usecs[j] += _hcd->frame_usecs[j]; -+ _hcd->frame_usecs[j] = 0; -+ } -+ } -+ } else { -+ i++; -+ if (i == 8) { -+ done = 1; -+ ret = -1; -+ } -+ } -+ } -+ return ret; -+} -+ -+static int find_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh) -+{ -+ int ret; -+ ret = -1; -+ -+ if (_qh->speed == USB_SPEED_HIGH) { -+ /* if this is a hs transaction we need a full frame */ -+ ret = find_single_uframe(_hcd, _qh); -+ } else { -+ /* if this is a fs transaction we may need a sequence of frames */ -+ ret = find_multi_uframe(_hcd, _qh); -+ } -+ return ret; -+} -+ -+/** -+ * Checks that the max transfer size allowed in a host channel is large enough -+ * to handle the maximum data transfer in a single (micro)frame for a periodic -+ * transfer. -+ * -+ * @param hcd The HCD state structure for the DWC OTG controller. -+ * @param qh QH for a periodic endpoint. -+ * -+ * @return 0 if successful, negative error code otherwise. -+ */ -+static int check_max_xfer_size(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) -+{ -+ int status; -+ uint32_t max_xfer_size; -+ uint32_t max_channel_xfer_size; -+ -+ status = 0; -+ -+ max_xfer_size = dwc_max_packet(qh->maxp) * dwc_hb_mult(qh->maxp); -+ max_channel_xfer_size = hcd->core_if->core_params->max_transfer_size; -+ -+ if (max_xfer_size > max_channel_xfer_size) { -+ DWC_INFO("%s: Periodic xfer length %d > " "max xfer length for channel %d\n", -+ __func__, max_xfer_size, max_channel_xfer_size); //NOTICE -+ status = -DWC_E_NO_SPACE; -+ } -+ -+ return status; -+} -+ -+ -+ -+/** -+ * Schedules an interrupt or isochronous transfer in the periodic schedule. -+ * -+ * @param hcd The HCD state structure for the DWC OTG controller. -+ * @param qh QH for the periodic transfer. The QH should already contain the -+ * scheduling information. -+ * -+ * @return 0 if successful, negative error code otherwise. -+ */ -+static int schedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) -+{ -+ int status = 0; -+ -+ if (microframe_schedule) { -+ int frame; -+ status = find_uframe(hcd, qh); -+ frame = -1; -+ if (status == 0) { -+ frame = 7; -+ } else { -+ if (status > 0 ) -+ frame = status-1; -+ } -+ -+ /* Set the new frame up */ -+ if (frame > -1) { -+ qh->sched_frame &= ~0x7; -+ qh->sched_frame |= (frame & 7); -+ } -+ -+ if (status != -1) -+ status = 0; -+ } else { -+ status = periodic_channel_available(hcd); -+ if (status) { -+ DWC_INFO("%s: No host channel available for periodic " "transfer.\n", __func__); //NOTICE -+ return status; -+ } -+ -+ status = check_periodic_bandwidth(hcd, qh); -+ } -+ if (status) { -+ DWC_INFO("%s: Insufficient periodic bandwidth for " -+ "periodic transfer.\n", __func__); -+ return status; -+ } -+ status = check_max_xfer_size(hcd, qh); -+ if (status) { -+ DWC_INFO("%s: Channel max transfer size too small " -+ "for periodic transfer.\n", __func__); -+ return status; -+ } -+ -+ if (hcd->core_if->dma_desc_enable) { -+ /* Don't rely on SOF and start in ready schedule */ -+ DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_ready, &qh->qh_list_entry); -+ } -+ else { -+ if(fiq_enable && (DWC_LIST_EMPTY(&hcd->periodic_sched_inactive) || dwc_frame_num_le(qh->sched_frame, hcd->fiq_state->next_sched_frame))) -+ { -+ hcd->fiq_state->next_sched_frame = qh->sched_frame; -+ -+ } -+ /* Always start in the inactive schedule. */ -+ DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_inactive, &qh->qh_list_entry); -+ } -+ -+ if (!microframe_schedule) { -+ /* Reserve the periodic channel. */ -+ hcd->periodic_channels++; -+ } -+ -+ /* Update claimed usecs per (micro)frame. */ -+ hcd->periodic_usecs += qh->usecs; -+ -+ return status; -+} -+ -+ -+/** -+ * This function adds a QH to either the non periodic or periodic schedule if -+ * it is not already in the schedule. If the QH is already in the schedule, no -+ * action is taken. -+ * -+ * @return 0 if successful, negative error code otherwise. -+ */ -+int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) -+{ -+ int status = 0; -+ gintmsk_data_t intr_mask = {.d32 = 0 }; -+ -+ if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) { -+ /* QH already in a schedule. */ -+ return status; -+ } -+ -+ /* Add the new QH to the appropriate schedule */ -+ if (dwc_qh_is_non_per(qh)) { -+ /* Always start in the inactive schedule. */ -+ DWC_LIST_INSERT_TAIL(&hcd->non_periodic_sched_inactive, -+ &qh->qh_list_entry); -+ //hcd->fiq_state->kick_np_queues = 1; -+ } else { -+ status = schedule_periodic(hcd, qh); -+ if ( !hcd->periodic_qh_count ) { -+ intr_mask.b.sofintr = 1; -+ if (fiq_enable) { -+ local_fiq_disable(); -+ fiq_fsm_spin_lock(&hcd->fiq_state->lock); -+ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, intr_mask.d32); -+ fiq_fsm_spin_unlock(&hcd->fiq_state->lock); -+ local_fiq_enable(); -+ } else { -+ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, intr_mask.d32); -+ } -+ } -+ hcd->periodic_qh_count++; -+ } -+ -+ return status; -+} -+ -+/** -+ * Removes an interrupt or isochronous transfer from the periodic schedule. -+ * -+ * @param hcd The HCD state structure for the DWC OTG controller. -+ * @param qh QH for the periodic transfer. -+ */ -+static void deschedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) -+{ -+ int i; -+ DWC_LIST_REMOVE_INIT(&qh->qh_list_entry); -+ -+ /* Update claimed usecs per (micro)frame. */ -+ hcd->periodic_usecs -= qh->usecs; -+ -+ if (!microframe_schedule) { -+ /* Release the periodic channel reservation. */ -+ hcd->periodic_channels--; -+ } else { -+ for (i = 0; i < 8; i++) { -+ hcd->frame_usecs[i] += qh->frame_usecs[i]; -+ qh->frame_usecs[i] = 0; -+ } -+ } -+} -+ -+/** -+ * Removes a QH from either the non-periodic or periodic schedule. Memory is -+ * not freed. -+ * -+ * @param hcd The HCD state structure. -+ * @param qh QH to remove from schedule. */ -+void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) -+{ -+ gintmsk_data_t intr_mask = {.d32 = 0 }; -+ -+ if (DWC_LIST_EMPTY(&qh->qh_list_entry)) { -+ /* QH is not in a schedule. */ -+ return; -+ } -+ -+ if (dwc_qh_is_non_per(qh)) { -+ if (hcd->non_periodic_qh_ptr == &qh->qh_list_entry) { -+ hcd->non_periodic_qh_ptr = -+ hcd->non_periodic_qh_ptr->next; -+ } -+ DWC_LIST_REMOVE_INIT(&qh->qh_list_entry); -+ //if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_inactive)) -+ // hcd->fiq_state->kick_np_queues = 1; -+ } else { -+ deschedule_periodic(hcd, qh); -+ hcd->periodic_qh_count--; -+ if( !hcd->periodic_qh_count && !fiq_fsm_enable ) { -+ intr_mask.b.sofintr = 1; -+ if (fiq_enable) { -+ local_fiq_disable(); -+ fiq_fsm_spin_lock(&hcd->fiq_state->lock); -+ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, 0); -+ fiq_fsm_spin_unlock(&hcd->fiq_state->lock); -+ local_fiq_enable(); -+ } else { -+ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, 0); -+ } -+ } -+ } -+} -+ -+/** -+ * Deactivates a QH. For non-periodic QHs, removes the QH from the active -+ * non-periodic schedule. The QH is added to the inactive non-periodic -+ * schedule if any QTDs are still attached to the QH. -+ * -+ * For periodic QHs, the QH is removed from the periodic queued schedule. If -+ * there are any QTDs still attached to the QH, the QH is added to either the -+ * periodic inactive schedule or the periodic ready schedule and its next -+ * scheduled frame is calculated. The QH is placed in the ready schedule if -+ * the scheduled frame has been reached already. Otherwise it's placed in the -+ * inactive schedule. If there are no QTDs attached to the QH, the QH is -+ * completely removed from the periodic schedule. -+ */ -+void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, -+ int sched_next_periodic_split) -+{ -+ if (dwc_qh_is_non_per(qh)) { -+ dwc_otg_hcd_qh_remove(hcd, qh); -+ if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) { -+ /* Add back to inactive non-periodic schedule. */ -+ dwc_otg_hcd_qh_add(hcd, qh); -+ //hcd->fiq_state->kick_np_queues = 1; -+ } -+ } else { -+ uint16_t frame_number = dwc_otg_hcd_get_frame_number(hcd); -+ -+ if (qh->do_split) { -+ /* Schedule the next continuing periodic split transfer */ -+ if (sched_next_periodic_split) { -+ -+ qh->sched_frame = frame_number; -+ -+ if (dwc_frame_num_le(frame_number, -+ dwc_frame_num_inc -+ (qh->start_split_frame, -+ 1))) { -+ /* -+ * Allow one frame to elapse after start -+ * split microframe before scheduling -+ * complete split, but DONT if we are -+ * doing the next start split in the -+ * same frame for an ISOC out. -+ */ -+ if ((qh->ep_type != UE_ISOCHRONOUS) || -+ (qh->ep_is_in != 0)) { -+ qh->sched_frame = -+ dwc_frame_num_inc(qh->sched_frame, 1); -+ } -+ } -+ } else { -+ qh->sched_frame = -+ dwc_frame_num_inc(qh->start_split_frame, -+ qh->interval); -+ if (dwc_frame_num_le -+ (qh->sched_frame, frame_number)) { -+ qh->sched_frame = frame_number; -+ } -+ qh->sched_frame |= 0x7; -+ qh->start_split_frame = qh->sched_frame; -+ } -+ } else { -+ qh->sched_frame = -+ dwc_frame_num_inc(qh->sched_frame, qh->interval); -+ if (dwc_frame_num_le(qh->sched_frame, frame_number)) { -+ qh->sched_frame = frame_number; -+ } -+ } -+ -+ if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) { -+ dwc_otg_hcd_qh_remove(hcd, qh); -+ } else { -+ /* -+ * Remove from periodic_sched_queued and move to -+ * appropriate queue. -+ */ -+ if ((microframe_schedule && dwc_frame_num_le(qh->sched_frame, frame_number)) || -+ (!microframe_schedule && qh->sched_frame == frame_number)) { -+ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready, -+ &qh->qh_list_entry); -+ } else { -+ if(fiq_enable && !dwc_frame_num_le(hcd->fiq_state->next_sched_frame, qh->sched_frame)) -+ { -+ hcd->fiq_state->next_sched_frame = qh->sched_frame; -+ } -+ -+ DWC_LIST_MOVE_HEAD -+ (&hcd->periodic_sched_inactive, -+ &qh->qh_list_entry); -+ } -+ } -+ } -+} -+ -+/** -+ * This function allocates and initializes a QTD. -+ * -+ * @param urb The URB to create a QTD from. Each URB-QTD pair will end up -+ * pointing to each other so each pair should have a unique correlation. -+ * @param atomic_alloc Flag to do atomic alloc if needed -+ * -+ * @return Returns pointer to the newly allocated QTD, or NULL on error. */ -+dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb, int atomic_alloc) -+{ -+ dwc_otg_qtd_t *qtd; -+ -+ qtd = dwc_otg_hcd_qtd_alloc(atomic_alloc); -+ if (qtd == NULL) { -+ return NULL; -+ } -+ -+ dwc_otg_hcd_qtd_init(qtd, urb); -+ return qtd; -+} -+ -+/** -+ * Initializes a QTD structure. -+ * -+ * @param qtd The QTD to initialize. -+ * @param urb The URB to use for initialization. */ -+void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb) -+{ -+ dwc_memset(qtd, 0, sizeof(dwc_otg_qtd_t)); -+ qtd->urb = urb; -+ if (dwc_otg_hcd_get_pipe_type(&urb->pipe_info) == UE_CONTROL) { -+ /* -+ * The only time the QTD data toggle is used is on the data -+ * phase of control transfers. This phase always starts with -+ * DATA1. -+ */ -+ qtd->data_toggle = DWC_OTG_HC_PID_DATA1; -+ qtd->control_phase = DWC_OTG_CONTROL_SETUP; -+ } -+ -+ /* start split */ -+ qtd->complete_split = 0; -+ qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL; -+ qtd->isoc_split_offset = 0; -+ qtd->in_process = 0; -+ -+ /* Store the qtd ptr in the urb to reference what QTD. */ -+ urb->qtd = qtd; -+ return; -+} -+ -+/** -+ * This function adds a QTD to the QTD-list of a QH. It will find the correct -+ * QH to place the QTD into. If it does not find a QH, then it will create a -+ * new QH. If the QH to which the QTD is added is not currently scheduled, it -+ * is placed into the proper schedule based on its EP type. -+ * HCD lock must be held and interrupts must be disabled on entry -+ * -+ * @param[in] qtd The QTD to add -+ * @param[in] hcd The DWC HCD structure -+ * @param[out] qh out parameter to return queue head -+ * @param atomic_alloc Flag to do atomic alloc if needed -+ * -+ * @return 0 if successful, negative error code otherwise. -+ */ -+int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, -+ dwc_otg_hcd_t * hcd, dwc_otg_qh_t ** qh, int atomic_alloc) -+{ -+ int retval = 0; -+ dwc_otg_hcd_urb_t *urb = qtd->urb; -+ -+ /* -+ * Get the QH which holds the QTD-list to insert to. Create QH if it -+ * doesn't exist. -+ */ -+ if (*qh == NULL) { -+ *qh = dwc_otg_hcd_qh_create(hcd, urb, atomic_alloc); -+ if (*qh == NULL) { -+ retval = -DWC_E_NO_MEMORY; -+ goto done; -+ } else { -+ if (fiq_enable) -+ hcd->fiq_state->kick_np_queues = 1; -+ } -+ } -+ retval = dwc_otg_hcd_qh_add(hcd, *qh); -+ if (retval == 0) { -+ DWC_CIRCLEQ_INSERT_TAIL(&((*qh)->qtd_list), qtd, -+ qtd_list_entry); -+ qtd->qh = *qh; -+ } -+done: -+ -+ return retval; -+} -+ -+#endif /* DWC_DEVICE_ONLY */ -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h 2015-11-29 09:42:39.923098428 +0100 -@@ -0,0 +1,188 @@ -+#ifndef _DWC_OS_DEP_H_ -+#define _DWC_OS_DEP_H_ -+ -+/** -+ * @file -+ * -+ * This file contains OS dependent structures. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+# include -+#endif -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21) -+# include -+#else -+# include -+#endif -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24) -+# include -+#else -+# include -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+# include -+#endif -+ -+#ifdef PCI_INTERFACE -+# include -+#endif -+ -+#ifdef LM_INTERFACE -+# include -+# include -+# include -+# include -+# if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) -+# include -+# include -+# include -+# include -+# else -+/* in 2.6.31, at least, we seem to have lost the generic LM infrastructure - -+ here we assume that the machine architecture provides definitions -+ in its own header -+*/ -+# include -+# include -+# endif -+#endif -+ -+#ifdef PLATFORM_INTERFACE -+#include -+#include -+#endif -+ -+/** The OS page size */ -+#define DWC_OS_PAGE_SIZE PAGE_SIZE -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14) -+typedef int gfp_t; -+#endif -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) -+# define IRQF_SHARED SA_SHIRQ -+#endif -+ -+typedef struct os_dependent { -+ /** Base address returned from ioremap() */ -+ void *base; -+ -+ /** Register offset for Diagnostic API */ -+ uint32_t reg_offset; -+ -+ /** Base address for MPHI peripheral */ -+ void *mphi_base; -+ -+#ifdef LM_INTERFACE -+ struct lm_device *lmdev; -+#elif defined(PCI_INTERFACE) -+ struct pci_dev *pcidev; -+ -+ /** Start address of a PCI region */ -+ resource_size_t rsrc_start; -+ -+ /** Length address of a PCI region */ -+ resource_size_t rsrc_len; -+#elif defined(PLATFORM_INTERFACE) -+ struct platform_device *platformdev; -+#endif -+ -+} os_dependent_t; -+ -+#ifdef __cplusplus -+} -+#endif -+ -+ -+ -+/* Type for the our device on the chosen bus */ -+#if defined(LM_INTERFACE) -+typedef struct lm_device dwc_bus_dev_t; -+#elif defined(PCI_INTERFACE) -+typedef struct pci_dev dwc_bus_dev_t; -+#elif defined(PLATFORM_INTERFACE) -+typedef struct platform_device dwc_bus_dev_t; -+#endif -+ -+/* Helper macro to retrieve drvdata from the device on the chosen bus */ -+#if defined(LM_INTERFACE) -+#define DWC_OTG_BUSDRVDATA(_dev) lm_get_drvdata(_dev) -+#elif defined(PCI_INTERFACE) -+#define DWC_OTG_BUSDRVDATA(_dev) pci_get_drvdata(_dev) -+#elif defined(PLATFORM_INTERFACE) -+#define DWC_OTG_BUSDRVDATA(_dev) platform_get_drvdata(_dev) -+#endif -+ -+/** -+ * Helper macro returning the otg_device structure of a given struct device -+ * -+ * c.f. static dwc_otg_device_t *dwc_otg_drvdev(struct device *_dev) -+ */ -+#ifdef LM_INTERFACE -+#define DWC_OTG_GETDRVDEV(_var, _dev) do { \ -+ struct lm_device *lm_dev = \ -+ container_of(_dev, struct lm_device, dev); \ -+ _var = lm_get_drvdata(lm_dev); \ -+ } while (0) -+ -+#elif defined(PCI_INTERFACE) -+#define DWC_OTG_GETDRVDEV(_var, _dev) do { \ -+ _var = dev_get_drvdata(_dev); \ -+ } while (0) -+ -+#elif defined(PLATFORM_INTERFACE) -+#define DWC_OTG_GETDRVDEV(_var, _dev) do { \ -+ struct platform_device *platform_dev = \ -+ container_of(_dev, struct platform_device, dev); \ -+ _var = platform_get_drvdata(platform_dev); \ -+ } while (0) -+#endif -+ -+ -+/** -+ * Helper macro returning the struct dev of the given struct os_dependent -+ * -+ * c.f. static struct device *dwc_otg_getdev(struct os_dependent *osdep) -+ */ -+#ifdef LM_INTERFACE -+#define DWC_OTG_OS_GETDEV(_osdep) \ -+ ((_osdep).lmdev == NULL? NULL: &(_osdep).lmdev->dev) -+#elif defined(PCI_INTERFACE) -+#define DWC_OTG_OS_GETDEV(_osdep) \ -+ ((_osdep).pci_dev == NULL? NULL: &(_osdep).pci_dev->dev) -+#elif defined(PLATFORM_INTERFACE) -+#define DWC_OTG_OS_GETDEV(_osdep) \ -+ ((_osdep).platformdev == NULL? NULL: &(_osdep).platformdev->dev) -+#endif -+ -+ -+ -+ -+#endif /* _DWC_OS_DEP_H_ */ -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_pcd.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd.c ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_pcd.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd.c 2015-11-29 09:42:39.923098428 +0100 -@@ -0,0 +1,2712 @@ -+/* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.c $ -+ * $Revision: #101 $ -+ * $Date: 2012/08/10 $ -+ * $Change: 2047372 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+#ifndef DWC_HOST_ONLY -+ -+/** @file -+ * This file implements PCD Core. All code in this file is portable and doesn't -+ * use any OS specific functions. -+ * PCD Core provides Interface, defined in -+ * header file, which can be used to implement OS specific PCD interface. -+ * -+ * An important function of the PCD is managing interrupts generated -+ * by the DWC_otg controller. The implementation of the DWC_otg device -+ * mode interrupt service routines is in dwc_otg_pcd_intr.c. -+ * -+ * @todo Add Device Mode test modes (Test J mode, Test K mode, etc). -+ * @todo Does it work when the request size is greater than DEPTSIZ -+ * transfer size -+ * -+ */ -+ -+#include "dwc_otg_pcd.h" -+ -+#ifdef DWC_UTE_CFI -+#include "dwc_otg_cfi.h" -+ -+extern int init_cfi(cfiobject_t * cfiobj); -+#endif -+ -+/** -+ * Choose endpoint from ep arrays using usb_ep structure. -+ */ -+static dwc_otg_pcd_ep_t *get_ep_from_handle(dwc_otg_pcd_t * pcd, void *handle) -+{ -+ int i; -+ if (pcd->ep0.priv == handle) { -+ return &pcd->ep0; -+ } -+ for (i = 0; i < MAX_EPS_CHANNELS - 1; i++) { -+ if (pcd->in_ep[i].priv == handle) -+ return &pcd->in_ep[i]; -+ if (pcd->out_ep[i].priv == handle) -+ return &pcd->out_ep[i]; -+ } -+ -+ return NULL; -+} -+ -+/** -+ * This function completes a request. It call's the request call back. -+ */ -+void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep, dwc_otg_pcd_request_t * req, -+ int32_t status) -+{ -+ unsigned stopped = ep->stopped; -+ -+ DWC_DEBUGPL(DBG_PCDV, "%s(ep %p req %p)\n", __func__, ep, req); -+ DWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry); -+ -+ /* don't modify queue heads during completion callback */ -+ ep->stopped = 1; -+ /* spin_unlock/spin_lock now done in fops->complete() */ -+ ep->pcd->fops->complete(ep->pcd, ep->priv, req->priv, status, -+ req->actual); -+ -+ if (ep->pcd->request_pending > 0) { -+ --ep->pcd->request_pending; -+ } -+ -+ ep->stopped = stopped; -+ DWC_FREE(req); -+} -+ -+/** -+ * This function terminates all the requsts in the EP request queue. -+ */ -+void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep) -+{ -+ dwc_otg_pcd_request_t *req; -+ -+ ep->stopped = 1; -+ -+ /* called with irqs blocked?? */ -+ while (!DWC_CIRCLEQ_EMPTY(&ep->queue)) { -+ req = DWC_CIRCLEQ_FIRST(&ep->queue); -+ dwc_otg_request_done(ep, req, -DWC_E_SHUTDOWN); -+ } -+} -+ -+void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd, -+ const struct dwc_otg_pcd_function_ops *fops) -+{ -+ pcd->fops = fops; -+} -+ -+/** -+ * PCD Callback function for initializing the PCD when switching to -+ * device mode. -+ * -+ * @param p void pointer to the dwc_otg_pcd_t -+ */ -+static int32_t dwc_otg_pcd_start_cb(void *p) -+{ -+ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p; -+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); -+ -+ /* -+ * Initialized the Core for Device mode. -+ */ -+ if (dwc_otg_is_device_mode(core_if)) { -+ dwc_otg_core_dev_init(core_if); -+ /* Set core_if's lock pointer to the pcd->lock */ -+ core_if->lock = pcd->lock; -+ } -+ return 1; -+} -+ -+/** CFI-specific buffer allocation function for EP */ -+#ifdef DWC_UTE_CFI -+uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr, -+ size_t buflen, int flags) -+{ -+ dwc_otg_pcd_ep_t *ep; -+ ep = get_ep_from_handle(pcd, pep); -+ if (!ep) { -+ DWC_WARN("bad ep\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ return pcd->cfi->ops.ep_alloc_buf(pcd->cfi, pcd, ep, addr, buflen, -+ flags); -+} -+#else -+uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr, -+ size_t buflen, int flags); -+#endif -+ -+/** -+ * PCD Callback function for notifying the PCD when resuming from -+ * suspend. -+ * -+ * @param p void pointer to the dwc_otg_pcd_t -+ */ -+static int32_t dwc_otg_pcd_resume_cb(void *p) -+{ -+ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p; -+ -+ if (pcd->fops->resume) { -+ pcd->fops->resume(pcd); -+ } -+ -+ /* Stop the SRP timeout timer. */ -+ if ((GET_CORE_IF(pcd)->core_params->phy_type != DWC_PHY_TYPE_PARAM_FS) -+ || (!GET_CORE_IF(pcd)->core_params->i2c_enable)) { -+ if (GET_CORE_IF(pcd)->srp_timer_started) { -+ GET_CORE_IF(pcd)->srp_timer_started = 0; -+ DWC_TIMER_CANCEL(GET_CORE_IF(pcd)->srp_timer); -+ } -+ } -+ return 1; -+} -+ -+/** -+ * PCD Callback function for notifying the PCD device is suspended. -+ * -+ * @param p void pointer to the dwc_otg_pcd_t -+ */ -+static int32_t dwc_otg_pcd_suspend_cb(void *p) -+{ -+ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p; -+ -+ if (pcd->fops->suspend) { -+ DWC_SPINUNLOCK(pcd->lock); -+ pcd->fops->suspend(pcd); -+ DWC_SPINLOCK(pcd->lock); -+ } -+ -+ return 1; -+} -+ -+/** -+ * PCD Callback function for stopping the PCD when switching to Host -+ * mode. -+ * -+ * @param p void pointer to the dwc_otg_pcd_t -+ */ -+static int32_t dwc_otg_pcd_stop_cb(void *p) -+{ -+ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p; -+ extern void dwc_otg_pcd_stop(dwc_otg_pcd_t * _pcd); -+ -+ dwc_otg_pcd_stop(pcd); -+ return 1; -+} -+ -+/** -+ * PCD Callback structure for handling mode switching. -+ */ -+static dwc_otg_cil_callbacks_t pcd_callbacks = { -+ .start = dwc_otg_pcd_start_cb, -+ .stop = dwc_otg_pcd_stop_cb, -+ .suspend = dwc_otg_pcd_suspend_cb, -+ .resume_wakeup = dwc_otg_pcd_resume_cb, -+ .p = 0, /* Set at registration */ -+}; -+ -+/** -+ * This function allocates a DMA Descriptor chain for the Endpoint -+ * buffer to be used for a transfer to/from the specified endpoint. -+ */ -+dwc_otg_dev_dma_desc_t *dwc_otg_ep_alloc_desc_chain(dwc_dma_t * dma_desc_addr, -+ uint32_t count) -+{ -+ return DWC_DMA_ALLOC_ATOMIC(count * sizeof(dwc_otg_dev_dma_desc_t), -+ dma_desc_addr); -+} -+ -+/** -+ * This function frees a DMA Descriptor chain that was allocated by ep_alloc_desc. -+ */ -+void dwc_otg_ep_free_desc_chain(dwc_otg_dev_dma_desc_t * desc_addr, -+ uint32_t dma_desc_addr, uint32_t count) -+{ -+ DWC_DMA_FREE(count * sizeof(dwc_otg_dev_dma_desc_t), desc_addr, -+ dma_desc_addr); -+} -+ -+#ifdef DWC_EN_ISOC -+ -+/** -+ * This function initializes a descriptor chain for Isochronous transfer -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ * @param dwc_ep The EP to start the transfer on. -+ * -+ */ -+void dwc_otg_iso_ep_start_ddma_transfer(dwc_otg_core_if_t * core_if, -+ dwc_ep_t * dwc_ep) -+{ -+ -+ dsts_data_t dsts = {.d32 = 0 }; -+ depctl_data_t depctl = {.d32 = 0 }; -+ volatile uint32_t *addr; -+ int i, j; -+ uint32_t len; -+ -+ if (dwc_ep->is_in) -+ dwc_ep->desc_cnt = dwc_ep->buf_proc_intrvl / dwc_ep->bInterval; -+ else -+ dwc_ep->desc_cnt = -+ dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm / -+ dwc_ep->bInterval; -+ -+ /** Allocate descriptors for double buffering */ -+ dwc_ep->iso_desc_addr = -+ dwc_otg_ep_alloc_desc_chain(&dwc_ep->iso_dma_desc_addr, -+ dwc_ep->desc_cnt * 2); -+ if (dwc_ep->desc_addr) { -+ DWC_WARN("%s, can't allocate DMA descriptor chain\n", __func__); -+ return; -+ } -+ -+ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); -+ -+ /** ISO OUT EP */ -+ if (dwc_ep->is_in == 0) { -+ dev_dma_desc_sts_t sts = {.d32 = 0 }; -+ dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr; -+ dma_addr_t dma_ad; -+ uint32_t data_per_desc; -+ dwc_otg_dev_out_ep_regs_t *out_regs = -+ core_if->dev_if->out_ep_regs[dwc_ep->num]; -+ int offset; -+ -+ addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl; -+ dma_ad = (dma_addr_t) DWC_READ_REG32(&(out_regs->doepdma)); -+ -+ /** Buffer 0 descriptors setup */ -+ dma_ad = dwc_ep->dma_addr0; -+ -+ sts.b_iso_out.bs = BS_HOST_READY; -+ sts.b_iso_out.rxsts = 0; -+ sts.b_iso_out.l = 0; -+ sts.b_iso_out.sp = 0; -+ sts.b_iso_out.ioc = 0; -+ sts.b_iso_out.pid = 0; -+ sts.b_iso_out.framenum = 0; -+ -+ offset = 0; -+ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; -+ i += dwc_ep->pkt_per_frm) { -+ -+ for (j = 0; j < dwc_ep->pkt_per_frm; ++j) { -+ uint32_t len = (j + 1) * dwc_ep->maxpacket; -+ if (len > dwc_ep->data_per_frame) -+ data_per_desc = -+ dwc_ep->data_per_frame - -+ j * dwc_ep->maxpacket; -+ else -+ data_per_desc = dwc_ep->maxpacket; -+ len = data_per_desc % 4; -+ if (len) -+ data_per_desc += 4 - len; -+ -+ sts.b_iso_out.rxbytes = data_per_desc; -+ dma_desc->buf = dma_ad; -+ dma_desc->status.d32 = sts.d32; -+ -+ offset += data_per_desc; -+ dma_desc++; -+ dma_ad += data_per_desc; -+ } -+ } -+ -+ for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) { -+ uint32_t len = (j + 1) * dwc_ep->maxpacket; -+ if (len > dwc_ep->data_per_frame) -+ data_per_desc = -+ dwc_ep->data_per_frame - -+ j * dwc_ep->maxpacket; -+ else -+ data_per_desc = dwc_ep->maxpacket; -+ len = data_per_desc % 4; -+ if (len) -+ data_per_desc += 4 - len; -+ sts.b_iso_out.rxbytes = data_per_desc; -+ dma_desc->buf = dma_ad; -+ dma_desc->status.d32 = sts.d32; -+ -+ offset += data_per_desc; -+ dma_desc++; -+ dma_ad += data_per_desc; -+ } -+ -+ sts.b_iso_out.ioc = 1; -+ len = (j + 1) * dwc_ep->maxpacket; -+ if (len > dwc_ep->data_per_frame) -+ data_per_desc = -+ dwc_ep->data_per_frame - j * dwc_ep->maxpacket; -+ else -+ data_per_desc = dwc_ep->maxpacket; -+ len = data_per_desc % 4; -+ if (len) -+ data_per_desc += 4 - len; -+ sts.b_iso_out.rxbytes = data_per_desc; -+ -+ dma_desc->buf = dma_ad; -+ dma_desc->status.d32 = sts.d32; -+ dma_desc++; -+ -+ /** Buffer 1 descriptors setup */ -+ sts.b_iso_out.ioc = 0; -+ dma_ad = dwc_ep->dma_addr1; -+ -+ offset = 0; -+ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; -+ i += dwc_ep->pkt_per_frm) { -+ for (j = 0; j < dwc_ep->pkt_per_frm; ++j) { -+ uint32_t len = (j + 1) * dwc_ep->maxpacket; -+ if (len > dwc_ep->data_per_frame) -+ data_per_desc = -+ dwc_ep->data_per_frame - -+ j * dwc_ep->maxpacket; -+ else -+ data_per_desc = dwc_ep->maxpacket; -+ len = data_per_desc % 4; -+ if (len) -+ data_per_desc += 4 - len; -+ -+ data_per_desc = -+ sts.b_iso_out.rxbytes = data_per_desc; -+ dma_desc->buf = dma_ad; -+ dma_desc->status.d32 = sts.d32; -+ -+ offset += data_per_desc; -+ dma_desc++; -+ dma_ad += data_per_desc; -+ } -+ } -+ for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) { -+ data_per_desc = -+ ((j + 1) * dwc_ep->maxpacket > -+ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame - -+ j * dwc_ep->maxpacket : dwc_ep->maxpacket; -+ data_per_desc += -+ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0; -+ sts.b_iso_out.rxbytes = data_per_desc; -+ dma_desc->buf = dma_ad; -+ dma_desc->status.d32 = sts.d32; -+ -+ offset += data_per_desc; -+ dma_desc++; -+ dma_ad += data_per_desc; -+ } -+ -+ sts.b_iso_out.ioc = 1; -+ sts.b_iso_out.l = 1; -+ data_per_desc = -+ ((j + 1) * dwc_ep->maxpacket > -+ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame - -+ j * dwc_ep->maxpacket : dwc_ep->maxpacket; -+ data_per_desc += -+ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0; -+ sts.b_iso_out.rxbytes = data_per_desc; -+ -+ dma_desc->buf = dma_ad; -+ dma_desc->status.d32 = sts.d32; -+ -+ dwc_ep->next_frame = 0; -+ -+ /** Write dma_ad into DOEPDMA register */ -+ DWC_WRITE_REG32(&(out_regs->doepdma), -+ (uint32_t) dwc_ep->iso_dma_desc_addr); -+ -+ } -+ /** ISO IN EP */ -+ else { -+ dev_dma_desc_sts_t sts = {.d32 = 0 }; -+ dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr; -+ dma_addr_t dma_ad; -+ dwc_otg_dev_in_ep_regs_t *in_regs = -+ core_if->dev_if->in_ep_regs[dwc_ep->num]; -+ unsigned int frmnumber; -+ fifosize_data_t txfifosize, rxfifosize; -+ -+ txfifosize.d32 = -+ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[dwc_ep->num]-> -+ dtxfsts); -+ rxfifosize.d32 = -+ DWC_READ_REG32(&core_if->core_global_regs->grxfsiz); -+ -+ addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl; -+ -+ dma_ad = dwc_ep->dma_addr0; -+ -+ dsts.d32 = -+ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); -+ -+ sts.b_iso_in.bs = BS_HOST_READY; -+ sts.b_iso_in.txsts = 0; -+ sts.b_iso_in.sp = -+ (dwc_ep->data_per_frame % dwc_ep->maxpacket) ? 1 : 0; -+ sts.b_iso_in.ioc = 0; -+ sts.b_iso_in.pid = dwc_ep->pkt_per_frm; -+ -+ frmnumber = dwc_ep->next_frame; -+ -+ sts.b_iso_in.framenum = frmnumber; -+ sts.b_iso_in.txbytes = dwc_ep->data_per_frame; -+ sts.b_iso_in.l = 0; -+ -+ /** Buffer 0 descriptors setup */ -+ for (i = 0; i < dwc_ep->desc_cnt - 1; i++) { -+ dma_desc->buf = dma_ad; -+ dma_desc->status.d32 = sts.d32; -+ dma_desc++; -+ -+ dma_ad += dwc_ep->data_per_frame; -+ sts.b_iso_in.framenum += dwc_ep->bInterval; -+ } -+ -+ sts.b_iso_in.ioc = 1; -+ dma_desc->buf = dma_ad; -+ dma_desc->status.d32 = sts.d32; -+ ++dma_desc; -+ -+ /** Buffer 1 descriptors setup */ -+ sts.b_iso_in.ioc = 0; -+ dma_ad = dwc_ep->dma_addr1; -+ -+ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; -+ i += dwc_ep->pkt_per_frm) { -+ dma_desc->buf = dma_ad; -+ dma_desc->status.d32 = sts.d32; -+ dma_desc++; -+ -+ dma_ad += dwc_ep->data_per_frame; -+ sts.b_iso_in.framenum += dwc_ep->bInterval; -+ -+ sts.b_iso_in.ioc = 0; -+ } -+ sts.b_iso_in.ioc = 1; -+ sts.b_iso_in.l = 1; -+ -+ dma_desc->buf = dma_ad; -+ dma_desc->status.d32 = sts.d32; -+ -+ dwc_ep->next_frame = sts.b_iso_in.framenum + dwc_ep->bInterval; -+ -+ /** Write dma_ad into diepdma register */ -+ DWC_WRITE_REG32(&(in_regs->diepdma), -+ (uint32_t) dwc_ep->iso_dma_desc_addr); -+ } -+ /** Enable endpoint, clear nak */ -+ depctl.d32 = 0; -+ depctl.b.epena = 1; -+ depctl.b.usbactep = 1; -+ depctl.b.cnak = 1; -+ -+ DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32); -+ depctl.d32 = DWC_READ_REG32(addr); -+} -+ -+/** -+ * This function initializes a descriptor chain for Isochronous transfer -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ * @param ep The EP to start the transfer on. -+ * -+ */ -+void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if, -+ dwc_ep_t * ep) -+{ -+ depctl_data_t depctl = {.d32 = 0 }; -+ volatile uint32_t *addr; -+ -+ if (ep->is_in) { -+ addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl; -+ } else { -+ addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl; -+ } -+ -+ if (core_if->dma_enable == 0 || core_if->dma_desc_enable != 0) { -+ return; -+ } else { -+ deptsiz_data_t deptsiz = {.d32 = 0 }; -+ -+ ep->xfer_len = -+ ep->data_per_frame * ep->buf_proc_intrvl / ep->bInterval; -+ ep->pkt_cnt = -+ (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket; -+ ep->xfer_count = 0; -+ ep->xfer_buff = -+ (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0; -+ ep->dma_addr = -+ (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0; -+ -+ if (ep->is_in) { -+ /* Program the transfer size and packet count -+ * as follows: xfersize = N * maxpacket + -+ * short_packet pktcnt = N + (short_packet -+ * exist ? 1 : 0) -+ */ -+ deptsiz.b.mc = ep->pkt_per_frm; -+ deptsiz.b.xfersize = ep->xfer_len; -+ deptsiz.b.pktcnt = -+ (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket; -+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]-> -+ dieptsiz, deptsiz.d32); -+ -+ /* Write the DMA register */ -+ DWC_WRITE_REG32(& -+ (core_if->dev_if->in_ep_regs[ep->num]-> -+ diepdma), (uint32_t) ep->dma_addr); -+ -+ } else { -+ deptsiz.b.pktcnt = -+ (ep->xfer_len + (ep->maxpacket - 1)) / -+ ep->maxpacket; -+ deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket; -+ -+ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]-> -+ doeptsiz, deptsiz.d32); -+ -+ /* Write the DMA register */ -+ DWC_WRITE_REG32(& -+ (core_if->dev_if->out_ep_regs[ep->num]-> -+ doepdma), (uint32_t) ep->dma_addr); -+ -+ } -+ /** Enable endpoint, clear nak */ -+ depctl.d32 = 0; -+ depctl.b.epena = 1; -+ depctl.b.cnak = 1; -+ -+ DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32); -+ } -+} -+ -+/** -+ * This function does the setup for a data transfer for an EP and -+ * starts the transfer. For an IN transfer, the packets will be -+ * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, -+ * the packets are unloaded from the Rx FIFO in the ISR. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ * @param ep The EP to start the transfer on. -+ */ -+ -+static void dwc_otg_iso_ep_start_transfer(dwc_otg_core_if_t * core_if, -+ dwc_ep_t * ep) -+{ -+ if (core_if->dma_enable) { -+ if (core_if->dma_desc_enable) { -+ if (ep->is_in) { -+ ep->desc_cnt = ep->pkt_cnt / ep->pkt_per_frm; -+ } else { -+ ep->desc_cnt = ep->pkt_cnt; -+ } -+ dwc_otg_iso_ep_start_ddma_transfer(core_if, ep); -+ } else { -+ if (core_if->pti_enh_enable) { -+ dwc_otg_iso_ep_start_buf_transfer(core_if, ep); -+ } else { -+ ep->cur_pkt_addr = -+ (ep->proc_buf_num) ? ep->xfer_buff1 : ep-> -+ xfer_buff0; -+ ep->cur_pkt_dma_addr = -+ (ep->proc_buf_num) ? ep->dma_addr1 : ep-> -+ dma_addr0; -+ dwc_otg_iso_ep_start_frm_transfer(core_if, ep); -+ } -+ } -+ } else { -+ ep->cur_pkt_addr = -+ (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0; -+ ep->cur_pkt_dma_addr = -+ (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0; -+ dwc_otg_iso_ep_start_frm_transfer(core_if, ep); -+ } -+} -+ -+/** -+ * This function stops transfer for an EP and -+ * resets the ep's variables. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ * @param ep The EP to start the transfer on. -+ */ -+ -+void dwc_otg_iso_ep_stop_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) -+{ -+ depctl_data_t depctl = {.d32 = 0 }; -+ volatile uint32_t *addr; -+ -+ if (ep->is_in == 1) { -+ addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl; -+ } else { -+ addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl; -+ } -+ -+ /* disable the ep */ -+ depctl.d32 = DWC_READ_REG32(addr); -+ -+ depctl.b.epdis = 1; -+ depctl.b.snak = 1; -+ -+ DWC_WRITE_REG32(addr, depctl.d32); -+ -+ if (core_if->dma_desc_enable && -+ ep->iso_desc_addr && ep->iso_dma_desc_addr) { -+ dwc_otg_ep_free_desc_chain(ep->iso_desc_addr, -+ ep->iso_dma_desc_addr, -+ ep->desc_cnt * 2); -+ } -+ -+ /* reset varibales */ -+ ep->dma_addr0 = 0; -+ ep->dma_addr1 = 0; -+ ep->xfer_buff0 = 0; -+ ep->xfer_buff1 = 0; -+ ep->data_per_frame = 0; -+ ep->data_pattern_frame = 0; -+ ep->sync_frame = 0; -+ ep->buf_proc_intrvl = 0; -+ ep->bInterval = 0; -+ ep->proc_buf_num = 0; -+ ep->pkt_per_frm = 0; -+ ep->pkt_per_frm = 0; -+ ep->desc_cnt = 0; -+ ep->iso_desc_addr = 0; -+ ep->iso_dma_desc_addr = 0; -+} -+ -+int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle, -+ uint8_t * buf0, uint8_t * buf1, dwc_dma_t dma0, -+ dwc_dma_t dma1, int sync_frame, int dp_frame, -+ int data_per_frame, int start_frame, -+ int buf_proc_intrvl, void *req_handle, -+ int atomic_alloc) -+{ -+ dwc_otg_pcd_ep_t *ep; -+ dwc_irqflags_t flags = 0; -+ dwc_ep_t *dwc_ep; -+ int32_t frm_data; -+ dsts_data_t dsts; -+ dwc_otg_core_if_t *core_if; -+ -+ ep = get_ep_from_handle(pcd, ep_handle); -+ -+ if (!ep || !ep->desc || ep->dwc_ep.num == 0) { -+ DWC_WARN("bad ep\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); -+ core_if = GET_CORE_IF(pcd); -+ dwc_ep = &ep->dwc_ep; -+ -+ if (ep->iso_req_handle) { -+ DWC_WARN("ISO request in progress\n"); -+ } -+ -+ dwc_ep->dma_addr0 = dma0; -+ dwc_ep->dma_addr1 = dma1; -+ -+ dwc_ep->xfer_buff0 = buf0; -+ dwc_ep->xfer_buff1 = buf1; -+ -+ dwc_ep->data_per_frame = data_per_frame; -+ -+ /** @todo - pattern data support is to be implemented in the future */ -+ dwc_ep->data_pattern_frame = dp_frame; -+ dwc_ep->sync_frame = sync_frame; -+ -+ dwc_ep->buf_proc_intrvl = buf_proc_intrvl; -+ -+ dwc_ep->bInterval = 1 << (ep->desc->bInterval - 1); -+ -+ dwc_ep->proc_buf_num = 0; -+ -+ dwc_ep->pkt_per_frm = 0; -+ frm_data = ep->dwc_ep.data_per_frame; -+ while (frm_data > 0) { -+ dwc_ep->pkt_per_frm++; -+ frm_data -= ep->dwc_ep.maxpacket; -+ } -+ -+ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); -+ -+ if (start_frame == -1) { -+ dwc_ep->next_frame = dsts.b.soffn + 1; -+ if (dwc_ep->bInterval != 1) { -+ dwc_ep->next_frame = -+ dwc_ep->next_frame + (dwc_ep->bInterval - 1 - -+ dwc_ep->next_frame % -+ dwc_ep->bInterval); -+ } -+ } else { -+ dwc_ep->next_frame = start_frame; -+ } -+ -+ if (!core_if->pti_enh_enable) { -+ dwc_ep->pkt_cnt = -+ dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm / -+ dwc_ep->bInterval; -+ } else { -+ dwc_ep->pkt_cnt = -+ (dwc_ep->data_per_frame * -+ (dwc_ep->buf_proc_intrvl / dwc_ep->bInterval) -+ - 1 + dwc_ep->maxpacket) / dwc_ep->maxpacket; -+ } -+ -+ if (core_if->dma_desc_enable) { -+ dwc_ep->desc_cnt = -+ dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm / -+ dwc_ep->bInterval; -+ } -+ -+ if (atomic_alloc) { -+ dwc_ep->pkt_info = -+ DWC_ALLOC_ATOMIC(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt); -+ } else { -+ dwc_ep->pkt_info = -+ DWC_ALLOC(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt); -+ } -+ if (!dwc_ep->pkt_info) { -+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); -+ return -DWC_E_NO_MEMORY; -+ } -+ if (core_if->pti_enh_enable) { -+ dwc_memset(dwc_ep->pkt_info, 0, -+ sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt); -+ } -+ -+ dwc_ep->cur_pkt = 0; -+ ep->iso_req_handle = req_handle; -+ -+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); -+ dwc_otg_iso_ep_start_transfer(core_if, dwc_ep); -+ return 0; -+} -+ -+int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle, -+ void *req_handle) -+{ -+ dwc_irqflags_t flags = 0; -+ dwc_otg_pcd_ep_t *ep; -+ dwc_ep_t *dwc_ep; -+ -+ ep = get_ep_from_handle(pcd, ep_handle); -+ if (!ep || !ep->desc || ep->dwc_ep.num == 0) { -+ DWC_WARN("bad ep\n"); -+ return -DWC_E_INVALID; -+ } -+ dwc_ep = &ep->dwc_ep; -+ -+ dwc_otg_iso_ep_stop_transfer(GET_CORE_IF(pcd), dwc_ep); -+ -+ DWC_FREE(dwc_ep->pkt_info); -+ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); -+ if (ep->iso_req_handle != req_handle) { -+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); -+ return -DWC_E_INVALID; -+ } -+ -+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); -+ -+ ep->iso_req_handle = 0; -+ return 0; -+} -+ -+/** -+ * This function is used for perodical data exchnage between PCD and gadget drivers. -+ * for Isochronous EPs -+ * -+ * - Every time a sync period completes this function is called to -+ * perform data exchange between PCD and gadget -+ */ -+void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep, -+ void *req_handle) -+{ -+ int i; -+ dwc_ep_t *dwc_ep; -+ -+ dwc_ep = &ep->dwc_ep; -+ -+ DWC_SPINUNLOCK(ep->pcd->lock); -+ pcd->fops->isoc_complete(pcd, ep->priv, ep->iso_req_handle, -+ dwc_ep->proc_buf_num ^ 0x1); -+ DWC_SPINLOCK(ep->pcd->lock); -+ -+ for (i = 0; i < dwc_ep->pkt_cnt; ++i) { -+ dwc_ep->pkt_info[i].status = 0; -+ dwc_ep->pkt_info[i].offset = 0; -+ dwc_ep->pkt_info[i].length = 0; -+ } -+} -+ -+int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd, void *ep_handle, -+ void *iso_req_handle) -+{ -+ dwc_otg_pcd_ep_t *ep; -+ dwc_ep_t *dwc_ep; -+ -+ ep = get_ep_from_handle(pcd, ep_handle); -+ if (!ep->desc || ep->dwc_ep.num == 0) { -+ DWC_WARN("bad ep\n"); -+ return -DWC_E_INVALID; -+ } -+ dwc_ep = &ep->dwc_ep; -+ -+ return dwc_ep->pkt_cnt; -+} -+ -+void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd, void *ep_handle, -+ void *iso_req_handle, int packet, -+ int *status, int *actual, int *offset) -+{ -+ dwc_otg_pcd_ep_t *ep; -+ dwc_ep_t *dwc_ep; -+ -+ ep = get_ep_from_handle(pcd, ep_handle); -+ if (!ep) -+ DWC_WARN("bad ep\n"); -+ -+ dwc_ep = &ep->dwc_ep; -+ -+ *status = dwc_ep->pkt_info[packet].status; -+ *actual = dwc_ep->pkt_info[packet].length; -+ *offset = dwc_ep->pkt_info[packet].offset; -+} -+ -+#endif /* DWC_EN_ISOC */ -+ -+static void dwc_otg_pcd_init_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * pcd_ep, -+ uint32_t is_in, uint32_t ep_num) -+{ -+ /* Init EP structure */ -+ pcd_ep->desc = 0; -+ pcd_ep->pcd = pcd; -+ pcd_ep->stopped = 1; -+ pcd_ep->queue_sof = 0; -+ -+ /* Init DWC ep structure */ -+ pcd_ep->dwc_ep.is_in = is_in; -+ pcd_ep->dwc_ep.num = ep_num; -+ pcd_ep->dwc_ep.active = 0; -+ pcd_ep->dwc_ep.tx_fifo_num = 0; -+ /* Control until ep is actvated */ -+ pcd_ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL; -+ pcd_ep->dwc_ep.maxpacket = MAX_PACKET_SIZE; -+ pcd_ep->dwc_ep.dma_addr = 0; -+ pcd_ep->dwc_ep.start_xfer_buff = 0; -+ pcd_ep->dwc_ep.xfer_buff = 0; -+ pcd_ep->dwc_ep.xfer_len = 0; -+ pcd_ep->dwc_ep.xfer_count = 0; -+ pcd_ep->dwc_ep.sent_zlp = 0; -+ pcd_ep->dwc_ep.total_len = 0; -+ pcd_ep->dwc_ep.desc_addr = 0; -+ pcd_ep->dwc_ep.dma_desc_addr = 0; -+ DWC_CIRCLEQ_INIT(&pcd_ep->queue); -+} -+ -+/** -+ * Initialize ep's -+ */ -+static void dwc_otg_pcd_reinit(dwc_otg_pcd_t * pcd) -+{ -+ int i; -+ uint32_t hwcfg1; -+ dwc_otg_pcd_ep_t *ep; -+ int in_ep_cntr, out_ep_cntr; -+ uint32_t num_in_eps = (GET_CORE_IF(pcd))->dev_if->num_in_eps; -+ uint32_t num_out_eps = (GET_CORE_IF(pcd))->dev_if->num_out_eps; -+ -+ /** -+ * Initialize the EP0 structure. -+ */ -+ ep = &pcd->ep0; -+ dwc_otg_pcd_init_ep(pcd, ep, 0, 0); -+ -+ in_ep_cntr = 0; -+ hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 3; -+ for (i = 1; in_ep_cntr < num_in_eps; i++) { -+ if ((hwcfg1 & 0x1) == 0) { -+ dwc_otg_pcd_ep_t *ep = &pcd->in_ep[in_ep_cntr]; -+ in_ep_cntr++; -+ /** -+ * @todo NGS: Add direction to EP, based on contents -+ * of HWCFG1. Need a copy of HWCFG1 in pcd structure? -+ * sprintf(";r -+ */ -+ dwc_otg_pcd_init_ep(pcd, ep, 1 /* IN */ , i); -+ -+ DWC_CIRCLEQ_INIT(&ep->queue); -+ } -+ hwcfg1 >>= 2; -+ } -+ -+ out_ep_cntr = 0; -+ hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 2; -+ for (i = 1; out_ep_cntr < num_out_eps; i++) { -+ if ((hwcfg1 & 0x1) == 0) { -+ dwc_otg_pcd_ep_t *ep = &pcd->out_ep[out_ep_cntr]; -+ out_ep_cntr++; -+ /** -+ * @todo NGS: Add direction to EP, based on contents -+ * of HWCFG1. Need a copy of HWCFG1 in pcd structure? -+ * sprintf(";r -+ */ -+ dwc_otg_pcd_init_ep(pcd, ep, 0 /* OUT */ , i); -+ DWC_CIRCLEQ_INIT(&ep->queue); -+ } -+ hwcfg1 >>= 2; -+ } -+ -+ pcd->ep0state = EP0_DISCONNECT; -+ pcd->ep0.dwc_ep.maxpacket = MAX_EP0_SIZE; -+ pcd->ep0.dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL; -+} -+ -+/** -+ * This function is called when the SRP timer expires. The SRP should -+ * complete within 6 seconds. -+ */ -+static void srp_timeout(void *ptr) -+{ -+ gotgctl_data_t gotgctl; -+ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr; -+ volatile uint32_t *addr = &core_if->core_global_regs->gotgctl; -+ -+ gotgctl.d32 = DWC_READ_REG32(addr); -+ -+ core_if->srp_timer_started = 0; -+ -+ if (core_if->adp_enable) { -+ if (gotgctl.b.bsesvld == 0) { -+ gpwrdn_data_t gpwrdn = {.d32 = 0 }; -+ DWC_PRINTF("SRP Timeout BSESSVLD = 0\n"); -+ /* Power off the core */ -+ if (core_if->power_down == 2) { -+ gpwrdn.b.pwrdnswtch = 1; -+ DWC_MODIFY_REG32(&core_if-> -+ core_global_regs->gpwrdn, -+ gpwrdn.d32, 0); -+ } -+ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pmuintsel = 1; -+ gpwrdn.b.pmuactv = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, -+ gpwrdn.d32); -+ dwc_otg_adp_probe_start(core_if); -+ } else { -+ DWC_PRINTF("SRP Timeout BSESSVLD = 1\n"); -+ core_if->op_state = B_PERIPHERAL; -+ dwc_otg_core_init(core_if); -+ dwc_otg_enable_global_interrupts(core_if); -+ cil_pcd_start(core_if); -+ } -+ } -+ -+ if ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) && -+ (core_if->core_params->i2c_enable)) { -+ DWC_PRINTF("SRP Timeout\n"); -+ -+ if ((core_if->srp_success) && (gotgctl.b.bsesvld)) { -+ if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) { -+ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p); -+ } -+ -+ /* Clear Session Request */ -+ gotgctl.d32 = 0; -+ gotgctl.b.sesreq = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl, -+ gotgctl.d32, 0); -+ -+ core_if->srp_success = 0; -+ } else { -+ __DWC_ERROR("Device not connected/responding\n"); -+ gotgctl.b.sesreq = 0; -+ DWC_WRITE_REG32(addr, gotgctl.d32); -+ } -+ } else if (gotgctl.b.sesreq) { -+ DWC_PRINTF("SRP Timeout\n"); -+ -+ __DWC_ERROR("Device not connected/responding\n"); -+ gotgctl.b.sesreq = 0; -+ DWC_WRITE_REG32(addr, gotgctl.d32); -+ } else { -+ DWC_PRINTF(" SRP GOTGCTL=%0x\n", gotgctl.d32); -+ } -+} -+ -+/** -+ * Tasklet -+ * -+ */ -+extern void start_next_request(dwc_otg_pcd_ep_t * ep); -+ -+static void start_xfer_tasklet_func(void *data) -+{ -+ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data; -+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); -+ -+ int i; -+ depctl_data_t diepctl; -+ -+ DWC_DEBUGPL(DBG_PCDV, "Start xfer tasklet\n"); -+ -+ diepctl.d32 = DWC_READ_REG32(&core_if->dev_if->in_ep_regs[0]->diepctl); -+ -+ if (pcd->ep0.queue_sof) { -+ pcd->ep0.queue_sof = 0; -+ start_next_request(&pcd->ep0); -+ // break; -+ } -+ -+ for (i = 0; i < core_if->dev_if->num_in_eps; i++) { -+ depctl_data_t diepctl; -+ diepctl.d32 = -+ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl); -+ -+ if (pcd->in_ep[i].queue_sof) { -+ pcd->in_ep[i].queue_sof = 0; -+ start_next_request(&pcd->in_ep[i]); -+ // break; -+ } -+ } -+ -+ return; -+} -+ -+/** -+ * This function initialized the PCD portion of the driver. -+ * -+ */ -+dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if) -+{ -+ dwc_otg_pcd_t *pcd = NULL; -+ dwc_otg_dev_if_t *dev_if; -+ int i; -+ -+ /* -+ * Allocate PCD structure -+ */ -+ pcd = DWC_ALLOC(sizeof(dwc_otg_pcd_t)); -+ -+ if (pcd == NULL) { -+ return NULL; -+ } -+ -+#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK)) -+ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(pcd->lock); -+#else -+ pcd->lock = DWC_SPINLOCK_ALLOC(); -+#endif -+ DWC_DEBUGPL(DBG_HCDV, "Init of PCD %p given core_if %p\n", -+ pcd, core_if);//GRAYG -+ if (!pcd->lock) { -+ DWC_ERROR("Could not allocate lock for pcd"); -+ DWC_FREE(pcd); -+ return NULL; -+ } -+ /* Set core_if's lock pointer to hcd->lock */ -+ core_if->lock = pcd->lock; -+ pcd->core_if = core_if; -+ -+ dev_if = core_if->dev_if; -+ dev_if->isoc_ep = NULL; -+ -+ if (core_if->hwcfg4.b.ded_fifo_en) { -+ DWC_PRINTF("Dedicated Tx FIFOs mode\n"); -+ } else { -+ DWC_PRINTF("Shared Tx FIFO mode\n"); -+ } -+ -+ /* -+ * Initialized the Core for Device mode here if there is nod ADP support. -+ * Otherwise it will be done later in dwc_otg_adp_start routine. -+ */ -+ if (dwc_otg_is_device_mode(core_if) /*&& !core_if->adp_enable*/) { -+ dwc_otg_core_dev_init(core_if); -+ } -+ -+ /* -+ * Register the PCD Callbacks. -+ */ -+ dwc_otg_cil_register_pcd_callbacks(core_if, &pcd_callbacks, pcd); -+ -+ /* -+ * Initialize the DMA buffer for SETUP packets -+ */ -+ if (GET_CORE_IF(pcd)->dma_enable) { -+ pcd->setup_pkt = -+ DWC_DMA_ALLOC(sizeof(*pcd->setup_pkt) * 5, -+ &pcd->setup_pkt_dma_handle); -+ if (pcd->setup_pkt == NULL) { -+ DWC_FREE(pcd); -+ return NULL; -+ } -+ -+ pcd->status_buf = -+ DWC_DMA_ALLOC(sizeof(uint16_t), -+ &pcd->status_buf_dma_handle); -+ if (pcd->status_buf == NULL) { -+ DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5, -+ pcd->setup_pkt, pcd->setup_pkt_dma_handle); -+ DWC_FREE(pcd); -+ return NULL; -+ } -+ -+ if (GET_CORE_IF(pcd)->dma_desc_enable) { -+ dev_if->setup_desc_addr[0] = -+ dwc_otg_ep_alloc_desc_chain -+ (&dev_if->dma_setup_desc_addr[0], 1); -+ dev_if->setup_desc_addr[1] = -+ dwc_otg_ep_alloc_desc_chain -+ (&dev_if->dma_setup_desc_addr[1], 1); -+ dev_if->in_desc_addr = -+ dwc_otg_ep_alloc_desc_chain -+ (&dev_if->dma_in_desc_addr, 1); -+ dev_if->out_desc_addr = -+ dwc_otg_ep_alloc_desc_chain -+ (&dev_if->dma_out_desc_addr, 1); -+ pcd->data_terminated = 0; -+ -+ if (dev_if->setup_desc_addr[0] == 0 -+ || dev_if->setup_desc_addr[1] == 0 -+ || dev_if->in_desc_addr == 0 -+ || dev_if->out_desc_addr == 0) { -+ -+ if (dev_if->out_desc_addr) -+ dwc_otg_ep_free_desc_chain -+ (dev_if->out_desc_addr, -+ dev_if->dma_out_desc_addr, 1); -+ if (dev_if->in_desc_addr) -+ dwc_otg_ep_free_desc_chain -+ (dev_if->in_desc_addr, -+ dev_if->dma_in_desc_addr, 1); -+ if (dev_if->setup_desc_addr[1]) -+ dwc_otg_ep_free_desc_chain -+ (dev_if->setup_desc_addr[1], -+ dev_if->dma_setup_desc_addr[1], 1); -+ if (dev_if->setup_desc_addr[0]) -+ dwc_otg_ep_free_desc_chain -+ (dev_if->setup_desc_addr[0], -+ dev_if->dma_setup_desc_addr[0], 1); -+ -+ DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5, -+ pcd->setup_pkt, -+ pcd->setup_pkt_dma_handle); -+ DWC_DMA_FREE(sizeof(*pcd->status_buf), -+ pcd->status_buf, -+ pcd->status_buf_dma_handle); -+ -+ DWC_FREE(pcd); -+ -+ return NULL; -+ } -+ } -+ } else { -+ pcd->setup_pkt = DWC_ALLOC(sizeof(*pcd->setup_pkt) * 5); -+ if (pcd->setup_pkt == NULL) { -+ DWC_FREE(pcd); -+ return NULL; -+ } -+ -+ pcd->status_buf = DWC_ALLOC(sizeof(uint16_t)); -+ if (pcd->status_buf == NULL) { -+ DWC_FREE(pcd->setup_pkt); -+ DWC_FREE(pcd); -+ return NULL; -+ } -+ } -+ -+ dwc_otg_pcd_reinit(pcd); -+ -+ /* Allocate the cfi object for the PCD */ -+#ifdef DWC_UTE_CFI -+ pcd->cfi = DWC_ALLOC(sizeof(cfiobject_t)); -+ if (NULL == pcd->cfi) -+ goto fail; -+ if (init_cfi(pcd->cfi)) { -+ CFI_INFO("%s: Failed to init the CFI object\n", __func__); -+ goto fail; -+ } -+#endif -+ -+ /* Initialize tasklets */ -+ pcd->start_xfer_tasklet = DWC_TASK_ALLOC("xfer_tasklet", -+ start_xfer_tasklet_func, pcd); -+ pcd->test_mode_tasklet = DWC_TASK_ALLOC("test_mode_tasklet", -+ do_test_mode, pcd); -+ -+ /* Initialize SRP timer */ -+ core_if->srp_timer = DWC_TIMER_ALLOC("SRP TIMER", srp_timeout, core_if); -+ -+ if (core_if->core_params->dev_out_nak) { -+ /** -+ * Initialize xfer timeout timer. Implemented for -+ * 2.93a feature "Device DDMA OUT NAK Enhancement" -+ */ -+ for(i = 0; i < MAX_EPS_CHANNELS; i++) { -+ pcd->core_if->ep_xfer_timer[i] = -+ DWC_TIMER_ALLOC("ep timer", ep_xfer_timeout, -+ &pcd->core_if->ep_xfer_info[i]); -+ } -+ } -+ -+ return pcd; -+#ifdef DWC_UTE_CFI -+fail: -+#endif -+ if (pcd->setup_pkt) -+ DWC_FREE(pcd->setup_pkt); -+ if (pcd->status_buf) -+ DWC_FREE(pcd->status_buf); -+#ifdef DWC_UTE_CFI -+ if (pcd->cfi) -+ DWC_FREE(pcd->cfi); -+#endif -+ if (pcd) -+ DWC_FREE(pcd); -+ return NULL; -+ -+} -+ -+/** -+ * Remove PCD specific data -+ */ -+void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd) -+{ -+ dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if; -+ int i; -+ if (pcd->core_if->core_params->dev_out_nak) { -+ for (i = 0; i < MAX_EPS_CHANNELS; i++) { -+ DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[i]); -+ pcd->core_if->ep_xfer_info[i].state = 0; -+ } -+ } -+ -+ if (GET_CORE_IF(pcd)->dma_enable) { -+ DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5, pcd->setup_pkt, -+ pcd->setup_pkt_dma_handle); -+ DWC_DMA_FREE(sizeof(uint16_t), pcd->status_buf, -+ pcd->status_buf_dma_handle); -+ if (GET_CORE_IF(pcd)->dma_desc_enable) { -+ dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[0], -+ dev_if->dma_setup_desc_addr -+ [0], 1); -+ dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[1], -+ dev_if->dma_setup_desc_addr -+ [1], 1); -+ dwc_otg_ep_free_desc_chain(dev_if->in_desc_addr, -+ dev_if->dma_in_desc_addr, 1); -+ dwc_otg_ep_free_desc_chain(dev_if->out_desc_addr, -+ dev_if->dma_out_desc_addr, -+ 1); -+ } -+ } else { -+ DWC_FREE(pcd->setup_pkt); -+ DWC_FREE(pcd->status_buf); -+ } -+ DWC_SPINLOCK_FREE(pcd->lock); -+ /* Set core_if's lock pointer to NULL */ -+ pcd->core_if->lock = NULL; -+ -+ DWC_TASK_FREE(pcd->start_xfer_tasklet); -+ DWC_TASK_FREE(pcd->test_mode_tasklet); -+ if (pcd->core_if->core_params->dev_out_nak) { -+ for (i = 0; i < MAX_EPS_CHANNELS; i++) { -+ if (pcd->core_if->ep_xfer_timer[i]) { -+ DWC_TIMER_FREE(pcd->core_if->ep_xfer_timer[i]); -+ } -+ } -+ } -+ -+/* Release the CFI object's dynamic memory */ -+#ifdef DWC_UTE_CFI -+ if (pcd->cfi->ops.release) { -+ pcd->cfi->ops.release(pcd->cfi); -+ } -+#endif -+ -+ DWC_FREE(pcd); -+} -+ -+/** -+ * Returns whether registered pcd is dual speed or not -+ */ -+uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd) -+{ -+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); -+ -+ if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) || -+ ((core_if->hwcfg2.b.hs_phy_type == 2) && -+ (core_if->hwcfg2.b.fs_phy_type == 1) && -+ (core_if->core_params->ulpi_fs_ls))) { -+ return 0; -+ } -+ -+ return 1; -+} -+ -+/** -+ * Returns whether registered pcd is OTG capable or not -+ */ -+uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd) -+{ -+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); -+ gusbcfg_data_t usbcfg = {.d32 = 0 }; -+ -+ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); -+ if (!usbcfg.b.srpcap || !usbcfg.b.hnpcap) { -+ return 0; -+ } -+ -+ return 1; -+} -+ -+/** -+ * This function assigns periodic Tx FIFO to an periodic EP -+ * in shared Tx FIFO mode -+ */ -+static uint32_t assign_tx_fifo(dwc_otg_core_if_t * core_if) -+{ -+ uint32_t TxMsk = 1; -+ int i; -+ -+ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; ++i) { -+ if ((TxMsk & core_if->tx_msk) == 0) { -+ core_if->tx_msk |= TxMsk; -+ return i + 1; -+ } -+ TxMsk <<= 1; -+ } -+ return 0; -+} -+ -+/** -+ * This function assigns periodic Tx FIFO to an periodic EP -+ * in shared Tx FIFO mode -+ */ -+static uint32_t assign_perio_tx_fifo(dwc_otg_core_if_t * core_if) -+{ -+ uint32_t PerTxMsk = 1; -+ int i; -+ for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; ++i) { -+ if ((PerTxMsk & core_if->p_tx_msk) == 0) { -+ core_if->p_tx_msk |= PerTxMsk; -+ return i + 1; -+ } -+ PerTxMsk <<= 1; -+ } -+ return 0; -+} -+ -+/** -+ * This function releases periodic Tx FIFO -+ * in shared Tx FIFO mode -+ */ -+static void release_perio_tx_fifo(dwc_otg_core_if_t * core_if, -+ uint32_t fifo_num) -+{ -+ core_if->p_tx_msk = -+ (core_if->p_tx_msk & (1 << (fifo_num - 1))) ^ core_if->p_tx_msk; -+} -+ -+/** -+ * This function releases periodic Tx FIFO -+ * in shared Tx FIFO mode -+ */ -+static void release_tx_fifo(dwc_otg_core_if_t * core_if, uint32_t fifo_num) -+{ -+ core_if->tx_msk = -+ (core_if->tx_msk & (1 << (fifo_num - 1))) ^ core_if->tx_msk; -+} -+ -+/** -+ * This function is being called from gadget -+ * to enable PCD endpoint. -+ */ -+int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd, -+ const uint8_t * ep_desc, void *usb_ep) -+{ -+ int num, dir; -+ dwc_otg_pcd_ep_t *ep = NULL; -+ const usb_endpoint_descriptor_t *desc; -+ dwc_irqflags_t flags; -+ fifosize_data_t dptxfsiz = {.d32 = 0 }; -+ gdfifocfg_data_t gdfifocfg = {.d32 = 0 }; -+ gdfifocfg_data_t gdfifocfgbase = {.d32 = 0 }; -+ int retval = 0; -+ int i, epcount; -+ -+ desc = (const usb_endpoint_descriptor_t *)ep_desc; -+ -+ if (!desc) { -+ pcd->ep0.priv = usb_ep; -+ ep = &pcd->ep0; -+ retval = -DWC_E_INVALID; -+ goto out; -+ } -+ -+ num = UE_GET_ADDR(desc->bEndpointAddress); -+ dir = UE_GET_DIR(desc->bEndpointAddress); -+ -+ if (!desc->wMaxPacketSize) { -+ DWC_WARN("bad maxpacketsize\n"); -+ retval = -DWC_E_INVALID; -+ goto out; -+ } -+ -+ if (dir == UE_DIR_IN) { -+ epcount = pcd->core_if->dev_if->num_in_eps; -+ for (i = 0; i < epcount; i++) { -+ if (num == pcd->in_ep[i].dwc_ep.num) { -+ ep = &pcd->in_ep[i]; -+ break; -+ } -+ } -+ } else { -+ epcount = pcd->core_if->dev_if->num_out_eps; -+ for (i = 0; i < epcount; i++) { -+ if (num == pcd->out_ep[i].dwc_ep.num) { -+ ep = &pcd->out_ep[i]; -+ break; -+ } -+ } -+ } -+ -+ if (!ep) { -+ DWC_WARN("bad address\n"); -+ retval = -DWC_E_INVALID; -+ goto out; -+ } -+ -+ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); -+ -+ ep->desc = desc; -+ ep->priv = usb_ep; -+ -+ /* -+ * Activate the EP -+ */ -+ ep->stopped = 0; -+ -+ ep->dwc_ep.is_in = (dir == UE_DIR_IN); -+ ep->dwc_ep.maxpacket = UGETW(desc->wMaxPacketSize); -+ -+ ep->dwc_ep.type = desc->bmAttributes & UE_XFERTYPE; -+ -+ if (ep->dwc_ep.is_in) { -+ if (!GET_CORE_IF(pcd)->en_multiple_tx_fifo) { -+ ep->dwc_ep.tx_fifo_num = 0; -+ -+ if (ep->dwc_ep.type == UE_ISOCHRONOUS) { -+ /* -+ * if ISOC EP then assign a Periodic Tx FIFO. -+ */ -+ ep->dwc_ep.tx_fifo_num = -+ assign_perio_tx_fifo(GET_CORE_IF(pcd)); -+ } -+ } else { -+ /* -+ * if Dedicated FIFOs mode is on then assign a Tx FIFO. -+ */ -+ ep->dwc_ep.tx_fifo_num = -+ assign_tx_fifo(GET_CORE_IF(pcd)); -+ } -+ -+ /* Calculating EP info controller base address */ -+ if (ep->dwc_ep.tx_fifo_num -+ && GET_CORE_IF(pcd)->en_multiple_tx_fifo) { -+ gdfifocfg.d32 = -+ DWC_READ_REG32(&GET_CORE_IF(pcd)-> -+ core_global_regs->gdfifocfg); -+ gdfifocfgbase.d32 = gdfifocfg.d32 >> 16; -+ dptxfsiz.d32 = -+ (DWC_READ_REG32 -+ (&GET_CORE_IF(pcd)->core_global_regs-> -+ dtxfsiz[ep->dwc_ep.tx_fifo_num - 1]) >> 16); -+ gdfifocfg.b.epinfobase = -+ gdfifocfgbase.d32 + dptxfsiz.d32; -+ if (GET_CORE_IF(pcd)->snpsid <= OTG_CORE_REV_2_94a) { -+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)-> -+ core_global_regs->gdfifocfg, -+ gdfifocfg.d32); -+ } -+ } -+ } -+ /* Set initial data PID. */ -+ if (ep->dwc_ep.type == UE_BULK) { -+ ep->dwc_ep.data_pid_start = 0; -+ } -+ -+ /* Alloc DMA Descriptors */ -+ if (GET_CORE_IF(pcd)->dma_desc_enable) { -+#ifndef DWC_UTE_PER_IO -+ if (ep->dwc_ep.type != UE_ISOCHRONOUS) { -+#endif -+ ep->dwc_ep.desc_addr = -+ dwc_otg_ep_alloc_desc_chain(&ep-> -+ dwc_ep.dma_desc_addr, -+ MAX_DMA_DESC_CNT); -+ if (!ep->dwc_ep.desc_addr) { -+ DWC_WARN("%s, can't allocate DMA descriptor\n", -+ __func__); -+ retval = -DWC_E_SHUTDOWN; -+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); -+ goto out; -+ } -+#ifndef DWC_UTE_PER_IO -+ } -+#endif -+ } -+ -+ DWC_DEBUGPL(DBG_PCD, "Activate %s: type=%d, mps=%d desc=%p\n", -+ (ep->dwc_ep.is_in ? "IN" : "OUT"), -+ ep->dwc_ep.type, ep->dwc_ep.maxpacket, ep->desc); -+#ifdef DWC_UTE_PER_IO -+ ep->dwc_ep.xiso_bInterval = 1 << (ep->desc->bInterval - 1); -+#endif -+ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) { -+ ep->dwc_ep.bInterval = 1 << (ep->desc->bInterval - 1); -+ ep->dwc_ep.frame_num = 0xFFFFFFFF; -+ } -+ -+ dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep); -+ -+#ifdef DWC_UTE_CFI -+ if (pcd->cfi->ops.ep_enable) { -+ pcd->cfi->ops.ep_enable(pcd->cfi, pcd, ep); -+ } -+#endif -+ -+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); -+ -+out: -+ return retval; -+} -+ -+/** -+ * This function is being called from gadget -+ * to disable PCD endpoint. -+ */ -+int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle) -+{ -+ dwc_otg_pcd_ep_t *ep; -+ dwc_irqflags_t flags; -+ dwc_otg_dev_dma_desc_t *desc_addr; -+ dwc_dma_t dma_desc_addr; -+ gdfifocfg_data_t gdfifocfgbase = {.d32 = 0 }; -+ gdfifocfg_data_t gdfifocfg = {.d32 = 0 }; -+ fifosize_data_t dptxfsiz = {.d32 = 0 }; -+ -+ ep = get_ep_from_handle(pcd, ep_handle); -+ -+ if (!ep || !ep->desc) { -+ DWC_DEBUGPL(DBG_PCD, "bad ep address\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); -+ -+ dwc_otg_request_nuke(ep); -+ -+ dwc_otg_ep_deactivate(GET_CORE_IF(pcd), &ep->dwc_ep); -+ if (pcd->core_if->core_params->dev_out_nak) { -+ DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[ep->dwc_ep.num]); -+ pcd->core_if->ep_xfer_info[ep->dwc_ep.num].state = 0; -+ } -+ ep->desc = NULL; -+ ep->stopped = 1; -+ -+ gdfifocfg.d32 = -+ DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs->gdfifocfg); -+ gdfifocfgbase.d32 = gdfifocfg.d32 >> 16; -+ -+ if (ep->dwc_ep.is_in) { -+ if (GET_CORE_IF(pcd)->en_multiple_tx_fifo) { -+ /* Flush the Tx FIFO */ -+ dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), -+ ep->dwc_ep.tx_fifo_num); -+ } -+ release_perio_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num); -+ release_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num); -+ if (GET_CORE_IF(pcd)->en_multiple_tx_fifo) { -+ /* Decreasing EPinfo Base Addr */ -+ dptxfsiz.d32 = -+ (DWC_READ_REG32 -+ (&GET_CORE_IF(pcd)-> -+ core_global_regs->dtxfsiz[ep->dwc_ep.tx_fifo_num-1]) >> 16); -+ gdfifocfg.b.epinfobase = gdfifocfgbase.d32 - dptxfsiz.d32; -+ if (GET_CORE_IF(pcd)->snpsid <= OTG_CORE_REV_2_94a) { -+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gdfifocfg, -+ gdfifocfg.d32); -+ } -+ } -+ } -+ -+ /* Free DMA Descriptors */ -+ if (GET_CORE_IF(pcd)->dma_desc_enable) { -+ if (ep->dwc_ep.type != UE_ISOCHRONOUS) { -+ desc_addr = ep->dwc_ep.desc_addr; -+ dma_desc_addr = ep->dwc_ep.dma_desc_addr; -+ -+ /* Cannot call dma_free_coherent() with IRQs disabled */ -+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); -+ dwc_otg_ep_free_desc_chain(desc_addr, dma_desc_addr, -+ MAX_DMA_DESC_CNT); -+ -+ goto out_unlocked; -+ } -+ } -+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); -+ -+out_unlocked: -+ DWC_DEBUGPL(DBG_PCD, "%d %s disabled\n", ep->dwc_ep.num, -+ ep->dwc_ep.is_in ? "IN" : "OUT"); -+ return 0; -+ -+} -+ -+/******************************************************************************/ -+#ifdef DWC_UTE_PER_IO -+ -+/** -+ * Free the request and its extended parts -+ * -+ */ -+void dwc_pcd_xiso_ereq_free(dwc_otg_pcd_ep_t * ep, dwc_otg_pcd_request_t * req) -+{ -+ DWC_FREE(req->ext_req.per_io_frame_descs); -+ DWC_FREE(req); -+} -+ -+/** -+ * Start the next request in the endpoint's queue. -+ * -+ */ -+int dwc_otg_pcd_xiso_start_next_request(dwc_otg_pcd_t * pcd, -+ dwc_otg_pcd_ep_t * ep) -+{ -+ int i; -+ dwc_otg_pcd_request_t *req = NULL; -+ dwc_ep_t *dwcep = NULL; -+ struct dwc_iso_xreq_port *ereq = NULL; -+ struct dwc_iso_pkt_desc_port *ddesc_iso; -+ uint16_t nat; -+ depctl_data_t diepctl; -+ -+ dwcep = &ep->dwc_ep; -+ -+ if (dwcep->xiso_active_xfers > 0) { -+#if 0 //Disable this to decrease s/w overhead that is crucial for Isoc transfers -+ DWC_WARN("There are currently active transfers for EP%d \ -+ (active=%d; queued=%d)", dwcep->num, dwcep->xiso_active_xfers, -+ dwcep->xiso_queued_xfers); -+#endif -+ return 0; -+ } -+ -+ nat = UGETW(ep->desc->wMaxPacketSize); -+ nat = (nat >> 11) & 0x03; -+ -+ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) { -+ req = DWC_CIRCLEQ_FIRST(&ep->queue); -+ ereq = &req->ext_req; -+ ep->stopped = 0; -+ -+ /* Get the frame number */ -+ dwcep->xiso_frame_num = -+ dwc_otg_get_frame_number(GET_CORE_IF(pcd)); -+ DWC_DEBUG("FRM_NUM=%d", dwcep->xiso_frame_num); -+ -+ ddesc_iso = ereq->per_io_frame_descs; -+ -+ if (dwcep->is_in) { -+ /* Setup DMA Descriptor chain for IN Isoc request */ -+ for (i = 0; i < ereq->pio_pkt_count; i++) { -+ //if ((i % (nat + 1)) == 0) -+ if ( i > 0 ) -+ dwcep->xiso_frame_num = -+ (dwcep->xiso_bInterval + -+ dwcep->xiso_frame_num) & 0x3FFF; -+ dwcep->desc_addr[i].buf = -+ req->dma + ddesc_iso[i].offset; -+ dwcep->desc_addr[i].status.b_iso_in.txbytes = -+ ddesc_iso[i].length; -+ dwcep->desc_addr[i].status.b_iso_in.framenum = -+ dwcep->xiso_frame_num; -+ dwcep->desc_addr[i].status.b_iso_in.bs = -+ BS_HOST_READY; -+ dwcep->desc_addr[i].status.b_iso_in.txsts = 0; -+ dwcep->desc_addr[i].status.b_iso_in.sp = -+ (ddesc_iso[i].length % -+ dwcep->maxpacket) ? 1 : 0; -+ dwcep->desc_addr[i].status.b_iso_in.ioc = 0; -+ dwcep->desc_addr[i].status.b_iso_in.pid = nat + 1; -+ dwcep->desc_addr[i].status.b_iso_in.l = 0; -+ -+ /* Process the last descriptor */ -+ if (i == ereq->pio_pkt_count - 1) { -+ dwcep->desc_addr[i].status.b_iso_in.ioc = 1; -+ dwcep->desc_addr[i].status.b_iso_in.l = 1; -+ } -+ } -+ -+ /* Setup and start the transfer for this endpoint */ -+ dwcep->xiso_active_xfers++; -+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->dev_if-> -+ in_ep_regs[dwcep->num]->diepdma, -+ dwcep->dma_desc_addr); -+ diepctl.d32 = 0; -+ diepctl.b.epena = 1; -+ diepctl.b.cnak = 1; -+ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->dev_if-> -+ in_ep_regs[dwcep->num]->diepctl, 0, -+ diepctl.d32); -+ } else { -+ /* Setup DMA Descriptor chain for OUT Isoc request */ -+ for (i = 0; i < ereq->pio_pkt_count; i++) { -+ //if ((i % (nat + 1)) == 0) -+ dwcep->xiso_frame_num = (dwcep->xiso_bInterval + -+ dwcep->xiso_frame_num) & 0x3FFF; -+ dwcep->desc_addr[i].buf = -+ req->dma + ddesc_iso[i].offset; -+ dwcep->desc_addr[i].status.b_iso_out.rxbytes = -+ ddesc_iso[i].length; -+ dwcep->desc_addr[i].status.b_iso_out.framenum = -+ dwcep->xiso_frame_num; -+ dwcep->desc_addr[i].status.b_iso_out.bs = -+ BS_HOST_READY; -+ dwcep->desc_addr[i].status.b_iso_out.rxsts = 0; -+ dwcep->desc_addr[i].status.b_iso_out.sp = -+ (ddesc_iso[i].length % -+ dwcep->maxpacket) ? 1 : 0; -+ dwcep->desc_addr[i].status.b_iso_out.ioc = 0; -+ dwcep->desc_addr[i].status.b_iso_out.pid = nat + 1; -+ dwcep->desc_addr[i].status.b_iso_out.l = 0; -+ -+ /* Process the last descriptor */ -+ if (i == ereq->pio_pkt_count - 1) { -+ dwcep->desc_addr[i].status.b_iso_out.ioc = 1; -+ dwcep->desc_addr[i].status.b_iso_out.l = 1; -+ } -+ } -+ -+ /* Setup and start the transfer for this endpoint */ -+ dwcep->xiso_active_xfers++; -+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)-> -+ dev_if->out_ep_regs[dwcep->num]-> -+ doepdma, dwcep->dma_desc_addr); -+ diepctl.d32 = 0; -+ diepctl.b.epena = 1; -+ diepctl.b.cnak = 1; -+ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)-> -+ dev_if->out_ep_regs[dwcep->num]-> -+ doepctl, 0, diepctl.d32); -+ } -+ -+ } else { -+ ep->stopped = 1; -+ } -+ -+ return 0; -+} -+ -+/** -+ * - Remove the request from the queue -+ */ -+void complete_xiso_ep(dwc_otg_pcd_ep_t * ep) -+{ -+ dwc_otg_pcd_request_t *req = NULL; -+ struct dwc_iso_xreq_port *ereq = NULL; -+ struct dwc_iso_pkt_desc_port *ddesc_iso = NULL; -+ dwc_ep_t *dwcep = NULL; -+ int i; -+ -+ //DWC_DEBUG(); -+ dwcep = &ep->dwc_ep; -+ -+ /* Get the first pending request from the queue */ -+ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) { -+ req = DWC_CIRCLEQ_FIRST(&ep->queue); -+ if (!req) { -+ DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep); -+ return; -+ } -+ dwcep->xiso_active_xfers--; -+ dwcep->xiso_queued_xfers--; -+ /* Remove this request from the queue */ -+ DWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry); -+ } else { -+ DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep); -+ return; -+ } -+ -+ ep->stopped = 1; -+ ereq = &req->ext_req; -+ ddesc_iso = ereq->per_io_frame_descs; -+ -+ if (dwcep->xiso_active_xfers < 0) { -+ DWC_WARN("EP#%d (xiso_active_xfers=%d)", dwcep->num, -+ dwcep->xiso_active_xfers); -+ } -+ -+ /* Fill the Isoc descs of portable extended req from dma descriptors */ -+ for (i = 0; i < ereq->pio_pkt_count; i++) { -+ if (dwcep->is_in) { /* IN endpoints */ -+ ddesc_iso[i].actual_length = ddesc_iso[i].length - -+ dwcep->desc_addr[i].status.b_iso_in.txbytes; -+ ddesc_iso[i].status = -+ dwcep->desc_addr[i].status.b_iso_in.txsts; -+ } else { /* OUT endpoints */ -+ ddesc_iso[i].actual_length = ddesc_iso[i].length - -+ dwcep->desc_addr[i].status.b_iso_out.rxbytes; -+ ddesc_iso[i].status = -+ dwcep->desc_addr[i].status.b_iso_out.rxsts; -+ } -+ } -+ -+ DWC_SPINUNLOCK(ep->pcd->lock); -+ -+ /* Call the completion function in the non-portable logic */ -+ ep->pcd->fops->xisoc_complete(ep->pcd, ep->priv, req->priv, 0, -+ &req->ext_req); -+ -+ DWC_SPINLOCK(ep->pcd->lock); -+ -+ /* Free the request - specific freeing needed for extended request object */ -+ dwc_pcd_xiso_ereq_free(ep, req); -+ -+ /* Start the next request */ -+ dwc_otg_pcd_xiso_start_next_request(ep->pcd, ep); -+ -+ return; -+} -+ -+/** -+ * Create and initialize the Isoc pkt descriptors of the extended request. -+ * -+ */ -+static int dwc_otg_pcd_xiso_create_pkt_descs(dwc_otg_pcd_request_t * req, -+ void *ereq_nonport, -+ int atomic_alloc) -+{ -+ struct dwc_iso_xreq_port *ereq = NULL; -+ struct dwc_iso_xreq_port *req_mapped = NULL; -+ struct dwc_iso_pkt_desc_port *ipds = NULL; /* To be created in this function */ -+ uint32_t pkt_count; -+ int i; -+ -+ ereq = &req->ext_req; -+ req_mapped = (struct dwc_iso_xreq_port *)ereq_nonport; -+ pkt_count = req_mapped->pio_pkt_count; -+ -+ /* Create the isoc descs */ -+ if (atomic_alloc) { -+ ipds = DWC_ALLOC_ATOMIC(sizeof(*ipds) * pkt_count); -+ } else { -+ ipds = DWC_ALLOC(sizeof(*ipds) * pkt_count); -+ } -+ -+ if (!ipds) { -+ DWC_ERROR("Failed to allocate isoc descriptors"); -+ return -DWC_E_NO_MEMORY; -+ } -+ -+ /* Initialize the extended request fields */ -+ ereq->per_io_frame_descs = ipds; -+ ereq->error_count = 0; -+ ereq->pio_alloc_pkt_count = pkt_count; -+ ereq->pio_pkt_count = pkt_count; -+ ereq->tr_sub_flags = req_mapped->tr_sub_flags; -+ -+ /* Init the Isoc descriptors */ -+ for (i = 0; i < pkt_count; i++) { -+ ipds[i].length = req_mapped->per_io_frame_descs[i].length; -+ ipds[i].offset = req_mapped->per_io_frame_descs[i].offset; -+ ipds[i].status = req_mapped->per_io_frame_descs[i].status; /* 0 */ -+ ipds[i].actual_length = -+ req_mapped->per_io_frame_descs[i].actual_length; -+ } -+ -+ return 0; -+} -+ -+static void prn_ext_request(struct dwc_iso_xreq_port *ereq) -+{ -+ struct dwc_iso_pkt_desc_port *xfd = NULL; -+ int i; -+ -+ DWC_DEBUG("per_io_frame_descs=%p", ereq->per_io_frame_descs); -+ DWC_DEBUG("tr_sub_flags=%d", ereq->tr_sub_flags); -+ DWC_DEBUG("error_count=%d", ereq->error_count); -+ DWC_DEBUG("pio_alloc_pkt_count=%d", ereq->pio_alloc_pkt_count); -+ DWC_DEBUG("pio_pkt_count=%d", ereq->pio_pkt_count); -+ DWC_DEBUG("res=%d", ereq->res); -+ -+ for (i = 0; i < ereq->pio_pkt_count; i++) { -+ xfd = &ereq->per_io_frame_descs[0]; -+ DWC_DEBUG("FD #%d", i); -+ -+ DWC_DEBUG("xfd->actual_length=%d", xfd->actual_length); -+ DWC_DEBUG("xfd->length=%d", xfd->length); -+ DWC_DEBUG("xfd->offset=%d", xfd->offset); -+ DWC_DEBUG("xfd->status=%d", xfd->status); -+ } -+} -+ -+/** -+ * -+ */ -+int dwc_otg_pcd_xiso_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle, -+ uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen, -+ int zero, void *req_handle, int atomic_alloc, -+ void *ereq_nonport) -+{ -+ dwc_otg_pcd_request_t *req = NULL; -+ dwc_otg_pcd_ep_t *ep; -+ dwc_irqflags_t flags; -+ int res; -+ -+ ep = get_ep_from_handle(pcd, ep_handle); -+ if (!ep) { -+ DWC_WARN("bad ep\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ /* We support this extension only for DDMA mode */ -+ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) -+ if (!GET_CORE_IF(pcd)->dma_desc_enable) -+ return -DWC_E_INVALID; -+ -+ /* Create a dwc_otg_pcd_request_t object */ -+ if (atomic_alloc) { -+ req = DWC_ALLOC_ATOMIC(sizeof(*req)); -+ } else { -+ req = DWC_ALLOC(sizeof(*req)); -+ } -+ -+ if (!req) { -+ return -DWC_E_NO_MEMORY; -+ } -+ -+ /* Create the Isoc descs for this request which shall be the exact match -+ * of the structure sent to us from the non-portable logic */ -+ res = -+ dwc_otg_pcd_xiso_create_pkt_descs(req, ereq_nonport, atomic_alloc); -+ if (res) { -+ DWC_WARN("Failed to init the Isoc descriptors"); -+ DWC_FREE(req); -+ return res; -+ } -+ -+ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); -+ -+ DWC_CIRCLEQ_INIT_ENTRY(req, queue_entry); -+ req->buf = buf; -+ req->dma = dma_buf; -+ req->length = buflen; -+ req->sent_zlp = zero; -+ req->priv = req_handle; -+ -+ //DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); -+ ep->dwc_ep.dma_addr = dma_buf; -+ ep->dwc_ep.start_xfer_buff = buf; -+ ep->dwc_ep.xfer_buff = buf; -+ ep->dwc_ep.xfer_len = 0; -+ ep->dwc_ep.xfer_count = 0; -+ ep->dwc_ep.sent_zlp = 0; -+ ep->dwc_ep.total_len = buflen; -+ -+ /* Add this request to the tail */ -+ DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry); -+ ep->dwc_ep.xiso_queued_xfers++; -+ -+//DWC_DEBUG("CP_0"); -+//DWC_DEBUG("req->ext_req.tr_sub_flags=%d", req->ext_req.tr_sub_flags); -+//prn_ext_request((struct dwc_iso_xreq_port *) ereq_nonport); -+//prn_ext_request(&req->ext_req); -+ -+ //DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); -+ -+ /* If the req->status == ASAP then check if there is any active transfer -+ * for this endpoint. If no active transfers, then get the first entry -+ * from the queue and start that transfer -+ */ -+ if (req->ext_req.tr_sub_flags == DWC_EREQ_TF_ASAP) { -+ res = dwc_otg_pcd_xiso_start_next_request(pcd, ep); -+ if (res) { -+ DWC_WARN("Failed to start the next Isoc transfer"); -+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); -+ DWC_FREE(req); -+ return res; -+ } -+ } -+ -+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); -+ return 0; -+} -+ -+#endif -+/* END ifdef DWC_UTE_PER_IO ***************************************************/ -+int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle, -+ uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen, -+ int zero, void *req_handle, int atomic_alloc) -+{ -+ dwc_irqflags_t flags; -+ dwc_otg_pcd_request_t *req; -+ dwc_otg_pcd_ep_t *ep; -+ uint32_t max_transfer; -+ -+ ep = get_ep_from_handle(pcd, ep_handle); -+ if (!ep || (!ep->desc && ep->dwc_ep.num != 0)) { -+ DWC_WARN("bad ep\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ if (atomic_alloc) { -+ req = DWC_ALLOC_ATOMIC(sizeof(*req)); -+ } else { -+ req = DWC_ALLOC(sizeof(*req)); -+ } -+ -+ if (!req) { -+ return -DWC_E_NO_MEMORY; -+ } -+ DWC_CIRCLEQ_INIT_ENTRY(req, queue_entry); -+ if (!GET_CORE_IF(pcd)->core_params->opt) { -+ if (ep->dwc_ep.num != 0) { -+ DWC_ERROR("queue req %p, len %d buf %p\n", -+ req_handle, buflen, buf); -+ } -+ } -+ -+ req->buf = buf; -+ req->dma = dma_buf; -+ req->length = buflen; -+ req->sent_zlp = zero; -+ req->priv = req_handle; -+ req->dw_align_buf = NULL; -+ if ((dma_buf & 0x3) && GET_CORE_IF(pcd)->dma_enable -+ && !GET_CORE_IF(pcd)->dma_desc_enable) -+ req->dw_align_buf = DWC_DMA_ALLOC(buflen, -+ &req->dw_align_buf_dma); -+ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); -+ -+ /* -+ * After adding request to the queue for IN ISOC wait for In Token Received -+ * when TX FIFO is empty interrupt and for OUT ISOC wait for OUT Token -+ * Received when EP is disabled interrupt to obtain starting microframe -+ * (odd/even) start transfer -+ */ -+ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) { -+ if (req != 0) { -+ depctl_data_t depctl = {.d32 = -+ DWC_READ_REG32(&pcd->core_if->dev_if-> -+ in_ep_regs[ep->dwc_ep.num]-> -+ diepctl) }; -+ ++pcd->request_pending; -+ -+ DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry); -+ if (ep->dwc_ep.is_in) { -+ depctl.b.cnak = 1; -+ DWC_WRITE_REG32(&pcd->core_if->dev_if-> -+ in_ep_regs[ep->dwc_ep.num]-> -+ diepctl, depctl.d32); -+ } -+ -+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); -+ } -+ return 0; -+ } -+ -+ /* -+ * For EP0 IN without premature status, zlp is required? -+ */ -+ if (ep->dwc_ep.num == 0 && ep->dwc_ep.is_in) { -+ DWC_DEBUGPL(DBG_PCDV, "%d-OUT ZLP\n", ep->dwc_ep.num); -+ //_req->zero = 1; -+ } -+ -+ /* Start the transfer */ -+ if (DWC_CIRCLEQ_EMPTY(&ep->queue) && !ep->stopped) { -+ /* EP0 Transfer? */ -+ if (ep->dwc_ep.num == 0) { -+ switch (pcd->ep0state) { -+ case EP0_IN_DATA_PHASE: -+ DWC_DEBUGPL(DBG_PCD, -+ "%s ep0: EP0_IN_DATA_PHASE\n", -+ __func__); -+ break; -+ -+ case EP0_OUT_DATA_PHASE: -+ DWC_DEBUGPL(DBG_PCD, -+ "%s ep0: EP0_OUT_DATA_PHASE\n", -+ __func__); -+ if (pcd->request_config) { -+ /* Complete STATUS PHASE */ -+ ep->dwc_ep.is_in = 1; -+ pcd->ep0state = EP0_IN_STATUS_PHASE; -+ } -+ break; -+ -+ case EP0_IN_STATUS_PHASE: -+ DWC_DEBUGPL(DBG_PCD, -+ "%s ep0: EP0_IN_STATUS_PHASE\n", -+ __func__); -+ break; -+ -+ default: -+ DWC_DEBUGPL(DBG_ANY, "ep0: odd state %d\n", -+ pcd->ep0state); -+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); -+ return -DWC_E_SHUTDOWN; -+ } -+ -+ ep->dwc_ep.dma_addr = dma_buf; -+ ep->dwc_ep.start_xfer_buff = buf; -+ ep->dwc_ep.xfer_buff = buf; -+ ep->dwc_ep.xfer_len = buflen; -+ ep->dwc_ep.xfer_count = 0; -+ ep->dwc_ep.sent_zlp = 0; -+ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len; -+ -+ if (zero) { -+ if ((ep->dwc_ep.xfer_len % -+ ep->dwc_ep.maxpacket == 0) -+ && (ep->dwc_ep.xfer_len != 0)) { -+ ep->dwc_ep.sent_zlp = 1; -+ } -+ -+ } -+ -+ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), -+ &ep->dwc_ep); -+ } // non-ep0 endpoints -+ else { -+#ifdef DWC_UTE_CFI -+ if (ep->dwc_ep.buff_mode != BM_STANDARD) { -+ /* store the request length */ -+ ep->dwc_ep.cfi_req_len = buflen; -+ pcd->cfi->ops.build_descriptors(pcd->cfi, pcd, -+ ep, req); -+ } else { -+#endif -+ max_transfer = -+ GET_CORE_IF(ep->pcd)->core_params-> -+ max_transfer_size; -+ -+ /* Setup and start the Transfer */ -+ if (req->dw_align_buf){ -+ if (ep->dwc_ep.is_in) -+ dwc_memcpy(req->dw_align_buf, -+ buf, buflen); -+ ep->dwc_ep.dma_addr = -+ req->dw_align_buf_dma; -+ ep->dwc_ep.start_xfer_buff = -+ req->dw_align_buf; -+ ep->dwc_ep.xfer_buff = -+ req->dw_align_buf; -+ } else { -+ ep->dwc_ep.dma_addr = dma_buf; -+ ep->dwc_ep.start_xfer_buff = buf; -+ ep->dwc_ep.xfer_buff = buf; -+ } -+ ep->dwc_ep.xfer_len = 0; -+ ep->dwc_ep.xfer_count = 0; -+ ep->dwc_ep.sent_zlp = 0; -+ ep->dwc_ep.total_len = buflen; -+ -+ ep->dwc_ep.maxxfer = max_transfer; -+ if (GET_CORE_IF(pcd)->dma_desc_enable) { -+ uint32_t out_max_xfer = -+ DDMA_MAX_TRANSFER_SIZE - -+ (DDMA_MAX_TRANSFER_SIZE % 4); -+ if (ep->dwc_ep.is_in) { -+ if (ep->dwc_ep.maxxfer > -+ DDMA_MAX_TRANSFER_SIZE) { -+ ep->dwc_ep.maxxfer = -+ DDMA_MAX_TRANSFER_SIZE; -+ } -+ } else { -+ if (ep->dwc_ep.maxxfer > -+ out_max_xfer) { -+ ep->dwc_ep.maxxfer = -+ out_max_xfer; -+ } -+ } -+ } -+ if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) { -+ ep->dwc_ep.maxxfer -= -+ (ep->dwc_ep.maxxfer % -+ ep->dwc_ep.maxpacket); -+ } -+ -+ if (zero) { -+ if ((ep->dwc_ep.total_len % -+ ep->dwc_ep.maxpacket == 0) -+ && (ep->dwc_ep.total_len != 0)) { -+ ep->dwc_ep.sent_zlp = 1; -+ } -+ } -+#ifdef DWC_UTE_CFI -+ } -+#endif -+ dwc_otg_ep_start_transfer(GET_CORE_IF(pcd), -+ &ep->dwc_ep); -+ } -+ } -+ -+ if (req != 0) { -+ ++pcd->request_pending; -+ DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry); -+ if (ep->dwc_ep.is_in && ep->stopped -+ && !(GET_CORE_IF(pcd)->dma_enable)) { -+ /** @todo NGS Create a function for this. */ -+ diepmsk_data_t diepmsk = {.d32 = 0 }; -+ diepmsk.b.intktxfemp = 1; -+ if (GET_CORE_IF(pcd)->multiproc_int_enable) { -+ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)-> -+ dev_if->dev_global_regs->diepeachintmsk -+ [ep->dwc_ep.num], 0, -+ diepmsk.d32); -+ } else { -+ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)-> -+ dev_if->dev_global_regs-> -+ diepmsk, 0, diepmsk.d32); -+ } -+ -+ } -+ } -+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); -+ -+ return 0; -+} -+ -+int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle, -+ void *req_handle) -+{ -+ dwc_irqflags_t flags; -+ dwc_otg_pcd_request_t *req; -+ dwc_otg_pcd_ep_t *ep; -+ -+ ep = get_ep_from_handle(pcd, ep_handle); -+ if (!ep || (!ep->desc && ep->dwc_ep.num != 0)) { -+ DWC_WARN("bad argument\n"); -+ return -DWC_E_INVALID; -+ } -+ -+ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); -+ -+ /* make sure it's actually queued on this endpoint */ -+ DWC_CIRCLEQ_FOREACH(req, &ep->queue, queue_entry) { -+ if (req->priv == (void *)req_handle) { -+ break; -+ } -+ } -+ -+ if (req->priv != (void *)req_handle) { -+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); -+ return -DWC_E_INVALID; -+ } -+ -+ if (!DWC_CIRCLEQ_EMPTY_ENTRY(req, queue_entry)) { -+ dwc_otg_request_done(ep, req, -DWC_E_RESTART); -+ } else { -+ req = NULL; -+ } -+ -+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); -+ -+ return req ? 0 : -DWC_E_SHUTDOWN; -+ -+} -+ -+/** -+ * dwc_otg_pcd_ep_wedge - sets the halt feature and ignores clear requests -+ * -+ * Use this to stall an endpoint and ignore CLEAR_FEATURE(HALT_ENDPOINT) -+ * requests. If the gadget driver clears the halt status, it will -+ * automatically unwedge the endpoint. -+ * -+ * Returns zero on success, else negative DWC error code. -+ */ -+int dwc_otg_pcd_ep_wedge(dwc_otg_pcd_t * pcd, void *ep_handle) -+{ -+ dwc_otg_pcd_ep_t *ep; -+ dwc_irqflags_t flags; -+ int retval = 0; -+ -+ ep = get_ep_from_handle(pcd, ep_handle); -+ -+ if ((!ep->desc && ep != &pcd->ep0) || -+ (ep->desc && (ep->desc->bmAttributes == UE_ISOCHRONOUS))) { -+ DWC_WARN("%s, bad ep\n", __func__); -+ return -DWC_E_INVALID; -+ } -+ -+ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); -+ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) { -+ DWC_WARN("%d %s XFer In process\n", ep->dwc_ep.num, -+ ep->dwc_ep.is_in ? "IN" : "OUT"); -+ retval = -DWC_E_AGAIN; -+ } else { -+ /* This code needs to be reviewed */ -+ if (ep->dwc_ep.is_in == 1 && GET_CORE_IF(pcd)->dma_desc_enable) { -+ dtxfsts_data_t txstatus; -+ fifosize_data_t txfifosize; -+ -+ txfifosize.d32 = -+ DWC_READ_REG32(&GET_CORE_IF(pcd)-> -+ core_global_regs->dtxfsiz[ep->dwc_ep. -+ tx_fifo_num]); -+ txstatus.d32 = -+ DWC_READ_REG32(&GET_CORE_IF(pcd)-> -+ dev_if->in_ep_regs[ep->dwc_ep.num]-> -+ dtxfsts); -+ -+ if (txstatus.b.txfspcavail < txfifosize.b.depth) { -+ DWC_WARN("%s() Data In Tx Fifo\n", __func__); -+ retval = -DWC_E_AGAIN; -+ } else { -+ if (ep->dwc_ep.num == 0) { -+ pcd->ep0state = EP0_STALL; -+ } -+ -+ ep->stopped = 1; -+ dwc_otg_ep_set_stall(GET_CORE_IF(pcd), -+ &ep->dwc_ep); -+ } -+ } else { -+ if (ep->dwc_ep.num == 0) { -+ pcd->ep0state = EP0_STALL; -+ } -+ -+ ep->stopped = 1; -+ dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep->dwc_ep); -+ } -+ } -+ -+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); -+ -+ return retval; -+} -+ -+int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value) -+{ -+ dwc_otg_pcd_ep_t *ep; -+ dwc_irqflags_t flags; -+ int retval = 0; -+ -+ ep = get_ep_from_handle(pcd, ep_handle); -+ -+ if (!ep || (!ep->desc && ep != &pcd->ep0) || -+ (ep->desc && (ep->desc->bmAttributes == UE_ISOCHRONOUS))) { -+ DWC_WARN("%s, bad ep\n", __func__); -+ return -DWC_E_INVALID; -+ } -+ -+ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); -+ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) { -+ DWC_WARN("%d %s XFer In process\n", ep->dwc_ep.num, -+ ep->dwc_ep.is_in ? "IN" : "OUT"); -+ retval = -DWC_E_AGAIN; -+ } else if (value == 0) { -+ dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep); -+ } else if (value == 1) { -+ if (ep->dwc_ep.is_in == 1 && GET_CORE_IF(pcd)->dma_desc_enable) { -+ dtxfsts_data_t txstatus; -+ fifosize_data_t txfifosize; -+ -+ txfifosize.d32 = -+ DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs-> -+ dtxfsiz[ep->dwc_ep.tx_fifo_num]); -+ txstatus.d32 = -+ DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if-> -+ in_ep_regs[ep->dwc_ep.num]->dtxfsts); -+ -+ if (txstatus.b.txfspcavail < txfifosize.b.depth) { -+ DWC_WARN("%s() Data In Tx Fifo\n", __func__); -+ retval = -DWC_E_AGAIN; -+ } else { -+ if (ep->dwc_ep.num == 0) { -+ pcd->ep0state = EP0_STALL; -+ } -+ -+ ep->stopped = 1; -+ dwc_otg_ep_set_stall(GET_CORE_IF(pcd), -+ &ep->dwc_ep); -+ } -+ } else { -+ if (ep->dwc_ep.num == 0) { -+ pcd->ep0state = EP0_STALL; -+ } -+ -+ ep->stopped = 1; -+ dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep->dwc_ep); -+ } -+ } else if (value == 2) { -+ ep->dwc_ep.stall_clear_flag = 0; -+ } else if (value == 3) { -+ ep->dwc_ep.stall_clear_flag = 1; -+ } -+ -+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); -+ -+ return retval; -+} -+ -+/** -+ * This function initiates remote wakeup of the host from suspend state. -+ */ -+void dwc_otg_pcd_rem_wkup_from_suspend(dwc_otg_pcd_t * pcd, int set) -+{ -+ dctl_data_t dctl = { 0 }; -+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); -+ dsts_data_t dsts; -+ -+ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); -+ if (!dsts.b.suspsts) { -+ DWC_WARN("Remote wakeup while is not in suspend state\n"); -+ } -+ /* Check if DEVICE_REMOTE_WAKEUP feature enabled */ -+ if (pcd->remote_wakeup_enable) { -+ if (set) { -+ -+ if (core_if->adp_enable) { -+ gpwrdn_data_t gpwrdn; -+ -+ dwc_otg_adp_probe_stop(core_if); -+ -+ /* Mask SRP detected interrupt from Power Down Logic */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.srp_det_msk = 1; -+ DWC_MODIFY_REG32(&core_if-> -+ core_global_regs->gpwrdn, -+ gpwrdn.d32, 0); -+ -+ /* Disable Power Down Logic */ -+ gpwrdn.d32 = 0; -+ gpwrdn.b.pmuactv = 1; -+ DWC_MODIFY_REG32(&core_if-> -+ core_global_regs->gpwrdn, -+ gpwrdn.d32, 0); -+ -+ /* -+ * Initialize the Core for Device mode. -+ */ -+ core_if->op_state = B_PERIPHERAL; -+ dwc_otg_core_init(core_if); -+ dwc_otg_enable_global_interrupts(core_if); -+ cil_pcd_start(core_if); -+ -+ dwc_otg_initiate_srp(core_if); -+ } -+ -+ dctl.b.rmtwkupsig = 1; -+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> -+ dctl, 0, dctl.d32); -+ DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n"); -+ -+ dwc_mdelay(2); -+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> -+ dctl, dctl.d32, 0); -+ DWC_DEBUGPL(DBG_PCD, "Clear Remote Wakeup\n"); -+ } -+ } else { -+ DWC_DEBUGPL(DBG_PCD, "Remote Wakeup is disabled\n"); -+ } -+} -+ -+#ifdef CONFIG_USB_DWC_OTG_LPM -+/** -+ * This function initiates remote wakeup of the host from L1 sleep state. -+ */ -+void dwc_otg_pcd_rem_wkup_from_sleep(dwc_otg_pcd_t * pcd, int set) -+{ -+ glpmcfg_data_t lpmcfg; -+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); -+ -+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); -+ -+ /* Check if we are in L1 state */ -+ if (!lpmcfg.b.prt_sleep_sts) { -+ DWC_DEBUGPL(DBG_PCD, "Device is not in sleep state\n"); -+ return; -+ } -+ -+ /* Check if host allows remote wakeup */ -+ if (!lpmcfg.b.rem_wkup_en) { -+ DWC_DEBUGPL(DBG_PCD, "Host does not allow remote wakeup\n"); -+ return; -+ } -+ -+ /* Check if Resume OK */ -+ if (!lpmcfg.b.sleep_state_resumeok) { -+ DWC_DEBUGPL(DBG_PCD, "Sleep state resume is not OK\n"); -+ return; -+ } -+ -+ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); -+ lpmcfg.b.en_utmi_sleep = 0; -+ lpmcfg.b.hird_thres &= (~(1 << 4)); -+ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32); -+ -+ if (set) { -+ dctl_data_t dctl = {.d32 = 0 }; -+ dctl.b.rmtwkupsig = 1; -+ /* Set RmtWkUpSig bit to start remote wakup signaling. -+ * Hardware will automatically clear this bit. -+ */ -+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, -+ 0, dctl.d32); -+ DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n"); -+ } -+ -+} -+#endif -+ -+/** -+ * Performs remote wakeup. -+ */ -+void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set) -+{ -+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); -+ dwc_irqflags_t flags; -+ if (dwc_otg_is_device_mode(core_if)) { -+ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); -+#ifdef CONFIG_USB_DWC_OTG_LPM -+ if (core_if->lx_state == DWC_OTG_L1) { -+ dwc_otg_pcd_rem_wkup_from_sleep(pcd, set); -+ } else { -+#endif -+ dwc_otg_pcd_rem_wkup_from_suspend(pcd, set); -+#ifdef CONFIG_USB_DWC_OTG_LPM -+ } -+#endif -+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); -+ } -+ return; -+} -+ -+void dwc_otg_pcd_disconnect_us(dwc_otg_pcd_t * pcd, int no_of_usecs) -+{ -+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); -+ dctl_data_t dctl = { 0 }; -+ -+ if (dwc_otg_is_device_mode(core_if)) { -+ dctl.b.sftdiscon = 1; -+ DWC_PRINTF("Soft disconnect for %d useconds\n",no_of_usecs); -+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32); -+ dwc_udelay(no_of_usecs); -+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32,0); -+ -+ } else{ -+ DWC_PRINTF("NOT SUPPORTED IN HOST MODE\n"); -+ } -+ return; -+ -+} -+ -+int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd) -+{ -+ dsts_data_t dsts; -+ gotgctl_data_t gotgctl; -+ -+ /* -+ * This function starts the Protocol if no session is in progress. If -+ * a session is already in progress, but the device is suspended, -+ * remote wakeup signaling is started. -+ */ -+ -+ /* Check if valid session */ -+ gotgctl.d32 = -+ DWC_READ_REG32(&(GET_CORE_IF(pcd)->core_global_regs->gotgctl)); -+ if (gotgctl.b.bsesvld) { -+ /* Check if suspend state */ -+ dsts.d32 = -+ DWC_READ_REG32(& -+ (GET_CORE_IF(pcd)->dev_if-> -+ dev_global_regs->dsts)); -+ if (dsts.b.suspsts) { -+ dwc_otg_pcd_remote_wakeup(pcd, 1); -+ } -+ } else { -+ dwc_otg_pcd_initiate_srp(pcd); -+ } -+ -+ return 0; -+ -+} -+ -+/** -+ * Start the SRP timer to detect when the SRP does not complete within -+ * 6 seconds. -+ * -+ * @param pcd the pcd structure. -+ */ -+void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd) -+{ -+ dwc_irqflags_t flags; -+ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); -+ dwc_otg_initiate_srp(GET_CORE_IF(pcd)); -+ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); -+} -+ -+int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd) -+{ -+ return dwc_otg_get_frame_number(GET_CORE_IF(pcd)); -+} -+ -+int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd) -+{ -+ return GET_CORE_IF(pcd)->core_params->lpm_enable; -+} -+ -+uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd) -+{ -+ return pcd->b_hnp_enable; -+} -+ -+uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd) -+{ -+ return pcd->a_hnp_support; -+} -+ -+uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd) -+{ -+ return pcd->a_alt_hnp_support; -+} -+ -+int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd) -+{ -+ return pcd->remote_wakeup_enable; -+} -+ -+#endif /* DWC_HOST_ONLY */ -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_pcd.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd.h ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_pcd.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd.h 2015-11-29 09:42:39.923098428 +0100 -@@ -0,0 +1,266 @@ -+/* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.h $ -+ * $Revision: #48 $ -+ * $Date: 2012/08/10 $ -+ * $Change: 2047372 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+#ifndef DWC_HOST_ONLY -+#if !defined(__DWC_PCD_H__) -+#define __DWC_PCD_H__ -+ -+#include "dwc_otg_os_dep.h" -+#include "usb.h" -+#include "dwc_otg_cil.h" -+#include "dwc_otg_pcd_if.h" -+struct cfiobject; -+ -+/** -+ * @file -+ * -+ * This file contains the structures, constants, and interfaces for -+ * the Perpherial Contoller Driver (PCD). -+ * -+ * The Peripheral Controller Driver (PCD) for Linux will implement the -+ * Gadget API, so that the existing Gadget drivers can be used. For -+ * the Mass Storage Function driver the File-backed USB Storage Gadget -+ * (FBS) driver will be used. The FBS driver supports the -+ * Control-Bulk (CB), Control-Bulk-Interrupt (CBI), and Bulk-Only -+ * transports. -+ * -+ */ -+ -+/** Invalid DMA Address */ -+#define DWC_DMA_ADDR_INVALID (~(dwc_dma_t)0) -+ -+/** Max Transfer size for any EP */ -+#define DDMA_MAX_TRANSFER_SIZE 65535 -+ -+/** -+ * Get the pointer to the core_if from the pcd pointer. -+ */ -+#define GET_CORE_IF( _pcd ) (_pcd->core_if) -+ -+/** -+ * States of EP0. -+ */ -+typedef enum ep0_state { -+ EP0_DISCONNECT, /* no host */ -+ EP0_IDLE, -+ EP0_IN_DATA_PHASE, -+ EP0_OUT_DATA_PHASE, -+ EP0_IN_STATUS_PHASE, -+ EP0_OUT_STATUS_PHASE, -+ EP0_STALL, -+} ep0state_e; -+ -+/** Fordward declaration.*/ -+struct dwc_otg_pcd; -+ -+/** DWC_otg iso request structure. -+ * -+ */ -+typedef struct usb_iso_request dwc_otg_pcd_iso_request_t; -+ -+#ifdef DWC_UTE_PER_IO -+ -+/** -+ * This shall be the exact analogy of the same type structure defined in the -+ * usb_gadget.h. Each descriptor contains -+ */ -+struct dwc_iso_pkt_desc_port { -+ uint32_t offset; -+ uint32_t length; /* expected length */ -+ uint32_t actual_length; -+ uint32_t status; -+}; -+ -+struct dwc_iso_xreq_port { -+ /** transfer/submission flag */ -+ uint32_t tr_sub_flags; -+ /** Start the request ASAP */ -+#define DWC_EREQ_TF_ASAP 0x00000002 -+ /** Just enqueue the request w/o initiating a transfer */ -+#define DWC_EREQ_TF_ENQUEUE 0x00000004 -+ -+ /** -+ * count of ISO packets attached to this request - shall -+ * not exceed the pio_alloc_pkt_count -+ */ -+ uint32_t pio_pkt_count; -+ /** count of ISO packets allocated for this request */ -+ uint32_t pio_alloc_pkt_count; -+ /** number of ISO packet errors */ -+ uint32_t error_count; -+ /** reserved for future extension */ -+ uint32_t res; -+ /** Will be allocated and freed in the UTE gadget and based on the CFC value */ -+ struct dwc_iso_pkt_desc_port *per_io_frame_descs; -+}; -+#endif -+/** DWC_otg request structure. -+ * This structure is a list of requests. -+ */ -+typedef struct dwc_otg_pcd_request { -+ void *priv; -+ void *buf; -+ dwc_dma_t dma; -+ uint32_t length; -+ uint32_t actual; -+ unsigned sent_zlp:1; -+ /** -+ * Used instead of original buffer if -+ * it(physical address) is not dword-aligned. -+ **/ -+ uint8_t *dw_align_buf; -+ dwc_dma_t dw_align_buf_dma; -+ -+ DWC_CIRCLEQ_ENTRY(dwc_otg_pcd_request) queue_entry; -+#ifdef DWC_UTE_PER_IO -+ struct dwc_iso_xreq_port ext_req; -+ //void *priv_ereq_nport; /* */ -+#endif -+} dwc_otg_pcd_request_t; -+ -+DWC_CIRCLEQ_HEAD(req_list, dwc_otg_pcd_request); -+ -+/** PCD EP structure. -+ * This structure describes an EP, there is an array of EPs in the PCD -+ * structure. -+ */ -+typedef struct dwc_otg_pcd_ep { -+ /** USB EP Descriptor */ -+ const usb_endpoint_descriptor_t *desc; -+ -+ /** queue of dwc_otg_pcd_requests. */ -+ struct req_list queue; -+ unsigned stopped:1; -+ unsigned disabling:1; -+ unsigned dma:1; -+ unsigned queue_sof:1; -+ -+#ifdef DWC_EN_ISOC -+ /** ISOC req handle passed */ -+ void *iso_req_handle; -+#endif //_EN_ISOC_ -+ -+ /** DWC_otg ep data. */ -+ dwc_ep_t dwc_ep; -+ -+ /** Pointer to PCD */ -+ struct dwc_otg_pcd *pcd; -+ -+ void *priv; -+} dwc_otg_pcd_ep_t; -+ -+/** DWC_otg PCD Structure. -+ * This structure encapsulates the data for the dwc_otg PCD. -+ */ -+struct dwc_otg_pcd { -+ const struct dwc_otg_pcd_function_ops *fops; -+ /** The DWC otg device pointer */ -+ struct dwc_otg_device *otg_dev; -+ /** Core Interface */ -+ dwc_otg_core_if_t *core_if; -+ /** State of EP0 */ -+ ep0state_e ep0state; -+ /** EP0 Request is pending */ -+ unsigned ep0_pending:1; -+ /** Indicates when SET CONFIGURATION Request is in process */ -+ unsigned request_config:1; -+ /** The state of the Remote Wakeup Enable. */ -+ unsigned remote_wakeup_enable:1; -+ /** The state of the B-Device HNP Enable. */ -+ unsigned b_hnp_enable:1; -+ /** The state of A-Device HNP Support. */ -+ unsigned a_hnp_support:1; -+ /** The state of the A-Device Alt HNP support. */ -+ unsigned a_alt_hnp_support:1; -+ /** Count of pending Requests */ -+ unsigned request_pending; -+ -+ /** SETUP packet for EP0 -+ * This structure is allocated as a DMA buffer on PCD initialization -+ * with enough space for up to 3 setup packets. -+ */ -+ union { -+ usb_device_request_t req; -+ uint32_t d32[2]; -+ } *setup_pkt; -+ -+ dwc_dma_t setup_pkt_dma_handle; -+ -+ /* Additional buffer and flag for CTRL_WR premature case */ -+ uint8_t *backup_buf; -+ unsigned data_terminated; -+ -+ /** 2-byte dma buffer used to return status from GET_STATUS */ -+ uint16_t *status_buf; -+ dwc_dma_t status_buf_dma_handle; -+ -+ /** EP0 */ -+ dwc_otg_pcd_ep_t ep0; -+ -+ /** Array of IN EPs. */ -+ dwc_otg_pcd_ep_t in_ep[MAX_EPS_CHANNELS - 1]; -+ /** Array of OUT EPs. */ -+ dwc_otg_pcd_ep_t out_ep[MAX_EPS_CHANNELS - 1]; -+ /** number of valid EPs in the above array. */ -+// unsigned num_eps : 4; -+ dwc_spinlock_t *lock; -+ -+ /** Tasklet to defer starting of TEST mode transmissions until -+ * Status Phase has been completed. -+ */ -+ dwc_tasklet_t *test_mode_tasklet; -+ -+ /** Tasklet to delay starting of xfer in DMA mode */ -+ dwc_tasklet_t *start_xfer_tasklet; -+ -+ /** The test mode to enter when the tasklet is executed. */ -+ unsigned test_mode; -+ /** The cfi_api structure that implements most of the CFI API -+ * and OTG specific core configuration functionality -+ */ -+#ifdef DWC_UTE_CFI -+ struct cfiobject *cfi; -+#endif -+ -+}; -+ -+//FIXME this functions should be static, and this prototypes should be removed -+extern void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep); -+extern void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep, -+ dwc_otg_pcd_request_t * req, int32_t status); -+ -+void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep, -+ void *req_handle); -+ -+extern void do_test_mode(void *data); -+#endif -+#endif /* DWC_HOST_ONLY */ -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h 2015-11-29 09:42:39.923098428 +0100 -@@ -0,0 +1,360 @@ -+/* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_if.h $ -+ * $Revision: #11 $ -+ * $Date: 2011/10/26 $ -+ * $Change: 1873028 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+#ifndef DWC_HOST_ONLY -+ -+#if !defined(__DWC_PCD_IF_H__) -+#define __DWC_PCD_IF_H__ -+ -+//#include "dwc_os.h" -+#include "dwc_otg_core_if.h" -+ -+/** @file -+ * This file defines DWC_OTG PCD Core API. -+ */ -+ -+struct dwc_otg_pcd; -+typedef struct dwc_otg_pcd dwc_otg_pcd_t; -+ -+/** Maxpacket size for EP0 */ -+#define MAX_EP0_SIZE 64 -+/** Maxpacket size for any EP */ -+#define MAX_PACKET_SIZE 1024 -+ -+/** @name Function Driver Callbacks */ -+/** @{ */ -+ -+/** This function will be called whenever a previously queued request has -+ * completed. The status value will be set to -DWC_E_SHUTDOWN to indicated a -+ * failed or aborted transfer, or -DWC_E_RESTART to indicate the device was reset, -+ * or -DWC_E_TIMEOUT to indicate it timed out, or -DWC_E_INVALID to indicate invalid -+ * parameters. */ -+typedef int (*dwc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle, -+ void *req_handle, int32_t status, -+ uint32_t actual); -+/** -+ * This function will be called whenever a previousle queued ISOC request has -+ * completed. Count of ISOC packets could be read using dwc_otg_pcd_get_iso_packet_count -+ * function. -+ * The status of each ISOC packet could be read using dwc_otg_pcd_get_iso_packet_* -+ * functions. -+ */ -+typedef int (*dwc_isoc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle, -+ void *req_handle, int proc_buf_num); -+/** This function should handle any SETUP request that cannot be handled by the -+ * PCD Core. This includes most GET_DESCRIPTORs, SET_CONFIGS, Any -+ * class-specific requests, etc. The function must non-blocking. -+ * -+ * Returns 0 on success. -+ * Returns -DWC_E_NOT_SUPPORTED if the request is not supported. -+ * Returns -DWC_E_INVALID if the setup request had invalid parameters or bytes. -+ * Returns -DWC_E_SHUTDOWN on any other error. */ -+typedef int (*dwc_setup_cb_t) (dwc_otg_pcd_t * pcd, uint8_t * bytes); -+/** This is called whenever the device has been disconnected. The function -+ * driver should take appropriate action to clean up all pending requests in the -+ * PCD Core, remove all endpoints (except ep0), and initialize back to reset -+ * state. */ -+typedef int (*dwc_disconnect_cb_t) (dwc_otg_pcd_t * pcd); -+/** This function is called when device has been connected. */ -+typedef int (*dwc_connect_cb_t) (dwc_otg_pcd_t * pcd, int speed); -+/** This function is called when device has been suspended */ -+typedef int (*dwc_suspend_cb_t) (dwc_otg_pcd_t * pcd); -+/** This function is called when device has received LPM tokens, i.e. -+ * device has been sent to sleep state. */ -+typedef int (*dwc_sleep_cb_t) (dwc_otg_pcd_t * pcd); -+/** This function is called when device has been resumed -+ * from suspend(L2) or L1 sleep state. */ -+typedef int (*dwc_resume_cb_t) (dwc_otg_pcd_t * pcd); -+/** This function is called whenever hnp params has been changed. -+ * User can call get_b_hnp_enable, get_a_hnp_support, get_a_alt_hnp_support functions -+ * to get hnp parameters. */ -+typedef int (*dwc_hnp_params_changed_cb_t) (dwc_otg_pcd_t * pcd); -+/** This function is called whenever USB RESET is detected. */ -+typedef int (*dwc_reset_cb_t) (dwc_otg_pcd_t * pcd); -+ -+typedef int (*cfi_setup_cb_t) (dwc_otg_pcd_t * pcd, void *ctrl_req_bytes); -+ -+/** -+ * -+ * @param ep_handle Void pointer to the usb_ep structure -+ * @param ereq_port Pointer to the extended request structure created in the -+ * portable part. -+ */ -+typedef int (*xiso_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle, -+ void *req_handle, int32_t status, -+ void *ereq_port); -+/** Function Driver Ops Data Structure */ -+struct dwc_otg_pcd_function_ops { -+ dwc_connect_cb_t connect; -+ dwc_disconnect_cb_t disconnect; -+ dwc_setup_cb_t setup; -+ dwc_completion_cb_t complete; -+ dwc_isoc_completion_cb_t isoc_complete; -+ dwc_suspend_cb_t suspend; -+ dwc_sleep_cb_t sleep; -+ dwc_resume_cb_t resume; -+ dwc_reset_cb_t reset; -+ dwc_hnp_params_changed_cb_t hnp_changed; -+ cfi_setup_cb_t cfi_setup; -+#ifdef DWC_UTE_PER_IO -+ xiso_completion_cb_t xisoc_complete; -+#endif -+}; -+/** @} */ -+ -+/** @name Function Driver Functions */ -+/** @{ */ -+ -+/** Call this function to get pointer on dwc_otg_pcd_t, -+ * this pointer will be used for all PCD API functions. -+ * -+ * @param core_if The DWC_OTG Core -+ */ -+extern dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if); -+ -+/** Frees PCD allocated by dwc_otg_pcd_init -+ * -+ * @param pcd The PCD -+ */ -+extern void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd); -+ -+/** Call this to bind the function driver to the PCD Core. -+ * -+ * @param pcd Pointer on dwc_otg_pcd_t returned by dwc_otg_pcd_init function. -+ * @param fops The Function Driver Ops data structure containing pointers to all callbacks. -+ */ -+extern void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd, -+ const struct dwc_otg_pcd_function_ops *fops); -+ -+/** Enables an endpoint for use. This function enables an endpoint in -+ * the PCD. The endpoint is described by the ep_desc which has the -+ * same format as a USB ep descriptor. The ep_handle parameter is used to refer -+ * to the endpoint from other API functions and in callbacks. Normally this -+ * should be called after a SET_CONFIGURATION/SET_INTERFACE to configure the -+ * core for that interface. -+ * -+ * Returns -DWC_E_INVALID if invalid parameters were passed. -+ * Returns -DWC_E_SHUTDOWN if any other error ocurred. -+ * Returns 0 on success. -+ * -+ * @param pcd The PCD -+ * @param ep_desc Endpoint descriptor -+ * @param usb_ep Handle on endpoint, that will be used to identify endpoint. -+ */ -+extern int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd, -+ const uint8_t * ep_desc, void *usb_ep); -+ -+/** Disable the endpoint referenced by ep_handle. -+ * -+ * Returns -DWC_E_INVALID if invalid parameters were passed. -+ * Returns -DWC_E_SHUTDOWN if any other error occurred. -+ * Returns 0 on success. */ -+extern int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle); -+ -+/** Queue a data transfer request on the endpoint referenced by ep_handle. -+ * After the transfer is completes, the complete callback will be called with -+ * the request status. -+ * -+ * @param pcd The PCD -+ * @param ep_handle The handle of the endpoint -+ * @param buf The buffer for the data -+ * @param dma_buf The DMA buffer for the data -+ * @param buflen The length of the data transfer -+ * @param zero Specifies whether to send zero length last packet. -+ * @param req_handle Set this handle to any value to use to reference this -+ * request in the ep_dequeue function or from the complete callback -+ * @param atomic_alloc If driver need to perform atomic allocations -+ * for internal data structures. -+ * -+ * Returns -DWC_E_INVALID if invalid parameters were passed. -+ * Returns -DWC_E_SHUTDOWN if any other error ocurred. -+ * Returns 0 on success. */ -+extern int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle, -+ uint8_t * buf, dwc_dma_t dma_buf, -+ uint32_t buflen, int zero, void *req_handle, -+ int atomic_alloc); -+#ifdef DWC_UTE_PER_IO -+/** -+ * -+ * @param ereq_nonport Pointer to the extended request part of the -+ * usb_request structure defined in usb_gadget.h file. -+ */ -+extern int dwc_otg_pcd_xiso_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle, -+ uint8_t * buf, dwc_dma_t dma_buf, -+ uint32_t buflen, int zero, -+ void *req_handle, int atomic_alloc, -+ void *ereq_nonport); -+ -+#endif -+ -+/** De-queue the specified data transfer that has not yet completed. -+ * -+ * Returns -DWC_E_INVALID if invalid parameters were passed. -+ * Returns -DWC_E_SHUTDOWN if any other error ocurred. -+ * Returns 0 on success. */ -+extern int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle, -+ void *req_handle); -+ -+/** Halt (STALL) an endpoint or clear it. -+ * -+ * Returns -DWC_E_INVALID if invalid parameters were passed. -+ * Returns -DWC_E_SHUTDOWN if any other error ocurred. -+ * Returns -DWC_E_AGAIN if the STALL cannot be sent and must be tried again later -+ * Returns 0 on success. */ -+extern int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value); -+ -+/** This function */ -+extern int dwc_otg_pcd_ep_wedge(dwc_otg_pcd_t * pcd, void *ep_handle); -+ -+/** This function should be called on every hardware interrupt */ -+extern int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd); -+ -+/** This function returns current frame number */ -+extern int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd); -+ -+/** -+ * Start isochronous transfers on the endpoint referenced by ep_handle. -+ * For isochronous transfers duble buffering is used. -+ * After processing each of buffers comlete callback will be called with -+ * status for each transaction. -+ * -+ * @param pcd The PCD -+ * @param ep_handle The handle of the endpoint -+ * @param buf0 The virtual address of first data buffer -+ * @param buf1 The virtual address of second data buffer -+ * @param dma0 The DMA address of first data buffer -+ * @param dma1 The DMA address of second data buffer -+ * @param sync_frame Data pattern frame number -+ * @param dp_frame Data size for pattern frame -+ * @param data_per_frame Data size for regular frame -+ * @param start_frame Frame number to start transfers, if -1 then start transfers ASAP. -+ * @param buf_proc_intrvl Interval of ISOC Buffer processing -+ * @param req_handle Handle of ISOC request -+ * @param atomic_alloc Specefies whether to perform atomic allocation for -+ * internal data structures. -+ * -+ * Returns -DWC_E_NO_MEMORY if there is no enough memory. -+ * Returns -DWC_E_INVALID if incorrect arguments are passed to the function. -+ * Returns -DW_E_SHUTDOWN for any other error. -+ * Returns 0 on success -+ */ -+extern int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle, -+ uint8_t * buf0, uint8_t * buf1, -+ dwc_dma_t dma0, dwc_dma_t dma1, -+ int sync_frame, int dp_frame, -+ int data_per_frame, int start_frame, -+ int buf_proc_intrvl, void *req_handle, -+ int atomic_alloc); -+ -+/** Stop ISOC transfers on endpoint referenced by ep_handle. -+ * -+ * @param pcd The PCD -+ * @param ep_handle The handle of the endpoint -+ * @param req_handle Handle of ISOC request -+ * -+ * Returns -DWC_E_INVALID if incorrect arguments are passed to the function -+ * Returns 0 on success -+ */ -+int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle, -+ void *req_handle); -+ -+/** Get ISOC packet status. -+ * -+ * @param pcd The PCD -+ * @param ep_handle The handle of the endpoint -+ * @param iso_req_handle Isochronoush request handle -+ * @param packet Number of packet -+ * @param status Out parameter for returning status -+ * @param actual Out parameter for returning actual length -+ * @param offset Out parameter for returning offset -+ * -+ */ -+extern void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd, -+ void *ep_handle, -+ void *iso_req_handle, int packet, -+ int *status, int *actual, -+ int *offset); -+ -+/** Get ISOC packet count. -+ * -+ * @param pcd The PCD -+ * @param ep_handle The handle of the endpoint -+ * @param iso_req_handle -+ */ -+extern int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd, -+ void *ep_handle, -+ void *iso_req_handle); -+ -+/** This function starts the SRP Protocol if no session is in progress. If -+ * a session is already in progress, but the device is suspended, -+ * remote wakeup signaling is started. -+ */ -+extern int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd); -+ -+/** This function returns 1 if LPM support is enabled, and 0 otherwise. */ -+extern int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd); -+ -+/** This function returns 1 if remote wakeup is allowed and 0, otherwise. */ -+extern int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd); -+ -+/** Initiate SRP */ -+extern void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd); -+ -+/** Starts remote wakeup signaling. */ -+extern void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set); -+ -+/** Starts micorsecond soft disconnect. */ -+extern void dwc_otg_pcd_disconnect_us(dwc_otg_pcd_t * pcd, int no_of_usecs); -+/** This function returns whether device is dualspeed.*/ -+extern uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd); -+ -+/** This function returns whether device is otg. */ -+extern uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd); -+ -+/** These functions allow to get hnp parameters */ -+extern uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd); -+extern uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd); -+extern uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd); -+ -+/** CFI specific Interface functions */ -+/** Allocate a cfi buffer */ -+extern uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, -+ dwc_dma_t * addr, size_t buflen, -+ int flags); -+ -+/******************************************************************************/ -+ -+/** @} */ -+ -+#endif /* __DWC_PCD_IF_H__ */ -+ -+#endif /* DWC_HOST_ONLY */ -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c 2015-11-29 09:42:39.923098428 +0100 -@@ -0,0 +1,5147 @@ -+/* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_intr.c $ -+ * $Revision: #116 $ -+ * $Date: 2012/08/10 $ -+ * $Change: 2047372 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+#ifndef DWC_HOST_ONLY -+ -+#include "dwc_otg_pcd.h" -+ -+#ifdef DWC_UTE_CFI -+#include "dwc_otg_cfi.h" -+#endif -+ -+#ifdef DWC_UTE_PER_IO -+extern void complete_xiso_ep(dwc_otg_pcd_ep_t * ep); -+#endif -+//#define PRINT_CFI_DMA_DESCS -+ -+#define DEBUG_EP0 -+ -+/** -+ * This function updates OTG. -+ */ -+static void dwc_otg_pcd_update_otg(dwc_otg_pcd_t * pcd, const unsigned reset) -+{ -+ -+ if (reset) { -+ pcd->b_hnp_enable = 0; -+ pcd->a_hnp_support = 0; -+ pcd->a_alt_hnp_support = 0; -+ } -+ -+ if (pcd->fops->hnp_changed) { -+ pcd->fops->hnp_changed(pcd); -+ } -+} -+ -+/** @file -+ * This file contains the implementation of the PCD Interrupt handlers. -+ * -+ * The PCD handles the device interrupts. Many conditions can cause a -+ * device interrupt. When an interrupt occurs, the device interrupt -+ * service routine determines the cause of the interrupt and -+ * dispatches handling to the appropriate function. These interrupt -+ * handling functions are described below. -+ * All interrupt registers are processed from LSB to MSB. -+ */ -+ -+/** -+ * This function prints the ep0 state for debug purposes. -+ */ -+static inline void print_ep0_state(dwc_otg_pcd_t * pcd) -+{ -+#ifdef DEBUG -+ char str[40]; -+ -+ switch (pcd->ep0state) { -+ case EP0_DISCONNECT: -+ dwc_strcpy(str, "EP0_DISCONNECT"); -+ break; -+ case EP0_IDLE: -+ dwc_strcpy(str, "EP0_IDLE"); -+ break; -+ case EP0_IN_DATA_PHASE: -+ dwc_strcpy(str, "EP0_IN_DATA_PHASE"); -+ break; -+ case EP0_OUT_DATA_PHASE: -+ dwc_strcpy(str, "EP0_OUT_DATA_PHASE"); -+ break; -+ case EP0_IN_STATUS_PHASE: -+ dwc_strcpy(str, "EP0_IN_STATUS_PHASE"); -+ break; -+ case EP0_OUT_STATUS_PHASE: -+ dwc_strcpy(str, "EP0_OUT_STATUS_PHASE"); -+ break; -+ case EP0_STALL: -+ dwc_strcpy(str, "EP0_STALL"); -+ break; -+ default: -+ dwc_strcpy(str, "EP0_INVALID"); -+ } -+ -+ DWC_DEBUGPL(DBG_ANY, "%s(%d)\n", str, pcd->ep0state); -+#endif -+} -+ -+/** -+ * This function calculate the size of the payload in the memory -+ * for out endpoints and prints size for debug purposes(used in -+ * 2.93a DevOutNak feature). -+ */ -+static inline void print_memory_payload(dwc_otg_pcd_t * pcd, dwc_ep_t * ep) -+{ -+#ifdef DEBUG -+ deptsiz_data_t deptsiz_init = {.d32 = 0 }; -+ deptsiz_data_t deptsiz_updt = {.d32 = 0 }; -+ int pack_num; -+ unsigned payload; -+ -+ deptsiz_init.d32 = pcd->core_if->start_doeptsiz_val[ep->num]; -+ deptsiz_updt.d32 = -+ DWC_READ_REG32(&pcd->core_if->dev_if-> -+ out_ep_regs[ep->num]->doeptsiz); -+ /* Payload will be */ -+ payload = deptsiz_init.b.xfersize - deptsiz_updt.b.xfersize; -+ /* Packet count is decremented every time a packet -+ * is written to the RxFIFO not in to the external memory -+ * So, if payload == 0, then it means no packet was sent to ext memory*/ -+ pack_num = (!payload) ? 0 : (deptsiz_init.b.pktcnt - deptsiz_updt.b.pktcnt); -+ DWC_DEBUGPL(DBG_PCDV, -+ "Payload for EP%d-%s\n", -+ ep->num, (ep->is_in ? "IN" : "OUT")); -+ DWC_DEBUGPL(DBG_PCDV, -+ "Number of transfered bytes = 0x%08x\n", payload); -+ DWC_DEBUGPL(DBG_PCDV, -+ "Number of transfered packets = %d\n", pack_num); -+#endif -+} -+ -+ -+#ifdef DWC_UTE_CFI -+static inline void print_desc(struct dwc_otg_dma_desc *ddesc, -+ const uint8_t * epname, int descnum) -+{ -+ CFI_INFO -+ ("%s DMA_DESC(%d) buf=0x%08x bytes=0x%04x; sp=0x%x; l=0x%x; sts=0x%02x; bs=0x%02x\n", -+ epname, descnum, ddesc->buf, ddesc->status.b.bytes, -+ ddesc->status.b.sp, ddesc->status.b.l, ddesc->status.b.sts, -+ ddesc->status.b.bs); -+} -+#endif -+ -+/** -+ * This function returns pointer to in ep struct with number ep_num -+ */ -+static inline dwc_otg_pcd_ep_t *get_in_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num) -+{ -+ int i; -+ int num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps; -+ if (ep_num == 0) { -+ return &pcd->ep0; -+ } else { -+ for (i = 0; i < num_in_eps; ++i) { -+ if (pcd->in_ep[i].dwc_ep.num == ep_num) -+ return &pcd->in_ep[i]; -+ } -+ return 0; -+ } -+} -+ -+/** -+ * This function returns pointer to out ep struct with number ep_num -+ */ -+static inline dwc_otg_pcd_ep_t *get_out_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num) -+{ -+ int i; -+ int num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps; -+ if (ep_num == 0) { -+ return &pcd->ep0; -+ } else { -+ for (i = 0; i < num_out_eps; ++i) { -+ if (pcd->out_ep[i].dwc_ep.num == ep_num) -+ return &pcd->out_ep[i]; -+ } -+ return 0; -+ } -+} -+ -+/** -+ * This functions gets a pointer to an EP from the wIndex address -+ * value of the control request. -+ */ -+dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex) -+{ -+ dwc_otg_pcd_ep_t *ep; -+ uint32_t ep_num = UE_GET_ADDR(wIndex); -+ -+ if (ep_num == 0) { -+ ep = &pcd->ep0; -+ } else if (UE_GET_DIR(wIndex) == UE_DIR_IN) { /* in ep */ -+ ep = &pcd->in_ep[ep_num - 1]; -+ } else { -+ ep = &pcd->out_ep[ep_num - 1]; -+ } -+ -+ return ep; -+} -+ -+/** -+ * This function checks the EP request queue, if the queue is not -+ * empty the next request is started. -+ */ -+void start_next_request(dwc_otg_pcd_ep_t * ep) -+{ -+ dwc_otg_pcd_request_t *req = 0; -+ uint32_t max_transfer = -+ GET_CORE_IF(ep->pcd)->core_params->max_transfer_size; -+ -+#ifdef DWC_UTE_CFI -+ struct dwc_otg_pcd *pcd; -+ pcd = ep->pcd; -+#endif -+ -+ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) { -+ req = DWC_CIRCLEQ_FIRST(&ep->queue); -+ -+#ifdef DWC_UTE_CFI -+ if (ep->dwc_ep.buff_mode != BM_STANDARD) { -+ ep->dwc_ep.cfi_req_len = req->length; -+ pcd->cfi->ops.build_descriptors(pcd->cfi, pcd, ep, req); -+ } else { -+#endif -+ /* Setup and start the Transfer */ -+ if (req->dw_align_buf) { -+ ep->dwc_ep.dma_addr = req->dw_align_buf_dma; -+ ep->dwc_ep.start_xfer_buff = req->dw_align_buf; -+ ep->dwc_ep.xfer_buff = req->dw_align_buf; -+ } else { -+ ep->dwc_ep.dma_addr = req->dma; -+ ep->dwc_ep.start_xfer_buff = req->buf; -+ ep->dwc_ep.xfer_buff = req->buf; -+ } -+ ep->dwc_ep.sent_zlp = 0; -+ ep->dwc_ep.total_len = req->length; -+ ep->dwc_ep.xfer_len = 0; -+ ep->dwc_ep.xfer_count = 0; -+ -+ ep->dwc_ep.maxxfer = max_transfer; -+ if (GET_CORE_IF(ep->pcd)->dma_desc_enable) { -+ uint32_t out_max_xfer = DDMA_MAX_TRANSFER_SIZE -+ - (DDMA_MAX_TRANSFER_SIZE % 4); -+ if (ep->dwc_ep.is_in) { -+ if (ep->dwc_ep.maxxfer > -+ DDMA_MAX_TRANSFER_SIZE) { -+ ep->dwc_ep.maxxfer = -+ DDMA_MAX_TRANSFER_SIZE; -+ } -+ } else { -+ if (ep->dwc_ep.maxxfer > out_max_xfer) { -+ ep->dwc_ep.maxxfer = -+ out_max_xfer; -+ } -+ } -+ } -+ if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) { -+ ep->dwc_ep.maxxfer -= -+ (ep->dwc_ep.maxxfer % ep->dwc_ep.maxpacket); -+ } -+ if (req->sent_zlp) { -+ if ((ep->dwc_ep.total_len % -+ ep->dwc_ep.maxpacket == 0) -+ && (ep->dwc_ep.total_len != 0)) { -+ ep->dwc_ep.sent_zlp = 1; -+ } -+ -+ } -+#ifdef DWC_UTE_CFI -+ } -+#endif -+ dwc_otg_ep_start_transfer(GET_CORE_IF(ep->pcd), &ep->dwc_ep); -+ } else if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) { -+ DWC_PRINTF("There are no more ISOC requests \n"); -+ ep->dwc_ep.frame_num = 0xFFFFFFFF; -+ } -+} -+ -+/** -+ * This function handles the SOF Interrupts. At this time the SOF -+ * Interrupt is disabled. -+ */ -+int32_t dwc_otg_pcd_handle_sof_intr(dwc_otg_pcd_t * pcd) -+{ -+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); -+ -+ gintsts_data_t gintsts; -+ -+ DWC_DEBUGPL(DBG_PCD, "SOF\n"); -+ -+ /* Clear interrupt */ -+ gintsts.d32 = 0; -+ gintsts.b.sofintr = 1; -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); -+ -+ return 1; -+} -+ -+/** -+ * This function handles the Rx Status Queue Level Interrupt, which -+ * indicates that there is a least one packet in the Rx FIFO. The -+ * packets are moved from the FIFO to memory, where they will be -+ * processed when the Endpoint Interrupt Register indicates Transfer -+ * Complete or SETUP Phase Done. -+ * -+ * Repeat the following until the Rx Status Queue is empty: -+ * -# Read the Receive Status Pop Register (GRXSTSP) to get Packet -+ * info -+ * -# If Receive FIFO is empty then skip to step Clear the interrupt -+ * and exit -+ * -# If SETUP Packet call dwc_otg_read_setup_packet to copy the -+ * SETUP data to the buffer -+ * -# If OUT Data Packet call dwc_otg_read_packet to copy the data -+ * to the destination buffer -+ */ -+int32_t dwc_otg_pcd_handle_rx_status_q_level_intr(dwc_otg_pcd_t * pcd) -+{ -+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); -+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; -+ gintmsk_data_t gintmask = {.d32 = 0 }; -+ device_grxsts_data_t status; -+ dwc_otg_pcd_ep_t *ep; -+ gintsts_data_t gintsts; -+#ifdef DEBUG -+ static char *dpid_str[] = { "D0", "D2", "D1", "MDATA" }; -+#endif -+ -+ //DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _pcd); -+ /* Disable the Rx Status Queue Level interrupt */ -+ gintmask.b.rxstsqlvl = 1; -+ DWC_MODIFY_REG32(&global_regs->gintmsk, gintmask.d32, 0); -+ -+ /* Get the Status from the top of the FIFO */ -+ status.d32 = DWC_READ_REG32(&global_regs->grxstsp); -+ -+ DWC_DEBUGPL(DBG_PCD, "EP:%d BCnt:%d DPID:%s " -+ "pktsts:%x Frame:%d(0x%0x)\n", -+ status.b.epnum, status.b.bcnt, -+ dpid_str[status.b.dpid], -+ status.b.pktsts, status.b.fn, status.b.fn); -+ /* Get pointer to EP structure */ -+ ep = get_out_ep(pcd, status.b.epnum); -+ -+ switch (status.b.pktsts) { -+ case DWC_DSTS_GOUT_NAK: -+ DWC_DEBUGPL(DBG_PCDV, "Global OUT NAK\n"); -+ break; -+ case DWC_STS_DATA_UPDT: -+ DWC_DEBUGPL(DBG_PCDV, "OUT Data Packet\n"); -+ if (status.b.bcnt && ep->dwc_ep.xfer_buff) { -+ /** @todo NGS Check for buffer overflow? */ -+ dwc_otg_read_packet(core_if, -+ ep->dwc_ep.xfer_buff, -+ status.b.bcnt); -+ ep->dwc_ep.xfer_count += status.b.bcnt; -+ ep->dwc_ep.xfer_buff += status.b.bcnt; -+ } -+ break; -+ case DWC_STS_XFER_COMP: -+ DWC_DEBUGPL(DBG_PCDV, "OUT Complete\n"); -+ break; -+ case DWC_DSTS_SETUP_COMP: -+#ifdef DEBUG_EP0 -+ DWC_DEBUGPL(DBG_PCDV, "Setup Complete\n"); -+#endif -+ break; -+ case DWC_DSTS_SETUP_UPDT: -+ dwc_otg_read_setup_packet(core_if, pcd->setup_pkt->d32); -+#ifdef DEBUG_EP0 -+ DWC_DEBUGPL(DBG_PCD, -+ "SETUP PKT: %02x.%02x v%04x i%04x l%04x\n", -+ pcd->setup_pkt->req.bmRequestType, -+ pcd->setup_pkt->req.bRequest, -+ UGETW(pcd->setup_pkt->req.wValue), -+ UGETW(pcd->setup_pkt->req.wIndex), -+ UGETW(pcd->setup_pkt->req.wLength)); -+#endif -+ ep->dwc_ep.xfer_count += status.b.bcnt; -+ break; -+ default: -+ DWC_DEBUGPL(DBG_PCDV, "Invalid Packet Status (0x%0x)\n", -+ status.b.pktsts); -+ break; -+ } -+ -+ /* Enable the Rx Status Queue Level interrupt */ -+ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmask.d32); -+ /* Clear interrupt */ -+ gintsts.d32 = 0; -+ gintsts.b.rxstsqlvl = 1; -+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); -+ -+ //DWC_DEBUGPL(DBG_PCDV, "EXIT: %s\n", __func__); -+ return 1; -+} -+ -+/** -+ * This function examines the Device IN Token Learning Queue to -+ * determine the EP number of the last IN token received. This -+ * implementation is for the Mass Storage device where there are only -+ * 2 IN EPs (Control-IN and BULK-IN). -+ * -+ * The EP numbers for the first six IN Tokens are in DTKNQR1 and there -+ * are 8 EP Numbers in each of the other possible DTKNQ Registers. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ * -+ */ -+static inline int get_ep_of_last_in_token(dwc_otg_core_if_t * core_if) -+{ -+ dwc_otg_device_global_regs_t *dev_global_regs = -+ core_if->dev_if->dev_global_regs; -+ const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth; -+ /* Number of Token Queue Registers */ -+ const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8; -+ dtknq1_data_t dtknqr1; -+ uint32_t in_tkn_epnums[4]; -+ int ndx = 0; -+ int i = 0; -+ volatile uint32_t *addr = &dev_global_regs->dtknqr1; -+ int epnum = 0; -+ -+ //DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH); -+ -+ /* Read the DTKNQ Registers */ -+ for (i = 0; i < DTKNQ_REG_CNT; i++) { -+ in_tkn_epnums[i] = DWC_READ_REG32(addr); -+ DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i + 1, -+ in_tkn_epnums[i]); -+ if (addr == &dev_global_regs->dvbusdis) { -+ addr = &dev_global_regs->dtknqr3_dthrctl; -+ } else { -+ ++addr; -+ } -+ -+ } -+ -+ /* Copy the DTKNQR1 data to the bit field. */ -+ dtknqr1.d32 = in_tkn_epnums[0]; -+ /* Get the EP numbers */ -+ in_tkn_epnums[0] = dtknqr1.b.epnums0_5; -+ ndx = dtknqr1.b.intknwptr - 1; -+ -+ //DWC_DEBUGPL(DBG_PCDV,"ndx=%d\n",ndx); -+ if (ndx == -1) { -+ /** @todo Find a simpler way to calculate the max -+ * queue position.*/ -+ int cnt = TOKEN_Q_DEPTH; -+ if (TOKEN_Q_DEPTH <= 6) { -+ cnt = TOKEN_Q_DEPTH - 1; -+ } else if (TOKEN_Q_DEPTH <= 14) { -+ cnt = TOKEN_Q_DEPTH - 7; -+ } else if (TOKEN_Q_DEPTH <= 22) { -+ cnt = TOKEN_Q_DEPTH - 15; -+ } else { -+ cnt = TOKEN_Q_DEPTH - 23; -+ } -+ epnum = (in_tkn_epnums[DTKNQ_REG_CNT - 1] >> (cnt * 4)) & 0xF; -+ } else { -+ if (ndx <= 5) { -+ epnum = (in_tkn_epnums[0] >> (ndx * 4)) & 0xF; -+ } else if (ndx <= 13) { -+ ndx -= 6; -+ epnum = (in_tkn_epnums[1] >> (ndx * 4)) & 0xF; -+ } else if (ndx <= 21) { -+ ndx -= 14; -+ epnum = (in_tkn_epnums[2] >> (ndx * 4)) & 0xF; -+ } else if (ndx <= 29) { -+ ndx -= 22; -+ epnum = (in_tkn_epnums[3] >> (ndx * 4)) & 0xF; -+ } -+ } -+ //DWC_DEBUGPL(DBG_PCD,"epnum=%d\n",epnum); -+ return epnum; -+} -+ -+/** -+ * This interrupt occurs when the non-periodic Tx FIFO is half-empty. -+ * The active request is checked for the next packet to be loaded into -+ * the non-periodic Tx FIFO. -+ */ -+int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr(dwc_otg_pcd_t * pcd) -+{ -+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); -+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; -+ dwc_otg_dev_in_ep_regs_t *ep_regs; -+ gnptxsts_data_t txstatus = {.d32 = 0 }; -+ gintsts_data_t gintsts; -+ -+ int epnum = 0; -+ dwc_otg_pcd_ep_t *ep = 0; -+ uint32_t len = 0; -+ int dwords; -+ -+ /* Get the epnum from the IN Token Learning Queue. */ -+ epnum = get_ep_of_last_in_token(core_if); -+ ep = get_in_ep(pcd, epnum); -+ -+ DWC_DEBUGPL(DBG_PCD, "NP TxFifo Empty: %d \n", epnum); -+ -+ ep_regs = core_if->dev_if->in_ep_regs[epnum]; -+ -+ len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count; -+ if (len > ep->dwc_ep.maxpacket) { -+ len = ep->dwc_ep.maxpacket; -+ } -+ dwords = (len + 3) / 4; -+ -+ /* While there is space in the queue and space in the FIFO and -+ * More data to tranfer, Write packets to the Tx FIFO */ -+ txstatus.d32 = DWC_READ_REG32(&global_regs->gnptxsts); -+ DWC_DEBUGPL(DBG_PCDV, "b4 GNPTXSTS=0x%08x\n", txstatus.d32); -+ -+ while (txstatus.b.nptxqspcavail > 0 && -+ txstatus.b.nptxfspcavail > dwords && -+ ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len) { -+ /* Write the FIFO */ -+ dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0); -+ len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count; -+ -+ if (len > ep->dwc_ep.maxpacket) { -+ len = ep->dwc_ep.maxpacket; -+ } -+ -+ dwords = (len + 3) / 4; -+ txstatus.d32 = DWC_READ_REG32(&global_regs->gnptxsts); -+ DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n", txstatus.d32); -+ } -+ -+ DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n", -+ DWC_READ_REG32(&global_regs->gnptxsts)); -+ -+ /* Clear interrupt */ -+ gintsts.d32 = 0; -+ gintsts.b.nptxfempty = 1; -+ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); -+ -+ return 1; -+} -+ -+/** -+ * This function is called when dedicated Tx FIFO Empty interrupt occurs. -+ * The active request is checked for the next packet to be loaded into -+ * apropriate Tx FIFO. -+ */ -+static int32_t write_empty_tx_fifo(dwc_otg_pcd_t * pcd, uint32_t epnum) -+{ -+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); -+ dwc_otg_dev_if_t *dev_if = core_if->dev_if; -+ dwc_otg_dev_in_ep_regs_t *ep_regs; -+ dtxfsts_data_t txstatus = {.d32 = 0 }; -+ dwc_otg_pcd_ep_t *ep = 0; -+ uint32_t len = 0; -+ int dwords; -+ -+ ep = get_in_ep(pcd, epnum); -+ -+ DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum); -+ -+ ep_regs = core_if->dev_if->in_ep_regs[epnum]; -+ -+ len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count; -+ -+ if (len > ep->dwc_ep.maxpacket) { -+ len = ep->dwc_ep.maxpacket; -+ } -+ -+ dwords = (len + 3) / 4; -+ -+ /* While there is space in the queue and space in the FIFO and -+ * More data to tranfer, Write packets to the Tx FIFO */ -+ txstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts); -+ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32); -+ -+ while (txstatus.b.txfspcavail > dwords && -+ ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len && -+ ep->dwc_ep.xfer_len != 0) { -+ /* Write the FIFO */ -+ dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0); -+ -+ len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count; -+ if (len > ep->dwc_ep.maxpacket) { -+ len = ep->dwc_ep.maxpacket; -+ } -+ -+ dwords = (len + 3) / 4; -+ txstatus.d32 = -+ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts); -+ DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum, -+ txstatus.d32); -+ } -+ -+ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, -+ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts)); -+ -+ return 1; -+} -+ -+/** -+ * This function is called when the Device is disconnected. It stops -+ * any active requests and informs the Gadget driver of the -+ * disconnect. -+ */ -+void dwc_otg_pcd_stop(dwc_otg_pcd_t * pcd) -+{ -+ int i, num_in_eps, num_out_eps; -+ dwc_otg_pcd_ep_t *ep; -+ -+ gintmsk_data_t intr_mask = {.d32 = 0 }; -+ -+ DWC_SPINLOCK(pcd->lock); -+ -+ num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps; -+ num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps; -+ -+ DWC_DEBUGPL(DBG_PCDV, "%s() \n", __func__); -+ /* don't disconnect drivers more than once */ -+ if (pcd->ep0state == EP0_DISCONNECT) { -+ DWC_DEBUGPL(DBG_ANY, "%s() Already Disconnected\n", __func__); -+ DWC_SPINUNLOCK(pcd->lock); -+ return; -+ } -+ pcd->ep0state = EP0_DISCONNECT; -+ -+ /* Reset the OTG state. */ -+ dwc_otg_pcd_update_otg(pcd, 1); -+ -+ /* Disable the NP Tx Fifo Empty Interrupt. */ -+ intr_mask.b.nptxfempty = 1; -+ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, -+ intr_mask.d32, 0); -+ -+ /* Flush the FIFOs */ -+ /**@todo NGS Flush Periodic FIFOs */ -+ dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), 0x10); -+ dwc_otg_flush_rx_fifo(GET_CORE_IF(pcd)); -+ -+ /* prevent new request submissions, kill any outstanding requests */ -+ ep = &pcd->ep0; -+ dwc_otg_request_nuke(ep); -+ /* prevent new request submissions, kill any outstanding requests */ -+ for (i = 0; i < num_in_eps; i++) { -+ dwc_otg_pcd_ep_t *ep = &pcd->in_ep[i]; -+ dwc_otg_request_nuke(ep); -+ } -+ /* prevent new request submissions, kill any outstanding requests */ -+ for (i = 0; i < num_out_eps; i++) { -+ dwc_otg_pcd_ep_t *ep = &pcd->out_ep[i]; -+ dwc_otg_request_nuke(ep); -+ } -+ -+ /* report disconnect; the driver is already quiesced */ -+ if (pcd->fops->disconnect) { -+ DWC_SPINUNLOCK(pcd->lock); -+ pcd->fops->disconnect(pcd); -+ DWC_SPINLOCK(pcd->lock); -+ } -+ DWC_SPINUNLOCK(pcd->lock); -+} -+ -+/** -+ * This interrupt indicates that ... -+ */ -+int32_t dwc_otg_pcd_handle_i2c_intr(dwc_otg_pcd_t * pcd) -+{ -+ gintmsk_data_t intr_mask = {.d32 = 0 }; -+ gintsts_data_t gintsts; -+ -+ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "i2cintr"); -+ intr_mask.b.i2cintr = 1; -+ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, -+ intr_mask.d32, 0); -+ -+ /* Clear interrupt */ -+ gintsts.d32 = 0; -+ gintsts.b.i2cintr = 1; -+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, -+ gintsts.d32); -+ return 1; -+} -+ -+/** -+ * This interrupt indicates that ... -+ */ -+int32_t dwc_otg_pcd_handle_early_suspend_intr(dwc_otg_pcd_t * pcd) -+{ -+ gintsts_data_t gintsts; -+#if defined(VERBOSE) -+ DWC_PRINTF("Early Suspend Detected\n"); -+#endif -+ -+ /* Clear interrupt */ -+ gintsts.d32 = 0; -+ gintsts.b.erlysuspend = 1; -+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, -+ gintsts.d32); -+ return 1; -+} -+ -+/** -+ * This function configures EPO to receive SETUP packets. -+ * -+ * @todo NGS: Update the comments from the HW FS. -+ * -+ * -# Program the following fields in the endpoint specific registers -+ * for Control OUT EP 0, in order to receive a setup packet -+ * - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back -+ * setup packets) -+ * - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back -+ * to back setup packets) -+ * - In DMA mode, DOEPDMA0 Register with a memory address to -+ * store any setup packets received -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ * @param pcd Programming view of the PCD. -+ */ -+static inline void ep0_out_start(dwc_otg_core_if_t * core_if, -+ dwc_otg_pcd_t * pcd) -+{ -+ dwc_otg_dev_if_t *dev_if = core_if->dev_if; -+ deptsiz0_data_t doeptsize0 = {.d32 = 0 }; -+ dwc_otg_dev_dma_desc_t *dma_desc; -+ depctl_data_t doepctl = {.d32 = 0 }; -+ -+#ifdef VERBOSE -+ DWC_DEBUGPL(DBG_PCDV, "%s() doepctl0=%0x\n", __func__, -+ DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl)); -+#endif -+ if (core_if->snpsid >= OTG_CORE_REV_3_00a) { -+ doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl); -+ if (doepctl.b.epena) { -+ return; -+ } -+ } -+ -+ doeptsize0.b.supcnt = 3; -+ doeptsize0.b.pktcnt = 1; -+ doeptsize0.b.xfersize = 8 * 3; -+ -+ if (core_if->dma_enable) { -+ if (!core_if->dma_desc_enable) { -+ /** put here as for Hermes mode deptisz register should not be written */ -+ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doeptsiz, -+ doeptsize0.d32); -+ -+ /** @todo dma needs to handle multiple setup packets (up to 3) */ -+ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepdma, -+ pcd->setup_pkt_dma_handle); -+ } else { -+ dev_if->setup_desc_index = -+ (dev_if->setup_desc_index + 1) & 1; -+ dma_desc = -+ dev_if->setup_desc_addr[dev_if->setup_desc_index]; -+ -+ /** DMA Descriptor Setup */ -+ dma_desc->status.b.bs = BS_HOST_BUSY; -+ if (core_if->snpsid >= OTG_CORE_REV_3_00a) { -+ dma_desc->status.b.sr = 0; -+ dma_desc->status.b.mtrf = 0; -+ } -+ dma_desc->status.b.l = 1; -+ dma_desc->status.b.ioc = 1; -+ dma_desc->status.b.bytes = pcd->ep0.dwc_ep.maxpacket; -+ dma_desc->buf = pcd->setup_pkt_dma_handle; -+ dma_desc->status.b.sts = 0; -+ dma_desc->status.b.bs = BS_HOST_READY; -+ -+ /** DOEPDMA0 Register write */ -+ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepdma, -+ dev_if->dma_setup_desc_addr -+ [dev_if->setup_desc_index]); -+ } -+ -+ } else { -+ /** put here as for Hermes mode deptisz register should not be written */ -+ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doeptsiz, -+ doeptsize0.d32); -+ } -+ -+ /** DOEPCTL0 Register write cnak will be set after setup interrupt */ -+ doepctl.d32 = 0; -+ doepctl.b.epena = 1; -+ if (core_if->snpsid <= OTG_CORE_REV_2_94a) { -+ doepctl.b.cnak = 1; -+ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32); -+ } else { -+ DWC_MODIFY_REG32(&dev_if->out_ep_regs[0]->doepctl, 0, doepctl.d32); -+ } -+ -+#ifdef VERBOSE -+ DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n", -+ DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl)); -+ DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n", -+ DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl)); -+#endif -+} -+ -+/** -+ * This interrupt occurs when a USB Reset is detected. When the USB -+ * Reset Interrupt occurs the device state is set to DEFAULT and the -+ * EP0 state is set to IDLE. -+ * -# Set the NAK bit for all OUT endpoints (DOEPCTLn.SNAK = 1) -+ * -# Unmask the following interrupt bits -+ * - DAINTMSK.INEP0 = 1 (Control 0 IN endpoint) -+ * - DAINTMSK.OUTEP0 = 1 (Control 0 OUT endpoint) -+ * - DOEPMSK.SETUP = 1 -+ * - DOEPMSK.XferCompl = 1 -+ * - DIEPMSK.XferCompl = 1 -+ * - DIEPMSK.TimeOut = 1 -+ * -# Program the following fields in the endpoint specific registers -+ * for Control OUT EP 0, in order to receive a setup packet -+ * - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back -+ * setup packets) -+ * - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back -+ * to back setup packets) -+ * - In DMA mode, DOEPDMA0 Register with a memory address to -+ * store any setup packets received -+ * At this point, all the required initialization, except for enabling -+ * the control 0 OUT endpoint is done, for receiving SETUP packets. -+ */ -+int32_t dwc_otg_pcd_handle_usb_reset_intr(dwc_otg_pcd_t * pcd) -+{ -+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); -+ dwc_otg_dev_if_t *dev_if = core_if->dev_if; -+ depctl_data_t doepctl = {.d32 = 0 }; -+ depctl_data_t diepctl = {.d32 = 0 }; -+ daint_data_t daintmsk = {.d32 = 0 }; -+ doepmsk_data_t doepmsk = {.d32 = 0 }; -+ diepmsk_data_t diepmsk = {.d32 = 0 }; -+ dcfg_data_t dcfg = {.d32 = 0 }; -+ grstctl_t resetctl = {.d32 = 0 }; -+ dctl_data_t dctl = {.d32 = 0 }; -+ int i = 0; -+ gintsts_data_t gintsts; -+ pcgcctl_data_t power = {.d32 = 0 }; -+ -+ power.d32 = DWC_READ_REG32(core_if->pcgcctl); -+ if (power.b.stoppclk) { -+ power.d32 = 0; -+ power.b.stoppclk = 1; -+ DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0); -+ -+ power.b.pwrclmp = 1; -+ DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0); -+ -+ power.b.rstpdwnmodule = 1; -+ DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0); -+ } -+ -+ core_if->lx_state = DWC_OTG_L0; -+ -+ DWC_PRINTF("USB RESET\n"); -+#ifdef DWC_EN_ISOC -+ for (i = 1; i < 16; ++i) { -+ dwc_otg_pcd_ep_t *ep; -+ dwc_ep_t *dwc_ep; -+ ep = get_in_ep(pcd, i); -+ if (ep != 0) { -+ dwc_ep = &ep->dwc_ep; -+ dwc_ep->next_frame = 0xffffffff; -+ } -+ } -+#endif /* DWC_EN_ISOC */ -+ -+ /* reset the HNP settings */ -+ dwc_otg_pcd_update_otg(pcd, 1); -+ -+ /* Clear the Remote Wakeup Signalling */ -+ dctl.b.rmtwkupsig = 1; -+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0); -+ -+ /* Set NAK for all OUT EPs */ -+ doepctl.b.snak = 1; -+ for (i = 0; i <= dev_if->num_out_eps; i++) { -+ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32); -+ } -+ -+ /* Flush the NP Tx FIFO */ -+ dwc_otg_flush_tx_fifo(core_if, 0x10); -+ /* Flush the Learning Queue */ -+ resetctl.b.intknqflsh = 1; -+ DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32); -+ -+ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) { -+ core_if->start_predict = 0; -+ for (i = 0; i<= core_if->dev_if->num_in_eps; ++i) { -+ core_if->nextep_seq[i] = 0xff; // 0xff - EP not active -+ } -+ core_if->nextep_seq[0] = 0; -+ core_if->first_in_nextep_seq = 0; -+ diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl); -+ diepctl.b.nextep = 0; -+ DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32); -+ -+ /* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */ -+ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg); -+ dcfg.b.epmscnt = 2; -+ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32); -+ -+ DWC_DEBUGPL(DBG_PCDV, -+ "%s first_in_nextep_seq= %2d; nextep_seq[]:\n", -+ __func__, core_if->first_in_nextep_seq); -+ for (i=0; i <= core_if->dev_if->num_in_eps; i++) { -+ DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]); -+ } -+ } -+ -+ if (core_if->multiproc_int_enable) { -+ daintmsk.b.inep0 = 1; -+ daintmsk.b.outep0 = 1; -+ DWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk, -+ daintmsk.d32); -+ -+ doepmsk.b.setup = 1; -+ doepmsk.b.xfercompl = 1; -+ doepmsk.b.ahberr = 1; -+ doepmsk.b.epdisabled = 1; -+ -+ if ((core_if->dma_desc_enable) || -+ (core_if->dma_enable -+ && core_if->snpsid >= OTG_CORE_REV_3_00a)) { -+ doepmsk.b.stsphsercvd = 1; -+ } -+ if (core_if->dma_desc_enable) -+ doepmsk.b.bna = 1; -+/* -+ doepmsk.b.babble = 1; -+ doepmsk.b.nyet = 1; -+ -+ if (core_if->dma_enable) { -+ doepmsk.b.nak = 1; -+ } -+*/ -+ DWC_WRITE_REG32(&dev_if->dev_global_regs->doepeachintmsk[0], -+ doepmsk.d32); -+ -+ diepmsk.b.xfercompl = 1; -+ diepmsk.b.timeout = 1; -+ diepmsk.b.epdisabled = 1; -+ diepmsk.b.ahberr = 1; -+ diepmsk.b.intknepmis = 1; -+ if (!core_if->en_multiple_tx_fifo && core_if->dma_enable) -+ diepmsk.b.intknepmis = 0; -+ -+/* if (core_if->dma_desc_enable) { -+ diepmsk.b.bna = 1; -+ } -+*/ -+/* -+ if (core_if->dma_enable) { -+ diepmsk.b.nak = 1; -+ } -+*/ -+ DWC_WRITE_REG32(&dev_if->dev_global_regs->diepeachintmsk[0], -+ diepmsk.d32); -+ } else { -+ daintmsk.b.inep0 = 1; -+ daintmsk.b.outep0 = 1; -+ DWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk, -+ daintmsk.d32); -+ -+ doepmsk.b.setup = 1; -+ doepmsk.b.xfercompl = 1; -+ doepmsk.b.ahberr = 1; -+ doepmsk.b.epdisabled = 1; -+ -+ if ((core_if->dma_desc_enable) || -+ (core_if->dma_enable -+ && core_if->snpsid >= OTG_CORE_REV_3_00a)) { -+ doepmsk.b.stsphsercvd = 1; -+ } -+ if (core_if->dma_desc_enable) -+ doepmsk.b.bna = 1; -+ DWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, doepmsk.d32); -+ -+ diepmsk.b.xfercompl = 1; -+ diepmsk.b.timeout = 1; -+ diepmsk.b.epdisabled = 1; -+ diepmsk.b.ahberr = 1; -+ if (!core_if->en_multiple_tx_fifo && core_if->dma_enable) -+ diepmsk.b.intknepmis = 0; -+/* -+ if (core_if->dma_desc_enable) { -+ diepmsk.b.bna = 1; -+ } -+*/ -+ -+ DWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, diepmsk.d32); -+ } -+ -+ /* Reset Device Address */ -+ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg); -+ dcfg.b.devaddr = 0; -+ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32); -+ -+ /* setup EP0 to receive SETUP packets */ -+ if (core_if->snpsid <= OTG_CORE_REV_2_94a) -+ ep0_out_start(core_if, pcd); -+ -+ /* Clear interrupt */ -+ gintsts.d32 = 0; -+ gintsts.b.usbreset = 1; -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); -+ -+ return 1; -+} -+ -+/** -+ * Get the device speed from the device status register and convert it -+ * to USB speed constant. -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ */ -+static int get_device_speed(dwc_otg_core_if_t * core_if) -+{ -+ dsts_data_t dsts; -+ int speed = 0; -+ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); -+ -+ switch (dsts.b.enumspd) { -+ case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: -+ speed = USB_SPEED_HIGH; -+ break; -+ case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: -+ case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ: -+ speed = USB_SPEED_FULL; -+ break; -+ -+ case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ: -+ speed = USB_SPEED_LOW; -+ break; -+ } -+ -+ return speed; -+} -+ -+/** -+ * Read the device status register and set the device speed in the -+ * data structure. -+ * Set up EP0 to receive SETUP packets by calling dwc_ep0_activate. -+ */ -+int32_t dwc_otg_pcd_handle_enum_done_intr(dwc_otg_pcd_t * pcd) -+{ -+ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; -+ gintsts_data_t gintsts; -+ gusbcfg_data_t gusbcfg; -+ dwc_otg_core_global_regs_t *global_regs = -+ GET_CORE_IF(pcd)->core_global_regs; -+ uint8_t utmi16b, utmi8b; -+ int speed; -+ DWC_DEBUGPL(DBG_PCD, "SPEED ENUM\n"); -+ -+ if (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_2_60a) { -+ utmi16b = 6; //vahrama old value was 6; -+ utmi8b = 9; -+ } else { -+ utmi16b = 4; -+ utmi8b = 8; -+ } -+ dwc_otg_ep0_activate(GET_CORE_IF(pcd), &ep0->dwc_ep); -+ if (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_3_00a) { -+ ep0_out_start(GET_CORE_IF(pcd), pcd); -+ } -+ -+#ifdef DEBUG_EP0 -+ print_ep0_state(pcd); -+#endif -+ -+ if (pcd->ep0state == EP0_DISCONNECT) { -+ pcd->ep0state = EP0_IDLE; -+ } else if (pcd->ep0state == EP0_STALL) { -+ pcd->ep0state = EP0_IDLE; -+ } -+ -+ pcd->ep0state = EP0_IDLE; -+ -+ ep0->stopped = 0; -+ -+ speed = get_device_speed(GET_CORE_IF(pcd)); -+ pcd->fops->connect(pcd, speed); -+ -+ /* Set USB turnaround time based on device speed and PHY interface. */ -+ gusbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg); -+ if (speed == USB_SPEED_HIGH) { -+ if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == -+ DWC_HWCFG2_HS_PHY_TYPE_ULPI) { -+ /* ULPI interface */ -+ gusbcfg.b.usbtrdtim = 9; -+ } -+ if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == -+ DWC_HWCFG2_HS_PHY_TYPE_UTMI) { -+ /* UTMI+ interface */ -+ if (GET_CORE_IF(pcd)->hwcfg4.b.utmi_phy_data_width == 0) { -+ gusbcfg.b.usbtrdtim = utmi8b; -+ } else if (GET_CORE_IF(pcd)->hwcfg4. -+ b.utmi_phy_data_width == 1) { -+ gusbcfg.b.usbtrdtim = utmi16b; -+ } else if (GET_CORE_IF(pcd)-> -+ core_params->phy_utmi_width == 8) { -+ gusbcfg.b.usbtrdtim = utmi8b; -+ } else { -+ gusbcfg.b.usbtrdtim = utmi16b; -+ } -+ } -+ if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == -+ DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI) { -+ /* UTMI+ OR ULPI interface */ -+ if (gusbcfg.b.ulpi_utmi_sel == 1) { -+ /* ULPI interface */ -+ gusbcfg.b.usbtrdtim = 9; -+ } else { -+ /* UTMI+ interface */ -+ if (GET_CORE_IF(pcd)-> -+ core_params->phy_utmi_width == 16) { -+ gusbcfg.b.usbtrdtim = utmi16b; -+ } else { -+ gusbcfg.b.usbtrdtim = utmi8b; -+ } -+ } -+ } -+ } else { -+ /* Full or low speed */ -+ gusbcfg.b.usbtrdtim = 9; -+ } -+ DWC_WRITE_REG32(&global_regs->gusbcfg, gusbcfg.d32); -+ -+ /* Clear interrupt */ -+ gintsts.d32 = 0; -+ gintsts.b.enumdone = 1; -+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, -+ gintsts.d32); -+ return 1; -+} -+ -+/** -+ * This interrupt indicates that the ISO OUT Packet was dropped due to -+ * Rx FIFO full or Rx Status Queue Full. If this interrupt occurs -+ * read all the data from the Rx FIFO. -+ */ -+int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr(dwc_otg_pcd_t * pcd) -+{ -+ gintmsk_data_t intr_mask = {.d32 = 0 }; -+ gintsts_data_t gintsts; -+ -+ DWC_WARN("INTERRUPT Handler not implemented for %s\n", -+ "ISOC Out Dropped"); -+ -+ intr_mask.b.isooutdrop = 1; -+ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, -+ intr_mask.d32, 0); -+ -+ /* Clear interrupt */ -+ gintsts.d32 = 0; -+ gintsts.b.isooutdrop = 1; -+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, -+ gintsts.d32); -+ -+ return 1; -+} -+ -+/** -+ * This interrupt indicates the end of the portion of the micro-frame -+ * for periodic transactions. If there is a periodic transaction for -+ * the next frame, load the packets into the EP periodic Tx FIFO. -+ */ -+int32_t dwc_otg_pcd_handle_end_periodic_frame_intr(dwc_otg_pcd_t * pcd) -+{ -+ gintmsk_data_t intr_mask = {.d32 = 0 }; -+ gintsts_data_t gintsts; -+ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "EOP"); -+ -+ intr_mask.b.eopframe = 1; -+ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, -+ intr_mask.d32, 0); -+ -+ /* Clear interrupt */ -+ gintsts.d32 = 0; -+ gintsts.b.eopframe = 1; -+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, -+ gintsts.d32); -+ -+ return 1; -+} -+ -+/** -+ * This interrupt indicates that EP of the packet on the top of the -+ * non-periodic Tx FIFO does not match EP of the IN Token received. -+ * -+ * The "Device IN Token Queue" Registers are read to determine the -+ * order the IN Tokens have been received. The non-periodic Tx FIFO -+ * is flushed, so it can be reloaded in the order seen in the IN Token -+ * Queue. -+ */ -+int32_t dwc_otg_pcd_handle_ep_mismatch_intr(dwc_otg_pcd_t * pcd) -+{ -+ gintsts_data_t gintsts; -+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); -+ dctl_data_t dctl; -+ gintmsk_data_t intr_mask = {.d32 = 0 }; -+ -+ if (!core_if->en_multiple_tx_fifo && core_if->dma_enable) { -+ core_if->start_predict = 1; -+ -+ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if); -+ -+ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts); -+ if (!gintsts.b.ginnakeff) { -+ /* Disable EP Mismatch interrupt */ -+ intr_mask.d32 = 0; -+ intr_mask.b.epmismatch = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, intr_mask.d32, 0); -+ /* Enable the Global IN NAK Effective Interrupt */ -+ intr_mask.d32 = 0; -+ intr_mask.b.ginnakeff = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32); -+ /* Set the global non-periodic IN NAK handshake */ -+ dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl); -+ dctl.b.sgnpinnak = 1; -+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32); -+ } else { -+ DWC_PRINTF("gintsts.b.ginnakeff = 1! dctl.b.sgnpinnak not set\n"); -+ } -+ /* Disabling of all EP's will be done in dwc_otg_pcd_handle_in_nak_effective() -+ * handler after Global IN NAK Effective interrupt will be asserted */ -+ } -+ /* Clear interrupt */ -+ gintsts.d32 = 0; -+ gintsts.b.epmismatch = 1; -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); -+ -+ return 1; -+} -+ -+/** -+ * This interrupt is valid only in DMA mode. This interrupt indicates that the -+ * core has stopped fetching data for IN endpoints due to the unavailability of -+ * TxFIFO space or Request Queue space. This interrupt is used by the -+ * application for an endpoint mismatch algorithm. -+ * -+ * @param pcd The PCD -+ */ -+int32_t dwc_otg_pcd_handle_ep_fetsusp_intr(dwc_otg_pcd_t * pcd) -+{ -+ gintsts_data_t gintsts; -+ gintmsk_data_t gintmsk_data; -+ dctl_data_t dctl; -+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); -+ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if); -+ -+ /* Clear the global non-periodic IN NAK handshake */ -+ dctl.d32 = 0; -+ dctl.b.cgnpinnak = 1; -+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); -+ -+ /* Mask GINTSTS.FETSUSP interrupt */ -+ gintmsk_data.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk); -+ gintmsk_data.b.fetsusp = 0; -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk_data.d32); -+ -+ /* Clear interrupt */ -+ gintsts.d32 = 0; -+ gintsts.b.fetsusp = 1; -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); -+ -+ return 1; -+} -+/** -+ * This funcion stalls EP0. -+ */ -+static inline void ep0_do_stall(dwc_otg_pcd_t * pcd, const int err_val) -+{ -+ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; -+ usb_device_request_t *ctrl = &pcd->setup_pkt->req; -+ DWC_WARN("req %02x.%02x protocol STALL; err %d\n", -+ ctrl->bmRequestType, ctrl->bRequest, err_val); -+ -+ ep0->dwc_ep.is_in = 1; -+ dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep0->dwc_ep); -+ pcd->ep0.stopped = 1; -+ pcd->ep0state = EP0_IDLE; -+ ep0_out_start(GET_CORE_IF(pcd), pcd); -+} -+ -+/** -+ * This functions delegates the setup command to the gadget driver. -+ */ -+static inline void do_gadget_setup(dwc_otg_pcd_t * pcd, -+ usb_device_request_t * ctrl) -+{ -+ int ret = 0; -+ DWC_SPINUNLOCK(pcd->lock); -+ ret = pcd->fops->setup(pcd, (uint8_t *) ctrl); -+ DWC_SPINLOCK(pcd->lock); -+ if (ret < 0) { -+ ep0_do_stall(pcd, ret); -+ } -+ -+ /** @todo This is a g_file_storage gadget driver specific -+ * workaround: a DELAYED_STATUS result from the fsg_setup -+ * routine will result in the gadget queueing a EP0 IN status -+ * phase for a two-stage control transfer. Exactly the same as -+ * a SET_CONFIGURATION/SET_INTERFACE except that this is a class -+ * specific request. Need a generic way to know when the gadget -+ * driver will queue the status phase. Can we assume when we -+ * call the gadget driver setup() function that it will always -+ * queue and require the following flag? Need to look into -+ * this. -+ */ -+ -+ if (ret == 256 + 999) { -+ pcd->request_config = 1; -+ } -+} -+ -+#ifdef DWC_UTE_CFI -+/** -+ * This functions delegates the CFI setup commands to the gadget driver. -+ * This function will return a negative value to indicate a failure. -+ */ -+static inline int cfi_gadget_setup(dwc_otg_pcd_t * pcd, -+ struct cfi_usb_ctrlrequest *ctrl_req) -+{ -+ int ret = 0; -+ -+ if (pcd->fops && pcd->fops->cfi_setup) { -+ DWC_SPINUNLOCK(pcd->lock); -+ ret = pcd->fops->cfi_setup(pcd, ctrl_req); -+ DWC_SPINLOCK(pcd->lock); -+ if (ret < 0) { -+ ep0_do_stall(pcd, ret); -+ return ret; -+ } -+ } -+ -+ return ret; -+} -+#endif -+ -+/** -+ * This function starts the Zero-Length Packet for the IN status phase -+ * of a 2 stage control transfer. -+ */ -+static inline void do_setup_in_status_phase(dwc_otg_pcd_t * pcd) -+{ -+ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; -+ if (pcd->ep0state == EP0_STALL) { -+ return; -+ } -+ -+ pcd->ep0state = EP0_IN_STATUS_PHASE; -+ -+ /* Prepare for more SETUP Packets */ -+ DWC_DEBUGPL(DBG_PCD, "EP0 IN ZLP\n"); -+ if ((GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_3_00a) -+ && (pcd->core_if->dma_desc_enable) -+ && (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len)) { -+ DWC_DEBUGPL(DBG_PCDV, -+ "Data terminated wait next packet in out_desc_addr\n"); -+ pcd->backup_buf = phys_to_virt(ep0->dwc_ep.dma_addr); -+ pcd->data_terminated = 1; -+ } -+ ep0->dwc_ep.xfer_len = 0; -+ ep0->dwc_ep.xfer_count = 0; -+ ep0->dwc_ep.is_in = 1; -+ ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle; -+ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep); -+ -+ /* Prepare for more SETUP Packets */ -+ //ep0_out_start(GET_CORE_IF(pcd), pcd); -+} -+ -+/** -+ * This function starts the Zero-Length Packet for the OUT status phase -+ * of a 2 stage control transfer. -+ */ -+static inline void do_setup_out_status_phase(dwc_otg_pcd_t * pcd) -+{ -+ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; -+ if (pcd->ep0state == EP0_STALL) { -+ DWC_DEBUGPL(DBG_PCD, "EP0 STALLED\n"); -+ return; -+ } -+ pcd->ep0state = EP0_OUT_STATUS_PHASE; -+ -+ DWC_DEBUGPL(DBG_PCD, "EP0 OUT ZLP\n"); -+ ep0->dwc_ep.xfer_len = 0; -+ ep0->dwc_ep.xfer_count = 0; -+ ep0->dwc_ep.is_in = 0; -+ ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle; -+ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep); -+ -+ /* Prepare for more SETUP Packets */ -+ if (GET_CORE_IF(pcd)->dma_enable == 0) { -+ ep0_out_start(GET_CORE_IF(pcd), pcd); -+ } -+} -+ -+/** -+ * Clear the EP halt (STALL) and if pending requests start the -+ * transfer. -+ */ -+static inline void pcd_clear_halt(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep) -+{ -+ if (ep->dwc_ep.stall_clear_flag == 0) -+ dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep); -+ -+ /* Reactive the EP */ -+ dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep); -+ if (ep->stopped) { -+ ep->stopped = 0; -+ /* If there is a request in the EP queue start it */ -+ -+ /** @todo FIXME: this causes an EP mismatch in DMA mode. -+ * epmismatch not yet implemented. */ -+ -+ /* -+ * Above fixme is solved by implmenting a tasklet to call the -+ * start_next_request(), outside of interrupt context at some -+ * time after the current time, after a clear-halt setup packet. -+ * Still need to implement ep mismatch in the future if a gadget -+ * ever uses more than one endpoint at once -+ */ -+ ep->queue_sof = 1; -+ DWC_TASK_SCHEDULE(pcd->start_xfer_tasklet); -+ } -+ /* Start Control Status Phase */ -+ do_setup_in_status_phase(pcd); -+} -+ -+/** -+ * This function is called when the SET_FEATURE TEST_MODE Setup packet -+ * is sent from the host. The Device Control register is written with -+ * the Test Mode bits set to the specified Test Mode. This is done as -+ * a tasklet so that the "Status" phase of the control transfer -+ * completes before transmitting the TEST packets. -+ * -+ * @todo This has not been tested since the tasklet struct was put -+ * into the PCD struct! -+ * -+ */ -+void do_test_mode(void *data) -+{ -+ dctl_data_t dctl; -+ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data; -+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); -+ int test_mode = pcd->test_mode; -+ -+// DWC_WARN("%s() has not been tested since being rewritten!\n", __func__); -+ -+ dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl); -+ switch (test_mode) { -+ case 1: // TEST_J -+ dctl.b.tstctl = 1; -+ break; -+ -+ case 2: // TEST_K -+ dctl.b.tstctl = 2; -+ break; -+ -+ case 3: // TEST_SE0_NAK -+ dctl.b.tstctl = 3; -+ break; -+ -+ case 4: // TEST_PACKET -+ dctl.b.tstctl = 4; -+ break; -+ -+ case 5: // TEST_FORCE_ENABLE -+ dctl.b.tstctl = 5; -+ break; -+ } -+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32); -+} -+ -+/** -+ * This function process the GET_STATUS Setup Commands. -+ */ -+static inline void do_get_status(dwc_otg_pcd_t * pcd) -+{ -+ usb_device_request_t ctrl = pcd->setup_pkt->req; -+ dwc_otg_pcd_ep_t *ep; -+ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; -+ uint16_t *status = pcd->status_buf; -+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); -+ -+#ifdef DEBUG_EP0 -+ DWC_DEBUGPL(DBG_PCD, -+ "GET_STATUS %02x.%02x v%04x i%04x l%04x\n", -+ ctrl.bmRequestType, ctrl.bRequest, -+ UGETW(ctrl.wValue), UGETW(ctrl.wIndex), -+ UGETW(ctrl.wLength)); -+#endif -+ -+ switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) { -+ case UT_DEVICE: -+ if(UGETW(ctrl.wIndex) == 0xF000) { /* OTG Status selector */ -+ DWC_PRINTF("wIndex - %d\n", UGETW(ctrl.wIndex)); -+ DWC_PRINTF("OTG VERSION - %d\n", core_if->otg_ver); -+ DWC_PRINTF("OTG CAP - %d, %d\n", -+ core_if->core_params->otg_cap, -+ DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE); -+ if (core_if->otg_ver == 1 -+ && core_if->core_params->otg_cap == -+ DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) { -+ uint8_t *otgsts = (uint8_t*)pcd->status_buf; -+ *otgsts = (core_if->otg_sts & 0x1); -+ pcd->ep0_pending = 1; -+ ep0->dwc_ep.start_xfer_buff = -+ (uint8_t *) otgsts; -+ ep0->dwc_ep.xfer_buff = (uint8_t *) otgsts; -+ ep0->dwc_ep.dma_addr = -+ pcd->status_buf_dma_handle; -+ ep0->dwc_ep.xfer_len = 1; -+ ep0->dwc_ep.xfer_count = 0; -+ ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len; -+ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), -+ &ep0->dwc_ep); -+ return; -+ } else { -+ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); -+ return; -+ } -+ break; -+ } else { -+ *status = 0x1; /* Self powered */ -+ *status |= pcd->remote_wakeup_enable << 1; -+ break; -+ } -+ case UT_INTERFACE: -+ *status = 0; -+ break; -+ -+ case UT_ENDPOINT: -+ ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex)); -+ if (ep == 0 || UGETW(ctrl.wLength) > 2) { -+ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); -+ return; -+ } -+ /** @todo check for EP stall */ -+ *status = ep->stopped; -+ break; -+ } -+ pcd->ep0_pending = 1; -+ ep0->dwc_ep.start_xfer_buff = (uint8_t *) status; -+ ep0->dwc_ep.xfer_buff = (uint8_t *) status; -+ ep0->dwc_ep.dma_addr = pcd->status_buf_dma_handle; -+ ep0->dwc_ep.xfer_len = 2; -+ ep0->dwc_ep.xfer_count = 0; -+ ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len; -+ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep); -+} -+ -+/** -+ * This function process the SET_FEATURE Setup Commands. -+ */ -+static inline void do_set_feature(dwc_otg_pcd_t * pcd) -+{ -+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); -+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; -+ usb_device_request_t ctrl = pcd->setup_pkt->req; -+ dwc_otg_pcd_ep_t *ep = 0; -+ int32_t otg_cap_param = core_if->core_params->otg_cap; -+ gotgctl_data_t gotgctl = {.d32 = 0 }; -+ -+ DWC_DEBUGPL(DBG_PCD, "SET_FEATURE:%02x.%02x v%04x i%04x l%04x\n", -+ ctrl.bmRequestType, ctrl.bRequest, -+ UGETW(ctrl.wValue), UGETW(ctrl.wIndex), -+ UGETW(ctrl.wLength)); -+ DWC_DEBUGPL(DBG_PCD, "otg_cap=%d\n", otg_cap_param); -+ -+ switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) { -+ case UT_DEVICE: -+ switch (UGETW(ctrl.wValue)) { -+ case UF_DEVICE_REMOTE_WAKEUP: -+ pcd->remote_wakeup_enable = 1; -+ break; -+ -+ case UF_TEST_MODE: -+ /* Setup the Test Mode tasklet to do the Test -+ * Packet generation after the SETUP Status -+ * phase has completed. */ -+ -+ /** @todo This has not been tested since the -+ * tasklet struct was put into the PCD -+ * struct! */ -+ pcd->test_mode = UGETW(ctrl.wIndex) >> 8; -+ DWC_TASK_SCHEDULE(pcd->test_mode_tasklet); -+ break; -+ -+ case UF_DEVICE_B_HNP_ENABLE: -+ DWC_DEBUGPL(DBG_PCDV, -+ "SET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n"); -+ -+ /* dev may initiate HNP */ -+ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) { -+ pcd->b_hnp_enable = 1; -+ dwc_otg_pcd_update_otg(pcd, 0); -+ DWC_DEBUGPL(DBG_PCD, "Request B HNP\n"); -+ /**@todo Is the gotgctl.devhnpen cleared -+ * by a USB Reset? */ -+ gotgctl.b.devhnpen = 1; -+ gotgctl.b.hnpreq = 1; -+ DWC_WRITE_REG32(&global_regs->gotgctl, -+ gotgctl.d32); -+ } else { -+ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); -+ return; -+ } -+ break; -+ -+ case UF_DEVICE_A_HNP_SUPPORT: -+ /* RH port supports HNP */ -+ DWC_DEBUGPL(DBG_PCDV, -+ "SET_FEATURE: USB_DEVICE_A_HNP_SUPPORT\n"); -+ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) { -+ pcd->a_hnp_support = 1; -+ dwc_otg_pcd_update_otg(pcd, 0); -+ } else { -+ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); -+ return; -+ } -+ break; -+ -+ case UF_DEVICE_A_ALT_HNP_SUPPORT: -+ /* other RH port does */ -+ DWC_DEBUGPL(DBG_PCDV, -+ "SET_FEATURE: USB_DEVICE_A_ALT_HNP_SUPPORT\n"); -+ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) { -+ pcd->a_alt_hnp_support = 1; -+ dwc_otg_pcd_update_otg(pcd, 0); -+ } else { -+ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); -+ return; -+ } -+ break; -+ -+ default: -+ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); -+ return; -+ -+ } -+ do_setup_in_status_phase(pcd); -+ break; -+ -+ case UT_INTERFACE: -+ do_gadget_setup(pcd, &ctrl); -+ break; -+ -+ case UT_ENDPOINT: -+ if (UGETW(ctrl.wValue) == UF_ENDPOINT_HALT) { -+ ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex)); -+ if (ep == 0) { -+ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); -+ return; -+ } -+ ep->stopped = 1; -+ dwc_otg_ep_set_stall(core_if, &ep->dwc_ep); -+ } -+ do_setup_in_status_phase(pcd); -+ break; -+ } -+} -+ -+/** -+ * This function process the CLEAR_FEATURE Setup Commands. -+ */ -+static inline void do_clear_feature(dwc_otg_pcd_t * pcd) -+{ -+ usb_device_request_t ctrl = pcd->setup_pkt->req; -+ dwc_otg_pcd_ep_t *ep = 0; -+ -+ DWC_DEBUGPL(DBG_PCD, -+ "CLEAR_FEATURE:%02x.%02x v%04x i%04x l%04x\n", -+ ctrl.bmRequestType, ctrl.bRequest, -+ UGETW(ctrl.wValue), UGETW(ctrl.wIndex), -+ UGETW(ctrl.wLength)); -+ -+ switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) { -+ case UT_DEVICE: -+ switch (UGETW(ctrl.wValue)) { -+ case UF_DEVICE_REMOTE_WAKEUP: -+ pcd->remote_wakeup_enable = 0; -+ break; -+ -+ case UF_TEST_MODE: -+ /** @todo Add CLEAR_FEATURE for TEST modes. */ -+ break; -+ -+ default: -+ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); -+ return; -+ } -+ do_setup_in_status_phase(pcd); -+ break; -+ -+ case UT_ENDPOINT: -+ ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex)); -+ if (ep == 0) { -+ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); -+ return; -+ } -+ -+ pcd_clear_halt(pcd, ep); -+ -+ break; -+ } -+} -+ -+/** -+ * This function process the SET_ADDRESS Setup Commands. -+ */ -+static inline void do_set_address(dwc_otg_pcd_t * pcd) -+{ -+ dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if; -+ usb_device_request_t ctrl = pcd->setup_pkt->req; -+ -+ if (ctrl.bmRequestType == UT_DEVICE) { -+ dcfg_data_t dcfg = {.d32 = 0 }; -+ -+#ifdef DEBUG_EP0 -+// DWC_DEBUGPL(DBG_PCDV, "SET_ADDRESS:%d\n", ctrl.wValue); -+#endif -+ dcfg.b.devaddr = UGETW(ctrl.wValue); -+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dcfg, 0, dcfg.d32); -+ do_setup_in_status_phase(pcd); -+ } -+} -+ -+/** -+ * This function processes SETUP commands. In Linux, the USB Command -+ * processing is done in two places - the first being the PCD and the -+ * second in the Gadget Driver (for example, the File-Backed Storage -+ * Gadget Driver). -+ * -+ *
Parameter NameMeaning
otg_capSpecifies the OTG capabilities. The driver will automatically detect the -+ value for this parameter if none is specified. -+ - 0: HNP and SRP capable (default, if available) -+ - 1: SRP Only capable -+ - 2: No HNP/SRP capable -+
dma_enableSpecifies whether to use slave or DMA mode for accessing the data FIFOs. -+ The driver will automatically detect the value for this parameter if none is -+ specified. -+ - 0: Slave -+ - 1: DMA (default, if available) -+
dma_burst_sizeThe DMA Burst size (applicable only for External DMA Mode). -+ - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32) -+
speedSpecifies the maximum speed of operation in host and device mode. The -+ actual speed depends on the speed of the attached device and the value of -+ phy_type. -+ - 0: High Speed (default) -+ - 1: Full Speed -+
host_support_fs_ls_low_powerSpecifies whether low power mode is supported when attached to a Full -+ Speed or Low Speed device in host mode. -+ - 0: Don't support low power mode (default) -+ - 1: Support low power mode -+
host_ls_low_power_phy_clkSpecifies the PHY clock rate in low power mode when connected to a Low -+ Speed device in host mode. This parameter is applicable only if -+ HOST_SUPPORT_FS_LS_LOW_POWER is enabled. -+ - 0: 48 MHz (default) -+ - 1: 6 MHz -+
enable_dynamic_fifo Specifies whether FIFOs may be resized by the driver software. -+ - 0: Use cC FIFO size parameters -+ - 1: Allow dynamic FIFO sizing (default) -+
data_fifo_sizeTotal number of 4-byte words in the data FIFO memory. This memory -+ includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs. -+ - Values: 32 to 32768 (default 8192) -+ -+ Note: The total FIFO memory depth in the FPGA configuration is 8192. -+
dev_rx_fifo_sizeNumber of 4-byte words in the Rx FIFO in device mode when dynamic -+ FIFO sizing is enabled. -+ - Values: 16 to 32768 (default 1064) -+
dev_nperio_tx_fifo_sizeNumber of 4-byte words in the non-periodic Tx FIFO in device mode when -+ dynamic FIFO sizing is enabled. -+ - Values: 16 to 32768 (default 1024) -+
dev_perio_tx_fifo_size_n (n = 1 to 15)Number of 4-byte words in each of the periodic Tx FIFOs in device mode -+ when dynamic FIFO sizing is enabled. -+ - Values: 4 to 768 (default 256) -+
host_rx_fifo_sizeNumber of 4-byte words in the Rx FIFO in host mode when dynamic FIFO -+ sizing is enabled. -+ - Values: 16 to 32768 (default 1024) -+
host_nperio_tx_fifo_sizeNumber of 4-byte words in the non-periodic Tx FIFO in host mode when -+ dynamic FIFO sizing is enabled in the core. -+ - Values: 16 to 32768 (default 1024) -+
host_perio_tx_fifo_sizeNumber of 4-byte words in the host periodic Tx FIFO when dynamic FIFO -+ sizing is enabled. -+ - Values: 16 to 32768 (default 1024) -+
max_transfer_sizeThe maximum transfer size supported in bytes. -+ - Values: 2047 to 65,535 (default 65,535) -+
max_packet_countThe maximum number of packets in a transfer. -+ - Values: 15 to 511 (default 511) -+
host_channelsThe number of host channel registers to use. -+ - Values: 1 to 16 (default 12) -+ -+ Note: The FPGA configuration supports a maximum of 12 host channels. -+
dev_endpointsThe number of endpoints in addition to EP0 available for device mode -+ operations. -+ - Values: 1 to 15 (default 6 IN and OUT) -+ -+ Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in -+ addition to EP0. -+
phy_typeSpecifies the type of PHY interface to use. By default, the driver will -+ automatically detect the phy_type. -+ - 0: Full Speed -+ - 1: UTMI+ (default, if available) -+ - 2: ULPI -+
phy_utmi_widthSpecifies the UTMI+ Data Width. This parameter is applicable for a -+ phy_type of UTMI+. Also, this parameter is applicable only if the -+ OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the -+ core has been configured to work at either data path width. -+ - Values: 8 or 16 bits (default 16) -+
phy_ulpi_ddrSpecifies whether the ULPI operates at double or single data rate. This -+ parameter is only applicable if phy_type is ULPI. -+ - 0: single data rate ULPI interface with 8 bit wide data bus (default) -+ - 1: double data rate ULPI interface with 4 bit wide data bus -+
i2c_enableSpecifies whether to use the I2C interface for full speed PHY. This -+ parameter is only applicable if PHY_TYPE is FS. -+ - 0: Disabled (default) -+ - 1: Enabled -+
ulpi_fs_lsSpecifies whether to use ULPI FS/LS mode only. -+ - 0: Disabled (default) -+ - 1: Enabled -+
ts_dlineSpecifies whether term select D-Line pulsing for all PHYs is enabled. -+ - 0: Disabled (default) -+ - 1: Enabled -+
en_multiple_tx_fifoSpecifies whether dedicatedto tx fifos are enabled for non periodic IN EPs. -+ The driver will automatically detect the value for this parameter if none is -+ specified. -+ - 0: Disabled -+ - 1: Enabled (default, if available) -+
dev_tx_fifo_size_n (n = 1 to 15)Number of 4-byte words in each of the Tx FIFOs in device mode -+ when dynamic FIFO sizing is enabled. -+ - Values: 4 to 768 (default 256) -+
tx_thr_lengthTransmit Threshold length in 32 bit double words -+ - Values: 8 to 128 (default 64) -+
rx_thr_lengthReceive Threshold length in 32 bit double words -+ - Values: 8 to 128 (default 64) -+
thr_ctlSpecifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of -+ this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and -+ Rx transfers accordingly. -+ The driver will automatically detect the value for this parameter if none is -+ specified. -+ - Values: 0 to 7 (default 0) -+ Bit values indicate: -+ - 0: Thresholding disabled -+ - 1: Thresholding enabled -+
dma_desc_enableSpecifies whether to enable Descriptor DMA mode. -+ The driver will automatically detect the value for this parameter if none is -+ specified. -+ - 0: Descriptor DMA disabled -+ - 1: Descriptor DMA (default, if available) -+
mpi_enableSpecifies whether to enable MPI enhancement mode. -+ The driver will automatically detect the value for this parameter if none is -+ specified. -+ - 0: MPI disabled (default) -+ - 1: MPI enable -+
pti_enableSpecifies whether to enable PTI enhancement support. -+ The driver will automatically detect the value for this parameter if none is -+ specified. -+ - 0: PTI disabled (default) -+ - 1: PTI enable -+
lpm_enableSpecifies whether to enable LPM support. -+ The driver will automatically detect the value for this parameter if none is -+ specified. -+ - 0: LPM disabled -+ - 1: LPM enable (default, if available) -+
ic_usb_capSpecifies whether to enable IC_USB capability. -+ The driver will automatically detect the value for this parameter if none is -+ specified. -+ - 0: IC_USB disabled (default, if available) -+ - 1: IC_USB enable -+
ahb_thr_ratioSpecifies AHB Threshold ratio. -+ - Values: 0 to 3 (default 0) -+
power_downSpecifies Power Down(Hibernation) Mode. -+ The driver will automatically detect the value for this parameter if none is -+ specified. -+ - 0: Power Down disabled (default) -+ - 2: Power Down enabled -+
reload_ctlSpecifies whether dynamic reloading of the HFIR register is allowed during -+ run time. The driver will automatically detect the value for this parameter if -+ none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0 -+ the core might misbehave. -+ - 0: Reload Control disabled (default) -+ - 1: Reload Control enabled -+
dev_out_nakSpecifies whether Device OUT NAK enhancement enabled or no. -+ The driver will automatically detect the value for this parameter if -+ none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1b1. -+ - 0: The core does not set NAK after Bulk OUT transfer complete (default) -+ - 1: The core sets NAK after Bulk OUT transfer complete -+
cont_on_bnaSpecifies whether Enable Continue on BNA enabled or no. -+ After receiving BNA interrupt the core disables the endpoint,when the -+ endpoint is re-enabled by the application the -+ - 0: Core starts processing from the DOEPDMA descriptor (default) -+ - 1: Core starts processing from the descriptor which received the BNA. -+ This parameter is valid only when OTG_EN_DESC_DMA == 1b1. -+
ahb_singleThis bit when programmed supports SINGLE transfers for remainder data -+ in a transfer for DMA mode of operation. -+ - 0: The remainder data will be sent using INCR burst size (default) -+ - 1: The remainder data will be sent using SINGLE burst size. -+
adp_enableSpecifies whether ADP feature is enabled. -+ The driver will automatically detect the value for this parameter if none is -+ specified. -+ - 0: ADP feature disabled (default) -+ - 1: ADP feature enabled -+
otg_verSpecifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3 -+ USB OTG device. -+ - 0: OTG 2.0 support disabled (default) -+ - 1: OTG 2.0 support enabled -+
-+ * -+ * -+ * -+ * -+ * -+ * -+ * -+ * -+ * -+ * -+ * -+ * -+ * -+ * -+ * -+ * -+ * -+ * -+ * -+ * -+ * -+ * -+ * -+ *
Command Driver Description
GET_STATUS PCD Command is processed as -+ * defined in chapter 9 of the USB 2.0 Specification chapter 9 -+ *
CLEAR_FEATURE PCD The Device and Endpoint -+ * requests are the ENDPOINT_HALT feature is procesed, all others the -+ * interface requests are ignored.
SET_FEATURE PCD The Device and Endpoint -+ * requests are processed by the PCD. Interface requests are passed -+ * to the Gadget Driver.
SET_ADDRESS PCD Program the DCFG reg, -+ * with device address received
GET_DESCRIPTOR Gadget Driver Return the -+ * requested descriptor
SET_DESCRIPTOR Gadget Driver Optional - -+ * not implemented by any of the existing Gadget Drivers.
SET_CONFIGURATION Gadget Driver Disable -+ * all EPs and enable EPs for new configuration.
GET_CONFIGURATION Gadget Driver Return -+ * the current configuration
SET_INTERFACE Gadget Driver Disable all -+ * EPs and enable EPs for new configuration.
GET_INTERFACE Gadget Driver Return the -+ * current interface.
SYNC_FRAME PCD Display debug -+ * message.
-+ * -+ * When the SETUP Phase Done interrupt occurs, the PCD SETUP commands are -+ * processed by pcd_setup. Calling the Function Driver's setup function from -+ * pcd_setup processes the gadget SETUP commands. -+ */ -+static inline void pcd_setup(dwc_otg_pcd_t * pcd) -+{ -+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); -+ dwc_otg_dev_if_t *dev_if = core_if->dev_if; -+ usb_device_request_t ctrl = pcd->setup_pkt->req; -+ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; -+ -+ deptsiz0_data_t doeptsize0 = {.d32 = 0 }; -+ -+#ifdef DWC_UTE_CFI -+ int retval = 0; -+ struct cfi_usb_ctrlrequest cfi_req; -+#endif -+ -+ doeptsize0.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doeptsiz); -+ -+ /** In BDMA more then 1 setup packet is not supported till 3.00a */ -+ if (core_if->dma_enable && core_if->dma_desc_enable == 0 -+ && (doeptsize0.b.supcnt < 2) -+ && (core_if->snpsid < OTG_CORE_REV_2_94a)) { -+ DWC_ERROR -+ ("\n\n----------- CANNOT handle > 1 setup packet in DMA mode\n\n"); -+ } -+ if ((core_if->snpsid >= OTG_CORE_REV_3_00a) -+ && (core_if->dma_enable == 1) && (core_if->dma_desc_enable == 0)) { -+ ctrl = -+ (pcd->setup_pkt + -+ (3 - doeptsize0.b.supcnt - 1 + -+ ep0->dwc_ep.stp_rollover))->req; -+ } -+#ifdef DEBUG_EP0 -+ DWC_DEBUGPL(DBG_PCD, "SETUP %02x.%02x v%04x i%04x l%04x\n", -+ ctrl.bmRequestType, ctrl.bRequest, -+ UGETW(ctrl.wValue), UGETW(ctrl.wIndex), -+ UGETW(ctrl.wLength)); -+#endif -+ -+ /* Clean up the request queue */ -+ dwc_otg_request_nuke(ep0); -+ ep0->stopped = 0; -+ -+ if (ctrl.bmRequestType & UE_DIR_IN) { -+ ep0->dwc_ep.is_in = 1; -+ pcd->ep0state = EP0_IN_DATA_PHASE; -+ } else { -+ ep0->dwc_ep.is_in = 0; -+ pcd->ep0state = EP0_OUT_DATA_PHASE; -+ } -+ -+ if (UGETW(ctrl.wLength) == 0) { -+ ep0->dwc_ep.is_in = 1; -+ pcd->ep0state = EP0_IN_STATUS_PHASE; -+ } -+ -+ if (UT_GET_TYPE(ctrl.bmRequestType) != UT_STANDARD) { -+ -+#ifdef DWC_UTE_CFI -+ DWC_MEMCPY(&cfi_req, &ctrl, sizeof(usb_device_request_t)); -+ -+ //printk(KERN_ALERT "CFI: req_type=0x%02x; req=0x%02x\n", -+ ctrl.bRequestType, ctrl.bRequest); -+ if (UT_GET_TYPE(cfi_req.bRequestType) == UT_VENDOR) { -+ if (cfi_req.bRequest > 0xB0 && cfi_req.bRequest < 0xBF) { -+ retval = cfi_setup(pcd, &cfi_req); -+ if (retval < 0) { -+ ep0_do_stall(pcd, retval); -+ pcd->ep0_pending = 0; -+ return; -+ } -+ -+ /* if need gadget setup then call it and check the retval */ -+ if (pcd->cfi->need_gadget_att) { -+ retval = -+ cfi_gadget_setup(pcd, -+ &pcd-> -+ cfi->ctrl_req); -+ if (retval < 0) { -+ pcd->ep0_pending = 0; -+ return; -+ } -+ } -+ -+ if (pcd->cfi->need_status_in_complete) { -+ do_setup_in_status_phase(pcd); -+ } -+ return; -+ } -+ } -+#endif -+ -+ /* handle non-standard (class/vendor) requests in the gadget driver */ -+ do_gadget_setup(pcd, &ctrl); -+ return; -+ } -+ -+ /** @todo NGS: Handle bad setup packet? */ -+ -+/////////////////////////////////////////// -+//// --- Standard Request handling --- //// -+ -+ switch (ctrl.bRequest) { -+ case UR_GET_STATUS: -+ do_get_status(pcd); -+ break; -+ -+ case UR_CLEAR_FEATURE: -+ do_clear_feature(pcd); -+ break; -+ -+ case UR_SET_FEATURE: -+ do_set_feature(pcd); -+ break; -+ -+ case UR_SET_ADDRESS: -+ do_set_address(pcd); -+ break; -+ -+ case UR_SET_INTERFACE: -+ case UR_SET_CONFIG: -+// _pcd->request_config = 1; /* Configuration changed */ -+ do_gadget_setup(pcd, &ctrl); -+ break; -+ -+ case UR_SYNCH_FRAME: -+ do_gadget_setup(pcd, &ctrl); -+ break; -+ -+ default: -+ /* Call the Gadget Driver's setup functions */ -+ do_gadget_setup(pcd, &ctrl); -+ break; -+ } -+} -+ -+/** -+ * This function completes the ep0 control transfer. -+ */ -+static int32_t ep0_complete_request(dwc_otg_pcd_ep_t * ep) -+{ -+ dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd); -+ dwc_otg_dev_if_t *dev_if = core_if->dev_if; -+ dwc_otg_dev_in_ep_regs_t *in_ep_regs = -+ dev_if->in_ep_regs[ep->dwc_ep.num]; -+#ifdef DEBUG_EP0 -+ dwc_otg_dev_out_ep_regs_t *out_ep_regs = -+ dev_if->out_ep_regs[ep->dwc_ep.num]; -+#endif -+ deptsiz0_data_t deptsiz; -+ dev_dma_desc_sts_t desc_sts; -+ dwc_otg_pcd_request_t *req; -+ int is_last = 0; -+ dwc_otg_pcd_t *pcd = ep->pcd; -+ -+#ifdef DWC_UTE_CFI -+ struct cfi_usb_ctrlrequest *ctrlreq; -+ int retval = -DWC_E_NOT_SUPPORTED; -+#endif -+ -+ desc_sts.b.bytes = 0; -+ -+ if (pcd->ep0_pending && DWC_CIRCLEQ_EMPTY(&ep->queue)) { -+ if (ep->dwc_ep.is_in) { -+#ifdef DEBUG_EP0 -+ DWC_DEBUGPL(DBG_PCDV, "Do setup OUT status phase\n"); -+#endif -+ do_setup_out_status_phase(pcd); -+ } else { -+#ifdef DEBUG_EP0 -+ DWC_DEBUGPL(DBG_PCDV, "Do setup IN status phase\n"); -+#endif -+ -+#ifdef DWC_UTE_CFI -+ ctrlreq = &pcd->cfi->ctrl_req; -+ -+ if (UT_GET_TYPE(ctrlreq->bRequestType) == UT_VENDOR) { -+ if (ctrlreq->bRequest > 0xB0 -+ && ctrlreq->bRequest < 0xBF) { -+ -+ /* Return if the PCD failed to handle the request */ -+ if ((retval = -+ pcd->cfi->ops. -+ ctrl_write_complete(pcd->cfi, -+ pcd)) < 0) { -+ CFI_INFO -+ ("ERROR setting a new value in the PCD(%d)\n", -+ retval); -+ ep0_do_stall(pcd, retval); -+ pcd->ep0_pending = 0; -+ return 0; -+ } -+ -+ /* If the gadget needs to be notified on the request */ -+ if (pcd->cfi->need_gadget_att == 1) { -+ //retval = do_gadget_setup(pcd, &pcd->cfi->ctrl_req); -+ retval = -+ cfi_gadget_setup(pcd, -+ &pcd->cfi-> -+ ctrl_req); -+ -+ /* Return from the function if the gadget failed to process -+ * the request properly - this should never happen !!! -+ */ -+ if (retval < 0) { -+ CFI_INFO -+ ("ERROR setting a new value in the gadget(%d)\n", -+ retval); -+ pcd->ep0_pending = 0; -+ return 0; -+ } -+ } -+ -+ CFI_INFO("%s: RETVAL=%d\n", __func__, -+ retval); -+ /* If we hit here then the PCD and the gadget has properly -+ * handled the request - so send the ZLP IN to the host. -+ */ -+ /* @todo: MAS - decide whether we need to start the setup -+ * stage based on the need_setup value of the cfi object -+ */ -+ do_setup_in_status_phase(pcd); -+ pcd->ep0_pending = 0; -+ return 1; -+ } -+ } -+#endif -+ -+ do_setup_in_status_phase(pcd); -+ } -+ pcd->ep0_pending = 0; -+ return 1; -+ } -+ -+ if (DWC_CIRCLEQ_EMPTY(&ep->queue)) { -+ return 0; -+ } -+ req = DWC_CIRCLEQ_FIRST(&ep->queue); -+ -+ if (pcd->ep0state == EP0_OUT_STATUS_PHASE -+ || pcd->ep0state == EP0_IN_STATUS_PHASE) { -+ is_last = 1; -+ } else if (ep->dwc_ep.is_in) { -+ deptsiz.d32 = DWC_READ_REG32(&in_ep_regs->dieptsiz); -+ if (core_if->dma_desc_enable != 0) -+ desc_sts = dev_if->in_desc_addr->status; -+#ifdef DEBUG_EP0 -+ DWC_DEBUGPL(DBG_PCDV, "%d len=%d xfersize=%d pktcnt=%d\n", -+ ep->dwc_ep.num, ep->dwc_ep.xfer_len, -+ deptsiz.b.xfersize, deptsiz.b.pktcnt); -+#endif -+ -+ if (((core_if->dma_desc_enable == 0) -+ && (deptsiz.b.xfersize == 0)) -+ || ((core_if->dma_desc_enable != 0) -+ && (desc_sts.b.bytes == 0))) { -+ req->actual = ep->dwc_ep.xfer_count; -+ /* Is a Zero Len Packet needed? */ -+ if (req->sent_zlp) { -+#ifdef DEBUG_EP0 -+ DWC_DEBUGPL(DBG_PCD, "Setup Rx ZLP\n"); -+#endif -+ req->sent_zlp = 0; -+ } -+ do_setup_out_status_phase(pcd); -+ } -+ } else { -+ /* ep0-OUT */ -+#ifdef DEBUG_EP0 -+ deptsiz.d32 = DWC_READ_REG32(&out_ep_regs->doeptsiz); -+ DWC_DEBUGPL(DBG_PCDV, "%d len=%d xsize=%d pktcnt=%d\n", -+ ep->dwc_ep.num, ep->dwc_ep.xfer_len, -+ deptsiz.b.xfersize, deptsiz.b.pktcnt); -+#endif -+ req->actual = ep->dwc_ep.xfer_count; -+ -+ /* Is a Zero Len Packet needed? */ -+ if (req->sent_zlp) { -+#ifdef DEBUG_EP0 -+ DWC_DEBUGPL(DBG_PCDV, "Setup Tx ZLP\n"); -+#endif -+ req->sent_zlp = 0; -+ } -+ /* For older cores do setup in status phase in Slave/BDMA modes, -+ * starting from 3.00 do that only in slave, and for DMA modes -+ * just re-enable ep 0 OUT here*/ -+ if (core_if->dma_enable == 0 -+ || (core_if->dma_desc_enable == 0 -+ && core_if->snpsid <= OTG_CORE_REV_2_94a)) { -+ do_setup_in_status_phase(pcd); -+ } else if (core_if->snpsid >= OTG_CORE_REV_3_00a) { -+ DWC_DEBUGPL(DBG_PCDV, -+ "Enable out ep before in status phase\n"); -+ ep0_out_start(core_if, pcd); -+ } -+ } -+ -+ /* Complete the request */ -+ if (is_last) { -+ dwc_otg_request_done(ep, req, 0); -+ ep->dwc_ep.start_xfer_buff = 0; -+ ep->dwc_ep.xfer_buff = 0; -+ ep->dwc_ep.xfer_len = 0; -+ return 1; -+ } -+ return 0; -+} -+ -+#ifdef DWC_UTE_CFI -+/** -+ * This function calculates traverses all the CFI DMA descriptors and -+ * and accumulates the bytes that are left to be transfered. -+ * -+ * @return The total bytes left to transfered, or a negative value as failure -+ */ -+static inline int cfi_calc_desc_residue(dwc_otg_pcd_ep_t * ep) -+{ -+ int32_t ret = 0; -+ int i; -+ struct dwc_otg_dma_desc *ddesc = NULL; -+ struct cfi_ep *cfiep; -+ -+ /* See if the pcd_ep has its respective cfi_ep mapped */ -+ cfiep = get_cfi_ep_by_pcd_ep(ep->pcd->cfi, ep); -+ if (!cfiep) { -+ CFI_INFO("%s: Failed to find ep\n", __func__); -+ return -1; -+ } -+ -+ ddesc = ep->dwc_ep.descs; -+ -+ for (i = 0; (i < cfiep->desc_count) && (i < MAX_DMA_DESCS_PER_EP); i++) { -+ -+#if defined(PRINT_CFI_DMA_DESCS) -+ print_desc(ddesc, ep->ep.name, i); -+#endif -+ ret += ddesc->status.b.bytes; -+ ddesc++; -+ } -+ -+ if (ret) -+ CFI_INFO("!!!!!!!!!! WARNING (%s) - residue=%d\n", __func__, -+ ret); -+ -+ return ret; -+} -+#endif -+ -+/** -+ * This function completes the request for the EP. If there are -+ * additional requests for the EP in the queue they will be started. -+ */ -+static void complete_ep(dwc_otg_pcd_ep_t * ep) -+{ -+ dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd); -+ dwc_otg_dev_if_t *dev_if = core_if->dev_if; -+ dwc_otg_dev_in_ep_regs_t *in_ep_regs = -+ dev_if->in_ep_regs[ep->dwc_ep.num]; -+ deptsiz_data_t deptsiz; -+ dev_dma_desc_sts_t desc_sts; -+ dwc_otg_pcd_request_t *req = 0; -+ dwc_otg_dev_dma_desc_t *dma_desc; -+ uint32_t byte_count = 0; -+ int is_last = 0; -+ int i; -+ -+ DWC_DEBUGPL(DBG_PCDV, "%s() %d-%s\n", __func__, ep->dwc_ep.num, -+ (ep->dwc_ep.is_in ? "IN" : "OUT")); -+ -+ /* Get any pending requests */ -+ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) { -+ req = DWC_CIRCLEQ_FIRST(&ep->queue); -+ if (!req) { -+ DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep); -+ return; -+ } -+ } else { -+ DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep); -+ return; -+ } -+ -+ DWC_DEBUGPL(DBG_PCD, "Requests %d\n", ep->pcd->request_pending); -+ -+ if (ep->dwc_ep.is_in) { -+ deptsiz.d32 = DWC_READ_REG32(&in_ep_regs->dieptsiz); -+ -+ if (core_if->dma_enable) { -+ if (core_if->dma_desc_enable == 0) { -+ if (deptsiz.b.xfersize == 0 -+ && deptsiz.b.pktcnt == 0) { -+ byte_count = -+ ep->dwc_ep.xfer_len - -+ ep->dwc_ep.xfer_count; -+ -+ ep->dwc_ep.xfer_buff += byte_count; -+ ep->dwc_ep.dma_addr += byte_count; -+ ep->dwc_ep.xfer_count += byte_count; -+ -+ DWC_DEBUGPL(DBG_PCDV, -+ "%d-%s len=%d xfersize=%d pktcnt=%d\n", -+ ep->dwc_ep.num, -+ (ep->dwc_ep. -+ is_in ? "IN" : "OUT"), -+ ep->dwc_ep.xfer_len, -+ deptsiz.b.xfersize, -+ deptsiz.b.pktcnt); -+ -+ if (ep->dwc_ep.xfer_len < -+ ep->dwc_ep.total_len) { -+ dwc_otg_ep_start_transfer -+ (core_if, &ep->dwc_ep); -+ } else if (ep->dwc_ep.sent_zlp) { -+ /* -+ * This fragment of code should initiate 0 -+ * length transfer in case if it is queued -+ * a transfer with size divisible to EPs max -+ * packet size and with usb_request zero field -+ * is set, which means that after data is transfered, -+ * it is also should be transfered -+ * a 0 length packet at the end. For Slave and -+ * Buffer DMA modes in this case SW has -+ * to initiate 2 transfers one with transfer size, -+ * and the second with 0 size. For Descriptor -+ * DMA mode SW is able to initiate a transfer, -+ * which will handle all the packets including -+ * the last 0 length. -+ */ -+ ep->dwc_ep.sent_zlp = 0; -+ dwc_otg_ep_start_zl_transfer -+ (core_if, &ep->dwc_ep); -+ } else { -+ is_last = 1; -+ } -+ } else { -+ if (ep->dwc_ep.type == -+ DWC_OTG_EP_TYPE_ISOC) { -+ req->actual = 0; -+ dwc_otg_request_done(ep, req, 0); -+ -+ ep->dwc_ep.start_xfer_buff = 0; -+ ep->dwc_ep.xfer_buff = 0; -+ ep->dwc_ep.xfer_len = 0; -+ -+ /* If there is a request in the queue start it. */ -+ start_next_request(ep); -+ } else -+ DWC_WARN -+ ("Incomplete transfer (%d - %s [siz=%d pkt=%d])\n", -+ ep->dwc_ep.num, -+ (ep->dwc_ep.is_in ? "IN" : "OUT"), -+ deptsiz.b.xfersize, -+ deptsiz.b.pktcnt); -+ } -+ } else { -+ dma_desc = ep->dwc_ep.desc_addr; -+ byte_count = 0; -+ ep->dwc_ep.sent_zlp = 0; -+ -+#ifdef DWC_UTE_CFI -+ CFI_INFO("%s: BUFFER_MODE=%d\n", __func__, -+ ep->dwc_ep.buff_mode); -+ if (ep->dwc_ep.buff_mode != BM_STANDARD) { -+ int residue; -+ -+ residue = cfi_calc_desc_residue(ep); -+ if (residue < 0) -+ return; -+ -+ byte_count = residue; -+ } else { -+#endif -+ for (i = 0; i < ep->dwc_ep.desc_cnt; -+ ++i) { -+ desc_sts = dma_desc->status; -+ byte_count += desc_sts.b.bytes; -+ dma_desc++; -+ } -+#ifdef DWC_UTE_CFI -+ } -+#endif -+ if (byte_count == 0) { -+ ep->dwc_ep.xfer_count = -+ ep->dwc_ep.total_len; -+ is_last = 1; -+ } else { -+ DWC_WARN("Incomplete transfer\n"); -+ } -+ } -+ } else { -+ if (deptsiz.b.xfersize == 0 && deptsiz.b.pktcnt == 0) { -+ DWC_DEBUGPL(DBG_PCDV, -+ "%d-%s len=%d xfersize=%d pktcnt=%d\n", -+ ep->dwc_ep.num, -+ ep->dwc_ep.is_in ? "IN" : "OUT", -+ ep->dwc_ep.xfer_len, -+ deptsiz.b.xfersize, -+ deptsiz.b.pktcnt); -+ -+ /* Check if the whole transfer was completed, -+ * if no, setup transfer for next portion of data -+ */ -+ if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) { -+ dwc_otg_ep_start_transfer(core_if, -+ &ep->dwc_ep); -+ } else if (ep->dwc_ep.sent_zlp) { -+ /* -+ * This fragment of code should initiate 0 -+ * length trasfer in case if it is queued -+ * a trasfer with size divisible to EPs max -+ * packet size and with usb_request zero field -+ * is set, which means that after data is transfered, -+ * it is also should be transfered -+ * a 0 length packet at the end. For Slave and -+ * Buffer DMA modes in this case SW has -+ * to initiate 2 transfers one with transfer size, -+ * and the second with 0 size. For Desriptor -+ * DMA mode SW is able to initiate a transfer, -+ * which will handle all the packets including -+ * the last 0 legth. -+ */ -+ ep->dwc_ep.sent_zlp = 0; -+ dwc_otg_ep_start_zl_transfer(core_if, -+ &ep->dwc_ep); -+ } else { -+ is_last = 1; -+ } -+ } else { -+ DWC_WARN -+ ("Incomplete transfer (%d-%s [siz=%d pkt=%d])\n", -+ ep->dwc_ep.num, -+ (ep->dwc_ep.is_in ? "IN" : "OUT"), -+ deptsiz.b.xfersize, deptsiz.b.pktcnt); -+ } -+ } -+ } else { -+ dwc_otg_dev_out_ep_regs_t *out_ep_regs = -+ dev_if->out_ep_regs[ep->dwc_ep.num]; -+ desc_sts.d32 = 0; -+ if (core_if->dma_enable) { -+ if (core_if->dma_desc_enable) { -+ dma_desc = ep->dwc_ep.desc_addr; -+ byte_count = 0; -+ ep->dwc_ep.sent_zlp = 0; -+ -+#ifdef DWC_UTE_CFI -+ CFI_INFO("%s: BUFFER_MODE=%d\n", __func__, -+ ep->dwc_ep.buff_mode); -+ if (ep->dwc_ep.buff_mode != BM_STANDARD) { -+ int residue; -+ residue = cfi_calc_desc_residue(ep); -+ if (residue < 0) -+ return; -+ byte_count = residue; -+ } else { -+#endif -+ -+ for (i = 0; i < ep->dwc_ep.desc_cnt; -+ ++i) { -+ desc_sts = dma_desc->status; -+ byte_count += desc_sts.b.bytes; -+ dma_desc++; -+ } -+ -+#ifdef DWC_UTE_CFI -+ } -+#endif -+ /* Checking for interrupt Out transfers with not -+ * dword aligned mps sizes -+ */ -+ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_INTR && -+ (ep->dwc_ep.maxpacket%4)) { -+ ep->dwc_ep.xfer_count = -+ ep->dwc_ep.total_len - byte_count; -+ if ((ep->dwc_ep.xfer_len % -+ ep->dwc_ep.maxpacket) -+ && (ep->dwc_ep.xfer_len / -+ ep->dwc_ep.maxpacket < -+ MAX_DMA_DESC_CNT)) -+ ep->dwc_ep.xfer_len -= -+ (ep->dwc_ep.desc_cnt - -+ 1) * ep->dwc_ep.maxpacket + -+ ep->dwc_ep.xfer_len % -+ ep->dwc_ep.maxpacket; -+ else -+ ep->dwc_ep.xfer_len -= -+ ep->dwc_ep.desc_cnt * -+ ep->dwc_ep.maxpacket; -+ if (ep->dwc_ep.xfer_len > 0) { -+ dwc_otg_ep_start_transfer -+ (core_if, &ep->dwc_ep); -+ } else { -+ is_last = 1; -+ } -+ } else { -+ ep->dwc_ep.xfer_count = -+ ep->dwc_ep.total_len - byte_count + -+ ((4 - -+ (ep->dwc_ep. -+ total_len & 0x3)) & 0x3); -+ is_last = 1; -+ } -+ } else { -+ deptsiz.d32 = 0; -+ deptsiz.d32 = -+ DWC_READ_REG32(&out_ep_regs->doeptsiz); -+ -+ byte_count = (ep->dwc_ep.xfer_len - -+ ep->dwc_ep.xfer_count - -+ deptsiz.b.xfersize); -+ ep->dwc_ep.xfer_buff += byte_count; -+ ep->dwc_ep.dma_addr += byte_count; -+ ep->dwc_ep.xfer_count += byte_count; -+ -+ /* Check if the whole transfer was completed, -+ * if no, setup transfer for next portion of data -+ */ -+ if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) { -+ dwc_otg_ep_start_transfer(core_if, -+ &ep->dwc_ep); -+ } else if (ep->dwc_ep.sent_zlp) { -+ /* -+ * This fragment of code should initiate 0 -+ * length trasfer in case if it is queued -+ * a trasfer with size divisible to EPs max -+ * packet size and with usb_request zero field -+ * is set, which means that after data is transfered, -+ * it is also should be transfered -+ * a 0 length packet at the end. For Slave and -+ * Buffer DMA modes in this case SW has -+ * to initiate 2 transfers one with transfer size, -+ * and the second with 0 size. For Desriptor -+ * DMA mode SW is able to initiate a transfer, -+ * which will handle all the packets including -+ * the last 0 legth. -+ */ -+ ep->dwc_ep.sent_zlp = 0; -+ dwc_otg_ep_start_zl_transfer(core_if, -+ &ep->dwc_ep); -+ } else { -+ is_last = 1; -+ } -+ } -+ } else { -+ /* Check if the whole transfer was completed, -+ * if no, setup transfer for next portion of data -+ */ -+ if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) { -+ dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep); -+ } else if (ep->dwc_ep.sent_zlp) { -+ /* -+ * This fragment of code should initiate 0 -+ * length transfer in case if it is queued -+ * a transfer with size divisible to EPs max -+ * packet size and with usb_request zero field -+ * is set, which means that after data is transfered, -+ * it is also should be transfered -+ * a 0 length packet at the end. For Slave and -+ * Buffer DMA modes in this case SW has -+ * to initiate 2 transfers one with transfer size, -+ * and the second with 0 size. For Descriptor -+ * DMA mode SW is able to initiate a transfer, -+ * which will handle all the packets including -+ * the last 0 length. -+ */ -+ ep->dwc_ep.sent_zlp = 0; -+ dwc_otg_ep_start_zl_transfer(core_if, -+ &ep->dwc_ep); -+ } else { -+ is_last = 1; -+ } -+ } -+ -+ DWC_DEBUGPL(DBG_PCDV, -+ "addr %p, %d-%s len=%d cnt=%d xsize=%d pktcnt=%d\n", -+ &out_ep_regs->doeptsiz, ep->dwc_ep.num, -+ ep->dwc_ep.is_in ? "IN" : "OUT", -+ ep->dwc_ep.xfer_len, ep->dwc_ep.xfer_count, -+ deptsiz.b.xfersize, deptsiz.b.pktcnt); -+ } -+ -+ /* Complete the request */ -+ if (is_last) { -+#ifdef DWC_UTE_CFI -+ if (ep->dwc_ep.buff_mode != BM_STANDARD) { -+ req->actual = ep->dwc_ep.cfi_req_len - byte_count; -+ } else { -+#endif -+ req->actual = ep->dwc_ep.xfer_count; -+#ifdef DWC_UTE_CFI -+ } -+#endif -+ if (req->dw_align_buf) { -+ if (!ep->dwc_ep.is_in) { -+ dwc_memcpy(req->buf, req->dw_align_buf, req->length); -+ } -+ DWC_DMA_FREE(req->length, req->dw_align_buf, -+ req->dw_align_buf_dma); -+ } -+ -+ dwc_otg_request_done(ep, req, 0); -+ -+ ep->dwc_ep.start_xfer_buff = 0; -+ ep->dwc_ep.xfer_buff = 0; -+ ep->dwc_ep.xfer_len = 0; -+ -+ /* If there is a request in the queue start it. */ -+ start_next_request(ep); -+ } -+} -+ -+#ifdef DWC_EN_ISOC -+ -+/** -+ * This function BNA interrupt for Isochronous EPs -+ * -+ */ -+static void dwc_otg_pcd_handle_iso_bna(dwc_otg_pcd_ep_t * ep) -+{ -+ dwc_ep_t *dwc_ep = &ep->dwc_ep; -+ volatile uint32_t *addr; -+ depctl_data_t depctl = {.d32 = 0 }; -+ dwc_otg_pcd_t *pcd = ep->pcd; -+ dwc_otg_dev_dma_desc_t *dma_desc; -+ int i; -+ -+ dma_desc = -+ dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * (dwc_ep->proc_buf_num); -+ -+ if (dwc_ep->is_in) { -+ dev_dma_desc_sts_t sts = {.d32 = 0 }; -+ for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) { -+ sts.d32 = dma_desc->status.d32; -+ sts.b_iso_in.bs = BS_HOST_READY; -+ dma_desc->status.d32 = sts.d32; -+ } -+ } else { -+ dev_dma_desc_sts_t sts = {.d32 = 0 }; -+ for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) { -+ sts.d32 = dma_desc->status.d32; -+ sts.b_iso_out.bs = BS_HOST_READY; -+ dma_desc->status.d32 = sts.d32; -+ } -+ } -+ -+ if (dwc_ep->is_in == 0) { -+ addr = -+ &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep-> -+ num]->doepctl; -+ } else { -+ addr = -+ &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl; -+ } -+ depctl.b.epena = 1; -+ DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32); -+} -+ -+/** -+ * This function sets latest iso packet information(non-PTI mode) -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ * @param ep The EP to start the transfer on. -+ * -+ */ -+void set_current_pkt_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) -+{ -+ deptsiz_data_t deptsiz = {.d32 = 0 }; -+ dma_addr_t dma_addr; -+ uint32_t offset; -+ -+ if (ep->proc_buf_num) -+ dma_addr = ep->dma_addr1; -+ else -+ dma_addr = ep->dma_addr0; -+ -+ if (ep->is_in) { -+ deptsiz.d32 = -+ DWC_READ_REG32(&core_if->dev_if-> -+ in_ep_regs[ep->num]->dieptsiz); -+ offset = ep->data_per_frame; -+ } else { -+ deptsiz.d32 = -+ DWC_READ_REG32(&core_if->dev_if-> -+ out_ep_regs[ep->num]->doeptsiz); -+ offset = -+ ep->data_per_frame + -+ (0x4 & (0x4 - (ep->data_per_frame & 0x3))); -+ } -+ -+ if (!deptsiz.b.xfersize) { -+ ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame; -+ ep->pkt_info[ep->cur_pkt].offset = -+ ep->cur_pkt_dma_addr - dma_addr; -+ ep->pkt_info[ep->cur_pkt].status = 0; -+ } else { -+ ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame; -+ ep->pkt_info[ep->cur_pkt].offset = -+ ep->cur_pkt_dma_addr - dma_addr; -+ ep->pkt_info[ep->cur_pkt].status = -DWC_E_NO_DATA; -+ } -+ ep->cur_pkt_addr += offset; -+ ep->cur_pkt_dma_addr += offset; -+ ep->cur_pkt++; -+} -+ -+/** -+ * This function sets latest iso packet information(DDMA mode) -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ * @param dwc_ep The EP to start the transfer on. -+ * -+ */ -+static void set_ddma_iso_pkts_info(dwc_otg_core_if_t * core_if, -+ dwc_ep_t * dwc_ep) -+{ -+ dwc_otg_dev_dma_desc_t *dma_desc; -+ dev_dma_desc_sts_t sts = {.d32 = 0 }; -+ iso_pkt_info_t *iso_packet; -+ uint32_t data_per_desc; -+ uint32_t offset; -+ int i, j; -+ -+ iso_packet = dwc_ep->pkt_info; -+ -+ /** Reinit closed DMA Descriptors*/ -+ /** ISO OUT EP */ -+ if (dwc_ep->is_in == 0) { -+ dma_desc = -+ dwc_ep->iso_desc_addr + -+ dwc_ep->desc_cnt * dwc_ep->proc_buf_num; -+ offset = 0; -+ -+ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; -+ i += dwc_ep->pkt_per_frm) { -+ for (j = 0; j < dwc_ep->pkt_per_frm; ++j) { -+ data_per_desc = -+ ((j + 1) * dwc_ep->maxpacket > -+ dwc_ep-> -+ data_per_frame) ? dwc_ep->data_per_frame - -+ j * dwc_ep->maxpacket : dwc_ep->maxpacket; -+ data_per_desc += -+ (data_per_desc % 4) ? (4 - -+ data_per_desc % -+ 4) : 0; -+ -+ sts.d32 = dma_desc->status.d32; -+ -+ /* Write status in iso_packet_decsriptor */ -+ iso_packet->status = -+ sts.b_iso_out.rxsts + -+ (sts.b_iso_out.bs ^ BS_DMA_DONE); -+ if (iso_packet->status) { -+ iso_packet->status = -DWC_E_NO_DATA; -+ } -+ -+ /* Received data length */ -+ if (!sts.b_iso_out.rxbytes) { -+ iso_packet->length = -+ data_per_desc - -+ sts.b_iso_out.rxbytes; -+ } else { -+ iso_packet->length = -+ data_per_desc - -+ sts.b_iso_out.rxbytes + (4 - -+ dwc_ep->data_per_frame -+ % 4); -+ } -+ -+ iso_packet->offset = offset; -+ -+ offset += data_per_desc; -+ dma_desc++; -+ iso_packet++; -+ } -+ } -+ -+ for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) { -+ data_per_desc = -+ ((j + 1) * dwc_ep->maxpacket > -+ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame - -+ j * dwc_ep->maxpacket : dwc_ep->maxpacket; -+ data_per_desc += -+ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0; -+ -+ sts.d32 = dma_desc->status.d32; -+ -+ /* Write status in iso_packet_decsriptor */ -+ iso_packet->status = -+ sts.b_iso_out.rxsts + -+ (sts.b_iso_out.bs ^ BS_DMA_DONE); -+ if (iso_packet->status) { -+ iso_packet->status = -DWC_E_NO_DATA; -+ } -+ -+ /* Received data length */ -+ iso_packet->length = -+ dwc_ep->data_per_frame - sts.b_iso_out.rxbytes; -+ -+ iso_packet->offset = offset; -+ -+ offset += data_per_desc; -+ iso_packet++; -+ dma_desc++; -+ } -+ -+ sts.d32 = dma_desc->status.d32; -+ -+ /* Write status in iso_packet_decsriptor */ -+ iso_packet->status = -+ sts.b_iso_out.rxsts + (sts.b_iso_out.bs ^ BS_DMA_DONE); -+ if (iso_packet->status) { -+ iso_packet->status = -DWC_E_NO_DATA; -+ } -+ /* Received data length */ -+ if (!sts.b_iso_out.rxbytes) { -+ iso_packet->length = -+ dwc_ep->data_per_frame - sts.b_iso_out.rxbytes; -+ } else { -+ iso_packet->length = -+ dwc_ep->data_per_frame - sts.b_iso_out.rxbytes + -+ (4 - dwc_ep->data_per_frame % 4); -+ } -+ -+ iso_packet->offset = offset; -+ } else { -+/** ISO IN EP */ -+ -+ dma_desc = -+ dwc_ep->iso_desc_addr + -+ dwc_ep->desc_cnt * dwc_ep->proc_buf_num; -+ -+ for (i = 0; i < dwc_ep->desc_cnt - 1; i++) { -+ sts.d32 = dma_desc->status.d32; -+ -+ /* Write status in iso packet descriptor */ -+ iso_packet->status = -+ sts.b_iso_in.txsts + -+ (sts.b_iso_in.bs ^ BS_DMA_DONE); -+ if (iso_packet->status != 0) { -+ iso_packet->status = -DWC_E_NO_DATA; -+ -+ } -+ /* Bytes has been transfered */ -+ iso_packet->length = -+ dwc_ep->data_per_frame - sts.b_iso_in.txbytes; -+ -+ dma_desc++; -+ iso_packet++; -+ } -+ -+ sts.d32 = dma_desc->status.d32; -+ while (sts.b_iso_in.bs == BS_DMA_BUSY) { -+ sts.d32 = dma_desc->status.d32; -+ } -+ -+ /* Write status in iso packet descriptor ??? do be done with ERROR codes */ -+ iso_packet->status = -+ sts.b_iso_in.txsts + (sts.b_iso_in.bs ^ BS_DMA_DONE); -+ if (iso_packet->status != 0) { -+ iso_packet->status = -DWC_E_NO_DATA; -+ } -+ -+ /* Bytes has been transfered */ -+ iso_packet->length = -+ dwc_ep->data_per_frame - sts.b_iso_in.txbytes; -+ } -+} -+ -+/** -+ * This function reinitialize DMA Descriptors for Isochronous transfer -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ * @param dwc_ep The EP to start the transfer on. -+ * -+ */ -+static void reinit_ddma_iso_xfer(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep) -+{ -+ int i, j; -+ dwc_otg_dev_dma_desc_t *dma_desc; -+ dma_addr_t dma_ad; -+ volatile uint32_t *addr; -+ dev_dma_desc_sts_t sts = {.d32 = 0 }; -+ uint32_t data_per_desc; -+ -+ if (dwc_ep->is_in == 0) { -+ addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl; -+ } else { -+ addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl; -+ } -+ -+ if (dwc_ep->proc_buf_num == 0) { -+ /** Buffer 0 descriptors setup */ -+ dma_ad = dwc_ep->dma_addr0; -+ } else { -+ /** Buffer 1 descriptors setup */ -+ dma_ad = dwc_ep->dma_addr1; -+ } -+ -+ /** Reinit closed DMA Descriptors*/ -+ /** ISO OUT EP */ -+ if (dwc_ep->is_in == 0) { -+ dma_desc = -+ dwc_ep->iso_desc_addr + -+ dwc_ep->desc_cnt * dwc_ep->proc_buf_num; -+ -+ sts.b_iso_out.bs = BS_HOST_READY; -+ sts.b_iso_out.rxsts = 0; -+ sts.b_iso_out.l = 0; -+ sts.b_iso_out.sp = 0; -+ sts.b_iso_out.ioc = 0; -+ sts.b_iso_out.pid = 0; -+ sts.b_iso_out.framenum = 0; -+ -+ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; -+ i += dwc_ep->pkt_per_frm) { -+ for (j = 0; j < dwc_ep->pkt_per_frm; ++j) { -+ data_per_desc = -+ ((j + 1) * dwc_ep->maxpacket > -+ dwc_ep-> -+ data_per_frame) ? dwc_ep->data_per_frame - -+ j * dwc_ep->maxpacket : dwc_ep->maxpacket; -+ data_per_desc += -+ (data_per_desc % 4) ? (4 - -+ data_per_desc % -+ 4) : 0; -+ sts.b_iso_out.rxbytes = data_per_desc; -+ dma_desc->buf = dma_ad; -+ dma_desc->status.d32 = sts.d32; -+ -+ dma_ad += data_per_desc; -+ dma_desc++; -+ } -+ } -+ -+ for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) { -+ -+ data_per_desc = -+ ((j + 1) * dwc_ep->maxpacket > -+ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame - -+ j * dwc_ep->maxpacket : dwc_ep->maxpacket; -+ data_per_desc += -+ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0; -+ sts.b_iso_out.rxbytes = data_per_desc; -+ -+ dma_desc->buf = dma_ad; -+ dma_desc->status.d32 = sts.d32; -+ -+ dma_desc++; -+ dma_ad += data_per_desc; -+ } -+ -+ sts.b_iso_out.ioc = 1; -+ sts.b_iso_out.l = dwc_ep->proc_buf_num; -+ -+ data_per_desc = -+ ((j + 1) * dwc_ep->maxpacket > -+ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame - -+ j * dwc_ep->maxpacket : dwc_ep->maxpacket; -+ data_per_desc += -+ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0; -+ sts.b_iso_out.rxbytes = data_per_desc; -+ -+ dma_desc->buf = dma_ad; -+ dma_desc->status.d32 = sts.d32; -+ } else { -+/** ISO IN EP */ -+ -+ dma_desc = -+ dwc_ep->iso_desc_addr + -+ dwc_ep->desc_cnt * dwc_ep->proc_buf_num; -+ -+ sts.b_iso_in.bs = BS_HOST_READY; -+ sts.b_iso_in.txsts = 0; -+ sts.b_iso_in.sp = 0; -+ sts.b_iso_in.ioc = 0; -+ sts.b_iso_in.pid = dwc_ep->pkt_per_frm; -+ sts.b_iso_in.framenum = dwc_ep->next_frame; -+ sts.b_iso_in.txbytes = dwc_ep->data_per_frame; -+ sts.b_iso_in.l = 0; -+ -+ for (i = 0; i < dwc_ep->desc_cnt - 1; i++) { -+ dma_desc->buf = dma_ad; -+ dma_desc->status.d32 = sts.d32; -+ -+ sts.b_iso_in.framenum += dwc_ep->bInterval; -+ dma_ad += dwc_ep->data_per_frame; -+ dma_desc++; -+ } -+ -+ sts.b_iso_in.ioc = 1; -+ sts.b_iso_in.l = dwc_ep->proc_buf_num; -+ -+ dma_desc->buf = dma_ad; -+ dma_desc->status.d32 = sts.d32; -+ -+ dwc_ep->next_frame = -+ sts.b_iso_in.framenum + dwc_ep->bInterval * 1; -+ } -+ dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1; -+} -+ -+/** -+ * This function is to handle Iso EP transfer complete interrupt -+ * in case Iso out packet was dropped -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ * @param dwc_ep The EP for wihich transfer complete was asserted -+ * -+ */ -+static uint32_t handle_iso_out_pkt_dropped(dwc_otg_core_if_t * core_if, -+ dwc_ep_t * dwc_ep) -+{ -+ uint32_t dma_addr; -+ uint32_t drp_pkt; -+ uint32_t drp_pkt_cnt; -+ deptsiz_data_t deptsiz = {.d32 = 0 }; -+ depctl_data_t depctl = {.d32 = 0 }; -+ int i; -+ -+ deptsiz.d32 = -+ DWC_READ_REG32(&core_if->dev_if-> -+ out_ep_regs[dwc_ep->num]->doeptsiz); -+ -+ drp_pkt = dwc_ep->pkt_cnt - deptsiz.b.pktcnt; -+ drp_pkt_cnt = dwc_ep->pkt_per_frm - (drp_pkt % dwc_ep->pkt_per_frm); -+ -+ /* Setting dropped packets status */ -+ for (i = 0; i < drp_pkt_cnt; ++i) { -+ dwc_ep->pkt_info[drp_pkt].status = -DWC_E_NO_DATA; -+ drp_pkt++; -+ deptsiz.b.pktcnt--; -+ } -+ -+ if (deptsiz.b.pktcnt > 0) { -+ deptsiz.b.xfersize = -+ dwc_ep->xfer_len - (dwc_ep->pkt_cnt - -+ deptsiz.b.pktcnt) * dwc_ep->maxpacket; -+ } else { -+ deptsiz.b.xfersize = 0; -+ deptsiz.b.pktcnt = 0; -+ } -+ -+ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz, -+ deptsiz.d32); -+ -+ if (deptsiz.b.pktcnt > 0) { -+ if (dwc_ep->proc_buf_num) { -+ dma_addr = -+ dwc_ep->dma_addr1 + dwc_ep->xfer_len - -+ deptsiz.b.xfersize; -+ } else { -+ dma_addr = -+ dwc_ep->dma_addr0 + dwc_ep->xfer_len - -+ deptsiz.b.xfersize;; -+ } -+ -+ DWC_WRITE_REG32(&core_if->dev_if-> -+ out_ep_regs[dwc_ep->num]->doepdma, dma_addr); -+ -+ /** Re-enable endpoint, clear nak */ -+ depctl.d32 = 0; -+ depctl.b.epena = 1; -+ depctl.b.cnak = 1; -+ -+ DWC_MODIFY_REG32(&core_if->dev_if-> -+ out_ep_regs[dwc_ep->num]->doepctl, depctl.d32, -+ depctl.d32); -+ return 0; -+ } else { -+ return 1; -+ } -+} -+ -+/** -+ * This function sets iso packets information(PTI mode) -+ * -+ * @param core_if Programming view of DWC_otg controller. -+ * @param ep The EP to start the transfer on. -+ * -+ */ -+static uint32_t set_iso_pkts_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) -+{ -+ int i, j; -+ dma_addr_t dma_ad; -+ iso_pkt_info_t *packet_info = ep->pkt_info; -+ uint32_t offset; -+ uint32_t frame_data; -+ deptsiz_data_t deptsiz; -+ -+ if (ep->proc_buf_num == 0) { -+ /** Buffer 0 descriptors setup */ -+ dma_ad = ep->dma_addr0; -+ } else { -+ /** Buffer 1 descriptors setup */ -+ dma_ad = ep->dma_addr1; -+ } -+ -+ if (ep->is_in) { -+ deptsiz.d32 = -+ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]-> -+ dieptsiz); -+ } else { -+ deptsiz.d32 = -+ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[ep->num]-> -+ doeptsiz); -+ } -+ -+ if (!deptsiz.b.xfersize) { -+ offset = 0; -+ for (i = 0; i < ep->pkt_cnt; i += ep->pkt_per_frm) { -+ frame_data = ep->data_per_frame; -+ for (j = 0; j < ep->pkt_per_frm; ++j) { -+ -+ /* Packet status - is not set as initially -+ * it is set to 0 and if packet was sent -+ successfully, status field will remain 0*/ -+ -+ /* Bytes has been transfered */ -+ packet_info->length = -+ (ep->maxpacket < -+ frame_data) ? ep->maxpacket : frame_data; -+ -+ /* Received packet offset */ -+ packet_info->offset = offset; -+ offset += packet_info->length; -+ frame_data -= packet_info->length; -+ -+ packet_info++; -+ } -+ } -+ return 1; -+ } else { -+ /* This is a workaround for in case of Transfer Complete with -+ * PktDrpSts interrupts merging - in this case Transfer complete -+ * interrupt for Isoc Out Endpoint is asserted without PktDrpSts -+ * set and with DOEPTSIZ register non zero. Investigations showed, -+ * that this happens when Out packet is dropped, but because of -+ * interrupts merging during first interrupt handling PktDrpSts -+ * bit is cleared and for next merged interrupts it is not reset. -+ * In this case SW hadles the interrupt as if PktDrpSts bit is set. -+ */ -+ if (ep->is_in) { -+ return 1; -+ } else { -+ return handle_iso_out_pkt_dropped(core_if, ep); -+ } -+ } -+} -+ -+/** -+ * This function is to handle Iso EP transfer complete interrupt -+ * -+ * @param pcd The PCD -+ * @param ep The EP for which transfer complete was asserted -+ * -+ */ -+static void complete_iso_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep) -+{ -+ dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd); -+ dwc_ep_t *dwc_ep = &ep->dwc_ep; -+ uint8_t is_last = 0; -+ -+ if (ep->dwc_ep.next_frame == 0xffffffff) { -+ DWC_WARN("Next frame is not set!\n"); -+ return; -+ } -+ -+ if (core_if->dma_enable) { -+ if (core_if->dma_desc_enable) { -+ set_ddma_iso_pkts_info(core_if, dwc_ep); -+ reinit_ddma_iso_xfer(core_if, dwc_ep); -+ is_last = 1; -+ } else { -+ if (core_if->pti_enh_enable) { -+ if (set_iso_pkts_info(core_if, dwc_ep)) { -+ dwc_ep->proc_buf_num = -+ (dwc_ep->proc_buf_num ^ 1) & 0x1; -+ dwc_otg_iso_ep_start_buf_transfer -+ (core_if, dwc_ep); -+ is_last = 1; -+ } -+ } else { -+ set_current_pkt_info(core_if, dwc_ep); -+ if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) { -+ is_last = 1; -+ dwc_ep->cur_pkt = 0; -+ dwc_ep->proc_buf_num = -+ (dwc_ep->proc_buf_num ^ 1) & 0x1; -+ if (dwc_ep->proc_buf_num) { -+ dwc_ep->cur_pkt_addr = -+ dwc_ep->xfer_buff1; -+ dwc_ep->cur_pkt_dma_addr = -+ dwc_ep->dma_addr1; -+ } else { -+ dwc_ep->cur_pkt_addr = -+ dwc_ep->xfer_buff0; -+ dwc_ep->cur_pkt_dma_addr = -+ dwc_ep->dma_addr0; -+ } -+ -+ } -+ dwc_otg_iso_ep_start_frm_transfer(core_if, -+ dwc_ep); -+ } -+ } -+ } else { -+ set_current_pkt_info(core_if, dwc_ep); -+ if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) { -+ is_last = 1; -+ dwc_ep->cur_pkt = 0; -+ dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1; -+ if (dwc_ep->proc_buf_num) { -+ dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1; -+ dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1; -+ } else { -+ dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0; -+ dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0; -+ } -+ -+ } -+ dwc_otg_iso_ep_start_frm_transfer(core_if, dwc_ep); -+ } -+ if (is_last) -+ dwc_otg_iso_buffer_done(pcd, ep, ep->iso_req_handle); -+} -+#endif /* DWC_EN_ISOC */ -+ -+/** -+ * This function handle BNA interrupt for Non Isochronous EPs -+ * -+ */ -+static void dwc_otg_pcd_handle_noniso_bna(dwc_otg_pcd_ep_t * ep) -+{ -+ dwc_ep_t *dwc_ep = &ep->dwc_ep; -+ volatile uint32_t *addr; -+ depctl_data_t depctl = {.d32 = 0 }; -+ dwc_otg_pcd_t *pcd = ep->pcd; -+ dwc_otg_dev_dma_desc_t *dma_desc; -+ dev_dma_desc_sts_t sts = {.d32 = 0 }; -+ dwc_otg_core_if_t *core_if = ep->pcd->core_if; -+ int i, start; -+ -+ if (!dwc_ep->desc_cnt) -+ DWC_WARN("Ep%d %s Descriptor count = %d \n", dwc_ep->num, -+ (dwc_ep->is_in ? "IN" : "OUT"), dwc_ep->desc_cnt); -+ -+ if (core_if->core_params->cont_on_bna && !dwc_ep->is_in -+ && dwc_ep->type != DWC_OTG_EP_TYPE_CONTROL) { -+ uint32_t doepdma; -+ dwc_otg_dev_out_ep_regs_t *out_regs = -+ core_if->dev_if->out_ep_regs[dwc_ep->num]; -+ doepdma = DWC_READ_REG32(&(out_regs->doepdma)); -+ start = (doepdma - dwc_ep->dma_desc_addr)/sizeof(dwc_otg_dev_dma_desc_t); -+ dma_desc = &(dwc_ep->desc_addr[start]); -+ } else { -+ start = 0; -+ dma_desc = dwc_ep->desc_addr; -+ } -+ -+ -+ for (i = start; i < dwc_ep->desc_cnt; ++i, ++dma_desc) { -+ sts.d32 = dma_desc->status.d32; -+ sts.b.bs = BS_HOST_READY; -+ dma_desc->status.d32 = sts.d32; -+ } -+ -+ if (dwc_ep->is_in == 0) { -+ addr = -+ &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->num]-> -+ doepctl; -+ } else { -+ addr = -+ &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl; -+ } -+ depctl.b.epena = 1; -+ depctl.b.cnak = 1; -+ DWC_MODIFY_REG32(addr, 0, depctl.d32); -+} -+ -+/** -+ * This function handles EP0 Control transfers. -+ * -+ * The state of the control transfers are tracked in -+ * ep0state. -+ */ -+static void handle_ep0(dwc_otg_pcd_t * pcd) -+{ -+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); -+ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; -+ dev_dma_desc_sts_t desc_sts; -+ deptsiz0_data_t deptsiz; -+ uint32_t byte_count; -+ -+#ifdef DEBUG_EP0 -+ DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__); -+ print_ep0_state(pcd); -+#endif -+ -+// DWC_PRINTF("HANDLE EP0\n"); -+ -+ switch (pcd->ep0state) { -+ case EP0_DISCONNECT: -+ break; -+ -+ case EP0_IDLE: -+ pcd->request_config = 0; -+ -+ pcd_setup(pcd); -+ break; -+ -+ case EP0_IN_DATA_PHASE: -+#ifdef DEBUG_EP0 -+ DWC_DEBUGPL(DBG_PCD, "DATA_IN EP%d-%s: type=%d, mps=%d\n", -+ ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"), -+ ep0->dwc_ep.type, ep0->dwc_ep.maxpacket); -+#endif -+ -+ if (core_if->dma_enable != 0) { -+ /* -+ * For EP0 we can only program 1 packet at a time so we -+ * need to do the make calculations after each complete. -+ * Call write_packet to make the calculations, as in -+ * slave mode, and use those values to determine if we -+ * can complete. -+ */ -+ if (core_if->dma_desc_enable == 0) { -+ deptsiz.d32 = -+ DWC_READ_REG32(&core_if-> -+ dev_if->in_ep_regs[0]-> -+ dieptsiz); -+ byte_count = -+ ep0->dwc_ep.xfer_len - deptsiz.b.xfersize; -+ } else { -+ desc_sts = -+ core_if->dev_if->in_desc_addr->status; -+ byte_count = -+ ep0->dwc_ep.xfer_len - desc_sts.b.bytes; -+ } -+ ep0->dwc_ep.xfer_count += byte_count; -+ ep0->dwc_ep.xfer_buff += byte_count; -+ ep0->dwc_ep.dma_addr += byte_count; -+ } -+ if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) { -+ dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd), -+ &ep0->dwc_ep); -+ DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n"); -+ } else if (ep0->dwc_ep.sent_zlp) { -+ dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd), -+ &ep0->dwc_ep); -+ ep0->dwc_ep.sent_zlp = 0; -+ DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER sent zlp\n"); -+ } else { -+ ep0_complete_request(ep0); -+ DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n"); -+ } -+ break; -+ case EP0_OUT_DATA_PHASE: -+#ifdef DEBUG_EP0 -+ DWC_DEBUGPL(DBG_PCD, "DATA_OUT EP%d-%s: type=%d, mps=%d\n", -+ ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"), -+ ep0->dwc_ep.type, ep0->dwc_ep.maxpacket); -+#endif -+ if (core_if->dma_enable != 0) { -+ if (core_if->dma_desc_enable == 0) { -+ deptsiz.d32 = -+ DWC_READ_REG32(&core_if-> -+ dev_if->out_ep_regs[0]-> -+ doeptsiz); -+ byte_count = -+ ep0->dwc_ep.maxpacket - deptsiz.b.xfersize; -+ } else { -+ desc_sts = -+ core_if->dev_if->out_desc_addr->status; -+ byte_count = -+ ep0->dwc_ep.maxpacket - desc_sts.b.bytes; -+ } -+ ep0->dwc_ep.xfer_count += byte_count; -+ ep0->dwc_ep.xfer_buff += byte_count; -+ ep0->dwc_ep.dma_addr += byte_count; -+ } -+ if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) { -+ dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd), -+ &ep0->dwc_ep); -+ DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n"); -+ } else if (ep0->dwc_ep.sent_zlp) { -+ dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd), -+ &ep0->dwc_ep); -+ ep0->dwc_ep.sent_zlp = 0; -+ DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER sent zlp\n"); -+ } else { -+ ep0_complete_request(ep0); -+ DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n"); -+ } -+ break; -+ -+ case EP0_IN_STATUS_PHASE: -+ case EP0_OUT_STATUS_PHASE: -+ DWC_DEBUGPL(DBG_PCD, "CASE: EP0_STATUS\n"); -+ ep0_complete_request(ep0); -+ pcd->ep0state = EP0_IDLE; -+ ep0->stopped = 1; -+ ep0->dwc_ep.is_in = 0; /* OUT for next SETUP */ -+ -+ /* Prepare for more SETUP Packets */ -+ if (core_if->dma_enable) { -+ ep0_out_start(core_if, pcd); -+ } -+ break; -+ -+ case EP0_STALL: -+ DWC_ERROR("EP0 STALLed, should not get here pcd_setup()\n"); -+ break; -+ } -+#ifdef DEBUG_EP0 -+ print_ep0_state(pcd); -+#endif -+} -+ -+/** -+ * Restart transfer -+ */ -+static void restart_transfer(dwc_otg_pcd_t * pcd, const uint32_t epnum) -+{ -+ dwc_otg_core_if_t *core_if; -+ dwc_otg_dev_if_t *dev_if; -+ deptsiz_data_t dieptsiz = {.d32 = 0 }; -+ dwc_otg_pcd_ep_t *ep; -+ -+ ep = get_in_ep(pcd, epnum); -+ -+#ifdef DWC_EN_ISOC -+ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) { -+ return; -+ } -+#endif /* DWC_EN_ISOC */ -+ -+ core_if = GET_CORE_IF(pcd); -+ dev_if = core_if->dev_if; -+ -+ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dieptsiz); -+ -+ DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x xfer_len=%0x" -+ " stopped=%d\n", ep->dwc_ep.xfer_buff, -+ ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len, ep->stopped); -+ /* -+ * If xfersize is 0 and pktcnt in not 0, resend the last packet. -+ */ -+ if (dieptsiz.b.pktcnt && dieptsiz.b.xfersize == 0 && -+ ep->dwc_ep.start_xfer_buff != 0) { -+ if (ep->dwc_ep.total_len <= ep->dwc_ep.maxpacket) { -+ ep->dwc_ep.xfer_count = 0; -+ ep->dwc_ep.xfer_buff = ep->dwc_ep.start_xfer_buff; -+ ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count; -+ } else { -+ ep->dwc_ep.xfer_count -= ep->dwc_ep.maxpacket; -+ /* convert packet size to dwords. */ -+ ep->dwc_ep.xfer_buff -= ep->dwc_ep.maxpacket; -+ ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count; -+ } -+ ep->stopped = 0; -+ DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x " -+ "xfer_len=%0x stopped=%d\n", -+ ep->dwc_ep.xfer_buff, -+ ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len, -+ ep->stopped); -+ if (epnum == 0) { -+ dwc_otg_ep0_start_transfer(core_if, &ep->dwc_ep); -+ } else { -+ dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep); -+ } -+ } -+} -+ -+/* -+ * This function create new nextep sequnce based on Learn Queue. -+ * -+ * @param core_if Programming view of DWC_otg controller -+ */ -+void predict_nextep_seq( dwc_otg_core_if_t * core_if) -+{ -+ dwc_otg_device_global_regs_t *dev_global_regs = -+ core_if->dev_if->dev_global_regs; -+ const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth; -+ /* Number of Token Queue Registers */ -+ const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8; -+ dtknq1_data_t dtknqr1; -+ uint32_t in_tkn_epnums[4]; -+ uint8_t seqnum[MAX_EPS_CHANNELS]; -+ uint8_t intkn_seq[TOKEN_Q_DEPTH]; -+ grstctl_t resetctl = {.d32 = 0 }; -+ uint8_t temp; -+ int ndx = 0; -+ int start = 0; -+ int end = 0; -+ int sort_done = 0; -+ int i = 0; -+ volatile uint32_t *addr = &dev_global_regs->dtknqr1; -+ -+ -+ DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH); -+ -+ /* Read the DTKNQ Registers */ -+ for (i = 0; i < DTKNQ_REG_CNT; i++) { -+ in_tkn_epnums[i] = DWC_READ_REG32(addr); -+ DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i + 1, -+ in_tkn_epnums[i]); -+ if (addr == &dev_global_regs->dvbusdis) { -+ addr = &dev_global_regs->dtknqr3_dthrctl; -+ } else { -+ ++addr; -+ } -+ -+ } -+ -+ /* Copy the DTKNQR1 data to the bit field. */ -+ dtknqr1.d32 = in_tkn_epnums[0]; -+ if (dtknqr1.b.wrap_bit) { -+ ndx = dtknqr1.b.intknwptr; -+ end = ndx -1; -+ if (end < 0) -+ end = TOKEN_Q_DEPTH -1; -+ } else { -+ ndx = 0; -+ end = dtknqr1.b.intknwptr -1; -+ if (end < 0) -+ end = 0; -+ } -+ start = ndx; -+ -+ /* Fill seqnum[] by initial values: EP number + 31 */ -+ for (i=0; i <= core_if->dev_if->num_in_eps; i++) { -+ seqnum[i] = i +31; -+ } -+ -+ /* Fill intkn_seq[] from in_tkn_epnums[0] */ -+ for (i=0; i < 6; i++) -+ intkn_seq[i] = (in_tkn_epnums[0] >> ((7-i) * 4)) & 0xf; -+ -+ if (TOKEN_Q_DEPTH > 6) { -+ /* Fill intkn_seq[] from in_tkn_epnums[1] */ -+ for (i=6; i < 14; i++) -+ intkn_seq[i] = -+ (in_tkn_epnums[1] >> ((7 - (i - 6)) * 4)) & 0xf; -+ } -+ -+ if (TOKEN_Q_DEPTH > 14) { -+ /* Fill intkn_seq[] from in_tkn_epnums[1] */ -+ for (i=14; i < 22; i++) -+ intkn_seq[i] = -+ (in_tkn_epnums[2] >> ((7 - (i - 14)) * 4)) & 0xf; -+ } -+ -+ if (TOKEN_Q_DEPTH > 22) { -+ /* Fill intkn_seq[] from in_tkn_epnums[1] */ -+ for (i=22; i < 30; i++) -+ intkn_seq[i] = -+ (in_tkn_epnums[3] >> ((7 - (i - 22)) * 4)) & 0xf; -+ } -+ -+ DWC_DEBUGPL(DBG_PCDV, "%s start=%d end=%d intkn_seq[]:\n", __func__, -+ start, end); -+ for (i=0; idev_if->num_in_eps; i++) { -+ if (core_if->nextep_seq[i] == 0xff ) -+ seqnum[i] = 0xff; -+ } -+ -+ /* Sort seqnum[] */ -+ sort_done = 0; -+ while (!sort_done) { -+ sort_done = 1; -+ for (i=0; idev_if->num_in_eps; i++) { -+ if (seqnum[i] > seqnum[i+1]) { -+ temp = seqnum[i]; -+ seqnum[i] = seqnum[i+1]; -+ seqnum[i+1] = temp; -+ sort_done = 0; -+ } -+ } -+ } -+ -+ ndx = start + seqnum[0]; -+ if (ndx >= TOKEN_Q_DEPTH) -+ ndx = ndx % TOKEN_Q_DEPTH; -+ core_if->first_in_nextep_seq = intkn_seq[ndx]; -+ -+ /* Update seqnum[] by EP numbers */ -+ for (i=0; i<=core_if->dev_if->num_in_eps; i++) { -+ ndx = start + i; -+ if (seqnum[i] < 31) { -+ ndx = start + seqnum[i]; -+ if (ndx >= TOKEN_Q_DEPTH) -+ ndx = ndx % TOKEN_Q_DEPTH; -+ seqnum[i] = intkn_seq[ndx]; -+ } else { -+ if (seqnum[i] < 0xff) { -+ seqnum[i] = seqnum[i] - 31; -+ } else { -+ break; -+ } -+ } -+ } -+ -+ /* Update nextep_seq[] based on seqnum[] */ -+ for (i=0; idev_if->num_in_eps; i++) { -+ if (seqnum[i] != 0xff) { -+ if (seqnum[i+1] != 0xff) { -+ core_if->nextep_seq[seqnum[i]] = seqnum[i+1]; -+ } else { -+ core_if->nextep_seq[seqnum[i]] = core_if->first_in_nextep_seq; -+ break; -+ } -+ } else { -+ break; -+ } -+ } -+ -+ DWC_DEBUGPL(DBG_PCDV, "%s first_in_nextep_seq= %2d; nextep_seq[]:\n", -+ __func__, core_if->first_in_nextep_seq); -+ for (i=0; i <= core_if->dev_if->num_in_eps; i++) { -+ DWC_DEBUGPL(DBG_PCDV,"%2d\n", core_if->nextep_seq[i]); -+ } -+ -+ /* Flush the Learning Queue */ -+ resetctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->grstctl); -+ resetctl.b.intknqflsh = 1; -+ DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32); -+ -+ -+} -+ -+/** -+ * handle the IN EP disable interrupt. -+ */ -+static inline void handle_in_ep_disable_intr(dwc_otg_pcd_t * pcd, -+ const uint32_t epnum) -+{ -+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); -+ dwc_otg_dev_if_t *dev_if = core_if->dev_if; -+ deptsiz_data_t dieptsiz = {.d32 = 0 }; -+ dctl_data_t dctl = {.d32 = 0 }; -+ dwc_otg_pcd_ep_t *ep; -+ dwc_ep_t *dwc_ep; -+ gintmsk_data_t gintmsk_data; -+ depctl_data_t depctl; -+ uint32_t diepdma; -+ uint32_t remain_to_transfer = 0; -+ uint8_t i; -+ uint32_t xfer_size; -+ -+ ep = get_in_ep(pcd, epnum); -+ dwc_ep = &ep->dwc_ep; -+ -+ if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { -+ dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num); -+ complete_ep(ep); -+ return; -+ } -+ -+ DWC_DEBUGPL(DBG_PCD, "diepctl%d=%0x\n", epnum, -+ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl)); -+ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dieptsiz); -+ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl); -+ -+ DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n", -+ dieptsiz.b.pktcnt, dieptsiz.b.xfersize); -+ -+ if ((core_if->start_predict == 0) || (depctl.b.eptype & 1)) { -+ if (ep->stopped) { -+ if (core_if->en_multiple_tx_fifo) -+ /* Flush the Tx FIFO */ -+ dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num); -+ /* Clear the Global IN NP NAK */ -+ dctl.d32 = 0; -+ dctl.b.cgnpinnak = 1; -+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); -+ /* Restart the transaction */ -+ if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) { -+ restart_transfer(pcd, epnum); -+ } -+ } else { -+ /* Restart the transaction */ -+ if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) { -+ restart_transfer(pcd, epnum); -+ } -+ DWC_DEBUGPL(DBG_ANY, "STOPPED!!!\n"); -+ } -+ return; -+ } -+ -+ if (core_if->start_predict > 2) { // NP IN EP -+ core_if->start_predict--; -+ return; -+ } -+ -+ core_if->start_predict--; -+ -+ if (core_if->start_predict == 1) { // All NP IN Ep's disabled now -+ -+ predict_nextep_seq(core_if); -+ -+ /* Update all active IN EP's NextEP field based of nextep_seq[] */ -+ for ( i = 0; i <= core_if->dev_if->num_in_eps; i++) { -+ depctl.d32 = -+ DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); -+ if (core_if->nextep_seq[i] != 0xff) { // Active NP IN EP -+ depctl.b.nextep = core_if->nextep_seq[i]; -+ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32); -+ } -+ } -+ /* Flush Shared NP TxFIFO */ -+ dwc_otg_flush_tx_fifo(core_if, 0); -+ /* Rewind buffers */ -+ if (!core_if->dma_desc_enable) { -+ i = core_if->first_in_nextep_seq; -+ do { -+ ep = get_in_ep(pcd, i); -+ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz); -+ xfer_size = ep->dwc_ep.total_len - ep->dwc_ep.xfer_count; -+ if (xfer_size > ep->dwc_ep.maxxfer) -+ xfer_size = ep->dwc_ep.maxxfer; -+ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); -+ if (dieptsiz.b.pktcnt != 0) { -+ if (xfer_size == 0) { -+ remain_to_transfer = 0; -+ } else { -+ if ((xfer_size % ep->dwc_ep.maxpacket) == 0) { -+ remain_to_transfer = -+ dieptsiz.b.pktcnt * ep->dwc_ep.maxpacket; -+ } else { -+ remain_to_transfer = ((dieptsiz.b.pktcnt -1) * ep->dwc_ep.maxpacket) -+ + (xfer_size % ep->dwc_ep.maxpacket); -+ } -+ } -+ diepdma = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepdma); -+ dieptsiz.b.xfersize = remain_to_transfer; -+ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, dieptsiz.d32); -+ diepdma = ep->dwc_ep.dma_addr + (xfer_size - remain_to_transfer); -+ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, diepdma); -+ } -+ i = core_if->nextep_seq[i]; -+ } while (i != core_if->first_in_nextep_seq); -+ } else { // dma_desc_enable -+ DWC_PRINTF("%s Learning Queue not supported in DDMA\n", __func__); -+ } -+ -+ /* Restart transfers in predicted sequences */ -+ i = core_if->first_in_nextep_seq; -+ do { -+ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz); -+ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); -+ if (dieptsiz.b.pktcnt != 0) { -+ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); -+ depctl.b.epena = 1; -+ depctl.b.cnak = 1; -+ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32); -+ } -+ i = core_if->nextep_seq[i]; -+ } while (i != core_if->first_in_nextep_seq); -+ -+ /* Clear the global non-periodic IN NAK handshake */ -+ dctl.d32 = 0; -+ dctl.b.cgnpinnak = 1; -+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); -+ -+ /* Unmask EP Mismatch interrupt */ -+ gintmsk_data.d32 = 0; -+ gintmsk_data.b.epmismatch = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, gintmsk_data.d32); -+ -+ core_if->start_predict = 0; -+ -+ } -+} -+ -+/** -+ * Handler for the IN EP timeout handshake interrupt. -+ */ -+static inline void handle_in_ep_timeout_intr(dwc_otg_pcd_t * pcd, -+ const uint32_t epnum) -+{ -+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); -+ dwc_otg_dev_if_t *dev_if = core_if->dev_if; -+ -+#ifdef DEBUG -+ deptsiz_data_t dieptsiz = {.d32 = 0 }; -+ uint32_t num = 0; -+#endif -+ dctl_data_t dctl = {.d32 = 0 }; -+ dwc_otg_pcd_ep_t *ep; -+ -+ gintmsk_data_t intr_mask = {.d32 = 0 }; -+ -+ ep = get_in_ep(pcd, epnum); -+ -+ /* Disable the NP Tx Fifo Empty Interrrupt */ -+ if (!core_if->dma_enable) { -+ intr_mask.b.nptxfempty = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, -+ intr_mask.d32, 0); -+ } -+ /** @todo NGS Check EP type. -+ * Implement for Periodic EPs */ -+ /* -+ * Non-periodic EP -+ */ -+ /* Enable the Global IN NAK Effective Interrupt */ -+ intr_mask.b.ginnakeff = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32); -+ -+ /* Set Global IN NAK */ -+ dctl.b.sgnpinnak = 1; -+ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); -+ -+ ep->stopped = 1; -+ -+#ifdef DEBUG -+ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[num]->dieptsiz); -+ DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n", -+ dieptsiz.b.pktcnt, dieptsiz.b.xfersize); -+#endif -+ -+#ifdef DISABLE_PERIODIC_EP -+ /* -+ * Set the NAK bit for this EP to -+ * start the disable process. -+ */ -+ diepctl.d32 = 0; -+ diepctl.b.snak = 1; -+ DWC_MODIFY_REG32(&dev_if->in_ep_regs[num]->diepctl, diepctl.d32, -+ diepctl.d32); -+ ep->disabling = 1; -+ ep->stopped = 1; -+#endif -+} -+ -+/** -+ * Handler for the IN EP NAK interrupt. -+ */ -+static inline int32_t handle_in_ep_nak_intr(dwc_otg_pcd_t * pcd, -+ const uint32_t epnum) -+{ -+ /** @todo implement ISR */ -+ dwc_otg_core_if_t *core_if; -+ diepmsk_data_t intr_mask = {.d32 = 0 }; -+ -+ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "IN EP NAK"); -+ core_if = GET_CORE_IF(pcd); -+ intr_mask.b.nak = 1; -+ -+ if (core_if->multiproc_int_enable) { -+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> -+ diepeachintmsk[epnum], intr_mask.d32, 0); -+ } else { -+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->diepmsk, -+ intr_mask.d32, 0); -+ } -+ -+ return 1; -+} -+ -+/** -+ * Handler for the OUT EP Babble interrupt. -+ */ -+static inline int32_t handle_out_ep_babble_intr(dwc_otg_pcd_t * pcd, -+ const uint32_t epnum) -+{ -+ /** @todo implement ISR */ -+ dwc_otg_core_if_t *core_if; -+ doepmsk_data_t intr_mask = {.d32 = 0 }; -+ -+ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", -+ "OUT EP Babble"); -+ core_if = GET_CORE_IF(pcd); -+ intr_mask.b.babble = 1; -+ -+ if (core_if->multiproc_int_enable) { -+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> -+ doepeachintmsk[epnum], intr_mask.d32, 0); -+ } else { -+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk, -+ intr_mask.d32, 0); -+ } -+ -+ return 1; -+} -+ -+/** -+ * Handler for the OUT EP NAK interrupt. -+ */ -+static inline int32_t handle_out_ep_nak_intr(dwc_otg_pcd_t * pcd, -+ const uint32_t epnum) -+{ -+ /** @todo implement ISR */ -+ dwc_otg_core_if_t *core_if; -+ doepmsk_data_t intr_mask = {.d32 = 0 }; -+ -+ DWC_DEBUGPL(DBG_ANY, "INTERRUPT Handler not implemented for %s\n", "OUT EP NAK"); -+ core_if = GET_CORE_IF(pcd); -+ intr_mask.b.nak = 1; -+ -+ if (core_if->multiproc_int_enable) { -+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> -+ doepeachintmsk[epnum], intr_mask.d32, 0); -+ } else { -+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk, -+ intr_mask.d32, 0); -+ } -+ -+ return 1; -+} -+ -+/** -+ * Handler for the OUT EP NYET interrupt. -+ */ -+static inline int32_t handle_out_ep_nyet_intr(dwc_otg_pcd_t * pcd, -+ const uint32_t epnum) -+{ -+ /** @todo implement ISR */ -+ dwc_otg_core_if_t *core_if; -+ doepmsk_data_t intr_mask = {.d32 = 0 }; -+ -+ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "OUT EP NYET"); -+ core_if = GET_CORE_IF(pcd); -+ intr_mask.b.nyet = 1; -+ -+ if (core_if->multiproc_int_enable) { -+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> -+ doepeachintmsk[epnum], intr_mask.d32, 0); -+ } else { -+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk, -+ intr_mask.d32, 0); -+ } -+ -+ return 1; -+} -+ -+/** -+ * This interrupt indicates that an IN EP has a pending Interrupt. -+ * The sequence for handling the IN EP interrupt is shown below: -+ * -# Read the Device All Endpoint Interrupt register -+ * -# Repeat the following for each IN EP interrupt bit set (from -+ * LSB to MSB). -+ * -# Read the Device Endpoint Interrupt (DIEPINTn) register -+ * -# If "Transfer Complete" call the request complete function -+ * -# If "Endpoint Disabled" complete the EP disable procedure. -+ * -# If "AHB Error Interrupt" log error -+ * -# If "Time-out Handshake" log error -+ * -# If "IN Token Received when TxFIFO Empty" write packet to Tx -+ * FIFO. -+ * -# If "IN Token EP Mismatch" (disable, this is handled by EP -+ * Mismatch Interrupt) -+ */ -+static int32_t dwc_otg_pcd_handle_in_ep_intr(dwc_otg_pcd_t * pcd) -+{ -+#define CLEAR_IN_EP_INTR(__core_if,__epnum,__intr) \ -+do { \ -+ diepint_data_t diepint = {.d32=0}; \ -+ diepint.b.__intr = 1; \ -+ DWC_WRITE_REG32(&__core_if->dev_if->in_ep_regs[__epnum]->diepint, \ -+ diepint.d32); \ -+} while (0) -+ -+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); -+ dwc_otg_dev_if_t *dev_if = core_if->dev_if; -+ diepint_data_t diepint = {.d32 = 0 }; -+ depctl_data_t depctl = {.d32 = 0 }; -+ uint32_t ep_intr; -+ uint32_t epnum = 0; -+ dwc_otg_pcd_ep_t *ep; -+ dwc_ep_t *dwc_ep; -+ gintmsk_data_t intr_mask = {.d32 = 0 }; -+ -+ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, pcd); -+ -+ /* Read in the device interrupt bits */ -+ ep_intr = dwc_otg_read_dev_all_in_ep_intr(core_if); -+ -+ /* Service the Device IN interrupts for each endpoint */ -+ while (ep_intr) { -+ if (ep_intr & 0x1) { -+ uint32_t empty_msk; -+ /* Get EP pointer */ -+ ep = get_in_ep(pcd, epnum); -+ dwc_ep = &ep->dwc_ep; -+ -+ depctl.d32 = -+ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl); -+ empty_msk = -+ DWC_READ_REG32(&dev_if-> -+ dev_global_regs->dtknqr4_fifoemptymsk); -+ -+ DWC_DEBUGPL(DBG_PCDV, -+ "IN EP INTERRUPT - %d\nepmty_msk - %8x diepctl - %8x\n", -+ epnum, empty_msk, depctl.d32); -+ -+ DWC_DEBUGPL(DBG_PCD, -+ "EP%d-%s: type=%d, mps=%d\n", -+ dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"), -+ dwc_ep->type, dwc_ep->maxpacket); -+ -+ diepint.d32 = -+ dwc_otg_read_dev_in_ep_intr(core_if, dwc_ep); -+ -+ DWC_DEBUGPL(DBG_PCDV, -+ "EP %d Interrupt Register - 0x%x\n", epnum, -+ diepint.d32); -+ /* Transfer complete */ -+ if (diepint.b.xfercompl) { -+ /* Disable the NP Tx FIFO Empty -+ * Interrupt */ -+ if (core_if->en_multiple_tx_fifo == 0) { -+ intr_mask.b.nptxfempty = 1; -+ DWC_MODIFY_REG32 -+ (&core_if->core_global_regs->gintmsk, -+ intr_mask.d32, 0); -+ } else { -+ /* Disable the Tx FIFO Empty Interrupt for this EP */ -+ uint32_t fifoemptymsk = -+ 0x1 << dwc_ep->num; -+ DWC_MODIFY_REG32(&core_if-> -+ dev_if->dev_global_regs->dtknqr4_fifoemptymsk, -+ fifoemptymsk, 0); -+ } -+ /* Clear the bit in DIEPINTn for this interrupt */ -+ CLEAR_IN_EP_INTR(core_if, epnum, xfercompl); -+ -+ /* Complete the transfer */ -+ if (epnum == 0) { -+ handle_ep0(pcd); -+ } -+#ifdef DWC_EN_ISOC -+ else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { -+ if (!ep->stopped) -+ complete_iso_ep(pcd, ep); -+ } -+#endif /* DWC_EN_ISOC */ -+#ifdef DWC_UTE_PER_IO -+ else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { -+ if (!ep->stopped) -+ complete_xiso_ep(ep); -+ } -+#endif /* DWC_UTE_PER_IO */ -+ else { -+ if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC && -+ dwc_ep->bInterval > 1) { -+ dwc_ep->frame_num += dwc_ep->bInterval; -+ if (dwc_ep->frame_num > 0x3FFF) -+ { -+ dwc_ep->frm_overrun = 1; -+ dwc_ep->frame_num &= 0x3FFF; -+ } else -+ dwc_ep->frm_overrun = 0; -+ } -+ complete_ep(ep); -+ if(diepint.b.nak) -+ CLEAR_IN_EP_INTR(core_if, epnum, nak); -+ } -+ } -+ /* Endpoint disable */ -+ if (diepint.b.epdisabled) { -+ DWC_DEBUGPL(DBG_ANY, "EP%d IN disabled\n", -+ epnum); -+ handle_in_ep_disable_intr(pcd, epnum); -+ -+ /* Clear the bit in DIEPINTn for this interrupt */ -+ CLEAR_IN_EP_INTR(core_if, epnum, epdisabled); -+ } -+ /* AHB Error */ -+ if (diepint.b.ahberr) { -+ DWC_ERROR("EP%d IN AHB Error\n", epnum); -+ /* Clear the bit in DIEPINTn for this interrupt */ -+ CLEAR_IN_EP_INTR(core_if, epnum, ahberr); -+ } -+ /* TimeOUT Handshake (non-ISOC IN EPs) */ -+ if (diepint.b.timeout) { -+ DWC_ERROR("EP%d IN Time-out\n", epnum); -+ handle_in_ep_timeout_intr(pcd, epnum); -+ -+ CLEAR_IN_EP_INTR(core_if, epnum, timeout); -+ } -+ /** IN Token received with TxF Empty */ -+ if (diepint.b.intktxfemp) { -+ DWC_DEBUGPL(DBG_ANY, -+ "EP%d IN TKN TxFifo Empty\n", -+ epnum); -+ if (!ep->stopped && epnum != 0) { -+ -+ diepmsk_data_t diepmsk = {.d32 = 0 }; -+ diepmsk.b.intktxfemp = 1; -+ -+ if (core_if->multiproc_int_enable) { -+ DWC_MODIFY_REG32 -+ (&dev_if->dev_global_regs->diepeachintmsk -+ [epnum], diepmsk.d32, 0); -+ } else { -+ DWC_MODIFY_REG32 -+ (&dev_if->dev_global_regs->diepmsk, -+ diepmsk.d32, 0); -+ } -+ } else if (core_if->dma_desc_enable -+ && epnum == 0 -+ && pcd->ep0state == -+ EP0_OUT_STATUS_PHASE) { -+ // EP0 IN set STALL -+ depctl.d32 = -+ DWC_READ_REG32(&dev_if->in_ep_regs -+ [epnum]->diepctl); -+ -+ /* set the disable and stall bits */ -+ if (depctl.b.epena) { -+ depctl.b.epdis = 1; -+ } -+ depctl.b.stall = 1; -+ DWC_WRITE_REG32(&dev_if->in_ep_regs -+ [epnum]->diepctl, -+ depctl.d32); -+ } -+ CLEAR_IN_EP_INTR(core_if, epnum, intktxfemp); -+ } -+ /** IN Token Received with EP mismatch */ -+ if (diepint.b.intknepmis) { -+ DWC_DEBUGPL(DBG_ANY, -+ "EP%d IN TKN EP Mismatch\n", epnum); -+ CLEAR_IN_EP_INTR(core_if, epnum, intknepmis); -+ } -+ /** IN Endpoint NAK Effective */ -+ if (diepint.b.inepnakeff) { -+ DWC_DEBUGPL(DBG_ANY, -+ "EP%d IN EP NAK Effective\n", -+ epnum); -+ /* Periodic EP */ -+ if (ep->disabling) { -+ depctl.d32 = 0; -+ depctl.b.snak = 1; -+ depctl.b.epdis = 1; -+ DWC_MODIFY_REG32(&dev_if->in_ep_regs -+ [epnum]->diepctl, -+ depctl.d32, -+ depctl.d32); -+ } -+ CLEAR_IN_EP_INTR(core_if, epnum, inepnakeff); -+ -+ } -+ -+ /** IN EP Tx FIFO Empty Intr */ -+ if (diepint.b.emptyintr) { -+ DWC_DEBUGPL(DBG_ANY, -+ "EP%d Tx FIFO Empty Intr \n", -+ epnum); -+ write_empty_tx_fifo(pcd, epnum); -+ -+ CLEAR_IN_EP_INTR(core_if, epnum, emptyintr); -+ -+ } -+ -+ /** IN EP BNA Intr */ -+ if (diepint.b.bna) { -+ CLEAR_IN_EP_INTR(core_if, epnum, bna); -+ if (core_if->dma_desc_enable) { -+#ifdef DWC_EN_ISOC -+ if (dwc_ep->type == -+ DWC_OTG_EP_TYPE_ISOC) { -+ /* -+ * This checking is performed to prevent first "false" BNA -+ * handling occuring right after reconnect -+ */ -+ if (dwc_ep->next_frame != -+ 0xffffffff) -+ dwc_otg_pcd_handle_iso_bna(ep); -+ } else -+#endif /* DWC_EN_ISOC */ -+ { -+ dwc_otg_pcd_handle_noniso_bna(ep); -+ } -+ } -+ } -+ /* NAK Interrutp */ -+ if (diepint.b.nak) { -+ DWC_DEBUGPL(DBG_ANY, "EP%d IN NAK Interrupt\n", -+ epnum); -+ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) { -+ depctl_data_t depctl; -+ if (ep->dwc_ep.frame_num == 0xFFFFFFFF) { -+ ep->dwc_ep.frame_num = core_if->frame_num; -+ if (ep->dwc_ep.bInterval > 1) { -+ depctl.d32 = 0; -+ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl); -+ if (ep->dwc_ep.frame_num & 0x1) { -+ depctl.b.setd1pid = 1; -+ depctl.b.setd0pid = 0; -+ } else { -+ depctl.b.setd0pid = 1; -+ depctl.b.setd1pid = 0; -+ } -+ DWC_WRITE_REG32(&dev_if->in_ep_regs[epnum]->diepctl, depctl.d32); -+ } -+ start_next_request(ep); -+ } -+ ep->dwc_ep.frame_num += ep->dwc_ep.bInterval; -+ if (dwc_ep->frame_num > 0x3FFF) { -+ dwc_ep->frm_overrun = 1; -+ dwc_ep->frame_num &= 0x3FFF; -+ } else -+ dwc_ep->frm_overrun = 0; -+ } -+ -+ CLEAR_IN_EP_INTR(core_if, epnum, nak); -+ } -+ } -+ epnum++; -+ ep_intr >>= 1; -+ } -+ -+ return 1; -+#undef CLEAR_IN_EP_INTR -+} -+ -+/** -+ * This interrupt indicates that an OUT EP has a pending Interrupt. -+ * The sequence for handling the OUT EP interrupt is shown below: -+ * -# Read the Device All Endpoint Interrupt register -+ * -# Repeat the following for each OUT EP interrupt bit set (from -+ * LSB to MSB). -+ * -# Read the Device Endpoint Interrupt (DOEPINTn) register -+ * -# If "Transfer Complete" call the request complete function -+ * -# If "Endpoint Disabled" complete the EP disable procedure. -+ * -# If "AHB Error Interrupt" log error -+ * -# If "Setup Phase Done" process Setup Packet (See Standard USB -+ * Command Processing) -+ */ -+static int32_t dwc_otg_pcd_handle_out_ep_intr(dwc_otg_pcd_t * pcd) -+{ -+#define CLEAR_OUT_EP_INTR(__core_if,__epnum,__intr) \ -+do { \ -+ doepint_data_t doepint = {.d32=0}; \ -+ doepint.b.__intr = 1; \ -+ DWC_WRITE_REG32(&__core_if->dev_if->out_ep_regs[__epnum]->doepint, \ -+ doepint.d32); \ -+} while (0) -+ -+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); -+ uint32_t ep_intr; -+ doepint_data_t doepint = {.d32 = 0 }; -+ uint32_t epnum = 0; -+ dwc_otg_pcd_ep_t *ep; -+ dwc_ep_t *dwc_ep; -+ dctl_data_t dctl = {.d32 = 0 }; -+ gintmsk_data_t gintmsk = {.d32 = 0 }; -+ -+ -+ DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__); -+ -+ /* Read in the device interrupt bits */ -+ ep_intr = dwc_otg_read_dev_all_out_ep_intr(core_if); -+ -+ while (ep_intr) { -+ if (ep_intr & 0x1) { -+ /* Get EP pointer */ -+ ep = get_out_ep(pcd, epnum); -+ dwc_ep = &ep->dwc_ep; -+ -+#ifdef VERBOSE -+ DWC_DEBUGPL(DBG_PCDV, -+ "EP%d-%s: type=%d, mps=%d\n", -+ dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"), -+ dwc_ep->type, dwc_ep->maxpacket); -+#endif -+ doepint.d32 = -+ dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep); -+ /* Moved this interrupt upper due to core deffect of asserting -+ * OUT EP 0 xfercompl along with stsphsrcvd in BDMA */ -+ if (doepint.b.stsphsercvd) { -+ deptsiz0_data_t deptsiz; -+ CLEAR_OUT_EP_INTR(core_if, epnum, stsphsercvd); -+ deptsiz.d32 = -+ DWC_READ_REG32(&core_if->dev_if-> -+ out_ep_regs[0]->doeptsiz); -+ if (core_if->snpsid >= OTG_CORE_REV_3_00a -+ && core_if->dma_enable -+ && core_if->dma_desc_enable == 0 -+ && doepint.b.xfercompl -+ && deptsiz.b.xfersize == 24) { -+ CLEAR_OUT_EP_INTR(core_if, epnum, -+ xfercompl); -+ doepint.b.xfercompl = 0; -+ ep0_out_start(core_if, pcd); -+ } -+ if ((core_if->dma_desc_enable) || -+ (core_if->dma_enable -+ && core_if->snpsid >= -+ OTG_CORE_REV_3_00a)) { -+ do_setup_in_status_phase(pcd); -+ } -+ } -+ /* Transfer complete */ -+ if (doepint.b.xfercompl) { -+ -+ if (epnum == 0) { -+ /* Clear the bit in DOEPINTn for this interrupt */ -+ CLEAR_OUT_EP_INTR(core_if, epnum, xfercompl); -+ if (core_if->snpsid >= OTG_CORE_REV_3_00a) { -+ DWC_DEBUGPL(DBG_PCDV, "DOEPINT=%x doepint=%x\n", -+ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[0]->doepint), -+ doepint.d32); -+ DWC_DEBUGPL(DBG_PCDV, "DOEPCTL=%x \n", -+ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[0]->doepctl)); -+ -+ if (core_if->snpsid >= OTG_CORE_REV_3_00a -+ && core_if->dma_enable == 0) { -+ doepint_data_t doepint; -+ doepint.d32 = DWC_READ_REG32(&core_if->dev_if-> -+ out_ep_regs[0]->doepint); -+ if (pcd->ep0state == EP0_IDLE && doepint.b.sr) { -+ CLEAR_OUT_EP_INTR(core_if, epnum, sr); -+ goto exit_xfercompl; -+ } -+ } -+ /* In case of DDMA look at SR bit to go to the Data Stage */ -+ if (core_if->dma_desc_enable) { -+ dev_dma_desc_sts_t status = {.d32 = 0}; -+ if (pcd->ep0state == EP0_IDLE) { -+ status.d32 = core_if->dev_if->setup_desc_addr[core_if-> -+ dev_if->setup_desc_index]->status.d32; -+ if(pcd->data_terminated) { -+ pcd->data_terminated = 0; -+ status.d32 = core_if->dev_if->out_desc_addr->status.d32; -+ dwc_memcpy(&pcd->setup_pkt->req, pcd->backup_buf, 8); -+ } -+ if (status.b.sr) { -+ if (doepint.b.setup) { -+ DWC_DEBUGPL(DBG_PCDV, "DMA DESC EP0_IDLE SR=1 setup=1\n"); -+ /* Already started data stage, clear setup */ -+ CLEAR_OUT_EP_INTR(core_if, epnum, setup); -+ doepint.b.setup = 0; -+ handle_ep0(pcd); -+ /* Prepare for more setup packets */ -+ if (pcd->ep0state == EP0_IN_STATUS_PHASE || -+ pcd->ep0state == EP0_IN_DATA_PHASE) { -+ ep0_out_start(core_if, pcd); -+ } -+ -+ goto exit_xfercompl; -+ } else { -+ /* Prepare for more setup packets */ -+ DWC_DEBUGPL(DBG_PCDV, -+ "EP0_IDLE SR=1 setup=0 new setup comes\n"); -+ ep0_out_start(core_if, pcd); -+ } -+ } -+ } else { -+ dwc_otg_pcd_request_t *req; -+ dev_dma_desc_sts_t status = {.d32 = 0}; -+ diepint_data_t diepint0; -+ diepint0.d32 = DWC_READ_REG32(&core_if->dev_if-> -+ in_ep_regs[0]->diepint); -+ -+ if (pcd->ep0state == EP0_STALL || pcd->ep0state == EP0_DISCONNECT) { -+ DWC_ERROR("EP0 is stalled/disconnected\n"); -+ } -+ -+ /* Clear IN xfercompl if set */ -+ if (diepint0.b.xfercompl && (pcd->ep0state == EP0_IN_STATUS_PHASE -+ || pcd->ep0state == EP0_IN_DATA_PHASE)) { -+ DWC_WRITE_REG32(&core_if->dev_if-> -+ in_ep_regs[0]->diepint, diepint0.d32); -+ } -+ -+ status.d32 = core_if->dev_if->setup_desc_addr[core_if-> -+ dev_if->setup_desc_index]->status.d32; -+ -+ if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len -+ && (pcd->ep0state == EP0_OUT_DATA_PHASE)) -+ status.d32 = core_if->dev_if->out_desc_addr->status.d32; -+ if (pcd->ep0state == EP0_OUT_STATUS_PHASE) -+ status.d32 = core_if->dev_if-> -+ out_desc_addr->status.d32; -+ -+ if (status.b.sr) { -+ if (DWC_CIRCLEQ_EMPTY(&ep->queue)) { -+ DWC_DEBUGPL(DBG_PCDV, "Request queue empty!!\n"); -+ } else { -+ DWC_DEBUGPL(DBG_PCDV, "complete req!!\n"); -+ req = DWC_CIRCLEQ_FIRST(&ep->queue); -+ if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len && -+ pcd->ep0state == EP0_OUT_DATA_PHASE) { -+ /* Read arrived setup packet from req->buf */ -+ dwc_memcpy(&pcd->setup_pkt->req, -+ req->buf + ep->dwc_ep.xfer_count, 8); -+ } -+ req->actual = ep->dwc_ep.xfer_count; -+ dwc_otg_request_done(ep, req, -ECONNRESET); -+ ep->dwc_ep.start_xfer_buff = 0; -+ ep->dwc_ep.xfer_buff = 0; -+ ep->dwc_ep.xfer_len = 0; -+ } -+ pcd->ep0state = EP0_IDLE; -+ if (doepint.b.setup) { -+ DWC_DEBUGPL(DBG_PCDV, "EP0_IDLE SR=1 setup=1\n"); -+ /* Data stage started, clear setup */ -+ CLEAR_OUT_EP_INTR(core_if, epnum, setup); -+ doepint.b.setup = 0; -+ handle_ep0(pcd); -+ /* Prepare for setup packets if ep0in was enabled*/ -+ if (pcd->ep0state == EP0_IN_STATUS_PHASE) { -+ ep0_out_start(core_if, pcd); -+ } -+ -+ goto exit_xfercompl; -+ } else { -+ /* Prepare for more setup packets */ -+ DWC_DEBUGPL(DBG_PCDV, -+ "EP0_IDLE SR=1 setup=0 new setup comes 2\n"); -+ ep0_out_start(core_if, pcd); -+ } -+ } -+ } -+ } -+ if (core_if->snpsid >= OTG_CORE_REV_2_94a && core_if->dma_enable -+ && core_if->dma_desc_enable == 0) { -+ doepint_data_t doepint_temp = {.d32 = 0}; -+ deptsiz0_data_t doeptsize0 = {.d32 = 0 }; -+ doepint_temp.d32 = DWC_READ_REG32(&core_if->dev_if-> -+ out_ep_regs[ep->dwc_ep.num]->doepint); -+ doeptsize0.d32 = DWC_READ_REG32(&core_if->dev_if-> -+ out_ep_regs[ep->dwc_ep.num]->doeptsiz); -+ if (pcd->ep0state == EP0_IDLE) { -+ if (doepint_temp.b.sr) { -+ CLEAR_OUT_EP_INTR(core_if, epnum, sr); -+ } -+ doepint.d32 = DWC_READ_REG32(&core_if->dev_if-> -+ out_ep_regs[0]->doepint); -+ if (doeptsize0.b.supcnt == 3) { -+ DWC_DEBUGPL(DBG_ANY, "Rolling over!!!!!!!\n"); -+ ep->dwc_ep.stp_rollover = 1; -+ } -+ if (doepint.b.setup) { -+retry: -+ /* Already started data stage, clear setup */ -+ CLEAR_OUT_EP_INTR(core_if, epnum, setup); -+ doepint.b.setup = 0; -+ handle_ep0(pcd); -+ ep->dwc_ep.stp_rollover = 0; -+ /* Prepare for more setup packets */ -+ if (pcd->ep0state == EP0_IN_STATUS_PHASE || -+ pcd->ep0state == EP0_IN_DATA_PHASE) { -+ ep0_out_start(core_if, pcd); -+ } -+ goto exit_xfercompl; -+ } else { -+ /* Prepare for more setup packets */ -+ DWC_DEBUGPL(DBG_ANY, -+ "EP0_IDLE SR=1 setup=0 new setup comes\n"); -+ doepint.d32 = DWC_READ_REG32(&core_if->dev_if-> -+ out_ep_regs[0]->doepint); -+ if(doepint.b.setup) -+ goto retry; -+ ep0_out_start(core_if, pcd); -+ } -+ } else { -+ dwc_otg_pcd_request_t *req; -+ diepint_data_t diepint0 = {.d32 = 0}; -+ doepint_data_t doepint_temp = {.d32 = 0}; -+ depctl_data_t diepctl0; -+ diepint0.d32 = DWC_READ_REG32(&core_if->dev_if-> -+ in_ep_regs[0]->diepint); -+ diepctl0.d32 = DWC_READ_REG32(&core_if->dev_if-> -+ in_ep_regs[0]->diepctl); -+ -+ if (pcd->ep0state == EP0_IN_DATA_PHASE -+ || pcd->ep0state == EP0_IN_STATUS_PHASE) { -+ if (diepint0.b.xfercompl) { -+ DWC_WRITE_REG32(&core_if->dev_if-> -+ in_ep_regs[0]->diepint, diepint0.d32); -+ } -+ if (diepctl0.b.epena) { -+ diepint_data_t diepint = {.d32 = 0}; -+ diepctl0.b.snak = 1; -+ DWC_WRITE_REG32(&core_if->dev_if-> -+ in_ep_regs[0]->diepctl, diepctl0.d32); -+ do { -+ dwc_udelay(10); -+ diepint.d32 = DWC_READ_REG32(&core_if->dev_if-> -+ in_ep_regs[0]->diepint); -+ } while (!diepint.b.inepnakeff); -+ diepint.b.inepnakeff = 1; -+ DWC_WRITE_REG32(&core_if->dev_if-> -+ in_ep_regs[0]->diepint, diepint.d32); -+ diepctl0.d32 = 0; -+ diepctl0.b.epdis = 1; -+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[0]->diepctl, -+ diepctl0.d32); -+ do { -+ dwc_udelay(10); -+ diepint.d32 = DWC_READ_REG32(&core_if->dev_if-> -+ in_ep_regs[0]->diepint); -+ } while (!diepint.b.epdisabled); -+ diepint.b.epdisabled = 1; -+ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[0]->diepint, -+ diepint.d32); -+ } -+ } -+ doepint_temp.d32 = DWC_READ_REG32(&core_if->dev_if-> -+ out_ep_regs[ep->dwc_ep.num]->doepint); -+ if (doepint_temp.b.sr) { -+ CLEAR_OUT_EP_INTR(core_if, epnum, sr); -+ if (DWC_CIRCLEQ_EMPTY(&ep->queue)) { -+ DWC_DEBUGPL(DBG_PCDV, "Request queue empty!!\n"); -+ } else { -+ DWC_DEBUGPL(DBG_PCDV, "complete req!!\n"); -+ req = DWC_CIRCLEQ_FIRST(&ep->queue); -+ if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len && -+ pcd->ep0state == EP0_OUT_DATA_PHASE) { -+ /* Read arrived setup packet from req->buf */ -+ dwc_memcpy(&pcd->setup_pkt->req, -+ req->buf + ep->dwc_ep.xfer_count, 8); -+ } -+ req->actual = ep->dwc_ep.xfer_count; -+ dwc_otg_request_done(ep, req, -ECONNRESET); -+ ep->dwc_ep.start_xfer_buff = 0; -+ ep->dwc_ep.xfer_buff = 0; -+ ep->dwc_ep.xfer_len = 0; -+ } -+ pcd->ep0state = EP0_IDLE; -+ if (doepint.b.setup) { -+ DWC_DEBUGPL(DBG_PCDV, "EP0_IDLE SR=1 setup=1\n"); -+ /* Data stage started, clear setup */ -+ CLEAR_OUT_EP_INTR(core_if, epnum, setup); -+ doepint.b.setup = 0; -+ handle_ep0(pcd); -+ /* Prepare for setup packets if ep0in was enabled*/ -+ if (pcd->ep0state == EP0_IN_STATUS_PHASE) { -+ ep0_out_start(core_if, pcd); -+ } -+ goto exit_xfercompl; -+ } else { -+ /* Prepare for more setup packets */ -+ DWC_DEBUGPL(DBG_PCDV, -+ "EP0_IDLE SR=1 setup=0 new setup comes 2\n"); -+ ep0_out_start(core_if, pcd); -+ } -+ } -+ } -+ } -+ if (core_if->dma_enable == 0 || pcd->ep0state != EP0_IDLE) -+ handle_ep0(pcd); -+exit_xfercompl: -+ DWC_DEBUGPL(DBG_PCDV, "DOEPINT=%x doepint=%x\n", -+ dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep), doepint.d32); -+ } else { -+ if (core_if->dma_desc_enable == 0 -+ || pcd->ep0state != EP0_IDLE) -+ handle_ep0(pcd); -+ } -+#ifdef DWC_EN_ISOC -+ } else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { -+ if (doepint.b.pktdrpsts == 0) { -+ /* Clear the bit in DOEPINTn for this interrupt */ -+ CLEAR_OUT_EP_INTR(core_if, -+ epnum, -+ xfercompl); -+ complete_iso_ep(pcd, ep); -+ } else { -+ -+ doepint_data_t doepint = {.d32 = 0 }; -+ doepint.b.xfercompl = 1; -+ doepint.b.pktdrpsts = 1; -+ DWC_WRITE_REG32 -+ (&core_if->dev_if->out_ep_regs -+ [epnum]->doepint, -+ doepint.d32); -+ if (handle_iso_out_pkt_dropped -+ (core_if, dwc_ep)) { -+ complete_iso_ep(pcd, -+ ep); -+ } -+ } -+#endif /* DWC_EN_ISOC */ -+#ifdef DWC_UTE_PER_IO -+ } else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { -+ CLEAR_OUT_EP_INTR(core_if, epnum, xfercompl); -+ if (!ep->stopped) -+ complete_xiso_ep(ep); -+#endif /* DWC_UTE_PER_IO */ -+ } else { -+ /* Clear the bit in DOEPINTn for this interrupt */ -+ CLEAR_OUT_EP_INTR(core_if, epnum, -+ xfercompl); -+ -+ if (core_if->core_params->dev_out_nak) { -+ DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[epnum]); -+ pcd->core_if->ep_xfer_info[epnum].state = 0; -+#ifdef DEBUG -+ print_memory_payload(pcd, dwc_ep); -+#endif -+ } -+ complete_ep(ep); -+ } -+ -+ } -+ -+ /* Endpoint disable */ -+ if (doepint.b.epdisabled) { -+ -+ /* Clear the bit in DOEPINTn for this interrupt */ -+ CLEAR_OUT_EP_INTR(core_if, epnum, epdisabled); -+ if (core_if->core_params->dev_out_nak) { -+#ifdef DEBUG -+ print_memory_payload(pcd, dwc_ep); -+#endif -+ /* In case of timeout condition */ -+ if (core_if->ep_xfer_info[epnum].state == 2) { -+ dctl.d32 = DWC_READ_REG32(&core_if->dev_if-> -+ dev_global_regs->dctl); -+ dctl.b.cgoutnak = 1; -+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, -+ dctl.d32); -+ /* Unmask goutnakeff interrupt which was masked -+ * during handle nak out interrupt */ -+ gintmsk.b.goutnakeff = 1; -+ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, -+ 0, gintmsk.d32); -+ -+ complete_ep(ep); -+ } -+ } -+ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) -+ { -+ dctl_data_t dctl; -+ gintmsk_data_t intr_mask = {.d32 = 0}; -+ dwc_otg_pcd_request_t *req = 0; -+ -+ dctl.d32 = DWC_READ_REG32(&core_if->dev_if-> -+ dev_global_regs->dctl); -+ dctl.b.cgoutnak = 1; -+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, -+ dctl.d32); -+ -+ intr_mask.d32 = 0; -+ intr_mask.b.incomplisoout = 1; -+ -+ /* Get any pending requests */ -+ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) { -+ req = DWC_CIRCLEQ_FIRST(&ep->queue); -+ if (!req) { -+ DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep); -+ } else { -+ dwc_otg_request_done(ep, req, 0); -+ start_next_request(ep); -+ } -+ } else { -+ DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep); -+ } -+ } -+ } -+ /* AHB Error */ -+ if (doepint.b.ahberr) { -+ DWC_ERROR("EP%d OUT AHB Error\n", epnum); -+ DWC_ERROR("EP%d DEPDMA=0x%08x \n", -+ epnum, core_if->dev_if->out_ep_regs[epnum]->doepdma); -+ CLEAR_OUT_EP_INTR(core_if, epnum, ahberr); -+ } -+ /* Setup Phase Done (contorl EPs) */ -+ if (doepint.b.setup) { -+#ifdef DEBUG_EP0 -+ DWC_DEBUGPL(DBG_PCD, "EP%d SETUP Done\n", epnum); -+#endif -+ CLEAR_OUT_EP_INTR(core_if, epnum, setup); -+ -+ handle_ep0(pcd); -+ } -+ -+ /** OUT EP BNA Intr */ -+ if (doepint.b.bna) { -+ CLEAR_OUT_EP_INTR(core_if, epnum, bna); -+ if (core_if->dma_desc_enable) { -+#ifdef DWC_EN_ISOC -+ if (dwc_ep->type == -+ DWC_OTG_EP_TYPE_ISOC) { -+ /* -+ * This checking is performed to prevent first "false" BNA -+ * handling occuring right after reconnect -+ */ -+ if (dwc_ep->next_frame != -+ 0xffffffff) -+ dwc_otg_pcd_handle_iso_bna(ep); -+ } else -+#endif /* DWC_EN_ISOC */ -+ { -+ dwc_otg_pcd_handle_noniso_bna(ep); -+ } -+ } -+ } -+ /* Babble Interrupt */ -+ if (doepint.b.babble) { -+ DWC_DEBUGPL(DBG_ANY, "EP%d OUT Babble\n", -+ epnum); -+ handle_out_ep_babble_intr(pcd, epnum); -+ -+ CLEAR_OUT_EP_INTR(core_if, epnum, babble); -+ } -+ if (doepint.b.outtknepdis) { -+ DWC_DEBUGPL(DBG_ANY, "EP%d OUT Token received when EP is \ -+ disabled\n",epnum); -+ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) { -+ doepmsk_data_t doepmsk = {.d32 = 0}; -+ ep->dwc_ep.frame_num = core_if->frame_num; -+ if (ep->dwc_ep.bInterval > 1) { -+ depctl_data_t depctl; -+ depctl.d32 = DWC_READ_REG32(&core_if->dev_if-> -+ out_ep_regs[epnum]->doepctl); -+ if (ep->dwc_ep.frame_num & 0x1) { -+ depctl.b.setd1pid = 1; -+ depctl.b.setd0pid = 0; -+ } else { -+ depctl.b.setd0pid = 1; -+ depctl.b.setd1pid = 0; -+ } -+ DWC_WRITE_REG32(&core_if->dev_if-> -+ out_ep_regs[epnum]->doepctl, depctl.d32); -+ } -+ start_next_request(ep); -+ doepmsk.b.outtknepdis = 1; -+ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk, -+ doepmsk.d32, 0); -+ } -+ CLEAR_OUT_EP_INTR(core_if, epnum, outtknepdis); -+ } -+ -+ /* NAK Interrutp */ -+ if (doepint.b.nak) { -+ DWC_DEBUGPL(DBG_ANY, "EP%d OUT NAK\n", epnum); -+ handle_out_ep_nak_intr(pcd, epnum); -+ -+ CLEAR_OUT_EP_INTR(core_if, epnum, nak); -+ } -+ /* NYET Interrutp */ -+ if (doepint.b.nyet) { -+ DWC_DEBUGPL(DBG_ANY, "EP%d OUT NYET\n", epnum); -+ handle_out_ep_nyet_intr(pcd, epnum); -+ -+ CLEAR_OUT_EP_INTR(core_if, epnum, nyet); -+ } -+ } -+ -+ epnum++; -+ ep_intr >>= 1; -+ } -+ -+ return 1; -+ -+#undef CLEAR_OUT_EP_INTR -+} -+static int drop_transfer(uint32_t trgt_fr, uint32_t curr_fr, uint8_t frm_overrun) -+{ -+ int retval = 0; -+ if(!frm_overrun && curr_fr >= trgt_fr) -+ retval = 1; -+ else if (frm_overrun -+ && (curr_fr >= trgt_fr && ((curr_fr - trgt_fr) < 0x3FFF / 2))) -+ retval = 1; -+ return retval; -+} -+/** -+ * Incomplete ISO IN Transfer Interrupt. -+ * This interrupt indicates one of the following conditions occurred -+ * while transmitting an ISOC transaction. -+ * - Corrupted IN Token for ISOC EP. -+ * - Packet not complete in FIFO. -+ * The follow actions will be taken: -+ * -# Determine the EP -+ * -# Set incomplete flag in dwc_ep structure -+ * -# Disable EP; when "Endpoint Disabled" interrupt is received -+ * Flush FIFO -+ */ -+int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr(dwc_otg_pcd_t * pcd) -+{ -+ gintsts_data_t gintsts; -+ -+#ifdef DWC_EN_ISOC -+ dwc_otg_dev_if_t *dev_if; -+ deptsiz_data_t deptsiz = {.d32 = 0 }; -+ depctl_data_t depctl = {.d32 = 0 }; -+ dsts_data_t dsts = {.d32 = 0 }; -+ dwc_ep_t *dwc_ep; -+ int i; -+ -+ dev_if = GET_CORE_IF(pcd)->dev_if; -+ -+ for (i = 1; i <= dev_if->num_in_eps; ++i) { -+ dwc_ep = &pcd->in_ep[i].dwc_ep; -+ if (dwc_ep->active && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { -+ deptsiz.d32 = -+ DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz); -+ depctl.d32 = -+ DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); -+ -+ if (depctl.b.epdis && deptsiz.d32) { -+ set_current_pkt_info(GET_CORE_IF(pcd), dwc_ep); -+ if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) { -+ dwc_ep->cur_pkt = 0; -+ dwc_ep->proc_buf_num = -+ (dwc_ep->proc_buf_num ^ 1) & 0x1; -+ -+ if (dwc_ep->proc_buf_num) { -+ dwc_ep->cur_pkt_addr = -+ dwc_ep->xfer_buff1; -+ dwc_ep->cur_pkt_dma_addr = -+ dwc_ep->dma_addr1; -+ } else { -+ dwc_ep->cur_pkt_addr = -+ dwc_ep->xfer_buff0; -+ dwc_ep->cur_pkt_dma_addr = -+ dwc_ep->dma_addr0; -+ } -+ -+ } -+ -+ dsts.d32 = -+ DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if-> -+ dev_global_regs->dsts); -+ dwc_ep->next_frame = dsts.b.soffn; -+ -+ dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF -+ (pcd), -+ dwc_ep); -+ } -+ } -+ } -+ -+#else -+ depctl_data_t depctl = {.d32 = 0 }; -+ dwc_ep_t *dwc_ep; -+ dwc_otg_dev_if_t *dev_if; -+ int i; -+ dev_if = GET_CORE_IF(pcd)->dev_if; -+ -+ DWC_DEBUGPL(DBG_PCD,"Incomplete ISO IN \n"); -+ -+ for (i = 1; i <= dev_if->num_in_eps; ++i) { -+ dwc_ep = &pcd->in_ep[i-1].dwc_ep; -+ depctl.d32 = -+ DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); -+ if (depctl.b.epena && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { -+ if (drop_transfer(dwc_ep->frame_num, GET_CORE_IF(pcd)->frame_num, -+ dwc_ep->frm_overrun)) -+ { -+ depctl.d32 = -+ DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); -+ depctl.b.snak = 1; -+ depctl.b.epdis = 1; -+ DWC_MODIFY_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32, depctl.d32); -+ } -+ } -+ } -+ -+ /*intr_mask.b.incomplisoin = 1; -+ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, -+ intr_mask.d32, 0); */ -+#endif //DWC_EN_ISOC -+ -+ /* Clear interrupt */ -+ gintsts.d32 = 0; -+ gintsts.b.incomplisoin = 1; -+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, -+ gintsts.d32); -+ -+ return 1; -+} -+ -+/** -+ * Incomplete ISO OUT Transfer Interrupt. -+ * -+ * This interrupt indicates that the core has dropped an ISO OUT -+ * packet. The following conditions can be the cause: -+ * - FIFO Full, the entire packet would not fit in the FIFO. -+ * - CRC Error -+ * - Corrupted Token -+ * The follow actions will be taken: -+ * -# Determine the EP -+ * -# Set incomplete flag in dwc_ep structure -+ * -# Read any data from the FIFO -+ * -# Disable EP. When "Endpoint Disabled" interrupt is received -+ * re-enable EP. -+ */ -+int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr(dwc_otg_pcd_t * pcd) -+{ -+ -+ gintsts_data_t gintsts; -+ -+#ifdef DWC_EN_ISOC -+ dwc_otg_dev_if_t *dev_if; -+ deptsiz_data_t deptsiz = {.d32 = 0 }; -+ depctl_data_t depctl = {.d32 = 0 }; -+ dsts_data_t dsts = {.d32 = 0 }; -+ dwc_ep_t *dwc_ep; -+ int i; -+ -+ dev_if = GET_CORE_IF(pcd)->dev_if; -+ -+ for (i = 1; i <= dev_if->num_out_eps; ++i) { -+ dwc_ep = &pcd->in_ep[i].dwc_ep; -+ if (pcd->out_ep[i].dwc_ep.active && -+ pcd->out_ep[i].dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) { -+ deptsiz.d32 = -+ DWC_READ_REG32(&dev_if->out_ep_regs[i]->doeptsiz); -+ depctl.d32 = -+ DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl); -+ -+ if (depctl.b.epdis && deptsiz.d32) { -+ set_current_pkt_info(GET_CORE_IF(pcd), -+ &pcd->out_ep[i].dwc_ep); -+ if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) { -+ dwc_ep->cur_pkt = 0; -+ dwc_ep->proc_buf_num = -+ (dwc_ep->proc_buf_num ^ 1) & 0x1; -+ -+ if (dwc_ep->proc_buf_num) { -+ dwc_ep->cur_pkt_addr = -+ dwc_ep->xfer_buff1; -+ dwc_ep->cur_pkt_dma_addr = -+ dwc_ep->dma_addr1; -+ } else { -+ dwc_ep->cur_pkt_addr = -+ dwc_ep->xfer_buff0; -+ dwc_ep->cur_pkt_dma_addr = -+ dwc_ep->dma_addr0; -+ } -+ -+ } -+ -+ dsts.d32 = -+ DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if-> -+ dev_global_regs->dsts); -+ dwc_ep->next_frame = dsts.b.soffn; -+ -+ dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF -+ (pcd), -+ dwc_ep); -+ } -+ } -+ } -+#else -+ /** @todo implement ISR */ -+ gintmsk_data_t intr_mask = {.d32 = 0 }; -+ dwc_otg_core_if_t *core_if; -+ deptsiz_data_t deptsiz = {.d32 = 0 }; -+ depctl_data_t depctl = {.d32 = 0 }; -+ dctl_data_t dctl = {.d32 = 0 }; -+ dwc_ep_t *dwc_ep = NULL; -+ int i; -+ core_if = GET_CORE_IF(pcd); -+ -+ for (i = 0; i < core_if->dev_if->num_out_eps; ++i) { -+ dwc_ep = &pcd->out_ep[i].dwc_ep; -+ depctl.d32 = -+ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl); -+ if (depctl.b.epena && depctl.b.dpid == (core_if->frame_num & 0x1)) { -+ core_if->dev_if->isoc_ep = dwc_ep; -+ deptsiz.d32 = -+ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz); -+ break; -+ } -+ } -+ dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl); -+ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts); -+ intr_mask.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk); -+ -+ if (!intr_mask.b.goutnakeff) { -+ /* Unmask it */ -+ intr_mask.b.goutnakeff = 1; -+ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, intr_mask.d32); -+ } -+ if (!gintsts.b.goutnakeff) { -+ dctl.b.sgoutnak = 1; -+ } -+ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32); -+ -+ depctl.d32 = DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl); -+ if (depctl.b.epena) { -+ depctl.b.epdis = 1; -+ depctl.b.snak = 1; -+ } -+ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl, depctl.d32); -+ -+ intr_mask.d32 = 0; -+ intr_mask.b.incomplisoout = 1; -+ -+#endif /* DWC_EN_ISOC */ -+ -+ /* Clear interrupt */ -+ gintsts.d32 = 0; -+ gintsts.b.incomplisoout = 1; -+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, -+ gintsts.d32); -+ -+ return 1; -+} -+ -+/** -+ * This function handles the Global IN NAK Effective interrupt. -+ * -+ */ -+int32_t dwc_otg_pcd_handle_in_nak_effective(dwc_otg_pcd_t * pcd) -+{ -+ dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if; -+ depctl_data_t diepctl = {.d32 = 0 }; -+ gintmsk_data_t intr_mask = {.d32 = 0 }; -+ gintsts_data_t gintsts; -+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); -+ int i; -+ -+ DWC_DEBUGPL(DBG_PCD, "Global IN NAK Effective\n"); -+ -+ /* Disable all active IN EPs */ -+ for (i = 0; i <= dev_if->num_in_eps; i++) { -+ diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); -+ if (!(diepctl.b.eptype & 1) && diepctl.b.epena) { -+ if (core_if->start_predict > 0) -+ core_if->start_predict++; -+ diepctl.b.epdis = 1; -+ diepctl.b.snak = 1; -+ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, diepctl.d32); -+ } -+ } -+ -+ -+ /* Disable the Global IN NAK Effective Interrupt */ -+ intr_mask.b.ginnakeff = 1; -+ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, -+ intr_mask.d32, 0); -+ -+ /* Clear interrupt */ -+ gintsts.d32 = 0; -+ gintsts.b.ginnakeff = 1; -+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, -+ gintsts.d32); -+ -+ return 1; -+} -+ -+/** -+ * OUT NAK Effective. -+ * -+ */ -+int32_t dwc_otg_pcd_handle_out_nak_effective(dwc_otg_pcd_t * pcd) -+{ -+ dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if; -+ gintmsk_data_t intr_mask = {.d32 = 0 }; -+ gintsts_data_t gintsts; -+ depctl_data_t doepctl; -+ int i; -+ -+ /* Disable the Global OUT NAK Effective Interrupt */ -+ intr_mask.b.goutnakeff = 1; -+ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, -+ intr_mask.d32, 0); -+ -+ /* If DEV OUT NAK enabled*/ -+ if (pcd->core_if->core_params->dev_out_nak) { -+ /* Run over all out endpoints to determine the ep number on -+ * which the timeout has happened -+ */ -+ for (i = 0; i <= dev_if->num_out_eps; i++) { -+ if ( pcd->core_if->ep_xfer_info[i].state == 2 ) -+ break; -+ } -+ if (i > dev_if->num_out_eps) { -+ dctl_data_t dctl; -+ dctl.d32 = -+ DWC_READ_REG32(&dev_if->dev_global_regs->dctl); -+ dctl.b.cgoutnak = 1; -+ DWC_WRITE_REG32(&dev_if->dev_global_regs->dctl, -+ dctl.d32); -+ goto out; -+ } -+ -+ /* Disable the endpoint */ -+ doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl); -+ if (doepctl.b.epena) { -+ doepctl.b.epdis = 1; -+ doepctl.b.snak = 1; -+ } -+ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32); -+ return 1; -+ } -+ /* We come here from Incomplete ISO OUT handler */ -+ if (dev_if->isoc_ep) { -+ dwc_ep_t *dwc_ep = (dwc_ep_t *)dev_if->isoc_ep; -+ uint32_t epnum = dwc_ep->num; -+ doepint_data_t doepint; -+ doepint.d32 = -+ DWC_READ_REG32(&dev_if->out_ep_regs[dwc_ep->num]->doepint); -+ dev_if->isoc_ep = NULL; -+ doepctl.d32 = -+ DWC_READ_REG32(&dev_if->out_ep_regs[epnum]->doepctl); -+ DWC_PRINTF("Before disable DOEPCTL = %08x\n", doepctl.d32); -+ if (doepctl.b.epena) { -+ doepctl.b.epdis = 1; -+ doepctl.b.snak = 1; -+ } -+ DWC_WRITE_REG32(&dev_if->out_ep_regs[epnum]->doepctl, -+ doepctl.d32); -+ return 1; -+ } else -+ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", -+ "Global OUT NAK Effective\n"); -+ -+out: -+ /* Clear interrupt */ -+ gintsts.d32 = 0; -+ gintsts.b.goutnakeff = 1; -+ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, -+ gintsts.d32); -+ -+ return 1; -+} -+ -+/** -+ * PCD interrupt handler. -+ * -+ * The PCD handles the device interrupts. Many conditions can cause a -+ * device interrupt. When an interrupt occurs, the device interrupt -+ * service routine determines the cause of the interrupt and -+ * dispatches handling to the appropriate function. These interrupt -+ * handling functions are described below. -+ * -+ * All interrupt registers are processed from LSB to MSB. -+ * -+ */ -+int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd) -+{ -+ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); -+#ifdef VERBOSE -+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; -+#endif -+ gintsts_data_t gintr_status; -+ int32_t retval = 0; -+ -+ /* Exit from ISR if core is hibernated */ -+ if (core_if->hibernation_suspend == 1) { -+ return retval; -+ } -+#ifdef VERBOSE -+ DWC_DEBUGPL(DBG_ANY, "%s() gintsts=%08x gintmsk=%08x\n", -+ __func__, -+ DWC_READ_REG32(&global_regs->gintsts), -+ DWC_READ_REG32(&global_regs->gintmsk)); -+#endif -+ -+ if (dwc_otg_is_device_mode(core_if)) { -+ DWC_SPINLOCK(pcd->lock); -+#ifdef VERBOSE -+ DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%08x gintmsk=%08x\n", -+ __func__, -+ DWC_READ_REG32(&global_regs->gintsts), -+ DWC_READ_REG32(&global_regs->gintmsk)); -+#endif -+ -+ gintr_status.d32 = dwc_otg_read_core_intr(core_if); -+ -+ DWC_DEBUGPL(DBG_PCDV, "%s: gintsts&gintmsk=%08x\n", -+ __func__, gintr_status.d32); -+ -+ if (gintr_status.b.sofintr) { -+ retval |= dwc_otg_pcd_handle_sof_intr(pcd); -+ } -+ if (gintr_status.b.rxstsqlvl) { -+ retval |= -+ dwc_otg_pcd_handle_rx_status_q_level_intr(pcd); -+ } -+ if (gintr_status.b.nptxfempty) { -+ retval |= dwc_otg_pcd_handle_np_tx_fifo_empty_intr(pcd); -+ } -+ if (gintr_status.b.goutnakeff) { -+ retval |= dwc_otg_pcd_handle_out_nak_effective(pcd); -+ } -+ if (gintr_status.b.i2cintr) { -+ retval |= dwc_otg_pcd_handle_i2c_intr(pcd); -+ } -+ if (gintr_status.b.erlysuspend) { -+ retval |= dwc_otg_pcd_handle_early_suspend_intr(pcd); -+ } -+ if (gintr_status.b.usbreset) { -+ retval |= dwc_otg_pcd_handle_usb_reset_intr(pcd); -+ } -+ if (gintr_status.b.enumdone) { -+ retval |= dwc_otg_pcd_handle_enum_done_intr(pcd); -+ } -+ if (gintr_status.b.isooutdrop) { -+ retval |= -+ dwc_otg_pcd_handle_isoc_out_packet_dropped_intr -+ (pcd); -+ } -+ if (gintr_status.b.eopframe) { -+ retval |= -+ dwc_otg_pcd_handle_end_periodic_frame_intr(pcd); -+ } -+ if (gintr_status.b.inepint) { -+ if (!core_if->multiproc_int_enable) { -+ retval |= dwc_otg_pcd_handle_in_ep_intr(pcd); -+ } -+ } -+ if (gintr_status.b.outepintr) { -+ if (!core_if->multiproc_int_enable) { -+ retval |= dwc_otg_pcd_handle_out_ep_intr(pcd); -+ } -+ } -+ if (gintr_status.b.epmismatch) { -+ retval |= dwc_otg_pcd_handle_ep_mismatch_intr(pcd); -+ } -+ if (gintr_status.b.fetsusp) { -+ retval |= dwc_otg_pcd_handle_ep_fetsusp_intr(pcd); -+ } -+ if (gintr_status.b.ginnakeff) { -+ retval |= dwc_otg_pcd_handle_in_nak_effective(pcd); -+ } -+ if (gintr_status.b.incomplisoin) { -+ retval |= -+ dwc_otg_pcd_handle_incomplete_isoc_in_intr(pcd); -+ } -+ if (gintr_status.b.incomplisoout) { -+ retval |= -+ dwc_otg_pcd_handle_incomplete_isoc_out_intr(pcd); -+ } -+ -+ /* In MPI mode Device Endpoints interrupts are asserted -+ * without setting outepintr and inepint bits set, so these -+ * Interrupt handlers are called without checking these bit-fields -+ */ -+ if (core_if->multiproc_int_enable) { -+ retval |= dwc_otg_pcd_handle_in_ep_intr(pcd); -+ retval |= dwc_otg_pcd_handle_out_ep_intr(pcd); -+ } -+#ifdef VERBOSE -+ DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%0x\n", __func__, -+ DWC_READ_REG32(&global_regs->gintsts)); -+#endif -+ DWC_SPINUNLOCK(pcd->lock); -+ } -+ return retval; -+} -+ -+#endif /* DWC_HOST_ONLY */ -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c 2015-11-29 09:42:39.923098428 +0100 -@@ -0,0 +1,1360 @@ -+ /* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_linux.c $ -+ * $Revision: #21 $ -+ * $Date: 2012/08/10 $ -+ * $Change: 2047372 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+#ifndef DWC_HOST_ONLY -+ -+/** @file -+ * This file implements the Peripheral Controller Driver. -+ * -+ * The Peripheral Controller Driver (PCD) is responsible for -+ * translating requests from the Function Driver into the appropriate -+ * actions on the DWC_otg controller. It isolates the Function Driver -+ * from the specifics of the controller by providing an API to the -+ * Function Driver. -+ * -+ * The Peripheral Controller Driver for Linux will implement the -+ * Gadget API, so that the existing Gadget drivers can be used. -+ * (Gadget Driver is the Linux terminology for a Function Driver.) -+ * -+ * The Linux Gadget API is defined in the header file -+ * . The USB EP operations API is -+ * defined in the structure usb_ep_ops and the USB -+ * Controller API is defined in the structure -+ * usb_gadget_ops. -+ * -+ */ -+ -+#include "dwc_otg_os_dep.h" -+#include "dwc_otg_pcd_if.h" -+#include "dwc_otg_pcd.h" -+#include "dwc_otg_driver.h" -+#include "dwc_otg_dbg.h" -+ -+extern bool fiq_enable; -+ -+static struct gadget_wrapper { -+ dwc_otg_pcd_t *pcd; -+ -+ struct usb_gadget gadget; -+ struct usb_gadget_driver *driver; -+ -+ struct usb_ep ep0; -+ struct usb_ep in_ep[16]; -+ struct usb_ep out_ep[16]; -+ -+} *gadget_wrapper; -+ -+/* Display the contents of the buffer */ -+extern void dump_msg(const u8 * buf, unsigned int length); -+/** -+ * Get the dwc_otg_pcd_ep_t* from usb_ep* pointer - NULL in case -+ * if the endpoint is not found -+ */ -+static struct dwc_otg_pcd_ep *ep_from_handle(dwc_otg_pcd_t * pcd, void *handle) -+{ -+ int i; -+ if (pcd->ep0.priv == handle) { -+ return &pcd->ep0; -+ } -+ -+ for (i = 0; i < MAX_EPS_CHANNELS - 1; i++) { -+ if (pcd->in_ep[i].priv == handle) -+ return &pcd->in_ep[i]; -+ if (pcd->out_ep[i].priv == handle) -+ return &pcd->out_ep[i]; -+ } -+ -+ return NULL; -+} -+ -+/* USB Endpoint Operations */ -+/* -+ * The following sections briefly describe the behavior of the Gadget -+ * API endpoint operations implemented in the DWC_otg driver -+ * software. Detailed descriptions of the generic behavior of each of -+ * these functions can be found in the Linux header file -+ * include/linux/usb_gadget.h. -+ * -+ * The Gadget API provides wrapper functions for each of the function -+ * pointers defined in usb_ep_ops. The Gadget Driver calls the wrapper -+ * function, which then calls the underlying PCD function. The -+ * following sections are named according to the wrapper -+ * functions. Within each section, the corresponding DWC_otg PCD -+ * function name is specified. -+ * -+ */ -+ -+/** -+ * This function is called by the Gadget Driver for each EP to be -+ * configured for the current configuration (SET_CONFIGURATION). -+ * -+ * This function initializes the dwc_otg_ep_t data structure, and then -+ * calls dwc_otg_ep_activate. -+ */ -+static int ep_enable(struct usb_ep *usb_ep, -+ const struct usb_endpoint_descriptor *ep_desc) -+{ -+ int retval; -+ -+ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, usb_ep, ep_desc); -+ -+ if (!usb_ep || !ep_desc || ep_desc->bDescriptorType != USB_DT_ENDPOINT) { -+ DWC_WARN("%s, bad ep or descriptor\n", __func__); -+ return -EINVAL; -+ } -+ if (usb_ep == &gadget_wrapper->ep0) { -+ DWC_WARN("%s, bad ep(0)\n", __func__); -+ return -EINVAL; -+ } -+ -+ /* Check FIFO size? */ -+ if (!ep_desc->wMaxPacketSize) { -+ DWC_WARN("%s, bad %s maxpacket\n", __func__, usb_ep->name); -+ return -ERANGE; -+ } -+ -+ if (!gadget_wrapper->driver || -+ gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) { -+ DWC_WARN("%s, bogus device state\n", __func__); -+ return -ESHUTDOWN; -+ } -+ -+ /* Delete after check - MAS */ -+#if 0 -+ nat = (uint32_t) ep_desc->wMaxPacketSize; -+ printk(KERN_ALERT "%s: nat (before) =%d\n", __func__, nat); -+ nat = (nat >> 11) & 0x03; -+ printk(KERN_ALERT "%s: nat (after) =%d\n", __func__, nat); -+#endif -+ retval = dwc_otg_pcd_ep_enable(gadget_wrapper->pcd, -+ (const uint8_t *)ep_desc, -+ (void *)usb_ep); -+ if (retval) { -+ DWC_WARN("dwc_otg_pcd_ep_enable failed\n"); -+ return -EINVAL; -+ } -+ -+ usb_ep->maxpacket = le16_to_cpu(ep_desc->wMaxPacketSize); -+ -+ return 0; -+} -+ -+/** -+ * This function is called when an EP is disabled due to disconnect or -+ * change in configuration. Any pending requests will terminate with a -+ * status of -ESHUTDOWN. -+ * -+ * This function modifies the dwc_otg_ep_t data structure for this EP, -+ * and then calls dwc_otg_ep_deactivate. -+ */ -+static int ep_disable(struct usb_ep *usb_ep) -+{ -+ int retval; -+ -+ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, usb_ep); -+ if (!usb_ep) { -+ DWC_DEBUGPL(DBG_PCD, "%s, %s not enabled\n", __func__, -+ usb_ep ? usb_ep->name : NULL); -+ return -EINVAL; -+ } -+ -+ retval = dwc_otg_pcd_ep_disable(gadget_wrapper->pcd, usb_ep); -+ if (retval) { -+ retval = -EINVAL; -+ } -+ -+ return retval; -+} -+ -+/** -+ * This function allocates a request object to use with the specified -+ * endpoint. -+ * -+ * @param ep The endpoint to be used with with the request -+ * @param gfp_flags the GFP_* flags to use. -+ */ -+static struct usb_request *dwc_otg_pcd_alloc_request(struct usb_ep *ep, -+ gfp_t gfp_flags) -+{ -+ struct usb_request *usb_req; -+ -+ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%d)\n", __func__, ep, gfp_flags); -+ if (0 == ep) { -+ DWC_WARN("%s() %s\n", __func__, "Invalid EP!\n"); -+ return 0; -+ } -+ usb_req = kmalloc(sizeof(*usb_req), gfp_flags); -+ if (0 == usb_req) { -+ DWC_WARN("%s() %s\n", __func__, "request allocation failed!\n"); -+ return 0; -+ } -+ memset(usb_req, 0, sizeof(*usb_req)); -+ usb_req->dma = DWC_DMA_ADDR_INVALID; -+ -+ return usb_req; -+} -+ -+/** -+ * This function frees a request object. -+ * -+ * @param ep The endpoint associated with the request -+ * @param req The request being freed -+ */ -+static void dwc_otg_pcd_free_request(struct usb_ep *ep, struct usb_request *req) -+{ -+ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, ep, req); -+ -+ if (0 == ep || 0 == req) { -+ DWC_WARN("%s() %s\n", __func__, -+ "Invalid ep or req argument!\n"); -+ return; -+ } -+ -+ kfree(req); -+} -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) -+/** -+ * This function allocates an I/O buffer to be used for a transfer -+ * to/from the specified endpoint. -+ * -+ * @param usb_ep The endpoint to be used with with the request -+ * @param bytes The desired number of bytes for the buffer -+ * @param dma Pointer to the buffer's DMA address; must be valid -+ * @param gfp_flags the GFP_* flags to use. -+ * @return address of a new buffer or null is buffer could not be allocated. -+ */ -+static void *dwc_otg_pcd_alloc_buffer(struct usb_ep *usb_ep, unsigned bytes, -+ dma_addr_t * dma, gfp_t gfp_flags) -+{ -+ void *buf; -+ dwc_otg_pcd_t *pcd = 0; -+ -+ pcd = gadget_wrapper->pcd; -+ -+ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%d,%p,%0x)\n", __func__, usb_ep, bytes, -+ dma, gfp_flags); -+ -+ /* Check dword alignment */ -+ if ((bytes & 0x3UL) != 0) { -+ DWC_WARN("%s() Buffer size is not a multiple of" -+ "DWORD size (%d)", __func__, bytes); -+ } -+ -+ buf = dma_alloc_coherent(NULL, bytes, dma, gfp_flags); -+ -+ /* Check dword alignment */ -+ if (((int)buf & 0x3UL) != 0) { -+ DWC_WARN("%s() Buffer is not DWORD aligned (%p)", -+ __func__, buf); -+ } -+ -+ return buf; -+} -+ -+/** -+ * This function frees an I/O buffer that was allocated by alloc_buffer. -+ * -+ * @param usb_ep the endpoint associated with the buffer -+ * @param buf address of the buffer -+ * @param dma The buffer's DMA address -+ * @param bytes The number of bytes of the buffer -+ */ -+static void dwc_otg_pcd_free_buffer(struct usb_ep *usb_ep, void *buf, -+ dma_addr_t dma, unsigned bytes) -+{ -+ dwc_otg_pcd_t *pcd = 0; -+ -+ pcd = gadget_wrapper->pcd; -+ -+ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%0x,%d)\n", __func__, buf, dma, bytes); -+ -+ dma_free_coherent(NULL, bytes, buf, dma); -+} -+#endif -+ -+/** -+ * This function is used to submit an I/O Request to an EP. -+ * -+ * - When the request completes the request's completion callback -+ * is called to return the request to the driver. -+ * - An EP, except control EPs, may have multiple requests -+ * pending. -+ * - Once submitted the request cannot be examined or modified. -+ * - Each request is turned into one or more packets. -+ * - A BULK EP can queue any amount of data; the transfer is -+ * packetized. -+ * - Zero length Packets are specified with the request 'zero' -+ * flag. -+ */ -+static int ep_queue(struct usb_ep *usb_ep, struct usb_request *usb_req, -+ gfp_t gfp_flags) -+{ -+ dwc_otg_pcd_t *pcd; -+ struct dwc_otg_pcd_ep *ep = NULL; -+ int retval = 0, is_isoc_ep = 0; -+ dma_addr_t dma_addr = DWC_DMA_ADDR_INVALID; -+ -+ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p,%d)\n", -+ __func__, usb_ep, usb_req, gfp_flags); -+ -+ if (!usb_req || !usb_req->complete || !usb_req->buf) { -+ DWC_WARN("bad params\n"); -+ return -EINVAL; -+ } -+ -+ if (!usb_ep) { -+ DWC_WARN("bad ep\n"); -+ return -EINVAL; -+ } -+ -+ pcd = gadget_wrapper->pcd; -+ if (!gadget_wrapper->driver || -+ gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) { -+ DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n", -+ gadget_wrapper->gadget.speed); -+ DWC_WARN("bogus device state\n"); -+ return -ESHUTDOWN; -+ } -+ -+ DWC_DEBUGPL(DBG_PCD, "%s queue req %p, len %d buf %p\n", -+ usb_ep->name, usb_req, usb_req->length, usb_req->buf); -+ -+ usb_req->status = -EINPROGRESS; -+ usb_req->actual = 0; -+ -+ ep = ep_from_handle(pcd, usb_ep); -+ if (ep == NULL) -+ is_isoc_ep = 0; -+ else -+ is_isoc_ep = (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) ? 1 : 0; -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) -+ dma_addr = usb_req->dma; -+#else -+ if (GET_CORE_IF(pcd)->dma_enable) { -+ dwc_otg_device_t *otg_dev = gadget_wrapper->pcd->otg_dev; -+ struct device *dev = NULL; -+ -+ if (otg_dev != NULL) -+ dev = DWC_OTG_OS_GETDEV(otg_dev->os_dep); -+ -+ if (usb_req->length != 0 && -+ usb_req->dma == DWC_DMA_ADDR_INVALID) { -+ dma_addr = dma_map_single(dev, usb_req->buf, -+ usb_req->length, -+ ep->dwc_ep.is_in ? -+ DMA_TO_DEVICE: -+ DMA_FROM_DEVICE); -+ } -+ } -+#endif -+ -+#ifdef DWC_UTE_PER_IO -+ if (is_isoc_ep == 1) { -+ retval = dwc_otg_pcd_xiso_ep_queue(pcd, usb_ep, usb_req->buf, dma_addr, -+ usb_req->length, usb_req->zero, usb_req, -+ gfp_flags == GFP_ATOMIC ? 1 : 0, &usb_req->ext_req); -+ if (retval) -+ return -EINVAL; -+ -+ return 0; -+ } -+#endif -+ retval = dwc_otg_pcd_ep_queue(pcd, usb_ep, usb_req->buf, dma_addr, -+ usb_req->length, usb_req->zero, usb_req, -+ gfp_flags == GFP_ATOMIC ? 1 : 0); -+ if (retval) { -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+/** -+ * This function cancels an I/O request from an EP. -+ */ -+static int ep_dequeue(struct usb_ep *usb_ep, struct usb_request *usb_req) -+{ -+ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, usb_ep, usb_req); -+ -+ if (!usb_ep || !usb_req) { -+ DWC_WARN("bad argument\n"); -+ return -EINVAL; -+ } -+ if (!gadget_wrapper->driver || -+ gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) { -+ DWC_WARN("bogus device state\n"); -+ return -ESHUTDOWN; -+ } -+ if (dwc_otg_pcd_ep_dequeue(gadget_wrapper->pcd, usb_ep, usb_req)) { -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+/** -+ * usb_ep_set_halt stalls an endpoint. -+ * -+ * usb_ep_clear_halt clears an endpoint halt and resets its data -+ * toggle. -+ * -+ * Both of these functions are implemented with the same underlying -+ * function. The behavior depends on the value argument. -+ * -+ * @param[in] usb_ep the Endpoint to halt or clear halt. -+ * @param[in] value -+ * - 0 means clear_halt. -+ * - 1 means set_halt, -+ * - 2 means clear stall lock flag. -+ * - 3 means set stall lock flag. -+ */ -+static int ep_halt(struct usb_ep *usb_ep, int value) -+{ -+ int retval = 0; -+ -+ DWC_DEBUGPL(DBG_PCD, "HALT %s %d\n", usb_ep->name, value); -+ -+ if (!usb_ep) { -+ DWC_WARN("bad ep\n"); -+ return -EINVAL; -+ } -+ -+ retval = dwc_otg_pcd_ep_halt(gadget_wrapper->pcd, usb_ep, value); -+ if (retval == -DWC_E_AGAIN) { -+ return -EAGAIN; -+ } else if (retval) { -+ retval = -EINVAL; -+ } -+ -+ return retval; -+} -+ -+//#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)) -+#if 0 -+/** -+ * ep_wedge: sets the halt feature and ignores clear requests -+ * -+ * @usb_ep: the endpoint being wedged -+ * -+ * Use this to stall an endpoint and ignore CLEAR_FEATURE(HALT_ENDPOINT) -+ * requests. If the gadget driver clears the halt status, it will -+ * automatically unwedge the endpoint. -+ * -+ * Returns zero on success, else negative errno. * -+ * Check usb_ep_set_wedge() at "usb_gadget.h" for details -+ */ -+static int ep_wedge(struct usb_ep *usb_ep) -+{ -+ int retval = 0; -+ -+ DWC_DEBUGPL(DBG_PCD, "WEDGE %s\n", usb_ep->name); -+ -+ if (!usb_ep) { -+ DWC_WARN("bad ep\n"); -+ return -EINVAL; -+ } -+ -+ retval = dwc_otg_pcd_ep_wedge(gadget_wrapper->pcd, usb_ep); -+ if (retval == -DWC_E_AGAIN) { -+ retval = -EAGAIN; -+ } else if (retval) { -+ retval = -EINVAL; -+ } -+ -+ return retval; -+} -+#endif -+ -+#ifdef DWC_EN_ISOC -+/** -+ * This function is used to submit an ISOC Transfer Request to an EP. -+ * -+ * - Every time a sync period completes the request's completion callback -+ * is called to provide data to the gadget driver. -+ * - Once submitted the request cannot be modified. -+ * - Each request is turned into periodic data packets untill ISO -+ * Transfer is stopped.. -+ */ -+static int iso_ep_start(struct usb_ep *usb_ep, struct usb_iso_request *req, -+ gfp_t gfp_flags) -+{ -+ int retval = 0; -+ -+ if (!req || !req->process_buffer || !req->buf0 || !req->buf1) { -+ DWC_WARN("bad params\n"); -+ return -EINVAL; -+ } -+ -+ if (!usb_ep) { -+ DWC_PRINTF("bad params\n"); -+ return -EINVAL; -+ } -+ -+ req->status = -EINPROGRESS; -+ -+ retval = -+ dwc_otg_pcd_iso_ep_start(gadget_wrapper->pcd, usb_ep, req->buf0, -+ req->buf1, req->dma0, req->dma1, -+ req->sync_frame, req->data_pattern_frame, -+ req->data_per_frame, -+ req-> -+ flags & USB_REQ_ISO_ASAP ? -1 : -+ req->start_frame, req->buf_proc_intrvl, -+ req, gfp_flags == GFP_ATOMIC ? 1 : 0); -+ -+ if (retval) { -+ return -EINVAL; -+ } -+ -+ return retval; -+} -+ -+/** -+ * This function stops ISO EP Periodic Data Transfer. -+ */ -+static int iso_ep_stop(struct usb_ep *usb_ep, struct usb_iso_request *req) -+{ -+ int retval = 0; -+ if (!usb_ep) { -+ DWC_WARN("bad ep\n"); -+ } -+ -+ if (!gadget_wrapper->driver || -+ gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) { -+ DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n", -+ gadget_wrapper->gadget.speed); -+ DWC_WARN("bogus device state\n"); -+ } -+ -+ dwc_otg_pcd_iso_ep_stop(gadget_wrapper->pcd, usb_ep, req); -+ if (retval) { -+ retval = -EINVAL; -+ } -+ -+ return retval; -+} -+ -+static struct usb_iso_request *alloc_iso_request(struct usb_ep *ep, -+ int packets, gfp_t gfp_flags) -+{ -+ struct usb_iso_request *pReq = NULL; -+ uint32_t req_size; -+ -+ req_size = sizeof(struct usb_iso_request); -+ req_size += -+ (2 * packets * (sizeof(struct usb_gadget_iso_packet_descriptor))); -+ -+ pReq = kmalloc(req_size, gfp_flags); -+ if (!pReq) { -+ DWC_WARN("Can't allocate Iso Request\n"); -+ return 0; -+ } -+ pReq->iso_packet_desc0 = (void *)(pReq + 1); -+ -+ pReq->iso_packet_desc1 = pReq->iso_packet_desc0 + packets; -+ -+ return pReq; -+} -+ -+static void free_iso_request(struct usb_ep *ep, struct usb_iso_request *req) -+{ -+ kfree(req); -+} -+ -+static struct usb_isoc_ep_ops dwc_otg_pcd_ep_ops = { -+ .ep_ops = { -+ .enable = ep_enable, -+ .disable = ep_disable, -+ -+ .alloc_request = dwc_otg_pcd_alloc_request, -+ .free_request = dwc_otg_pcd_free_request, -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) -+ .alloc_buffer = dwc_otg_pcd_alloc_buffer, -+ .free_buffer = dwc_otg_pcd_free_buffer, -+#endif -+ -+ .queue = ep_queue, -+ .dequeue = ep_dequeue, -+ -+ .set_halt = ep_halt, -+ .fifo_status = 0, -+ .fifo_flush = 0, -+ }, -+ .iso_ep_start = iso_ep_start, -+ .iso_ep_stop = iso_ep_stop, -+ .alloc_iso_request = alloc_iso_request, -+ .free_iso_request = free_iso_request, -+}; -+ -+#else -+ -+ int (*enable) (struct usb_ep *ep, -+ const struct usb_endpoint_descriptor *desc); -+ int (*disable) (struct usb_ep *ep); -+ -+ struct usb_request *(*alloc_request) (struct usb_ep *ep, -+ gfp_t gfp_flags); -+ void (*free_request) (struct usb_ep *ep, struct usb_request *req); -+ -+ int (*queue) (struct usb_ep *ep, struct usb_request *req, -+ gfp_t gfp_flags); -+ int (*dequeue) (struct usb_ep *ep, struct usb_request *req); -+ -+ int (*set_halt) (struct usb_ep *ep, int value); -+ int (*set_wedge) (struct usb_ep *ep); -+ -+ int (*fifo_status) (struct usb_ep *ep); -+ void (*fifo_flush) (struct usb_ep *ep); -+static struct usb_ep_ops dwc_otg_pcd_ep_ops = { -+ .enable = ep_enable, -+ .disable = ep_disable, -+ -+ .alloc_request = dwc_otg_pcd_alloc_request, -+ .free_request = dwc_otg_pcd_free_request, -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) -+ .alloc_buffer = dwc_otg_pcd_alloc_buffer, -+ .free_buffer = dwc_otg_pcd_free_buffer, -+#else -+ /* .set_wedge = ep_wedge, */ -+ .set_wedge = NULL, /* uses set_halt instead */ -+#endif -+ -+ .queue = ep_queue, -+ .dequeue = ep_dequeue, -+ -+ .set_halt = ep_halt, -+ .fifo_status = 0, -+ .fifo_flush = 0, -+ -+}; -+ -+#endif /* _EN_ISOC_ */ -+/* Gadget Operations */ -+/** -+ * The following gadget operations will be implemented in the DWC_otg -+ * PCD. Functions in the API that are not described below are not -+ * implemented. -+ * -+ * The Gadget API provides wrapper functions for each of the function -+ * pointers defined in usb_gadget_ops. The Gadget Driver calls the -+ * wrapper function, which then calls the underlying PCD function. The -+ * following sections are named according to the wrapper functions -+ * (except for ioctl, which doesn't have a wrapper function). Within -+ * each section, the corresponding DWC_otg PCD function name is -+ * specified. -+ * -+ */ -+ -+/** -+ *Gets the USB Frame number of the last SOF. -+ */ -+static int get_frame_number(struct usb_gadget *gadget) -+{ -+ struct gadget_wrapper *d; -+ -+ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, gadget); -+ -+ if (gadget == 0) { -+ return -ENODEV; -+ } -+ -+ d = container_of(gadget, struct gadget_wrapper, gadget); -+ return dwc_otg_pcd_get_frame_number(d->pcd); -+} -+ -+#ifdef CONFIG_USB_DWC_OTG_LPM -+static int test_lpm_enabled(struct usb_gadget *gadget) -+{ -+ struct gadget_wrapper *d; -+ -+ d = container_of(gadget, struct gadget_wrapper, gadget); -+ -+ return dwc_otg_pcd_is_lpm_enabled(d->pcd); -+} -+#endif -+ -+/** -+ * Initiates Session Request Protocol (SRP) to wakeup the host if no -+ * session is in progress. If a session is already in progress, but -+ * the device is suspended, remote wakeup signaling is started. -+ * -+ */ -+static int wakeup(struct usb_gadget *gadget) -+{ -+ struct gadget_wrapper *d; -+ -+ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, gadget); -+ -+ if (gadget == 0) { -+ return -ENODEV; -+ } else { -+ d = container_of(gadget, struct gadget_wrapper, gadget); -+ } -+ dwc_otg_pcd_wakeup(d->pcd); -+ return 0; -+} -+ -+static const struct usb_gadget_ops dwc_otg_pcd_ops = { -+ .get_frame = get_frame_number, -+ .wakeup = wakeup, -+#ifdef CONFIG_USB_DWC_OTG_LPM -+ .lpm_support = test_lpm_enabled, -+#endif -+ // current versions must always be self-powered -+}; -+ -+static int _setup(dwc_otg_pcd_t * pcd, uint8_t * bytes) -+{ -+ int retval = -DWC_E_NOT_SUPPORTED; -+ if (gadget_wrapper->driver && gadget_wrapper->driver->setup) { -+ retval = gadget_wrapper->driver->setup(&gadget_wrapper->gadget, -+ (struct usb_ctrlrequest -+ *)bytes); -+ } -+ -+ if (retval == -ENOTSUPP) { -+ retval = -DWC_E_NOT_SUPPORTED; -+ } else if (retval < 0) { -+ retval = -DWC_E_INVALID; -+ } -+ -+ return retval; -+} -+ -+#ifdef DWC_EN_ISOC -+static int _isoc_complete(dwc_otg_pcd_t * pcd, void *ep_handle, -+ void *req_handle, int proc_buf_num) -+{ -+ int i, packet_count; -+ struct usb_gadget_iso_packet_descriptor *iso_packet = 0; -+ struct usb_iso_request *iso_req = req_handle; -+ -+ if (proc_buf_num) { -+ iso_packet = iso_req->iso_packet_desc1; -+ } else { -+ iso_packet = iso_req->iso_packet_desc0; -+ } -+ packet_count = -+ dwc_otg_pcd_get_iso_packet_count(pcd, ep_handle, req_handle); -+ for (i = 0; i < packet_count; ++i) { -+ int status; -+ int actual; -+ int offset; -+ dwc_otg_pcd_get_iso_packet_params(pcd, ep_handle, req_handle, -+ i, &status, &actual, &offset); -+ switch (status) { -+ case -DWC_E_NO_DATA: -+ status = -ENODATA; -+ break; -+ default: -+ if (status) { -+ DWC_PRINTF("unknown status in isoc packet\n"); -+ } -+ -+ } -+ iso_packet[i].status = status; -+ iso_packet[i].offset = offset; -+ iso_packet[i].actual_length = actual; -+ } -+ -+ iso_req->status = 0; -+ iso_req->process_buffer(ep_handle, iso_req); -+ -+ return 0; -+} -+#endif /* DWC_EN_ISOC */ -+ -+#ifdef DWC_UTE_PER_IO -+/** -+ * Copy the contents of the extended request to the Linux usb_request's -+ * extended part and call the gadget's completion. -+ * -+ * @param pcd Pointer to the pcd structure -+ * @param ep_handle Void pointer to the usb_ep structure -+ * @param req_handle Void pointer to the usb_request structure -+ * @param status Request status returned from the portable logic -+ * @param ereq_port Void pointer to the extended request structure -+ * created in the the portable part that contains the -+ * results of the processed iso packets. -+ */ -+static int _xisoc_complete(dwc_otg_pcd_t * pcd, void *ep_handle, -+ void *req_handle, int32_t status, void *ereq_port) -+{ -+ struct dwc_ute_iso_req_ext *ereqorg = NULL; -+ struct dwc_iso_xreq_port *ereqport = NULL; -+ struct dwc_ute_iso_packet_descriptor *desc_org = NULL; -+ int i; -+ struct usb_request *req; -+ //struct dwc_ute_iso_packet_descriptor * -+ //int status = 0; -+ -+ req = (struct usb_request *)req_handle; -+ ereqorg = &req->ext_req; -+ ereqport = (struct dwc_iso_xreq_port *)ereq_port; -+ desc_org = ereqorg->per_io_frame_descs; -+ -+ if (req && req->complete) { -+ /* Copy the request data from the portable logic to our request */ -+ for (i = 0; i < ereqport->pio_pkt_count; i++) { -+ desc_org[i].actual_length = -+ ereqport->per_io_frame_descs[i].actual_length; -+ desc_org[i].status = -+ ereqport->per_io_frame_descs[i].status; -+ } -+ -+ switch (status) { -+ case -DWC_E_SHUTDOWN: -+ req->status = -ESHUTDOWN; -+ break; -+ case -DWC_E_RESTART: -+ req->status = -ECONNRESET; -+ break; -+ case -DWC_E_INVALID: -+ req->status = -EINVAL; -+ break; -+ case -DWC_E_TIMEOUT: -+ req->status = -ETIMEDOUT; -+ break; -+ default: -+ req->status = status; -+ } -+ -+ /* And call the gadget's completion */ -+ req->complete(ep_handle, req); -+ } -+ -+ return 0; -+} -+#endif /* DWC_UTE_PER_IO */ -+ -+static int _complete(dwc_otg_pcd_t * pcd, void *ep_handle, -+ void *req_handle, int32_t status, uint32_t actual) -+{ -+ struct usb_request *req = (struct usb_request *)req_handle; -+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27) -+ struct dwc_otg_pcd_ep *ep = NULL; -+#endif -+ -+ if (req && req->complete) { -+ switch (status) { -+ case -DWC_E_SHUTDOWN: -+ req->status = -ESHUTDOWN; -+ break; -+ case -DWC_E_RESTART: -+ req->status = -ECONNRESET; -+ break; -+ case -DWC_E_INVALID: -+ req->status = -EINVAL; -+ break; -+ case -DWC_E_TIMEOUT: -+ req->status = -ETIMEDOUT; -+ break; -+ default: -+ req->status = status; -+ -+ } -+ -+ req->actual = actual; -+ DWC_SPINUNLOCK(pcd->lock); -+ req->complete(ep_handle, req); -+ DWC_SPINLOCK(pcd->lock); -+ } -+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27) -+ ep = ep_from_handle(pcd, ep_handle); -+ if (GET_CORE_IF(pcd)->dma_enable) { -+ if (req->length != 0) { -+ dwc_otg_device_t *otg_dev = gadget_wrapper->pcd->otg_dev; -+ struct device *dev = NULL; -+ -+ if (otg_dev != NULL) -+ dev = DWC_OTG_OS_GETDEV(otg_dev->os_dep); -+ -+ dma_unmap_single(dev, req->dma, req->length, -+ ep->dwc_ep.is_in ? -+ DMA_TO_DEVICE: DMA_FROM_DEVICE); -+ } -+ } -+#endif -+ -+ return 0; -+} -+ -+static int _connect(dwc_otg_pcd_t * pcd, int speed) -+{ -+ gadget_wrapper->gadget.speed = speed; -+ return 0; -+} -+ -+static int _disconnect(dwc_otg_pcd_t * pcd) -+{ -+ if (gadget_wrapper->driver && gadget_wrapper->driver->disconnect) { -+ gadget_wrapper->driver->disconnect(&gadget_wrapper->gadget); -+ } -+ return 0; -+} -+ -+static int _resume(dwc_otg_pcd_t * pcd) -+{ -+ if (gadget_wrapper->driver && gadget_wrapper->driver->resume) { -+ gadget_wrapper->driver->resume(&gadget_wrapper->gadget); -+ } -+ -+ return 0; -+} -+ -+static int _suspend(dwc_otg_pcd_t * pcd) -+{ -+ if (gadget_wrapper->driver && gadget_wrapper->driver->suspend) { -+ gadget_wrapper->driver->suspend(&gadget_wrapper->gadget); -+ } -+ return 0; -+} -+ -+/** -+ * This function updates the otg values in the gadget structure. -+ */ -+static int _hnp_changed(dwc_otg_pcd_t * pcd) -+{ -+ -+ if (!gadget_wrapper->gadget.is_otg) -+ return 0; -+ -+ gadget_wrapper->gadget.b_hnp_enable = get_b_hnp_enable(pcd); -+ gadget_wrapper->gadget.a_hnp_support = get_a_hnp_support(pcd); -+ gadget_wrapper->gadget.a_alt_hnp_support = get_a_alt_hnp_support(pcd); -+ return 0; -+} -+ -+static int _reset(dwc_otg_pcd_t * pcd) -+{ -+ return 0; -+} -+ -+#ifdef DWC_UTE_CFI -+static int _cfi_setup(dwc_otg_pcd_t * pcd, void *cfi_req) -+{ -+ int retval = -DWC_E_INVALID; -+ if (gadget_wrapper->driver->cfi_feature_setup) { -+ retval = -+ gadget_wrapper->driver-> -+ cfi_feature_setup(&gadget_wrapper->gadget, -+ (struct cfi_usb_ctrlrequest *)cfi_req); -+ } -+ -+ return retval; -+} -+#endif -+ -+static const struct dwc_otg_pcd_function_ops fops = { -+ .complete = _complete, -+#ifdef DWC_EN_ISOC -+ .isoc_complete = _isoc_complete, -+#endif -+ .setup = _setup, -+ .disconnect = _disconnect, -+ .connect = _connect, -+ .resume = _resume, -+ .suspend = _suspend, -+ .hnp_changed = _hnp_changed, -+ .reset = _reset, -+#ifdef DWC_UTE_CFI -+ .cfi_setup = _cfi_setup, -+#endif -+#ifdef DWC_UTE_PER_IO -+ .xisoc_complete = _xisoc_complete, -+#endif -+}; -+ -+/** -+ * This function is the top level PCD interrupt handler. -+ */ -+static irqreturn_t dwc_otg_pcd_irq(int irq, void *dev) -+{ -+ dwc_otg_pcd_t *pcd = dev; -+ int32_t retval = IRQ_NONE; -+ -+ retval = dwc_otg_pcd_handle_intr(pcd); -+ if (retval != 0) { -+ S3C2410X_CLEAR_EINTPEND(); -+ } -+ return IRQ_RETVAL(retval); -+} -+ -+/** -+ * This function initialized the usb_ep structures to there default -+ * state. -+ * -+ * @param d Pointer on gadget_wrapper. -+ */ -+void gadget_add_eps(struct gadget_wrapper *d) -+{ -+ static const char *names[] = { -+ -+ "ep0", -+ "ep1in", -+ "ep2in", -+ "ep3in", -+ "ep4in", -+ "ep5in", -+ "ep6in", -+ "ep7in", -+ "ep8in", -+ "ep9in", -+ "ep10in", -+ "ep11in", -+ "ep12in", -+ "ep13in", -+ "ep14in", -+ "ep15in", -+ "ep1out", -+ "ep2out", -+ "ep3out", -+ "ep4out", -+ "ep5out", -+ "ep6out", -+ "ep7out", -+ "ep8out", -+ "ep9out", -+ "ep10out", -+ "ep11out", -+ "ep12out", -+ "ep13out", -+ "ep14out", -+ "ep15out" -+ }; -+ -+ int i; -+ struct usb_ep *ep; -+ int8_t dev_endpoints; -+ -+ DWC_DEBUGPL(DBG_PCDV, "%s\n", __func__); -+ -+ INIT_LIST_HEAD(&d->gadget.ep_list); -+ d->gadget.ep0 = &d->ep0; -+ d->gadget.speed = USB_SPEED_UNKNOWN; -+ -+ INIT_LIST_HEAD(&d->gadget.ep0->ep_list); -+ -+ /** -+ * Initialize the EP0 structure. -+ */ -+ ep = &d->ep0; -+ -+ /* Init the usb_ep structure. */ -+ ep->name = names[0]; -+ ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops; -+ -+ /** -+ * @todo NGS: What should the max packet size be set to -+ * here? Before EP type is set? -+ */ -+ ep->maxpacket = MAX_PACKET_SIZE; -+ dwc_otg_pcd_ep_enable(d->pcd, NULL, ep); -+ -+ list_add_tail(&ep->ep_list, &d->gadget.ep_list); -+ -+ /** -+ * Initialize the EP structures. -+ */ -+ dev_endpoints = d->pcd->core_if->dev_if->num_in_eps; -+ -+ for (i = 0; i < dev_endpoints; i++) { -+ ep = &d->in_ep[i]; -+ -+ /* Init the usb_ep structure. */ -+ ep->name = names[d->pcd->in_ep[i].dwc_ep.num]; -+ ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops; -+ -+ /** -+ * @todo NGS: What should the max packet size be set to -+ * here? Before EP type is set? -+ */ -+ ep->maxpacket = MAX_PACKET_SIZE; -+ list_add_tail(&ep->ep_list, &d->gadget.ep_list); -+ } -+ -+ dev_endpoints = d->pcd->core_if->dev_if->num_out_eps; -+ -+ for (i = 0; i < dev_endpoints; i++) { -+ ep = &d->out_ep[i]; -+ -+ /* Init the usb_ep structure. */ -+ ep->name = names[15 + d->pcd->out_ep[i].dwc_ep.num]; -+ ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops; -+ -+ /** -+ * @todo NGS: What should the max packet size be set to -+ * here? Before EP type is set? -+ */ -+ ep->maxpacket = MAX_PACKET_SIZE; -+ -+ list_add_tail(&ep->ep_list, &d->gadget.ep_list); -+ } -+ -+ /* remove ep0 from the list. There is a ep0 pointer. */ -+ list_del_init(&d->ep0.ep_list); -+ -+ d->ep0.maxpacket = MAX_EP0_SIZE; -+} -+ -+/** -+ * This function releases the Gadget device. -+ * required by device_unregister(). -+ * -+ * @todo Should this do something? Should it free the PCD? -+ */ -+static void dwc_otg_pcd_gadget_release(struct device *dev) -+{ -+ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, dev); -+} -+ -+static struct gadget_wrapper *alloc_wrapper(dwc_bus_dev_t *_dev) -+{ -+ static char pcd_name[] = "dwc_otg_pcd"; -+ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev); -+ struct gadget_wrapper *d; -+ int retval; -+ -+ d = DWC_ALLOC(sizeof(*d)); -+ if (d == NULL) { -+ return NULL; -+ } -+ -+ memset(d, 0, sizeof(*d)); -+ -+ d->gadget.name = pcd_name; -+ d->pcd = otg_dev->pcd; -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) -+ strcpy(d->gadget.dev.bus_id, "gadget"); -+#else -+ dev_set_name(&d->gadget.dev, "%s", "gadget"); -+#endif -+ -+ d->gadget.dev.parent = &_dev->dev; -+ d->gadget.dev.release = dwc_otg_pcd_gadget_release; -+ d->gadget.ops = &dwc_otg_pcd_ops; -+ d->gadget.max_speed = dwc_otg_pcd_is_dualspeed(otg_dev->pcd) ? USB_SPEED_HIGH:USB_SPEED_FULL; -+ d->gadget.is_otg = dwc_otg_pcd_is_otg(otg_dev->pcd); -+ -+ d->driver = 0; -+ /* Register the gadget device */ -+ retval = device_register(&d->gadget.dev); -+ if (retval != 0) { -+ DWC_ERROR("device_register failed\n"); -+ DWC_FREE(d); -+ return NULL; -+ } -+ -+ return d; -+} -+ -+static void free_wrapper(struct gadget_wrapper *d) -+{ -+ if (d->driver) { -+ /* should have been done already by driver model core */ -+ DWC_WARN("driver '%s' is still registered\n", -+ d->driver->driver.name); -+ usb_gadget_unregister_driver(d->driver); -+ } -+ -+ device_unregister(&d->gadget.dev); -+ DWC_FREE(d); -+} -+ -+/** -+ * This function initialized the PCD portion of the driver. -+ * -+ */ -+int pcd_init(dwc_bus_dev_t *_dev) -+{ -+ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev); -+ int retval = 0; -+ -+ DWC_DEBUGPL(DBG_PCDV, "%s(%p) otg_dev=%p\n", __func__, _dev, otg_dev); -+ -+ otg_dev->pcd = dwc_otg_pcd_init(otg_dev->core_if); -+ -+ if (!otg_dev->pcd) { -+ DWC_ERROR("dwc_otg_pcd_init failed\n"); -+ return -ENOMEM; -+ } -+ -+ otg_dev->pcd->otg_dev = otg_dev; -+ gadget_wrapper = alloc_wrapper(_dev); -+ -+ /* -+ * Initialize EP structures -+ */ -+ gadget_add_eps(gadget_wrapper); -+ /* -+ * Setup interupt handler -+ */ -+#ifdef PLATFORM_INTERFACE -+ DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n", -+ platform_get_irq(_dev, fiq_enable ? 0 : 1)); -+ retval = request_irq(platform_get_irq(_dev, fiq_enable ? 0 : 1), dwc_otg_pcd_irq, -+ IRQF_SHARED, gadget_wrapper->gadget.name, -+ otg_dev->pcd); -+ if (retval != 0) { -+ DWC_ERROR("request of irq%d failed\n", -+ platform_get_irq(_dev, fiq_enable ? 0 : 1)); -+ free_wrapper(gadget_wrapper); -+ return -EBUSY; -+ } -+#else -+ DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n", -+ _dev->irq); -+ retval = request_irq(_dev->irq, dwc_otg_pcd_irq, -+ IRQF_SHARED | IRQF_DISABLED, -+ gadget_wrapper->gadget.name, otg_dev->pcd); -+ if (retval != 0) { -+ DWC_ERROR("request of irq%d failed\n", _dev->irq); -+ free_wrapper(gadget_wrapper); -+ return -EBUSY; -+ } -+#endif -+ -+ dwc_otg_pcd_start(gadget_wrapper->pcd, &fops); -+ -+ return retval; -+} -+ -+/** -+ * Cleanup the PCD. -+ */ -+void pcd_remove(dwc_bus_dev_t *_dev) -+{ -+ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev); -+ dwc_otg_pcd_t *pcd = otg_dev->pcd; -+ -+ DWC_DEBUGPL(DBG_PCDV, "%s(%p) otg_dev %p\n", __func__, _dev, otg_dev); -+ -+ /* -+ * Free the IRQ -+ */ -+#ifdef PLATFORM_INTERFACE -+ free_irq(platform_get_irq(_dev, 0), pcd); -+#else -+ free_irq(_dev->irq, pcd); -+#endif -+ dwc_otg_pcd_remove(otg_dev->pcd); -+ free_wrapper(gadget_wrapper); -+ otg_dev->pcd = 0; -+} -+ -+/** -+ * This function registers a gadget driver with the PCD. -+ * -+ * When a driver is successfully registered, it will receive control -+ * requests including set_configuration(), which enables non-control -+ * requests. then usb traffic follows until a disconnect is reported. -+ * then a host may connect again, or the driver might get unbound. -+ * -+ * @param driver The driver being registered -+ * @param bind The bind function of gadget driver -+ */ -+ -+int usb_gadget_probe_driver(struct usb_gadget_driver *driver) -+{ -+ int retval; -+ -+ DWC_DEBUGPL(DBG_PCD, "registering gadget driver '%s'\n", -+ driver->driver.name); -+ -+ if (!driver || driver->max_speed == USB_SPEED_UNKNOWN || -+ !driver->bind || -+ !driver->unbind || !driver->disconnect || !driver->setup) { -+ DWC_DEBUGPL(DBG_PCDV, "EINVAL\n"); -+ return -EINVAL; -+ } -+ if (gadget_wrapper == 0) { -+ DWC_DEBUGPL(DBG_PCDV, "ENODEV\n"); -+ return -ENODEV; -+ } -+ if (gadget_wrapper->driver != 0) { -+ DWC_DEBUGPL(DBG_PCDV, "EBUSY (%p)\n", gadget_wrapper->driver); -+ return -EBUSY; -+ } -+ -+ /* hook up the driver */ -+ gadget_wrapper->driver = driver; -+ gadget_wrapper->gadget.dev.driver = &driver->driver; -+ -+ DWC_DEBUGPL(DBG_PCD, "bind to driver %s\n", driver->driver.name); -+ retval = driver->bind(&gadget_wrapper->gadget, gadget_wrapper->driver); -+ if (retval) { -+ DWC_ERROR("bind to driver %s --> error %d\n", -+ driver->driver.name, retval); -+ gadget_wrapper->driver = 0; -+ gadget_wrapper->gadget.dev.driver = 0; -+ return retval; -+ } -+ DWC_DEBUGPL(DBG_ANY, "registered gadget driver '%s'\n", -+ driver->driver.name); -+ return 0; -+} -+EXPORT_SYMBOL(usb_gadget_probe_driver); -+ -+/** -+ * This function unregisters a gadget driver -+ * -+ * @param driver The driver being unregistered -+ */ -+int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) -+{ -+ //DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, _driver); -+ -+ if (gadget_wrapper == 0) { -+ DWC_DEBUGPL(DBG_ANY, "%s Return(%d): s_pcd==0\n", __func__, -+ -ENODEV); -+ return -ENODEV; -+ } -+ if (driver == 0 || driver != gadget_wrapper->driver) { -+ DWC_DEBUGPL(DBG_ANY, "%s Return(%d): driver?\n", __func__, -+ -EINVAL); -+ return -EINVAL; -+ } -+ -+ driver->unbind(&gadget_wrapper->gadget); -+ gadget_wrapper->driver = 0; -+ -+ DWC_DEBUGPL(DBG_ANY, "unregistered driver '%s'\n", driver->driver.name); -+ return 0; -+} -+ -+EXPORT_SYMBOL(usb_gadget_unregister_driver); -+ -+#endif /* DWC_HOST_ONLY */ -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_regs.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_regs.h ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_regs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_regs.h 2015-11-29 09:42:39.923098428 +0100 -@@ -0,0 +1,2550 @@ -+/* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $ -+ * $Revision: #98 $ -+ * $Date: 2012/08/10 $ -+ * $Change: 2047372 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+ -+#ifndef __DWC_OTG_REGS_H__ -+#define __DWC_OTG_REGS_H__ -+ -+#include "dwc_otg_core_if.h" -+ -+/** -+ * @file -+ * -+ * This file contains the data structures for accessing the DWC_otg core registers. -+ * -+ * The application interfaces with the HS OTG core by reading from and -+ * writing to the Control and Status Register (CSR) space through the -+ * AHB Slave interface. These registers are 32 bits wide, and the -+ * addresses are 32-bit-block aligned. -+ * CSRs are classified as follows: -+ * - Core Global Registers -+ * - Device Mode Registers -+ * - Device Global Registers -+ * - Device Endpoint Specific Registers -+ * - Host Mode Registers -+ * - Host Global Registers -+ * - Host Port CSRs -+ * - Host Channel Specific Registers -+ * -+ * Only the Core Global registers can be accessed in both Device and -+ * Host modes. When the HS OTG core is operating in one mode, either -+ * Device or Host, the application must not access registers from the -+ * other mode. When the core switches from one mode to another, the -+ * registers in the new mode of operation must be reprogrammed as they -+ * would be after a power-on reset. -+ */ -+ -+/****************************************************************************/ -+/** DWC_otg Core registers . -+ * The dwc_otg_core_global_regs structure defines the size -+ * and relative field offsets for the Core Global registers. -+ */ -+typedef struct dwc_otg_core_global_regs { -+ /** OTG Control and Status Register. Offset: 000h */ -+ volatile uint32_t gotgctl; -+ /** OTG Interrupt Register. Offset: 004h */ -+ volatile uint32_t gotgint; -+ /**Core AHB Configuration Register. Offset: 008h */ -+ volatile uint32_t gahbcfg; -+ -+#define DWC_GLBINTRMASK 0x0001 -+#define DWC_DMAENABLE 0x0020 -+#define DWC_NPTXEMPTYLVL_EMPTY 0x0080 -+#define DWC_NPTXEMPTYLVL_HALFEMPTY 0x0000 -+#define DWC_PTXEMPTYLVL_EMPTY 0x0100 -+#define DWC_PTXEMPTYLVL_HALFEMPTY 0x0000 -+ -+ /**Core USB Configuration Register. Offset: 00Ch */ -+ volatile uint32_t gusbcfg; -+ /**Core Reset Register. Offset: 010h */ -+ volatile uint32_t grstctl; -+ /**Core Interrupt Register. Offset: 014h */ -+ volatile uint32_t gintsts; -+ /**Core Interrupt Mask Register. Offset: 018h */ -+ volatile uint32_t gintmsk; -+ /**Receive Status Queue Read Register (Read Only). Offset: 01Ch */ -+ volatile uint32_t grxstsr; -+ /**Receive Status Queue Read & POP Register (Read Only). Offset: 020h*/ -+ volatile uint32_t grxstsp; -+ /**Receive FIFO Size Register. Offset: 024h */ -+ volatile uint32_t grxfsiz; -+ /**Non Periodic Transmit FIFO Size Register. Offset: 028h */ -+ volatile uint32_t gnptxfsiz; -+ /**Non Periodic Transmit FIFO/Queue Status Register (Read -+ * Only). Offset: 02Ch */ -+ volatile uint32_t gnptxsts; -+ /**I2C Access Register. Offset: 030h */ -+ volatile uint32_t gi2cctl; -+ /**PHY Vendor Control Register. Offset: 034h */ -+ volatile uint32_t gpvndctl; -+ /**General Purpose Input/Output Register. Offset: 038h */ -+ volatile uint32_t ggpio; -+ /**User ID Register. Offset: 03Ch */ -+ volatile uint32_t guid; -+ /**Synopsys ID Register (Read Only). Offset: 040h */ -+ volatile uint32_t gsnpsid; -+ /**User HW Config1 Register (Read Only). Offset: 044h */ -+ volatile uint32_t ghwcfg1; -+ /**User HW Config2 Register (Read Only). Offset: 048h */ -+ volatile uint32_t ghwcfg2; -+#define DWC_SLAVE_ONLY_ARCH 0 -+#define DWC_EXT_DMA_ARCH 1 -+#define DWC_INT_DMA_ARCH 2 -+ -+#define DWC_MODE_HNP_SRP_CAPABLE 0 -+#define DWC_MODE_SRP_ONLY_CAPABLE 1 -+#define DWC_MODE_NO_HNP_SRP_CAPABLE 2 -+#define DWC_MODE_SRP_CAPABLE_DEVICE 3 -+#define DWC_MODE_NO_SRP_CAPABLE_DEVICE 4 -+#define DWC_MODE_SRP_CAPABLE_HOST 5 -+#define DWC_MODE_NO_SRP_CAPABLE_HOST 6 -+ -+ /**User HW Config3 Register (Read Only). Offset: 04Ch */ -+ volatile uint32_t ghwcfg3; -+ /**User HW Config4 Register (Read Only). Offset: 050h*/ -+ volatile uint32_t ghwcfg4; -+ /** Core LPM Configuration register Offset: 054h*/ -+ volatile uint32_t glpmcfg; -+ /** Global PowerDn Register Offset: 058h */ -+ volatile uint32_t gpwrdn; -+ /** Global DFIFO SW Config Register Offset: 05Ch */ -+ volatile uint32_t gdfifocfg; -+ /** ADP Control Register Offset: 060h */ -+ volatile uint32_t adpctl; -+ /** Reserved Offset: 064h-0FFh */ -+ volatile uint32_t reserved39[39]; -+ /** Host Periodic Transmit FIFO Size Register. Offset: 100h */ -+ volatile uint32_t hptxfsiz; -+ /** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled, -+ otherwise Device Transmit FIFO#n Register. -+ * Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15). */ -+ volatile uint32_t dtxfsiz[15]; -+} dwc_otg_core_global_regs_t; -+ -+/** -+ * This union represents the bit fields of the Core OTG Control -+ * and Status Register (GOTGCTL). Set the bits using the bit -+ * fields then write the d32 value to the register. -+ */ -+typedef union gotgctl_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned sesreqscs:1; -+ unsigned sesreq:1; -+ unsigned vbvalidoven:1; -+ unsigned vbvalidovval:1; -+ unsigned avalidoven:1; -+ unsigned avalidovval:1; -+ unsigned bvalidoven:1; -+ unsigned bvalidovval:1; -+ unsigned hstnegscs:1; -+ unsigned hnpreq:1; -+ unsigned hstsethnpen:1; -+ unsigned devhnpen:1; -+ unsigned reserved12_15:4; -+ unsigned conidsts:1; -+ unsigned dbnctime:1; -+ unsigned asesvld:1; -+ unsigned bsesvld:1; -+ unsigned otgver:1; -+ unsigned reserved1:1; -+ unsigned multvalidbc:5; -+ unsigned chirpen:1; -+ unsigned reserved28_31:4; -+ } b; -+} gotgctl_data_t; -+ -+/** -+ * This union represents the bit fields of the Core OTG Interrupt Register -+ * (GOTGINT). Set/clear the bits using the bit fields then write the d32 -+ * value to the register. -+ */ -+typedef union gotgint_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ /** Current Mode */ -+ unsigned reserved0_1:2; -+ -+ /** Session End Detected */ -+ unsigned sesenddet:1; -+ -+ unsigned reserved3_7:5; -+ -+ /** Session Request Success Status Change */ -+ unsigned sesreqsucstschng:1; -+ /** Host Negotiation Success Status Change */ -+ unsigned hstnegsucstschng:1; -+ -+ unsigned reserved10_16:7; -+ -+ /** Host Negotiation Detected */ -+ unsigned hstnegdet:1; -+ /** A-Device Timeout Change */ -+ unsigned adevtoutchng:1; -+ /** Debounce Done */ -+ unsigned debdone:1; -+ /** Multi-Valued input changed */ -+ unsigned mvic:1; -+ -+ unsigned reserved31_21:11; -+ -+ } b; -+} gotgint_data_t; -+ -+/** -+ * This union represents the bit fields of the Core AHB Configuration -+ * Register (GAHBCFG). Set/clear the bits using the bit fields then -+ * write the d32 value to the register. -+ */ -+typedef union gahbcfg_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned glblintrmsk:1; -+#define DWC_GAHBCFG_GLBINT_ENABLE 1 -+ -+ unsigned hburstlen:4; -+#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0 -+#define DWC_GAHBCFG_INT_DMA_BURST_INCR 1 -+#define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3 -+#define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5 -+#define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7 -+ -+ unsigned dmaenable:1; -+#define DWC_GAHBCFG_DMAENABLE 1 -+ unsigned reserved:1; -+ unsigned nptxfemplvl_txfemplvl:1; -+ unsigned ptxfemplvl:1; -+#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY 1 -+#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0 -+ unsigned reserved9_20:12; -+ unsigned remmemsupp:1; -+ unsigned notialldmawrit:1; -+ unsigned ahbsingle:1; -+ unsigned reserved24_31:8; -+ } b; -+} gahbcfg_data_t; -+ -+/** -+ * This union represents the bit fields of the Core USB Configuration -+ * Register (GUSBCFG). Set the bits using the bit fields then write -+ * the d32 value to the register. -+ */ -+typedef union gusbcfg_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned toutcal:3; -+ unsigned phyif:1; -+ unsigned ulpi_utmi_sel:1; -+ unsigned fsintf:1; -+ unsigned physel:1; -+ unsigned ddrsel:1; -+ unsigned srpcap:1; -+ unsigned hnpcap:1; -+ unsigned usbtrdtim:4; -+ unsigned reserved1:1; -+ unsigned phylpwrclksel:1; -+ unsigned otgutmifssel:1; -+ unsigned ulpi_fsls:1; -+ unsigned ulpi_auto_res:1; -+ unsigned ulpi_clk_sus_m:1; -+ unsigned ulpi_ext_vbus_drv:1; -+ unsigned ulpi_int_vbus_indicator:1; -+ unsigned term_sel_dl_pulse:1; -+ unsigned indicator_complement:1; -+ unsigned indicator_pass_through:1; -+ unsigned ulpi_int_prot_dis:1; -+ unsigned ic_usb_cap:1; -+ unsigned ic_traffic_pull_remove:1; -+ unsigned tx_end_delay:1; -+ unsigned force_host_mode:1; -+ unsigned force_dev_mode:1; -+ unsigned reserved31:1; -+ } b; -+} gusbcfg_data_t; -+ -+/** -+ * This union represents the bit fields of the Core Reset Register -+ * (GRSTCTL). Set/clear the bits using the bit fields then write the -+ * d32 value to the register. -+ */ -+typedef union grstctl_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ /** Core Soft Reset (CSftRst) (Device and Host) -+ * -+ * The application can flush the control logic in the -+ * entire core using this bit. This bit resets the -+ * pipelines in the AHB Clock domain as well as the -+ * PHY Clock domain. -+ * -+ * The state machines are reset to an IDLE state, the -+ * control bits in the CSRs are cleared, all the -+ * transmit FIFOs and the receive FIFO are flushed. -+ * -+ * The status mask bits that control the generation of -+ * the interrupt, are cleared, to clear the -+ * interrupt. The interrupt status bits are not -+ * cleared, so the application can get the status of -+ * any events that occurred in the core after it has -+ * set this bit. -+ * -+ * Any transactions on the AHB are terminated as soon -+ * as possible following the protocol. Any -+ * transactions on the USB are terminated immediately. -+ * -+ * The configuration settings in the CSRs are -+ * unchanged, so the software doesn't have to -+ * reprogram these registers (Device -+ * Configuration/Host Configuration/Core System -+ * Configuration/Core PHY Configuration). -+ * -+ * The application can write to this bit, any time it -+ * wants to reset the core. This is a self clearing -+ * bit and the core clears this bit after all the -+ * necessary logic is reset in the core, which may -+ * take several clocks, depending on the current state -+ * of the core. -+ */ -+ unsigned csftrst:1; -+ /** Hclk Soft Reset -+ * -+ * The application uses this bit to reset the control logic in -+ * the AHB clock domain. Only AHB clock domain pipelines are -+ * reset. -+ */ -+ unsigned hsftrst:1; -+ /** Host Frame Counter Reset (Host Only)
-+ * -+ * The application can reset the (micro)frame number -+ * counter inside the core, using this bit. When the -+ * (micro)frame counter is reset, the subsequent SOF -+ * sent out by the core, will have a (micro)frame -+ * number of 0. -+ */ -+ unsigned hstfrm:1; -+ /** In Token Sequence Learning Queue Flush -+ * (INTknQFlsh) (Device Only) -+ */ -+ unsigned intknqflsh:1; -+ /** RxFIFO Flush (RxFFlsh) (Device and Host) -+ * -+ * The application can flush the entire Receive FIFO -+ * using this bit. The application must first -+ * ensure that the core is not in the middle of a -+ * transaction. The application should write into -+ * this bit, only after making sure that neither the -+ * DMA engine is reading from the RxFIFO nor the MAC -+ * is writing the data in to the FIFO. The -+ * application should wait until the bit is cleared -+ * before performing any other operations. This bit -+ * will takes 8 clocks (slowest of PHY or AHB clock) -+ * to clear. -+ */ -+ unsigned rxfflsh:1; -+ /** TxFIFO Flush (TxFFlsh) (Device and Host). -+ * -+ * This bit is used to selectively flush a single or -+ * all transmit FIFOs. The application must first -+ * ensure that the core is not in the middle of a -+ * transaction. The application should write into -+ * this bit, only after making sure that neither the -+ * DMA engine is writing into the TxFIFO nor the MAC -+ * is reading the data out of the FIFO. The -+ * application should wait until the core clears this -+ * bit, before performing any operations. This bit -+ * will takes 8 clocks (slowest of PHY or AHB clock) -+ * to clear. -+ */ -+ unsigned txfflsh:1; -+ -+ /** TxFIFO Number (TxFNum) (Device and Host). -+ * -+ * This is the FIFO number which needs to be flushed, -+ * using the TxFIFO Flush bit. This field should not -+ * be changed until the TxFIFO Flush bit is cleared by -+ * the core. -+ * - 0x0 : Non Periodic TxFIFO Flush -+ * - 0x1 : Periodic TxFIFO #1 Flush in device mode -+ * or Periodic TxFIFO in host mode -+ * - 0x2 : Periodic TxFIFO #2 Flush in device mode. -+ * - ... -+ * - 0xF : Periodic TxFIFO #15 Flush in device mode -+ * - 0x10: Flush all the Transmit NonPeriodic and -+ * Transmit Periodic FIFOs in the core -+ */ -+ unsigned txfnum:5; -+ /** Reserved */ -+ unsigned reserved11_29:19; -+ /** DMA Request Signal. Indicated DMA request is in -+ * probress. Used for debug purpose. */ -+ unsigned dmareq:1; -+ /** AHB Master Idle. Indicates the AHB Master State -+ * Machine is in IDLE condition. */ -+ unsigned ahbidle:1; -+ } b; -+} grstctl_t; -+ -+/** -+ * This union represents the bit fields of the Core Interrupt Mask -+ * Register (GINTMSK). Set/clear the bits using the bit fields then -+ * write the d32 value to the register. -+ */ -+typedef union gintmsk_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned reserved0:1; -+ unsigned modemismatch:1; -+ unsigned otgintr:1; -+ unsigned sofintr:1; -+ unsigned rxstsqlvl:1; -+ unsigned nptxfempty:1; -+ unsigned ginnakeff:1; -+ unsigned goutnakeff:1; -+ unsigned ulpickint:1; -+ unsigned i2cintr:1; -+ unsigned erlysuspend:1; -+ unsigned usbsuspend:1; -+ unsigned usbreset:1; -+ unsigned enumdone:1; -+ unsigned isooutdrop:1; -+ unsigned eopframe:1; -+ unsigned restoredone:1; -+ unsigned epmismatch:1; -+ unsigned inepintr:1; -+ unsigned outepintr:1; -+ unsigned incomplisoin:1; -+ unsigned incomplisoout:1; -+ unsigned fetsusp:1; -+ unsigned resetdet:1; -+ unsigned portintr:1; -+ unsigned hcintr:1; -+ unsigned ptxfempty:1; -+ unsigned lpmtranrcvd:1; -+ unsigned conidstschng:1; -+ unsigned disconnect:1; -+ unsigned sessreqintr:1; -+ unsigned wkupintr:1; -+ } b; -+} gintmsk_data_t; -+/** -+ * This union represents the bit fields of the Core Interrupt Register -+ * (GINTSTS). Set/clear the bits using the bit fields then write the -+ * d32 value to the register. -+ */ -+typedef union gintsts_data { -+ /** raw register data */ -+ uint32_t d32; -+#define DWC_SOF_INTR_MASK 0x0008 -+ /** register bits */ -+ struct { -+#define DWC_HOST_MODE 1 -+ unsigned curmode:1; -+ unsigned modemismatch:1; -+ unsigned otgintr:1; -+ unsigned sofintr:1; -+ unsigned rxstsqlvl:1; -+ unsigned nptxfempty:1; -+ unsigned ginnakeff:1; -+ unsigned goutnakeff:1; -+ unsigned ulpickint:1; -+ unsigned i2cintr:1; -+ unsigned erlysuspend:1; -+ unsigned usbsuspend:1; -+ unsigned usbreset:1; -+ unsigned enumdone:1; -+ unsigned isooutdrop:1; -+ unsigned eopframe:1; -+ unsigned restoredone:1; -+ unsigned epmismatch:1; -+ unsigned inepint:1; -+ unsigned outepintr:1; -+ unsigned incomplisoin:1; -+ unsigned incomplisoout:1; -+ unsigned fetsusp:1; -+ unsigned resetdet:1; -+ unsigned portintr:1; -+ unsigned hcintr:1; -+ unsigned ptxfempty:1; -+ unsigned lpmtranrcvd:1; -+ unsigned conidstschng:1; -+ unsigned disconnect:1; -+ unsigned sessreqintr:1; -+ unsigned wkupintr:1; -+ } b; -+} gintsts_data_t; -+ -+/** -+ * This union represents the bit fields in the Device Receive Status Read and -+ * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 -+ * element then read out the bits using the bit elements. -+ */ -+typedef union device_grxsts_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned epnum:4; -+ unsigned bcnt:11; -+ unsigned dpid:2; -+ -+#define DWC_STS_DATA_UPDT 0x2 // OUT Data Packet -+#define DWC_STS_XFER_COMP 0x3 // OUT Data Transfer Complete -+ -+#define DWC_DSTS_GOUT_NAK 0x1 // Global OUT NAK -+#define DWC_DSTS_SETUP_COMP 0x4 // Setup Phase Complete -+#define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet -+ unsigned pktsts:4; -+ unsigned fn:4; -+ unsigned reserved25_31:7; -+ } b; -+} device_grxsts_data_t; -+ -+/** -+ * This union represents the bit fields in the Host Receive Status Read and -+ * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 -+ * element then read out the bits using the bit elements. -+ */ -+typedef union host_grxsts_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned chnum:4; -+ unsigned bcnt:11; -+ unsigned dpid:2; -+ -+ unsigned pktsts:4; -+#define DWC_GRXSTS_PKTSTS_IN 0x2 -+#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP 0x3 -+#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5 -+#define DWC_GRXSTS_PKTSTS_CH_HALTED 0x7 -+ -+ unsigned reserved21_31:11; -+ } b; -+} host_grxsts_data_t; -+ -+/** -+ * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, -+ * GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). Read the register into the d32 element -+ * then read out the bits using the bit elements. -+ */ -+typedef union fifosize_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned startaddr:16; -+ unsigned depth:16; -+ } b; -+} fifosize_data_t; -+ -+/** -+ * This union represents the bit fields in the Non-Periodic Transmit -+ * FIFO/Queue Status Register (GNPTXSTS). Read the register into the -+ * d32 element then read out the bits using the bit -+ * elements. -+ */ -+typedef union gnptxsts_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned nptxfspcavail:16; -+ unsigned nptxqspcavail:8; -+ /** Top of the Non-Periodic Transmit Request Queue -+ * - bit 24 - Terminate (Last entry for the selected -+ * channel/EP) -+ * - bits 26:25 - Token Type -+ * - 2'b00 - IN/OUT -+ * - 2'b01 - Zero Length OUT -+ * - 2'b10 - PING/Complete Split -+ * - 2'b11 - Channel Halt -+ * - bits 30:27 - Channel/EP Number -+ */ -+ unsigned nptxqtop_terminate:1; -+ unsigned nptxqtop_token:2; -+ unsigned nptxqtop_chnep:4; -+ unsigned reserved:1; -+ } b; -+} gnptxsts_data_t; -+ -+/** -+ * This union represents the bit fields in the Transmit -+ * FIFO Status Register (DTXFSTS). Read the register into the -+ * d32 element then read out the bits using the bit -+ * elements. -+ */ -+typedef union dtxfsts_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned txfspcavail:16; -+ unsigned reserved:16; -+ } b; -+} dtxfsts_data_t; -+ -+/** -+ * This union represents the bit fields in the I2C Control Register -+ * (I2CCTL). Read the register into the d32 element then read out the -+ * bits using the bit elements. -+ */ -+typedef union gi2cctl_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned rwdata:8; -+ unsigned regaddr:8; -+ unsigned addr:7; -+ unsigned i2cen:1; -+ unsigned ack:1; -+ unsigned i2csuspctl:1; -+ unsigned i2cdevaddr:2; -+ unsigned i2cdatse0:1; -+ unsigned reserved:1; -+ unsigned rw:1; -+ unsigned bsydne:1; -+ } b; -+} gi2cctl_data_t; -+ -+/** -+ * This union represents the bit fields in the PHY Vendor Control Register -+ * (GPVNDCTL). Read the register into the d32 element then read out the -+ * bits using the bit elements. -+ */ -+typedef union gpvndctl_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned regdata:8; -+ unsigned vctrl:8; -+ unsigned regaddr16_21:6; -+ unsigned regwr:1; -+ unsigned reserved23_24:2; -+ unsigned newregreq:1; -+ unsigned vstsbsy:1; -+ unsigned vstsdone:1; -+ unsigned reserved28_30:3; -+ unsigned disulpidrvr:1; -+ } b; -+} gpvndctl_data_t; -+ -+/** -+ * This union represents the bit fields in the General Purpose -+ * Input/Output Register (GGPIO). -+ * Read the register into the d32 element then read out the -+ * bits using the bit elements. -+ */ -+typedef union ggpio_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned gpi:16; -+ unsigned gpo:16; -+ } b; -+} ggpio_data_t; -+ -+/** -+ * This union represents the bit fields in the User ID Register -+ * (GUID). Read the register into the d32 element then read out the -+ * bits using the bit elements. -+ */ -+typedef union guid_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned rwdata:32; -+ } b; -+} guid_data_t; -+ -+/** -+ * This union represents the bit fields in the Synopsys ID Register -+ * (GSNPSID). Read the register into the d32 element then read out the -+ * bits using the bit elements. -+ */ -+typedef union gsnpsid_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned rwdata:32; -+ } b; -+} gsnpsid_data_t; -+ -+/** -+ * This union represents the bit fields in the User HW Config1 -+ * Register. Read the register into the d32 element then read -+ * out the bits using the bit elements. -+ */ -+typedef union hwcfg1_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned ep_dir0:2; -+ unsigned ep_dir1:2; -+ unsigned ep_dir2:2; -+ unsigned ep_dir3:2; -+ unsigned ep_dir4:2; -+ unsigned ep_dir5:2; -+ unsigned ep_dir6:2; -+ unsigned ep_dir7:2; -+ unsigned ep_dir8:2; -+ unsigned ep_dir9:2; -+ unsigned ep_dir10:2; -+ unsigned ep_dir11:2; -+ unsigned ep_dir12:2; -+ unsigned ep_dir13:2; -+ unsigned ep_dir14:2; -+ unsigned ep_dir15:2; -+ } b; -+} hwcfg1_data_t; -+ -+/** -+ * This union represents the bit fields in the User HW Config2 -+ * Register. Read the register into the d32 element then read -+ * out the bits using the bit elements. -+ */ -+typedef union hwcfg2_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ /* GHWCFG2 */ -+ unsigned op_mode:3; -+#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0 -+#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1 -+#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2 -+#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3 -+#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4 -+#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5 -+#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6 -+ -+ unsigned architecture:2; -+ unsigned point2point:1; -+ unsigned hs_phy_type:2; -+#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0 -+#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1 -+#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2 -+#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3 -+ -+ unsigned fs_phy_type:2; -+ unsigned num_dev_ep:4; -+ unsigned num_host_chan:4; -+ unsigned perio_ep_supported:1; -+ unsigned dynamic_fifo:1; -+ unsigned multi_proc_int:1; -+ unsigned reserved21:1; -+ unsigned nonperio_tx_q_depth:2; -+ unsigned host_perio_tx_q_depth:2; -+ unsigned dev_token_q_depth:5; -+ unsigned otg_enable_ic_usb:1; -+ } b; -+} hwcfg2_data_t; -+ -+/** -+ * This union represents the bit fields in the User HW Config3 -+ * Register. Read the register into the d32 element then read -+ * out the bits using the bit elements. -+ */ -+typedef union hwcfg3_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ /* GHWCFG3 */ -+ unsigned xfer_size_cntr_width:4; -+ unsigned packet_size_cntr_width:3; -+ unsigned otg_func:1; -+ unsigned i2c:1; -+ unsigned vendor_ctrl_if:1; -+ unsigned optional_features:1; -+ unsigned synch_reset_type:1; -+ unsigned adp_supp:1; -+ unsigned otg_enable_hsic:1; -+ unsigned bc_support:1; -+ unsigned otg_lpm_en:1; -+ unsigned dfifo_depth:16; -+ } b; -+} hwcfg3_data_t; -+ -+/** -+ * This union represents the bit fields in the User HW Config4 -+ * Register. Read the register into the d32 element then read -+ * out the bits using the bit elements. -+ */ -+typedef union hwcfg4_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned num_dev_perio_in_ep:4; -+ unsigned power_optimiz:1; -+ unsigned min_ahb_freq:1; -+ unsigned hiber:1; -+ unsigned xhiber:1; -+ unsigned reserved:6; -+ unsigned utmi_phy_data_width:2; -+ unsigned num_dev_mode_ctrl_ep:4; -+ unsigned iddig_filt_en:1; -+ unsigned vbus_valid_filt_en:1; -+ unsigned a_valid_filt_en:1; -+ unsigned b_valid_filt_en:1; -+ unsigned session_end_filt_en:1; -+ unsigned ded_fifo_en:1; -+ unsigned num_in_eps:4; -+ unsigned desc_dma:1; -+ unsigned desc_dma_dyn:1; -+ } b; -+} hwcfg4_data_t; -+ -+/** -+ * This union represents the bit fields of the Core LPM Configuration -+ * Register (GLPMCFG). Set the bits using bit fields then write -+ * the d32 value to the register. -+ */ -+typedef union glpmctl_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ /** LPM-Capable (LPMCap) (Device and Host) -+ * The application uses this bit to control -+ * the DWC_otg core LPM capabilities. -+ */ -+ unsigned lpm_cap_en:1; -+ /** LPM response programmed by application (AppL1Res) (Device) -+ * Handshake response to LPM token pre-programmed -+ * by device application software. -+ */ -+ unsigned appl_resp:1; -+ /** Host Initiated Resume Duration (HIRD) (Device and Host) -+ * In Host mode this field indicates the value of HIRD -+ * to be sent in an LPM transaction. -+ * In Device mode this field is updated with the -+ * Received LPM Token HIRD bmAttribute -+ * when an ACK/NYET/STALL response is sent -+ * to an LPM transaction. -+ */ -+ unsigned hird:4; -+ /** RemoteWakeEnable (bRemoteWake) (Device and Host) -+ * In Host mode this bit indicates the value of remote -+ * wake up to be sent in wIndex field of LPM transaction. -+ * In Device mode this field is updated with the -+ * Received LPM Token bRemoteWake bmAttribute -+ * when an ACK/NYET/STALL response is sent -+ * to an LPM transaction. -+ */ -+ unsigned rem_wkup_en:1; -+ /** Enable utmi_sleep_n (EnblSlpM) (Device and Host) -+ * The application uses this bit to control -+ * the utmi_sleep_n assertion to the PHY when in L1 state. -+ */ -+ unsigned en_utmi_sleep:1; -+ /** HIRD Threshold (HIRD_Thres) (Device and Host) -+ */ -+ unsigned hird_thres:5; -+ /** LPM Response (CoreL1Res) (Device and Host) -+ * In Host mode this bit contains handsake response to -+ * LPM transaction. -+ * In Device mode the response of the core to -+ * LPM transaction received is reflected in these two bits. -+ - 0x0 : ERROR (No handshake response) -+ - 0x1 : STALL -+ - 0x2 : NYET -+ - 0x3 : ACK -+ */ -+ unsigned lpm_resp:2; -+ /** Port Sleep Status (SlpSts) (Device and Host) -+ * This bit is set as long as a Sleep condition -+ * is present on the USB bus. -+ */ -+ unsigned prt_sleep_sts:1; -+ /** Sleep State Resume OK (L1ResumeOK) (Device and Host) -+ * Indicates that the application or host -+ * can start resume from Sleep state. -+ */ -+ unsigned sleep_state_resumeok:1; -+ /** LPM channel Index (LPM_Chnl_Indx) (Host) -+ * The channel number on which the LPM transaction -+ * has to be applied while sending -+ * an LPM transaction to the local device. -+ */ -+ unsigned lpm_chan_index:4; -+ /** LPM Retry Count (LPM_Retry_Cnt) (Host) -+ * Number host retries that would be performed -+ * if the device response was not valid response. -+ */ -+ unsigned retry_count:3; -+ /** Send LPM Transaction (SndLPM) (Host) -+ * When set by application software, -+ * an LPM transaction containing two tokens -+ * is sent. -+ */ -+ unsigned send_lpm:1; -+ /** LPM Retry status (LPM_RetryCnt_Sts) (Host) -+ * Number of LPM Host Retries still remaining -+ * to be transmitted for the current LPM sequence -+ */ -+ unsigned retry_count_sts:3; -+ unsigned reserved28_29:2; -+ /** In host mode once this bit is set, the host -+ * configures to drive the HSIC Idle state on the bus. -+ * It then waits for the device to initiate the Connect sequence. -+ * In device mode once this bit is set, the device waits for -+ * the HSIC Idle line state on the bus. Upon receving the Idle -+ * line state, it initiates the HSIC Connect sequence. -+ */ -+ unsigned hsic_connect:1; -+ /** This bit overrides and functionally inverts -+ * the if_select_hsic input port signal. -+ */ -+ unsigned inv_sel_hsic:1; -+ } b; -+} glpmcfg_data_t; -+ -+/** -+ * This union represents the bit fields of the Core ADP Timer, Control and -+ * Status Register (ADPTIMCTLSTS). Set the bits using bit fields then write -+ * the d32 value to the register. -+ */ -+typedef union adpctl_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ /** Probe Discharge (PRB_DSCHG) -+ * These bits set the times for TADP_DSCHG. -+ * These bits are defined as follows: -+ * 2'b00 - 4 msec -+ * 2'b01 - 8 msec -+ * 2'b10 - 16 msec -+ * 2'b11 - 32 msec -+ */ -+ unsigned prb_dschg:2; -+ /** Probe Delta (PRB_DELTA) -+ * These bits set the resolution for RTIM value. -+ * The bits are defined in units of 32 kHz clock cycles as follows: -+ * 2'b00 - 1 cycles -+ * 2'b01 - 2 cycles -+ * 2'b10 - 3 cycles -+ * 2'b11 - 4 cycles -+ * For example if this value is chosen to 2'b01, it means that RTIM -+ * increments for every 3(three) 32Khz clock cycles. -+ */ -+ unsigned prb_delta:2; -+ /** Probe Period (PRB_PER) -+ * These bits sets the TADP_PRD as shown in Figure 4 as follows: -+ * 2'b00 - 0.625 to 0.925 sec (typical 0.775 sec) -+ * 2'b01 - 1.25 to 1.85 sec (typical 1.55 sec) -+ * 2'b10 - 1.9 to 2.6 sec (typical 2.275 sec) -+ * 2'b11 - Reserved -+ */ -+ unsigned prb_per:2; -+ /** These bits capture the latest time it took for VBUS to ramp from -+ * VADP_SINK to VADP_PRB. -+ * 0x000 - 1 cycles -+ * 0x001 - 2 cycles -+ * 0x002 - 3 cycles -+ * etc -+ * 0x7FF - 2048 cycles -+ * A time of 1024 cycles at 32 kHz corresponds to a time of 32 msec. -+ */ -+ unsigned rtim:11; -+ /** Enable Probe (EnaPrb) -+ * When programmed to 1'b1, the core performs a probe operation. -+ * This bit is valid only if OTG_Ver = 1'b1. -+ */ -+ unsigned enaprb:1; -+ /** Enable Sense (EnaSns) -+ * When programmed to 1'b1, the core performs a Sense operation. -+ * This bit is valid only if OTG_Ver = 1'b1. -+ */ -+ unsigned enasns:1; -+ /** ADP Reset (ADPRes) -+ * When set, ADP controller is reset. -+ * This bit is valid only if OTG_Ver = 1'b1. -+ */ -+ unsigned adpres:1; -+ /** ADP Enable (ADPEn) -+ * When set, the core performs either ADP probing or sensing -+ * based on EnaPrb or EnaSns. -+ * This bit is valid only if OTG_Ver = 1'b1. -+ */ -+ unsigned adpen:1; -+ /** ADP Probe Interrupt (ADP_PRB_INT) -+ * When this bit is set, it means that the VBUS -+ * voltage is greater than VADP_PRB or VADP_PRB is reached. -+ * This bit is valid only if OTG_Ver = 1'b1. -+ */ -+ unsigned adp_prb_int:1; -+ /** -+ * ADP Sense Interrupt (ADP_SNS_INT) -+ * When this bit is set, it means that the VBUS voltage is greater than -+ * VADP_SNS value or VADP_SNS is reached. -+ * This bit is valid only if OTG_Ver = 1'b1. -+ */ -+ unsigned adp_sns_int:1; -+ /** ADP Tomeout Interrupt (ADP_TMOUT_INT) -+ * This bit is relevant only for an ADP probe. -+ * When this bit is set, it means that the ramp time has -+ * completed ie ADPCTL.RTIM has reached its terminal value -+ * of 0x7FF. This is a debug feature that allows software -+ * to read the ramp time after each cycle. -+ * This bit is valid only if OTG_Ver = 1'b1. -+ */ -+ unsigned adp_tmout_int:1; -+ /** ADP Probe Interrupt Mask (ADP_PRB_INT_MSK) -+ * When this bit is set, it unmasks the interrupt due to ADP_PRB_INT. -+ * This bit is valid only if OTG_Ver = 1'b1. -+ */ -+ unsigned adp_prb_int_msk:1; -+ /** ADP Sense Interrupt Mask (ADP_SNS_INT_MSK) -+ * When this bit is set, it unmasks the interrupt due to ADP_SNS_INT. -+ * This bit is valid only if OTG_Ver = 1'b1. -+ */ -+ unsigned adp_sns_int_msk:1; -+ /** ADP Timoeout Interrupt Mask (ADP_TMOUT_MSK) -+ * When this bit is set, it unmasks the interrupt due to ADP_TMOUT_INT. -+ * This bit is valid only if OTG_Ver = 1'b1. -+ */ -+ unsigned adp_tmout_int_msk:1; -+ /** Access Request -+ * 2'b00 - Read/Write Valid (updated by the core) -+ * 2'b01 - Read -+ * 2'b00 - Write -+ * 2'b00 - Reserved -+ */ -+ unsigned ar:2; -+ /** Reserved */ -+ unsigned reserved29_31:3; -+ } b; -+} adpctl_data_t; -+ -+//////////////////////////////////////////// -+// Device Registers -+/** -+ * Device Global Registers. Offsets 800h-BFFh -+ * -+ * The following structures define the size and relative field offsets -+ * for the Device Mode Registers. -+ * -+ * These registers are visible only in Device mode and must not be -+ * accessed in Host mode, as the results are unknown. -+ */ -+typedef struct dwc_otg_dev_global_regs { -+ /** Device Configuration Register. Offset 800h */ -+ volatile uint32_t dcfg; -+ /** Device Control Register. Offset: 804h */ -+ volatile uint32_t dctl; -+ /** Device Status Register (Read Only). Offset: 808h */ -+ volatile uint32_t dsts; -+ /** Reserved. Offset: 80Ch */ -+ uint32_t unused; -+ /** Device IN Endpoint Common Interrupt Mask -+ * Register. Offset: 810h */ -+ volatile uint32_t diepmsk; -+ /** Device OUT Endpoint Common Interrupt Mask -+ * Register. Offset: 814h */ -+ volatile uint32_t doepmsk; -+ /** Device All Endpoints Interrupt Register. Offset: 818h */ -+ volatile uint32_t daint; -+ /** Device All Endpoints Interrupt Mask Register. Offset: -+ * 81Ch */ -+ volatile uint32_t daintmsk; -+ /** Device IN Token Queue Read Register-1 (Read Only). -+ * Offset: 820h */ -+ volatile uint32_t dtknqr1; -+ /** Device IN Token Queue Read Register-2 (Read Only). -+ * Offset: 824h */ -+ volatile uint32_t dtknqr2; -+ /** Device VBUS discharge Register. Offset: 828h */ -+ volatile uint32_t dvbusdis; -+ /** Device VBUS Pulse Register. Offset: 82Ch */ -+ volatile uint32_t dvbuspulse; -+ /** Device IN Token Queue Read Register-3 (Read Only). / -+ * Device Thresholding control register (Read/Write) -+ * Offset: 830h */ -+ volatile uint32_t dtknqr3_dthrctl; -+ /** Device IN Token Queue Read Register-4 (Read Only). / -+ * Device IN EPs empty Inr. Mask Register (Read/Write) -+ * Offset: 834h */ -+ volatile uint32_t dtknqr4_fifoemptymsk; -+ /** Device Each Endpoint Interrupt Register (Read Only). / -+ * Offset: 838h */ -+ volatile uint32_t deachint; -+ /** Device Each Endpoint Interrupt mask Register (Read/Write). / -+ * Offset: 83Ch */ -+ volatile uint32_t deachintmsk; -+ /** Device Each In Endpoint Interrupt mask Register (Read/Write). / -+ * Offset: 840h */ -+ volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS]; -+ /** Device Each Out Endpoint Interrupt mask Register (Read/Write). / -+ * Offset: 880h */ -+ volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS]; -+} dwc_otg_device_global_regs_t; -+ -+/** -+ * This union represents the bit fields in the Device Configuration -+ * Register. Read the register into the d32 member then -+ * set/clear the bits using the bit elements. Write the -+ * d32 member to the dcfg register. -+ */ -+typedef union dcfg_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ /** Device Speed */ -+ unsigned devspd:2; -+ /** Non Zero Length Status OUT Handshake */ -+ unsigned nzstsouthshk:1; -+#define DWC_DCFG_SEND_STALL 1 -+ -+ unsigned ena32khzs:1; -+ /** Device Addresses */ -+ unsigned devaddr:7; -+ /** Periodic Frame Interval */ -+ unsigned perfrint:2; -+#define DWC_DCFG_FRAME_INTERVAL_80 0 -+#define DWC_DCFG_FRAME_INTERVAL_85 1 -+#define DWC_DCFG_FRAME_INTERVAL_90 2 -+#define DWC_DCFG_FRAME_INTERVAL_95 3 -+ -+ /** Enable Device OUT NAK for bulk in DDMA mode */ -+ unsigned endevoutnak:1; -+ -+ unsigned reserved14_17:4; -+ /** In Endpoint Mis-match count */ -+ unsigned epmscnt:5; -+ /** Enable Descriptor DMA in Device mode */ -+ unsigned descdma:1; -+ unsigned perschintvl:2; -+ unsigned resvalid:6; -+ } b; -+} dcfg_data_t; -+ -+/** -+ * This union represents the bit fields in the Device Control -+ * Register. Read the register into the d32 member then -+ * set/clear the bits using the bit elements. -+ */ -+typedef union dctl_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ /** Remote Wakeup */ -+ unsigned rmtwkupsig:1; -+ /** Soft Disconnect */ -+ unsigned sftdiscon:1; -+ /** Global Non-Periodic IN NAK Status */ -+ unsigned gnpinnaksts:1; -+ /** Global OUT NAK Status */ -+ unsigned goutnaksts:1; -+ /** Test Control */ -+ unsigned tstctl:3; -+ /** Set Global Non-Periodic IN NAK */ -+ unsigned sgnpinnak:1; -+ /** Clear Global Non-Periodic IN NAK */ -+ unsigned cgnpinnak:1; -+ /** Set Global OUT NAK */ -+ unsigned sgoutnak:1; -+ /** Clear Global OUT NAK */ -+ unsigned cgoutnak:1; -+ /** Power-On Programming Done */ -+ unsigned pwronprgdone:1; -+ /** Reserved */ -+ unsigned reserved:1; -+ /** Global Multi Count */ -+ unsigned gmc:2; -+ /** Ignore Frame Number for ISOC EPs */ -+ unsigned ifrmnum:1; -+ /** NAK on Babble */ -+ unsigned nakonbble:1; -+ /** Enable Continue on BNA */ -+ unsigned encontonbna:1; -+ -+ unsigned reserved18_31:14; -+ } b; -+} dctl_data_t; -+ -+/** -+ * This union represents the bit fields in the Device Status -+ * Register. Read the register into the d32 member then -+ * set/clear the bits using the bit elements. -+ */ -+typedef union dsts_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ /** Suspend Status */ -+ unsigned suspsts:1; -+ /** Enumerated Speed */ -+ unsigned enumspd:2; -+#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 -+#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 -+#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ 2 -+#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ 3 -+ /** Erratic Error */ -+ unsigned errticerr:1; -+ unsigned reserved4_7:4; -+ /** Frame or Microframe Number of the received SOF */ -+ unsigned soffn:14; -+ unsigned reserved22_31:10; -+ } b; -+} dsts_data_t; -+ -+/** -+ * This union represents the bit fields in the Device IN EP Interrupt -+ * Register and the Device IN EP Common Mask Register. -+ * -+ * - Read the register into the d32 member then set/clear the -+ * bits using the bit elements. -+ */ -+typedef union diepint_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ /** Transfer complete mask */ -+ unsigned xfercompl:1; -+ /** Endpoint disable mask */ -+ unsigned epdisabled:1; -+ /** AHB Error mask */ -+ unsigned ahberr:1; -+ /** TimeOUT Handshake mask (non-ISOC EPs) */ -+ unsigned timeout:1; -+ /** IN Token received with TxF Empty mask */ -+ unsigned intktxfemp:1; -+ /** IN Token Received with EP mismatch mask */ -+ unsigned intknepmis:1; -+ /** IN Endpoint NAK Effective mask */ -+ unsigned inepnakeff:1; -+ /** Reserved */ -+ unsigned emptyintr:1; -+ -+ unsigned txfifoundrn:1; -+ -+ /** BNA Interrupt mask */ -+ unsigned bna:1; -+ -+ unsigned reserved10_12:3; -+ /** BNA Interrupt mask */ -+ unsigned nak:1; -+ -+ unsigned reserved14_31:18; -+ } b; -+} diepint_data_t; -+ -+/** -+ * This union represents the bit fields in the Device IN EP -+ * Common/Dedicated Interrupt Mask Register. -+ */ -+typedef union diepint_data diepmsk_data_t; -+ -+/** -+ * This union represents the bit fields in the Device OUT EP Interrupt -+ * Registerand Device OUT EP Common Interrupt Mask Register. -+ * -+ * - Read the register into the d32 member then set/clear the -+ * bits using the bit elements. -+ */ -+typedef union doepint_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ /** Transfer complete */ -+ unsigned xfercompl:1; -+ /** Endpoint disable */ -+ unsigned epdisabled:1; -+ /** AHB Error */ -+ unsigned ahberr:1; -+ /** Setup Phase Done (contorl EPs) */ -+ unsigned setup:1; -+ /** OUT Token Received when Endpoint Disabled */ -+ unsigned outtknepdis:1; -+ -+ unsigned stsphsercvd:1; -+ /** Back-to-Back SETUP Packets Received */ -+ unsigned back2backsetup:1; -+ -+ unsigned reserved7:1; -+ /** OUT packet Error */ -+ unsigned outpkterr:1; -+ /** BNA Interrupt */ -+ unsigned bna:1; -+ -+ unsigned reserved10:1; -+ /** Packet Drop Status */ -+ unsigned pktdrpsts:1; -+ /** Babble Interrupt */ -+ unsigned babble:1; -+ /** NAK Interrupt */ -+ unsigned nak:1; -+ /** NYET Interrupt */ -+ unsigned nyet:1; -+ /** Bit indicating setup packet received */ -+ unsigned sr:1; -+ -+ unsigned reserved16_31:16; -+ } b; -+} doepint_data_t; -+ -+/** -+ * This union represents the bit fields in the Device OUT EP -+ * Common/Dedicated Interrupt Mask Register. -+ */ -+typedef union doepint_data doepmsk_data_t; -+ -+/** -+ * This union represents the bit fields in the Device All EP Interrupt -+ * and Mask Registers. -+ * - Read the register into the d32 member then set/clear the -+ * bits using the bit elements. -+ */ -+typedef union daint_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ /** IN Endpoint bits */ -+ unsigned in:16; -+ /** OUT Endpoint bits */ -+ unsigned out:16; -+ } ep; -+ struct { -+ /** IN Endpoint bits */ -+ unsigned inep0:1; -+ unsigned inep1:1; -+ unsigned inep2:1; -+ unsigned inep3:1; -+ unsigned inep4:1; -+ unsigned inep5:1; -+ unsigned inep6:1; -+ unsigned inep7:1; -+ unsigned inep8:1; -+ unsigned inep9:1; -+ unsigned inep10:1; -+ unsigned inep11:1; -+ unsigned inep12:1; -+ unsigned inep13:1; -+ unsigned inep14:1; -+ unsigned inep15:1; -+ /** OUT Endpoint bits */ -+ unsigned outep0:1; -+ unsigned outep1:1; -+ unsigned outep2:1; -+ unsigned outep3:1; -+ unsigned outep4:1; -+ unsigned outep5:1; -+ unsigned outep6:1; -+ unsigned outep7:1; -+ unsigned outep8:1; -+ unsigned outep9:1; -+ unsigned outep10:1; -+ unsigned outep11:1; -+ unsigned outep12:1; -+ unsigned outep13:1; -+ unsigned outep14:1; -+ unsigned outep15:1; -+ } b; -+} daint_data_t; -+ -+/** -+ * This union represents the bit fields in the Device IN Token Queue -+ * Read Registers. -+ * - Read the register into the d32 member. -+ * - READ-ONLY Register -+ */ -+typedef union dtknq1_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ /** In Token Queue Write Pointer */ -+ unsigned intknwptr:5; -+ /** Reserved */ -+ unsigned reserved05_06:2; -+ /** write pointer has wrapped. */ -+ unsigned wrap_bit:1; -+ /** EP Numbers of IN Tokens 0 ... 4 */ -+ unsigned epnums0_5:24; -+ } b; -+} dtknq1_data_t; -+ -+/** -+ * This union represents Threshold control Register -+ * - Read and write the register into the d32 member. -+ * - READ-WRITABLE Register -+ */ -+typedef union dthrctl_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ /** non ISO Tx Thr. Enable */ -+ unsigned non_iso_thr_en:1; -+ /** ISO Tx Thr. Enable */ -+ unsigned iso_thr_en:1; -+ /** Tx Thr. Length */ -+ unsigned tx_thr_len:9; -+ /** AHB Threshold ratio */ -+ unsigned ahb_thr_ratio:2; -+ /** Reserved */ -+ unsigned reserved13_15:3; -+ /** Rx Thr. Enable */ -+ unsigned rx_thr_en:1; -+ /** Rx Thr. Length */ -+ unsigned rx_thr_len:9; -+ unsigned reserved26:1; -+ /** Arbiter Parking Enable*/ -+ unsigned arbprken:1; -+ /** Reserved */ -+ unsigned reserved28_31:4; -+ } b; -+} dthrctl_data_t; -+ -+/** -+ * Device Logical IN Endpoint-Specific Registers. Offsets -+ * 900h-AFCh -+ * -+ * There will be one set of endpoint registers per logical endpoint -+ * implemented. -+ * -+ * These registers are visible only in Device mode and must not be -+ * accessed in Host mode, as the results are unknown. -+ */ -+typedef struct dwc_otg_dev_in_ep_regs { -+ /** Device IN Endpoint Control Register. Offset:900h + -+ * (ep_num * 20h) + 00h */ -+ volatile uint32_t diepctl; -+ /** Reserved. Offset:900h + (ep_num * 20h) + 04h */ -+ uint32_t reserved04; -+ /** Device IN Endpoint Interrupt Register. Offset:900h + -+ * (ep_num * 20h) + 08h */ -+ volatile uint32_t diepint; -+ /** Reserved. Offset:900h + (ep_num * 20h) + 0Ch */ -+ uint32_t reserved0C; -+ /** Device IN Endpoint Transfer Size -+ * Register. Offset:900h + (ep_num * 20h) + 10h */ -+ volatile uint32_t dieptsiz; -+ /** Device IN Endpoint DMA Address Register. Offset:900h + -+ * (ep_num * 20h) + 14h */ -+ volatile uint32_t diepdma; -+ /** Device IN Endpoint Transmit FIFO Status Register. Offset:900h + -+ * (ep_num * 20h) + 18h */ -+ volatile uint32_t dtxfsts; -+ /** Device IN Endpoint DMA Buffer Register. Offset:900h + -+ * (ep_num * 20h) + 1Ch */ -+ volatile uint32_t diepdmab; -+} dwc_otg_dev_in_ep_regs_t; -+ -+/** -+ * Device Logical OUT Endpoint-Specific Registers. Offsets: -+ * B00h-CFCh -+ * -+ * There will be one set of endpoint registers per logical endpoint -+ * implemented. -+ * -+ * These registers are visible only in Device mode and must not be -+ * accessed in Host mode, as the results are unknown. -+ */ -+typedef struct dwc_otg_dev_out_ep_regs { -+ /** Device OUT Endpoint Control Register. Offset:B00h + -+ * (ep_num * 20h) + 00h */ -+ volatile uint32_t doepctl; -+ /** Reserved. Offset:B00h + (ep_num * 20h) + 04h */ -+ uint32_t reserved04; -+ /** Device OUT Endpoint Interrupt Register. Offset:B00h + -+ * (ep_num * 20h) + 08h */ -+ volatile uint32_t doepint; -+ /** Reserved. Offset:B00h + (ep_num * 20h) + 0Ch */ -+ uint32_t reserved0C; -+ /** Device OUT Endpoint Transfer Size Register. Offset: -+ * B00h + (ep_num * 20h) + 10h */ -+ volatile uint32_t doeptsiz; -+ /** Device OUT Endpoint DMA Address Register. Offset:B00h -+ * + (ep_num * 20h) + 14h */ -+ volatile uint32_t doepdma; -+ /** Reserved. Offset:B00h + * (ep_num * 20h) + 18h */ -+ uint32_t unused; -+ /** Device OUT Endpoint DMA Buffer Register. Offset:B00h -+ * + (ep_num * 20h) + 1Ch */ -+ uint32_t doepdmab; -+} dwc_otg_dev_out_ep_regs_t; -+ -+/** -+ * This union represents the bit fields in the Device EP Control -+ * Register. Read the register into the d32 member then -+ * set/clear the bits using the bit elements. -+ */ -+typedef union depctl_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ /** Maximum Packet Size -+ * IN/OUT EPn -+ * IN/OUT EP0 - 2 bits -+ * 2'b00: 64 Bytes -+ * 2'b01: 32 -+ * 2'b10: 16 -+ * 2'b11: 8 */ -+ unsigned mps:11; -+#define DWC_DEP0CTL_MPS_64 0 -+#define DWC_DEP0CTL_MPS_32 1 -+#define DWC_DEP0CTL_MPS_16 2 -+#define DWC_DEP0CTL_MPS_8 3 -+ -+ /** Next Endpoint -+ * IN EPn/IN EP0 -+ * OUT EPn/OUT EP0 - reserved */ -+ unsigned nextep:4; -+ -+ /** USB Active Endpoint */ -+ unsigned usbactep:1; -+ -+ /** Endpoint DPID (INTR/Bulk IN and OUT endpoints) -+ * This field contains the PID of the packet going to -+ * be received or transmitted on this endpoint. The -+ * application should program the PID of the first -+ * packet going to be received or transmitted on this -+ * endpoint , after the endpoint is -+ * activated. Application use the SetD1PID and -+ * SetD0PID fields of this register to program either -+ * D0 or D1 PID. -+ * -+ * The encoding for this field is -+ * - 0: D0 -+ * - 1: D1 -+ */ -+ unsigned dpid:1; -+ -+ /** NAK Status */ -+ unsigned naksts:1; -+ -+ /** Endpoint Type -+ * 2'b00: Control -+ * 2'b01: Isochronous -+ * 2'b10: Bulk -+ * 2'b11: Interrupt */ -+ unsigned eptype:2; -+ -+ /** Snoop Mode -+ * OUT EPn/OUT EP0 -+ * IN EPn/IN EP0 - reserved */ -+ unsigned snp:1; -+ -+ /** Stall Handshake */ -+ unsigned stall:1; -+ -+ /** Tx Fifo Number -+ * IN EPn/IN EP0 -+ * OUT EPn/OUT EP0 - reserved */ -+ unsigned txfnum:4; -+ -+ /** Clear NAK */ -+ unsigned cnak:1; -+ /** Set NAK */ -+ unsigned snak:1; -+ /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints) -+ * Writing to this field sets the Endpoint DPID (DPID) -+ * field in this register to DATA0. Set Even -+ * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints) -+ * Writing to this field sets the Even/Odd -+ * (micro)frame (EO_FrNum) field to even (micro) -+ * frame. -+ */ -+ unsigned setd0pid:1; -+ /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints) -+ * Writing to this field sets the Endpoint DPID (DPID) -+ * field in this register to DATA1 Set Odd -+ * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints) -+ * Writing to this field sets the Even/Odd -+ * (micro)frame (EO_FrNum) field to odd (micro) frame. -+ */ -+ unsigned setd1pid:1; -+ -+ /** Endpoint Disable */ -+ unsigned epdis:1; -+ /** Endpoint Enable */ -+ unsigned epena:1; -+ } b; -+} depctl_data_t; -+ -+/** -+ * This union represents the bit fields in the Device EP Transfer -+ * Size Register. Read the register into the d32 member then -+ * set/clear the bits using the bit elements. -+ */ -+typedef union deptsiz_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ /** Transfer size */ -+ unsigned xfersize:19; -+/** Max packet count for EP (pow(2,10)-1) */ -+#define MAX_PKT_CNT 1023 -+ /** Packet Count */ -+ unsigned pktcnt:10; -+ /** Multi Count - Periodic IN endpoints */ -+ unsigned mc:2; -+ unsigned reserved:1; -+ } b; -+} deptsiz_data_t; -+ -+/** -+ * This union represents the bit fields in the Device EP 0 Transfer -+ * Size Register. Read the register into the d32 member then -+ * set/clear the bits using the bit elements. -+ */ -+typedef union deptsiz0_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ /** Transfer size */ -+ unsigned xfersize:7; -+ /** Reserved */ -+ unsigned reserved7_18:12; -+ /** Packet Count */ -+ unsigned pktcnt:2; -+ /** Reserved */ -+ unsigned reserved21_28:8; -+ /**Setup Packet Count (DOEPTSIZ0 Only) */ -+ unsigned supcnt:2; -+ unsigned reserved31; -+ } b; -+} deptsiz0_data_t; -+ -+///////////////////////////////////////////////// -+// DMA Descriptor Specific Structures -+// -+ -+/** Buffer status definitions */ -+ -+#define BS_HOST_READY 0x0 -+#define BS_DMA_BUSY 0x1 -+#define BS_DMA_DONE 0x2 -+#define BS_HOST_BUSY 0x3 -+ -+/** Receive/Transmit status definitions */ -+ -+#define RTS_SUCCESS 0x0 -+#define RTS_BUFFLUSH 0x1 -+#define RTS_RESERVED 0x2 -+#define RTS_BUFERR 0x3 -+ -+/** -+ * This union represents the bit fields in the DMA Descriptor -+ * status quadlet. Read the quadlet into the d32 member then -+ * set/clear the bits using the bit, b_iso_out and -+ * b_iso_in elements. -+ */ -+typedef union dev_dma_desc_sts { -+ /** raw register data */ -+ uint32_t d32; -+ /** quadlet bits */ -+ struct { -+ /** Received number of bytes */ -+ unsigned bytes:16; -+ /** NAK bit - only for OUT EPs */ -+ unsigned nak:1; -+ unsigned reserved17_22:6; -+ /** Multiple Transfer - only for OUT EPs */ -+ unsigned mtrf:1; -+ /** Setup Packet received - only for OUT EPs */ -+ unsigned sr:1; -+ /** Interrupt On Complete */ -+ unsigned ioc:1; -+ /** Short Packet */ -+ unsigned sp:1; -+ /** Last */ -+ unsigned l:1; -+ /** Receive Status */ -+ unsigned sts:2; -+ /** Buffer Status */ -+ unsigned bs:2; -+ } b; -+ -+//#ifdef DWC_EN_ISOC -+ /** iso out quadlet bits */ -+ struct { -+ /** Received number of bytes */ -+ unsigned rxbytes:11; -+ -+ unsigned reserved11:1; -+ /** Frame Number */ -+ unsigned framenum:11; -+ /** Received ISO Data PID */ -+ unsigned pid:2; -+ /** Interrupt On Complete */ -+ unsigned ioc:1; -+ /** Short Packet */ -+ unsigned sp:1; -+ /** Last */ -+ unsigned l:1; -+ /** Receive Status */ -+ unsigned rxsts:2; -+ /** Buffer Status */ -+ unsigned bs:2; -+ } b_iso_out; -+ -+ /** iso in quadlet bits */ -+ struct { -+ /** Transmited number of bytes */ -+ unsigned txbytes:12; -+ /** Frame Number */ -+ unsigned framenum:11; -+ /** Transmited ISO Data PID */ -+ unsigned pid:2; -+ /** Interrupt On Complete */ -+ unsigned ioc:1; -+ /** Short Packet */ -+ unsigned sp:1; -+ /** Last */ -+ unsigned l:1; -+ /** Transmit Status */ -+ unsigned txsts:2; -+ /** Buffer Status */ -+ unsigned bs:2; -+ } b_iso_in; -+//#endif /* DWC_EN_ISOC */ -+} dev_dma_desc_sts_t; -+ -+/** -+ * DMA Descriptor structure -+ * -+ * DMA Descriptor structure contains two quadlets: -+ * Status quadlet and Data buffer pointer. -+ */ -+typedef struct dwc_otg_dev_dma_desc { -+ /** DMA Descriptor status quadlet */ -+ dev_dma_desc_sts_t status; -+ /** DMA Descriptor data buffer pointer */ -+ uint32_t buf; -+} dwc_otg_dev_dma_desc_t; -+ -+/** -+ * The dwc_otg_dev_if structure contains information needed to manage -+ * the DWC_otg controller acting in device mode. It represents the -+ * programming view of the device-specific aspects of the controller. -+ */ -+typedef struct dwc_otg_dev_if { -+ /** Pointer to device Global registers. -+ * Device Global Registers starting at offset 800h -+ */ -+ dwc_otg_device_global_regs_t *dev_global_regs; -+#define DWC_DEV_GLOBAL_REG_OFFSET 0x800 -+ -+ /** -+ * Device Logical IN Endpoint-Specific Registers 900h-AFCh -+ */ -+ dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS]; -+#define DWC_DEV_IN_EP_REG_OFFSET 0x900 -+#define DWC_EP_REG_OFFSET 0x20 -+ -+ /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */ -+ dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS]; -+#define DWC_DEV_OUT_EP_REG_OFFSET 0xB00 -+ -+ /* Device configuration information */ -+ uint8_t speed; /**< Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS */ -+ uint8_t num_in_eps; /**< Number # of Tx EP range: 0-15 exept ep0 */ -+ uint8_t num_out_eps; /**< Number # of Rx EP range: 0-15 exept ep 0*/ -+ -+ /** Size of periodic FIFOs (Bytes) */ -+ uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS]; -+ -+ /** Size of Tx FIFOs (Bytes) */ -+ uint16_t tx_fifo_size[MAX_TX_FIFOS]; -+ -+ /** Thresholding enable flags and length varaiables **/ -+ uint16_t rx_thr_en; -+ uint16_t iso_tx_thr_en; -+ uint16_t non_iso_tx_thr_en; -+ -+ uint16_t rx_thr_length; -+ uint16_t tx_thr_length; -+ -+ /** -+ * Pointers to the DMA Descriptors for EP0 Control -+ * transfers (virtual and physical) -+ */ -+ -+ /** 2 descriptors for SETUP packets */ -+ dwc_dma_t dma_setup_desc_addr[2]; -+ dwc_otg_dev_dma_desc_t *setup_desc_addr[2]; -+ -+ /** Pointer to Descriptor with latest SETUP packet */ -+ dwc_otg_dev_dma_desc_t *psetup; -+ -+ /** Index of current SETUP handler descriptor */ -+ uint32_t setup_desc_index; -+ -+ /** Descriptor for Data In or Status In phases */ -+ dwc_dma_t dma_in_desc_addr; -+ dwc_otg_dev_dma_desc_t *in_desc_addr; -+ -+ /** Descriptor for Data Out or Status Out phases */ -+ dwc_dma_t dma_out_desc_addr; -+ dwc_otg_dev_dma_desc_t *out_desc_addr; -+ -+ /** Setup Packet Detected - if set clear NAK when queueing */ -+ uint32_t spd; -+ /** Isoc ep pointer on which incomplete happens */ -+ void *isoc_ep; -+ -+} dwc_otg_dev_if_t; -+ -+///////////////////////////////////////////////// -+// Host Mode Register Structures -+// -+/** -+ * The Host Global Registers structure defines the size and relative -+ * field offsets for the Host Mode Global Registers. Host Global -+ * Registers offsets 400h-7FFh. -+*/ -+typedef struct dwc_otg_host_global_regs { -+ /** Host Configuration Register. Offset: 400h */ -+ volatile uint32_t hcfg; -+ /** Host Frame Interval Register. Offset: 404h */ -+ volatile uint32_t hfir; -+ /** Host Frame Number / Frame Remaining Register. Offset: 408h */ -+ volatile uint32_t hfnum; -+ /** Reserved. Offset: 40Ch */ -+ uint32_t reserved40C; -+ /** Host Periodic Transmit FIFO/ Queue Status Register. Offset: 410h */ -+ volatile uint32_t hptxsts; -+ /** Host All Channels Interrupt Register. Offset: 414h */ -+ volatile uint32_t haint; -+ /** Host All Channels Interrupt Mask Register. Offset: 418h */ -+ volatile uint32_t haintmsk; -+ /** Host Frame List Base Address Register . Offset: 41Ch */ -+ volatile uint32_t hflbaddr; -+} dwc_otg_host_global_regs_t; -+ -+/** -+ * This union represents the bit fields in the Host Configuration Register. -+ * Read the register into the d32 member then set/clear the bits using -+ * the bit elements. Write the d32 member to the hcfg register. -+ */ -+typedef union hcfg_data { -+ /** raw register data */ -+ uint32_t d32; -+ -+ /** register bits */ -+ struct { -+ /** FS/LS Phy Clock Select */ -+ unsigned fslspclksel:2; -+#define DWC_HCFG_30_60_MHZ 0 -+#define DWC_HCFG_48_MHZ 1 -+#define DWC_HCFG_6_MHZ 2 -+ -+ /** FS/LS Only Support */ -+ unsigned fslssupp:1; -+ unsigned reserved3_6:4; -+ /** Enable 32-KHz Suspend Mode */ -+ unsigned ena32khzs:1; -+ /** Resume Validation Periiod */ -+ unsigned resvalid:8; -+ unsigned reserved16_22:7; -+ /** Enable Scatter/gather DMA in Host mode */ -+ unsigned descdma:1; -+ /** Frame List Entries */ -+ unsigned frlisten:2; -+ /** Enable Periodic Scheduling */ -+ unsigned perschedena:1; -+ unsigned reserved27_30:4; -+ unsigned modechtimen:1; -+ } b; -+} hcfg_data_t; -+ -+/** -+ * This union represents the bit fields in the Host Frame Remaing/Number -+ * Register. -+ */ -+typedef union hfir_data { -+ /** raw register data */ -+ uint32_t d32; -+ -+ /** register bits */ -+ struct { -+ unsigned frint:16; -+ unsigned hfirrldctrl:1; -+ unsigned reserved:15; -+ } b; -+} hfir_data_t; -+ -+/** -+ * This union represents the bit fields in the Host Frame Remaing/Number -+ * Register. -+ */ -+typedef union hfnum_data { -+ /** raw register data */ -+ uint32_t d32; -+ -+ /** register bits */ -+ struct { -+ unsigned frnum:16; -+#define DWC_HFNUM_MAX_FRNUM 0x3FFF -+ unsigned frrem:16; -+ } b; -+} hfnum_data_t; -+ -+typedef union hptxsts_data { -+ /** raw register data */ -+ uint32_t d32; -+ -+ /** register bits */ -+ struct { -+ unsigned ptxfspcavail:16; -+ unsigned ptxqspcavail:8; -+ /** Top of the Periodic Transmit Request Queue -+ * - bit 24 - Terminate (last entry for the selected channel) -+ * - bits 26:25 - Token Type -+ * - 2'b00 - Zero length -+ * - 2'b01 - Ping -+ * - 2'b10 - Disable -+ * - bits 30:27 - Channel Number -+ * - bit 31 - Odd/even microframe -+ */ -+ unsigned ptxqtop_terminate:1; -+ unsigned ptxqtop_token:2; -+ unsigned ptxqtop_chnum:4; -+ unsigned ptxqtop_odd:1; -+ } b; -+} hptxsts_data_t; -+ -+/** -+ * This union represents the bit fields in the Host Port Control and Status -+ * Register. Read the register into the d32 member then set/clear the -+ * bits using the bit elements. Write the d32 member to the -+ * hprt0 register. -+ */ -+typedef union hprt0_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned prtconnsts:1; -+ unsigned prtconndet:1; -+ unsigned prtena:1; -+ unsigned prtenchng:1; -+ unsigned prtovrcurract:1; -+ unsigned prtovrcurrchng:1; -+ unsigned prtres:1; -+ unsigned prtsusp:1; -+ unsigned prtrst:1; -+ unsigned reserved9:1; -+ unsigned prtlnsts:2; -+ unsigned prtpwr:1; -+ unsigned prttstctl:4; -+ unsigned prtspd:2; -+#define DWC_HPRT0_PRTSPD_HIGH_SPEED 0 -+#define DWC_HPRT0_PRTSPD_FULL_SPEED 1 -+#define DWC_HPRT0_PRTSPD_LOW_SPEED 2 -+ unsigned reserved19_31:13; -+ } b; -+} hprt0_data_t; -+ -+/** -+ * This union represents the bit fields in the Host All Interrupt -+ * Register. -+ */ -+typedef union haint_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned ch0:1; -+ unsigned ch1:1; -+ unsigned ch2:1; -+ unsigned ch3:1; -+ unsigned ch4:1; -+ unsigned ch5:1; -+ unsigned ch6:1; -+ unsigned ch7:1; -+ unsigned ch8:1; -+ unsigned ch9:1; -+ unsigned ch10:1; -+ unsigned ch11:1; -+ unsigned ch12:1; -+ unsigned ch13:1; -+ unsigned ch14:1; -+ unsigned ch15:1; -+ unsigned reserved:16; -+ } b; -+ -+ struct { -+ unsigned chint:16; -+ unsigned reserved:16; -+ } b2; -+} haint_data_t; -+ -+/** -+ * This union represents the bit fields in the Host All Interrupt -+ * Register. -+ */ -+typedef union haintmsk_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned ch0:1; -+ unsigned ch1:1; -+ unsigned ch2:1; -+ unsigned ch3:1; -+ unsigned ch4:1; -+ unsigned ch5:1; -+ unsigned ch6:1; -+ unsigned ch7:1; -+ unsigned ch8:1; -+ unsigned ch9:1; -+ unsigned ch10:1; -+ unsigned ch11:1; -+ unsigned ch12:1; -+ unsigned ch13:1; -+ unsigned ch14:1; -+ unsigned ch15:1; -+ unsigned reserved:16; -+ } b; -+ -+ struct { -+ unsigned chint:16; -+ unsigned reserved:16; -+ } b2; -+} haintmsk_data_t; -+ -+/** -+ * Host Channel Specific Registers. 500h-5FCh -+ */ -+typedef struct dwc_otg_hc_regs { -+ /** Host Channel 0 Characteristic Register. Offset: 500h + (chan_num * 20h) + 00h */ -+ volatile uint32_t hcchar; -+ /** Host Channel 0 Split Control Register. Offset: 500h + (chan_num * 20h) + 04h */ -+ volatile uint32_t hcsplt; -+ /** Host Channel 0 Interrupt Register. Offset: 500h + (chan_num * 20h) + 08h */ -+ volatile uint32_t hcint; -+ /** Host Channel 0 Interrupt Mask Register. Offset: 500h + (chan_num * 20h) + 0Ch */ -+ volatile uint32_t hcintmsk; -+ /** Host Channel 0 Transfer Size Register. Offset: 500h + (chan_num * 20h) + 10h */ -+ volatile uint32_t hctsiz; -+ /** Host Channel 0 DMA Address Register. Offset: 500h + (chan_num * 20h) + 14h */ -+ volatile uint32_t hcdma; -+ volatile uint32_t reserved; -+ /** Host Channel 0 DMA Buffer Address Register. Offset: 500h + (chan_num * 20h) + 1Ch */ -+ volatile uint32_t hcdmab; -+} dwc_otg_hc_regs_t; -+ -+/** -+ * This union represents the bit fields in the Host Channel Characteristics -+ * Register. Read the register into the d32 member then set/clear the -+ * bits using the bit elements. Write the d32 member to the -+ * hcchar register. -+ */ -+typedef union hcchar_data { -+ /** raw register data */ -+ uint32_t d32; -+ -+ /** register bits */ -+ struct { -+ /** Maximum packet size in bytes */ -+ unsigned mps:11; -+ -+ /** Endpoint number */ -+ unsigned epnum:4; -+ -+ /** 0: OUT, 1: IN */ -+ unsigned epdir:1; -+ -+ unsigned reserved:1; -+ -+ /** 0: Full/high speed device, 1: Low speed device */ -+ unsigned lspddev:1; -+ -+ /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */ -+ unsigned eptype:2; -+ -+ /** Packets per frame for periodic transfers. 0 is reserved. */ -+ unsigned multicnt:2; -+ -+ /** Device address */ -+ unsigned devaddr:7; -+ -+ /** -+ * Frame to transmit periodic transaction. -+ * 0: even, 1: odd -+ */ -+ unsigned oddfrm:1; -+ -+ /** Channel disable */ -+ unsigned chdis:1; -+ -+ /** Channel enable */ -+ unsigned chen:1; -+ } b; -+} hcchar_data_t; -+ -+typedef union hcsplt_data { -+ /** raw register data */ -+ uint32_t d32; -+ -+ /** register bits */ -+ struct { -+ /** Port Address */ -+ unsigned prtaddr:7; -+ -+ /** Hub Address */ -+ unsigned hubaddr:7; -+ -+ /** Transaction Position */ -+ unsigned xactpos:2; -+#define DWC_HCSPLIT_XACTPOS_MID 0 -+#define DWC_HCSPLIT_XACTPOS_END 1 -+#define DWC_HCSPLIT_XACTPOS_BEGIN 2 -+#define DWC_HCSPLIT_XACTPOS_ALL 3 -+ -+ /** Do Complete Split */ -+ unsigned compsplt:1; -+ -+ /** Reserved */ -+ unsigned reserved:14; -+ -+ /** Split Enble */ -+ unsigned spltena:1; -+ } b; -+} hcsplt_data_t; -+ -+/** -+ * This union represents the bit fields in the Host All Interrupt -+ * Register. -+ */ -+typedef union hcint_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ /** Transfer Complete */ -+ unsigned xfercomp:1; -+ /** Channel Halted */ -+ unsigned chhltd:1; -+ /** AHB Error */ -+ unsigned ahberr:1; -+ /** STALL Response Received */ -+ unsigned stall:1; -+ /** NAK Response Received */ -+ unsigned nak:1; -+ /** ACK Response Received */ -+ unsigned ack:1; -+ /** NYET Response Received */ -+ unsigned nyet:1; -+ /** Transaction Err */ -+ unsigned xacterr:1; -+ /** Babble Error */ -+ unsigned bblerr:1; -+ /** Frame Overrun */ -+ unsigned frmovrun:1; -+ /** Data Toggle Error */ -+ unsigned datatglerr:1; -+ /** Buffer Not Available (only for DDMA mode) */ -+ unsigned bna:1; -+ /** Exessive transaction error (only for DDMA mode) */ -+ unsigned xcs_xact:1; -+ /** Frame List Rollover interrupt */ -+ unsigned frm_list_roll:1; -+ /** Reserved */ -+ unsigned reserved14_31:18; -+ } b; -+} hcint_data_t; -+ -+/** -+ * This union represents the bit fields in the Host Channel Interrupt Mask -+ * Register. Read the register into the d32 member then set/clear the -+ * bits using the bit elements. Write the d32 member to the -+ * hcintmsk register. -+ */ -+typedef union hcintmsk_data { -+ /** raw register data */ -+ uint32_t d32; -+ -+ /** register bits */ -+ struct { -+ unsigned xfercompl:1; -+ unsigned chhltd:1; -+ unsigned ahberr:1; -+ unsigned stall:1; -+ unsigned nak:1; -+ unsigned ack:1; -+ unsigned nyet:1; -+ unsigned xacterr:1; -+ unsigned bblerr:1; -+ unsigned frmovrun:1; -+ unsigned datatglerr:1; -+ unsigned bna:1; -+ unsigned xcs_xact:1; -+ unsigned frm_list_roll:1; -+ unsigned reserved14_31:18; -+ } b; -+} hcintmsk_data_t; -+ -+/** -+ * This union represents the bit fields in the Host Channel Transfer Size -+ * Register. Read the register into the d32 member then set/clear the -+ * bits using the bit elements. Write the d32 member to the -+ * hcchar register. -+ */ -+ -+typedef union hctsiz_data { -+ /** raw register data */ -+ uint32_t d32; -+ -+ /** register bits */ -+ struct { -+ /** Total transfer size in bytes */ -+ unsigned xfersize:19; -+ -+ /** Data packets to transfer */ -+ unsigned pktcnt:10; -+ -+ /** -+ * Packet ID for next data packet -+ * 0: DATA0 -+ * 1: DATA2 -+ * 2: DATA1 -+ * 3: MDATA (non-Control), SETUP (Control) -+ */ -+ unsigned pid:2; -+#define DWC_HCTSIZ_DATA0 0 -+#define DWC_HCTSIZ_DATA1 2 -+#define DWC_HCTSIZ_DATA2 1 -+#define DWC_HCTSIZ_MDATA 3 -+#define DWC_HCTSIZ_SETUP 3 -+ -+ /** Do PING protocol when 1 */ -+ unsigned dopng:1; -+ } b; -+ -+ /** register bits */ -+ struct { -+ /** Scheduling information */ -+ unsigned schinfo:8; -+ -+ /** Number of transfer descriptors. -+ * Max value: -+ * 64 in general, -+ * 256 only for HS isochronous endpoint. -+ */ -+ unsigned ntd:8; -+ -+ /** Data packets to transfer */ -+ unsigned reserved16_28:13; -+ -+ /** -+ * Packet ID for next data packet -+ * 0: DATA0 -+ * 1: DATA2 -+ * 2: DATA1 -+ * 3: MDATA (non-Control) -+ */ -+ unsigned pid:2; -+ -+ /** Do PING protocol when 1 */ -+ unsigned dopng:1; -+ } b_ddma; -+} hctsiz_data_t; -+ -+/** -+ * This union represents the bit fields in the Host DMA Address -+ * Register used in Descriptor DMA mode. -+ */ -+typedef union hcdma_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned reserved0_2:3; -+ /** Current Transfer Descriptor. Not used for ISOC */ -+ unsigned ctd:8; -+ /** Start Address of Descriptor List */ -+ unsigned dma_addr:21; -+ } b; -+} hcdma_data_t; -+ -+/** -+ * This union represents the bit fields in the DMA Descriptor -+ * status quadlet for host mode. Read the quadlet into the d32 member then -+ * set/clear the bits using the bit elements. -+ */ -+typedef union host_dma_desc_sts { -+ /** raw register data */ -+ uint32_t d32; -+ /** quadlet bits */ -+ -+ /* for non-isochronous */ -+ struct { -+ /** Number of bytes */ -+ unsigned n_bytes:17; -+ /** QTD offset to jump when Short Packet received - only for IN EPs */ -+ unsigned qtd_offset:6; -+ /** -+ * Set to request the core to jump to alternate QTD if -+ * Short Packet received - only for IN EPs -+ */ -+ unsigned a_qtd:1; -+ /** -+ * Setup Packet bit. When set indicates that buffer contains -+ * setup packet. -+ */ -+ unsigned sup:1; -+ /** Interrupt On Complete */ -+ unsigned ioc:1; -+ /** End of List */ -+ unsigned eol:1; -+ unsigned reserved27:1; -+ /** Rx/Tx Status */ -+ unsigned sts:2; -+#define DMA_DESC_STS_PKTERR 1 -+ unsigned reserved30:1; -+ /** Active Bit */ -+ unsigned a:1; -+ } b; -+ /* for isochronous */ -+ struct { -+ /** Number of bytes */ -+ unsigned n_bytes:12; -+ unsigned reserved12_24:13; -+ /** Interrupt On Complete */ -+ unsigned ioc:1; -+ unsigned reserved26_27:2; -+ /** Rx/Tx Status */ -+ unsigned sts:2; -+ unsigned reserved30:1; -+ /** Active Bit */ -+ unsigned a:1; -+ } b_isoc; -+} host_dma_desc_sts_t; -+ -+#define MAX_DMA_DESC_SIZE 131071 -+#define MAX_DMA_DESC_NUM_GENERIC 64 -+#define MAX_DMA_DESC_NUM_HS_ISOC 256 -+#define MAX_FRLIST_EN_NUM 64 -+/** -+ * Host-mode DMA Descriptor structure -+ * -+ * DMA Descriptor structure contains two quadlets: -+ * Status quadlet and Data buffer pointer. -+ */ -+typedef struct dwc_otg_host_dma_desc { -+ /** DMA Descriptor status quadlet */ -+ host_dma_desc_sts_t status; -+ /** DMA Descriptor data buffer pointer */ -+ uint32_t buf; -+} dwc_otg_host_dma_desc_t; -+ -+/** OTG Host Interface Structure. -+ * -+ * The OTG Host Interface Structure structure contains information -+ * needed to manage the DWC_otg controller acting in host mode. It -+ * represents the programming view of the host-specific aspects of the -+ * controller. -+ */ -+typedef struct dwc_otg_host_if { -+ /** Host Global Registers starting at offset 400h.*/ -+ dwc_otg_host_global_regs_t *host_global_regs; -+#define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400 -+ -+ /** Host Port 0 Control and Status Register */ -+ volatile uint32_t *hprt0; -+#define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440 -+ -+ /** Host Channel Specific Registers at offsets 500h-5FCh. */ -+ dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS]; -+#define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500 -+#define DWC_OTG_CHAN_REGS_OFFSET 0x20 -+ -+ /* Host configuration information */ -+ /** Number of Host Channels (range: 1-16) */ -+ uint8_t num_host_channels; -+ /** Periodic EPs supported (0: no, 1: yes) */ -+ uint8_t perio_eps_supported; -+ /** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */ -+ uint16_t perio_tx_fifo_size; -+ -+} dwc_otg_host_if_t; -+ -+/** -+ * This union represents the bit fields in the Power and Clock Gating Control -+ * Register. Read the register into the d32 member then set/clear the -+ * bits using the bit elements. -+ */ -+typedef union pcgcctl_data { -+ /** raw register data */ -+ uint32_t d32; -+ -+ /** register bits */ -+ struct { -+ /** Stop Pclk */ -+ unsigned stoppclk:1; -+ /** Gate Hclk */ -+ unsigned gatehclk:1; -+ /** Power Clamp */ -+ unsigned pwrclmp:1; -+ /** Reset Power Down Modules */ -+ unsigned rstpdwnmodule:1; -+ /** Reserved */ -+ unsigned reserved:1; -+ /** Enable Sleep Clock Gating (Enbl_L1Gating) */ -+ unsigned enbl_sleep_gating:1; -+ /** PHY In Sleep (PhySleep) */ -+ unsigned phy_in_sleep:1; -+ /** Deep Sleep*/ -+ unsigned deep_sleep:1; -+ unsigned resetaftsusp:1; -+ unsigned restoremode:1; -+ unsigned enbl_extnd_hiber:1; -+ unsigned extnd_hiber_pwrclmp:1; -+ unsigned extnd_hiber_switch:1; -+ unsigned ess_reg_restored:1; -+ unsigned prt_clk_sel:2; -+ unsigned port_power:1; -+ unsigned max_xcvrselect:2; -+ unsigned max_termsel:1; -+ unsigned mac_dev_addr:7; -+ unsigned p2hd_dev_enum_spd:2; -+ unsigned p2hd_prt_spd:2; -+ unsigned if_dev_mode:1; -+ } b; -+} pcgcctl_data_t; -+ -+/** -+ * This union represents the bit fields in the Global Data FIFO Software -+ * Configuration Register. Read the register into the d32 member then -+ * set/clear the bits using the bit elements. -+ */ -+typedef union gdfifocfg_data { -+ /* raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ /** OTG Data FIFO depth */ -+ unsigned gdfifocfg:16; -+ /** Start address of EP info controller */ -+ unsigned epinfobase:16; -+ } b; -+} gdfifocfg_data_t; -+ -+/** -+ * This union represents the bit fields in the Global Power Down Register -+ * Register. Read the register into the d32 member then set/clear the -+ * bits using the bit elements. -+ */ -+typedef union gpwrdn_data { -+ /* raw register data */ -+ uint32_t d32; -+ -+ /** register bits */ -+ struct { -+ /** PMU Interrupt Select */ -+ unsigned pmuintsel:1; -+ /** PMU Active */ -+ unsigned pmuactv:1; -+ /** Restore */ -+ unsigned restore:1; -+ /** Power Down Clamp */ -+ unsigned pwrdnclmp:1; -+ /** Power Down Reset */ -+ unsigned pwrdnrstn:1; -+ /** Power Down Switch */ -+ unsigned pwrdnswtch:1; -+ /** Disable VBUS */ -+ unsigned dis_vbus:1; -+ /** Line State Change */ -+ unsigned lnstschng:1; -+ /** Line state change mask */ -+ unsigned lnstchng_msk:1; -+ /** Reset Detected */ -+ unsigned rst_det:1; -+ /** Reset Detect mask */ -+ unsigned rst_det_msk:1; -+ /** Disconnect Detected */ -+ unsigned disconn_det:1; -+ /** Disconnect Detect mask */ -+ unsigned disconn_det_msk:1; -+ /** Connect Detected*/ -+ unsigned connect_det:1; -+ /** Connect Detected Mask*/ -+ unsigned connect_det_msk:1; -+ /** SRP Detected */ -+ unsigned srp_det:1; -+ /** SRP Detect mask */ -+ unsigned srp_det_msk:1; -+ /** Status Change Interrupt */ -+ unsigned sts_chngint:1; -+ /** Status Change Interrupt Mask */ -+ unsigned sts_chngint_msk:1; -+ /** Line State */ -+ unsigned linestate:2; -+ /** Indicates current mode(status of IDDIG signal) */ -+ unsigned idsts:1; -+ /** B Session Valid signal status*/ -+ unsigned bsessvld:1; -+ /** ADP Event Detected */ -+ unsigned adp_int:1; -+ /** Multi Valued ID pin */ -+ unsigned mult_val_id_bc:5; -+ /** Reserved 24_31 */ -+ unsigned reserved29_31:3; -+ } b; -+} gpwrdn_data_t; -+ -+#endif -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/Makefile linux-rpi/drivers/usb/host/dwc_otg/Makefile ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/Makefile 2015-11-29 09:42:39.915098960 +0100 -@@ -0,0 +1,82 @@ -+# -+# Makefile for DWC_otg Highspeed USB controller driver -+# -+ -+ifneq ($(KERNELRELEASE),) -+ -+# Use the BUS_INTERFACE variable to compile the software for either -+# PCI(PCI_INTERFACE) or LM(LM_INTERFACE) bus. -+ifeq ($(BUS_INTERFACE),) -+# BUS_INTERFACE = -DPCI_INTERFACE -+# BUS_INTERFACE = -DLM_INTERFACE -+ BUS_INTERFACE = -DPLATFORM_INTERFACE -+endif -+ -+#ccflags-y += -DDEBUG -+#ccflags-y += -DDWC_OTG_DEBUGLEV=1 # reduce common debug msgs -+ -+# Use one of the following flags to compile the software in host-only or -+# device-only mode. -+#ccflags-y += -DDWC_HOST_ONLY -+#ccflags-y += -DDWC_DEVICE_ONLY -+ -+ccflags-y += -Dlinux -DDWC_HS_ELECT_TST -+#ccflags-y += -DDWC_EN_ISOC -+ccflags-y += -I$(obj)/../dwc_common_port -+#ccflags-y += -I$(PORTLIB) -+ccflags-y += -DDWC_LINUX -+ccflags-y += $(CFI) -+ccflags-y += $(BUS_INTERFACE) -+#ccflags-y += -DDWC_DEV_SRPCAP -+ -+obj-$(CONFIG_USB_DWCOTG) += dwc_otg.o -+ -+dwc_otg-objs := dwc_otg_driver.o dwc_otg_attr.o -+dwc_otg-objs += dwc_otg_cil.o dwc_otg_cil_intr.o -+dwc_otg-objs += dwc_otg_pcd_linux.o dwc_otg_pcd.o dwc_otg_pcd_intr.o -+dwc_otg-objs += dwc_otg_hcd.o dwc_otg_hcd_linux.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o dwc_otg_hcd_ddma.o -+dwc_otg-objs += dwc_otg_adp.o -+dwc_otg-objs += dwc_otg_fiq_fsm.o -+dwc_otg-objs += dwc_otg_fiq_stub.o -+ifneq ($(CFI),) -+dwc_otg-objs += dwc_otg_cfi.o -+endif -+ -+kernrelwd := $(subst ., ,$(KERNELRELEASE)) -+kernrel3 := $(word 1,$(kernrelwd)).$(word 2,$(kernrelwd)).$(word 3,$(kernrelwd)) -+ -+ifneq ($(kernrel3),2.6.20) -+ccflags-y += $(CPPFLAGS) -+endif -+ -+else -+ -+PWD := $(shell pwd) -+PORTLIB := $(PWD)/../dwc_common_port -+ -+# Command paths -+CTAGS := $(CTAGS) -+DOXYGEN := $(DOXYGEN) -+ -+default: portlib -+ $(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules -+ -+install: default -+ $(MAKE) -C$(KDIR) M=$(PORTLIB) modules_install -+ $(MAKE) -C$(KDIR) M=$(PWD) modules_install -+ -+portlib: -+ $(MAKE) -C$(KDIR) M=$(PORTLIB) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules -+ cp $(PORTLIB)/Module.symvers $(PWD)/ -+ -+docs: $(wildcard *.[hc]) doc/doxygen.cfg -+ $(DOXYGEN) doc/doxygen.cfg -+ -+tags: $(wildcard *.[hc]) -+ $(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h) -+ -+ -+clean: -+ rm -rf *.o *.ko .*cmd *.mod.c .tmp_versions Module.symvers -+ -+endif -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/test/dwc_otg_test.pm linux-rpi/drivers/usb/host/dwc_otg/test/dwc_otg_test.pm ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/test/dwc_otg_test.pm 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/test/dwc_otg_test.pm 2015-11-29 09:42:39.923098428 +0100 -@@ -0,0 +1,337 @@ -+package dwc_otg_test; -+ -+use strict; -+use Exporter (); -+ -+use vars qw(@ISA @EXPORT -+$sysfsdir $paramdir $errors $params -+); -+ -+@ISA = qw(Exporter); -+ -+# -+# Globals -+# -+$sysfsdir = "/sys/devices/lm0"; -+$paramdir = "/sys/module/dwc_otg"; -+$errors = 0; -+ -+$params = [ -+ { -+ NAME => "otg_cap", -+ DEFAULT => 0, -+ ENUM => [], -+ LOW => 0, -+ HIGH => 2 -+ }, -+ { -+ NAME => "dma_enable", -+ DEFAULT => 0, -+ ENUM => [], -+ LOW => 0, -+ HIGH => 1 -+ }, -+ { -+ NAME => "dma_burst_size", -+ DEFAULT => 32, -+ ENUM => [1, 4, 8, 16, 32, 64, 128, 256], -+ LOW => 1, -+ HIGH => 256 -+ }, -+ { -+ NAME => "host_speed", -+ DEFAULT => 0, -+ ENUM => [], -+ LOW => 0, -+ HIGH => 1 -+ }, -+ { -+ NAME => "host_support_fs_ls_low_power", -+ DEFAULT => 0, -+ ENUM => [], -+ LOW => 0, -+ HIGH => 1 -+ }, -+ { -+ NAME => "host_ls_low_power_phy_clk", -+ DEFAULT => 0, -+ ENUM => [], -+ LOW => 0, -+ HIGH => 1 -+ }, -+ { -+ NAME => "dev_speed", -+ DEFAULT => 0, -+ ENUM => [], -+ LOW => 0, -+ HIGH => 1 -+ }, -+ { -+ NAME => "enable_dynamic_fifo", -+ DEFAULT => 1, -+ ENUM => [], -+ LOW => 0, -+ HIGH => 1 -+ }, -+ { -+ NAME => "data_fifo_size", -+ DEFAULT => 8192, -+ ENUM => [], -+ LOW => 32, -+ HIGH => 32768 -+ }, -+ { -+ NAME => "dev_rx_fifo_size", -+ DEFAULT => 1064, -+ ENUM => [], -+ LOW => 16, -+ HIGH => 32768 -+ }, -+ { -+ NAME => "dev_nperio_tx_fifo_size", -+ DEFAULT => 1024, -+ ENUM => [], -+ LOW => 16, -+ HIGH => 32768 -+ }, -+ { -+ NAME => "dev_perio_tx_fifo_size_1", -+ DEFAULT => 256, -+ ENUM => [], -+ LOW => 4, -+ HIGH => 768 -+ }, -+ { -+ NAME => "dev_perio_tx_fifo_size_2", -+ DEFAULT => 256, -+ ENUM => [], -+ LOW => 4, -+ HIGH => 768 -+ }, -+ { -+ NAME => "dev_perio_tx_fifo_size_3", -+ DEFAULT => 256, -+ ENUM => [], -+ LOW => 4, -+ HIGH => 768 -+ }, -+ { -+ NAME => "dev_perio_tx_fifo_size_4", -+ DEFAULT => 256, -+ ENUM => [], -+ LOW => 4, -+ HIGH => 768 -+ }, -+ { -+ NAME => "dev_perio_tx_fifo_size_5", -+ DEFAULT => 256, -+ ENUM => [], -+ LOW => 4, -+ HIGH => 768 -+ }, -+ { -+ NAME => "dev_perio_tx_fifo_size_6", -+ DEFAULT => 256, -+ ENUM => [], -+ LOW => 4, -+ HIGH => 768 -+ }, -+ { -+ NAME => "dev_perio_tx_fifo_size_7", -+ DEFAULT => 256, -+ ENUM => [], -+ LOW => 4, -+ HIGH => 768 -+ }, -+ { -+ NAME => "dev_perio_tx_fifo_size_8", -+ DEFAULT => 256, -+ ENUM => [], -+ LOW => 4, -+ HIGH => 768 -+ }, -+ { -+ NAME => "dev_perio_tx_fifo_size_9", -+ DEFAULT => 256, -+ ENUM => [], -+ LOW => 4, -+ HIGH => 768 -+ }, -+ { -+ NAME => "dev_perio_tx_fifo_size_10", -+ DEFAULT => 256, -+ ENUM => [], -+ LOW => 4, -+ HIGH => 768 -+ }, -+ { -+ NAME => "dev_perio_tx_fifo_size_11", -+ DEFAULT => 256, -+ ENUM => [], -+ LOW => 4, -+ HIGH => 768 -+ }, -+ { -+ NAME => "dev_perio_tx_fifo_size_12", -+ DEFAULT => 256, -+ ENUM => [], -+ LOW => 4, -+ HIGH => 768 -+ }, -+ { -+ NAME => "dev_perio_tx_fifo_size_13", -+ DEFAULT => 256, -+ ENUM => [], -+ LOW => 4, -+ HIGH => 768 -+ }, -+ { -+ NAME => "dev_perio_tx_fifo_size_14", -+ DEFAULT => 256, -+ ENUM => [], -+ LOW => 4, -+ HIGH => 768 -+ }, -+ { -+ NAME => "dev_perio_tx_fifo_size_15", -+ DEFAULT => 256, -+ ENUM => [], -+ LOW => 4, -+ HIGH => 768 -+ }, -+ { -+ NAME => "host_rx_fifo_size", -+ DEFAULT => 1024, -+ ENUM => [], -+ LOW => 16, -+ HIGH => 32768 -+ }, -+ { -+ NAME => "host_nperio_tx_fifo_size", -+ DEFAULT => 1024, -+ ENUM => [], -+ LOW => 16, -+ HIGH => 32768 -+ }, -+ { -+ NAME => "host_perio_tx_fifo_size", -+ DEFAULT => 1024, -+ ENUM => [], -+ LOW => 16, -+ HIGH => 32768 -+ }, -+ { -+ NAME => "max_transfer_size", -+ DEFAULT => 65535, -+ ENUM => [], -+ LOW => 2047, -+ HIGH => 65535 -+ }, -+ { -+ NAME => "max_packet_count", -+ DEFAULT => 511, -+ ENUM => [], -+ LOW => 15, -+ HIGH => 511 -+ }, -+ { -+ NAME => "host_channels", -+ DEFAULT => 12, -+ ENUM => [], -+ LOW => 1, -+ HIGH => 16 -+ }, -+ { -+ NAME => "dev_endpoints", -+ DEFAULT => 6, -+ ENUM => [], -+ LOW => 1, -+ HIGH => 15 -+ }, -+ { -+ NAME => "phy_type", -+ DEFAULT => 1, -+ ENUM => [], -+ LOW => 0, -+ HIGH => 2 -+ }, -+ { -+ NAME => "phy_utmi_width", -+ DEFAULT => 16, -+ ENUM => [8, 16], -+ LOW => 8, -+ HIGH => 16 -+ }, -+ { -+ NAME => "phy_ulpi_ddr", -+ DEFAULT => 0, -+ ENUM => [], -+ LOW => 0, -+ HIGH => 1 -+ }, -+ ]; -+ -+ -+# -+# -+sub check_arch { -+ $_ = `uname -m`; -+ chomp; -+ unless (m/armv4tl/) { -+ warn "# \n# Can't execute on $_. Run on integrator platform.\n# \n"; -+ return 0; -+ } -+ return 1; -+} -+ -+# -+# -+sub load_module { -+ my $params = shift; -+ print "\nRemoving Module\n"; -+ system "rmmod dwc_otg"; -+ print "Loading Module\n"; -+ if ($params ne "") { -+ print "Module Parameters: $params\n"; -+ } -+ if (system("modprobe dwc_otg $params")) { -+ warn "Unable to load module\n"; -+ return 0; -+ } -+ return 1; -+} -+ -+# -+# -+sub test_status { -+ my $arg = shift; -+ -+ print "\n"; -+ -+ if (defined $arg) { -+ warn "WARNING: $arg\n"; -+ } -+ -+ if ($errors > 0) { -+ warn "TEST FAILED with $errors errors\n"; -+ return 0; -+ } else { -+ print "TEST PASSED\n"; -+ return 0 if (defined $arg); -+ } -+ return 1; -+} -+ -+# -+# -+@EXPORT = qw( -+$sysfsdir -+$paramdir -+$params -+$errors -+check_arch -+load_module -+test_status -+); -+ -+1; -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/test/Makefile linux-rpi/drivers/usb/host/dwc_otg/test/Makefile ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/test/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/test/Makefile 2015-11-29 09:42:39.923098428 +0100 -@@ -0,0 +1,16 @@ -+ -+PERL=/usr/bin/perl -+PL_TESTS=test_sysfs.pl test_mod_param.pl -+ -+.PHONY : test -+test : perl_tests -+ -+perl_tests : -+ @echo -+ @echo Running perl tests -+ @for test in $(PL_TESTS); do \ -+ if $(PERL) ./$$test ; then \ -+ echo "=======> $$test, PASSED" ; \ -+ else echo "=======> $$test, FAILED" ; \ -+ fi \ -+ done -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/test/test_mod_param.pl linux-rpi/drivers/usb/host/dwc_otg/test/test_mod_param.pl ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/test/test_mod_param.pl 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/test/test_mod_param.pl 2015-11-29 09:42:39.923098428 +0100 -@@ -0,0 +1,133 @@ -+#!/usr/bin/perl -w -+# -+# Run this program on the integrator. -+# -+# - Tests module parameter default values. -+# - Tests setting of valid module parameter values via modprobe. -+# - Tests invalid module parameter values. -+# ----------------------------------------------------------------------------- -+use strict; -+use dwc_otg_test; -+ -+check_arch() or die; -+ -+# -+# -+sub test { -+ my ($param,$expected) = @_; -+ my $value = get($param); -+ -+ if ($value == $expected) { -+ print "$param = $value, okay\n"; -+ } -+ -+ else { -+ warn "ERROR: value of $param != $expected, $value\n"; -+ $errors ++; -+ } -+} -+ -+# -+# -+sub get { -+ my $param = shift; -+ my $tmp = `cat $paramdir/$param`; -+ chomp $tmp; -+ return $tmp; -+} -+ -+# -+# -+sub test_main { -+ -+ print "\nTesting Module Parameters\n"; -+ -+ load_module("") or die; -+ -+ # Test initial values -+ print "\nTesting Default Values\n"; -+ foreach (@{$params}) { -+ test ($_->{NAME}, $_->{DEFAULT}); -+ } -+ -+ # Test low value -+ print "\nTesting Low Value\n"; -+ my $cmd_params = ""; -+ foreach (@{$params}) { -+ $cmd_params = $cmd_params . "$_->{NAME}=$_->{LOW} "; -+ } -+ load_module($cmd_params) or die; -+ -+ foreach (@{$params}) { -+ test ($_->{NAME}, $_->{LOW}); -+ } -+ -+ # Test high value -+ print "\nTesting High Value\n"; -+ $cmd_params = ""; -+ foreach (@{$params}) { -+ $cmd_params = $cmd_params . "$_->{NAME}=$_->{HIGH} "; -+ } -+ load_module($cmd_params) or die; -+ -+ foreach (@{$params}) { -+ test ($_->{NAME}, $_->{HIGH}); -+ } -+ -+ # Test Enum -+ print "\nTesting Enumerated\n"; -+ foreach (@{$params}) { -+ if (defined $_->{ENUM}) { -+ my $value; -+ foreach $value (@{$_->{ENUM}}) { -+ $cmd_params = "$_->{NAME}=$value"; -+ load_module($cmd_params) or die; -+ test ($_->{NAME}, $value); -+ } -+ } -+ } -+ -+ # Test Invalid Values -+ print "\nTesting Invalid Values\n"; -+ $cmd_params = ""; -+ foreach (@{$params}) { -+ $cmd_params = $cmd_params . sprintf "$_->{NAME}=%d ", $_->{LOW}-1; -+ } -+ load_module($cmd_params) or die; -+ -+ foreach (@{$params}) { -+ test ($_->{NAME}, $_->{DEFAULT}); -+ } -+ -+ $cmd_params = ""; -+ foreach (@{$params}) { -+ $cmd_params = $cmd_params . sprintf "$_->{NAME}=%d ", $_->{HIGH}+1; -+ } -+ load_module($cmd_params) or die; -+ -+ foreach (@{$params}) { -+ test ($_->{NAME}, $_->{DEFAULT}); -+ } -+ -+ print "\nTesting Enumerated\n"; -+ foreach (@{$params}) { -+ if (defined $_->{ENUM}) { -+ my $value; -+ foreach $value (@{$_->{ENUM}}) { -+ $value = $value + 1; -+ $cmd_params = "$_->{NAME}=$value"; -+ load_module($cmd_params) or die; -+ test ($_->{NAME}, $_->{DEFAULT}); -+ $value = $value - 2; -+ $cmd_params = "$_->{NAME}=$value"; -+ load_module($cmd_params) or die; -+ test ($_->{NAME}, $_->{DEFAULT}); -+ } -+ } -+ } -+ -+ test_status() or die; -+} -+ -+test_main(); -+0; -diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/test/test_sysfs.pl linux-rpi/drivers/usb/host/dwc_otg/test/test_sysfs.pl ---- linux-4.1.13.orig/drivers/usb/host/dwc_otg/test/test_sysfs.pl 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/usb/host/dwc_otg/test/test_sysfs.pl 2015-11-29 09:42:39.923098428 +0100 -@@ -0,0 +1,193 @@ -+#!/usr/bin/perl -w -+# -+# Run this program on the integrator -+# - Tests select sysfs attributes. -+# - Todo ... test more attributes, hnp/srp, buspower/bussuspend, etc. -+# ----------------------------------------------------------------------------- -+use strict; -+use dwc_otg_test; -+ -+check_arch() or die; -+ -+# -+# -+sub test { -+ my ($attr,$expected) = @_; -+ my $string = get($attr); -+ -+ if ($string eq $expected) { -+ printf("$attr = $string, okay\n"); -+ } -+ else { -+ warn "ERROR: value of $attr != $expected, $string\n"; -+ $errors ++; -+ } -+} -+ -+# -+# -+sub set { -+ my ($reg, $value) = @_; -+ system "echo $value > $sysfsdir/$reg"; -+} -+ -+# -+# -+sub get { -+ my $attr = shift; -+ my $string = `cat $sysfsdir/$attr`; -+ chomp $string; -+ if ($string =~ m/\s\=\s/) { -+ my $tmp; -+ ($tmp, $string) = split /\s=\s/, $string; -+ } -+ return $string; -+} -+ -+# -+# -+sub test_main { -+ print("\nTesting Sysfs Attributes\n"); -+ -+ load_module("") or die; -+ -+ # Test initial values of regoffset/regvalue/guid/gsnpsid -+ print("\nTesting Default Values\n"); -+ -+ test("regoffset", "0xffffffff"); -+ test("regvalue", "invalid offset"); -+ test("guid", "0x12345678"); # this will fail if it has been changed -+ test("gsnpsid", "0x4f54200a"); -+ -+ # Test operation of regoffset/regvalue -+ print("\nTesting regoffset\n"); -+ set('regoffset', '5a5a5a5a'); -+ test("regoffset", "0xffffffff"); -+ -+ set('regoffset', '0'); -+ test("regoffset", "0x00000000"); -+ -+ set('regoffset', '40000'); -+ test("regoffset", "0x00000000"); -+ -+ set('regoffset', '3ffff'); -+ test("regoffset", "0x0003ffff"); -+ -+ set('regoffset', '1'); -+ test("regoffset", "0x00000001"); -+ -+ print("\nTesting regvalue\n"); -+ set('regoffset', '3c'); -+ test("regvalue", "0x12345678"); -+ set('regvalue', '5a5a5a5a'); -+ test("regvalue", "0x5a5a5a5a"); -+ set('regvalue','a5a5a5a5'); -+ test("regvalue", "0xa5a5a5a5"); -+ set('guid','12345678'); -+ -+ # Test HNP Capable -+ print("\nTesting HNP Capable bit\n"); -+ set('hnpcapable', '1'); -+ test("hnpcapable", "0x1"); -+ set('hnpcapable','0'); -+ test("hnpcapable", "0x0"); -+ -+ set('regoffset','0c'); -+ -+ my $old = get('gusbcfg'); -+ print("setting hnpcapable\n"); -+ set('hnpcapable', '1'); -+ test("hnpcapable", "0x1"); -+ test('gusbcfg', sprintf "0x%08x", (oct ($old) | (1<<9))); -+ test('regvalue', sprintf "0x%08x", (oct ($old) | (1<<9))); -+ -+ $old = get('gusbcfg'); -+ print("clearing hnpcapable\n"); -+ set('hnpcapable', '0'); -+ test("hnpcapable", "0x0"); -+ test ('gusbcfg', sprintf "0x%08x", oct ($old) & (~(1<<9))); -+ test ('regvalue', sprintf "0x%08x", oct ($old) & (~(1<<9))); -+ -+ # Test SRP Capable -+ print("\nTesting SRP Capable bit\n"); -+ set('srpcapable', '1'); -+ test("srpcapable", "0x1"); -+ set('srpcapable','0'); -+ test("srpcapable", "0x0"); -+ -+ set('regoffset','0c'); -+ -+ $old = get('gusbcfg'); -+ print("setting srpcapable\n"); -+ set('srpcapable', '1'); -+ test("srpcapable", "0x1"); -+ test('gusbcfg', sprintf "0x%08x", (oct ($old) | (1<<8))); -+ test('regvalue', sprintf "0x%08x", (oct ($old) | (1<<8))); -+ -+ $old = get('gusbcfg'); -+ print("clearing srpcapable\n"); -+ set('srpcapable', '0'); -+ test("srpcapable", "0x0"); -+ test('gusbcfg', sprintf "0x%08x", oct ($old) & (~(1<<8))); -+ test('regvalue', sprintf "0x%08x", oct ($old) & (~(1<<8))); -+ -+ # Test GGPIO -+ print("\nTesting GGPIO\n"); -+ set('ggpio','5a5a5a5a'); -+ test('ggpio','0x5a5a0000'); -+ set('ggpio','a5a5a5a5'); -+ test('ggpio','0xa5a50000'); -+ set('ggpio','11110000'); -+ test('ggpio','0x11110000'); -+ set('ggpio','00001111'); -+ test('ggpio','0x00000000'); -+ -+ # Test DEVSPEED -+ print("\nTesting DEVSPEED\n"); -+ set('regoffset','800'); -+ $old = get('regvalue'); -+ set('devspeed','0'); -+ test('devspeed','0x0'); -+ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3))); -+ set('devspeed','1'); -+ test('devspeed','0x1'); -+ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 1)); -+ set('devspeed','2'); -+ test('devspeed','0x2'); -+ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 2)); -+ set('devspeed','3'); -+ test('devspeed','0x3'); -+ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 3)); -+ set('devspeed','4'); -+ test('devspeed','0x0'); -+ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3))); -+ set('devspeed','5'); -+ test('devspeed','0x1'); -+ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 1)); -+ -+ -+ # mode Returns the current mode:0 for device mode1 for host mode Read -+ # hnp Initiate the Host Negotiation Protocol. Read returns the status. Read/Write -+ # srp Initiate the Session Request Protocol. Read returns the status. Read/Write -+ # buspower Get or Set the Power State of the bus (0 - Off or 1 - On) Read/Write -+ # bussuspend Suspend the USB bus. Read/Write -+ # busconnected Get the connection status of the bus Read -+ -+ # gotgctl Get or set the Core Control Status Register. Read/Write -+ ## gusbcfg Get or set the Core USB Configuration Register Read/Write -+ # grxfsiz Get or set the Receive FIFO Size Register Read/Write -+ # gnptxfsiz Get or set the non-periodic Transmit Size Register Read/Write -+ # gpvndctl Get or set the PHY Vendor Control Register Read/Write -+ ## ggpio Get the value in the lower 16-bits of the General Purpose IO Register or Set the upper 16 bits. Read/Write -+ ## guid Get or set the value of the User ID Register Read/Write -+ ## gsnpsid Get the value of the Synopsys ID Regester Read -+ ## devspeed Get or set the device speed setting in the DCFG register Read/Write -+ # enumspeed Gets the device enumeration Speed. Read -+ # hptxfsiz Get the value of the Host Periodic Transmit FIFO Read -+ # hprt0 Get or Set the value in the Host Port Control and Status Register Read/Write -+ -+ test_status("TEST NYI") or die; -+} -+ -+test_main(); -+0; -diff -Nur linux-4.1.13.orig/drivers/usb/host/Kconfig linux-rpi/drivers/usb/host/Kconfig ---- linux-4.1.13.orig/drivers/usb/host/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/usb/host/Kconfig 2015-11-29 09:42:39.915098960 +0100 -@@ -738,6 +738,19 @@ - To compile this driver a module, choose M here: the module - will be called "hwa-hc". - -+config USB_DWCOTG -+ tristate "Synopsis DWC host support" -+ depends on USB -+ help -+ The Synopsis DWC controller is a dual-role -+ host/peripheral/OTG ("On The Go") USB controllers. -+ -+ Enable this option to support this IP in host controller mode. -+ If unsure, say N. -+ -+ To compile this driver as a module, choose M here: the -+ modules built will be called dwc_otg and dwc_common_port. -+ - config USB_IMX21_HCD - tristate "i.MX21 HCD support" - depends on ARM && ARCH_MXC -diff -Nur linux-4.1.13.orig/drivers/usb/host/Makefile linux-rpi/drivers/usb/host/Makefile ---- linux-4.1.13.orig/drivers/usb/host/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/usb/host/Makefile 2015-11-29 09:42:39.915098960 +0100 -@@ -68,6 +68,8 @@ - obj-$(CONFIG_USB_U132_HCD) += u132-hcd.o - obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o - obj-$(CONFIG_USB_HWA_HCD) += hwa-hc.o -+ -+obj-$(CONFIG_USB_DWCOTG) += dwc_otg/ dwc_common_port/ - obj-$(CONFIG_USB_IMX21_HCD) += imx21-hcd.o - obj-$(CONFIG_USB_FSL_MPH_DR_OF) += fsl-mph-dr-of.o - obj-$(CONFIG_USB_HCD_BCMA) += bcma-hcd.o -diff -Nur linux-4.1.13.orig/drivers/usb/Makefile linux-rpi/drivers/usb/Makefile ---- linux-4.1.13.orig/drivers/usb/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/usb/Makefile 2015-11-29 09:42:39.847103478 +0100 -@@ -7,6 +7,7 @@ - obj-$(CONFIG_USB) += core/ - obj-$(CONFIG_USB_SUPPORT) += phy/ - -+obj-$(CONFIG_USB_DWCOTG) += host/ - obj-$(CONFIG_USB_DWC3) += dwc3/ - obj-$(CONFIG_USB_DWC2) += dwc2/ - obj-$(CONFIG_USB_ISP1760) += isp1760/ -diff -Nur linux-4.1.13.orig/drivers/video/backlight/Kconfig linux-rpi/drivers/video/backlight/Kconfig ---- linux-4.1.13.orig/drivers/video/backlight/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/video/backlight/Kconfig 2015-11-29 09:42:40.023091784 +0100 -@@ -263,6 +263,12 @@ - If you have a LCD backlight adjustable by PWM, say Y to enable - this driver. - -+config BACKLIGHT_RPI -+ tristate "Raspberry Pi display firmware driven backlight" -+ help -+ If you have the Raspberry Pi DSI touchscreen display, say Y to -+ enable the mailbox-controlled backlight driver. -+ - config BACKLIGHT_DA903X - tristate "Backlight Driver for DA9030/DA9034 using WLED" - depends on PMIC_DA903X -diff -Nur linux-4.1.13.orig/drivers/video/backlight/Makefile linux-rpi/drivers/video/backlight/Makefile ---- linux-4.1.13.orig/drivers/video/backlight/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/video/backlight/Makefile 2015-11-29 09:42:40.023091784 +0100 -@@ -49,6 +49,7 @@ - obj-$(CONFIG_BACKLIGHT_PANDORA) += pandora_bl.o - obj-$(CONFIG_BACKLIGHT_PCF50633) += pcf50633-backlight.o - obj-$(CONFIG_BACKLIGHT_PWM) += pwm_bl.o -+obj-$(CONFIG_BACKLIGHT_RPI) += rpi_backlight.o - obj-$(CONFIG_BACKLIGHT_SAHARA) += kb3886_bl.o - obj-$(CONFIG_BACKLIGHT_SKY81452) += sky81452-backlight.o - obj-$(CONFIG_BACKLIGHT_TOSA) += tosa_bl.o -diff -Nur linux-4.1.13.orig/drivers/video/backlight/rpi_backlight.c linux-rpi/drivers/video/backlight/rpi_backlight.c ---- linux-4.1.13.orig/drivers/video/backlight/rpi_backlight.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/video/backlight/rpi_backlight.c 2015-11-29 09:42:40.027091518 +0100 -@@ -0,0 +1,119 @@ -+/* -+ * rpi_bl.c - Backlight controller through VPU -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+struct rpi_backlight { -+ struct device *dev; -+ struct device *fbdev; -+ struct rpi_firmware *fw; -+}; -+ -+static int rpi_backlight_update_status(struct backlight_device *bl) -+{ -+ struct rpi_backlight *gbl = bl_get_data(bl); -+ int brightness = bl->props.brightness; -+ int ret; -+ -+ if (bl->props.power != FB_BLANK_UNBLANK || -+ bl->props.fb_blank != FB_BLANK_UNBLANK || -+ bl->props.state & (BL_CORE_SUSPENDED | BL_CORE_FBBLANK)) -+ brightness = 0; -+ -+ ret = rpi_firmware_property(gbl->fw, -+ RPI_FIRMWARE_FRAMEBUFFER_SET_BACKLIGHT, -+ &brightness, sizeof(brightness)); -+ if (ret) { -+ dev_err(gbl->dev, "Failed to set brightness\n"); -+ return ret; -+ } -+ -+ if (brightness < 0) { -+ dev_err(gbl->dev, "Backlight change failed\n"); -+ return -EAGAIN; -+ } -+ -+ return 0; -+} -+ -+static const struct backlight_ops rpi_backlight_ops = { -+ .options = BL_CORE_SUSPENDRESUME, -+ .update_status = rpi_backlight_update_status, -+}; -+ -+static int rpi_backlight_probe(struct platform_device *pdev) -+{ -+ struct backlight_properties props; -+ struct backlight_device *bl; -+ struct rpi_backlight *gbl; -+ struct device_node *fw_node; -+ -+ gbl = devm_kzalloc(&pdev->dev, sizeof(*gbl), GFP_KERNEL); -+ if (gbl == NULL) -+ return -ENOMEM; -+ -+ gbl->dev = &pdev->dev; -+ -+ fw_node = of_parse_phandle(pdev->dev.of_node, "firmware", 0); -+ if (!fw_node) { -+ dev_err(&pdev->dev, "Missing firmware node\n"); -+ return -ENOENT; -+ } -+ -+ gbl->fw = rpi_firmware_get(fw_node); -+ if (!gbl->fw) -+ return -EPROBE_DEFER; -+ -+ memset(&props, 0, sizeof(props)); -+ props.type = BACKLIGHT_RAW; -+ props.max_brightness = 255; -+ bl = devm_backlight_device_register(&pdev->dev, dev_name(&pdev->dev), -+ &pdev->dev, gbl, &rpi_backlight_ops, -+ &props); -+ if (IS_ERR(bl)) { -+ dev_err(&pdev->dev, "failed to register backlight\n"); -+ return PTR_ERR(bl); -+ } -+ -+ bl->props.brightness = 255; -+ backlight_update_status(bl); -+ -+ platform_set_drvdata(pdev, bl); -+ return 0; -+} -+ -+static const struct of_device_id rpi_backlight_of_match[] = { -+ { .compatible = "raspberrypi,rpi-backlight" }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, rpi_backlight_of_match); -+ -+static struct platform_driver rpi_backlight_driver = { -+ .driver = { -+ .name = "rpi-backlight", -+ .of_match_table = of_match_ptr(rpi_backlight_of_match), -+ }, -+ .probe = rpi_backlight_probe, -+}; -+ -+module_platform_driver(rpi_backlight_driver); -+ -+MODULE_AUTHOR("Gordon Hollingworth "); -+MODULE_DESCRIPTION("Raspberry Pi mailbox based Backlight Driver"); -+MODULE_LICENSE("GPL"); -diff -Nur linux-4.1.13.orig/drivers/video/fbdev/bcm2708_fb.c linux-rpi/drivers/video/fbdev/bcm2708_fb.c ---- linux-4.1.13.orig/drivers/video/fbdev/bcm2708_fb.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/video/fbdev/bcm2708_fb.c 2015-11-29 09:42:40.071088595 +0100 -@@ -0,0 +1,847 @@ -+/* -+ * linux/drivers/video/bcm2708_fb.c -+ * -+ * Copyright (C) 2010 Broadcom -+ * -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file COPYING in the main directory of this archive -+ * for more details. -+ * -+ * Broadcom simple framebuffer driver -+ * -+ * This file is derived from cirrusfb.c -+ * Copyright 1999-2001 Jeff Garzik -+ * -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+//#define BCM2708_FB_DEBUG -+#define MODULE_NAME "bcm2708_fb" -+ -+#ifdef BCM2708_FB_DEBUG -+#define print_debug(fmt,...) pr_debug("%s:%s:%d: "fmt, MODULE_NAME, __func__, __LINE__, ##__VA_ARGS__) -+#else -+#define print_debug(fmt,...) -+#endif -+ -+/* This is limited to 16 characters when displayed by X startup */ -+static const char *bcm2708_name = "BCM2708 FB"; -+ -+#define DRIVER_NAME "bcm2708_fb" -+ -+static int fbwidth = 800; /* module parameter */ -+static int fbheight = 480; /* module parameter */ -+static int fbdepth = 16; /* module parameter */ -+static int fbswap = 0; /* module parameter */ -+ -+static u32 dma_busy_wait_threshold = 1<<15; -+module_param(dma_busy_wait_threshold, int, 0644); -+MODULE_PARM_DESC(dma_busy_wait_threshold, "Busy-wait for DMA completion below this area"); -+ -+struct fb_alloc_tags { -+ struct rpi_firmware_property_tag_header tag1; -+ u32 xres, yres; -+ struct rpi_firmware_property_tag_header tag2; -+ u32 xres_virtual, yres_virtual; -+ struct rpi_firmware_property_tag_header tag3; -+ u32 bpp; -+ struct rpi_firmware_property_tag_header tag4; -+ u32 xoffset, yoffset; -+ struct rpi_firmware_property_tag_header tag5; -+ u32 base, screen_size; -+ struct rpi_firmware_property_tag_header tag6; -+ u32 pitch; -+}; -+ -+struct bcm2708_fb_stats { -+ struct debugfs_regset32 regset; -+ u32 dma_copies; -+ u32 dma_irqs; -+}; -+ -+struct bcm2708_fb { -+ struct fb_info fb; -+ struct platform_device *dev; -+ struct rpi_firmware *fw; -+ u32 cmap[16]; -+ u32 gpu_cmap[256]; -+ int dma_chan; -+ int dma_irq; -+ void __iomem *dma_chan_base; -+ void *cb_base; /* DMA control blocks */ -+ dma_addr_t cb_handle; -+ struct dentry *debugfs_dir; -+ wait_queue_head_t dma_waitq; -+ struct bcm2708_fb_stats stats; -+ unsigned long fb_bus_address; -+}; -+ -+#define to_bcm2708(info) container_of(info, struct bcm2708_fb, fb) -+ -+static void bcm2708_fb_debugfs_deinit(struct bcm2708_fb *fb) -+{ -+ debugfs_remove_recursive(fb->debugfs_dir); -+ fb->debugfs_dir = NULL; -+} -+ -+static int bcm2708_fb_debugfs_init(struct bcm2708_fb *fb) -+{ -+ static struct debugfs_reg32 stats_registers[] = { -+ { -+ "dma_copies", -+ offsetof(struct bcm2708_fb_stats, dma_copies) -+ }, -+ { -+ "dma_irqs", -+ offsetof(struct bcm2708_fb_stats, dma_irqs) -+ }, -+ }; -+ -+ fb->debugfs_dir = debugfs_create_dir(DRIVER_NAME, NULL); -+ if (!fb->debugfs_dir) { -+ pr_warn("%s: could not create debugfs entry\n", -+ __func__); -+ return -EFAULT; -+ } -+ -+ fb->stats.regset.regs = stats_registers; -+ fb->stats.regset.nregs = ARRAY_SIZE(stats_registers); -+ fb->stats.regset.base = &fb->stats; -+ -+ if (!debugfs_create_regset32( -+ "stats", 0444, fb->debugfs_dir, &fb->stats.regset)) { -+ pr_warn("%s: could not create statistics registers\n", -+ __func__); -+ goto fail; -+ } -+ return 0; -+ -+fail: -+ bcm2708_fb_debugfs_deinit(fb); -+ return -EFAULT; -+} -+ -+static int bcm2708_fb_set_bitfields(struct fb_var_screeninfo *var) -+{ -+ int ret = 0; -+ -+ memset(&var->transp, 0, sizeof(var->transp)); -+ -+ var->red.msb_right = 0; -+ var->green.msb_right = 0; -+ var->blue.msb_right = 0; -+ -+ switch (var->bits_per_pixel) { -+ case 1: -+ case 2: -+ case 4: -+ case 8: -+ var->red.length = var->bits_per_pixel; -+ var->red.offset = 0; -+ var->green.length = var->bits_per_pixel; -+ var->green.offset = 0; -+ var->blue.length = var->bits_per_pixel; -+ var->blue.offset = 0; -+ break; -+ case 16: -+ var->red.length = 5; -+ var->blue.length = 5; -+ /* -+ * Green length can be 5 or 6 depending whether -+ * we're operating in RGB555 or RGB565 mode. -+ */ -+ if (var->green.length != 5 && var->green.length != 6) -+ var->green.length = 6; -+ break; -+ case 24: -+ var->red.length = 8; -+ var->blue.length = 8; -+ var->green.length = 8; -+ break; -+ case 32: -+ var->red.length = 8; -+ var->green.length = 8; -+ var->blue.length = 8; -+ var->transp.length = 8; -+ break; -+ default: -+ ret = -EINVAL; -+ break; -+ } -+ -+ /* -+ * >= 16bpp displays have separate colour component bitfields -+ * encoded in the pixel data. Calculate their position from -+ * the bitfield length defined above. -+ */ -+ if (ret == 0 && var->bits_per_pixel >= 24 && fbswap) { -+ var->blue.offset = 0; -+ var->green.offset = var->blue.offset + var->blue.length; -+ var->red.offset = var->green.offset + var->green.length; -+ var->transp.offset = var->red.offset + var->red.length; -+ } else if (ret == 0 && var->bits_per_pixel >= 24) { -+ var->red.offset = 0; -+ var->green.offset = var->red.offset + var->red.length; -+ var->blue.offset = var->green.offset + var->green.length; -+ var->transp.offset = var->blue.offset + var->blue.length; -+ } else if (ret == 0 && var->bits_per_pixel >= 16) { -+ var->blue.offset = 0; -+ var->green.offset = var->blue.offset + var->blue.length; -+ var->red.offset = var->green.offset + var->green.length; -+ var->transp.offset = var->red.offset + var->red.length; -+ } -+ -+ return ret; -+} -+ -+static int bcm2708_fb_check_var(struct fb_var_screeninfo *var, -+ struct fb_info *info) -+{ -+ /* info input, var output */ -+ int yres; -+ -+ /* info input, var output */ -+ print_debug("bcm2708_fb_check_var info(%p) %dx%d (%dx%d), %d, %d\n", info, -+ info->var.xres, info->var.yres, info->var.xres_virtual, -+ info->var.yres_virtual, (int)info->screen_size, -+ info->var.bits_per_pixel); -+ print_debug("bcm2708_fb_check_var var(%p) %dx%d (%dx%d), %d\n", var, -+ var->xres, var->yres, var->xres_virtual, var->yres_virtual, -+ var->bits_per_pixel); -+ -+ if (!var->bits_per_pixel) -+ var->bits_per_pixel = 16; -+ -+ if (bcm2708_fb_set_bitfields(var) != 0) { -+ pr_err("bcm2708_fb_check_var: invalid bits_per_pixel %d\n", -+ var->bits_per_pixel); -+ return -EINVAL; -+ } -+ -+ -+ if (var->xres_virtual < var->xres) -+ var->xres_virtual = var->xres; -+ /* use highest possible virtual resolution */ -+ if (var->yres_virtual == -1) { -+ var->yres_virtual = 480; -+ -+ pr_err -+ ("bcm2708_fb_check_var: virtual resolution set to maximum of %dx%d\n", -+ var->xres_virtual, var->yres_virtual); -+ } -+ if (var->yres_virtual < var->yres) -+ var->yres_virtual = var->yres; -+ -+ if (var->xoffset < 0) -+ var->xoffset = 0; -+ if (var->yoffset < 0) -+ var->yoffset = 0; -+ -+ /* truncate xoffset and yoffset to maximum if too high */ -+ if (var->xoffset > var->xres_virtual - var->xres) -+ var->xoffset = var->xres_virtual - var->xres - 1; -+ if (var->yoffset > var->yres_virtual - var->yres) -+ var->yoffset = var->yres_virtual - var->yres - 1; -+ -+ return 0; -+} -+ -+static int bcm2708_fb_set_par(struct fb_info *info) -+{ -+ struct bcm2708_fb *fb = to_bcm2708(info); -+ struct fb_alloc_tags fbinfo = { -+ .tag1 = { RPI_FIRMWARE_FRAMEBUFFER_SET_PHYSICAL_WIDTH_HEIGHT, -+ 8, 0, }, -+ .xres = info->var.xres, -+ .yres = info->var.yres, -+ .tag2 = { RPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_WIDTH_HEIGHT, -+ 8, 0, }, -+ .xres_virtual = info->var.xres_virtual, -+ .yres_virtual = info->var.yres_virtual, -+ .tag3 = { RPI_FIRMWARE_FRAMEBUFFER_SET_DEPTH, 4, 0 }, -+ .bpp = info->var.bits_per_pixel, -+ .tag4 = { RPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_OFFSET, 8, 0 }, -+ .xoffset = info->var.xoffset, -+ .yoffset = info->var.yoffset, -+ .tag5 = { RPI_FIRMWARE_FRAMEBUFFER_ALLOCATE, 8, 0 }, -+ .base = 0, -+ .screen_size = 0, -+ .tag6 = { RPI_FIRMWARE_FRAMEBUFFER_GET_PITCH, 4, 0 }, -+ .pitch = 0, -+ }; -+ int ret; -+ -+ print_debug("bcm2708_fb_set_par info(%p) %dx%d (%dx%d), %d, %d\n", info, -+ info->var.xres, info->var.yres, info->var.xres_virtual, -+ info->var.yres_virtual, (int)info->screen_size, -+ info->var.bits_per_pixel); -+ -+ ret = rpi_firmware_property_list(fb->fw, &fbinfo, sizeof(fbinfo)); -+ if (ret) { -+ dev_err(info->device, -+ "Failed to allocate GPU framebuffer (%d)\n", ret); -+ return ret; -+ } -+ -+ if (info->var.bits_per_pixel <= 8) -+ fb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR; -+ else -+ fb->fb.fix.visual = FB_VISUAL_TRUECOLOR; -+ -+ fb->fb.fix.line_length = fbinfo.pitch; -+ fbinfo.base |= 0x40000000; -+ fb->fb_bus_address = fbinfo.base; -+ fbinfo.base &= ~0xc0000000; -+ fb->fb.fix.smem_start = fbinfo.base; -+ fb->fb.fix.smem_len = fbinfo.pitch * fbinfo.yres_virtual; -+ fb->fb.screen_size = fbinfo.screen_size; -+ if (fb->fb.screen_base) -+ iounmap(fb->fb.screen_base); -+ fb->fb.screen_base = ioremap_wc(fbinfo.base, fb->fb.screen_size); -+ if (!fb->fb.screen_base) { -+ /* the console may currently be locked */ -+ console_trylock(); -+ console_unlock(); -+ dev_err(info->device, "Failed to set screen_base\n"); -+ return -ENOMEM; -+ } -+ -+ print_debug -+ ("BCM2708FB: start = %p,%p width=%d, height=%d, bpp=%d, pitch=%d size=%d\n", -+ (void *)fb->fb.screen_base, (void *)fb->fb_bus_address, -+ fbinfo.xres, fbinfo.yres, fbinfo.bpp, -+ fbinfo.pitch, (int)fb->fb.screen_size); -+ -+ return 0; -+} -+ -+static inline u32 convert_bitfield(int val, struct fb_bitfield *bf) -+{ -+ unsigned int mask = (1 << bf->length) - 1; -+ -+ return (val >> (16 - bf->length) & mask) << bf->offset; -+} -+ -+ -+static int bcm2708_fb_setcolreg(unsigned int regno, unsigned int red, -+ unsigned int green, unsigned int blue, -+ unsigned int transp, struct fb_info *info) -+{ -+ struct bcm2708_fb *fb = to_bcm2708(info); -+ -+ /*print_debug("BCM2708FB: setcolreg %d:(%02x,%02x,%02x,%02x) %x\n", regno, red, green, blue, transp, fb->fb.fix.visual);*/ -+ if (fb->fb.var.bits_per_pixel <= 8) { -+ if (regno < 256) { -+ /* blue [23:16], green [15:8], red [7:0] */ -+ fb->gpu_cmap[regno] = ((red >> 8) & 0xff) << 0 | -+ ((green >> 8) & 0xff) << 8 | -+ ((blue >> 8) & 0xff) << 16; -+ } -+ /* Hack: we need to tell GPU the palette has changed, but currently bcm2708_fb_set_par takes noticable time when called for every (256) colour */ -+ /* So just call it for what looks like the last colour in a list for now. */ -+ if (regno == 15 || regno == 255) { -+ struct packet { -+ u32 offset; -+ u32 length; -+ u32 cmap[256]; -+ } *packet; -+ int ret; -+ -+ packet = kmalloc(sizeof(*packet), GFP_KERNEL); -+ if (!packet) -+ return -ENOMEM; -+ packet->offset = 0; -+ packet->length = regno + 1; -+ memcpy(packet->cmap, fb->gpu_cmap, sizeof(packet->cmap)); -+ ret = rpi_firmware_property(fb->fw, RPI_FIRMWARE_FRAMEBUFFER_SET_PALETTE, -+ packet, (2 + packet->length) * sizeof(u32)); -+ if (ret || packet->offset) -+ dev_err(info->device, "Failed to set palette (%d,%u)\n", -+ ret, packet->offset); -+ kfree(packet); -+ } -+ } else if (regno < 16) { -+ fb->cmap[regno] = convert_bitfield(transp, &fb->fb.var.transp) | -+ convert_bitfield(blue, &fb->fb.var.blue) | -+ convert_bitfield(green, &fb->fb.var.green) | -+ convert_bitfield(red, &fb->fb.var.red); -+ } -+ return regno > 255; -+} -+ -+static int bcm2708_fb_blank(int blank_mode, struct fb_info *info) -+{ -+ struct bcm2708_fb *fb = to_bcm2708(info); -+ u32 value; -+ int ret; -+ -+ switch (blank_mode) { -+ case FB_BLANK_UNBLANK: -+ value = 0; -+ break; -+ case FB_BLANK_NORMAL: -+ case FB_BLANK_VSYNC_SUSPEND: -+ case FB_BLANK_HSYNC_SUSPEND: -+ case FB_BLANK_POWERDOWN: -+ value = 1; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ ret = rpi_firmware_property(fb->fw, RPI_FIRMWARE_FRAMEBUFFER_BLANK, -+ &value, sizeof(value)); -+ if (ret) -+ dev_err(info->device, "bcm2708_fb_blank(%d) failed: %d\n", -+ blank_mode, ret); -+ -+ return ret; -+} -+ -+static int bcm2708_fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) -+{ -+ s32 result; -+ info->var.xoffset = var->xoffset; -+ info->var.yoffset = var->yoffset; -+ result = bcm2708_fb_set_par(info); -+ if (result != 0) -+ pr_err("bcm2708_fb_pan_display(%d,%d) returns=%d\n", var->xoffset, var->yoffset, result); -+ return result; -+} -+ -+static int bcm2708_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg) -+{ -+ struct bcm2708_fb *fb = to_bcm2708(info); -+ u32 dummy = 0; -+ int ret; -+ -+ switch (cmd) { -+ case FBIO_WAITFORVSYNC: -+ ret = rpi_firmware_property(fb->fw, -+ RPI_FIRMWARE_FRAMEBUFFER_SET_VSYNC, -+ &dummy, sizeof(dummy)); -+ break; -+ default: -+ dev_dbg(info->device, "Unknown ioctl 0x%x\n", cmd); -+ return -ENOTTY; -+ } -+ -+ if (ret) -+ dev_err(info->device, "ioctl 0x%x failed (%d)\n", cmd, ret); -+ -+ return ret; -+} -+static void bcm2708_fb_fillrect(struct fb_info *info, -+ const struct fb_fillrect *rect) -+{ -+ /* (is called) print_debug("bcm2708_fb_fillrect\n"); */ -+ cfb_fillrect(info, rect); -+} -+ -+/* A helper function for configuring dma control block */ -+static void set_dma_cb(struct bcm2708_dma_cb *cb, -+ int burst_size, -+ dma_addr_t dst, -+ int dst_stride, -+ dma_addr_t src, -+ int src_stride, -+ int w, -+ int h) -+{ -+ cb->info = BCM2708_DMA_BURST(burst_size) | BCM2708_DMA_S_WIDTH | -+ BCM2708_DMA_S_INC | BCM2708_DMA_D_WIDTH | -+ BCM2708_DMA_D_INC | BCM2708_DMA_TDMODE; -+ cb->dst = dst; -+ cb->src = src; -+ /* -+ * This is not really obvious from the DMA documentation, -+ * but the top 16 bits must be programmmed to "height -1" -+ * and not "height" in 2D mode. -+ */ -+ cb->length = ((h - 1) << 16) | w; -+ cb->stride = ((dst_stride - w) << 16) | (u16)(src_stride - w); -+ cb->pad[0] = 0; -+ cb->pad[1] = 0; -+} -+ -+static void bcm2708_fb_copyarea(struct fb_info *info, -+ const struct fb_copyarea *region) -+{ -+ struct bcm2708_fb *fb = to_bcm2708(info); -+ struct bcm2708_dma_cb *cb = fb->cb_base; -+ int bytes_per_pixel = (info->var.bits_per_pixel + 7) >> 3; -+ /* Channel 0 supports larger bursts and is a bit faster */ -+ int burst_size = (fb->dma_chan == 0) ? 8 : 2; -+ int pixels = region->width * region->height; -+ -+ /* Fallback to cfb_copyarea() if we don't like something */ -+ if (in_atomic() || -+ bytes_per_pixel > 4 || -+ info->var.xres * info->var.yres > 1920 * 1200 || -+ region->width <= 0 || region->width > info->var.xres || -+ region->height <= 0 || region->height > info->var.yres || -+ region->sx < 0 || region->sx >= info->var.xres || -+ region->sy < 0 || region->sy >= info->var.yres || -+ region->dx < 0 || region->dx >= info->var.xres || -+ region->dy < 0 || region->dy >= info->var.yres || -+ region->sx + region->width > info->var.xres || -+ region->dx + region->width > info->var.xres || -+ region->sy + region->height > info->var.yres || -+ region->dy + region->height > info->var.yres) { -+ cfb_copyarea(info, region); -+ return; -+ } -+ -+ if (region->dy == region->sy && region->dx > region->sx) { -+ /* -+ * A difficult case of overlapped copy. Because DMA can't -+ * copy individual scanlines in backwards direction, we need -+ * two-pass processing. We do it by programming a chain of dma -+ * control blocks in the first 16K part of the buffer and use -+ * the remaining 48K as the intermediate temporary scratch -+ * buffer. The buffer size is sufficient to handle up to -+ * 1920x1200 resolution at 32bpp pixel depth. -+ */ -+ int y; -+ dma_addr_t control_block_pa = fb->cb_handle; -+ dma_addr_t scratchbuf = fb->cb_handle + 16 * 1024; -+ int scanline_size = bytes_per_pixel * region->width; -+ int scanlines_per_cb = (64 * 1024 - 16 * 1024) / scanline_size; -+ -+ for (y = 0; y < region->height; y += scanlines_per_cb) { -+ dma_addr_t src = -+ fb->fb_bus_address + -+ bytes_per_pixel * region->sx + -+ (region->sy + y) * fb->fb.fix.line_length; -+ dma_addr_t dst = -+ fb->fb_bus_address + -+ bytes_per_pixel * region->dx + -+ (region->dy + y) * fb->fb.fix.line_length; -+ -+ if (region->height - y < scanlines_per_cb) -+ scanlines_per_cb = region->height - y; -+ -+ set_dma_cb(cb, burst_size, scratchbuf, scanline_size, -+ src, fb->fb.fix.line_length, -+ scanline_size, scanlines_per_cb); -+ control_block_pa += sizeof(struct bcm2708_dma_cb); -+ cb->next = control_block_pa; -+ cb++; -+ -+ set_dma_cb(cb, burst_size, dst, fb->fb.fix.line_length, -+ scratchbuf, scanline_size, -+ scanline_size, scanlines_per_cb); -+ control_block_pa += sizeof(struct bcm2708_dma_cb); -+ cb->next = control_block_pa; -+ cb++; -+ } -+ /* move the pointer back to the last dma control block */ -+ cb--; -+ } else { -+ /* A single dma control block is enough. */ -+ int sy, dy, stride; -+ if (region->dy <= region->sy) { -+ /* processing from top to bottom */ -+ dy = region->dy; -+ sy = region->sy; -+ stride = fb->fb.fix.line_length; -+ } else { -+ /* processing from bottom to top */ -+ dy = region->dy + region->height - 1; -+ sy = region->sy + region->height - 1; -+ stride = -fb->fb.fix.line_length; -+ } -+ set_dma_cb(cb, burst_size, -+ fb->fb_bus_address + dy * fb->fb.fix.line_length + -+ bytes_per_pixel * region->dx, -+ stride, -+ fb->fb_bus_address + sy * fb->fb.fix.line_length + -+ bytes_per_pixel * region->sx, -+ stride, -+ region->width * bytes_per_pixel, -+ region->height); -+ } -+ -+ /* end of dma control blocks chain */ -+ cb->next = 0; -+ -+ -+ if (pixels < dma_busy_wait_threshold) { -+ bcm_dma_start(fb->dma_chan_base, fb->cb_handle); -+ bcm_dma_wait_idle(fb->dma_chan_base); -+ } else { -+ void __iomem *dma_chan = fb->dma_chan_base; -+ cb->info |= BCM2708_DMA_INT_EN; -+ bcm_dma_start(fb->dma_chan_base, fb->cb_handle); -+ while (bcm_dma_is_busy(dma_chan)) { -+ wait_event_interruptible( -+ fb->dma_waitq, -+ !bcm_dma_is_busy(dma_chan)); -+ } -+ fb->stats.dma_irqs++; -+ } -+ fb->stats.dma_copies++; -+} -+ -+static void bcm2708_fb_imageblit(struct fb_info *info, -+ const struct fb_image *image) -+{ -+ /* (is called) print_debug("bcm2708_fb_imageblit\n"); */ -+ cfb_imageblit(info, image); -+} -+ -+static irqreturn_t bcm2708_fb_dma_irq(int irq, void *cxt) -+{ -+ struct bcm2708_fb *fb = cxt; -+ -+ /* FIXME: should read status register to check if this is -+ * actually interrupting us or not, in case this interrupt -+ * ever becomes shared amongst several DMA channels -+ * -+ * readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_IRQ; -+ */ -+ -+ /* acknowledge the interrupt */ -+ writel(BCM2708_DMA_INT, fb->dma_chan_base + BCM2708_DMA_CS); -+ -+ wake_up(&fb->dma_waitq); -+ return IRQ_HANDLED; -+} -+ -+static struct fb_ops bcm2708_fb_ops = { -+ .owner = THIS_MODULE, -+ .fb_check_var = bcm2708_fb_check_var, -+ .fb_set_par = bcm2708_fb_set_par, -+ .fb_setcolreg = bcm2708_fb_setcolreg, -+ .fb_blank = bcm2708_fb_blank, -+ .fb_fillrect = bcm2708_fb_fillrect, -+ .fb_copyarea = bcm2708_fb_copyarea, -+ .fb_imageblit = bcm2708_fb_imageblit, -+ .fb_pan_display = bcm2708_fb_pan_display, -+ .fb_ioctl = bcm2708_ioctl, -+}; -+ -+static int bcm2708_fb_register(struct bcm2708_fb *fb) -+{ -+ int ret; -+ -+ fb->fb.fbops = &bcm2708_fb_ops; -+ fb->fb.flags = FBINFO_FLAG_DEFAULT | FBINFO_HWACCEL_COPYAREA; -+ fb->fb.pseudo_palette = fb->cmap; -+ -+ strncpy(fb->fb.fix.id, bcm2708_name, sizeof(fb->fb.fix.id)); -+ fb->fb.fix.type = FB_TYPE_PACKED_PIXELS; -+ fb->fb.fix.type_aux = 0; -+ fb->fb.fix.xpanstep = 1; -+ fb->fb.fix.ypanstep = 1; -+ fb->fb.fix.ywrapstep = 0; -+ fb->fb.fix.accel = FB_ACCEL_NONE; -+ -+ fb->fb.var.xres = fbwidth; -+ fb->fb.var.yres = fbheight; -+ fb->fb.var.xres_virtual = fbwidth; -+ fb->fb.var.yres_virtual = fbheight; -+ fb->fb.var.bits_per_pixel = fbdepth; -+ fb->fb.var.vmode = FB_VMODE_NONINTERLACED; -+ fb->fb.var.activate = FB_ACTIVATE_NOW; -+ fb->fb.var.nonstd = 0; -+ fb->fb.var.height = -1; /* height of picture in mm */ -+ fb->fb.var.width = -1; /* width of picture in mm */ -+ fb->fb.var.accel_flags = 0; -+ -+ fb->fb.monspecs.hfmin = 0; -+ fb->fb.monspecs.hfmax = 100000; -+ fb->fb.monspecs.vfmin = 0; -+ fb->fb.monspecs.vfmax = 400; -+ fb->fb.monspecs.dclkmin = 1000000; -+ fb->fb.monspecs.dclkmax = 100000000; -+ -+ bcm2708_fb_set_bitfields(&fb->fb.var); -+ init_waitqueue_head(&fb->dma_waitq); -+ -+ /* -+ * Allocate colourmap. -+ */ -+ -+ fb_set_var(&fb->fb, &fb->fb.var); -+ ret = bcm2708_fb_set_par(&fb->fb); -+ if (ret) -+ return ret; -+ -+ print_debug("BCM2708FB: registering framebuffer (%dx%d@%d) (%d)\n", fbwidth, -+ fbheight, fbdepth, fbswap); -+ -+ ret = register_framebuffer(&fb->fb); -+ print_debug("BCM2708FB: register framebuffer (%d)\n", ret); -+ if (ret == 0) -+ goto out; -+ -+ print_debug("BCM2708FB: cannot register framebuffer (%d)\n", ret); -+out: -+ return ret; -+} -+ -+static int bcm2708_fb_probe(struct platform_device *dev) -+{ -+ struct device_node *fw_np; -+ struct rpi_firmware *fw; -+ struct bcm2708_fb *fb; -+ int ret; -+ -+ fw_np = of_parse_phandle(dev->dev.of_node, "firmware", 0); -+/* Remove comment when booting without Device Tree is no longer supported -+ if (!fw_np) { -+ dev_err(&dev->dev, "Missing firmware node\n"); -+ return -ENOENT; -+ } -+*/ -+ fw = rpi_firmware_get(fw_np); -+ if (!fw) -+ return -EPROBE_DEFER; -+ -+ fb = kzalloc(sizeof(struct bcm2708_fb), GFP_KERNEL); -+ if (!fb) { -+ dev_err(&dev->dev, -+ "could not allocate new bcm2708_fb struct\n"); -+ ret = -ENOMEM; -+ goto free_region; -+ } -+ -+ fb->fw = fw; -+ bcm2708_fb_debugfs_init(fb); -+ -+ fb->cb_base = dma_alloc_writecombine(&dev->dev, SZ_64K, -+ &fb->cb_handle, GFP_KERNEL); -+ if (!fb->cb_base) { -+ dev_err(&dev->dev, "cannot allocate DMA CBs\n"); -+ ret = -ENOMEM; -+ goto free_fb; -+ } -+ -+ pr_info("BCM2708FB: allocated DMA memory %08x\n", -+ fb->cb_handle); -+ -+ ret = bcm_dma_chan_alloc(BCM_DMA_FEATURE_BULK, -+ &fb->dma_chan_base, &fb->dma_irq); -+ if (ret < 0) { -+ dev_err(&dev->dev, "couldn't allocate a DMA channel\n"); -+ goto free_cb; -+ } -+ fb->dma_chan = ret; -+ -+ ret = request_irq(fb->dma_irq, bcm2708_fb_dma_irq, -+ 0, "bcm2708_fb dma", fb); -+ if (ret) { -+ pr_err("%s: failed to request DMA irq\n", __func__); -+ goto free_dma_chan; -+ } -+ -+ -+ pr_info("BCM2708FB: allocated DMA channel %d @ %p\n", -+ fb->dma_chan, fb->dma_chan_base); -+ -+ fb->dev = dev; -+ fb->fb.device = &dev->dev; -+ -+ ret = bcm2708_fb_register(fb); -+ if (ret == 0) { -+ platform_set_drvdata(dev, fb); -+ goto out; -+ } -+ -+free_dma_chan: -+ bcm_dma_chan_free(fb->dma_chan); -+free_cb: -+ dma_free_writecombine(&dev->dev, SZ_64K, fb->cb_base, fb->cb_handle); -+free_fb: -+ kfree(fb); -+free_region: -+ dev_err(&dev->dev, "probe failed, err %d\n", ret); -+out: -+ return ret; -+} -+ -+static int bcm2708_fb_remove(struct platform_device *dev) -+{ -+ struct bcm2708_fb *fb = platform_get_drvdata(dev); -+ -+ platform_set_drvdata(dev, NULL); -+ -+ if (fb->fb.screen_base) -+ iounmap(fb->fb.screen_base); -+ unregister_framebuffer(&fb->fb); -+ -+ dma_free_writecombine(&dev->dev, SZ_64K, fb->cb_base, fb->cb_handle); -+ bcm_dma_chan_free(fb->dma_chan); -+ -+ bcm2708_fb_debugfs_deinit(fb); -+ -+ free_irq(fb->dma_irq, fb); -+ -+ kfree(fb); -+ -+ return 0; -+} -+ -+static const struct of_device_id bcm2708_fb_of_match_table[] = { -+ { .compatible = "brcm,bcm2708-fb", }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, bcm2708_fb_of_match_table); -+ -+static struct platform_driver bcm2708_fb_driver = { -+ .probe = bcm2708_fb_probe, -+ .remove = bcm2708_fb_remove, -+ .driver = { -+ .name = DRIVER_NAME, -+ .owner = THIS_MODULE, -+ .of_match_table = bcm2708_fb_of_match_table, -+ }, -+}; -+ -+static int __init bcm2708_fb_init(void) -+{ -+ return platform_driver_register(&bcm2708_fb_driver); -+} -+ -+module_init(bcm2708_fb_init); -+ -+static void __exit bcm2708_fb_exit(void) -+{ -+ platform_driver_unregister(&bcm2708_fb_driver); -+} -+ -+module_exit(bcm2708_fb_exit); -+ -+module_param(fbwidth, int, 0644); -+module_param(fbheight, int, 0644); -+module_param(fbdepth, int, 0644); -+module_param(fbswap, int, 0644); -+ -+MODULE_DESCRIPTION("BCM2708 framebuffer driver"); -+MODULE_LICENSE("GPL"); -+ -+MODULE_PARM_DESC(fbwidth, "Width of ARM Framebuffer"); -+MODULE_PARM_DESC(fbheight, "Height of ARM Framebuffer"); -+MODULE_PARM_DESC(fbdepth, "Bit depth of ARM Framebuffer"); -+MODULE_PARM_DESC(fbswap, "Swap order of red and blue in 24 and 32 bit modes"); -diff -Nur linux-4.1.13.orig/drivers/video/fbdev/core/cfbimgblt.c linux-rpi/drivers/video/fbdev/core/cfbimgblt.c ---- linux-4.1.13.orig/drivers/video/fbdev/core/cfbimgblt.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/video/fbdev/core/cfbimgblt.c 2015-11-29 09:42:40.075088329 +0100 -@@ -28,6 +28,11 @@ - * - * Also need to add code to deal with cards endians that are different than - * the native cpu endians. I also need to deal with MSB position in the word. -+ * Modified by Harm Hanemaaijer (fgenfb@yahoo.com) 2013: -+ * - Provide optimized versions of fast_imageblit for 16 and 32bpp that are -+ * significantly faster than the previous implementation. -+ * - Simplify the fast/slow_imageblit selection code, avoiding integer -+ * divides. - */ - #include - #include -@@ -262,6 +267,133 @@ - } - } - -+/* -+ * Optimized fast_imageblit for bpp == 16. ppw = 2, bit_mask = 3 folded -+ * into the code, main loop unrolled. -+ */ -+ -+static inline void fast_imageblit16(const struct fb_image *image, -+ struct fb_info *p, u8 __iomem * dst1, -+ u32 fgcolor, u32 bgcolor) -+{ -+ u32 fgx = fgcolor, bgx = bgcolor; -+ u32 spitch = (image->width + 7) / 8; -+ u32 end_mask, eorx; -+ const char *s = image->data, *src; -+ u32 __iomem *dst; -+ const u32 *tab = NULL; -+ int i, j, k; -+ -+ tab = fb_be_math(p) ? cfb_tab16_be : cfb_tab16_le; -+ -+ fgx <<= 16; -+ bgx <<= 16; -+ fgx |= fgcolor; -+ bgx |= bgcolor; -+ -+ eorx = fgx ^ bgx; -+ k = image->width / 2; -+ -+ for (i = image->height; i--;) { -+ dst = (u32 __iomem *) dst1; -+ src = s; -+ -+ j = k; -+ while (j >= 4) { -+ u8 bits = *src; -+ end_mask = tab[(bits >> 6) & 3]; -+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); -+ end_mask = tab[(bits >> 4) & 3]; -+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); -+ end_mask = tab[(bits >> 2) & 3]; -+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); -+ end_mask = tab[bits & 3]; -+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); -+ src++; -+ j -= 4; -+ } -+ if (j != 0) { -+ u8 bits = *src; -+ end_mask = tab[(bits >> 6) & 3]; -+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); -+ if (j >= 2) { -+ end_mask = tab[(bits >> 4) & 3]; -+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); -+ if (j == 3) { -+ end_mask = tab[(bits >> 2) & 3]; -+ FB_WRITEL((end_mask & eorx) ^ bgx, dst); -+ } -+ } -+ } -+ dst1 += p->fix.line_length; -+ s += spitch; -+ } -+} -+ -+/* -+ * Optimized fast_imageblit for bpp == 32. ppw = 1, bit_mask = 1 folded -+ * into the code, main loop unrolled. -+ */ -+ -+static inline void fast_imageblit32(const struct fb_image *image, -+ struct fb_info *p, u8 __iomem * dst1, -+ u32 fgcolor, u32 bgcolor) -+{ -+ u32 fgx = fgcolor, bgx = bgcolor; -+ u32 spitch = (image->width + 7) / 8; -+ u32 end_mask, eorx; -+ const char *s = image->data, *src; -+ u32 __iomem *dst; -+ const u32 *tab = NULL; -+ int i, j, k; -+ -+ tab = cfb_tab32; -+ -+ eorx = fgx ^ bgx; -+ k = image->width; -+ -+ for (i = image->height; i--;) { -+ dst = (u32 __iomem *) dst1; -+ src = s; -+ -+ j = k; -+ while (j >= 8) { -+ u8 bits = *src; -+ end_mask = tab[(bits >> 7) & 1]; -+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); -+ end_mask = tab[(bits >> 6) & 1]; -+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); -+ end_mask = tab[(bits >> 5) & 1]; -+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); -+ end_mask = tab[(bits >> 4) & 1]; -+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); -+ end_mask = tab[(bits >> 3) & 1]; -+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); -+ end_mask = tab[(bits >> 2) & 1]; -+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); -+ end_mask = tab[(bits >> 1) & 1]; -+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); -+ end_mask = tab[bits & 1]; -+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); -+ src++; -+ j -= 8; -+ } -+ if (j != 0) { -+ u32 bits = (u32) * src; -+ while (j > 1) { -+ end_mask = tab[(bits >> 7) & 1]; -+ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); -+ bits <<= 1; -+ j--; -+ } -+ end_mask = tab[(bits >> 7) & 1]; -+ FB_WRITEL((end_mask & eorx) ^ bgx, dst); -+ } -+ dst1 += p->fix.line_length; -+ s += spitch; -+ } -+} -+ - void cfb_imageblit(struct fb_info *p, const struct fb_image *image) - { - u32 fgcolor, bgcolor, start_index, bitstart, pitch_index = 0; -@@ -294,11 +426,21 @@ - bgcolor = image->bg_color; - } - -- if (32 % bpp == 0 && !start_index && !pitch_index && -- ((width & (32/bpp-1)) == 0) && -- bpp >= 8 && bpp <= 32) -- fast_imageblit(image, p, dst1, fgcolor, bgcolor); -- else -+ if (!start_index && !pitch_index) { -+ if (bpp == 32) -+ fast_imageblit32(image, p, dst1, fgcolor, -+ bgcolor); -+ else if (bpp == 16 && (width & 1) == 0) -+ fast_imageblit16(image, p, dst1, fgcolor, -+ bgcolor); -+ else if (bpp == 8 && (width & 3) == 0) -+ fast_imageblit(image, p, dst1, fgcolor, -+ bgcolor); -+ else -+ slow_imageblit(image, p, dst1, fgcolor, -+ bgcolor, -+ start_index, pitch_index); -+ } else - slow_imageblit(image, p, dst1, fgcolor, bgcolor, - start_index, pitch_index); - } else -diff -Nur linux-4.1.13.orig/drivers/video/fbdev/core/fbmem.c linux-rpi/drivers/video/fbdev/core/fbmem.c ---- linux-4.1.13.orig/drivers/video/fbdev/core/fbmem.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/video/fbdev/core/fbmem.c 2015-11-29 09:42:40.075088329 +0100 -@@ -1084,6 +1084,25 @@ - } - EXPORT_SYMBOL(fb_blank); - -+static int fb_copyarea_user(struct fb_info *info, -+ struct fb_copyarea *copy) -+{ -+ int ret = 0; -+ if (!lock_fb_info(info)) -+ return -ENODEV; -+ if (copy->dx + copy->width > info->var.xres || -+ copy->sx + copy->width > info->var.xres || -+ copy->dy + copy->height > info->var.yres || -+ copy->sy + copy->height > info->var.yres) { -+ ret = -EINVAL; -+ goto out; -+ } -+ info->fbops->fb_copyarea(info, copy); -+out: -+ unlock_fb_info(info); -+ return ret; -+} -+ - static long do_fb_ioctl(struct fb_info *info, unsigned int cmd, - unsigned long arg) - { -@@ -1094,6 +1113,7 @@ - struct fb_cmap cmap_from; - struct fb_cmap_user cmap; - struct fb_event event; -+ struct fb_copyarea copy; - void __user *argp = (void __user *)arg; - long ret = 0; - -@@ -1211,6 +1231,15 @@ - unlock_fb_info(info); - console_unlock(); - break; -+ case FBIOCOPYAREA: -+ if (info->flags & FBINFO_HWACCEL_COPYAREA) { -+ /* only provide this ioctl if it is accelerated */ -+ if (copy_from_user(©, argp, sizeof(copy))) -+ return -EFAULT; -+ ret = fb_copyarea_user(info, ©); -+ break; -+ } -+ /* fall through */ - default: - if (!lock_fb_info(info)) - return -ENODEV; -@@ -1365,6 +1394,7 @@ - case FBIOPAN_DISPLAY: - case FBIOGET_CON2FBMAP: - case FBIOPUT_CON2FBMAP: -+ case FBIOCOPYAREA: - arg = (unsigned long) compat_ptr(arg); - case FBIOBLANK: - ret = do_fb_ioctl(info, cmd, arg); -diff -Nur linux-4.1.13.orig/drivers/video/fbdev/Kconfig linux-rpi/drivers/video/fbdev/Kconfig ---- linux-4.1.13.orig/drivers/video/fbdev/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/video/fbdev/Kconfig 2015-11-29 09:42:40.031091253 +0100 -@@ -224,6 +224,20 @@ - comment "Frame buffer hardware drivers" - depends on FB - -+config FB_BCM2708 -+ tristate "BCM2708 framebuffer support" -+ depends on FB && RASPBERRYPI_FIRMWARE -+ select FB_CFB_FILLRECT -+ select FB_CFB_COPYAREA -+ select FB_CFB_IMAGEBLIT -+ help -+ This framebuffer device driver is for the BCM2708 framebuffer. -+ -+ If you want to compile this as a module (=code which can be -+ inserted into and removed from the running kernel), say M -+ here and read . The module -+ will be called bcm2708_fb. -+ - config FB_GRVGA - tristate "Aeroflex Gaisler framebuffer support" - depends on FB && SPARC -@@ -2481,3 +2495,16 @@ - help - This driver implements support for the Solomon SSD1307 - OLED controller over I2C. -+ -+config FB_RPISENSE -+ tristate "Raspberry Pi Sense HAT framebuffer" -+ depends on FB -+ select MFD_RPISENSE_CORE -+ select FB_SYS_FOPS -+ select FB_SYS_FILLRECT -+ select FB_SYS_COPYAREA -+ select FB_SYS_IMAGEBLIT -+ select FB_DEFERRED_IO -+ -+ help -+ This is the framebuffer driver for the Raspberry Pi Sense HAT -diff -Nur linux-4.1.13.orig/drivers/video/fbdev/Makefile linux-rpi/drivers/video/fbdev/Makefile ---- linux-4.1.13.orig/drivers/video/fbdev/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/video/fbdev/Makefile 2015-11-29 09:42:40.031091253 +0100 -@@ -12,6 +12,7 @@ - obj-$(CONFIG_FB_WMT_GE_ROPS) += wmt_ge_rops.o - - # Hardware specific drivers go first -+obj-$(CONFIG_FB_BCM2708) += bcm2708_fb.o - obj-$(CONFIG_FB_AMIGA) += amifb.o c2p_planar.o - obj-$(CONFIG_FB_ARC) += arcfb.o - obj-$(CONFIG_FB_CLPS711X) += clps711x-fb.o -@@ -149,6 +150,7 @@ - obj-$(CONFIG_FB_MXS) += mxsfb.o - obj-$(CONFIG_FB_SSD1307) += ssd1307fb.o - obj-$(CONFIG_FB_SIMPLE) += simplefb.o -+obj-$(CONFIG_FB_RPISENSE) += rpisense-fb.o - - # the test framebuffer is last - obj-$(CONFIG_FB_VIRTUAL) += vfb.o -diff -Nur linux-4.1.13.orig/drivers/video/fbdev/rpisense-fb.c linux-rpi/drivers/video/fbdev/rpisense-fb.c ---- linux-4.1.13.orig/drivers/video/fbdev/rpisense-fb.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/video/fbdev/rpisense-fb.c 2015-11-29 09:42:40.111085937 +0100 -@@ -0,0 +1,293 @@ -+/* -+ * Raspberry Pi Sense HAT framebuffer driver -+ * http://raspberrypi.org -+ * -+ * Copyright (C) 2015 Raspberry Pi -+ * -+ * Author: Serge Schneider -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+static bool lowlight; -+module_param(lowlight, bool, 0); -+MODULE_PARM_DESC(lowlight, "Reduce LED matrix brightness to one third"); -+ -+struct rpisense *rpisense; -+ -+struct rpisense_fb_param { -+ char __iomem *vmem; -+ u8 *vmem_work; -+ u32 vmemsize; -+ u8 *gamma; -+}; -+ -+static u8 gamma_default[32] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, -+ 0x02, 0x02, 0x03, 0x03, 0x04, 0x05, 0x06, 0x07, -+ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0E, 0x0F, 0x11, -+ 0x12, 0x14, 0x15, 0x17, 0x19, 0x1B, 0x1D, 0x1F,}; -+ -+static u8 gamma_low[32] = {0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, -+ 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x02, 0x02, -+ 0x03, 0x03, 0x03, 0x04, 0x04, 0x05, 0x05, 0x06, -+ 0x06, 0x07, 0x07, 0x08, 0x08, 0x09, 0x0A, 0x0A,}; -+ -+static u8 gamma_user[32]; -+ -+static struct rpisense_fb_param rpisense_fb_param = { -+ .vmem = NULL, -+ .vmemsize = 128, -+ .gamma = gamma_default, -+}; -+ -+static struct fb_deferred_io rpisense_fb_defio; -+ -+static struct fb_fix_screeninfo rpisense_fb_fix = { -+ .id = "RPi-Sense FB", -+ .type = FB_TYPE_PACKED_PIXELS, -+ .visual = FB_VISUAL_TRUECOLOR, -+ .xpanstep = 0, -+ .ypanstep = 0, -+ .ywrapstep = 0, -+ .accel = FB_ACCEL_NONE, -+ .line_length = 16, -+}; -+ -+static struct fb_var_screeninfo rpisense_fb_var = { -+ .xres = 8, -+ .yres = 8, -+ .xres_virtual = 8, -+ .yres_virtual = 8, -+ .bits_per_pixel = 16, -+ .red = {11, 5, 0}, -+ .green = {5, 6, 0}, -+ .blue = {0, 5, 0}, -+}; -+ -+static ssize_t rpisense_fb_write(struct fb_info *info, -+ const char __user *buf, size_t count, -+ loff_t *ppos) -+{ -+ ssize_t res = fb_sys_write(info, buf, count, ppos); -+ -+ schedule_delayed_work(&info->deferred_work, rpisense_fb_defio.delay); -+ return res; -+} -+ -+static void rpisense_fb_fillrect(struct fb_info *info, -+ const struct fb_fillrect *rect) -+{ -+ sys_fillrect(info, rect); -+ schedule_delayed_work(&info->deferred_work, rpisense_fb_defio.delay); -+} -+ -+static void rpisense_fb_copyarea(struct fb_info *info, -+ const struct fb_copyarea *area) -+{ -+ sys_copyarea(info, area); -+ schedule_delayed_work(&info->deferred_work, rpisense_fb_defio.delay); -+} -+ -+static void rpisense_fb_imageblit(struct fb_info *info, -+ const struct fb_image *image) -+{ -+ sys_imageblit(info, image); -+ schedule_delayed_work(&info->deferred_work, rpisense_fb_defio.delay); -+} -+ -+static void rpisense_fb_deferred_io(struct fb_info *info, -+ struct list_head *pagelist) -+{ -+ int i; -+ int j; -+ u8 *vmem_work = rpisense_fb_param.vmem_work; -+ u16 *mem = (u16 *)rpisense_fb_param.vmem; -+ u8 *gamma = rpisense_fb_param.gamma; -+ -+ vmem_work[0] = 0; -+ for (j = 0; j < 8; j++) { -+ for (i = 0; i < 8; i++) { -+ vmem_work[(j * 24) + i + 1] = -+ gamma[(mem[(j * 8) + i] >> 11) & 0x1F]; -+ vmem_work[(j * 24) + (i + 8) + 1] = -+ gamma[(mem[(j * 8) + i] >> 6) & 0x1F]; -+ vmem_work[(j * 24) + (i + 16) + 1] = -+ gamma[(mem[(j * 8) + i]) & 0x1F]; -+ } -+ } -+ rpisense_block_write(rpisense, vmem_work, 193); -+} -+ -+static struct fb_deferred_io rpisense_fb_defio = { -+ .delay = HZ/100, -+ .deferred_io = rpisense_fb_deferred_io, -+}; -+ -+static int rpisense_fb_ioctl(struct fb_info *info, unsigned int cmd, -+ unsigned long arg) -+{ -+ switch (cmd) { -+ case SENSEFB_FBIOGET_GAMMA: -+ if (copy_to_user((void __user *) arg, rpisense_fb_param.gamma, -+ sizeof(u8[32]))) -+ return -EFAULT; -+ return 0; -+ case SENSEFB_FBIOSET_GAMMA: -+ if (copy_from_user(gamma_user, (void __user *)arg, -+ sizeof(u8[32]))) -+ return -EFAULT; -+ rpisense_fb_param.gamma = gamma_user; -+ schedule_delayed_work(&info->deferred_work, -+ rpisense_fb_defio.delay); -+ return 0; -+ case SENSEFB_FBIORESET_GAMMA: -+ switch (arg) { -+ case 0: -+ rpisense_fb_param.gamma = gamma_default; -+ break; -+ case 1: -+ rpisense_fb_param.gamma = gamma_low; -+ break; -+ case 2: -+ rpisense_fb_param.gamma = gamma_user; -+ break; -+ default: -+ return -EINVAL; -+ } -+ schedule_delayed_work(&info->deferred_work, -+ rpisense_fb_defio.delay); -+ break; -+ default: -+ return -EINVAL; -+ } -+ return 0; -+} -+ -+static struct fb_ops rpisense_fb_ops = { -+ .owner = THIS_MODULE, -+ .fb_read = fb_sys_read, -+ .fb_write = rpisense_fb_write, -+ .fb_fillrect = rpisense_fb_fillrect, -+ .fb_copyarea = rpisense_fb_copyarea, -+ .fb_imageblit = rpisense_fb_imageblit, -+ .fb_ioctl = rpisense_fb_ioctl, -+}; -+ -+static int rpisense_fb_probe(struct platform_device *pdev) -+{ -+ struct fb_info *info; -+ int ret = -ENOMEM; -+ struct rpisense_fb *rpisense_fb; -+ -+ rpisense = rpisense_get_dev(); -+ rpisense_fb = &rpisense->framebuffer; -+ -+ rpisense_fb_param.vmem = vzalloc(rpisense_fb_param.vmemsize); -+ if (!rpisense_fb_param.vmem) -+ return ret; -+ -+ rpisense_fb_param.vmem_work = devm_kmalloc(&pdev->dev, 193, GFP_KERNEL); -+ if (!rpisense_fb_param.vmem_work) -+ goto err_malloc; -+ -+ info = framebuffer_alloc(0, &pdev->dev); -+ if (!info) { -+ dev_err(&pdev->dev, "Could not allocate framebuffer.\n"); -+ goto err_malloc; -+ } -+ rpisense_fb->info = info; -+ -+ rpisense_fb_fix.smem_start = (unsigned long)rpisense_fb_param.vmem; -+ rpisense_fb_fix.smem_len = rpisense_fb_param.vmemsize; -+ -+ info->fbops = &rpisense_fb_ops; -+ info->fix = rpisense_fb_fix; -+ info->var = rpisense_fb_var; -+ info->fbdefio = &rpisense_fb_defio; -+ info->flags = FBINFO_FLAG_DEFAULT | FBINFO_VIRTFB; -+ info->screen_base = rpisense_fb_param.vmem; -+ info->screen_size = rpisense_fb_param.vmemsize; -+ -+ if (lowlight) -+ rpisense_fb_param.gamma = gamma_low; -+ -+ fb_deferred_io_init(info); -+ -+ ret = register_framebuffer(info); -+ if (ret < 0) { -+ dev_err(&pdev->dev, "Could not register framebuffer.\n"); -+ goto err_fballoc; -+ } -+ -+ fb_info(info, "%s frame buffer device\n", info->fix.id); -+ schedule_delayed_work(&info->deferred_work, rpisense_fb_defio.delay); -+ return 0; -+err_fballoc: -+ framebuffer_release(info); -+err_malloc: -+ vfree(rpisense_fb_param.vmem); -+ return ret; -+} -+ -+static int rpisense_fb_remove(struct platform_device *pdev) -+{ -+ struct rpisense_fb *rpisense_fb = &rpisense->framebuffer; -+ struct fb_info *info = rpisense_fb->info; -+ -+ if (info) { -+ unregister_framebuffer(info); -+ fb_deferred_io_cleanup(info); -+ framebuffer_release(info); -+ vfree(rpisense_fb_param.vmem); -+ } -+ -+ return 0; -+} -+ -+#ifdef CONFIG_OF -+static const struct of_device_id rpisense_fb_id[] = { -+ { .compatible = "rpi,rpi-sense-fb" }, -+ { }, -+}; -+MODULE_DEVICE_TABLE(of, rpisense_fb_id); -+#endif -+ -+static struct platform_device_id rpisense_fb_device_id[] = { -+ { .name = "rpi-sense-fb" }, -+ { }, -+}; -+MODULE_DEVICE_TABLE(platform, rpisense_fb_device_id); -+ -+static struct platform_driver rpisense_fb_driver = { -+ .probe = rpisense_fb_probe, -+ .remove = rpisense_fb_remove, -+ .driver = { -+ .name = "rpi-sense-fb", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+module_platform_driver(rpisense_fb_driver); -+ -+MODULE_DESCRIPTION("Raspberry Pi Sense HAT framebuffer driver"); -+MODULE_AUTHOR("Serge Schneider "); -+MODULE_LICENSE("GPL"); -+ -diff -Nur linux-4.1.13.orig/drivers/video/logo/logo_linux_clut224.ppm linux-rpi/drivers/video/logo/logo_linux_clut224.ppm ---- linux-4.1.13.orig/drivers/video/logo/logo_linux_clut224.ppm 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/video/logo/logo_linux_clut224.ppm 2015-11-29 09:42:40.131084608 +0100 -@@ -1,1604 +1,883 @@ - P3 --# Standard 224-color Linux logo --80 80 -+63 80 - 255 -- 0 0 0 0 0 0 0 0 0 0 0 0 -- 0 0 0 0 0 0 0 0 0 0 0 0 -- 0 0 0 0 0 0 0 0 0 0 0 0 -- 0 0 0 0 0 0 0 0 0 0 0 0 -- 0 0 0 0 0 0 0 0 0 0 0 0 -- 0 0 0 0 0 0 0 0 0 0 0 0 -- 0 0 0 0 0 0 0 0 0 0 0 0 -- 0 0 0 0 0 0 0 0 0 0 0 0 -- 0 0 0 0 0 0 0 0 0 0 0 0 -- 6 6 6 6 6 6 10 10 10 10 10 10 -- 10 10 10 6 6 6 6 6 6 6 6 6 -- 0 0 0 0 0 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0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -+0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -+0 0 0 0 0 0 0 0 0 -diff -Nur linux-4.1.13.orig/drivers/w1/masters/w1-gpio.c linux-rpi/drivers/w1/masters/w1-gpio.c ---- linux-4.1.13.orig/drivers/w1/masters/w1-gpio.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/w1/masters/w1-gpio.c 2015-11-29 09:42:40.139084077 +0100 -@@ -23,6 +23,19 @@ - #include "../w1.h" - #include "../w1_int.h" - -+static int w1_gpio_pullup = 0; -+static int w1_gpio_pullup_orig = 0; -+module_param_named(pullup, w1_gpio_pullup, int, 0); -+MODULE_PARM_DESC(pullup, "Enable parasitic power (power on data) mode"); -+static int w1_gpio_pullup_pin = -1; -+static int w1_gpio_pullup_pin_orig = -1; -+module_param_named(extpullup, w1_gpio_pullup_pin, int, 0); -+MODULE_PARM_DESC(extpullup, "GPIO external pullup pin number"); -+static int w1_gpio_pin = -1; -+static int w1_gpio_pin_orig = -1; -+module_param_named(gpiopin, w1_gpio_pin, int, 0); -+MODULE_PARM_DESC(gpiopin, "GPIO pin number"); -+ - static u8 w1_gpio_set_pullup(void *data, int delay) - { - struct w1_gpio_platform_data *pdata = data; -@@ -67,6 +80,16 @@ - return gpio_get_value(pdata->pin) ? 1 : 0; - } - -+static void w1_gpio_bitbang_pullup(void *data, u8 on) -+{ -+ struct w1_gpio_platform_data *pdata = data; -+ -+ if (on) -+ gpio_direction_output(pdata->pin, 1); -+ else -+ gpio_direction_input(pdata->pin); -+} -+ - #if defined(CONFIG_OF) - static const struct of_device_id w1_gpio_dt_ids[] = { - { .compatible = "w1-gpio" }, -@@ -80,6 +103,7 @@ - struct w1_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev); - struct device_node *np = pdev->dev.of_node; - int gpio; -+ u32 value; - - pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); - if (!pdata) -@@ -88,6 +112,9 @@ - if (of_get_property(np, "linux,open-drain", NULL)) - pdata->is_open_drain = 1; - -+ if (of_property_read_u32(np, "rpi,parasitic-power", &value) == 0) -+ pdata->parasitic_power = (value != 0); -+ - gpio = of_get_gpio(np, 0); - if (gpio < 0) { - if (gpio != -EPROBE_DEFER) -@@ -103,7 +130,7 @@ - if (gpio == -EPROBE_DEFER) - return gpio; - /* ignore other errors as the pullup gpio is optional */ -- pdata->ext_pullup_enable_pin = gpio; -+ pdata->ext_pullup_enable_pin = (gpio >= 0) ? gpio : -1; - - pdev->dev.platform_data = pdata; - -@@ -113,13 +140,15 @@ - static int w1_gpio_probe(struct platform_device *pdev) - { - struct w1_bus_master *master; -- struct w1_gpio_platform_data *pdata; -+ struct w1_gpio_platform_data *pdata = pdev->dev.platform_data; - int err; - -- if (of_have_populated_dt()) { -- err = w1_gpio_probe_dt(pdev); -- if (err < 0) -- return err; -+ if(pdata == NULL) { -+ if (of_have_populated_dt()) { -+ err = w1_gpio_probe_dt(pdev); -+ if (err < 0) -+ return err; -+ } - } - - pdata = dev_get_platdata(&pdev->dev); -@@ -136,6 +165,22 @@ - return -ENOMEM; - } - -+ w1_gpio_pin_orig = pdata->pin; -+ w1_gpio_pullup_pin_orig = pdata->ext_pullup_enable_pin; -+ w1_gpio_pullup_orig = pdata->parasitic_power; -+ -+ if(gpio_is_valid(w1_gpio_pin)) { -+ pdata->pin = w1_gpio_pin; -+ pdata->ext_pullup_enable_pin = -1; -+ pdata->parasitic_power = -1; -+ } -+ pdata->parasitic_power |= w1_gpio_pullup; -+ if(gpio_is_valid(w1_gpio_pullup_pin)) { -+ pdata->ext_pullup_enable_pin = w1_gpio_pullup_pin; -+ } -+ -+ dev_info(&pdev->dev, "gpio pin %d, external pullup pin %d, parasitic power %d\n", pdata->pin, pdata->ext_pullup_enable_pin, pdata->parasitic_power); -+ - err = devm_gpio_request(&pdev->dev, pdata->pin, "w1"); - if (err) { - dev_err(&pdev->dev, "gpio_request (pin) failed\n"); -@@ -165,6 +210,14 @@ - master->set_pullup = w1_gpio_set_pullup; - } - -+ if (pdata->parasitic_power) { -+ if (pdata->is_open_drain) -+ printk(KERN_ERR "w1-gpio 'pullup'(parasitic power) " -+ "option doesn't work with open drain GPIO\n"); -+ else -+ master->bitbang_pullup = w1_gpio_bitbang_pullup; -+ } -+ - err = w1_add_master_device(master); - if (err) { - dev_err(&pdev->dev, "w1_add_master device failed\n"); -@@ -195,6 +248,10 @@ - - w1_remove_master_device(master); - -+ pdata->pin = w1_gpio_pin_orig; -+ pdata->ext_pullup_enable_pin = w1_gpio_pullup_pin_orig; -+ pdata->parasitic_power = w1_gpio_pullup_orig; -+ - return 0; - } - -diff -Nur linux-4.1.13.orig/drivers/w1/slaves/w1_therm.c linux-rpi/drivers/w1/slaves/w1_therm.c ---- linux-4.1.13.orig/drivers/w1/slaves/w1_therm.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/w1/slaves/w1_therm.c 2015-11-29 09:42:40.139084077 +0100 -@@ -92,13 +92,24 @@ - static ssize_t w1_slave_show(struct device *device, - struct device_attribute *attr, char *buf); - -+static ssize_t w1_seq_show(struct device *device, -+ struct device_attribute *attr, char *buf); -+ - static DEVICE_ATTR_RO(w1_slave); -+static DEVICE_ATTR_RO(w1_seq); - - static struct attribute *w1_therm_attrs[] = { - &dev_attr_w1_slave.attr, - NULL, - }; -+ -+static struct attribute *w1_ds28ea00_attrs[] = { -+ &dev_attr_w1_slave.attr, -+ &dev_attr_w1_seq.attr, -+ NULL, -+}; - ATTRIBUTE_GROUPS(w1_therm); -+ATTRIBUTE_GROUPS(w1_ds28ea00); - - static struct w1_family_ops w1_therm_fops = { - .add_slave = w1_therm_add_slave, -@@ -106,6 +117,12 @@ - .groups = w1_therm_groups, - }; - -+static struct w1_family_ops w1_ds28ea00_fops = { -+ .add_slave = w1_therm_add_slave, -+ .remove_slave = w1_therm_remove_slave, -+ .groups = w1_ds28ea00_groups, -+}; -+ - static struct w1_family w1_therm_family_DS18S20 = { - .fid = W1_THERM_DS18S20, - .fops = &w1_therm_fops, -@@ -123,7 +140,7 @@ - - static struct w1_family w1_therm_family_DS28EA00 = { - .fid = W1_THERM_DS28EA00, -- .fops = &w1_therm_fops, -+ .fops = &w1_ds28ea00_fops, - }; - - static struct w1_family w1_therm_family_DS1825 = { -@@ -316,6 +333,89 @@ - return ret; - } - -+#define W1_42_CHAIN 0x99 -+#define W1_42_CHAIN_OFF 0x3C -+#define W1_42_CHAIN_OFF_INV 0xC3 -+#define W1_42_CHAIN_ON 0x5A -+#define W1_42_CHAIN_ON_INV 0xA5 -+#define W1_42_CHAIN_DONE 0x96 -+#define W1_42_CHAIN_DONE_INV 0x69 -+#define W1_42_COND_READ 0x0F -+#define W1_42_SUCCESS_CONFIRM_BYTE 0xAA -+#define W1_42_FINISHED_BYTE 0xFF -+static ssize_t w1_seq_show(struct device *device, -+ struct device_attribute *attr, char *buf) -+{ -+ struct w1_slave *sl = dev_to_w1_slave(device); -+ ssize_t c = PAGE_SIZE; -+ int rv; -+ int i; -+ u8 ack; -+ u64 rn; -+ struct w1_reg_num *reg_num; -+ int seq = 0; -+ -+ mutex_lock(&sl->master->bus_mutex); -+ /* Place all devices in CHAIN state */ -+ if (w1_reset_bus(sl->master)) -+ goto error; -+ w1_write_8(sl->master, W1_SKIP_ROM); -+ w1_write_8(sl->master, W1_42_CHAIN); -+ w1_write_8(sl->master, W1_42_CHAIN_ON); -+ w1_write_8(sl->master, W1_42_CHAIN_ON_INV); -+ msleep(sl->master->pullup_duration); -+ -+ /* check for acknowledgment */ -+ ack = w1_read_8(sl->master); -+ if (ack != W1_42_SUCCESS_CONFIRM_BYTE) -+ goto error; -+ -+ /* In case the bus fails to send 0xFF, limit*/ -+ for (i = 0; i <= 64; i++) { -+ if (w1_reset_bus(sl->master)) -+ goto error; -+ -+ w1_write_8(sl->master, W1_42_COND_READ); -+ rv = w1_read_block(sl->master, (u8 *)&rn, 8); -+ reg_num = (struct w1_reg_num *) &rn; -+ if (reg_num->family == W1_42_FINISHED_BYTE) -+ break; -+ if (sl->reg_num.id == reg_num->id) -+ seq = i; -+ -+ w1_write_8(sl->master, W1_42_CHAIN); -+ w1_write_8(sl->master, W1_42_CHAIN_DONE); -+ w1_write_8(sl->master, W1_42_CHAIN_DONE_INV); -+ w1_read_block(sl->master, &ack, sizeof(ack)); -+ -+ /* check for acknowledgment */ -+ ack = w1_read_8(sl->master); -+ if (ack != W1_42_SUCCESS_CONFIRM_BYTE) -+ goto error; -+ -+ } -+ -+ /* Exit from CHAIN state */ -+ if (w1_reset_bus(sl->master)) -+ goto error; -+ w1_write_8(sl->master, W1_SKIP_ROM); -+ w1_write_8(sl->master, W1_42_CHAIN); -+ w1_write_8(sl->master, W1_42_CHAIN_OFF); -+ w1_write_8(sl->master, W1_42_CHAIN_OFF_INV); -+ -+ /* check for acknowledgment */ -+ ack = w1_read_8(sl->master); -+ if (ack != W1_42_SUCCESS_CONFIRM_BYTE) -+ goto error; -+ mutex_unlock(&sl->master->bus_mutex); -+ -+ c -= snprintf(buf + PAGE_SIZE - c, c, "%d\n", seq); -+ return PAGE_SIZE - c; -+error: -+ mutex_unlock(&sl->master->bus_mutex); -+ return -EIO; -+} -+ - static int __init w1_therm_init(void) - { - int err, i; -diff -Nur linux-4.1.13.orig/drivers/w1/w1.h linux-rpi/drivers/w1/w1.h ---- linux-4.1.13.orig/drivers/w1/w1.h 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/w1/w1.h 2015-11-29 09:42:40.139084077 +0100 -@@ -171,6 +171,12 @@ - - u8 (*set_pullup)(void *, int); - -+ /** -+ * Turns the pullup on/off in bitbanging mode, takes an on/off argument. -+ * @return -1=Error, 0=completed -+ */ -+ void (*bitbang_pullup) (void *, u8); -+ - void (*search)(void *, struct w1_master *, - u8, w1_slave_found_callback); - }; -diff -Nur linux-4.1.13.orig/drivers/w1/w1_int.c linux-rpi/drivers/w1/w1_int.c ---- linux-4.1.13.orig/drivers/w1/w1_int.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/w1/w1_int.c 2015-11-29 09:42:40.139084077 +0100 -@@ -123,6 +123,20 @@ - return(-EINVAL); - } - -+ /* bitbanging hardware uses bitbang_pullup, other hardware uses set_pullup -+ * and takes care of timing itself */ -+ if (!master->write_byte && !master->touch_bit && master->set_pullup) { -+ printk(KERN_ERR "w1_add_master_device: set_pullup requires " -+ "write_byte or touch_bit, disabling\n"); -+ master->set_pullup = NULL; -+ } -+ -+ if (master->set_pullup && master->bitbang_pullup) { -+ printk(KERN_ERR "w1_add_master_device: set_pullup should not " -+ "be set when bitbang_pullup is used, disabling\n"); -+ master->set_pullup = NULL; -+ } -+ - /* Lock until the device is added (or not) to w1_masters. */ - mutex_lock(&w1_mlock); - /* Search for the first available id (starting at 1). */ -diff -Nur linux-4.1.13.orig/drivers/w1/w1_io.c linux-rpi/drivers/w1/w1_io.c ---- linux-4.1.13.orig/drivers/w1/w1_io.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/w1/w1_io.c 2015-11-29 09:42:40.139084077 +0100 -@@ -134,10 +134,22 @@ - static void w1_post_write(struct w1_master *dev) - { - if (dev->pullup_duration) { -- if (dev->enable_pullup && dev->bus_master->set_pullup) -- dev->bus_master->set_pullup(dev->bus_master->data, 0); -- else -+ if (dev->enable_pullup) { -+ if (dev->bus_master->set_pullup) { -+ dev->bus_master->set_pullup(dev-> -+ bus_master->data, -+ 0); -+ } else if (dev->bus_master->bitbang_pullup) { -+ dev->bus_master-> -+ bitbang_pullup(dev->bus_master->data, 1); - msleep(dev->pullup_duration); -+ dev->bus_master-> -+ bitbang_pullup(dev->bus_master->data, 0); -+ } -+ } else { -+ msleep(dev->pullup_duration); -+ } -+ - dev->pullup_duration = 0; - } - } -diff -Nur linux-4.1.13.orig/drivers/watchdog/bcm2708_wdog.c linux-rpi/drivers/watchdog/bcm2708_wdog.c ---- linux-4.1.13.orig/drivers/watchdog/bcm2708_wdog.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/drivers/watchdog/bcm2708_wdog.c 2015-11-29 09:42:40.139084077 +0100 -@@ -0,0 +1,382 @@ -+/* -+ * Broadcom BCM2708 watchdog driver. -+ * -+ * (c) Copyright 2010 Broadcom Europe Ltd -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ * -+ * BCM2708 watchdog driver. Loosely based on wdt driver. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define SECS_TO_WDOG_TICKS(x) ((x) << 16) -+#define WDOG_TICKS_TO_SECS(x) ((x) >> 16) -+ -+static unsigned long wdog_is_open; -+static uint32_t wdog_ticks; /* Ticks to load into wdog timer */ -+static char expect_close; -+ -+/* -+ * Module parameters -+ */ -+ -+#define WD_TIMO 10 /* Default heartbeat = 60 seconds */ -+static int heartbeat = WD_TIMO; /* Heartbeat in seconds */ -+ -+module_param(heartbeat, int, 0); -+MODULE_PARM_DESC(heartbeat, -+ "Watchdog heartbeat in seconds. (0 < heartbeat < 65536, default=" -+ __MODULE_STRING(WD_TIMO) ")"); -+ -+static int nowayout = WATCHDOG_NOWAYOUT; -+module_param(nowayout, int, 0); -+MODULE_PARM_DESC(nowayout, -+ "Watchdog cannot be stopped once started (default=" -+ __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); -+ -+static DEFINE_SPINLOCK(wdog_lock); -+ -+/** -+ * Start the watchdog driver. -+ */ -+ -+static int wdog_start(unsigned long timeout) -+{ -+ uint32_t cur; -+ unsigned long flags; -+ spin_lock_irqsave(&wdog_lock, flags); -+ -+ /* enable the watchdog */ -+ iowrite32(PM_PASSWORD | (timeout & PM_WDOG_TIME_SET), -+ __io_address(PM_WDOG)); -+ cur = ioread32(__io_address(PM_RSTC)); -+ iowrite32(PM_PASSWORD | (cur & PM_RSTC_WRCFG_CLR) | -+ PM_RSTC_WRCFG_FULL_RESET, __io_address(PM_RSTC)); -+ -+ spin_unlock_irqrestore(&wdog_lock, flags); -+ return 0; -+} -+ -+/** -+ * Stop the watchdog driver. -+ */ -+ -+static int wdog_stop(void) -+{ -+ iowrite32(PM_PASSWORD | PM_RSTC_RESET, __io_address(PM_RSTC)); -+ printk(KERN_INFO "watchdog stopped\n"); -+ return 0; -+} -+ -+/** -+ * Reload counter one with the watchdog heartbeat. We don't bother -+ * reloading the cascade counter. -+ */ -+ -+static void wdog_ping(void) -+{ -+ wdog_start(wdog_ticks); -+} -+ -+/** -+ * @t: the new heartbeat value that needs to be set. -+ * -+ * Set a new heartbeat value for the watchdog device. If the heartbeat -+ * value is incorrect we keep the old value and return -EINVAL. If -+ * successful we return 0. -+ */ -+ -+static int wdog_set_heartbeat(int t) -+{ -+ if (t < 1 || t > WDOG_TICKS_TO_SECS(PM_WDOG_TIME_SET)) -+ return -EINVAL; -+ -+ heartbeat = t; -+ wdog_ticks = SECS_TO_WDOG_TICKS(t); -+ return 0; -+} -+ -+/** -+ * @file: file handle to the watchdog -+ * @buf: buffer to write (unused as data does not matter here -+ * @count: count of bytes -+ * @ppos: pointer to the position to write. No seeks allowed -+ * -+ * A write to a watchdog device is defined as a keepalive signal. -+ * -+ * if 'nowayout' is set then normally a close() is ignored. But -+ * if you write 'V' first then the close() will stop the timer. -+ */ -+ -+static ssize_t wdog_write(struct file *file, const char __user *buf, -+ size_t count, loff_t *ppos) -+{ -+ if (count) { -+ if (!nowayout) { -+ size_t i; -+ -+ /* In case it was set long ago */ -+ expect_close = 0; -+ -+ for (i = 0; i != count; i++) { -+ char c; -+ if (get_user(c, buf + i)) -+ return -EFAULT; -+ if (c == 'V') -+ expect_close = 42; -+ } -+ } -+ wdog_ping(); -+ } -+ return count; -+} -+ -+static int wdog_get_status(void) -+{ -+ unsigned long flags; -+ int status = 0; -+ spin_lock_irqsave(&wdog_lock, flags); -+ /* FIXME: readback reset reason */ -+ spin_unlock_irqrestore(&wdog_lock, flags); -+ return status; -+} -+ -+static uint32_t wdog_get_remaining(void) -+{ -+ uint32_t ret = ioread32(__io_address(PM_WDOG)); -+ return ret & PM_WDOG_TIME_SET; -+} -+ -+/** -+ * @file: file handle to the device -+ * @cmd: watchdog command -+ * @arg: argument pointer -+ * -+ * The watchdog API defines a common set of functions for all watchdogs -+ * according to their available features. We only actually usefully support -+ * querying capabilities and current status. -+ */ -+ -+static long wdog_ioctl(struct file *file, unsigned int cmd, unsigned long arg) -+{ -+ void __user *argp = (void __user *)arg; -+ int __user *p = argp; -+ int new_heartbeat; -+ int status; -+ int options; -+ uint32_t remaining; -+ -+ struct watchdog_info ident = { -+ .options = WDIOF_SETTIMEOUT| -+ WDIOF_MAGICCLOSE| -+ WDIOF_KEEPALIVEPING, -+ .firmware_version = 1, -+ .identity = "BCM2708", -+ }; -+ -+ switch (cmd) { -+ case WDIOC_GETSUPPORT: -+ return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; -+ case WDIOC_GETSTATUS: -+ status = wdog_get_status(); -+ return put_user(status, p); -+ case WDIOC_GETBOOTSTATUS: -+ return put_user(0, p); -+ case WDIOC_KEEPALIVE: -+ wdog_ping(); -+ return 0; -+ case WDIOC_SETTIMEOUT: -+ if (get_user(new_heartbeat, p)) -+ return -EFAULT; -+ if (wdog_set_heartbeat(new_heartbeat)) -+ return -EINVAL; -+ wdog_ping(); -+ /* Fall */ -+ case WDIOC_GETTIMEOUT: -+ return put_user(heartbeat, p); -+ case WDIOC_GETTIMELEFT: -+ remaining = WDOG_TICKS_TO_SECS(wdog_get_remaining()); -+ return put_user(remaining, p); -+ case WDIOC_SETOPTIONS: -+ if (get_user(options, p)) -+ return -EFAULT; -+ if (options & WDIOS_DISABLECARD) -+ wdog_stop(); -+ if (options & WDIOS_ENABLECARD) -+ wdog_start(wdog_ticks); -+ return 0; -+ default: -+ return -ENOTTY; -+ } -+} -+ -+/** -+ * @inode: inode of device -+ * @file: file handle to device -+ * -+ * The watchdog device has been opened. The watchdog device is single -+ * open and on opening we load the counters. -+ */ -+ -+static int wdog_open(struct inode *inode, struct file *file) -+{ -+ if (test_and_set_bit(0, &wdog_is_open)) -+ return -EBUSY; -+ /* -+ * Activate -+ */ -+ wdog_start(wdog_ticks); -+ return nonseekable_open(inode, file); -+} -+ -+/** -+ * @inode: inode to board -+ * @file: file handle to board -+ * -+ * The watchdog has a configurable API. There is a religious dispute -+ * between people who want their watchdog to be able to shut down and -+ * those who want to be sure if the watchdog manager dies the machine -+ * reboots. In the former case we disable the counters, in the latter -+ * case you have to open it again very soon. -+ */ -+ -+static int wdog_release(struct inode *inode, struct file *file) -+{ -+ if (expect_close == 42) { -+ wdog_stop(); -+ } else { -+ printk(KERN_CRIT -+ "wdt: WDT device closed unexpectedly. WDT will not stop!\n"); -+ wdog_ping(); -+ } -+ clear_bit(0, &wdog_is_open); -+ expect_close = 0; -+ return 0; -+} -+ -+/** -+ * @this: our notifier block -+ * @code: the event being reported -+ * @unused: unused -+ * -+ * Our notifier is called on system shutdowns. Turn the watchdog -+ * off so that it does not fire during the next reboot. -+ */ -+ -+static int wdog_notify_sys(struct notifier_block *this, unsigned long code, -+ void *unused) -+{ -+ if (code == SYS_DOWN || code == SYS_HALT) -+ wdog_stop(); -+ return NOTIFY_DONE; -+} -+ -+/* -+ * Kernel Interfaces -+ */ -+ -+ -+static const struct file_operations wdog_fops = { -+ .owner = THIS_MODULE, -+ .llseek = no_llseek, -+ .write = wdog_write, -+ .unlocked_ioctl = wdog_ioctl, -+ .open = wdog_open, -+ .release = wdog_release, -+}; -+ -+static struct miscdevice wdog_miscdev = { -+ .minor = WATCHDOG_MINOR, -+ .name = "watchdog", -+ .fops = &wdog_fops, -+}; -+ -+/* -+ * The WDT card needs to learn about soft shutdowns in order to -+ * turn the timebomb registers off. -+ */ -+ -+static struct notifier_block wdog_notifier = { -+ .notifier_call = wdog_notify_sys, -+}; -+ -+/** -+ * cleanup_module: -+ * -+ * Unload the watchdog. You cannot do this with any file handles open. -+ * If your watchdog is set to continue ticking on close and you unload -+ * it, well it keeps ticking. We won't get the interrupt but the board -+ * will not touch PC memory so all is fine. You just have to load a new -+ * module in 60 seconds or reboot. -+ */ -+ -+static void __exit wdog_exit(void) -+{ -+ misc_deregister(&wdog_miscdev); -+ unregister_reboot_notifier(&wdog_notifier); -+} -+ -+static int __init wdog_init(void) -+{ -+ int ret; -+ -+ /* Check that the heartbeat value is within it's range; -+ if not reset to the default */ -+ if (wdog_set_heartbeat(heartbeat)) { -+ wdog_set_heartbeat(WD_TIMO); -+ printk(KERN_INFO "bcm2708_wdog: heartbeat value must be " -+ "0 < heartbeat < %d, using %d\n", -+ WDOG_TICKS_TO_SECS(PM_WDOG_TIME_SET), -+ WD_TIMO); -+ } -+ -+ ret = register_reboot_notifier(&wdog_notifier); -+ if (ret) { -+ printk(KERN_ERR -+ "wdt: cannot register reboot notifier (err=%d)\n", ret); -+ goto out_reboot; -+ } -+ -+ ret = misc_register(&wdog_miscdev); -+ if (ret) { -+ printk(KERN_ERR -+ "wdt: cannot register miscdev on minor=%d (err=%d)\n", -+ WATCHDOG_MINOR, ret); -+ goto out_misc; -+ } -+ -+ printk(KERN_INFO "bcm2708 watchdog, heartbeat=%d sec (nowayout=%d)\n", -+ heartbeat, nowayout); -+ return 0; -+ -+out_misc: -+ unregister_reboot_notifier(&wdog_notifier); -+out_reboot: -+ return ret; -+} -+ -+module_init(wdog_init); -+module_exit(wdog_exit); -+ -+MODULE_AUTHOR("Luke Diamand"); -+MODULE_DESCRIPTION("Driver for BCM2708 watchdog"); -+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); -+MODULE_ALIAS_MISCDEV(TEMP_MINOR); -+MODULE_LICENSE("GPL"); -diff -Nur linux-4.1.13.orig/drivers/watchdog/Kconfig linux-rpi/drivers/watchdog/Kconfig ---- linux-4.1.13.orig/drivers/watchdog/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/watchdog/Kconfig 2015-11-29 09:42:40.139084077 +0100 -@@ -451,6 +451,12 @@ - To compile this driver as a module, choose M here: the - module will be called retu_wdt. - -+config BCM2708_WDT -+ tristate "BCM2708 Watchdog" -+ depends on ARCH_BCM2708 || ARCH_BCM2709 -+ help -+ Enables BCM2708 watchdog support. -+ - config MOXART_WDT - tristate "MOXART watchdog" - depends on ARCH_MOXART -@@ -1216,7 +1222,7 @@ - - config BCM2835_WDT - tristate "Broadcom BCM2835 hardware watchdog" -- depends on ARCH_BCM2835 -+ depends on ARCH_BCM2835 || ARCH_BCM2708 || ARCH_BCM2709 - select WATCHDOG_CORE - help - Watchdog driver for the built in watchdog hardware in Broadcom -diff -Nur linux-4.1.13.orig/drivers/watchdog/Makefile linux-rpi/drivers/watchdog/Makefile ---- linux-4.1.13.orig/drivers/watchdog/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/drivers/watchdog/Makefile 2015-11-29 09:42:40.139084077 +0100 -@@ -56,6 +56,7 @@ - obj-$(CONFIG_IMX2_WDT) += imx2_wdt.o - obj-$(CONFIG_UX500_WATCHDOG) += ux500_wdt.o - obj-$(CONFIG_RETU_WATCHDOG) += retu_wdt.o -+obj-$(CONFIG_BCM2708_WDT) += bcm2708_wdog.o - obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o - obj-$(CONFIG_MOXART_WDT) += moxart_wdt.o - obj-$(CONFIG_SIRFSOC_WATCHDOG) += sirfsoc_wdt.o -diff -Nur linux-4.1.13.orig/include/linux/broadcom/bcm2835_smi.h linux-rpi/include/linux/broadcom/bcm2835_smi.h ---- linux-4.1.13.orig/include/linux/broadcom/bcm2835_smi.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/include/linux/broadcom/bcm2835_smi.h 2015-11-29 09:42:40.679048199 +0100 -@@ -0,0 +1,391 @@ -+/** -+ * Declarations and definitions for Broadcom's Secondary Memory Interface -+ * -+ * Written by Luke Wren -+ * Copyright (c) 2015, Raspberry Pi (Trading) Ltd. -+ * Copyright (c) 2010-2012 Broadcom. All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#ifndef BCM2835_SMI_H -+#define BCM2835_SMI_H -+ -+#include -+ -+#ifndef __KERNEL__ -+#include -+#include -+#endif -+ -+#define BCM2835_SMI_IOC_MAGIC 0x1 -+#define BCM2835_SMI_INVALID_HANDLE (~0) -+ -+/* IOCTLs 0x100...0x1ff are not device-specific - we can use them */ -+#define BCM2835_SMI_IOC_GET_SETTINGS _IO(BCM2835_SMI_IOC_MAGIC, 0) -+#define BCM2835_SMI_IOC_WRITE_SETTINGS _IO(BCM2835_SMI_IOC_MAGIC, 1) -+#define BCM2835_SMI_IOC_ADDRESS _IO(BCM2835_SMI_IOC_MAGIC, 2) -+#define BCM2835_SMI_IOC_MAX 2 -+ -+#define SMI_WIDTH_8BIT 0 -+#define SMI_WIDTH_16BIT 1 -+#define SMI_WIDTH_9BIT 2 -+#define SMI_WIDTH_18BIT 3 -+ -+/* max number of bytes where DMA will not be used */ -+#define DMA_THRESHOLD_BYTES 128 -+#define DMA_BOUNCE_BUFFER_SIZE (1024 * 1024 / 2) -+#define DMA_BOUNCE_BUFFER_COUNT 3 -+ -+ -+struct smi_settings { -+ int data_width; -+ /* Whether or not to pack multiple SMI transfers into a -+ single 32 bit FIFO word */ -+ bool pack_data; -+ -+ /* Timing for reads (writes the same but for WE) -+ * -+ * OE ----------+ +-------------------- -+ * | | -+ * +----------+ -+ * SD -<==============================>----------- -+ * SA -<=========================================>- -+ * <-setup-> <-strobe -> <-hold -> <- pace -> -+ */ -+ -+ int read_setup_time; -+ int read_hold_time; -+ int read_pace_time; -+ int read_strobe_time; -+ -+ int write_setup_time; -+ int write_hold_time; -+ int write_pace_time; -+ int write_strobe_time; -+ -+ bool dma_enable; /* DREQs */ -+ bool dma_passthrough_enable; /* External DREQs */ -+ int dma_read_thresh; -+ int dma_write_thresh; -+ int dma_panic_read_thresh; -+ int dma_panic_write_thresh; -+}; -+ -+/**************************************************************************** -+* -+* Declare exported SMI functions -+* -+***************************************************************************/ -+ -+#ifdef __KERNEL__ -+ -+#include /* for enum dma_transfer_direction */ -+#include -+#include -+ -+struct bcm2835_smi_instance; -+ -+struct bcm2835_smi_bounce_info { -+ struct semaphore callback_sem; -+ void *buffer[DMA_BOUNCE_BUFFER_COUNT]; -+ dma_addr_t phys[DMA_BOUNCE_BUFFER_COUNT]; -+ struct scatterlist sgl[DMA_BOUNCE_BUFFER_COUNT]; -+}; -+ -+ -+void bcm2835_smi_set_regs_from_settings(struct bcm2835_smi_instance *); -+ -+struct smi_settings *bcm2835_smi_get_settings_from_regs( -+ struct bcm2835_smi_instance *inst); -+ -+void bcm2835_smi_write_buf( -+ struct bcm2835_smi_instance *inst, -+ const void *buf, -+ size_t n_bytes); -+ -+void bcm2835_smi_read_buf( -+ struct bcm2835_smi_instance *inst, -+ void *buf, -+ size_t n_bytes); -+ -+void bcm2835_smi_set_address(struct bcm2835_smi_instance *inst, -+ unsigned int address); -+ -+ssize_t bcm2835_smi_user_dma( -+ struct bcm2835_smi_instance *inst, -+ enum dma_transfer_direction dma_dir, -+ char __user *user_ptr, -+ size_t count, -+ struct bcm2835_smi_bounce_info **bounce); -+ -+struct bcm2835_smi_instance *bcm2835_smi_get(struct device_node *node); -+ -+#endif /* __KERNEL__ */ -+ -+/**************************************************************** -+* -+* Implementation-only declarations -+* -+****************************************************************/ -+ -+#ifdef BCM2835_SMI_IMPLEMENTATION -+ -+/* Clock manager registers for SMI clock: */ -+#define CM_SMI_BASE_ADDRESS ((BCM2708_PERI_BASE) + 0x1010b0) -+/* Clock manager "password" to protect registers from spurious writes */ -+#define CM_PWD (0x5a << 24) -+ -+#define CM_SMI_CTL 0x00 -+#define CM_SMI_DIV 0x04 -+ -+#define CM_SMI_CTL_FLIP (1 << 8) -+#define CM_SMI_CTL_BUSY (1 << 7) -+#define CM_SMI_CTL_KILL (1 << 5) -+#define CM_SMI_CTL_ENAB (1 << 4) -+#define CM_SMI_CTL_SRC_MASK (0xf) -+#define CM_SMI_CTL_SRC_OFFS (0) -+ -+#define CM_SMI_DIV_DIVI_MASK (0xf << 12) -+#define CM_SMI_DIV_DIVI_OFFS (12) -+#define CM_SMI_DIV_DIVF_MASK (0xff << 4) -+#define CM_SMI_DIV_DIVF_OFFS (4) -+ -+/* SMI register mapping:*/ -+#define SMI_BASE_ADDRESS ((BCM2708_PERI_BASE) + 0x600000) -+ -+#define SMICS 0x00 /* control + status register */ -+#define SMIL 0x04 /* length/count (n external txfers) */ -+#define SMIA 0x08 /* address register */ -+#define SMID 0x0c /* data register */ -+#define SMIDSR0 0x10 /* device 0 read settings */ -+#define SMIDSW0 0x14 /* device 0 write settings */ -+#define SMIDSR1 0x18 /* device 1 read settings */ -+#define SMIDSW1 0x1c /* device 1 write settings */ -+#define SMIDSR2 0x20 /* device 2 read settings */ -+#define SMIDSW2 0x24 /* device 2 write settings */ -+#define SMIDSR3 0x28 /* device 3 read settings */ -+#define SMIDSW3 0x2c /* device 3 write settings */ -+#define SMIDC 0x30 /* DMA control registers */ -+#define SMIDCS 0x34 /* direct control/status register */ -+#define SMIDA 0x38 /* direct address register */ -+#define SMIDD 0x3c /* direct data registers */ -+#define SMIFD 0x40 /* FIFO debug register */ -+ -+ -+ -+/* Control and Status register bits: -+ * SMICS_RXF : RX fifo full: 1 when RX fifo is full -+ * SMICS_TXE : TX fifo empty: 1 when empty. -+ * SMICS_RXD : RX fifo contains data: 1 when there is data. -+ * SMICS_TXD : TX fifo can accept data: 1 when true. -+ * SMICS_RXR : RX fifo needs reading: 1 when fifo more than 3/4 full, or -+ * when "DONE" and fifo not emptied. -+ * SMICS_TXW : TX fifo needs writing: 1 when less than 1/4 full. -+ * SMICS_AFERR : AXI FIFO error: 1 when fifo read when empty or written -+ * when full. Write 1 to clear. -+ * SMICS_EDREQ : 1 when external DREQ received. -+ * SMICS_PXLDAT : Pixel data: write 1 to enable pixel transfer modes. -+ * SMICS_SETERR : 1 if there was an error writing to setup regs (e.g. -+ * tx was in progress). Write 1 to clear. -+ * SMICS_PVMODE : Set to 1 to enable pixel valve mode. -+ * SMICS_INTR : Set to 1 to enable interrupt on RX. -+ * SMICS_INTT : Set to 1 to enable interrupt on TX. -+ * SMICS_INTD : Set to 1 to enable interrupt on DONE condition. -+ * SMICS_TEEN : Tear effect mode enabled: Programmed transfers will wait -+ * for a TE trigger before writing. -+ * SMICS_PAD1 : Padding settings for external transfers. For writes: the -+ * number of bytes initially written to the TX fifo that -+ * SMICS_PAD0 : should be ignored. For reads: the number of bytes that will -+ * be read before the data, and should be dropped. -+ * SMICS_WRITE : Transfer direction: 1 = write to external device, 0 = read -+ * SMICS_CLEAR : Write 1 to clear the FIFOs. -+ * SMICS_START : Write 1 to start the programmed transfer. -+ * SMICS_ACTIVE : Reads as 1 when a programmed transfer is underway. -+ * SMICS_DONE : Reads as 1 when transfer finished. For RX, not set until -+ * FIFO emptied. -+ * SMICS_ENABLE : Set to 1 to enable the SMI peripheral, 0 to disable. -+ */ -+ -+#define SMICS_RXF (1 << 31) -+#define SMICS_TXE (1 << 30) -+#define SMICS_RXD (1 << 29) -+#define SMICS_TXD (1 << 28) -+#define SMICS_RXR (1 << 27) -+#define SMICS_TXW (1 << 26) -+#define SMICS_AFERR (1 << 25) -+#define SMICS_EDREQ (1 << 15) -+#define SMICS_PXLDAT (1 << 14) -+#define SMICS_SETERR (1 << 13) -+#define SMICS_PVMODE (1 << 12) -+#define SMICS_INTR (1 << 11) -+#define SMICS_INTT (1 << 10) -+#define SMICS_INTD (1 << 9) -+#define SMICS_TEEN (1 << 8) -+#define SMICS_PAD1 (1 << 7) -+#define SMICS_PAD0 (1 << 6) -+#define SMICS_WRITE (1 << 5) -+#define SMICS_CLEAR (1 << 4) -+#define SMICS_START (1 << 3) -+#define SMICS_ACTIVE (1 << 2) -+#define SMICS_DONE (1 << 1) -+#define SMICS_ENABLE (1 << 0) -+ -+/* Address register bits: */ -+ -+#define SMIA_DEVICE_MASK ((1 << 9) | (1 << 8)) -+#define SMIA_DEVICE_OFFS (8) -+#define SMIA_ADDR_MASK (0x3f) /* bits 5 -> 0 */ -+#define SMIA_ADDR_OFFS (0) -+ -+/* DMA control register bits: -+ * SMIDC_DMAEN : DMA enable: set 1: DMA requests will be issued. -+ * SMIDC_DMAP : DMA passthrough: when set to 0, top two data pins are used by -+ * SMI as usual. When set to 1, the top two pins are used for -+ * external DREQs: pin 16 read request, 17 write. -+ * SMIDC_PANIC* : Threshold at which DMA will panic during read/write. -+ * SMIDC_REQ* : Threshold at which DMA will generate a DREQ. -+ */ -+ -+#define SMIDC_DMAEN (1 << 28) -+#define SMIDC_DMAP (1 << 24) -+#define SMIDC_PANICR_MASK (0x3f << 18) -+#define SMIDC_PANICR_OFFS (18) -+#define SMIDC_PANICW_MASK (0x3f << 12) -+#define SMIDC_PANICW_OFFS (12) -+#define SMIDC_REQR_MASK (0x3f << 6) -+#define SMIDC_REQR_OFFS (6) -+#define SMIDC_REQW_MASK (0x3f) -+#define SMIDC_REQW_OFFS (0) -+ -+/* Device settings register bits: same for all 4 (or 3?) device register sets. -+ * Device read settings: -+ * SMIDSR_RWIDTH : Read transfer width. 00 = 8bit, 01 = 16bit, -+ * 10 = 18bit, 11 = 9bit. -+ * SMIDSR_RSETUP : Read setup time: number of core cycles between chip -+ * select/address and read strobe. Min 1, max 64. -+ * SMIDSR_MODE68 : 1 for System 68 mode (i.e. enable + direction pins, -+ * rather than OE + WE pin) -+ * SMIDSR_FSETUP : If set to 1, setup time only applies to first -+ * transfer after address change. -+ * SMIDSR_RHOLD : Number of core cycles between read strobe going -+ * inactive and CS/address going inactive. Min 1, max 64 -+ * SMIDSR_RPACEALL : When set to 1, this device's RPACE value will always -+ * be used for the next transaction, even if it is not -+ * to this device. -+ * SMIDSR_RPACE : Number of core cycles spent waiting between CS -+ * deassert and start of next transfer. Min 1, max 128 -+ * SMIDSR_RDREQ : 1 = use external DMA request on SD16 to pace reads -+ * from device. Must also set DMAP in SMICS. -+ * SMIDSR_RSTROBE : Number of cycles to assert the read strobe. -+ * min 1, max 128. -+ */ -+#define SMIDSR_RWIDTH_MASK ((1<<31)|(1<<30)) -+#define SMIDSR_RWIDTH_OFFS (30) -+#define SMIDSR_RSETUP_MASK (0x3f << 24) -+#define SMIDSR_RSETUP_OFFS (24) -+#define SMIDSR_MODE68 (1 << 23) -+#define SMIDSR_FSETUP (1 << 22) -+#define SMIDSR_RHOLD_MASK (0x3f << 16) -+#define SMIDSR_RHOLD_OFFS (16) -+#define SMIDSR_RPACEALL (1 << 15) -+#define SMIDSR_RPACE_MASK (0x7f << 8) -+#define SMIDSR_RPACE_OFFS (8) -+#define SMIDSR_RDREQ (1 << 7) -+#define SMIDSR_RSTROBE_MASK (0x7f) -+#define SMIDSR_RSTROBE_OFFS (0) -+ -+/* Device write settings: -+ * SMIDSW_WWIDTH : Write transfer width. 00 = 8bit, 01 = 16bit, -+ * 10= 18bit, 11 = 9bit. -+ * SMIDSW_WSETUP : Number of cycles between CS assert and write strobe. -+ * Min 1, max 64. -+ * SMIDSW_WFORMAT : Pixel format of input. 0 = 16bit RGB 565, -+ * 1 = 32bit RGBA 8888 -+ * SMIDSW_WSWAP : 1 = swap pixel data bits. (Use with SMICS_PXLDAT) -+ * SMIDSW_WHOLD : Time between WE deassert and CS deassert. 1 to 64 -+ * SMIDSW_WPACEALL : 1: this device's WPACE will be used for the next -+ * transfer, regardless of that transfer's device. -+ * SMIDSW_WPACE : Cycles between CS deassert and next CS assert. -+ * Min 1, max 128 -+ * SMIDSW_WDREQ : Use external DREQ on pin 17 to pace writes. DMAP must -+ * be set in SMICS. -+ * SMIDSW_WSTROBE : Number of cycles to assert the write strobe. -+ * Min 1, max 128 -+ */ -+#define SMIDSW_WWIDTH_MASK ((1<<31)|(1<<30)) -+#define SMIDSW_WWIDTH_OFFS (30) -+#define SMIDSW_WSETUP_MASK (0x3f << 24) -+#define SMIDSW_WSETUP_OFFS (24) -+#define SMIDSW_WFORMAT (1 << 23) -+#define SMIDSW_WSWAP (1 << 22) -+#define SMIDSW_WHOLD_MASK (0x3f << 16) -+#define SMIDSW_WHOLD_OFFS (16) -+#define SMIDSW_WPACEALL (1 << 15) -+#define SMIDSW_WPACE_MASK (0x7f << 8) -+#define SMIDSW_WPACE_OFFS (8) -+#define SMIDSW_WDREQ (1 << 7) -+#define SMIDSW_WSTROBE_MASK (0x7f) -+#define SMIDSW_WSTROBE_OFFS (0) -+ -+/* Direct transfer control + status register -+ * SMIDCS_WRITE : Direction of transfer: 1 -> write, 0 -> read -+ * SMIDCS_DONE : 1 when a transfer has finished. Write 1 to clear. -+ * SMIDCS_START : Write 1 to start a transfer, if one is not already underway. -+ * SMIDCE_ENABLE: Write 1 to enable SMI in direct mode. -+ */ -+ -+#define SMIDCS_WRITE (1 << 3) -+#define SMIDCS_DONE (1 << 2) -+#define SMIDCS_START (1 << 1) -+#define SMIDCS_ENABLE (1 << 0) -+ -+/* Direct transfer address register -+ * SMIDA_DEVICE : Indicates which of the device settings banks should be used. -+ * SMIDA_ADDR : The value to be asserted on the address pins. -+ */ -+ -+#define SMIDA_DEVICE_MASK ((1<<9)|(1<<8)) -+#define SMIDA_DEVICE_OFFS (8) -+#define SMIDA_ADDR_MASK (0x3f) -+#define SMIDA_ADDR_OFFS (0) -+ -+/* FIFO debug register -+ * SMIFD_FLVL : The high-tide mark of FIFO count during the most recent txfer -+ * SMIFD_FCNT : The current FIFO count. -+ */ -+#define SMIFD_FLVL_MASK (0x3f << 8) -+#define SMIFD_FLVL_OFFS (8) -+#define SMIFD_FCNT_MASK (0x3f) -+#define SMIFD_FCNT_OFFS (0) -+ -+#endif /* BCM2835_SMI_IMPLEMENTATION */ -+ -+#endif /* BCM2835_SMI_H */ -diff -Nur linux-4.1.13.orig/include/linux/broadcom/vc_cma.h linux-rpi/include/linux/broadcom/vc_cma.h ---- linux-4.1.13.orig/include/linux/broadcom/vc_cma.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/include/linux/broadcom/vc_cma.h 2015-11-29 09:42:40.679048199 +0100 -@@ -0,0 +1,29 @@ -+/***************************************************************************** -+* Copyright 2012 Broadcom Corporation. All rights reserved. -+* -+* Unless you and Broadcom execute a separate written software license -+* agreement governing use of this software, this software is licensed to you -+* under the terms of the GNU General Public License version 2, available at -+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -+* -+* Notwithstanding the above, under no circumstances may you combine this -+* software in any way with any other Broadcom software provided under a -+* license other than the GPL, without Broadcom's express prior written -+* consent. -+*****************************************************************************/ -+ -+#if !defined( VC_CMA_H ) -+#define VC_CMA_H -+ -+#include -+ -+#define VC_CMA_IOC_MAGIC 0xc5 -+ -+#define VC_CMA_IOC_RESERVE _IO(VC_CMA_IOC_MAGIC, 0) -+ -+#ifdef __KERNEL__ -+extern void __init vc_cma_early_init(void); -+extern void __init vc_cma_reserve(void); -+#endif -+ -+#endif /* VC_CMA_H */ -diff -Nur linux-4.1.13.orig/include/linux/broadcom/vc_mem.h linux-rpi/include/linux/broadcom/vc_mem.h ---- linux-4.1.13.orig/include/linux/broadcom/vc_mem.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/include/linux/broadcom/vc_mem.h 2015-11-29 09:42:40.679048199 +0100 -@@ -0,0 +1,35 @@ -+/***************************************************************************** -+* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved. -+* -+* Unless you and Broadcom execute a separate written software license -+* agreement governing use of this software, this software is licensed to you -+* under the terms of the GNU General Public License version 2, available at -+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -+* -+* Notwithstanding the above, under no circumstances may you combine this -+* software in any way with any other Broadcom software provided under a -+* license other than the GPL, without Broadcom's express prior written -+* consent. -+*****************************************************************************/ -+ -+#ifndef _VC_MEM_H -+#define _VC_MEM_H -+ -+#include -+ -+#define VC_MEM_IOC_MAGIC 'v' -+ -+#define VC_MEM_IOC_MEM_PHYS_ADDR _IOR( VC_MEM_IOC_MAGIC, 0, unsigned long ) -+#define VC_MEM_IOC_MEM_SIZE _IOR( VC_MEM_IOC_MAGIC, 1, unsigned int ) -+#define VC_MEM_IOC_MEM_BASE _IOR( VC_MEM_IOC_MAGIC, 2, unsigned int ) -+#define VC_MEM_IOC_MEM_LOAD _IOR( VC_MEM_IOC_MAGIC, 3, unsigned int ) -+ -+#if defined( __KERNEL__ ) -+#define VC_MEM_TO_ARM_ADDR_MASK 0x3FFFFFFF -+ -+extern unsigned long mm_vc_mem_phys_addr; -+extern unsigned int mm_vc_mem_size; -+extern int vc_mem_get_current_size( void ); -+#endif -+ -+#endif /* _VC_MEM_H */ -diff -Nur linux-4.1.13.orig/include/linux/leds.h linux-rpi/include/linux/leds.h ---- linux-4.1.13.orig/include/linux/leds.h 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/include/linux/leds.h 2015-11-29 09:42:40.723045276 +0100 -@@ -47,6 +47,9 @@ - #define SET_BRIGHTNESS_ASYNC (1 << 21) - #define SET_BRIGHTNESS_SYNC (1 << 22) - #define LED_DEV_CAP_FLASH (1 << 23) -+ /* Additions for Raspberry Pi PWR LED */ -+#define SET_GPIO_INPUT (1 << 30) -+#define SET_GPIO_OUTPUT (1 << 31) - - /* Set LED brightness level */ - /* Must not sleep, use a workqueue if needed */ -diff -Nur linux-4.1.13.orig/include/linux/mfd/rpisense/core.h linux-rpi/include/linux/mfd/rpisense/core.h ---- linux-4.1.13.orig/include/linux/mfd/rpisense/core.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/include/linux/mfd/rpisense/core.h 2015-11-29 09:42:40.747043681 +0100 -@@ -0,0 +1,47 @@ -+/* -+ * Raspberry Pi Sense HAT core driver -+ * http://raspberrypi.org -+ * -+ * Copyright (C) 2015 Raspberry Pi -+ * -+ * Author: Serge Schneider -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ */ -+ -+#ifndef __LINUX_MFD_RPISENSE_CORE_H_ -+#define __LINUX_MFD_RPISENSE_CORE_H_ -+ -+#include -+#include -+ -+/* -+ * Register values. -+ */ -+#define RPISENSE_FB 0x00 -+#define RPISENSE_WAI 0xF0 -+#define RPISENSE_VER 0xF1 -+#define RPISENSE_KEYS 0xF2 -+#define RPISENSE_EE_WP 0xF3 -+ -+#define RPISENSE_ID 's' -+ -+struct rpisense { -+ struct device *dev; -+ struct i2c_client *i2c_client; -+ -+ /* Client devices */ -+ struct rpisense_js joystick; -+ struct rpisense_fb framebuffer; -+}; -+ -+struct rpisense *rpisense_get_dev(void); -+s32 rpisense_reg_read(struct rpisense *rpisense, int reg); -+int rpisense_reg_write(struct rpisense *rpisense, int reg, u16 val); -+int rpisense_block_write(struct rpisense *rpisense, const char *buf, int count); -+ -+#endif -diff -Nur linux-4.1.13.orig/include/linux/mfd/rpisense/framebuffer.h linux-rpi/include/linux/mfd/rpisense/framebuffer.h ---- linux-4.1.13.orig/include/linux/mfd/rpisense/framebuffer.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/include/linux/mfd/rpisense/framebuffer.h 2015-11-29 09:42:40.747043681 +0100 -@@ -0,0 +1,32 @@ -+/* -+ * Raspberry Pi Sense HAT framebuffer driver -+ * http://raspberrypi.org -+ * -+ * Copyright (C) 2015 Raspberry Pi -+ * -+ * Author: Serge Schneider -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ */ -+ -+#ifndef __LINUX_RPISENSE_FB_H_ -+#define __LINUX_RPISENSE_FB_H_ -+ -+#define SENSEFB_FBIO_IOC_MAGIC 0xF1 -+ -+#define SENSEFB_FBIOGET_GAMMA _IO(SENSEFB_FBIO_IOC_MAGIC, 0) -+#define SENSEFB_FBIOSET_GAMMA _IO(SENSEFB_FBIO_IOC_MAGIC, 1) -+#define SENSEFB_FBIORESET_GAMMA _IO(SENSEFB_FBIO_IOC_MAGIC, 2) -+ -+struct rpisense; -+ -+struct rpisense_fb { -+ struct platform_device *pdev; -+ struct fb_info *info; -+}; -+ -+#endif -diff -Nur linux-4.1.13.orig/include/linux/mfd/rpisense/joystick.h linux-rpi/include/linux/mfd/rpisense/joystick.h ---- linux-4.1.13.orig/include/linux/mfd/rpisense/joystick.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/include/linux/mfd/rpisense/joystick.h 2015-11-29 09:42:40.747043681 +0100 -@@ -0,0 +1,35 @@ -+/* -+ * Raspberry Pi Sense HAT joystick driver -+ * http://raspberrypi.org -+ * -+ * Copyright (C) 2015 Raspberry Pi -+ * -+ * Author: Serge Schneider -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ */ -+ -+#ifndef __LINUX_RPISENSE_JOYSTICK_H_ -+#define __LINUX_RPISENSE_JOYSTICK_H_ -+ -+#include -+#include -+#include -+#include -+ -+struct rpisense; -+ -+struct rpisense_js { -+ struct platform_device *pdev; -+ struct input_dev *keys_dev; -+ struct gpio_desc *keys_desc; -+ struct work_struct keys_work_s; -+ int keys_irq; -+}; -+ -+ -+#endif -diff -Nur linux-4.1.13.orig/include/linux/mmc/host.h linux-rpi/include/linux/mmc/host.h ---- linux-4.1.13.orig/include/linux/mmc/host.h 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/include/linux/mmc/host.h 2015-11-29 09:42:40.759042884 +0100 -@@ -140,7 +140,9 @@ - * I/O. Returns the number of supported blocks for the request. - */ - int (*multi_io_quirk)(struct mmc_card *card, -- unsigned int direction, int blk_size); -+ unsigned int direction, -+ u32 blk_pos, -+ int blk_size); - }; - - struct mmc_card; -@@ -285,6 +287,7 @@ - MMC_CAP2_HS400_1_2V) - #define MMC_CAP2_HSX00_1_2V (MMC_CAP2_HS200_1_2V_SDR | MMC_CAP2_HS400_1_2V) - #define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17) -+#define MMC_CAP2_FORCE_MULTIBLOCK (1 << 31) /* Always use multiblock transfers */ - - mmc_pm_flag_t pm_caps; /* supported pm features */ - -diff -Nur linux-4.1.13.orig/include/linux/platform_data/bcm2708.h linux-rpi/include/linux/platform_data/bcm2708.h ---- linux-4.1.13.orig/include/linux/platform_data/bcm2708.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/include/linux/platform_data/bcm2708.h 2015-11-29 09:42:40.779041555 +0100 -@@ -0,0 +1,23 @@ -+/* -+ * include/linux/platform_data/bcm2708.h -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * (C) 2014 Julian Scheel -+ * -+ */ -+#ifndef __BCM2708_H_ -+#define __BCM2708_H_ -+ -+typedef enum { -+ BCM2708_PULL_OFF, -+ BCM2708_PULL_UP, -+ BCM2708_PULL_DOWN -+} bcm2708_gpio_pull_t; -+ -+extern int bcm2708_gpio_setpull(struct gpio_chip *gc, unsigned offset, -+ bcm2708_gpio_pull_t value); -+ -+#endif -diff -Nur linux-4.1.13.orig/include/linux/platform_data/dma-bcm2708.h linux-rpi/include/linux/platform_data/dma-bcm2708.h ---- linux-4.1.13.orig/include/linux/platform_data/dma-bcm2708.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/include/linux/platform_data/dma-bcm2708.h 2015-11-29 09:42:40.779041555 +0100 -@@ -0,0 +1,127 @@ -+/* -+ * Copyright (C) 2010 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#ifndef _PLAT_BCM2708_DMA_H -+#define _PLAT_BCM2708_DMA_H -+ -+/* DMA CS Control and Status bits */ -+#define BCM2708_DMA_ACTIVE BIT(0) -+#define BCM2708_DMA_INT BIT(2) -+#define BCM2708_DMA_ISPAUSED BIT(4) /* Pause requested or not active */ -+#define BCM2708_DMA_ISHELD BIT(5) /* Is held by DREQ flow control */ -+#define BCM2708_DMA_ERR BIT(8) -+#define BCM2708_DMA_ABORT BIT(30) /* stop current CB, go to next, WO */ -+#define BCM2708_DMA_RESET BIT(31) /* WO, self clearing */ -+ -+/* DMA control block "info" field bits */ -+#define BCM2708_DMA_INT_EN BIT(0) -+#define BCM2708_DMA_TDMODE BIT(1) -+#define BCM2708_DMA_WAIT_RESP BIT(3) -+#define BCM2708_DMA_D_INC BIT(4) -+#define BCM2708_DMA_D_WIDTH BIT(5) -+#define BCM2708_DMA_D_DREQ BIT(6) -+#define BCM2708_DMA_S_INC BIT(8) -+#define BCM2708_DMA_S_WIDTH BIT(9) -+#define BCM2708_DMA_S_DREQ BIT(10) -+ -+#define BCM2708_DMA_BURST(x) (((x) & 0xf) << 12) -+#define BCM2708_DMA_PER_MAP(x) ((x) << 16) -+#define BCM2708_DMA_WAITS(x) (((x) & 0x1f) << 21) -+ -+#define BCM2708_DMA_DREQ_EMMC 11 -+#define BCM2708_DMA_DREQ_SDHOST 13 -+ -+#define BCM2708_DMA_CS 0x00 /* Control and Status */ -+#define BCM2708_DMA_ADDR 0x04 -+/* the current control block appears in the following registers - read only */ -+#define BCM2708_DMA_INFO 0x08 -+#define BCM2708_DMA_SOURCE_AD 0x0c -+#define BCM2708_DMA_DEST_AD 0x10 -+#define BCM2708_DMA_NEXTCB 0x1C -+#define BCM2708_DMA_DEBUG 0x20 -+ -+#define BCM2708_DMA4_CS (BCM2708_DMA_CHAN(4) + BCM2708_DMA_CS) -+#define BCM2708_DMA4_ADDR (BCM2708_DMA_CHAN(4) + BCM2708_DMA_ADDR) -+ -+#define BCM2708_DMA_TDMODE_LEN(w, h) ((h) << 16 | (w)) -+ -+/* When listing features we can ask for when allocating DMA channels give -+ those with higher priority smaller ordinal numbers */ -+#define BCM_DMA_FEATURE_FAST_ORD 0 -+#define BCM_DMA_FEATURE_BULK_ORD 1 -+#define BCM_DMA_FEATURE_NORMAL_ORD 2 -+#define BCM_DMA_FEATURE_LITE_ORD 3 -+#define BCM_DMA_FEATURE_FAST BIT(BCM_DMA_FEATURE_FAST_ORD) -+#define BCM_DMA_FEATURE_BULK BIT(BCM_DMA_FEATURE_BULK_ORD) -+#define BCM_DMA_FEATURE_NORMAL BIT(BCM_DMA_FEATURE_NORMAL_ORD) -+#define BCM_DMA_FEATURE_LITE BIT(BCM_DMA_FEATURE_LITE_ORD) -+#define BCM_DMA_FEATURE_COUNT 4 -+ -+struct bcm2708_dma_cb { -+ unsigned long info; -+ unsigned long src; -+ unsigned long dst; -+ unsigned long length; -+ unsigned long stride; -+ unsigned long next; -+ unsigned long pad[2]; -+}; -+ -+struct scatterlist; -+ -+#ifdef CONFIG_DMA_BCM2708_LEGACY -+ -+int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len); -+void bcm_dma_start(void __iomem *dma_chan_base, dma_addr_t control_block); -+void bcm_dma_wait_idle(void __iomem *dma_chan_base); -+bool bcm_dma_is_busy(void __iomem *dma_chan_base); -+int bcm_dma_abort(void __iomem *dma_chan_base); -+ -+/* return channel no or -ve error */ -+int bcm_dma_chan_alloc(unsigned preferred_feature_set, -+ void __iomem **out_dma_base, int *out_dma_irq); -+int bcm_dma_chan_free(int channel); -+ -+#else /* CONFIG_DMA_BCM2708_LEGACY */ -+ -+static inline int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, -+ int sg_len) -+{ -+ return 0; -+} -+ -+static inline void bcm_dma_start(void __iomem *dma_chan_base, -+ dma_addr_t control_block) { } -+ -+static inline void bcm_dma_wait_idle(void __iomem *dma_chan_base) { } -+ -+static inline bool bcm_dma_is_busy(void __iomem *dma_chan_base) -+{ -+ return false; -+} -+ -+static inline int bcm_dma_abort(void __iomem *dma_chan_base) -+{ -+ return -EINVAL; -+} -+ -+static inline int bcm_dma_chan_alloc(unsigned preferred_feature_set, -+ void __iomem **out_dma_base, -+ int *out_dma_irq) -+{ -+ return -EINVAL; -+} -+ -+static inline int bcm_dma_chan_free(int channel) -+{ -+ return -EINVAL; -+} -+ -+#endif /* CONFIG_DMA_BCM2708_LEGACY */ -+ -+#endif /* _PLAT_BCM2708_DMA_H */ -diff -Nur linux-4.1.13.orig/include/linux/vmstat.h linux-rpi/include/linux/vmstat.h ---- linux-4.1.13.orig/include/linux/vmstat.h 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/include/linux/vmstat.h 2015-11-29 09:42:40.827038366 +0100 -@@ -241,7 +241,11 @@ - static inline void __dec_zone_state(struct zone *zone, enum zone_stat_item item) - { - atomic_long_dec(&zone->vm_stat[item]); -+ if (item == NR_FILE_DIRTY && unlikely(atomic_long_read(&zone->vm_stat[item]) < 0)) -+ atomic_long_set(&zone->vm_stat[item], 0); - atomic_long_dec(&vm_stat[item]); -+ if (item == NR_FILE_DIRTY && unlikely(atomic_long_read(&vm_stat[item]) < 0)) -+ atomic_long_set(&vm_stat[item], 0); - } - - static inline void __inc_zone_page_state(struct page *page, -diff -Nur linux-4.1.13.orig/include/linux/w1-gpio.h linux-rpi/include/linux/w1-gpio.h ---- linux-4.1.13.orig/include/linux/w1-gpio.h 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/include/linux/w1-gpio.h 2015-11-29 09:42:40.827038366 +0100 -@@ -18,6 +18,7 @@ - struct w1_gpio_platform_data { - unsigned int pin; - unsigned int is_open_drain:1; -+ unsigned int parasitic_power:1; - void (*enable_external_pullup)(int enable); - unsigned int ext_pullup_enable_pin; - unsigned int pullup_duration; -diff -Nur linux-4.1.13.orig/include/soc/bcm2835/raspberrypi-firmware.h linux-rpi/include/soc/bcm2835/raspberrypi-firmware.h ---- linux-4.1.13.orig/include/soc/bcm2835/raspberrypi-firmware.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/include/soc/bcm2835/raspberrypi-firmware.h 2015-11-29 09:42:40.871035442 +0100 -@@ -0,0 +1,124 @@ -+/* -+ * Copyright © 2015 Broadcom -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+struct rpi_firmware; -+ -+enum rpi_firmware_property_status { -+ RPI_FIRMWARE_STATUS_REQUEST = 0, -+ RPI_FIRMWARE_STATUS_SUCCESS = 0x80000000, -+ RPI_FIRMWARE_STATUS_ERROR = 0x80000001, -+}; -+ -+/** -+ * struct rpi_firmware_property_tag_header - Firmware property tag header -+ * @tag: One of enum_mbox_property_tag. -+ * @buf_size: The number of bytes in the value buffer following this -+ * struct. -+ * @req_resp_size: On submit, the length of the request (though it doesn't -+ * appear to be currently used by the firmware). On return, -+ * the length of the response (always 4 byte aligned), with -+ * the low bit set. -+ */ -+struct rpi_firmware_property_tag_header { -+ u32 tag; -+ u32 buf_size; -+ u32 req_resp_size; -+}; -+ -+enum rpi_firmware_property_tag { -+ RPI_FIRMWARE_PROPERTY_END = 0, -+ RPI_FIRMWARE_GET_FIRMWARE_REVISION = 0x00000001, -+ -+ RPI_FIRMWARE_SET_CURSOR_INFO = 0x00008010, -+ RPI_FIRMWARE_SET_CURSOR_STATE = 0x00008011, -+ -+ RPI_FIRMWARE_GET_BOARD_MODEL = 0x00010001, -+ RPI_FIRMWARE_GET_BOARD_REVISION = 0x00010002, -+ RPI_FIRMWARE_GET_BOARD_MAC_ADDRESS = 0x00010003, -+ RPI_FIRMWARE_GET_BOARD_SERIAL = 0x00010004, -+ RPI_FIRMWARE_GET_ARM_MEMORY = 0x00010005, -+ RPI_FIRMWARE_GET_VC_MEMORY = 0x00010006, -+ RPI_FIRMWARE_GET_CLOCKS = 0x00010007, -+ RPI_FIRMWARE_GET_POWER_STATE = 0x00020001, -+ RPI_FIRMWARE_GET_TIMING = 0x00020002, -+ RPI_FIRMWARE_SET_POWER_STATE = 0x00028001, -+ RPI_FIRMWARE_GET_CLOCK_STATE = 0x00030001, -+ RPI_FIRMWARE_GET_CLOCK_RATE = 0x00030002, -+ RPI_FIRMWARE_GET_VOLTAGE = 0x00030003, -+ RPI_FIRMWARE_GET_MAX_CLOCK_RATE = 0x00030004, -+ RPI_FIRMWARE_GET_MAX_VOLTAGE = 0x00030005, -+ RPI_FIRMWARE_GET_TEMPERATURE = 0x00030006, -+ RPI_FIRMWARE_GET_MIN_CLOCK_RATE = 0x00030007, -+ RPI_FIRMWARE_GET_MIN_VOLTAGE = 0x00030008, -+ RPI_FIRMWARE_GET_TURBO = 0x00030009, -+ RPI_FIRMWARE_GET_MAX_TEMPERATURE = 0x0003000a, -+ RPI_FIRMWARE_GET_STC = 0x0003000b, -+ RPI_FIRMWARE_ALLOCATE_MEMORY = 0x0003000c, -+ RPI_FIRMWARE_LOCK_MEMORY = 0x0003000d, -+ RPI_FIRMWARE_UNLOCK_MEMORY = 0x0003000e, -+ RPI_FIRMWARE_RELEASE_MEMORY = 0x0003000f, -+ RPI_FIRMWARE_EXECUTE_CODE = 0x00030010, -+ RPI_FIRMWARE_EXECUTE_QPU = 0x00030011, -+ RPI_FIRMWARE_SET_ENABLE_QPU = 0x00030012, -+ RPI_FIRMWARE_GET_DISPMANX_RESOURCE_MEM_HANDLE = 0x00030014, -+ RPI_FIRMWARE_GET_EDID_BLOCK = 0x00030020, -+ RPI_FIRMWARE_GET_CUSTOMER_OTP = 0x00030021, -+ RPI_FIRMWARE_SET_CLOCK_STATE = 0x00038001, -+ RPI_FIRMWARE_SET_CLOCK_RATE = 0x00038002, -+ RPI_FIRMWARE_SET_VOLTAGE = 0x00038003, -+ RPI_FIRMWARE_SET_TURBO = 0x00038009, -+ RPI_FIRMWARE_SET_CUSTOMER_OTP = 0x00038021, -+ -+ /* Dispmanx TAGS */ -+ RPI_FIRMWARE_FRAMEBUFFER_ALLOCATE = 0x00040001, -+ RPI_FIRMWARE_FRAMEBUFFER_BLANK = 0x00040002, -+ RPI_FIRMWARE_FRAMEBUFFER_GET_PHYSICAL_WIDTH_HEIGHT = 0x00040003, -+ RPI_FIRMWARE_FRAMEBUFFER_GET_VIRTUAL_WIDTH_HEIGHT = 0x00040004, -+ RPI_FIRMWARE_FRAMEBUFFER_GET_DEPTH = 0x00040005, -+ RPI_FIRMWARE_FRAMEBUFFER_GET_PIXEL_ORDER = 0x00040006, -+ RPI_FIRMWARE_FRAMEBUFFER_GET_ALPHA_MODE = 0x00040007, -+ RPI_FIRMWARE_FRAMEBUFFER_GET_PITCH = 0x00040008, -+ RPI_FIRMWARE_FRAMEBUFFER_GET_VIRTUAL_OFFSET = 0x00040009, -+ RPI_FIRMWARE_FRAMEBUFFER_GET_OVERSCAN = 0x0004000a, -+ RPI_FIRMWARE_FRAMEBUFFER_GET_PALETTE = 0x0004000b, -+ RPI_FIRMWARE_FRAMEBUFFER_GET_TOUCHBUF = 0x0004000f, -+ RPI_FIRMWARE_FRAMEBUFFER_RELEASE = 0x00048001, -+ RPI_FIRMWARE_FRAMEBUFFER_TEST_PHYSICAL_WIDTH_HEIGHT = 0x00044003, -+ RPI_FIRMWARE_FRAMEBUFFER_TEST_VIRTUAL_WIDTH_HEIGHT = 0x00044004, -+ RPI_FIRMWARE_FRAMEBUFFER_TEST_DEPTH = 0x00044005, -+ RPI_FIRMWARE_FRAMEBUFFER_TEST_PIXEL_ORDER = 0x00044006, -+ RPI_FIRMWARE_FRAMEBUFFER_TEST_ALPHA_MODE = 0x00044007, -+ RPI_FIRMWARE_FRAMEBUFFER_TEST_VIRTUAL_OFFSET = 0x00044009, -+ RPI_FIRMWARE_FRAMEBUFFER_TEST_OVERSCAN = 0x0004400a, -+ RPI_FIRMWARE_FRAMEBUFFER_TEST_PALETTE = 0x0004400b, -+ RPI_FIRMWARE_FRAMEBUFFER_TEST_VSYNC = 0x0004400e, -+ RPI_FIRMWARE_FRAMEBUFFER_SET_PHYSICAL_WIDTH_HEIGHT = 0x00048003, -+ RPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_WIDTH_HEIGHT = 0x00048004, -+ RPI_FIRMWARE_FRAMEBUFFER_SET_DEPTH = 0x00048005, -+ RPI_FIRMWARE_FRAMEBUFFER_SET_PIXEL_ORDER = 0x00048006, -+ RPI_FIRMWARE_FRAMEBUFFER_SET_ALPHA_MODE = 0x00048007, -+ RPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_OFFSET = 0x00048009, -+ RPI_FIRMWARE_FRAMEBUFFER_SET_OVERSCAN = 0x0004800a, -+ RPI_FIRMWARE_FRAMEBUFFER_SET_PALETTE = 0x0004800b, -+ RPI_FIRMWARE_FRAMEBUFFER_SET_VSYNC = 0x0004800e, -+ RPI_FIRMWARE_FRAMEBUFFER_SET_BACKLIGHT = 0x0004800f, -+ -+ RPI_FIRMWARE_VCHIQ_INIT = 0x00048010, -+ -+ RPI_FIRMWARE_GET_COMMAND_LINE = 0x00050001, -+ RPI_FIRMWARE_GET_DMA_CHANNELS = 0x00060001, -+}; -+ -+int rpi_firmware_property(struct rpi_firmware *fw, -+ u32 tag, void *data, size_t len); -+int rpi_firmware_property_list(struct rpi_firmware *fw, -+ void *data, size_t tag_size); -+struct rpi_firmware *rpi_firmware_get(struct device_node *firmware_node); -diff -Nur linux-4.1.13.orig/include/uapi/linux/fb.h linux-rpi/include/uapi/linux/fb.h ---- linux-4.1.13.orig/include/uapi/linux/fb.h 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/include/uapi/linux/fb.h 2015-11-29 09:42:40.943030659 +0100 -@@ -34,6 +34,11 @@ - #define FBIOPUT_MODEINFO 0x4617 - #define FBIOGET_DISPINFO 0x4618 - #define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32) -+/* -+ * HACK: use 'z' in order not to clash with any other ioctl numbers which might -+ * be concurrently added to the mainline kernel -+ */ -+#define FBIOCOPYAREA _IOW('z', 0x21, struct fb_copyarea) - - #define FB_TYPE_PACKED_PIXELS 0 /* Packed Pixels */ - #define FB_TYPE_PLANES 1 /* Non interleaved planes */ -diff -Nur linux-4.1.13.orig/kernel/cgroup.c linux-rpi/kernel/cgroup.c ---- linux-4.1.13.orig/kernel/cgroup.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/kernel/cgroup.c 2015-11-29 09:42:41.015025875 +0100 -@@ -5394,6 +5394,29 @@ - } - __setup("cgroup_disable=", cgroup_disable); - -+static int __init cgroup_enable(char *str) -+{ -+ struct cgroup_subsys *ss; -+ char *token; -+ int i; -+ -+ while ((token = strsep(&str, ",")) != NULL) { -+ if (!*token) -+ continue; -+ -+ for_each_subsys(ss, i) { -+ if (!strcmp(token, ss->name)) { -+ ss->disabled = 0; -+ printk(KERN_INFO "Enabling %s control group" -+ " subsystem\n", ss->name); -+ break; -+ } -+ } -+ } -+ return 1; -+} -+__setup("cgroup_enable=", cgroup_enable); -+ - static int __init cgroup_set_legacy_files_on_dfl(char *str) - { - printk("cgroup: using legacy files on the default hierarchy\n"); -diff -Nur linux-4.1.13.orig/mm/memcontrol.c linux-rpi/mm/memcontrol.c ---- linux-4.1.13.orig/mm/memcontrol.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/mm/memcontrol.c 2015-11-29 09:42:41.131018168 +0100 -@@ -5389,6 +5389,7 @@ - .dfl_cftypes = memory_files, - .legacy_cftypes = mem_cgroup_legacy_files, - .early_init = 0, -+ .disabled = 1, - }; - - /** -diff -Nur linux-4.1.13.orig/scripts/dtc/checks.c linux-rpi/scripts/dtc/checks.c ---- linux-4.1.13.orig/scripts/dtc/checks.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/scripts/dtc/checks.c 2015-11-29 09:42:41.403000096 +0100 -@@ -53,7 +53,7 @@ - void *data; - bool warn, error; - enum checkstatus status; -- int inprogress; -+ bool inprogress; - int num_prereqs; - struct check **prereq; - }; -@@ -113,6 +113,7 @@ - vfprintf(stderr, fmt, ap); - fprintf(stderr, "\n"); - } -+ va_end(ap); - } - - #define FAIL(c, ...) \ -@@ -141,9 +142,9 @@ - check_nodes_props(c, dt, child); - } - --static int run_check(struct check *c, struct node *dt) -+static bool run_check(struct check *c, struct node *dt) - { -- int error = 0; -+ bool error = false; - int i; - - assert(!c->inprogress); -@@ -151,11 +152,11 @@ - if (c->status != UNCHECKED) - goto out; - -- c->inprogress = 1; -+ c->inprogress = true; - - for (i = 0; i < c->num_prereqs; i++) { - struct check *prq = c->prereq[i]; -- error |= run_check(prq, dt); -+ error = error || run_check(prq, dt); - if (prq->status != PASSED) { - c->status = PREREQ; - check_msg(c, "Failed prerequisite '%s'", -@@ -177,9 +178,9 @@ - TRACE(c, "\tCompleted, status %d", c->status); - - out: -- c->inprogress = 0; -+ c->inprogress = false; - if ((c->status != PASSED) && (c->error)) -- error = 1; -+ error = true; - return error; - } - -@@ -457,22 +458,93 @@ - struct node *node, struct property *prop) - { - struct marker *m = prop->val.markers; -+ struct fixup *f, **fp; -+ struct fixup_entry *fe, **fep; - struct node *refnode; - cell_t phandle; -+ int has_phandle_refs; -+ -+ has_phandle_refs = 0; -+ for_each_marker_of_type(m, REF_PHANDLE) { -+ has_phandle_refs = 1; -+ break; -+ } -+ -+ if (!has_phandle_refs) -+ return; - - for_each_marker_of_type(m, REF_PHANDLE) { - assert(m->offset + sizeof(cell_t) <= prop->val.len); - - refnode = get_node_by_ref(dt, m->ref); -- if (! refnode) { -+ if (!refnode && !symbol_fixup_support) { - FAIL(c, "Reference to non-existent node or label \"%s\"\n", -- m->ref); -+ m->ref); - continue; - } - -- phandle = get_node_phandle(dt, refnode); -- *((cell_t *)(prop->val.val + m->offset)) = cpu_to_fdt32(phandle); -+ if (!refnode) { -+ /* allocate fixup entry */ -+ fe = xmalloc(sizeof(*fe)); -+ -+ fe->node = node; -+ fe->prop = prop; -+ fe->offset = m->offset; -+ fe->next = NULL; -+ -+ /* search for an already existing fixup */ -+ for_each_fixup(dt, f) -+ if (strcmp(f->ref, m->ref) == 0) -+ break; -+ -+ /* no fixup found, add new */ -+ if (f == NULL) { -+ f = xmalloc(sizeof(*f)); -+ f->ref = m->ref; -+ f->entries = NULL; -+ f->next = NULL; -+ -+ /* add it to the tree */ -+ fp = &dt->fixups; -+ while (*fp) -+ fp = &(*fp)->next; -+ *fp = f; -+ } -+ -+ /* and now append fixup entry */ -+ fep = &f->entries; -+ while (*fep) -+ fep = &(*fep)->next; -+ *fep = fe; -+ -+ /* mark the entry as unresolved */ -+ phandle = 0xdeadbeef; -+ } else { -+ phandle = get_node_phandle(dt, refnode); -+ -+ /* if it's a plugin, we need to record it */ -+ if (symbol_fixup_support && dt->is_plugin) { -+ -+ /* allocate a new local fixup entry */ -+ fe = xmalloc(sizeof(*fe)); -+ -+ fe->node = node; -+ fe->prop = prop; -+ fe->offset = m->offset; -+ fe->next = NULL; -+ -+ /* append it to the local fixups */ -+ fep = &dt->local_fixups; -+ while (*fep) -+ fep = &(*fep)->next; -+ *fep = fe; -+ } -+ } -+ -+ *((cell_t *)(prop->val.val + m->offset)) = -+ cpu_to_fdt32(phandle); - } -+ - } - ERROR(phandle_references, NULL, NULL, fixup_phandle_references, NULL, - &duplicate_node_names, &explicit_phandles); -@@ -624,11 +696,11 @@ - if (!reg && !ranges) - return; - -- if ((node->parent->addr_cells == -1)) -+ if (node->parent->addr_cells == -1) - FAIL(c, "Relying on default #address-cells value for %s", - node->fullpath); - -- if ((node->parent->size_cells == -1)) -+ if (node->parent->size_cells == -1) - FAIL(c, "Relying on default #size-cells value for %s", - node->fullpath); - } -@@ -651,6 +723,45 @@ - } - TREE_WARNING(obsolete_chosen_interrupt_controller, NULL); - -+static void check_auto_label_phandles(struct check *c, struct node *dt, -+ struct node *node) -+{ -+ struct label *l; -+ struct symbol *s, **sp; -+ int has_label; -+ -+ if (!symbol_fixup_support) -+ return; -+ -+ has_label = 0; -+ for_each_label(node->labels, l) { -+ has_label = 1; -+ break; -+ } -+ -+ if (!has_label) -+ return; -+ -+ /* force allocation of a phandle for this node */ -+ (void)get_node_phandle(dt, node); -+ -+ /* add the symbol */ -+ for_each_label(node->labels, l) { -+ -+ s = xmalloc(sizeof(*s)); -+ s->label = l; -+ s->node = node; -+ s->next = NULL; -+ -+ /* add it to the symbols list */ -+ sp = &dt->symbols; -+ while (*sp) -+ sp = &((*sp)->next); -+ *sp = s; -+ } -+} -+NODE_WARNING(auto_label_phandles, NULL); -+ - static struct check *check_table[] = { - &duplicate_node_names, &duplicate_property_names, - &node_name_chars, &node_name_format, &property_name_chars, -@@ -669,6 +780,8 @@ - &avoid_default_addr_size, - &obsolete_chosen_interrupt_controller, - -+ &auto_label_phandles, -+ - &always_fail, - }; - -@@ -706,15 +819,15 @@ - c->error = c->error && !error; - } - --void parse_checks_option(bool warn, bool error, const char *optarg) -+void parse_checks_option(bool warn, bool error, const char *arg) - { - int i; -- const char *name = optarg; -+ const char *name = arg; - bool enable = true; - -- if ((strncmp(optarg, "no-", 3) == 0) -- || (strncmp(optarg, "no_", 3) == 0)) { -- name = optarg + 3; -+ if ((strncmp(arg, "no-", 3) == 0) -+ || (strncmp(arg, "no_", 3) == 0)) { -+ name = arg + 3; - enable = false; - } - -@@ -733,7 +846,7 @@ - die("Unrecognized check name \"%s\"\n", name); - } - --void process_checks(int force, struct boot_info *bi) -+void process_checks(bool force, struct boot_info *bi) - { - struct node *dt = bi->dt; - int i; -diff -Nur linux-4.1.13.orig/scripts/dtc/data.c linux-rpi/scripts/dtc/data.c ---- linux-4.1.13.orig/scripts/dtc/data.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/scripts/dtc/data.c 2015-11-29 09:42:41.403000096 +0100 -@@ -74,7 +74,7 @@ - struct data d; - char *q; - -- d = data_grow_for(empty_data, strlen(s)+1); -+ d = data_grow_for(empty_data, len + 1); - - q = d.val; - while (i < len) { -@@ -250,20 +250,20 @@ - return data_append_markers(d, m); - } - --int data_is_one_string(struct data d) -+bool data_is_one_string(struct data d) - { - int i; - int len = d.len; - - if (len == 0) -- return 0; -+ return false; - - for (i = 0; i < len-1; i++) - if (d.val[i] == '\0') -- return 0; -+ return false; - - if (d.val[len-1] != '\0') -- return 0; -+ return false; - -- return 1; -+ return true; - } -diff -Nur linux-4.1.13.orig/scripts/dtc/dtc.c linux-rpi/scripts/dtc/dtc.c ---- linux-4.1.13.orig/scripts/dtc/dtc.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/scripts/dtc/dtc.c 2015-11-29 09:42:41.406999830 +0100 -@@ -29,6 +29,7 @@ - int minsize; /* Minimum blob size */ - int padsize; /* Additional padding to blob */ - int phandle_format = PHANDLE_BOTH; /* Use linux,phandle or phandle properties */ -+int symbol_fixup_support = 0; - - static void fill_fullpaths(struct node *tree, const char *prefix) - { -@@ -48,8 +49,10 @@ - } - - /* Usage related data. */ -+#define FDT_VERSION(version) _FDT_VERSION(version) -+#define _FDT_VERSION(version) #version - static const char usage_synopsis[] = "dtc [options] "; --static const char usage_short_opts[] = "qI:O:o:V:d:R:S:p:fb:i:H:sW:E:hv"; -+static const char usage_short_opts[] = "qI:O:o:V:d:R:S:p:fb:i:H:sW:E:hv@"; - static struct option const usage_long_opts[] = { - {"quiet", no_argument, NULL, 'q'}, - {"in-format", a_argument, NULL, 'I'}, -@@ -67,6 +70,7 @@ - {"phandle", a_argument, NULL, 'H'}, - {"warning", a_argument, NULL, 'W'}, - {"error", a_argument, NULL, 'E'}, -+ {"symbols", a_argument, NULL, '@'}, - {"help", no_argument, NULL, 'h'}, - {"version", no_argument, NULL, 'v'}, - {NULL, no_argument, NULL, 0x0}, -@@ -82,9 +86,9 @@ - "\t\tdts - device tree source text\n" - "\t\tdtb - device tree blob\n" - "\t\tasm - assembler source", -- "\n\tBlob version to produce, defaults to %d (for dtb and asm output)", //, DEFAULT_FDT_VERSION); -+ "\n\tBlob version to produce, defaults to "FDT_VERSION(DEFAULT_FDT_VERSION)" (for dtb and asm output)", - "\n\tOutput dependency file", -- "\n\ttMake space for reserve map entries (for dtb and asm output)", -+ "\n\tMake space for reserve map entries (for dtb and asm output)", - "\n\tMake the blob at least long (extra space)", - "\n\tAdd padding to the blob of long (extra space)", - "\n\tSet the physical boot cpu", -@@ -97,6 +101,7 @@ - "\t\tboth - Both \"linux,phandle\" and \"phandle\" properties", - "\n\tEnable/disable warnings (prefix with \"no-\")", - "\n\tEnable/disable errors (prefix with \"no-\")", -+ "\n\tSymbols and Fixups support", - "\n\tPrint this help and exit", - "\n\tPrint version and exit", - NULL, -@@ -109,7 +114,7 @@ - const char *outform = "dts"; - const char *outname = "-"; - const char *depname = NULL; -- int force = 0, sort = 0; -+ bool force = false, sort = false; - const char *arg; - int opt; - FILE *outf = NULL; -@@ -148,7 +153,7 @@ - padsize = strtol(optarg, NULL, 0); - break; - case 'f': -- force = 1; -+ force = true; - break; - case 'q': - quiet++; -@@ -174,7 +179,7 @@ - break; - - case 's': -- sort = 1; -+ sort = true; - break; - - case 'W': -@@ -184,7 +189,9 @@ - case 'E': - parse_checks_option(false, true, optarg); - break; -- -+ case '@': -+ symbol_fixup_support = 1; -+ break; - case 'h': - usage(NULL); - default: -@@ -237,7 +244,7 @@ - if (streq(outname, "-")) { - outf = stdout; - } else { -- outf = fopen(outname, "w"); -+ outf = fopen(outname, "wb"); - if (! outf) - die("Couldn't open output file %s: %s\n", - outname, strerror(errno)); -diff -Nur linux-4.1.13.orig/scripts/dtc/dtc.h linux-rpi/scripts/dtc/dtc.h ---- linux-4.1.13.orig/scripts/dtc/dtc.h 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/scripts/dtc/dtc.h 2015-11-29 09:42:41.406999830 +0100 -@@ -38,9 +38,9 @@ - #include "util.h" - - #ifdef DEBUG --#define debug(fmt,args...) printf(fmt, ##args) -+#define debug(...) printf(__VA_ARGS__) - #else --#define debug(fmt,args...) -+#define debug(...) - #endif - - -@@ -54,6 +54,7 @@ - extern int minsize; /* Minimum blob size */ - extern int padsize; /* Additional padding to blob */ - extern int phandle_format; /* Use linux,phandle or phandle properties */ -+extern int symbol_fixup_support;/* enable symbols & fixup support */ - - #define PHANDLE_LEGACY 0x1 - #define PHANDLE_EPAPR 0x2 -@@ -88,7 +89,7 @@ - }; - - --#define empty_data ((struct data){ /* all .members = 0 or NULL */ }) -+#define empty_data ((struct data){ 0 /* all .members = 0 or NULL */ }) - - #define for_each_marker(m) \ - for (; (m); (m) = (m)->next) -@@ -118,7 +119,7 @@ - - struct data data_add_marker(struct data d, enum markertype type, char *ref); - --int data_is_one_string(struct data d); -+bool data_is_one_string(struct data d); - - /* DT constraints */ - -@@ -127,13 +128,32 @@ - - /* Live trees */ - struct label { -- int deleted; -+ bool deleted; - char *label; - struct label *next; - }; - -+struct fixup_entry { -+ int offset; -+ struct node *node; -+ struct property *prop; -+ struct fixup_entry *next; -+}; -+ -+struct fixup { -+ char *ref; -+ struct fixup_entry *entries; -+ struct fixup *next; -+}; -+ -+struct symbol { -+ struct label *label; -+ struct node *node; -+ struct symbol *next; -+}; -+ - struct property { -- int deleted; -+ bool deleted; - char *name; - struct data val; - -@@ -143,7 +163,7 @@ - }; - - struct node { -- int deleted; -+ bool deleted; - char *name; - struct property *proplist; - struct node *children; -@@ -158,6 +178,12 @@ - int addr_cells, size_cells; - - struct label *labels; -+ -+ int is_root; -+ int is_plugin; -+ struct fixup *fixups; -+ struct symbol *symbols; -+ struct fixup_entry *local_fixups; - }; - - #define for_each_label_withdel(l0, l) \ -@@ -181,6 +207,18 @@ - for_each_child_withdel(n, c) \ - if (!(c)->deleted) - -+#define for_each_fixup(n, f) \ -+ for ((f) = (n)->fixups; (f); (f) = (f)->next) -+ -+#define for_each_fixup_entry(f, fe) \ -+ for ((fe) = (f)->entries; (fe); (fe) = (fe)->next) -+ -+#define for_each_symbol(n, s) \ -+ for ((s) = (n)->symbols; (s); (s) = (s)->next) -+ -+#define for_each_local_fixup_entry(n, fe) \ -+ for ((fe) = (n)->local_fixups; (fe); (fe) = (fe)->next) -+ - void add_label(struct label **labels, char *label); - void delete_labels(struct label **labels); - -@@ -247,8 +285,8 @@ - - /* Checks */ - --void parse_checks_option(bool warn, bool error, const char *optarg); --void process_checks(int force, struct boot_info *bi); -+void parse_checks_option(bool warn, bool error, const char *arg); -+void process_checks(bool force, struct boot_info *bi); - - /* Flattened trees */ - -diff -Nur linux-4.1.13.orig/scripts/dtc/dtc-lexer.l linux-rpi/scripts/dtc/dtc-lexer.l ---- linux-4.1.13.orig/scripts/dtc/dtc-lexer.l 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/scripts/dtc/dtc-lexer.l 2015-11-29 09:42:41.403000096 +0100 -@@ -20,7 +20,6 @@ - - %option noyywrap nounput noinput never-interactive - --%x INCLUDE - %x BYTESTRING - %x PROPNODENAME - %s V1 -@@ -40,6 +39,7 @@ - #include "dtc-parser.tab.h" - - YYLTYPE yylloc; -+extern bool treesource_error; - - /* CAUTION: this will stop working if we ever use yyless() or yyunput() */ - #define YY_USER_ACTION \ -@@ -61,7 +61,8 @@ - BEGIN(V1); \ - - static void push_input_file(const char *filename); --static int pop_input_file(void); -+static bool pop_input_file(void); -+static void lexical_error(const char *fmt, ...); - %} - - %% -@@ -75,11 +76,11 @@ - char *line, *tmp, *fn; - /* skip text before line # */ - line = yytext; -- while (!isdigit(*line)) -+ while (!isdigit((unsigned char)*line)) - line++; - /* skip digits in line # */ - tmp = line; -- while (!isspace(*tmp)) -+ while (!isspace((unsigned char)*tmp)) - tmp++; - /* "NULL"-terminate line # */ - *tmp = '\0'; -@@ -112,6 +113,11 @@ - return DT_V1; - } - -+<*>"/plugin/" { -+ DPRINT("Keyword: /plugin/\n"); -+ return DT_PLUGIN; -+ } -+ - <*>"/memreserve/" { - DPRINT("Keyword: /memreserve/\n"); - BEGIN_DEFAULT(); -@@ -146,15 +152,42 @@ - } - - ([0-9]+|0[xX][0-9a-fA-F]+)(U|L|UL|LL|ULL)? { -- yylval.literal = xstrdup(yytext); -- DPRINT("Literal: '%s'\n", yylval.literal); -+ char *e; -+ DPRINT("Integer Literal: '%s'\n", yytext); -+ -+ errno = 0; -+ yylval.integer = strtoull(yytext, &e, 0); -+ -+ assert(!(*e) || !e[strspn(e, "UL")]); -+ -+ if (errno == ERANGE) -+ lexical_error("Integer literal '%s' out of range", -+ yytext); -+ else -+ /* ERANGE is the only strtoull error triggerable -+ * by strings matching the pattern */ -+ assert(errno == 0); - return DT_LITERAL; - } - - <*>{CHAR_LITERAL} { -- yytext[yyleng-1] = '\0'; -- yylval.literal = xstrdup(yytext+1); -- DPRINT("Character literal: %s\n", yylval.literal); -+ struct data d; -+ DPRINT("Character literal: %s\n", yytext); -+ -+ d = data_copy_escape_string(yytext+1, yyleng-2); -+ if (d.len == 1) { -+ lexical_error("Empty character literal"); -+ yylval.integer = 0; -+ return DT_CHAR_LITERAL; -+ } -+ -+ yylval.integer = (unsigned char)d.val[0]; -+ -+ if (d.len > 2) -+ lexical_error("Character literal has %d" -+ " characters instead of 1", -+ d.len - 1); -+ - return DT_CHAR_LITERAL; - } - -@@ -164,7 +197,7 @@ - return DT_REF; - } - --<*>"&{/"{PATHCHAR}+\} { /* new-style path reference */ -+<*>"&{/"{PATHCHAR}*\} { /* new-style path reference */ - yytext[yyleng-1] = '\0'; - DPRINT("Ref: %s\n", yytext+2); - yylval.labelref = xstrdup(yytext+2); -@@ -238,13 +271,24 @@ - } - - --static int pop_input_file(void) -+static bool pop_input_file(void) - { - if (srcfile_pop() == 0) -- return 0; -+ return false; - - yypop_buffer_state(); - yyin = current_srcfile->f; - -- return 1; -+ return true; -+} -+ -+static void lexical_error(const char *fmt, ...) -+{ -+ va_list ap; -+ -+ va_start(ap, fmt); -+ srcpos_verror(&yylloc, "Lexical error", fmt, ap); -+ va_end(ap); -+ -+ treesource_error = true; - } -diff -Nur linux-4.1.13.orig/scripts/dtc/dtc-lexer.lex.c_shipped linux-rpi/scripts/dtc/dtc-lexer.lex.c_shipped ---- linux-4.1.13.orig/scripts/dtc/dtc-lexer.lex.c_shipped 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/scripts/dtc/dtc-lexer.lex.c_shipped 2015-11-29 09:42:41.406999830 +0100 -@@ -372,8 +372,8 @@ - *yy_cp = '\0'; \ - (yy_c_buf_p) = yy_cp; - --#define YY_NUM_RULES 30 --#define YY_END_OF_BUFFER 31 -+#define YY_NUM_RULES 31 -+#define YY_END_OF_BUFFER 32 - /* This struct is not used in this scanner, - but its presence is necessary. */ - struct yy_trans_info -@@ -381,25 +381,26 @@ - flex_int32_t yy_verify; - flex_int32_t yy_nxt; - }; --static yyconst flex_int16_t yy_accept[161] = -+static yyconst flex_int16_t yy_accept[166] = - { 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, 32, 30, -+ 19, 19, 30, 30, 30, 30, 30, 30, 30, 30, -+ 30, 30, 30, 30, 30, 30, 16, 17, 17, 30, -+ 17, 11, 11, 19, 27, 0, 3, 0, 28, 13, -+ 0, 0, 12, 0, 0, 0, 0, 0, 0, 0, -+ 0, 22, 24, 26, 25, 23, 0, 10, 29, 0, -+ 0, 0, 15, 15, 17, 17, 17, 11, 11, 11, -+ 0, 13, 0, 12, 0, 0, 0, 21, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 17, 11, 11, -+ 11, 0, 14, 20, 0, 0, 0, 0, 0, 0, -+ -+ 0, 0, 0, 0, 17, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 0, 17, 7, 0, 0, 0, -+ 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, -+ 0, 0, 0, 0, 4, 18, 0, 0, 5, 2, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- 31, 29, 18, 18, 29, 29, 29, 29, 29, 29, -- 29, 29, 29, 29, 29, 29, 29, 29, 15, 16, -- 16, 29, 16, 10, 10, 18, 26, 0, 3, 0, -- 27, 12, 0, 0, 11, 0, 0, 0, 0, 0, -- 0, 0, 21, 23, 25, 24, 22, 0, 9, 28, -- 0, 0, 0, 14, 14, 16, 16, 16, 10, 10, -- 10, 0, 12, 0, 11, 0, 0, 0, 20, 0, -- 0, 0, 0, 0, 0, 0, 0, 16, 10, 10, -- 10, 0, 19, 0, 0, 0, 0, 0, 0, 0, -- -- 0, 0, 16, 13, 0, 0, 0, 0, 0, 0, -- 0, 0, 0, 16, 6, 0, 0, 0, 0, 0, -- 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, -- 4, 17, 0, 0, 2, 0, 0, 0, 0, 0, -- 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, -- 0, 0, 5, 8, 0, 0, 0, 0, 7, 0 -+ 0, 0, 1, 0, 0, 0, 0, 6, 9, 0, -+ 0, 0, 0, 8, 0 - } ; - - static yyconst flex_int32_t yy_ec[256] = -@@ -415,9 +416,9 @@ - 22, 22, 22, 22, 24, 22, 22, 25, 22, 22, - 1, 26, 27, 1, 22, 1, 21, 28, 29, 30, - -- 31, 21, 22, 22, 32, 22, 22, 33, 34, 35, -- 36, 37, 22, 38, 39, 40, 41, 42, 22, 25, -- 43, 22, 44, 45, 46, 1, 1, 1, 1, 1, -+ 31, 21, 32, 22, 33, 22, 22, 34, 35, 36, -+ 37, 38, 22, 39, 40, 41, 42, 43, 22, 25, -+ 44, 22, 45, 46, 47, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, -@@ -434,163 +435,165 @@ - 1, 1, 1, 1, 1 - } ; - --static yyconst flex_int32_t yy_meta[47] = -+static yyconst flex_int32_t yy_meta[48] = - { 0, - 1, 1, 1, 1, 1, 1, 2, 3, 1, 2, - 2, 2, 4, 5, 5, 5, 6, 1, 1, 1, - 7, 8, 8, 8, 8, 1, 1, 7, 7, 7, - 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, -- 8, 8, 8, 3, 1, 1 -+ 8, 8, 8, 8, 3, 1, 4 - } ; - --static yyconst flex_int16_t yy_base[175] = -+static yyconst flex_int16_t yy_base[180] = - { 0, -- 0, 385, 378, 40, 41, 383, 72, 382, 34, 44, -- 388, 393, 61, 117, 368, 116, 115, 115, 115, 48, -- 367, 107, 368, 339, 127, 120, 0, 147, 393, 0, -- 127, 0, 133, 156, 168, 153, 393, 125, 393, 380, -- 393, 0, 369, 127, 393, 160, 371, 377, 347, 21, -- 343, 346, 393, 393, 393, 393, 393, 359, 393, 393, -- 183, 343, 339, 393, 356, 0, 183, 340, 187, 348, -- 347, 0, 0, 0, 178, 359, 195, 365, 354, 326, -- 332, 325, 334, 328, 204, 326, 331, 324, 393, 335, -- 150, 311, 343, 342, 315, 322, 340, 179, 313, 207, -- -- 319, 316, 317, 393, 337, 333, 305, 302, 311, 301, -- 310, 190, 338, 337, 393, 307, 322, 301, 305, 277, -- 208, 311, 307, 278, 271, 270, 248, 246, 213, 130, -- 393, 393, 263, 235, 207, 221, 218, 229, 213, 213, -- 206, 234, 218, 210, 208, 193, 219, 393, 223, 204, -- 176, 157, 393, 393, 120, 106, 97, 119, 393, 393, -- 245, 251, 259, 263, 267, 273, 280, 284, 292, 300, -- 304, 310, 318, 326 -+ 0, 393, 35, 392, 66, 391, 38, 107, 397, 401, -+ 55, 113, 377, 112, 111, 111, 114, 42, 376, 106, -+ 377, 347, 126, 120, 0, 147, 401, 0, 124, 0, -+ 137, 158, 170, 163, 401, 153, 401, 389, 401, 0, -+ 378, 120, 401, 131, 380, 386, 355, 139, 351, 355, -+ 351, 401, 401, 401, 401, 401, 367, 401, 401, 185, -+ 350, 346, 401, 364, 0, 185, 347, 189, 356, 355, -+ 0, 0, 330, 180, 366, 141, 372, 361, 332, 338, -+ 331, 341, 334, 326, 205, 331, 337, 329, 401, 341, -+ 167, 316, 401, 349, 348, 320, 328, 346, 180, 318, -+ -+ 324, 209, 324, 320, 322, 342, 338, 309, 306, 315, -+ 305, 315, 312, 192, 342, 341, 401, 293, 306, 282, -+ 268, 252, 255, 203, 285, 282, 272, 268, 252, 233, -+ 232, 239, 208, 107, 401, 401, 238, 211, 401, 211, -+ 212, 208, 228, 203, 215, 207, 233, 222, 212, 211, -+ 203, 227, 401, 237, 225, 204, 185, 401, 401, 149, -+ 128, 88, 42, 401, 401, 253, 259, 267, 271, 275, -+ 281, 288, 292, 300, 308, 312, 318, 326, 334 - } ; - --static yyconst flex_int16_t yy_def[175] = -+static yyconst flex_int16_t yy_def[180] = - { 0, -- 160, 1, 1, 1, 1, 5, 160, 7, 1, 1, -- 160, 160, 160, 160, 160, 161, 162, 163, 160, 160, -- 160, 160, 164, 160, 160, 160, 165, 164, 160, 166, -- 167, 166, 166, 160, 160, 160, 160, 161, 160, 161, -- 160, 168, 160, 163, 160, 163, 169, 170, 160, 160, -- 160, 160, 160, 160, 160, 160, 160, 164, 160, 160, -- 160, 160, 160, 160, 164, 166, 167, 166, 160, 160, -- 160, 171, 168, 172, 163, 169, 169, 170, 160, 160, -- 160, 160, 160, 160, 160, 160, 160, 166, 160, 160, -- 171, 172, 160, 160, 160, 160, 160, 160, 160, 160, -- -- 160, 160, 166, 160, 160, 160, 160, 160, 160, 160, -- 160, 173, 160, 166, 160, 160, 160, 160, 160, 160, -- 173, 160, 173, 160, 160, 160, 160, 160, 160, 160, -- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, -- 160, 160, 174, 160, 160, 160, 174, 160, 174, 160, -- 160, 160, 160, 160, 160, 160, 160, 160, 160, 0, -- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, -- 160, 160, 160, 160 -+ 165, 1, 1, 3, 165, 5, 1, 1, 165, 165, -+ 165, 165, 165, 166, 167, 168, 165, 165, 165, 165, -+ 169, 165, 165, 165, 170, 169, 165, 171, 172, 171, -+ 171, 165, 165, 165, 165, 166, 165, 166, 165, 173, -+ 165, 168, 165, 168, 174, 175, 165, 165, 165, 165, -+ 165, 165, 165, 165, 165, 165, 169, 165, 165, 165, -+ 165, 165, 165, 169, 171, 172, 171, 165, 165, 165, -+ 176, 173, 177, 168, 174, 174, 175, 165, 165, 165, -+ 165, 165, 165, 165, 165, 165, 165, 171, 165, 165, -+ 176, 177, 165, 165, 165, 165, 165, 165, 165, 165, -+ -+ 165, 165, 165, 165, 171, 165, 165, 165, 165, 165, -+ 165, 165, 165, 178, 165, 171, 165, 165, 165, 165, -+ 165, 165, 165, 178, 165, 178, 165, 165, 165, 165, -+ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165, -+ 165, 165, 165, 165, 165, 165, 165, 179, 165, 165, -+ 165, 179, 165, 179, 165, 165, 165, 165, 165, 165, -+ 165, 165, 165, 165, 0, 165, 165, 165, 165, 165, -+ 165, 165, 165, 165, 165, 165, 165, 165, 165 - } ; - --static yyconst flex_int16_t yy_nxt[440] = -+static yyconst flex_int16_t yy_nxt[449] = - { 0, -- 12, 13, 14, 13, 15, 16, 12, 17, 18, 12, -- 12, 12, 19, 12, 12, 12, 12, 20, 21, 22, -- 23, 23, 23, 23, 23, 12, 12, 23, 23, 23, -- 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, -- 23, 23, 23, 12, 24, 12, 25, 34, 35, 35, -- 25, 81, 26, 26, 27, 27, 27, 34, 35, 35, -- 82, 28, 36, 36, 36, 53, 54, 29, 28, 28, -- 28, 28, 12, 13, 14, 13, 15, 16, 30, 17, -- 18, 30, 30, 30, 26, 30, 30, 30, 12, 20, -- 21, 22, 31, 31, 31, 31, 31, 32, 12, 31, -- -- 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, -- 31, 31, 31, 31, 31, 12, 24, 12, 36, 36, -- 36, 39, 41, 45, 47, 56, 57, 48, 61, 47, -- 39, 159, 48, 66, 61, 45, 66, 66, 66, 158, -- 46, 40, 49, 59, 50, 157, 51, 49, 52, 50, -- 40, 63, 46, 52, 36, 36, 36, 156, 43, 62, -- 65, 65, 65, 59, 136, 68, 137, 65, 75, 69, -- 69, 69, 70, 71, 65, 65, 65, 65, 70, 71, -- 72, 69, 69, 69, 61, 46, 45, 155, 154, 66, -- 70, 71, 66, 66, 66, 122, 85, 85, 85, 59, -- -- 69, 69, 69, 46, 77, 100, 109, 93, 100, 70, -- 71, 110, 112, 122, 129, 123, 153, 85, 85, 85, -- 135, 135, 135, 148, 148, 160, 135, 135, 135, 152, -- 142, 142, 142, 123, 143, 142, 142, 142, 151, 143, -- 150, 146, 145, 149, 149, 38, 38, 38, 38, 38, -- 38, 38, 38, 42, 144, 141, 140, 42, 42, 44, -- 44, 44, 44, 44, 44, 44, 44, 58, 58, 58, -- 58, 64, 139, 64, 66, 138, 134, 66, 133, 66, -- 66, 67, 132, 131, 67, 67, 67, 67, 73, 130, -- 73, 73, 76, 76, 76, 76, 76, 76, 76, 76, -- -- 78, 78, 78, 78, 78, 78, 78, 78, 91, 160, -- 91, 92, 129, 92, 92, 128, 92, 92, 121, 121, -- 121, 121, 121, 121, 121, 121, 147, 147, 147, 147, -- 147, 147, 147, 147, 127, 126, 125, 124, 61, 61, -- 120, 119, 118, 117, 116, 115, 47, 114, 110, 113, -- 111, 108, 107, 106, 48, 105, 104, 89, 103, 102, -- 101, 99, 98, 97, 96, 95, 94, 79, 77, 90, -- 89, 88, 59, 87, 86, 59, 84, 83, 80, 79, -- 77, 74, 160, 60, 59, 55, 37, 160, 33, 25, -- 26, 25, 11, 160, 160, 160, 160, 160, 160, 160, -- -- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, -- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, -- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, -- 160, 160, 160, 160, 160, 160, 160, 160, 160 -+ 10, 11, 12, 11, 13, 14, 10, 15, 16, 10, -+ 10, 10, 17, 10, 10, 10, 10, 18, 19, 20, -+ 21, 21, 21, 21, 21, 10, 10, 21, 21, 21, -+ 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, -+ 21, 21, 21, 21, 10, 22, 10, 24, 25, 25, -+ 25, 32, 33, 33, 164, 26, 34, 34, 34, 52, -+ 53, 27, 26, 26, 26, 26, 10, 11, 12, 11, -+ 13, 14, 28, 15, 16, 28, 28, 28, 24, 28, -+ 28, 28, 10, 18, 19, 20, 29, 29, 29, 29, -+ 29, 30, 10, 29, 29, 29, 29, 29, 29, 29, -+ -+ 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, -+ 10, 22, 10, 23, 34, 34, 34, 37, 39, 43, -+ 32, 33, 33, 45, 55, 56, 46, 60, 43, 45, -+ 65, 163, 46, 65, 65, 65, 44, 38, 60, 74, -+ 58, 47, 141, 48, 142, 44, 49, 47, 50, 48, -+ 76, 51, 62, 94, 50, 41, 44, 51, 37, 61, -+ 64, 64, 64, 58, 34, 34, 34, 64, 162, 80, -+ 67, 68, 68, 68, 64, 64, 64, 64, 38, 81, -+ 69, 70, 71, 68, 68, 68, 60, 161, 43, 69, -+ 70, 65, 69, 70, 65, 65, 65, 125, 85, 85, -+ -+ 85, 58, 68, 68, 68, 44, 102, 110, 125, 133, -+ 102, 69, 70, 111, 114, 160, 159, 126, 85, 85, -+ 85, 140, 140, 140, 140, 140, 140, 153, 126, 147, -+ 147, 147, 153, 148, 147, 147, 147, 158, 148, 165, -+ 157, 156, 155, 151, 150, 149, 146, 154, 145, 144, -+ 143, 139, 154, 36, 36, 36, 36, 36, 36, 36, -+ 36, 40, 138, 137, 136, 40, 40, 42, 42, 42, -+ 42, 42, 42, 42, 42, 57, 57, 57, 57, 63, -+ 135, 63, 65, 134, 165, 65, 133, 65, 65, 66, -+ 132, 131, 66, 66, 66, 66, 72, 130, 72, 72, -+ -+ 75, 75, 75, 75, 75, 75, 75, 75, 77, 77, -+ 77, 77, 77, 77, 77, 77, 91, 129, 91, 92, -+ 128, 92, 92, 127, 92, 92, 124, 124, 124, 124, -+ 124, 124, 124, 124, 152, 152, 152, 152, 152, 152, -+ 152, 152, 60, 60, 123, 122, 121, 120, 119, 118, -+ 117, 45, 116, 111, 115, 113, 112, 109, 108, 107, -+ 46, 106, 93, 89, 105, 104, 103, 101, 100, 99, -+ 98, 97, 96, 95, 78, 76, 93, 90, 89, 88, -+ 58, 87, 86, 58, 84, 83, 82, 79, 78, 76, -+ 73, 165, 59, 58, 54, 35, 165, 31, 23, 23, -+ -+ 9, 165, 165, 165, 165, 165, 165, 165, 165, 165, -+ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165, -+ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165, -+ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165, -+ 165, 165, 165, 165, 165, 165, 165, 165 - } ; - --static yyconst flex_int16_t yy_chk[440] = -+static yyconst flex_int16_t yy_chk[449] = - { 0, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, -- 1, 1, 1, 1, 1, 1, 4, 9, 9, 9, -- 10, 50, 4, 5, 5, 5, 5, 10, 10, 10, -- 50, 5, 13, 13, 13, 20, 20, 5, 5, 5, -- 5, 5, 7, 7, 7, 7, 7, 7, 7, 7, -- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, -- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, -- -- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, -- 7, 7, 7, 7, 7, 7, 7, 7, 14, 14, -- 14, 16, 17, 18, 19, 22, 22, 19, 25, 26, -- 38, 158, 26, 31, 33, 44, 31, 31, 31, 157, -- 18, 16, 19, 31, 19, 156, 19, 26, 19, 26, -- 38, 26, 44, 26, 36, 36, 36, 155, 17, 25, -- 28, 28, 28, 28, 130, 33, 130, 28, 46, 34, -- 34, 34, 91, 91, 28, 28, 28, 28, 34, 34, -- 34, 35, 35, 35, 61, 46, 75, 152, 151, 67, -- 35, 35, 67, 67, 67, 112, 61, 61, 61, 67, -- -- 69, 69, 69, 75, 77, 85, 98, 77, 100, 69, -- 69, 98, 100, 121, 129, 112, 150, 85, 85, 85, -- 135, 135, 135, 143, 147, 149, 129, 129, 129, 146, -- 138, 138, 138, 121, 138, 142, 142, 142, 145, 142, -- 144, 141, 140, 143, 147, 161, 161, 161, 161, 161, -- 161, 161, 161, 162, 139, 137, 136, 162, 162, 163, -- 163, 163, 163, 163, 163, 163, 163, 164, 164, 164, -- 164, 165, 134, 165, 166, 133, 128, 166, 127, 166, -- 166, 167, 126, 125, 167, 167, 167, 167, 168, 124, -- 168, 168, 169, 169, 169, 169, 169, 169, 169, 169, -- -- 170, 170, 170, 170, 170, 170, 170, 170, 171, 123, -- 171, 172, 122, 172, 172, 120, 172, 172, 173, 173, -- 173, 173, 173, 173, 173, 173, 174, 174, 174, 174, -- 174, 174, 174, 174, 119, 118, 117, 116, 114, 113, -- 111, 110, 109, 108, 107, 106, 105, 103, 102, 101, -- 99, 97, 96, 95, 94, 93, 92, 90, 88, 87, -- 86, 84, 83, 82, 81, 80, 79, 78, 76, 71, -- 70, 68, 65, 63, 62, 58, 52, 51, 49, 48, -- 47, 43, 40, 24, 23, 21, 15, 11, 8, 6, -- 3, 2, 160, 160, 160, 160, 160, 160, 160, 160, -- -- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, -- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, -- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, -- 160, 160, 160, 160, 160, 160, 160, 160, 160 -+ 1, 1, 1, 1, 1, 1, 1, 3, 3, 3, -+ 3, 7, 7, 7, 163, 3, 11, 11, 11, 18, -+ 18, 3, 3, 3, 3, 3, 5, 5, 5, 5, -+ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, -+ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, -+ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, -+ -+ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, -+ 5, 5, 5, 8, 12, 12, 12, 14, 15, 16, -+ 8, 8, 8, 17, 20, 20, 17, 23, 42, 24, -+ 29, 162, 24, 29, 29, 29, 16, 14, 31, 44, -+ 29, 17, 134, 17, 134, 42, 17, 24, 17, 24, -+ 76, 17, 24, 76, 24, 15, 44, 24, 36, 23, -+ 26, 26, 26, 26, 34, 34, 34, 26, 161, 48, -+ 31, 32, 32, 32, 26, 26, 26, 26, 36, 48, -+ 32, 32, 32, 33, 33, 33, 60, 160, 74, 91, -+ 91, 66, 33, 33, 66, 66, 66, 114, 60, 60, -+ -+ 60, 66, 68, 68, 68, 74, 85, 99, 124, 133, -+ 102, 68, 68, 99, 102, 157, 156, 114, 85, 85, -+ 85, 133, 133, 133, 140, 140, 140, 148, 124, 143, -+ 143, 143, 152, 143, 147, 147, 147, 155, 147, 154, -+ 151, 150, 149, 146, 145, 144, 142, 148, 141, 138, -+ 137, 132, 152, 166, 166, 166, 166, 166, 166, 166, -+ 166, 167, 131, 130, 129, 167, 167, 168, 168, 168, -+ 168, 168, 168, 168, 168, 169, 169, 169, 169, 170, -+ 128, 170, 171, 127, 126, 171, 125, 171, 171, 172, -+ 123, 122, 172, 172, 172, 172, 173, 121, 173, 173, -+ -+ 174, 174, 174, 174, 174, 174, 174, 174, 175, 175, -+ 175, 175, 175, 175, 175, 175, 176, 120, 176, 177, -+ 119, 177, 177, 118, 177, 177, 178, 178, 178, 178, -+ 178, 178, 178, 178, 179, 179, 179, 179, 179, 179, -+ 179, 179, 116, 115, 113, 112, 111, 110, 109, 108, -+ 107, 106, 105, 104, 103, 101, 100, 98, 97, 96, -+ 95, 94, 92, 90, 88, 87, 86, 84, 83, 82, -+ 81, 80, 79, 78, 77, 75, 73, 70, 69, 67, -+ 64, 62, 61, 57, 51, 50, 49, 47, 46, 45, -+ 41, 38, 22, 21, 19, 13, 9, 6, 4, 2, -+ -+ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165, -+ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165, -+ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165, -+ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165, -+ 165, 165, 165, 165, 165, 165, 165, 165 - } ; - - static yy_state_type yy_last_accepting_state; -@@ -631,13 +634,13 @@ - - - -- --#line 38 "dtc-lexer.l" -+#line 37 "dtc-lexer.l" - #include "dtc.h" - #include "srcpos.h" - #include "dtc-parser.tab.h" - - YYLTYPE yylloc; -+extern bool treesource_error; - - /* CAUTION: this will stop working if we ever use yyless() or yyunput() */ - #define YY_USER_ACTION \ -@@ -659,14 +662,14 @@ - BEGIN(V1); \ - - static void push_input_file(const char *filename); --static int pop_input_file(void); --#line 664 "dtc-lexer.lex.c" -+static bool pop_input_file(void); -+static void lexical_error(const char *fmt, ...); -+#line 668 "dtc-lexer.lex.c" - - #define INITIAL 0 --#define INCLUDE 1 --#define BYTESTRING 2 --#define PROPNODENAME 3 --#define V1 4 -+#define BYTESTRING 1 -+#define PROPNODENAME 2 -+#define V1 3 - - #ifndef YY_NO_UNISTD_H - /* Special case for "unistd.h", since it is non-ANSI. We include it way -@@ -852,9 +855,9 @@ - register char *yy_cp, *yy_bp; - register int yy_act; - --#line 67 "dtc-lexer.l" -+#line 68 "dtc-lexer.l" - --#line 858 "dtc-lexer.lex.c" -+#line 861 "dtc-lexer.lex.c" - - if ( !(yy_init) ) - { -@@ -908,13 +911,13 @@ - while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) - { - yy_current_state = (int) yy_def[yy_current_state]; -- if ( yy_current_state >= 161 ) -+ if ( yy_current_state >= 166 ) - yy_c = yy_meta[(unsigned int) yy_c]; - } - yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c]; - ++yy_cp; - } -- while ( yy_current_state != 160 ); -+ while ( yy_current_state != 165 ); - yy_cp = (yy_last_accepting_cpos); - yy_current_state = (yy_last_accepting_state); - -@@ -937,7 +940,7 @@ - case 1: - /* rule 1 can match eol */ - YY_RULE_SETUP --#line 68 "dtc-lexer.l" -+#line 69 "dtc-lexer.l" - { - char *name = strchr(yytext, '\"') + 1; - yytext[yyleng-1] = '\0'; -@@ -947,16 +950,16 @@ - case 2: - /* rule 2 can match eol */ - YY_RULE_SETUP --#line 74 "dtc-lexer.l" -+#line 75 "dtc-lexer.l" - { - char *line, *tmp, *fn; - /* skip text before line # */ - line = yytext; -- while (!isdigit(*line)) -+ while (!isdigit((unsigned char)*line)) - line++; - /* skip digits in line # */ - tmp = line; -- while (!isspace(*tmp)) -+ while (!isspace((unsigned char)*tmp)) - tmp++; - /* "NULL"-terminate line # */ - *tmp = '\0'; -@@ -970,11 +973,10 @@ - } - YY_BREAK - case YY_STATE_EOF(INITIAL): --case YY_STATE_EOF(INCLUDE): - case YY_STATE_EOF(BYTESTRING): - case YY_STATE_EOF(PROPNODENAME): - case YY_STATE_EOF(V1): --#line 95 "dtc-lexer.l" -+#line 96 "dtc-lexer.l" - { - if (!pop_input_file()) { - yyterminate(); -@@ -984,7 +986,7 @@ - case 3: - /* rule 3 can match eol */ - YY_RULE_SETUP --#line 101 "dtc-lexer.l" -+#line 102 "dtc-lexer.l" - { - DPRINT("String: %s\n", yytext); - yylval.data = data_copy_escape_string(yytext+1, -@@ -994,7 +996,7 @@ - YY_BREAK - case 4: - YY_RULE_SETUP --#line 108 "dtc-lexer.l" -+#line 109 "dtc-lexer.l" - { - DPRINT("Keyword: /dts-v1/\n"); - dts_version = 1; -@@ -1004,25 +1006,33 @@ - YY_BREAK - case 5: - YY_RULE_SETUP --#line 115 "dtc-lexer.l" -+#line 116 "dtc-lexer.l" -+{ -+ DPRINT("Keyword: /plugin/\n"); -+ return DT_PLUGIN; -+ } -+ YY_BREAK -+case 6: -+YY_RULE_SETUP -+#line 121 "dtc-lexer.l" - { - DPRINT("Keyword: /memreserve/\n"); - BEGIN_DEFAULT(); - return DT_MEMRESERVE; - } - YY_BREAK --case 6: -+case 7: - YY_RULE_SETUP --#line 121 "dtc-lexer.l" -+#line 127 "dtc-lexer.l" - { - DPRINT("Keyword: /bits/\n"); - BEGIN_DEFAULT(); - return DT_BITS; - } - YY_BREAK --case 7: -+case 8: - YY_RULE_SETUP --#line 127 "dtc-lexer.l" -+#line 133 "dtc-lexer.l" - { - DPRINT("Keyword: /delete-property/\n"); - DPRINT("\n"); -@@ -1030,9 +1040,9 @@ - return DT_DEL_PROP; - } - YY_BREAK --case 8: -+case 9: - YY_RULE_SETUP --#line 134 "dtc-lexer.l" -+#line 140 "dtc-lexer.l" - { - DPRINT("Keyword: /delete-node/\n"); - DPRINT("\n"); -@@ -1040,9 +1050,9 @@ - return DT_DEL_NODE; - } - YY_BREAK --case 9: -+case 10: - YY_RULE_SETUP --#line 141 "dtc-lexer.l" -+#line 147 "dtc-lexer.l" - { - DPRINT("Label: %s\n", yytext); - yylval.labelref = xstrdup(yytext); -@@ -1050,38 +1060,65 @@ - return DT_LABEL; - } - YY_BREAK --case 10: -+case 11: - YY_RULE_SETUP --#line 148 "dtc-lexer.l" -+#line 154 "dtc-lexer.l" - { -- yylval.literal = xstrdup(yytext); -- DPRINT("Literal: '%s'\n", yylval.literal); -+ char *e; -+ DPRINT("Integer Literal: '%s'\n", yytext); -+ -+ errno = 0; -+ yylval.integer = strtoull(yytext, &e, 0); -+ -+ assert(!(*e) || !e[strspn(e, "UL")]); -+ -+ if (errno == ERANGE) -+ lexical_error("Integer literal '%s' out of range", -+ yytext); -+ else -+ /* ERANGE is the only strtoull error triggerable -+ * by strings matching the pattern */ -+ assert(errno == 0); - return DT_LITERAL; - } - YY_BREAK --case 11: --/* rule 11 can match eol */ -+case 12: -+/* rule 12 can match eol */ - YY_RULE_SETUP --#line 154 "dtc-lexer.l" -+#line 173 "dtc-lexer.l" - { -- yytext[yyleng-1] = '\0'; -- yylval.literal = xstrdup(yytext+1); -- DPRINT("Character literal: %s\n", yylval.literal); -+ struct data d; -+ DPRINT("Character literal: %s\n", yytext); -+ -+ d = data_copy_escape_string(yytext+1, yyleng-2); -+ if (d.len == 1) { -+ lexical_error("Empty character literal"); -+ yylval.integer = 0; -+ return DT_CHAR_LITERAL; -+ } -+ -+ yylval.integer = (unsigned char)d.val[0]; -+ -+ if (d.len > 2) -+ lexical_error("Character literal has %d" -+ " characters instead of 1", -+ d.len - 1); -+ - return DT_CHAR_LITERAL; - } - YY_BREAK --case 12: -+case 13: - YY_RULE_SETUP --#line 161 "dtc-lexer.l" -+#line 194 "dtc-lexer.l" - { /* label reference */ - DPRINT("Ref: %s\n", yytext+1); - yylval.labelref = xstrdup(yytext+1); - return DT_REF; - } - YY_BREAK --case 13: -+case 14: - YY_RULE_SETUP --#line 167 "dtc-lexer.l" -+#line 200 "dtc-lexer.l" - { /* new-style path reference */ - yytext[yyleng-1] = '\0'; - DPRINT("Ref: %s\n", yytext+2); -@@ -1089,27 +1126,27 @@ - return DT_REF; - } - YY_BREAK --case 14: -+case 15: - YY_RULE_SETUP --#line 174 "dtc-lexer.l" -+#line 207 "dtc-lexer.l" - { - yylval.byte = strtol(yytext, NULL, 16); - DPRINT("Byte: %02x\n", (int)yylval.byte); - return DT_BYTE; - } - YY_BREAK --case 15: -+case 16: - YY_RULE_SETUP --#line 180 "dtc-lexer.l" -+#line 213 "dtc-lexer.l" - { - DPRINT("/BYTESTRING\n"); - BEGIN_DEFAULT(); - return ']'; - } - YY_BREAK --case 16: -+case 17: - YY_RULE_SETUP --#line 186 "dtc-lexer.l" -+#line 219 "dtc-lexer.l" - { - DPRINT("PropNodeName: %s\n", yytext); - yylval.propnodename = xstrdup((yytext[0] == '\\') ? -@@ -1118,75 +1155,75 @@ - return DT_PROPNODENAME; - } - YY_BREAK --case 17: -+case 18: - YY_RULE_SETUP --#line 194 "dtc-lexer.l" -+#line 227 "dtc-lexer.l" - { - DPRINT("Binary Include\n"); - return DT_INCBIN; - } - YY_BREAK --case 18: --/* rule 18 can match eol */ --YY_RULE_SETUP --#line 199 "dtc-lexer.l" --/* eat whitespace */ -- YY_BREAK - case 19: - /* rule 19 can match eol */ - YY_RULE_SETUP --#line 200 "dtc-lexer.l" --/* eat C-style comments */ -+#line 232 "dtc-lexer.l" -+/* eat whitespace */ - YY_BREAK - case 20: - /* rule 20 can match eol */ - YY_RULE_SETUP --#line 201 "dtc-lexer.l" --/* eat C++-style comments */ -+#line 233 "dtc-lexer.l" -+/* eat C-style comments */ - YY_BREAK - case 21: -+/* rule 21 can match eol */ - YY_RULE_SETUP --#line 203 "dtc-lexer.l" --{ return DT_LSHIFT; }; -+#line 234 "dtc-lexer.l" -+/* eat C++-style comments */ - YY_BREAK - case 22: - YY_RULE_SETUP --#line 204 "dtc-lexer.l" --{ return DT_RSHIFT; }; -+#line 236 "dtc-lexer.l" -+{ return DT_LSHIFT; }; - YY_BREAK - case 23: - YY_RULE_SETUP --#line 205 "dtc-lexer.l" --{ return DT_LE; }; -+#line 237 "dtc-lexer.l" -+{ return DT_RSHIFT; }; - YY_BREAK - case 24: - YY_RULE_SETUP --#line 206 "dtc-lexer.l" --{ return DT_GE; }; -+#line 238 "dtc-lexer.l" -+{ return DT_LE; }; - YY_BREAK - case 25: - YY_RULE_SETUP --#line 207 "dtc-lexer.l" --{ return DT_EQ; }; -+#line 239 "dtc-lexer.l" -+{ return DT_GE; }; - YY_BREAK - case 26: - YY_RULE_SETUP --#line 208 "dtc-lexer.l" --{ return DT_NE; }; -+#line 240 "dtc-lexer.l" -+{ return DT_EQ; }; - YY_BREAK - case 27: - YY_RULE_SETUP --#line 209 "dtc-lexer.l" --{ return DT_AND; }; -+#line 241 "dtc-lexer.l" -+{ return DT_NE; }; - YY_BREAK - case 28: - YY_RULE_SETUP --#line 210 "dtc-lexer.l" --{ return DT_OR; }; -+#line 242 "dtc-lexer.l" -+{ return DT_AND; }; - YY_BREAK - case 29: - YY_RULE_SETUP --#line 212 "dtc-lexer.l" -+#line 243 "dtc-lexer.l" -+{ return DT_OR; }; -+ YY_BREAK -+case 30: -+YY_RULE_SETUP -+#line 245 "dtc-lexer.l" - { - DPRINT("Char: %c (\\x%02x)\n", yytext[0], - (unsigned)yytext[0]); -@@ -1202,12 +1239,12 @@ - return yytext[0]; - } - YY_BREAK --case 30: -+case 31: - YY_RULE_SETUP --#line 227 "dtc-lexer.l" -+#line 260 "dtc-lexer.l" - ECHO; - YY_BREAK --#line 1211 "dtc-lexer.lex.c" -+#line 1248 "dtc-lexer.lex.c" - - case YY_END_OF_BUFFER: - { -@@ -1499,7 +1536,7 @@ - while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) - { - yy_current_state = (int) yy_def[yy_current_state]; -- if ( yy_current_state >= 161 ) -+ if ( yy_current_state >= 166 ) - yy_c = yy_meta[(unsigned int) yy_c]; - } - yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c]; -@@ -1527,11 +1564,11 @@ - while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) - { - yy_current_state = (int) yy_def[yy_current_state]; -- if ( yy_current_state >= 161 ) -+ if ( yy_current_state >= 166 ) - yy_c = yy_meta[(unsigned int) yy_c]; - } - yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c]; -- yy_is_jam = (yy_current_state == 160); -+ yy_is_jam = (yy_current_state == 165); - - return yy_is_jam ? 0 : yy_current_state; - } -@@ -2166,7 +2203,7 @@ - - #define YYTABLES_NAME "yytables" - --#line 227 "dtc-lexer.l" -+#line 260 "dtc-lexer.l" - - - -@@ -2182,14 +2219,25 @@ - } - - --static int pop_input_file(void) -+static bool pop_input_file(void) - { - if (srcfile_pop() == 0) -- return 0; -+ return false; - - yypop_buffer_state(); - yyin = current_srcfile->f; - -- return 1; -+ return true; -+} -+ -+static void lexical_error(const char *fmt, ...) -+{ -+ va_list ap; -+ -+ va_start(ap, fmt); -+ srcpos_verror(&yylloc, "Lexical error", fmt, ap); -+ va_end(ap); -+ -+ treesource_error = true; - } - -diff -Nur linux-4.1.13.orig/scripts/dtc/dtc-parser.tab.c_shipped linux-rpi/scripts/dtc/dtc-parser.tab.c_shipped ---- linux-4.1.13.orig/scripts/dtc/dtc-parser.tab.c_shipped 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/scripts/dtc/dtc-parser.tab.c_shipped 2015-11-29 09:42:41.406999830 +0100 -@@ -1,19 +1,19 @@ --/* A Bison parser, made by GNU Bison 2.7.12-4996. */ -+/* A Bison parser, made by GNU Bison 3.0.2. */ - - /* Bison implementation for Yacc-like parsers in C -- -- Copyright (C) 1984, 1989-1990, 2000-2013 Free Software Foundation, Inc. -- -+ -+ Copyright (C) 1984, 1989-1990, 2000-2013 Free Software Foundation, Inc. -+ - This program is free software: you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation, either version 3 of the License, or - (at your option) any later version. -- -+ - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -- -+ - You should have received a copy of the GNU General Public License - along with this program. If not, see . */ - -@@ -26,7 +26,7 @@ - special exception, which will cause the skeleton and the resulting - Bison output files to be licensed under the GNU General Public - License without this special exception. -- -+ - This special exception was added by the Free Software Foundation in - version 2.2 of Bison. */ - -@@ -44,7 +44,7 @@ - #define YYBISON 1 - - /* Bison version. */ --#define YYBISON_VERSION "2.7.12-4996" -+#define YYBISON_VERSION "3.0.2" - - /* Skeleton name. */ - #define YYSKELETON_NAME "yacc.c" -@@ -62,34 +62,32 @@ - - - /* Copy the first part of user declarations. */ --/* Line 371 of yacc.c */ --#line 21 "dtc-parser.y" -+#line 20 "dtc-parser.y" /* yacc.c:339 */ - - #include -+#include - - #include "dtc.h" - #include "srcpos.h" - --YYLTYPE yylloc; -- - extern int yylex(void); --extern void print_error(char const *fmt, ...); - extern void yyerror(char const *s); -+#define ERROR(loc, ...) \ -+ do { \ -+ srcpos_error((loc), "Error", __VA_ARGS__); \ -+ treesource_error = true; \ -+ } while (0) - - extern struct boot_info *the_boot_info; --extern int treesource_error; -- --static unsigned long long eval_literal(const char *s, int base, int bits); --static unsigned char eval_char_literal(const char *s); -+extern bool treesource_error; - --/* Line 371 of yacc.c */ --#line 87 "dtc-parser.tab.c" -+#line 85 "dtc-parser.tab.c" /* yacc.c:339 */ - --# ifndef YY_NULL -+# ifndef YY_NULLPTR - # if defined __cplusplus && 201103L <= __cplusplus --# define YY_NULL nullptr -+# define YY_NULLPTR nullptr - # else --# define YY_NULL 0 -+# define YY_NULLPTR 0 - # endif - # endif - -@@ -105,7 +103,7 @@ - by #include "dtc-parser.tab.h". */ - #ifndef YY_YY_DTC_PARSER_TAB_H_INCLUDED - # define YY_YY_DTC_PARSER_TAB_H_INCLUDED --/* Enabling traces. */ -+/* Debug traces. */ - #ifndef YYDEBUG - # define YYDEBUG 0 - #endif -@@ -113,48 +111,45 @@ - extern int yydebug; - #endif - --/* Tokens. */ -+/* Token type. */ - #ifndef YYTOKENTYPE - # define YYTOKENTYPE -- /* Put the tokens into the symbol table, so that GDB and other debuggers -- know about them. */ -- enum yytokentype { -- DT_V1 = 258, -- DT_MEMRESERVE = 259, -- DT_LSHIFT = 260, -- DT_RSHIFT = 261, -- DT_LE = 262, -- DT_GE = 263, -- DT_EQ = 264, -- DT_NE = 265, -- DT_AND = 266, -- DT_OR = 267, -- DT_BITS = 268, -- DT_DEL_PROP = 269, -- DT_DEL_NODE = 270, -- DT_PROPNODENAME = 271, -- DT_LITERAL = 272, -- DT_CHAR_LITERAL = 273, -- DT_BASE = 274, -- DT_BYTE = 275, -- DT_STRING = 276, -- DT_LABEL = 277, -- DT_REF = 278, -- DT_INCBIN = 279 -- }; -+ enum yytokentype -+ { -+ DT_V1 = 258, -+ DT_PLUGIN = 259, -+ DT_MEMRESERVE = 260, -+ DT_LSHIFT = 261, -+ DT_RSHIFT = 262, -+ DT_LE = 263, -+ DT_GE = 264, -+ DT_EQ = 265, -+ DT_NE = 266, -+ DT_AND = 267, -+ DT_OR = 268, -+ DT_BITS = 269, -+ DT_DEL_PROP = 270, -+ DT_DEL_NODE = 271, -+ DT_PROPNODENAME = 272, -+ DT_LITERAL = 273, -+ DT_CHAR_LITERAL = 274, -+ DT_BYTE = 275, -+ DT_STRING = 276, -+ DT_LABEL = 277, -+ DT_REF = 278, -+ DT_INCBIN = 279 -+ }; - #endif - -- -+/* Value type. */ - #if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED --typedef union YYSTYPE -+typedef union YYSTYPE YYSTYPE; -+union YYSTYPE - { --/* Line 387 of yacc.c */ --#line 40 "dtc-parser.y" -+#line 39 "dtc-parser.y" /* yacc.c:355 */ - - char *propnodename; -- char *literal; - char *labelref; -- unsigned int cbase; - uint8_t byte; - struct data data; - -@@ -169,38 +164,38 @@ - struct node *nodelist; - struct reserve_info *re; - uint64_t integer; -+ int is_plugin; - -- --/* Line 387 of yacc.c */ --#line 176 "dtc-parser.tab.c" --} YYSTYPE; -+#line 170 "dtc-parser.tab.c" /* yacc.c:355 */ -+}; - # define YYSTYPE_IS_TRIVIAL 1 --# define yystype YYSTYPE /* obsolescent; will be withdrawn */ - # define YYSTYPE_IS_DECLARED 1 - #endif - --extern YYSTYPE yylval; -- --#ifdef YYPARSE_PARAM --#if defined __STDC__ || defined __cplusplus --int yyparse (void *YYPARSE_PARAM); --#else --int yyparse (); -+/* Location type. */ -+#if ! defined YYLTYPE && ! defined YYLTYPE_IS_DECLARED -+typedef struct YYLTYPE YYLTYPE; -+struct YYLTYPE -+{ -+ int first_line; -+ int first_column; -+ int last_line; -+ int last_column; -+}; -+# define YYLTYPE_IS_DECLARED 1 -+# define YYLTYPE_IS_TRIVIAL 1 - #endif --#else /* ! YYPARSE_PARAM */ --#if defined __STDC__ || defined __cplusplus -+ -+ -+extern YYSTYPE yylval; -+extern YYLTYPE yylloc; - int yyparse (void); --#else --int yyparse (); --#endif --#endif /* ! YYPARSE_PARAM */ - - #endif /* !YY_YY_DTC_PARSER_TAB_H_INCLUDED */ - - /* Copy the second part of user declarations. */ - --/* Line 390 of yacc.c */ --#line 204 "dtc-parser.tab.c" -+#line 199 "dtc-parser.tab.c" /* yacc.c:358 */ - - #ifdef short - # undef short -@@ -214,11 +209,8 @@ - - #ifdef YYTYPE_INT8 - typedef YYTYPE_INT8 yytype_int8; --#elif (defined __STDC__ || defined __C99__FUNC__ \ -- || defined __cplusplus || defined _MSC_VER) --typedef signed char yytype_int8; - #else --typedef short int yytype_int8; -+typedef signed char yytype_int8; - #endif - - #ifdef YYTYPE_UINT16 -@@ -238,8 +230,7 @@ - # define YYSIZE_T __SIZE_TYPE__ - # elif defined size_t - # define YYSIZE_T size_t --# elif ! defined YYSIZE_T && (defined __STDC__ || defined __C99__FUNC__ \ -- || defined __cplusplus || defined _MSC_VER) -+# elif ! defined YYSIZE_T - # include /* INFRINGES ON USER NAME SPACE */ - # define YYSIZE_T size_t - # else -@@ -261,11 +252,30 @@ - # endif - #endif - --#ifndef __attribute__ --/* This feature is available in gcc versions 2.5 and later. */ --# if (! defined __GNUC__ || __GNUC__ < 2 \ -- || (__GNUC__ == 2 && __GNUC_MINOR__ < 5)) --# define __attribute__(Spec) /* empty */ -+#ifndef YY_ATTRIBUTE -+# if (defined __GNUC__ \ -+ && (2 < __GNUC__ || (__GNUC__ == 2 && 96 <= __GNUC_MINOR__))) \ -+ || defined __SUNPRO_C && 0x5110 <= __SUNPRO_C -+# define YY_ATTRIBUTE(Spec) __attribute__(Spec) -+# else -+# define YY_ATTRIBUTE(Spec) /* empty */ -+# endif -+#endif -+ -+#ifndef YY_ATTRIBUTE_PURE -+# define YY_ATTRIBUTE_PURE YY_ATTRIBUTE ((__pure__)) -+#endif -+ -+#ifndef YY_ATTRIBUTE_UNUSED -+# define YY_ATTRIBUTE_UNUSED YY_ATTRIBUTE ((__unused__)) -+#endif -+ -+#if !defined _Noreturn \ -+ && (!defined __STDC_VERSION__ || __STDC_VERSION__ < 201112) -+# if defined _MSC_VER && 1200 <= _MSC_VER -+# define _Noreturn __declspec (noreturn) -+# else -+# define _Noreturn YY_ATTRIBUTE ((__noreturn__)) - # endif - #endif - -@@ -276,24 +286,25 @@ - # define YYUSE(E) /* empty */ - #endif - -- --/* Identity function, used to suppress warnings about constant conditions. */ --#ifndef lint --# define YYID(N) (N) --#else --#if (defined __STDC__ || defined __C99__FUNC__ \ -- || defined __cplusplus || defined _MSC_VER) --static int --YYID (int yyi) -+#if defined __GNUC__ && 407 <= __GNUC__ * 100 + __GNUC_MINOR__ -+/* Suppress an incorrect diagnostic about yylval being uninitialized. */ -+# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \ -+ _Pragma ("GCC diagnostic push") \ -+ _Pragma ("GCC diagnostic ignored \"-Wuninitialized\"")\ -+ _Pragma ("GCC diagnostic ignored \"-Wmaybe-uninitialized\"") -+# define YY_IGNORE_MAYBE_UNINITIALIZED_END \ -+ _Pragma ("GCC diagnostic pop") - #else --static int --YYID (yyi) -- int yyi; -+# define YY_INITIAL_VALUE(Value) Value - #endif --{ -- return yyi; --} -+#ifndef YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN -+# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN -+# define YY_IGNORE_MAYBE_UNINITIALIZED_END - #endif -+#ifndef YY_INITIAL_VALUE -+# define YY_INITIAL_VALUE(Value) /* Nothing. */ -+#endif -+ - - #if ! defined yyoverflow || YYERROR_VERBOSE - -@@ -312,8 +323,7 @@ - # define alloca _alloca - # else - # define YYSTACK_ALLOC alloca --# if ! defined _ALLOCA_H && ! defined EXIT_SUCCESS && (defined __STDC__ || defined __C99__FUNC__ \ -- || defined __cplusplus || defined _MSC_VER) -+# if ! defined _ALLOCA_H && ! defined EXIT_SUCCESS - # include /* INFRINGES ON USER NAME SPACE */ - /* Use EXIT_SUCCESS as a witness for stdlib.h. */ - # ifndef EXIT_SUCCESS -@@ -325,8 +335,8 @@ - # endif - - # ifdef YYSTACK_ALLOC -- /* Pacify GCC's `empty if-body' warning. */ --# define YYSTACK_FREE(Ptr) do { /* empty */; } while (YYID (0)) -+ /* Pacify GCC's 'empty if-body' warning. */ -+# define YYSTACK_FREE(Ptr) do { /* empty */; } while (0) - # ifndef YYSTACK_ALLOC_MAXIMUM - /* The OS might guarantee only one guard page at the bottom of the stack, - and a page size can be as small as 4096 bytes. So we cannot safely -@@ -342,7 +352,7 @@ - # endif - # if (defined __cplusplus && ! defined EXIT_SUCCESS \ - && ! ((defined YYMALLOC || defined malloc) \ -- && (defined YYFREE || defined free))) -+ && (defined YYFREE || defined free))) - # include /* INFRINGES ON USER NAME SPACE */ - # ifndef EXIT_SUCCESS - # define EXIT_SUCCESS 0 -@@ -350,15 +360,13 @@ - # endif - # ifndef YYMALLOC - # define YYMALLOC malloc --# if ! defined malloc && ! defined EXIT_SUCCESS && (defined __STDC__ || defined __C99__FUNC__ \ -- || defined __cplusplus || defined _MSC_VER) -+# if ! defined malloc && ! defined EXIT_SUCCESS - void *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */ - # endif - # endif - # ifndef YYFREE - # define YYFREE free --# if ! defined free && ! defined EXIT_SUCCESS && (defined __STDC__ || defined __C99__FUNC__ \ -- || defined __cplusplus || defined _MSC_VER) -+# if ! defined free && ! defined EXIT_SUCCESS - void free (void *); /* INFRINGES ON USER NAME SPACE */ - # endif - # endif -@@ -368,13 +376,15 @@ - - #if (! defined yyoverflow \ - && (! defined __cplusplus \ -- || (defined YYSTYPE_IS_TRIVIAL && YYSTYPE_IS_TRIVIAL))) -+ || (defined YYLTYPE_IS_TRIVIAL && YYLTYPE_IS_TRIVIAL \ -+ && defined YYSTYPE_IS_TRIVIAL && YYSTYPE_IS_TRIVIAL))) - - /* A type that is properly aligned for any stack member. */ - union yyalloc - { - yytype_int16 yyss_alloc; - YYSTYPE yyvs_alloc; -+ YYLTYPE yyls_alloc; - }; - - /* The size of the maximum gap between one aligned stack and the next. */ -@@ -383,8 +393,8 @@ - /* The size of an array large to enough to hold all stacks, each with - N elements. */ - # define YYSTACK_BYTES(N) \ -- ((N) * (sizeof (yytype_int16) + sizeof (YYSTYPE)) \ -- + YYSTACK_GAP_MAXIMUM) -+ ((N) * (sizeof (yytype_int16) + sizeof (YYSTYPE) + sizeof (YYLTYPE)) \ -+ + 2 * YYSTACK_GAP_MAXIMUM) - - # define YYCOPY_NEEDED 1 - -@@ -393,16 +403,16 @@ - elements in the stack, and YYPTR gives the new location of the - stack. Advance YYPTR to a properly aligned location for the next - stack. */ --# define YYSTACK_RELOCATE(Stack_alloc, Stack) \ -- do \ -- { \ -- YYSIZE_T yynewbytes; \ -- YYCOPY (&yyptr->Stack_alloc, Stack, yysize); \ -- Stack = &yyptr->Stack_alloc; \ -- yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \ -- yyptr += yynewbytes / sizeof (*yyptr); \ -- } \ -- while (YYID (0)) -+# define YYSTACK_RELOCATE(Stack_alloc, Stack) \ -+ do \ -+ { \ -+ YYSIZE_T yynewbytes; \ -+ YYCOPY (&yyptr->Stack_alloc, Stack, yysize); \ -+ Stack = &yyptr->Stack_alloc; \ -+ yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \ -+ yyptr += yynewbytes / sizeof (*yyptr); \ -+ } \ -+ while (0) - - #endif - -@@ -421,7 +431,7 @@ - for (yyi = 0; yyi < (Count); yyi++) \ - (Dst)[yyi] = (Src)[yyi]; \ - } \ -- while (YYID (0)) -+ while (0) - # endif - # endif - #endif /* !YYCOPY_NEEDED */ -@@ -429,25 +439,27 @@ - /* YYFINAL -- State number of the termination state. */ - #define YYFINAL 4 - /* YYLAST -- Last index in YYTABLE. */ --#define YYLAST 133 -+#define YYLAST 135 - - /* YYNTOKENS -- Number of terminals. */ - #define YYNTOKENS 48 - /* YYNNTS -- Number of nonterminals. */ --#define YYNNTS 28 -+#define YYNNTS 29 - /* YYNRULES -- Number of rules. */ --#define YYNRULES 79 --/* YYNRULES -- Number of states. */ --#define YYNSTATES 141 -+#define YYNRULES 81 -+/* YYNSTATES -- Number of states. */ -+#define YYNSTATES 144 - --/* YYTRANSLATE(YYLEX) -- Bison symbol number corresponding to YYLEX. */ -+/* YYTRANSLATE[YYX] -- Symbol number corresponding to YYX as returned -+ by yylex, with out-of-bounds checking. */ - #define YYUNDEFTOK 2 - #define YYMAXUTOK 279 - --#define YYTRANSLATE(YYX) \ -+#define YYTRANSLATE(YYX) \ - ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK) - --/* YYTRANSLATE[YYLEX] -- Bison symbol number corresponding to YYLEX. */ -+/* YYTRANSLATE[TOKEN-NUM] -- Symbol number corresponding to TOKEN-NUM -+ as returned by yylex, without out-of-bounds checking. */ - static const yytype_uint8 yytranslate[] = - { - 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, -@@ -481,63 +493,18 @@ - }; - - #if YYDEBUG --/* YYPRHS[YYN] -- Index of the first RHS symbol of rule number YYN in -- YYRHS. */ --static const yytype_uint16 yyprhs[] = --{ -- 0, 0, 3, 8, 9, 12, 17, 20, 23, 27, -- 31, 36, 42, 43, 46, 51, 54, 58, 61, 64, -- 68, 73, 76, 86, 92, 95, 96, 99, 102, 106, -- 108, 111, 114, 117, 119, 121, 125, 127, 129, 135, -- 137, 141, 143, 147, 149, 153, 155, 159, 161, 165, -- 167, 171, 175, 177, 181, 185, 189, 193, 197, 201, -- 203, 207, 211, 213, 217, 221, 225, 227, 229, 232, -- 235, 238, 239, 242, 245, 246, 249, 252, 255, 259 --}; -- --/* YYRHS -- A `-1'-separated list of the rules' RHS. */ --static const yytype_int8 yyrhs[] = --{ -- 49, 0, -1, 3, 25, 50, 52, -1, -1, 51, -- 50, -1, 4, 59, 59, 25, -1, 22, 51, -1, -- 26, 53, -1, 52, 26, 53, -1, 52, 23, 53, -- -1, 52, 15, 23, 25, -1, 27, 54, 74, 28, -- 25, -1, -1, 54, 55, -1, 16, 29, 56, 25, -- -1, 16, 25, -1, 14, 16, 25, -1, 22, 55, -- -1, 57, 21, -1, 57, 58, 30, -1, 57, 31, -- 73, 32, -1, 57, 23, -1, 57, 24, 33, 21, -- 34, 59, 34, 59, 35, -1, 57, 24, 33, 21, -- 35, -1, 56, 22, -1, -1, 56, 34, -1, 57, -- 22, -1, 13, 17, 36, -1, 36, -1, 58, 59, -- -1, 58, 23, -1, 58, 22, -1, 17, -1, 18, -- -1, 33, 60, 35, -1, 61, -1, 62, -1, 62, -- 37, 60, 38, 61, -1, 63, -1, 62, 12, 63, -- -1, 64, -1, 63, 11, 64, -1, 65, -1, 64, -- 39, 65, -1, 66, -1, 65, 40, 66, -1, 67, -- -1, 66, 41, 67, -1, 68, -1, 67, 9, 68, -- -1, 67, 10, 68, -1, 69, -1, 68, 36, 69, -- -1, 68, 30, 69, -1, 68, 7, 69, -1, 68, -- 8, 69, -1, 69, 5, 70, -1, 69, 6, 70, -- -1, 70, -1, 70, 42, 71, -1, 70, 43, 71, -- -1, 71, -1, 71, 44, 72, -1, 71, 26, 72, -- -1, 71, 45, 72, -1, 72, -1, 59, -1, 43, -- 72, -1, 46, 72, -1, 47, 72, -1, -1, 73, -- 20, -1, 73, 22, -1, -1, 75, 74, -1, 75, -- 55, -1, 16, 53, -1, 15, 16, 25, -1, 22, -- 75, -1 --}; -- --/* YYRLINE[YYN] -- source line where rule number YYN was defined. */ -+ /* YYRLINE[YYN] -- Source line where rule number YYN was defined. */ - static const yytype_uint16 yyrline[] = - { -- 0, 109, 109, 118, 121, 128, 132, 140, 144, 148, -- 158, 172, 180, 183, 190, 194, 198, 202, 210, 214, -- 218, 222, 226, 243, 253, 261, 264, 268, 275, 290, -- 295, 315, 329, 336, 340, 344, 351, 355, 356, 360, -- 361, 365, 366, 370, 371, 375, 376, 380, 381, 385, -- 386, 387, 391, 392, 393, 394, 395, 399, 400, 401, -- 405, 406, 407, 411, 412, 413, 414, 418, 419, 420, -- 421, 426, 429, 433, 441, 444, 448, 456, 460, 464 -+ 0, 108, 108, 119, 122, 130, 133, 140, 144, 152, -+ 156, 160, 170, 185, 193, 196, 203, 207, 211, 215, -+ 223, 227, 231, 235, 239, 255, 265, 273, 276, 280, -+ 287, 303, 308, 327, 341, 348, 349, 350, 357, 361, -+ 362, 366, 367, 371, 372, 376, 377, 381, 382, 386, -+ 387, 391, 392, 393, 397, 398, 399, 400, 401, 405, -+ 406, 407, 411, 412, 413, 417, 418, 419, 420, 424, -+ 425, 426, 427, 432, 435, 439, 447, 450, 454, 462, -+ 466, 470 - }; - #endif - -@@ -546,25 +513,25 @@ - First, the terminals, then, starting at YYNTOKENS, nonterminals. */ - static const char *const yytname[] = - { -- "$end", "error", "$undefined", "DT_V1", "DT_MEMRESERVE", "DT_LSHIFT", -- "DT_RSHIFT", "DT_LE", "DT_GE", "DT_EQ", "DT_NE", "DT_AND", "DT_OR", -- "DT_BITS", "DT_DEL_PROP", "DT_DEL_NODE", "DT_PROPNODENAME", "DT_LITERAL", -- "DT_CHAR_LITERAL", "DT_BASE", "DT_BYTE", "DT_STRING", "DT_LABEL", -+ "$end", "error", "$undefined", "DT_V1", "DT_PLUGIN", "DT_MEMRESERVE", -+ "DT_LSHIFT", "DT_RSHIFT", "DT_LE", "DT_GE", "DT_EQ", "DT_NE", "DT_AND", -+ "DT_OR", "DT_BITS", "DT_DEL_PROP", "DT_DEL_NODE", "DT_PROPNODENAME", -+ "DT_LITERAL", "DT_CHAR_LITERAL", "DT_BYTE", "DT_STRING", "DT_LABEL", - "DT_REF", "DT_INCBIN", "';'", "'/'", "'{'", "'}'", "'='", "'>'", "'['", - "']'", "'('", "','", "')'", "'<'", "'?'", "':'", "'|'", "'^'", "'&'", - "'+'", "'-'", "'*'", "'%'", "'~'", "'!'", "$accept", "sourcefile", -- "memreserves", "memreserve", "devicetree", "nodedef", "proplist", -- "propdef", "propdata", "propdataprefix", "arrayprefix", "integer_prim", -- "integer_expr", "integer_trinary", "integer_or", "integer_and", -- "integer_bitor", "integer_bitxor", "integer_bitand", "integer_eq", -- "integer_rela", "integer_shift", "integer_add", "integer_mul", -- "integer_unary", "bytestring", "subnodes", "subnode", YY_NULL -+ "plugindecl", "memreserves", "memreserve", "devicetree", "nodedef", -+ "proplist", "propdef", "propdata", "propdataprefix", "arrayprefix", -+ "integer_prim", "integer_expr", "integer_trinary", "integer_or", -+ "integer_and", "integer_bitor", "integer_bitxor", "integer_bitand", -+ "integer_eq", "integer_rela", "integer_shift", "integer_add", -+ "integer_mul", "integer_unary", "bytestring", "subnodes", "subnode", YY_NULLPTR - }; - #endif - - # ifdef YYPRINT --/* YYTOKNUM[YYLEX-NUM] -- Internal token number corresponding to -- token YYLEX-NUM. */ -+/* YYTOKNUM[NUM] -- (External) token number corresponding to the -+ (internal) symbol number NUM (which must be that of a token). */ - static const yytype_uint16 yytoknum[] = - { - 0, 256, 257, 258, 259, 260, 261, 262, 263, 264, -@@ -575,183 +542,173 @@ - }; - # endif - --/* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */ --static const yytype_uint8 yyr1[] = --{ -- 0, 48, 49, 50, 50, 51, 51, 52, 52, 52, -- 52, 53, 54, 54, 55, 55, 55, 55, 56, 56, -- 56, 56, 56, 56, 56, 57, 57, 57, 58, 58, -- 58, 58, 58, 59, 59, 59, 60, 61, 61, 62, -- 62, 63, 63, 64, 64, 65, 65, 66, 66, 67, -- 67, 67, 68, 68, 68, 68, 68, 69, 69, 69, -- 70, 70, 70, 71, 71, 71, 71, 72, 72, 72, -- 72, 73, 73, 73, 74, 74, 74, 75, 75, 75 --}; -+#define YYPACT_NINF -41 - --/* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN. */ --static const yytype_uint8 yyr2[] = -+#define yypact_value_is_default(Yystate) \ -+ (!!((Yystate) == (-41))) -+ -+#define YYTABLE_NINF -1 -+ -+#define yytable_value_is_error(Yytable_value) \ -+ 0 -+ -+ /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing -+ STATE-NUM. */ -+static const yytype_int8 yypact[] = - { -- 0, 2, 4, 0, 2, 4, 2, 2, 3, 3, -- 4, 5, 0, 2, 4, 2, 3, 2, 2, 3, -- 4, 2, 9, 5, 2, 0, 2, 2, 3, 1, -- 2, 2, 2, 1, 1, 3, 1, 1, 5, 1, -- 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, -- 3, 3, 1, 3, 3, 3, 3, 3, 3, 1, -- 3, 3, 1, 3, 3, 3, 1, 1, 2, 2, -- 2, 0, 2, 2, 0, 2, 2, 2, 3, 2 -+ 37, 10, 24, 78, -41, 20, 9, -41, 8, 9, -+ 59, 9, -41, -41, -10, 8, -41, 60, 39, -41, -+ -10, -10, -10, -41, 51, -41, -7, 76, 50, 52, -+ 53, 49, 2, 65, 32, -1, -41, 66, -41, -41, -+ 67, 60, 60, -41, -41, -41, -41, -10, -10, -10, -+ -10, -10, -10, -10, -10, -10, -10, -10, -10, -10, -+ -10, -10, -10, -10, -10, -10, -41, 41, 68, -41, -+ -41, 76, 57, 50, 52, 53, 49, 2, 2, 65, -+ 65, 65, 65, 32, 32, -1, -1, -41, -41, -41, -+ 79, 80, -12, 41, -41, 70, 41, -41, -10, 74, -+ 75, -41, -41, -41, -41, -41, 77, -41, -41, -41, -+ -41, -41, 17, -2, -41, -41, -41, -41, 83, -41, -+ -41, -41, 71, -41, -41, 31, 69, 82, -4, -41, -+ -41, -41, -41, -41, 42, -41, -41, -41, 8, -41, -+ 72, 8, 73, -41 - }; - --/* YYDEFACT[STATE-NAME] -- Default reduction number in state STATE-NUM. -- Performed when YYTABLE doesn't specify something else to do. Zero -- means the default is an error. */ -+ /* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM. -+ Performed when YYTABLE does not specify something else to do. Zero -+ means the default is an error. */ - static const yytype_uint8 yydefact[] = - { -- 0, 0, 0, 3, 1, 0, 0, 0, 3, 33, -- 34, 0, 0, 6, 0, 2, 4, 0, 0, 0, -- 67, 0, 36, 37, 39, 41, 43, 45, 47, 49, -- 52, 59, 62, 66, 0, 12, 7, 0, 0, 0, -- 68, 69, 70, 35, 0, 0, 0, 0, 0, 0, -+ 0, 0, 0, 3, 1, 0, 5, 4, 0, 0, -+ 0, 5, 35, 36, 0, 0, 8, 0, 2, 6, -+ 0, 0, 0, 69, 0, 38, 39, 41, 43, 45, -+ 47, 49, 51, 54, 61, 64, 68, 0, 14, 9, -+ 0, 0, 0, 70, 71, 72, 37, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -- 0, 0, 0, 5, 74, 0, 9, 8, 40, 0, -- 42, 44, 46, 48, 50, 51, 55, 56, 54, 53, -- 57, 58, 60, 61, 64, 63, 65, 0, 0, 0, -- 0, 13, 0, 74, 10, 0, 0, 0, 15, 25, -- 77, 17, 79, 0, 76, 75, 38, 16, 78, 0, -- 0, 11, 24, 14, 26, 0, 18, 27, 21, 0, -- 71, 29, 0, 0, 0, 0, 32, 31, 19, 30, -- 28, 0, 72, 73, 20, 0, 23, 0, 0, 0, -- 22 -+ 0, 0, 0, 0, 0, 0, 7, 76, 0, 11, -+ 10, 42, 0, 44, 46, 48, 50, 52, 53, 57, -+ 58, 56, 55, 59, 60, 62, 63, 66, 65, 67, -+ 0, 0, 0, 0, 15, 0, 76, 12, 0, 0, -+ 0, 17, 27, 79, 19, 81, 0, 78, 77, 40, -+ 18, 80, 0, 0, 13, 26, 16, 28, 0, 20, -+ 29, 23, 0, 73, 31, 0, 0, 0, 0, 34, -+ 33, 21, 32, 30, 0, 74, 75, 22, 0, 25, -+ 0, 0, 0, 24 - }; - --/* YYDEFGOTO[NTERM-NUM]. */ --static const yytype_int8 yydefgoto[] = -+ /* YYPGOTO[NTERM-NUM]. */ -+static const yytype_int8 yypgoto[] = - { -- -1, 2, 7, 8, 15, 36, 64, 91, 109, 110, -- 122, 20, 21, 22, 23, 24, 25, 26, 27, 28, -- 29, 30, 31, 32, 33, 125, 92, 93 -+ -41, -41, -41, 96, 100, -41, -40, -41, -23, -41, -+ -41, -41, -8, 62, 13, -41, 81, 63, 64, 84, -+ 61, 25, 11, 21, 22, -17, -41, 19, 23 - }; - --/* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing -- STATE-NUM. */ --#define YYPACT_NINF -78 --static const yytype_int8 yypact[] = -+ /* YYDEFGOTO[NTERM-NUM]. */ -+static const yytype_int16 yydefgoto[] = - { -- 22, 11, 51, 10, -78, 23, 10, 2, 10, -78, -- -78, -9, 23, -78, 30, 38, -78, -9, -9, -9, -- -78, 35, -78, -6, 52, 29, 48, 49, 33, 3, -- 71, 36, 0, -78, 64, -78, -78, 68, 30, 30, -- -78, -78, -78, -78, -9, -9, -9, -9, -9, -9, -- -9, -9, -9, -9, -9, -9, -9, -9, -9, -9, -- -9, -9, -9, -78, 44, 67, -78, -78, 52, 55, -- 29, 48, 49, 33, 3, 3, 71, 71, 71, 71, -- 36, 36, 0, 0, -78, -78, -78, 78, 79, 42, -- 44, -78, 69, 44, -78, -9, 73, 74, -78, -78, -- -78, -78, -78, 75, -78, -78, -78, -78, -78, -7, -- -1, -78, -78, -78, -78, 84, -78, -78, -78, 63, -- -78, -78, 32, 66, 82, -3, -78, -78, -78, -78, -- -78, 46, -78, -78, -78, 23, -78, 70, 23, 72, -- -78 -+ -1, 2, 6, 10, 11, 18, 39, 67, 94, 112, -+ 113, 125, 23, 24, 25, 26, 27, 28, 29, 30, -+ 31, 32, 33, 34, 35, 36, 128, 95, 96 - }; - --/* YYPGOTO[NTERM-NUM]. */ --static const yytype_int8 yypgoto[] = -+ /* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM. If -+ positive, shift that token. If negative, reduce the rule whose -+ number is the opposite. If YYTABLE_NINF, syntax error. */ -+static const yytype_uint8 yytable[] = - { -- -78, -78, 97, 100, -78, -37, -78, -77, -78, -78, -- -78, -5, 65, 13, -78, 76, 77, 62, 80, 83, -- 34, 20, 26, 28, -14, -78, 18, 24 -+ 15, 69, 70, 43, 44, 45, 47, 37, 12, 13, -+ 55, 56, 118, 101, 8, 38, 135, 102, 136, 119, -+ 120, 121, 122, 14, 4, 63, 12, 13, 137, 123, -+ 48, 9, 57, 20, 124, 3, 21, 22, 58, 115, -+ 1, 14, 116, 64, 65, 7, 87, 88, 89, 12, -+ 13, 117, 103, 129, 130, 40, 90, 91, 92, 53, -+ 54, 131, 41, 93, 14, 42, 79, 80, 81, 82, -+ 104, 59, 60, 107, 61, 62, 138, 139, 77, 78, -+ 83, 84, 5, 85, 86, 17, 46, 38, 49, 50, -+ 68, 66, 51, 97, 52, 98, 99, 100, 106, 110, -+ 111, 126, 114, 134, 127, 133, 141, 19, 143, 16, -+ 72, 109, 73, 76, 74, 108, 105, 132, 0, 0, -+ 0, 0, 0, 0, 0, 0, 0, 0, 71, 0, -+ 140, 0, 0, 142, 0, 75 - }; - --/* YYTABLE[YYPACT[STATE-NUM]]. What to do in state STATE-NUM. If -- positive, shift that token. If negative, reduce the rule which -- number is the opposite. If YYTABLE_NINF, syntax error. */ --#define YYTABLE_NINF -1 --static const yytype_uint8 yytable[] = -+static const yytype_int16 yycheck[] = - { -- 12, 66, 67, 40, 41, 42, 44, 34, 9, 10, -- 52, 53, 115, 101, 5, 112, 104, 132, 113, 133, -- 116, 117, 118, 119, 11, 1, 60, 114, 14, 134, -- 120, 45, 6, 54, 17, 121, 3, 18, 19, 55, -- 9, 10, 50, 51, 61, 62, 84, 85, 86, 9, -- 10, 4, 100, 37, 126, 127, 11, 35, 87, 88, -- 89, 38, 128, 46, 39, 11, 90, 98, 47, 35, -- 43, 99, 76, 77, 78, 79, 56, 57, 58, 59, -- 135, 136, 80, 81, 74, 75, 82, 83, 48, 63, -- 49, 65, 94, 95, 96, 97, 124, 103, 107, 108, -- 111, 123, 130, 131, 138, 16, 13, 140, 106, 71, -- 69, 105, 0, 0, 102, 0, 0, 129, 0, 0, -- 68, 0, 0, 70, 0, 0, 0, 0, 72, 0, -- 137, 0, 73, 139 -+ 8, 41, 42, 20, 21, 22, 13, 15, 18, 19, -+ 8, 9, 14, 25, 5, 27, 20, 29, 22, 21, -+ 22, 23, 24, 33, 0, 26, 18, 19, 32, 31, -+ 37, 22, 30, 43, 36, 25, 46, 47, 36, 22, -+ 3, 33, 25, 44, 45, 25, 63, 64, 65, 18, -+ 19, 34, 92, 22, 23, 16, 15, 16, 17, 10, -+ 11, 30, 23, 22, 33, 26, 55, 56, 57, 58, -+ 93, 6, 7, 96, 42, 43, 34, 35, 53, 54, -+ 59, 60, 4, 61, 62, 26, 35, 27, 12, 39, -+ 23, 25, 40, 25, 41, 38, 17, 17, 28, 25, -+ 25, 18, 25, 21, 33, 36, 34, 11, 35, 9, -+ 48, 98, 49, 52, 50, 96, 93, 125, -1, -1, -+ -1, -1, -1, -1, -1, -1, -1, -1, 47, -1, -+ 138, -1, -1, 141, -1, 51 - }; - --#define yypact_value_is_default(Yystate) \ -- (!!((Yystate) == (-78))) -- --#define yytable_value_is_error(Yytable_value) \ -- YYID (0) -+ /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing -+ symbol of state STATE-NUM. */ -+static const yytype_uint8 yystos[] = -+{ -+ 0, 3, 49, 25, 0, 4, 50, 25, 5, 22, -+ 51, 52, 18, 19, 33, 60, 52, 26, 53, 51, -+ 43, 46, 47, 60, 61, 62, 63, 64, 65, 66, -+ 67, 68, 69, 70, 71, 72, 73, 60, 27, 54, -+ 16, 23, 26, 73, 73, 73, 35, 13, 37, 12, -+ 39, 40, 41, 10, 11, 8, 9, 30, 36, 6, -+ 7, 42, 43, 26, 44, 45, 25, 55, 23, 54, -+ 54, 64, 61, 65, 66, 67, 68, 69, 69, 70, -+ 70, 70, 70, 71, 71, 72, 72, 73, 73, 73, -+ 15, 16, 17, 22, 56, 75, 76, 25, 38, 17, -+ 17, 25, 29, 54, 56, 76, 28, 56, 75, 62, -+ 25, 25, 57, 58, 25, 22, 25, 34, 14, 21, -+ 22, 23, 24, 31, 36, 59, 18, 33, 74, 22, -+ 23, 30, 60, 36, 21, 20, 22, 32, 34, 35, -+ 60, 34, 60, 35 -+}; - --static const yytype_int16 yycheck[] = -+ /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */ -+static const yytype_uint8 yyr1[] = - { -- 5, 38, 39, 17, 18, 19, 12, 12, 17, 18, -- 7, 8, 13, 90, 4, 22, 93, 20, 25, 22, -- 21, 22, 23, 24, 33, 3, 26, 34, 26, 32, -- 31, 37, 22, 30, 43, 36, 25, 46, 47, 36, -- 17, 18, 9, 10, 44, 45, 60, 61, 62, 17, -- 18, 0, 89, 15, 22, 23, 33, 27, 14, 15, -- 16, 23, 30, 11, 26, 33, 22, 25, 39, 27, -- 35, 29, 52, 53, 54, 55, 5, 6, 42, 43, -- 34, 35, 56, 57, 50, 51, 58, 59, 40, 25, -- 41, 23, 25, 38, 16, 16, 33, 28, 25, 25, -- 25, 17, 36, 21, 34, 8, 6, 35, 95, 47, -- 45, 93, -1, -1, 90, -1, -1, 122, -1, -1, -- 44, -1, -1, 46, -1, -1, -1, -1, 48, -1, -- 135, -1, 49, 138 -+ 0, 48, 49, 50, 50, 51, 51, 52, 52, 53, -+ 53, 53, 53, 54, 55, 55, 56, 56, 56, 56, -+ 57, 57, 57, 57, 57, 57, 57, 58, 58, 58, -+ 59, 59, 59, 59, 59, 60, 60, 60, 61, 62, -+ 62, 63, 63, 64, 64, 65, 65, 66, 66, 67, -+ 67, 68, 68, 68, 69, 69, 69, 69, 69, 70, -+ 70, 70, 71, 71, 71, 72, 72, 72, 72, 73, -+ 73, 73, 73, 74, 74, 74, 75, 75, 75, 76, -+ 76, 76 - }; - --/* YYSTOS[STATE-NUM] -- The (internal number of the) accessing -- symbol of state STATE-NUM. */ --static const yytype_uint8 yystos[] = -+ /* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN. */ -+static const yytype_uint8 yyr2[] = - { -- 0, 3, 49, 25, 0, 4, 22, 50, 51, 17, -- 18, 33, 59, 51, 26, 52, 50, 43, 46, 47, -- 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, -- 69, 70, 71, 72, 59, 27, 53, 15, 23, 26, -- 72, 72, 72, 35, 12, 37, 11, 39, 40, 41, -- 9, 10, 7, 8, 30, 36, 5, 6, 42, 43, -- 26, 44, 45, 25, 54, 23, 53, 53, 63, 60, -- 64, 65, 66, 67, 68, 68, 69, 69, 69, 69, -- 70, 70, 71, 71, 72, 72, 72, 14, 15, 16, -- 22, 55, 74, 75, 25, 38, 16, 16, 25, 29, -- 53, 55, 75, 28, 55, 74, 61, 25, 25, 56, -- 57, 25, 22, 25, 34, 13, 21, 22, 23, 24, -- 31, 36, 58, 17, 33, 73, 22, 23, 30, 59, -- 36, 21, 20, 22, 32, 34, 35, 59, 34, 59, -- 35 -+ 0, 2, 5, 0, 2, 0, 2, 4, 2, 2, -+ 3, 3, 4, 5, 0, 2, 4, 2, 3, 2, -+ 2, 3, 4, 2, 9, 5, 2, 0, 2, 2, -+ 3, 1, 2, 2, 2, 1, 1, 3, 1, 1, -+ 5, 1, 3, 1, 3, 1, 3, 1, 3, 1, -+ 3, 1, 3, 3, 1, 3, 3, 3, 3, 3, -+ 3, 1, 3, 3, 1, 3, 3, 3, 1, 1, -+ 2, 2, 2, 0, 2, 2, 0, 2, 2, 2, -+ 3, 2 - }; - --#define yyerrok (yyerrstatus = 0) --#define yyclearin (yychar = YYEMPTY) --#define YYEMPTY (-2) --#define YYEOF 0 -- --#define YYACCEPT goto yyacceptlab --#define YYABORT goto yyabortlab --#define YYERROR goto yyerrorlab -- -- --/* Like YYERROR except do call yyerror. This remains here temporarily -- to ease the transition to the new meaning of YYERROR, for GCC. -- Once GCC version 2 has supplanted version 1, this can go. However, -- YYFAIL appears to be in use. Nevertheless, it is formally deprecated -- in Bison 2.4.2's NEWS entry, where a plan to phase it out is -- discussed. */ -- --#define YYFAIL goto yyerrlab --#if defined YYFAIL -- /* This is here to suppress warnings from the GCC cpp's -- -Wunused-macros. Normally we don't worry about that warning, but -- some users do, and we want to make it easy for users to remove -- YYFAIL uses, which will produce warnings from Bison 2.5. */ --#endif -+ -+#define yyerrok (yyerrstatus = 0) -+#define yyclearin (yychar = YYEMPTY) -+#define YYEMPTY (-2) -+#define YYEOF 0 -+ -+#define YYACCEPT goto yyacceptlab -+#define YYABORT goto yyabortlab -+#define YYERROR goto yyerrorlab -+ - - #define YYRECOVERING() (!!yyerrstatus) - -@@ -768,27 +725,41 @@ - else \ - { \ - yyerror (YY_("syntax error: cannot back up")); \ -- YYERROR; \ -- } \ --while (YYID (0)) -+ YYERROR; \ -+ } \ -+while (0) - - /* Error token number */ --#define YYTERROR 1 --#define YYERRCODE 256 -+#define YYTERROR 1 -+#define YYERRCODE 256 - - --/* This macro is provided for backward compatibility. */ --#ifndef YY_LOCATION_PRINT --# define YY_LOCATION_PRINT(File, Loc) ((void) 0) -+/* YYLLOC_DEFAULT -- Set CURRENT to span from RHS[1] to RHS[N]. -+ If N is 0, then set CURRENT to the empty location which ends -+ the previous symbol: RHS[0] (always defined). */ -+ -+#ifndef YYLLOC_DEFAULT -+# define YYLLOC_DEFAULT(Current, Rhs, N) \ -+ do \ -+ if (N) \ -+ { \ -+ (Current).first_line = YYRHSLOC (Rhs, 1).first_line; \ -+ (Current).first_column = YYRHSLOC (Rhs, 1).first_column; \ -+ (Current).last_line = YYRHSLOC (Rhs, N).last_line; \ -+ (Current).last_column = YYRHSLOC (Rhs, N).last_column; \ -+ } \ -+ else \ -+ { \ -+ (Current).first_line = (Current).last_line = \ -+ YYRHSLOC (Rhs, 0).last_line; \ -+ (Current).first_column = (Current).last_column = \ -+ YYRHSLOC (Rhs, 0).last_column; \ -+ } \ -+ while (0) - #endif - -+#define YYRHSLOC(Rhs, K) ((Rhs)[K]) - --/* YYLEX -- calling `yylex' with the right arguments. */ --#ifdef YYLEX_PARAM --# define YYLEX yylex (YYLEX_PARAM) --#else --# define YYLEX yylex () --#endif - - /* Enable debugging if requested. */ - #if YYDEBUG -@@ -798,50 +769,84 @@ - # define YYFPRINTF fprintf - # endif - --# define YYDPRINTF(Args) \ --do { \ -- if (yydebug) \ -- YYFPRINTF Args; \ --} while (YYID (0)) -- --# define YY_SYMBOL_PRINT(Title, Type, Value, Location) \ --do { \ -- if (yydebug) \ -- { \ -- YYFPRINTF (stderr, "%s ", Title); \ -- yy_symbol_print (stderr, \ -- Type, Value); \ -- YYFPRINTF (stderr, "\n"); \ -- } \ --} while (YYID (0)) -+# define YYDPRINTF(Args) \ -+do { \ -+ if (yydebug) \ -+ YYFPRINTF Args; \ -+} while (0) - - --/*--------------------------------. --| Print this symbol on YYOUTPUT. | --`--------------------------------*/ -+/* YY_LOCATION_PRINT -- Print the location on the stream. -+ This macro was not mandated originally: define only if we know -+ we won't break user code: when these are the locations we know. */ - --/*ARGSUSED*/ --#if (defined __STDC__ || defined __C99__FUNC__ \ -- || defined __cplusplus || defined _MSC_VER) --static void --yy_symbol_value_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep) --#else --static void --yy_symbol_value_print (yyoutput, yytype, yyvaluep) -- FILE *yyoutput; -- int yytype; -- YYSTYPE const * const yyvaluep; -+#ifndef YY_LOCATION_PRINT -+# if defined YYLTYPE_IS_TRIVIAL && YYLTYPE_IS_TRIVIAL -+ -+/* Print *YYLOCP on YYO. Private, do not rely on its existence. */ -+ -+YY_ATTRIBUTE_UNUSED -+static unsigned -+yy_location_print_ (FILE *yyo, YYLTYPE const * const yylocp) -+{ -+ unsigned res = 0; -+ int end_col = 0 != yylocp->last_column ? yylocp->last_column - 1 : 0; -+ if (0 <= yylocp->first_line) -+ { -+ res += YYFPRINTF (yyo, "%d", yylocp->first_line); -+ if (0 <= yylocp->first_column) -+ res += YYFPRINTF (yyo, ".%d", yylocp->first_column); -+ } -+ if (0 <= yylocp->last_line) -+ { -+ if (yylocp->first_line < yylocp->last_line) -+ { -+ res += YYFPRINTF (yyo, "-%d", yylocp->last_line); -+ if (0 <= end_col) -+ res += YYFPRINTF (yyo, ".%d", end_col); -+ } -+ else if (0 <= end_col && yylocp->first_column < end_col) -+ res += YYFPRINTF (yyo, "-%d", end_col); -+ } -+ return res; -+ } -+ -+# define YY_LOCATION_PRINT(File, Loc) \ -+ yy_location_print_ (File, &(Loc)) -+ -+# else -+# define YY_LOCATION_PRINT(File, Loc) ((void) 0) -+# endif - #endif -+ -+ -+# define YY_SYMBOL_PRINT(Title, Type, Value, Location) \ -+do { \ -+ if (yydebug) \ -+ { \ -+ YYFPRINTF (stderr, "%s ", Title); \ -+ yy_symbol_print (stderr, \ -+ Type, Value, Location); \ -+ YYFPRINTF (stderr, "\n"); \ -+ } \ -+} while (0) -+ -+ -+/*----------------------------------------. -+| Print this symbol's value on YYOUTPUT. | -+`----------------------------------------*/ -+ -+static void -+yy_symbol_value_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep, YYLTYPE const * const yylocationp) - { - FILE *yyo = yyoutput; - YYUSE (yyo); -+ YYUSE (yylocationp); - if (!yyvaluep) - return; - # ifdef YYPRINT - if (yytype < YYNTOKENS) - YYPRINT (yyoutput, yytoknum[yytype], *yyvaluep); --# else -- YYUSE (yyoutput); - # endif - YYUSE (yytype); - } -@@ -851,24 +856,15 @@ - | Print this symbol on YYOUTPUT. | - `--------------------------------*/ - --#if (defined __STDC__ || defined __C99__FUNC__ \ -- || defined __cplusplus || defined _MSC_VER) --static void --yy_symbol_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep) --#else - static void --yy_symbol_print (yyoutput, yytype, yyvaluep) -- FILE *yyoutput; -- int yytype; -- YYSTYPE const * const yyvaluep; --#endif -+yy_symbol_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep, YYLTYPE const * const yylocationp) - { -- if (yytype < YYNTOKENS) -- YYFPRINTF (yyoutput, "token %s (", yytname[yytype]); -- else -- YYFPRINTF (yyoutput, "nterm %s (", yytname[yytype]); -+ YYFPRINTF (yyoutput, "%s %s (", -+ yytype < YYNTOKENS ? "token" : "nterm", yytname[yytype]); - -- yy_symbol_value_print (yyoutput, yytype, yyvaluep); -+ YY_LOCATION_PRINT (yyoutput, *yylocationp); -+ YYFPRINTF (yyoutput, ": "); -+ yy_symbol_value_print (yyoutput, yytype, yyvaluep, yylocationp); - YYFPRINTF (yyoutput, ")"); - } - -@@ -877,16 +873,8 @@ - | TOP (included). | - `------------------------------------------------------------------*/ - --#if (defined __STDC__ || defined __C99__FUNC__ \ -- || defined __cplusplus || defined _MSC_VER) - static void - yy_stack_print (yytype_int16 *yybottom, yytype_int16 *yytop) --#else --static void --yy_stack_print (yybottom, yytop) -- yytype_int16 *yybottom; -- yytype_int16 *yytop; --#endif - { - YYFPRINTF (stderr, "Stack now"); - for (; yybottom <= yytop; yybottom++) -@@ -897,49 +885,42 @@ - YYFPRINTF (stderr, "\n"); - } - --# define YY_STACK_PRINT(Bottom, Top) \ --do { \ -- if (yydebug) \ -- yy_stack_print ((Bottom), (Top)); \ --} while (YYID (0)) -+# define YY_STACK_PRINT(Bottom, Top) \ -+do { \ -+ if (yydebug) \ -+ yy_stack_print ((Bottom), (Top)); \ -+} while (0) - - - /*------------------------------------------------. - | Report that the YYRULE is going to be reduced. | - `------------------------------------------------*/ - --#if (defined __STDC__ || defined __C99__FUNC__ \ -- || defined __cplusplus || defined _MSC_VER) --static void --yy_reduce_print (YYSTYPE *yyvsp, int yyrule) --#else - static void --yy_reduce_print (yyvsp, yyrule) -- YYSTYPE *yyvsp; -- int yyrule; --#endif -+yy_reduce_print (yytype_int16 *yyssp, YYSTYPE *yyvsp, YYLTYPE *yylsp, int yyrule) - { -+ unsigned long int yylno = yyrline[yyrule]; - int yynrhs = yyr2[yyrule]; - int yyi; -- unsigned long int yylno = yyrline[yyrule]; - YYFPRINTF (stderr, "Reducing stack by rule %d (line %lu):\n", -- yyrule - 1, yylno); -+ yyrule - 1, yylno); - /* The symbols being reduced. */ - for (yyi = 0; yyi < yynrhs; yyi++) - { - YYFPRINTF (stderr, " $%d = ", yyi + 1); -- yy_symbol_print (stderr, yyrhs[yyprhs[yyrule] + yyi], -- &(yyvsp[(yyi + 1) - (yynrhs)]) -- ); -+ yy_symbol_print (stderr, -+ yystos[yyssp[yyi + 1 - yynrhs]], -+ &(yyvsp[(yyi + 1) - (yynrhs)]) -+ , &(yylsp[(yyi + 1) - (yynrhs)]) ); - YYFPRINTF (stderr, "\n"); - } - } - --# define YY_REDUCE_PRINT(Rule) \ --do { \ -- if (yydebug) \ -- yy_reduce_print (yyvsp, Rule); \ --} while (YYID (0)) -+# define YY_REDUCE_PRINT(Rule) \ -+do { \ -+ if (yydebug) \ -+ yy_reduce_print (yyssp, yyvsp, yylsp, Rule); \ -+} while (0) - - /* Nonzero means print parse trace. It is left uninitialized so that - multiple parsers can coexist. */ -@@ -953,7 +934,7 @@ - - - /* YYINITDEPTH -- initial size of the parser's stacks. */ --#ifndef YYINITDEPTH -+#ifndef YYINITDEPTH - # define YYINITDEPTH 200 - #endif - -@@ -976,15 +957,8 @@ - # define yystrlen strlen - # else - /* Return the length of YYSTR. */ --#if (defined __STDC__ || defined __C99__FUNC__ \ -- || defined __cplusplus || defined _MSC_VER) - static YYSIZE_T - yystrlen (const char *yystr) --#else --static YYSIZE_T --yystrlen (yystr) -- const char *yystr; --#endif - { - YYSIZE_T yylen; - for (yylen = 0; yystr[yylen]; yylen++) -@@ -1000,16 +974,8 @@ - # else - /* Copy YYSRC to YYDEST, returning the address of the terminating '\0' in - YYDEST. */ --#if (defined __STDC__ || defined __C99__FUNC__ \ -- || defined __cplusplus || defined _MSC_VER) - static char * - yystpcpy (char *yydest, const char *yysrc) --#else --static char * --yystpcpy (yydest, yysrc) -- char *yydest; -- const char *yysrc; --#endif - { - char *yyd = yydest; - const char *yys = yysrc; -@@ -1039,27 +1005,27 @@ - char const *yyp = yystr; - - for (;;) -- switch (*++yyp) -- { -- case '\'': -- case ',': -- goto do_not_strip_quotes; -- -- case '\\': -- if (*++yyp != '\\') -- goto do_not_strip_quotes; -- /* Fall through. */ -- default: -- if (yyres) -- yyres[yyn] = *yyp; -- yyn++; -- break; -- -- case '"': -- if (yyres) -- yyres[yyn] = '\0'; -- return yyn; -- } -+ switch (*++yyp) -+ { -+ case '\'': -+ case ',': -+ goto do_not_strip_quotes; -+ -+ case '\\': -+ if (*++yyp != '\\') -+ goto do_not_strip_quotes; -+ /* Fall through. */ -+ default: -+ if (yyres) -+ yyres[yyn] = *yyp; -+ yyn++; -+ break; -+ -+ case '"': -+ if (yyres) -+ yyres[yyn] = '\0'; -+ return yyn; -+ } - do_not_strip_quotes: ; - } - -@@ -1082,11 +1048,11 @@ - yysyntax_error (YYSIZE_T *yymsg_alloc, char **yymsg, - yytype_int16 *yyssp, int yytoken) - { -- YYSIZE_T yysize0 = yytnamerr (YY_NULL, yytname[yytoken]); -+ YYSIZE_T yysize0 = yytnamerr (YY_NULLPTR, yytname[yytoken]); - YYSIZE_T yysize = yysize0; - enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 }; - /* Internationalized format string. */ -- const char *yyformat = YY_NULL; -+ const char *yyformat = YY_NULLPTR; - /* Arguments of yyformat. */ - char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM]; - /* Number of reported tokens (one for the "unexpected", one per -@@ -1094,10 +1060,6 @@ - int yycount = 0; - - /* There are many possibilities here to consider: -- - Assume YYFAIL is not used. It's too flawed to consider. See -- -- for details. YYERROR is fine as it does not invoke this -- function. - - If this state is a consistent state with a default action, then - the only way this function was invoked is if the default action - is an error action. In that case, don't check for expected -@@ -1147,7 +1109,7 @@ - } - yyarg[yycount++] = yytname[yyx]; - { -- YYSIZE_T yysize1 = yysize + yytnamerr (YY_NULL, yytname[yyx]); -+ YYSIZE_T yysize1 = yysize + yytnamerr (YY_NULLPTR, yytname[yyx]); - if (! (yysize <= yysize1 - && yysize1 <= YYSTACK_ALLOC_MAXIMUM)) - return 2; -@@ -1214,26 +1176,18 @@ - | Release the memory associated to this symbol. | - `-----------------------------------------------*/ - --/*ARGSUSED*/ --#if (defined __STDC__ || defined __C99__FUNC__ \ -- || defined __cplusplus || defined _MSC_VER) --static void --yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep) --#else - static void --yydestruct (yymsg, yytype, yyvaluep) -- const char *yymsg; -- int yytype; -- YYSTYPE *yyvaluep; --#endif -+yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep, YYLTYPE *yylocationp) - { - YYUSE (yyvaluep); -- -+ YYUSE (yylocationp); - if (!yymsg) - yymsg = "Deleting"; - YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp); - -+ YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN - YYUSE (yytype); -+ YY_IGNORE_MAYBE_UNINITIALIZED_END - } - - -@@ -1242,18 +1196,14 @@ - /* The lookahead symbol. */ - int yychar; - -- --#ifndef YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN --# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN --# define YY_IGNORE_MAYBE_UNINITIALIZED_END --#endif --#ifndef YY_INITIAL_VALUE --# define YY_INITIAL_VALUE(Value) /* Nothing. */ --#endif -- - /* The semantic value of the lookahead symbol. */ --YYSTYPE yylval YY_INITIAL_VALUE(yyval_default); -- -+YYSTYPE yylval; -+/* Location data for the lookahead symbol. */ -+YYLTYPE yylloc -+# if defined YYLTYPE_IS_TRIVIAL && YYLTYPE_IS_TRIVIAL -+ = { 1, 1, 1, 1 } -+# endif -+; - /* Number of syntax errors so far. */ - int yynerrs; - -@@ -1262,35 +1212,17 @@ - | yyparse. | - `----------*/ - --#ifdef YYPARSE_PARAM --#if (defined __STDC__ || defined __C99__FUNC__ \ -- || defined __cplusplus || defined _MSC_VER) --int --yyparse (void *YYPARSE_PARAM) --#else --int --yyparse (YYPARSE_PARAM) -- void *YYPARSE_PARAM; --#endif --#else /* ! YYPARSE_PARAM */ --#if (defined __STDC__ || defined __C99__FUNC__ \ -- || defined __cplusplus || defined _MSC_VER) - int - yyparse (void) --#else --int --yyparse () -- --#endif --#endif - { - int yystate; - /* Number of tokens to shift before error messages enabled. */ - int yyerrstatus; - - /* The stacks and their tools: -- `yyss': related to states. -- `yyvs': related to semantic values. -+ 'yyss': related to states. -+ 'yyvs': related to semantic values. -+ 'yyls': related to locations. - - Refer to the stacks through separate pointers, to allow yyoverflow - to reallocate them elsewhere. */ -@@ -1305,6 +1237,14 @@ - YYSTYPE *yyvs; - YYSTYPE *yyvsp; - -+ /* The location stack. */ -+ YYLTYPE yylsa[YYINITDEPTH]; -+ YYLTYPE *yyls; -+ YYLTYPE *yylsp; -+ -+ /* The locations where the error started and ended. */ -+ YYLTYPE yyerror_range[3]; -+ - YYSIZE_T yystacksize; - - int yyn; -@@ -1314,6 +1254,7 @@ - /* The variables used to return semantic value and location from the - action routines. */ - YYSTYPE yyval; -+ YYLTYPE yyloc; - - #if YYERROR_VERBOSE - /* Buffer for error messages, and its allocated size. */ -@@ -1322,7 +1263,7 @@ - YYSIZE_T yymsg_alloc = sizeof yymsgbuf; - #endif - --#define YYPOPSTACK(N) (yyvsp -= (N), yyssp -= (N)) -+#define YYPOPSTACK(N) (yyvsp -= (N), yyssp -= (N), yylsp -= (N)) - - /* The number of symbols on the RHS of the reduced rule. - Keep to zero when no symbol should be popped. */ -@@ -1330,6 +1271,7 @@ - - yyssp = yyss = yyssa; - yyvsp = yyvs = yyvsa; -+ yylsp = yyls = yylsa; - yystacksize = YYINITDEPTH; - - YYDPRINTF ((stderr, "Starting parse\n")); -@@ -1338,6 +1280,7 @@ - yyerrstatus = 0; - yynerrs = 0; - yychar = YYEMPTY; /* Cause a token to be read. */ -+ yylsp[0] = yylloc; - goto yysetstate; - - /*------------------------------------------------------------. -@@ -1358,23 +1301,26 @@ - - #ifdef yyoverflow - { -- /* Give user a chance to reallocate the stack. Use copies of -- these so that the &'s don't force the real ones into -- memory. */ -- YYSTYPE *yyvs1 = yyvs; -- yytype_int16 *yyss1 = yyss; -- -- /* Each stack pointer address is followed by the size of the -- data in use in that stack, in bytes. This used to be a -- conditional around just the two extra args, but that might -- be undefined if yyoverflow is a macro. */ -- yyoverflow (YY_("memory exhausted"), -- &yyss1, yysize * sizeof (*yyssp), -- &yyvs1, yysize * sizeof (*yyvsp), -- &yystacksize); -- -- yyss = yyss1; -- yyvs = yyvs1; -+ /* Give user a chance to reallocate the stack. Use copies of -+ these so that the &'s don't force the real ones into -+ memory. */ -+ YYSTYPE *yyvs1 = yyvs; -+ yytype_int16 *yyss1 = yyss; -+ YYLTYPE *yyls1 = yyls; -+ -+ /* Each stack pointer address is followed by the size of the -+ data in use in that stack, in bytes. This used to be a -+ conditional around just the two extra args, but that might -+ be undefined if yyoverflow is a macro. */ -+ yyoverflow (YY_("memory exhausted"), -+ &yyss1, yysize * sizeof (*yyssp), -+ &yyvs1, yysize * sizeof (*yyvsp), -+ &yyls1, yysize * sizeof (*yylsp), -+ &yystacksize); -+ -+ yyls = yyls1; -+ yyss = yyss1; -+ yyvs = yyvs1; - } - #else /* no yyoverflow */ - # ifndef YYSTACK_RELOCATE -@@ -1382,34 +1328,36 @@ - # else - /* Extend the stack our own way. */ - if (YYMAXDEPTH <= yystacksize) -- goto yyexhaustedlab; -+ goto yyexhaustedlab; - yystacksize *= 2; - if (YYMAXDEPTH < yystacksize) -- yystacksize = YYMAXDEPTH; -+ yystacksize = YYMAXDEPTH; - - { -- yytype_int16 *yyss1 = yyss; -- union yyalloc *yyptr = -- (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize)); -- if (! yyptr) -- goto yyexhaustedlab; -- YYSTACK_RELOCATE (yyss_alloc, yyss); -- YYSTACK_RELOCATE (yyvs_alloc, yyvs); -+ yytype_int16 *yyss1 = yyss; -+ union yyalloc *yyptr = -+ (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize)); -+ if (! yyptr) -+ goto yyexhaustedlab; -+ YYSTACK_RELOCATE (yyss_alloc, yyss); -+ YYSTACK_RELOCATE (yyvs_alloc, yyvs); -+ YYSTACK_RELOCATE (yyls_alloc, yyls); - # undef YYSTACK_RELOCATE -- if (yyss1 != yyssa) -- YYSTACK_FREE (yyss1); -+ if (yyss1 != yyssa) -+ YYSTACK_FREE (yyss1); - } - # endif - #endif /* no yyoverflow */ - - yyssp = yyss + yysize - 1; - yyvsp = yyvs + yysize - 1; -+ yylsp = yyls + yysize - 1; - - YYDPRINTF ((stderr, "Stack size increased to %lu\n", -- (unsigned long int) yystacksize)); -+ (unsigned long int) yystacksize)); - - if (yyss + yystacksize - 1 <= yyssp) -- YYABORT; -+ YYABORT; - } - - YYDPRINTF ((stderr, "Entering state %d\n", yystate)); -@@ -1438,7 +1386,7 @@ - if (yychar == YYEMPTY) - { - YYDPRINTF ((stderr, "Reading a token: ")); -- yychar = YYLEX; -+ yychar = yylex (); - } - - if (yychar <= YYEOF) -@@ -1481,7 +1429,7 @@ - YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN - *++yyvsp = yylval; - YY_IGNORE_MAYBE_UNINITIALIZED_END -- -+ *++yylsp = yylloc; - goto yynewstate; - - -@@ -1503,7 +1451,7 @@ - yylen = yyr2[yyn]; - - /* If YYLEN is nonzero, implement the default value of the action: -- `$$ = $1'. -+ '$$ = $1'. - - Otherwise, the following line sets YYVAL to garbage. - This behavior is undocumented and Bison -@@ -1512,287 +1460,306 @@ - GCC warning that YYVAL may be used uninitialized. */ - yyval = yyvsp[1-yylen]; - -- -+ /* Default location. */ -+ YYLLOC_DEFAULT (yyloc, (yylsp - yylen), yylen); - YY_REDUCE_PRINT (yyn); - switch (yyn) - { - case 2: --/* Line 1787 of yacc.c */ --#line 110 "dtc-parser.y" -+#line 109 "dtc-parser.y" /* yacc.c:1646 */ - { -- the_boot_info = build_boot_info((yyvsp[(3) - (4)].re), (yyvsp[(4) - (4)].node), -- guess_boot_cpuid((yyvsp[(4) - (4)].node))); -+ (yyvsp[0].node)->is_plugin = (yyvsp[-2].is_plugin); -+ (yyvsp[0].node)->is_root = 1; -+ the_boot_info = build_boot_info((yyvsp[-1].re), (yyvsp[0].node), -+ guess_boot_cpuid((yyvsp[0].node))); - } -+#line 1477 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 3: --/* Line 1787 of yacc.c */ --#line 118 "dtc-parser.y" -+#line 119 "dtc-parser.y" /* yacc.c:1646 */ - { -- (yyval.re) = NULL; -+ (yyval.is_plugin) = 0; - } -+#line 1485 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 4: --/* Line 1787 of yacc.c */ --#line 122 "dtc-parser.y" -+#line 123 "dtc-parser.y" /* yacc.c:1646 */ - { -- (yyval.re) = chain_reserve_entry((yyvsp[(1) - (2)].re), (yyvsp[(2) - (2)].re)); -+ (yyval.is_plugin) = 1; - } -+#line 1493 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 5: --/* Line 1787 of yacc.c */ --#line 129 "dtc-parser.y" -+#line 130 "dtc-parser.y" /* yacc.c:1646 */ - { -- (yyval.re) = build_reserve_entry((yyvsp[(2) - (4)].integer), (yyvsp[(3) - (4)].integer)); -+ (yyval.re) = NULL; - } -+#line 1501 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 6: --/* Line 1787 of yacc.c */ --#line 133 "dtc-parser.y" -+#line 134 "dtc-parser.y" /* yacc.c:1646 */ - { -- add_label(&(yyvsp[(2) - (2)].re)->labels, (yyvsp[(1) - (2)].labelref)); -- (yyval.re) = (yyvsp[(2) - (2)].re); -+ (yyval.re) = chain_reserve_entry((yyvsp[-1].re), (yyvsp[0].re)); - } -+#line 1509 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 7: --/* Line 1787 of yacc.c */ --#line 141 "dtc-parser.y" -+#line 141 "dtc-parser.y" /* yacc.c:1646 */ - { -- (yyval.node) = name_node((yyvsp[(2) - (2)].node), ""); -+ (yyval.re) = build_reserve_entry((yyvsp[-2].integer), (yyvsp[-1].integer)); - } -+#line 1517 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 8: --/* Line 1787 of yacc.c */ --#line 145 "dtc-parser.y" -+#line 145 "dtc-parser.y" /* yacc.c:1646 */ - { -- (yyval.node) = merge_nodes((yyvsp[(1) - (3)].node), (yyvsp[(3) - (3)].node)); -+ add_label(&(yyvsp[0].re)->labels, (yyvsp[-1].labelref)); -+ (yyval.re) = (yyvsp[0].re); - } -+#line 1526 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 9: --/* Line 1787 of yacc.c */ --#line 149 "dtc-parser.y" -+#line 153 "dtc-parser.y" /* yacc.c:1646 */ - { -- struct node *target = get_node_by_ref((yyvsp[(1) - (3)].node), (yyvsp[(2) - (3)].labelref)); -- -- if (target) -- merge_nodes(target, (yyvsp[(3) - (3)].node)); -- else -- print_error("label or path, '%s', not found", (yyvsp[(2) - (3)].labelref)); -- (yyval.node) = (yyvsp[(1) - (3)].node); -+ (yyval.node) = name_node((yyvsp[0].node), ""); - } -+#line 1534 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 10: --/* Line 1787 of yacc.c */ --#line 159 "dtc-parser.y" -+#line 157 "dtc-parser.y" /* yacc.c:1646 */ - { -- struct node *target = get_node_by_ref((yyvsp[(1) - (4)].node), (yyvsp[(3) - (4)].labelref)); -- -- if (!target) -- print_error("label or path, '%s', not found", (yyvsp[(3) - (4)].labelref)); -- else -- delete_node(target); -- -- (yyval.node) = (yyvsp[(1) - (4)].node); -+ (yyval.node) = merge_nodes((yyvsp[-2].node), (yyvsp[0].node)); - } -+#line 1542 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 11: --/* Line 1787 of yacc.c */ --#line 173 "dtc-parser.y" -+#line 161 "dtc-parser.y" /* yacc.c:1646 */ - { -- (yyval.node) = build_node((yyvsp[(2) - (5)].proplist), (yyvsp[(3) - (5)].nodelist)); -+ struct node *target = get_node_by_ref((yyvsp[-2].node), (yyvsp[-1].labelref)); -+ -+ if (target) -+ merge_nodes(target, (yyvsp[0].node)); -+ else -+ ERROR(&(yylsp[-1]), "Label or path %s not found", (yyvsp[-1].labelref)); -+ (yyval.node) = (yyvsp[-2].node); - } -+#line 1556 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 12: --/* Line 1787 of yacc.c */ --#line 180 "dtc-parser.y" -+#line 171 "dtc-parser.y" /* yacc.c:1646 */ - { -- (yyval.proplist) = NULL; -+ struct node *target = get_node_by_ref((yyvsp[-3].node), (yyvsp[-1].labelref)); -+ -+ if (target) -+ delete_node(target); -+ else -+ ERROR(&(yylsp[-1]), "Label or path %s not found", (yyvsp[-1].labelref)); -+ -+ -+ (yyval.node) = (yyvsp[-3].node); - } -+#line 1572 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 13: --/* Line 1787 of yacc.c */ --#line 184 "dtc-parser.y" -+#line 186 "dtc-parser.y" /* yacc.c:1646 */ - { -- (yyval.proplist) = chain_property((yyvsp[(2) - (2)].prop), (yyvsp[(1) - (2)].proplist)); -+ (yyval.node) = build_node((yyvsp[-3].proplist), (yyvsp[-2].nodelist)); - } -+#line 1580 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 14: --/* Line 1787 of yacc.c */ --#line 191 "dtc-parser.y" -+#line 193 "dtc-parser.y" /* yacc.c:1646 */ - { -- (yyval.prop) = build_property((yyvsp[(1) - (4)].propnodename), (yyvsp[(3) - (4)].data)); -+ (yyval.proplist) = NULL; - } -+#line 1588 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 15: --/* Line 1787 of yacc.c */ --#line 195 "dtc-parser.y" -+#line 197 "dtc-parser.y" /* yacc.c:1646 */ - { -- (yyval.prop) = build_property((yyvsp[(1) - (2)].propnodename), empty_data); -+ (yyval.proplist) = chain_property((yyvsp[0].prop), (yyvsp[-1].proplist)); - } -+#line 1596 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 16: --/* Line 1787 of yacc.c */ --#line 199 "dtc-parser.y" -+#line 204 "dtc-parser.y" /* yacc.c:1646 */ - { -- (yyval.prop) = build_property_delete((yyvsp[(2) - (3)].propnodename)); -+ (yyval.prop) = build_property((yyvsp[-3].propnodename), (yyvsp[-1].data)); - } -+#line 1604 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 17: --/* Line 1787 of yacc.c */ --#line 203 "dtc-parser.y" -+#line 208 "dtc-parser.y" /* yacc.c:1646 */ - { -- add_label(&(yyvsp[(2) - (2)].prop)->labels, (yyvsp[(1) - (2)].labelref)); -- (yyval.prop) = (yyvsp[(2) - (2)].prop); -+ (yyval.prop) = build_property((yyvsp[-1].propnodename), empty_data); - } -+#line 1612 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 18: --/* Line 1787 of yacc.c */ --#line 211 "dtc-parser.y" -+#line 212 "dtc-parser.y" /* yacc.c:1646 */ - { -- (yyval.data) = data_merge((yyvsp[(1) - (2)].data), (yyvsp[(2) - (2)].data)); -+ (yyval.prop) = build_property_delete((yyvsp[-1].propnodename)); - } -+#line 1620 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 19: --/* Line 1787 of yacc.c */ --#line 215 "dtc-parser.y" -+#line 216 "dtc-parser.y" /* yacc.c:1646 */ - { -- (yyval.data) = data_merge((yyvsp[(1) - (3)].data), (yyvsp[(2) - (3)].array).data); -+ add_label(&(yyvsp[0].prop)->labels, (yyvsp[-1].labelref)); -+ (yyval.prop) = (yyvsp[0].prop); - } -+#line 1629 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 20: --/* Line 1787 of yacc.c */ --#line 219 "dtc-parser.y" -+#line 224 "dtc-parser.y" /* yacc.c:1646 */ - { -- (yyval.data) = data_merge((yyvsp[(1) - (4)].data), (yyvsp[(3) - (4)].data)); -+ (yyval.data) = data_merge((yyvsp[-1].data), (yyvsp[0].data)); - } -+#line 1637 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 21: --/* Line 1787 of yacc.c */ --#line 223 "dtc-parser.y" -+#line 228 "dtc-parser.y" /* yacc.c:1646 */ - { -- (yyval.data) = data_add_marker((yyvsp[(1) - (2)].data), REF_PATH, (yyvsp[(2) - (2)].labelref)); -+ (yyval.data) = data_merge((yyvsp[-2].data), (yyvsp[-1].array).data); - } -+#line 1645 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 22: --/* Line 1787 of yacc.c */ --#line 227 "dtc-parser.y" -+#line 232 "dtc-parser.y" /* yacc.c:1646 */ - { -- FILE *f = srcfile_relative_open((yyvsp[(4) - (9)].data).val, NULL); -+ (yyval.data) = data_merge((yyvsp[-3].data), (yyvsp[-1].data)); -+ } -+#line 1653 "dtc-parser.tab.c" /* yacc.c:1646 */ -+ break; -+ -+ case 23: -+#line 236 "dtc-parser.y" /* yacc.c:1646 */ -+ { -+ (yyval.data) = data_add_marker((yyvsp[-1].data), REF_PATH, (yyvsp[0].labelref)); -+ } -+#line 1661 "dtc-parser.tab.c" /* yacc.c:1646 */ -+ break; -+ -+ case 24: -+#line 240 "dtc-parser.y" /* yacc.c:1646 */ -+ { -+ FILE *f = srcfile_relative_open((yyvsp[-5].data).val, NULL); - struct data d; - -- if ((yyvsp[(6) - (9)].integer) != 0) -- if (fseek(f, (yyvsp[(6) - (9)].integer), SEEK_SET) != 0) -- print_error("Couldn't seek to offset %llu in \"%s\": %s", -- (unsigned long long)(yyvsp[(6) - (9)].integer), -- (yyvsp[(4) - (9)].data).val, -- strerror(errno)); -+ if ((yyvsp[-3].integer) != 0) -+ if (fseek(f, (yyvsp[-3].integer), SEEK_SET) != 0) -+ die("Couldn't seek to offset %llu in \"%s\": %s", -+ (unsigned long long)(yyvsp[-3].integer), (yyvsp[-5].data).val, -+ strerror(errno)); - -- d = data_copy_file(f, (yyvsp[(8) - (9)].integer)); -+ d = data_copy_file(f, (yyvsp[-1].integer)); - -- (yyval.data) = data_merge((yyvsp[(1) - (9)].data), d); -+ (yyval.data) = data_merge((yyvsp[-8].data), d); - fclose(f); - } -+#line 1681 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - -- case 23: --/* Line 1787 of yacc.c */ --#line 244 "dtc-parser.y" -+ case 25: -+#line 256 "dtc-parser.y" /* yacc.c:1646 */ - { -- FILE *f = srcfile_relative_open((yyvsp[(4) - (5)].data).val, NULL); -+ FILE *f = srcfile_relative_open((yyvsp[-1].data).val, NULL); - struct data d = empty_data; - - d = data_copy_file(f, -1); - -- (yyval.data) = data_merge((yyvsp[(1) - (5)].data), d); -+ (yyval.data) = data_merge((yyvsp[-4].data), d); - fclose(f); - } -+#line 1695 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - -- case 24: --/* Line 1787 of yacc.c */ --#line 254 "dtc-parser.y" -+ case 26: -+#line 266 "dtc-parser.y" /* yacc.c:1646 */ - { -- (yyval.data) = data_add_marker((yyvsp[(1) - (2)].data), LABEL, (yyvsp[(2) - (2)].labelref)); -+ (yyval.data) = data_add_marker((yyvsp[-1].data), LABEL, (yyvsp[0].labelref)); - } -+#line 1703 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - -- case 25: --/* Line 1787 of yacc.c */ --#line 261 "dtc-parser.y" -+ case 27: -+#line 273 "dtc-parser.y" /* yacc.c:1646 */ - { - (yyval.data) = empty_data; - } -+#line 1711 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - -- case 26: --/* Line 1787 of yacc.c */ --#line 265 "dtc-parser.y" -+ case 28: -+#line 277 "dtc-parser.y" /* yacc.c:1646 */ - { -- (yyval.data) = (yyvsp[(1) - (2)].data); -+ (yyval.data) = (yyvsp[-1].data); - } -+#line 1719 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - -- case 27: --/* Line 1787 of yacc.c */ --#line 269 "dtc-parser.y" -+ case 29: -+#line 281 "dtc-parser.y" /* yacc.c:1646 */ - { -- (yyval.data) = data_add_marker((yyvsp[(1) - (2)].data), LABEL, (yyvsp[(2) - (2)].labelref)); -+ (yyval.data) = data_add_marker((yyvsp[-1].data), LABEL, (yyvsp[0].labelref)); - } -+#line 1727 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - -- case 28: --/* Line 1787 of yacc.c */ --#line 276 "dtc-parser.y" -+ case 30: -+#line 288 "dtc-parser.y" /* yacc.c:1646 */ - { -- (yyval.array).data = empty_data; -- (yyval.array).bits = eval_literal((yyvsp[(2) - (3)].literal), 0, 7); -+ unsigned long long bits; - -- if (((yyval.array).bits != 8) && -- ((yyval.array).bits != 16) && -- ((yyval.array).bits != 32) && -- ((yyval.array).bits != 64)) -- { -- print_error("Only 8, 16, 32 and 64-bit elements" -- " are currently supported"); -- (yyval.array).bits = 32; -+ bits = (yyvsp[-1].integer); -+ -+ if ((bits != 8) && (bits != 16) && -+ (bits != 32) && (bits != 64)) { -+ ERROR(&(yylsp[-1]), "Array elements must be" -+ " 8, 16, 32 or 64-bits"); -+ bits = 32; - } -+ -+ (yyval.array).data = empty_data; -+ (yyval.array).bits = bits; - } -+#line 1747 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - -- case 29: --/* Line 1787 of yacc.c */ --#line 291 "dtc-parser.y" -+ case 31: -+#line 304 "dtc-parser.y" /* yacc.c:1646 */ - { - (yyval.array).data = empty_data; - (yyval.array).bits = 32; - } -+#line 1756 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - -- case 30: --/* Line 1787 of yacc.c */ --#line 296 "dtc-parser.y" -+ case 32: -+#line 309 "dtc-parser.y" /* yacc.c:1646 */ - { -- if ((yyvsp[(1) - (2)].array).bits < 64) { -- uint64_t mask = (1ULL << (yyvsp[(1) - (2)].array).bits) - 1; -+ if ((yyvsp[-1].array).bits < 64) { -+ uint64_t mask = (1ULL << (yyvsp[-1].array).bits) - 1; - /* - * Bits above mask must either be all zero - * (positive within range of mask) or all one -@@ -1801,275 +1768,258 @@ - * within the mask to one (i.e. | in the - * mask), all bits are one. - */ -- if (((yyvsp[(2) - (2)].integer) > mask) && (((yyvsp[(2) - (2)].integer) | mask) != -1ULL)) -- print_error( -- "integer value out of range " -- "%016lx (%d bits)", (yyvsp[(1) - (2)].array).bits); -+ if (((yyvsp[0].integer) > mask) && (((yyvsp[0].integer) | mask) != -1ULL)) -+ ERROR(&(yylsp[0]), "Value out of range for" -+ " %d-bit array element", (yyvsp[-1].array).bits); - } - -- (yyval.array).data = data_append_integer((yyvsp[(1) - (2)].array).data, (yyvsp[(2) - (2)].integer), (yyvsp[(1) - (2)].array).bits); -+ (yyval.array).data = data_append_integer((yyvsp[-1].array).data, (yyvsp[0].integer), (yyvsp[-1].array).bits); - } -+#line 1779 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - -- case 31: --/* Line 1787 of yacc.c */ --#line 316 "dtc-parser.y" -+ case 33: -+#line 328 "dtc-parser.y" /* yacc.c:1646 */ - { -- uint64_t val = ~0ULL >> (64 - (yyvsp[(1) - (2)].array).bits); -+ uint64_t val = ~0ULL >> (64 - (yyvsp[-1].array).bits); - -- if ((yyvsp[(1) - (2)].array).bits == 32) -- (yyvsp[(1) - (2)].array).data = data_add_marker((yyvsp[(1) - (2)].array).data, -+ if ((yyvsp[-1].array).bits == 32) -+ (yyvsp[-1].array).data = data_add_marker((yyvsp[-1].array).data, - REF_PHANDLE, -- (yyvsp[(2) - (2)].labelref)); -+ (yyvsp[0].labelref)); - else -- print_error("References are only allowed in " -+ ERROR(&(yylsp[0]), "References are only allowed in " - "arrays with 32-bit elements."); - -- (yyval.array).data = data_append_integer((yyvsp[(1) - (2)].array).data, val, (yyvsp[(1) - (2)].array).bits); -- } -- break; -- -- case 32: --/* Line 1787 of yacc.c */ --#line 330 "dtc-parser.y" -- { -- (yyval.array).data = data_add_marker((yyvsp[(1) - (2)].array).data, LABEL, (yyvsp[(2) - (2)].labelref)); -- } -- break; -- -- case 33: --/* Line 1787 of yacc.c */ --#line 337 "dtc-parser.y" -- { -- (yyval.integer) = eval_literal((yyvsp[(1) - (1)].literal), 0, 64); -+ (yyval.array).data = data_append_integer((yyvsp[-1].array).data, val, (yyvsp[-1].array).bits); - } -+#line 1797 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 34: --/* Line 1787 of yacc.c */ --#line 341 "dtc-parser.y" -+#line 342 "dtc-parser.y" /* yacc.c:1646 */ - { -- (yyval.integer) = eval_char_literal((yyvsp[(1) - (1)].literal)); -+ (yyval.array).data = data_add_marker((yyvsp[-1].array).data, LABEL, (yyvsp[0].labelref)); - } -+#line 1805 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - -- case 35: --/* Line 1787 of yacc.c */ --#line 345 "dtc-parser.y" -+ case 37: -+#line 351 "dtc-parser.y" /* yacc.c:1646 */ - { -- (yyval.integer) = (yyvsp[(2) - (3)].integer); -+ (yyval.integer) = (yyvsp[-1].integer); - } -- break; -- -- case 38: --/* Line 1787 of yacc.c */ --#line 356 "dtc-parser.y" -- { (yyval.integer) = (yyvsp[(1) - (5)].integer) ? (yyvsp[(3) - (5)].integer) : (yyvsp[(5) - (5)].integer); } -+#line 1813 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 40: --/* Line 1787 of yacc.c */ --#line 361 "dtc-parser.y" -- { (yyval.integer) = (yyvsp[(1) - (3)].integer) || (yyvsp[(3) - (3)].integer); } -+#line 362 "dtc-parser.y" /* yacc.c:1646 */ -+ { (yyval.integer) = (yyvsp[-4].integer) ? (yyvsp[-2].integer) : (yyvsp[0].integer); } -+#line 1819 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 42: --/* Line 1787 of yacc.c */ --#line 366 "dtc-parser.y" -- { (yyval.integer) = (yyvsp[(1) - (3)].integer) && (yyvsp[(3) - (3)].integer); } -+#line 367 "dtc-parser.y" /* yacc.c:1646 */ -+ { (yyval.integer) = (yyvsp[-2].integer) || (yyvsp[0].integer); } -+#line 1825 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 44: --/* Line 1787 of yacc.c */ --#line 371 "dtc-parser.y" -- { (yyval.integer) = (yyvsp[(1) - (3)].integer) | (yyvsp[(3) - (3)].integer); } -+#line 372 "dtc-parser.y" /* yacc.c:1646 */ -+ { (yyval.integer) = (yyvsp[-2].integer) && (yyvsp[0].integer); } -+#line 1831 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 46: --/* Line 1787 of yacc.c */ --#line 376 "dtc-parser.y" -- { (yyval.integer) = (yyvsp[(1) - (3)].integer) ^ (yyvsp[(3) - (3)].integer); } -+#line 377 "dtc-parser.y" /* yacc.c:1646 */ -+ { (yyval.integer) = (yyvsp[-2].integer) | (yyvsp[0].integer); } -+#line 1837 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 48: --/* Line 1787 of yacc.c */ --#line 381 "dtc-parser.y" -- { (yyval.integer) = (yyvsp[(1) - (3)].integer) & (yyvsp[(3) - (3)].integer); } -+#line 382 "dtc-parser.y" /* yacc.c:1646 */ -+ { (yyval.integer) = (yyvsp[-2].integer) ^ (yyvsp[0].integer); } -+#line 1843 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 50: --/* Line 1787 of yacc.c */ --#line 386 "dtc-parser.y" -- { (yyval.integer) = (yyvsp[(1) - (3)].integer) == (yyvsp[(3) - (3)].integer); } -+#line 387 "dtc-parser.y" /* yacc.c:1646 */ -+ { (yyval.integer) = (yyvsp[-2].integer) & (yyvsp[0].integer); } -+#line 1849 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - -- case 51: --/* Line 1787 of yacc.c */ --#line 387 "dtc-parser.y" -- { (yyval.integer) = (yyvsp[(1) - (3)].integer) != (yyvsp[(3) - (3)].integer); } -+ case 52: -+#line 392 "dtc-parser.y" /* yacc.c:1646 */ -+ { (yyval.integer) = (yyvsp[-2].integer) == (yyvsp[0].integer); } -+#line 1855 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 53: --/* Line 1787 of yacc.c */ --#line 392 "dtc-parser.y" -- { (yyval.integer) = (yyvsp[(1) - (3)].integer) < (yyvsp[(3) - (3)].integer); } -- break; -- -- case 54: --/* Line 1787 of yacc.c */ --#line 393 "dtc-parser.y" -- { (yyval.integer) = (yyvsp[(1) - (3)].integer) > (yyvsp[(3) - (3)].integer); } -+#line 393 "dtc-parser.y" /* yacc.c:1646 */ -+ { (yyval.integer) = (yyvsp[-2].integer) != (yyvsp[0].integer); } -+#line 1861 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 55: --/* Line 1787 of yacc.c */ --#line 394 "dtc-parser.y" -- { (yyval.integer) = (yyvsp[(1) - (3)].integer) <= (yyvsp[(3) - (3)].integer); } -+#line 398 "dtc-parser.y" /* yacc.c:1646 */ -+ { (yyval.integer) = (yyvsp[-2].integer) < (yyvsp[0].integer); } -+#line 1867 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 56: --/* Line 1787 of yacc.c */ --#line 395 "dtc-parser.y" -- { (yyval.integer) = (yyvsp[(1) - (3)].integer) >= (yyvsp[(3) - (3)].integer); } -+#line 399 "dtc-parser.y" /* yacc.c:1646 */ -+ { (yyval.integer) = (yyvsp[-2].integer) > (yyvsp[0].integer); } -+#line 1873 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 57: --/* Line 1787 of yacc.c */ --#line 399 "dtc-parser.y" -- { (yyval.integer) = (yyvsp[(1) - (3)].integer) << (yyvsp[(3) - (3)].integer); } -+#line 400 "dtc-parser.y" /* yacc.c:1646 */ -+ { (yyval.integer) = (yyvsp[-2].integer) <= (yyvsp[0].integer); } -+#line 1879 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 58: --/* Line 1787 of yacc.c */ --#line 400 "dtc-parser.y" -- { (yyval.integer) = (yyvsp[(1) - (3)].integer) >> (yyvsp[(3) - (3)].integer); } -+#line 401 "dtc-parser.y" /* yacc.c:1646 */ -+ { (yyval.integer) = (yyvsp[-2].integer) >= (yyvsp[0].integer); } -+#line 1885 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - -- case 60: --/* Line 1787 of yacc.c */ --#line 405 "dtc-parser.y" -- { (yyval.integer) = (yyvsp[(1) - (3)].integer) + (yyvsp[(3) - (3)].integer); } -+ case 59: -+#line 405 "dtc-parser.y" /* yacc.c:1646 */ -+ { (yyval.integer) = (yyvsp[-2].integer) << (yyvsp[0].integer); } -+#line 1891 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - -- case 61: --/* Line 1787 of yacc.c */ --#line 406 "dtc-parser.y" -- { (yyval.integer) = (yyvsp[(1) - (3)].integer) - (yyvsp[(3) - (3)].integer); } -+ case 60: -+#line 406 "dtc-parser.y" /* yacc.c:1646 */ -+ { (yyval.integer) = (yyvsp[-2].integer) >> (yyvsp[0].integer); } -+#line 1897 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - -- case 63: --/* Line 1787 of yacc.c */ --#line 411 "dtc-parser.y" -- { (yyval.integer) = (yyvsp[(1) - (3)].integer) * (yyvsp[(3) - (3)].integer); } -+ case 62: -+#line 411 "dtc-parser.y" /* yacc.c:1646 */ -+ { (yyval.integer) = (yyvsp[-2].integer) + (yyvsp[0].integer); } -+#line 1903 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - -- case 64: --/* Line 1787 of yacc.c */ --#line 412 "dtc-parser.y" -- { (yyval.integer) = (yyvsp[(1) - (3)].integer) / (yyvsp[(3) - (3)].integer); } -+ case 63: -+#line 412 "dtc-parser.y" /* yacc.c:1646 */ -+ { (yyval.integer) = (yyvsp[-2].integer) - (yyvsp[0].integer); } -+#line 1909 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 65: --/* Line 1787 of yacc.c */ --#line 413 "dtc-parser.y" -- { (yyval.integer) = (yyvsp[(1) - (3)].integer) % (yyvsp[(3) - (3)].integer); } -+#line 417 "dtc-parser.y" /* yacc.c:1646 */ -+ { (yyval.integer) = (yyvsp[-2].integer) * (yyvsp[0].integer); } -+#line 1915 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - -- case 68: --/* Line 1787 of yacc.c */ --#line 419 "dtc-parser.y" -- { (yyval.integer) = -(yyvsp[(2) - (2)].integer); } -+ case 66: -+#line 418 "dtc-parser.y" /* yacc.c:1646 */ -+ { (yyval.integer) = (yyvsp[-2].integer) / (yyvsp[0].integer); } -+#line 1921 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - -- case 69: --/* Line 1787 of yacc.c */ --#line 420 "dtc-parser.y" -- { (yyval.integer) = ~(yyvsp[(2) - (2)].integer); } -+ case 67: -+#line 419 "dtc-parser.y" /* yacc.c:1646 */ -+ { (yyval.integer) = (yyvsp[-2].integer) % (yyvsp[0].integer); } -+#line 1927 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 70: --/* Line 1787 of yacc.c */ --#line 421 "dtc-parser.y" -- { (yyval.integer) = !(yyvsp[(2) - (2)].integer); } -+#line 425 "dtc-parser.y" /* yacc.c:1646 */ -+ { (yyval.integer) = -(yyvsp[0].integer); } -+#line 1933 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 71: --/* Line 1787 of yacc.c */ --#line 426 "dtc-parser.y" -- { -- (yyval.data) = empty_data; -- } -+#line 426 "dtc-parser.y" /* yacc.c:1646 */ -+ { (yyval.integer) = ~(yyvsp[0].integer); } -+#line 1939 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 72: --/* Line 1787 of yacc.c */ --#line 430 "dtc-parser.y" -- { -- (yyval.data) = data_append_byte((yyvsp[(1) - (2)].data), (yyvsp[(2) - (2)].byte)); -- } -+#line 427 "dtc-parser.y" /* yacc.c:1646 */ -+ { (yyval.integer) = !(yyvsp[0].integer); } -+#line 1945 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 73: --/* Line 1787 of yacc.c */ --#line 434 "dtc-parser.y" -+#line 432 "dtc-parser.y" /* yacc.c:1646 */ - { -- (yyval.data) = data_add_marker((yyvsp[(1) - (2)].data), LABEL, (yyvsp[(2) - (2)].labelref)); -+ (yyval.data) = empty_data; - } -+#line 1953 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 74: --/* Line 1787 of yacc.c */ --#line 441 "dtc-parser.y" -+#line 436 "dtc-parser.y" /* yacc.c:1646 */ - { -- (yyval.nodelist) = NULL; -+ (yyval.data) = data_append_byte((yyvsp[-1].data), (yyvsp[0].byte)); - } -+#line 1961 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 75: --/* Line 1787 of yacc.c */ --#line 445 "dtc-parser.y" -+#line 440 "dtc-parser.y" /* yacc.c:1646 */ - { -- (yyval.nodelist) = chain_node((yyvsp[(1) - (2)].node), (yyvsp[(2) - (2)].nodelist)); -+ (yyval.data) = data_add_marker((yyvsp[-1].data), LABEL, (yyvsp[0].labelref)); - } -+#line 1969 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 76: --/* Line 1787 of yacc.c */ --#line 449 "dtc-parser.y" -+#line 447 "dtc-parser.y" /* yacc.c:1646 */ - { -- print_error("syntax error: properties must precede subnodes"); -- YYERROR; -+ (yyval.nodelist) = NULL; - } -+#line 1977 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 77: --/* Line 1787 of yacc.c */ --#line 457 "dtc-parser.y" -+#line 451 "dtc-parser.y" /* yacc.c:1646 */ - { -- (yyval.node) = name_node((yyvsp[(2) - (2)].node), (yyvsp[(1) - (2)].propnodename)); -+ (yyval.nodelist) = chain_node((yyvsp[-1].node), (yyvsp[0].nodelist)); - } -+#line 1985 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 78: --/* Line 1787 of yacc.c */ --#line 461 "dtc-parser.y" -+#line 455 "dtc-parser.y" /* yacc.c:1646 */ - { -- (yyval.node) = name_node(build_node_delete(), (yyvsp[(2) - (3)].propnodename)); -+ ERROR(&(yylsp[0]), "Properties must precede subnodes"); -+ YYERROR; - } -+#line 1994 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - - case 79: --/* Line 1787 of yacc.c */ --#line 465 "dtc-parser.y" -+#line 463 "dtc-parser.y" /* yacc.c:1646 */ - { -- add_label(&(yyvsp[(2) - (2)].node)->labels, (yyvsp[(1) - (2)].labelref)); -- (yyval.node) = (yyvsp[(2) - (2)].node); -+ (yyval.node) = name_node((yyvsp[0].node), (yyvsp[-1].propnodename)); - } -+#line 2002 "dtc-parser.tab.c" /* yacc.c:1646 */ - break; - -+ case 80: -+#line 467 "dtc-parser.y" /* yacc.c:1646 */ -+ { -+ (yyval.node) = name_node(build_node_delete(), (yyvsp[-1].propnodename)); -+ } -+#line 2010 "dtc-parser.tab.c" /* yacc.c:1646 */ -+ break; -+ -+ case 81: -+#line 471 "dtc-parser.y" /* yacc.c:1646 */ -+ { -+ add_label(&(yyvsp[0].node)->labels, (yyvsp[-1].labelref)); -+ (yyval.node) = (yyvsp[0].node); -+ } -+#line 2019 "dtc-parser.tab.c" /* yacc.c:1646 */ -+ break; - --/* Line 1787 of yacc.c */ --#line 2073 "dtc-parser.tab.c" -+ -+#line 2023 "dtc-parser.tab.c" /* yacc.c:1646 */ - default: break; - } - /* User semantic actions sometimes alter yychar, and that requires -@@ -2090,8 +2040,9 @@ - YY_STACK_PRINT (yyss, yyssp); - - *++yyvsp = yyval; -+ *++yylsp = yyloc; - -- /* Now `shift' the result of the reduction. Determine what state -+ /* Now 'shift' the result of the reduction. Determine what state - that goes to, based on the state we popped back to and the rule - number reduced by. */ - -@@ -2106,9 +2057,9 @@ - goto yynewstate; - - --/*------------------------------------. --| yyerrlab -- here on detecting error | --`------------------------------------*/ -+/*--------------------------------------. -+| yyerrlab -- here on detecting error. | -+`--------------------------------------*/ - yyerrlab: - /* Make sure we have latest lookahead translation. See comments at - user semantic actions for why this is necessary. */ -@@ -2154,25 +2105,25 @@ - #endif - } - -- -+ yyerror_range[1] = yylloc; - - if (yyerrstatus == 3) - { - /* If just tried and failed to reuse lookahead token after an -- error, discard it. */ -+ error, discard it. */ - - if (yychar <= YYEOF) -- { -- /* Return failure if at end of input. */ -- if (yychar == YYEOF) -- YYABORT; -- } -+ { -+ /* Return failure if at end of input. */ -+ if (yychar == YYEOF) -+ YYABORT; -+ } - else -- { -- yydestruct ("Error: discarding", -- yytoken, &yylval); -- yychar = YYEMPTY; -- } -+ { -+ yydestruct ("Error: discarding", -+ yytoken, &yylval, &yylloc); -+ yychar = YYEMPTY; -+ } - } - - /* Else will try to reuse lookahead token after shifting the error -@@ -2191,7 +2142,8 @@ - if (/*CONSTCOND*/ 0) - goto yyerrorlab; - -- /* Do not reclaim the symbols of the rule which action triggered -+ yyerror_range[1] = yylsp[1-yylen]; -+ /* Do not reclaim the symbols of the rule whose action triggered - this YYERROR. */ - YYPOPSTACK (yylen); - yylen = 0; -@@ -2204,29 +2156,29 @@ - | yyerrlab1 -- common code for both syntax error and YYERROR. | - `-------------------------------------------------------------*/ - yyerrlab1: -- yyerrstatus = 3; /* Each real token shifted decrements this. */ -+ yyerrstatus = 3; /* Each real token shifted decrements this. */ - - for (;;) - { - yyn = yypact[yystate]; - if (!yypact_value_is_default (yyn)) -- { -- yyn += YYTERROR; -- if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR) -- { -- yyn = yytable[yyn]; -- if (0 < yyn) -- break; -- } -- } -+ { -+ yyn += YYTERROR; -+ if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR) -+ { -+ yyn = yytable[yyn]; -+ if (0 < yyn) -+ break; -+ } -+ } - - /* Pop the current state because it cannot handle the error token. */ - if (yyssp == yyss) -- YYABORT; -- -+ YYABORT; - -+ yyerror_range[1] = *yylsp; - yydestruct ("Error: popping", -- yystos[yystate], yyvsp); -+ yystos[yystate], yyvsp, yylsp); - YYPOPSTACK (1); - yystate = *yyssp; - YY_STACK_PRINT (yyss, yyssp); -@@ -2236,6 +2188,11 @@ - *++yyvsp = yylval; - YY_IGNORE_MAYBE_UNINITIALIZED_END - -+ yyerror_range[2] = yylloc; -+ /* Using YYLLOC is tempting, but would change the location of -+ the lookahead. YYLOC is available though. */ -+ YYLLOC_DEFAULT (yyloc, yyerror_range, 2); -+ *++yylsp = yyloc; - - /* Shift the error token. */ - YY_SYMBOL_PRINT ("Shifting", yystos[yyn], yyvsp, yylsp); -@@ -2275,16 +2232,16 @@ - user semantic actions for why this is necessary. */ - yytoken = YYTRANSLATE (yychar); - yydestruct ("Cleanup: discarding lookahead", -- yytoken, &yylval); -+ yytoken, &yylval, &yylloc); - } -- /* Do not reclaim the symbols of the rule which action triggered -+ /* Do not reclaim the symbols of the rule whose action triggered - this YYABORT or YYACCEPT. */ - YYPOPSTACK (yylen); - YY_STACK_PRINT (yyss, yyssp); - while (yyssp != yyss) - { - yydestruct ("Cleanup: popping", -- yystos[*yyssp], yyvsp); -+ yystos[*yyssp], yyvsp, yylsp); - YYPOPSTACK (1); - } - #ifndef yyoverflow -@@ -2295,72 +2252,12 @@ - if (yymsg != yymsgbuf) - YYSTACK_FREE (yymsg); - #endif -- /* Make sure YYID is used. */ -- return YYID (yyresult); -+ return yyresult; - } -+#line 477 "dtc-parser.y" /* yacc.c:1906 */ - - --/* Line 2050 of yacc.c */ --#line 471 "dtc-parser.y" -- -- --void print_error(char const *fmt, ...) -+void yyerror(char const *s) - { -- va_list va; -- -- va_start(va, fmt); -- srcpos_verror(&yylloc, fmt, va); -- va_end(va); -- -- treesource_error = 1; --} -- --void yyerror(char const *s) { -- print_error("%s", s); --} -- --static unsigned long long eval_literal(const char *s, int base, int bits) --{ -- unsigned long long val; -- char *e; -- -- errno = 0; -- val = strtoull(s, &e, base); -- if (*e) { -- size_t uls = strspn(e, "UL"); -- if (e[uls]) -- print_error("bad characters in literal"); -- } -- if ((errno == ERANGE) -- || ((bits < 64) && (val >= (1ULL << bits)))) -- print_error("literal out of range"); -- else if (errno != 0) -- print_error("bad literal"); -- return val; --} -- --static unsigned char eval_char_literal(const char *s) --{ -- int i = 1; -- char c = s[0]; -- -- if (c == '\0') -- { -- print_error("empty character literal"); -- return 0; -- } -- -- /* -- * If the first character in the character literal is a \ then process -- * the remaining characters as an escape encoding. If the first -- * character is neither an escape or a terminator it should be the only -- * character in the literal and will be returned. -- */ -- if (c == '\\') -- c = get_escape_char(s, &i); -- -- if (s[i] != '\0') -- print_error("malformed character literal"); -- -- return c; -+ ERROR(&yylloc, "%s", s); - } -diff -Nur linux-4.1.13.orig/scripts/dtc/dtc-parser.tab.h_shipped linux-rpi/scripts/dtc/dtc-parser.tab.h_shipped ---- linux-4.1.13.orig/scripts/dtc/dtc-parser.tab.h_shipped 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/scripts/dtc/dtc-parser.tab.h_shipped 2015-11-29 09:42:41.406999830 +0100 -@@ -1,19 +1,19 @@ --/* A Bison parser, made by GNU Bison 2.7.12-4996. */ -+/* A Bison parser, made by GNU Bison 3.0.2. */ - - /* Bison interface for Yacc-like parsers in C -- -- Copyright (C) 1984, 1989-1990, 2000-2013 Free Software Foundation, Inc. -- -+ -+ Copyright (C) 1984, 1989-1990, 2000-2013 Free Software Foundation, Inc. -+ - This program is free software: you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation, either version 3 of the License, or - (at your option) any later version. -- -+ - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -- -+ - You should have received a copy of the GNU General Public License - along with this program. If not, see . */ - -@@ -26,13 +26,13 @@ - special exception, which will cause the skeleton and the resulting - Bison output files to be licensed under the GNU General Public - License without this special exception. -- -+ - This special exception was added by the Free Software Foundation in - version 2.2 of Bison. */ - - #ifndef YY_YY_DTC_PARSER_TAB_H_INCLUDED - # define YY_YY_DTC_PARSER_TAB_H_INCLUDED --/* Enabling traces. */ -+/* Debug traces. */ - #ifndef YYDEBUG - # define YYDEBUG 0 - #endif -@@ -40,48 +40,45 @@ - extern int yydebug; - #endif - --/* Tokens. */ -+/* Token type. */ - #ifndef YYTOKENTYPE - # define YYTOKENTYPE -- /* Put the tokens into the symbol table, so that GDB and other debuggers -- know about them. */ -- enum yytokentype { -- DT_V1 = 258, -- DT_MEMRESERVE = 259, -- DT_LSHIFT = 260, -- DT_RSHIFT = 261, -- DT_LE = 262, -- DT_GE = 263, -- DT_EQ = 264, -- DT_NE = 265, -- DT_AND = 266, -- DT_OR = 267, -- DT_BITS = 268, -- DT_DEL_PROP = 269, -- DT_DEL_NODE = 270, -- DT_PROPNODENAME = 271, -- DT_LITERAL = 272, -- DT_CHAR_LITERAL = 273, -- DT_BASE = 274, -- DT_BYTE = 275, -- DT_STRING = 276, -- DT_LABEL = 277, -- DT_REF = 278, -- DT_INCBIN = 279 -- }; -+ enum yytokentype -+ { -+ DT_V1 = 258, -+ DT_PLUGIN = 259, -+ DT_MEMRESERVE = 260, -+ DT_LSHIFT = 261, -+ DT_RSHIFT = 262, -+ DT_LE = 263, -+ DT_GE = 264, -+ DT_EQ = 265, -+ DT_NE = 266, -+ DT_AND = 267, -+ DT_OR = 268, -+ DT_BITS = 269, -+ DT_DEL_PROP = 270, -+ DT_DEL_NODE = 271, -+ DT_PROPNODENAME = 272, -+ DT_LITERAL = 273, -+ DT_CHAR_LITERAL = 274, -+ DT_BYTE = 275, -+ DT_STRING = 276, -+ DT_LABEL = 277, -+ DT_REF = 278, -+ DT_INCBIN = 279 -+ }; - #endif - -- -+/* Value type. */ - #if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED --typedef union YYSTYPE -+typedef union YYSTYPE YYSTYPE; -+union YYSTYPE - { --/* Line 2053 of yacc.c */ --#line 40 "dtc-parser.y" -+#line 39 "dtc-parser.y" /* yacc.c:1909 */ - - char *propnodename; -- char *literal; - char *labelref; -- unsigned int cbase; - uint8_t byte; - struct data data; - -@@ -96,30 +93,31 @@ - struct node *nodelist; - struct reserve_info *re; - uint64_t integer; -+ int is_plugin; - -- --/* Line 2053 of yacc.c */ --#line 103 "dtc-parser.tab.h" --} YYSTYPE; -+#line 99 "dtc-parser.tab.h" /* yacc.c:1909 */ -+}; - # define YYSTYPE_IS_TRIVIAL 1 --# define yystype YYSTYPE /* obsolescent; will be withdrawn */ - # define YYSTYPE_IS_DECLARED 1 - #endif - --extern YYSTYPE yylval; -- --#ifdef YYPARSE_PARAM --#if defined __STDC__ || defined __cplusplus --int yyparse (void *YYPARSE_PARAM); --#else --int yyparse (); -+/* Location type. */ -+#if ! defined YYLTYPE && ! defined YYLTYPE_IS_DECLARED -+typedef struct YYLTYPE YYLTYPE; -+struct YYLTYPE -+{ -+ int first_line; -+ int first_column; -+ int last_line; -+ int last_column; -+}; -+# define YYLTYPE_IS_DECLARED 1 -+# define YYLTYPE_IS_TRIVIAL 1 - #endif --#else /* ! YYPARSE_PARAM */ --#if defined __STDC__ || defined __cplusplus -+ -+ -+extern YYSTYPE yylval; -+extern YYLTYPE yylloc; - int yyparse (void); --#else --int yyparse (); --#endif --#endif /* ! YYPARSE_PARAM */ - - #endif /* !YY_YY_DTC_PARSER_TAB_H_INCLUDED */ -diff -Nur linux-4.1.13.orig/scripts/dtc/dtc-parser.y linux-rpi/scripts/dtc/dtc-parser.y ---- linux-4.1.13.orig/scripts/dtc/dtc-parser.y 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/scripts/dtc/dtc-parser.y 2015-11-29 09:42:41.406999830 +0100 -@@ -17,31 +17,28 @@ - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 - * USA - */ -- - %{ - #include -+#include - - #include "dtc.h" - #include "srcpos.h" - --YYLTYPE yylloc; -- - extern int yylex(void); --extern void print_error(char const *fmt, ...); - extern void yyerror(char const *s); -+#define ERROR(loc, ...) \ -+ do { \ -+ srcpos_error((loc), "Error", __VA_ARGS__); \ -+ treesource_error = true; \ -+ } while (0) - - extern struct boot_info *the_boot_info; --extern int treesource_error; -- --static unsigned long long eval_literal(const char *s, int base, int bits); --static unsigned char eval_char_literal(const char *s); -+extern bool treesource_error; - %} - - %union { - char *propnodename; -- char *literal; - char *labelref; -- unsigned int cbase; - uint8_t byte; - struct data data; - -@@ -56,18 +53,19 @@ - struct node *nodelist; - struct reserve_info *re; - uint64_t integer; -+ int is_plugin; - } - - %token DT_V1 -+%token DT_PLUGIN - %token DT_MEMRESERVE - %token DT_LSHIFT DT_RSHIFT DT_LE DT_GE DT_EQ DT_NE DT_AND DT_OR - %token DT_BITS - %token DT_DEL_PROP - %token DT_DEL_NODE - %token DT_PROPNODENAME --%token DT_LITERAL --%token DT_CHAR_LITERAL --%token DT_BASE -+%token DT_LITERAL -+%token DT_CHAR_LITERAL - %token DT_BYTE - %token DT_STRING - %token DT_LABEL -@@ -76,6 +74,7 @@ - - %type propdata - %type propdataprefix -+%type plugindecl - %type memreserve - %type memreserves - %type arrayprefix -@@ -106,10 +105,23 @@ - %% - - sourcefile: -- DT_V1 ';' memreserves devicetree -+ DT_V1 ';' plugindecl memreserves devicetree -+ { -+ $5->is_plugin = $3; -+ $5->is_root = 1; -+ the_boot_info = build_boot_info($4, $5, -+ guess_boot_cpuid($5)); -+ } -+ ; -+ -+plugindecl: -+ /* empty */ -+ { -+ $$ = 0; -+ } -+ | DT_PLUGIN ';' - { -- the_boot_info = build_boot_info($3, $4, -- guess_boot_cpuid($4)); -+ $$ = 1; - } - ; - -@@ -152,17 +164,18 @@ - if (target) - merge_nodes(target, $3); - else -- print_error("label or path, '%s', not found", $2); -+ ERROR(&@2, "Label or path %s not found", $2); - $$ = $1; - } - | devicetree DT_DEL_NODE DT_REF ';' - { - struct node *target = get_node_by_ref($1, $3); - -- if (!target) -- print_error("label or path, '%s', not found", $3); -- else -+ if (target) - delete_node(target); -+ else -+ ERROR(&@3, "Label or path %s not found", $3); -+ - - $$ = $1; - } -@@ -230,10 +243,9 @@ - - if ($6 != 0) - if (fseek(f, $6, SEEK_SET) != 0) -- print_error("Couldn't seek to offset %llu in \"%s\": %s", -- (unsigned long long)$6, -- $4.val, -- strerror(errno)); -+ die("Couldn't seek to offset %llu in \"%s\": %s", -+ (unsigned long long)$6, $4.val, -+ strerror(errno)); - - d = data_copy_file(f, $8); - -@@ -274,18 +286,19 @@ - arrayprefix: - DT_BITS DT_LITERAL '<' - { -- $$.data = empty_data; -- $$.bits = eval_literal($2, 0, 7); -+ unsigned long long bits; - -- if (($$.bits != 8) && -- ($$.bits != 16) && -- ($$.bits != 32) && -- ($$.bits != 64)) -- { -- print_error("Only 8, 16, 32 and 64-bit elements" -- " are currently supported"); -- $$.bits = 32; -+ bits = $2; -+ -+ if ((bits != 8) && (bits != 16) && -+ (bits != 32) && (bits != 64)) { -+ ERROR(&@2, "Array elements must be" -+ " 8, 16, 32 or 64-bits"); -+ bits = 32; - } -+ -+ $$.data = empty_data; -+ $$.bits = bits; - } - | '<' - { -@@ -305,9 +318,8 @@ - * mask), all bits are one. - */ - if (($2 > mask) && (($2 | mask) != -1ULL)) -- print_error( -- "integer value out of range " -- "%016lx (%d bits)", $1.bits); -+ ERROR(&@2, "Value out of range for" -+ " %d-bit array element", $1.bits); - } - - $$.data = data_append_integer($1.data, $2, $1.bits); -@@ -321,7 +333,7 @@ - REF_PHANDLE, - $2); - else -- print_error("References are only allowed in " -+ ERROR(&@2, "References are only allowed in " - "arrays with 32-bit elements."); - - $$.data = data_append_integer($1.data, val, $1.bits); -@@ -334,13 +346,7 @@ - - integer_prim: - DT_LITERAL -- { -- $$ = eval_literal($1, 0, 64); -- } - | DT_CHAR_LITERAL -- { -- $$ = eval_char_literal($1); -- } - | '(' integer_expr ')' - { - $$ = $2; -@@ -447,7 +453,7 @@ - } - | subnode propdef - { -- print_error("syntax error: properties must precede subnodes"); -+ ERROR(&@2, "Properties must precede subnodes"); - YYERROR; - } - ; -@@ -470,63 +476,7 @@ - - %% - --void print_error(char const *fmt, ...) -+void yyerror(char const *s) - { -- va_list va; -- -- va_start(va, fmt); -- srcpos_verror(&yylloc, fmt, va); -- va_end(va); -- -- treesource_error = 1; --} -- --void yyerror(char const *s) { -- print_error("%s", s); --} -- --static unsigned long long eval_literal(const char *s, int base, int bits) --{ -- unsigned long long val; -- char *e; -- -- errno = 0; -- val = strtoull(s, &e, base); -- if (*e) { -- size_t uls = strspn(e, "UL"); -- if (e[uls]) -- print_error("bad characters in literal"); -- } -- if ((errno == ERANGE) -- || ((bits < 64) && (val >= (1ULL << bits)))) -- print_error("literal out of range"); -- else if (errno != 0) -- print_error("bad literal"); -- return val; --} -- --static unsigned char eval_char_literal(const char *s) --{ -- int i = 1; -- char c = s[0]; -- -- if (c == '\0') -- { -- print_error("empty character literal"); -- return 0; -- } -- -- /* -- * If the first character in the character literal is a \ then process -- * the remaining characters as an escape encoding. If the first -- * character is neither an escape or a terminator it should be the only -- * character in the literal and will be returned. -- */ -- if (c == '\\') -- c = get_escape_char(s, &i); -- -- if (s[i] != '\0') -- print_error("malformed character literal"); -- -- return c; -+ ERROR(&yylloc, "%s", s); - } -diff -Nur linux-4.1.13.orig/scripts/dtc/flattree.c linux-rpi/scripts/dtc/flattree.c ---- linux-4.1.13.orig/scripts/dtc/flattree.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/scripts/dtc/flattree.c 2015-11-29 09:42:41.406999830 +0100 -@@ -261,7 +261,13 @@ - { - struct property *prop; - struct node *child; -- int seen_name_prop = 0; -+ bool seen_name_prop = false; -+ struct symbol *sym; -+ struct fixup *f; -+ struct fixup_entry *fe; -+ char *name, *s; -+ const char *fullpath; -+ int namesz, nameoff, vallen; - - if (tree->deleted) - return; -@@ -276,10 +282,8 @@ - emit->align(etarget, sizeof(cell_t)); - - for_each_property(tree, prop) { -- int nameoff; -- - if (streq(prop->name, "name")) -- seen_name_prop = 1; -+ seen_name_prop = true; - - nameoff = stringtable_insert(strbuf, prop->name); - -@@ -310,6 +314,139 @@ - flatten_tree(child, emit, etarget, strbuf, vi); - } - -+ if (!symbol_fixup_support) -+ goto no_symbols; -+ -+ /* add the symbol nodes (if any) */ -+ if (tree->symbols) { -+ -+ emit->beginnode(etarget, NULL); -+ emit->string(etarget, "__symbols__", 0); -+ emit->align(etarget, sizeof(cell_t)); -+ -+ for_each_symbol(tree, sym) { -+ -+ vallen = strlen(sym->node->fullpath); -+ -+ nameoff = stringtable_insert(strbuf, sym->label->label); -+ -+ emit->property(etarget, NULL); -+ emit->cell(etarget, vallen + 1); -+ emit->cell(etarget, nameoff); -+ -+ if ((vi->flags & FTF_VARALIGN) && vallen >= 8) -+ emit->align(etarget, 8); -+ -+ emit->string(etarget, sym->node->fullpath, -+ strlen(sym->node->fullpath)); -+ emit->align(etarget, sizeof(cell_t)); -+ } -+ -+ emit->endnode(etarget, NULL); -+ } -+ -+ /* add the fixup nodes */ -+ if (tree->fixups) { -+ -+ /* emit the external fixups */ -+ emit->beginnode(etarget, NULL); -+ emit->string(etarget, "__fixups__", 0); -+ emit->align(etarget, sizeof(cell_t)); -+ -+ for_each_fixup(tree, f) { -+ -+ namesz = 0; -+ for_each_fixup_entry(f, fe) { -+ fullpath = fe->node->fullpath; -+ if (fullpath[0] == '\0') -+ fullpath = "/"; -+ namesz += strlen(fullpath) + 1; -+ namesz += strlen(fe->prop->name) + 1; -+ namesz += 32; /* space for : + '\0' */ -+ } -+ -+ name = xmalloc(namesz); -+ -+ s = name; -+ for_each_fixup_entry(f, fe) { -+ fullpath = fe->node->fullpath; -+ if (fullpath[0] == '\0') -+ fullpath = "/"; -+ snprintf(s, name + namesz - s, "%s:%s:%d", -+ fullpath, -+ fe->prop->name, fe->offset); -+ s += strlen(s) + 1; -+ } -+ -+ nameoff = stringtable_insert(strbuf, f->ref); -+ vallen = s - name - 1; -+ -+ emit->property(etarget, NULL); -+ emit->cell(etarget, vallen + 1); -+ emit->cell(etarget, nameoff); -+ -+ if ((vi->flags & FTF_VARALIGN) && vallen >= 8) -+ emit->align(etarget, 8); -+ -+ emit->string(etarget, name, vallen); -+ emit->align(etarget, sizeof(cell_t)); -+ -+ free(name); -+ } -+ -+ emit->endnode(etarget, tree->labels); -+ } -+ -+ /* add the local fixup property */ -+ if (tree->local_fixups) { -+ -+ /* emit the external fixups */ -+ emit->beginnode(etarget, NULL); -+ emit->string(etarget, "__local_fixups__", 0); -+ emit->align(etarget, sizeof(cell_t)); -+ -+ namesz = 0; -+ for_each_local_fixup_entry(tree, fe) { -+ fullpath = fe->node->fullpath; -+ if (fullpath[0] == '\0') -+ fullpath = "/"; -+ namesz += strlen(fullpath) + 1; -+ namesz += strlen(fe->prop->name) + 1; -+ namesz += 32; /* space for : + '\0' */ -+ } -+ -+ name = xmalloc(namesz); -+ -+ s = name; -+ for_each_local_fixup_entry(tree, fe) { -+ fullpath = fe->node->fullpath; -+ if (fullpath[0] == '\0') -+ fullpath = "/"; -+ snprintf(s, name + namesz - s, "%s:%s:%d", -+ fullpath, fe->prop->name, -+ fe->offset); -+ s += strlen(s) + 1; -+ } -+ -+ nameoff = stringtable_insert(strbuf, "fixup"); -+ vallen = s - name - 1; -+ -+ emit->property(etarget, NULL); -+ emit->cell(etarget, vallen + 1); -+ emit->cell(etarget, nameoff); -+ -+ if ((vi->flags & FTF_VARALIGN) && vallen >= 8) -+ emit->align(etarget, 8); -+ -+ emit->string(etarget, name, vallen); -+ emit->align(etarget, sizeof(cell_t)); -+ -+ free(name); -+ -+ emit->endnode(etarget, tree->labels); -+ } -+ -+no_symbols: - emit->endnode(etarget, tree->labels); - } - -diff -Nur linux-4.1.13.orig/scripts/dtc/fstree.c linux-rpi/scripts/dtc/fstree.c ---- linux-4.1.13.orig/scripts/dtc/fstree.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/scripts/dtc/fstree.c 2015-11-29 09:42:41.406999830 +0100 -@@ -37,26 +37,26 @@ - tree = build_node(NULL, NULL); - - while ((de = readdir(d)) != NULL) { -- char *tmpnam; -+ char *tmpname; - - if (streq(de->d_name, ".") - || streq(de->d_name, "..")) - continue; - -- tmpnam = join_path(dirname, de->d_name); -+ tmpname = join_path(dirname, de->d_name); - -- if (lstat(tmpnam, &st) < 0) -- die("stat(%s): %s\n", tmpnam, strerror(errno)); -+ if (lstat(tmpname, &st) < 0) -+ die("stat(%s): %s\n", tmpname, strerror(errno)); - - if (S_ISREG(st.st_mode)) { - struct property *prop; - FILE *pfile; - -- pfile = fopen(tmpnam, "r"); -+ pfile = fopen(tmpname, "rb"); - if (! pfile) { - fprintf(stderr, - "WARNING: Cannot open %s: %s\n", -- tmpnam, strerror(errno)); -+ tmpname, strerror(errno)); - } else { - prop = build_property(xstrdup(de->d_name), - data_copy_file(pfile, -@@ -67,12 +67,12 @@ - } else if (S_ISDIR(st.st_mode)) { - struct node *newchild; - -- newchild = read_fstree(tmpnam); -+ newchild = read_fstree(tmpname); - newchild = name_node(newchild, xstrdup(de->d_name)); - add_child(tree, newchild); - } - -- free(tmpnam); -+ free(tmpname); - } - - closedir(d); -diff -Nur linux-4.1.13.orig/scripts/dtc/livetree.c linux-rpi/scripts/dtc/livetree.c ---- linux-4.1.13.orig/scripts/dtc/livetree.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/scripts/dtc/livetree.c 2015-11-29 09:42:41.410999565 +0100 -@@ -511,7 +511,9 @@ - - struct node *get_node_by_ref(struct node *tree, const char *ref) - { -- if (ref[0] == '/') -+ if (streq(ref, "/")) -+ return tree; -+ else if (ref[0] == '/') - return get_node_by_path(tree, ref); - else - return get_node_by_label(tree, ref); -diff -Nur linux-4.1.13.orig/scripts/dtc/srcpos.c linux-rpi/scripts/dtc/srcpos.c ---- linux-4.1.13.orig/scripts/dtc/srcpos.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/scripts/dtc/srcpos.c 2015-11-29 09:42:41.410999565 +0100 -@@ -34,7 +34,7 @@ - static struct search_path *search_path_head, **search_path_tail; - - --static char *dirname(const char *path) -+static char *get_dirname(const char *path) - { - const char *slash = strrchr(path, '/'); - -@@ -77,7 +77,7 @@ - else - fullname = join_path(dirname, fname); - -- *fp = fopen(fullname, "r"); -+ *fp = fopen(fullname, "rb"); - if (!*fp) { - free(fullname); - fullname = NULL; -@@ -150,7 +150,7 @@ - srcfile = xmalloc(sizeof(*srcfile)); - - srcfile->f = srcfile_relative_open(fname, &srcfile->name); -- srcfile->dir = dirname(srcfile->name); -+ srcfile->dir = get_dirname(srcfile->name); - srcfile->prev = current_srcfile; - - srcfile->lineno = 1; -@@ -159,7 +159,7 @@ - current_srcfile = srcfile; - } - --int srcfile_pop(void) -+bool srcfile_pop(void) - { - struct srcfile_state *srcfile = current_srcfile; - -@@ -177,7 +177,7 @@ - * fix this we could either allocate all the files from a - * table, or use a pool allocator. */ - -- return current_srcfile ? 1 : 0; -+ return current_srcfile ? true : false; - } - - void srcfile_add_search_path(const char *dirname) -@@ -290,42 +290,27 @@ - return pos_str; - } - --void --srcpos_verror(struct srcpos *pos, char const *fmt, va_list va) -+void srcpos_verror(struct srcpos *pos, const char *prefix, -+ const char *fmt, va_list va) - { -- const char *srcstr; -- -- srcstr = srcpos_string(pos); -+ char *srcstr; - -- fprintf(stderr, "Error: %s ", srcstr); -- vfprintf(stderr, fmt, va); -- fprintf(stderr, "\n"); --} -+ srcstr = srcpos_string(pos); - --void --srcpos_error(struct srcpos *pos, char const *fmt, ...) --{ -- va_list va; -+ fprintf(stderr, "%s: %s ", prefix, srcstr); -+ vfprintf(stderr, fmt, va); -+ fprintf(stderr, "\n"); - -- va_start(va, fmt); -- srcpos_verror(pos, fmt, va); -- va_end(va); -+ free(srcstr); - } - -- --void --srcpos_warn(struct srcpos *pos, char const *fmt, ...) -+void srcpos_error(struct srcpos *pos, const char *prefix, -+ const char *fmt, ...) - { -- const char *srcstr; - va_list va; -- va_start(va, fmt); -- -- srcstr = srcpos_string(pos); -- -- fprintf(stderr, "Warning: %s ", srcstr); -- vfprintf(stderr, fmt, va); -- fprintf(stderr, "\n"); - -+ va_start(va, fmt); -+ srcpos_verror(pos, prefix, fmt, va); - va_end(va); - } - -diff -Nur linux-4.1.13.orig/scripts/dtc/srcpos.h linux-rpi/scripts/dtc/srcpos.h ---- linux-4.1.13.orig/scripts/dtc/srcpos.h 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/scripts/dtc/srcpos.h 2015-11-29 09:42:41.410999565 +0100 -@@ -21,6 +21,7 @@ - #define _SRCPOS_H_ - - #include -+#include - - struct srcfile_state { - FILE *f; -@@ -55,7 +56,7 @@ - FILE *srcfile_relative_open(const char *fname, char **fullnamep); - - void srcfile_push(const char *fname); --int srcfile_pop(void); -+bool srcfile_pop(void); - - /** - * Add a new directory to the search path for input files -@@ -106,12 +107,12 @@ - extern char *srcpos_string(struct srcpos *pos); - extern void srcpos_dump(struct srcpos *pos); - --extern void srcpos_verror(struct srcpos *pos, char const *, va_list va) -- __attribute__((format(printf, 2, 0))); --extern void srcpos_error(struct srcpos *pos, char const *, ...) -- __attribute__((format(printf, 2, 3))); --extern void srcpos_warn(struct srcpos *pos, char const *, ...) -- __attribute__((format(printf, 2, 3))); -+extern void srcpos_verror(struct srcpos *pos, const char *prefix, -+ const char *fmt, va_list va) -+ __attribute__((format(printf, 3, 0))); -+extern void srcpos_error(struct srcpos *pos, const char *prefix, -+ const char *fmt, ...) -+ __attribute__((format(printf, 3, 4))); - - extern void srcpos_set_line(char *f, int l); - -diff -Nur linux-4.1.13.orig/scripts/dtc/treesource.c linux-rpi/scripts/dtc/treesource.c ---- linux-4.1.13.orig/scripts/dtc/treesource.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/scripts/dtc/treesource.c 2015-11-29 09:42:41.410999565 +0100 -@@ -26,12 +26,12 @@ - extern YYLTYPE yylloc; - - struct boot_info *the_boot_info; --int treesource_error; -+bool treesource_error; - - struct boot_info *dt_from_source(const char *fname) - { - the_boot_info = NULL; -- treesource_error = 0; -+ treesource_error = false; - - srcfile_push(fname); - yyin = current_srcfile->f; -@@ -54,9 +54,9 @@ - fputc('\t', f); - } - --static int isstring(char c) -+static bool isstring(char c) - { -- return (isprint(c) -+ return (isprint((unsigned char)c) - || (c == '\0') - || strchr("\a\b\t\n\v\f\r", c)); - } -@@ -109,7 +109,7 @@ - break; - case '\0': - fprintf(f, "\", "); -- while (m && (m->offset < i)) { -+ while (m && (m->offset <= (i + 1))) { - if (m->type == LABEL) { - assert(m->offset == (i+1)); - fprintf(f, "%s: ", m->ref); -@@ -119,7 +119,7 @@ - fprintf(f, "\""); - break; - default: -- if (isprint(c)) -+ if (isprint((unsigned char)c)) - fprintf(f, "%c", c); - else - fprintf(f, "\\x%02hhx", c); -@@ -178,7 +178,7 @@ - m = m->next; - } - -- fprintf(f, "%02hhx", *bp++); -+ fprintf(f, "%02hhx", (unsigned char)(*bp++)); - if ((const void *)bp >= propend) - break; - fprintf(f, " "); -diff -Nur linux-4.1.13.orig/scripts/dtc/util.c linux-rpi/scripts/dtc/util.c ---- linux-4.1.13.orig/scripts/dtc/util.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/scripts/dtc/util.c 2015-11-29 09:42:41.410999565 +0100 -@@ -39,11 +39,11 @@ - char *xstrdup(const char *s) - { - int len = strlen(s) + 1; -- char *dup = xmalloc(len); -+ char *d = xmalloc(len); - -- memcpy(dup, s, len); -+ memcpy(d, s, len); - -- return dup; -+ return d; - } - - char *join_path(const char *path, const char *name) -@@ -70,7 +70,7 @@ - return str; - } - --int util_is_printable_string(const void *data, int len) -+bool util_is_printable_string(const void *data, int len) - { - const char *s = data; - const char *ss, *se; -@@ -87,7 +87,7 @@ - - while (s < se) { - ss = s; -- while (s < se && *s && isprint(*s)) -+ while (s < se && *s && isprint((unsigned char)*s)) - s++; - - /* not zero, or not done yet */ -@@ -219,10 +219,6 @@ - if (offset == bufsize) { - bufsize *= 2; - buf = xrealloc(buf, bufsize); -- if (!buf) { -- ret = ENOMEM; -- break; -- } - } - - ret = read(fd, &buf[offset], bufsize - offset); -@@ -375,9 +371,9 @@ - const uint32_t *cell = (const uint32_t *)data; - - printf(" = <"); -- for (i = 0; i < len; i += 4) -+ for (i = 0, len /= 4; i < len; i++) - printf("0x%08x%s", fdt32_to_cpu(cell[i]), -- i < (len - 4) ? " " : ""); -+ i < (len - 1) ? " " : ""); - printf(">"); - } else { - printf(" = ["); -diff -Nur linux-4.1.13.orig/scripts/dtc/util.h linux-rpi/scripts/dtc/util.h ---- linux-4.1.13.orig/scripts/dtc/util.h 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/scripts/dtc/util.h 2015-11-29 09:42:41.410999565 +0100 -@@ -2,6 +2,7 @@ - #define _UTIL_H - - #include -+#include - #include - - /* -@@ -33,6 +34,7 @@ - va_start(ap, str); - fprintf(stderr, "FATAL ERROR: "); - vfprintf(stderr, str, ap); -+ va_end(ap); - exit(1); - } - -@@ -68,7 +70,7 @@ - * @param len The string length including terminator - * @return 1 if a valid printable string, 0 if not - */ --int util_is_printable_string(const void *data, int len); -+bool util_is_printable_string(const void *data, int len); - - /* - * Parse an escaped character starting at index i in string s. The resulting -diff -Nur linux-4.1.13.orig/scripts/dtc/version_gen.h linux-rpi/scripts/dtc/version_gen.h ---- linux-4.1.13.orig/scripts/dtc/version_gen.h 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/scripts/dtc/version_gen.h 2015-11-29 09:42:41.410999565 +0100 -@@ -1 +1 @@ --#define DTC_VERSION "DTC 1.4.0-dirty" -+#define DTC_VERSION "DTC 1.4.1-g36c70742" -diff -Nur linux-4.1.13.orig/scripts/knlinfo linux-rpi/scripts/knlinfo ---- linux-4.1.13.orig/scripts/knlinfo 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/scripts/knlinfo 2015-11-29 09:42:41.418999033 +0100 -@@ -0,0 +1,168 @@ -+#!/usr/bin/env perl -+# ---------------------------------------------------------------------- -+# knlinfo by Phil Elwell for Raspberry Pi -+# -+# (c) 2014,2015 Raspberry Pi (Trading) Limited -+# -+# Licensed under the terms of the GNU General Public License. -+# ---------------------------------------------------------------------- -+ -+use strict; -+use integer; -+ -+use Fcntl ":seek"; -+ -+my $trailer_magic = 'RPTL'; -+ -+my %atom_formats = -+( -+ 'DTOK' => \&format_bool, -+ 'KVer' => \&format_string, -+ '283x' => \&format_bool, -+); -+ -+if (@ARGV != 1) -+{ -+ print ("Usage: knlinfo \n"); -+ exit(1); -+} -+ -+my $kernel_file = $ARGV[0]; -+ -+ -+my ($atoms, $pos) = read_trailer($kernel_file); -+ -+exit(1) if (!$atoms); -+ -+printf("Kernel trailer found at %d/0x%x:\n", $pos, $pos); -+ -+foreach my $atom (@$atoms) -+{ -+ printf(" %s: %s\n", $atom->[0], format_atom($atom)); -+} -+ -+exit(0); -+ -+sub read_trailer -+{ -+ my ($kernel_file) = @_; -+ my $fh; -+ -+ if (!open($fh, '<', $kernel_file)) -+ { -+ print ("* Failed to open '$kernel_file'\n"); -+ return undef; -+ } -+ -+ if (!seek($fh, -12, SEEK_END)) -+ { -+ print ("* seek error in '$kernel_file'\n"); -+ return undef; -+ } -+ -+ my $last_bytes; -+ sysread($fh, $last_bytes, 12); -+ -+ my ($trailer_len, $data_len, $magic) = unpack('VVa4', $last_bytes); -+ -+ if (($magic ne $trailer_magic) || ($data_len != 4)) -+ { -+ print ("* no trailer\n"); -+ return undef; -+ } -+ if (!seek($fh, -12, SEEK_END)) -+ { -+ print ("* seek error in '$kernel_file'\n"); -+ return undef; -+ } -+ -+ $trailer_len -= 12; -+ -+ while ($trailer_len > 0) -+ { -+ if ($trailer_len < 8) -+ { -+ print ("* truncated atom header in trailer\n"); -+ return undef; -+ } -+ if (!seek($fh, -8, SEEK_CUR)) -+ { -+ print ("* seek error in '$kernel_file'\n"); -+ return undef; -+ } -+ $trailer_len -= 8; -+ -+ my $atom_hdr; -+ sysread($fh, $atom_hdr, 8); -+ my ($atom_len, $atom_type) = unpack('Va4', $atom_hdr); -+ -+ if ($trailer_len < $atom_len) -+ { -+ print ("* truncated atom data in trailer\n"); -+ return undef; -+ } -+ -+ my $rounded_len = (($atom_len + 3) & ~3); -+ if (!seek($fh, -(8 + $rounded_len), SEEK_CUR)) -+ { -+ print ("* seek error in '$kernel_file'\n"); -+ return undef; -+ } -+ $trailer_len -= $rounded_len; -+ -+ my $atom_data; -+ sysread($fh, $atom_data, $atom_len); -+ -+ if (!seek($fh, -$atom_len, SEEK_CUR)) -+ { -+ print ("* seek error in '$kernel_file'\n"); -+ return undef; -+ } -+ -+ push @$atoms, [ $atom_type, $atom_data ]; -+ } -+ -+ if (($$atoms[-1][0] eq "\x00\x00\x00\x00") && -+ ($$atoms[-1][1] eq "")) -+ { -+ pop @$atoms; -+ } -+ else -+ { -+ print ("* end marker missing from trailer\n"); -+ } -+ -+ return ($atoms, tell($fh)); -+} -+ -+sub format_atom -+{ -+ my ($atom) = @_; -+ -+ my $format_func = $atom_formats{$atom->[0]} || \&format_hex; -+ return $format_func->($atom->[1]); -+} -+ -+sub format_bool -+{ -+ my ($data) = @_; -+ return unpack('V', $data) ? 'true' : 'false'; -+} -+ -+sub format_int -+{ -+ my ($data) = @_; -+ return unpack('V', $data); -+} -+ -+sub format_string -+{ -+ my ($data) = @_; -+ return '"'.$data.'"'; -+} -+ -+sub format_hex -+{ -+ my ($data) = @_; -+ return unpack('H*', $data); -+} -diff -Nur linux-4.1.13.orig/scripts/mkknlimg linux-rpi/scripts/mkknlimg ---- linux-4.1.13.orig/scripts/mkknlimg 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/scripts/mkknlimg 2015-11-29 09:42:41.422998767 +0100 -@@ -0,0 +1,244 @@ -+#!/usr/bin/env perl -+# ---------------------------------------------------------------------- -+# mkknlimg by Phil Elwell for Raspberry Pi -+# based on extract-ikconfig by Dick Streefland -+# -+# (c) 2009,2010 Dick Streefland -+# (c) 2014,2015 Raspberry Pi (Trading) Limited -+# -+# Licensed under the terms of the GNU General Public License. -+# ---------------------------------------------------------------------- -+ -+use strict; -+use warnings; -+use integer; -+ -+my $trailer_magic = 'RPTL'; -+ -+my $tmpfile1 = "/tmp/mkknlimg_$$.1"; -+my $tmpfile2 = "/tmp/mkknlimg_$$.2"; -+ -+my $dtok = 0; -+my $is_283x = 0; -+ -+while (@ARGV && ($ARGV[0] =~ /^-/)) -+{ -+ my $arg = shift(@ARGV); -+ if ($arg eq '--dtok') -+ { -+ $dtok = 1; -+ } -+ elsif ($arg eq '--283x') -+ { -+ $is_283x = 1; -+ } -+ else -+ { -+ print ("* Unknown option '$arg'\n"); -+ usage(); -+ } -+} -+ -+usage() if (@ARGV != 2); -+ -+my $kernel_file = $ARGV[0]; -+my $out_file = $ARGV[1]; -+ -+if (! -r $kernel_file) -+{ -+ print ("* File '$kernel_file' not found\n"); -+ usage(); -+} -+ -+my @wanted_strings = -+( -+ 'bcm2708_fb', -+ 'brcm,bcm2835-mmc', -+ 'brcm,bcm2835-sdhost', -+ 'brcm,bcm2708-pinctrl', -+ 'brcm,bcm2835-gpio', -+ 'brcm,bcm2835', -+ 'brcm,bcm2836' -+); -+ -+my $res = try_extract($kernel_file, $tmpfile1); -+$res = try_decompress('\037\213\010', 'xy', 'gunzip', 0, -+ $kernel_file, $tmpfile1, $tmpfile2) if (!$res); -+$res = try_decompress('\3757zXZ\000', 'abcde', 'unxz --single-stream', -1, -+ $kernel_file, $tmpfile1, $tmpfile2) if (!$res); -+$res = try_decompress('BZh', 'xy', 'bunzip2', 0, -+ $kernel_file, $tmpfile1, $tmpfile2) if (!$res); -+$res = try_decompress('\135\0\0\0', 'xxx', 'unlzma', 0, -+ $kernel_file, $tmpfile1, $tmpfile2) if (!$res); -+$res = try_decompress('\211\114\132', 'xy', 'lzop -d', 0, -+ $kernel_file, $tmpfile1, $tmpfile2) if (!$res); -+$res = try_decompress('\002\041\114\030', 'xy', 'lz4 -d', 1, -+ $kernel_file, $tmpfile1, $tmpfile2) if (!$res); -+ -+my $append_trailer; -+my $trailer; -+my $kver = '?'; -+ -+$append_trailer = $dtok; -+ -+if ($res) -+{ -+ $kver = $res->{''} || '?'; -+ print("Version: $kver\n"); -+ -+ $append_trailer = $dtok; -+ if (!$dtok) -+ { -+ if (config_bool($res, 'bcm2708_fb') || -+ config_bool($res, 'brcm,bcm2835-mmc') || -+ config_bool($res, 'brcm,bcm2835-sdhost')) -+ { -+ $dtok ||= config_bool($res, 'brcm,bcm2708-pinctrl'); -+ $dtok ||= config_bool($res, 'brcm,bcm2835-gpio'); -+ $is_283x ||= config_bool($res, 'brcm,bcm2835'); -+ $is_283x ||= config_bool($res, 'brcm,bcm2836'); -+ $dtok ||= $is_283x; -+ $append_trailer = 1; -+ } -+ else -+ { -+ print ("* This doesn't look like a Raspberry Pi kernel. In pass-through mode.\n"); -+ } -+ } -+} -+elsif (!$dtok) -+{ -+ print ("* Is this a valid kernel? In pass-through mode.\n"); -+} -+ -+if ($append_trailer) -+{ -+ printf("DT: %s\n", $dtok ? "y" : "n"); -+ printf("283x: %s\n", $is_283x ? "y" : "n"); -+ -+ my @atoms; -+ -+ push @atoms, [ $trailer_magic, pack('V', 0) ]; -+ push @atoms, [ 'KVer', $kver ]; -+ push @atoms, [ 'DTOK', pack('V', $dtok) ]; -+ push @atoms, [ '283x', pack('V', $is_283x) ]; -+ -+ $trailer = pack_trailer(\@atoms); -+ $atoms[0]->[1] = pack('V', length($trailer)); -+ -+ $trailer = pack_trailer(\@atoms); -+} -+ -+my $ofh; -+my $total_len = 0; -+ -+if ($out_file eq $kernel_file) -+{ -+ die "* Failed to open '$out_file' for append\n" -+ if (!open($ofh, '>>', $out_file)); -+ $total_len = tell($ofh); -+} -+else -+{ -+ die "* Failed to open '$kernel_file'\n" -+ if (!open(my $ifh, '<', $kernel_file)); -+ die "* Failed to create '$out_file'\n" -+ if (!open($ofh, '>', $out_file)); -+ -+ my $copybuf; -+ while (1) -+ { -+ my $bytes = sysread($ifh, $copybuf, 64*1024); -+ last if (!$bytes); -+ syswrite($ofh, $copybuf, $bytes); -+ $total_len += $bytes; -+ } -+ close($ifh); -+} -+ -+if ($trailer) -+{ -+ # Pad to word-alignment -+ syswrite($ofh, "\x000\x000\x000", (-$total_len & 0x3)); -+ syswrite($ofh, $trailer); -+} -+ -+close($ofh); -+ -+exit($trailer ? 0 : 1); -+ -+END { -+ unlink($tmpfile1) if ($tmpfile1); -+ unlink($tmpfile2) if ($tmpfile2); -+} -+ -+ -+sub usage -+{ -+ print ("Usage: mkknlimg [--dtok] [--283x] \n"); -+ exit(1); -+} -+ -+sub try_extract -+{ -+ my ($knl, $tmp) = @_; -+ -+ my $ver = `strings "$knl" | grep -a -E "^Linux version [1-9]"`; -+ -+ return undef if (!$ver); -+ -+ chomp($ver); -+ -+ my $res = { ''=>$ver }; -+ my $string_pattern = '^('.join('|', @wanted_strings).')$'; -+ -+ my @matches = `strings \"$knl\" | grep -E \"$string_pattern\"`; -+ foreach my $match (@matches) -+ { -+ chomp($match); -+ $res->{$match} = 1; -+ } -+ -+ return $res; -+} -+ -+ -+sub try_decompress -+{ -+ my ($magic, $subst, $zcat, $idx, $knl, $tmp1, $tmp2) = @_; -+ -+ my $pos = `tr "$magic\n$subst" "\n$subst=" < "$knl" | grep -abo "^$subst"`; -+ if ($pos) -+ { -+ chomp($pos); -+ $pos = (split(/[\r\n]+/, $pos))[$idx]; -+ return undef if (!defined($pos)); -+ $pos =~ s/:.*[\r\n]*$//s; -+ my $cmd = "tail -c+$pos \"$knl\" | $zcat > $tmp2 2> /dev/null"; -+ my $err = (system($cmd) >> 8); -+ return undef if (($err != 0) && ($err != 2)); -+ -+ return try_extract($tmp2, $tmp1); -+ } -+ -+ return undef; -+} -+ -+sub pack_trailer -+{ -+ my ($atoms) = @_; -+ my $trailer = pack('VV', 0, 0); -+ for (my $i = $#$atoms; $i>=0; $i--) -+ { -+ my $atom = $atoms->[$i]; -+ $trailer .= pack('a*x!4Va4', $atom->[1], length($atom->[1]), $atom->[0]); -+ } -+ return $trailer; -+} -+ -+sub config_bool -+{ -+ my ($configs, $wanted) = @_; -+ my $val = $configs->{$wanted} || 'n'; -+ return (($val eq 'y') || ($val eq '1')); -+} -diff -Nur linux-4.1.13.orig/sound/arm/bcm2835.c linux-rpi/sound/arm/bcm2835.c ---- linux-4.1.13.orig/sound/arm/bcm2835.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/sound/arm/bcm2835.c 2015-11-29 09:42:41.446997173 +0100 -@@ -0,0 +1,511 @@ -+/***************************************************************************** -+* Copyright 2011 Broadcom Corporation. All rights reserved. -+* -+* Unless you and Broadcom execute a separate written software license -+* agreement governing use of this software, this software is licensed to you -+* under the terms of the GNU General Public License version 2, available at -+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -+* -+* Notwithstanding the above, under no circumstances may you combine this -+* software in any way with any other Broadcom software provided under a -+* license other than the GPL, without Broadcom's express prior written -+* consent. -+*****************************************************************************/ -+ -+#include -+ -+#include -+#include -+#include -+#include -+ -+#include "bcm2835.h" -+ -+/* module parameters (see "Module Parameters") */ -+/* SNDRV_CARDS: maximum number of cards supported by this module */ -+static int index[MAX_SUBSTREAMS] = {[0 ... (MAX_SUBSTREAMS - 1)] = -1 }; -+static char *id[MAX_SUBSTREAMS] = {[0 ... (MAX_SUBSTREAMS - 1)] = NULL }; -+static int enable[MAX_SUBSTREAMS] = {[0 ... (MAX_SUBSTREAMS - 1)] = 1 }; -+ -+/* HACKY global pointers needed for successive probes to work : ssp -+ * But compared against the changes we will have to do in VC audio_ipc code -+ * to export 8 audio_ipc devices as a single IPC device and then monitor all -+ * four devices in a thread, this gets things done quickly and should be easier -+ * to debug if we run into issues -+ */ -+ -+static struct snd_card *g_card = NULL; -+static bcm2835_chip_t *g_chip = NULL; -+ -+static int snd_bcm2835_free(bcm2835_chip_t * chip) -+{ -+ kfree(chip); -+ return 0; -+} -+ -+/* component-destructor -+ * (see "Management of Cards and Components") -+ */ -+static int snd_bcm2835_dev_free(struct snd_device *device) -+{ -+ return snd_bcm2835_free(device->device_data); -+} -+ -+/* chip-specific constructor -+ * (see "Management of Cards and Components") -+ */ -+static int snd_bcm2835_create(struct snd_card *card, -+ struct platform_device *pdev, -+ bcm2835_chip_t ** rchip) -+{ -+ bcm2835_chip_t *chip; -+ int err; -+ static struct snd_device_ops ops = { -+ .dev_free = snd_bcm2835_dev_free, -+ }; -+ -+ *rchip = NULL; -+ -+ chip = kzalloc(sizeof(*chip), GFP_KERNEL); -+ if (chip == NULL) -+ return -ENOMEM; -+ -+ chip->card = card; -+ -+ err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); -+ if (err < 0) { -+ snd_bcm2835_free(chip); -+ return err; -+ } -+ -+ *rchip = chip; -+ return 0; -+} -+ -+static int snd_bcm2835_alsa_probe_dt(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ bcm2835_chip_t *chip; -+ struct snd_card *card; -+ u32 numchans; -+ int err, i; -+ -+ err = of_property_read_u32(dev->of_node, "brcm,pwm-channels", -+ &numchans); -+ if (err) { -+ dev_err(dev, "Failed to get DT property 'brcm,pwm-channels'"); -+ return err; -+ } -+ -+ if (numchans == 0 || numchans > MAX_SUBSTREAMS) { -+ numchans = MAX_SUBSTREAMS; -+ dev_warn(dev, "Illegal 'brcm,pwm-channels' value, will use %u\n", -+ numchans); -+ } -+ -+ err = snd_card_new(NULL, -1, NULL, THIS_MODULE, 0, &card); -+ if (err) { -+ dev_err(dev, "Failed to create soundcard structure\n"); -+ return err; -+ } -+ -+ snd_card_set_dev(card, dev); -+ strcpy(card->driver, "bcm2835"); -+ strcpy(card->shortname, "bcm2835 ALSA"); -+ sprintf(card->longname, "%s", card->shortname); -+ -+ err = snd_bcm2835_create(card, pdev, &chip); -+ if (err < 0) { -+ dev_err(dev, "Failed to create bcm2835 chip\n"); -+ goto err_free; -+ } -+ -+ err = snd_bcm2835_new_pcm(chip); -+ if (err < 0) { -+ dev_err(dev, "Failed to create new bcm2835 pcm device\n"); -+ goto err_free; -+ } -+ -+ err = snd_bcm2835_new_spdif_pcm(chip); -+ if (err < 0) { -+ dev_err(dev, "Failed to create new bcm2835 spdif pcm device\n"); -+ goto err_free; -+ } -+ -+ err = snd_bcm2835_new_ctl(chip); -+ if (err < 0) { -+ dev_err(dev, "Failed to create new bcm2835 ctl\n"); -+ goto err_free; -+ } -+ -+ for (i = 0; i < numchans; i++) { -+ chip->avail_substreams |= (1 << i); -+ chip->pdev[i] = pdev; -+ } -+ -+ err = snd_card_register(card); -+ if (err) { -+ dev_err(dev, "Failed to register bcm2835 ALSA card \n"); -+ goto err_free; -+ } -+ -+ g_card = card; -+ g_chip = chip; -+ platform_set_drvdata(pdev, card); -+ audio_info("bcm2835 ALSA card created with %u channels\n", numchans); -+ -+ return 0; -+ -+err_free: -+ snd_card_free(card); -+ -+ return err; -+} -+ -+static int snd_bcm2835_alsa_probe(struct platform_device *pdev) -+{ -+ static int dev; -+ bcm2835_chip_t *chip; -+ struct snd_card *card; -+ int err; -+ -+ if (pdev->dev.of_node) -+ return snd_bcm2835_alsa_probe_dt(pdev); -+ -+ if (dev >= MAX_SUBSTREAMS) -+ return -ENODEV; -+ -+ if (!enable[dev]) { -+ dev++; -+ return -ENOENT; -+ } -+ -+ if (dev > 0) -+ goto add_register_map; -+ -+ err = snd_card_new(NULL, index[dev], id[dev], THIS_MODULE, 0, &g_card); -+ if (err < 0) -+ goto out; -+ -+ snd_card_set_dev(g_card, &pdev->dev); -+ strcpy(g_card->driver, "bcm2835"); -+ strcpy(g_card->shortname, "bcm2835 ALSA"); -+ sprintf(g_card->longname, "%s", g_card->shortname); -+ -+ err = snd_bcm2835_create(g_card, pdev, &chip); -+ if (err < 0) { -+ dev_err(&pdev->dev, "Failed to create bcm2835 chip\n"); -+ goto out_bcm2835_create; -+ } -+ -+ g_chip = chip; -+ err = snd_bcm2835_new_pcm(chip); -+ if (err < 0) { -+ dev_err(&pdev->dev, "Failed to create new BCM2835 pcm device\n"); -+ goto out_bcm2835_new_pcm; -+ } -+ -+ err = snd_bcm2835_new_spdif_pcm(chip); -+ if (err < 0) { -+ dev_err(&pdev->dev, "Failed to create new BCM2835 spdif pcm device\n"); -+ goto out_bcm2835_new_spdif; -+ } -+ -+ err = snd_bcm2835_new_ctl(chip); -+ if (err < 0) { -+ dev_err(&pdev->dev, "Failed to create new BCM2835 ctl\n"); -+ goto out_bcm2835_new_ctl; -+ } -+ -+add_register_map: -+ card = g_card; -+ chip = g_chip; -+ -+ BUG_ON(!(card && chip)); -+ -+ chip->avail_substreams |= (1 << dev); -+ chip->pdev[dev] = pdev; -+ -+ if (dev == 0) { -+ err = snd_card_register(card); -+ if (err < 0) { -+ dev_err(&pdev->dev, -+ "Failed to register bcm2835 ALSA card \n"); -+ goto out_card_register; -+ } -+ platform_set_drvdata(pdev, card); -+ audio_info("bcm2835 ALSA card created!\n"); -+ } else { -+ audio_info("bcm2835 ALSA chip created!\n"); -+ platform_set_drvdata(pdev, (void *)dev); -+ } -+ -+ dev++; -+ -+ return 0; -+ -+out_card_register: -+out_bcm2835_new_ctl: -+out_bcm2835_new_spdif: -+out_bcm2835_new_pcm: -+out_bcm2835_create: -+ BUG_ON(!g_card); -+ if (snd_card_free(g_card)) -+ dev_err(&pdev->dev, "Failed to free Registered alsa card\n"); -+ g_card = NULL; -+out: -+ dev = SNDRV_CARDS; /* stop more avail_substreams from being probed */ -+ dev_err(&pdev->dev, "BCM2835 ALSA Probe failed !!\n"); -+ return err; -+} -+ -+static int snd_bcm2835_alsa_remove(struct platform_device *pdev) -+{ -+ uint32_t idx; -+ void *drv_data; -+ -+ drv_data = platform_get_drvdata(pdev); -+ -+ if (drv_data == (void *)g_card) { -+ /* This is the card device */ -+ snd_card_free((struct snd_card *)drv_data); -+ g_card = NULL; -+ g_chip = NULL; -+ } else { -+ idx = (uint32_t) drv_data; -+ if (g_card != NULL) { -+ BUG_ON(!g_chip); -+ /* We pass chip device numbers in audio ipc devices -+ * other than the one we registered our card with -+ */ -+ idx = (uint32_t) drv_data; -+ BUG_ON(!idx || idx > MAX_SUBSTREAMS); -+ g_chip->avail_substreams &= ~(1 << idx); -+ /* There should be atleast one substream registered -+ * after we are done here, as it wil be removed when -+ * the *remove* is called for the card device -+ */ -+ BUG_ON(!g_chip->avail_substreams); -+ } -+ } -+ -+ platform_set_drvdata(pdev, NULL); -+ -+ return 0; -+} -+ -+#ifdef CONFIG_PM -+static int snd_bcm2835_alsa_suspend(struct platform_device *pdev, -+ pm_message_t state) -+{ -+ return 0; -+} -+ -+static int snd_bcm2835_alsa_resume(struct platform_device *pdev) -+{ -+ return 0; -+} -+ -+#endif -+ -+static const struct of_device_id snd_bcm2835_of_match_table[] = { -+ { .compatible = "brcm,bcm2835-audio", }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, snd_bcm2835_of_match_table); -+ -+static struct platform_driver bcm2835_alsa0_driver = { -+ .probe = snd_bcm2835_alsa_probe, -+ .remove = snd_bcm2835_alsa_remove, -+#ifdef CONFIG_PM -+ .suspend = snd_bcm2835_alsa_suspend, -+ .resume = snd_bcm2835_alsa_resume, -+#endif -+ .driver = { -+ .name = "bcm2835_AUD0", -+ .owner = THIS_MODULE, -+ .of_match_table = snd_bcm2835_of_match_table, -+ }, -+}; -+ -+static struct platform_driver bcm2835_alsa1_driver = { -+ .probe = snd_bcm2835_alsa_probe, -+ .remove = snd_bcm2835_alsa_remove, -+#ifdef CONFIG_PM -+ .suspend = snd_bcm2835_alsa_suspend, -+ .resume = snd_bcm2835_alsa_resume, -+#endif -+ .driver = { -+ .name = "bcm2835_AUD1", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static struct platform_driver bcm2835_alsa2_driver = { -+ .probe = snd_bcm2835_alsa_probe, -+ .remove = snd_bcm2835_alsa_remove, -+#ifdef CONFIG_PM -+ .suspend = snd_bcm2835_alsa_suspend, -+ .resume = snd_bcm2835_alsa_resume, -+#endif -+ .driver = { -+ .name = "bcm2835_AUD2", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static struct platform_driver bcm2835_alsa3_driver = { -+ .probe = snd_bcm2835_alsa_probe, -+ .remove = snd_bcm2835_alsa_remove, -+#ifdef CONFIG_PM -+ .suspend = snd_bcm2835_alsa_suspend, -+ .resume = snd_bcm2835_alsa_resume, -+#endif -+ .driver = { -+ .name = "bcm2835_AUD3", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static struct platform_driver bcm2835_alsa4_driver = { -+ .probe = snd_bcm2835_alsa_probe, -+ .remove = snd_bcm2835_alsa_remove, -+#ifdef CONFIG_PM -+ .suspend = snd_bcm2835_alsa_suspend, -+ .resume = snd_bcm2835_alsa_resume, -+#endif -+ .driver = { -+ .name = "bcm2835_AUD4", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static struct platform_driver bcm2835_alsa5_driver = { -+ .probe = snd_bcm2835_alsa_probe, -+ .remove = snd_bcm2835_alsa_remove, -+#ifdef CONFIG_PM -+ .suspend = snd_bcm2835_alsa_suspend, -+ .resume = snd_bcm2835_alsa_resume, -+#endif -+ .driver = { -+ .name = "bcm2835_AUD5", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static struct platform_driver bcm2835_alsa6_driver = { -+ .probe = snd_bcm2835_alsa_probe, -+ .remove = snd_bcm2835_alsa_remove, -+#ifdef CONFIG_PM -+ .suspend = snd_bcm2835_alsa_suspend, -+ .resume = snd_bcm2835_alsa_resume, -+#endif -+ .driver = { -+ .name = "bcm2835_AUD6", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static struct platform_driver bcm2835_alsa7_driver = { -+ .probe = snd_bcm2835_alsa_probe, -+ .remove = snd_bcm2835_alsa_remove, -+#ifdef CONFIG_PM -+ .suspend = snd_bcm2835_alsa_suspend, -+ .resume = snd_bcm2835_alsa_resume, -+#endif -+ .driver = { -+ .name = "bcm2835_AUD7", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int bcm2835_alsa_device_init(void) -+{ -+ int err; -+ err = platform_driver_register(&bcm2835_alsa0_driver); -+ if (err) { -+ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err); -+ goto out; -+ } -+ -+ err = platform_driver_register(&bcm2835_alsa1_driver); -+ if (err) { -+ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err); -+ goto unregister_0; -+ } -+ -+ err = platform_driver_register(&bcm2835_alsa2_driver); -+ if (err) { -+ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err); -+ goto unregister_1; -+ } -+ -+ err = platform_driver_register(&bcm2835_alsa3_driver); -+ if (err) { -+ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err); -+ goto unregister_2; -+ } -+ -+ err = platform_driver_register(&bcm2835_alsa4_driver); -+ if (err) { -+ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err); -+ goto unregister_3; -+ } -+ -+ err = platform_driver_register(&bcm2835_alsa5_driver); -+ if (err) { -+ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err); -+ goto unregister_4; -+ } -+ -+ err = platform_driver_register(&bcm2835_alsa6_driver); -+ if (err) { -+ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err); -+ goto unregister_5; -+ } -+ -+ err = platform_driver_register(&bcm2835_alsa7_driver); -+ if (err) { -+ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err); -+ goto unregister_6; -+ } -+ -+ return 0; -+ -+unregister_6: -+ platform_driver_unregister(&bcm2835_alsa6_driver); -+unregister_5: -+ platform_driver_unregister(&bcm2835_alsa5_driver); -+unregister_4: -+ platform_driver_unregister(&bcm2835_alsa4_driver); -+unregister_3: -+ platform_driver_unregister(&bcm2835_alsa3_driver); -+unregister_2: -+ platform_driver_unregister(&bcm2835_alsa2_driver); -+unregister_1: -+ platform_driver_unregister(&bcm2835_alsa1_driver); -+unregister_0: -+ platform_driver_unregister(&bcm2835_alsa0_driver); -+out: -+ return err; -+} -+ -+static void bcm2835_alsa_device_exit(void) -+{ -+ platform_driver_unregister(&bcm2835_alsa0_driver); -+ platform_driver_unregister(&bcm2835_alsa1_driver); -+ platform_driver_unregister(&bcm2835_alsa2_driver); -+ platform_driver_unregister(&bcm2835_alsa3_driver); -+ platform_driver_unregister(&bcm2835_alsa4_driver); -+ platform_driver_unregister(&bcm2835_alsa5_driver); -+ platform_driver_unregister(&bcm2835_alsa6_driver); -+ platform_driver_unregister(&bcm2835_alsa7_driver); -+} -+ -+late_initcall(bcm2835_alsa_device_init); -+module_exit(bcm2835_alsa_device_exit); -+ -+MODULE_AUTHOR("Dom Cobley"); -+MODULE_DESCRIPTION("Alsa driver for BCM2835 chip"); -+MODULE_LICENSE("GPL"); -+MODULE_ALIAS("platform:bcm2835_alsa"); -diff -Nur linux-4.1.13.orig/sound/arm/bcm2835-ctl.c linux-rpi/sound/arm/bcm2835-ctl.c ---- linux-4.1.13.orig/sound/arm/bcm2835-ctl.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/sound/arm/bcm2835-ctl.c 2015-11-29 09:42:41.446997173 +0100 -@@ -0,0 +1,323 @@ -+/***************************************************************************** -+* Copyright 2011 Broadcom Corporation. All rights reserved. -+* -+* Unless you and Broadcom execute a separate written software license -+* agreement governing use of this software, this software is licensed to you -+* under the terms of the GNU General Public License version 2, available at -+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -+* -+* Notwithstanding the above, under no circumstances may you combine this -+* software in any way with any other Broadcom software provided under a -+* license other than the GPL, without Broadcom's express prior written -+* consent. -+*****************************************************************************/ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "bcm2835.h" -+ -+/* volume maximum and minimum in terms of 0.01dB */ -+#define CTRL_VOL_MAX 400 -+#define CTRL_VOL_MIN -10239 /* originally -10240 */ -+ -+ -+static int snd_bcm2835_ctl_info(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_info *uinfo) -+{ -+ audio_info(" ... IN\n"); -+ if (kcontrol->private_value == PCM_PLAYBACK_VOLUME) { -+ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; -+ uinfo->count = 1; -+ uinfo->value.integer.min = CTRL_VOL_MIN; -+ uinfo->value.integer.max = CTRL_VOL_MAX; /* 2303 */ -+ } else if (kcontrol->private_value == PCM_PLAYBACK_MUTE) { -+ uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; -+ uinfo->count = 1; -+ uinfo->value.integer.min = 0; -+ uinfo->value.integer.max = 1; -+ } else if (kcontrol->private_value == PCM_PLAYBACK_DEVICE) { -+ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; -+ uinfo->count = 1; -+ uinfo->value.integer.min = 0; -+ uinfo->value.integer.max = AUDIO_DEST_MAX-1; -+ } -+ audio_info(" ... OUT\n"); -+ return 0; -+} -+ -+/* toggles mute on or off depending on the value of nmute, and returns -+ * 1 if the mute value was changed, otherwise 0 -+ */ -+static int toggle_mute(struct bcm2835_chip *chip, int nmute) -+{ -+ /* if settings are ok, just return 0 */ -+ if(chip->mute == nmute) -+ return 0; -+ -+ /* if the sound is muted then we need to unmute */ -+ if(chip->mute == CTRL_VOL_MUTE) -+ { -+ chip->volume = chip->old_volume; /* copy the old volume back */ -+ audio_info("Unmuting, old_volume = %d, volume = %d ...\n", chip->old_volume, chip->volume); -+ } -+ else /* otherwise we mute */ -+ { -+ chip->old_volume = chip->volume; -+ chip->volume = 26214; /* set volume to minimum level AKA mute */ -+ audio_info("Muting, old_volume = %d, volume = %d ...\n", chip->old_volume, chip->volume); -+ } -+ -+ chip->mute = nmute; -+ return 1; -+} -+ -+static int snd_bcm2835_ctl_get(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol); -+ -+ BUG_ON(!chip && !(chip->avail_substreams & AVAIL_SUBSTREAMS_MASK)); -+ -+ if (kcontrol->private_value == PCM_PLAYBACK_VOLUME) -+ ucontrol->value.integer.value[0] = chip2alsa(chip->volume); -+ else if (kcontrol->private_value == PCM_PLAYBACK_MUTE) -+ ucontrol->value.integer.value[0] = chip->mute; -+ else if (kcontrol->private_value == PCM_PLAYBACK_DEVICE) -+ ucontrol->value.integer.value[0] = chip->dest; -+ -+ return 0; -+} -+ -+static int snd_bcm2835_ctl_put(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol); -+ int changed = 0; -+ -+ if (kcontrol->private_value == PCM_PLAYBACK_VOLUME) { -+ audio_info("Volume change attempted.. volume = %d new_volume = %d\n", chip->volume, (int)ucontrol->value.integer.value[0]); -+ if (chip->mute == CTRL_VOL_MUTE) { -+ /* changed = toggle_mute(chip, CTRL_VOL_UNMUTE); */ -+ return 1; /* should return 0 to signify no change but the mixer takes this as the opposite sign (no idea why) */ -+ } -+ if (changed -+ || (ucontrol->value.integer.value[0] != chip2alsa(chip->volume))) { -+ -+ chip->volume = alsa2chip(ucontrol->value.integer.value[0]); -+ changed = 1; -+ } -+ -+ } else if (kcontrol->private_value == PCM_PLAYBACK_MUTE) { -+ /* Now implemented */ -+ audio_info(" Mute attempted\n"); -+ changed = toggle_mute(chip, ucontrol->value.integer.value[0]); -+ -+ } else if (kcontrol->private_value == PCM_PLAYBACK_DEVICE) { -+ if (ucontrol->value.integer.value[0] != chip->dest) { -+ chip->dest = ucontrol->value.integer.value[0]; -+ changed = 1; -+ } -+ } -+ -+ if (changed) { -+ if (bcm2835_audio_set_ctls(chip)) -+ printk(KERN_ERR "Failed to set ALSA controls..\n"); -+ } -+ -+ return changed; -+} -+ -+static DECLARE_TLV_DB_SCALE(snd_bcm2835_db_scale, CTRL_VOL_MIN, 1, 1); -+ -+static struct snd_kcontrol_new snd_bcm2835_ctl[] = { -+ { -+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, -+ .name = "PCM Playback Volume", -+ .index = 0, -+ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, -+ .private_value = PCM_PLAYBACK_VOLUME, -+ .info = snd_bcm2835_ctl_info, -+ .get = snd_bcm2835_ctl_get, -+ .put = snd_bcm2835_ctl_put, -+ .count = 1, -+ .tlv = {.p = snd_bcm2835_db_scale} -+ }, -+ { -+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, -+ .name = "PCM Playback Switch", -+ .index = 0, -+ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, -+ .private_value = PCM_PLAYBACK_MUTE, -+ .info = snd_bcm2835_ctl_info, -+ .get = snd_bcm2835_ctl_get, -+ .put = snd_bcm2835_ctl_put, -+ .count = 1, -+ }, -+ { -+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, -+ .name = "PCM Playback Route", -+ .index = 0, -+ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, -+ .private_value = PCM_PLAYBACK_DEVICE, -+ .info = snd_bcm2835_ctl_info, -+ .get = snd_bcm2835_ctl_get, -+ .put = snd_bcm2835_ctl_put, -+ .count = 1, -+ }, -+}; -+ -+static int snd_bcm2835_spdif_default_info(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_info *uinfo) -+{ -+ uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; -+ uinfo->count = 1; -+ return 0; -+} -+ -+static int snd_bcm2835_spdif_default_get(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol); -+ int i; -+ -+ for (i = 0; i < 4; i++) -+ ucontrol->value.iec958.status[i] = -+ (chip->spdif_status >> (i * 8)) && 0xff; -+ -+ return 0; -+} -+ -+static int snd_bcm2835_spdif_default_put(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol); -+ unsigned int val = 0; -+ int i, change; -+ -+ for (i = 0; i < 4; i++) -+ val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8); -+ -+ change = val != chip->spdif_status; -+ chip->spdif_status = val; -+ -+ return change; -+} -+ -+static int snd_bcm2835_spdif_mask_info(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_info *uinfo) -+{ -+ uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; -+ uinfo->count = 1; -+ return 0; -+} -+ -+static int snd_bcm2835_spdif_mask_get(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ /* bcm2835 supports only consumer mode and sets all other format flags -+ * automatically. So the only thing left is signalling non-audio -+ * content */ -+ ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO; -+ return 0; -+} -+ -+static int snd_bcm2835_spdif_stream_info(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_info *uinfo) -+{ -+ uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; -+ uinfo->count = 1; -+ return 0; -+} -+ -+static int snd_bcm2835_spdif_stream_get(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol); -+ int i; -+ -+ for (i = 0; i < 4; i++) -+ ucontrol->value.iec958.status[i] = -+ (chip->spdif_status >> (i * 8)) & 0xff; -+ return 0; -+} -+ -+static int snd_bcm2835_spdif_stream_put(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol); -+ unsigned int val = 0; -+ int i, change; -+ -+ for (i = 0; i < 4; i++) -+ val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8); -+ change = val != chip->spdif_status; -+ chip->spdif_status = val; -+ -+ return change; -+} -+ -+static struct snd_kcontrol_new snd_bcm2835_spdif[] = { -+ { -+ .iface = SNDRV_CTL_ELEM_IFACE_PCM, -+ .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), -+ .info = snd_bcm2835_spdif_default_info, -+ .get = snd_bcm2835_spdif_default_get, -+ .put = snd_bcm2835_spdif_default_put -+ }, -+ { -+ .access = SNDRV_CTL_ELEM_ACCESS_READ, -+ .iface = SNDRV_CTL_ELEM_IFACE_PCM, -+ .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK), -+ .info = snd_bcm2835_spdif_mask_info, -+ .get = snd_bcm2835_spdif_mask_get, -+ }, -+ { -+ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | -+ SNDRV_CTL_ELEM_ACCESS_INACTIVE, -+ .iface = SNDRV_CTL_ELEM_IFACE_PCM, -+ .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM), -+ .info = snd_bcm2835_spdif_stream_info, -+ .get = snd_bcm2835_spdif_stream_get, -+ .put = snd_bcm2835_spdif_stream_put, -+ }, -+}; -+ -+int snd_bcm2835_new_ctl(bcm2835_chip_t * chip) -+{ -+ int err; -+ unsigned int idx; -+ -+ strcpy(chip->card->mixername, "Broadcom Mixer"); -+ for (idx = 0; idx < ARRAY_SIZE(snd_bcm2835_ctl); idx++) { -+ err = -+ snd_ctl_add(chip->card, -+ snd_ctl_new1(&snd_bcm2835_ctl[idx], chip)); -+ if (err < 0) -+ return err; -+ } -+ for (idx = 0; idx < ARRAY_SIZE(snd_bcm2835_spdif); idx++) { -+ err = snd_ctl_add(chip->card, -+ snd_ctl_new1(&snd_bcm2835_spdif[idx], chip)); -+ if (err < 0) -+ return err; -+ } -+ return 0; -+} -diff -Nur linux-4.1.13.orig/sound/arm/bcm2835.h linux-rpi/sound/arm/bcm2835.h ---- linux-4.1.13.orig/sound/arm/bcm2835.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/sound/arm/bcm2835.h 2015-11-29 09:42:41.446997173 +0100 -@@ -0,0 +1,167 @@ -+/***************************************************************************** -+* Copyright 2011 Broadcom Corporation. All rights reserved. -+* -+* Unless you and Broadcom execute a separate written software license -+* agreement governing use of this software, this software is licensed to you -+* under the terms of the GNU General Public License version 2, available at -+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -+* -+* Notwithstanding the above, under no circumstances may you combine this -+* software in any way with any other Broadcom software provided under a -+* license other than the GPL, without Broadcom's express prior written -+* consent. -+*****************************************************************************/ -+ -+#ifndef __SOUND_ARM_BCM2835_H -+#define __SOUND_ARM_BCM2835_H -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* -+#define AUDIO_DEBUG_ENABLE -+#define AUDIO_VERBOSE_DEBUG_ENABLE -+*/ -+ -+/* Debug macros */ -+ -+#ifdef AUDIO_DEBUG_ENABLE -+#ifdef AUDIO_VERBOSE_DEBUG_ENABLE -+ -+#define audio_debug(fmt, arg...) \ -+ printk(KERN_INFO"%s:%d " fmt, __func__, __LINE__, ##arg) -+ -+#define audio_info(fmt, arg...) \ -+ printk(KERN_INFO"%s:%d " fmt, __func__, __LINE__, ##arg) -+ -+#else -+ -+#define audio_debug(fmt, arg...) -+ -+#define audio_info(fmt, arg...) -+ -+#endif /* AUDIO_VERBOSE_DEBUG_ENABLE */ -+ -+#else -+ -+#define audio_debug(fmt, arg...) -+ -+#define audio_info(fmt, arg...) -+ -+#endif /* AUDIO_DEBUG_ENABLE */ -+ -+#define audio_error(fmt, arg...) \ -+ printk(KERN_ERR"%s:%d " fmt, __func__, __LINE__, ##arg) -+ -+#define audio_warning(fmt, arg...) \ -+ printk(KERN_WARNING"%s:%d " fmt, __func__, __LINE__, ##arg) -+ -+#define audio_alert(fmt, arg...) \ -+ printk(KERN_ALERT"%s:%d " fmt, __func__, __LINE__, ##arg) -+ -+#define MAX_SUBSTREAMS (8) -+#define AVAIL_SUBSTREAMS_MASK (0xff) -+enum { -+ CTRL_VOL_MUTE, -+ CTRL_VOL_UNMUTE -+}; -+ -+/* macros for alsa2chip and chip2alsa, instead of functions */ -+ -+#define alsa2chip(vol) (uint)(-((vol << 8) / 100)) /* convert alsa to chip volume (defined as macro rather than function call) */ -+#define chip2alsa(vol) -((vol * 100) >> 8) /* convert chip to alsa volume */ -+ -+/* Some constants for values .. */ -+typedef enum { -+ AUDIO_DEST_AUTO = 0, -+ AUDIO_DEST_HEADPHONES = 1, -+ AUDIO_DEST_HDMI = 2, -+ AUDIO_DEST_MAX, -+} SND_BCM2835_ROUTE_T; -+ -+typedef enum { -+ PCM_PLAYBACK_VOLUME, -+ PCM_PLAYBACK_MUTE, -+ PCM_PLAYBACK_DEVICE, -+} SND_BCM2835_CTRL_T; -+ -+/* definition of the chip-specific record */ -+typedef struct bcm2835_chip { -+ struct snd_card *card; -+ struct snd_pcm *pcm; -+ struct snd_pcm *pcm_spdif; -+ /* Bitmat for valid reg_base and irq numbers */ -+ uint32_t avail_substreams; -+ struct platform_device *pdev[MAX_SUBSTREAMS]; -+ struct bcm2835_alsa_stream *alsa_stream[MAX_SUBSTREAMS]; -+ -+ int volume; -+ int old_volume; /* stores the volume value whist muted */ -+ int dest; -+ int mute; -+ -+ unsigned int opened; -+ unsigned int spdif_status; -+ struct mutex audio_mutex; -+} bcm2835_chip_t; -+ -+typedef struct bcm2835_alsa_stream { -+ bcm2835_chip_t *chip; -+ struct snd_pcm_substream *substream; -+ struct snd_pcm_indirect pcm_indirect; -+ -+ struct semaphore buffers_update_sem; -+ struct semaphore control_sem; -+ spinlock_t lock; -+ volatile uint32_t control; -+ volatile uint32_t status; -+ -+ int open; -+ int running; -+ int draining; -+ -+ int channels; -+ int params_rate; -+ int pcm_format_width; -+ -+ unsigned int pos; -+ unsigned int buffer_size; -+ unsigned int period_size; -+ -+ uint32_t enable_fifo_irq; -+ irq_handler_t fifo_irq_handler; -+ -+ atomic_t retrieved; -+ struct opaque_AUDIO_INSTANCE_T *instance; -+ struct workqueue_struct *my_wq; -+ int idx; -+} bcm2835_alsa_stream_t; -+ -+int snd_bcm2835_new_ctl(bcm2835_chip_t * chip); -+int snd_bcm2835_new_pcm(bcm2835_chip_t * chip); -+int snd_bcm2835_new_spdif_pcm(bcm2835_chip_t * chip); -+ -+int bcm2835_audio_open(bcm2835_alsa_stream_t * alsa_stream); -+int bcm2835_audio_close(bcm2835_alsa_stream_t * alsa_stream); -+int bcm2835_audio_set_params(bcm2835_alsa_stream_t * alsa_stream, -+ uint32_t channels, uint32_t samplerate, -+ uint32_t bps); -+int bcm2835_audio_setup(bcm2835_alsa_stream_t * alsa_stream); -+int bcm2835_audio_start(bcm2835_alsa_stream_t * alsa_stream); -+int bcm2835_audio_stop(bcm2835_alsa_stream_t * alsa_stream); -+int bcm2835_audio_set_ctls(bcm2835_chip_t * chip); -+int bcm2835_audio_write(bcm2835_alsa_stream_t * alsa_stream, uint32_t count, -+ void *src); -+uint32_t bcm2835_audio_retrieve_buffers(bcm2835_alsa_stream_t * alsa_stream); -+void bcm2835_audio_flush_buffers(bcm2835_alsa_stream_t * alsa_stream); -+void bcm2835_audio_flush_playback_buffers(bcm2835_alsa_stream_t * alsa_stream); -+ -+#endif /* __SOUND_ARM_BCM2835_H */ -diff -Nur linux-4.1.13.orig/sound/arm/bcm2835-pcm.c linux-rpi/sound/arm/bcm2835-pcm.c ---- linux-4.1.13.orig/sound/arm/bcm2835-pcm.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/sound/arm/bcm2835-pcm.c 2015-11-29 09:42:41.446997173 +0100 -@@ -0,0 +1,557 @@ -+/***************************************************************************** -+* Copyright 2011 Broadcom Corporation. All rights reserved. -+* -+* Unless you and Broadcom execute a separate written software license -+* agreement governing use of this software, this software is licensed to you -+* under the terms of the GNU General Public License version 2, available at -+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -+* -+* Notwithstanding the above, under no circumstances may you combine this -+* software in any way with any other Broadcom software provided under a -+* license other than the GPL, without Broadcom's express prior written -+* consent. -+*****************************************************************************/ -+ -+#include -+#include -+ -+#include -+ -+#include "bcm2835.h" -+ -+/* hardware definition */ -+static struct snd_pcm_hardware snd_bcm2835_playback_hw = { -+ .info = (SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | -+ SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID), -+ .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, -+ .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, -+ .rate_min = 8000, -+ .rate_max = 48000, -+ .channels_min = 1, -+ .channels_max = 2, -+ .buffer_bytes_max = 128 * 1024, -+ .period_bytes_min = 1 * 1024, -+ .period_bytes_max = 128 * 1024, -+ .periods_min = 1, -+ .periods_max = 128, -+}; -+ -+static struct snd_pcm_hardware snd_bcm2835_playback_spdif_hw = { -+ .info = (SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | -+ SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID), -+ .formats = SNDRV_PCM_FMTBIT_S16_LE, -+ .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_44100 | -+ SNDRV_PCM_RATE_48000, -+ .rate_min = 44100, -+ .rate_max = 48000, -+ .channels_min = 2, -+ .channels_max = 2, -+ .buffer_bytes_max = 128 * 1024, -+ .period_bytes_min = 1 * 1024, -+ .period_bytes_max = 128 * 1024, -+ .periods_min = 1, -+ .periods_max = 128, -+}; -+ -+static void snd_bcm2835_playback_free(struct snd_pcm_runtime *runtime) -+{ -+ audio_info("Freeing up alsa stream here ..\n"); -+ if (runtime->private_data) -+ kfree(runtime->private_data); -+ runtime->private_data = NULL; -+} -+ -+static irqreturn_t bcm2835_playback_fifo_irq(int irq, void *dev_id) -+{ -+ bcm2835_alsa_stream_t *alsa_stream = (bcm2835_alsa_stream_t *) dev_id; -+ uint32_t consumed = 0; -+ int new_period = 0; -+ -+ audio_info(" .. IN\n"); -+ -+ audio_info("alsa_stream=%p substream=%p\n", alsa_stream, -+ alsa_stream ? alsa_stream->substream : 0); -+ -+ if (alsa_stream->open) -+ consumed = bcm2835_audio_retrieve_buffers(alsa_stream); -+ -+ /* We get called only if playback was triggered, So, the number of buffers we retrieve in -+ * each iteration are the buffers that have been played out already -+ */ -+ -+ if (alsa_stream->period_size) { -+ if ((alsa_stream->pos / alsa_stream->period_size) != -+ ((alsa_stream->pos + consumed) / alsa_stream->period_size)) -+ new_period = 1; -+ } -+ audio_debug("updating pos cur: %d + %d max:%d period_bytes:%d, hw_ptr: %d new_period:%d\n", -+ alsa_stream->pos, -+ consumed, -+ alsa_stream->buffer_size, -+ (int)(alsa_stream->period_size*alsa_stream->substream->runtime->periods), -+ frames_to_bytes(alsa_stream->substream->runtime, alsa_stream->substream->runtime->status->hw_ptr), -+ new_period); -+ if (alsa_stream->buffer_size) { -+ alsa_stream->pos += consumed &~ (1<<30); -+ alsa_stream->pos %= alsa_stream->buffer_size; -+ } -+ -+ if (alsa_stream->substream) { -+ if (new_period) -+ snd_pcm_period_elapsed(alsa_stream->substream); -+ } else { -+ audio_warning(" unexpected NULL substream\n"); -+ } -+ audio_info(" .. OUT\n"); -+ -+ return IRQ_HANDLED; -+} -+ -+/* open callback */ -+static int snd_bcm2835_playback_open_generic( -+ struct snd_pcm_substream *substream, int spdif) -+{ -+ bcm2835_chip_t *chip = snd_pcm_substream_chip(substream); -+ struct snd_pcm_runtime *runtime = substream->runtime; -+ bcm2835_alsa_stream_t *alsa_stream; -+ int idx; -+ int err; -+ -+ audio_info(" .. IN (%d)\n", substream->number); -+ -+ if(mutex_lock_interruptible(&chip->audio_mutex)) -+ { -+ audio_error("Interrupted whilst waiting for lock\n"); -+ return -EINTR; -+ } -+ audio_info("Alsa open (%d)\n", substream->number); -+ idx = substream->number; -+ -+ if (spdif && chip->opened != 0) { -+ err = -EBUSY; -+ goto out; -+ } -+ else if (!spdif && (chip->opened & (1 << idx))) { -+ err = -EBUSY; -+ goto out; -+ } -+ if (idx > MAX_SUBSTREAMS) { -+ audio_error -+ ("substream(%d) device doesn't exist max(%d) substreams allowed\n", -+ idx, MAX_SUBSTREAMS); -+ err = -ENODEV; -+ goto out; -+ } -+ -+ /* Check if we are ready */ -+ if (!(chip->avail_substreams & (1 << idx))) { -+ /* We are not ready yet */ -+ audio_error("substream(%d) device is not ready yet\n", idx); -+ err = -EAGAIN; -+ goto out; -+ } -+ -+ alsa_stream = kzalloc(sizeof(bcm2835_alsa_stream_t), GFP_KERNEL); -+ if (alsa_stream == NULL) { -+ err = -ENOMEM; -+ goto out; -+ } -+ -+ /* Initialise alsa_stream */ -+ alsa_stream->chip = chip; -+ alsa_stream->substream = substream; -+ alsa_stream->idx = idx; -+ -+ sema_init(&alsa_stream->buffers_update_sem, 0); -+ sema_init(&alsa_stream->control_sem, 0); -+ spin_lock_init(&alsa_stream->lock); -+ -+ /* Enabled in start trigger, called on each "fifo irq" after that */ -+ alsa_stream->enable_fifo_irq = 0; -+ alsa_stream->fifo_irq_handler = bcm2835_playback_fifo_irq; -+ -+ err = bcm2835_audio_open(alsa_stream); -+ if (err != 0) { -+ kfree(alsa_stream); -+ goto out; -+ } -+ runtime->private_data = alsa_stream; -+ runtime->private_free = snd_bcm2835_playback_free; -+ if (spdif) { -+ runtime->hw = snd_bcm2835_playback_spdif_hw; -+ } else { -+ /* clear spdif status, as we are not in spdif mode */ -+ chip->spdif_status = 0; -+ runtime->hw = snd_bcm2835_playback_hw; -+ } -+ /* minimum 16 bytes alignment (for vchiq bulk transfers) */ -+ snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, -+ 16); -+ -+ chip->alsa_stream[idx] = alsa_stream; -+ -+ chip->opened |= (1 << idx); -+ alsa_stream->open = 1; -+ alsa_stream->draining = 1; -+ -+out: -+ mutex_unlock(&chip->audio_mutex); -+ -+ audio_info(" .. OUT =%d\n", err); -+ -+ return err; -+} -+ -+static int snd_bcm2835_playback_open(struct snd_pcm_substream *substream) -+{ -+ return snd_bcm2835_playback_open_generic(substream, 0); -+} -+ -+static int snd_bcm2835_playback_spdif_open(struct snd_pcm_substream *substream) -+{ -+ return snd_bcm2835_playback_open_generic(substream, 1); -+} -+ -+/* close callback */ -+static int snd_bcm2835_playback_close(struct snd_pcm_substream *substream) -+{ -+ /* the hardware-specific codes will be here */ -+ -+ bcm2835_chip_t *chip; -+ struct snd_pcm_runtime *runtime; -+ bcm2835_alsa_stream_t *alsa_stream; -+ -+ audio_info(" .. IN\n"); -+ -+ chip = snd_pcm_substream_chip(substream); -+ if(mutex_lock_interruptible(&chip->audio_mutex)) -+ { -+ audio_error("Interrupted whilst waiting for lock\n"); -+ return -EINTR; -+ } -+ runtime = substream->runtime; -+ alsa_stream = runtime->private_data; -+ -+ audio_info("Alsa close\n"); -+ -+ /* -+ * Call stop if it's still running. This happens when app -+ * is force killed and we don't get a stop trigger. -+ */ -+ if (alsa_stream->running) { -+ int err; -+ err = bcm2835_audio_stop(alsa_stream); -+ alsa_stream->running = 0; -+ if (err != 0) -+ audio_error(" Failed to STOP alsa device\n"); -+ } -+ -+ alsa_stream->period_size = 0; -+ alsa_stream->buffer_size = 0; -+ -+ if (alsa_stream->open) { -+ alsa_stream->open = 0; -+ bcm2835_audio_close(alsa_stream); -+ } -+ if (alsa_stream->chip) -+ alsa_stream->chip->alsa_stream[alsa_stream->idx] = NULL; -+ /* -+ * Do not free up alsa_stream here, it will be freed up by -+ * runtime->private_free callback we registered in *_open above -+ */ -+ -+ chip->opened &= ~(1 << substream->number); -+ -+ mutex_unlock(&chip->audio_mutex); -+ audio_info(" .. OUT\n"); -+ -+ return 0; -+} -+ -+/* hw_params callback */ -+static int snd_bcm2835_pcm_hw_params(struct snd_pcm_substream *substream, -+ struct snd_pcm_hw_params *params) -+{ -+ struct snd_pcm_runtime *runtime = substream->runtime; -+ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data; -+ int err; -+ -+ audio_info(" .. IN\n"); -+ -+ err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params)); -+ if (err < 0) { -+ audio_error -+ (" pcm_lib_malloc failed to allocated pages for buffers\n"); -+ return err; -+ } -+ -+ alsa_stream->channels = params_channels(params); -+ alsa_stream->params_rate = params_rate(params); -+ alsa_stream->pcm_format_width = snd_pcm_format_width(params_format (params)); -+ audio_info(" .. OUT\n"); -+ -+ return err; -+} -+ -+/* hw_free callback */ -+static int snd_bcm2835_pcm_hw_free(struct snd_pcm_substream *substream) -+{ -+ audio_info(" .. IN\n"); -+ return snd_pcm_lib_free_pages(substream); -+} -+ -+/* prepare callback */ -+static int snd_bcm2835_pcm_prepare(struct snd_pcm_substream *substream) -+{ -+ bcm2835_chip_t *chip = snd_pcm_substream_chip(substream); -+ struct snd_pcm_runtime *runtime = substream->runtime; -+ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data; -+ int channels; -+ int err; -+ -+ audio_info(" .. IN\n"); -+ -+ /* notify the vchiq that it should enter spdif passthrough mode by -+ * setting channels=0 (see -+ * https://github.com/raspberrypi/linux/issues/528) */ -+ if (chip->spdif_status & IEC958_AES0_NONAUDIO) -+ channels = 0; -+ else -+ channels = alsa_stream->channels; -+ -+ err = bcm2835_audio_set_params(alsa_stream, channels, -+ alsa_stream->params_rate, -+ alsa_stream->pcm_format_width); -+ if (err < 0) { -+ audio_error(" error setting hw params\n"); -+ } -+ -+ bcm2835_audio_setup(alsa_stream); -+ -+ /* in preparation of the stream, set the controls (volume level) of the stream */ -+ bcm2835_audio_set_ctls(alsa_stream->chip); -+ -+ -+ memset(&alsa_stream->pcm_indirect, 0, sizeof(alsa_stream->pcm_indirect)); -+ -+ alsa_stream->pcm_indirect.hw_buffer_size = -+ alsa_stream->pcm_indirect.sw_buffer_size = -+ snd_pcm_lib_buffer_bytes(substream); -+ -+ alsa_stream->buffer_size = snd_pcm_lib_buffer_bytes(substream); -+ alsa_stream->period_size = snd_pcm_lib_period_bytes(substream); -+ alsa_stream->pos = 0; -+ -+ audio_debug("buffer_size=%d, period_size=%d pos=%d frame_bits=%d\n", -+ alsa_stream->buffer_size, alsa_stream->period_size, -+ alsa_stream->pos, runtime->frame_bits); -+ -+ audio_info(" .. OUT\n"); -+ return 0; -+} -+ -+static void snd_bcm2835_pcm_transfer(struct snd_pcm_substream *substream, -+ struct snd_pcm_indirect *rec, size_t bytes) -+{ -+ struct snd_pcm_runtime *runtime = substream->runtime; -+ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data; -+ void *src = (void *)(substream->runtime->dma_area + rec->sw_data); -+ int err; -+ -+ err = bcm2835_audio_write(alsa_stream, bytes, src); -+ if (err) -+ audio_error(" Failed to transfer to alsa device (%d)\n", err); -+ -+} -+ -+static int snd_bcm2835_pcm_ack(struct snd_pcm_substream *substream) -+{ -+ struct snd_pcm_runtime *runtime = substream->runtime; -+ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data; -+ struct snd_pcm_indirect *pcm_indirect = &alsa_stream->pcm_indirect; -+ -+ pcm_indirect->hw_queue_size = runtime->hw.buffer_bytes_max; -+ snd_pcm_indirect_playback_transfer(substream, pcm_indirect, -+ snd_bcm2835_pcm_transfer); -+ return 0; -+} -+ -+/* trigger callback */ -+static int snd_bcm2835_pcm_trigger(struct snd_pcm_substream *substream, int cmd) -+{ -+ struct snd_pcm_runtime *runtime = substream->runtime; -+ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data; -+ int err = 0; -+ -+ audio_info(" .. IN\n"); -+ -+ switch (cmd) { -+ case SNDRV_PCM_TRIGGER_START: -+ audio_debug("bcm2835_AUDIO_TRIGGER_START running=%d\n", -+ alsa_stream->running); -+ if (!alsa_stream->running) { -+ err = bcm2835_audio_start(alsa_stream); -+ if (err == 0) { -+ alsa_stream->pcm_indirect.hw_io = -+ alsa_stream->pcm_indirect.hw_data = -+ bytes_to_frames(runtime, -+ alsa_stream->pos); -+ substream->ops->ack(substream); -+ alsa_stream->running = 1; -+ alsa_stream->draining = 1; -+ } else { -+ audio_error(" Failed to START alsa device (%d)\n", err); -+ } -+ } -+ break; -+ case SNDRV_PCM_TRIGGER_STOP: -+ audio_debug -+ ("bcm2835_AUDIO_TRIGGER_STOP running=%d draining=%d\n", -+ alsa_stream->running, runtime->status->state == SNDRV_PCM_STATE_DRAINING); -+ if (runtime->status->state == SNDRV_PCM_STATE_DRAINING) { -+ audio_info("DRAINING\n"); -+ alsa_stream->draining = 1; -+ } else { -+ audio_info("DROPPING\n"); -+ alsa_stream->draining = 0; -+ } -+ if (alsa_stream->running) { -+ err = bcm2835_audio_stop(alsa_stream); -+ if (err != 0) -+ audio_error(" Failed to STOP alsa device (%d)\n", err); -+ alsa_stream->running = 0; -+ } -+ break; -+ default: -+ err = -EINVAL; -+ } -+ -+ audio_info(" .. OUT\n"); -+ return err; -+} -+ -+/* pointer callback */ -+static snd_pcm_uframes_t -+snd_bcm2835_pcm_pointer(struct snd_pcm_substream *substream) -+{ -+ struct snd_pcm_runtime *runtime = substream->runtime; -+ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data; -+ -+ audio_info(" .. IN\n"); -+ -+ audio_debug("pcm_pointer... (%d) hwptr=%d appl=%d pos=%d\n", 0, -+ frames_to_bytes(runtime, runtime->status->hw_ptr), -+ frames_to_bytes(runtime, runtime->control->appl_ptr), -+ alsa_stream->pos); -+ -+ audio_info(" .. OUT\n"); -+ return snd_pcm_indirect_playback_pointer(substream, -+ &alsa_stream->pcm_indirect, -+ alsa_stream->pos); -+} -+ -+static int snd_bcm2835_pcm_lib_ioctl(struct snd_pcm_substream *substream, -+ unsigned int cmd, void *arg) -+{ -+ int ret = snd_pcm_lib_ioctl(substream, cmd, arg); -+ audio_info(" .. substream=%p, cmd=%d, arg=%p (%x) ret=%d\n", substream, -+ cmd, arg, arg ? *(unsigned *)arg : 0, ret); -+ return ret; -+} -+ -+/* operators */ -+static struct snd_pcm_ops snd_bcm2835_playback_ops = { -+ .open = snd_bcm2835_playback_open, -+ .close = snd_bcm2835_playback_close, -+ .ioctl = snd_bcm2835_pcm_lib_ioctl, -+ .hw_params = snd_bcm2835_pcm_hw_params, -+ .hw_free = snd_bcm2835_pcm_hw_free, -+ .prepare = snd_bcm2835_pcm_prepare, -+ .trigger = snd_bcm2835_pcm_trigger, -+ .pointer = snd_bcm2835_pcm_pointer, -+ .ack = snd_bcm2835_pcm_ack, -+}; -+ -+static struct snd_pcm_ops snd_bcm2835_playback_spdif_ops = { -+ .open = snd_bcm2835_playback_spdif_open, -+ .close = snd_bcm2835_playback_close, -+ .ioctl = snd_bcm2835_pcm_lib_ioctl, -+ .hw_params = snd_bcm2835_pcm_hw_params, -+ .hw_free = snd_bcm2835_pcm_hw_free, -+ .prepare = snd_bcm2835_pcm_prepare, -+ .trigger = snd_bcm2835_pcm_trigger, -+ .pointer = snd_bcm2835_pcm_pointer, -+ .ack = snd_bcm2835_pcm_ack, -+}; -+ -+/* create a pcm device */ -+int snd_bcm2835_new_pcm(bcm2835_chip_t * chip) -+{ -+ struct snd_pcm *pcm; -+ int err; -+ -+ audio_info(" .. IN\n"); -+ mutex_init(&chip->audio_mutex); -+ if(mutex_lock_interruptible(&chip->audio_mutex)) -+ { -+ audio_error("Interrupted whilst waiting for lock\n"); -+ return -EINTR; -+ } -+ err = -+ snd_pcm_new(chip->card, "bcm2835 ALSA", 0, MAX_SUBSTREAMS, 0, &pcm); -+ if (err < 0) -+ goto out; -+ pcm->private_data = chip; -+ strcpy(pcm->name, "bcm2835 ALSA"); -+ chip->pcm = pcm; -+ chip->dest = AUDIO_DEST_AUTO; -+ chip->volume = alsa2chip(0); -+ chip->mute = CTRL_VOL_UNMUTE; /*disable mute on startup */ -+ /* set operators */ -+ snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, -+ &snd_bcm2835_playback_ops); -+ -+ /* pre-allocation of buffers */ -+ /* NOTE: this may fail */ -+ snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS, -+ snd_dma_continuous_data -+ (GFP_KERNEL), 64 * 1024, -+ 64 * 1024); -+ -+out: -+ mutex_unlock(&chip->audio_mutex); -+ audio_info(" .. OUT\n"); -+ -+ return 0; -+} -+ -+int snd_bcm2835_new_spdif_pcm(bcm2835_chip_t * chip) -+{ -+ struct snd_pcm *pcm; -+ int err; -+ -+ audio_info(" .. IN\n"); -+ if(mutex_lock_interruptible(&chip->audio_mutex)) -+ { -+ audio_error("Interrupted whilst waiting for lock\n"); -+ return -EINTR; -+ } -+ err = snd_pcm_new(chip->card, "bcm2835 ALSA", 1, 1, 0, &pcm); -+ if (err < 0) -+ goto out; -+ -+ pcm->private_data = chip; -+ strcpy(pcm->name, "bcm2835 IEC958/HDMI"); -+ chip->pcm_spdif = pcm; -+ snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, -+ &snd_bcm2835_playback_spdif_ops); -+ -+ snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS, -+ snd_dma_continuous_data (GFP_KERNEL), -+ 64 * 1024, 64 * 1024); -+out: -+ mutex_unlock(&chip->audio_mutex); -+ audio_info(" .. OUT\n"); -+ -+ return 0; -+} -diff -Nur linux-4.1.13.orig/sound/arm/bcm2835-vchiq.c linux-rpi/sound/arm/bcm2835-vchiq.c ---- linux-4.1.13.orig/sound/arm/bcm2835-vchiq.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/sound/arm/bcm2835-vchiq.c 2015-11-29 09:42:41.446997173 +0100 -@@ -0,0 +1,902 @@ -+/***************************************************************************** -+* Copyright 2011 Broadcom Corporation. All rights reserved. -+* -+* Unless you and Broadcom execute a separate written software license -+* agreement governing use of this software, this software is licensed to you -+* under the terms of the GNU General Public License version 2, available at -+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -+* -+* Notwithstanding the above, under no circumstances may you combine this -+* software in any way with any other Broadcom software provided under a -+* license other than the GPL, without Broadcom's express prior written -+* consent. -+*****************************************************************************/ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "bcm2835.h" -+ -+/* ---- Include Files -------------------------------------------------------- */ -+ -+#include "interface/vchi/vchi.h" -+#include "vc_vchi_audioserv_defs.h" -+ -+/* ---- Private Constants and Types ------------------------------------------ */ -+ -+#define BCM2835_AUDIO_STOP 0 -+#define BCM2835_AUDIO_START 1 -+#define BCM2835_AUDIO_WRITE 2 -+ -+/* Logging macros (for remapping to other logging mechanisms, i.e., printf) */ -+#ifdef AUDIO_DEBUG_ENABLE -+ #define LOG_ERR( fmt, arg... ) pr_err( "%s:%d " fmt, __func__, __LINE__, ##arg) -+ #define LOG_WARN( fmt, arg... ) pr_info( "%s:%d " fmt, __func__, __LINE__, ##arg) -+ #define LOG_INFO( fmt, arg... ) pr_info( "%s:%d " fmt, __func__, __LINE__, ##arg) -+ #define LOG_DBG( fmt, arg... ) pr_info( "%s:%d " fmt, __func__, __LINE__, ##arg) -+#else -+ #define LOG_ERR( fmt, arg... ) pr_err( "%s:%d " fmt, __func__, __LINE__, ##arg) -+ #define LOG_WARN( fmt, arg... ) -+ #define LOG_INFO( fmt, arg... ) -+ #define LOG_DBG( fmt, arg... ) -+#endif -+ -+typedef struct opaque_AUDIO_INSTANCE_T { -+ uint32_t num_connections; -+ VCHI_SERVICE_HANDLE_T vchi_handle[VCHI_MAX_NUM_CONNECTIONS]; -+ struct completion msg_avail_comp; -+ struct mutex vchi_mutex; -+ bcm2835_alsa_stream_t *alsa_stream; -+ int32_t result; -+ short peer_version; -+} AUDIO_INSTANCE_T; -+ -+bool force_bulk = false; -+ -+/* ---- Private Variables ---------------------------------------------------- */ -+ -+/* ---- Private Function Prototypes ------------------------------------------ */ -+ -+/* ---- Private Functions ---------------------------------------------------- */ -+ -+static int bcm2835_audio_stop_worker(bcm2835_alsa_stream_t * alsa_stream); -+static int bcm2835_audio_start_worker(bcm2835_alsa_stream_t * alsa_stream); -+static int bcm2835_audio_write_worker(bcm2835_alsa_stream_t *alsa_stream, -+ uint32_t count, void *src); -+ -+typedef struct { -+ struct work_struct my_work; -+ bcm2835_alsa_stream_t *alsa_stream; -+ int cmd; -+ void *src; -+ uint32_t count; -+} my_work_t; -+ -+static void my_wq_function(struct work_struct *work) -+{ -+ my_work_t *w = (my_work_t *) work; -+ int ret = -9; -+ LOG_DBG(" .. IN %p:%d\n", w->alsa_stream, w->cmd); -+ switch (w->cmd) { -+ case BCM2835_AUDIO_START: -+ ret = bcm2835_audio_start_worker(w->alsa_stream); -+ break; -+ case BCM2835_AUDIO_STOP: -+ ret = bcm2835_audio_stop_worker(w->alsa_stream); -+ break; -+ case BCM2835_AUDIO_WRITE: -+ ret = bcm2835_audio_write_worker(w->alsa_stream, w->count, -+ w->src); -+ break; -+ default: -+ LOG_ERR(" Unexpected work: %p:%d\n", w->alsa_stream, w->cmd); -+ break; -+ } -+ kfree((void *)work); -+ LOG_DBG(" .. OUT %d\n", ret); -+} -+ -+int bcm2835_audio_start(bcm2835_alsa_stream_t * alsa_stream) -+{ -+ int ret = -1; -+ LOG_DBG(" .. IN\n"); -+ if (alsa_stream->my_wq) { -+ my_work_t *work = kmalloc(sizeof(my_work_t), GFP_ATOMIC); -+ /*--- Queue some work (item 1) ---*/ -+ if (work) { -+ INIT_WORK((struct work_struct *)work, my_wq_function); -+ work->alsa_stream = alsa_stream; -+ work->cmd = BCM2835_AUDIO_START; -+ if (queue_work -+ (alsa_stream->my_wq, (struct work_struct *)work)) -+ ret = 0; -+ } else -+ LOG_ERR(" .. Error: NULL work kmalloc\n"); -+ } -+ LOG_DBG(" .. OUT %d\n", ret); -+ return ret; -+} -+ -+int bcm2835_audio_stop(bcm2835_alsa_stream_t * alsa_stream) -+{ -+ int ret = -1; -+ LOG_DBG(" .. IN\n"); -+ if (alsa_stream->my_wq) { -+ my_work_t *work = kmalloc(sizeof(my_work_t), GFP_ATOMIC); -+ /*--- Queue some work (item 1) ---*/ -+ if (work) { -+ INIT_WORK((struct work_struct *)work, my_wq_function); -+ work->alsa_stream = alsa_stream; -+ work->cmd = BCM2835_AUDIO_STOP; -+ if (queue_work -+ (alsa_stream->my_wq, (struct work_struct *)work)) -+ ret = 0; -+ } else -+ LOG_ERR(" .. Error: NULL work kmalloc\n"); -+ } -+ LOG_DBG(" .. OUT %d\n", ret); -+ return ret; -+} -+ -+int bcm2835_audio_write(bcm2835_alsa_stream_t *alsa_stream, -+ uint32_t count, void *src) -+{ -+ int ret = -1; -+ LOG_DBG(" .. IN\n"); -+ if (alsa_stream->my_wq) { -+ my_work_t *work = kmalloc(sizeof(my_work_t), GFP_ATOMIC); -+ /*--- Queue some work (item 1) ---*/ -+ if (work) { -+ INIT_WORK((struct work_struct *)work, my_wq_function); -+ work->alsa_stream = alsa_stream; -+ work->cmd = BCM2835_AUDIO_WRITE; -+ work->src = src; -+ work->count = count; -+ if (queue_work -+ (alsa_stream->my_wq, (struct work_struct *)work)) -+ ret = 0; -+ } else -+ LOG_ERR(" .. Error: NULL work kmalloc\n"); -+ } -+ LOG_DBG(" .. OUT %d\n", ret); -+ return ret; -+} -+ -+void my_workqueue_init(bcm2835_alsa_stream_t * alsa_stream) -+{ -+ alsa_stream->my_wq = alloc_workqueue("my_queue", WQ_HIGHPRI, 1); -+ return; -+} -+ -+void my_workqueue_quit(bcm2835_alsa_stream_t * alsa_stream) -+{ -+ if (alsa_stream->my_wq) { -+ flush_workqueue(alsa_stream->my_wq); -+ destroy_workqueue(alsa_stream->my_wq); -+ alsa_stream->my_wq = NULL; -+ } -+ return; -+} -+ -+static void audio_vchi_callback(void *param, -+ const VCHI_CALLBACK_REASON_T reason, -+ void *msg_handle) -+{ -+ AUDIO_INSTANCE_T *instance = (AUDIO_INSTANCE_T *) param; -+ int32_t status; -+ int32_t msg_len; -+ VC_AUDIO_MSG_T m; -+ LOG_DBG(" .. IN instance=%p, handle=%p, alsa=%p, reason=%d, handle=%p\n", -+ instance, instance ? instance->vchi_handle[0] : NULL, instance ? instance->alsa_stream : NULL, reason, msg_handle); -+ -+ if (reason != VCHI_CALLBACK_MSG_AVAILABLE) { -+ return; -+ } -+ if (!instance) { -+ LOG_ERR(" .. instance is null\n"); -+ BUG(); -+ return; -+ } -+ if (!instance->vchi_handle[0]) { -+ LOG_ERR(" .. instance->vchi_handle[0] is null\n"); -+ BUG(); -+ return; -+ } -+ status = vchi_msg_dequeue(instance->vchi_handle[0], -+ &m, sizeof m, &msg_len, VCHI_FLAGS_NONE); -+ if (m.type == VC_AUDIO_MSG_TYPE_RESULT) { -+ LOG_DBG -+ (" .. instance=%p, m.type=VC_AUDIO_MSG_TYPE_RESULT, success=%d\n", -+ instance, m.u.result.success); -+ instance->result = m.u.result.success; -+ complete(&instance->msg_avail_comp); -+ } else if (m.type == VC_AUDIO_MSG_TYPE_COMPLETE) { -+ bcm2835_alsa_stream_t *alsa_stream = instance->alsa_stream; -+ irq_handler_t callback = (irq_handler_t) m.u.complete.callback; -+ LOG_DBG -+ (" .. instance=%p, m.type=VC_AUDIO_MSG_TYPE_COMPLETE, complete=%d\n", -+ instance, m.u.complete.count); -+ if (alsa_stream && callback) { -+ atomic_add(m.u.complete.count, &alsa_stream->retrieved); -+ callback(0, alsa_stream); -+ } else { -+ LOG_ERR(" .. unexpected alsa_stream=%p, callback=%p\n", -+ alsa_stream, callback); -+ } -+ } else { -+ LOG_ERR(" .. unexpected m.type=%d\n", m.type); -+ } -+ LOG_DBG(" .. OUT\n"); -+} -+ -+static AUDIO_INSTANCE_T *vc_vchi_audio_init(VCHI_INSTANCE_T vchi_instance, -+ VCHI_CONNECTION_T ** -+ vchi_connections, -+ uint32_t num_connections) -+{ -+ uint32_t i; -+ AUDIO_INSTANCE_T *instance; -+ int status; -+ -+ LOG_DBG("%s: start", __func__); -+ -+ if (num_connections > VCHI_MAX_NUM_CONNECTIONS) { -+ LOG_ERR("%s: unsupported number of connections %u (max=%u)\n", -+ __func__, num_connections, VCHI_MAX_NUM_CONNECTIONS); -+ -+ return NULL; -+ } -+ /* Allocate memory for this instance */ -+ instance = kmalloc(sizeof(*instance), GFP_KERNEL); -+ if (!instance) -+ return NULL; -+ -+ memset(instance, 0, sizeof(*instance)); -+ instance->num_connections = num_connections; -+ -+ /* Create a lock for exclusive, serialized VCHI connection access */ -+ mutex_init(&instance->vchi_mutex); -+ /* Open the VCHI service connections */ -+ for (i = 0; i < num_connections; i++) { -+ SERVICE_CREATION_T params = { -+ VCHI_VERSION_EX(VC_AUDIOSERV_VER, VC_AUDIOSERV_MIN_VER), -+ VC_AUDIO_SERVER_NAME, // 4cc service code -+ vchi_connections[i], // passed in fn pointers -+ 0, // rx fifo size (unused) -+ 0, // tx fifo size (unused) -+ audio_vchi_callback, // service callback -+ instance, // service callback parameter -+ 1, //TODO: remove VCOS_FALSE, // unaligned bulk recieves -+ 1, //TODO: remove VCOS_FALSE, // unaligned bulk transmits -+ 0 // want crc check on bulk transfers -+ }; -+ -+ LOG_DBG("%s: about to open %i\n", __func__, i); -+ status = vchi_service_open(vchi_instance, ¶ms, -+ &instance->vchi_handle[i]); -+ LOG_DBG("%s: opened %i: %p=%d\n", __func__, i, instance->vchi_handle[i], status); -+ if (status) { -+ LOG_ERR -+ ("%s: failed to open VCHI service connection (status=%d)\n", -+ __func__, status); -+ -+ goto err_close_services; -+ } -+ /* Finished with the service for now */ -+ vchi_service_release(instance->vchi_handle[i]); -+ } -+ -+ LOG_DBG("%s: okay\n", __func__); -+ return instance; -+ -+err_close_services: -+ for (i = 0; i < instance->num_connections; i++) { -+ LOG_ERR("%s: closing %i: %p\n", __func__, i, instance->vchi_handle[i]); -+ if (instance->vchi_handle[i]) -+ vchi_service_close(instance->vchi_handle[i]); -+ } -+ -+ kfree(instance); -+ LOG_ERR("%s: error\n", __func__); -+ -+ return NULL; -+} -+ -+static int32_t vc_vchi_audio_deinit(AUDIO_INSTANCE_T * instance) -+{ -+ uint32_t i; -+ -+ LOG_DBG(" .. IN\n"); -+ -+ if (instance == NULL) { -+ LOG_ERR("%s: invalid handle %p\n", __func__, instance); -+ -+ return -1; -+ } -+ -+ LOG_DBG(" .. about to lock (%d)\n", instance->num_connections); -+ if(mutex_lock_interruptible(&instance->vchi_mutex)) -+ { -+ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections); -+ return -EINTR; -+ } -+ -+ /* Close all VCHI service connections */ -+ for (i = 0; i < instance->num_connections; i++) { -+ int32_t success; -+ LOG_DBG(" .. %i:closing %p\n", i, instance->vchi_handle[i]); -+ vchi_service_use(instance->vchi_handle[i]); -+ -+ success = vchi_service_close(instance->vchi_handle[i]); -+ if (success != 0) { -+ LOG_DBG -+ ("%s: failed to close VCHI service connection (status=%d)\n", -+ __func__, success); -+ } -+ } -+ -+ mutex_unlock(&instance->vchi_mutex); -+ -+ kfree(instance); -+ -+ LOG_DBG(" .. OUT\n"); -+ -+ return 0; -+} -+ -+static int bcm2835_audio_open_connection(bcm2835_alsa_stream_t * alsa_stream) -+{ -+ static VCHI_INSTANCE_T vchi_instance; -+ static VCHI_CONNECTION_T *vchi_connection; -+ static int initted; -+ AUDIO_INSTANCE_T *instance = alsa_stream->instance; -+ int ret; -+ LOG_DBG(" .. IN\n"); -+ -+ LOG_INFO("%s: start\n", __func__); -+ BUG_ON(instance); -+ if (instance) { -+ LOG_ERR("%s: VCHI instance already open (%p)\n", -+ __func__, instance); -+ instance->alsa_stream = alsa_stream; -+ alsa_stream->instance = instance; -+ ret = 0; // xxx todo -1; -+ goto err_free_mem; -+ } -+ -+ /* Initialize and create a VCHI connection */ -+ if (!initted) { -+ ret = vchi_initialise(&vchi_instance); -+ if (ret != 0) { -+ LOG_ERR("%s: failed to initialise VCHI instance (ret=%d)\n", -+ __func__, ret); -+ -+ ret = -EIO; -+ goto err_free_mem; -+ } -+ ret = vchi_connect(NULL, 0, vchi_instance); -+ if (ret != 0) { -+ LOG_ERR("%s: failed to connect VCHI instance (ret=%d)\n", -+ __func__, ret); -+ -+ ret = -EIO; -+ goto err_free_mem; -+ } -+ initted = 1; -+ } -+ -+ /* Initialize an instance of the audio service */ -+ instance = vc_vchi_audio_init(vchi_instance, &vchi_connection, 1); -+ -+ if (instance == NULL) { -+ LOG_ERR("%s: failed to initialize audio service\n", __func__); -+ -+ ret = -EPERM; -+ goto err_free_mem; -+ } -+ -+ instance->alsa_stream = alsa_stream; -+ alsa_stream->instance = instance; -+ -+ LOG_DBG(" success !\n"); -+err_free_mem: -+ LOG_DBG(" .. OUT\n"); -+ -+ return ret; -+} -+ -+int bcm2835_audio_open(bcm2835_alsa_stream_t * alsa_stream) -+{ -+ AUDIO_INSTANCE_T *instance; -+ VC_AUDIO_MSG_T m; -+ int32_t success; -+ int ret; -+ LOG_DBG(" .. IN\n"); -+ -+ my_workqueue_init(alsa_stream); -+ -+ ret = bcm2835_audio_open_connection(alsa_stream); -+ if (ret != 0) { -+ ret = -1; -+ goto exit; -+ } -+ instance = alsa_stream->instance; -+ LOG_DBG(" instance (%p)\n", instance); -+ -+ if(mutex_lock_interruptible(&instance->vchi_mutex)) -+ { -+ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections); -+ return -EINTR; -+ } -+ vchi_service_use(instance->vchi_handle[0]); -+ -+ m.type = VC_AUDIO_MSG_TYPE_OPEN; -+ -+ /* Send the message to the videocore */ -+ success = vchi_msg_queue(instance->vchi_handle[0], -+ &m, sizeof m, -+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); -+ -+ if (success != 0) { -+ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n", -+ __func__, success); -+ -+ ret = -1; -+ goto unlock; -+ } -+ -+ ret = 0; -+ -+unlock: -+ vchi_service_release(instance->vchi_handle[0]); -+ mutex_unlock(&instance->vchi_mutex); -+exit: -+ LOG_DBG(" .. OUT\n"); -+ return ret; -+} -+ -+static int bcm2835_audio_set_ctls_chan(bcm2835_alsa_stream_t * alsa_stream, -+ bcm2835_chip_t * chip) -+{ -+ VC_AUDIO_MSG_T m; -+ AUDIO_INSTANCE_T *instance = alsa_stream->instance; -+ int32_t success; -+ int ret; -+ LOG_DBG(" .. IN\n"); -+ -+ LOG_INFO -+ (" Setting ALSA dest(%d), volume(%d)\n", chip->dest, chip->volume); -+ -+ if(mutex_lock_interruptible(&instance->vchi_mutex)) -+ { -+ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections); -+ return -EINTR; -+ } -+ vchi_service_use(instance->vchi_handle[0]); -+ -+ instance->result = -1; -+ -+ m.type = VC_AUDIO_MSG_TYPE_CONTROL; -+ m.u.control.dest = chip->dest; -+ m.u.control.volume = chip->volume; -+ -+ /* Create the message available completion */ -+ init_completion(&instance->msg_avail_comp); -+ -+ /* Send the message to the videocore */ -+ success = vchi_msg_queue(instance->vchi_handle[0], -+ &m, sizeof m, -+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); -+ -+ if (success != 0) { -+ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n", -+ __func__, success); -+ -+ ret = -1; -+ goto unlock; -+ } -+ -+ /* We are expecting a reply from the videocore */ -+ ret = wait_for_completion_interruptible(&instance->msg_avail_comp); -+ if (ret) { -+ LOG_DBG("%s: failed on waiting for event (status=%d)\n", -+ __func__, success); -+ goto unlock; -+ } -+ -+ if (instance->result != 0) { -+ LOG_ERR("%s: result=%d\n", __func__, instance->result); -+ -+ ret = -1; -+ goto unlock; -+ } -+ -+ ret = 0; -+ -+unlock: -+ vchi_service_release(instance->vchi_handle[0]); -+ mutex_unlock(&instance->vchi_mutex); -+ -+ LOG_DBG(" .. OUT\n"); -+ return ret; -+} -+ -+int bcm2835_audio_set_ctls(bcm2835_chip_t * chip) -+{ -+ int i; -+ int ret = 0; -+ LOG_DBG(" .. IN\n"); -+ LOG_DBG(" Setting ALSA dest(%d), volume(%d)\n", chip->dest, chip->volume); -+ -+ /* change ctls for all substreams */ -+ for (i = 0; i < MAX_SUBSTREAMS; i++) { -+ if (chip->avail_substreams & (1 << i)) { -+ if (!chip->alsa_stream[i]) -+ { -+ LOG_DBG(" No ALSA stream available?! %i:%p (%x)\n", i, chip->alsa_stream[i], chip->avail_substreams); -+ ret = 0; -+ } -+ else if (bcm2835_audio_set_ctls_chan /* returns 0 on success */ -+ (chip->alsa_stream[i], chip) != 0) -+ { -+ LOG_ERR("Couldn't set the controls for stream %d\n", i); -+ ret = -1; -+ } -+ else LOG_DBG(" Controls set for stream %d\n", i); -+ } -+ } -+ LOG_DBG(" .. OUT ret=%d\n", ret); -+ return ret; -+} -+ -+int bcm2835_audio_set_params(bcm2835_alsa_stream_t * alsa_stream, -+ uint32_t channels, uint32_t samplerate, -+ uint32_t bps) -+{ -+ VC_AUDIO_MSG_T m; -+ AUDIO_INSTANCE_T *instance = alsa_stream->instance; -+ int32_t success; -+ int ret; -+ LOG_DBG(" .. IN\n"); -+ -+ LOG_INFO -+ (" Setting ALSA channels(%d), samplerate(%d), bits-per-sample(%d)\n", -+ channels, samplerate, bps); -+ -+ /* resend ctls - alsa_stream may not have been open when first send */ -+ ret = bcm2835_audio_set_ctls_chan(alsa_stream, alsa_stream->chip); -+ if (ret != 0) { -+ LOG_ERR(" Alsa controls not supported\n"); -+ return -EINVAL; -+ } -+ -+ if(mutex_lock_interruptible(&instance->vchi_mutex)) -+ { -+ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections); -+ return -EINTR; -+ } -+ vchi_service_use(instance->vchi_handle[0]); -+ -+ instance->result = -1; -+ -+ m.type = VC_AUDIO_MSG_TYPE_CONFIG; -+ m.u.config.channels = channels; -+ m.u.config.samplerate = samplerate; -+ m.u.config.bps = bps; -+ -+ /* Create the message available completion */ -+ init_completion(&instance->msg_avail_comp); -+ -+ /* Send the message to the videocore */ -+ success = vchi_msg_queue(instance->vchi_handle[0], -+ &m, sizeof m, -+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); -+ -+ if (success != 0) { -+ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n", -+ __func__, success); -+ -+ ret = -1; -+ goto unlock; -+ } -+ -+ /* We are expecting a reply from the videocore */ -+ ret = wait_for_completion_interruptible(&instance->msg_avail_comp); -+ if (ret) { -+ LOG_DBG("%s: failed on waiting for event (status=%d)\n", -+ __func__, success); -+ goto unlock; -+ } -+ -+ if (instance->result != 0) { -+ LOG_ERR("%s: result=%d", __func__, instance->result); -+ -+ ret = -1; -+ goto unlock; -+ } -+ -+ ret = 0; -+ -+unlock: -+ vchi_service_release(instance->vchi_handle[0]); -+ mutex_unlock(&instance->vchi_mutex); -+ -+ LOG_DBG(" .. OUT\n"); -+ return ret; -+} -+ -+int bcm2835_audio_setup(bcm2835_alsa_stream_t * alsa_stream) -+{ -+ LOG_DBG(" .. IN\n"); -+ -+ LOG_DBG(" .. OUT\n"); -+ -+ return 0; -+} -+ -+static int bcm2835_audio_start_worker(bcm2835_alsa_stream_t * alsa_stream) -+{ -+ VC_AUDIO_MSG_T m; -+ AUDIO_INSTANCE_T *instance = alsa_stream->instance; -+ int32_t success; -+ int ret; -+ LOG_DBG(" .. IN\n"); -+ -+ if(mutex_lock_interruptible(&instance->vchi_mutex)) -+ { -+ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections); -+ return -EINTR; -+ } -+ vchi_service_use(instance->vchi_handle[0]); -+ -+ m.type = VC_AUDIO_MSG_TYPE_START; -+ -+ /* Send the message to the videocore */ -+ success = vchi_msg_queue(instance->vchi_handle[0], -+ &m, sizeof m, -+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); -+ -+ if (success != 0) { -+ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n", -+ __func__, success); -+ -+ ret = -1; -+ goto unlock; -+ } -+ -+ ret = 0; -+ -+unlock: -+ vchi_service_release(instance->vchi_handle[0]); -+ mutex_unlock(&instance->vchi_mutex); -+ LOG_DBG(" .. OUT\n"); -+ return ret; -+} -+ -+static int bcm2835_audio_stop_worker(bcm2835_alsa_stream_t * alsa_stream) -+{ -+ VC_AUDIO_MSG_T m; -+ AUDIO_INSTANCE_T *instance = alsa_stream->instance; -+ int32_t success; -+ int ret; -+ LOG_DBG(" .. IN\n"); -+ -+ if(mutex_lock_interruptible(&instance->vchi_mutex)) -+ { -+ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections); -+ return -EINTR; -+ } -+ vchi_service_use(instance->vchi_handle[0]); -+ -+ m.type = VC_AUDIO_MSG_TYPE_STOP; -+ m.u.stop.draining = alsa_stream->draining; -+ -+ /* Send the message to the videocore */ -+ success = vchi_msg_queue(instance->vchi_handle[0], -+ &m, sizeof m, -+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); -+ -+ if (success != 0) { -+ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n", -+ __func__, success); -+ -+ ret = -1; -+ goto unlock; -+ } -+ -+ ret = 0; -+ -+unlock: -+ vchi_service_release(instance->vchi_handle[0]); -+ mutex_unlock(&instance->vchi_mutex); -+ LOG_DBG(" .. OUT\n"); -+ return ret; -+} -+ -+int bcm2835_audio_close(bcm2835_alsa_stream_t * alsa_stream) -+{ -+ VC_AUDIO_MSG_T m; -+ AUDIO_INSTANCE_T *instance = alsa_stream->instance; -+ int32_t success; -+ int ret; -+ LOG_DBG(" .. IN\n"); -+ -+ my_workqueue_quit(alsa_stream); -+ -+ if(mutex_lock_interruptible(&instance->vchi_mutex)) -+ { -+ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections); -+ return -EINTR; -+ } -+ vchi_service_use(instance->vchi_handle[0]); -+ -+ m.type = VC_AUDIO_MSG_TYPE_CLOSE; -+ -+ /* Create the message available completion */ -+ init_completion(&instance->msg_avail_comp); -+ -+ /* Send the message to the videocore */ -+ success = vchi_msg_queue(instance->vchi_handle[0], -+ &m, sizeof m, -+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); -+ -+ if (success != 0) { -+ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n", -+ __func__, success); -+ ret = -1; -+ goto unlock; -+ } -+ -+ ret = wait_for_completion_interruptible(&instance->msg_avail_comp); -+ if (ret) { -+ LOG_DBG("%s: failed on waiting for event (status=%d)\n", -+ __func__, success); -+ goto unlock; -+ } -+ if (instance->result != 0) { -+ LOG_ERR("%s: failed result (status=%d)\n", -+ __func__, instance->result); -+ -+ ret = -1; -+ goto unlock; -+ } -+ -+ ret = 0; -+ -+unlock: -+ vchi_service_release(instance->vchi_handle[0]); -+ mutex_unlock(&instance->vchi_mutex); -+ -+ /* Stop the audio service */ -+ if (instance) { -+ vc_vchi_audio_deinit(instance); -+ alsa_stream->instance = NULL; -+ } -+ LOG_DBG(" .. OUT\n"); -+ return ret; -+} -+ -+int bcm2835_audio_write_worker(bcm2835_alsa_stream_t *alsa_stream, -+ uint32_t count, void *src) -+{ -+ VC_AUDIO_MSG_T m; -+ AUDIO_INSTANCE_T *instance = alsa_stream->instance; -+ int32_t success; -+ int ret; -+ -+ LOG_DBG(" .. IN\n"); -+ -+ LOG_INFO(" Writing %d bytes from %p\n", count, src); -+ -+ if(mutex_lock_interruptible(&instance->vchi_mutex)) -+ { -+ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections); -+ return -EINTR; -+ } -+ vchi_service_use(instance->vchi_handle[0]); -+ -+ if ( instance->peer_version==0 && vchi_get_peer_version(instance->vchi_handle[0], &instance->peer_version) == 0 ) { -+ LOG_DBG("%s: client version %d connected\n", __func__, instance->peer_version); -+ } -+ m.type = VC_AUDIO_MSG_TYPE_WRITE; -+ m.u.write.count = count; -+ // old version uses bulk, new version uses control -+ m.u.write.max_packet = instance->peer_version < 2 || force_bulk ? 0:4000; -+ m.u.write.callback = alsa_stream->fifo_irq_handler; -+ m.u.write.cookie = alsa_stream; -+ m.u.write.silence = src == NULL; -+ -+ /* Send the message to the videocore */ -+ success = vchi_msg_queue(instance->vchi_handle[0], -+ &m, sizeof m, -+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); -+ -+ if (success != 0) { -+ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n", -+ __func__, success); -+ -+ ret = -1; -+ goto unlock; -+ } -+ if (!m.u.write.silence) { -+ if (m.u.write.max_packet == 0) { -+ /* Send the message to the videocore */ -+ success = vchi_bulk_queue_transmit(instance->vchi_handle[0], -+ src, count, -+ 0 * -+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED -+ + -+ 1 * -+ VCHI_FLAGS_BLOCK_UNTIL_DATA_READ, -+ NULL); -+ } else { -+ while (count > 0) { -+ int bytes = min((int)m.u.write.max_packet, (int)count); -+ success = vchi_msg_queue(instance->vchi_handle[0], -+ src, bytes, -+ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); -+ src = (char *)src + bytes; -+ count -= bytes; -+ } -+ } -+ if (success != 0) { -+ LOG_ERR -+ ("%s: failed on vchi_bulk_queue_transmit (status=%d)\n", -+ __func__, success); -+ -+ ret = -1; -+ goto unlock; -+ } -+ } -+ ret = 0; -+ -+unlock: -+ vchi_service_release(instance->vchi_handle[0]); -+ mutex_unlock(&instance->vchi_mutex); -+ LOG_DBG(" .. OUT\n"); -+ return ret; -+} -+ -+/** -+ * Returns all buffers from arm->vc -+ */ -+void bcm2835_audio_flush_buffers(bcm2835_alsa_stream_t * alsa_stream) -+{ -+ LOG_DBG(" .. IN\n"); -+ LOG_DBG(" .. OUT\n"); -+ return; -+} -+ -+/** -+ * Forces VC to flush(drop) its filled playback buffers and -+ * return them the us. (VC->ARM) -+ */ -+void bcm2835_audio_flush_playback_buffers(bcm2835_alsa_stream_t * alsa_stream) -+{ -+ LOG_DBG(" .. IN\n"); -+ LOG_DBG(" .. OUT\n"); -+} -+ -+uint32_t bcm2835_audio_retrieve_buffers(bcm2835_alsa_stream_t * alsa_stream) -+{ -+ uint32_t count = atomic_read(&alsa_stream->retrieved); -+ atomic_sub(count, &alsa_stream->retrieved); -+ return count; -+} -+ -+module_param(force_bulk, bool, 0444); -+MODULE_PARM_DESC(force_bulk, "Force use of vchiq bulk for audio"); -diff -Nur linux-4.1.13.orig/sound/arm/Kconfig linux-rpi/sound/arm/Kconfig ---- linux-4.1.13.orig/sound/arm/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/sound/arm/Kconfig 2015-11-29 09:42:41.446997173 +0100 -@@ -40,5 +40,13 @@ - Say Y or M if you want to support any AC97 codec attached to - the PXA2xx AC97 interface. - -+config SND_BCM2835 -+ tristate "BCM2835 ALSA driver" -+ depends on (ARCH_BCM2708 || ARCH_BCM2709 || ARCH_BCM2835) \ -+ && BCM2708_VCHIQ && SND -+ select SND_PCM -+ help -+ Say Y or M if you want to support BCM2835 Alsa pcm card driver -+ - endif # SND_ARM - -diff -Nur linux-4.1.13.orig/sound/arm/Makefile linux-rpi/sound/arm/Makefile ---- linux-4.1.13.orig/sound/arm/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/sound/arm/Makefile 2015-11-29 09:42:41.446997173 +0100 -@@ -14,3 +14,8 @@ - - obj-$(CONFIG_SND_PXA2XX_AC97) += snd-pxa2xx-ac97.o - snd-pxa2xx-ac97-objs := pxa2xx-ac97.o -+ -+obj-$(CONFIG_SND_BCM2835) += snd-bcm2835.o -+snd-bcm2835-objs := bcm2835.o bcm2835-ctl.o bcm2835-pcm.o bcm2835-vchiq.o -+ -+ccflags-y += -Idrivers/misc/vc04_services -Idrivers/misc/vc04_services/interface/vcos/linuxkernel -D__VCCOREVER__=0x04000000 -diff -Nur linux-4.1.13.orig/sound/arm/vc_vchi_audioserv_defs.h linux-rpi/sound/arm/vc_vchi_audioserv_defs.h ---- linux-4.1.13.orig/sound/arm/vc_vchi_audioserv_defs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/sound/arm/vc_vchi_audioserv_defs.h 2015-11-29 09:42:41.446997173 +0100 -@@ -0,0 +1,116 @@ -+/***************************************************************************** -+* Copyright 2011 Broadcom Corporation. All rights reserved. -+* -+* Unless you and Broadcom execute a separate written software license -+* agreement governing use of this software, this software is licensed to you -+* under the terms of the GNU General Public License version 2, available at -+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). -+* -+* Notwithstanding the above, under no circumstances may you combine this -+* software in any way with any other Broadcom software provided under a -+* license other than the GPL, without Broadcom's express prior written -+* consent. -+*****************************************************************************/ -+ -+#ifndef _VC_AUDIO_DEFS_H_ -+#define _VC_AUDIO_DEFS_H_ -+ -+#define VC_AUDIOSERV_MIN_VER 1 -+#define VC_AUDIOSERV_VER 2 -+ -+// FourCC code used for VCHI connection -+#define VC_AUDIO_SERVER_NAME MAKE_FOURCC("AUDS") -+ -+// Maximum message length -+#define VC_AUDIO_MAX_MSG_LEN (sizeof( VC_AUDIO_MSG_T )) -+ -+// List of screens that are currently supported -+// All message types supported for HOST->VC direction -+typedef enum { -+ VC_AUDIO_MSG_TYPE_RESULT, // Generic result -+ VC_AUDIO_MSG_TYPE_COMPLETE, // Generic result -+ VC_AUDIO_MSG_TYPE_CONFIG, // Configure audio -+ VC_AUDIO_MSG_TYPE_CONTROL, // Configure audio -+ VC_AUDIO_MSG_TYPE_OPEN, // Configure audio -+ VC_AUDIO_MSG_TYPE_CLOSE, // Configure audio -+ VC_AUDIO_MSG_TYPE_START, // Configure audio -+ VC_AUDIO_MSG_TYPE_STOP, // Configure audio -+ VC_AUDIO_MSG_TYPE_WRITE, // Configure audio -+ VC_AUDIO_MSG_TYPE_MAX -+} VC_AUDIO_MSG_TYPE; -+ -+// configure the audio -+typedef struct { -+ uint32_t channels; -+ uint32_t samplerate; -+ uint32_t bps; -+ -+} VC_AUDIO_CONFIG_T; -+ -+typedef struct { -+ uint32_t volume; -+ uint32_t dest; -+ -+} VC_AUDIO_CONTROL_T; -+ -+// audio -+typedef struct { -+ uint32_t dummy; -+ -+} VC_AUDIO_OPEN_T; -+ -+// audio -+typedef struct { -+ uint32_t dummy; -+ -+} VC_AUDIO_CLOSE_T; -+// audio -+typedef struct { -+ uint32_t dummy; -+ -+} VC_AUDIO_START_T; -+// audio -+typedef struct { -+ uint32_t draining; -+ -+} VC_AUDIO_STOP_T; -+ -+// configure the write audio samples -+typedef struct { -+ uint32_t count; // in bytes -+ void *callback; -+ void *cookie; -+ uint16_t silence; -+ uint16_t max_packet; -+} VC_AUDIO_WRITE_T; -+ -+// Generic result for a request (VC->HOST) -+typedef struct { -+ int32_t success; // Success value -+ -+} VC_AUDIO_RESULT_T; -+ -+// Generic result for a request (VC->HOST) -+typedef struct { -+ int32_t count; // Success value -+ void *callback; -+ void *cookie; -+} VC_AUDIO_COMPLETE_T; -+ -+// Message header for all messages in HOST->VC direction -+typedef struct { -+ int32_t type; // Message type (VC_AUDIO_MSG_TYPE) -+ union { -+ VC_AUDIO_CONFIG_T config; -+ VC_AUDIO_CONTROL_T control; -+ VC_AUDIO_OPEN_T open; -+ VC_AUDIO_CLOSE_T close; -+ VC_AUDIO_START_T start; -+ VC_AUDIO_STOP_T stop; -+ VC_AUDIO_WRITE_T write; -+ VC_AUDIO_RESULT_T result; -+ VC_AUDIO_COMPLETE_T complete; -+ } u; -+} VC_AUDIO_MSG_T; -+ -+#endif // _VC_AUDIO_DEFS_H_ -diff -Nur linux-4.1.13.orig/sound/soc/bcm/bcm2708-i2s.c linux-rpi/sound/soc/bcm/bcm2708-i2s.c ---- linux-4.1.13.orig/sound/soc/bcm/bcm2708-i2s.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/sound/soc/bcm/bcm2708-i2s.c 2015-11-29 09:42:41.558989731 +0100 -@@ -0,0 +1,1014 @@ -+/* -+ * ALSA SoC I2S Audio Layer for Broadcom BCM2708 SoC -+ * -+ * Author: Florian Meier -+ * Copyright 2013 -+ * -+ * Based on -+ * Raspberry Pi PCM I2S ALSA Driver -+ * Copyright (c) by Phil Poole 2013 -+ * -+ * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor -+ * Vladimir Barinov, -+ * Copyright (C) 2007 MontaVista Software, Inc., -+ * -+ * OMAP ALSA SoC DAI driver using McBSP port -+ * Copyright (C) 2008 Nokia Corporation -+ * Contact: Jarkko Nikula -+ * Peter Ujfalusi -+ * -+ * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver -+ * Author: Timur Tabi -+ * Copyright 2007-2010 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ */ -+ -+#include "bcm2708-i2s.h" -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+/* Clock registers */ -+#define BCM2708_CLK_PCMCTL_REG 0x00 -+#define BCM2708_CLK_PCMDIV_REG 0x04 -+ -+/* Clock register settings */ -+#define BCM2708_CLK_PASSWD (0x5a000000) -+#define BCM2708_CLK_PASSWD_MASK (0xff000000) -+#define BCM2708_CLK_MASH(v) ((v) << 9) -+#define BCM2708_CLK_FLIP BIT(8) -+#define BCM2708_CLK_BUSY BIT(7) -+#define BCM2708_CLK_KILL BIT(5) -+#define BCM2708_CLK_ENAB BIT(4) -+#define BCM2708_CLK_SRC(v) (v) -+ -+#define BCM2708_CLK_SHIFT (12) -+#define BCM2708_CLK_DIVI(v) ((v) << BCM2708_CLK_SHIFT) -+#define BCM2708_CLK_DIVF(v) (v) -+#define BCM2708_CLK_DIVF_MASK (0xFFF) -+ -+enum { -+ BCM2708_CLK_MASH_0 = 0, -+ BCM2708_CLK_MASH_1, -+ BCM2708_CLK_MASH_2, -+ BCM2708_CLK_MASH_3, -+}; -+ -+enum { -+ BCM2708_CLK_SRC_GND = 0, -+ BCM2708_CLK_SRC_OSC, -+ BCM2708_CLK_SRC_DBG0, -+ BCM2708_CLK_SRC_DBG1, -+ BCM2708_CLK_SRC_PLLA, -+ BCM2708_CLK_SRC_PLLC, -+ BCM2708_CLK_SRC_PLLD, -+ BCM2708_CLK_SRC_HDMI, -+}; -+ -+/* Most clocks are not useable (freq = 0) */ -+static const unsigned int bcm2708_clk_freq[BCM2708_CLK_SRC_HDMI+1] = { -+ [BCM2708_CLK_SRC_GND] = 0, -+ [BCM2708_CLK_SRC_OSC] = 19200000, -+ [BCM2708_CLK_SRC_DBG0] = 0, -+ [BCM2708_CLK_SRC_DBG1] = 0, -+ [BCM2708_CLK_SRC_PLLA] = 0, -+ [BCM2708_CLK_SRC_PLLC] = 0, -+ [BCM2708_CLK_SRC_PLLD] = 500000000, -+ [BCM2708_CLK_SRC_HDMI] = 0, -+}; -+ -+/* I2S registers */ -+#define BCM2708_I2S_CS_A_REG 0x00 -+#define BCM2708_I2S_FIFO_A_REG 0x04 -+#define BCM2708_I2S_MODE_A_REG 0x08 -+#define BCM2708_I2S_RXC_A_REG 0x0c -+#define BCM2708_I2S_TXC_A_REG 0x10 -+#define BCM2708_I2S_DREQ_A_REG 0x14 -+#define BCM2708_I2S_INTEN_A_REG 0x18 -+#define BCM2708_I2S_INTSTC_A_REG 0x1c -+#define BCM2708_I2S_GRAY_REG 0x20 -+ -+/* I2S register settings */ -+#define BCM2708_I2S_STBY BIT(25) -+#define BCM2708_I2S_SYNC BIT(24) -+#define BCM2708_I2S_RXSEX BIT(23) -+#define BCM2708_I2S_RXF BIT(22) -+#define BCM2708_I2S_TXE BIT(21) -+#define BCM2708_I2S_RXD BIT(20) -+#define BCM2708_I2S_TXD BIT(19) -+#define BCM2708_I2S_RXR BIT(18) -+#define BCM2708_I2S_TXW BIT(17) -+#define BCM2708_I2S_CS_RXERR BIT(16) -+#define BCM2708_I2S_CS_TXERR BIT(15) -+#define BCM2708_I2S_RXSYNC BIT(14) -+#define BCM2708_I2S_TXSYNC BIT(13) -+#define BCM2708_I2S_DMAEN BIT(9) -+#define BCM2708_I2S_RXTHR(v) ((v) << 7) -+#define BCM2708_I2S_TXTHR(v) ((v) << 5) -+#define BCM2708_I2S_RXCLR BIT(4) -+#define BCM2708_I2S_TXCLR BIT(3) -+#define BCM2708_I2S_TXON BIT(2) -+#define BCM2708_I2S_RXON BIT(1) -+#define BCM2708_I2S_EN (1) -+ -+#define BCM2708_I2S_CLKDIS BIT(28) -+#define BCM2708_I2S_PDMN BIT(27) -+#define BCM2708_I2S_PDME BIT(26) -+#define BCM2708_I2S_FRXP BIT(25) -+#define BCM2708_I2S_FTXP BIT(24) -+#define BCM2708_I2S_CLKM BIT(23) -+#define BCM2708_I2S_CLKI BIT(22) -+#define BCM2708_I2S_FSM BIT(21) -+#define BCM2708_I2S_FSI BIT(20) -+#define BCM2708_I2S_FLEN(v) ((v) << 10) -+#define BCM2708_I2S_FSLEN(v) (v) -+ -+#define BCM2708_I2S_CHWEX BIT(15) -+#define BCM2708_I2S_CHEN BIT(14) -+#define BCM2708_I2S_CHPOS(v) ((v) << 4) -+#define BCM2708_I2S_CHWID(v) (v) -+#define BCM2708_I2S_CH1(v) ((v) << 16) -+#define BCM2708_I2S_CH2(v) (v) -+ -+#define BCM2708_I2S_TX_PANIC(v) ((v) << 24) -+#define BCM2708_I2S_RX_PANIC(v) ((v) << 16) -+#define BCM2708_I2S_TX(v) ((v) << 8) -+#define BCM2708_I2S_RX(v) (v) -+ -+#define BCM2708_I2S_INT_RXERR BIT(3) -+#define BCM2708_I2S_INT_TXERR BIT(2) -+#define BCM2708_I2S_INT_RXR BIT(1) -+#define BCM2708_I2S_INT_TXW BIT(0) -+ -+/* I2S DMA interface */ -+#define BCM2708_I2S_FIFO_PHYSICAL_ADDR 0x7E203004 -+#define BCM2708_DMA_DREQ_PCM_TX 2 -+#define BCM2708_DMA_DREQ_PCM_RX 3 -+ -+/* I2S pin configuration */ -+static int bcm2708_i2s_gpio=BCM2708_I2S_GPIO_AUTO; -+ -+/* General device struct */ -+struct bcm2708_i2s_dev { -+ struct device *dev; -+ struct snd_dmaengine_dai_dma_data dma_data[2]; -+ unsigned int fmt; -+ unsigned int bclk_ratio; -+ -+ struct regmap *i2s_regmap; -+ struct regmap *clk_regmap; -+}; -+ -+void bcm2708_i2s_set_gpio(int gpio) { -+ bcm2708_i2s_gpio=gpio; -+} -+EXPORT_SYMBOL(bcm2708_i2s_set_gpio); -+ -+ -+static void bcm2708_i2s_start_clock(struct bcm2708_i2s_dev *dev) -+{ -+ /* Start the clock if in master mode */ -+ unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK; -+ -+ switch (master) { -+ case SND_SOC_DAIFMT_CBS_CFS: -+ case SND_SOC_DAIFMT_CBS_CFM: -+ regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, -+ BCM2708_CLK_PASSWD_MASK | BCM2708_CLK_ENAB, -+ BCM2708_CLK_PASSWD | BCM2708_CLK_ENAB); -+ break; -+ default: -+ break; -+ } -+} -+ -+static void bcm2708_i2s_stop_clock(struct bcm2708_i2s_dev *dev) -+{ -+ uint32_t clkreg; -+ int timeout = 1000; -+ -+ /* Stop clock */ -+ regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, -+ BCM2708_CLK_PASSWD_MASK | BCM2708_CLK_ENAB, -+ BCM2708_CLK_PASSWD); -+ -+ /* Wait for the BUSY flag going down */ -+ while (--timeout) { -+ regmap_read(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, &clkreg); -+ if (!(clkreg & BCM2708_CLK_BUSY)) -+ break; -+ } -+ -+ if (!timeout) { -+ /* KILL the clock */ -+ dev_err(dev->dev, "I2S clock didn't stop. Kill the clock!\n"); -+ regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, -+ BCM2708_CLK_KILL | BCM2708_CLK_PASSWD_MASK, -+ BCM2708_CLK_KILL | BCM2708_CLK_PASSWD); -+ } -+} -+ -+static void bcm2708_i2s_clear_fifos(struct bcm2708_i2s_dev *dev, -+ bool tx, bool rx) -+{ -+ int timeout = 1000; -+ uint32_t syncval; -+ uint32_t csreg; -+ uint32_t i2s_active_state; -+ uint32_t clkreg; -+ uint32_t clk_active_state; -+ uint32_t off; -+ uint32_t clr; -+ -+ off = tx ? BCM2708_I2S_TXON : 0; -+ off |= rx ? BCM2708_I2S_RXON : 0; -+ -+ clr = tx ? BCM2708_I2S_TXCLR : 0; -+ clr |= rx ? BCM2708_I2S_RXCLR : 0; -+ -+ /* Backup the current state */ -+ regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &csreg); -+ i2s_active_state = csreg & (BCM2708_I2S_RXON | BCM2708_I2S_TXON); -+ -+ regmap_read(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, &clkreg); -+ clk_active_state = clkreg & BCM2708_CLK_ENAB; -+ -+ /* Start clock if not running */ -+ if (!clk_active_state) { -+ regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, -+ BCM2708_CLK_PASSWD_MASK | BCM2708_CLK_ENAB, -+ BCM2708_CLK_PASSWD | BCM2708_CLK_ENAB); -+ } -+ -+ /* Stop I2S module */ -+ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, off, 0); -+ -+ /* -+ * Clear the FIFOs -+ * Requires at least 2 PCM clock cycles to take effect -+ */ -+ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, clr, clr); -+ -+ /* Wait for 2 PCM clock cycles */ -+ -+ /* -+ * Toggle the SYNC flag. After 2 PCM clock cycles it can be read back -+ * FIXME: This does not seem to work for slave mode! -+ */ -+ regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &syncval); -+ syncval &= BCM2708_I2S_SYNC; -+ -+ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, -+ BCM2708_I2S_SYNC, ~syncval); -+ -+ /* Wait for the SYNC flag changing it's state */ -+ while (--timeout) { -+ regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &csreg); -+ if ((csreg & BCM2708_I2S_SYNC) != syncval) -+ break; -+ } -+ -+ if (!timeout) -+ dev_err(dev->dev, "I2S SYNC error!\n"); -+ -+ /* Stop clock if it was not running before */ -+ if (!clk_active_state) -+ bcm2708_i2s_stop_clock(dev); -+ -+ /* Restore I2S state */ -+ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, -+ BCM2708_I2S_RXON | BCM2708_I2S_TXON, i2s_active_state); -+} -+ -+static int bcm2708_i2s_set_dai_fmt(struct snd_soc_dai *dai, -+ unsigned int fmt) -+{ -+ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); -+ dev->fmt = fmt; -+ return 0; -+} -+ -+static int bcm2708_i2s_set_dai_bclk_ratio(struct snd_soc_dai *dai, -+ unsigned int ratio) -+{ -+ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); -+ dev->bclk_ratio = ratio; -+ return 0; -+} -+ -+ -+static int bcm2708_i2s_set_function(unsigned offset, int function) -+{ -+ #define GPIOFSEL(x) (0x00+(x)*4) -+ void __iomem *gpio = __io_address(GPIO_BASE); -+ unsigned alt = function <= 3 ? function + 4: function == 4 ? 3 : 2; -+ unsigned gpiodir; -+ unsigned gpio_bank = offset / 10; -+ unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3; -+ -+ if (offset >= BCM2708_NR_GPIOS) -+ return -EINVAL; -+ -+ gpiodir = readl(gpio + GPIOFSEL(gpio_bank)); -+ gpiodir &= ~(7 << gpio_field_offset); -+ gpiodir |= alt << gpio_field_offset; -+ writel(gpiodir, gpio + GPIOFSEL(gpio_bank)); -+ return 0; -+} -+ -+static void bcm2708_i2s_setup_gpio(void) -+{ -+ /* -+ * This is the common way to handle the GPIO pins for -+ * the Raspberry Pi. -+ * TODO Better way would be to handle -+ * this in the device tree! -+ */ -+ int pin,pinconfig,startpin,alt; -+ -+ /* SPI is on different GPIOs on different boards */ -+ /* for Raspberry Pi B+, this is pin GPIO18-21, for original on 28-31 */ -+ if (bcm2708_i2s_gpio==BCM2708_I2S_GPIO_AUTO) { -+ if ((system_rev & 0xffffff) >= 0x10) { -+ /* Model B+ */ -+ pinconfig=BCM2708_I2S_GPIO_PIN18; -+ } else { -+ /* original */ -+ pinconfig=BCM2708_I2S_GPIO_PIN28; -+ } -+ } else { -+ pinconfig=bcm2708_i2s_gpio; -+ } -+ -+ if (pinconfig==BCM2708_I2S_GPIO_PIN18) { -+ startpin=18; -+ alt=BCM2708_I2S_GPIO_PIN18_ALT; -+ } else if (pinconfig==BCM2708_I2S_GPIO_PIN28) { -+ startpin=28; -+ alt=BCM2708_I2S_GPIO_PIN28_ALT; -+ } else { -+ printk(KERN_INFO "Can't configure I2S GPIOs, unknown pin mode for I2S: %i\n",pinconfig); -+ return; -+ } -+ -+ /* configure I2S pins to correct ALT mode */ -+ for (pin = startpin; pin <= startpin+3; pin++) { -+ bcm2708_i2s_set_function(pin, alt); -+ } -+} -+ -+static int bcm2708_i2s_hw_params(struct snd_pcm_substream *substream, -+ struct snd_pcm_hw_params *params, -+ struct snd_soc_dai *dai) -+{ -+ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); -+ -+ unsigned int sampling_rate = params_rate(params); -+ unsigned int data_length, data_delay, bclk_ratio; -+ unsigned int ch1pos, ch2pos, mode, format; -+ unsigned int mash = BCM2708_CLK_MASH_1; -+ unsigned int divi, divf, target_frequency; -+ int clk_src = -1; -+ unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK; -+ bool bit_master = (master == SND_SOC_DAIFMT_CBS_CFS -+ || master == SND_SOC_DAIFMT_CBS_CFM); -+ -+ bool frame_master = (master == SND_SOC_DAIFMT_CBS_CFS -+ || master == SND_SOC_DAIFMT_CBM_CFS); -+ uint32_t csreg; -+ -+ /* -+ * If a stream is already enabled, -+ * the registers are already set properly. -+ */ -+ regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &csreg); -+ -+ if (csreg & (BCM2708_I2S_TXON | BCM2708_I2S_RXON)) -+ return 0; -+ -+ if (!dev->dev->of_node) -+ bcm2708_i2s_setup_gpio(); -+ -+ /* -+ * Adjust the data length according to the format. -+ * We prefill the half frame length with an integer -+ * divider of 2400 as explained at the clock settings. -+ * Maybe it is overwritten there, if the Integer mode -+ * does not apply. -+ */ -+ switch (params_format(params)) { -+ case SNDRV_PCM_FORMAT_S16_LE: -+ data_length = 16; -+ bclk_ratio = 50; -+ break; -+ case SNDRV_PCM_FORMAT_S24_LE: -+ data_length = 24; -+ bclk_ratio = 50; -+ break; -+ case SNDRV_PCM_FORMAT_S32_LE: -+ data_length = 32; -+ bclk_ratio = 100; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ /* If bclk_ratio already set, use that one. */ -+ if (dev->bclk_ratio) -+ bclk_ratio = dev->bclk_ratio; -+ -+ /* -+ * Clock Settings -+ * -+ * The target frequency of the bit clock is -+ * sampling rate * frame length -+ * -+ * Integer mode: -+ * Sampling rates that are multiples of 8000 kHz -+ * can be driven by the oscillator of 19.2 MHz -+ * with an integer divider as long as the frame length -+ * is an integer divider of 19200000/8000=2400 as set up above. -+ * This is no longer possible if the sampling rate -+ * is too high (e.g. 192 kHz), because the oscillator is too slow. -+ * -+ * MASH mode: -+ * For all other sampling rates, it is not possible to -+ * have an integer divider. Approximate the clock -+ * with the MASH module that induces a slight frequency -+ * variance. To minimize that it is best to have the fastest -+ * clock here. That is PLLD with 500 MHz. -+ */ -+ target_frequency = sampling_rate * bclk_ratio; -+ clk_src = BCM2708_CLK_SRC_OSC; -+ mash = BCM2708_CLK_MASH_0; -+ -+ if (bcm2708_clk_freq[clk_src] % target_frequency == 0 -+ && bit_master && frame_master) { -+ divi = bcm2708_clk_freq[clk_src] / target_frequency; -+ divf = 0; -+ } else { -+ uint64_t dividend; -+ -+ if (!dev->bclk_ratio) { -+ /* -+ * Overwrite bclk_ratio, because the -+ * above trick is not needed or can -+ * not be used. -+ */ -+ bclk_ratio = 2 * data_length; -+ } -+ -+ target_frequency = sampling_rate * bclk_ratio; -+ -+ clk_src = BCM2708_CLK_SRC_PLLD; -+ mash = BCM2708_CLK_MASH_1; -+ -+ dividend = bcm2708_clk_freq[clk_src]; -+ dividend <<= BCM2708_CLK_SHIFT; -+ do_div(dividend, target_frequency); -+ divi = dividend >> BCM2708_CLK_SHIFT; -+ divf = dividend & BCM2708_CLK_DIVF_MASK; -+ } -+ -+ /* Clock should only be set up here if CPU is clock master */ -+ if (((dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBS_CFS) || -+ ((dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBS_CFM)) { -+ /* Set clock divider */ -+ regmap_write(dev->clk_regmap, BCM2708_CLK_PCMDIV_REG, BCM2708_CLK_PASSWD -+ | BCM2708_CLK_DIVI(divi) -+ | BCM2708_CLK_DIVF(divf)); -+ -+ /* Setup clock, but don't start it yet */ -+ regmap_write(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, BCM2708_CLK_PASSWD -+ | BCM2708_CLK_MASH(mash) -+ | BCM2708_CLK_SRC(clk_src)); -+ } -+ -+ /* Setup the frame format */ -+ format = BCM2708_I2S_CHEN; -+ -+ if (data_length >= 24) -+ format |= BCM2708_I2S_CHWEX; -+ -+ format |= BCM2708_I2S_CHWID((data_length-8)&0xf); -+ -+ switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) { -+ case SND_SOC_DAIFMT_I2S: -+ data_delay = 1; -+ break; -+ default: -+ /* -+ * TODO -+ * Others are possible but are not implemented at the moment. -+ */ -+ dev_err(dev->dev, "%s:bad format\n", __func__); -+ return -EINVAL; -+ } -+ -+ ch1pos = data_delay; -+ ch2pos = bclk_ratio / 2 + data_delay; -+ -+ switch (params_channels(params)) { -+ case 2: -+ format = BCM2708_I2S_CH1(format) | BCM2708_I2S_CH2(format); -+ format |= BCM2708_I2S_CH1(BCM2708_I2S_CHPOS(ch1pos)); -+ format |= BCM2708_I2S_CH2(BCM2708_I2S_CHPOS(ch2pos)); -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ /* -+ * Set format for both streams. -+ * We cannot set another frame length -+ * (and therefore word length) anyway, -+ * so the format will be the same. -+ */ -+ regmap_write(dev->i2s_regmap, BCM2708_I2S_RXC_A_REG, format); -+ regmap_write(dev->i2s_regmap, BCM2708_I2S_TXC_A_REG, format); -+ -+ /* Setup the I2S mode */ -+ mode = 0; -+ -+ if (data_length <= 16) { -+ /* -+ * Use frame packed mode (2 channels per 32 bit word) -+ * We cannot set another frame length in the second stream -+ * (and therefore word length) anyway, -+ * so the format will be the same. -+ */ -+ mode |= BCM2708_I2S_FTXP | BCM2708_I2S_FRXP; -+ } -+ -+ mode |= BCM2708_I2S_FLEN(bclk_ratio - 1); -+ mode |= BCM2708_I2S_FSLEN(bclk_ratio / 2); -+ -+ /* Master or slave? */ -+ switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) { -+ case SND_SOC_DAIFMT_CBS_CFS: -+ /* CPU is master */ -+ break; -+ case SND_SOC_DAIFMT_CBM_CFS: -+ /* -+ * CODEC is bit clock master -+ * CPU is frame master -+ */ -+ mode |= BCM2708_I2S_CLKM; -+ break; -+ case SND_SOC_DAIFMT_CBS_CFM: -+ /* -+ * CODEC is frame master -+ * CPU is bit clock master -+ */ -+ mode |= BCM2708_I2S_FSM; -+ break; -+ case SND_SOC_DAIFMT_CBM_CFM: -+ /* CODEC is master */ -+ mode |= BCM2708_I2S_CLKM; -+ mode |= BCM2708_I2S_FSM; -+ break; -+ default: -+ dev_err(dev->dev, "%s:bad master\n", __func__); -+ return -EINVAL; -+ } -+ -+ /* -+ * Invert clocks? -+ * -+ * The BCM approach seems to be inverted to the classical I2S approach. -+ */ -+ switch (dev->fmt & SND_SOC_DAIFMT_INV_MASK) { -+ case SND_SOC_DAIFMT_NB_NF: -+ /* None. Therefore, both for BCM */ -+ mode |= BCM2708_I2S_CLKI; -+ mode |= BCM2708_I2S_FSI; -+ break; -+ case SND_SOC_DAIFMT_IB_IF: -+ /* Both. Therefore, none for BCM */ -+ break; -+ case SND_SOC_DAIFMT_NB_IF: -+ /* -+ * Invert only frame sync. Therefore, -+ * invert only bit clock for BCM -+ */ -+ mode |= BCM2708_I2S_CLKI; -+ break; -+ case SND_SOC_DAIFMT_IB_NF: -+ /* -+ * Invert only bit clock. Therefore, -+ * invert only frame sync for BCM -+ */ -+ mode |= BCM2708_I2S_FSI; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ regmap_write(dev->i2s_regmap, BCM2708_I2S_MODE_A_REG, mode); -+ -+ /* Setup the DMA parameters */ -+ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, -+ BCM2708_I2S_RXTHR(1) -+ | BCM2708_I2S_TXTHR(1) -+ | BCM2708_I2S_DMAEN, 0xffffffff); -+ -+ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_DREQ_A_REG, -+ BCM2708_I2S_TX_PANIC(0x10) -+ | BCM2708_I2S_RX_PANIC(0x30) -+ | BCM2708_I2S_TX(0x30) -+ | BCM2708_I2S_RX(0x20), 0xffffffff); -+ -+ /* Clear FIFOs */ -+ bcm2708_i2s_clear_fifos(dev, true, true); -+ -+ return 0; -+} -+ -+static int bcm2708_i2s_prepare(struct snd_pcm_substream *substream, -+ struct snd_soc_dai *dai) -+{ -+ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); -+ uint32_t cs_reg; -+ -+ bcm2708_i2s_start_clock(dev); -+ -+ /* -+ * Clear both FIFOs if the one that should be started -+ * is not empty at the moment. This should only happen -+ * after overrun. Otherwise, hw_params would have cleared -+ * the FIFO. -+ */ -+ regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &cs_reg); -+ -+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK -+ && !(cs_reg & BCM2708_I2S_TXE)) -+ bcm2708_i2s_clear_fifos(dev, true, false); -+ else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE -+ && (cs_reg & BCM2708_I2S_RXD)) -+ bcm2708_i2s_clear_fifos(dev, false, true); -+ -+ return 0; -+} -+ -+static void bcm2708_i2s_stop(struct bcm2708_i2s_dev *dev, -+ struct snd_pcm_substream *substream, -+ struct snd_soc_dai *dai) -+{ -+ uint32_t mask; -+ -+ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) -+ mask = BCM2708_I2S_RXON; -+ else -+ mask = BCM2708_I2S_TXON; -+ -+ regmap_update_bits(dev->i2s_regmap, -+ BCM2708_I2S_CS_A_REG, mask, 0); -+ -+ /* Stop also the clock when not SND_SOC_DAIFMT_CONT */ -+ if (!dai->active && !(dev->fmt & SND_SOC_DAIFMT_CONT)) -+ bcm2708_i2s_stop_clock(dev); -+} -+ -+static int bcm2708_i2s_trigger(struct snd_pcm_substream *substream, int cmd, -+ struct snd_soc_dai *dai) -+{ -+ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); -+ uint32_t mask; -+ -+ switch (cmd) { -+ case SNDRV_PCM_TRIGGER_START: -+ case SNDRV_PCM_TRIGGER_RESUME: -+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: -+ bcm2708_i2s_start_clock(dev); -+ -+ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) -+ mask = BCM2708_I2S_RXON; -+ else -+ mask = BCM2708_I2S_TXON; -+ -+ regmap_update_bits(dev->i2s_regmap, -+ BCM2708_I2S_CS_A_REG, mask, mask); -+ break; -+ -+ case SNDRV_PCM_TRIGGER_STOP: -+ case SNDRV_PCM_TRIGGER_SUSPEND: -+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH: -+ bcm2708_i2s_stop(dev, substream, dai); -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static int bcm2708_i2s_startup(struct snd_pcm_substream *substream, -+ struct snd_soc_dai *dai) -+{ -+ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); -+ -+ if (dai->active) -+ return 0; -+ -+ /* Should this still be running stop it */ -+ bcm2708_i2s_stop_clock(dev); -+ -+ /* Enable PCM block */ -+ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, -+ BCM2708_I2S_EN, BCM2708_I2S_EN); -+ -+ /* -+ * Disable STBY. -+ * Requires at least 4 PCM clock cycles to take effect. -+ */ -+ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, -+ BCM2708_I2S_STBY, BCM2708_I2S_STBY); -+ -+ return 0; -+} -+ -+static void bcm2708_i2s_shutdown(struct snd_pcm_substream *substream, -+ struct snd_soc_dai *dai) -+{ -+ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); -+ -+ bcm2708_i2s_stop(dev, substream, dai); -+ -+ /* If both streams are stopped, disable module and clock */ -+ if (dai->active) -+ return; -+ -+ /* Disable the module */ -+ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, -+ BCM2708_I2S_EN, 0); -+ -+ /* -+ * Stopping clock is necessary, because stop does -+ * not stop the clock when SND_SOC_DAIFMT_CONT -+ */ -+ bcm2708_i2s_stop_clock(dev); -+} -+ -+static const struct snd_soc_dai_ops bcm2708_i2s_dai_ops = { -+ .startup = bcm2708_i2s_startup, -+ .shutdown = bcm2708_i2s_shutdown, -+ .prepare = bcm2708_i2s_prepare, -+ .trigger = bcm2708_i2s_trigger, -+ .hw_params = bcm2708_i2s_hw_params, -+ .set_fmt = bcm2708_i2s_set_dai_fmt, -+ .set_bclk_ratio = bcm2708_i2s_set_dai_bclk_ratio -+}; -+ -+static int bcm2708_i2s_dai_probe(struct snd_soc_dai *dai) -+{ -+ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); -+ -+ dai->playback_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; -+ dai->capture_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_CAPTURE]; -+ -+ return 0; -+} -+ -+static struct snd_soc_dai_driver bcm2708_i2s_dai = { -+ .name = "bcm2708-i2s", -+ .probe = bcm2708_i2s_dai_probe, -+ .playback = { -+ .channels_min = 2, -+ .channels_max = 2, -+ .rates = SNDRV_PCM_RATE_8000_192000, -+ .formats = SNDRV_PCM_FMTBIT_S16_LE -+ | SNDRV_PCM_FMTBIT_S24_LE -+ | SNDRV_PCM_FMTBIT_S32_LE -+ }, -+ .capture = { -+ .channels_min = 2, -+ .channels_max = 2, -+ .rates = SNDRV_PCM_RATE_8000_192000, -+ .formats = SNDRV_PCM_FMTBIT_S16_LE -+ | SNDRV_PCM_FMTBIT_S24_LE -+ | SNDRV_PCM_FMTBIT_S32_LE -+ }, -+ .ops = &bcm2708_i2s_dai_ops, -+ .symmetric_rates = 1 -+}; -+ -+static bool bcm2708_i2s_volatile_reg(struct device *dev, unsigned int reg) -+{ -+ switch (reg) { -+ case BCM2708_I2S_CS_A_REG: -+ case BCM2708_I2S_FIFO_A_REG: -+ case BCM2708_I2S_INTSTC_A_REG: -+ case BCM2708_I2S_GRAY_REG: -+ return true; -+ default: -+ return false; -+ }; -+} -+ -+static bool bcm2708_i2s_precious_reg(struct device *dev, unsigned int reg) -+{ -+ switch (reg) { -+ case BCM2708_I2S_FIFO_A_REG: -+ return true; -+ default: -+ return false; -+ }; -+} -+ -+static bool bcm2708_clk_volatile_reg(struct device *dev, unsigned int reg) -+{ -+ switch (reg) { -+ case BCM2708_CLK_PCMCTL_REG: -+ return true; -+ default: -+ return false; -+ }; -+} -+ -+static const struct regmap_config bcm2708_regmap_config[] = { -+ { -+ .reg_bits = 32, -+ .reg_stride = 4, -+ .val_bits = 32, -+ .max_register = BCM2708_I2S_GRAY_REG, -+ .precious_reg = bcm2708_i2s_precious_reg, -+ .volatile_reg = bcm2708_i2s_volatile_reg, -+ .cache_type = REGCACHE_RBTREE, -+ .name = "i2s", -+ }, -+ { -+ .reg_bits = 32, -+ .reg_stride = 4, -+ .val_bits = 32, -+ .max_register = BCM2708_CLK_PCMDIV_REG, -+ .volatile_reg = bcm2708_clk_volatile_reg, -+ .cache_type = REGCACHE_RBTREE, -+ .name = "clk", -+ }, -+}; -+ -+static const struct snd_soc_component_driver bcm2708_i2s_component = { -+ .name = "bcm2708-i2s-comp", -+}; -+ -+static struct snd_pcm_hardware bcm2708_pcm_hardware = { -+ .info = SNDRV_PCM_INFO_INTERLEAVED | -+ SNDRV_PCM_INFO_JOINT_DUPLEX, -+ .formats = SNDRV_PCM_FMTBIT_S16_LE | -+ SNDRV_PCM_FMTBIT_S24_LE | -+ SNDRV_PCM_FMTBIT_S32_LE, -+ .period_bytes_min = 32, -+ .period_bytes_max = 64 * PAGE_SIZE, -+ .periods_min = 2, -+ .periods_max = 255, -+ .buffer_bytes_max = 128 * PAGE_SIZE, -+}; -+ -+static const struct snd_dmaengine_pcm_config bcm2708_dmaengine_pcm_config = { -+ .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, -+ .pcm_hardware = &bcm2708_pcm_hardware, -+ .prealloc_buffer_size = 256 * PAGE_SIZE, -+}; -+ -+ -+static int bcm2708_i2s_probe(struct platform_device *pdev) -+{ -+ struct bcm2708_i2s_dev *dev; -+ int i; -+ int ret; -+ struct regmap *regmap[2]; -+ struct resource *mem[2]; -+ -+ if (of_property_read_bool(pdev->dev.of_node, "brcm,enable-mmap")) -+ bcm2708_pcm_hardware.info |= -+ SNDRV_PCM_INFO_MMAP | -+ SNDRV_PCM_INFO_MMAP_VALID; -+ -+ /* Request both ioareas */ -+ for (i = 0; i <= 1; i++) { -+ void __iomem *base; -+ -+ mem[i] = platform_get_resource(pdev, IORESOURCE_MEM, i); -+ base = devm_ioremap_resource(&pdev->dev, mem[i]); -+ if (IS_ERR(base)) -+ return PTR_ERR(base); -+ -+ regmap[i] = devm_regmap_init_mmio(&pdev->dev, base, -+ &bcm2708_regmap_config[i]); -+ if (IS_ERR(regmap[i])) { -+ dev_err(&pdev->dev, "I2S probe: regmap init failed\n"); -+ return PTR_ERR(regmap[i]); -+ } -+ } -+ -+ dev = devm_kzalloc(&pdev->dev, sizeof(*dev), -+ GFP_KERNEL); -+ if (IS_ERR(dev)) -+ return PTR_ERR(dev); -+ -+ dev->i2s_regmap = regmap[0]; -+ dev->clk_regmap = regmap[1]; -+ -+ /* Set the DMA address */ -+ dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr = -+ (dma_addr_t)BCM2708_I2S_FIFO_PHYSICAL_ADDR; -+ -+ dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr = -+ (dma_addr_t)BCM2708_I2S_FIFO_PHYSICAL_ADDR; -+ -+ /* Set the DREQ */ -+ dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].slave_id = -+ BCM2708_DMA_DREQ_PCM_TX; -+ dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].slave_id = -+ BCM2708_DMA_DREQ_PCM_RX; -+ -+ /* Set the bus width */ -+ dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr_width = -+ DMA_SLAVE_BUSWIDTH_4_BYTES; -+ dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr_width = -+ DMA_SLAVE_BUSWIDTH_4_BYTES; -+ -+ /* Set burst */ -+ dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].maxburst = 2; -+ dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].maxburst = 2; -+ -+ /* BCLK ratio - use default */ -+ dev->bclk_ratio = 0; -+ -+ /* Store the pdev */ -+ dev->dev = &pdev->dev; -+ dev_set_drvdata(&pdev->dev, dev); -+ -+ ret = snd_soc_register_component(&pdev->dev, -+ &bcm2708_i2s_component, &bcm2708_i2s_dai, 1); -+ -+ if (ret) { -+ dev_err(&pdev->dev, "Could not register DAI: %d\n", ret); -+ ret = -ENOMEM; -+ return ret; -+ } -+ -+ ret = snd_dmaengine_pcm_register(&pdev->dev, -+ &bcm2708_dmaengine_pcm_config, -+ SND_DMAENGINE_PCM_FLAG_COMPAT); -+ if (ret) { -+ dev_err(&pdev->dev, "Could not register PCM: %d\n", ret); -+ snd_soc_unregister_component(&pdev->dev); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int bcm2708_i2s_remove(struct platform_device *pdev) -+{ -+ snd_dmaengine_pcm_unregister(&pdev->dev); -+ snd_soc_unregister_component(&pdev->dev); -+ return 0; -+} -+ -+static const struct of_device_id bcm2708_i2s_of_match[] = { -+ { .compatible = "brcm,bcm2708-i2s", }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, bcm2708_i2s_of_match); -+ -+static struct platform_driver bcm2708_i2s_driver = { -+ .probe = bcm2708_i2s_probe, -+ .remove = bcm2708_i2s_remove, -+ .driver = { -+ .name = "bcm2708-i2s", -+ .owner = THIS_MODULE, -+ .of_match_table = bcm2708_i2s_of_match, -+ }, -+}; -+ -+module_platform_driver(bcm2708_i2s_driver); -+ -+MODULE_ALIAS("platform:bcm2708-i2s"); -+MODULE_DESCRIPTION("BCM2708 I2S interface"); -+MODULE_AUTHOR("Florian Meier "); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-4.1.13.orig/sound/soc/bcm/bcm2708-i2s.h linux-rpi/sound/soc/bcm/bcm2708-i2s.h ---- linux-4.1.13.orig/sound/soc/bcm/bcm2708-i2s.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/sound/soc/bcm/bcm2708-i2s.h 2015-11-29 09:42:41.558989731 +0100 -@@ -0,0 +1,35 @@ -+/* -+ * I2S configuration for sound cards. -+ * -+ * Copyright (c) 2014 Daniel Matuschek -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ */ -+ -+#ifndef BCM2708_I2S_H -+#define BCM2708_I2S_H -+ -+/* I2S pin assignment */ -+#define BCM2708_I2S_GPIO_AUTO 0 -+#define BCM2708_I2S_GPIO_PIN18 1 -+#define BCM2708_I2S_GPIO_PIN28 2 -+ -+/* Alt mode to enable I2S */ -+#define BCM2708_I2S_GPIO_PIN18_ALT 0 -+#define BCM2708_I2S_GPIO_PIN28_ALT 2 -+ -+extern void bcm2708_i2s_set_gpio(int gpio); -+ -+#endif -diff -Nur linux-4.1.13.orig/sound/soc/bcm/bcm2835-i2s.c linux-rpi/sound/soc/bcm/bcm2835-i2s.c ---- linux-4.1.13.orig/sound/soc/bcm/bcm2835-i2s.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/sound/soc/bcm/bcm2835-i2s.c 2015-11-29 09:42:41.558989731 +0100 -@@ -861,6 +861,7 @@ - { .compatible = "brcm,bcm2835-i2s", }, - {}, - }; -+MODULE_DEVICE_TABLE(of, bcm2835_i2s_of_match); - - static struct platform_driver bcm2835_i2s_driver = { - .probe = bcm2835_i2s_probe, -diff -Nur linux-4.1.13.orig/sound/soc/bcm/hifiberry_amp.c linux-rpi/sound/soc/bcm/hifiberry_amp.c ---- linux-4.1.13.orig/sound/soc/bcm/hifiberry_amp.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/sound/soc/bcm/hifiberry_amp.c 2015-11-29 09:42:41.558989731 +0100 -@@ -0,0 +1,127 @@ -+/* -+ * ASoC Driver for HifiBerry AMP -+ * -+ * Author: Sebastian Eickhoff -+ * Copyright 2014 -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ */ -+ -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+ -+static int snd_rpi_hifiberry_amp_init(struct snd_soc_pcm_runtime *rtd) -+{ -+ // ToDo: init of the dsp-registers. -+ return 0; -+} -+ -+static int snd_rpi_hifiberry_amp_hw_params( struct snd_pcm_substream *substream, -+ struct snd_pcm_hw_params *params ) -+{ -+ struct snd_soc_pcm_runtime *rtd = substream->private_data; -+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai; -+ -+ return snd_soc_dai_set_bclk_ratio(cpu_dai, 64); -+} -+ -+static struct snd_soc_ops snd_rpi_hifiberry_amp_ops = { -+ .hw_params = snd_rpi_hifiberry_amp_hw_params, -+}; -+ -+static struct snd_soc_dai_link snd_rpi_hifiberry_amp_dai[] = { -+ { -+ .name = "HifiBerry AMP", -+ .stream_name = "HifiBerry AMP HiFi", -+ .cpu_dai_name = "bcm2708-i2s.0", -+ .codec_dai_name = "tas5713-hifi", -+ .platform_name = "bcm2708-i2s.0", -+ .codec_name = "tas5713.1-001b", -+ .dai_fmt = SND_SOC_DAIFMT_I2S | -+ SND_SOC_DAIFMT_NB_NF | -+ SND_SOC_DAIFMT_CBS_CFS, -+ .ops = &snd_rpi_hifiberry_amp_ops, -+ .init = snd_rpi_hifiberry_amp_init, -+ }, -+}; -+ -+ -+static struct snd_soc_card snd_rpi_hifiberry_amp = { -+ .name = "snd_rpi_hifiberry_amp", -+ .dai_link = snd_rpi_hifiberry_amp_dai, -+ .num_links = ARRAY_SIZE(snd_rpi_hifiberry_amp_dai), -+}; -+ -+static const struct of_device_id snd_rpi_hifiberry_amp_of_match[] = { -+ { .compatible = "hifiberry,hifiberry-amp", }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_amp_of_match); -+ -+ -+static int snd_rpi_hifiberry_amp_probe(struct platform_device *pdev) -+{ -+ int ret = 0; -+ -+ snd_rpi_hifiberry_amp.dev = &pdev->dev; -+ -+ if (pdev->dev.of_node) { -+ struct device_node *i2s_node; -+ struct snd_soc_dai_link *dai = &snd_rpi_hifiberry_amp_dai[0]; -+ i2s_node = of_parse_phandle(pdev->dev.of_node, -+ "i2s-controller", 0); -+ -+ if (i2s_node) { -+ dai->cpu_dai_name = NULL; -+ dai->cpu_of_node = i2s_node; -+ dai->platform_name = NULL; -+ dai->platform_of_node = i2s_node; -+ } -+ } -+ -+ ret = snd_soc_register_card(&snd_rpi_hifiberry_amp); -+ -+ if (ret != 0) { -+ dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret); -+ } -+ -+ return ret; -+} -+ -+ -+static int snd_rpi_hifiberry_amp_remove(struct platform_device *pdev) -+{ -+ return snd_soc_unregister_card(&snd_rpi_hifiberry_amp); -+} -+ -+ -+static struct platform_driver snd_rpi_hifiberry_amp_driver = { -+ .driver = { -+ .name = "snd-hifiberry-amp", -+ .owner = THIS_MODULE, -+ .of_match_table = snd_rpi_hifiberry_amp_of_match, -+ }, -+ .probe = snd_rpi_hifiberry_amp_probe, -+ .remove = snd_rpi_hifiberry_amp_remove, -+}; -+ -+ -+module_platform_driver(snd_rpi_hifiberry_amp_driver); -+ -+ -+MODULE_AUTHOR("Sebastian Eickhoff "); -+MODULE_DESCRIPTION("ASoC driver for HiFiBerry-AMP"); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-4.1.13.orig/sound/soc/bcm/hifiberry_dac.c linux-rpi/sound/soc/bcm/hifiberry_dac.c ---- linux-4.1.13.orig/sound/soc/bcm/hifiberry_dac.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/sound/soc/bcm/hifiberry_dac.c 2015-11-29 09:42:41.558989731 +0100 -@@ -0,0 +1,122 @@ -+/* -+ * ASoC Driver for HifiBerry DAC -+ * -+ * Author: Florian Meier -+ * Copyright 2013 -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ */ -+ -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+ -+static int snd_rpi_hifiberry_dac_init(struct snd_soc_pcm_runtime *rtd) -+{ -+ return 0; -+} -+ -+static int snd_rpi_hifiberry_dac_hw_params(struct snd_pcm_substream *substream, -+ struct snd_pcm_hw_params *params) -+{ -+ struct snd_soc_pcm_runtime *rtd = substream->private_data; -+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai; -+ -+ unsigned int sample_bits = -+ snd_pcm_format_physical_width(params_format(params)); -+ -+ return snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2); -+} -+ -+/* machine stream operations */ -+static struct snd_soc_ops snd_rpi_hifiberry_dac_ops = { -+ .hw_params = snd_rpi_hifiberry_dac_hw_params, -+}; -+ -+static struct snd_soc_dai_link snd_rpi_hifiberry_dac_dai[] = { -+{ -+ .name = "HifiBerry DAC", -+ .stream_name = "HifiBerry DAC HiFi", -+ .cpu_dai_name = "bcm2708-i2s.0", -+ .codec_dai_name = "pcm5102a-hifi", -+ .platform_name = "bcm2708-i2s.0", -+ .codec_name = "pcm5102a-codec", -+ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | -+ SND_SOC_DAIFMT_CBS_CFS, -+ .ops = &snd_rpi_hifiberry_dac_ops, -+ .init = snd_rpi_hifiberry_dac_init, -+}, -+}; -+ -+/* audio machine driver */ -+static struct snd_soc_card snd_rpi_hifiberry_dac = { -+ .name = "snd_rpi_hifiberry_dac", -+ .dai_link = snd_rpi_hifiberry_dac_dai, -+ .num_links = ARRAY_SIZE(snd_rpi_hifiberry_dac_dai), -+}; -+ -+static int snd_rpi_hifiberry_dac_probe(struct platform_device *pdev) -+{ -+ int ret = 0; -+ -+ snd_rpi_hifiberry_dac.dev = &pdev->dev; -+ -+ if (pdev->dev.of_node) { -+ struct device_node *i2s_node; -+ struct snd_soc_dai_link *dai = &snd_rpi_hifiberry_dac_dai[0]; -+ i2s_node = of_parse_phandle(pdev->dev.of_node, -+ "i2s-controller", 0); -+ -+ if (i2s_node) { -+ dai->cpu_dai_name = NULL; -+ dai->cpu_of_node = i2s_node; -+ dai->platform_name = NULL; -+ dai->platform_of_node = i2s_node; -+ } -+ } -+ -+ ret = snd_soc_register_card(&snd_rpi_hifiberry_dac); -+ if (ret) -+ dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret); -+ -+ return ret; -+} -+ -+static int snd_rpi_hifiberry_dac_remove(struct platform_device *pdev) -+{ -+ return snd_soc_unregister_card(&snd_rpi_hifiberry_dac); -+} -+ -+static const struct of_device_id snd_rpi_hifiberry_dac_of_match[] = { -+ { .compatible = "hifiberry,hifiberry-dac", }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_dac_of_match); -+ -+static struct platform_driver snd_rpi_hifiberry_dac_driver = { -+ .driver = { -+ .name = "snd-hifiberry-dac", -+ .owner = THIS_MODULE, -+ .of_match_table = snd_rpi_hifiberry_dac_of_match, -+ }, -+ .probe = snd_rpi_hifiberry_dac_probe, -+ .remove = snd_rpi_hifiberry_dac_remove, -+}; -+ -+module_platform_driver(snd_rpi_hifiberry_dac_driver); -+ -+MODULE_AUTHOR("Florian Meier "); -+MODULE_DESCRIPTION("ASoC Driver for HifiBerry DAC"); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-4.1.13.orig/sound/soc/bcm/hifiberry_dacplus.c linux-rpi/sound/soc/bcm/hifiberry_dacplus.c ---- linux-4.1.13.orig/sound/soc/bcm/hifiberry_dacplus.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/sound/soc/bcm/hifiberry_dacplus.c 2015-11-29 09:42:41.558989731 +0100 -@@ -0,0 +1,337 @@ -+/* -+ * ASoC Driver for HiFiBerry DAC+ / DAC Pro -+ * -+ * Author: Daniel Matuschek, Stuart MacLean -+ * Copyright 2014-2015 -+ * based on code by Florian Meier -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "../codecs/pcm512x.h" -+ -+#define HIFIBERRY_DACPRO_NOCLOCK 0 -+#define HIFIBERRY_DACPRO_CLK44EN 1 -+#define HIFIBERRY_DACPRO_CLK48EN 2 -+ -+struct pcm512x_priv { -+ struct regmap *regmap; -+ struct clk *sclk; -+}; -+ -+/* Clock rate of CLK44EN attached to GPIO6 pin */ -+#define CLK_44EN_RATE 22579200UL -+/* Clock rate of CLK48EN attached to GPIO3 pin */ -+#define CLK_48EN_RATE 24576000UL -+ -+static bool snd_rpi_hifiberry_is_dacpro; -+ -+static void snd_rpi_hifiberry_dacplus_select_clk(struct snd_soc_codec *codec, -+ int clk_id) -+{ -+ switch (clk_id) { -+ case HIFIBERRY_DACPRO_NOCLOCK: -+ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x24, 0x00); -+ break; -+ case HIFIBERRY_DACPRO_CLK44EN: -+ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x24, 0x20); -+ break; -+ case HIFIBERRY_DACPRO_CLK48EN: -+ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x24, 0x04); -+ break; -+ } -+} -+ -+static void snd_rpi_hifiberry_dacplus_clk_gpio(struct snd_soc_codec *codec) -+{ -+ snd_soc_update_bits(codec, PCM512x_GPIO_EN, 0x24, 0x24); -+ snd_soc_update_bits(codec, PCM512x_GPIO_OUTPUT_3, 0x0f, 0x02); -+ snd_soc_update_bits(codec, PCM512x_GPIO_OUTPUT_6, 0x0f, 0x02); -+} -+ -+static bool snd_rpi_hifiberry_dacplus_is_sclk(struct snd_soc_codec *codec) -+{ -+ int sck; -+ -+ sck = snd_soc_read(codec, PCM512x_RATE_DET_4); -+ return (!(sck & 0x40)); -+} -+ -+static bool snd_rpi_hifiberry_dacplus_is_sclk_sleep( -+ struct snd_soc_codec *codec) -+{ -+ msleep(2); -+ return snd_rpi_hifiberry_dacplus_is_sclk(codec); -+} -+ -+static bool snd_rpi_hifiberry_dacplus_is_pro_card(struct snd_soc_codec *codec) -+{ -+ bool isClk44EN, isClk48En, isNoClk; -+ -+ snd_rpi_hifiberry_dacplus_clk_gpio(codec); -+ -+ snd_rpi_hifiberry_dacplus_select_clk(codec, HIFIBERRY_DACPRO_CLK44EN); -+ isClk44EN = snd_rpi_hifiberry_dacplus_is_sclk_sleep(codec); -+ -+ snd_rpi_hifiberry_dacplus_select_clk(codec, HIFIBERRY_DACPRO_NOCLOCK); -+ isNoClk = snd_rpi_hifiberry_dacplus_is_sclk_sleep(codec); -+ -+ snd_rpi_hifiberry_dacplus_select_clk(codec, HIFIBERRY_DACPRO_CLK48EN); -+ isClk48En = snd_rpi_hifiberry_dacplus_is_sclk_sleep(codec); -+ -+ return (isClk44EN && isClk48En && !isNoClk); -+} -+ -+static int snd_rpi_hifiberry_dacplus_clk_for_rate(int sample_rate) -+{ -+ int type; -+ -+ switch (sample_rate) { -+ case 11025: -+ case 22050: -+ case 44100: -+ case 88200: -+ case 176400: -+ type = HIFIBERRY_DACPRO_CLK44EN; -+ break; -+ default: -+ type = HIFIBERRY_DACPRO_CLK48EN; -+ break; -+ } -+ return type; -+} -+ -+static void snd_rpi_hifiberry_dacplus_set_sclk(struct snd_soc_codec *codec, -+ int sample_rate) -+{ -+ struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); -+ -+ if (!IS_ERR(pcm512x->sclk)) { -+ int ctype; -+ -+ ctype = snd_rpi_hifiberry_dacplus_clk_for_rate(sample_rate); -+ clk_set_rate(pcm512x->sclk, (ctype == HIFIBERRY_DACPRO_CLK44EN) -+ ? CLK_44EN_RATE : CLK_48EN_RATE); -+ snd_rpi_hifiberry_dacplus_select_clk(codec, ctype); -+ } -+} -+ -+static int snd_rpi_hifiberry_dacplus_init(struct snd_soc_pcm_runtime *rtd) -+{ -+ struct snd_soc_codec *codec = rtd->codec; -+ struct pcm512x_priv *priv; -+ -+ snd_rpi_hifiberry_is_dacpro -+ = snd_rpi_hifiberry_dacplus_is_pro_card(codec); -+ -+ if (snd_rpi_hifiberry_is_dacpro) { -+ struct snd_soc_dai_link *dai = rtd->dai_link; -+ -+ dai->name = "HiFiBerry DAC+ Pro"; -+ dai->stream_name = "HiFiBerry DAC+ Pro HiFi"; -+ dai->dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF -+ | SND_SOC_DAIFMT_CBM_CFM; -+ -+ snd_soc_update_bits(codec, PCM512x_BCLK_LRCLK_CFG, 0x31, 0x11); -+ snd_soc_update_bits(codec, PCM512x_MASTER_MODE, 0x03, 0x03); -+ snd_soc_update_bits(codec, PCM512x_MASTER_CLKDIV_2, 0x7f, 63); -+ } else { -+ priv = snd_soc_codec_get_drvdata(codec); -+ priv->sclk = ERR_PTR(-ENOENT); -+ } -+ -+ snd_soc_update_bits(codec, PCM512x_GPIO_EN, 0x08, 0x08); -+ snd_soc_update_bits(codec, PCM512x_GPIO_OUTPUT_4, 0x0f, 0x02); -+ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08, 0x08); -+ -+ return 0; -+} -+ -+static int snd_rpi_hifiberry_dacplus_update_rate_den( -+ struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) -+{ -+ struct snd_soc_pcm_runtime *rtd = substream->private_data; -+ struct snd_soc_codec *codec = rtd->codec; -+ struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); -+ struct snd_ratnum *rats_no_pll; -+ unsigned int num = 0, den = 0; -+ int err; -+ -+ rats_no_pll = devm_kzalloc(rtd->dev, sizeof(*rats_no_pll), GFP_KERNEL); -+ if (!rats_no_pll) -+ return -ENOMEM; -+ -+ rats_no_pll->num = clk_get_rate(pcm512x->sclk) / 64; -+ rats_no_pll->den_min = 1; -+ rats_no_pll->den_max = 128; -+ rats_no_pll->den_step = 1; -+ -+ err = snd_interval_ratnum(hw_param_interval(params, -+ SNDRV_PCM_HW_PARAM_RATE), 1, rats_no_pll, &num, &den); -+ if (err >= 0 && den) { -+ params->rate_num = num; -+ params->rate_den = den; -+ } -+ -+ devm_kfree(rtd->dev, rats_no_pll); -+ return 0; -+} -+ -+static int snd_rpi_hifiberry_dacplus_set_bclk_ratio_pro( -+ struct snd_soc_dai *cpu_dai, struct snd_pcm_hw_params *params) -+{ -+ int bratio = snd_pcm_format_physical_width(params_format(params)) -+ * params_channels(params); -+ return snd_soc_dai_set_bclk_ratio(cpu_dai, bratio); -+} -+ -+static int snd_rpi_hifiberry_dacplus_hw_params( -+ struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) -+{ -+ int ret; -+ struct snd_soc_pcm_runtime *rtd = substream->private_data; -+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai; -+ -+ if (snd_rpi_hifiberry_is_dacpro) { -+ struct snd_soc_codec *codec = rtd->codec; -+ -+ snd_rpi_hifiberry_dacplus_set_sclk(codec, -+ params_rate(params)); -+ -+ ret = snd_rpi_hifiberry_dacplus_set_bclk_ratio_pro(cpu_dai, -+ params); -+ if (!ret) -+ ret = snd_rpi_hifiberry_dacplus_update_rate_den( -+ substream, params); -+ } else { -+ ret = snd_soc_dai_set_bclk_ratio(cpu_dai, 64); -+ } -+ return ret; -+} -+ -+static int snd_rpi_hifiberry_dacplus_startup( -+ struct snd_pcm_substream *substream) -+{ -+ struct snd_soc_pcm_runtime *rtd = substream->private_data; -+ struct snd_soc_codec *codec = rtd->codec; -+ -+ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08, 0x08); -+ return 0; -+} -+ -+static void snd_rpi_hifiberry_dacplus_shutdown( -+ struct snd_pcm_substream *substream) -+{ -+ struct snd_soc_pcm_runtime *rtd = substream->private_data; -+ struct snd_soc_codec *codec = rtd->codec; -+ -+ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08, 0x00); -+} -+ -+/* machine stream operations */ -+static struct snd_soc_ops snd_rpi_hifiberry_dacplus_ops = { -+ .hw_params = snd_rpi_hifiberry_dacplus_hw_params, -+ .startup = snd_rpi_hifiberry_dacplus_startup, -+ .shutdown = snd_rpi_hifiberry_dacplus_shutdown, -+}; -+ -+static struct snd_soc_dai_link snd_rpi_hifiberry_dacplus_dai[] = { -+{ -+ .name = "HiFiBerry DAC+", -+ .stream_name = "HiFiBerry DAC+ HiFi", -+ .cpu_dai_name = "bcm2708-i2s.0", -+ .codec_dai_name = "pcm512x-hifi", -+ .platform_name = "bcm2708-i2s.0", -+ .codec_name = "pcm512x.1-004d", -+ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | -+ SND_SOC_DAIFMT_CBS_CFS, -+ .ops = &snd_rpi_hifiberry_dacplus_ops, -+ .init = snd_rpi_hifiberry_dacplus_init, -+}, -+}; -+ -+/* audio machine driver */ -+static struct snd_soc_card snd_rpi_hifiberry_dacplus = { -+ .name = "snd_rpi_hifiberry_dacplus", -+ .dai_link = snd_rpi_hifiberry_dacplus_dai, -+ .num_links = ARRAY_SIZE(snd_rpi_hifiberry_dacplus_dai), -+}; -+ -+static int snd_rpi_hifiberry_dacplus_probe(struct platform_device *pdev) -+{ -+ int ret = 0; -+ -+ snd_rpi_hifiberry_dacplus.dev = &pdev->dev; -+ if (pdev->dev.of_node) { -+ struct device_node *i2s_node; -+ struct snd_soc_dai_link *dai; -+ -+ dai = &snd_rpi_hifiberry_dacplus_dai[0]; -+ i2s_node = of_parse_phandle(pdev->dev.of_node, -+ "i2s-controller", 0); -+ -+ if (i2s_node) { -+ dai->cpu_dai_name = NULL; -+ dai->cpu_of_node = i2s_node; -+ dai->platform_name = NULL; -+ dai->platform_of_node = i2s_node; -+ } -+ } -+ -+ ret = snd_soc_register_card(&snd_rpi_hifiberry_dacplus); -+ if (ret) -+ dev_err(&pdev->dev, -+ "snd_soc_register_card() failed: %d\n", ret); -+ -+ return ret; -+} -+ -+static int snd_rpi_hifiberry_dacplus_remove(struct platform_device *pdev) -+{ -+ return snd_soc_unregister_card(&snd_rpi_hifiberry_dacplus); -+} -+ -+static const struct of_device_id snd_rpi_hifiberry_dacplus_of_match[] = { -+ { .compatible = "hifiberry,hifiberry-dacplus", }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_dacplus_of_match); -+ -+static struct platform_driver snd_rpi_hifiberry_dacplus_driver = { -+ .driver = { -+ .name = "snd-rpi-hifiberry-dacplus", -+ .owner = THIS_MODULE, -+ .of_match_table = snd_rpi_hifiberry_dacplus_of_match, -+ }, -+ .probe = snd_rpi_hifiberry_dacplus_probe, -+ .remove = snd_rpi_hifiberry_dacplus_remove, -+}; -+ -+module_platform_driver(snd_rpi_hifiberry_dacplus_driver); -+ -+MODULE_AUTHOR("Daniel Matuschek "); -+MODULE_DESCRIPTION("ASoC Driver for HiFiBerry DAC+"); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-4.1.13.orig/sound/soc/bcm/hifiberry_digi.c linux-rpi/sound/soc/bcm/hifiberry_digi.c ---- linux-4.1.13.orig/sound/soc/bcm/hifiberry_digi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/sound/soc/bcm/hifiberry_digi.c 2015-11-29 09:42:41.558989731 +0100 -@@ -0,0 +1,223 @@ -+/* -+ * ASoC Driver for HifiBerry Digi -+ * -+ * Author: Daniel Matuschek -+ * based on the HifiBerry DAC driver by Florian Meier -+ * Copyright 2013 -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ */ -+ -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "../codecs/wm8804.h" -+ -+static short int auto_shutdown_output = 0; -+module_param(auto_shutdown_output, short, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP); -+MODULE_PARM_DESC(auto_shutdown_output, "Shutdown SP/DIF output if playback is stopped"); -+ -+ -+static int samplerate=44100; -+ -+static int snd_rpi_hifiberry_digi_init(struct snd_soc_pcm_runtime *rtd) -+{ -+ struct snd_soc_codec *codec = rtd->codec; -+ -+ /* enable TX output */ -+ snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, 0x0); -+ -+ return 0; -+} -+ -+static int snd_rpi_hifiberry_digi_startup(struct snd_pcm_substream *substream) { -+ /* turn on digital output */ -+ struct snd_soc_pcm_runtime *rtd = substream->private_data; -+ struct snd_soc_codec *codec = rtd->codec; -+ snd_soc_update_bits(codec, WM8804_PWRDN, 0x3c, 0x00); -+ return 0; -+} -+ -+static void snd_rpi_hifiberry_digi_shutdown(struct snd_pcm_substream *substream) { -+ /* turn off output */ -+ if (auto_shutdown_output) { -+ /* turn off output */ -+ struct snd_soc_pcm_runtime *rtd = substream->private_data; -+ struct snd_soc_codec *codec = rtd->codec; -+ snd_soc_update_bits(codec, WM8804_PWRDN, 0x3c, 0x3c); -+ } -+} -+ -+ -+static int snd_rpi_hifiberry_digi_hw_params(struct snd_pcm_substream *substream, -+ struct snd_pcm_hw_params *params) -+{ -+ struct snd_soc_pcm_runtime *rtd = substream->private_data; -+ struct snd_soc_dai *codec_dai = rtd->codec_dai; -+ struct snd_soc_codec *codec = rtd->codec; -+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai; -+ -+ int sysclk = 27000000; /* This is fixed on this board */ -+ -+ long mclk_freq=0; -+ int mclk_div=1; -+ int sampling_freq=1; -+ -+ int ret; -+ -+ samplerate = params_rate(params); -+ -+ if (samplerate<=96000) { -+ mclk_freq=samplerate*256; -+ mclk_div=WM8804_MCLKDIV_256FS; -+ } else { -+ mclk_freq=samplerate*128; -+ mclk_div=WM8804_MCLKDIV_128FS; -+ } -+ -+ switch (samplerate) { -+ case 32000: -+ sampling_freq=0x03; -+ break; -+ case 44100: -+ sampling_freq=0x00; -+ break; -+ case 48000: -+ sampling_freq=0x02; -+ break; -+ case 88200: -+ sampling_freq=0x08; -+ break; -+ case 96000: -+ sampling_freq=0x0a; -+ break; -+ case 176400: -+ sampling_freq=0x0c; -+ break; -+ case 192000: -+ sampling_freq=0x0e; -+ break; -+ default: -+ dev_err(codec->dev, -+ "Failed to set WM8804 SYSCLK, unsupported samplerate %d\n", -+ samplerate); -+ } -+ -+ snd_soc_dai_set_clkdiv(codec_dai, WM8804_MCLK_DIV, mclk_div); -+ snd_soc_dai_set_pll(codec_dai, 0, 0, sysclk, mclk_freq); -+ -+ ret = snd_soc_dai_set_sysclk(codec_dai, WM8804_TX_CLKSRC_PLL, -+ sysclk, SND_SOC_CLOCK_OUT); -+ if (ret < 0) { -+ dev_err(codec->dev, -+ "Failed to set WM8804 SYSCLK: %d\n", ret); -+ return ret; -+ } -+ -+ /* Enable TX output */ -+ snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, 0x0); -+ -+ /* Power on */ -+ snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0); -+ -+ /* set sampling frequency status bits */ -+ snd_soc_update_bits(codec, WM8804_SPDTX4, 0x0f, sampling_freq); -+ -+ return snd_soc_dai_set_bclk_ratio(cpu_dai,64); -+} -+ -+/* machine stream operations */ -+static struct snd_soc_ops snd_rpi_hifiberry_digi_ops = { -+ .hw_params = snd_rpi_hifiberry_digi_hw_params, -+ .startup = snd_rpi_hifiberry_digi_startup, -+ .shutdown = snd_rpi_hifiberry_digi_shutdown, -+}; -+ -+static struct snd_soc_dai_link snd_rpi_hifiberry_digi_dai[] = { -+{ -+ .name = "HifiBerry Digi", -+ .stream_name = "HifiBerry Digi HiFi", -+ .cpu_dai_name = "bcm2708-i2s.0", -+ .codec_dai_name = "wm8804-spdif", -+ .platform_name = "bcm2708-i2s.0", -+ .codec_name = "wm8804.1-003b", -+ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | -+ SND_SOC_DAIFMT_CBM_CFM, -+ .ops = &snd_rpi_hifiberry_digi_ops, -+ .init = snd_rpi_hifiberry_digi_init, -+}, -+}; -+ -+/* audio machine driver */ -+static struct snd_soc_card snd_rpi_hifiberry_digi = { -+ .name = "snd_rpi_hifiberry_digi", -+ .dai_link = snd_rpi_hifiberry_digi_dai, -+ .num_links = ARRAY_SIZE(snd_rpi_hifiberry_digi_dai), -+}; -+ -+static int snd_rpi_hifiberry_digi_probe(struct platform_device *pdev) -+{ -+ int ret = 0; -+ -+ snd_rpi_hifiberry_digi.dev = &pdev->dev; -+ -+ if (pdev->dev.of_node) { -+ struct device_node *i2s_node; -+ struct snd_soc_dai_link *dai = &snd_rpi_hifiberry_digi_dai[0]; -+ i2s_node = of_parse_phandle(pdev->dev.of_node, -+ "i2s-controller", 0); -+ -+ if (i2s_node) { -+ dai->cpu_dai_name = NULL; -+ dai->cpu_of_node = i2s_node; -+ dai->platform_name = NULL; -+ dai->platform_of_node = i2s_node; -+ } -+ } -+ -+ ret = snd_soc_register_card(&snd_rpi_hifiberry_digi); -+ if (ret) -+ dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret); -+ -+ return ret; -+} -+ -+static int snd_rpi_hifiberry_digi_remove(struct platform_device *pdev) -+{ -+ return snd_soc_unregister_card(&snd_rpi_hifiberry_digi); -+} -+ -+static const struct of_device_id snd_rpi_hifiberry_digi_of_match[] = { -+ { .compatible = "hifiberry,hifiberry-digi", }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_digi_of_match); -+ -+static struct platform_driver snd_rpi_hifiberry_digi_driver = { -+ .driver = { -+ .name = "snd-hifiberry-digi", -+ .owner = THIS_MODULE, -+ .of_match_table = snd_rpi_hifiberry_digi_of_match, -+ }, -+ .probe = snd_rpi_hifiberry_digi_probe, -+ .remove = snd_rpi_hifiberry_digi_remove, -+}; -+ -+module_platform_driver(snd_rpi_hifiberry_digi_driver); -+ -+MODULE_AUTHOR("Daniel Matuschek "); -+MODULE_DESCRIPTION("ASoC Driver for HifiBerry Digi"); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-4.1.13.orig/sound/soc/bcm/iqaudio-dac.c linux-rpi/sound/soc/bcm/iqaudio-dac.c ---- linux-4.1.13.orig/sound/soc/bcm/iqaudio-dac.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/sound/soc/bcm/iqaudio-dac.c 2015-11-29 09:42:41.558989731 +0100 -@@ -0,0 +1,133 @@ -+/* -+ * ASoC Driver for IQaudIO DAC -+ * -+ * Author: Florian Meier -+ * Copyright 2013 -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ */ -+ -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+ -+static int snd_rpi_iqaudio_dac_init(struct snd_soc_pcm_runtime *rtd) -+{ -+ int ret; -+ struct snd_soc_card *card = rtd->card; -+ struct snd_soc_codec *codec = rtd->codec; -+ -+ ret = snd_soc_limit_volume(codec, "Digital Playback Volume", 207); -+ if (ret < 0) -+ dev_warn(card->dev, "Failed to set volume limit: %d\n", ret); -+ -+ return 0; -+} -+ -+static int snd_rpi_iqaudio_dac_hw_params(struct snd_pcm_substream *substream, -+ struct snd_pcm_hw_params *params) -+{ -+ struct snd_soc_pcm_runtime *rtd = substream->private_data; -+// NOT USED struct snd_soc_dai *codec_dai = rtd->codec_dai; -+// NOT USED struct snd_soc_codec *codec = rtd->codec; -+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai; -+ -+ unsigned int sample_bits = -+ snd_pcm_format_physical_width(params_format(params)); -+ -+ return snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2); -+} -+ -+/* machine stream operations */ -+static struct snd_soc_ops snd_rpi_iqaudio_dac_ops = { -+ .hw_params = snd_rpi_iqaudio_dac_hw_params, -+}; -+ -+static struct snd_soc_dai_link snd_rpi_iqaudio_dac_dai[] = { -+{ -+ .name = "IQaudIO DAC", -+ .stream_name = "IQaudIO DAC HiFi", -+ .cpu_dai_name = "bcm2708-i2s.0", -+ .codec_dai_name = "pcm512x-hifi", -+ .platform_name = "bcm2708-i2s.0", -+ .codec_name = "pcm512x.1-004c", -+ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | -+ SND_SOC_DAIFMT_CBS_CFS, -+ .ops = &snd_rpi_iqaudio_dac_ops, -+ .init = snd_rpi_iqaudio_dac_init, -+}, -+}; -+ -+/* audio machine driver */ -+static struct snd_soc_card snd_rpi_iqaudio_dac = { -+ .name = "IQaudIODAC", -+ .dai_link = snd_rpi_iqaudio_dac_dai, -+ .num_links = ARRAY_SIZE(snd_rpi_iqaudio_dac_dai), -+}; -+ -+static int snd_rpi_iqaudio_dac_probe(struct platform_device *pdev) -+{ -+ int ret = 0; -+ -+ snd_rpi_iqaudio_dac.dev = &pdev->dev; -+ -+ if (pdev->dev.of_node) { -+ struct device_node *i2s_node; -+ struct snd_soc_dai_link *dai = &snd_rpi_iqaudio_dac_dai[0]; -+ i2s_node = of_parse_phandle(pdev->dev.of_node, -+ "i2s-controller", 0); -+ -+ if (i2s_node) { -+ dai->cpu_dai_name = NULL; -+ dai->cpu_of_node = i2s_node; -+ dai->platform_name = NULL; -+ dai->platform_of_node = i2s_node; -+ } -+ } -+ -+ ret = snd_soc_register_card(&snd_rpi_iqaudio_dac); -+ if (ret) -+ dev_err(&pdev->dev, -+ "snd_soc_register_card() failed: %d\n", ret); -+ -+ return ret; -+} -+ -+static int snd_rpi_iqaudio_dac_remove(struct platform_device *pdev) -+{ -+ return snd_soc_unregister_card(&snd_rpi_iqaudio_dac); -+} -+ -+static const struct of_device_id iqaudio_of_match[] = { -+ { .compatible = "iqaudio,iqaudio-dac", }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, iqaudio_of_match); -+ -+static struct platform_driver snd_rpi_iqaudio_dac_driver = { -+ .driver = { -+ .name = "snd-rpi-iqaudio-dac", -+ .owner = THIS_MODULE, -+ .of_match_table = iqaudio_of_match, -+ }, -+ .probe = snd_rpi_iqaudio_dac_probe, -+ .remove = snd_rpi_iqaudio_dac_remove, -+}; -+ -+module_platform_driver(snd_rpi_iqaudio_dac_driver); -+ -+MODULE_AUTHOR("Florian Meier "); -+MODULE_DESCRIPTION("ASoC Driver for IQAudio DAC"); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-4.1.13.orig/sound/soc/bcm/Kconfig linux-rpi/sound/soc/bcm/Kconfig ---- linux-4.1.13.orig/sound/soc/bcm/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/sound/soc/bcm/Kconfig 2015-11-29 09:42:41.558989731 +0100 -@@ -7,3 +7,71 @@ - Say Y or M if you want to add support for codecs attached to - the BCM2835 I2S interface. You will also need - to select the audio interfaces to support below. -+ -+config SND_BCM2708_SOC_I2S -+ tristate "SoC Audio support for the Broadcom BCM2708 I2S module" -+ depends on MACH_BCM2708 || MACH_BCM2709 -+ select REGMAP_MMIO -+ select SND_SOC_DMAENGINE_PCM -+ select SND_SOC_GENERIC_DMAENGINE_PCM -+ help -+ Say Y or M if you want to add support for codecs attached to -+ the BCM2708 I2S interface. You will also need -+ to select the audio interfaces to support below. -+ -+config SND_BCM2708_SOC_HIFIBERRY_DAC -+ tristate "Support for HifiBerry DAC" -+ depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S -+ select SND_SOC_PCM5102A -+ help -+ Say Y or M if you want to add support for HifiBerry DAC. -+ -+config SND_BCM2708_SOC_HIFIBERRY_DACPLUS -+ tristate "Support for HifiBerry DAC+" -+ depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S -+ select SND_SOC_PCM512x -+ help -+ Say Y or M if you want to add support for HifiBerry DAC+. -+ -+config SND_BCM2708_SOC_HIFIBERRY_DIGI -+ tristate "Support for HifiBerry Digi" -+ depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S -+ select SND_SOC_WM8804 -+ help -+ Say Y or M if you want to add support for HifiBerry Digi S/PDIF output board. -+ -+config SND_BCM2708_SOC_HIFIBERRY_AMP -+ tristate "Support for the HifiBerry Amp" -+ depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S -+ select SND_SOC_TAS5713 -+ help -+ Say Y or M if you want to add support for the HifiBerry Amp amplifier board. -+ -+config SND_BCM2708_SOC_RPI_DAC -+ tristate "Support for RPi-DAC" -+ depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S -+ select SND_SOC_PCM1794A -+ help -+ Say Y or M if you want to add support for RPi-DAC. -+ -+config SND_BCM2708_SOC_RPI_PROTO -+ tristate "Support for Rpi-PROTO" -+ depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S -+ select SND_SOC_WM8731 -+ help -+ Say Y or M if you want to add support for Audio Codec Board PROTO (WM8731). -+ -+config SND_BCM2708_SOC_IQAUDIO_DAC -+ tristate "Support for IQaudIO-DAC" -+ depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S -+ select SND_SOC_PCM512x_I2C -+ help -+ Say Y or M if you want to add support for IQaudIO-DAC. -+ -+config SND_BCM2708_SOC_RASPIDAC3 -+ tristate "Support for RaspiDAC Rev.3x" -+ depends on SND_BCM2708_SOC_I2S -+ select SND_SOC_PCM512x_I2C -+ select SND_SOC_TPA6130A2 -+ help -+ Say Y or M if you want to add support for RaspiDAC Rev.3x. -diff -Nur linux-4.1.13.orig/sound/soc/bcm/Makefile linux-rpi/sound/soc/bcm/Makefile ---- linux-4.1.13.orig/sound/soc/bcm/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/sound/soc/bcm/Makefile 2015-11-29 09:42:41.558989731 +0100 -@@ -3,3 +3,26 @@ - - obj-$(CONFIG_SND_BCM2835_SOC_I2S) += snd-soc-bcm2835-i2s.o - -+# BCM2708 Platform Support -+snd-soc-bcm2708-i2s-objs := bcm2708-i2s.o -+ -+obj-$(CONFIG_SND_BCM2708_SOC_I2S) += snd-soc-bcm2708-i2s.o -+ -+# BCM2708 Machine Support -+snd-soc-hifiberry-dac-objs := hifiberry_dac.o -+snd-soc-hifiberry-dacplus-objs := hifiberry_dacplus.o -+snd-soc-hifiberry-digi-objs := hifiberry_digi.o -+snd-soc-hifiberry-amp-objs := hifiberry_amp.o -+snd-soc-rpi-dac-objs := rpi-dac.o -+snd-soc-rpi-proto-objs := rpi-proto.o -+snd-soc-iqaudio-dac-objs := iqaudio-dac.o -+snd-soc-raspidac3-objs := raspidac3.o -+ -+obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) += snd-soc-hifiberry-dac.o -+obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) += snd-soc-hifiberry-dacplus.o -+obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) += snd-soc-hifiberry-digi.o -+obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) += snd-soc-hifiberry-amp.o -+obj-$(CONFIG_SND_BCM2708_SOC_RPI_DAC) += snd-soc-rpi-dac.o -+obj-$(CONFIG_SND_BCM2708_SOC_RPI_PROTO) += snd-soc-rpi-proto.o -+obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) += snd-soc-iqaudio-dac.o -+obj-$(CONFIG_SND_BCM2708_SOC_RASPIDAC3) += snd-soc-raspidac3.o -diff -Nur linux-4.1.13.orig/sound/soc/bcm/raspidac3.c linux-rpi/sound/soc/bcm/raspidac3.c ---- linux-4.1.13.orig/sound/soc/bcm/raspidac3.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/sound/soc/bcm/raspidac3.c 2015-11-29 09:42:41.558989731 +0100 -@@ -0,0 +1,191 @@ -+/* -+ * ASoC Driver for RaspiDAC v3 -+ * -+ * Author: Jan Grulich -+ * Copyright 2015 -+ * based on code by Daniel Matuschek -+ * based on code by Florian Meier -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ */ -+ -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "../codecs/pcm512x.h" -+#include "../codecs/tpa6130a2.h" -+ -+/* sound card init */ -+static int snd_rpi_raspidac3_init(struct snd_soc_pcm_runtime *rtd) -+{ -+ int ret; -+ struct snd_soc_card *card = rtd->card; -+ struct snd_soc_codec *codec = rtd->codec; -+ snd_soc_update_bits(codec, PCM512x_GPIO_EN, 0x08, 0x08); -+ snd_soc_update_bits(codec, PCM512x_GPIO_OUTPUT_4, 0xf, 0x02); -+ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x00); -+ -+ ret = snd_soc_limit_volume(codec, "Digital Playback Volume", 207); -+ if (ret < 0) -+ dev_warn(card->dev, "Failed to set volume limit: %d\n", ret); -+ else { -+ struct snd_kcontrol *kctl; -+ -+ ret = tpa6130a2_add_controls(codec); -+ if (ret < 0) -+ dev_warn(card->dev, "Failed to add TPA6130A2 controls: %d\n", -+ ret); -+ ret = snd_soc_limit_volume(codec, -+ "TPA6130A2 Headphone Playback Volume", -+ 54); -+ if (ret < 0) -+ dev_warn(card->dev, "Failed to set TPA6130A2 volume limit: %d\n", -+ ret); -+ kctl = snd_soc_card_get_kcontrol(card, -+ "TPA6130A2 Headphone Playback Volume"); -+ if (kctl) { -+ strcpy(kctl->id.name, "Headphones Playback Volume"); -+ /* disable the volume dB scale so alsamixer works */ -+ kctl->vd[0].access = SNDRV_CTL_ELEM_ACCESS_READWRITE; -+ } -+ -+ kctl = snd_soc_card_get_kcontrol(card, -+ "TPA6130A2 Headphone Playback Switch"); -+ if (kctl) -+ strcpy(kctl->id.name, "Headphones Playback Switch"); -+ } -+ -+ return 0; -+} -+ -+/* set hw parameters */ -+static int snd_rpi_raspidac3_hw_params(struct snd_pcm_substream *substream, -+ struct snd_pcm_hw_params *params) -+{ -+ struct snd_soc_pcm_runtime *rtd = substream->private_data; -+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai; -+ -+ unsigned int sample_bits = -+ snd_pcm_format_physical_width(params_format(params)); -+ -+ return snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2); -+} -+ -+/* startup */ -+static int snd_rpi_raspidac3_startup(struct snd_pcm_substream *substream) { -+ struct snd_soc_pcm_runtime *rtd = substream->private_data; -+ struct snd_soc_codec *codec = rtd->codec; -+ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x08); -+ tpa6130a2_stereo_enable(codec, 1); -+ return 0; -+} -+ -+/* shutdown */ -+static void snd_rpi_raspidac3_shutdown(struct snd_pcm_substream *substream) { -+ struct snd_soc_pcm_runtime *rtd = substream->private_data; -+ struct snd_soc_codec *codec = rtd->codec; -+ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x00); -+ tpa6130a2_stereo_enable(codec, 0); -+} -+ -+/* machine stream operations */ -+static struct snd_soc_ops snd_rpi_raspidac3_ops = { -+ .hw_params = snd_rpi_raspidac3_hw_params, -+ .startup = snd_rpi_raspidac3_startup, -+ .shutdown = snd_rpi_raspidac3_shutdown, -+}; -+ -+/* interface setup */ -+static struct snd_soc_dai_link snd_rpi_raspidac3_dai[] = { -+{ -+ .name = "RaspiDAC Rev.3x", -+ .stream_name = "RaspiDAC HiFi", -+ .cpu_dai_name = "bcm2708-i2s.0", -+ .codec_dai_name = "pcm512x-hifi", -+ .platform_name = "bcm2708-i2s.0", -+ .codec_name = "pcm512x.1-004c", -+ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | -+ SND_SOC_DAIFMT_CBS_CFS, -+ .ops = &snd_rpi_raspidac3_ops, -+ .init = snd_rpi_raspidac3_init, -+}, -+}; -+ -+/* audio machine driver */ -+static struct snd_soc_card snd_rpi_raspidac3 = { -+ .name = "RaspiDAC Rev.3x HiFi Audio Card", -+ .dai_link = snd_rpi_raspidac3_dai, -+ .num_links = ARRAY_SIZE(snd_rpi_raspidac3_dai), -+}; -+ -+/* sound card test */ -+static int snd_rpi_raspidac3_probe(struct platform_device *pdev) -+{ -+ int ret = 0; -+ -+ snd_rpi_raspidac3.dev = &pdev->dev; -+ -+ if (pdev->dev.of_node) { -+ struct device_node *i2s_node; -+ struct snd_soc_dai_link *dai = &snd_rpi_raspidac3_dai[0]; -+ i2s_node = of_parse_phandle(pdev->dev.of_node, -+ "i2s-controller", 0); -+ -+ if (i2s_node) { -+ dai->cpu_dai_name = NULL; -+ dai->cpu_of_node = i2s_node; -+ dai->platform_name = NULL; -+ dai->platform_of_node = i2s_node; -+ } -+ } -+ -+ ret = snd_soc_register_card(&snd_rpi_raspidac3); -+ if (ret) -+ dev_err(&pdev->dev, -+ "snd_soc_register_card() failed: %d\n", ret); -+ -+ return ret; -+} -+ -+/* sound card disconnect */ -+static int snd_rpi_raspidac3_remove(struct platform_device *pdev) -+{ -+ return snd_soc_unregister_card(&snd_rpi_raspidac3); -+} -+ -+static const struct of_device_id raspidac3_of_match[] = { -+ { .compatible = "jg,raspidacv3", }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, raspidac3_of_match); -+ -+/* sound card platform driver */ -+static struct platform_driver snd_rpi_raspidac3_driver = { -+ .driver = { -+ .name = "snd-rpi-raspidac3", -+ .owner = THIS_MODULE, -+ .of_match_table = raspidac3_of_match, -+ }, -+ .probe = snd_rpi_raspidac3_probe, -+ .remove = snd_rpi_raspidac3_remove, -+}; -+ -+module_platform_driver(snd_rpi_raspidac3_driver); -+ -+MODULE_AUTHOR("Jan Grulich "); -+MODULE_DESCRIPTION("ASoC Driver for RaspiDAC Rev.3x"); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-4.1.13.orig/sound/soc/bcm/rpi-dac.c linux-rpi/sound/soc/bcm/rpi-dac.c ---- linux-4.1.13.orig/sound/soc/bcm/rpi-dac.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/sound/soc/bcm/rpi-dac.c 2015-11-29 09:42:41.558989731 +0100 -@@ -0,0 +1,118 @@ -+/* -+ * ASoC Driver for RPi-DAC. -+ * -+ * Author: Florian Meier -+ * Copyright 2013 -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ */ -+ -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+ -+static int snd_rpi_rpi_dac_init(struct snd_soc_pcm_runtime *rtd) -+{ -+ return 0; -+} -+ -+static int snd_rpi_rpi_dac_hw_params(struct snd_pcm_substream *substream, -+ struct snd_pcm_hw_params *params) -+{ -+ struct snd_soc_pcm_runtime *rtd = substream->private_data; -+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai; -+ -+ return snd_soc_dai_set_bclk_ratio(cpu_dai, 32*2); -+} -+ -+/* machine stream operations */ -+static struct snd_soc_ops snd_rpi_rpi_dac_ops = { -+ .hw_params = snd_rpi_rpi_dac_hw_params, -+}; -+ -+static struct snd_soc_dai_link snd_rpi_rpi_dac_dai[] = { -+{ -+ .name = "RPi-DAC", -+ .stream_name = "RPi-DAC HiFi", -+ .cpu_dai_name = "bcm2708-i2s.0", -+ .codec_dai_name = "pcm1794a-hifi", -+ .platform_name = "bcm2708-i2s.0", -+ .codec_name = "pcm1794a-codec", -+ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | -+ SND_SOC_DAIFMT_CBS_CFS, -+ .ops = &snd_rpi_rpi_dac_ops, -+ .init = snd_rpi_rpi_dac_init, -+}, -+}; -+ -+/* audio machine driver */ -+static struct snd_soc_card snd_rpi_rpi_dac = { -+ .name = "snd_rpi_rpi_dac", -+ .dai_link = snd_rpi_rpi_dac_dai, -+ .num_links = ARRAY_SIZE(snd_rpi_rpi_dac_dai), -+}; -+ -+static int snd_rpi_rpi_dac_probe(struct platform_device *pdev) -+{ -+ int ret = 0; -+ -+ snd_rpi_rpi_dac.dev = &pdev->dev; -+ -+ if (pdev->dev.of_node) { -+ struct device_node *i2s_node; -+ struct snd_soc_dai_link *dai = &snd_rpi_rpi_dac_dai[0]; -+ i2s_node = of_parse_phandle(pdev->dev.of_node, "i2s-controller", 0); -+ -+ if (i2s_node) { -+ dai->cpu_dai_name = NULL; -+ dai->cpu_of_node = i2s_node; -+ dai->platform_name = NULL; -+ dai->platform_of_node = i2s_node; -+ } -+ } -+ -+ ret = snd_soc_register_card(&snd_rpi_rpi_dac); -+ if (ret) -+ dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret); -+ -+ return ret; -+} -+ -+static int snd_rpi_rpi_dac_remove(struct platform_device *pdev) -+{ -+ return snd_soc_unregister_card(&snd_rpi_rpi_dac); -+} -+ -+static const struct of_device_id snd_rpi_rpi_dac_of_match[] = { -+ { .compatible = "rpi,rpi-dac", }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, snd_rpi_rpi_dac_of_match); -+ -+static struct platform_driver snd_rpi_rpi_dac_driver = { -+ .driver = { -+ .name = "snd-rpi-dac", -+ .owner = THIS_MODULE, -+ .of_match_table = snd_rpi_rpi_dac_of_match, -+ }, -+ .probe = snd_rpi_rpi_dac_probe, -+ .remove = snd_rpi_rpi_dac_remove, -+}; -+ -+module_platform_driver(snd_rpi_rpi_dac_driver); -+ -+MODULE_AUTHOR("Florian Meier "); -+MODULE_DESCRIPTION("ASoC Driver for RPi-DAC"); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-4.1.13.orig/sound/soc/bcm/rpi-proto.c linux-rpi/sound/soc/bcm/rpi-proto.c ---- linux-4.1.13.orig/sound/soc/bcm/rpi-proto.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/sound/soc/bcm/rpi-proto.c 2015-11-29 09:42:41.558989731 +0100 -@@ -0,0 +1,153 @@ -+/* -+ * ASoC driver for PROTO AudioCODEC (with a WM8731) -+ * connected to a Raspberry Pi -+ * -+ * Author: Florian Meier, -+ * Copyright 2013 -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+#include -+#include -+#include -+ -+#include "../codecs/wm8731.h" -+ -+static const unsigned int wm8731_rates_12288000[] = { -+ 8000, 32000, 48000, 96000, -+}; -+ -+static struct snd_pcm_hw_constraint_list wm8731_constraints_12288000 = { -+ .list = wm8731_rates_12288000, -+ .count = ARRAY_SIZE(wm8731_rates_12288000), -+}; -+ -+static int snd_rpi_proto_startup(struct snd_pcm_substream *substream) -+{ -+ /* Setup constraints, because there is a 12.288 MHz XTAL on the board */ -+ snd_pcm_hw_constraint_list(substream->runtime, 0, -+ SNDRV_PCM_HW_PARAM_RATE, -+ &wm8731_constraints_12288000); -+ return 0; -+} -+ -+static int snd_rpi_proto_hw_params(struct snd_pcm_substream *substream, -+ struct snd_pcm_hw_params *params) -+{ -+ struct snd_soc_pcm_runtime *rtd = substream->private_data; -+ struct snd_soc_codec *codec = rtd->codec; -+ struct snd_soc_dai *codec_dai = rtd->codec_dai; -+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai; -+ int sysclk = 12288000; /* This is fixed on this board */ -+ -+ /* Set proto bclk */ -+ int ret = snd_soc_dai_set_bclk_ratio(cpu_dai,32*2); -+ if (ret < 0){ -+ dev_err(codec->dev, -+ "Failed to set BCLK ratio %d\n", ret); -+ return ret; -+ } -+ -+ /* Set proto sysclk */ -+ ret = snd_soc_dai_set_sysclk(codec_dai, WM8731_SYSCLK_XTAL, -+ sysclk, SND_SOC_CLOCK_IN); -+ if (ret < 0) { -+ dev_err(codec->dev, -+ "Failed to set WM8731 SYSCLK: %d\n", ret); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+/* machine stream operations */ -+static struct snd_soc_ops snd_rpi_proto_ops = { -+ .startup = snd_rpi_proto_startup, -+ .hw_params = snd_rpi_proto_hw_params, -+}; -+ -+static struct snd_soc_dai_link snd_rpi_proto_dai[] = { -+{ -+ .name = "WM8731", -+ .stream_name = "WM8731 HiFi", -+ .cpu_dai_name = "bcm2708-i2s.0", -+ .codec_dai_name = "wm8731-hifi", -+ .platform_name = "bcm2708-i2s.0", -+ .codec_name = "wm8731.1-001a", -+ .dai_fmt = SND_SOC_DAIFMT_I2S -+ | SND_SOC_DAIFMT_NB_NF -+ | SND_SOC_DAIFMT_CBM_CFM, -+ .ops = &snd_rpi_proto_ops, -+}, -+}; -+ -+/* audio machine driver */ -+static struct snd_soc_card snd_rpi_proto = { -+ .name = "snd_rpi_proto", -+ .dai_link = snd_rpi_proto_dai, -+ .num_links = ARRAY_SIZE(snd_rpi_proto_dai), -+}; -+ -+static int snd_rpi_proto_probe(struct platform_device *pdev) -+{ -+ int ret = 0; -+ -+ snd_rpi_proto.dev = &pdev->dev; -+ -+ if (pdev->dev.of_node) { -+ struct device_node *i2s_node; -+ struct snd_soc_dai_link *dai = &snd_rpi_proto_dai[0]; -+ i2s_node = of_parse_phandle(pdev->dev.of_node, -+ "i2s-controller", 0); -+ -+ if (i2s_node) { -+ dai->cpu_dai_name = NULL; -+ dai->cpu_of_node = i2s_node; -+ dai->platform_name = NULL; -+ dai->platform_of_node = i2s_node; -+ } -+ } -+ -+ ret = snd_soc_register_card(&snd_rpi_proto); -+ if (ret) { -+ dev_err(&pdev->dev, -+ "snd_soc_register_card() failed: %d\n", ret); -+ } -+ -+ return ret; -+} -+ -+ -+static int snd_rpi_proto_remove(struct platform_device *pdev) -+{ -+ return snd_soc_unregister_card(&snd_rpi_proto); -+} -+ -+static const struct of_device_id snd_rpi_proto_of_match[] = { -+ { .compatible = "rpi,rpi-proto", }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, snd_rpi_proto_of_match); -+ -+static struct platform_driver snd_rpi_proto_driver = { -+ .driver = { -+ .name = "snd-rpi-proto", -+ .owner = THIS_MODULE, -+ .of_match_table = snd_rpi_proto_of_match, -+ }, -+ .probe = snd_rpi_proto_probe, -+ .remove = snd_rpi_proto_remove, -+}; -+ -+module_platform_driver(snd_rpi_proto_driver); -+ -+MODULE_AUTHOR("Florian Meier"); -+MODULE_DESCRIPTION("ASoC Driver for Raspberry Pi connected to PROTO board (WM8731)"); -+MODULE_LICENSE("GPL"); -diff -Nur linux-4.1.13.orig/sound/soc/codecs/Kconfig linux-rpi/sound/soc/codecs/Kconfig ---- linux-4.1.13.orig/sound/soc/codecs/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/sound/soc/codecs/Kconfig 2015-11-29 09:42:41.562989466 +0100 -@@ -83,6 +83,8 @@ - select SND_SOC_PCM512x_I2C if I2C - select SND_SOC_PCM512x_SPI if SPI_MASTER - select SND_SOC_RT286 if I2C -+ select SND_SOC_PCM5102A if I2C -+ select SND_SOC_PCM1794A if I2C - select SND_SOC_RT5631 if I2C - select SND_SOC_RT5640 if I2C - select SND_SOC_RT5645 if I2C -@@ -107,6 +109,7 @@ - select SND_SOC_TFA9879 if I2C - select SND_SOC_TLV320AIC23_I2C if I2C - select SND_SOC_TLV320AIC23_SPI if SPI_MASTER -+ select SND_SOC_TAS5713 if I2C - select SND_SOC_TLV320AIC26 if SPI_MASTER - select SND_SOC_TLV320AIC31XX if I2C - select SND_SOC_TLV320AIC32X4 if I2C -@@ -511,6 +514,12 @@ - tristate - depends on I2C - -+config SND_SOC_PCM1794A -+ tristate -+ -+config SND_SOC_PCM5102A -+ tristate -+ - config SND_SOC_RT5631 - tristate "Realtek ALC5631/RT5631 CODEC" - depends on I2C -@@ -615,6 +624,9 @@ - tristate "NXP Semiconductors TFA9879 amplifier" - depends on I2C - -+config SND_SOC_TAS5713 -+ tristate -+ - config SND_SOC_TLV320AIC23 - tristate - -diff -Nur linux-4.1.13.orig/sound/soc/codecs/Makefile linux-rpi/sound/soc/codecs/Makefile ---- linux-4.1.13.orig/sound/soc/codecs/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/sound/soc/codecs/Makefile 2015-11-29 09:42:41.562989466 +0100 -@@ -78,6 +78,8 @@ - snd-soc-pcm512x-spi-objs := pcm512x-spi.o - snd-soc-rl6231-objs := rl6231.o - snd-soc-rt286-objs := rt286.o -+snd-soc-pcm1794a-objs := pcm1794a.o -+snd-soc-pcm5102a-objs := pcm5102a.o - snd-soc-rt5631-objs := rt5631.o - snd-soc-rt5640-objs := rt5640.o - snd-soc-rt5645-objs := rt5645.o -@@ -107,6 +109,7 @@ - snd-soc-stac9766-objs := stac9766.o - snd-soc-tas5086-objs := tas5086.o - snd-soc-tfa9879-objs := tfa9879.o -+snd-soc-tas5713-objs := tas5713.o - snd-soc-tlv320aic23-objs := tlv320aic23.o - snd-soc-tlv320aic23-i2c-objs := tlv320aic23-i2c.o - snd-soc-tlv320aic23-spi-objs := tlv320aic23-spi.o -@@ -263,6 +266,8 @@ - obj-$(CONFIG_SND_SOC_PCM512x_SPI) += snd-soc-pcm512x-spi.o - obj-$(CONFIG_SND_SOC_RL6231) += snd-soc-rl6231.o - obj-$(CONFIG_SND_SOC_RT286) += snd-soc-rt286.o -+obj-$(CONFIG_SND_SOC_PCM1794A) += snd-soc-pcm1794a.o -+obj-$(CONFIG_SND_SOC_PCM5102A) += snd-soc-pcm5102a.o - obj-$(CONFIG_SND_SOC_RT5631) += snd-soc-rt5631.o - obj-$(CONFIG_SND_SOC_RT5640) += snd-soc-rt5640.o - obj-$(CONFIG_SND_SOC_RT5645) += snd-soc-rt5645.o -@@ -289,6 +294,7 @@ - obj-$(CONFIG_SND_SOC_TAS2552) += snd-soc-tas2552.o - obj-$(CONFIG_SND_SOC_TAS5086) += snd-soc-tas5086.o - obj-$(CONFIG_SND_SOC_TFA9879) += snd-soc-tfa9879.o -+obj-$(CONFIG_SND_SOC_TAS5713) += snd-soc-tas5713.o - obj-$(CONFIG_SND_SOC_TLV320AIC23) += snd-soc-tlv320aic23.o - obj-$(CONFIG_SND_SOC_TLV320AIC23_I2C) += snd-soc-tlv320aic23-i2c.o - obj-$(CONFIG_SND_SOC_TLV320AIC23_SPI) += snd-soc-tlv320aic23-spi.o -diff -Nur linux-4.1.13.orig/sound/soc/codecs/pcm1794a.c linux-rpi/sound/soc/codecs/pcm1794a.c ---- linux-4.1.13.orig/sound/soc/codecs/pcm1794a.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/sound/soc/codecs/pcm1794a.c 2015-11-29 09:42:41.574988668 +0100 -@@ -0,0 +1,69 @@ -+/* -+ * Driver for the PCM1794A codec -+ * -+ * Author: Florian Meier -+ * Copyright 2013 -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ */ -+ -+ -+#include -+#include -+#include -+ -+#include -+ -+static struct snd_soc_dai_driver pcm1794a_dai = { -+ .name = "pcm1794a-hifi", -+ .playback = { -+ .channels_min = 2, -+ .channels_max = 2, -+ .rates = SNDRV_PCM_RATE_8000_192000, -+ .formats = SNDRV_PCM_FMTBIT_S16_LE | -+ SNDRV_PCM_FMTBIT_S24_LE -+ }, -+}; -+ -+static struct snd_soc_codec_driver soc_codec_dev_pcm1794a; -+ -+static int pcm1794a_probe(struct platform_device *pdev) -+{ -+ return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_pcm1794a, -+ &pcm1794a_dai, 1); -+} -+ -+static int pcm1794a_remove(struct platform_device *pdev) -+{ -+ snd_soc_unregister_codec(&pdev->dev); -+ return 0; -+} -+ -+static const struct of_device_id pcm1794a_of_match[] = { -+ { .compatible = "ti,pcm1794a", }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, pcm1794a_of_match); -+ -+static struct platform_driver pcm1794a_codec_driver = { -+ .probe = pcm1794a_probe, -+ .remove = pcm1794a_remove, -+ .driver = { -+ .name = "pcm1794a-codec", -+ .owner = THIS_MODULE, -+ .of_match_table = of_match_ptr(pcm1794a_of_match), -+ }, -+}; -+ -+module_platform_driver(pcm1794a_codec_driver); -+ -+MODULE_DESCRIPTION("ASoC PCM1794A codec driver"); -+MODULE_AUTHOR("Florian Meier "); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-4.1.13.orig/sound/soc/codecs/pcm5102a.c linux-rpi/sound/soc/codecs/pcm5102a.c ---- linux-4.1.13.orig/sound/soc/codecs/pcm5102a.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/sound/soc/codecs/pcm5102a.c 2015-11-29 09:42:41.574988668 +0100 -@@ -0,0 +1,70 @@ -+/* -+ * Driver for the PCM5102A codec -+ * -+ * Author: Florian Meier -+ * Copyright 2013 -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ */ -+ -+ -+#include -+#include -+#include -+ -+#include -+ -+static struct snd_soc_dai_driver pcm5102a_dai = { -+ .name = "pcm5102a-hifi", -+ .playback = { -+ .channels_min = 2, -+ .channels_max = 2, -+ .rates = SNDRV_PCM_RATE_8000_192000, -+ .formats = SNDRV_PCM_FMTBIT_S16_LE | -+ SNDRV_PCM_FMTBIT_S24_LE | -+ SNDRV_PCM_FMTBIT_S32_LE -+ }, -+}; -+ -+static struct snd_soc_codec_driver soc_codec_dev_pcm5102a; -+ -+static int pcm5102a_probe(struct platform_device *pdev) -+{ -+ return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_pcm5102a, -+ &pcm5102a_dai, 1); -+} -+ -+static int pcm5102a_remove(struct platform_device *pdev) -+{ -+ snd_soc_unregister_codec(&pdev->dev); -+ return 0; -+} -+ -+static const struct of_device_id pcm5102a_of_match[] = { -+ { .compatible = "ti,pcm5102a", }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, pcm5102a_of_match); -+ -+static struct platform_driver pcm5102a_codec_driver = { -+ .probe = pcm5102a_probe, -+ .remove = pcm5102a_remove, -+ .driver = { -+ .name = "pcm5102a-codec", -+ .owner = THIS_MODULE, -+ .of_match_table = pcm5102a_of_match, -+ }, -+}; -+ -+module_platform_driver(pcm5102a_codec_driver); -+ -+MODULE_DESCRIPTION("ASoC PCM5102A codec driver"); -+MODULE_AUTHOR("Florian Meier "); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-4.1.13.orig/sound/soc/codecs/pcm512x.c linux-rpi/sound/soc/codecs/pcm512x.c ---- linux-4.1.13.orig/sound/soc/codecs/pcm512x.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/sound/soc/codecs/pcm512x.c 2015-11-29 09:42:41.574988668 +0100 -@@ -856,7 +856,8 @@ - int fssp; - int gpio; - -- lrclk_div = snd_soc_params_to_frame_size(params); -+ lrclk_div = snd_pcm_format_physical_width(params_format(params)) -+ * params_channels(params); - if (lrclk_div == 0) { - dev_err(dev, "No LRCLK?\n"); - return -EINVAL; -diff -Nur linux-4.1.13.orig/sound/soc/codecs/tas5713.c linux-rpi/sound/soc/codecs/tas5713.c ---- linux-4.1.13.orig/sound/soc/codecs/tas5713.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/sound/soc/codecs/tas5713.c 2015-11-29 09:42:41.586987871 +0100 -@@ -0,0 +1,369 @@ -+/* -+ * ASoC Driver for TAS5713 -+ * -+ * Author: Sebastian Eickhoff -+ * Copyright 2014 -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+ -+#include "tas5713.h" -+ -+ -+static struct i2c_client *i2c; -+ -+struct tas5713_priv { -+ struct regmap *regmap; -+ int mclk_div; -+ struct snd_soc_codec *codec; -+}; -+ -+static struct tas5713_priv *priv_data; -+ -+ -+ -+ -+/* -+ * _ _ ___ _ ___ _ _ -+ * /_\ | | / __| /_\ / __|___ _ _| |_ _ _ ___| |___ -+ * / _ \| |__\__ \/ _ \ | (__/ _ \ ' \ _| '_/ _ \ (_-< -+ * /_/ \_\____|___/_/ \_\ \___\___/_||_\__|_| \___/_/__/ -+ * -+ */ -+ -+static const DECLARE_TLV_DB_SCALE(tas5713_vol_tlv, -10000, 50, 1); -+ -+ -+static const struct snd_kcontrol_new tas5713_snd_controls[] = { -+ SOC_SINGLE_TLV ("Master" , TAS5713_VOL_MASTER, 0, 248, 1, tas5713_vol_tlv), -+ SOC_DOUBLE_R_TLV("Channels" , TAS5713_VOL_CH1, TAS5713_VOL_CH2, 0, 248, 1, tas5713_vol_tlv) -+}; -+ -+ -+ -+ -+/* -+ * __ __ _ _ ___ _ -+ * | \/ |__ _ __| |_ (_)_ _ ___ | \ _ _(_)_ _____ _ _ -+ * | |\/| / _` / _| ' \| | ' \/ -_) | |) | '_| \ V / -_) '_| -+ * |_| |_\__,_\__|_||_|_|_||_\___| |___/|_| |_|\_/\___|_| -+ * -+ */ -+ -+static int tas5713_hw_params(struct snd_pcm_substream *substream, -+ struct snd_pcm_hw_params *params, -+ struct snd_soc_dai *dai) -+{ -+ u16 blen = 0x00; -+ -+ struct snd_soc_codec *codec; -+ codec = dai->codec; -+ priv_data->codec = dai->codec; -+ -+ switch (params_format(params)) { -+ case SNDRV_PCM_FORMAT_S16_LE: -+ blen = 0x03; -+ break; -+ case SNDRV_PCM_FORMAT_S20_3LE: -+ blen = 0x1; -+ break; -+ case SNDRV_PCM_FORMAT_S24_LE: -+ blen = 0x04; -+ break; -+ case SNDRV_PCM_FORMAT_S32_LE: -+ blen = 0x05; -+ break; -+ default: -+ dev_err(dai->dev, "Unsupported word length: %u\n", -+ params_format(params)); -+ return -EINVAL; -+ } -+ -+ // set word length -+ snd_soc_update_bits(codec, TAS5713_SERIAL_DATA_INTERFACE, 0x7, blen); -+ -+ return 0; -+} -+ -+ -+static int tas5713_mute_stream(struct snd_soc_dai *dai, int mute, int stream) -+{ -+ unsigned int val = 0; -+ -+ struct tas5713_priv *tas5713; -+ struct snd_soc_codec *codec = dai->codec; -+ tas5713 = snd_soc_codec_get_drvdata(codec); -+ -+ if (mute) { -+ val = TAS5713_SOFT_MUTE_ALL; -+ } -+ -+ return regmap_write(tas5713->regmap, TAS5713_SOFT_MUTE, val); -+} -+ -+ -+static const struct snd_soc_dai_ops tas5713_dai_ops = { -+ .hw_params = tas5713_hw_params, -+ .mute_stream = tas5713_mute_stream, -+}; -+ -+ -+static struct snd_soc_dai_driver tas5713_dai = { -+ .name = "tas5713-hifi", -+ .playback = { -+ .stream_name = "Playback", -+ .channels_min = 2, -+ .channels_max = 2, -+ .rates = SNDRV_PCM_RATE_8000_48000, -+ .formats = (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE ), -+ }, -+ .ops = &tas5713_dai_ops, -+}; -+ -+ -+ -+ -+/* -+ * ___ _ ___ _ -+ * / __|___ __| |___ __ | \ _ _(_)_ _____ _ _ -+ * | (__/ _ \/ _` / -_) _| | |) | '_| \ V / -_) '_| -+ * \___\___/\__,_\___\__| |___/|_| |_|\_/\___|_| -+ * -+ */ -+ -+static int tas5713_remove(struct snd_soc_codec *codec) -+{ -+ struct tas5713_priv *tas5713; -+ -+ tas5713 = snd_soc_codec_get_drvdata(codec); -+ -+ return 0; -+} -+ -+ -+static int tas5713_probe(struct snd_soc_codec *codec) -+{ -+ struct tas5713_priv *tas5713; -+ int i, ret; -+ -+ i2c = container_of(codec->dev, struct i2c_client, dev); -+ -+ tas5713 = snd_soc_codec_get_drvdata(codec); -+ -+ // Reset error -+ ret = snd_soc_write(codec, TAS5713_ERROR_STATUS, 0x00); -+ if (ret < 0) return ret; -+ -+ // Trim oscillator -+ ret = snd_soc_write(codec, TAS5713_OSC_TRIM, 0x00); -+ if (ret < 0) return ret; -+ msleep(1000); -+ -+ // Reset error -+ ret = snd_soc_write(codec, TAS5713_ERROR_STATUS, 0x00); -+ if (ret < 0) return ret; -+ -+ // Clock mode: 44/48kHz, MCLK=64xfs -+ ret = snd_soc_write(codec, TAS5713_CLOCK_CTRL, 0x60); -+ if (ret < 0) return ret; -+ -+ // I2S 24bit -+ ret = snd_soc_write(codec, TAS5713_SERIAL_DATA_INTERFACE, 0x05); -+ if (ret < 0) return ret; -+ -+ // Unmute -+ ret = snd_soc_write(codec, TAS5713_SYSTEM_CTRL2, 0x00); -+ if (ret < 0) return ret; -+ ret = snd_soc_write(codec, TAS5713_SOFT_MUTE, 0x00); -+ if (ret < 0) return ret; -+ -+ // Set volume to 0db -+ ret = snd_soc_write(codec, TAS5713_VOL_MASTER, 0x00); -+ if (ret < 0) return ret; -+ -+ // Now start programming the default initialization sequence -+ for (i = 0; i < ARRAY_SIZE(tas5713_init_sequence); ++i) { -+ ret = i2c_master_send(i2c, -+ tas5713_init_sequence[i].data, -+ tas5713_init_sequence[i].size); -+ if (ret < 0) { -+ printk(KERN_INFO "TAS5713 CODEC PROBE: InitSeq returns: %d\n", ret); -+ } -+ } -+ -+ // Unmute -+ ret = snd_soc_write(codec, TAS5713_SYSTEM_CTRL2, 0x00); -+ if (ret < 0) return ret; -+ -+ return 0; -+} -+ -+ -+static struct snd_soc_codec_driver soc_codec_dev_tas5713 = { -+ .probe = tas5713_probe, -+ .remove = tas5713_remove, -+ .controls = tas5713_snd_controls, -+ .num_controls = ARRAY_SIZE(tas5713_snd_controls), -+}; -+ -+ -+ -+ -+/* -+ * ___ ___ ___ ___ _ -+ * |_ _|_ ) __| | \ _ _(_)_ _____ _ _ -+ * | | / / (__ | |) | '_| \ V / -_) '_| -+ * |___/___\___| |___/|_| |_|\_/\___|_| -+ * -+ */ -+ -+static const struct reg_default tas5713_reg_defaults[] = { -+ { 0x07 ,0x80 }, // R7 - VOL_MASTER - -40dB -+ { 0x08 , 30 }, // R8 - VOL_CH1 - 0dB -+ { 0x09 , 30 }, // R9 - VOL_CH2 - 0dB -+ { 0x0A ,0x80 }, // R10 - VOL_HEADPHONE - -40dB -+}; -+ -+ -+static bool tas5713_reg_volatile(struct device *dev, unsigned int reg) -+{ -+ switch (reg) { -+ case TAS5713_DEVICE_ID: -+ case TAS5713_ERROR_STATUS: -+ return true; -+ default: -+ return false; -+ } -+} -+ -+ -+static const struct of_device_id tas5713_of_match[] = { -+ { .compatible = "ti,tas5713", }, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, tas5713_of_match); -+ -+ -+static struct regmap_config tas5713_regmap_config = { -+ .reg_bits = 8, -+ .val_bits = 8, -+ -+ .max_register = TAS5713_MAX_REGISTER, -+ .volatile_reg = tas5713_reg_volatile, -+ -+ .cache_type = REGCACHE_RBTREE, -+ .reg_defaults = tas5713_reg_defaults, -+ .num_reg_defaults = ARRAY_SIZE(tas5713_reg_defaults), -+}; -+ -+ -+static int tas5713_i2c_probe(struct i2c_client *i2c, -+ const struct i2c_device_id *id) -+{ -+ int ret; -+ -+ priv_data = devm_kzalloc(&i2c->dev, sizeof *priv_data, GFP_KERNEL); -+ if (!priv_data) -+ return -ENOMEM; -+ -+ priv_data->regmap = devm_regmap_init_i2c(i2c, &tas5713_regmap_config); -+ if (IS_ERR(priv_data->regmap)) { -+ ret = PTR_ERR(priv_data->regmap); -+ return ret; -+ } -+ -+ i2c_set_clientdata(i2c, priv_data); -+ -+ ret = snd_soc_register_codec(&i2c->dev, -+ &soc_codec_dev_tas5713, &tas5713_dai, 1); -+ -+ return ret; -+} -+ -+ -+static int tas5713_i2c_remove(struct i2c_client *i2c) -+{ -+ snd_soc_unregister_codec(&i2c->dev); -+ i2c_set_clientdata(i2c, NULL); -+ -+ kfree(priv_data); -+ -+ return 0; -+} -+ -+ -+static const struct i2c_device_id tas5713_i2c_id[] = { -+ { "tas5713", 0 }, -+ { } -+}; -+ -+MODULE_DEVICE_TABLE(i2c, tas5713_i2c_id); -+ -+ -+static struct i2c_driver tas5713_i2c_driver = { -+ .driver = { -+ .name = "tas5713", -+ .owner = THIS_MODULE, -+ .of_match_table = tas5713_of_match, -+ }, -+ .probe = tas5713_i2c_probe, -+ .remove = tas5713_i2c_remove, -+ .id_table = tas5713_i2c_id -+}; -+ -+ -+static int __init tas5713_modinit(void) -+{ -+ int ret = 0; -+ -+ ret = i2c_add_driver(&tas5713_i2c_driver); -+ if (ret) { -+ printk(KERN_ERR "Failed to register tas5713 I2C driver: %d\n", -+ ret); -+ } -+ -+ return ret; -+} -+module_init(tas5713_modinit); -+ -+ -+static void __exit tas5713_exit(void) -+{ -+ i2c_del_driver(&tas5713_i2c_driver); -+} -+module_exit(tas5713_exit); -+ -+ -+MODULE_AUTHOR("Sebastian Eickhoff "); -+MODULE_DESCRIPTION("ASoC driver for TAS5713"); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-4.1.13.orig/sound/soc/codecs/tas5713.h linux-rpi/sound/soc/codecs/tas5713.h ---- linux-4.1.13.orig/sound/soc/codecs/tas5713.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-rpi/sound/soc/codecs/tas5713.h 2015-11-29 09:42:41.586987871 +0100 -@@ -0,0 +1,210 @@ -+/* -+ * ASoC Driver for TAS5713 -+ * -+ * Author: Sebastian Eickhoff -+ * Copyright 2014 -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ */ -+ -+#ifndef _TAS5713_H -+#define _TAS5713_H -+ -+ -+// TAS5713 I2C-bus register addresses -+ -+#define TAS5713_CLOCK_CTRL 0x00 -+#define TAS5713_DEVICE_ID 0x01 -+#define TAS5713_ERROR_STATUS 0x02 -+#define TAS5713_SYSTEM_CTRL1 0x03 -+#define TAS5713_SERIAL_DATA_INTERFACE 0x04 -+#define TAS5713_SYSTEM_CTRL2 0x05 -+#define TAS5713_SOFT_MUTE 0x06 -+#define TAS5713_VOL_MASTER 0x07 -+#define TAS5713_VOL_CH1 0x08 -+#define TAS5713_VOL_CH2 0x09 -+#define TAS5713_VOL_HEADPHONE 0x0A -+#define TAS5713_VOL_CONFIG 0x0E -+#define TAS5713_MODULATION_LIMIT 0x10 -+#define TAS5713_IC_DLY_CH1 0x11 -+#define TAS5713_IC_DLY_CH2 0x12 -+#define TAS5713_IC_DLY_CH3 0x13 -+#define TAS5713_IC_DLY_CH4 0x14 -+ -+#define TAS5713_START_STOP_PERIOD 0x1A -+#define TAS5713_OSC_TRIM 0x1B -+#define TAS5713_BKND_ERR 0x1C -+ -+#define TAS5713_INPUT_MUX 0x20 -+#define TAS5713_SRC_SELECT_CH4 0x21 -+#define TAS5713_PWM_MUX 0x25 -+ -+#define TAS5713_CH1_BQ0 0x29 -+#define TAS5713_CH1_BQ1 0x2A -+#define TAS5713_CH1_BQ2 0x2B -+#define TAS5713_CH1_BQ3 0x2C -+#define TAS5713_CH1_BQ4 0x2D -+#define TAS5713_CH1_BQ5 0x2E -+#define TAS5713_CH1_BQ6 0x2F -+#define TAS5713_CH1_BQ7 0x58 -+#define TAS5713_CH1_BQ8 0x59 -+ -+#define TAS5713_CH2_BQ0 0x30 -+#define TAS5713_CH2_BQ1 0x31 -+#define TAS5713_CH2_BQ2 0x32 -+#define TAS5713_CH2_BQ3 0x33 -+#define TAS5713_CH2_BQ4 0x34 -+#define TAS5713_CH2_BQ5 0x35 -+#define TAS5713_CH2_BQ6 0x36 -+#define TAS5713_CH2_BQ7 0x5C -+#define TAS5713_CH2_BQ8 0x5D -+ -+#define TAS5713_CH4_BQ0 0x5A -+#define TAS5713_CH4_BQ1 0x5B -+#define TAS5713_CH3_BQ0 0x5E -+#define TAS5713_CH3_BQ1 0x5F -+ -+#define TAS5713_DRC1_SOFTENING_FILTER_ALPHA_OMEGA 0x3B -+#define TAS5713_DRC1_ATTACK_RELEASE_RATE 0x3C -+#define TAS5713_DRC2_SOFTENING_FILTER_ALPHA_OMEGA 0x3E -+#define TAS5713_DRC2_ATTACK_RELEASE_RATE 0x3F -+#define TAS5713_DRC1_ATTACK_RELEASE_THRES 0x40 -+#define TAS5713_DRC2_ATTACK_RELEASE_THRES 0x43 -+#define TAS5713_DRC_CTRL 0x46 -+ -+#define TAS5713_BANK_SW_CTRL 0x50 -+#define TAS5713_CH1_OUTPUT_MIXER 0x51 -+#define TAS5713_CH2_OUTPUT_MIXER 0x52 -+#define TAS5713_CH1_INPUT_MIXER 0x53 -+#define TAS5713_CH2_INPUT_MIXER 0x54 -+#define TAS5713_OUTPUT_POST_SCALE 0x56 -+#define TAS5713_OUTPUT_PRESCALE 0x57 -+ -+#define TAS5713_IDF_POST_SCALE 0x62 -+ -+#define TAS5713_CH1_INLINE_MIXER 0x70 -+#define TAS5713_CH1_INLINE_DRC_EN_MIXER 0x71 -+#define TAS5713_CH1_R_CHANNEL_MIXER 0x72 -+#define TAS5713_CH1_L_CHANNEL_MIXER 0x73 -+#define TAS5713_CH2_INLINE_MIXER 0x74 -+#define TAS5713_CH2_INLINE_DRC_EN_MIXER 0x75 -+#define TAS5713_CH2_L_CHANNEL_MIXER 0x76 -+#define TAS5713_CH2_R_CHANNEL_MIXER 0x77 -+ -+#define TAS5713_UPDATE_DEV_ADDR_KEY 0xF8 -+#define TAS5713_UPDATE_DEV_ADDR_REG 0xF9 -+ -+#define TAS5713_REGISTER_COUNT 0x46 -+#define TAS5713_MAX_REGISTER 0xF9 -+ -+ -+// Bitmasks for registers -+#define TAS5713_SOFT_MUTE_ALL 0x07 -+ -+ -+ -+struct tas5713_init_command { -+ const int size; -+ const char *const data; -+}; -+ -+static const struct tas5713_init_command tas5713_init_sequence[] = { -+ -+ // Trim oscillator -+ { .size = 2, .data = "\x1B\x00" }, -+ // System control register 1 (0x03): block DC -+ { .size = 2, .data = "\x03\x80" }, -+ // Mute everything -+ { .size = 2, .data = "\x05\x40" }, -+ // Modulation limit register (0x10): 97.7% -+ { .size = 2, .data = "\x10\x02" }, -+ // Interchannel delay registers -+ // (0x11, 0x12, 0x13, and 0x14): BD mode -+ { .size = 2, .data = "\x11\xB8" }, -+ { .size = 2, .data = "\x12\x60" }, -+ { .size = 2, .data = "\x13\xA0" }, -+ { .size = 2, .data = "\x14\x48" }, -+ // PWM shutdown group register (0x19): no shutdown -+ { .size = 2, .data = "\x19\x00" }, -+ // Input multiplexer register (0x20): BD mode -+ { .size = 2, .data = "\x20\x00\x89\x77\x72" }, -+ // PWM output mux register (0x25) -+ // Channel 1 --> OUTA, channel 1 neg --> OUTB -+ // Channel 2 --> OUTC, channel 2 neg --> OUTD -+ { .size = 5, .data = "\x25\x01\x02\x13\x45" }, -+ // DRC control (0x46): DRC off -+ { .size = 5, .data = "\x46\x00\x00\x00\x00" }, -+ // BKND_ERR register (0x1C): 299ms reset period -+ { .size = 2, .data = "\x1C\x07" }, -+ // Mute channel 3 -+ { .size = 2, .data = "\x0A\xFF" }, -+ // Volume configuration register (0x0E): volume slew 512 steps -+ { .size = 2, .data = "\x0E\x90" }, -+ // Clock control register (0x00): 44/48kHz, MCLK=64xfs -+ { .size = 2, .data = "\x00\x60" }, -+ // Bank switch and eq control (0x50): no bank switching -+ { .size = 5, .data = "\x50\x00\x00\x00\x00" }, -+ // Volume registers (0x07, 0x08, 0x09, 0x0A) -+ { .size = 2, .data = "\x07\x20" }, -+ { .size = 2, .data = "\x08\x30" }, -+ { .size = 2, .data = "\x09\x30" }, -+ { .size = 2, .data = "\x0A\xFF" }, -+ // 0x72, 0x73, 0x76, 0x77 input mixer: -+ // no intermix between channels -+ { .size = 5, .data = "\x72\x00\x00\x00\x00" }, -+ { .size = 5, .data = "\x73\x00\x80\x00\x00" }, -+ { .size = 5, .data = "\x76\x00\x00\x00\x00" }, -+ { .size = 5, .data = "\x77\x00\x80\x00\x00" }, -+ // 0x70, 0x71, 0x74, 0x75 inline DRC mixer: -+ // no inline DRC inmix -+ { .size = 5, .data = "\x70\x00\x80\x00\x00" }, -+ { .size = 5, .data = "\x71\x00\x00\x00\x00" }, -+ { .size = 5, .data = "\x74\x00\x80\x00\x00" }, -+ { .size = 5, .data = "\x75\x00\x00\x00\x00" }, -+ // 0x56, 0x57 Output scale -+ { .size = 5, .data = "\x56\x00\x80\x00\x00" }, -+ { .size = 5, .data = "\x57\x00\x02\x00\x00" }, -+ // 0x3B, 0x3c -+ { .size = 9, .data = "\x3B\x00\x08\x00\x00\x00\x78\x00\x00" }, -+ { .size = 9, .data = "\x3C\x00\x00\x01\x00\xFF\xFF\xFF\x00" }, -+ { .size = 9, .data = "\x3E\x00\x08\x00\x00\x00\x78\x00\x00" }, -+ { .size = 9, .data = "\x3F\x00\x00\x01\x00\xFF\xFF\xFF\x00" }, -+ { .size = 9, .data = "\x40\x00\x00\x01\x00\xFF\xFF\xFF\x00" }, -+ { .size = 9, .data = "\x43\x00\x00\x01\x00\xFF\xFF\xFF\x00" }, -+ // 0x51, 0x52: output mixer -+ { .size = 9, .data = "\x51\x00\x80\x00\x00\x00\x00\x00\x00" }, -+ { .size = 9, .data = "\x52\x00\x80\x00\x00\x00\x00\x00\x00" }, -+ // PEQ defaults -+ { .size = 21, .data = "\x29\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, -+ { .size = 21, .data = "\x2A\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, -+ { .size = 21, .data = "\x2B\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, -+ { .size = 21, .data = "\x2C\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, -+ { .size = 21, .data = "\x2D\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, -+ { .size = 21, .data = "\x2E\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, -+ { .size = 21, .data = "\x2F\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, -+ { .size = 21, .data = "\x30\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, -+ { .size = 21, .data = "\x31\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, -+ { .size = 21, .data = "\x32\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, -+ { .size = 21, .data = "\x33\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, -+ { .size = 21, .data = "\x34\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, -+ { .size = 21, .data = "\x35\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, -+ { .size = 21, .data = "\x36\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, -+ { .size = 21, .data = "\x58\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, -+ { .size = 21, .data = "\x59\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, -+ { .size = 21, .data = "\x5C\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, -+ { .size = 21, .data = "\x5D\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, -+ { .size = 21, .data = "\x5E\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, -+ { .size = 21, .data = "\x5F\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, -+ { .size = 21, .data = "\x5A\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, -+ { .size = 21, .data = "\x5B\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, -+}; -+ -+ -+#endif /* _TAS5713_H */ -diff -Nur linux-4.1.13.orig/sound/soc/codecs/tpa6130a2.c linux-rpi/sound/soc/codecs/tpa6130a2.c ---- linux-4.1.13.orig/sound/soc/codecs/tpa6130a2.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/sound/soc/codecs/tpa6130a2.c 2015-11-29 09:42:41.586987871 +0100 -@@ -4,6 +4,7 @@ - * Copyright (C) Nokia Corporation - * - * Author: Peter Ujfalusi -+ * Modified: Jan Grulich - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License -@@ -52,6 +53,8 @@ - enum tpa_model id; - }; - -+static void tpa6130a2_channel_enable(u8 channel, int enable); -+ - static int tpa6130a2_i2c_read(int reg) - { - struct tpa6130a2_data *data; -@@ -189,7 +192,7 @@ - } - - static int tpa6130a2_get_volsw(struct snd_kcontrol *kcontrol, -- struct snd_ctl_elem_value *ucontrol) -+ struct snd_ctl_elem_value *ucontrol) - { - struct soc_mixer_control *mc = - (struct soc_mixer_control *)kcontrol->private_value; -@@ -218,7 +221,7 @@ - } - - static int tpa6130a2_put_volsw(struct snd_kcontrol *kcontrol, -- struct snd_ctl_elem_value *ucontrol) -+ struct snd_ctl_elem_value *ucontrol) - { - struct soc_mixer_control *mc = - (struct soc_mixer_control *)kcontrol->private_value; -@@ -255,8 +258,22 @@ - return 1; - } - -+static int tpa6130a2_put_hp_sw(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ int enable = ucontrol->value.integer.value[0]; -+ unsigned int state; -+ -+ state = (tpa6130a2_read(TPA6130A2_REG_VOL_MUTE) & 0x80) == 0; -+ if (state == enable) -+ return 0; /* No change */ -+ -+ tpa6130a2_channel_enable(TPA6130A2_HP_EN_R | TPA6130A2_HP_EN_L, enable); -+ return 1; /* Changed */ -+} -+ - /* -- * TPA6130 volume. From -59.5 to 4 dB with increasing step size when going -+ * TPA6130 volume. From -59.5 to +4.0 dB with increasing step size when going - * down in gain. - */ - static const unsigned int tpa6130_tlv[] = { -@@ -278,6 +295,9 @@ - TPA6130A2_REG_VOL_MUTE, 0, 0x3f, 0, - tpa6130a2_get_volsw, tpa6130a2_put_volsw, - tpa6130_tlv), -+ SOC_SINGLE_EXT("TPA6130A2 Headphone Playback Switch", -+ TPA6130A2_REG_VOL_MUTE, 7, 1, 1, -+ tpa6130a2_get_volsw, tpa6130a2_put_hp_sw), - }; - - static const unsigned int tpa6140_tlv[] = { -@@ -292,6 +312,9 @@ - TPA6130A2_REG_VOL_MUTE, 1, 0x1f, 0, - tpa6130a2_get_volsw, tpa6130a2_put_volsw, - tpa6140_tlv), -+ SOC_SINGLE_EXT("TPA6140A2 Headphone Playback Switch", -+ TPA6130A2_REG_VOL_MUTE, 7, 1, 1, -+ tpa6130a2_get_volsw, tpa6130a2_put_hp_sw), - }; - - /* -diff -Nur linux-4.1.13.orig/sound/soc/codecs/wm8804.c linux-rpi/sound/soc/codecs/wm8804.c ---- linux-4.1.13.orig/sound/soc/codecs/wm8804.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-rpi/sound/soc/codecs/wm8804.c 2015-11-29 09:42:41.598987074 +0100 -@@ -304,6 +304,7 @@ - blen = 0x1; - break; - case 24: -+ case 32: - blen = 0x2; - break; - default: -@@ -515,7 +516,7 @@ - }; - - #define WM8804_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ -- SNDRV_PCM_FMTBIT_S24_LE) -+ SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) - - #define WM8804_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ - SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \ -@@ -543,7 +544,7 @@ - }; - - static const struct snd_soc_codec_driver soc_codec_dev_wm8804 = { -- .idle_bias_off = true, -+ .idle_bias_off = false, - - .dapm_widgets = wm8804_dapm_widgets, - .num_dapm_widgets = ARRAY_SIZE(wm8804_dapm_widgets), diff --git a/target/arm/bcm28xx/patches/4.1.16/0001-raspberry-pi-github.patch b/target/arm/bcm28xx/patches/4.1.16/0001-raspberry-pi-github.patch new file mode 100644 index 000000000..4fe3c5c2d --- /dev/null +++ b/target/arm/bcm28xx/patches/4.1.16/0001-raspberry-pi-github.patch @@ -0,0 +1,143407 @@ +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/bcm2708_common.dtsi linux-rpi/arch/arm/boot/dts/bcm2708_common.dtsi +--- linux-4.1.13.orig/arch/arm/boot/dts/bcm2708_common.dtsi 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/bcm2708_common.dtsi 2015-11-29 09:42:34.571454018 +0100 +@@ -0,0 +1,321 @@ ++/include/ "skeleton.dtsi" ++ ++/ { ++ interrupt-parent = <&intc>; ++ ++ aliases { ++ audio = &audio; ++ sound = &sound; ++ soc = &soc; ++ dma = &dma; ++ intc = &intc; ++ watchdog = &watchdog; ++ random = &random; ++ mailbox = &mailbox; ++ gpio = &gpio; ++ uart0 = &uart0; ++ i2s = &i2s; ++ spi0 = &spi0; ++ i2c0 = &i2c0; ++ uart1 = &uart1; ++ mmc = &mmc; ++ i2c1 = &i2c1; ++ i2c2 = &i2c2; ++ usb = &usb; ++ leds = &leds; ++ fb = &fb; ++ vchiq = &vchiq; ++ thermal = &thermal; ++ clocks = &clocks; ++ }; ++ ++ /* Onboard audio */ ++ audio: audio { ++ compatible = "brcm,bcm2835-audio"; ++ brcm,pwm-channels = <8>; ++ status = "disabled"; ++ }; ++ ++ /* External sound card */ ++ sound: sound { ++ }; ++ ++ soc: soc { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ dma: dma@7e007000 { ++ compatible = "brcm,bcm2835-dma"; ++ reg = <0x7e007000 0xf00>; ++ interrupts = <1 16>, ++ <1 17>, ++ <1 18>, ++ <1 19>, ++ <1 20>, ++ <1 21>, ++ <1 22>, ++ <1 23>, ++ <1 24>, ++ <1 25>, ++ <1 26>, ++ <1 27>; ++ ++ #dma-cells = <1>; ++ brcm,dma-channel-mask = <0x0f35>; ++ }; ++ ++ intc: interrupt-controller { ++ compatible = "brcm,bcm2708-armctrl-ic"; ++ reg = <0x7e00b200 0x200>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ ++ mailbox: mailbox@7e00b800 { ++ compatible = "brcm,bcm2835-mbox"; ++ reg = <0x7e00b880 0x40>; ++ interrupts = <0 1>; ++ #mbox-cells = <0>; ++ }; ++ ++ watchdog: watchdog@7e100000 { ++ compatible = "brcm,bcm2835-pm-wdt"; ++ reg = <0x7e100000 0x28>; ++ status = "disabled"; ++ }; ++ ++ random: rng@7e104000 { ++ compatible = "brcm,bcm2835-rng"; ++ reg = <0x7e104000 0x10>; ++ status = "disabled"; ++ }; ++ ++ gpio: gpio@7e200000 { ++ compatible = "brcm,bcm2835-gpio"; ++ reg = <0x7e200000 0xb4>; ++ interrupts = <2 17>, <2 18>; ++ ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ ++ uart0: uart@7e201000 { ++ compatible = "arm,pl011", "arm,primecell"; ++ reg = <0x7e201000 0x1000>; ++ interrupts = <2 25>; ++ clocks = <&clk_uart0 &clk_apb_p>; ++ clock-names = "uartclk","apb_pclk"; ++ arm,primecell-periphid = <0x00241011>; // For an explanation, see ++ // https://github.com/raspberrypi/linux/commit/13731d862cf5219216533a3b0de052cee4cc5038 ++ status = "disabled"; ++ }; ++ ++ i2s: i2s@7e203000 { ++ compatible = "brcm,bcm2708-i2s"; ++ reg = <0x7e203000 0x24>, ++ <0x7e101098 0x08>; ++ ++ //dmas = <&dma 2>, ++ // <&dma 3>; ++ dma-names = "tx", "rx"; ++ status = "disabled"; ++ }; ++ ++ spi0: spi@7e204000 { ++ compatible = "brcm,bcm2835-spi"; ++ reg = <0x7e204000 0x1000>; ++ interrupts = <2 22>; ++ clocks = <&clk_core>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ /* the dma channels */ ++ dmas = <&dma 6>, <&dma 7>; ++ dma-names = "tx", "rx"; ++ /* the chipselects used - <0> means native GPIO ++ * add more gpios if necessary as <&gpio 6 1> ++ * (but do not forget to make them output!) ++ */ ++ cs-gpios = <0>, <0>; ++ }; ++ ++ i2c0: i2c@7e205000 { ++ compatible = "brcm,bcm2708-i2c"; ++ reg = <0x7e205000 0x1000>; ++ interrupts = <2 21>; ++ clocks = <&clk_i2c>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ pwm: pwm@7e20c000 { ++ compatible = "brcm,bcm2835-pwm"; ++ reg = <0x7e20c000 0x28>; ++ clocks = <&clk_pwm>; ++ #pwm-cells = <2>; ++ status = "disabled"; ++ }; ++ ++ uart1: uart@7e215040 { ++ compatible = "brcm,bcm2835-aux-uart", "ns16550"; ++ reg = <0x7e215040 0x40>; ++ interrupts = <1 29>; ++ clocks = <&clk_uart1>; ++ reg-shift = <2>; ++ no-loopback-test; ++ status = "disabled"; ++ }; ++ ++ mmc: mmc@7e300000 { ++ compatible = "brcm,bcm2835-mmc"; ++ reg = <0x7e300000 0x100>; ++ interrupts = <2 30>; ++ clocks = <&clk_mmc>; ++ dmas = <&dma 11>, ++ <&dma 11>; ++ dma-names = "tx", "rx"; ++ status = "disabled"; ++ }; ++ ++ i2c1: i2c@7e804000 { ++ compatible = "brcm,bcm2708-i2c"; ++ reg = <0x7e804000 0x1000>; ++ interrupts = <2 21>; ++ clocks = <&clk_i2c>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c2: i2c@7e805000 { ++ // Beware - this is shared with the HDMI module. ++ // Careless use may break (really) your display. ++ // Caveat emptor. ++ compatible = "brcm,bcm2708-i2c"; ++ reg = <0x7e805000 0x1000>; ++ interrupts = <2 21>; ++ clocks = <&clk_i2c>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ smi: smi@7e600000 { ++ compatible = "brcm,bcm2835-smi"; ++ reg = <0x7e600000 0x44>, <0x7e1010b0 0x8>; ++ interrupts = <2 16>; ++ brcm,smi-clock-source = <6>; ++ brcm,smi-clock-divisor = <4>; ++ dmas = <&dma 4>; ++ dma-names = "rx-tx"; ++ status = "disabled"; ++ }; ++ ++ usb: usb@7e980000 { ++ compatible = "brcm,bcm2708-usb"; ++ reg = <0x7e980000 0x10000>, ++ <0x7e006000 0x1000>; ++ interrupts = <2 0>, ++ <1 9>; ++ }; ++ ++ firmware: firmware { ++ compatible = "raspberrypi,bcm2835-firmware"; ++ mboxes = <&mailbox>; ++ }; ++ ++ leds: leds { ++ compatible = "gpio-leds"; ++ }; ++ ++ fb: fb { ++ compatible = "brcm,bcm2708-fb"; ++ firmware = <&firmware>; ++ status = "disabled"; ++ }; ++ ++ vchiq: vchiq { ++ compatible = "brcm,bcm2835-vchiq"; ++ reg = <0x7e00b840 0xf>; ++ interrupts = <0 2>; ++ cache-line-size = <32>; ++ firmware = <&firmware>; ++ }; ++ ++ thermal: thermal { ++ compatible = "brcm,bcm2835-thermal"; ++ firmware = <&firmware>; ++ }; ++ }; ++ ++ clocks: clocks { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ clk_mmc: clock@0 { ++ compatible = "fixed-clock"; ++ reg = <0>; ++ #clock-cells = <0>; ++ clock-output-names = "mmc"; ++ clock-frequency = <250000000>; ++ }; ++ ++ clk_i2c: clock@1 { ++ compatible = "fixed-clock"; ++ reg = <1>; ++ #clock-cells = <0>; ++ clock-output-names = "i2c"; ++ clock-frequency = <250000000>; ++ }; ++ ++ clk_core: clock@2 { ++ compatible = "fixed-clock"; ++ reg = <2>; ++ #clock-cells = <0>; ++ clock-output-names = "core"; ++ clock-frequency = <250000000>; ++ }; ++ ++ clk_uart0: clock@3 { ++ compatible = "fixed-clock"; ++ reg = <3>; ++ #clock-cells = <0>; ++ clock-output-names = "uart0_pclk"; ++ clock-frequency = <3000000>; ++ }; ++ ++ clk_apb_p: clock@4 { ++ compatible = "fixed-clock"; ++ reg = <4>; ++ #clock-cells = <0>; ++ clock-output-names = "apb_pclk"; ++ clock-frequency = <126000000>; ++ }; ++ ++ clk_pwm: clock@5 { ++ compatible = "fixed-clock"; ++ reg = <3>; ++ #clock-cells = <0>; ++ clock-output-names = "pwm"; ++ clock-frequency = <100000000>; ++ }; ++ ++ clk_uart1: clock@6 { ++ compatible = "fixed-factor-clock"; ++ clocks = <&clk_core>; ++ #clock-cells = <0>; ++ clock-div = <1>; ++ clock-mult = <2>; ++ }; ++ }; ++ ++ __overrides__ { ++ cache_line_size = <&vchiq>, "cache-line-size:0"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/bcm2708.dtsi linux-rpi/arch/arm/boot/dts/bcm2708.dtsi +--- linux-4.1.13.orig/arch/arm/boot/dts/bcm2708.dtsi 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/bcm2708.dtsi 2015-11-29 09:42:34.571454018 +0100 +@@ -0,0 +1,25 @@ ++/include/ "bcm2708_common.dtsi" ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ model = "BCM2708"; ++ ++ chosen { ++ /* No padding required - the boot loader can do that. */ ++ bootargs = ""; ++ }; ++ ++ soc { ++ ranges = <0x7e000000 0x20000000 0x01000000>; ++ ++ arm-pmu { ++ compatible = "arm,arm1176-pmu"; ++ }; ++ ++ gpiomem { ++ compatible = "brcm,bcm2835-gpiomem"; ++ reg = <0x7e200000 0x1000>; ++ status = "okay"; ++ }; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/bcm2708-rpi-b.dts linux-rpi/arch/arm/boot/dts/bcm2708-rpi-b.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/bcm2708-rpi-b.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/bcm2708-rpi-b.dts 2015-11-29 09:42:34.571454018 +0100 +@@ -0,0 +1,118 @@ ++/dts-v1/; ++ ++/include/ "bcm2708.dtsi" ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ model = "Raspberry Pi Model B"; ++}; ++ ++&gpio { ++ spi0_pins: spi0_pins { ++ brcm,pins = <7 8 9 10 11>; ++ brcm,function = <4>; /* alt0 */ ++ }; ++ ++ i2c0_pins: i2c0 { ++ brcm,pins = <0 1>; ++ brcm,function = <4>; ++ }; ++ ++ i2c1_pins: i2c1 { ++ brcm,pins = <2 3>; ++ brcm,function = <4>; ++ }; ++ ++ i2s_pins: i2s { ++ brcm,pins = <28 29 30 31>; ++ brcm,function = <6>; /* alt2 */ ++ }; ++}; ++ ++&mmc { ++ status = "okay"; ++ bus-width = <4>; ++}; ++ ++&fb { ++ status = "okay"; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; ++ ++ spidev@0{ ++ compatible = "spidev"; ++ reg = <0>; /* CE0 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <500000>; ++ }; ++ ++ spidev@1{ ++ compatible = "spidev"; ++ reg = <1>; /* CE1 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <500000>; ++ }; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++ clock-frequency = <100000>; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ clock-frequency = <100000>; ++}; ++ ++&i2c2 { ++ clock-frequency = <100000>; ++}; ++ ++&i2s { ++ #sound-dai-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s_pins>; ++}; ++ ++&leds { ++ act_led: act { ++ label = "led0"; ++ linux,default-trigger = "mmc0"; ++ gpios = <&gpio 16 1>; ++ }; ++}; ++ ++/ { ++ __overrides__ { ++ uart0 = <&uart0>,"status"; ++ uart0_clkrate = <&clk_uart0>,"clock-frequency:0"; ++ i2s = <&i2s>,"status"; ++ spi = <&spi0>,"status"; ++ i2c0 = <&i2c0>,"status"; ++ i2c1 = <&i2c1>,"status"; ++ i2c2_iknowwhatimdoing = <&i2c2>,"status"; ++ i2c0_baudrate = <&i2c0>,"clock-frequency:0"; ++ i2c1_baudrate = <&i2c1>,"clock-frequency:0"; ++ i2c2_baudrate = <&i2c2>,"clock-frequency:0"; ++ core_freq = <&clk_core>,"clock-frequency:0"; ++ ++ act_led_gpio = <&act_led>,"gpios:4"; ++ act_led_activelow = <&act_led>,"gpios:8"; ++ act_led_trigger = <&act_led>,"linux,default-trigger"; ++ ++ audio = <&audio>,"status"; ++ watchdog = <&watchdog>,"status"; ++ random = <&random>,"status"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts linux-rpi/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts 2015-11-29 09:42:34.571454018 +0100 +@@ -0,0 +1,128 @@ ++/dts-v1/; ++ ++/include/ "bcm2708.dtsi" ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ model = "Raspberry Pi Model B+"; ++}; ++ ++&gpio { ++ spi0_pins: spi0_pins { ++ brcm,pins = <7 8 9 10 11>; ++ brcm,function = <4>; /* alt0 */ ++ }; ++ ++ i2c0_pins: i2c0 { ++ brcm,pins = <0 1>; ++ brcm,function = <4>; ++ }; ++ ++ i2c1_pins: i2c1 { ++ brcm,pins = <2 3>; ++ brcm,function = <4>; ++ }; ++ ++ i2s_pins: i2s { ++ brcm,pins = <18 19 20 21>; ++ brcm,function = <4>; /* alt0 */ ++ }; ++}; ++ ++&mmc { ++ status = "okay"; ++ bus-width = <4>; ++}; ++ ++&fb { ++ status = "okay"; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; ++ ++ spidev@0{ ++ compatible = "spidev"; ++ reg = <0>; /* CE0 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <500000>; ++ }; ++ ++ spidev@1{ ++ compatible = "spidev"; ++ reg = <1>; /* CE1 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <500000>; ++ }; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++ clock-frequency = <100000>; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ clock-frequency = <100000>; ++}; ++ ++&i2c2 { ++ clock-frequency = <100000>; ++}; ++ ++&i2s { ++ #sound-dai-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s_pins>; ++}; ++ ++&leds { ++ act_led: act { ++ label = "led0"; ++ linux,default-trigger = "mmc0"; ++ gpios = <&gpio 47 0>; ++ }; ++ ++ pwr_led: pwr { ++ label = "led1"; ++ linux,default-trigger = "input"; ++ gpios = <&gpio 35 0>; ++ }; ++}; ++ ++/ { ++ __overrides__ { ++ uart0 = <&uart0>,"status"; ++ uart0_clkrate = <&clk_uart0>,"clock-frequency:0"; ++ i2s = <&i2s>,"status"; ++ spi = <&spi0>,"status"; ++ i2c0 = <&i2c0>,"status"; ++ i2c1 = <&i2c1>,"status"; ++ i2c2_iknowwhatimdoing = <&i2c2>,"status"; ++ i2c0_baudrate = <&i2c0>,"clock-frequency:0"; ++ i2c1_baudrate = <&i2c1>,"clock-frequency:0"; ++ i2c2_baudrate = <&i2c2>,"clock-frequency:0"; ++ core_freq = <&clk_core>,"clock-frequency:0"; ++ ++ act_led_gpio = <&act_led>,"gpios:4"; ++ act_led_activelow = <&act_led>,"gpios:8"; ++ act_led_trigger = <&act_led>,"linux,default-trigger"; ++ ++ pwr_led_gpio = <&pwr_led>,"gpios:4"; ++ pwr_led_activelow = <&pwr_led>,"gpios:8"; ++ pwr_led_trigger = <&pwr_led>,"linux,default-trigger"; ++ ++ audio = <&audio>,"status"; ++ watchdog = <&watchdog>,"status"; ++ random = <&random>,"status"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/bcm2708-rpi-cm.dts linux-rpi/arch/arm/boot/dts/bcm2708-rpi-cm.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/bcm2708-rpi-cm.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/bcm2708-rpi-cm.dts 2015-11-29 09:42:34.571454018 +0100 +@@ -0,0 +1,92 @@ ++/dts-v1/; ++ ++/include/ "bcm2708-rpi-cm.dtsi" ++ ++/ { ++ model = "Raspberry Pi Compute Module"; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&gpio { ++ spi0_pins: spi0_pins { ++ brcm,pins = <7 8 9 10 11>; ++ brcm,function = <4>; /* alt0 */ ++ }; ++ ++ i2c0_pins: i2c0 { ++ brcm,pins = <0 1>; ++ brcm,function = <4>; ++ }; ++ ++ i2c1_pins: i2c1 { ++ brcm,pins = <2 3>; ++ brcm,function = <4>; ++ }; ++ ++ i2s_pins: i2s { ++ brcm,pins = <18 19 20 21>; ++ brcm,function = <4>; /* alt0 */ ++ }; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; ++ ++ spidev@0{ ++ compatible = "spidev"; ++ reg = <0>; /* CE0 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <500000>; ++ }; ++ ++ spidev@1{ ++ compatible = "spidev"; ++ reg = <1>; /* CE1 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <500000>; ++ }; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++ clock-frequency = <100000>; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ clock-frequency = <100000>; ++}; ++ ++&i2c2 { ++ clock-frequency = <100000>; ++}; ++ ++&i2s { ++ #sound-dai-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s_pins>; ++}; ++ ++/ { ++ __overrides__ { ++ uart0 = <&uart0>,"status"; ++ uart0_clkrate = <&clk_uart0>,"clock-frequency:0"; ++ i2s = <&i2s>,"status"; ++ spi = <&spi0>,"status"; ++ i2c0 = <&i2c0>,"status"; ++ i2c1 = <&i2c1>,"status"; ++ i2c2_iknowwhatimdoing = <&i2c2>,"status"; ++ i2c0_baudrate = <&i2c0>,"clock-frequency:0"; ++ i2c1_baudrate = <&i2c1>,"clock-frequency:0"; ++ i2c2_baudrate = <&i2c2>,"clock-frequency:0"; ++ core_freq = <&clk_core>,"clock-frequency:0"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi linux-rpi/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi +--- linux-4.1.13.orig/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi 2015-11-29 09:42:34.571454018 +0100 +@@ -0,0 +1,30 @@ ++/include/ "bcm2708.dtsi" ++ ++&leds { ++ act_led: act { ++ label = "led0"; ++ linux,default-trigger = "mmc0"; ++ gpios = <&gpio 47 0>; ++ }; ++}; ++ ++&mmc { ++ status = "okay"; ++ bus-width = <4>; ++}; ++ ++&fb { ++ status = "okay"; ++}; ++ ++/ { ++ __overrides__ { ++ act_led_gpio = <&act_led>,"gpios:4"; ++ act_led_activelow = <&act_led>,"gpios:8"; ++ act_led_trigger = <&act_led>,"linux,default-trigger"; ++ ++ audio = <&audio>,"status"; ++ watchdog = <&watchdog>,"status"; ++ random = <&random>,"status"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/bcm2709.dtsi linux-rpi/arch/arm/boot/dts/bcm2709.dtsi +--- linux-4.1.13.orig/arch/arm/boot/dts/bcm2709.dtsi 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/bcm2709.dtsi 2015-11-29 09:42:34.571454018 +0100 +@@ -0,0 +1,76 @@ ++/include/ "bcm2708_common.dtsi" ++ ++/ { ++ compatible = "brcm,bcm2709"; ++ model = "BCM2709"; ++ ++ chosen { ++ /* No padding required - the boot loader can do that. */ ++ bootargs = ""; ++ }; ++ ++ soc { ++ ranges = <0x7e000000 0x3f000000 0x01000000>; ++ ++ arm-pmu { ++ compatible = "arm,cortex-a7-pmu"; ++ interrupts = <3 9>; ++ }; ++ ++ gpiomem { ++ compatible = "brcm,bcm2835-gpiomem"; ++ reg = <0x7e200000 0x1000>; ++ status = "okay"; ++ }; ++ }; ++ ++ timer { ++ compatible = "arm,armv7-timer"; ++ clock-frequency = <19200000>; ++ interrupts = <3 0>, // PHYS_SECURE_PPI ++ <3 1>, // PHYS_NONSECURE_PPI ++ <3 3>, // VIRT_PPI ++ <3 2>; // HYP_PPI ++ always-on; ++ }; ++ ++ cpus: cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ v7_cpu0: cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ reg = <0xf00>; ++ clock-frequency = <800000000>; ++ }; ++ ++ v7_cpu1: cpu@1 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ reg = <0xf01>; ++ clock-frequency = <800000000>; ++ }; ++ ++ v7_cpu2: cpu@2 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ reg = <0xf02>; ++ clock-frequency = <800000000>; ++ }; ++ ++ v7_cpu3: cpu@3 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ reg = <0xf03>; ++ clock-frequency = <800000000>; ++ }; ++ }; ++ ++ __overrides__ { ++ arm_freq = <&v7_cpu0>, "clock-frequency:0", ++ <&v7_cpu1>, "clock-frequency:0", ++ <&v7_cpu2>, "clock-frequency:0", ++ <&v7_cpu3>, "clock-frequency:0"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/bcm2709-rpi-2-b.dts linux-rpi/arch/arm/boot/dts/bcm2709-rpi-2-b.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/bcm2709-rpi-2-b.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/bcm2709-rpi-2-b.dts 2015-11-29 09:42:34.571454018 +0100 +@@ -0,0 +1,128 @@ ++/dts-v1/; ++ ++/include/ "bcm2709.dtsi" ++ ++/ { ++ compatible = "brcm,bcm2709"; ++ model = "Raspberry Pi 2 Model B"; ++}; ++ ++&gpio { ++ spi0_pins: spi0_pins { ++ brcm,pins = <7 8 9 10 11>; ++ brcm,function = <4>; /* alt0 */ ++ }; ++ ++ i2c0_pins: i2c0 { ++ brcm,pins = <0 1>; ++ brcm,function = <4>; ++ }; ++ ++ i2c1_pins: i2c1 { ++ brcm,pins = <2 3>; ++ brcm,function = <4>; ++ }; ++ ++ i2s_pins: i2s { ++ brcm,pins = <18 19 20 21>; ++ brcm,function = <4>; /* alt0 */ ++ }; ++}; ++ ++&mmc { ++ status = "okay"; ++ bus-width = <4>; ++}; ++ ++&fb { ++ status = "okay"; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; ++ ++ spidev@0{ ++ compatible = "spidev"; ++ reg = <0>; /* CE0 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <500000>; ++ }; ++ ++ spidev@1{ ++ compatible = "spidev"; ++ reg = <1>; /* CE1 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <500000>; ++ }; ++}; ++ ++&i2c0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; ++ clock-frequency = <100000>; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ clock-frequency = <100000>; ++}; ++ ++&i2c2 { ++ clock-frequency = <100000>; ++}; ++ ++&i2s { ++ #sound-dai-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s_pins>; ++}; ++ ++&leds { ++ act_led: act { ++ label = "led0"; ++ linux,default-trigger = "mmc0"; ++ gpios = <&gpio 47 0>; ++ }; ++ ++ pwr_led: pwr { ++ label = "led1"; ++ linux,default-trigger = "input"; ++ gpios = <&gpio 35 0>; ++ }; ++}; ++ ++/ { ++ __overrides__ { ++ uart0 = <&uart0>,"status"; ++ uart0_clkrate = <&clk_uart0>,"clock-frequency:0"; ++ i2s = <&i2s>,"status"; ++ spi = <&spi0>,"status"; ++ i2c0 = <&i2c0>,"status"; ++ i2c1 = <&i2c1>,"status"; ++ i2c2_iknowwhatimdoing = <&i2c2>,"status"; ++ i2c0_baudrate = <&i2c0>,"clock-frequency:0"; ++ i2c1_baudrate = <&i2c1>,"clock-frequency:0"; ++ i2c2_baudrate = <&i2c2>,"clock-frequency:0"; ++ core_freq = <&clk_core>,"clock-frequency:0"; ++ ++ act_led_gpio = <&act_led>,"gpios:4"; ++ act_led_activelow = <&act_led>,"gpios:8"; ++ act_led_trigger = <&act_led>,"linux,default-trigger"; ++ ++ pwr_led_gpio = <&pwr_led>,"gpios:4"; ++ pwr_led_activelow = <&pwr_led>,"gpios:8"; ++ pwr_led_trigger = <&pwr_led>,"linux,default-trigger"; ++ ++ audio = <&audio>,"status"; ++ watchdog = <&watchdog>,"status"; ++ random = <&random>,"status"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/bcm2835.dtsi linux-rpi/arch/arm/boot/dts/bcm2835.dtsi +--- linux-4.1.13.orig/arch/arm/boot/dts/bcm2835.dtsi 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/bcm2835.dtsi 2015-11-29 09:42:34.571454018 +0100 +@@ -6,14 +6,15 @@ + interrupt-parent = <&intc>; + + chosen { +- bootargs = "earlyprintk console=ttyAMA0"; ++ bootargs = ""; + }; + +- soc { ++ soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x7e000000 0x20000000 0x02000000>; ++ dma-ranges = <0x40000000 0x00000000 0x20000000>; + + timer@7e003000 { + compatible = "brcm,bcm2835-system-timer"; +@@ -50,16 +51,23 @@ + #interrupt-cells = <2>; + }; + +- watchdog@7e100000 { ++ watchdog: watchdog@7e100000 { + compatible = "brcm,bcm2835-pm-wdt"; + reg = <0x7e100000 0x28>; + }; + +- rng@7e104000 { ++ random: rng@7e104000 { + compatible = "brcm,bcm2835-rng"; + reg = <0x7e104000 0x10>; + }; + ++ mailbox: mailbox@7e00b800 { ++ compatible = "brcm,bcm2835-mbox"; ++ reg = <0x7e00b880 0x40>; ++ interrupts = <0 1>; ++ #mbox-cells = <0>; ++ }; ++ + gpio: gpio@7e200000 { + compatible = "brcm,bcm2835-gpio"; + reg = <0x7e200000 0xb4>; +@@ -83,7 +91,7 @@ + #interrupt-cells = <2>; + }; + +- uart@7e201000 { ++ uart0: uart@7e201000 { + compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell"; + reg = <0x7e201000 0x1000>; + interrupts = <2 25>; +@@ -93,8 +101,8 @@ + + i2s: i2s@7e203000 { + compatible = "brcm,bcm2835-i2s"; +- reg = <0x7e203000 0x20>, +- <0x7e101098 0x02>; ++ reg = <0x7e203000 0x24>, ++ <0x7e101098 0x08>; + + dmas = <&dma 2>, + <&dma 3>; +@@ -102,7 +110,7 @@ + status = "disabled"; + }; + +- spi: spi@7e204000 { ++ spi0: spi@7e204000 { + compatible = "brcm,bcm2835-spi"; + reg = <0x7e204000 0x1000>; + interrupts = <2 22>; +@@ -122,11 +130,14 @@ + status = "disabled"; + }; + +- sdhci: sdhci@7e300000 { +- compatible = "brcm,bcm2835-sdhci"; ++ mmc: mmc@7e300000 { ++ compatible = "brcm,bcm2835-mmc"; + reg = <0x7e300000 0x100>; + interrupts = <2 30>; + clocks = <&clk_mmc>; ++ dmas = <&dma 11>, ++ <&dma 11>; ++ dma-names = "tx", "rx"; + status = "disabled"; + }; + +@@ -140,10 +151,12 @@ + status = "disabled"; + }; + +- usb@7e980000 { +- compatible = "brcm,bcm2835-usb"; +- reg = <0x7e980000 0x10000>; +- interrupts = <1 9>; ++ usb: usb@7e980000 { ++ compatible = "brcm,bcm2708-usb"; ++ reg = <0x7e980000 0x10000>, ++ <0x7e006000 0x1000>; ++ interrupts = <2 0>, ++ <1 9>; + }; + + arm-pmu { +@@ -161,7 +174,7 @@ + reg = <0>; + #clock-cells = <0>; + clock-output-names = "mmc"; +- clock-frequency = <100000000>; ++ clock-frequency = <250000000>; + }; + + clk_i2c: clock@1 { +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/bcm2835-rpi-b.dts linux-rpi/arch/arm/boot/dts/bcm2835-rpi-b.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/bcm2835-rpi-b.dts 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/bcm2835-rpi-b.dts 2015-11-29 09:42:34.571454018 +0100 +@@ -5,19 +5,28 @@ + compatible = "raspberrypi,model-b", "brcm,bcm2835"; + model = "Raspberry Pi Model B"; + +- leds { +- act { +- gpios = <&gpio 16 1>; +- }; +- }; + }; + + &gpio { +- pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>; +- +- /* I2S interface */ +- i2s_alt2: i2s_alt2 { ++ i2s_pins: i2s { + brcm,pins = <28 29 30 31>; +- brcm,function = <6>; /* alt2 */ ++ brcm,function = <4>; /* alt0 */ ++ }; ++}; ++ ++&i2s { ++ #sound-dai-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s_pins>; ++}; ++ ++&act_led { ++ gpios = <&gpio 16 1>; ++}; ++ ++/ { ++ __overrides__ { ++ act_led_gpio = <&act_led>,"gpios:4"; ++ act_led_activelow = <&act_led>,"gpios:8"; + }; + }; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts linux-rpi/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts 2015-11-29 09:42:34.571454018 +0100 +@@ -4,27 +4,40 @@ + / { + compatible = "raspberrypi,model-b-plus", "brcm,bcm2835"; + model = "Raspberry Pi Model B+"; +- +- leds { +- act { +- gpios = <&gpio 47 0>; +- }; +- +- pwr { +- label = "PWR"; +- gpios = <&gpio 35 0>; +- default-state = "keep"; +- linux,default-trigger = "default-on"; +- }; +- }; + }; + + &gpio { +- pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>; +- +- /* I2S interface */ +- i2s_alt0: i2s_alt0 { ++ i2s_pins: i2s { + brcm,pins = <18 19 20 21>; + brcm,function = <4>; /* alt0 */ + }; + }; ++ ++&i2s { ++ #sound-dai-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s_pins>; ++}; ++ ++&act_led { ++ gpios = <&gpio 47 0>; ++}; ++ ++&leds { ++ pwr_led: pwr { ++ label = "led1"; ++ linux,default-trigger = "input"; ++ gpios = <&gpio 35 0>; ++ }; ++}; ++ ++/ { ++ __overrides__ { ++ act_led_gpio = <&act_led>,"gpios:4"; ++ act_led_activelow = <&act_led>,"gpios:8"; ++ ++ pwr_led_gpio = <&pwr_led>,"gpios:4"; ++ pwr_led_activelow = <&pwr_led>,"gpios:8"; ++ pwr_led_trigger = <&pwr_led>,"linux,default-trigger"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/bcm2835-rpi.dtsi linux-rpi/arch/arm/boot/dts/bcm2835-rpi.dtsi +--- linux-4.1.13.orig/arch/arm/boot/dts/bcm2835-rpi.dtsi 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/bcm2835-rpi.dtsi 2015-11-29 09:42:34.571454018 +0100 +@@ -1,51 +1,133 @@ + /include/ "bcm2835.dtsi" + + / { ++ /* This is left here in case u-boot needs it */ + memory { + reg = <0 0x10000000>; + }; + +- leds { ++ aliases { ++ soc = &soc; ++ spi0 = &spi0; ++ i2c0 = &i2c0; ++ i2c1 = &i2c1; ++ i2s = &i2s; ++ gpio = &gpio; ++ intc = &intc; ++ leds = &leds; ++ sound = &sound; ++ }; ++ ++ leds: leds { + compatible = "gpio-leds"; + +- act { +- label = "ACT"; +- default-state = "keep"; +- linux,default-trigger = "heartbeat"; ++ act_led: act { ++ label = "led0"; ++ linux,default-trigger = "mmc0"; ++ }; ++ }; ++ ++ soc { ++ firmware: firmware { ++ compatible = "raspberrypi,bcm2835-firmware"; ++ mboxes = <&mailbox>; ++ }; ++ ++ fb: fb { ++ compatible = "brcm,bcm2708-fb"; ++ firmware = <&firmware>; ++ }; ++ ++ thermal: thermal { ++ compatible = "brcm,bcm2835-thermal"; ++ firmware = <&firmware>; ++ }; ++ ++ vchiq: vchiq { ++ compatible = "brcm,bcm2835-vchiq"; ++ reg = <0x7e00b840 0xf>; ++ interrupts = <0 2>; ++ cache-line-size = <32>; ++ firmware = <&firmware>; + }; + }; ++ ++ /* Onboard audio */ ++ audio: audio { ++ compatible = "brcm,bcm2835-audio"; ++ brcm,pwm-channels = <8>; ++ status = "disabled"; ++ }; ++ ++ /* External sound card */ ++ sound: sound { ++ }; + }; + + &gpio { +- pinctrl-names = "default"; ++ spi0_pins: spi0_pins { ++ brcm,pins = <7 8 9 10 11>; ++ brcm,function = <4>; /* alt0 */ ++ }; + +- gpioout: gpioout { +- brcm,pins = <6>; +- brcm,function = <1>; /* GPIO out */ ++ i2c0_pins: i2c0 { ++ brcm,pins = <0 1>; ++ brcm,function = <4>; + }; + +- alt0: alt0 { +- brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15 40 45>; +- brcm,function = <4>; /* alt0 */ ++ i2c1_pins: i2c1 { ++ brcm,pins = <2 3>; ++ brcm,function = <4>; ++ }; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; ++ ++ spidev@0{ ++ compatible = "spidev"; ++ reg = <0>; /* CE0 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <500000>; + }; + +- alt3: alt3 { +- brcm,pins = <48 49 50 51 52 53>; +- brcm,function = <7>; /* alt3 */ ++ spidev@1{ ++ compatible = "spidev"; ++ reg = <1>; /* CE1 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <500000>; + }; + }; + + &i2c0 { +- status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c0_pins>; + clock-frequency = <100000>; + }; + + &i2c1 { +- status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; + clock-frequency = <100000>; + }; + +-&sdhci { ++&mmc { + status = "okay"; + bus-width = <4>; + }; ++ ++/ { ++ __overrides__ { ++ i2s = <&i2s>,"status"; ++ spi = <&spi0>,"status"; ++ i2c0 = <&i2c0>,"status"; ++ i2c1 = <&i2c1>,"status"; ++ i2c0_baudrate = <&i2c0>,"clock-frequency:0"; ++ i2c1_baudrate = <&i2c1>,"clock-frequency:0"; ++ act_led_trigger = <&act_led>,"linux,default-trigger"; ++ audio = <&audio>,"status"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/Makefile linux-rpi/arch/arm/boot/dts/Makefile +--- linux-4.1.13.orig/arch/arm/boot/dts/Makefile 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/Makefile 2015-11-29 09:42:34.559454815 +0100 +@@ -1,5 +1,24 @@ + ifeq ($(CONFIG_OF),y) + ++dtb-$(CONFIG_BCM2708_DT) += bcm2708-rpi-b.dtb ++dtb-$(CONFIG_BCM2708_DT) += bcm2708-rpi-b-plus.dtb ++dtb-$(CONFIG_BCM2708_DT) += bcm2708-rpi-cm.dtb ++dtb-$(CONFIG_BCM2709_DT) += bcm2709-rpi-2-b.dtb ++ ++# Raspberry Pi ++ifeq ($(CONFIG_BCM2708_DT),y) ++ RPI_DT_OVERLAYS=y ++endif ++ifeq ($(CONFIG_BCM2709_DT),y) ++ RPI_DT_OVERLAYS=y ++endif ++ifeq ($(CONFIG_ARCH_BCM2835),y) ++ RPI_DT_OVERLAYS=y ++endif ++ifeq ($(RPI_DT_OVERLAYS),y) ++ dts-dirs += overlays ++endif ++ + dtb-$(CONFIG_ARCH_ALPINE) += \ + alpine-db.dtb + dtb-$(CONFIG_MACH_ASM9260) += \ +@@ -660,7 +679,17 @@ + mt6592-evb.dtb \ + mt8127-moose.dtb \ + mt8135-evbp1.dtb ++ ++targets += dtbs dtbs_install ++targets += $(dtb-y) ++ + endif + + always := $(dtb-y) ++subdir-y := $(dts-dirs) + clean-files := *.dtb ++ ++# Enable fixups to support overlays on BCM2708 platforms ++ifeq ($(RPI_DT_OVERLAYS),y) ++ DTC_FLAGS ?= -@ ++endif +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/ads7846-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/ads7846-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/ads7846-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/ads7846-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,83 @@ ++/* ++ * Generic Device Tree overlay for the ADS7846 touch controller ++ * ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709"; ++ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ ++ spidev@0{ ++ status = "disabled"; ++ }; ++ ++ spidev@1{ ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ ads7846_pins: ads7846_pins { ++ brcm,pins = <255>; /* illegal default value */ ++ brcm,function = <0>; /* in */ ++ brcm,pull = <0>; /* none */ ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi0>; ++ __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ ads7846: ads7846@1 { ++ compatible = "ti,ads7846"; ++ reg = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ads7846_pins>; ++ ++ spi-max-frequency = <2000000>; ++ interrupts = <255 2>; /* high-to-low edge triggered */ ++ interrupt-parent = <&gpio>; ++ pendown-gpio = <&gpio 255 0>; ++ ++ /* driver defaults */ ++ ti,x-min = /bits/ 16 <0>; ++ ti,y-min = /bits/ 16 <0>; ++ ti,x-max = /bits/ 16 <0x0FFF>; ++ ti,y-max = /bits/ 16 <0x0FFF>; ++ ti,pressure-min = /bits/ 16 <0>; ++ ti,pressure-max = /bits/ 16 <0xFFFF>; ++ ti,x-plate-ohms = /bits/ 16 <400>; ++ }; ++ }; ++ }; ++ __overrides__ { ++ cs = <&ads7846>,"reg:0"; ++ speed = <&ads7846>,"spi-max-frequency:0"; ++ penirq = <&ads7846_pins>,"brcm,pins:0", /* REQUIRED */ ++ <&ads7846>,"interrupts:0", ++ <&ads7846>,"pendown-gpio:4"; ++ penirq_pull = <&ads7846_pins>,"brcm,pull:0"; ++ swapxy = <&ads7846>,"ti,swap-xy?"; ++ xmin = <&ads7846>,"ti,x-min;0"; ++ ymin = <&ads7846>,"ti,y-min;0"; ++ xmax = <&ads7846>,"ti,x-max;0"; ++ ymax = <&ads7846>,"ti,y-max;0"; ++ pmin = <&ads7846>,"ti,pressure-min;0"; ++ pmax = <&ads7846>,"ti,pressure-max;0"; ++ xohms = <&ads7846>,"ti,x-plate-ohms;0"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/at86rf233-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/at86rf233-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/at86rf233-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/at86rf233-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,54 @@ ++/dts-v1/; ++/plugin/; ++ ++/* Overlay for Atmel AT86RF233 IEEE 802.15.4 WPAN transceiver on spi0.0 */ ++ ++/ { ++ compatible = "brcm,bcm2835", "brcm,bcm2836", "brcm,bcm2708", "brcm,bcm2709"; ++ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ status = "okay"; ++ ++ spidev@0{ ++ status = "disabled"; ++ }; ++ ++ lowpan0: at86rf233@0 { ++ compatible = "atmel,at86rf233"; ++ reg = <0>; ++ interrupt-parent = <&gpio>; ++ interrupts = <23 4>; /* active high */ ++ reset-gpio = <&gpio 24 1>; ++ sleep-gpio = <&gpio 25 1>; ++ spi-max-frequency = <6000000>; ++ xtal-trim = /bits/ 8 <0xf>; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ lowpan0_pins: lowpan0_pins { ++ brcm,pins = <23 24 25>; ++ brcm,function = <0 1 1>; /* in out out */ ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ interrupt = <&lowpan0>, "interrupts:0", ++ <&lowpan0_pins>, "brcm,pins:0"; ++ reset = <&lowpan0>, "reset-gpio:4", ++ <&lowpan0_pins>, "brcm,pins:4"; ++ sleep = <&lowpan0>, "sleep-gpio:4", ++ <&lowpan0_pins>, "brcm,pins:8"; ++ speed = <&lowpan0>, "spi-max-frequency:0"; ++ trim = <&lowpan0>, "xtal-trim.0"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/bmp085_i2c-sensor-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/bmp085_i2c-sensor-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/bmp085_i2c-sensor-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/bmp085_i2c-sensor-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,23 @@ ++// Definitions for BMP085/BMP180 digital barometric pressure and temperature sensors from Bosch Sensortec ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&i2c_arm>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ bmp085@77 { ++ compatible = "bosch,bmp085"; ++ reg = <0x77>; ++ default-oversampling = <3>; ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/dht11-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/dht11-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/dht11-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/dht11-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,39 @@ ++/* ++ * Overlay for the DHT11/21/22 humidity/temperature sensor modules. ++ */ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target-path = "/"; ++ __overlay__ { ++ ++ dht11: dht11@0 { ++ compatible = "dht11"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&dht11_pins>; ++ gpios = <&gpio 4 0>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ dht11_pins: dht11_pins { ++ brcm,pins = <4>; ++ brcm,function = <0>; // in ++ brcm,pull = <0>; // off ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ gpiopin = <&dht11_pins>,"brcm,pins:0", ++ <&dht11>,"gpios:4"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/enc28j60-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/enc28j60-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/enc28j60-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/enc28j60-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,50 @@ ++// Overlay for the Microchip ENC28J60 Ethernet Controller ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ status = "okay"; ++ ++ spidev@0{ ++ status = "disabled"; ++ }; ++ ++ eth1: enc28j60@0{ ++ compatible = "microchip,enc28j60"; ++ reg = <0>; /* CE0 */ ++ pinctrl-names = "default"; ++ pinctrl-0 = <ð1_pins>; ++ interrupt-parent = <&gpio>; ++ interrupts = <25 0x2>; /* falling edge */ ++ spi-max-frequency = <12000000>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ eth1_pins: eth1_pins { ++ brcm,pins = <25>; ++ brcm,function = <0>; /* in */ ++ brcm,pull = <0>; /* none */ ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ int_pin = <ð1>, "interrupts:0", ++ <ð1_pins>, "brcm,pins:0"; ++ speed = <ð1>, "spi-max-frequency:0"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/gpio-ir-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/gpio-ir-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/gpio-ir-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/gpio-ir-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,45 @@ ++// Definitions for ir-gpio module ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target-path = "/"; ++ __overlay__ { ++ gpio_ir: ir-receiver { ++ compatible = "gpio-ir-receiver"; ++ ++ // pin number, high or low ++ gpios = <&gpio 18 1>; ++ ++ // parameter for keymap name ++ linux,rc-map-name = "rc-rc6-mce"; ++ ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ gpio_ir_pins: gpio_ir_pins { ++ brcm,pins = <18>; // pin 18 ++ brcm,function = <0>; // in ++ brcm,pull = <1>; // down ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ // parameters ++ gpio_pin = <&gpio_ir>,"gpios:4", ++ <&gpio_ir_pins>,"brcm,pins:0", ++ <&gpio_ir_pins>,"brcm,pull:0"; // pin number ++ gpio_pull = <&gpio_ir_pins>,"brcm,pull:0"; // pull-up/down state ++ ++ rc-map-name = <&gpio_ir>,"linux,rc-map-name"; // default rc map ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/gpio-poweroff-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/gpio-poweroff-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/gpio-poweroff-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/gpio-poweroff-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,34 @@ ++// Definitions for gpio-poweroff module ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target-path = "/"; ++ __overlay__ { ++ power_ctrl: power_ctrl { ++ compatible = "gpio-poweroff"; ++ gpios = <&gpio 26 0>; ++ force; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ power_ctrl_pins: power_ctrl_pins { ++ brcm,pins = <26>; ++ brcm,function = <1>; // out ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ gpiopin = <&power_ctrl>,"gpios:4", ++ <&power_ctrl_pins>,"brcm,pins:0"; ++ active_low = <&power_ctrl>,"gpios:8"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/hifiberry-amp-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/hifiberry-amp-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/hifiberry-amp-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/hifiberry-amp-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,39 @@ ++// Definitions for HiFiBerry Amp/Amp+ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&sound>; ++ __overlay__ { ++ compatible = "hifiberry,hifiberry-amp"; ++ i2s-controller = <&i2s>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2s>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&i2c1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ tas5713@1b { ++ #sound-dai-cells = <0>; ++ compatible = "ti,tas5713"; ++ reg = <0x1b>; ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/hifiberry-dac-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/hifiberry-dac-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/hifiberry-dac-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/hifiberry-dac-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,34 @@ ++// Definitions for HiFiBerry DAC ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&sound>; ++ __overlay__ { ++ compatible = "hifiberry,hifiberry-dac"; ++ i2s-controller = <&i2s>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2s>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target-path = "/"; ++ __overlay__ { ++ pcm5102a-codec { ++ #sound-dai-cells = <0>; ++ compatible = "ti,pcm5102a"; ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/hifiberry-dacplus-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/hifiberry-dacplus-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/hifiberry-dacplus-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/hifiberry-dacplus-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,50 @@ ++// Definitions for HiFiBerry DAC+ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target-path = "/clocks"; ++ __overlay__ { ++ dacpro_osc: dacpro_osc { ++ compatible = "hifiberry,dacpro-clk"; ++ #clock-cells = <0>; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&sound>; ++ __overlay__ { ++ compatible = "hifiberry,hifiberry-dacplus"; ++ i2s-controller = <&i2s>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&i2s>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&i2c1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ pcm5122@4d { ++ #sound-dai-cells = <0>; ++ compatible = "ti,pcm5122"; ++ reg = <0x4d>; ++ clocks = <&dacpro_osc>; ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/hifiberry-digi-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/hifiberry-digi-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/hifiberry-digi-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/hifiberry-digi-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,39 @@ ++// Definitions for HiFiBerry Digi ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&sound>; ++ __overlay__ { ++ compatible = "hifiberry,hifiberry-digi"; ++ i2s-controller = <&i2s>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2s>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&i2c1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ wm8804@3b { ++ #sound-dai-cells = <0>; ++ compatible = "wlf,wm8804"; ++ reg = <0x3b>; ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/hy28a-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/hy28a-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/hy28a-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/hy28a-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,87 @@ ++/* ++ * Device Tree overlay for HY28A display ++ * ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709"; ++ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ ++ spidev@0{ ++ status = "disabled"; ++ }; ++ ++ spidev@1{ ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ hy28a_pins: hy28a_pins { ++ brcm,pins = <17 25 18>; ++ brcm,function = <0 1 1>; /* in out out */ ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi0>; ++ __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ hy28a: hy28a@0{ ++ compatible = "ilitek,ili9320"; ++ reg = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hy28a_pins>; ++ ++ spi-max-frequency = <32000000>; ++ spi-cpol; ++ spi-cpha; ++ rotate = <270>; ++ bgr; ++ fps = <50>; ++ buswidth = <8>; ++ startbyte = <0x70>; ++ reset-gpios = <&gpio 25 0>; ++ led-gpios = <&gpio 18 1>; ++ debug = <0>; ++ }; ++ ++ hy28a_ts: hy28a-ts@1 { ++ compatible = "ti,ads7846"; ++ reg = <1>; ++ ++ spi-max-frequency = <2000000>; ++ interrupts = <17 2>; /* high-to-low edge triggered */ ++ interrupt-parent = <&gpio>; ++ pendown-gpio = <&gpio 17 0>; ++ ti,x-plate-ohms = /bits/ 16 <100>; ++ ti,pressure-max = /bits/ 16 <255>; ++ }; ++ }; ++ }; ++ __overrides__ { ++ speed = <&hy28a>,"spi-max-frequency:0"; ++ rotate = <&hy28a>,"rotate:0"; ++ fps = <&hy28a>,"fps:0"; ++ debug = <&hy28a>,"debug:0"; ++ xohms = <&hy28a_ts>,"ti,x-plate-ohms;0"; ++ resetgpio = <&hy28a>,"reset-gpios:4", ++ <&hy28a_pins>, "brcm,pins:1"; ++ ledgpio = <&hy28a>,"led-gpios:4", ++ <&hy28a_pins>, "brcm,pins:2"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/hy28b-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/hy28b-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/hy28b-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/hy28b-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,142 @@ ++/* ++ * Device Tree overlay for HY28b display shield by Texy ++ * ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709"; ++ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ ++ spidev@0{ ++ status = "disabled"; ++ }; ++ ++ spidev@1{ ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ hy28b_pins: hy28b_pins { ++ brcm,pins = <17 25 18>; ++ brcm,function = <0 1 1>; /* in out out */ ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi0>; ++ __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ hy28b: hy28b@0{ ++ compatible = "ilitek,ili9325"; ++ reg = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hy28b_pins>; ++ ++ spi-max-frequency = <48000000>; ++ spi-cpol; ++ spi-cpha; ++ rotate = <270>; ++ bgr; ++ fps = <50>; ++ buswidth = <8>; ++ startbyte = <0x70>; ++ reset-gpios = <&gpio 25 0>; ++ led-gpios = <&gpio 18 1>; ++ ++ gamma = "04 1F 4 7 7 0 7 7 6 0\n0F 00 1 7 4 0 0 0 6 7"; ++ ++ init = <0x10000e7 0x0010 ++ 0x1000000 0x0001 ++ 0x1000001 0x0100 ++ 0x1000002 0x0700 ++ 0x1000003 0x1030 ++ 0x1000004 0x0000 ++ 0x1000008 0x0207 ++ 0x1000009 0x0000 ++ 0x100000a 0x0000 ++ 0x100000c 0x0001 ++ 0x100000d 0x0000 ++ 0x100000f 0x0000 ++ 0x1000010 0x0000 ++ 0x1000011 0x0007 ++ 0x1000012 0x0000 ++ 0x1000013 0x0000 ++ 0x2000032 ++ 0x1000010 0x1590 ++ 0x1000011 0x0227 ++ 0x2000032 ++ 0x1000012 0x009c ++ 0x2000032 ++ 0x1000013 0x1900 ++ 0x1000029 0x0023 ++ 0x100002b 0x000e ++ 0x2000032 ++ 0x1000020 0x0000 ++ 0x1000021 0x0000 ++ 0x2000032 ++ 0x1000050 0x0000 ++ 0x1000051 0x00ef ++ 0x1000052 0x0000 ++ 0x1000053 0x013f ++ 0x1000060 0xa700 ++ 0x1000061 0x0001 ++ 0x100006a 0x0000 ++ 0x1000080 0x0000 ++ 0x1000081 0x0000 ++ 0x1000082 0x0000 ++ 0x1000083 0x0000 ++ 0x1000084 0x0000 ++ 0x1000085 0x0000 ++ 0x1000090 0x0010 ++ 0x1000092 0x0000 ++ 0x1000093 0x0003 ++ 0x1000095 0x0110 ++ 0x1000097 0x0000 ++ 0x1000098 0x0000 ++ 0x1000007 0x0133 ++ 0x1000020 0x0000 ++ 0x1000021 0x0000 ++ 0x2000064>; ++ debug = <0>; ++ }; ++ ++ hy28b_ts: hy28b-ts@1 { ++ compatible = "ti,ads7846"; ++ reg = <1>; ++ ++ spi-max-frequency = <2000000>; ++ interrupts = <17 2>; /* high-to-low edge triggered */ ++ interrupt-parent = <&gpio>; ++ pendown-gpio = <&gpio 17 0>; ++ ti,x-plate-ohms = /bits/ 16 <100>; ++ ti,pressure-max = /bits/ 16 <255>; ++ }; ++ }; ++ }; ++ __overrides__ { ++ speed = <&hy28b>,"spi-max-frequency:0"; ++ rotate = <&hy28b>,"rotate:0"; ++ fps = <&hy28b>,"fps:0"; ++ debug = <&hy28b>,"debug:0"; ++ xohms = <&hy28b_ts>,"ti,x-plate-ohms;0"; ++ resetgpio = <&hy28b>,"reset-gpios:4", ++ <&hy28b_pins>, "brcm,pins:1"; ++ ledgpio = <&hy28b>,"led-gpios:4", ++ <&hy28b_pins>, "brcm,pins:2"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,28 @@ ++// Overlay for i2c_gpio bitbanging host bus. ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target-path = "/"; ++ __overlay__ { ++ i2c_gpio: i2c@0 { ++ compatible = "i2c-gpio"; ++ gpios = <&gpio 23 0 /* sda */ ++ &gpio 24 0 /* scl */ ++ >; ++ i2c-gpio,delay-us = <2>; /* ~100 kHz */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ }; ++ }; ++ __overrides__ { ++ i2c_gpio_sda = <&i2c_gpio>,"gpios:4"; ++ i2c_gpio_scl = <&i2c_gpio>,"gpios:16"; ++ i2c_gpio_delay_us = <&i2c_gpio>,"i2c-gpio,delay-us:0"; ++ }; ++}; ++ +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,55 @@ ++// Definitions for several I2C based Real Time Clocks ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&i2c_arm>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ ds1307: ds1307@68 { ++ compatible = "maxim,ds1307"; ++ reg = <0x68>; ++ status = "disable"; ++ }; ++ mcp7941x: mcp7941x@6f { ++ compatible = "microchip,mcp7941x"; ++ reg = <0x6f>; ++ status = "disable"; ++ }; ++ ds3231: ds3231@68 { ++ compatible = "maxim,ds3231"; ++ reg = <0x68>; ++ status = "disable"; ++ }; ++ pcf2127: pcf2127@51 { ++ compatible = "nxp,pcf2127"; ++ reg = <0x51>; ++ status = "disable"; ++ }; ++ pcf8523: pcf8523@68 { ++ compatible = "nxp,pcf8523"; ++ reg = <0x68>; ++ status = "disable"; ++ }; ++ pcf8563: pcf8563@51 { ++ compatible = "nxp,pcf8563"; ++ reg = <0x51>; ++ status = "disable"; ++ }; ++ }; ++ }; ++ __overrides__ { ++ ds1307 = <&ds1307>,"status"; ++ ds3231 = <&ds3231>,"status"; ++ mcp7941x = <&mcp7941x>,"status"; ++ pcf2127 = <&pcf2127>,"status"; ++ pcf8523 = <&pcf8523>,"status"; ++ pcf8563 = <&pcf8563>,"status"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/i2s-mmap-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/i2s-mmap-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/i2s-mmap-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/i2s-mmap-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,13 @@ ++/dts-v1/; ++/plugin/; ++ ++/{ ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&i2s>; ++ __overlay__ { ++ brcm,enable-mmap; ++ }; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/iqaudio-dac-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/iqaudio-dac-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/iqaudio-dac-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/iqaudio-dac-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,39 @@ ++// Definitions for IQaudIO DAC ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&sound>; ++ __overlay__ { ++ compatible = "iqaudio,iqaudio-dac"; ++ i2s-controller = <&i2s>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2s>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&i2c1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ pcm5122@4c { ++ #sound-dai-cells = <0>; ++ compatible = "ti,pcm5122"; ++ reg = <0x4c>; ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/iqaudio-dacplus-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/iqaudio-dacplus-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/iqaudio-dacplus-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/iqaudio-dacplus-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,39 @@ ++// Definitions for IQaudIO DAC+ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&sound>; ++ __overlay__ { ++ compatible = "iqaudio,iqaudio-dac"; ++ i2s-controller = <&i2s>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2s>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&i2c1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ pcm5122@4c { ++ #sound-dai-cells = <0>; ++ compatible = "ti,pcm5122"; ++ reg = <0x4c>; ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/lirc-rpi-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/lirc-rpi-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/lirc-rpi-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/lirc-rpi-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,57 @@ ++// Definitions for lirc-rpi module ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target-path = "/"; ++ __overlay__ { ++ lirc_rpi: lirc_rpi { ++ compatible = "rpi,lirc-rpi"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&lirc_pins>; ++ status = "okay"; ++ ++ // Override autodetection of IR receiver circuit ++ // (0 = active high, 1 = active low, -1 = no override ) ++ rpi,sense = <0xffffffff>; ++ ++ // Software carrier ++ // (0 = off, 1 = on) ++ rpi,softcarrier = <1>; ++ ++ // Invert output ++ // (0 = off, 1 = on) ++ rpi,invert = <0>; ++ ++ // Enable debugging messages ++ // (0 = off, 1 = on) ++ rpi,debug = <0>; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ lirc_pins: lirc_pins { ++ brcm,pins = <17 18>; ++ brcm,function = <1 0>; // out in ++ brcm,pull = <0 1>; // off down ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ gpio_out_pin = <&lirc_pins>,"brcm,pins:0"; ++ gpio_in_pin = <&lirc_pins>,"brcm,pins:4"; ++ gpio_in_pull = <&lirc_pins>,"brcm,pull:4"; ++ ++ sense = <&lirc_rpi>,"rpi,sense:0"; ++ softcarrier = <&lirc_rpi>,"rpi,softcarrier:0"; ++ invert = <&lirc_rpi>,"rpi,invert:0"; ++ debug = <&lirc_rpi>,"rpi,debug:0"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/Makefile linux-rpi/arch/arm/boot/dts/overlays/Makefile +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/Makefile 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,77 @@ ++ifeq ($(CONFIG_OF),y) ++ ++# Overlays for the Raspberry Pi platform ++ ++ifeq ($(CONFIG_BCM2708_DT),y) ++ RPI_DT_OVERLAYS=y ++endif ++ifeq ($(CONFIG_BCM2709_DT),y) ++ RPI_DT_OVERLAYS=y ++endif ++ifeq ($(CONFIG_ARCH_BCM2835),y) ++ RPI_DT_OVERLAYS=y ++endif ++ ++dtb-$(RPI_DT_OVERLAYS) += ads7846-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += at86rf233-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += bmp085_i2c-sensor-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += dht11-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += enc28j60-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += gpio-ir-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += gpio-poweroff-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += hifiberry-amp-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += hifiberry-dac-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += hifiberry-dacplus-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += hifiberry-digi-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += hy28a-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += hy28b-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += i2c-rtc-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += i2c-gpio-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += i2s-mmap-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += iqaudio-dac-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += iqaudio-dacplus-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += lirc-rpi-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += mcp2515-can0-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += mcp2515-can1-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += mmc-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += mz61581-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += piscreen-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += piscreen2r-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += pitft28-capacitive-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += pitft28-resistive-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += pps-gpio-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += pwm-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += pwm-2chan-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += raspidac3-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += rpi-backlight-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += rpi-dac-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += rpi-display-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += rpi-ft5406-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += rpi-proto-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += rpi-sense-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += sdhost-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += sdio-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += smi-dev-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += smi-nand-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += smi-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += spi-bcm2708-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += spi-bcm2835-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += spi-dma-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += tinylcd35-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += uart1-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += vga666-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += w1-gpio-overlay.dtb ++dtb-$(RPI_DT_OVERLAYS) += w1-gpio-pullup-overlay.dtb ++ ++targets += dtbs dtbs_install ++targets += $(dtb-y) ++ ++endif ++ ++always := $(dtb-y) ++clean-files := *.dtb ++ ++# Enable fixups to support overlays on BCM2708 platforms ++ifeq ($(RPI_DT_OVERLAYS),y) ++ DTC_FLAGS ?= -@ ++endif +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/mcp2515-can0-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/mcp2515-can0-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/mcp2515-can0-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/mcp2515-can0-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,69 @@ ++/* ++ * Device tree overlay for mcp251x/can0 on spi0.0 ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835", "brcm,bcm2836", "brcm,bcm2708", "brcm,bcm2709"; ++ /* disable spi-dev for spi0.0 */ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ spidev@0{ ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ /* the interrupt pin of the can-controller */ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ can0_pins: can0_pins { ++ brcm,pins = <25>; ++ brcm,function = <0>; /* input */ ++ }; ++ }; ++ }; ++ ++ /* the clock/oscillator of the can-controller */ ++ fragment@2 { ++ target-path = "/clocks"; ++ __overlay__ { ++ /* external oscillator of mcp2515 on SPI0.0 */ ++ can0_osc: can0_osc { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <16000000>; ++ }; ++ }; ++ }; ++ ++ /* the spi config of the can-controller itself binding everything together */ ++ fragment@3 { ++ target = <&spi0>; ++ __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ can0: mcp2515@0 { ++ reg = <0>; ++ compatible = "microchip,mcp2515"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&can0_pins>; ++ spi-max-frequency = <10000000>; ++ interrupt-parent = <&gpio>; ++ interrupts = <25 0x2>; ++ clocks = <&can0_osc>; ++ }; ++ }; ++ }; ++ __overrides__ { ++ oscillator = <&can0_osc>,"clock-frequency:0"; ++ spimaxfrequency = <&can0>,"spi-max-frequency:0"; ++ interrupt = <&can0_pins>,"brcm,pins:0",<&can0>,"interrupts:0"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/mcp2515-can1-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/mcp2515-can1-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/mcp2515-can1-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/mcp2515-can1-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,69 @@ ++/* ++ * Device tree overlay for mcp251x/can1 on spi0.1 edited by petit_miner ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835", "brcm,bcm2836", "brcm,bcm2708", "brcm,bcm2709"; ++ /* disable spi-dev for spi0.1 */ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ spidev@1{ ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ /* the interrupt pin of the can-controller */ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ can1_pins: can1_pins { ++ brcm,pins = <25>; ++ brcm,function = <0>; /* input */ ++ }; ++ }; ++ }; ++ ++ /* the clock/oscillator of the can-controller */ ++ fragment@2 { ++ target-path = "/clocks"; ++ __overlay__ { ++ /* external oscillator of mcp2515 on spi0.1 */ ++ can1_osc: can1_osc { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <16000000>; ++ }; ++ }; ++ }; ++ ++ /* the spi config of the can-controller itself binding everything together */ ++ fragment@3 { ++ target = <&spi0>; ++ __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ can1: mcp2515@1 { ++ reg = <1>; ++ compatible = "microchip,mcp2515"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&can1_pins>; ++ spi-max-frequency = <10000000>; ++ interrupt-parent = <&gpio>; ++ interrupts = <25 0x2>; ++ clocks = <&can1_osc>; ++ }; ++ }; ++ }; ++ __overrides__ { ++ oscillator = <&can1_osc>,"clock-frequency:0"; ++ spimaxfrequency = <&can1>,"spi-max-frequency:0"; ++ interrupt = <&can1_pins>,"brcm,pins:0",<&can1>,"interrupts:0"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/mmc-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/mmc-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/mmc-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/mmc-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,19 @@ ++/dts-v1/; ++/plugin/; ++ ++/{ ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&mmc>; ++ ++ frag0: __overlay__ { ++ brcm,overclock-50 = <0>; ++ }; ++ }; ++ ++ __overrides__ { ++ overclock_50 = <&frag0>,"brcm,overclock-50:0"; ++ force_pio = <&frag0>,"brcm,force-pio?"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/mz61581-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/mz61581-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/mz61581-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/mz61581-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,111 @@ ++/* ++ * Device Tree overlay for MZ61581-PI-EXT 2014.12.28 by Tontec ++ * ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709"; ++ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ ++ spidev@0{ ++ status = "disabled"; ++ }; ++ ++ spidev@1{ ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ mz61581_pins: mz61581_pins { ++ brcm,pins = <4 15 18 25>; ++ brcm,function = <0 1 1 1>; /* in out out out */ ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi0>; ++ __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ mz61581: mz61581@0{ ++ compatible = "samsung,s6d02a1"; ++ reg = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mz61581_pins>; ++ ++ spi-max-frequency = <128000000>; ++ spi-cpol; ++ spi-cpha; ++ ++ width = <320>; ++ height = <480>; ++ rotate = <270>; ++ bgr; ++ fps = <30>; ++ buswidth = <8>; ++ txbuflen = <32768>; ++ ++ reset-gpios = <&gpio 15 0>; ++ dc-gpios = <&gpio 25 0>; ++ led-gpios = <&gpio 18 0>; ++ ++ init = <0x10000b0 00 ++ 0x1000011 ++ 0x20000ff ++ 0x10000b3 0x02 0x00 0x00 0x00 ++ 0x10000c0 0x13 0x3b 0x00 0x02 0x00 0x01 0x00 0x43 ++ 0x10000c1 0x08 0x16 0x08 0x08 ++ 0x10000c4 0x11 0x07 0x03 0x03 ++ 0x10000c6 0x00 ++ 0x10000c8 0x03 0x03 0x13 0x5c 0x03 0x07 0x14 0x08 0x00 0x21 0x08 0x14 0x07 0x53 0x0c 0x13 0x03 0x03 0x21 0x00 ++ 0x1000035 0x00 ++ 0x1000036 0xa0 ++ 0x100003a 0x55 ++ 0x1000044 0x00 0x01 ++ 0x10000d0 0x07 0x07 0x1d 0x03 ++ 0x10000d1 0x03 0x30 0x10 ++ 0x10000d2 0x03 0x14 0x04 ++ 0x1000029 ++ 0x100002c>; ++ ++ /* This is a workaround to make sure the init sequence slows down and doesn't fail */ ++ debug = <3>; ++ }; ++ ++ mz61581_ts: mz61581_ts@1 { ++ compatible = "ti,ads7846"; ++ reg = <1>; ++ ++ spi-max-frequency = <2000000>; ++ interrupts = <4 2>; /* high-to-low edge triggered */ ++ interrupt-parent = <&gpio>; ++ pendown-gpio = <&gpio 4 0>; ++ ++ ti,x-plate-ohms = /bits/ 16 <60>; ++ ti,pressure-max = /bits/ 16 <255>; ++ }; ++ }; ++ }; ++ __overrides__ { ++ speed = <&mz61581>, "spi-max-frequency:0"; ++ rotate = <&mz61581>, "rotate:0"; ++ fps = <&mz61581>, "fps:0"; ++ txbuflen = <&mz61581>, "txbuflen:0"; ++ debug = <&mz61581>, "debug:0"; ++ xohms = <&mz61581_ts>,"ti,x-plate-ohms;0"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/piscreen2r-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/piscreen2r-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/piscreen2r-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/piscreen2r-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,100 @@ ++ /* ++ * Device Tree overlay for PiScreen2 3.5" TFT with resistive touch by Ozzmaker.com ++ * ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709"; ++ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ ++ spidev@0{ ++ status = "disabled"; ++ }; ++ ++ spidev@1{ ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ piscreen2_pins: piscreen2_pins { ++ brcm,pins = <17 25 24 22>; ++ brcm,function = <0 1 1 1>; /* in out out out */ ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi0>; ++ __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ piscreen2: piscreen2@0{ ++ compatible = "ilitek,ili9486"; ++ reg = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&piscreen2_pins>; ++ bgr; ++ spi-max-frequency = <64000000>; ++ rotate = <90>; ++ fps = <30>; ++ buswidth = <8>; ++ regwidth = <16>; ++ txbuflen = <32768>; ++ reset-gpios = <&gpio 25 0>; ++ dc-gpios = <&gpio 24 0>; ++ led-gpios = <&gpio 22 1>; ++ debug = <0>; ++ ++ init = <0x10000b0 0x00 ++ 0x1000011 ++ 0x20000ff ++ 0x100003a 0x55 ++ 0x1000036 0x28 ++ 0x10000c0 0x11 0x09 ++ 0x10000c1 0x41 ++ 0x10000c5 0x00 0x00 0x00 0x00 ++ 0x10000b6 0x00 0x02 ++ 0x10000f7 0xa9 0x51 0x2c 0x2 ++ 0x10000be 0x00 0x04 ++ 0x10000e9 0x00 ++ 0x1000011 ++ 0x1000029>; ++ ++ }; ++ ++ piscreen2_ts: piscreen2-ts@1 { ++ compatible = "ti,ads7846"; ++ reg = <1>; ++ ++ spi-max-frequency = <2000000>; ++ interrupts = <17 2>; /* high-to-low edge triggered */ ++ interrupt-parent = <&gpio>; ++ pendown-gpio = <&gpio 17 0>; ++ ti,swap-xy; ++ ti,x-plate-ohms = /bits/ 16 <100>; ++ ti,pressure-max = /bits/ 16 <255>; ++ }; ++ }; ++ }; ++ __overrides__ { ++ speed = <&piscreen2>,"spi-max-frequency:0"; ++ rotate = <&piscreen2>,"rotate:0"; ++ fps = <&piscreen2>,"fps:0"; ++ debug = <&piscreen2>,"debug:0"; ++ xohms = <&piscreen2_ts>,"ti,x-plate-ohms;0"; ++ }; ++}; ++ +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/piscreen-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/piscreen-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/piscreen-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/piscreen-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,96 @@ ++/* ++ * Device Tree overlay for PiScreen 3.5" display shield by Ozzmaker ++ * ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709"; ++ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ ++ spidev@0{ ++ status = "disabled"; ++ }; ++ ++ spidev@1{ ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ piscreen_pins: piscreen_pins { ++ brcm,pins = <17 25 24 22>; ++ brcm,function = <0 1 1 1>; /* in out out out */ ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi0>; ++ __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ piscreen: piscreen@0{ ++ compatible = "ilitek,ili9486"; ++ reg = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&piscreen_pins>; ++ ++ spi-max-frequency = <24000000>; ++ rotate = <270>; ++ bgr; ++ fps = <30>; ++ buswidth = <8>; ++ regwidth = <16>; ++ reset-gpios = <&gpio 25 0>; ++ dc-gpios = <&gpio 24 0>; ++ led-gpios = <&gpio 22 1>; ++ debug = <0>; ++ ++ init = <0x10000b0 0x00 ++ 0x1000011 ++ 0x20000ff ++ 0x100003a 0x55 ++ 0x1000036 0x28 ++ 0x10000c2 0x44 ++ 0x10000c5 0x00 0x00 0x00 0x00 ++ 0x10000e0 0x0f 0x1f 0x1c 0x0c 0x0f 0x08 0x48 0x98 0x37 0x0a 0x13 0x04 0x11 0x0d 0x00 ++ 0x10000e1 0x0f 0x32 0x2e 0x0b 0x0d 0x05 0x47 0x75 0x37 0x06 0x10 0x03 0x24 0x20 0x00 ++ 0x10000e2 0x0f 0x32 0x2e 0x0b 0x0d 0x05 0x47 0x75 0x37 0x06 0x10 0x03 0x24 0x20 0x00 ++ 0x1000011 ++ 0x1000029>; ++ }; ++ ++ piscreen_ts: piscreen-ts@1 { ++ compatible = "ti,ads7846"; ++ reg = <1>; ++ ++ spi-max-frequency = <2000000>; ++ interrupts = <17 2>; /* high-to-low edge triggered */ ++ interrupt-parent = <&gpio>; ++ pendown-gpio = <&gpio 17 0>; ++ ti,swap-xy; ++ ti,x-plate-ohms = /bits/ 16 <100>; ++ ti,pressure-max = /bits/ 16 <255>; ++ }; ++ }; ++ }; ++ __overrides__ { ++ speed = <&piscreen>,"spi-max-frequency:0"; ++ rotate = <&piscreen>,"rotate:0"; ++ fps = <&piscreen>,"fps:0"; ++ debug = <&piscreen>,"debug:0"; ++ xohms = <&piscreen_ts>,"ti,x-plate-ohms;0"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/pitft28-capacitive-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/pitft28-capacitive-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/pitft28-capacitive-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/pitft28-capacitive-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,88 @@ ++/* ++ * Device Tree overlay for Adafruit PiTFT 2.8" capacitive touch screen ++ * ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709"; ++ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ ++ spidev@0{ ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ pitft_pins: pitft_pins { ++ brcm,pins = <24 25>; ++ brcm,function = <0 1>; /* in out */ ++ brcm,pull = <2 0>; /* pullup none */ ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi0>; ++ __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ pitft: pitft@0{ ++ compatible = "ilitek,ili9340"; ++ reg = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pitft_pins>; ++ ++ spi-max-frequency = <32000000>; ++ rotate = <90>; ++ fps = <25>; ++ bgr; ++ buswidth = <8>; ++ dc-gpios = <&gpio 25 0>; ++ debug = <0>; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&i2c1>; ++ __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ ft6236: ft6236@38 { ++ compatible = "focaltech,ft6236"; ++ reg = <0x38>; ++ ++ interrupt-parent = <&gpio>; ++ interrupts = <24 2>; ++ touchscreen-size-x = <240>; ++ touchscreen-size-y = <320>; ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ speed = <&pitft>,"spi-max-frequency:0"; ++ rotate = <&pitft>,"rotate:0"; ++ fps = <&pitft>,"fps:0"; ++ debug = <&pitft>,"debug:0"; ++ touch-sizex = <&ft6236>,"touchscreen-size-x?"; ++ touch-sizey = <&ft6236>,"touchscreen-size-y?"; ++ touch-invx = <&ft6236>,"touchscreen-inverted-x?"; ++ touch-invy = <&ft6236>,"touchscreen-inverted-y?"; ++ touch-swapxy = <&ft6236>,"touchscreen-swapped-x-y?"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/pitft28-resistive-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/pitft28-resistive-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/pitft28-resistive-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/pitft28-resistive-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,115 @@ ++/* ++ * Device Tree overlay for Adafruit PiTFT 2.8" resistive touch screen ++ * ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709"; ++ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ ++ spidev@0{ ++ status = "disabled"; ++ }; ++ ++ spidev@1{ ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ pitft_pins: pitft_pins { ++ brcm,pins = <24 25>; ++ brcm,function = <0 1>; /* in out */ ++ brcm,pull = <2 0>; /* pullup none */ ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi0>; ++ __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ pitft: pitft@0{ ++ compatible = "ilitek,ili9340"; ++ reg = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pitft_pins>; ++ ++ spi-max-frequency = <32000000>; ++ rotate = <90>; ++ fps = <25>; ++ bgr; ++ buswidth = <8>; ++ dc-gpios = <&gpio 25 0>; ++ debug = <0>; ++ }; ++ ++ pitft_ts@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stmpe610"; ++ reg = <1>; ++ ++ spi-max-frequency = <500000>; ++ irq-gpio = <&gpio 24 0x2>; /* IRQF_TRIGGER_FALLING */ ++ interrupts = <24 2>; /* high-to-low edge triggered */ ++ interrupt-parent = <&gpio>; ++ interrupt-controller; ++ ++ stmpe_touchscreen { ++ compatible = "st,stmpe-ts"; ++ st,sample-time = <4>; ++ st,mod-12b = <1>; ++ st,ref-sel = <0>; ++ st,adc-freq = <2>; ++ st,ave-ctrl = <3>; ++ st,touch-det-delay = <4>; ++ st,settling = <2>; ++ st,fraction-z = <7>; ++ st,i-drive = <0>; ++ }; ++ ++ stmpe_gpio: stmpe_gpio { ++ #gpio-cells = <2>; ++ compatible = "st,stmpe-gpio"; ++ /* ++ * only GPIO2 is wired/available ++ * and it is wired to the backlight ++ */ ++ st,norequest-mask = <0x7b>; ++ }; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target-path = "/soc"; ++ __overlay__ { ++ backlight { ++ compatible = "gpio-backlight"; ++ gpios = <&stmpe_gpio 2 0>; ++ default-on; ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ speed = <&pitft>,"spi-max-frequency:0"; ++ rotate = <&pitft>,"rotate:0"; ++ fps = <&pitft>,"fps:0"; ++ debug = <&pitft>,"debug:0"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/pps-gpio-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/pps-gpio-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/pps-gpio-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/pps-gpio-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,34 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ fragment@0 { ++ target-path = "/"; ++ __overlay__ { ++ pps: pps { ++ compatible = "pps-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pps_pins>; ++ gpios = <&gpio 18 0>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ pps_pins: pps_pins { ++ brcm,pins = <18>; ++ brcm,function = <0>; // in ++ brcm,pull = <0>; // off ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ gpiopin = <&pps>,"gpios:4", ++ <&pps_pins>,"brcm,pins:0"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/pwm-2chan-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/pwm-2chan-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/pwm-2chan-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/pwm-2chan-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,46 @@ ++/dts-v1/; ++/plugin/; ++ ++/* ++This is the 2-channel overlay - only use it if you need both channels. ++ ++Legal pin,function combinations for each channel: ++ PWM0: 12,4(Alt0) 18,2(Alt5) 40,4(Alt0) 52,5(Alt1) ++ PWM1: 13,4(Alt0) 19,2(Alt5) 41,4(Alt0) 45,4(Alt0) 53,5(Alt1) ++ ++N.B.: ++ 1) Pin 18 is the only one available on all platforms, and ++ it is the one used by the I2S audio interface. ++ Pins 12 and 13 might be better choices on an A+, B+ or Pi2. ++ 2) The onboard analogue audio output uses both PWM channels. ++ 3) So be careful mixing audio and PWM. ++*/ ++ ++/ { ++ fragment@0 { ++ target = <&gpio>; ++ __overlay__ { ++ pwm_pins: pwm_pins { ++ brcm,pins = <18 19>; ++ brcm,function = <2 2>; /* Alt5 */ ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pwm>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm_pins>; ++ status = "okay"; ++ }; ++ }; ++ ++ __overrides__ { ++ pin = <&pwm_pins>,"brcm,pins:0"; ++ pin2 = <&pwm_pins>,"brcm,pins:4"; ++ func = <&pwm_pins>,"brcm,function:0"; ++ func2 = <&pwm_pins>,"brcm,function:4"; ++ clock = <&clk_pwm>,"clock-frequency:0"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/pwm-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/pwm-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/pwm-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/pwm-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,42 @@ ++/dts-v1/; ++/plugin/; ++ ++/* ++Legal pin,function combinations for each channel: ++ PWM0: 12,4(Alt0) 18,2(Alt5) 40,4(Alt0) 52,5(Alt1) ++ PWM1: 13,4(Alt0) 19,2(Alt5) 41,4(Alt0) 45,4(Alt0) 53,5(Alt1) ++ ++N.B.: ++ 1) Pin 18 is the only one available on all platforms, and ++ it is the one used by the I2S audio interface. ++ Pins 12 and 13 might be better choices on an A+, B+ or Pi2. ++ 2) The onboard analogue audio output uses both PWM channels. ++ 3) So be careful mixing audio and PWM. ++*/ ++ ++/ { ++ fragment@0 { ++ target = <&gpio>; ++ __overlay__ { ++ pwm_pins: pwm_pins { ++ brcm,pins = <18>; ++ brcm,function = <2>; /* Alt5 */ ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pwm>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm_pins>; ++ status = "okay"; ++ }; ++ }; ++ ++ __overrides__ { ++ pin = <&pwm_pins>,"brcm,pins:0"; ++ func = <&pwm_pins>,"brcm,function:0"; ++ clock = <&clk_pwm>,"clock-frequency:0"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/raspidac3-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/raspidac3-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/raspidac3-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/raspidac3-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,45 @@ ++// Definitions for RaspiDACv3 ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&sound>; ++ __overlay__ { ++ compatible = "jg,raspidacv3"; ++ i2s-controller = <&i2s>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2s>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&i2c1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ pcm5122@4c { ++ #sound-dai-cells = <0>; ++ compatible = "ti,pcm5122"; ++ reg = <0x4c>; ++ status = "okay"; ++ }; ++ ++ tpa6130a2: tpa6130a2@60 { ++ compatible = "ti,tpa6130a2"; ++ reg = <0x60>; ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/README linux-rpi/arch/arm/boot/dts/overlays/README +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/README 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/README 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,742 @@ ++Introduction ++============ ++ ++This directory contains Device Tree overlays. Device Tree makes it possible ++to support many hardware configurations with a single kernel and without the ++need to explicitly load or blacklist kernel modules. Note that this isn't a ++"pure" Device Tree configuration (c.f. MACH_BCM2835) - some on-board devices ++are still configured by the board support code, but the intention is to ++eventually reach that goal. ++ ++On Raspberry Pi, Device Tree usage is controlled from /boot/config.txt. By ++default, the Raspberry Pi kernel boots with device tree enabled. You can ++completely disable DT usage (for now) by adding: ++ ++ device_tree= ++ ++to your config.txt, which should cause your Pi to revert to the old way of ++doing things after a reboot. ++ ++In /boot you will find a .dtb for each base platform. This describes the ++hardware that is part of the Raspberry Pi board. The loader (start.elf and its ++siblings) selects the .dtb file appropriate for the platform by name, and reads ++it into memory. At this point, all of the optional interfaces (i2c, i2s, spi) ++are disabled, but they can be enabled using Device Tree parameters: ++ ++ dtparam=i2c=on,i2s=on,spi=on ++ ++However, this shouldn't be necessary in many use cases because loading an ++overlay that requires one of those interfaces will cause it to be enabled ++automatically, and it is advisable to only enable interfaces if they are ++needed. ++ ++Configuring additional, optional hardware is done using Device Tree overlays ++(see below). ++ ++raspi-config ++============ ++ ++The Advanced Options section of the raspi-config utility can enable and disable ++Device Tree use, as well as toggling the I2C and SPI interfaces. Note that it ++is possible to both enable an interface and blacklist the driver, if for some ++reason you should want to defer the loading. ++ ++Modules ++======= ++ ++As well as describing the hardware, Device Tree also gives enough information ++to allow suitable driver modules to be located and loaded, with the corollary ++that unneeded modules are not loaded. As a result it should be possible to ++remove lines from /etc/modules, and /etc/modprobe.d/raspi-blacklist.conf can ++have its contents deleted (or commented out). ++ ++Using Overlays ++============== ++ ++Overlays are loaded using the "dtoverlay" directive. As an example, consider the ++popular lirc-rpi module, the Linux Infrared Remote Control driver. In the ++pre-DT world this would be loaded from /etc/modules, with an explicit ++"modprobe lirc-rpi" command, or programmatically by lircd. With DT enabled, ++this becomes a line in config.txt: ++ ++ dtoverlay=lirc-rpi ++ ++This causes the file /boot/overlays/lirc-rpi-overlay.dtb to be loaded. By ++default it will use GPIOs 17 (out) and 18 (in), but this can be modified using ++DT parameters: ++ ++ dtoverlay=lirc-rpi,gpio_out_pin=17,gpio_in_pin=13 ++ ++Parameters always have default values, although in some cases (e.g. "w1-gpio") ++it is necessary to provided multiple overlays in order to get the desired ++behaviour. See the list of overlays below for a description of the parameters ++and their defaults. ++ ++The Overlay and Parameter Reference ++=================================== ++ ++N.B. When editing this file, please preserve the indentation levels to make it ++simple to parse programmatically. NO HARD TABS. ++ ++ ++Name: ++Info: Configures the base Raspberry Pi hardware ++Load: ++Params: ++ audio Set to "on" to enable the onboard ALSA audio ++ interface (default "off") ++ ++ i2c_arm Set to "on" to enable the ARM's i2c interface ++ (default "off") ++ ++ i2c_vc Set to "on" to enable the i2c interface ++ usually reserved for the VideoCore processor ++ (default "off") ++ ++ i2c An alias for i2c_arm ++ ++ i2c_arm_baudrate Set the baudrate of the ARM's i2c interface ++ (default "100000") ++ ++ i2c_vc_baudrate Set the baudrate of the VideoCore i2c interface ++ (default "100000") ++ ++ i2c_baudrate An alias for i2c_arm_baudrate ++ ++ i2s Set to "on" to enable the i2s interface ++ (default "off") ++ ++ spi Set to "on" to enable the spi interfaces ++ (default "off") ++ ++ random Set to "on" to enable the hardware random ++ number generator (default "off") ++ ++ uart0 Set to "off" to disable uart0 (default "on") ++ ++ watchdog Set to "on" to enable the hardware watchdog ++ (default "off") ++ ++ act_led_trigger Choose which activity the LED tracks. ++ Use "heartbeat" for a nice load indicator. ++ (default "mmc") ++ ++ act_led_activelow Set to "on" to invert the sense of the LED ++ (default "off") ++ ++ act_led_gpio Set which GPIO to use for the activity LED ++ (in case you want to connect it to an external ++ device) ++ (default "16" on a non-Plus board, "47" on a ++ Plus or Pi 2) ++ ++ pwr_led_trigger ++ pwr_led_activelow ++ pwr_led_gpio ++ As for act_led_*, but using the PWR LED. ++ Not available on Model A/B boards. ++ ++ N.B. It is recommended to only enable those interfaces that are needed. ++ Leaving all interfaces enabled can lead to unwanted behaviour (i2c_vc ++ interfering with Pi Camera, I2S and SPI hogging GPIO pins, etc.) ++ Note also that i2c, i2c_arm and i2c_vc are aliases for the physical ++ interfaces i2c0 and i2c1. Use of the numeric variants is still possible ++ but deprecated because the ARM/VC assignments differ between board ++ revisions. The same board-specific mapping applies to i2c_baudrate, ++ and the other i2c baudrate parameters. ++ ++ ++Name: ads7846 ++Info: ADS7846 Touch controller ++Load: dtoverlay=ads7846,= ++Params: cs SPI bus Chip Select (default 1) ++ speed SPI bus speed (default 2MHz, max 3.25MHz) ++ penirq GPIO used for PENIRQ. REQUIRED ++ penirq_pull Set GPIO pull (default 0=none, 2=pullup) ++ swapxy Swap x and y axis ++ xmin Minimum value on the X axis (default 0) ++ ymin Minimum value on the Y axis (default 0) ++ xmax Maximum value on the X axis (default 4095) ++ ymax Maximum value on the Y axis (default 4095) ++ pmin Minimum reported pressure value (default 0) ++ pmax Maximum reported pressure value (default 65535) ++ xohms Touchpanel sensitivity (X-plate resistance) ++ (default 400) ++ ++ penirq is required and usually xohms (60-100) has to be set as well. ++ Apart from that, pmax (255) and swapxy are also common. ++ The rest of the calibration can be done with xinput-calibrator. ++ See: github.com/notro/fbtft/wiki/FBTFT-on-Raspian ++ Device Tree binding document: ++ www.kernel.org/doc/Documentation/devicetree/bindings/input/ads7846.txt ++ ++ ++Name: at86rf233 ++Info: Configures the Atmel AT86RF233 802.15.4 low-power WPAN transceiver, ++ connected to spi0.0 ++Load: dtoverlay=at86rf233,= ++Params: interrupt GPIO used for INT (default 23) ++ reset GPIO used for Reset (default 24) ++ sleep GPIO used for Sleep (default 25) ++ speed SPI bus speed in Hz (default 6000000) ++ trim Fine tuning of the internal capacitance ++ arrays (0=+0pF, 15=+4.5pF, default 15) ++ ++ ++Name: bmp085_i2c-sensor ++Info: Configures the BMP085/BMP180 digital barometric pressure and temperature ++ sensors from Bosch Sensortec ++Load: dtoverlay=bmp085_i2c-sensor ++Params: ++ ++ ++Name: dht11 ++Info: Overlay for the DHT11/DHT21/DHT22 humidity/temperature sensors ++ Also sometimes found with the part number(s) AM230x. ++Load: dtoverlay=dht11,= ++Params: gpiopin GPIO connected to the sensor's DATA output. ++ (default 4) ++ ++ ++[ The ds1307-rtc overlay has been deleted. See i2c-rtc. ] ++ ++ ++Name: enc28j60 ++Info: Overlay for the Microchip ENC28J60 Ethernet Controller (SPI) ++Load: dtoverlay=enc28j60,= ++Params: int_pin GPIO used for INT (default 25) ++ ++ speed SPI bus speed (default 12000000) ++ ++ ++Name: gpio-ir ++Info: Use GPIO pin as rc-core style infrared receiver input. The rc-core- ++ based gpio_ir_recv driver maps received keys directly to a ++ /dev/input/event* device, all decoding is done by the kernel - LIRC is ++ not required! The key mapping and other decoding parameters can be ++ configured by "ir-keytable" tool. ++Load: dtoverlay=gpio-ir,= ++Params: gpio_pin Input pin number. Default is 18. ++ ++ gpio_pull Desired pull-up/down state (off, down, up) ++ Default is "down". ++ ++ rc-map-name Default rc keymap (can also be changed by ++ ir-keytable), defaults to "rc-rc6-mce" ++ ++ ++Name: gpio-poweroff ++Info: Drives a GPIO high or low on reboot ++Load: dtoverlay=gpio-poweroff,= ++Params: gpiopin GPIO for signalling (default 26) ++ ++ active_low Set if the power control device requires a ++ high->low transition to trigger a power-down. ++ Note that this will require the support of a ++ custom dt-blob.bin to prevent a power-down ++ during the boot process, and that a reboot ++ will also cause the pin to go low. ++ ++ ++Name: hifiberry-amp ++Info: Configures the HifiBerry Amp and Amp+ audio cards ++Load: dtoverlay=hifiberry-amp ++Params: ++ ++ ++Name: hifiberry-dac ++Info: Configures the HifiBerry DAC audio card ++Load: dtoverlay=hifiberry-dac ++Params: ++ ++ ++Name: hifiberry-dacplus ++Info: Configures the HifiBerry DAC+ audio card ++Load: dtoverlay=hifiberry-dacplus ++Params: ++ ++ ++Name: hifiberry-digi ++Info: Configures the HifiBerry Digi audio card ++Load: dtoverlay=hifiberry-digi ++Params: ++ ++ ++Name: hy28a ++Info: HY28A - 2.8" TFT LCD Display Module by HAOYU Electronics ++ Default values match Texy's display shield ++Load: dtoverlay=hy28a,= ++Params: speed Display SPI bus speed ++ ++ rotate Display rotation {0,90,180,270} ++ ++ fps Delay between frame updates ++ ++ debug Debug output level {0-7} ++ ++ xohms Touchpanel sensitivity (X-plate resistance) ++ ++ resetgpio GPIO used to reset controller ++ ++ ledgpio GPIO used to control backlight ++ ++ ++Name: hy28b ++Info: HY28B - 2.8" TFT LCD Display Module by HAOYU Electronics ++ Default values match Texy's display shield ++Load: dtoverlay=hy28b,= ++Params: speed Display SPI bus speed ++ ++ rotate Display rotation {0,90,180,270} ++ ++ fps Delay between frame updates ++ ++ debug Debug output level {0-7} ++ ++ xohms Touchpanel sensitivity (X-plate resistance) ++ ++ resetgpio GPIO used to reset controller ++ ++ ledgpio GPIO used to control backlight ++ ++ ++Name: i2c-gpio ++Info: Adds support for software i2c controller on gpio pins ++Load: dtoverlay=i2c-gpio,= ++Params: i2c_gpio_sda GPIO used for I2C data (default "23") ++ ++ i2c_gpio_scl GPIO used for I2C clock (default "24") ++ ++ i2c_gpio_delay_us Clock delay in microseconds ++ (default "2" = ~100kHz) ++ ++ ++Name: i2c-rtc ++Info: Adds support for a number of I2C Real Time Clock devices ++Load: dtoverlay=i2c-rtc,= ++Params: ds1307 Select the DS1307 device ++ ++ ds3231 Select the DS3231 device ++ ++ mcp7941x Select the MCP7941x device ++ ++ pcf2127 Select the PCF2127 device ++ ++ pcf8523 Select the PCF8523 device ++ ++ pcf8563 Select the PCF8563 device ++ ++ ++Name: i2s-mmap ++Info: Enables mmap support in the bcm2708-i2s driver ++Load: dtoverlay=i2s-mmap ++Params: ++ ++ ++Name: iqaudio-dac ++Info: Configures the IQaudio DAC audio card ++Load: dtoverlay=iqaudio-dac ++Params: ++ ++ ++Name: iqaudio-dacplus ++Info: Configures the IQaudio DAC+ audio card ++Load: dtoverlay=iqaudio-dacplus ++Params: ++ ++ ++Name: lirc-rpi ++Info: Configures lirc-rpi (Linux Infrared Remote Control for Raspberry Pi) ++ Consult the module documentation for more details. ++Load: dtoverlay=lirc-rpi,= ++Params: gpio_out_pin GPIO for output (default "17") ++ ++ gpio_in_pin GPIO for input (default "18") ++ ++ gpio_in_pull Pull up/down/off on the input pin ++ (default "down") ++ ++ sense Override the IR receive auto-detection logic: ++ "0" = force active-high ++ "1" = force active-low ++ "-1" = use auto-detection ++ (default "-1") ++ ++ softcarrier Turn the software carrier "on" or "off" ++ (default "on") ++ ++ invert "on" = invert the output pin (default "off") ++ ++ debug "on" = enable additional debug messages ++ (default "off") ++ ++ ++Name: mcp2515-can0 ++Info: Configures the MCP2515 CAN controller on spi0.0 ++Load: dtoverlay=mcp2515-can0,= ++Params: oscillator Clock frequency for the CAN controller (Hz) ++ ++ spimaxfrequency Maximum SPI frequence (Hz) ++ ++ interrupt GPIO for interrupt signal ++ ++ ++Name: mcp2515-can1 ++Info: Configures the MCP2515 CAN controller on spi0.1 ++Load: dtoverlay=mcp2515-can1,= ++Params: oscillator Clock frequency for the CAN controller (Hz) ++ ++ spimaxfrequency Maximum SPI frequence (Hz) ++ ++ interrupt GPIO for interrupt signal ++ ++ ++Name: mmc ++Info: Selects the bcm2835-mmc SD/MMC driver, optionally with overclock ++Load: dtoverlay=mmc,= ++Params: overclock_50 Clock (in MHz) to use when the MMC framework ++ requests 50MHz ++ force_pio Disable DMA support ++ ++ ++Name: mz61581 ++Info: MZ61581 display by Tontec ++Load: dtoverlay=mz61581,= ++Params: speed Display SPI bus speed ++ ++ rotate Display rotation {0,90,180,270} ++ ++ fps Delay between frame updates ++ ++ txbuflen Transmit buffer length (default 32768) ++ ++ debug Debug output level {0-7} ++ ++ xohms Touchpanel sensitivity (X-plate resistance) ++ ++ ++[ The pcf2127-rtc overlay has been deleted. See i2c-rtc. ] ++ ++ ++[ The pcf8523-rtc overlay has been deleted. See i2c-rtc. ] ++ ++ ++[ The pcf8563-rtc overlay has been deleted. See i2c-rtc. ] ++ ++ ++Name: piscreen ++Info: PiScreen display by OzzMaker.com ++Load: dtoverlay=piscreen,= ++Params: speed Display SPI bus speed ++ ++ rotate Display rotation {0,90,180,270} ++ ++ fps Delay between frame updates ++ ++ debug Debug output level {0-7} ++ ++ xohms Touchpanel sensitivity (X-plate resistance) ++ ++ ++Name: piscreen2r ++Info: PiScreen 2 with resistive TP display by OzzMaker.com ++Load: dtoverlay=piscreen2r,= ++Params: speed Display SPI bus speed ++ ++ rotate Display rotation {0,90,180,270} ++ ++ fps Delay between frame updates ++ ++ debug Debug output level {0-7} ++ ++ xohms Touchpanel sensitivity (X-plate resistance) ++ ++ ++Name: pitft28-capacitive ++Info: Adafruit PiTFT 2.8" capacitive touch screen ++Load: dtoverlay=pitft28-capacitive,= ++Params: speed Display SPI bus speed ++ ++ rotate Display rotation {0,90,180,270} ++ ++ fps Delay between frame updates ++ ++ debug Debug output level {0-7} ++ ++ touch-sizex Touchscreen size x (default 240) ++ ++ touch-sizey Touchscreen size y (default 320) ++ ++ touch-invx Touchscreen inverted x axis ++ ++ touch-invy Touchscreen inverted y axis ++ ++ touch-swapxy Touchscreen swapped x y axis ++ ++ ++Name: pitft28-resistive ++Info: Adafruit PiTFT 2.8" resistive touch screen ++Load: dtoverlay=pitft28-resistive,= ++Params: speed Display SPI bus speed ++ ++ rotate Display rotation {0,90,180,270} ++ ++ fps Delay between frame updates ++ ++ debug Debug output level {0-7} ++ ++ ++Name: pps-gpio ++Info: Configures the pps-gpio (pulse-per-second time signal via GPIO). ++Load: dtoverlay=pps-gpio,= ++Params: gpiopin Input GPIO (default "18") ++ ++ ++Name: pwm ++Info: Configures a single PWM channel ++ Legal pin,function combinations for each channel: ++ PWM0: 12,4(Alt0) 18,2(Alt5) 40,4(Alt0) 52,5(Alt1) ++ PWM1: 13,4(Alt0) 19,2(Alt5) 41,4(Alt0) 45,4(Alt0) 53,5(Alt1) ++ N.B.: ++ 1) Pin 18 is the only one available on all platforms, and ++ it is the one used by the I2S audio interface. ++ Pins 12 and 13 might be better choices on an A+, B+ or Pi2. ++ 2) The onboard analogue audio output uses both PWM channels. ++ 3) So be careful mixing audio and PWM. ++ 4) Currently the clock must have been enabled and configured ++ by other means. ++Load: dtoverlay=pwm,= ++Params: pin Output pin (default 18) - see table ++ func Pin function (default 2 = Alt5) - see above ++ clock PWM clock frequency (informational) ++ ++ ++Name: pwm-2chan ++Info: Configures both PWM channels ++ Legal pin,function combinations for each channel: ++ PWM0: 12,4(Alt0) 18,2(Alt5) 40,4(Alt0) 52,5(Alt1) ++ PWM1: 13,4(Alt0) 19,2(Alt5) 41,4(Alt0) 45,4(Alt0) 53,5(Alt1) ++ N.B.: ++ 1) Pin 18 is the only one available on all platforms, and ++ it is the one used by the I2S audio interface. ++ Pins 12 and 13 might be better choices on an A+, B+ or Pi2. ++ 2) The onboard analogue audio output uses both PWM channels. ++ 3) So be careful mixing audio and PWM. ++ 4) Currently the clock must have been enabled and configured ++ by other means. ++Load: dtoverlay=pwm-2chan,= ++Params: pin Output pin (default 18) - see table ++ pin2 Output pin for other channel (default 19) ++ func Pin function (default 2 = Alt5) - see above ++ func2 Function for pin2 (default 2 = Alt5) ++ clock PWM clock frequency (informational) ++ ++ ++Name: raspidac3 ++Info: Configures the RaspiDAV Rev.3x audio card ++Load: dtoverlay=raspidac3 ++Params: ++ ++ ++Name: rpi-backlight ++Info: Raspberry Pi official display backlight driver ++Load: dtoverlay=rpi-backlight ++Params: ++ ++ ++Name: rpi-dac ++Info: Configures the RPi DAC audio card ++Load: dtoverlay=rpi-dac ++Params: ++ ++ ++Name: rpi-display ++Info: RPi-Display - 2.8" Touch Display by Watterott ++Load: dtoverlay=rpi-display,= ++Params: speed Display SPI bus speed ++ ++ rotate Display rotation {0,90,180,270} ++ ++ fps Delay between frame updates ++ ++ debug Debug output level {0-7} ++ ++ xohms Touchpanel sensitivity (X-plate resistance) ++ ++ ++Name: rpi-ft5406 ++Info: Official Raspberry Pi display touchscreen ++Load: dtoverlay=rpi-ft5406 ++Params: ++ ++ ++Name: rpi-proto ++Info: Configures the RPi Proto audio card ++Load: dtoverlay=rpi-proto ++Params: ++ ++ ++Name: rpi-sense ++Info: Raspberry Pi Sense HAT ++Load: dtoverlay=rpi-sense ++Params: ++ ++ ++Name: sdhost ++Info: Selects the bcm2835-sdhost SD/MMC driver, optionally with overclock ++Load: dtoverlay=sdhost,= ++Params: overclock_50 Clock (in MHz) to use when the MMC framework ++ requests 50MHz ++ ++ force_pio Disable DMA support (default off) ++ ++ pio_limit Number of blocks above which to use DMA ++ (default 1) ++ ++ debug Enable debug output (default off) ++ ++ ++Name: sdio ++Info: Selects the bcm2835-sdhost SD/MMC driver, optionally with overclock, ++ and enables SDIO via GPIOs 22-27. ++Load: dtoverlay=sdio,= ++Params: overclock_50 Clock (in MHz) to use when the MMC framework ++ requests 50MHz ++ ++ force_pio Disable DMA support (default off) ++ ++ pio_limit Number of blocks above which to use DMA ++ (default 1) ++ ++ debug Enable debug output (default off) ++ ++ poll_once Disable SDIO-device polling every second ++ (default on: polling once at boot-time) ++ ++ ++Name: smi ++Info: Enables the Secondary Memory Interface peripheral. Uses GPIOs 2-25! ++Load: dtoverlay=smi ++Params: ++ ++ ++Name: smi-dev ++Info: Enables the userspace interface for the SMI driver ++Load: dtoverlay=smi-dev ++Params: ++ ++ ++Name: smi-nand ++Info: Enables access to NAND flash via the SMI interface ++Load: dtoverlay=smi-nand ++Params: ++ ++ ++Name: spi-bcm2708 ++Info: Selects the bcm2708-spi SPI driver ++Load: dtoverlay=spi-bcm2708 ++Params: ++ ++ ++Name: spi-bcm2835 ++Info: Selects the bcm2835-spi SPI driver ++Load: dtoverlay=spi-bcm2835 ++Params: ++ ++ ++Name: spi-dma ++Info: enables dma modes for spi-bcm2835 ++Load: dtoverlay=spi-dma ++Params: ++ ++ ++Name: tinylcd35 ++Info: 3.5" Color TFT Display by www.tinylcd.com ++ Options: Touch, RTC, keypad ++Load: dtoverlay=tinylcd35,= ++Params: speed Display SPI bus speed ++ ++ rotate Display rotation {0,90,180,270} ++ ++ fps Delay between frame updates ++ ++ debug Debug output level {0-7} ++ ++ touch Enable touch panel ++ ++ touchgpio Touch controller IRQ GPIO ++ ++ xohms Touchpanel: Resistance of X-plate in ohms ++ ++ rtc-pcf PCF8563 Real Time Clock ++ ++ rtc-ds DS1307 Real Time Clock ++ ++ keypad Enable keypad ++ ++ Examples: ++ Display with touchpanel, PCF8563 RTC and keypad: ++ dtoverlay=tinylcd35,touch,rtc-pcf,keypad ++ Old touch display: ++ dtoverlay=tinylcd35,touch,touchgpio=3 ++ ++ ++Name: uart1 ++Info: Enable uart1 in place of uart0 ++Load: dtoverlay=uart1,= ++Params: txd1_pin GPIO pin for TXD1 (14, 32 or 40 - default 14) ++ ++ rxd1_pin GPIO pin for RXD1 (15, 33 or 41 - default 15) ++ ++ ++Name: vga666 ++Info: Overlay for the Fen Logic VGA666 board ++ This uses GPIOs 2-21 (so no I2C), and activates the output 2-3 seconds ++ after the kernel has started. ++Load: dtoverlay=vga666 ++Params: ++ ++ ++Name: w1-gpio ++Info: Configures the w1-gpio Onewire interface module. ++ Use this overlay if you *don't* need a GPIO to drive an external pullup. ++Load: dtoverlay=w1-gpio,= ++Params: gpiopin GPIO for I/O (default "4") ++ ++ pullup Non-zero, "on", or "y" to enable the parasitic ++ power (2-wire, power-on-data) feature ++ ++ ++Name: w1-gpio-pullup ++Info: Configures the w1-gpio Onewire interface module. ++ Use this overlay if you *do* need a GPIO to drive an external pullup. ++Load: dtoverlay=w1-gpio-pullup,= ++Params: gpiopin GPIO for I/O (default "4") ++ ++ pullup Non-zero, "on", or "y" to enable the parasitic ++ power (2-wire, power-on-data) feature ++ ++ extpullup GPIO for external pullup (default "5") ++ ++ ++Troubleshooting ++=============== ++ ++If you are experiencing problems that you think are DT-related, enable DT ++diagnostic output by adding this to /boot/config.txt: ++ ++ dtdebug=on ++ ++and rebooting. Then run: ++ ++ sudo vcdbg log msg ++ ++and look for relevant messages. ++ ++Further reading ++=============== ++ ++This is only meant to be a quick introduction to the subject of Device Tree on ++Raspberry Pi. There is a more complete explanation here: ++ ++http://www.raspberrypi.org/documentation/configuration/device-tree.md +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/rpi-backlight-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/rpi-backlight-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/rpi-backlight-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/rpi-backlight-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,21 @@ ++/* ++ * Devicetree overlay for mailbox-driven Raspberry Pi DSI Display ++ * backlight controller ++ */ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target-path = "/"; ++ __overlay__ { ++ rpi_backlight: rpi_backlight { ++ compatible = "raspberrypi,rpi-backlight"; ++ firmware = <&firmware>; ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/rpi-dac-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/rpi-dac-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/rpi-dac-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/rpi-dac-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,34 @@ ++// Definitions for RPi DAC ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&sound>; ++ __overlay__ { ++ compatible = "rpi,rpi-dac"; ++ i2s-controller = <&i2s>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2s>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target-path = "/"; ++ __overlay__ { ++ pcm1794a-codec { ++ #sound-dai-cells = <0>; ++ compatible = "ti,pcm1794a"; ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/rpi-display-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/rpi-display-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/rpi-display-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/rpi-display-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,82 @@ ++/* ++ * Device Tree overlay for rpi-display by Watterott ++ * ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709"; ++ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ ++ spidev@0{ ++ status = "disabled"; ++ }; ++ ++ spidev@1{ ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ rpi_display_pins: rpi_display_pins { ++ brcm,pins = <18 23 24 25>; ++ brcm,function = <1 1 1 0>; /* out out out in */ ++ brcm,pull = <0 0 0 2>; /* - - - up */ ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi0>; ++ __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ rpidisplay: rpi-display@0{ ++ compatible = "ilitek,ili9341"; ++ reg = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rpi_display_pins>; ++ ++ spi-max-frequency = <32000000>; ++ rotate = <270>; ++ bgr; ++ fps = <30>; ++ buswidth = <8>; ++ reset-gpios = <&gpio 23 0>; ++ dc-gpios = <&gpio 24 0>; ++ led-gpios = <&gpio 18 1>; ++ debug = <0>; ++ }; ++ ++ rpidisplay_ts: rpi-display-ts@1 { ++ compatible = "ti,ads7846"; ++ reg = <1>; ++ ++ spi-max-frequency = <2000000>; ++ interrupts = <25 2>; /* high-to-low edge triggered */ ++ interrupt-parent = <&gpio>; ++ pendown-gpio = <&gpio 25 0>; ++ ti,x-plate-ohms = /bits/ 16 <60>; ++ ti,pressure-max = /bits/ 16 <255>; ++ }; ++ }; ++ }; ++ __overrides__ { ++ speed = <&rpidisplay>,"spi-max-frequency:0"; ++ rotate = <&rpidisplay>,"rotate:0"; ++ fps = <&rpidisplay>,"fps:0"; ++ debug = <&rpidisplay>,"debug:0"; ++ xohms = <&rpidisplay_ts>,"ti,x-plate-ohms;0"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,17 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target-path = "/"; ++ __overlay__ { ++ rpi_ft5406: rpi_ft5406 { ++ compatible = "rpi,rpi-ft5406"; ++ firmware = <&firmware>; ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/rpi-proto-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/rpi-proto-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/rpi-proto-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/rpi-proto-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,39 @@ ++// Definitions for Rpi-Proto ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&sound>; ++ __overlay__ { ++ compatible = "rpi,rpi-proto"; ++ i2s-controller = <&i2s>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2s>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&i2c1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ wm8731@1a { ++ #sound-dai-cells = <0>; ++ compatible = "wlf,wm8731"; ++ reg = <0x1a>; ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/rpi-sense-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/rpi-sense-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/rpi-sense-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/rpi-sense-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,47 @@ ++// rpi-sense HAT ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708", "brcm,bcm2709"; ++ ++ fragment@0 { ++ target = <&i2c1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ rpi-sense@46 { ++ compatible = "rpi,rpi-sense"; ++ reg = <0x46>; ++ keys-int-gpios = <&gpio 23 1>; ++ status = "okay"; ++ }; ++ ++ lsm9ds1-magn@1c { ++ compatible = "st,lsm9ds1-magn"; ++ reg = <0x1c>; ++ status = "okay"; ++ }; ++ ++ lsm9ds1-accel6a { ++ compatible = "st,lsm9ds1-accel"; ++ reg = <0x6a>; ++ status = "okay"; ++ }; ++ ++ lps25h-press@5c { ++ compatible = "st,lps25h-press"; ++ reg = <0x5c>; ++ status = "okay"; ++ }; ++ ++ hts221-humid@5f { ++ compatible = "st,hts221-humid"; ++ reg = <0x5f>; ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/sdhost-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/sdhost-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/sdhost-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/sdhost-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,56 @@ ++/dts-v1/; ++/plugin/; ++ ++/{ ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&soc>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ sdhost: sdhost@7e202000 { ++ compatible = "brcm,bcm2835-sdhost"; ++ reg = <0x7e202000 0x100>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdhost_pins>; ++ interrupts = <2 24>; ++ clocks = <&clk_core>; ++ dmas = <&dma 13>, ++ <&dma 13>; ++ dma-names = "tx", "rx"; ++ brcm,delay-after-stop = <0>; ++ brcm,overclock-50 = <0>; ++ brcm,pio-limit = <1>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ sdhost_pins: sdhost_pins { ++ brcm,pins = <48 49 50 51 52 53>; ++ brcm,function = <4>; /* alt0 */ ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&mmc>; ++ __overlay__ { ++ /* Find a way to disable the other driver */ ++ compatible = ""; ++ status = "disabled"; ++ }; ++ }; ++ ++ __overrides__ { ++ overclock_50 = <&sdhost>,"brcm,overclock-50:0"; ++ force_pio = <&sdhost>,"brcm,force-pio?"; ++ pio_limit = <&sdhost>,"brcm,pio-limit:0"; ++ debug = <&sdhost>,"brcm,debug?"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/sdio-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/sdio-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/sdio-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/sdio-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,33 @@ ++/* Enable SDIO from MMC interface via GPIOs 22-27. Includes sdhost overlay. */ ++ ++/include/ "sdhost-overlay.dts" ++ ++/{ ++ compatible = "brcm,bcm2708"; ++ ++ fragment@3 { ++ target = <&mmc>; ++ sdio_mmc: __overlay__ { ++ compatible = "brcm,bcm2835-mmc"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdio_pins>; ++ non-removable; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@4 { ++ target = <&gpio>; ++ __overlay__ { ++ sdio_pins: sdio_pins { ++ brcm,pins = <22 23 24 25 26 27>; ++ brcm,function = <7 7 7 7 7 7>; /* ALT3 = SD1 */ ++ brcm,pull = <0 2 2 2 2 2>; ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ poll_once = <&sdio_mmc>,"non-removable?"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/smi-dev-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/smi-dev-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/smi-dev-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/smi-dev-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,18 @@ ++// Description: Overlay to enable character device interface for SMI. ++// Author: Luke Wren ++ ++/dts-v1/; ++/plugin/; ++ ++/{ ++ fragment@0 { ++ target = <&soc>; ++ __overlay__ { ++ smi_dev { ++ compatible = "brcm,bcm2835-smi-dev"; ++ smi_handle = <&smi>; ++ status = "okay"; ++ }; ++ }; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/smi-nand-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/smi-nand-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/smi-nand-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/smi-nand-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,69 @@ ++// Description: Overlay to enable NAND flash through ++// the secondary memory interface ++// Author: Luke Wren ++ ++/dts-v1/; ++/plugin/; ++ ++/{ ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&smi>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&smi_pins>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&soc>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ nand: flash@0 { ++ compatible = "brcm,bcm2835-smi-nand"; ++ smi_handle = <&smi>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ status = "okay"; ++ ++ partition@0 { ++ label = "stage2"; ++ // 128k ++ reg = <0 0x20000>; ++ read-only; ++ }; ++ partition@1 { ++ label = "firmware"; ++ // 16M ++ reg = <0x20000 0x1000000>; ++ read-only; ++ }; ++ partition@2 { ++ label = "root"; ++ // 2G (will need to use 64 bit for >=4G) ++ reg = <0x1020000 0x80000000>; ++ }; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&gpio>; ++ __overlay__ { ++ smi_pins: smi_pins { ++ brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11 ++ 12 13 14 15>; ++ /* Alt 1: SMI */ ++ brcm,function = <5 5 5 5 5 5 5 5 5 5 5 ++ 5 5 5 5 5>; ++ /* /CS, /WE and /OE are pulled high, as they are ++ generally active low signals */ ++ brcm,pull = <2 2 2 2 2 2 2 2 0 0 0 0 0 0 0 0>; ++ }; ++ }; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/smi-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/smi-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/smi-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/smi-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,37 @@ ++// Description: Overlay to enable the secondary memory interface peripheral ++// Author: Luke Wren ++ ++/dts-v1/; ++/plugin/; ++ ++/{ ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&smi>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&smi_pins>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ smi_pins: smi_pins { ++ /* Don't configure the top two address bits, as ++ these are already used as ID_SD and ID_SC */ ++ brcm,pins = <2 3 4 5 6 7 8 9 10 11 12 13 14 15 ++ 16 17 18 19 20 21 22 23 24 25>; ++ /* Alt 0: SMI */ ++ brcm,function = <5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 ++ 5 5 5 5 5 5 5 5 5>; ++ /* /CS, /WE and /OE are pulled high, as they are ++ generally active low signals */ ++ brcm,pull = <2 2 2 2 2 2 0 0 0 0 0 0 0 0 0 0 0 ++ 0 0 0 0 0 0 0>; ++ }; ++ }; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/spi-bcm2708-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/spi-bcm2708-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/spi-bcm2708-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/spi-bcm2708-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,18 @@ ++/* ++ * Device tree overlay for spi-bcm2835 ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835", "brcm,bcm2836", "brcm,bcm2708", "brcm,bcm2709"; ++ /* setting up compatiblity to allow loading the spi-bcm2835 driver */ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ compatible = "brcm,bcm2708-spi"; ++ }; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/spi-bcm2835-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/spi-bcm2835-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/spi-bcm2835-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/spi-bcm2835-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,18 @@ ++/* ++ * Device tree overlay for spi-bcm2835 ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835", "brcm,bcm2836", "brcm,bcm2708", "brcm,bcm2709"; ++ /* setting up compatiblity to allow loading the spi-bcm2835 driver */ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ compatible = "brcm,bcm2835-spi"; ++ }; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/spi-dma-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/spi-dma-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/spi-dma-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/spi-dma-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,20 @@ ++/* ++ * Device tree overlay for spi-bcm2835 to allow dma ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835", "brcm,bcm2836", "brcm,bcm2708", "brcm,bcm2709"; ++ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ dmas = <&dma 6>, <&dma 7>; ++ dma-names = "tx", "rx"; ++ }; ++ }; ++ }; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/tinylcd35-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/tinylcd35-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/tinylcd35-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/tinylcd35-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,216 @@ ++/* ++ * tinylcd35-overlay.dts ++ * ++ * ------------------------------------------------- ++ * www.tinlylcd.com ++ * ------------------------------------------------- ++ * Device---Driver-----BUS GPIO's ++ * display tinylcd35 spi0.0 25 24 18 ++ * touch ads7846 spi0.1 5 ++ * rtc ds1307 i2c1-0068 ++ * rtc pcf8563 i2c1-0051 ++ * keypad gpio-keys --------- 17 22 27 23 28 ++ * ++ * ++ * TinyLCD.com 3.5 inch TFT ++ * ++ * Version 001 ++ * 5/3/2015 -- Noralf Trønnes Initial Device tree framework ++ * 10/3/2015 -- tinylcd@gmail.com added ds1307 support. ++ * ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709"; ++ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ ++ spidev@0{ ++ status = "disabled"; ++ }; ++ ++ spidev@1{ ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ tinylcd35_pins: tinylcd35_pins { ++ brcm,pins = <25 24 18>; ++ brcm,function = <1>; /* out */ ++ }; ++ tinylcd35_ts_pins: tinylcd35_ts_pins { ++ brcm,pins = <5>; ++ brcm,function = <0>; /* in */ ++ }; ++ keypad_pins: keypad_pins { ++ brcm,pins = <4 17 22 23 27>; ++ brcm,function = <0>; /* in */ ++ brcm,pull = <1>; /* down */ ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi0>; ++ __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ tinylcd35: tinylcd35@0{ ++ compatible = "neosec,tinylcd"; ++ reg = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&tinylcd35_pins>, ++ <&tinylcd35_ts_pins>; ++ ++ spi-max-frequency = <48000000>; ++ rotate = <270>; ++ fps = <20>; ++ bgr; ++ buswidth = <8>; ++ reset-gpios = <&gpio 25 0>; ++ dc-gpios = <&gpio 24 0>; ++ led-gpios = <&gpio 18 1>; ++ debug = <0>; ++ ++ init = <0x10000B0 0x80 ++ 0x10000C0 0x0A 0x0A ++ 0x10000C1 0x01 0x01 ++ 0x10000C2 0x33 ++ 0x10000C5 0x00 0x42 0x80 ++ 0x10000B1 0xD0 0x11 ++ 0x10000B4 0x02 ++ 0x10000B6 0x00 0x22 0x3B ++ 0x10000B7 0x07 ++ 0x1000036 0x58 ++ 0x10000F0 0x36 0xA5 0xD3 ++ 0x10000E5 0x80 ++ 0x10000E5 0x01 ++ 0x10000B3 0x00 ++ 0x10000E5 0x00 ++ 0x10000F0 0x36 0xA5 0x53 ++ 0x10000E0 0x00 0x35 0x33 0x00 0x00 0x00 0x00 0x35 0x33 0x00 0x00 0x00 ++ 0x100003A 0x55 ++ 0x1000011 ++ 0x2000001 ++ 0x1000029>; ++ }; ++ ++ tinylcd35_ts: tinylcd35_ts@1 { ++ compatible = "ti,ads7846"; ++ reg = <1>; ++ status = "disabled"; ++ ++ spi-max-frequency = <2000000>; ++ interrupts = <5 2>; /* high-to-low edge triggered */ ++ interrupt-parent = <&gpio>; ++ pendown-gpio = <&gpio 5 0>; ++ ti,x-plate-ohms = /bits/ 16 <100>; ++ ti,pressure-max = /bits/ 16 <255>; ++ }; ++ }; ++ }; ++ ++ /* RTC */ ++ ++ fragment@3 { ++ target = <&i2c1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ pcf8563: pcf8563@51 { ++ compatible = "nxp,pcf8563"; ++ reg = <0x51>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@4 { ++ target = <&i2c1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ ds1307: ds1307@68 { ++ compatible = "maxim,ds1307"; ++ reg = <0x68>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ /* ++ * Values for input event code is found under the ++ * 'Keys and buttons' heading in include/uapi/linux/input.h ++ */ ++ fragment@5 { ++ target-path = "/soc"; ++ __overlay__ { ++ keypad: keypad { ++ compatible = "gpio-keys"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&keypad_pins>; ++ status = "disabled"; ++ autorepeat; ++ ++ button@17 { ++ label = "GPIO KEY_UP"; ++ linux,code = <103>; ++ gpios = <&gpio 17 0>; ++ }; ++ button@22 { ++ label = "GPIO KEY_DOWN"; ++ linux,code = <108>; ++ gpios = <&gpio 22 0>; ++ }; ++ button@27 { ++ label = "GPIO KEY_LEFT"; ++ linux,code = <105>; ++ gpios = <&gpio 27 0>; ++ }; ++ button@23 { ++ label = "GPIO KEY_RIGHT"; ++ linux,code = <106>; ++ gpios = <&gpio 23 0>; ++ }; ++ button@4 { ++ label = "GPIO KEY_ENTER"; ++ linux,code = <28>; ++ gpios = <&gpio 4 0>; ++ }; ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ speed = <&tinylcd35>,"spi-max-frequency:0"; ++ rotate = <&tinylcd35>,"rotate:0"; ++ fps = <&tinylcd35>,"fps:0"; ++ debug = <&tinylcd35>,"debug:0"; ++ touch = <&tinylcd35_ts>,"status"; ++ touchgpio = <&tinylcd35_ts_pins>,"brcm,pins:0", ++ <&tinylcd35_ts>,"interrupts:0", ++ <&tinylcd35_ts>,"pendown-gpio:4"; ++ xohms = <&tinylcd35_ts>,"ti,x-plate-ohms;0"; ++ rtc-pcf = <&i2c1>,"status", ++ <&pcf8563>,"status"; ++ rtc-ds = <&i2c1>,"status", ++ <&ds1307>,"status"; ++ keypad = <&keypad>,"status"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/uart1-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/uart1-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/uart1-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/uart1-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,38 @@ ++/dts-v1/; ++/plugin/; ++ ++/{ ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target = <&uart1>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ uart1_pins: uart1_pins { ++ brcm,pins = <14 15>; ++ brcm,function = <2>; /* alt5 */ ++ brcm,pull = <0 2>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target-path = "/chosen"; ++ __overlay__ { ++ bootargs = "8250.nr_uarts=1"; ++ }; ++ }; ++ ++ __overrides__ { ++ txd1_pin = <&uart1_pins>,"brcm,pins:0"; ++ rxd1_pin = <&uart1_pins>,"brcm,pins:4"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/vga666-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/vga666-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/vga666-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/vga666-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,30 @@ ++/dts-v1/; ++/plugin/; ++ ++/{ ++ compatible = "brcm,bcm2708"; ++ ++ // There is no VGA driver module, but we need a platform device ++ // node (that doesn't already use pinctrl) to hang the pinctrl ++ // reference on - leds will do ++ ++ fragment@0 { ++ target = <&leds>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vga666_pins>; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ vga666_pins: vga666_pins { ++ brcm,pins = <2 3 4 5 6 7 8 9 10 11 12 ++ 13 14 15 16 17 18 19 20 21>; ++ brcm,function = <6>; /* alt2 */ ++ brcm,pull = <0>; /* no pull */ ++ }; ++ }; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/w1-gpio-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/w1-gpio-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/w1-gpio-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/w1-gpio-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,39 @@ ++// Definitions for w1-gpio module (without external pullup) ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target-path = "/"; ++ __overlay__ { ++ ++ w1: onewire@0 { ++ compatible = "w1-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&w1_pins>; ++ gpios = <&gpio 4 0>; ++ rpi,parasitic-power = <0>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ w1_pins: w1_pins { ++ brcm,pins = <4>; ++ brcm,function = <0>; // in (initially) ++ brcm,pull = <0>; // off ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ gpiopin = <&w1>,"gpios:4", ++ <&w1_pins>,"brcm,pins:0"; ++ pullup = <&w1>,"rpi,parasitic-power:0"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/overlays/w1-gpio-pullup-overlay.dts linux-rpi/arch/arm/boot/dts/overlays/w1-gpio-pullup-overlay.dts +--- linux-4.1.13.orig/arch/arm/boot/dts/overlays/w1-gpio-pullup-overlay.dts 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/boot/dts/overlays/w1-gpio-pullup-overlay.dts 2015-11-29 09:42:34.663447905 +0100 +@@ -0,0 +1,41 @@ ++// Definitions for w1-gpio module (with external pullup) ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2708"; ++ ++ fragment@0 { ++ target-path = "/"; ++ __overlay__ { ++ ++ w1: onewire@0 { ++ compatible = "w1-gpio"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&w1_pins>; ++ gpios = <&gpio 4 0>, <&gpio 5 1>; ++ rpi,parasitic-power = <0>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ w1_pins: w1_pins { ++ brcm,pins = <4 5>; ++ brcm,function = <0 1>; // in out ++ brcm,pull = <0 0>; // off off ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ gpiopin = <&w1>,"gpios:4", ++ <&w1_pins>,"brcm,pins:0"; ++ extpullup = <&w1>,"gpios:16", ++ <&w1_pins>,"brcm,pins:4"; ++ pullup = <&w1>,"rpi,parasitic-power:0"; ++ }; ++}; +diff -Nur linux-4.1.13.orig/arch/arm/configs/bcm2709_defconfig linux-rpi/arch/arm/configs/bcm2709_defconfig +--- linux-4.1.13.orig/arch/arm/configs/bcm2709_defconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/configs/bcm2709_defconfig 2015-11-29 09:42:34.707444982 +0100 +@@ -0,0 +1,1260 @@ ++# CONFIG_ARM_PATCH_PHYS_VIRT is not set ++CONFIG_PHYS_OFFSET=0 ++CONFIG_LOCALVERSION="-v7" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_SYSVIPC=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_FHANDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++CONFIG_BSD_PROCESS_ACCT=y ++CONFIG_BSD_PROCESS_ACCT_V3=y ++CONFIG_TASKSTATS=y ++CONFIG_TASK_DELAY_ACCT=y ++CONFIG_TASK_XACCT=y ++CONFIG_TASK_IO_ACCOUNTING=y ++CONFIG_IKCONFIG=m ++CONFIG_IKCONFIG_PROC=y ++CONFIG_CGROUP_FREEZER=y ++CONFIG_CGROUP_DEVICE=y ++CONFIG_CPUSETS=y ++CONFIG_CGROUP_CPUACCT=y ++CONFIG_MEMCG=y ++CONFIG_BLK_CGROUP=y ++CONFIG_NAMESPACES=y ++CONFIG_SCHED_AUTOGROUP=y ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_EMBEDDED=y ++# CONFIG_COMPAT_BRK is not set ++CONFIG_PROFILING=y ++CONFIG_OPROFILE=m ++CONFIG_KPROBES=y ++CONFIG_JUMP_LABEL=y ++CONFIG_MODULES=y ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODVERSIONS=y ++CONFIG_MODULE_SRCVERSION_ALL=y ++CONFIG_BLK_DEV_THROTTLING=y ++CONFIG_PARTITION_ADVANCED=y ++CONFIG_MAC_PARTITION=y ++CONFIG_CFQ_GROUP_IOSCHED=y ++CONFIG_ARCH_BCM2709=y ++CONFIG_BCM2709_DT=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_SMP=y ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_2G=y ++CONFIG_PREEMPT=y ++CONFIG_AEABI=y ++CONFIG_OABI_COMPAT=y ++CONFIG_CLEANCACHE=y ++CONFIG_FRONTSWAP=y ++CONFIG_CMA=y ++CONFIG_ZSMALLOC=m ++CONFIG_PGTABLE_MAPPING=y ++CONFIG_UACCESS_WITH_MEMCPY=y ++CONFIG_SECCOMP=y ++CONFIG_ZBOOT_ROM_TEXT=0x0 ++CONFIG_ZBOOT_ROM_BSS=0x0 ++CONFIG_CMDLINE="console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait" ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_STAT=m ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y ++CONFIG_VFP=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++CONFIG_BINFMT_MISC=m ++# CONFIG_SUSPEND is not set ++CONFIG_NET=y ++CONFIG_PACKET=y ++CONFIG_UNIX=y ++CONFIG_XFRM_USER=y ++CONFIG_NET_KEY=m ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++CONFIG_IP_MULTIPLE_TABLES=y ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++CONFIG_IP_PNP=y ++CONFIG_IP_PNP_DHCP=y ++CONFIG_IP_PNP_RARP=y ++CONFIG_NET_IPIP=m ++CONFIG_NET_IPGRE_DEMUX=m ++CONFIG_NET_IPGRE=m ++CONFIG_IP_MROUTE=y ++CONFIG_IP_MROUTE_MULTIPLE_TABLES=y ++CONFIG_IP_PIMSM_V1=y ++CONFIG_IP_PIMSM_V2=y ++CONFIG_SYN_COOKIES=y ++CONFIG_INET_AH=m ++CONFIG_INET_ESP=m ++CONFIG_INET_IPCOMP=m ++CONFIG_INET_XFRM_MODE_TRANSPORT=m ++CONFIG_INET_XFRM_MODE_TUNNEL=m ++CONFIG_INET_XFRM_MODE_BEET=m ++CONFIG_INET_LRO=m ++CONFIG_INET_DIAG=m ++CONFIG_INET6_AH=m ++CONFIG_INET6_ESP=m ++CONFIG_INET6_IPCOMP=m ++CONFIG_IPV6_TUNNEL=m ++CONFIG_IPV6_MULTIPLE_TABLES=y ++CONFIG_IPV6_MROUTE=y ++CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y ++CONFIG_IPV6_PIMSM_V2=y ++CONFIG_NETFILTER=y ++CONFIG_NF_CONNTRACK=m ++CONFIG_NF_CONNTRACK_ZONES=y ++CONFIG_NF_CONNTRACK_EVENTS=y ++CONFIG_NF_CONNTRACK_TIMESTAMP=y ++CONFIG_NF_CT_PROTO_DCCP=m ++CONFIG_NF_CT_PROTO_UDPLITE=m ++CONFIG_NF_CONNTRACK_AMANDA=m ++CONFIG_NF_CONNTRACK_FTP=m ++CONFIG_NF_CONNTRACK_H323=m ++CONFIG_NF_CONNTRACK_IRC=m ++CONFIG_NF_CONNTRACK_NETBIOS_NS=m ++CONFIG_NF_CONNTRACK_SNMP=m ++CONFIG_NF_CONNTRACK_PPTP=m ++CONFIG_NF_CONNTRACK_SANE=m ++CONFIG_NF_CONNTRACK_SIP=m ++CONFIG_NF_CONNTRACK_TFTP=m ++CONFIG_NF_CT_NETLINK=m ++CONFIG_NETFILTER_XT_SET=m ++CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m ++CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m ++CONFIG_NETFILTER_XT_TARGET_CONNMARK=m ++CONFIG_NETFILTER_XT_TARGET_DSCP=m ++CONFIG_NETFILTER_XT_TARGET_HMARK=m ++CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m ++CONFIG_NETFILTER_XT_TARGET_LED=m ++CONFIG_NETFILTER_XT_TARGET_LOG=m ++CONFIG_NETFILTER_XT_TARGET_MARK=m ++CONFIG_NETFILTER_XT_TARGET_NFLOG=m ++CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m ++CONFIG_NETFILTER_XT_TARGET_NOTRACK=m ++CONFIG_NETFILTER_XT_TARGET_TEE=m ++CONFIG_NETFILTER_XT_TARGET_TPROXY=m ++CONFIG_NETFILTER_XT_TARGET_TRACE=m ++CONFIG_NETFILTER_XT_TARGET_TCPMSS=m ++CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m ++CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m ++CONFIG_NETFILTER_XT_MATCH_BPF=m ++CONFIG_NETFILTER_XT_MATCH_CLUSTER=m ++CONFIG_NETFILTER_XT_MATCH_COMMENT=m ++CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m ++CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m ++CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m ++CONFIG_NETFILTER_XT_MATCH_CONNMARK=m ++CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m ++CONFIG_NETFILTER_XT_MATCH_CPU=m ++CONFIG_NETFILTER_XT_MATCH_DCCP=m ++CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m ++CONFIG_NETFILTER_XT_MATCH_DSCP=m ++CONFIG_NETFILTER_XT_MATCH_ESP=m ++CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m ++CONFIG_NETFILTER_XT_MATCH_HELPER=m ++CONFIG_NETFILTER_XT_MATCH_IPRANGE=m ++CONFIG_NETFILTER_XT_MATCH_IPVS=m ++CONFIG_NETFILTER_XT_MATCH_LENGTH=m ++CONFIG_NETFILTER_XT_MATCH_LIMIT=m ++CONFIG_NETFILTER_XT_MATCH_MAC=m ++CONFIG_NETFILTER_XT_MATCH_MARK=m ++CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m ++CONFIG_NETFILTER_XT_MATCH_NFACCT=m ++CONFIG_NETFILTER_XT_MATCH_OSF=m ++CONFIG_NETFILTER_XT_MATCH_OWNER=m ++CONFIG_NETFILTER_XT_MATCH_POLICY=m ++CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m ++CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m ++CONFIG_NETFILTER_XT_MATCH_QUOTA=m ++CONFIG_NETFILTER_XT_MATCH_RATEEST=m ++CONFIG_NETFILTER_XT_MATCH_REALM=m ++CONFIG_NETFILTER_XT_MATCH_RECENT=m ++CONFIG_NETFILTER_XT_MATCH_SOCKET=m ++CONFIG_NETFILTER_XT_MATCH_STATE=m ++CONFIG_NETFILTER_XT_MATCH_STATISTIC=m ++CONFIG_NETFILTER_XT_MATCH_STRING=m ++CONFIG_NETFILTER_XT_MATCH_TCPMSS=m ++CONFIG_NETFILTER_XT_MATCH_TIME=m ++CONFIG_NETFILTER_XT_MATCH_U32=m ++CONFIG_IP_SET=m ++CONFIG_IP_SET_BITMAP_IP=m ++CONFIG_IP_SET_BITMAP_IPMAC=m ++CONFIG_IP_SET_BITMAP_PORT=m ++CONFIG_IP_SET_HASH_IP=m ++CONFIG_IP_SET_HASH_IPPORT=m ++CONFIG_IP_SET_HASH_IPPORTIP=m ++CONFIG_IP_SET_HASH_IPPORTNET=m ++CONFIG_IP_SET_HASH_NET=m ++CONFIG_IP_SET_HASH_NETPORT=m ++CONFIG_IP_SET_HASH_NETIFACE=m ++CONFIG_IP_SET_LIST_SET=m ++CONFIG_IP_VS=m ++CONFIG_IP_VS_PROTO_TCP=y ++CONFIG_IP_VS_PROTO_UDP=y ++CONFIG_IP_VS_PROTO_ESP=y ++CONFIG_IP_VS_PROTO_AH=y ++CONFIG_IP_VS_PROTO_SCTP=y ++CONFIG_IP_VS_RR=m ++CONFIG_IP_VS_WRR=m ++CONFIG_IP_VS_LC=m ++CONFIG_IP_VS_WLC=m ++CONFIG_IP_VS_LBLC=m ++CONFIG_IP_VS_LBLCR=m ++CONFIG_IP_VS_DH=m ++CONFIG_IP_VS_SH=m ++CONFIG_IP_VS_SED=m ++CONFIG_IP_VS_NQ=m ++CONFIG_IP_VS_FTP=m ++CONFIG_IP_VS_PE_SIP=m ++CONFIG_NF_CONNTRACK_IPV4=m ++CONFIG_IP_NF_IPTABLES=m ++CONFIG_IP_NF_MATCH_AH=m ++CONFIG_IP_NF_MATCH_ECN=m ++CONFIG_IP_NF_MATCH_TTL=m ++CONFIG_IP_NF_FILTER=m ++CONFIG_IP_NF_TARGET_REJECT=m ++CONFIG_IP_NF_NAT=m ++CONFIG_IP_NF_TARGET_MASQUERADE=m ++CONFIG_IP_NF_TARGET_NETMAP=m ++CONFIG_IP_NF_TARGET_REDIRECT=m ++CONFIG_IP_NF_MANGLE=m ++CONFIG_IP_NF_TARGET_CLUSTERIP=m ++CONFIG_IP_NF_TARGET_ECN=m ++CONFIG_IP_NF_TARGET_TTL=m ++CONFIG_IP_NF_RAW=m ++CONFIG_IP_NF_ARPTABLES=m ++CONFIG_IP_NF_ARPFILTER=m ++CONFIG_IP_NF_ARP_MANGLE=m ++CONFIG_NF_CONNTRACK_IPV6=m ++CONFIG_IP6_NF_IPTABLES=m ++CONFIG_IP6_NF_MATCH_AH=m ++CONFIG_IP6_NF_MATCH_EUI64=m ++CONFIG_IP6_NF_MATCH_FRAG=m ++CONFIG_IP6_NF_MATCH_OPTS=m ++CONFIG_IP6_NF_MATCH_HL=m ++CONFIG_IP6_NF_MATCH_IPV6HEADER=m ++CONFIG_IP6_NF_MATCH_MH=m ++CONFIG_IP6_NF_MATCH_RT=m ++CONFIG_IP6_NF_TARGET_HL=m ++CONFIG_IP6_NF_FILTER=m ++CONFIG_IP6_NF_TARGET_REJECT=m ++CONFIG_IP6_NF_MANGLE=m ++CONFIG_IP6_NF_RAW=m ++CONFIG_IP6_NF_NAT=m ++CONFIG_IP6_NF_TARGET_MASQUERADE=m ++CONFIG_IP6_NF_TARGET_NPT=m ++CONFIG_BRIDGE_NF_EBTABLES=m ++CONFIG_BRIDGE_EBT_BROUTE=m ++CONFIG_BRIDGE_EBT_T_FILTER=m ++CONFIG_BRIDGE_EBT_T_NAT=m ++CONFIG_BRIDGE_EBT_802_3=m ++CONFIG_BRIDGE_EBT_AMONG=m ++CONFIG_BRIDGE_EBT_ARP=m ++CONFIG_BRIDGE_EBT_IP=m ++CONFIG_BRIDGE_EBT_IP6=m ++CONFIG_BRIDGE_EBT_LIMIT=m ++CONFIG_BRIDGE_EBT_MARK=m ++CONFIG_BRIDGE_EBT_PKTTYPE=m ++CONFIG_BRIDGE_EBT_STP=m ++CONFIG_BRIDGE_EBT_VLAN=m ++CONFIG_BRIDGE_EBT_ARPREPLY=m ++CONFIG_BRIDGE_EBT_DNAT=m ++CONFIG_BRIDGE_EBT_MARK_T=m ++CONFIG_BRIDGE_EBT_REDIRECT=m ++CONFIG_BRIDGE_EBT_SNAT=m ++CONFIG_BRIDGE_EBT_LOG=m ++CONFIG_BRIDGE_EBT_NFLOG=m ++CONFIG_SCTP_COOKIE_HMAC_SHA1=y ++CONFIG_ATM=m ++CONFIG_L2TP=m ++CONFIG_L2TP_V3=y ++CONFIG_L2TP_IP=m ++CONFIG_L2TP_ETH=m ++CONFIG_BRIDGE=m ++CONFIG_VLAN_8021Q=m ++CONFIG_VLAN_8021Q_GVRP=y ++CONFIG_ATALK=m ++CONFIG_6LOWPAN=m ++CONFIG_IEEE802154=m ++CONFIG_IEEE802154_6LOWPAN=m ++CONFIG_MAC802154=m ++CONFIG_NET_SCHED=y ++CONFIG_NET_SCH_CBQ=m ++CONFIG_NET_SCH_HTB=m ++CONFIG_NET_SCH_HFSC=m ++CONFIG_NET_SCH_PRIO=m ++CONFIG_NET_SCH_MULTIQ=m ++CONFIG_NET_SCH_RED=m ++CONFIG_NET_SCH_SFB=m ++CONFIG_NET_SCH_SFQ=m ++CONFIG_NET_SCH_TEQL=m ++CONFIG_NET_SCH_TBF=m ++CONFIG_NET_SCH_GRED=m ++CONFIG_NET_SCH_DSMARK=m ++CONFIG_NET_SCH_NETEM=m ++CONFIG_NET_SCH_DRR=m ++CONFIG_NET_SCH_MQPRIO=m ++CONFIG_NET_SCH_CHOKE=m ++CONFIG_NET_SCH_QFQ=m ++CONFIG_NET_SCH_CODEL=m ++CONFIG_NET_SCH_FQ_CODEL=m ++CONFIG_NET_SCH_INGRESS=m ++CONFIG_NET_SCH_PLUG=m ++CONFIG_NET_CLS_BASIC=m ++CONFIG_NET_CLS_TCINDEX=m ++CONFIG_NET_CLS_ROUTE4=m ++CONFIG_NET_CLS_FW=m ++CONFIG_NET_CLS_U32=m ++CONFIG_CLS_U32_MARK=y ++CONFIG_NET_CLS_RSVP=m ++CONFIG_NET_CLS_RSVP6=m ++CONFIG_NET_CLS_FLOW=m ++CONFIG_NET_CLS_CGROUP=m ++CONFIG_NET_EMATCH=y ++CONFIG_NET_EMATCH_CMP=m ++CONFIG_NET_EMATCH_NBYTE=m ++CONFIG_NET_EMATCH_U32=m ++CONFIG_NET_EMATCH_META=m ++CONFIG_NET_EMATCH_TEXT=m ++CONFIG_NET_EMATCH_IPSET=m ++CONFIG_NET_CLS_ACT=y ++CONFIG_NET_ACT_POLICE=m ++CONFIG_NET_ACT_GACT=m ++CONFIG_GACT_PROB=y ++CONFIG_NET_ACT_MIRRED=m ++CONFIG_NET_ACT_IPT=m ++CONFIG_NET_ACT_NAT=m ++CONFIG_NET_ACT_PEDIT=m ++CONFIG_NET_ACT_SIMP=m ++CONFIG_NET_ACT_SKBEDIT=m ++CONFIG_NET_ACT_CSUM=m ++CONFIG_BATMAN_ADV=m ++CONFIG_OPENVSWITCH=m ++CONFIG_NET_PKTGEN=m ++CONFIG_HAMRADIO=y ++CONFIG_AX25=m ++CONFIG_NETROM=m ++CONFIG_ROSE=m ++CONFIG_MKISS=m ++CONFIG_6PACK=m ++CONFIG_BPQETHER=m ++CONFIG_BAYCOM_SER_FDX=m ++CONFIG_BAYCOM_SER_HDX=m ++CONFIG_YAM=m ++CONFIG_CAN=m ++CONFIG_CAN_VCAN=m ++CONFIG_CAN_MCP251X=m ++CONFIG_IRDA=m ++CONFIG_IRLAN=m ++CONFIG_IRNET=m ++CONFIG_IRCOMM=m ++CONFIG_IRDA_ULTRA=y ++CONFIG_IRDA_CACHE_LAST_LSAP=y ++CONFIG_IRDA_FAST_RR=y ++CONFIG_IRTTY_SIR=m ++CONFIG_KINGSUN_DONGLE=m ++CONFIG_KSDAZZLE_DONGLE=m ++CONFIG_KS959_DONGLE=m ++CONFIG_USB_IRDA=m ++CONFIG_SIGMATEL_FIR=m ++CONFIG_MCS_FIR=m ++CONFIG_BT=m ++CONFIG_BT_RFCOMM=m ++CONFIG_BT_RFCOMM_TTY=y ++CONFIG_BT_BNEP=m ++CONFIG_BT_BNEP_MC_FILTER=y ++CONFIG_BT_BNEP_PROTO_FILTER=y ++CONFIG_BT_HIDP=m ++CONFIG_BT_6LOWPAN=m ++CONFIG_BT_HCIBTUSB=m ++CONFIG_BT_HCIBCM203X=m ++CONFIG_BT_HCIBPA10X=m ++CONFIG_BT_HCIBFUSB=m ++CONFIG_BT_HCIVHCI=m ++CONFIG_BT_MRVL=m ++CONFIG_BT_MRVL_SDIO=m ++CONFIG_BT_ATH3K=m ++CONFIG_BT_WILINK=m ++CONFIG_MAC80211=m ++CONFIG_MAC80211_MESH=y ++CONFIG_WIMAX=m ++CONFIG_RFKILL=m ++CONFIG_RFKILL_INPUT=y ++CONFIG_NET_9P=m ++CONFIG_NFC=m ++CONFIG_NFC_PN533=m ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++CONFIG_DMA_CMA=y ++CONFIG_CMA_SIZE_MBYTES=5 ++CONFIG_MTD=m ++CONFIG_MTD_BLOCK=m ++CONFIG_MTD_NAND=m ++CONFIG_MTD_UBI=m ++CONFIG_ZRAM=m ++CONFIG_ZRAM_LZ4_COMPRESS=y ++CONFIG_BLK_DEV_LOOP=y ++CONFIG_BLK_DEV_CRYPTOLOOP=m ++CONFIG_BLK_DEV_DRBD=m ++CONFIG_BLK_DEV_NBD=m ++CONFIG_BLK_DEV_RAM=y ++CONFIG_CDROM_PKTCDVD=m ++CONFIG_ATA_OVER_ETH=m ++CONFIG_EEPROM_AT24=m ++CONFIG_TI_ST=m ++CONFIG_SCSI=y ++# CONFIG_SCSI_PROC_FS is not set ++CONFIG_BLK_DEV_SD=y ++CONFIG_CHR_DEV_ST=m ++CONFIG_CHR_DEV_OSST=m ++CONFIG_BLK_DEV_SR=m ++CONFIG_CHR_DEV_SG=m ++CONFIG_SCSI_ISCSI_ATTRS=y ++CONFIG_ISCSI_TCP=m ++CONFIG_ISCSI_BOOT_SYSFS=m ++CONFIG_MD=y ++CONFIG_MD_LINEAR=m ++CONFIG_MD_RAID0=m ++CONFIG_BLK_DEV_DM=m ++CONFIG_DM_CRYPT=m ++CONFIG_DM_SNAPSHOT=m ++CONFIG_DM_THIN_PROVISIONING=m ++CONFIG_DM_MIRROR=m ++CONFIG_DM_LOG_USERSPACE=m ++CONFIG_DM_RAID=m ++CONFIG_DM_ZERO=m ++CONFIG_DM_DELAY=m ++CONFIG_NETDEVICES=y ++CONFIG_BONDING=m ++CONFIG_DUMMY=m ++CONFIG_IFB=m ++CONFIG_MACVLAN=m ++CONFIG_NETCONSOLE=m ++CONFIG_TUN=m ++CONFIG_VETH=m ++CONFIG_ENC28J60=m ++CONFIG_MDIO_BITBANG=m ++CONFIG_PPP=m ++CONFIG_PPP_BSDCOMP=m ++CONFIG_PPP_DEFLATE=m ++CONFIG_PPP_FILTER=y ++CONFIG_PPP_MPPE=m ++CONFIG_PPP_MULTILINK=y ++CONFIG_PPPOATM=m ++CONFIG_PPPOE=m ++CONFIG_PPPOL2TP=m ++CONFIG_PPP_ASYNC=m ++CONFIG_PPP_SYNC_TTY=m ++CONFIG_SLIP=m ++CONFIG_SLIP_COMPRESSED=y ++CONFIG_SLIP_SMART=y ++CONFIG_USB_CATC=m ++CONFIG_USB_KAWETH=m ++CONFIG_USB_PEGASUS=m ++CONFIG_USB_RTL8150=m ++CONFIG_USB_RTL8152=m ++CONFIG_USB_USBNET=y ++CONFIG_USB_NET_AX8817X=m ++CONFIG_USB_NET_AX88179_178A=m ++CONFIG_USB_NET_CDCETHER=m ++CONFIG_USB_NET_CDC_EEM=m ++CONFIG_USB_NET_CDC_NCM=m ++CONFIG_USB_NET_HUAWEI_CDC_NCM=m ++CONFIG_USB_NET_CDC_MBIM=m ++CONFIG_USB_NET_DM9601=m ++CONFIG_USB_NET_SR9700=m ++CONFIG_USB_NET_SR9800=m ++CONFIG_USB_NET_SMSC75XX=m ++CONFIG_USB_NET_SMSC95XX=y ++CONFIG_USB_NET_GL620A=m ++CONFIG_USB_NET_NET1080=m ++CONFIG_USB_NET_PLUSB=m ++CONFIG_USB_NET_MCS7830=m ++CONFIG_USB_NET_CDC_SUBSET=m ++CONFIG_USB_ALI_M5632=y ++CONFIG_USB_AN2720=y ++CONFIG_USB_EPSON2888=y ++CONFIG_USB_KC2190=y ++CONFIG_USB_NET_ZAURUS=m ++CONFIG_USB_NET_CX82310_ETH=m ++CONFIG_USB_NET_KALMIA=m ++CONFIG_USB_NET_QMI_WWAN=m ++CONFIG_USB_HSO=m ++CONFIG_USB_NET_INT51X1=m ++CONFIG_USB_IPHETH=m ++CONFIG_USB_SIERRA_NET=m ++CONFIG_USB_VL600=m ++CONFIG_LIBERTAS_THINFIRM=m ++CONFIG_LIBERTAS_THINFIRM_USB=m ++CONFIG_AT76C50X_USB=m ++CONFIG_USB_ZD1201=m ++CONFIG_USB_NET_RNDIS_WLAN=m ++CONFIG_RTL8187=m ++CONFIG_MAC80211_HWSIM=m ++CONFIG_ATH_CARDS=m ++CONFIG_ATH9K=m ++CONFIG_ATH9K_HTC=m ++CONFIG_CARL9170=m ++CONFIG_ATH6KL=m ++CONFIG_ATH6KL_USB=m ++CONFIG_AR5523=m ++CONFIG_B43=m ++# CONFIG_B43_PHY_N is not set ++CONFIG_B43LEGACY=m ++CONFIG_BRCMFMAC=m ++CONFIG_BRCMFMAC_USB=y ++CONFIG_HOSTAP=m ++CONFIG_LIBERTAS=m ++CONFIG_LIBERTAS_USB=m ++CONFIG_LIBERTAS_SDIO=m ++CONFIG_P54_COMMON=m ++CONFIG_P54_USB=m ++CONFIG_RT2X00=m ++CONFIG_RT2500USB=m ++CONFIG_RT73USB=m ++CONFIG_RT2800USB=m ++CONFIG_RT2800USB_RT3573=y ++CONFIG_RT2800USB_RT53XX=y ++CONFIG_RT2800USB_RT55XX=y ++CONFIG_RT2800USB_UNKNOWN=y ++CONFIG_WL_MEDIATEK=y ++CONFIG_MT7601U=m ++CONFIG_RTL8192CU=m ++CONFIG_ZD1211RW=m ++CONFIG_MWIFIEX=m ++CONFIG_MWIFIEX_SDIO=m ++CONFIG_WIMAX_I2400M_USB=m ++CONFIG_IEEE802154_AT86RF230=m ++CONFIG_IEEE802154_MRF24J40=m ++CONFIG_IEEE802154_CC2520=m ++CONFIG_INPUT_POLLDEV=m ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_JOYDEV=m ++CONFIG_INPUT_EVDEV=m ++# CONFIG_KEYBOARD_ATKBD is not set ++CONFIG_KEYBOARD_GPIO=m ++# CONFIG_INPUT_MOUSE is not set ++CONFIG_INPUT_JOYSTICK=y ++CONFIG_JOYSTICK_IFORCE=m ++CONFIG_JOYSTICK_IFORCE_USB=y ++CONFIG_JOYSTICK_XPAD=m ++CONFIG_JOYSTICK_XPAD_FF=y ++CONFIG_JOYSTICK_RPISENSE=m ++CONFIG_INPUT_TOUCHSCREEN=y ++CONFIG_TOUCHSCREEN_ADS7846=m ++CONFIG_TOUCHSCREEN_EGALAX=m ++CONFIG_TOUCHSCREEN_FT6236=m ++CONFIG_TOUCHSCREEN_RPI_FT5406=m ++CONFIG_TOUCHSCREEN_USB_COMPOSITE=m ++CONFIG_TOUCHSCREEN_STMPE=m ++CONFIG_INPUT_MISC=y ++CONFIG_INPUT_AD714X=m ++CONFIG_INPUT_ATI_REMOTE2=m ++CONFIG_INPUT_KEYSPAN_REMOTE=m ++CONFIG_INPUT_POWERMATE=m ++CONFIG_INPUT_YEALINK=m ++CONFIG_INPUT_CM109=m ++CONFIG_INPUT_UINPUT=m ++CONFIG_INPUT_GPIO_ROTARY_ENCODER=m ++CONFIG_INPUT_ADXL34X=m ++CONFIG_INPUT_CMA3000=m ++CONFIG_SERIO=m ++CONFIG_SERIO_RAW=m ++CONFIG_GAMEPORT=m ++CONFIG_GAMEPORT_NS558=m ++CONFIG_GAMEPORT_L4=m ++CONFIG_DEVPTS_MULTIPLE_INSTANCES=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_DEVKMEM is not set ++CONFIG_SERIAL_8250=y ++# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set ++CONFIG_SERIAL_8250_CONSOLE=y ++# CONFIG_SERIAL_8250_DMA is not set ++CONFIG_SERIAL_8250_NR_UARTS=1 ++CONFIG_SERIAL_8250_RUNTIME_UARTS=0 ++CONFIG_SERIAL_AMBA_PL011=y ++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y ++CONFIG_SERIAL_OF_PLATFORM=y ++CONFIG_TTY_PRINTK=y ++CONFIG_HW_RANDOM=y ++CONFIG_HW_RANDOM_BCM2835=m ++CONFIG_HW_RANDOM_BCM2708=m ++CONFIG_RAW_DRIVER=y ++CONFIG_BRCM_CHAR_DRIVERS=y ++CONFIG_BCM_VC_CMA=y ++CONFIG_BCM_VCIO=y ++CONFIG_BCM_VC_SM=y ++CONFIG_I2C=y ++CONFIG_I2C_CHARDEV=m ++CONFIG_I2C_BCM2708=m ++CONFIG_I2C_GPIO=m ++CONFIG_SPI=y ++CONFIG_SPI_BCM2835=m ++CONFIG_SPI_BCM2708=m ++CONFIG_SPI_SPIDEV=y ++CONFIG_PPS=m ++CONFIG_PPS_CLIENT_LDISC=m ++CONFIG_PPS_CLIENT_GPIO=m ++CONFIG_GPIO_SYSFS=y ++CONFIG_GPIO_ARIZONA=m ++CONFIG_GPIO_STMPE=y ++CONFIG_W1=m ++CONFIG_W1_MASTER_DS2490=m ++CONFIG_W1_MASTER_DS2482=m ++CONFIG_W1_MASTER_DS1WM=m ++CONFIG_W1_MASTER_GPIO=m ++CONFIG_W1_SLAVE_THERM=m ++CONFIG_W1_SLAVE_SMEM=m ++CONFIG_W1_SLAVE_DS2408=m ++CONFIG_W1_SLAVE_DS2413=m ++CONFIG_W1_SLAVE_DS2406=m ++CONFIG_W1_SLAVE_DS2423=m ++CONFIG_W1_SLAVE_DS2431=m ++CONFIG_W1_SLAVE_DS2433=m ++CONFIG_W1_SLAVE_DS2760=m ++CONFIG_W1_SLAVE_DS2780=m ++CONFIG_W1_SLAVE_DS2781=m ++CONFIG_W1_SLAVE_DS28E04=m ++CONFIG_W1_SLAVE_BQ27000=m ++CONFIG_BATTERY_DS2760=m ++CONFIG_POWER_RESET=y ++CONFIG_POWER_RESET_GPIO=y ++CONFIG_HWMON=m ++CONFIG_SENSORS_SHT21=m ++CONFIG_SENSORS_SHTC1=m ++CONFIG_THERMAL=y ++CONFIG_THERMAL_BCM2835=y ++CONFIG_WATCHDOG=y ++CONFIG_BCM2708_WDT=m ++CONFIG_BCM2835_WDT=m ++CONFIG_UCB1400_CORE=m ++CONFIG_MFD_STMPE=y ++CONFIG_STMPE_SPI=y ++CONFIG_MFD_ARIZONA_I2C=m ++CONFIG_MFD_ARIZONA_SPI=m ++CONFIG_MFD_WM5102=y ++CONFIG_MEDIA_SUPPORT=m ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++CONFIG_MEDIA_ANALOG_TV_SUPPORT=y ++CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y ++CONFIG_MEDIA_RADIO_SUPPORT=y ++CONFIG_MEDIA_RC_SUPPORT=y ++CONFIG_MEDIA_CONTROLLER=y ++CONFIG_LIRC=m ++CONFIG_RC_DEVICES=y ++CONFIG_RC_ATI_REMOTE=m ++CONFIG_IR_IMON=m ++CONFIG_IR_MCEUSB=m ++CONFIG_IR_REDRAT3=m ++CONFIG_IR_STREAMZAP=m ++CONFIG_IR_IGUANA=m ++CONFIG_IR_TTUSBIR=m ++CONFIG_RC_LOOPBACK=m ++CONFIG_IR_GPIO_CIR=m ++CONFIG_MEDIA_USB_SUPPORT=y ++CONFIG_USB_VIDEO_CLASS=m ++CONFIG_USB_M5602=m ++CONFIG_USB_STV06XX=m ++CONFIG_USB_GL860=m ++CONFIG_USB_GSPCA_BENQ=m ++CONFIG_USB_GSPCA_CONEX=m ++CONFIG_USB_GSPCA_CPIA1=m ++CONFIG_USB_GSPCA_DTCS033=m ++CONFIG_USB_GSPCA_ETOMS=m ++CONFIG_USB_GSPCA_FINEPIX=m ++CONFIG_USB_GSPCA_JEILINJ=m ++CONFIG_USB_GSPCA_JL2005BCD=m ++CONFIG_USB_GSPCA_KINECT=m ++CONFIG_USB_GSPCA_KONICA=m ++CONFIG_USB_GSPCA_MARS=m ++CONFIG_USB_GSPCA_MR97310A=m ++CONFIG_USB_GSPCA_NW80X=m ++CONFIG_USB_GSPCA_OV519=m ++CONFIG_USB_GSPCA_OV534=m ++CONFIG_USB_GSPCA_OV534_9=m ++CONFIG_USB_GSPCA_PAC207=m ++CONFIG_USB_GSPCA_PAC7302=m ++CONFIG_USB_GSPCA_PAC7311=m ++CONFIG_USB_GSPCA_SE401=m ++CONFIG_USB_GSPCA_SN9C2028=m ++CONFIG_USB_GSPCA_SN9C20X=m ++CONFIG_USB_GSPCA_SONIXB=m ++CONFIG_USB_GSPCA_SONIXJ=m ++CONFIG_USB_GSPCA_SPCA500=m ++CONFIG_USB_GSPCA_SPCA501=m ++CONFIG_USB_GSPCA_SPCA505=m ++CONFIG_USB_GSPCA_SPCA506=m ++CONFIG_USB_GSPCA_SPCA508=m ++CONFIG_USB_GSPCA_SPCA561=m ++CONFIG_USB_GSPCA_SPCA1528=m ++CONFIG_USB_GSPCA_SQ905=m ++CONFIG_USB_GSPCA_SQ905C=m ++CONFIG_USB_GSPCA_SQ930X=m ++CONFIG_USB_GSPCA_STK014=m ++CONFIG_USB_GSPCA_STK1135=m ++CONFIG_USB_GSPCA_STV0680=m ++CONFIG_USB_GSPCA_SUNPLUS=m ++CONFIG_USB_GSPCA_T613=m ++CONFIG_USB_GSPCA_TOPRO=m ++CONFIG_USB_GSPCA_TV8532=m ++CONFIG_USB_GSPCA_VC032X=m ++CONFIG_USB_GSPCA_VICAM=m ++CONFIG_USB_GSPCA_XIRLINK_CIT=m ++CONFIG_USB_GSPCA_ZC3XX=m ++CONFIG_USB_PWC=m ++CONFIG_VIDEO_CPIA2=m ++CONFIG_USB_ZR364XX=m ++CONFIG_USB_STKWEBCAM=m ++CONFIG_USB_S2255=m ++CONFIG_VIDEO_USBTV=m ++CONFIG_VIDEO_PVRUSB2=m ++CONFIG_VIDEO_HDPVR=m ++CONFIG_VIDEO_USBVISION=m ++CONFIG_VIDEO_STK1160_COMMON=m ++CONFIG_VIDEO_STK1160_AC97=y ++CONFIG_VIDEO_GO7007=m ++CONFIG_VIDEO_GO7007_USB=m ++CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m ++CONFIG_VIDEO_AU0828=m ++CONFIG_VIDEO_AU0828_RC=y ++CONFIG_VIDEO_CX231XX=m ++CONFIG_VIDEO_CX231XX_ALSA=m ++CONFIG_VIDEO_CX231XX_DVB=m ++CONFIG_VIDEO_TM6000=m ++CONFIG_VIDEO_TM6000_ALSA=m ++CONFIG_VIDEO_TM6000_DVB=m ++CONFIG_DVB_USB=m ++CONFIG_DVB_USB_A800=m ++CONFIG_DVB_USB_DIBUSB_MB=m ++CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y ++CONFIG_DVB_USB_DIBUSB_MC=m ++CONFIG_DVB_USB_DIB0700=m ++CONFIG_DVB_USB_UMT_010=m ++CONFIG_DVB_USB_CXUSB=m ++CONFIG_DVB_USB_M920X=m ++CONFIG_DVB_USB_DIGITV=m ++CONFIG_DVB_USB_VP7045=m ++CONFIG_DVB_USB_VP702X=m ++CONFIG_DVB_USB_GP8PSK=m ++CONFIG_DVB_USB_NOVA_T_USB2=m ++CONFIG_DVB_USB_TTUSB2=m ++CONFIG_DVB_USB_DTT200U=m ++CONFIG_DVB_USB_OPERA1=m ++CONFIG_DVB_USB_AF9005=m ++CONFIG_DVB_USB_AF9005_REMOTE=m ++CONFIG_DVB_USB_PCTV452E=m ++CONFIG_DVB_USB_DW2102=m ++CONFIG_DVB_USB_CINERGY_T2=m ++CONFIG_DVB_USB_DTV5100=m ++CONFIG_DVB_USB_FRIIO=m ++CONFIG_DVB_USB_AZ6027=m ++CONFIG_DVB_USB_TECHNISAT_USB2=m ++CONFIG_DVB_USB_V2=m ++CONFIG_DVB_USB_AF9015=m ++CONFIG_DVB_USB_AF9035=m ++CONFIG_DVB_USB_ANYSEE=m ++CONFIG_DVB_USB_AU6610=m ++CONFIG_DVB_USB_AZ6007=m ++CONFIG_DVB_USB_CE6230=m ++CONFIG_DVB_USB_EC168=m ++CONFIG_DVB_USB_GL861=m ++CONFIG_DVB_USB_LME2510=m ++CONFIG_DVB_USB_MXL111SF=m ++CONFIG_DVB_USB_RTL28XXU=m ++CONFIG_DVB_USB_DVBSKY=m ++CONFIG_SMS_USB_DRV=m ++CONFIG_DVB_B2C2_FLEXCOP_USB=m ++CONFIG_DVB_AS102=m ++CONFIG_VIDEO_EM28XX=m ++CONFIG_VIDEO_EM28XX_V4L2=m ++CONFIG_VIDEO_EM28XX_ALSA=m ++CONFIG_VIDEO_EM28XX_DVB=m ++CONFIG_V4L_PLATFORM_DRIVERS=y ++CONFIG_VIDEO_BCM2835=y ++CONFIG_VIDEO_BCM2835_MMAL=m ++CONFIG_RADIO_SI470X=y ++CONFIG_USB_SI470X=m ++CONFIG_I2C_SI470X=m ++CONFIG_RADIO_SI4713=m ++CONFIG_I2C_SI4713=m ++CONFIG_USB_MR800=m ++CONFIG_USB_DSBR=m ++CONFIG_RADIO_SHARK=m ++CONFIG_RADIO_SHARK2=m ++CONFIG_USB_KEENE=m ++CONFIG_USB_MA901=m ++CONFIG_RADIO_TEA5764=m ++CONFIG_RADIO_SAA7706H=m ++CONFIG_RADIO_TEF6862=m ++CONFIG_RADIO_WL1273=m ++CONFIG_RADIO_WL128X=m ++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set ++CONFIG_VIDEO_UDA1342=m ++CONFIG_VIDEO_SONY_BTF_MPX=m ++CONFIG_VIDEO_TVP5150=m ++CONFIG_VIDEO_TW2804=m ++CONFIG_VIDEO_TW9903=m ++CONFIG_VIDEO_TW9906=m ++CONFIG_VIDEO_OV7640=m ++CONFIG_VIDEO_MT9V011=m ++CONFIG_FB=y ++CONFIG_FB_BCM2708=y ++CONFIG_FB_UDL=m ++CONFIG_FB_SSD1307=m ++CONFIG_FB_RPISENSE=m ++# CONFIG_BACKLIGHT_GENERIC is not set ++CONFIG_BACKLIGHT_RPI=m ++CONFIG_BACKLIGHT_GPIO=m ++CONFIG_FRAMEBUFFER_CONSOLE=y ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++CONFIG_SOUND=y ++CONFIG_SND=m ++CONFIG_SND_SEQUENCER=m ++CONFIG_SND_SEQ_DUMMY=m ++CONFIG_SND_MIXER_OSS=m ++CONFIG_SND_PCM_OSS=m ++CONFIG_SND_SEQUENCER_OSS=y ++CONFIG_SND_HRTIMER=m ++CONFIG_SND_DUMMY=m ++CONFIG_SND_ALOOP=m ++CONFIG_SND_VIRMIDI=m ++CONFIG_SND_MTPAV=m ++CONFIG_SND_SERIAL_U16550=m ++CONFIG_SND_MPU401=m ++CONFIG_SND_BCM2835=m ++CONFIG_SND_USB_AUDIO=m ++CONFIG_SND_USB_UA101=m ++CONFIG_SND_USB_CAIAQ=m ++CONFIG_SND_USB_CAIAQ_INPUT=y ++CONFIG_SND_USB_6FIRE=m ++CONFIG_SND_SOC=m ++CONFIG_SND_BCM2708_SOC_I2S=m ++CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m ++CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m ++CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m ++CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m ++CONFIG_SND_BCM2708_SOC_RPI_DAC=m ++CONFIG_SND_BCM2708_SOC_RPI_PROTO=m ++CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m ++CONFIG_SND_BCM2708_SOC_RASPIDAC3=m ++CONFIG_SND_SOC_ADAU1701=m ++CONFIG_SND_SOC_WM8804_I2C=m ++CONFIG_SND_SIMPLE_CARD=m ++CONFIG_SOUND_PRIME=m ++CONFIG_HIDRAW=y ++CONFIG_UHID=m ++CONFIG_HID_A4TECH=m ++CONFIG_HID_ACRUX=m ++CONFIG_HID_APPLE=m ++CONFIG_HID_BELKIN=m ++CONFIG_HID_CHERRY=m ++CONFIG_HID_CHICONY=m ++CONFIG_HID_CYPRESS=m ++CONFIG_HID_DRAGONRISE=m ++CONFIG_HID_EMS_FF=m ++CONFIG_HID_ELECOM=m ++CONFIG_HID_ELO=m ++CONFIG_HID_EZKEY=m ++CONFIG_HID_HOLTEK=m ++CONFIG_HID_KEYTOUCH=m ++CONFIG_HID_KYE=m ++CONFIG_HID_UCLOGIC=m ++CONFIG_HID_WALTOP=m ++CONFIG_HID_GYRATION=m ++CONFIG_HID_TWINHAN=m ++CONFIG_HID_KENSINGTON=m ++CONFIG_HID_LCPOWER=m ++CONFIG_HID_LOGITECH=m ++CONFIG_HID_MAGICMOUSE=m ++CONFIG_HID_MICROSOFT=m ++CONFIG_HID_MONTEREY=m ++CONFIG_HID_MULTITOUCH=m ++CONFIG_HID_NTRIG=m ++CONFIG_HID_ORTEK=m ++CONFIG_HID_PANTHERLORD=m ++CONFIG_HID_PETALYNX=m ++CONFIG_HID_PICOLCD=m ++CONFIG_HID_ROCCAT=m ++CONFIG_HID_SAMSUNG=m ++CONFIG_HID_SONY=m ++CONFIG_HID_SPEEDLINK=m ++CONFIG_HID_SUNPLUS=m ++CONFIG_HID_GREENASIA=m ++CONFIG_HID_SMARTJOYPLUS=m ++CONFIG_HID_TOPSEED=m ++CONFIG_HID_THINGM=m ++CONFIG_HID_THRUSTMASTER=m ++CONFIG_HID_WACOM=m ++CONFIG_HID_WIIMOTE=m ++CONFIG_HID_XINMO=m ++CONFIG_HID_ZEROPLUS=m ++CONFIG_HID_ZYDACRON=m ++CONFIG_HID_PID=y ++CONFIG_USB_HIDDEV=y ++CONFIG_USB=y ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++CONFIG_USB_MON=m ++CONFIG_USB_DWCOTG=y ++CONFIG_USB_PRINTER=m ++CONFIG_USB_STORAGE=y ++CONFIG_USB_STORAGE_REALTEK=m ++CONFIG_USB_STORAGE_DATAFAB=m ++CONFIG_USB_STORAGE_FREECOM=m ++CONFIG_USB_STORAGE_ISD200=m ++CONFIG_USB_STORAGE_USBAT=m ++CONFIG_USB_STORAGE_SDDR09=m ++CONFIG_USB_STORAGE_SDDR55=m ++CONFIG_USB_STORAGE_JUMPSHOT=m ++CONFIG_USB_STORAGE_ALAUDA=m ++CONFIG_USB_STORAGE_ONETOUCH=m ++CONFIG_USB_STORAGE_KARMA=m ++CONFIG_USB_STORAGE_CYPRESS_ATACB=m ++CONFIG_USB_STORAGE_ENE_UB6250=m ++CONFIG_USB_MDC800=m ++CONFIG_USB_MICROTEK=m ++CONFIG_USBIP_CORE=m ++CONFIG_USBIP_VHCI_HCD=m ++CONFIG_USBIP_HOST=m ++CONFIG_USB_SERIAL=m ++CONFIG_USB_SERIAL_GENERIC=y ++CONFIG_USB_SERIAL_AIRCABLE=m ++CONFIG_USB_SERIAL_ARK3116=m ++CONFIG_USB_SERIAL_BELKIN=m ++CONFIG_USB_SERIAL_CH341=m ++CONFIG_USB_SERIAL_WHITEHEAT=m ++CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m ++CONFIG_USB_SERIAL_CP210X=m ++CONFIG_USB_SERIAL_CYPRESS_M8=m ++CONFIG_USB_SERIAL_EMPEG=m ++CONFIG_USB_SERIAL_FTDI_SIO=m ++CONFIG_USB_SERIAL_VISOR=m ++CONFIG_USB_SERIAL_IPAQ=m ++CONFIG_USB_SERIAL_IR=m ++CONFIG_USB_SERIAL_EDGEPORT=m ++CONFIG_USB_SERIAL_EDGEPORT_TI=m ++CONFIG_USB_SERIAL_F81232=m ++CONFIG_USB_SERIAL_GARMIN=m ++CONFIG_USB_SERIAL_IPW=m ++CONFIG_USB_SERIAL_IUU=m ++CONFIG_USB_SERIAL_KEYSPAN_PDA=m ++CONFIG_USB_SERIAL_KEYSPAN=m ++CONFIG_USB_SERIAL_KLSI=m ++CONFIG_USB_SERIAL_KOBIL_SCT=m ++CONFIG_USB_SERIAL_MCT_U232=m ++CONFIG_USB_SERIAL_METRO=m ++CONFIG_USB_SERIAL_MOS7720=m ++CONFIG_USB_SERIAL_MOS7840=m ++CONFIG_USB_SERIAL_NAVMAN=m ++CONFIG_USB_SERIAL_PL2303=m ++CONFIG_USB_SERIAL_OTI6858=m ++CONFIG_USB_SERIAL_QCAUX=m ++CONFIG_USB_SERIAL_QUALCOMM=m ++CONFIG_USB_SERIAL_SPCP8X5=m ++CONFIG_USB_SERIAL_SAFE=m ++CONFIG_USB_SERIAL_SIERRAWIRELESS=m ++CONFIG_USB_SERIAL_SYMBOL=m ++CONFIG_USB_SERIAL_TI=m ++CONFIG_USB_SERIAL_CYBERJACK=m ++CONFIG_USB_SERIAL_XIRCOM=m ++CONFIG_USB_SERIAL_OPTION=m ++CONFIG_USB_SERIAL_OMNINET=m ++CONFIG_USB_SERIAL_OPTICON=m ++CONFIG_USB_SERIAL_XSENS_MT=m ++CONFIG_USB_SERIAL_WISHBONE=m ++CONFIG_USB_SERIAL_SSU100=m ++CONFIG_USB_SERIAL_QT2=m ++CONFIG_USB_SERIAL_DEBUG=m ++CONFIG_USB_EMI62=m ++CONFIG_USB_EMI26=m ++CONFIG_USB_ADUTUX=m ++CONFIG_USB_SEVSEG=m ++CONFIG_USB_RIO500=m ++CONFIG_USB_LEGOTOWER=m ++CONFIG_USB_LCD=m ++CONFIG_USB_LED=m ++CONFIG_USB_CYPRESS_CY7C63=m ++CONFIG_USB_CYTHERM=m ++CONFIG_USB_IDMOUSE=m ++CONFIG_USB_FTDI_ELAN=m ++CONFIG_USB_APPLEDISPLAY=m ++CONFIG_USB_LD=m ++CONFIG_USB_TRANCEVIBRATOR=m ++CONFIG_USB_IOWARRIOR=m ++CONFIG_USB_TEST=m ++CONFIG_USB_ISIGHTFW=m ++CONFIG_USB_YUREX=m ++CONFIG_USB_ATM=m ++CONFIG_USB_SPEEDTOUCH=m ++CONFIG_USB_CXACRU=m ++CONFIG_USB_UEAGLEATM=m ++CONFIG_USB_XUSBATM=m ++CONFIG_MMC=y ++CONFIG_MMC_BLOCK_MINORS=32 ++CONFIG_MMC_BCM2835=y ++CONFIG_MMC_BCM2835_DMA=y ++CONFIG_MMC_BCM2835_SDHOST=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_PLTFM=y ++CONFIG_MMC_SPI=m ++CONFIG_LEDS_CLASS=y ++CONFIG_LEDS_GPIO=y ++CONFIG_LEDS_TRIGGER_TIMER=y ++CONFIG_LEDS_TRIGGER_ONESHOT=y ++CONFIG_LEDS_TRIGGER_HEARTBEAT=y ++CONFIG_LEDS_TRIGGER_BACKLIGHT=y ++CONFIG_LEDS_TRIGGER_CPU=y ++CONFIG_LEDS_TRIGGER_GPIO=y ++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y ++CONFIG_LEDS_TRIGGER_TRANSIENT=m ++CONFIG_LEDS_TRIGGER_CAMERA=m ++CONFIG_LEDS_TRIGGER_INPUT=y ++CONFIG_RTC_CLASS=y ++# CONFIG_RTC_HCTOSYS is not set ++CONFIG_RTC_DRV_DS1307=m ++CONFIG_RTC_DRV_DS1374=m ++CONFIG_RTC_DRV_DS1672=m ++CONFIG_RTC_DRV_DS3232=m ++CONFIG_RTC_DRV_MAX6900=m ++CONFIG_RTC_DRV_RS5C372=m ++CONFIG_RTC_DRV_ISL1208=m ++CONFIG_RTC_DRV_ISL12022=m ++CONFIG_RTC_DRV_ISL12057=m ++CONFIG_RTC_DRV_X1205=m ++CONFIG_RTC_DRV_PCF2127=m ++CONFIG_RTC_DRV_PCF8523=m ++CONFIG_RTC_DRV_PCF8563=m ++CONFIG_RTC_DRV_PCF8583=m ++CONFIG_RTC_DRV_M41T80=m ++CONFIG_RTC_DRV_BQ32K=m ++CONFIG_RTC_DRV_S35390A=m ++CONFIG_RTC_DRV_FM3130=m ++CONFIG_RTC_DRV_RX8581=m ++CONFIG_RTC_DRV_RX8025=m ++CONFIG_RTC_DRV_EM3027=m ++CONFIG_RTC_DRV_RV3029C2=m ++CONFIG_RTC_DRV_M41T93=m ++CONFIG_RTC_DRV_M41T94=m ++CONFIG_RTC_DRV_DS1305=m ++CONFIG_RTC_DRV_DS1390=m ++CONFIG_RTC_DRV_MAX6902=m ++CONFIG_RTC_DRV_R9701=m ++CONFIG_RTC_DRV_RS5C348=m ++CONFIG_RTC_DRV_DS3234=m ++CONFIG_RTC_DRV_PCF2123=m ++CONFIG_RTC_DRV_RX4581=m ++CONFIG_DMADEVICES=y ++CONFIG_DMA_BCM2708=y ++CONFIG_UIO=m ++CONFIG_UIO_PDRV_GENIRQ=m ++CONFIG_STAGING=y ++CONFIG_PRISM2_USB=m ++CONFIG_R8712U=m ++CONFIG_R8188EU=m ++CONFIG_R8723AU=m ++CONFIG_VT6656=m ++CONFIG_SPEAKUP=m ++CONFIG_SPEAKUP_SYNTH_SOFT=m ++CONFIG_STAGING_MEDIA=y ++CONFIG_LIRC_STAGING=y ++CONFIG_LIRC_IMON=m ++CONFIG_LIRC_RPI=m ++CONFIG_LIRC_SASEM=m ++CONFIG_LIRC_SERIAL=m ++CONFIG_FB_TFT=m ++CONFIG_FB_TFT_AGM1264K_FL=m ++CONFIG_FB_TFT_BD663474=m ++CONFIG_FB_TFT_HX8340BN=m ++CONFIG_FB_TFT_HX8347D=m ++CONFIG_FB_TFT_HX8353D=m ++CONFIG_FB_TFT_ILI9163=m ++CONFIG_FB_TFT_ILI9320=m ++CONFIG_FB_TFT_ILI9325=m ++CONFIG_FB_TFT_ILI9340=m ++CONFIG_FB_TFT_ILI9341=m ++CONFIG_FB_TFT_ILI9481=m ++CONFIG_FB_TFT_ILI9486=m ++CONFIG_FB_TFT_PCD8544=m ++CONFIG_FB_TFT_RA8875=m ++CONFIG_FB_TFT_S6D02A1=m ++CONFIG_FB_TFT_S6D1121=m ++CONFIG_FB_TFT_SSD1289=m ++CONFIG_FB_TFT_SSD1306=m ++CONFIG_FB_TFT_SSD1331=m ++CONFIG_FB_TFT_SSD1351=m ++CONFIG_FB_TFT_ST7735R=m ++CONFIG_FB_TFT_TINYLCD=m ++CONFIG_FB_TFT_TLS8204=m ++CONFIG_FB_TFT_UC1701=m ++CONFIG_FB_TFT_UPD161704=m ++CONFIG_FB_TFT_WATTEROTT=m ++CONFIG_FB_FLEX=m ++CONFIG_FB_TFT_FBTFT_DEVICE=m ++CONFIG_MAILBOX=y ++CONFIG_BCM2835_MBOX=y ++# CONFIG_IOMMU_SUPPORT is not set ++CONFIG_EXTCON=m ++CONFIG_EXTCON_ARIZONA=m ++CONFIG_IIO=m ++CONFIG_IIO_BUFFER=y ++CONFIG_IIO_BUFFER_CB=y ++CONFIG_IIO_KFIFO_BUF=m ++CONFIG_MCP320X=m ++CONFIG_DHT11=m ++CONFIG_PWM_BCM2835=m ++CONFIG_RASPBERRYPI_FIRMWARE=y ++CONFIG_EXT4_FS=y ++CONFIG_EXT4_FS_POSIX_ACL=y ++CONFIG_EXT4_FS_SECURITY=y ++CONFIG_REISERFS_FS=m ++CONFIG_REISERFS_FS_XATTR=y ++CONFIG_REISERFS_FS_POSIX_ACL=y ++CONFIG_REISERFS_FS_SECURITY=y ++CONFIG_JFS_FS=m ++CONFIG_JFS_POSIX_ACL=y ++CONFIG_JFS_SECURITY=y ++CONFIG_JFS_STATISTICS=y ++CONFIG_XFS_FS=m ++CONFIG_XFS_QUOTA=y ++CONFIG_XFS_POSIX_ACL=y ++CONFIG_XFS_RT=y ++CONFIG_GFS2_FS=m ++CONFIG_OCFS2_FS=m ++CONFIG_BTRFS_FS=m ++CONFIG_BTRFS_FS_POSIX_ACL=y ++CONFIG_NILFS2_FS=m ++CONFIG_F2FS_FS=y ++CONFIG_FANOTIFY=y ++CONFIG_QFMT_V1=m ++CONFIG_QFMT_V2=m ++CONFIG_AUTOFS4_FS=y ++CONFIG_FUSE_FS=m ++CONFIG_CUSE=m ++CONFIG_OVERLAY_FS=m ++CONFIG_FSCACHE=y ++CONFIG_FSCACHE_STATS=y ++CONFIG_FSCACHE_HISTOGRAM=y ++CONFIG_CACHEFILES=y ++CONFIG_ISO9660_FS=m ++CONFIG_JOLIET=y ++CONFIG_ZISOFS=y ++CONFIG_UDF_FS=m ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_IOCHARSET="ascii" ++CONFIG_NTFS_FS=m ++CONFIG_NTFS_RW=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_CONFIGFS_FS=y ++CONFIG_ECRYPT_FS=m ++CONFIG_HFS_FS=m ++CONFIG_HFSPLUS_FS=m ++CONFIG_JFFS2_FS=m ++CONFIG_JFFS2_SUMMARY=y ++CONFIG_UBIFS_FS=m ++CONFIG_SQUASHFS=m ++CONFIG_SQUASHFS_XATTR=y ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3_ACL=y ++CONFIG_NFS_V4=y ++CONFIG_NFS_SWAP=y ++CONFIG_ROOT_NFS=y ++CONFIG_NFS_FSCACHE=y ++CONFIG_NFSD=m ++CONFIG_NFSD_V3_ACL=y ++CONFIG_NFSD_V4=y ++CONFIG_CIFS=m ++CONFIG_CIFS_WEAK_PW_HASH=y ++CONFIG_CIFS_UPCALL=y ++CONFIG_CIFS_XATTR=y ++CONFIG_CIFS_POSIX=y ++CONFIG_CIFS_ACL=y ++CONFIG_CIFS_DFS_UPCALL=y ++CONFIG_CIFS_SMB2=y ++CONFIG_CIFS_FSCACHE=y ++CONFIG_9P_FS=m ++CONFIG_9P_FS_POSIX_ACL=y ++CONFIG_NLS_DEFAULT="utf8" ++CONFIG_NLS_CODEPAGE_437=y ++CONFIG_NLS_CODEPAGE_737=m ++CONFIG_NLS_CODEPAGE_775=m ++CONFIG_NLS_CODEPAGE_850=m ++CONFIG_NLS_CODEPAGE_852=m ++CONFIG_NLS_CODEPAGE_855=m ++CONFIG_NLS_CODEPAGE_857=m ++CONFIG_NLS_CODEPAGE_860=m ++CONFIG_NLS_CODEPAGE_861=m ++CONFIG_NLS_CODEPAGE_862=m ++CONFIG_NLS_CODEPAGE_863=m ++CONFIG_NLS_CODEPAGE_864=m ++CONFIG_NLS_CODEPAGE_865=m ++CONFIG_NLS_CODEPAGE_866=m ++CONFIG_NLS_CODEPAGE_869=m ++CONFIG_NLS_CODEPAGE_936=m ++CONFIG_NLS_CODEPAGE_950=m ++CONFIG_NLS_CODEPAGE_932=m ++CONFIG_NLS_CODEPAGE_949=m ++CONFIG_NLS_CODEPAGE_874=m ++CONFIG_NLS_ISO8859_8=m ++CONFIG_NLS_CODEPAGE_1250=m ++CONFIG_NLS_CODEPAGE_1251=m ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=m ++CONFIG_NLS_ISO8859_2=m ++CONFIG_NLS_ISO8859_3=m ++CONFIG_NLS_ISO8859_4=m ++CONFIG_NLS_ISO8859_5=m ++CONFIG_NLS_ISO8859_6=m ++CONFIG_NLS_ISO8859_7=m ++CONFIG_NLS_ISO8859_9=m ++CONFIG_NLS_ISO8859_13=m ++CONFIG_NLS_ISO8859_14=m ++CONFIG_NLS_ISO8859_15=m ++CONFIG_NLS_KOI8_R=m ++CONFIG_NLS_KOI8_U=m ++CONFIG_DLM=m ++CONFIG_PRINTK_TIME=y ++CONFIG_BOOT_PRINTK_DELAY=y ++CONFIG_DEBUG_MEMORY_INIT=y ++CONFIG_DETECT_HUNG_TASK=y ++CONFIG_TIMER_STATS=y ++# CONFIG_DEBUG_PREEMPT is not set ++CONFIG_IRQSOFF_TRACER=y ++CONFIG_SCHED_TRACER=y ++CONFIG_STACK_TRACER=y ++CONFIG_BLK_DEV_IO_TRACE=y ++# CONFIG_KPROBE_EVENT is not set ++CONFIG_FUNCTION_PROFILER=y ++CONFIG_KGDB=y ++CONFIG_KGDB_KDB=y ++CONFIG_KDB_KEYBOARD=y ++CONFIG_CRYPTO_USER=m ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTS=m ++CONFIG_CRYPTO_XTS=m ++CONFIG_CRYPTO_XCBC=m ++CONFIG_CRYPTO_TGR192=m ++CONFIG_CRYPTO_WP512=m ++CONFIG_CRYPTO_CAST5=m ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_USER_API_SKCIPHER=m ++# CONFIG_CRYPTO_HW is not set ++CONFIG_ARM_CRYPTO=y ++CONFIG_CRYPTO_SHA1_ARM_NEON=m ++CONFIG_CRYPTO_SHA512_ARM_NEON=m ++CONFIG_CRYPTO_AES_ARM_BS=m ++CONFIG_CRC_ITU_T=y ++CONFIG_LIBCRC32C=y +diff -Nur linux-4.1.13.orig/arch/arm/configs/bcm2835_defconfig linux-rpi/arch/arm/configs/bcm2835_defconfig +--- linux-4.1.13.orig/arch/arm/configs/bcm2835_defconfig 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/arch/arm/configs/bcm2835_defconfig 2015-11-29 09:42:34.707444982 +0100 +@@ -1,105 +1,1075 @@ + # CONFIG_LOCALVERSION_AUTO is not set + CONFIG_SYSVIPC=y ++CONFIG_POSIX_MQUEUE=y + CONFIG_FHANDLE=y + CONFIG_NO_HZ=y + CONFIG_HIGH_RES_TIMERS=y + CONFIG_BSD_PROCESS_ACCT=y + CONFIG_BSD_PROCESS_ACCT_V3=y ++CONFIG_TASKSTATS=y ++CONFIG_TASK_DELAY_ACCT=y ++CONFIG_TASK_XACCT=y ++CONFIG_TASK_IO_ACCOUNTING=y ++CONFIG_IKCONFIG=m ++CONFIG_IKCONFIG_PROC=y + CONFIG_LOG_BUF_SHIFT=18 + CONFIG_CGROUP_FREEZER=y + CONFIG_CGROUP_DEVICE=y + CONFIG_CPUSETS=y + CONFIG_CGROUP_CPUACCT=y +-CONFIG_RESOURCE_COUNTERS=y ++CONFIG_MEMCG=y + CONFIG_CGROUP_PERF=y + CONFIG_CFS_BANDWIDTH=y + CONFIG_RT_GROUP_SCHED=y ++CONFIG_BLK_CGROUP=y + CONFIG_NAMESPACES=y + CONFIG_SCHED_AUTOGROUP=y +-CONFIG_RELAY=y + CONFIG_BLK_DEV_INITRD=y +-CONFIG_RD_BZIP2=y +-CONFIG_RD_LZMA=y +-CONFIG_RD_XZ=y +-CONFIG_RD_LZO=y + CONFIG_CC_OPTIMIZE_FOR_SIZE=y +-CONFIG_KALLSYMS_ALL=y + CONFIG_EMBEDDED=y + # CONFIG_COMPAT_BRK is not set + CONFIG_PROFILING=y +-CONFIG_OPROFILE=y ++CONFIG_OPROFILE=m ++CONFIG_KPROBES=y + CONFIG_JUMP_LABEL=y ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++CONFIG_MODULES=y ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODVERSIONS=y ++CONFIG_MODULE_SRCVERSION_ALL=y ++CONFIG_BLK_DEV_THROTTLING=y ++CONFIG_PARTITION_ADVANCED=y ++CONFIG_MAC_PARTITION=y ++CONFIG_CFQ_GROUP_IOSCHED=y + CONFIG_ARCH_MULTI_V6=y + # CONFIG_ARCH_MULTI_V7 is not set + CONFIG_ARCH_BCM=y + CONFIG_ARCH_BCM2835=y +-CONFIG_PREEMPT_VOLUNTARY=y ++CONFIG_PREEMPT=y + CONFIG_AEABI=y ++CONFIG_OABI_COMPAT=y + CONFIG_KSM=y + CONFIG_CLEANCACHE=y ++CONFIG_FRONTSWAP=y ++CONFIG_CMA=y ++CONFIG_UACCESS_WITH_MEMCPY=y + CONFIG_SECCOMP=y +-CONFIG_CC_STACKPROTECTOR=y ++CONFIG_ZBOOT_ROM_TEXT=0x0 ++CONFIG_ZBOOT_ROM_BSS=0x0 + CONFIG_KEXEC=y + CONFIG_CRASH_DUMP=y ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_STAT=m ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y + CONFIG_VFP=y + # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_BINFMT_MISC=m + # CONFIG_SUSPEND is not set + CONFIG_NET=y + CONFIG_PACKET=y + CONFIG_UNIX=y ++CONFIG_XFRM_USER=y ++CONFIG_NET_KEY=m + CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++CONFIG_IP_MULTIPLE_TABLES=y ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++CONFIG_IP_PNP=y ++CONFIG_IP_PNP_DHCP=y ++CONFIG_IP_PNP_RARP=y ++CONFIG_NET_IPIP=m ++CONFIG_NET_IPGRE_DEMUX=m ++CONFIG_NET_IPGRE=m ++CONFIG_IP_MROUTE=y ++CONFIG_IP_MROUTE_MULTIPLE_TABLES=y ++CONFIG_IP_PIMSM_V1=y ++CONFIG_IP_PIMSM_V2=y ++CONFIG_SYN_COOKIES=y ++CONFIG_INET_AH=m ++CONFIG_INET_ESP=m ++CONFIG_INET_IPCOMP=m ++CONFIG_INET_XFRM_MODE_TRANSPORT=m ++CONFIG_INET_XFRM_MODE_TUNNEL=m ++CONFIG_INET_XFRM_MODE_BEET=m ++CONFIG_INET_LRO=m ++CONFIG_INET_DIAG=m ++CONFIG_INET6_AH=m ++CONFIG_INET6_ESP=m ++CONFIG_INET6_IPCOMP=m ++CONFIG_IPV6_TUNNEL=m ++CONFIG_IPV6_MULTIPLE_TABLES=y ++CONFIG_IPV6_MROUTE=y ++CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y ++CONFIG_IPV6_PIMSM_V2=y + CONFIG_NETWORK_SECMARK=y + CONFIG_NETFILTER=y +-CONFIG_CFG80211=y +-CONFIG_MAC80211=y ++CONFIG_NF_CONNTRACK=m ++CONFIG_NF_CONNTRACK_ZONES=y ++CONFIG_NF_CONNTRACK_EVENTS=y ++CONFIG_NF_CONNTRACK_TIMESTAMP=y ++CONFIG_NF_CT_PROTO_DCCP=m ++CONFIG_NF_CT_PROTO_UDPLITE=m ++CONFIG_NF_CONNTRACK_AMANDA=m ++CONFIG_NF_CONNTRACK_FTP=m ++CONFIG_NF_CONNTRACK_H323=m ++CONFIG_NF_CONNTRACK_IRC=m ++CONFIG_NF_CONNTRACK_NETBIOS_NS=m ++CONFIG_NF_CONNTRACK_SNMP=m ++CONFIG_NF_CONNTRACK_PPTP=m ++CONFIG_NF_CONNTRACK_SANE=m ++CONFIG_NF_CONNTRACK_SIP=m ++CONFIG_NF_CONNTRACK_TFTP=m ++CONFIG_NF_CT_NETLINK=m ++CONFIG_NETFILTER_XT_SET=m ++CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m ++CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m ++CONFIG_NETFILTER_XT_TARGET_CONNMARK=m ++CONFIG_NETFILTER_XT_TARGET_DSCP=m ++CONFIG_NETFILTER_XT_TARGET_HMARK=m ++CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m ++CONFIG_NETFILTER_XT_TARGET_LED=m ++CONFIG_NETFILTER_XT_TARGET_LOG=m ++CONFIG_NETFILTER_XT_TARGET_MARK=m ++CONFIG_NETFILTER_XT_TARGET_NFLOG=m ++CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m ++CONFIG_NETFILTER_XT_TARGET_NOTRACK=m ++CONFIG_NETFILTER_XT_TARGET_TEE=m ++CONFIG_NETFILTER_XT_TARGET_TPROXY=m ++CONFIG_NETFILTER_XT_TARGET_TRACE=m ++CONFIG_NETFILTER_XT_TARGET_TCPMSS=m ++CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m ++CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m ++CONFIG_NETFILTER_XT_MATCH_BPF=m ++CONFIG_NETFILTER_XT_MATCH_CLUSTER=m ++CONFIG_NETFILTER_XT_MATCH_COMMENT=m ++CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m ++CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m ++CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m ++CONFIG_NETFILTER_XT_MATCH_CONNMARK=m ++CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m ++CONFIG_NETFILTER_XT_MATCH_CPU=m ++CONFIG_NETFILTER_XT_MATCH_DCCP=m ++CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m ++CONFIG_NETFILTER_XT_MATCH_DSCP=m ++CONFIG_NETFILTER_XT_MATCH_ESP=m ++CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m ++CONFIG_NETFILTER_XT_MATCH_HELPER=m ++CONFIG_NETFILTER_XT_MATCH_IPRANGE=m ++CONFIG_NETFILTER_XT_MATCH_IPVS=m ++CONFIG_NETFILTER_XT_MATCH_LENGTH=m ++CONFIG_NETFILTER_XT_MATCH_LIMIT=m ++CONFIG_NETFILTER_XT_MATCH_MAC=m ++CONFIG_NETFILTER_XT_MATCH_MARK=m ++CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m ++CONFIG_NETFILTER_XT_MATCH_NFACCT=m ++CONFIG_NETFILTER_XT_MATCH_OSF=m ++CONFIG_NETFILTER_XT_MATCH_OWNER=m ++CONFIG_NETFILTER_XT_MATCH_POLICY=m ++CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m ++CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m ++CONFIG_NETFILTER_XT_MATCH_QUOTA=m ++CONFIG_NETFILTER_XT_MATCH_RATEEST=m ++CONFIG_NETFILTER_XT_MATCH_REALM=m ++CONFIG_NETFILTER_XT_MATCH_RECENT=m ++CONFIG_NETFILTER_XT_MATCH_SOCKET=m ++CONFIG_NETFILTER_XT_MATCH_STATE=m ++CONFIG_NETFILTER_XT_MATCH_STATISTIC=m ++CONFIG_NETFILTER_XT_MATCH_STRING=m ++CONFIG_NETFILTER_XT_MATCH_TCPMSS=m ++CONFIG_NETFILTER_XT_MATCH_TIME=m ++CONFIG_NETFILTER_XT_MATCH_U32=m ++CONFIG_IP_SET=m ++CONFIG_IP_SET_BITMAP_IP=m ++CONFIG_IP_SET_BITMAP_IPMAC=m ++CONFIG_IP_SET_BITMAP_PORT=m ++CONFIG_IP_SET_HASH_IP=m ++CONFIG_IP_SET_HASH_IPPORT=m ++CONFIG_IP_SET_HASH_IPPORTIP=m ++CONFIG_IP_SET_HASH_IPPORTNET=m ++CONFIG_IP_SET_HASH_NET=m ++CONFIG_IP_SET_HASH_NETPORT=m ++CONFIG_IP_SET_HASH_NETIFACE=m ++CONFIG_IP_SET_LIST_SET=m ++CONFIG_IP_VS=m ++CONFIG_IP_VS_PROTO_TCP=y ++CONFIG_IP_VS_PROTO_UDP=y ++CONFIG_IP_VS_PROTO_ESP=y ++CONFIG_IP_VS_PROTO_AH=y ++CONFIG_IP_VS_PROTO_SCTP=y ++CONFIG_IP_VS_RR=m ++CONFIG_IP_VS_WRR=m ++CONFIG_IP_VS_LC=m ++CONFIG_IP_VS_WLC=m ++CONFIG_IP_VS_LBLC=m ++CONFIG_IP_VS_LBLCR=m ++CONFIG_IP_VS_DH=m ++CONFIG_IP_VS_SH=m ++CONFIG_IP_VS_SED=m ++CONFIG_IP_VS_NQ=m ++CONFIG_IP_VS_FTP=m ++CONFIG_IP_VS_PE_SIP=m ++CONFIG_NF_CONNTRACK_IPV4=m ++CONFIG_IP_NF_IPTABLES=m ++CONFIG_IP_NF_MATCH_AH=m ++CONFIG_IP_NF_MATCH_ECN=m ++CONFIG_IP_NF_MATCH_TTL=m ++CONFIG_IP_NF_FILTER=m ++CONFIG_IP_NF_TARGET_REJECT=m ++CONFIG_IP_NF_NAT=m ++CONFIG_IP_NF_TARGET_MASQUERADE=m ++CONFIG_IP_NF_TARGET_NETMAP=m ++CONFIG_IP_NF_TARGET_REDIRECT=m ++CONFIG_IP_NF_MANGLE=m ++CONFIG_IP_NF_TARGET_CLUSTERIP=m ++CONFIG_IP_NF_TARGET_ECN=m ++CONFIG_IP_NF_TARGET_TTL=m ++CONFIG_IP_NF_RAW=m ++CONFIG_IP_NF_ARPTABLES=m ++CONFIG_IP_NF_ARPFILTER=m ++CONFIG_IP_NF_ARP_MANGLE=m ++CONFIG_NF_CONNTRACK_IPV6=m ++CONFIG_IP6_NF_IPTABLES=m ++CONFIG_IP6_NF_MATCH_AH=m ++CONFIG_IP6_NF_MATCH_EUI64=m ++CONFIG_IP6_NF_MATCH_FRAG=m ++CONFIG_IP6_NF_MATCH_OPTS=m ++CONFIG_IP6_NF_MATCH_HL=m ++CONFIG_IP6_NF_MATCH_IPV6HEADER=m ++CONFIG_IP6_NF_MATCH_MH=m ++CONFIG_IP6_NF_MATCH_RT=m ++CONFIG_IP6_NF_TARGET_HL=m ++CONFIG_IP6_NF_FILTER=m ++CONFIG_IP6_NF_TARGET_REJECT=m ++CONFIG_IP6_NF_MANGLE=m ++CONFIG_IP6_NF_RAW=m ++CONFIG_IP6_NF_NAT=m ++CONFIG_IP6_NF_TARGET_MASQUERADE=m ++CONFIG_IP6_NF_TARGET_NPT=m ++CONFIG_BRIDGE_NF_EBTABLES=m ++CONFIG_BRIDGE_EBT_BROUTE=m ++CONFIG_BRIDGE_EBT_T_FILTER=m ++CONFIG_BRIDGE_EBT_T_NAT=m ++CONFIG_BRIDGE_EBT_802_3=m ++CONFIG_BRIDGE_EBT_AMONG=m ++CONFIG_BRIDGE_EBT_ARP=m ++CONFIG_BRIDGE_EBT_IP=m ++CONFIG_BRIDGE_EBT_IP6=m ++CONFIG_BRIDGE_EBT_LIMIT=m ++CONFIG_BRIDGE_EBT_MARK=m ++CONFIG_BRIDGE_EBT_PKTTYPE=m ++CONFIG_BRIDGE_EBT_STP=m ++CONFIG_BRIDGE_EBT_VLAN=m ++CONFIG_BRIDGE_EBT_ARPREPLY=m ++CONFIG_BRIDGE_EBT_DNAT=m ++CONFIG_BRIDGE_EBT_MARK_T=m ++CONFIG_BRIDGE_EBT_REDIRECT=m ++CONFIG_BRIDGE_EBT_SNAT=m ++CONFIG_BRIDGE_EBT_LOG=m ++CONFIG_BRIDGE_EBT_NFLOG=m ++CONFIG_SCTP_COOKIE_HMAC_SHA1=y ++CONFIG_ATM=m ++CONFIG_L2TP=m ++CONFIG_L2TP_V3=y ++CONFIG_L2TP_IP=m ++CONFIG_L2TP_ETH=m ++CONFIG_BRIDGE=m ++CONFIG_VLAN_8021Q=m ++CONFIG_VLAN_8021Q_GVRP=y ++CONFIG_ATALK=m ++CONFIG_6LOWPAN=m ++CONFIG_NET_SCHED=y ++CONFIG_NET_SCH_CBQ=m ++CONFIG_NET_SCH_HTB=m ++CONFIG_NET_SCH_HFSC=m ++CONFIG_NET_SCH_PRIO=m ++CONFIG_NET_SCH_MULTIQ=m ++CONFIG_NET_SCH_RED=m ++CONFIG_NET_SCH_SFB=m ++CONFIG_NET_SCH_SFQ=m ++CONFIG_NET_SCH_TEQL=m ++CONFIG_NET_SCH_TBF=m ++CONFIG_NET_SCH_GRED=m ++CONFIG_NET_SCH_DSMARK=m ++CONFIG_NET_SCH_NETEM=m ++CONFIG_NET_SCH_DRR=m ++CONFIG_NET_SCH_MQPRIO=m ++CONFIG_NET_SCH_CHOKE=m ++CONFIG_NET_SCH_QFQ=m ++CONFIG_NET_SCH_CODEL=m ++CONFIG_NET_SCH_FQ_CODEL=m ++CONFIG_NET_SCH_INGRESS=m ++CONFIG_NET_SCH_PLUG=m ++CONFIG_NET_CLS_BASIC=m ++CONFIG_NET_CLS_TCINDEX=m ++CONFIG_NET_CLS_ROUTE4=m ++CONFIG_NET_CLS_FW=m ++CONFIG_NET_CLS_U32=m ++CONFIG_CLS_U32_MARK=y ++CONFIG_NET_CLS_RSVP=m ++CONFIG_NET_CLS_RSVP6=m ++CONFIG_NET_CLS_FLOW=m ++CONFIG_NET_CLS_CGROUP=m ++CONFIG_NET_EMATCH=y ++CONFIG_NET_EMATCH_CMP=m ++CONFIG_NET_EMATCH_NBYTE=m ++CONFIG_NET_EMATCH_U32=m ++CONFIG_NET_EMATCH_META=m ++CONFIG_NET_EMATCH_TEXT=m ++CONFIG_NET_EMATCH_IPSET=m ++CONFIG_NET_CLS_ACT=y ++CONFIG_NET_ACT_POLICE=m ++CONFIG_NET_ACT_GACT=m ++CONFIG_GACT_PROB=y ++CONFIG_NET_ACT_MIRRED=m ++CONFIG_NET_ACT_IPT=m ++CONFIG_NET_ACT_NAT=m ++CONFIG_NET_ACT_PEDIT=m ++CONFIG_NET_ACT_SIMP=m ++CONFIG_NET_ACT_SKBEDIT=m ++CONFIG_NET_ACT_CSUM=m ++CONFIG_BATMAN_ADV=m ++CONFIG_OPENVSWITCH=m ++CONFIG_NET_PKTGEN=m ++CONFIG_HAMRADIO=y ++CONFIG_AX25=m ++CONFIG_NETROM=m ++CONFIG_ROSE=m ++CONFIG_MKISS=m ++CONFIG_6PACK=m ++CONFIG_BPQETHER=m ++CONFIG_BAYCOM_SER_FDX=m ++CONFIG_BAYCOM_SER_HDX=m ++CONFIG_YAM=m ++CONFIG_CAN=m ++CONFIG_CAN_VCAN=m ++CONFIG_CAN_MCP251X=m ++CONFIG_IRDA=m ++CONFIG_IRLAN=m ++CONFIG_IRNET=m ++CONFIG_IRCOMM=m ++CONFIG_IRDA_ULTRA=y ++CONFIG_IRDA_CACHE_LAST_LSAP=y ++CONFIG_IRDA_FAST_RR=y ++CONFIG_IRTTY_SIR=m ++CONFIG_KINGSUN_DONGLE=m ++CONFIG_KSDAZZLE_DONGLE=m ++CONFIG_KS959_DONGLE=m ++CONFIG_USB_IRDA=m ++CONFIG_SIGMATEL_FIR=m ++CONFIG_MCS_FIR=m ++CONFIG_BT=m ++CONFIG_BT_RFCOMM=m ++CONFIG_BT_RFCOMM_TTY=y ++CONFIG_BT_BNEP=m ++CONFIG_BT_BNEP_MC_FILTER=y ++CONFIG_BT_BNEP_PROTO_FILTER=y ++CONFIG_BT_HIDP=m ++CONFIG_BT_6LOWPAN=m ++CONFIG_BT_HCIBTUSB=m ++CONFIG_BT_HCIBCM203X=m ++CONFIG_BT_HCIBPA10X=m ++CONFIG_BT_HCIBFUSB=m ++CONFIG_BT_HCIVHCI=m ++CONFIG_BT_MRVL=m ++CONFIG_BT_MRVL_SDIO=m ++CONFIG_BT_ATH3K=m ++CONFIG_BT_WILINK=m ++CONFIG_MAC80211=m ++CONFIG_MAC80211_MESH=y ++CONFIG_WIMAX=m ++CONFIG_RFKILL=m ++CONFIG_RFKILL_INPUT=y ++CONFIG_NET_9P=m ++CONFIG_NFC=m ++CONFIG_NFC_PN533=m + CONFIG_DEVTMPFS=y + CONFIG_DEVTMPFS_MOUNT=y + # CONFIG_STANDALONE is not set ++CONFIG_DMA_CMA=y ++CONFIG_CMA_SIZE_MBYTES=5 ++CONFIG_BLK_DEV_LOOP=y ++CONFIG_BLK_DEV_CRYPTOLOOP=m ++CONFIG_BLK_DEV_DRBD=m ++CONFIG_BLK_DEV_NBD=m ++CONFIG_BLK_DEV_RAM=y ++CONFIG_CDROM_PKTCDVD=m ++CONFIG_ATA_OVER_ETH=m ++CONFIG_EEPROM_AT24=m ++CONFIG_TI_ST=m + CONFIG_SCSI=y ++# CONFIG_SCSI_PROC_FS is not set + CONFIG_BLK_DEV_SD=y +-CONFIG_SCSI_MULTI_LUN=y ++CONFIG_CHR_DEV_ST=m ++CONFIG_CHR_DEV_OSST=m ++CONFIG_BLK_DEV_SR=m ++CONFIG_CHR_DEV_SG=m + CONFIG_SCSI_CONSTANTS=y + CONFIG_SCSI_SCAN_ASYNC=y ++CONFIG_SCSI_ISCSI_ATTRS=y ++CONFIG_ISCSI_TCP=m ++CONFIG_ISCSI_BOOT_SYSFS=m ++CONFIG_MD=y ++CONFIG_MD_LINEAR=m ++CONFIG_MD_RAID0=m ++CONFIG_BLK_DEV_DM=m ++CONFIG_DM_CRYPT=m ++CONFIG_DM_SNAPSHOT=m ++CONFIG_DM_MIRROR=m ++CONFIG_DM_LOG_USERSPACE=m ++CONFIG_DM_RAID=m ++CONFIG_DM_ZERO=m ++CONFIG_DM_DELAY=m + CONFIG_NETDEVICES=y ++CONFIG_BONDING=m ++CONFIG_DUMMY=m ++CONFIG_IFB=m ++CONFIG_MACVLAN=m ++CONFIG_NETCONSOLE=m ++CONFIG_TUN=m ++CONFIG_VETH=m ++CONFIG_ENC28J60=m ++CONFIG_MDIO_BITBANG=m ++CONFIG_PPP=m ++CONFIG_PPP_BSDCOMP=m ++CONFIG_PPP_DEFLATE=m ++CONFIG_PPP_FILTER=y ++CONFIG_PPP_MPPE=m ++CONFIG_PPP_MULTILINK=y ++CONFIG_PPPOATM=m ++CONFIG_PPPOE=m ++CONFIG_PPPOL2TP=m ++CONFIG_PPP_ASYNC=m ++CONFIG_PPP_SYNC_TTY=m ++CONFIG_SLIP=m ++CONFIG_SLIP_COMPRESSED=y ++CONFIG_SLIP_SMART=y ++CONFIG_USB_CATC=m ++CONFIG_USB_KAWETH=m ++CONFIG_USB_PEGASUS=m ++CONFIG_USB_RTL8150=m ++CONFIG_USB_RTL8152=m + CONFIG_USB_USBNET=y ++CONFIG_USB_NET_AX8817X=m ++CONFIG_USB_NET_AX88179_178A=m ++CONFIG_USB_NET_CDCETHER=m ++CONFIG_USB_NET_CDC_EEM=m ++CONFIG_USB_NET_CDC_NCM=m ++CONFIG_USB_NET_HUAWEI_CDC_NCM=m ++CONFIG_USB_NET_CDC_MBIM=m ++CONFIG_USB_NET_DM9601=m ++CONFIG_USB_NET_SR9700=m ++CONFIG_USB_NET_SR9800=m ++CONFIG_USB_NET_SMSC75XX=m + CONFIG_USB_NET_SMSC95XX=y +-CONFIG_ZD1211RW=y +-CONFIG_INPUT_EVDEV=y ++CONFIG_USB_NET_GL620A=m ++CONFIG_USB_NET_NET1080=m ++CONFIG_USB_NET_PLUSB=m ++CONFIG_USB_NET_MCS7830=m ++CONFIG_USB_NET_CDC_SUBSET=m ++CONFIG_USB_ALI_M5632=y ++CONFIG_USB_AN2720=y ++CONFIG_USB_EPSON2888=y ++CONFIG_USB_KC2190=y ++CONFIG_USB_NET_ZAURUS=m ++CONFIG_USB_NET_CX82310_ETH=m ++CONFIG_USB_NET_KALMIA=m ++CONFIG_USB_NET_QMI_WWAN=m ++CONFIG_USB_HSO=m ++CONFIG_USB_NET_INT51X1=m ++CONFIG_USB_IPHETH=m ++CONFIG_USB_SIERRA_NET=m ++CONFIG_USB_VL600=m ++CONFIG_LIBERTAS_THINFIRM=m ++CONFIG_LIBERTAS_THINFIRM_USB=m ++CONFIG_AT76C50X_USB=m ++CONFIG_USB_ZD1201=m ++CONFIG_USB_NET_RNDIS_WLAN=m ++CONFIG_RTL8187=m ++CONFIG_MAC80211_HWSIM=m ++CONFIG_ATH_CARDS=m ++CONFIG_ATH9K=m ++CONFIG_ATH9K_HTC=m ++CONFIG_CARL9170=m ++CONFIG_ATH6KL=m ++CONFIG_ATH6KL_USB=m ++CONFIG_AR5523=m ++CONFIG_B43=m ++# CONFIG_B43_PHY_N is not set ++CONFIG_B43LEGACY=m ++CONFIG_BRCMFMAC=m ++CONFIG_BRCMFMAC_USB=y ++CONFIG_HOSTAP=m ++CONFIG_LIBERTAS=m ++CONFIG_LIBERTAS_USB=m ++CONFIG_LIBERTAS_SDIO=m ++CONFIG_P54_COMMON=m ++CONFIG_P54_USB=m ++CONFIG_RT2X00=m ++CONFIG_RT2500USB=m ++CONFIG_RT73USB=m ++CONFIG_RT2800USB=m ++CONFIG_RT2800USB_RT3573=y ++CONFIG_RT2800USB_RT53XX=y ++CONFIG_RT2800USB_RT55XX=y ++CONFIG_RT2800USB_UNKNOWN=y ++CONFIG_RTL8192CU=m ++CONFIG_ZD1211RW=m ++CONFIG_MWIFIEX=m ++CONFIG_MWIFIEX_SDIO=m ++CONFIG_WIMAX_I2400M_USB=m ++CONFIG_INPUT_POLLDEV=m ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_JOYDEV=m ++CONFIG_INPUT_EVDEV=m ++# CONFIG_KEYBOARD_ATKBD is not set ++CONFIG_KEYBOARD_GPIO=m ++# CONFIG_INPUT_MOUSE is not set ++CONFIG_INPUT_JOYSTICK=y ++CONFIG_JOYSTICK_IFORCE=m ++CONFIG_JOYSTICK_IFORCE_USB=y ++CONFIG_JOYSTICK_XPAD=m ++CONFIG_JOYSTICK_XPAD_FF=y ++CONFIG_INPUT_TOUCHSCREEN=y ++CONFIG_TOUCHSCREEN_ADS7846=m ++CONFIG_TOUCHSCREEN_EGALAX=m ++CONFIG_TOUCHSCREEN_USB_COMPOSITE=m ++CONFIG_TOUCHSCREEN_STMPE=m ++CONFIG_INPUT_MISC=y ++CONFIG_INPUT_AD714X=m ++CONFIG_INPUT_ATI_REMOTE2=m ++CONFIG_INPUT_KEYSPAN_REMOTE=m ++CONFIG_INPUT_POWERMATE=m ++CONFIG_INPUT_YEALINK=m ++CONFIG_INPUT_CM109=m ++CONFIG_INPUT_UINPUT=m ++CONFIG_INPUT_GPIO_ROTARY_ENCODER=m ++CONFIG_INPUT_ADXL34X=m ++CONFIG_INPUT_CMA3000=m ++CONFIG_SERIO=m ++CONFIG_SERIO_RAW=m ++CONFIG_GAMEPORT=m ++CONFIG_GAMEPORT_NS558=m ++CONFIG_GAMEPORT_L4=m ++CONFIG_DEVPTS_MULTIPLE_INSTANCES=y + # CONFIG_LEGACY_PTYS is not set + # CONFIG_DEVKMEM is not set + CONFIG_SERIAL_AMBA_PL011=y + CONFIG_SERIAL_AMBA_PL011_CONSOLE=y + CONFIG_TTY_PRINTK=y ++CONFIG_HW_RANDOM=y ++CONFIG_HW_RANDOM_BCM2835=m ++CONFIG_RAW_DRIVER=y ++CONFIG_BRCM_CHAR_DRIVERS=y ++CONFIG_BCM_VC_CMA=y ++CONFIG_BCM_VCIO=y ++CONFIG_BCM_VC_SM=y + CONFIG_I2C=y +-CONFIG_I2C_CHARDEV=y ++CONFIG_I2C_CHARDEV=m + CONFIG_I2C_BCM2835=y + CONFIG_SPI=y +-CONFIG_SPI_BCM2835=y ++CONFIG_SPI_BCM2835=m ++CONFIG_SPI_SPIDEV=y ++CONFIG_PPS=m ++CONFIG_PPS_CLIENT_LDISC=m ++CONFIG_PPS_CLIENT_GPIO=m + CONFIG_GPIO_SYSFS=y ++CONFIG_GPIO_ARIZONA=m ++CONFIG_GPIO_STMPE=y ++CONFIG_W1=m ++CONFIG_W1_MASTER_DS2490=m ++CONFIG_W1_MASTER_DS2482=m ++CONFIG_W1_MASTER_DS1WM=m ++CONFIG_W1_MASTER_GPIO=m ++CONFIG_W1_SLAVE_THERM=m ++CONFIG_W1_SLAVE_SMEM=m ++CONFIG_W1_SLAVE_DS2408=m ++CONFIG_W1_SLAVE_DS2413=m ++CONFIG_W1_SLAVE_DS2406=m ++CONFIG_W1_SLAVE_DS2423=m ++CONFIG_W1_SLAVE_DS2431=m ++CONFIG_W1_SLAVE_DS2433=m ++CONFIG_W1_SLAVE_DS2760=m ++CONFIG_W1_SLAVE_DS2780=m ++CONFIG_W1_SLAVE_DS2781=m ++CONFIG_W1_SLAVE_DS28E04=m ++CONFIG_W1_SLAVE_BQ27000=m ++CONFIG_BATTERY_DS2760=m + # CONFIG_HWMON is not set ++CONFIG_THERMAL=y ++CONFIG_THERMAL_BCM2835=y ++CONFIG_WATCHDOG=y ++CONFIG_BCM2835_WDT=y ++CONFIG_UCB1400_CORE=m ++CONFIG_MFD_STMPE=y ++CONFIG_STMPE_SPI=y ++CONFIG_MFD_ARIZONA_I2C=m ++CONFIG_MFD_ARIZONA_SPI=m ++CONFIG_MFD_WM5102=y ++CONFIG_MEDIA_SUPPORT=m ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++CONFIG_MEDIA_ANALOG_TV_SUPPORT=y ++CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y ++CONFIG_MEDIA_RADIO_SUPPORT=y ++CONFIG_MEDIA_RC_SUPPORT=y ++CONFIG_MEDIA_CONTROLLER=y ++CONFIG_LIRC=m ++CONFIG_RC_DEVICES=y ++CONFIG_RC_ATI_REMOTE=m ++CONFIG_IR_IMON=m ++CONFIG_IR_MCEUSB=m ++CONFIG_IR_REDRAT3=m ++CONFIG_IR_STREAMZAP=m ++CONFIG_IR_IGUANA=m ++CONFIG_IR_TTUSBIR=m ++CONFIG_RC_LOOPBACK=m ++CONFIG_IR_GPIO_CIR=m ++CONFIG_MEDIA_USB_SUPPORT=y ++CONFIG_USB_VIDEO_CLASS=m ++CONFIG_USB_M5602=m ++CONFIG_USB_STV06XX=m ++CONFIG_USB_GL860=m ++CONFIG_USB_GSPCA_BENQ=m ++CONFIG_USB_GSPCA_CONEX=m ++CONFIG_USB_GSPCA_CPIA1=m ++CONFIG_USB_GSPCA_DTCS033=m ++CONFIG_USB_GSPCA_ETOMS=m ++CONFIG_USB_GSPCA_FINEPIX=m ++CONFIG_USB_GSPCA_JEILINJ=m ++CONFIG_USB_GSPCA_JL2005BCD=m ++CONFIG_USB_GSPCA_KINECT=m ++CONFIG_USB_GSPCA_KONICA=m ++CONFIG_USB_GSPCA_MARS=m ++CONFIG_USB_GSPCA_MR97310A=m ++CONFIG_USB_GSPCA_NW80X=m ++CONFIG_USB_GSPCA_OV519=m ++CONFIG_USB_GSPCA_OV534=m ++CONFIG_USB_GSPCA_OV534_9=m ++CONFIG_USB_GSPCA_PAC207=m ++CONFIG_USB_GSPCA_PAC7302=m ++CONFIG_USB_GSPCA_PAC7311=m ++CONFIG_USB_GSPCA_SE401=m ++CONFIG_USB_GSPCA_SN9C2028=m ++CONFIG_USB_GSPCA_SN9C20X=m ++CONFIG_USB_GSPCA_SONIXB=m ++CONFIG_USB_GSPCA_SONIXJ=m ++CONFIG_USB_GSPCA_SPCA500=m ++CONFIG_USB_GSPCA_SPCA501=m ++CONFIG_USB_GSPCA_SPCA505=m ++CONFIG_USB_GSPCA_SPCA506=m ++CONFIG_USB_GSPCA_SPCA508=m ++CONFIG_USB_GSPCA_SPCA561=m ++CONFIG_USB_GSPCA_SPCA1528=m ++CONFIG_USB_GSPCA_SQ905=m ++CONFIG_USB_GSPCA_SQ905C=m ++CONFIG_USB_GSPCA_SQ930X=m ++CONFIG_USB_GSPCA_STK014=m ++CONFIG_USB_GSPCA_STK1135=m ++CONFIG_USB_GSPCA_STV0680=m ++CONFIG_USB_GSPCA_SUNPLUS=m ++CONFIG_USB_GSPCA_T613=m ++CONFIG_USB_GSPCA_TOPRO=m ++CONFIG_USB_GSPCA_TV8532=m ++CONFIG_USB_GSPCA_VC032X=m ++CONFIG_USB_GSPCA_VICAM=m ++CONFIG_USB_GSPCA_XIRLINK_CIT=m ++CONFIG_USB_GSPCA_ZC3XX=m ++CONFIG_USB_PWC=m ++CONFIG_VIDEO_CPIA2=m ++CONFIG_USB_ZR364XX=m ++CONFIG_USB_STKWEBCAM=m ++CONFIG_USB_S2255=m ++CONFIG_VIDEO_USBTV=m ++CONFIG_VIDEO_PVRUSB2=m ++CONFIG_VIDEO_HDPVR=m ++CONFIG_VIDEO_USBVISION=m ++CONFIG_VIDEO_STK1160_COMMON=m ++CONFIG_VIDEO_STK1160_AC97=y ++CONFIG_VIDEO_GO7007=m ++CONFIG_VIDEO_GO7007_USB=m ++CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m ++CONFIG_VIDEO_AU0828=m ++CONFIG_VIDEO_AU0828_RC=y ++CONFIG_VIDEO_CX231XX=m ++CONFIG_VIDEO_CX231XX_ALSA=m ++CONFIG_VIDEO_CX231XX_DVB=m ++CONFIG_VIDEO_TM6000=m ++CONFIG_VIDEO_TM6000_ALSA=m ++CONFIG_VIDEO_TM6000_DVB=m ++CONFIG_DVB_USB=m ++CONFIG_DVB_USB_A800=m ++CONFIG_DVB_USB_DIBUSB_MB=m ++CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y ++CONFIG_DVB_USB_DIBUSB_MC=m ++CONFIG_DVB_USB_DIB0700=m ++CONFIG_DVB_USB_UMT_010=m ++CONFIG_DVB_USB_CXUSB=m ++CONFIG_DVB_USB_M920X=m ++CONFIG_DVB_USB_DIGITV=m ++CONFIG_DVB_USB_VP7045=m ++CONFIG_DVB_USB_VP702X=m ++CONFIG_DVB_USB_GP8PSK=m ++CONFIG_DVB_USB_NOVA_T_USB2=m ++CONFIG_DVB_USB_TTUSB2=m ++CONFIG_DVB_USB_DTT200U=m ++CONFIG_DVB_USB_OPERA1=m ++CONFIG_DVB_USB_AF9005=m ++CONFIG_DVB_USB_AF9005_REMOTE=m ++CONFIG_DVB_USB_PCTV452E=m ++CONFIG_DVB_USB_DW2102=m ++CONFIG_DVB_USB_CINERGY_T2=m ++CONFIG_DVB_USB_DTV5100=m ++CONFIG_DVB_USB_FRIIO=m ++CONFIG_DVB_USB_AZ6027=m ++CONFIG_DVB_USB_TECHNISAT_USB2=m ++CONFIG_DVB_USB_V2=m ++CONFIG_DVB_USB_AF9015=m ++CONFIG_DVB_USB_AF9035=m ++CONFIG_DVB_USB_ANYSEE=m ++CONFIG_DVB_USB_AU6610=m ++CONFIG_DVB_USB_AZ6007=m ++CONFIG_DVB_USB_CE6230=m ++CONFIG_DVB_USB_EC168=m ++CONFIG_DVB_USB_GL861=m ++CONFIG_DVB_USB_LME2510=m ++CONFIG_DVB_USB_MXL111SF=m ++CONFIG_DVB_USB_RTL28XXU=m ++CONFIG_DVB_USB_DVBSKY=m ++CONFIG_SMS_USB_DRV=m ++CONFIG_DVB_B2C2_FLEXCOP_USB=m ++CONFIG_DVB_AS102=m ++CONFIG_VIDEO_EM28XX=m ++CONFIG_VIDEO_EM28XX_V4L2=m ++CONFIG_VIDEO_EM28XX_ALSA=m ++CONFIG_VIDEO_EM28XX_DVB=m ++CONFIG_V4L_PLATFORM_DRIVERS=y ++CONFIG_VIDEO_BCM2835=y ++CONFIG_VIDEO_BCM2835_MMAL=m ++CONFIG_RADIO_SI470X=y ++CONFIG_USB_SI470X=m ++CONFIG_I2C_SI470X=m ++CONFIG_RADIO_SI4713=m ++CONFIG_I2C_SI4713=m ++CONFIG_USB_MR800=m ++CONFIG_USB_DSBR=m ++CONFIG_RADIO_SHARK=m ++CONFIG_RADIO_SHARK2=m ++CONFIG_USB_KEENE=m ++CONFIG_USB_MA901=m ++CONFIG_RADIO_TEA5764=m ++CONFIG_RADIO_SAA7706H=m ++CONFIG_RADIO_TEF6862=m ++CONFIG_RADIO_WL1273=m ++CONFIG_RADIO_WL128X=m ++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set ++CONFIG_VIDEO_UDA1342=m ++CONFIG_VIDEO_SONY_BTF_MPX=m ++CONFIG_VIDEO_TVP5150=m ++CONFIG_VIDEO_TW2804=m ++CONFIG_VIDEO_TW9903=m ++CONFIG_VIDEO_TW9906=m ++CONFIG_VIDEO_OV7640=m ++CONFIG_VIDEO_MT9V011=m + CONFIG_FB=y +-CONFIG_FB_SIMPLE=y ++CONFIG_FB_BCM2708=y ++CONFIG_FB_SSD1307=m ++# CONFIG_BACKLIGHT_GENERIC is not set ++CONFIG_BACKLIGHT_GPIO=m + CONFIG_FRAMEBUFFER_CONSOLE=y + CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++CONFIG_SOUND=y ++CONFIG_SND=m ++CONFIG_SND_SEQUENCER=m ++CONFIG_SND_SEQ_DUMMY=m ++CONFIG_SND_MIXER_OSS=m ++CONFIG_SND_PCM_OSS=m ++CONFIG_SND_SEQUENCER_OSS=y ++CONFIG_SND_HRTIMER=m ++CONFIG_SND_DUMMY=m ++CONFIG_SND_ALOOP=m ++CONFIG_SND_VIRMIDI=m ++CONFIG_SND_MTPAV=m ++CONFIG_SND_SERIAL_U16550=m ++CONFIG_SND_MPU401=m ++CONFIG_SND_BCM2835=m ++CONFIG_SND_USB_AUDIO=m ++CONFIG_SND_USB_UA101=m ++CONFIG_SND_USB_CAIAQ=m ++CONFIG_SND_USB_CAIAQ_INPUT=y ++CONFIG_SND_USB_6FIRE=m ++CONFIG_SND_SOC=m ++CONFIG_SND_BCM2835_SOC_I2S=m ++CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m ++CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m ++CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m ++CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m ++CONFIG_SND_BCM2708_SOC_RPI_DAC=m ++CONFIG_SND_BCM2708_SOC_RPI_PROTO=m ++CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m ++CONFIG_SND_SIMPLE_CARD=m ++CONFIG_SOUND_PRIME=m ++CONFIG_HIDRAW=y ++CONFIG_HID_A4TECH=m ++CONFIG_HID_ACRUX=m ++CONFIG_HID_APPLE=m ++CONFIG_HID_BELKIN=m ++CONFIG_HID_CHERRY=m ++CONFIG_HID_CHICONY=m ++CONFIG_HID_CYPRESS=m ++CONFIG_HID_DRAGONRISE=m ++CONFIG_HID_EMS_FF=m ++CONFIG_HID_ELECOM=m ++CONFIG_HID_ELO=m ++CONFIG_HID_EZKEY=m ++CONFIG_HID_HOLTEK=m ++CONFIG_HID_KEYTOUCH=m ++CONFIG_HID_KYE=m ++CONFIG_HID_UCLOGIC=m ++CONFIG_HID_WALTOP=m ++CONFIG_HID_GYRATION=m ++CONFIG_HID_TWINHAN=m ++CONFIG_HID_KENSINGTON=m ++CONFIG_HID_LCPOWER=m ++CONFIG_HID_LOGITECH=m ++CONFIG_HID_MAGICMOUSE=m ++CONFIG_HID_MICROSOFT=m ++CONFIG_HID_MONTEREY=m ++CONFIG_HID_MULTITOUCH=m ++CONFIG_HID_NTRIG=m ++CONFIG_HID_ORTEK=m ++CONFIG_HID_PANTHERLORD=m ++CONFIG_HID_PETALYNX=m ++CONFIG_HID_PICOLCD=m ++CONFIG_HID_ROCCAT=m ++CONFIG_HID_SAMSUNG=m ++CONFIG_HID_SONY=m ++CONFIG_HID_SPEEDLINK=m ++CONFIG_HID_SUNPLUS=m ++CONFIG_HID_GREENASIA=m ++CONFIG_HID_SMARTJOYPLUS=m ++CONFIG_HID_TOPSEED=m ++CONFIG_HID_THINGM=m ++CONFIG_HID_THRUSTMASTER=m ++CONFIG_HID_WACOM=m ++CONFIG_HID_WIIMOTE=m ++CONFIG_HID_XINMO=m ++CONFIG_HID_ZEROPLUS=m ++CONFIG_HID_ZYDACRON=m ++CONFIG_HID_PID=y ++CONFIG_USB_HIDDEV=y + CONFIG_USB=y ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++CONFIG_USB_MON=m ++CONFIG_USB_DWCOTG=y ++CONFIG_USB_PRINTER=m + CONFIG_USB_STORAGE=y ++CONFIG_USB_STORAGE_REALTEK=m ++CONFIG_USB_STORAGE_DATAFAB=m ++CONFIG_USB_STORAGE_FREECOM=m ++CONFIG_USB_STORAGE_ISD200=m ++CONFIG_USB_STORAGE_USBAT=m ++CONFIG_USB_STORAGE_SDDR09=m ++CONFIG_USB_STORAGE_SDDR55=m ++CONFIG_USB_STORAGE_JUMPSHOT=m ++CONFIG_USB_STORAGE_ALAUDA=m ++CONFIG_USB_STORAGE_ONETOUCH=m ++CONFIG_USB_STORAGE_KARMA=m ++CONFIG_USB_STORAGE_CYPRESS_ATACB=m ++CONFIG_USB_STORAGE_ENE_UB6250=m ++CONFIG_USB_MDC800=m ++CONFIG_USB_MICROTEK=m ++CONFIG_USBIP_CORE=m ++CONFIG_USBIP_VHCI_HCD=m ++CONFIG_USBIP_HOST=m ++CONFIG_USB_DWC2=y ++CONFIG_USB_SERIAL=m ++CONFIG_USB_SERIAL_GENERIC=y ++CONFIG_USB_SERIAL_AIRCABLE=m ++CONFIG_USB_SERIAL_ARK3116=m ++CONFIG_USB_SERIAL_BELKIN=m ++CONFIG_USB_SERIAL_CH341=m ++CONFIG_USB_SERIAL_WHITEHEAT=m ++CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m ++CONFIG_USB_SERIAL_CP210X=m ++CONFIG_USB_SERIAL_CYPRESS_M8=m ++CONFIG_USB_SERIAL_EMPEG=m ++CONFIG_USB_SERIAL_FTDI_SIO=m ++CONFIG_USB_SERIAL_VISOR=m ++CONFIG_USB_SERIAL_IPAQ=m ++CONFIG_USB_SERIAL_IR=m ++CONFIG_USB_SERIAL_EDGEPORT=m ++CONFIG_USB_SERIAL_EDGEPORT_TI=m ++CONFIG_USB_SERIAL_F81232=m ++CONFIG_USB_SERIAL_GARMIN=m ++CONFIG_USB_SERIAL_IPW=m ++CONFIG_USB_SERIAL_IUU=m ++CONFIG_USB_SERIAL_KEYSPAN_PDA=m ++CONFIG_USB_SERIAL_KEYSPAN=m ++CONFIG_USB_SERIAL_KLSI=m ++CONFIG_USB_SERIAL_KOBIL_SCT=m ++CONFIG_USB_SERIAL_MCT_U232=m ++CONFIG_USB_SERIAL_METRO=m ++CONFIG_USB_SERIAL_MOS7720=m ++CONFIG_USB_SERIAL_MOS7840=m ++CONFIG_USB_SERIAL_NAVMAN=m ++CONFIG_USB_SERIAL_PL2303=m ++CONFIG_USB_SERIAL_OTI6858=m ++CONFIG_USB_SERIAL_QCAUX=m ++CONFIG_USB_SERIAL_QUALCOMM=m ++CONFIG_USB_SERIAL_SPCP8X5=m ++CONFIG_USB_SERIAL_SAFE=m ++CONFIG_USB_SERIAL_SIERRAWIRELESS=m ++CONFIG_USB_SERIAL_SYMBOL=m ++CONFIG_USB_SERIAL_TI=m ++CONFIG_USB_SERIAL_CYBERJACK=m ++CONFIG_USB_SERIAL_XIRCOM=m ++CONFIG_USB_SERIAL_OPTION=m ++CONFIG_USB_SERIAL_OMNINET=m ++CONFIG_USB_SERIAL_OPTICON=m ++CONFIG_USB_SERIAL_XSENS_MT=m ++CONFIG_USB_SERIAL_WISHBONE=m ++CONFIG_USB_SERIAL_SSU100=m ++CONFIG_USB_SERIAL_QT2=m ++CONFIG_USB_SERIAL_DEBUG=m ++CONFIG_USB_EMI62=m ++CONFIG_USB_EMI26=m ++CONFIG_USB_ADUTUX=m ++CONFIG_USB_SEVSEG=m ++CONFIG_USB_RIO500=m ++CONFIG_USB_LEGOTOWER=m ++CONFIG_USB_LCD=m ++CONFIG_USB_LED=m ++CONFIG_USB_CYPRESS_CY7C63=m ++CONFIG_USB_CYTHERM=m ++CONFIG_USB_IDMOUSE=m ++CONFIG_USB_FTDI_ELAN=m ++CONFIG_USB_APPLEDISPLAY=m ++CONFIG_USB_LD=m ++CONFIG_USB_TRANCEVIBRATOR=m ++CONFIG_USB_IOWARRIOR=m ++CONFIG_USB_TEST=m ++CONFIG_USB_ISIGHTFW=m ++CONFIG_USB_YUREX=m ++CONFIG_USB_ATM=m ++CONFIG_USB_SPEEDTOUCH=m ++CONFIG_USB_CXACRU=m ++CONFIG_USB_UEAGLEATM=m ++CONFIG_USB_XUSBATM=m + CONFIG_MMC=y ++CONFIG_MMC_BLOCK_MINORS=32 ++CONFIG_MMC_BCM2835=y ++CONFIG_MMC_BCM2835_DMA=y ++CONFIG_MMC_BCM2835_SDHOST=y + CONFIG_MMC_SDHCI=y + CONFIG_MMC_SDHCI_PLTFM=y + CONFIG_MMC_SDHCI_BCM2835=y ++CONFIG_MMC_SPI=m ++CONFIG_LEDS_CLASS=y + CONFIG_LEDS_GPIO=y + CONFIG_LEDS_TRIGGER_TIMER=y + CONFIG_LEDS_TRIGGER_ONESHOT=y + CONFIG_LEDS_TRIGGER_HEARTBEAT=y ++CONFIG_LEDS_TRIGGER_BACKLIGHT=y + CONFIG_LEDS_TRIGGER_CPU=y + CONFIG_LEDS_TRIGGER_GPIO=y + CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +-CONFIG_LEDS_TRIGGER_TRANSIENT=y +-CONFIG_LEDS_TRIGGER_CAMERA=y ++CONFIG_LEDS_TRIGGER_TRANSIENT=m ++CONFIG_LEDS_TRIGGER_CAMERA=m ++CONFIG_LEDS_TRIGGER_INPUT=y ++CONFIG_RTC_CLASS=y ++# CONFIG_RTC_HCTOSYS is not set ++CONFIG_RTC_DRV_DS1307=m ++CONFIG_RTC_DRV_DS1374=m ++CONFIG_RTC_DRV_DS1672=m ++CONFIG_RTC_DRV_DS3232=m ++CONFIG_RTC_DRV_MAX6900=m ++CONFIG_RTC_DRV_RS5C372=m ++CONFIG_RTC_DRV_ISL1208=m ++CONFIG_RTC_DRV_ISL12022=m ++CONFIG_RTC_DRV_ISL12057=m ++CONFIG_RTC_DRV_X1205=m ++CONFIG_RTC_DRV_PCF2127=m ++CONFIG_RTC_DRV_PCF8523=m ++CONFIG_RTC_DRV_PCF8563=m ++CONFIG_RTC_DRV_PCF8583=m ++CONFIG_RTC_DRV_M41T80=m ++CONFIG_RTC_DRV_BQ32K=m ++CONFIG_RTC_DRV_S35390A=m ++CONFIG_RTC_DRV_FM3130=m ++CONFIG_RTC_DRV_RX8581=m ++CONFIG_RTC_DRV_RX8025=m ++CONFIG_RTC_DRV_EM3027=m ++CONFIG_RTC_DRV_RV3029C2=m ++CONFIG_RTC_DRV_M41T93=m ++CONFIG_RTC_DRV_M41T94=m ++CONFIG_RTC_DRV_DS1305=m ++CONFIG_RTC_DRV_DS1390=m ++CONFIG_RTC_DRV_MAX6902=m ++CONFIG_RTC_DRV_R9701=m ++CONFIG_RTC_DRV_RS5C348=m ++CONFIG_RTC_DRV_DS3234=m ++CONFIG_RTC_DRV_PCF2123=m ++CONFIG_RTC_DRV_RX4581=m ++CONFIG_DMADEVICES=y ++CONFIG_DMA_BCM2708=y ++CONFIG_UIO=m ++CONFIG_UIO_PDRV_GENIRQ=m + CONFIG_STAGING=y +-CONFIG_USB_DWC2=y +-CONFIG_USB_DWC2_HOST=y ++CONFIG_PRISM2_USB=m ++CONFIG_R8712U=m ++CONFIG_R8188EU=m ++CONFIG_R8723AU=m ++CONFIG_VT6656=m ++CONFIG_SPEAKUP=m ++CONFIG_SPEAKUP_SYNTH_SOFT=m ++CONFIG_STAGING_MEDIA=y ++CONFIG_LIRC_STAGING=y ++CONFIG_LIRC_IMON=m ++CONFIG_LIRC_SASEM=m ++CONFIG_LIRC_SERIAL=m ++CONFIG_FB_TFT=m ++CONFIG_FB_TFT_AGM1264K_FL=m ++CONFIG_FB_TFT_BD663474=m ++CONFIG_FB_TFT_HX8340BN=m ++CONFIG_FB_TFT_HX8347D=m ++CONFIG_FB_TFT_HX8353D=m ++CONFIG_FB_TFT_ILI9320=m ++CONFIG_FB_TFT_ILI9325=m ++CONFIG_FB_TFT_ILI9340=m ++CONFIG_FB_TFT_ILI9341=m ++CONFIG_FB_TFT_ILI9481=m ++CONFIG_FB_TFT_ILI9486=m ++CONFIG_FB_TFT_PCD8544=m ++CONFIG_FB_TFT_RA8875=m ++CONFIG_FB_TFT_S6D02A1=m ++CONFIG_FB_TFT_S6D1121=m ++CONFIG_FB_TFT_SSD1289=m ++CONFIG_FB_TFT_SSD1306=m ++CONFIG_FB_TFT_SSD1331=m ++CONFIG_FB_TFT_SSD1351=m ++CONFIG_FB_TFT_ST7735R=m ++CONFIG_FB_TFT_TINYLCD=m ++CONFIG_FB_TFT_TLS8204=m ++CONFIG_FB_TFT_UC1701=m ++CONFIG_FB_TFT_UPD161704=m ++CONFIG_FB_TFT_WATTEROTT=m ++CONFIG_FB_FLEX=m ++CONFIG_FB_TFT_FBTFT_DEVICE=m ++CONFIG_MAILBOX=y ++CONFIG_BCM2835_MBOX=y + # CONFIG_IOMMU_SUPPORT is not set ++CONFIG_EXTCON=m ++CONFIG_EXTCON_ARIZONA=m ++CONFIG_RASPBERRYPI_FIRMWARE=y + CONFIG_EXT2_FS=y + CONFIG_EXT2_FS_XATTR=y + CONFIG_EXT2_FS_POSIX_ACL=y +@@ -107,18 +1077,110 @@ + CONFIG_EXT3_FS_POSIX_ACL=y + CONFIG_EXT4_FS=y + CONFIG_EXT4_FS_POSIX_ACL=y ++CONFIG_EXT4_FS_SECURITY=y ++CONFIG_REISERFS_FS=m ++CONFIG_REISERFS_FS_XATTR=y ++CONFIG_REISERFS_FS_POSIX_ACL=y ++CONFIG_REISERFS_FS_SECURITY=y ++CONFIG_JFS_FS=m ++CONFIG_JFS_POSIX_ACL=y ++CONFIG_JFS_SECURITY=y ++CONFIG_JFS_STATISTICS=y ++CONFIG_XFS_FS=m ++CONFIG_XFS_QUOTA=y ++CONFIG_XFS_POSIX_ACL=y ++CONFIG_XFS_RT=y ++CONFIG_GFS2_FS=m ++CONFIG_OCFS2_FS=m ++CONFIG_BTRFS_FS=m ++CONFIG_BTRFS_FS_POSIX_ACL=y ++CONFIG_NILFS2_FS=m ++CONFIG_F2FS_FS=y + CONFIG_FANOTIFY=y ++CONFIG_QFMT_V1=m ++CONFIG_QFMT_V2=m ++CONFIG_AUTOFS4_FS=y ++CONFIG_FUSE_FS=m ++CONFIG_CUSE=m ++CONFIG_FSCACHE=y ++CONFIG_FSCACHE_STATS=y ++CONFIG_FSCACHE_HISTOGRAM=y ++CONFIG_CACHEFILES=y ++CONFIG_ISO9660_FS=m ++CONFIG_JOLIET=y ++CONFIG_ZISOFS=y ++CONFIG_UDF_FS=m + CONFIG_MSDOS_FS=y + CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_IOCHARSET="ascii" ++CONFIG_NTFS_FS=m ++CONFIG_NTFS_RW=y + CONFIG_TMPFS=y + CONFIG_TMPFS_POSIX_ACL=y +-# CONFIG_MISC_FILESYSTEMS is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_ECRYPT_FS=m ++CONFIG_HFS_FS=m ++CONFIG_HFSPLUS_FS=m ++CONFIG_SQUASHFS=m ++CONFIG_SQUASHFS_XATTR=y ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y + CONFIG_NFS_FS=y +-CONFIG_NFSD=y ++CONFIG_NFS_V3_ACL=y ++CONFIG_NFS_V4=y ++CONFIG_NFS_SWAP=y ++CONFIG_ROOT_NFS=y ++CONFIG_NFS_FSCACHE=y ++CONFIG_NFSD=m ++CONFIG_NFSD_V3_ACL=y ++CONFIG_NFSD_V4=y ++CONFIG_CIFS=m ++CONFIG_CIFS_WEAK_PW_HASH=y ++CONFIG_CIFS_UPCALL=y ++CONFIG_CIFS_XATTR=y ++CONFIG_CIFS_POSIX=y ++CONFIG_9P_FS=m ++CONFIG_9P_FS_POSIX_ACL=y ++CONFIG_NLS_DEFAULT="utf8" + CONFIG_NLS_CODEPAGE_437=y ++CONFIG_NLS_CODEPAGE_737=m ++CONFIG_NLS_CODEPAGE_775=m ++CONFIG_NLS_CODEPAGE_850=m ++CONFIG_NLS_CODEPAGE_852=m ++CONFIG_NLS_CODEPAGE_855=m ++CONFIG_NLS_CODEPAGE_857=m ++CONFIG_NLS_CODEPAGE_860=m ++CONFIG_NLS_CODEPAGE_861=m ++CONFIG_NLS_CODEPAGE_862=m ++CONFIG_NLS_CODEPAGE_863=m ++CONFIG_NLS_CODEPAGE_864=m ++CONFIG_NLS_CODEPAGE_865=m ++CONFIG_NLS_CODEPAGE_866=m ++CONFIG_NLS_CODEPAGE_869=m ++CONFIG_NLS_CODEPAGE_936=m ++CONFIG_NLS_CODEPAGE_950=m ++CONFIG_NLS_CODEPAGE_932=m ++CONFIG_NLS_CODEPAGE_949=m ++CONFIG_NLS_CODEPAGE_874=m ++CONFIG_NLS_ISO8859_8=m ++CONFIG_NLS_CODEPAGE_1250=m ++CONFIG_NLS_CODEPAGE_1251=m + CONFIG_NLS_ASCII=y +-CONFIG_NLS_ISO8859_1=y ++CONFIG_NLS_ISO8859_1=m ++CONFIG_NLS_ISO8859_2=m ++CONFIG_NLS_ISO8859_3=m ++CONFIG_NLS_ISO8859_4=m ++CONFIG_NLS_ISO8859_5=m ++CONFIG_NLS_ISO8859_6=m ++CONFIG_NLS_ISO8859_7=m ++CONFIG_NLS_ISO8859_9=m ++CONFIG_NLS_ISO8859_13=m ++CONFIG_NLS_ISO8859_14=m ++CONFIG_NLS_ISO8859_15=m ++CONFIG_NLS_KOI8_R=m ++CONFIG_NLS_KOI8_U=m + CONFIG_NLS_UTF8=y ++CONFIG_DLM=m + CONFIG_PRINTK_TIME=y + CONFIG_BOOT_PRINTK_DELAY=y + CONFIG_DYNAMIC_DEBUG=y +@@ -128,14 +1190,39 @@ + CONFIG_UNUSED_SYMBOLS=y + CONFIG_DEBUG_MEMORY_INIT=y + CONFIG_LOCKUP_DETECTOR=y ++CONFIG_TIMER_STATS=y ++# CONFIG_DEBUG_PREEMPT is not set ++CONFIG_LATENCYTOP=y ++CONFIG_IRQSOFF_TRACER=y + CONFIG_SCHED_TRACER=y + CONFIG_STACK_TRACER=y ++CONFIG_BLK_DEV_IO_TRACE=y ++# CONFIG_KPROBE_EVENT is not set + CONFIG_FUNCTION_PROFILER=y + CONFIG_TEST_KSTRTOX=y + CONFIG_KGDB=y + CONFIG_KGDB_KDB=y ++CONFIG_KDB_KEYBOARD=y + CONFIG_STRICT_DEVMEM=y + CONFIG_DEBUG_LL=y + CONFIG_EARLY_PRINTK=y ++CONFIG_CRYPTO_USER=m ++CONFIG_CRYPTO_CRYPTD=m ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTS=m ++CONFIG_CRYPTO_XTS=m ++CONFIG_CRYPTO_XCBC=m ++CONFIG_CRYPTO_SHA512=m ++CONFIG_CRYPTO_TGR192=m ++CONFIG_CRYPTO_WP512=m ++CONFIG_CRYPTO_CAST5=m ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++# CONFIG_CRYPTO_HW is not set ++CONFIG_ARM_CRYPTO=y ++CONFIG_CRYPTO_SHA1_ARM=m ++CONFIG_CRYPTO_AES_ARM=m ++CONFIG_CRC_ITU_T=y ++CONFIG_LIBCRC32C=y + # CONFIG_XZ_DEC_ARM is not set + # CONFIG_XZ_DEC_ARMTHUMB is not set +diff -Nur linux-4.1.13.orig/arch/arm/configs/bcmrpi_defconfig linux-rpi/arch/arm/configs/bcmrpi_defconfig +--- linux-4.1.13.orig/arch/arm/configs/bcmrpi_defconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/configs/bcmrpi_defconfig 2015-11-29 09:42:34.707444982 +0100 +@@ -0,0 +1,1255 @@ ++# CONFIG_ARM_PATCH_PHYS_VIRT is not set ++CONFIG_PHYS_OFFSET=0 ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_SYSVIPC=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_FHANDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++CONFIG_BSD_PROCESS_ACCT=y ++CONFIG_BSD_PROCESS_ACCT_V3=y ++CONFIG_TASKSTATS=y ++CONFIG_TASK_DELAY_ACCT=y ++CONFIG_TASK_XACCT=y ++CONFIG_TASK_IO_ACCOUNTING=y ++CONFIG_IKCONFIG=m ++CONFIG_IKCONFIG_PROC=y ++CONFIG_CGROUP_FREEZER=y ++CONFIG_CGROUP_DEVICE=y ++CONFIG_CPUSETS=y ++CONFIG_CGROUP_CPUACCT=y ++CONFIG_MEMCG=y ++CONFIG_BLK_CGROUP=y ++CONFIG_NAMESPACES=y ++CONFIG_SCHED_AUTOGROUP=y ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_EMBEDDED=y ++# CONFIG_COMPAT_BRK is not set ++CONFIG_PROFILING=y ++CONFIG_OPROFILE=m ++CONFIG_KPROBES=y ++CONFIG_JUMP_LABEL=y ++CONFIG_MODULES=y ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODVERSIONS=y ++CONFIG_MODULE_SRCVERSION_ALL=y ++CONFIG_BLK_DEV_THROTTLING=y ++CONFIG_PARTITION_ADVANCED=y ++CONFIG_MAC_PARTITION=y ++CONFIG_CFQ_GROUP_IOSCHED=y ++CONFIG_ARCH_BCM2708=y ++CONFIG_BCM2708_DT=y ++CONFIG_PREEMPT=y ++CONFIG_AEABI=y ++CONFIG_OABI_COMPAT=y ++CONFIG_CLEANCACHE=y ++CONFIG_FRONTSWAP=y ++CONFIG_CMA=y ++CONFIG_ZSMALLOC=m ++CONFIG_PGTABLE_MAPPING=y ++CONFIG_UACCESS_WITH_MEMCPY=y ++CONFIG_SECCOMP=y ++CONFIG_ZBOOT_ROM_TEXT=0x0 ++CONFIG_ZBOOT_ROM_BSS=0x0 ++CONFIG_CMDLINE="console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait" ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_STAT=m ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y ++CONFIG_VFP=y ++CONFIG_BINFMT_MISC=m ++# CONFIG_SUSPEND is not set ++CONFIG_NET=y ++CONFIG_PACKET=y ++CONFIG_UNIX=y ++CONFIG_XFRM_USER=y ++CONFIG_NET_KEY=m ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++CONFIG_IP_MULTIPLE_TABLES=y ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++CONFIG_IP_PNP=y ++CONFIG_IP_PNP_DHCP=y ++CONFIG_IP_PNP_RARP=y ++CONFIG_NET_IPIP=m ++CONFIG_NET_IPGRE_DEMUX=m ++CONFIG_NET_IPGRE=m ++CONFIG_IP_MROUTE=y ++CONFIG_IP_MROUTE_MULTIPLE_TABLES=y ++CONFIG_IP_PIMSM_V1=y ++CONFIG_IP_PIMSM_V2=y ++CONFIG_SYN_COOKIES=y ++CONFIG_INET_AH=m ++CONFIG_INET_ESP=m ++CONFIG_INET_IPCOMP=m ++CONFIG_INET_XFRM_MODE_TRANSPORT=m ++CONFIG_INET_XFRM_MODE_TUNNEL=m ++CONFIG_INET_XFRM_MODE_BEET=m ++CONFIG_INET_LRO=m ++CONFIG_INET_DIAG=m ++CONFIG_INET6_AH=m ++CONFIG_INET6_ESP=m ++CONFIG_INET6_IPCOMP=m ++CONFIG_IPV6_TUNNEL=m ++CONFIG_IPV6_MULTIPLE_TABLES=y ++CONFIG_IPV6_MROUTE=y ++CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y ++CONFIG_IPV6_PIMSM_V2=y ++CONFIG_NETFILTER=y ++CONFIG_NF_CONNTRACK=m ++CONFIG_NF_CONNTRACK_ZONES=y ++CONFIG_NF_CONNTRACK_EVENTS=y ++CONFIG_NF_CONNTRACK_TIMESTAMP=y ++CONFIG_NF_CT_PROTO_DCCP=m ++CONFIG_NF_CT_PROTO_UDPLITE=m ++CONFIG_NF_CONNTRACK_AMANDA=m ++CONFIG_NF_CONNTRACK_FTP=m ++CONFIG_NF_CONNTRACK_H323=m ++CONFIG_NF_CONNTRACK_IRC=m ++CONFIG_NF_CONNTRACK_NETBIOS_NS=m ++CONFIG_NF_CONNTRACK_SNMP=m ++CONFIG_NF_CONNTRACK_PPTP=m ++CONFIG_NF_CONNTRACK_SANE=m ++CONFIG_NF_CONNTRACK_SIP=m ++CONFIG_NF_CONNTRACK_TFTP=m ++CONFIG_NF_CT_NETLINK=m ++CONFIG_NETFILTER_XT_SET=m ++CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m ++CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m ++CONFIG_NETFILTER_XT_TARGET_CONNMARK=m ++CONFIG_NETFILTER_XT_TARGET_DSCP=m ++CONFIG_NETFILTER_XT_TARGET_HMARK=m ++CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m ++CONFIG_NETFILTER_XT_TARGET_LED=m ++CONFIG_NETFILTER_XT_TARGET_LOG=m ++CONFIG_NETFILTER_XT_TARGET_MARK=m ++CONFIG_NETFILTER_XT_TARGET_NFLOG=m ++CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m ++CONFIG_NETFILTER_XT_TARGET_NOTRACK=m ++CONFIG_NETFILTER_XT_TARGET_TEE=m ++CONFIG_NETFILTER_XT_TARGET_TPROXY=m ++CONFIG_NETFILTER_XT_TARGET_TRACE=m ++CONFIG_NETFILTER_XT_TARGET_TCPMSS=m ++CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m ++CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m ++CONFIG_NETFILTER_XT_MATCH_BPF=m ++CONFIG_NETFILTER_XT_MATCH_CLUSTER=m ++CONFIG_NETFILTER_XT_MATCH_COMMENT=m ++CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m ++CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m ++CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m ++CONFIG_NETFILTER_XT_MATCH_CONNMARK=m ++CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m ++CONFIG_NETFILTER_XT_MATCH_CPU=m ++CONFIG_NETFILTER_XT_MATCH_DCCP=m ++CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m ++CONFIG_NETFILTER_XT_MATCH_DSCP=m ++CONFIG_NETFILTER_XT_MATCH_ESP=m ++CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m ++CONFIG_NETFILTER_XT_MATCH_HELPER=m ++CONFIG_NETFILTER_XT_MATCH_IPRANGE=m ++CONFIG_NETFILTER_XT_MATCH_IPVS=m ++CONFIG_NETFILTER_XT_MATCH_LENGTH=m ++CONFIG_NETFILTER_XT_MATCH_LIMIT=m ++CONFIG_NETFILTER_XT_MATCH_MAC=m ++CONFIG_NETFILTER_XT_MATCH_MARK=m ++CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m ++CONFIG_NETFILTER_XT_MATCH_NFACCT=m ++CONFIG_NETFILTER_XT_MATCH_OSF=m ++CONFIG_NETFILTER_XT_MATCH_OWNER=m ++CONFIG_NETFILTER_XT_MATCH_POLICY=m ++CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m ++CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m ++CONFIG_NETFILTER_XT_MATCH_QUOTA=m ++CONFIG_NETFILTER_XT_MATCH_RATEEST=m ++CONFIG_NETFILTER_XT_MATCH_REALM=m ++CONFIG_NETFILTER_XT_MATCH_RECENT=m ++CONFIG_NETFILTER_XT_MATCH_SOCKET=m ++CONFIG_NETFILTER_XT_MATCH_STATE=m ++CONFIG_NETFILTER_XT_MATCH_STATISTIC=m ++CONFIG_NETFILTER_XT_MATCH_STRING=m ++CONFIG_NETFILTER_XT_MATCH_TCPMSS=m ++CONFIG_NETFILTER_XT_MATCH_TIME=m ++CONFIG_NETFILTER_XT_MATCH_U32=m ++CONFIG_IP_SET=m ++CONFIG_IP_SET_BITMAP_IP=m ++CONFIG_IP_SET_BITMAP_IPMAC=m ++CONFIG_IP_SET_BITMAP_PORT=m ++CONFIG_IP_SET_HASH_IP=m ++CONFIG_IP_SET_HASH_IPPORT=m ++CONFIG_IP_SET_HASH_IPPORTIP=m ++CONFIG_IP_SET_HASH_IPPORTNET=m ++CONFIG_IP_SET_HASH_NET=m ++CONFIG_IP_SET_HASH_NETPORT=m ++CONFIG_IP_SET_HASH_NETIFACE=m ++CONFIG_IP_SET_LIST_SET=m ++CONFIG_IP_VS=m ++CONFIG_IP_VS_PROTO_TCP=y ++CONFIG_IP_VS_PROTO_UDP=y ++CONFIG_IP_VS_PROTO_ESP=y ++CONFIG_IP_VS_PROTO_AH=y ++CONFIG_IP_VS_PROTO_SCTP=y ++CONFIG_IP_VS_RR=m ++CONFIG_IP_VS_WRR=m ++CONFIG_IP_VS_LC=m ++CONFIG_IP_VS_WLC=m ++CONFIG_IP_VS_LBLC=m ++CONFIG_IP_VS_LBLCR=m ++CONFIG_IP_VS_DH=m ++CONFIG_IP_VS_SH=m ++CONFIG_IP_VS_SED=m ++CONFIG_IP_VS_NQ=m ++CONFIG_IP_VS_FTP=m ++CONFIG_IP_VS_PE_SIP=m ++CONFIG_NF_CONNTRACK_IPV4=m ++CONFIG_IP_NF_IPTABLES=m ++CONFIG_IP_NF_MATCH_AH=m ++CONFIG_IP_NF_MATCH_ECN=m ++CONFIG_IP_NF_MATCH_TTL=m ++CONFIG_IP_NF_FILTER=m ++CONFIG_IP_NF_TARGET_REJECT=m ++CONFIG_IP_NF_NAT=m ++CONFIG_IP_NF_TARGET_MASQUERADE=m ++CONFIG_IP_NF_TARGET_NETMAP=m ++CONFIG_IP_NF_TARGET_REDIRECT=m ++CONFIG_IP_NF_MANGLE=m ++CONFIG_IP_NF_TARGET_CLUSTERIP=m ++CONFIG_IP_NF_TARGET_ECN=m ++CONFIG_IP_NF_TARGET_TTL=m ++CONFIG_IP_NF_RAW=m ++CONFIG_IP_NF_ARPTABLES=m ++CONFIG_IP_NF_ARPFILTER=m ++CONFIG_IP_NF_ARP_MANGLE=m ++CONFIG_NF_CONNTRACK_IPV6=m ++CONFIG_IP6_NF_IPTABLES=m ++CONFIG_IP6_NF_MATCH_AH=m ++CONFIG_IP6_NF_MATCH_EUI64=m ++CONFIG_IP6_NF_MATCH_FRAG=m ++CONFIG_IP6_NF_MATCH_OPTS=m ++CONFIG_IP6_NF_MATCH_HL=m ++CONFIG_IP6_NF_MATCH_IPV6HEADER=m ++CONFIG_IP6_NF_MATCH_MH=m ++CONFIG_IP6_NF_MATCH_RT=m ++CONFIG_IP6_NF_TARGET_HL=m ++CONFIG_IP6_NF_FILTER=m ++CONFIG_IP6_NF_TARGET_REJECT=m ++CONFIG_IP6_NF_MANGLE=m ++CONFIG_IP6_NF_RAW=m ++CONFIG_IP6_NF_NAT=m ++CONFIG_IP6_NF_TARGET_MASQUERADE=m ++CONFIG_IP6_NF_TARGET_NPT=m ++CONFIG_BRIDGE_NF_EBTABLES=m ++CONFIG_BRIDGE_EBT_BROUTE=m ++CONFIG_BRIDGE_EBT_T_FILTER=m ++CONFIG_BRIDGE_EBT_T_NAT=m ++CONFIG_BRIDGE_EBT_802_3=m ++CONFIG_BRIDGE_EBT_AMONG=m ++CONFIG_BRIDGE_EBT_ARP=m ++CONFIG_BRIDGE_EBT_IP=m ++CONFIG_BRIDGE_EBT_IP6=m ++CONFIG_BRIDGE_EBT_LIMIT=m ++CONFIG_BRIDGE_EBT_MARK=m ++CONFIG_BRIDGE_EBT_PKTTYPE=m ++CONFIG_BRIDGE_EBT_STP=m ++CONFIG_BRIDGE_EBT_VLAN=m ++CONFIG_BRIDGE_EBT_ARPREPLY=m ++CONFIG_BRIDGE_EBT_DNAT=m ++CONFIG_BRIDGE_EBT_MARK_T=m ++CONFIG_BRIDGE_EBT_REDIRECT=m ++CONFIG_BRIDGE_EBT_SNAT=m ++CONFIG_BRIDGE_EBT_LOG=m ++CONFIG_BRIDGE_EBT_NFLOG=m ++CONFIG_SCTP_COOKIE_HMAC_SHA1=y ++CONFIG_ATM=m ++CONFIG_L2TP=m ++CONFIG_L2TP_V3=y ++CONFIG_L2TP_IP=m ++CONFIG_L2TP_ETH=m ++CONFIG_BRIDGE=m ++CONFIG_VLAN_8021Q=m ++CONFIG_VLAN_8021Q_GVRP=y ++CONFIG_ATALK=m ++CONFIG_6LOWPAN=m ++CONFIG_IEEE802154=m ++CONFIG_IEEE802154_6LOWPAN=m ++CONFIG_MAC802154=m ++CONFIG_NET_SCHED=y ++CONFIG_NET_SCH_CBQ=m ++CONFIG_NET_SCH_HTB=m ++CONFIG_NET_SCH_HFSC=m ++CONFIG_NET_SCH_PRIO=m ++CONFIG_NET_SCH_MULTIQ=m ++CONFIG_NET_SCH_RED=m ++CONFIG_NET_SCH_SFB=m ++CONFIG_NET_SCH_SFQ=m ++CONFIG_NET_SCH_TEQL=m ++CONFIG_NET_SCH_TBF=m ++CONFIG_NET_SCH_GRED=m ++CONFIG_NET_SCH_DSMARK=m ++CONFIG_NET_SCH_NETEM=m ++CONFIG_NET_SCH_DRR=m ++CONFIG_NET_SCH_MQPRIO=m ++CONFIG_NET_SCH_CHOKE=m ++CONFIG_NET_SCH_QFQ=m ++CONFIG_NET_SCH_CODEL=m ++CONFIG_NET_SCH_FQ_CODEL=m ++CONFIG_NET_SCH_INGRESS=m ++CONFIG_NET_SCH_PLUG=m ++CONFIG_NET_CLS_BASIC=m ++CONFIG_NET_CLS_TCINDEX=m ++CONFIG_NET_CLS_ROUTE4=m ++CONFIG_NET_CLS_FW=m ++CONFIG_NET_CLS_U32=m ++CONFIG_CLS_U32_MARK=y ++CONFIG_NET_CLS_RSVP=m ++CONFIG_NET_CLS_RSVP6=m ++CONFIG_NET_CLS_FLOW=m ++CONFIG_NET_CLS_CGROUP=m ++CONFIG_NET_EMATCH=y ++CONFIG_NET_EMATCH_CMP=m ++CONFIG_NET_EMATCH_NBYTE=m ++CONFIG_NET_EMATCH_U32=m ++CONFIG_NET_EMATCH_META=m ++CONFIG_NET_EMATCH_TEXT=m ++CONFIG_NET_EMATCH_IPSET=m ++CONFIG_NET_CLS_ACT=y ++CONFIG_NET_ACT_POLICE=m ++CONFIG_NET_ACT_GACT=m ++CONFIG_GACT_PROB=y ++CONFIG_NET_ACT_MIRRED=m ++CONFIG_NET_ACT_IPT=m ++CONFIG_NET_ACT_NAT=m ++CONFIG_NET_ACT_PEDIT=m ++CONFIG_NET_ACT_SIMP=m ++CONFIG_NET_ACT_SKBEDIT=m ++CONFIG_NET_ACT_CSUM=m ++CONFIG_BATMAN_ADV=m ++CONFIG_OPENVSWITCH=m ++CONFIG_NET_PKTGEN=m ++CONFIG_HAMRADIO=y ++CONFIG_AX25=m ++CONFIG_NETROM=m ++CONFIG_ROSE=m ++CONFIG_MKISS=m ++CONFIG_6PACK=m ++CONFIG_BPQETHER=m ++CONFIG_BAYCOM_SER_FDX=m ++CONFIG_BAYCOM_SER_HDX=m ++CONFIG_YAM=m ++CONFIG_CAN=m ++CONFIG_CAN_VCAN=m ++CONFIG_CAN_MCP251X=m ++CONFIG_IRDA=m ++CONFIG_IRLAN=m ++CONFIG_IRNET=m ++CONFIG_IRCOMM=m ++CONFIG_IRDA_ULTRA=y ++CONFIG_IRDA_CACHE_LAST_LSAP=y ++CONFIG_IRDA_FAST_RR=y ++CONFIG_IRTTY_SIR=m ++CONFIG_KINGSUN_DONGLE=m ++CONFIG_KSDAZZLE_DONGLE=m ++CONFIG_KS959_DONGLE=m ++CONFIG_USB_IRDA=m ++CONFIG_SIGMATEL_FIR=m ++CONFIG_MCS_FIR=m ++CONFIG_BT=m ++CONFIG_BT_RFCOMM=m ++CONFIG_BT_RFCOMM_TTY=y ++CONFIG_BT_BNEP=m ++CONFIG_BT_BNEP_MC_FILTER=y ++CONFIG_BT_BNEP_PROTO_FILTER=y ++CONFIG_BT_HIDP=m ++CONFIG_BT_6LOWPAN=m ++CONFIG_BT_HCIBTUSB=m ++CONFIG_BT_HCIBCM203X=m ++CONFIG_BT_HCIBPA10X=m ++CONFIG_BT_HCIBFUSB=m ++CONFIG_BT_HCIVHCI=m ++CONFIG_BT_MRVL=m ++CONFIG_BT_MRVL_SDIO=m ++CONFIG_BT_ATH3K=m ++CONFIG_BT_WILINK=m ++CONFIG_MAC80211=m ++CONFIG_MAC80211_MESH=y ++CONFIG_WIMAX=m ++CONFIG_RFKILL=m ++CONFIG_RFKILL_INPUT=y ++CONFIG_NET_9P=m ++CONFIG_NFC=m ++CONFIG_NFC_PN533=m ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++CONFIG_DMA_CMA=y ++CONFIG_CMA_SIZE_MBYTES=5 ++CONFIG_MTD=m ++CONFIG_MTD_BLOCK=m ++CONFIG_MTD_NAND=m ++CONFIG_MTD_UBI=m ++CONFIG_ZRAM=m ++CONFIG_ZRAM_LZ4_COMPRESS=y ++CONFIG_BLK_DEV_LOOP=y ++CONFIG_BLK_DEV_CRYPTOLOOP=m ++CONFIG_BLK_DEV_DRBD=m ++CONFIG_BLK_DEV_NBD=m ++CONFIG_BLK_DEV_RAM=y ++CONFIG_CDROM_PKTCDVD=m ++CONFIG_ATA_OVER_ETH=m ++CONFIG_EEPROM_AT24=m ++CONFIG_TI_ST=m ++CONFIG_SCSI=y ++# CONFIG_SCSI_PROC_FS is not set ++CONFIG_BLK_DEV_SD=y ++CONFIG_CHR_DEV_ST=m ++CONFIG_CHR_DEV_OSST=m ++CONFIG_BLK_DEV_SR=m ++CONFIG_CHR_DEV_SG=m ++CONFIG_SCSI_ISCSI_ATTRS=y ++CONFIG_ISCSI_TCP=m ++CONFIG_ISCSI_BOOT_SYSFS=m ++CONFIG_MD=y ++CONFIG_MD_LINEAR=m ++CONFIG_MD_RAID0=m ++CONFIG_BLK_DEV_DM=m ++CONFIG_DM_CRYPT=m ++CONFIG_DM_SNAPSHOT=m ++CONFIG_DM_THIN_PROVISIONING=m ++CONFIG_DM_MIRROR=m ++CONFIG_DM_LOG_USERSPACE=m ++CONFIG_DM_RAID=m ++CONFIG_DM_ZERO=m ++CONFIG_DM_DELAY=m ++CONFIG_NETDEVICES=y ++CONFIG_BONDING=m ++CONFIG_DUMMY=m ++CONFIG_IFB=m ++CONFIG_MACVLAN=m ++CONFIG_NETCONSOLE=m ++CONFIG_TUN=m ++CONFIG_VETH=m ++CONFIG_ENC28J60=m ++CONFIG_MDIO_BITBANG=m ++CONFIG_PPP=m ++CONFIG_PPP_BSDCOMP=m ++CONFIG_PPP_DEFLATE=m ++CONFIG_PPP_FILTER=y ++CONFIG_PPP_MPPE=m ++CONFIG_PPP_MULTILINK=y ++CONFIG_PPPOATM=m ++CONFIG_PPPOE=m ++CONFIG_PPPOL2TP=m ++CONFIG_PPP_ASYNC=m ++CONFIG_PPP_SYNC_TTY=m ++CONFIG_SLIP=m ++CONFIG_SLIP_COMPRESSED=y ++CONFIG_SLIP_SMART=y ++CONFIG_USB_CATC=m ++CONFIG_USB_KAWETH=m ++CONFIG_USB_PEGASUS=m ++CONFIG_USB_RTL8150=m ++CONFIG_USB_RTL8152=m ++CONFIG_USB_USBNET=y ++CONFIG_USB_NET_AX8817X=m ++CONFIG_USB_NET_AX88179_178A=m ++CONFIG_USB_NET_CDCETHER=m ++CONFIG_USB_NET_CDC_EEM=m ++CONFIG_USB_NET_CDC_NCM=m ++CONFIG_USB_NET_HUAWEI_CDC_NCM=m ++CONFIG_USB_NET_CDC_MBIM=m ++CONFIG_USB_NET_DM9601=m ++CONFIG_USB_NET_SR9700=m ++CONFIG_USB_NET_SR9800=m ++CONFIG_USB_NET_SMSC75XX=m ++CONFIG_USB_NET_SMSC95XX=y ++CONFIG_USB_NET_GL620A=m ++CONFIG_USB_NET_NET1080=m ++CONFIG_USB_NET_PLUSB=m ++CONFIG_USB_NET_MCS7830=m ++CONFIG_USB_NET_CDC_SUBSET=m ++CONFIG_USB_ALI_M5632=y ++CONFIG_USB_AN2720=y ++CONFIG_USB_EPSON2888=y ++CONFIG_USB_KC2190=y ++CONFIG_USB_NET_ZAURUS=m ++CONFIG_USB_NET_CX82310_ETH=m ++CONFIG_USB_NET_KALMIA=m ++CONFIG_USB_NET_QMI_WWAN=m ++CONFIG_USB_HSO=m ++CONFIG_USB_NET_INT51X1=m ++CONFIG_USB_IPHETH=m ++CONFIG_USB_SIERRA_NET=m ++CONFIG_USB_VL600=m ++CONFIG_LIBERTAS_THINFIRM=m ++CONFIG_LIBERTAS_THINFIRM_USB=m ++CONFIG_AT76C50X_USB=m ++CONFIG_USB_ZD1201=m ++CONFIG_USB_NET_RNDIS_WLAN=m ++CONFIG_RTL8187=m ++CONFIG_MAC80211_HWSIM=m ++CONFIG_ATH_CARDS=m ++CONFIG_ATH9K=m ++CONFIG_ATH9K_HTC=m ++CONFIG_CARL9170=m ++CONFIG_ATH6KL=m ++CONFIG_ATH6KL_USB=m ++CONFIG_AR5523=m ++CONFIG_B43=m ++# CONFIG_B43_PHY_N is not set ++CONFIG_B43LEGACY=m ++CONFIG_BRCMFMAC=m ++CONFIG_BRCMFMAC_USB=y ++CONFIG_HOSTAP=m ++CONFIG_LIBERTAS=m ++CONFIG_LIBERTAS_USB=m ++CONFIG_LIBERTAS_SDIO=m ++CONFIG_P54_COMMON=m ++CONFIG_P54_USB=m ++CONFIG_RT2X00=m ++CONFIG_RT2500USB=m ++CONFIG_RT73USB=m ++CONFIG_RT2800USB=m ++CONFIG_RT2800USB_RT3573=y ++CONFIG_RT2800USB_RT53XX=y ++CONFIG_RT2800USB_RT55XX=y ++CONFIG_RT2800USB_UNKNOWN=y ++CONFIG_WL_MEDIATEK=y ++CONFIG_MT7601U=m ++CONFIG_RTL8192CU=m ++CONFIG_ZD1211RW=m ++CONFIG_MWIFIEX=m ++CONFIG_MWIFIEX_SDIO=m ++CONFIG_WIMAX_I2400M_USB=m ++CONFIG_IEEE802154_AT86RF230=m ++CONFIG_IEEE802154_MRF24J40=m ++CONFIG_IEEE802154_CC2520=m ++CONFIG_INPUT_POLLDEV=m ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_JOYDEV=m ++CONFIG_INPUT_EVDEV=m ++# CONFIG_KEYBOARD_ATKBD is not set ++CONFIG_KEYBOARD_GPIO=m ++# CONFIG_INPUT_MOUSE is not set ++CONFIG_INPUT_JOYSTICK=y ++CONFIG_JOYSTICK_IFORCE=m ++CONFIG_JOYSTICK_IFORCE_USB=y ++CONFIG_JOYSTICK_XPAD=m ++CONFIG_JOYSTICK_XPAD_FF=y ++CONFIG_JOYSTICK_RPISENSE=m ++CONFIG_INPUT_TOUCHSCREEN=y ++CONFIG_TOUCHSCREEN_ADS7846=m ++CONFIG_TOUCHSCREEN_EGALAX=m ++CONFIG_TOUCHSCREEN_FT6236=m ++CONFIG_TOUCHSCREEN_RPI_FT5406=m ++CONFIG_TOUCHSCREEN_USB_COMPOSITE=m ++CONFIG_TOUCHSCREEN_STMPE=m ++CONFIG_INPUT_MISC=y ++CONFIG_INPUT_AD714X=m ++CONFIG_INPUT_ATI_REMOTE2=m ++CONFIG_INPUT_KEYSPAN_REMOTE=m ++CONFIG_INPUT_POWERMATE=m ++CONFIG_INPUT_YEALINK=m ++CONFIG_INPUT_CM109=m ++CONFIG_INPUT_UINPUT=m ++CONFIG_INPUT_GPIO_ROTARY_ENCODER=m ++CONFIG_INPUT_ADXL34X=m ++CONFIG_INPUT_CMA3000=m ++CONFIG_SERIO=m ++CONFIG_SERIO_RAW=m ++CONFIG_GAMEPORT=m ++CONFIG_GAMEPORT_NS558=m ++CONFIG_GAMEPORT_L4=m ++CONFIG_DEVPTS_MULTIPLE_INSTANCES=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_DEVKMEM is not set ++CONFIG_SERIAL_8250=y ++# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set ++CONFIG_SERIAL_8250_CONSOLE=y ++# CONFIG_SERIAL_8250_DMA is not set ++CONFIG_SERIAL_8250_NR_UARTS=1 ++CONFIG_SERIAL_8250_RUNTIME_UARTS=0 ++CONFIG_SERIAL_AMBA_PL011=y ++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y ++CONFIG_SERIAL_OF_PLATFORM=y ++CONFIG_TTY_PRINTK=y ++CONFIG_HW_RANDOM=y ++CONFIG_HW_RANDOM_BCM2835=m ++CONFIG_HW_RANDOM_BCM2708=m ++CONFIG_RAW_DRIVER=y ++CONFIG_BRCM_CHAR_DRIVERS=y ++CONFIG_BCM_VC_CMA=y ++CONFIG_BCM_VCIO=y ++CONFIG_BCM_VC_SM=y ++CONFIG_I2C=y ++CONFIG_I2C_CHARDEV=m ++CONFIG_I2C_BCM2708=m ++CONFIG_I2C_GPIO=m ++CONFIG_SPI=y ++CONFIG_SPI_BCM2835=m ++CONFIG_SPI_BCM2708=m ++CONFIG_SPI_SPIDEV=y ++CONFIG_PPS=m ++CONFIG_PPS_CLIENT_LDISC=m ++CONFIG_PPS_CLIENT_GPIO=m ++CONFIG_GPIO_SYSFS=y ++CONFIG_GPIO_ARIZONA=m ++CONFIG_GPIO_STMPE=y ++CONFIG_W1=m ++CONFIG_W1_MASTER_DS2490=m ++CONFIG_W1_MASTER_DS2482=m ++CONFIG_W1_MASTER_DS1WM=m ++CONFIG_W1_MASTER_GPIO=m ++CONFIG_W1_SLAVE_THERM=m ++CONFIG_W1_SLAVE_SMEM=m ++CONFIG_W1_SLAVE_DS2408=m ++CONFIG_W1_SLAVE_DS2413=m ++CONFIG_W1_SLAVE_DS2406=m ++CONFIG_W1_SLAVE_DS2423=m ++CONFIG_W1_SLAVE_DS2431=m ++CONFIG_W1_SLAVE_DS2433=m ++CONFIG_W1_SLAVE_DS2760=m ++CONFIG_W1_SLAVE_DS2780=m ++CONFIG_W1_SLAVE_DS2781=m ++CONFIG_W1_SLAVE_DS28E04=m ++CONFIG_W1_SLAVE_BQ27000=m ++CONFIG_BATTERY_DS2760=m ++CONFIG_POWER_RESET=y ++CONFIG_POWER_RESET_GPIO=y ++CONFIG_HWMON=m ++CONFIG_SENSORS_SHT21=m ++CONFIG_SENSORS_SHTC1=m ++CONFIG_THERMAL=y ++CONFIG_THERMAL_BCM2835=y ++CONFIG_WATCHDOG=y ++CONFIG_BCM2708_WDT=m ++CONFIG_BCM2835_WDT=m ++CONFIG_UCB1400_CORE=m ++CONFIG_MFD_STMPE=y ++CONFIG_STMPE_SPI=y ++CONFIG_MFD_ARIZONA_I2C=m ++CONFIG_MFD_ARIZONA_SPI=m ++CONFIG_MFD_WM5102=y ++CONFIG_MEDIA_SUPPORT=m ++CONFIG_MEDIA_CAMERA_SUPPORT=y ++CONFIG_MEDIA_ANALOG_TV_SUPPORT=y ++CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y ++CONFIG_MEDIA_RADIO_SUPPORT=y ++CONFIG_MEDIA_RC_SUPPORT=y ++CONFIG_MEDIA_CONTROLLER=y ++CONFIG_LIRC=m ++CONFIG_RC_DEVICES=y ++CONFIG_RC_ATI_REMOTE=m ++CONFIG_IR_IMON=m ++CONFIG_IR_MCEUSB=m ++CONFIG_IR_REDRAT3=m ++CONFIG_IR_STREAMZAP=m ++CONFIG_IR_IGUANA=m ++CONFIG_IR_TTUSBIR=m ++CONFIG_RC_LOOPBACK=m ++CONFIG_IR_GPIO_CIR=m ++CONFIG_MEDIA_USB_SUPPORT=y ++CONFIG_USB_VIDEO_CLASS=m ++CONFIG_USB_M5602=m ++CONFIG_USB_STV06XX=m ++CONFIG_USB_GL860=m ++CONFIG_USB_GSPCA_BENQ=m ++CONFIG_USB_GSPCA_CONEX=m ++CONFIG_USB_GSPCA_CPIA1=m ++CONFIG_USB_GSPCA_DTCS033=m ++CONFIG_USB_GSPCA_ETOMS=m ++CONFIG_USB_GSPCA_FINEPIX=m ++CONFIG_USB_GSPCA_JEILINJ=m ++CONFIG_USB_GSPCA_JL2005BCD=m ++CONFIG_USB_GSPCA_KINECT=m ++CONFIG_USB_GSPCA_KONICA=m ++CONFIG_USB_GSPCA_MARS=m ++CONFIG_USB_GSPCA_MR97310A=m ++CONFIG_USB_GSPCA_NW80X=m ++CONFIG_USB_GSPCA_OV519=m ++CONFIG_USB_GSPCA_OV534=m ++CONFIG_USB_GSPCA_OV534_9=m ++CONFIG_USB_GSPCA_PAC207=m ++CONFIG_USB_GSPCA_PAC7302=m ++CONFIG_USB_GSPCA_PAC7311=m ++CONFIG_USB_GSPCA_SE401=m ++CONFIG_USB_GSPCA_SN9C2028=m ++CONFIG_USB_GSPCA_SN9C20X=m ++CONFIG_USB_GSPCA_SONIXB=m ++CONFIG_USB_GSPCA_SONIXJ=m ++CONFIG_USB_GSPCA_SPCA500=m ++CONFIG_USB_GSPCA_SPCA501=m ++CONFIG_USB_GSPCA_SPCA505=m ++CONFIG_USB_GSPCA_SPCA506=m ++CONFIG_USB_GSPCA_SPCA508=m ++CONFIG_USB_GSPCA_SPCA561=m ++CONFIG_USB_GSPCA_SPCA1528=m ++CONFIG_USB_GSPCA_SQ905=m ++CONFIG_USB_GSPCA_SQ905C=m ++CONFIG_USB_GSPCA_SQ930X=m ++CONFIG_USB_GSPCA_STK014=m ++CONFIG_USB_GSPCA_STK1135=m ++CONFIG_USB_GSPCA_STV0680=m ++CONFIG_USB_GSPCA_SUNPLUS=m ++CONFIG_USB_GSPCA_T613=m ++CONFIG_USB_GSPCA_TOPRO=m ++CONFIG_USB_GSPCA_TV8532=m ++CONFIG_USB_GSPCA_VC032X=m ++CONFIG_USB_GSPCA_VICAM=m ++CONFIG_USB_GSPCA_XIRLINK_CIT=m ++CONFIG_USB_GSPCA_ZC3XX=m ++CONFIG_USB_PWC=m ++CONFIG_VIDEO_CPIA2=m ++CONFIG_USB_ZR364XX=m ++CONFIG_USB_STKWEBCAM=m ++CONFIG_USB_S2255=m ++CONFIG_VIDEO_USBTV=m ++CONFIG_VIDEO_PVRUSB2=m ++CONFIG_VIDEO_HDPVR=m ++CONFIG_VIDEO_USBVISION=m ++CONFIG_VIDEO_STK1160_COMMON=m ++CONFIG_VIDEO_STK1160_AC97=y ++CONFIG_VIDEO_GO7007=m ++CONFIG_VIDEO_GO7007_USB=m ++CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m ++CONFIG_VIDEO_AU0828=m ++CONFIG_VIDEO_AU0828_RC=y ++CONFIG_VIDEO_CX231XX=m ++CONFIG_VIDEO_CX231XX_ALSA=m ++CONFIG_VIDEO_CX231XX_DVB=m ++CONFIG_VIDEO_TM6000=m ++CONFIG_VIDEO_TM6000_ALSA=m ++CONFIG_VIDEO_TM6000_DVB=m ++CONFIG_DVB_USB=m ++CONFIG_DVB_USB_A800=m ++CONFIG_DVB_USB_DIBUSB_MB=m ++CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y ++CONFIG_DVB_USB_DIBUSB_MC=m ++CONFIG_DVB_USB_DIB0700=m ++CONFIG_DVB_USB_UMT_010=m ++CONFIG_DVB_USB_CXUSB=m ++CONFIG_DVB_USB_M920X=m ++CONFIG_DVB_USB_DIGITV=m ++CONFIG_DVB_USB_VP7045=m ++CONFIG_DVB_USB_VP702X=m ++CONFIG_DVB_USB_GP8PSK=m ++CONFIG_DVB_USB_NOVA_T_USB2=m ++CONFIG_DVB_USB_TTUSB2=m ++CONFIG_DVB_USB_DTT200U=m ++CONFIG_DVB_USB_OPERA1=m ++CONFIG_DVB_USB_AF9005=m ++CONFIG_DVB_USB_AF9005_REMOTE=m ++CONFIG_DVB_USB_PCTV452E=m ++CONFIG_DVB_USB_DW2102=m ++CONFIG_DVB_USB_CINERGY_T2=m ++CONFIG_DVB_USB_DTV5100=m ++CONFIG_DVB_USB_FRIIO=m ++CONFIG_DVB_USB_AZ6027=m ++CONFIG_DVB_USB_TECHNISAT_USB2=m ++CONFIG_DVB_USB_V2=m ++CONFIG_DVB_USB_AF9015=m ++CONFIG_DVB_USB_AF9035=m ++CONFIG_DVB_USB_ANYSEE=m ++CONFIG_DVB_USB_AU6610=m ++CONFIG_DVB_USB_AZ6007=m ++CONFIG_DVB_USB_CE6230=m ++CONFIG_DVB_USB_EC168=m ++CONFIG_DVB_USB_GL861=m ++CONFIG_DVB_USB_LME2510=m ++CONFIG_DVB_USB_MXL111SF=m ++CONFIG_DVB_USB_RTL28XXU=m ++CONFIG_DVB_USB_DVBSKY=m ++CONFIG_SMS_USB_DRV=m ++CONFIG_DVB_B2C2_FLEXCOP_USB=m ++CONFIG_DVB_AS102=m ++CONFIG_VIDEO_EM28XX=m ++CONFIG_VIDEO_EM28XX_V4L2=m ++CONFIG_VIDEO_EM28XX_ALSA=m ++CONFIG_VIDEO_EM28XX_DVB=m ++CONFIG_V4L_PLATFORM_DRIVERS=y ++CONFIG_VIDEO_BCM2835=y ++CONFIG_VIDEO_BCM2835_MMAL=m ++CONFIG_RADIO_SI470X=y ++CONFIG_USB_SI470X=m ++CONFIG_I2C_SI470X=m ++CONFIG_RADIO_SI4713=m ++CONFIG_I2C_SI4713=m ++CONFIG_USB_MR800=m ++CONFIG_USB_DSBR=m ++CONFIG_RADIO_SHARK=m ++CONFIG_RADIO_SHARK2=m ++CONFIG_USB_KEENE=m ++CONFIG_USB_MA901=m ++CONFIG_RADIO_TEA5764=m ++CONFIG_RADIO_SAA7706H=m ++CONFIG_RADIO_TEF6862=m ++CONFIG_RADIO_WL1273=m ++CONFIG_RADIO_WL128X=m ++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set ++CONFIG_VIDEO_UDA1342=m ++CONFIG_VIDEO_SONY_BTF_MPX=m ++CONFIG_VIDEO_TVP5150=m ++CONFIG_VIDEO_TW2804=m ++CONFIG_VIDEO_TW9903=m ++CONFIG_VIDEO_TW9906=m ++CONFIG_VIDEO_OV7640=m ++CONFIG_VIDEO_MT9V011=m ++CONFIG_FB=y ++CONFIG_FB_BCM2708=y ++CONFIG_FB_UDL=m ++CONFIG_FB_SSD1307=m ++CONFIG_FB_RPISENSE=m ++# CONFIG_BACKLIGHT_GENERIC is not set ++CONFIG_BACKLIGHT_RPI=m ++CONFIG_BACKLIGHT_GPIO=m ++CONFIG_FRAMEBUFFER_CONSOLE=y ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++CONFIG_SOUND=y ++CONFIG_SND=m ++CONFIG_SND_SEQUENCER=m ++CONFIG_SND_SEQ_DUMMY=m ++CONFIG_SND_MIXER_OSS=m ++CONFIG_SND_PCM_OSS=m ++CONFIG_SND_SEQUENCER_OSS=y ++CONFIG_SND_HRTIMER=m ++CONFIG_SND_DUMMY=m ++CONFIG_SND_ALOOP=m ++CONFIG_SND_VIRMIDI=m ++CONFIG_SND_MTPAV=m ++CONFIG_SND_SERIAL_U16550=m ++CONFIG_SND_MPU401=m ++CONFIG_SND_BCM2835=m ++CONFIG_SND_USB_AUDIO=m ++CONFIG_SND_USB_UA101=m ++CONFIG_SND_USB_CAIAQ=m ++CONFIG_SND_USB_CAIAQ_INPUT=y ++CONFIG_SND_USB_6FIRE=m ++CONFIG_SND_SOC=m ++CONFIG_SND_BCM2708_SOC_I2S=m ++CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m ++CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m ++CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m ++CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m ++CONFIG_SND_BCM2708_SOC_RPI_DAC=m ++CONFIG_SND_BCM2708_SOC_RPI_PROTO=m ++CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m ++CONFIG_SND_BCM2708_SOC_RASPIDAC3=m ++CONFIG_SND_SOC_ADAU1701=m ++CONFIG_SND_SOC_WM8804_I2C=m ++CONFIG_SND_SIMPLE_CARD=m ++CONFIG_SOUND_PRIME=m ++CONFIG_HIDRAW=y ++CONFIG_UHID=m ++CONFIG_HID_A4TECH=m ++CONFIG_HID_ACRUX=m ++CONFIG_HID_APPLE=m ++CONFIG_HID_BELKIN=m ++CONFIG_HID_CHERRY=m ++CONFIG_HID_CHICONY=m ++CONFIG_HID_CYPRESS=m ++CONFIG_HID_DRAGONRISE=m ++CONFIG_HID_EMS_FF=m ++CONFIG_HID_ELECOM=m ++CONFIG_HID_ELO=m ++CONFIG_HID_EZKEY=m ++CONFIG_HID_HOLTEK=m ++CONFIG_HID_KEYTOUCH=m ++CONFIG_HID_KYE=m ++CONFIG_HID_UCLOGIC=m ++CONFIG_HID_WALTOP=m ++CONFIG_HID_GYRATION=m ++CONFIG_HID_TWINHAN=m ++CONFIG_HID_KENSINGTON=m ++CONFIG_HID_LCPOWER=m ++CONFIG_HID_LOGITECH=m ++CONFIG_HID_MAGICMOUSE=m ++CONFIG_HID_MICROSOFT=m ++CONFIG_HID_MONTEREY=m ++CONFIG_HID_MULTITOUCH=m ++CONFIG_HID_NTRIG=m ++CONFIG_HID_ORTEK=m ++CONFIG_HID_PANTHERLORD=m ++CONFIG_HID_PETALYNX=m ++CONFIG_HID_PICOLCD=m ++CONFIG_HID_ROCCAT=m ++CONFIG_HID_SAMSUNG=m ++CONFIG_HID_SONY=m ++CONFIG_HID_SPEEDLINK=m ++CONFIG_HID_SUNPLUS=m ++CONFIG_HID_GREENASIA=m ++CONFIG_HID_SMARTJOYPLUS=m ++CONFIG_HID_TOPSEED=m ++CONFIG_HID_THINGM=m ++CONFIG_HID_THRUSTMASTER=m ++CONFIG_HID_WACOM=m ++CONFIG_HID_WIIMOTE=m ++CONFIG_HID_XINMO=m ++CONFIG_HID_ZEROPLUS=m ++CONFIG_HID_ZYDACRON=m ++CONFIG_HID_PID=y ++CONFIG_USB_HIDDEV=y ++CONFIG_USB=y ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++CONFIG_USB_MON=m ++CONFIG_USB_DWCOTG=y ++CONFIG_USB_PRINTER=m ++CONFIG_USB_STORAGE=y ++CONFIG_USB_STORAGE_REALTEK=m ++CONFIG_USB_STORAGE_DATAFAB=m ++CONFIG_USB_STORAGE_FREECOM=m ++CONFIG_USB_STORAGE_ISD200=m ++CONFIG_USB_STORAGE_USBAT=m ++CONFIG_USB_STORAGE_SDDR09=m ++CONFIG_USB_STORAGE_SDDR55=m ++CONFIG_USB_STORAGE_JUMPSHOT=m ++CONFIG_USB_STORAGE_ALAUDA=m ++CONFIG_USB_STORAGE_ONETOUCH=m ++CONFIG_USB_STORAGE_KARMA=m ++CONFIG_USB_STORAGE_CYPRESS_ATACB=m ++CONFIG_USB_STORAGE_ENE_UB6250=m ++CONFIG_USB_MDC800=m ++CONFIG_USB_MICROTEK=m ++CONFIG_USBIP_CORE=m ++CONFIG_USBIP_VHCI_HCD=m ++CONFIG_USBIP_HOST=m ++CONFIG_USB_SERIAL=m ++CONFIG_USB_SERIAL_GENERIC=y ++CONFIG_USB_SERIAL_AIRCABLE=m ++CONFIG_USB_SERIAL_ARK3116=m ++CONFIG_USB_SERIAL_BELKIN=m ++CONFIG_USB_SERIAL_CH341=m ++CONFIG_USB_SERIAL_WHITEHEAT=m ++CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m ++CONFIG_USB_SERIAL_CP210X=m ++CONFIG_USB_SERIAL_CYPRESS_M8=m ++CONFIG_USB_SERIAL_EMPEG=m ++CONFIG_USB_SERIAL_FTDI_SIO=m ++CONFIG_USB_SERIAL_VISOR=m ++CONFIG_USB_SERIAL_IPAQ=m ++CONFIG_USB_SERIAL_IR=m ++CONFIG_USB_SERIAL_EDGEPORT=m ++CONFIG_USB_SERIAL_EDGEPORT_TI=m ++CONFIG_USB_SERIAL_F81232=m ++CONFIG_USB_SERIAL_GARMIN=m ++CONFIG_USB_SERIAL_IPW=m ++CONFIG_USB_SERIAL_IUU=m ++CONFIG_USB_SERIAL_KEYSPAN_PDA=m ++CONFIG_USB_SERIAL_KEYSPAN=m ++CONFIG_USB_SERIAL_KLSI=m ++CONFIG_USB_SERIAL_KOBIL_SCT=m ++CONFIG_USB_SERIAL_MCT_U232=m ++CONFIG_USB_SERIAL_METRO=m ++CONFIG_USB_SERIAL_MOS7720=m ++CONFIG_USB_SERIAL_MOS7840=m ++CONFIG_USB_SERIAL_NAVMAN=m ++CONFIG_USB_SERIAL_PL2303=m ++CONFIG_USB_SERIAL_OTI6858=m ++CONFIG_USB_SERIAL_QCAUX=m ++CONFIG_USB_SERIAL_QUALCOMM=m ++CONFIG_USB_SERIAL_SPCP8X5=m ++CONFIG_USB_SERIAL_SAFE=m ++CONFIG_USB_SERIAL_SIERRAWIRELESS=m ++CONFIG_USB_SERIAL_SYMBOL=m ++CONFIG_USB_SERIAL_TI=m ++CONFIG_USB_SERIAL_CYBERJACK=m ++CONFIG_USB_SERIAL_XIRCOM=m ++CONFIG_USB_SERIAL_OPTION=m ++CONFIG_USB_SERIAL_OMNINET=m ++CONFIG_USB_SERIAL_OPTICON=m ++CONFIG_USB_SERIAL_XSENS_MT=m ++CONFIG_USB_SERIAL_WISHBONE=m ++CONFIG_USB_SERIAL_SSU100=m ++CONFIG_USB_SERIAL_QT2=m ++CONFIG_USB_SERIAL_DEBUG=m ++CONFIG_USB_EMI62=m ++CONFIG_USB_EMI26=m ++CONFIG_USB_ADUTUX=m ++CONFIG_USB_SEVSEG=m ++CONFIG_USB_RIO500=m ++CONFIG_USB_LEGOTOWER=m ++CONFIG_USB_LCD=m ++CONFIG_USB_LED=m ++CONFIG_USB_CYPRESS_CY7C63=m ++CONFIG_USB_CYTHERM=m ++CONFIG_USB_IDMOUSE=m ++CONFIG_USB_FTDI_ELAN=m ++CONFIG_USB_APPLEDISPLAY=m ++CONFIG_USB_LD=m ++CONFIG_USB_TRANCEVIBRATOR=m ++CONFIG_USB_IOWARRIOR=m ++CONFIG_USB_TEST=m ++CONFIG_USB_ISIGHTFW=m ++CONFIG_USB_YUREX=m ++CONFIG_USB_ATM=m ++CONFIG_USB_SPEEDTOUCH=m ++CONFIG_USB_CXACRU=m ++CONFIG_USB_UEAGLEATM=m ++CONFIG_USB_XUSBATM=m ++CONFIG_MMC=y ++CONFIG_MMC_BLOCK_MINORS=32 ++CONFIG_MMC_BCM2835=y ++CONFIG_MMC_BCM2835_DMA=y ++CONFIG_MMC_BCM2835_SDHOST=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_PLTFM=y ++CONFIG_MMC_SPI=m ++CONFIG_LEDS_CLASS=y ++CONFIG_LEDS_GPIO=y ++CONFIG_LEDS_TRIGGER_TIMER=y ++CONFIG_LEDS_TRIGGER_ONESHOT=y ++CONFIG_LEDS_TRIGGER_HEARTBEAT=y ++CONFIG_LEDS_TRIGGER_BACKLIGHT=y ++CONFIG_LEDS_TRIGGER_CPU=y ++CONFIG_LEDS_TRIGGER_GPIO=y ++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y ++CONFIG_LEDS_TRIGGER_TRANSIENT=m ++CONFIG_LEDS_TRIGGER_CAMERA=m ++CONFIG_LEDS_TRIGGER_INPUT=y ++CONFIG_RTC_CLASS=y ++# CONFIG_RTC_HCTOSYS is not set ++CONFIG_RTC_DRV_DS1307=m ++CONFIG_RTC_DRV_DS1374=m ++CONFIG_RTC_DRV_DS1672=m ++CONFIG_RTC_DRV_DS3232=m ++CONFIG_RTC_DRV_MAX6900=m ++CONFIG_RTC_DRV_RS5C372=m ++CONFIG_RTC_DRV_ISL1208=m ++CONFIG_RTC_DRV_ISL12022=m ++CONFIG_RTC_DRV_ISL12057=m ++CONFIG_RTC_DRV_X1205=m ++CONFIG_RTC_DRV_PCF2127=m ++CONFIG_RTC_DRV_PCF8523=m ++CONFIG_RTC_DRV_PCF8563=m ++CONFIG_RTC_DRV_PCF8583=m ++CONFIG_RTC_DRV_M41T80=m ++CONFIG_RTC_DRV_BQ32K=m ++CONFIG_RTC_DRV_S35390A=m ++CONFIG_RTC_DRV_FM3130=m ++CONFIG_RTC_DRV_RX8581=m ++CONFIG_RTC_DRV_RX8025=m ++CONFIG_RTC_DRV_EM3027=m ++CONFIG_RTC_DRV_RV3029C2=m ++CONFIG_RTC_DRV_M41T93=m ++CONFIG_RTC_DRV_M41T94=m ++CONFIG_RTC_DRV_DS1305=m ++CONFIG_RTC_DRV_DS1390=m ++CONFIG_RTC_DRV_MAX6902=m ++CONFIG_RTC_DRV_R9701=m ++CONFIG_RTC_DRV_RS5C348=m ++CONFIG_RTC_DRV_DS3234=m ++CONFIG_RTC_DRV_PCF2123=m ++CONFIG_RTC_DRV_RX4581=m ++CONFIG_DMADEVICES=y ++CONFIG_DMA_BCM2708=y ++CONFIG_UIO=m ++CONFIG_UIO_PDRV_GENIRQ=m ++CONFIG_STAGING=y ++CONFIG_PRISM2_USB=m ++CONFIG_R8712U=m ++CONFIG_R8188EU=m ++CONFIG_R8723AU=m ++CONFIG_VT6656=m ++CONFIG_SPEAKUP=m ++CONFIG_SPEAKUP_SYNTH_SOFT=m ++CONFIG_STAGING_MEDIA=y ++CONFIG_LIRC_STAGING=y ++CONFIG_LIRC_IMON=m ++CONFIG_LIRC_RPI=m ++CONFIG_LIRC_SASEM=m ++CONFIG_LIRC_SERIAL=m ++CONFIG_FB_TFT=m ++CONFIG_FB_TFT_AGM1264K_FL=m ++CONFIG_FB_TFT_BD663474=m ++CONFIG_FB_TFT_HX8340BN=m ++CONFIG_FB_TFT_HX8347D=m ++CONFIG_FB_TFT_HX8353D=m ++CONFIG_FB_TFT_ILI9163=m ++CONFIG_FB_TFT_ILI9320=m ++CONFIG_FB_TFT_ILI9325=m ++CONFIG_FB_TFT_ILI9340=m ++CONFIG_FB_TFT_ILI9341=m ++CONFIG_FB_TFT_ILI9481=m ++CONFIG_FB_TFT_ILI9486=m ++CONFIG_FB_TFT_PCD8544=m ++CONFIG_FB_TFT_RA8875=m ++CONFIG_FB_TFT_S6D02A1=m ++CONFIG_FB_TFT_S6D1121=m ++CONFIG_FB_TFT_SSD1289=m ++CONFIG_FB_TFT_SSD1306=m ++CONFIG_FB_TFT_SSD1331=m ++CONFIG_FB_TFT_SSD1351=m ++CONFIG_FB_TFT_ST7735R=m ++CONFIG_FB_TFT_TINYLCD=m ++CONFIG_FB_TFT_TLS8204=m ++CONFIG_FB_TFT_UC1701=m ++CONFIG_FB_TFT_UPD161704=m ++CONFIG_FB_TFT_WATTEROTT=m ++CONFIG_FB_FLEX=m ++CONFIG_FB_TFT_FBTFT_DEVICE=m ++CONFIG_MAILBOX=y ++CONFIG_BCM2835_MBOX=y ++# CONFIG_IOMMU_SUPPORT is not set ++CONFIG_EXTCON=m ++CONFIG_EXTCON_ARIZONA=m ++CONFIG_IIO=m ++CONFIG_IIO_BUFFER=y ++CONFIG_IIO_BUFFER_CB=y ++CONFIG_IIO_KFIFO_BUF=m ++CONFIG_MCP320X=m ++CONFIG_DHT11=m ++CONFIG_PWM_BCM2835=m ++CONFIG_RASPBERRYPI_FIRMWARE=y ++CONFIG_EXT4_FS=y ++CONFIG_EXT4_FS_POSIX_ACL=y ++CONFIG_EXT4_FS_SECURITY=y ++CONFIG_REISERFS_FS=m ++CONFIG_REISERFS_FS_XATTR=y ++CONFIG_REISERFS_FS_POSIX_ACL=y ++CONFIG_REISERFS_FS_SECURITY=y ++CONFIG_JFS_FS=m ++CONFIG_JFS_POSIX_ACL=y ++CONFIG_JFS_SECURITY=y ++CONFIG_JFS_STATISTICS=y ++CONFIG_XFS_FS=m ++CONFIG_XFS_QUOTA=y ++CONFIG_XFS_POSIX_ACL=y ++CONFIG_XFS_RT=y ++CONFIG_GFS2_FS=m ++CONFIG_OCFS2_FS=m ++CONFIG_BTRFS_FS=m ++CONFIG_BTRFS_FS_POSIX_ACL=y ++CONFIG_NILFS2_FS=m ++CONFIG_F2FS_FS=y ++CONFIG_FANOTIFY=y ++CONFIG_QFMT_V1=m ++CONFIG_QFMT_V2=m ++CONFIG_AUTOFS4_FS=y ++CONFIG_FUSE_FS=m ++CONFIG_CUSE=m ++CONFIG_OVERLAY_FS=m ++CONFIG_FSCACHE=y ++CONFIG_FSCACHE_STATS=y ++CONFIG_FSCACHE_HISTOGRAM=y ++CONFIG_CACHEFILES=y ++CONFIG_ISO9660_FS=m ++CONFIG_JOLIET=y ++CONFIG_ZISOFS=y ++CONFIG_UDF_FS=m ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_IOCHARSET="ascii" ++CONFIG_NTFS_FS=m ++CONFIG_NTFS_RW=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_CONFIGFS_FS=y ++CONFIG_ECRYPT_FS=m ++CONFIG_HFS_FS=m ++CONFIG_HFSPLUS_FS=m ++CONFIG_JFFS2_FS=m ++CONFIG_JFFS2_SUMMARY=y ++CONFIG_UBIFS_FS=m ++CONFIG_SQUASHFS=m ++CONFIG_SQUASHFS_XATTR=y ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3_ACL=y ++CONFIG_NFS_V4=y ++CONFIG_NFS_SWAP=y ++CONFIG_ROOT_NFS=y ++CONFIG_NFS_FSCACHE=y ++CONFIG_NFSD=m ++CONFIG_NFSD_V3_ACL=y ++CONFIG_NFSD_V4=y ++CONFIG_CIFS=m ++CONFIG_CIFS_WEAK_PW_HASH=y ++CONFIG_CIFS_UPCALL=y ++CONFIG_CIFS_XATTR=y ++CONFIG_CIFS_POSIX=y ++CONFIG_CIFS_ACL=y ++CONFIG_CIFS_DFS_UPCALL=y ++CONFIG_CIFS_SMB2=y ++CONFIG_CIFS_FSCACHE=y ++CONFIG_9P_FS=m ++CONFIG_9P_FS_POSIX_ACL=y ++CONFIG_NLS_DEFAULT="utf8" ++CONFIG_NLS_CODEPAGE_437=y ++CONFIG_NLS_CODEPAGE_737=m ++CONFIG_NLS_CODEPAGE_775=m ++CONFIG_NLS_CODEPAGE_850=m ++CONFIG_NLS_CODEPAGE_852=m ++CONFIG_NLS_CODEPAGE_855=m ++CONFIG_NLS_CODEPAGE_857=m ++CONFIG_NLS_CODEPAGE_860=m ++CONFIG_NLS_CODEPAGE_861=m ++CONFIG_NLS_CODEPAGE_862=m ++CONFIG_NLS_CODEPAGE_863=m ++CONFIG_NLS_CODEPAGE_864=m ++CONFIG_NLS_CODEPAGE_865=m ++CONFIG_NLS_CODEPAGE_866=m ++CONFIG_NLS_CODEPAGE_869=m ++CONFIG_NLS_CODEPAGE_936=m ++CONFIG_NLS_CODEPAGE_950=m ++CONFIG_NLS_CODEPAGE_932=m ++CONFIG_NLS_CODEPAGE_949=m ++CONFIG_NLS_CODEPAGE_874=m ++CONFIG_NLS_ISO8859_8=m ++CONFIG_NLS_CODEPAGE_1250=m ++CONFIG_NLS_CODEPAGE_1251=m ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=m ++CONFIG_NLS_ISO8859_2=m ++CONFIG_NLS_ISO8859_3=m ++CONFIG_NLS_ISO8859_4=m ++CONFIG_NLS_ISO8859_5=m ++CONFIG_NLS_ISO8859_6=m ++CONFIG_NLS_ISO8859_7=m ++CONFIG_NLS_ISO8859_9=m ++CONFIG_NLS_ISO8859_13=m ++CONFIG_NLS_ISO8859_14=m ++CONFIG_NLS_ISO8859_15=m ++CONFIG_NLS_KOI8_R=m ++CONFIG_NLS_KOI8_U=m ++CONFIG_DLM=m ++CONFIG_PRINTK_TIME=y ++CONFIG_BOOT_PRINTK_DELAY=y ++CONFIG_DEBUG_MEMORY_INIT=y ++CONFIG_DETECT_HUNG_TASK=y ++CONFIG_TIMER_STATS=y ++# CONFIG_DEBUG_PREEMPT is not set ++CONFIG_LATENCYTOP=y ++CONFIG_IRQSOFF_TRACER=y ++CONFIG_SCHED_TRACER=y ++CONFIG_STACK_TRACER=y ++CONFIG_BLK_DEV_IO_TRACE=y ++# CONFIG_KPROBE_EVENT is not set ++CONFIG_FUNCTION_PROFILER=y ++CONFIG_KGDB=y ++CONFIG_KGDB_KDB=y ++CONFIG_KDB_KEYBOARD=y ++CONFIG_CRYPTO_USER=m ++CONFIG_CRYPTO_CRYPTD=m ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTS=m ++CONFIG_CRYPTO_XTS=m ++CONFIG_CRYPTO_XCBC=m ++CONFIG_CRYPTO_SHA512=m ++CONFIG_CRYPTO_TGR192=m ++CONFIG_CRYPTO_WP512=m ++CONFIG_CRYPTO_CAST5=m ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++CONFIG_CRYPTO_USER_API_SKCIPHER=m ++# CONFIG_CRYPTO_HW is not set ++CONFIG_ARM_CRYPTO=y ++CONFIG_CRYPTO_SHA1_ARM=m ++CONFIG_CRYPTO_AES_ARM=m ++CONFIG_CRC_ITU_T=y ++CONFIG_LIBCRC32C=y +diff -Nur linux-4.1.13.orig/arch/arm/include/asm/entry-macro-multi.S linux-rpi/arch/arm/include/asm/entry-macro-multi.S +--- linux-4.1.13.orig/arch/arm/include/asm/entry-macro-multi.S 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/arch/arm/include/asm/entry-macro-multi.S 2015-11-29 09:42:34.731443387 +0100 +@@ -1,5 +1,6 @@ + #include + ++#ifndef CONFIG_ARCH_BCM2709 + /* + * Interrupt handling. Preserves r7, r8, r9 + */ +@@ -28,6 +29,7 @@ + #endif + 9997: + .endm ++#endif + + .macro arch_irq_handler, symbol_name + .align 5 +diff -Nur linux-4.1.13.orig/arch/arm/include/asm/irqflags.h linux-rpi/arch/arm/include/asm/irqflags.h +--- linux-4.1.13.orig/arch/arm/include/asm/irqflags.h 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/arch/arm/include/asm/irqflags.h 2015-11-29 09:42:34.735443122 +0100 +@@ -145,12 +145,22 @@ + } + + /* +- * restore saved IRQ & FIQ state ++ * restore saved IRQ state + */ + static inline void arch_local_irq_restore(unsigned long flags) + { +- asm volatile( +- " msr " IRQMASK_REG_NAME_W ", %0 @ local_irq_restore" ++ unsigned long temp = 0; ++ flags &= ~(1 << 6); ++ asm volatile ( ++ " mrs %0, cpsr" ++ : "=r" (temp) ++ : ++ : "memory", "cc"); ++ /* Preserve FIQ bit */ ++ temp &= (1 << 6); ++ flags = flags | temp; ++ asm volatile ( ++ " msr cpsr_c, %0 @ local_irq_restore" + : + : "r" (flags) + : "memory", "cc"); +diff -Nur linux-4.1.13.orig/arch/arm/include/asm/string.h linux-rpi/arch/arm/include/asm/string.h +--- linux-4.1.13.orig/arch/arm/include/asm/string.h 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/arch/arm/include/asm/string.h 2015-11-29 09:42:34.739442856 +0100 +@@ -24,6 +24,11 @@ + #define __HAVE_ARCH_MEMSET + extern void * memset(void *, int, __kernel_size_t); + ++#ifdef CONFIG_MACH_BCM2708 ++#define __HAVE_ARCH_MEMCMP ++extern int memcmp(const void *, const void *, size_t); ++#endif ++ + extern void __memzero(void *ptr, __kernel_size_t n); + + #define memset(p,v,n) \ +diff -Nur linux-4.1.13.orig/arch/arm/include/asm/uaccess.h linux-rpi/arch/arm/include/asm/uaccess.h +--- linux-4.1.13.orig/arch/arm/include/asm/uaccess.h 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/arch/arm/include/asm/uaccess.h 2015-11-29 09:42:34.739442856 +0100 +@@ -475,6 +475,7 @@ + + #ifdef CONFIG_MMU + extern unsigned long __must_check __copy_from_user(void *to, const void __user *from, unsigned long n); ++extern unsigned long __must_check __copy_from_user_std(void *to, const void __user *from, unsigned long n); + extern unsigned long __must_check __copy_to_user(void __user *to, const void *from, unsigned long n); + extern unsigned long __must_check __copy_to_user_std(void __user *to, const void *from, unsigned long n); + extern unsigned long __must_check __clear_user(void __user *addr, unsigned long n); +diff -Nur linux-4.1.13.orig/arch/arm/Kconfig linux-rpi/arch/arm/Kconfig +--- linux-4.1.13.orig/arch/arm/Kconfig 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/arch/arm/Kconfig 2015-11-29 09:42:34.555455081 +0100 +@@ -314,6 +314,42 @@ + default ARCH_VERSATILE if !MMU + default ARCH_MULTIPLATFORM if MMU + ++config ARCH_BCM2708 ++ bool "Broadcom BCM2708 family" ++ select CPU_V6 ++ select ARM_AMBA ++ select HAVE_SCHED_CLOCK ++ select NEED_MACH_GPIO_H ++ select NEED_MACH_MEMORY_H ++ select COMMON_CLK ++ select ARCH_HAS_CPUFREQ ++ select GENERIC_CLOCKEVENTS ++ select ARM_ERRATA_411920 ++ select MACH_BCM2708 ++ select VC4 ++ select FIQ ++ help ++ This enables support for Broadcom BCM2708 boards. ++ ++config ARCH_BCM2709 ++ bool "Broadcom BCM2709 family" ++ select ARCH_HAS_BARRIERS if SMP ++ select CPU_V7 ++ select HAVE_SMP ++ select ARM_AMBA ++ select MIGHT_HAVE_CACHE_L2X0 ++ select HAVE_SCHED_CLOCK ++ select NEED_MACH_MEMORY_H ++ select NEED_MACH_IO_H ++ select COMMON_CLK ++ select ARCH_HAS_CPUFREQ ++ select GENERIC_CLOCKEVENTS ++ select MACH_BCM2709 ++ select VC4 ++ select FIQ ++ help ++ This enables support for Broadcom BCM2709 boards. ++ + config ARCH_MULTIPLATFORM + bool "Allow multiple platforms to be selected" + depends on MMU +@@ -824,6 +860,9 @@ + # Kconfigs may be included either alphabetically (according to the + # plat- suffix) or along side the corresponding mach-* source. + # ++source "arch/arm/mach-bcm2708/Kconfig" ++source "arch/arm/mach-bcm2709/Kconfig" ++ + source "arch/arm/mach-mvebu/Kconfig" + + source "arch/arm/mach-alpine/Kconfig" +diff -Nur linux-4.1.13.orig/arch/arm/Kconfig.debug linux-rpi/arch/arm/Kconfig.debug +--- linux-4.1.13.orig/arch/arm/Kconfig.debug 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/arch/arm/Kconfig.debug 2015-11-29 09:42:34.559454815 +0100 +@@ -1197,6 +1197,14 @@ + options; the platform specific options are deprecated + and will be soon removed. + ++ config DEBUG_BCM2708_UART0 ++ bool "Broadcom BCM2708 UART0 (PL011)" ++ depends on MACH_BCM2708 ++ help ++ Say Y here if you want the debug print routines to direct ++ their output to UART 0. The port must have been initialised ++ by the boot-loader before use. ++ + endchoice + + config DEBUG_AT91_UART +diff -Nur linux-4.1.13.orig/arch/arm/kernel/fiqasm.S linux-rpi/arch/arm/kernel/fiqasm.S +--- linux-4.1.13.orig/arch/arm/kernel/fiqasm.S 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/arch/arm/kernel/fiqasm.S 2015-11-29 09:42:34.743442590 +0100 +@@ -47,3 +47,7 @@ + mov r0, r0 @ avoid hazard prior to ARMv4 + ret lr + ENDPROC(__get_fiq_regs) ++ ++ENTRY(__FIQ_Branch) ++ mov pc, r8 ++ENDPROC(__FIQ_Branch) +diff -Nur linux-4.1.13.orig/arch/arm/kernel/head.S linux-rpi/arch/arm/kernel/head.S +--- linux-4.1.13.orig/arch/arm/kernel/head.S 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/arch/arm/kernel/head.S 2015-11-29 09:42:34.747442324 +0100 +@@ -680,6 +680,14 @@ + ldrcc r7, [r4], #4 @ use branch for delay slot + bcc 1b + ret lr ++ nop ++ nop ++ nop ++ nop ++ nop ++ nop ++ nop ++ nop + #endif + ENDPROC(__fixup_a_pv_table) + +diff -Nur linux-4.1.13.orig/arch/arm/kernel/process.c linux-rpi/arch/arm/kernel/process.c +--- linux-4.1.13.orig/arch/arm/kernel/process.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/arch/arm/kernel/process.c 2015-11-29 09:42:34.747442324 +0100 +@@ -98,6 +98,16 @@ + } + #endif + ++char bcm2708_reboot_mode = 'h'; ++ ++int __init reboot_setup(char *str) ++{ ++ bcm2708_reboot_mode = str[0]; ++ return 1; ++} ++ ++__setup("reboot=", reboot_setup); ++ + void __show_regs(struct pt_regs *regs) + { + unsigned long flags; +diff -Nur linux-4.1.13.orig/arch/arm/lib/arm-mem.h linux-rpi/arch/arm/lib/arm-mem.h +--- linux-4.1.13.orig/arch/arm/lib/arm-mem.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/lib/arm-mem.h 2015-11-29 09:42:34.767440995 +0100 +@@ -0,0 +1,159 @@ ++/* ++Copyright (c) 2013, Raspberry Pi Foundation ++Copyright (c) 2013, RISC OS Open Ltd ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions are met: ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ * Neither the name of the copyright holder nor the ++ names of its contributors may be used to endorse or promote products ++ derived from this software without specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY ++DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++*/ ++ ++.macro myfunc fname ++ .func fname ++ .global fname ++fname: ++.endm ++ ++.macro preload_leading_step1 backwards, ptr, base ++/* If the destination is already 16-byte aligned, then we need to preload ++ * between 0 and prefetch_distance (inclusive) cache lines ahead so there ++ * are no gaps when the inner loop starts. ++ */ ++ .if backwards ++ sub ptr, base, #1 ++ bic ptr, ptr, #31 ++ .else ++ bic ptr, base, #31 ++ .endif ++ .set OFFSET, 0 ++ .rept prefetch_distance+1 ++ pld [ptr, #OFFSET] ++ .if backwards ++ .set OFFSET, OFFSET-32 ++ .else ++ .set OFFSET, OFFSET+32 ++ .endif ++ .endr ++.endm ++ ++.macro preload_leading_step2 backwards, ptr, base, leading_bytes, tmp ++/* However, if the destination is not 16-byte aligned, we may need to ++ * preload one more cache line than that. The question we need to ask is: ++ * are the leading bytes more than the amount by which the source ++ * pointer will be rounded down for preloading, and if so, by how many ++ * cache lines? ++ */ ++ .if backwards ++/* Here we compare against how many bytes we are into the ++ * cache line, counting down from the highest such address. ++ * Effectively, we want to calculate ++ * leading_bytes = dst&15 ++ * cacheline_offset = 31-((src-leading_bytes-1)&31) ++ * extra_needed = leading_bytes - cacheline_offset ++ * and test if extra_needed is <= 0, or rearranging: ++ * leading_bytes + (src-leading_bytes-1)&31 <= 31 ++ */ ++ mov tmp, base, lsl #32-5 ++ sbc tmp, tmp, leading_bytes, lsl #32-5 ++ adds tmp, tmp, leading_bytes, lsl #32-5 ++ bcc 61f ++ pld [ptr, #-32*(prefetch_distance+1)] ++ .else ++/* Effectively, we want to calculate ++ * leading_bytes = (-dst)&15 ++ * cacheline_offset = (src+leading_bytes)&31 ++ * extra_needed = leading_bytes - cacheline_offset ++ * and test if extra_needed is <= 0. ++ */ ++ mov tmp, base, lsl #32-5 ++ add tmp, tmp, leading_bytes, lsl #32-5 ++ rsbs tmp, tmp, leading_bytes, lsl #32-5 ++ bls 61f ++ pld [ptr, #32*(prefetch_distance+1)] ++ .endif ++61: ++.endm ++ ++.macro preload_trailing backwards, base, remain, tmp ++ /* We need either 0, 1 or 2 extra preloads */ ++ .if backwards ++ rsb tmp, base, #0 ++ mov tmp, tmp, lsl #32-5 ++ .else ++ mov tmp, base, lsl #32-5 ++ .endif ++ adds tmp, tmp, remain, lsl #32-5 ++ adceqs tmp, tmp, #0 ++ /* The instruction above has two effects: ensures Z is only ++ * set if C was clear (so Z indicates that both shifted quantities ++ * were 0), and clears C if Z was set (so C indicates that the sum ++ * of the shifted quantities was greater and not equal to 32) */ ++ beq 82f ++ .if backwards ++ sub tmp, base, #1 ++ bic tmp, tmp, #31 ++ .else ++ bic tmp, base, #31 ++ .endif ++ bcc 81f ++ .if backwards ++ pld [tmp, #-32*(prefetch_distance+1)] ++81: ++ pld [tmp, #-32*prefetch_distance] ++ .else ++ pld [tmp, #32*(prefetch_distance+2)] ++81: ++ pld [tmp, #32*(prefetch_distance+1)] ++ .endif ++82: ++.endm ++ ++.macro preload_all backwards, narrow_case, shift, base, remain, tmp0, tmp1 ++ .if backwards ++ sub tmp0, base, #1 ++ bic tmp0, tmp0, #31 ++ pld [tmp0] ++ sub tmp1, base, remain, lsl #shift ++ .else ++ bic tmp0, base, #31 ++ pld [tmp0] ++ add tmp1, base, remain, lsl #shift ++ sub tmp1, tmp1, #1 ++ .endif ++ bic tmp1, tmp1, #31 ++ cmp tmp1, tmp0 ++ beq 92f ++ .if narrow_case ++ /* In this case, all the data fits in either 1 or 2 cache lines */ ++ pld [tmp1] ++ .else ++91: ++ .if backwards ++ sub tmp0, tmp0, #32 ++ .else ++ add tmp0, tmp0, #32 ++ .endif ++ cmp tmp0, tmp1 ++ pld [tmp0] ++ bne 91b ++ .endif ++92: ++.endm +diff -Nur linux-4.1.13.orig/arch/arm/lib/copy_from_user.S linux-rpi/arch/arm/lib/copy_from_user.S +--- linux-4.1.13.orig/arch/arm/lib/copy_from_user.S 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/arch/arm/lib/copy_from_user.S 2015-11-29 09:42:34.767440995 +0100 +@@ -89,11 +89,13 @@ + + .text + +-ENTRY(__copy_from_user) ++ENTRY(__copy_from_user_std) ++WEAK(__copy_from_user) + + #include "copy_template.S" + + ENDPROC(__copy_from_user) ++ENDPROC(__copy_from_user_std) + + .pushsection .fixup,"ax" + .align 0 +diff -Nur linux-4.1.13.orig/arch/arm/lib/exports_rpi.c linux-rpi/arch/arm/lib/exports_rpi.c +--- linux-4.1.13.orig/arch/arm/lib/exports_rpi.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/lib/exports_rpi.c 2015-11-29 09:42:34.771440730 +0100 +@@ -0,0 +1,37 @@ ++/** ++ * Copyright (c) 2014, Raspberry Pi (Trading) Ltd. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include ++#include ++ ++EXPORT_SYMBOL(memcmp); +diff -Nur linux-4.1.13.orig/arch/arm/lib/Makefile linux-rpi/arch/arm/lib/Makefile +--- linux-4.1.13.orig/arch/arm/lib/Makefile 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/arch/arm/lib/Makefile 2015-11-29 09:42:34.767440995 +0100 +@@ -6,9 +6,8 @@ + + lib-y := backtrace.o changebit.o csumipv6.o csumpartial.o \ + csumpartialcopy.o csumpartialcopyuser.o clearbit.o \ +- delay.o delay-loop.o findbit.o memchr.o memcpy.o \ +- memmove.o memset.o memzero.o setbit.o \ +- strchr.o strrchr.o \ ++ delay.o delay-loop.o findbit.o memchr.o memzero.o \ ++ setbit.o strchr.o strrchr.o \ + testchangebit.o testclearbit.o testsetbit.o \ + ashldi3.o ashrdi3.o lshrdi3.o muldi3.o \ + ucmpdi2.o lib1funcs.o div64.o \ +@@ -18,6 +17,16 @@ + mmu-y := clear_user.o copy_page.o getuser.o putuser.o \ + copy_from_user.o copy_to_user.o + ++# Choose optimised implementations for Raspberry Pi ++ifeq ($(CONFIG_MACH_BCM2708),y) ++ CFLAGS_uaccess_with_memcpy.o += -DCOPY_FROM_USER_THRESHOLD=1600 ++ CFLAGS_uaccess_with_memcpy.o += -DCOPY_TO_USER_THRESHOLD=672 ++ obj-$(CONFIG_MODULES) += exports_rpi.o ++ lib-y += memcpy_rpi.o memmove_rpi.o memset_rpi.o memcmp_rpi.o ++else ++ lib-y += memcpy.o memmove.o memset.o ++endif ++ + # using lib_ here won't override already available weak symbols + obj-$(CONFIG_UACCESS_WITH_MEMCPY) += uaccess_with_memcpy.o + +diff -Nur linux-4.1.13.orig/arch/arm/lib/memcmp_rpi.S linux-rpi/arch/arm/lib/memcmp_rpi.S +--- linux-4.1.13.orig/arch/arm/lib/memcmp_rpi.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/lib/memcmp_rpi.S 2015-11-29 09:42:34.771440730 +0100 +@@ -0,0 +1,285 @@ ++/* ++Copyright (c) 2013, Raspberry Pi Foundation ++Copyright (c) 2013, RISC OS Open Ltd ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions are met: ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ * Neither the name of the copyright holder nor the ++ names of its contributors may be used to endorse or promote products ++ derived from this software without specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY ++DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++*/ ++ ++#include ++#include "arm-mem.h" ++ ++/* Prevent the stack from becoming executable */ ++#if defined(__linux__) && defined(__ELF__) ++.section .note.GNU-stack,"",%progbits ++#endif ++ ++ .text ++ .arch armv6 ++ .object_arch armv4 ++ .arm ++ .altmacro ++ .p2align 2 ++ ++.macro memcmp_process_head unaligned ++ .if unaligned ++ ldr DAT0, [S_1], #4 ++ ldr DAT1, [S_1], #4 ++ ldr DAT2, [S_1], #4 ++ ldr DAT3, [S_1], #4 ++ .else ++ ldmia S_1!, {DAT0, DAT1, DAT2, DAT3} ++ .endif ++ ldmia S_2!, {DAT4, DAT5, DAT6, DAT7} ++.endm ++ ++.macro memcmp_process_tail ++ cmp DAT0, DAT4 ++ cmpeq DAT1, DAT5 ++ cmpeq DAT2, DAT6 ++ cmpeq DAT3, DAT7 ++ bne 200f ++.endm ++ ++.macro memcmp_leading_31bytes ++ movs DAT0, OFF, lsl #31 ++ ldrmib DAT0, [S_1], #1 ++ ldrcsh DAT1, [S_1], #2 ++ ldrmib DAT4, [S_2], #1 ++ ldrcsh DAT5, [S_2], #2 ++ movpl DAT0, #0 ++ movcc DAT1, #0 ++ movpl DAT4, #0 ++ movcc DAT5, #0 ++ submi N, N, #1 ++ subcs N, N, #2 ++ cmp DAT0, DAT4 ++ cmpeq DAT1, DAT5 ++ bne 200f ++ movs DAT0, OFF, lsl #29 ++ ldrmi DAT0, [S_1], #4 ++ ldrcs DAT1, [S_1], #4 ++ ldrcs DAT2, [S_1], #4 ++ ldrmi DAT4, [S_2], #4 ++ ldmcsia S_2!, {DAT5, DAT6} ++ movpl DAT0, #0 ++ movcc DAT1, #0 ++ movcc DAT2, #0 ++ movpl DAT4, #0 ++ movcc DAT5, #0 ++ movcc DAT6, #0 ++ submi N, N, #4 ++ subcs N, N, #8 ++ cmp DAT0, DAT4 ++ cmpeq DAT1, DAT5 ++ cmpeq DAT2, DAT6 ++ bne 200f ++ tst OFF, #16 ++ beq 105f ++ memcmp_process_head 1 ++ sub N, N, #16 ++ memcmp_process_tail ++105: ++.endm ++ ++.macro memcmp_trailing_15bytes unaligned ++ movs N, N, lsl #29 ++ .if unaligned ++ ldrcs DAT0, [S_1], #4 ++ ldrcs DAT1, [S_1], #4 ++ .else ++ ldmcsia S_1!, {DAT0, DAT1} ++ .endif ++ ldrmi DAT2, [S_1], #4 ++ ldmcsia S_2!, {DAT4, DAT5} ++ ldrmi DAT6, [S_2], #4 ++ movcc DAT0, #0 ++ movcc DAT1, #0 ++ movpl DAT2, #0 ++ movcc DAT4, #0 ++ movcc DAT5, #0 ++ movpl DAT6, #0 ++ cmp DAT0, DAT4 ++ cmpeq DAT1, DAT5 ++ cmpeq DAT2, DAT6 ++ bne 200f ++ movs N, N, lsl #2 ++ ldrcsh DAT0, [S_1], #2 ++ ldrmib DAT1, [S_1] ++ ldrcsh DAT4, [S_2], #2 ++ ldrmib DAT5, [S_2] ++ movcc DAT0, #0 ++ movpl DAT1, #0 ++ movcc DAT4, #0 ++ movpl DAT5, #0 ++ cmp DAT0, DAT4 ++ cmpeq DAT1, DAT5 ++ bne 200f ++.endm ++ ++.macro memcmp_long_inner_loop unaligned ++110: ++ memcmp_process_head unaligned ++ pld [S_2, #prefetch_distance*32 + 16] ++ memcmp_process_tail ++ memcmp_process_head unaligned ++ pld [S_1, OFF] ++ memcmp_process_tail ++ subs N, N, #32 ++ bhs 110b ++ /* Just before the final (prefetch_distance+1) 32-byte blocks, ++ * deal with final preloads */ ++ preload_trailing 0, S_1, N, DAT0 ++ preload_trailing 0, S_2, N, DAT0 ++ add N, N, #(prefetch_distance+2)*32 - 16 ++120: ++ memcmp_process_head unaligned ++ memcmp_process_tail ++ subs N, N, #16 ++ bhs 120b ++ /* Trailing words and bytes */ ++ tst N, #15 ++ beq 199f ++ memcmp_trailing_15bytes unaligned ++199: /* Reached end without detecting a difference */ ++ mov a1, #0 ++ setend le ++ pop {DAT1-DAT6, pc} ++.endm ++ ++.macro memcmp_short_inner_loop unaligned ++ subs N, N, #16 /* simplifies inner loop termination */ ++ blo 122f ++120: ++ memcmp_process_head unaligned ++ memcmp_process_tail ++ subs N, N, #16 ++ bhs 120b ++122: /* Trailing words and bytes */ ++ tst N, #15 ++ beq 199f ++ memcmp_trailing_15bytes unaligned ++199: /* Reached end without detecting a difference */ ++ mov a1, #0 ++ setend le ++ pop {DAT1-DAT6, pc} ++.endm ++ ++/* ++ * int memcmp(const void *s1, const void *s2, size_t n); ++ * On entry: ++ * a1 = pointer to buffer 1 ++ * a2 = pointer to buffer 2 ++ * a3 = number of bytes to compare (as unsigned chars) ++ * On exit: ++ * a1 = >0/=0/<0 if s1 >/=/< s2 ++ */ ++ ++.set prefetch_distance, 2 ++ ++ENTRY(memcmp) ++ S_1 .req a1 ++ S_2 .req a2 ++ N .req a3 ++ DAT0 .req a4 ++ DAT1 .req v1 ++ DAT2 .req v2 ++ DAT3 .req v3 ++ DAT4 .req v4 ++ DAT5 .req v5 ++ DAT6 .req v6 ++ DAT7 .req ip ++ OFF .req lr ++ ++ push {DAT1-DAT6, lr} ++ setend be /* lowest-addressed bytes are most significant */ ++ ++ /* To preload ahead as we go, we need at least (prefetch_distance+2) 32-byte blocks */ ++ cmp N, #(prefetch_distance+3)*32 - 1 ++ blo 170f ++ ++ /* Long case */ ++ /* Adjust N so that the decrement instruction can also test for ++ * inner loop termination. We want it to stop when there are ++ * (prefetch_distance+1) complete blocks to go. */ ++ sub N, N, #(prefetch_distance+2)*32 ++ preload_leading_step1 0, DAT0, S_1 ++ preload_leading_step1 0, DAT1, S_2 ++ tst S_2, #31 ++ beq 154f ++ rsb OFF, S_2, #0 /* no need to AND with 15 here */ ++ preload_leading_step2 0, DAT0, S_1, OFF, DAT2 ++ preload_leading_step2 0, DAT1, S_2, OFF, DAT2 ++ memcmp_leading_31bytes ++154: /* Second source now cacheline (32-byte) aligned; we have at ++ * least one prefetch to go. */ ++ /* Prefetch offset is best selected such that it lies in the ++ * first 8 of each 32 bytes - but it's just as easy to aim for ++ * the first one */ ++ and OFF, S_1, #31 ++ rsb OFF, OFF, #32*prefetch_distance ++ tst S_1, #3 ++ bne 140f ++ memcmp_long_inner_loop 0 ++140: memcmp_long_inner_loop 1 ++ ++170: /* Short case */ ++ teq N, #0 ++ beq 199f ++ preload_all 0, 0, 0, S_1, N, DAT0, DAT1 ++ preload_all 0, 0, 0, S_2, N, DAT0, DAT1 ++ tst S_2, #3 ++ beq 174f ++172: subs N, N, #1 ++ blo 199f ++ ldrb DAT0, [S_1], #1 ++ ldrb DAT4, [S_2], #1 ++ cmp DAT0, DAT4 ++ bne 200f ++ tst S_2, #3 ++ bne 172b ++174: /* Second source now 4-byte aligned; we have 0 or more bytes to go */ ++ tst S_1, #3 ++ bne 140f ++ memcmp_short_inner_loop 0 ++140: memcmp_short_inner_loop 1 ++ ++200: /* Difference found: determine sign. */ ++ movhi a1, #1 ++ movlo a1, #-1 ++ setend le ++ pop {DAT1-DAT6, pc} ++ ++ .unreq S_1 ++ .unreq S_2 ++ .unreq N ++ .unreq DAT0 ++ .unreq DAT1 ++ .unreq DAT2 ++ .unreq DAT3 ++ .unreq DAT4 ++ .unreq DAT5 ++ .unreq DAT6 ++ .unreq DAT7 ++ .unreq OFF ++ENDPROC(memcmp) +diff -Nur linux-4.1.13.orig/arch/arm/lib/memcpymove.h linux-rpi/arch/arm/lib/memcpymove.h +--- linux-4.1.13.orig/arch/arm/lib/memcpymove.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/lib/memcpymove.h 2015-11-29 09:42:34.771440730 +0100 +@@ -0,0 +1,506 @@ ++/* ++Copyright (c) 2013, Raspberry Pi Foundation ++Copyright (c) 2013, RISC OS Open Ltd ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions are met: ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ * Neither the name of the copyright holder nor the ++ names of its contributors may be used to endorse or promote products ++ derived from this software without specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY ++DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++*/ ++ ++.macro unaligned_words backwards, align, use_pld, words, r0, r1, r2, r3, r4, r5, r6, r7, r8 ++ .if words == 1 ++ .if backwards ++ mov r1, r0, lsl #32-align*8 ++ ldr r0, [S, #-4]! ++ orr r1, r1, r0, lsr #align*8 ++ str r1, [D, #-4]! ++ .else ++ mov r0, r1, lsr #align*8 ++ ldr r1, [S, #4]! ++ orr r0, r0, r1, lsl #32-align*8 ++ str r0, [D], #4 ++ .endif ++ .elseif words == 2 ++ .if backwards ++ ldr r1, [S, #-4]! ++ mov r2, r0, lsl #32-align*8 ++ ldr r0, [S, #-4]! ++ orr r2, r2, r1, lsr #align*8 ++ mov r1, r1, lsl #32-align*8 ++ orr r1, r1, r0, lsr #align*8 ++ stmdb D!, {r1, r2} ++ .else ++ ldr r1, [S, #4]! ++ mov r0, r2, lsr #align*8 ++ ldr r2, [S, #4]! ++ orr r0, r0, r1, lsl #32-align*8 ++ mov r1, r1, lsr #align*8 ++ orr r1, r1, r2, lsl #32-align*8 ++ stmia D!, {r0, r1} ++ .endif ++ .elseif words == 4 ++ .if backwards ++ ldmdb S!, {r2, r3} ++ mov r4, r0, lsl #32-align*8 ++ ldmdb S!, {r0, r1} ++ orr r4, r4, r3, lsr #align*8 ++ mov r3, r3, lsl #32-align*8 ++ orr r3, r3, r2, lsr #align*8 ++ mov r2, r2, lsl #32-align*8 ++ orr r2, r2, r1, lsr #align*8 ++ mov r1, r1, lsl #32-align*8 ++ orr r1, r1, r0, lsr #align*8 ++ stmdb D!, {r1, r2, r3, r4} ++ .else ++ ldmib S!, {r1, r2} ++ mov r0, r4, lsr #align*8 ++ ldmib S!, {r3, r4} ++ orr r0, r0, r1, lsl #32-align*8 ++ mov r1, r1, lsr #align*8 ++ orr r1, r1, r2, lsl #32-align*8 ++ mov r2, r2, lsr #align*8 ++ orr r2, r2, r3, lsl #32-align*8 ++ mov r3, r3, lsr #align*8 ++ orr r3, r3, r4, lsl #32-align*8 ++ stmia D!, {r0, r1, r2, r3} ++ .endif ++ .elseif words == 8 ++ .if backwards ++ ldmdb S!, {r4, r5, r6, r7} ++ mov r8, r0, lsl #32-align*8 ++ ldmdb S!, {r0, r1, r2, r3} ++ .if use_pld ++ pld [S, OFF] ++ .endif ++ orr r8, r8, r7, lsr #align*8 ++ mov r7, r7, lsl #32-align*8 ++ orr r7, r7, r6, lsr #align*8 ++ mov r6, r6, lsl #32-align*8 ++ orr r6, r6, r5, lsr #align*8 ++ mov r5, r5, lsl #32-align*8 ++ orr r5, r5, r4, lsr #align*8 ++ mov r4, r4, lsl #32-align*8 ++ orr r4, r4, r3, lsr #align*8 ++ mov r3, r3, lsl #32-align*8 ++ orr r3, r3, r2, lsr #align*8 ++ mov r2, r2, lsl #32-align*8 ++ orr r2, r2, r1, lsr #align*8 ++ mov r1, r1, lsl #32-align*8 ++ orr r1, r1, r0, lsr #align*8 ++ stmdb D!, {r5, r6, r7, r8} ++ stmdb D!, {r1, r2, r3, r4} ++ .else ++ ldmib S!, {r1, r2, r3, r4} ++ mov r0, r8, lsr #align*8 ++ ldmib S!, {r5, r6, r7, r8} ++ .if use_pld ++ pld [S, OFF] ++ .endif ++ orr r0, r0, r1, lsl #32-align*8 ++ mov r1, r1, lsr #align*8 ++ orr r1, r1, r2, lsl #32-align*8 ++ mov r2, r2, lsr #align*8 ++ orr r2, r2, r3, lsl #32-align*8 ++ mov r3, r3, lsr #align*8 ++ orr r3, r3, r4, lsl #32-align*8 ++ mov r4, r4, lsr #align*8 ++ orr r4, r4, r5, lsl #32-align*8 ++ mov r5, r5, lsr #align*8 ++ orr r5, r5, r6, lsl #32-align*8 ++ mov r6, r6, lsr #align*8 ++ orr r6, r6, r7, lsl #32-align*8 ++ mov r7, r7, lsr #align*8 ++ orr r7, r7, r8, lsl #32-align*8 ++ stmia D!, {r0, r1, r2, r3} ++ stmia D!, {r4, r5, r6, r7} ++ .endif ++ .endif ++.endm ++ ++.macro memcpy_leading_15bytes backwards, align ++ movs DAT1, DAT2, lsl #31 ++ sub N, N, DAT2 ++ .if backwards ++ ldrmib DAT0, [S, #-1]! ++ ldrcsh DAT1, [S, #-2]! ++ strmib DAT0, [D, #-1]! ++ strcsh DAT1, [D, #-2]! ++ .else ++ ldrmib DAT0, [S], #1 ++ ldrcsh DAT1, [S], #2 ++ strmib DAT0, [D], #1 ++ strcsh DAT1, [D], #2 ++ .endif ++ movs DAT1, DAT2, lsl #29 ++ .if backwards ++ ldrmi DAT0, [S, #-4]! ++ .if align == 0 ++ ldmcsdb S!, {DAT1, DAT2} ++ .else ++ ldrcs DAT2, [S, #-4]! ++ ldrcs DAT1, [S, #-4]! ++ .endif ++ strmi DAT0, [D, #-4]! ++ stmcsdb D!, {DAT1, DAT2} ++ .else ++ ldrmi DAT0, [S], #4 ++ .if align == 0 ++ ldmcsia S!, {DAT1, DAT2} ++ .else ++ ldrcs DAT1, [S], #4 ++ ldrcs DAT2, [S], #4 ++ .endif ++ strmi DAT0, [D], #4 ++ stmcsia D!, {DAT1, DAT2} ++ .endif ++.endm ++ ++.macro memcpy_trailing_15bytes backwards, align ++ movs N, N, lsl #29 ++ .if backwards ++ .if align == 0 ++ ldmcsdb S!, {DAT0, DAT1} ++ .else ++ ldrcs DAT1, [S, #-4]! ++ ldrcs DAT0, [S, #-4]! ++ .endif ++ ldrmi DAT2, [S, #-4]! ++ stmcsdb D!, {DAT0, DAT1} ++ strmi DAT2, [D, #-4]! ++ .else ++ .if align == 0 ++ ldmcsia S!, {DAT0, DAT1} ++ .else ++ ldrcs DAT0, [S], #4 ++ ldrcs DAT1, [S], #4 ++ .endif ++ ldrmi DAT2, [S], #4 ++ stmcsia D!, {DAT0, DAT1} ++ strmi DAT2, [D], #4 ++ .endif ++ movs N, N, lsl #2 ++ .if backwards ++ ldrcsh DAT0, [S, #-2]! ++ ldrmib DAT1, [S, #-1] ++ strcsh DAT0, [D, #-2]! ++ strmib DAT1, [D, #-1] ++ .else ++ ldrcsh DAT0, [S], #2 ++ ldrmib DAT1, [S] ++ strcsh DAT0, [D], #2 ++ strmib DAT1, [D] ++ .endif ++.endm ++ ++.macro memcpy_long_inner_loop backwards, align ++ .if align != 0 ++ .if backwards ++ ldr DAT0, [S, #-align]! ++ .else ++ ldr LAST, [S, #-align]! ++ .endif ++ .endif ++110: ++ .if align == 0 ++ .if backwards ++ ldmdb S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST} ++ pld [S, OFF] ++ stmdb D!, {DAT4, DAT5, DAT6, LAST} ++ stmdb D!, {DAT0, DAT1, DAT2, DAT3} ++ .else ++ ldmia S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST} ++ pld [S, OFF] ++ stmia D!, {DAT0, DAT1, DAT2, DAT3} ++ stmia D!, {DAT4, DAT5, DAT6, LAST} ++ .endif ++ .else ++ unaligned_words backwards, align, 1, 8, DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, DAT7, LAST ++ .endif ++ subs N, N, #32 ++ bhs 110b ++ /* Just before the final (prefetch_distance+1) 32-byte blocks, deal with final preloads */ ++ preload_trailing backwards, S, N, OFF ++ add N, N, #(prefetch_distance+2)*32 - 32 ++120: ++ .if align == 0 ++ .if backwards ++ ldmdb S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST} ++ stmdb D!, {DAT4, DAT5, DAT6, LAST} ++ stmdb D!, {DAT0, DAT1, DAT2, DAT3} ++ .else ++ ldmia S!, {DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, LAST} ++ stmia D!, {DAT0, DAT1, DAT2, DAT3} ++ stmia D!, {DAT4, DAT5, DAT6, LAST} ++ .endif ++ .else ++ unaligned_words backwards, align, 0, 8, DAT0, DAT1, DAT2, DAT3, DAT4, DAT5, DAT6, DAT7, LAST ++ .endif ++ subs N, N, #32 ++ bhs 120b ++ tst N, #16 ++ .if align == 0 ++ .if backwards ++ ldmnedb S!, {DAT0, DAT1, DAT2, LAST} ++ stmnedb D!, {DAT0, DAT1, DAT2, LAST} ++ .else ++ ldmneia S!, {DAT0, DAT1, DAT2, LAST} ++ stmneia D!, {DAT0, DAT1, DAT2, LAST} ++ .endif ++ .else ++ beq 130f ++ unaligned_words backwards, align, 0, 4, DAT0, DAT1, DAT2, DAT3, LAST ++130: ++ .endif ++ /* Trailing words and bytes */ ++ tst N, #15 ++ beq 199f ++ .if align != 0 ++ add S, S, #align ++ .endif ++ memcpy_trailing_15bytes backwards, align ++199: ++ pop {DAT3, DAT4, DAT5, DAT6, DAT7} ++ pop {D, DAT1, DAT2, pc} ++.endm ++ ++.macro memcpy_medium_inner_loop backwards, align ++120: ++ .if backwards ++ .if align == 0 ++ ldmdb S!, {DAT0, DAT1, DAT2, LAST} ++ .else ++ ldr LAST, [S, #-4]! ++ ldr DAT2, [S, #-4]! ++ ldr DAT1, [S, #-4]! ++ ldr DAT0, [S, #-4]! ++ .endif ++ stmdb D!, {DAT0, DAT1, DAT2, LAST} ++ .else ++ .if align == 0 ++ ldmia S!, {DAT0, DAT1, DAT2, LAST} ++ .else ++ ldr DAT0, [S], #4 ++ ldr DAT1, [S], #4 ++ ldr DAT2, [S], #4 ++ ldr LAST, [S], #4 ++ .endif ++ stmia D!, {DAT0, DAT1, DAT2, LAST} ++ .endif ++ subs N, N, #16 ++ bhs 120b ++ /* Trailing words and bytes */ ++ tst N, #15 ++ beq 199f ++ memcpy_trailing_15bytes backwards, align ++199: ++ pop {D, DAT1, DAT2, pc} ++.endm ++ ++.macro memcpy_short_inner_loop backwards, align ++ tst N, #16 ++ .if backwards ++ .if align == 0 ++ ldmnedb S!, {DAT0, DAT1, DAT2, LAST} ++ .else ++ ldrne LAST, [S, #-4]! ++ ldrne DAT2, [S, #-4]! ++ ldrne DAT1, [S, #-4]! ++ ldrne DAT0, [S, #-4]! ++ .endif ++ stmnedb D!, {DAT0, DAT1, DAT2, LAST} ++ .else ++ .if align == 0 ++ ldmneia S!, {DAT0, DAT1, DAT2, LAST} ++ .else ++ ldrne DAT0, [S], #4 ++ ldrne DAT1, [S], #4 ++ ldrne DAT2, [S], #4 ++ ldrne LAST, [S], #4 ++ .endif ++ stmneia D!, {DAT0, DAT1, DAT2, LAST} ++ .endif ++ memcpy_trailing_15bytes backwards, align ++199: ++ pop {D, DAT1, DAT2, pc} ++.endm ++ ++.macro memcpy backwards ++ D .req a1 ++ S .req a2 ++ N .req a3 ++ DAT0 .req a4 ++ DAT1 .req v1 ++ DAT2 .req v2 ++ DAT3 .req v3 ++ DAT4 .req v4 ++ DAT5 .req v5 ++ DAT6 .req v6 ++ DAT7 .req sl ++ LAST .req ip ++ OFF .req lr ++ ++ .cfi_startproc ++ ++ push {D, DAT1, DAT2, lr} ++ ++ .cfi_def_cfa_offset 16 ++ .cfi_rel_offset D, 0 ++ .cfi_undefined S ++ .cfi_undefined N ++ .cfi_undefined DAT0 ++ .cfi_rel_offset DAT1, 4 ++ .cfi_rel_offset DAT2, 8 ++ .cfi_undefined LAST ++ .cfi_rel_offset lr, 12 ++ ++ .if backwards ++ add D, D, N ++ add S, S, N ++ .endif ++ ++ /* See if we're guaranteed to have at least one 16-byte aligned 16-byte write */ ++ cmp N, #31 ++ blo 170f ++ /* To preload ahead as we go, we need at least (prefetch_distance+2) 32-byte blocks */ ++ cmp N, #(prefetch_distance+3)*32 - 1 ++ blo 160f ++ ++ /* Long case */ ++ push {DAT3, DAT4, DAT5, DAT6, DAT7} ++ ++ .cfi_def_cfa_offset 36 ++ .cfi_rel_offset D, 20 ++ .cfi_rel_offset DAT1, 24 ++ .cfi_rel_offset DAT2, 28 ++ .cfi_rel_offset DAT3, 0 ++ .cfi_rel_offset DAT4, 4 ++ .cfi_rel_offset DAT5, 8 ++ .cfi_rel_offset DAT6, 12 ++ .cfi_rel_offset DAT7, 16 ++ .cfi_rel_offset lr, 32 ++ ++ /* Adjust N so that the decrement instruction can also test for ++ * inner loop termination. We want it to stop when there are ++ * (prefetch_distance+1) complete blocks to go. */ ++ sub N, N, #(prefetch_distance+2)*32 ++ preload_leading_step1 backwards, DAT0, S ++ .if backwards ++ /* Bug in GAS: it accepts, but mis-assembles the instruction ++ * ands DAT2, D, #60, 2 ++ * which sets DAT2 to the number of leading bytes until destination is aligned and also clears C (sets borrow) ++ */ ++ .word 0xE210513C ++ beq 154f ++ .else ++ ands DAT2, D, #15 ++ beq 154f ++ rsb DAT2, DAT2, #16 /* number of leading bytes until destination aligned */ ++ .endif ++ preload_leading_step2 backwards, DAT0, S, DAT2, OFF ++ memcpy_leading_15bytes backwards, 1 ++154: /* Destination now 16-byte aligned; we have at least one prefetch as well as at least one 16-byte output block */ ++ /* Prefetch offset is best selected such that it lies in the first 8 of each 32 bytes - but it's just as easy to aim for the first one */ ++ .if backwards ++ rsb OFF, S, #3 ++ and OFF, OFF, #28 ++ sub OFF, OFF, #32*(prefetch_distance+1) ++ .else ++ and OFF, S, #28 ++ rsb OFF, OFF, #32*prefetch_distance ++ .endif ++ movs DAT0, S, lsl #31 ++ bhi 157f ++ bcs 156f ++ bmi 155f ++ memcpy_long_inner_loop backwards, 0 ++155: memcpy_long_inner_loop backwards, 1 ++156: memcpy_long_inner_loop backwards, 2 ++157: memcpy_long_inner_loop backwards, 3 ++ ++ .cfi_def_cfa_offset 16 ++ .cfi_rel_offset D, 0 ++ .cfi_rel_offset DAT1, 4 ++ .cfi_rel_offset DAT2, 8 ++ .cfi_same_value DAT3 ++ .cfi_same_value DAT4 ++ .cfi_same_value DAT5 ++ .cfi_same_value DAT6 ++ .cfi_same_value DAT7 ++ .cfi_rel_offset lr, 12 ++ ++160: /* Medium case */ ++ preload_all backwards, 0, 0, S, N, DAT2, OFF ++ sub N, N, #16 /* simplifies inner loop termination */ ++ .if backwards ++ ands DAT2, D, #15 ++ beq 164f ++ .else ++ ands DAT2, D, #15 ++ beq 164f ++ rsb DAT2, DAT2, #16 ++ .endif ++ memcpy_leading_15bytes backwards, align ++164: /* Destination now 16-byte aligned; we have at least one 16-byte output block */ ++ tst S, #3 ++ bne 140f ++ memcpy_medium_inner_loop backwards, 0 ++140: memcpy_medium_inner_loop backwards, 1 ++ ++170: /* Short case, less than 31 bytes, so no guarantee of at least one 16-byte block */ ++ teq N, #0 ++ beq 199f ++ preload_all backwards, 1, 0, S, N, DAT2, LAST ++ tst D, #3 ++ beq 174f ++172: subs N, N, #1 ++ blo 199f ++ .if backwards ++ ldrb DAT0, [S, #-1]! ++ strb DAT0, [D, #-1]! ++ .else ++ ldrb DAT0, [S], #1 ++ strb DAT0, [D], #1 ++ .endif ++ tst D, #3 ++ bne 172b ++174: /* Destination now 4-byte aligned; we have 0 or more output bytes to go */ ++ tst S, #3 ++ bne 140f ++ memcpy_short_inner_loop backwards, 0 ++140: memcpy_short_inner_loop backwards, 1 ++ ++ .cfi_endproc ++ ++ .unreq D ++ .unreq S ++ .unreq N ++ .unreq DAT0 ++ .unreq DAT1 ++ .unreq DAT2 ++ .unreq DAT3 ++ .unreq DAT4 ++ .unreq DAT5 ++ .unreq DAT6 ++ .unreq DAT7 ++ .unreq LAST ++ .unreq OFF ++.endm +diff -Nur linux-4.1.13.orig/arch/arm/lib/memcpy_rpi.S linux-rpi/arch/arm/lib/memcpy_rpi.S +--- linux-4.1.13.orig/arch/arm/lib/memcpy_rpi.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/lib/memcpy_rpi.S 2015-11-29 09:42:34.771440730 +0100 +@@ -0,0 +1,59 @@ ++/* ++Copyright (c) 2013, Raspberry Pi Foundation ++Copyright (c) 2013, RISC OS Open Ltd ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions are met: ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ * Neither the name of the copyright holder nor the ++ names of its contributors may be used to endorse or promote products ++ derived from this software without specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY ++DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++*/ ++ ++#include ++#include "arm-mem.h" ++#include "memcpymove.h" ++ ++/* Prevent the stack from becoming executable */ ++#if defined(__linux__) && defined(__ELF__) ++.section .note.GNU-stack,"",%progbits ++#endif ++ ++ .text ++ .arch armv6 ++ .object_arch armv4 ++ .arm ++ .altmacro ++ .p2align 2 ++ ++/* ++ * void *memcpy(void * restrict s1, const void * restrict s2, size_t n); ++ * On entry: ++ * a1 = pointer to destination ++ * a2 = pointer to source ++ * a3 = number of bytes to copy ++ * On exit: ++ * a1 preserved ++ */ ++ ++.set prefetch_distance, 3 ++ ++ENTRY(memcpy) ++ memcpy 0 ++ENDPROC(memcpy) +diff -Nur linux-4.1.13.orig/arch/arm/lib/memmove_rpi.S linux-rpi/arch/arm/lib/memmove_rpi.S +--- linux-4.1.13.orig/arch/arm/lib/memmove_rpi.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/lib/memmove_rpi.S 2015-11-29 09:42:34.771440730 +0100 +@@ -0,0 +1,61 @@ ++/* ++Copyright (c) 2013, Raspberry Pi Foundation ++Copyright (c) 2013, RISC OS Open Ltd ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions are met: ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ * Neither the name of the copyright holder nor the ++ names of its contributors may be used to endorse or promote products ++ derived from this software without specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY ++DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++*/ ++ ++#include ++#include "arm-mem.h" ++#include "memcpymove.h" ++ ++/* Prevent the stack from becoming executable */ ++#if defined(__linux__) && defined(__ELF__) ++.section .note.GNU-stack,"",%progbits ++#endif ++ ++ .text ++ .arch armv6 ++ .object_arch armv4 ++ .arm ++ .altmacro ++ .p2align 2 ++ ++/* ++ * void *memmove(void *s1, const void *s2, size_t n); ++ * On entry: ++ * a1 = pointer to destination ++ * a2 = pointer to source ++ * a3 = number of bytes to copy ++ * On exit: ++ * a1 preserved ++ */ ++ ++.set prefetch_distance, 3 ++ ++ENTRY(memmove) ++ cmp a2, a1 ++ bpl memcpy /* pl works even over -1 - 0 and 0x7fffffff - 0x80000000 boundaries */ ++ memcpy 1 ++ENDPROC(memmove) +diff -Nur linux-4.1.13.orig/arch/arm/lib/memset_rpi.S linux-rpi/arch/arm/lib/memset_rpi.S +--- linux-4.1.13.orig/arch/arm/lib/memset_rpi.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/lib/memset_rpi.S 2015-11-29 09:42:34.771440730 +0100 +@@ -0,0 +1,121 @@ ++/* ++Copyright (c) 2013, Raspberry Pi Foundation ++Copyright (c) 2013, RISC OS Open Ltd ++All rights reserved. ++ ++Redistribution and use in source and binary forms, with or without ++modification, are permitted provided that the following conditions are met: ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in the ++ documentation and/or other materials provided with the distribution. ++ * Neither the name of the copyright holder nor the ++ names of its contributors may be used to endorse or promote products ++ derived from this software without specific prior written permission. ++ ++THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY ++DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++*/ ++ ++#include ++#include "arm-mem.h" ++ ++/* Prevent the stack from becoming executable */ ++#if defined(__linux__) && defined(__ELF__) ++.section .note.GNU-stack,"",%progbits ++#endif ++ ++ .text ++ .arch armv6 ++ .object_arch armv4 ++ .arm ++ .altmacro ++ .p2align 2 ++ ++/* ++ * void *memset(void *s, int c, size_t n); ++ * On entry: ++ * a1 = pointer to buffer to fill ++ * a2 = byte pattern to fill with (caller-narrowed) ++ * a3 = number of bytes to fill ++ * On exit: ++ * a1 preserved ++ */ ++ENTRY(memset) ++ S .req a1 ++ DAT0 .req a2 ++ N .req a3 ++ DAT1 .req a4 ++ DAT2 .req ip ++ DAT3 .req lr ++ ++ orr DAT0, DAT0, lsl #8 ++ push {S, lr} ++ orr DAT0, DAT0, lsl #16 ++ mov DAT1, DAT0 ++ ++ /* See if we're guaranteed to have at least one 16-byte aligned 16-byte write */ ++ cmp N, #31 ++ blo 170f ++ ++161: sub N, N, #16 /* simplifies inner loop termination */ ++ /* Leading words and bytes */ ++ tst S, #15 ++ beq 164f ++ rsb DAT3, S, #0 /* bits 0-3 = number of leading bytes until aligned */ ++ movs DAT2, DAT3, lsl #31 ++ submi N, N, #1 ++ strmib DAT0, [S], #1 ++ subcs N, N, #2 ++ strcsh DAT0, [S], #2 ++ movs DAT2, DAT3, lsl #29 ++ submi N, N, #4 ++ strmi DAT0, [S], #4 ++ subcs N, N, #8 ++ stmcsia S!, {DAT0, DAT1} ++164: /* Delayed set up of DAT2 and DAT3 so we could use them as scratch registers above */ ++ mov DAT2, DAT0 ++ mov DAT3, DAT0 ++ /* Now the inner loop of 16-byte stores */ ++165: stmia S!, {DAT0, DAT1, DAT2, DAT3} ++ subs N, N, #16 ++ bhs 165b ++166: /* Trailing words and bytes */ ++ movs N, N, lsl #29 ++ stmcsia S!, {DAT0, DAT1} ++ strmi DAT0, [S], #4 ++ movs N, N, lsl #2 ++ strcsh DAT0, [S], #2 ++ strmib DAT0, [S] ++199: pop {S, pc} ++ ++170: /* Short case */ ++ mov DAT2, DAT0 ++ mov DAT3, DAT0 ++ tst S, #3 ++ beq 174f ++172: subs N, N, #1 ++ blo 199b ++ strb DAT0, [S], #1 ++ tst S, #3 ++ bne 172b ++174: tst N, #16 ++ stmneia S!, {DAT0, DAT1, DAT2, DAT3} ++ b 166b ++ ++ .unreq S ++ .unreq DAT0 ++ .unreq N ++ .unreq DAT1 ++ .unreq DAT2 ++ .unreq DAT3 ++ENDPROC(memset) +diff -Nur linux-4.1.13.orig/arch/arm/lib/uaccess_with_memcpy.c linux-rpi/arch/arm/lib/uaccess_with_memcpy.c +--- linux-4.1.13.orig/arch/arm/lib/uaccess_with_memcpy.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/arch/arm/lib/uaccess_with_memcpy.c 2015-11-29 09:42:34.771440730 +0100 +@@ -22,6 +22,14 @@ + #include + #include + ++#ifndef COPY_FROM_USER_THRESHOLD ++#define COPY_FROM_USER_THRESHOLD 64 ++#endif ++ ++#ifndef COPY_TO_USER_THRESHOLD ++#define COPY_TO_USER_THRESHOLD 64 ++#endif ++ + static int + pin_page_for_write(const void __user *_addr, pte_t **ptep, spinlock_t **ptlp) + { +@@ -85,7 +93,44 @@ + return 1; + } + +-static unsigned long noinline ++static int ++pin_page_for_read(const void __user *_addr, pte_t **ptep, spinlock_t **ptlp) ++{ ++ unsigned long addr = (unsigned long)_addr; ++ pgd_t *pgd; ++ pmd_t *pmd; ++ pte_t *pte; ++ pud_t *pud; ++ spinlock_t *ptl; ++ ++ pgd = pgd_offset(current->mm, addr); ++ if (unlikely(pgd_none(*pgd) || pgd_bad(*pgd))) ++ { ++ return 0; ++ } ++ pud = pud_offset(pgd, addr); ++ if (unlikely(pud_none(*pud) || pud_bad(*pud))) ++ { ++ return 0; ++ } ++ ++ pmd = pmd_offset(pud, addr); ++ if (unlikely(pmd_none(*pmd) || pmd_bad(*pmd))) ++ return 0; ++ ++ pte = pte_offset_map_lock(current->mm, pmd, addr, &ptl); ++ if (unlikely(!pte_present(*pte) || !pte_young(*pte))) { ++ pte_unmap_unlock(pte, ptl); ++ return 0; ++ } ++ ++ *ptep = pte; ++ *ptlp = ptl; ++ ++ return 1; ++} ++ ++unsigned long noinline + __copy_to_user_memcpy(void __user *to, const void *from, unsigned long n) + { + int atomic; +@@ -135,6 +180,54 @@ + return n; + } + ++unsigned long noinline ++__copy_from_user_memcpy(void *to, const void __user *from, unsigned long n) ++{ ++ int atomic; ++ ++ if (unlikely(segment_eq(get_fs(), KERNEL_DS))) { ++ memcpy(to, (const void *)from, n); ++ return 0; ++ } ++ ++ /* the mmap semaphore is taken only if not in an atomic context */ ++ atomic = in_atomic(); ++ ++ if (!atomic) ++ down_read(¤t->mm->mmap_sem); ++ while (n) { ++ pte_t *pte; ++ spinlock_t *ptl; ++ int tocopy; ++ ++ while (!pin_page_for_read(from, &pte, &ptl)) { ++ char temp; ++ if (!atomic) ++ up_read(¤t->mm->mmap_sem); ++ if (__get_user(temp, (char __user *)from)) ++ goto out; ++ if (!atomic) ++ down_read(¤t->mm->mmap_sem); ++ } ++ ++ tocopy = (~(unsigned long)from & ~PAGE_MASK) + 1; ++ if (tocopy > n) ++ tocopy = n; ++ ++ memcpy(to, (const void *)from, tocopy); ++ to += tocopy; ++ from += tocopy; ++ n -= tocopy; ++ ++ pte_unmap_unlock(pte, ptl); ++ } ++ if (!atomic) ++ up_read(¤t->mm->mmap_sem); ++ ++out: ++ return n; ++} ++ + unsigned long + __copy_to_user(void __user *to, const void *from, unsigned long n) + { +@@ -145,10 +238,25 @@ + * With frame pointer disabled, tail call optimization kicks in + * as well making this test almost invisible. + */ +- if (n < 64) ++ if (n < COPY_TO_USER_THRESHOLD) + return __copy_to_user_std(to, from, n); + return __copy_to_user_memcpy(to, from, n); + } ++ ++unsigned long ++__copy_from_user(void *to, const void __user *from, unsigned long n) ++{ ++ /* ++ * This test is stubbed out of the main function above to keep ++ * the overhead for small copies low by avoiding a large ++ * register dump on the stack just to reload them right away. ++ * With frame pointer disabled, tail call optimization kicks in ++ * as well making this test almost invisible. ++ */ ++ if (n < COPY_FROM_USER_THRESHOLD) ++ return __copy_from_user_std(to, from, n); ++ return __copy_from_user_memcpy(to, from, n); ++} + + static unsigned long noinline + __clear_user_memset(void __user *addr, unsigned long n) +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm/board_bcm2835.c linux-rpi/arch/arm/mach-bcm/board_bcm2835.c +--- linux-4.1.13.orig/arch/arm/mach-bcm/board_bcm2835.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm/board_bcm2835.c 2015-11-29 09:42:34.787439667 +0100 +@@ -18,6 +18,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -107,6 +108,9 @@ + + static void __init bcm2835_init(void) + { ++ struct device_node *np = of_find_node_by_path("/system"); ++ u32 val; ++ u64 val64; + int ret; + + bcm2835_setup_restart(); +@@ -121,6 +125,11 @@ + pr_err("of_platform_populate failed: %d\n", ret); + BUG(); + } ++ ++ if (!of_property_read_u32(np, "linux,revision", &val)) ++ system_rev = val; ++ if (!of_property_read_u64(np, "linux,serial", &val64)) ++ system_serial_low = val64; + } + + static const char * const bcm2835_compat[] = { +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm/Kconfig linux-rpi/arch/arm/mach-bcm/Kconfig +--- linux-4.1.13.orig/arch/arm/mach-bcm/Kconfig 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm/Kconfig 2015-11-29 09:42:34.787439667 +0100 +@@ -114,6 +114,7 @@ + select ARM_ERRATA_411920 + select ARM_TIMER_SP804 + select CLKSRC_OF ++ select FIQ + select PINCTRL + select PINCTRL_BCM2835 + help +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/armctrl.c linux-rpi/arch/arm/mach-bcm2708/armctrl.c +--- linux-4.1.13.orig/arch/arm/mach-bcm2708/armctrl.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2708/armctrl.c 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,315 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/armctrl.c ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include "armctrl.h" ++ ++/* For support of kernels >= 3.0 assume only one VIC for now*/ ++static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = { ++ INTERRUPT_VC_JPEG, ++ INTERRUPT_VC_USB, ++ INTERRUPT_VC_3D, ++ INTERRUPT_VC_DMA2, ++ INTERRUPT_VC_DMA3, ++ INTERRUPT_VC_I2C, ++ INTERRUPT_VC_SPI, ++ INTERRUPT_VC_I2SPCM, ++ INTERRUPT_VC_SDIO, ++ INTERRUPT_VC_UART, ++ INTERRUPT_VC_ARASANSDIO ++}; ++ ++static void armctrl_mask_irq(struct irq_data *d) ++{ ++ static const unsigned int disables[4] = { ++ ARM_IRQ_DIBL1, ++ ARM_IRQ_DIBL2, ++ ARM_IRQ_DIBL3, ++ 0 ++ }; ++ ++ if (d->irq >= FIQ_START) { ++ writel(0, __io_address(ARM_IRQ_FAST)); ++ } else { ++ unsigned int data = (unsigned int)irq_get_chip_data(d->irq); ++ writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3])); ++ } ++} ++ ++static void armctrl_unmask_irq(struct irq_data *d) ++{ ++ static const unsigned int enables[4] = { ++ ARM_IRQ_ENBL1, ++ ARM_IRQ_ENBL2, ++ ARM_IRQ_ENBL3, ++ 0 ++ }; ++ ++ if (d->irq >= FIQ_START) { ++ unsigned int data = ++ (unsigned int)irq_get_chip_data(d->irq) - FIQ_START; ++ writel(0x80 | data, __io_address(ARM_IRQ_FAST)); ++ } else { ++ unsigned int data = (unsigned int)irq_get_chip_data(d->irq); ++ writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3])); ++ } ++} ++ ++#ifdef CONFIG_OF ++ ++#define NR_IRQS_BANK0 21 ++#define NR_BANKS 3 ++#define IRQS_PER_BANK 32 ++ ++/* from drivers/irqchip/irq-bcm2835.c */ ++static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr, ++ const u32 *intspec, unsigned int intsize, ++ unsigned long *out_hwirq, unsigned int *out_type) ++{ ++ if (WARN_ON(intsize != 2)) ++ return -EINVAL; ++ ++ if (WARN_ON(intspec[0] >= NR_BANKS)) ++ return -EINVAL; ++ ++ if (WARN_ON(intspec[1] >= IRQS_PER_BANK)) ++ return -EINVAL; ++ ++ if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0)) ++ return -EINVAL; ++ ++ if (intspec[0] == 0) ++ *out_hwirq = ARM_IRQ0_BASE + intspec[1]; ++ else if (intspec[0] == 1) ++ *out_hwirq = ARM_IRQ1_BASE + intspec[1]; ++ else ++ *out_hwirq = ARM_IRQ2_BASE + intspec[1]; ++ ++ /* reverse remap_irqs[] */ ++ switch (*out_hwirq) { ++ case INTERRUPT_VC_JPEG: ++ *out_hwirq = INTERRUPT_JPEG; ++ break; ++ case INTERRUPT_VC_USB: ++ *out_hwirq = INTERRUPT_USB; ++ break; ++ case INTERRUPT_VC_3D: ++ *out_hwirq = INTERRUPT_3D; ++ break; ++ case INTERRUPT_VC_DMA2: ++ *out_hwirq = INTERRUPT_DMA2; ++ break; ++ case INTERRUPT_VC_DMA3: ++ *out_hwirq = INTERRUPT_DMA3; ++ break; ++ case INTERRUPT_VC_I2C: ++ *out_hwirq = INTERRUPT_I2C; ++ break; ++ case INTERRUPT_VC_SPI: ++ *out_hwirq = INTERRUPT_SPI; ++ break; ++ case INTERRUPT_VC_I2SPCM: ++ *out_hwirq = INTERRUPT_I2SPCM; ++ break; ++ case INTERRUPT_VC_SDIO: ++ *out_hwirq = INTERRUPT_SDIO; ++ break; ++ case INTERRUPT_VC_UART: ++ *out_hwirq = INTERRUPT_UART; ++ break; ++ case INTERRUPT_VC_ARASANSDIO: ++ *out_hwirq = INTERRUPT_ARASANSDIO; ++ break; ++ } ++ ++ *out_type = IRQ_TYPE_NONE; ++ return 0; ++} ++ ++static struct irq_domain_ops armctrl_ops = { ++ .xlate = armctrl_xlate ++}; ++ ++void __init armctrl_dt_init(void) ++{ ++ struct device_node *np; ++ struct irq_domain *domain; ++ ++ np = of_find_compatible_node(NULL, NULL, "brcm,bcm2708-armctrl-ic"); ++ if (!np) ++ return; ++ ++ domain = irq_domain_add_legacy(np, BCM2708_ALLOC_IRQS, ++ IRQ_ARMCTRL_START, 0, ++ &armctrl_ops, NULL); ++ WARN_ON(!domain); ++} ++#else ++void __init armctrl_dt_init(void) { } ++#endif /* CONFIG_OF */ ++ ++#if defined(CONFIG_PM) ++ ++/* for kernels 3.xx use the new syscore_ops apis but for older kernels use the sys dev class */ ++ ++/* Static defines ++ * struct armctrl_device - VIC PM device (< 3.xx) ++ * @sysdev: The system device which is registered. (< 3.xx) ++ * @irq: The IRQ number for the base of the VIC. ++ * @base: The register base for the VIC. ++ * @resume_sources: A bitmask of interrupts for resume. ++ * @resume_irqs: The IRQs enabled for resume. ++ * @int_select: Save for VIC_INT_SELECT. ++ * @int_enable: Save for VIC_INT_ENABLE. ++ * @soft_int: Save for VIC_INT_SOFT. ++ * @protect: Save for VIC_PROTECT. ++ */ ++struct armctrl_info { ++ void __iomem *base; ++ int irq; ++ u32 resume_sources; ++ u32 resume_irqs; ++ u32 int_select; ++ u32 int_enable; ++ u32 soft_int; ++ u32 protect; ++} armctrl; ++ ++static int armctrl_suspend(void) ++{ ++ return 0; ++} ++ ++static void armctrl_resume(void) ++{ ++ return; ++} ++ ++/** ++ * armctrl_pm_register - Register a VIC for later power management control ++ * @base: The base address of the VIC. ++ * @irq: The base IRQ for the VIC. ++ * @resume_sources: bitmask of interrupts allowed for resume sources. ++ * ++ * For older kernels (< 3.xx) do - ++ * Register the VIC with the system device tree so that it can be notified ++ * of suspend and resume requests and ensure that the correct actions are ++ * taken to re-instate the settings on resume. ++ */ ++static void __init armctrl_pm_register(void __iomem * base, unsigned int irq, ++ u32 resume_sources) ++{ ++ armctrl.base = base; ++ armctrl.resume_sources = resume_sources; ++ armctrl.irq = irq; ++} ++ ++static int armctrl_set_wake(struct irq_data *d, unsigned int on) ++{ ++ unsigned int off = d->irq & 31; ++ u32 bit = 1 << off; ++ ++ if (!(bit & armctrl.resume_sources)) ++ return -EINVAL; ++ ++ if (on) ++ armctrl.resume_irqs |= bit; ++ else ++ armctrl.resume_irqs &= ~bit; ++ ++ return 0; ++} ++ ++#else ++static inline void armctrl_pm_register(void __iomem * base, unsigned int irq, ++ u32 arg1) ++{ ++} ++ ++#define armctrl_suspend NULL ++#define armctrl_resume NULL ++#define armctrl_set_wake NULL ++#endif /* CONFIG_PM */ ++ ++static struct syscore_ops armctrl_syscore_ops = { ++ .suspend = armctrl_suspend, ++ .resume = armctrl_resume, ++}; ++ ++/** ++ * armctrl_syscore_init - initicall to register VIC pm functions ++ * ++ * This is called via late_initcall() to register ++ * the resources for the VICs due to the early ++ * nature of the VIC's registration. ++*/ ++static int __init armctrl_syscore_init(void) ++{ ++ register_syscore_ops(&armctrl_syscore_ops); ++ return 0; ++} ++ ++late_initcall(armctrl_syscore_init); ++ ++static struct irq_chip armctrl_chip = { ++ .name = "ARMCTRL", ++ .irq_ack = NULL, ++ .irq_mask = armctrl_mask_irq, ++ .irq_unmask = armctrl_unmask_irq, ++ .irq_set_wake = armctrl_set_wake, ++}; ++ ++/** ++ * armctrl_init - initialise a vectored interrupt controller ++ * @base: iomem base address ++ * @irq_start: starting interrupt number, must be muliple of 32 ++ * @armctrl_sources: bitmask of interrupt sources to allow ++ * @resume_sources: bitmask of interrupt sources to allow for resume ++ */ ++int __init armctrl_init(void __iomem * base, unsigned int irq_start, ++ u32 armctrl_sources, u32 resume_sources) ++{ ++ unsigned int irq; ++ ++ for (irq = 0; irq < BCM2708_ALLOC_IRQS; irq++) { ++ unsigned int data = irq; ++ if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO) ++ data = remap_irqs[irq - INTERRUPT_JPEG]; ++ ++ irq_set_chip(irq, &armctrl_chip); ++ irq_set_chip_data(irq, (void *)data); ++ irq_set_handler(irq, handle_level_irq); ++ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); ++ } ++ ++ armctrl_pm_register(base, irq_start, resume_sources); ++ init_FIQ(FIQ_START); ++ armctrl_dt_init(); ++ return 0; ++} +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/armctrl.h linux-rpi/arch/arm/mach-bcm2708/armctrl.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2708/armctrl.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2708/armctrl.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,27 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/armctrl.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef __BCM2708_ARMCTRL_H ++#define __BCM2708_ARMCTRL_H ++ ++extern int __init armctrl_init(void __iomem * base, unsigned int irq_start, ++ u32 armctrl_sources, u32 resume_sources); ++ ++#endif +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/bcm2708.c linux-rpi/arch/arm/mach-bcm2708/bcm2708.c +--- linux-4.1.13.orig/arch/arm/mach-bcm2708/bcm2708.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2708/bcm2708.c 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,1162 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/bcm2708.c ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++ ++#include "bcm2708.h" ++#include "armctrl.h" ++ ++#ifdef CONFIG_BCM_VC_CMA ++#include ++#endif ++ ++ ++/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to ++ * give us IO access only to 64Mbytes of physical memory (26 bits). We could ++ * represent this window by setting our dmamasks to 26 bits but, in fact ++ * we're not going to use addresses outside this range (they're not in real ++ * memory) so we don't bother. ++ * ++ * In the future we might include code to use this IOMMU to remap other ++ * physical addresses onto VideoCore memory then the use of 32-bits would be ++ * more legitimate. ++ */ ++#define DMA_MASK_BITS_COMMON 32 ++ ++// use GPIO 4 for the one-wire GPIO pin, if enabled ++#define W1_GPIO 4 ++// ensure one-wire GPIO pullup is disabled by default ++#define W1_PULLUP -1 ++ ++/* command line parameters */ ++static unsigned boardrev, serial; ++static unsigned uart_clock = UART0_CLOCK; ++static unsigned disk_led_gpio = 16; ++static unsigned disk_led_active_low = 1; ++static unsigned reboot_part = 0; ++static unsigned w1_gpio_pin = W1_GPIO; ++static unsigned w1_gpio_pullup = W1_PULLUP; ++static bool vc_i2c_override = false; ++static int pps_gpio_pin = -1; ++ ++static unsigned use_dt = 0; ++ ++static void __init bcm2708_init_led(void); ++ ++void __init bcm2708_init_irq(void) ++{ ++ armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0); ++} ++ ++static struct map_desc bcm2708_io_desc[] __initdata = { ++ { ++ .virtual = IO_ADDRESS(ARMCTRL_BASE), ++ .pfn = __phys_to_pfn(ARMCTRL_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(UART0_BASE), ++ .pfn = __phys_to_pfn(UART0_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(UART1_BASE), ++ .pfn = __phys_to_pfn(UART1_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(DMA_BASE), ++ .pfn = __phys_to_pfn(DMA_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(MCORE_BASE), ++ .pfn = __phys_to_pfn(MCORE_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(ST_BASE), ++ .pfn = __phys_to_pfn(ST_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(USB_BASE), ++ .pfn = __phys_to_pfn(USB_BASE), ++ .length = SZ_128K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(PM_BASE), ++ .pfn = __phys_to_pfn(PM_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(GPIO_BASE), ++ .pfn = __phys_to_pfn(GPIO_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE} ++}; ++ ++void __init bcm2708_map_io(void) ++{ ++ iotable_init(bcm2708_io_desc, ARRAY_SIZE(bcm2708_io_desc)); ++} ++ ++/* The STC is a free running counter that increments at the rate of 1MHz */ ++#define STC_FREQ_HZ 1000000 ++ ++static inline uint32_t timer_read(void) ++{ ++ /* STC: a free running counter that increments at the rate of 1MHz */ ++ return readl(__io_address(ST_BASE + 0x04)); ++} ++ ++static unsigned long bcm2708_read_current_timer(void) ++{ ++ return timer_read(); ++} ++ ++static u64 notrace bcm2708_read_sched_clock(void) ++{ ++ return timer_read(); ++} ++ ++static cycle_t clksrc_read(struct clocksource *cs) ++{ ++ return timer_read(); ++} ++ ++static struct clocksource clocksource_stc = { ++ .name = "stc", ++ .rating = 300, ++ .read = clksrc_read, ++ .mask = CLOCKSOURCE_MASK(32), ++ .flags = CLOCK_SOURCE_IS_CONTINUOUS, ++}; ++ ++unsigned long frc_clock_ticks32(void) ++{ ++ return timer_read(); ++} ++ ++static void __init bcm2708_clocksource_init(void) ++{ ++ if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) { ++ printk(KERN_ERR "timer: failed to initialize clock " ++ "source %s\n", clocksource_stc.name); ++ } ++} ++ ++struct clk __init *bcm2708_clk_register(const char *name, unsigned long fixed_rate) ++{ ++ struct clk *clk; ++ ++ clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, ++ fixed_rate); ++ if (IS_ERR(clk)) ++ pr_err("%s not registered\n", name); ++ ++ return clk; ++} ++ ++void __init bcm2708_register_clkdev(struct clk *clk, const char *name) ++{ ++ int ret; ++ ++ ret = clk_register_clkdev(clk, NULL, name); ++ if (ret) ++ pr_err("%s alias not registered\n", name); ++} ++ ++void __init bcm2708_init_clocks(void) ++{ ++ struct clk *clk; ++ ++ clk = bcm2708_clk_register("uart0_clk", uart_clock); ++ bcm2708_register_clkdev(clk, "dev:f1"); ++ ++ clk = bcm2708_clk_register("sdhost_clk", 250000000); ++ bcm2708_register_clkdev(clk, "mmc-bcm2835.0"); ++ bcm2708_register_clkdev(clk, "bcm2708_spi.0"); ++ bcm2708_register_clkdev(clk, "bcm2708_i2c.0"); ++ bcm2708_register_clkdev(clk, "bcm2708_i2c.1"); ++} ++ ++#define UART0_IRQ { IRQ_UART, 0 /*NO_IRQ*/ } ++#define UART0_DMA { 15, 14 } ++ ++AMBA_DEVICE(uart0, "dev:f1", UART0, NULL); ++ ++static struct amba_device *amba_devs[] __initdata = { ++ &uart0_device, ++}; ++ ++static struct resource bcm2708_dmaengine_resources[] = { ++ { ++ .start = DMA_BASE, ++ .end = DMA_BASE + SZ_4K - 1, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .start = IRQ_DMA0, ++ .end = IRQ_DMA0, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA1, ++ .end = IRQ_DMA1, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA2, ++ .end = IRQ_DMA2, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA3, ++ .end = IRQ_DMA3, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA4, ++ .end = IRQ_DMA4, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA5, ++ .end = IRQ_DMA5, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA6, ++ .end = IRQ_DMA6, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA7, ++ .end = IRQ_DMA7, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA8, ++ .end = IRQ_DMA8, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA9, ++ .end = IRQ_DMA9, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA10, ++ .end = IRQ_DMA10, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA11, ++ .end = IRQ_DMA11, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA12, ++ .end = IRQ_DMA12, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct platform_device bcm2708_dmaengine_device = { ++ .name = "bcm2708-dmaengine", ++ .id = -1, ++ .resource = bcm2708_dmaengine_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_dmaengine_resources), ++}; ++ ++#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE) ++static struct w1_gpio_platform_data w1_gpio_pdata = { ++ .pin = W1_GPIO, ++ .ext_pullup_enable_pin = W1_PULLUP, ++ .is_open_drain = 0, ++}; ++ ++static struct platform_device w1_device = { ++ .name = "w1-gpio", ++ .id = -1, ++ .dev.platform_data = &w1_gpio_pdata, ++}; ++#endif ++ ++static struct pps_gpio_platform_data pps_gpio_info = { ++ .assert_falling_edge = false, ++ .capture_clear = false, ++ .gpio_pin = -1, ++ .gpio_label = "PPS", ++}; ++ ++static struct platform_device pps_gpio_device = { ++ .name = "pps-gpio", ++ .id = PLATFORM_DEVID_NONE, ++ .dev.platform_data = &pps_gpio_info, ++}; ++ ++static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++ ++static struct platform_device bcm2708_fb_device = { ++ .name = "bcm2708_fb", ++ .id = -1, /* only one bcm2708_fb */ ++ .resource = NULL, ++ .num_resources = 0, ++ .dev = { ++ .dma_mask = &fb_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, ++}; ++ ++static struct resource bcm2708_usb_resources[] = { ++ [0] = { ++ .start = USB_BASE, ++ .end = USB_BASE + SZ_128K - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = MPHI_BASE, ++ .end = MPHI_BASE + SZ_4K - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [2] = { ++ .start = IRQ_HOSTPORT, ++ .end = IRQ_HOSTPORT, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [3] = { ++ .start = IRQ_USB, ++ .end = IRQ_USB, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++ ++static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++ ++static struct platform_device bcm2708_usb_device = { ++ .name = "bcm2708_usb", ++ .id = -1, /* only one bcm2708_usb */ ++ .resource = bcm2708_usb_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_usb_resources), ++ .dev = { ++ .dma_mask = &usb_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, ++}; ++ ++static struct resource bcm2708_vcio_resources[] = { ++ { ++ .start = ARMCTRL_0_MAIL0_BASE, ++ .end = ARMCTRL_0_MAIL0_BASE + SZ_64 - 1, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .start = IRQ_ARM_MAILBOX, ++ .end = IRQ_ARM_MAILBOX, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static u64 vcio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++ ++static struct platform_device bcm2708_vcio_device = { ++ .name = "bcm2835-mbox", ++ .id = -1, /* only one VideoCore I/O area */ ++ .resource = bcm2708_vcio_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_vcio_resources), ++ .dev = { ++ .dma_mask = &vcio_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, ++}; ++ ++static u64 rpifw_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++ ++static struct platform_device bcm2708_rpifw_device = { ++ .name = "raspberrypi-firmware", ++ .dev = { ++ .dma_mask = &rpifw_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, ++}; ++ ++static struct resource bcm2708_vchiq_resources[] = { ++ { ++ .start = ARMCTRL_0_BELL_BASE, ++ .end = ARMCTRL_0_BELL_BASE + 16, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .start = IRQ_ARM_DOORBELL_0, ++ .end = IRQ_ARM_DOORBELL_0, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static u64 vchiq_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++ ++static struct platform_device bcm2708_vchiq_device = { ++ .name = "bcm2835_vchiq", ++ .id = -1, ++ .resource = bcm2708_vchiq_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_vchiq_resources), ++ .dev = { ++ .dma_mask = &vchiq_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, ++}; ++ ++#ifdef CONFIG_BCM2708_GPIO ++#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio" ++ ++static struct resource bcm2708_gpio_resources[] = { ++ [0] = { /* general purpose I/O */ ++ .start = GPIO_BASE, ++ .end = GPIO_BASE + SZ_4K - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++}; ++ ++static u64 gpio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++ ++static struct platform_device bcm2708_gpio_device = { ++ .name = BCM_GPIO_DRIVER_NAME, ++ .id = -1, /* only one VideoCore I/O area */ ++ .resource = bcm2708_gpio_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_gpio_resources), ++ .dev = { ++ .dma_mask = &gpio_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, ++}; ++#endif ++ ++#ifdef CONFIG_MMC_BCM2835 /* Arasan emmc SD (new) */ ++static struct resource bcm2835_emmc_resources[] = { ++ [0] = { ++ .start = EMMC_BASE, ++ .end = EMMC_BASE + SZ_256 - 1, /* we only need this area */ ++ /* the memory map actually makes SZ_4K available */ ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_ARASANSDIO, ++ .end = IRQ_ARASANSDIO, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static u64 bcm2835_emmc_dmamask = 0xffffffffUL; ++ ++struct platform_device bcm2835_emmc_device = { ++ .name = "mmc-bcm2835", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(bcm2835_emmc_resources), ++ .resource = bcm2835_emmc_resources, ++ .dev = { ++ .dma_mask = &bcm2835_emmc_dmamask, ++ .coherent_dma_mask = 0xffffffffUL}, ++}; ++#endif /* CONFIG_MMC_BCM2835 */ ++ ++static struct platform_device bcm2708_alsa_devices[] = { ++ [0] = { ++ .name = "bcm2835_AUD0", ++ .id = 0, /* first audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++ [1] = { ++ .name = "bcm2835_AUD1", ++ .id = 1, /* second audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++ [2] = { ++ .name = "bcm2835_AUD2", ++ .id = 2, /* third audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++ [3] = { ++ .name = "bcm2835_AUD3", ++ .id = 3, /* forth audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++ [4] = { ++ .name = "bcm2835_AUD4", ++ .id = 4, /* fifth audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++ [5] = { ++ .name = "bcm2835_AUD5", ++ .id = 5, /* sixth audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++ [6] = { ++ .name = "bcm2835_AUD6", ++ .id = 6, /* seventh audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++ [7] = { ++ .name = "bcm2835_AUD7", ++ .id = 7, /* eighth audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++}; ++ ++static struct resource bcm2708_spi_resources[] = { ++ { ++ .start = SPI0_BASE, ++ .end = SPI0_BASE + SZ_256 - 1, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .start = IRQ_SPI, ++ .end = IRQ_SPI, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++ ++static u64 bcm2708_spi_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++static struct platform_device bcm2708_spi_device = { ++ .name = "bcm2708_spi", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(bcm2708_spi_resources), ++ .resource = bcm2708_spi_resources, ++ .dev = { ++ .dma_mask = &bcm2708_spi_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON)}, ++}; ++ ++#ifdef CONFIG_BCM2708_SPIDEV ++static struct spi_board_info bcm2708_spi_devices[] = { ++#ifdef CONFIG_SPI_SPIDEV ++ { ++ .modalias = "spidev", ++ .max_speed_hz = 500000, ++ .bus_num = 0, ++ .chip_select = 0, ++ .mode = SPI_MODE_0, ++ }, { ++ .modalias = "spidev", ++ .max_speed_hz = 500000, ++ .bus_num = 0, ++ .chip_select = 1, ++ .mode = SPI_MODE_0, ++ } ++#endif ++}; ++#endif ++ ++static struct resource bcm2708_bsc0_resources[] = { ++ { ++ .start = BSC0_BASE, ++ .end = BSC0_BASE + SZ_256 - 1, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .start = INTERRUPT_I2C, ++ .end = INTERRUPT_I2C, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct platform_device bcm2708_bsc0_device = { ++ .name = "bcm2708_i2c", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(bcm2708_bsc0_resources), ++ .resource = bcm2708_bsc0_resources, ++}; ++ ++ ++static struct resource bcm2708_bsc1_resources[] = { ++ { ++ .start = BSC1_BASE, ++ .end = BSC1_BASE + SZ_256 - 1, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .start = INTERRUPT_I2C, ++ .end = INTERRUPT_I2C, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct platform_device bcm2708_bsc1_device = { ++ .name = "bcm2708_i2c", ++ .id = 1, ++ .num_resources = ARRAY_SIZE(bcm2708_bsc1_resources), ++ .resource = bcm2708_bsc1_resources, ++}; ++ ++static struct platform_device bcm2835_thermal_device = { ++ .name = "bcm2835_thermal", ++}; ++ ++#if defined(CONFIG_SND_BCM2708_SOC_I2S) || defined(CONFIG_SND_BCM2708_SOC_I2S_MODULE) ++static struct resource bcm2708_i2s_resources[] = { ++ { ++ .start = I2S_BASE, ++ .end = I2S_BASE + 0x20, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .start = PCM_CLOCK_BASE, ++ .end = PCM_CLOCK_BASE + 0x02, ++ .flags = IORESOURCE_MEM, ++ } ++}; ++ ++static struct platform_device bcm2708_i2s_device = { ++ .name = "bcm2708-i2s", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(bcm2708_i2s_resources), ++ .resource = bcm2708_i2s_resources, ++}; ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC_MODULE) ++static struct platform_device snd_hifiberry_dac_device = { ++ .name = "snd-hifiberry-dac", ++ .id = 0, ++ .num_resources = 0, ++}; ++ ++static struct platform_device snd_pcm5102a_codec_device = { ++ .name = "pcm5102a-codec", ++ .id = -1, ++ .num_resources = 0, ++}; ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS_MODULE) ++static struct platform_device snd_rpi_hifiberry_dacplus_device = { ++ .name = "snd-rpi-hifiberry-dacplus", ++ .id = 0, ++ .num_resources = 0, ++}; ++ ++static struct i2c_board_info __initdata snd_pcm512x_hbdacplus_i2c_devices[] = { ++ { ++ I2C_BOARD_INFO("pcm5122", 0x4d) ++ }, ++}; ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI_MODULE) ++static struct platform_device snd_hifiberry_digi_device = { ++ .name = "snd-hifiberry-digi", ++ .id = 0, ++ .num_resources = 0, ++}; ++ ++static struct i2c_board_info __initdata snd_wm8804_i2c_devices[] = { ++ { ++ I2C_BOARD_INFO("wm8804", 0x3b) ++ }, ++}; ++ ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP_MODULE) ++static struct platform_device snd_hifiberry_amp_device = { ++ .name = "snd-hifiberry-amp", ++ .id = 0, ++ .num_resources = 0, ++}; ++ ++static struct i2c_board_info __initdata snd_tas5713_i2c_devices[] = { ++ { ++ I2C_BOARD_INFO("tas5713", 0x1b) ++ }, ++}; ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_RPI_DAC) || defined(CONFIG_SND_BCM2708_SOC_RPI_DAC_MODULE) ++static struct platform_device snd_rpi_dac_device = { ++ .name = "snd-rpi-dac", ++ .id = 0, ++ .num_resources = 0, ++}; ++ ++static struct platform_device snd_pcm1794a_codec_device = { ++ .name = "pcm1794a-codec", ++ .id = -1, ++ .num_resources = 0, ++}; ++#endif ++ ++ ++#if defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) || defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC_MODULE) ++static struct platform_device snd_rpi_iqaudio_dac_device = { ++ .name = "snd-rpi-iqaudio-dac", ++ .id = 0, ++ .num_resources = 0, ++}; ++ ++// Use the actual device name rather than generic driver name ++static struct i2c_board_info __initdata snd_pcm512x_i2c_devices[] = { ++ { ++ I2C_BOARD_INFO("pcm5122", 0x4c) ++ }, ++}; ++#endif ++ ++int __init bcm_register_device(struct platform_device *pdev) ++{ ++ int ret; ++ ++ ret = platform_device_register(pdev); ++ if (ret) ++ pr_debug("Unable to register platform device '%s': %d\n", ++ pdev->name, ret); ++ ++ return ret; ++} ++ ++/* ++ * Use these macros for platform and i2c devices that are present in the ++ * Device Tree. This way the devices are only added on non-DT systems. ++ */ ++#define bcm_register_device_dt(pdev) \ ++ if (!use_dt) bcm_register_device(pdev) ++ ++#define i2c_register_board_info_dt(busnum, info, n) \ ++ if (!use_dt) i2c_register_board_info(busnum, info, n) ++ ++int calc_rsts(int partition) ++{ ++ return PM_PASSWORD | ++ ((partition & (1 << 0)) << 0) | ++ ((partition & (1 << 1)) << 1) | ++ ((partition & (1 << 2)) << 2) | ++ ((partition & (1 << 3)) << 3) | ++ ((partition & (1 << 4)) << 4) | ++ ((partition & (1 << 5)) << 5); ++} ++ ++static void bcm2708_restart(enum reboot_mode mode, const char *cmd) ++{ ++ extern char bcm2708_reboot_mode; ++ uint32_t pm_rstc, pm_wdog; ++ uint32_t timeout = 10; ++ uint32_t pm_rsts = 0; ++ ++ if(bcm2708_reboot_mode == 'q') ++ { ++ // NOOBS < 1.3 booting with reboot=q ++ pm_rsts = readl(__io_address(PM_RSTS)); ++ pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET; ++ } ++ else if(bcm2708_reboot_mode == 'p') ++ { ++ // NOOBS < 1.3 halting ++ pm_rsts = readl(__io_address(PM_RSTS)); ++ pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRH_SET; ++ } ++ else ++ { ++ pm_rsts = calc_rsts(reboot_part); ++ } ++ ++ writel(pm_rsts, __io_address(PM_RSTS)); ++ ++ /* Setup watchdog for reset */ ++ pm_rstc = readl(__io_address(PM_RSTC)); ++ ++ pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0) ++ pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET; ++ ++ writel(pm_wdog, __io_address(PM_WDOG)); ++ writel(pm_rstc, __io_address(PM_RSTC)); ++} ++ ++/* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */ ++static void bcm2708_power_off(void) ++{ ++ extern char bcm2708_reboot_mode; ++ if(bcm2708_reboot_mode == 'q') ++ { ++ // NOOBS < v1.3 ++ bcm2708_restart('p', ""); ++ } ++ else ++ { ++ /* partition 63 is special code for HALT the bootloader knows not to boot*/ ++ reboot_part = 63; ++ /* continue with normal reset mechanism */ ++ bcm2708_restart(0, ""); ++ } ++} ++ ++static void __init bcm2708_init_uart1(void) ++{ ++ struct device_node *np; ++ ++ np = of_find_compatible_node(NULL, NULL, "brcm,bcm2835-aux-uart"); ++ if (of_device_is_available(np)) { ++ pr_info("bcm2708: Mini UART enabled\n"); ++ writel(1, __io_address(UART1_BASE + 0x4)); ++ } ++} ++ ++#ifdef CONFIG_OF ++static void __init bcm2708_dt_init(void) ++{ ++ int ret; ++ ++ of_clk_init(NULL); ++ ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); ++ if (ret) { ++ pr_err("of_platform_populate failed: %d\n", ret); ++ /* Proceed as if CONFIG_OF was not defined */ ++ } else { ++ use_dt = 1; ++ } ++} ++#else ++static void __init bcm2708_dt_init(void) { } ++#endif /* CONFIG_OF */ ++ ++void __init bcm2708_init(void) ++{ ++ int i; ++ ++#if defined(CONFIG_BCM_VC_CMA) ++ vc_cma_early_init(); ++#endif ++ printk("bcm2708.uart_clock = %d\n", uart_clock); ++ pm_power_off = bcm2708_power_off; ++ ++ bcm2708_init_clocks(); ++ bcm2708_dt_init(); ++ ++ bcm_register_device_dt(&bcm2708_dmaengine_device); ++ bcm_register_device_dt(&bcm2708_vcio_device); ++ bcm_register_device_dt(&bcm2708_rpifw_device); ++ bcm_register_device_dt(&bcm2708_vchiq_device); ++#ifdef CONFIG_BCM2708_GPIO ++ bcm_register_device_dt(&bcm2708_gpio_device); ++#endif ++ ++#if defined(CONFIG_PPS_CLIENT_GPIO) || defined(CONFIG_PPS_CLIENT_GPIO_MODULE) ++ if (!use_dt && (pps_gpio_pin >= 0)) { ++ pr_info("bcm2708: GPIO %d setup as pps-gpio device\n", pps_gpio_pin); ++ pps_gpio_info.gpio_pin = pps_gpio_pin; ++ pps_gpio_device.id = pps_gpio_pin; ++ bcm_register_device(&pps_gpio_device); ++ } ++#endif ++ ++#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE) ++ w1_gpio_pdata.pin = w1_gpio_pin; ++ w1_gpio_pdata.ext_pullup_enable_pin = w1_gpio_pullup; ++ bcm_register_device_dt(&w1_device); ++#endif ++ bcm_register_device_dt(&bcm2708_fb_device); ++ bcm_register_device_dt(&bcm2708_usb_device); ++ ++#ifdef CONFIG_MMC_BCM2835 ++ bcm_register_device_dt(&bcm2835_emmc_device); ++#endif ++ bcm2708_init_led(); ++ bcm2708_init_uart1(); ++ ++ /* Only create the platform devices for the ALSA driver in the ++ absence of an enabled "audio" DT node */ ++ if (!use_dt || ++ !of_device_is_available(of_find_node_by_path("/audio"))) { ++ for (i = 0; i < ARRAY_SIZE(bcm2708_alsa_devices); i++) ++ bcm_register_device(&bcm2708_alsa_devices[i]); ++ } ++ ++ bcm_register_device_dt(&bcm2708_spi_device); ++ ++ if (vc_i2c_override) { ++ bcm_register_device_dt(&bcm2708_bsc0_device); ++ bcm_register_device_dt(&bcm2708_bsc1_device); ++ } else if ((boardrev & 0xffffff) == 0x2 || (boardrev & 0xffffff) == 0x3) { ++ bcm_register_device_dt(&bcm2708_bsc0_device); ++ } else { ++ bcm_register_device_dt(&bcm2708_bsc1_device); ++ } ++ ++ bcm_register_device_dt(&bcm2835_thermal_device); ++ ++#if defined(CONFIG_SND_BCM2708_SOC_I2S) || defined(CONFIG_SND_BCM2708_SOC_I2S_MODULE) ++ bcm_register_device_dt(&bcm2708_i2s_device); ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC_MODULE) ++ bcm_register_device_dt(&snd_hifiberry_dac_device); ++ bcm_register_device_dt(&snd_pcm5102a_codec_device); ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS_MODULE) ++ bcm_register_device_dt(&snd_rpi_hifiberry_dacplus_device); ++ i2c_register_board_info_dt(1, snd_pcm512x_hbdacplus_i2c_devices, ARRAY_SIZE(snd_pcm512x_hbdacplus_i2c_devices)); ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI_MODULE) ++ bcm_register_device_dt(&snd_hifiberry_digi_device); ++ i2c_register_board_info_dt(1, snd_wm8804_i2c_devices, ARRAY_SIZE(snd_wm8804_i2c_devices)); ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP_MODULE) ++ bcm_register_device_dt(&snd_hifiberry_amp_device); ++ i2c_register_board_info_dt(1, snd_tas5713_i2c_devices, ARRAY_SIZE(snd_tas5713_i2c_devices)); ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_RPI_DAC) || defined(CONFIG_SND_BCM2708_SOC_RPI_DAC_MODULE) ++ bcm_register_device_dt(&snd_rpi_dac_device); ++ bcm_register_device_dt(&snd_pcm1794a_codec_device); ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) || defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC_MODULE) ++ bcm_register_device_dt(&snd_rpi_iqaudio_dac_device); ++ i2c_register_board_info_dt(1, snd_pcm512x_i2c_devices, ARRAY_SIZE(snd_pcm512x_i2c_devices)); ++#endif ++ ++ if (!use_dt) { ++ for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { ++ struct amba_device *d = amba_devs[i]; ++ amba_device_register(d, &iomem_resource); ++ } ++ } ++ system_rev = boardrev; ++ system_serial_low = serial; ++ ++#ifdef CONFIG_BCM2708_SPIDEV ++ if (!use_dt) ++ spi_register_board_info(bcm2708_spi_devices, ++ ARRAY_SIZE(bcm2708_spi_devices)); ++#endif ++} ++ ++static void timer_set_mode(enum clock_event_mode mode, ++ struct clock_event_device *clk) ++{ ++ switch (mode) { ++ case CLOCK_EVT_MODE_ONESHOT: /* Leave the timer disabled, .set_next_event will enable it */ ++ case CLOCK_EVT_MODE_SHUTDOWN: ++ break; ++ case CLOCK_EVT_MODE_PERIODIC: ++ ++ case CLOCK_EVT_MODE_UNUSED: ++ case CLOCK_EVT_MODE_RESUME: ++ ++ default: ++ printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n", ++ (int)mode); ++ break; ++ } ++ ++} ++ ++static int timer_set_next_event(unsigned long cycles, ++ struct clock_event_device *unused) ++{ ++ unsigned long stc; ++ do { ++ stc = readl(__io_address(ST_BASE + 0x04)); ++ /* We could take a FIQ here, which may push ST above STC3 */ ++ writel(stc + cycles, __io_address(ST_BASE + 0x18)); ++ } while ((signed long) cycles >= 0 && ++ (signed long) (readl(__io_address(ST_BASE + 0x04)) - stc) ++ >= (signed long) cycles); ++ return 0; ++} ++ ++static struct clock_event_device timer0_clockevent = { ++ .name = "timer0", ++ .shift = 32, ++ .features = CLOCK_EVT_FEAT_ONESHOT, ++ .set_mode = timer_set_mode, ++ .set_next_event = timer_set_next_event, ++}; ++ ++/* ++ * IRQ handler for the timer ++ */ ++static irqreturn_t bcm2708_timer_interrupt(int irq, void *dev_id) ++{ ++ struct clock_event_device *evt = &timer0_clockevent; ++ ++ writel(1 << 3, __io_address(ST_BASE + 0x00)); /* stcs clear timer int */ ++ ++ evt->event_handler(evt); ++ ++ return IRQ_HANDLED; ++} ++ ++static struct irqaction bcm2708_timer_irq = { ++ .name = "BCM2708 Timer Tick", ++ .flags = IRQF_TIMER | IRQF_IRQPOLL, ++ .handler = bcm2708_timer_interrupt, ++}; ++ ++/* ++ * Set up timer interrupt, and return the current time in seconds. ++ */ ++ ++static struct delay_timer bcm2708_delay_timer = { ++ .read_current_timer = bcm2708_read_current_timer, ++ .freq = STC_FREQ_HZ, ++}; ++ ++static void __init bcm2708_timer_init(void) ++{ ++ /* init high res timer */ ++ bcm2708_clocksource_init(); ++ ++ /* ++ * Make irqs happen for the system timer ++ */ ++ setup_irq(IRQ_TIMER3, &bcm2708_timer_irq); ++ ++ sched_clock_register(bcm2708_read_sched_clock, 32, STC_FREQ_HZ); ++ ++ timer0_clockevent.mult = ++ div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift); ++ timer0_clockevent.max_delta_ns = ++ clockevent_delta2ns(0xffffffff, &timer0_clockevent); ++ timer0_clockevent.min_delta_ns = ++ clockevent_delta2ns(0xf, &timer0_clockevent); ++ ++ timer0_clockevent.cpumask = cpumask_of(0); ++ clockevents_register_device(&timer0_clockevent); ++ ++ register_current_timer_delay(&bcm2708_delay_timer); ++} ++ ++#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) ++#include ++ ++static struct gpio_led bcm2708_leds[] = { ++ [0] = { ++ .gpio = 16, ++ .name = "led0", ++ .default_trigger = "mmc0", ++ .active_low = 1, ++ }, ++}; ++ ++static struct gpio_led_platform_data bcm2708_led_pdata = { ++ .num_leds = ARRAY_SIZE(bcm2708_leds), ++ .leds = bcm2708_leds, ++}; ++ ++static struct platform_device bcm2708_led_device = { ++ .name = "leds-gpio", ++ .id = -1, ++ .dev = { ++ .platform_data = &bcm2708_led_pdata, ++ }, ++}; ++ ++static void __init bcm2708_init_led(void) ++{ ++ bcm2708_leds[0].gpio = disk_led_gpio; ++ bcm2708_leds[0].active_low = disk_led_active_low; ++ bcm_register_device_dt(&bcm2708_led_device); ++} ++#else ++static inline void bcm2708_init_led(void) ++{ ++} ++#endif ++ ++void __init bcm2708_init_early(void) ++{ ++ /* ++ * Some devices allocate their coherent buffers from atomic ++ * context. Increase size of atomic coherent pool to make sure such ++ * the allocations won't fail. ++ */ ++ init_dma_coherent_pool_size(SZ_4M); ++} ++ ++static void __init board_reserve(void) ++{ ++#if defined(CONFIG_BCM_VC_CMA) ++ vc_cma_reserve(); ++#endif ++} ++ ++static const char * const bcm2708_compat[] = { ++ "brcm,bcm2708", ++ NULL ++}; ++ ++MACHINE_START(BCM2708, "BCM2708") ++ /* Maintainer: Broadcom Europe Ltd. */ ++ .map_io = bcm2708_map_io, ++ .init_irq = bcm2708_init_irq, ++ .init_time = bcm2708_timer_init, ++ .init_machine = bcm2708_init, ++ .init_early = bcm2708_init_early, ++ .reserve = board_reserve, ++ .restart = bcm2708_restart, ++ .dt_compat = bcm2708_compat, ++MACHINE_END ++ ++module_param(boardrev, uint, 0644); ++module_param(serial, uint, 0644); ++module_param(uart_clock, uint, 0644); ++module_param(disk_led_gpio, uint, 0644); ++module_param(disk_led_active_low, uint, 0644); ++module_param(reboot_part, uint, 0644); ++module_param(w1_gpio_pin, uint, 0644); ++module_param(w1_gpio_pullup, uint, 0644); ++module_param(vc_i2c_override, bool, 0644); ++MODULE_PARM_DESC(vc_i2c_override, "Allow the use of VC's I2C peripheral."); ++module_param(pps_gpio_pin, int, 0644); ++MODULE_PARM_DESC(pps_gpio_pin, "Set GPIO pin to reserve for PPS"); +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/bcm2708_gpio.c linux-rpi/arch/arm/mach-bcm2708/bcm2708_gpio.c +--- linux-4.1.13.orig/arch/arm/mach-bcm2708/bcm2708_gpio.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2708/bcm2708_gpio.c 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,426 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/bcm2708_gpio.c ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio" ++#define DRIVER_NAME BCM_GPIO_DRIVER_NAME ++#define BCM_GPIO_USE_IRQ 1 ++ ++#define GPIOFSEL(x) (0x00+(x)*4) ++#define GPIOSET(x) (0x1c+(x)*4) ++#define GPIOCLR(x) (0x28+(x)*4) ++#define GPIOLEV(x) (0x34+(x)*4) ++#define GPIOEDS(x) (0x40+(x)*4) ++#define GPIOREN(x) (0x4c+(x)*4) ++#define GPIOFEN(x) (0x58+(x)*4) ++#define GPIOHEN(x) (0x64+(x)*4) ++#define GPIOLEN(x) (0x70+(x)*4) ++#define GPIOAREN(x) (0x7c+(x)*4) ++#define GPIOAFEN(x) (0x88+(x)*4) ++#define GPIOUD(x) (0x94+(x)*4) ++#define GPIOUDCLK(x) (0x98+(x)*4) ++ ++#define GPIO_BANKS 2 ++ ++enum { GPIO_FSEL_INPUT, GPIO_FSEL_OUTPUT, ++ GPIO_FSEL_ALT5, GPIO_FSEL_ALT_4, ++ GPIO_FSEL_ALT0, GPIO_FSEL_ALT1, ++ GPIO_FSEL_ALT2, GPIO_FSEL_ALT3, ++}; ++ ++ /* Each of the two spinlocks protects a different set of hardware ++ * regiters and data structurs. This decouples the code of the IRQ from ++ * the GPIO code. This also makes the case of a GPIO routine call from ++ * the IRQ code simpler. ++ */ ++static DEFINE_SPINLOCK(lock); /* GPIO registers */ ++ ++struct bcm2708_gpio { ++ struct list_head list; ++ void __iomem *base; ++ struct gpio_chip gc; ++ unsigned long rising[(BCM2708_NR_GPIOS + 31) / 32]; ++ unsigned long falling[(BCM2708_NR_GPIOS + 31) / 32]; ++ unsigned long high[(BCM2708_NR_GPIOS + 31) / 32]; ++ unsigned long low[(BCM2708_NR_GPIOS + 31) / 32]; ++}; ++ ++static int bcm2708_set_function(struct gpio_chip *gc, unsigned offset, ++ int function) ++{ ++ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); ++ unsigned long flags; ++ unsigned gpiodir; ++ unsigned gpio_bank = offset / 10; ++ unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3; ++ ++//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set_function %p (%d,%d)\n", gc, offset, function); ++ if (offset >= BCM2708_NR_GPIOS) ++ return -EINVAL; ++ ++ spin_lock_irqsave(&lock, flags); ++ ++ gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank)); ++ gpiodir &= ~(7 << gpio_field_offset); ++ gpiodir |= function << gpio_field_offset; ++ writel(gpiodir, gpio->base + GPIOFSEL(gpio_bank)); ++ spin_unlock_irqrestore(&lock, flags); ++ gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank)); ++ ++ return 0; ++} ++ ++static int bcm2708_gpio_dir_in(struct gpio_chip *gc, unsigned offset) ++{ ++ return bcm2708_set_function(gc, offset, GPIO_FSEL_INPUT); ++} ++ ++static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value); ++static int bcm2708_gpio_dir_out(struct gpio_chip *gc, unsigned offset, ++ int value) ++{ ++ int ret; ++ ret = bcm2708_set_function(gc, offset, GPIO_FSEL_OUTPUT); ++ if (ret >= 0) ++ bcm2708_gpio_set(gc, offset, value); ++ return ret; ++} ++ ++static int bcm2708_gpio_get(struct gpio_chip *gc, unsigned offset) ++{ ++ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); ++ unsigned gpio_bank = offset / 32; ++ unsigned gpio_field_offset = (offset - 32 * gpio_bank); ++ unsigned lev; ++ ++ if (offset >= BCM2708_NR_GPIOS) ++ return 0; ++ lev = readl(gpio->base + GPIOLEV(gpio_bank)); ++//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_get %p (%d)=%d\n", gc, offset, 0x1 & (lev>>gpio_field_offset)); ++ return 0x1 & (lev >> gpio_field_offset); ++} ++ ++static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value) ++{ ++ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); ++ unsigned gpio_bank = offset / 32; ++ unsigned gpio_field_offset = (offset - 32 * gpio_bank); ++//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set %p (%d=%d)\n", gc, offset, value); ++ if (offset >= BCM2708_NR_GPIOS) ++ return; ++ if (value) ++ writel(1 << gpio_field_offset, gpio->base + GPIOSET(gpio_bank)); ++ else ++ writel(1 << gpio_field_offset, gpio->base + GPIOCLR(gpio_bank)); ++} ++ ++/********************** ++ * extension to configure pullups ++ */ ++int bcm2708_gpio_setpull(struct gpio_chip *gc, unsigned offset, ++ bcm2708_gpio_pull_t value) ++{ ++ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); ++ unsigned gpio_bank = offset / 32; ++ unsigned gpio_field_offset = (offset - 32 * gpio_bank); ++ ++ if (offset >= BCM2708_NR_GPIOS) ++ return -EINVAL; ++ ++ switch (value) { ++ case BCM2708_PULL_UP: ++ writel(2, gpio->base + GPIOUD(0)); ++ break; ++ case BCM2708_PULL_DOWN: ++ writel(1, gpio->base + GPIOUD(0)); ++ break; ++ case BCM2708_PULL_OFF: ++ writel(0, gpio->base + GPIOUD(0)); ++ break; ++ } ++ ++ udelay(5); ++ writel(1 << gpio_field_offset, gpio->base + GPIOUDCLK(gpio_bank)); ++ udelay(5); ++ writel(0, gpio->base + GPIOUD(0)); ++ writel(0 << gpio_field_offset, gpio->base + GPIOUDCLK(gpio_bank)); ++ ++ return 0; ++} ++EXPORT_SYMBOL(bcm2708_gpio_setpull); ++ ++/************************************************************************************************************************* ++ * bcm2708 GPIO IRQ ++ */ ++ ++#if BCM_GPIO_USE_IRQ ++ ++static int bcm2708_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) ++{ ++ return gpio_to_irq(gpio); ++} ++ ++static int bcm2708_gpio_irq_set_type(struct irq_data *d, unsigned type) ++{ ++ unsigned irq = d->irq; ++ struct bcm2708_gpio *gpio = irq_get_chip_data(irq); ++ unsigned gn = irq_to_gpio(irq); ++ unsigned gb = gn / 32; ++ unsigned go = gn % 32; ++ ++ gpio->rising[gb] &= ~(1 << go); ++ gpio->falling[gb] &= ~(1 << go); ++ gpio->high[gb] &= ~(1 << go); ++ gpio->low[gb] &= ~(1 << go); ++ ++ if (type & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) ++ return -EINVAL; ++ ++ if (type & IRQ_TYPE_EDGE_RISING) ++ gpio->rising[gb] |= (1 << go); ++ if (type & IRQ_TYPE_EDGE_FALLING) ++ gpio->falling[gb] |= (1 << go); ++ if (type & IRQ_TYPE_LEVEL_HIGH) ++ gpio->high[gb] |= (1 << go); ++ if (type & IRQ_TYPE_LEVEL_LOW) ++ gpio->low[gb] |= (1 << go); ++ return 0; ++} ++ ++static void bcm2708_gpio_irq_mask(struct irq_data *d) ++{ ++ unsigned irq = d->irq; ++ struct bcm2708_gpio *gpio = irq_get_chip_data(irq); ++ unsigned gn = irq_to_gpio(irq); ++ unsigned gb = gn / 32; ++ unsigned long rising = readl(gpio->base + GPIOREN(gb)); ++ unsigned long falling = readl(gpio->base + GPIOFEN(gb)); ++ unsigned long high = readl(gpio->base + GPIOHEN(gb)); ++ unsigned long low = readl(gpio->base + GPIOLEN(gb)); ++ ++ gn = gn % 32; ++ ++ writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb)); ++ writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb)); ++ writel(high & ~(1 << gn), gpio->base + GPIOHEN(gb)); ++ writel(low & ~(1 << gn), gpio->base + GPIOLEN(gb)); ++} ++ ++static void bcm2708_gpio_irq_unmask(struct irq_data *d) ++{ ++ unsigned irq = d->irq; ++ struct bcm2708_gpio *gpio = irq_get_chip_data(irq); ++ unsigned gn = irq_to_gpio(irq); ++ unsigned gb = gn / 32; ++ unsigned go = gn % 32; ++ unsigned long rising = readl(gpio->base + GPIOREN(gb)); ++ unsigned long falling = readl(gpio->base + GPIOFEN(gb)); ++ unsigned long high = readl(gpio->base + GPIOHEN(gb)); ++ unsigned long low = readl(gpio->base + GPIOLEN(gb)); ++ ++ if (gpio->rising[gb] & (1 << go)) { ++ writel(rising | (1 << go), gpio->base + GPIOREN(gb)); ++ } else { ++ writel(rising & ~(1 << go), gpio->base + GPIOREN(gb)); ++ } ++ ++ if (gpio->falling[gb] & (1 << go)) { ++ writel(falling | (1 << go), gpio->base + GPIOFEN(gb)); ++ } else { ++ writel(falling & ~(1 << go), gpio->base + GPIOFEN(gb)); ++ } ++ ++ if (gpio->high[gb] & (1 << go)) { ++ writel(high | (1 << go), gpio->base + GPIOHEN(gb)); ++ } else { ++ writel(high & ~(1 << go), gpio->base + GPIOHEN(gb)); ++ } ++ ++ if (gpio->low[gb] & (1 << go)) { ++ writel(low | (1 << go), gpio->base + GPIOLEN(gb)); ++ } else { ++ writel(low & ~(1 << go), gpio->base + GPIOLEN(gb)); ++ } ++} ++ ++static struct irq_chip bcm2708_irqchip = { ++ .name = "GPIO", ++ .irq_enable = bcm2708_gpio_irq_unmask, ++ .irq_disable = bcm2708_gpio_irq_mask, ++ .irq_unmask = bcm2708_gpio_irq_unmask, ++ .irq_mask = bcm2708_gpio_irq_mask, ++ .irq_set_type = bcm2708_gpio_irq_set_type, ++}; ++ ++static irqreturn_t bcm2708_gpio_interrupt(int irq, void *dev_id) ++{ ++ unsigned long edsr; ++ unsigned bank; ++ int i; ++ unsigned gpio; ++ unsigned level_bits; ++ struct bcm2708_gpio *gpio_data = dev_id; ++ ++ for (bank = 0; bank < GPIO_BANKS; bank++) { ++ edsr = readl(__io_address(GPIO_BASE) + GPIOEDS(bank)); ++ level_bits = gpio_data->high[bank] | gpio_data->low[bank]; ++ ++ for_each_set_bit(i, &edsr, 32) { ++ gpio = i + bank * 32; ++ /* ack edge triggered IRQs immediately */ ++ if (!(level_bits & (1<gc.to_irq = bcm2708_gpio_to_irq; ++ ++ for (irq = GPIO_IRQ_START; irq < (GPIO_IRQ_START + GPIO_IRQS); irq++) { ++ irq_set_chip_data(irq, ucb); ++ irq_set_chip_and_handler(irq, &bcm2708_irqchip, ++ handle_simple_irq); ++ set_irq_flags(irq, IRQF_VALID); ++ } ++ ++ bcm2708_gpio_irq.dev_id = ucb; ++ setup_irq(IRQ_GPIO3, &bcm2708_gpio_irq); ++} ++ ++#else ++ ++static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb) ++{ ++} ++ ++#endif /* #if BCM_GPIO_USE_IRQ ***************************************************************************************************************** */ ++ ++static int bcm2708_gpio_probe(struct platform_device *dev) ++{ ++ struct bcm2708_gpio *ucb; ++ struct resource *res; ++ int bank; ++ int err = 0; ++ ++ printk(KERN_INFO DRIVER_NAME ": bcm2708_gpio_probe %p\n", dev); ++ ++ ucb = kzalloc(sizeof(*ucb), GFP_KERNEL); ++ if (NULL == ucb) { ++ printk(KERN_ERR DRIVER_NAME ": failed to allocate " ++ "mailbox memory\n"); ++ err = -ENOMEM; ++ goto err; ++ } ++ ++ res = platform_get_resource(dev, IORESOURCE_MEM, 0); ++ ++ platform_set_drvdata(dev, ucb); ++ ucb->base = __io_address(GPIO_BASE); ++ ++ ucb->gc.label = "bcm2708_gpio"; ++ ucb->gc.base = 0; ++ ucb->gc.ngpio = BCM2708_NR_GPIOS; ++ ucb->gc.owner = THIS_MODULE; ++ ++ ucb->gc.direction_input = bcm2708_gpio_dir_in; ++ ucb->gc.direction_output = bcm2708_gpio_dir_out; ++ ucb->gc.get = bcm2708_gpio_get; ++ ucb->gc.set = bcm2708_gpio_set; ++ ucb->gc.can_sleep = 0; ++ ++ for (bank = 0; bank < GPIO_BANKS; bank++) { ++ writel(0, ucb->base + GPIOREN(bank)); ++ writel(0, ucb->base + GPIOFEN(bank)); ++ writel(0, ucb->base + GPIOHEN(bank)); ++ writel(0, ucb->base + GPIOLEN(bank)); ++ writel(0, ucb->base + GPIOAREN(bank)); ++ writel(0, ucb->base + GPIOAFEN(bank)); ++ writel(~0, ucb->base + GPIOEDS(bank)); ++ } ++ ++ bcm2708_gpio_irq_init(ucb); ++ ++ err = gpiochip_add(&ucb->gc); ++ ++err: ++ return err; ++ ++} ++ ++static int bcm2708_gpio_remove(struct platform_device *dev) ++{ ++ int err = 0; ++ struct bcm2708_gpio *ucb = platform_get_drvdata(dev); ++ ++ printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_remove %p\n", dev); ++ ++ gpiochip_remove(&ucb->gc); ++ ++ platform_set_drvdata(dev, NULL); ++ kfree(ucb); ++ ++ return err; ++} ++ ++static struct platform_driver bcm2708_gpio_driver = { ++ .probe = bcm2708_gpio_probe, ++ .remove = bcm2708_gpio_remove, ++ .driver = { ++ .name = "bcm2708_gpio"}, ++}; ++ ++static int __init bcm2708_gpio_init(void) ++{ ++ return platform_driver_register(&bcm2708_gpio_driver); ++} ++ ++static void __exit bcm2708_gpio_exit(void) ++{ ++ platform_driver_unregister(&bcm2708_gpio_driver); ++} ++ ++module_init(bcm2708_gpio_init); ++module_exit(bcm2708_gpio_exit); ++ ++MODULE_DESCRIPTION("Broadcom BCM2708 GPIO driver"); ++MODULE_LICENSE("GPL"); +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/bcm2708.h linux-rpi/arch/arm/mach-bcm2708/bcm2708.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2708/bcm2708.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2708/bcm2708.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,49 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/bcm2708.h ++ * ++ * BCM2708 machine support header ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef __BCM2708_BCM2708_H ++#define __BCM2708_BCM2708_H ++ ++#include ++ ++extern void __init bcm2708_init(void); ++extern void __init bcm2708_init_irq(void); ++extern void __init bcm2708_map_io(void); ++extern struct sys_timer bcm2708_timer; ++extern unsigned int mmc_status(struct device *dev); ++ ++#define AMBA_DEVICE(name, busid, base, plat) \ ++static struct amba_device name##_device = { \ ++ .dev = { \ ++ .coherent_dma_mask = ~0, \ ++ .init_name = busid, \ ++ .platform_data = plat, \ ++ }, \ ++ .res = { \ ++ .start = base##_BASE, \ ++ .end = (base##_BASE) + SZ_4K - 1,\ ++ .flags = IORESOURCE_MEM, \ ++ }, \ ++ .irq = base##_IRQ, \ ++} ++ ++#endif +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/arm_control.h linux-rpi/arch/arm/mach-bcm2708/include/mach/arm_control.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/arm_control.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2708/include/mach/arm_control.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,419 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/arm_control.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef __BCM2708_ARM_CONTROL_H ++#define __BCM2708_ARM_CONTROL_H ++ ++/* ++ * Definitions and addresses for the ARM CONTROL logic ++ * This file is manually generated. ++ */ ++ ++#define ARM_BASE 0x7E00B000 ++ ++/* Basic configuration */ ++#define ARM_CONTROL0 HW_REGISTER_RW(ARM_BASE+0x000) ++#define ARM_C0_SIZ128M 0x00000000 ++#define ARM_C0_SIZ256M 0x00000001 ++#define ARM_C0_SIZ512M 0x00000002 ++#define ARM_C0_SIZ1G 0x00000003 ++#define ARM_C0_BRESP0 0x00000000 ++#define ARM_C0_BRESP1 0x00000004 ++#define ARM_C0_BRESP2 0x00000008 ++#define ARM_C0_BOOTHI 0x00000010 ++#define ARM_C0_UNUSED05 0x00000020 /* free */ ++#define ARM_C0_FULLPERI 0x00000040 ++#define ARM_C0_UNUSED78 0x00000180 /* free */ ++#define ARM_C0_JTAGMASK 0x00000E00 ++#define ARM_C0_JTAGOFF 0x00000000 ++#define ARM_C0_JTAGBASH 0x00000800 /* Debug on GPIO off */ ++#define ARM_C0_JTAGGPIO 0x00000C00 /* Debug on GPIO on */ ++#define ARM_C0_APROTMSK 0x0000F000 ++#define ARM_C0_DBG0SYNC 0x00010000 /* VPU0 halt sync */ ++#define ARM_C0_DBG1SYNC 0x00020000 /* VPU1 halt sync */ ++#define ARM_C0_SWDBGREQ 0x00040000 /* HW debug request */ ++#define ARM_C0_PASSHALT 0x00080000 /* ARM halt passed to debugger */ ++#define ARM_C0_PRIO_PER 0x00F00000 /* per priority mask */ ++#define ARM_C0_PRIO_L2 0x0F000000 ++#define ARM_C0_PRIO_UC 0xF0000000 ++ ++#define ARM_C0_APROTPASS 0x0000A000 /* Translate 1:1 */ ++#define ARM_C0_APROTUSER 0x00000000 /* Only user mode */ ++#define ARM_C0_APROTSYST 0x0000F000 /* Only system mode */ ++ ++ ++#define ARM_CONTROL1 HW_REGISTER_RW(ARM_BASE+0x440) ++#define ARM_C1_TIMER 0x00000001 /* re-route timer IRQ to VC */ ++#define ARM_C1_MAIL 0x00000002 /* re-route Mail IRQ to VC */ ++#define ARM_C1_BELL0 0x00000004 /* re-route Doorbell 0 to VC */ ++#define ARM_C1_BELL1 0x00000008 /* re-route Doorbell 1 to VC */ ++#define ARM_C1_PERSON 0x00000100 /* peripherals on */ ++#define ARM_C1_REQSTOP 0x00000200 /* ASYNC bridge request stop */ ++ ++#define ARM_STATUS HW_REGISTER_RW(ARM_BASE+0x444) ++#define ARM_S_ACKSTOP 0x80000000 /* Bridge stopped */ ++#define ARM_S_READPEND 0x000003FF /* pending reads counter */ ++#define ARM_S_WRITPEND 0x000FFC00 /* pending writes counter */ ++ ++#define ARM_ERRHALT HW_REGISTER_RW(ARM_BASE+0x448) ++#define ARM_EH_PERIBURST 0x00000001 /* Burst write seen on peri bus */ ++#define ARM_EH_ILLADDRS1 0x00000002 /* Address bits 25-27 error */ ++#define ARM_EH_ILLADDRS2 0x00000004 /* Address bits 31-28 error */ ++#define ARM_EH_VPU0HALT 0x00000008 /* VPU0 halted & in debug mode */ ++#define ARM_EH_VPU1HALT 0x00000010 /* VPU1 halted & in debug mode */ ++#define ARM_EH_ARMHALT 0x00000020 /* ARM in halted debug mode */ ++ ++#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C) ++#define ARM_ID HW_REGISTER_RW(ARM_BASE+0x44C) ++#define ARM_IDVAL 0x364D5241 ++ ++/* Translation memory */ ++#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100) ++/* 32 locations: 0x100.. 0x17F */ ++/* 32 spare means we CAN go to 64 pages.... */ ++ ++ ++/* Interrupts */ ++#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200) /* Top IRQ bits */ ++#define ARM_I0_TIMER 0x00000001 /* timer IRQ */ ++#define ARM_I0_MAIL 0x00000002 /* Mail IRQ */ ++#define ARM_I0_BELL0 0x00000004 /* Doorbell 0 */ ++#define ARM_I0_BELL1 0x00000008 /* Doorbell 1 */ ++#define ARM_I0_BANK1 0x00000100 /* Bank1 IRQ */ ++#define ARM_I0_BANK2 0x00000200 /* Bank2 IRQ */ ++ ++#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) /* All bank1 IRQ bits */ ++/* todo: all I1_interrupt sources */ ++#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) /* All bank2 IRQ bits */ ++/* todo: all I2_interrupt sources */ ++ ++#define ARM_IRQ_FAST HW_REGISTER_RW(ARM_BASE+0x20C) /* FIQ control */ ++#define ARM_IF_INDEX 0x0000007F /* FIQ select */ ++#define ARM_IF_ENABLE 0x00000080 /* FIQ enable */ ++#define ARM_IF_VCMASK 0x0000003F /* FIQ = (index from VC source) */ ++#define ARM_IF_TIMER 0x00000040 /* FIQ = ARM timer */ ++#define ARM_IF_MAIL 0x00000041 /* FIQ = ARM Mail */ ++#define ARM_IF_BELL0 0x00000042 /* FIQ = ARM Doorbell 0 */ ++#define ARM_IF_BELL1 0x00000043 /* FIQ = ARM Doorbell 1 */ ++#define ARM_IF_VP0HALT 0x00000044 /* FIQ = VPU0 Halt seen */ ++#define ARM_IF_VP1HALT 0x00000045 /* FIQ = VPU1 Halt seen */ ++#define ARM_IF_ILLEGAL 0x00000046 /* FIQ = Illegal access seen */ ++ ++#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) /* Bank1 enable bits */ ++#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) /* Bank2 enable bits */ ++#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) /* ARM irqs enable bits */ ++#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) /* Bank1 disable bits */ ++#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) /* Bank2 disable bits */ ++#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) /* ARM irqs disable bits */ ++#define ARM_IE_TIMER 0x00000001 /* Timer IRQ */ ++#define ARM_IE_MAIL 0x00000002 /* Mail IRQ */ ++#define ARM_IE_BELL0 0x00000004 /* Doorbell 0 */ ++#define ARM_IE_BELL1 0x00000008 /* Doorbell 1 */ ++#define ARM_IE_VP0HALT 0x00000010 /* VPU0 Halt */ ++#define ARM_IE_VP1HALT 0x00000020 /* VPU1 Halt */ ++#define ARM_IE_ILLEGAL 0x00000040 /* Illegal access seen */ ++ ++/* Timer */ ++/* For reg. fields see sp804 spec. */ ++#define ARM_T_LOAD HW_REGISTER_RW(ARM_BASE+0x400) ++#define ARM_T_VALUE HW_REGISTER_RW(ARM_BASE+0x404) ++#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408) ++#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C) ++#define ARM_T_RAWIRQ HW_REGISTER_RW(ARM_BASE+0x410) ++#define ARM_T_MSKIRQ HW_REGISTER_RW(ARM_BASE+0x414) ++#define ARM_T_RELOAD HW_REGISTER_RW(ARM_BASE+0x418) ++#define ARM_T_PREDIV HW_REGISTER_RW(ARM_BASE+0x41c) ++#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420) ++ ++#define TIMER_CTRL_ONESHOT (1 << 0) ++#define TIMER_CTRL_32BIT (1 << 1) ++#define TIMER_CTRL_DIV1 (0 << 2) ++#define TIMER_CTRL_DIV16 (1 << 2) ++#define TIMER_CTRL_DIV256 (2 << 2) ++#define TIMER_CTRL_IE (1 << 5) ++#define TIMER_CTRL_PERIODIC (1 << 6) ++#define TIMER_CTRL_ENABLE (1 << 7) ++#define TIMER_CTRL_DBGHALT (1 << 8) ++#define TIMER_CTRL_ENAFREE (1 << 9) ++#define TIMER_CTRL_FREEDIV_SHIFT 16) ++#define TIMER_CTRL_FREEDIV_MASK 0xff ++ ++/* Semaphores, Doorbells, Mailboxes */ ++#define ARM_SBM_OWN0 (ARM_BASE+0x800) ++#define ARM_SBM_OWN1 (ARM_BASE+0x900) ++#define ARM_SBM_OWN2 (ARM_BASE+0xA00) ++#define ARM_SBM_OWN3 (ARM_BASE+0xB00) ++ ++/* MAILBOXES ++ * Register flags are common across all ++ * owner registers. See end of this section ++ * ++ * Semaphores, Doorbells, Mailboxes Owner 0 ++ * ++ */ ++ ++#define ARM_0_SEMS HW_REGISTER_RW(ARM_SBM_OWN0+0x00) ++#define ARM_0_SEM0 HW_REGISTER_RW(ARM_SBM_OWN0+0x00) ++#define ARM_0_SEM1 HW_REGISTER_RW(ARM_SBM_OWN0+0x04) ++#define ARM_0_SEM2 HW_REGISTER_RW(ARM_SBM_OWN0+0x08) ++#define ARM_0_SEM3 HW_REGISTER_RW(ARM_SBM_OWN0+0x0C) ++#define ARM_0_SEM4 HW_REGISTER_RW(ARM_SBM_OWN0+0x10) ++#define ARM_0_SEM5 HW_REGISTER_RW(ARM_SBM_OWN0+0x14) ++#define ARM_0_SEM6 HW_REGISTER_RW(ARM_SBM_OWN0+0x18) ++#define ARM_0_SEM7 HW_REGISTER_RW(ARM_SBM_OWN0+0x1C) ++#define ARM_0_BELL0 HW_REGISTER_RW(ARM_SBM_OWN0+0x40) ++#define ARM_0_BELL1 HW_REGISTER_RW(ARM_SBM_OWN0+0x44) ++#define ARM_0_BELL2 HW_REGISTER_RW(ARM_SBM_OWN0+0x48) ++#define ARM_0_BELL3 HW_REGISTER_RW(ARM_SBM_OWN0+0x4C) ++/* MAILBOX 0 access in Owner 0 area */ ++/* Some addresses should ONLY be used by owner 0 */ ++#define ARM_0_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) */ ++#define ARM_0_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) Normal read */ ++#define ARM_0_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN0+0x90) /* none-pop read */ ++#define ARM_0_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN0+0x94) /* Sender read (only LS 2 bits) */ ++#define ARM_0_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN0+0x98) /* Status read */ ++#define ARM_0_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0x9C) /* Config read/write */ ++/* MAILBOX 1 access in Owner 0 area */ ++/* Owner 0 should only WRITE to this mailbox */ ++#define ARM_0_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) /* .. 0xAC (4 locations) */ ++/*#define ARM_0_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_0_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_0_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) */ /* DO NOT USE THIS !!!!! */ ++#define ARM_0_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN0+0xB8) /* Status read */ ++/*#define ARM_0_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) */ /* DO NOT USE THIS !!!!! */ ++/* General SEM, BELL, MAIL config/status */ ++#define ARM_0_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE0) /* semaphore clear/debug register */ ++#define ARM_0_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE4) /* Doorbells clear/debug register */ ++#define ARM_0_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xF8) /* ALL interrupts */ ++#define ARM_0_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xFC) /* IRQS pending for owner 0 */ ++ ++/* Semaphores, Doorbells, Mailboxes Owner 1 */ ++#define ARM_1_SEMS HW_REGISTER_RW(ARM_SBM_OWN1+0x00) ++#define ARM_1_SEM0 HW_REGISTER_RW(ARM_SBM_OWN1+0x00) ++#define ARM_1_SEM1 HW_REGISTER_RW(ARM_SBM_OWN1+0x04) ++#define ARM_1_SEM2 HW_REGISTER_RW(ARM_SBM_OWN1+0x08) ++#define ARM_1_SEM3 HW_REGISTER_RW(ARM_SBM_OWN1+0x0C) ++#define ARM_1_SEM4 HW_REGISTER_RW(ARM_SBM_OWN1+0x10) ++#define ARM_1_SEM5 HW_REGISTER_RW(ARM_SBM_OWN1+0x14) ++#define ARM_1_SEM6 HW_REGISTER_RW(ARM_SBM_OWN1+0x18) ++#define ARM_1_SEM7 HW_REGISTER_RW(ARM_SBM_OWN1+0x1C) ++#define ARM_1_BELL0 HW_REGISTER_RW(ARM_SBM_OWN1+0x40) ++#define ARM_1_BELL1 HW_REGISTER_RW(ARM_SBM_OWN1+0x44) ++#define ARM_1_BELL2 HW_REGISTER_RW(ARM_SBM_OWN1+0x48) ++#define ARM_1_BELL3 HW_REGISTER_RW(ARM_SBM_OWN1+0x4C) ++/* MAILBOX 0 access in Owner 0 area */ ++/* Owner 1 should only WRITE to this mailbox */ ++#define ARM_1_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0x80) /* .. 0x8C (4 locations) */ ++/*#define ARM_1_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN1+0x80) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) */ /* DO NOT USE THIS !!!!! */ ++#define ARM_1_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN1+0x98) /* Status read */ ++/*#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) */ /* DO NOT USE THIS !!!!! */ ++/* MAILBOX 1 access in Owner 0 area */ ++#define ARM_1_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) */ ++#define ARM_1_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) Normal read */ ++#define ARM_1_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN1+0xB0) /* none-pop read */ ++#define ARM_1_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN1+0xB4) /* Sender read (only LS 2 bits) */ ++#define ARM_1_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN1+0xB8) /* Status read */ ++#define ARM_1_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0xBC) ++/* General SEM, BELL, MAIL config/status */ ++#define ARM_1_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE0) /* semaphore clear/debug register */ ++#define ARM_1_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE4) /* Doorbells clear/debug register */ ++#define ARM_1_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xFC) /* IRQS pending for owner 1 */ ++#define ARM_1_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xF8) /* ALL interrupts */ ++ ++/* Semaphores, Doorbells, Mailboxes Owner 2 */ ++#define ARM_2_SEMS HW_REGISTER_RW(ARM_SBM_OWN2+0x00) ++#define ARM_2_SEM0 HW_REGISTER_RW(ARM_SBM_OWN2+0x00) ++#define ARM_2_SEM1 HW_REGISTER_RW(ARM_SBM_OWN2+0x04) ++#define ARM_2_SEM2 HW_REGISTER_RW(ARM_SBM_OWN2+0x08) ++#define ARM_2_SEM3 HW_REGISTER_RW(ARM_SBM_OWN2+0x0C) ++#define ARM_2_SEM4 HW_REGISTER_RW(ARM_SBM_OWN2+0x10) ++#define ARM_2_SEM5 HW_REGISTER_RW(ARM_SBM_OWN2+0x14) ++#define ARM_2_SEM6 HW_REGISTER_RW(ARM_SBM_OWN2+0x18) ++#define ARM_2_SEM7 HW_REGISTER_RW(ARM_SBM_OWN2+0x1C) ++#define ARM_2_BELL0 HW_REGISTER_RW(ARM_SBM_OWN2+0x40) ++#define ARM_2_BELL1 HW_REGISTER_RW(ARM_SBM_OWN2+0x44) ++#define ARM_2_BELL2 HW_REGISTER_RW(ARM_SBM_OWN2+0x48) ++#define ARM_2_BELL3 HW_REGISTER_RW(ARM_SBM_OWN2+0x4C) ++/* MAILBOX 0 access in Owner 2 area */ ++/* Owner 2 should only WRITE to this mailbox */ ++#define ARM_2_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0x80) /* .. 0x8C (4 locations) */ ++/*#define ARM_2_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN2+0x80) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94) */ /* DO NOT USE THIS !!!!! */ ++#define ARM_2_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN2+0x98) /* Status read */ ++/*#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C) */ /* DO NOT USE THIS !!!!! */ ++/* MAILBOX 1 access in Owner 2 area */ ++/* Owner 2 should only WRITE to this mailbox */ ++#define ARM_2_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) /* .. 0xAC (4 locations) */ ++/*#define ARM_2_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_2_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_2_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) */ /* DO NOT USE THIS !!!!! */ ++#define ARM_2_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN2+0xB8) /* Status read */ ++/*#define ARM_2_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) */ /* DO NOT USE THIS !!!!! */ ++/* General SEM, BELL, MAIL config/status */ ++#define ARM_2_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE0) /* semaphore clear/debug register */ ++#define ARM_2_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE4) /* Doorbells clear/debug register */ ++#define ARM_2_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xFC) /* IRQS pending for owner 2 */ ++#define ARM_2_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xF8) /* ALL interrupts */ ++ ++/* Semaphores, Doorbells, Mailboxes Owner 3 */ ++#define ARM_3_SEMS HW_REGISTER_RW(ARM_SBM_OWN3+0x00) ++#define ARM_3_SEM0 HW_REGISTER_RW(ARM_SBM_OWN3+0x00) ++#define ARM_3_SEM1 HW_REGISTER_RW(ARM_SBM_OWN3+0x04) ++#define ARM_3_SEM2 HW_REGISTER_RW(ARM_SBM_OWN3+0x08) ++#define ARM_3_SEM3 HW_REGISTER_RW(ARM_SBM_OWN3+0x0C) ++#define ARM_3_SEM4 HW_REGISTER_RW(ARM_SBM_OWN3+0x10) ++#define ARM_3_SEM5 HW_REGISTER_RW(ARM_SBM_OWN3+0x14) ++#define ARM_3_SEM6 HW_REGISTER_RW(ARM_SBM_OWN3+0x18) ++#define ARM_3_SEM7 HW_REGISTER_RW(ARM_SBM_OWN3+0x1C) ++#define ARM_3_BELL0 HW_REGISTER_RW(ARM_SBM_OWN3+0x40) ++#define ARM_3_BELL1 HW_REGISTER_RW(ARM_SBM_OWN3+0x44) ++#define ARM_3_BELL2 HW_REGISTER_RW(ARM_SBM_OWN3+0x48) ++#define ARM_3_BELL3 HW_REGISTER_RW(ARM_SBM_OWN3+0x4C) ++/* MAILBOX 0 access in Owner 3 area */ ++/* Owner 3 should only WRITE to this mailbox */ ++#define ARM_3_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0x80) /* .. 0x8C (4 locations) */ ++/*#define ARM_3_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN3+0x80) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94) */ /* DO NOT USE THIS !!!!! */ ++#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98) /* Status read */ ++/*#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C) */ /* DO NOT USE THIS !!!!! */ ++/* MAILBOX 1 access in Owner 3 area */ ++/* Owner 3 should only WRITE to this mailbox */ ++#define ARM_3_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) /* .. 0xAC (4 locations) */ ++/*#define ARM_3_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_3_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_3_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) */ /* DO NOT USE THIS !!!!! */ ++#define ARM_3_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN3+0xB8) /* Status read */ ++/*#define ARM_3_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) */ /* DO NOT USE THIS !!!!! */ ++/* General SEM, BELL, MAIL config/status */ ++#define ARM_3_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE0) /* semaphore clear/debug register */ ++#define ARM_3_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE4) /* Doorbells clear/debug register */ ++#define ARM_3_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xFC) /* IRQS pending for owner 3 */ ++#define ARM_3_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xF8) /* ALL interrupts */ ++ ++ ++ ++/* Mailbox flags. Valid for all owners */ ++ ++/* Mailbox status register (...0x98) */ ++#define ARM_MS_FULL 0x80000000 ++#define ARM_MS_EMPTY 0x40000000 ++#define ARM_MS_LEVEL 0x400000FF /* Max. value depdnds on mailbox depth parameter */ ++ ++/* MAILBOX config/status register (...0x9C) */ ++/* ANY write to this register clears the error bits! */ ++#define ARM_MC_IHAVEDATAIRQEN 0x00000001 /* mailbox irq enable: has data */ ++#define ARM_MC_IHAVESPACEIRQEN 0x00000002 /* mailbox irq enable: has space */ ++#define ARM_MC_OPPISEMPTYIRQEN 0x00000004 /* mailbox irq enable: Opp. is empty */ ++#define ARM_MC_MAIL_CLEAR 0x00000008 /* mailbox clear write 1, then 0 */ ++#define ARM_MC_IHAVEDATAIRQPEND 0x00000010 /* mailbox irq pending: has space */ ++#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mailbox irq pending: Opp. is empty */ ++#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mailbox irq pending */ ++/* Bit 7 is unused */ ++#define ARM_MC_ERRNOOWN 0x00000100 /* error : none owner read from mailbox */ ++#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */ ++#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */ ++ ++/* Semaphore clear/debug register (...0xE0) */ ++#define ARM_SD_OWN0 0x00000003 /* Owner of sem 0 */ ++#define ARM_SD_OWN1 0x0000000C /* Owner of sem 1 */ ++#define ARM_SD_OWN2 0x00000030 /* Owner of sem 2 */ ++#define ARM_SD_OWN3 0x000000C0 /* Owner of sem 3 */ ++#define ARM_SD_OWN4 0x00000300 /* Owner of sem 4 */ ++#define ARM_SD_OWN5 0x00000C00 /* Owner of sem 5 */ ++#define ARM_SD_OWN6 0x00003000 /* Owner of sem 6 */ ++#define ARM_SD_OWN7 0x0000C000 /* Owner of sem 7 */ ++#define ARM_SD_SEM0 0x00010000 /* Status of sem 0 */ ++#define ARM_SD_SEM1 0x00020000 /* Status of sem 1 */ ++#define ARM_SD_SEM2 0x00040000 /* Status of sem 2 */ ++#define ARM_SD_SEM3 0x00080000 /* Status of sem 3 */ ++#define ARM_SD_SEM4 0x00100000 /* Status of sem 4 */ ++#define ARM_SD_SEM5 0x00200000 /* Status of sem 5 */ ++#define ARM_SD_SEM6 0x00400000 /* Status of sem 6 */ ++#define ARM_SD_SEM7 0x00800000 /* Status of sem 7 */ ++ ++/* Doorbells clear/debug register (...0xE4) */ ++#define ARM_BD_OWN0 0x00000003 /* Owner of doorbell 0 */ ++#define ARM_BD_OWN1 0x0000000C /* Owner of doorbell 1 */ ++#define ARM_BD_OWN2 0x00000030 /* Owner of doorbell 2 */ ++#define ARM_BD_OWN3 0x000000C0 /* Owner of doorbell 3 */ ++#define ARM_BD_BELL0 0x00000100 /* Status of doorbell 0 */ ++#define ARM_BD_BELL1 0x00000200 /* Status of doorbell 1 */ ++#define ARM_BD_BELL2 0x00000400 /* Status of doorbell 2 */ ++#define ARM_BD_BELL3 0x00000800 /* Status of doorbell 3 */ ++ ++/* MY IRQS register (...0xF8) */ ++#define ARM_MYIRQ_BELL 0x00000001 /* This owner has a doorbell IRQ */ ++#define ARM_MYIRQ_MAIL 0x00000002 /* This owner has a mailbox IRQ */ ++ ++/* ALL IRQS register (...0xF8) */ ++#define ARM_AIS_BELL0 0x00000001 /* Doorbell 0 IRQ pending */ ++#define ARM_AIS_BELL1 0x00000002 /* Doorbell 1 IRQ pending */ ++#define ARM_AIS_BELL2 0x00000004 /* Doorbell 2 IRQ pending */ ++#define ARM_AIS_BELL3 0x00000008 /* Doorbell 3 IRQ pending */ ++#define ARM_AIS0_HAVEDATA 0x00000010 /* MAIL 0 has data IRQ pending */ ++#define ARM_AIS0_HAVESPAC 0x00000020 /* MAIL 0 has space IRQ pending */ ++#define ARM_AIS0_OPPEMPTY 0x00000040 /* MAIL 0 opposite is empty IRQ */ ++#define ARM_AIS1_HAVEDATA 0x00000080 /* MAIL 1 has data IRQ pending */ ++#define ARM_AIS1_HAVESPAC 0x00000100 /* MAIL 1 has space IRQ pending */ ++#define ARM_AIS1_OPPEMPTY 0x00000200 /* MAIL 1 opposite is empty IRQ */ ++/* Note that bell-0, bell-1 and MAIL0 IRQ go only to the ARM */ ++/* Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC */ ++/* */ ++/* ARM JTAG BASH */ ++/* */ ++#define AJB_BASE 0x7e2000c0 ++ ++#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00) ++#define AJB_BITS0 0x000000 ++#define AJB_BITS4 0x000004 ++#define AJB_BITS8 0x000008 ++#define AJB_BITS12 0x00000C ++#define AJB_BITS16 0x000010 ++#define AJB_BITS20 0x000014 ++#define AJB_BITS24 0x000018 ++#define AJB_BITS28 0x00001C ++#define AJB_BITS32 0x000020 ++#define AJB_BITS34 0x000022 ++#define AJB_OUT_MS 0x000040 ++#define AJB_OUT_LS 0x000000 ++#define AJB_INV_CLK 0x000080 ++#define AJB_D0_RISE 0x000100 ++#define AJB_D0_FALL 0x000000 ++#define AJB_D1_RISE 0x000200 ++#define AJB_D1_FALL 0x000000 ++#define AJB_IN_RISE 0x000400 ++#define AJB_IN_FALL 0x000000 ++#define AJB_ENABLE 0x000800 ++#define AJB_HOLD0 0x000000 ++#define AJB_HOLD1 0x001000 ++#define AJB_HOLD2 0x002000 ++#define AJB_HOLD3 0x003000 ++#define AJB_RESETN 0x004000 ++#define AJB_CLKSHFT 16 ++#define AJB_BUSY 0x80000000 ++#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04) ++#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08) ++#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c) ++ ++#endif +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/clkdev.h linux-rpi/arch/arm/mach-bcm2708/include/mach/clkdev.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/clkdev.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2708/include/mach/clkdev.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,7 @@ ++#ifndef __ASM_MACH_CLKDEV_H ++#define __ASM_MACH_CLKDEV_H ++ ++#define __clk_get(clk) ({ 1; }) ++#define __clk_put(clk) do { } while (0) ++ ++#endif +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/debug-macro.S linux-rpi/arch/arm/mach-bcm2708/include/mach/debug-macro.S +--- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/debug-macro.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2708/include/mach/debug-macro.S 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,22 @@ ++/* arch/arm/mach-bcm2708/include/mach/debug-macro.S ++ * ++ * Debugging macro include header ++ * ++ * Copyright (C) 2010 Broadcom ++ * Copyright (C) 1994-1999 Russell King ++ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++*/ ++ ++#include ++ ++ .macro addruart, rp, rv, tmp ++ ldr \rp, =UART0_BASE ++ ldr \rv, =IO_ADDRESS(UART0_BASE) ++ .endm ++ ++#include +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/entry-macro.S linux-rpi/arch/arm/mach-bcm2708/include/mach/entry-macro.S +--- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/entry-macro.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2708/include/mach/entry-macro.S 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,69 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/entry-macro.S ++ * ++ * Low-level IRQ helper macros for BCM2708 platforms ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#include ++ ++ .macro disable_fiq ++ .endm ++ ++ .macro get_irqnr_preamble, base, tmp ++ ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE) ++ .endm ++ ++ .macro arch_ret_to_user, tmp1, tmp2 ++ .endm ++ ++ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp ++ /* get masked status */ ++ ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)] ++ mov \irqnr, #(ARM_IRQ0_BASE + 31) ++ and \tmp, \irqstat, #0x300 @ save bits 8 and 9 ++ /* clear bits 8 and 9, and test */ ++ bics \irqstat, \irqstat, #0x300 ++ bne 1010f ++ ++ tst \tmp, #0x100 ++ ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)] ++ movne \irqnr, #(ARM_IRQ1_BASE + 31) ++ @ Mask out the interrupts also present in PEND0 - see SW-5809 ++ bicne \irqstat, #((1<<7) | (1<<9) | (1<<10)) ++ bicne \irqstat, #((1<<18) | (1<<19)) ++ bne 1010f ++ ++ tst \tmp, #0x200 ++ ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)] ++ movne \irqnr, #(ARM_IRQ2_BASE + 31) ++ @ Mask out the interrupts also present in PEND0 - see SW-5809 ++ bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25)) ++ bicne \irqstat, #((1<<30)) ++ beq 1020f ++ ++1010: ++ @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1)) ++ @ N.B. CLZ is an ARM5 instruction. ++ sub \tmp, \irqstat, #1 ++ eor \irqstat, \irqstat, \tmp ++ clz \tmp, \irqstat ++ sub \irqnr, \tmp ++ ++1020: @ EQ will be set if no irqs pending ++ ++ .endm +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/frc.h linux-rpi/arch/arm/mach-bcm2708/include/mach/frc.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/frc.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2708/include/mach/frc.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,38 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/timex.h ++ * ++ * BCM2708 free running counter (timer) ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef _MACH_FRC_H ++#define _MACH_FRC_H ++ ++#define FRC_TICK_RATE (1000000) ++ ++/*! Free running counter incrementing at the CLOCK_TICK_RATE ++ (slightly faster than frc_clock_ticks63() ++ */ ++extern unsigned long frc_clock_ticks32(void); ++ ++/*! Free running counter incrementing at the CLOCK_TICK_RATE ++ * Note - top bit should be ignored (see cnt32_to_63) ++ */ ++extern unsigned long long frc_clock_ticks63(void); ++ ++#endif +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/gpio.h linux-rpi/arch/arm/mach-bcm2708/include/mach/gpio.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/gpio.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2708/include/mach/gpio.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,17 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/gpio.h ++ * ++ * This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without any ++ * warranty of any kind, whether express or implied. ++ */ ++ ++#ifndef __ASM_ARCH_GPIO_H ++#define __ASM_ARCH_GPIO_H ++ ++#define BCM2708_NR_GPIOS 54 // number of gpio lines ++ ++#define gpio_to_irq(x) ((x) + GPIO_IRQ_START) ++#define irq_to_gpio(x) ((x) - GPIO_IRQ_START) ++ ++#endif +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/hardware.h linux-rpi/arch/arm/mach-bcm2708/include/mach/hardware.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/hardware.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2708/include/mach/hardware.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,28 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/hardware.h ++ * ++ * This file contains the hardware definitions of the BCM2708 devices. ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#ifndef __ASM_ARCH_HARDWARE_H ++#define __ASM_ARCH_HARDWARE_H ++ ++#include ++#include ++ ++#endif +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/io.h linux-rpi/arch/arm/mach-bcm2708/include/mach/io.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/io.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2708/include/mach/io.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,27 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/io.h ++ * ++ * Copyright (C) 2003 ARM Limited ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#ifndef __ASM_ARM_ARCH_IO_H ++#define __ASM_ARM_ARCH_IO_H ++ ++#define IO_SPACE_LIMIT 0xffffffff ++ ++#define __io(a) __typesafe_io(a) ++ ++#endif +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/irqs.h linux-rpi/arch/arm/mach-bcm2708/include/mach/irqs.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/irqs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2708/include/mach/irqs.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,199 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/irqs.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * Copyright (C) 2003 ARM Limited ++ * Copyright (C) 2000 Deep Blue Solutions Ltd. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef _BCM2708_IRQS_H_ ++#define _BCM2708_IRQS_H_ ++ ++#include ++ ++/* ++ * IRQ interrupts definitions are the same as the INT definitions ++ * held within platform.h ++ */ ++#define IRQ_ARMCTRL_START 0 ++#define IRQ_TIMER0 (IRQ_ARMCTRL_START + INTERRUPT_TIMER0) ++#define IRQ_TIMER1 (IRQ_ARMCTRL_START + INTERRUPT_TIMER1) ++#define IRQ_TIMER2 (IRQ_ARMCTRL_START + INTERRUPT_TIMER2) ++#define IRQ_TIMER3 (IRQ_ARMCTRL_START + INTERRUPT_TIMER3) ++#define IRQ_CODEC0 (IRQ_ARMCTRL_START + INTERRUPT_CODEC0) ++#define IRQ_CODEC1 (IRQ_ARMCTRL_START + INTERRUPT_CODEC1) ++#define IRQ_CODEC2 (IRQ_ARMCTRL_START + INTERRUPT_CODEC2) ++#define IRQ_JPEG (IRQ_ARMCTRL_START + INTERRUPT_JPEG) ++#define IRQ_ISP (IRQ_ARMCTRL_START + INTERRUPT_ISP) ++#define IRQ_USB (IRQ_ARMCTRL_START + INTERRUPT_USB) ++#define IRQ_3D (IRQ_ARMCTRL_START + INTERRUPT_3D) ++#define IRQ_TRANSPOSER (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER) ++#define IRQ_MULTICORESYNC0 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0) ++#define IRQ_MULTICORESYNC1 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1) ++#define IRQ_MULTICORESYNC2 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2) ++#define IRQ_MULTICORESYNC3 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3) ++#define IRQ_DMA0 (IRQ_ARMCTRL_START + INTERRUPT_DMA0) ++#define IRQ_DMA1 (IRQ_ARMCTRL_START + INTERRUPT_DMA1) ++#define IRQ_DMA2 (IRQ_ARMCTRL_START + INTERRUPT_DMA2) ++#define IRQ_DMA3 (IRQ_ARMCTRL_START + INTERRUPT_DMA3) ++#define IRQ_DMA4 (IRQ_ARMCTRL_START + INTERRUPT_DMA4) ++#define IRQ_DMA5 (IRQ_ARMCTRL_START + INTERRUPT_DMA5) ++#define IRQ_DMA6 (IRQ_ARMCTRL_START + INTERRUPT_DMA6) ++#define IRQ_DMA7 (IRQ_ARMCTRL_START + INTERRUPT_DMA7) ++#define IRQ_DMA8 (IRQ_ARMCTRL_START + INTERRUPT_DMA8) ++#define IRQ_DMA9 (IRQ_ARMCTRL_START + INTERRUPT_DMA9) ++#define IRQ_DMA10 (IRQ_ARMCTRL_START + INTERRUPT_DMA10) ++#define IRQ_DMA11 (IRQ_ARMCTRL_START + INTERRUPT_DMA11) ++#define IRQ_DMA12 (IRQ_ARMCTRL_START + INTERRUPT_DMA12) ++#define IRQ_AUX (IRQ_ARMCTRL_START + INTERRUPT_AUX) ++#define IRQ_ARM (IRQ_ARMCTRL_START + INTERRUPT_ARM) ++#define IRQ_VPUDMA (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA) ++#define IRQ_HOSTPORT (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT) ++#define IRQ_VIDEOSCALER (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER) ++#define IRQ_CCP2TX (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX) ++#define IRQ_SDC (IRQ_ARMCTRL_START + INTERRUPT_SDC) ++#define IRQ_DSI0 (IRQ_ARMCTRL_START + INTERRUPT_DSI0) ++#define IRQ_AVE (IRQ_ARMCTRL_START + INTERRUPT_AVE) ++#define IRQ_CAM0 (IRQ_ARMCTRL_START + INTERRUPT_CAM0) ++#define IRQ_CAM1 (IRQ_ARMCTRL_START + INTERRUPT_CAM1) ++#define IRQ_HDMI0 (IRQ_ARMCTRL_START + INTERRUPT_HDMI0) ++#define IRQ_HDMI1 (IRQ_ARMCTRL_START + INTERRUPT_HDMI1) ++#define IRQ_PIXELVALVE1 (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1) ++#define IRQ_I2CSPISLV (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV) ++#define IRQ_DSI1 (IRQ_ARMCTRL_START + INTERRUPT_DSI1) ++#define IRQ_PWA0 (IRQ_ARMCTRL_START + INTERRUPT_PWA0) ++#define IRQ_PWA1 (IRQ_ARMCTRL_START + INTERRUPT_PWA1) ++#define IRQ_CPR (IRQ_ARMCTRL_START + INTERRUPT_CPR) ++#define IRQ_SMI (IRQ_ARMCTRL_START + INTERRUPT_SMI) ++#define IRQ_GPIO0 (IRQ_ARMCTRL_START + INTERRUPT_GPIO0) ++#define IRQ_GPIO1 (IRQ_ARMCTRL_START + INTERRUPT_GPIO1) ++#define IRQ_GPIO2 (IRQ_ARMCTRL_START + INTERRUPT_GPIO2) ++#define IRQ_GPIO3 (IRQ_ARMCTRL_START + INTERRUPT_GPIO3) ++#define IRQ_I2C (IRQ_ARMCTRL_START + INTERRUPT_I2C) ++#define IRQ_SPI (IRQ_ARMCTRL_START + INTERRUPT_SPI) ++#define IRQ_I2SPCM (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM) ++#define IRQ_SDIO (IRQ_ARMCTRL_START + INTERRUPT_SDIO) ++#define IRQ_UART (IRQ_ARMCTRL_START + INTERRUPT_UART) ++#define IRQ_SLIMBUS (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS) ++#define IRQ_VEC (IRQ_ARMCTRL_START + INTERRUPT_VEC) ++#define IRQ_CPG (IRQ_ARMCTRL_START + INTERRUPT_CPG) ++#define IRQ_RNG (IRQ_ARMCTRL_START + INTERRUPT_RNG) ++#define IRQ_ARASANSDIO (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO) ++#define IRQ_AVSPMON (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON) ++ ++#define IRQ_ARM_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER) ++#define IRQ_ARM_MAILBOX (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX) ++#define IRQ_ARM_DOORBELL_0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0) ++#define IRQ_ARM_DOORBELL_1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1) ++#define IRQ_VPU0_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED) ++#define IRQ_VPU1_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED) ++#define IRQ_ILLEGAL_TYPE0 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0) ++#define IRQ_ILLEGAL_TYPE1 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1) ++#define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1) ++#define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2) ++ ++#define FIQ_START HARD_IRQS ++ ++/* ++ * FIQ interrupts definitions are the same as the INT definitions. ++ */ ++#define FIQ_TIMER0 (FIQ_START+INTERRUPT_TIMER0) ++#define FIQ_TIMER1 (FIQ_START+INTERRUPT_TIMER1) ++#define FIQ_TIMER2 (FIQ_START+INTERRUPT_TIMER2) ++#define FIQ_TIMER3 (FIQ_START+INTERRUPT_TIMER3) ++#define FIQ_CODEC0 (FIQ_START+INTERRUPT_CODEC0) ++#define FIQ_CODEC1 (FIQ_START+INTERRUPT_CODEC1) ++#define FIQ_CODEC2 (FIQ_START+INTERRUPT_CODEC2) ++#define FIQ_JPEG (FIQ_START+INTERRUPT_JPEG) ++#define FIQ_ISP (FIQ_START+INTERRUPT_ISP) ++#define FIQ_USB (FIQ_START+INTERRUPT_USB) ++#define FIQ_3D (FIQ_START+INTERRUPT_3D) ++#define FIQ_TRANSPOSER (FIQ_START+INTERRUPT_TRANSPOSER) ++#define FIQ_MULTICORESYNC0 (FIQ_START+INTERRUPT_MULTICORESYNC0) ++#define FIQ_MULTICORESYNC1 (FIQ_START+INTERRUPT_MULTICORESYNC1) ++#define FIQ_MULTICORESYNC2 (FIQ_START+INTERRUPT_MULTICORESYNC2) ++#define FIQ_MULTICORESYNC3 (FIQ_START+INTERRUPT_MULTICORESYNC3) ++#define FIQ_DMA0 (FIQ_START+INTERRUPT_DMA0) ++#define FIQ_DMA1 (FIQ_START+INTERRUPT_DMA1) ++#define FIQ_DMA2 (FIQ_START+INTERRUPT_DMA2) ++#define FIQ_DMA3 (FIQ_START+INTERRUPT_DMA3) ++#define FIQ_DMA4 (FIQ_START+INTERRUPT_DMA4) ++#define FIQ_DMA5 (FIQ_START+INTERRUPT_DMA5) ++#define FIQ_DMA6 (FIQ_START+INTERRUPT_DMA6) ++#define FIQ_DMA7 (FIQ_START+INTERRUPT_DMA7) ++#define FIQ_DMA8 (FIQ_START+INTERRUPT_DMA8) ++#define FIQ_DMA9 (FIQ_START+INTERRUPT_DMA9) ++#define FIQ_DMA10 (FIQ_START+INTERRUPT_DMA10) ++#define FIQ_DMA11 (FIQ_START+INTERRUPT_DMA11) ++#define FIQ_DMA12 (FIQ_START+INTERRUPT_DMA12) ++#define FIQ_AUX (FIQ_START+INTERRUPT_AUX) ++#define FIQ_ARM (FIQ_START+INTERRUPT_ARM) ++#define FIQ_VPUDMA (FIQ_START+INTERRUPT_VPUDMA) ++#define FIQ_HOSTPORT (FIQ_START+INTERRUPT_HOSTPORT) ++#define FIQ_VIDEOSCALER (FIQ_START+INTERRUPT_VIDEOSCALER) ++#define FIQ_CCP2TX (FIQ_START+INTERRUPT_CCP2TX) ++#define FIQ_SDC (FIQ_START+INTERRUPT_SDC) ++#define FIQ_DSI0 (FIQ_START+INTERRUPT_DSI0) ++#define FIQ_AVE (FIQ_START+INTERRUPT_AVE) ++#define FIQ_CAM0 (FIQ_START+INTERRUPT_CAM0) ++#define FIQ_CAM1 (FIQ_START+INTERRUPT_CAM1) ++#define FIQ_HDMI0 (FIQ_START+INTERRUPT_HDMI0) ++#define FIQ_HDMI1 (FIQ_START+INTERRUPT_HDMI1) ++#define FIQ_PIXELVALVE1 (FIQ_START+INTERRUPT_PIXELVALVE1) ++#define FIQ_I2CSPISLV (FIQ_START+INTERRUPT_I2CSPISLV) ++#define FIQ_DSI1 (FIQ_START+INTERRUPT_DSI1) ++#define FIQ_PWA0 (FIQ_START+INTERRUPT_PWA0) ++#define FIQ_PWA1 (FIQ_START+INTERRUPT_PWA1) ++#define FIQ_CPR (FIQ_START+INTERRUPT_CPR) ++#define FIQ_SMI (FIQ_START+INTERRUPT_SMI) ++#define FIQ_GPIO0 (FIQ_START+INTERRUPT_GPIO0) ++#define FIQ_GPIO1 (FIQ_START+INTERRUPT_GPIO1) ++#define FIQ_GPIO2 (FIQ_START+INTERRUPT_GPIO2) ++#define FIQ_GPIO3 (FIQ_START+INTERRUPT_GPIO3) ++#define FIQ_I2C (FIQ_START+INTERRUPT_I2C) ++#define FIQ_SPI (FIQ_START+INTERRUPT_SPI) ++#define FIQ_I2SPCM (FIQ_START+INTERRUPT_I2SPCM) ++#define FIQ_SDIO (FIQ_START+INTERRUPT_SDIO) ++#define FIQ_UART (FIQ_START+INTERRUPT_UART) ++#define FIQ_SLIMBUS (FIQ_START+INTERRUPT_SLIMBUS) ++#define FIQ_VEC (FIQ_START+INTERRUPT_VEC) ++#define FIQ_CPG (FIQ_START+INTERRUPT_CPG) ++#define FIQ_RNG (FIQ_START+INTERRUPT_RNG) ++#define FIQ_ARASANSDIO (FIQ_START+INTERRUPT_ARASANSDIO) ++#define FIQ_AVSPMON (FIQ_START+INTERRUPT_AVSPMON) ++ ++#define FIQ_ARM_TIMER (FIQ_START+INTERRUPT_ARM_TIMER) ++#define FIQ_ARM_MAILBOX (FIQ_START+INTERRUPT_ARM_MAILBOX) ++#define FIQ_ARM_DOORBELL_0 (FIQ_START+INTERRUPT_ARM_DOORBELL_0) ++#define FIQ_ARM_DOORBELL_1 (FIQ_START+INTERRUPT_ARM_DOORBELL_1) ++#define FIQ_VPU0_HALTED (FIQ_START+INTERRUPT_VPU0_HALTED) ++#define FIQ_VPU1_HALTED (FIQ_START+INTERRUPT_VPU1_HALTED) ++#define FIQ_ILLEGAL_TYPE0 (FIQ_START+INTERRUPT_ILLEGAL_TYPE0) ++#define FIQ_ILLEGAL_TYPE1 (FIQ_START+INTERRUPT_ILLEGAL_TYPE1) ++#define FIQ_PENDING1 (FIQ_START+INTERRUPT_PENDING1) ++#define FIQ_PENDING2 (FIQ_START+INTERRUPT_PENDING2) ++ ++#define HARD_IRQS (64 + 21) ++#define FIQ_IRQS (64 + 21) ++#define GPIO_IRQ_START (HARD_IRQS + FIQ_IRQS) ++#define GPIO_IRQS (32*5) ++#define SPARE_ALLOC_IRQS 64 ++#define BCM2708_ALLOC_IRQS (HARD_IRQS+FIQ_IRQS+GPIO_IRQS+SPARE_ALLOC_IRQS) ++#define FREE_IRQS 128 ++#define NR_IRQS (BCM2708_ALLOC_IRQS+FREE_IRQS) ++ ++#endif /* _BCM2708_IRQS_H_ */ +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/memory.h linux-rpi/arch/arm/mach-bcm2708/include/mach/memory.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/memory.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2708/include/mach/memory.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,57 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/memory.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#ifndef __ASM_ARCH_MEMORY_H ++#define __ASM_ARCH_MEMORY_H ++ ++/* Memory overview: ++ ++ [ARMcore] <--virtual addr--> ++ [ARMmmu] <--physical addr--> ++ [GERTmap] <--bus add--> ++ [VCperiph] ++ ++*/ ++ ++/* ++ * Physical DRAM offset. ++ */ ++#define BCM_PLAT_PHYS_OFFSET UL(0x00000000) ++#define VC_ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */ ++ ++#ifdef CONFIG_BCM2708_NOL2CACHE ++ #define _REAL_BUS_OFFSET UL(0xC0000000) /* don't use L1 or L2 caches */ ++#else ++ #define _REAL_BUS_OFFSET UL(0x40000000) /* use L2 cache */ ++#endif ++ ++/* We're using the memory at 64M in the VideoCore for Linux - this adjustment ++ * will provide the offset into this area as well as setting the bits that ++ * stop the L1 and L2 cache from being used ++ * ++ * WARNING: this only works because the ARM is given memory at a fixed location ++ * (ARMMEM_OFFSET) ++ */ ++#define BUS_OFFSET (VC_ARMMEM_OFFSET + _REAL_BUS_OFFSET) ++#define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET)) ++#define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET)) ++#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET)) ++#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET)) ++ ++#endif +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/platform.h linux-rpi/arch/arm/mach-bcm2708/include/mach/platform.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/platform.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2708/include/mach/platform.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,230 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/platform.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef _BCM2708_PLATFORM_H ++#define _BCM2708_PLATFORM_H ++ ++ ++/* macros to get at IO space when running virtually */ ++#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000) ++ ++#define __io_address(n) IOMEM(IO_ADDRESS(n)) ++ ++ ++/* ++ * SDRAM ++ */ ++#define BCM2708_SDRAM_BASE 0x00000000 ++ ++/* ++ * Logic expansion modules ++ * ++ */ ++ ++ ++/* ------------------------------------------------------------------------ ++ * BCM2708 ARMCTRL Registers ++ * ------------------------------------------------------------------------ ++ */ ++ ++#define HW_REGISTER_RW(addr) (addr) ++#define HW_REGISTER_RO(addr) (addr) ++ ++#include "arm_control.h" ++#undef ARM_BASE ++ ++/* ++ * Definitions and addresses for the ARM CONTROL logic ++ * This file is manually generated. ++ */ ++ ++#define BCM2708_PERI_BASE 0x20000000 ++#define IC0_BASE (BCM2708_PERI_BASE + 0x2000) ++#define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */ ++#define MPHI_BASE (BCM2708_PERI_BASE + 0x6000) /* Message -based Parallel Host Interface */ ++#define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */ ++#define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */ ++#define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */ ++#define PCM_CLOCK_BASE (BCM2708_PERI_BASE + 0x101098) /* PCM Clock */ ++#define RNG_BASE (BCM2708_PERI_BASE + 0x104000) /* Hardware RNG */ ++#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */ ++#define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */ ++#define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */ ++#define I2S_BASE (BCM2708_PERI_BASE + 0x203000) /* I2S */ ++#define SPI0_BASE (BCM2708_PERI_BASE + 0x204000) /* SPI0 */ ++#define BSC0_BASE (BCM2708_PERI_BASE + 0x205000) /* BSC0 I2C/TWI */ ++#define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */ ++#define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */ ++#define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */ ++#define BSC1_BASE (BCM2708_PERI_BASE + 0x804000) /* BSC1 I2C/TWI */ ++#define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */ ++#define MCORE_BASE (BCM2708_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/ ++ ++#define ARMCTRL_BASE (ARM_BASE + 0x000) ++#define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */ ++#define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */ ++#define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */ ++#define ARMCTRL_0_BELL_BASE (ARMCTRL_0_SBM_BASE + 0x40) /* User 0 (ARM)'s Doorbell */ ++#define ARMCTRL_0_MAIL0_BASE (ARMCTRL_0_SBM_BASE + 0x80) /* User 0 (ARM)'s Mailbox 0 */ ++ ++ ++/* ++ * Interrupt assignments ++ */ ++ ++#define ARM_IRQ1_BASE 0 ++#define INTERRUPT_TIMER0 (ARM_IRQ1_BASE + 0) ++#define INTERRUPT_TIMER1 (ARM_IRQ1_BASE + 1) ++#define INTERRUPT_TIMER2 (ARM_IRQ1_BASE + 2) ++#define INTERRUPT_TIMER3 (ARM_IRQ1_BASE + 3) ++#define INTERRUPT_CODEC0 (ARM_IRQ1_BASE + 4) ++#define INTERRUPT_CODEC1 (ARM_IRQ1_BASE + 5) ++#define INTERRUPT_CODEC2 (ARM_IRQ1_BASE + 6) ++#define INTERRUPT_VC_JPEG (ARM_IRQ1_BASE + 7) ++#define INTERRUPT_ISP (ARM_IRQ1_BASE + 8) ++#define INTERRUPT_VC_USB (ARM_IRQ1_BASE + 9) ++#define INTERRUPT_VC_3D (ARM_IRQ1_BASE + 10) ++#define INTERRUPT_TRANSPOSER (ARM_IRQ1_BASE + 11) ++#define INTERRUPT_MULTICORESYNC0 (ARM_IRQ1_BASE + 12) ++#define INTERRUPT_MULTICORESYNC1 (ARM_IRQ1_BASE + 13) ++#define INTERRUPT_MULTICORESYNC2 (ARM_IRQ1_BASE + 14) ++#define INTERRUPT_MULTICORESYNC3 (ARM_IRQ1_BASE + 15) ++#define INTERRUPT_DMA0 (ARM_IRQ1_BASE + 16) ++#define INTERRUPT_DMA1 (ARM_IRQ1_BASE + 17) ++#define INTERRUPT_VC_DMA2 (ARM_IRQ1_BASE + 18) ++#define INTERRUPT_VC_DMA3 (ARM_IRQ1_BASE + 19) ++#define INTERRUPT_DMA4 (ARM_IRQ1_BASE + 20) ++#define INTERRUPT_DMA5 (ARM_IRQ1_BASE + 21) ++#define INTERRUPT_DMA6 (ARM_IRQ1_BASE + 22) ++#define INTERRUPT_DMA7 (ARM_IRQ1_BASE + 23) ++#define INTERRUPT_DMA8 (ARM_IRQ1_BASE + 24) ++#define INTERRUPT_DMA9 (ARM_IRQ1_BASE + 25) ++#define INTERRUPT_DMA10 (ARM_IRQ1_BASE + 26) ++#define INTERRUPT_DMA11 (ARM_IRQ1_BASE + 27) ++#define INTERRUPT_DMA12 (ARM_IRQ1_BASE + 28) ++#define INTERRUPT_AUX (ARM_IRQ1_BASE + 29) ++#define INTERRUPT_ARM (ARM_IRQ1_BASE + 30) ++#define INTERRUPT_VPUDMA (ARM_IRQ1_BASE + 31) ++ ++#define ARM_IRQ2_BASE 32 ++#define INTERRUPT_HOSTPORT (ARM_IRQ2_BASE + 0) ++#define INTERRUPT_VIDEOSCALER (ARM_IRQ2_BASE + 1) ++#define INTERRUPT_CCP2TX (ARM_IRQ2_BASE + 2) ++#define INTERRUPT_SDC (ARM_IRQ2_BASE + 3) ++#define INTERRUPT_DSI0 (ARM_IRQ2_BASE + 4) ++#define INTERRUPT_AVE (ARM_IRQ2_BASE + 5) ++#define INTERRUPT_CAM0 (ARM_IRQ2_BASE + 6) ++#define INTERRUPT_CAM1 (ARM_IRQ2_BASE + 7) ++#define INTERRUPT_HDMI0 (ARM_IRQ2_BASE + 8) ++#define INTERRUPT_HDMI1 (ARM_IRQ2_BASE + 9) ++#define INTERRUPT_PIXELVALVE1 (ARM_IRQ2_BASE + 10) ++#define INTERRUPT_I2CSPISLV (ARM_IRQ2_BASE + 11) ++#define INTERRUPT_DSI1 (ARM_IRQ2_BASE + 12) ++#define INTERRUPT_PWA0 (ARM_IRQ2_BASE + 13) ++#define INTERRUPT_PWA1 (ARM_IRQ2_BASE + 14) ++#define INTERRUPT_CPR (ARM_IRQ2_BASE + 15) ++#define INTERRUPT_SMI (ARM_IRQ2_BASE + 16) ++#define INTERRUPT_GPIO0 (ARM_IRQ2_BASE + 17) ++#define INTERRUPT_GPIO1 (ARM_IRQ2_BASE + 18) ++#define INTERRUPT_GPIO2 (ARM_IRQ2_BASE + 19) ++#define INTERRUPT_GPIO3 (ARM_IRQ2_BASE + 20) ++#define INTERRUPT_VC_I2C (ARM_IRQ2_BASE + 21) ++#define INTERRUPT_VC_SPI (ARM_IRQ2_BASE + 22) ++#define INTERRUPT_VC_I2SPCM (ARM_IRQ2_BASE + 23) ++#define INTERRUPT_VC_SDIO (ARM_IRQ2_BASE + 24) ++#define INTERRUPT_VC_UART (ARM_IRQ2_BASE + 25) ++#define INTERRUPT_SLIMBUS (ARM_IRQ2_BASE + 26) ++#define INTERRUPT_VEC (ARM_IRQ2_BASE + 27) ++#define INTERRUPT_CPG (ARM_IRQ2_BASE + 28) ++#define INTERRUPT_RNG (ARM_IRQ2_BASE + 29) ++#define INTERRUPT_VC_ARASANSDIO (ARM_IRQ2_BASE + 30) ++#define INTERRUPT_AVSPMON (ARM_IRQ2_BASE + 31) ++ ++#define ARM_IRQ0_BASE 64 ++#define INTERRUPT_ARM_TIMER (ARM_IRQ0_BASE + 0) ++#define INTERRUPT_ARM_MAILBOX (ARM_IRQ0_BASE + 1) ++#define INTERRUPT_ARM_DOORBELL_0 (ARM_IRQ0_BASE + 2) ++#define INTERRUPT_ARM_DOORBELL_1 (ARM_IRQ0_BASE + 3) ++#define INTERRUPT_VPU0_HALTED (ARM_IRQ0_BASE + 4) ++#define INTERRUPT_VPU1_HALTED (ARM_IRQ0_BASE + 5) ++#define INTERRUPT_ILLEGAL_TYPE0 (ARM_IRQ0_BASE + 6) ++#define INTERRUPT_ILLEGAL_TYPE1 (ARM_IRQ0_BASE + 7) ++#define INTERRUPT_PENDING1 (ARM_IRQ0_BASE + 8) ++#define INTERRUPT_PENDING2 (ARM_IRQ0_BASE + 9) ++#define INTERRUPT_JPEG (ARM_IRQ0_BASE + 10) ++#define INTERRUPT_USB (ARM_IRQ0_BASE + 11) ++#define INTERRUPT_3D (ARM_IRQ0_BASE + 12) ++#define INTERRUPT_DMA2 (ARM_IRQ0_BASE + 13) ++#define INTERRUPT_DMA3 (ARM_IRQ0_BASE + 14) ++#define INTERRUPT_I2C (ARM_IRQ0_BASE + 15) ++#define INTERRUPT_SPI (ARM_IRQ0_BASE + 16) ++#define INTERRUPT_I2SPCM (ARM_IRQ0_BASE + 17) ++#define INTERRUPT_SDIO (ARM_IRQ0_BASE + 18) ++#define INTERRUPT_UART (ARM_IRQ0_BASE + 19) ++#define INTERRUPT_ARASANSDIO (ARM_IRQ0_BASE + 20) ++ ++#define MAXIRQNUM (32 + 32 + 20) ++#define MAXFIQNUM (32 + 32 + 20) ++ ++#define MAX_TIMER 2 ++#define MAX_PERIOD 699050 ++#define TICKS_PER_uSEC 1 ++ ++/* ++ * These are useconds NOT ticks. ++ * ++ */ ++#define mSEC_1 1000 ++#define mSEC_5 (mSEC_1 * 5) ++#define mSEC_10 (mSEC_1 * 10) ++#define mSEC_25 (mSEC_1 * 25) ++#define SEC_1 (mSEC_1 * 1000) ++ ++/* ++ * Watchdog ++ */ ++#define PM_RSTC (PM_BASE+0x1c) ++#define PM_RSTS (PM_BASE+0x20) ++#define PM_WDOG (PM_BASE+0x24) ++ ++#define PM_WDOG_RESET 0000000000 ++#define PM_PASSWORD 0x5a000000 ++#define PM_WDOG_TIME_SET 0x000fffff ++#define PM_RSTC_WRCFG_CLR 0xffffffcf ++#define PM_RSTC_WRCFG_SET 0x00000030 ++#define PM_RSTC_WRCFG_FULL_RESET 0x00000020 ++#define PM_RSTC_RESET 0x00000102 ++ ++#define PM_RSTS_HADPOR_SET 0x00001000 ++#define PM_RSTS_HADSRH_SET 0x00000400 ++#define PM_RSTS_HADSRF_SET 0x00000200 ++#define PM_RSTS_HADSRQ_SET 0x00000100 ++#define PM_RSTS_HADWRH_SET 0x00000040 ++#define PM_RSTS_HADWRF_SET 0x00000020 ++#define PM_RSTS_HADWRQ_SET 0x00000010 ++#define PM_RSTS_HADDRH_SET 0x00000004 ++#define PM_RSTS_HADDRF_SET 0x00000002 ++#define PM_RSTS_HADDRQ_SET 0x00000001 ++ ++#define UART0_CLOCK 3000000 ++ ++#endif ++ ++/* END */ +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/system.h linux-rpi/arch/arm/mach-bcm2708/include/mach/system.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/system.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2708/include/mach/system.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,38 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/system.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * Copyright (C) 2003 ARM Limited ++ * Copyright (C) 2000 Deep Blue Solutions Ltd ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#ifndef __ASM_ARCH_SYSTEM_H ++#define __ASM_ARCH_SYSTEM_H ++ ++#include ++#include ++#include ++ ++static inline void arch_idle(void) ++{ ++ /* ++ * This should do all the clock switching ++ * and wait for interrupt tricks ++ */ ++ cpu_do_idle(); ++} ++ ++#endif +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/timex.h linux-rpi/arch/arm/mach-bcm2708/include/mach/timex.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/timex.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2708/include/mach/timex.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,23 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/timex.h ++ * ++ * BCM2708 sysem clock frequency ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#define CLOCK_TICK_RATE (1000000) +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/uncompress.h linux-rpi/arch/arm/mach-bcm2708/include/mach/uncompress.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/uncompress.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2708/include/mach/uncompress.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,84 @@ ++/* ++ * arch/arm/mach-bcn2708/include/mach/uncompress.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * Copyright (C) 2003 ARM Limited ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++ ++#define UART_BAUD 115200 ++ ++#define BCM2708_UART_DR __io(UART0_BASE + UART01x_DR) ++#define BCM2708_UART_FR __io(UART0_BASE + UART01x_FR) ++#define BCM2708_UART_IBRD __io(UART0_BASE + UART011_IBRD) ++#define BCM2708_UART_FBRD __io(UART0_BASE + UART011_FBRD) ++#define BCM2708_UART_LCRH __io(UART0_BASE + UART011_LCRH) ++#define BCM2708_UART_CR __io(UART0_BASE + UART011_CR) ++ ++/* ++ * This does not append a newline ++ */ ++static inline void putc(int c) ++{ ++ while (__raw_readl(BCM2708_UART_FR) & UART01x_FR_TXFF) ++ barrier(); ++ ++ __raw_writel(c, BCM2708_UART_DR); ++} ++ ++static inline void flush(void) ++{ ++ int fr; ++ ++ do { ++ fr = __raw_readl(BCM2708_UART_FR); ++ barrier(); ++ } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE); ++} ++ ++static inline void arch_decomp_setup(void) ++{ ++ int temp, div, rem, frac; ++ ++ temp = 16 * UART_BAUD; ++ div = UART0_CLOCK / temp; ++ rem = UART0_CLOCK % temp; ++ temp = (8 * rem) / UART_BAUD; ++ frac = (temp >> 1) + (temp & 1); ++ ++ /* Make sure the UART is disabled before we start */ ++ __raw_writel(0, BCM2708_UART_CR); ++ ++ /* Set the baud rate */ ++ __raw_writel(div, BCM2708_UART_IBRD); ++ __raw_writel(frac, BCM2708_UART_FBRD); ++ ++ /* Set the UART to 8n1, FIFO enabled */ ++ __raw_writel(UART01x_LCRH_WLEN_8 | UART01x_LCRH_FEN, BCM2708_UART_LCRH); ++ ++ /* Enable the UART */ ++ __raw_writel(UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_RXE, ++ BCM2708_UART_CR); ++} ++ ++/* ++ * nothing to do ++ */ ++#define arch_decomp_wdog() +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/vc_sm_defs.h linux-rpi/arch/arm/mach-bcm2708/include/mach/vc_sm_defs.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/vc_sm_defs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2708/include/mach/vc_sm_defs.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,181 @@ ++/***************************************************************************** ++* Copyright 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#ifndef __VC_SM_DEFS_H__INCLUDED__ ++#define __VC_SM_DEFS_H__INCLUDED__ ++ ++/* FourCC code used for VCHI connection */ ++#define VC_SM_SERVER_NAME MAKE_FOURCC("SMEM") ++ ++/* Maximum message length */ ++#define VC_SM_MAX_MSG_LEN (sizeof(VC_SM_MSG_UNION_T) + \ ++ sizeof(VC_SM_MSG_HDR_T)) ++#define VC_SM_MAX_RSP_LEN (sizeof(VC_SM_MSG_UNION_T)) ++ ++/* Resource name maximum size */ ++#define VC_SM_RESOURCE_NAME 32 ++ ++/* All message types supported for HOST->VC direction */ ++typedef enum { ++ /* Allocate shared memory block */ ++ VC_SM_MSG_TYPE_ALLOC, ++ /* Lock allocated shared memory block */ ++ VC_SM_MSG_TYPE_LOCK, ++ /* Unlock allocated shared memory block */ ++ VC_SM_MSG_TYPE_UNLOCK, ++ /* Unlock allocated shared memory block, do not answer command */ ++ VC_SM_MSG_TYPE_UNLOCK_NOANS, ++ /* Free shared memory block */ ++ VC_SM_MSG_TYPE_FREE, ++ /* Resize a shared memory block */ ++ VC_SM_MSG_TYPE_RESIZE, ++ /* Walk the allocated shared memory block(s) */ ++ VC_SM_MSG_TYPE_WALK_ALLOC, ++ ++ /* A previously applied action will need to be reverted */ ++ VC_SM_MSG_TYPE_ACTION_CLEAN, ++ VC_SM_MSG_TYPE_MAX ++} VC_SM_MSG_TYPE; ++ ++/* Type of memory to be allocated */ ++typedef enum { ++ VC_SM_ALLOC_CACHED, ++ VC_SM_ALLOC_NON_CACHED, ++ ++} VC_SM_ALLOC_TYPE_T; ++ ++/* Message header for all messages in HOST->VC direction */ ++typedef struct { ++ int32_t type; ++ uint32_t trans_id; ++ uint8_t body[0]; ++ ++} VC_SM_MSG_HDR_T; ++ ++/* Request to allocate memory (HOST->VC) */ ++typedef struct { ++ /* type of memory to allocate */ ++ VC_SM_ALLOC_TYPE_T type; ++ /* byte amount of data to allocate per unit */ ++ uint32_t base_unit; ++ /* number of unit to allocate */ ++ uint32_t num_unit; ++ /* alignement to be applied on allocation */ ++ uint32_t alignement; ++ /* identity of who allocated this block */ ++ uint32_t allocator; ++ /* resource name (for easier tracking on vc side) */ ++ char name[VC_SM_RESOURCE_NAME]; ++ ++} VC_SM_ALLOC_T; ++ ++/* Result of a requested memory allocation (VC->HOST) */ ++typedef struct { ++ /* Transaction identifier */ ++ uint32_t trans_id; ++ ++ /* Resource handle */ ++ uint32_t res_handle; ++ /* Pointer to resource buffer */ ++ void *res_mem; ++ /* Resource base size (bytes) */ ++ uint32_t res_base_size; ++ /* Resource number */ ++ uint32_t res_num; ++ ++} VC_SM_ALLOC_RESULT_T; ++ ++/* Request to free a previously allocated memory (HOST->VC) */ ++typedef struct { ++ /* Resource handle (returned from alloc) */ ++ uint32_t res_handle; ++ /* Resource buffer (returned from alloc) */ ++ void *res_mem; ++ ++} VC_SM_FREE_T; ++ ++/* Request to lock a previously allocated memory (HOST->VC) */ ++typedef struct { ++ /* Resource handle (returned from alloc) */ ++ uint32_t res_handle; ++ /* Resource buffer (returned from alloc) */ ++ void *res_mem; ++ ++} VC_SM_LOCK_UNLOCK_T; ++ ++/* Request to resize a previously allocated memory (HOST->VC) */ ++typedef struct { ++ /* Resource handle (returned from alloc) */ ++ uint32_t res_handle; ++ /* Resource buffer (returned from alloc) */ ++ void *res_mem; ++ /* Resource *new* size requested (bytes) */ ++ uint32_t res_new_size; ++ ++} VC_SM_RESIZE_T; ++ ++/* Result of a requested memory lock (VC->HOST) */ ++typedef struct { ++ /* Transaction identifier */ ++ uint32_t trans_id; ++ ++ /* Resource handle */ ++ uint32_t res_handle; ++ /* Pointer to resource buffer */ ++ void *res_mem; ++ /* Pointer to former resource buffer if the memory ++ * was reallocated */ ++ void *res_old_mem; ++ ++} VC_SM_LOCK_RESULT_T; ++ ++/* Generic result for a request (VC->HOST) */ ++typedef struct { ++ /* Transaction identifier */ ++ uint32_t trans_id; ++ ++ int32_t success; ++ ++} VC_SM_RESULT_T; ++ ++/* Request to revert a previously applied action (HOST->VC) */ ++typedef struct { ++ /* Action of interest */ ++ VC_SM_MSG_TYPE res_action; ++ /* Transaction identifier for the action of interest */ ++ uint32_t action_trans_id; ++ ++} VC_SM_ACTION_CLEAN_T; ++ ++/* Request to remove all data associated with a given allocator (HOST->VC) */ ++typedef struct { ++ /* Allocator identifier */ ++ uint32_t allocator; ++ ++} VC_SM_FREE_ALL_T; ++ ++/* Union of ALL messages */ ++typedef union { ++ VC_SM_ALLOC_T alloc; ++ VC_SM_ALLOC_RESULT_T alloc_result; ++ VC_SM_FREE_T free; ++ VC_SM_ACTION_CLEAN_T action_clean; ++ VC_SM_RESIZE_T resize; ++ VC_SM_LOCK_RESULT_T lock_result; ++ VC_SM_RESULT_T result; ++ VC_SM_FREE_ALL_T free_all; ++ ++} VC_SM_MSG_UNION_T; ++ ++#endif /* __VC_SM_DEFS_H__INCLUDED__ */ +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/vc_sm_knl.h linux-rpi/arch/arm/mach-bcm2708/include/mach/vc_sm_knl.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/vc_sm_knl.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2708/include/mach/vc_sm_knl.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,55 @@ ++/***************************************************************************** ++* Copyright 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#ifndef __VC_SM_KNL_H__INCLUDED__ ++#define __VC_SM_KNL_H__INCLUDED__ ++ ++#if !defined(__KERNEL__) ++#error "This interface is for kernel use only..." ++#endif ++ ++/* Type of memory to be locked (ie mapped) */ ++typedef enum { ++ VC_SM_LOCK_CACHED, ++ VC_SM_LOCK_NON_CACHED, ++ ++} VC_SM_LOCK_CACHE_MODE_T; ++ ++/* Allocate a shared memory handle and block. ++*/ ++int vc_sm_alloc(VC_SM_ALLOC_T *alloc, int *handle); ++ ++/* Free a previously allocated shared memory handle and block. ++*/ ++int vc_sm_free(int handle); ++ ++/* Lock a memory handle for use by kernel. ++*/ ++int vc_sm_lock(int handle, VC_SM_LOCK_CACHE_MODE_T mode, ++ long unsigned int *data); ++ ++/* Unlock a memory handle in use by kernel. ++*/ ++int vc_sm_unlock(int handle, int flush, int no_vc_unlock); ++ ++/* Get an internal resource handle mapped from the external one. ++*/ ++int vc_sm_int_handle(int handle); ++ ++/* Map a shared memory region for use by kernel. ++*/ ++int vc_sm_map(int handle, unsigned int sm_addr, VC_SM_LOCK_CACHE_MODE_T mode, ++ long unsigned int *data); ++ ++#endif /* __VC_SM_KNL_H__INCLUDED__ */ +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/vc_vchi_sm.h linux-rpi/arch/arm/mach-bcm2708/include/mach/vc_vchi_sm.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/vc_vchi_sm.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2708/include/mach/vc_vchi_sm.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,82 @@ ++/***************************************************************************** ++* Copyright 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#ifndef __VC_VCHI_SM_H__INCLUDED__ ++#define __VC_VCHI_SM_H__INCLUDED__ ++ ++#include "interface/vchi/vchi.h" ++ ++#include "vc_sm_defs.h" ++ ++/* Forward declare. ++*/ ++typedef struct sm_instance *VC_VCHI_SM_HANDLE_T; ++ ++/* Initialize the shared memory service, opens up vchi connection to talk to it. ++*/ ++VC_VCHI_SM_HANDLE_T vc_vchi_sm_init(VCHI_INSTANCE_T vchi_instance, ++ VCHI_CONNECTION_T **vchi_connections, ++ uint32_t num_connections); ++ ++/* Terminates the shared memory service. ++*/ ++int vc_vchi_sm_stop(VC_VCHI_SM_HANDLE_T *handle); ++ ++/* Ask the shared memory service to allocate some memory on videocre and ++** return the result of this allocation (which upon success will be a pointer ++** to some memory in videocore space). ++*/ ++int vc_vchi_sm_alloc(VC_VCHI_SM_HANDLE_T handle, ++ VC_SM_ALLOC_T *alloc, ++ VC_SM_ALLOC_RESULT_T *alloc_result, uint32_t *trans_id); ++ ++/* Ask the shared memory service to free up some memory that was previously ++** allocated by the vc_vchi_sm_alloc function call. ++*/ ++int vc_vchi_sm_free(VC_VCHI_SM_HANDLE_T handle, ++ VC_SM_FREE_T *free, uint32_t *trans_id); ++ ++/* Ask the shared memory service to lock up some memory that was previously ++** allocated by the vc_vchi_sm_alloc function call. ++*/ ++int vc_vchi_sm_lock(VC_VCHI_SM_HANDLE_T handle, ++ VC_SM_LOCK_UNLOCK_T *lock_unlock, ++ VC_SM_LOCK_RESULT_T *lock_result, uint32_t *trans_id); ++ ++/* Ask the shared memory service to unlock some memory that was previously ++** allocated by the vc_vchi_sm_alloc function call. ++*/ ++int vc_vchi_sm_unlock(VC_VCHI_SM_HANDLE_T handle, ++ VC_SM_LOCK_UNLOCK_T *lock_unlock, ++ uint32_t *trans_id, uint8_t wait_reply); ++ ++/* Ask the shared memory service to resize some memory that was previously ++** allocated by the vc_vchi_sm_alloc function call. ++*/ ++int vc_vchi_sm_resize(VC_VCHI_SM_HANDLE_T handle, ++ VC_SM_RESIZE_T *resize, uint32_t *trans_id); ++ ++/* Walk the allocated resources on the videocore side, the allocation will ++** show up in the log. This is purely for debug/information and takes no ++** specific actions. ++*/ ++int vc_vchi_sm_walk_alloc(VC_VCHI_SM_HANDLE_T handle); ++ ++/* Clean up following a previously interrupted action which left the system ++** in a bad state of some sort. ++*/ ++int vc_vchi_sm_clean_up(VC_VCHI_SM_HANDLE_T handle, ++ VC_SM_ACTION_CLEAN_T *action_clean); ++ ++#endif /* __VC_VCHI_SM_H__INCLUDED__ */ +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/vmalloc.h linux-rpi/arch/arm/mach-bcm2708/include/mach/vmalloc.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2708/include/mach/vmalloc.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,20 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/vmalloc.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#define VMALLOC_END (0xe8000000) +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/vmcs_sm_ioctl.h linux-rpi/arch/arm/mach-bcm2708/include/mach/vmcs_sm_ioctl.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2708/include/mach/vmcs_sm_ioctl.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2708/include/mach/vmcs_sm_ioctl.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,248 @@ ++/***************************************************************************** ++* Copyright 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++* ++*****************************************************************************/ ++ ++#if !defined(__VMCS_SM_IOCTL_H__INCLUDED__) ++#define __VMCS_SM_IOCTL_H__INCLUDED__ ++ ++/* ---- Include Files ---------------------------------------------------- */ ++ ++#if defined(__KERNEL__) ++#include /* Needed for standard types */ ++#else ++#include ++#endif ++ ++#include ++ ++/* ---- Constants and Types ---------------------------------------------- */ ++ ++#define VMCS_SM_RESOURCE_NAME 32 ++#define VMCS_SM_RESOURCE_NAME_DEFAULT "sm-host-resource" ++ ++/* Type define used to create unique IOCTL number */ ++#define VMCS_SM_MAGIC_TYPE 'I' ++ ++/* IOCTL commands */ ++enum vmcs_sm_cmd_e { ++ VMCS_SM_CMD_ALLOC = 0x5A, /* Start at 0x5A arbitrarily */ ++ VMCS_SM_CMD_ALLOC_SHARE, ++ VMCS_SM_CMD_LOCK, ++ VMCS_SM_CMD_LOCK_CACHE, ++ VMCS_SM_CMD_UNLOCK, ++ VMCS_SM_CMD_RESIZE, ++ VMCS_SM_CMD_UNMAP, ++ VMCS_SM_CMD_FREE, ++ VMCS_SM_CMD_FLUSH, ++ VMCS_SM_CMD_INVALID, ++ ++ VMCS_SM_CMD_SIZE_USR_HANDLE, ++ VMCS_SM_CMD_CHK_USR_HANDLE, ++ ++ VMCS_SM_CMD_MAPPED_USR_HANDLE, ++ VMCS_SM_CMD_MAPPED_USR_ADDRESS, ++ VMCS_SM_CMD_MAPPED_VC_HDL_FROM_ADDR, ++ VMCS_SM_CMD_MAPPED_VC_HDL_FROM_HDL, ++ VMCS_SM_CMD_MAPPED_VC_ADDR_FROM_HDL, ++ ++ VMCS_SM_CMD_VC_WALK_ALLOC, ++ VMCS_SM_CMD_HOST_WALK_MAP, ++ VMCS_SM_CMD_HOST_WALK_PID_ALLOC, ++ VMCS_SM_CMD_HOST_WALK_PID_MAP, ++ ++ VMCS_SM_CMD_CLEAN_INVALID, ++ ++ VMCS_SM_CMD_LAST /* Do no delete */ ++}; ++ ++/* Cache type supported, conveniently matches the user space definition in ++** user-vcsm.h. ++*/ ++enum vmcs_sm_cache_e { ++ VMCS_SM_CACHE_NONE, ++ VMCS_SM_CACHE_HOST, ++ VMCS_SM_CACHE_VC, ++ VMCS_SM_CACHE_BOTH, ++}; ++ ++/* IOCTL Data structures */ ++struct vmcs_sm_ioctl_alloc { ++ /* user -> kernel */ ++ unsigned int size; ++ unsigned int num; ++ enum vmcs_sm_cache_e cached; ++ char name[VMCS_SM_RESOURCE_NAME]; ++ ++ /* kernel -> user */ ++ unsigned int handle; ++ /* unsigned int base_addr; */ ++}; ++ ++struct vmcs_sm_ioctl_alloc_share { ++ /* user -> kernel */ ++ unsigned int handle; ++ unsigned int size; ++}; ++ ++struct vmcs_sm_ioctl_free { ++ /* user -> kernel */ ++ unsigned int handle; ++ /* unsigned int base_addr; */ ++}; ++ ++struct vmcs_sm_ioctl_lock_unlock { ++ /* user -> kernel */ ++ unsigned int handle; ++ ++ /* kernel -> user */ ++ unsigned int addr; ++}; ++ ++struct vmcs_sm_ioctl_lock_cache { ++ /* user -> kernel */ ++ unsigned int handle; ++ enum vmcs_sm_cache_e cached; ++}; ++ ++struct vmcs_sm_ioctl_resize { ++ /* user -> kernel */ ++ unsigned int handle; ++ unsigned int new_size; ++ ++ /* kernel -> user */ ++ unsigned int old_size; ++}; ++ ++struct vmcs_sm_ioctl_map { ++ /* user -> kernel */ ++ /* and kernel -> user */ ++ unsigned int pid; ++ unsigned int handle; ++ unsigned int addr; ++ ++ /* kernel -> user */ ++ unsigned int size; ++}; ++ ++struct vmcs_sm_ioctl_walk { ++ /* user -> kernel */ ++ unsigned int pid; ++}; ++ ++struct vmcs_sm_ioctl_chk { ++ /* user -> kernel */ ++ unsigned int handle; ++ ++ /* kernel -> user */ ++ unsigned int addr; ++ unsigned int size; ++ enum vmcs_sm_cache_e cache; ++}; ++ ++struct vmcs_sm_ioctl_size { ++ /* user -> kernel */ ++ unsigned int handle; ++ ++ /* kernel -> user */ ++ unsigned int size; ++}; ++ ++struct vmcs_sm_ioctl_cache { ++ /* user -> kernel */ ++ unsigned int handle; ++ unsigned int addr; ++ unsigned int size; ++}; ++ ++struct vmcs_sm_ioctl_clean_invalid { ++ /* user -> kernel */ ++ struct { ++ unsigned int cmd; ++ unsigned int handle; ++ unsigned int addr; ++ unsigned int size; ++ } s[8]; ++}; ++ ++/* IOCTL numbers */ ++#define VMCS_SM_IOCTL_MEM_ALLOC\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_ALLOC,\ ++ struct vmcs_sm_ioctl_alloc) ++#define VMCS_SM_IOCTL_MEM_ALLOC_SHARE\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_ALLOC_SHARE,\ ++ struct vmcs_sm_ioctl_alloc_share) ++#define VMCS_SM_IOCTL_MEM_LOCK\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_LOCK,\ ++ struct vmcs_sm_ioctl_lock_unlock) ++#define VMCS_SM_IOCTL_MEM_LOCK_CACHE\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_LOCK_CACHE,\ ++ struct vmcs_sm_ioctl_lock_cache) ++#define VMCS_SM_IOCTL_MEM_UNLOCK\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_UNLOCK,\ ++ struct vmcs_sm_ioctl_lock_unlock) ++#define VMCS_SM_IOCTL_MEM_RESIZE\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_RESIZE,\ ++ struct vmcs_sm_ioctl_resize) ++#define VMCS_SM_IOCTL_MEM_FREE\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_FREE,\ ++ struct vmcs_sm_ioctl_free) ++#define VMCS_SM_IOCTL_MEM_FLUSH\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_FLUSH,\ ++ struct vmcs_sm_ioctl_cache) ++#define VMCS_SM_IOCTL_MEM_INVALID\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_INVALID,\ ++ struct vmcs_sm_ioctl_cache) ++#define VMCS_SM_IOCTL_MEM_CLEAN_INVALID\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_CLEAN_INVALID,\ ++ struct vmcs_sm_ioctl_clean_invalid) ++ ++#define VMCS_SM_IOCTL_SIZE_USR_HDL\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_SIZE_USR_HANDLE,\ ++ struct vmcs_sm_ioctl_size) ++#define VMCS_SM_IOCTL_CHK_USR_HDL\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_CHK_USR_HANDLE,\ ++ struct vmcs_sm_ioctl_chk) ++ ++#define VMCS_SM_IOCTL_MAP_USR_HDL\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_USR_HANDLE,\ ++ struct vmcs_sm_ioctl_map) ++#define VMCS_SM_IOCTL_MAP_USR_ADDRESS\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_USR_ADDRESS,\ ++ struct vmcs_sm_ioctl_map) ++#define VMCS_SM_IOCTL_MAP_VC_HDL_FR_ADDR\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_VC_HDL_FROM_ADDR,\ ++ struct vmcs_sm_ioctl_map) ++#define VMCS_SM_IOCTL_MAP_VC_HDL_FR_HDL\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_VC_HDL_FROM_HDL,\ ++ struct vmcs_sm_ioctl_map) ++#define VMCS_SM_IOCTL_MAP_VC_ADDR_FR_HDL\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_MAPPED_VC_ADDR_FROM_HDL,\ ++ struct vmcs_sm_ioctl_map) ++ ++#define VMCS_SM_IOCTL_VC_WALK_ALLOC\ ++ _IO(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_VC_WALK_ALLOC) ++#define VMCS_SM_IOCTL_HOST_WALK_MAP\ ++ _IO(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_HOST_WALK_MAP) ++#define VMCS_SM_IOCTL_HOST_WALK_PID_ALLOC\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_HOST_WALK_PID_ALLOC,\ ++ struct vmcs_sm_ioctl_walk) ++#define VMCS_SM_IOCTL_HOST_WALK_PID_MAP\ ++ _IOR(VMCS_SM_MAGIC_TYPE, VMCS_SM_CMD_HOST_WALK_PID_MAP,\ ++ struct vmcs_sm_ioctl_walk) ++ ++/* ---- Variable Externs ------------------------------------------------- */ ++ ++/* ---- Function Prototypes ---------------------------------------------- */ ++ ++#endif /* __VMCS_SM_IOCTL_H__INCLUDED__ */ +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/Kconfig linux-rpi/arch/arm/mach-bcm2708/Kconfig +--- linux-4.1.13.orig/arch/arm/mach-bcm2708/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2708/Kconfig 2015-11-29 09:42:34.787439667 +0100 +@@ -0,0 +1,45 @@ ++menu "Broadcom BCM2708 Implementations" ++ depends on ARCH_BCM2708 ++ ++config MACH_BCM2708 ++ bool "Broadcom BCM2708 Development Platform" ++ select NEED_MACH_MEMORY_H ++ select NEED_MACH_IO_H ++ select CPU_V6 ++ help ++ Include support for the Broadcom(R) BCM2708 platform. ++ ++config BCM2708_DT ++ bool "BCM2708 Device Tree support" ++ depends on MACH_BCM2708 ++ default n ++ select USE_OF ++ select ARCH_REQUIRE_GPIOLIB ++ select PINCTRL ++ select PINCTRL_BCM2835 ++ help ++ Enable Device Tree support for BCM2708 ++ ++config BCM2708_GPIO ++ bool "BCM2708 gpio support" ++ depends on MACH_BCM2708 ++ select ARCH_REQUIRE_GPIOLIB ++ default y ++ help ++ Include support for the Broadcom(R) BCM2708 gpio. ++ ++config BCM2708_NOL2CACHE ++ bool "Videocore L2 cache disable" ++ depends on MACH_BCM2708 ++ default n ++ help ++ Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt. ++ ++config BCM2708_SPIDEV ++ bool "Bind spidev to SPI0 master" ++ depends on MACH_BCM2708 ++ depends on SPI ++ default y ++ help ++ Binds spidev driver to the SPI0 master ++endmenu +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/Makefile linux-rpi/arch/arm/mach-bcm2708/Makefile +--- linux-4.1.13.orig/arch/arm/mach-bcm2708/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2708/Makefile 2015-11-29 09:42:34.787439667 +0100 +@@ -0,0 +1,6 @@ ++# ++# Makefile for the linux kernel. ++# ++ ++obj-$(CONFIG_MACH_BCM2708) += bcm2708.o armctrl.o ++obj-$(CONFIG_BCM2708_GPIO) += bcm2708_gpio.o +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2708/Makefile.boot linux-rpi/arch/arm/mach-bcm2708/Makefile.boot +--- linux-4.1.13.orig/arch/arm/mach-bcm2708/Makefile.boot 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2708/Makefile.boot 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,3 @@ ++ zreladdr-y := 0x00008000 ++params_phys-y := 0x00000100 ++initrd_phys-y := 0x00800000 +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/armctrl.c linux-rpi/arch/arm/mach-bcm2709/armctrl.c +--- linux-4.1.13.orig/arch/arm/mach-bcm2709/armctrl.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2709/armctrl.c 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,384 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/armctrl.c ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include "armctrl.h" ++ ++/* For support of kernels >= 3.0 assume only one VIC for now*/ ++static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = { ++ INTERRUPT_VC_JPEG, ++ INTERRUPT_VC_USB, ++ INTERRUPT_VC_3D, ++ INTERRUPT_VC_DMA2, ++ INTERRUPT_VC_DMA3, ++ INTERRUPT_VC_I2C, ++ INTERRUPT_VC_SPI, ++ INTERRUPT_VC_I2SPCM, ++ INTERRUPT_VC_SDIO, ++ INTERRUPT_VC_UART, ++ INTERRUPT_VC_ARASANSDIO ++}; ++ ++extern unsigned force_core; ++ ++static void armctrl_mask_irq(struct irq_data *d) ++{ ++ static const unsigned int disables[4] = { ++ ARM_IRQ_DIBL1, ++ ARM_IRQ_DIBL2, ++ ARM_IRQ_DIBL3, ++ 0 ++ }; ++ int i; ++ if (d->irq >= FIQ_START) { ++ writel(0, __io_address(ARM_IRQ_FAST)); ++ } else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) { ++#if 1 ++ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_CNTPSIRQ; ++ for (i=0; i<4; i++) // i = raw_smp_processor_id(); // ++ { ++ unsigned int val = readl(__io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); ++ writel(val &~ (1 << data), __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); ++ } ++#endif ++ } else if (d->irq >= IRQ_ARM_LOCAL_MAILBOX0 && d->irq < IRQ_ARM_LOCAL_MAILBOX0 + 4) { ++#if 0 ++ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_MAILBOX0; ++ for (i=0; i<4; i++) { ++ unsigned int val = readl(__io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); ++ writel(val &~ (1 << data), __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); ++ } ++#endif ++ } else if (d->irq >= ARM_IRQ1_BASE && d->irq < ARM_IRQ_LOCAL_BASE) { ++ unsigned int data = (unsigned int)irq_get_chip_data(d->irq); ++ writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3])); ++ } else if (d->irq == INTERRUPT_ARM_LOCAL_PMU_FAST) { ++ writel(0xf, __io_address(ARM_LOCAL_PM_ROUTING_CLR)); ++ } else { printk("%s: %d\n", __func__, d->irq); BUG(); } ++} ++ ++static void armctrl_unmask_irq(struct irq_data *d) ++{ ++ static const unsigned int enables[4] = { ++ ARM_IRQ_ENBL1, ++ ARM_IRQ_ENBL2, ++ ARM_IRQ_ENBL3, ++ 0 ++ }; ++ int i; ++ if (d->irq >= FIQ_START) { ++ unsigned int data; ++ if (force_core) { ++ data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING)); ++ data &= ~0xc; ++ data |= ((force_core-1) << 2); ++ writel(data, __io_address(ARM_LOCAL_GPU_INT_ROUTING)); ++ } ++ else if (num_online_cpus() > 1) { ++ data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING)); ++ data &= ~0xc; ++ data |= (1 << 2); ++ writel(data, __io_address(ARM_LOCAL_GPU_INT_ROUTING)); ++ } ++ /* Unmask in ARMCTRL block after routing it properly */ ++ data = (unsigned int)irq_get_chip_data(d->irq) - FIQ_START; ++ writel(0x80 | data, __io_address(ARM_IRQ_FAST)); ++ } else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) { ++#if 1 ++ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_CNTPSIRQ; ++ for (i=0; i<4; i++) // i = raw_smp_processor_id(); ++ { ++ unsigned int val = readl(__io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); ++ writel(val | (1 << data), __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i)); ++ } ++#endif ++ } else if (d->irq >= IRQ_ARM_LOCAL_MAILBOX0 && d->irq < IRQ_ARM_LOCAL_MAILBOX0 + 4) { ++#if 0 ++ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_MAILBOX0; ++ for (i=0; i<4; i++) { ++ unsigned int val = readl(__io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); ++ writel(val | (1 << data), __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i)); ++ } ++#endif ++ } else if (d->irq >= ARM_IRQ1_BASE && d->irq < ARM_IRQ_LOCAL_BASE) { ++ if (force_core) { ++ unsigned int data; ++ data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING)); ++ data &= ~0x3; ++ data |= ((force_core-1) << 0); ++ writel(data, __io_address(ARM_LOCAL_GPU_INT_ROUTING)); ++ } ++ unsigned int data = (unsigned int)irq_get_chip_data(d->irq); ++ writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3])); ++ } else if (d->irq == INTERRUPT_ARM_LOCAL_PMU_FAST) { ++ writel(0xf, __io_address(ARM_LOCAL_PM_ROUTING_SET)); ++ } else { printk("%s: %d\n", __func__, d->irq); BUG(); } ++} ++ ++#ifdef CONFIG_OF ++ ++#define NR_IRQS_BANK0 21 ++#define NR_BANKS 4 ++#define IRQS_PER_BANK 32 ++ ++/* from drivers/irqchip/irq-bcm2835.c */ ++static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr, ++ const u32 *intspec, unsigned int intsize, ++ unsigned long *out_hwirq, unsigned int *out_type) ++{ ++ if (WARN_ON(intsize != 2)) ++ return -EINVAL; ++ ++ if (WARN_ON(intspec[0] >= NR_BANKS)) ++ return -EINVAL; ++ ++ if (WARN_ON(intspec[1] >= IRQS_PER_BANK)) ++ return -EINVAL; ++ ++ if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0)) ++ return -EINVAL; ++ ++ if (WARN_ON(intspec[0] == 3 && intspec[1] > 3 && intspec[1] != 5 && intspec[1] != 9)) ++ return -EINVAL; ++ ++ if (intspec[0] == 0) ++ *out_hwirq = ARM_IRQ0_BASE + intspec[1]; ++ else if (intspec[0] == 1) ++ *out_hwirq = ARM_IRQ1_BASE + intspec[1]; ++ else if (intspec[0] == 2) ++ *out_hwirq = ARM_IRQ2_BASE + intspec[1]; ++ else ++ *out_hwirq = ARM_IRQ_LOCAL_BASE + intspec[1]; ++ ++ /* reverse remap_irqs[] */ ++ switch (*out_hwirq) { ++ case INTERRUPT_VC_JPEG: ++ *out_hwirq = INTERRUPT_JPEG; ++ break; ++ case INTERRUPT_VC_USB: ++ *out_hwirq = INTERRUPT_USB; ++ break; ++ case INTERRUPT_VC_3D: ++ *out_hwirq = INTERRUPT_3D; ++ break; ++ case INTERRUPT_VC_DMA2: ++ *out_hwirq = INTERRUPT_DMA2; ++ break; ++ case INTERRUPT_VC_DMA3: ++ *out_hwirq = INTERRUPT_DMA3; ++ break; ++ case INTERRUPT_VC_I2C: ++ *out_hwirq = INTERRUPT_I2C; ++ break; ++ case INTERRUPT_VC_SPI: ++ *out_hwirq = INTERRUPT_SPI; ++ break; ++ case INTERRUPT_VC_I2SPCM: ++ *out_hwirq = INTERRUPT_I2SPCM; ++ break; ++ case INTERRUPT_VC_SDIO: ++ *out_hwirq = INTERRUPT_SDIO; ++ break; ++ case INTERRUPT_VC_UART: ++ *out_hwirq = INTERRUPT_UART; ++ break; ++ case INTERRUPT_VC_ARASANSDIO: ++ *out_hwirq = INTERRUPT_ARASANSDIO; ++ break; ++ } ++ ++ *out_type = IRQ_TYPE_NONE; ++ return 0; ++} ++ ++static struct irq_domain_ops armctrl_ops = { ++ .xlate = armctrl_xlate ++}; ++ ++void __init armctrl_dt_init(void) ++{ ++ struct device_node *np; ++ struct irq_domain *domain; ++ ++ np = of_find_compatible_node(NULL, NULL, "brcm,bcm2708-armctrl-ic"); ++ if (!np) ++ return; ++ ++ domain = irq_domain_add_legacy(np, BCM2708_ALLOC_IRQS, ++ IRQ_ARMCTRL_START, 0, ++ &armctrl_ops, NULL); ++ WARN_ON(!domain); ++} ++#else ++void __init armctrl_dt_init(void) { } ++#endif /* CONFIG_OF */ ++ ++#if defined(CONFIG_PM) ++ ++/* for kernels 3.xx use the new syscore_ops apis but for older kernels use the sys dev class */ ++ ++/* Static defines ++ * struct armctrl_device - VIC PM device (< 3.xx) ++ * @sysdev: The system device which is registered. (< 3.xx) ++ * @irq: The IRQ number for the base of the VIC. ++ * @base: The register base for the VIC. ++ * @resume_sources: A bitmask of interrupts for resume. ++ * @resume_irqs: The IRQs enabled for resume. ++ * @int_select: Save for VIC_INT_SELECT. ++ * @int_enable: Save for VIC_INT_ENABLE. ++ * @soft_int: Save for VIC_INT_SOFT. ++ * @protect: Save for VIC_PROTECT. ++ */ ++struct armctrl_info { ++ void __iomem *base; ++ int irq; ++ u32 resume_sources; ++ u32 resume_irqs; ++ u32 int_select; ++ u32 int_enable; ++ u32 soft_int; ++ u32 protect; ++} armctrl; ++ ++static int armctrl_suspend(void) ++{ ++ return 0; ++} ++ ++static void armctrl_resume(void) ++{ ++ return; ++} ++ ++/** ++ * armctrl_pm_register - Register a VIC for later power management control ++ * @base: The base address of the VIC. ++ * @irq: The base IRQ for the VIC. ++ * @resume_sources: bitmask of interrupts allowed for resume sources. ++ * ++ * For older kernels (< 3.xx) do - ++ * Register the VIC with the system device tree so that it can be notified ++ * of suspend and resume requests and ensure that the correct actions are ++ * taken to re-instate the settings on resume. ++ */ ++static void __init armctrl_pm_register(void __iomem * base, unsigned int irq, ++ u32 resume_sources) ++{ ++ armctrl.base = base; ++ armctrl.resume_sources = resume_sources; ++ armctrl.irq = irq; ++} ++ ++static int armctrl_set_wake(struct irq_data *d, unsigned int on) ++{ ++ unsigned int off = d->irq & 31; ++ u32 bit = 1 << off; ++ ++ if (!(bit & armctrl.resume_sources)) ++ return -EINVAL; ++ ++ if (on) ++ armctrl.resume_irqs |= bit; ++ else ++ armctrl.resume_irqs &= ~bit; ++ ++ return 0; ++} ++ ++#else ++static inline void armctrl_pm_register(void __iomem * base, unsigned int irq, ++ u32 arg1) ++{ ++} ++ ++#define armctrl_suspend NULL ++#define armctrl_resume NULL ++#define armctrl_set_wake NULL ++#endif /* CONFIG_PM */ ++ ++static struct syscore_ops armctrl_syscore_ops = { ++ .suspend = armctrl_suspend, ++ .resume = armctrl_resume, ++}; ++ ++/** ++ * armctrl_syscore_init - initicall to register VIC pm functions ++ * ++ * This is called via late_initcall() to register ++ * the resources for the VICs due to the early ++ * nature of the VIC's registration. ++*/ ++static int __init armctrl_syscore_init(void) ++{ ++ register_syscore_ops(&armctrl_syscore_ops); ++ return 0; ++} ++ ++late_initcall(armctrl_syscore_init); ++ ++static struct irq_chip armctrl_chip = { ++ .name = "ARMCTRL", ++ .irq_ack = NULL, ++ .irq_mask = armctrl_mask_irq, ++ .irq_unmask = armctrl_unmask_irq, ++ .irq_set_wake = armctrl_set_wake, ++}; ++ ++/** ++ * armctrl_init - initialise a vectored interrupt controller ++ * @base: iomem base address ++ * @irq_start: starting interrupt number, must be muliple of 32 ++ * @armctrl_sources: bitmask of interrupt sources to allow ++ * @resume_sources: bitmask of interrupt sources to allow for resume ++ */ ++int __init armctrl_init(void __iomem * base, unsigned int irq_start, ++ u32 armctrl_sources, u32 resume_sources) ++{ ++ unsigned int irq; ++ ++ for (irq = 0; irq < BCM2708_ALLOC_IRQS; irq++) { ++ unsigned int data = irq; ++ if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO) ++ data = remap_irqs[irq - INTERRUPT_JPEG]; ++ if (irq >= IRQ_ARM_LOCAL_CNTPSIRQ && irq <= IRQ_ARM_LOCAL_TIMER) { ++ irq_set_percpu_devid(irq); ++ irq_set_chip_and_handler(irq, &armctrl_chip, handle_percpu_devid_irq); ++ set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN); ++ } else { ++ irq_set_chip_and_handler(irq, &armctrl_chip, handle_level_irq); ++ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); ++ } ++ irq_set_chip_data(irq, (void *)data); ++ } ++ ++ armctrl_pm_register(base, irq_start, resume_sources); ++ init_FIQ(FIQ_START); ++ armctrl_dt_init(); ++ return 0; ++} +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/armctrl.h linux-rpi/arch/arm/mach-bcm2709/armctrl.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2709/armctrl.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2709/armctrl.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,27 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/armctrl.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef __BCM2708_ARMCTRL_H ++#define __BCM2708_ARMCTRL_H ++ ++extern int __init armctrl_init(void __iomem * base, unsigned int irq_start, ++ u32 armctrl_sources, u32 resume_sources); ++ ++#endif +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/bcm2708_gpio.c linux-rpi/arch/arm/mach-bcm2709/bcm2708_gpio.c +--- linux-4.1.13.orig/arch/arm/mach-bcm2709/bcm2708_gpio.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2709/bcm2708_gpio.c 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,426 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/bcm2708_gpio.c ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio" ++#define DRIVER_NAME BCM_GPIO_DRIVER_NAME ++#define BCM_GPIO_USE_IRQ 1 ++ ++#define GPIOFSEL(x) (0x00+(x)*4) ++#define GPIOSET(x) (0x1c+(x)*4) ++#define GPIOCLR(x) (0x28+(x)*4) ++#define GPIOLEV(x) (0x34+(x)*4) ++#define GPIOEDS(x) (0x40+(x)*4) ++#define GPIOREN(x) (0x4c+(x)*4) ++#define GPIOFEN(x) (0x58+(x)*4) ++#define GPIOHEN(x) (0x64+(x)*4) ++#define GPIOLEN(x) (0x70+(x)*4) ++#define GPIOAREN(x) (0x7c+(x)*4) ++#define GPIOAFEN(x) (0x88+(x)*4) ++#define GPIOUD(x) (0x94+(x)*4) ++#define GPIOUDCLK(x) (0x98+(x)*4) ++ ++#define GPIO_BANKS 2 ++ ++enum { GPIO_FSEL_INPUT, GPIO_FSEL_OUTPUT, ++ GPIO_FSEL_ALT5, GPIO_FSEL_ALT_4, ++ GPIO_FSEL_ALT0, GPIO_FSEL_ALT1, ++ GPIO_FSEL_ALT2, GPIO_FSEL_ALT3, ++}; ++ ++ /* Each of the two spinlocks protects a different set of hardware ++ * regiters and data structurs. This decouples the code of the IRQ from ++ * the GPIO code. This also makes the case of a GPIO routine call from ++ * the IRQ code simpler. ++ */ ++static DEFINE_SPINLOCK(lock); /* GPIO registers */ ++ ++struct bcm2708_gpio { ++ struct list_head list; ++ void __iomem *base; ++ struct gpio_chip gc; ++ unsigned long rising[(BCM2708_NR_GPIOS + 31) / 32]; ++ unsigned long falling[(BCM2708_NR_GPIOS + 31) / 32]; ++ unsigned long high[(BCM2708_NR_GPIOS + 31) / 32]; ++ unsigned long low[(BCM2708_NR_GPIOS + 31) / 32]; ++}; ++ ++static int bcm2708_set_function(struct gpio_chip *gc, unsigned offset, ++ int function) ++{ ++ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); ++ unsigned long flags; ++ unsigned gpiodir; ++ unsigned gpio_bank = offset / 10; ++ unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3; ++ ++//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set_function %p (%d,%d)\n", gc, offset, function); ++ if (offset >= BCM2708_NR_GPIOS) ++ return -EINVAL; ++ ++ spin_lock_irqsave(&lock, flags); ++ ++ gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank)); ++ gpiodir &= ~(7 << gpio_field_offset); ++ gpiodir |= function << gpio_field_offset; ++ writel(gpiodir, gpio->base + GPIOFSEL(gpio_bank)); ++ spin_unlock_irqrestore(&lock, flags); ++ gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank)); ++ ++ return 0; ++} ++ ++static int bcm2708_gpio_dir_in(struct gpio_chip *gc, unsigned offset) ++{ ++ return bcm2708_set_function(gc, offset, GPIO_FSEL_INPUT); ++} ++ ++static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value); ++static int bcm2708_gpio_dir_out(struct gpio_chip *gc, unsigned offset, ++ int value) ++{ ++ int ret; ++ ret = bcm2708_set_function(gc, offset, GPIO_FSEL_OUTPUT); ++ if (ret >= 0) ++ bcm2708_gpio_set(gc, offset, value); ++ return ret; ++} ++ ++static int bcm2708_gpio_get(struct gpio_chip *gc, unsigned offset) ++{ ++ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); ++ unsigned gpio_bank = offset / 32; ++ unsigned gpio_field_offset = (offset - 32 * gpio_bank); ++ unsigned lev; ++ ++ if (offset >= BCM2708_NR_GPIOS) ++ return 0; ++ lev = readl(gpio->base + GPIOLEV(gpio_bank)); ++//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_get %p (%d)=%d\n", gc, offset, 0x1 & (lev>>gpio_field_offset)); ++ return 0x1 & (lev >> gpio_field_offset); ++} ++ ++static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value) ++{ ++ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); ++ unsigned gpio_bank = offset / 32; ++ unsigned gpio_field_offset = (offset - 32 * gpio_bank); ++//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set %p (%d=%d)\n", gc, offset, value); ++ if (offset >= BCM2708_NR_GPIOS) ++ return; ++ if (value) ++ writel(1 << gpio_field_offset, gpio->base + GPIOSET(gpio_bank)); ++ else ++ writel(1 << gpio_field_offset, gpio->base + GPIOCLR(gpio_bank)); ++} ++ ++/********************** ++ * extension to configure pullups ++ */ ++int bcm2708_gpio_setpull(struct gpio_chip *gc, unsigned offset, ++ bcm2708_gpio_pull_t value) ++{ ++ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); ++ unsigned gpio_bank = offset / 32; ++ unsigned gpio_field_offset = (offset - 32 * gpio_bank); ++ ++ if (offset >= BCM2708_NR_GPIOS) ++ return -EINVAL; ++ ++ switch (value) { ++ case BCM2708_PULL_UP: ++ writel(2, gpio->base + GPIOUD(0)); ++ break; ++ case BCM2708_PULL_DOWN: ++ writel(1, gpio->base + GPIOUD(0)); ++ break; ++ case BCM2708_PULL_OFF: ++ writel(0, gpio->base + GPIOUD(0)); ++ break; ++ } ++ ++ udelay(5); ++ writel(1 << gpio_field_offset, gpio->base + GPIOUDCLK(gpio_bank)); ++ udelay(5); ++ writel(0, gpio->base + GPIOUD(0)); ++ writel(0 << gpio_field_offset, gpio->base + GPIOUDCLK(gpio_bank)); ++ ++ return 0; ++} ++EXPORT_SYMBOL(bcm2708_gpio_setpull); ++ ++/************************************************************************************************************************* ++ * bcm2708 GPIO IRQ ++ */ ++ ++#if BCM_GPIO_USE_IRQ ++ ++static int bcm2708_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) ++{ ++ return gpio_to_irq(gpio); ++} ++ ++static int bcm2708_gpio_irq_set_type(struct irq_data *d, unsigned type) ++{ ++ unsigned irq = d->irq; ++ struct bcm2708_gpio *gpio = irq_get_chip_data(irq); ++ unsigned gn = irq_to_gpio(irq); ++ unsigned gb = gn / 32; ++ unsigned go = gn % 32; ++ ++ gpio->rising[gb] &= ~(1 << go); ++ gpio->falling[gb] &= ~(1 << go); ++ gpio->high[gb] &= ~(1 << go); ++ gpio->low[gb] &= ~(1 << go); ++ ++ if (type & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) ++ return -EINVAL; ++ ++ if (type & IRQ_TYPE_EDGE_RISING) ++ gpio->rising[gb] |= (1 << go); ++ if (type & IRQ_TYPE_EDGE_FALLING) ++ gpio->falling[gb] |= (1 << go); ++ if (type & IRQ_TYPE_LEVEL_HIGH) ++ gpio->high[gb] |= (1 << go); ++ if (type & IRQ_TYPE_LEVEL_LOW) ++ gpio->low[gb] |= (1 << go); ++ return 0; ++} ++ ++static void bcm2708_gpio_irq_mask(struct irq_data *d) ++{ ++ unsigned irq = d->irq; ++ struct bcm2708_gpio *gpio = irq_get_chip_data(irq); ++ unsigned gn = irq_to_gpio(irq); ++ unsigned gb = gn / 32; ++ unsigned long rising = readl(gpio->base + GPIOREN(gb)); ++ unsigned long falling = readl(gpio->base + GPIOFEN(gb)); ++ unsigned long high = readl(gpio->base + GPIOHEN(gb)); ++ unsigned long low = readl(gpio->base + GPIOLEN(gb)); ++ ++ gn = gn % 32; ++ ++ writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb)); ++ writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb)); ++ writel(high & ~(1 << gn), gpio->base + GPIOHEN(gb)); ++ writel(low & ~(1 << gn), gpio->base + GPIOLEN(gb)); ++} ++ ++static void bcm2708_gpio_irq_unmask(struct irq_data *d) ++{ ++ unsigned irq = d->irq; ++ struct bcm2708_gpio *gpio = irq_get_chip_data(irq); ++ unsigned gn = irq_to_gpio(irq); ++ unsigned gb = gn / 32; ++ unsigned go = gn % 32; ++ unsigned long rising = readl(gpio->base + GPIOREN(gb)); ++ unsigned long falling = readl(gpio->base + GPIOFEN(gb)); ++ unsigned long high = readl(gpio->base + GPIOHEN(gb)); ++ unsigned long low = readl(gpio->base + GPIOLEN(gb)); ++ ++ if (gpio->rising[gb] & (1 << go)) { ++ writel(rising | (1 << go), gpio->base + GPIOREN(gb)); ++ } else { ++ writel(rising & ~(1 << go), gpio->base + GPIOREN(gb)); ++ } ++ ++ if (gpio->falling[gb] & (1 << go)) { ++ writel(falling | (1 << go), gpio->base + GPIOFEN(gb)); ++ } else { ++ writel(falling & ~(1 << go), gpio->base + GPIOFEN(gb)); ++ } ++ ++ if (gpio->high[gb] & (1 << go)) { ++ writel(high | (1 << go), gpio->base + GPIOHEN(gb)); ++ } else { ++ writel(high & ~(1 << go), gpio->base + GPIOHEN(gb)); ++ } ++ ++ if (gpio->low[gb] & (1 << go)) { ++ writel(low | (1 << go), gpio->base + GPIOLEN(gb)); ++ } else { ++ writel(low & ~(1 << go), gpio->base + GPIOLEN(gb)); ++ } ++} ++ ++static struct irq_chip bcm2708_irqchip = { ++ .name = "GPIO", ++ .irq_enable = bcm2708_gpio_irq_unmask, ++ .irq_disable = bcm2708_gpio_irq_mask, ++ .irq_unmask = bcm2708_gpio_irq_unmask, ++ .irq_mask = bcm2708_gpio_irq_mask, ++ .irq_set_type = bcm2708_gpio_irq_set_type, ++}; ++ ++static irqreturn_t bcm2708_gpio_interrupt(int irq, void *dev_id) ++{ ++ unsigned long edsr; ++ unsigned bank; ++ int i; ++ unsigned gpio; ++ unsigned level_bits; ++ struct bcm2708_gpio *gpio_data = dev_id; ++ ++ for (bank = 0; bank < GPIO_BANKS; bank++) { ++ edsr = readl(__io_address(GPIO_BASE) + GPIOEDS(bank)); ++ level_bits = gpio_data->high[bank] | gpio_data->low[bank]; ++ ++ for_each_set_bit(i, &edsr, 32) { ++ gpio = i + bank * 32; ++ /* ack edge triggered IRQs immediately */ ++ if (!(level_bits & (1<gc.to_irq = bcm2708_gpio_to_irq; ++ ++ for (irq = GPIO_IRQ_START; irq < (GPIO_IRQ_START + GPIO_IRQS); irq++) { ++ irq_set_chip_data(irq, ucb); ++ irq_set_chip_and_handler(irq, &bcm2708_irqchip, ++ handle_simple_irq); ++ set_irq_flags(irq, IRQF_VALID); ++ } ++ ++ bcm2708_gpio_irq.dev_id = ucb; ++ setup_irq(IRQ_GPIO3, &bcm2708_gpio_irq); ++} ++ ++#else ++ ++static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb) ++{ ++} ++ ++#endif /* #if BCM_GPIO_USE_IRQ ***************************************************************************************************************** */ ++ ++static int bcm2708_gpio_probe(struct platform_device *dev) ++{ ++ struct bcm2708_gpio *ucb; ++ struct resource *res; ++ int bank; ++ int err = 0; ++ ++ printk(KERN_INFO DRIVER_NAME ": bcm2708_gpio_probe %p\n", dev); ++ ++ ucb = kzalloc(sizeof(*ucb), GFP_KERNEL); ++ if (NULL == ucb) { ++ printk(KERN_ERR DRIVER_NAME ": failed to allocate " ++ "mailbox memory\n"); ++ err = -ENOMEM; ++ goto err; ++ } ++ ++ res = platform_get_resource(dev, IORESOURCE_MEM, 0); ++ ++ platform_set_drvdata(dev, ucb); ++ ucb->base = __io_address(GPIO_BASE); ++ ++ ucb->gc.label = "bcm2708_gpio"; ++ ucb->gc.base = 0; ++ ucb->gc.ngpio = BCM2708_NR_GPIOS; ++ ucb->gc.owner = THIS_MODULE; ++ ++ ucb->gc.direction_input = bcm2708_gpio_dir_in; ++ ucb->gc.direction_output = bcm2708_gpio_dir_out; ++ ucb->gc.get = bcm2708_gpio_get; ++ ucb->gc.set = bcm2708_gpio_set; ++ ucb->gc.can_sleep = 0; ++ ++ for (bank = 0; bank < GPIO_BANKS; bank++) { ++ writel(0, ucb->base + GPIOREN(bank)); ++ writel(0, ucb->base + GPIOFEN(bank)); ++ writel(0, ucb->base + GPIOHEN(bank)); ++ writel(0, ucb->base + GPIOLEN(bank)); ++ writel(0, ucb->base + GPIOAREN(bank)); ++ writel(0, ucb->base + GPIOAFEN(bank)); ++ writel(~0, ucb->base + GPIOEDS(bank)); ++ } ++ ++ bcm2708_gpio_irq_init(ucb); ++ ++ err = gpiochip_add(&ucb->gc); ++ ++err: ++ return err; ++ ++} ++ ++static int bcm2708_gpio_remove(struct platform_device *dev) ++{ ++ int err = 0; ++ struct bcm2708_gpio *ucb = platform_get_drvdata(dev); ++ ++ printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_remove %p\n", dev); ++ ++ gpiochip_remove(&ucb->gc); ++ ++ platform_set_drvdata(dev, NULL); ++ kfree(ucb); ++ ++ return err; ++} ++ ++static struct platform_driver bcm2708_gpio_driver = { ++ .probe = bcm2708_gpio_probe, ++ .remove = bcm2708_gpio_remove, ++ .driver = { ++ .name = "bcm2708_gpio"}, ++}; ++ ++static int __init bcm2708_gpio_init(void) ++{ ++ return platform_driver_register(&bcm2708_gpio_driver); ++} ++ ++static void __exit bcm2708_gpio_exit(void) ++{ ++ platform_driver_unregister(&bcm2708_gpio_driver); ++} ++ ++module_init(bcm2708_gpio_init); ++module_exit(bcm2708_gpio_exit); ++ ++MODULE_DESCRIPTION("Broadcom BCM2708 GPIO driver"); ++MODULE_LICENSE("GPL"); +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/bcm2709.c linux-rpi/arch/arm/mach-bcm2709/bcm2709.c +--- linux-4.1.13.orig/arch/arm/mach-bcm2709/bcm2709.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2709/bcm2709.c 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,1332 @@ ++/* ++ * linux/arch/arm/mach-bcm2709/bcm2709.c ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++ ++#include "bcm2709.h" ++#include "armctrl.h" ++ ++#ifdef CONFIG_BCM_VC_CMA ++#include ++#endif ++ ++//#define SYSTEM_TIMER ++ ++/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to ++ * give us IO access only to 64Mbytes of physical memory (26 bits). We could ++ * represent this window by setting our dmamasks to 26 bits but, in fact ++ * we're not going to use addresses outside this range (they're not in real ++ * memory) so we don't bother. ++ * ++ * In the future we might include code to use this IOMMU to remap other ++ * physical addresses onto VideoCore memory then the use of 32-bits would be ++ * more legitimate. ++ */ ++#define DMA_MASK_BITS_COMMON 32 ++ ++// use GPIO 4 for the one-wire GPIO pin, if enabled ++#define W1_GPIO 4 ++// ensure one-wire GPIO pullup is disabled by default ++#define W1_PULLUP -1 ++ ++/* command line parameters */ ++static unsigned boardrev, serial; ++static unsigned uart_clock = UART0_CLOCK; ++static unsigned disk_led_gpio = 16; ++static unsigned disk_led_active_low = 1; ++static unsigned reboot_part = 0; ++static unsigned w1_gpio_pin = W1_GPIO; ++static unsigned w1_gpio_pullup = W1_PULLUP; ++static bool vc_i2c_override = false; ++static int pps_gpio_pin = -1; ++unsigned force_core; ++ ++static unsigned use_dt = 0; ++ ++static void __init bcm2709_init_led(void); ++ ++void __init bcm2709_init_irq(void) ++{ ++ armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0); ++} ++ ++static struct map_desc bcm2709_io_desc[] __initdata = { ++ { ++ .virtual = IO_ADDRESS(ARMCTRL_BASE), ++ .pfn = __phys_to_pfn(ARMCTRL_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(UART0_BASE), ++ .pfn = __phys_to_pfn(UART0_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(UART1_BASE), ++ .pfn = __phys_to_pfn(UART1_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(DMA_BASE), ++ .pfn = __phys_to_pfn(DMA_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(MCORE_BASE), ++ .pfn = __phys_to_pfn(MCORE_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(ST_BASE), ++ .pfn = __phys_to_pfn(ST_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(USB_BASE), ++ .pfn = __phys_to_pfn(USB_BASE), ++ .length = SZ_128K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(PM_BASE), ++ .pfn = __phys_to_pfn(PM_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(GPIO_BASE), ++ .pfn = __phys_to_pfn(GPIO_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(ARM_LOCAL_BASE), ++ .pfn = __phys_to_pfn(ARM_LOCAL_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++}; ++ ++void __init bcm2709_map_io(void) ++{ ++ iotable_init(bcm2709_io_desc, ARRAY_SIZE(bcm2709_io_desc)); ++} ++ ++#ifdef SYSTEM_TIMER ++ ++/* The STC is a free running counter that increments at the rate of 1MHz */ ++#define STC_FREQ_HZ 1000000 ++ ++static inline uint32_t timer_read(void) ++{ ++ /* STC: a free running counter that increments at the rate of 1MHz */ ++ return readl(__io_address(ST_BASE + 0x04)); ++} ++ ++static unsigned long bcm2709_read_current_timer(void) ++{ ++ return timer_read(); ++} ++ ++static u64 notrace bcm2709_read_sched_clock(void) ++{ ++ return timer_read(); ++} ++ ++static cycle_t clksrc_read(struct clocksource *cs) ++{ ++ return timer_read(); ++} ++ ++static struct clocksource clocksource_stc = { ++ .name = "stc", ++ .rating = 300, ++ .read = clksrc_read, ++ .mask = CLOCKSOURCE_MASK(32), ++ .flags = CLOCK_SOURCE_IS_CONTINUOUS, ++}; ++ ++unsigned long frc_clock_ticks32(void) ++{ ++ return timer_read(); ++} ++ ++static void __init bcm2709_clocksource_init(void) ++{ ++ if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) { ++ printk(KERN_ERR "timer: failed to initialize clock " ++ "source %s\n", clocksource_stc.name); ++ } ++} ++#endif ++ ++struct clk __init *bcm2709_clk_register(const char *name, unsigned long fixed_rate) ++{ ++ struct clk *clk; ++ ++ clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, ++ fixed_rate); ++ if (IS_ERR(clk)) ++ pr_err("%s not registered\n", name); ++ ++ return clk; ++} ++ ++void __init bcm2709_register_clkdev(struct clk *clk, const char *name) ++{ ++ int ret; ++ ++ ret = clk_register_clkdev(clk, NULL, name); ++ if (ret) ++ pr_err("%s alias not registered\n", name); ++} ++ ++void __init bcm2709_init_clocks(void) ++{ ++ struct clk *clk; ++ ++ clk = bcm2709_clk_register("uart0_clk", uart_clock); ++ bcm2709_register_clkdev(clk, "dev:f1"); ++ ++ clk = bcm2709_clk_register("sdhost_clk", 250000000); ++ bcm2709_register_clkdev(clk, "mmc-bcm2835.0"); ++ bcm2709_register_clkdev(clk, "bcm2708_spi.0"); ++ bcm2709_register_clkdev(clk, "bcm2708_i2c.0"); ++ bcm2709_register_clkdev(clk, "bcm2708_i2c.1"); ++} ++ ++#define UART0_IRQ { IRQ_UART, 0 /*NO_IRQ*/ } ++#define UART0_DMA { 15, 14 } ++ ++AMBA_DEVICE(uart0, "dev:f1", UART0, NULL); ++ ++static struct amba_device *amba_devs[] __initdata = { ++ &uart0_device, ++}; ++ ++static struct resource bcm2708_dmaengine_resources[] = { ++ { ++ .start = DMA_BASE, ++ .end = DMA_BASE + SZ_4K - 1, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .start = IRQ_DMA0, ++ .end = IRQ_DMA0, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA1, ++ .end = IRQ_DMA1, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA2, ++ .end = IRQ_DMA2, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA3, ++ .end = IRQ_DMA3, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA4, ++ .end = IRQ_DMA4, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA5, ++ .end = IRQ_DMA5, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA6, ++ .end = IRQ_DMA6, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA7, ++ .end = IRQ_DMA7, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA8, ++ .end = IRQ_DMA8, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA9, ++ .end = IRQ_DMA9, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA10, ++ .end = IRQ_DMA10, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA11, ++ .end = IRQ_DMA11, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .start = IRQ_DMA12, ++ .end = IRQ_DMA12, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct platform_device bcm2708_dmaengine_device = { ++ .name = "bcm2708-dmaengine", ++ .id = -1, ++ .resource = bcm2708_dmaengine_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_dmaengine_resources), ++}; ++ ++#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE) ++static struct w1_gpio_platform_data w1_gpio_pdata = { ++ .pin = W1_GPIO, ++ .ext_pullup_enable_pin = W1_PULLUP, ++ .is_open_drain = 0, ++}; ++ ++static struct platform_device w1_device = { ++ .name = "w1-gpio", ++ .id = -1, ++ .dev.platform_data = &w1_gpio_pdata, ++}; ++#endif ++ ++static struct pps_gpio_platform_data pps_gpio_info = { ++ .assert_falling_edge = false, ++ .capture_clear = false, ++ .gpio_pin = -1, ++ .gpio_label = "PPS", ++}; ++ ++static struct platform_device pps_gpio_device = { ++ .name = "pps-gpio", ++ .id = PLATFORM_DEVID_NONE, ++ .dev.platform_data = &pps_gpio_info, ++}; ++ ++static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++ ++static struct platform_device bcm2708_fb_device = { ++ .name = "bcm2708_fb", ++ .id = -1, /* only one bcm2708_fb */ ++ .resource = NULL, ++ .num_resources = 0, ++ .dev = { ++ .dma_mask = &fb_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, ++}; ++ ++static struct resource bcm2708_usb_resources[] = { ++ [0] = { ++ .start = USB_BASE, ++ .end = USB_BASE + SZ_128K - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = MPHI_BASE, ++ .end = MPHI_BASE + SZ_4K - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [2] = { ++ .start = IRQ_HOSTPORT, ++ .end = IRQ_HOSTPORT, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [3] = { ++ .start = IRQ_USB, ++ .end = IRQ_USB, ++ .flags = IORESOURCE_IRQ, ++ }, ++ [4] = { ++ .start = ARM_LOCAL_BASE, ++ .end = ARM_LOCAL_BASE + SZ_4K - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [5] = { ++ .start = IRQ_ARM_LOCAL_MAILBOX1, ++ .end = IRQ_ARM_LOCAL_MAILBOX1, ++ .flags = IORESOURCE_IRQ ++ }, ++}; ++ ++ ++static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++ ++static struct platform_device bcm2708_usb_device = { ++ .name = "bcm2708_usb", ++ .id = -1, /* only one bcm2708_usb */ ++ .resource = bcm2708_usb_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_usb_resources), ++ .dev = { ++ .dma_mask = &usb_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, ++}; ++ ++static struct resource bcm2708_vcio_resources[] = { ++ { ++ .start = ARMCTRL_0_MAIL0_BASE, ++ .end = ARMCTRL_0_MAIL0_BASE + SZ_64 - 1, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .start = IRQ_ARM_MAILBOX, ++ .end = IRQ_ARM_MAILBOX, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static u64 vcio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++ ++static struct platform_device bcm2708_vcio_device = { ++ .name = "bcm2835-mbox", ++ .id = -1, /* only one VideoCore I/O area */ ++ .resource = bcm2708_vcio_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_vcio_resources), ++ .dev = { ++ .dma_mask = &vcio_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, ++}; ++ ++static u64 rpifw_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++ ++static struct platform_device bcm2708_rpifw_device = { ++ .name = "raspberrypi-firmware", ++ .dev = { ++ .dma_mask = &rpifw_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, ++}; ++ ++static struct resource bcm2708_vchiq_resources[] = { ++ { ++ .start = ARMCTRL_0_BELL_BASE, ++ .end = ARMCTRL_0_BELL_BASE + 16, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .start = IRQ_ARM_DOORBELL_0, ++ .end = IRQ_ARM_DOORBELL_0, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static u64 vchiq_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++ ++static struct platform_device bcm2708_vchiq_device = { ++ .name = "bcm2835_vchiq", ++ .id = -1, ++ .resource = bcm2708_vchiq_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_vchiq_resources), ++ .dev = { ++ .dma_mask = &vchiq_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, ++}; ++ ++#ifdef CONFIG_BCM2708_GPIO ++#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio" ++ ++static struct resource bcm2708_gpio_resources[] = { ++ [0] = { /* general purpose I/O */ ++ .start = GPIO_BASE, ++ .end = GPIO_BASE + SZ_4K - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++}; ++ ++static u64 gpio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++ ++static struct platform_device bcm2708_gpio_device = { ++ .name = BCM_GPIO_DRIVER_NAME, ++ .id = -1, /* only one VideoCore I/O area */ ++ .resource = bcm2708_gpio_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_gpio_resources), ++ .dev = { ++ .dma_mask = &gpio_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, ++}; ++#endif ++ ++#ifdef CONFIG_MMC_BCM2835 /* Arasan emmc SD (new) */ ++static struct resource bcm2835_emmc_resources[] = { ++ [0] = { ++ .start = EMMC_BASE, ++ .end = EMMC_BASE + SZ_256 - 1, /* we only need this area */ ++ /* the memory map actually makes SZ_4K available */ ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_ARASANSDIO, ++ .end = IRQ_ARASANSDIO, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static u64 bcm2835_emmc_dmamask = 0xffffffffUL; ++ ++struct platform_device bcm2835_emmc_device = { ++ .name = "mmc-bcm2835", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(bcm2835_emmc_resources), ++ .resource = bcm2835_emmc_resources, ++ .dev = { ++ .dma_mask = &bcm2835_emmc_dmamask, ++ .coherent_dma_mask = 0xffffffffUL}, ++}; ++#endif /* CONFIG_MMC_BCM2835 */ ++ ++static struct platform_device bcm2708_alsa_devices[] = { ++ [0] = { ++ .name = "bcm2835_AUD0", ++ .id = 0, /* first audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++ [1] = { ++ .name = "bcm2835_AUD1", ++ .id = 1, /* second audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++ [2] = { ++ .name = "bcm2835_AUD2", ++ .id = 2, /* third audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++ [3] = { ++ .name = "bcm2835_AUD3", ++ .id = 3, /* forth audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++ [4] = { ++ .name = "bcm2835_AUD4", ++ .id = 4, /* fifth audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++ [5] = { ++ .name = "bcm2835_AUD5", ++ .id = 5, /* sixth audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++ [6] = { ++ .name = "bcm2835_AUD6", ++ .id = 6, /* seventh audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++ [7] = { ++ .name = "bcm2835_AUD7", ++ .id = 7, /* eighth audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++}; ++ ++static struct resource bcm2708_spi_resources[] = { ++ { ++ .start = SPI0_BASE, ++ .end = SPI0_BASE + SZ_256 - 1, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .start = IRQ_SPI, ++ .end = IRQ_SPI, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++ ++static u64 bcm2708_spi_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++static struct platform_device bcm2708_spi_device = { ++ .name = "bcm2708_spi", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(bcm2708_spi_resources), ++ .resource = bcm2708_spi_resources, ++ .dev = { ++ .dma_mask = &bcm2708_spi_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON)}, ++}; ++ ++#ifdef CONFIG_BCM2708_SPIDEV ++static struct spi_board_info bcm2708_spi_devices[] = { ++#ifdef CONFIG_SPI_SPIDEV ++ { ++ .modalias = "spidev", ++ .max_speed_hz = 500000, ++ .bus_num = 0, ++ .chip_select = 0, ++ .mode = SPI_MODE_0, ++ }, { ++ .modalias = "spidev", ++ .max_speed_hz = 500000, ++ .bus_num = 0, ++ .chip_select = 1, ++ .mode = SPI_MODE_0, ++ } ++#endif ++}; ++#endif ++ ++static struct resource bcm2708_bsc0_resources[] = { ++ { ++ .start = BSC0_BASE, ++ .end = BSC0_BASE + SZ_256 - 1, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .start = INTERRUPT_I2C, ++ .end = INTERRUPT_I2C, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct platform_device bcm2708_bsc0_device = { ++ .name = "bcm2708_i2c", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(bcm2708_bsc0_resources), ++ .resource = bcm2708_bsc0_resources, ++}; ++ ++ ++static struct resource bcm2708_bsc1_resources[] = { ++ { ++ .start = BSC1_BASE, ++ .end = BSC1_BASE + SZ_256 - 1, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .start = INTERRUPT_I2C, ++ .end = INTERRUPT_I2C, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct platform_device bcm2708_bsc1_device = { ++ .name = "bcm2708_i2c", ++ .id = 1, ++ .num_resources = ARRAY_SIZE(bcm2708_bsc1_resources), ++ .resource = bcm2708_bsc1_resources, ++}; ++ ++static struct platform_device bcm2835_thermal_device = { ++ .name = "bcm2835_thermal", ++}; ++ ++#if defined(CONFIG_SND_BCM2708_SOC_I2S) || defined(CONFIG_SND_BCM2708_SOC_I2S_MODULE) ++static struct resource bcm2708_i2s_resources[] = { ++ { ++ .start = I2S_BASE, ++ .end = I2S_BASE + 0x20, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .start = PCM_CLOCK_BASE, ++ .end = PCM_CLOCK_BASE + 0x02, ++ .flags = IORESOURCE_MEM, ++ } ++}; ++ ++static struct platform_device bcm2708_i2s_device = { ++ .name = "bcm2708-i2s", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(bcm2708_i2s_resources), ++ .resource = bcm2708_i2s_resources, ++}; ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC_MODULE) ++static struct platform_device snd_hifiberry_dac_device = { ++ .name = "snd-hifiberry-dac", ++ .id = 0, ++ .num_resources = 0, ++}; ++ ++static struct platform_device snd_pcm5102a_codec_device = { ++ .name = "pcm5102a-codec", ++ .id = -1, ++ .num_resources = 0, ++}; ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS_MODULE) ++static struct platform_device snd_rpi_hifiberry_dacplus_device = { ++ .name = "snd-rpi-hifiberry-dacplus", ++ .id = 0, ++ .num_resources = 0, ++}; ++ ++static struct i2c_board_info __initdata snd_pcm512x_hbdacplus_i2c_devices[] = { ++ { ++ I2C_BOARD_INFO("pcm5122", 0x4d) ++ }, ++}; ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI_MODULE) ++static struct platform_device snd_hifiberry_digi_device = { ++ .name = "snd-hifiberry-digi", ++ .id = 0, ++ .num_resources = 0, ++}; ++ ++static struct i2c_board_info __initdata snd_wm8804_i2c_devices[] = { ++ { ++ I2C_BOARD_INFO("wm8804", 0x3b) ++ }, ++}; ++ ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP_MODULE) ++static struct platform_device snd_hifiberry_amp_device = { ++ .name = "snd-hifiberry-amp", ++ .id = 0, ++ .num_resources = 0, ++}; ++ ++static struct i2c_board_info __initdata snd_tas5713_i2c_devices[] = { ++ { ++ I2C_BOARD_INFO("tas5713", 0x1b) ++ }, ++}; ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_RPI_DAC) || defined(CONFIG_SND_BCM2708_SOC_RPI_DAC_MODULE) ++static struct platform_device snd_rpi_dac_device = { ++ .name = "snd-rpi-dac", ++ .id = 0, ++ .num_resources = 0, ++}; ++ ++static struct platform_device snd_pcm1794a_codec_device = { ++ .name = "pcm1794a-codec", ++ .id = -1, ++ .num_resources = 0, ++}; ++#endif ++ ++ ++#if defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) || defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC_MODULE) ++static struct platform_device snd_rpi_iqaudio_dac_device = { ++ .name = "snd-rpi-iqaudio-dac", ++ .id = 0, ++ .num_resources = 0, ++}; ++ ++// Use the actual device name rather than generic driver name ++static struct i2c_board_info __initdata snd_pcm512x_i2c_devices[] = { ++ { ++ I2C_BOARD_INFO("pcm5122", 0x4c) ++ }, ++}; ++#endif ++ ++int __init bcm_register_device(struct platform_device *pdev) ++{ ++ int ret; ++ ++ ret = platform_device_register(pdev); ++ if (ret) ++ pr_debug("Unable to register platform device '%s': %d\n", ++ pdev->name, ret); ++ ++ return ret; ++} ++ ++/* ++ * Use these macros for platform and i2c devices that are present in the ++ * Device Tree. This way the devices are only added on non-DT systems. ++ */ ++#define bcm_register_device_dt(pdev) \ ++ if (!use_dt) bcm_register_device(pdev) ++ ++#define i2c_register_board_info_dt(busnum, info, n) \ ++ if (!use_dt) i2c_register_board_info(busnum, info, n) ++ ++int calc_rsts(int partition) ++{ ++ return PM_PASSWORD | ++ ((partition & (1 << 0)) << 0) | ++ ((partition & (1 << 1)) << 1) | ++ ((partition & (1 << 2)) << 2) | ++ ((partition & (1 << 3)) << 3) | ++ ((partition & (1 << 4)) << 4) | ++ ((partition & (1 << 5)) << 5); ++} ++ ++static void bcm2709_restart(enum reboot_mode mode, const char *cmd) ++{ ++ extern char bcm2708_reboot_mode; ++ uint32_t pm_rstc, pm_wdog; ++ uint32_t timeout = 10; ++ uint32_t pm_rsts = 0; ++ ++ if(bcm2708_reboot_mode == 'q') ++ { ++ // NOOBS < 1.3 booting with reboot=q ++ pm_rsts = readl(__io_address(PM_RSTS)); ++ pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET; ++ } ++ else if(bcm2708_reboot_mode == 'p') ++ { ++ // NOOBS < 1.3 halting ++ pm_rsts = readl(__io_address(PM_RSTS)); ++ pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRH_SET; ++ } ++ else ++ { ++ pm_rsts = calc_rsts(reboot_part); ++ } ++ ++ writel(pm_rsts, __io_address(PM_RSTS)); ++ ++ /* Setup watchdog for reset */ ++ pm_rstc = readl(__io_address(PM_RSTC)); ++ ++ pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0) ++ pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET; ++ ++ writel(pm_wdog, __io_address(PM_WDOG)); ++ writel(pm_rstc, __io_address(PM_RSTC)); ++} ++ ++/* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */ ++static void bcm2709_power_off(void) ++{ ++ extern char bcm2708_reboot_mode; ++ if(bcm2708_reboot_mode == 'q') ++ { ++ // NOOBS < v1.3 ++ bcm2709_restart('p', ""); ++ } ++ else ++ { ++ /* partition 63 is special code for HALT the bootloader knows not to boot*/ ++ reboot_part = 63; ++ /* continue with normal reset mechanism */ ++ bcm2709_restart(0, ""); ++ } ++} ++ ++static void __init bcm2709_init_uart1(void) ++{ ++ struct device_node *np; ++ ++ np = of_find_compatible_node(NULL, NULL, "brcm,bcm2835-aux-uart"); ++ if (of_device_is_available(np)) { ++ pr_info("bcm2709: Mini UART enabled\n"); ++ writel(1, __io_address(UART1_BASE + 0x4)); ++ } ++} ++ ++#ifdef CONFIG_OF ++static void __init bcm2709_dt_init(void) ++{ ++ int ret; ++ ++ of_clk_init(NULL); ++ ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); ++ if (ret) { ++ pr_err("of_platform_populate failed: %d\n", ret); ++ /* Proceed as if CONFIG_OF was not defined */ ++ } else { ++ use_dt = 1; ++ } ++} ++#else ++static void __init bcm2709_dt_init(void) { } ++#endif /* CONFIG_OF */ ++ ++void __init bcm2709_init(void) ++{ ++ int i; ++ ++#if defined(CONFIG_BCM_VC_CMA) ++ vc_cma_early_init(); ++#endif ++ printk("bcm2709.uart_clock = %d\n", uart_clock); ++ pm_power_off = bcm2709_power_off; ++ ++ bcm2709_init_clocks(); ++ bcm2709_dt_init(); ++ ++ bcm_register_device_dt(&bcm2708_dmaengine_device); ++ bcm_register_device_dt(&bcm2708_vcio_device); ++ bcm_register_device_dt(&bcm2708_rpifw_device); ++ bcm_register_device_dt(&bcm2708_vchiq_device); ++#ifdef CONFIG_BCM2708_GPIO ++ bcm_register_device_dt(&bcm2708_gpio_device); ++#endif ++ ++#if defined(CONFIG_PPS_CLIENT_GPIO) || defined(CONFIG_PPS_CLIENT_GPIO_MODULE) ++ if (!use_dt && (pps_gpio_pin >= 0)) { ++ pr_info("bcm2709: GPIO %d setup as pps-gpio device\n", pps_gpio_pin); ++ pps_gpio_info.gpio_pin = pps_gpio_pin; ++ pps_gpio_device.id = pps_gpio_pin; ++ bcm_register_device(&pps_gpio_device); ++ } ++#endif ++ ++#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE) ++ w1_gpio_pdata.pin = w1_gpio_pin; ++ w1_gpio_pdata.ext_pullup_enable_pin = w1_gpio_pullup; ++ bcm_register_device_dt(&w1_device); ++#endif ++ bcm_register_device_dt(&bcm2708_fb_device); ++ bcm_register_device_dt(&bcm2708_usb_device); ++ ++#ifdef CONFIG_MMC_BCM2835 ++ bcm_register_device_dt(&bcm2835_emmc_device); ++#endif ++ bcm2709_init_led(); ++ bcm2709_init_uart1(); ++ ++ /* Only create the platform devices for the ALSA driver in the ++ absence of an enabled "audio" DT node */ ++ if (!use_dt || ++ !of_device_is_available(of_find_node_by_path("/audio"))) { ++ for (i = 0; i < ARRAY_SIZE(bcm2708_alsa_devices); i++) ++ bcm_register_device(&bcm2708_alsa_devices[i]); ++ } ++ ++ bcm_register_device_dt(&bcm2708_spi_device); ++ ++ if (vc_i2c_override) { ++ bcm_register_device_dt(&bcm2708_bsc0_device); ++ bcm_register_device_dt(&bcm2708_bsc1_device); ++ } else if ((boardrev & 0xffffff) == 0x2 || (boardrev & 0xffffff) == 0x3) { ++ bcm_register_device_dt(&bcm2708_bsc0_device); ++ } else { ++ bcm_register_device_dt(&bcm2708_bsc1_device); ++ } ++ ++ bcm_register_device_dt(&bcm2835_thermal_device); ++ ++#if defined(CONFIG_SND_BCM2708_SOC_I2S) || defined(CONFIG_SND_BCM2708_SOC_I2S_MODULE) ++ bcm_register_device_dt(&bcm2708_i2s_device); ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC_MODULE) ++ bcm_register_device_dt(&snd_hifiberry_dac_device); ++ bcm_register_device_dt(&snd_pcm5102a_codec_device); ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS_MODULE) ++ bcm_register_device_dt(&snd_rpi_hifiberry_dacplus_device); ++ i2c_register_board_info_dt(1, snd_pcm512x_hbdacplus_i2c_devices, ARRAY_SIZE(snd_pcm512x_hbdacplus_i2c_devices)); ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI_MODULE) ++ bcm_register_device_dt(&snd_hifiberry_digi_device); ++ i2c_register_board_info_dt(1, snd_wm8804_i2c_devices, ARRAY_SIZE(snd_wm8804_i2c_devices)); ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP_MODULE) ++ bcm_register_device_dt(&snd_hifiberry_amp_device); ++ i2c_register_board_info_dt(1, snd_tas5713_i2c_devices, ARRAY_SIZE(snd_tas5713_i2c_devices)); ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_RPI_DAC) || defined(CONFIG_SND_BCM2708_SOC_RPI_DAC_MODULE) ++ bcm_register_device_dt(&snd_rpi_dac_device); ++ bcm_register_device_dt(&snd_pcm1794a_codec_device); ++#endif ++ ++#if defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) || defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC_MODULE) ++ bcm_register_device_dt(&snd_rpi_iqaudio_dac_device); ++ i2c_register_board_info_dt(1, snd_pcm512x_i2c_devices, ARRAY_SIZE(snd_pcm512x_i2c_devices)); ++#endif ++ ++ if (!use_dt) { ++ for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { ++ struct amba_device *d = amba_devs[i]; ++ amba_device_register(d, &iomem_resource); ++ } ++ } ++ system_rev = boardrev; ++ system_serial_low = serial; ++ ++#ifdef CONFIG_BCM2708_SPIDEV ++ if (!use_dt) ++ spi_register_board_info(bcm2708_spi_devices, ++ ARRAY_SIZE(bcm2708_spi_devices)); ++#endif ++} ++ ++#ifdef SYSTEM_TIMER ++static void timer_set_mode(enum clock_event_mode mode, ++ struct clock_event_device *clk) ++{ ++ switch (mode) { ++ case CLOCK_EVT_MODE_ONESHOT: /* Leave the timer disabled, .set_next_event will enable it */ ++ case CLOCK_EVT_MODE_SHUTDOWN: ++ break; ++ case CLOCK_EVT_MODE_PERIODIC: ++ ++ case CLOCK_EVT_MODE_UNUSED: ++ case CLOCK_EVT_MODE_RESUME: ++ ++ default: ++ printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n", ++ (int)mode); ++ break; ++ } ++ ++} ++ ++static int timer_set_next_event(unsigned long cycles, ++ struct clock_event_device *unused) ++{ ++ unsigned long stc; ++ do { ++ stc = readl(__io_address(ST_BASE + 0x04)); ++ /* We could take a FIQ here, which may push ST above STC3 */ ++ writel(stc + cycles, __io_address(ST_BASE + 0x18)); ++ } while ((signed long) cycles >= 0 && ++ (signed long) (readl(__io_address(ST_BASE + 0x04)) - stc) ++ >= (signed long) cycles); ++ return 0; ++} ++ ++static struct clock_event_device timer0_clockevent = { ++ .name = "timer0", ++ .shift = 32, ++ .features = CLOCK_EVT_FEAT_ONESHOT, ++ .set_mode = timer_set_mode, ++ .set_next_event = timer_set_next_event, ++}; ++ ++/* ++ * IRQ handler for the timer ++ */ ++static irqreturn_t bcm2709_timer_interrupt(int irq, void *dev_id) ++{ ++ struct clock_event_device *evt = &timer0_clockevent; ++ ++ writel(1 << 3, __io_address(ST_BASE + 0x00)); /* stcs clear timer int */ ++ ++ evt->event_handler(evt); ++ ++ return IRQ_HANDLED; ++} ++ ++static struct irqaction bcm2709_timer_irq = { ++ .name = "BCM2709 Timer Tick", ++ .flags = IRQF_TIMER | IRQF_IRQPOLL, ++ .handler = bcm2709_timer_interrupt, ++}; ++ ++/* ++ * Set up timer interrupt, and return the current time in seconds. ++ */ ++ ++static struct delay_timer bcm2709_delay_timer = { ++ .read_current_timer = bcm2709_read_current_timer, ++ .freq = STC_FREQ_HZ, ++}; ++ ++static void __init bcm2709_timer_init(void) ++{ ++ /* init high res timer */ ++ bcm2709_clocksource_init(); ++ ++ /* ++ * Make irqs happen for the system timer ++ */ ++ setup_irq(IRQ_TIMER3, &bcm2709_timer_irq); ++ ++ sched_clock_register(bcm2709_read_sched_clock, 32, STC_FREQ_HZ); ++ ++ timer0_clockevent.mult = ++ div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift); ++ timer0_clockevent.max_delta_ns = ++ clockevent_delta2ns(0xffffffff, &timer0_clockevent); ++ timer0_clockevent.min_delta_ns = ++ clockevent_delta2ns(0xf, &timer0_clockevent); ++ ++ timer0_clockevent.cpumask = cpumask_of(0); ++ clockevents_register_device(&timer0_clockevent); ++ ++ register_current_timer_delay(&bcm2709_delay_timer); ++} ++ ++#else ++ ++static void __init bcm2709_timer_init(void) ++{ ++ extern void dc4_arch_timer_init(void); ++ // timer control ++ writel(0, __io_address(ARM_LOCAL_CONTROL)); ++ // timer pre_scaler ++ writel(0x80000000, __io_address(ARM_LOCAL_PRESCALER)); // 19.2MHz ++ //writel(0x06AAAAAB, __io_address(ARM_LOCAL_PRESCALER)); // 1MHz ++ ++ if (use_dt) ++ { ++ of_clk_init(NULL); ++ clocksource_of_init(); ++ } ++ else ++ dc4_arch_timer_init(); ++} ++ ++#endif ++ ++#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) ++#include ++ ++static struct gpio_led bcm2709_leds[] = { ++ [0] = { ++ .gpio = 16, ++ .name = "led0", ++ .default_trigger = "mmc0", ++ .active_low = 1, ++ }, ++}; ++ ++static struct gpio_led_platform_data bcm2709_led_pdata = { ++ .num_leds = ARRAY_SIZE(bcm2709_leds), ++ .leds = bcm2709_leds, ++}; ++ ++static struct platform_device bcm2709_led_device = { ++ .name = "leds-gpio", ++ .id = -1, ++ .dev = { ++ .platform_data = &bcm2709_led_pdata, ++ }, ++}; ++ ++static void __init bcm2709_init_led(void) ++{ ++ bcm2709_leds[0].gpio = disk_led_gpio; ++ bcm2709_leds[0].active_low = disk_led_active_low; ++ bcm_register_device_dt(&bcm2709_led_device); ++} ++#else ++static inline void bcm2709_init_led(void) ++{ ++} ++#endif ++ ++void __init bcm2709_init_early(void) ++{ ++ /* ++ * Some devices allocate their coherent buffers from atomic ++ * context. Increase size of atomic coherent pool to make sure such ++ * the allocations won't fail. ++ */ ++ init_dma_coherent_pool_size(SZ_4M); ++} ++ ++static void __init board_reserve(void) ++{ ++#if defined(CONFIG_BCM_VC_CMA) ++ vc_cma_reserve(); ++#endif ++} ++ ++ ++#ifdef CONFIG_SMP ++#include ++ ++#include ++#include ++#include ++int dc4=0; ++//void dc4_log(unsigned x) { if (dc4) writel((x), __io_address(ST_BASE+10 + raw_smp_processor_id()*4)); } ++void dc4_log_dead(unsigned x) { if (dc4) writel((readl(__io_address(ST_BASE+0x10 + raw_smp_processor_id()*4)) & 0xffff) | ((x)<<16), __io_address(ST_BASE+0x10 + raw_smp_processor_id()*4)); } ++ ++static void bcm2835_send_doorbell(const struct cpumask *mask, unsigned int irq) ++{ ++ int cpu; ++ /* ++ * Ensure that stores to Normal memory are visible to the ++ * other CPUs before issuing the IPI. ++ */ ++ dsb(); ++ ++ /* Convert our logical CPU mask into a physical one. */ ++ for_each_cpu(cpu, mask) ++ { ++ /* submit softirq */ ++ writel(1<%x)\n", __FUNCTION__, (unsigned)virt_to_phys((void *)secondary_startup), (unsigned)__io_address(ST_BASE + 0x10)); ++ printk("[%s] ncores=%d\n", __FUNCTION__, ncores); ++ ++ for (i = 0; i < ncores; i++) { ++ set_cpu_possible(i, true); ++ /* enable IRQ (not FIQ) */ ++ writel(0x1, __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 0x4 * i)); ++ //writel(0xf, __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 0x4 * i)); ++ } ++ set_smp_cross_call(bcm2835_send_doorbell); ++} ++ ++/* ++ * for arch/arm/kernel/smp.c:smp_prepare_cpus(unsigned int max_cpus) ++ */ ++void __init bcm2709_smp_prepare_cpus(unsigned int max_cpus) ++{ ++ //void __iomem *scu_base; ++ ++ printk("[%s] enter\n", __FUNCTION__); ++ //scu_base = scu_base_addr(); ++ //scu_enable(scu_base); ++} ++ ++/* ++ * for linux/arch/arm/kernel/smp.c:secondary_start_kernel(void) ++ */ ++void __cpuinit bcm2709_secondary_init(unsigned int cpu) ++{ ++ printk("[%s] enter cpu:%d\n", __FUNCTION__, cpu); ++ //gic_secondary_init(0); ++} ++ ++/* ++ * for linux/arch/arm/kernel/smp.c:__cpu_up(..) ++ */ ++int __cpuinit bcm2709_boot_secondary(unsigned int cpu, struct task_struct *idle) ++{ ++ void secondary_startup(void); ++ void *mbox_set = __io_address(ARM_LOCAL_MAILBOX3_SET0 + 0x10 * MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0)); ++ void *mbox_clr = __io_address(ARM_LOCAL_MAILBOX3_CLR0 + 0x10 * MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0)); ++ unsigned secondary_boot = (unsigned)virt_to_phys((void *)secondary_startup); ++ int timeout=20; ++ unsigned t = -1; ++ //printk("[%s] enter cpu:%d (%x->%p) %x\n", __FUNCTION__, cpu, secondary_boot, wake, readl(wake)); ++ ++ dsb(); ++ BUG_ON(readl(mbox_clr) != 0); ++ writel(secondary_boot, mbox_set); ++ ++ while (--timeout > 0) { ++ t = readl(mbox_clr); ++ if (t == 0) break; ++ cpu_relax(); ++ } ++ if (timeout==0) ++ printk("[%s] cpu:%d failed to start (%x)\n", __FUNCTION__, cpu, t); ++ else ++ printk("[%s] cpu:%d started (%x) %d\n", __FUNCTION__, cpu, t, timeout); ++ ++ return 0; ++} ++ ++ ++struct smp_operations bcm2709_smp_ops __initdata = { ++ .smp_init_cpus = bcm2709_smp_init_cpus, ++ .smp_prepare_cpus = bcm2709_smp_prepare_cpus, ++ .smp_secondary_init = bcm2709_secondary_init, ++ .smp_boot_secondary = bcm2709_boot_secondary, ++}; ++#endif ++ ++static const char * const bcm2709_compat[] = { ++ "brcm,bcm2709", ++ "brcm,bcm2708", /* Could use bcm2708 in a pinch */ ++ NULL ++}; ++ ++MACHINE_START(BCM2709, "BCM2709") ++ /* Maintainer: Broadcom Europe Ltd. */ ++#ifdef CONFIG_SMP ++ .smp = smp_ops(bcm2709_smp_ops), ++#endif ++ .map_io = bcm2709_map_io, ++ .init_irq = bcm2709_init_irq, ++ .init_time = bcm2709_timer_init, ++ .init_machine = bcm2709_init, ++ .init_early = bcm2709_init_early, ++ .reserve = board_reserve, ++ .restart = bcm2709_restart, ++ .dt_compat = bcm2709_compat, ++MACHINE_END ++ ++MACHINE_START(BCM2708, "BCM2709") ++ /* Maintainer: Broadcom Europe Ltd. */ ++#ifdef CONFIG_SMP ++ .smp = smp_ops(bcm2709_smp_ops), ++#endif ++ .map_io = bcm2709_map_io, ++ .init_irq = bcm2709_init_irq, ++ .init_time = bcm2709_timer_init, ++ .init_machine = bcm2709_init, ++ .init_early = bcm2709_init_early, ++ .reserve = board_reserve, ++ .restart = bcm2709_restart, ++ .dt_compat = bcm2709_compat, ++MACHINE_END ++ ++module_param(force_core, uint, 0644); ++module_param(boardrev, uint, 0644); ++module_param(serial, uint, 0644); ++module_param(uart_clock, uint, 0644); ++module_param(disk_led_gpio, uint, 0644); ++module_param(disk_led_active_low, uint, 0644); ++module_param(reboot_part, uint, 0644); ++module_param(w1_gpio_pin, uint, 0644); ++module_param(w1_gpio_pullup, uint, 0644); ++module_param(vc_i2c_override, bool, 0644); ++MODULE_PARM_DESC(vc_i2c_override, "Allow the use of VC's I2C peripheral."); ++module_param(pps_gpio_pin, int, 0644); ++MODULE_PARM_DESC(pps_gpio_pin, "Set GPIO pin to reserve for PPS"); +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/bcm2709.h linux-rpi/arch/arm/mach-bcm2709/bcm2709.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2709/bcm2709.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2709/bcm2709.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,49 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/bcm2708.h ++ * ++ * BCM2708 machine support header ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef __BCM2708_BCM2708_H ++#define __BCM2708_BCM2708_H ++ ++#include ++ ++extern void __init bcm2708_init(void); ++extern void __init bcm2708_init_irq(void); ++extern void __init bcm2708_map_io(void); ++extern struct sys_timer bcm2708_timer; ++extern unsigned int mmc_status(struct device *dev); ++ ++#define AMBA_DEVICE(name, busid, base, plat) \ ++static struct amba_device name##_device = { \ ++ .dev = { \ ++ .coherent_dma_mask = ~0, \ ++ .init_name = busid, \ ++ .platform_data = plat, \ ++ }, \ ++ .res = { \ ++ .start = base##_BASE, \ ++ .end = (base##_BASE) + SZ_4K - 1,\ ++ .flags = IORESOURCE_MEM, \ ++ }, \ ++ .irq = base##_IRQ, \ ++} ++ ++#endif +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/delay.S linux-rpi/arch/arm/mach-bcm2709/delay.S +--- linux-4.1.13.orig/arch/arm/mach-bcm2709/delay.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2709/delay.S 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,21 @@ ++/* ++ * linux/arch/arm/lib/delay.S ++ * ++ * Copyright (C) 1995, 1996 Russell King ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++#include ++#include ++#include ++ ++ .text ++.align 3 @ 8 byte alignment seems to be needed to avoid fetching stalls ++@ Delay routine ++ENTRY(bcm2708_delay) ++ subs r0, r0, #1 ++ bhi bcm2708_delay ++ mov pc, lr ++ENDPROC(bcm2708_delay) +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/arm_control.h linux-rpi/arch/arm/mach-bcm2709/include/mach/arm_control.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/arm_control.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2709/include/mach/arm_control.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,493 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/arm_control.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef __BCM2708_ARM_CONTROL_H ++#define __BCM2708_ARM_CONTROL_H ++ ++/* ++ * Definitions and addresses for the ARM CONTROL logic ++ * This file is manually generated. ++ */ ++ ++#define ARM_BASE 0x7E00B000 ++ ++/* Basic configuration */ ++#define ARM_CONTROL0 HW_REGISTER_RW(ARM_BASE+0x000) ++#define ARM_C0_SIZ128M 0x00000000 ++#define ARM_C0_SIZ256M 0x00000001 ++#define ARM_C0_SIZ512M 0x00000002 ++#define ARM_C0_SIZ1G 0x00000003 ++#define ARM_C0_BRESP0 0x00000000 ++#define ARM_C0_BRESP1 0x00000004 ++#define ARM_C0_BRESP2 0x00000008 ++#define ARM_C0_BOOTHI 0x00000010 ++#define ARM_C0_UNUSED05 0x00000020 /* free */ ++#define ARM_C0_FULLPERI 0x00000040 ++#define ARM_C0_UNUSED78 0x00000180 /* free */ ++#define ARM_C0_JTAGMASK 0x00000E00 ++#define ARM_C0_JTAGOFF 0x00000000 ++#define ARM_C0_JTAGBASH 0x00000800 /* Debug on GPIO off */ ++#define ARM_C0_JTAGGPIO 0x00000C00 /* Debug on GPIO on */ ++#define ARM_C0_APROTMSK 0x0000F000 ++#define ARM_C0_DBG0SYNC 0x00010000 /* VPU0 halt sync */ ++#define ARM_C0_DBG1SYNC 0x00020000 /* VPU1 halt sync */ ++#define ARM_C0_SWDBGREQ 0x00040000 /* HW debug request */ ++#define ARM_C0_PASSHALT 0x00080000 /* ARM halt passed to debugger */ ++#define ARM_C0_PRIO_PER 0x00F00000 /* per priority mask */ ++#define ARM_C0_PRIO_L2 0x0F000000 ++#define ARM_C0_PRIO_UC 0xF0000000 ++ ++#define ARM_C0_APROTPASS 0x0000A000 /* Translate 1:1 */ ++#define ARM_C0_APROTUSER 0x00000000 /* Only user mode */ ++#define ARM_C0_APROTSYST 0x0000F000 /* Only system mode */ ++ ++ ++#define ARM_CONTROL1 HW_REGISTER_RW(ARM_BASE+0x440) ++#define ARM_C1_TIMER 0x00000001 /* re-route timer IRQ to VC */ ++#define ARM_C1_MAIL 0x00000002 /* re-route Mail IRQ to VC */ ++#define ARM_C1_BELL0 0x00000004 /* re-route Doorbell 0 to VC */ ++#define ARM_C1_BELL1 0x00000008 /* re-route Doorbell 1 to VC */ ++#define ARM_C1_PERSON 0x00000100 /* peripherals on */ ++#define ARM_C1_REQSTOP 0x00000200 /* ASYNC bridge request stop */ ++ ++#define ARM_STATUS HW_REGISTER_RW(ARM_BASE+0x444) ++#define ARM_S_ACKSTOP 0x80000000 /* Bridge stopped */ ++#define ARM_S_READPEND 0x000003FF /* pending reads counter */ ++#define ARM_S_WRITPEND 0x000FFC00 /* pending writes counter */ ++ ++#define ARM_ERRHALT HW_REGISTER_RW(ARM_BASE+0x448) ++#define ARM_EH_PERIBURST 0x00000001 /* Burst write seen on peri bus */ ++#define ARM_EH_ILLADDRS1 0x00000002 /* Address bits 25-27 error */ ++#define ARM_EH_ILLADDRS2 0x00000004 /* Address bits 31-28 error */ ++#define ARM_EH_VPU0HALT 0x00000008 /* VPU0 halted & in debug mode */ ++#define ARM_EH_VPU1HALT 0x00000010 /* VPU1 halted & in debug mode */ ++#define ARM_EH_ARMHALT 0x00000020 /* ARM in halted debug mode */ ++ ++#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C) ++#define ARM_ID HW_REGISTER_RW(ARM_BASE+0x44C) ++#define ARM_IDVAL 0x364D5241 ++ ++/* Translation memory */ ++#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100) ++/* 32 locations: 0x100.. 0x17F */ ++/* 32 spare means we CAN go to 64 pages.... */ ++ ++ ++/* Interrupts */ ++#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200) /* Top IRQ bits */ ++#define ARM_I0_TIMER 0x00000001 /* timer IRQ */ ++#define ARM_I0_MAIL 0x00000002 /* Mail IRQ */ ++#define ARM_I0_BELL0 0x00000004 /* Doorbell 0 */ ++#define ARM_I0_BELL1 0x00000008 /* Doorbell 1 */ ++#define ARM_I0_BANK1 0x00000100 /* Bank1 IRQ */ ++#define ARM_I0_BANK2 0x00000200 /* Bank2 IRQ */ ++ ++#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) /* All bank1 IRQ bits */ ++/* todo: all I1_interrupt sources */ ++#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) /* All bank2 IRQ bits */ ++/* todo: all I2_interrupt sources */ ++ ++#define ARM_IRQ_FAST HW_REGISTER_RW(ARM_BASE+0x20C) /* FIQ control */ ++#define ARM_IF_INDEX 0x0000007F /* FIQ select */ ++#define ARM_IF_ENABLE 0x00000080 /* FIQ enable */ ++#define ARM_IF_VCMASK 0x0000003F /* FIQ = (index from VC source) */ ++#define ARM_IF_TIMER 0x00000040 /* FIQ = ARM timer */ ++#define ARM_IF_MAIL 0x00000041 /* FIQ = ARM Mail */ ++#define ARM_IF_BELL0 0x00000042 /* FIQ = ARM Doorbell 0 */ ++#define ARM_IF_BELL1 0x00000043 /* FIQ = ARM Doorbell 1 */ ++#define ARM_IF_VP0HALT 0x00000044 /* FIQ = VPU0 Halt seen */ ++#define ARM_IF_VP1HALT 0x00000045 /* FIQ = VPU1 Halt seen */ ++#define ARM_IF_ILLEGAL 0x00000046 /* FIQ = Illegal access seen */ ++ ++#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) /* Bank1 enable bits */ ++#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) /* Bank2 enable bits */ ++#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) /* ARM irqs enable bits */ ++#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) /* Bank1 disable bits */ ++#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) /* Bank2 disable bits */ ++#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) /* ARM irqs disable bits */ ++#define ARM_IE_TIMER 0x00000001 /* Timer IRQ */ ++#define ARM_IE_MAIL 0x00000002 /* Mail IRQ */ ++#define ARM_IE_BELL0 0x00000004 /* Doorbell 0 */ ++#define ARM_IE_BELL1 0x00000008 /* Doorbell 1 */ ++#define ARM_IE_VP0HALT 0x00000010 /* VPU0 Halt */ ++#define ARM_IE_VP1HALT 0x00000020 /* VPU1 Halt */ ++#define ARM_IE_ILLEGAL 0x00000040 /* Illegal access seen */ ++ ++/* Timer */ ++/* For reg. fields see sp804 spec. */ ++#define ARM_T_LOAD HW_REGISTER_RW(ARM_BASE+0x400) ++#define ARM_T_VALUE HW_REGISTER_RW(ARM_BASE+0x404) ++#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408) ++#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C) ++#define ARM_T_RAWIRQ HW_REGISTER_RW(ARM_BASE+0x410) ++#define ARM_T_MSKIRQ HW_REGISTER_RW(ARM_BASE+0x414) ++#define ARM_T_RELOAD HW_REGISTER_RW(ARM_BASE+0x418) ++#define ARM_T_PREDIV HW_REGISTER_RW(ARM_BASE+0x41c) ++#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420) ++ ++#define TIMER_CTRL_ONESHOT (1 << 0) ++#define TIMER_CTRL_32BIT (1 << 1) ++#define TIMER_CTRL_DIV1 (0 << 2) ++#define TIMER_CTRL_DIV16 (1 << 2) ++#define TIMER_CTRL_DIV256 (2 << 2) ++#define TIMER_CTRL_IE (1 << 5) ++#define TIMER_CTRL_PERIODIC (1 << 6) ++#define TIMER_CTRL_ENABLE (1 << 7) ++#define TIMER_CTRL_DBGHALT (1 << 8) ++#define TIMER_CTRL_ENAFREE (1 << 9) ++#define TIMER_CTRL_FREEDIV_SHIFT 16) ++#define TIMER_CTRL_FREEDIV_MASK 0xff ++ ++/* Semaphores, Doorbells, Mailboxes */ ++#define ARM_SBM_OWN0 (ARM_BASE+0x800) ++#define ARM_SBM_OWN1 (ARM_BASE+0x900) ++#define ARM_SBM_OWN2 (ARM_BASE+0xA00) ++#define ARM_SBM_OWN3 (ARM_BASE+0xB00) ++ ++/* MAILBOXES ++ * Register flags are common across all ++ * owner registers. See end of this section ++ * ++ * Semaphores, Doorbells, Mailboxes Owner 0 ++ * ++ */ ++ ++#define ARM_0_SEMS HW_REGISTER_RW(ARM_SBM_OWN0+0x00) ++#define ARM_0_SEM0 HW_REGISTER_RW(ARM_SBM_OWN0+0x00) ++#define ARM_0_SEM1 HW_REGISTER_RW(ARM_SBM_OWN0+0x04) ++#define ARM_0_SEM2 HW_REGISTER_RW(ARM_SBM_OWN0+0x08) ++#define ARM_0_SEM3 HW_REGISTER_RW(ARM_SBM_OWN0+0x0C) ++#define ARM_0_SEM4 HW_REGISTER_RW(ARM_SBM_OWN0+0x10) ++#define ARM_0_SEM5 HW_REGISTER_RW(ARM_SBM_OWN0+0x14) ++#define ARM_0_SEM6 HW_REGISTER_RW(ARM_SBM_OWN0+0x18) ++#define ARM_0_SEM7 HW_REGISTER_RW(ARM_SBM_OWN0+0x1C) ++#define ARM_0_BELL0 HW_REGISTER_RW(ARM_SBM_OWN0+0x40) ++#define ARM_0_BELL1 HW_REGISTER_RW(ARM_SBM_OWN0+0x44) ++#define ARM_0_BELL2 HW_REGISTER_RW(ARM_SBM_OWN0+0x48) ++#define ARM_0_BELL3 HW_REGISTER_RW(ARM_SBM_OWN0+0x4C) ++/* MAILBOX 0 access in Owner 0 area */ ++/* Some addresses should ONLY be used by owner 0 */ ++#define ARM_0_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) */ ++#define ARM_0_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) Normal read */ ++#define ARM_0_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN0+0x90) /* none-pop read */ ++#define ARM_0_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN0+0x94) /* Sender read (only LS 2 bits) */ ++#define ARM_0_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN0+0x98) /* Status read */ ++#define ARM_0_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0x9C) /* Config read/write */ ++/* MAILBOX 1 access in Owner 0 area */ ++/* Owner 0 should only WRITE to this mailbox */ ++#define ARM_0_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) /* .. 0xAC (4 locations) */ ++/*#define ARM_0_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_0_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_0_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) */ /* DO NOT USE THIS !!!!! */ ++#define ARM_0_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN0+0xB8) /* Status read */ ++/*#define ARM_0_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) */ /* DO NOT USE THIS !!!!! */ ++/* General SEM, BELL, MAIL config/status */ ++#define ARM_0_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE0) /* semaphore clear/debug register */ ++#define ARM_0_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE4) /* Doorbells clear/debug register */ ++#define ARM_0_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xF8) /* ALL interrupts */ ++#define ARM_0_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xFC) /* IRQS pending for owner 0 */ ++ ++/* Semaphores, Doorbells, Mailboxes Owner 1 */ ++#define ARM_1_SEMS HW_REGISTER_RW(ARM_SBM_OWN1+0x00) ++#define ARM_1_SEM0 HW_REGISTER_RW(ARM_SBM_OWN1+0x00) ++#define ARM_1_SEM1 HW_REGISTER_RW(ARM_SBM_OWN1+0x04) ++#define ARM_1_SEM2 HW_REGISTER_RW(ARM_SBM_OWN1+0x08) ++#define ARM_1_SEM3 HW_REGISTER_RW(ARM_SBM_OWN1+0x0C) ++#define ARM_1_SEM4 HW_REGISTER_RW(ARM_SBM_OWN1+0x10) ++#define ARM_1_SEM5 HW_REGISTER_RW(ARM_SBM_OWN1+0x14) ++#define ARM_1_SEM6 HW_REGISTER_RW(ARM_SBM_OWN1+0x18) ++#define ARM_1_SEM7 HW_REGISTER_RW(ARM_SBM_OWN1+0x1C) ++#define ARM_1_BELL0 HW_REGISTER_RW(ARM_SBM_OWN1+0x40) ++#define ARM_1_BELL1 HW_REGISTER_RW(ARM_SBM_OWN1+0x44) ++#define ARM_1_BELL2 HW_REGISTER_RW(ARM_SBM_OWN1+0x48) ++#define ARM_1_BELL3 HW_REGISTER_RW(ARM_SBM_OWN1+0x4C) ++/* MAILBOX 0 access in Owner 0 area */ ++/* Owner 1 should only WRITE to this mailbox */ ++#define ARM_1_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0x80) /* .. 0x8C (4 locations) */ ++/*#define ARM_1_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN1+0x80) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) */ /* DO NOT USE THIS !!!!! */ ++#define ARM_1_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN1+0x98) /* Status read */ ++/*#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) */ /* DO NOT USE THIS !!!!! */ ++/* MAILBOX 1 access in Owner 0 area */ ++#define ARM_1_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) */ ++#define ARM_1_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) Normal read */ ++#define ARM_1_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN1+0xB0) /* none-pop read */ ++#define ARM_1_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN1+0xB4) /* Sender read (only LS 2 bits) */ ++#define ARM_1_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN1+0xB8) /* Status read */ ++#define ARM_1_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0xBC) ++/* General SEM, BELL, MAIL config/status */ ++#define ARM_1_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE0) /* semaphore clear/debug register */ ++#define ARM_1_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE4) /* Doorbells clear/debug register */ ++#define ARM_1_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xFC) /* IRQS pending for owner 1 */ ++#define ARM_1_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xF8) /* ALL interrupts */ ++ ++/* Semaphores, Doorbells, Mailboxes Owner 2 */ ++#define ARM_2_SEMS HW_REGISTER_RW(ARM_SBM_OWN2+0x00) ++#define ARM_2_SEM0 HW_REGISTER_RW(ARM_SBM_OWN2+0x00) ++#define ARM_2_SEM1 HW_REGISTER_RW(ARM_SBM_OWN2+0x04) ++#define ARM_2_SEM2 HW_REGISTER_RW(ARM_SBM_OWN2+0x08) ++#define ARM_2_SEM3 HW_REGISTER_RW(ARM_SBM_OWN2+0x0C) ++#define ARM_2_SEM4 HW_REGISTER_RW(ARM_SBM_OWN2+0x10) ++#define ARM_2_SEM5 HW_REGISTER_RW(ARM_SBM_OWN2+0x14) ++#define ARM_2_SEM6 HW_REGISTER_RW(ARM_SBM_OWN2+0x18) ++#define ARM_2_SEM7 HW_REGISTER_RW(ARM_SBM_OWN2+0x1C) ++#define ARM_2_BELL0 HW_REGISTER_RW(ARM_SBM_OWN2+0x40) ++#define ARM_2_BELL1 HW_REGISTER_RW(ARM_SBM_OWN2+0x44) ++#define ARM_2_BELL2 HW_REGISTER_RW(ARM_SBM_OWN2+0x48) ++#define ARM_2_BELL3 HW_REGISTER_RW(ARM_SBM_OWN2+0x4C) ++/* MAILBOX 0 access in Owner 2 area */ ++/* Owner 2 should only WRITE to this mailbox */ ++#define ARM_2_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0x80) /* .. 0x8C (4 locations) */ ++/*#define ARM_2_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN2+0x80) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94) */ /* DO NOT USE THIS !!!!! */ ++#define ARM_2_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN2+0x98) /* Status read */ ++/*#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C) */ /* DO NOT USE THIS !!!!! */ ++/* MAILBOX 1 access in Owner 2 area */ ++/* Owner 2 should only WRITE to this mailbox */ ++#define ARM_2_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) /* .. 0xAC (4 locations) */ ++/*#define ARM_2_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_2_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_2_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) */ /* DO NOT USE THIS !!!!! */ ++#define ARM_2_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN2+0xB8) /* Status read */ ++/*#define ARM_2_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) */ /* DO NOT USE THIS !!!!! */ ++/* General SEM, BELL, MAIL config/status */ ++#define ARM_2_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE0) /* semaphore clear/debug register */ ++#define ARM_2_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE4) /* Doorbells clear/debug register */ ++#define ARM_2_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xFC) /* IRQS pending for owner 2 */ ++#define ARM_2_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xF8) /* ALL interrupts */ ++ ++/* Semaphores, Doorbells, Mailboxes Owner 3 */ ++#define ARM_3_SEMS HW_REGISTER_RW(ARM_SBM_OWN3+0x00) ++#define ARM_3_SEM0 HW_REGISTER_RW(ARM_SBM_OWN3+0x00) ++#define ARM_3_SEM1 HW_REGISTER_RW(ARM_SBM_OWN3+0x04) ++#define ARM_3_SEM2 HW_REGISTER_RW(ARM_SBM_OWN3+0x08) ++#define ARM_3_SEM3 HW_REGISTER_RW(ARM_SBM_OWN3+0x0C) ++#define ARM_3_SEM4 HW_REGISTER_RW(ARM_SBM_OWN3+0x10) ++#define ARM_3_SEM5 HW_REGISTER_RW(ARM_SBM_OWN3+0x14) ++#define ARM_3_SEM6 HW_REGISTER_RW(ARM_SBM_OWN3+0x18) ++#define ARM_3_SEM7 HW_REGISTER_RW(ARM_SBM_OWN3+0x1C) ++#define ARM_3_BELL0 HW_REGISTER_RW(ARM_SBM_OWN3+0x40) ++#define ARM_3_BELL1 HW_REGISTER_RW(ARM_SBM_OWN3+0x44) ++#define ARM_3_BELL2 HW_REGISTER_RW(ARM_SBM_OWN3+0x48) ++#define ARM_3_BELL3 HW_REGISTER_RW(ARM_SBM_OWN3+0x4C) ++/* MAILBOX 0 access in Owner 3 area */ ++/* Owner 3 should only WRITE to this mailbox */ ++#define ARM_3_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0x80) /* .. 0x8C (4 locations) */ ++/*#define ARM_3_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN3+0x80) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94) */ /* DO NOT USE THIS !!!!! */ ++#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98) /* Status read */ ++/*#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C) */ /* DO NOT USE THIS !!!!! */ ++/* MAILBOX 1 access in Owner 3 area */ ++/* Owner 3 should only WRITE to this mailbox */ ++#define ARM_3_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) /* .. 0xAC (4 locations) */ ++/*#define ARM_3_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_3_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_3_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) */ /* DO NOT USE THIS !!!!! */ ++#define ARM_3_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN3+0xB8) /* Status read */ ++/*#define ARM_3_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) */ /* DO NOT USE THIS !!!!! */ ++/* General SEM, BELL, MAIL config/status */ ++#define ARM_3_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE0) /* semaphore clear/debug register */ ++#define ARM_3_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE4) /* Doorbells clear/debug register */ ++#define ARM_3_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xFC) /* IRQS pending for owner 3 */ ++#define ARM_3_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xF8) /* ALL interrupts */ ++ ++ ++ ++/* Mailbox flags. Valid for all owners */ ++ ++/* Mailbox status register (...0x98) */ ++#define ARM_MS_FULL 0x80000000 ++#define ARM_MS_EMPTY 0x40000000 ++#define ARM_MS_LEVEL 0x400000FF /* Max. value depdnds on mailbox depth parameter */ ++ ++/* MAILBOX config/status register (...0x9C) */ ++/* ANY write to this register clears the error bits! */ ++#define ARM_MC_IHAVEDATAIRQEN 0x00000001 /* mailbox irq enable: has data */ ++#define ARM_MC_IHAVESPACEIRQEN 0x00000002 /* mailbox irq enable: has space */ ++#define ARM_MC_OPPISEMPTYIRQEN 0x00000004 /* mailbox irq enable: Opp. is empty */ ++#define ARM_MC_MAIL_CLEAR 0x00000008 /* mailbox clear write 1, then 0 */ ++#define ARM_MC_IHAVEDATAIRQPEND 0x00000010 /* mailbox irq pending: has space */ ++#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mailbox irq pending: Opp. is empty */ ++#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mailbox irq pending */ ++/* Bit 7 is unused */ ++#define ARM_MC_ERRNOOWN 0x00000100 /* error : none owner read from mailbox */ ++#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */ ++#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */ ++ ++/* Semaphore clear/debug register (...0xE0) */ ++#define ARM_SD_OWN0 0x00000003 /* Owner of sem 0 */ ++#define ARM_SD_OWN1 0x0000000C /* Owner of sem 1 */ ++#define ARM_SD_OWN2 0x00000030 /* Owner of sem 2 */ ++#define ARM_SD_OWN3 0x000000C0 /* Owner of sem 3 */ ++#define ARM_SD_OWN4 0x00000300 /* Owner of sem 4 */ ++#define ARM_SD_OWN5 0x00000C00 /* Owner of sem 5 */ ++#define ARM_SD_OWN6 0x00003000 /* Owner of sem 6 */ ++#define ARM_SD_OWN7 0x0000C000 /* Owner of sem 7 */ ++#define ARM_SD_SEM0 0x00010000 /* Status of sem 0 */ ++#define ARM_SD_SEM1 0x00020000 /* Status of sem 1 */ ++#define ARM_SD_SEM2 0x00040000 /* Status of sem 2 */ ++#define ARM_SD_SEM3 0x00080000 /* Status of sem 3 */ ++#define ARM_SD_SEM4 0x00100000 /* Status of sem 4 */ ++#define ARM_SD_SEM5 0x00200000 /* Status of sem 5 */ ++#define ARM_SD_SEM6 0x00400000 /* Status of sem 6 */ ++#define ARM_SD_SEM7 0x00800000 /* Status of sem 7 */ ++ ++/* Doorbells clear/debug register (...0xE4) */ ++#define ARM_BD_OWN0 0x00000003 /* Owner of doorbell 0 */ ++#define ARM_BD_OWN1 0x0000000C /* Owner of doorbell 1 */ ++#define ARM_BD_OWN2 0x00000030 /* Owner of doorbell 2 */ ++#define ARM_BD_OWN3 0x000000C0 /* Owner of doorbell 3 */ ++#define ARM_BD_BELL0 0x00000100 /* Status of doorbell 0 */ ++#define ARM_BD_BELL1 0x00000200 /* Status of doorbell 1 */ ++#define ARM_BD_BELL2 0x00000400 /* Status of doorbell 2 */ ++#define ARM_BD_BELL3 0x00000800 /* Status of doorbell 3 */ ++ ++/* MY IRQS register (...0xF8) */ ++#define ARM_MYIRQ_BELL 0x00000001 /* This owner has a doorbell IRQ */ ++#define ARM_MYIRQ_MAIL 0x00000002 /* This owner has a mailbox IRQ */ ++ ++/* ALL IRQS register (...0xF8) */ ++#define ARM_AIS_BELL0 0x00000001 /* Doorbell 0 IRQ pending */ ++#define ARM_AIS_BELL1 0x00000002 /* Doorbell 1 IRQ pending */ ++#define ARM_AIS_BELL2 0x00000004 /* Doorbell 2 IRQ pending */ ++#define ARM_AIS_BELL3 0x00000008 /* Doorbell 3 IRQ pending */ ++#define ARM_AIS0_HAVEDATA 0x00000010 /* MAIL 0 has data IRQ pending */ ++#define ARM_AIS0_HAVESPAC 0x00000020 /* MAIL 0 has space IRQ pending */ ++#define ARM_AIS0_OPPEMPTY 0x00000040 /* MAIL 0 opposite is empty IRQ */ ++#define ARM_AIS1_HAVEDATA 0x00000080 /* MAIL 1 has data IRQ pending */ ++#define ARM_AIS1_HAVESPAC 0x00000100 /* MAIL 1 has space IRQ pending */ ++#define ARM_AIS1_OPPEMPTY 0x00000200 /* MAIL 1 opposite is empty IRQ */ ++/* Note that bell-0, bell-1 and MAIL0 IRQ go only to the ARM */ ++/* Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC */ ++/* */ ++/* ARM JTAG BASH */ ++/* */ ++#define AJB_BASE 0x7e2000c0 ++ ++#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00) ++#define AJB_BITS0 0x000000 ++#define AJB_BITS4 0x000004 ++#define AJB_BITS8 0x000008 ++#define AJB_BITS12 0x00000C ++#define AJB_BITS16 0x000010 ++#define AJB_BITS20 0x000014 ++#define AJB_BITS24 0x000018 ++#define AJB_BITS28 0x00001C ++#define AJB_BITS32 0x000020 ++#define AJB_BITS34 0x000022 ++#define AJB_OUT_MS 0x000040 ++#define AJB_OUT_LS 0x000000 ++#define AJB_INV_CLK 0x000080 ++#define AJB_D0_RISE 0x000100 ++#define AJB_D0_FALL 0x000000 ++#define AJB_D1_RISE 0x000200 ++#define AJB_D1_FALL 0x000000 ++#define AJB_IN_RISE 0x000400 ++#define AJB_IN_FALL 0x000000 ++#define AJB_ENABLE 0x000800 ++#define AJB_HOLD0 0x000000 ++#define AJB_HOLD1 0x001000 ++#define AJB_HOLD2 0x002000 ++#define AJB_HOLD3 0x003000 ++#define AJB_RESETN 0x004000 ++#define AJB_CLKSHFT 16 ++#define AJB_BUSY 0x80000000 ++#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04) ++#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08) ++#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c) ++ ++#define ARM_LOCAL_BASE 0x40000000 ++#define ARM_LOCAL_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x000) ++#define ARM_LOCAL_PRESCALER HW_REGISTER_RW(ARM_LOCAL_BASE+0x008) ++#define ARM_LOCAL_GPU_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x00C) ++#define ARM_LOCAL_PM_ROUTING_SET HW_REGISTER_RW(ARM_LOCAL_BASE+0x010) ++#define ARM_LOCAL_PM_ROUTING_CLR HW_REGISTER_RW(ARM_LOCAL_BASE+0x014) ++#define ARM_LOCAL_TIMER_LS HW_REGISTER_RW(ARM_LOCAL_BASE+0x01C) ++#define ARM_LOCAL_TIMER_MS HW_REGISTER_RW(ARM_LOCAL_BASE+0x020) ++#define ARM_LOCAL_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x024) ++#define ARM_LOCAL_AXI_COUNT HW_REGISTER_RW(ARM_LOCAL_BASE+0x02C) ++#define ARM_LOCAL_AXI_IRQ HW_REGISTER_RW(ARM_LOCAL_BASE+0x030) ++#define ARM_LOCAL_TIMER_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x034) ++#define ARM_LOCAL_TIMER_WRITE HW_REGISTER_RW(ARM_LOCAL_BASE+0x038) ++ ++#define ARM_LOCAL_TIMER_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x040) ++#define ARM_LOCAL_TIMER_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x044) ++#define ARM_LOCAL_TIMER_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x048) ++#define ARM_LOCAL_TIMER_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x04C) ++ ++#define ARM_LOCAL_MAILBOX_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x050) ++#define ARM_LOCAL_MAILBOX_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x054) ++#define ARM_LOCAL_MAILBOX_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x058) ++#define ARM_LOCAL_MAILBOX_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x05C) ++ ++#define ARM_LOCAL_IRQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x060) ++#define ARM_LOCAL_IRQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x064) ++#define ARM_LOCAL_IRQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x068) ++#define ARM_LOCAL_IRQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x06C) ++ ++#define ARM_LOCAL_FIQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x070) ++#define ARM_LOCAL_FIQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x074) ++#define ARM_LOCAL_FIQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x078) ++#define ARM_LOCAL_FIQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x07C) ++ ++#define ARM_LOCAL_MAILBOX0_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x080) ++#define ARM_LOCAL_MAILBOX1_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x084) ++#define ARM_LOCAL_MAILBOX2_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x088) ++#define ARM_LOCAL_MAILBOX3_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x08C) ++ ++#define ARM_LOCAL_MAILBOX0_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x090) ++#define ARM_LOCAL_MAILBOX1_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x094) ++#define ARM_LOCAL_MAILBOX2_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x098) ++#define ARM_LOCAL_MAILBOX3_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x09C) ++ ++#define ARM_LOCAL_MAILBOX0_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A0) ++#define ARM_LOCAL_MAILBOX1_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A4) ++#define ARM_LOCAL_MAILBOX2_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A8) ++#define ARM_LOCAL_MAILBOX3_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0AC) ++ ++#define ARM_LOCAL_MAILBOX0_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B0) ++#define ARM_LOCAL_MAILBOX1_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B4) ++#define ARM_LOCAL_MAILBOX2_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B8) ++#define ARM_LOCAL_MAILBOX3_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0BC) ++ ++#define ARM_LOCAL_MAILBOX0_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C0) ++#define ARM_LOCAL_MAILBOX1_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C4) ++#define ARM_LOCAL_MAILBOX2_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C8) ++#define ARM_LOCAL_MAILBOX3_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0CC) ++ ++#define ARM_LOCAL_MAILBOX0_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D0) ++#define ARM_LOCAL_MAILBOX1_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D4) ++#define ARM_LOCAL_MAILBOX2_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D8) ++#define ARM_LOCAL_MAILBOX3_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0DC) ++ ++#define ARM_LOCAL_MAILBOX0_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E0) ++#define ARM_LOCAL_MAILBOX1_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E4) ++#define ARM_LOCAL_MAILBOX2_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E8) ++#define ARM_LOCAL_MAILBOX3_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0EC) ++ ++#define ARM_LOCAL_MAILBOX0_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F0) ++#define ARM_LOCAL_MAILBOX1_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F4) ++#define ARM_LOCAL_MAILBOX2_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F8) ++#define ARM_LOCAL_MAILBOX3_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0FC) ++ ++#endif +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/barriers.h linux-rpi/arch/arm/mach-bcm2709/include/mach/barriers.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/barriers.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2709/include/mach/barriers.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,3 @@ ++#define mb() dsb() ++#define rmb() dsb() ++#define wmb() mb() +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/clkdev.h linux-rpi/arch/arm/mach-bcm2709/include/mach/clkdev.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/clkdev.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2709/include/mach/clkdev.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,7 @@ ++#ifndef __ASM_MACH_CLKDEV_H ++#define __ASM_MACH_CLKDEV_H ++ ++#define __clk_get(clk) ({ 1; }) ++#define __clk_put(clk) do { } while (0) ++ ++#endif +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/debug-macro.S linux-rpi/arch/arm/mach-bcm2709/include/mach/debug-macro.S +--- linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/debug-macro.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2709/include/mach/debug-macro.S 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,22 @@ ++/* arch/arm/mach-bcm2708/include/mach/debug-macro.S ++ * ++ * Debugging macro include header ++ * ++ * Copyright (C) 2010 Broadcom ++ * Copyright (C) 1994-1999 Russell King ++ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++*/ ++ ++#include ++ ++ .macro addruart, rp, rv, tmp ++ ldr \rp, =UART0_BASE ++ ldr \rv, =IO_ADDRESS(UART0_BASE) ++ .endm ++ ++#include +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/entry-macro.S linux-rpi/arch/arm/mach-bcm2709/include/mach/entry-macro.S +--- linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/entry-macro.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2709/include/mach/entry-macro.S 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,120 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/entry-macro.S ++ * ++ * Low-level IRQ helper macros for BCM2708 platforms ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#include ++#include ++ ++ .macro arch_ret_to_user, tmp1, tmp2 ++ .endm ++ ++ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp ++ ++ /* get core number */ ++ mrc p15, 0, \base, c0, c0, 5 ++ ubfx \base, \base, #0, #2 ++ ++ /* get core's local interrupt controller */ ++ ldr \irqstat, = __io_address(ARM_LOCAL_IRQ_PENDING0) @ local interrupt source ++ add \irqstat, \irqstat, \base, lsl #2 ++ ldr \tmp, [\irqstat] ++#ifdef CONFIG_SMP ++ /* test for mailbox0 (IPI) interrupt */ ++ tst \tmp, #0x10 ++ beq 1030f ++ ++ /* get core's mailbox interrupt control */ ++ ldr \irqstat, = __io_address(ARM_LOCAL_MAILBOX0_CLR0) @ mbox_clr ++ add \irqstat, \irqstat, \base, lsl #4 ++ ldr \tmp, [\irqstat] ++ clz \tmp, \tmp ++ rsb \irqnr, \tmp, #31 ++ mov \tmp, #1 ++ lsl \tmp, \irqnr ++ str \tmp, [\irqstat] @ clear interrupt source ++ dsb ++ mov r1, sp ++ adr lr, BSYM(1b) ++ b do_IPI ++#endif ++1030: ++ /* check gpu interrupt */ ++ tst \tmp, #0x100 ++ beq 1040f ++ ++ ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE) ++ /* get masked status */ ++ ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)] ++ mov \irqnr, #(ARM_IRQ0_BASE + 31) ++ and \tmp, \irqstat, #0x300 @ save bits 8 and 9 ++ /* clear bits 8 and 9, and test */ ++ bics \irqstat, \irqstat, #0x300 ++ bne 1010f ++ ++ tst \tmp, #0x100 ++ ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)] ++ movne \irqnr, #(ARM_IRQ1_BASE + 31) ++ @ Mask out the interrupts also present in PEND0 - see SW-5809 ++ bicne \irqstat, #((1<<7) | (1<<9) | (1<<10)) ++ bicne \irqstat, #((1<<18) | (1<<19)) ++ bne 1010f ++ ++ tst \tmp, #0x200 ++ ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)] ++ movne \irqnr, #(ARM_IRQ2_BASE + 31) ++ @ Mask out the interrupts also present in PEND0 - see SW-5809 ++ bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25)) ++ bicne \irqstat, #((1<<30)) ++ beq 1020f ++1010: ++ @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1)) ++ sub \tmp, \irqstat, #1 ++ eor \irqstat, \irqstat, \tmp ++ clz \tmp, \irqstat ++ sub \irqnr, \tmp ++ b 1050f ++1040: ++ cmp \tmp, #0 ++ beq 1020f ++ ++ /* handle local (e.g. timer) interrupts */ ++ @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1)) ++ mov \irqnr, #(ARM_IRQ_LOCAL_BASE + 31) ++ sub \irqstat, \tmp, #1 ++ eor \irqstat, \irqstat, \tmp ++ clz \tmp, \irqstat ++ sub \irqnr, \tmp ++1050: ++ mov r1, sp ++ @ ++ @ routine called with r0 = irq number, r1 = struct pt_regs * ++ @ ++ adr lr, BSYM(1b) ++ b asm_do_IRQ ++ ++1020: @ EQ will be set if no irqs pending ++ .endm ++ ++/* ++ * Interrupt handling. Preserves r7, r8, r9 ++ */ ++ .macro arch_irq_handler_default ++1: get_irqnr_and_base r0, r2, r6, lr ++ .endm +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/frc.h linux-rpi/arch/arm/mach-bcm2709/include/mach/frc.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/frc.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2709/include/mach/frc.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,38 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/timex.h ++ * ++ * BCM2708 free running counter (timer) ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef _MACH_FRC_H ++#define _MACH_FRC_H ++ ++#define FRC_TICK_RATE (1000000) ++ ++/*! Free running counter incrementing at the CLOCK_TICK_RATE ++ (slightly faster than frc_clock_ticks63() ++ */ ++extern unsigned long frc_clock_ticks32(void); ++ ++/*! Free running counter incrementing at the CLOCK_TICK_RATE ++ * Note - top bit should be ignored (see cnt32_to_63) ++ */ ++extern unsigned long long frc_clock_ticks63(void); ++ ++#endif +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/gpio.h linux-rpi/arch/arm/mach-bcm2709/include/mach/gpio.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/gpio.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2709/include/mach/gpio.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,17 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/gpio.h ++ * ++ * This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without any ++ * warranty of any kind, whether express or implied. ++ */ ++ ++#ifndef __ASM_ARCH_GPIO_H ++#define __ASM_ARCH_GPIO_H ++ ++#define BCM2708_NR_GPIOS 54 // number of gpio lines ++ ++#define gpio_to_irq(x) ((x) + GPIO_IRQ_START) ++#define irq_to_gpio(x) ((x) - GPIO_IRQ_START) ++ ++#endif +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/hardware.h linux-rpi/arch/arm/mach-bcm2709/include/mach/hardware.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/hardware.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2709/include/mach/hardware.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,28 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/hardware.h ++ * ++ * This file contains the hardware definitions of the BCM2708 devices. ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#ifndef __ASM_ARCH_HARDWARE_H ++#define __ASM_ARCH_HARDWARE_H ++ ++#include ++#include ++ ++#endif +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/io.h linux-rpi/arch/arm/mach-bcm2709/include/mach/io.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/io.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2709/include/mach/io.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,27 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/io.h ++ * ++ * Copyright (C) 2003 ARM Limited ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#ifndef __ASM_ARM_ARCH_IO_H ++#define __ASM_ARM_ARCH_IO_H ++ ++#define IO_SPACE_LIMIT 0xffffffff ++ ++#define __io(a) __typesafe_io(a) ++ ++#endif +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/irqs.h linux-rpi/arch/arm/mach-bcm2709/include/mach/irqs.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/irqs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2709/include/mach/irqs.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,225 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/irqs.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * Copyright (C) 2003 ARM Limited ++ * Copyright (C) 2000 Deep Blue Solutions Ltd. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef _BCM2708_IRQS_H_ ++#define _BCM2708_IRQS_H_ ++ ++#include ++ ++/* ++ * IRQ interrupts definitions are the same as the INT definitions ++ * held within platform.h ++ */ ++#define IRQ_ARMCTRL_START 0 ++#define IRQ_TIMER0 (IRQ_ARMCTRL_START + INTERRUPT_TIMER0) ++#define IRQ_TIMER1 (IRQ_ARMCTRL_START + INTERRUPT_TIMER1) ++#define IRQ_TIMER2 (IRQ_ARMCTRL_START + INTERRUPT_TIMER2) ++#define IRQ_TIMER3 (IRQ_ARMCTRL_START + INTERRUPT_TIMER3) ++#define IRQ_CODEC0 (IRQ_ARMCTRL_START + INTERRUPT_CODEC0) ++#define IRQ_CODEC1 (IRQ_ARMCTRL_START + INTERRUPT_CODEC1) ++#define IRQ_CODEC2 (IRQ_ARMCTRL_START + INTERRUPT_CODEC2) ++#define IRQ_JPEG (IRQ_ARMCTRL_START + INTERRUPT_JPEG) ++#define IRQ_ISP (IRQ_ARMCTRL_START + INTERRUPT_ISP) ++#define IRQ_USB (IRQ_ARMCTRL_START + INTERRUPT_USB) ++#define IRQ_3D (IRQ_ARMCTRL_START + INTERRUPT_3D) ++#define IRQ_TRANSPOSER (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER) ++#define IRQ_MULTICORESYNC0 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0) ++#define IRQ_MULTICORESYNC1 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1) ++#define IRQ_MULTICORESYNC2 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2) ++#define IRQ_MULTICORESYNC3 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3) ++#define IRQ_DMA0 (IRQ_ARMCTRL_START + INTERRUPT_DMA0) ++#define IRQ_DMA1 (IRQ_ARMCTRL_START + INTERRUPT_DMA1) ++#define IRQ_DMA2 (IRQ_ARMCTRL_START + INTERRUPT_DMA2) ++#define IRQ_DMA3 (IRQ_ARMCTRL_START + INTERRUPT_DMA3) ++#define IRQ_DMA4 (IRQ_ARMCTRL_START + INTERRUPT_DMA4) ++#define IRQ_DMA5 (IRQ_ARMCTRL_START + INTERRUPT_DMA5) ++#define IRQ_DMA6 (IRQ_ARMCTRL_START + INTERRUPT_DMA6) ++#define IRQ_DMA7 (IRQ_ARMCTRL_START + INTERRUPT_DMA7) ++#define IRQ_DMA8 (IRQ_ARMCTRL_START + INTERRUPT_DMA8) ++#define IRQ_DMA9 (IRQ_ARMCTRL_START + INTERRUPT_DMA9) ++#define IRQ_DMA10 (IRQ_ARMCTRL_START + INTERRUPT_DMA10) ++#define IRQ_DMA11 (IRQ_ARMCTRL_START + INTERRUPT_DMA11) ++#define IRQ_DMA12 (IRQ_ARMCTRL_START + INTERRUPT_DMA12) ++#define IRQ_AUX (IRQ_ARMCTRL_START + INTERRUPT_AUX) ++#define IRQ_ARM (IRQ_ARMCTRL_START + INTERRUPT_ARM) ++#define IRQ_VPUDMA (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA) ++#define IRQ_HOSTPORT (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT) ++#define IRQ_VIDEOSCALER (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER) ++#define IRQ_CCP2TX (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX) ++#define IRQ_SDC (IRQ_ARMCTRL_START + INTERRUPT_SDC) ++#define IRQ_DSI0 (IRQ_ARMCTRL_START + INTERRUPT_DSI0) ++#define IRQ_AVE (IRQ_ARMCTRL_START + INTERRUPT_AVE) ++#define IRQ_CAM0 (IRQ_ARMCTRL_START + INTERRUPT_CAM0) ++#define IRQ_CAM1 (IRQ_ARMCTRL_START + INTERRUPT_CAM1) ++#define IRQ_HDMI0 (IRQ_ARMCTRL_START + INTERRUPT_HDMI0) ++#define IRQ_HDMI1 (IRQ_ARMCTRL_START + INTERRUPT_HDMI1) ++#define IRQ_PIXELVALVE1 (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1) ++#define IRQ_I2CSPISLV (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV) ++#define IRQ_DSI1 (IRQ_ARMCTRL_START + INTERRUPT_DSI1) ++#define IRQ_PWA0 (IRQ_ARMCTRL_START + INTERRUPT_PWA0) ++#define IRQ_PWA1 (IRQ_ARMCTRL_START + INTERRUPT_PWA1) ++#define IRQ_CPR (IRQ_ARMCTRL_START + INTERRUPT_CPR) ++#define IRQ_SMI (IRQ_ARMCTRL_START + INTERRUPT_SMI) ++#define IRQ_GPIO0 (IRQ_ARMCTRL_START + INTERRUPT_GPIO0) ++#define IRQ_GPIO1 (IRQ_ARMCTRL_START + INTERRUPT_GPIO1) ++#define IRQ_GPIO2 (IRQ_ARMCTRL_START + INTERRUPT_GPIO2) ++#define IRQ_GPIO3 (IRQ_ARMCTRL_START + INTERRUPT_GPIO3) ++#define IRQ_I2C (IRQ_ARMCTRL_START + INTERRUPT_I2C) ++#define IRQ_SPI (IRQ_ARMCTRL_START + INTERRUPT_SPI) ++#define IRQ_I2SPCM (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM) ++#define IRQ_SDIO (IRQ_ARMCTRL_START + INTERRUPT_SDIO) ++#define IRQ_UART (IRQ_ARMCTRL_START + INTERRUPT_UART) ++#define IRQ_SLIMBUS (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS) ++#define IRQ_VEC (IRQ_ARMCTRL_START + INTERRUPT_VEC) ++#define IRQ_CPG (IRQ_ARMCTRL_START + INTERRUPT_CPG) ++#define IRQ_RNG (IRQ_ARMCTRL_START + INTERRUPT_RNG) ++#define IRQ_ARASANSDIO (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO) ++#define IRQ_AVSPMON (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON) ++ ++#define IRQ_ARM_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER) ++#define IRQ_ARM_MAILBOX (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX) ++#define IRQ_ARM_DOORBELL_0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0) ++#define IRQ_ARM_DOORBELL_1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1) ++#define IRQ_VPU0_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED) ++#define IRQ_VPU1_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED) ++#define IRQ_ILLEGAL_TYPE0 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0) ++#define IRQ_ILLEGAL_TYPE1 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1) ++#define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1) ++#define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2) ++ ++#define IRQ_ARM_LOCAL_CNTPSIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPSIRQ) ++#define IRQ_ARM_LOCAL_CNTPNSIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPNSIRQ) ++#define IRQ_ARM_LOCAL_CNTHPIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTHPIRQ) ++#define IRQ_ARM_LOCAL_CNTVIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTVIRQ) ++#define IRQ_ARM_LOCAL_MAILBOX0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX0) ++#define IRQ_ARM_LOCAL_MAILBOX1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX1) ++#define IRQ_ARM_LOCAL_MAILBOX2 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX2) ++#define IRQ_ARM_LOCAL_MAILBOX3 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX3) ++#define IRQ_ARM_LOCAL_GPU_FAST (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_GPU_FAST) ++#define IRQ_ARM_LOCAL_PMU_FAST (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_PMU_FAST) ++#define IRQ_ARM_LOCAL_ZERO (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_ZERO) ++#define IRQ_ARM_LOCAL_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_TIMER) ++ ++#define FIQ_START HARD_IRQS ++ ++/* ++ * FIQ interrupts definitions are the same as the INT definitions. ++ */ ++#define FIQ_TIMER0 (FIQ_START+INTERRUPT_TIMER0) ++#define FIQ_TIMER1 (FIQ_START+INTERRUPT_TIMER1) ++#define FIQ_TIMER2 (FIQ_START+INTERRUPT_TIMER2) ++#define FIQ_TIMER3 (FIQ_START+INTERRUPT_TIMER3) ++#define FIQ_CODEC0 (FIQ_START+INTERRUPT_CODEC0) ++#define FIQ_CODEC1 (FIQ_START+INTERRUPT_CODEC1) ++#define FIQ_CODEC2 (FIQ_START+INTERRUPT_CODEC2) ++#define FIQ_JPEG (FIQ_START+INTERRUPT_JPEG) ++#define FIQ_ISP (FIQ_START+INTERRUPT_ISP) ++#define FIQ_USB (FIQ_START+INTERRUPT_USB) ++#define FIQ_3D (FIQ_START+INTERRUPT_3D) ++#define FIQ_TRANSPOSER (FIQ_START+INTERRUPT_TRANSPOSER) ++#define FIQ_MULTICORESYNC0 (FIQ_START+INTERRUPT_MULTICORESYNC0) ++#define FIQ_MULTICORESYNC1 (FIQ_START+INTERRUPT_MULTICORESYNC1) ++#define FIQ_MULTICORESYNC2 (FIQ_START+INTERRUPT_MULTICORESYNC2) ++#define FIQ_MULTICORESYNC3 (FIQ_START+INTERRUPT_MULTICORESYNC3) ++#define FIQ_DMA0 (FIQ_START+INTERRUPT_DMA0) ++#define FIQ_DMA1 (FIQ_START+INTERRUPT_DMA1) ++#define FIQ_DMA2 (FIQ_START+INTERRUPT_DMA2) ++#define FIQ_DMA3 (FIQ_START+INTERRUPT_DMA3) ++#define FIQ_DMA4 (FIQ_START+INTERRUPT_DMA4) ++#define FIQ_DMA5 (FIQ_START+INTERRUPT_DMA5) ++#define FIQ_DMA6 (FIQ_START+INTERRUPT_DMA6) ++#define FIQ_DMA7 (FIQ_START+INTERRUPT_DMA7) ++#define FIQ_DMA8 (FIQ_START+INTERRUPT_DMA8) ++#define FIQ_DMA9 (FIQ_START+INTERRUPT_DMA9) ++#define FIQ_DMA10 (FIQ_START+INTERRUPT_DMA10) ++#define FIQ_DMA11 (FIQ_START+INTERRUPT_DMA11) ++#define FIQ_DMA12 (FIQ_START+INTERRUPT_DMA12) ++#define FIQ_AUX (FIQ_START+INTERRUPT_AUX) ++#define FIQ_ARM (FIQ_START+INTERRUPT_ARM) ++#define FIQ_VPUDMA (FIQ_START+INTERRUPT_VPUDMA) ++#define FIQ_HOSTPORT (FIQ_START+INTERRUPT_HOSTPORT) ++#define FIQ_VIDEOSCALER (FIQ_START+INTERRUPT_VIDEOSCALER) ++#define FIQ_CCP2TX (FIQ_START+INTERRUPT_CCP2TX) ++#define FIQ_SDC (FIQ_START+INTERRUPT_SDC) ++#define FIQ_DSI0 (FIQ_START+INTERRUPT_DSI0) ++#define FIQ_AVE (FIQ_START+INTERRUPT_AVE) ++#define FIQ_CAM0 (FIQ_START+INTERRUPT_CAM0) ++#define FIQ_CAM1 (FIQ_START+INTERRUPT_CAM1) ++#define FIQ_HDMI0 (FIQ_START+INTERRUPT_HDMI0) ++#define FIQ_HDMI1 (FIQ_START+INTERRUPT_HDMI1) ++#define FIQ_PIXELVALVE1 (FIQ_START+INTERRUPT_PIXELVALVE1) ++#define FIQ_I2CSPISLV (FIQ_START+INTERRUPT_I2CSPISLV) ++#define FIQ_DSI1 (FIQ_START+INTERRUPT_DSI1) ++#define FIQ_PWA0 (FIQ_START+INTERRUPT_PWA0) ++#define FIQ_PWA1 (FIQ_START+INTERRUPT_PWA1) ++#define FIQ_CPR (FIQ_START+INTERRUPT_CPR) ++#define FIQ_SMI (FIQ_START+INTERRUPT_SMI) ++#define FIQ_GPIO0 (FIQ_START+INTERRUPT_GPIO0) ++#define FIQ_GPIO1 (FIQ_START+INTERRUPT_GPIO1) ++#define FIQ_GPIO2 (FIQ_START+INTERRUPT_GPIO2) ++#define FIQ_GPIO3 (FIQ_START+INTERRUPT_GPIO3) ++#define FIQ_I2C (FIQ_START+INTERRUPT_I2C) ++#define FIQ_SPI (FIQ_START+INTERRUPT_SPI) ++#define FIQ_I2SPCM (FIQ_START+INTERRUPT_I2SPCM) ++#define FIQ_SDIO (FIQ_START+INTERRUPT_SDIO) ++#define FIQ_UART (FIQ_START+INTERRUPT_UART) ++#define FIQ_SLIMBUS (FIQ_START+INTERRUPT_SLIMBUS) ++#define FIQ_VEC (FIQ_START+INTERRUPT_VEC) ++#define FIQ_CPG (FIQ_START+INTERRUPT_CPG) ++#define FIQ_RNG (FIQ_START+INTERRUPT_RNG) ++#define FIQ_ARASANSDIO (FIQ_START+INTERRUPT_ARASANSDIO) ++#define FIQ_AVSPMON (FIQ_START+INTERRUPT_AVSPMON) ++ ++#define FIQ_ARM_TIMER (FIQ_START+INTERRUPT_ARM_TIMER) ++#define FIQ_ARM_MAILBOX (FIQ_START+INTERRUPT_ARM_MAILBOX) ++#define FIQ_ARM_DOORBELL_0 (FIQ_START+INTERRUPT_ARM_DOORBELL_0) ++#define FIQ_ARM_DOORBELL_1 (FIQ_START+INTERRUPT_ARM_DOORBELL_1) ++#define FIQ_VPU0_HALTED (FIQ_START+INTERRUPT_VPU0_HALTED) ++#define FIQ_VPU1_HALTED (FIQ_START+INTERRUPT_VPU1_HALTED) ++#define FIQ_ILLEGAL_TYPE0 (FIQ_START+INTERRUPT_ILLEGAL_TYPE0) ++#define FIQ_ILLEGAL_TYPE1 (FIQ_START+INTERRUPT_ILLEGAL_TYPE1) ++#define FIQ_PENDING1 (FIQ_START+INTERRUPT_PENDING1) ++#define FIQ_PENDING2 (FIQ_START+INTERRUPT_PENDING2) ++ ++#define FIQ_ARM_LOCAL_CNTPSIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPSIRQ) ++#define FIQ_ARM_LOCAL_CNTPNSIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPNSIRQ) ++#define FIQ_ARM_LOCAL_CNTHPIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTHPIRQ) ++#define FIQ_ARM_LOCAL_CNTVIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTVIRQ) ++#define FIQ_ARM_LOCAL_MAILBOX0 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX0) ++#define FIQ_ARM_LOCAL_MAILBOX1 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX1) ++#define FIQ_ARM_LOCAL_MAILBOX2 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX2) ++#define FIQ_ARM_LOCAL_MAILBOX3 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX3) ++#define FIQ_ARM_LOCAL_GPU_FAST (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_GPU_FAST) ++#define FIQ_ARM_LOCAL_PMU_FAST (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_PMU_FAST) ++#define FIQ_ARM_LOCAL_ZERO (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_ZERO) ++#define FIQ_ARM_LOCAL_TIMER (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_TIMER) ++ ++#define HARD_IRQS (128) ++#define FIQ_IRQS (128) ++#define GPIO_IRQ_START (HARD_IRQS + FIQ_IRQS) ++#define GPIO_IRQS (32*5) ++#define SPARE_ALLOC_IRQS 64 ++#define BCM2708_ALLOC_IRQS (HARD_IRQS+FIQ_IRQS+GPIO_IRQS+SPARE_ALLOC_IRQS) ++#define FREE_IRQS 128 ++#define NR_IRQS (BCM2708_ALLOC_IRQS+FREE_IRQS) ++ ++#endif /* _BCM2708_IRQS_H_ */ +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/memory.h linux-rpi/arch/arm/mach-bcm2709/include/mach/memory.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/memory.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2709/include/mach/memory.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,57 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/memory.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#ifndef __ASM_ARCH_MEMORY_H ++#define __ASM_ARCH_MEMORY_H ++ ++/* Memory overview: ++ ++ [ARMcore] <--virtual addr--> ++ [ARMmmu] <--physical addr--> ++ [GERTmap] <--bus add--> ++ [VCperiph] ++ ++*/ ++ ++/* ++ * Physical DRAM offset. ++ */ ++#define BCM_PLAT_PHYS_OFFSET UL(0x00000000) ++#define VC_ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */ ++ ++#ifdef CONFIG_BCM2708_NOL2CACHE ++ #define _REAL_BUS_OFFSET UL(0xC0000000) /* don't use L1 or L2 caches */ ++#else ++ #define _REAL_BUS_OFFSET UL(0x40000000) /* use L2 cache */ ++#endif ++ ++/* We're using the memory at 64M in the VideoCore for Linux - this adjustment ++ * will provide the offset into this area as well as setting the bits that ++ * stop the L1 and L2 cache from being used ++ * ++ * WARNING: this only works because the ARM is given memory at a fixed location ++ * (ARMMEM_OFFSET) ++ */ ++#define BUS_OFFSET (VC_ARMMEM_OFFSET + _REAL_BUS_OFFSET) ++#define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET)) ++#define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET)) ++#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET)) ++#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET)) ++ ++#endif +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/platform.h linux-rpi/arch/arm/mach-bcm2709/include/mach/platform.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/platform.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2709/include/mach/platform.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,227 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/platform.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef _BCM2708_PLATFORM_H ++#define _BCM2708_PLATFORM_H ++ ++ ++/* macros to get at IO space when running virtually */ ++#define IO_ADDRESS(x) (((x) & 0x00ffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000) ++ ++#define __io_address(n) IOMEM(IO_ADDRESS(n)) ++ ++ ++/* ++ * SDRAM ++ */ ++#define BCM2708_SDRAM_BASE 0x00000000 ++ ++/* ++ * Logic expansion modules ++ * ++ */ ++ ++ ++/* ------------------------------------------------------------------------ ++ * BCM2708 ARMCTRL Registers ++ * ------------------------------------------------------------------------ ++ */ ++ ++#define HW_REGISTER_RW(addr) (addr) ++#define HW_REGISTER_RO(addr) (addr) ++ ++#include "arm_control.h" ++#undef ARM_BASE ++ ++/* ++ * Definitions and addresses for the ARM CONTROL logic ++ * This file is manually generated. ++ */ ++ ++#define BCM2708_PERI_BASE 0x3F000000 ++#define IC0_BASE (BCM2708_PERI_BASE + 0x2000) ++#define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */ ++#define MPHI_BASE (BCM2708_PERI_BASE + 0x6000) /* Message -based Parallel Host Interface */ ++#define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */ ++#define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */ ++#define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */ ++#define PCM_CLOCK_BASE (BCM2708_PERI_BASE + 0x101098) /* PCM Clock */ ++#define RNG_BASE (BCM2708_PERI_BASE + 0x104000) /* Hardware RNG */ ++#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */ ++#define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */ ++#define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */ ++#define I2S_BASE (BCM2708_PERI_BASE + 0x203000) /* I2S */ ++#define SPI0_BASE (BCM2708_PERI_BASE + 0x204000) /* SPI0 */ ++#define BSC0_BASE (BCM2708_PERI_BASE + 0x205000) /* BSC0 I2C/TWI */ ++#define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */ ++#define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */ ++#define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */ ++#define BSC1_BASE (BCM2708_PERI_BASE + 0x804000) /* BSC1 I2C/TWI */ ++#define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */ ++#define MCORE_BASE (BCM2708_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/ ++ ++#define ARMCTRL_BASE (ARM_BASE + 0x000) ++#define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */ ++#define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */ ++#define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */ ++#define ARMCTRL_0_BELL_BASE (ARMCTRL_0_SBM_BASE + 0x40) /* User 0 (ARM)'s Doorbell */ ++#define ARMCTRL_0_MAIL0_BASE (ARMCTRL_0_SBM_BASE + 0x80) /* User 0 (ARM)'s Mailbox 0 */ ++ ++ ++/* ++ * Interrupt assignments ++ */ ++ ++#define ARM_IRQ1_BASE 0 ++#define INTERRUPT_TIMER0 (ARM_IRQ1_BASE + 0) ++#define INTERRUPT_TIMER1 (ARM_IRQ1_BASE + 1) ++#define INTERRUPT_TIMER2 (ARM_IRQ1_BASE + 2) ++#define INTERRUPT_TIMER3 (ARM_IRQ1_BASE + 3) ++#define INTERRUPT_CODEC0 (ARM_IRQ1_BASE + 4) ++#define INTERRUPT_CODEC1 (ARM_IRQ1_BASE + 5) ++#define INTERRUPT_CODEC2 (ARM_IRQ1_BASE + 6) ++#define INTERRUPT_VC_JPEG (ARM_IRQ1_BASE + 7) ++#define INTERRUPT_ISP (ARM_IRQ1_BASE + 8) ++#define INTERRUPT_VC_USB (ARM_IRQ1_BASE + 9) ++#define INTERRUPT_VC_3D (ARM_IRQ1_BASE + 10) ++#define INTERRUPT_TRANSPOSER (ARM_IRQ1_BASE + 11) ++#define INTERRUPT_MULTICORESYNC0 (ARM_IRQ1_BASE + 12) ++#define INTERRUPT_MULTICORESYNC1 (ARM_IRQ1_BASE + 13) ++#define INTERRUPT_MULTICORESYNC2 (ARM_IRQ1_BASE + 14) ++#define INTERRUPT_MULTICORESYNC3 (ARM_IRQ1_BASE + 15) ++#define INTERRUPT_DMA0 (ARM_IRQ1_BASE + 16) ++#define INTERRUPT_DMA1 (ARM_IRQ1_BASE + 17) ++#define INTERRUPT_VC_DMA2 (ARM_IRQ1_BASE + 18) ++#define INTERRUPT_VC_DMA3 (ARM_IRQ1_BASE + 19) ++#define INTERRUPT_DMA4 (ARM_IRQ1_BASE + 20) ++#define INTERRUPT_DMA5 (ARM_IRQ1_BASE + 21) ++#define INTERRUPT_DMA6 (ARM_IRQ1_BASE + 22) ++#define INTERRUPT_DMA7 (ARM_IRQ1_BASE + 23) ++#define INTERRUPT_DMA8 (ARM_IRQ1_BASE + 24) ++#define INTERRUPT_DMA9 (ARM_IRQ1_BASE + 25) ++#define INTERRUPT_DMA10 (ARM_IRQ1_BASE + 26) ++#define INTERRUPT_DMA11 (ARM_IRQ1_BASE + 27) ++#define INTERRUPT_DMA12 (ARM_IRQ1_BASE + 28) ++#define INTERRUPT_AUX (ARM_IRQ1_BASE + 29) ++#define INTERRUPT_ARM (ARM_IRQ1_BASE + 30) ++#define INTERRUPT_VPUDMA (ARM_IRQ1_BASE + 31) ++ ++#define ARM_IRQ2_BASE 32 ++#define INTERRUPT_HOSTPORT (ARM_IRQ2_BASE + 0) ++#define INTERRUPT_VIDEOSCALER (ARM_IRQ2_BASE + 1) ++#define INTERRUPT_CCP2TX (ARM_IRQ2_BASE + 2) ++#define INTERRUPT_SDC (ARM_IRQ2_BASE + 3) ++#define INTERRUPT_DSI0 (ARM_IRQ2_BASE + 4) ++#define INTERRUPT_AVE (ARM_IRQ2_BASE + 5) ++#define INTERRUPT_CAM0 (ARM_IRQ2_BASE + 6) ++#define INTERRUPT_CAM1 (ARM_IRQ2_BASE + 7) ++#define INTERRUPT_HDMI0 (ARM_IRQ2_BASE + 8) ++#define INTERRUPT_HDMI1 (ARM_IRQ2_BASE + 9) ++#define INTERRUPT_PIXELVALVE1 (ARM_IRQ2_BASE + 10) ++#define INTERRUPT_I2CSPISLV (ARM_IRQ2_BASE + 11) ++#define INTERRUPT_DSI1 (ARM_IRQ2_BASE + 12) ++#define INTERRUPT_PWA0 (ARM_IRQ2_BASE + 13) ++#define INTERRUPT_PWA1 (ARM_IRQ2_BASE + 14) ++#define INTERRUPT_CPR (ARM_IRQ2_BASE + 15) ++#define INTERRUPT_SMI (ARM_IRQ2_BASE + 16) ++#define INTERRUPT_GPIO0 (ARM_IRQ2_BASE + 17) ++#define INTERRUPT_GPIO1 (ARM_IRQ2_BASE + 18) ++#define INTERRUPT_GPIO2 (ARM_IRQ2_BASE + 19) ++#define INTERRUPT_GPIO3 (ARM_IRQ2_BASE + 20) ++#define INTERRUPT_VC_I2C (ARM_IRQ2_BASE + 21) ++#define INTERRUPT_VC_SPI (ARM_IRQ2_BASE + 22) ++#define INTERRUPT_VC_I2SPCM (ARM_IRQ2_BASE + 23) ++#define INTERRUPT_VC_SDIO (ARM_IRQ2_BASE + 24) ++#define INTERRUPT_VC_UART (ARM_IRQ2_BASE + 25) ++#define INTERRUPT_SLIMBUS (ARM_IRQ2_BASE + 26) ++#define INTERRUPT_VEC (ARM_IRQ2_BASE + 27) ++#define INTERRUPT_CPG (ARM_IRQ2_BASE + 28) ++#define INTERRUPT_RNG (ARM_IRQ2_BASE + 29) ++#define INTERRUPT_VC_ARASANSDIO (ARM_IRQ2_BASE + 30) ++#define INTERRUPT_AVSPMON (ARM_IRQ2_BASE + 31) ++ ++#define ARM_IRQ0_BASE 64 ++#define INTERRUPT_ARM_TIMER (ARM_IRQ0_BASE + 0) ++#define INTERRUPT_ARM_MAILBOX (ARM_IRQ0_BASE + 1) ++#define INTERRUPT_ARM_DOORBELL_0 (ARM_IRQ0_BASE + 2) ++#define INTERRUPT_ARM_DOORBELL_1 (ARM_IRQ0_BASE + 3) ++#define INTERRUPT_VPU0_HALTED (ARM_IRQ0_BASE + 4) ++#define INTERRUPT_VPU1_HALTED (ARM_IRQ0_BASE + 5) ++#define INTERRUPT_ILLEGAL_TYPE0 (ARM_IRQ0_BASE + 6) ++#define INTERRUPT_ILLEGAL_TYPE1 (ARM_IRQ0_BASE + 7) ++#define INTERRUPT_PENDING1 (ARM_IRQ0_BASE + 8) ++#define INTERRUPT_PENDING2 (ARM_IRQ0_BASE + 9) ++#define INTERRUPT_JPEG (ARM_IRQ0_BASE + 10) ++#define INTERRUPT_USB (ARM_IRQ0_BASE + 11) ++#define INTERRUPT_3D (ARM_IRQ0_BASE + 12) ++#define INTERRUPT_DMA2 (ARM_IRQ0_BASE + 13) ++#define INTERRUPT_DMA3 (ARM_IRQ0_BASE + 14) ++#define INTERRUPT_I2C (ARM_IRQ0_BASE + 15) ++#define INTERRUPT_SPI (ARM_IRQ0_BASE + 16) ++#define INTERRUPT_I2SPCM (ARM_IRQ0_BASE + 17) ++#define INTERRUPT_SDIO (ARM_IRQ0_BASE + 18) ++#define INTERRUPT_UART (ARM_IRQ0_BASE + 19) ++#define INTERRUPT_ARASANSDIO (ARM_IRQ0_BASE + 20) ++ ++#define ARM_IRQ_LOCAL_BASE 96 ++#define INTERRUPT_ARM_LOCAL_CNTPSIRQ (ARM_IRQ_LOCAL_BASE + 0) ++#define INTERRUPT_ARM_LOCAL_CNTPNSIRQ (ARM_IRQ_LOCAL_BASE + 1) ++#define INTERRUPT_ARM_LOCAL_CNTHPIRQ (ARM_IRQ_LOCAL_BASE + 2) ++#define INTERRUPT_ARM_LOCAL_CNTVIRQ (ARM_IRQ_LOCAL_BASE + 3) ++#define INTERRUPT_ARM_LOCAL_MAILBOX0 (ARM_IRQ_LOCAL_BASE + 4) ++#define INTERRUPT_ARM_LOCAL_MAILBOX1 (ARM_IRQ_LOCAL_BASE + 5) ++#define INTERRUPT_ARM_LOCAL_MAILBOX2 (ARM_IRQ_LOCAL_BASE + 6) ++#define INTERRUPT_ARM_LOCAL_MAILBOX3 (ARM_IRQ_LOCAL_BASE + 7) ++#define INTERRUPT_ARM_LOCAL_GPU_FAST (ARM_IRQ_LOCAL_BASE + 8) ++#define INTERRUPT_ARM_LOCAL_PMU_FAST (ARM_IRQ_LOCAL_BASE + 9) ++#define INTERRUPT_ARM_LOCAL_ZERO (ARM_IRQ_LOCAL_BASE + 10) ++#define INTERRUPT_ARM_LOCAL_TIMER (ARM_IRQ_LOCAL_BASE + 11) ++ ++/* ++ * Watchdog ++ */ ++#define PM_RSTC (PM_BASE+0x1c) ++#define PM_RSTS (PM_BASE+0x20) ++#define PM_WDOG (PM_BASE+0x24) ++ ++#define PM_WDOG_RESET 0000000000 ++#define PM_PASSWORD 0x5a000000 ++#define PM_WDOG_TIME_SET 0x000fffff ++#define PM_RSTC_WRCFG_CLR 0xffffffcf ++#define PM_RSTC_WRCFG_SET 0x00000030 ++#define PM_RSTC_WRCFG_FULL_RESET 0x00000020 ++#define PM_RSTC_RESET 0x00000102 ++ ++#define PM_RSTS_HADPOR_SET 0x00001000 ++#define PM_RSTS_HADSRH_SET 0x00000400 ++#define PM_RSTS_HADSRF_SET 0x00000200 ++#define PM_RSTS_HADSRQ_SET 0x00000100 ++#define PM_RSTS_HADWRH_SET 0x00000040 ++#define PM_RSTS_HADWRF_SET 0x00000020 ++#define PM_RSTS_HADWRQ_SET 0x00000010 ++#define PM_RSTS_HADDRH_SET 0x00000004 ++#define PM_RSTS_HADDRF_SET 0x00000002 ++#define PM_RSTS_HADDRQ_SET 0x00000001 ++ ++#define UART0_CLOCK 3000000 ++ ++#endif ++ ++/* END */ +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/system.h linux-rpi/arch/arm/mach-bcm2709/include/mach/system.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/system.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2709/include/mach/system.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,38 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/system.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * Copyright (C) 2003 ARM Limited ++ * Copyright (C) 2000 Deep Blue Solutions Ltd ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#ifndef __ASM_ARCH_SYSTEM_H ++#define __ASM_ARCH_SYSTEM_H ++ ++#include ++#include ++#include ++ ++static inline void arch_idle(void) ++{ ++ /* ++ * This should do all the clock switching ++ * and wait for interrupt tricks ++ */ ++ cpu_do_idle(); ++} ++ ++#endif +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/timex.h linux-rpi/arch/arm/mach-bcm2709/include/mach/timex.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/timex.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2709/include/mach/timex.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,23 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/timex.h ++ * ++ * BCM2708 sysem clock frequency ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#define CLOCK_TICK_RATE (1000000) +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/uncompress.h linux-rpi/arch/arm/mach-bcm2709/include/mach/uncompress.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/uncompress.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2709/include/mach/uncompress.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,84 @@ ++/* ++ * arch/arm/mach-bcn2708/include/mach/uncompress.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * Copyright (C) 2003 ARM Limited ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++ ++#define UART_BAUD 115200 ++ ++#define BCM2708_UART_DR __io(UART0_BASE + UART01x_DR) ++#define BCM2708_UART_FR __io(UART0_BASE + UART01x_FR) ++#define BCM2708_UART_IBRD __io(UART0_BASE + UART011_IBRD) ++#define BCM2708_UART_FBRD __io(UART0_BASE + UART011_FBRD) ++#define BCM2708_UART_LCRH __io(UART0_BASE + UART011_LCRH) ++#define BCM2708_UART_CR __io(UART0_BASE + UART011_CR) ++ ++/* ++ * This does not append a newline ++ */ ++static inline void putc(int c) ++{ ++ while (__raw_readl(BCM2708_UART_FR) & UART01x_FR_TXFF) ++ barrier(); ++ ++ __raw_writel(c, BCM2708_UART_DR); ++} ++ ++static inline void flush(void) ++{ ++ int fr; ++ ++ do { ++ fr = __raw_readl(BCM2708_UART_FR); ++ barrier(); ++ } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE); ++} ++ ++static inline void arch_decomp_setup(void) ++{ ++ int temp, div, rem, frac; ++ ++ temp = 16 * UART_BAUD; ++ div = UART0_CLOCK / temp; ++ rem = UART0_CLOCK % temp; ++ temp = (8 * rem) / UART_BAUD; ++ frac = (temp >> 1) + (temp & 1); ++ ++ /* Make sure the UART is disabled before we start */ ++ __raw_writel(0, BCM2708_UART_CR); ++ ++ /* Set the baud rate */ ++ __raw_writel(div, BCM2708_UART_IBRD); ++ __raw_writel(frac, BCM2708_UART_FBRD); ++ ++ /* Set the UART to 8n1, FIFO enabled */ ++ __raw_writel(UART01x_LCRH_WLEN_8 | UART01x_LCRH_FEN, BCM2708_UART_LCRH); ++ ++ /* Enable the UART */ ++ __raw_writel(UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_RXE, ++ BCM2708_UART_CR); ++} ++ ++/* ++ * nothing to do ++ */ ++#define arch_decomp_wdog() +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/vc_support.h linux-rpi/arch/arm/mach-bcm2709/include/mach/vc_support.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/vc_support.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2709/include/mach/vc_support.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,69 @@ ++#ifndef _VC_SUPPORT_H_ ++#define _VC_SUPPORT_H_ ++ ++/* ++ * vc_support.h ++ * ++ * Created on: 25 Nov 2012 ++ * Author: Simon ++ */ ++ ++enum { ++/* ++ If a MEM_HANDLE_T is discardable, the memory manager may resize it to size ++ 0 at any time when it is not locked or retained. ++ */ ++ MEM_FLAG_DISCARDABLE = 1 << 0, ++ ++ /* ++ If a MEM_HANDLE_T is allocating (or normal), its block of memory will be ++ accessed in an allocating fashion through the cache. ++ */ ++ MEM_FLAG_NORMAL = 0 << 2, ++ MEM_FLAG_ALLOCATING = MEM_FLAG_NORMAL, ++ ++ /* ++ If a MEM_HANDLE_T is direct, its block of memory will be accessed ++ directly, bypassing the cache. ++ */ ++ MEM_FLAG_DIRECT = 1 << 2, ++ ++ /* ++ If a MEM_HANDLE_T is coherent, its block of memory will be accessed in a ++ non-allocating fashion through the cache. ++ */ ++ MEM_FLAG_COHERENT = 2 << 2, ++ ++ /* ++ If a MEM_HANDLE_T is L1-nonallocating, its block of memory will be accessed by ++ the VPU in a fashion which is allocating in L2, but only coherent in L1. ++ */ ++ MEM_FLAG_L1_NONALLOCATING = (MEM_FLAG_DIRECT | MEM_FLAG_COHERENT), ++ ++ /* ++ If a MEM_HANDLE_T is zero'd, its contents are set to 0 rather than ++ MEM_HANDLE_INVALID on allocation and resize up. ++ */ ++ MEM_FLAG_ZERO = 1 << 4, ++ ++ /* ++ If a MEM_HANDLE_T is uninitialised, it will not be reset to a defined value ++ (either zero, or all 1's) on allocation. ++ */ ++ MEM_FLAG_NO_INIT = 1 << 5, ++ ++ /* ++ Hints. ++ */ ++ MEM_FLAG_HINT_PERMALOCK = 1 << 6, /* Likely to be locked for long periods of time. */ ++}; ++ ++unsigned int AllocateVcMemory(unsigned int *pHandle, unsigned int size, unsigned int alignment, unsigned int flags); ++unsigned int ReleaseVcMemory(unsigned int handle); ++unsigned int LockVcMemory(unsigned int *pBusAddress, unsigned int handle); ++unsigned int UnlockVcMemory(unsigned int handle); ++ ++unsigned int ExecuteVcCode(unsigned int code, ++ unsigned int r0, unsigned int r1, unsigned int r2, unsigned int r3, unsigned int r4, unsigned int r5); ++ ++#endif +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/vmalloc.h linux-rpi/arch/arm/mach-bcm2709/include/mach/vmalloc.h +--- linux-4.1.13.orig/arch/arm/mach-bcm2709/include/mach/vmalloc.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2709/include/mach/vmalloc.h 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,20 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/vmalloc.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#define VMALLOC_END (0xff000000) +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/Kconfig linux-rpi/arch/arm/mach-bcm2709/Kconfig +--- linux-4.1.13.orig/arch/arm/mach-bcm2709/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2709/Kconfig 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,42 @@ ++menu "Broadcom BCM2709 Implementations" ++ depends on ARCH_BCM2709 ++ ++config MACH_BCM2709 ++ bool "Broadcom BCM2709 Development Platform" ++ help ++ Include support for the Broadcom(R) BCM2709 platform. ++ ++config BCM2709_DT ++ bool "BCM2709 Device Tree support" ++ depends on MACH_BCM2709 ++ default n ++ select USE_OF ++ select ARCH_REQUIRE_GPIOLIB ++ select PINCTRL ++ select PINCTRL_BCM2835 ++ help ++ Enable Device Tree support for BCM2709 ++ ++config BCM2708_GPIO ++ bool "BCM2709 gpio support" ++ depends on MACH_BCM2709 ++ select ARCH_REQUIRE_GPIOLIB ++ default y ++ help ++ Include support for the Broadcom(R) BCM2709 gpio. ++ ++config BCM2708_NOL2CACHE ++ bool "Videocore L2 cache disable" ++ depends on MACH_BCM2709 ++ default y ++ help ++ Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt. ++ ++config BCM2708_SPIDEV ++ bool "Bind spidev to SPI0 master" ++ depends on MACH_BCM2709 ++ depends on SPI ++ default y ++ help ++ Binds spidev driver to the SPI0 master ++endmenu +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/Makefile linux-rpi/arch/arm/mach-bcm2709/Makefile +--- linux-4.1.13.orig/arch/arm/mach-bcm2709/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2709/Makefile 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,6 @@ ++# ++# Makefile for the linux kernel. ++# ++ ++obj-$(CONFIG_MACH_BCM2709) += bcm2709.o armctrl.o ++obj-$(CONFIG_BCM2708_GPIO) += bcm2708_gpio.o +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/Makefile.boot linux-rpi/arch/arm/mach-bcm2709/Makefile.boot +--- linux-4.1.13.orig/arch/arm/mach-bcm2709/Makefile.boot 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2709/Makefile.boot 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,3 @@ ++ zreladdr-y := 0x00008000 ++params_phys-y := 0x00000100 ++initrd_phys-y := 0x00800000 +diff -Nur linux-4.1.13.orig/arch/arm/mach-bcm2709/vc_support.c linux-rpi/arch/arm/mach-bcm2709/vc_support.c +--- linux-4.1.13.orig/arch/arm/mach-bcm2709/vc_support.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/arch/arm/mach-bcm2709/vc_support.c 2015-11-29 09:42:34.791439401 +0100 +@@ -0,0 +1,318 @@ ++/* ++ * vc_support.c ++ * ++ * Created on: 25 Nov 2012 ++ * Author: Simon ++ */ ++ ++#include ++#include ++ ++#ifdef ECLIPSE_IGNORE ++ ++#define __user ++#define __init ++#define __exit ++#define __iomem ++#define KERN_DEBUG ++#define KERN_ERR ++#define KERN_WARNING ++#define KERN_INFO ++#define _IOWR(a, b, c) b ++#define _IOW(a, b, c) b ++#define _IO(a, b) b ++ ++#endif ++ ++/****** VC MAILBOX FUNCTIONALITY ******/ ++unsigned int AllocateVcMemory(unsigned int *pHandle, unsigned int size, unsigned int alignment, unsigned int flags) ++{ ++ struct vc_msg ++ { ++ unsigned int m_msgSize; ++ unsigned int m_response; ++ ++ struct vc_tag ++ { ++ unsigned int m_tagId; ++ unsigned int m_sendBufferSize; ++ union { ++ unsigned int m_sendDataSize; ++ unsigned int m_recvDataSize; ++ }; ++ ++ struct args ++ { ++ union { ++ unsigned int m_size; ++ unsigned int m_handle; ++ }; ++ unsigned int m_alignment; ++ unsigned int m_flags; ++ } m_args; ++ } m_tag; ++ ++ unsigned int m_endTag; ++ } msg; ++ int s; ++ ++ msg.m_msgSize = sizeof(msg); ++ msg.m_response = 0; ++ msg.m_endTag = 0; ++ ++ //fill in the tag for the allocation command ++ msg.m_tag.m_tagId = 0x3000c; ++ msg.m_tag.m_sendBufferSize = 12; ++ msg.m_tag.m_sendDataSize = 12; ++ ++ //fill in our args ++ msg.m_tag.m_args.m_size = size; ++ msg.m_tag.m_args.m_alignment = alignment; ++ msg.m_tag.m_args.m_flags = flags; ++ ++ //run the command ++ s = bcm_mailbox_property(&msg, sizeof(msg)); ++ ++ if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004) ++ { ++ *pHandle = msg.m_tag.m_args.m_handle; ++ return 0; ++ } ++ else ++ { ++ printk(KERN_ERR "failed to allocate vc memory: s=%d response=%08x recv data size=%08x\n", ++ s, msg.m_response, msg.m_tag.m_recvDataSize); ++ return 1; ++ } ++} ++ ++unsigned int ReleaseVcMemory(unsigned int handle) ++{ ++ struct vc_msg ++ { ++ unsigned int m_msgSize; ++ unsigned int m_response; ++ ++ struct vc_tag ++ { ++ unsigned int m_tagId; ++ unsigned int m_sendBufferSize; ++ union { ++ unsigned int m_sendDataSize; ++ unsigned int m_recvDataSize; ++ }; ++ ++ struct args ++ { ++ union { ++ unsigned int m_handle; ++ unsigned int m_error; ++ }; ++ } m_args; ++ } m_tag; ++ ++ unsigned int m_endTag; ++ } msg; ++ int s; ++ ++ msg.m_msgSize = sizeof(msg); ++ msg.m_response = 0; ++ msg.m_endTag = 0; ++ ++ //fill in the tag for the release command ++ msg.m_tag.m_tagId = 0x3000f; ++ msg.m_tag.m_sendBufferSize = 4; ++ msg.m_tag.m_sendDataSize = 4; ++ ++ //pass across the handle ++ msg.m_tag.m_args.m_handle = handle; ++ ++ s = bcm_mailbox_property(&msg, sizeof(msg)); ++ ++ if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004 && msg.m_tag.m_args.m_error == 0) ++ return 0; ++ else ++ { ++ printk(KERN_ERR "failed to release vc memory: s=%d response=%08x recv data size=%08x error=%08x\n", ++ s, msg.m_response, msg.m_tag.m_recvDataSize, msg.m_tag.m_args.m_error); ++ return 1; ++ } ++} ++ ++unsigned int LockVcMemory(unsigned int *pBusAddress, unsigned int handle) ++{ ++ struct vc_msg ++ { ++ unsigned int m_msgSize; ++ unsigned int m_response; ++ ++ struct vc_tag ++ { ++ unsigned int m_tagId; ++ unsigned int m_sendBufferSize; ++ union { ++ unsigned int m_sendDataSize; ++ unsigned int m_recvDataSize; ++ }; ++ ++ struct args ++ { ++ union { ++ unsigned int m_handle; ++ unsigned int m_busAddress; ++ }; ++ } m_args; ++ } m_tag; ++ ++ unsigned int m_endTag; ++ } msg; ++ int s; ++ ++ msg.m_msgSize = sizeof(msg); ++ msg.m_response = 0; ++ msg.m_endTag = 0; ++ ++ //fill in the tag for the lock command ++ msg.m_tag.m_tagId = 0x3000d; ++ msg.m_tag.m_sendBufferSize = 4; ++ msg.m_tag.m_sendDataSize = 4; ++ ++ //pass across the handle ++ msg.m_tag.m_args.m_handle = handle; ++ ++ s = bcm_mailbox_property(&msg, sizeof(msg)); ++ ++ if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004) ++ { ++ //pick out the bus address ++ *pBusAddress = msg.m_tag.m_args.m_busAddress; ++ return 0; ++ } ++ else ++ { ++ printk(KERN_ERR "failed to lock vc memory: s=%d response=%08x recv data size=%08x\n", ++ s, msg.m_response, msg.m_tag.m_recvDataSize); ++ return 1; ++ } ++} ++ ++unsigned int UnlockVcMemory(unsigned int handle) ++{ ++ struct vc_msg ++ { ++ unsigned int m_msgSize; ++ unsigned int m_response; ++ ++ struct vc_tag ++ { ++ unsigned int m_tagId; ++ unsigned int m_sendBufferSize; ++ union { ++ unsigned int m_sendDataSize; ++ unsigned int m_recvDataSize; ++ }; ++ ++ struct args ++ { ++ union { ++ unsigned int m_handle; ++ unsigned int m_error; ++ }; ++ } m_args; ++ } m_tag; ++ ++ unsigned int m_endTag; ++ } msg; ++ int s; ++ ++ msg.m_msgSize = sizeof(msg); ++ msg.m_response = 0; ++ msg.m_endTag = 0; ++ ++ //fill in the tag for the unlock command ++ msg.m_tag.m_tagId = 0x3000e; ++ msg.m_tag.m_sendBufferSize = 4; ++ msg.m_tag.m_sendDataSize = 4; ++ ++ //pass across the handle ++ msg.m_tag.m_args.m_handle = handle; ++ ++ s = bcm_mailbox_property(&msg, sizeof(msg)); ++ ++ //check the error code too ++ if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004 && msg.m_tag.m_args.m_error == 0) ++ return 0; ++ else ++ { ++ printk(KERN_ERR "failed to unlock vc memory: s=%d response=%08x recv data size=%08x error%08x\n", ++ s, msg.m_response, msg.m_tag.m_recvDataSize, msg.m_tag.m_args.m_error); ++ return 1; ++ } ++} ++ ++unsigned int ExecuteVcCode(unsigned int code, ++ unsigned int r0, unsigned int r1, unsigned int r2, unsigned int r3, unsigned int r4, unsigned int r5) ++{ ++ struct vc_msg ++ { ++ unsigned int m_msgSize; ++ unsigned int m_response; ++ ++ struct vc_tag ++ { ++ unsigned int m_tagId; ++ unsigned int m_sendBufferSize; ++ union { ++ unsigned int m_sendDataSize; ++ unsigned int m_recvDataSize; ++ }; ++ ++ struct args ++ { ++ union { ++ unsigned int m_pCode; ++ unsigned int m_return; ++ }; ++ unsigned int m_r0; ++ unsigned int m_r1; ++ unsigned int m_r2; ++ unsigned int m_r3; ++ unsigned int m_r4; ++ unsigned int m_r5; ++ } m_args; ++ } m_tag; ++ ++ unsigned int m_endTag; ++ } msg; ++ int s; ++ ++ msg.m_msgSize = sizeof(msg); ++ msg.m_response = 0; ++ msg.m_endTag = 0; ++ ++ //fill in the tag for the unlock command ++ msg.m_tag.m_tagId = 0x30010; ++ msg.m_tag.m_sendBufferSize = 28; ++ msg.m_tag.m_sendDataSize = 28; ++ ++ //pass across the handle ++ msg.m_tag.m_args.m_pCode = code; ++ msg.m_tag.m_args.m_r0 = r0; ++ msg.m_tag.m_args.m_r1 = r1; ++ msg.m_tag.m_args.m_r2 = r2; ++ msg.m_tag.m_args.m_r3 = r3; ++ msg.m_tag.m_args.m_r4 = r4; ++ msg.m_tag.m_args.m_r5 = r5; ++ ++ s = bcm_mailbox_property(&msg, sizeof(msg)); ++ ++ //check the error code too ++ if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004) ++ return msg.m_tag.m_args.m_return; ++ else ++ { ++ printk(KERN_ERR "failed to execute: s=%d response=%08x recv data size=%08x\n", ++ s, msg.m_response, msg.m_tag.m_recvDataSize); ++ return 1; ++ } ++} +diff -Nur linux-4.1.13.orig/arch/arm/Makefile linux-rpi/arch/arm/Makefile +--- linux-4.1.13.orig/arch/arm/Makefile 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/arch/arm/Makefile 2015-11-29 09:42:34.559454815 +0100 +@@ -150,6 +150,8 @@ + + # Machine directory name. This list is sorted alphanumerically + # by CONFIG_* macro name. ++machine-$(CONFIG_ARCH_BCM2708) += bcm2708 ++machine-$(CONFIG_ARCH_BCM2709) += bcm2709 + machine-$(CONFIG_ARCH_ALPINE) += alpine + machine-$(CONFIG_ARCH_AT91) += at91 + machine-$(CONFIG_ARCH_AXXIA) += axxia +diff -Nur linux-4.1.13.orig/arch/arm/mm/Kconfig linux-rpi/arch/arm/mm/Kconfig +--- linux-4.1.13.orig/arch/arm/mm/Kconfig 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/arch/arm/mm/Kconfig 2015-11-29 09:42:35.047422392 +0100 +@@ -358,7 +358,7 @@ + + # ARMv6 + config CPU_V6 +- bool "Support ARM V6 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V6) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX) ++ bool "Support ARM V6 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V6) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || MACH_BCM2708) + select CPU_32v6 + select CPU_ABRT_EV6 + select CPU_CACHE_V6 +diff -Nur linux-4.1.13.orig/arch/arm/mm/proc-v6.S linux-rpi/arch/arm/mm/proc-v6.S +--- linux-4.1.13.orig/arch/arm/mm/proc-v6.S 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/arch/arm/mm/proc-v6.S 2015-11-29 09:42:35.055421861 +0100 +@@ -73,10 +73,19 @@ + * + * IRQs are already disabled. + */ ++ ++/* See jira SW-5991 for details of this workaround */ + ENTRY(cpu_v6_do_idle) +- mov r1, #0 +- mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode +- mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt ++ .align 5 ++ mov r1, #2 ++1: subs r1, #1 ++ nop ++ mcreq p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode ++ mcreq p15, 0, r1, c7, c0, 4 @ wait for interrupt ++ nop ++ nop ++ nop ++ bne 1b + ret lr + + ENTRY(cpu_v6_dcache_clean_area) +diff -Nur linux-4.1.13.orig/arch/arm/mm/proc-v7.S linux-rpi/arch/arm/mm/proc-v7.S +--- linux-4.1.13.orig/arch/arm/mm/proc-v7.S 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/arch/arm/mm/proc-v7.S 2015-11-29 09:42:35.055421861 +0100 +@@ -460,6 +460,7 @@ + orr r0, r0, r6 @ set them + THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions + ret lr @ return to head.S:__ret ++ .space 256 + ENDPROC(__v7_setup) + + .align 2 +diff -Nur linux-4.1.13.orig/arch/arm/tools/mach-types linux-rpi/arch/arm/tools/mach-types +--- linux-4.1.13.orig/arch/arm/tools/mach-types 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/arch/arm/tools/mach-types 2015-11-29 09:42:35.103418671 +0100 +@@ -522,6 +522,8 @@ + prima2_evb MACH_PRIMA2_EVB PRIMA2_EVB 3103 + paz00 MACH_PAZ00 PAZ00 3128 + acmenetusfoxg20 MACH_ACMENETUSFOXG20 ACMENETUSFOXG20 3129 ++bcm2708 MACH_BCM2708 BCM2708 3138 ++bcm2709 MACH_BCM2709 BCM2709 3139 + ag5evm MACH_AG5EVM AG5EVM 3189 + ics_if_voip MACH_ICS_IF_VOIP ICS_IF_VOIP 3206 + wlf_cragg_6410 MACH_WLF_CRAGG_6410 WLF_CRAGG_6410 3207 +diff -Nur linux-4.1.13.orig/Documentation/ABI/stable/sysfs-driver-w1_ds28ea00 linux-rpi/Documentation/ABI/stable/sysfs-driver-w1_ds28ea00 +--- linux-4.1.13.orig/Documentation/ABI/stable/sysfs-driver-w1_ds28ea00 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/Documentation/ABI/stable/sysfs-driver-w1_ds28ea00 2015-11-29 09:42:34.091485909 +0100 +@@ -0,0 +1,6 @@ ++What: /sys/bus/w1/devices/.../w1_seq ++Date: Apr 2015 ++Contact: Matt Campbell ++Description: Support for the DS28EA00 chain sequence function ++ see Documentation/w1/slaves/w1_therm for detailed information ++Users: any user space application which wants to communicate with DS28EA00 +diff -Nur linux-4.1.13.orig/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt linux-rpi/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt +--- linux-4.1.13.orig/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/Documentation/devicetree/bindings/dma/brcm,bcm2835-dma.txt 2015-11-29 09:42:34.191479265 +0100 +@@ -48,8 +48,8 @@ + + bcm2835_i2s: i2s@7e203000 { + compatible = "brcm,bcm2835-i2s"; +- reg = < 0x7e203000 0x20>, +- < 0x7e101098 0x02>; ++ reg = < 0x7e203000 0x24>, ++ < 0x7e101098 0x08>; + + dmas = <&dma 2>, + <&dma 3>; +diff -Nur linux-4.1.13.orig/Documentation/devicetree/bindings/input/touchscreen/focaltech-ft6236.txt linux-rpi/Documentation/devicetree/bindings/input/touchscreen/focaltech-ft6236.txt +--- linux-4.1.13.orig/Documentation/devicetree/bindings/input/touchscreen/focaltech-ft6236.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/Documentation/devicetree/bindings/input/touchscreen/focaltech-ft6236.txt 2015-11-29 09:42:34.203478468 +0100 +@@ -0,0 +1,35 @@ ++* FocalTech FT6236 I2C touchscreen controller ++ ++Required properties: ++ - compatible : "focaltech,ft6236" ++ - reg : I2C slave address of the chip (0x38) ++ - interrupt-parent : a phandle pointing to the interrupt controller ++ serving the interrupt for this chip ++ - interrupts : interrupt specification for the touch controller ++ interrupt ++ - reset-gpios : GPIO specification for the RSTN input ++ - touchscreen-size-x : horizontal resolution of touchscreen (in pixels) ++ - touchscreen-size-y : vertical resolution of touchscreen (in pixels) ++ ++Optional properties: ++ - touchscreen-fuzz-x : horizontal noise value of the absolute input ++ device (in pixels) ++ - touchscreen-fuzz-y : vertical noise value of the absolute input ++ device (in pixels) ++ - touchscreen-inverted-x : X axis is inverted (boolean) ++ - touchscreen-inverted-y : Y axis is inverted (boolean) ++ - touchscreen-swapped-x-y: X and Y axis are swapped (boolean) ++ Swapping is done after inverting the axis ++ ++Example: ++ ++ ft6x06@38 { ++ compatible = "focaltech,ft6236"; ++ reg = <0x38>; ++ interrupt-parent = <&gpio>; ++ interrupts = <23 2>; ++ touchscreen-size-x = <320>; ++ touchscreen-size-y = <480>; ++ touchscreen-inverted-x; ++ touchscreen-swapped-x-y; ++ }; +diff -Nur linux-4.1.13.orig/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi-dev.txt linux-rpi/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi-dev.txt +--- linux-4.1.13.orig/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi-dev.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi-dev.txt 2015-11-29 09:42:34.211477936 +0100 +@@ -0,0 +1,17 @@ ++* Broadcom BCM2835 SMI character device driver. ++ ++SMI or secondary memory interface is a peripheral specific to certain Broadcom ++SOCs, and is helpful for talking to things like parallel-interface displays ++and NAND flashes (in fact, most things with a parallel register interface). ++ ++This driver adds a character device which provides a user-space interface to ++an instance of the SMI driver. ++ ++Required properties: ++- compatible: "brcm,bcm2835-smi-dev" ++- smi_handle: a phandle to the smi node. ++ ++Optional properties: ++- None. ++ ++ +diff -Nur linux-4.1.13.orig/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi.txt linux-rpi/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi.txt +--- linux-4.1.13.orig/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi.txt 2015-11-29 09:42:34.211477936 +0100 +@@ -0,0 +1,48 @@ ++* Broadcom BCM2835 SMI driver. ++ ++SMI or secondary memory interface is a peripheral specific to certain Broadcom ++SOCs, and is helpful for talking to things like parallel-interface displays ++and NAND flashes (in fact, most things with a parallel register interface). ++ ++Required properties: ++- compatible: "brcm,bcm2835-smi" ++- reg: Should contain location and length of SMI registers and SMI clkman regs ++- interrupts: *the* SMI interrupt. ++- pinctrl-names: should be "default". ++- pinctrl-0: the phandle of the gpio pin node. ++- brcm,smi-clock-source: the clock source for clkman ++- brcm,smi-clock-divisor: the integer clock divisor for clkman ++- dmas: the dma controller phandle and the DREQ number (4 on a 2835) ++- dma-names: the name used by the driver to request its channel. ++ Should be "rx-tx". ++ ++Optional properties: ++- None. ++ ++Examples: ++ ++8 data pin configuration: ++ ++smi: smi@7e600000 { ++ compatible = "brcm,bcm2835-smi"; ++ reg = <0x7e600000 0x44>, <0x7e1010b0 0x8>; ++ interrupts = <2 16>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&smi_pins>; ++ brcm,smi-clock-source = <6>; ++ brcm,smi-clock-divisor = <4>; ++ dmas = <&dma 4>; ++ dma-names = "rx-tx"; ++ ++ status = "okay"; ++}; ++ ++smi_pins: smi_pins { ++ brcm,pins = <2 3 4 5 6 7 8 9 10 11 12 13 14 15>; ++ /* Alt 1: SMI */ ++ brcm,function = <5 5 5 5 5 5 5 5 5 5 5 5 5 5>; ++ /* /CS, /WE and /OE are pulled high, as they are ++ generally active low signals */ ++ brcm,pull = <2 2 2 2 2 2 0 0 0 0 0 0 0 0>; ++}; ++ +diff -Nur linux-4.1.13.orig/Documentation/devicetree/bindings/mtd/brcm,bcm2835-smi-nand.txt linux-rpi/Documentation/devicetree/bindings/mtd/brcm,bcm2835-smi-nand.txt +--- linux-4.1.13.orig/Documentation/devicetree/bindings/mtd/brcm,bcm2835-smi-nand.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/Documentation/devicetree/bindings/mtd/brcm,bcm2835-smi-nand.txt 2015-11-29 09:42:34.211477936 +0100 +@@ -0,0 +1,42 @@ ++* BCM2835 SMI NAND flash ++ ++This driver is a shim between the BCM2835 SMI driver (SMI is a peripheral for ++talking to parallel register interfaces) and Linux's MTD layer. ++ ++Required properties: ++- compatible: "brcm,bcm2835-smi-nand" ++- status: "okay" ++ ++Optional properties: ++- partition@n, where n is an integer from a consecutive sequence starting at 0 ++ - Difficult to store partition table on NAND device - normally put it ++ in the source code, kernel bootparams, or device tree (the best way!) ++ - Sub-properties: ++ - label: the partition name, as shown by mtdinfo /dev/mtd* ++ - reg: the size and offset of this partition. ++ - (optional) read-only: an empty property flagging as read only ++ ++Example: ++ ++nand: flash@0 { ++ compatible = "brcm,bcm2835-smi-nand"; ++ status = "okay"; ++ ++ partition@0 { ++ label = "stage2"; ++ // 128k ++ reg = <0 0x20000>; ++ read-only; ++ }; ++ partition@1 { ++ label = "firmware"; ++ // 16M ++ reg = <0x20000 0x1000000>; ++ read-only; ++ }; ++ partition@2 { ++ label = "root"; ++ // 2G ++ reg = <0x1020000 0x80000000>; ++ }; ++}; +\ No newline at end of file +diff -Nur linux-4.1.13.orig/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt linux-rpi/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt +--- linux-4.1.13.orig/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt 2015-11-29 09:42:34.251475279 +0100 +@@ -16,8 +16,8 @@ + + bcm2835_i2s: i2s@7e203000 { + compatible = "brcm,bcm2835-i2s"; +- reg = <0x7e203000 0x20>, +- <0x7e101098 0x02>; ++ reg = <0x7e203000 0x24>, ++ <0x7e101098 0x08>; + + dmas = <&dma 2>, + <&dma 3>; +diff -Nur linux-4.1.13.orig/Documentation/devicetree/bindings/vendor-prefixes.txt linux-rpi/Documentation/devicetree/bindings/vendor-prefixes.txt +--- linux-4.1.13.orig/Documentation/devicetree/bindings/vendor-prefixes.txt 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/Documentation/devicetree/bindings/vendor-prefixes.txt 2015-11-29 09:42:34.263474481 +0100 +@@ -76,6 +76,7 @@ + excito Excito + fcs Fairchild Semiconductor + firefly Firefly ++focaltech FocalTech Systems Co.,Ltd + fsl Freescale Semiconductor + GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc. + gef GE Fanuc Intelligent Platforms Embedded Systems, Inc. +diff -Nur linux-4.1.13.orig/Documentation/video4linux/bcm2835-v4l2.txt linux-rpi/Documentation/video4linux/bcm2835-v4l2.txt +--- linux-4.1.13.orig/Documentation/video4linux/bcm2835-v4l2.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/Documentation/video4linux/bcm2835-v4l2.txt 2015-11-29 09:42:34.479460130 +0100 +@@ -0,0 +1,60 @@ ++ ++BCM2835 (aka Raspberry Pi) V4L2 driver ++====================================== ++ ++1. Copyright ++============ ++ ++Copyright © 2013 Raspberry Pi (Trading) Ltd. ++ ++2. License ++========== ++ ++This program is free software; you can redistribute it and/or modify ++it under the terms of the GNU General Public License as published by ++the Free Software Foundation; either version 2 of the License, or ++(at your option) any later version. ++ ++This program is distributed in the hope that it will be useful, ++but WITHOUT ANY WARRANTY; without even the implied warranty of ++MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++GNU General Public License for more details. ++ ++You should have received a copy of the GNU General Public License ++along with this program; if not, write to the Free Software ++Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ++ ++3. Quick Start ++============== ++ ++You need a version 1.0 or later of v4l2-ctl, available from: ++ git://git.linuxtv.org/v4l-utils.git ++ ++$ sudo modprobe bcm2835-v4l2 ++ ++Turn on the overlay: ++ ++$ v4l2-ctl --overlay=1 ++ ++Turn off the overlay: ++ ++$ v4l2-ctl --overlay=0 ++ ++Set the capture format for video: ++ ++$ v4l2-ctl --set-fmt-video=width=1920,height=1088,pixelformat=4 ++ ++(Note: 1088 not 1080). ++ ++Capture: ++ ++$ v4l2-ctl --stream-mmap=3 --stream-count=100 --stream-to=somefile.h264 ++ ++Stills capture: ++ ++$ v4l2-ctl --set-fmt-video=width=2592,height=1944,pixelformat=3 ++$ v4l2-ctl --stream-mmap=3 --stream-count=1 --stream-to=somefile.jpg ++ ++List of available formats: ++ ++$ v4l2-ctl --list-formats +diff -Nur linux-4.1.13.orig/Documentation/w1/slaves/w1_therm linux-rpi/Documentation/w1/slaves/w1_therm +--- linux-4.1.13.orig/Documentation/w1/slaves/w1_therm 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/Documentation/w1/slaves/w1_therm 2015-11-29 09:42:34.491459333 +0100 +@@ -11,12 +11,14 @@ + Description + ----------- + +-w1_therm provides basic temperature conversion for ds18*20 devices. ++w1_therm provides basic temperature conversion for ds18*20 devices, and the ++ds28ea00 device. + supported family codes: + W1_THERM_DS18S20 0x10 + W1_THERM_DS1822 0x22 + W1_THERM_DS18B20 0x28 + W1_THERM_DS1825 0x3B ++W1_THERM_DS28EA00 0x42 + + Support is provided through the sysfs w1_slave file. Each open and + read sequence will initiate a temperature conversion then provide two +@@ -48,3 +50,10 @@ + maximum current draw of 1.5mA and that a 5k pullup resistor is not + sufficient. The strong pullup is designed to provide the additional + current required. ++ ++The DS28EA00 provides an additional two pins for implementing a sequence ++detection algorithm. This feature allows you to determine the physical ++location of the chip in the 1-wire bus without needing pre-existing ++knowledge of the bus ordering. Support is provided through the sysfs ++w1_seq file. The file will contain a single line with an integer value ++representing the device index in the bus starting at 0. +diff -Nur linux-4.1.13.orig/drivers/char/broadcom/bcm2835-gpiomem.c linux-rpi/drivers/char/broadcom/bcm2835-gpiomem.c +--- linux-4.1.13.orig/drivers/char/broadcom/bcm2835-gpiomem.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/char/broadcom/bcm2835-gpiomem.c 2015-11-29 09:42:36.703312367 +0100 +@@ -0,0 +1,260 @@ ++/** ++ * GPIO memory device driver ++ * ++ * Creates a chardev /dev/gpiomem which will provide user access to ++ * the BCM2835's GPIO registers when it is mmap()'d. ++ * No longer need root for user GPIO access, but without relaxing permissions ++ * on /dev/mem. ++ * ++ * Written by Luke Wren ++ * Copyright (c) 2015, Raspberry Pi (Trading) Ltd. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define DEVICE_NAME "bcm2835-gpiomem" ++#define DRIVER_NAME "gpiomem-bcm2835" ++#define DEVICE_MINOR 0 ++ ++struct bcm2835_gpiomem_instance { ++ unsigned long gpio_regs_phys; ++ struct device *dev; ++}; ++ ++static struct cdev bcm2835_gpiomem_cdev; ++static dev_t bcm2835_gpiomem_devid; ++static struct class *bcm2835_gpiomem_class; ++static struct device *bcm2835_gpiomem_dev; ++static struct bcm2835_gpiomem_instance *inst; ++ ++ ++/**************************************************************************** ++* ++* GPIO mem chardev file ops ++* ++***************************************************************************/ ++ ++static int bcm2835_gpiomem_open(struct inode *inode, struct file *file) ++{ ++ int dev = iminor(inode); ++ int ret = 0; ++ ++ dev_info(inst->dev, "gpiomem device opened."); ++ ++ if (dev != DEVICE_MINOR) { ++ dev_err(inst->dev, "Unknown minor device: %d", dev); ++ ret = -ENXIO; ++ } ++ return ret; ++} ++ ++static int bcm2835_gpiomem_release(struct inode *inode, struct file *file) ++{ ++ int dev = iminor(inode); ++ int ret = 0; ++ ++ if (dev != DEVICE_MINOR) { ++ dev_err(inst->dev, "Unknown minor device %d", dev); ++ ret = -ENXIO; ++ } ++ return ret; ++} ++ ++static const struct vm_operations_struct bcm2835_gpiomem_vm_ops = { ++#ifdef CONFIG_HAVE_IOREMAP_PROT ++ .access = generic_access_phys ++#endif ++}; ++ ++static int bcm2835_gpiomem_mmap(struct file *file, struct vm_area_struct *vma) ++{ ++ /* Ignore what the user says - they're getting the GPIO regs ++ whether they like it or not! */ ++ unsigned long gpio_page = inst->gpio_regs_phys >> PAGE_SHIFT; ++ ++ vma->vm_page_prot = phys_mem_access_prot(file, gpio_page, ++ PAGE_SIZE, ++ vma->vm_page_prot); ++ vma->vm_ops = &bcm2835_gpiomem_vm_ops; ++ if (remap_pfn_range(vma, vma->vm_start, ++ gpio_page, ++ PAGE_SIZE, ++ vma->vm_page_prot)) { ++ return -EAGAIN; ++ } ++ return 0; ++} ++ ++static const struct file_operations ++bcm2835_gpiomem_fops = { ++ .owner = THIS_MODULE, ++ .open = bcm2835_gpiomem_open, ++ .release = bcm2835_gpiomem_release, ++ .mmap = bcm2835_gpiomem_mmap, ++}; ++ ++ ++ /**************************************************************************** ++* ++* Probe and remove functions ++* ++***************************************************************************/ ++ ++ ++static int bcm2835_gpiomem_probe(struct platform_device *pdev) ++{ ++ int err; ++ void *ptr_err; ++ struct device *dev = &pdev->dev; ++ struct resource *ioresource; ++ ++ /* Allocate buffers and instance data */ ++ ++ inst = kzalloc(sizeof(struct bcm2835_gpiomem_instance), GFP_KERNEL); ++ ++ if (!inst) { ++ err = -ENOMEM; ++ goto failed_inst_alloc; ++ } ++ ++ inst->dev = dev; ++ ++ ioresource = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (ioresource) { ++ inst->gpio_regs_phys = ioresource->start; ++ } else { ++ dev_err(inst->dev, "failed to get IO resource"); ++ err = -ENOENT; ++ goto failed_get_resource; ++ } ++ ++ /* Create character device entries */ ++ ++ err = alloc_chrdev_region(&bcm2835_gpiomem_devid, ++ DEVICE_MINOR, 1, DEVICE_NAME); ++ if (err != 0) { ++ dev_err(inst->dev, "unable to allocate device number"); ++ goto failed_alloc_chrdev; ++ } ++ cdev_init(&bcm2835_gpiomem_cdev, &bcm2835_gpiomem_fops); ++ bcm2835_gpiomem_cdev.owner = THIS_MODULE; ++ err = cdev_add(&bcm2835_gpiomem_cdev, bcm2835_gpiomem_devid, 1); ++ if (err != 0) { ++ dev_err(inst->dev, "unable to register device"); ++ goto failed_cdev_add; ++ } ++ ++ /* Create sysfs entries */ ++ ++ bcm2835_gpiomem_class = class_create(THIS_MODULE, DEVICE_NAME); ++ ptr_err = bcm2835_gpiomem_class; ++ if (IS_ERR(ptr_err)) ++ goto failed_class_create; ++ ++ bcm2835_gpiomem_dev = device_create(bcm2835_gpiomem_class, NULL, ++ bcm2835_gpiomem_devid, NULL, ++ "gpiomem"); ++ ptr_err = bcm2835_gpiomem_dev; ++ if (IS_ERR(ptr_err)) ++ goto failed_device_create; ++ ++ dev_info(inst->dev, "Initialised: Registers at 0x%08lx", ++ inst->gpio_regs_phys); ++ ++ return 0; ++ ++failed_device_create: ++ class_destroy(bcm2835_gpiomem_class); ++failed_class_create: ++ cdev_del(&bcm2835_gpiomem_cdev); ++ err = PTR_ERR(ptr_err); ++failed_cdev_add: ++ unregister_chrdev_region(bcm2835_gpiomem_devid, 1); ++failed_alloc_chrdev: ++failed_get_resource: ++ kfree(inst); ++failed_inst_alloc: ++ dev_err(inst->dev, "could not load bcm2835_gpiomem"); ++ return err; ++} ++ ++static int bcm2835_gpiomem_remove(struct platform_device *pdev) ++{ ++ struct device *dev = inst->dev; ++ ++ kfree(inst); ++ device_destroy(bcm2835_gpiomem_class, bcm2835_gpiomem_devid); ++ class_destroy(bcm2835_gpiomem_class); ++ cdev_del(&bcm2835_gpiomem_cdev); ++ unregister_chrdev_region(bcm2835_gpiomem_devid, 1); ++ ++ dev_info(dev, "GPIO mem driver removed - OK"); ++ return 0; ++} ++ ++ /**************************************************************************** ++* ++* Register the driver with device tree ++* ++***************************************************************************/ ++ ++static const struct of_device_id bcm2835_gpiomem_of_match[] = { ++ {.compatible = "brcm,bcm2835-gpiomem",}, ++ { /* sentinel */ }, ++}; ++ ++MODULE_DEVICE_TABLE(of, bcm2835_gpiomem_of_match); ++ ++static struct platform_driver bcm2835_gpiomem_driver = { ++ .probe = bcm2835_gpiomem_probe, ++ .remove = bcm2835_gpiomem_remove, ++ .driver = { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = bcm2835_gpiomem_of_match, ++ }, ++}; ++ ++module_platform_driver(bcm2835_gpiomem_driver); ++ ++MODULE_ALIAS("platform:gpiomem-bcm2835"); ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("gpiomem driver for accessing GPIO from userspace"); ++MODULE_AUTHOR("Luke Wren "); +diff -Nur linux-4.1.13.orig/drivers/char/broadcom/bcm2835_smi_dev.c linux-rpi/drivers/char/broadcom/bcm2835_smi_dev.c +--- linux-4.1.13.orig/drivers/char/broadcom/bcm2835_smi_dev.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/char/broadcom/bcm2835_smi_dev.c 2015-11-29 09:42:36.703312367 +0100 +@@ -0,0 +1,402 @@ ++/** ++ * Character device driver for Broadcom Secondary Memory Interface ++ * ++ * Written by Luke Wren ++ * Copyright (c) 2015, Raspberry Pi (Trading) Ltd. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define DEVICE_NAME "bcm2835-smi-dev" ++#define DRIVER_NAME "smi-dev-bcm2835" ++#define DEVICE_MINOR 0 ++ ++static struct cdev bcm2835_smi_cdev; ++static dev_t bcm2835_smi_devid; ++static struct class *bcm2835_smi_class; ++static struct device *bcm2835_smi_dev; ++ ++struct bcm2835_smi_dev_instance { ++ struct device *dev; ++}; ++ ++static struct bcm2835_smi_instance *smi_inst; ++static struct bcm2835_smi_dev_instance *inst; ++ ++static const char *const ioctl_names[] = { ++ "READ_SETTINGS", ++ "WRITE_SETTINGS", ++ "ADDRESS" ++}; ++ ++/**************************************************************************** ++* ++* SMI chardev file ops ++* ++***************************************************************************/ ++static long ++bcm2835_smi_ioctl(struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ long ret = 0; ++ ++ dev_info(inst->dev, "serving ioctl..."); ++ ++ switch (cmd) { ++ case BCM2835_SMI_IOC_GET_SETTINGS:{ ++ struct smi_settings *settings; ++ ++ dev_info(inst->dev, "Reading SMI settings to user."); ++ settings = bcm2835_smi_get_settings_from_regs(smi_inst); ++ if (copy_to_user((void *)arg, settings, ++ sizeof(struct smi_settings))) ++ dev_err(inst->dev, "settings copy failed."); ++ break; ++ } ++ case BCM2835_SMI_IOC_WRITE_SETTINGS:{ ++ struct smi_settings *settings; ++ ++ dev_info(inst->dev, "Setting user's SMI settings."); ++ settings = bcm2835_smi_get_settings_from_regs(smi_inst); ++ if (copy_from_user(settings, (void *)arg, ++ sizeof(struct smi_settings))) ++ dev_err(inst->dev, "settings copy failed."); ++ else ++ bcm2835_smi_set_regs_from_settings(smi_inst); ++ break; ++ } ++ case BCM2835_SMI_IOC_ADDRESS: ++ dev_info(inst->dev, "SMI address set: 0x%02x", (int)arg); ++ bcm2835_smi_set_address(smi_inst, arg); ++ break; ++ default: ++ dev_err(inst->dev, "invalid ioctl cmd: %d", cmd); ++ ret = -ENOTTY; ++ break; ++ } ++ ++ return ret; ++} ++ ++static int bcm2835_smi_open(struct inode *inode, struct file *file) ++{ ++ int dev = iminor(inode); ++ ++ dev_dbg(inst->dev, "SMI device opened."); ++ ++ if (dev != DEVICE_MINOR) { ++ dev_err(inst->dev, ++ "bcm2835_smi_release: Unknown minor device: %d", ++ dev); ++ return -ENXIO; ++ } ++ ++ return 0; ++} ++ ++static int bcm2835_smi_release(struct inode *inode, struct file *file) ++{ ++ int dev = iminor(inode); ++ ++ if (dev != DEVICE_MINOR) { ++ dev_err(inst->dev, ++ "bcm2835_smi_release: Unknown minor device %d", dev); ++ return -ENXIO; ++ } ++ ++ return 0; ++} ++ ++static ssize_t dma_bounce_user( ++ enum dma_transfer_direction dma_dir, ++ char __user *user_ptr, ++ size_t count, ++ struct bcm2835_smi_bounce_info *bounce) ++{ ++ int chunk_size; ++ int chunk_no = 0; ++ int count_left = count; ++ ++ while (count_left) { ++ int rv; ++ void *buf; ++ ++ /* Wait for current chunk to complete: */ ++ if (down_timeout(&bounce->callback_sem, ++ msecs_to_jiffies(1000))) { ++ dev_err(inst->dev, "DMA bounce timed out"); ++ count -= (count_left); ++ break; ++ } ++ ++ if (bounce->callback_sem.count >= DMA_BOUNCE_BUFFER_COUNT - 1) ++ dev_err(inst->dev, "WARNING: Ring buffer overflow"); ++ chunk_size = count_left > DMA_BOUNCE_BUFFER_SIZE ? ++ DMA_BOUNCE_BUFFER_SIZE : count_left; ++ buf = bounce->buffer[chunk_no % DMA_BOUNCE_BUFFER_COUNT]; ++ if (dma_dir == DMA_DEV_TO_MEM) ++ rv = copy_to_user(user_ptr, buf, chunk_size); ++ else ++ rv = copy_from_user(buf, user_ptr, chunk_size); ++ if (rv) ++ dev_err(inst->dev, "copy_*_user() failed!: %d", rv); ++ user_ptr += chunk_size; ++ count_left -= chunk_size; ++ chunk_no++; ++ } ++ return count; ++} ++ ++static ssize_t ++bcm2835_read_file(struct file *f, char __user *user_ptr, ++ size_t count, loff_t *offs) ++{ ++ int odd_bytes; ++ ++ dev_dbg(inst->dev, "User reading %d bytes from SMI.", count); ++ /* We don't want to DMA a number of bytes % 4 != 0 (32 bit FIFO) */ ++ if (count > DMA_THRESHOLD_BYTES) ++ odd_bytes = count & 0x3; ++ else ++ odd_bytes = count; ++ count -= odd_bytes; ++ if (count) { ++ struct bcm2835_smi_bounce_info *bounce; ++ ++ count = bcm2835_smi_user_dma(smi_inst, ++ DMA_DEV_TO_MEM, user_ptr, count, ++ &bounce); ++ if (count) ++ count = dma_bounce_user(DMA_DEV_TO_MEM, user_ptr, ++ count, bounce); ++ } ++ if (odd_bytes) { ++ /* Read from FIFO directly if not using DMA */ ++ uint8_t buf[DMA_THRESHOLD_BYTES]; ++ ++ bcm2835_smi_read_buf(smi_inst, buf, odd_bytes); ++ if (copy_to_user(user_ptr, buf, odd_bytes)) ++ dev_err(inst->dev, "copy_to_user() failed."); ++ count += odd_bytes; ++ ++ } ++ return count; ++} ++ ++static ssize_t ++bcm2835_write_file(struct file *f, const char __user *user_ptr, ++ size_t count, loff_t *offs) ++{ ++ int odd_bytes; ++ ++ dev_dbg(inst->dev, "User writing %d bytes to SMI.", count); ++ if (count > DMA_THRESHOLD_BYTES) ++ odd_bytes = count & 0x3; ++ else ++ odd_bytes = count; ++ count -= odd_bytes; ++ if (count) { ++ struct bcm2835_smi_bounce_info *bounce; ++ ++ count = bcm2835_smi_user_dma(smi_inst, ++ DMA_MEM_TO_DEV, (char __user *)user_ptr, count, ++ &bounce); ++ if (count) ++ count = dma_bounce_user(DMA_MEM_TO_DEV, ++ (char __user *)user_ptr, ++ count, bounce); ++ } ++ if (odd_bytes) { ++ uint8_t buf[DMA_THRESHOLD_BYTES]; ++ ++ if (copy_from_user(buf, user_ptr, odd_bytes)) ++ dev_err(inst->dev, "copy_from_user() failed."); ++ else ++ bcm2835_smi_write_buf(smi_inst, buf, odd_bytes); ++ count += odd_bytes; ++ } ++ return count; ++} ++ ++static const struct file_operations ++bcm2835_smi_fops = { ++ .owner = THIS_MODULE, ++ .unlocked_ioctl = bcm2835_smi_ioctl, ++ .open = bcm2835_smi_open, ++ .release = bcm2835_smi_release, ++ .read = bcm2835_read_file, ++ .write = bcm2835_write_file, ++}; ++ ++ ++/**************************************************************************** ++* ++* bcm2835_smi_probe - called when the driver is loaded. ++* ++***************************************************************************/ ++ ++static int bcm2835_smi_dev_probe(struct platform_device *pdev) ++{ ++ int err; ++ void *ptr_err; ++ struct device *dev = &pdev->dev; ++ struct device_node *node = dev->of_node, *smi_node; ++ ++ if (!node) { ++ dev_err(dev, "No device tree node supplied!"); ++ return -EINVAL; ++ } ++ ++ smi_node = of_parse_phandle(node, "smi_handle", 0); ++ ++ if (!smi_node) { ++ dev_err(dev, "No such property: smi_handle"); ++ return -ENXIO; ++ } ++ ++ smi_inst = bcm2835_smi_get(smi_node); ++ ++ if (!smi_inst) ++ return -EPROBE_DEFER; ++ ++ /* Allocate buffers and instance data */ ++ ++ inst = devm_kzalloc(dev, sizeof(*inst), GFP_KERNEL); ++ ++ if (!inst) ++ return -ENOMEM; ++ ++ inst->dev = dev; ++ ++ /* Create character device entries */ ++ ++ err = alloc_chrdev_region(&bcm2835_smi_devid, ++ DEVICE_MINOR, 1, DEVICE_NAME); ++ if (err != 0) { ++ dev_err(inst->dev, "unable to allocate device number"); ++ return -ENOMEM; ++ } ++ cdev_init(&bcm2835_smi_cdev, &bcm2835_smi_fops); ++ bcm2835_smi_cdev.owner = THIS_MODULE; ++ err = cdev_add(&bcm2835_smi_cdev, bcm2835_smi_devid, 1); ++ if (err != 0) { ++ dev_err(inst->dev, "unable to register device"); ++ err = -ENOMEM; ++ goto failed_cdev_add; ++ } ++ ++ /* Create sysfs entries */ ++ ++ bcm2835_smi_class = class_create(THIS_MODULE, DEVICE_NAME); ++ ptr_err = bcm2835_smi_class; ++ if (IS_ERR(ptr_err)) ++ goto failed_class_create; ++ ++ bcm2835_smi_dev = device_create(bcm2835_smi_class, NULL, ++ bcm2835_smi_devid, NULL, ++ "smi"); ++ ptr_err = bcm2835_smi_dev; ++ if (IS_ERR(ptr_err)) ++ goto failed_device_create; ++ ++ dev_info(inst->dev, "initialised"); ++ ++ return 0; ++ ++failed_device_create: ++ class_destroy(bcm2835_smi_class); ++failed_class_create: ++ cdev_del(&bcm2835_smi_cdev); ++ err = PTR_ERR(ptr_err); ++failed_cdev_add: ++ unregister_chrdev_region(bcm2835_smi_devid, 1); ++ dev_err(dev, "could not load bcm2835_smi_dev"); ++ return err; ++} ++ ++/**************************************************************************** ++* ++* bcm2835_smi_remove - called when the driver is unloaded. ++* ++***************************************************************************/ ++ ++static int bcm2835_smi_dev_remove(struct platform_device *pdev) ++{ ++ device_destroy(bcm2835_smi_class, bcm2835_smi_devid); ++ class_destroy(bcm2835_smi_class); ++ cdev_del(&bcm2835_smi_cdev); ++ unregister_chrdev_region(bcm2835_smi_devid, 1); ++ ++ dev_info(inst->dev, "SMI character dev removed - OK"); ++ return 0; ++} ++ ++/**************************************************************************** ++* ++* Register the driver with device tree ++* ++***************************************************************************/ ++ ++static const struct of_device_id bcm2835_smi_dev_of_match[] = { ++ {.compatible = "brcm,bcm2835-smi-dev",}, ++ { /* sentinel */ }, ++}; ++ ++MODULE_DEVICE_TABLE(of, bcm2835_smi_dev_of_match); ++ ++static struct platform_driver bcm2835_smi_dev_driver = { ++ .probe = bcm2835_smi_dev_probe, ++ .remove = bcm2835_smi_dev_remove, ++ .driver = { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = bcm2835_smi_dev_of_match, ++ }, ++}; ++ ++module_platform_driver(bcm2835_smi_dev_driver); ++ ++MODULE_ALIAS("platform:smi-dev-bcm2835"); ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION( ++ "Character device driver for BCM2835's secondary memory interface"); ++MODULE_AUTHOR("Luke Wren "); +diff -Nur linux-4.1.13.orig/drivers/char/broadcom/Kconfig linux-rpi/drivers/char/broadcom/Kconfig +--- linux-4.1.13.orig/drivers/char/broadcom/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/char/broadcom/Kconfig 2015-11-29 09:42:36.703312367 +0100 +@@ -0,0 +1,57 @@ ++# ++# Broadcom char driver config ++# ++ ++menuconfig BRCM_CHAR_DRIVERS ++ bool "Broadcom Char Drivers" ++ help ++ Broadcom's char drivers ++ ++if BRCM_CHAR_DRIVERS ++ ++config BCM_VC_CMA ++ bool "Videocore CMA" ++ depends on CMA && BCM2708_VCHIQ ++ default n ++ help ++ Helper for videocore CMA access. ++ ++config BCM2708_VCMEM ++ bool "Videocore Memory" ++ default y ++ help ++ Helper for videocore memory access and total size allocation. ++ ++config BCM_VCIO ++ tristate "Mailbox userspace access" ++ depends on BCM2835_MBOX ++ help ++ Gives access to the mailbox property channel from userspace. ++ ++endif ++ ++config BCM_VC_SM ++ bool "VMCS Shared Memory" ++ depends on BCM2708_VCHIQ ++ select BCM2708_VCMEM ++ default n ++ help ++ Support for the VC shared memory on the Broadcom reference ++ design. Uses the VCHIQ stack. ++ ++config BCM2835_DEVGPIOMEM ++ tristate "/dev/gpiomem rootless GPIO access via mmap() on the BCM2835" ++ default m ++ help ++ Provides users with root-free access to the GPIO registers ++ on the 2835. Calling mmap(/dev/gpiomem) will map the GPIO ++ register page to the user's pointer. ++ ++config BCM2835_SMI_DEV ++ tristate "Character device driver for BCM2835 Secondary Memory Interface" ++ depends on (MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835) && BCM2835_SMI ++ default m ++ help ++ This driver provides a character device interface (ioctl + read/write) to ++ Broadcom's Secondary Memory interface. The low-level functionality is provided ++ by the SMI driver itself. +diff -Nur linux-4.1.13.orig/drivers/char/broadcom/Makefile linux-rpi/drivers/char/broadcom/Makefile +--- linux-4.1.13.orig/drivers/char/broadcom/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/char/broadcom/Makefile 2015-11-29 09:42:36.703312367 +0100 +@@ -0,0 +1,7 @@ ++obj-$(CONFIG_BCM_VC_CMA) += vc_cma/ ++obj-$(CONFIG_BCM2708_VCMEM) += vc_mem.o ++obj-$(CONFIG_BCM_VCIO) += vcio.o ++obj-$(CONFIG_BCM_VC_SM) += vc_sm/ ++ ++obj-$(CONFIG_BCM2835_DEVGPIOMEM)+= bcm2835-gpiomem.o ++obj-$(CONFIG_BCM2835_SMI_DEV) += bcm2835_smi_dev.o +diff -Nur linux-4.1.13.orig/drivers/char/broadcom/vc_cma/Makefile linux-rpi/drivers/char/broadcom/vc_cma/Makefile +--- linux-4.1.13.orig/drivers/char/broadcom/vc_cma/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/char/broadcom/vc_cma/Makefile 2015-11-29 09:42:36.703312367 +0100 +@@ -0,0 +1,14 @@ ++ccflags-y += -Wall -Wstrict-prototypes -Wno-trigraphs ++ccflags-y += -Werror ++ccflags-y += -Iinclude/linux/broadcom ++ccflags-y += -Idrivers/misc/vc04_services ++ccflags-y += -Idrivers/misc/vc04_services/interface/vchi ++ccflags-y += -Idrivers/misc/vc04_services/interface/vchiq_arm ++ ++ccflags-y += -D__KERNEL__ ++ccflags-y += -D__linux__ ++ccflags-y += -Werror ++ ++obj-$(CONFIG_BCM_VC_CMA) += vc-cma.o ++ ++vc-cma-objs := vc_cma.o +diff -Nur linux-4.1.13.orig/drivers/char/broadcom/vc_cma/vc_cma.c linux-rpi/drivers/char/broadcom/vc_cma/vc_cma.c +--- linux-4.1.13.orig/drivers/char/broadcom/vc_cma/vc_cma.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/char/broadcom/vc_cma/vc_cma.c 2015-11-29 09:42:36.703312367 +0100 +@@ -0,0 +1,1193 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "vc_cma.h" ++ ++#include "vchiq_util.h" ++#include "vchiq_connected.h" ++//#include "debug_sym.h" ++//#include "vc_mem.h" ++ ++#define DRIVER_NAME "vc-cma" ++ ++#define LOG_DBG(fmt, ...) \ ++ if (vc_cma_debug) \ ++ printk(KERN_INFO fmt "\n", ##__VA_ARGS__) ++#define LOG_INFO(fmt, ...) \ ++ printk(KERN_INFO fmt "\n", ##__VA_ARGS__) ++#define LOG_ERR(fmt, ...) \ ++ printk(KERN_ERR fmt "\n", ##__VA_ARGS__) ++ ++#define VC_CMA_FOURCC VCHIQ_MAKE_FOURCC('C', 'M', 'A', ' ') ++#define VC_CMA_VERSION 2 ++ ++#define VC_CMA_CHUNK_ORDER 6 /* 256K */ ++#define VC_CMA_CHUNK_SIZE (4096 << VC_CMA_CHUNK_ORDER) ++#define VC_CMA_MAX_PARAMS_PER_MSG \ ++ ((VCHIQ_MAX_MSG_SIZE - sizeof(unsigned short))/sizeof(unsigned short)) ++#define VC_CMA_RESERVE_COUNT_MAX 16 ++ ++#define PAGES_PER_CHUNK (VC_CMA_CHUNK_SIZE / PAGE_SIZE) ++ ++#define VCADDR_TO_PHYSADDR(vcaddr) (mm_vc_mem_phys_addr + vcaddr) ++ ++#define loud_error(...) \ ++ LOG_ERR("===== " __VA_ARGS__) ++ ++enum { ++ VC_CMA_MSG_QUIT, ++ VC_CMA_MSG_OPEN, ++ VC_CMA_MSG_TICK, ++ VC_CMA_MSG_ALLOC, /* chunk count */ ++ VC_CMA_MSG_FREE, /* chunk, chunk, ... */ ++ VC_CMA_MSG_ALLOCATED, /* chunk, chunk, ... */ ++ VC_CMA_MSG_REQUEST_ALLOC, /* chunk count */ ++ VC_CMA_MSG_REQUEST_FREE, /* chunk count */ ++ VC_CMA_MSG_RESERVE, /* bytes lo, bytes hi */ ++ VC_CMA_MSG_UPDATE_RESERVE, ++ VC_CMA_MSG_MAX ++}; ++ ++struct cma_msg { ++ unsigned short type; ++ unsigned short params[VC_CMA_MAX_PARAMS_PER_MSG]; ++}; ++ ++struct vc_cma_reserve_user { ++ unsigned int pid; ++ unsigned int reserve; ++}; ++ ++/* Device (/dev) related variables */ ++static dev_t vc_cma_devnum; ++static struct class *vc_cma_class; ++static struct cdev vc_cma_cdev; ++static int vc_cma_inited; ++static int vc_cma_debug; ++ ++/* Proc entry */ ++static struct proc_dir_entry *vc_cma_proc_entry; ++ ++phys_addr_t vc_cma_base; ++struct page *vc_cma_base_page; ++unsigned int vc_cma_size; ++EXPORT_SYMBOL(vc_cma_size); ++unsigned int vc_cma_initial; ++unsigned int vc_cma_chunks; ++unsigned int vc_cma_chunks_used; ++unsigned int vc_cma_chunks_reserved; ++ ++ ++void *vc_cma_dma_alloc; ++unsigned int vc_cma_dma_size; ++ ++static int in_loud_error; ++ ++unsigned int vc_cma_reserve_total; ++unsigned int vc_cma_reserve_count; ++struct vc_cma_reserve_user vc_cma_reserve_users[VC_CMA_RESERVE_COUNT_MAX]; ++static DEFINE_SEMAPHORE(vc_cma_reserve_mutex); ++static DEFINE_SEMAPHORE(vc_cma_worker_queue_push_mutex); ++ ++static u64 vc_cma_dma_mask = DMA_BIT_MASK(32); ++static struct platform_device vc_cma_device = { ++ .name = "vc-cma", ++ .id = 0, ++ .dev = { ++ .dma_mask = &vc_cma_dma_mask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ }, ++}; ++ ++static VCHIQ_INSTANCE_T cma_instance; ++static VCHIQ_SERVICE_HANDLE_T cma_service; ++static VCHIU_QUEUE_T cma_msg_queue; ++static struct task_struct *cma_worker; ++ ++static int vc_cma_set_reserve(unsigned int reserve, unsigned int pid); ++static int vc_cma_alloc_chunks(int num_chunks, struct cma_msg *reply); ++static VCHIQ_STATUS_T cma_service_callback(VCHIQ_REASON_T reason, ++ VCHIQ_HEADER_T * header, ++ VCHIQ_SERVICE_HANDLE_T service, ++ void *bulk_userdata); ++static void send_vc_msg(unsigned short type, ++ unsigned short param1, unsigned short param2); ++static bool send_worker_msg(VCHIQ_HEADER_T * msg); ++ ++static int early_vc_cma_mem(char *p) ++{ ++ unsigned int new_size; ++ printk(KERN_NOTICE "early_vc_cma_mem(%s)", p); ++ vc_cma_size = memparse(p, &p); ++ vc_cma_initial = vc_cma_size; ++ if (*p == '/') ++ vc_cma_size = memparse(p + 1, &p); ++ if (*p == '@') ++ vc_cma_base = memparse(p + 1, &p); ++ ++ new_size = (vc_cma_size - ((-vc_cma_base) & (VC_CMA_CHUNK_SIZE - 1))) ++ & ~(VC_CMA_CHUNK_SIZE - 1); ++ if (new_size > vc_cma_size) ++ vc_cma_size = 0; ++ vc_cma_initial = (vc_cma_initial + VC_CMA_CHUNK_SIZE - 1) ++ & ~(VC_CMA_CHUNK_SIZE - 1); ++ if (vc_cma_initial > vc_cma_size) ++ vc_cma_initial = vc_cma_size; ++ vc_cma_base = (vc_cma_base + VC_CMA_CHUNK_SIZE - 1) ++ & ~(VC_CMA_CHUNK_SIZE - 1); ++ ++ printk(KERN_NOTICE " -> initial %x, size %x, base %x", vc_cma_initial, ++ vc_cma_size, (unsigned int)vc_cma_base); ++ ++ return 0; ++} ++ ++early_param("vc-cma-mem", early_vc_cma_mem); ++ ++void vc_cma_early_init(void) ++{ ++ LOG_DBG("vc_cma_early_init - vc_cma_chunks = %d", vc_cma_chunks); ++ if (vc_cma_size) { ++ int rc = platform_device_register(&vc_cma_device); ++ LOG_DBG("platform_device_register -> %d", rc); ++ } ++} ++ ++void vc_cma_reserve(void) ++{ ++ /* if vc_cma_size is set, then declare vc CMA area of the same ++ * size from the end of memory ++ */ ++ if (vc_cma_size) { ++ if (dma_declare_contiguous(&vc_cma_device.dev, vc_cma_size, ++ vc_cma_base, 0) == 0) { ++ if (!dev_get_cma_area(NULL)) { ++ /* There is no default CMA area - make this ++ the default */ ++ struct cma *vc_cma_area = dev_get_cma_area( ++ &vc_cma_device.dev); ++ dma_contiguous_set_default(vc_cma_area); ++ LOG_INFO("vc_cma_reserve - using vc_cma as " ++ "the default contiguous DMA area"); ++ } ++ } else { ++ LOG_ERR("vc_cma: dma_declare_contiguous(%x,%x) failed", ++ vc_cma_size, (unsigned int)vc_cma_base); ++ vc_cma_size = 0; ++ } ++ } ++ vc_cma_chunks = vc_cma_size / VC_CMA_CHUNK_SIZE; ++} ++ ++/**************************************************************************** ++* ++* vc_cma_open ++* ++***************************************************************************/ ++ ++static int vc_cma_open(struct inode *inode, struct file *file) ++{ ++ (void)inode; ++ (void)file; ++ ++ return 0; ++} ++ ++/**************************************************************************** ++* ++* vc_cma_release ++* ++***************************************************************************/ ++ ++static int vc_cma_release(struct inode *inode, struct file *file) ++{ ++ (void)inode; ++ (void)file; ++ ++ vc_cma_set_reserve(0, current->tgid); ++ ++ return 0; ++} ++ ++/**************************************************************************** ++* ++* vc_cma_ioctl ++* ++***************************************************************************/ ++ ++static long vc_cma_ioctl(struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ int rc = 0; ++ ++ (void)cmd; ++ (void)arg; ++ ++ switch (cmd) { ++ case VC_CMA_IOC_RESERVE: ++ rc = vc_cma_set_reserve((unsigned int)arg, current->tgid); ++ if (rc >= 0) ++ rc = 0; ++ break; ++ default: ++ LOG_ERR("vc-cma: Unknown ioctl %x", cmd); ++ return -ENOTTY; ++ } ++ ++ return rc; ++} ++ ++/**************************************************************************** ++* ++* File Operations for the driver. ++* ++***************************************************************************/ ++ ++static const struct file_operations vc_cma_fops = { ++ .owner = THIS_MODULE, ++ .open = vc_cma_open, ++ .release = vc_cma_release, ++ .unlocked_ioctl = vc_cma_ioctl, ++}; ++ ++/**************************************************************************** ++* ++* vc_cma_proc_open ++* ++***************************************************************************/ ++ ++static int vc_cma_show_info(struct seq_file *m, void *v) ++{ ++ int i; ++ ++ seq_printf(m, "Videocore CMA:\n"); ++ seq_printf(m, " Base : %08x\n", (unsigned int)vc_cma_base); ++ seq_printf(m, " Length : %08x\n", vc_cma_size); ++ seq_printf(m, " Initial : %08x\n", vc_cma_initial); ++ seq_printf(m, " Chunk size : %08x\n", VC_CMA_CHUNK_SIZE); ++ seq_printf(m, " Chunks : %4d (%d bytes)\n", ++ (int)vc_cma_chunks, ++ (int)(vc_cma_chunks * VC_CMA_CHUNK_SIZE)); ++ seq_printf(m, " Used : %4d (%d bytes)\n", ++ (int)vc_cma_chunks_used, ++ (int)(vc_cma_chunks_used * VC_CMA_CHUNK_SIZE)); ++ seq_printf(m, " Reserved : %4d (%d bytes)\n", ++ (unsigned int)vc_cma_chunks_reserved, ++ (int)(vc_cma_chunks_reserved * VC_CMA_CHUNK_SIZE)); ++ ++ for (i = 0; i < vc_cma_reserve_count; i++) { ++ struct vc_cma_reserve_user *user = &vc_cma_reserve_users[i]; ++ seq_printf(m, " PID %5d: %d bytes\n", user->pid, ++ user->reserve); ++ } ++ seq_printf(m, " dma_alloc : %p (%d pages)\n", ++ vc_cma_dma_alloc ? page_address(vc_cma_dma_alloc) : 0, ++ vc_cma_dma_size); ++ ++ seq_printf(m, "\n"); ++ ++ return 0; ++} ++ ++static int vc_cma_proc_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, vc_cma_show_info, NULL); ++} ++ ++/**************************************************************************** ++* ++* vc_cma_proc_write ++* ++***************************************************************************/ ++ ++static int vc_cma_proc_write(struct file *file, ++ const char __user *buffer, ++ size_t size, loff_t *ppos) ++{ ++ int rc = -EFAULT; ++ char input_str[20]; ++ ++ memset(input_str, 0, sizeof(input_str)); ++ ++ if (size > sizeof(input_str)) { ++ LOG_ERR("%s: input string length too long", __func__); ++ goto out; ++ } ++ ++ if (copy_from_user(input_str, buffer, size - 1)) { ++ LOG_ERR("%s: failed to get input string", __func__); ++ goto out; ++ } ++#define ALLOC_STR "alloc" ++#define FREE_STR "free" ++#define DEBUG_STR "debug" ++#define RESERVE_STR "reserve" ++#define DMA_ALLOC_STR "dma_alloc" ++#define DMA_FREE_STR "dma_free" ++ if (strncmp(input_str, ALLOC_STR, strlen(ALLOC_STR)) == 0) { ++ int alloc_size; ++ char *p = input_str + strlen(ALLOC_STR); ++ ++ while (*p == ' ') ++ p++; ++ alloc_size = memparse(p, NULL); ++ LOG_INFO("/proc/vc-cma: alloc %d", alloc_size); ++ if (alloc_size) ++ send_vc_msg(VC_CMA_MSG_REQUEST_FREE, ++ alloc_size / VC_CMA_CHUNK_SIZE, 0); ++ else ++ LOG_ERR("invalid size '%s'", p); ++ rc = size; ++ } else if (strncmp(input_str, FREE_STR, strlen(FREE_STR)) == 0) { ++ int alloc_size; ++ char *p = input_str + strlen(FREE_STR); ++ ++ while (*p == ' ') ++ p++; ++ alloc_size = memparse(p, NULL); ++ LOG_INFO("/proc/vc-cma: free %d", alloc_size); ++ if (alloc_size) ++ send_vc_msg(VC_CMA_MSG_REQUEST_ALLOC, ++ alloc_size / VC_CMA_CHUNK_SIZE, 0); ++ else ++ LOG_ERR("invalid size '%s'", p); ++ rc = size; ++ } else if (strncmp(input_str, DEBUG_STR, strlen(DEBUG_STR)) == 0) { ++ char *p = input_str + strlen(DEBUG_STR); ++ while (*p == ' ') ++ p++; ++ if ((strcmp(p, "on") == 0) || (strcmp(p, "1") == 0)) ++ vc_cma_debug = 1; ++ else if ((strcmp(p, "off") == 0) || (strcmp(p, "0") == 0)) ++ vc_cma_debug = 0; ++ LOG_INFO("/proc/vc-cma: debug %s", vc_cma_debug ? "on" : "off"); ++ rc = size; ++ } else if (strncmp(input_str, RESERVE_STR, strlen(RESERVE_STR)) == 0) { ++ int alloc_size; ++ int reserved; ++ char *p = input_str + strlen(RESERVE_STR); ++ while (*p == ' ') ++ p++; ++ alloc_size = memparse(p, NULL); ++ ++ reserved = vc_cma_set_reserve(alloc_size, current->tgid); ++ rc = (reserved >= 0) ? size : reserved; ++ } else if (strncmp(input_str, DMA_ALLOC_STR, strlen(DMA_ALLOC_STR)) == 0) { ++ int alloc_size; ++ char *p = input_str + strlen(DMA_ALLOC_STR); ++ while (*p == ' ') ++ p++; ++ alloc_size = memparse(p, NULL); ++ ++ if (vc_cma_dma_alloc) { ++ dma_release_from_contiguous(NULL, vc_cma_dma_alloc, ++ vc_cma_dma_size); ++ vc_cma_dma_alloc = NULL; ++ vc_cma_dma_size = 0; ++ } ++ vc_cma_dma_alloc = dma_alloc_from_contiguous(NULL, alloc_size, 0); ++ vc_cma_dma_size = (vc_cma_dma_alloc ? alloc_size : 0); ++ if (vc_cma_dma_alloc) ++ LOG_INFO("dma_alloc(%d pages) -> %p", alloc_size, page_address(vc_cma_dma_alloc)); ++ else ++ LOG_ERR("dma_alloc(%d pages) failed", alloc_size); ++ rc = size; ++ } else if (strncmp(input_str, DMA_FREE_STR, strlen(DMA_FREE_STR)) == 0) { ++ if (vc_cma_dma_alloc) { ++ dma_release_from_contiguous(NULL, vc_cma_dma_alloc, ++ vc_cma_dma_size); ++ vc_cma_dma_alloc = NULL; ++ vc_cma_dma_size = 0; ++ } ++ rc = size; ++ } ++ ++out: ++ return rc; ++} ++ ++/**************************************************************************** ++* ++* File Operations for /proc interface. ++* ++***************************************************************************/ ++ ++static const struct file_operations vc_cma_proc_fops = { ++ .open = vc_cma_proc_open, ++ .read = seq_read, ++ .write = vc_cma_proc_write, ++ .llseek = seq_lseek, ++ .release = single_release ++}; ++ ++static int vc_cma_set_reserve(unsigned int reserve, unsigned int pid) ++{ ++ struct vc_cma_reserve_user *user = NULL; ++ int delta = 0; ++ int i; ++ ++ if (down_interruptible(&vc_cma_reserve_mutex)) ++ return -ERESTARTSYS; ++ ++ for (i = 0; i < vc_cma_reserve_count; i++) { ++ if (pid == vc_cma_reserve_users[i].pid) { ++ user = &vc_cma_reserve_users[i]; ++ delta = reserve - user->reserve; ++ if (reserve) ++ user->reserve = reserve; ++ else { ++ /* Remove this entry by copying downwards */ ++ while ((i + 1) < vc_cma_reserve_count) { ++ user[0].pid = user[1].pid; ++ user[0].reserve = user[1].reserve; ++ user++; ++ i++; ++ } ++ vc_cma_reserve_count--; ++ user = NULL; ++ } ++ break; ++ } ++ } ++ ++ if (reserve && !user) { ++ if (vc_cma_reserve_count == VC_CMA_RESERVE_COUNT_MAX) { ++ LOG_ERR("vc-cma: Too many reservations - " ++ "increase CMA_RESERVE_COUNT_MAX"); ++ up(&vc_cma_reserve_mutex); ++ return -EBUSY; ++ } ++ user = &vc_cma_reserve_users[vc_cma_reserve_count]; ++ user->pid = pid; ++ user->reserve = reserve; ++ delta = reserve; ++ vc_cma_reserve_count++; ++ } ++ ++ vc_cma_reserve_total += delta; ++ ++ send_vc_msg(VC_CMA_MSG_RESERVE, ++ vc_cma_reserve_total & 0xffff, vc_cma_reserve_total >> 16); ++ ++ send_worker_msg((VCHIQ_HEADER_T *) VC_CMA_MSG_UPDATE_RESERVE); ++ ++ LOG_DBG("/proc/vc-cma: reserve %d (PID %d) - total %u", ++ reserve, pid, vc_cma_reserve_total); ++ ++ up(&vc_cma_reserve_mutex); ++ ++ return vc_cma_reserve_total; ++} ++ ++static VCHIQ_STATUS_T cma_service_callback(VCHIQ_REASON_T reason, ++ VCHIQ_HEADER_T * header, ++ VCHIQ_SERVICE_HANDLE_T service, ++ void *bulk_userdata) ++{ ++ switch (reason) { ++ case VCHIQ_MESSAGE_AVAILABLE: ++ if (!send_worker_msg(header)) ++ return VCHIQ_RETRY; ++ break; ++ case VCHIQ_SERVICE_CLOSED: ++ LOG_DBG("CMA service closed"); ++ break; ++ default: ++ LOG_ERR("Unexpected CMA callback reason %d", reason); ++ break; ++ } ++ return VCHIQ_SUCCESS; ++} ++ ++static void send_vc_msg(unsigned short type, ++ unsigned short param1, unsigned short param2) ++{ ++ unsigned short msg[] = { type, param1, param2 }; ++ VCHIQ_ELEMENT_T elem = { &msg, sizeof(msg) }; ++ VCHIQ_STATUS_T ret; ++ vchiq_use_service(cma_service); ++ ret = vchiq_queue_message(cma_service, &elem, 1); ++ vchiq_release_service(cma_service); ++ if (ret != VCHIQ_SUCCESS) ++ LOG_ERR("vchiq_queue_message returned %x", ret); ++} ++ ++static bool send_worker_msg(VCHIQ_HEADER_T * msg) ++{ ++ if (down_interruptible(&vc_cma_worker_queue_push_mutex)) ++ return false; ++ vchiu_queue_push(&cma_msg_queue, msg); ++ up(&vc_cma_worker_queue_push_mutex); ++ return true; ++} ++ ++static int vc_cma_alloc_chunks(int num_chunks, struct cma_msg *reply) ++{ ++ int i; ++ for (i = 0; i < num_chunks; i++) { ++ struct page *chunk; ++ unsigned int chunk_num; ++ uint8_t *chunk_addr; ++ size_t chunk_size = PAGES_PER_CHUNK << PAGE_SHIFT; ++ ++ chunk = dma_alloc_from_contiguous(&vc_cma_device.dev, ++ PAGES_PER_CHUNK, ++ VC_CMA_CHUNK_ORDER); ++ if (!chunk) ++ break; ++ ++ chunk_addr = page_address(chunk); ++ dmac_flush_range(chunk_addr, chunk_addr + chunk_size); ++ outer_inv_range(__pa(chunk_addr), __pa(chunk_addr) + ++ chunk_size); ++ ++ chunk_num = ++ (page_to_phys(chunk) - vc_cma_base) / VC_CMA_CHUNK_SIZE; ++ BUG_ON(((page_to_phys(chunk) - vc_cma_base) % ++ VC_CMA_CHUNK_SIZE) != 0); ++ if (chunk_num >= vc_cma_chunks) { ++ phys_addr_t _pa = vc_cma_base + vc_cma_size - 1; ++ LOG_ERR("%s: ===============================", ++ __func__); ++ LOG_ERR("%s: chunk phys %x, vc_cma %pa-%pa - " ++ "bad SPARSEMEM configuration?", ++ __func__, (unsigned int)page_to_phys(chunk), ++ &vc_cma_base, &_pa); ++ LOG_ERR("%s: dev->cma_area = %p", __func__, ++ (void*)0/*vc_cma_device.dev.cma_area*/); ++ LOG_ERR("%s: ===============================", ++ __func__); ++ break; ++ } ++ reply->params[i] = chunk_num; ++ vc_cma_chunks_used++; ++ } ++ ++ if (i < num_chunks) { ++ LOG_ERR("%s: dma_alloc_from_contiguous failed " ++ "for %x bytes (alloc %d of %d, %d free)", ++ __func__, VC_CMA_CHUNK_SIZE, i, ++ num_chunks, vc_cma_chunks - vc_cma_chunks_used); ++ num_chunks = i; ++ } ++ ++ LOG_DBG("CMA allocated %d chunks -> %d used", ++ num_chunks, vc_cma_chunks_used); ++ reply->type = VC_CMA_MSG_ALLOCATED; ++ ++ { ++ VCHIQ_ELEMENT_T elem = { ++ reply, ++ offsetof(struct cma_msg, params[0]) + ++ num_chunks * sizeof(reply->params[0]) ++ }; ++ VCHIQ_STATUS_T ret; ++ vchiq_use_service(cma_service); ++ ret = vchiq_queue_message(cma_service, &elem, 1); ++ vchiq_release_service(cma_service); ++ if (ret != VCHIQ_SUCCESS) ++ LOG_ERR("vchiq_queue_message return " "%x", ret); ++ } ++ ++ return num_chunks; ++} ++ ++static int cma_worker_proc(void *param) ++{ ++ static struct cma_msg reply; ++ (void)param; ++ ++ while (1) { ++ VCHIQ_HEADER_T *msg; ++ static struct cma_msg msg_copy; ++ struct cma_msg *cma_msg = &msg_copy; ++ int type, msg_size; ++ ++ msg = vchiu_queue_pop(&cma_msg_queue); ++ if ((unsigned int)msg >= VC_CMA_MSG_MAX) { ++ msg_size = msg->size; ++ memcpy(&msg_copy, msg->data, msg_size); ++ type = cma_msg->type; ++ vchiq_release_message(cma_service, msg); ++ } else { ++ msg_size = 0; ++ type = (int)msg; ++ if (type == VC_CMA_MSG_QUIT) ++ break; ++ else if (type == VC_CMA_MSG_UPDATE_RESERVE) { ++ msg = NULL; ++ cma_msg = NULL; ++ } else { ++ BUG(); ++ continue; ++ } ++ } ++ ++ switch (type) { ++ case VC_CMA_MSG_ALLOC:{ ++ int num_chunks, free_chunks; ++ num_chunks = cma_msg->params[0]; ++ free_chunks = ++ vc_cma_chunks - vc_cma_chunks_used; ++ LOG_DBG("CMA_MSG_ALLOC(%d chunks)", num_chunks); ++ if (num_chunks > VC_CMA_MAX_PARAMS_PER_MSG) { ++ LOG_ERR ++ ("CMA_MSG_ALLOC - chunk count (%d) " ++ "exceeds VC_CMA_MAX_PARAMS_PER_MSG (%d)", ++ num_chunks, ++ VC_CMA_MAX_PARAMS_PER_MSG); ++ num_chunks = VC_CMA_MAX_PARAMS_PER_MSG; ++ } ++ ++ if (num_chunks > free_chunks) { ++ LOG_ERR ++ ("CMA_MSG_ALLOC - chunk count (%d) " ++ "exceeds free chunks (%d)", ++ num_chunks, free_chunks); ++ num_chunks = free_chunks; ++ } ++ ++ vc_cma_alloc_chunks(num_chunks, &reply); ++ } ++ break; ++ ++ case VC_CMA_MSG_FREE:{ ++ int chunk_count = ++ (msg_size - ++ offsetof(struct cma_msg, ++ params)) / ++ sizeof(cma_msg->params[0]); ++ int i; ++ BUG_ON(chunk_count <= 0); ++ ++ LOG_DBG("CMA_MSG_FREE(%d chunks - %x, ...)", ++ chunk_count, cma_msg->params[0]); ++ for (i = 0; i < chunk_count; i++) { ++ int chunk_num = cma_msg->params[i]; ++ struct page *page = vc_cma_base_page + ++ chunk_num * PAGES_PER_CHUNK; ++ if (chunk_num >= vc_cma_chunks) { ++ LOG_ERR ++ ("CMA_MSG_FREE - chunk %d of %d" ++ " (value %x) exceeds maximum " ++ "(%x)", i, chunk_count, ++ chunk_num, ++ vc_cma_chunks - 1); ++ break; ++ } ++ ++ if (!dma_release_from_contiguous ++ (&vc_cma_device.dev, page, ++ PAGES_PER_CHUNK)) { ++ phys_addr_t _pa = page_to_phys(page); ++ LOG_ERR ++ ("CMA_MSG_FREE - failed to " ++ "release chunk %d (phys %pa, " ++ "page %x)", chunk_num, ++ &_pa, ++ (unsigned int)page); ++ } ++ vc_cma_chunks_used--; ++ } ++ LOG_DBG("CMA released %d chunks -> %d used", ++ i, vc_cma_chunks_used); ++ } ++ break; ++ ++ case VC_CMA_MSG_UPDATE_RESERVE:{ ++ int chunks_needed = ++ ((vc_cma_reserve_total + VC_CMA_CHUNK_SIZE - ++ 1) ++ / VC_CMA_CHUNK_SIZE) - ++ vc_cma_chunks_reserved; ++ ++ LOG_DBG ++ ("CMA_MSG_UPDATE_RESERVE(%d chunks needed)", ++ chunks_needed); ++ ++ /* Cap the reservations to what is available */ ++ if (chunks_needed > 0) { ++ if (chunks_needed > ++ (vc_cma_chunks - ++ vc_cma_chunks_used)) ++ chunks_needed = ++ (vc_cma_chunks - ++ vc_cma_chunks_used); ++ ++ chunks_needed = ++ vc_cma_alloc_chunks(chunks_needed, ++ &reply); ++ } ++ ++ LOG_DBG ++ ("CMA_MSG_UPDATE_RESERVE(%d chunks allocated)", ++ chunks_needed); ++ vc_cma_chunks_reserved += chunks_needed; ++ } ++ break; ++ ++ default: ++ LOG_ERR("unexpected msg type %d", type); ++ break; ++ } ++ } ++ ++ LOG_DBG("quitting..."); ++ return 0; ++} ++ ++/**************************************************************************** ++* ++* vc_cma_connected_init ++* ++* This function is called once the videocore has been connected. ++* ++***************************************************************************/ ++ ++static void vc_cma_connected_init(void) ++{ ++ VCHIQ_SERVICE_PARAMS_T service_params; ++ ++ LOG_DBG("vc_cma_connected_init"); ++ ++ if (!vchiu_queue_init(&cma_msg_queue, 16)) { ++ LOG_ERR("could not create CMA msg queue"); ++ goto fail_queue; ++ } ++ ++ if (vchiq_initialise(&cma_instance) != VCHIQ_SUCCESS) ++ goto fail_vchiq_init; ++ ++ vchiq_connect(cma_instance); ++ ++ service_params.fourcc = VC_CMA_FOURCC; ++ service_params.callback = cma_service_callback; ++ service_params.userdata = NULL; ++ service_params.version = VC_CMA_VERSION; ++ service_params.version_min = VC_CMA_VERSION; ++ ++ if (vchiq_open_service(cma_instance, &service_params, ++ &cma_service) != VCHIQ_SUCCESS) { ++ LOG_ERR("failed to open service - already in use?"); ++ goto fail_vchiq_open; ++ } ++ ++ vchiq_release_service(cma_service); ++ ++ cma_worker = kthread_create(cma_worker_proc, NULL, "cma_worker"); ++ if (!cma_worker) { ++ LOG_ERR("could not create CMA worker thread"); ++ goto fail_worker; ++ } ++ set_user_nice(cma_worker, -20); ++ wake_up_process(cma_worker); ++ ++ return; ++ ++fail_worker: ++ vchiq_close_service(cma_service); ++fail_vchiq_open: ++ vchiq_shutdown(cma_instance); ++fail_vchiq_init: ++ vchiu_queue_delete(&cma_msg_queue); ++fail_queue: ++ return; ++} ++ ++void ++loud_error_header(void) ++{ ++ if (in_loud_error) ++ return; ++ ++ LOG_ERR("============================================================" ++ "================"); ++ LOG_ERR("============================================================" ++ "================"); ++ LOG_ERR("====="); ++ ++ in_loud_error = 1; ++} ++ ++void ++loud_error_footer(void) ++{ ++ if (!in_loud_error) ++ return; ++ ++ LOG_ERR("====="); ++ LOG_ERR("============================================================" ++ "================"); ++ LOG_ERR("============================================================" ++ "================"); ++ ++ in_loud_error = 0; ++} ++ ++#if 1 ++static int check_cma_config(void) { return 1; } ++#else ++static int ++read_vc_debug_var(VC_MEM_ACCESS_HANDLE_T handle, ++ const char *symbol, ++ void *buf, size_t bufsize) ++{ ++ VC_MEM_ADDR_T vcMemAddr; ++ size_t vcMemSize; ++ uint8_t *mapAddr; ++ off_t vcMapAddr; ++ ++ if (!LookupVideoCoreSymbol(handle, symbol, ++ &vcMemAddr, ++ &vcMemSize)) { ++ loud_error_header(); ++ loud_error( ++ "failed to find VC symbol \"%s\".", ++ symbol); ++ loud_error_footer(); ++ return 0; ++ } ++ ++ if (vcMemSize != bufsize) { ++ loud_error_header(); ++ loud_error( ++ "VC symbol \"%s\" is the wrong size.", ++ symbol); ++ loud_error_footer(); ++ return 0; ++ } ++ ++ vcMapAddr = (off_t)vcMemAddr & VC_MEM_TO_ARM_ADDR_MASK; ++ vcMapAddr += mm_vc_mem_phys_addr; ++ mapAddr = ioremap_nocache(vcMapAddr, vcMemSize); ++ if (mapAddr == 0) { ++ loud_error_header(); ++ loud_error( ++ "failed to ioremap \"%s\" @ 0x%x " ++ "(phys: 0x%x, size: %u).", ++ symbol, ++ (unsigned int)vcMapAddr, ++ (unsigned int)vcMemAddr, ++ (unsigned int)vcMemSize); ++ loud_error_footer(); ++ return 0; ++ } ++ ++ memcpy(buf, mapAddr, bufsize); ++ iounmap(mapAddr); ++ ++ return 1; ++} ++ ++ ++static int ++check_cma_config(void) ++{ ++ VC_MEM_ACCESS_HANDLE_T mem_hndl; ++ VC_MEM_ADDR_T mempool_start; ++ VC_MEM_ADDR_T mempool_end; ++ VC_MEM_ADDR_T mempool_offline_start; ++ VC_MEM_ADDR_T mempool_offline_end; ++ VC_MEM_ADDR_T cam_alloc_base; ++ VC_MEM_ADDR_T cam_alloc_size; ++ VC_MEM_ADDR_T cam_alloc_end; ++ int success = 0; ++ ++ if (OpenVideoCoreMemory(&mem_hndl) != 0) ++ goto out; ++ ++ /* Read the relevant VideoCore variables */ ++ if (!read_vc_debug_var(mem_hndl, "__MEMPOOL_START", ++ &mempool_start, ++ sizeof(mempool_start))) ++ goto close; ++ ++ if (!read_vc_debug_var(mem_hndl, "__MEMPOOL_END", ++ &mempool_end, ++ sizeof(mempool_end))) ++ goto close; ++ ++ if (!read_vc_debug_var(mem_hndl, "__MEMPOOL_OFFLINE_START", ++ &mempool_offline_start, ++ sizeof(mempool_offline_start))) ++ goto close; ++ ++ if (!read_vc_debug_var(mem_hndl, "__MEMPOOL_OFFLINE_END", ++ &mempool_offline_end, ++ sizeof(mempool_offline_end))) ++ goto close; ++ ++ if (!read_vc_debug_var(mem_hndl, "cam_alloc_base", ++ &cam_alloc_base, ++ sizeof(cam_alloc_base))) ++ goto close; ++ ++ if (!read_vc_debug_var(mem_hndl, "cam_alloc_size", ++ &cam_alloc_size, ++ sizeof(cam_alloc_size))) ++ goto close; ++ ++ cam_alloc_end = cam_alloc_base + cam_alloc_size; ++ ++ success = 1; ++ ++ /* Now the sanity checks */ ++ if (!mempool_offline_start) ++ mempool_offline_start = mempool_start; ++ if (!mempool_offline_end) ++ mempool_offline_end = mempool_end; ++ ++ if (VCADDR_TO_PHYSADDR(mempool_offline_start) != vc_cma_base) { ++ loud_error_header(); ++ loud_error( ++ "__MEMPOOL_OFFLINE_START(%x -> %lx) doesn't match " ++ "vc_cma_base(%x)", ++ mempool_offline_start, ++ VCADDR_TO_PHYSADDR(mempool_offline_start), ++ vc_cma_base); ++ success = 0; ++ } ++ ++ if (VCADDR_TO_PHYSADDR(mempool_offline_end) != ++ (vc_cma_base + vc_cma_size)) { ++ loud_error_header(); ++ loud_error( ++ "__MEMPOOL_OFFLINE_END(%x -> %lx) doesn't match " ++ "vc_cma_base(%x) + vc_cma_size(%x) = %x", ++ mempool_offline_start, ++ VCADDR_TO_PHYSADDR(mempool_offline_end), ++ vc_cma_base, vc_cma_size, vc_cma_base + vc_cma_size); ++ success = 0; ++ } ++ ++ if (mempool_end < mempool_start) { ++ loud_error_header(); ++ loud_error( ++ "__MEMPOOL_END(%x) must not be before " ++ "__MEMPOOL_START(%x)", ++ mempool_end, ++ mempool_start); ++ success = 0; ++ } ++ ++ if (mempool_offline_end < mempool_offline_start) { ++ loud_error_header(); ++ loud_error( ++ "__MEMPOOL_OFFLINE_END(%x) must not be before " ++ "__MEMPOOL_OFFLINE_START(%x)", ++ mempool_offline_end, ++ mempool_offline_start); ++ success = 0; ++ } ++ ++ if (mempool_offline_start < mempool_start) { ++ loud_error_header(); ++ loud_error( ++ "__MEMPOOL_OFFLINE_START(%x) must not be before " ++ "__MEMPOOL_START(%x)", ++ mempool_offline_start, ++ mempool_start); ++ success = 0; ++ } ++ ++ if (mempool_offline_end > mempool_end) { ++ loud_error_header(); ++ loud_error( ++ "__MEMPOOL_OFFLINE_END(%x) must not be after " ++ "__MEMPOOL_END(%x)", ++ mempool_offline_end, ++ mempool_end); ++ success = 0; ++ } ++ ++ if ((cam_alloc_base < mempool_end) && ++ (cam_alloc_end > mempool_start)) { ++ loud_error_header(); ++ loud_error( ++ "cam_alloc pool(%x-%x) overlaps " ++ "mempool(%x-%x)", ++ cam_alloc_base, cam_alloc_end, ++ mempool_start, mempool_end); ++ success = 0; ++ } ++ ++ loud_error_footer(); ++ ++close: ++ CloseVideoCoreMemory(mem_hndl); ++ ++out: ++ return success; ++} ++#endif ++ ++static int vc_cma_init(void) ++{ ++ int rc = -EFAULT; ++ struct device *dev; ++ ++ if (!check_cma_config()) ++ goto out_release; ++ ++ LOG_INFO("vc-cma: Videocore CMA driver"); ++ LOG_INFO("vc-cma: vc_cma_base = %pa", &vc_cma_base); ++ LOG_INFO("vc-cma: vc_cma_size = 0x%08x (%u MiB)", ++ vc_cma_size, vc_cma_size / (1024 * 1024)); ++ LOG_INFO("vc-cma: vc_cma_initial = 0x%08x (%u MiB)", ++ vc_cma_initial, vc_cma_initial / (1024 * 1024)); ++ ++ vc_cma_base_page = phys_to_page(vc_cma_base); ++ ++ if (vc_cma_chunks) { ++ int chunks_needed = vc_cma_initial / VC_CMA_CHUNK_SIZE; ++ ++ for (vc_cma_chunks_used = 0; ++ vc_cma_chunks_used < chunks_needed; vc_cma_chunks_used++) { ++ struct page *chunk; ++ chunk = dma_alloc_from_contiguous(&vc_cma_device.dev, ++ PAGES_PER_CHUNK, ++ VC_CMA_CHUNK_ORDER); ++ if (!chunk) ++ break; ++ BUG_ON(((page_to_phys(chunk) - vc_cma_base) % ++ VC_CMA_CHUNK_SIZE) != 0); ++ } ++ if (vc_cma_chunks_used != chunks_needed) { ++ LOG_ERR("%s: dma_alloc_from_contiguous failed (%d " ++ "bytes, allocation %d of %d)", ++ __func__, VC_CMA_CHUNK_SIZE, ++ vc_cma_chunks_used, chunks_needed); ++ goto out_release; ++ } ++ ++ vchiq_add_connected_callback(vc_cma_connected_init); ++ } ++ ++ rc = alloc_chrdev_region(&vc_cma_devnum, 0, 1, DRIVER_NAME); ++ if (rc < 0) { ++ LOG_ERR("%s: alloc_chrdev_region failed (rc=%d)", __func__, rc); ++ goto out_release; ++ } ++ ++ cdev_init(&vc_cma_cdev, &vc_cma_fops); ++ rc = cdev_add(&vc_cma_cdev, vc_cma_devnum, 1); ++ if (rc != 0) { ++ LOG_ERR("%s: cdev_add failed (rc=%d)", __func__, rc); ++ goto out_unregister; ++ } ++ ++ vc_cma_class = class_create(THIS_MODULE, DRIVER_NAME); ++ if (IS_ERR(vc_cma_class)) { ++ rc = PTR_ERR(vc_cma_class); ++ LOG_ERR("%s: class_create failed (rc=%d)", __func__, rc); ++ goto out_cdev_del; ++ } ++ ++ dev = device_create(vc_cma_class, NULL, vc_cma_devnum, NULL, ++ DRIVER_NAME); ++ if (IS_ERR(dev)) { ++ rc = PTR_ERR(dev); ++ LOG_ERR("%s: device_create failed (rc=%d)", __func__, rc); ++ goto out_class_destroy; ++ } ++ ++ vc_cma_proc_entry = proc_create(DRIVER_NAME, 0444, NULL, &vc_cma_proc_fops); ++ if (vc_cma_proc_entry == NULL) { ++ rc = -EFAULT; ++ LOG_ERR("%s: proc_create failed", __func__); ++ goto out_device_destroy; ++ } ++ ++ vc_cma_inited = 1; ++ return 0; ++ ++out_device_destroy: ++ device_destroy(vc_cma_class, vc_cma_devnum); ++ ++out_class_destroy: ++ class_destroy(vc_cma_class); ++ vc_cma_class = NULL; ++ ++out_cdev_del: ++ cdev_del(&vc_cma_cdev); ++ ++out_unregister: ++ unregister_chrdev_region(vc_cma_devnum, 1); ++ ++out_release: ++ /* It is tempting to try to clean up by calling ++ dma_release_from_contiguous for all allocated chunks, but it isn't ++ a very safe thing to do. If vc_cma_initial is non-zero it is because ++ VideoCore is already using that memory, so giving it back to Linux ++ is likely to be fatal. ++ */ ++ return -1; ++} ++ ++/**************************************************************************** ++* ++* vc_cma_exit ++* ++***************************************************************************/ ++ ++static void __exit vc_cma_exit(void) ++{ ++ LOG_DBG("%s: called", __func__); ++ ++ if (vc_cma_inited) { ++ remove_proc_entry(DRIVER_NAME, NULL); ++ device_destroy(vc_cma_class, vc_cma_devnum); ++ class_destroy(vc_cma_class); ++ cdev_del(&vc_cma_cdev); ++ unregister_chrdev_region(vc_cma_devnum, 1); ++ } ++} ++ ++module_init(vc_cma_init); ++module_exit(vc_cma_exit); ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Broadcom Corporation"); +diff -Nur linux-4.1.13.orig/drivers/char/broadcom/vcio.c linux-rpi/drivers/char/broadcom/vcio.c +--- linux-4.1.13.orig/drivers/char/broadcom/vcio.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/char/broadcom/vcio.c 2015-11-29 09:42:36.707312101 +0100 +@@ -0,0 +1,175 @@ ++/* ++ * Copyright (C) 2010 Broadcom ++ * Copyright (C) 2015 Noralf Trønnes ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define MBOX_CHAN_PROPERTY 8 ++ ++#define VCIO_IOC_MAGIC 100 ++#define IOCTL_MBOX_PROPERTY _IOWR(VCIO_IOC_MAGIC, 0, char *) ++ ++static struct { ++ dev_t devt; ++ struct cdev cdev; ++ struct class *class; ++ struct rpi_firmware *fw; ++} vcio; ++ ++static int vcio_user_property_list(void *user) ++{ ++ u32 *buf, size; ++ int ret; ++ ++ /* The first 32-bit is the size of the buffer */ ++ if (copy_from_user(&size, user, sizeof(size))) ++ return -EFAULT; ++ ++ buf = kmalloc(size, GFP_KERNEL); ++ if (!buf) ++ return -ENOMEM; ++ ++ if (copy_from_user(buf, user, size)) { ++ kfree(buf); ++ return -EFAULT; ++ } ++ ++ /* Strip off protocol encapsulation */ ++ ret = rpi_firmware_property_list(vcio.fw, &buf[2], size - 12); ++ if (ret) { ++ kfree(buf); ++ return ret; ++ } ++ ++ buf[1] = RPI_FIRMWARE_STATUS_SUCCESS; ++ if (copy_to_user(user, buf, size)) ++ ret = -EFAULT; ++ ++ kfree(buf); ++ ++ return ret; ++} ++ ++static int vcio_device_open(struct inode *inode, struct file *file) ++{ ++ try_module_get(THIS_MODULE); ++ ++ return 0; ++} ++ ++static int vcio_device_release(struct inode *inode, struct file *file) ++{ ++ module_put(THIS_MODULE); ++ ++ return 0; ++} ++ ++static long vcio_device_ioctl(struct file *file, unsigned int ioctl_num, ++ unsigned long ioctl_param) ++{ ++ switch (ioctl_num) { ++ case IOCTL_MBOX_PROPERTY: ++ return vcio_user_property_list((void *)ioctl_param); ++ default: ++ pr_err("unknown ioctl: %d\n", ioctl_num); ++ return -EINVAL; ++ } ++} ++ ++const struct file_operations vcio_fops = { ++ .unlocked_ioctl = vcio_device_ioctl, ++ .open = vcio_device_open, ++ .release = vcio_device_release, ++}; ++ ++static int __init vcio_init(void) ++{ ++ struct device_node *np; ++ static struct device *dev; ++ int ret; ++ ++ np = of_find_compatible_node(NULL, NULL, ++ "raspberrypi,bcm2835-firmware"); ++/* Uncomment this when we only boot with Device Tree ++ if (!of_device_is_available(np)) ++ return -ENODEV; ++*/ ++ vcio.fw = rpi_firmware_get(np); ++ if (!vcio.fw) ++ return -ENODEV; ++ ++ ret = alloc_chrdev_region(&vcio.devt, 0, 1, "vcio"); ++ if (ret) { ++ pr_err("failed to allocate device number\n"); ++ return ret; ++ } ++ ++ cdev_init(&vcio.cdev, &vcio_fops); ++ vcio.cdev.owner = THIS_MODULE; ++ ret = cdev_add(&vcio.cdev, vcio.devt, 1); ++ if (ret) { ++ pr_err("failed to register device\n"); ++ goto err_unregister_chardev; ++ } ++ ++ /* ++ * Create sysfs entries ++ * 'bcm2708_vcio' is used for backwards compatibility so we don't break ++ * userspace. Raspian has a udev rule that changes the permissions. ++ */ ++ vcio.class = class_create(THIS_MODULE, "bcm2708_vcio"); ++ if (IS_ERR(vcio.class)) { ++ ret = PTR_ERR(vcio.class); ++ pr_err("failed to create class\n"); ++ goto err_cdev_del; ++ } ++ ++ dev = device_create(vcio.class, NULL, vcio.devt, NULL, "vcio"); ++ if (IS_ERR(dev)) { ++ ret = PTR_ERR(dev); ++ pr_err("failed to create device\n"); ++ goto err_class_destroy; ++ } ++ ++ return 0; ++ ++err_class_destroy: ++ class_destroy(vcio.class); ++err_cdev_del: ++ cdev_del(&vcio.cdev); ++err_unregister_chardev: ++ unregister_chrdev_region(vcio.devt, 1); ++ ++ return ret; ++} ++module_init(vcio_init); ++ ++static void __exit vcio_exit(void) ++{ ++ device_destroy(vcio.class, vcio.devt); ++ class_destroy(vcio.class); ++ cdev_del(&vcio.cdev); ++ unregister_chrdev_region(vcio.devt, 1); ++} ++module_exit(vcio_exit); ++ ++MODULE_AUTHOR("Gray Girling"); ++MODULE_AUTHOR("Noralf Trønnes"); ++MODULE_DESCRIPTION("Mailbox userspace access"); ++MODULE_LICENSE("GPL"); +diff -Nur linux-4.1.13.orig/drivers/char/broadcom/vc_mem.c linux-rpi/drivers/char/broadcom/vc_mem.c +--- linux-4.1.13.orig/drivers/char/broadcom/vc_mem.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/char/broadcom/vc_mem.c 2015-11-29 09:42:36.703312367 +0100 +@@ -0,0 +1,422 @@ ++/***************************************************************************** ++* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define DRIVER_NAME "vc-mem" ++ ++// Device (/dev) related variables ++static dev_t vc_mem_devnum = 0; ++static struct class *vc_mem_class = NULL; ++static struct cdev vc_mem_cdev; ++static int vc_mem_inited = 0; ++ ++#ifdef CONFIG_DEBUG_FS ++static struct dentry *vc_mem_debugfs_entry; ++#endif ++ ++/* ++ * Videocore memory addresses and size ++ * ++ * Drivers that wish to know the videocore memory addresses and sizes should ++ * use these variables instead of the MM_IO_BASE and MM_ADDR_IO defines in ++ * headers. This allows the other drivers to not be tied down to a a certain ++ * address/size at compile time. ++ * ++ * In the future, the goal is to have the videocore memory virtual address and ++ * size be calculated at boot time rather than at compile time. The decision of ++ * where the videocore memory resides and its size would be in the hands of the ++ * bootloader (and/or kernel). When that happens, the values of these variables ++ * would be calculated and assigned in the init function. ++ */ ++// in the 2835 VC in mapped above ARM, but ARM has full access to VC space ++unsigned long mm_vc_mem_phys_addr = 0x00000000; ++unsigned int mm_vc_mem_size = 0; ++unsigned int mm_vc_mem_base = 0; ++ ++EXPORT_SYMBOL(mm_vc_mem_phys_addr); ++EXPORT_SYMBOL(mm_vc_mem_size); ++EXPORT_SYMBOL(mm_vc_mem_base); ++ ++static uint phys_addr = 0; ++static uint mem_size = 0; ++static uint mem_base = 0; ++ ++ ++/**************************************************************************** ++* ++* vc_mem_open ++* ++***************************************************************************/ ++ ++static int ++vc_mem_open(struct inode *inode, struct file *file) ++{ ++ (void) inode; ++ (void) file; ++ ++ pr_debug("%s: called file = 0x%p\n", __func__, file); ++ ++ return 0; ++} ++ ++/**************************************************************************** ++* ++* vc_mem_release ++* ++***************************************************************************/ ++ ++static int ++vc_mem_release(struct inode *inode, struct file *file) ++{ ++ (void) inode; ++ (void) file; ++ ++ pr_debug("%s: called file = 0x%p\n", __func__, file); ++ ++ return 0; ++} ++ ++/**************************************************************************** ++* ++* vc_mem_get_size ++* ++***************************************************************************/ ++ ++static void ++vc_mem_get_size(void) ++{ ++} ++ ++/**************************************************************************** ++* ++* vc_mem_get_base ++* ++***************************************************************************/ ++ ++static void ++vc_mem_get_base(void) ++{ ++} ++ ++/**************************************************************************** ++* ++* vc_mem_get_current_size ++* ++***************************************************************************/ ++ ++int ++vc_mem_get_current_size(void) ++{ ++ return mm_vc_mem_size; ++} ++ ++EXPORT_SYMBOL_GPL(vc_mem_get_current_size); ++ ++/**************************************************************************** ++* ++* vc_mem_ioctl ++* ++***************************************************************************/ ++ ++static long ++vc_mem_ioctl(struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ int rc = 0; ++ ++ (void) cmd; ++ (void) arg; ++ ++ pr_debug("%s: called file = 0x%p\n", __func__, file); ++ ++ switch (cmd) { ++ case VC_MEM_IOC_MEM_PHYS_ADDR: ++ { ++ pr_debug("%s: VC_MEM_IOC_MEM_PHYS_ADDR=0x%p\n", ++ __func__, (void *) mm_vc_mem_phys_addr); ++ ++ if (copy_to_user((void *) arg, &mm_vc_mem_phys_addr, ++ sizeof (mm_vc_mem_phys_addr)) != 0) { ++ rc = -EFAULT; ++ } ++ break; ++ } ++ case VC_MEM_IOC_MEM_SIZE: ++ { ++ // Get the videocore memory size first ++ vc_mem_get_size(); ++ ++ pr_debug("%s: VC_MEM_IOC_MEM_SIZE=%u\n", __func__, ++ mm_vc_mem_size); ++ ++ if (copy_to_user((void *) arg, &mm_vc_mem_size, ++ sizeof (mm_vc_mem_size)) != 0) { ++ rc = -EFAULT; ++ } ++ break; ++ } ++ case VC_MEM_IOC_MEM_BASE: ++ { ++ // Get the videocore memory base ++ vc_mem_get_base(); ++ ++ pr_debug("%s: VC_MEM_IOC_MEM_BASE=%u\n", __func__, ++ mm_vc_mem_base); ++ ++ if (copy_to_user((void *) arg, &mm_vc_mem_base, ++ sizeof (mm_vc_mem_base)) != 0) { ++ rc = -EFAULT; ++ } ++ break; ++ } ++ case VC_MEM_IOC_MEM_LOAD: ++ { ++ // Get the videocore memory base ++ vc_mem_get_base(); ++ ++ pr_debug("%s: VC_MEM_IOC_MEM_LOAD=%u\n", __func__, ++ mm_vc_mem_base); ++ ++ if (copy_to_user((void *) arg, &mm_vc_mem_base, ++ sizeof (mm_vc_mem_base)) != 0) { ++ rc = -EFAULT; ++ } ++ break; ++ } ++ default: ++ { ++ return -ENOTTY; ++ } ++ } ++ pr_debug("%s: file = 0x%p returning %d\n", __func__, file, rc); ++ ++ return rc; ++} ++ ++/**************************************************************************** ++* ++* vc_mem_mmap ++* ++***************************************************************************/ ++ ++static int ++vc_mem_mmap(struct file *filp, struct vm_area_struct *vma) ++{ ++ int rc = 0; ++ unsigned long length = vma->vm_end - vma->vm_start; ++ unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; ++ ++ pr_debug("%s: vm_start = 0x%08lx vm_end = 0x%08lx vm_pgoff = 0x%08lx\n", ++ __func__, (long) vma->vm_start, (long) vma->vm_end, ++ (long) vma->vm_pgoff); ++ ++ if (offset + length > mm_vc_mem_size) { ++ pr_err("%s: length %ld is too big\n", __func__, length); ++ return -EINVAL; ++ } ++ // Do not cache the memory map ++ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); ++ ++ rc = remap_pfn_range(vma, vma->vm_start, ++ (mm_vc_mem_phys_addr >> PAGE_SHIFT) + ++ vma->vm_pgoff, length, vma->vm_page_prot); ++ if (rc != 0) { ++ pr_err("%s: remap_pfn_range failed (rc=%d)\n", __func__, rc); ++ } ++ ++ return rc; ++} ++ ++/**************************************************************************** ++* ++* File Operations for the driver. ++* ++***************************************************************************/ ++ ++static const struct file_operations vc_mem_fops = { ++ .owner = THIS_MODULE, ++ .open = vc_mem_open, ++ .release = vc_mem_release, ++ .unlocked_ioctl = vc_mem_ioctl, ++ .mmap = vc_mem_mmap, ++}; ++ ++#ifdef CONFIG_DEBUG_FS ++static void vc_mem_debugfs_deinit(void) ++{ ++ debugfs_remove_recursive(vc_mem_debugfs_entry); ++ vc_mem_debugfs_entry = NULL; ++} ++ ++ ++static int vc_mem_debugfs_init( ++ struct device *dev) ++{ ++ vc_mem_debugfs_entry = debugfs_create_dir(DRIVER_NAME, NULL); ++ if (!vc_mem_debugfs_entry) { ++ dev_warn(dev, "could not create debugfs entry\n"); ++ return -EFAULT; ++ } ++ ++ if (!debugfs_create_x32("vc_mem_phys_addr", ++ 0444, ++ vc_mem_debugfs_entry, ++ (u32 *)&mm_vc_mem_phys_addr)) { ++ dev_warn(dev, "%s:could not create vc_mem_phys entry\n", ++ __func__); ++ goto fail; ++ } ++ ++ if (!debugfs_create_x32("vc_mem_size", ++ 0444, ++ vc_mem_debugfs_entry, ++ (u32 *)&mm_vc_mem_size)) { ++ dev_warn(dev, "%s:could not create vc_mem_size entry\n", ++ __func__); ++ goto fail; ++ } ++ ++ if (!debugfs_create_x32("vc_mem_base", ++ 0444, ++ vc_mem_debugfs_entry, ++ (u32 *)&mm_vc_mem_base)) { ++ dev_warn(dev, "%s:could not create vc_mem_base entry\n", ++ __func__); ++ goto fail; ++ } ++ ++ return 0; ++ ++fail: ++ vc_mem_debugfs_deinit(); ++ return -EFAULT; ++} ++ ++#endif /* CONFIG_DEBUG_FS */ ++ ++ ++/**************************************************************************** ++* ++* vc_mem_init ++* ++***************************************************************************/ ++ ++static int __init ++vc_mem_init(void) ++{ ++ int rc = -EFAULT; ++ struct device *dev; ++ ++ pr_debug("%s: called\n", __func__); ++ ++ mm_vc_mem_phys_addr = phys_addr; ++ mm_vc_mem_size = mem_size; ++ mm_vc_mem_base = mem_base; ++ ++ vc_mem_get_size(); ++ ++ pr_info("vc-mem: phys_addr:0x%08lx mem_base=0x%08x mem_size:0x%08x(%u MiB)\n", ++ mm_vc_mem_phys_addr, mm_vc_mem_base, mm_vc_mem_size, mm_vc_mem_size / (1024 * 1024)); ++ ++ if ((rc = alloc_chrdev_region(&vc_mem_devnum, 0, 1, DRIVER_NAME)) < 0) { ++ pr_err("%s: alloc_chrdev_region failed (rc=%d)\n", ++ __func__, rc); ++ goto out_err; ++ } ++ ++ cdev_init(&vc_mem_cdev, &vc_mem_fops); ++ if ((rc = cdev_add(&vc_mem_cdev, vc_mem_devnum, 1)) != 0) { ++ pr_err("%s: cdev_add failed (rc=%d)\n", __func__, rc); ++ goto out_unregister; ++ } ++ ++ vc_mem_class = class_create(THIS_MODULE, DRIVER_NAME); ++ if (IS_ERR(vc_mem_class)) { ++ rc = PTR_ERR(vc_mem_class); ++ pr_err("%s: class_create failed (rc=%d)\n", __func__, rc); ++ goto out_cdev_del; ++ } ++ ++ dev = device_create(vc_mem_class, NULL, vc_mem_devnum, NULL, ++ DRIVER_NAME); ++ if (IS_ERR(dev)) { ++ rc = PTR_ERR(dev); ++ pr_err("%s: device_create failed (rc=%d)\n", __func__, rc); ++ goto out_class_destroy; ++ } ++ ++#ifdef CONFIG_DEBUG_FS ++ /* don't fail if the debug entries cannot be created */ ++ vc_mem_debugfs_init(dev); ++#endif ++ ++ vc_mem_inited = 1; ++ return 0; ++ ++ device_destroy(vc_mem_class, vc_mem_devnum); ++ ++ out_class_destroy: ++ class_destroy(vc_mem_class); ++ vc_mem_class = NULL; ++ ++ out_cdev_del: ++ cdev_del(&vc_mem_cdev); ++ ++ out_unregister: ++ unregister_chrdev_region(vc_mem_devnum, 1); ++ ++ out_err: ++ return -1; ++} ++ ++/**************************************************************************** ++* ++* vc_mem_exit ++* ++***************************************************************************/ ++ ++static void __exit ++vc_mem_exit(void) ++{ ++ pr_debug("%s: called\n", __func__); ++ ++ if (vc_mem_inited) { ++#if CONFIG_DEBUG_FS ++ vc_mem_debugfs_deinit(); ++#endif ++ device_destroy(vc_mem_class, vc_mem_devnum); ++ class_destroy(vc_mem_class); ++ cdev_del(&vc_mem_cdev); ++ unregister_chrdev_region(vc_mem_devnum, 1); ++ } ++} ++ ++module_init(vc_mem_init); ++module_exit(vc_mem_exit); ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Broadcom Corporation"); ++ ++module_param(phys_addr, uint, 0644); ++module_param(mem_size, uint, 0644); ++module_param(mem_base, uint, 0644); +diff -Nur linux-4.1.13.orig/drivers/char/broadcom/vc_sm/Makefile linux-rpi/drivers/char/broadcom/vc_sm/Makefile +--- linux-4.1.13.orig/drivers/char/broadcom/vc_sm/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/char/broadcom/vc_sm/Makefile 2015-11-29 09:42:36.703312367 +0100 +@@ -0,0 +1,21 @@ ++EXTRA_CFLAGS += -Wall -Wstrict-prototypes -Wno-trigraphs -O2 ++ ++EXTRA_CFLAGS += -I"./arch/arm/mach-bcm2708/include/mach" ++EXTRA_CFLAGS += -I"drivers/misc/vc04_services" ++EXTRA_CFLAGS += -I"drivers/misc/vc04_services/interface/vchi" ++EXTRA_CFLAGS += -I"drivers/misc/vc04_services/interface/vchiq_arm" ++EXTRA_CFLAGS += -I"$(srctree)/fs/" ++ ++EXTRA_CFLAGS += -DOS_ASSERT_FAILURE ++EXTRA_CFLAGS += -D__STDC_VERSION=199901L ++EXTRA_CFLAGS += -D__STDC_VERSION__=199901L ++EXTRA_CFLAGS += -D__VCCOREVER__=0 ++EXTRA_CFLAGS += -D__KERNEL__ ++EXTRA_CFLAGS += -D__linux__ ++EXTRA_CFLAGS += -Werror ++ ++obj-$(CONFIG_BCM_VC_SM) := vc-sm.o ++ ++vc-sm-objs := \ ++ vmcs_sm.o \ ++ vc_vchi_sm.o +diff -Nur linux-4.1.13.orig/drivers/char/broadcom/vc_sm/vc_vchi_sm.c linux-rpi/drivers/char/broadcom/vc_sm/vc_vchi_sm.c +--- linux-4.1.13.orig/drivers/char/broadcom/vc_sm/vc_vchi_sm.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/char/broadcom/vc_sm/vc_vchi_sm.c 2015-11-29 09:42:36.703312367 +0100 +@@ -0,0 +1,492 @@ ++/***************************************************************************** ++* Copyright 2011-2012 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++/* ---- Include Files ----------------------------------------------------- */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "vc_vchi_sm.h" ++ ++#define VC_SM_VER 1 ++#define VC_SM_MIN_VER 0 ++ ++/* ---- Private Constants and Types -------------------------------------- */ ++ ++/* Command blocks come from a pool */ ++#define SM_MAX_NUM_CMD_RSP_BLKS 32 ++ ++struct sm_cmd_rsp_blk { ++ struct list_head head; /* To create lists */ ++ struct semaphore sema; /* To be signaled when the response is there */ ++ ++ uint16_t id; ++ uint16_t length; ++ ++ uint8_t msg[VC_SM_MAX_MSG_LEN]; ++ ++ uint32_t wait:1; ++ uint32_t sent:1; ++ uint32_t alloc:1; ++ ++}; ++ ++struct sm_instance { ++ uint32_t num_connections; ++ VCHI_SERVICE_HANDLE_T vchi_handle[VCHI_MAX_NUM_CONNECTIONS]; ++ struct task_struct *io_thread; ++ struct semaphore io_sema; ++ ++ uint32_t trans_id; ++ ++ struct mutex lock; ++ struct list_head cmd_list; ++ struct list_head rsp_list; ++ struct list_head dead_list; ++ ++ struct sm_cmd_rsp_blk free_blk[SM_MAX_NUM_CMD_RSP_BLKS]; ++ struct list_head free_list; ++ struct mutex free_lock; ++ struct semaphore free_sema; ++ ++}; ++ ++/* ---- Private Variables ------------------------------------------------ */ ++ ++/* ---- Private Function Prototypes -------------------------------------- */ ++ ++/* ---- Private Functions ------------------------------------------------ */ ++static struct ++sm_cmd_rsp_blk *vc_vchi_cmd_create(struct sm_instance *instance, ++ VC_SM_MSG_TYPE id, void *msg, ++ uint32_t size, int wait) ++{ ++ struct sm_cmd_rsp_blk *blk; ++ VC_SM_MSG_HDR_T *hdr; ++ ++ if (down_interruptible(&instance->free_sema)) { ++ blk = kmalloc(sizeof(*blk), GFP_KERNEL); ++ if (!blk) ++ return NULL; ++ ++ blk->alloc = 1; ++ sema_init(&blk->sema, 0); ++ } else { ++ mutex_lock(&instance->free_lock); ++ blk = ++ list_first_entry(&instance->free_list, ++ struct sm_cmd_rsp_blk, head); ++ list_del(&blk->head); ++ mutex_unlock(&instance->free_lock); ++ } ++ ++ blk->sent = 0; ++ blk->wait = wait; ++ blk->length = sizeof(*hdr) + size; ++ ++ hdr = (VC_SM_MSG_HDR_T *) blk->msg; ++ hdr->type = id; ++ mutex_lock(&instance->lock); ++ hdr->trans_id = blk->id = ++instance->trans_id; ++ mutex_unlock(&instance->lock); ++ ++ if (size) ++ memcpy(hdr->body, msg, size); ++ ++ return blk; ++} ++ ++static void ++vc_vchi_cmd_delete(struct sm_instance *instance, struct sm_cmd_rsp_blk *blk) ++{ ++ if (blk->alloc) { ++ kfree(blk); ++ return; ++ } ++ ++ mutex_lock(&instance->free_lock); ++ list_add(&blk->head, &instance->free_list); ++ mutex_unlock(&instance->free_lock); ++ up(&instance->free_sema); ++} ++ ++static int vc_vchi_sm_videocore_io(void *arg) ++{ ++ struct sm_instance *instance = arg; ++ struct sm_cmd_rsp_blk *cmd = NULL, *cmd_tmp; ++ VC_SM_RESULT_T *reply; ++ uint32_t reply_len; ++ int32_t status; ++ int svc_use = 1; ++ ++ while (1) { ++ if (svc_use) ++ vchi_service_release(instance->vchi_handle[0]); ++ svc_use = 0; ++ if (!down_interruptible(&instance->io_sema)) { ++ vchi_service_use(instance->vchi_handle[0]); ++ svc_use = 1; ++ ++ do { ++ unsigned int flags; ++ /* ++ * Get new command and move it to response list ++ */ ++ mutex_lock(&instance->lock); ++ if (list_empty(&instance->cmd_list)) { ++ /* no more commands to process */ ++ mutex_unlock(&instance->lock); ++ break; ++ } ++ cmd = ++ list_first_entry(&instance->cmd_list, ++ struct sm_cmd_rsp_blk, ++ head); ++ list_move(&cmd->head, &instance->rsp_list); ++ cmd->sent = 1; ++ mutex_unlock(&instance->lock); ++ ++ /* Send the command */ ++ flags = VCHI_FLAGS_BLOCK_UNTIL_QUEUED; ++ status = vchi_msg_queue( ++ instance->vchi_handle[0], ++ cmd->msg, cmd->length, ++ flags, NULL); ++ if (status) { ++ pr_err("%s: failed to queue message (%d)", ++ __func__, status); ++ } ++ ++ /* If no reply is needed then we're done */ ++ if (!cmd->wait) { ++ mutex_lock(&instance->lock); ++ list_del(&cmd->head); ++ mutex_unlock(&instance->lock); ++ vc_vchi_cmd_delete(instance, cmd); ++ continue; ++ } ++ ++ if (status) { ++ up(&cmd->sema); ++ continue; ++ } ++ ++ } while (1); ++ ++ while (!vchi_msg_peek ++ (instance->vchi_handle[0], (void **)&reply, ++ &reply_len, VCHI_FLAGS_NONE)) { ++ mutex_lock(&instance->lock); ++ list_for_each_entry(cmd, &instance->rsp_list, ++ head) { ++ if (cmd->id == reply->trans_id) ++ break; ++ } ++ mutex_unlock(&instance->lock); ++ ++ if (&cmd->head == &instance->rsp_list) { ++ pr_debug("%s: received response %u, throw away...", ++ __func__, reply->trans_id); ++ } else if (reply_len > sizeof(cmd->msg)) { ++ pr_err("%s: reply too big (%u) %u, throw away...", ++ __func__, reply_len, ++ reply->trans_id); ++ } else { ++ memcpy(cmd->msg, reply, reply_len); ++ up(&cmd->sema); ++ } ++ ++ vchi_msg_remove(instance->vchi_handle[0]); ++ } ++ ++ /* Go through the dead list and free them */ ++ mutex_lock(&instance->lock); ++ list_for_each_entry_safe(cmd, cmd_tmp, ++ &instance->dead_list, head) { ++ list_del(&cmd->head); ++ vc_vchi_cmd_delete(instance, cmd); ++ } ++ mutex_unlock(&instance->lock); ++ } ++ } ++ ++ return 0; ++} ++ ++static void vc_sm_vchi_callback(void *param, ++ const VCHI_CALLBACK_REASON_T reason, ++ void *msg_handle) ++{ ++ struct sm_instance *instance = param; ++ ++ (void)msg_handle; ++ ++ switch (reason) { ++ case VCHI_CALLBACK_MSG_AVAILABLE: ++ up(&instance->io_sema); ++ break; ++ ++ case VCHI_CALLBACK_SERVICE_CLOSED: ++ pr_info("%s: service CLOSED!!", __func__); ++ default: ++ break; ++ } ++} ++ ++VC_VCHI_SM_HANDLE_T vc_vchi_sm_init(VCHI_INSTANCE_T vchi_instance, ++ VCHI_CONNECTION_T **vchi_connections, ++ uint32_t num_connections) ++{ ++ uint32_t i; ++ struct sm_instance *instance; ++ int status; ++ ++ pr_debug("%s: start", __func__); ++ ++ if (num_connections > VCHI_MAX_NUM_CONNECTIONS) { ++ pr_err("%s: unsupported number of connections %u (max=%u)", ++ __func__, num_connections, VCHI_MAX_NUM_CONNECTIONS); ++ ++ goto err_null; ++ } ++ /* Allocate memory for this instance */ ++ instance = kzalloc(sizeof(*instance), GFP_KERNEL); ++ ++ /* Misc initialisations */ ++ mutex_init(&instance->lock); ++ sema_init(&instance->io_sema, 0); ++ INIT_LIST_HEAD(&instance->cmd_list); ++ INIT_LIST_HEAD(&instance->rsp_list); ++ INIT_LIST_HEAD(&instance->dead_list); ++ INIT_LIST_HEAD(&instance->free_list); ++ sema_init(&instance->free_sema, SM_MAX_NUM_CMD_RSP_BLKS); ++ mutex_init(&instance->free_lock); ++ for (i = 0; i < SM_MAX_NUM_CMD_RSP_BLKS; i++) { ++ sema_init(&instance->free_blk[i].sema, 0); ++ list_add(&instance->free_blk[i].head, &instance->free_list); ++ } ++ ++ /* Open the VCHI service connections */ ++ instance->num_connections = num_connections; ++ for (i = 0; i < num_connections; i++) { ++ SERVICE_CREATION_T params = { ++ VCHI_VERSION_EX(VC_SM_VER, VC_SM_MIN_VER), ++ VC_SM_SERVER_NAME, ++ vchi_connections[i], ++ 0, ++ 0, ++ vc_sm_vchi_callback, ++ instance, ++ 0, ++ 0, ++ 0, ++ }; ++ ++ status = vchi_service_open(vchi_instance, ++ ¶ms, &instance->vchi_handle[i]); ++ if (status) { ++ pr_err("%s: failed to open VCHI service (%d)", ++ __func__, status); ++ ++ goto err_close_services; ++ } ++ } ++ ++ /* Create the thread which takes care of all io to/from videoocore. */ ++ instance->io_thread = kthread_create(&vc_vchi_sm_videocore_io, ++ (void *)instance, "SMIO"); ++ if (instance->io_thread == NULL) { ++ pr_err("%s: failed to create SMIO thread", __func__); ++ ++ goto err_close_services; ++ } ++ set_user_nice(instance->io_thread, -10); ++ wake_up_process(instance->io_thread); ++ ++ pr_debug("%s: success - instance 0x%x", __func__, (unsigned)instance); ++ return instance; ++ ++err_close_services: ++ for (i = 0; i < instance->num_connections; i++) { ++ if (instance->vchi_handle[i] != NULL) ++ vchi_service_close(instance->vchi_handle[i]); ++ } ++ kfree(instance); ++err_null: ++ pr_debug("%s: FAILED", __func__); ++ return NULL; ++} ++ ++int vc_vchi_sm_stop(VC_VCHI_SM_HANDLE_T *handle) ++{ ++ struct sm_instance *instance; ++ uint32_t i; ++ ++ if (handle == NULL) { ++ pr_err("%s: invalid pointer to handle %p", __func__, handle); ++ goto lock; ++ } ++ ++ if (*handle == NULL) { ++ pr_err("%s: invalid handle %p", __func__, *handle); ++ goto lock; ++ } ++ ++ instance = *handle; ++ ++ /* Close all VCHI service connections */ ++ for (i = 0; i < instance->num_connections; i++) { ++ int32_t success; ++ vchi_service_use(instance->vchi_handle[i]); ++ ++ success = vchi_service_close(instance->vchi_handle[i]); ++ } ++ ++ kfree(instance); ++ ++ *handle = NULL; ++ return 0; ++ ++lock: ++ return -EINVAL; ++} ++ ++int vc_vchi_sm_send_msg(VC_VCHI_SM_HANDLE_T handle, ++ VC_SM_MSG_TYPE msg_id, ++ void *msg, uint32_t msg_size, ++ void *result, uint32_t result_size, ++ uint32_t *cur_trans_id, uint8_t wait_reply) ++{ ++ int status = 0; ++ struct sm_instance *instance = handle; ++ struct sm_cmd_rsp_blk *cmd_blk; ++ ++ if (handle == NULL) { ++ pr_err("%s: invalid handle", __func__); ++ return -EINVAL; ++ } ++ if (msg == NULL) { ++ pr_err("%s: invalid msg pointer", __func__); ++ return -EINVAL; ++ } ++ ++ cmd_blk = ++ vc_vchi_cmd_create(instance, msg_id, msg, msg_size, wait_reply); ++ if (cmd_blk == NULL) { ++ pr_err("[%s]: failed to allocate global tracking resource", ++ __func__); ++ return -ENOMEM; ++ } ++ ++ if (cur_trans_id != NULL) ++ *cur_trans_id = cmd_blk->id; ++ ++ mutex_lock(&instance->lock); ++ list_add_tail(&cmd_blk->head, &instance->cmd_list); ++ mutex_unlock(&instance->lock); ++ up(&instance->io_sema); ++ ++ if (!wait_reply) ++ /* We're done */ ++ return 0; ++ ++ /* Wait for the response */ ++ if (down_interruptible(&cmd_blk->sema)) { ++ mutex_lock(&instance->lock); ++ if (!cmd_blk->sent) { ++ list_del(&cmd_blk->head); ++ mutex_unlock(&instance->lock); ++ vc_vchi_cmd_delete(instance, cmd_blk); ++ return -ENXIO; ++ } ++ mutex_unlock(&instance->lock); ++ ++ mutex_lock(&instance->lock); ++ list_move(&cmd_blk->head, &instance->dead_list); ++ mutex_unlock(&instance->lock); ++ up(&instance->io_sema); ++ return -EINTR; /* We're done */ ++ } ++ ++ if (result && result_size) { ++ memcpy(result, cmd_blk->msg, result_size); ++ } else { ++ VC_SM_RESULT_T *res = (VC_SM_RESULT_T *) cmd_blk->msg; ++ status = (res->success == 0) ? 0 : -ENXIO; ++ } ++ ++ mutex_lock(&instance->lock); ++ list_del(&cmd_blk->head); ++ mutex_unlock(&instance->lock); ++ vc_vchi_cmd_delete(instance, cmd_blk); ++ return status; ++} ++ ++int vc_vchi_sm_alloc(VC_VCHI_SM_HANDLE_T handle, VC_SM_ALLOC_T *msg, ++ VC_SM_ALLOC_RESULT_T *result, uint32_t *cur_trans_id) ++{ ++ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_ALLOC, ++ msg, sizeof(*msg), result, sizeof(*result), ++ cur_trans_id, 1); ++} ++ ++int vc_vchi_sm_free(VC_VCHI_SM_HANDLE_T handle, ++ VC_SM_FREE_T *msg, uint32_t *cur_trans_id) ++{ ++ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_FREE, ++ msg, sizeof(*msg), 0, 0, cur_trans_id, 0); ++} ++ ++int vc_vchi_sm_lock(VC_VCHI_SM_HANDLE_T handle, ++ VC_SM_LOCK_UNLOCK_T *msg, ++ VC_SM_LOCK_RESULT_T *result, uint32_t *cur_trans_id) ++{ ++ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_LOCK, ++ msg, sizeof(*msg), result, sizeof(*result), ++ cur_trans_id, 1); ++} ++ ++int vc_vchi_sm_unlock(VC_VCHI_SM_HANDLE_T handle, ++ VC_SM_LOCK_UNLOCK_T *msg, ++ uint32_t *cur_trans_id, uint8_t wait_reply) ++{ ++ return vc_vchi_sm_send_msg(handle, wait_reply ? ++ VC_SM_MSG_TYPE_UNLOCK : ++ VC_SM_MSG_TYPE_UNLOCK_NOANS, msg, ++ sizeof(*msg), 0, 0, cur_trans_id, ++ wait_reply); ++} ++ ++int vc_vchi_sm_resize(VC_VCHI_SM_HANDLE_T handle, VC_SM_RESIZE_T *msg, ++ uint32_t *cur_trans_id) ++{ ++ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_RESIZE, ++ msg, sizeof(*msg), 0, 0, cur_trans_id, 1); ++} ++ ++int vc_vchi_sm_walk_alloc(VC_VCHI_SM_HANDLE_T handle) ++{ ++ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_WALK_ALLOC, ++ 0, 0, 0, 0, 0, 0); ++} ++ ++int vc_vchi_sm_clean_up(VC_VCHI_SM_HANDLE_T handle, VC_SM_ACTION_CLEAN_T *msg) ++{ ++ return vc_vchi_sm_send_msg(handle, VC_SM_MSG_TYPE_ACTION_CLEAN, ++ msg, sizeof(*msg), 0, 0, 0, 0); ++} +diff -Nur linux-4.1.13.orig/drivers/char/broadcom/vc_sm/vmcs_sm.c linux-rpi/drivers/char/broadcom/vc_sm/vmcs_sm.c +--- linux-4.1.13.orig/drivers/char/broadcom/vc_sm/vmcs_sm.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/char/broadcom/vc_sm/vmcs_sm.c 2015-11-29 09:42:36.707312101 +0100 +@@ -0,0 +1,3211 @@ ++/***************************************************************************** ++* Copyright 2011-2012 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++/* ---- Include Files ----------------------------------------------------- */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "vchiq_connected.h" ++#include "vc_vchi_sm.h" ++ ++#include ++#include "vc_sm_knl.h" ++ ++/* ---- Private Constants and Types --------------------------------------- */ ++ ++#define DEVICE_NAME "vcsm" ++#define DEVICE_MINOR 0 ++ ++#define VC_SM_DIR_ROOT_NAME "vc-smem" ++#define VC_SM_DIR_ALLOC_NAME "alloc" ++#define VC_SM_STATE "state" ++#define VC_SM_STATS "statistics" ++#define VC_SM_RESOURCES "resources" ++#define VC_SM_DEBUG "debug" ++#define VC_SM_WRITE_BUF_SIZE 128 ++ ++/* Statistics tracked per resource and globally. ++*/ ++enum SM_STATS_T { ++ /* Attempt. */ ++ ALLOC, ++ FREE, ++ LOCK, ++ UNLOCK, ++ MAP, ++ FLUSH, ++ INVALID, ++ ++ END_ATTEMPT, ++ ++ /* Failure. */ ++ ALLOC_FAIL, ++ FREE_FAIL, ++ LOCK_FAIL, ++ UNLOCK_FAIL, ++ MAP_FAIL, ++ FLUSH_FAIL, ++ INVALID_FAIL, ++ ++ END_ALL, ++ ++}; ++ ++static const char *const sm_stats_human_read[] = { ++ "Alloc", ++ "Free", ++ "Lock", ++ "Unlock", ++ "Map", ++ "Cache Flush", ++ "Cache Invalidate", ++}; ++ ++typedef int (*VC_SM_SHOW) (struct seq_file *s, void *v); ++struct SM_PDE_T { ++ VC_SM_SHOW show; /* Debug fs function hookup. */ ++ struct dentry *dir_entry; /* Debug fs directory entry. */ ++ void *priv_data; /* Private data */ ++ ++}; ++ ++/* Single resource allocation tracked for all devices. ++*/ ++struct sm_mmap { ++ struct list_head map_list; /* Linked list of maps. */ ++ ++ struct SM_RESOURCE_T *resource; /* Pointer to the resource. */ ++ ++ pid_t res_pid; /* PID owning that resource. */ ++ unsigned int res_vc_hdl; /* Resource handle (videocore). */ ++ unsigned int res_usr_hdl; /* Resource handle (user). */ ++ ++ long unsigned int res_addr; /* Mapped virtual address. */ ++ struct vm_area_struct *vma; /* VM area for this mapping. */ ++ unsigned int ref_count; /* Reference count to this vma. */ ++ ++ /* Used to link maps associated with a resource. */ ++ struct list_head resource_map_list; ++}; ++ ++/* Single resource allocation tracked for each opened device. ++*/ ++struct SM_RESOURCE_T { ++ struct list_head resource_list; /* List of resources. */ ++ struct list_head global_resource_list; /* Global list of resources. */ ++ ++ pid_t pid; /* PID owning that resource. */ ++ uint32_t res_guid; /* Unique identifier. */ ++ uint32_t lock_count; /* Lock count for this resource. */ ++ uint32_t ref_count; /* Ref count for this resource. */ ++ ++ uint32_t res_handle; /* Resource allocation handle. */ ++ void *res_base_mem; /* Resource base memory address. */ ++ uint32_t res_size; /* Resource size allocated. */ ++ enum vmcs_sm_cache_e res_cached; /* Resource cache type. */ ++ struct SM_RESOURCE_T *res_shared; /* Shared resource */ ++ ++ enum SM_STATS_T res_stats[END_ALL]; /* Resource statistics. */ ++ ++ uint8_t map_count; /* Counter of mappings for this resource. */ ++ struct list_head map_list; /* Maps associated with a resource. */ ++ ++ struct SM_PRIV_DATA_T *private; ++}; ++ ++/* Private file data associated with each opened device. ++*/ ++struct SM_PRIV_DATA_T { ++ struct list_head resource_list; /* List of resources. */ ++ ++ pid_t pid; /* PID of creator. */ ++ ++ struct dentry *dir_pid; /* Debug fs entries root. */ ++ struct SM_PDE_T dir_stats; /* Debug fs entries statistics sub-tree. */ ++ struct SM_PDE_T dir_res; /* Debug fs resource sub-tree. */ ++ ++ int restart_sys; /* Tracks restart on interrupt. */ ++ VC_SM_MSG_TYPE int_action; /* Interrupted action. */ ++ uint32_t int_trans_id; /* Interrupted transaction. */ ++ ++}; ++ ++/* Global state information. ++*/ ++struct SM_STATE_T { ++ VC_VCHI_SM_HANDLE_T sm_handle; /* Handle for videocore service. */ ++ struct dentry *dir_root; /* Debug fs entries root. */ ++ struct dentry *dir_alloc; /* Debug fs entries allocations. */ ++ struct SM_PDE_T dir_stats; /* Debug fs entries statistics sub-tree. */ ++ struct SM_PDE_T dir_state; /* Debug fs entries state sub-tree. */ ++ struct dentry *debug; /* Debug fs entries debug. */ ++ ++ struct mutex map_lock; /* Global map lock. */ ++ struct list_head map_list; /* List of maps. */ ++ struct list_head resource_list; /* List of resources. */ ++ ++ enum SM_STATS_T deceased[END_ALL]; /* Natural termination stats. */ ++ enum SM_STATS_T terminated[END_ALL]; /* Forced termination stats. */ ++ uint32_t res_deceased_cnt; /* Natural termination counter. */ ++ uint32_t res_terminated_cnt; /* Forced termination counter. */ ++ ++ struct cdev sm_cdev; /* Device. */ ++ dev_t sm_devid; /* Device identifier. */ ++ struct class *sm_class; /* Class. */ ++ struct device *sm_dev; /* Device. */ ++ ++ struct SM_PRIV_DATA_T *data_knl; /* Kernel internal data tracking. */ ++ ++ struct mutex lock; /* Global lock. */ ++ uint32_t guid; /* GUID (next) tracker. */ ++ ++}; ++ ++/* ---- Private Variables ----------------------------------------------- */ ++ ++static struct SM_STATE_T *sm_state; ++static int sm_inited; ++ ++static const char *const sm_cache_map_vector[] = { ++ "(null)", ++ "host", ++ "videocore", ++ "host+videocore", ++}; ++ ++/* ---- Private Function Prototypes -------------------------------------- */ ++ ++/* ---- Private Functions ------------------------------------------------ */ ++ ++static inline unsigned vcaddr_to_pfn(unsigned long vc_addr) ++{ ++ unsigned long pfn = vc_addr & 0x3FFFFFFF; ++ pfn += mm_vc_mem_phys_addr; ++ pfn >>= PAGE_SHIFT; ++ return pfn; ++} ++ ++/* Carries over to the state statistics the statistics once owned by a deceased ++** resource. ++*/ ++static void vc_sm_resource_deceased(struct SM_RESOURCE_T *p_res, int terminated) ++{ ++ if (sm_state != NULL) { ++ if (p_res != NULL) { ++ int ix; ++ ++ if (terminated) ++ sm_state->res_terminated_cnt++; ++ else ++ sm_state->res_deceased_cnt++; ++ ++ for (ix = 0; ix < END_ALL; ix++) { ++ if (terminated) ++ sm_state->terminated[ix] += ++ p_res->res_stats[ix]; ++ else ++ sm_state->deceased[ix] += ++ p_res->res_stats[ix]; ++ } ++ } ++ } ++} ++ ++/* Fetch a videocore handle corresponding to a mapping of the pid+address ++** returns 0 (ie NULL) if no such handle exists in the global map. ++*/ ++static unsigned int vmcs_sm_vc_handle_from_pid_and_address(unsigned int pid, ++ unsigned int addr) ++{ ++ struct sm_mmap *map = NULL; ++ unsigned int handle = 0; ++ ++ if (!sm_state || addr == 0) ++ goto out; ++ ++ mutex_lock(&(sm_state->map_lock)); ++ ++ /* Lookup the resource. ++ */ ++ if (!list_empty(&sm_state->map_list)) { ++ list_for_each_entry(map, &sm_state->map_list, map_list) { ++ if (map->res_pid != pid || map->res_addr != addr) ++ continue; ++ ++ pr_debug("[%s]: global map %p (pid %u, addr %lx) -> vc-hdl %x (usr-hdl %x)\n", ++ __func__, map, map->res_pid, map->res_addr, ++ map->res_vc_hdl, map->res_usr_hdl); ++ ++ handle = map->res_vc_hdl; ++ break; ++ } ++ } ++ ++ mutex_unlock(&(sm_state->map_lock)); ++ ++out: ++ /* Use a debug log here as it may be a valid situation that we query ++ ** for something that is not mapped, we do not want a kernel log each ++ ** time around. ++ ** ++ ** There are other error log that would pop up accordingly if someone ++ ** subsequently tries to use something invalid after being told not to ++ ** use it... ++ */ ++ if (handle == 0) { ++ pr_debug("[%s]: not a valid map (pid %u, addr %x)\n", ++ __func__, pid, addr); ++ } ++ ++ return handle; ++} ++ ++/* Fetch a user handle corresponding to a mapping of the pid+address ++** returns 0 (ie NULL) if no such handle exists in the global map. ++*/ ++static unsigned int vmcs_sm_usr_handle_from_pid_and_address(unsigned int pid, ++ unsigned int addr) ++{ ++ struct sm_mmap *map = NULL; ++ unsigned int handle = 0; ++ ++ if (!sm_state || addr == 0) ++ goto out; ++ ++ mutex_lock(&(sm_state->map_lock)); ++ ++ /* Lookup the resource. ++ */ ++ if (!list_empty(&sm_state->map_list)) { ++ list_for_each_entry(map, &sm_state->map_list, map_list) { ++ if (map->res_pid != pid || map->res_addr != addr) ++ continue; ++ ++ pr_debug("[%s]: global map %p (pid %u, addr %lx) -> usr-hdl %x (vc-hdl %x)\n", ++ __func__, map, map->res_pid, map->res_addr, ++ map->res_usr_hdl, map->res_vc_hdl); ++ ++ handle = map->res_usr_hdl; ++ break; ++ } ++ } ++ ++ mutex_unlock(&(sm_state->map_lock)); ++ ++out: ++ /* Use a debug log here as it may be a valid situation that we query ++ * for something that is not mapped yet. ++ * ++ * There are other error log that would pop up accordingly if someone ++ * subsequently tries to use something invalid after being told not to ++ * use it... ++ */ ++ if (handle == 0) ++ pr_debug("[%s]: not a valid map (pid %u, addr %x)\n", ++ __func__, pid, addr); ++ ++ return handle; ++} ++ ++#if defined(DO_NOT_USE) ++/* Fetch an address corresponding to a mapping of the pid+handle ++** returns 0 (ie NULL) if no such address exists in the global map. ++*/ ++static unsigned int vmcs_sm_usr_address_from_pid_and_vc_handle(unsigned int pid, ++ unsigned int hdl) ++{ ++ struct sm_mmap *map = NULL; ++ unsigned int addr = 0; ++ ++ if (sm_state == NULL || hdl == 0) ++ goto out; ++ ++ mutex_lock(&(sm_state->map_lock)); ++ ++ /* Lookup the resource. ++ */ ++ if (!list_empty(&sm_state->map_list)) { ++ list_for_each_entry(map, &sm_state->map_list, map_list) { ++ if (map->res_pid != pid || map->res_vc_hdl != hdl) ++ continue; ++ ++ pr_debug("[%s]: global map %p (pid %u, vc-hdl %x, usr-hdl %x) -> addr %lx\n", ++ __func__, map, map->res_pid, map->res_vc_hdl, ++ map->res_usr_hdl, map->res_addr); ++ ++ addr = map->res_addr; ++ break; ++ } ++ } ++ ++ mutex_unlock(&(sm_state->map_lock)); ++ ++out: ++ /* Use a debug log here as it may be a valid situation that we query ++ ** for something that is not mapped, we do not want a kernel log each ++ ** time around. ++ ** ++ ** There are other error log that would pop up accordingly if someone ++ ** subsequently tries to use something invalid after being told not to ++ ** use it... ++ */ ++ if (addr == 0) ++ pr_debug("[%s]: not a valid map (pid %u, hdl %x)\n", ++ __func__, pid, hdl); ++ ++ return addr; ++} ++#endif ++ ++/* Fetch an address corresponding to a mapping of the pid+handle ++** returns 0 (ie NULL) if no such address exists in the global map. ++*/ ++static unsigned int vmcs_sm_usr_address_from_pid_and_usr_handle(unsigned int ++ pid, ++ unsigned int ++ hdl) ++{ ++ struct sm_mmap *map = NULL; ++ unsigned int addr = 0; ++ ++ if (sm_state == NULL || hdl == 0) ++ goto out; ++ ++ mutex_lock(&(sm_state->map_lock)); ++ ++ /* Lookup the resource. ++ */ ++ if (!list_empty(&sm_state->map_list)) { ++ list_for_each_entry(map, &sm_state->map_list, map_list) { ++ if (map->res_pid != pid || map->res_usr_hdl != hdl) ++ continue; ++ ++ pr_debug("[%s]: global map %p (pid %u, vc-hdl %x, usr-hdl %x) -> addr %lx\n", ++ __func__, map, map->res_pid, map->res_vc_hdl, ++ map->res_usr_hdl, map->res_addr); ++ ++ addr = map->res_addr; ++ break; ++ } ++ } ++ ++ mutex_unlock(&(sm_state->map_lock)); ++ ++out: ++ /* Use a debug log here as it may be a valid situation that we query ++ * for something that is not mapped, we do not want a kernel log each ++ * time around. ++ * ++ * There are other error log that would pop up accordingly if someone ++ * subsequently tries to use something invalid after being told not to ++ * use it... ++ */ ++ if (addr == 0) ++ pr_debug("[%s]: not a valid map (pid %u, hdl %x)\n", __func__, ++ pid, hdl); ++ ++ return addr; ++} ++ ++/* Adds a resource mapping to the global data list. ++*/ ++static void vmcs_sm_add_map(struct SM_STATE_T *state, ++ struct SM_RESOURCE_T *resource, struct sm_mmap *map) ++{ ++ mutex_lock(&(state->map_lock)); ++ ++ /* Add to the global list of mappings ++ */ ++ list_add(&map->map_list, &state->map_list); ++ ++ /* Add to the list of mappings for this resource ++ */ ++ list_add(&map->resource_map_list, &resource->map_list); ++ resource->map_count++; ++ ++ mutex_unlock(&(state->map_lock)); ++ ++ pr_debug("[%s]: added map %p (pid %u, vc-hdl %x, usr-hdl %x, addr %lx)\n", ++ __func__, map, map->res_pid, map->res_vc_hdl, ++ map->res_usr_hdl, map->res_addr); ++} ++ ++/* Removes a resource mapping from the global data list. ++*/ ++static void vmcs_sm_remove_map(struct SM_STATE_T *state, ++ struct SM_RESOURCE_T *resource, ++ struct sm_mmap *map) ++{ ++ mutex_lock(&(state->map_lock)); ++ ++ /* Remove from the global list of mappings ++ */ ++ list_del(&map->map_list); ++ ++ /* Remove from the list of mapping for this resource ++ */ ++ list_del(&map->resource_map_list); ++ if (resource->map_count > 0) ++ resource->map_count--; ++ ++ mutex_unlock(&(state->map_lock)); ++ ++ pr_debug("[%s]: removed map %p (pid %d, vc-hdl %x, usr-hdl %x, addr %lx)\n", ++ __func__, map, map->res_pid, map->res_vc_hdl, map->res_usr_hdl, ++ map->res_addr); ++ ++ kfree(map); ++} ++ ++/* Read callback for the global state proc entry. ++*/ ++static int vc_sm_global_state_show(struct seq_file *s, void *v) ++{ ++ struct sm_mmap *map = NULL; ++ int map_count = 0; ++ ++ if (sm_state == NULL) ++ return 0; ++ ++ seq_printf(s, "\nVC-ServiceHandle 0x%x\n", ++ (unsigned int)sm_state->sm_handle); ++ ++ /* Log all applicable mapping(s). ++ */ ++ ++ mutex_lock(&(sm_state->map_lock)); ++ ++ if (!list_empty(&sm_state->map_list)) { ++ list_for_each_entry(map, &sm_state->map_list, map_list) { ++ map_count++; ++ ++ seq_printf(s, "\nMapping 0x%x\n", ++ (unsigned int)map); ++ seq_printf(s, " TGID %u\n", ++ map->res_pid); ++ seq_printf(s, " VC-HDL 0x%x\n", ++ map->res_vc_hdl); ++ seq_printf(s, " USR-HDL 0x%x\n", ++ map->res_usr_hdl); ++ seq_printf(s, " USR-ADDR 0x%lx\n", ++ map->res_addr); ++ } ++ } ++ ++ mutex_unlock(&(sm_state->map_lock)); ++ seq_printf(s, "\n\nTotal map count: %d\n\n", map_count); ++ ++ return 0; ++} ++ ++static int vc_sm_global_statistics_show(struct seq_file *s, void *v) ++{ ++ int ix; ++ ++ /* Global state tracked statistics. ++ */ ++ if (sm_state != NULL) { ++ seq_puts(s, "\nDeceased Resources Statistics\n"); ++ ++ seq_printf(s, "\nNatural Cause (%u occurences)\n", ++ sm_state->res_deceased_cnt); ++ for (ix = 0; ix < END_ATTEMPT; ix++) { ++ if (sm_state->deceased[ix] > 0) { ++ seq_printf(s, " %u\t%s\n", ++ sm_state->deceased[ix], ++ sm_stats_human_read[ix]); ++ } ++ } ++ seq_puts(s, "\n"); ++ for (ix = 0; ix < END_ATTEMPT; ix++) { ++ if (sm_state->deceased[ix + END_ATTEMPT] > 0) { ++ seq_printf(s, " %u\tFAILED %s\n", ++ sm_state->deceased[ix + END_ATTEMPT], ++ sm_stats_human_read[ix]); ++ } ++ } ++ ++ seq_printf(s, "\nForcefull (%u occurences)\n", ++ sm_state->res_terminated_cnt); ++ for (ix = 0; ix < END_ATTEMPT; ix++) { ++ if (sm_state->terminated[ix] > 0) { ++ seq_printf(s, " %u\t%s\n", ++ sm_state->terminated[ix], ++ sm_stats_human_read[ix]); ++ } ++ } ++ seq_puts(s, "\n"); ++ for (ix = 0; ix < END_ATTEMPT; ix++) { ++ if (sm_state->terminated[ix + END_ATTEMPT] > 0) { ++ seq_printf(s, " %u\tFAILED %s\n", ++ sm_state->terminated[ix + ++ END_ATTEMPT], ++ sm_stats_human_read[ix]); ++ } ++ } ++ } ++ ++ return 0; ++} ++ ++#if 0 ++/* Read callback for the statistics proc entry. ++*/ ++static int vc_sm_statistics_show(struct seq_file *s, void *v) ++{ ++ int ix; ++ struct SM_PRIV_DATA_T *file_data; ++ struct SM_RESOURCE_T *resource; ++ int res_count = 0; ++ struct SM_PDE_T *p_pde; ++ ++ p_pde = (struct SM_PDE_T *)(s->private); ++ file_data = (struct SM_PRIV_DATA_T *)(p_pde->priv_data); ++ ++ if (file_data == NULL) ++ return 0; ++ ++ /* Per process statistics. ++ */ ++ ++ seq_printf(s, "\nStatistics for TGID %d\n", file_data->pid); ++ ++ mutex_lock(&(sm_state->map_lock)); ++ ++ if (!list_empty(&file_data->resource_list)) { ++ list_for_each_entry(resource, &file_data->resource_list, ++ resource_list) { ++ res_count++; ++ ++ seq_printf(s, "\nGUID: 0x%x\n\n", ++ resource->res_guid); ++ for (ix = 0; ix < END_ATTEMPT; ix++) { ++ if (resource->res_stats[ix] > 0) { ++ seq_printf(s, ++ " %u\t%s\n", ++ resource->res_stats[ix], ++ sm_stats_human_read[ix]); ++ } ++ } ++ seq_puts(s, "\n"); ++ for (ix = 0; ix < END_ATTEMPT; ix++) { ++ if (resource->res_stats[ix + END_ATTEMPT] > 0) { ++ seq_printf(s, ++ " %u\tFAILED %s\n", ++ resource->res_stats[ ++ ix + END_ATTEMPT], ++ sm_stats_human_read[ix]); ++ } ++ } ++ } ++ } ++ ++ mutex_unlock(&(sm_state->map_lock)); ++ ++ seq_printf(s, "\nResources Count %d\n", res_count); ++ ++ return 0; ++} ++#endif ++ ++#if 0 ++/* Read callback for the allocation proc entry. */ ++static int vc_sm_alloc_show(struct seq_file *s, void *v) ++{ ++ struct SM_PRIV_DATA_T *file_data; ++ struct SM_RESOURCE_T *resource; ++ int alloc_count = 0; ++ struct SM_PDE_T *p_pde; ++ ++ p_pde = (struct SM_PDE_T *)(s->private); ++ file_data = (struct SM_PRIV_DATA_T *)(p_pde->priv_data); ++ ++ if (!file_data) ++ return 0; ++ ++ /* Per process statistics. */ ++ seq_printf(s, "\nAllocation for TGID %d\n", file_data->pid); ++ ++ mutex_lock(&(sm_state->map_lock)); ++ ++ if (!list_empty(&file_data->resource_list)) { ++ list_for_each_entry(resource, &file_data->resource_list, ++ resource_list) { ++ alloc_count++; ++ ++ seq_printf(s, "\nGUID: 0x%x\n", ++ resource->res_guid); ++ seq_printf(s, "Lock Count: %u\n", ++ resource->lock_count); ++ seq_printf(s, "Mapped: %s\n", ++ (resource->map_count ? "yes" : "no")); ++ seq_printf(s, "VC-handle: 0x%x\n", ++ resource->res_handle); ++ seq_printf(s, "VC-address: 0x%p\n", ++ resource->res_base_mem); ++ seq_printf(s, "VC-size (bytes): %u\n", ++ resource->res_size); ++ seq_printf(s, "Cache: %s\n", ++ sm_cache_map_vector[resource->res_cached]); ++ } ++ } ++ ++ mutex_unlock(&(sm_state->map_lock)); ++ ++ seq_printf(s, "\n\nTotal allocation count: %d\n\n", alloc_count); ++ ++ return 0; ++} ++#endif ++ ++static int vc_sm_seq_file_show(struct seq_file *s, void *v) ++{ ++ struct SM_PDE_T *sm_pde; ++ ++ sm_pde = (struct SM_PDE_T *)(s->private); ++ ++ if (sm_pde && sm_pde->show) ++ sm_pde->show(s, v); ++ ++ return 0; ++} ++ ++static int vc_sm_single_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, vc_sm_seq_file_show, inode->i_private); ++} ++ ++static const struct file_operations vc_sm_debug_fs_fops = { ++ .open = vc_sm_single_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++/* Adds a resource to the private data list which tracks all the allocated ++** data. ++*/ ++static void vmcs_sm_add_resource(struct SM_PRIV_DATA_T *privdata, ++ struct SM_RESOURCE_T *resource) ++{ ++ mutex_lock(&(sm_state->map_lock)); ++ list_add(&resource->resource_list, &privdata->resource_list); ++ list_add(&resource->global_resource_list, &sm_state->resource_list); ++ mutex_unlock(&(sm_state->map_lock)); ++ ++ pr_debug("[%s]: added resource %p (base addr %p, hdl %x, size %u, cache %u)\n", ++ __func__, resource, resource->res_base_mem, ++ resource->res_handle, resource->res_size, resource->res_cached); ++} ++ ++/* Locates a resource and acquire a reference on it. ++** The resource won't be deleted while there is a reference on it. ++*/ ++static struct SM_RESOURCE_T *vmcs_sm_acquire_resource(struct SM_PRIV_DATA_T ++ *private, ++ unsigned int res_guid) ++{ ++ struct SM_RESOURCE_T *resource, *ret = NULL; ++ ++ mutex_lock(&(sm_state->map_lock)); ++ ++ list_for_each_entry(resource, &private->resource_list, resource_list) { ++ if (resource->res_guid != res_guid) ++ continue; ++ ++ pr_debug("[%s]: located resource %p (guid: %x, base addr %p, hdl %x, size %u, cache %u)\n", ++ __func__, resource, resource->res_guid, ++ resource->res_base_mem, resource->res_handle, ++ resource->res_size, resource->res_cached); ++ resource->ref_count++; ++ ret = resource; ++ break; ++ } ++ ++ mutex_unlock(&(sm_state->map_lock)); ++ ++ return ret; ++} ++ ++/* Locates a resource and acquire a reference on it. ++** The resource won't be deleted while there is a reference on it. ++*/ ++static struct SM_RESOURCE_T *vmcs_sm_acquire_first_resource( ++ struct SM_PRIV_DATA_T *private) ++{ ++ struct SM_RESOURCE_T *resource, *ret = NULL; ++ ++ mutex_lock(&(sm_state->map_lock)); ++ ++ list_for_each_entry(resource, &private->resource_list, resource_list) { ++ pr_debug("[%s]: located resource %p (guid: %x, base addr %p, hdl %x, size %u, cache %u)\n", ++ __func__, resource, resource->res_guid, ++ resource->res_base_mem, resource->res_handle, ++ resource->res_size, resource->res_cached); ++ resource->ref_count++; ++ ret = resource; ++ break; ++ } ++ ++ mutex_unlock(&(sm_state->map_lock)); ++ ++ return ret; ++} ++ ++/* Locates a resource and acquire a reference on it. ++** The resource won't be deleted while there is a reference on it. ++*/ ++static struct SM_RESOURCE_T *vmcs_sm_acquire_global_resource(unsigned int ++ res_guid) ++{ ++ struct SM_RESOURCE_T *resource, *ret = NULL; ++ ++ mutex_lock(&(sm_state->map_lock)); ++ ++ list_for_each_entry(resource, &sm_state->resource_list, ++ global_resource_list) { ++ if (resource->res_guid != res_guid) ++ continue; ++ ++ pr_debug("[%s]: located resource %p (guid: %x, base addr %p, hdl %x, size %u, cache %u)\n", ++ __func__, resource, resource->res_guid, ++ resource->res_base_mem, resource->res_handle, ++ resource->res_size, resource->res_cached); ++ resource->ref_count++; ++ ret = resource; ++ break; ++ } ++ ++ mutex_unlock(&(sm_state->map_lock)); ++ ++ return ret; ++} ++ ++/* Release a previously acquired resource. ++** The resource will be deleted when its refcount reaches 0. ++*/ ++static void vmcs_sm_release_resource(struct SM_RESOURCE_T *resource, int force) ++{ ++ struct SM_PRIV_DATA_T *private = resource->private; ++ struct sm_mmap *map, *map_tmp; ++ struct SM_RESOURCE_T *res_tmp; ++ int ret; ++ ++ mutex_lock(&(sm_state->map_lock)); ++ ++ if (--resource->ref_count) { ++ if (force) ++ pr_err("[%s]: resource %p in use\n", __func__, resource); ++ ++ mutex_unlock(&(sm_state->map_lock)); ++ return; ++ } ++ ++ /* Time to free the resource. Start by removing it from the list */ ++ list_del(&resource->resource_list); ++ list_del(&resource->global_resource_list); ++ ++ /* Walk the global resource list, find out if the resource is used ++ * somewhere else. In which case we don't want to delete it. ++ */ ++ list_for_each_entry(res_tmp, &sm_state->resource_list, ++ global_resource_list) { ++ if (res_tmp->res_handle == resource->res_handle) { ++ resource->res_handle = 0; ++ break; ++ } ++ } ++ ++ mutex_unlock(&(sm_state->map_lock)); ++ ++ pr_debug("[%s]: freeing data - guid %x, hdl %x, base address %p\n", ++ __func__, resource->res_guid, resource->res_handle, ++ resource->res_base_mem); ++ resource->res_stats[FREE]++; ++ ++ /* Make sure the resource we're removing is unmapped first */ ++ if (resource->map_count && !list_empty(&resource->map_list)) { ++ down_write(¤t->mm->mmap_sem); ++ list_for_each_entry_safe(map, map_tmp, &resource->map_list, ++ resource_map_list) { ++ ret = ++ do_munmap(current->mm, map->res_addr, ++ resource->res_size); ++ if (ret) { ++ pr_err("[%s]: could not unmap resource %p\n", ++ __func__, resource); ++ } ++ } ++ up_write(¤t->mm->mmap_sem); ++ } ++ ++ /* Free up the videocore allocated resource. ++ */ ++ if (resource->res_handle) { ++ VC_SM_FREE_T free = { ++ resource->res_handle, resource->res_base_mem ++ }; ++ int status = vc_vchi_sm_free(sm_state->sm_handle, &free, ++ &private->int_trans_id); ++ if (status != 0 && status != -EINTR) { ++ pr_err("[%s]: failed to free memory on videocore (status: %u, trans_id: %u)\n", ++ __func__, status, private->int_trans_id); ++ resource->res_stats[FREE_FAIL]++; ++ ret = -EPERM; ++ } ++ } ++ ++ /* Free up the shared resource. ++ */ ++ if (resource->res_shared) ++ vmcs_sm_release_resource(resource->res_shared, 0); ++ ++ /* Free up the local resource tracking this allocation. ++ */ ++ vc_sm_resource_deceased(resource, force); ++ kfree(resource); ++} ++ ++/* Dump the map table for the driver. If process is -1, dumps the whole table, ++** if process is a valid pid (non -1) dump only the entries associated with the ++** pid of interest. ++*/ ++static void vmcs_sm_host_walk_map_per_pid(int pid) ++{ ++ struct sm_mmap *map = NULL; ++ ++ /* Make sure the device was started properly. ++ */ ++ if (sm_state == NULL) { ++ pr_err("[%s]: invalid device\n", __func__); ++ return; ++ } ++ ++ mutex_lock(&(sm_state->map_lock)); ++ ++ /* Log all applicable mapping(s). ++ */ ++ if (!list_empty(&sm_state->map_list)) { ++ list_for_each_entry(map, &sm_state->map_list, map_list) { ++ if (pid == -1 || map->res_pid == pid) { ++ pr_info("[%s]: tgid: %u - vc-hdl: %x, usr-hdl: %x, usr-addr: %lx\n", ++ __func__, map->res_pid, map->res_vc_hdl, ++ map->res_usr_hdl, map->res_addr); ++ } ++ } ++ } ++ ++ mutex_unlock(&(sm_state->map_lock)); ++ ++ return; ++} ++ ++/* Dump the allocation table from host side point of view. This only dumps the ++** data allocated for this process/device referenced by the file_data. ++*/ ++static void vmcs_sm_host_walk_alloc(struct SM_PRIV_DATA_T *file_data) ++{ ++ struct SM_RESOURCE_T *resource = NULL; ++ ++ /* Make sure the device was started properly. ++ */ ++ if ((sm_state == NULL) || (file_data == NULL)) { ++ pr_err("[%s]: invalid device\n", __func__); ++ return; ++ } ++ ++ mutex_lock(&(sm_state->map_lock)); ++ ++ if (!list_empty(&file_data->resource_list)) { ++ list_for_each_entry(resource, &file_data->resource_list, ++ resource_list) { ++ pr_info("[%s]: guid: %x - hdl: %x, vc-mem: %p, size: %u, cache: %u\n", ++ __func__, resource->res_guid, resource->res_handle, ++ resource->res_base_mem, resource->res_size, ++ resource->res_cached); ++ } ++ } ++ ++ mutex_unlock(&(sm_state->map_lock)); ++ ++ return; ++} ++ ++/* Create support for private data tracking. ++*/ ++static struct SM_PRIV_DATA_T *vc_sm_create_priv_data(pid_t id) ++{ ++ char alloc_name[32]; ++ struct SM_PRIV_DATA_T *file_data = NULL; ++ ++ /* Allocate private structure. */ ++ file_data = kzalloc(sizeof(*file_data), GFP_KERNEL); ++ ++ if (!file_data) { ++ pr_err("[%s]: cannot allocate file data\n", __func__); ++ goto out; ++ } ++ ++ snprintf(alloc_name, sizeof(alloc_name), "%d", id); ++ ++ INIT_LIST_HEAD(&file_data->resource_list); ++ file_data->pid = id; ++ file_data->dir_pid = debugfs_create_dir(alloc_name, ++ sm_state->dir_alloc); ++#if 0 ++ /* TODO: fix this to support querying statistics per pid */ ++ ++ if (IS_ERR_OR_NULL(file_data->dir_pid)) { ++ file_data->dir_pid = NULL; ++ } else { ++ struct dentry *dir_entry; ++ ++ dir_entry = debugfs_create_file(VC_SM_RESOURCES, S_IRUGO, ++ file_data->dir_pid, file_data, ++ vc_sm_debug_fs_fops); ++ ++ file_data->dir_res.dir_entry = dir_entry; ++ file_data->dir_res.priv_data = file_data; ++ file_data->dir_res.show = &vc_sm_alloc_show; ++ ++ dir_entry = debugfs_create_file(VC_SM_STATS, S_IRUGO, ++ file_data->dir_pid, file_data, ++ vc_sm_debug_fs_fops); ++ ++ file_data->dir_res.dir_entry = dir_entry; ++ file_data->dir_res.priv_data = file_data; ++ file_data->dir_res.show = &vc_sm_statistics_show; ++ } ++ pr_debug("[%s]: private data allocated %p\n", __func__, file_data); ++ ++#endif ++out: ++ return file_data; ++} ++ ++/* Open the device. Creates a private state to help track all allocation ++** associated with this device. ++*/ ++static int vc_sm_open(struct inode *inode, struct file *file) ++{ ++ int ret = 0; ++ ++ /* Make sure the device was started properly. ++ */ ++ if (!sm_state) { ++ pr_err("[%s]: invalid device\n", __func__); ++ ret = -EPERM; ++ goto out; ++ } ++ ++ file->private_data = vc_sm_create_priv_data(current->tgid); ++ if (file->private_data == NULL) { ++ pr_err("[%s]: failed to create data tracker\n", __func__); ++ ++ ret = -ENOMEM; ++ goto out; ++ } ++ ++out: ++ return ret; ++} ++ ++/* Close the device. Free up all resources still associated with this device ++** at the time. ++*/ ++static int vc_sm_release(struct inode *inode, struct file *file) ++{ ++ struct SM_PRIV_DATA_T *file_data = ++ (struct SM_PRIV_DATA_T *)file->private_data; ++ struct SM_RESOURCE_T *resource; ++ int ret = 0; ++ ++ /* Make sure the device was started properly. ++ */ ++ if (sm_state == NULL || file_data == NULL) { ++ pr_err("[%s]: invalid device\n", __func__); ++ ret = -EPERM; ++ goto out; ++ } ++ ++ pr_debug("[%s]: using private data %p\n", __func__, file_data); ++ ++ if (file_data->restart_sys == -EINTR) { ++ VC_SM_ACTION_CLEAN_T action_clean; ++ ++ pr_debug("[%s]: releasing following EINTR on %u (trans_id: %u) (likely due to signal)...\n", ++ __func__, file_data->int_action, ++ file_data->int_trans_id); ++ ++ action_clean.res_action = file_data->int_action; ++ action_clean.action_trans_id = file_data->int_trans_id; ++ ++ vc_vchi_sm_clean_up(sm_state->sm_handle, &action_clean); ++ } ++ ++ while ((resource = vmcs_sm_acquire_first_resource(file_data)) != NULL) { ++ vmcs_sm_release_resource(resource, 0); ++ vmcs_sm_release_resource(resource, 1); ++ } ++ ++ /* Remove the corresponding proc entry. */ ++ debugfs_remove_recursive(file_data->dir_pid); ++ ++ /* Terminate the private data. ++ */ ++ kfree(file_data); ++ ++out: ++ return ret; ++} ++ ++static void vcsm_vma_open(struct vm_area_struct *vma) ++{ ++ struct sm_mmap *map = (struct sm_mmap *)vma->vm_private_data; ++ ++ pr_debug("[%s]: virt %lx-%lx, pid %i, pfn %i\n", ++ __func__, vma->vm_start, vma->vm_end, (int)current->tgid, ++ (int)vma->vm_pgoff); ++ ++ map->ref_count++; ++} ++ ++static void vcsm_vma_close(struct vm_area_struct *vma) ++{ ++ struct sm_mmap *map = (struct sm_mmap *)vma->vm_private_data; ++ ++ pr_debug("[%s]: virt %lx-%lx, pid %i, pfn %i\n", ++ __func__, vma->vm_start, vma->vm_end, (int)current->tgid, ++ (int)vma->vm_pgoff); ++ ++ map->ref_count--; ++ ++ /* Remove from the map table. ++ */ ++ if (map->ref_count == 0) ++ vmcs_sm_remove_map(sm_state, map->resource, map); ++} ++ ++static int vcsm_vma_fault(struct vm_area_struct *vma, struct vm_fault *vmf) ++{ ++ struct sm_mmap *map = (struct sm_mmap *)vma->vm_private_data; ++ struct SM_RESOURCE_T *resource = map->resource; ++ pgoff_t page_offset; ++ unsigned long pfn; ++ int ret = 0; ++ ++ /* Lock the resource if necessary. ++ */ ++ if (!resource->lock_count) { ++ VC_SM_LOCK_UNLOCK_T lock_unlock; ++ VC_SM_LOCK_RESULT_T lock_result; ++ int status; ++ ++ lock_unlock.res_handle = resource->res_handle; ++ lock_unlock.res_mem = resource->res_base_mem; ++ ++ pr_debug("[%s]: attempt to lock data - hdl %x, base address %p\n", ++ __func__, lock_unlock.res_handle, lock_unlock.res_mem); ++ ++ /* Lock the videocore allocated resource. ++ */ ++ status = vc_vchi_sm_lock(sm_state->sm_handle, ++ &lock_unlock, &lock_result, 0); ++ if ((status != 0) || ++ ((status == 0) && (lock_result.res_mem == NULL))) { ++ pr_err("[%s]: failed to lock memory on videocore (status: %u)\n", ++ __func__, status); ++ resource->res_stats[LOCK_FAIL]++; ++ return VM_FAULT_SIGBUS; ++ } ++ ++ pfn = vcaddr_to_pfn((unsigned long)resource->res_base_mem); ++ outer_inv_range(__pfn_to_phys(pfn), ++ __pfn_to_phys(pfn) + resource->res_size); ++ ++ resource->res_stats[LOCK]++; ++ resource->lock_count++; ++ ++ /* Keep track of the new base memory. ++ */ ++ if ((lock_result.res_mem != NULL) && ++ (lock_result.res_old_mem != NULL) && ++ (lock_result.res_mem != lock_result.res_old_mem)) { ++ resource->res_base_mem = lock_result.res_mem; ++ } ++ } ++ ++ /* We don't use vmf->pgoff since that has the fake offset */ ++ page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start); ++ pfn = (uint32_t)resource->res_base_mem & 0x3FFFFFFF; ++ pfn += mm_vc_mem_phys_addr; ++ pfn += page_offset; ++ pfn >>= PAGE_SHIFT; ++ ++ /* Finally, remap it */ ++ ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); ++ ++ switch (ret) { ++ case 0: ++ case -ERESTARTSYS: ++ return VM_FAULT_NOPAGE; ++ case -ENOMEM: ++ case -EAGAIN: ++ return VM_FAULT_OOM; ++ default: ++ return VM_FAULT_SIGBUS; ++ } ++} ++ ++static struct vm_operations_struct vcsm_vm_ops = { ++ .open = vcsm_vma_open, ++ .close = vcsm_vma_close, ++ .fault = vcsm_vma_fault, ++}; ++ ++/* Walks a VMA and clean each valid page from the cache */ ++static void vcsm_vma_cache_clean_page_range(unsigned long addr, ++ unsigned long end) ++{ ++ pgd_t *pgd; ++ pud_t *pud; ++ pmd_t *pmd; ++ pte_t *pte; ++ unsigned long pgd_next, pud_next, pmd_next; ++ ++ if (addr >= end) ++ return; ++ ++ /* Walk PGD */ ++ pgd = pgd_offset(current->mm, addr); ++ do { ++ pgd_next = pgd_addr_end(addr, end); ++ ++ if (pgd_none(*pgd) || pgd_bad(*pgd)) ++ continue; ++ ++ /* Walk PUD */ ++ pud = pud_offset(pgd, addr); ++ do { ++ pud_next = pud_addr_end(addr, pgd_next); ++ if (pud_none(*pud) || pud_bad(*pud)) ++ continue; ++ ++ /* Walk PMD */ ++ pmd = pmd_offset(pud, addr); ++ do { ++ pmd_next = pmd_addr_end(addr, pud_next); ++ if (pmd_none(*pmd) || pmd_bad(*pmd)) ++ continue; ++ ++ /* Walk PTE */ ++ pte = pte_offset_map(pmd, addr); ++ do { ++ if (pte_none(*pte) ++ || !pte_present(*pte)) ++ continue; ++ ++ /* Clean + invalidate */ ++ dmac_flush_range((const void *) addr, ++ (const void *) ++ (addr + PAGE_SIZE)); ++ ++ } while (pte++, addr += ++ PAGE_SIZE, addr != pmd_next); ++ pte_unmap(pte); ++ ++ } while (pmd++, addr = pmd_next, addr != pud_next); ++ ++ } while (pud++, addr = pud_next, addr != pgd_next); ++ } while (pgd++, addr = pgd_next, addr != end); ++} ++ ++/* Map an allocated data into something that the user space. ++*/ ++static int vc_sm_mmap(struct file *file, struct vm_area_struct *vma) ++{ ++ int ret = 0; ++ struct SM_PRIV_DATA_T *file_data = ++ (struct SM_PRIV_DATA_T *)file->private_data; ++ struct SM_RESOURCE_T *resource = NULL; ++ struct sm_mmap *map = NULL; ++ ++ /* Make sure the device was started properly. ++ */ ++ if ((sm_state == NULL) || (file_data == NULL)) { ++ pr_err("[%s]: invalid device\n", __func__); ++ return -EPERM; ++ } ++ ++ pr_debug("[%s]: private data %p, guid %x\n", __func__, file_data, ++ ((unsigned int)vma->vm_pgoff << PAGE_SHIFT)); ++ ++ /* We lookup to make sure that the data we are being asked to mmap is ++ ** something that we allocated. ++ ** ++ ** We use the offset information as the key to tell us which resource ++ ** we are mapping. ++ */ ++ resource = vmcs_sm_acquire_resource(file_data, ++ ((unsigned int)vma->vm_pgoff << ++ PAGE_SHIFT)); ++ if (resource == NULL) { ++ pr_err("[%s]: failed to locate resource for guid %x\n", __func__, ++ ((unsigned int)vma->vm_pgoff << PAGE_SHIFT)); ++ return -ENOMEM; ++ } ++ ++ pr_debug("[%s]: guid %x, tgid %u, %u, %u\n", ++ __func__, resource->res_guid, current->tgid, resource->pid, ++ file_data->pid); ++ ++ /* Check permissions. ++ */ ++ if (resource->pid && (resource->pid != current->tgid)) { ++ pr_err("[%s]: current tgid %u != %u owner\n", ++ __func__, current->tgid, resource->pid); ++ ret = -EPERM; ++ goto error; ++ } ++ ++ /* Verify that what we are asked to mmap is proper. ++ */ ++ if (resource->res_size != (unsigned int)(vma->vm_end - vma->vm_start)) { ++ pr_err("[%s]: size inconsistency (resource: %u - mmap: %u)\n", ++ __func__, ++ resource->res_size, ++ (unsigned int)(vma->vm_end - vma->vm_start)); ++ ++ ret = -EINVAL; ++ goto error; ++ } ++ ++ /* Keep track of the tuple in the global resource list such that one ++ * can do a mapping lookup for address/memory handle. ++ */ ++ map = kzalloc(sizeof(*map), GFP_KERNEL); ++ if (map == NULL) { ++ pr_err("[%s]: failed to allocate global tracking resource\n", ++ __func__); ++ ret = -ENOMEM; ++ goto error; ++ } ++ ++ map->res_pid = current->tgid; ++ map->res_vc_hdl = resource->res_handle; ++ map->res_usr_hdl = resource->res_guid; ++ map->res_addr = (long unsigned int)vma->vm_start; ++ map->resource = resource; ++ map->vma = vma; ++ vmcs_sm_add_map(sm_state, resource, map); ++ ++ /* We are not actually mapping the pages, we just provide a fault ++ ** handler to allow pages to be mapped when accessed ++ */ ++ vma->vm_flags |= ++ VM_IO | VM_PFNMAP | VM_DONTCOPY | VM_DONTEXPAND; ++ vma->vm_ops = &vcsm_vm_ops; ++ vma->vm_private_data = map; ++ ++ /* vm_pgoff is the first PFN of the mapped memory */ ++ vma->vm_pgoff = (unsigned long)resource->res_base_mem & 0x3FFFFFFF; ++ vma->vm_pgoff += mm_vc_mem_phys_addr; ++ vma->vm_pgoff >>= PAGE_SHIFT; ++ ++ if ((resource->res_cached == VMCS_SM_CACHE_NONE) || ++ (resource->res_cached == VMCS_SM_CACHE_VC)) { ++ /* Allocated non host cached memory, honour it. ++ */ ++ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); ++ } ++ ++ pr_debug("[%s]: resource %p (guid %x) - cnt %u, base address %p, handle %x, size %u (%u), cache %u\n", ++ __func__, ++ resource, resource->res_guid, resource->lock_count, ++ resource->res_base_mem, resource->res_handle, ++ resource->res_size, (unsigned int)(vma->vm_end - vma->vm_start), ++ resource->res_cached); ++ ++ pr_debug("[%s]: resource %p (base address %p, handle %x) - map-count %d, usr-addr %x\n", ++ __func__, resource, resource->res_base_mem, ++ resource->res_handle, resource->map_count, ++ (unsigned int)vma->vm_start); ++ ++ vcsm_vma_open(vma); ++ resource->res_stats[MAP]++; ++ vmcs_sm_release_resource(resource, 0); ++ return 0; ++ ++error: ++ resource->res_stats[MAP_FAIL]++; ++ vmcs_sm_release_resource(resource, 0); ++ return ret; ++} ++ ++/* Allocate a shared memory handle and block. ++*/ ++int vc_sm_ioctl_alloc(struct SM_PRIV_DATA_T *private, ++ struct vmcs_sm_ioctl_alloc *ioparam) ++{ ++ int ret = 0; ++ int status; ++ struct SM_RESOURCE_T *resource; ++ VC_SM_ALLOC_T alloc = { 0 }; ++ VC_SM_ALLOC_RESULT_T result = { 0 }; ++ ++ /* Setup our allocation parameters */ ++ alloc.type = ((ioparam->cached == VMCS_SM_CACHE_VC) ++ || (ioparam->cached == ++ VMCS_SM_CACHE_BOTH)) ? VC_SM_ALLOC_CACHED : ++ VC_SM_ALLOC_NON_CACHED; ++ alloc.base_unit = ioparam->size; ++ alloc.num_unit = ioparam->num; ++ alloc.allocator = current->tgid; ++ /* Align to kernel page size */ ++ alloc.alignement = 4096; ++ /* Align the size to the kernel page size */ ++ alloc.base_unit = ++ (alloc.base_unit + alloc.alignement - 1) & ~(alloc.alignement - 1); ++ if (*ioparam->name) { ++ memcpy(alloc.name, ioparam->name, sizeof(alloc.name) - 1); ++ } else { ++ memcpy(alloc.name, VMCS_SM_RESOURCE_NAME_DEFAULT, ++ sizeof(VMCS_SM_RESOURCE_NAME_DEFAULT)); ++ } ++ ++ pr_debug("[%s]: attempt to allocate \"%s\" data - type %u, base %u (%u), num %u, alignement %u\n", ++ __func__, alloc.name, alloc.type, ioparam->size, ++ alloc.base_unit, alloc.num_unit, alloc.alignement); ++ ++ /* Allocate local resource to track this allocation. ++ */ ++ resource = kzalloc(sizeof(*resource), GFP_KERNEL); ++ if (!resource) { ++ ret = -ENOMEM; ++ goto error; ++ } ++ INIT_LIST_HEAD(&resource->map_list); ++ resource->ref_count++; ++ resource->pid = current->tgid; ++ ++ /* Allocate the videocore resource. ++ */ ++ status = vc_vchi_sm_alloc(sm_state->sm_handle, &alloc, &result, ++ &private->int_trans_id); ++ if (status == -EINTR) { ++ pr_debug("[%s]: requesting allocate memory action restart (trans_id: %u)\n", ++ __func__, private->int_trans_id); ++ ret = -ERESTARTSYS; ++ private->restart_sys = -EINTR; ++ private->int_action = VC_SM_MSG_TYPE_ALLOC; ++ goto error; ++ } else if (status != 0 || (status == 0 && result.res_mem == NULL)) { ++ pr_err("[%s]: failed to allocate memory on videocore (status: %u, trans_id: %u)\n", ++ __func__, status, private->int_trans_id); ++ ret = -ENOMEM; ++ resource->res_stats[ALLOC_FAIL]++; ++ goto error; ++ } ++ ++ /* Keep track of the resource we created. ++ */ ++ resource->private = private; ++ resource->res_handle = result.res_handle; ++ resource->res_base_mem = result.res_mem; ++ resource->res_size = alloc.base_unit * alloc.num_unit; ++ resource->res_cached = ioparam->cached; ++ ++ /* Kernel/user GUID. This global identifier is used for mmap'ing the ++ * allocated region from user space, it is passed as the mmap'ing ++ * offset, we use it to 'hide' the videocore handle/address. ++ */ ++ mutex_lock(&sm_state->lock); ++ resource->res_guid = ++sm_state->guid; ++ mutex_unlock(&sm_state->lock); ++ resource->res_guid <<= PAGE_SHIFT; ++ ++ vmcs_sm_add_resource(private, resource); ++ ++ pr_debug("[%s]: allocated data - guid %x, hdl %x, base address %p, size %d, cache %d\n", ++ __func__, resource->res_guid, resource->res_handle, ++ resource->res_base_mem, resource->res_size, ++ resource->res_cached); ++ ++ /* We're done */ ++ resource->res_stats[ALLOC]++; ++ ioparam->handle = resource->res_guid; ++ return 0; ++ ++error: ++ pr_err("[%s]: failed to allocate \"%s\" data (%i) - type %u, base %u (%u), num %u, alignment %u\n", ++ __func__, alloc.name, ret, alloc.type, ioparam->size, ++ alloc.base_unit, alloc.num_unit, alloc.alignement); ++ if (resource != NULL) { ++ vc_sm_resource_deceased(resource, 1); ++ kfree(resource); ++ } ++ return ret; ++} ++ ++/* Share an allocate memory handle and block. ++*/ ++int vc_sm_ioctl_alloc_share(struct SM_PRIV_DATA_T *private, ++ struct vmcs_sm_ioctl_alloc_share *ioparam) ++{ ++ struct SM_RESOURCE_T *resource, *shared_resource; ++ int ret = 0; ++ ++ pr_debug("[%s]: attempt to share resource %u\n", __func__, ++ ioparam->handle); ++ ++ shared_resource = vmcs_sm_acquire_global_resource(ioparam->handle); ++ if (shared_resource == NULL) { ++ ret = -ENOMEM; ++ goto error; ++ } ++ ++ /* Allocate local resource to track this allocation. ++ */ ++ resource = kzalloc(sizeof(*resource), GFP_KERNEL); ++ if (resource == NULL) { ++ pr_err("[%s]: failed to allocate local tracking resource\n", ++ __func__); ++ ret = -ENOMEM; ++ goto error; ++ } ++ INIT_LIST_HEAD(&resource->map_list); ++ resource->ref_count++; ++ resource->pid = current->tgid; ++ ++ /* Keep track of the resource we created. ++ */ ++ resource->private = private; ++ resource->res_handle = shared_resource->res_handle; ++ resource->res_base_mem = shared_resource->res_base_mem; ++ resource->res_size = shared_resource->res_size; ++ resource->res_cached = shared_resource->res_cached; ++ resource->res_shared = shared_resource; ++ ++ mutex_lock(&sm_state->lock); ++ resource->res_guid = ++sm_state->guid; ++ mutex_unlock(&sm_state->lock); ++ resource->res_guid <<= PAGE_SHIFT; ++ ++ vmcs_sm_add_resource(private, resource); ++ ++ pr_debug("[%s]: allocated data - guid %x, hdl %x, base address %p, size %d, cache %d\n", ++ __func__, resource->res_guid, resource->res_handle, ++ resource->res_base_mem, resource->res_size, ++ resource->res_cached); ++ ++ /* We're done */ ++ resource->res_stats[ALLOC]++; ++ ioparam->handle = resource->res_guid; ++ ioparam->size = resource->res_size; ++ return 0; ++ ++error: ++ pr_err("[%s]: failed to share %u\n", __func__, ioparam->handle); ++ if (shared_resource != NULL) ++ vmcs_sm_release_resource(shared_resource, 0); ++ ++ return ret; ++} ++ ++/* Free a previously allocated shared memory handle and block. ++*/ ++static int vc_sm_ioctl_free(struct SM_PRIV_DATA_T *private, ++ struct vmcs_sm_ioctl_free *ioparam) ++{ ++ struct SM_RESOURCE_T *resource = ++ vmcs_sm_acquire_resource(private, ioparam->handle); ++ ++ if (resource == NULL) { ++ pr_err("[%s]: resource for guid %u does not exist\n", __func__, ++ ioparam->handle); ++ return -EINVAL; ++ } ++ ++ /* Check permissions. ++ */ ++ if (resource->pid && (resource->pid != current->tgid)) { ++ pr_err("[%s]: current tgid %u != %u owner\n", ++ __func__, current->tgid, resource->pid); ++ vmcs_sm_release_resource(resource, 0); ++ return -EPERM; ++ } ++ ++ vmcs_sm_release_resource(resource, 0); ++ vmcs_sm_release_resource(resource, 0); ++ return 0; ++} ++ ++/* Resize a previously allocated shared memory handle and block. ++*/ ++static int vc_sm_ioctl_resize(struct SM_PRIV_DATA_T *private, ++ struct vmcs_sm_ioctl_resize *ioparam) ++{ ++ int ret = 0; ++ int status; ++ VC_SM_RESIZE_T resize; ++ struct SM_RESOURCE_T *resource; ++ ++ /* Locate resource from GUID. ++ */ ++ resource = vmcs_sm_acquire_resource(private, ioparam->handle); ++ if (!resource) { ++ pr_err("[%s]: failed resource - guid %x\n", ++ __func__, ioparam->handle); ++ ret = -EFAULT; ++ goto error; ++ } ++ ++ /* If the resource is locked, its reference count will be not NULL, ++ ** in which case we will not be allowed to resize it anyways, so ++ ** reject the attempt here. ++ */ ++ if (resource->lock_count != 0) { ++ pr_err("[%s]: cannot resize - guid %x, ref-cnt %d\n", ++ __func__, ioparam->handle, resource->lock_count); ++ ret = -EFAULT; ++ goto error; ++ } ++ ++ /* Check permissions. ++ */ ++ if (resource->pid && (resource->pid != current->tgid)) { ++ pr_err("[%s]: current tgid %u != %u owner\n", __func__, ++ current->tgid, resource->pid); ++ ret = -EPERM; ++ goto error; ++ } ++ ++ if (resource->map_count != 0) { ++ pr_err("[%s]: cannot resize - guid %x, ref-cnt %d\n", ++ __func__, ioparam->handle, resource->map_count); ++ ret = -EFAULT; ++ goto error; ++ } ++ ++ resize.res_handle = resource->res_handle; ++ resize.res_mem = resource->res_base_mem; ++ resize.res_new_size = ioparam->new_size; ++ ++ pr_debug("[%s]: attempt to resize data - guid %x, hdl %x, base address %p\n", ++ __func__, ioparam->handle, resize.res_handle, resize.res_mem); ++ ++ /* Resize the videocore allocated resource. ++ */ ++ status = vc_vchi_sm_resize(sm_state->sm_handle, &resize, ++ &private->int_trans_id); ++ if (status == -EINTR) { ++ pr_debug("[%s]: requesting resize memory action restart (trans_id: %u)\n", ++ __func__, private->int_trans_id); ++ ret = -ERESTARTSYS; ++ private->restart_sys = -EINTR; ++ private->int_action = VC_SM_MSG_TYPE_RESIZE; ++ goto error; ++ } else if (status != 0) { ++ pr_err("[%s]: failed to resize memory on videocore (status: %u, trans_id: %u)\n", ++ __func__, status, private->int_trans_id); ++ ret = -EPERM; ++ goto error; ++ } ++ ++ pr_debug("[%s]: success to resize data - hdl %x, size %d -> %d\n", ++ __func__, resize.res_handle, resource->res_size, ++ resize.res_new_size); ++ ++ /* Successfully resized, save the information and inform the user. ++ */ ++ ioparam->old_size = resource->res_size; ++ resource->res_size = resize.res_new_size; ++ ++error: ++ if (resource) ++ vmcs_sm_release_resource(resource, 0); ++ ++ return ret; ++} ++ ++/* Lock a previously allocated shared memory handle and block. ++*/ ++static int vc_sm_ioctl_lock(struct SM_PRIV_DATA_T *private, ++ struct vmcs_sm_ioctl_lock_unlock *ioparam, ++ int change_cache, enum vmcs_sm_cache_e cache_type, ++ unsigned int vc_addr) ++{ ++ int status; ++ VC_SM_LOCK_UNLOCK_T lock; ++ VC_SM_LOCK_RESULT_T result; ++ struct SM_RESOURCE_T *resource; ++ int ret = 0; ++ struct sm_mmap *map, *map_tmp; ++ long unsigned int phys_addr; ++ ++ map = NULL; ++ ++ /* Locate resource from GUID. ++ */ ++ resource = vmcs_sm_acquire_resource(private, ioparam->handle); ++ if (resource == NULL) { ++ ret = -EINVAL; ++ goto error; ++ } ++ ++ /* Check permissions. ++ */ ++ if (resource->pid && (resource->pid != current->tgid)) { ++ pr_err("[%s]: current tgid %u != %u owner\n", __func__, ++ current->tgid, resource->pid); ++ ret = -EPERM; ++ goto error; ++ } ++ ++ lock.res_handle = resource->res_handle; ++ lock.res_mem = resource->res_base_mem; ++ ++ /* Take the lock and get the address to be mapped. ++ */ ++ if (vc_addr == 0) { ++ pr_debug("[%s]: attempt to lock data - guid %x, hdl %x, base address %p\n", ++ __func__, ioparam->handle, lock.res_handle, ++ lock.res_mem); ++ ++ /* Lock the videocore allocated resource. ++ */ ++ status = vc_vchi_sm_lock(sm_state->sm_handle, &lock, &result, ++ &private->int_trans_id); ++ if (status == -EINTR) { ++ pr_debug("[%s]: requesting lock memory action restart (trans_id: %u)\n", ++ __func__, private->int_trans_id); ++ ret = -ERESTARTSYS; ++ private->restart_sys = -EINTR; ++ private->int_action = VC_SM_MSG_TYPE_LOCK; ++ goto error; ++ } else if (status != 0 || ++ (status == 0 && result.res_mem == NULL)) { ++ pr_err("[%s]: failed to lock memory on videocore (status: %u, trans_id: %u)\n", ++ __func__, status, private->int_trans_id); ++ ret = -EPERM; ++ resource->res_stats[LOCK_FAIL]++; ++ goto error; ++ } ++ ++ pr_debug("[%s]: succeed to lock data - hdl %x, base address %p (%p), ref-cnt %d\n", ++ __func__, lock.res_handle, result.res_mem, ++ lock.res_mem, resource->lock_count); ++ } ++ /* Lock assumed taken already, address to be mapped is known. ++ */ ++ else ++ resource->res_base_mem = (void *)vc_addr; ++ ++ resource->res_stats[LOCK]++; ++ resource->lock_count++; ++ ++ /* Keep track of the new base memory allocation if it has changed. ++ */ ++ if ((vc_addr == 0) && ++ (result.res_mem != NULL) && ++ (result.res_old_mem != NULL) && ++ (result.res_mem != result.res_old_mem)) { ++ resource->res_base_mem = result.res_mem; ++ ++ /* Kernel allocated resources. ++ */ ++ if (resource->pid == 0) { ++ if (!list_empty(&resource->map_list)) { ++ list_for_each_entry_safe(map, map_tmp, ++ &resource->map_list, ++ resource_map_list) { ++ if (map->res_addr) { ++ iounmap((void *)map->res_addr); ++ map->res_addr = 0; ++ ++ vmcs_sm_remove_map(sm_state, ++ map->resource, ++ map); ++ break; ++ } ++ } ++ } ++ } ++ } ++ ++ if (change_cache) ++ resource->res_cached = cache_type; ++ ++ if (resource->map_count) { ++ ioparam->addr = ++ vmcs_sm_usr_address_from_pid_and_usr_handle( ++ current->tgid, ioparam->handle); ++ ++ pr_debug("[%s] map_count %d private->pid %d current->tgid %d hnd %x addr %u\n", ++ __func__, resource->map_count, private->pid, ++ current->tgid, ioparam->handle, ioparam->addr); ++ } else { ++ /* Kernel allocated resources. ++ */ ++ if (resource->pid == 0) { ++ pr_debug("[%s]: attempt mapping kernel resource - guid %x, hdl %x\n", ++ __func__, ioparam->handle, lock.res_handle); ++ ++ ioparam->addr = 0; ++ ++ map = kzalloc(sizeof(*map), GFP_KERNEL); ++ if (map == NULL) { ++ pr_err("[%s]: failed allocating tracker\n", ++ __func__); ++ ret = -ENOMEM; ++ goto error; ++ } else { ++ phys_addr = (uint32_t)resource->res_base_mem & ++ 0x3FFFFFFF; ++ phys_addr += mm_vc_mem_phys_addr; ++ if (resource->res_cached ++ == VMCS_SM_CACHE_HOST) { ++ ioparam->addr = (long unsigned int) ++ /* TODO - make cached work */ ++ ioremap_nocache(phys_addr, ++ resource->res_size); ++ ++ pr_debug("[%s]: mapping kernel - guid %x, hdl %x - cached mapping %u\n", ++ __func__, ioparam->handle, ++ lock.res_handle, ioparam->addr); ++ } else { ++ ioparam->addr = (long unsigned int) ++ ioremap_nocache(phys_addr, ++ resource->res_size); ++ ++ pr_debug("[%s]: mapping kernel- guid %x, hdl %x - non cached mapping %u\n", ++ __func__, ioparam->handle, ++ lock.res_handle, ioparam->addr); ++ } ++ ++ map->res_pid = 0; ++ map->res_vc_hdl = resource->res_handle; ++ map->res_usr_hdl = resource->res_guid; ++ map->res_addr = ioparam->addr; ++ map->resource = resource; ++ map->vma = NULL; ++ ++ vmcs_sm_add_map(sm_state, resource, map); ++ } ++ } else ++ ioparam->addr = 0; ++ } ++ ++error: ++ if (resource) ++ vmcs_sm_release_resource(resource, 0); ++ ++ return ret; ++} ++ ++/* Unlock a previously allocated shared memory handle and block. ++*/ ++static int vc_sm_ioctl_unlock(struct SM_PRIV_DATA_T *private, ++ struct vmcs_sm_ioctl_lock_unlock *ioparam, ++ int flush, int wait_reply, int no_vc_unlock) ++{ ++ int status; ++ VC_SM_LOCK_UNLOCK_T unlock; ++ struct sm_mmap *map, *map_tmp; ++ struct SM_RESOURCE_T *resource; ++ int ret = 0; ++ ++ map = NULL; ++ ++ /* Locate resource from GUID. ++ */ ++ resource = vmcs_sm_acquire_resource(private, ioparam->handle); ++ if (resource == NULL) { ++ ret = -EINVAL; ++ goto error; ++ } ++ ++ /* Check permissions. ++ */ ++ if (resource->pid && (resource->pid != current->tgid)) { ++ pr_err("[%s]: current tgid %u != %u owner\n", ++ __func__, current->tgid, resource->pid); ++ ret = -EPERM; ++ goto error; ++ } ++ ++ unlock.res_handle = resource->res_handle; ++ unlock.res_mem = resource->res_base_mem; ++ ++ pr_debug("[%s]: attempt to unlock data - guid %x, hdl %x, base address %p\n", ++ __func__, ioparam->handle, unlock.res_handle, unlock.res_mem); ++ ++ /* User space allocated resources. ++ */ ++ if (resource->pid) { ++ /* Flush if requested */ ++ if (resource->res_cached && flush) { ++ dma_addr_t phys_addr = 0; ++ resource->res_stats[FLUSH]++; ++ ++ phys_addr = ++ (dma_addr_t)((uint32_t)resource->res_base_mem & ++ 0x3FFFFFFF); ++ phys_addr += (dma_addr_t)mm_vc_mem_phys_addr; ++ ++ /* L1 cache flush */ ++ down_read(¤t->mm->mmap_sem); ++ list_for_each_entry(map, &resource->map_list, ++ resource_map_list) { ++ if (map->vma) { ++ unsigned long start; ++ unsigned long end; ++ start = map->vma->vm_start; ++ end = map->vma->vm_end; ++ ++ vcsm_vma_cache_clean_page_range( ++ start, end); ++ } ++ } ++ up_read(¤t->mm->mmap_sem); ++ ++ /* L2 cache flush */ ++ outer_clean_range(phys_addr, ++ phys_addr + ++ (size_t) resource->res_size); ++ } ++ ++ /* We need to zap all the vmas associated with this resource */ ++ if (resource->lock_count == 1) { ++ down_read(¤t->mm->mmap_sem); ++ list_for_each_entry(map, &resource->map_list, ++ resource_map_list) { ++ if (map->vma) { ++ zap_vma_ptes(map->vma, ++ map->vma->vm_start, ++ map->vma->vm_end - ++ map->vma->vm_start); ++ } ++ } ++ up_read(¤t->mm->mmap_sem); ++ } ++ } ++ /* Kernel allocated resources. */ ++ else { ++ /* Global + Taken in this context */ ++ if (resource->ref_count == 2) { ++ if (!list_empty(&resource->map_list)) { ++ list_for_each_entry_safe(map, map_tmp, ++ &resource->map_list, ++ resource_map_list) { ++ if (map->res_addr) { ++ if (flush && ++ (resource->res_cached == ++ VMCS_SM_CACHE_HOST)) { ++ long unsigned int ++ phys_addr; ++ phys_addr = (uint32_t) ++ resource->res_base_mem & 0x3FFFFFFF; ++ phys_addr += ++ mm_vc_mem_phys_addr; ++ ++ /* L1 cache flush */ ++ dmac_flush_range((const ++ void ++ *) ++ map->res_addr, (const void *) ++ (map->res_addr + resource->res_size)); ++ ++ /* L2 cache flush */ ++ outer_clean_range ++ (phys_addr, ++ phys_addr + ++ (size_t) ++ resource->res_size); ++ } ++ ++ iounmap((void *)map->res_addr); ++ map->res_addr = 0; ++ ++ vmcs_sm_remove_map(sm_state, ++ map->resource, ++ map); ++ break; ++ } ++ } ++ } ++ } ++ } ++ ++ if (resource->lock_count) { ++ /* Bypass the videocore unlock. ++ */ ++ if (no_vc_unlock) ++ status = 0; ++ /* Unlock the videocore allocated resource. ++ */ ++ else { ++ status = ++ vc_vchi_sm_unlock(sm_state->sm_handle, &unlock, ++ &private->int_trans_id, ++ wait_reply); ++ if (status == -EINTR) { ++ pr_debug("[%s]: requesting unlock memory action restart (trans_id: %u)\n", ++ __func__, private->int_trans_id); ++ ++ ret = -ERESTARTSYS; ++ resource->res_stats[UNLOCK]--; ++ private->restart_sys = -EINTR; ++ private->int_action = VC_SM_MSG_TYPE_UNLOCK; ++ goto error; ++ } else if (status != 0) { ++ pr_err("[%s]: failed to unlock vc mem (status: %u, trans_id: %u)\n", ++ __func__, status, private->int_trans_id); ++ ++ ret = -EPERM; ++ resource->res_stats[UNLOCK_FAIL]++; ++ goto error; ++ } ++ } ++ ++ resource->res_stats[UNLOCK]++; ++ resource->lock_count--; ++ } ++ ++ pr_debug("[%s]: success to unlock data - hdl %x, base address %p, ref-cnt %d\n", ++ __func__, unlock.res_handle, unlock.res_mem, ++ resource->lock_count); ++ ++error: ++ if (resource) ++ vmcs_sm_release_resource(resource, 0); ++ ++ return ret; ++} ++ ++/* Handle control from host. */ ++static long vc_sm_ioctl(struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ int ret = 0; ++ unsigned int cmdnr = _IOC_NR(cmd); ++ struct SM_PRIV_DATA_T *file_data = ++ (struct SM_PRIV_DATA_T *)file->private_data; ++ struct SM_RESOURCE_T *resource = NULL; ++ ++ /* Validate we can work with this device. */ ++ if ((sm_state == NULL) || (file_data == NULL)) { ++ pr_err("[%s]: invalid device\n", __func__); ++ ret = -EPERM; ++ goto out; ++ } ++ ++ pr_debug("[%s]: cmd %x tgid %u, owner %u\n", __func__, cmdnr, ++ current->tgid, file_data->pid); ++ ++ /* Action is a re-post of a previously interrupted action? */ ++ if (file_data->restart_sys == -EINTR) { ++ VC_SM_ACTION_CLEAN_T action_clean; ++ ++ pr_debug("[%s]: clean up of action %u (trans_id: %u) following EINTR\n", ++ __func__, file_data->int_action, ++ file_data->int_trans_id); ++ ++ action_clean.res_action = file_data->int_action; ++ action_clean.action_trans_id = file_data->int_trans_id; ++ ++ vc_vchi_sm_clean_up(sm_state->sm_handle, &action_clean); ++ ++ file_data->restart_sys = 0; ++ } ++ ++ /* Now process the command. ++ */ ++ switch (cmdnr) { ++ /* New memory allocation. ++ */ ++ case VMCS_SM_CMD_ALLOC: ++ { ++ struct vmcs_sm_ioctl_alloc ioparam; ++ ++ /* Get the parameter data. ++ */ ++ if (copy_from_user ++ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ ret = vc_sm_ioctl_alloc(file_data, &ioparam); ++ if (!ret && ++ (copy_to_user((void *)arg, ++ &ioparam, sizeof(ioparam)) != 0)) { ++ struct vmcs_sm_ioctl_free freeparam = { ++ ioparam.handle ++ }; ++ pr_err("[%s]: failed to copy-to-user for cmd %x\n", ++ __func__, cmdnr); ++ vc_sm_ioctl_free(file_data, &freeparam); ++ ret = -EFAULT; ++ } ++ ++ /* Done. ++ */ ++ goto out; ++ } ++ break; ++ ++ /* Share existing memory allocation. ++ */ ++ case VMCS_SM_CMD_ALLOC_SHARE: ++ { ++ struct vmcs_sm_ioctl_alloc_share ioparam; ++ ++ /* Get the parameter data. ++ */ ++ if (copy_from_user ++ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ ret = vc_sm_ioctl_alloc_share(file_data, &ioparam); ++ ++ /* Copy result back to user. ++ */ ++ if (!ret ++ && copy_to_user((void *)arg, &ioparam, ++ sizeof(ioparam)) != 0) { ++ struct vmcs_sm_ioctl_free freeparam = { ++ ioparam.handle ++ }; ++ pr_err("[%s]: failed to copy-to-user for cmd %x\n", ++ __func__, cmdnr); ++ vc_sm_ioctl_free(file_data, &freeparam); ++ ret = -EFAULT; ++ } ++ ++ /* Done. ++ */ ++ goto out; ++ } ++ break; ++ ++ /* Lock (attempt to) *and* register a cache behavior change. ++ */ ++ case VMCS_SM_CMD_LOCK_CACHE: ++ { ++ struct vmcs_sm_ioctl_lock_cache ioparam; ++ struct vmcs_sm_ioctl_lock_unlock lock; ++ ++ /* Get parameter data. ++ */ ++ if (copy_from_user ++ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ lock.handle = ioparam.handle; ++ ret = ++ vc_sm_ioctl_lock(file_data, &lock, 1, ++ ioparam.cached, 0); ++ ++ /* Done. ++ */ ++ goto out; ++ } ++ break; ++ ++ /* Lock (attempt to) existing memory allocation. ++ */ ++ case VMCS_SM_CMD_LOCK: ++ { ++ struct vmcs_sm_ioctl_lock_unlock ioparam; ++ ++ /* Get parameter data. ++ */ ++ if (copy_from_user ++ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ ret = vc_sm_ioctl_lock(file_data, &ioparam, 0, 0, 0); ++ ++ /* Copy result back to user. ++ */ ++ if (copy_to_user((void *)arg, &ioparam, sizeof(ioparam)) ++ != 0) { ++ pr_err("[%s]: failed to copy-to-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ } ++ ++ /* Done. ++ */ ++ goto out; ++ } ++ break; ++ ++ /* Unlock (attempt to) existing memory allocation. ++ */ ++ case VMCS_SM_CMD_UNLOCK: ++ { ++ struct vmcs_sm_ioctl_lock_unlock ioparam; ++ ++ /* Get parameter data. ++ */ ++ if (copy_from_user ++ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ ret = vc_sm_ioctl_unlock(file_data, &ioparam, 0, 1, 0); ++ ++ /* Done. ++ */ ++ goto out; ++ } ++ break; ++ ++ /* Resize (attempt to) existing memory allocation. ++ */ ++ case VMCS_SM_CMD_RESIZE: ++ { ++ struct vmcs_sm_ioctl_resize ioparam; ++ ++ /* Get parameter data. ++ */ ++ if (copy_from_user ++ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ ret = vc_sm_ioctl_resize(file_data, &ioparam); ++ ++ /* Copy result back to user. ++ */ ++ if (copy_to_user((void *)arg, &ioparam, sizeof(ioparam)) ++ != 0) { ++ pr_err("[%s]: failed to copy-to-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ } ++ ++ /* Done. ++ */ ++ goto out; ++ } ++ break; ++ ++ /* Terminate existing memory allocation. ++ */ ++ case VMCS_SM_CMD_FREE: ++ { ++ struct vmcs_sm_ioctl_free ioparam; ++ ++ /* Get parameter data. ++ */ ++ if (copy_from_user ++ (&ioparam, (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ ret = vc_sm_ioctl_free(file_data, &ioparam); ++ ++ /* Done. ++ */ ++ goto out; ++ } ++ break; ++ ++ /* Walk allocation on videocore, information shows up in the ++ ** videocore log. ++ */ ++ case VMCS_SM_CMD_VC_WALK_ALLOC: ++ { ++ pr_debug("[%s]: invoking walk alloc\n", __func__); ++ ++ if (vc_vchi_sm_walk_alloc(sm_state->sm_handle) != 0) ++ pr_err("[%s]: failed to walk-alloc on videocore\n", ++ __func__); ++ ++ /* Done. ++ */ ++ goto out; ++ } ++ break; ++/* Walk mapping table on host, information shows up in the ++ ** kernel log. ++ */ ++ case VMCS_SM_CMD_HOST_WALK_MAP: ++ { ++ /* Use pid of -1 to tell to walk the whole map. */ ++ vmcs_sm_host_walk_map_per_pid(-1); ++ ++ /* Done. */ ++ goto out; ++ } ++ break; ++ ++ /* Walk mapping table per process on host. */ ++ case VMCS_SM_CMD_HOST_WALK_PID_ALLOC: ++ { ++ struct vmcs_sm_ioctl_walk ioparam; ++ ++ /* Get parameter data. */ ++ if (copy_from_user(&ioparam, ++ (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ vmcs_sm_host_walk_alloc(file_data); ++ ++ /* Done. */ ++ goto out; ++ } ++ break; ++ ++ /* Walk allocation per process on host. */ ++ case VMCS_SM_CMD_HOST_WALK_PID_MAP: ++ { ++ struct vmcs_sm_ioctl_walk ioparam; ++ ++ /* Get parameter data. */ ++ if (copy_from_user(&ioparam, ++ (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ vmcs_sm_host_walk_map_per_pid(ioparam.pid); ++ ++ /* Done. */ ++ goto out; ++ } ++ break; ++ ++ /* Gets the size of the memory associated with a user handle. */ ++ case VMCS_SM_CMD_SIZE_USR_HANDLE: ++ { ++ struct vmcs_sm_ioctl_size ioparam; ++ ++ /* Get parameter data. */ ++ if (copy_from_user(&ioparam, ++ (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ /* Locate resource from GUID. */ ++ resource = ++ vmcs_sm_acquire_resource(file_data, ioparam.handle); ++ if (resource != NULL) { ++ ioparam.size = resource->res_size; ++ vmcs_sm_release_resource(resource, 0); ++ } else { ++ ioparam.size = 0; ++ } ++ ++ if (copy_to_user((void *)arg, ++ &ioparam, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-to-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ } ++ ++ /* Done. */ ++ goto out; ++ } ++ break; ++ ++ /* Verify we are dealing with a valid resource. */ ++ case VMCS_SM_CMD_CHK_USR_HANDLE: ++ { ++ struct vmcs_sm_ioctl_chk ioparam; ++ ++ /* Get parameter data. ++ */ ++ if (copy_from_user(&ioparam, ++ (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ /* Locate resource from GUID. */ ++ resource = ++ vmcs_sm_acquire_resource(file_data, ioparam.handle); ++ if (resource == NULL) ++ ret = -EINVAL; ++ /* If the resource is cacheable, return additional ++ * information that may be needed to flush the cache. ++ */ ++ else if ((resource->res_cached == VMCS_SM_CACHE_HOST) || ++ (resource->res_cached == VMCS_SM_CACHE_BOTH)) { ++ ioparam.addr = ++ vmcs_sm_usr_address_from_pid_and_usr_handle ++ (current->tgid, ioparam.handle); ++ ioparam.size = resource->res_size; ++ ioparam.cache = resource->res_cached; ++ } else { ++ ioparam.addr = 0; ++ ioparam.size = 0; ++ ioparam.cache = resource->res_cached; ++ } ++ ++ if (resource) ++ vmcs_sm_release_resource(resource, 0); ++ ++ if (copy_to_user((void *)arg, ++ &ioparam, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-to-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ } ++ ++ /* Done. ++ */ ++ goto out; ++ } ++ break; ++ ++ /* ++ * Maps a user handle given the process and the virtual address. ++ */ ++ case VMCS_SM_CMD_MAPPED_USR_HANDLE: ++ { ++ struct vmcs_sm_ioctl_map ioparam; ++ ++ /* Get parameter data. */ ++ if (copy_from_user(&ioparam, ++ (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ ioparam.handle = ++ vmcs_sm_usr_handle_from_pid_and_address( ++ ioparam.pid, ioparam.addr); ++ ++ resource = ++ vmcs_sm_acquire_resource(file_data, ioparam.handle); ++ if ((resource != NULL) ++ && ((resource->res_cached == VMCS_SM_CACHE_HOST) ++ || (resource->res_cached == ++ VMCS_SM_CACHE_BOTH))) { ++ ioparam.size = resource->res_size; ++ } else { ++ ioparam.size = 0; ++ } ++ ++ if (resource) ++ vmcs_sm_release_resource(resource, 0); ++ ++ if (copy_to_user((void *)arg, ++ &ioparam, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-to-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ } ++ ++ /* Done. */ ++ goto out; ++ } ++ break; ++ ++ /* ++ * Maps a videocore handle given process and virtual address. ++ */ ++ case VMCS_SM_CMD_MAPPED_VC_HDL_FROM_ADDR: ++ { ++ struct vmcs_sm_ioctl_map ioparam; ++ ++ /* Get parameter data. */ ++ if (copy_from_user(&ioparam, ++ (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ ioparam.handle = vmcs_sm_vc_handle_from_pid_and_address( ++ ioparam.pid, ioparam.addr); ++ ++ if (copy_to_user((void *)arg, ++ &ioparam, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-to-user for cmd %x\n", ++ __func__, cmdnr); ++ ++ ret = -EFAULT; ++ } ++ ++ /* Done. ++ */ ++ goto out; ++ } ++ break; ++ ++ /* Maps a videocore handle given process and user handle. */ ++ case VMCS_SM_CMD_MAPPED_VC_HDL_FROM_HDL: ++ { ++ struct vmcs_sm_ioctl_map ioparam; ++ ++ /* Get parameter data. */ ++ if (copy_from_user(&ioparam, ++ (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ /* Locate resource from GUID. */ ++ resource = ++ vmcs_sm_acquire_resource(file_data, ioparam.handle); ++ if (resource != NULL) { ++ ioparam.handle = resource->res_handle; ++ vmcs_sm_release_resource(resource, 0); ++ } else { ++ ioparam.handle = 0; ++ } ++ ++ if (copy_to_user((void *)arg, ++ &ioparam, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-to-user for cmd %x\n", ++ __func__, cmdnr); ++ ++ ret = -EFAULT; ++ } ++ ++ /* Done. */ ++ goto out; ++ } ++ break; ++ ++ /* ++ * Maps a videocore address given process and videocore handle. ++ */ ++ case VMCS_SM_CMD_MAPPED_VC_ADDR_FROM_HDL: ++ { ++ struct vmcs_sm_ioctl_map ioparam; ++ ++ /* Get parameter data. */ ++ if (copy_from_user(&ioparam, ++ (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ /* Locate resource from GUID. */ ++ resource = ++ vmcs_sm_acquire_resource(file_data, ioparam.handle); ++ if (resource != NULL) { ++ ioparam.addr = ++ (unsigned int)resource->res_base_mem; ++ vmcs_sm_release_resource(resource, 0); ++ } else { ++ ioparam.addr = 0; ++ } ++ ++ if (copy_to_user((void *)arg, ++ &ioparam, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-to-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ } ++ ++ /* Done. */ ++ goto out; ++ } ++ break; ++ ++ /* Maps a user address given process and vc handle. ++ */ ++ case VMCS_SM_CMD_MAPPED_USR_ADDRESS: ++ { ++ struct vmcs_sm_ioctl_map ioparam; ++ ++ /* Get parameter data. */ ++ if (copy_from_user(&ioparam, ++ (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ /* ++ * Return the address information from the mapping, ++ * 0 (ie NULL) if it cannot locate the actual mapping. ++ */ ++ ioparam.addr = ++ vmcs_sm_usr_address_from_pid_and_usr_handle ++ (ioparam.pid, ioparam.handle); ++ ++ if (copy_to_user((void *)arg, ++ &ioparam, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-to-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ } ++ ++ /* Done. */ ++ goto out; ++ } ++ break; ++ ++ /* Flush the cache for a given mapping. */ ++ case VMCS_SM_CMD_FLUSH: ++ { ++ struct vmcs_sm_ioctl_cache ioparam; ++ ++ /* Get parameter data. */ ++ if (copy_from_user(&ioparam, ++ (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ /* Locate resource from GUID. */ ++ resource = ++ vmcs_sm_acquire_resource(file_data, ioparam.handle); ++ ++ if ((resource != NULL) && resource->res_cached) { ++ dma_addr_t phys_addr = 0; ++ ++ resource->res_stats[FLUSH]++; ++ ++ phys_addr = ++ (dma_addr_t)((uint32_t) ++ resource->res_base_mem & ++ 0x3FFFFFFF); ++ phys_addr += (dma_addr_t)mm_vc_mem_phys_addr; ++ ++ /* L1 cache flush */ ++ down_read(¤t->mm->mmap_sem); ++ vcsm_vma_cache_clean_page_range((unsigned long) ++ ioparam.addr, ++ (unsigned long) ++ ioparam.addr + ++ ioparam.size); ++ up_read(¤t->mm->mmap_sem); ++ ++ /* L2 cache flush */ ++ outer_clean_range(phys_addr, ++ phys_addr + ++ (size_t) ioparam.size); ++ } else if (resource == NULL) { ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ if (resource) ++ vmcs_sm_release_resource(resource, 0); ++ ++ /* Done. */ ++ goto out; ++ } ++ break; ++ ++ /* Invalidate the cache for a given mapping. */ ++ case VMCS_SM_CMD_INVALID: ++ { ++ struct vmcs_sm_ioctl_cache ioparam; ++ ++ /* Get parameter data. */ ++ if (copy_from_user(&ioparam, ++ (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ /* Locate resource from GUID. ++ */ ++ resource = ++ vmcs_sm_acquire_resource(file_data, ioparam.handle); ++ ++ if ((resource != NULL) && resource->res_cached) { ++ dma_addr_t phys_addr = 0; ++ ++ resource->res_stats[INVALID]++; ++ ++ phys_addr = ++ (dma_addr_t)((uint32_t) ++ resource->res_base_mem & ++ 0x3FFFFFFF); ++ phys_addr += (dma_addr_t)mm_vc_mem_phys_addr; ++ ++ /* L2 cache invalidate */ ++ outer_inv_range(phys_addr, ++ phys_addr + ++ (size_t) ioparam.size); ++ ++ /* L1 cache invalidate */ ++ down_read(¤t->mm->mmap_sem); ++ vcsm_vma_cache_clean_page_range((unsigned long) ++ ioparam.addr, ++ (unsigned long) ++ ioparam.addr + ++ ioparam.size); ++ up_read(¤t->mm->mmap_sem); ++ } else if (resource == NULL) { ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ if (resource) ++ vmcs_sm_release_resource(resource, 0); ++ ++ /* Done. ++ */ ++ goto out; ++ } ++ break; ++ ++ /* Flush/Invalidate the cache for a given mapping. */ ++ case VMCS_SM_CMD_CLEAN_INVALID: ++ { ++ int i; ++ struct vmcs_sm_ioctl_clean_invalid ioparam; ++ ++ /* Get parameter data. */ ++ if (copy_from_user(&ioparam, ++ (void *)arg, sizeof(ioparam)) != 0) { ++ pr_err("[%s]: failed to copy-from-user for cmd %x\n", ++ __func__, cmdnr); ++ ret = -EFAULT; ++ goto out; ++ } ++ for (i=0; ires_cached) { ++ unsigned long base = ioparam.s[i].addr & ~(PAGE_SIZE-1); ++ unsigned long end = (ioparam.s[i].addr + ioparam.s[i].size + PAGE_SIZE-1) & ~(PAGE_SIZE-1); ++ resource->res_stats[ioparam.s[i].cmd == 1 ? INVALID:FLUSH]++; ++ ++ /* L1/L2 cache flush */ ++ down_read(¤t->mm->mmap_sem); ++ vcsm_vma_cache_clean_page_range(base, end); ++ up_read(¤t->mm->mmap_sem); ++ } else if (resource == NULL) { ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ if (resource) ++ vmcs_sm_release_resource(resource, 0); ++ } ++ break; ++ } ++ } ++ } ++ break; ++ ++ default: ++ { ++ ret = -EINVAL; ++ goto out; ++ } ++ break; ++ } ++ ++out: ++ return ret; ++} ++ ++/* Device operations that we managed in this driver. ++*/ ++static const struct file_operations vmcs_sm_ops = { ++ .owner = THIS_MODULE, ++ .unlocked_ioctl = vc_sm_ioctl, ++ .open = vc_sm_open, ++ .release = vc_sm_release, ++ .mmap = vc_sm_mmap, ++}; ++ ++/* Creation of device. ++*/ ++static int vc_sm_create_sharedmemory(void) ++{ ++ int ret; ++ ++ if (sm_state == NULL) { ++ ret = -ENOMEM; ++ goto out; ++ } ++ ++ /* Create a device class for creating dev nodes. ++ */ ++ sm_state->sm_class = class_create(THIS_MODULE, "vc-sm"); ++ if (IS_ERR(sm_state->sm_class)) { ++ pr_err("[%s]: unable to create device class\n", __func__); ++ ret = PTR_ERR(sm_state->sm_class); ++ goto out; ++ } ++ ++ /* Create a character driver. ++ */ ++ ret = alloc_chrdev_region(&sm_state->sm_devid, ++ DEVICE_MINOR, 1, DEVICE_NAME); ++ if (ret != 0) { ++ pr_err("[%s]: unable to allocate device number\n", __func__); ++ goto out_dev_class_destroy; ++ } ++ ++ cdev_init(&sm_state->sm_cdev, &vmcs_sm_ops); ++ ret = cdev_add(&sm_state->sm_cdev, sm_state->sm_devid, 1); ++ if (ret != 0) { ++ pr_err("[%s]: unable to register device\n", __func__); ++ goto out_chrdev_unreg; ++ } ++ ++ /* Create a device node. ++ */ ++ sm_state->sm_dev = device_create(sm_state->sm_class, ++ NULL, ++ MKDEV(MAJOR(sm_state->sm_devid), ++ DEVICE_MINOR), NULL, ++ DEVICE_NAME); ++ if (IS_ERR(sm_state->sm_dev)) { ++ pr_err("[%s]: unable to create device node\n", __func__); ++ ret = PTR_ERR(sm_state->sm_dev); ++ goto out_chrdev_del; ++ } ++ ++ goto out; ++ ++out_chrdev_del: ++ cdev_del(&sm_state->sm_cdev); ++out_chrdev_unreg: ++ unregister_chrdev_region(sm_state->sm_devid, 1); ++out_dev_class_destroy: ++ class_destroy(sm_state->sm_class); ++ sm_state->sm_class = NULL; ++out: ++ return ret; ++} ++ ++/* Termination of the device. ++*/ ++static int vc_sm_remove_sharedmemory(void) ++{ ++ int ret; ++ ++ if (sm_state == NULL) { ++ /* Nothing to do. ++ */ ++ ret = 0; ++ goto out; ++ } ++ ++ /* Remove the sharedmemory character driver. ++ */ ++ cdev_del(&sm_state->sm_cdev); ++ ++ /* Unregister region. ++ */ ++ unregister_chrdev_region(sm_state->sm_devid, 1); ++ ++ ret = 0; ++ goto out; ++ ++out: ++ return ret; ++} ++ ++/* Videocore connected. */ ++static void vc_sm_connected_init(void) ++{ ++ int ret; ++ VCHI_INSTANCE_T vchi_instance; ++ VCHI_CONNECTION_T *vchi_connection = NULL; ++ ++ pr_info("[%s]: start\n", __func__); ++ ++ /* Allocate memory for the state structure. ++ */ ++ sm_state = kzalloc(sizeof(struct SM_STATE_T), GFP_KERNEL); ++ if (sm_state == NULL) { ++ pr_err("[%s]: failed to allocate memory\n", __func__); ++ ret = -ENOMEM; ++ goto out; ++ } ++ ++ mutex_init(&sm_state->lock); ++ mutex_init(&sm_state->map_lock); ++ ++ /* Initialize and create a VCHI connection for the shared memory service ++ ** running on videocore. ++ */ ++ ret = vchi_initialise(&vchi_instance); ++ if (ret != 0) { ++ pr_err("[%s]: failed to initialise VCHI instance (ret=%d)\n", ++ __func__, ret); ++ ++ ret = -EIO; ++ goto err_free_mem; ++ } ++ ++ ret = vchi_connect(NULL, 0, vchi_instance); ++ if (ret != 0) { ++ pr_err("[%s]: failed to connect VCHI instance (ret=%d)\n", ++ __func__, ret); ++ ++ ret = -EIO; ++ goto err_free_mem; ++ } ++ ++ /* Initialize an instance of the shared memory service. */ ++ sm_state->sm_handle = ++ vc_vchi_sm_init(vchi_instance, &vchi_connection, 1); ++ if (sm_state->sm_handle == NULL) { ++ pr_err("[%s]: failed to initialize shared memory service\n", ++ __func__); ++ ++ ret = -EPERM; ++ goto err_free_mem; ++ } ++ ++ /* Create a debug fs directory entry (root). */ ++ sm_state->dir_root = debugfs_create_dir(VC_SM_DIR_ROOT_NAME, NULL); ++ if (!sm_state->dir_root) { ++ pr_err("[%s]: failed to create \'%s\' directory entry\n", ++ __func__, VC_SM_DIR_ROOT_NAME); ++ ++ ret = -EPERM; ++ goto err_stop_sm_service; ++ } ++ ++ sm_state->dir_state.show = &vc_sm_global_state_show; ++ sm_state->dir_state.dir_entry = debugfs_create_file(VC_SM_STATE, ++ S_IRUGO, sm_state->dir_root, &sm_state->dir_state, ++ &vc_sm_debug_fs_fops); ++ ++ sm_state->dir_stats.show = &vc_sm_global_statistics_show; ++ sm_state->dir_stats.dir_entry = debugfs_create_file(VC_SM_STATS, ++ S_IRUGO, sm_state->dir_root, &sm_state->dir_stats, ++ &vc_sm_debug_fs_fops); ++ ++ /* Create the proc entry children. */ ++ sm_state->dir_alloc = debugfs_create_dir(VC_SM_DIR_ALLOC_NAME, ++ sm_state->dir_root); ++ ++ /* Create a shared memory device. */ ++ ret = vc_sm_create_sharedmemory(); ++ if (ret != 0) { ++ pr_err("[%s]: failed to create shared memory device\n", ++ __func__); ++ goto err_remove_debugfs; ++ } ++ ++ INIT_LIST_HEAD(&sm_state->map_list); ++ INIT_LIST_HEAD(&sm_state->resource_list); ++ ++ sm_state->data_knl = vc_sm_create_priv_data(0); ++ if (sm_state->data_knl == NULL) { ++ pr_err("[%s]: failed to create kernel private data tracker\n", ++ __func__); ++ goto err_remove_shared_memory; ++ } ++ ++ /* Done! ++ */ ++ sm_inited = 1; ++ goto out; ++ ++err_remove_shared_memory: ++ vc_sm_remove_sharedmemory(); ++err_remove_debugfs: ++ debugfs_remove_recursive(sm_state->dir_root); ++err_stop_sm_service: ++ vc_vchi_sm_stop(&sm_state->sm_handle); ++err_free_mem: ++ kfree(sm_state); ++out: ++ pr_info("[%s]: end - returning %d\n", __func__, ret); ++} ++ ++/* Driver loading. */ ++static int __init vc_sm_init(void) ++{ ++ pr_info("vc-sm: Videocore shared memory driver\n"); ++ vchiq_add_connected_callback(vc_sm_connected_init); ++ return 0; ++} ++ ++/* Driver unloading. */ ++static void __exit vc_sm_exit(void) ++{ ++ pr_debug("[%s]: start\n", __func__); ++ if (sm_inited) { ++ /* Remove shared memory device. ++ */ ++ vc_sm_remove_sharedmemory(); ++ ++ /* Remove all proc entries. ++ */ ++ debugfs_remove_recursive(sm_state->dir_root); ++ ++ /* Stop the videocore shared memory service. ++ */ ++ vc_vchi_sm_stop(&sm_state->sm_handle); ++ ++ /* Free the memory for the state structure. ++ */ ++ mutex_destroy(&(sm_state->map_lock)); ++ kfree(sm_state); ++ } ++ ++ pr_debug("[%s]: end\n", __func__); ++} ++ ++#if defined(__KERNEL__) ++/* Allocate a shared memory handle and block. */ ++int vc_sm_alloc(VC_SM_ALLOC_T *alloc, int *handle) ++{ ++ struct vmcs_sm_ioctl_alloc ioparam = { 0 }; ++ int ret; ++ struct SM_RESOURCE_T *resource; ++ ++ /* Validate we can work with this device. ++ */ ++ if (sm_state == NULL || alloc == NULL || handle == NULL) { ++ pr_err("[%s]: invalid input\n", __func__); ++ return -EPERM; ++ } ++ ++ ioparam.size = alloc->base_unit; ++ ioparam.num = alloc->num_unit; ++ ioparam.cached = ++ alloc->type == VC_SM_ALLOC_CACHED ? VMCS_SM_CACHE_VC : 0; ++ ++ ret = vc_sm_ioctl_alloc(sm_state->data_knl, &ioparam); ++ ++ if (ret == 0) { ++ resource = ++ vmcs_sm_acquire_resource(sm_state->data_knl, ++ ioparam.handle); ++ if (resource) { ++ resource->pid = 0; ++ vmcs_sm_release_resource(resource, 0); ++ ++ /* Assign valid handle at this time. ++ */ ++ *handle = ioparam.handle; ++ } else { ++ ret = -ENOMEM; ++ } ++ } ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(vc_sm_alloc); ++ ++/* Get an internal resource handle mapped from the external one. ++*/ ++int vc_sm_int_handle(int handle) ++{ ++ struct SM_RESOURCE_T *resource; ++ int ret = 0; ++ ++ /* Validate we can work with this device. ++ */ ++ if (sm_state == NULL || handle == 0) { ++ pr_err("[%s]: invalid input\n", __func__); ++ return 0; ++ } ++ ++ /* Locate resource from GUID. ++ */ ++ resource = vmcs_sm_acquire_resource(sm_state->data_knl, handle); ++ if (resource) { ++ ret = resource->res_handle; ++ vmcs_sm_release_resource(resource, 0); ++ } ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(vc_sm_int_handle); ++ ++/* Free a previously allocated shared memory handle and block. ++*/ ++int vc_sm_free(int handle) ++{ ++ struct vmcs_sm_ioctl_free ioparam = { handle }; ++ ++ /* Validate we can work with this device. ++ */ ++ if (sm_state == NULL || handle == 0) { ++ pr_err("[%s]: invalid input\n", __func__); ++ return -EPERM; ++ } ++ ++ return vc_sm_ioctl_free(sm_state->data_knl, &ioparam); ++} ++EXPORT_SYMBOL_GPL(vc_sm_free); ++ ++/* Lock a memory handle for use by kernel. ++*/ ++int vc_sm_lock(int handle, VC_SM_LOCK_CACHE_MODE_T mode, ++ long unsigned int *data) ++{ ++ struct vmcs_sm_ioctl_lock_unlock ioparam; ++ int ret; ++ ++ /* Validate we can work with this device. ++ */ ++ if (sm_state == NULL || handle == 0 || data == NULL) { ++ pr_err("[%s]: invalid input\n", __func__); ++ return -EPERM; ++ } ++ ++ *data = 0; ++ ++ ioparam.handle = handle; ++ ret = vc_sm_ioctl_lock(sm_state->data_knl, ++ &ioparam, ++ 1, ++ ((mode == ++ VC_SM_LOCK_CACHED) ? VMCS_SM_CACHE_HOST : ++ VMCS_SM_CACHE_NONE), 0); ++ ++ *data = ioparam.addr; ++ return ret; ++} ++EXPORT_SYMBOL_GPL(vc_sm_lock); ++ ++/* Unlock a memory handle in use by kernel. ++*/ ++int vc_sm_unlock(int handle, int flush, int no_vc_unlock) ++{ ++ struct vmcs_sm_ioctl_lock_unlock ioparam; ++ ++ /* Validate we can work with this device. ++ */ ++ if (sm_state == NULL || handle == 0) { ++ pr_err("[%s]: invalid input\n", __func__); ++ return -EPERM; ++ } ++ ++ ioparam.handle = handle; ++ return vc_sm_ioctl_unlock(sm_state->data_knl, ++ &ioparam, flush, 0, no_vc_unlock); ++} ++EXPORT_SYMBOL_GPL(vc_sm_unlock); ++ ++/* Map a shared memory region for use by kernel. ++*/ ++int vc_sm_map(int handle, unsigned int sm_addr, VC_SM_LOCK_CACHE_MODE_T mode, ++ long unsigned int *data) ++{ ++ struct vmcs_sm_ioctl_lock_unlock ioparam; ++ int ret; ++ ++ /* Validate we can work with this device. ++ */ ++ if (sm_state == NULL || handle == 0 || data == NULL || sm_addr == 0) { ++ pr_err("[%s]: invalid input\n", __func__); ++ return -EPERM; ++ } ++ ++ *data = 0; ++ ++ ioparam.handle = handle; ++ ret = vc_sm_ioctl_lock(sm_state->data_knl, ++ &ioparam, ++ 1, ++ ((mode == ++ VC_SM_LOCK_CACHED) ? VMCS_SM_CACHE_HOST : ++ VMCS_SM_CACHE_NONE), sm_addr); ++ ++ *data = ioparam.addr; ++ return ret; ++} ++EXPORT_SYMBOL_GPL(vc_sm_map); ++#endif ++ ++late_initcall(vc_sm_init); ++module_exit(vc_sm_exit); ++ ++MODULE_AUTHOR("Broadcom"); ++MODULE_DESCRIPTION("VideoCore SharedMemory Driver"); ++MODULE_LICENSE("GPL v2"); +diff -Nur linux-4.1.13.orig/drivers/char/hw_random/bcm2708-rng.c linux-rpi/drivers/char/hw_random/bcm2708-rng.c +--- linux-4.1.13.orig/drivers/char/hw_random/bcm2708-rng.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/char/hw_random/bcm2708-rng.c 2015-11-29 09:42:36.707312101 +0100 +@@ -0,0 +1,118 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#define RNG_CTRL (0x0) ++#define RNG_STATUS (0x4) ++#define RNG_DATA (0x8) ++#define RNG_FF_THRESHOLD (0xc) ++ ++/* enable rng */ ++#define RNG_RBGEN 0x1 ++/* double speed, less random mode */ ++#define RNG_RBG2X 0x2 ++ ++/* the initial numbers generated are "less random" so will be discarded */ ++#define RNG_WARMUP_COUNT 0x40000 ++ ++static int bcm2708_rng_data_read(struct hwrng *rng, u32 *buffer) ++{ ++ void __iomem *rng_base = (void __iomem *)rng->priv; ++ unsigned words; ++ /* wait for a random number to be in fifo */ ++ do { ++ words = __raw_readl(rng_base + RNG_STATUS)>>24; ++ } ++ while (words == 0); ++ /* read the random number */ ++ *buffer = __raw_readl(rng_base + RNG_DATA); ++ return 4; ++} ++ ++static struct hwrng bcm2708_rng_ops = { ++ .name = "bcm2708", ++ .data_read = bcm2708_rng_data_read, ++}; ++ ++static int __init bcm2708_rng_init(void) ++{ ++ void __iomem *rng_base; ++ int err; ++ ++ /* map peripheral */ ++ rng_base = ioremap(RNG_BASE, 0x10); ++ pr_info("bcm2708_rng_init=%p\n", rng_base); ++ if (!rng_base) { ++ pr_err("bcm2708_rng_init failed to ioremap\n"); ++ return -ENOMEM; ++ } ++ bcm2708_rng_ops.priv = (unsigned long)rng_base; ++ ++ /* set warm-up count & enable */ ++ __raw_writel(RNG_WARMUP_COUNT, rng_base + RNG_STATUS); ++ __raw_writel(RNG_RBGEN, rng_base + RNG_CTRL); ++ ++ /* register driver */ ++ err = hwrng_register(&bcm2708_rng_ops); ++ if (err) { ++ pr_err("bcm2708_rng_init hwrng_register()=%d\n", err); ++ iounmap(rng_base); ++ } ++ return err; ++} ++ ++static void __exit bcm2708_rng_exit(void) ++{ ++ void __iomem *rng_base = (void __iomem *)bcm2708_rng_ops.priv; ++ pr_info("bcm2708_rng_exit\n"); ++ /* disable rng hardware */ ++ __raw_writel(0, rng_base + RNG_CTRL); ++ /* unregister driver */ ++ hwrng_unregister(&bcm2708_rng_ops); ++ iounmap(rng_base); ++} ++ ++module_init(bcm2708_rng_init); ++module_exit(bcm2708_rng_exit); ++ ++MODULE_DESCRIPTION("BCM2708 H/W Random Number Generator (RNG) driver"); ++MODULE_LICENSE("GPL and additional rights"); +diff -Nur linux-4.1.13.orig/drivers/char/hw_random/Kconfig linux-rpi/drivers/char/hw_random/Kconfig +--- linux-4.1.13.orig/drivers/char/hw_random/Kconfig 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/char/hw_random/Kconfig 2015-11-29 09:42:36.707312101 +0100 +@@ -90,7 +90,7 @@ + + config HW_RANDOM_BCM2835 + tristate "Broadcom BCM2835 Random Number Generator support" +- depends on ARCH_BCM2835 ++ depends on ARCH_BCM2835 || ARCH_BCM2708 || ARCH_BCM2709 + default HW_RANDOM + ---help--- + This driver provides kernel-side support for the Random Number +@@ -333,6 +333,17 @@ + + If unsure, say Y. + ++config HW_RANDOM_BCM2708 ++ tristate "BCM2708 generic true random number generator support" ++ depends on HW_RANDOM && (ARCH_BCM2708 || ARCH_BCM2709) ++ ---help--- ++ This driver provides the kernel-side support for the BCM2708 hardware. ++ ++ To compile this driver as a module, choose M here: the ++ module will be called bcm2708-rng. ++ ++ If unsure, say N. ++ + config HW_RANDOM_MSM + tristate "Qualcomm SoCs Random Number Generator support" + depends on HW_RANDOM && ARCH_QCOM +diff -Nur linux-4.1.13.orig/drivers/char/hw_random/Makefile linux-rpi/drivers/char/hw_random/Makefile +--- linux-4.1.13.orig/drivers/char/hw_random/Makefile 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/char/hw_random/Makefile 2015-11-29 09:42:36.707312101 +0100 +@@ -4,6 +4,7 @@ + + obj-$(CONFIG_HW_RANDOM) += rng-core.o + rng-core-y := core.o ++obj-$(CONFIG_HW_RANDOM_BCM2708) += bcm2708-rng.o + obj-$(CONFIG_HW_RANDOM_TIMERIOMEM) += timeriomem-rng.o + obj-$(CONFIG_HW_RANDOM_INTEL) += intel-rng.o + obj-$(CONFIG_HW_RANDOM_AMD) += amd-rng.o +diff -Nur linux-4.1.13.orig/drivers/char/Kconfig linux-rpi/drivers/char/Kconfig +--- linux-4.1.13.orig/drivers/char/Kconfig 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/char/Kconfig 2015-11-29 09:42:36.687313430 +0100 +@@ -590,6 +590,8 @@ + + source "drivers/s390/char/Kconfig" + ++source "drivers/char/broadcom/Kconfig" ++ + config MSM_SMD_PKT + bool "Enable device interface for some SMD packet ports" + default n +diff -Nur linux-4.1.13.orig/drivers/char/Makefile linux-rpi/drivers/char/Makefile +--- linux-4.1.13.orig/drivers/char/Makefile 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/char/Makefile 2015-11-29 09:42:36.687313430 +0100 +@@ -62,3 +62,4 @@ + + obj-$(CONFIG_TILE_SROM) += tile-srom.o + obj-$(CONFIG_XILLYBUS) += xillybus/ ++obj-$(CONFIG_BRCM_CHAR_DRIVERS) += broadcom/ +diff -Nur linux-4.1.13.orig/drivers/clk/clk-hifiberry-dacpro.c linux-rpi/drivers/clk/clk-hifiberry-dacpro.c +--- linux-4.1.13.orig/drivers/clk/clk-hifiberry-dacpro.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/clk/clk-hifiberry-dacpro.c 2015-11-29 09:42:36.751309177 +0100 +@@ -0,0 +1,160 @@ ++/* ++ * Clock Driver for HiFiBerry DAC Pro ++ * ++ * Author: Stuart MacLean ++ * Copyright 2015 ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* Clock rate of CLK44EN attached to GPIO6 pin */ ++#define CLK_44EN_RATE 22579200UL ++/* Clock rate of CLK48EN attached to GPIO3 pin */ ++#define CLK_48EN_RATE 24576000UL ++ ++/** ++ * struct hifiberry_dacpro_clk - Common struct to the HiFiBerry DAC Pro ++ * @hw: clk_hw for the common clk framework ++ * @mode: 0 => CLK44EN, 1 => CLK48EN ++ */ ++struct clk_hifiberry_hw { ++ struct clk_hw hw; ++ uint8_t mode; ++}; ++ ++#define to_hifiberry_clk(_hw) container_of(_hw, struct clk_hifiberry_hw, hw) ++ ++static const struct of_device_id clk_hifiberry_dacpro_dt_ids[] = { ++ { .compatible = "hifiberry,dacpro-clk",}, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, clk_hifiberry_dacpro_dt_ids); ++ ++static unsigned long clk_hifiberry_dacpro_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ return (to_hifiberry_clk(hw)->mode == 0) ? CLK_44EN_RATE : ++ CLK_48EN_RATE; ++} ++ ++static long clk_hifiberry_dacpro_round_rate(struct clk_hw *hw, ++ unsigned long rate, unsigned long *parent_rate) ++{ ++ long actual_rate; ++ ++ if (rate <= CLK_44EN_RATE) { ++ actual_rate = (long)CLK_44EN_RATE; ++ } else if (rate >= CLK_48EN_RATE) { ++ actual_rate = (long)CLK_48EN_RATE; ++ } else { ++ long diff44Rate = (long)(rate - CLK_44EN_RATE); ++ long diff48Rate = (long)(CLK_48EN_RATE - rate); ++ ++ if (diff44Rate < diff48Rate) ++ actual_rate = (long)CLK_44EN_RATE; ++ else ++ actual_rate = (long)CLK_48EN_RATE; ++ } ++ return actual_rate; ++} ++ ++ ++static int clk_hifiberry_dacpro_set_rate(struct clk_hw *hw, ++ unsigned long rate, unsigned long parent_rate) ++{ ++ unsigned long actual_rate; ++ struct clk_hifiberry_hw *clk = to_hifiberry_clk(hw); ++ ++ actual_rate = (unsigned long)clk_hifiberry_dacpro_round_rate(hw, rate, ++ &parent_rate); ++ clk->mode = (actual_rate == CLK_44EN_RATE) ? 0 : 1; ++ return 0; ++} ++ ++ ++const struct clk_ops clk_hifiberry_dacpro_rate_ops = { ++ .recalc_rate = clk_hifiberry_dacpro_recalc_rate, ++ .round_rate = clk_hifiberry_dacpro_round_rate, ++ .set_rate = clk_hifiberry_dacpro_set_rate, ++}; ++ ++static int clk_hifiberry_dacpro_probe(struct platform_device *pdev) ++{ ++ int ret; ++ struct clk_hifiberry_hw *proclk; ++ struct clk *clk; ++ struct device *dev; ++ struct clk_init_data init; ++ ++ dev = &pdev->dev; ++ ++ proclk = kzalloc(sizeof(struct clk_hifiberry_hw), GFP_KERNEL); ++ if (!proclk) ++ return -ENOMEM; ++ ++ init.name = "clk-hifiberry-dacpro"; ++ init.ops = &clk_hifiberry_dacpro_rate_ops; ++ init.flags = CLK_IS_ROOT | CLK_IS_BASIC; ++ init.parent_names = NULL; ++ init.num_parents = 0; ++ ++ proclk->mode = 0; ++ proclk->hw.init = &init; ++ ++ clk = devm_clk_register(dev, &proclk->hw); ++ if (!IS_ERR(clk)) { ++ ret = of_clk_add_provider(dev->of_node, of_clk_src_simple_get, ++ clk); ++ } else { ++ dev_err(dev, "Fail to register clock driver\n"); ++ kfree(proclk); ++ ret = PTR_ERR(clk); ++ } ++ return ret; ++} ++ ++static int clk_hifiberry_dacpro_remove(struct platform_device *pdev) ++{ ++ of_clk_del_provider(pdev->dev.of_node); ++ return 0; ++} ++ ++static struct platform_driver clk_hifiberry_dacpro_driver = { ++ .probe = clk_hifiberry_dacpro_probe, ++ .remove = clk_hifiberry_dacpro_remove, ++ .driver = { ++ .name = "clk-hifiberry-dacpro", ++ .of_match_table = clk_hifiberry_dacpro_dt_ids, ++ }, ++}; ++ ++static int __init clk_hifiberry_dacpro_init(void) ++{ ++ return platform_driver_register(&clk_hifiberry_dacpro_driver); ++} ++core_initcall(clk_hifiberry_dacpro_init); ++ ++static void __exit clk_hifiberry_dacpro_exit(void) ++{ ++ platform_driver_unregister(&clk_hifiberry_dacpro_driver); ++} ++module_exit(clk_hifiberry_dacpro_exit); ++ ++MODULE_DESCRIPTION("HiFiBerry DAC Pro clock driver"); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:clk-hifiberry-dacpro"); +diff -Nur linux-4.1.13.orig/drivers/clk/Makefile linux-rpi/drivers/clk/Makefile +--- linux-4.1.13.orig/drivers/clk/Makefile 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/clk/Makefile 2015-11-29 09:42:36.747309443 +0100 +@@ -24,6 +24,7 @@ + obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o + obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o + obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o ++obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) += clk-hifiberry-dacpro.o + obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o + obj-$(CONFIG_COMMON_CLK_MAX_GEN) += clk-max-gen.o + obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o +diff -Nur linux-4.1.13.orig/drivers/clocksource/arm_arch_timer.c linux-rpi/drivers/clocksource/arm_arch_timer.c +--- linux-4.1.13.orig/drivers/clocksource/arm_arch_timer.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/clocksource/arm_arch_timer.c 2015-11-29 09:42:36.779307317 +0100 +@@ -882,3 +882,39 @@ + acpi_table_parse(ACPI_SIG_GTDT, arch_timer_acpi_init); + } + #endif ++ ++int __init dc4_arch_timer_init(void) ++{ ++ if (arch_timers_present & ARCH_CP15_TIMER) { ++ pr_warn("arch_timer: multiple nodes in dt, skipping\n"); ++ return -1; ++ } ++ ++ arch_timers_present |= ARCH_CP15_TIMER; ++ ++ /* Try to determine the frequency from the device tree or CNTFRQ */ ++ arch_timer_rate = 19200000; ++ ++ arch_timer_ppi[PHYS_SECURE_PPI] = IRQ_ARM_LOCAL_CNTPSIRQ; ++ arch_timer_ppi[PHYS_NONSECURE_PPI] = IRQ_ARM_LOCAL_CNTPNSIRQ; ++ arch_timer_ppi[VIRT_PPI] = IRQ_ARM_LOCAL_CNTVIRQ; ++ arch_timer_ppi[HYP_PPI] = IRQ_ARM_LOCAL_CNTHPIRQ; ++ ++ /* ++ * If HYP mode is available, we know that the physical timer ++ * has been configured to be accessible from PL1. Use it, so ++ * that a guest can use the virtual timer instead. ++ * ++ * If no interrupt provided for virtual timer, we'll have to ++ * stick to the physical timer. It'd better be accessible... ++ */ ++ if (is_hyp_mode_available() || !arch_timer_ppi[VIRT_PPI]) { ++ arch_timer_use_virtual = false; ++ } ++ ++ arch_timer_c3stop = 0; ++ ++ arch_timer_register(); ++ arch_timer_common_init(); ++ return 0; ++} +diff -Nur linux-4.1.13.orig/drivers/cpufreq/bcm2835-cpufreq.c linux-rpi/drivers/cpufreq/bcm2835-cpufreq.c +--- linux-4.1.13.orig/drivers/cpufreq/bcm2835-cpufreq.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/cpufreq/bcm2835-cpufreq.c 2015-11-29 09:42:36.783307051 +0100 +@@ -0,0 +1,213 @@ ++/***************************************************************************** ++* Copyright 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++/***************************************************************************** ++* FILENAME: bcm2835-cpufreq.h ++* DESCRIPTION: This driver dynamically manages the CPU Frequency of the ARM ++* processor. Messages are sent to Videocore either setting or requesting the ++* frequency of the ARM in order to match an appropiate frequency to the current ++* usage of the processor. The policy which selects the frequency to use is ++* defined in the kernel .config file, but can be changed during runtime. ++*****************************************************************************/ ++ ++/* ---------- INCLUDES ---------- */ ++#include ++#include ++#include ++#include ++#include ++ ++/* ---------- DEFINES ---------- */ ++/*#define CPUFREQ_DEBUG_ENABLE*/ /* enable debugging */ ++#define MODULE_NAME "bcm2835-cpufreq" ++ ++#define VCMSG_ID_ARM_CLOCK 0x000000003 /* Clock/Voltage ID's */ ++ ++/* debug printk macros */ ++#ifdef CPUFREQ_DEBUG_ENABLE ++#define print_debug(fmt,...) pr_debug("%s:%s:%d: "fmt, MODULE_NAME, __func__, __LINE__, ##__VA_ARGS__) ++#else ++#define print_debug(fmt,...) ++#endif ++#define print_err(fmt,...) pr_err("%s:%s:%d: "fmt, MODULE_NAME, __func__,__LINE__, ##__VA_ARGS__) ++#define print_info(fmt,...) pr_info("%s: "fmt, MODULE_NAME, ##__VA_ARGS__) ++ ++/* ---------- GLOBALS ---------- */ ++static struct cpufreq_driver bcm2835_cpufreq_driver; /* the cpufreq driver global */ ++ ++static struct cpufreq_frequency_table bcm2835_freq_table[] = { ++ {0, 0, 0}, ++ {0, 0, 0}, ++ {0, 0, CPUFREQ_TABLE_END}, ++}; ++ ++/* ++ =============================================== ++ clk_rate either gets or sets the clock rates. ++ =============================================== ++*/ ++ ++static int bcm2835_cpufreq_clock_property(u32 tag, u32 id, u32 *val) ++{ ++ struct rpi_firmware *fw = rpi_firmware_get(NULL); ++ struct { ++ u32 id; ++ u32 val; ++ } packet; ++ int ret; ++ ++ packet.id = id; ++ packet.val = *val; ++ ret = rpi_firmware_property(fw, tag, &packet, sizeof(packet)); ++ if (ret) ++ return ret; ++ ++ *val = packet.val; ++ ++ return 0; ++} ++ ++static uint32_t bcm2835_cpufreq_set_clock(int cur_rate, int arm_rate) ++{ ++ u32 rate = arm_rate * 1000; ++ int ret; ++ ++ ret = bcm2835_cpufreq_clock_property(RPI_FIRMWARE_SET_CLOCK_RATE, VCMSG_ID_ARM_CLOCK, &rate); ++ if (ret) { ++ print_err("Failed to set clock: %d (%d)\n", arm_rate, ret); ++ return 0; ++ } ++ ++ rate /= 1000; ++ print_debug("Setting new frequency = %d -> %d (actual %d)\n", cur_rate, arm_rate, rate); ++ ++ return rate; ++} ++ ++static uint32_t bcm2835_cpufreq_get_clock(int tag) ++{ ++ u32 rate; ++ int ret; ++ ++ ret = bcm2835_cpufreq_clock_property(tag, VCMSG_ID_ARM_CLOCK, &rate); ++ if (ret) { ++ print_err("Failed to get clock (%d)\n", ret); ++ return 0; ++ } ++ ++ rate /= 1000; ++ print_debug("%s frequency = %u\n", ++ tag == RPI_FIRMWARE_GET_CLOCK_RATE ? "Current": ++ tag == RPI_FIRMWARE_GET_MIN_CLOCK_RATE ? "Min": ++ tag == RPI_FIRMWARE_GET_MAX_CLOCK_RATE ? "Max": ++ "Unexpected", rate); ++ ++ return rate; ++} ++ ++/* ++ ==================================================== ++ Module Initialisation registers the cpufreq driver ++ ==================================================== ++*/ ++static int __init bcm2835_cpufreq_module_init(void) ++{ ++ print_debug("IN\n"); ++ return cpufreq_register_driver(&bcm2835_cpufreq_driver); ++} ++ ++/* ++ ============= ++ Module exit ++ ============= ++*/ ++static void __exit bcm2835_cpufreq_module_exit(void) ++{ ++ print_debug("IN\n"); ++ cpufreq_unregister_driver(&bcm2835_cpufreq_driver); ++ return; ++} ++ ++/* ++ ============================================================== ++ Initialisation function sets up the CPU policy for first use ++ ============================================================== ++*/ ++static int bcm2835_cpufreq_driver_init(struct cpufreq_policy *policy) ++{ ++ /* measured value of how long it takes to change frequency */ ++ const unsigned int transition_latency = 355000; /* ns */ ++ ++ if (!rpi_firmware_get(NULL)) { ++ print_err("Firmware is not available\n"); ++ return -ENODEV; ++ } ++ ++ /* now find out what the maximum and minimum frequencies are */ ++ bcm2835_freq_table[0].frequency = bcm2835_cpufreq_get_clock(RPI_FIRMWARE_GET_MIN_CLOCK_RATE); ++ bcm2835_freq_table[1].frequency = bcm2835_cpufreq_get_clock(RPI_FIRMWARE_GET_MAX_CLOCK_RATE); ++ ++ print_info("min=%d max=%d\n", bcm2835_freq_table[0].frequency, bcm2835_freq_table[1].frequency); ++ return cpufreq_generic_init(policy, bcm2835_freq_table, transition_latency); ++} ++ ++/* ++ ===================================================================== ++ Target index function chooses the requested frequency from the table ++ ===================================================================== ++*/ ++ ++static int bcm2835_cpufreq_driver_target_index(struct cpufreq_policy *policy, unsigned int state) ++{ ++ unsigned int target_freq = bcm2835_freq_table[state].frequency; ++ unsigned int cur = bcm2835_cpufreq_set_clock(policy->cur, target_freq); ++ ++ if (!cur) ++ { ++ print_err("Error occurred setting a new frequency (%d)\n", target_freq); ++ return -EINVAL; ++ } ++ print_debug("%s: %i: freq %d->%d\n", policy->governor->name, state, policy->cur, cur); ++ return 0; ++} ++ ++/* ++ ====================================================== ++ Get function returns the current frequency from table ++ ====================================================== ++*/ ++ ++static unsigned int bcm2835_cpufreq_driver_get(unsigned int cpu) ++{ ++ unsigned int actual_rate = bcm2835_cpufreq_get_clock(RPI_FIRMWARE_GET_CLOCK_RATE); ++ print_debug("cpu%d: freq=%d\n", cpu, actual_rate); ++ return actual_rate <= bcm2835_freq_table[0].frequency ? bcm2835_freq_table[0].frequency : bcm2835_freq_table[1].frequency; ++} ++ ++/* the CPUFreq driver */ ++static struct cpufreq_driver bcm2835_cpufreq_driver = { ++ .name = "BCM2835 CPUFreq", ++ .init = bcm2835_cpufreq_driver_init, ++ .verify = cpufreq_generic_frequency_table_verify, ++ .target_index = bcm2835_cpufreq_driver_target_index, ++ .get = bcm2835_cpufreq_driver_get, ++ .attr = cpufreq_generic_attr, ++}; ++ ++MODULE_AUTHOR("Dorian Peake and Dom Cobley"); ++MODULE_DESCRIPTION("CPU frequency driver for BCM2835 chip"); ++MODULE_LICENSE("GPL"); ++ ++module_init(bcm2835_cpufreq_module_init); ++module_exit(bcm2835_cpufreq_module_exit); +diff -Nur linux-4.1.13.orig/drivers/cpufreq/Kconfig.arm linux-rpi/drivers/cpufreq/Kconfig.arm +--- linux-4.1.13.orig/drivers/cpufreq/Kconfig.arm 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/cpufreq/Kconfig.arm 2015-11-29 09:42:36.783307051 +0100 +@@ -258,6 +258,15 @@ + help + This adds the CPUFreq driver support for SPEAr SOCs. + ++config ARM_BCM2835_CPUFREQ ++ depends on RASPBERRYPI_FIRMWARE ++ bool "BCM2835 Driver" ++ default y ++ help ++ This adds the CPUFreq driver for BCM2835 ++ ++ If in doubt, say N. ++ + config ARM_TEGRA_CPUFREQ + bool "TEGRA CPUFreq support" + depends on ARCH_TEGRA +diff -Nur linux-4.1.13.orig/drivers/cpufreq/Makefile linux-rpi/drivers/cpufreq/Makefile +--- linux-4.1.13.orig/drivers/cpufreq/Makefile 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/cpufreq/Makefile 2015-11-29 09:42:36.783307051 +0100 +@@ -77,6 +77,7 @@ + obj-$(CONFIG_ARM_SA1100_CPUFREQ) += sa1100-cpufreq.o + obj-$(CONFIG_ARM_SA1110_CPUFREQ) += sa1110-cpufreq.o + obj-$(CONFIG_ARM_SPEAR_CPUFREQ) += spear-cpufreq.o ++obj-$(CONFIG_ARM_BCM2835_CPUFREQ) += bcm2835-cpufreq.o + obj-$(CONFIG_ARM_TEGRA_CPUFREQ) += tegra-cpufreq.o + obj-$(CONFIG_ARM_VEXPRESS_SPC_CPUFREQ) += vexpress-spc-cpufreq.o + +diff -Nur linux-4.1.13.orig/drivers/dma/bcm2708-dmaengine.c linux-rpi/drivers/dma/bcm2708-dmaengine.c +--- linux-4.1.13.orig/drivers/dma/bcm2708-dmaengine.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/dma/bcm2708-dmaengine.c 2015-11-29 09:42:36.815304925 +0100 +@@ -0,0 +1,1314 @@ ++/* ++ * BCM2835 DMA engine support ++ * ++ * This driver supports cyclic and scatter/gather DMA transfers. ++ * ++ * Author: Florian Meier ++ * Gellert Weisz ++ * Copyright 2013-2014 ++ * ++ * Based on ++ * OMAP DMAengine support by Russell King ++ * ++ * BCM2708 DMA Driver ++ * Copyright (C) 2010 Broadcom ++ * ++ * Raspberry Pi PCM I2S ALSA Driver ++ * Copyright (c) by Phil Poole 2013 ++ * ++ * MARVELL MMP Peripheral DMA Driver ++ * Copyright 2012 Marvell International Ltd. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "virt-dma.h" ++ ++static unsigned dma_debug; ++ ++/* ++ * Legacy DMA API ++ */ ++ ++#ifdef CONFIG_DMA_BCM2708_LEGACY ++ ++#define CACHE_LINE_MASK 31 ++#define DEFAULT_DMACHAN_BITMAP 0x10 /* channel 4 only */ ++ ++/* valid only for channels 0 - 14, 15 has its own base address */ ++#define BCM2708_DMA_CHAN(n) ((n) << 8) /* base address */ ++#define BCM2708_DMA_CHANIO(dma_base, n) \ ++ ((void __iomem *)((char *)(dma_base) + BCM2708_DMA_CHAN(n))) ++ ++struct vc_dmaman { ++ void __iomem *dma_base; ++ u32 chan_available; /* bitmap of available channels */ ++ u32 has_feature[BCM_DMA_FEATURE_COUNT]; /* bitmap of feature presence */ ++ struct mutex lock; ++}; ++ ++static struct device *dmaman_dev; /* we assume there's only one! */ ++static struct vc_dmaman *g_dmaman; /* DMA manager */ ++static int dmachans = -1; /* module parameter */ ++ ++/* DMA Auxiliary Functions */ ++ ++/* A DMA buffer on an arbitrary boundary may separate a cache line into a ++ section inside the DMA buffer and another section outside it. ++ Even if we flush DMA buffers from the cache there is always the chance that ++ during a DMA someone will access the part of a cache line that is outside ++ the DMA buffer - which will then bring in unwelcome data. ++ Without being able to dictate our own buffer pools we must insist that ++ DMA buffers consist of a whole number of cache lines. ++*/ ++extern int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len) ++{ ++ int i; ++ ++ for (i = 0; i < sg_len; i++) { ++ if (sg_ptr[i].offset & CACHE_LINE_MASK || ++ sg_ptr[i].length & CACHE_LINE_MASK) ++ return 0; ++ } ++ ++ return 1; ++} ++EXPORT_SYMBOL_GPL(bcm_sg_suitable_for_dma); ++ ++extern void bcm_dma_start(void __iomem *dma_chan_base, ++ dma_addr_t control_block) ++{ ++ dsb(); /* ARM data synchronization (push) operation */ ++ ++ writel(control_block, dma_chan_base + BCM2708_DMA_ADDR); ++ writel(BCM2708_DMA_ACTIVE, dma_chan_base + BCM2708_DMA_CS); ++} ++EXPORT_SYMBOL_GPL(bcm_dma_start); ++ ++extern void bcm_dma_wait_idle(void __iomem *dma_chan_base) ++{ ++ dsb(); ++ ++ /* ugly busy wait only option for now */ ++ while (readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE) ++ cpu_relax(); ++} ++EXPORT_SYMBOL_GPL(bcm_dma_wait_idle); ++ ++extern bool bcm_dma_is_busy(void __iomem *dma_chan_base) ++{ ++ dsb(); ++ ++ return readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE; ++} ++EXPORT_SYMBOL_GPL(bcm_dma_is_busy); ++ ++/* Complete an ongoing DMA (assuming its results are to be ignored) ++ Does nothing if there is no DMA in progress. ++ This routine waits for the current AXI transfer to complete before ++ terminating the current DMA. If the current transfer is hung on a DREQ used ++ by an uncooperative peripheral the AXI transfer may never complete. In this ++ case the routine times out and return a non-zero error code. ++ Use of this routine doesn't guarantee that the ongoing or aborted DMA ++ does not produce an interrupt. ++*/ ++extern int bcm_dma_abort(void __iomem *dma_chan_base) ++{ ++ unsigned long int cs; ++ int rc = 0; ++ ++ cs = readl(dma_chan_base + BCM2708_DMA_CS); ++ ++ if (BCM2708_DMA_ACTIVE & cs) { ++ long int timeout = 10000; ++ ++ /* write 0 to the active bit - pause the DMA */ ++ writel(0, dma_chan_base + BCM2708_DMA_CS); ++ ++ /* wait for any current AXI transfer to complete */ ++ while (0 != (cs & BCM2708_DMA_ISPAUSED) && --timeout >= 0) ++ cs = readl(dma_chan_base + BCM2708_DMA_CS); ++ ++ if (0 != (cs & BCM2708_DMA_ISPAUSED)) { ++ /* we'll un-pause when we set of our next DMA */ ++ rc = -ETIMEDOUT; ++ ++ } else if (BCM2708_DMA_ACTIVE & cs) { ++ /* terminate the control block chain */ ++ writel(0, dma_chan_base + BCM2708_DMA_NEXTCB); ++ ++ /* abort the whole DMA */ ++ writel(BCM2708_DMA_ABORT | BCM2708_DMA_ACTIVE, ++ dma_chan_base + BCM2708_DMA_CS); ++ } ++ } ++ ++ return rc; ++} ++EXPORT_SYMBOL_GPL(bcm_dma_abort); ++ ++ /* DMA Manager Device Methods */ ++ ++static void vc_dmaman_init(struct vc_dmaman *dmaman, void __iomem *dma_base, ++ u32 chans_available) ++{ ++ dmaman->dma_base = dma_base; ++ dmaman->chan_available = chans_available; ++ dmaman->has_feature[BCM_DMA_FEATURE_FAST_ORD] = 0x0c; /* 2 & 3 */ ++ dmaman->has_feature[BCM_DMA_FEATURE_BULK_ORD] = 0x01; /* 0 */ ++ dmaman->has_feature[BCM_DMA_FEATURE_NORMAL_ORD] = 0xfe; /* 1 to 7 */ ++ dmaman->has_feature[BCM_DMA_FEATURE_LITE_ORD] = 0x7f00; /* 8 to 14 */ ++} ++ ++static int vc_dmaman_chan_alloc(struct vc_dmaman *dmaman, ++ unsigned required_feature_set) ++{ ++ u32 chans; ++ int chan = 0; ++ int feature; ++ ++ chans = dmaman->chan_available; ++ for (feature = 0; feature < BCM_DMA_FEATURE_COUNT; feature++) ++ /* select the subset of available channels with the desired ++ features */ ++ if (required_feature_set & (1 << feature)) ++ chans &= dmaman->has_feature[feature]; ++ ++ if (!chans) ++ return -ENOENT; ++ ++ /* return the ordinal of the first channel in the bitmap */ ++ while (chans != 0 && (chans & 1) == 0) { ++ chans >>= 1; ++ chan++; ++ } ++ /* claim the channel */ ++ dmaman->chan_available &= ~(1 << chan); ++ ++ return chan; ++} ++ ++static int vc_dmaman_chan_free(struct vc_dmaman *dmaman, int chan) ++{ ++ if (chan < 0) ++ return -EINVAL; ++ ++ if ((1 << chan) & dmaman->chan_available) ++ return -EIDRM; ++ ++ dmaman->chan_available |= (1 << chan); ++ ++ return 0; ++} ++ ++/* DMA Manager Monitor */ ++ ++extern int bcm_dma_chan_alloc(unsigned required_feature_set, ++ void __iomem **out_dma_base, int *out_dma_irq) ++{ ++ struct vc_dmaman *dmaman = g_dmaman; ++ struct platform_device *pdev = to_platform_device(dmaman_dev); ++ struct resource *r; ++ int chan; ++ ++ if (!dmaman_dev) ++ return -ENODEV; ++ ++ mutex_lock(&dmaman->lock); ++ chan = vc_dmaman_chan_alloc(dmaman, required_feature_set); ++ if (chan < 0) ++ goto out; ++ ++ r = platform_get_resource(pdev, IORESOURCE_IRQ, (unsigned int)chan); ++ if (!r) { ++ dev_err(dmaman_dev, "failed to get irq for DMA channel %d\n", ++ chan); ++ vc_dmaman_chan_free(dmaman, chan); ++ chan = -ENOENT; ++ goto out; ++ } ++ ++ *out_dma_base = BCM2708_DMA_CHANIO(dmaman->dma_base, chan); ++ *out_dma_irq = r->start; ++ dev_dbg(dmaman_dev, ++ "Legacy API allocated channel=%d, base=%p, irq=%i\n", ++ chan, *out_dma_base, *out_dma_irq); ++ ++out: ++ mutex_unlock(&dmaman->lock); ++ ++ return chan; ++} ++EXPORT_SYMBOL_GPL(bcm_dma_chan_alloc); ++ ++extern int bcm_dma_chan_free(int channel) ++{ ++ struct vc_dmaman *dmaman = g_dmaman; ++ int rc; ++ ++ if (!dmaman_dev) ++ return -ENODEV; ++ ++ mutex_lock(&dmaman->lock); ++ rc = vc_dmaman_chan_free(dmaman, channel); ++ mutex_unlock(&dmaman->lock); ++ ++ return rc; ++} ++EXPORT_SYMBOL_GPL(bcm_dma_chan_free); ++ ++static int bcm_dmaman_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct vc_dmaman *dmaman; ++ struct resource *r; ++ void __iomem *dma_base; ++ uint32_t val; ++ ++ if (!of_property_read_u32(dev->of_node, ++ "brcm,dma-channel-mask", &val)) ++ dmachans = val; ++ else if (dmachans == -1) ++ dmachans = DEFAULT_DMACHAN_BITMAP; ++ ++ dmaman = devm_kzalloc(dev, sizeof(*dmaman), GFP_KERNEL); ++ if (!dmaman) ++ return -ENOMEM; ++ ++ mutex_init(&dmaman->lock); ++ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ dma_base = devm_ioremap_resource(dev, r); ++ if (IS_ERR(dma_base)) ++ return PTR_ERR(dma_base); ++ ++ vc_dmaman_init(dmaman, dma_base, dmachans); ++ g_dmaman = dmaman; ++ dmaman_dev = dev; ++ ++ dev_info(dev, "DMA legacy API manager at %p, dmachans=0x%x\n", ++ dma_base, dmachans); ++ ++ return 0; ++} ++ ++static int bcm_dmaman_remove(struct platform_device *pdev) ++{ ++ dmaman_dev = NULL; ++ ++ return 0; ++} ++ ++#else /* CONFIG_DMA_BCM2708_LEGACY */ ++ ++static int bcm_dmaman_remove(struct platform_device *pdev) ++{ ++ return 0; ++} ++ ++#endif /* CONFIG_DMA_BCM2708_LEGACY */ ++ ++/* ++ * DMA engine ++ */ ++ ++struct bcm2835_dmadev { ++ struct dma_device ddev; ++ spinlock_t lock; ++ void __iomem *base; ++ struct device_dma_parameters dma_parms; ++}; ++ ++struct bcm2835_dma_cb { ++ uint32_t info; ++ uint32_t src; ++ uint32_t dst; ++ uint32_t length; ++ uint32_t stride; ++ uint32_t next; ++ uint32_t pad[2]; ++}; ++ ++struct bcm2835_chan { ++ struct virt_dma_chan vc; ++ struct list_head node; ++ ++ struct dma_slave_config cfg; ++ bool cyclic; ++ ++ int ch; ++ struct bcm2835_desc *desc; ++ ++ void __iomem *chan_base; ++ int irq_number; ++ ++ unsigned int dreq; ++}; ++ ++struct bcm2835_desc { ++ struct virt_dma_desc vd; ++ enum dma_transfer_direction dir; ++ ++ unsigned int control_block_size; ++ struct bcm2835_dma_cb *control_block_base; ++ dma_addr_t control_block_base_phys; ++ ++ unsigned int frames; ++ size_t size; ++}; ++ ++#define BCM2835_DMA_CS 0x00 ++#define BCM2835_DMA_ADDR 0x04 ++#define BCM2835_DMA_SOURCE_AD 0x0c ++#define BCM2835_DMA_DEST_AD 0x10 ++#define BCM2835_DMA_NEXTCB 0x1C ++ ++/* DMA CS Control and Status bits */ ++#define BCM2835_DMA_ACTIVE BIT(0) ++#define BCM2835_DMA_INT BIT(2) ++#define BCM2835_DMA_ISPAUSED BIT(4) /* Pause requested or not active */ ++#define BCM2835_DMA_ISHELD BIT(5) /* Is held by DREQ flow control */ ++#define BCM2835_DMA_ERR BIT(8) ++#define BCM2835_DMA_ABORT BIT(30) /* Stop current CB, go to next, WO */ ++#define BCM2835_DMA_RESET BIT(31) /* WO, self clearing */ ++ ++#define BCM2835_DMA_INT_EN BIT(0) ++#define BCM2835_DMA_WAIT_RESP BIT(3) ++#define BCM2835_DMA_D_INC BIT(4) ++#define BCM2835_DMA_D_WIDTH BIT(5) ++#define BCM2835_DMA_D_DREQ BIT(6) ++#define BCM2835_DMA_S_INC BIT(8) ++#define BCM2835_DMA_S_WIDTH BIT(9) ++#define BCM2835_DMA_S_DREQ BIT(10) ++ ++#define BCM2835_DMA_PER_MAP(x) ((x) << 16) ++#define BCM2835_DMA_WAITS(x) (((x)&0x1f) << 21) ++ ++#define SDHCI_BCM_DMA_WAITS 0 /* delays slowing DMA transfers: 0-31 */ ++ ++#define BCM2835_DMA_DATA_TYPE_S8 1 ++#define BCM2835_DMA_DATA_TYPE_S16 2 ++#define BCM2835_DMA_DATA_TYPE_S32 4 ++#define BCM2835_DMA_DATA_TYPE_S128 16 ++ ++#define BCM2835_DMA_BULK_MASK BIT(0) ++#define BCM2835_DMA_FIQ_MASK (BIT(2) | BIT(3)) ++ ++ ++/* Valid only for channels 0 - 14, 15 has its own base address */ ++#define BCM2835_DMA_CHAN(n) ((n) << 8) /* Base address */ ++#define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n)) ++ ++#define MAX_LITE_TRANSFER 32768 ++#define MAX_NORMAL_TRANSFER 1073741824 ++ ++static inline struct bcm2835_dmadev *to_bcm2835_dma_dev(struct dma_device *d) ++{ ++ return container_of(d, struct bcm2835_dmadev, ddev); ++} ++ ++static inline struct bcm2835_chan *to_bcm2835_dma_chan(struct dma_chan *c) ++{ ++ return container_of(c, struct bcm2835_chan, vc.chan); ++} ++ ++static inline struct bcm2835_desc *to_bcm2835_dma_desc( ++ struct dma_async_tx_descriptor *t) ++{ ++ return container_of(t, struct bcm2835_desc, vd.tx); ++} ++ ++#if 0 ++static void dma_dumpregs(struct bcm2835_chan *c) ++{ ++ pr_debug("-------------DMA DUMPREGS-------------\n"); ++ pr_debug("CS= %u\n", ++ readl(c->chan_base + BCM2835_DMA_CS)); ++ pr_debug("ADDR= %u\n", ++ readl(c->chan_base + BCM2835_DMA_ADDR)); ++ pr_debug("SOURCE_ADDR= %u\n", ++ readl(c->chan_base + BCM2835_DMA_SOURCE_AD)); ++ pr_debug("DEST_AD= %u\n", ++ readl(c->chan_base + BCM2835_DMA_DEST_AD)); ++ pr_debug("NEXTCB= %u\n", ++ readl(c->chan_base + BCM2835_DMA_NEXTCB)); ++ pr_debug("--------------------------------------\n"); ++} ++#endif ++ ++static void bcm2835_dma_desc_free(struct virt_dma_desc *vd) ++{ ++ struct bcm2835_desc *desc = container_of(vd, struct bcm2835_desc, vd); ++ dma_free_coherent(desc->vd.tx.chan->device->dev, ++ desc->control_block_size, ++ desc->control_block_base, ++ desc->control_block_base_phys); ++ kfree(desc); ++} ++ ++static int bcm2835_dma_abort(void __iomem *chan_base) ++{ ++ unsigned long cs; ++ long int timeout = 10000; ++ ++ cs = readl(chan_base + BCM2835_DMA_CS); ++ if (!(cs & BCM2835_DMA_ACTIVE)) ++ return 0; ++ ++ /* Write 0 to the active bit - Pause the DMA */ ++ writel(0, chan_base + BCM2835_DMA_CS); ++ ++ /* Wait for any current AXI transfer to complete */ ++ while ((cs & BCM2835_DMA_ISPAUSED) && --timeout) { ++ cpu_relax(); ++ cs = readl(chan_base + BCM2835_DMA_CS); ++ } ++ ++ /* We'll un-pause when we set of our next DMA */ ++ if (!timeout) ++ return -ETIMEDOUT; ++ ++ if (!(cs & BCM2835_DMA_ACTIVE)) ++ return 0; ++ ++ /* Terminate the control block chain */ ++ writel(0, chan_base + BCM2835_DMA_NEXTCB); ++ ++ /* Abort the whole DMA */ ++ writel(BCM2835_DMA_ABORT | BCM2835_DMA_ACTIVE, ++ chan_base + BCM2835_DMA_CS); ++ ++ return 0; ++} ++ ++ ++static void bcm2835_dma_start_desc(struct bcm2835_chan *c) ++{ ++ struct virt_dma_desc *vd = vchan_next_desc(&c->vc); ++ struct bcm2835_desc *d; ++ ++ if (!vd) { ++ c->desc = NULL; ++ return; ++ } ++ ++ list_del(&vd->node); ++ ++ c->desc = d = to_bcm2835_dma_desc(&vd->tx); ++ ++ writel(d->control_block_base_phys, c->chan_base + BCM2835_DMA_ADDR); ++ writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS); ++ ++} ++ ++static irqreturn_t bcm2835_dma_callback(int irq, void *data) ++{ ++ struct bcm2835_chan *c = data; ++ struct bcm2835_desc *d; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&c->vc.lock, flags); ++ ++ /* Acknowledge interrupt */ ++ writel(BCM2835_DMA_INT, c->chan_base + BCM2835_DMA_CS); ++ ++ d = c->desc; ++ ++ if (d) { ++ if (c->cyclic) { ++ vchan_cyclic_callback(&d->vd); ++ ++ /* Keep the DMA engine running */ ++ writel(BCM2835_DMA_ACTIVE, ++ c->chan_base + BCM2835_DMA_CS); ++ ++ } else { ++ vchan_cookie_complete(&c->desc->vd); ++ bcm2835_dma_start_desc(c); ++ } ++ } ++ ++ spin_unlock_irqrestore(&c->vc.lock, flags); ++ ++ return IRQ_HANDLED; ++} ++ ++static int bcm2835_dma_alloc_chan_resources(struct dma_chan *chan) ++{ ++ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); ++ int ret; ++ ++ dev_dbg(c->vc.chan.device->dev, ++ "Allocating DMA channel %d\n", c->ch); ++ ++ ret = request_irq(c->irq_number, ++ bcm2835_dma_callback, 0, "DMA IRQ", c); ++ ++ return ret; ++} ++ ++static void bcm2835_dma_free_chan_resources(struct dma_chan *chan) ++{ ++ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); ++ ++ vchan_free_chan_resources(&c->vc); ++ free_irq(c->irq_number, c); ++ ++ dev_dbg(c->vc.chan.device->dev, "Freeing DMA channel %u\n", c->ch); ++} ++ ++static size_t bcm2835_dma_desc_size(struct bcm2835_desc *d) ++{ ++ return d->size; ++} ++ ++static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr) ++{ ++ unsigned int i; ++ size_t size; ++ ++ for (size = i = 0; i < d->frames; i++) { ++ struct bcm2835_dma_cb *control_block = ++ &d->control_block_base[i]; ++ size_t this_size = control_block->length; ++ dma_addr_t dma; ++ ++ if (d->dir == DMA_DEV_TO_MEM) ++ dma = control_block->dst; ++ else ++ dma = control_block->src; ++ ++ if (size) ++ size += this_size; ++ else if (addr >= dma && addr < dma + this_size) ++ size += dma + this_size - addr; ++ } ++ ++ return size; ++} ++ ++static enum dma_status bcm2835_dma_tx_status(struct dma_chan *chan, ++ dma_cookie_t cookie, struct dma_tx_state *txstate) ++{ ++ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); ++ struct bcm2835_desc *d; ++ struct virt_dma_desc *vd; ++ enum dma_status ret; ++ unsigned long flags; ++ dma_addr_t pos; ++ ++ ret = dma_cookie_status(chan, cookie, txstate); ++ if (ret == DMA_COMPLETE || !txstate) ++ return ret; ++ ++ spin_lock_irqsave(&c->vc.lock, flags); ++ vd = vchan_find_desc(&c->vc, cookie); ++ if (vd) { ++ txstate->residue = ++ bcm2835_dma_desc_size(to_bcm2835_dma_desc(&vd->tx)); ++ } else if (c->desc && c->desc->vd.tx.cookie == cookie) { ++ d = c->desc; ++ ++ if (d->dir == DMA_MEM_TO_DEV) ++ pos = readl(c->chan_base + BCM2835_DMA_SOURCE_AD); ++ else if (d->dir == DMA_DEV_TO_MEM) ++ pos = readl(c->chan_base + BCM2835_DMA_DEST_AD); ++ else ++ pos = 0; ++ ++ txstate->residue = bcm2835_dma_desc_size_pos(d, pos); ++ } else { ++ txstate->residue = 0; ++ } ++ ++ spin_unlock_irqrestore(&c->vc.lock, flags); ++ ++ return ret; ++} ++ ++static void bcm2835_dma_issue_pending(struct dma_chan *chan) ++{ ++ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&c->vc.lock, flags); ++ if (vchan_issue_pending(&c->vc) && !c->desc) ++ bcm2835_dma_start_desc(c); ++ ++ spin_unlock_irqrestore(&c->vc.lock, flags); ++} ++ ++static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic( ++ struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, ++ size_t period_len, enum dma_transfer_direction direction, ++ unsigned long flags) ++{ ++ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); ++ enum dma_slave_buswidth dev_width; ++ struct bcm2835_desc *d; ++ dma_addr_t dev_addr; ++ unsigned int es, sync_type; ++ unsigned int frame, max_size; ++ ++ /* Grab configuration */ ++ if (!is_slave_direction(direction)) { ++ dev_err(chan->device->dev, "%s: bad direction?\n", __func__); ++ return NULL; ++ } ++ ++ if (direction == DMA_DEV_TO_MEM) { ++ dev_addr = c->cfg.src_addr; ++ dev_width = c->cfg.src_addr_width; ++ sync_type = BCM2835_DMA_S_DREQ; ++ } else { ++ dev_addr = c->cfg.dst_addr; ++ dev_width = c->cfg.dst_addr_width; ++ sync_type = BCM2835_DMA_D_DREQ; ++ } ++ ++ /* Bus width translates to the element size (ES) */ ++ switch (dev_width) { ++ case DMA_SLAVE_BUSWIDTH_4_BYTES: ++ es = BCM2835_DMA_DATA_TYPE_S32; ++ break; ++ default: ++ return NULL; ++ } ++ ++ /* Now allocate and setup the descriptor. */ ++ d = kzalloc(sizeof(*d), GFP_NOWAIT); ++ if (!d) ++ return NULL; ++ ++ d->dir = direction; ++ ++ if (c->ch >= 8) /* we have a LITE channel */ ++ max_size = MAX_LITE_TRANSFER; ++ else ++ max_size = MAX_NORMAL_TRANSFER; ++ period_len = min(period_len, max_size); ++ ++ d->frames = (buf_len-1) / period_len + 1; ++ ++ /* Allocate memory for control blocks */ ++ d->control_block_size = d->frames * sizeof(struct bcm2835_dma_cb); ++ d->control_block_base = dma_zalloc_coherent(chan->device->dev, ++ d->control_block_size, &d->control_block_base_phys, ++ GFP_NOWAIT); ++ ++ if (!d->control_block_base) { ++ kfree(d); ++ return NULL; ++ } ++ ++ /* ++ * Iterate over all frames, create a control block ++ * for each frame and link them together. ++ */ ++ for (frame = 0; frame < d->frames; frame++) { ++ struct bcm2835_dma_cb *control_block = ++ &d->control_block_base[frame]; ++ ++ /* Setup adresses */ ++ if (d->dir == DMA_DEV_TO_MEM) { ++ control_block->info = BCM2835_DMA_D_INC; ++ control_block->src = dev_addr; ++ control_block->dst = buf_addr + frame * period_len; ++ } else { ++ control_block->info = BCM2835_DMA_S_INC; ++ control_block->src = buf_addr + frame * period_len; ++ control_block->dst = dev_addr; ++ } ++ ++ /* Enable interrupt */ ++ control_block->info |= BCM2835_DMA_INT_EN; ++ ++ /* Setup synchronization */ ++ if (sync_type != 0) ++ control_block->info |= sync_type; ++ ++ /* Setup DREQ channel */ ++ if (c->cfg.slave_id != 0) ++ control_block->info |= ++ BCM2835_DMA_PER_MAP(c->cfg.slave_id); ++ ++ /* Length of a frame */ ++ if (frame != d->frames-1) ++ control_block->length = period_len; ++ else ++ control_block->length = buf_len - (d->frames - 1) * period_len; ++ ++ d->size += control_block->length; ++ ++ /* ++ * Next block is the next frame. ++ * This function is called on cyclic DMA transfers. ++ * Therefore, wrap around at number of frames. ++ */ ++ control_block->next = d->control_block_base_phys + ++ sizeof(struct bcm2835_dma_cb) ++ * ((frame + 1) % d->frames); ++ } ++ ++ c->cyclic = true; ++ ++ return vchan_tx_prep(&c->vc, &d->vd, flags); ++} ++ ++ ++static struct dma_async_tx_descriptor *bcm2835_dma_prep_slave_sg( ++ struct dma_chan *chan, struct scatterlist *sgl, ++ unsigned int sg_len, enum dma_transfer_direction direction, ++ unsigned long flags, void *context) ++{ ++ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); ++ enum dma_slave_buswidth dev_width; ++ struct bcm2835_desc *d; ++ dma_addr_t dev_addr; ++ struct scatterlist *sgent; ++ unsigned int es, sync_type; ++ unsigned int i, j, splitct, max_size; ++ ++ if (!is_slave_direction(direction)) { ++ dev_err(chan->device->dev, "%s: bad direction?\n", __func__); ++ return NULL; ++ } ++ ++ if (direction == DMA_DEV_TO_MEM) { ++ dev_addr = c->cfg.src_addr; ++ dev_width = c->cfg.src_addr_width; ++ sync_type = BCM2835_DMA_S_DREQ; ++ } else { ++ dev_addr = c->cfg.dst_addr; ++ dev_width = c->cfg.dst_addr_width; ++ sync_type = BCM2835_DMA_D_DREQ; ++ } ++ ++ /* Bus width translates to the element size (ES) */ ++ switch (dev_width) { ++ case DMA_SLAVE_BUSWIDTH_4_BYTES: ++ es = BCM2835_DMA_DATA_TYPE_S32; ++ break; ++ default: ++ return NULL; ++ } ++ ++ /* Now allocate and setup the descriptor. */ ++ d = kzalloc(sizeof(*d), GFP_NOWAIT); ++ if (!d) ++ return NULL; ++ ++ d->dir = direction; ++ ++ if (c->ch >= 8) /* we have a LITE channel */ ++ max_size = MAX_LITE_TRANSFER; ++ else ++ max_size = MAX_NORMAL_TRANSFER; ++ ++ /* We store the length of the SG list in d->frames ++ taking care to account for splitting up transfers ++ too large for a LITE channel */ ++ ++ d->frames = 0; ++ for_each_sg(sgl, sgent, sg_len, i) { ++ uint32_t len = sg_dma_len(sgent); ++ d->frames += 1 + len / max_size; ++ } ++ ++ /* Allocate memory for control blocks */ ++ d->control_block_size = d->frames * sizeof(struct bcm2835_dma_cb); ++ d->control_block_base = dma_zalloc_coherent(chan->device->dev, ++ d->control_block_size, &d->control_block_base_phys, ++ GFP_NOWAIT); ++ ++ if (!d->control_block_base) { ++ kfree(d); ++ return NULL; ++ } ++ ++ /* ++ * Iterate over all SG entries, create a control block ++ * for each frame and link them together. ++ */ ++ ++ /* we count the number of times an SG entry had to be splitct ++ as a result of using a LITE channel */ ++ splitct = 0; ++ ++ for_each_sg(sgl, sgent, sg_len, i) { ++ dma_addr_t addr = sg_dma_address(sgent); ++ uint32_t len = sg_dma_len(sgent); ++ ++ for (j = 0; j < len; j += max_size) { ++ u32 waits; ++ struct bcm2835_dma_cb *control_block = ++ &d->control_block_base[i+splitct]; ++ ++ /* Setup adresses */ ++ if (d->dir == DMA_DEV_TO_MEM) { ++ control_block->info = BCM2835_DMA_D_INC | ++ BCM2835_DMA_D_WIDTH | BCM2835_DMA_S_DREQ; ++ control_block->src = dev_addr; ++ control_block->dst = addr + (dma_addr_t)j; ++ } else { ++ control_block->info = BCM2835_DMA_S_INC | ++ BCM2835_DMA_S_WIDTH | BCM2835_DMA_D_DREQ; ++ control_block->src = addr + (dma_addr_t)j; ++ control_block->dst = dev_addr; ++ } ++ ++ /* Common part */ ++ waits = SDHCI_BCM_DMA_WAITS; ++ if ((dma_debug >> 0) & 0x1f) ++ waits = (dma_debug >> 0) & 0x1f; ++ control_block->info |= BCM2835_DMA_WAITS(waits); ++ control_block->info |= BCM2835_DMA_WAIT_RESP; ++ ++ /* Enable */ ++ if (i == sg_len-1 && len-j <= max_size) ++ control_block->info |= BCM2835_DMA_INT_EN; ++ ++ /* Setup synchronization */ ++ if (sync_type != 0) ++ control_block->info |= sync_type; ++ ++ /* Setup DREQ channel */ ++ if (c->dreq != 0) ++ control_block->info |= ++ BCM2835_DMA_PER_MAP(c->dreq); ++ ++ /* Length of a frame */ ++ control_block->length = min(len-j, max_size); ++ d->size += control_block->length; ++ ++ /* ++ * Next block is the next frame. ++ */ ++ if (i < sg_len-1 || len-j > max_size) { ++ /* next block is the next frame. */ ++ control_block->next = d->control_block_base_phys + ++ sizeof(struct bcm2835_dma_cb) * (i + splitct + 1); ++ } else { ++ /* next block is empty. */ ++ control_block->next = 0; ++ } ++ ++ if (len-j > max_size) ++ splitct++; ++ } ++ } ++ ++ c->cyclic = false; ++ ++ return vchan_tx_prep(&c->vc, &d->vd, flags); ++} ++ ++static int bcm2835_dma_slave_config(struct dma_chan *chan, ++ struct dma_slave_config *cfg) ++{ ++ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); ++ if ((cfg->direction == DMA_DEV_TO_MEM && ++ cfg->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) || ++ (cfg->direction == DMA_MEM_TO_DEV && ++ cfg->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) || ++ !is_slave_direction(cfg->direction)) { ++ return -EINVAL; ++ } ++ ++ c->cfg = *cfg; ++ if (!c->dreq) ++ c->dreq = cfg->slave_id; ++ ++ return 0; ++} ++ ++static int bcm2835_dma_terminate_all(struct dma_chan *chan) ++{ ++ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); ++ struct bcm2835_dmadev *d = to_bcm2835_dma_dev(c->vc.chan.device); ++ unsigned long flags; ++ int timeout = 10000; ++ LIST_HEAD(head); ++ ++ spin_lock_irqsave(&c->vc.lock, flags); ++ ++ /* Prevent this channel being scheduled */ ++ spin_lock(&d->lock); ++ list_del_init(&c->node); ++ spin_unlock(&d->lock); ++ ++ /* ++ * Stop DMA activity: we assume the callback will not be called ++ * after bcm_dma_abort() returns (even if it does, it will see ++ * c->desc is NULL and exit.) ++ */ ++ if (c->desc) { ++ bcm2835_dma_desc_free(&c->desc->vd); ++ c->desc = NULL; ++ bcm2835_dma_abort(c->chan_base); ++ ++ /* Wait for stopping */ ++ while (--timeout) { ++ if (!(readl(c->chan_base + BCM2835_DMA_CS) & ++ BCM2835_DMA_ACTIVE)) ++ break; ++ ++ cpu_relax(); ++ } ++ ++ if (!timeout) ++ dev_err(d->ddev.dev, "DMA transfer could not be terminated\n"); ++ } ++ ++ vchan_get_all_descriptors(&c->vc, &head); ++ spin_unlock_irqrestore(&c->vc.lock, flags); ++ vchan_dma_desc_free_list(&c->vc, &head); ++ ++ return 0; ++} ++ ++#ifndef CONFIG_DMA_BCM2708_LEGACY ++static int bcm2835_dma_chan_init(struct bcm2835_dmadev *d, int chan_id, int irq) ++{ ++ struct bcm2835_chan *c; ++ ++ c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL); ++ if (!c) ++ return -ENOMEM; ++ ++ c->vc.desc_free = bcm2835_dma_desc_free; ++ vchan_init(&c->vc, &d->ddev); ++ INIT_LIST_HEAD(&c->node); ++ ++ c->chan_base = BCM2835_DMA_CHANIO(d->base, chan_id); ++ c->ch = chan_id; ++ c->irq_number = irq; ++ ++ return 0; ++} ++#endif ++ ++static int bcm2708_dma_chan_init(struct bcm2835_dmadev *d, ++ void __iomem *chan_base, int chan_id, int irq) ++{ ++ struct bcm2835_chan *c; ++ ++ c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL); ++ if (!c) ++ return -ENOMEM; ++ ++ c->vc.desc_free = bcm2835_dma_desc_free; ++ vchan_init(&c->vc, &d->ddev); ++ INIT_LIST_HEAD(&c->node); ++ ++ c->chan_base = chan_base; ++ c->ch = chan_id; ++ c->irq_number = irq; ++ ++ return 0; ++} ++ ++ ++static void bcm2835_dma_free(struct bcm2835_dmadev *od) ++{ ++ struct bcm2835_chan *c, *next; ++ ++ list_for_each_entry_safe(c, next, &od->ddev.channels, ++ vc.chan.device_node) { ++ list_del(&c->vc.chan.device_node); ++ tasklet_kill(&c->vc.task); ++ } ++} ++ ++static const struct of_device_id bcm2835_dma_of_match[] = { ++ { .compatible = "brcm,bcm2835-dma", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, bcm2835_dma_of_match); ++ ++static struct dma_chan *bcm2835_dma_xlate(struct of_phandle_args *spec, ++ struct of_dma *ofdma) ++{ ++ struct bcm2835_dmadev *d = ofdma->of_dma_data; ++ struct dma_chan *chan; ++ ++ chan = dma_get_any_slave_channel(&d->ddev); ++ if (!chan) ++ return NULL; ++ ++ /* Set DREQ from param */ ++ to_bcm2835_dma_chan(chan)->dreq = spec->args[0]; ++ ++ return chan; ++} ++ ++static int bcm2835_dma_probe(struct platform_device *pdev) ++{ ++ struct bcm2835_dmadev *od; ++#ifndef CONFIG_DMA_BCM2708_LEGACY ++ struct resource *res; ++ void __iomem *base; ++ uint32_t chans_available; ++#endif ++ int rc; ++ int i; ++ int irq; ++#ifdef CONFIG_DMA_BCM2708_LEGACY ++ static const u32 wanted_features[] = { ++ BCM_DMA_FEATURE_FAST, ++ BCM_DMA_FEATURE_NORMAL, ++ BCM_DMA_FEATURE_LITE ++ }; ++ int j; ++#endif ++ ++ ++ if (!pdev->dev.dma_mask) ++ pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; ++ ++#ifdef CONFIG_DMA_BCM2708_LEGACY ++ ++ rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); ++ if (rc) ++ return rc; ++ dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); ++ ++ ++ od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL); ++ if (!od) ++ return -ENOMEM; ++ ++ rc = bcm_dmaman_probe(pdev); ++ if (rc) ++ return rc; ++ ++ pdev->dev.dma_parms = &od->dma_parms; ++ dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF); ++ ++ ++ dma_cap_set(DMA_SLAVE, od->ddev.cap_mask); ++ dma_cap_set(DMA_PRIVATE, od->ddev.cap_mask); ++ dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask); ++ od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources; ++ od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources; ++ od->ddev.device_tx_status = bcm2835_dma_tx_status; ++ od->ddev.device_issue_pending = bcm2835_dma_issue_pending; ++ od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic; ++ od->ddev.device_prep_slave_sg = bcm2835_dma_prep_slave_sg; ++ od->ddev.device_terminate_all = bcm2835_dma_terminate_all; ++ od->ddev.device_config = bcm2835_dma_slave_config; ++ od->ddev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); ++ od->ddev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); ++ od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); ++ od->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; ++ od->ddev.dev = &pdev->dev; ++ INIT_LIST_HEAD(&od->ddev.channels); ++ spin_lock_init(&od->lock); ++ ++ platform_set_drvdata(pdev, od); ++ ++ for (i = 0, j = 0; j < ARRAY_SIZE(wanted_features);) { ++ ++ void __iomem *chan_base; ++ int chan_id; ++ ++ chan_id = bcm_dma_chan_alloc(wanted_features[j], ++ &chan_base, ++ &irq); ++ ++ if (chan_id < 0) { ++ j++; ++ continue; ++ } ++ ++ rc = bcm2708_dma_chan_init(od, chan_base, chan_id, irq); ++ if (rc) ++ goto err_no_dma; ++ i++; ++ } ++ ++ if (pdev->dev.of_node) { ++ rc = of_dma_controller_register(pdev->dev.of_node, ++ bcm2835_dma_xlate, od); ++ if (rc) { ++ dev_err(&pdev->dev, ++ "Failed to register DMA controller\n"); ++ goto err_no_dma; ++ } ++ } ++ ++ dev_info(&pdev->dev, "Initialized %i DMA channels (+ 1 legacy)\n", i); ++ ++#else ++ rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); ++ if (rc) ++ return rc; ++ ++ ++ od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL); ++ if (!od) ++ return -ENOMEM; ++ ++ pdev->dev.dma_parms = &od->dma_parms; ++ dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF); ++ ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(base)) ++ return PTR_ERR(base); ++ ++ od->base = base; ++ ++ ++ dma_cap_set(DMA_SLAVE, od->ddev.cap_mask); ++ dma_cap_set(DMA_PRIVATE, od->ddev.cap_mask); ++ dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask); ++ od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources; ++ od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources; ++ od->ddev.device_tx_status = bcm2835_dma_tx_status; ++ od->ddev.device_issue_pending = bcm2835_dma_issue_pending; ++ od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic; ++ od->ddev.device_prep_slave_sg = bcm2835_dma_prep_slave_sg; ++ od->ddev.device_terminate_all = bcm2835_dma_terminate_all; ++ od->ddev.device_config = bcm2835_dma_slave_config; ++ od->ddev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); ++ od->ddev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); ++ od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); ++ od->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; ++ od->ddev.dev = &pdev->dev; ++ INIT_LIST_HEAD(&od->ddev.channels); ++ spin_lock_init(&od->lock); ++ ++ platform_set_drvdata(pdev, od); ++ ++ ++ /* Request DMA channel mask from device tree */ ++ if (of_property_read_u32(pdev->dev.of_node, ++ "brcm,dma-channel-mask", ++ &chans_available)) { ++ dev_err(&pdev->dev, "Failed to get channel mask\n"); ++ rc = -EINVAL; ++ goto err_no_dma; ++ } ++ ++ ++ /* ++ * Do not use the FIQ and BULK channels, ++ * because they are used by the GPU. ++ */ ++ chans_available &= ~(BCM2835_DMA_FIQ_MASK | BCM2835_DMA_BULK_MASK); ++ ++ ++ for (i = 0; i < pdev->num_resources; i++) { ++ irq = platform_get_irq(pdev, i); ++ if (irq < 0) ++ break; ++ ++ if (chans_available & (1 << i)) { ++ rc = bcm2835_dma_chan_init(od, i, irq); ++ if (rc) ++ goto err_no_dma; ++ } ++ } ++ ++ dev_dbg(&pdev->dev, "Initialized %i DMA channels\n", i); ++ ++ /* Device-tree DMA controller registration */ ++ rc = of_dma_controller_register(pdev->dev.of_node, ++ bcm2835_dma_xlate, od); ++ if (rc) { ++ dev_err(&pdev->dev, "Failed to register DMA controller\n"); ++ goto err_no_dma; ++ } ++#endif ++ ++ rc = dma_async_device_register(&od->ddev); ++ if (rc) { ++ dev_err(&pdev->dev, ++ "Failed to register slave DMA engine device: %d\n", rc); ++ goto err_no_dma; ++ } ++ ++ dev_info(&pdev->dev, "Load BCM2835 DMA engine driver\n"); ++ dev_info(&pdev->dev, "dma_debug:%x\n", dma_debug); ++ ++ return 0; ++ ++err_no_dma: ++ bcm2835_dma_free(od); ++ return rc; ++} ++ ++static int bcm2835_dma_remove(struct platform_device *pdev) ++{ ++ struct bcm2835_dmadev *od = platform_get_drvdata(pdev); ++ ++ dma_async_device_unregister(&od->ddev); ++ bcm2835_dma_free(od); ++ bcm_dmaman_remove(pdev); ++ ++ return 0; ++} ++ ++static struct platform_driver bcm2835_dma_driver = { ++ .probe = bcm2835_dma_probe, ++ .remove = bcm2835_dma_remove, ++ .driver = { ++ .name = "bcm2708-dmaengine", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(bcm2835_dma_of_match), ++ }, ++}; ++ ++static int bcm2835_init(void) ++{ ++ return platform_driver_register(&bcm2835_dma_driver); ++} ++ ++static void bcm2835_exit(void) ++{ ++ platform_driver_unregister(&bcm2835_dma_driver); ++} ++ ++/* ++ * Load after serial driver (arch_initcall) so we see the messages if it fails, ++ * but before drivers (module_init) that need a DMA channel. ++ */ ++subsys_initcall(bcm2835_init); ++module_exit(bcm2835_exit); ++ ++module_param(dma_debug, uint, 0644); ++#ifdef CONFIG_DMA_BCM2708_LEGACY ++/* Keep backward compatibility: dma.dmachans= */ ++#undef MODULE_PARAM_PREFIX ++#define MODULE_PARAM_PREFIX "dma." ++module_param(dmachans, int, 0644); ++#endif ++MODULE_ALIAS("platform:bcm2835-dma"); ++MODULE_DESCRIPTION("BCM2835 DMA engine driver"); ++MODULE_AUTHOR("Florian Meier "); ++MODULE_AUTHOR("Gellert Weisz "); ++MODULE_LICENSE("GPL v2"); +diff -Nur linux-4.1.13.orig/drivers/dma/Kconfig linux-rpi/drivers/dma/Kconfig +--- linux-4.1.13.orig/drivers/dma/Kconfig 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/dma/Kconfig 2015-11-29 09:42:36.815304925 +0100 +@@ -337,6 +337,17 @@ + select DMA_ENGINE + select DMA_VIRTUAL_CHANNELS + ++config DMA_BCM2708 ++ tristate "BCM2708 DMA engine support" ++ depends on MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835 ++ select DMA_ENGINE ++ select DMA_VIRTUAL_CHANNELS ++ ++config DMA_BCM2708_LEGACY ++ bool "BCM2708 DMA legacy API support" ++ depends on DMA_BCM2708 ++ default y ++ + config TI_CPPI41 + tristate "AM33xx CPPI41 DMA support" + depends on ARCH_OMAP +@@ -385,7 +396,7 @@ + select DMA_VIRTUAL_CHANNELS + help + Enable support for the MOXA ART SoC DMA controller. +- ++ + config FSL_EDMA + tristate "Freescale eDMA engine support" + depends on OF +diff -Nur linux-4.1.13.orig/drivers/dma/Makefile linux-rpi/drivers/dma/Makefile +--- linux-4.1.13.orig/drivers/dma/Makefile 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/dma/Makefile 2015-11-29 09:42:36.815304925 +0100 +@@ -39,6 +39,7 @@ + obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o + obj-$(CONFIG_DMA_OMAP) += omap-dma.o + obj-$(CONFIG_DMA_BCM2835) += bcm2835-dma.o ++obj-$(CONFIG_DMA_BCM2708) += bcm2708-dmaengine.o + obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o + obj-$(CONFIG_DMA_JZ4740) += dma-jz4740.o + obj-$(CONFIG_DMA_JZ4780) += dma-jz4780.o +diff -Nur linux-4.1.13.orig/drivers/firmware/Kconfig linux-rpi/drivers/firmware/Kconfig +--- linux-4.1.13.orig/drivers/firmware/Kconfig 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/firmware/Kconfig 2015-11-29 09:42:36.883300407 +0100 +@@ -136,6 +136,13 @@ + bool + depends on ARM || ARM64 + ++config RASPBERRYPI_FIRMWARE ++ tristate "Raspberry Pi Firmware Driver" ++ depends on BCM2835_MBOX ++ help ++ This option enables support for communicating with the firmware on the ++ Raspberry Pi. ++ + source "drivers/firmware/google/Kconfig" + source "drivers/firmware/efi/Kconfig" + +diff -Nur linux-4.1.13.orig/drivers/firmware/Makefile linux-rpi/drivers/firmware/Makefile +--- linux-4.1.13.orig/drivers/firmware/Makefile 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/firmware/Makefile 2015-11-29 09:42:36.883300407 +0100 +@@ -13,6 +13,7 @@ + obj-$(CONFIG_FIRMWARE_MEMMAP) += memmap.o + obj-$(CONFIG_QCOM_SCM) += qcom_scm.o + CFLAGS_qcom_scm.o :=$(call as-instr,.arch_extension sec,-DREQUIRES_SEC=1) ++obj-$(CONFIG_RASPBERRYPI_FIRMWARE) += raspberrypi.o + + obj-$(CONFIG_GOOGLE_FIRMWARE) += google/ + obj-$(CONFIG_EFI) += efi/ +diff -Nur linux-4.1.13.orig/drivers/firmware/raspberrypi.c linux-rpi/drivers/firmware/raspberrypi.c +--- linux-4.1.13.orig/drivers/firmware/raspberrypi.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/firmware/raspberrypi.c 2015-11-29 09:42:36.887300142 +0100 +@@ -0,0 +1,297 @@ ++/* ++ * Defines interfaces for interacting wtih the Raspberry Pi firmware's ++ * property channel. ++ * ++ * Copyright © 2015 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define MBOX_MSG(chan, data28) (((data28) & ~0xf) | ((chan) & 0xf)) ++#define MBOX_CHAN(msg) ((msg) & 0xf) ++#define MBOX_DATA28(msg) ((msg) & ~0xf) ++#define MBOX_CHAN_PROPERTY 8 ++ ++struct rpi_firmware { ++ struct mbox_client cl; ++ struct mbox_chan *chan; /* The property channel. */ ++ struct completion c; ++ u32 enabled; ++}; ++ ++static struct platform_device *g_pdev; ++ ++static DEFINE_MUTEX(transaction_lock); ++ ++static void response_callback(struct mbox_client *cl, void *msg) ++{ ++ struct rpi_firmware *fw = container_of(cl, struct rpi_firmware, cl); ++ complete(&fw->c); ++} ++ ++/* ++ * Sends a request to the firmware through the BCM2835 mailbox driver, ++ * and synchronously waits for the reply. ++ */ ++static int ++rpi_firmware_transaction(struct rpi_firmware *fw, u32 chan, u32 data) ++{ ++ u32 message = MBOX_MSG(chan, data); ++ int ret; ++ ++ WARN_ON(data & 0xf); ++ ++ mutex_lock(&transaction_lock); ++ reinit_completion(&fw->c); ++ ret = mbox_send_message(fw->chan, &message); ++ if (ret >= 0) { ++ wait_for_completion(&fw->c); ++ ret = 0; ++ } else { ++ dev_err(fw->cl.dev, "mbox_send_message returned %d\n", ret); ++ } ++ mutex_unlock(&transaction_lock); ++ ++ return ret; ++} ++ ++/** ++ * rpi_firmware_property_list - Submit firmware property list ++ * @fw: Pointer to firmware structure from rpi_firmware_get(). ++ * @data: Buffer holding tags. ++ * @tag_size: Size of tags buffer. ++ * ++ * Submits a set of concatenated tags to the VPU firmware through the ++ * mailbox property interface. ++ * ++ * The buffer header and the ending tag are added by this function and ++ * don't need to be supplied, just the actual tags for your operation. ++ * See struct rpi_firmware_property_tag_header for the per-tag ++ * structure. ++ */ ++int rpi_firmware_property_list(struct rpi_firmware *fw, ++ void *data, size_t tag_size) ++{ ++ size_t size = tag_size + 12; ++ u32 *buf; ++ dma_addr_t bus_addr; ++ int ret; ++ ++ /* Packets are processed a dword at a time. */ ++ if (size & 3) ++ return -EINVAL; ++ ++ buf = dma_alloc_coherent(fw->cl.dev, PAGE_ALIGN(size), &bus_addr, ++ GFP_ATOMIC); ++ if (!buf) ++ return -ENOMEM; ++ ++ /* The firmware will error out without parsing in this case. */ ++ WARN_ON(size >= 1024 * 1024); ++ ++ buf[0] = size; ++ buf[1] = RPI_FIRMWARE_STATUS_REQUEST; ++ memcpy(&buf[2], data, tag_size); ++ buf[size / 4 - 1] = RPI_FIRMWARE_PROPERTY_END; ++ wmb(); ++ ++ ret = rpi_firmware_transaction(fw, MBOX_CHAN_PROPERTY, bus_addr); ++ ++ rmb(); ++ memcpy(data, &buf[2], tag_size); ++ if (ret == 0 && buf[1] != RPI_FIRMWARE_STATUS_SUCCESS) { ++ /* ++ * The tag name here might not be the one causing the ++ * error, if there were multiple tags in the request. ++ * But single-tag is the most common, so go with it. ++ */ ++ dev_err(fw->cl.dev, "Request 0x%08x returned status 0x%08x\n", ++ buf[2], buf[1]); ++ ret = -EINVAL; ++ } ++ ++ dma_free_coherent(fw->cl.dev, PAGE_ALIGN(size), buf, bus_addr); ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(rpi_firmware_property_list); ++ ++/** ++ * rpi_firmware_property - Submit single firmware property ++ * @fw: Pointer to firmware structure from rpi_firmware_get(). ++ * @tag: One of enum_mbox_property_tag. ++ * @tag_data: Tag data buffer. ++ * @buf_size: Buffer size. ++ * ++ * Submits a single tag to the VPU firmware through the mailbox ++ * property interface. ++ * ++ * This is a convenience wrapper around ++ * rpi_firmware_property_list() to avoid some of the ++ * boilerplate in property calls. ++ */ ++int rpi_firmware_property(struct rpi_firmware *fw, ++ u32 tag, void *tag_data, size_t buf_size) ++{ ++ /* Single tags are very small (generally 8 bytes), so the ++ * stack should be safe. ++ */ ++ u8 data[buf_size + sizeof(struct rpi_firmware_property_tag_header)]; ++ struct rpi_firmware_property_tag_header *header = ++ (struct rpi_firmware_property_tag_header *)data; ++ int ret; ++ ++ header->tag = tag; ++ header->buf_size = buf_size; ++ header->req_resp_size = 0; ++ memcpy(data + sizeof(struct rpi_firmware_property_tag_header), ++ tag_data, buf_size); ++ ++ ret = rpi_firmware_property_list(fw, &data, sizeof(data)); ++ memcpy(tag_data, ++ data + sizeof(struct rpi_firmware_property_tag_header), ++ buf_size); ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(rpi_firmware_property); ++ ++static void ++rpi_firmware_print_firmware_revision(struct rpi_firmware *fw) ++{ ++ u32 packet; ++ int ret = rpi_firmware_property(fw, ++ RPI_FIRMWARE_GET_FIRMWARE_REVISION, ++ &packet, sizeof(packet)); ++ ++ if (ret == 0) { ++ struct tm tm; ++ ++ time_to_tm(packet, 0, &tm); ++ ++ dev_info(fw->cl.dev, ++ "Attached to firmware from %04ld-%02d-%02d %02d:%02d\n", ++ tm.tm_year + 1900, tm.tm_mon + 1, tm.tm_mday, ++ tm.tm_hour, tm.tm_min); ++ } ++} ++ ++static int raspberrypi_firmware_set_power(struct rpi_firmware *fw, ++ u32 domain, bool on) ++{ ++ struct { ++ u32 domain; ++ u32 on; ++ } packet; ++ int ret; ++ ++ packet.domain = domain; ++ packet.on = on; ++ ret = rpi_firmware_property(fw, RPI_FIRMWARE_SET_POWER_STATE, ++ &packet, sizeof(packet)); ++ if (!ret && packet.on != on) ++ ret = -EINVAL; ++ ++ return ret; ++} ++ ++static int rpi_firmware_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct rpi_firmware *fw; ++ ++ fw = devm_kzalloc(dev, sizeof(*fw), GFP_KERNEL); ++ if (!fw) ++ return -ENOMEM; ++ ++ fw->cl.dev = dev; ++ fw->cl.rx_callback = response_callback; ++ fw->cl.tx_block = true; ++ ++ fw->chan = mbox_request_channel(&fw->cl, 0); ++ if (IS_ERR(fw->chan)) { ++ int ret = PTR_ERR(fw->chan); ++ if (ret != -EPROBE_DEFER) ++ dev_err(dev, "Failed to get mbox channel: %d\n", ret); ++ return ret; ++ } ++ ++ init_completion(&fw->c); ++ ++ platform_set_drvdata(pdev, fw); ++ g_pdev = pdev; ++ ++ rpi_firmware_print_firmware_revision(fw); ++ ++ if (raspberrypi_firmware_set_power(fw, 3, true)) ++ dev_err(dev, "failed to turn on USB power\n"); ++ ++ return 0; ++} ++ ++static int rpi_firmware_remove(struct platform_device *pdev) ++{ ++ struct rpi_firmware *fw = platform_get_drvdata(pdev); ++ ++ mbox_free_channel(fw->chan); ++ g_pdev = NULL; ++ ++ return 0; ++} ++ ++/** ++ * rpi_firmware_get - Get pointer to rpi_firmware structure. ++ * @firmware_node: Pointer to the firmware Device Tree node. ++ * ++ * Returns NULL is the firmware device is not ready. ++ */ ++struct rpi_firmware *rpi_firmware_get(struct device_node *firmware_node) ++{ ++ struct platform_device *pdev = g_pdev; ++ ++ if (!pdev) ++ return NULL; ++ ++ return platform_get_drvdata(pdev); ++} ++EXPORT_SYMBOL_GPL(rpi_firmware_get); ++ ++static const struct of_device_id rpi_firmware_of_match[] = { ++ { .compatible = "raspberrypi,bcm2835-firmware", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, rpi_firmware_of_match); ++ ++static struct platform_driver rpi_firmware_driver = { ++ .driver = { ++ .name = "raspberrypi-firmware", ++ .of_match_table = rpi_firmware_of_match, ++ }, ++ .probe = rpi_firmware_probe, ++ .remove = rpi_firmware_remove, ++}; ++ ++static int __init rpi_firmware_init(void) ++{ ++ return platform_driver_register(&rpi_firmware_driver); ++} ++subsys_initcall(rpi_firmware_init); ++ ++static void __init rpi_firmware_exit(void) ++{ ++ platform_driver_unregister(&rpi_firmware_driver); ++} ++module_exit(rpi_firmware_exit); ++ ++MODULE_AUTHOR("Eric Anholt "); ++MODULE_DESCRIPTION("Raspberry Pi firmware driver"); ++MODULE_LICENSE("GPL v2"); +diff -Nur linux-4.1.13.orig/drivers/hid/usbhid/hid-core.c linux-rpi/drivers/hid/usbhid/hid-core.c +--- linux-4.1.13.orig/drivers/hid/usbhid/hid-core.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/hid/usbhid/hid-core.c 2015-11-29 09:42:37.327270908 +0100 +@@ -49,7 +49,7 @@ + * Module parameters. + */ + +-static unsigned int hid_mousepoll_interval; ++static unsigned int hid_mousepoll_interval = ~0; + module_param_named(mousepoll, hid_mousepoll_interval, uint, 0644); + MODULE_PARM_DESC(mousepoll, "Polling interval of mice"); + +@@ -1090,8 +1090,12 @@ + } + + /* Change the polling interval of mice. */ +- if (hid->collection->usage == HID_GD_MOUSE && hid_mousepoll_interval > 0) +- interval = hid_mousepoll_interval; ++ if (hid->collection->usage == HID_GD_MOUSE) { ++ if (hid_mousepoll_interval == ~0 && interval < 16) ++ interval = 16; ++ else if (hid_mousepoll_interval != ~0 && hid_mousepoll_interval != 0) ++ interval = hid_mousepoll_interval; ++ } + + ret = -ENOMEM; + if (usb_endpoint_dir_in(endpoint)) { +diff -Nur linux-4.1.13.orig/drivers/i2c/busses/i2c-bcm2708.c linux-rpi/drivers/i2c/busses/i2c-bcm2708.c +--- linux-4.1.13.orig/drivers/i2c/busses/i2c-bcm2708.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/i2c/busses/i2c-bcm2708.c 2015-11-29 09:42:37.375267719 +0100 +@@ -0,0 +1,524 @@ ++/* ++ * Driver for Broadcom BCM2708 BSC Controllers ++ * ++ * Copyright (C) 2012 Chris Boot & Frank Buss ++ * ++ * This driver is inspired by: ++ * i2c-ocores.c, by Peter Korsgaard ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* BSC register offsets */ ++#define BSC_C 0x00 ++#define BSC_S 0x04 ++#define BSC_DLEN 0x08 ++#define BSC_A 0x0c ++#define BSC_FIFO 0x10 ++#define BSC_DIV 0x14 ++#define BSC_DEL 0x18 ++#define BSC_CLKT 0x1c ++ ++/* Bitfields in BSC_C */ ++#define BSC_C_I2CEN 0x00008000 ++#define BSC_C_INTR 0x00000400 ++#define BSC_C_INTT 0x00000200 ++#define BSC_C_INTD 0x00000100 ++#define BSC_C_ST 0x00000080 ++#define BSC_C_CLEAR_1 0x00000020 ++#define BSC_C_CLEAR_2 0x00000010 ++#define BSC_C_READ 0x00000001 ++ ++/* Bitfields in BSC_S */ ++#define BSC_S_CLKT 0x00000200 ++#define BSC_S_ERR 0x00000100 ++#define BSC_S_RXF 0x00000080 ++#define BSC_S_TXE 0x00000040 ++#define BSC_S_RXD 0x00000020 ++#define BSC_S_TXD 0x00000010 ++#define BSC_S_RXR 0x00000008 ++#define BSC_S_TXW 0x00000004 ++#define BSC_S_DONE 0x00000002 ++#define BSC_S_TA 0x00000001 ++ ++#define I2C_WAIT_LOOP_COUNT 200 ++ ++#define DRV_NAME "bcm2708_i2c" ++ ++static unsigned int baudrate = CONFIG_I2C_BCM2708_BAUDRATE; ++module_param(baudrate, uint, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP); ++MODULE_PARM_DESC(baudrate, "The I2C baudrate"); ++ ++static bool combined = false; ++module_param(combined, bool, 0644); ++MODULE_PARM_DESC(combined, "Use combined transactions"); ++ ++struct bcm2708_i2c { ++ struct i2c_adapter adapter; ++ ++ spinlock_t lock; ++ void __iomem *base; ++ int irq; ++ struct clk *clk; ++ u32 cdiv; ++ ++ struct completion done; ++ ++ struct i2c_msg *msg; ++ int pos; ++ int nmsgs; ++ bool error; ++}; ++ ++/* ++ * This function sets the ALT mode on the I2C pins so that we can use them with ++ * the BSC hardware. ++ * ++ * FIXME: This is a hack. Use pinmux / pinctrl. ++ */ ++static void bcm2708_i2c_init_pinmode(int id) ++{ ++#define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3)) ++#define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3)) ++ ++ int pin; ++ u32 *gpio = ioremap(GPIO_BASE, SZ_16K); ++ ++ BUG_ON(id != 0 && id != 1); ++ /* BSC0 is on GPIO 0 & 1, BSC1 is on GPIO 2 & 3 */ ++ for (pin = id*2+0; pin <= id*2+1; pin++) { ++ printk("bcm2708_i2c_init_pinmode(%d,%d)\n", id, pin); ++ INP_GPIO(pin); /* set mode to GPIO input first */ ++ SET_GPIO_ALT(pin, 0); /* set mode to ALT 0 */ ++ } ++ ++ iounmap(gpio); ++ ++#undef INP_GPIO ++#undef SET_GPIO_ALT ++} ++ ++static inline u32 bcm2708_rd(struct bcm2708_i2c *bi, unsigned reg) ++{ ++ return readl(bi->base + reg); ++} ++ ++static inline void bcm2708_wr(struct bcm2708_i2c *bi, unsigned reg, u32 val) ++{ ++ writel(val, bi->base + reg); ++} ++ ++static inline void bcm2708_bsc_reset(struct bcm2708_i2c *bi) ++{ ++ bcm2708_wr(bi, BSC_C, 0); ++ bcm2708_wr(bi, BSC_S, BSC_S_CLKT | BSC_S_ERR | BSC_S_DONE); ++} ++ ++static inline void bcm2708_bsc_fifo_drain(struct bcm2708_i2c *bi) ++{ ++ while ((bcm2708_rd(bi, BSC_S) & BSC_S_RXD) && (bi->pos < bi->msg->len)) ++ bi->msg->buf[bi->pos++] = bcm2708_rd(bi, BSC_FIFO); ++} ++ ++static inline void bcm2708_bsc_fifo_fill(struct bcm2708_i2c *bi) ++{ ++ while ((bcm2708_rd(bi, BSC_S) & BSC_S_TXD) && (bi->pos < bi->msg->len)) ++ bcm2708_wr(bi, BSC_FIFO, bi->msg->buf[bi->pos++]); ++} ++ ++static inline int bcm2708_bsc_setup(struct bcm2708_i2c *bi) ++{ ++ u32 cdiv, s; ++ u32 c = BSC_C_I2CEN | BSC_C_INTD | BSC_C_ST | BSC_C_CLEAR_1; ++ int wait_loops = I2C_WAIT_LOOP_COUNT; ++ ++ /* Can't call clk_get_rate as it locks a mutex and here we are spinlocked. ++ * Use the value that we cached in the probe. ++ */ ++ cdiv = bi->cdiv; ++ ++ if (bi->msg->flags & I2C_M_RD) ++ c |= BSC_C_INTR | BSC_C_READ; ++ else ++ c |= BSC_C_INTT; ++ ++ bcm2708_wr(bi, BSC_DIV, cdiv); ++ bcm2708_wr(bi, BSC_A, bi->msg->addr); ++ bcm2708_wr(bi, BSC_DLEN, bi->msg->len); ++ if (combined) ++ { ++ /* Do the next two messages meet combined transaction criteria? ++ - Current message is a write, next message is a read ++ - Both messages to same slave address ++ - Write message can fit inside FIFO (16 bytes or less) */ ++ if ( (bi->nmsgs > 1) && ++ !(bi->msg[0].flags & I2C_M_RD) && (bi->msg[1].flags & I2C_M_RD) && ++ (bi->msg[0].addr == bi->msg[1].addr) && (bi->msg[0].len <= 16)) { ++ /* Fill FIFO with entire write message (16 byte FIFO) */ ++ while (bi->pos < bi->msg->len) { ++ bcm2708_wr(bi, BSC_FIFO, bi->msg->buf[bi->pos++]); ++ } ++ /* Start write transfer (no interrupts, don't clear FIFO) */ ++ bcm2708_wr(bi, BSC_C, BSC_C_I2CEN | BSC_C_ST); ++ ++ /* poll for transfer start bit (should only take 1-20 polls) */ ++ do { ++ s = bcm2708_rd(bi, BSC_S); ++ } while (!(s & (BSC_S_TA | BSC_S_ERR | BSC_S_CLKT | BSC_S_DONE)) && --wait_loops >= 0); ++ ++ /* did we time out or some error occured? */ ++ if (wait_loops < 0 || (s & (BSC_S_ERR | BSC_S_CLKT))) { ++ return -1; ++ } ++ ++ /* Send next read message before the write transfer finishes. */ ++ bi->nmsgs--; ++ bi->msg++; ++ bi->pos = 0; ++ bcm2708_wr(bi, BSC_DLEN, bi->msg->len); ++ c = BSC_C_I2CEN | BSC_C_INTD | BSC_C_INTR | BSC_C_ST | BSC_C_READ; ++ } ++ } ++ bcm2708_wr(bi, BSC_C, c); ++ ++ return 0; ++} ++ ++static irqreturn_t bcm2708_i2c_interrupt(int irq, void *dev_id) ++{ ++ struct bcm2708_i2c *bi = dev_id; ++ bool handled = true; ++ u32 s; ++ int ret; ++ ++ spin_lock(&bi->lock); ++ ++ /* we may see camera interrupts on the "other" I2C channel ++ Just return if we've not sent anything */ ++ if (!bi->nmsgs || !bi->msg) { ++ goto early_exit; ++ } ++ ++ s = bcm2708_rd(bi, BSC_S); ++ ++ if (s & (BSC_S_CLKT | BSC_S_ERR)) { ++ bcm2708_bsc_reset(bi); ++ bi->error = true; ++ ++ bi->msg = 0; /* to inform the that all work is done */ ++ bi->nmsgs = 0; ++ /* wake up our bh */ ++ complete(&bi->done); ++ } else if (s & BSC_S_DONE) { ++ bi->nmsgs--; ++ ++ if (bi->msg->flags & I2C_M_RD) { ++ bcm2708_bsc_fifo_drain(bi); ++ } ++ ++ bcm2708_bsc_reset(bi); ++ ++ if (bi->nmsgs) { ++ /* advance to next message */ ++ bi->msg++; ++ bi->pos = 0; ++ ret = bcm2708_bsc_setup(bi); ++ if (ret < 0) { ++ bcm2708_bsc_reset(bi); ++ bi->error = true; ++ bi->msg = 0; /* to inform the that all work is done */ ++ bi->nmsgs = 0; ++ /* wake up our bh */ ++ complete(&bi->done); ++ goto early_exit; ++ } ++ } else { ++ bi->msg = 0; /* to inform the that all work is done */ ++ bi->nmsgs = 0; ++ /* wake up our bh */ ++ complete(&bi->done); ++ } ++ } else if (s & BSC_S_TXW) { ++ bcm2708_bsc_fifo_fill(bi); ++ } else if (s & BSC_S_RXR) { ++ bcm2708_bsc_fifo_drain(bi); ++ } else { ++ handled = false; ++ } ++ ++early_exit: ++ spin_unlock(&bi->lock); ++ ++ return handled ? IRQ_HANDLED : IRQ_NONE; ++} ++ ++static int bcm2708_i2c_master_xfer(struct i2c_adapter *adap, ++ struct i2c_msg *msgs, int num) ++{ ++ struct bcm2708_i2c *bi = adap->algo_data; ++ unsigned long flags; ++ int ret; ++ ++ spin_lock_irqsave(&bi->lock, flags); ++ ++ reinit_completion(&bi->done); ++ bi->msg = msgs; ++ bi->pos = 0; ++ bi->nmsgs = num; ++ bi->error = false; ++ ++ ret = bcm2708_bsc_setup(bi); ++ ++ spin_unlock_irqrestore(&bi->lock, flags); ++ ++ /* check the result of the setup */ ++ if (ret < 0) ++ { ++ dev_err(&adap->dev, "transfer setup timed out\n"); ++ goto error_timeout; ++ } ++ ++ ret = wait_for_completion_timeout(&bi->done, adap->timeout); ++ if (ret == 0) { ++ dev_err(&adap->dev, "transfer timed out\n"); ++ goto error_timeout; ++ } ++ ++ ret = bi->error ? -EIO : num; ++ return ret; ++ ++error_timeout: ++ spin_lock_irqsave(&bi->lock, flags); ++ bcm2708_bsc_reset(bi); ++ bi->msg = 0; /* to inform the interrupt handler that there's nothing else to be done */ ++ bi->nmsgs = 0; ++ spin_unlock_irqrestore(&bi->lock, flags); ++ return -ETIMEDOUT; ++} ++ ++static u32 bcm2708_i2c_functionality(struct i2c_adapter *adap) ++{ ++ return I2C_FUNC_I2C | /*I2C_FUNC_10BIT_ADDR |*/ I2C_FUNC_SMBUS_EMUL; ++} ++ ++static struct i2c_algorithm bcm2708_i2c_algorithm = { ++ .master_xfer = bcm2708_i2c_master_xfer, ++ .functionality = bcm2708_i2c_functionality, ++}; ++ ++static int bcm2708_i2c_probe(struct platform_device *pdev) ++{ ++ struct resource *regs; ++ int irq, err = -ENOMEM; ++ struct clk *clk; ++ struct bcm2708_i2c *bi; ++ struct i2c_adapter *adap; ++ unsigned long bus_hz; ++ u32 cdiv; ++ ++ if (pdev->dev.of_node) { ++ u32 bus_clk_rate; ++ pdev->id = of_alias_get_id(pdev->dev.of_node, "i2c"); ++ if (pdev->id < 0) { ++ dev_err(&pdev->dev, "alias is missing\n"); ++ return -EINVAL; ++ } ++ if (!of_property_read_u32(pdev->dev.of_node, ++ "clock-frequency", &bus_clk_rate)) ++ baudrate = bus_clk_rate; ++ else ++ dev_warn(&pdev->dev, ++ "Could not read clock-frequency property\n"); ++ } ++ ++ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!regs) { ++ dev_err(&pdev->dev, "could not get IO memory\n"); ++ return -ENXIO; ++ } ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) { ++ dev_err(&pdev->dev, "could not get IRQ\n"); ++ return irq; ++ } ++ ++ clk = clk_get(&pdev->dev, NULL); ++ if (IS_ERR(clk)) { ++ dev_err(&pdev->dev, "could not find clk: %ld\n", PTR_ERR(clk)); ++ return PTR_ERR(clk); ++ } ++ ++ err = clk_prepare_enable(clk); ++ if (err) { ++ dev_err(&pdev->dev, "could not enable clk: %d\n", err); ++ goto out_clk_put; ++ } ++ ++ if (!pdev->dev.of_node) ++ bcm2708_i2c_init_pinmode(pdev->id); ++ ++ bi = kzalloc(sizeof(*bi), GFP_KERNEL); ++ if (!bi) ++ goto out_clk_disable; ++ ++ platform_set_drvdata(pdev, bi); ++ ++ adap = &bi->adapter; ++ adap->class = I2C_CLASS_HWMON | I2C_CLASS_DDC; ++ adap->algo = &bcm2708_i2c_algorithm; ++ adap->algo_data = bi; ++ adap->dev.parent = &pdev->dev; ++ adap->nr = pdev->id; ++ strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name)); ++ adap->dev.of_node = pdev->dev.of_node; ++ ++ switch (pdev->id) { ++ case 0: ++ adap->class = I2C_CLASS_HWMON; ++ break; ++ case 1: ++ adap->class = I2C_CLASS_DDC; ++ break; ++ case 2: ++ adap->class = I2C_CLASS_DDC; ++ break; ++ default: ++ dev_err(&pdev->dev, "can only bind to BSC 0, 1 or 2\n"); ++ err = -ENXIO; ++ goto out_free_bi; ++ } ++ ++ spin_lock_init(&bi->lock); ++ init_completion(&bi->done); ++ ++ bi->base = ioremap(regs->start, resource_size(regs)); ++ if (!bi->base) { ++ dev_err(&pdev->dev, "could not remap memory\n"); ++ goto out_free_bi; ++ } ++ ++ bi->irq = irq; ++ bi->clk = clk; ++ ++ err = request_irq(irq, bcm2708_i2c_interrupt, IRQF_SHARED, ++ dev_name(&pdev->dev), bi); ++ if (err) { ++ dev_err(&pdev->dev, "could not request IRQ: %d\n", err); ++ goto out_iounmap; ++ } ++ ++ bcm2708_bsc_reset(bi); ++ ++ err = i2c_add_numbered_adapter(adap); ++ if (err < 0) { ++ dev_err(&pdev->dev, "could not add I2C adapter: %d\n", err); ++ goto out_free_irq; ++ } ++ ++ bus_hz = clk_get_rate(bi->clk); ++ cdiv = bus_hz / baudrate; ++ if (cdiv > 0xffff) { ++ cdiv = 0xffff; ++ baudrate = bus_hz / cdiv; ++ } ++ bi->cdiv = cdiv; ++ ++ dev_info(&pdev->dev, "BSC%d Controller at 0x%08lx (irq %d) (baudrate %d)\n", ++ pdev->id, (unsigned long)regs->start, irq, baudrate); ++ ++ return 0; ++ ++out_free_irq: ++ free_irq(bi->irq, bi); ++out_iounmap: ++ iounmap(bi->base); ++out_free_bi: ++ kfree(bi); ++out_clk_disable: ++ clk_disable_unprepare(clk); ++out_clk_put: ++ clk_put(clk); ++ return err; ++} ++ ++static int bcm2708_i2c_remove(struct platform_device *pdev) ++{ ++ struct bcm2708_i2c *bi = platform_get_drvdata(pdev); ++ ++ platform_set_drvdata(pdev, NULL); ++ ++ i2c_del_adapter(&bi->adapter); ++ free_irq(bi->irq, bi); ++ iounmap(bi->base); ++ clk_disable_unprepare(bi->clk); ++ clk_put(bi->clk); ++ kfree(bi); ++ ++ return 0; ++} ++ ++static const struct of_device_id bcm2708_i2c_of_match[] = { ++ { .compatible = "brcm,bcm2708-i2c" }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, bcm2708_i2c_of_match); ++ ++static struct platform_driver bcm2708_i2c_driver = { ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = bcm2708_i2c_of_match, ++ }, ++ .probe = bcm2708_i2c_probe, ++ .remove = bcm2708_i2c_remove, ++}; ++ ++// module_platform_driver(bcm2708_i2c_driver); ++ ++ ++static int __init bcm2708_i2c_init(void) ++{ ++ return platform_driver_register(&bcm2708_i2c_driver); ++} ++ ++static void __exit bcm2708_i2c_exit(void) ++{ ++ platform_driver_unregister(&bcm2708_i2c_driver); ++} ++ ++module_init(bcm2708_i2c_init); ++module_exit(bcm2708_i2c_exit); ++ ++ ++ ++MODULE_DESCRIPTION("BSC controller driver for Broadcom BCM2708"); ++MODULE_AUTHOR("Chris Boot "); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:" DRV_NAME); +diff -Nur linux-4.1.13.orig/drivers/i2c/busses/Kconfig linux-rpi/drivers/i2c/busses/Kconfig +--- linux-4.1.13.orig/drivers/i2c/busses/Kconfig 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/i2c/busses/Kconfig 2015-11-29 09:42:37.371267984 +0100 +@@ -8,6 +8,25 @@ + comment "PC SMBus host controller drivers" + depends on PCI + ++config I2C_BCM2708 ++ tristate "BCM2708 BSC" ++ depends on MACH_BCM2708 || MACH_BCM2709 ++ help ++ Enabling this option will add BSC (Broadcom Serial Controller) ++ support for the BCM2708. BSC is a Broadcom proprietary bus compatible ++ with I2C/TWI/SMBus. ++ ++config I2C_BCM2708_BAUDRATE ++ prompt "BCM2708 I2C baudrate" ++ depends on I2C_BCM2708 ++ int ++ default 100000 ++ help ++ Set the I2C baudrate. This will alter the default value. A ++ different baudrate can be set by using a module parameter as well. If ++ no parameter is provided when loading, this is the value that will be ++ used. ++ + config I2C_ALI1535 + tristate "ALI 1535" + depends on PCI +@@ -362,7 +381,7 @@ + + config I2C_BCM2835 + tristate "Broadcom BCM2835 I2C controller" +- depends on ARCH_BCM2835 ++ depends on ARCH_BCM2835 || ARCH_BCM2708 || ARCH_BCM2709 + help + If you say yes to this option, support will be included for the + BCM2835 I2C controller. +diff -Nur linux-4.1.13.orig/drivers/i2c/busses/Makefile linux-rpi/drivers/i2c/busses/Makefile +--- linux-4.1.13.orig/drivers/i2c/busses/Makefile 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/i2c/busses/Makefile 2015-11-29 09:42:37.371267984 +0100 +@@ -2,6 +2,8 @@ + # Makefile for the i2c bus drivers. + # + ++obj-$(CONFIG_I2C_BCM2708) += i2c-bcm2708.o ++ + # ACPI drivers + obj-$(CONFIG_I2C_SCMI) += i2c-scmi.o + +diff -Nur linux-4.1.13.orig/drivers/input/joystick/Kconfig linux-rpi/drivers/input/joystick/Kconfig +--- linux-4.1.13.orig/drivers/input/joystick/Kconfig 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/input/joystick/Kconfig 2015-11-29 09:42:37.515258417 +0100 +@@ -329,4 +329,12 @@ + To compile this as a module choose M here: the module will be called + maplecontrol. + ++config JOYSTICK_RPISENSE ++ tristate "Raspberry Pi Sense HAT joystick" ++ depends on GPIOLIB && INPUT ++ select MFD_RPISENSE_CORE ++ ++ help ++ This is the joystick driver for the Raspberry Pi Sense HAT ++ + endif +diff -Nur linux-4.1.13.orig/drivers/input/joystick/Makefile linux-rpi/drivers/input/joystick/Makefile +--- linux-4.1.13.orig/drivers/input/joystick/Makefile 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/input/joystick/Makefile 2015-11-29 09:42:37.515258417 +0100 +@@ -32,4 +32,5 @@ + obj-$(CONFIG_JOYSTICK_XPAD) += xpad.o + obj-$(CONFIG_JOYSTICK_ZHENHUA) += zhenhua.o + obj-$(CONFIG_JOYSTICK_WALKERA0701) += walkera0701.o ++obj-$(CONFIG_JOYSTICK_RPISENSE) += rpisense-js.o + +diff -Nur linux-4.1.13.orig/drivers/input/joystick/rpisense-js.c linux-rpi/drivers/input/joystick/rpisense-js.c +--- linux-4.1.13.orig/drivers/input/joystick/rpisense-js.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/input/joystick/rpisense-js.c 2015-11-29 09:42:37.515258417 +0100 +@@ -0,0 +1,153 @@ ++/* ++ * Raspberry Pi Sense HAT joystick driver ++ * http://raspberrypi.org ++ * ++ * Copyright (C) 2015 Raspberry Pi ++ * ++ * Author: Serge Schneider ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++ ++#include ++ ++#include ++#include ++ ++struct rpisense *rpisense; ++unsigned char keymap[5] = {KEY_DOWN, KEY_RIGHT, KEY_UP, KEY_ENTER, KEY_LEFT,}; ++ ++static void keys_work_fn(struct work_struct *work) ++{ ++ int i; ++ static s32 prev_keys; ++ struct rpisense_js *rpisense_js = &rpisense->joystick; ++ s32 keys = rpisense_reg_read(rpisense, RPISENSE_KEYS); ++ s32 changes = keys ^ prev_keys; ++ ++ prev_keys = keys; ++ for (i = 0; i < 5; i++) { ++ if (changes & 1) { ++ input_report_key(rpisense_js->keys_dev, ++ keymap[i], keys & 1); ++ } ++ changes >>= 1; ++ keys >>= 1; ++ } ++ input_sync(rpisense_js->keys_dev); ++} ++ ++static irqreturn_t keys_irq_handler(int irq, void *pdev) ++{ ++ struct rpisense_js *rpisense_js = &rpisense->joystick; ++ ++ schedule_work(&rpisense_js->keys_work_s); ++ return IRQ_HANDLED; ++} ++ ++static int rpisense_js_probe(struct platform_device *pdev) ++{ ++ int ret; ++ int i; ++ struct rpisense_js *rpisense_js; ++ ++ rpisense = rpisense_get_dev(); ++ rpisense_js = &rpisense->joystick; ++ ++ INIT_WORK(&rpisense_js->keys_work_s, keys_work_fn); ++ ++ rpisense_js->keys_dev = input_allocate_device(); ++ if (!rpisense_js->keys_dev) { ++ dev_err(&pdev->dev, "Could not allocate input device.\n"); ++ return -ENOMEM; ++ } ++ ++ rpisense_js->keys_dev->evbit[0] = BIT_MASK(EV_KEY); ++ for (i = 0; i < ARRAY_SIZE(keymap); i++) { ++ set_bit(keymap[i], ++ rpisense_js->keys_dev->keybit); ++ } ++ ++ rpisense_js->keys_dev->name = "Raspberry Pi Sense HAT Joystick"; ++ rpisense_js->keys_dev->phys = "rpi-sense-joy/input0"; ++ rpisense_js->keys_dev->id.bustype = BUS_I2C; ++ rpisense_js->keys_dev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_REP); ++ rpisense_js->keys_dev->keycode = keymap; ++ rpisense_js->keys_dev->keycodesize = sizeof(unsigned char); ++ rpisense_js->keys_dev->keycodemax = ARRAY_SIZE(keymap); ++ ++ ret = input_register_device(rpisense_js->keys_dev); ++ if (ret) { ++ dev_err(&pdev->dev, "Could not register input device.\n"); ++ goto err_keys_alloc; ++ } ++ ++ ret = gpiod_direction_input(rpisense_js->keys_desc); ++ if (ret) { ++ dev_err(&pdev->dev, "Could not set keys-int direction.\n"); ++ goto err_keys_reg; ++ } ++ ++ rpisense_js->keys_irq = gpiod_to_irq(rpisense_js->keys_desc); ++ if (rpisense_js->keys_irq < 0) { ++ dev_err(&pdev->dev, "Could not determine keys-int IRQ.\n"); ++ ret = rpisense_js->keys_irq; ++ goto err_keys_reg; ++ } ++ ++ ret = devm_request_irq(&pdev->dev, rpisense_js->keys_irq, ++ keys_irq_handler, IRQF_TRIGGER_RISING, ++ "keys", &pdev->dev); ++ if (ret) { ++ dev_err(&pdev->dev, "IRQ request failed.\n"); ++ goto err_keys_reg; ++ } ++ return 0; ++err_keys_reg: ++ input_unregister_device(rpisense_js->keys_dev); ++err_keys_alloc: ++ input_free_device(rpisense_js->keys_dev); ++ return ret; ++} ++ ++static int rpisense_js_remove(struct platform_device *pdev) ++{ ++ struct rpisense_js *rpisense_js = &rpisense->joystick; ++ ++ input_unregister_device(rpisense_js->keys_dev); ++ input_free_device(rpisense_js->keys_dev); ++ return 0; ++} ++ ++#ifdef CONFIG_OF ++static const struct of_device_id rpisense_js_id[] = { ++ { .compatible = "rpi,rpi-sense-js" }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, rpisense_js_id); ++#endif ++ ++static struct platform_device_id rpisense_js_device_id[] = { ++ { .name = "rpi-sense-js" }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(platform, rpisense_js_device_id); ++ ++static struct platform_driver rpisense_js_driver = { ++ .probe = rpisense_js_probe, ++ .remove = rpisense_js_remove, ++ .driver = { ++ .name = "rpi-sense-js", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++module_platform_driver(rpisense_js_driver); ++ ++MODULE_DESCRIPTION("Raspberry Pi Sense HAT joystick driver"); ++MODULE_AUTHOR("Serge Schneider "); ++MODULE_LICENSE("GPL"); +diff -Nur linux-4.1.13.orig/drivers/input/touchscreen/ft6236.c linux-rpi/drivers/input/touchscreen/ft6236.c +--- linux-4.1.13.orig/drivers/input/touchscreen/ft6236.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/input/touchscreen/ft6236.c 2015-11-29 09:42:37.567254962 +0100 +@@ -0,0 +1,326 @@ ++/* ++ * FocalTech FT6236 TouchScreen driver. ++ * ++ * Copyright (c) 2010 Focal tech Ltd. ++ * ++ * This software is licensed under the terms of the GNU General Public ++ * License version 2, as published by the Free Software Foundation, and ++ * may be copied, distributed, and modified under those terms. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define FT6236_MAX_TOUCH_POINTS 2 ++ ++#define FT6236_REG_TH_GROUP 0x80 ++#define FT6236_REG_PERIODACTIVE 0x88 ++#define FT6236_REG_LIB_VER_H 0xa1 ++#define FT6236_REG_LIB_VER_L 0xa2 ++#define FT6236_REG_CIPHER 0xa3 ++#define FT6236_REG_FIRMID 0xa6 ++#define FT6236_REG_FOCALTECH_ID 0xa8 ++#define FT6236_REG_RELEASE_CODE_ID 0xaf ++ ++#define FT6236_EVENT_PRESS_DOWN 0 ++#define FT6236_EVENT_LIFT_UP 1 ++#define FT6236_EVENT_CONTACT 2 ++#define FT6236_EVENT_NO_EVENT 3 ++ ++struct ft6236_data { ++ struct i2c_client *client; ++ struct input_dev *input; ++ struct gpio_desc *reset_gpio; ++ u32 max_x; ++ u32 max_y; ++ bool invert_x; ++ bool invert_y; ++ bool swap_xy; ++}; ++ ++/* ++ * This struct is a touchpoint as stored in hardware. Note that the id, ++ * as well as the event, are stored in the upper nybble of the hi byte. ++ */ ++struct ft6236_touchpoint { ++ union { ++ u8 xhi; ++ u8 event; ++ }; ++ u8 xlo; ++ union { ++ u8 yhi; ++ u8 id; ++ }; ++ u8 ylo; ++ u8 weight; ++ u8 misc; ++} __packed; ++ ++/* This packet represents the register map as read from offset 0 */ ++struct ft6236_packet { ++ u8 dev_mode; ++ u8 gest_id; ++ u8 touches; ++ struct ft6236_touchpoint points[FT6236_MAX_TOUCH_POINTS]; ++} __packed; ++ ++static int ft6236_read(struct i2c_client *client, u8 reg, u8 len, void *data) ++{ ++ int error; ++ ++ error = i2c_smbus_read_i2c_block_data(client, reg, len, data); ++ if (error < 0) ++ return error; ++ ++ if (error != len) ++ return -EIO; ++ ++ return 0; ++} ++ ++static irqreturn_t ft6236_interrupt(int irq, void *dev_id) ++{ ++ struct ft6236_data *ft6236 = dev_id; ++ struct device *dev = &ft6236->client->dev; ++ struct input_dev *input = ft6236->input; ++ struct ft6236_packet buf; ++ u8 touches; ++ int i, error; ++ ++ error = ft6236_read(ft6236->client, 0, sizeof(buf), &buf); ++ if (error) { ++ dev_err(dev, "read touchdata failed %d\n", error); ++ return IRQ_HANDLED; ++ } ++ ++ touches = buf.touches & 0xf; ++ if (touches > FT6236_MAX_TOUCH_POINTS) { ++ dev_dbg(dev, ++ "%d touch points reported, only %d are supported\n", ++ touches, FT6236_MAX_TOUCH_POINTS); ++ touches = FT6236_MAX_TOUCH_POINTS; ++ } ++ ++ for (i = 0; i < touches; i++) { ++ struct ft6236_touchpoint *point = &buf.points[i]; ++ u16 x = ((point->xhi & 0xf) << 8) | buf.points[i].xlo; ++ u16 y = ((point->yhi & 0xf) << 8) | buf.points[i].ylo; ++ u8 event = point->event >> 6; ++ u8 id = point->id >> 4; ++ bool act = (event == FT6236_EVENT_PRESS_DOWN || ++ event == FT6236_EVENT_CONTACT); ++ ++ input_mt_slot(input, id); ++ input_mt_report_slot_state(input, MT_TOOL_FINGER, act); ++ if (!act) ++ continue; ++ ++ if (ft6236->invert_x) ++ x = ft6236->max_x - x; ++ ++ if (ft6236->invert_y) ++ y = ft6236->max_y - y; ++ ++ if (ft6236->swap_xy) { ++ input_report_abs(input, ABS_MT_POSITION_X, y); ++ input_report_abs(input, ABS_MT_POSITION_Y, x); ++ } else { ++ input_report_abs(input, ABS_MT_POSITION_X, x); ++ input_report_abs(input, ABS_MT_POSITION_Y, y); ++ } ++ } ++ ++ input_mt_sync_frame(input); ++ input_sync(input); ++ ++ return IRQ_HANDLED; ++} ++ ++static u8 ft6236_debug_read_byte(struct ft6236_data *ft6236, u8 reg) ++{ ++ struct i2c_client *client = ft6236->client; ++ u8 val = 0; ++ int error; ++ ++ error = ft6236_read(client, reg, 1, &val); ++ if (error) ++ dev_dbg(&client->dev, ++ "error reading register 0x%02x: %d\n", reg, error); ++ ++ return val; ++} ++ ++static void ft6236_debug_info(struct ft6236_data *ft6236) ++{ ++ struct device *dev = &ft6236->client->dev; ++ ++ dev_dbg(dev, "Touch threshold is %d\n", ++ ft6236_debug_read_byte(ft6236, FT6236_REG_TH_GROUP) * 4); ++ dev_dbg(dev, "Report rate is %dHz\n", ++ ft6236_debug_read_byte(ft6236, FT6236_REG_PERIODACTIVE) * 10); ++ dev_dbg(dev, "Firmware library version 0x%02x%02x\n", ++ ft6236_debug_read_byte(ft6236, FT6236_REG_LIB_VER_H), ++ ft6236_debug_read_byte(ft6236, FT6236_REG_LIB_VER_L)); ++ dev_dbg(dev, "Firmware version 0x%02x\n", ++ ft6236_debug_read_byte(ft6236, FT6236_REG_FIRMID)); ++ dev_dbg(dev, "Chip vendor ID 0x%02x\n", ++ ft6236_debug_read_byte(ft6236, FT6236_REG_CIPHER)); ++ dev_dbg(dev, "CTPM vendor ID 0x%02x\n", ++ ft6236_debug_read_byte(ft6236, FT6236_REG_FOCALTECH_ID)); ++ dev_dbg(dev, "Release code version 0x%02x\n", ++ ft6236_debug_read_byte(ft6236, FT6236_REG_RELEASE_CODE_ID)); ++} ++ ++static void ft6236_reset(struct ft6236_data *ft6236) ++{ ++ if (!ft6236->reset_gpio) ++ return; ++ ++ gpiod_set_value_cansleep(ft6236->reset_gpio, 1); ++ usleep_range(5000, 20000); ++ gpiod_set_value_cansleep(ft6236->reset_gpio, 0); ++ msleep(300); ++} ++ ++static int ft6236_probe(struct i2c_client *client, ++ const struct i2c_device_id *id) ++{ ++ struct device *dev = &client->dev; ++ struct ft6236_data *ft6236; ++ struct input_dev *input; ++ u32 fuzz_x = 0, fuzz_y = 0; ++ u8 val; ++ int error; ++ ++ if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) ++ return -ENXIO; ++ ++ if (!client->irq) { ++ dev_err(dev, "irq is missing\n"); ++ return -EINVAL; ++ } ++ ++ ft6236 = devm_kzalloc(dev, sizeof(*ft6236), GFP_KERNEL); ++ if (!ft6236) ++ return -ENOMEM; ++ ++ ft6236->client = client; ++ ft6236->reset_gpio = devm_gpiod_get_optional(dev, "reset", ++ GPIOD_OUT_LOW); ++ if (IS_ERR(ft6236->reset_gpio)) { ++ error = PTR_ERR(ft6236->reset_gpio); ++ if (error != -EPROBE_DEFER) ++ dev_err(dev, "error getting reset gpio: %d\n", error); ++ return error; ++ } ++ ++ ft6236_reset(ft6236); ++ ++ /* verify that the controller is present */ ++ error = ft6236_read(client, 0x00, 1, &val); ++ if (error) { ++ dev_err(dev, "failed to read from controller: %d\n", error); ++ return error; ++ } ++ ++ ft6236_debug_info(ft6236); ++ ++ input = devm_input_allocate_device(dev); ++ if (!input) ++ return -ENOMEM; ++ ++ ft6236->input = input; ++ input->name = client->name; ++ input->id.bustype = BUS_I2C; ++ ++ if (device_property_read_u32(dev, "touchscreen-size-x", ++ &ft6236->max_x) || ++ device_property_read_u32(dev, "touchscreen-size-y", ++ &ft6236->max_y)) { ++ dev_err(dev, "touchscreen-size-x and/or -y missing\n"); ++ return -EINVAL; ++ } ++ ++ device_property_read_u32(dev, "touchscreen-fuzz-x", &fuzz_x); ++ device_property_read_u32(dev, "touchscreen-fuzz-y", &fuzz_y); ++ ft6236->invert_x = device_property_read_bool(dev, ++ "touchscreen-inverted-x"); ++ ft6236->invert_y = device_property_read_bool(dev, ++ "touchscreen-inverted-y"); ++ ft6236->swap_xy = device_property_read_bool(dev, ++ "touchscreen-swapped-x-y"); ++ ++ if (ft6236->swap_xy) { ++ input_set_abs_params(input, ABS_MT_POSITION_X, 0, ++ ft6236->max_y, fuzz_y, 0); ++ input_set_abs_params(input, ABS_MT_POSITION_Y, 0, ++ ft6236->max_x, fuzz_x, 0); ++ } else { ++ input_set_abs_params(input, ABS_MT_POSITION_X, 0, ++ ft6236->max_x, fuzz_x, 0); ++ input_set_abs_params(input, ABS_MT_POSITION_Y, 0, ++ ft6236->max_y, fuzz_y, 0); ++ } ++ ++ error = input_mt_init_slots(input, FT6236_MAX_TOUCH_POINTS, ++ INPUT_MT_DIRECT | INPUT_MT_DROP_UNUSED); ++ if (error) ++ return error; ++ ++ error = devm_request_threaded_irq(dev, client->irq, NULL, ++ ft6236_interrupt, IRQF_ONESHOT, ++ client->name, ft6236); ++ if (error) { ++ dev_err(dev, "request irq %d failed: %d\n", client->irq, error); ++ return error; ++ } ++ ++ error = input_register_device(input); ++ if (error) { ++ dev_err(dev, "failed to register input device: %d\n", error); ++ return error; ++ } ++ ++ return 0; ++} ++ ++#ifdef CONFIG_OF ++static const struct of_device_id ft6236_of_match[] = { ++ { .compatible = "focaltech,ft6236", }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, ft6236_of_match); ++#endif ++ ++static const struct i2c_device_id ft6236_id[] = { ++ { "ft6236", }, ++ { } ++}; ++MODULE_DEVICE_TABLE(i2c, ft6236_id); ++ ++static struct i2c_driver ft6236_driver = { ++ .driver = { ++ .name = "ft6236", ++ .of_match_table = of_match_ptr(ft6236_of_match), ++ }, ++ .probe = ft6236_probe, ++ .id_table = ft6236_id, ++}; ++module_i2c_driver(ft6236_driver); ++ ++MODULE_AUTHOR("Sean Cross "); ++MODULE_AUTHOR("Noralf Trønnes "); ++MODULE_DESCRIPTION("FocalTech FT6236 TouchScreen driver"); ++MODULE_LICENSE("GPL v2"); +diff -Nur linux-4.1.13.orig/drivers/input/touchscreen/Kconfig linux-rpi/drivers/input/touchscreen/Kconfig +--- linux-4.1.13.orig/drivers/input/touchscreen/Kconfig 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/input/touchscreen/Kconfig 2015-11-29 09:42:37.563255228 +0100 +@@ -295,6 +295,19 @@ + To compile this driver as a module, choose M here: the + module will be called egalax_ts. + ++config TOUCHSCREEN_FT6236 ++ tristate "FT6236 I2C touchscreen" ++ depends on I2C ++ depends on GPIOLIB || COMPILE_TEST ++ help ++ Say Y here to enable support for the I2C connected FT6x06 and ++ FT6x36 family of capacitive touchscreen drivers. ++ ++ If unsure, say N. ++ ++ To compile this driver as a module, choose M here: the ++ module will be called ft6236. ++ + config TOUCHSCREEN_FUJITSU + tristate "Fujitsu serial touchscreen" + select SERIO +@@ -583,6 +596,13 @@ + To compile this driver as a module, choose M here: the + module will be called edt-ft5x06. + ++config TOUCHSCREEN_RPI_FT5406 ++ tristate "Raspberry Pi FT5406 driver" ++ depends on RASPBERRYPI_FIRMWARE ++ help ++ Say Y here to enable the Raspberry Pi memory based FT5406 device ++ ++ + config TOUCHSCREEN_MIGOR + tristate "Renesas MIGO-R touchscreen" + depends on SH_MIGOR && I2C +diff -Nur linux-4.1.13.orig/drivers/input/touchscreen/Makefile linux-rpi/drivers/input/touchscreen/Makefile +--- linux-4.1.13.orig/drivers/input/touchscreen/Makefile 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/input/touchscreen/Makefile 2015-11-29 09:42:37.563255228 +0100 +@@ -29,12 +29,14 @@ + obj-$(CONFIG_TOUCHSCREEN_DA9052) += da9052_tsi.o + obj-$(CONFIG_TOUCHSCREEN_DYNAPRO) += dynapro.o + obj-$(CONFIG_TOUCHSCREEN_EDT_FT5X06) += edt-ft5x06.o ++obj-$(CONFIG_TOUCHSCREEN_RPI_FT5406) += rpi-ft5406.o + obj-$(CONFIG_TOUCHSCREEN_HAMPSHIRE) += hampshire.o + obj-$(CONFIG_TOUCHSCREEN_GUNZE) += gunze.o + obj-$(CONFIG_TOUCHSCREEN_EETI) += eeti_ts.o + obj-$(CONFIG_TOUCHSCREEN_ELAN) += elants_i2c.o + obj-$(CONFIG_TOUCHSCREEN_ELO) += elo.o + obj-$(CONFIG_TOUCHSCREEN_EGALAX) += egalax_ts.o ++obj-$(CONFIG_TOUCHSCREEN_FT6236) += ft6236.o + obj-$(CONFIG_TOUCHSCREEN_FUJITSU) += fujitsu_ts.o + obj-$(CONFIG_TOUCHSCREEN_GOODIX) += goodix.o + obj-$(CONFIG_TOUCHSCREEN_ILI210X) += ili210x.o +diff -Nur linux-4.1.13.orig/drivers/input/touchscreen/rpi-ft5406.c linux-rpi/drivers/input/touchscreen/rpi-ft5406.c +--- linux-4.1.13.orig/drivers/input/touchscreen/rpi-ft5406.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/input/touchscreen/rpi-ft5406.c 2015-11-29 09:42:37.571254696 +0100 +@@ -0,0 +1,246 @@ ++/* ++ * Driver for memory based ft5406 touchscreen ++ * ++ * Copyright (C) 2015 Raspberry Pi ++ * ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define MAXIMUM_SUPPORTED_POINTS 10 ++struct ft5406_regs { ++ uint8_t device_mode; ++ uint8_t gesture_id; ++ uint8_t num_points; ++ struct ft5406_touch { ++ uint8_t xh; ++ uint8_t xl; ++ uint8_t yh; ++ uint8_t yl; ++ uint8_t res1; ++ uint8_t res2; ++ } point[MAXIMUM_SUPPORTED_POINTS]; ++}; ++ ++#define SCREEN_WIDTH 800 ++#define SCREEN_HEIGHT 480 ++ ++struct ft5406 { ++ struct platform_device * pdev; ++ struct input_dev * input_dev; ++ void __iomem * ts_base; ++ struct ft5406_regs * regs; ++ struct task_struct * thread; ++}; ++ ++/* Thread to poll for touchscreen events ++ * ++ * This thread polls the memory based register copy of the ft5406 registers ++ * using the number of points register to know whether the copy has been ++ * updated (we write 99 to the memory copy, the GPU will write between ++ * 0 - 10 points) ++ */ ++static int ft5406_thread(void *arg) ++{ ++ struct ft5406 *ts = (struct ft5406 *) arg; ++ struct ft5406_regs regs; ++ int known_ids = 0; ++ ++ while(!kthread_should_stop()) ++ { ++ // 60fps polling ++ msleep_interruptible(17); ++ memcpy_fromio(®s, ts->regs, sizeof(*ts->regs)); ++ writel(99, &ts->regs->num_points); ++ // Do not output if theres no new information (num_points is 99) ++ // or we have no touch points and don't need to release any ++ if(!(regs.num_points == 99 || (regs.num_points == 0 && known_ids == 0))) ++ { ++ int i; ++ int modified_ids = 0, released_ids; ++ for(i = 0; i < regs.num_points; i++) ++ { ++ int x = (((int) regs.point[i].xh & 0xf) << 8) + regs.point[i].xl; ++ int y = (((int) regs.point[i].yh & 0xf) << 8) + regs.point[i].yl; ++ int touchid = (regs.point[i].yh >> 4) & 0xf; ++ ++ modified_ids |= 1 << touchid; ++ ++ if(!((1 << touchid) & known_ids)) ++ dev_dbg(&ts->pdev->dev, "x = %d, y = %d, touchid = %d\n", x, y, touchid); ++ ++ input_mt_slot(ts->input_dev, touchid); ++ input_mt_report_slot_state(ts->input_dev, MT_TOOL_FINGER, 1); ++ ++ input_report_abs(ts->input_dev, ABS_MT_POSITION_X, x); ++ input_report_abs(ts->input_dev, ABS_MT_POSITION_Y, y); ++ ++ } ++ ++ released_ids = known_ids & ~modified_ids; ++ for(i = 0; released_ids && i < MAXIMUM_SUPPORTED_POINTS; i++) ++ { ++ if(released_ids & (1<pdev->dev, "Released %d, known = %x modified = %x\n", i, known_ids, modified_ids); ++ input_mt_slot(ts->input_dev, i); ++ input_mt_report_slot_state(ts->input_dev, MT_TOOL_FINGER, 0); ++ modified_ids &= ~(1 << i); ++ } ++ } ++ known_ids = modified_ids; ++ ++ input_mt_report_pointer_emulation(ts->input_dev, true); ++ input_sync(ts->input_dev); ++ } ++ ++ } ++ ++ return 0; ++} ++ ++static int ft5406_probe(struct platform_device *pdev) ++{ ++ int ret; ++ struct input_dev * input_dev = input_allocate_device(); ++ struct ft5406 * ts; ++ struct device_node *fw_node; ++ struct rpi_firmware *fw; ++ u32 touchbuf; ++ ++ dev_info(&pdev->dev, "Probing device\n"); ++ ++ fw_node = of_parse_phandle(pdev->dev.of_node, "firmware", 0); ++ if (!fw_node) { ++ dev_err(&pdev->dev, "Missing firmware node\n"); ++ return -ENOENT; ++ } ++ ++ fw = rpi_firmware_get(fw_node); ++ if (!fw) ++ return -EPROBE_DEFER; ++ ++ ret = rpi_firmware_property(fw, RPI_FIRMWARE_FRAMEBUFFER_GET_TOUCHBUF, ++ &touchbuf, sizeof(touchbuf)); ++ if (ret) { ++ dev_err(&pdev->dev, "Failed to get touch buffer\n"); ++ return ret; ++ } ++ ++ if (!touchbuf) { ++ dev_err(&pdev->dev, "Touchscreen not detected\n"); ++ return -ENODEV; ++ } ++ ++ dev_dbg(&pdev->dev, "Got TS buffer 0x%x\n", touchbuf); ++ ++ ts = kzalloc(sizeof(struct ft5406), GFP_KERNEL); ++ ++ if (!ts || !input_dev) { ++ ret = -ENOMEM; ++ dev_err(&pdev->dev, "Failed to allocate memory\n"); ++ return ret; ++ } ++ ts->input_dev = input_dev; ++ platform_set_drvdata(pdev, ts); ++ ts->pdev = pdev; ++ ++ input_dev->name = "FT5406 memory based driver"; ++ ++ __set_bit(EV_KEY, input_dev->evbit); ++ __set_bit(EV_SYN, input_dev->evbit); ++ __set_bit(EV_ABS, input_dev->evbit); ++ ++ input_set_abs_params(input_dev, ABS_MT_POSITION_X, 0, ++ SCREEN_WIDTH, 0, 0); ++ input_set_abs_params(input_dev, ABS_MT_POSITION_Y, 0, ++ SCREEN_HEIGHT, 0, 0); ++ ++ input_mt_init_slots(input_dev, MAXIMUM_SUPPORTED_POINTS, INPUT_MT_DIRECT); ++ ++ input_set_drvdata(input_dev, ts); ++ ++ ret = input_register_device(input_dev); ++ if (ret) { ++ dev_err(&pdev->dev, "could not register input device, %d\n", ++ ret); ++ return ret; ++ } ++ ++ // mmap the physical memory ++ touchbuf &= ~0xc0000000; ++ ts->ts_base = ioremap(touchbuf, sizeof(*ts->regs)); ++ if(ts->ts_base == NULL) ++ { ++ dev_err(&pdev->dev, "Failed to map physical address\n"); ++ input_unregister_device(input_dev); ++ kzfree(ts); ++ return -ENOMEM; ++ } ++ ++ ts->regs = (struct ft5406_regs *) ts->ts_base; ++ ++ // create thread to poll the touch events ++ ts->thread = kthread_run(ft5406_thread, ts, "ft5406"); ++ if(ts->thread == NULL) ++ { ++ dev_err(&pdev->dev, "Failed to create kernel thread"); ++ iounmap(ts->ts_base); ++ input_unregister_device(input_dev); ++ kzfree(ts); ++ } ++ ++ return 0; ++} ++ ++static int ft5406_remove(struct platform_device *pdev) ++{ ++ struct ft5406 *ts = (struct ft5406 *) platform_get_drvdata(pdev); ++ ++ dev_info(&pdev->dev, "Removing rpi-ft5406\n"); ++ ++ kthread_stop(ts->thread); ++ iounmap(ts->ts_base); ++ input_unregister_device(ts->input_dev); ++ kzfree(ts); ++ ++ return 0; ++} ++ ++static const struct of_device_id ft5406_match[] = { ++ { .compatible = "rpi,rpi-ft5406", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, ft5406_match); ++ ++static struct platform_driver ft5406_driver = { ++ .driver = { ++ .name = "rpi-ft5406", ++ .owner = THIS_MODULE, ++ .of_match_table = ft5406_match, ++ }, ++ .probe = ft5406_probe, ++ .remove = ft5406_remove, ++}; ++ ++module_platform_driver(ft5406_driver); ++ ++MODULE_AUTHOR("Gordon Hollingworth"); ++MODULE_DESCRIPTION("Touchscreen driver for memory based FT5406"); ++MODULE_LICENSE("GPL"); +diff -Nur linux-4.1.13.orig/drivers/irqchip/irq-bcm2835.c linux-rpi/drivers/irqchip/irq-bcm2835.c +--- linux-4.1.13.orig/drivers/irqchip/irq-bcm2835.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/irqchip/irq-bcm2835.c 2015-11-29 09:42:37.583253899 +0100 +@@ -56,7 +56,7 @@ + #include "irqchip.h" + + /* Put the bank and irq (32 bits) into the hwirq */ +-#define MAKE_HWIRQ(b, n) ((b << 5) | (n)) ++#define MAKE_HWIRQ(b, n) (((b) << 5) | (n)) + #define HWIRQ_BANK(i) (i >> 5) + #define HWIRQ_BIT(i) BIT(i & 0x1f) + +@@ -72,9 +72,13 @@ + | SHORTCUT1_MASK | SHORTCUT2_MASK) + + #define REG_FIQ_CONTROL 0x0c ++#define REG_FIQ_ENABLE 0x80 ++#define REG_FIQ_DISABLE 0 + + #define NR_BANKS 3 + #define IRQS_PER_BANK 32 ++#define NUMBER_IRQS MAKE_HWIRQ(NR_BANKS, 0) ++#define FIQ_START (NR_IRQS_BANK0 + MAKE_HWIRQ(NR_BANKS - 1, 0)) + + static int reg_pending[] __initconst = { 0x00, 0x04, 0x08 }; + static int reg_enable[] __initconst = { 0x18, 0x10, 0x14 }; +@@ -98,14 +102,38 @@ + static void __exception_irq_entry bcm2835_handle_irq( + struct pt_regs *regs); + ++static inline unsigned int hwirq_to_fiq(unsigned long hwirq) ++{ ++ hwirq -= NUMBER_IRQS; ++ /* ++ * The hwirq numbering used in this driver is: ++ * BASE (0-7) GPU1 (32-63) GPU2 (64-95). ++ * This differ from the one used in the FIQ register: ++ * GPU1 (0-31) GPU2 (32-63) BASE (64-71) ++ */ ++ if (hwirq >= 32) ++ return hwirq - 32; ++ ++ return hwirq + 64; ++} ++ + static void armctrl_mask_irq(struct irq_data *d) + { +- writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]); ++ if (d->hwirq >= NUMBER_IRQS) ++ writel_relaxed(REG_FIQ_DISABLE, intc.base + REG_FIQ_CONTROL); ++ else ++ writel_relaxed(HWIRQ_BIT(d->hwirq), ++ intc.disable[HWIRQ_BANK(d->hwirq)]); + } + + static void armctrl_unmask_irq(struct irq_data *d) + { +- writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]); ++ if (d->hwirq >= NUMBER_IRQS) ++ writel_relaxed(REG_FIQ_ENABLE | hwirq_to_fiq(d->hwirq), ++ intc.base + REG_FIQ_CONTROL); ++ else ++ writel_relaxed(HWIRQ_BIT(d->hwirq), ++ intc.enable[HWIRQ_BANK(d->hwirq)]); + } + + static struct irq_chip armctrl_chip = { +@@ -150,8 +178,9 @@ + panic("%s: unable to map IC registers\n", + node->full_name); + +- intc.domain = irq_domain_add_linear(node, MAKE_HWIRQ(NR_BANKS, 0), +- &armctrl_ops, NULL); ++ intc.base = base; ++ intc.domain = irq_domain_add_linear(node, NUMBER_IRQS * 2, ++ &armctrl_ops, NULL); + if (!intc.domain) + panic("%s: unable to create IRQ domain\n", node->full_name); + +@@ -168,8 +197,20 @@ + set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); + } + } +- + set_handle_irq(bcm2835_handle_irq); ++ ++ /* Make a duplicate irq range which is used to enable FIQ */ ++ for (b = 0; b < NR_BANKS; b++) { ++ for (i = 0; i < bank_irqs[b]; i++) { ++ irq = irq_create_mapping(intc.domain, ++ MAKE_HWIRQ(b, i) + NUMBER_IRQS); ++ BUG_ON(irq <= 0); ++ irq_set_chip(irq, &armctrl_chip); ++ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); ++ } ++ } ++ init_FIQ(FIQ_START); ++ + return 0; + } + +diff -Nur linux-4.1.13.orig/drivers/leds/leds-gpio.c linux-rpi/drivers/leds/leds-gpio.c +--- linux-4.1.13.orig/drivers/leds/leds-gpio.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/leds/leds-gpio.c 2015-11-29 09:42:37.639250178 +0100 +@@ -41,6 +41,13 @@ + led_dat->platform_gpio_blink_set(led_dat->gpiod, + led_dat->new_level, NULL, NULL); + led_dat->blinking = 0; ++ } else if (led_dat->cdev.flags & SET_GPIO_INPUT) { ++ gpiod_direction_input(led_dat->gpiod); ++ led_dat->cdev.flags &= ~SET_GPIO_INPUT; ++ } ++ else if (led_dat->cdev.flags & SET_GPIO_OUTPUT) { ++ gpiod_direction_output(led_dat->gpiod, led_dat->new_level); ++ led_dat->cdev.flags &= ~SET_GPIO_OUTPUT; + } else + gpiod_set_value_cansleep(led_dat->gpiod, led_dat->new_level); + } +@@ -61,7 +68,8 @@ + * seem to have a reliable way to know if we're already in one; so + * let's just assume the worst. + */ +- if (led_dat->can_sleep) { ++ if (led_dat->can_sleep || ++ (led_dat->cdev.flags & (SET_GPIO_INPUT | SET_GPIO_OUTPUT) )) { + led_dat->new_level = level; + schedule_work(&led_dat->work); + } else { +@@ -74,6 +82,13 @@ + } + } + ++static enum led_brightness gpio_led_get(struct led_classdev *led_cdev) ++{ ++ struct gpio_led_data *led_dat = ++ container_of(led_cdev, struct gpio_led_data, cdev); ++ return gpiod_get_value_cansleep(led_dat->gpiod) ? LED_FULL : LED_OFF; ++} ++ + static int gpio_blink_set(struct led_classdev *led_cdev, + unsigned long *delay_on, unsigned long *delay_off) + { +@@ -130,6 +145,7 @@ + led_dat->cdev.blink_set = gpio_blink_set; + } + led_dat->cdev.brightness_set = gpio_led_set; ++ led_dat->cdev.brightness_get = gpio_led_get; + if (template->default_state == LEDS_GPIO_DEFSTATE_KEEP) + state = !!gpiod_get_value_cansleep(led_dat->gpiod); + else +diff -Nur linux-4.1.13.orig/drivers/leds/trigger/Kconfig linux-rpi/drivers/leds/trigger/Kconfig +--- linux-4.1.13.orig/drivers/leds/trigger/Kconfig 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/leds/trigger/Kconfig 2015-11-29 09:42:37.643249912 +0100 +@@ -108,4 +108,11 @@ + This enables direct flash/torch on/off by the driver, kernel space. + If unsure, say Y. + ++config LEDS_TRIGGER_INPUT ++ tristate "LED Input Trigger" ++ depends on LEDS_TRIGGERS ++ help ++ This allows the GPIOs assigned to be LEDs to be initialised to inputs. ++ If unsure, say Y. ++ + endif # LEDS_TRIGGERS +diff -Nur linux-4.1.13.orig/drivers/leds/trigger/ledtrig-input.c linux-rpi/drivers/leds/trigger/ledtrig-input.c +--- linux-4.1.13.orig/drivers/leds/trigger/ledtrig-input.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/leds/trigger/ledtrig-input.c 2015-11-29 09:42:37.643249912 +0100 +@@ -0,0 +1,54 @@ ++/* ++ * Set LED GPIO to Input "Trigger" ++ * ++ * Copyright 2015 Phil Elwell ++ * ++ * Based on Nick Forbes's ledtrig-default-on.c. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include "../leds.h" ++ ++static void input_trig_activate(struct led_classdev *led_cdev) ++{ ++ led_cdev->flags |= SET_GPIO_INPUT; ++ led_set_brightness_async(led_cdev, 0); ++} ++ ++static void input_trig_deactivate(struct led_classdev *led_cdev) ++{ ++ led_cdev->flags |= SET_GPIO_OUTPUT; ++ led_set_brightness_async(led_cdev, 0); ++} ++ ++static struct led_trigger input_led_trigger = { ++ .name = "input", ++ .activate = input_trig_activate, ++ .deactivate = input_trig_deactivate, ++}; ++ ++static int __init input_trig_init(void) ++{ ++ return led_trigger_register(&input_led_trigger); ++} ++ ++static void __exit input_trig_exit(void) ++{ ++ led_trigger_unregister(&input_led_trigger); ++} ++ ++module_init(input_trig_init); ++module_exit(input_trig_exit); ++ ++MODULE_AUTHOR("Phil Elwell "); ++MODULE_DESCRIPTION("Set LED GPIO to Input \"trigger\""); ++MODULE_LICENSE("GPL"); +diff -Nur linux-4.1.13.orig/drivers/leds/trigger/Makefile linux-rpi/drivers/leds/trigger/Makefile +--- linux-4.1.13.orig/drivers/leds/trigger/Makefile 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/leds/trigger/Makefile 2015-11-29 09:42:37.643249912 +0100 +@@ -8,3 +8,4 @@ + obj-$(CONFIG_LEDS_TRIGGER_DEFAULT_ON) += ledtrig-default-on.o + obj-$(CONFIG_LEDS_TRIGGER_TRANSIENT) += ledtrig-transient.o + obj-$(CONFIG_LEDS_TRIGGER_CAMERA) += ledtrig-camera.o ++obj-$(CONFIG_LEDS_TRIGGER_INPUT) += ledtrig-input.o +diff -Nur linux-4.1.13.orig/drivers/mailbox/bcm2835-mailbox.c linux-rpi/drivers/mailbox/bcm2835-mailbox.c +--- linux-4.1.13.orig/drivers/mailbox/bcm2835-mailbox.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/mailbox/bcm2835-mailbox.c 2015-11-29 09:42:37.651249381 +0100 +@@ -0,0 +1,231 @@ ++/* ++ * Copyright (C) 2010,2015 Broadcom ++ * Copyright (C) 2013-2014 Lubomir Rintel ++ * Copyright (C) 2013 Craig McGeachie ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This device provides a mechanism for writing to the mailboxes, ++ * that are shared between the ARM and the VideoCore processor ++ * ++ * Parts of the driver are based on: ++ * - arch/arm/mach-bcm2708/vcio.c file written by Gray Girling that was ++ * obtained from branch "rpi-3.6.y" of git://github.com/raspberrypi/ ++ * linux.git ++ * - drivers/mailbox/bcm2835-ipc.c by Lubomir Rintel at ++ * https://github.com/hackerspace/rpi-linux/blob/lr-raspberry-pi/drivers/ ++ * mailbox/bcm2835-ipc.c ++ * - documentation available on the following web site: ++ * https://github.com/raspberrypi/firmware/wiki/Mailbox-property-interface ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* Mailboxes */ ++#define ARM_0_MAIL0 0x00 ++#define ARM_0_MAIL1 0x20 ++ ++/* ++ * Mailbox registers. We basically only support mailbox 0 & 1. We ++ * deliver to the VC in mailbox 1, it delivers to us in mailbox 0. See ++ * BCM2835-ARM-Peripherals.pdf section 1.3 for an explanation about ++ * the placement of memory barriers. ++ */ ++#define MAIL0_RD (ARM_0_MAIL0 + 0x00) ++#define MAIL0_POL (ARM_0_MAIL0 + 0x10) ++#define MAIL0_STA (ARM_0_MAIL0 + 0x18) ++#define MAIL0_CNF (ARM_0_MAIL0 + 0x1C) ++#define MAIL1_WRT (ARM_0_MAIL1 + 0x00) ++#define MAIL1_STA (ARM_0_MAIL1 + 0x18) ++ ++/* On ARCH_BCM270x these come through (arm_control.h ) */ ++#ifndef ARM_MS_FULL ++/* Status register: FIFO state. */ ++#define ARM_MS_FULL BIT(31) ++#define ARM_MS_EMPTY BIT(30) ++ ++/* Configuration register: Enable interrupts. */ ++#define ARM_MC_IHAVEDATAIRQEN BIT(0) ++#endif ++ ++struct bcm2835_mbox { ++ void __iomem *regs; ++ spinlock_t lock; ++ struct mbox_controller controller; ++}; ++ ++static struct bcm2835_mbox *bcm2835_link_mbox(struct mbox_chan *link) ++{ ++ return container_of(link->mbox, struct bcm2835_mbox, controller); ++} ++ ++static irqreturn_t bcm2835_mbox_irq(int irq, void *dev_id) ++{ ++ struct bcm2835_mbox *mbox = dev_id; ++ struct device *dev = mbox->controller.dev; ++ struct mbox_chan *link = &mbox->controller.chans[0]; ++ ++ while (!(readl(mbox->regs + MAIL0_STA) & ARM_MS_EMPTY)) { ++ u32 msg = readl(mbox->regs + MAIL0_RD); ++ dev_dbg(dev, "Reply 0x%08X\n", msg); ++ mbox_chan_received_data(link, &msg); ++ } ++ return IRQ_HANDLED; ++} ++ ++static int bcm2835_send_data(struct mbox_chan *link, void *data) ++{ ++ struct bcm2835_mbox *mbox = bcm2835_link_mbox(link); ++ u32 msg = *(u32 *)data; ++ ++ spin_lock(&mbox->lock); ++ writel(msg, mbox->regs + MAIL1_WRT); ++ dev_dbg(mbox->controller.dev, "Request 0x%08X\n", msg); ++ spin_unlock(&mbox->lock); ++ return 0; ++} ++ ++static int bcm2835_startup(struct mbox_chan *link) ++{ ++ struct bcm2835_mbox *mbox = bcm2835_link_mbox(link); ++ ++ /* Enable the interrupt on data reception */ ++ writel(ARM_MC_IHAVEDATAIRQEN, mbox->regs + MAIL0_CNF); ++ ++ return 0; ++} ++ ++static void bcm2835_shutdown(struct mbox_chan *link) ++{ ++ struct bcm2835_mbox *mbox = bcm2835_link_mbox(link); ++ ++ writel(0, mbox->regs + MAIL0_CNF); ++} ++ ++static bool bcm2835_last_tx_done(struct mbox_chan *link) ++{ ++ struct bcm2835_mbox *mbox = bcm2835_link_mbox(link); ++ bool ret; ++ ++ spin_lock(&mbox->lock); ++ ret = !(readl(mbox->regs + MAIL1_STA) & ARM_MS_FULL); ++ spin_unlock(&mbox->lock); ++ return ret; ++} ++ ++static const struct mbox_chan_ops bcm2835_mbox_chan_ops = { ++ .send_data = bcm2835_send_data, ++ .startup = bcm2835_startup, ++ .shutdown = bcm2835_shutdown, ++ .last_tx_done = bcm2835_last_tx_done ++}; ++ ++static struct mbox_chan *bcm2835_mbox_index_xlate(struct mbox_controller *mbox, ++ const struct of_phandle_args *sp) ++{ ++ if (sp->args_count != 0) ++ return NULL; ++ ++ return &mbox->chans[0]; ++} ++ ++static int bcm2835_mbox_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ int ret = 0; ++ struct resource *iomem; ++ struct bcm2835_mbox *mbox; ++ ++ mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL); ++ if (mbox == NULL) ++ return -ENOMEM; ++ spin_lock_init(&mbox->lock); ++ ++ ret = devm_request_irq(dev, platform_get_irq(pdev, 0), ++ bcm2835_mbox_irq, 0, dev_name(dev), mbox); ++ if (ret) { ++ dev_err(dev, "Failed to register a mailbox IRQ handler: %d\n", ++ ret); ++ return -ENODEV; ++ } ++ ++ iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ mbox->regs = devm_ioremap_resource(&pdev->dev, iomem); ++ if (IS_ERR(mbox->regs)) { ++ ret = PTR_ERR(mbox->regs); ++ dev_err(&pdev->dev, "Failed to remap mailbox regs: %d\n", ret); ++ return ret; ++ } ++ ++ mbox->controller.txdone_poll = true; ++ mbox->controller.txpoll_period = 5; ++ mbox->controller.ops = &bcm2835_mbox_chan_ops; ++ mbox->controller.of_xlate = &bcm2835_mbox_index_xlate; ++ mbox->controller.dev = dev; ++ mbox->controller.num_chans = 1; ++ mbox->controller.chans = devm_kzalloc(dev, ++ sizeof(*mbox->controller.chans), GFP_KERNEL); ++ if (!mbox->controller.chans) ++ return -ENOMEM; ++ ++ ret = mbox_controller_register(&mbox->controller); ++ if (ret) ++ return ret; ++ ++ platform_set_drvdata(pdev, mbox); ++ dev_info(dev, "mailbox enabled\n"); ++ ++ return ret; ++} ++ ++static int bcm2835_mbox_remove(struct platform_device *pdev) ++{ ++ struct bcm2835_mbox *mbox = platform_get_drvdata(pdev); ++ mbox_controller_unregister(&mbox->controller); ++ return 0; ++} ++ ++static const struct of_device_id bcm2835_mbox_of_match[] = { ++ { .compatible = "brcm,bcm2835-mbox", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, bcm2835_mbox_of_match); ++ ++static struct platform_driver bcm2835_mbox_driver = { ++ .driver = { ++ .name = "bcm2835-mbox", ++ .owner = THIS_MODULE, ++ .of_match_table = bcm2835_mbox_of_match, ++ }, ++ .probe = bcm2835_mbox_probe, ++ .remove = bcm2835_mbox_remove, ++}; ++ ++static int __init bcm2835_mbox_init(void) ++{ ++ return platform_driver_register(&bcm2835_mbox_driver); ++} ++arch_initcall(bcm2835_mbox_init); ++ ++static void __init bcm2835_mbox_exit(void) ++{ ++ platform_driver_unregister(&bcm2835_mbox_driver); ++} ++module_exit(bcm2835_mbox_exit); ++ ++MODULE_AUTHOR("Lubomir Rintel "); ++MODULE_DESCRIPTION("BCM2835 mailbox IPC driver"); ++MODULE_LICENSE("GPL v2"); +diff -Nur linux-4.1.13.orig/drivers/mailbox/Kconfig linux-rpi/drivers/mailbox/Kconfig +--- linux-4.1.13.orig/drivers/mailbox/Kconfig 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/mailbox/Kconfig 2015-11-29 09:42:37.651249381 +0100 +@@ -60,4 +60,13 @@ + An implementation of the Altera Mailbox soft core. It is used + to send message between processors. Say Y here if you want to use the + Altera mailbox support. ++ ++config BCM2835_MBOX ++ tristate "BCM2835 Mailbox" ++ depends on ARCH_BCM2835 || ARCH_BCM2708 || ARCH_BCM2709 ++ help ++ An implementation of the BCM2385 Mailbox. It is used to invoke ++ the services of the Videocore. Say Y here if you want to use the ++ BCM2835 Mailbox. ++ + endif +diff -Nur linux-4.1.13.orig/drivers/mailbox/mailbox.c linux-rpi/drivers/mailbox/mailbox.c +--- linux-4.1.13.orig/drivers/mailbox/mailbox.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/mailbox/mailbox.c 2015-11-29 09:42:37.651249381 +0100 +@@ -304,13 +304,23 @@ + unsigned long flags; + int ret; + +- if (!dev || !dev->of_node) { ++ if (!dev) { + pr_debug("%s: No owner device node\n", __func__); + return ERR_PTR(-ENODEV); + } + + mutex_lock(&con_mutex); + ++ if (!dev->of_node) { ++ chan = NULL; ++ /* pick the first controller in the list */ ++ list_for_each_entry(mbox, &mbox_cons, node) { ++ chan = &mbox->chans[0]; ++ break; ++ } ++ goto skip_dt; ++ } ++ + if (of_parse_phandle_with_args(dev->of_node, "mboxes", + "#mbox-cells", index, &spec)) { + dev_dbg(dev, "%s: can't parse \"mboxes\" property\n", __func__); +@@ -327,6 +337,7 @@ + + of_node_put(spec.np); + ++skip_dt: + if (!chan || chan->cl || !try_module_get(mbox->dev->driver->owner)) { + dev_dbg(dev, "%s: mailbox not free\n", __func__); + mutex_unlock(&con_mutex); +diff -Nur linux-4.1.13.orig/drivers/mailbox/Makefile linux-rpi/drivers/mailbox/Makefile +--- linux-4.1.13.orig/drivers/mailbox/Makefile 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/mailbox/Makefile 2015-11-29 09:42:37.651249381 +0100 +@@ -11,3 +11,5 @@ + obj-$(CONFIG_PCC) += pcc.o + + obj-$(CONFIG_ALTERA_MBOX) += mailbox-altera.o ++ ++obj-$(CONFIG_BCM2835_MBOX) += bcm2835-mailbox.o +diff -Nur linux-4.1.13.orig/drivers/media/platform/bcm2835/bcm2835-camera.c linux-rpi/drivers/media/platform/bcm2835/bcm2835-camera.c +--- linux-4.1.13.orig/drivers/media/platform/bcm2835/bcm2835-camera.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/media/platform/bcm2835/bcm2835-camera.c 2015-11-29 09:42:37.835237156 +0100 +@@ -0,0 +1,1843 @@ ++/* ++ * Broadcom BM2835 V4L2 driver ++ * ++ * Copyright © 2013 Raspberry Pi (Trading) Ltd. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ * ++ * Authors: Vincent Sanders ++ * Dave Stevenson ++ * Simon Mellor ++ * Luke Diamand ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mmal-common.h" ++#include "mmal-encodings.h" ++#include "mmal-vchiq.h" ++#include "mmal-msg.h" ++#include "mmal-parameters.h" ++#include "bcm2835-camera.h" ++ ++#define BM2835_MMAL_VERSION "0.0.2" ++#define BM2835_MMAL_MODULE_NAME "bcm2835-v4l2" ++#define MIN_WIDTH 16 ++#define MIN_HEIGHT 16 ++#define MAX_WIDTH 2592 ++#define MAX_HEIGHT 1944 ++#define MIN_BUFFER_SIZE (80*1024) ++ ++#define MAX_VIDEO_MODE_WIDTH 1280 ++#define MAX_VIDEO_MODE_HEIGHT 720 ++ ++MODULE_DESCRIPTION("Broadcom 2835 MMAL video capture"); ++MODULE_AUTHOR("Vincent Sanders"); ++MODULE_LICENSE("GPL"); ++MODULE_VERSION(BM2835_MMAL_VERSION); ++ ++int bcm2835_v4l2_debug; ++module_param_named(debug, bcm2835_v4l2_debug, int, 0644); ++MODULE_PARM_DESC(bcm2835_v4l2_debug, "Debug level 0-2"); ++ ++int max_video_width = MAX_VIDEO_MODE_WIDTH; ++int max_video_height = MAX_VIDEO_MODE_HEIGHT; ++module_param(max_video_width, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); ++MODULE_PARM_DESC(max_video_width, "Threshold for video mode"); ++module_param(max_video_height, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); ++MODULE_PARM_DESC(max_video_height, "Threshold for video mode"); ++ ++/* Gstreamer bug https://bugzilla.gnome.org/show_bug.cgi?id=726521 ++ * v4l2src does bad (and actually wrong) things when the vidioc_enum_framesizes ++ * function says type V4L2_FRMSIZE_TYPE_STEPWISE, which we do by default. ++ * It's happier if we just don't say anything at all, when it then ++ * sets up a load of defaults that it thinks might work. ++ * If gst_v4l2src_is_broken is non-zero, then we remove the function from ++ * our function table list (actually switch to an alternate set, but same ++ * result). ++ */ ++int gst_v4l2src_is_broken = 0; ++module_param(gst_v4l2src_is_broken, int, S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH); ++MODULE_PARM_DESC(gst_v4l2src_is_broken, "If non-zero, enable workaround for Gstreamer"); ++ ++static struct bm2835_mmal_dev *gdev; /* global device data */ ++ ++#define FPS_MIN 1 ++#define FPS_MAX 90 ++ ++/* timeperframe: min/max and default */ ++static const struct v4l2_fract ++ tpf_min = {.numerator = 1, .denominator = FPS_MAX}, ++ tpf_max = {.numerator = 1, .denominator = FPS_MIN}, ++ tpf_default = {.numerator = 1000, .denominator = 30000}; ++ ++/* video formats */ ++static struct mmal_fmt formats[] = { ++ { ++ .name = "4:2:0, planar, YUV", ++ .fourcc = V4L2_PIX_FMT_YUV420, ++ .flags = 0, ++ .mmal = MMAL_ENCODING_I420, ++ .depth = 12, ++ .mmal_component = MMAL_COMPONENT_CAMERA, ++ .ybbp = 1, ++ }, ++ { ++ .name = "4:2:2, packed, YUYV", ++ .fourcc = V4L2_PIX_FMT_YUYV, ++ .flags = 0, ++ .mmal = MMAL_ENCODING_YUYV, ++ .depth = 16, ++ .mmal_component = MMAL_COMPONENT_CAMERA, ++ .ybbp = 2, ++ }, ++ { ++ .name = "RGB24 (LE)", ++ .fourcc = V4L2_PIX_FMT_RGB24, ++ .flags = 0, ++ .mmal = MMAL_ENCODING_BGR24, ++ .depth = 24, ++ .mmal_component = MMAL_COMPONENT_CAMERA, ++ .ybbp = 3, ++ }, ++ { ++ .name = "JPEG", ++ .fourcc = V4L2_PIX_FMT_JPEG, ++ .flags = V4L2_FMT_FLAG_COMPRESSED, ++ .mmal = MMAL_ENCODING_JPEG, ++ .depth = 8, ++ .mmal_component = MMAL_COMPONENT_IMAGE_ENCODE, ++ .ybbp = 0, ++ }, ++ { ++ .name = "H264", ++ .fourcc = V4L2_PIX_FMT_H264, ++ .flags = V4L2_FMT_FLAG_COMPRESSED, ++ .mmal = MMAL_ENCODING_H264, ++ .depth = 8, ++ .mmal_component = MMAL_COMPONENT_VIDEO_ENCODE, ++ .ybbp = 0, ++ }, ++ { ++ .name = "MJPEG", ++ .fourcc = V4L2_PIX_FMT_MJPEG, ++ .flags = V4L2_FMT_FLAG_COMPRESSED, ++ .mmal = MMAL_ENCODING_MJPEG, ++ .depth = 8, ++ .mmal_component = MMAL_COMPONENT_VIDEO_ENCODE, ++ .ybbp = 0, ++ }, ++ { ++ .name = "4:2:2, packed, YVYU", ++ .fourcc = V4L2_PIX_FMT_YVYU, ++ .flags = 0, ++ .mmal = MMAL_ENCODING_YVYU, ++ .depth = 16, ++ .mmal_component = MMAL_COMPONENT_CAMERA, ++ .ybbp = 2, ++ }, ++ { ++ .name = "4:2:2, packed, VYUY", ++ .fourcc = V4L2_PIX_FMT_VYUY, ++ .flags = 0, ++ .mmal = MMAL_ENCODING_VYUY, ++ .depth = 16, ++ .mmal_component = MMAL_COMPONENT_CAMERA, ++ .ybbp = 2, ++ }, ++ { ++ .name = "4:2:2, packed, UYVY", ++ .fourcc = V4L2_PIX_FMT_UYVY, ++ .flags = 0, ++ .mmal = MMAL_ENCODING_UYVY, ++ .depth = 16, ++ .mmal_component = MMAL_COMPONENT_CAMERA, ++ .ybbp = 2, ++ }, ++ { ++ .name = "4:2:0, planar, NV12", ++ .fourcc = V4L2_PIX_FMT_NV12, ++ .flags = 0, ++ .mmal = MMAL_ENCODING_NV12, ++ .depth = 12, ++ .mmal_component = MMAL_COMPONENT_CAMERA, ++ .ybbp = 1, ++ }, ++ { ++ .name = "RGB24 (BE)", ++ .fourcc = V4L2_PIX_FMT_BGR24, ++ .flags = 0, ++ .mmal = MMAL_ENCODING_RGB24, ++ .depth = 24, ++ .mmal_component = MMAL_COMPONENT_CAMERA, ++ .ybbp = 3, ++ }, ++ { ++ .name = "4:2:0, planar, YVU", ++ .fourcc = V4L2_PIX_FMT_YVU420, ++ .flags = 0, ++ .mmal = MMAL_ENCODING_YV12, ++ .depth = 12, ++ .mmal_component = MMAL_COMPONENT_CAMERA, ++ .ybbp = 1, ++ }, ++ { ++ .name = "4:2:0, planar, NV21", ++ .fourcc = V4L2_PIX_FMT_NV21, ++ .flags = 0, ++ .mmal = MMAL_ENCODING_NV21, ++ .depth = 12, ++ .mmal_component = MMAL_COMPONENT_CAMERA, ++ .ybbp = 1, ++ }, ++ { ++ .name = "RGB32 (BE)", ++ .fourcc = V4L2_PIX_FMT_BGR32, ++ .flags = 0, ++ .mmal = MMAL_ENCODING_BGRA, ++ .depth = 32, ++ .mmal_component = MMAL_COMPONENT_CAMERA, ++ .ybbp = 4, ++ }, ++}; ++ ++static struct mmal_fmt *get_format(struct v4l2_format *f) ++{ ++ struct mmal_fmt *fmt; ++ unsigned int k; ++ ++ for (k = 0; k < ARRAY_SIZE(formats); k++) { ++ fmt = &formats[k]; ++ if (fmt->fourcc == f->fmt.pix.pixelformat) ++ break; ++ } ++ ++ if (k == ARRAY_SIZE(formats)) ++ return NULL; ++ ++ return &formats[k]; ++} ++ ++/* ------------------------------------------------------------------ ++ Videobuf queue operations ++ ------------------------------------------------------------------*/ ++ ++static int queue_setup(struct vb2_queue *vq, const struct v4l2_format *fmt, ++ unsigned int *nbuffers, unsigned int *nplanes, ++ unsigned int sizes[], void *alloc_ctxs[]) ++{ ++ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vq); ++ unsigned long size; ++ ++ /* refuse queue setup if port is not configured */ ++ if (dev->capture.port == NULL) { ++ v4l2_err(&dev->v4l2_dev, ++ "%s: capture port not configured\n", __func__); ++ return -EINVAL; ++ } ++ ++ size = dev->capture.port->current_buffer.size; ++ if (size == 0) { ++ v4l2_err(&dev->v4l2_dev, ++ "%s: capture port buffer size is zero\n", __func__); ++ return -EINVAL; ++ } ++ ++ if (*nbuffers < (dev->capture.port->current_buffer.num + 2)) ++ *nbuffers = (dev->capture.port->current_buffer.num + 2); ++ ++ *nplanes = 1; ++ ++ sizes[0] = size; ++ ++ /* ++ * videobuf2-vmalloc allocator is context-less so no need to set ++ * alloc_ctxs array. ++ */ ++ ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "%s: dev:%p\n", ++ __func__, dev); ++ ++ return 0; ++} ++ ++static int buffer_prepare(struct vb2_buffer *vb) ++{ ++ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vb->vb2_queue); ++ unsigned long size; ++ ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "%s: dev:%p\n", ++ __func__, dev); ++ ++ BUG_ON(dev->capture.port == NULL); ++ BUG_ON(dev->capture.fmt == NULL); ++ ++ size = dev->capture.stride * dev->capture.height; ++ if (vb2_plane_size(vb, 0) < size) { ++ v4l2_err(&dev->v4l2_dev, ++ "%s data will not fit into plane (%lu < %lu)\n", ++ __func__, vb2_plane_size(vb, 0), size); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static inline bool is_capturing(struct bm2835_mmal_dev *dev) ++{ ++ return dev->capture.camera_port == ++ &dev-> ++ component[MMAL_COMPONENT_CAMERA]->output[MMAL_CAMERA_PORT_CAPTURE]; ++} ++ ++static void buffer_cb(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port, ++ int status, ++ struct mmal_buffer *buf, ++ unsigned long length, u32 mmal_flags, s64 dts, s64 pts) ++{ ++ struct bm2835_mmal_dev *dev = port->cb_ctx; ++ ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "%s: status:%d, buf:%p, length:%lu, flags %u, pts %lld\n", ++ __func__, status, buf, length, mmal_flags, pts); ++ ++ if (status != 0) { ++ /* error in transfer */ ++ if (buf != NULL) { ++ /* there was a buffer with the error so return it */ ++ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); ++ } ++ return; ++ } else if (length == 0) { ++ /* stream ended */ ++ if (buf != NULL) { ++ /* this should only ever happen if the port is ++ * disabled and there are buffers still queued ++ */ ++ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); ++ pr_debug("Empty buffer"); ++ } else if (dev->capture.frame_count) { ++ /* grab another frame */ ++ if (is_capturing(dev)) { ++ pr_debug("Grab another frame"); ++ vchiq_mmal_port_parameter_set( ++ instance, ++ dev->capture. ++ camera_port, ++ MMAL_PARAMETER_CAPTURE, ++ &dev->capture. ++ frame_count, ++ sizeof(dev->capture.frame_count)); ++ } ++ } else { ++ /* signal frame completion */ ++ complete(&dev->capture.frame_cmplt); ++ } ++ } else { ++ if (dev->capture.frame_count) { ++ if (dev->capture.vc_start_timestamp != -1 && ++ pts != 0) { ++ s64 runtime_us = pts - ++ dev->capture.vc_start_timestamp; ++ u32 div = 0; ++ u32 rem = 0; ++ ++ div = ++ div_u64_rem(runtime_us, USEC_PER_SEC, &rem); ++ buf->vb.v4l2_buf.timestamp.tv_sec = ++ dev->capture.kernel_start_ts.tv_sec - 1 + ++ div; ++ buf->vb.v4l2_buf.timestamp.tv_usec = ++ dev->capture.kernel_start_ts.tv_usec + rem; ++ ++ if (buf->vb.v4l2_buf.timestamp.tv_usec >= ++ USEC_PER_SEC) { ++ buf->vb.v4l2_buf.timestamp.tv_sec++; ++ buf->vb.v4l2_buf.timestamp.tv_usec -= ++ USEC_PER_SEC; ++ } ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "Convert start time %d.%06d and %llu " ++ "with offset %llu to %d.%06d\n", ++ (int)dev->capture.kernel_start_ts. ++ tv_sec, ++ (int)dev->capture.kernel_start_ts. ++ tv_usec, ++ dev->capture.vc_start_timestamp, pts, ++ (int)buf->vb.v4l2_buf.timestamp.tv_sec, ++ (int)buf->vb.v4l2_buf.timestamp. ++ tv_usec); ++ } else { ++ v4l2_get_timestamp(&buf->vb.v4l2_buf.timestamp); ++ } ++ ++ vb2_set_plane_payload(&buf->vb, 0, length); ++ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_DONE); ++ ++ if (mmal_flags & MMAL_BUFFER_HEADER_FLAG_EOS && ++ is_capturing(dev)) { ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "Grab another frame as buffer has EOS"); ++ vchiq_mmal_port_parameter_set( ++ instance, ++ dev->capture. ++ camera_port, ++ MMAL_PARAMETER_CAPTURE, ++ &dev->capture. ++ frame_count, ++ sizeof(dev->capture.frame_count)); ++ } ++ } else { ++ /* signal frame completion */ ++ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); ++ complete(&dev->capture.frame_cmplt); ++ } ++ } ++} ++ ++static int enable_camera(struct bm2835_mmal_dev *dev) ++{ ++ int ret; ++ if (!dev->camera_use_count) { ++ ret = vchiq_mmal_component_enable( ++ dev->instance, ++ dev->component[MMAL_COMPONENT_CAMERA]); ++ if (ret < 0) { ++ v4l2_err(&dev->v4l2_dev, ++ "Failed enabling camera, ret %d\n", ret); ++ return -EINVAL; ++ } ++ } ++ dev->camera_use_count++; ++ v4l2_dbg(1, bcm2835_v4l2_debug, ++ &dev->v4l2_dev, "enabled camera (refcount %d)\n", ++ dev->camera_use_count); ++ return 0; ++} ++ ++static int disable_camera(struct bm2835_mmal_dev *dev) ++{ ++ int ret; ++ if (!dev->camera_use_count) { ++ v4l2_err(&dev->v4l2_dev, ++ "Disabled the camera when already disabled\n"); ++ return -EINVAL; ++ } ++ dev->camera_use_count--; ++ if (!dev->camera_use_count) { ++ unsigned int i = 0xFFFFFFFF; ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "Disabling camera\n"); ++ ret = ++ vchiq_mmal_component_disable( ++ dev->instance, ++ dev->component[MMAL_COMPONENT_CAMERA]); ++ if (ret < 0) { ++ v4l2_err(&dev->v4l2_dev, ++ "Failed disabling camera, ret %d\n", ret); ++ return -EINVAL; ++ } ++ vchiq_mmal_port_parameter_set( ++ dev->instance, ++ &dev->component[MMAL_COMPONENT_CAMERA]->control, ++ MMAL_PARAMETER_CAMERA_NUM, &i, ++ sizeof(i)); ++ } ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "Camera refcount now %d\n", dev->camera_use_count); ++ return 0; ++} ++ ++static void buffer_queue(struct vb2_buffer *vb) ++{ ++ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vb->vb2_queue); ++ struct mmal_buffer *buf = container_of(vb, struct mmal_buffer, vb); ++ int ret; ++ ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "%s: dev:%p buf:%p\n", __func__, dev, buf); ++ ++ buf->buffer = vb2_plane_vaddr(&buf->vb, 0); ++ buf->buffer_size = vb2_plane_size(&buf->vb, 0); ++ ++ ret = vchiq_mmal_submit_buffer(dev->instance, dev->capture.port, buf); ++ if (ret < 0) ++ v4l2_err(&dev->v4l2_dev, "%s: error submitting buffer\n", ++ __func__); ++} ++ ++static int start_streaming(struct vb2_queue *vq, unsigned int count) ++{ ++ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vq); ++ int ret; ++ int parameter_size; ++ ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "%s: dev:%p\n", ++ __func__, dev); ++ ++ /* ensure a format has actually been set */ ++ if (dev->capture.port == NULL) ++ return -EINVAL; ++ ++ if (enable_camera(dev) < 0) { ++ v4l2_err(&dev->v4l2_dev, "Failed to enable camera\n"); ++ return -EINVAL; ++ } ++ ++ /*init_completion(&dev->capture.frame_cmplt); */ ++ ++ /* enable frame capture */ ++ dev->capture.frame_count = 1; ++ ++ /* if the preview is not already running, wait for a few frames for AGC ++ * to settle down. ++ */ ++ if (!dev->component[MMAL_COMPONENT_PREVIEW]->enabled) ++ msleep(300); ++ ++ /* enable the connection from camera to encoder (if applicable) */ ++ if (dev->capture.camera_port != dev->capture.port ++ && dev->capture.camera_port) { ++ ret = vchiq_mmal_port_enable(dev->instance, ++ dev->capture.camera_port, NULL); ++ if (ret) { ++ v4l2_err(&dev->v4l2_dev, ++ "Failed to enable encode tunnel - error %d\n", ++ ret); ++ return -1; ++ } ++ } ++ ++ /* Get VC timestamp at this point in time */ ++ parameter_size = sizeof(dev->capture.vc_start_timestamp); ++ if (vchiq_mmal_port_parameter_get(dev->instance, ++ dev->capture.camera_port, ++ MMAL_PARAMETER_SYSTEM_TIME, ++ &dev->capture.vc_start_timestamp, ++ ¶meter_size)) { ++ v4l2_err(&dev->v4l2_dev, ++ "Failed to get VC start time - update your VC f/w\n"); ++ ++ /* Flag to indicate just to rely on kernel timestamps */ ++ dev->capture.vc_start_timestamp = -1; ++ } else ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "Start time %lld size %d\n", ++ dev->capture.vc_start_timestamp, parameter_size); ++ ++ v4l2_get_timestamp(&dev->capture.kernel_start_ts); ++ ++ /* enable the camera port */ ++ dev->capture.port->cb_ctx = dev; ++ ret = ++ vchiq_mmal_port_enable(dev->instance, dev->capture.port, buffer_cb); ++ if (ret) { ++ v4l2_err(&dev->v4l2_dev, ++ "Failed to enable capture port - error %d. " ++ "Disabling camera port again\n", ret); ++ ++ vchiq_mmal_port_disable(dev->instance, ++ dev->capture.camera_port); ++ if (disable_camera(dev) < 0) { ++ v4l2_err(&dev->v4l2_dev, "Failed to disable camera\n"); ++ return -EINVAL; ++ } ++ return -1; ++ } ++ ++ /* capture the first frame */ ++ vchiq_mmal_port_parameter_set(dev->instance, ++ dev->capture.camera_port, ++ MMAL_PARAMETER_CAPTURE, ++ &dev->capture.frame_count, ++ sizeof(dev->capture.frame_count)); ++ return 0; ++} ++ ++/* abort streaming and wait for last buffer */ ++static void stop_streaming(struct vb2_queue *vq) ++{ ++ int ret; ++ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vq); ++ ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "%s: dev:%p\n", ++ __func__, dev); ++ ++ init_completion(&dev->capture.frame_cmplt); ++ dev->capture.frame_count = 0; ++ ++ /* ensure a format has actually been set */ ++ if (dev->capture.port == NULL) { ++ v4l2_err(&dev->v4l2_dev, ++ "no capture port - stream not started?\n"); ++ return; ++ } ++ ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "stopping capturing\n"); ++ ++ /* stop capturing frames */ ++ vchiq_mmal_port_parameter_set(dev->instance, ++ dev->capture.camera_port, ++ MMAL_PARAMETER_CAPTURE, ++ &dev->capture.frame_count, ++ sizeof(dev->capture.frame_count)); ++ ++ /* wait for last frame to complete */ ++ ret = wait_for_completion_timeout(&dev->capture.frame_cmplt, HZ); ++ if (ret <= 0) ++ v4l2_err(&dev->v4l2_dev, ++ "error %d waiting for frame completion\n", ret); ++ ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "disabling connection\n"); ++ ++ /* disable the connection from camera to encoder */ ++ ret = vchiq_mmal_port_disable(dev->instance, dev->capture.camera_port); ++ if (!ret && dev->capture.camera_port != dev->capture.port) { ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "disabling port\n"); ++ ret = vchiq_mmal_port_disable(dev->instance, dev->capture.port); ++ } else if (dev->capture.camera_port != dev->capture.port) { ++ v4l2_err(&dev->v4l2_dev, "port_disable failed, error %d\n", ++ ret); ++ } ++ ++ if (disable_camera(dev) < 0) ++ v4l2_err(&dev->v4l2_dev, "Failed to disable camera\n"); ++} ++ ++static void bm2835_mmal_lock(struct vb2_queue *vq) ++{ ++ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vq); ++ mutex_lock(&dev->mutex); ++} ++ ++static void bm2835_mmal_unlock(struct vb2_queue *vq) ++{ ++ struct bm2835_mmal_dev *dev = vb2_get_drv_priv(vq); ++ mutex_unlock(&dev->mutex); ++} ++ ++static struct vb2_ops bm2835_mmal_video_qops = { ++ .queue_setup = queue_setup, ++ .buf_prepare = buffer_prepare, ++ .buf_queue = buffer_queue, ++ .start_streaming = start_streaming, ++ .stop_streaming = stop_streaming, ++ .wait_prepare = bm2835_mmal_unlock, ++ .wait_finish = bm2835_mmal_lock, ++}; ++ ++/* ------------------------------------------------------------------ ++ IOCTL operations ++ ------------------------------------------------------------------*/ ++ ++/* overlay ioctl */ ++static int vidioc_enum_fmt_vid_overlay(struct file *file, void *priv, ++ struct v4l2_fmtdesc *f) ++{ ++ struct mmal_fmt *fmt; ++ ++ if (f->index >= ARRAY_SIZE(formats)) ++ return -EINVAL; ++ ++ fmt = &formats[f->index]; ++ ++ strlcpy(f->description, fmt->name, sizeof(f->description)); ++ f->pixelformat = fmt->fourcc; ++ f->flags = fmt->flags; ++ ++ return 0; ++} ++ ++static int vidioc_g_fmt_vid_overlay(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct bm2835_mmal_dev *dev = video_drvdata(file); ++ ++ f->fmt.win = dev->overlay; ++ ++ return 0; ++} ++ ++static int vidioc_try_fmt_vid_overlay(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ /* Only support one format so get the current one. */ ++ vidioc_g_fmt_vid_overlay(file, priv, f); ++ ++ /* todo: allow the size and/or offset to be changed. */ ++ return 0; ++} ++ ++static int vidioc_s_fmt_vid_overlay(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct bm2835_mmal_dev *dev = video_drvdata(file); ++ ++ vidioc_try_fmt_vid_overlay(file, priv, f); ++ ++ dev->overlay = f->fmt.win; ++ ++ /* todo: program the preview port parameters */ ++ return 0; ++} ++ ++static int vidioc_overlay(struct file *file, void *f, unsigned int on) ++{ ++ int ret; ++ struct bm2835_mmal_dev *dev = video_drvdata(file); ++ struct vchiq_mmal_port *src; ++ struct vchiq_mmal_port *dst; ++ struct mmal_parameter_displayregion prev_config = { ++ .set = MMAL_DISPLAY_SET_LAYER | MMAL_DISPLAY_SET_ALPHA | ++ MMAL_DISPLAY_SET_DEST_RECT | MMAL_DISPLAY_SET_FULLSCREEN, ++ .layer = PREVIEW_LAYER, ++ .alpha = 255, ++ .fullscreen = 0, ++ .dest_rect = { ++ .x = dev->overlay.w.left, ++ .y = dev->overlay.w.top, ++ .width = dev->overlay.w.width, ++ .height = dev->overlay.w.height, ++ }, ++ }; ++ ++ if ((on && dev->component[MMAL_COMPONENT_PREVIEW]->enabled) || ++ (!on && !dev->component[MMAL_COMPONENT_PREVIEW]->enabled)) ++ return 0; /* already in requested state */ ++ ++ src = ++ &dev->component[MMAL_COMPONENT_CAMERA]-> ++ output[MMAL_CAMERA_PORT_PREVIEW]; ++ ++ if (!on) { ++ /* disconnect preview ports and disable component */ ++ ret = vchiq_mmal_port_disable(dev->instance, src); ++ if (!ret) ++ ret = ++ vchiq_mmal_port_connect_tunnel(dev->instance, src, ++ NULL); ++ if (ret >= 0) ++ ret = vchiq_mmal_component_disable( ++ dev->instance, ++ dev->component[MMAL_COMPONENT_PREVIEW]); ++ ++ disable_camera(dev); ++ return ret; ++ } ++ ++ /* set preview port format and connect it to output */ ++ dst = &dev->component[MMAL_COMPONENT_PREVIEW]->input[0]; ++ ++ ret = vchiq_mmal_port_set_format(dev->instance, src); ++ if (ret < 0) ++ goto error; ++ ++ ret = vchiq_mmal_port_parameter_set(dev->instance, dst, ++ MMAL_PARAMETER_DISPLAYREGION, ++ &prev_config, sizeof(prev_config)); ++ if (ret < 0) ++ goto error; ++ ++ if (enable_camera(dev) < 0) ++ goto error; ++ ++ ret = vchiq_mmal_component_enable( ++ dev->instance, ++ dev->component[MMAL_COMPONENT_PREVIEW]); ++ if (ret < 0) ++ goto error; ++ ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, "connecting %p to %p\n", ++ src, dst); ++ ret = vchiq_mmal_port_connect_tunnel(dev->instance, src, dst); ++ if (!ret) ++ ret = vchiq_mmal_port_enable(dev->instance, src, NULL); ++error: ++ return ret; ++} ++ ++static int vidioc_g_fbuf(struct file *file, void *fh, ++ struct v4l2_framebuffer *a) ++{ ++ /* The video overlay must stay within the framebuffer and can't be ++ positioned independently. */ ++ struct bm2835_mmal_dev *dev = video_drvdata(file); ++ struct vchiq_mmal_port *preview_port = ++ &dev->component[MMAL_COMPONENT_CAMERA]-> ++ output[MMAL_CAMERA_PORT_PREVIEW]; ++ a->flags = V4L2_FBUF_FLAG_OVERLAY; ++ a->fmt.width = preview_port->es.video.width; ++ a->fmt.height = preview_port->es.video.height; ++ a->fmt.pixelformat = V4L2_PIX_FMT_YUV420; ++ a->fmt.bytesperline = preview_port->es.video.width; ++ a->fmt.sizeimage = (preview_port->es.video.width * ++ preview_port->es.video.height * 3)>>1; ++ a->fmt.colorspace = V4L2_COLORSPACE_SMPTE170M; ++ ++ return 0; ++} ++ ++/* input ioctls */ ++static int vidioc_enum_input(struct file *file, void *priv, ++ struct v4l2_input *inp) ++{ ++ /* only a single camera input */ ++ if (inp->index != 0) ++ return -EINVAL; ++ ++ inp->type = V4L2_INPUT_TYPE_CAMERA; ++ sprintf(inp->name, "Camera %u", inp->index); ++ return 0; ++} ++ ++static int vidioc_g_input(struct file *file, void *priv, unsigned int *i) ++{ ++ *i = 0; ++ return 0; ++} ++ ++static int vidioc_s_input(struct file *file, void *priv, unsigned int i) ++{ ++ if (i != 0) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++/* capture ioctls */ ++static int vidioc_querycap(struct file *file, void *priv, ++ struct v4l2_capability *cap) ++{ ++ struct bm2835_mmal_dev *dev = video_drvdata(file); ++ u32 major; ++ u32 minor; ++ ++ vchiq_mmal_version(dev->instance, &major, &minor); ++ ++ strcpy(cap->driver, "bm2835 mmal"); ++ snprintf(cap->card, sizeof(cap->card), "mmal service %d.%d", ++ major, minor); ++ ++ snprintf(cap->bus_info, sizeof(cap->bus_info), ++ "platform:%s", dev->v4l2_dev.name); ++ cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OVERLAY | ++ V4L2_CAP_STREAMING | V4L2_CAP_READWRITE; ++ cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS; ++ ++ return 0; ++} ++ ++static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv, ++ struct v4l2_fmtdesc *f) ++{ ++ struct mmal_fmt *fmt; ++ ++ if (f->index >= ARRAY_SIZE(formats)) ++ return -EINVAL; ++ ++ fmt = &formats[f->index]; ++ ++ strlcpy(f->description, fmt->name, sizeof(f->description)); ++ f->pixelformat = fmt->fourcc; ++ f->flags = fmt->flags; ++ ++ return 0; ++} ++ ++static int vidioc_g_fmt_vid_cap(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct bm2835_mmal_dev *dev = video_drvdata(file); ++ ++ f->fmt.pix.width = dev->capture.width; ++ f->fmt.pix.height = dev->capture.height; ++ f->fmt.pix.field = V4L2_FIELD_NONE; ++ f->fmt.pix.pixelformat = dev->capture.fmt->fourcc; ++ f->fmt.pix.bytesperline = dev->capture.stride; ++ f->fmt.pix.sizeimage = dev->capture.buffersize; ++ ++ if (dev->capture.fmt->fourcc == V4L2_PIX_FMT_RGB24) ++ f->fmt.pix.colorspace = V4L2_COLORSPACE_SRGB; ++ else if (dev->capture.fmt->fourcc == V4L2_PIX_FMT_JPEG) ++ f->fmt.pix.colorspace = V4L2_COLORSPACE_JPEG; ++ else ++ f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; ++ f->fmt.pix.priv = 0; ++ ++ v4l2_dump_pix_format(1, bcm2835_v4l2_debug, &dev->v4l2_dev, &f->fmt.pix, ++ __func__); ++ return 0; ++} ++ ++static int vidioc_try_fmt_vid_cap(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ struct bm2835_mmal_dev *dev = video_drvdata(file); ++ struct mmal_fmt *mfmt; ++ ++ mfmt = get_format(f); ++ if (!mfmt) { ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "Fourcc format (0x%08x) unknown.\n", ++ f->fmt.pix.pixelformat); ++ f->fmt.pix.pixelformat = formats[0].fourcc; ++ mfmt = get_format(f); ++ } ++ ++ f->fmt.pix.field = V4L2_FIELD_NONE; ++ ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "Clipping/aligning %dx%d format %08X\n", ++ f->fmt.pix.width, f->fmt.pix.height, f->fmt.pix.pixelformat); ++ ++ v4l_bound_align_image(&f->fmt.pix.width, MIN_WIDTH, MAX_WIDTH, 1, ++ &f->fmt.pix.height, MIN_HEIGHT, MAX_HEIGHT, 1, 0); ++ f->fmt.pix.bytesperline = f->fmt.pix.width * mfmt->ybbp; ++ ++ /* Image buffer has to be padded to allow for alignment, even though ++ * we then remove that padding before delivering the buffer. ++ */ ++ f->fmt.pix.sizeimage = ((f->fmt.pix.height+15)&~15) * ++ (((f->fmt.pix.width+31)&~31) * mfmt->depth) >> 3; ++ ++ if ((mfmt->flags & V4L2_FMT_FLAG_COMPRESSED) && ++ f->fmt.pix.sizeimage < MIN_BUFFER_SIZE) ++ f->fmt.pix.sizeimage = MIN_BUFFER_SIZE; ++ ++ if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_RGB24) ++ f->fmt.pix.colorspace = V4L2_COLORSPACE_SRGB; ++ else if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_JPEG) ++ f->fmt.pix.colorspace = V4L2_COLORSPACE_JPEG; ++ else ++ f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; ++ f->fmt.pix.priv = 0; ++ ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "Now %dx%d format %08X\n", ++ f->fmt.pix.width, f->fmt.pix.height, f->fmt.pix.pixelformat); ++ ++ v4l2_dump_pix_format(1, bcm2835_v4l2_debug, &dev->v4l2_dev, &f->fmt.pix, ++ __func__); ++ return 0; ++} ++ ++static int mmal_setup_components(struct bm2835_mmal_dev *dev, ++ struct v4l2_format *f) ++{ ++ int ret; ++ struct vchiq_mmal_port *port = NULL, *camera_port = NULL; ++ struct vchiq_mmal_component *encode_component = NULL; ++ struct mmal_fmt *mfmt = get_format(f); ++ ++ BUG_ON(!mfmt); ++ ++ if (dev->capture.encode_component) { ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "vid_cap - disconnect previous tunnel\n"); ++ ++ /* Disconnect any previous connection */ ++ vchiq_mmal_port_connect_tunnel(dev->instance, ++ dev->capture.camera_port, NULL); ++ dev->capture.camera_port = NULL; ++ ret = vchiq_mmal_component_disable(dev->instance, ++ dev->capture. ++ encode_component); ++ if (ret) ++ v4l2_err(&dev->v4l2_dev, ++ "Failed to disable encode component %d\n", ++ ret); ++ ++ dev->capture.encode_component = NULL; ++ } ++ /* format dependant port setup */ ++ switch (mfmt->mmal_component) { ++ case MMAL_COMPONENT_CAMERA: ++ /* Make a further decision on port based on resolution */ ++ if (f->fmt.pix.width <= max_video_width ++ && f->fmt.pix.height <= max_video_height) ++ camera_port = port = ++ &dev->component[MMAL_COMPONENT_CAMERA]-> ++ output[MMAL_CAMERA_PORT_VIDEO]; ++ else ++ camera_port = port = ++ &dev->component[MMAL_COMPONENT_CAMERA]-> ++ output[MMAL_CAMERA_PORT_CAPTURE]; ++ break; ++ case MMAL_COMPONENT_IMAGE_ENCODE: ++ encode_component = dev->component[MMAL_COMPONENT_IMAGE_ENCODE]; ++ port = &dev->component[MMAL_COMPONENT_IMAGE_ENCODE]->output[0]; ++ camera_port = ++ &dev->component[MMAL_COMPONENT_CAMERA]-> ++ output[MMAL_CAMERA_PORT_CAPTURE]; ++ break; ++ case MMAL_COMPONENT_VIDEO_ENCODE: ++ encode_component = dev->component[MMAL_COMPONENT_VIDEO_ENCODE]; ++ port = &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0]; ++ camera_port = ++ &dev->component[MMAL_COMPONENT_CAMERA]-> ++ output[MMAL_CAMERA_PORT_VIDEO]; ++ break; ++ default: ++ break; ++ } ++ ++ if (!port) ++ return -EINVAL; ++ ++ if (encode_component) ++ camera_port->format.encoding = MMAL_ENCODING_OPAQUE; ++ else ++ camera_port->format.encoding = mfmt->mmal; ++ ++ camera_port->format.encoding_variant = 0; ++ camera_port->es.video.width = f->fmt.pix.width; ++ camera_port->es.video.height = f->fmt.pix.height; ++ camera_port->es.video.crop.x = 0; ++ camera_port->es.video.crop.y = 0; ++ camera_port->es.video.crop.width = f->fmt.pix.width; ++ camera_port->es.video.crop.height = f->fmt.pix.height; ++ camera_port->es.video.frame_rate.num = 0; ++ camera_port->es.video.frame_rate.den = 1; ++ camera_port->es.video.color_space = MMAL_COLOR_SPACE_JPEG_JFIF; ++ ++ ret = vchiq_mmal_port_set_format(dev->instance, camera_port); ++ ++ if (!ret ++ && camera_port == ++ &dev->component[MMAL_COMPONENT_CAMERA]-> ++ output[MMAL_CAMERA_PORT_VIDEO]) { ++ bool overlay_enabled = ++ !!dev->component[MMAL_COMPONENT_PREVIEW]->enabled; ++ struct vchiq_mmal_port *preview_port = ++ &dev->component[MMAL_COMPONENT_CAMERA]-> ++ output[MMAL_CAMERA_PORT_PREVIEW]; ++ /* Preview and encode ports need to match on resolution */ ++ if (overlay_enabled) { ++ /* Need to disable the overlay before we can update ++ * the resolution ++ */ ++ ret = ++ vchiq_mmal_port_disable(dev->instance, ++ preview_port); ++ if (!ret) ++ ret = ++ vchiq_mmal_port_connect_tunnel( ++ dev->instance, ++ preview_port, ++ NULL); ++ } ++ preview_port->es.video.width = f->fmt.pix.width; ++ preview_port->es.video.height = f->fmt.pix.height; ++ preview_port->es.video.crop.x = 0; ++ preview_port->es.video.crop.y = 0; ++ preview_port->es.video.crop.width = f->fmt.pix.width; ++ preview_port->es.video.crop.height = f->fmt.pix.height; ++ preview_port->es.video.frame_rate.num = ++ dev->capture.timeperframe.denominator; ++ preview_port->es.video.frame_rate.den = ++ dev->capture.timeperframe.numerator; ++ ret = vchiq_mmal_port_set_format(dev->instance, preview_port); ++ if (overlay_enabled) { ++ ret = vchiq_mmal_port_connect_tunnel( ++ dev->instance, ++ preview_port, ++ &dev->component[MMAL_COMPONENT_PREVIEW]->input[0]); ++ if (!ret) ++ ret = vchiq_mmal_port_enable(dev->instance, ++ preview_port, ++ NULL); ++ } ++ } ++ ++ if (ret) { ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "%s failed to set format %dx%d %08X\n", __func__, ++ f->fmt.pix.width, f->fmt.pix.height, ++ f->fmt.pix.pixelformat); ++ /* ensure capture is not going to be tried */ ++ dev->capture.port = NULL; ++ } else { ++ if (encode_component) { ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "vid_cap - set up encode comp\n"); ++ ++ /* configure buffering */ ++ camera_port->current_buffer.size = ++ camera_port->recommended_buffer.size; ++ camera_port->current_buffer.num = ++ camera_port->recommended_buffer.num; ++ ++ ret = ++ vchiq_mmal_port_connect_tunnel( ++ dev->instance, ++ camera_port, ++ &encode_component->input[0]); ++ if (ret) { ++ v4l2_dbg(1, bcm2835_v4l2_debug, ++ &dev->v4l2_dev, ++ "%s failed to create connection\n", ++ __func__); ++ /* ensure capture is not going to be tried */ ++ dev->capture.port = NULL; ++ } else { ++ port->es.video.width = f->fmt.pix.width; ++ port->es.video.height = f->fmt.pix.height; ++ port->es.video.crop.x = 0; ++ port->es.video.crop.y = 0; ++ port->es.video.crop.width = f->fmt.pix.width; ++ port->es.video.crop.height = f->fmt.pix.height; ++ port->es.video.frame_rate.num = ++ dev->capture.timeperframe.denominator; ++ port->es.video.frame_rate.den = ++ dev->capture.timeperframe.numerator; ++ ++ port->format.encoding = mfmt->mmal; ++ port->format.encoding_variant = 0; ++ /* Set any encoding specific parameters */ ++ switch (mfmt->mmal_component) { ++ case MMAL_COMPONENT_VIDEO_ENCODE: ++ port->format.bitrate = ++ dev->capture.encode_bitrate; ++ break; ++ case MMAL_COMPONENT_IMAGE_ENCODE: ++ /* Could set EXIF parameters here */ ++ break; ++ default: ++ break; ++ } ++ ret = vchiq_mmal_port_set_format(dev->instance, ++ port); ++ if (ret) ++ v4l2_dbg(1, bcm2835_v4l2_debug, ++ &dev->v4l2_dev, ++ "%s failed to set format %dx%d fmt %08X\n", ++ __func__, ++ f->fmt.pix.width, ++ f->fmt.pix.height, ++ f->fmt.pix.pixelformat ++ ); ++ } ++ ++ if (!ret) { ++ ret = vchiq_mmal_component_enable( ++ dev->instance, ++ encode_component); ++ if (ret) { ++ v4l2_dbg(1, bcm2835_v4l2_debug, ++ &dev->v4l2_dev, ++ "%s Failed to enable encode components\n", ++ __func__); ++ } ++ } ++ if (!ret) { ++ /* configure buffering */ ++ port->current_buffer.num = 1; ++ port->current_buffer.size = ++ f->fmt.pix.sizeimage; ++ if (port->format.encoding == ++ MMAL_ENCODING_JPEG) { ++ v4l2_dbg(1, bcm2835_v4l2_debug, ++ &dev->v4l2_dev, ++ "JPG - buf size now %d was %d\n", ++ f->fmt.pix.sizeimage, ++ port->current_buffer.size); ++ port->current_buffer.size = ++ (f->fmt.pix.sizeimage < ++ (100 << 10)) ++ ? (100 << 10) : f->fmt.pix. ++ sizeimage; ++ } ++ v4l2_dbg(1, bcm2835_v4l2_debug, ++ &dev->v4l2_dev, ++ "vid_cap - cur_buf.size set to %d\n", ++ f->fmt.pix.sizeimage); ++ port->current_buffer.alignment = 0; ++ } ++ } else { ++ /* configure buffering */ ++ camera_port->current_buffer.num = 1; ++ camera_port->current_buffer.size = f->fmt.pix.sizeimage; ++ camera_port->current_buffer.alignment = 0; ++ } ++ ++ if (!ret) { ++ dev->capture.fmt = mfmt; ++ dev->capture.stride = f->fmt.pix.bytesperline; ++ dev->capture.width = camera_port->es.video.crop.width; ++ dev->capture.height = camera_port->es.video.crop.height; ++ dev->capture.buffersize = port->current_buffer.size; ++ ++ /* select port for capture */ ++ dev->capture.port = port; ++ dev->capture.camera_port = camera_port; ++ dev->capture.encode_component = encode_component; ++ v4l2_dbg(1, bcm2835_v4l2_debug, ++ &dev->v4l2_dev, ++ "Set dev->capture.fmt %08X, %dx%d, stride %d, size %d", ++ port->format.encoding, ++ dev->capture.width, dev->capture.height, ++ dev->capture.stride, dev->capture.buffersize); ++ } ++ } ++ ++ /* todo: Need to convert the vchiq/mmal error into a v4l2 error. */ ++ return ret; ++} ++ ++static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, ++ struct v4l2_format *f) ++{ ++ int ret; ++ struct bm2835_mmal_dev *dev = video_drvdata(file); ++ struct mmal_fmt *mfmt; ++ ++ /* try the format to set valid parameters */ ++ ret = vidioc_try_fmt_vid_cap(file, priv, f); ++ if (ret) { ++ v4l2_err(&dev->v4l2_dev, ++ "vid_cap - vidioc_try_fmt_vid_cap failed\n"); ++ return ret; ++ } ++ ++ /* if a capture is running refuse to set format */ ++ if (vb2_is_busy(&dev->capture.vb_vidq)) { ++ v4l2_info(&dev->v4l2_dev, "%s device busy\n", __func__); ++ return -EBUSY; ++ } ++ ++ /* If the format is unsupported v4l2 says we should switch to ++ * a supported one and not return an error. */ ++ mfmt = get_format(f); ++ if (!mfmt) { ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "Fourcc format (0x%08x) unknown.\n", ++ f->fmt.pix.pixelformat); ++ f->fmt.pix.pixelformat = formats[0].fourcc; ++ mfmt = get_format(f); ++ } ++ ++ ret = mmal_setup_components(dev, f); ++ if (ret != 0) { ++ v4l2_err(&dev->v4l2_dev, ++ "%s: failed to setup mmal components: %d\n", ++ __func__, ret); ++ ret = -EINVAL; ++ } ++ ++ return ret; ++} ++ ++int vidioc_enum_framesizes(struct file *file, void *fh, ++ struct v4l2_frmsizeenum *fsize) ++{ ++ static const struct v4l2_frmsize_stepwise sizes = { ++ MIN_WIDTH, MAX_WIDTH, 2, ++ MIN_HEIGHT, MAX_HEIGHT, 2 ++ }; ++ int i; ++ ++ if (fsize->index) ++ return -EINVAL; ++ for (i = 0; i < ARRAY_SIZE(formats); i++) ++ if (formats[i].fourcc == fsize->pixel_format) ++ break; ++ if (i == ARRAY_SIZE(formats)) ++ return -EINVAL; ++ fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE; ++ fsize->stepwise = sizes; ++ return 0; ++} ++ ++/* timeperframe is arbitrary and continous */ ++static int vidioc_enum_frameintervals(struct file *file, void *priv, ++ struct v4l2_frmivalenum *fival) ++{ ++ int i; ++ ++ if (fival->index) ++ return -EINVAL; ++ ++ for (i = 0; i < ARRAY_SIZE(formats); i++) ++ if (formats[i].fourcc == fival->pixel_format) ++ break; ++ if (i == ARRAY_SIZE(formats)) ++ return -EINVAL; ++ ++ /* regarding width & height - we support any within range */ ++ if (fival->width < MIN_WIDTH || fival->width > MAX_WIDTH || ++ fival->height < MIN_HEIGHT || fival->height > MAX_HEIGHT) ++ return -EINVAL; ++ ++ fival->type = V4L2_FRMIVAL_TYPE_CONTINUOUS; ++ ++ /* fill in stepwise (step=1.0 is requred by V4L2 spec) */ ++ fival->stepwise.min = tpf_min; ++ fival->stepwise.max = tpf_max; ++ fival->stepwise.step = (struct v4l2_fract) {1, 1}; ++ ++ return 0; ++} ++ ++static int vidioc_g_parm(struct file *file, void *priv, ++ struct v4l2_streamparm *parm) ++{ ++ struct bm2835_mmal_dev *dev = video_drvdata(file); ++ ++ if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) ++ return -EINVAL; ++ ++ parm->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; ++ parm->parm.capture.timeperframe = dev->capture.timeperframe; ++ parm->parm.capture.readbuffers = 1; ++ return 0; ++} ++ ++#define FRACT_CMP(a, OP, b) \ ++ ((u64)(a).numerator * (b).denominator OP \ ++ (u64)(b).numerator * (a).denominator) ++ ++static int vidioc_s_parm(struct file *file, void *priv, ++ struct v4l2_streamparm *parm) ++{ ++ struct bm2835_mmal_dev *dev = video_drvdata(file); ++ struct v4l2_fract tpf; ++ struct mmal_parameter_rational fps_param; ++ ++ if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) ++ return -EINVAL; ++ ++ tpf = parm->parm.capture.timeperframe; ++ ++ /* tpf: {*, 0} resets timing; clip to [min, max]*/ ++ tpf = tpf.denominator ? tpf : tpf_default; ++ tpf = FRACT_CMP(tpf, <, tpf_min) ? tpf_min : tpf; ++ tpf = FRACT_CMP(tpf, >, tpf_max) ? tpf_max : tpf; ++ ++ dev->capture.timeperframe = tpf; ++ parm->parm.capture.timeperframe = tpf; ++ parm->parm.capture.readbuffers = 1; ++ ++ fps_param.num = 0; /* Select variable fps, and then use ++ * FPS_RANGE to select the actual limits. ++ */ ++ fps_param.den = 1; ++ set_framerate_params(dev); ++ ++ return 0; ++} ++ ++static const struct v4l2_ioctl_ops camera0_ioctl_ops = { ++ /* overlay */ ++ .vidioc_enum_fmt_vid_overlay = vidioc_enum_fmt_vid_overlay, ++ .vidioc_g_fmt_vid_overlay = vidioc_g_fmt_vid_overlay, ++ .vidioc_try_fmt_vid_overlay = vidioc_try_fmt_vid_overlay, ++ .vidioc_s_fmt_vid_overlay = vidioc_s_fmt_vid_overlay, ++ .vidioc_overlay = vidioc_overlay, ++ .vidioc_g_fbuf = vidioc_g_fbuf, ++ ++ /* inputs */ ++ .vidioc_enum_input = vidioc_enum_input, ++ .vidioc_g_input = vidioc_g_input, ++ .vidioc_s_input = vidioc_s_input, ++ ++ /* capture */ ++ .vidioc_querycap = vidioc_querycap, ++ .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, ++ .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, ++ .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, ++ .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, ++ ++ /* buffer management */ ++ .vidioc_reqbufs = vb2_ioctl_reqbufs, ++ .vidioc_create_bufs = vb2_ioctl_create_bufs, ++ .vidioc_prepare_buf = vb2_ioctl_prepare_buf, ++ .vidioc_querybuf = vb2_ioctl_querybuf, ++ .vidioc_qbuf = vb2_ioctl_qbuf, ++ .vidioc_dqbuf = vb2_ioctl_dqbuf, ++ .vidioc_enum_framesizes = vidioc_enum_framesizes, ++ .vidioc_enum_frameintervals = vidioc_enum_frameintervals, ++ .vidioc_g_parm = vidioc_g_parm, ++ .vidioc_s_parm = vidioc_s_parm, ++ .vidioc_streamon = vb2_ioctl_streamon, ++ .vidioc_streamoff = vb2_ioctl_streamoff, ++ ++ .vidioc_log_status = v4l2_ctrl_log_status, ++ .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, ++ .vidioc_unsubscribe_event = v4l2_event_unsubscribe, ++}; ++ ++static const struct v4l2_ioctl_ops camera0_ioctl_ops_gstreamer = { ++ /* overlay */ ++ .vidioc_enum_fmt_vid_overlay = vidioc_enum_fmt_vid_overlay, ++ .vidioc_g_fmt_vid_overlay = vidioc_g_fmt_vid_overlay, ++ .vidioc_try_fmt_vid_overlay = vidioc_try_fmt_vid_overlay, ++ .vidioc_s_fmt_vid_overlay = vidioc_s_fmt_vid_overlay, ++ .vidioc_overlay = vidioc_overlay, ++ .vidioc_g_fbuf = vidioc_g_fbuf, ++ ++ /* inputs */ ++ .vidioc_enum_input = vidioc_enum_input, ++ .vidioc_g_input = vidioc_g_input, ++ .vidioc_s_input = vidioc_s_input, ++ ++ /* capture */ ++ .vidioc_querycap = vidioc_querycap, ++ .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap, ++ .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap, ++ .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap, ++ .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, ++ ++ /* buffer management */ ++ .vidioc_reqbufs = vb2_ioctl_reqbufs, ++ .vidioc_create_bufs = vb2_ioctl_create_bufs, ++ .vidioc_prepare_buf = vb2_ioctl_prepare_buf, ++ .vidioc_querybuf = vb2_ioctl_querybuf, ++ .vidioc_qbuf = vb2_ioctl_qbuf, ++ .vidioc_dqbuf = vb2_ioctl_dqbuf, ++ /* Remove this function ptr to fix gstreamer bug ++ .vidioc_enum_framesizes = vidioc_enum_framesizes, */ ++ .vidioc_enum_frameintervals = vidioc_enum_frameintervals, ++ .vidioc_g_parm = vidioc_g_parm, ++ .vidioc_s_parm = vidioc_s_parm, ++ .vidioc_streamon = vb2_ioctl_streamon, ++ .vidioc_streamoff = vb2_ioctl_streamoff, ++ ++ .vidioc_log_status = v4l2_ctrl_log_status, ++ .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, ++ .vidioc_unsubscribe_event = v4l2_event_unsubscribe, ++}; ++ ++/* ------------------------------------------------------------------ ++ Driver init/finalise ++ ------------------------------------------------------------------*/ ++ ++static const struct v4l2_file_operations camera0_fops = { ++ .owner = THIS_MODULE, ++ .open = v4l2_fh_open, ++ .release = vb2_fop_release, ++ .read = vb2_fop_read, ++ .poll = vb2_fop_poll, ++ .unlocked_ioctl = video_ioctl2, /* V4L2 ioctl handler */ ++ .mmap = vb2_fop_mmap, ++}; ++ ++static struct video_device vdev_template = { ++ .name = "camera0", ++ .fops = &camera0_fops, ++ .ioctl_ops = &camera0_ioctl_ops, ++ .release = video_device_release_empty, ++}; ++ ++static int set_camera_parameters(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_component *camera) ++{ ++ int ret; ++ struct mmal_parameter_camera_config cam_config = { ++ .max_stills_w = MAX_WIDTH, ++ .max_stills_h = MAX_HEIGHT, ++ .stills_yuv422 = 1, ++ .one_shot_stills = 1, ++ .max_preview_video_w = (max_video_width > 1920) ? ++ max_video_width : 1920, ++ .max_preview_video_h = (max_video_height > 1088) ? ++ max_video_height : 1088, ++ .num_preview_video_frames = 3, ++ .stills_capture_circular_buffer_height = 0, ++ .fast_preview_resume = 0, ++ .use_stc_timestamp = MMAL_PARAM_TIMESTAMP_MODE_RAW_STC ++ }; ++ ++ ret = vchiq_mmal_port_parameter_set(instance, &camera->control, ++ MMAL_PARAMETER_CAMERA_CONFIG, ++ &cam_config, sizeof(cam_config)); ++ return ret; ++} ++ ++/* MMAL instance and component init */ ++static int __init mmal_init(struct bm2835_mmal_dev *dev) ++{ ++ int ret; ++ struct mmal_es_format *format; ++ u32 bool_true = 1; ++ ++ ret = vchiq_mmal_init(&dev->instance); ++ if (ret < 0) ++ return ret; ++ ++ /* get the camera component ready */ ++ ret = vchiq_mmal_component_init(dev->instance, "ril.camera", ++ &dev->component[MMAL_COMPONENT_CAMERA]); ++ if (ret < 0) ++ goto unreg_mmal; ++ ++ if (dev->component[MMAL_COMPONENT_CAMERA]->outputs < ++ MMAL_CAMERA_PORT_COUNT) { ++ ret = -EINVAL; ++ goto unreg_camera; ++ } ++ ++ ret = set_camera_parameters(dev->instance, ++ dev->component[MMAL_COMPONENT_CAMERA]); ++ if (ret < 0) ++ goto unreg_camera; ++ ++ format = ++ &dev->component[MMAL_COMPONENT_CAMERA]-> ++ output[MMAL_CAMERA_PORT_PREVIEW].format; ++ ++ format->encoding = MMAL_ENCODING_OPAQUE; ++ format->encoding_variant = MMAL_ENCODING_I420; ++ ++ format->es->video.width = 1024; ++ format->es->video.height = 768; ++ format->es->video.crop.x = 0; ++ format->es->video.crop.y = 0; ++ format->es->video.crop.width = 1024; ++ format->es->video.crop.height = 768; ++ format->es->video.frame_rate.num = 0; /* Rely on fps_range */ ++ format->es->video.frame_rate.den = 1; ++ ++ format = ++ &dev->component[MMAL_COMPONENT_CAMERA]-> ++ output[MMAL_CAMERA_PORT_VIDEO].format; ++ ++ format->encoding = MMAL_ENCODING_OPAQUE; ++ format->encoding_variant = MMAL_ENCODING_I420; ++ ++ format->es->video.width = 1024; ++ format->es->video.height = 768; ++ format->es->video.crop.x = 0; ++ format->es->video.crop.y = 0; ++ format->es->video.crop.width = 1024; ++ format->es->video.crop.height = 768; ++ format->es->video.frame_rate.num = 0; /* Rely on fps_range */ ++ format->es->video.frame_rate.den = 1; ++ ++ vchiq_mmal_port_parameter_set(dev->instance, ++ &dev->component[MMAL_COMPONENT_CAMERA]-> ++ output[MMAL_CAMERA_PORT_VIDEO], ++ MMAL_PARAMETER_NO_IMAGE_PADDING, ++ &bool_true, sizeof(bool_true)); ++ ++ format = ++ &dev->component[MMAL_COMPONENT_CAMERA]-> ++ output[MMAL_CAMERA_PORT_CAPTURE].format; ++ ++ format->encoding = MMAL_ENCODING_OPAQUE; ++ ++ format->es->video.width = 2592; ++ format->es->video.height = 1944; ++ format->es->video.crop.x = 0; ++ format->es->video.crop.y = 0; ++ format->es->video.crop.width = 2592; ++ format->es->video.crop.height = 1944; ++ format->es->video.frame_rate.num = 0; /* Rely on fps_range */ ++ format->es->video.frame_rate.den = 1; ++ ++ dev->capture.width = format->es->video.width; ++ dev->capture.height = format->es->video.height; ++ dev->capture.fmt = &formats[0]; ++ dev->capture.encode_component = NULL; ++ dev->capture.timeperframe = tpf_default; ++ dev->capture.enc_profile = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH; ++ dev->capture.enc_level = V4L2_MPEG_VIDEO_H264_LEVEL_4_0; ++ ++ vchiq_mmal_port_parameter_set(dev->instance, ++ &dev->component[MMAL_COMPONENT_CAMERA]-> ++ output[MMAL_CAMERA_PORT_CAPTURE], ++ MMAL_PARAMETER_NO_IMAGE_PADDING, ++ &bool_true, sizeof(bool_true)); ++ ++ /* get the preview component ready */ ++ ret = vchiq_mmal_component_init( ++ dev->instance, "ril.video_render", ++ &dev->component[MMAL_COMPONENT_PREVIEW]); ++ if (ret < 0) ++ goto unreg_camera; ++ ++ if (dev->component[MMAL_COMPONENT_PREVIEW]->inputs < 1) { ++ ret = -EINVAL; ++ pr_debug("too few input ports %d needed %d\n", ++ dev->component[MMAL_COMPONENT_PREVIEW]->inputs, 1); ++ goto unreg_preview; ++ } ++ ++ /* get the image encoder component ready */ ++ ret = vchiq_mmal_component_init( ++ dev->instance, "ril.image_encode", ++ &dev->component[MMAL_COMPONENT_IMAGE_ENCODE]); ++ if (ret < 0) ++ goto unreg_preview; ++ ++ if (dev->component[MMAL_COMPONENT_IMAGE_ENCODE]->inputs < 1) { ++ ret = -EINVAL; ++ v4l2_err(&dev->v4l2_dev, "too few input ports %d needed %d\n", ++ dev->component[MMAL_COMPONENT_IMAGE_ENCODE]->inputs, ++ 1); ++ goto unreg_image_encoder; ++ } ++ ++ /* get the video encoder component ready */ ++ ret = vchiq_mmal_component_init(dev->instance, "ril.video_encode", ++ &dev-> ++ component[MMAL_COMPONENT_VIDEO_ENCODE]); ++ if (ret < 0) ++ goto unreg_image_encoder; ++ ++ if (dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->inputs < 1) { ++ ret = -EINVAL; ++ v4l2_err(&dev->v4l2_dev, "too few input ports %d needed %d\n", ++ dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->inputs, ++ 1); ++ goto unreg_vid_encoder; ++ } ++ ++ { ++ struct vchiq_mmal_port *encoder_port = ++ &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0]; ++ encoder_port->format.encoding = MMAL_ENCODING_H264; ++ ret = vchiq_mmal_port_set_format(dev->instance, ++ encoder_port); ++ } ++ ++ { ++ unsigned int enable = 1; ++ vchiq_mmal_port_parameter_set( ++ dev->instance, ++ &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->control, ++ MMAL_PARAMETER_VIDEO_IMMUTABLE_INPUT, ++ &enable, sizeof(enable)); ++ ++ vchiq_mmal_port_parameter_set(dev->instance, ++ &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->control, ++ MMAL_PARAMETER_MINIMISE_FRAGMENTATION, ++ &enable, ++ sizeof(enable)); ++ } ++ ret = bm2835_mmal_set_all_camera_controls(dev); ++ if (ret < 0) ++ goto unreg_vid_encoder; ++ ++ return 0; ++ ++unreg_vid_encoder: ++ pr_err("Cleanup: Destroy video encoder\n"); ++ vchiq_mmal_component_finalise( ++ dev->instance, ++ dev->component[MMAL_COMPONENT_VIDEO_ENCODE]); ++ ++unreg_image_encoder: ++ pr_err("Cleanup: Destroy image encoder\n"); ++ vchiq_mmal_component_finalise( ++ dev->instance, ++ dev->component[MMAL_COMPONENT_IMAGE_ENCODE]); ++ ++unreg_preview: ++ pr_err("Cleanup: Destroy video render\n"); ++ vchiq_mmal_component_finalise(dev->instance, ++ dev->component[MMAL_COMPONENT_PREVIEW]); ++ ++unreg_camera: ++ pr_err("Cleanup: Destroy camera\n"); ++ vchiq_mmal_component_finalise(dev->instance, ++ dev->component[MMAL_COMPONENT_CAMERA]); ++ ++unreg_mmal: ++ vchiq_mmal_finalise(dev->instance); ++ return ret; ++} ++ ++static int __init bm2835_mmal_init_device(struct bm2835_mmal_dev *dev, ++ struct video_device *vfd) ++{ ++ int ret; ++ ++ *vfd = vdev_template; ++ if (gst_v4l2src_is_broken) { ++ v4l2_info(&dev->v4l2_dev, ++ "Work-around for gstreamer issue is active.\n"); ++ vfd->ioctl_ops = &camera0_ioctl_ops_gstreamer; ++ } ++ ++ vfd->v4l2_dev = &dev->v4l2_dev; ++ ++ vfd->lock = &dev->mutex; ++ ++ vfd->queue = &dev->capture.vb_vidq; ++ ++ /* video device needs to be able to access instance data */ ++ video_set_drvdata(vfd, dev); ++ ++ ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1); ++ if (ret < 0) ++ return ret; ++ ++ v4l2_info(vfd->v4l2_dev, ++ "V4L2 device registered as %s - stills mode > %dx%d\n", ++ video_device_node_name(vfd), max_video_width, max_video_height); ++ ++ return 0; ++} ++ ++static struct v4l2_format default_v4l2_format = { ++ .fmt.pix.pixelformat = V4L2_PIX_FMT_JPEG, ++ .fmt.pix.width = 1024, ++ .fmt.pix.bytesperline = 1024, ++ .fmt.pix.height = 768, ++ .fmt.pix.sizeimage = 1024*768, ++}; ++ ++static int __init bm2835_mmal_init(void) ++{ ++ int ret; ++ struct bm2835_mmal_dev *dev; ++ struct vb2_queue *q; ++ ++ dev = kzalloc(sizeof(*gdev), GFP_KERNEL); ++ if (!dev) ++ return -ENOMEM; ++ ++ /* setup device defaults */ ++ dev->overlay.w.left = 150; ++ dev->overlay.w.top = 50; ++ dev->overlay.w.width = 1024; ++ dev->overlay.w.height = 768; ++ dev->overlay.clipcount = 0; ++ dev->overlay.field = V4L2_FIELD_NONE; ++ ++ dev->capture.fmt = &formats[3]; /* JPEG */ ++ ++ /* v4l device registration */ ++ snprintf(dev->v4l2_dev.name, sizeof(dev->v4l2_dev.name), ++ "%s", BM2835_MMAL_MODULE_NAME); ++ ret = v4l2_device_register(NULL, &dev->v4l2_dev); ++ if (ret) ++ goto free_dev; ++ ++ /* setup v4l controls */ ++ ret = bm2835_mmal_init_controls(dev, &dev->ctrl_handler); ++ if (ret < 0) ++ goto unreg_dev; ++ dev->v4l2_dev.ctrl_handler = &dev->ctrl_handler; ++ ++ /* mmal init */ ++ ret = mmal_init(dev); ++ if (ret < 0) ++ goto unreg_dev; ++ ++ /* initialize queue */ ++ q = &dev->capture.vb_vidq; ++ memset(q, 0, sizeof(*q)); ++ q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; ++ q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_READ; ++ q->drv_priv = dev; ++ q->buf_struct_size = sizeof(struct mmal_buffer); ++ q->ops = &bm2835_mmal_video_qops; ++ q->mem_ops = &vb2_vmalloc_memops; ++ q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; ++ ret = vb2_queue_init(q); ++ if (ret < 0) ++ goto unreg_dev; ++ ++ /* v4l2 core mutex used to protect all fops and v4l2 ioctls. */ ++ mutex_init(&dev->mutex); ++ ++ /* initialise video devices */ ++ ret = bm2835_mmal_init_device(dev, &dev->vdev); ++ if (ret < 0) ++ goto unreg_dev; ++ ++ /* Really want to call vidioc_s_fmt_vid_cap with the default ++ * format, but currently the APIs don't join up. ++ */ ++ ret = mmal_setup_components(dev, &default_v4l2_format); ++ if (ret < 0) { ++ v4l2_err(&dev->v4l2_dev, ++ "%s: could not setup components\n", __func__); ++ goto unreg_dev; ++ } ++ ++ v4l2_info(&dev->v4l2_dev, ++ "Broadcom 2835 MMAL video capture ver %s loaded.\n", ++ BM2835_MMAL_VERSION); ++ ++ gdev = dev; ++ return 0; ++ ++unreg_dev: ++ v4l2_ctrl_handler_free(&dev->ctrl_handler); ++ v4l2_device_unregister(&dev->v4l2_dev); ++ ++free_dev: ++ kfree(dev); ++ ++ v4l2_err(&dev->v4l2_dev, ++ "%s: error %d while loading driver\n", ++ BM2835_MMAL_MODULE_NAME, ret); ++ ++ return ret; ++} ++ ++static void __exit bm2835_mmal_exit(void) ++{ ++ if (!gdev) ++ return; ++ ++ v4l2_info(&gdev->v4l2_dev, "unregistering %s\n", ++ video_device_node_name(&gdev->vdev)); ++ ++ video_unregister_device(&gdev->vdev); ++ ++ if (gdev->capture.encode_component) { ++ v4l2_dbg(1, bcm2835_v4l2_debug, &gdev->v4l2_dev, ++ "mmal_exit - disconnect tunnel\n"); ++ vchiq_mmal_port_connect_tunnel(gdev->instance, ++ gdev->capture.camera_port, NULL); ++ vchiq_mmal_component_disable(gdev->instance, ++ gdev->capture.encode_component); ++ } ++ vchiq_mmal_component_disable(gdev->instance, ++ gdev->component[MMAL_COMPONENT_CAMERA]); ++ ++ vchiq_mmal_component_finalise(gdev->instance, ++ gdev-> ++ component[MMAL_COMPONENT_VIDEO_ENCODE]); ++ ++ vchiq_mmal_component_finalise(gdev->instance, ++ gdev-> ++ component[MMAL_COMPONENT_IMAGE_ENCODE]); ++ ++ vchiq_mmal_component_finalise(gdev->instance, ++ gdev->component[MMAL_COMPONENT_PREVIEW]); ++ ++ vchiq_mmal_component_finalise(gdev->instance, ++ gdev->component[MMAL_COMPONENT_CAMERA]); ++ ++ vchiq_mmal_finalise(gdev->instance); ++ ++ v4l2_ctrl_handler_free(&gdev->ctrl_handler); ++ ++ v4l2_device_unregister(&gdev->v4l2_dev); ++ ++ kfree(gdev); ++} ++ ++module_init(bm2835_mmal_init); ++module_exit(bm2835_mmal_exit); +diff -Nur linux-4.1.13.orig/drivers/media/platform/bcm2835/bcm2835-camera.h linux-rpi/drivers/media/platform/bcm2835/bcm2835-camera.h +--- linux-4.1.13.orig/drivers/media/platform/bcm2835/bcm2835-camera.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/media/platform/bcm2835/bcm2835-camera.h 2015-11-29 09:42:37.835237156 +0100 +@@ -0,0 +1,126 @@ ++/* ++ * Broadcom BM2835 V4L2 driver ++ * ++ * Copyright © 2013 Raspberry Pi (Trading) Ltd. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ * ++ * Authors: Vincent Sanders ++ * Dave Stevenson ++ * Simon Mellor ++ * Luke Diamand ++ * ++ * core driver device ++ */ ++ ++#define V4L2_CTRL_COUNT 28 /* number of v4l controls */ ++ ++enum { ++ MMAL_COMPONENT_CAMERA = 0, ++ MMAL_COMPONENT_PREVIEW, ++ MMAL_COMPONENT_IMAGE_ENCODE, ++ MMAL_COMPONENT_VIDEO_ENCODE, ++ MMAL_COMPONENT_COUNT ++}; ++ ++enum { ++ MMAL_CAMERA_PORT_PREVIEW = 0, ++ MMAL_CAMERA_PORT_VIDEO, ++ MMAL_CAMERA_PORT_CAPTURE, ++ MMAL_CAMERA_PORT_COUNT ++}; ++ ++#define PREVIEW_LAYER 2 ++ ++extern int bcm2835_v4l2_debug; ++ ++struct bm2835_mmal_dev { ++ /* v4l2 devices */ ++ struct v4l2_device v4l2_dev; ++ struct video_device vdev; ++ struct mutex mutex; ++ ++ /* controls */ ++ struct v4l2_ctrl_handler ctrl_handler; ++ struct v4l2_ctrl *ctrls[V4L2_CTRL_COUNT]; ++ enum v4l2_scene_mode scene_mode; ++ struct mmal_colourfx colourfx; ++ int hflip; ++ int vflip; ++ int red_gain; ++ int blue_gain; ++ enum mmal_parameter_exposuremode exposure_mode_user; ++ enum v4l2_exposure_auto_type exposure_mode_v4l2_user; ++ /* active exposure mode may differ if selected via a scene mode */ ++ enum mmal_parameter_exposuremode exposure_mode_active; ++ enum mmal_parameter_exposuremeteringmode metering_mode; ++ unsigned int manual_shutter_speed; ++ bool exp_auto_priority; ++ ++ /* allocated mmal instance and components */ ++ struct vchiq_mmal_instance *instance; ++ struct vchiq_mmal_component *component[MMAL_COMPONENT_COUNT]; ++ int camera_use_count; ++ ++ struct v4l2_window overlay; ++ ++ struct { ++ unsigned int width; /* width */ ++ unsigned int height; /* height */ ++ unsigned int stride; /* stride */ ++ unsigned int buffersize; /* buffer size with padding */ ++ struct mmal_fmt *fmt; ++ struct v4l2_fract timeperframe; ++ ++ /* H264 encode bitrate */ ++ int encode_bitrate; ++ /* H264 bitrate mode. CBR/VBR */ ++ int encode_bitrate_mode; ++ /* H264 profile */ ++ enum v4l2_mpeg_video_h264_profile enc_profile; ++ /* H264 level */ ++ enum v4l2_mpeg_video_h264_level enc_level; ++ /* JPEG Q-factor */ ++ int q_factor; ++ ++ struct vb2_queue vb_vidq; ++ ++ /* VC start timestamp for streaming */ ++ s64 vc_start_timestamp; ++ /* Kernel start timestamp for streaming */ ++ struct timeval kernel_start_ts; ++ ++ struct vchiq_mmal_port *port; /* port being used for capture */ ++ /* camera port being used for capture */ ++ struct vchiq_mmal_port *camera_port; ++ /* component being used for encode */ ++ struct vchiq_mmal_component *encode_component; ++ /* number of frames remaining which driver should capture */ ++ unsigned int frame_count; ++ /* last frame completion */ ++ struct completion frame_cmplt; ++ ++ } capture; ++ ++}; ++ ++int bm2835_mmal_init_controls( ++ struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl_handler *hdl); ++ ++int bm2835_mmal_set_all_camera_controls(struct bm2835_mmal_dev *dev); ++int set_framerate_params(struct bm2835_mmal_dev *dev); ++ ++/* Debug helpers */ ++ ++#define v4l2_dump_pix_format(level, debug, dev, pix_fmt, desc) \ ++{ \ ++ v4l2_dbg(level, debug, dev, \ ++"%s: w %u h %u field %u pfmt 0x%x bpl %u sz_img %u colorspace 0x%x priv %u\n", \ ++ desc == NULL ? "" : desc, \ ++ (pix_fmt)->width, (pix_fmt)->height, (pix_fmt)->field, \ ++ (pix_fmt)->pixelformat, (pix_fmt)->bytesperline, \ ++ (pix_fmt)->sizeimage, (pix_fmt)->colorspace, (pix_fmt)->priv); \ ++} +diff -Nur linux-4.1.13.orig/drivers/media/platform/bcm2835/controls.c linux-rpi/drivers/media/platform/bcm2835/controls.c +--- linux-4.1.13.orig/drivers/media/platform/bcm2835/controls.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/media/platform/bcm2835/controls.c 2015-11-29 09:42:37.835237156 +0100 +@@ -0,0 +1,1324 @@ ++/* ++ * Broadcom BM2835 V4L2 driver ++ * ++ * Copyright © 2013 Raspberry Pi (Trading) Ltd. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ * ++ * Authors: Vincent Sanders ++ * Dave Stevenson ++ * Simon Mellor ++ * Luke Diamand ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mmal-common.h" ++#include "mmal-vchiq.h" ++#include "mmal-parameters.h" ++#include "bcm2835-camera.h" ++ ++/* The supported V4L2_CID_AUTO_EXPOSURE_BIAS values are from -4.0 to +4.0. ++ * MMAL values are in 1/6th increments so the MMAL range is -24 to +24. ++ * V4L2 docs say value "is expressed in terms of EV, drivers should interpret ++ * the values as 0.001 EV units, where the value 1000 stands for +1 EV." ++ * V4L2 is limited to a max of 32 values in a menu, so count in 1/3rds from ++ * -4 to +4 ++ */ ++static const s64 ev_bias_qmenu[] = { ++ -4000, -3667, -3333, ++ -3000, -2667, -2333, ++ -2000, -1667, -1333, ++ -1000, -667, -333, ++ 0, 333, 667, ++ 1000, 1333, 1667, ++ 2000, 2333, 2667, ++ 3000, 3333, 3667, ++ 4000 ++}; ++ ++/* Supported ISO values ++ * ISOO = auto ISO ++ */ ++static const s64 iso_qmenu[] = { ++ 0, 100, 200, 400, 800, ++}; ++ ++static const s64 mains_freq_qmenu[] = { ++ V4L2_CID_POWER_LINE_FREQUENCY_DISABLED, ++ V4L2_CID_POWER_LINE_FREQUENCY_50HZ, ++ V4L2_CID_POWER_LINE_FREQUENCY_60HZ, ++ V4L2_CID_POWER_LINE_FREQUENCY_AUTO ++}; ++ ++/* Supported video encode modes */ ++static const s64 bitrate_mode_qmenu[] = { ++ (s64)V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, ++ (s64)V4L2_MPEG_VIDEO_BITRATE_MODE_CBR, ++}; ++ ++enum bm2835_mmal_ctrl_type { ++ MMAL_CONTROL_TYPE_STD, ++ MMAL_CONTROL_TYPE_STD_MENU, ++ MMAL_CONTROL_TYPE_INT_MENU, ++ MMAL_CONTROL_TYPE_CLUSTER, /* special cluster entry */ ++}; ++ ++struct bm2835_mmal_v4l2_ctrl; ++ ++typedef int(bm2835_mmal_v4l2_ctrl_cb)( ++ struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl); ++ ++struct bm2835_mmal_v4l2_ctrl { ++ u32 id; /* v4l2 control identifier */ ++ enum bm2835_mmal_ctrl_type type; ++ /* control minimum value or ++ * mask for MMAL_CONTROL_TYPE_STD_MENU */ ++ s32 min; ++ s32 max; /* maximum value of control */ ++ s32 def; /* default value of control */ ++ s32 step; /* step size of the control */ ++ const s64 *imenu; /* integer menu array */ ++ u32 mmal_id; /* mmal parameter id */ ++ bm2835_mmal_v4l2_ctrl_cb *setter; ++ bool ignore_errors; ++}; ++ ++struct v4l2_to_mmal_effects_setting { ++ u32 v4l2_effect; ++ u32 mmal_effect; ++ s32 col_fx_enable; ++ s32 col_fx_fixed_cbcr; ++ u32 u; ++ u32 v; ++ u32 num_effect_params; ++ u32 effect_params[MMAL_MAX_IMAGEFX_PARAMETERS]; ++}; ++ ++static const struct v4l2_to_mmal_effects_setting ++ v4l2_to_mmal_effects_values[] = { ++ { V4L2_COLORFX_NONE, MMAL_PARAM_IMAGEFX_NONE, ++ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} }, ++ { V4L2_COLORFX_BW, MMAL_PARAM_IMAGEFX_NONE, ++ 1, 0, 128, 128, 0, {0, 0, 0, 0, 0} }, ++ { V4L2_COLORFX_SEPIA, MMAL_PARAM_IMAGEFX_NONE, ++ 1, 0, 87, 151, 0, {0, 0, 0, 0, 0} }, ++ { V4L2_COLORFX_NEGATIVE, MMAL_PARAM_IMAGEFX_NEGATIVE, ++ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} }, ++ { V4L2_COLORFX_EMBOSS, MMAL_PARAM_IMAGEFX_EMBOSS, ++ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} }, ++ { V4L2_COLORFX_SKETCH, MMAL_PARAM_IMAGEFX_SKETCH, ++ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} }, ++ { V4L2_COLORFX_SKY_BLUE, MMAL_PARAM_IMAGEFX_PASTEL, ++ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} }, ++ { V4L2_COLORFX_GRASS_GREEN, MMAL_PARAM_IMAGEFX_WATERCOLOUR, ++ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} }, ++ { V4L2_COLORFX_SKIN_WHITEN, MMAL_PARAM_IMAGEFX_WASHEDOUT, ++ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} }, ++ { V4L2_COLORFX_VIVID, MMAL_PARAM_IMAGEFX_SATURATION, ++ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} }, ++ { V4L2_COLORFX_AQUA, MMAL_PARAM_IMAGEFX_NONE, ++ 1, 0, 171, 121, 0, {0, 0, 0, 0, 0} }, ++ { V4L2_COLORFX_ART_FREEZE, MMAL_PARAM_IMAGEFX_HATCH, ++ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} }, ++ { V4L2_COLORFX_SILHOUETTE, MMAL_PARAM_IMAGEFX_FILM, ++ 0, 0, 0, 0, 0, {0, 0, 0, 0, 0} }, ++ { V4L2_COLORFX_SOLARIZATION, MMAL_PARAM_IMAGEFX_SOLARIZE, ++ 0, 0, 0, 0, 5, {1, 128, 160, 160, 48} }, ++ { V4L2_COLORFX_ANTIQUE, MMAL_PARAM_IMAGEFX_COLOURBALANCE, ++ 0, 0, 0, 0, 3, {108, 274, 238, 0, 0} }, ++ { V4L2_COLORFX_SET_CBCR, MMAL_PARAM_IMAGEFX_NONE, ++ 1, 1, 0, 0, 0, {0, 0, 0, 0, 0} } ++}; ++ ++struct v4l2_mmal_scene_config { ++ enum v4l2_scene_mode v4l2_scene; ++ enum mmal_parameter_exposuremode exposure_mode; ++ enum mmal_parameter_exposuremeteringmode metering_mode; ++}; ++ ++static const struct v4l2_mmal_scene_config scene_configs[] = { ++ /* V4L2_SCENE_MODE_NONE automatically added */ ++ { ++ V4L2_SCENE_MODE_NIGHT, ++ MMAL_PARAM_EXPOSUREMODE_NIGHT, ++ MMAL_PARAM_EXPOSUREMETERINGMODE_AVERAGE ++ }, ++ { ++ V4L2_SCENE_MODE_SPORTS, ++ MMAL_PARAM_EXPOSUREMODE_SPORTS, ++ MMAL_PARAM_EXPOSUREMETERINGMODE_AVERAGE ++ }, ++}; ++ ++/* control handlers*/ ++ ++static int ctrl_set_rational(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ struct mmal_parameter_rational rational_value; ++ struct vchiq_mmal_port *control; ++ ++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; ++ ++ rational_value.num = ctrl->val; ++ rational_value.den = 100; ++ ++ return vchiq_mmal_port_parameter_set(dev->instance, control, ++ mmal_ctrl->mmal_id, ++ &rational_value, ++ sizeof(rational_value)); ++} ++ ++static int ctrl_set_value(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ u32 u32_value; ++ struct vchiq_mmal_port *control; ++ ++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; ++ ++ u32_value = ctrl->val; ++ ++ return vchiq_mmal_port_parameter_set(dev->instance, control, ++ mmal_ctrl->mmal_id, ++ &u32_value, sizeof(u32_value)); ++} ++ ++static int ctrl_set_value_menu(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ u32 u32_value; ++ struct vchiq_mmal_port *control; ++ ++ if (ctrl->val > mmal_ctrl->max || ctrl->val < mmal_ctrl->min) ++ return 1; ++ ++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; ++ ++ u32_value = mmal_ctrl->imenu[ctrl->val]; ++ ++ return vchiq_mmal_port_parameter_set(dev->instance, control, ++ mmal_ctrl->mmal_id, ++ &u32_value, sizeof(u32_value)); ++} ++ ++static int ctrl_set_value_ev(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ s32 s32_value; ++ struct vchiq_mmal_port *control; ++ ++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; ++ ++ s32_value = (ctrl->val-12)*2; /* Convert from index to 1/6ths */ ++ ++ return vchiq_mmal_port_parameter_set(dev->instance, control, ++ mmal_ctrl->mmal_id, ++ &s32_value, sizeof(s32_value)); ++} ++ ++static int ctrl_set_rotate(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ int ret; ++ u32 u32_value; ++ struct vchiq_mmal_component *camera; ++ ++ camera = dev->component[MMAL_COMPONENT_CAMERA]; ++ ++ u32_value = ((ctrl->val % 360) / 90) * 90; ++ ++ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[0], ++ mmal_ctrl->mmal_id, ++ &u32_value, sizeof(u32_value)); ++ if (ret < 0) ++ return ret; ++ ++ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[1], ++ mmal_ctrl->mmal_id, ++ &u32_value, sizeof(u32_value)); ++ if (ret < 0) ++ return ret; ++ ++ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[2], ++ mmal_ctrl->mmal_id, ++ &u32_value, sizeof(u32_value)); ++ ++ return ret; ++} ++ ++static int ctrl_set_flip(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ int ret; ++ u32 u32_value; ++ struct vchiq_mmal_component *camera; ++ ++ if (ctrl->id == V4L2_CID_HFLIP) ++ dev->hflip = ctrl->val; ++ else ++ dev->vflip = ctrl->val; ++ ++ camera = dev->component[MMAL_COMPONENT_CAMERA]; ++ ++ if (dev->hflip && dev->vflip) ++ u32_value = MMAL_PARAM_MIRROR_BOTH; ++ else if (dev->hflip) ++ u32_value = MMAL_PARAM_MIRROR_HORIZONTAL; ++ else if (dev->vflip) ++ u32_value = MMAL_PARAM_MIRROR_VERTICAL; ++ else ++ u32_value = MMAL_PARAM_MIRROR_NONE; ++ ++ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[0], ++ mmal_ctrl->mmal_id, ++ &u32_value, sizeof(u32_value)); ++ if (ret < 0) ++ return ret; ++ ++ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[1], ++ mmal_ctrl->mmal_id, ++ &u32_value, sizeof(u32_value)); ++ if (ret < 0) ++ return ret; ++ ++ ret = vchiq_mmal_port_parameter_set(dev->instance, &camera->output[2], ++ mmal_ctrl->mmal_id, ++ &u32_value, sizeof(u32_value)); ++ ++ return ret; ++ ++} ++ ++static int ctrl_set_exposure(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ enum mmal_parameter_exposuremode exp_mode = dev->exposure_mode_user; ++ u32 shutter_speed = 0; ++ struct vchiq_mmal_port *control; ++ int ret = 0; ++ ++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; ++ ++ if (mmal_ctrl->mmal_id == MMAL_PARAMETER_SHUTTER_SPEED) { ++ /* V4L2 is in 100usec increments. ++ * MMAL is 1usec. ++ */ ++ dev->manual_shutter_speed = ctrl->val * 100; ++ } else if (mmal_ctrl->mmal_id == MMAL_PARAMETER_EXPOSURE_MODE) { ++ switch (ctrl->val) { ++ case V4L2_EXPOSURE_AUTO: ++ exp_mode = MMAL_PARAM_EXPOSUREMODE_AUTO; ++ break; ++ ++ case V4L2_EXPOSURE_MANUAL: ++ exp_mode = MMAL_PARAM_EXPOSUREMODE_OFF; ++ break; ++ } ++ dev->exposure_mode_user = exp_mode; ++ dev->exposure_mode_v4l2_user = ctrl->val; ++ } else if (mmal_ctrl->id == V4L2_CID_EXPOSURE_AUTO_PRIORITY) { ++ dev->exp_auto_priority = ctrl->val; ++ } ++ ++ if (dev->scene_mode == V4L2_SCENE_MODE_NONE) { ++ if (exp_mode == MMAL_PARAM_EXPOSUREMODE_OFF) ++ shutter_speed = dev->manual_shutter_speed; ++ ++ ret = vchiq_mmal_port_parameter_set(dev->instance, ++ control, ++ MMAL_PARAMETER_SHUTTER_SPEED, ++ &shutter_speed, ++ sizeof(shutter_speed)); ++ ret += vchiq_mmal_port_parameter_set(dev->instance, ++ control, ++ MMAL_PARAMETER_EXPOSURE_MODE, ++ &exp_mode, ++ sizeof(u32)); ++ dev->exposure_mode_active = exp_mode; ++ } ++ /* exposure_dynamic_framerate (V4L2_CID_EXPOSURE_AUTO_PRIORITY) should ++ * always apply irrespective of scene mode. ++ */ ++ ret += set_framerate_params(dev); ++ ++ return ret; ++} ++ ++static int ctrl_set_metering_mode(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ switch (ctrl->val) { ++ case V4L2_EXPOSURE_METERING_AVERAGE: ++ dev->metering_mode = MMAL_PARAM_EXPOSUREMETERINGMODE_AVERAGE; ++ break; ++ ++ case V4L2_EXPOSURE_METERING_CENTER_WEIGHTED: ++ dev->metering_mode = MMAL_PARAM_EXPOSUREMETERINGMODE_BACKLIT; ++ break; ++ ++ case V4L2_EXPOSURE_METERING_SPOT: ++ dev->metering_mode = MMAL_PARAM_EXPOSUREMETERINGMODE_SPOT; ++ break; ++ ++ /* todo matrix weighting not added to Linux API till 3.9 ++ case V4L2_EXPOSURE_METERING_MATRIX: ++ dev->metering_mode = MMAL_PARAM_EXPOSUREMETERINGMODE_MATRIX; ++ break; ++ */ ++ ++ } ++ ++ if (dev->scene_mode == V4L2_SCENE_MODE_NONE) { ++ struct vchiq_mmal_port *control; ++ u32 u32_value = dev->metering_mode; ++ ++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; ++ ++ return vchiq_mmal_port_parameter_set(dev->instance, control, ++ mmal_ctrl->mmal_id, ++ &u32_value, sizeof(u32_value)); ++ } else ++ return 0; ++} ++ ++static int ctrl_set_flicker_avoidance(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ u32 u32_value; ++ struct vchiq_mmal_port *control; ++ ++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; ++ ++ switch (ctrl->val) { ++ case V4L2_CID_POWER_LINE_FREQUENCY_DISABLED: ++ u32_value = MMAL_PARAM_FLICKERAVOID_OFF; ++ break; ++ case V4L2_CID_POWER_LINE_FREQUENCY_50HZ: ++ u32_value = MMAL_PARAM_FLICKERAVOID_50HZ; ++ break; ++ case V4L2_CID_POWER_LINE_FREQUENCY_60HZ: ++ u32_value = MMAL_PARAM_FLICKERAVOID_60HZ; ++ break; ++ case V4L2_CID_POWER_LINE_FREQUENCY_AUTO: ++ u32_value = MMAL_PARAM_FLICKERAVOID_AUTO; ++ break; ++ } ++ ++ return vchiq_mmal_port_parameter_set(dev->instance, control, ++ mmal_ctrl->mmal_id, ++ &u32_value, sizeof(u32_value)); ++} ++ ++static int ctrl_set_awb_mode(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ u32 u32_value; ++ struct vchiq_mmal_port *control; ++ ++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; ++ ++ switch (ctrl->val) { ++ case V4L2_WHITE_BALANCE_MANUAL: ++ u32_value = MMAL_PARAM_AWBMODE_OFF; ++ break; ++ ++ case V4L2_WHITE_BALANCE_AUTO: ++ u32_value = MMAL_PARAM_AWBMODE_AUTO; ++ break; ++ ++ case V4L2_WHITE_BALANCE_INCANDESCENT: ++ u32_value = MMAL_PARAM_AWBMODE_INCANDESCENT; ++ break; ++ ++ case V4L2_WHITE_BALANCE_FLUORESCENT: ++ u32_value = MMAL_PARAM_AWBMODE_FLUORESCENT; ++ break; ++ ++ case V4L2_WHITE_BALANCE_FLUORESCENT_H: ++ u32_value = MMAL_PARAM_AWBMODE_TUNGSTEN; ++ break; ++ ++ case V4L2_WHITE_BALANCE_HORIZON: ++ u32_value = MMAL_PARAM_AWBMODE_HORIZON; ++ break; ++ ++ case V4L2_WHITE_BALANCE_DAYLIGHT: ++ u32_value = MMAL_PARAM_AWBMODE_SUNLIGHT; ++ break; ++ ++ case V4L2_WHITE_BALANCE_FLASH: ++ u32_value = MMAL_PARAM_AWBMODE_FLASH; ++ break; ++ ++ case V4L2_WHITE_BALANCE_CLOUDY: ++ u32_value = MMAL_PARAM_AWBMODE_CLOUDY; ++ break; ++ ++ case V4L2_WHITE_BALANCE_SHADE: ++ u32_value = MMAL_PARAM_AWBMODE_SHADE; ++ break; ++ ++ } ++ ++ return vchiq_mmal_port_parameter_set(dev->instance, control, ++ mmal_ctrl->mmal_id, ++ &u32_value, sizeof(u32_value)); ++} ++ ++static int ctrl_set_awb_gains(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ struct vchiq_mmal_port *control; ++ struct mmal_parameter_awbgains gains; ++ ++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; ++ ++ if (ctrl->id == V4L2_CID_RED_BALANCE) ++ dev->red_gain = ctrl->val; ++ else if (ctrl->id == V4L2_CID_BLUE_BALANCE) ++ dev->blue_gain = ctrl->val; ++ ++ gains.r_gain.num = dev->red_gain; ++ gains.b_gain.num = dev->blue_gain; ++ gains.r_gain.den = gains.b_gain.den = 1000; ++ ++ return vchiq_mmal_port_parameter_set(dev->instance, control, ++ mmal_ctrl->mmal_id, ++ &gains, sizeof(gains)); ++} ++ ++static int ctrl_set_image_effect(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ int ret = -EINVAL; ++ int i, j; ++ struct vchiq_mmal_port *control; ++ struct mmal_parameter_imagefx_parameters imagefx; ++ ++ for (i = 0; i < ARRAY_SIZE(v4l2_to_mmal_effects_values); i++) { ++ if (ctrl->val == v4l2_to_mmal_effects_values[i].v4l2_effect) { ++ ++ imagefx.effect = ++ v4l2_to_mmal_effects_values[i].mmal_effect; ++ imagefx.num_effect_params = ++ v4l2_to_mmal_effects_values[i].num_effect_params; ++ ++ if (imagefx.num_effect_params > MMAL_MAX_IMAGEFX_PARAMETERS) ++ imagefx.num_effect_params = MMAL_MAX_IMAGEFX_PARAMETERS; ++ ++ for (j = 0; j < imagefx.num_effect_params; j++) ++ imagefx.effect_parameter[j] = ++ v4l2_to_mmal_effects_values[i].effect_params[j]; ++ ++ dev->colourfx.enable = ++ v4l2_to_mmal_effects_values[i].col_fx_enable; ++ if (!v4l2_to_mmal_effects_values[i].col_fx_fixed_cbcr) { ++ dev->colourfx.u = ++ v4l2_to_mmal_effects_values[i].u; ++ dev->colourfx.v = ++ v4l2_to_mmal_effects_values[i].v; ++ } ++ ++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; ++ ++ ret = vchiq_mmal_port_parameter_set( ++ dev->instance, control, ++ MMAL_PARAMETER_IMAGE_EFFECT_PARAMETERS, ++ &imagefx, sizeof(imagefx)); ++ if (ret) ++ goto exit; ++ ++ ret = vchiq_mmal_port_parameter_set( ++ dev->instance, control, ++ MMAL_PARAMETER_COLOUR_EFFECT, ++ &dev->colourfx, sizeof(dev->colourfx)); ++ } ++ } ++ ++exit: ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "mmal_ctrl:%p ctrl id:0x%x ctrl val:%d imagefx:0x%x color_effect:%s u:%d v:%d ret %d(%d)\n", ++ mmal_ctrl, ctrl->id, ctrl->val, imagefx.effect, ++ dev->colourfx.enable ? "true" : "false", ++ dev->colourfx.u, dev->colourfx.v, ++ ret, (ret == 0 ? 0 : -EINVAL)); ++ return (ret == 0 ? 0 : EINVAL); ++} ++ ++static int ctrl_set_colfx(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ int ret = -EINVAL; ++ struct vchiq_mmal_port *control; ++ ++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; ++ ++ dev->colourfx.enable = (ctrl->val & 0xff00) >> 8; ++ dev->colourfx.enable = ctrl->val & 0xff; ++ ++ ret = vchiq_mmal_port_parameter_set(dev->instance, control, ++ MMAL_PARAMETER_COLOUR_EFFECT, ++ &dev->colourfx, sizeof(dev->colourfx)); ++ ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "%s: After: mmal_ctrl:%p ctrl id:0x%x ctrl val:%d ret %d(%d)\n", ++ __func__, mmal_ctrl, ctrl->id, ctrl->val, ret, ++ (ret == 0 ? 0 : -EINVAL)); ++ return (ret == 0 ? 0 : EINVAL); ++} ++ ++static int ctrl_set_bitrate(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ int ret; ++ struct vchiq_mmal_port *encoder_out; ++ ++ dev->capture.encode_bitrate = ctrl->val; ++ ++ encoder_out = &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0]; ++ ++ ret = vchiq_mmal_port_parameter_set(dev->instance, encoder_out, ++ mmal_ctrl->mmal_id, ++ &ctrl->val, sizeof(ctrl->val)); ++ ret = 0; ++ return ret; ++} ++ ++static int ctrl_set_bitrate_mode(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ u32 bitrate_mode; ++ struct vchiq_mmal_port *encoder_out; ++ ++ encoder_out = &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0]; ++ ++ dev->capture.encode_bitrate_mode = ctrl->val; ++ switch (ctrl->val) { ++ default: ++ case V4L2_MPEG_VIDEO_BITRATE_MODE_VBR: ++ bitrate_mode = MMAL_VIDEO_RATECONTROL_VARIABLE; ++ break; ++ case V4L2_MPEG_VIDEO_BITRATE_MODE_CBR: ++ bitrate_mode = MMAL_VIDEO_RATECONTROL_CONSTANT; ++ break; ++ } ++ ++ vchiq_mmal_port_parameter_set(dev->instance, encoder_out, ++ mmal_ctrl->mmal_id, ++ &bitrate_mode, ++ sizeof(bitrate_mode)); ++ return 0; ++} ++ ++static int ctrl_set_image_encode_output(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ u32 u32_value; ++ struct vchiq_mmal_port *jpeg_out; ++ ++ jpeg_out = &dev->component[MMAL_COMPONENT_IMAGE_ENCODE]->output[0]; ++ ++ u32_value = ctrl->val; ++ ++ return vchiq_mmal_port_parameter_set(dev->instance, jpeg_out, ++ mmal_ctrl->mmal_id, ++ &u32_value, sizeof(u32_value)); ++} ++ ++static int ctrl_set_video_encode_param_output(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ u32 u32_value; ++ struct vchiq_mmal_port *vid_enc_ctl; ++ ++ vid_enc_ctl = &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0]; ++ ++ u32_value = ctrl->val; ++ ++ return vchiq_mmal_port_parameter_set(dev->instance, vid_enc_ctl, ++ mmal_ctrl->mmal_id, ++ &u32_value, sizeof(u32_value)); ++} ++ ++static int ctrl_set_video_encode_profile_level(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ struct mmal_parameter_video_profile param; ++ int ret = 0; ++ ++ if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_PROFILE) { ++ switch (ctrl->val) { ++ case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE: ++ case V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE: ++ case V4L2_MPEG_VIDEO_H264_PROFILE_MAIN: ++ case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH: ++ dev->capture.enc_profile = ctrl->val; ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ } else if (ctrl->id == V4L2_CID_MPEG_VIDEO_H264_LEVEL) { ++ switch (ctrl->val) { ++ case V4L2_MPEG_VIDEO_H264_LEVEL_1_0: ++ case V4L2_MPEG_VIDEO_H264_LEVEL_1B: ++ case V4L2_MPEG_VIDEO_H264_LEVEL_1_1: ++ case V4L2_MPEG_VIDEO_H264_LEVEL_1_2: ++ case V4L2_MPEG_VIDEO_H264_LEVEL_1_3: ++ case V4L2_MPEG_VIDEO_H264_LEVEL_2_0: ++ case V4L2_MPEG_VIDEO_H264_LEVEL_2_1: ++ case V4L2_MPEG_VIDEO_H264_LEVEL_2_2: ++ case V4L2_MPEG_VIDEO_H264_LEVEL_3_0: ++ case V4L2_MPEG_VIDEO_H264_LEVEL_3_1: ++ case V4L2_MPEG_VIDEO_H264_LEVEL_3_2: ++ case V4L2_MPEG_VIDEO_H264_LEVEL_4_0: ++ dev->capture.enc_level = ctrl->val; ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ } ++ ++ if (!ret) { ++ switch (dev->capture.enc_profile) { ++ case V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE: ++ param.profile = MMAL_VIDEO_PROFILE_H264_BASELINE; ++ break; ++ case V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE: ++ param.profile = ++ MMAL_VIDEO_PROFILE_H264_CONSTRAINED_BASELINE; ++ break; ++ case V4L2_MPEG_VIDEO_H264_PROFILE_MAIN: ++ param.profile = MMAL_VIDEO_PROFILE_H264_MAIN; ++ break; ++ case V4L2_MPEG_VIDEO_H264_PROFILE_HIGH: ++ param.profile = MMAL_VIDEO_PROFILE_H264_HIGH; ++ break; ++ default: ++ /* Should never get here */ ++ break; ++ } ++ ++ switch (dev->capture.enc_level) { ++ case V4L2_MPEG_VIDEO_H264_LEVEL_1_0: ++ param.level = MMAL_VIDEO_LEVEL_H264_1; ++ break; ++ case V4L2_MPEG_VIDEO_H264_LEVEL_1B: ++ param.level = MMAL_VIDEO_LEVEL_H264_1b; ++ break; ++ case V4L2_MPEG_VIDEO_H264_LEVEL_1_1: ++ param.level = MMAL_VIDEO_LEVEL_H264_11; ++ break; ++ case V4L2_MPEG_VIDEO_H264_LEVEL_1_2: ++ param.level = MMAL_VIDEO_LEVEL_H264_12; ++ break; ++ case V4L2_MPEG_VIDEO_H264_LEVEL_1_3: ++ param.level = MMAL_VIDEO_LEVEL_H264_13; ++ break; ++ case V4L2_MPEG_VIDEO_H264_LEVEL_2_0: ++ param.level = MMAL_VIDEO_LEVEL_H264_2; ++ break; ++ case V4L2_MPEG_VIDEO_H264_LEVEL_2_1: ++ param.level = MMAL_VIDEO_LEVEL_H264_21; ++ break; ++ case V4L2_MPEG_VIDEO_H264_LEVEL_2_2: ++ param.level = MMAL_VIDEO_LEVEL_H264_22; ++ break; ++ case V4L2_MPEG_VIDEO_H264_LEVEL_3_0: ++ param.level = MMAL_VIDEO_LEVEL_H264_3; ++ break; ++ case V4L2_MPEG_VIDEO_H264_LEVEL_3_1: ++ param.level = MMAL_VIDEO_LEVEL_H264_31; ++ break; ++ case V4L2_MPEG_VIDEO_H264_LEVEL_3_2: ++ param.level = MMAL_VIDEO_LEVEL_H264_32; ++ break; ++ case V4L2_MPEG_VIDEO_H264_LEVEL_4_0: ++ param.level = MMAL_VIDEO_LEVEL_H264_4; ++ break; ++ default: ++ /* Should never get here */ ++ break; ++ } ++ ++ ret = vchiq_mmal_port_parameter_set(dev->instance, ++ &dev->component[MMAL_COMPONENT_VIDEO_ENCODE]->output[0], ++ mmal_ctrl->mmal_id, ++ ¶m, sizeof(param)); ++ } ++ return ret; ++} ++ ++static int ctrl_set_scene_mode(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl *ctrl, ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl) ++{ ++ int ret = 0; ++ int shutter_speed; ++ struct vchiq_mmal_port *control; ++ ++ v4l2_dbg(0, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "scene mode selected %d, was %d\n", ctrl->val, ++ dev->scene_mode); ++ control = &dev->component[MMAL_COMPONENT_CAMERA]->control; ++ ++ if (ctrl->val == dev->scene_mode) ++ return 0; ++ ++ if (ctrl->val == V4L2_SCENE_MODE_NONE) { ++ /* Restore all user selections */ ++ dev->scene_mode = V4L2_SCENE_MODE_NONE; ++ ++ if (dev->exposure_mode_user == MMAL_PARAM_EXPOSUREMODE_OFF) ++ shutter_speed = dev->manual_shutter_speed; ++ else ++ shutter_speed = 0; ++ ++ v4l2_dbg(0, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "%s: scene mode none: shut_speed %d, exp_mode %d, metering %d\n", ++ __func__, shutter_speed, dev->exposure_mode_user, ++ dev->metering_mode); ++ ret = vchiq_mmal_port_parameter_set(dev->instance, ++ control, ++ MMAL_PARAMETER_SHUTTER_SPEED, ++ &shutter_speed, ++ sizeof(shutter_speed)); ++ ret += vchiq_mmal_port_parameter_set(dev->instance, ++ control, ++ MMAL_PARAMETER_EXPOSURE_MODE, ++ &dev->exposure_mode_user, ++ sizeof(u32)); ++ dev->exposure_mode_active = dev->exposure_mode_user; ++ ret += vchiq_mmal_port_parameter_set(dev->instance, ++ control, ++ MMAL_PARAMETER_EXP_METERING_MODE, ++ &dev->metering_mode, ++ sizeof(u32)); ++ ret += set_framerate_params(dev); ++ } else { ++ /* Set up scene mode */ ++ int i; ++ const struct v4l2_mmal_scene_config *scene = NULL; ++ int shutter_speed; ++ enum mmal_parameter_exposuremode exposure_mode; ++ enum mmal_parameter_exposuremeteringmode metering_mode; ++ ++ for (i = 0; i < ARRAY_SIZE(scene_configs); i++) { ++ if (scene_configs[i].v4l2_scene == ++ ctrl->val) { ++ scene = &scene_configs[i]; ++ break; ++ } ++ } ++ if (!scene) ++ return -EINVAL; ++ if (i >= ARRAY_SIZE(scene_configs)) ++ return -EINVAL; ++ ++ /* Set all the values */ ++ dev->scene_mode = ctrl->val; ++ ++ if (scene->exposure_mode == MMAL_PARAM_EXPOSUREMODE_OFF) ++ shutter_speed = dev->manual_shutter_speed; ++ else ++ shutter_speed = 0; ++ exposure_mode = scene->exposure_mode; ++ metering_mode = scene->metering_mode; ++ ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "%s: scene mode none: shut_speed %d, exp_mode %d, metering %d\n", ++ __func__, shutter_speed, exposure_mode, metering_mode); ++ ++ ret = vchiq_mmal_port_parameter_set(dev->instance, control, ++ MMAL_PARAMETER_SHUTTER_SPEED, ++ &shutter_speed, ++ sizeof(shutter_speed)); ++ ret += vchiq_mmal_port_parameter_set(dev->instance, ++ control, ++ MMAL_PARAMETER_EXPOSURE_MODE, ++ &exposure_mode, ++ sizeof(u32)); ++ dev->exposure_mode_active = exposure_mode; ++ ret += vchiq_mmal_port_parameter_set(dev->instance, control, ++ MMAL_PARAMETER_EXPOSURE_MODE, ++ &exposure_mode, ++ sizeof(u32)); ++ ret += vchiq_mmal_port_parameter_set(dev->instance, control, ++ MMAL_PARAMETER_EXP_METERING_MODE, ++ &metering_mode, ++ sizeof(u32)); ++ ret += set_framerate_params(dev); ++ } ++ if (ret) { ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "%s: Setting scene to %d, ret=%d\n", ++ __func__, ctrl->val, ret); ++ ret = -EINVAL; ++ } ++ return 0; ++} ++ ++static int bm2835_mmal_s_ctrl(struct v4l2_ctrl *ctrl) ++{ ++ struct bm2835_mmal_dev *dev = ++ container_of(ctrl->handler, struct bm2835_mmal_dev, ++ ctrl_handler); ++ const struct bm2835_mmal_v4l2_ctrl *mmal_ctrl = ctrl->priv; ++ int ret; ++ ++ if ((mmal_ctrl == NULL) || ++ (mmal_ctrl->id != ctrl->id) || ++ (mmal_ctrl->setter == NULL)) { ++ pr_warn("mmal_ctrl:%p ctrl id:%d\n", mmal_ctrl, ctrl->id); ++ return -EINVAL; ++ } ++ ++ ret = mmal_ctrl->setter(dev, ctrl, mmal_ctrl); ++ if (ret) ++ pr_warn("ctrl id:%d/MMAL param %08X- returned ret %d\n", ++ ctrl->id, mmal_ctrl->mmal_id, ret); ++ if (mmal_ctrl->ignore_errors) ++ ret = 0; ++ return ret; ++} ++ ++static const struct v4l2_ctrl_ops bm2835_mmal_ctrl_ops = { ++ .s_ctrl = bm2835_mmal_s_ctrl, ++}; ++ ++ ++ ++static const struct bm2835_mmal_v4l2_ctrl v4l2_ctrls[V4L2_CTRL_COUNT] = { ++ { ++ V4L2_CID_SATURATION, MMAL_CONTROL_TYPE_STD, ++ -100, 100, 0, 1, NULL, ++ MMAL_PARAMETER_SATURATION, ++ &ctrl_set_rational, ++ false ++ }, ++ { ++ V4L2_CID_SHARPNESS, MMAL_CONTROL_TYPE_STD, ++ -100, 100, 0, 1, NULL, ++ MMAL_PARAMETER_SHARPNESS, ++ &ctrl_set_rational, ++ false ++ }, ++ { ++ V4L2_CID_CONTRAST, MMAL_CONTROL_TYPE_STD, ++ -100, 100, 0, 1, NULL, ++ MMAL_PARAMETER_CONTRAST, ++ &ctrl_set_rational, ++ false ++ }, ++ { ++ V4L2_CID_BRIGHTNESS, MMAL_CONTROL_TYPE_STD, ++ 0, 100, 50, 1, NULL, ++ MMAL_PARAMETER_BRIGHTNESS, ++ &ctrl_set_rational, ++ false ++ }, ++ { ++ V4L2_CID_ISO_SENSITIVITY, MMAL_CONTROL_TYPE_INT_MENU, ++ 0, ARRAY_SIZE(iso_qmenu) - 1, 0, 1, iso_qmenu, ++ MMAL_PARAMETER_ISO, ++ &ctrl_set_value_menu, ++ false ++ }, ++ { ++ V4L2_CID_IMAGE_STABILIZATION, MMAL_CONTROL_TYPE_STD, ++ 0, 1, 0, 1, NULL, ++ MMAL_PARAMETER_VIDEO_STABILISATION, ++ &ctrl_set_value, ++ false ++ }, ++/* { ++ 0, MMAL_CONTROL_TYPE_CLUSTER, 3, 1, 0, NULL, 0, NULL ++ }, */ ++ { ++ V4L2_CID_EXPOSURE_AUTO, MMAL_CONTROL_TYPE_STD_MENU, ++ ~0x03, 3, V4L2_EXPOSURE_AUTO, 0, NULL, ++ MMAL_PARAMETER_EXPOSURE_MODE, ++ &ctrl_set_exposure, ++ false ++ }, ++/* todo this needs mixing in with set exposure ++ { ++ V4L2_CID_SCENE_MODE, MMAL_CONTROL_TYPE_STD_MENU, ++ }, ++ */ ++ { ++ V4L2_CID_EXPOSURE_ABSOLUTE, MMAL_CONTROL_TYPE_STD, ++ /* Units of 100usecs */ ++ 1, 1*1000*10, 100*10, 1, NULL, ++ MMAL_PARAMETER_SHUTTER_SPEED, ++ &ctrl_set_exposure, ++ false ++ }, ++ { ++ V4L2_CID_AUTO_EXPOSURE_BIAS, MMAL_CONTROL_TYPE_INT_MENU, ++ 0, ARRAY_SIZE(ev_bias_qmenu) - 1, ++ (ARRAY_SIZE(ev_bias_qmenu)+1)/2 - 1, 0, ev_bias_qmenu, ++ MMAL_PARAMETER_EXPOSURE_COMP, ++ &ctrl_set_value_ev, ++ false ++ }, ++ { ++ V4L2_CID_EXPOSURE_AUTO_PRIORITY, MMAL_CONTROL_TYPE_STD, ++ 0, 1, ++ 0, 1, NULL, ++ 0, /* Dummy MMAL ID as it gets mapped into FPS range*/ ++ &ctrl_set_exposure, ++ false ++ }, ++ { ++ V4L2_CID_EXPOSURE_METERING, ++ MMAL_CONTROL_TYPE_STD_MENU, ++ ~0x7, 2, V4L2_EXPOSURE_METERING_AVERAGE, 0, NULL, ++ MMAL_PARAMETER_EXP_METERING_MODE, ++ &ctrl_set_metering_mode, ++ false ++ }, ++ { ++ V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE, ++ MMAL_CONTROL_TYPE_STD_MENU, ++ ~0x3ff, 9, V4L2_WHITE_BALANCE_AUTO, 0, NULL, ++ MMAL_PARAMETER_AWB_MODE, ++ &ctrl_set_awb_mode, ++ false ++ }, ++ { ++ V4L2_CID_RED_BALANCE, MMAL_CONTROL_TYPE_STD, ++ 1, 7999, 1000, 1, NULL, ++ MMAL_PARAMETER_CUSTOM_AWB_GAINS, ++ &ctrl_set_awb_gains, ++ false ++ }, ++ { ++ V4L2_CID_BLUE_BALANCE, MMAL_CONTROL_TYPE_STD, ++ 1, 7999, 1000, 1, NULL, ++ MMAL_PARAMETER_CUSTOM_AWB_GAINS, ++ &ctrl_set_awb_gains, ++ false ++ }, ++ { ++ V4L2_CID_COLORFX, MMAL_CONTROL_TYPE_STD_MENU, ++ 0, 15, V4L2_COLORFX_NONE, 0, NULL, ++ MMAL_PARAMETER_IMAGE_EFFECT, ++ &ctrl_set_image_effect, ++ false ++ }, ++ { ++ V4L2_CID_COLORFX_CBCR, MMAL_CONTROL_TYPE_STD, ++ 0, 0xffff, 0x8080, 1, NULL, ++ MMAL_PARAMETER_COLOUR_EFFECT, ++ &ctrl_set_colfx, ++ false ++ }, ++ { ++ V4L2_CID_ROTATE, MMAL_CONTROL_TYPE_STD, ++ 0, 360, 0, 90, NULL, ++ MMAL_PARAMETER_ROTATION, ++ &ctrl_set_rotate, ++ false ++ }, ++ { ++ V4L2_CID_HFLIP, MMAL_CONTROL_TYPE_STD, ++ 0, 1, 0, 1, NULL, ++ MMAL_PARAMETER_MIRROR, ++ &ctrl_set_flip, ++ false ++ }, ++ { ++ V4L2_CID_VFLIP, MMAL_CONTROL_TYPE_STD, ++ 0, 1, 0, 1, NULL, ++ MMAL_PARAMETER_MIRROR, ++ &ctrl_set_flip, ++ false ++ }, ++ { ++ V4L2_CID_MPEG_VIDEO_BITRATE_MODE, MMAL_CONTROL_TYPE_STD_MENU, ++ 0, ARRAY_SIZE(bitrate_mode_qmenu) - 1, ++ 0, 0, bitrate_mode_qmenu, ++ MMAL_PARAMETER_RATECONTROL, ++ &ctrl_set_bitrate_mode, ++ false ++ }, ++ { ++ V4L2_CID_MPEG_VIDEO_BITRATE, MMAL_CONTROL_TYPE_STD, ++ 25*1000, 25*1000*1000, 10*1000*1000, 25*1000, NULL, ++ MMAL_PARAMETER_VIDEO_BIT_RATE, ++ &ctrl_set_bitrate, ++ false ++ }, ++ { ++ V4L2_CID_JPEG_COMPRESSION_QUALITY, MMAL_CONTROL_TYPE_STD, ++ 1, 100, ++ 30, 1, NULL, ++ MMAL_PARAMETER_JPEG_Q_FACTOR, ++ &ctrl_set_image_encode_output, ++ false ++ }, ++ { ++ V4L2_CID_POWER_LINE_FREQUENCY, MMAL_CONTROL_TYPE_STD_MENU, ++ 0, ARRAY_SIZE(mains_freq_qmenu) - 1, ++ 1, 1, NULL, ++ MMAL_PARAMETER_FLICKER_AVOID, ++ &ctrl_set_flicker_avoidance, ++ false ++ }, ++ { ++ V4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER, MMAL_CONTROL_TYPE_STD, ++ 0, 1, ++ 0, 1, NULL, ++ MMAL_PARAMETER_VIDEO_ENCODE_INLINE_HEADER, ++ &ctrl_set_video_encode_param_output, ++ true /* Errors ignored as requires latest firmware to work */ ++ }, ++ { ++ V4L2_CID_MPEG_VIDEO_H264_PROFILE, ++ MMAL_CONTROL_TYPE_STD_MENU, ++ ~((1<ctrls[c]) && (v4l2_ctrls[c].setter)) { ++ ret = v4l2_ctrls[c].setter(dev, dev->ctrls[c], ++ &v4l2_ctrls[c]); ++ if (!v4l2_ctrls[c].ignore_errors && ret) { ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "Failed when setting default values for ctrl %d\n", ++ c); ++ break; ++ } ++ } ++ } ++ return ret; ++} ++ ++int set_framerate_params(struct bm2835_mmal_dev *dev) ++{ ++ struct mmal_parameter_fps_range fps_range; ++ int ret; ++ ++ if ((dev->exposure_mode_active != MMAL_PARAM_EXPOSUREMODE_OFF) && ++ (dev->exp_auto_priority)) { ++ /* Variable FPS. Define min FPS as 1fps. ++ * Max as max defined FPS. ++ */ ++ fps_range.fps_low.num = 1; ++ fps_range.fps_low.den = 1; ++ fps_range.fps_high.num = dev->capture.timeperframe.denominator; ++ fps_range.fps_high.den = dev->capture.timeperframe.numerator; ++ } else { ++ /* Fixed FPS - set min and max to be the same */ ++ fps_range.fps_low.num = fps_range.fps_high.num = ++ dev->capture.timeperframe.denominator; ++ fps_range.fps_low.den = fps_range.fps_high.den = ++ dev->capture.timeperframe.numerator; ++ } ++ ++ v4l2_dbg(1, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "Set fps range to %d/%d to %d/%d\n", ++ fps_range.fps_low.num, ++ fps_range.fps_low.den, ++ fps_range.fps_high.num, ++ fps_range.fps_high.den ++ ); ++ ++ ret = vchiq_mmal_port_parameter_set(dev->instance, ++ &dev->component[MMAL_COMPONENT_CAMERA]-> ++ output[MMAL_CAMERA_PORT_PREVIEW], ++ MMAL_PARAMETER_FPS_RANGE, ++ &fps_range, sizeof(fps_range)); ++ ret += vchiq_mmal_port_parameter_set(dev->instance, ++ &dev->component[MMAL_COMPONENT_CAMERA]-> ++ output[MMAL_CAMERA_PORT_VIDEO], ++ MMAL_PARAMETER_FPS_RANGE, ++ &fps_range, sizeof(fps_range)); ++ ret += vchiq_mmal_port_parameter_set(dev->instance, ++ &dev->component[MMAL_COMPONENT_CAMERA]-> ++ output[MMAL_CAMERA_PORT_CAPTURE], ++ MMAL_PARAMETER_FPS_RANGE, ++ &fps_range, sizeof(fps_range)); ++ if (ret) ++ v4l2_dbg(0, bcm2835_v4l2_debug, &dev->v4l2_dev, ++ "Failed to set fps ret %d\n", ++ ret); ++ ++ return ret; ++ ++} ++ ++int bm2835_mmal_init_controls(struct bm2835_mmal_dev *dev, ++ struct v4l2_ctrl_handler *hdl) ++{ ++ int c; ++ const struct bm2835_mmal_v4l2_ctrl *ctrl; ++ ++ v4l2_ctrl_handler_init(hdl, V4L2_CTRL_COUNT); ++ ++ for (c = 0; c < V4L2_CTRL_COUNT; c++) { ++ ctrl = &v4l2_ctrls[c]; ++ ++ switch (ctrl->type) { ++ case MMAL_CONTROL_TYPE_STD: ++ dev->ctrls[c] = v4l2_ctrl_new_std(hdl, ++ &bm2835_mmal_ctrl_ops, ctrl->id, ++ ctrl->min, ctrl->max, ctrl->step, ctrl->def); ++ break; ++ ++ case MMAL_CONTROL_TYPE_STD_MENU: ++ { ++ int mask = ctrl->min; ++ ++ if (ctrl->id == V4L2_CID_SCENE_MODE) { ++ /* Special handling to work out the mask ++ * value based on the scene_configs array ++ * at runtime. Reduces the chance of ++ * mismatches. ++ */ ++ int i; ++ mask = 1<ctrls[c] = v4l2_ctrl_new_std_menu(hdl, ++ &bm2835_mmal_ctrl_ops, ctrl->id, ++ ctrl->max, mask, ctrl->def); ++ break; ++ } ++ ++ case MMAL_CONTROL_TYPE_INT_MENU: ++ dev->ctrls[c] = v4l2_ctrl_new_int_menu(hdl, ++ &bm2835_mmal_ctrl_ops, ctrl->id, ++ ctrl->max, ctrl->def, ctrl->imenu); ++ break; ++ ++ case MMAL_CONTROL_TYPE_CLUSTER: ++ /* skip this entry when constructing controls */ ++ continue; ++ } ++ ++ if (hdl->error) ++ break; ++ ++ dev->ctrls[c]->priv = (void *)ctrl; ++ } ++ ++ if (hdl->error) { ++ pr_err("error adding control %d/%d id 0x%x\n", c, ++ V4L2_CTRL_COUNT, ctrl->id); ++ return hdl->error; ++ } ++ ++ for (c = 0; c < V4L2_CTRL_COUNT; c++) { ++ ctrl = &v4l2_ctrls[c]; ++ ++ switch (ctrl->type) { ++ case MMAL_CONTROL_TYPE_CLUSTER: ++ v4l2_ctrl_auto_cluster(ctrl->min, ++ &dev->ctrls[c+1], ++ ctrl->max, ++ ctrl->def); ++ break; ++ ++ case MMAL_CONTROL_TYPE_STD: ++ case MMAL_CONTROL_TYPE_STD_MENU: ++ case MMAL_CONTROL_TYPE_INT_MENU: ++ break; ++ } ++ ++ } ++ ++ return 0; ++} +diff -Nur linux-4.1.13.orig/drivers/media/platform/bcm2835/Kconfig linux-rpi/drivers/media/platform/bcm2835/Kconfig +--- linux-4.1.13.orig/drivers/media/platform/bcm2835/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/media/platform/bcm2835/Kconfig 2015-11-29 09:42:37.835237156 +0100 +@@ -0,0 +1,25 @@ ++# Broadcom VideoCore IV v4l2 camera support ++ ++config VIDEO_BCM2835 ++ bool "Broadcom BCM2835 camera interface driver" ++ depends on VIDEO_V4L2 && (ARCH_BCM2708 || ARCH_BCM2709 || ARCH_BCM2835) ++ ---help--- ++ Say Y here to enable camera host interface devices for ++ Broadcom BCM2835 SoC. This operates over the VCHIQ interface ++ to a service running on VideoCore. ++ ++ ++if VIDEO_BCM2835 ++ ++config VIDEO_BCM2835_MMAL ++ tristate "Broadcom BM2835 MMAL camera interface driver" ++ depends on BCM2708_VCHIQ ++ select VIDEOBUF2_VMALLOC ++ ---help--- ++ This is a V4L2 driver for the Broadcom BCM2835 MMAL camera host interface ++ ++ To compile this driver as a module, choose M here: the ++ module will be called bcm2835-v4l2.o ++ ++ ++endif # VIDEO_BM2835 +diff -Nur linux-4.1.13.orig/drivers/media/platform/bcm2835/Makefile linux-rpi/drivers/media/platform/bcm2835/Makefile +--- linux-4.1.13.orig/drivers/media/platform/bcm2835/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/media/platform/bcm2835/Makefile 2015-11-29 09:42:37.835237156 +0100 +@@ -0,0 +1,5 @@ ++bcm2835-v4l2-objs := bcm2835-camera.o controls.o mmal-vchiq.o ++ ++obj-$(CONFIG_VIDEO_BCM2835_MMAL) += bcm2835-v4l2.o ++ ++ccflags-$(CONFIG_VIDEO_BCM2835) += -Idrivers/misc/vc04_services -Idrivers/misc/vc04_services/interface/vcos/linuxkernel -D__VCCOREVER__=0x04000000 +diff -Nur linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-common.h linux-rpi/drivers/media/platform/bcm2835/mmal-common.h +--- linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-common.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/media/platform/bcm2835/mmal-common.h 2015-11-29 09:42:37.835237156 +0100 +@@ -0,0 +1,53 @@ ++/* ++ * Broadcom BM2835 V4L2 driver ++ * ++ * Copyright © 2013 Raspberry Pi (Trading) Ltd. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ * ++ * Authors: Vincent Sanders ++ * Dave Stevenson ++ * Simon Mellor ++ * Luke Diamand ++ * ++ * MMAL structures ++ * ++ */ ++ ++#define MMAL_FOURCC(a, b, c, d) ((a) | (b << 8) | (c << 16) | (d << 24)) ++#define MMAL_MAGIC MMAL_FOURCC('m', 'm', 'a', 'l') ++ ++/** Special value signalling that time is not known */ ++#define MMAL_TIME_UNKNOWN (1LL<<63) ++ ++/* mapping between v4l and mmal video modes */ ++struct mmal_fmt { ++ char *name; ++ u32 fourcc; /* v4l2 format id */ ++ int flags; /* v4l2 flags field */ ++ u32 mmal; ++ int depth; ++ u32 mmal_component; /* MMAL component index to be used to encode */ ++ u32 ybbp; /* depth of first Y plane for planar formats */ ++}; ++ ++/* buffer for one video frame */ ++struct mmal_buffer { ++ /* v4l buffer data -- must be first */ ++ struct vb2_buffer vb; ++ ++ /* list of buffers available */ ++ struct list_head list; ++ ++ void *buffer; /* buffer pointer */ ++ unsigned long buffer_size; /* size of allocated buffer */ ++}; ++ ++/* */ ++struct mmal_colourfx { ++ s32 enable; ++ u32 u; ++ u32 v; ++}; +diff -Nur linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-encodings.h linux-rpi/drivers/media/platform/bcm2835/mmal-encodings.h +--- linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-encodings.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/media/platform/bcm2835/mmal-encodings.h 2015-11-29 09:42:37.835237156 +0100 +@@ -0,0 +1,127 @@ ++/* ++ * Broadcom BM2835 V4L2 driver ++ * ++ * Copyright © 2013 Raspberry Pi (Trading) Ltd. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ * ++ * Authors: Vincent Sanders ++ * Dave Stevenson ++ * Simon Mellor ++ * Luke Diamand ++ */ ++#ifndef MMAL_ENCODINGS_H ++#define MMAL_ENCODINGS_H ++ ++#define MMAL_ENCODING_H264 MMAL_FOURCC('H', '2', '6', '4') ++#define MMAL_ENCODING_H263 MMAL_FOURCC('H', '2', '6', '3') ++#define MMAL_ENCODING_MP4V MMAL_FOURCC('M', 'P', '4', 'V') ++#define MMAL_ENCODING_MP2V MMAL_FOURCC('M', 'P', '2', 'V') ++#define MMAL_ENCODING_MP1V MMAL_FOURCC('M', 'P', '1', 'V') ++#define MMAL_ENCODING_WMV3 MMAL_FOURCC('W', 'M', 'V', '3') ++#define MMAL_ENCODING_WMV2 MMAL_FOURCC('W', 'M', 'V', '2') ++#define MMAL_ENCODING_WMV1 MMAL_FOURCC('W', 'M', 'V', '1') ++#define MMAL_ENCODING_WVC1 MMAL_FOURCC('W', 'V', 'C', '1') ++#define MMAL_ENCODING_VP8 MMAL_FOURCC('V', 'P', '8', ' ') ++#define MMAL_ENCODING_VP7 MMAL_FOURCC('V', 'P', '7', ' ') ++#define MMAL_ENCODING_VP6 MMAL_FOURCC('V', 'P', '6', ' ') ++#define MMAL_ENCODING_THEORA MMAL_FOURCC('T', 'H', 'E', 'O') ++#define MMAL_ENCODING_SPARK MMAL_FOURCC('S', 'P', 'R', 'K') ++#define MMAL_ENCODING_MJPEG MMAL_FOURCC('M', 'J', 'P', 'G') ++ ++#define MMAL_ENCODING_JPEG MMAL_FOURCC('J', 'P', 'E', 'G') ++#define MMAL_ENCODING_GIF MMAL_FOURCC('G', 'I', 'F', ' ') ++#define MMAL_ENCODING_PNG MMAL_FOURCC('P', 'N', 'G', ' ') ++#define MMAL_ENCODING_PPM MMAL_FOURCC('P', 'P', 'M', ' ') ++#define MMAL_ENCODING_TGA MMAL_FOURCC('T', 'G', 'A', ' ') ++#define MMAL_ENCODING_BMP MMAL_FOURCC('B', 'M', 'P', ' ') ++ ++#define MMAL_ENCODING_I420 MMAL_FOURCC('I', '4', '2', '0') ++#define MMAL_ENCODING_I420_SLICE MMAL_FOURCC('S', '4', '2', '0') ++#define MMAL_ENCODING_YV12 MMAL_FOURCC('Y', 'V', '1', '2') ++#define MMAL_ENCODING_I422 MMAL_FOURCC('I', '4', '2', '2') ++#define MMAL_ENCODING_I422_SLICE MMAL_FOURCC('S', '4', '2', '2') ++#define MMAL_ENCODING_YUYV MMAL_FOURCC('Y', 'U', 'Y', 'V') ++#define MMAL_ENCODING_YVYU MMAL_FOURCC('Y', 'V', 'Y', 'U') ++#define MMAL_ENCODING_UYVY MMAL_FOURCC('U', 'Y', 'V', 'Y') ++#define MMAL_ENCODING_VYUY MMAL_FOURCC('V', 'Y', 'U', 'Y') ++#define MMAL_ENCODING_NV12 MMAL_FOURCC('N', 'V', '1', '2') ++#define MMAL_ENCODING_NV21 MMAL_FOURCC('N', 'V', '2', '1') ++#define MMAL_ENCODING_ARGB MMAL_FOURCC('A', 'R', 'G', 'B') ++#define MMAL_ENCODING_RGBA MMAL_FOURCC('R', 'G', 'B', 'A') ++#define MMAL_ENCODING_ABGR MMAL_FOURCC('A', 'B', 'G', 'R') ++#define MMAL_ENCODING_BGRA MMAL_FOURCC('B', 'G', 'R', 'A') ++#define MMAL_ENCODING_RGB16 MMAL_FOURCC('R', 'G', 'B', '2') ++#define MMAL_ENCODING_RGB24 MMAL_FOURCC('R', 'G', 'B', '3') ++#define MMAL_ENCODING_RGB32 MMAL_FOURCC('R', 'G', 'B', '4') ++#define MMAL_ENCODING_BGR16 MMAL_FOURCC('B', 'G', 'R', '2') ++#define MMAL_ENCODING_BGR24 MMAL_FOURCC('B', 'G', 'R', '3') ++#define MMAL_ENCODING_BGR32 MMAL_FOURCC('B', 'G', 'R', '4') ++ ++/** SAND Video (YUVUV128) format, native format understood by VideoCore. ++ * This format is *not* opaque - if requested you will receive full frames ++ * of YUV_UV video. ++ */ ++#define MMAL_ENCODING_YUVUV128 MMAL_FOURCC('S', 'A', 'N', 'D') ++ ++/** VideoCore opaque image format, image handles are returned to ++ * the host but not the actual image data. ++ */ ++#define MMAL_ENCODING_OPAQUE MMAL_FOURCC('O', 'P', 'Q', 'V') ++ ++/** An EGL image handle ++ */ ++#define MMAL_ENCODING_EGL_IMAGE MMAL_FOURCC('E', 'G', 'L', 'I') ++ ++/* }@ */ ++ ++/** \name Pre-defined audio encodings */ ++/* @{ */ ++#define MMAL_ENCODING_PCM_UNSIGNED_BE MMAL_FOURCC('P', 'C', 'M', 'U') ++#define MMAL_ENCODING_PCM_UNSIGNED_LE MMAL_FOURCC('p', 'c', 'm', 'u') ++#define MMAL_ENCODING_PCM_SIGNED_BE MMAL_FOURCC('P', 'C', 'M', 'S') ++#define MMAL_ENCODING_PCM_SIGNED_LE MMAL_FOURCC('p', 'c', 'm', 's') ++#define MMAL_ENCODING_PCM_FLOAT_BE MMAL_FOURCC('P', 'C', 'M', 'F') ++#define MMAL_ENCODING_PCM_FLOAT_LE MMAL_FOURCC('p', 'c', 'm', 'f') ++ ++/* Pre-defined H264 encoding variants */ ++ ++/** ISO 14496-10 Annex B byte stream format */ ++#define MMAL_ENCODING_VARIANT_H264_DEFAULT 0 ++/** ISO 14496-15 AVC stream format */ ++#define MMAL_ENCODING_VARIANT_H264_AVC1 MMAL_FOURCC('A', 'V', 'C', '1') ++/** Implicitly delineated NAL units without emulation prevention */ ++#define MMAL_ENCODING_VARIANT_H264_RAW MMAL_FOURCC('R', 'A', 'W', ' ') ++ ++ ++/** \defgroup MmalColorSpace List of pre-defined video color spaces ++ * This defines a list of common color spaces. This list isn't exhaustive and ++ * is only provided as a convenience to avoid clients having to use FourCC ++ * codes directly. However components are allowed to define and use their own ++ * FourCC codes. ++ */ ++/* @{ */ ++ ++/** Unknown color space */ ++#define MMAL_COLOR_SPACE_UNKNOWN 0 ++/** ITU-R BT.601-5 [SDTV] */ ++#define MMAL_COLOR_SPACE_ITUR_BT601 MMAL_FOURCC('Y', '6', '0', '1') ++/** ITU-R BT.709-3 [HDTV] */ ++#define MMAL_COLOR_SPACE_ITUR_BT709 MMAL_FOURCC('Y', '7', '0', '9') ++/** JPEG JFIF */ ++#define MMAL_COLOR_SPACE_JPEG_JFIF MMAL_FOURCC('Y', 'J', 'F', 'I') ++/** Title 47 Code of Federal Regulations (2003) 73.682 (a) (20) */ ++#define MMAL_COLOR_SPACE_FCC MMAL_FOURCC('Y', 'F', 'C', 'C') ++/** Society of Motion Picture and Television Engineers 240M (1999) */ ++#define MMAL_COLOR_SPACE_SMPTE240M MMAL_FOURCC('Y', '2', '4', '0') ++/** ITU-R BT.470-2 System M */ ++#define MMAL_COLOR_SPACE_BT470_2_M MMAL_FOURCC('Y', '_', '_', 'M') ++/** ITU-R BT.470-2 System BG */ ++#define MMAL_COLOR_SPACE_BT470_2_BG MMAL_FOURCC('Y', '_', 'B', 'G') ++/** JPEG JFIF, but with 16..255 luma */ ++#define MMAL_COLOR_SPACE_JFIF_Y16_255 MMAL_FOURCC('Y', 'Y', '1', '6') ++/* @} MmalColorSpace List */ ++ ++#endif /* MMAL_ENCODINGS_H */ +diff -Nur linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-msg-common.h linux-rpi/drivers/media/platform/bcm2835/mmal-msg-common.h +--- linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-msg-common.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/media/platform/bcm2835/mmal-msg-common.h 2015-11-29 09:42:37.835237156 +0100 +@@ -0,0 +1,50 @@ ++/* ++ * Broadcom BM2835 V4L2 driver ++ * ++ * Copyright © 2013 Raspberry Pi (Trading) Ltd. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ * ++ * Authors: Vincent Sanders ++ * Dave Stevenson ++ * Simon Mellor ++ * Luke Diamand ++ */ ++ ++#ifndef MMAL_MSG_COMMON_H ++#define MMAL_MSG_COMMON_H ++ ++enum mmal_msg_status { ++ MMAL_MSG_STATUS_SUCCESS = 0, /**< Success */ ++ MMAL_MSG_STATUS_ENOMEM, /**< Out of memory */ ++ MMAL_MSG_STATUS_ENOSPC, /**< Out of resources other than memory */ ++ MMAL_MSG_STATUS_EINVAL, /**< Argument is invalid */ ++ MMAL_MSG_STATUS_ENOSYS, /**< Function not implemented */ ++ MMAL_MSG_STATUS_ENOENT, /**< No such file or directory */ ++ MMAL_MSG_STATUS_ENXIO, /**< No such device or address */ ++ MMAL_MSG_STATUS_EIO, /**< I/O error */ ++ MMAL_MSG_STATUS_ESPIPE, /**< Illegal seek */ ++ MMAL_MSG_STATUS_ECORRUPT, /**< Data is corrupt \attention */ ++ MMAL_MSG_STATUS_ENOTREADY, /**< Component is not ready */ ++ MMAL_MSG_STATUS_ECONFIG, /**< Component is not configured */ ++ MMAL_MSG_STATUS_EISCONN, /**< Port is already connected */ ++ MMAL_MSG_STATUS_ENOTCONN, /**< Port is disconnected */ ++ MMAL_MSG_STATUS_EAGAIN, /**< Resource temporarily unavailable. */ ++ MMAL_MSG_STATUS_EFAULT, /**< Bad address */ ++}; ++ ++struct mmal_rect { ++ s32 x; /**< x coordinate (from left) */ ++ s32 y; /**< y coordinate (from top) */ ++ s32 width; /**< width */ ++ s32 height; /**< height */ ++}; ++ ++struct mmal_rational { ++ s32 num; /**< Numerator */ ++ s32 den; /**< Denominator */ ++}; ++ ++#endif /* MMAL_MSG_COMMON_H */ +diff -Nur linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-msg-format.h linux-rpi/drivers/media/platform/bcm2835/mmal-msg-format.h +--- linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-msg-format.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/media/platform/bcm2835/mmal-msg-format.h 2015-11-29 09:42:37.835237156 +0100 +@@ -0,0 +1,81 @@ ++/* ++ * Broadcom BM2835 V4L2 driver ++ * ++ * Copyright © 2013 Raspberry Pi (Trading) Ltd. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ * ++ * Authors: Vincent Sanders ++ * Dave Stevenson ++ * Simon Mellor ++ * Luke Diamand ++ */ ++ ++#ifndef MMAL_MSG_FORMAT_H ++#define MMAL_MSG_FORMAT_H ++ ++#include "mmal-msg-common.h" ++ ++/* MMAL_ES_FORMAT_T */ ++ ++ ++struct mmal_audio_format { ++ u32 channels; /**< Number of audio channels */ ++ u32 sample_rate; /**< Sample rate */ ++ ++ u32 bits_per_sample; /**< Bits per sample */ ++ u32 block_align; /**< Size of a block of data */ ++}; ++ ++struct mmal_video_format { ++ u32 width; /**< Width of frame in pixels */ ++ u32 height; /**< Height of frame in rows of pixels */ ++ struct mmal_rect crop; /**< Visible region of the frame */ ++ struct mmal_rational frame_rate; /**< Frame rate */ ++ struct mmal_rational par; /**< Pixel aspect ratio */ ++ ++ /* FourCC specifying the color space of the video stream. See the ++ * \ref MmalColorSpace "pre-defined color spaces" for some examples. ++ */ ++ u32 color_space; ++}; ++ ++struct mmal_subpicture_format { ++ u32 x_offset; ++ u32 y_offset; ++}; ++ ++union mmal_es_specific_format { ++ struct mmal_audio_format audio; ++ struct mmal_video_format video; ++ struct mmal_subpicture_format subpicture; ++}; ++ ++/** Definition of an elementary stream format (MMAL_ES_FORMAT_T) */ ++struct mmal_es_format { ++ u32 type; /* enum mmal_es_type */ ++ ++ u32 encoding; /* FourCC specifying encoding of the elementary stream.*/ ++ u32 encoding_variant; /* FourCC specifying the specific ++ * encoding variant of the elementary ++ * stream. ++ */ ++ ++ union mmal_es_specific_format *es; /* TODO: pointers in ++ * message serialisation?!? ++ */ ++ /* Type specific ++ * information for the ++ * elementary stream ++ */ ++ ++ u32 bitrate; /**< Bitrate in bits per second */ ++ u32 flags; /**< Flags describing properties of the elementary stream. */ ++ ++ u32 extradata_size; /**< Size of the codec specific data */ ++ u8 *extradata; /**< Codec specific data */ ++}; ++ ++#endif /* MMAL_MSG_FORMAT_H */ +diff -Nur linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-msg.h linux-rpi/drivers/media/platform/bcm2835/mmal-msg.h +--- linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-msg.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/media/platform/bcm2835/mmal-msg.h 2015-11-29 09:42:37.835237156 +0100 +@@ -0,0 +1,404 @@ ++/* ++ * Broadcom BM2835 V4L2 driver ++ * ++ * Copyright © 2013 Raspberry Pi (Trading) Ltd. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ * ++ * Authors: Vincent Sanders ++ * Dave Stevenson ++ * Simon Mellor ++ * Luke Diamand ++ */ ++ ++/* all the data structures which serialise the MMAL protocol. note ++ * these are directly mapped onto the recived message data. ++ * ++ * BEWARE: They seem to *assume* pointers are u32 and that there is no ++ * structure padding! ++ * ++ * NOTE: this implementation uses kernel types to ensure sizes. Rather ++ * than assigning values to enums to force their size the ++ * implementation uses fixed size types and not the enums (though the ++ * comments have the actual enum type ++ */ ++ ++#define VC_MMAL_VER 15 ++#define VC_MMAL_MIN_VER 10 ++#define VC_MMAL_SERVER_NAME MAKE_FOURCC("mmal") ++ ++/* max total message size is 512 bytes */ ++#define MMAL_MSG_MAX_SIZE 512 ++/* with six 32bit header elements max payload is therefore 488 bytes */ ++#define MMAL_MSG_MAX_PAYLOAD 488 ++ ++#include "mmal-msg-common.h" ++#include "mmal-msg-format.h" ++#include "mmal-msg-port.h" ++ ++enum mmal_msg_type { ++ MMAL_MSG_TYPE_QUIT = 1, ++ MMAL_MSG_TYPE_SERVICE_CLOSED, ++ MMAL_MSG_TYPE_GET_VERSION, ++ MMAL_MSG_TYPE_COMPONENT_CREATE, ++ MMAL_MSG_TYPE_COMPONENT_DESTROY, /* 5 */ ++ MMAL_MSG_TYPE_COMPONENT_ENABLE, ++ MMAL_MSG_TYPE_COMPONENT_DISABLE, ++ MMAL_MSG_TYPE_PORT_INFO_GET, ++ MMAL_MSG_TYPE_PORT_INFO_SET, ++ MMAL_MSG_TYPE_PORT_ACTION, /* 10 */ ++ MMAL_MSG_TYPE_BUFFER_FROM_HOST, ++ MMAL_MSG_TYPE_BUFFER_TO_HOST, ++ MMAL_MSG_TYPE_GET_STATS, ++ MMAL_MSG_TYPE_PORT_PARAMETER_SET, ++ MMAL_MSG_TYPE_PORT_PARAMETER_GET, /* 15 */ ++ MMAL_MSG_TYPE_EVENT_TO_HOST, ++ MMAL_MSG_TYPE_GET_CORE_STATS_FOR_PORT, ++ MMAL_MSG_TYPE_OPAQUE_ALLOCATOR, ++ MMAL_MSG_TYPE_CONSUME_MEM, ++ MMAL_MSG_TYPE_LMK, /* 20 */ ++ MMAL_MSG_TYPE_OPAQUE_ALLOCATOR_DESC, ++ MMAL_MSG_TYPE_DRM_GET_LHS32, ++ MMAL_MSG_TYPE_DRM_GET_TIME, ++ MMAL_MSG_TYPE_BUFFER_FROM_HOST_ZEROLEN, ++ MMAL_MSG_TYPE_PORT_FLUSH, /* 25 */ ++ MMAL_MSG_TYPE_HOST_LOG, ++ MMAL_MSG_TYPE_MSG_LAST ++}; ++ ++/* port action request messages differ depending on the action type */ ++enum mmal_msg_port_action_type { ++ MMAL_MSG_PORT_ACTION_TYPE_UNKNOWN = 0, /* Unkown action */ ++ MMAL_MSG_PORT_ACTION_TYPE_ENABLE, /* Enable a port */ ++ MMAL_MSG_PORT_ACTION_TYPE_DISABLE, /* Disable a port */ ++ MMAL_MSG_PORT_ACTION_TYPE_FLUSH, /* Flush a port */ ++ MMAL_MSG_PORT_ACTION_TYPE_CONNECT, /* Connect ports */ ++ MMAL_MSG_PORT_ACTION_TYPE_DISCONNECT, /* Disconnect ports */ ++ MMAL_MSG_PORT_ACTION_TYPE_SET_REQUIREMENTS, /* Set buffer requirements*/ ++}; ++ ++struct mmal_msg_header { ++ u32 magic; ++ u32 type; /** enum mmal_msg_type */ ++ ++ /* Opaque handle to the control service */ ++ struct mmal_control_service *control_service; ++ ++ struct mmal_msg_context *context; /** a u32 per message context */ ++ u32 status; /** The status of the vchiq operation */ ++ u32 padding; ++}; ++ ++/* Send from VC to host to report version */ ++struct mmal_msg_version { ++ u32 flags; ++ u32 major; ++ u32 minor; ++ u32 minimum; ++}; ++ ++/* request to VC to create component */ ++struct mmal_msg_component_create { ++ void *client_component; /* component context */ ++ char name[128]; ++ u32 pid; /* For debug */ ++}; ++ ++/* reply from VC to component creation request */ ++struct mmal_msg_component_create_reply { ++ u32 status; /** enum mmal_msg_status - how does this differ to ++ * the one in the header? ++ */ ++ u32 component_handle; /* VideoCore handle for component */ ++ u32 input_num; /* Number of input ports */ ++ u32 output_num; /* Number of output ports */ ++ u32 clock_num; /* Number of clock ports */ ++}; ++ ++/* request to VC to destroy a component */ ++struct mmal_msg_component_destroy { ++ u32 component_handle; ++}; ++ ++struct mmal_msg_component_destroy_reply { ++ u32 status; /** The component destruction status */ ++}; ++ ++ ++/* request and reply to VC to enable a component */ ++struct mmal_msg_component_enable { ++ u32 component_handle; ++}; ++ ++struct mmal_msg_component_enable_reply { ++ u32 status; /** The component enable status */ ++}; ++ ++ ++/* request and reply to VC to disable a component */ ++struct mmal_msg_component_disable { ++ u32 component_handle; ++}; ++ ++struct mmal_msg_component_disable_reply { ++ u32 status; /** The component disable status */ ++}; ++ ++/* request to VC to get port information */ ++struct mmal_msg_port_info_get { ++ u32 component_handle; /* component handle port is associated with */ ++ u32 port_type; /* enum mmal_msg_port_type */ ++ u32 index; /* port index to query */ ++}; ++ ++/* reply from VC to get port info request */ ++struct mmal_msg_port_info_get_reply { ++ u32 status; /** enum mmal_msg_status */ ++ u32 component_handle; /* component handle port is associated with */ ++ u32 port_type; /* enum mmal_msg_port_type */ ++ u32 port_index; /* port indexed in query */ ++ s32 found; /* unused */ ++ u32 port_handle; /**< Handle to use for this port */ ++ struct mmal_port port; ++ struct mmal_es_format format; /* elementry stream format */ ++ union mmal_es_specific_format es; /* es type specific data */ ++ u8 extradata[MMAL_FORMAT_EXTRADATA_MAX_SIZE]; /* es extra data */ ++}; ++ ++/* request to VC to set port information */ ++struct mmal_msg_port_info_set { ++ u32 component_handle; ++ u32 port_type; /* enum mmal_msg_port_type */ ++ u32 port_index; /* port indexed in query */ ++ struct mmal_port port; ++ struct mmal_es_format format; ++ union mmal_es_specific_format es; ++ u8 extradata[MMAL_FORMAT_EXTRADATA_MAX_SIZE]; ++}; ++ ++/* reply from VC to port info set request */ ++struct mmal_msg_port_info_set_reply { ++ u32 status; ++ u32 component_handle; /* component handle port is associated with */ ++ u32 port_type; /* enum mmal_msg_port_type */ ++ u32 index; /* port indexed in query */ ++ s32 found; /* unused */ ++ u32 port_handle; /**< Handle to use for this port */ ++ struct mmal_port port; ++ struct mmal_es_format format; ++ union mmal_es_specific_format es; ++ u8 extradata[MMAL_FORMAT_EXTRADATA_MAX_SIZE]; ++}; ++ ++ ++/* port action requests that take a mmal_port as a parameter */ ++struct mmal_msg_port_action_port { ++ u32 component_handle; ++ u32 port_handle; ++ u32 action; /* enum mmal_msg_port_action_type */ ++ struct mmal_port port; ++}; ++ ++/* port action requests that take handles as a parameter */ ++struct mmal_msg_port_action_handle { ++ u32 component_handle; ++ u32 port_handle; ++ u32 action; /* enum mmal_msg_port_action_type */ ++ u32 connect_component_handle; ++ u32 connect_port_handle; ++}; ++ ++struct mmal_msg_port_action_reply { ++ u32 status; /** The port action operation status */ ++}; ++ ++ ++ ++ ++/* MMAL buffer transfer */ ++ ++/** Size of space reserved in a buffer message for short messages. */ ++#define MMAL_VC_SHORT_DATA 128 ++ ++/** Signals that the current payload is the end of the stream of data */ ++#define MMAL_BUFFER_HEADER_FLAG_EOS (1<<0) ++/** Signals that the start of the current payload starts a frame */ ++#define MMAL_BUFFER_HEADER_FLAG_FRAME_START (1<<1) ++/** Signals that the end of the current payload ends a frame */ ++#define MMAL_BUFFER_HEADER_FLAG_FRAME_END (1<<2) ++/** Signals that the current payload contains only complete frames (>1) */ ++#define MMAL_BUFFER_HEADER_FLAG_FRAME \ ++ (MMAL_BUFFER_HEADER_FLAG_FRAME_START|MMAL_BUFFER_HEADER_FLAG_FRAME_END) ++/** Signals that the current payload is a keyframe (i.e. self decodable) */ ++#define MMAL_BUFFER_HEADER_FLAG_KEYFRAME (1<<3) ++/** Signals a discontinuity in the stream of data (e.g. after a seek). ++ * Can be used for instance by a decoder to reset its state */ ++#define MMAL_BUFFER_HEADER_FLAG_DISCONTINUITY (1<<4) ++/** Signals a buffer containing some kind of config data for the component ++ * (e.g. codec config data) */ ++#define MMAL_BUFFER_HEADER_FLAG_CONFIG (1<<5) ++/** Signals an encrypted payload */ ++#define MMAL_BUFFER_HEADER_FLAG_ENCRYPTED (1<<6) ++/** Signals a buffer containing side information */ ++#define MMAL_BUFFER_HEADER_FLAG_CODECSIDEINFO (1<<7) ++/** Signals a buffer which is the snapshot/postview image from a stills ++ * capture ++ */ ++#define MMAL_BUFFER_HEADER_FLAGS_SNAPSHOT (1<<8) ++/** Signals a buffer which contains data known to be corrupted */ ++#define MMAL_BUFFER_HEADER_FLAG_CORRUPTED (1<<9) ++/** Signals that a buffer failed to be transmitted */ ++#define MMAL_BUFFER_HEADER_FLAG_TRANSMISSION_FAILED (1<<10) ++ ++struct mmal_driver_buffer { ++ u32 magic; ++ u32 component_handle; ++ u32 port_handle; ++ void *client_context; ++}; ++ ++/* buffer header */ ++struct mmal_buffer_header { ++ struct mmal_buffer_header *next; /* next header */ ++ void *priv; /* framework private data */ ++ u32 cmd; ++ void *data; ++ u32 alloc_size; ++ u32 length; ++ u32 offset; ++ u32 flags; ++ s64 pts; ++ s64 dts; ++ void *type; ++ void *user_data; ++}; ++ ++struct mmal_buffer_header_type_specific { ++ union { ++ struct { ++ u32 planes; ++ u32 offset[4]; ++ u32 pitch[4]; ++ u32 flags; ++ } video; ++ } u; ++}; ++ ++struct mmal_msg_buffer_from_host { ++ /* The front 32 bytes of the buffer header are copied ++ * back to us in the reply to allow for context. This ++ * area is used to store two mmal_driver_buffer structures to ++ * allow for multiple concurrent service users. ++ */ ++ /* control data */ ++ struct mmal_driver_buffer drvbuf; ++ ++ /* referenced control data for passthrough buffer management */ ++ struct mmal_driver_buffer drvbuf_ref; ++ struct mmal_buffer_header buffer_header; /* buffer header itself */ ++ struct mmal_buffer_header_type_specific buffer_header_type_specific; ++ s32 is_zero_copy; ++ s32 has_reference; ++ ++ /** allows short data to be xfered in control message */ ++ u32 payload_in_message; ++ u8 short_data[MMAL_VC_SHORT_DATA]; ++}; ++ ++ ++/* port parameter setting */ ++ ++#define MMAL_WORKER_PORT_PARAMETER_SPACE 96 ++ ++struct mmal_msg_port_parameter_set { ++ u32 component_handle; /* component */ ++ u32 port_handle; /* port */ ++ u32 id; /* Parameter ID */ ++ u32 size; /* Parameter size */ ++ uint32_t value[MMAL_WORKER_PORT_PARAMETER_SPACE]; ++}; ++ ++struct mmal_msg_port_parameter_set_reply { ++ u32 status; /** enum mmal_msg_status todo: how does this ++ * differ to the one in the header? ++ */ ++}; ++ ++/* port parameter getting */ ++ ++struct mmal_msg_port_parameter_get { ++ u32 component_handle; /* component */ ++ u32 port_handle; /* port */ ++ u32 id; /* Parameter ID */ ++ u32 size; /* Parameter size */ ++}; ++ ++struct mmal_msg_port_parameter_get_reply { ++ u32 status; /* Status of mmal_port_parameter_get call */ ++ u32 id; /* Parameter ID */ ++ u32 size; /* Parameter size */ ++ uint32_t value[MMAL_WORKER_PORT_PARAMETER_SPACE]; ++}; ++ ++/* event messages */ ++#define MMAL_WORKER_EVENT_SPACE 256 ++ ++struct mmal_msg_event_to_host { ++ void *client_component; /* component context */ ++ ++ u32 port_type; ++ u32 port_num; ++ ++ u32 cmd; ++ u32 length; ++ u8 data[MMAL_WORKER_EVENT_SPACE]; ++ struct mmal_buffer_header *delayed_buffer; ++}; ++ ++/* all mmal messages are serialised through this structure */ ++struct mmal_msg { ++ /* header */ ++ struct mmal_msg_header h; ++ /* payload */ ++ union { ++ struct mmal_msg_version version; ++ ++ struct mmal_msg_component_create component_create; ++ struct mmal_msg_component_create_reply component_create_reply; ++ ++ struct mmal_msg_component_destroy component_destroy; ++ struct mmal_msg_component_destroy_reply component_destroy_reply; ++ ++ struct mmal_msg_component_enable component_enable; ++ struct mmal_msg_component_enable_reply component_enable_reply; ++ ++ struct mmal_msg_component_disable component_disable; ++ struct mmal_msg_component_disable_reply component_disable_reply; ++ ++ struct mmal_msg_port_info_get port_info_get; ++ struct mmal_msg_port_info_get_reply port_info_get_reply; ++ ++ struct mmal_msg_port_info_set port_info_set; ++ struct mmal_msg_port_info_set_reply port_info_set_reply; ++ ++ struct mmal_msg_port_action_port port_action_port; ++ struct mmal_msg_port_action_handle port_action_handle; ++ struct mmal_msg_port_action_reply port_action_reply; ++ ++ struct mmal_msg_buffer_from_host buffer_from_host; ++ ++ struct mmal_msg_port_parameter_set port_parameter_set; ++ struct mmal_msg_port_parameter_set_reply ++ port_parameter_set_reply; ++ struct mmal_msg_port_parameter_get ++ port_parameter_get; ++ struct mmal_msg_port_parameter_get_reply ++ port_parameter_get_reply; ++ ++ struct mmal_msg_event_to_host event_to_host; ++ ++ u8 payload[MMAL_MSG_MAX_PAYLOAD]; ++ } u; ++}; +diff -Nur linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-msg-port.h linux-rpi/drivers/media/platform/bcm2835/mmal-msg-port.h +--- linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-msg-port.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/media/platform/bcm2835/mmal-msg-port.h 2015-11-29 09:42:37.835237156 +0100 +@@ -0,0 +1,107 @@ ++/* ++ * Broadcom BM2835 V4L2 driver ++ * ++ * Copyright © 2013 Raspberry Pi (Trading) Ltd. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ * ++ * Authors: Vincent Sanders ++ * Dave Stevenson ++ * Simon Mellor ++ * Luke Diamand ++ */ ++ ++/* MMAL_PORT_TYPE_T */ ++enum mmal_port_type { ++ MMAL_PORT_TYPE_UNKNOWN = 0, /**< Unknown port type */ ++ MMAL_PORT_TYPE_CONTROL, /**< Control port */ ++ MMAL_PORT_TYPE_INPUT, /**< Input port */ ++ MMAL_PORT_TYPE_OUTPUT, /**< Output port */ ++ MMAL_PORT_TYPE_CLOCK, /**< Clock port */ ++}; ++ ++/** The port is pass-through and doesn't need buffer headers allocated */ ++#define MMAL_PORT_CAPABILITY_PASSTHROUGH 0x01 ++/** The port wants to allocate the buffer payloads. ++ * This signals a preference that payload allocation should be done ++ * on this port for efficiency reasons. */ ++#define MMAL_PORT_CAPABILITY_ALLOCATION 0x02 ++/** The port supports format change events. ++ * This applies to input ports and is used to let the client know ++ * whether the port supports being reconfigured via a format ++ * change event (i.e. without having to disable the port). */ ++#define MMAL_PORT_CAPABILITY_SUPPORTS_EVENT_FORMAT_CHANGE 0x04 ++ ++/* mmal port structure (MMAL_PORT_T) ++ * ++ * most elements are informational only, the pointer values for ++ * interogation messages are generally provided as additional ++ * strucures within the message. When used to set values only teh ++ * buffer_num, buffer_size and userdata parameters are writable. ++ */ ++struct mmal_port { ++ void *priv; /* Private member used by the framework */ ++ const char *name; /* Port name. Used for debugging purposes (RO) */ ++ ++ u32 type; /* Type of the port (RO) enum mmal_port_type */ ++ u16 index; /* Index of the port in its type list (RO) */ ++ u16 index_all; /* Index of the port in the list of all ports (RO) */ ++ ++ u32 is_enabled; /* Indicates whether the port is enabled or not (RO) */ ++ struct mmal_es_format *format; /* Format of the elementary stream */ ++ ++ u32 buffer_num_min; /* Minimum number of buffers the port ++ * requires (RO). This is set by the ++ * component. ++ */ ++ ++ u32 buffer_size_min; /* Minimum size of buffers the port ++ * requires (RO). This is set by the ++ * component. ++ */ ++ ++ u32 buffer_alignment_min; /* Minimum alignment requirement for ++ * the buffers (RO). A value of ++ * zero means no special alignment ++ * requirements. This is set by the ++ * component. ++ */ ++ ++ u32 buffer_num_recommended; /* Number of buffers the port ++ * recommends for optimal ++ * performance (RO). A value of ++ * zero means no special ++ * recommendation. This is set ++ * by the component. ++ */ ++ ++ u32 buffer_size_recommended; /* Size of buffers the port ++ * recommends for optimal ++ * performance (RO). A value of ++ * zero means no special ++ * recommendation. This is set ++ * by the component. ++ */ ++ ++ u32 buffer_num; /* Actual number of buffers the port will use. ++ * This is set by the client. ++ */ ++ ++ u32 buffer_size; /* Actual maximum size of the buffers that ++ * will be sent to the port. This is set by ++ * the client. ++ */ ++ ++ void *component; /* Component this port belongs to (Read Only) */ ++ ++ void *userdata; /* Field reserved for use by the client */ ++ ++ u32 capabilities; /* Flags describing the capabilities of a ++ * port (RO). Bitwise combination of \ref ++ * portcapabilities "Port capabilities" ++ * values. ++ */ ++ ++}; +diff -Nur linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-parameters.h linux-rpi/drivers/media/platform/bcm2835/mmal-parameters.h +--- linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-parameters.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/media/platform/bcm2835/mmal-parameters.h 2015-11-29 09:42:37.835237156 +0100 +@@ -0,0 +1,656 @@ ++/* ++ * Broadcom BM2835 V4L2 driver ++ * ++ * Copyright © 2013 Raspberry Pi (Trading) Ltd. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ * ++ * Authors: Vincent Sanders ++ * Dave Stevenson ++ * Simon Mellor ++ * Luke Diamand ++ */ ++ ++/* common parameters */ ++ ++/** @name Parameter groups ++ * Parameters are divided into groups, and then allocated sequentially within ++ * a group using an enum. ++ * @{ ++ */ ++ ++/** Common parameter ID group, used with many types of component. */ ++#define MMAL_PARAMETER_GROUP_COMMON (0<<16) ++/** Camera-specific parameter ID group. */ ++#define MMAL_PARAMETER_GROUP_CAMERA (1<<16) ++/** Video-specific parameter ID group. */ ++#define MMAL_PARAMETER_GROUP_VIDEO (2<<16) ++/** Audio-specific parameter ID group. */ ++#define MMAL_PARAMETER_GROUP_AUDIO (3<<16) ++/** Clock-specific parameter ID group. */ ++#define MMAL_PARAMETER_GROUP_CLOCK (4<<16) ++/** Miracast-specific parameter ID group. */ ++#define MMAL_PARAMETER_GROUP_MIRACAST (5<<16) ++ ++/* Common parameters */ ++enum mmal_parameter_common_type { ++ MMAL_PARAMETER_UNUSED /**< Never a valid parameter ID */ ++ = MMAL_PARAMETER_GROUP_COMMON, ++ MMAL_PARAMETER_SUPPORTED_ENCODINGS, /**< MMAL_PARAMETER_ENCODING_T */ ++ MMAL_PARAMETER_URI, /**< MMAL_PARAMETER_URI_T */ ++ ++ /** MMAL_PARAMETER_CHANGE_EVENT_REQUEST_T */ ++ MMAL_PARAMETER_CHANGE_EVENT_REQUEST, ++ ++ /** MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_ZERO_COPY, ++ ++ /**< MMAL_PARAMETER_BUFFER_REQUIREMENTS_T */ ++ MMAL_PARAMETER_BUFFER_REQUIREMENTS, ++ ++ MMAL_PARAMETER_STATISTICS, /**< MMAL_PARAMETER_STATISTICS_T */ ++ MMAL_PARAMETER_CORE_STATISTICS, /**< MMAL_PARAMETER_CORE_STATISTICS_T */ ++ MMAL_PARAMETER_MEM_USAGE, /**< MMAL_PARAMETER_MEM_USAGE_T */ ++ MMAL_PARAMETER_BUFFER_FLAG_FILTER, /**< MMAL_PARAMETER_UINT32_T */ ++ MMAL_PARAMETER_SEEK, /**< MMAL_PARAMETER_SEEK_T */ ++ MMAL_PARAMETER_POWERMON_ENABLE, /**< MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_LOGGING, /**< MMAL_PARAMETER_LOGGING_T */ ++ MMAL_PARAMETER_SYSTEM_TIME, /**< MMAL_PARAMETER_UINT64_T */ ++ MMAL_PARAMETER_NO_IMAGE_PADDING /**< MMAL_PARAMETER_BOOLEAN_T */ ++}; ++ ++/* camera parameters */ ++ ++enum mmal_parameter_camera_type { ++ /* 0 */ ++ /** @ref MMAL_PARAMETER_THUMBNAIL_CONFIG_T */ ++ MMAL_PARAMETER_THUMBNAIL_CONFIGURATION ++ = MMAL_PARAMETER_GROUP_CAMERA, ++ MMAL_PARAMETER_CAPTURE_QUALITY, /**< Unused? */ ++ MMAL_PARAMETER_ROTATION, /**< @ref MMAL_PARAMETER_INT32_T */ ++ MMAL_PARAMETER_EXIF_DISABLE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_EXIF, /**< @ref MMAL_PARAMETER_EXIF_T */ ++ MMAL_PARAMETER_AWB_MODE, /**< @ref MMAL_PARAM_AWBMODE_T */ ++ MMAL_PARAMETER_IMAGE_EFFECT, /**< @ref MMAL_PARAMETER_IMAGEFX_T */ ++ MMAL_PARAMETER_COLOUR_EFFECT, /**< @ref MMAL_PARAMETER_COLOURFX_T */ ++ MMAL_PARAMETER_FLICKER_AVOID, /**< @ref MMAL_PARAMETER_FLICKERAVOID_T */ ++ MMAL_PARAMETER_FLASH, /**< @ref MMAL_PARAMETER_FLASH_T */ ++ MMAL_PARAMETER_REDEYE, /**< @ref MMAL_PARAMETER_REDEYE_T */ ++ MMAL_PARAMETER_FOCUS, /**< @ref MMAL_PARAMETER_FOCUS_T */ ++ MMAL_PARAMETER_FOCAL_LENGTHS, /**< Unused? */ ++ MMAL_PARAMETER_EXPOSURE_COMP, /**< @ref MMAL_PARAMETER_INT32_T */ ++ MMAL_PARAMETER_ZOOM, /**< @ref MMAL_PARAMETER_SCALEFACTOR_T */ ++ MMAL_PARAMETER_MIRROR, /**< @ref MMAL_PARAMETER_MIRROR_T */ ++ ++ /* 0x10 */ ++ MMAL_PARAMETER_CAMERA_NUM, /**< @ref MMAL_PARAMETER_UINT32_T */ ++ MMAL_PARAMETER_CAPTURE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_EXPOSURE_MODE, /**< @ref MMAL_PARAMETER_EXPOSUREMODE_T */ ++ MMAL_PARAMETER_EXP_METERING_MODE, /**< @ref MMAL_PARAMETER_EXPOSUREMETERINGMODE_T */ ++ MMAL_PARAMETER_FOCUS_STATUS, /**< @ref MMAL_PARAMETER_FOCUS_STATUS_T */ ++ MMAL_PARAMETER_CAMERA_CONFIG, /**< @ref MMAL_PARAMETER_CAMERA_CONFIG_T */ ++ MMAL_PARAMETER_CAPTURE_STATUS, /**< @ref MMAL_PARAMETER_CAPTURE_STATUS_T */ ++ MMAL_PARAMETER_FACE_TRACK, /**< @ref MMAL_PARAMETER_FACE_TRACK_T */ ++ MMAL_PARAMETER_DRAW_BOX_FACES_AND_FOCUS, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_JPEG_Q_FACTOR, /**< @ref MMAL_PARAMETER_UINT32_T */ ++ MMAL_PARAMETER_FRAME_RATE, /**< @ref MMAL_PARAMETER_FRAME_RATE_T */ ++ MMAL_PARAMETER_USE_STC, /**< @ref MMAL_PARAMETER_CAMERA_STC_MODE_T */ ++ MMAL_PARAMETER_CAMERA_INFO, /**< @ref MMAL_PARAMETER_CAMERA_INFO_T */ ++ MMAL_PARAMETER_VIDEO_STABILISATION, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_FACE_TRACK_RESULTS, /**< @ref MMAL_PARAMETER_FACE_TRACK_RESULTS_T */ ++ MMAL_PARAMETER_ENABLE_RAW_CAPTURE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ ++ ++ /* 0x20 */ ++ MMAL_PARAMETER_DPF_FILE, /**< @ref MMAL_PARAMETER_URI_T */ ++ MMAL_PARAMETER_ENABLE_DPF_FILE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_DPF_FAIL_IS_FATAL, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_CAPTURE_MODE, /**< @ref MMAL_PARAMETER_CAPTUREMODE_T */ ++ MMAL_PARAMETER_FOCUS_REGIONS, /**< @ref MMAL_PARAMETER_FOCUS_REGIONS_T */ ++ MMAL_PARAMETER_INPUT_CROP, /**< @ref MMAL_PARAMETER_INPUT_CROP_T */ ++ MMAL_PARAMETER_SENSOR_INFORMATION, /**< @ref MMAL_PARAMETER_SENSOR_INFORMATION_T */ ++ MMAL_PARAMETER_FLASH_SELECT, /**< @ref MMAL_PARAMETER_FLASH_SELECT_T */ ++ MMAL_PARAMETER_FIELD_OF_VIEW, /**< @ref MMAL_PARAMETER_FIELD_OF_VIEW_T */ ++ MMAL_PARAMETER_HIGH_DYNAMIC_RANGE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_DYNAMIC_RANGE_COMPRESSION, /**< @ref MMAL_PARAMETER_DRC_T */ ++ MMAL_PARAMETER_ALGORITHM_CONTROL, /**< @ref MMAL_PARAMETER_ALGORITHM_CONTROL_T */ ++ MMAL_PARAMETER_SHARPNESS, /**< @ref MMAL_PARAMETER_RATIONAL_T */ ++ MMAL_PARAMETER_CONTRAST, /**< @ref MMAL_PARAMETER_RATIONAL_T */ ++ MMAL_PARAMETER_BRIGHTNESS, /**< @ref MMAL_PARAMETER_RATIONAL_T */ ++ MMAL_PARAMETER_SATURATION, /**< @ref MMAL_PARAMETER_RATIONAL_T */ ++ ++ /* 0x30 */ ++ MMAL_PARAMETER_ISO, /**< @ref MMAL_PARAMETER_UINT32_T */ ++ MMAL_PARAMETER_ANTISHAKE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ ++ ++ /** @ref MMAL_PARAMETER_IMAGEFX_PARAMETERS_T */ ++ MMAL_PARAMETER_IMAGE_EFFECT_PARAMETERS, ++ ++ /** @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_CAMERA_BURST_CAPTURE, ++ ++ /** @ref MMAL_PARAMETER_UINT32_T */ ++ MMAL_PARAMETER_CAMERA_MIN_ISO, ++ ++ /** @ref MMAL_PARAMETER_CAMERA_USE_CASE_T */ ++ MMAL_PARAMETER_CAMERA_USE_CASE, ++ ++ /**< @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_CAPTURE_STATS_PASS, ++ ++ /** @ref MMAL_PARAMETER_UINT32_T */ ++ MMAL_PARAMETER_CAMERA_CUSTOM_SENSOR_CONFIG, ++ ++ /** @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_ENABLE_REGISTER_FILE, ++ ++ /** @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_REGISTER_FAIL_IS_FATAL, ++ ++ /** @ref MMAL_PARAMETER_CONFIGFILE_T */ ++ MMAL_PARAMETER_CONFIGFILE_REGISTERS, ++ ++ /** @ref MMAL_PARAMETER_CONFIGFILE_CHUNK_T */ ++ MMAL_PARAMETER_CONFIGFILE_CHUNK_REGISTERS, ++ MMAL_PARAMETER_JPEG_ATTACH_LOG, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_ZERO_SHUTTER_LAG, /**< @ref MMAL_PARAMETER_ZEROSHUTTERLAG_T */ ++ MMAL_PARAMETER_FPS_RANGE, /**< @ref MMAL_PARAMETER_FPS_RANGE_T */ ++ MMAL_PARAMETER_CAPTURE_EXPOSURE_COMP, /**< @ref MMAL_PARAMETER_INT32_T */ ++ ++ /* 0x40 */ ++ MMAL_PARAMETER_SW_SHARPEN_DISABLE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_FLASH_REQUIRED, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_SW_SATURATION_DISABLE, /**< @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_SHUTTER_SPEED, /**< Takes a @ref MMAL_PARAMETER_UINT32_T */ ++ MMAL_PARAMETER_CUSTOM_AWB_GAINS, /**< Takes a @ref MMAL_PARAMETER_AWB_GAINS_T */ ++}; ++ ++struct mmal_parameter_rational { ++ s32 num; /**< Numerator */ ++ s32 den; /**< Denominator */ ++}; ++ ++enum mmal_parameter_camera_config_timestamp_mode { ++ MMAL_PARAM_TIMESTAMP_MODE_ZERO = 0, /* Always timestamp frames as 0 */ ++ MMAL_PARAM_TIMESTAMP_MODE_RAW_STC, /* Use the raw STC value ++ * for the frame timestamp ++ */ ++ MMAL_PARAM_TIMESTAMP_MODE_RESET_STC, /* Use the STC timestamp ++ * but subtract the ++ * timestamp of the first ++ * frame sent to give a ++ * zero based timestamp. ++ */ ++}; ++ ++struct mmal_parameter_fps_range { ++ /**< Low end of the permitted framerate range */ ++ struct mmal_parameter_rational fps_low; ++ /**< High end of the permitted framerate range */ ++ struct mmal_parameter_rational fps_high; ++}; ++ ++ ++/* camera configuration parameter */ ++struct mmal_parameter_camera_config { ++ /* Parameters for setting up the image pools */ ++ u32 max_stills_w; /* Max size of stills capture */ ++ u32 max_stills_h; ++ u32 stills_yuv422; /* Allow YUV422 stills capture */ ++ u32 one_shot_stills; /* Continuous or one shot stills captures. */ ++ ++ u32 max_preview_video_w; /* Max size of the preview or video ++ * capture frames ++ */ ++ u32 max_preview_video_h; ++ u32 num_preview_video_frames; ++ ++ /** Sets the height of the circular buffer for stills capture. */ ++ u32 stills_capture_circular_buffer_height; ++ ++ /** Allows preview/encode to resume as fast as possible after the stills ++ * input frame has been received, and then processes the still frame in ++ * the background whilst preview/encode has resumed. ++ * Actual mode is controlled by MMAL_PARAMETER_CAPTURE_MODE. ++ */ ++ u32 fast_preview_resume; ++ ++ /** Selects algorithm for timestamping frames if ++ * there is no clock component connected. ++ * enum mmal_parameter_camera_config_timestamp_mode ++ */ ++ s32 use_stc_timestamp; ++}; ++ ++ ++enum mmal_parameter_exposuremode { ++ MMAL_PARAM_EXPOSUREMODE_OFF, ++ MMAL_PARAM_EXPOSUREMODE_AUTO, ++ MMAL_PARAM_EXPOSUREMODE_NIGHT, ++ MMAL_PARAM_EXPOSUREMODE_NIGHTPREVIEW, ++ MMAL_PARAM_EXPOSUREMODE_BACKLIGHT, ++ MMAL_PARAM_EXPOSUREMODE_SPOTLIGHT, ++ MMAL_PARAM_EXPOSUREMODE_SPORTS, ++ MMAL_PARAM_EXPOSUREMODE_SNOW, ++ MMAL_PARAM_EXPOSUREMODE_BEACH, ++ MMAL_PARAM_EXPOSUREMODE_VERYLONG, ++ MMAL_PARAM_EXPOSUREMODE_FIXEDFPS, ++ MMAL_PARAM_EXPOSUREMODE_ANTISHAKE, ++ MMAL_PARAM_EXPOSUREMODE_FIREWORKS, ++}; ++ ++enum mmal_parameter_exposuremeteringmode { ++ MMAL_PARAM_EXPOSUREMETERINGMODE_AVERAGE, ++ MMAL_PARAM_EXPOSUREMETERINGMODE_SPOT, ++ MMAL_PARAM_EXPOSUREMETERINGMODE_BACKLIT, ++ MMAL_PARAM_EXPOSUREMETERINGMODE_MATRIX, ++}; ++ ++enum mmal_parameter_awbmode { ++ MMAL_PARAM_AWBMODE_OFF, ++ MMAL_PARAM_AWBMODE_AUTO, ++ MMAL_PARAM_AWBMODE_SUNLIGHT, ++ MMAL_PARAM_AWBMODE_CLOUDY, ++ MMAL_PARAM_AWBMODE_SHADE, ++ MMAL_PARAM_AWBMODE_TUNGSTEN, ++ MMAL_PARAM_AWBMODE_FLUORESCENT, ++ MMAL_PARAM_AWBMODE_INCANDESCENT, ++ MMAL_PARAM_AWBMODE_FLASH, ++ MMAL_PARAM_AWBMODE_HORIZON, ++}; ++ ++enum mmal_parameter_imagefx { ++ MMAL_PARAM_IMAGEFX_NONE, ++ MMAL_PARAM_IMAGEFX_NEGATIVE, ++ MMAL_PARAM_IMAGEFX_SOLARIZE, ++ MMAL_PARAM_IMAGEFX_POSTERIZE, ++ MMAL_PARAM_IMAGEFX_WHITEBOARD, ++ MMAL_PARAM_IMAGEFX_BLACKBOARD, ++ MMAL_PARAM_IMAGEFX_SKETCH, ++ MMAL_PARAM_IMAGEFX_DENOISE, ++ MMAL_PARAM_IMAGEFX_EMBOSS, ++ MMAL_PARAM_IMAGEFX_OILPAINT, ++ MMAL_PARAM_IMAGEFX_HATCH, ++ MMAL_PARAM_IMAGEFX_GPEN, ++ MMAL_PARAM_IMAGEFX_PASTEL, ++ MMAL_PARAM_IMAGEFX_WATERCOLOUR, ++ MMAL_PARAM_IMAGEFX_FILM, ++ MMAL_PARAM_IMAGEFX_BLUR, ++ MMAL_PARAM_IMAGEFX_SATURATION, ++ MMAL_PARAM_IMAGEFX_COLOURSWAP, ++ MMAL_PARAM_IMAGEFX_WASHEDOUT, ++ MMAL_PARAM_IMAGEFX_POSTERISE, ++ MMAL_PARAM_IMAGEFX_COLOURPOINT, ++ MMAL_PARAM_IMAGEFX_COLOURBALANCE, ++ MMAL_PARAM_IMAGEFX_CARTOON, ++}; ++ ++enum MMAL_PARAM_FLICKERAVOID_T { ++ MMAL_PARAM_FLICKERAVOID_OFF, ++ MMAL_PARAM_FLICKERAVOID_AUTO, ++ MMAL_PARAM_FLICKERAVOID_50HZ, ++ MMAL_PARAM_FLICKERAVOID_60HZ, ++ MMAL_PARAM_FLICKERAVOID_MAX = 0x7FFFFFFF ++}; ++ ++struct mmal_parameter_awbgains { ++ struct mmal_parameter_rational r_gain; /**< Red gain */ ++ struct mmal_parameter_rational b_gain; /**< Blue gain */ ++}; ++ ++/** Manner of video rate control */ ++enum mmal_parameter_rate_control_mode { ++ MMAL_VIDEO_RATECONTROL_DEFAULT, ++ MMAL_VIDEO_RATECONTROL_VARIABLE, ++ MMAL_VIDEO_RATECONTROL_CONSTANT, ++ MMAL_VIDEO_RATECONTROL_VARIABLE_SKIP_FRAMES, ++ MMAL_VIDEO_RATECONTROL_CONSTANT_SKIP_FRAMES ++}; ++ ++enum mmal_video_profile { ++ MMAL_VIDEO_PROFILE_H263_BASELINE, ++ MMAL_VIDEO_PROFILE_H263_H320CODING, ++ MMAL_VIDEO_PROFILE_H263_BACKWARDCOMPATIBLE, ++ MMAL_VIDEO_PROFILE_H263_ISWV2, ++ MMAL_VIDEO_PROFILE_H263_ISWV3, ++ MMAL_VIDEO_PROFILE_H263_HIGHCOMPRESSION, ++ MMAL_VIDEO_PROFILE_H263_INTERNET, ++ MMAL_VIDEO_PROFILE_H263_INTERLACE, ++ MMAL_VIDEO_PROFILE_H263_HIGHLATENCY, ++ MMAL_VIDEO_PROFILE_MP4V_SIMPLE, ++ MMAL_VIDEO_PROFILE_MP4V_SIMPLESCALABLE, ++ MMAL_VIDEO_PROFILE_MP4V_CORE, ++ MMAL_VIDEO_PROFILE_MP4V_MAIN, ++ MMAL_VIDEO_PROFILE_MP4V_NBIT, ++ MMAL_VIDEO_PROFILE_MP4V_SCALABLETEXTURE, ++ MMAL_VIDEO_PROFILE_MP4V_SIMPLEFACE, ++ MMAL_VIDEO_PROFILE_MP4V_SIMPLEFBA, ++ MMAL_VIDEO_PROFILE_MP4V_BASICANIMATED, ++ MMAL_VIDEO_PROFILE_MP4V_HYBRID, ++ MMAL_VIDEO_PROFILE_MP4V_ADVANCEDREALTIME, ++ MMAL_VIDEO_PROFILE_MP4V_CORESCALABLE, ++ MMAL_VIDEO_PROFILE_MP4V_ADVANCEDCODING, ++ MMAL_VIDEO_PROFILE_MP4V_ADVANCEDCORE, ++ MMAL_VIDEO_PROFILE_MP4V_ADVANCEDSCALABLE, ++ MMAL_VIDEO_PROFILE_MP4V_ADVANCEDSIMPLE, ++ MMAL_VIDEO_PROFILE_H264_BASELINE, ++ MMAL_VIDEO_PROFILE_H264_MAIN, ++ MMAL_VIDEO_PROFILE_H264_EXTENDED, ++ MMAL_VIDEO_PROFILE_H264_HIGH, ++ MMAL_VIDEO_PROFILE_H264_HIGH10, ++ MMAL_VIDEO_PROFILE_H264_HIGH422, ++ MMAL_VIDEO_PROFILE_H264_HIGH444, ++ MMAL_VIDEO_PROFILE_H264_CONSTRAINED_BASELINE, ++ MMAL_VIDEO_PROFILE_DUMMY = 0x7FFFFFFF ++}; ++ ++enum mmal_video_level { ++ MMAL_VIDEO_LEVEL_H263_10, ++ MMAL_VIDEO_LEVEL_H263_20, ++ MMAL_VIDEO_LEVEL_H263_30, ++ MMAL_VIDEO_LEVEL_H263_40, ++ MMAL_VIDEO_LEVEL_H263_45, ++ MMAL_VIDEO_LEVEL_H263_50, ++ MMAL_VIDEO_LEVEL_H263_60, ++ MMAL_VIDEO_LEVEL_H263_70, ++ MMAL_VIDEO_LEVEL_MP4V_0, ++ MMAL_VIDEO_LEVEL_MP4V_0b, ++ MMAL_VIDEO_LEVEL_MP4V_1, ++ MMAL_VIDEO_LEVEL_MP4V_2, ++ MMAL_VIDEO_LEVEL_MP4V_3, ++ MMAL_VIDEO_LEVEL_MP4V_4, ++ MMAL_VIDEO_LEVEL_MP4V_4a, ++ MMAL_VIDEO_LEVEL_MP4V_5, ++ MMAL_VIDEO_LEVEL_MP4V_6, ++ MMAL_VIDEO_LEVEL_H264_1, ++ MMAL_VIDEO_LEVEL_H264_1b, ++ MMAL_VIDEO_LEVEL_H264_11, ++ MMAL_VIDEO_LEVEL_H264_12, ++ MMAL_VIDEO_LEVEL_H264_13, ++ MMAL_VIDEO_LEVEL_H264_2, ++ MMAL_VIDEO_LEVEL_H264_21, ++ MMAL_VIDEO_LEVEL_H264_22, ++ MMAL_VIDEO_LEVEL_H264_3, ++ MMAL_VIDEO_LEVEL_H264_31, ++ MMAL_VIDEO_LEVEL_H264_32, ++ MMAL_VIDEO_LEVEL_H264_4, ++ MMAL_VIDEO_LEVEL_H264_41, ++ MMAL_VIDEO_LEVEL_H264_42, ++ MMAL_VIDEO_LEVEL_H264_5, ++ MMAL_VIDEO_LEVEL_H264_51, ++ MMAL_VIDEO_LEVEL_DUMMY = 0x7FFFFFFF ++}; ++ ++struct mmal_parameter_video_profile { ++ enum mmal_video_profile profile; ++ enum mmal_video_level level; ++}; ++ ++/* video parameters */ ++ ++enum mmal_parameter_video_type { ++ /** @ref MMAL_DISPLAYREGION_T */ ++ MMAL_PARAMETER_DISPLAYREGION = MMAL_PARAMETER_GROUP_VIDEO, ++ ++ /** @ref MMAL_PARAMETER_VIDEO_PROFILE_T */ ++ MMAL_PARAMETER_SUPPORTED_PROFILES, ++ ++ /** @ref MMAL_PARAMETER_VIDEO_PROFILE_T */ ++ MMAL_PARAMETER_PROFILE, ++ ++ /** @ref MMAL_PARAMETER_UINT32_T */ ++ MMAL_PARAMETER_INTRAPERIOD, ++ ++ /** @ref MMAL_PARAMETER_VIDEO_RATECONTROL_T */ ++ MMAL_PARAMETER_RATECONTROL, ++ ++ /** @ref MMAL_PARAMETER_VIDEO_NALUNITFORMAT_T */ ++ MMAL_PARAMETER_NALUNITFORMAT, ++ ++ /** @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_MINIMISE_FRAGMENTATION, ++ ++ /** @ref MMAL_PARAMETER_UINT32_T. ++ * Setting the value to zero resets to the default (one slice per frame). ++ */ ++ MMAL_PARAMETER_MB_ROWS_PER_SLICE, ++ ++ /** @ref MMAL_PARAMETER_VIDEO_LEVEL_EXTENSION_T */ ++ MMAL_PARAMETER_VIDEO_LEVEL_EXTENSION, ++ ++ /** @ref MMAL_PARAMETER_VIDEO_EEDE_ENABLE_T */ ++ MMAL_PARAMETER_VIDEO_EEDE_ENABLE, ++ ++ /** @ref MMAL_PARAMETER_VIDEO_EEDE_LOSSRATE_T */ ++ MMAL_PARAMETER_VIDEO_EEDE_LOSSRATE, ++ ++ /** @ref MMAL_PARAMETER_BOOLEAN_T. Request an I-frame. */ ++ MMAL_PARAMETER_VIDEO_REQUEST_I_FRAME, ++ /** @ref MMAL_PARAMETER_VIDEO_INTRA_REFRESH_T */ ++ MMAL_PARAMETER_VIDEO_INTRA_REFRESH, ++ ++ /** @ref MMAL_PARAMETER_BOOLEAN_T. */ ++ MMAL_PARAMETER_VIDEO_IMMUTABLE_INPUT, ++ ++ /** @ref MMAL_PARAMETER_UINT32_T. Run-time bit rate control */ ++ MMAL_PARAMETER_VIDEO_BIT_RATE, ++ ++ /** @ref MMAL_PARAMETER_FRAME_RATE_T */ ++ MMAL_PARAMETER_VIDEO_FRAME_RATE, ++ ++ /** @ref MMAL_PARAMETER_UINT32_T. */ ++ MMAL_PARAMETER_VIDEO_ENCODE_MIN_QUANT, ++ ++ /** @ref MMAL_PARAMETER_UINT32_T. */ ++ MMAL_PARAMETER_VIDEO_ENCODE_MAX_QUANT, ++ ++ /** @ref MMAL_PARAMETER_VIDEO_ENCODE_RC_MODEL_T. */ ++ MMAL_PARAMETER_VIDEO_ENCODE_RC_MODEL, ++ ++ MMAL_PARAMETER_EXTRA_BUFFERS, /**< @ref MMAL_PARAMETER_UINT32_T. */ ++ /** @ref MMAL_PARAMETER_UINT32_T. ++ * Changing this parameter from the default can reduce frame rate ++ * because image buffers need to be re-pitched. ++ */ ++ MMAL_PARAMETER_VIDEO_ALIGN_HORIZ, ++ ++ /** @ref MMAL_PARAMETER_UINT32_T. ++ * Changing this parameter from the default can reduce frame rate ++ * because image buffers need to be re-pitched. ++ */ ++ MMAL_PARAMETER_VIDEO_ALIGN_VERT, ++ ++ /** @ref MMAL_PARAMETER_BOOLEAN_T. */ ++ MMAL_PARAMETER_VIDEO_DROPPABLE_PFRAMES, ++ ++ /** @ref MMAL_PARAMETER_UINT32_T. */ ++ MMAL_PARAMETER_VIDEO_ENCODE_INITIAL_QUANT, ++ ++ /**< @ref MMAL_PARAMETER_UINT32_T. */ ++ MMAL_PARAMETER_VIDEO_ENCODE_QP_P, ++ ++ /**< @ref MMAL_PARAMETER_UINT32_T. */ ++ MMAL_PARAMETER_VIDEO_ENCODE_RC_SLICE_DQUANT, ++ ++ /** @ref MMAL_PARAMETER_UINT32_T */ ++ MMAL_PARAMETER_VIDEO_ENCODE_FRAME_LIMIT_BITS, ++ ++ /** @ref MMAL_PARAMETER_UINT32_T. */ ++ MMAL_PARAMETER_VIDEO_ENCODE_PEAK_RATE, ++ ++ /* H264 specific parameters */ ++ ++ /** @ref MMAL_PARAMETER_BOOLEAN_T. */ ++ MMAL_PARAMETER_VIDEO_ENCODE_H264_DISABLE_CABAC, ++ ++ /** @ref MMAL_PARAMETER_BOOLEAN_T. */ ++ MMAL_PARAMETER_VIDEO_ENCODE_H264_LOW_LATENCY, ++ ++ /** @ref MMAL_PARAMETER_BOOLEAN_T. */ ++ MMAL_PARAMETER_VIDEO_ENCODE_H264_AU_DELIMITERS, ++ ++ /** @ref MMAL_PARAMETER_UINT32_T. */ ++ MMAL_PARAMETER_VIDEO_ENCODE_H264_DEBLOCK_IDC, ++ ++ /** @ref MMAL_PARAMETER_VIDEO_ENCODER_H264_MB_INTRA_MODES_T. */ ++ MMAL_PARAMETER_VIDEO_ENCODE_H264_MB_INTRA_MODE, ++ ++ /** @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_VIDEO_ENCODE_HEADER_ON_OPEN, ++ ++ /** @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_VIDEO_ENCODE_PRECODE_FOR_QP, ++ ++ /** @ref MMAL_PARAMETER_VIDEO_DRM_INIT_INFO_T. */ ++ MMAL_PARAMETER_VIDEO_DRM_INIT_INFO, ++ ++ /** @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_VIDEO_TIMESTAMP_FIFO, ++ ++ /** @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_VIDEO_DECODE_ERROR_CONCEALMENT, ++ ++ /** @ref MMAL_PARAMETER_VIDEO_DRM_PROTECT_BUFFER_T. */ ++ MMAL_PARAMETER_VIDEO_DRM_PROTECT_BUFFER, ++ ++ /** @ref MMAL_PARAMETER_BYTES_T */ ++ MMAL_PARAMETER_VIDEO_DECODE_CONFIG_VD3, ++ ++ /**< @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_VIDEO_ENCODE_H264_VCL_HRD_PARAMETERS, ++ ++ /**< @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_VIDEO_ENCODE_H264_LOW_DELAY_HRD_FLAG, ++ ++ /**< @ref MMAL_PARAMETER_BOOLEAN_T */ ++ MMAL_PARAMETER_VIDEO_ENCODE_INLINE_HEADER ++}; ++ ++/** Valid mirror modes */ ++enum mmal_parameter_mirror { ++ MMAL_PARAM_MIRROR_NONE, ++ MMAL_PARAM_MIRROR_VERTICAL, ++ MMAL_PARAM_MIRROR_HORIZONTAL, ++ MMAL_PARAM_MIRROR_BOTH, ++}; ++ ++enum mmal_parameter_displaytransform { ++ MMAL_DISPLAY_ROT0 = 0, ++ MMAL_DISPLAY_MIRROR_ROT0 = 1, ++ MMAL_DISPLAY_MIRROR_ROT180 = 2, ++ MMAL_DISPLAY_ROT180 = 3, ++ MMAL_DISPLAY_MIRROR_ROT90 = 4, ++ MMAL_DISPLAY_ROT270 = 5, ++ MMAL_DISPLAY_ROT90 = 6, ++ MMAL_DISPLAY_MIRROR_ROT270 = 7, ++}; ++ ++enum mmal_parameter_displaymode { ++ MMAL_DISPLAY_MODE_FILL = 0, ++ MMAL_DISPLAY_MODE_LETTERBOX = 1, ++}; ++ ++enum mmal_parameter_displayset { ++ MMAL_DISPLAY_SET_NONE = 0, ++ MMAL_DISPLAY_SET_NUM = 1, ++ MMAL_DISPLAY_SET_FULLSCREEN = 2, ++ MMAL_DISPLAY_SET_TRANSFORM = 4, ++ MMAL_DISPLAY_SET_DEST_RECT = 8, ++ MMAL_DISPLAY_SET_SRC_RECT = 0x10, ++ MMAL_DISPLAY_SET_MODE = 0x20, ++ MMAL_DISPLAY_SET_PIXEL = 0x40, ++ MMAL_DISPLAY_SET_NOASPECT = 0x80, ++ MMAL_DISPLAY_SET_LAYER = 0x100, ++ MMAL_DISPLAY_SET_COPYPROTECT = 0x200, ++ MMAL_DISPLAY_SET_ALPHA = 0x400, ++}; ++ ++struct mmal_parameter_displayregion { ++ /** Bitfield that indicates which fields are set and should be ++ * used. All other fields will maintain their current value. ++ * \ref MMAL_DISPLAYSET_T defines the bits that can be ++ * combined. ++ */ ++ u32 set; ++ ++ /** Describes the display output device, with 0 typically ++ * being a directly connected LCD display. The actual values ++ * will depend on the hardware. Code using hard-wired numbers ++ * (e.g. 2) is certain to fail. ++ */ ++ ++ u32 display_num; ++ /** Indicates that we are using the full device screen area, ++ * rather than a window of the display. If zero, then ++ * dest_rect is used to specify a region of the display to ++ * use. ++ */ ++ ++ s32 fullscreen; ++ /** Indicates any rotation or flipping used to map frames onto ++ * the natural display orientation. ++ */ ++ u32 transform; /* enum mmal_parameter_displaytransform */ ++ ++ /** Where to display the frame within the screen, if ++ * fullscreen is zero. ++ */ ++ struct vchiq_mmal_rect dest_rect; ++ ++ /** Indicates which area of the frame to display. If all ++ * values are zero, the whole frame will be used. ++ */ ++ struct vchiq_mmal_rect src_rect; ++ ++ /** If set to non-zero, indicates that any display scaling ++ * should disregard the aspect ratio of the frame region being ++ * displayed. ++ */ ++ s32 noaspect; ++ ++ /** Indicates how the image should be scaled to fit the ++ * display. \code MMAL_DISPLAY_MODE_FILL \endcode indicates ++ * that the image should fill the screen by potentially ++ * cropping the frames. Setting \code mode \endcode to \code ++ * MMAL_DISPLAY_MODE_LETTERBOX \endcode indicates that all the ++ * source region should be displayed and black bars added if ++ * necessary. ++ */ ++ u32 mode; /* enum mmal_parameter_displaymode */ ++ ++ /** If non-zero, defines the width of a source pixel relative ++ * to \code pixel_y \endcode. If zero, then pixels default to ++ * being square. ++ */ ++ u32 pixel_x; ++ ++ /** If non-zero, defines the height of a source pixel relative ++ * to \code pixel_x \endcode. If zero, then pixels default to ++ * being square. ++ */ ++ u32 pixel_y; ++ ++ /** Sets the relative depth of the images, with greater values ++ * being in front of smaller values. ++ */ ++ u32 layer; ++ ++ /** Set to non-zero to ensure copy protection is used on ++ * output. ++ */ ++ s32 copyprotect_required; ++ ++ /** Level of opacity of the layer, where zero is fully ++ * transparent and 255 is fully opaque. ++ */ ++ u32 alpha; ++}; ++ ++#define MMAL_MAX_IMAGEFX_PARAMETERS 5 ++ ++struct mmal_parameter_imagefx_parameters { ++ enum mmal_parameter_imagefx effect; ++ u32 num_effect_params; ++ u32 effect_parameter[MMAL_MAX_IMAGEFX_PARAMETERS]; ++}; +diff -Nur linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-vchiq.c linux-rpi/drivers/media/platform/bcm2835/mmal-vchiq.c +--- linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-vchiq.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/media/platform/bcm2835/mmal-vchiq.c 2015-11-29 09:42:37.835237156 +0100 +@@ -0,0 +1,1916 @@ ++/* ++ * Broadcom BM2835 V4L2 driver ++ * ++ * Copyright © 2013 Raspberry Pi (Trading) Ltd. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ * ++ * Authors: Vincent Sanders ++ * Dave Stevenson ++ * Simon Mellor ++ * Luke Diamand ++ * ++ * V4L2 driver MMAL vchiq interface code ++ */ ++ ++#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mmal-common.h" ++#include "mmal-vchiq.h" ++#include "mmal-msg.h" ++ ++#define USE_VCHIQ_ARM ++#include "interface/vchi/vchi.h" ++ ++/* maximum number of components supported */ ++#define VCHIQ_MMAL_MAX_COMPONENTS 4 ++ ++/*#define FULL_MSG_DUMP 1*/ ++ ++#ifdef DEBUG ++static const char *const msg_type_names[] = { ++ "UNKNOWN", ++ "QUIT", ++ "SERVICE_CLOSED", ++ "GET_VERSION", ++ "COMPONENT_CREATE", ++ "COMPONENT_DESTROY", ++ "COMPONENT_ENABLE", ++ "COMPONENT_DISABLE", ++ "PORT_INFO_GET", ++ "PORT_INFO_SET", ++ "PORT_ACTION", ++ "BUFFER_FROM_HOST", ++ "BUFFER_TO_HOST", ++ "GET_STATS", ++ "PORT_PARAMETER_SET", ++ "PORT_PARAMETER_GET", ++ "EVENT_TO_HOST", ++ "GET_CORE_STATS_FOR_PORT", ++ "OPAQUE_ALLOCATOR", ++ "CONSUME_MEM", ++ "LMK", ++ "OPAQUE_ALLOCATOR_DESC", ++ "DRM_GET_LHS32", ++ "DRM_GET_TIME", ++ "BUFFER_FROM_HOST_ZEROLEN", ++ "PORT_FLUSH", ++ "HOST_LOG", ++}; ++#endif ++ ++static const char *const port_action_type_names[] = { ++ "UNKNOWN", ++ "ENABLE", ++ "DISABLE", ++ "FLUSH", ++ "CONNECT", ++ "DISCONNECT", ++ "SET_REQUIREMENTS", ++}; ++ ++#if defined(DEBUG) ++#if defined(FULL_MSG_DUMP) ++#define DBG_DUMP_MSG(MSG, MSG_LEN, TITLE) \ ++ do { \ ++ pr_debug(TITLE" type:%s(%d) length:%d\n", \ ++ msg_type_names[(MSG)->h.type], \ ++ (MSG)->h.type, (MSG_LEN)); \ ++ print_hex_dump(KERN_DEBUG, "<h.type], \ ++ (MSG)->h.type, (MSG_LEN)); \ ++ } ++#endif ++#else ++#define DBG_DUMP_MSG(MSG, MSG_LEN, TITLE) ++#endif ++ ++/* normal message context */ ++struct mmal_msg_context { ++ union { ++ struct { ++ /* work struct for defered callback - must come first */ ++ struct work_struct work; ++ /* mmal instance */ ++ struct vchiq_mmal_instance *instance; ++ /* mmal port */ ++ struct vchiq_mmal_port *port; ++ /* actual buffer used to store bulk reply */ ++ struct mmal_buffer *buffer; ++ /* amount of buffer used */ ++ unsigned long buffer_used; ++ /* MMAL buffer flags */ ++ u32 mmal_flags; ++ /* Presentation and Decode timestamps */ ++ s64 pts; ++ s64 dts; ++ ++ int status; /* context status */ ++ ++ } bulk; /* bulk data */ ++ ++ struct { ++ /* message handle to release */ ++ VCHI_HELD_MSG_T msg_handle; ++ /* pointer to received message */ ++ struct mmal_msg *msg; ++ /* received message length */ ++ u32 msg_len; ++ /* completion upon reply */ ++ struct completion cmplt; ++ } sync; /* synchronous response */ ++ } u; ++ ++}; ++ ++struct vchiq_mmal_instance { ++ VCHI_SERVICE_HANDLE_T handle; ++ ++ /* ensure serialised access to service */ ++ struct mutex vchiq_mutex; ++ ++ /* ensure serialised access to bulk operations */ ++ struct mutex bulk_mutex; ++ ++ /* vmalloc page to receive scratch bulk xfers into */ ++ void *bulk_scratch; ++ ++ /* component to use next */ ++ int component_idx; ++ struct vchiq_mmal_component component[VCHIQ_MMAL_MAX_COMPONENTS]; ++}; ++ ++static struct mmal_msg_context *get_msg_context(struct vchiq_mmal_instance ++ *instance) ++{ ++ struct mmal_msg_context *msg_context; ++ ++ /* todo: should this be allocated from a pool to avoid kmalloc */ ++ msg_context = kmalloc(sizeof(*msg_context), GFP_KERNEL); ++ memset(msg_context, 0, sizeof(*msg_context)); ++ ++ return msg_context; ++} ++ ++static void release_msg_context(struct mmal_msg_context *msg_context) ++{ ++ kfree(msg_context); ++} ++ ++/* deals with receipt of event to host message */ ++static void event_to_host_cb(struct vchiq_mmal_instance *instance, ++ struct mmal_msg *msg, u32 msg_len) ++{ ++ pr_debug("unhandled event\n"); ++ pr_debug("component:%p port type:%d num:%d cmd:0x%x length:%d\n", ++ msg->u.event_to_host.client_component, ++ msg->u.event_to_host.port_type, ++ msg->u.event_to_host.port_num, ++ msg->u.event_to_host.cmd, msg->u.event_to_host.length); ++} ++ ++/* workqueue scheduled callback ++ * ++ * we do this because it is important we do not call any other vchiq ++ * sync calls from witin the message delivery thread ++ */ ++static void buffer_work_cb(struct work_struct *work) ++{ ++ struct mmal_msg_context *msg_context = (struct mmal_msg_context *)work; ++ ++ msg_context->u.bulk.port->buffer_cb(msg_context->u.bulk.instance, ++ msg_context->u.bulk.port, ++ msg_context->u.bulk.status, ++ msg_context->u.bulk.buffer, ++ msg_context->u.bulk.buffer_used, ++ msg_context->u.bulk.mmal_flags, ++ msg_context->u.bulk.dts, ++ msg_context->u.bulk.pts); ++ ++ /* release message context */ ++ release_msg_context(msg_context); ++} ++ ++/* enqueue a bulk receive for a given message context */ ++static int bulk_receive(struct vchiq_mmal_instance *instance, ++ struct mmal_msg *msg, ++ struct mmal_msg_context *msg_context) ++{ ++ unsigned long rd_len; ++ unsigned long flags = 0; ++ int ret; ++ ++ /* bulk mutex stops other bulk operations while we have a ++ * receive in progress - released in callback ++ */ ++ ret = mutex_lock_interruptible(&instance->bulk_mutex); ++ if (ret != 0) ++ return ret; ++ ++ rd_len = msg->u.buffer_from_host.buffer_header.length; ++ ++ /* take buffer from queue */ ++ spin_lock_irqsave(&msg_context->u.bulk.port->slock, flags); ++ if (list_empty(&msg_context->u.bulk.port->buffers)) { ++ spin_unlock_irqrestore(&msg_context->u.bulk.port->slock, flags); ++ pr_err("buffer list empty trying to submit bulk receive\n"); ++ ++ /* todo: this is a serious error, we should never have ++ * commited a buffer_to_host operation to the mmal ++ * port without the buffer to back it up (underflow ++ * handling) and there is no obvious way to deal with ++ * this - how is the mmal servie going to react when ++ * we fail to do the xfer and reschedule a buffer when ++ * it arrives? perhaps a starved flag to indicate a ++ * waiting bulk receive? ++ */ ++ ++ mutex_unlock(&instance->bulk_mutex); ++ ++ return -EINVAL; ++ } ++ ++ msg_context->u.bulk.buffer = ++ list_entry(msg_context->u.bulk.port->buffers.next, ++ struct mmal_buffer, list); ++ list_del(&msg_context->u.bulk.buffer->list); ++ ++ spin_unlock_irqrestore(&msg_context->u.bulk.port->slock, flags); ++ ++ /* ensure we do not overrun the available buffer */ ++ if (rd_len > msg_context->u.bulk.buffer->buffer_size) { ++ rd_len = msg_context->u.bulk.buffer->buffer_size; ++ pr_warn("short read as not enough receive buffer space\n"); ++ /* todo: is this the correct response, what happens to ++ * the rest of the message data? ++ */ ++ } ++ ++ /* store length */ ++ msg_context->u.bulk.buffer_used = rd_len; ++ msg_context->u.bulk.mmal_flags = ++ msg->u.buffer_from_host.buffer_header.flags; ++ msg_context->u.bulk.dts = msg->u.buffer_from_host.buffer_header.dts; ++ msg_context->u.bulk.pts = msg->u.buffer_from_host.buffer_header.pts; ++ ++ // only need to flush L1 cache here, as VCHIQ takes care of the L2 ++ // cache. ++ __cpuc_flush_dcache_area(msg_context->u.bulk.buffer->buffer, rd_len); ++ ++ /* queue the bulk submission */ ++ vchi_service_use(instance->handle); ++ ret = vchi_bulk_queue_receive(instance->handle, ++ msg_context->u.bulk.buffer->buffer, ++ /* Actual receive needs to be a multiple ++ * of 4 bytes ++ */ ++ (rd_len + 3) & ~3, ++ VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE | ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, ++ msg_context); ++ ++ vchi_service_release(instance->handle); ++ ++ if (ret != 0) { ++ /* callback will not be clearing the mutex */ ++ mutex_unlock(&instance->bulk_mutex); ++ } ++ ++ return ret; ++} ++ ++/* enque a dummy bulk receive for a given message context */ ++static int dummy_bulk_receive(struct vchiq_mmal_instance *instance, ++ struct mmal_msg_context *msg_context) ++{ ++ int ret; ++ ++ /* bulk mutex stops other bulk operations while we have a ++ * receive in progress - released in callback ++ */ ++ ret = mutex_lock_interruptible(&instance->bulk_mutex); ++ if (ret != 0) ++ return ret; ++ ++ /* zero length indicates this was a dummy transfer */ ++ msg_context->u.bulk.buffer_used = 0; ++ ++ /* queue the bulk submission */ ++ vchi_service_use(instance->handle); ++ ++ ret = vchi_bulk_queue_receive(instance->handle, ++ instance->bulk_scratch, ++ 8, ++ VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE | ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, ++ msg_context); ++ ++ vchi_service_release(instance->handle); ++ ++ if (ret != 0) { ++ /* callback will not be clearing the mutex */ ++ mutex_unlock(&instance->bulk_mutex); ++ } ++ ++ return ret; ++} ++ ++/* data in message, memcpy from packet into output buffer */ ++static int inline_receive(struct vchiq_mmal_instance *instance, ++ struct mmal_msg *msg, ++ struct mmal_msg_context *msg_context) ++{ ++ unsigned long flags = 0; ++ ++ /* take buffer from queue */ ++ spin_lock_irqsave(&msg_context->u.bulk.port->slock, flags); ++ if (list_empty(&msg_context->u.bulk.port->buffers)) { ++ spin_unlock_irqrestore(&msg_context->u.bulk.port->slock, flags); ++ pr_err("buffer list empty trying to receive inline\n"); ++ ++ /* todo: this is a serious error, we should never have ++ * commited a buffer_to_host operation to the mmal ++ * port without the buffer to back it up (with ++ * underflow handling) and there is no obvious way to ++ * deal with this. Less bad than the bulk case as we ++ * can just drop this on the floor but...unhelpful ++ */ ++ return -EINVAL; ++ } ++ ++ msg_context->u.bulk.buffer = ++ list_entry(msg_context->u.bulk.port->buffers.next, ++ struct mmal_buffer, list); ++ list_del(&msg_context->u.bulk.buffer->list); ++ ++ spin_unlock_irqrestore(&msg_context->u.bulk.port->slock, flags); ++ ++ memcpy(msg_context->u.bulk.buffer->buffer, ++ msg->u.buffer_from_host.short_data, ++ msg->u.buffer_from_host.payload_in_message); ++ ++ msg_context->u.bulk.buffer_used = ++ msg->u.buffer_from_host.payload_in_message; ++ ++ return 0; ++} ++ ++/* queue the buffer availability with MMAL_MSG_TYPE_BUFFER_FROM_HOST */ ++static int ++buffer_from_host(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port, struct mmal_buffer *buf) ++{ ++ struct mmal_msg_context *msg_context; ++ struct mmal_msg m; ++ int ret; ++ ++ pr_debug("instance:%p buffer:%p\n", instance->handle, buf); ++ ++ /* bulk mutex stops other bulk operations while we ++ * have a receive in progress ++ */ ++ if (mutex_lock_interruptible(&instance->bulk_mutex)) ++ return -EINTR; ++ ++ /* get context */ ++ msg_context = get_msg_context(instance); ++ if (msg_context == NULL) ++ return -ENOMEM; ++ ++ /* store bulk message context for when data arrives */ ++ msg_context->u.bulk.instance = instance; ++ msg_context->u.bulk.port = port; ++ msg_context->u.bulk.buffer = NULL; /* not valid until bulk xfer */ ++ msg_context->u.bulk.buffer_used = 0; ++ ++ /* initialise work structure ready to schedule callback */ ++ INIT_WORK(&msg_context->u.bulk.work, buffer_work_cb); ++ ++ /* prep the buffer from host message */ ++ memset(&m, 0xbc, sizeof(m)); /* just to make debug clearer */ ++ ++ m.h.type = MMAL_MSG_TYPE_BUFFER_FROM_HOST; ++ m.h.magic = MMAL_MAGIC; ++ m.h.context = msg_context; ++ m.h.status = 0; ++ ++ /* drvbuf is our private data passed back */ ++ m.u.buffer_from_host.drvbuf.magic = MMAL_MAGIC; ++ m.u.buffer_from_host.drvbuf.component_handle = port->component->handle; ++ m.u.buffer_from_host.drvbuf.port_handle = port->handle; ++ m.u.buffer_from_host.drvbuf.client_context = msg_context; ++ ++ /* buffer header */ ++ m.u.buffer_from_host.buffer_header.cmd = 0; ++ m.u.buffer_from_host.buffer_header.data = buf->buffer; ++ m.u.buffer_from_host.buffer_header.alloc_size = buf->buffer_size; ++ m.u.buffer_from_host.buffer_header.length = 0; /* nothing used yet */ ++ m.u.buffer_from_host.buffer_header.offset = 0; /* no offset */ ++ m.u.buffer_from_host.buffer_header.flags = 0; /* no flags */ ++ m.u.buffer_from_host.buffer_header.pts = MMAL_TIME_UNKNOWN; ++ m.u.buffer_from_host.buffer_header.dts = MMAL_TIME_UNKNOWN; ++ ++ /* clear buffer type sepecific data */ ++ memset(&m.u.buffer_from_host.buffer_header_type_specific, 0, ++ sizeof(m.u.buffer_from_host.buffer_header_type_specific)); ++ ++ /* no payload in message */ ++ m.u.buffer_from_host.payload_in_message = 0; ++ ++ vchi_service_use(instance->handle); ++ ++ ret = vchi_msg_queue(instance->handle, &m, ++ sizeof(struct mmal_msg_header) + ++ sizeof(m.u.buffer_from_host), ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); ++ ++ if (ret != 0) { ++ release_msg_context(msg_context); ++ /* todo: is this correct error value? */ ++ } ++ ++ vchi_service_release(instance->handle); ++ ++ mutex_unlock(&instance->bulk_mutex); ++ ++ return ret; ++} ++ ++/* submit a buffer to the mmal sevice ++ * ++ * the buffer_from_host uses size data from the ports next available ++ * mmal_buffer and deals with there being no buffer available by ++ * incrementing the underflow for later ++ */ ++static int port_buffer_from_host(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port) ++{ ++ int ret; ++ struct mmal_buffer *buf; ++ unsigned long flags = 0; ++ ++ if (!port->enabled) ++ return -EINVAL; ++ ++ /* peek buffer from queue */ ++ spin_lock_irqsave(&port->slock, flags); ++ if (list_empty(&port->buffers)) { ++ port->buffer_underflow++; ++ spin_unlock_irqrestore(&port->slock, flags); ++ return -ENOSPC; ++ } ++ ++ buf = list_entry(port->buffers.next, struct mmal_buffer, list); ++ ++ spin_unlock_irqrestore(&port->slock, flags); ++ ++ /* issue buffer to mmal service */ ++ ret = buffer_from_host(instance, port, buf); ++ if (ret) { ++ pr_err("adding buffer header failed\n"); ++ /* todo: how should this be dealt with */ ++ } ++ ++ return ret; ++} ++ ++/* deals with receipt of buffer to host message */ ++static void buffer_to_host_cb(struct vchiq_mmal_instance *instance, ++ struct mmal_msg *msg, u32 msg_len) ++{ ++ struct mmal_msg_context *msg_context; ++ ++ pr_debug("buffer_to_host_cb: instance:%p msg:%p msg_len:%d\n", ++ instance, msg, msg_len); ++ ++ if (msg->u.buffer_from_host.drvbuf.magic == MMAL_MAGIC) { ++ msg_context = msg->u.buffer_from_host.drvbuf.client_context; ++ } else { ++ pr_err("MMAL_MSG_TYPE_BUFFER_TO_HOST with bad magic\n"); ++ return; ++ } ++ ++ if (msg->h.status != MMAL_MSG_STATUS_SUCCESS) { ++ /* message reception had an error */ ++ pr_warn("error %d in reply\n", msg->h.status); ++ ++ msg_context->u.bulk.status = msg->h.status; ++ ++ } else if (msg->u.buffer_from_host.buffer_header.length == 0) { ++ /* empty buffer */ ++ if (msg->u.buffer_from_host.buffer_header.flags & ++ MMAL_BUFFER_HEADER_FLAG_EOS) { ++ msg_context->u.bulk.status = ++ dummy_bulk_receive(instance, msg_context); ++ if (msg_context->u.bulk.status == 0) ++ return; /* successful bulk submission, bulk ++ * completion will trigger callback ++ */ ++ } else { ++ /* do callback with empty buffer - not EOS though */ ++ msg_context->u.bulk.status = 0; ++ msg_context->u.bulk.buffer_used = 0; ++ } ++ } else if (msg->u.buffer_from_host.payload_in_message == 0) { ++ /* data is not in message, queue a bulk receive */ ++ msg_context->u.bulk.status = ++ bulk_receive(instance, msg, msg_context); ++ if (msg_context->u.bulk.status == 0) ++ return; /* successful bulk submission, bulk ++ * completion will trigger callback ++ */ ++ ++ /* failed to submit buffer, this will end badly */ ++ pr_err("error %d on bulk submission\n", ++ msg_context->u.bulk.status); ++ ++ } else if (msg->u.buffer_from_host.payload_in_message <= ++ MMAL_VC_SHORT_DATA) { ++ /* data payload within message */ ++ msg_context->u.bulk.status = inline_receive(instance, msg, ++ msg_context); ++ } else { ++ pr_err("message with invalid short payload\n"); ++ ++ /* signal error */ ++ msg_context->u.bulk.status = -EINVAL; ++ msg_context->u.bulk.buffer_used = ++ msg->u.buffer_from_host.payload_in_message; ++ } ++ ++ /* replace the buffer header */ ++ port_buffer_from_host(instance, msg_context->u.bulk.port); ++ ++ /* schedule the port callback */ ++ schedule_work(&msg_context->u.bulk.work); ++} ++ ++static void bulk_receive_cb(struct vchiq_mmal_instance *instance, ++ struct mmal_msg_context *msg_context) ++{ ++ /* bulk receive operation complete */ ++ mutex_unlock(&msg_context->u.bulk.instance->bulk_mutex); ++ ++ /* replace the buffer header */ ++ port_buffer_from_host(msg_context->u.bulk.instance, ++ msg_context->u.bulk.port); ++ ++ msg_context->u.bulk.status = 0; ++ ++ /* schedule the port callback */ ++ schedule_work(&msg_context->u.bulk.work); ++} ++ ++static void bulk_abort_cb(struct vchiq_mmal_instance *instance, ++ struct mmal_msg_context *msg_context) ++{ ++ pr_err("%s: bulk ABORTED msg_context:%p\n", __func__, msg_context); ++ ++ /* bulk receive operation complete */ ++ mutex_unlock(&msg_context->u.bulk.instance->bulk_mutex); ++ ++ /* replace the buffer header */ ++ port_buffer_from_host(msg_context->u.bulk.instance, ++ msg_context->u.bulk.port); ++ ++ msg_context->u.bulk.status = -EINTR; ++ ++ schedule_work(&msg_context->u.bulk.work); ++} ++ ++/* incoming event service callback */ ++static void service_callback(void *param, ++ const VCHI_CALLBACK_REASON_T reason, ++ void *bulk_ctx) ++{ ++ struct vchiq_mmal_instance *instance = param; ++ int status; ++ u32 msg_len; ++ struct mmal_msg *msg; ++ VCHI_HELD_MSG_T msg_handle; ++ ++ if (!instance) { ++ pr_err("Message callback passed NULL instance\n"); ++ return; ++ } ++ ++ switch (reason) { ++ case VCHI_CALLBACK_MSG_AVAILABLE: ++ status = vchi_msg_hold(instance->handle, (void **)&msg, ++ &msg_len, VCHI_FLAGS_NONE, &msg_handle); ++ if (status) { ++ pr_err("Unable to dequeue a message (%d)\n", status); ++ break; ++ } ++ ++ DBG_DUMP_MSG(msg, msg_len, "<<< reply message"); ++ ++ /* handling is different for buffer messages */ ++ switch (msg->h.type) { ++ ++ case MMAL_MSG_TYPE_BUFFER_FROM_HOST: ++ vchi_held_msg_release(&msg_handle); ++ break; ++ ++ case MMAL_MSG_TYPE_EVENT_TO_HOST: ++ event_to_host_cb(instance, msg, msg_len); ++ vchi_held_msg_release(&msg_handle); ++ ++ break; ++ ++ case MMAL_MSG_TYPE_BUFFER_TO_HOST: ++ buffer_to_host_cb(instance, msg, msg_len); ++ vchi_held_msg_release(&msg_handle); ++ break; ++ ++ default: ++ /* messages dependant on header context to complete */ ++ ++ /* todo: the msg.context really ought to be sanity ++ * checked before we just use it, afaict it comes back ++ * and is used raw from the videocore. Perhaps it ++ * should be verified the address lies in the kernel ++ * address space. ++ */ ++ if (msg->h.context == NULL) { ++ pr_err("received message context was null!\n"); ++ vchi_held_msg_release(&msg_handle); ++ break; ++ } ++ ++ /* fill in context values */ ++ msg->h.context->u.sync.msg_handle = msg_handle; ++ msg->h.context->u.sync.msg = msg; ++ msg->h.context->u.sync.msg_len = msg_len; ++ ++ /* todo: should this check (completion_done() ++ * == 1) for no one waiting? or do we need a ++ * flag to tell us the completion has been ++ * interrupted so we can free the message and ++ * its context. This probably also solves the ++ * message arriving after interruption todo ++ * below ++ */ ++ ++ /* complete message so caller knows it happened */ ++ complete(&msg->h.context->u.sync.cmplt); ++ break; ++ } ++ ++ break; ++ ++ case VCHI_CALLBACK_BULK_RECEIVED: ++ bulk_receive_cb(instance, bulk_ctx); ++ break; ++ ++ case VCHI_CALLBACK_BULK_RECEIVE_ABORTED: ++ bulk_abort_cb(instance, bulk_ctx); ++ break; ++ ++ case VCHI_CALLBACK_SERVICE_CLOSED: ++ /* TODO: consider if this requires action if received when ++ * driver is not explicitly closing the service ++ */ ++ break; ++ ++ default: ++ pr_err("Received unhandled message reason %d\n", reason); ++ break; ++ } ++} ++ ++static int send_synchronous_mmal_msg(struct vchiq_mmal_instance *instance, ++ struct mmal_msg *msg, ++ unsigned int payload_len, ++ struct mmal_msg **msg_out, ++ VCHI_HELD_MSG_T *msg_handle_out) ++{ ++ struct mmal_msg_context msg_context; ++ int ret; ++ ++ /* payload size must not cause message to exceed max size */ ++ if (payload_len > ++ (MMAL_MSG_MAX_SIZE - sizeof(struct mmal_msg_header))) { ++ pr_err("payload length %d exceeds max:%d\n", payload_len, ++ (MMAL_MSG_MAX_SIZE - sizeof(struct mmal_msg_header))); ++ return -EINVAL; ++ } ++ ++ init_completion(&msg_context.u.sync.cmplt); ++ ++ msg->h.magic = MMAL_MAGIC; ++ msg->h.context = &msg_context; ++ msg->h.status = 0; ++ ++ DBG_DUMP_MSG(msg, (sizeof(struct mmal_msg_header) + payload_len), ++ ">>> sync message"); ++ ++ vchi_service_use(instance->handle); ++ ++ ret = vchi_msg_queue(instance->handle, ++ msg, ++ sizeof(struct mmal_msg_header) + payload_len, ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); ++ ++ vchi_service_release(instance->handle); ++ ++ if (ret) { ++ pr_err("error %d queuing message\n", ret); ++ return ret; ++ } ++ ++ ret = wait_for_completion_timeout(&msg_context.u.sync.cmplt, 3*HZ); ++ if (ret <= 0) { ++ pr_err("error %d waiting for sync completion\n", ret); ++ if (ret == 0) ++ ret = -ETIME; ++ /* todo: what happens if the message arrives after aborting */ ++ return ret; ++ } ++ ++ *msg_out = msg_context.u.sync.msg; ++ *msg_handle_out = msg_context.u.sync.msg_handle; ++ ++ return 0; ++} ++ ++static void dump_port_info(struct vchiq_mmal_port *port) ++{ ++ pr_debug("port handle:0x%x enabled:%d\n", port->handle, port->enabled); ++ ++ pr_debug("buffer minimum num:%d size:%d align:%d\n", ++ port->minimum_buffer.num, ++ port->minimum_buffer.size, port->minimum_buffer.alignment); ++ ++ pr_debug("buffer recommended num:%d size:%d align:%d\n", ++ port->recommended_buffer.num, ++ port->recommended_buffer.size, ++ port->recommended_buffer.alignment); ++ ++ pr_debug("buffer current values num:%d size:%d align:%d\n", ++ port->current_buffer.num, ++ port->current_buffer.size, port->current_buffer.alignment); ++ ++ pr_debug("elementry stream: type:%d encoding:0x%x varient:0x%x\n", ++ port->format.type, ++ port->format.encoding, port->format.encoding_variant); ++ ++ pr_debug(" bitrate:%d flags:0x%x\n", ++ port->format.bitrate, port->format.flags); ++ ++ if (port->format.type == MMAL_ES_TYPE_VIDEO) { ++ pr_debug ++ ("es video format: width:%d height:%d colourspace:0x%x\n", ++ port->es.video.width, port->es.video.height, ++ port->es.video.color_space); ++ ++ pr_debug(" : crop xywh %d,%d,%d,%d\n", ++ port->es.video.crop.x, ++ port->es.video.crop.y, ++ port->es.video.crop.width, port->es.video.crop.height); ++ pr_debug(" : framerate %d/%d aspect %d/%d\n", ++ port->es.video.frame_rate.num, ++ port->es.video.frame_rate.den, ++ port->es.video.par.num, port->es.video.par.den); ++ } ++} ++ ++static void port_to_mmal_msg(struct vchiq_mmal_port *port, struct mmal_port *p) ++{ ++ ++ /* todo do readonly fields need setting at all? */ ++ p->type = port->type; ++ p->index = port->index; ++ p->index_all = 0; ++ p->is_enabled = port->enabled; ++ p->buffer_num_min = port->minimum_buffer.num; ++ p->buffer_size_min = port->minimum_buffer.size; ++ p->buffer_alignment_min = port->minimum_buffer.alignment; ++ p->buffer_num_recommended = port->recommended_buffer.num; ++ p->buffer_size_recommended = port->recommended_buffer.size; ++ ++ /* only three writable fields in a port */ ++ p->buffer_num = port->current_buffer.num; ++ p->buffer_size = port->current_buffer.size; ++ p->userdata = port; ++} ++ ++static int port_info_set(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port) ++{ ++ int ret; ++ struct mmal_msg m; ++ struct mmal_msg *rmsg; ++ VCHI_HELD_MSG_T rmsg_handle; ++ ++ pr_debug("setting port info port %p\n", port); ++ if (!port) ++ return -1; ++ dump_port_info(port); ++ ++ m.h.type = MMAL_MSG_TYPE_PORT_INFO_SET; ++ ++ m.u.port_info_set.component_handle = port->component->handle; ++ m.u.port_info_set.port_type = port->type; ++ m.u.port_info_set.port_index = port->index; ++ ++ port_to_mmal_msg(port, &m.u.port_info_set.port); ++ ++ /* elementry stream format setup */ ++ m.u.port_info_set.format.type = port->format.type; ++ m.u.port_info_set.format.encoding = port->format.encoding; ++ m.u.port_info_set.format.encoding_variant = ++ port->format.encoding_variant; ++ m.u.port_info_set.format.bitrate = port->format.bitrate; ++ m.u.port_info_set.format.flags = port->format.flags; ++ ++ memcpy(&m.u.port_info_set.es, &port->es, ++ sizeof(union mmal_es_specific_format)); ++ ++ m.u.port_info_set.format.extradata_size = port->format.extradata_size; ++ memcpy(&m.u.port_info_set.extradata, port->format.extradata, ++ port->format.extradata_size); ++ ++ ret = send_synchronous_mmal_msg(instance, &m, ++ sizeof(m.u.port_info_set), ++ &rmsg, &rmsg_handle); ++ if (ret) ++ return ret; ++ ++ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_INFO_SET) { ++ /* got an unexpected message type in reply */ ++ ret = -EINVAL; ++ goto release_msg; ++ } ++ ++ /* return operation status */ ++ ret = -rmsg->u.port_info_get_reply.status; ++ ++ pr_debug("%s:result:%d component:0x%x port:%d\n", __func__, ret, ++ port->component->handle, port->handle); ++ ++release_msg: ++ vchi_held_msg_release(&rmsg_handle); ++ ++ return ret; ++ ++} ++ ++/* use port info get message to retrive port information */ ++static int port_info_get(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port) ++{ ++ int ret; ++ struct mmal_msg m; ++ struct mmal_msg *rmsg; ++ VCHI_HELD_MSG_T rmsg_handle; ++ ++ /* port info time */ ++ m.h.type = MMAL_MSG_TYPE_PORT_INFO_GET; ++ m.u.port_info_get.component_handle = port->component->handle; ++ m.u.port_info_get.port_type = port->type; ++ m.u.port_info_get.index = port->index; ++ ++ ret = send_synchronous_mmal_msg(instance, &m, ++ sizeof(m.u.port_info_get), ++ &rmsg, &rmsg_handle); ++ if (ret) ++ return ret; ++ ++ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_INFO_GET) { ++ /* got an unexpected message type in reply */ ++ ret = -EINVAL; ++ goto release_msg; ++ } ++ ++ /* return operation status */ ++ ret = -rmsg->u.port_info_get_reply.status; ++ if (ret != MMAL_MSG_STATUS_SUCCESS) ++ goto release_msg; ++ ++ if (rmsg->u.port_info_get_reply.port.is_enabled == 0) ++ port->enabled = false; ++ else ++ port->enabled = true; ++ ++ /* copy the values out of the message */ ++ port->handle = rmsg->u.port_info_get_reply.port_handle; ++ ++ /* port type and index cached to use on port info set becuase ++ * it does not use a port handle ++ */ ++ port->type = rmsg->u.port_info_get_reply.port_type; ++ port->index = rmsg->u.port_info_get_reply.port_index; ++ ++ port->minimum_buffer.num = ++ rmsg->u.port_info_get_reply.port.buffer_num_min; ++ port->minimum_buffer.size = ++ rmsg->u.port_info_get_reply.port.buffer_size_min; ++ port->minimum_buffer.alignment = ++ rmsg->u.port_info_get_reply.port.buffer_alignment_min; ++ ++ port->recommended_buffer.alignment = ++ rmsg->u.port_info_get_reply.port.buffer_alignment_min; ++ port->recommended_buffer.num = ++ rmsg->u.port_info_get_reply.port.buffer_num_recommended; ++ ++ port->current_buffer.num = rmsg->u.port_info_get_reply.port.buffer_num; ++ port->current_buffer.size = ++ rmsg->u.port_info_get_reply.port.buffer_size; ++ ++ /* stream format */ ++ port->format.type = rmsg->u.port_info_get_reply.format.type; ++ port->format.encoding = rmsg->u.port_info_get_reply.format.encoding; ++ port->format.encoding_variant = ++ rmsg->u.port_info_get_reply.format.encoding_variant; ++ port->format.bitrate = rmsg->u.port_info_get_reply.format.bitrate; ++ port->format.flags = rmsg->u.port_info_get_reply.format.flags; ++ ++ /* elementry stream format */ ++ memcpy(&port->es, ++ &rmsg->u.port_info_get_reply.es, ++ sizeof(union mmal_es_specific_format)); ++ port->format.es = &port->es; ++ ++ port->format.extradata_size = ++ rmsg->u.port_info_get_reply.format.extradata_size; ++ memcpy(port->format.extradata, ++ rmsg->u.port_info_get_reply.extradata, ++ port->format.extradata_size); ++ ++ pr_debug("received port info\n"); ++ dump_port_info(port); ++ ++release_msg: ++ ++ pr_debug("%s:result:%d component:0x%x port:%d\n", ++ __func__, ret, port->component->handle, port->handle); ++ ++ vchi_held_msg_release(&rmsg_handle); ++ ++ return ret; ++} ++ ++/* create comonent on vc */ ++static int create_component(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_component *component, ++ const char *name) ++{ ++ int ret; ++ struct mmal_msg m; ++ struct mmal_msg *rmsg; ++ VCHI_HELD_MSG_T rmsg_handle; ++ ++ /* build component create message */ ++ m.h.type = MMAL_MSG_TYPE_COMPONENT_CREATE; ++ m.u.component_create.client_component = component; ++ strncpy(m.u.component_create.name, name, ++ sizeof(m.u.component_create.name)); ++ ++ ret = send_synchronous_mmal_msg(instance, &m, ++ sizeof(m.u.component_create), ++ &rmsg, &rmsg_handle); ++ if (ret) ++ return ret; ++ ++ if (rmsg->h.type != m.h.type) { ++ /* got an unexpected message type in reply */ ++ ret = -EINVAL; ++ goto release_msg; ++ } ++ ++ ret = -rmsg->u.component_create_reply.status; ++ if (ret != MMAL_MSG_STATUS_SUCCESS) ++ goto release_msg; ++ ++ /* a valid component response received */ ++ component->handle = rmsg->u.component_create_reply.component_handle; ++ component->inputs = rmsg->u.component_create_reply.input_num; ++ component->outputs = rmsg->u.component_create_reply.output_num; ++ component->clocks = rmsg->u.component_create_reply.clock_num; ++ ++ pr_debug("Component handle:0x%x in:%d out:%d clock:%d\n", ++ component->handle, ++ component->inputs, component->outputs, component->clocks); ++ ++release_msg: ++ vchi_held_msg_release(&rmsg_handle); ++ ++ return ret; ++} ++ ++/* destroys a component on vc */ ++static int destroy_component(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_component *component) ++{ ++ int ret; ++ struct mmal_msg m; ++ struct mmal_msg *rmsg; ++ VCHI_HELD_MSG_T rmsg_handle; ++ ++ m.h.type = MMAL_MSG_TYPE_COMPONENT_DESTROY; ++ m.u.component_destroy.component_handle = component->handle; ++ ++ ret = send_synchronous_mmal_msg(instance, &m, ++ sizeof(m.u.component_destroy), ++ &rmsg, &rmsg_handle); ++ if (ret) ++ return ret; ++ ++ if (rmsg->h.type != m.h.type) { ++ /* got an unexpected message type in reply */ ++ ret = -EINVAL; ++ goto release_msg; ++ } ++ ++ ret = -rmsg->u.component_destroy_reply.status; ++ ++release_msg: ++ ++ vchi_held_msg_release(&rmsg_handle); ++ ++ return ret; ++} ++ ++/* enable a component on vc */ ++static int enable_component(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_component *component) ++{ ++ int ret; ++ struct mmal_msg m; ++ struct mmal_msg *rmsg; ++ VCHI_HELD_MSG_T rmsg_handle; ++ ++ m.h.type = MMAL_MSG_TYPE_COMPONENT_ENABLE; ++ m.u.component_enable.component_handle = component->handle; ++ ++ ret = send_synchronous_mmal_msg(instance, &m, ++ sizeof(m.u.component_enable), ++ &rmsg, &rmsg_handle); ++ if (ret) ++ return ret; ++ ++ if (rmsg->h.type != m.h.type) { ++ /* got an unexpected message type in reply */ ++ ret = -EINVAL; ++ goto release_msg; ++ } ++ ++ ret = -rmsg->u.component_enable_reply.status; ++ ++release_msg: ++ vchi_held_msg_release(&rmsg_handle); ++ ++ return ret; ++} ++ ++/* disable a component on vc */ ++static int disable_component(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_component *component) ++{ ++ int ret; ++ struct mmal_msg m; ++ struct mmal_msg *rmsg; ++ VCHI_HELD_MSG_T rmsg_handle; ++ ++ m.h.type = MMAL_MSG_TYPE_COMPONENT_DISABLE; ++ m.u.component_disable.component_handle = component->handle; ++ ++ ret = send_synchronous_mmal_msg(instance, &m, ++ sizeof(m.u.component_disable), ++ &rmsg, &rmsg_handle); ++ if (ret) ++ return ret; ++ ++ if (rmsg->h.type != m.h.type) { ++ /* got an unexpected message type in reply */ ++ ret = -EINVAL; ++ goto release_msg; ++ } ++ ++ ret = -rmsg->u.component_disable_reply.status; ++ ++release_msg: ++ ++ vchi_held_msg_release(&rmsg_handle); ++ ++ return ret; ++} ++ ++/* get version of mmal implementation */ ++static int get_version(struct vchiq_mmal_instance *instance, ++ u32 *major_out, u32 *minor_out) ++{ ++ int ret; ++ struct mmal_msg m; ++ struct mmal_msg *rmsg; ++ VCHI_HELD_MSG_T rmsg_handle; ++ ++ m.h.type = MMAL_MSG_TYPE_GET_VERSION; ++ ++ ret = send_synchronous_mmal_msg(instance, &m, ++ sizeof(m.u.version), ++ &rmsg, &rmsg_handle); ++ if (ret) ++ return ret; ++ ++ if (rmsg->h.type != m.h.type) { ++ /* got an unexpected message type in reply */ ++ ret = -EINVAL; ++ goto release_msg; ++ } ++ ++ *major_out = rmsg->u.version.major; ++ *minor_out = rmsg->u.version.minor; ++ ++release_msg: ++ vchi_held_msg_release(&rmsg_handle); ++ ++ return ret; ++} ++ ++/* do a port action with a port as a parameter */ ++static int port_action_port(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port, ++ enum mmal_msg_port_action_type action_type) ++{ ++ int ret; ++ struct mmal_msg m; ++ struct mmal_msg *rmsg; ++ VCHI_HELD_MSG_T rmsg_handle; ++ ++ m.h.type = MMAL_MSG_TYPE_PORT_ACTION; ++ m.u.port_action_port.component_handle = port->component->handle; ++ m.u.port_action_port.port_handle = port->handle; ++ m.u.port_action_port.action = action_type; ++ ++ port_to_mmal_msg(port, &m.u.port_action_port.port); ++ ++ ret = send_synchronous_mmal_msg(instance, &m, ++ sizeof(m.u.port_action_port), ++ &rmsg, &rmsg_handle); ++ if (ret) ++ return ret; ++ ++ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_ACTION) { ++ /* got an unexpected message type in reply */ ++ ret = -EINVAL; ++ goto release_msg; ++ } ++ ++ ret = -rmsg->u.port_action_reply.status; ++ ++ pr_debug("%s:result:%d component:0x%x port:%d action:%s(%d)\n", ++ __func__, ++ ret, port->component->handle, port->handle, ++ port_action_type_names[action_type], action_type); ++ ++release_msg: ++ vchi_held_msg_release(&rmsg_handle); ++ ++ return ret; ++} ++ ++/* do a port action with handles as parameters */ ++static int port_action_handle(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port, ++ enum mmal_msg_port_action_type action_type, ++ u32 connect_component_handle, ++ u32 connect_port_handle) ++{ ++ int ret; ++ struct mmal_msg m; ++ struct mmal_msg *rmsg; ++ VCHI_HELD_MSG_T rmsg_handle; ++ ++ m.h.type = MMAL_MSG_TYPE_PORT_ACTION; ++ ++ m.u.port_action_handle.component_handle = port->component->handle; ++ m.u.port_action_handle.port_handle = port->handle; ++ m.u.port_action_handle.action = action_type; ++ ++ m.u.port_action_handle.connect_component_handle = ++ connect_component_handle; ++ m.u.port_action_handle.connect_port_handle = connect_port_handle; ++ ++ ret = send_synchronous_mmal_msg(instance, &m, ++ sizeof(m.u.port_action_handle), ++ &rmsg, &rmsg_handle); ++ if (ret) ++ return ret; ++ ++ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_ACTION) { ++ /* got an unexpected message type in reply */ ++ ret = -EINVAL; ++ goto release_msg; ++ } ++ ++ ret = -rmsg->u.port_action_reply.status; ++ ++ pr_debug("%s:result:%d component:0x%x port:%d action:%s(%d)" \ ++ " connect component:0x%x connect port:%d\n", ++ __func__, ++ ret, port->component->handle, port->handle, ++ port_action_type_names[action_type], ++ action_type, connect_component_handle, connect_port_handle); ++ ++release_msg: ++ vchi_held_msg_release(&rmsg_handle); ++ ++ return ret; ++} ++ ++static int port_parameter_set(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port, ++ u32 parameter_id, void *value, u32 value_size) ++{ ++ int ret; ++ struct mmal_msg m; ++ struct mmal_msg *rmsg; ++ VCHI_HELD_MSG_T rmsg_handle; ++ ++ m.h.type = MMAL_MSG_TYPE_PORT_PARAMETER_SET; ++ ++ m.u.port_parameter_set.component_handle = port->component->handle; ++ m.u.port_parameter_set.port_handle = port->handle; ++ m.u.port_parameter_set.id = parameter_id; ++ m.u.port_parameter_set.size = (2 * sizeof(u32)) + value_size; ++ memcpy(&m.u.port_parameter_set.value, value, value_size); ++ ++ ret = send_synchronous_mmal_msg(instance, &m, ++ (4 * sizeof(u32)) + value_size, ++ &rmsg, &rmsg_handle); ++ if (ret) ++ return ret; ++ ++ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_PARAMETER_SET) { ++ /* got an unexpected message type in reply */ ++ ret = -EINVAL; ++ goto release_msg; ++ } ++ ++ ret = -rmsg->u.port_parameter_set_reply.status; ++ ++ pr_debug("%s:result:%d component:0x%x port:%d parameter:%d\n", ++ __func__, ++ ret, port->component->handle, port->handle, parameter_id); ++ ++release_msg: ++ vchi_held_msg_release(&rmsg_handle); ++ ++ return ret; ++} ++ ++static int port_parameter_get(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port, ++ u32 parameter_id, void *value, u32 *value_size) ++{ ++ int ret; ++ struct mmal_msg m; ++ struct mmal_msg *rmsg; ++ VCHI_HELD_MSG_T rmsg_handle; ++ ++ m.h.type = MMAL_MSG_TYPE_PORT_PARAMETER_GET; ++ ++ m.u.port_parameter_get.component_handle = port->component->handle; ++ m.u.port_parameter_get.port_handle = port->handle; ++ m.u.port_parameter_get.id = parameter_id; ++ m.u.port_parameter_get.size = (2 * sizeof(u32)) + *value_size; ++ ++ ret = send_synchronous_mmal_msg(instance, &m, ++ sizeof(struct ++ mmal_msg_port_parameter_get), ++ &rmsg, &rmsg_handle); ++ if (ret) ++ return ret; ++ ++ if (rmsg->h.type != MMAL_MSG_TYPE_PORT_PARAMETER_GET) { ++ /* got an unexpected message type in reply */ ++ pr_err("Incorrect reply type %d\n", rmsg->h.type); ++ ret = -EINVAL; ++ goto release_msg; ++ } ++ ++ ret = -rmsg->u.port_parameter_get_reply.status; ++ if (ret) { ++ /* Copy only as much as we have space for ++ * but report true size of parameter ++ */ ++ memcpy(value, &rmsg->u.port_parameter_get_reply.value, ++ *value_size); ++ *value_size = rmsg->u.port_parameter_get_reply.size; ++ } else ++ memcpy(value, &rmsg->u.port_parameter_get_reply.value, ++ rmsg->u.port_parameter_get_reply.size); ++ ++ pr_debug("%s:result:%d component:0x%x port:%d parameter:%d\n", __func__, ++ ret, port->component->handle, port->handle, parameter_id); ++ ++release_msg: ++ vchi_held_msg_release(&rmsg_handle); ++ ++ return ret; ++} ++ ++/* disables a port and drains buffers from it */ ++static int port_disable(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port) ++{ ++ int ret; ++ struct list_head *q, *buf_head; ++ unsigned long flags = 0; ++ ++ if (!port->enabled) ++ return 0; ++ ++ port->enabled = false; ++ ++ ret = port_action_port(instance, port, ++ MMAL_MSG_PORT_ACTION_TYPE_DISABLE); ++ if (ret == 0) { ++ ++ /* drain all queued buffers on port */ ++ spin_lock_irqsave(&port->slock, flags); ++ ++ list_for_each_safe(buf_head, q, &port->buffers) { ++ struct mmal_buffer *mmalbuf; ++ mmalbuf = list_entry(buf_head, struct mmal_buffer, ++ list); ++ list_del(buf_head); ++ if (port->buffer_cb) ++ port->buffer_cb(instance, ++ port, 0, mmalbuf, 0, 0, ++ MMAL_TIME_UNKNOWN, ++ MMAL_TIME_UNKNOWN); ++ } ++ ++ spin_unlock_irqrestore(&port->slock, flags); ++ ++ ret = port_info_get(instance, port); ++ } ++ ++ return ret; ++} ++ ++/* enable a port */ ++static int port_enable(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port) ++{ ++ unsigned int hdr_count; ++ struct list_head *buf_head; ++ int ret; ++ ++ if (port->enabled) ++ return 0; ++ ++ /* ensure there are enough buffers queued to cover the buffer headers */ ++ if (port->buffer_cb != NULL) { ++ hdr_count = 0; ++ list_for_each(buf_head, &port->buffers) { ++ hdr_count++; ++ } ++ if (hdr_count < port->current_buffer.num) ++ return -ENOSPC; ++ } ++ ++ ret = port_action_port(instance, port, ++ MMAL_MSG_PORT_ACTION_TYPE_ENABLE); ++ if (ret) ++ goto done; ++ ++ port->enabled = true; ++ ++ if (port->buffer_cb) { ++ /* send buffer headers to videocore */ ++ hdr_count = 1; ++ list_for_each(buf_head, &port->buffers) { ++ struct mmal_buffer *mmalbuf; ++ mmalbuf = list_entry(buf_head, struct mmal_buffer, ++ list); ++ ret = buffer_from_host(instance, port, mmalbuf); ++ if (ret) ++ goto done; ++ ++ hdr_count++; ++ if (hdr_count > port->current_buffer.num) ++ break; ++ } ++ } ++ ++ ret = port_info_get(instance, port); ++ ++done: ++ return ret; ++} ++ ++/* ------------------------------------------------------------------ ++ * Exported API ++ *------------------------------------------------------------------*/ ++ ++int vchiq_mmal_port_set_format(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port) ++{ ++ int ret; ++ ++ if (mutex_lock_interruptible(&instance->vchiq_mutex)) ++ return -EINTR; ++ ++ ret = port_info_set(instance, port); ++ if (ret) ++ goto release_unlock; ++ ++ /* read what has actually been set */ ++ ret = port_info_get(instance, port); ++ ++release_unlock: ++ mutex_unlock(&instance->vchiq_mutex); ++ ++ return ret; ++ ++} ++ ++int vchiq_mmal_port_parameter_set(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port, ++ u32 parameter, void *value, u32 value_size) ++{ ++ int ret; ++ ++ if (mutex_lock_interruptible(&instance->vchiq_mutex)) ++ return -EINTR; ++ ++ ret = port_parameter_set(instance, port, parameter, value, value_size); ++ ++ mutex_unlock(&instance->vchiq_mutex); ++ ++ return ret; ++} ++ ++int vchiq_mmal_port_parameter_get(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port, ++ u32 parameter, void *value, u32 *value_size) ++{ ++ int ret; ++ ++ if (mutex_lock_interruptible(&instance->vchiq_mutex)) ++ return -EINTR; ++ ++ ret = port_parameter_get(instance, port, parameter, value, value_size); ++ ++ mutex_unlock(&instance->vchiq_mutex); ++ ++ return ret; ++} ++ ++/* enable a port ++ * ++ * enables a port and queues buffers for satisfying callbacks if we ++ * provide a callback handler ++ */ ++int vchiq_mmal_port_enable(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port, ++ vchiq_mmal_buffer_cb buffer_cb) ++{ ++ int ret; ++ ++ if (mutex_lock_interruptible(&instance->vchiq_mutex)) ++ return -EINTR; ++ ++ /* already enabled - noop */ ++ if (port->enabled) { ++ ret = 0; ++ goto unlock; ++ } ++ ++ port->buffer_cb = buffer_cb; ++ ++ ret = port_enable(instance, port); ++ ++unlock: ++ mutex_unlock(&instance->vchiq_mutex); ++ ++ return ret; ++} ++ ++int vchiq_mmal_port_disable(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port) ++{ ++ int ret; ++ ++ if (mutex_lock_interruptible(&instance->vchiq_mutex)) ++ return -EINTR; ++ ++ if (!port->enabled) { ++ mutex_unlock(&instance->vchiq_mutex); ++ return 0; ++ } ++ ++ ret = port_disable(instance, port); ++ ++ mutex_unlock(&instance->vchiq_mutex); ++ ++ return ret; ++} ++ ++/* ports will be connected in a tunneled manner so data buffers ++ * are not handled by client. ++ */ ++int vchiq_mmal_port_connect_tunnel(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *src, ++ struct vchiq_mmal_port *dst) ++{ ++ int ret; ++ ++ if (mutex_lock_interruptible(&instance->vchiq_mutex)) ++ return -EINTR; ++ ++ /* disconnect ports if connected */ ++ if (src->connected != NULL) { ++ ret = port_disable(instance, src); ++ if (ret) { ++ pr_err("failed disabling src port(%d)\n", ret); ++ goto release_unlock; ++ } ++ ++ /* do not need to disable the destination port as they ++ * are connected and it is done automatically ++ */ ++ ++ ret = port_action_handle(instance, src, ++ MMAL_MSG_PORT_ACTION_TYPE_DISCONNECT, ++ src->connected->component->handle, ++ src->connected->handle); ++ if (ret < 0) { ++ pr_err("failed disconnecting src port\n"); ++ goto release_unlock; ++ } ++ src->connected->enabled = false; ++ src->connected = NULL; ++ } ++ ++ if (dst == NULL) { ++ /* do not make new connection */ ++ ret = 0; ++ pr_debug("not making new connection\n"); ++ goto release_unlock; ++ } ++ ++ /* copy src port format to dst */ ++ dst->format.encoding = src->format.encoding; ++ dst->es.video.width = src->es.video.width; ++ dst->es.video.height = src->es.video.height; ++ dst->es.video.crop.x = src->es.video.crop.x; ++ dst->es.video.crop.y = src->es.video.crop.y; ++ dst->es.video.crop.width = src->es.video.crop.width; ++ dst->es.video.crop.height = src->es.video.crop.height; ++ dst->es.video.frame_rate.num = src->es.video.frame_rate.num; ++ dst->es.video.frame_rate.den = src->es.video.frame_rate.den; ++ ++ /* set new format */ ++ ret = port_info_set(instance, dst); ++ if (ret) { ++ pr_debug("setting port info failed\n"); ++ goto release_unlock; ++ } ++ ++ /* read what has actually been set */ ++ ret = port_info_get(instance, dst); ++ if (ret) { ++ pr_debug("read back port info failed\n"); ++ goto release_unlock; ++ } ++ ++ /* connect two ports together */ ++ ret = port_action_handle(instance, src, ++ MMAL_MSG_PORT_ACTION_TYPE_CONNECT, ++ dst->component->handle, dst->handle); ++ if (ret < 0) { ++ pr_debug("connecting port %d:%d to %d:%d failed\n", ++ src->component->handle, src->handle, ++ dst->component->handle, dst->handle); ++ goto release_unlock; ++ } ++ src->connected = dst; ++ ++release_unlock: ++ ++ mutex_unlock(&instance->vchiq_mutex); ++ ++ return ret; ++} ++ ++int vchiq_mmal_submit_buffer(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port, ++ struct mmal_buffer *buffer) ++{ ++ unsigned long flags = 0; ++ ++ spin_lock_irqsave(&port->slock, flags); ++ list_add_tail(&buffer->list, &port->buffers); ++ spin_unlock_irqrestore(&port->slock, flags); ++ ++ /* the port previously underflowed because it was missing a ++ * mmal_buffer which has just been added, submit that buffer ++ * to the mmal service. ++ */ ++ if (port->buffer_underflow) { ++ port_buffer_from_host(instance, port); ++ port->buffer_underflow--; ++ } ++ ++ return 0; ++} ++ ++/* Initialise a mmal component and its ports ++ * ++ */ ++int vchiq_mmal_component_init(struct vchiq_mmal_instance *instance, ++ const char *name, ++ struct vchiq_mmal_component **component_out) ++{ ++ int ret; ++ int idx; /* port index */ ++ struct vchiq_mmal_component *component; ++ ++ if (mutex_lock_interruptible(&instance->vchiq_mutex)) ++ return -EINTR; ++ ++ if (instance->component_idx == VCHIQ_MMAL_MAX_COMPONENTS) { ++ ret = -EINVAL; /* todo is this correct error? */ ++ goto unlock; ++ } ++ ++ component = &instance->component[instance->component_idx]; ++ ++ ret = create_component(instance, component, name); ++ if (ret < 0) ++ goto unlock; ++ ++ /* ports info needs gathering */ ++ component->control.type = MMAL_PORT_TYPE_CONTROL; ++ component->control.index = 0; ++ component->control.component = component; ++ spin_lock_init(&component->control.slock); ++ INIT_LIST_HEAD(&component->control.buffers); ++ ret = port_info_get(instance, &component->control); ++ if (ret < 0) ++ goto release_component; ++ ++ for (idx = 0; idx < component->inputs; idx++) { ++ component->input[idx].type = MMAL_PORT_TYPE_INPUT; ++ component->input[idx].index = idx; ++ component->input[idx].component = component; ++ spin_lock_init(&component->input[idx].slock); ++ INIT_LIST_HEAD(&component->input[idx].buffers); ++ ret = port_info_get(instance, &component->input[idx]); ++ if (ret < 0) ++ goto release_component; ++ } ++ ++ for (idx = 0; idx < component->outputs; idx++) { ++ component->output[idx].type = MMAL_PORT_TYPE_OUTPUT; ++ component->output[idx].index = idx; ++ component->output[idx].component = component; ++ spin_lock_init(&component->output[idx].slock); ++ INIT_LIST_HEAD(&component->output[idx].buffers); ++ ret = port_info_get(instance, &component->output[idx]); ++ if (ret < 0) ++ goto release_component; ++ } ++ ++ for (idx = 0; idx < component->clocks; idx++) { ++ component->clock[idx].type = MMAL_PORT_TYPE_CLOCK; ++ component->clock[idx].index = idx; ++ component->clock[idx].component = component; ++ spin_lock_init(&component->clock[idx].slock); ++ INIT_LIST_HEAD(&component->clock[idx].buffers); ++ ret = port_info_get(instance, &component->clock[idx]); ++ if (ret < 0) ++ goto release_component; ++ } ++ ++ instance->component_idx++; ++ ++ *component_out = component; ++ ++ mutex_unlock(&instance->vchiq_mutex); ++ ++ return 0; ++ ++release_component: ++ destroy_component(instance, component); ++unlock: ++ mutex_unlock(&instance->vchiq_mutex); ++ ++ return ret; ++} ++ ++/* ++ * cause a mmal component to be destroyed ++ */ ++int vchiq_mmal_component_finalise(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_component *component) ++{ ++ int ret; ++ ++ if (mutex_lock_interruptible(&instance->vchiq_mutex)) ++ return -EINTR; ++ ++ if (component->enabled) ++ ret = disable_component(instance, component); ++ ++ ret = destroy_component(instance, component); ++ ++ mutex_unlock(&instance->vchiq_mutex); ++ ++ return ret; ++} ++ ++/* ++ * cause a mmal component to be enabled ++ */ ++int vchiq_mmal_component_enable(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_component *component) ++{ ++ int ret; ++ ++ if (mutex_lock_interruptible(&instance->vchiq_mutex)) ++ return -EINTR; ++ ++ if (component->enabled) { ++ mutex_unlock(&instance->vchiq_mutex); ++ return 0; ++ } ++ ++ ret = enable_component(instance, component); ++ if (ret == 0) ++ component->enabled = true; ++ ++ mutex_unlock(&instance->vchiq_mutex); ++ ++ return ret; ++} ++ ++/* ++ * cause a mmal component to be enabled ++ */ ++int vchiq_mmal_component_disable(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_component *component) ++{ ++ int ret; ++ ++ if (mutex_lock_interruptible(&instance->vchiq_mutex)) ++ return -EINTR; ++ ++ if (!component->enabled) { ++ mutex_unlock(&instance->vchiq_mutex); ++ return 0; ++ } ++ ++ ret = disable_component(instance, component); ++ if (ret == 0) ++ component->enabled = false; ++ ++ mutex_unlock(&instance->vchiq_mutex); ++ ++ return ret; ++} ++ ++int vchiq_mmal_version(struct vchiq_mmal_instance *instance, ++ u32 *major_out, u32 *minor_out) ++{ ++ int ret; ++ ++ if (mutex_lock_interruptible(&instance->vchiq_mutex)) ++ return -EINTR; ++ ++ ret = get_version(instance, major_out, minor_out); ++ ++ mutex_unlock(&instance->vchiq_mutex); ++ ++ return ret; ++} ++ ++int vchiq_mmal_finalise(struct vchiq_mmal_instance *instance) ++{ ++ int status = 0; ++ ++ if (instance == NULL) ++ return -EINVAL; ++ ++ if (mutex_lock_interruptible(&instance->vchiq_mutex)) ++ return -EINTR; ++ ++ vchi_service_use(instance->handle); ++ ++ status = vchi_service_close(instance->handle); ++ if (status != 0) ++ pr_err("mmal-vchiq: VCHIQ close failed"); ++ ++ mutex_unlock(&instance->vchiq_mutex); ++ ++ vfree(instance->bulk_scratch); ++ ++ kfree(instance); ++ ++ return status; ++} ++ ++int vchiq_mmal_init(struct vchiq_mmal_instance **out_instance) ++{ ++ int status; ++ struct vchiq_mmal_instance *instance; ++ static VCHI_CONNECTION_T *vchi_connection; ++ static VCHI_INSTANCE_T vchi_instance; ++ SERVICE_CREATION_T params = { ++ VCHI_VERSION_EX(VC_MMAL_VER, VC_MMAL_MIN_VER), ++ VC_MMAL_SERVER_NAME, ++ vchi_connection, ++ 0, /* rx fifo size (unused) */ ++ 0, /* tx fifo size (unused) */ ++ service_callback, ++ NULL, /* service callback parameter */ ++ 1, /* unaligned bulk receives */ ++ 1, /* unaligned bulk transmits */ ++ 0 /* want crc check on bulk transfers */ ++ }; ++ ++ /* compile time checks to ensure structure size as they are ++ * directly (de)serialised from memory. ++ */ ++ ++ /* ensure the header structure has packed to the correct size */ ++ BUILD_BUG_ON(sizeof(struct mmal_msg_header) != 24); ++ ++ /* ensure message structure does not exceed maximum length */ ++ BUILD_BUG_ON(sizeof(struct mmal_msg) > MMAL_MSG_MAX_SIZE); ++ ++ /* mmal port struct is correct size */ ++ BUILD_BUG_ON(sizeof(struct mmal_port) != 64); ++ ++ /* create a vchi instance */ ++ status = vchi_initialise(&vchi_instance); ++ if (status) { ++ pr_err("Failed to initialise VCHI instance (status=%d)\n", ++ status); ++ return -EIO; ++ } ++ ++ status = vchi_connect(NULL, 0, vchi_instance); ++ if (status) { ++ pr_err("Failed to connect VCHI instance (status=%d)\n", status); ++ return -EIO; ++ } ++ ++ instance = kmalloc(sizeof(*instance), GFP_KERNEL); ++ memset(instance, 0, sizeof(*instance)); ++ ++ mutex_init(&instance->vchiq_mutex); ++ mutex_init(&instance->bulk_mutex); ++ ++ instance->bulk_scratch = vmalloc(PAGE_SIZE); ++ ++ params.callback_param = instance; ++ ++ status = vchi_service_open(vchi_instance, ¶ms, &instance->handle); ++ if (status) { ++ pr_err("Failed to open VCHI service connection (status=%d)\n", ++ status); ++ goto err_close_services; ++ } ++ ++ vchi_service_release(instance->handle); ++ ++ *out_instance = instance; ++ ++ return 0; ++ ++err_close_services: ++ ++ vchi_service_close(instance->handle); ++ vfree(instance->bulk_scratch); ++ kfree(instance); ++ return -ENODEV; ++} +diff -Nur linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-vchiq.h linux-rpi/drivers/media/platform/bcm2835/mmal-vchiq.h +--- linux-4.1.13.orig/drivers/media/platform/bcm2835/mmal-vchiq.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/media/platform/bcm2835/mmal-vchiq.h 2015-11-29 09:42:37.835237156 +0100 +@@ -0,0 +1,178 @@ ++/* ++ * Broadcom BM2835 V4L2 driver ++ * ++ * Copyright © 2013 Raspberry Pi (Trading) Ltd. ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ * ++ * Authors: Vincent Sanders ++ * Dave Stevenson ++ * Simon Mellor ++ * Luke Diamand ++ * ++ * MMAL interface to VCHIQ message passing ++ */ ++ ++#ifndef MMAL_VCHIQ_H ++#define MMAL_VCHIQ_H ++ ++#include "mmal-msg-format.h" ++ ++#define MAX_PORT_COUNT 4 ++ ++/* Maximum size of the format extradata. */ ++#define MMAL_FORMAT_EXTRADATA_MAX_SIZE 128 ++ ++struct vchiq_mmal_instance; ++ ++enum vchiq_mmal_es_type { ++ MMAL_ES_TYPE_UNKNOWN, /**< Unknown elementary stream type */ ++ MMAL_ES_TYPE_CONTROL, /**< Elementary stream of control commands */ ++ MMAL_ES_TYPE_AUDIO, /**< Audio elementary stream */ ++ MMAL_ES_TYPE_VIDEO, /**< Video elementary stream */ ++ MMAL_ES_TYPE_SUBPICTURE /**< Sub-picture elementary stream */ ++}; ++ ++/* rectangle, used lots so it gets its own struct */ ++struct vchiq_mmal_rect { ++ s32 x; ++ s32 y; ++ s32 width; ++ s32 height; ++}; ++ ++struct vchiq_mmal_port_buffer { ++ unsigned int num; /* number of buffers */ ++ u32 size; /* size of buffers */ ++ u32 alignment; /* alignment of buffers */ ++}; ++ ++struct vchiq_mmal_port; ++ ++typedef void (*vchiq_mmal_buffer_cb)( ++ struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port, ++ int status, struct mmal_buffer *buffer, ++ unsigned long length, u32 mmal_flags, s64 dts, s64 pts); ++ ++struct vchiq_mmal_port { ++ bool enabled; ++ u32 handle; ++ u32 type; /* port type, cached to use on port info set */ ++ u32 index; /* port index, cached to use on port info set */ ++ ++ /* component port belongs to, allows simple deref */ ++ struct vchiq_mmal_component *component; ++ ++ struct vchiq_mmal_port *connected; /* port conencted to */ ++ ++ /* buffer info */ ++ struct vchiq_mmal_port_buffer minimum_buffer; ++ struct vchiq_mmal_port_buffer recommended_buffer; ++ struct vchiq_mmal_port_buffer current_buffer; ++ ++ /* stream format */ ++ struct mmal_es_format format; ++ /* elementry stream format */ ++ union mmal_es_specific_format es; ++ ++ /* data buffers to fill */ ++ struct list_head buffers; ++ /* lock to serialise adding and removing buffers from list */ ++ spinlock_t slock; ++ /* count of how many buffer header refils have failed because ++ * there was no buffer to satisfy them ++ */ ++ int buffer_underflow; ++ /* callback on buffer completion */ ++ vchiq_mmal_buffer_cb buffer_cb; ++ /* callback context */ ++ void *cb_ctx; ++}; ++ ++struct vchiq_mmal_component { ++ bool enabled; ++ u32 handle; /* VideoCore handle for component */ ++ u32 inputs; /* Number of input ports */ ++ u32 outputs; /* Number of output ports */ ++ u32 clocks; /* Number of clock ports */ ++ struct vchiq_mmal_port control; /* control port */ ++ struct vchiq_mmal_port input[MAX_PORT_COUNT]; /* input ports */ ++ struct vchiq_mmal_port output[MAX_PORT_COUNT]; /* output ports */ ++ struct vchiq_mmal_port clock[MAX_PORT_COUNT]; /* clock ports */ ++}; ++ ++ ++int vchiq_mmal_init(struct vchiq_mmal_instance **out_instance); ++int vchiq_mmal_finalise(struct vchiq_mmal_instance *instance); ++ ++/* Initialise a mmal component and its ports ++* ++*/ ++int vchiq_mmal_component_init( ++ struct vchiq_mmal_instance *instance, ++ const char *name, ++ struct vchiq_mmal_component **component_out); ++ ++int vchiq_mmal_component_finalise( ++ struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_component *component); ++ ++int vchiq_mmal_component_enable( ++ struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_component *component); ++ ++int vchiq_mmal_component_disable( ++ struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_component *component); ++ ++ ++ ++/* enable a mmal port ++ * ++ * enables a port and if a buffer callback provided enque buffer ++ * headers as apropriate for the port. ++ */ ++int vchiq_mmal_port_enable( ++ struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port, ++ vchiq_mmal_buffer_cb buffer_cb); ++ ++/* disable a port ++ * ++ * disable a port will dequeue any pending buffers ++ */ ++int vchiq_mmal_port_disable(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port); ++ ++ ++int vchiq_mmal_port_parameter_set(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port, ++ u32 parameter, ++ void *value, ++ u32 value_size); ++ ++int vchiq_mmal_port_parameter_get(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port, ++ u32 parameter, ++ void *value, ++ u32 *value_size); ++ ++int vchiq_mmal_port_set_format(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port); ++ ++int vchiq_mmal_port_connect_tunnel(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *src, ++ struct vchiq_mmal_port *dst); ++ ++int vchiq_mmal_version(struct vchiq_mmal_instance *instance, ++ u32 *major_out, ++ u32 *minor_out); ++ ++int vchiq_mmal_submit_buffer(struct vchiq_mmal_instance *instance, ++ struct vchiq_mmal_port *port, ++ struct mmal_buffer *buf); ++ ++#endif /* MMAL_VCHIQ_H */ +diff -Nur linux-4.1.13.orig/drivers/media/platform/Kconfig linux-rpi/drivers/media/platform/Kconfig +--- linux-4.1.13.orig/drivers/media/platform/Kconfig 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/media/platform/Kconfig 2015-11-29 09:42:37.835237156 +0100 +@@ -11,6 +11,8 @@ + + if V4L_PLATFORM_DRIVERS + ++source "drivers/media/platform/bcm2835/Kconfig" ++ + source "drivers/media/platform/marvell-ccic/Kconfig" + + config VIDEO_VIA_CAMERA +diff -Nur linux-4.1.13.orig/drivers/media/platform/Makefile linux-rpi/drivers/media/platform/Makefile +--- linux-4.1.13.orig/drivers/media/platform/Makefile 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/media/platform/Makefile 2015-11-29 09:42:37.835237156 +0100 +@@ -2,6 +2,8 @@ + # Makefile for the video capture/playback device drivers. + # + ++obj-$(CONFIG_VIDEO_BCM2835) += bcm2835/ ++ + obj-$(CONFIG_VIDEO_TIMBERDALE) += timblogiw.o + obj-$(CONFIG_VIDEO_M32R_AR_M64278) += arv.o + +diff -Nur linux-4.1.13.orig/drivers/media/usb/dvb-usb-v2/rtl28xxu.c linux-rpi/drivers/media/usb/dvb-usb-v2/rtl28xxu.c +--- linux-4.1.13.orig/drivers/media/usb/dvb-usb-v2/rtl28xxu.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/media/usb/dvb-usb-v2/rtl28xxu.c 2015-11-29 09:42:37.915231841 +0100 +@@ -1755,6 +1755,10 @@ + &rtl28xxu_props, "Compro VideoMate U620F", NULL) }, + { DVB_USB_DEVICE(USB_VID_KWORLD_2, 0xd394, + &rtl28xxu_props, "MaxMedia HU394-T", NULL) }, ++ { DVB_USB_DEVICE(USB_VID_GTEK, 0xb803 /*USB_PID_AUGUST_DVBT205*/, ++ &rtl28xxu_props, "August DVB-T 205", NULL) }, ++ { DVB_USB_DEVICE(USB_VID_GTEK, 0xa803 /*USB_PID_AUGUST_DVBT205*/, ++ &rtl28xxu_props, "August DVB-T 205", NULL) }, + { DVB_USB_DEVICE(USB_VID_LEADTEK, 0x6a03, + &rtl28xxu_props, "Leadtek WinFast DTV Dongle mini", NULL) }, + { DVB_USB_DEVICE(USB_VID_GTEK, USB_PID_CPYTO_REDI_PC50A, +diff -Nur linux-4.1.13.orig/drivers/mfd/Kconfig linux-rpi/drivers/mfd/Kconfig +--- linux-4.1.13.orig/drivers/mfd/Kconfig 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/mfd/Kconfig 2015-11-29 09:42:37.991226791 +0100 +@@ -10,6 +10,14 @@ + select IRQ_DOMAIN + default n + ++config MFD_RPISENSE_CORE ++ tristate "Raspberry Pi Sense HAT core functions" ++ depends on I2C ++ select MFD_CORE ++ help ++ This is the core driver for the Raspberry Pi Sense HAT. This provides ++ the necessary functions to communicate with the hardware. ++ + config MFD_CS5535 + tristate "AMD CS5535 and CS5536 southbridge core functions" + select MFD_CORE +diff -Nur linux-4.1.13.orig/drivers/mfd/Makefile linux-rpi/drivers/mfd/Makefile +--- linux-4.1.13.orig/drivers/mfd/Makefile 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/mfd/Makefile 2015-11-29 09:42:37.991226791 +0100 +@@ -185,3 +185,5 @@ + intel-soc-pmic-objs := intel_soc_pmic_core.o intel_soc_pmic_crc.o + obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o + obj-$(CONFIG_MFD_MT6397) += mt6397-core.o ++ ++obj-$(CONFIG_MFD_RPISENSE_CORE) += rpisense-core.o +diff -Nur linux-4.1.13.orig/drivers/mfd/rpisense-core.c linux-rpi/drivers/mfd/rpisense-core.c +--- linux-4.1.13.orig/drivers/mfd/rpisense-core.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/mfd/rpisense-core.c 2015-11-29 09:42:38.019224931 +0100 +@@ -0,0 +1,157 @@ ++/* ++ * Raspberry Pi Sense HAT core driver ++ * http://raspberrypi.org ++ * ++ * Copyright (C) 2015 Raspberry Pi ++ * ++ * Author: Serge Schneider ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * This driver is based on wm8350 implementation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++struct rpisense *rpisense; ++ ++static void rpisense_client_dev_register(struct rpisense *rpisense, ++ const char *name, ++ struct platform_device **pdev) ++{ ++ int ret; ++ ++ *pdev = platform_device_alloc(name, -1); ++ if (*pdev == NULL) { ++ dev_err(rpisense->dev, "Failed to allocate %s\n", name); ++ return; ++ } ++ ++ (*pdev)->dev.parent = rpisense->dev; ++ platform_set_drvdata(*pdev, rpisense); ++ ret = platform_device_add(*pdev); ++ if (ret != 0) { ++ dev_err(rpisense->dev, "Failed to register %s: %d\n", ++ name, ret); ++ platform_device_put(*pdev); ++ *pdev = NULL; ++ } ++} ++ ++static int rpisense_probe(struct i2c_client *i2c, ++ const struct i2c_device_id *id) ++{ ++ int ret; ++ struct rpisense_js *rpisense_js; ++ ++ rpisense = devm_kzalloc(&i2c->dev, sizeof(struct rpisense), GFP_KERNEL); ++ if (rpisense == NULL) ++ return -ENOMEM; ++ ++ i2c_set_clientdata(i2c, rpisense); ++ rpisense->dev = &i2c->dev; ++ rpisense->i2c_client = i2c; ++ ++ ret = rpisense_reg_read(rpisense, RPISENSE_WAI); ++ if (ret > 0) { ++ if (ret != 's') ++ return -EINVAL; ++ } else { ++ return ret; ++ } ++ ret = rpisense_reg_read(rpisense, RPISENSE_VER); ++ if (ret < 0) ++ return ret; ++ ++ dev_info(rpisense->dev, ++ "Raspberry Pi Sense HAT firmware version %i\n", ret); ++ ++ rpisense_js = &rpisense->joystick; ++ rpisense_js->keys_desc = devm_gpiod_get(&i2c->dev, ++ "keys-int", GPIOD_IN); ++ if (IS_ERR(rpisense_js->keys_desc)) { ++ dev_warn(&i2c->dev, "Failed to get keys-int descriptor.\n"); ++ rpisense_js->keys_desc = gpio_to_desc(23); ++ if (rpisense_js->keys_desc == NULL) { ++ dev_err(&i2c->dev, "GPIO23 fallback failed.\n"); ++ return PTR_ERR(rpisense_js->keys_desc); ++ } ++ } ++ rpisense_client_dev_register(rpisense, "rpi-sense-js", ++ &(rpisense->joystick.pdev)); ++ rpisense_client_dev_register(rpisense, "rpi-sense-fb", ++ &(rpisense->framebuffer.pdev)); ++ ++ return 0; ++} ++ ++static int rpisense_remove(struct i2c_client *i2c) ++{ ++ struct rpisense *rpisense = i2c_get_clientdata(i2c); ++ ++ platform_device_unregister(rpisense->joystick.pdev); ++ return 0; ++} ++ ++struct rpisense *rpisense_get_dev(void) ++{ ++ return rpisense; ++} ++EXPORT_SYMBOL_GPL(rpisense_get_dev); ++ ++s32 rpisense_reg_read(struct rpisense *rpisense, int reg) ++{ ++ int ret = i2c_smbus_read_byte_data(rpisense->i2c_client, reg); ++ ++ if (ret < 0) ++ dev_err(rpisense->dev, "Read from reg %d failed\n", reg); ++ /* Due to the BCM270x I2C clock stretching bug, some values ++ * may have MSB set. Clear it to avoid incorrect values. ++ * */ ++ return ret & 0x7F; ++} ++EXPORT_SYMBOL_GPL(rpisense_reg_read); ++ ++int rpisense_block_write(struct rpisense *rpisense, const char *buf, int count) ++{ ++ int ret = i2c_master_send(rpisense->i2c_client, buf, count); ++ ++ if (ret < 0) ++ dev_err(rpisense->dev, "Block write failed\n"); ++ return ret; ++} ++EXPORT_SYMBOL_GPL(rpisense_block_write); ++ ++static const struct i2c_device_id rpisense_i2c_id[] = { ++ { "rpi-sense", 0 }, ++ { } ++}; ++MODULE_DEVICE_TABLE(i2c, rpisense_i2c_id); ++ ++ ++static struct i2c_driver rpisense_driver = { ++ .driver = { ++ .name = "rpi-sense", ++ .owner = THIS_MODULE, ++ }, ++ .probe = rpisense_probe, ++ .remove = rpisense_remove, ++ .id_table = rpisense_i2c_id, ++}; ++ ++module_i2c_driver(rpisense_driver); ++ ++MODULE_DESCRIPTION("Raspberry Pi Sense HAT core driver"); ++MODULE_AUTHOR("Serge Schneider "); ++MODULE_LICENSE("GPL"); ++ +diff -Nur linux-4.1.13.orig/drivers/misc/bcm2835_smi.c linux-rpi/drivers/misc/bcm2835_smi.c +--- linux-4.1.13.orig/drivers/misc/bcm2835_smi.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/misc/bcm2835_smi.c 2015-11-29 09:42:38.035223868 +0100 +@@ -0,0 +1,985 @@ ++/** ++ * Broadcom Secondary Memory Interface driver ++ * ++ * Written by Luke Wren ++ * Copyright (c) 2015, Raspberry Pi (Trading) Ltd. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define BCM2835_SMI_IMPLEMENTATION ++#include ++ ++#define DRIVER_NAME "smi-bcm2835" ++ ++#define N_PAGES_FROM_BYTES(n) ((n + PAGE_SIZE-1) / PAGE_SIZE) ++ ++#define DMA_WRITE_TO_MEM true ++#define DMA_READ_FROM_MEM false ++ ++struct bcm2835_smi_instance { ++ struct device *dev; ++ struct smi_settings settings; ++ __iomem void *smi_regs_ptr, *cm_smi_regs_ptr; ++ dma_addr_t smi_regs_busaddr; ++ ++ struct dma_chan *dma_chan; ++ struct dma_slave_config dma_config; ++ ++ struct bcm2835_smi_bounce_info bounce; ++ ++ struct scatterlist buffer_sgl; ++ ++ int clock_source; ++ int clock_divisor; ++ ++ /* Sometimes we are called into in an atomic context (e.g. by ++ JFFS2 + MTD) so we can't use a mutex */ ++ spinlock_t transaction_lock; ++}; ++ ++/**************************************************************************** ++* ++* SMI clock manager setup ++* ++***************************************************************************/ ++ ++static inline void write_smi_cm_reg(struct bcm2835_smi_instance *inst, ++ u32 val, unsigned reg) ++{ ++ writel(CM_PWD | val, inst->cm_smi_regs_ptr + reg); ++} ++ ++static inline u32 read_smi_cm_reg(struct bcm2835_smi_instance *inst, ++ unsigned reg) ++{ ++ return readl(inst->cm_smi_regs_ptr + reg); ++} ++ ++static void smi_setup_clock(struct bcm2835_smi_instance *inst) ++{ ++ dev_dbg(inst->dev, "Setting up clock..."); ++ /* Disable SMI clock and wait for it to stop. */ ++ write_smi_cm_reg(inst, 0, CM_SMI_CTL); ++ while (read_smi_cm_reg(inst, CM_SMI_CTL) & CM_SMI_CTL_BUSY) ++ ; ++ ++ write_smi_cm_reg(inst, (inst->clock_divisor << CM_SMI_DIV_DIVI_OFFS), ++ CM_SMI_DIV); ++ write_smi_cm_reg(inst, (inst->clock_source << CM_SMI_CTL_SRC_OFFS), ++ CM_SMI_CTL); ++ ++ /* Enable the clock */ ++ write_smi_cm_reg(inst, (inst->clock_source << CM_SMI_CTL_SRC_OFFS) | ++ CM_SMI_CTL_ENAB, CM_SMI_CTL); ++} ++ ++/**************************************************************************** ++* ++* SMI peripheral setup ++* ++***************************************************************************/ ++ ++static inline void write_smi_reg(struct bcm2835_smi_instance *inst, ++ u32 val, unsigned reg) ++{ ++ writel(val, inst->smi_regs_ptr + reg); ++} ++ ++static inline u32 read_smi_reg(struct bcm2835_smi_instance *inst, unsigned reg) ++{ ++ return readl(inst->smi_regs_ptr + reg); ++} ++ ++/* Token-paste macro for e.g SMIDSR_RSTROBE -> value of SMIDSR_RSTROBE_MASK */ ++#define _CONCAT(x, y) x##y ++#define CONCAT(x, y) _CONCAT(x, y) ++ ++#define SET_BIT_FIELD(dest, field, bits) ((dest) = \ ++ ((dest) & ~CONCAT(field, _MASK)) | (((bits) << CONCAT(field, _OFFS))& \ ++ CONCAT(field, _MASK))) ++#define GET_BIT_FIELD(src, field) (((src) & \ ++ CONCAT(field, _MASK)) >> CONCAT(field, _OFFS)) ++ ++static void smi_dump_context_labelled(struct bcm2835_smi_instance *inst, ++ const char *label) ++{ ++ dev_err(inst->dev, "SMI context dump: %s", label); ++ dev_err(inst->dev, "SMICS: 0x%08x", read_smi_reg(inst, SMICS)); ++ dev_err(inst->dev, "SMIL: 0x%08x", read_smi_reg(inst, SMIL)); ++ dev_err(inst->dev, "SMIDSR: 0x%08x", read_smi_reg(inst, SMIDSR0)); ++ dev_err(inst->dev, "SMIDSW: 0x%08x", read_smi_reg(inst, SMIDSW0)); ++ dev_err(inst->dev, "SMIDC: 0x%08x", read_smi_reg(inst, SMIDC)); ++ dev_err(inst->dev, "SMIFD: 0x%08x", read_smi_reg(inst, SMIFD)); ++ dev_err(inst->dev, " "); ++} ++ ++static inline void smi_dump_context(struct bcm2835_smi_instance *inst) ++{ ++ smi_dump_context_labelled(inst, ""); ++} ++ ++static void smi_get_default_settings(struct bcm2835_smi_instance *inst) ++{ ++ struct smi_settings *settings = &inst->settings; ++ ++ settings->data_width = SMI_WIDTH_16BIT; ++ settings->pack_data = true; ++ ++ settings->read_setup_time = 1; ++ settings->read_hold_time = 1; ++ settings->read_pace_time = 1; ++ settings->read_strobe_time = 3; ++ ++ settings->write_setup_time = settings->read_setup_time; ++ settings->write_hold_time = settings->read_hold_time; ++ settings->write_pace_time = settings->read_pace_time; ++ settings->write_strobe_time = settings->read_strobe_time; ++ ++ settings->dma_enable = true; ++ settings->dma_passthrough_enable = false; ++ settings->dma_read_thresh = 0x01; ++ settings->dma_write_thresh = 0x3f; ++ settings->dma_panic_read_thresh = 0x20; ++ settings->dma_panic_write_thresh = 0x20; ++} ++ ++void bcm2835_smi_set_regs_from_settings(struct bcm2835_smi_instance *inst) ++{ ++ struct smi_settings *settings = &inst->settings; ++ int smidsr_temp = 0, smidsw_temp = 0, smics_temp, ++ smidcs_temp, smidc_temp = 0; ++ ++ spin_lock(&inst->transaction_lock); ++ ++ /* temporarily disable the peripheral: */ ++ smics_temp = read_smi_reg(inst, SMICS); ++ write_smi_reg(inst, 0, SMICS); ++ smidcs_temp = read_smi_reg(inst, SMIDCS); ++ write_smi_reg(inst, 0, SMIDCS); ++ ++ if (settings->pack_data) ++ smics_temp |= SMICS_PXLDAT; ++ else ++ smics_temp &= ~SMICS_PXLDAT; ++ ++ SET_BIT_FIELD(smidsr_temp, SMIDSR_RWIDTH, settings->data_width); ++ SET_BIT_FIELD(smidsr_temp, SMIDSR_RSETUP, settings->read_setup_time); ++ SET_BIT_FIELD(smidsr_temp, SMIDSR_RHOLD, settings->read_hold_time); ++ SET_BIT_FIELD(smidsr_temp, SMIDSR_RPACE, settings->read_pace_time); ++ SET_BIT_FIELD(smidsr_temp, SMIDSR_RSTROBE, settings->read_strobe_time); ++ write_smi_reg(inst, smidsr_temp, SMIDSR0); ++ ++ SET_BIT_FIELD(smidsw_temp, SMIDSW_WWIDTH, settings->data_width); ++ if (settings->data_width == SMI_WIDTH_8BIT) ++ smidsw_temp |= SMIDSW_WSWAP; ++ else ++ smidsw_temp &= ~SMIDSW_WSWAP; ++ SET_BIT_FIELD(smidsw_temp, SMIDSW_WSETUP, settings->write_setup_time); ++ SET_BIT_FIELD(smidsw_temp, SMIDSW_WHOLD, settings->write_hold_time); ++ SET_BIT_FIELD(smidsw_temp, SMIDSW_WPACE, settings->write_pace_time); ++ SET_BIT_FIELD(smidsw_temp, SMIDSW_WSTROBE, ++ settings->write_strobe_time); ++ write_smi_reg(inst, smidsw_temp, SMIDSW0); ++ ++ SET_BIT_FIELD(smidc_temp, SMIDC_REQR, settings->dma_read_thresh); ++ SET_BIT_FIELD(smidc_temp, SMIDC_REQW, settings->dma_write_thresh); ++ SET_BIT_FIELD(smidc_temp, SMIDC_PANICR, ++ settings->dma_panic_read_thresh); ++ SET_BIT_FIELD(smidc_temp, SMIDC_PANICW, ++ settings->dma_panic_write_thresh); ++ if (settings->dma_passthrough_enable) { ++ smidc_temp |= SMIDC_DMAP; ++ smidsr_temp |= SMIDSR_RDREQ; ++ write_smi_reg(inst, smidsr_temp, SMIDSR0); ++ smidsw_temp |= SMIDSW_WDREQ; ++ write_smi_reg(inst, smidsw_temp, SMIDSW0); ++ } else ++ smidc_temp &= ~SMIDC_DMAP; ++ if (settings->dma_enable) ++ smidc_temp |= SMIDC_DMAEN; ++ else ++ smidc_temp &= ~SMIDC_DMAEN; ++ ++ write_smi_reg(inst, smidc_temp, SMIDC); ++ ++ /* re-enable (if was previously enabled) */ ++ write_smi_reg(inst, smics_temp, SMICS); ++ write_smi_reg(inst, smidcs_temp, SMIDCS); ++ ++ spin_unlock(&inst->transaction_lock); ++} ++EXPORT_SYMBOL(bcm2835_smi_set_regs_from_settings); ++ ++struct smi_settings *bcm2835_smi_get_settings_from_regs ++ (struct bcm2835_smi_instance *inst) ++{ ++ struct smi_settings *settings = &inst->settings; ++ int smidsr, smidsw, smidc; ++ ++ spin_lock(&inst->transaction_lock); ++ ++ smidsr = read_smi_reg(inst, SMIDSR0); ++ smidsw = read_smi_reg(inst, SMIDSW0); ++ smidc = read_smi_reg(inst, SMIDC); ++ ++ settings->pack_data = (read_smi_reg(inst, SMICS) & SMICS_PXLDAT) ? ++ true : false; ++ ++ settings->data_width = GET_BIT_FIELD(smidsr, SMIDSR_RWIDTH); ++ settings->read_setup_time = GET_BIT_FIELD(smidsr, SMIDSR_RSETUP); ++ settings->read_hold_time = GET_BIT_FIELD(smidsr, SMIDSR_RHOLD); ++ settings->read_pace_time = GET_BIT_FIELD(smidsr, SMIDSR_RPACE); ++ settings->read_strobe_time = GET_BIT_FIELD(smidsr, SMIDSR_RSTROBE); ++ ++ settings->write_setup_time = GET_BIT_FIELD(smidsw, SMIDSW_WSETUP); ++ settings->write_hold_time = GET_BIT_FIELD(smidsw, SMIDSW_WHOLD); ++ settings->write_pace_time = GET_BIT_FIELD(smidsw, SMIDSW_WPACE); ++ settings->write_strobe_time = GET_BIT_FIELD(smidsw, SMIDSW_WSTROBE); ++ ++ settings->dma_read_thresh = GET_BIT_FIELD(smidc, SMIDC_REQR); ++ settings->dma_write_thresh = GET_BIT_FIELD(smidc, SMIDC_REQW); ++ settings->dma_panic_read_thresh = GET_BIT_FIELD(smidc, SMIDC_PANICR); ++ settings->dma_panic_write_thresh = GET_BIT_FIELD(smidc, SMIDC_PANICW); ++ settings->dma_passthrough_enable = (smidc & SMIDC_DMAP) ? true : false; ++ settings->dma_enable = (smidc & SMIDC_DMAEN) ? true : false; ++ ++ spin_unlock(&inst->transaction_lock); ++ ++ return settings; ++} ++EXPORT_SYMBOL(bcm2835_smi_get_settings_from_regs); ++ ++static inline void smi_set_address(struct bcm2835_smi_instance *inst, ++ unsigned int address) ++{ ++ int smia_temp = 0, smida_temp = 0; ++ ++ SET_BIT_FIELD(smia_temp, SMIA_ADDR, address); ++ SET_BIT_FIELD(smida_temp, SMIDA_ADDR, address); ++ ++ /* Write to both address registers - user doesn't care whether we're ++ doing programmed or direct transfers. */ ++ write_smi_reg(inst, smia_temp, SMIA); ++ write_smi_reg(inst, smida_temp, SMIDA); ++} ++ ++static void smi_setup_regs(struct bcm2835_smi_instance *inst) ++{ ++ ++ dev_dbg(inst->dev, "Initialising SMI registers..."); ++ /* Disable the peripheral if already enabled */ ++ write_smi_reg(inst, 0, SMICS); ++ write_smi_reg(inst, 0, SMIDCS); ++ ++ smi_get_default_settings(inst); ++ bcm2835_smi_set_regs_from_settings(inst); ++ smi_set_address(inst, 0); ++ ++ write_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_ENABLE, SMICS); ++ write_smi_reg(inst, read_smi_reg(inst, SMIDCS) | SMIDCS_ENABLE, ++ SMIDCS); ++} ++ ++/**************************************************************************** ++* ++* Low-level SMI access functions ++* Other modules should use the exported higher-level functions e.g. ++* bcm2835_smi_write_buf() unless they have a good reason to use these ++* ++***************************************************************************/ ++ ++static inline uint32_t smi_read_single_word(struct bcm2835_smi_instance *inst) ++{ ++ int timeout = 0; ++ ++ write_smi_reg(inst, SMIDCS_ENABLE, SMIDCS); ++ write_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_START, SMIDCS); ++ /* Make sure things happen in the right order...*/ ++ mb(); ++ while (!(read_smi_reg(inst, SMIDCS) & SMIDCS_DONE) && ++ ++timeout < 10000) ++ ; ++ if (timeout < 10000) ++ return read_smi_reg(inst, SMIDD); ++ ++ dev_err(inst->dev, ++ "SMI direct read timed out (is the clock set up correctly?)"); ++ return 0; ++} ++ ++static inline void smi_write_single_word(struct bcm2835_smi_instance *inst, ++ uint32_t data) ++{ ++ int timeout = 0; ++ ++ write_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_WRITE, SMIDCS); ++ write_smi_reg(inst, data, SMIDD); ++ write_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_WRITE | SMIDCS_START, ++ SMIDCS); ++ ++ while (!(read_smi_reg(inst, SMIDCS) & SMIDCS_DONE) && ++ ++timeout < 10000) ++ ; ++ if (timeout >= 10000) ++ dev_err(inst->dev, ++ "SMI direct write timed out (is the clock set up correctly?)"); ++} ++ ++/* Initiates a programmed read into the read FIFO. It is up to the caller to ++ * read data from the FIFO - either via paced DMA transfer, ++ * or polling SMICS_RXD to check whether data is available. ++ * SMICS_ACTIVE will go low upon completion. */ ++static void smi_init_programmed_read(struct bcm2835_smi_instance *inst, ++ int num_transfers) ++{ ++ int smics_temp; ++ ++ /* Disable the peripheral: */ ++ smics_temp = read_smi_reg(inst, SMICS) & ~(SMICS_ENABLE | SMICS_WRITE); ++ write_smi_reg(inst, smics_temp, SMICS); ++ while (read_smi_reg(inst, SMICS) & SMICS_ENABLE) ++ ; ++ ++ /* Program the transfer count: */ ++ write_smi_reg(inst, num_transfers, SMIL); ++ ++ /* re-enable and start: */ ++ smics_temp |= SMICS_ENABLE; ++ write_smi_reg(inst, smics_temp, SMICS); ++ smics_temp |= SMICS_CLEAR; ++ /* Just to be certain: */ ++ mb(); ++ while (read_smi_reg(inst, SMICS) & SMICS_ACTIVE) ++ ; ++ write_smi_reg(inst, smics_temp, SMICS); ++ smics_temp |= SMICS_START; ++ write_smi_reg(inst, smics_temp, SMICS); ++} ++ ++/* Initiates a programmed write sequence, using data from the write FIFO. ++ * It is up to the caller to initiate a DMA transfer before calling, ++ * or use another method to keep the write FIFO topped up. ++ * SMICS_ACTIVE will go low upon completion. ++ */ ++static void smi_init_programmed_write(struct bcm2835_smi_instance *inst, ++ int num_transfers) ++{ ++ int smics_temp; ++ ++ /* Disable the peripheral: */ ++ smics_temp = read_smi_reg(inst, SMICS) & ~SMICS_ENABLE; ++ write_smi_reg(inst, smics_temp, SMICS); ++ while (read_smi_reg(inst, SMICS) & SMICS_ENABLE) ++ ; ++ ++ /* Program the transfer count: */ ++ write_smi_reg(inst, num_transfers, SMIL); ++ ++ /* setup, re-enable and start: */ ++ smics_temp |= SMICS_WRITE | SMICS_ENABLE; ++ write_smi_reg(inst, smics_temp, SMICS); ++ smics_temp |= SMICS_START; ++ write_smi_reg(inst, smics_temp, SMICS); ++} ++ ++/* Initiate a read and then poll FIFO for data, reading out as it appears. */ ++static void smi_read_fifo(struct bcm2835_smi_instance *inst, ++ uint32_t *dest, int n_bytes) ++{ ++ if (read_smi_reg(inst, SMICS) & SMICS_RXD) { ++ smi_dump_context_labelled(inst, ++ "WARNING: read FIFO not empty at start of read call."); ++ while (read_smi_reg(inst, SMICS)) ++ ; ++ } ++ ++ /* Dispatch the read: */ ++ if (inst->settings.data_width == SMI_WIDTH_8BIT) ++ smi_init_programmed_read(inst, n_bytes); ++ else if (inst->settings.data_width == SMI_WIDTH_16BIT) ++ smi_init_programmed_read(inst, n_bytes / 2); ++ else { ++ dev_err(inst->dev, "Unsupported data width for read."); ++ return; ++ } ++ ++ /* Poll FIFO to keep it empty */ ++ while (!(read_smi_reg(inst, SMICS) & SMICS_DONE)) ++ if (read_smi_reg(inst, SMICS) & SMICS_RXD) ++ *dest++ = read_smi_reg(inst, SMID); ++ ++ /* Ensure that the FIFO is emptied */ ++ if (read_smi_reg(inst, SMICS) & SMICS_RXD) { ++ int fifo_count; ++ ++ fifo_count = GET_BIT_FIELD(read_smi_reg(inst, SMIFD), ++ SMIFD_FCNT); ++ while (fifo_count--) ++ *dest++ = read_smi_reg(inst, SMID); ++ } ++ ++ if (!(read_smi_reg(inst, SMICS) & SMICS_DONE)) ++ smi_dump_context_labelled(inst, ++ "WARNING: transaction finished but done bit not set."); ++ ++ if (read_smi_reg(inst, SMICS) & SMICS_RXD) ++ smi_dump_context_labelled(inst, ++ "WARNING: read FIFO not empty at end of read call."); ++ ++} ++ ++/* Initiate a write, and then keep the FIFO topped up. */ ++static void smi_write_fifo(struct bcm2835_smi_instance *inst, ++ uint32_t *src, int n_bytes) ++{ ++ int i, timeout = 0; ++ ++ /* Empty FIFOs if not already so */ ++ if (!(read_smi_reg(inst, SMICS) & SMICS_TXE)) { ++ smi_dump_context_labelled(inst, ++ "WARNING: write fifo not empty at start of write call."); ++ write_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_CLEAR, ++ SMICS); ++ } ++ ++ /* Initiate the transfer */ ++ if (inst->settings.data_width == SMI_WIDTH_8BIT) ++ smi_init_programmed_write(inst, n_bytes); ++ else if (inst->settings.data_width == SMI_WIDTH_16BIT) ++ smi_init_programmed_write(inst, n_bytes / 2); ++ else { ++ dev_err(inst->dev, "Unsupported data width for write."); ++ return; ++ } ++ /* Fill the FIFO: */ ++ for (i = 0; i < (n_bytes - 1) / 4 + 1; ++i) { ++ while (!(read_smi_reg(inst, SMICS) & SMICS_TXD)) ++ ; ++ write_smi_reg(inst, *src++, SMID); ++ } ++ /* Busy wait... */ ++ while (!(read_smi_reg(inst, SMICS) & SMICS_DONE) && ++timeout < ++ 1000000) ++ ; ++ if (timeout >= 1000000) ++ smi_dump_context_labelled(inst, ++ "Timed out on write operation!"); ++ if (!(read_smi_reg(inst, SMICS) & SMICS_TXE)) ++ smi_dump_context_labelled(inst, ++ "WARNING: FIFO not empty at end of write operation."); ++} ++ ++/**************************************************************************** ++* ++* SMI DMA operations ++* ++***************************************************************************/ ++ ++/* Disable SMI and put it into the correct direction before doing DMA setup. ++ Stops spurious DREQs during setup. Peripheral is re-enabled by init_*() */ ++static void smi_disable(struct bcm2835_smi_instance *inst, ++ enum dma_transfer_direction direction) ++{ ++ int smics_temp = read_smi_reg(inst, SMICS) & ~SMICS_ENABLE; ++ ++ if (direction == DMA_DEV_TO_MEM) ++ smics_temp &= ~SMICS_WRITE; ++ else ++ smics_temp |= SMICS_WRITE; ++ write_smi_reg(inst, smics_temp, SMICS); ++ while (read_smi_reg(inst, SMICS) & SMICS_ACTIVE) ++ ; ++} ++ ++static struct scatterlist *smi_scatterlist_from_buffer( ++ struct bcm2835_smi_instance *inst, ++ dma_addr_t buf, ++ size_t len, ++ struct scatterlist *sg) ++{ ++ sg_init_table(sg, 1); ++ sg_dma_address(sg) = buf; ++ sg_dma_len(sg) = len; ++ return sg; ++} ++ ++static void smi_dma_callback_user_copy(void *param) ++{ ++ /* Notify the bottom half that a chunk is ready for user copy */ ++ struct bcm2835_smi_instance *inst = ++ (struct bcm2835_smi_instance *)param; ++ ++ up(&inst->bounce.callback_sem); ++} ++ ++/* Creates a descriptor, assigns the given callback, and submits the ++ descriptor to dmaengine. Does not block - can queue up multiple ++ descriptors and then wait for them all to complete. ++ sg_len is the number of control blocks, NOT the number of bytes. ++ dir can be DMA_MEM_TO_DEV or DMA_DEV_TO_MEM. ++ callback can be NULL - in this case it is not called. */ ++static inline struct dma_async_tx_descriptor *smi_dma_submit_sgl( ++ struct bcm2835_smi_instance *inst, ++ struct scatterlist *sgl, ++ size_t sg_len, ++ enum dma_transfer_direction dir, ++ dma_async_tx_callback callback) ++{ ++ struct dma_async_tx_descriptor *desc; ++ ++ desc = dmaengine_prep_slave_sg(inst->dma_chan, ++ sgl, ++ sg_len, ++ dir, ++ DMA_PREP_INTERRUPT | DMA_CTRL_ACK | ++ DMA_PREP_FENCE); ++ if (!desc) { ++ dev_err(inst->dev, "read_sgl: dma slave preparation failed!"); ++ write_smi_reg(inst, read_smi_reg(inst, SMICS) & ~SMICS_ACTIVE, ++ SMICS); ++ while (read_smi_reg(inst, SMICS) & SMICS_ACTIVE) ++ cpu_relax(); ++ write_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_ACTIVE, ++ SMICS); ++ return NULL; ++ } ++ desc->callback = callback; ++ desc->callback_param = inst; ++ if (dmaengine_submit(desc) < 0) ++ return NULL; ++ return desc; ++} ++ ++/* NB this function blocks until the transfer is complete */ ++static void ++smi_dma_read_sgl(struct bcm2835_smi_instance *inst, ++ struct scatterlist *sgl, size_t sg_len, size_t n_bytes) ++{ ++ struct dma_async_tx_descriptor *desc; ++ ++ /* Disable SMI and set to read before dispatching DMA - if SMI is in ++ * write mode and TX fifo is empty, it will generate a DREQ which may ++ * cause the read DMA to complete before the SMI read command is even ++ * dispatched! We want to dispatch DMA before SMI read so that reading ++ * is gapless, for logic analyser. ++ */ ++ ++ smi_disable(inst, DMA_DEV_TO_MEM); ++ ++ desc = smi_dma_submit_sgl(inst, sgl, sg_len, DMA_DEV_TO_MEM, NULL); ++ dma_async_issue_pending(inst->dma_chan); ++ ++ if (inst->settings.data_width == SMI_WIDTH_8BIT) ++ smi_init_programmed_read(inst, n_bytes); ++ else ++ smi_init_programmed_read(inst, n_bytes / 2); ++ ++ if (dma_wait_for_async_tx(desc) == DMA_ERROR) ++ smi_dump_context_labelled(inst, "DMA timeout!"); ++} ++ ++static void ++smi_dma_write_sgl(struct bcm2835_smi_instance *inst, ++ struct scatterlist *sgl, size_t sg_len, size_t n_bytes) ++{ ++ struct dma_async_tx_descriptor *desc; ++ ++ if (inst->settings.data_width == SMI_WIDTH_8BIT) ++ smi_init_programmed_write(inst, n_bytes); ++ else ++ smi_init_programmed_write(inst, n_bytes / 2); ++ ++ desc = smi_dma_submit_sgl(inst, sgl, sg_len, DMA_MEM_TO_DEV, NULL); ++ dma_async_issue_pending(inst->dma_chan); ++ ++ if (dma_wait_for_async_tx(desc) == DMA_ERROR) ++ smi_dump_context_labelled(inst, "DMA timeout!"); ++ else ++ /* Wait for SMI to finish our writes */ ++ while (!(read_smi_reg(inst, SMICS) & SMICS_DONE)) ++ cpu_relax(); ++} ++ ++ssize_t bcm2835_smi_user_dma( ++ struct bcm2835_smi_instance *inst, ++ enum dma_transfer_direction dma_dir, ++ char __user *user_ptr, size_t count, ++ struct bcm2835_smi_bounce_info **bounce) ++{ ++ int chunk_no = 0, chunk_size, count_left = count; ++ struct scatterlist *sgl; ++ void (*init_trans_func)(struct bcm2835_smi_instance *, int); ++ ++ spin_lock(&inst->transaction_lock); ++ ++ if (dma_dir == DMA_DEV_TO_MEM) ++ init_trans_func = smi_init_programmed_read; ++ else ++ init_trans_func = smi_init_programmed_write; ++ ++ smi_disable(inst, dma_dir); ++ ++ sema_init(&inst->bounce.callback_sem, 0); ++ if (bounce) ++ *bounce = &inst->bounce; ++ while (count_left) { ++ chunk_size = count_left > DMA_BOUNCE_BUFFER_SIZE ? ++ DMA_BOUNCE_BUFFER_SIZE : count_left; ++ if (chunk_size == DMA_BOUNCE_BUFFER_SIZE) { ++ sgl = ++ &inst->bounce.sgl[chunk_no % DMA_BOUNCE_BUFFER_COUNT]; ++ } else { ++ sgl = smi_scatterlist_from_buffer( ++ inst, ++ inst->bounce.phys[ ++ chunk_no % DMA_BOUNCE_BUFFER_COUNT], ++ chunk_size, ++ &inst->buffer_sgl); ++ } ++ ++ if (!smi_dma_submit_sgl(inst, sgl, 1, dma_dir, ++ smi_dma_callback_user_copy ++ )) { ++ dev_err(inst->dev, "sgl submit failed"); ++ count = 0; ++ goto out; ++ } ++ count_left -= chunk_size; ++ chunk_no++; ++ } ++ dma_async_issue_pending(inst->dma_chan); ++ ++ if (inst->settings.data_width == SMI_WIDTH_8BIT) ++ init_trans_func(inst, count); ++ else if (inst->settings.data_width == SMI_WIDTH_16BIT) ++ init_trans_func(inst, count / 2); ++out: ++ spin_unlock(&inst->transaction_lock); ++ return count; ++} ++EXPORT_SYMBOL(bcm2835_smi_user_dma); ++ ++ ++/**************************************************************************** ++* ++* High level buffer transfer functions - for use by other drivers ++* ++***************************************************************************/ ++ ++/* Buffer must be physically contiguous - i.e. kmalloc, not vmalloc! */ ++void bcm2835_smi_write_buf( ++ struct bcm2835_smi_instance *inst, ++ const void *buf, size_t n_bytes) ++{ ++ int odd_bytes = n_bytes & 0x3; ++ ++ n_bytes -= odd_bytes; ++ ++ spin_lock(&inst->transaction_lock); ++ ++ if (n_bytes > DMA_THRESHOLD_BYTES) { ++ dma_addr_t phy_addr = dma_map_single( ++ inst->dev, ++ (void *)buf, ++ n_bytes, ++ DMA_MEM_TO_DEV); ++ struct scatterlist *sgl = ++ smi_scatterlist_from_buffer(inst, phy_addr, n_bytes, ++ &inst->buffer_sgl); ++ ++ if (!sgl) { ++ smi_dump_context_labelled(inst, ++ "Error: could not create scatterlist for write!"); ++ goto out; ++ } ++ smi_dma_write_sgl(inst, sgl, 1, n_bytes); ++ ++ dma_unmap_single ++ (inst->dev, phy_addr, n_bytes, DMA_MEM_TO_DEV); ++ } else if (n_bytes) { ++ smi_write_fifo(inst, (uint32_t *) buf, n_bytes); ++ } ++ buf += n_bytes; ++ ++ if (inst->settings.data_width == SMI_WIDTH_8BIT) { ++ while (odd_bytes--) ++ smi_write_single_word(inst, *(uint8_t *) (buf++)); ++ } else { ++ while (odd_bytes >= 2) { ++ smi_write_single_word(inst, *(uint16_t *)buf); ++ buf += 2; ++ odd_bytes -= 2; ++ } ++ if (odd_bytes) { ++ /* Reading an odd number of bytes on a 16 bit bus is ++ a user bug. It's kinder to fail early and tell them ++ than to e.g. transparently give them the bottom byte ++ of a 16 bit transfer. */ ++ dev_err(inst->dev, ++ "WARNING: odd number of bytes specified for wide transfer."); ++ dev_err(inst->dev, ++ "At least one byte dropped as a result."); ++ dump_stack(); ++ } ++ } ++out: ++ spin_unlock(&inst->transaction_lock); ++} ++EXPORT_SYMBOL(bcm2835_smi_write_buf); ++ ++void bcm2835_smi_read_buf(struct bcm2835_smi_instance *inst, ++ void *buf, size_t n_bytes) ++{ ++ ++ /* SMI is inherently 32-bit, which causes surprising amounts of mess ++ for bytes % 4 != 0. Easiest to avoid this mess altogether ++ by handling remainder separately. */ ++ int odd_bytes = n_bytes & 0x3; ++ ++ spin_lock(&inst->transaction_lock); ++ n_bytes -= odd_bytes; ++ if (n_bytes > DMA_THRESHOLD_BYTES) { ++ dma_addr_t phy_addr = dma_map_single(inst->dev, ++ buf, n_bytes, ++ DMA_DEV_TO_MEM); ++ struct scatterlist *sgl = smi_scatterlist_from_buffer( ++ inst, phy_addr, n_bytes, ++ &inst->buffer_sgl); ++ if (!sgl) { ++ smi_dump_context_labelled(inst, ++ "Error: could not create scatterlist for read!"); ++ goto out; ++ } ++ smi_dma_read_sgl(inst, sgl, 1, n_bytes); ++ dma_unmap_single(inst->dev, phy_addr, n_bytes, DMA_DEV_TO_MEM); ++ } else if (n_bytes) { ++ smi_read_fifo(inst, (uint32_t *)buf, n_bytes); ++ } ++ buf += n_bytes; ++ ++ if (inst->settings.data_width == SMI_WIDTH_8BIT) { ++ while (odd_bytes--) ++ *((uint8_t *) (buf++)) = smi_read_single_word(inst); ++ } else { ++ while (odd_bytes >= 2) { ++ *(uint16_t *) buf = smi_read_single_word(inst); ++ buf += 2; ++ odd_bytes -= 2; ++ } ++ if (odd_bytes) { ++ dev_err(inst->dev, ++ "WARNING: odd number of bytes specified for wide transfer."); ++ dev_err(inst->dev, ++ "At least one byte dropped as a result."); ++ dump_stack(); ++ } ++ } ++out: ++ spin_unlock(&inst->transaction_lock); ++} ++EXPORT_SYMBOL(bcm2835_smi_read_buf); ++ ++void bcm2835_smi_set_address(struct bcm2835_smi_instance *inst, ++ unsigned int address) ++{ ++ spin_lock(&inst->transaction_lock); ++ smi_set_address(inst, address); ++ spin_unlock(&inst->transaction_lock); ++} ++EXPORT_SYMBOL(bcm2835_smi_set_address); ++ ++struct bcm2835_smi_instance *bcm2835_smi_get(struct device_node *node) ++{ ++ struct platform_device *pdev; ++ ++ if (!node) ++ return NULL; ++ ++ pdev = of_find_device_by_node(node); ++ if (!pdev) ++ return NULL; ++ ++ return platform_get_drvdata(pdev); ++} ++EXPORT_SYMBOL(bcm2835_smi_get); ++ ++/**************************************************************************** ++* ++* bcm2835_smi_probe - called when the driver is loaded. ++* ++***************************************************************************/ ++ ++static int bcm2835_smi_dma_setup(struct bcm2835_smi_instance *inst) ++{ ++ int i, rv = 0; ++ ++ inst->dma_chan = dma_request_slave_channel(inst->dev, "rx-tx"); ++ ++ inst->dma_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ inst->dma_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ inst->dma_config.src_addr = inst->smi_regs_busaddr + SMID; ++ inst->dma_config.dst_addr = inst->dma_config.src_addr; ++ /* Direction unimportant - always overridden by prep_slave_sg */ ++ inst->dma_config.direction = DMA_DEV_TO_MEM; ++ dmaengine_slave_config(inst->dma_chan, &inst->dma_config); ++ /* Alloc and map bounce buffers */ ++ for (i = 0; i < DMA_BOUNCE_BUFFER_COUNT; ++i) { ++ inst->bounce.buffer[i] = ++ dmam_alloc_coherent(inst->dev, DMA_BOUNCE_BUFFER_SIZE, ++ &inst->bounce.phys[i], ++ GFP_KERNEL); ++ if (!inst->bounce.buffer[i]) { ++ dev_err(inst->dev, "Could not allocate buffer!"); ++ rv = -ENOMEM; ++ break; ++ } ++ smi_scatterlist_from_buffer( ++ inst, ++ inst->bounce.phys[i], ++ DMA_BOUNCE_BUFFER_SIZE, ++ &inst->bounce.sgl[i] ++ ); ++ } ++ ++ return rv; ++} ++ ++static int bcm2835_smi_probe(struct platform_device *pdev) ++{ ++ int err; ++ struct device *dev = &pdev->dev; ++ struct device_node *node = dev->of_node; ++ struct resource *ioresource; ++ struct bcm2835_smi_instance *inst; ++ ++ /* Allocate buffers and instance data */ ++ ++ inst = devm_kzalloc(dev, sizeof(struct bcm2835_smi_instance), ++ GFP_KERNEL); ++ ++ if (!inst) ++ return -ENOMEM; ++ ++ inst->dev = dev; ++ spin_lock_init(&inst->transaction_lock); ++ ++ /* We require device tree support */ ++ if (!node) ++ return -EINVAL; ++ ++ ioresource = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ inst->smi_regs_ptr = devm_ioremap_resource(dev, ioresource); ++ ioresource = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ inst->cm_smi_regs_ptr = devm_ioremap_resource(dev, ioresource); ++ inst->smi_regs_busaddr = be32_to_cpu( ++ *of_get_address(node, 0, NULL, NULL)); ++ of_property_read_u32(node, ++ "brcm,smi-clock-source", ++ &inst->clock_source); ++ of_property_read_u32(node, ++ "brcm,smi-clock-divisor", ++ &inst->clock_divisor); ++ ++ err = bcm2835_smi_dma_setup(inst); ++ if (err) ++ return err; ++ ++ /* Finally, do peripheral setup */ ++ ++ smi_setup_clock(inst); ++ smi_setup_regs(inst); ++ ++ platform_set_drvdata(pdev, inst); ++ ++ dev_info(inst->dev, "initialised"); ++ ++ return 0; ++} ++ ++/**************************************************************************** ++* ++* bcm2835_smi_remove - called when the driver is unloaded. ++* ++***************************************************************************/ ++ ++static int bcm2835_smi_remove(struct platform_device *pdev) ++{ ++ struct bcm2835_smi_instance *inst = platform_get_drvdata(pdev); ++ struct device *dev = inst->dev; ++ ++ dev_info(dev, "SMI device removed - OK"); ++ return 0; ++} ++ ++/**************************************************************************** ++* ++* Register the driver with device tree ++* ++***************************************************************************/ ++ ++static const struct of_device_id bcm2835_smi_of_match[] = { ++ {.compatible = "brcm,bcm2835-smi",}, ++ { /* sentinel */ }, ++}; ++ ++MODULE_DEVICE_TABLE(of, bcm2835_smi_of_match); ++ ++static struct platform_driver bcm2835_smi_driver = { ++ .probe = bcm2835_smi_probe, ++ .remove = bcm2835_smi_remove, ++ .driver = { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = bcm2835_smi_of_match, ++ }, ++}; ++ ++module_platform_driver(bcm2835_smi_driver); ++ ++MODULE_ALIAS("platform:smi-bcm2835"); ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("Device driver for BCM2835's secondary memory interface"); ++MODULE_AUTHOR("Luke Wren "); +diff -Nur linux-4.1.13.orig/drivers/misc/Kconfig linux-rpi/drivers/misc/Kconfig +--- linux-4.1.13.orig/drivers/misc/Kconfig 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/misc/Kconfig 2015-11-29 09:42:38.035223868 +0100 +@@ -10,6 +10,14 @@ + select INPUT_POLLDEV + default n + ++config BCM2835_SMI ++ tristate "Broadcom 283x Secondary Memory Interface driver" ++ depends on MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835 ++ default m ++ help ++ Driver for enabling and using Broadcom's Secondary/Slow Memory Interface. ++ Appears as /dev/bcm2835_smi. For ioctl interface see drivers/misc/bcm2835_smi.h ++ + config AD525X_DPOT + tristate "Analog Devices Digital Potentiometers" + depends on (I2C || SPI) && SYSFS +@@ -524,6 +532,7 @@ + source "drivers/misc/altera-stapl/Kconfig" + source "drivers/misc/mei/Kconfig" + source "drivers/misc/vmw_vmci/Kconfig" ++source "drivers/misc/vc04_services/Kconfig" + source "drivers/misc/mic/Kconfig" + source "drivers/misc/genwqe/Kconfig" + source "drivers/misc/echo/Kconfig" +diff -Nur linux-4.1.13.orig/drivers/misc/Makefile linux-rpi/drivers/misc/Makefile +--- linux-4.1.13.orig/drivers/misc/Makefile 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/misc/Makefile 2015-11-29 09:42:38.035223868 +0100 +@@ -9,6 +9,7 @@ + obj-$(CONFIG_INTEL_MID_PTI) += pti.o + obj-$(CONFIG_ATMEL_SSC) += atmel-ssc.o + obj-$(CONFIG_ATMEL_TCLIB) += atmel_tclib.o ++obj-$(CONFIG_BCM2835_SMI) += bcm2835_smi.o + obj-$(CONFIG_BMP085) += bmp085.o + obj-$(CONFIG_BMP085_I2C) += bmp085-i2c.o + obj-$(CONFIG_BMP085_SPI) += bmp085-spi.o +@@ -51,6 +52,7 @@ + obj-$(CONFIG_VMWARE_VMCI) += vmw_vmci/ + obj-$(CONFIG_LATTICE_ECP3_CONFIG) += lattice-ecp3-config.o + obj-$(CONFIG_SRAM) += sram.o ++obj-$(CONFIG_BCM2708_VCHIQ) += vc04_services/ + obj-y += mic/ + obj-$(CONFIG_GENWQE) += genwqe/ + obj-$(CONFIG_ECHO) += echo/ +diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchi/connections/connection.h linux-rpi/drivers/misc/vc04_services/interface/vchi/connections/connection.h +--- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchi/connections/connection.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/misc/vc04_services/interface/vchi/connections/connection.h 2015-11-29 09:42:38.059222273 +0100 +@@ -0,0 +1,328 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef CONNECTION_H_ ++#define CONNECTION_H_ ++ ++#include ++#include ++#include ++ ++#include "interface/vchi/vchi_cfg_internal.h" ++#include "interface/vchi/vchi_common.h" ++#include "interface/vchi/message_drivers/message.h" ++ ++/****************************************************************************** ++ Global defs ++ *****************************************************************************/ ++ ++// Opaque handle for a connection / service pair ++typedef struct opaque_vchi_connection_connected_service_handle_t *VCHI_CONNECTION_SERVICE_HANDLE_T; ++ ++// opaque handle to the connection state information ++typedef struct opaque_vchi_connection_info_t VCHI_CONNECTION_STATE_T; ++ ++typedef struct vchi_connection_t VCHI_CONNECTION_T; ++ ++ ++/****************************************************************************** ++ API ++ *****************************************************************************/ ++ ++// Routine to init a connection with a particular low level driver ++typedef VCHI_CONNECTION_STATE_T * (*VCHI_CONNECTION_INIT_T)( struct vchi_connection_t * connection, ++ const VCHI_MESSAGE_DRIVER_T * driver ); ++ ++// Routine to control CRC enabling at a connection level ++typedef int32_t (*VCHI_CONNECTION_CRC_CONTROL_T)( VCHI_CONNECTION_STATE_T *state_handle, ++ VCHI_CRC_CONTROL_T control ); ++ ++// Routine to create a service ++typedef int32_t (*VCHI_CONNECTION_SERVICE_CONNECT_T)( VCHI_CONNECTION_STATE_T *state_handle, ++ int32_t service_id, ++ uint32_t rx_fifo_size, ++ uint32_t tx_fifo_size, ++ int server, ++ VCHI_CALLBACK_T callback, ++ void *callback_param, ++ int32_t want_crc, ++ int32_t want_unaligned_bulk_rx, ++ int32_t want_unaligned_bulk_tx, ++ VCHI_CONNECTION_SERVICE_HANDLE_T *service_handle ); ++ ++// Routine to close a service ++typedef int32_t (*VCHI_CONNECTION_SERVICE_DISCONNECT_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle ); ++ ++// Routine to queue a message ++typedef int32_t (*VCHI_CONNECTION_SERVICE_QUEUE_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, ++ const void *data, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void *msg_handle ); ++ ++// scatter-gather (vector) message queueing ++typedef int32_t (*VCHI_CONNECTION_SERVICE_QUEUE_MESSAGEV_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, ++ VCHI_MSG_VECTOR_T *vector, ++ uint32_t count, ++ VCHI_FLAGS_T flags, ++ void *msg_handle ); ++ ++// Routine to dequeue a message ++typedef int32_t (*VCHI_CONNECTION_SERVICE_DEQUEUE_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, ++ void *data, ++ uint32_t max_data_size_to_read, ++ uint32_t *actual_msg_size, ++ VCHI_FLAGS_T flags ); ++ ++// Routine to peek at a message ++typedef int32_t (*VCHI_CONNECTION_SERVICE_PEEK_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, ++ void **data, ++ uint32_t *msg_size, ++ VCHI_FLAGS_T flags ); ++ ++// Routine to hold a message ++typedef int32_t (*VCHI_CONNECTION_SERVICE_HOLD_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, ++ void **data, ++ uint32_t *msg_size, ++ VCHI_FLAGS_T flags, ++ void **message_handle ); ++ ++// Routine to initialise a received message iterator ++typedef int32_t (*VCHI_CONNECTION_SERVICE_LOOKAHEAD_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, ++ VCHI_MSG_ITER_T *iter, ++ VCHI_FLAGS_T flags ); ++ ++// Routine to release a held message ++typedef int32_t (*VCHI_CONNECTION_HELD_MSG_RELEASE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, ++ void *message_handle ); ++ ++// Routine to get info on a held message ++typedef int32_t (*VCHI_CONNECTION_HELD_MSG_INFO_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, ++ void *message_handle, ++ void **data, ++ int32_t *msg_size, ++ uint32_t *tx_timestamp, ++ uint32_t *rx_timestamp ); ++ ++// Routine to check whether the iterator has a next message ++typedef int32_t (*VCHI_CONNECTION_MSG_ITER_HAS_NEXT_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service, ++ const VCHI_MSG_ITER_T *iter ); ++ ++// Routine to advance the iterator ++typedef int32_t (*VCHI_CONNECTION_MSG_ITER_NEXT_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service, ++ VCHI_MSG_ITER_T *iter, ++ void **data, ++ uint32_t *msg_size ); ++ ++// Routine to remove the last message returned by the iterator ++typedef int32_t (*VCHI_CONNECTION_MSG_ITER_REMOVE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service, ++ VCHI_MSG_ITER_T *iter ); ++ ++// Routine to hold the last message returned by the iterator ++typedef int32_t (*VCHI_CONNECTION_MSG_ITER_HOLD_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service, ++ VCHI_MSG_ITER_T *iter, ++ void **msg_handle ); ++ ++// Routine to transmit bulk data ++typedef int32_t (*VCHI_CONNECTION_BULK_QUEUE_TRANSMIT_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, ++ const void *data_src, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void *bulk_handle ); ++ ++// Routine to receive data ++typedef int32_t (*VCHI_CONNECTION_BULK_QUEUE_RECEIVE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, ++ void *data_dst, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void *bulk_handle ); ++ ++// Routine to report if a server is available ++typedef int32_t (*VCHI_CONNECTION_SERVER_PRESENT)( VCHI_CONNECTION_STATE_T *state, int32_t service_id, int32_t peer_flags ); ++ ++// Routine to report the number of RX slots available ++typedef int (*VCHI_CONNECTION_RX_SLOTS_AVAILABLE)( const VCHI_CONNECTION_STATE_T *state ); ++ ++// Routine to report the RX slot size ++typedef uint32_t (*VCHI_CONNECTION_RX_SLOT_SIZE)( const VCHI_CONNECTION_STATE_T *state ); ++ ++// Callback to indicate that the other side has added a buffer to the rx bulk DMA FIFO ++typedef void (*VCHI_CONNECTION_RX_BULK_BUFFER_ADDED)(VCHI_CONNECTION_STATE_T *state, ++ int32_t service, ++ uint32_t length, ++ MESSAGE_TX_CHANNEL_T channel, ++ uint32_t channel_params, ++ uint32_t data_length, ++ uint32_t data_offset); ++ ++// Callback to inform a service that a Xon or Xoff message has been received ++typedef void (*VCHI_CONNECTION_FLOW_CONTROL)(VCHI_CONNECTION_STATE_T *state, int32_t service_id, int32_t xoff); ++ ++// Callback to inform a service that a server available reply message has been received ++typedef void (*VCHI_CONNECTION_SERVER_AVAILABLE_REPLY)(VCHI_CONNECTION_STATE_T *state, int32_t service_id, uint32_t flags); ++ ++// Callback to indicate that bulk auxiliary messages have arrived ++typedef void (*VCHI_CONNECTION_BULK_AUX_RECEIVED)(VCHI_CONNECTION_STATE_T *state); ++ ++// Callback to indicate that bulk auxiliary messages have arrived ++typedef void (*VCHI_CONNECTION_BULK_AUX_TRANSMITTED)(VCHI_CONNECTION_STATE_T *state, void *handle); ++ ++// Callback with all the connection info you require ++typedef void (*VCHI_CONNECTION_INFO)(VCHI_CONNECTION_STATE_T *state, uint32_t protocol_version, uint32_t slot_size, uint32_t num_slots, uint32_t min_bulk_size); ++ ++// Callback to inform of a disconnect ++typedef void (*VCHI_CONNECTION_DISCONNECT)(VCHI_CONNECTION_STATE_T *state, uint32_t flags); ++ ++// Callback to inform of a power control request ++typedef void (*VCHI_CONNECTION_POWER_CONTROL)(VCHI_CONNECTION_STATE_T *state, MESSAGE_TX_CHANNEL_T channel, int32_t enable); ++ ++// allocate memory suitably aligned for this connection ++typedef void * (*VCHI_BUFFER_ALLOCATE)(VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, uint32_t * length); ++ ++// free memory allocated by buffer_allocate ++typedef void (*VCHI_BUFFER_FREE)(VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, void * address); ++ ++ ++/****************************************************************************** ++ System driver struct ++ *****************************************************************************/ ++ ++struct opaque_vchi_connection_api_t ++{ ++ // Routine to init the connection ++ VCHI_CONNECTION_INIT_T init; ++ ++ // Connection-level CRC control ++ VCHI_CONNECTION_CRC_CONTROL_T crc_control; ++ ++ // Routine to connect to or create service ++ VCHI_CONNECTION_SERVICE_CONNECT_T service_connect; ++ ++ // Routine to disconnect from a service ++ VCHI_CONNECTION_SERVICE_DISCONNECT_T service_disconnect; ++ ++ // Routine to queue a message ++ VCHI_CONNECTION_SERVICE_QUEUE_MESSAGE_T service_queue_msg; ++ ++ // scatter-gather (vector) message queue ++ VCHI_CONNECTION_SERVICE_QUEUE_MESSAGEV_T service_queue_msgv; ++ ++ // Routine to dequeue a message ++ VCHI_CONNECTION_SERVICE_DEQUEUE_MESSAGE_T service_dequeue_msg; ++ ++ // Routine to peek at a message ++ VCHI_CONNECTION_SERVICE_PEEK_MESSAGE_T service_peek_msg; ++ ++ // Routine to hold a message ++ VCHI_CONNECTION_SERVICE_HOLD_MESSAGE_T service_hold_msg; ++ ++ // Routine to initialise a received message iterator ++ VCHI_CONNECTION_SERVICE_LOOKAHEAD_MESSAGE_T service_look_ahead_msg; ++ ++ // Routine to release a message ++ VCHI_CONNECTION_HELD_MSG_RELEASE_T held_msg_release; ++ ++ // Routine to get information on a held message ++ VCHI_CONNECTION_HELD_MSG_INFO_T held_msg_info; ++ ++ // Routine to check for next message on iterator ++ VCHI_CONNECTION_MSG_ITER_HAS_NEXT_T msg_iter_has_next; ++ ++ // Routine to get next message on iterator ++ VCHI_CONNECTION_MSG_ITER_NEXT_T msg_iter_next; ++ ++ // Routine to remove the last message returned by iterator ++ VCHI_CONNECTION_MSG_ITER_REMOVE_T msg_iter_remove; ++ ++ // Routine to hold the last message returned by iterator ++ VCHI_CONNECTION_MSG_ITER_HOLD_T msg_iter_hold; ++ ++ // Routine to transmit bulk data ++ VCHI_CONNECTION_BULK_QUEUE_TRANSMIT_T bulk_queue_transmit; ++ ++ // Routine to receive data ++ VCHI_CONNECTION_BULK_QUEUE_RECEIVE_T bulk_queue_receive; ++ ++ // Routine to report the available servers ++ VCHI_CONNECTION_SERVER_PRESENT server_present; ++ ++ // Routine to report the number of RX slots available ++ VCHI_CONNECTION_RX_SLOTS_AVAILABLE connection_rx_slots_available; ++ ++ // Routine to report the RX slot size ++ VCHI_CONNECTION_RX_SLOT_SIZE connection_rx_slot_size; ++ ++ // Callback to indicate that the other side has added a buffer to the rx bulk DMA FIFO ++ VCHI_CONNECTION_RX_BULK_BUFFER_ADDED rx_bulk_buffer_added; ++ ++ // Callback to inform a service that a Xon or Xoff message has been received ++ VCHI_CONNECTION_FLOW_CONTROL flow_control; ++ ++ // Callback to inform a service that a server available reply message has been received ++ VCHI_CONNECTION_SERVER_AVAILABLE_REPLY server_available_reply; ++ ++ // Callback to indicate that bulk auxiliary messages have arrived ++ VCHI_CONNECTION_BULK_AUX_RECEIVED bulk_aux_received; ++ ++ // Callback to indicate that a bulk auxiliary message has been transmitted ++ VCHI_CONNECTION_BULK_AUX_TRANSMITTED bulk_aux_transmitted; ++ ++ // Callback to provide information about the connection ++ VCHI_CONNECTION_INFO connection_info; ++ ++ // Callback to notify that peer has requested disconnect ++ VCHI_CONNECTION_DISCONNECT disconnect; ++ ++ // Callback to notify that peer has requested power change ++ VCHI_CONNECTION_POWER_CONTROL power_control; ++ ++ // allocate memory suitably aligned for this connection ++ VCHI_BUFFER_ALLOCATE buffer_allocate; ++ ++ // free memory allocated by buffer_allocate ++ VCHI_BUFFER_FREE buffer_free; ++ ++}; ++ ++struct vchi_connection_t { ++ const VCHI_CONNECTION_API_T *api; ++ VCHI_CONNECTION_STATE_T *state; ++#ifdef VCHI_COARSE_LOCKING ++ struct semaphore sem; ++#endif ++}; ++ ++ ++#endif /* CONNECTION_H_ */ ++ ++/****************************** End of file **********************************/ +diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchi/message_drivers/message.h linux-rpi/drivers/misc/vc04_services/interface/vchi/message_drivers/message.h +--- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchi/message_drivers/message.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/misc/vc04_services/interface/vchi/message_drivers/message.h 2015-11-29 09:42:38.059222273 +0100 +@@ -0,0 +1,204 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef _VCHI_MESSAGE_H_ ++#define _VCHI_MESSAGE_H_ ++ ++#include ++#include ++#include ++ ++#include "interface/vchi/vchi_cfg_internal.h" ++#include "interface/vchi/vchi_common.h" ++ ++ ++typedef enum message_event_type { ++ MESSAGE_EVENT_NONE, ++ MESSAGE_EVENT_NOP, ++ MESSAGE_EVENT_MESSAGE, ++ MESSAGE_EVENT_SLOT_COMPLETE, ++ MESSAGE_EVENT_RX_BULK_PAUSED, ++ MESSAGE_EVENT_RX_BULK_COMPLETE, ++ MESSAGE_EVENT_TX_COMPLETE, ++ MESSAGE_EVENT_MSG_DISCARDED ++} MESSAGE_EVENT_TYPE_T; ++ ++typedef enum vchi_msg_flags ++{ ++ VCHI_MSG_FLAGS_NONE = 0x0, ++ VCHI_MSG_FLAGS_TERMINATE_DMA = 0x1 ++} VCHI_MSG_FLAGS_T; ++ ++typedef enum message_tx_channel ++{ ++ MESSAGE_TX_CHANNEL_MESSAGE = 0, ++ MESSAGE_TX_CHANNEL_BULK = 1 // drivers may provide multiple bulk channels, from 1 upwards ++} MESSAGE_TX_CHANNEL_T; ++ ++// Macros used for cycling through bulk channels ++#define MESSAGE_TX_CHANNEL_BULK_PREV(c) (MESSAGE_TX_CHANNEL_BULK+((c)-MESSAGE_TX_CHANNEL_BULK+VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION-1)%VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION) ++#define MESSAGE_TX_CHANNEL_BULK_NEXT(c) (MESSAGE_TX_CHANNEL_BULK+((c)-MESSAGE_TX_CHANNEL_BULK+1)%VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION) ++ ++typedef enum message_rx_channel ++{ ++ MESSAGE_RX_CHANNEL_MESSAGE = 0, ++ MESSAGE_RX_CHANNEL_BULK = 1 // drivers may provide multiple bulk channels, from 1 upwards ++} MESSAGE_RX_CHANNEL_T; ++ ++// Message receive slot information ++typedef struct rx_msg_slot_info { ++ ++ struct rx_msg_slot_info *next; ++ //struct slot_info *prev; ++#if !defined VCHI_COARSE_LOCKING ++ struct semaphore sem; ++#endif ++ ++ uint8_t *addr; // base address of slot ++ uint32_t len; // length of slot in bytes ++ ++ uint32_t write_ptr; // hardware causes this to advance ++ uint32_t read_ptr; // this module does the reading ++ int active; // is this slot in the hardware dma fifo? ++ uint32_t msgs_parsed; // count how many messages are in this slot ++ uint32_t msgs_released; // how many messages have been released ++ void *state; // connection state information ++ uint8_t ref_count[VCHI_MAX_SERVICES_PER_CONNECTION]; // reference count for slots held by services ++} RX_MSG_SLOTINFO_T; ++ ++// The message driver no longer needs to know about the fields of RX_BULK_SLOTINFO_T - sort this out. ++// In particular, it mustn't use addr and len - they're the client buffer, but the message ++// driver will be tasked with sending the aligned core section. ++typedef struct rx_bulk_slotinfo_t { ++ struct rx_bulk_slotinfo_t *next; ++ ++ struct semaphore *blocking; ++ ++ // needed by DMA ++ void *addr; ++ uint32_t len; ++ ++ // needed for the callback ++ void *service; ++ void *handle; ++ VCHI_FLAGS_T flags; ++} RX_BULK_SLOTINFO_T; ++ ++ ++/* ---------------------------------------------------------------------- ++ * each connection driver will have a pool of the following struct. ++ * ++ * the pool will be managed by vchi_qman_* ++ * this means there will be multiple queues (single linked lists) ++ * a given struct message_info will be on exactly one of these queues ++ * at any one time ++ * -------------------------------------------------------------------- */ ++typedef struct rx_message_info { ++ ++ struct message_info *next; ++ //struct message_info *prev; ++ ++ uint8_t *addr; ++ uint32_t len; ++ RX_MSG_SLOTINFO_T *slot; // points to whichever slot contains this message ++ uint32_t tx_timestamp; ++ uint32_t rx_timestamp; ++ ++} RX_MESSAGE_INFO_T; ++ ++typedef struct { ++ MESSAGE_EVENT_TYPE_T type; ++ ++ struct { ++ // for messages ++ void *addr; // address of message ++ uint16_t slot_delta; // whether this message indicated slot delta ++ uint32_t len; // length of message ++ RX_MSG_SLOTINFO_T *slot; // slot this message is in ++ int32_t service; // service id this message is destined for ++ uint32_t tx_timestamp; // timestamp from the header ++ uint32_t rx_timestamp; // timestamp when we parsed it ++ } message; ++ ++ // FIXME: cleanup slot reporting... ++ RX_MSG_SLOTINFO_T *rx_msg; ++ RX_BULK_SLOTINFO_T *rx_bulk; ++ void *tx_handle; ++ MESSAGE_TX_CHANNEL_T tx_channel; ++ ++} MESSAGE_EVENT_T; ++ ++ ++// callbacks ++typedef void VCHI_MESSAGE_DRIVER_EVENT_CALLBACK_T( void *state ); ++ ++typedef struct { ++ VCHI_MESSAGE_DRIVER_EVENT_CALLBACK_T *event_callback; ++} VCHI_MESSAGE_DRIVER_OPEN_T; ++ ++ ++// handle to this instance of message driver (as returned by ->open) ++typedef struct opaque_mhandle_t *VCHI_MDRIVER_HANDLE_T; ++ ++struct opaque_vchi_message_driver_t { ++ VCHI_MDRIVER_HANDLE_T *(*open)( VCHI_MESSAGE_DRIVER_OPEN_T *params, void *state ); ++ int32_t (*suspending)( VCHI_MDRIVER_HANDLE_T *handle ); ++ int32_t (*resumed)( VCHI_MDRIVER_HANDLE_T *handle ); ++ int32_t (*power_control)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T, int32_t enable ); ++ int32_t (*add_msg_rx_slot)( VCHI_MDRIVER_HANDLE_T *handle, RX_MSG_SLOTINFO_T *slot ); // rx message ++ int32_t (*add_bulk_rx)( VCHI_MDRIVER_HANDLE_T *handle, void *data, uint32_t len, RX_BULK_SLOTINFO_T *slot ); // rx data (bulk) ++ int32_t (*send)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel, const void *data, uint32_t len, VCHI_MSG_FLAGS_T flags, void *send_handle ); // tx (message & bulk) ++ void (*next_event)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_EVENT_T *event ); // get the next event from message_driver ++ int32_t (*enable)( VCHI_MDRIVER_HANDLE_T *handle ); ++ int32_t (*form_message)( VCHI_MDRIVER_HANDLE_T *handle, int32_t service_id, VCHI_MSG_VECTOR_T *vector, uint32_t count, void ++ *address, uint32_t length_avail, uint32_t max_total_length, int32_t pad_to_fill, int32_t allow_partial ); ++ ++ int32_t (*update_message)( VCHI_MDRIVER_HANDLE_T *handle, void *dest, int16_t *slot_count ); ++ int32_t (*buffer_aligned)( VCHI_MDRIVER_HANDLE_T *handle, int tx, int uncached, const void *address, const uint32_t length ); ++ void * (*allocate_buffer)( VCHI_MDRIVER_HANDLE_T *handle, uint32_t *length ); ++ void (*free_buffer)( VCHI_MDRIVER_HANDLE_T *handle, void *address ); ++ int (*rx_slot_size)( VCHI_MDRIVER_HANDLE_T *handle, int msg_size ); ++ int (*tx_slot_size)( VCHI_MDRIVER_HANDLE_T *handle, int msg_size ); ++ ++ int32_t (*tx_supports_terminate)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel ); ++ uint32_t (*tx_bulk_chunk_size)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel ); ++ int (*tx_alignment)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel ); ++ int (*rx_alignment)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_RX_CHANNEL_T channel ); ++ void (*form_bulk_aux)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel, const void *data, uint32_t len, uint32_t chunk_size, const void **aux_data, int32_t *aux_len ); ++ void (*debug)( VCHI_MDRIVER_HANDLE_T *handle ); ++}; ++ ++ ++#endif // _VCHI_MESSAGE_H_ ++ ++/****************************** End of file ***********************************/ +diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchi/vchi_cfg.h linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi_cfg.h +--- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchi/vchi_cfg.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi_cfg.h 2015-11-29 09:42:38.059222273 +0100 +@@ -0,0 +1,224 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHI_CFG_H_ ++#define VCHI_CFG_H_ ++ ++/**************************************************************************************** ++ * Defines in this first section are part of the VCHI API and may be examined by VCHI ++ * services. ++ ***************************************************************************************/ ++ ++/* Required alignment of base addresses for bulk transfer, if unaligned transfers are not enabled */ ++/* Really determined by the message driver, and should be available from a run-time call. */ ++#ifndef VCHI_BULK_ALIGN ++# if __VCCOREVER__ >= 0x04000000 ++# define VCHI_BULK_ALIGN 32 // Allows for the need to do cache cleans ++# else ++# define VCHI_BULK_ALIGN 16 ++# endif ++#endif ++ ++/* Required length multiple for bulk transfers, if unaligned transfers are not enabled */ ++/* May be less than or greater than VCHI_BULK_ALIGN */ ++/* Really determined by the message driver, and should be available from a run-time call. */ ++#ifndef VCHI_BULK_GRANULARITY ++# if __VCCOREVER__ >= 0x04000000 ++# define VCHI_BULK_GRANULARITY 32 // Allows for the need to do cache cleans ++# else ++# define VCHI_BULK_GRANULARITY 16 ++# endif ++#endif ++ ++/* The largest possible message to be queued with vchi_msg_queue. */ ++#ifndef VCHI_MAX_MSG_SIZE ++# if defined VCHI_LOCAL_HOST_PORT ++# define VCHI_MAX_MSG_SIZE 16384 // makes file transfers fast, but should they be using bulk? ++# else ++# define VCHI_MAX_MSG_SIZE 4096 // NOTE: THIS MUST BE LARGER THAN OR EQUAL TO THE SIZE OF THE KHRONOS MERGE BUFFER!! ++# endif ++#endif ++ ++/****************************************************************************************** ++ * Defines below are system configuration options, and should not be used by VCHI services. ++ *****************************************************************************************/ ++ ++/* How many connections can we support? A localhost implementation uses 2 connections, ++ * 1 for host-app, 1 for VMCS, and these are hooked together by a loopback MPHI VCFW ++ * driver. */ ++#ifndef VCHI_MAX_NUM_CONNECTIONS ++# define VCHI_MAX_NUM_CONNECTIONS 3 ++#endif ++ ++/* How many services can we open per connection? Extending this doesn't cost processing time, just a small ++ * amount of static memory. */ ++#ifndef VCHI_MAX_SERVICES_PER_CONNECTION ++# define VCHI_MAX_SERVICES_PER_CONNECTION 36 ++#endif ++ ++/* Adjust if using a message driver that supports more logical TX channels */ ++#ifndef VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION ++# define VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION 9 // 1 MPHI + 8 CCP2 logical channels ++#endif ++ ++/* Adjust if using a message driver that supports more logical RX channels */ ++#ifndef VCHI_MAX_BULK_RX_CHANNELS_PER_CONNECTION ++# define VCHI_MAX_BULK_RX_CHANNELS_PER_CONNECTION 1 // 1 MPHI ++#endif ++ ++/* How many receive slots do we use. This times VCHI_MAX_MSG_SIZE gives the effective ++ * receive queue space, less message headers. */ ++#ifndef VCHI_NUM_READ_SLOTS ++# if defined(VCHI_LOCAL_HOST_PORT) ++# define VCHI_NUM_READ_SLOTS 4 ++# else ++# define VCHI_NUM_READ_SLOTS 48 ++# endif ++#endif ++ ++/* Do we utilise overrun facility for receive message slots? Can aid peer transmit ++ * performance. Only define on VideoCore end, talking to host. ++ */ ++//#define VCHI_MSG_RX_OVERRUN ++ ++/* How many transmit slots do we use. Generally don't need many, as the hardware driver ++ * underneath VCHI will usually have its own buffering. */ ++#ifndef VCHI_NUM_WRITE_SLOTS ++# define VCHI_NUM_WRITE_SLOTS 4 ++#endif ++ ++/* If a service has held or queued received messages in VCHI_XOFF_THRESHOLD or more slots, ++ * then it's taking up too much buffer space, and the peer service will be told to stop ++ * transmitting with an XOFF message. For this to be effective, the VCHI_NUM_READ_SLOTS ++ * needs to be considerably bigger than VCHI_NUM_WRITE_SLOTS, or the transmit latency ++ * is too high. */ ++#ifndef VCHI_XOFF_THRESHOLD ++# define VCHI_XOFF_THRESHOLD (VCHI_NUM_READ_SLOTS / 2) ++#endif ++ ++/* After we've sent an XOFF, the peer will be told to resume transmission once the local ++ * service has dequeued/released enough messages that it's now occupying ++ * VCHI_XON_THRESHOLD slots or fewer. */ ++#ifndef VCHI_XON_THRESHOLD ++# define VCHI_XON_THRESHOLD (VCHI_NUM_READ_SLOTS / 4) ++#endif ++ ++/* A size below which a bulk transfer omits the handshake completely and always goes ++ * via the message channel, if bulk auxiliary is being sent on that service. (The user ++ * can guarantee this by enabling unaligned transmits). ++ * Not API. */ ++#ifndef VCHI_MIN_BULK_SIZE ++# define VCHI_MIN_BULK_SIZE ( VCHI_MAX_MSG_SIZE / 2 < 4096 ? VCHI_MAX_MSG_SIZE / 2 : 4096 ) ++#endif ++ ++/* Maximum size of bulk transmission chunks, for each interface type. A trade-off between ++ * speed and latency; the smaller the chunk size the better change of messages and other ++ * bulk transmissions getting in when big bulk transfers are happening. Set to 0 to not ++ * break transmissions into chunks. ++ */ ++#ifndef VCHI_MAX_BULK_CHUNK_SIZE_MPHI ++# define VCHI_MAX_BULK_CHUNK_SIZE_MPHI (16 * 1024) ++#endif ++ ++/* NB Chunked CCP2 transmissions violate the letter of the CCP2 spec by using "JPEG8" mode ++ * with multiple-line frames. Only use if the receiver can cope. */ ++#ifndef VCHI_MAX_BULK_CHUNK_SIZE_CCP2 ++# define VCHI_MAX_BULK_CHUNK_SIZE_CCP2 0 ++#endif ++ ++/* How many TX messages can we have pending in our transmit slots. Once exhausted, ++ * vchi_msg_queue will be blocked. */ ++#ifndef VCHI_TX_MSG_QUEUE_SIZE ++# define VCHI_TX_MSG_QUEUE_SIZE 256 ++#endif ++ ++/* How many RX messages can we have parsed in the receive slots. Once exhausted, parsing ++ * will be suspended until older messages are dequeued/released. */ ++#ifndef VCHI_RX_MSG_QUEUE_SIZE ++# define VCHI_RX_MSG_QUEUE_SIZE 256 ++#endif ++ ++/* Really should be able to cope if we run out of received message descriptors, by ++ * suspending parsing as the comment above says, but we don't. This sweeps the issue ++ * under the carpet. */ ++#if VCHI_RX_MSG_QUEUE_SIZE < (VCHI_MAX_MSG_SIZE/16 + 1) * VCHI_NUM_READ_SLOTS ++# undef VCHI_RX_MSG_QUEUE_SIZE ++# define VCHI_RX_MSG_QUEUE_SIZE (VCHI_MAX_MSG_SIZE/16 + 1) * VCHI_NUM_READ_SLOTS ++#endif ++ ++/* How many bulk transmits can we have pending. Once exhausted, vchi_bulk_queue_transmit ++ * will be blocked. */ ++#ifndef VCHI_TX_BULK_QUEUE_SIZE ++# define VCHI_TX_BULK_QUEUE_SIZE 64 ++#endif ++ ++/* How many bulk receives can we have pending. Once exhausted, vchi_bulk_queue_receive ++ * will be blocked. */ ++#ifndef VCHI_RX_BULK_QUEUE_SIZE ++# define VCHI_RX_BULK_QUEUE_SIZE 64 ++#endif ++ ++/* A limit on how many outstanding bulk requests we expect the peer to give us. If ++ * the peer asks for more than this, VCHI will fail and assert. The number is determined ++ * by the peer's hardware - it's the number of outstanding requests that can be queued ++ * on all bulk channels. VC3's MPHI peripheral allows 16. */ ++#ifndef VCHI_MAX_PEER_BULK_REQUESTS ++# define VCHI_MAX_PEER_BULK_REQUESTS 32 ++#endif ++ ++/* Define VCHI_CCP2TX_MANUAL_POWER if the host tells us when to turn the CCP2 ++ * transmitter on and off. ++ */ ++/*#define VCHI_CCP2TX_MANUAL_POWER*/ ++ ++#ifndef VCHI_CCP2TX_MANUAL_POWER ++ ++/* Timeout (in milliseconds) for putting the CCP2TX interface into IDLE state. Set ++ * negative for no IDLE. ++ */ ++# ifndef VCHI_CCP2TX_IDLE_TIMEOUT ++# define VCHI_CCP2TX_IDLE_TIMEOUT 5 ++# endif ++ ++/* Timeout (in milliseconds) for putting the CCP2TX interface into OFF state. Set ++ * negative for no OFF. ++ */ ++# ifndef VCHI_CCP2TX_OFF_TIMEOUT ++# define VCHI_CCP2TX_OFF_TIMEOUT 1000 ++# endif ++ ++#endif /* VCHI_CCP2TX_MANUAL_POWER */ ++ ++#endif /* VCHI_CFG_H_ */ ++ ++/****************************** End of file **********************************/ +diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchi/vchi_cfg_internal.h linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi_cfg_internal.h +--- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchi/vchi_cfg_internal.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi_cfg_internal.h 2015-11-29 09:42:38.059222273 +0100 +@@ -0,0 +1,71 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHI_CFG_INTERNAL_H_ ++#define VCHI_CFG_INTERNAL_H_ ++ ++/**************************************************************************************** ++ * Control optimisation attempts. ++ ***************************************************************************************/ ++ ++// Don't use lots of short-term locks - use great long ones, reducing the overall locks-per-second ++#define VCHI_COARSE_LOCKING ++ ++// Avoid lock then unlock on exit from blocking queue operations (msg tx, bulk rx/tx) ++// (only relevant if VCHI_COARSE_LOCKING) ++#define VCHI_ELIDE_BLOCK_EXIT_LOCK ++ ++// Avoid lock on non-blocking peek ++// (only relevant if VCHI_COARSE_LOCKING) ++#define VCHI_AVOID_PEEK_LOCK ++ ++// Use one slot-handler thread per connection, rather than 1 thread dealing with all connections in rotation. ++#define VCHI_MULTIPLE_HANDLER_THREADS ++ ++// Put free descriptors onto the head of the free queue, rather than the tail, so that we don't thrash ++// our way through the pool of descriptors. ++#define VCHI_PUSH_FREE_DESCRIPTORS_ONTO_HEAD ++ ++// Don't issue a MSG_AVAILABLE callback for every single message. Possibly only safe if VCHI_COARSE_LOCKING. ++#define VCHI_FEWER_MSG_AVAILABLE_CALLBACKS ++ ++// Don't use message descriptors for TX messages that don't need them ++#define VCHI_MINIMISE_TX_MSG_DESCRIPTORS ++ ++// Nano-locks for multiqueue ++//#define VCHI_MQUEUE_NANOLOCKS ++ ++// Lock-free(er) dequeuing ++//#define VCHI_RX_NANOLOCKS ++ ++#endif /*VCHI_CFG_INTERNAL_H_*/ +diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchi/vchi_common.h linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi_common.h +--- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchi/vchi_common.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi_common.h 2015-11-29 09:42:38.059222273 +0100 +@@ -0,0 +1,175 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHI_COMMON_H_ ++#define VCHI_COMMON_H_ ++ ++ ++//flags used when sending messages (must be bitmapped) ++typedef enum ++{ ++ VCHI_FLAGS_NONE = 0x0, ++ VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE = 0x1, // waits for message to be received, or sent (NB. not the same as being seen on other side) ++ VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE = 0x2, // run a callback when message sent ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED = 0x4, // return once the transfer is in a queue ready to go ++ VCHI_FLAGS_ALLOW_PARTIAL = 0x8, ++ VCHI_FLAGS_BLOCK_UNTIL_DATA_READ = 0x10, ++ VCHI_FLAGS_CALLBACK_WHEN_DATA_READ = 0x20, ++ ++ VCHI_FLAGS_ALIGN_SLOT = 0x000080, // internal use only ++ VCHI_FLAGS_BULK_AUX_QUEUED = 0x010000, // internal use only ++ VCHI_FLAGS_BULK_AUX_COMPLETE = 0x020000, // internal use only ++ VCHI_FLAGS_BULK_DATA_QUEUED = 0x040000, // internal use only ++ VCHI_FLAGS_BULK_DATA_COMPLETE = 0x080000, // internal use only ++ VCHI_FLAGS_INTERNAL = 0xFF0000 ++} VCHI_FLAGS_T; ++ ++// constants for vchi_crc_control() ++typedef enum { ++ VCHI_CRC_NOTHING = -1, ++ VCHI_CRC_PER_SERVICE = 0, ++ VCHI_CRC_EVERYTHING = 1, ++} VCHI_CRC_CONTROL_T; ++ ++//callback reasons when an event occurs on a service ++typedef enum ++{ ++ VCHI_CALLBACK_REASON_MIN, ++ ++ //This indicates that there is data available ++ //handle is the msg id that was transmitted with the data ++ // When a message is received and there was no FULL message available previously, send callback ++ // Tasks get kicked by the callback, reset their event and try and read from the fifo until it fails ++ VCHI_CALLBACK_MSG_AVAILABLE, ++ VCHI_CALLBACK_MSG_SENT, ++ VCHI_CALLBACK_MSG_SPACE_AVAILABLE, // XXX not yet implemented ++ ++ // This indicates that a transfer from the other side has completed ++ VCHI_CALLBACK_BULK_RECEIVED, ++ //This indicates that data queued up to be sent has now gone ++ //handle is the msg id that was used when sending the data ++ VCHI_CALLBACK_BULK_SENT, ++ VCHI_CALLBACK_BULK_RX_SPACE_AVAILABLE, // XXX not yet implemented ++ VCHI_CALLBACK_BULK_TX_SPACE_AVAILABLE, // XXX not yet implemented ++ ++ VCHI_CALLBACK_SERVICE_CLOSED, ++ ++ // this side has sent XOFF to peer due to lack of data consumption by service ++ // (suggests the service may need to take some recovery action if it has ++ // been deliberately holding off consuming data) ++ VCHI_CALLBACK_SENT_XOFF, ++ VCHI_CALLBACK_SENT_XON, ++ ++ // indicates that a bulk transfer has finished reading the source buffer ++ VCHI_CALLBACK_BULK_DATA_READ, ++ ++ // power notification events (currently host side only) ++ VCHI_CALLBACK_PEER_OFF, ++ VCHI_CALLBACK_PEER_SUSPENDED, ++ VCHI_CALLBACK_PEER_ON, ++ VCHI_CALLBACK_PEER_RESUMED, ++ VCHI_CALLBACK_FORCED_POWER_OFF, ++ ++#ifdef USE_VCHIQ_ARM ++ // some extra notifications provided by vchiq_arm ++ VCHI_CALLBACK_SERVICE_OPENED, ++ VCHI_CALLBACK_BULK_RECEIVE_ABORTED, ++ VCHI_CALLBACK_BULK_TRANSMIT_ABORTED, ++#endif ++ ++ VCHI_CALLBACK_REASON_MAX ++} VCHI_CALLBACK_REASON_T; ++ ++// service control options ++typedef enum ++{ ++ VCHI_SERVICE_OPTION_MIN, ++ ++ VCHI_SERVICE_OPTION_TRACE, ++ VCHI_SERVICE_OPTION_SYNCHRONOUS, ++ ++ VCHI_SERVICE_OPTION_MAX ++} VCHI_SERVICE_OPTION_T; ++ ++ ++//Callback used by all services / bulk transfers ++typedef void (*VCHI_CALLBACK_T)( void *callback_param, //my service local param ++ VCHI_CALLBACK_REASON_T reason, ++ void *handle ); //for transmitting msg's only ++ ++ ++ ++/* ++ * Define vector struct for scatter-gather (vector) operations ++ * Vectors can be nested - if a vector element has negative length, then ++ * the data pointer is treated as pointing to another vector array, with ++ * '-vec_len' elements. Thus to append a header onto an existing vector, ++ * you can do this: ++ * ++ * void foo(const VCHI_MSG_VECTOR_T *v, int n) ++ * { ++ * VCHI_MSG_VECTOR_T nv[2]; ++ * nv[0].vec_base = my_header; ++ * nv[0].vec_len = sizeof my_header; ++ * nv[1].vec_base = v; ++ * nv[1].vec_len = -n; ++ * ... ++ * ++ */ ++typedef struct vchi_msg_vector { ++ const void *vec_base; ++ int32_t vec_len; ++} VCHI_MSG_VECTOR_T; ++ ++// Opaque type for a connection API ++typedef struct opaque_vchi_connection_api_t VCHI_CONNECTION_API_T; ++ ++// Opaque type for a message driver ++typedef struct opaque_vchi_message_driver_t VCHI_MESSAGE_DRIVER_T; ++ ++ ++// Iterator structure for reading ahead through received message queue. Allocated by client, ++// initialised by vchi_msg_look_ahead. Fields are for internal VCHI use only. ++// Iterates over messages in queue at the instant of the call to vchi_msg_lookahead - ++// will not proceed to messages received since. Behaviour is undefined if an iterator ++// is used again after messages for that service are removed/dequeued by any ++// means other than vchi_msg_iter_... calls on the iterator itself. ++typedef struct { ++ struct opaque_vchi_service_t *service; ++ void *last; ++ void *next; ++ void *remove; ++} VCHI_MSG_ITER_T; ++ ++ ++#endif // VCHI_COMMON_H_ +diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchi/vchi.h linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi.h +--- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchi/vchi.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi.h 2015-11-29 09:42:38.059222273 +0100 +@@ -0,0 +1,378 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHI_H_ ++#define VCHI_H_ ++ ++#include "interface/vchi/vchi_cfg.h" ++#include "interface/vchi/vchi_common.h" ++#include "interface/vchi/connections/connection.h" ++#include "vchi_mh.h" ++ ++ ++/****************************************************************************** ++ Global defs ++ *****************************************************************************/ ++ ++#define VCHI_BULK_ROUND_UP(x) ((((unsigned long)(x))+VCHI_BULK_ALIGN-1) & ~(VCHI_BULK_ALIGN-1)) ++#define VCHI_BULK_ROUND_DOWN(x) (((unsigned long)(x)) & ~(VCHI_BULK_ALIGN-1)) ++#define VCHI_BULK_ALIGN_NBYTES(x) (VCHI_BULK_ALIGNED(x) ? 0 : (VCHI_BULK_ALIGN - ((unsigned long)(x) & (VCHI_BULK_ALIGN-1)))) ++ ++#ifdef USE_VCHIQ_ARM ++#define VCHI_BULK_ALIGNED(x) 1 ++#else ++#define VCHI_BULK_ALIGNED(x) (((unsigned long)(x) & (VCHI_BULK_ALIGN-1)) == 0) ++#endif ++ ++struct vchi_version { ++ uint32_t version; ++ uint32_t version_min; ++}; ++#define VCHI_VERSION(v_) { v_, v_ } ++#define VCHI_VERSION_EX(v_, m_) { v_, m_ } ++ ++typedef enum ++{ ++ VCHI_VEC_POINTER, ++ VCHI_VEC_HANDLE, ++ VCHI_VEC_LIST ++} VCHI_MSG_VECTOR_TYPE_T; ++ ++typedef struct vchi_msg_vector_ex { ++ ++ VCHI_MSG_VECTOR_TYPE_T type; ++ union ++ { ++ // a memory handle ++ struct ++ { ++ VCHI_MEM_HANDLE_T handle; ++ uint32_t offset; ++ int32_t vec_len; ++ } handle; ++ ++ // an ordinary data pointer ++ struct ++ { ++ const void *vec_base; ++ int32_t vec_len; ++ } ptr; ++ ++ // a nested vector list ++ struct ++ { ++ struct vchi_msg_vector_ex *vec; ++ uint32_t vec_len; ++ } list; ++ } u; ++} VCHI_MSG_VECTOR_EX_T; ++ ++ ++// Construct an entry in a msg vector for a pointer (p) of length (l) ++#define VCHI_VEC_POINTER(p,l) VCHI_VEC_POINTER, { { (VCHI_MEM_HANDLE_T)(p), (l) } } ++ ++// Construct an entry in a msg vector for a message handle (h), starting at offset (o) of length (l) ++#define VCHI_VEC_HANDLE(h,o,l) VCHI_VEC_HANDLE, { { (h), (o), (l) } } ++ ++// Macros to manipulate 'FOURCC' values ++#define MAKE_FOURCC(x) ((int32_t)( (x[0] << 24) | (x[1] << 16) | (x[2] << 8) | x[3] )) ++#define FOURCC_TO_CHAR(x) (x >> 24) & 0xFF,(x >> 16) & 0xFF,(x >> 8) & 0xFF, x & 0xFF ++ ++ ++// Opaque service information ++struct opaque_vchi_service_t; ++ ++// Descriptor for a held message. Allocated by client, initialised by vchi_msg_hold, ++// vchi_msg_iter_hold or vchi_msg_iter_hold_next. Fields are for internal VCHI use only. ++typedef struct ++{ ++ struct opaque_vchi_service_t *service; ++ void *message; ++} VCHI_HELD_MSG_T; ++ ++ ++ ++// structure used to provide the information needed to open a server or a client ++typedef struct { ++ struct vchi_version version; ++ int32_t service_id; ++ VCHI_CONNECTION_T *connection; ++ uint32_t rx_fifo_size; ++ uint32_t tx_fifo_size; ++ VCHI_CALLBACK_T callback; ++ void *callback_param; ++ /* client intends to receive bulk transfers of ++ odd lengths or into unaligned buffers */ ++ int32_t want_unaligned_bulk_rx; ++ /* client intends to transmit bulk transfers of ++ odd lengths or out of unaligned buffers */ ++ int32_t want_unaligned_bulk_tx; ++ /* client wants to check CRCs on (bulk) xfers. ++ Only needs to be set at 1 end - will do both directions. */ ++ int32_t want_crc; ++} SERVICE_CREATION_T; ++ ++// Opaque handle for a VCHI instance ++typedef struct opaque_vchi_instance_handle_t *VCHI_INSTANCE_T; ++ ++// Opaque handle for a server or client ++typedef struct opaque_vchi_service_handle_t *VCHI_SERVICE_HANDLE_T; ++ ++// Service registration & startup ++typedef void (*VCHI_SERVICE_INIT)(VCHI_INSTANCE_T initialise_instance, VCHI_CONNECTION_T **connections, uint32_t num_connections); ++ ++typedef struct service_info_tag { ++ const char * const vll_filename; /* VLL to load to start this service. This is an empty string if VLL is "static" */ ++ VCHI_SERVICE_INIT init; /* Service initialisation function */ ++ void *vll_handle; /* VLL handle; NULL when unloaded or a "static VLL" in build */ ++} SERVICE_INFO_T; ++ ++/****************************************************************************** ++ Global funcs - implementation is specific to which side you are on (local / remote) ++ *****************************************************************************/ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++extern /*@observer@*/ VCHI_CONNECTION_T * vchi_create_connection( const VCHI_CONNECTION_API_T * function_table, ++ const VCHI_MESSAGE_DRIVER_T * low_level); ++ ++ ++// Routine used to initialise the vchi on both local + remote connections ++extern int32_t vchi_initialise( VCHI_INSTANCE_T *instance_handle ); ++ ++extern int32_t vchi_exit( void ); ++ ++extern int32_t vchi_connect( VCHI_CONNECTION_T **connections, ++ const uint32_t num_connections, ++ VCHI_INSTANCE_T instance_handle ); ++ ++//When this is called, ensure that all services have no data pending. ++//Bulk transfers can remain 'queued' ++extern int32_t vchi_disconnect( VCHI_INSTANCE_T instance_handle ); ++ ++// Global control over bulk CRC checking ++extern int32_t vchi_crc_control( VCHI_CONNECTION_T *connection, ++ VCHI_CRC_CONTROL_T control ); ++ ++// helper functions ++extern void * vchi_allocate_buffer(VCHI_SERVICE_HANDLE_T handle, uint32_t *length); ++extern void vchi_free_buffer(VCHI_SERVICE_HANDLE_T handle, void *address); ++extern uint32_t vchi_current_time(VCHI_INSTANCE_T instance_handle); ++ ++ ++/****************************************************************************** ++ Global service API ++ *****************************************************************************/ ++// Routine to create a named service ++extern int32_t vchi_service_create( VCHI_INSTANCE_T instance_handle, ++ SERVICE_CREATION_T *setup, ++ VCHI_SERVICE_HANDLE_T *handle ); ++ ++// Routine to destory a service ++extern int32_t vchi_service_destroy( const VCHI_SERVICE_HANDLE_T handle ); ++ ++// Routine to open a named service ++extern int32_t vchi_service_open( VCHI_INSTANCE_T instance_handle, ++ SERVICE_CREATION_T *setup, ++ VCHI_SERVICE_HANDLE_T *handle); ++ ++extern int32_t vchi_get_peer_version( const VCHI_SERVICE_HANDLE_T handle, ++ short *peer_version ); ++ ++// Routine to close a named service ++extern int32_t vchi_service_close( const VCHI_SERVICE_HANDLE_T handle ); ++ ++// Routine to increment ref count on a named service ++extern int32_t vchi_service_use( const VCHI_SERVICE_HANDLE_T handle ); ++ ++// Routine to decrement ref count on a named service ++extern int32_t vchi_service_release( const VCHI_SERVICE_HANDLE_T handle ); ++ ++// Routine to set a control option for a named service ++extern int32_t vchi_service_set_option( const VCHI_SERVICE_HANDLE_T handle, ++ VCHI_SERVICE_OPTION_T option, ++ int value); ++ ++// Routine to send a message across a service ++extern int32_t vchi_msg_queue( VCHI_SERVICE_HANDLE_T handle, ++ const void *data, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void *msg_handle ); ++ ++// scatter-gather (vector) and send message ++int32_t vchi_msg_queuev_ex( VCHI_SERVICE_HANDLE_T handle, ++ VCHI_MSG_VECTOR_EX_T *vector, ++ uint32_t count, ++ VCHI_FLAGS_T flags, ++ void *msg_handle ); ++ ++// legacy scatter-gather (vector) and send message, only handles pointers ++int32_t vchi_msg_queuev( VCHI_SERVICE_HANDLE_T handle, ++ VCHI_MSG_VECTOR_T *vector, ++ uint32_t count, ++ VCHI_FLAGS_T flags, ++ void *msg_handle ); ++ ++// Routine to receive a msg from a service ++// Dequeue is equivalent to hold, copy into client buffer, release ++extern int32_t vchi_msg_dequeue( VCHI_SERVICE_HANDLE_T handle, ++ void *data, ++ uint32_t max_data_size_to_read, ++ uint32_t *actual_msg_size, ++ VCHI_FLAGS_T flags ); ++ ++// Routine to look at a message in place. ++// The message is not dequeued, so a subsequent call to peek or dequeue ++// will return the same message. ++extern int32_t vchi_msg_peek( VCHI_SERVICE_HANDLE_T handle, ++ void **data, ++ uint32_t *msg_size, ++ VCHI_FLAGS_T flags ); ++ ++// Routine to remove a message after it has been read in place with peek ++// The first message on the queue is dequeued. ++extern int32_t vchi_msg_remove( VCHI_SERVICE_HANDLE_T handle ); ++ ++// Routine to look at a message in place. ++// The message is dequeued, so the caller is left holding it; the descriptor is ++// filled in and must be released when the user has finished with the message. ++extern int32_t vchi_msg_hold( VCHI_SERVICE_HANDLE_T handle, ++ void **data, // } may be NULL, as info can be ++ uint32_t *msg_size, // } obtained from HELD_MSG_T ++ VCHI_FLAGS_T flags, ++ VCHI_HELD_MSG_T *message_descriptor ); ++ ++// Initialise an iterator to look through messages in place ++extern int32_t vchi_msg_look_ahead( VCHI_SERVICE_HANDLE_T handle, ++ VCHI_MSG_ITER_T *iter, ++ VCHI_FLAGS_T flags ); ++ ++/****************************************************************************** ++ Global service support API - operations on held messages and message iterators ++ *****************************************************************************/ ++ ++// Routine to get the address of a held message ++extern void *vchi_held_msg_ptr( const VCHI_HELD_MSG_T *message ); ++ ++// Routine to get the size of a held message ++extern int32_t vchi_held_msg_size( const VCHI_HELD_MSG_T *message ); ++ ++// Routine to get the transmit timestamp as written into the header by the peer ++extern uint32_t vchi_held_msg_tx_timestamp( const VCHI_HELD_MSG_T *message ); ++ ++// Routine to get the reception timestamp, written as we parsed the header ++extern uint32_t vchi_held_msg_rx_timestamp( const VCHI_HELD_MSG_T *message ); ++ ++// Routine to release a held message after it has been processed ++extern int32_t vchi_held_msg_release( VCHI_HELD_MSG_T *message ); ++ ++// Indicates whether the iterator has a next message. ++extern int32_t vchi_msg_iter_has_next( const VCHI_MSG_ITER_T *iter ); ++ ++// Return the pointer and length for the next message and advance the iterator. ++extern int32_t vchi_msg_iter_next( VCHI_MSG_ITER_T *iter, ++ void **data, ++ uint32_t *msg_size ); ++ ++// Remove the last message returned by vchi_msg_iter_next. ++// Can only be called once after each call to vchi_msg_iter_next. ++extern int32_t vchi_msg_iter_remove( VCHI_MSG_ITER_T *iter ); ++ ++// Hold the last message returned by vchi_msg_iter_next. ++// Can only be called once after each call to vchi_msg_iter_next. ++extern int32_t vchi_msg_iter_hold( VCHI_MSG_ITER_T *iter, ++ VCHI_HELD_MSG_T *message ); ++ ++// Return information for the next message, and hold it, advancing the iterator. ++extern int32_t vchi_msg_iter_hold_next( VCHI_MSG_ITER_T *iter, ++ void **data, // } may be NULL ++ uint32_t *msg_size, // } ++ VCHI_HELD_MSG_T *message ); ++ ++ ++/****************************************************************************** ++ Global bulk API ++ *****************************************************************************/ ++ ++// Routine to prepare interface for a transfer from the other side ++extern int32_t vchi_bulk_queue_receive( VCHI_SERVICE_HANDLE_T handle, ++ void *data_dst, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void *transfer_handle ); ++ ++ ++// Prepare interface for a transfer from the other side into relocatable memory. ++int32_t vchi_bulk_queue_receive_reloc( const VCHI_SERVICE_HANDLE_T handle, ++ VCHI_MEM_HANDLE_T h_dst, ++ uint32_t offset, ++ uint32_t data_size, ++ const VCHI_FLAGS_T flags, ++ void * const bulk_handle ); ++ ++// Routine to queue up data ready for transfer to the other (once they have signalled they are ready) ++extern int32_t vchi_bulk_queue_transmit( VCHI_SERVICE_HANDLE_T handle, ++ const void *data_src, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void *transfer_handle ); ++ ++ ++/****************************************************************************** ++ Configuration plumbing ++ *****************************************************************************/ ++ ++// function prototypes for the different mid layers (the state info gives the different physical connections) ++extern const VCHI_CONNECTION_API_T *single_get_func_table( void ); ++//extern const VCHI_CONNECTION_API_T *local_server_get_func_table( void ); ++//extern const VCHI_CONNECTION_API_T *local_client_get_func_table( void ); ++ ++// declare all message drivers here ++const VCHI_MESSAGE_DRIVER_T *vchi_mphi_message_driver_func_table( void ); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++extern int32_t vchi_bulk_queue_transmit_reloc( VCHI_SERVICE_HANDLE_T handle, ++ VCHI_MEM_HANDLE_T h_src, ++ uint32_t offset, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void *transfer_handle ); ++#endif /* VCHI_H_ */ ++ ++/****************************** End of file **********************************/ +diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchi/vchi_mh.h linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi_mh.h +--- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchi/vchi_mh.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/misc/vc04_services/interface/vchi/vchi_mh.h 2015-11-29 09:42:38.059222273 +0100 +@@ -0,0 +1,42 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHI_MH_H_ ++#define VCHI_MH_H_ ++ ++#include ++ ++typedef int32_t VCHI_MEM_HANDLE_T; ++#define VCHI_MEM_HANDLE_INVALID 0 ++ ++#endif +diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c +--- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c 2015-11-29 09:42:38.059222273 +0100 +@@ -0,0 +1,580 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define TOTAL_SLOTS (VCHIQ_SLOT_ZERO_SLOTS + 2 * 32) ++ ++#define VCHIQ_ARM_ADDRESS(x) ((void *)((char *)x + g_virt_to_bus_offset)) ++ ++#include "vchiq_arm.h" ++#include "vchiq_2835.h" ++#include "vchiq_connected.h" ++#include "vchiq_killable.h" ++ ++#define MAX_FRAGMENTS (VCHIQ_NUM_CURRENT_BULKS * 2) ++ ++#define BELL0 0x00 ++#define BELL2 0x08 ++ ++typedef struct vchiq_2835_state_struct { ++ int inited; ++ VCHIQ_ARM_STATE_T arm_state; ++} VCHIQ_2835_ARM_STATE_T; ++ ++static void __iomem *g_regs; ++static unsigned int g_cache_line_size = sizeof(CACHE_LINE_SIZE); ++static unsigned int g_fragments_size; ++static char *g_fragments_base; ++static char *g_free_fragments; ++static struct semaphore g_free_fragments_sema; ++static unsigned long g_virt_to_bus_offset; ++ ++extern int vchiq_arm_log_level; ++ ++static DEFINE_SEMAPHORE(g_free_fragments_mutex); ++ ++static irqreturn_t ++vchiq_doorbell_irq(int irq, void *dev_id); ++ ++static int ++create_pagelist(char __user *buf, size_t count, unsigned short type, ++ struct task_struct *task, PAGELIST_T ** ppagelist); ++ ++static void ++free_pagelist(PAGELIST_T *pagelist, int actual); ++ ++int vchiq_platform_init(struct platform_device *pdev, VCHIQ_STATE_T *state) ++{ ++ struct device *dev = &pdev->dev; ++ struct rpi_firmware *fw = platform_get_drvdata(pdev); ++ VCHIQ_SLOT_ZERO_T *vchiq_slot_zero; ++ struct resource *res; ++ void *slot_mem; ++ dma_addr_t slot_phys; ++ u32 channelbase; ++ int slot_mem_size, frag_mem_size; ++ int err, irq, i; ++ ++ g_virt_to_bus_offset = virt_to_dma(dev, (void *)0); ++ ++ (void)of_property_read_u32(dev->of_node, "cache-line-size", ++ &g_cache_line_size); ++ g_fragments_size = 2 * g_cache_line_size; ++ ++ /* Allocate space for the channels in coherent memory */ ++ slot_mem_size = PAGE_ALIGN(TOTAL_SLOTS * VCHIQ_SLOT_SIZE); ++ frag_mem_size = PAGE_ALIGN(g_fragments_size * MAX_FRAGMENTS); ++ ++ slot_mem = dmam_alloc_coherent(dev, slot_mem_size + frag_mem_size, ++ &slot_phys, GFP_KERNEL); ++ if (!slot_mem) { ++ dev_err(dev, "could not allocate DMA memory\n"); ++ return -ENOMEM; ++ } ++ ++ WARN_ON(((int)slot_mem & (PAGE_SIZE - 1)) != 0); ++ ++ vchiq_slot_zero = vchiq_init_slots(slot_mem, slot_mem_size); ++ if (!vchiq_slot_zero) ++ return -EINVAL; ++ ++ vchiq_slot_zero->platform_data[VCHIQ_PLATFORM_FRAGMENTS_OFFSET_IDX] = ++ (int)slot_phys + slot_mem_size; ++ vchiq_slot_zero->platform_data[VCHIQ_PLATFORM_FRAGMENTS_COUNT_IDX] = ++ MAX_FRAGMENTS; ++ ++ g_fragments_base = (char *)slot_mem + slot_mem_size; ++ slot_mem_size += frag_mem_size; ++ ++ g_free_fragments = g_fragments_base; ++ for (i = 0; i < (MAX_FRAGMENTS - 1); i++) { ++ *(char **)&g_fragments_base[i*g_fragments_size] = ++ &g_fragments_base[(i + 1)*g_fragments_size]; ++ } ++ *(char **)&g_fragments_base[i * g_fragments_size] = NULL; ++ sema_init(&g_free_fragments_sema, MAX_FRAGMENTS); ++ ++ if (vchiq_init_state(state, vchiq_slot_zero, 0) != VCHIQ_SUCCESS) ++ return -EINVAL; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ g_regs = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(g_regs)) ++ return PTR_ERR(g_regs); ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq <= 0) { ++ dev_err(dev, "failed to get IRQ\n"); ++ return irq; ++ } ++ ++ err = devm_request_irq(dev, irq, vchiq_doorbell_irq, IRQF_IRQPOLL, ++ "VCHIQ doorbell", state); ++ if (err) { ++ dev_err(dev, "failed to register irq=%d\n", irq); ++ return err; ++ } ++ ++ /* Send the base address of the slots to VideoCore */ ++ channelbase = slot_phys; ++ err = rpi_firmware_property(fw, RPI_FIRMWARE_VCHIQ_INIT, ++ &channelbase, sizeof(channelbase)); ++ if (err || channelbase) { ++ dev_err(dev, "failed to set channelbase\n"); ++ return err ? : -ENXIO; ++ } ++ ++ vchiq_log_info(vchiq_arm_log_level, ++ "vchiq_init - done (slots %x, phys %pad)", ++ (unsigned int)vchiq_slot_zero, &slot_phys); ++ ++ vchiq_call_connected_callbacks(); ++ ++ return 0; ++} ++ ++VCHIQ_STATUS_T ++vchiq_platform_init_state(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ state->platform_state = kzalloc(sizeof(VCHIQ_2835_ARM_STATE_T), GFP_KERNEL); ++ ((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->inited = 1; ++ status = vchiq_arm_init_state(state, &((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->arm_state); ++ if(status != VCHIQ_SUCCESS) ++ { ++ ((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->inited = 0; ++ } ++ return status; ++} ++ ++VCHIQ_ARM_STATE_T* ++vchiq_platform_get_arm_state(VCHIQ_STATE_T *state) ++{ ++ if(!((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->inited) ++ { ++ BUG(); ++ } ++ return &((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->arm_state; ++} ++ ++void ++remote_event_signal(REMOTE_EVENT_T *event) ++{ ++ wmb(); ++ ++ event->fired = 1; ++ ++ dsb(); /* data barrier operation */ ++ ++ if (event->armed) ++ writel(0, g_regs + BELL2); /* trigger vc interrupt */ ++} ++ ++int ++vchiq_copy_from_user(void *dst, const void *src, int size) ++{ ++ if ((uint32_t)src < TASK_SIZE) { ++ return copy_from_user(dst, src, size); ++ } else { ++ memcpy(dst, src, size); ++ return 0; ++ } ++} ++ ++VCHIQ_STATUS_T ++vchiq_prepare_bulk_data(VCHIQ_BULK_T *bulk, VCHI_MEM_HANDLE_T memhandle, ++ void *offset, int size, int dir) ++{ ++ PAGELIST_T *pagelist; ++ int ret; ++ ++ WARN_ON(memhandle != VCHI_MEM_HANDLE_INVALID); ++ ++ ret = create_pagelist((char __user *)offset, size, ++ (dir == VCHIQ_BULK_RECEIVE) ++ ? PAGELIST_READ ++ : PAGELIST_WRITE, ++ current, ++ &pagelist); ++ if (ret != 0) ++ return VCHIQ_ERROR; ++ ++ bulk->handle = memhandle; ++ bulk->data = VCHIQ_ARM_ADDRESS(pagelist); ++ ++ /* Store the pagelist address in remote_data, which isn't used by the ++ slave. */ ++ bulk->remote_data = pagelist; ++ ++ return VCHIQ_SUCCESS; ++} ++ ++void ++vchiq_complete_bulk(VCHIQ_BULK_T *bulk) ++{ ++ if (bulk && bulk->remote_data && bulk->actual) ++ free_pagelist((PAGELIST_T *)bulk->remote_data, bulk->actual); ++} ++ ++void ++vchiq_transfer_bulk(VCHIQ_BULK_T *bulk) ++{ ++ /* ++ * This should only be called on the master (VideoCore) side, but ++ * provide an implementation to avoid the need for ifdefery. ++ */ ++ BUG(); ++} ++ ++void ++vchiq_dump_platform_state(void *dump_context) ++{ ++ char buf[80]; ++ int len; ++ len = snprintf(buf, sizeof(buf), ++ " Platform: 2835 (VC master)"); ++ vchiq_dump(dump_context, buf, len + 1); ++} ++ ++VCHIQ_STATUS_T ++vchiq_platform_suspend(VCHIQ_STATE_T *state) ++{ ++ return VCHIQ_ERROR; ++} ++ ++VCHIQ_STATUS_T ++vchiq_platform_resume(VCHIQ_STATE_T *state) ++{ ++ return VCHIQ_SUCCESS; ++} ++ ++void ++vchiq_platform_paused(VCHIQ_STATE_T *state) ++{ ++} ++ ++void ++vchiq_platform_resumed(VCHIQ_STATE_T *state) ++{ ++} ++ ++int ++vchiq_platform_videocore_wanted(VCHIQ_STATE_T* state) ++{ ++ return 1; // autosuspend not supported - videocore always wanted ++} ++ ++int ++vchiq_platform_use_suspend_timer(void) ++{ ++ return 0; ++} ++void ++vchiq_dump_platform_use_state(VCHIQ_STATE_T *state) ++{ ++ vchiq_log_info(vchiq_arm_log_level, "Suspend timer not in use"); ++} ++void ++vchiq_platform_handle_timeout(VCHIQ_STATE_T *state) ++{ ++ (void)state; ++} ++/* ++ * Local functions ++ */ ++ ++static irqreturn_t ++vchiq_doorbell_irq(int irq, void *dev_id) ++{ ++ VCHIQ_STATE_T *state = dev_id; ++ irqreturn_t ret = IRQ_NONE; ++ unsigned int status; ++ ++ /* Read (and clear) the doorbell */ ++ status = readl(g_regs + BELL0); ++ ++ if (status & 0x4) { /* Was the doorbell rung? */ ++ remote_event_pollall(state); ++ ret = IRQ_HANDLED; ++ } ++ ++ return ret; ++} ++ ++/* There is a potential problem with partial cache lines (pages?) ++** at the ends of the block when reading. If the CPU accessed anything in ++** the same line (page?) then it may have pulled old data into the cache, ++** obscuring the new data underneath. We can solve this by transferring the ++** partial cache lines separately, and allowing the ARM to copy into the ++** cached area. ++ ++** N.B. This implementation plays slightly fast and loose with the Linux ++** driver programming rules, e.g. its use of dmac_map_area instead of ++** dma_map_single, but it isn't a multi-platform driver and it benefits ++** from increased speed as a result. ++*/ ++ ++static int ++create_pagelist(char __user *buf, size_t count, unsigned short type, ++ struct task_struct *task, PAGELIST_T ** ppagelist) ++{ ++ PAGELIST_T *pagelist; ++ struct page **pages; ++ unsigned long *addrs; ++ unsigned int num_pages, offset, i; ++ char *addr, *base_addr, *next_addr; ++ int run, addridx, actual_pages; ++ unsigned long *need_release; ++ ++ offset = (unsigned int)buf & (PAGE_SIZE - 1); ++ num_pages = (count + offset + PAGE_SIZE - 1) / PAGE_SIZE; ++ ++ *ppagelist = NULL; ++ ++ /* Allocate enough storage to hold the page pointers and the page ++ ** list ++ */ ++ pagelist = kmalloc(sizeof(PAGELIST_T) + ++ (num_pages * sizeof(unsigned long)) + ++ sizeof(unsigned long) + ++ (num_pages * sizeof(pages[0])), ++ GFP_KERNEL); ++ ++ vchiq_log_trace(vchiq_arm_log_level, ++ "create_pagelist - %x", (unsigned int)pagelist); ++ if (!pagelist) ++ return -ENOMEM; ++ ++ addrs = pagelist->addrs; ++ need_release = (unsigned long *)(addrs + num_pages); ++ pages = (struct page **)(addrs + num_pages + 1); ++ ++ if (is_vmalloc_addr(buf)) { ++ int dir = (type == PAGELIST_WRITE) ? ++ DMA_TO_DEVICE : DMA_FROM_DEVICE; ++ unsigned long length = count; ++ unsigned int off = offset; ++ ++ for (actual_pages = 0; actual_pages < num_pages; ++ actual_pages++) { ++ struct page *pg = vmalloc_to_page(buf + (actual_pages * ++ PAGE_SIZE)); ++ size_t bytes = PAGE_SIZE - off; ++ ++ if (bytes > length) ++ bytes = length; ++ pages[actual_pages] = pg; ++ dmac_map_area(page_address(pg) + off, bytes, dir); ++ length -= bytes; ++ off = 0; ++ } ++ *need_release = 0; /* do not try and release vmalloc pages */ ++ } else { ++ down_read(&task->mm->mmap_sem); ++ actual_pages = get_user_pages(task, task->mm, ++ (unsigned long)buf & ~(PAGE_SIZE - 1), ++ num_pages, ++ (type == PAGELIST_READ) /*Write */ , ++ 0 /*Force */ , ++ pages, ++ NULL /*vmas */); ++ up_read(&task->mm->mmap_sem); ++ ++ if (actual_pages != num_pages) { ++ vchiq_log_info(vchiq_arm_log_level, ++ "create_pagelist - only %d/%d pages locked", ++ actual_pages, ++ num_pages); ++ ++ /* This is probably due to the process being killed */ ++ while (actual_pages > 0) ++ { ++ actual_pages--; ++ page_cache_release(pages[actual_pages]); ++ } ++ kfree(pagelist); ++ if (actual_pages == 0) ++ actual_pages = -ENOMEM; ++ return actual_pages; ++ } ++ *need_release = 1; /* release user pages */ ++ } ++ ++ pagelist->length = count; ++ pagelist->type = type; ++ pagelist->offset = offset; ++ ++ /* Group the pages into runs of contiguous pages */ ++ ++ base_addr = VCHIQ_ARM_ADDRESS(page_address(pages[0])); ++ next_addr = base_addr + PAGE_SIZE; ++ addridx = 0; ++ run = 0; ++ ++ for (i = 1; i < num_pages; i++) { ++ addr = VCHIQ_ARM_ADDRESS(page_address(pages[i])); ++ if ((addr == next_addr) && (run < (PAGE_SIZE - 1))) { ++ next_addr += PAGE_SIZE; ++ run++; ++ } else { ++ addrs[addridx] = (unsigned long)base_addr + run; ++ addridx++; ++ base_addr = addr; ++ next_addr = addr + PAGE_SIZE; ++ run = 0; ++ } ++ } ++ ++ addrs[addridx] = (unsigned long)base_addr + run; ++ addridx++; ++ ++ /* Partial cache lines (fragments) require special measures */ ++ if ((type == PAGELIST_READ) && ++ ((pagelist->offset & (g_cache_line_size - 1)) || ++ ((pagelist->offset + pagelist->length) & ++ (g_cache_line_size - 1)))) { ++ char *fragments; ++ ++ if (down_interruptible(&g_free_fragments_sema) != 0) { ++ kfree(pagelist); ++ return -EINTR; ++ } ++ ++ WARN_ON(g_free_fragments == NULL); ++ ++ down(&g_free_fragments_mutex); ++ fragments = g_free_fragments; ++ WARN_ON(fragments == NULL); ++ g_free_fragments = *(char **) g_free_fragments; ++ up(&g_free_fragments_mutex); ++ pagelist->type = PAGELIST_READ_WITH_FRAGMENTS + ++ (fragments - g_fragments_base) / g_fragments_size; ++ } ++ ++ dmac_flush_range(pagelist, addrs + num_pages); ++ ++ *ppagelist = pagelist; ++ ++ return 0; ++} ++ ++static void ++free_pagelist(PAGELIST_T *pagelist, int actual) ++{ ++ unsigned long *need_release; ++ struct page **pages; ++ unsigned int num_pages, i; ++ ++ vchiq_log_trace(vchiq_arm_log_level, ++ "free_pagelist - %x, %d", (unsigned int)pagelist, actual); ++ ++ num_pages = ++ (pagelist->length + pagelist->offset + PAGE_SIZE - 1) / ++ PAGE_SIZE; ++ ++ need_release = (unsigned long *)(pagelist->addrs + num_pages); ++ pages = (struct page **)(pagelist->addrs + num_pages + 1); ++ ++ /* Deal with any partial cache lines (fragments) */ ++ if (pagelist->type >= PAGELIST_READ_WITH_FRAGMENTS) { ++ char *fragments = g_fragments_base + ++ (pagelist->type - PAGELIST_READ_WITH_FRAGMENTS) * ++ g_fragments_size; ++ int head_bytes, tail_bytes; ++ head_bytes = (g_cache_line_size - pagelist->offset) & ++ (g_cache_line_size - 1); ++ tail_bytes = (pagelist->offset + actual) & ++ (g_cache_line_size - 1); ++ ++ if ((actual >= 0) && (head_bytes != 0)) { ++ if (head_bytes > actual) ++ head_bytes = actual; ++ ++ memcpy((char *)page_address(pages[0]) + ++ pagelist->offset, ++ fragments, ++ head_bytes); ++ } ++ if ((actual >= 0) && (head_bytes < actual) && ++ (tail_bytes != 0)) { ++ memcpy((char *)page_address(pages[num_pages - 1]) + ++ ((pagelist->offset + actual) & ++ (PAGE_SIZE - 1) & ~(g_cache_line_size - 1)), ++ fragments + g_cache_line_size, ++ tail_bytes); ++ } ++ ++ down(&g_free_fragments_mutex); ++ *(char **)fragments = g_free_fragments; ++ g_free_fragments = fragments; ++ up(&g_free_fragments_mutex); ++ up(&g_free_fragments_sema); ++ } ++ ++ if (*need_release) { ++ unsigned int length = pagelist->length; ++ unsigned int offset = pagelist->offset; ++ ++ for (i = 0; i < num_pages; i++) { ++ struct page *pg = pages[i]; ++ ++ if (pagelist->type != PAGELIST_WRITE) { ++ unsigned int bytes = PAGE_SIZE - offset; ++ ++ if (bytes > length) ++ bytes = length; ++ dmac_unmap_area(page_address(pg) + offset, ++ bytes, DMA_FROM_DEVICE); ++ length -= bytes; ++ offset = 0; ++ set_page_dirty(pg); ++ } ++ page_cache_release(pg); ++ } ++ } ++ ++ kfree(pagelist); ++} +diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835.h +--- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835.h 2015-11-29 09:42:38.059222273 +0100 +@@ -0,0 +1,42 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHIQ_2835_H ++#define VCHIQ_2835_H ++ ++#include "vchiq_pagelist.h" ++ ++#define VCHIQ_PLATFORM_FRAGMENTS_OFFSET_IDX 0 ++#define VCHIQ_PLATFORM_FRAGMENTS_COUNT_IDX 1 ++ ++#endif /* VCHIQ_2835_H */ +diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c +--- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c 2015-11-29 09:42:38.071221476 +0100 +@@ -0,0 +1,2903 @@ ++/** ++ * Copyright (c) 2014 Raspberry Pi (Trading) Ltd. All rights reserved. ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "vchiq_core.h" ++#include "vchiq_ioctl.h" ++#include "vchiq_arm.h" ++#include "vchiq_debugfs.h" ++#include "vchiq_killable.h" ++ ++#define DEVICE_NAME "vchiq" ++ ++/* Override the default prefix, which would be vchiq_arm (from the filename) */ ++#undef MODULE_PARAM_PREFIX ++#define MODULE_PARAM_PREFIX DEVICE_NAME "." ++ ++#define VCHIQ_MINOR 0 ++ ++/* Some per-instance constants */ ++#define MAX_COMPLETIONS 16 ++#define MAX_SERVICES 64 ++#define MAX_ELEMENTS 8 ++#define MSG_QUEUE_SIZE 64 ++ ++#define KEEPALIVE_VER 1 ++#define KEEPALIVE_VER_MIN KEEPALIVE_VER ++ ++/* Run time control of log level, based on KERN_XXX level. */ ++int vchiq_arm_log_level = VCHIQ_LOG_DEFAULT; ++int vchiq_susp_log_level = VCHIQ_LOG_ERROR; ++ ++#define SUSPEND_TIMER_TIMEOUT_MS 100 ++#define SUSPEND_RETRY_TIMER_TIMEOUT_MS 1000 ++ ++#define VC_SUSPEND_NUM_OFFSET 3 /* number of values before idle which are -ve */ ++static const char *const suspend_state_names[] = { ++ "VC_SUSPEND_FORCE_CANCELED", ++ "VC_SUSPEND_REJECTED", ++ "VC_SUSPEND_FAILED", ++ "VC_SUSPEND_IDLE", ++ "VC_SUSPEND_REQUESTED", ++ "VC_SUSPEND_IN_PROGRESS", ++ "VC_SUSPEND_SUSPENDED" ++}; ++#define VC_RESUME_NUM_OFFSET 1 /* number of values before idle which are -ve */ ++static const char *const resume_state_names[] = { ++ "VC_RESUME_FAILED", ++ "VC_RESUME_IDLE", ++ "VC_RESUME_REQUESTED", ++ "VC_RESUME_IN_PROGRESS", ++ "VC_RESUME_RESUMED" ++}; ++/* The number of times we allow force suspend to timeout before actually ++** _forcing_ suspend. This is to cater for SW which fails to release vchiq ++** correctly - we don't want to prevent ARM suspend indefinitely in this case. ++*/ ++#define FORCE_SUSPEND_FAIL_MAX 8 ++ ++/* The time in ms allowed for videocore to go idle when force suspend has been ++ * requested */ ++#define FORCE_SUSPEND_TIMEOUT_MS 200 ++ ++ ++static void suspend_timer_callback(unsigned long context); ++ ++ ++typedef struct user_service_struct { ++ VCHIQ_SERVICE_T *service; ++ void *userdata; ++ VCHIQ_INSTANCE_T instance; ++ char is_vchi; ++ char dequeue_pending; ++ char close_pending; ++ int message_available_pos; ++ int msg_insert; ++ int msg_remove; ++ struct semaphore insert_event; ++ struct semaphore remove_event; ++ struct semaphore close_event; ++ VCHIQ_HEADER_T * msg_queue[MSG_QUEUE_SIZE]; ++} USER_SERVICE_T; ++ ++struct bulk_waiter_node { ++ struct bulk_waiter bulk_waiter; ++ int pid; ++ struct list_head list; ++}; ++ ++struct vchiq_instance_struct { ++ VCHIQ_STATE_T *state; ++ VCHIQ_COMPLETION_DATA_T completions[MAX_COMPLETIONS]; ++ int completion_insert; ++ int completion_remove; ++ struct semaphore insert_event; ++ struct semaphore remove_event; ++ struct mutex completion_mutex; ++ ++ int connected; ++ int closing; ++ int pid; ++ int mark; ++ int use_close_delivered; ++ int trace; ++ ++ struct list_head bulk_waiter_list; ++ struct mutex bulk_waiter_list_mutex; ++ ++ VCHIQ_DEBUGFS_NODE_T debugfs_node; ++}; ++ ++typedef struct dump_context_struct { ++ char __user *buf; ++ size_t actual; ++ size_t space; ++ loff_t offset; ++} DUMP_CONTEXT_T; ++ ++static struct cdev vchiq_cdev; ++static dev_t vchiq_devid; ++static VCHIQ_STATE_T g_state; ++static struct class *vchiq_class; ++static struct device *vchiq_dev; ++static DEFINE_SPINLOCK(msg_queue_spinlock); ++ ++static const char *const ioctl_names[] = { ++ "CONNECT", ++ "SHUTDOWN", ++ "CREATE_SERVICE", ++ "REMOVE_SERVICE", ++ "QUEUE_MESSAGE", ++ "QUEUE_BULK_TRANSMIT", ++ "QUEUE_BULK_RECEIVE", ++ "AWAIT_COMPLETION", ++ "DEQUEUE_MESSAGE", ++ "GET_CLIENT_ID", ++ "GET_CONFIG", ++ "CLOSE_SERVICE", ++ "USE_SERVICE", ++ "RELEASE_SERVICE", ++ "SET_SERVICE_OPTION", ++ "DUMP_PHYS_MEM", ++ "LIB_VERSION", ++ "CLOSE_DELIVERED" ++}; ++ ++vchiq_static_assert((sizeof(ioctl_names)/sizeof(ioctl_names[0])) == ++ (VCHIQ_IOC_MAX + 1)); ++ ++static void ++dump_phys_mem(void *virt_addr, uint32_t num_bytes); ++ ++/**************************************************************************** ++* ++* add_completion ++* ++***************************************************************************/ ++ ++static VCHIQ_STATUS_T ++add_completion(VCHIQ_INSTANCE_T instance, VCHIQ_REASON_T reason, ++ VCHIQ_HEADER_T *header, USER_SERVICE_T *user_service, ++ void *bulk_userdata) ++{ ++ VCHIQ_COMPLETION_DATA_T *completion; ++ DEBUG_INITIALISE(g_state.local) ++ ++ while (instance->completion_insert == ++ (instance->completion_remove + MAX_COMPLETIONS)) { ++ /* Out of space - wait for the client */ ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ vchiq_log_trace(vchiq_arm_log_level, ++ "add_completion - completion queue full"); ++ DEBUG_COUNT(COMPLETION_QUEUE_FULL_COUNT); ++ if (down_interruptible(&instance->remove_event) != 0) { ++ vchiq_log_info(vchiq_arm_log_level, ++ "service_callback interrupted"); ++ return VCHIQ_RETRY; ++ } else if (instance->closing) { ++ vchiq_log_info(vchiq_arm_log_level, ++ "service_callback closing"); ++ return VCHIQ_ERROR; ++ } ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ } ++ ++ completion = ++ &instance->completions[instance->completion_insert & ++ (MAX_COMPLETIONS - 1)]; ++ ++ completion->header = header; ++ completion->reason = reason; ++ /* N.B. service_userdata is updated while processing AWAIT_COMPLETION */ ++ completion->service_userdata = user_service->service; ++ completion->bulk_userdata = bulk_userdata; ++ ++ if (reason == VCHIQ_SERVICE_CLOSED) { ++ /* Take an extra reference, to be held until ++ this CLOSED notification is delivered. */ ++ lock_service(user_service->service); ++ if (instance->use_close_delivered) ++ user_service->close_pending = 1; ++ } ++ ++ /* A write barrier is needed here to ensure that the entire completion ++ record is written out before the insert point. */ ++ wmb(); ++ ++ if (reason == VCHIQ_MESSAGE_AVAILABLE) ++ user_service->message_available_pos = ++ instance->completion_insert; ++ instance->completion_insert++; ++ ++ up(&instance->insert_event); ++ ++ return VCHIQ_SUCCESS; ++} ++ ++/**************************************************************************** ++* ++* service_callback ++* ++***************************************************************************/ ++ ++static VCHIQ_STATUS_T ++service_callback(VCHIQ_REASON_T reason, VCHIQ_HEADER_T *header, ++ VCHIQ_SERVICE_HANDLE_T handle, void *bulk_userdata) ++{ ++ /* How do we ensure the callback goes to the right client? ++ ** The service_user data points to a USER_SERVICE_T record containing ++ ** the original callback and the user state structure, which contains a ++ ** circular buffer for completion records. ++ */ ++ USER_SERVICE_T *user_service; ++ VCHIQ_SERVICE_T *service; ++ VCHIQ_INSTANCE_T instance; ++ DEBUG_INITIALISE(g_state.local) ++ ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ ++ service = handle_to_service(handle); ++ BUG_ON(!service); ++ user_service = (USER_SERVICE_T *)service->base.userdata; ++ instance = user_service->instance; ++ ++ if (!instance || instance->closing) ++ return VCHIQ_SUCCESS; ++ ++ vchiq_log_trace(vchiq_arm_log_level, ++ "service_callback - service %lx(%d,%p), reason %d, header %lx, " ++ "instance %lx, bulk_userdata %lx", ++ (unsigned long)user_service, ++ service->localport, user_service->userdata, ++ reason, (unsigned long)header, ++ (unsigned long)instance, (unsigned long)bulk_userdata); ++ ++ if (header && user_service->is_vchi) { ++ spin_lock(&msg_queue_spinlock); ++ while (user_service->msg_insert == ++ (user_service->msg_remove + MSG_QUEUE_SIZE)) { ++ spin_unlock(&msg_queue_spinlock); ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ DEBUG_COUNT(MSG_QUEUE_FULL_COUNT); ++ vchiq_log_trace(vchiq_arm_log_level, ++ "service_callback - msg queue full"); ++ /* If there is no MESSAGE_AVAILABLE in the completion ++ ** queue, add one ++ */ ++ if ((user_service->message_available_pos - ++ instance->completion_remove) < 0) { ++ VCHIQ_STATUS_T status; ++ vchiq_log_info(vchiq_arm_log_level, ++ "Inserting extra MESSAGE_AVAILABLE"); ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ status = add_completion(instance, reason, ++ NULL, user_service, bulk_userdata); ++ if (status != VCHIQ_SUCCESS) { ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ return status; ++ } ++ } ++ ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ if (down_interruptible(&user_service->remove_event) ++ != 0) { ++ vchiq_log_info(vchiq_arm_log_level, ++ "service_callback interrupted"); ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ return VCHIQ_RETRY; ++ } else if (instance->closing) { ++ vchiq_log_info(vchiq_arm_log_level, ++ "service_callback closing"); ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ return VCHIQ_ERROR; ++ } ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ spin_lock(&msg_queue_spinlock); ++ } ++ ++ user_service->msg_queue[user_service->msg_insert & ++ (MSG_QUEUE_SIZE - 1)] = header; ++ user_service->msg_insert++; ++ spin_unlock(&msg_queue_spinlock); ++ ++ up(&user_service->insert_event); ++ ++ /* If there is a thread waiting in DEQUEUE_MESSAGE, or if ++ ** there is a MESSAGE_AVAILABLE in the completion queue then ++ ** bypass the completion queue. ++ */ ++ if (((user_service->message_available_pos - ++ instance->completion_remove) >= 0) || ++ user_service->dequeue_pending) { ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ user_service->dequeue_pending = 0; ++ return VCHIQ_SUCCESS; ++ } ++ ++ header = NULL; ++ } ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ ++ return add_completion(instance, reason, header, user_service, ++ bulk_userdata); ++} ++ ++/**************************************************************************** ++* ++* user_service_free ++* ++***************************************************************************/ ++static void ++user_service_free(void *userdata) ++{ ++ kfree(userdata); ++} ++ ++/**************************************************************************** ++* ++* close_delivered ++* ++***************************************************************************/ ++static void close_delivered(USER_SERVICE_T *user_service) ++{ ++ vchiq_log_info(vchiq_arm_log_level, ++ "close_delivered(handle=%x)", ++ user_service->service->handle); ++ ++ if (user_service->close_pending) { ++ /* Allow the underlying service to be culled */ ++ unlock_service(user_service->service); ++ ++ /* Wake the user-thread blocked in close_ or remove_service */ ++ up(&user_service->close_event); ++ ++ user_service->close_pending = 0; ++ } ++} ++ ++/**************************************************************************** ++* ++* vchiq_ioctl ++* ++***************************************************************************/ ++static long ++vchiq_ioctl(struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ VCHIQ_INSTANCE_T instance = file->private_data; ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ VCHIQ_SERVICE_T *service = NULL; ++ long ret = 0; ++ int i, rc; ++ DEBUG_INITIALISE(g_state.local) ++ ++ vchiq_log_trace(vchiq_arm_log_level, ++ "vchiq_ioctl - instance %x, cmd %s, arg %lx", ++ (unsigned int)instance, ++ ((_IOC_TYPE(cmd) == VCHIQ_IOC_MAGIC) && ++ (_IOC_NR(cmd) <= VCHIQ_IOC_MAX)) ? ++ ioctl_names[_IOC_NR(cmd)] : "", arg); ++ ++ switch (cmd) { ++ case VCHIQ_IOC_SHUTDOWN: ++ if (!instance->connected) ++ break; ++ ++ /* Remove all services */ ++ i = 0; ++ while ((service = next_service_by_instance(instance->state, ++ instance, &i)) != NULL) { ++ status = vchiq_remove_service(service->handle); ++ unlock_service(service); ++ if (status != VCHIQ_SUCCESS) ++ break; ++ } ++ service = NULL; ++ ++ if (status == VCHIQ_SUCCESS) { ++ /* Wake the completion thread and ask it to exit */ ++ instance->closing = 1; ++ up(&instance->insert_event); ++ } ++ ++ break; ++ ++ case VCHIQ_IOC_CONNECT: ++ if (instance->connected) { ++ ret = -EINVAL; ++ break; ++ } ++ rc = mutex_lock_interruptible(&instance->state->mutex); ++ if (rc != 0) { ++ vchiq_log_error(vchiq_arm_log_level, ++ "vchiq: connect: could not lock mutex for " ++ "state %d: %d", ++ instance->state->id, rc); ++ ret = -EINTR; ++ break; ++ } ++ status = vchiq_connect_internal(instance->state, instance); ++ mutex_unlock(&instance->state->mutex); ++ ++ if (status == VCHIQ_SUCCESS) ++ instance->connected = 1; ++ else ++ vchiq_log_error(vchiq_arm_log_level, ++ "vchiq: could not connect: %d", status); ++ break; ++ ++ case VCHIQ_IOC_CREATE_SERVICE: { ++ VCHIQ_CREATE_SERVICE_T args; ++ USER_SERVICE_T *user_service = NULL; ++ void *userdata; ++ int srvstate; ++ ++ if (copy_from_user ++ (&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ ++ user_service = kmalloc(sizeof(USER_SERVICE_T), GFP_KERNEL); ++ if (!user_service) { ++ ret = -ENOMEM; ++ break; ++ } ++ ++ if (args.is_open) { ++ if (!instance->connected) { ++ ret = -ENOTCONN; ++ kfree(user_service); ++ break; ++ } ++ srvstate = VCHIQ_SRVSTATE_OPENING; ++ } else { ++ srvstate = ++ instance->connected ? ++ VCHIQ_SRVSTATE_LISTENING : ++ VCHIQ_SRVSTATE_HIDDEN; ++ } ++ ++ userdata = args.params.userdata; ++ args.params.callback = service_callback; ++ args.params.userdata = user_service; ++ service = vchiq_add_service_internal( ++ instance->state, ++ &args.params, srvstate, ++ instance, user_service_free); ++ ++ if (service != NULL) { ++ user_service->service = service; ++ user_service->userdata = userdata; ++ user_service->instance = instance; ++ user_service->is_vchi = (args.is_vchi != 0); ++ user_service->dequeue_pending = 0; ++ user_service->close_pending = 0; ++ user_service->message_available_pos = ++ instance->completion_remove - 1; ++ user_service->msg_insert = 0; ++ user_service->msg_remove = 0; ++ sema_init(&user_service->insert_event, 0); ++ sema_init(&user_service->remove_event, 0); ++ sema_init(&user_service->close_event, 0); ++ ++ if (args.is_open) { ++ status = vchiq_open_service_internal ++ (service, instance->pid); ++ if (status != VCHIQ_SUCCESS) { ++ vchiq_remove_service(service->handle); ++ service = NULL; ++ ret = (status == VCHIQ_RETRY) ? ++ -EINTR : -EIO; ++ break; ++ } ++ } ++ ++ if (copy_to_user((void __user *) ++ &(((VCHIQ_CREATE_SERVICE_T __user *) ++ arg)->handle), ++ (const void *)&service->handle, ++ sizeof(service->handle)) != 0) { ++ ret = -EFAULT; ++ vchiq_remove_service(service->handle); ++ } ++ ++ service = NULL; ++ } else { ++ ret = -EEXIST; ++ kfree(user_service); ++ } ++ } break; ++ ++ case VCHIQ_IOC_CLOSE_SERVICE: { ++ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg; ++ ++ service = find_service_for_instance(instance, handle); ++ if (service != NULL) { ++ USER_SERVICE_T *user_service = ++ (USER_SERVICE_T *)service->base.userdata; ++ /* close_pending is false on first entry, and when the ++ wait in vchiq_close_service has been interrupted. */ ++ if (!user_service->close_pending) { ++ status = vchiq_close_service(service->handle); ++ if (status != VCHIQ_SUCCESS) ++ break; ++ } ++ ++ /* close_pending is true once the underlying service ++ has been closed until the client library calls the ++ CLOSE_DELIVERED ioctl, signalling close_event. */ ++ if (user_service->close_pending && ++ down_interruptible(&user_service->close_event)) ++ status = VCHIQ_RETRY; ++ } ++ else ++ ret = -EINVAL; ++ } break; ++ ++ case VCHIQ_IOC_REMOVE_SERVICE: { ++ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg; ++ ++ service = find_service_for_instance(instance, handle); ++ if (service != NULL) { ++ USER_SERVICE_T *user_service = ++ (USER_SERVICE_T *)service->base.userdata; ++ /* close_pending is false on first entry, and when the ++ wait in vchiq_close_service has been interrupted. */ ++ if (!user_service->close_pending) { ++ status = vchiq_remove_service(service->handle); ++ if (status != VCHIQ_SUCCESS) ++ break; ++ } ++ ++ /* close_pending is true once the underlying service ++ has been closed until the client library calls the ++ CLOSE_DELIVERED ioctl, signalling close_event. */ ++ if (user_service->close_pending && ++ down_interruptible(&user_service->close_event)) ++ status = VCHIQ_RETRY; ++ } ++ else ++ ret = -EINVAL; ++ } break; ++ ++ case VCHIQ_IOC_USE_SERVICE: ++ case VCHIQ_IOC_RELEASE_SERVICE: { ++ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg; ++ ++ service = find_service_for_instance(instance, handle); ++ if (service != NULL) { ++ status = (cmd == VCHIQ_IOC_USE_SERVICE) ? ++ vchiq_use_service_internal(service) : ++ vchiq_release_service_internal(service); ++ if (status != VCHIQ_SUCCESS) { ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s: cmd %s returned error %d for " ++ "service %c%c%c%c:%03d", ++ __func__, ++ (cmd == VCHIQ_IOC_USE_SERVICE) ? ++ "VCHIQ_IOC_USE_SERVICE" : ++ "VCHIQ_IOC_RELEASE_SERVICE", ++ status, ++ VCHIQ_FOURCC_AS_4CHARS( ++ service->base.fourcc), ++ service->client_id); ++ ret = -EINVAL; ++ } ++ } else ++ ret = -EINVAL; ++ } break; ++ ++ case VCHIQ_IOC_QUEUE_MESSAGE: { ++ VCHIQ_QUEUE_MESSAGE_T args; ++ if (copy_from_user ++ (&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ ++ service = find_service_for_instance(instance, args.handle); ++ ++ if ((service != NULL) && (args.count <= MAX_ELEMENTS)) { ++ /* Copy elements into kernel space */ ++ VCHIQ_ELEMENT_T elements[MAX_ELEMENTS]; ++ if (copy_from_user(elements, args.elements, ++ args.count * sizeof(VCHIQ_ELEMENT_T)) == 0) ++ status = vchiq_queue_message ++ (args.handle, ++ elements, args.count); ++ else ++ ret = -EFAULT; ++ } else { ++ ret = -EINVAL; ++ } ++ } break; ++ ++ case VCHIQ_IOC_QUEUE_BULK_TRANSMIT: ++ case VCHIQ_IOC_QUEUE_BULK_RECEIVE: { ++ VCHIQ_QUEUE_BULK_TRANSFER_T args; ++ struct bulk_waiter_node *waiter = NULL; ++ VCHIQ_BULK_DIR_T dir = ++ (cmd == VCHIQ_IOC_QUEUE_BULK_TRANSMIT) ? ++ VCHIQ_BULK_TRANSMIT : VCHIQ_BULK_RECEIVE; ++ ++ if (copy_from_user ++ (&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ ++ service = find_service_for_instance(instance, args.handle); ++ if (!service) { ++ ret = -EINVAL; ++ break; ++ } ++ ++ if (args.mode == VCHIQ_BULK_MODE_BLOCKING) { ++ waiter = kzalloc(sizeof(struct bulk_waiter_node), ++ GFP_KERNEL); ++ if (!waiter) { ++ ret = -ENOMEM; ++ break; ++ } ++ args.userdata = &waiter->bulk_waiter; ++ } else if (args.mode == VCHIQ_BULK_MODE_WAITING) { ++ struct list_head *pos; ++ mutex_lock(&instance->bulk_waiter_list_mutex); ++ list_for_each(pos, &instance->bulk_waiter_list) { ++ if (list_entry(pos, struct bulk_waiter_node, ++ list)->pid == current->pid) { ++ waiter = list_entry(pos, ++ struct bulk_waiter_node, ++ list); ++ list_del(pos); ++ break; ++ } ++ ++ } ++ mutex_unlock(&instance->bulk_waiter_list_mutex); ++ if (!waiter) { ++ vchiq_log_error(vchiq_arm_log_level, ++ "no bulk_waiter found for pid %d", ++ current->pid); ++ ret = -ESRCH; ++ break; ++ } ++ vchiq_log_info(vchiq_arm_log_level, ++ "found bulk_waiter %x for pid %d", ++ (unsigned int)waiter, current->pid); ++ args.userdata = &waiter->bulk_waiter; ++ } ++ status = vchiq_bulk_transfer ++ (args.handle, ++ VCHI_MEM_HANDLE_INVALID, ++ args.data, args.size, ++ args.userdata, args.mode, ++ dir); ++ if (!waiter) ++ break; ++ if ((status != VCHIQ_RETRY) || fatal_signal_pending(current) || ++ !waiter->bulk_waiter.bulk) { ++ if (waiter->bulk_waiter.bulk) { ++ /* Cancel the signal when the transfer ++ ** completes. */ ++ spin_lock(&bulk_waiter_spinlock); ++ waiter->bulk_waiter.bulk->userdata = NULL; ++ spin_unlock(&bulk_waiter_spinlock); ++ } ++ kfree(waiter); ++ } else { ++ const VCHIQ_BULK_MODE_T mode_waiting = ++ VCHIQ_BULK_MODE_WAITING; ++ waiter->pid = current->pid; ++ mutex_lock(&instance->bulk_waiter_list_mutex); ++ list_add(&waiter->list, &instance->bulk_waiter_list); ++ mutex_unlock(&instance->bulk_waiter_list_mutex); ++ vchiq_log_info(vchiq_arm_log_level, ++ "saved bulk_waiter %x for pid %d", ++ (unsigned int)waiter, current->pid); ++ ++ if (copy_to_user((void __user *) ++ &(((VCHIQ_QUEUE_BULK_TRANSFER_T __user *) ++ arg)->mode), ++ (const void *)&mode_waiting, ++ sizeof(mode_waiting)) != 0) ++ ret = -EFAULT; ++ } ++ } break; ++ ++ case VCHIQ_IOC_AWAIT_COMPLETION: { ++ VCHIQ_AWAIT_COMPLETION_T args; ++ ++ DEBUG_TRACE(AWAIT_COMPLETION_LINE); ++ if (!instance->connected) { ++ ret = -ENOTCONN; ++ break; ++ } ++ ++ if (copy_from_user(&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ ++ mutex_lock(&instance->completion_mutex); ++ ++ DEBUG_TRACE(AWAIT_COMPLETION_LINE); ++ while ((instance->completion_remove == ++ instance->completion_insert) ++ && !instance->closing) { ++ int rc; ++ DEBUG_TRACE(AWAIT_COMPLETION_LINE); ++ mutex_unlock(&instance->completion_mutex); ++ rc = down_interruptible(&instance->insert_event); ++ mutex_lock(&instance->completion_mutex); ++ if (rc != 0) { ++ DEBUG_TRACE(AWAIT_COMPLETION_LINE); ++ vchiq_log_info(vchiq_arm_log_level, ++ "AWAIT_COMPLETION interrupted"); ++ ret = -EINTR; ++ break; ++ } ++ } ++ DEBUG_TRACE(AWAIT_COMPLETION_LINE); ++ ++ /* A read memory barrier is needed to stop prefetch of a stale ++ ** completion record ++ */ ++ rmb(); ++ ++ if (ret == 0) { ++ int msgbufcount = args.msgbufcount; ++ for (ret = 0; ret < args.count; ret++) { ++ VCHIQ_COMPLETION_DATA_T *completion; ++ VCHIQ_SERVICE_T *service; ++ USER_SERVICE_T *user_service; ++ VCHIQ_HEADER_T *header; ++ if (instance->completion_remove == ++ instance->completion_insert) ++ break; ++ completion = &instance->completions[ ++ instance->completion_remove & ++ (MAX_COMPLETIONS - 1)]; ++ ++ service = completion->service_userdata; ++ user_service = service->base.userdata; ++ completion->service_userdata = ++ user_service->userdata; ++ ++ header = completion->header; ++ if (header) { ++ void __user *msgbuf; ++ int msglen; ++ ++ msglen = header->size + ++ sizeof(VCHIQ_HEADER_T); ++ /* This must be a VCHIQ-style service */ ++ if (args.msgbufsize < msglen) { ++ vchiq_log_error( ++ vchiq_arm_log_level, ++ "header %x: msgbufsize" ++ " %x < msglen %x", ++ (unsigned int)header, ++ args.msgbufsize, ++ msglen); ++ WARN(1, "invalid message " ++ "size\n"); ++ if (ret == 0) ++ ret = -EMSGSIZE; ++ break; ++ } ++ if (msgbufcount <= 0) ++ /* Stall here for lack of a ++ ** buffer for the message. */ ++ break; ++ /* Get the pointer from user space */ ++ msgbufcount--; ++ if (copy_from_user(&msgbuf, ++ (const void __user *) ++ &args.msgbufs[msgbufcount], ++ sizeof(msgbuf)) != 0) { ++ if (ret == 0) ++ ret = -EFAULT; ++ break; ++ } ++ ++ /* Copy the message to user space */ ++ if (copy_to_user(msgbuf, header, ++ msglen) != 0) { ++ if (ret == 0) ++ ret = -EFAULT; ++ break; ++ } ++ ++ /* Now it has been copied, the message ++ ** can be released. */ ++ vchiq_release_message(service->handle, ++ header); ++ ++ /* The completion must point to the ++ ** msgbuf. */ ++ completion->header = msgbuf; ++ } ++ ++ if ((completion->reason == ++ VCHIQ_SERVICE_CLOSED) && ++ !instance->use_close_delivered) ++ unlock_service(service); ++ ++ if (copy_to_user((void __user *)( ++ (size_t)args.buf + ++ ret * sizeof(VCHIQ_COMPLETION_DATA_T)), ++ completion, ++ sizeof(VCHIQ_COMPLETION_DATA_T)) != 0) { ++ if (ret == 0) ++ ret = -EFAULT; ++ break; ++ } ++ ++ instance->completion_remove++; ++ } ++ ++ if (msgbufcount != args.msgbufcount) { ++ if (copy_to_user((void __user *) ++ &((VCHIQ_AWAIT_COMPLETION_T *)arg)-> ++ msgbufcount, ++ &msgbufcount, ++ sizeof(msgbufcount)) != 0) { ++ ret = -EFAULT; ++ } ++ } ++ } ++ ++ if (ret != 0) ++ up(&instance->remove_event); ++ mutex_unlock(&instance->completion_mutex); ++ DEBUG_TRACE(AWAIT_COMPLETION_LINE); ++ } break; ++ ++ case VCHIQ_IOC_DEQUEUE_MESSAGE: { ++ VCHIQ_DEQUEUE_MESSAGE_T args; ++ USER_SERVICE_T *user_service; ++ VCHIQ_HEADER_T *header; ++ ++ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE); ++ if (copy_from_user ++ (&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ service = find_service_for_instance(instance, args.handle); ++ if (!service) { ++ ret = -EINVAL; ++ break; ++ } ++ user_service = (USER_SERVICE_T *)service->base.userdata; ++ if (user_service->is_vchi == 0) { ++ ret = -EINVAL; ++ break; ++ } ++ ++ spin_lock(&msg_queue_spinlock); ++ if (user_service->msg_remove == user_service->msg_insert) { ++ if (!args.blocking) { ++ spin_unlock(&msg_queue_spinlock); ++ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE); ++ ret = -EWOULDBLOCK; ++ break; ++ } ++ user_service->dequeue_pending = 1; ++ do { ++ spin_unlock(&msg_queue_spinlock); ++ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE); ++ if (down_interruptible( ++ &user_service->insert_event) != 0) { ++ vchiq_log_info(vchiq_arm_log_level, ++ "DEQUEUE_MESSAGE interrupted"); ++ ret = -EINTR; ++ break; ++ } ++ spin_lock(&msg_queue_spinlock); ++ } while (user_service->msg_remove == ++ user_service->msg_insert); ++ ++ if (ret) ++ break; ++ } ++ ++ BUG_ON((int)(user_service->msg_insert - ++ user_service->msg_remove) < 0); ++ ++ header = user_service->msg_queue[user_service->msg_remove & ++ (MSG_QUEUE_SIZE - 1)]; ++ user_service->msg_remove++; ++ spin_unlock(&msg_queue_spinlock); ++ ++ up(&user_service->remove_event); ++ if (header == NULL) ++ ret = -ENOTCONN; ++ else if (header->size <= args.bufsize) { ++ /* Copy to user space if msgbuf is not NULL */ ++ if ((args.buf == NULL) || ++ (copy_to_user((void __user *)args.buf, ++ header->data, ++ header->size) == 0)) { ++ ret = header->size; ++ vchiq_release_message( ++ service->handle, ++ header); ++ } else ++ ret = -EFAULT; ++ } else { ++ vchiq_log_error(vchiq_arm_log_level, ++ "header %x: bufsize %x < size %x", ++ (unsigned int)header, args.bufsize, ++ header->size); ++ WARN(1, "invalid size\n"); ++ ret = -EMSGSIZE; ++ } ++ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE); ++ } break; ++ ++ case VCHIQ_IOC_GET_CLIENT_ID: { ++ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg; ++ ++ ret = vchiq_get_client_id(handle); ++ } break; ++ ++ case VCHIQ_IOC_GET_CONFIG: { ++ VCHIQ_GET_CONFIG_T args; ++ VCHIQ_CONFIG_T config; ++ ++ if (copy_from_user(&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ if (args.config_size > sizeof(config)) { ++ ret = -EINVAL; ++ break; ++ } ++ status = vchiq_get_config(instance, args.config_size, &config); ++ if (status == VCHIQ_SUCCESS) { ++ if (copy_to_user((void __user *)args.pconfig, ++ &config, args.config_size) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ } ++ } break; ++ ++ case VCHIQ_IOC_SET_SERVICE_OPTION: { ++ VCHIQ_SET_SERVICE_OPTION_T args; ++ ++ if (copy_from_user( ++ &args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ ++ service = find_service_for_instance(instance, args.handle); ++ if (!service) { ++ ret = -EINVAL; ++ break; ++ } ++ ++ status = vchiq_set_service_option( ++ args.handle, args.option, args.value); ++ } break; ++ ++ case VCHIQ_IOC_DUMP_PHYS_MEM: { ++ VCHIQ_DUMP_MEM_T args; ++ ++ if (copy_from_user ++ (&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ dump_phys_mem(args.virt_addr, args.num_bytes); ++ } break; ++ ++ case VCHIQ_IOC_LIB_VERSION: { ++ unsigned int lib_version = (unsigned int)arg; ++ ++ if (lib_version < VCHIQ_VERSION_MIN) ++ ret = -EINVAL; ++ else if (lib_version >= VCHIQ_VERSION_CLOSE_DELIVERED) ++ instance->use_close_delivered = 1; ++ } break; ++ ++ case VCHIQ_IOC_CLOSE_DELIVERED: { ++ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg; ++ ++ service = find_closed_service_for_instance(instance, handle); ++ if (service != NULL) { ++ USER_SERVICE_T *user_service = ++ (USER_SERVICE_T *)service->base.userdata; ++ close_delivered(user_service); ++ } ++ else ++ ret = -EINVAL; ++ } break; ++ ++ default: ++ ret = -ENOTTY; ++ break; ++ } ++ ++ if (service) ++ unlock_service(service); ++ ++ if (ret == 0) { ++ if (status == VCHIQ_ERROR) ++ ret = -EIO; ++ else if (status == VCHIQ_RETRY) ++ ret = -EINTR; ++ } ++ ++ if ((status == VCHIQ_SUCCESS) && (ret < 0) && (ret != -EINTR) && ++ (ret != -EWOULDBLOCK)) ++ vchiq_log_info(vchiq_arm_log_level, ++ " ioctl instance %lx, cmd %s -> status %d, %ld", ++ (unsigned long)instance, ++ (_IOC_NR(cmd) <= VCHIQ_IOC_MAX) ? ++ ioctl_names[_IOC_NR(cmd)] : ++ "", ++ status, ret); ++ else ++ vchiq_log_trace(vchiq_arm_log_level, ++ " ioctl instance %lx, cmd %s -> status %d, %ld", ++ (unsigned long)instance, ++ (_IOC_NR(cmd) <= VCHIQ_IOC_MAX) ? ++ ioctl_names[_IOC_NR(cmd)] : ++ "", ++ status, ret); ++ ++ return ret; ++} ++ ++/**************************************************************************** ++* ++* vchiq_open ++* ++***************************************************************************/ ++ ++static int ++vchiq_open(struct inode *inode, struct file *file) ++{ ++ int dev = iminor(inode) & 0x0f; ++ vchiq_log_info(vchiq_arm_log_level, "vchiq_open"); ++ switch (dev) { ++ case VCHIQ_MINOR: { ++ int ret; ++ VCHIQ_STATE_T *state = vchiq_get_state(); ++ VCHIQ_INSTANCE_T instance; ++ ++ if (!state) { ++ vchiq_log_error(vchiq_arm_log_level, ++ "vchiq has no connection to VideoCore"); ++ return -ENOTCONN; ++ } ++ ++ instance = kzalloc(sizeof(*instance), GFP_KERNEL); ++ if (!instance) ++ return -ENOMEM; ++ ++ instance->state = state; ++ instance->pid = current->tgid; ++ ++ ret = vchiq_debugfs_add_instance(instance); ++ if (ret != 0) { ++ kfree(instance); ++ return ret; ++ } ++ ++ sema_init(&instance->insert_event, 0); ++ sema_init(&instance->remove_event, 0); ++ mutex_init(&instance->completion_mutex); ++ mutex_init(&instance->bulk_waiter_list_mutex); ++ INIT_LIST_HEAD(&instance->bulk_waiter_list); ++ ++ file->private_data = instance; ++ } break; ++ ++ default: ++ vchiq_log_error(vchiq_arm_log_level, ++ "Unknown minor device: %d", dev); ++ return -ENXIO; ++ } ++ ++ return 0; ++} ++ ++/**************************************************************************** ++* ++* vchiq_release ++* ++***************************************************************************/ ++ ++static int ++vchiq_release(struct inode *inode, struct file *file) ++{ ++ int dev = iminor(inode) & 0x0f; ++ int ret = 0; ++ switch (dev) { ++ case VCHIQ_MINOR: { ++ VCHIQ_INSTANCE_T instance = file->private_data; ++ VCHIQ_STATE_T *state = vchiq_get_state(); ++ VCHIQ_SERVICE_T *service; ++ int i; ++ ++ vchiq_log_info(vchiq_arm_log_level, ++ "vchiq_release: instance=%lx", ++ (unsigned long)instance); ++ ++ if (!state) { ++ ret = -EPERM; ++ goto out; ++ } ++ ++ /* Ensure videocore is awake to allow termination. */ ++ vchiq_use_internal(instance->state, NULL, ++ USE_TYPE_VCHIQ); ++ ++ mutex_lock(&instance->completion_mutex); ++ ++ /* Wake the completion thread and ask it to exit */ ++ instance->closing = 1; ++ up(&instance->insert_event); ++ ++ mutex_unlock(&instance->completion_mutex); ++ ++ /* Wake the slot handler if the completion queue is full. */ ++ up(&instance->remove_event); ++ ++ /* Mark all services for termination... */ ++ i = 0; ++ while ((service = next_service_by_instance(state, instance, ++ &i)) != NULL) { ++ USER_SERVICE_T *user_service = service->base.userdata; ++ ++ /* Wake the slot handler if the msg queue is full. */ ++ up(&user_service->remove_event); ++ ++ vchiq_terminate_service_internal(service); ++ unlock_service(service); ++ } ++ ++ /* ...and wait for them to die */ ++ i = 0; ++ while ((service = next_service_by_instance(state, instance, &i)) ++ != NULL) { ++ USER_SERVICE_T *user_service = service->base.userdata; ++ ++ down(&service->remove_event); ++ ++ BUG_ON(service->srvstate != VCHIQ_SRVSTATE_FREE); ++ ++ spin_lock(&msg_queue_spinlock); ++ ++ while (user_service->msg_remove != ++ user_service->msg_insert) { ++ VCHIQ_HEADER_T *header = user_service-> ++ msg_queue[user_service->msg_remove & ++ (MSG_QUEUE_SIZE - 1)]; ++ user_service->msg_remove++; ++ spin_unlock(&msg_queue_spinlock); ++ ++ if (header) ++ vchiq_release_message( ++ service->handle, ++ header); ++ spin_lock(&msg_queue_spinlock); ++ } ++ ++ spin_unlock(&msg_queue_spinlock); ++ ++ unlock_service(service); ++ } ++ ++ /* Release any closed services */ ++ while (instance->completion_remove != ++ instance->completion_insert) { ++ VCHIQ_COMPLETION_DATA_T *completion; ++ VCHIQ_SERVICE_T *service; ++ completion = &instance->completions[ ++ instance->completion_remove & ++ (MAX_COMPLETIONS - 1)]; ++ service = completion->service_userdata; ++ if (completion->reason == VCHIQ_SERVICE_CLOSED) ++ { ++ USER_SERVICE_T *user_service = ++ service->base.userdata; ++ ++ /* Wake any blocked user-thread */ ++ if (instance->use_close_delivered) ++ up(&user_service->close_event); ++ unlock_service(service); ++ } ++ instance->completion_remove++; ++ } ++ ++ /* Release the PEER service count. */ ++ vchiq_release_internal(instance->state, NULL); ++ ++ { ++ struct list_head *pos, *next; ++ list_for_each_safe(pos, next, ++ &instance->bulk_waiter_list) { ++ struct bulk_waiter_node *waiter; ++ waiter = list_entry(pos, ++ struct bulk_waiter_node, ++ list); ++ list_del(pos); ++ vchiq_log_info(vchiq_arm_log_level, ++ "bulk_waiter - cleaned up %x " ++ "for pid %d", ++ (unsigned int)waiter, waiter->pid); ++ kfree(waiter); ++ } ++ } ++ ++ vchiq_debugfs_remove_instance(instance); ++ ++ kfree(instance); ++ file->private_data = NULL; ++ } break; ++ ++ default: ++ vchiq_log_error(vchiq_arm_log_level, ++ "Unknown minor device: %d", dev); ++ ret = -ENXIO; ++ } ++ ++out: ++ return ret; ++} ++ ++/**************************************************************************** ++* ++* vchiq_dump ++* ++***************************************************************************/ ++ ++void ++vchiq_dump(void *dump_context, const char *str, int len) ++{ ++ DUMP_CONTEXT_T *context = (DUMP_CONTEXT_T *)dump_context; ++ ++ if (context->actual < context->space) { ++ int copy_bytes; ++ if (context->offset > 0) { ++ int skip_bytes = min(len, (int)context->offset); ++ str += skip_bytes; ++ len -= skip_bytes; ++ context->offset -= skip_bytes; ++ if (context->offset > 0) ++ return; ++ } ++ copy_bytes = min(len, (int)(context->space - context->actual)); ++ if (copy_bytes == 0) ++ return; ++ if (copy_to_user(context->buf + context->actual, str, ++ copy_bytes)) ++ context->actual = -EFAULT; ++ context->actual += copy_bytes; ++ len -= copy_bytes; ++ ++ /* If tne terminating NUL is included in the length, then it ++ ** marks the end of a line and should be replaced with a ++ ** carriage return. */ ++ if ((len == 0) && (str[copy_bytes - 1] == '\0')) { ++ char cr = '\n'; ++ if (copy_to_user(context->buf + context->actual - 1, ++ &cr, 1)) ++ context->actual = -EFAULT; ++ } ++ } ++} ++ ++/**************************************************************************** ++* ++* vchiq_dump_platform_instance_state ++* ++***************************************************************************/ ++ ++void ++vchiq_dump_platform_instances(void *dump_context) ++{ ++ VCHIQ_STATE_T *state = vchiq_get_state(); ++ char buf[80]; ++ int len; ++ int i; ++ ++ /* There is no list of instances, so instead scan all services, ++ marking those that have been dumped. */ ++ ++ for (i = 0; i < state->unused_service; i++) { ++ VCHIQ_SERVICE_T *service = state->services[i]; ++ VCHIQ_INSTANCE_T instance; ++ ++ if (service && (service->base.callback == service_callback)) { ++ instance = service->instance; ++ if (instance) ++ instance->mark = 0; ++ } ++ } ++ ++ for (i = 0; i < state->unused_service; i++) { ++ VCHIQ_SERVICE_T *service = state->services[i]; ++ VCHIQ_INSTANCE_T instance; ++ ++ if (service && (service->base.callback == service_callback)) { ++ instance = service->instance; ++ if (instance && !instance->mark) { ++ len = snprintf(buf, sizeof(buf), ++ "Instance %x: pid %d,%s completions " ++ "%d/%d", ++ (unsigned int)instance, instance->pid, ++ instance->connected ? " connected, " : ++ "", ++ instance->completion_insert - ++ instance->completion_remove, ++ MAX_COMPLETIONS); ++ ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ instance->mark = 1; ++ } ++ } ++ } ++} ++ ++/**************************************************************************** ++* ++* vchiq_dump_platform_service_state ++* ++***************************************************************************/ ++ ++void ++vchiq_dump_platform_service_state(void *dump_context, VCHIQ_SERVICE_T *service) ++{ ++ USER_SERVICE_T *user_service = (USER_SERVICE_T *)service->base.userdata; ++ char buf[80]; ++ int len; ++ ++ len = snprintf(buf, sizeof(buf), " instance %x", ++ (unsigned int)service->instance); ++ ++ if ((service->base.callback == service_callback) && ++ user_service->is_vchi) { ++ len += snprintf(buf + len, sizeof(buf) - len, ++ ", %d/%d messages", ++ user_service->msg_insert - user_service->msg_remove, ++ MSG_QUEUE_SIZE); ++ ++ if (user_service->dequeue_pending) ++ len += snprintf(buf + len, sizeof(buf) - len, ++ " (dequeue pending)"); ++ } ++ ++ vchiq_dump(dump_context, buf, len + 1); ++} ++ ++/**************************************************************************** ++* ++* dump_user_mem ++* ++***************************************************************************/ ++ ++static void ++dump_phys_mem(void *virt_addr, uint32_t num_bytes) ++{ ++ int rc; ++ uint8_t *end_virt_addr = virt_addr + num_bytes; ++ int num_pages; ++ int offset; ++ int end_offset; ++ int page_idx; ++ int prev_idx; ++ struct page *page; ++ struct page **pages; ++ uint8_t *kmapped_virt_ptr; ++ ++ /* Align virtAddr and endVirtAddr to 16 byte boundaries. */ ++ ++ virt_addr = (void *)((unsigned long)virt_addr & ~0x0fuL); ++ end_virt_addr = (void *)(((unsigned long)end_virt_addr + 15uL) & ++ ~0x0fuL); ++ ++ offset = (int)(long)virt_addr & (PAGE_SIZE - 1); ++ end_offset = (int)(long)end_virt_addr & (PAGE_SIZE - 1); ++ ++ num_pages = (offset + num_bytes + PAGE_SIZE - 1) / PAGE_SIZE; ++ ++ pages = kmalloc(sizeof(struct page *) * num_pages, GFP_KERNEL); ++ if (pages == NULL) { ++ vchiq_log_error(vchiq_arm_log_level, ++ "Unable to allocation memory for %d pages\n", ++ num_pages); ++ return; ++ } ++ ++ down_read(¤t->mm->mmap_sem); ++ rc = get_user_pages(current, /* task */ ++ current->mm, /* mm */ ++ (unsigned long)virt_addr, /* start */ ++ num_pages, /* len */ ++ 0, /* write */ ++ 0, /* force */ ++ pages, /* pages (array of page pointers) */ ++ NULL); /* vmas */ ++ up_read(¤t->mm->mmap_sem); ++ ++ prev_idx = -1; ++ page = NULL; ++ ++ while (offset < end_offset) { ++ ++ int page_offset = offset % PAGE_SIZE; ++ page_idx = offset / PAGE_SIZE; ++ ++ if (page_idx != prev_idx) { ++ ++ if (page != NULL) ++ kunmap(page); ++ page = pages[page_idx]; ++ kmapped_virt_ptr = kmap(page); ++ ++ prev_idx = page_idx; ++ } ++ ++ if (vchiq_arm_log_level >= VCHIQ_LOG_TRACE) ++ vchiq_log_dump_mem("ph", ++ (uint32_t)(unsigned long)&kmapped_virt_ptr[ ++ page_offset], ++ &kmapped_virt_ptr[page_offset], 16); ++ ++ offset += 16; ++ } ++ if (page != NULL) ++ kunmap(page); ++ ++ for (page_idx = 0; page_idx < num_pages; page_idx++) ++ page_cache_release(pages[page_idx]); ++ ++ kfree(pages); ++} ++ ++/**************************************************************************** ++* ++* vchiq_read ++* ++***************************************************************************/ ++ ++static ssize_t ++vchiq_read(struct file *file, char __user *buf, ++ size_t count, loff_t *ppos) ++{ ++ DUMP_CONTEXT_T context; ++ context.buf = buf; ++ context.actual = 0; ++ context.space = count; ++ context.offset = *ppos; ++ ++ vchiq_dump_state(&context, &g_state); ++ ++ *ppos += context.actual; ++ ++ return context.actual; ++} ++ ++VCHIQ_STATE_T * ++vchiq_get_state(void) ++{ ++ ++ if (g_state.remote == NULL) ++ printk(KERN_ERR "%s: g_state.remote == NULL\n", __func__); ++ else if (g_state.remote->initialised != 1) ++ printk(KERN_NOTICE "%s: g_state.remote->initialised != 1 (%d)\n", ++ __func__, g_state.remote->initialised); ++ ++ return ((g_state.remote != NULL) && ++ (g_state.remote->initialised == 1)) ? &g_state : NULL; ++} ++ ++static const struct file_operations ++vchiq_fops = { ++ .owner = THIS_MODULE, ++ .unlocked_ioctl = vchiq_ioctl, ++ .open = vchiq_open, ++ .release = vchiq_release, ++ .read = vchiq_read ++}; ++ ++/* ++ * Autosuspend related functionality ++ */ ++ ++int ++vchiq_videocore_wanted(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ if (!arm_state) ++ /* autosuspend not supported - always return wanted */ ++ return 1; ++ else if (arm_state->blocked_count) ++ return 1; ++ else if (!arm_state->videocore_use_count) ++ /* usage count zero - check for override unless we're forcing */ ++ if (arm_state->resume_blocked) ++ return 0; ++ else ++ return vchiq_platform_videocore_wanted(state); ++ else ++ /* non-zero usage count - videocore still required */ ++ return 1; ++} ++ ++static VCHIQ_STATUS_T ++vchiq_keepalive_vchiq_callback(VCHIQ_REASON_T reason, ++ VCHIQ_HEADER_T *header, ++ VCHIQ_SERVICE_HANDLE_T service_user, ++ void *bulk_user) ++{ ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s callback reason %d", __func__, reason); ++ return 0; ++} ++ ++static int ++vchiq_keepalive_thread_func(void *v) ++{ ++ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v; ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ ++ VCHIQ_STATUS_T status; ++ VCHIQ_INSTANCE_T instance; ++ VCHIQ_SERVICE_HANDLE_T ka_handle; ++ ++ VCHIQ_SERVICE_PARAMS_T params = { ++ .fourcc = VCHIQ_MAKE_FOURCC('K', 'E', 'E', 'P'), ++ .callback = vchiq_keepalive_vchiq_callback, ++ .version = KEEPALIVE_VER, ++ .version_min = KEEPALIVE_VER_MIN ++ }; ++ ++ status = vchiq_initialise(&instance); ++ if (status != VCHIQ_SUCCESS) { ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s vchiq_initialise failed %d", __func__, status); ++ goto exit; ++ } ++ ++ status = vchiq_connect(instance); ++ if (status != VCHIQ_SUCCESS) { ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s vchiq_connect failed %d", __func__, status); ++ goto shutdown; ++ } ++ ++ status = vchiq_add_service(instance, ¶ms, &ka_handle); ++ if (status != VCHIQ_SUCCESS) { ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s vchiq_open_service failed %d", __func__, status); ++ goto shutdown; ++ } ++ ++ while (1) { ++ long rc = 0, uc = 0; ++ if (wait_for_completion_interruptible(&arm_state->ka_evt) ++ != 0) { ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s interrupted", __func__); ++ flush_signals(current); ++ continue; ++ } ++ ++ /* read and clear counters. Do release_count then use_count to ++ * prevent getting more releases than uses */ ++ rc = atomic_xchg(&arm_state->ka_release_count, 0); ++ uc = atomic_xchg(&arm_state->ka_use_count, 0); ++ ++ /* Call use/release service the requisite number of times. ++ * Process use before release so use counts don't go negative */ ++ while (uc--) { ++ atomic_inc(&arm_state->ka_use_ack_count); ++ status = vchiq_use_service(ka_handle); ++ if (status != VCHIQ_SUCCESS) { ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s vchiq_use_service error %d", ++ __func__, status); ++ } ++ } ++ while (rc--) { ++ status = vchiq_release_service(ka_handle); ++ if (status != VCHIQ_SUCCESS) { ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s vchiq_release_service error %d", ++ __func__, status); ++ } ++ } ++ } ++ ++shutdown: ++ vchiq_shutdown(instance); ++exit: ++ return 0; ++} ++ ++ ++ ++VCHIQ_STATUS_T ++vchiq_arm_init_state(VCHIQ_STATE_T *state, VCHIQ_ARM_STATE_T *arm_state) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ ++ if (arm_state) { ++ rwlock_init(&arm_state->susp_res_lock); ++ ++ init_completion(&arm_state->ka_evt); ++ atomic_set(&arm_state->ka_use_count, 0); ++ atomic_set(&arm_state->ka_use_ack_count, 0); ++ atomic_set(&arm_state->ka_release_count, 0); ++ ++ init_completion(&arm_state->vc_suspend_complete); ++ ++ init_completion(&arm_state->vc_resume_complete); ++ /* Initialise to 'done' state. We only want to block on resume ++ * completion while videocore is suspended. */ ++ set_resume_state(arm_state, VC_RESUME_RESUMED); ++ ++ init_completion(&arm_state->resume_blocker); ++ /* Initialise to 'done' state. We only want to block on this ++ * completion while resume is blocked */ ++ complete_all(&arm_state->resume_blocker); ++ ++ init_completion(&arm_state->blocked_blocker); ++ /* Initialise to 'done' state. We only want to block on this ++ * completion while things are waiting on the resume blocker */ ++ complete_all(&arm_state->blocked_blocker); ++ ++ arm_state->suspend_timer_timeout = SUSPEND_TIMER_TIMEOUT_MS; ++ arm_state->suspend_timer_running = 0; ++ init_timer(&arm_state->suspend_timer); ++ arm_state->suspend_timer.data = (unsigned long)(state); ++ arm_state->suspend_timer.function = suspend_timer_callback; ++ ++ arm_state->first_connect = 0; ++ ++ } ++ return status; ++} ++ ++/* ++** Functions to modify the state variables; ++** set_suspend_state ++** set_resume_state ++** ++** There are more state variables than we might like, so ensure they remain in ++** step. Suspend and resume state are maintained separately, since most of ++** these state machines can operate independently. However, there are a few ++** states where state transitions in one state machine cause a reset to the ++** other state machine. In addition, there are some completion events which ++** need to occur on state machine reset and end-state(s), so these are also ++** dealt with in these functions. ++** ++** In all states we set the state variable according to the input, but in some ++** cases we perform additional steps outlined below; ++** ++** VC_SUSPEND_IDLE - Initialise the suspend completion at the same time. ++** The suspend completion is completed after any suspend ++** attempt. When we reset the state machine we also reset ++** the completion. This reset occurs when videocore is ++** resumed, and also if we initiate suspend after a suspend ++** failure. ++** ++** VC_SUSPEND_IN_PROGRESS - This state is considered the point of no return for ++** suspend - ie from this point on we must try to suspend ++** before resuming can occur. We therefore also reset the ++** resume state machine to VC_RESUME_IDLE in this state. ++** ++** VC_SUSPEND_SUSPENDED - Suspend has completed successfully. Also call ++** complete_all on the suspend completion to notify ++** anything waiting for suspend to happen. ++** ++** VC_SUSPEND_REJECTED - Videocore rejected suspend. Videocore will also ++** initiate resume, so no need to alter resume state. ++** We call complete_all on the suspend completion to notify ++** of suspend rejection. ++** ++** VC_SUSPEND_FAILED - We failed to initiate videocore suspend. We notify the ++** suspend completion and reset the resume state machine. ++** ++** VC_RESUME_IDLE - Initialise the resume completion at the same time. The ++** resume completion is in it's 'done' state whenever ++** videcore is running. Therfore, the VC_RESUME_IDLE state ++** implies that videocore is suspended. ++** Hence, any thread which needs to wait until videocore is ++** running can wait on this completion - it will only block ++** if videocore is suspended. ++** ++** VC_RESUME_RESUMED - Resume has completed successfully. Videocore is running. ++** Call complete_all on the resume completion to unblock ++** any threads waiting for resume. Also reset the suspend ++** state machine to it's idle state. ++** ++** VC_RESUME_FAILED - Currently unused - no mechanism to fail resume exists. ++*/ ++ ++void ++set_suspend_state(VCHIQ_ARM_STATE_T *arm_state, ++ enum vc_suspend_status new_state) ++{ ++ /* set the state in all cases */ ++ arm_state->vc_suspend_state = new_state; ++ ++ /* state specific additional actions */ ++ switch (new_state) { ++ case VC_SUSPEND_FORCE_CANCELED: ++ complete_all(&arm_state->vc_suspend_complete); ++ break; ++ case VC_SUSPEND_REJECTED: ++ complete_all(&arm_state->vc_suspend_complete); ++ break; ++ case VC_SUSPEND_FAILED: ++ complete_all(&arm_state->vc_suspend_complete); ++ arm_state->vc_resume_state = VC_RESUME_RESUMED; ++ complete_all(&arm_state->vc_resume_complete); ++ break; ++ case VC_SUSPEND_IDLE: ++ reinit_completion(&arm_state->vc_suspend_complete); ++ break; ++ case VC_SUSPEND_REQUESTED: ++ break; ++ case VC_SUSPEND_IN_PROGRESS: ++ set_resume_state(arm_state, VC_RESUME_IDLE); ++ break; ++ case VC_SUSPEND_SUSPENDED: ++ complete_all(&arm_state->vc_suspend_complete); ++ break; ++ default: ++ BUG(); ++ break; ++ } ++} ++ ++void ++set_resume_state(VCHIQ_ARM_STATE_T *arm_state, ++ enum vc_resume_status new_state) ++{ ++ /* set the state in all cases */ ++ arm_state->vc_resume_state = new_state; ++ ++ /* state specific additional actions */ ++ switch (new_state) { ++ case VC_RESUME_FAILED: ++ break; ++ case VC_RESUME_IDLE: ++ reinit_completion(&arm_state->vc_resume_complete); ++ break; ++ case VC_RESUME_REQUESTED: ++ break; ++ case VC_RESUME_IN_PROGRESS: ++ break; ++ case VC_RESUME_RESUMED: ++ complete_all(&arm_state->vc_resume_complete); ++ set_suspend_state(arm_state, VC_SUSPEND_IDLE); ++ break; ++ default: ++ BUG(); ++ break; ++ } ++} ++ ++ ++/* should be called with the write lock held */ ++inline void ++start_suspend_timer(VCHIQ_ARM_STATE_T *arm_state) ++{ ++ del_timer(&arm_state->suspend_timer); ++ arm_state->suspend_timer.expires = jiffies + ++ msecs_to_jiffies(arm_state-> ++ suspend_timer_timeout); ++ add_timer(&arm_state->suspend_timer); ++ arm_state->suspend_timer_running = 1; ++} ++ ++/* should be called with the write lock held */ ++static inline void ++stop_suspend_timer(VCHIQ_ARM_STATE_T *arm_state) ++{ ++ if (arm_state->suspend_timer_running) { ++ del_timer(&arm_state->suspend_timer); ++ arm_state->suspend_timer_running = 0; ++ } ++} ++ ++static inline int ++need_resume(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ return (arm_state->vc_suspend_state > VC_SUSPEND_IDLE) && ++ (arm_state->vc_resume_state < VC_RESUME_REQUESTED) && ++ vchiq_videocore_wanted(state); ++} ++ ++static int ++block_resume(VCHIQ_ARM_STATE_T *arm_state) ++{ ++ int status = VCHIQ_SUCCESS; ++ const unsigned long timeout_val = ++ msecs_to_jiffies(FORCE_SUSPEND_TIMEOUT_MS); ++ int resume_count = 0; ++ ++ /* Allow any threads which were blocked by the last force suspend to ++ * complete if they haven't already. Only give this one shot; if ++ * blocked_count is incremented after blocked_blocker is completed ++ * (which only happens when blocked_count hits 0) then those threads ++ * will have to wait until next time around */ ++ if (arm_state->blocked_count) { ++ reinit_completion(&arm_state->blocked_blocker); ++ write_unlock_bh(&arm_state->susp_res_lock); ++ vchiq_log_info(vchiq_susp_log_level, "%s wait for previously " ++ "blocked clients", __func__); ++ if (wait_for_completion_interruptible_timeout( ++ &arm_state->blocked_blocker, timeout_val) ++ <= 0) { ++ vchiq_log_error(vchiq_susp_log_level, "%s wait for " ++ "previously blocked clients failed" , __func__); ++ status = VCHIQ_ERROR; ++ write_lock_bh(&arm_state->susp_res_lock); ++ goto out; ++ } ++ vchiq_log_info(vchiq_susp_log_level, "%s previously blocked " ++ "clients resumed", __func__); ++ write_lock_bh(&arm_state->susp_res_lock); ++ } ++ ++ /* We need to wait for resume to complete if it's in process */ ++ while (arm_state->vc_resume_state != VC_RESUME_RESUMED && ++ arm_state->vc_resume_state > VC_RESUME_IDLE) { ++ if (resume_count > 1) { ++ status = VCHIQ_ERROR; ++ vchiq_log_error(vchiq_susp_log_level, "%s waited too " ++ "many times for resume" , __func__); ++ goto out; ++ } ++ write_unlock_bh(&arm_state->susp_res_lock); ++ vchiq_log_info(vchiq_susp_log_level, "%s wait for resume", ++ __func__); ++ if (wait_for_completion_interruptible_timeout( ++ &arm_state->vc_resume_complete, timeout_val) ++ <= 0) { ++ vchiq_log_error(vchiq_susp_log_level, "%s wait for " ++ "resume failed (%s)", __func__, ++ resume_state_names[arm_state->vc_resume_state + ++ VC_RESUME_NUM_OFFSET]); ++ status = VCHIQ_ERROR; ++ write_lock_bh(&arm_state->susp_res_lock); ++ goto out; ++ } ++ vchiq_log_info(vchiq_susp_log_level, "%s resumed", __func__); ++ write_lock_bh(&arm_state->susp_res_lock); ++ resume_count++; ++ } ++ reinit_completion(&arm_state->resume_blocker); ++ arm_state->resume_blocked = 1; ++ ++out: ++ return status; ++} ++ ++static inline void ++unblock_resume(VCHIQ_ARM_STATE_T *arm_state) ++{ ++ complete_all(&arm_state->resume_blocker); ++ arm_state->resume_blocked = 0; ++} ++ ++/* Initiate suspend via slot handler. Should be called with the write lock ++ * held */ ++VCHIQ_STATUS_T ++vchiq_arm_vcsuspend(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_ERROR; ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ ++ if (!arm_state) ++ goto out; ++ ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ status = VCHIQ_SUCCESS; ++ ++ ++ switch (arm_state->vc_suspend_state) { ++ case VC_SUSPEND_REQUESTED: ++ vchiq_log_info(vchiq_susp_log_level, "%s: suspend already " ++ "requested", __func__); ++ break; ++ case VC_SUSPEND_IN_PROGRESS: ++ vchiq_log_info(vchiq_susp_log_level, "%s: suspend already in " ++ "progress", __func__); ++ break; ++ ++ default: ++ /* We don't expect to be in other states, so log but continue ++ * anyway */ ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s unexpected suspend state %s", __func__, ++ suspend_state_names[arm_state->vc_suspend_state + ++ VC_SUSPEND_NUM_OFFSET]); ++ /* fall through */ ++ case VC_SUSPEND_REJECTED: ++ case VC_SUSPEND_FAILED: ++ /* Ensure any idle state actions have been run */ ++ set_suspend_state(arm_state, VC_SUSPEND_IDLE); ++ /* fall through */ ++ case VC_SUSPEND_IDLE: ++ vchiq_log_info(vchiq_susp_log_level, ++ "%s: suspending", __func__); ++ set_suspend_state(arm_state, VC_SUSPEND_REQUESTED); ++ /* kick the slot handler thread to initiate suspend */ ++ request_poll(state, NULL, 0); ++ break; ++ } ++ ++out: ++ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, status); ++ return status; ++} ++ ++void ++vchiq_platform_check_suspend(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ int susp = 0; ++ ++ if (!arm_state) ++ goto out; ++ ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ ++ write_lock_bh(&arm_state->susp_res_lock); ++ if (arm_state->vc_suspend_state == VC_SUSPEND_REQUESTED && ++ arm_state->vc_resume_state == VC_RESUME_RESUMED) { ++ set_suspend_state(arm_state, VC_SUSPEND_IN_PROGRESS); ++ susp = 1; ++ } ++ write_unlock_bh(&arm_state->susp_res_lock); ++ ++ if (susp) ++ vchiq_platform_suspend(state); ++ ++out: ++ vchiq_log_trace(vchiq_susp_log_level, "%s exit", __func__); ++ return; ++} ++ ++ ++static void ++output_timeout_error(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ char service_err[50] = ""; ++ int vc_use_count = arm_state->videocore_use_count; ++ int active_services = state->unused_service; ++ int i; ++ ++ if (!arm_state->videocore_use_count) { ++ snprintf(service_err, 50, " Videocore usecount is 0"); ++ goto output_msg; ++ } ++ for (i = 0; i < active_services; i++) { ++ VCHIQ_SERVICE_T *service_ptr = state->services[i]; ++ if (service_ptr && service_ptr->service_use_count && ++ (service_ptr->srvstate != VCHIQ_SRVSTATE_FREE)) { ++ snprintf(service_err, 50, " %c%c%c%c(%d) service has " ++ "use count %d%s", VCHIQ_FOURCC_AS_4CHARS( ++ service_ptr->base.fourcc), ++ service_ptr->client_id, ++ service_ptr->service_use_count, ++ service_ptr->service_use_count == ++ vc_use_count ? "" : " (+ more)"); ++ break; ++ } ++ } ++ ++output_msg: ++ vchiq_log_error(vchiq_susp_log_level, ++ "timed out waiting for vc suspend (%d).%s", ++ arm_state->autosuspend_override, service_err); ++ ++} ++ ++/* Try to get videocore into suspended state, regardless of autosuspend state. ++** We don't actually force suspend, since videocore may get into a bad state ++** if we force suspend at a bad time. Instead, we wait for autosuspend to ++** determine a good point to suspend. If this doesn't happen within 100ms we ++** report failure. ++** ++** Returns VCHIQ_SUCCESS if videocore suspended successfully, VCHIQ_RETRY if ++** videocore failed to suspend in time or VCHIQ_ERROR if interrupted. ++*/ ++VCHIQ_STATUS_T ++vchiq_arm_force_suspend(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ VCHIQ_STATUS_T status = VCHIQ_ERROR; ++ long rc = 0; ++ int repeat = -1; ++ ++ if (!arm_state) ++ goto out; ++ ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ ++ write_lock_bh(&arm_state->susp_res_lock); ++ ++ status = block_resume(arm_state); ++ if (status != VCHIQ_SUCCESS) ++ goto unlock; ++ if (arm_state->vc_suspend_state == VC_SUSPEND_SUSPENDED) { ++ /* Already suspended - just block resume and exit */ ++ vchiq_log_info(vchiq_susp_log_level, "%s already suspended", ++ __func__); ++ status = VCHIQ_SUCCESS; ++ goto unlock; ++ } else if (arm_state->vc_suspend_state <= VC_SUSPEND_IDLE) { ++ /* initiate suspend immediately in the case that we're waiting ++ * for the timeout */ ++ stop_suspend_timer(arm_state); ++ if (!vchiq_videocore_wanted(state)) { ++ vchiq_log_info(vchiq_susp_log_level, "%s videocore " ++ "idle, initiating suspend", __func__); ++ status = vchiq_arm_vcsuspend(state); ++ } else if (arm_state->autosuspend_override < ++ FORCE_SUSPEND_FAIL_MAX) { ++ vchiq_log_info(vchiq_susp_log_level, "%s letting " ++ "videocore go idle", __func__); ++ status = VCHIQ_SUCCESS; ++ } else { ++ vchiq_log_warning(vchiq_susp_log_level, "%s failed too " ++ "many times - attempting suspend", __func__); ++ status = vchiq_arm_vcsuspend(state); ++ } ++ } else { ++ vchiq_log_info(vchiq_susp_log_level, "%s videocore suspend " ++ "in progress - wait for completion", __func__); ++ status = VCHIQ_SUCCESS; ++ } ++ ++ /* Wait for suspend to happen due to system idle (not forced..) */ ++ if (status != VCHIQ_SUCCESS) ++ goto unblock_resume; ++ ++ do { ++ write_unlock_bh(&arm_state->susp_res_lock); ++ ++ rc = wait_for_completion_interruptible_timeout( ++ &arm_state->vc_suspend_complete, ++ msecs_to_jiffies(FORCE_SUSPEND_TIMEOUT_MS)); ++ ++ write_lock_bh(&arm_state->susp_res_lock); ++ if (rc < 0) { ++ vchiq_log_warning(vchiq_susp_log_level, "%s " ++ "interrupted waiting for suspend", __func__); ++ status = VCHIQ_ERROR; ++ goto unblock_resume; ++ } else if (rc == 0) { ++ if (arm_state->vc_suspend_state > VC_SUSPEND_IDLE) { ++ /* Repeat timeout once if in progress */ ++ if (repeat < 0) { ++ repeat = 1; ++ continue; ++ } ++ } ++ arm_state->autosuspend_override++; ++ output_timeout_error(state); ++ ++ status = VCHIQ_RETRY; ++ goto unblock_resume; ++ } ++ } while (0 < (repeat--)); ++ ++ /* Check and report state in case we need to abort ARM suspend */ ++ if (arm_state->vc_suspend_state != VC_SUSPEND_SUSPENDED) { ++ status = VCHIQ_RETRY; ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s videocore suspend failed (state %s)", __func__, ++ suspend_state_names[arm_state->vc_suspend_state + ++ VC_SUSPEND_NUM_OFFSET]); ++ /* Reset the state only if it's still in an error state. ++ * Something could have already initiated another suspend. */ ++ if (arm_state->vc_suspend_state < VC_SUSPEND_IDLE) ++ set_suspend_state(arm_state, VC_SUSPEND_IDLE); ++ ++ goto unblock_resume; ++ } ++ ++ /* successfully suspended - unlock and exit */ ++ goto unlock; ++ ++unblock_resume: ++ /* all error states need to unblock resume before exit */ ++ unblock_resume(arm_state); ++ ++unlock: ++ write_unlock_bh(&arm_state->susp_res_lock); ++ ++out: ++ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, status); ++ return status; ++} ++ ++void ++vchiq_check_suspend(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ ++ if (!arm_state) ++ goto out; ++ ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ ++ write_lock_bh(&arm_state->susp_res_lock); ++ if (arm_state->vc_suspend_state != VC_SUSPEND_SUSPENDED && ++ arm_state->first_connect && ++ !vchiq_videocore_wanted(state)) { ++ vchiq_arm_vcsuspend(state); ++ } ++ write_unlock_bh(&arm_state->susp_res_lock); ++ ++out: ++ vchiq_log_trace(vchiq_susp_log_level, "%s exit", __func__); ++ return; ++} ++ ++ ++int ++vchiq_arm_allow_resume(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ int resume = 0; ++ int ret = -1; ++ ++ if (!arm_state) ++ goto out; ++ ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ ++ write_lock_bh(&arm_state->susp_res_lock); ++ unblock_resume(arm_state); ++ resume = vchiq_check_resume(state); ++ write_unlock_bh(&arm_state->susp_res_lock); ++ ++ if (resume) { ++ if (wait_for_completion_interruptible( ++ &arm_state->vc_resume_complete) < 0) { ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s interrupted", __func__); ++ /* failed, cannot accurately derive suspend ++ * state, so exit early. */ ++ goto out; ++ } ++ } ++ ++ read_lock_bh(&arm_state->susp_res_lock); ++ if (arm_state->vc_suspend_state == VC_SUSPEND_SUSPENDED) { ++ vchiq_log_info(vchiq_susp_log_level, ++ "%s: Videocore remains suspended", __func__); ++ } else { ++ vchiq_log_info(vchiq_susp_log_level, ++ "%s: Videocore resumed", __func__); ++ ret = 0; ++ } ++ read_unlock_bh(&arm_state->susp_res_lock); ++out: ++ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, ret); ++ return ret; ++} ++ ++/* This function should be called with the write lock held */ ++int ++vchiq_check_resume(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ int resume = 0; ++ ++ if (!arm_state) ++ goto out; ++ ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ ++ if (need_resume(state)) { ++ set_resume_state(arm_state, VC_RESUME_REQUESTED); ++ request_poll(state, NULL, 0); ++ resume = 1; ++ } ++ ++out: ++ vchiq_log_trace(vchiq_susp_log_level, "%s exit", __func__); ++ return resume; ++} ++ ++void ++vchiq_platform_check_resume(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ int res = 0; ++ ++ if (!arm_state) ++ goto out; ++ ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ ++ write_lock_bh(&arm_state->susp_res_lock); ++ if (arm_state->wake_address == 0) { ++ vchiq_log_info(vchiq_susp_log_level, ++ "%s: already awake", __func__); ++ goto unlock; ++ } ++ if (arm_state->vc_resume_state == VC_RESUME_IN_PROGRESS) { ++ vchiq_log_info(vchiq_susp_log_level, ++ "%s: already resuming", __func__); ++ goto unlock; ++ } ++ ++ if (arm_state->vc_resume_state == VC_RESUME_REQUESTED) { ++ set_resume_state(arm_state, VC_RESUME_IN_PROGRESS); ++ res = 1; ++ } else ++ vchiq_log_trace(vchiq_susp_log_level, ++ "%s: not resuming (resume state %s)", __func__, ++ resume_state_names[arm_state->vc_resume_state + ++ VC_RESUME_NUM_OFFSET]); ++ ++unlock: ++ write_unlock_bh(&arm_state->susp_res_lock); ++ ++ if (res) ++ vchiq_platform_resume(state); ++ ++out: ++ vchiq_log_trace(vchiq_susp_log_level, "%s exit", __func__); ++ return; ++ ++} ++ ++ ++ ++VCHIQ_STATUS_T ++vchiq_use_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, ++ enum USE_TYPE_E use_type) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ VCHIQ_STATUS_T ret = VCHIQ_SUCCESS; ++ char entity[16]; ++ int *entity_uc; ++ int local_uc, local_entity_uc; ++ ++ if (!arm_state) ++ goto out; ++ ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ ++ if (use_type == USE_TYPE_VCHIQ) { ++ sprintf(entity, "VCHIQ: "); ++ entity_uc = &arm_state->peer_use_count; ++ } else if (service) { ++ sprintf(entity, "%c%c%c%c:%03d", ++ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), ++ service->client_id); ++ entity_uc = &service->service_use_count; ++ } else { ++ vchiq_log_error(vchiq_susp_log_level, "%s null service " ++ "ptr", __func__); ++ ret = VCHIQ_ERROR; ++ goto out; ++ } ++ ++ write_lock_bh(&arm_state->susp_res_lock); ++ while (arm_state->resume_blocked) { ++ /* If we call 'use' while force suspend is waiting for suspend, ++ * then we're about to block the thread which the force is ++ * waiting to complete, so we're bound to just time out. In this ++ * case, set the suspend state such that the wait will be ++ * canceled, so we can complete as quickly as possible. */ ++ if (arm_state->resume_blocked && arm_state->vc_suspend_state == ++ VC_SUSPEND_IDLE) { ++ set_suspend_state(arm_state, VC_SUSPEND_FORCE_CANCELED); ++ break; ++ } ++ /* If suspend is already in progress then we need to block */ ++ if (!try_wait_for_completion(&arm_state->resume_blocker)) { ++ /* Indicate that there are threads waiting on the resume ++ * blocker. These need to be allowed to complete before ++ * a _second_ call to force suspend can complete, ++ * otherwise low priority threads might never actually ++ * continue */ ++ arm_state->blocked_count++; ++ write_unlock_bh(&arm_state->susp_res_lock); ++ vchiq_log_info(vchiq_susp_log_level, "%s %s resume " ++ "blocked - waiting...", __func__, entity); ++ if (wait_for_completion_killable( ++ &arm_state->resume_blocker) != 0) { ++ vchiq_log_error(vchiq_susp_log_level, "%s %s " ++ "wait for resume blocker interrupted", ++ __func__, entity); ++ ret = VCHIQ_ERROR; ++ write_lock_bh(&arm_state->susp_res_lock); ++ arm_state->blocked_count--; ++ write_unlock_bh(&arm_state->susp_res_lock); ++ goto out; ++ } ++ vchiq_log_info(vchiq_susp_log_level, "%s %s resume " ++ "unblocked", __func__, entity); ++ write_lock_bh(&arm_state->susp_res_lock); ++ if (--arm_state->blocked_count == 0) ++ complete_all(&arm_state->blocked_blocker); ++ } ++ } ++ ++ stop_suspend_timer(arm_state); ++ ++ local_uc = ++arm_state->videocore_use_count; ++ local_entity_uc = ++(*entity_uc); ++ ++ /* If there's a pending request which hasn't yet been serviced then ++ * just clear it. If we're past VC_SUSPEND_REQUESTED state then ++ * vc_resume_complete will block until we either resume or fail to ++ * suspend */ ++ if (arm_state->vc_suspend_state <= VC_SUSPEND_REQUESTED) ++ set_suspend_state(arm_state, VC_SUSPEND_IDLE); ++ ++ if ((use_type != USE_TYPE_SERVICE_NO_RESUME) && need_resume(state)) { ++ set_resume_state(arm_state, VC_RESUME_REQUESTED); ++ vchiq_log_info(vchiq_susp_log_level, ++ "%s %s count %d, state count %d", ++ __func__, entity, local_entity_uc, local_uc); ++ request_poll(state, NULL, 0); ++ } else ++ vchiq_log_trace(vchiq_susp_log_level, ++ "%s %s count %d, state count %d", ++ __func__, entity, *entity_uc, local_uc); ++ ++ ++ write_unlock_bh(&arm_state->susp_res_lock); ++ ++ /* Completion is in a done state when we're not suspended, so this won't ++ * block for the non-suspended case. */ ++ if (!try_wait_for_completion(&arm_state->vc_resume_complete)) { ++ vchiq_log_info(vchiq_susp_log_level, "%s %s wait for resume", ++ __func__, entity); ++ if (wait_for_completion_killable( ++ &arm_state->vc_resume_complete) != 0) { ++ vchiq_log_error(vchiq_susp_log_level, "%s %s wait for " ++ "resume interrupted", __func__, entity); ++ ret = VCHIQ_ERROR; ++ goto out; ++ } ++ vchiq_log_info(vchiq_susp_log_level, "%s %s resumed", __func__, ++ entity); ++ } ++ ++ if (ret == VCHIQ_SUCCESS) { ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ long ack_cnt = atomic_xchg(&arm_state->ka_use_ack_count, 0); ++ while (ack_cnt && (status == VCHIQ_SUCCESS)) { ++ /* Send the use notify to videocore */ ++ status = vchiq_send_remote_use_active(state); ++ if (status == VCHIQ_SUCCESS) ++ ack_cnt--; ++ else ++ atomic_add(ack_cnt, ++ &arm_state->ka_use_ack_count); ++ } ++ } ++ ++out: ++ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, ret); ++ return ret; ++} ++ ++VCHIQ_STATUS_T ++vchiq_release_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ VCHIQ_STATUS_T ret = VCHIQ_SUCCESS; ++ char entity[16]; ++ int *entity_uc; ++ int local_uc, local_entity_uc; ++ ++ if (!arm_state) ++ goto out; ++ ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ ++ if (service) { ++ sprintf(entity, "%c%c%c%c:%03d", ++ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), ++ service->client_id); ++ entity_uc = &service->service_use_count; ++ } else { ++ sprintf(entity, "PEER: "); ++ entity_uc = &arm_state->peer_use_count; ++ } ++ ++ write_lock_bh(&arm_state->susp_res_lock); ++ if (!arm_state->videocore_use_count || !(*entity_uc)) { ++ /* Don't use BUG_ON - don't allow user thread to crash kernel */ ++ WARN_ON(!arm_state->videocore_use_count); ++ WARN_ON(!(*entity_uc)); ++ ret = VCHIQ_ERROR; ++ goto unlock; ++ } ++ local_uc = --arm_state->videocore_use_count; ++ local_entity_uc = --(*entity_uc); ++ ++ if (!vchiq_videocore_wanted(state)) { ++ if (vchiq_platform_use_suspend_timer() && ++ !arm_state->resume_blocked) { ++ /* Only use the timer if we're not trying to force ++ * suspend (=> resume_blocked) */ ++ start_suspend_timer(arm_state); ++ } else { ++ vchiq_log_info(vchiq_susp_log_level, ++ "%s %s count %d, state count %d - suspending", ++ __func__, entity, *entity_uc, ++ arm_state->videocore_use_count); ++ vchiq_arm_vcsuspend(state); ++ } ++ } else ++ vchiq_log_trace(vchiq_susp_log_level, ++ "%s %s count %d, state count %d", ++ __func__, entity, *entity_uc, ++ arm_state->videocore_use_count); ++ ++unlock: ++ write_unlock_bh(&arm_state->susp_res_lock); ++ ++out: ++ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, ret); ++ return ret; ++} ++ ++void ++vchiq_on_remote_use(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ atomic_inc(&arm_state->ka_use_count); ++ complete(&arm_state->ka_evt); ++} ++ ++void ++vchiq_on_remote_release(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ atomic_inc(&arm_state->ka_release_count); ++ complete(&arm_state->ka_evt); ++} ++ ++VCHIQ_STATUS_T ++vchiq_use_service_internal(VCHIQ_SERVICE_T *service) ++{ ++ return vchiq_use_internal(service->state, service, USE_TYPE_SERVICE); ++} ++ ++VCHIQ_STATUS_T ++vchiq_release_service_internal(VCHIQ_SERVICE_T *service) ++{ ++ return vchiq_release_internal(service->state, service); ++} ++ ++VCHIQ_DEBUGFS_NODE_T * ++vchiq_instance_get_debugfs_node(VCHIQ_INSTANCE_T instance) ++{ ++ return &instance->debugfs_node; ++} ++ ++int ++vchiq_instance_get_use_count(VCHIQ_INSTANCE_T instance) ++{ ++ VCHIQ_SERVICE_T *service; ++ int use_count = 0, i; ++ i = 0; ++ while ((service = next_service_by_instance(instance->state, ++ instance, &i)) != NULL) { ++ use_count += service->service_use_count; ++ unlock_service(service); ++ } ++ return use_count; ++} ++ ++int ++vchiq_instance_get_pid(VCHIQ_INSTANCE_T instance) ++{ ++ return instance->pid; ++} ++ ++int ++vchiq_instance_get_trace(VCHIQ_INSTANCE_T instance) ++{ ++ return instance->trace; ++} ++ ++void ++vchiq_instance_set_trace(VCHIQ_INSTANCE_T instance, int trace) ++{ ++ VCHIQ_SERVICE_T *service; ++ int i; ++ i = 0; ++ while ((service = next_service_by_instance(instance->state, ++ instance, &i)) != NULL) { ++ service->trace = trace; ++ unlock_service(service); ++ } ++ instance->trace = (trace != 0); ++} ++ ++static void suspend_timer_callback(unsigned long context) ++{ ++ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *)context; ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ if (!arm_state) ++ goto out; ++ vchiq_log_info(vchiq_susp_log_level, ++ "%s - suspend timer expired - check suspend", __func__); ++ vchiq_check_suspend(state); ++out: ++ return; ++} ++ ++VCHIQ_STATUS_T ++vchiq_use_service_no_resume(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ VCHIQ_STATUS_T ret = VCHIQ_ERROR; ++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); ++ if (service) { ++ ret = vchiq_use_internal(service->state, service, ++ USE_TYPE_SERVICE_NO_RESUME); ++ unlock_service(service); ++ } ++ return ret; ++} ++ ++VCHIQ_STATUS_T ++vchiq_use_service(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ VCHIQ_STATUS_T ret = VCHIQ_ERROR; ++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); ++ if (service) { ++ ret = vchiq_use_internal(service->state, service, ++ USE_TYPE_SERVICE); ++ unlock_service(service); ++ } ++ return ret; ++} ++ ++VCHIQ_STATUS_T ++vchiq_release_service(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ VCHIQ_STATUS_T ret = VCHIQ_ERROR; ++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); ++ if (service) { ++ ret = vchiq_release_internal(service->state, service); ++ unlock_service(service); ++ } ++ return ret; ++} ++ ++void ++vchiq_dump_service_use_state(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ int i, j = 0; ++ /* Only dump 64 services */ ++ static const int local_max_services = 64; ++ /* If there's more than 64 services, only dump ones with ++ * non-zero counts */ ++ int only_nonzero = 0; ++ static const char *nz = "<-- preventing suspend"; ++ ++ enum vc_suspend_status vc_suspend_state; ++ enum vc_resume_status vc_resume_state; ++ int peer_count; ++ int vc_use_count; ++ int active_services; ++ struct service_data_struct { ++ int fourcc; ++ int clientid; ++ int use_count; ++ } service_data[local_max_services]; ++ ++ if (!arm_state) ++ return; ++ ++ read_lock_bh(&arm_state->susp_res_lock); ++ vc_suspend_state = arm_state->vc_suspend_state; ++ vc_resume_state = arm_state->vc_resume_state; ++ peer_count = arm_state->peer_use_count; ++ vc_use_count = arm_state->videocore_use_count; ++ active_services = state->unused_service; ++ if (active_services > local_max_services) ++ only_nonzero = 1; ++ ++ for (i = 0; (i < active_services) && (j < local_max_services); i++) { ++ VCHIQ_SERVICE_T *service_ptr = state->services[i]; ++ if (!service_ptr) ++ continue; ++ ++ if (only_nonzero && !service_ptr->service_use_count) ++ continue; ++ ++ if (service_ptr->srvstate != VCHIQ_SRVSTATE_FREE) { ++ service_data[j].fourcc = service_ptr->base.fourcc; ++ service_data[j].clientid = service_ptr->client_id; ++ service_data[j++].use_count = service_ptr-> ++ service_use_count; ++ } ++ } ++ ++ read_unlock_bh(&arm_state->susp_res_lock); ++ ++ vchiq_log_warning(vchiq_susp_log_level, ++ "-- Videcore suspend state: %s --", ++ suspend_state_names[vc_suspend_state + VC_SUSPEND_NUM_OFFSET]); ++ vchiq_log_warning(vchiq_susp_log_level, ++ "-- Videcore resume state: %s --", ++ resume_state_names[vc_resume_state + VC_RESUME_NUM_OFFSET]); ++ ++ if (only_nonzero) ++ vchiq_log_warning(vchiq_susp_log_level, "Too many active " ++ "services (%d). Only dumping up to first %d services " ++ "with non-zero use-count", active_services, ++ local_max_services); ++ ++ for (i = 0; i < j; i++) { ++ vchiq_log_warning(vchiq_susp_log_level, ++ "----- %c%c%c%c:%d service count %d %s", ++ VCHIQ_FOURCC_AS_4CHARS(service_data[i].fourcc), ++ service_data[i].clientid, ++ service_data[i].use_count, ++ service_data[i].use_count ? nz : ""); ++ } ++ vchiq_log_warning(vchiq_susp_log_level, ++ "----- VCHIQ use count count %d", peer_count); ++ vchiq_log_warning(vchiq_susp_log_level, ++ "--- Overall vchiq instance use count %d", vc_use_count); ++ ++ vchiq_dump_platform_use_state(state); ++} ++ ++VCHIQ_STATUS_T ++vchiq_check_service(VCHIQ_SERVICE_T *service) ++{ ++ VCHIQ_ARM_STATE_T *arm_state; ++ VCHIQ_STATUS_T ret = VCHIQ_ERROR; ++ ++ if (!service || !service->state) ++ goto out; ++ ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ ++ arm_state = vchiq_platform_get_arm_state(service->state); ++ ++ read_lock_bh(&arm_state->susp_res_lock); ++ if (service->service_use_count) ++ ret = VCHIQ_SUCCESS; ++ read_unlock_bh(&arm_state->susp_res_lock); ++ ++ if (ret == VCHIQ_ERROR) { ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s ERROR - %c%c%c%c:%d service count %d, " ++ "state count %d, videocore suspend state %s", __func__, ++ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), ++ service->client_id, service->service_use_count, ++ arm_state->videocore_use_count, ++ suspend_state_names[arm_state->vc_suspend_state + ++ VC_SUSPEND_NUM_OFFSET]); ++ vchiq_dump_service_use_state(service->state); ++ } ++out: ++ return ret; ++} ++ ++/* stub functions */ ++void vchiq_on_remote_use_active(VCHIQ_STATE_T *state) ++{ ++ (void)state; ++} ++ ++void vchiq_platform_conn_state_changed(VCHIQ_STATE_T *state, ++ VCHIQ_CONNSTATE_T oldstate, VCHIQ_CONNSTATE_T newstate) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ vchiq_log_info(vchiq_susp_log_level, "%d: %s->%s", state->id, ++ get_conn_state_name(oldstate), get_conn_state_name(newstate)); ++ if (state->conn_state == VCHIQ_CONNSTATE_CONNECTED) { ++ write_lock_bh(&arm_state->susp_res_lock); ++ if (!arm_state->first_connect) { ++ char threadname[10]; ++ arm_state->first_connect = 1; ++ write_unlock_bh(&arm_state->susp_res_lock); ++ snprintf(threadname, sizeof(threadname), "VCHIQka-%d", ++ state->id); ++ arm_state->ka_thread = kthread_create( ++ &vchiq_keepalive_thread_func, ++ (void *)state, ++ threadname); ++ if (arm_state->ka_thread == NULL) { ++ vchiq_log_error(vchiq_susp_log_level, ++ "vchiq: FATAL: couldn't create thread %s", ++ threadname); ++ } else { ++ wake_up_process(arm_state->ka_thread); ++ } ++ } else ++ write_unlock_bh(&arm_state->susp_res_lock); ++ } ++} ++ ++static int vchiq_probe(struct platform_device *pdev) ++{ ++ struct device_node *fw_node; ++ struct rpi_firmware *fw; ++ int err; ++ void *ptr_err; ++ ++ fw_node = of_parse_phandle(pdev->dev.of_node, "firmware", 0); ++/* Remove comment when booting without Device Tree is no longer supported ++ if (!fw_node) { ++ dev_err(&pdev->dev, "Missing firmware node\n"); ++ return -ENOENT; ++ } ++*/ ++ fw = rpi_firmware_get(fw_node); ++ if (!fw) ++ return -EPROBE_DEFER; ++ ++ platform_set_drvdata(pdev, fw); ++ ++ /* create debugfs entries */ ++ err = vchiq_debugfs_init(); ++ if (err != 0) ++ goto failed_debugfs_init; ++ ++ err = alloc_chrdev_region(&vchiq_devid, VCHIQ_MINOR, 1, DEVICE_NAME); ++ if (err != 0) { ++ vchiq_log_error(vchiq_arm_log_level, ++ "Unable to allocate device number"); ++ goto failed_alloc_chrdev; ++ } ++ cdev_init(&vchiq_cdev, &vchiq_fops); ++ vchiq_cdev.owner = THIS_MODULE; ++ err = cdev_add(&vchiq_cdev, vchiq_devid, 1); ++ if (err != 0) { ++ vchiq_log_error(vchiq_arm_log_level, ++ "Unable to register device"); ++ goto failed_cdev_add; ++ } ++ ++ /* create sysfs entries */ ++ vchiq_class = class_create(THIS_MODULE, DEVICE_NAME); ++ ptr_err = vchiq_class; ++ if (IS_ERR(ptr_err)) ++ goto failed_class_create; ++ ++ vchiq_dev = device_create(vchiq_class, NULL, ++ vchiq_devid, NULL, "vchiq"); ++ ptr_err = vchiq_dev; ++ if (IS_ERR(ptr_err)) ++ goto failed_device_create; ++ ++ err = vchiq_platform_init(pdev, &g_state); ++ if (err != 0) ++ goto failed_platform_init; ++ ++ vchiq_log_info(vchiq_arm_log_level, ++ "vchiq: initialised - version %d (min %d), device %d.%d", ++ VCHIQ_VERSION, VCHIQ_VERSION_MIN, ++ MAJOR(vchiq_devid), MINOR(vchiq_devid)); ++ ++ return 0; ++ ++failed_platform_init: ++ device_destroy(vchiq_class, vchiq_devid); ++failed_device_create: ++ class_destroy(vchiq_class); ++failed_class_create: ++ cdev_del(&vchiq_cdev); ++ err = PTR_ERR(ptr_err); ++failed_cdev_add: ++ unregister_chrdev_region(vchiq_devid, 1); ++failed_alloc_chrdev: ++ vchiq_debugfs_deinit(); ++failed_debugfs_init: ++ vchiq_log_warning(vchiq_arm_log_level, "could not load vchiq"); ++ return err; ++} ++ ++static int vchiq_remove(struct platform_device *pdev) ++{ ++ device_destroy(vchiq_class, vchiq_devid); ++ class_destroy(vchiq_class); ++ cdev_del(&vchiq_cdev); ++ unregister_chrdev_region(vchiq_devid, 1); ++ ++ return 0; ++} ++ ++static const struct of_device_id vchiq_of_match[] = { ++ { .compatible = "brcm,bcm2835-vchiq", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, vchiq_of_match); ++ ++static struct platform_driver vchiq_driver = { ++ .driver = { ++ .name = "bcm2835_vchiq", ++ .owner = THIS_MODULE, ++ .of_match_table = vchiq_of_match, ++ }, ++ .probe = vchiq_probe, ++ .remove = vchiq_remove, ++}; ++module_platform_driver(vchiq_driver); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Broadcom Corporation"); +diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h +--- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h 2015-11-29 09:42:38.071221476 +0100 +@@ -0,0 +1,220 @@ ++/** ++ * Copyright (c) 2014 Raspberry Pi (Trading) Ltd. All rights reserved. ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHIQ_ARM_H ++#define VCHIQ_ARM_H ++ ++#include ++#include ++#include ++#include ++#include "vchiq_core.h" ++#include "vchiq_debugfs.h" ++ ++ ++enum vc_suspend_status { ++ VC_SUSPEND_FORCE_CANCELED = -3, /* Force suspend canceled, too busy */ ++ VC_SUSPEND_REJECTED = -2, /* Videocore rejected suspend request */ ++ VC_SUSPEND_FAILED = -1, /* Videocore suspend failed */ ++ VC_SUSPEND_IDLE = 0, /* VC active, no suspend actions */ ++ VC_SUSPEND_REQUESTED, /* User has requested suspend */ ++ VC_SUSPEND_IN_PROGRESS, /* Slot handler has recvd suspend request */ ++ VC_SUSPEND_SUSPENDED /* Videocore suspend succeeded */ ++}; ++ ++enum vc_resume_status { ++ VC_RESUME_FAILED = -1, /* Videocore resume failed */ ++ VC_RESUME_IDLE = 0, /* VC suspended, no resume actions */ ++ VC_RESUME_REQUESTED, /* User has requested resume */ ++ VC_RESUME_IN_PROGRESS, /* Slot handler has received resume request */ ++ VC_RESUME_RESUMED /* Videocore resumed successfully (active) */ ++}; ++ ++ ++enum USE_TYPE_E { ++ USE_TYPE_SERVICE, ++ USE_TYPE_SERVICE_NO_RESUME, ++ USE_TYPE_VCHIQ ++}; ++ ++ ++ ++typedef struct vchiq_arm_state_struct { ++ /* Keepalive-related data */ ++ struct task_struct *ka_thread; ++ struct completion ka_evt; ++ atomic_t ka_use_count; ++ atomic_t ka_use_ack_count; ++ atomic_t ka_release_count; ++ ++ struct completion vc_suspend_complete; ++ struct completion vc_resume_complete; ++ ++ rwlock_t susp_res_lock; ++ enum vc_suspend_status vc_suspend_state; ++ enum vc_resume_status vc_resume_state; ++ ++ unsigned int wake_address; ++ ++ struct timer_list suspend_timer; ++ int suspend_timer_timeout; ++ int suspend_timer_running; ++ ++ /* Global use count for videocore. ++ ** This is equal to the sum of the use counts for all services. When ++ ** this hits zero the videocore suspend procedure will be initiated. ++ */ ++ int videocore_use_count; ++ ++ /* Use count to track requests from videocore peer. ++ ** This use count is not associated with a service, so needs to be ++ ** tracked separately with the state. ++ */ ++ int peer_use_count; ++ ++ /* Flag to indicate whether resume is blocked. This happens when the ++ ** ARM is suspending ++ */ ++ struct completion resume_blocker; ++ int resume_blocked; ++ struct completion blocked_blocker; ++ int blocked_count; ++ ++ int autosuspend_override; ++ ++ /* Flag to indicate that the first vchiq connect has made it through. ++ ** This means that both sides should be fully ready, and we should ++ ** be able to suspend after this point. ++ */ ++ int first_connect; ++ ++ unsigned long long suspend_start_time; ++ unsigned long long sleep_start_time; ++ unsigned long long resume_start_time; ++ unsigned long long last_wake_time; ++ ++} VCHIQ_ARM_STATE_T; ++ ++extern int vchiq_arm_log_level; ++extern int vchiq_susp_log_level; ++ ++int vchiq_platform_init(struct platform_device *pdev, VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATE_T * ++vchiq_get_state(void); ++ ++extern VCHIQ_STATUS_T ++vchiq_arm_vcsuspend(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATUS_T ++vchiq_arm_force_suspend(VCHIQ_STATE_T *state); ++ ++extern int ++vchiq_arm_allow_resume(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATUS_T ++vchiq_arm_vcresume(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATUS_T ++vchiq_arm_init_state(VCHIQ_STATE_T *state, VCHIQ_ARM_STATE_T *arm_state); ++ ++extern int ++vchiq_check_resume(VCHIQ_STATE_T *state); ++ ++extern void ++vchiq_check_suspend(VCHIQ_STATE_T *state); ++ VCHIQ_STATUS_T ++vchiq_use_service(VCHIQ_SERVICE_HANDLE_T handle); ++ ++extern VCHIQ_STATUS_T ++vchiq_release_service(VCHIQ_SERVICE_HANDLE_T handle); ++ ++extern VCHIQ_STATUS_T ++vchiq_check_service(VCHIQ_SERVICE_T *service); ++ ++extern VCHIQ_STATUS_T ++vchiq_platform_suspend(VCHIQ_STATE_T *state); ++ ++extern int ++vchiq_platform_videocore_wanted(VCHIQ_STATE_T *state); ++ ++extern int ++vchiq_platform_use_suspend_timer(void); ++ ++extern void ++vchiq_dump_platform_use_state(VCHIQ_STATE_T *state); ++ ++extern void ++vchiq_dump_service_use_state(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_ARM_STATE_T* ++vchiq_platform_get_arm_state(VCHIQ_STATE_T *state); ++ ++extern int ++vchiq_videocore_wanted(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATUS_T ++vchiq_use_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, ++ enum USE_TYPE_E use_type); ++extern VCHIQ_STATUS_T ++vchiq_release_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service); ++ ++extern VCHIQ_DEBUGFS_NODE_T * ++vchiq_instance_get_debugfs_node(VCHIQ_INSTANCE_T instance); ++ ++extern int ++vchiq_instance_get_use_count(VCHIQ_INSTANCE_T instance); ++ ++extern int ++vchiq_instance_get_pid(VCHIQ_INSTANCE_T instance); ++ ++extern int ++vchiq_instance_get_trace(VCHIQ_INSTANCE_T instance); ++ ++extern void ++vchiq_instance_set_trace(VCHIQ_INSTANCE_T instance, int trace); ++ ++extern void ++set_suspend_state(VCHIQ_ARM_STATE_T *arm_state, ++ enum vc_suspend_status new_state); ++ ++extern void ++set_resume_state(VCHIQ_ARM_STATE_T *arm_state, ++ enum vc_resume_status new_state); ++ ++extern void ++start_suspend_timer(VCHIQ_ARM_STATE_T *arm_state); ++ ++ ++#endif /* VCHIQ_ARM_H */ +diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_build_info.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_build_info.h +--- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_build_info.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_build_info.h 2015-11-29 09:42:38.071221476 +0100 +@@ -0,0 +1,37 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++const char *vchiq_get_build_hostname(void); ++const char *vchiq_get_build_version(void); ++const char *vchiq_get_build_time(void); ++const char *vchiq_get_build_date(void); +diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h +--- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h 2015-11-29 09:42:38.071221476 +0100 +@@ -0,0 +1,69 @@ ++/** ++ * Copyright (c) 2010-2014 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHIQ_CFG_H ++#define VCHIQ_CFG_H ++ ++#define VCHIQ_MAGIC VCHIQ_MAKE_FOURCC('V', 'C', 'H', 'I') ++/* The version of VCHIQ - change with any non-trivial change */ ++#define VCHIQ_VERSION 8 ++/* The minimum compatible version - update to match VCHIQ_VERSION with any ++** incompatible change */ ++#define VCHIQ_VERSION_MIN 3 ++ ++/* The version that introduced the VCHIQ_IOC_LIB_VERSION ioctl */ ++#define VCHIQ_VERSION_LIB_VERSION 7 ++ ++/* The version that introduced the VCHIQ_IOC_CLOSE_DELIVERED ioctl */ ++#define VCHIQ_VERSION_CLOSE_DELIVERED 7 ++ ++/* The version that made it safe to use SYNCHRONOUS mode */ ++#define VCHIQ_VERSION_SYNCHRONOUS_MODE 8 ++ ++#define VCHIQ_MAX_STATES 1 ++#define VCHIQ_MAX_SERVICES 4096 ++#define VCHIQ_MAX_SLOTS 128 ++#define VCHIQ_MAX_SLOTS_PER_SIDE 64 ++ ++#define VCHIQ_NUM_CURRENT_BULKS 32 ++#define VCHIQ_NUM_SERVICE_BULKS 4 ++ ++#ifndef VCHIQ_ENABLE_DEBUG ++#define VCHIQ_ENABLE_DEBUG 1 ++#endif ++ ++#ifndef VCHIQ_ENABLE_STATS ++#define VCHIQ_ENABLE_STATS 1 ++#endif ++ ++#endif /* VCHIQ_CFG_H */ +diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.c +--- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.c 2015-11-29 09:42:38.071221476 +0100 +@@ -0,0 +1,120 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include "vchiq_connected.h" ++#include "vchiq_core.h" ++#include "vchiq_killable.h" ++#include ++#include ++ ++#define MAX_CALLBACKS 10 ++ ++static int g_connected; ++static int g_num_deferred_callbacks; ++static VCHIQ_CONNECTED_CALLBACK_T g_deferred_callback[MAX_CALLBACKS]; ++static int g_once_init; ++static struct mutex g_connected_mutex; ++ ++/**************************************************************************** ++* ++* Function to initialize our lock. ++* ++***************************************************************************/ ++ ++static void connected_init(void) ++{ ++ if (!g_once_init) { ++ mutex_init(&g_connected_mutex); ++ g_once_init = 1; ++ } ++} ++ ++/**************************************************************************** ++* ++* This function is used to defer initialization until the vchiq stack is ++* initialized. If the stack is already initialized, then the callback will ++* be made immediately, otherwise it will be deferred until ++* vchiq_call_connected_callbacks is called. ++* ++***************************************************************************/ ++ ++void vchiq_add_connected_callback(VCHIQ_CONNECTED_CALLBACK_T callback) ++{ ++ connected_init(); ++ ++ if (mutex_lock_interruptible(&g_connected_mutex) != 0) ++ return; ++ ++ if (g_connected) ++ /* We're already connected. Call the callback immediately. */ ++ ++ callback(); ++ else { ++ if (g_num_deferred_callbacks >= MAX_CALLBACKS) ++ vchiq_log_error(vchiq_core_log_level, ++ "There already %d callback registered - " ++ "please increase MAX_CALLBACKS", ++ g_num_deferred_callbacks); ++ else { ++ g_deferred_callback[g_num_deferred_callbacks] = ++ callback; ++ g_num_deferred_callbacks++; ++ } ++ } ++ mutex_unlock(&g_connected_mutex); ++} ++ ++/**************************************************************************** ++* ++* This function is called by the vchiq stack once it has been connected to ++* the videocore and clients can start to use the stack. ++* ++***************************************************************************/ ++ ++void vchiq_call_connected_callbacks(void) ++{ ++ int i; ++ ++ connected_init(); ++ ++ if (mutex_lock_interruptible(&g_connected_mutex) != 0) ++ return; ++ ++ for (i = 0; i < g_num_deferred_callbacks; i++) ++ g_deferred_callback[i](); ++ ++ g_num_deferred_callbacks = 0; ++ g_connected = 1; ++ mutex_unlock(&g_connected_mutex); ++} ++EXPORT_SYMBOL(vchiq_add_connected_callback); +diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.h +--- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.h 2015-11-29 09:42:38.075221210 +0100 +@@ -0,0 +1,50 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHIQ_CONNECTED_H ++#define VCHIQ_CONNECTED_H ++ ++/* ---- Include Files ----------------------------------------------------- */ ++ ++/* ---- Constants and Types ---------------------------------------------- */ ++ ++typedef void (*VCHIQ_CONNECTED_CALLBACK_T)(void); ++ ++/* ---- Variable Externs ------------------------------------------------- */ ++ ++/* ---- Function Prototypes ---------------------------------------------- */ ++ ++void vchiq_add_connected_callback(VCHIQ_CONNECTED_CALLBACK_T callback); ++void vchiq_call_connected_callbacks(void); ++ ++#endif /* VCHIQ_CONNECTED_H */ +diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c +--- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c 2015-11-29 09:42:38.075221210 +0100 +@@ -0,0 +1,3934 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include "vchiq_core.h" ++#include "vchiq_killable.h" ++ ++#define VCHIQ_SLOT_HANDLER_STACK 8192 ++ ++#define HANDLE_STATE_SHIFT 12 ++ ++#define SLOT_INFO_FROM_INDEX(state, index) (state->slot_info + (index)) ++#define SLOT_DATA_FROM_INDEX(state, index) (state->slot_data + (index)) ++#define SLOT_INDEX_FROM_DATA(state, data) \ ++ (((unsigned int)((char *)data - (char *)state->slot_data)) / \ ++ VCHIQ_SLOT_SIZE) ++#define SLOT_INDEX_FROM_INFO(state, info) \ ++ ((unsigned int)(info - state->slot_info)) ++#define SLOT_QUEUE_INDEX_FROM_POS(pos) \ ++ ((int)((unsigned int)(pos) / VCHIQ_SLOT_SIZE)) ++ ++#define BULK_INDEX(x) (x & (VCHIQ_NUM_SERVICE_BULKS - 1)) ++ ++#define SRVTRACE_LEVEL(srv) \ ++ (((srv) && (srv)->trace) ? VCHIQ_LOG_TRACE : vchiq_core_msg_log_level) ++#define SRVTRACE_ENABLED(srv, lev) \ ++ (((srv) && (srv)->trace) || (vchiq_core_msg_log_level >= (lev))) ++ ++struct vchiq_open_payload { ++ int fourcc; ++ int client_id; ++ short version; ++ short version_min; ++}; ++ ++struct vchiq_openack_payload { ++ short version; ++}; ++ ++enum ++{ ++ QMFLAGS_IS_BLOCKING = (1 << 0), ++ QMFLAGS_NO_MUTEX_LOCK = (1 << 1), ++ QMFLAGS_NO_MUTEX_UNLOCK = (1 << 2) ++}; ++ ++/* we require this for consistency between endpoints */ ++vchiq_static_assert(sizeof(VCHIQ_HEADER_T) == 8); ++vchiq_static_assert(IS_POW2(sizeof(VCHIQ_HEADER_T))); ++vchiq_static_assert(IS_POW2(VCHIQ_NUM_CURRENT_BULKS)); ++vchiq_static_assert(IS_POW2(VCHIQ_NUM_SERVICE_BULKS)); ++vchiq_static_assert(IS_POW2(VCHIQ_MAX_SERVICES)); ++vchiq_static_assert(VCHIQ_VERSION >= VCHIQ_VERSION_MIN); ++ ++/* Run time control of log level, based on KERN_XXX level. */ ++int vchiq_core_log_level = VCHIQ_LOG_DEFAULT; ++int vchiq_core_msg_log_level = VCHIQ_LOG_DEFAULT; ++int vchiq_sync_log_level = VCHIQ_LOG_DEFAULT; ++ ++static atomic_t pause_bulks_count = ATOMIC_INIT(0); ++ ++static DEFINE_SPINLOCK(service_spinlock); ++DEFINE_SPINLOCK(bulk_waiter_spinlock); ++DEFINE_SPINLOCK(quota_spinlock); ++ ++VCHIQ_STATE_T *vchiq_states[VCHIQ_MAX_STATES]; ++static unsigned int handle_seq; ++ ++static const char *const srvstate_names[] = { ++ "FREE", ++ "HIDDEN", ++ "LISTENING", ++ "OPENING", ++ "OPEN", ++ "OPENSYNC", ++ "CLOSESENT", ++ "CLOSERECVD", ++ "CLOSEWAIT", ++ "CLOSED" ++}; ++ ++static const char *const reason_names[] = { ++ "SERVICE_OPENED", ++ "SERVICE_CLOSED", ++ "MESSAGE_AVAILABLE", ++ "BULK_TRANSMIT_DONE", ++ "BULK_RECEIVE_DONE", ++ "BULK_TRANSMIT_ABORTED", ++ "BULK_RECEIVE_ABORTED" ++}; ++ ++static const char *const conn_state_names[] = { ++ "DISCONNECTED", ++ "CONNECTING", ++ "CONNECTED", ++ "PAUSING", ++ "PAUSE_SENT", ++ "PAUSED", ++ "RESUMING", ++ "PAUSE_TIMEOUT", ++ "RESUME_TIMEOUT" ++}; ++ ++ ++static void ++release_message_sync(VCHIQ_STATE_T *state, VCHIQ_HEADER_T *header); ++ ++static const char *msg_type_str(unsigned int msg_type) ++{ ++ switch (msg_type) { ++ case VCHIQ_MSG_PADDING: return "PADDING"; ++ case VCHIQ_MSG_CONNECT: return "CONNECT"; ++ case VCHIQ_MSG_OPEN: return "OPEN"; ++ case VCHIQ_MSG_OPENACK: return "OPENACK"; ++ case VCHIQ_MSG_CLOSE: return "CLOSE"; ++ case VCHIQ_MSG_DATA: return "DATA"; ++ case VCHIQ_MSG_BULK_RX: return "BULK_RX"; ++ case VCHIQ_MSG_BULK_TX: return "BULK_TX"; ++ case VCHIQ_MSG_BULK_RX_DONE: return "BULK_RX_DONE"; ++ case VCHIQ_MSG_BULK_TX_DONE: return "BULK_TX_DONE"; ++ case VCHIQ_MSG_PAUSE: return "PAUSE"; ++ case VCHIQ_MSG_RESUME: return "RESUME"; ++ case VCHIQ_MSG_REMOTE_USE: return "REMOTE_USE"; ++ case VCHIQ_MSG_REMOTE_RELEASE: return "REMOTE_RELEASE"; ++ case VCHIQ_MSG_REMOTE_USE_ACTIVE: return "REMOTE_USE_ACTIVE"; ++ } ++ return "???"; ++} ++ ++static inline void ++vchiq_set_service_state(VCHIQ_SERVICE_T *service, int newstate) ++{ ++ vchiq_log_info(vchiq_core_log_level, "%d: srv:%d %s->%s", ++ service->state->id, service->localport, ++ srvstate_names[service->srvstate], ++ srvstate_names[newstate]); ++ service->srvstate = newstate; ++} ++ ++VCHIQ_SERVICE_T * ++find_service_by_handle(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ VCHIQ_SERVICE_T *service; ++ ++ spin_lock(&service_spinlock); ++ service = handle_to_service(handle); ++ if (service && (service->srvstate != VCHIQ_SRVSTATE_FREE) && ++ (service->handle == handle)) { ++ BUG_ON(service->ref_count == 0); ++ service->ref_count++; ++ } else ++ service = NULL; ++ spin_unlock(&service_spinlock); ++ ++ if (!service) ++ vchiq_log_info(vchiq_core_log_level, ++ "Invalid service handle 0x%x", handle); ++ ++ return service; ++} ++ ++VCHIQ_SERVICE_T * ++find_service_by_port(VCHIQ_STATE_T *state, int localport) ++{ ++ VCHIQ_SERVICE_T *service = NULL; ++ if ((unsigned int)localport <= VCHIQ_PORT_MAX) { ++ spin_lock(&service_spinlock); ++ service = state->services[localport]; ++ if (service && (service->srvstate != VCHIQ_SRVSTATE_FREE)) { ++ BUG_ON(service->ref_count == 0); ++ service->ref_count++; ++ } else ++ service = NULL; ++ spin_unlock(&service_spinlock); ++ } ++ ++ if (!service) ++ vchiq_log_info(vchiq_core_log_level, ++ "Invalid port %d", localport); ++ ++ return service; ++} ++ ++VCHIQ_SERVICE_T * ++find_service_for_instance(VCHIQ_INSTANCE_T instance, ++ VCHIQ_SERVICE_HANDLE_T handle) { ++ VCHIQ_SERVICE_T *service; ++ ++ spin_lock(&service_spinlock); ++ service = handle_to_service(handle); ++ if (service && (service->srvstate != VCHIQ_SRVSTATE_FREE) && ++ (service->handle == handle) && ++ (service->instance == instance)) { ++ BUG_ON(service->ref_count == 0); ++ service->ref_count++; ++ } else ++ service = NULL; ++ spin_unlock(&service_spinlock); ++ ++ if (!service) ++ vchiq_log_info(vchiq_core_log_level, ++ "Invalid service handle 0x%x", handle); ++ ++ return service; ++} ++ ++VCHIQ_SERVICE_T * ++find_closed_service_for_instance(VCHIQ_INSTANCE_T instance, ++ VCHIQ_SERVICE_HANDLE_T handle) { ++ VCHIQ_SERVICE_T *service; ++ ++ spin_lock(&service_spinlock); ++ service = handle_to_service(handle); ++ if (service && ++ ((service->srvstate == VCHIQ_SRVSTATE_FREE) || ++ (service->srvstate == VCHIQ_SRVSTATE_CLOSED)) && ++ (service->handle == handle) && ++ (service->instance == instance)) { ++ BUG_ON(service->ref_count == 0); ++ service->ref_count++; ++ } else ++ service = NULL; ++ spin_unlock(&service_spinlock); ++ ++ if (!service) ++ vchiq_log_info(vchiq_core_log_level, ++ "Invalid service handle 0x%x", handle); ++ ++ return service; ++} ++ ++VCHIQ_SERVICE_T * ++next_service_by_instance(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance, ++ int *pidx) ++{ ++ VCHIQ_SERVICE_T *service = NULL; ++ int idx = *pidx; ++ ++ spin_lock(&service_spinlock); ++ while (idx < state->unused_service) { ++ VCHIQ_SERVICE_T *srv = state->services[idx++]; ++ if (srv && (srv->srvstate != VCHIQ_SRVSTATE_FREE) && ++ (srv->instance == instance)) { ++ service = srv; ++ BUG_ON(service->ref_count == 0); ++ service->ref_count++; ++ break; ++ } ++ } ++ spin_unlock(&service_spinlock); ++ ++ *pidx = idx; ++ ++ return service; ++} ++ ++void ++lock_service(VCHIQ_SERVICE_T *service) ++{ ++ spin_lock(&service_spinlock); ++ BUG_ON(!service || (service->ref_count == 0)); ++ if (service) ++ service->ref_count++; ++ spin_unlock(&service_spinlock); ++} ++ ++void ++unlock_service(VCHIQ_SERVICE_T *service) ++{ ++ VCHIQ_STATE_T *state = service->state; ++ spin_lock(&service_spinlock); ++ BUG_ON(!service || (service->ref_count == 0)); ++ if (service && service->ref_count) { ++ service->ref_count--; ++ if (!service->ref_count) { ++ BUG_ON(service->srvstate != VCHIQ_SRVSTATE_FREE); ++ state->services[service->localport] = NULL; ++ } else ++ service = NULL; ++ } ++ spin_unlock(&service_spinlock); ++ ++ if (service && service->userdata_term) ++ service->userdata_term(service->base.userdata); ++ ++ kfree(service); ++} ++ ++int ++vchiq_get_client_id(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); ++ int id; ++ ++ id = service ? service->client_id : 0; ++ if (service) ++ unlock_service(service); ++ ++ return id; ++} ++ ++void * ++vchiq_get_service_userdata(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ VCHIQ_SERVICE_T *service = handle_to_service(handle); ++ ++ return service ? service->base.userdata : NULL; ++} ++ ++int ++vchiq_get_service_fourcc(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ VCHIQ_SERVICE_T *service = handle_to_service(handle); ++ ++ return service ? service->base.fourcc : 0; ++} ++ ++static void ++mark_service_closing_internal(VCHIQ_SERVICE_T *service, int sh_thread) ++{ ++ VCHIQ_STATE_T *state = service->state; ++ VCHIQ_SERVICE_QUOTA_T *service_quota; ++ ++ service->closing = 1; ++ ++ /* Synchronise with other threads. */ ++ mutex_lock(&state->recycle_mutex); ++ mutex_unlock(&state->recycle_mutex); ++ if (!sh_thread || (state->conn_state != VCHIQ_CONNSTATE_PAUSE_SENT)) { ++ /* If we're pausing then the slot_mutex is held until resume ++ * by the slot handler. Therefore don't try to acquire this ++ * mutex if we're the slot handler and in the pause sent state. ++ * We don't need to in this case anyway. */ ++ mutex_lock(&state->slot_mutex); ++ mutex_unlock(&state->slot_mutex); ++ } ++ ++ /* Unblock any sending thread. */ ++ service_quota = &state->service_quotas[service->localport]; ++ up(&service_quota->quota_event); ++} ++ ++static void ++mark_service_closing(VCHIQ_SERVICE_T *service) ++{ ++ mark_service_closing_internal(service, 0); ++} ++ ++static inline VCHIQ_STATUS_T ++make_service_callback(VCHIQ_SERVICE_T *service, VCHIQ_REASON_T reason, ++ VCHIQ_HEADER_T *header, void *bulk_userdata) ++{ ++ VCHIQ_STATUS_T status; ++ vchiq_log_trace(vchiq_core_log_level, "%d: callback:%d (%s, %x, %x)", ++ service->state->id, service->localport, reason_names[reason], ++ (unsigned int)header, (unsigned int)bulk_userdata); ++ status = service->base.callback(reason, header, service->handle, ++ bulk_userdata); ++ if (status == VCHIQ_ERROR) { ++ vchiq_log_warning(vchiq_core_log_level, ++ "%d: ignoring ERROR from callback to service %x", ++ service->state->id, service->handle); ++ status = VCHIQ_SUCCESS; ++ } ++ return status; ++} ++ ++inline void ++vchiq_set_conn_state(VCHIQ_STATE_T *state, VCHIQ_CONNSTATE_T newstate) ++{ ++ VCHIQ_CONNSTATE_T oldstate = state->conn_state; ++ vchiq_log_info(vchiq_core_log_level, "%d: %s->%s", state->id, ++ conn_state_names[oldstate], ++ conn_state_names[newstate]); ++ state->conn_state = newstate; ++ vchiq_platform_conn_state_changed(state, oldstate, newstate); ++} ++ ++static inline void ++remote_event_create(REMOTE_EVENT_T *event) ++{ ++ event->armed = 0; ++ /* Don't clear the 'fired' flag because it may already have been set ++ ** by the other side. */ ++ sema_init(event->event, 0); ++} ++ ++static inline void ++remote_event_destroy(REMOTE_EVENT_T *event) ++{ ++ (void)event; ++} ++ ++static inline int ++remote_event_wait(REMOTE_EVENT_T *event) ++{ ++ if (!event->fired) { ++ event->armed = 1; ++ dsb(); ++ if (!event->fired) { ++ if (down_interruptible(event->event) != 0) { ++ event->armed = 0; ++ return 0; ++ } ++ } ++ event->armed = 0; ++ wmb(); ++ } ++ ++ event->fired = 0; ++ return 1; ++} ++ ++static inline void ++remote_event_signal_local(REMOTE_EVENT_T *event) ++{ ++ event->armed = 0; ++ up(event->event); ++} ++ ++static inline void ++remote_event_poll(REMOTE_EVENT_T *event) ++{ ++ if (event->fired && event->armed) ++ remote_event_signal_local(event); ++} ++ ++void ++remote_event_pollall(VCHIQ_STATE_T *state) ++{ ++ remote_event_poll(&state->local->sync_trigger); ++ remote_event_poll(&state->local->sync_release); ++ remote_event_poll(&state->local->trigger); ++ remote_event_poll(&state->local->recycle); ++} ++ ++/* Round up message sizes so that any space at the end of a slot is always big ++** enough for a header. This relies on header size being a power of two, which ++** has been verified earlier by a static assertion. */ ++ ++static inline unsigned int ++calc_stride(unsigned int size) ++{ ++ /* Allow room for the header */ ++ size += sizeof(VCHIQ_HEADER_T); ++ ++ /* Round up */ ++ return (size + sizeof(VCHIQ_HEADER_T) - 1) & ~(sizeof(VCHIQ_HEADER_T) ++ - 1); ++} ++ ++/* Called by the slot handler thread */ ++static VCHIQ_SERVICE_T * ++get_listening_service(VCHIQ_STATE_T *state, int fourcc) ++{ ++ int i; ++ ++ WARN_ON(fourcc == VCHIQ_FOURCC_INVALID); ++ ++ for (i = 0; i < state->unused_service; i++) { ++ VCHIQ_SERVICE_T *service = state->services[i]; ++ if (service && ++ (service->public_fourcc == fourcc) && ++ ((service->srvstate == VCHIQ_SRVSTATE_LISTENING) || ++ ((service->srvstate == VCHIQ_SRVSTATE_OPEN) && ++ (service->remoteport == VCHIQ_PORT_FREE)))) { ++ lock_service(service); ++ return service; ++ } ++ } ++ ++ return NULL; ++} ++ ++/* Called by the slot handler thread */ ++static VCHIQ_SERVICE_T * ++get_connected_service(VCHIQ_STATE_T *state, unsigned int port) ++{ ++ int i; ++ for (i = 0; i < state->unused_service; i++) { ++ VCHIQ_SERVICE_T *service = state->services[i]; ++ if (service && (service->srvstate == VCHIQ_SRVSTATE_OPEN) ++ && (service->remoteport == port)) { ++ lock_service(service); ++ return service; ++ } ++ } ++ return NULL; ++} ++ ++inline void ++request_poll(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, int poll_type) ++{ ++ uint32_t value; ++ ++ if (service) { ++ do { ++ value = atomic_read(&service->poll_flags); ++ } while (atomic_cmpxchg(&service->poll_flags, value, ++ value | (1 << poll_type)) != value); ++ ++ do { ++ value = atomic_read(&state->poll_services[ ++ service->localport>>5]); ++ } while (atomic_cmpxchg( ++ &state->poll_services[service->localport>>5], ++ value, value | (1 << (service->localport & 0x1f))) ++ != value); ++ } ++ ++ state->poll_needed = 1; ++ wmb(); ++ ++ /* ... and ensure the slot handler runs. */ ++ remote_event_signal_local(&state->local->trigger); ++} ++ ++/* Called from queue_message, by the slot handler and application threads, ++** with slot_mutex held */ ++static VCHIQ_HEADER_T * ++reserve_space(VCHIQ_STATE_T *state, int space, int is_blocking) ++{ ++ VCHIQ_SHARED_STATE_T *local = state->local; ++ int tx_pos = state->local_tx_pos; ++ int slot_space = VCHIQ_SLOT_SIZE - (tx_pos & VCHIQ_SLOT_MASK); ++ ++ if (space > slot_space) { ++ VCHIQ_HEADER_T *header; ++ /* Fill the remaining space with padding */ ++ WARN_ON(state->tx_data == NULL); ++ header = (VCHIQ_HEADER_T *) ++ (state->tx_data + (tx_pos & VCHIQ_SLOT_MASK)); ++ header->msgid = VCHIQ_MSGID_PADDING; ++ header->size = slot_space - sizeof(VCHIQ_HEADER_T); ++ ++ tx_pos += slot_space; ++ } ++ ++ /* If necessary, get the next slot. */ ++ if ((tx_pos & VCHIQ_SLOT_MASK) == 0) { ++ int slot_index; ++ ++ /* If there is no free slot... */ ++ ++ if (down_trylock(&state->slot_available_event) != 0) { ++ /* ...wait for one. */ ++ ++ VCHIQ_STATS_INC(state, slot_stalls); ++ ++ /* But first, flush through the last slot. */ ++ state->local_tx_pos = tx_pos; ++ local->tx_pos = tx_pos; ++ remote_event_signal(&state->remote->trigger); ++ ++ if (!is_blocking || ++ (down_interruptible( ++ &state->slot_available_event) != 0)) ++ return NULL; /* No space available */ ++ } ++ ++ BUG_ON(tx_pos == ++ (state->slot_queue_available * VCHIQ_SLOT_SIZE)); ++ ++ slot_index = local->slot_queue[ ++ SLOT_QUEUE_INDEX_FROM_POS(tx_pos) & ++ VCHIQ_SLOT_QUEUE_MASK]; ++ state->tx_data = ++ (char *)SLOT_DATA_FROM_INDEX(state, slot_index); ++ } ++ ++ state->local_tx_pos = tx_pos + space; ++ ++ return (VCHIQ_HEADER_T *)(state->tx_data + (tx_pos & VCHIQ_SLOT_MASK)); ++} ++ ++/* Called by the recycle thread. */ ++static void ++process_free_queue(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_SHARED_STATE_T *local = state->local; ++ BITSET_T service_found[BITSET_SIZE(VCHIQ_MAX_SERVICES)]; ++ int slot_queue_available; ++ ++ /* Use a read memory barrier to ensure that any state that may have ++ ** been modified by another thread is not masked by stale prefetched ++ ** values. */ ++ rmb(); ++ ++ /* Find slots which have been freed by the other side, and return them ++ ** to the available queue. */ ++ slot_queue_available = state->slot_queue_available; ++ ++ while (slot_queue_available != local->slot_queue_recycle) { ++ unsigned int pos; ++ int slot_index = local->slot_queue[slot_queue_available++ & ++ VCHIQ_SLOT_QUEUE_MASK]; ++ char *data = (char *)SLOT_DATA_FROM_INDEX(state, slot_index); ++ int data_found = 0; ++ ++ vchiq_log_trace(vchiq_core_log_level, "%d: pfq %d=%x %x %x", ++ state->id, slot_index, (unsigned int)data, ++ local->slot_queue_recycle, slot_queue_available); ++ ++ /* Initialise the bitmask for services which have used this ++ ** slot */ ++ BITSET_ZERO(service_found); ++ ++ pos = 0; ++ ++ while (pos < VCHIQ_SLOT_SIZE) { ++ VCHIQ_HEADER_T *header = ++ (VCHIQ_HEADER_T *)(data + pos); ++ int msgid = header->msgid; ++ if (VCHIQ_MSG_TYPE(msgid) == VCHIQ_MSG_DATA) { ++ int port = VCHIQ_MSG_SRCPORT(msgid); ++ VCHIQ_SERVICE_QUOTA_T *service_quota = ++ &state->service_quotas[port]; ++ int count; ++ spin_lock("a_spinlock); ++ count = service_quota->message_use_count; ++ if (count > 0) ++ service_quota->message_use_count = ++ count - 1; ++ spin_unlock("a_spinlock); ++ ++ if (count == service_quota->message_quota) ++ /* Signal the service that it ++ ** has dropped below its quota ++ */ ++ up(&service_quota->quota_event); ++ else if (count == 0) { ++ vchiq_log_error(vchiq_core_log_level, ++ "service %d " ++ "message_use_count=%d " ++ "(header %x, msgid %x, " ++ "header->msgid %x, " ++ "header->size %x)", ++ port, ++ service_quota-> ++ message_use_count, ++ (unsigned int)header, msgid, ++ header->msgid, ++ header->size); ++ WARN(1, "invalid message use count\n"); ++ } ++ if (!BITSET_IS_SET(service_found, port)) { ++ /* Set the found bit for this service */ ++ BITSET_SET(service_found, port); ++ ++ spin_lock("a_spinlock); ++ count = service_quota->slot_use_count; ++ if (count > 0) ++ service_quota->slot_use_count = ++ count - 1; ++ spin_unlock("a_spinlock); ++ ++ if (count > 0) { ++ /* Signal the service in case ++ ** it has dropped below its ++ ** quota */ ++ up(&service_quota->quota_event); ++ vchiq_log_trace( ++ vchiq_core_log_level, ++ "%d: pfq:%d %x@%x - " ++ "slot_use->%d", ++ state->id, port, ++ header->size, ++ (unsigned int)header, ++ count - 1); ++ } else { ++ vchiq_log_error( ++ vchiq_core_log_level, ++ "service %d " ++ "slot_use_count" ++ "=%d (header %x" ++ ", msgid %x, " ++ "header->msgid" ++ " %x, header->" ++ "size %x)", ++ port, count, ++ (unsigned int)header, ++ msgid, ++ header->msgid, ++ header->size); ++ WARN(1, "bad slot use count\n"); ++ } ++ } ++ ++ data_found = 1; ++ } ++ ++ pos += calc_stride(header->size); ++ if (pos > VCHIQ_SLOT_SIZE) { ++ vchiq_log_error(vchiq_core_log_level, ++ "pfq - pos %x: header %x, msgid %x, " ++ "header->msgid %x, header->size %x", ++ pos, (unsigned int)header, msgid, ++ header->msgid, header->size); ++ WARN(1, "invalid slot position\n"); ++ } ++ } ++ ++ if (data_found) { ++ int count; ++ spin_lock("a_spinlock); ++ count = state->data_use_count; ++ if (count > 0) ++ state->data_use_count = ++ count - 1; ++ spin_unlock("a_spinlock); ++ if (count == state->data_quota) ++ up(&state->data_quota_event); ++ } ++ ++ state->slot_queue_available = slot_queue_available; ++ up(&state->slot_available_event); ++ } ++} ++ ++/* Called by the slot handler and application threads */ ++static VCHIQ_STATUS_T ++queue_message(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, ++ int msgid, const VCHIQ_ELEMENT_T *elements, ++ int count, int size, int flags) ++{ ++ VCHIQ_SHARED_STATE_T *local; ++ VCHIQ_SERVICE_QUOTA_T *service_quota = NULL; ++ VCHIQ_HEADER_T *header; ++ int type = VCHIQ_MSG_TYPE(msgid); ++ ++ unsigned int stride; ++ ++ local = state->local; ++ ++ stride = calc_stride(size); ++ ++ WARN_ON(!(stride <= VCHIQ_SLOT_SIZE)); ++ ++ if (!(flags & QMFLAGS_NO_MUTEX_LOCK) && ++ (mutex_lock_interruptible(&state->slot_mutex) != 0)) ++ return VCHIQ_RETRY; ++ ++ if (type == VCHIQ_MSG_DATA) { ++ int tx_end_index; ++ ++ BUG_ON(!service); ++ BUG_ON((flags & (QMFLAGS_NO_MUTEX_LOCK | ++ QMFLAGS_NO_MUTEX_UNLOCK)) != 0); ++ ++ if (service->closing) { ++ /* The service has been closed */ ++ mutex_unlock(&state->slot_mutex); ++ return VCHIQ_ERROR; ++ } ++ ++ service_quota = &state->service_quotas[service->localport]; ++ ++ spin_lock("a_spinlock); ++ ++ /* Ensure this service doesn't use more than its quota of ++ ** messages or slots */ ++ tx_end_index = SLOT_QUEUE_INDEX_FROM_POS( ++ state->local_tx_pos + stride - 1); ++ ++ /* Ensure data messages don't use more than their quota of ++ ** slots */ ++ while ((tx_end_index != state->previous_data_index) && ++ (state->data_use_count == state->data_quota)) { ++ VCHIQ_STATS_INC(state, data_stalls); ++ spin_unlock("a_spinlock); ++ mutex_unlock(&state->slot_mutex); ++ ++ if (down_interruptible(&state->data_quota_event) ++ != 0) ++ return VCHIQ_RETRY; ++ ++ mutex_lock(&state->slot_mutex); ++ spin_lock("a_spinlock); ++ tx_end_index = SLOT_QUEUE_INDEX_FROM_POS( ++ state->local_tx_pos + stride - 1); ++ if ((tx_end_index == state->previous_data_index) || ++ (state->data_use_count < state->data_quota)) { ++ /* Pass the signal on to other waiters */ ++ up(&state->data_quota_event); ++ break; ++ } ++ } ++ ++ while ((service_quota->message_use_count == ++ service_quota->message_quota) || ++ ((tx_end_index != service_quota->previous_tx_index) && ++ (service_quota->slot_use_count == ++ service_quota->slot_quota))) { ++ spin_unlock("a_spinlock); ++ vchiq_log_trace(vchiq_core_log_level, ++ "%d: qm:%d %s,%x - quota stall " ++ "(msg %d, slot %d)", ++ state->id, service->localport, ++ msg_type_str(type), size, ++ service_quota->message_use_count, ++ service_quota->slot_use_count); ++ VCHIQ_SERVICE_STATS_INC(service, quota_stalls); ++ mutex_unlock(&state->slot_mutex); ++ if (down_interruptible(&service_quota->quota_event) ++ != 0) ++ return VCHIQ_RETRY; ++ if (service->closing) ++ return VCHIQ_ERROR; ++ if (mutex_lock_interruptible(&state->slot_mutex) != 0) ++ return VCHIQ_RETRY; ++ if (service->srvstate != VCHIQ_SRVSTATE_OPEN) { ++ /* The service has been closed */ ++ mutex_unlock(&state->slot_mutex); ++ return VCHIQ_ERROR; ++ } ++ spin_lock("a_spinlock); ++ tx_end_index = SLOT_QUEUE_INDEX_FROM_POS( ++ state->local_tx_pos + stride - 1); ++ } ++ ++ spin_unlock("a_spinlock); ++ } ++ ++ header = reserve_space(state, stride, flags & QMFLAGS_IS_BLOCKING); ++ ++ if (!header) { ++ if (service) ++ VCHIQ_SERVICE_STATS_INC(service, slot_stalls); ++ /* In the event of a failure, return the mutex to the ++ state it was in */ ++ if (!(flags & QMFLAGS_NO_MUTEX_LOCK)) ++ mutex_unlock(&state->slot_mutex); ++ return VCHIQ_RETRY; ++ } ++ ++ if (type == VCHIQ_MSG_DATA) { ++ int i, pos; ++ int tx_end_index; ++ int slot_use_count; ++ ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: qm %s@%x,%x (%d->%d)", ++ state->id, ++ msg_type_str(VCHIQ_MSG_TYPE(msgid)), ++ (unsigned int)header, size, ++ VCHIQ_MSG_SRCPORT(msgid), ++ VCHIQ_MSG_DSTPORT(msgid)); ++ ++ BUG_ON(!service); ++ BUG_ON((flags & (QMFLAGS_NO_MUTEX_LOCK | ++ QMFLAGS_NO_MUTEX_UNLOCK)) != 0); ++ ++ for (i = 0, pos = 0; i < (unsigned int)count; ++ pos += elements[i++].size) ++ if (elements[i].size) { ++ if (vchiq_copy_from_user ++ (header->data + pos, elements[i].data, ++ (size_t) elements[i].size) != ++ VCHIQ_SUCCESS) { ++ mutex_unlock(&state->slot_mutex); ++ VCHIQ_SERVICE_STATS_INC(service, ++ error_count); ++ return VCHIQ_ERROR; ++ } ++ if (i == 0) { ++ if (SRVTRACE_ENABLED(service, ++ VCHIQ_LOG_INFO)) ++ vchiq_log_dump_mem("Sent", 0, ++ header->data + pos, ++ min(64u, ++ elements[0].size)); ++ } ++ } ++ ++ spin_lock("a_spinlock); ++ service_quota->message_use_count++; ++ ++ tx_end_index = ++ SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos - 1); ++ ++ /* If this transmission can't fit in the last slot used by any ++ ** service, the data_use_count must be increased. */ ++ if (tx_end_index != state->previous_data_index) { ++ state->previous_data_index = tx_end_index; ++ state->data_use_count++; ++ } ++ ++ /* If this isn't the same slot last used by this service, ++ ** the service's slot_use_count must be increased. */ ++ if (tx_end_index != service_quota->previous_tx_index) { ++ service_quota->previous_tx_index = tx_end_index; ++ slot_use_count = ++service_quota->slot_use_count; ++ } else { ++ slot_use_count = 0; ++ } ++ ++ spin_unlock("a_spinlock); ++ ++ if (slot_use_count) ++ vchiq_log_trace(vchiq_core_log_level, ++ "%d: qm:%d %s,%x - slot_use->%d (hdr %p)", ++ state->id, service->localport, ++ msg_type_str(VCHIQ_MSG_TYPE(msgid)), size, ++ slot_use_count, header); ++ ++ VCHIQ_SERVICE_STATS_INC(service, ctrl_tx_count); ++ VCHIQ_SERVICE_STATS_ADD(service, ctrl_tx_bytes, size); ++ } else { ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: qm %s@%x,%x (%d->%d)", state->id, ++ msg_type_str(VCHIQ_MSG_TYPE(msgid)), ++ (unsigned int)header, size, ++ VCHIQ_MSG_SRCPORT(msgid), ++ VCHIQ_MSG_DSTPORT(msgid)); ++ if (size != 0) { ++ WARN_ON(!((count == 1) && (size == elements[0].size))); ++ memcpy(header->data, elements[0].data, ++ elements[0].size); ++ } ++ VCHIQ_STATS_INC(state, ctrl_tx_count); ++ } ++ ++ header->msgid = msgid; ++ header->size = size; ++ ++ { ++ int svc_fourcc; ++ ++ svc_fourcc = service ++ ? service->base.fourcc ++ : VCHIQ_MAKE_FOURCC('?', '?', '?', '?'); ++ ++ vchiq_log_info(SRVTRACE_LEVEL(service), ++ "Sent Msg %s(%u) to %c%c%c%c s:%u d:%d len:%d", ++ msg_type_str(VCHIQ_MSG_TYPE(msgid)), ++ VCHIQ_MSG_TYPE(msgid), ++ VCHIQ_FOURCC_AS_4CHARS(svc_fourcc), ++ VCHIQ_MSG_SRCPORT(msgid), ++ VCHIQ_MSG_DSTPORT(msgid), ++ size); ++ } ++ ++ /* Make sure the new header is visible to the peer. */ ++ wmb(); ++ ++ /* Make the new tx_pos visible to the peer. */ ++ local->tx_pos = state->local_tx_pos; ++ wmb(); ++ ++ if (service && (type == VCHIQ_MSG_CLOSE)) ++ vchiq_set_service_state(service, VCHIQ_SRVSTATE_CLOSESENT); ++ ++ if (!(flags & QMFLAGS_NO_MUTEX_UNLOCK)) ++ mutex_unlock(&state->slot_mutex); ++ ++ remote_event_signal(&state->remote->trigger); ++ ++ return VCHIQ_SUCCESS; ++} ++ ++/* Called by the slot handler and application threads */ ++static VCHIQ_STATUS_T ++queue_message_sync(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, ++ int msgid, const VCHIQ_ELEMENT_T *elements, ++ int count, int size, int is_blocking) ++{ ++ VCHIQ_SHARED_STATE_T *local; ++ VCHIQ_HEADER_T *header; ++ ++ local = state->local; ++ ++ if ((VCHIQ_MSG_TYPE(msgid) != VCHIQ_MSG_RESUME) && ++ (mutex_lock_interruptible(&state->sync_mutex) != 0)) ++ return VCHIQ_RETRY; ++ ++ remote_event_wait(&local->sync_release); ++ ++ rmb(); ++ ++ header = (VCHIQ_HEADER_T *)SLOT_DATA_FROM_INDEX(state, ++ local->slot_sync); ++ ++ { ++ int oldmsgid = header->msgid; ++ if (oldmsgid != VCHIQ_MSGID_PADDING) ++ vchiq_log_error(vchiq_core_log_level, ++ "%d: qms - msgid %x, not PADDING", ++ state->id, oldmsgid); ++ } ++ ++ if (service) { ++ int i, pos; ++ ++ vchiq_log_info(vchiq_sync_log_level, ++ "%d: qms %s@%x,%x (%d->%d)", state->id, ++ msg_type_str(VCHIQ_MSG_TYPE(msgid)), ++ (unsigned int)header, size, ++ VCHIQ_MSG_SRCPORT(msgid), ++ VCHIQ_MSG_DSTPORT(msgid)); ++ ++ for (i = 0, pos = 0; i < (unsigned int)count; ++ pos += elements[i++].size) ++ if (elements[i].size) { ++ if (vchiq_copy_from_user ++ (header->data + pos, elements[i].data, ++ (size_t) elements[i].size) != ++ VCHIQ_SUCCESS) { ++ mutex_unlock(&state->sync_mutex); ++ VCHIQ_SERVICE_STATS_INC(service, ++ error_count); ++ return VCHIQ_ERROR; ++ } ++ if (i == 0) { ++ if (vchiq_sync_log_level >= ++ VCHIQ_LOG_TRACE) ++ vchiq_log_dump_mem("Sent Sync", ++ 0, header->data + pos, ++ min(64u, ++ elements[0].size)); ++ } ++ } ++ ++ VCHIQ_SERVICE_STATS_INC(service, ctrl_tx_count); ++ VCHIQ_SERVICE_STATS_ADD(service, ctrl_tx_bytes, size); ++ } else { ++ vchiq_log_info(vchiq_sync_log_level, ++ "%d: qms %s@%x,%x (%d->%d)", state->id, ++ msg_type_str(VCHIQ_MSG_TYPE(msgid)), ++ (unsigned int)header, size, ++ VCHIQ_MSG_SRCPORT(msgid), ++ VCHIQ_MSG_DSTPORT(msgid)); ++ if (size != 0) { ++ WARN_ON(!((count == 1) && (size == elements[0].size))); ++ memcpy(header->data, elements[0].data, ++ elements[0].size); ++ } ++ VCHIQ_STATS_INC(state, ctrl_tx_count); ++ } ++ ++ header->size = size; ++ header->msgid = msgid; ++ ++ if (vchiq_sync_log_level >= VCHIQ_LOG_TRACE) { ++ int svc_fourcc; ++ ++ svc_fourcc = service ++ ? service->base.fourcc ++ : VCHIQ_MAKE_FOURCC('?', '?', '?', '?'); ++ ++ vchiq_log_trace(vchiq_sync_log_level, ++ "Sent Sync Msg %s(%u) to %c%c%c%c s:%u d:%d len:%d", ++ msg_type_str(VCHIQ_MSG_TYPE(msgid)), ++ VCHIQ_MSG_TYPE(msgid), ++ VCHIQ_FOURCC_AS_4CHARS(svc_fourcc), ++ VCHIQ_MSG_SRCPORT(msgid), ++ VCHIQ_MSG_DSTPORT(msgid), ++ size); ++ } ++ ++ /* Make sure the new header is visible to the peer. */ ++ wmb(); ++ ++ remote_event_signal(&state->remote->sync_trigger); ++ ++ if (VCHIQ_MSG_TYPE(msgid) != VCHIQ_MSG_PAUSE) ++ mutex_unlock(&state->sync_mutex); ++ ++ return VCHIQ_SUCCESS; ++} ++ ++static inline void ++claim_slot(VCHIQ_SLOT_INFO_T *slot) ++{ ++ slot->use_count++; ++} ++ ++static void ++release_slot(VCHIQ_STATE_T *state, VCHIQ_SLOT_INFO_T *slot_info, ++ VCHIQ_HEADER_T *header, VCHIQ_SERVICE_T *service) ++{ ++ int release_count; ++ ++ mutex_lock(&state->recycle_mutex); ++ ++ if (header) { ++ int msgid = header->msgid; ++ if (((msgid & VCHIQ_MSGID_CLAIMED) == 0) || ++ (service && service->closing)) { ++ mutex_unlock(&state->recycle_mutex); ++ return; ++ } ++ ++ /* Rewrite the message header to prevent a double ++ ** release */ ++ header->msgid = msgid & ~VCHIQ_MSGID_CLAIMED; ++ } ++ ++ release_count = slot_info->release_count; ++ slot_info->release_count = ++release_count; ++ ++ if (release_count == slot_info->use_count) { ++ int slot_queue_recycle; ++ /* Add to the freed queue */ ++ ++ /* A read barrier is necessary here to prevent speculative ++ ** fetches of remote->slot_queue_recycle from overtaking the ++ ** mutex. */ ++ rmb(); ++ ++ slot_queue_recycle = state->remote->slot_queue_recycle; ++ state->remote->slot_queue[slot_queue_recycle & ++ VCHIQ_SLOT_QUEUE_MASK] = ++ SLOT_INDEX_FROM_INFO(state, slot_info); ++ state->remote->slot_queue_recycle = slot_queue_recycle + 1; ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: release_slot %d - recycle->%x", ++ state->id, SLOT_INDEX_FROM_INFO(state, slot_info), ++ state->remote->slot_queue_recycle); ++ ++ /* A write barrier is necessary, but remote_event_signal ++ ** contains one. */ ++ remote_event_signal(&state->remote->recycle); ++ } ++ ++ mutex_unlock(&state->recycle_mutex); ++} ++ ++/* Called by the slot handler - don't hold the bulk mutex */ ++static VCHIQ_STATUS_T ++notify_bulks(VCHIQ_SERVICE_T *service, VCHIQ_BULK_QUEUE_T *queue, ++ int retry_poll) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ ++ vchiq_log_trace(vchiq_core_log_level, ++ "%d: nb:%d %cx - p=%x rn=%x r=%x", ++ service->state->id, service->localport, ++ (queue == &service->bulk_tx) ? 't' : 'r', ++ queue->process, queue->remote_notify, queue->remove); ++ ++ if (service->state->is_master) { ++ while (queue->remote_notify != queue->process) { ++ VCHIQ_BULK_T *bulk = ++ &queue->bulks[BULK_INDEX(queue->remote_notify)]; ++ int msgtype = (bulk->dir == VCHIQ_BULK_TRANSMIT) ? ++ VCHIQ_MSG_BULK_RX_DONE : VCHIQ_MSG_BULK_TX_DONE; ++ int msgid = VCHIQ_MAKE_MSG(msgtype, service->localport, ++ service->remoteport); ++ VCHIQ_ELEMENT_T element = { &bulk->actual, 4 }; ++ /* Only reply to non-dummy bulk requests */ ++ if (bulk->remote_data) { ++ status = queue_message(service->state, NULL, ++ msgid, &element, 1, 4, 0); ++ if (status != VCHIQ_SUCCESS) ++ break; ++ } ++ queue->remote_notify++; ++ } ++ } else { ++ queue->remote_notify = queue->process; ++ } ++ ++ if (status == VCHIQ_SUCCESS) { ++ while (queue->remove != queue->remote_notify) { ++ VCHIQ_BULK_T *bulk = ++ &queue->bulks[BULK_INDEX(queue->remove)]; ++ ++ /* Only generate callbacks for non-dummy bulk ++ ** requests, and non-terminated services */ ++ if (bulk->data && service->instance) { ++ if (bulk->actual != VCHIQ_BULK_ACTUAL_ABORTED) { ++ if (bulk->dir == VCHIQ_BULK_TRANSMIT) { ++ VCHIQ_SERVICE_STATS_INC(service, ++ bulk_tx_count); ++ VCHIQ_SERVICE_STATS_ADD(service, ++ bulk_tx_bytes, ++ bulk->actual); ++ } else { ++ VCHIQ_SERVICE_STATS_INC(service, ++ bulk_rx_count); ++ VCHIQ_SERVICE_STATS_ADD(service, ++ bulk_rx_bytes, ++ bulk->actual); ++ } ++ } else { ++ VCHIQ_SERVICE_STATS_INC(service, ++ bulk_aborted_count); ++ } ++ if (bulk->mode == VCHIQ_BULK_MODE_BLOCKING) { ++ struct bulk_waiter *waiter; ++ spin_lock(&bulk_waiter_spinlock); ++ waiter = bulk->userdata; ++ if (waiter) { ++ waiter->actual = bulk->actual; ++ up(&waiter->event); ++ } ++ spin_unlock(&bulk_waiter_spinlock); ++ } else if (bulk->mode == ++ VCHIQ_BULK_MODE_CALLBACK) { ++ VCHIQ_REASON_T reason = (bulk->dir == ++ VCHIQ_BULK_TRANSMIT) ? ++ ((bulk->actual == ++ VCHIQ_BULK_ACTUAL_ABORTED) ? ++ VCHIQ_BULK_TRANSMIT_ABORTED : ++ VCHIQ_BULK_TRANSMIT_DONE) : ++ ((bulk->actual == ++ VCHIQ_BULK_ACTUAL_ABORTED) ? ++ VCHIQ_BULK_RECEIVE_ABORTED : ++ VCHIQ_BULK_RECEIVE_DONE); ++ status = make_service_callback(service, ++ reason, NULL, bulk->userdata); ++ if (status == VCHIQ_RETRY) ++ break; ++ } ++ } ++ ++ queue->remove++; ++ up(&service->bulk_remove_event); ++ } ++ if (!retry_poll) ++ status = VCHIQ_SUCCESS; ++ } ++ ++ if (status == VCHIQ_RETRY) ++ request_poll(service->state, service, ++ (queue == &service->bulk_tx) ? ++ VCHIQ_POLL_TXNOTIFY : VCHIQ_POLL_RXNOTIFY); ++ ++ return status; ++} ++ ++/* Called by the slot handler thread */ ++static void ++poll_services(VCHIQ_STATE_T *state) ++{ ++ int group, i; ++ ++ for (group = 0; group < BITSET_SIZE(state->unused_service); group++) { ++ uint32_t flags; ++ flags = atomic_xchg(&state->poll_services[group], 0); ++ for (i = 0; flags; i++) { ++ if (flags & (1 << i)) { ++ VCHIQ_SERVICE_T *service = ++ find_service_by_port(state, ++ (group<<5) + i); ++ uint32_t service_flags; ++ flags &= ~(1 << i); ++ if (!service) ++ continue; ++ service_flags = ++ atomic_xchg(&service->poll_flags, 0); ++ if (service_flags & ++ (1 << VCHIQ_POLL_REMOVE)) { ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: ps - remove %d<->%d", ++ state->id, service->localport, ++ service->remoteport); ++ ++ /* Make it look like a client, because ++ it must be removed and not left in ++ the LISTENING state. */ ++ service->public_fourcc = ++ VCHIQ_FOURCC_INVALID; ++ ++ if (vchiq_close_service_internal( ++ service, 0/*!close_recvd*/) != ++ VCHIQ_SUCCESS) ++ request_poll(state, service, ++ VCHIQ_POLL_REMOVE); ++ } else if (service_flags & ++ (1 << VCHIQ_POLL_TERMINATE)) { ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: ps - terminate %d<->%d", ++ state->id, service->localport, ++ service->remoteport); ++ if (vchiq_close_service_internal( ++ service, 0/*!close_recvd*/) != ++ VCHIQ_SUCCESS) ++ request_poll(state, service, ++ VCHIQ_POLL_TERMINATE); ++ } ++ if (service_flags & (1 << VCHIQ_POLL_TXNOTIFY)) ++ notify_bulks(service, ++ &service->bulk_tx, ++ 1/*retry_poll*/); ++ if (service_flags & (1 << VCHIQ_POLL_RXNOTIFY)) ++ notify_bulks(service, ++ &service->bulk_rx, ++ 1/*retry_poll*/); ++ unlock_service(service); ++ } ++ } ++ } ++} ++ ++/* Called by the slot handler or application threads, holding the bulk mutex. */ ++static int ++resolve_bulks(VCHIQ_SERVICE_T *service, VCHIQ_BULK_QUEUE_T *queue) ++{ ++ VCHIQ_STATE_T *state = service->state; ++ int resolved = 0; ++ int rc; ++ ++ while ((queue->process != queue->local_insert) && ++ (queue->process != queue->remote_insert)) { ++ VCHIQ_BULK_T *bulk = &queue->bulks[BULK_INDEX(queue->process)]; ++ ++ vchiq_log_trace(vchiq_core_log_level, ++ "%d: rb:%d %cx - li=%x ri=%x p=%x", ++ state->id, service->localport, ++ (queue == &service->bulk_tx) ? 't' : 'r', ++ queue->local_insert, queue->remote_insert, ++ queue->process); ++ ++ WARN_ON(!((int)(queue->local_insert - queue->process) > 0)); ++ WARN_ON(!((int)(queue->remote_insert - queue->process) > 0)); ++ ++ rc = mutex_lock_interruptible(&state->bulk_transfer_mutex); ++ if (rc != 0) ++ break; ++ ++ vchiq_transfer_bulk(bulk); ++ mutex_unlock(&state->bulk_transfer_mutex); ++ ++ if (SRVTRACE_ENABLED(service, VCHIQ_LOG_INFO)) { ++ const char *header = (queue == &service->bulk_tx) ? ++ "Send Bulk to" : "Recv Bulk from"; ++ if (bulk->actual != VCHIQ_BULK_ACTUAL_ABORTED) ++ vchiq_log_info(SRVTRACE_LEVEL(service), ++ "%s %c%c%c%c d:%d len:%d %x<->%x", ++ header, ++ VCHIQ_FOURCC_AS_4CHARS( ++ service->base.fourcc), ++ service->remoteport, ++ bulk->size, ++ (unsigned int)bulk->data, ++ (unsigned int)bulk->remote_data); ++ else ++ vchiq_log_info(SRVTRACE_LEVEL(service), ++ "%s %c%c%c%c d:%d ABORTED - tx len:%d," ++ " rx len:%d %x<->%x", ++ header, ++ VCHIQ_FOURCC_AS_4CHARS( ++ service->base.fourcc), ++ service->remoteport, ++ bulk->size, ++ bulk->remote_size, ++ (unsigned int)bulk->data, ++ (unsigned int)bulk->remote_data); ++ } ++ ++ vchiq_complete_bulk(bulk); ++ queue->process++; ++ resolved++; ++ } ++ return resolved; ++} ++ ++/* Called with the bulk_mutex held */ ++static void ++abort_outstanding_bulks(VCHIQ_SERVICE_T *service, VCHIQ_BULK_QUEUE_T *queue) ++{ ++ int is_tx = (queue == &service->bulk_tx); ++ vchiq_log_trace(vchiq_core_log_level, ++ "%d: aob:%d %cx - li=%x ri=%x p=%x", ++ service->state->id, service->localport, is_tx ? 't' : 'r', ++ queue->local_insert, queue->remote_insert, queue->process); ++ ++ WARN_ON(!((int)(queue->local_insert - queue->process) >= 0)); ++ WARN_ON(!((int)(queue->remote_insert - queue->process) >= 0)); ++ ++ while ((queue->process != queue->local_insert) || ++ (queue->process != queue->remote_insert)) { ++ VCHIQ_BULK_T *bulk = &queue->bulks[BULK_INDEX(queue->process)]; ++ ++ if (queue->process == queue->remote_insert) { ++ /* fabricate a matching dummy bulk */ ++ bulk->remote_data = NULL; ++ bulk->remote_size = 0; ++ queue->remote_insert++; ++ } ++ ++ if (queue->process != queue->local_insert) { ++ vchiq_complete_bulk(bulk); ++ ++ vchiq_log_info(SRVTRACE_LEVEL(service), ++ "%s %c%c%c%c d:%d ABORTED - tx len:%d, " ++ "rx len:%d", ++ is_tx ? "Send Bulk to" : "Recv Bulk from", ++ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), ++ service->remoteport, ++ bulk->size, ++ bulk->remote_size); ++ } else { ++ /* fabricate a matching dummy bulk */ ++ bulk->data = NULL; ++ bulk->size = 0; ++ bulk->actual = VCHIQ_BULK_ACTUAL_ABORTED; ++ bulk->dir = is_tx ? VCHIQ_BULK_TRANSMIT : ++ VCHIQ_BULK_RECEIVE; ++ queue->local_insert++; ++ } ++ ++ queue->process++; ++ } ++} ++ ++/* Called from the slot handler thread */ ++static void ++pause_bulks(VCHIQ_STATE_T *state) ++{ ++ if (unlikely(atomic_inc_return(&pause_bulks_count) != 1)) { ++ WARN_ON_ONCE(1); ++ atomic_set(&pause_bulks_count, 1); ++ return; ++ } ++ ++ /* Block bulk transfers from all services */ ++ mutex_lock(&state->bulk_transfer_mutex); ++} ++ ++/* Called from the slot handler thread */ ++static void ++resume_bulks(VCHIQ_STATE_T *state) ++{ ++ int i; ++ if (unlikely(atomic_dec_return(&pause_bulks_count) != 0)) { ++ WARN_ON_ONCE(1); ++ atomic_set(&pause_bulks_count, 0); ++ return; ++ } ++ ++ /* Allow bulk transfers from all services */ ++ mutex_unlock(&state->bulk_transfer_mutex); ++ ++ if (state->deferred_bulks == 0) ++ return; ++ ++ /* Deal with any bulks which had to be deferred due to being in ++ * paused state. Don't try to match up to number of deferred bulks ++ * in case we've had something come and close the service in the ++ * interim - just process all bulk queues for all services */ ++ vchiq_log_info(vchiq_core_log_level, "%s: processing %d deferred bulks", ++ __func__, state->deferred_bulks); ++ ++ for (i = 0; i < state->unused_service; i++) { ++ VCHIQ_SERVICE_T *service = state->services[i]; ++ int resolved_rx = 0; ++ int resolved_tx = 0; ++ if (!service || (service->srvstate != VCHIQ_SRVSTATE_OPEN)) ++ continue; ++ ++ mutex_lock(&service->bulk_mutex); ++ resolved_rx = resolve_bulks(service, &service->bulk_rx); ++ resolved_tx = resolve_bulks(service, &service->bulk_tx); ++ mutex_unlock(&service->bulk_mutex); ++ if (resolved_rx) ++ notify_bulks(service, &service->bulk_rx, 1); ++ if (resolved_tx) ++ notify_bulks(service, &service->bulk_tx, 1); ++ } ++ state->deferred_bulks = 0; ++} ++ ++static int ++parse_open(VCHIQ_STATE_T *state, VCHIQ_HEADER_T *header) ++{ ++ VCHIQ_SERVICE_T *service = NULL; ++ int msgid, size; ++ int type; ++ unsigned int localport, remoteport; ++ ++ msgid = header->msgid; ++ size = header->size; ++ type = VCHIQ_MSG_TYPE(msgid); ++ localport = VCHIQ_MSG_DSTPORT(msgid); ++ remoteport = VCHIQ_MSG_SRCPORT(msgid); ++ if (size >= sizeof(struct vchiq_open_payload)) { ++ const struct vchiq_open_payload *payload = ++ (struct vchiq_open_payload *)header->data; ++ unsigned int fourcc; ++ ++ fourcc = payload->fourcc; ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: prs OPEN@%x (%d->'%c%c%c%c')", ++ state->id, (unsigned int)header, ++ localport, ++ VCHIQ_FOURCC_AS_4CHARS(fourcc)); ++ ++ service = get_listening_service(state, fourcc); ++ ++ if (service) { ++ /* A matching service exists */ ++ short version = payload->version; ++ short version_min = payload->version_min; ++ if ((service->version < version_min) || ++ (version < service->version_min)) { ++ /* Version mismatch */ ++ vchiq_loud_error_header(); ++ vchiq_loud_error("%d: service %d (%c%c%c%c) " ++ "version mismatch - local (%d, min %d)" ++ " vs. remote (%d, min %d)", ++ state->id, service->localport, ++ VCHIQ_FOURCC_AS_4CHARS(fourcc), ++ service->version, service->version_min, ++ version, version_min); ++ vchiq_loud_error_footer(); ++ unlock_service(service); ++ service = NULL; ++ goto fail_open; ++ } ++ service->peer_version = version; ++ ++ if (service->srvstate == VCHIQ_SRVSTATE_LISTENING) { ++ struct vchiq_openack_payload ack_payload = { ++ service->version ++ }; ++ VCHIQ_ELEMENT_T body = { ++ &ack_payload, ++ sizeof(ack_payload) ++ }; ++ ++ if (state->version_common < ++ VCHIQ_VERSION_SYNCHRONOUS_MODE) ++ service->sync = 0; ++ ++ /* Acknowledge the OPEN */ ++ if (service->sync && ++ (state->version_common >= ++ VCHIQ_VERSION_SYNCHRONOUS_MODE)) { ++ if (queue_message_sync(state, NULL, ++ VCHIQ_MAKE_MSG( ++ VCHIQ_MSG_OPENACK, ++ service->localport, ++ remoteport), ++ &body, 1, sizeof(ack_payload), ++ 0) == VCHIQ_RETRY) ++ goto bail_not_ready; ++ } else { ++ if (queue_message(state, NULL, ++ VCHIQ_MAKE_MSG( ++ VCHIQ_MSG_OPENACK, ++ service->localport, ++ remoteport), ++ &body, 1, sizeof(ack_payload), ++ 0) == VCHIQ_RETRY) ++ goto bail_not_ready; ++ } ++ ++ /* The service is now open */ ++ vchiq_set_service_state(service, ++ service->sync ? VCHIQ_SRVSTATE_OPENSYNC ++ : VCHIQ_SRVSTATE_OPEN); ++ } ++ ++ service->remoteport = remoteport; ++ service->client_id = ((int *)header->data)[1]; ++ if (make_service_callback(service, VCHIQ_SERVICE_OPENED, ++ NULL, NULL) == VCHIQ_RETRY) { ++ /* Bail out if not ready */ ++ service->remoteport = VCHIQ_PORT_FREE; ++ goto bail_not_ready; ++ } ++ ++ /* Success - the message has been dealt with */ ++ unlock_service(service); ++ return 1; ++ } ++ } ++ ++fail_open: ++ /* No available service, or an invalid request - send a CLOSE */ ++ if (queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_CLOSE, 0, VCHIQ_MSG_SRCPORT(msgid)), ++ NULL, 0, 0, 0) == VCHIQ_RETRY) ++ goto bail_not_ready; ++ ++ return 1; ++ ++bail_not_ready: ++ if (service) ++ unlock_service(service); ++ ++ return 0; ++} ++ ++/* Called by the slot handler thread */ ++static void ++parse_rx_slots(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_SHARED_STATE_T *remote = state->remote; ++ VCHIQ_SERVICE_T *service = NULL; ++ int tx_pos; ++ DEBUG_INITIALISE(state->local) ++ ++ tx_pos = remote->tx_pos; ++ ++ while (state->rx_pos != tx_pos) { ++ VCHIQ_HEADER_T *header; ++ int msgid, size; ++ int type; ++ unsigned int localport, remoteport; ++ ++ DEBUG_TRACE(PARSE_LINE); ++ if (!state->rx_data) { ++ int rx_index; ++ WARN_ON(!((state->rx_pos & VCHIQ_SLOT_MASK) == 0)); ++ rx_index = remote->slot_queue[ ++ SLOT_QUEUE_INDEX_FROM_POS(state->rx_pos) & ++ VCHIQ_SLOT_QUEUE_MASK]; ++ state->rx_data = (char *)SLOT_DATA_FROM_INDEX(state, ++ rx_index); ++ state->rx_info = SLOT_INFO_FROM_INDEX(state, rx_index); ++ ++ /* Initialise use_count to one, and increment ++ ** release_count at the end of the slot to avoid ++ ** releasing the slot prematurely. */ ++ state->rx_info->use_count = 1; ++ state->rx_info->release_count = 0; ++ } ++ ++ header = (VCHIQ_HEADER_T *)(state->rx_data + ++ (state->rx_pos & VCHIQ_SLOT_MASK)); ++ DEBUG_VALUE(PARSE_HEADER, (int)header); ++ msgid = header->msgid; ++ DEBUG_VALUE(PARSE_MSGID, msgid); ++ size = header->size; ++ type = VCHIQ_MSG_TYPE(msgid); ++ localport = VCHIQ_MSG_DSTPORT(msgid); ++ remoteport = VCHIQ_MSG_SRCPORT(msgid); ++ ++ if (type != VCHIQ_MSG_DATA) ++ VCHIQ_STATS_INC(state, ctrl_rx_count); ++ ++ switch (type) { ++ case VCHIQ_MSG_OPENACK: ++ case VCHIQ_MSG_CLOSE: ++ case VCHIQ_MSG_DATA: ++ case VCHIQ_MSG_BULK_RX: ++ case VCHIQ_MSG_BULK_TX: ++ case VCHIQ_MSG_BULK_RX_DONE: ++ case VCHIQ_MSG_BULK_TX_DONE: ++ service = find_service_by_port(state, localport); ++ if ((!service || ++ ((service->remoteport != remoteport) && ++ (service->remoteport != VCHIQ_PORT_FREE))) && ++ (localport == 0) && ++ (type == VCHIQ_MSG_CLOSE)) { ++ /* This could be a CLOSE from a client which ++ hadn't yet received the OPENACK - look for ++ the connected service */ ++ if (service) ++ unlock_service(service); ++ service = get_connected_service(state, ++ remoteport); ++ if (service) ++ vchiq_log_warning(vchiq_core_log_level, ++ "%d: prs %s@%x (%d->%d) - " ++ "found connected service %d", ++ state->id, msg_type_str(type), ++ (unsigned int)header, ++ remoteport, localport, ++ service->localport); ++ } ++ ++ if (!service) { ++ vchiq_log_error(vchiq_core_log_level, ++ "%d: prs %s@%x (%d->%d) - " ++ "invalid/closed service %d", ++ state->id, msg_type_str(type), ++ (unsigned int)header, ++ remoteport, localport, localport); ++ goto skip_message; ++ } ++ break; ++ default: ++ break; ++ } ++ ++ if (SRVTRACE_ENABLED(service, VCHIQ_LOG_INFO)) { ++ int svc_fourcc; ++ ++ svc_fourcc = service ++ ? service->base.fourcc ++ : VCHIQ_MAKE_FOURCC('?', '?', '?', '?'); ++ vchiq_log_info(SRVTRACE_LEVEL(service), ++ "Rcvd Msg %s(%u) from %c%c%c%c s:%d d:%d " ++ "len:%d", ++ msg_type_str(type), type, ++ VCHIQ_FOURCC_AS_4CHARS(svc_fourcc), ++ remoteport, localport, size); ++ if (size > 0) ++ vchiq_log_dump_mem("Rcvd", 0, header->data, ++ min(64, size)); ++ } ++ ++ if (((unsigned int)header & VCHIQ_SLOT_MASK) + calc_stride(size) ++ > VCHIQ_SLOT_SIZE) { ++ vchiq_log_error(vchiq_core_log_level, ++ "header %x (msgid %x) - size %x too big for " ++ "slot", ++ (unsigned int)header, (unsigned int)msgid, ++ (unsigned int)size); ++ WARN(1, "oversized for slot\n"); ++ } ++ ++ switch (type) { ++ case VCHIQ_MSG_OPEN: ++ WARN_ON(!(VCHIQ_MSG_DSTPORT(msgid) == 0)); ++ if (!parse_open(state, header)) ++ goto bail_not_ready; ++ break; ++ case VCHIQ_MSG_OPENACK: ++ if (size >= sizeof(struct vchiq_openack_payload)) { ++ const struct vchiq_openack_payload *payload = ++ (struct vchiq_openack_payload *) ++ header->data; ++ service->peer_version = payload->version; ++ } ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: prs OPENACK@%x,%x (%d->%d) v:%d", ++ state->id, (unsigned int)header, size, ++ remoteport, localport, service->peer_version); ++ if (service->srvstate == ++ VCHIQ_SRVSTATE_OPENING) { ++ service->remoteport = remoteport; ++ vchiq_set_service_state(service, ++ VCHIQ_SRVSTATE_OPEN); ++ up(&service->remove_event); ++ } else ++ vchiq_log_error(vchiq_core_log_level, ++ "OPENACK received in state %s", ++ srvstate_names[service->srvstate]); ++ break; ++ case VCHIQ_MSG_CLOSE: ++ WARN_ON(size != 0); /* There should be no data */ ++ ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: prs CLOSE@%x (%d->%d)", ++ state->id, (unsigned int)header, ++ remoteport, localport); ++ ++ mark_service_closing_internal(service, 1); ++ ++ if (vchiq_close_service_internal(service, ++ 1/*close_recvd*/) == VCHIQ_RETRY) ++ goto bail_not_ready; ++ ++ vchiq_log_info(vchiq_core_log_level, ++ "Close Service %c%c%c%c s:%u d:%d", ++ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), ++ service->localport, ++ service->remoteport); ++ break; ++ case VCHIQ_MSG_DATA: ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: prs DATA@%x,%x (%d->%d)", ++ state->id, (unsigned int)header, size, ++ remoteport, localport); ++ ++ if ((service->remoteport == remoteport) ++ && (service->srvstate == ++ VCHIQ_SRVSTATE_OPEN)) { ++ header->msgid = msgid | VCHIQ_MSGID_CLAIMED; ++ claim_slot(state->rx_info); ++ DEBUG_TRACE(PARSE_LINE); ++ if (make_service_callback(service, ++ VCHIQ_MESSAGE_AVAILABLE, header, ++ NULL) == VCHIQ_RETRY) { ++ DEBUG_TRACE(PARSE_LINE); ++ goto bail_not_ready; ++ } ++ VCHIQ_SERVICE_STATS_INC(service, ctrl_rx_count); ++ VCHIQ_SERVICE_STATS_ADD(service, ctrl_rx_bytes, ++ size); ++ } else { ++ VCHIQ_STATS_INC(state, error_count); ++ } ++ break; ++ case VCHIQ_MSG_CONNECT: ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: prs CONNECT@%x", ++ state->id, (unsigned int)header); ++ state->version_common = ((VCHIQ_SLOT_ZERO_T *) ++ state->slot_data)->version; ++ up(&state->connect); ++ break; ++ case VCHIQ_MSG_BULK_RX: ++ case VCHIQ_MSG_BULK_TX: { ++ VCHIQ_BULK_QUEUE_T *queue; ++ WARN_ON(!state->is_master); ++ queue = (type == VCHIQ_MSG_BULK_RX) ? ++ &service->bulk_tx : &service->bulk_rx; ++ if ((service->remoteport == remoteport) ++ && (service->srvstate == ++ VCHIQ_SRVSTATE_OPEN)) { ++ VCHIQ_BULK_T *bulk; ++ int resolved = 0; ++ ++ DEBUG_TRACE(PARSE_LINE); ++ if (mutex_lock_interruptible( ++ &service->bulk_mutex) != 0) { ++ DEBUG_TRACE(PARSE_LINE); ++ goto bail_not_ready; ++ } ++ ++ WARN_ON(!(queue->remote_insert < queue->remove + ++ VCHIQ_NUM_SERVICE_BULKS)); ++ bulk = &queue->bulks[ ++ BULK_INDEX(queue->remote_insert)]; ++ bulk->remote_data = ++ (void *)((int *)header->data)[0]; ++ bulk->remote_size = ((int *)header->data)[1]; ++ wmb(); ++ ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: prs %s@%x (%d->%d) %x@%x", ++ state->id, msg_type_str(type), ++ (unsigned int)header, ++ remoteport, localport, ++ bulk->remote_size, ++ (unsigned int)bulk->remote_data); ++ ++ queue->remote_insert++; ++ ++ if (atomic_read(&pause_bulks_count)) { ++ state->deferred_bulks++; ++ vchiq_log_info(vchiq_core_log_level, ++ "%s: deferring bulk (%d)", ++ __func__, ++ state->deferred_bulks); ++ if (state->conn_state != ++ VCHIQ_CONNSTATE_PAUSE_SENT) ++ vchiq_log_error( ++ vchiq_core_log_level, ++ "%s: bulks paused in " ++ "unexpected state %s", ++ __func__, ++ conn_state_names[ ++ state->conn_state]); ++ } else if (state->conn_state == ++ VCHIQ_CONNSTATE_CONNECTED) { ++ DEBUG_TRACE(PARSE_LINE); ++ resolved = resolve_bulks(service, ++ queue); ++ } ++ ++ mutex_unlock(&service->bulk_mutex); ++ if (resolved) ++ notify_bulks(service, queue, ++ 1/*retry_poll*/); ++ } ++ } break; ++ case VCHIQ_MSG_BULK_RX_DONE: ++ case VCHIQ_MSG_BULK_TX_DONE: ++ WARN_ON(state->is_master); ++ if ((service->remoteport == remoteport) ++ && (service->srvstate != ++ VCHIQ_SRVSTATE_FREE)) { ++ VCHIQ_BULK_QUEUE_T *queue; ++ VCHIQ_BULK_T *bulk; ++ ++ queue = (type == VCHIQ_MSG_BULK_RX_DONE) ? ++ &service->bulk_rx : &service->bulk_tx; ++ ++ DEBUG_TRACE(PARSE_LINE); ++ if (mutex_lock_interruptible( ++ &service->bulk_mutex) != 0) { ++ DEBUG_TRACE(PARSE_LINE); ++ goto bail_not_ready; ++ } ++ if ((int)(queue->remote_insert - ++ queue->local_insert) >= 0) { ++ vchiq_log_error(vchiq_core_log_level, ++ "%d: prs %s@%x (%d->%d) " ++ "unexpected (ri=%d,li=%d)", ++ state->id, msg_type_str(type), ++ (unsigned int)header, ++ remoteport, localport, ++ queue->remote_insert, ++ queue->local_insert); ++ mutex_unlock(&service->bulk_mutex); ++ break; ++ } ++ ++ BUG_ON(queue->process == queue->local_insert); ++ BUG_ON(queue->process != queue->remote_insert); ++ ++ bulk = &queue->bulks[ ++ BULK_INDEX(queue->remote_insert)]; ++ bulk->actual = *(int *)header->data; ++ queue->remote_insert++; ++ ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: prs %s@%x (%d->%d) %x@%x", ++ state->id, msg_type_str(type), ++ (unsigned int)header, ++ remoteport, localport, ++ bulk->actual, (unsigned int)bulk->data); ++ ++ vchiq_log_trace(vchiq_core_log_level, ++ "%d: prs:%d %cx li=%x ri=%x p=%x", ++ state->id, localport, ++ (type == VCHIQ_MSG_BULK_RX_DONE) ? ++ 'r' : 't', ++ queue->local_insert, ++ queue->remote_insert, queue->process); ++ ++ DEBUG_TRACE(PARSE_LINE); ++ WARN_ON(queue->process == queue->local_insert); ++ vchiq_complete_bulk(bulk); ++ queue->process++; ++ mutex_unlock(&service->bulk_mutex); ++ DEBUG_TRACE(PARSE_LINE); ++ notify_bulks(service, queue, 1/*retry_poll*/); ++ DEBUG_TRACE(PARSE_LINE); ++ } ++ break; ++ case VCHIQ_MSG_PADDING: ++ vchiq_log_trace(vchiq_core_log_level, ++ "%d: prs PADDING@%x,%x", ++ state->id, (unsigned int)header, size); ++ break; ++ case VCHIQ_MSG_PAUSE: ++ /* If initiated, signal the application thread */ ++ vchiq_log_trace(vchiq_core_log_level, ++ "%d: prs PAUSE@%x,%x", ++ state->id, (unsigned int)header, size); ++ if (state->conn_state == VCHIQ_CONNSTATE_PAUSED) { ++ vchiq_log_error(vchiq_core_log_level, ++ "%d: PAUSE received in state PAUSED", ++ state->id); ++ break; ++ } ++ if (state->conn_state != VCHIQ_CONNSTATE_PAUSE_SENT) { ++ /* Send a PAUSE in response */ ++ if (queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_PAUSE, 0, 0), ++ NULL, 0, 0, QMFLAGS_NO_MUTEX_UNLOCK) ++ == VCHIQ_RETRY) ++ goto bail_not_ready; ++ if (state->is_master) ++ pause_bulks(state); ++ } ++ /* At this point slot_mutex is held */ ++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_PAUSED); ++ vchiq_platform_paused(state); ++ break; ++ case VCHIQ_MSG_RESUME: ++ vchiq_log_trace(vchiq_core_log_level, ++ "%d: prs RESUME@%x,%x", ++ state->id, (unsigned int)header, size); ++ /* Release the slot mutex */ ++ mutex_unlock(&state->slot_mutex); ++ if (state->is_master) ++ resume_bulks(state); ++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTED); ++ vchiq_platform_resumed(state); ++ break; ++ ++ case VCHIQ_MSG_REMOTE_USE: ++ vchiq_on_remote_use(state); ++ break; ++ case VCHIQ_MSG_REMOTE_RELEASE: ++ vchiq_on_remote_release(state); ++ break; ++ case VCHIQ_MSG_REMOTE_USE_ACTIVE: ++ vchiq_on_remote_use_active(state); ++ break; ++ ++ default: ++ vchiq_log_error(vchiq_core_log_level, ++ "%d: prs invalid msgid %x@%x,%x", ++ state->id, msgid, (unsigned int)header, size); ++ WARN(1, "invalid message\n"); ++ break; ++ } ++ ++skip_message: ++ if (service) { ++ unlock_service(service); ++ service = NULL; ++ } ++ ++ state->rx_pos += calc_stride(size); ++ ++ DEBUG_TRACE(PARSE_LINE); ++ /* Perform some housekeeping when the end of the slot is ++ ** reached. */ ++ if ((state->rx_pos & VCHIQ_SLOT_MASK) == 0) { ++ /* Remove the extra reference count. */ ++ release_slot(state, state->rx_info, NULL, NULL); ++ state->rx_data = NULL; ++ } ++ } ++ ++bail_not_ready: ++ if (service) ++ unlock_service(service); ++} ++ ++/* Called by the slot handler thread */ ++static int ++slot_handler_func(void *v) ++{ ++ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v; ++ VCHIQ_SHARED_STATE_T *local = state->local; ++ DEBUG_INITIALISE(local) ++ ++ while (1) { ++ DEBUG_COUNT(SLOT_HANDLER_COUNT); ++ DEBUG_TRACE(SLOT_HANDLER_LINE); ++ remote_event_wait(&local->trigger); ++ ++ rmb(); ++ ++ DEBUG_TRACE(SLOT_HANDLER_LINE); ++ if (state->poll_needed) { ++ /* Check if we need to suspend - may change our ++ * conn_state */ ++ vchiq_platform_check_suspend(state); ++ ++ state->poll_needed = 0; ++ ++ /* Handle service polling and other rare conditions here ++ ** out of the mainline code */ ++ switch (state->conn_state) { ++ case VCHIQ_CONNSTATE_CONNECTED: ++ /* Poll the services as requested */ ++ poll_services(state); ++ break; ++ ++ case VCHIQ_CONNSTATE_PAUSING: ++ if (state->is_master) ++ pause_bulks(state); ++ if (queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_PAUSE, 0, 0), ++ NULL, 0, 0, ++ QMFLAGS_NO_MUTEX_UNLOCK) ++ != VCHIQ_RETRY) { ++ vchiq_set_conn_state(state, ++ VCHIQ_CONNSTATE_PAUSE_SENT); ++ } else { ++ if (state->is_master) ++ resume_bulks(state); ++ /* Retry later */ ++ state->poll_needed = 1; ++ } ++ break; ++ ++ case VCHIQ_CONNSTATE_PAUSED: ++ vchiq_platform_resume(state); ++ break; ++ ++ case VCHIQ_CONNSTATE_RESUMING: ++ if (queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_RESUME, 0, 0), ++ NULL, 0, 0, QMFLAGS_NO_MUTEX_LOCK) ++ != VCHIQ_RETRY) { ++ if (state->is_master) ++ resume_bulks(state); ++ vchiq_set_conn_state(state, ++ VCHIQ_CONNSTATE_CONNECTED); ++ vchiq_platform_resumed(state); ++ } else { ++ /* This should really be impossible, ++ ** since the PAUSE should have flushed ++ ** through outstanding messages. */ ++ vchiq_log_error(vchiq_core_log_level, ++ "Failed to send RESUME " ++ "message"); ++ BUG(); ++ } ++ break; ++ ++ case VCHIQ_CONNSTATE_PAUSE_TIMEOUT: ++ case VCHIQ_CONNSTATE_RESUME_TIMEOUT: ++ vchiq_platform_handle_timeout(state); ++ break; ++ default: ++ break; ++ } ++ ++ ++ } ++ ++ DEBUG_TRACE(SLOT_HANDLER_LINE); ++ parse_rx_slots(state); ++ } ++ return 0; ++} ++ ++ ++/* Called by the recycle thread */ ++static int ++recycle_func(void *v) ++{ ++ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v; ++ VCHIQ_SHARED_STATE_T *local = state->local; ++ ++ while (1) { ++ remote_event_wait(&local->recycle); ++ ++ process_free_queue(state); ++ } ++ return 0; ++} ++ ++ ++/* Called by the sync thread */ ++static int ++sync_func(void *v) ++{ ++ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v; ++ VCHIQ_SHARED_STATE_T *local = state->local; ++ VCHIQ_HEADER_T *header = (VCHIQ_HEADER_T *)SLOT_DATA_FROM_INDEX(state, ++ state->remote->slot_sync); ++ ++ while (1) { ++ VCHIQ_SERVICE_T *service; ++ int msgid, size; ++ int type; ++ unsigned int localport, remoteport; ++ ++ remote_event_wait(&local->sync_trigger); ++ ++ rmb(); ++ ++ msgid = header->msgid; ++ size = header->size; ++ type = VCHIQ_MSG_TYPE(msgid); ++ localport = VCHIQ_MSG_DSTPORT(msgid); ++ remoteport = VCHIQ_MSG_SRCPORT(msgid); ++ ++ service = find_service_by_port(state, localport); ++ ++ if (!service) { ++ vchiq_log_error(vchiq_sync_log_level, ++ "%d: sf %s@%x (%d->%d) - " ++ "invalid/closed service %d", ++ state->id, msg_type_str(type), ++ (unsigned int)header, ++ remoteport, localport, localport); ++ release_message_sync(state, header); ++ continue; ++ } ++ ++ if (vchiq_sync_log_level >= VCHIQ_LOG_TRACE) { ++ int svc_fourcc; ++ ++ svc_fourcc = service ++ ? service->base.fourcc ++ : VCHIQ_MAKE_FOURCC('?', '?', '?', '?'); ++ vchiq_log_trace(vchiq_sync_log_level, ++ "Rcvd Msg %s from %c%c%c%c s:%d d:%d len:%d", ++ msg_type_str(type), ++ VCHIQ_FOURCC_AS_4CHARS(svc_fourcc), ++ remoteport, localport, size); ++ if (size > 0) ++ vchiq_log_dump_mem("Rcvd", 0, header->data, ++ min(64, size)); ++ } ++ ++ switch (type) { ++ case VCHIQ_MSG_OPENACK: ++ if (size >= sizeof(struct vchiq_openack_payload)) { ++ const struct vchiq_openack_payload *payload = ++ (struct vchiq_openack_payload *) ++ header->data; ++ service->peer_version = payload->version; ++ } ++ vchiq_log_info(vchiq_sync_log_level, ++ "%d: sf OPENACK@%x,%x (%d->%d) v:%d", ++ state->id, (unsigned int)header, size, ++ remoteport, localport, service->peer_version); ++ if (service->srvstate == VCHIQ_SRVSTATE_OPENING) { ++ service->remoteport = remoteport; ++ vchiq_set_service_state(service, ++ VCHIQ_SRVSTATE_OPENSYNC); ++ service->sync = 1; ++ up(&service->remove_event); ++ } ++ release_message_sync(state, header); ++ break; ++ ++ case VCHIQ_MSG_DATA: ++ vchiq_log_trace(vchiq_sync_log_level, ++ "%d: sf DATA@%x,%x (%d->%d)", ++ state->id, (unsigned int)header, size, ++ remoteport, localport); ++ ++ if ((service->remoteport == remoteport) && ++ (service->srvstate == ++ VCHIQ_SRVSTATE_OPENSYNC)) { ++ if (make_service_callback(service, ++ VCHIQ_MESSAGE_AVAILABLE, header, ++ NULL) == VCHIQ_RETRY) ++ vchiq_log_error(vchiq_sync_log_level, ++ "synchronous callback to " ++ "service %d returns " ++ "VCHIQ_RETRY", ++ localport); ++ } ++ break; ++ ++ default: ++ vchiq_log_error(vchiq_sync_log_level, ++ "%d: sf unexpected msgid %x@%x,%x", ++ state->id, msgid, (unsigned int)header, size); ++ release_message_sync(state, header); ++ break; ++ } ++ ++ unlock_service(service); ++ } ++ ++ return 0; ++} ++ ++ ++static void ++init_bulk_queue(VCHIQ_BULK_QUEUE_T *queue) ++{ ++ queue->local_insert = 0; ++ queue->remote_insert = 0; ++ queue->process = 0; ++ queue->remote_notify = 0; ++ queue->remove = 0; ++} ++ ++ ++inline const char * ++get_conn_state_name(VCHIQ_CONNSTATE_T conn_state) ++{ ++ return conn_state_names[conn_state]; ++} ++ ++ ++VCHIQ_SLOT_ZERO_T * ++vchiq_init_slots(void *mem_base, int mem_size) ++{ ++ int mem_align = (VCHIQ_SLOT_SIZE - (int)mem_base) & VCHIQ_SLOT_MASK; ++ VCHIQ_SLOT_ZERO_T *slot_zero = ++ (VCHIQ_SLOT_ZERO_T *)((char *)mem_base + mem_align); ++ int num_slots = (mem_size - mem_align)/VCHIQ_SLOT_SIZE; ++ int first_data_slot = VCHIQ_SLOT_ZERO_SLOTS; ++ ++ /* Ensure there is enough memory to run an absolutely minimum system */ ++ num_slots -= first_data_slot; ++ ++ if (num_slots < 4) { ++ vchiq_log_error(vchiq_core_log_level, ++ "vchiq_init_slots - insufficient memory %x bytes", ++ mem_size); ++ return NULL; ++ } ++ ++ memset(slot_zero, 0, sizeof(VCHIQ_SLOT_ZERO_T)); ++ ++ slot_zero->magic = VCHIQ_MAGIC; ++ slot_zero->version = VCHIQ_VERSION; ++ slot_zero->version_min = VCHIQ_VERSION_MIN; ++ slot_zero->slot_zero_size = sizeof(VCHIQ_SLOT_ZERO_T); ++ slot_zero->slot_size = VCHIQ_SLOT_SIZE; ++ slot_zero->max_slots = VCHIQ_MAX_SLOTS; ++ slot_zero->max_slots_per_side = VCHIQ_MAX_SLOTS_PER_SIDE; ++ ++ slot_zero->master.slot_sync = first_data_slot; ++ slot_zero->master.slot_first = first_data_slot + 1; ++ slot_zero->master.slot_last = first_data_slot + (num_slots/2) - 1; ++ slot_zero->slave.slot_sync = first_data_slot + (num_slots/2); ++ slot_zero->slave.slot_first = first_data_slot + (num_slots/2) + 1; ++ slot_zero->slave.slot_last = first_data_slot + num_slots - 1; ++ ++ return slot_zero; ++} ++ ++VCHIQ_STATUS_T ++vchiq_init_state(VCHIQ_STATE_T *state, VCHIQ_SLOT_ZERO_T *slot_zero, ++ int is_master) ++{ ++ VCHIQ_SHARED_STATE_T *local; ++ VCHIQ_SHARED_STATE_T *remote; ++ VCHIQ_STATUS_T status; ++ char threadname[10]; ++ static int id; ++ int i; ++ ++ vchiq_log_warning(vchiq_core_log_level, ++ "%s: slot_zero = 0x%08lx, is_master = %d", ++ __func__, (unsigned long)slot_zero, is_master); ++ ++ /* Check the input configuration */ ++ ++ if (slot_zero->magic != VCHIQ_MAGIC) { ++ vchiq_loud_error_header(); ++ vchiq_loud_error("Invalid VCHIQ magic value found."); ++ vchiq_loud_error("slot_zero=%x: magic=%x (expected %x)", ++ (unsigned int)slot_zero, slot_zero->magic, VCHIQ_MAGIC); ++ vchiq_loud_error_footer(); ++ return VCHIQ_ERROR; ++ } ++ ++ if (slot_zero->version < VCHIQ_VERSION_MIN) { ++ vchiq_loud_error_header(); ++ vchiq_loud_error("Incompatible VCHIQ versions found."); ++ vchiq_loud_error("slot_zero=%x: VideoCore version=%d " ++ "(minimum %d)", ++ (unsigned int)slot_zero, slot_zero->version, ++ VCHIQ_VERSION_MIN); ++ vchiq_loud_error("Restart with a newer VideoCore image."); ++ vchiq_loud_error_footer(); ++ return VCHIQ_ERROR; ++ } ++ ++ if (VCHIQ_VERSION < slot_zero->version_min) { ++ vchiq_loud_error_header(); ++ vchiq_loud_error("Incompatible VCHIQ versions found."); ++ vchiq_loud_error("slot_zero=%x: version=%d (VideoCore " ++ "minimum %d)", ++ (unsigned int)slot_zero, VCHIQ_VERSION, ++ slot_zero->version_min); ++ vchiq_loud_error("Restart with a newer kernel."); ++ vchiq_loud_error_footer(); ++ return VCHIQ_ERROR; ++ } ++ ++ if ((slot_zero->slot_zero_size != sizeof(VCHIQ_SLOT_ZERO_T)) || ++ (slot_zero->slot_size != VCHIQ_SLOT_SIZE) || ++ (slot_zero->max_slots != VCHIQ_MAX_SLOTS) || ++ (slot_zero->max_slots_per_side != VCHIQ_MAX_SLOTS_PER_SIDE)) { ++ vchiq_loud_error_header(); ++ if (slot_zero->slot_zero_size != sizeof(VCHIQ_SLOT_ZERO_T)) ++ vchiq_loud_error("slot_zero=%x: slot_zero_size=%x " ++ "(expected %x)", ++ (unsigned int)slot_zero, ++ slot_zero->slot_zero_size, ++ sizeof(VCHIQ_SLOT_ZERO_T)); ++ if (slot_zero->slot_size != VCHIQ_SLOT_SIZE) ++ vchiq_loud_error("slot_zero=%x: slot_size=%d " ++ "(expected %d", ++ (unsigned int)slot_zero, slot_zero->slot_size, ++ VCHIQ_SLOT_SIZE); ++ if (slot_zero->max_slots != VCHIQ_MAX_SLOTS) ++ vchiq_loud_error("slot_zero=%x: max_slots=%d " ++ "(expected %d)", ++ (unsigned int)slot_zero, slot_zero->max_slots, ++ VCHIQ_MAX_SLOTS); ++ if (slot_zero->max_slots_per_side != VCHIQ_MAX_SLOTS_PER_SIDE) ++ vchiq_loud_error("slot_zero=%x: max_slots_per_side=%d " ++ "(expected %d)", ++ (unsigned int)slot_zero, ++ slot_zero->max_slots_per_side, ++ VCHIQ_MAX_SLOTS_PER_SIDE); ++ vchiq_loud_error_footer(); ++ return VCHIQ_ERROR; ++ } ++ ++ if (VCHIQ_VERSION < slot_zero->version) ++ slot_zero->version = VCHIQ_VERSION; ++ ++ if (is_master) { ++ local = &slot_zero->master; ++ remote = &slot_zero->slave; ++ } else { ++ local = &slot_zero->slave; ++ remote = &slot_zero->master; ++ } ++ ++ if (local->initialised) { ++ vchiq_loud_error_header(); ++ if (remote->initialised) ++ vchiq_loud_error("local state has already been " ++ "initialised"); ++ else ++ vchiq_loud_error("master/slave mismatch - two %ss", ++ is_master ? "master" : "slave"); ++ vchiq_loud_error_footer(); ++ return VCHIQ_ERROR; ++ } ++ ++ memset(state, 0, sizeof(VCHIQ_STATE_T)); ++ ++ state->id = id++; ++ state->is_master = is_master; ++ ++ /* ++ initialize shared state pointers ++ */ ++ ++ state->local = local; ++ state->remote = remote; ++ state->slot_data = (VCHIQ_SLOT_T *)slot_zero; ++ ++ /* ++ initialize events and mutexes ++ */ ++ ++ sema_init(&state->connect, 0); ++ mutex_init(&state->mutex); ++ sema_init(&state->trigger_event, 0); ++ sema_init(&state->recycle_event, 0); ++ sema_init(&state->sync_trigger_event, 0); ++ sema_init(&state->sync_release_event, 0); ++ ++ mutex_init(&state->slot_mutex); ++ mutex_init(&state->recycle_mutex); ++ mutex_init(&state->sync_mutex); ++ mutex_init(&state->bulk_transfer_mutex); ++ ++ sema_init(&state->slot_available_event, 0); ++ sema_init(&state->slot_remove_event, 0); ++ sema_init(&state->data_quota_event, 0); ++ ++ state->slot_queue_available = 0; ++ ++ for (i = 0; i < VCHIQ_MAX_SERVICES; i++) { ++ VCHIQ_SERVICE_QUOTA_T *service_quota = ++ &state->service_quotas[i]; ++ sema_init(&service_quota->quota_event, 0); ++ } ++ ++ for (i = local->slot_first; i <= local->slot_last; i++) { ++ local->slot_queue[state->slot_queue_available++] = i; ++ up(&state->slot_available_event); ++ } ++ ++ state->default_slot_quota = state->slot_queue_available/2; ++ state->default_message_quota = ++ min((unsigned short)(state->default_slot_quota * 256), ++ (unsigned short)~0); ++ ++ state->previous_data_index = -1; ++ state->data_use_count = 0; ++ state->data_quota = state->slot_queue_available - 1; ++ ++ local->trigger.event = &state->trigger_event; ++ remote_event_create(&local->trigger); ++ local->tx_pos = 0; ++ ++ local->recycle.event = &state->recycle_event; ++ remote_event_create(&local->recycle); ++ local->slot_queue_recycle = state->slot_queue_available; ++ ++ local->sync_trigger.event = &state->sync_trigger_event; ++ remote_event_create(&local->sync_trigger); ++ ++ local->sync_release.event = &state->sync_release_event; ++ remote_event_create(&local->sync_release); ++ ++ /* At start-of-day, the slot is empty and available */ ++ ((VCHIQ_HEADER_T *)SLOT_DATA_FROM_INDEX(state, local->slot_sync))->msgid ++ = VCHIQ_MSGID_PADDING; ++ remote_event_signal_local(&local->sync_release); ++ ++ local->debug[DEBUG_ENTRIES] = DEBUG_MAX; ++ ++ status = vchiq_platform_init_state(state); ++ ++ /* ++ bring up slot handler thread ++ */ ++ snprintf(threadname, sizeof(threadname), "VCHIQ-%d", state->id); ++ state->slot_handler_thread = kthread_create(&slot_handler_func, ++ (void *)state, ++ threadname); ++ ++ if (state->slot_handler_thread == NULL) { ++ vchiq_loud_error_header(); ++ vchiq_loud_error("couldn't create thread %s", threadname); ++ vchiq_loud_error_footer(); ++ return VCHIQ_ERROR; ++ } ++ set_user_nice(state->slot_handler_thread, -19); ++ wake_up_process(state->slot_handler_thread); ++ ++ snprintf(threadname, sizeof(threadname), "VCHIQr-%d", state->id); ++ state->recycle_thread = kthread_create(&recycle_func, ++ (void *)state, ++ threadname); ++ if (state->recycle_thread == NULL) { ++ vchiq_loud_error_header(); ++ vchiq_loud_error("couldn't create thread %s", threadname); ++ vchiq_loud_error_footer(); ++ return VCHIQ_ERROR; ++ } ++ set_user_nice(state->recycle_thread, -19); ++ wake_up_process(state->recycle_thread); ++ ++ snprintf(threadname, sizeof(threadname), "VCHIQs-%d", state->id); ++ state->sync_thread = kthread_create(&sync_func, ++ (void *)state, ++ threadname); ++ if (state->sync_thread == NULL) { ++ vchiq_loud_error_header(); ++ vchiq_loud_error("couldn't create thread %s", threadname); ++ vchiq_loud_error_footer(); ++ return VCHIQ_ERROR; ++ } ++ set_user_nice(state->sync_thread, -20); ++ wake_up_process(state->sync_thread); ++ ++ BUG_ON(state->id >= VCHIQ_MAX_STATES); ++ vchiq_states[state->id] = state; ++ ++ /* Indicate readiness to the other side */ ++ local->initialised = 1; ++ ++ return status; ++} ++ ++/* Called from application thread when a client or server service is created. */ ++VCHIQ_SERVICE_T * ++vchiq_add_service_internal(VCHIQ_STATE_T *state, ++ const VCHIQ_SERVICE_PARAMS_T *params, int srvstate, ++ VCHIQ_INSTANCE_T instance, VCHIQ_USERDATA_TERM_T userdata_term) ++{ ++ VCHIQ_SERVICE_T *service; ++ ++ service = kmalloc(sizeof(VCHIQ_SERVICE_T), GFP_KERNEL); ++ if (service) { ++ service->base.fourcc = params->fourcc; ++ service->base.callback = params->callback; ++ service->base.userdata = params->userdata; ++ service->handle = VCHIQ_SERVICE_HANDLE_INVALID; ++ service->ref_count = 1; ++ service->srvstate = VCHIQ_SRVSTATE_FREE; ++ service->userdata_term = userdata_term; ++ service->localport = VCHIQ_PORT_FREE; ++ service->remoteport = VCHIQ_PORT_FREE; ++ ++ service->public_fourcc = (srvstate == VCHIQ_SRVSTATE_OPENING) ? ++ VCHIQ_FOURCC_INVALID : params->fourcc; ++ service->client_id = 0; ++ service->auto_close = 1; ++ service->sync = 0; ++ service->closing = 0; ++ service->trace = 0; ++ atomic_set(&service->poll_flags, 0); ++ service->version = params->version; ++ service->version_min = params->version_min; ++ service->state = state; ++ service->instance = instance; ++ service->service_use_count = 0; ++ init_bulk_queue(&service->bulk_tx); ++ init_bulk_queue(&service->bulk_rx); ++ sema_init(&service->remove_event, 0); ++ sema_init(&service->bulk_remove_event, 0); ++ mutex_init(&service->bulk_mutex); ++ memset(&service->stats, 0, sizeof(service->stats)); ++ } else { ++ vchiq_log_error(vchiq_core_log_level, ++ "Out of memory"); ++ } ++ ++ if (service) { ++ VCHIQ_SERVICE_T **pservice = NULL; ++ int i; ++ ++ /* Although it is perfectly possible to use service_spinlock ++ ** to protect the creation of services, it is overkill as it ++ ** disables interrupts while the array is searched. ++ ** The only danger is of another thread trying to create a ++ ** service - service deletion is safe. ++ ** Therefore it is preferable to use state->mutex which, ++ ** although slower to claim, doesn't block interrupts while ++ ** it is held. ++ */ ++ ++ mutex_lock(&state->mutex); ++ ++ /* Prepare to use a previously unused service */ ++ if (state->unused_service < VCHIQ_MAX_SERVICES) ++ pservice = &state->services[state->unused_service]; ++ ++ if (srvstate == VCHIQ_SRVSTATE_OPENING) { ++ for (i = 0; i < state->unused_service; i++) { ++ VCHIQ_SERVICE_T *srv = state->services[i]; ++ if (!srv) { ++ pservice = &state->services[i]; ++ break; ++ } ++ } ++ } else { ++ for (i = (state->unused_service - 1); i >= 0; i--) { ++ VCHIQ_SERVICE_T *srv = state->services[i]; ++ if (!srv) ++ pservice = &state->services[i]; ++ else if ((srv->public_fourcc == params->fourcc) ++ && ((srv->instance != instance) || ++ (srv->base.callback != ++ params->callback))) { ++ /* There is another server using this ++ ** fourcc which doesn't match. */ ++ pservice = NULL; ++ break; ++ } ++ } ++ } ++ ++ if (pservice) { ++ service->localport = (pservice - state->services); ++ if (!handle_seq) ++ handle_seq = VCHIQ_MAX_STATES * ++ VCHIQ_MAX_SERVICES; ++ service->handle = handle_seq | ++ (state->id * VCHIQ_MAX_SERVICES) | ++ service->localport; ++ handle_seq += VCHIQ_MAX_STATES * VCHIQ_MAX_SERVICES; ++ *pservice = service; ++ if (pservice == &state->services[state->unused_service]) ++ state->unused_service++; ++ } ++ ++ mutex_unlock(&state->mutex); ++ ++ if (!pservice) { ++ kfree(service); ++ service = NULL; ++ } ++ } ++ ++ if (service) { ++ VCHIQ_SERVICE_QUOTA_T *service_quota = ++ &state->service_quotas[service->localport]; ++ service_quota->slot_quota = state->default_slot_quota; ++ service_quota->message_quota = state->default_message_quota; ++ if (service_quota->slot_use_count == 0) ++ service_quota->previous_tx_index = ++ SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos) ++ - 1; ++ ++ /* Bring this service online */ ++ vchiq_set_service_state(service, srvstate); ++ ++ vchiq_log_info(vchiq_core_msg_log_level, ++ "%s Service %c%c%c%c SrcPort:%d", ++ (srvstate == VCHIQ_SRVSTATE_OPENING) ++ ? "Open" : "Add", ++ VCHIQ_FOURCC_AS_4CHARS(params->fourcc), ++ service->localport); ++ } ++ ++ /* Don't unlock the service - leave it with a ref_count of 1. */ ++ ++ return service; ++} ++ ++VCHIQ_STATUS_T ++vchiq_open_service_internal(VCHIQ_SERVICE_T *service, int client_id) ++{ ++ struct vchiq_open_payload payload = { ++ service->base.fourcc, ++ client_id, ++ service->version, ++ service->version_min ++ }; ++ VCHIQ_ELEMENT_T body = { &payload, sizeof(payload) }; ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ ++ service->client_id = client_id; ++ vchiq_use_service_internal(service); ++ status = queue_message(service->state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_OPEN, service->localport, 0), ++ &body, 1, sizeof(payload), QMFLAGS_IS_BLOCKING); ++ if (status == VCHIQ_SUCCESS) { ++ /* Wait for the ACK/NAK */ ++ if (down_interruptible(&service->remove_event) != 0) { ++ status = VCHIQ_RETRY; ++ vchiq_release_service_internal(service); ++ } else if ((service->srvstate != VCHIQ_SRVSTATE_OPEN) && ++ (service->srvstate != VCHIQ_SRVSTATE_OPENSYNC)) { ++ if (service->srvstate != VCHIQ_SRVSTATE_CLOSEWAIT) ++ vchiq_log_error(vchiq_core_log_level, ++ "%d: osi - srvstate = %s (ref %d)", ++ service->state->id, ++ srvstate_names[service->srvstate], ++ service->ref_count); ++ status = VCHIQ_ERROR; ++ VCHIQ_SERVICE_STATS_INC(service, error_count); ++ vchiq_release_service_internal(service); ++ } ++ } ++ return status; ++} ++ ++static void ++release_service_messages(VCHIQ_SERVICE_T *service) ++{ ++ VCHIQ_STATE_T *state = service->state; ++ int slot_last = state->remote->slot_last; ++ int i; ++ ++ /* Release any claimed messages aimed at this service */ ++ ++ if (service->sync) { ++ VCHIQ_HEADER_T *header = ++ (VCHIQ_HEADER_T *)SLOT_DATA_FROM_INDEX(state, ++ state->remote->slot_sync); ++ if (VCHIQ_MSG_DSTPORT(header->msgid) == service->localport) ++ release_message_sync(state, header); ++ ++ return; ++ } ++ ++ for (i = state->remote->slot_first; i <= slot_last; i++) { ++ VCHIQ_SLOT_INFO_T *slot_info = ++ SLOT_INFO_FROM_INDEX(state, i); ++ if (slot_info->release_count != slot_info->use_count) { ++ char *data = ++ (char *)SLOT_DATA_FROM_INDEX(state, i); ++ unsigned int pos, end; ++ ++ end = VCHIQ_SLOT_SIZE; ++ if (data == state->rx_data) ++ /* This buffer is still being read from - stop ++ ** at the current read position */ ++ end = state->rx_pos & VCHIQ_SLOT_MASK; ++ ++ pos = 0; ++ ++ while (pos < end) { ++ VCHIQ_HEADER_T *header = ++ (VCHIQ_HEADER_T *)(data + pos); ++ int msgid = header->msgid; ++ int port = VCHIQ_MSG_DSTPORT(msgid); ++ if ((port == service->localport) && ++ (msgid & VCHIQ_MSGID_CLAIMED)) { ++ vchiq_log_info(vchiq_core_log_level, ++ " fsi - hdr %x", ++ (unsigned int)header); ++ release_slot(state, slot_info, header, ++ NULL); ++ } ++ pos += calc_stride(header->size); ++ if (pos > VCHIQ_SLOT_SIZE) { ++ vchiq_log_error(vchiq_core_log_level, ++ "fsi - pos %x: header %x, " ++ "msgid %x, header->msgid %x, " ++ "header->size %x", ++ pos, (unsigned int)header, ++ msgid, header->msgid, ++ header->size); ++ WARN(1, "invalid slot position\n"); ++ } ++ } ++ } ++ } ++} ++ ++static int ++do_abort_bulks(VCHIQ_SERVICE_T *service) ++{ ++ VCHIQ_STATUS_T status; ++ ++ /* Abort any outstanding bulk transfers */ ++ if (mutex_lock_interruptible(&service->bulk_mutex) != 0) ++ return 0; ++ abort_outstanding_bulks(service, &service->bulk_tx); ++ abort_outstanding_bulks(service, &service->bulk_rx); ++ mutex_unlock(&service->bulk_mutex); ++ ++ status = notify_bulks(service, &service->bulk_tx, 0/*!retry_poll*/); ++ if (status == VCHIQ_SUCCESS) ++ status = notify_bulks(service, &service->bulk_rx, ++ 0/*!retry_poll*/); ++ return (status == VCHIQ_SUCCESS); ++} ++ ++static VCHIQ_STATUS_T ++close_service_complete(VCHIQ_SERVICE_T *service, int failstate) ++{ ++ VCHIQ_STATUS_T status; ++ int is_server = (service->public_fourcc != VCHIQ_FOURCC_INVALID); ++ int newstate; ++ ++ switch (service->srvstate) { ++ case VCHIQ_SRVSTATE_OPEN: ++ case VCHIQ_SRVSTATE_CLOSESENT: ++ case VCHIQ_SRVSTATE_CLOSERECVD: ++ if (is_server) { ++ if (service->auto_close) { ++ service->client_id = 0; ++ service->remoteport = VCHIQ_PORT_FREE; ++ newstate = VCHIQ_SRVSTATE_LISTENING; ++ } else ++ newstate = VCHIQ_SRVSTATE_CLOSEWAIT; ++ } else ++ newstate = VCHIQ_SRVSTATE_CLOSED; ++ vchiq_set_service_state(service, newstate); ++ break; ++ case VCHIQ_SRVSTATE_LISTENING: ++ break; ++ default: ++ vchiq_log_error(vchiq_core_log_level, ++ "close_service_complete(%x) called in state %s", ++ service->handle, srvstate_names[service->srvstate]); ++ WARN(1, "close_service_complete in unexpected state\n"); ++ return VCHIQ_ERROR; ++ } ++ ++ status = make_service_callback(service, ++ VCHIQ_SERVICE_CLOSED, NULL, NULL); ++ ++ if (status != VCHIQ_RETRY) { ++ int uc = service->service_use_count; ++ int i; ++ /* Complete the close process */ ++ for (i = 0; i < uc; i++) ++ /* cater for cases where close is forced and the ++ ** client may not close all it's handles */ ++ vchiq_release_service_internal(service); ++ ++ service->client_id = 0; ++ service->remoteport = VCHIQ_PORT_FREE; ++ ++ if (service->srvstate == VCHIQ_SRVSTATE_CLOSED) ++ vchiq_free_service_internal(service); ++ else if (service->srvstate != VCHIQ_SRVSTATE_CLOSEWAIT) { ++ if (is_server) ++ service->closing = 0; ++ ++ up(&service->remove_event); ++ } ++ } else ++ vchiq_set_service_state(service, failstate); ++ ++ return status; ++} ++ ++/* Called by the slot handler */ ++VCHIQ_STATUS_T ++vchiq_close_service_internal(VCHIQ_SERVICE_T *service, int close_recvd) ++{ ++ VCHIQ_STATE_T *state = service->state; ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ int is_server = (service->public_fourcc != VCHIQ_FOURCC_INVALID); ++ ++ vchiq_log_info(vchiq_core_log_level, "%d: csi:%d,%d (%s)", ++ service->state->id, service->localport, close_recvd, ++ srvstate_names[service->srvstate]); ++ ++ switch (service->srvstate) { ++ case VCHIQ_SRVSTATE_CLOSED: ++ case VCHIQ_SRVSTATE_HIDDEN: ++ case VCHIQ_SRVSTATE_LISTENING: ++ case VCHIQ_SRVSTATE_CLOSEWAIT: ++ if (close_recvd) ++ vchiq_log_error(vchiq_core_log_level, ++ "vchiq_close_service_internal(1) called " ++ "in state %s", ++ srvstate_names[service->srvstate]); ++ else if (is_server) { ++ if (service->srvstate == VCHIQ_SRVSTATE_LISTENING) { ++ status = VCHIQ_ERROR; ++ } else { ++ service->client_id = 0; ++ service->remoteport = VCHIQ_PORT_FREE; ++ if (service->srvstate == ++ VCHIQ_SRVSTATE_CLOSEWAIT) ++ vchiq_set_service_state(service, ++ VCHIQ_SRVSTATE_LISTENING); ++ } ++ up(&service->remove_event); ++ } else ++ vchiq_free_service_internal(service); ++ break; ++ case VCHIQ_SRVSTATE_OPENING: ++ if (close_recvd) { ++ /* The open was rejected - tell the user */ ++ vchiq_set_service_state(service, ++ VCHIQ_SRVSTATE_CLOSEWAIT); ++ up(&service->remove_event); ++ } else { ++ /* Shutdown mid-open - let the other side know */ ++ status = queue_message(state, service, ++ VCHIQ_MAKE_MSG ++ (VCHIQ_MSG_CLOSE, ++ service->localport, ++ VCHIQ_MSG_DSTPORT(service->remoteport)), ++ NULL, 0, 0, 0); ++ } ++ break; ++ ++ case VCHIQ_SRVSTATE_OPENSYNC: ++ mutex_lock(&state->sync_mutex); ++ /* Drop through */ ++ ++ case VCHIQ_SRVSTATE_OPEN: ++ if (state->is_master || close_recvd) { ++ if (!do_abort_bulks(service)) ++ status = VCHIQ_RETRY; ++ } ++ ++ release_service_messages(service); ++ ++ if (status == VCHIQ_SUCCESS) ++ status = queue_message(state, service, ++ VCHIQ_MAKE_MSG ++ (VCHIQ_MSG_CLOSE, ++ service->localport, ++ VCHIQ_MSG_DSTPORT(service->remoteport)), ++ NULL, 0, 0, QMFLAGS_NO_MUTEX_UNLOCK); ++ ++ if (status == VCHIQ_SUCCESS) { ++ if (!close_recvd) { ++ /* Change the state while the mutex is ++ still held */ ++ vchiq_set_service_state(service, ++ VCHIQ_SRVSTATE_CLOSESENT); ++ mutex_unlock(&state->slot_mutex); ++ if (service->sync) ++ mutex_unlock(&state->sync_mutex); ++ break; ++ } ++ } else if (service->srvstate == VCHIQ_SRVSTATE_OPENSYNC) { ++ mutex_unlock(&state->sync_mutex); ++ break; ++ } else ++ break; ++ ++ /* Change the state while the mutex is still held */ ++ vchiq_set_service_state(service, VCHIQ_SRVSTATE_CLOSERECVD); ++ mutex_unlock(&state->slot_mutex); ++ if (service->sync) ++ mutex_unlock(&state->sync_mutex); ++ ++ status = close_service_complete(service, ++ VCHIQ_SRVSTATE_CLOSERECVD); ++ break; ++ ++ case VCHIQ_SRVSTATE_CLOSESENT: ++ if (!close_recvd) ++ /* This happens when a process is killed mid-close */ ++ break; ++ ++ if (!state->is_master) { ++ if (!do_abort_bulks(service)) { ++ status = VCHIQ_RETRY; ++ break; ++ } ++ } ++ ++ if (status == VCHIQ_SUCCESS) ++ status = close_service_complete(service, ++ VCHIQ_SRVSTATE_CLOSERECVD); ++ break; ++ ++ case VCHIQ_SRVSTATE_CLOSERECVD: ++ if (!close_recvd && is_server) ++ /* Force into LISTENING mode */ ++ vchiq_set_service_state(service, ++ VCHIQ_SRVSTATE_LISTENING); ++ status = close_service_complete(service, ++ VCHIQ_SRVSTATE_CLOSERECVD); ++ break; ++ ++ default: ++ vchiq_log_error(vchiq_core_log_level, ++ "vchiq_close_service_internal(%d) called in state %s", ++ close_recvd, srvstate_names[service->srvstate]); ++ break; ++ } ++ ++ return status; ++} ++ ++/* Called from the application process upon process death */ ++void ++vchiq_terminate_service_internal(VCHIQ_SERVICE_T *service) ++{ ++ VCHIQ_STATE_T *state = service->state; ++ ++ vchiq_log_info(vchiq_core_log_level, "%d: tsi - (%d<->%d)", ++ state->id, service->localport, service->remoteport); ++ ++ mark_service_closing(service); ++ ++ /* Mark the service for removal by the slot handler */ ++ request_poll(state, service, VCHIQ_POLL_REMOVE); ++} ++ ++/* Called from the slot handler */ ++void ++vchiq_free_service_internal(VCHIQ_SERVICE_T *service) ++{ ++ VCHIQ_STATE_T *state = service->state; ++ ++ vchiq_log_info(vchiq_core_log_level, "%d: fsi - (%d)", ++ state->id, service->localport); ++ ++ switch (service->srvstate) { ++ case VCHIQ_SRVSTATE_OPENING: ++ case VCHIQ_SRVSTATE_CLOSED: ++ case VCHIQ_SRVSTATE_HIDDEN: ++ case VCHIQ_SRVSTATE_LISTENING: ++ case VCHIQ_SRVSTATE_CLOSEWAIT: ++ break; ++ default: ++ vchiq_log_error(vchiq_core_log_level, ++ "%d: fsi - (%d) in state %s", ++ state->id, service->localport, ++ srvstate_names[service->srvstate]); ++ return; ++ } ++ ++ vchiq_set_service_state(service, VCHIQ_SRVSTATE_FREE); ++ ++ up(&service->remove_event); ++ ++ /* Release the initial lock */ ++ unlock_service(service); ++} ++ ++VCHIQ_STATUS_T ++vchiq_connect_internal(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance) ++{ ++ VCHIQ_SERVICE_T *service; ++ int i; ++ ++ /* Find all services registered to this client and enable them. */ ++ i = 0; ++ while ((service = next_service_by_instance(state, instance, ++ &i)) != NULL) { ++ if (service->srvstate == VCHIQ_SRVSTATE_HIDDEN) ++ vchiq_set_service_state(service, ++ VCHIQ_SRVSTATE_LISTENING); ++ unlock_service(service); ++ } ++ ++ if (state->conn_state == VCHIQ_CONNSTATE_DISCONNECTED) { ++ if (queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_CONNECT, 0, 0), NULL, 0, ++ 0, QMFLAGS_IS_BLOCKING) == VCHIQ_RETRY) ++ return VCHIQ_RETRY; ++ ++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTING); ++ } ++ ++ if (state->conn_state == VCHIQ_CONNSTATE_CONNECTING) { ++ if (down_interruptible(&state->connect) != 0) ++ return VCHIQ_RETRY; ++ ++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTED); ++ up(&state->connect); ++ } ++ ++ return VCHIQ_SUCCESS; ++} ++ ++VCHIQ_STATUS_T ++vchiq_shutdown_internal(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance) ++{ ++ VCHIQ_SERVICE_T *service; ++ int i; ++ ++ /* Find all services registered to this client and enable them. */ ++ i = 0; ++ while ((service = next_service_by_instance(state, instance, ++ &i)) != NULL) { ++ (void)vchiq_remove_service(service->handle); ++ unlock_service(service); ++ } ++ ++ return VCHIQ_SUCCESS; ++} ++ ++VCHIQ_STATUS_T ++vchiq_pause_internal(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ ++ switch (state->conn_state) { ++ case VCHIQ_CONNSTATE_CONNECTED: ++ /* Request a pause */ ++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_PAUSING); ++ request_poll(state, NULL, 0); ++ break; ++ default: ++ vchiq_log_error(vchiq_core_log_level, ++ "vchiq_pause_internal in state %s\n", ++ conn_state_names[state->conn_state]); ++ status = VCHIQ_ERROR; ++ VCHIQ_STATS_INC(state, error_count); ++ break; ++ } ++ ++ return status; ++} ++ ++VCHIQ_STATUS_T ++vchiq_resume_internal(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ ++ if (state->conn_state == VCHIQ_CONNSTATE_PAUSED) { ++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_RESUMING); ++ request_poll(state, NULL, 0); ++ } else { ++ status = VCHIQ_ERROR; ++ VCHIQ_STATS_INC(state, error_count); ++ } ++ ++ return status; ++} ++ ++VCHIQ_STATUS_T ++vchiq_close_service(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ /* Unregister the service */ ++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ ++ if (!service) ++ return VCHIQ_ERROR; ++ ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: close_service:%d", ++ service->state->id, service->localport); ++ ++ if ((service->srvstate == VCHIQ_SRVSTATE_FREE) || ++ (service->srvstate == VCHIQ_SRVSTATE_LISTENING) || ++ (service->srvstate == VCHIQ_SRVSTATE_HIDDEN)) { ++ unlock_service(service); ++ return VCHIQ_ERROR; ++ } ++ ++ mark_service_closing(service); ++ ++ if (current == service->state->slot_handler_thread) { ++ status = vchiq_close_service_internal(service, ++ 0/*!close_recvd*/); ++ BUG_ON(status == VCHIQ_RETRY); ++ } else { ++ /* Mark the service for termination by the slot handler */ ++ request_poll(service->state, service, VCHIQ_POLL_TERMINATE); ++ } ++ ++ while (1) { ++ if (down_interruptible(&service->remove_event) != 0) { ++ status = VCHIQ_RETRY; ++ break; ++ } ++ ++ if ((service->srvstate == VCHIQ_SRVSTATE_FREE) || ++ (service->srvstate == VCHIQ_SRVSTATE_LISTENING) || ++ (service->srvstate == VCHIQ_SRVSTATE_OPEN)) ++ break; ++ ++ vchiq_log_warning(vchiq_core_log_level, ++ "%d: close_service:%d - waiting in state %s", ++ service->state->id, service->localport, ++ srvstate_names[service->srvstate]); ++ } ++ ++ if ((status == VCHIQ_SUCCESS) && ++ (service->srvstate != VCHIQ_SRVSTATE_FREE) && ++ (service->srvstate != VCHIQ_SRVSTATE_LISTENING)) ++ status = VCHIQ_ERROR; ++ ++ unlock_service(service); ++ ++ return status; ++} ++ ++VCHIQ_STATUS_T ++vchiq_remove_service(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ /* Unregister the service */ ++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ ++ if (!service) ++ return VCHIQ_ERROR; ++ ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: remove_service:%d", ++ service->state->id, service->localport); ++ ++ if (service->srvstate == VCHIQ_SRVSTATE_FREE) { ++ unlock_service(service); ++ return VCHIQ_ERROR; ++ } ++ ++ mark_service_closing(service); ++ ++ if ((service->srvstate == VCHIQ_SRVSTATE_HIDDEN) || ++ (current == service->state->slot_handler_thread)) { ++ /* Make it look like a client, because it must be removed and ++ not left in the LISTENING state. */ ++ service->public_fourcc = VCHIQ_FOURCC_INVALID; ++ ++ status = vchiq_close_service_internal(service, ++ 0/*!close_recvd*/); ++ BUG_ON(status == VCHIQ_RETRY); ++ } else { ++ /* Mark the service for removal by the slot handler */ ++ request_poll(service->state, service, VCHIQ_POLL_REMOVE); ++ } ++ while (1) { ++ if (down_interruptible(&service->remove_event) != 0) { ++ status = VCHIQ_RETRY; ++ break; ++ } ++ ++ if ((service->srvstate == VCHIQ_SRVSTATE_FREE) || ++ (service->srvstate == VCHIQ_SRVSTATE_OPEN)) ++ break; ++ ++ vchiq_log_warning(vchiq_core_log_level, ++ "%d: remove_service:%d - waiting in state %s", ++ service->state->id, service->localport, ++ srvstate_names[service->srvstate]); ++ } ++ ++ if ((status == VCHIQ_SUCCESS) && ++ (service->srvstate != VCHIQ_SRVSTATE_FREE)) ++ status = VCHIQ_ERROR; ++ ++ unlock_service(service); ++ ++ return status; ++} ++ ++ ++/* This function may be called by kernel threads or user threads. ++ * User threads may receive VCHIQ_RETRY to indicate that a signal has been ++ * received and the call should be retried after being returned to user ++ * context. ++ * When called in blocking mode, the userdata field points to a bulk_waiter ++ * structure. ++ */ ++VCHIQ_STATUS_T ++vchiq_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle, ++ VCHI_MEM_HANDLE_T memhandle, void *offset, int size, void *userdata, ++ VCHIQ_BULK_MODE_T mode, VCHIQ_BULK_DIR_T dir) ++{ ++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); ++ VCHIQ_BULK_QUEUE_T *queue; ++ VCHIQ_BULK_T *bulk; ++ VCHIQ_STATE_T *state; ++ struct bulk_waiter *bulk_waiter = NULL; ++ const char dir_char = (dir == VCHIQ_BULK_TRANSMIT) ? 't' : 'r'; ++ const int dir_msgtype = (dir == VCHIQ_BULK_TRANSMIT) ? ++ VCHIQ_MSG_BULK_TX : VCHIQ_MSG_BULK_RX; ++ VCHIQ_STATUS_T status = VCHIQ_ERROR; ++ ++ if (!service || ++ (service->srvstate != VCHIQ_SRVSTATE_OPEN) || ++ ((memhandle == VCHI_MEM_HANDLE_INVALID) && (offset == NULL)) || ++ (vchiq_check_service(service) != VCHIQ_SUCCESS)) ++ goto error_exit; ++ ++ switch (mode) { ++ case VCHIQ_BULK_MODE_NOCALLBACK: ++ case VCHIQ_BULK_MODE_CALLBACK: ++ break; ++ case VCHIQ_BULK_MODE_BLOCKING: ++ bulk_waiter = (struct bulk_waiter *)userdata; ++ sema_init(&bulk_waiter->event, 0); ++ bulk_waiter->actual = 0; ++ bulk_waiter->bulk = NULL; ++ break; ++ case VCHIQ_BULK_MODE_WAITING: ++ bulk_waiter = (struct bulk_waiter *)userdata; ++ bulk = bulk_waiter->bulk; ++ goto waiting; ++ default: ++ goto error_exit; ++ } ++ ++ state = service->state; ++ ++ queue = (dir == VCHIQ_BULK_TRANSMIT) ? ++ &service->bulk_tx : &service->bulk_rx; ++ ++ if (mutex_lock_interruptible(&service->bulk_mutex) != 0) { ++ status = VCHIQ_RETRY; ++ goto error_exit; ++ } ++ ++ if (queue->local_insert == queue->remove + VCHIQ_NUM_SERVICE_BULKS) { ++ VCHIQ_SERVICE_STATS_INC(service, bulk_stalls); ++ do { ++ mutex_unlock(&service->bulk_mutex); ++ if (down_interruptible(&service->bulk_remove_event) ++ != 0) { ++ status = VCHIQ_RETRY; ++ goto error_exit; ++ } ++ if (mutex_lock_interruptible(&service->bulk_mutex) ++ != 0) { ++ status = VCHIQ_RETRY; ++ goto error_exit; ++ } ++ } while (queue->local_insert == queue->remove + ++ VCHIQ_NUM_SERVICE_BULKS); ++ } ++ ++ bulk = &queue->bulks[BULK_INDEX(queue->local_insert)]; ++ ++ bulk->mode = mode; ++ bulk->dir = dir; ++ bulk->userdata = userdata; ++ bulk->size = size; ++ bulk->actual = VCHIQ_BULK_ACTUAL_ABORTED; ++ ++ if (vchiq_prepare_bulk_data(bulk, memhandle, offset, size, dir) != ++ VCHIQ_SUCCESS) ++ goto unlock_error_exit; ++ ++ wmb(); ++ ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: bt (%d->%d) %cx %x@%x %x", ++ state->id, ++ service->localport, service->remoteport, dir_char, ++ size, (unsigned int)bulk->data, (unsigned int)userdata); ++ ++ /* The slot mutex must be held when the service is being closed, so ++ claim it here to ensure that isn't happening */ ++ if (mutex_lock_interruptible(&state->slot_mutex) != 0) { ++ status = VCHIQ_RETRY; ++ goto cancel_bulk_error_exit; ++ } ++ ++ if (service->srvstate != VCHIQ_SRVSTATE_OPEN) ++ goto unlock_both_error_exit; ++ ++ if (state->is_master) { ++ queue->local_insert++; ++ if (resolve_bulks(service, queue)) ++ request_poll(state, service, ++ (dir == VCHIQ_BULK_TRANSMIT) ? ++ VCHIQ_POLL_TXNOTIFY : VCHIQ_POLL_RXNOTIFY); ++ } else { ++ int payload[2] = { (int)bulk->data, bulk->size }; ++ VCHIQ_ELEMENT_T element = { payload, sizeof(payload) }; ++ ++ status = queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(dir_msgtype, ++ service->localport, service->remoteport), ++ &element, 1, sizeof(payload), ++ QMFLAGS_IS_BLOCKING | ++ QMFLAGS_NO_MUTEX_LOCK | ++ QMFLAGS_NO_MUTEX_UNLOCK); ++ if (status != VCHIQ_SUCCESS) { ++ goto unlock_both_error_exit; ++ } ++ queue->local_insert++; ++ } ++ ++ mutex_unlock(&state->slot_mutex); ++ mutex_unlock(&service->bulk_mutex); ++ ++ vchiq_log_trace(vchiq_core_log_level, ++ "%d: bt:%d %cx li=%x ri=%x p=%x", ++ state->id, ++ service->localport, dir_char, ++ queue->local_insert, queue->remote_insert, queue->process); ++ ++waiting: ++ unlock_service(service); ++ ++ status = VCHIQ_SUCCESS; ++ ++ if (bulk_waiter) { ++ bulk_waiter->bulk = bulk; ++ if (down_interruptible(&bulk_waiter->event) != 0) ++ status = VCHIQ_RETRY; ++ else if (bulk_waiter->actual == VCHIQ_BULK_ACTUAL_ABORTED) ++ status = VCHIQ_ERROR; ++ } ++ ++ return status; ++ ++unlock_both_error_exit: ++ mutex_unlock(&state->slot_mutex); ++cancel_bulk_error_exit: ++ vchiq_complete_bulk(bulk); ++unlock_error_exit: ++ mutex_unlock(&service->bulk_mutex); ++ ++error_exit: ++ if (service) ++ unlock_service(service); ++ return status; ++} ++ ++VCHIQ_STATUS_T ++vchiq_queue_message(VCHIQ_SERVICE_HANDLE_T handle, ++ const VCHIQ_ELEMENT_T *elements, unsigned int count) ++{ ++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); ++ VCHIQ_STATUS_T status = VCHIQ_ERROR; ++ ++ unsigned int size = 0; ++ unsigned int i; ++ ++ if (!service || ++ (vchiq_check_service(service) != VCHIQ_SUCCESS)) ++ goto error_exit; ++ ++ for (i = 0; i < (unsigned int)count; i++) { ++ if (elements[i].size) { ++ if (elements[i].data == NULL) { ++ VCHIQ_SERVICE_STATS_INC(service, error_count); ++ goto error_exit; ++ } ++ size += elements[i].size; ++ } ++ } ++ ++ if (size > VCHIQ_MAX_MSG_SIZE) { ++ VCHIQ_SERVICE_STATS_INC(service, error_count); ++ goto error_exit; ++ } ++ ++ switch (service->srvstate) { ++ case VCHIQ_SRVSTATE_OPEN: ++ status = queue_message(service->state, service, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_DATA, ++ service->localport, ++ service->remoteport), ++ elements, count, size, 1); ++ break; ++ case VCHIQ_SRVSTATE_OPENSYNC: ++ status = queue_message_sync(service->state, service, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_DATA, ++ service->localport, ++ service->remoteport), ++ elements, count, size, 1); ++ break; ++ default: ++ status = VCHIQ_ERROR; ++ break; ++ } ++ ++error_exit: ++ if (service) ++ unlock_service(service); ++ ++ return status; ++} ++ ++void ++vchiq_release_message(VCHIQ_SERVICE_HANDLE_T handle, VCHIQ_HEADER_T *header) ++{ ++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); ++ VCHIQ_SHARED_STATE_T *remote; ++ VCHIQ_STATE_T *state; ++ int slot_index; ++ ++ if (!service) ++ return; ++ ++ state = service->state; ++ remote = state->remote; ++ ++ slot_index = SLOT_INDEX_FROM_DATA(state, (void *)header); ++ ++ if ((slot_index >= remote->slot_first) && ++ (slot_index <= remote->slot_last)) { ++ int msgid = header->msgid; ++ if (msgid & VCHIQ_MSGID_CLAIMED) { ++ VCHIQ_SLOT_INFO_T *slot_info = ++ SLOT_INFO_FROM_INDEX(state, slot_index); ++ ++ release_slot(state, slot_info, header, service); ++ } ++ } else if (slot_index == remote->slot_sync) ++ release_message_sync(state, header); ++ ++ unlock_service(service); ++} ++ ++static void ++release_message_sync(VCHIQ_STATE_T *state, VCHIQ_HEADER_T *header) ++{ ++ header->msgid = VCHIQ_MSGID_PADDING; ++ wmb(); ++ remote_event_signal(&state->remote->sync_release); ++} ++ ++VCHIQ_STATUS_T ++vchiq_get_peer_version(VCHIQ_SERVICE_HANDLE_T handle, short *peer_version) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_ERROR; ++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); ++ ++ if (!service || ++ (vchiq_check_service(service) != VCHIQ_SUCCESS) || ++ !peer_version) ++ goto exit; ++ *peer_version = service->peer_version; ++ status = VCHIQ_SUCCESS; ++ ++exit: ++ if (service) ++ unlock_service(service); ++ return status; ++} ++ ++VCHIQ_STATUS_T ++vchiq_get_config(VCHIQ_INSTANCE_T instance, ++ int config_size, VCHIQ_CONFIG_T *pconfig) ++{ ++ VCHIQ_CONFIG_T config; ++ ++ (void)instance; ++ ++ config.max_msg_size = VCHIQ_MAX_MSG_SIZE; ++ config.bulk_threshold = VCHIQ_MAX_MSG_SIZE; ++ config.max_outstanding_bulks = VCHIQ_NUM_SERVICE_BULKS; ++ config.max_services = VCHIQ_MAX_SERVICES; ++ config.version = VCHIQ_VERSION; ++ config.version_min = VCHIQ_VERSION_MIN; ++ ++ if (config_size > sizeof(VCHIQ_CONFIG_T)) ++ return VCHIQ_ERROR; ++ ++ memcpy(pconfig, &config, ++ min(config_size, (int)(sizeof(VCHIQ_CONFIG_T)))); ++ ++ return VCHIQ_SUCCESS; ++} ++ ++VCHIQ_STATUS_T ++vchiq_set_service_option(VCHIQ_SERVICE_HANDLE_T handle, ++ VCHIQ_SERVICE_OPTION_T option, int value) ++{ ++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); ++ VCHIQ_STATUS_T status = VCHIQ_ERROR; ++ ++ if (service) { ++ switch (option) { ++ case VCHIQ_SERVICE_OPTION_AUTOCLOSE: ++ service->auto_close = value; ++ status = VCHIQ_SUCCESS; ++ break; ++ ++ case VCHIQ_SERVICE_OPTION_SLOT_QUOTA: { ++ VCHIQ_SERVICE_QUOTA_T *service_quota = ++ &service->state->service_quotas[ ++ service->localport]; ++ if (value == 0) ++ value = service->state->default_slot_quota; ++ if ((value >= service_quota->slot_use_count) && ++ (value < (unsigned short)~0)) { ++ service_quota->slot_quota = value; ++ if ((value >= service_quota->slot_use_count) && ++ (service_quota->message_quota >= ++ service_quota->message_use_count)) { ++ /* Signal the service that it may have ++ ** dropped below its quota */ ++ up(&service_quota->quota_event); ++ } ++ status = VCHIQ_SUCCESS; ++ } ++ } break; ++ ++ case VCHIQ_SERVICE_OPTION_MESSAGE_QUOTA: { ++ VCHIQ_SERVICE_QUOTA_T *service_quota = ++ &service->state->service_quotas[ ++ service->localport]; ++ if (value == 0) ++ value = service->state->default_message_quota; ++ if ((value >= service_quota->message_use_count) && ++ (value < (unsigned short)~0)) { ++ service_quota->message_quota = value; ++ if ((value >= ++ service_quota->message_use_count) && ++ (service_quota->slot_quota >= ++ service_quota->slot_use_count)) ++ /* Signal the service that it may have ++ ** dropped below its quota */ ++ up(&service_quota->quota_event); ++ status = VCHIQ_SUCCESS; ++ } ++ } break; ++ ++ case VCHIQ_SERVICE_OPTION_SYNCHRONOUS: ++ if ((service->srvstate == VCHIQ_SRVSTATE_HIDDEN) || ++ (service->srvstate == ++ VCHIQ_SRVSTATE_LISTENING)) { ++ service->sync = value; ++ status = VCHIQ_SUCCESS; ++ } ++ break; ++ ++ case VCHIQ_SERVICE_OPTION_TRACE: ++ service->trace = value; ++ status = VCHIQ_SUCCESS; ++ break; ++ ++ default: ++ break; ++ } ++ unlock_service(service); ++ } ++ ++ return status; ++} ++ ++void ++vchiq_dump_shared_state(void *dump_context, VCHIQ_STATE_T *state, ++ VCHIQ_SHARED_STATE_T *shared, const char *label) ++{ ++ static const char *const debug_names[] = { ++ "", ++ "SLOT_HANDLER_COUNT", ++ "SLOT_HANDLER_LINE", ++ "PARSE_LINE", ++ "PARSE_HEADER", ++ "PARSE_MSGID", ++ "AWAIT_COMPLETION_LINE", ++ "DEQUEUE_MESSAGE_LINE", ++ "SERVICE_CALLBACK_LINE", ++ "MSG_QUEUE_FULL_COUNT", ++ "COMPLETION_QUEUE_FULL_COUNT" ++ }; ++ int i; ++ ++ char buf[80]; ++ int len; ++ len = snprintf(buf, sizeof(buf), ++ " %s: slots %d-%d tx_pos=%x recycle=%x", ++ label, shared->slot_first, shared->slot_last, ++ shared->tx_pos, shared->slot_queue_recycle); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ len = snprintf(buf, sizeof(buf), ++ " Slots claimed:"); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ for (i = shared->slot_first; i <= shared->slot_last; i++) { ++ VCHIQ_SLOT_INFO_T slot_info = *SLOT_INFO_FROM_INDEX(state, i); ++ if (slot_info.use_count != slot_info.release_count) { ++ len = snprintf(buf, sizeof(buf), ++ " %d: %d/%d", i, slot_info.use_count, ++ slot_info.release_count); ++ vchiq_dump(dump_context, buf, len + 1); ++ } ++ } ++ ++ for (i = 1; i < shared->debug[DEBUG_ENTRIES]; i++) { ++ len = snprintf(buf, sizeof(buf), " DEBUG: %s = %d(%x)", ++ debug_names[i], shared->debug[i], shared->debug[i]); ++ vchiq_dump(dump_context, buf, len + 1); ++ } ++} ++ ++void ++vchiq_dump_state(void *dump_context, VCHIQ_STATE_T *state) ++{ ++ char buf[80]; ++ int len; ++ int i; ++ ++ len = snprintf(buf, sizeof(buf), "State %d: %s", state->id, ++ conn_state_names[state->conn_state]); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ len = snprintf(buf, sizeof(buf), ++ " tx_pos=%x(@%x), rx_pos=%x(@%x)", ++ state->local->tx_pos, ++ (uint32_t)state->tx_data + ++ (state->local_tx_pos & VCHIQ_SLOT_MASK), ++ state->rx_pos, ++ (uint32_t)state->rx_data + ++ (state->rx_pos & VCHIQ_SLOT_MASK)); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ len = snprintf(buf, sizeof(buf), ++ " Version: %d (min %d)", ++ VCHIQ_VERSION, VCHIQ_VERSION_MIN); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ if (VCHIQ_ENABLE_STATS) { ++ len = snprintf(buf, sizeof(buf), ++ " Stats: ctrl_tx_count=%d, ctrl_rx_count=%d, " ++ "error_count=%d", ++ state->stats.ctrl_tx_count, state->stats.ctrl_rx_count, ++ state->stats.error_count); ++ vchiq_dump(dump_context, buf, len + 1); ++ } ++ ++ len = snprintf(buf, sizeof(buf), ++ " Slots: %d available (%d data), %d recyclable, %d stalls " ++ "(%d data)", ++ ((state->slot_queue_available * VCHIQ_SLOT_SIZE) - ++ state->local_tx_pos) / VCHIQ_SLOT_SIZE, ++ state->data_quota - state->data_use_count, ++ state->local->slot_queue_recycle - state->slot_queue_available, ++ state->stats.slot_stalls, state->stats.data_stalls); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ vchiq_dump_platform_state(dump_context); ++ ++ vchiq_dump_shared_state(dump_context, state, state->local, "Local"); ++ vchiq_dump_shared_state(dump_context, state, state->remote, "Remote"); ++ ++ vchiq_dump_platform_instances(dump_context); ++ ++ for (i = 0; i < state->unused_service; i++) { ++ VCHIQ_SERVICE_T *service = find_service_by_port(state, i); ++ ++ if (service) { ++ vchiq_dump_service_state(dump_context, service); ++ unlock_service(service); ++ } ++ } ++} ++ ++void ++vchiq_dump_service_state(void *dump_context, VCHIQ_SERVICE_T *service) ++{ ++ char buf[80]; ++ int len; ++ ++ len = snprintf(buf, sizeof(buf), "Service %d: %s (ref %u)", ++ service->localport, srvstate_names[service->srvstate], ++ service->ref_count - 1); /*Don't include the lock just taken*/ ++ ++ if (service->srvstate != VCHIQ_SRVSTATE_FREE) { ++ char remoteport[30]; ++ VCHIQ_SERVICE_QUOTA_T *service_quota = ++ &service->state->service_quotas[service->localport]; ++ int fourcc = service->base.fourcc; ++ int tx_pending, rx_pending; ++ if (service->remoteport != VCHIQ_PORT_FREE) { ++ int len2 = snprintf(remoteport, sizeof(remoteport), ++ "%d", service->remoteport); ++ if (service->public_fourcc != VCHIQ_FOURCC_INVALID) ++ snprintf(remoteport + len2, ++ sizeof(remoteport) - len2, ++ " (client %x)", service->client_id); ++ } else ++ strcpy(remoteport, "n/a"); ++ ++ len += snprintf(buf + len, sizeof(buf) - len, ++ " '%c%c%c%c' remote %s (msg use %d/%d, slot use %d/%d)", ++ VCHIQ_FOURCC_AS_4CHARS(fourcc), ++ remoteport, ++ service_quota->message_use_count, ++ service_quota->message_quota, ++ service_quota->slot_use_count, ++ service_quota->slot_quota); ++ ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ tx_pending = service->bulk_tx.local_insert - ++ service->bulk_tx.remote_insert; ++ ++ rx_pending = service->bulk_rx.local_insert - ++ service->bulk_rx.remote_insert; ++ ++ len = snprintf(buf, sizeof(buf), ++ " Bulk: tx_pending=%d (size %d)," ++ " rx_pending=%d (size %d)", ++ tx_pending, ++ tx_pending ? service->bulk_tx.bulks[ ++ BULK_INDEX(service->bulk_tx.remove)].size : 0, ++ rx_pending, ++ rx_pending ? service->bulk_rx.bulks[ ++ BULK_INDEX(service->bulk_rx.remove)].size : 0); ++ ++ if (VCHIQ_ENABLE_STATS) { ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ len = snprintf(buf, sizeof(buf), ++ " Ctrl: tx_count=%d, tx_bytes=%llu, " ++ "rx_count=%d, rx_bytes=%llu", ++ service->stats.ctrl_tx_count, ++ service->stats.ctrl_tx_bytes, ++ service->stats.ctrl_rx_count, ++ service->stats.ctrl_rx_bytes); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ len = snprintf(buf, sizeof(buf), ++ " Bulk: tx_count=%d, tx_bytes=%llu, " ++ "rx_count=%d, rx_bytes=%llu", ++ service->stats.bulk_tx_count, ++ service->stats.bulk_tx_bytes, ++ service->stats.bulk_rx_count, ++ service->stats.bulk_rx_bytes); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ len = snprintf(buf, sizeof(buf), ++ " %d quota stalls, %d slot stalls, " ++ "%d bulk stalls, %d aborted, %d errors", ++ service->stats.quota_stalls, ++ service->stats.slot_stalls, ++ service->stats.bulk_stalls, ++ service->stats.bulk_aborted_count, ++ service->stats.error_count); ++ } ++ } ++ ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ if (service->srvstate != VCHIQ_SRVSTATE_FREE) ++ vchiq_dump_platform_service_state(dump_context, service); ++} ++ ++ ++void ++vchiq_loud_error_header(void) ++{ ++ vchiq_log_error(vchiq_core_log_level, ++ "============================================================" ++ "================"); ++ vchiq_log_error(vchiq_core_log_level, ++ "============================================================" ++ "================"); ++ vchiq_log_error(vchiq_core_log_level, "====="); ++} ++ ++void ++vchiq_loud_error_footer(void) ++{ ++ vchiq_log_error(vchiq_core_log_level, "====="); ++ vchiq_log_error(vchiq_core_log_level, ++ "============================================================" ++ "================"); ++ vchiq_log_error(vchiq_core_log_level, ++ "============================================================" ++ "================"); ++} ++ ++ ++VCHIQ_STATUS_T vchiq_send_remote_use(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_RETRY; ++ if (state->conn_state != VCHIQ_CONNSTATE_DISCONNECTED) ++ status = queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_USE, 0, 0), ++ NULL, 0, 0, 0); ++ return status; ++} ++ ++VCHIQ_STATUS_T vchiq_send_remote_release(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_RETRY; ++ if (state->conn_state != VCHIQ_CONNSTATE_DISCONNECTED) ++ status = queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_RELEASE, 0, 0), ++ NULL, 0, 0, 0); ++ return status; ++} ++ ++VCHIQ_STATUS_T vchiq_send_remote_use_active(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_RETRY; ++ if (state->conn_state != VCHIQ_CONNSTATE_DISCONNECTED) ++ status = queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_USE_ACTIVE, 0, 0), ++ NULL, 0, 0, 0); ++ return status; ++} ++ ++void vchiq_log_dump_mem(const char *label, uint32_t addr, const void *voidMem, ++ size_t numBytes) ++{ ++ const uint8_t *mem = (const uint8_t *)voidMem; ++ size_t offset; ++ char lineBuf[100]; ++ char *s; ++ ++ while (numBytes > 0) { ++ s = lineBuf; ++ ++ for (offset = 0; offset < 16; offset++) { ++ if (offset < numBytes) ++ s += snprintf(s, 4, "%02x ", mem[offset]); ++ else ++ s += snprintf(s, 4, " "); ++ } ++ ++ for (offset = 0; offset < 16; offset++) { ++ if (offset < numBytes) { ++ uint8_t ch = mem[offset]; ++ ++ if ((ch < ' ') || (ch > '~')) ++ ch = '.'; ++ *s++ = (char)ch; ++ } ++ } ++ *s++ = '\0'; ++ ++ if ((label != NULL) && (*label != '\0')) ++ vchiq_log_trace(VCHIQ_LOG_TRACE, ++ "%s: %08x: %s", label, addr, lineBuf); ++ else ++ vchiq_log_trace(VCHIQ_LOG_TRACE, ++ "%08x: %s", addr, lineBuf); ++ ++ addr += 16; ++ mem += 16; ++ if (numBytes > 16) ++ numBytes -= 16; ++ else ++ numBytes = 0; ++ } ++} +diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h +--- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h 2015-11-29 09:42:38.075221210 +0100 +@@ -0,0 +1,712 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHIQ_CORE_H ++#define VCHIQ_CORE_H ++ ++#include ++#include ++#include ++ ++#include "vchiq_cfg.h" ++ ++#include "vchiq.h" ++ ++/* Run time control of log level, based on KERN_XXX level. */ ++#define VCHIQ_LOG_DEFAULT 4 ++#define VCHIQ_LOG_ERROR 3 ++#define VCHIQ_LOG_WARNING 4 ++#define VCHIQ_LOG_INFO 6 ++#define VCHIQ_LOG_TRACE 7 ++ ++#define VCHIQ_LOG_PREFIX KERN_INFO "vchiq: " ++ ++#ifndef vchiq_log_error ++#define vchiq_log_error(cat, fmt, ...) \ ++ do { if (cat >= VCHIQ_LOG_ERROR) \ ++ printk(VCHIQ_LOG_PREFIX fmt "\n", ##__VA_ARGS__); } while (0) ++#endif ++#ifndef vchiq_log_warning ++#define vchiq_log_warning(cat, fmt, ...) \ ++ do { if (cat >= VCHIQ_LOG_WARNING) \ ++ printk(VCHIQ_LOG_PREFIX fmt "\n", ##__VA_ARGS__); } while (0) ++#endif ++#ifndef vchiq_log_info ++#define vchiq_log_info(cat, fmt, ...) \ ++ do { if (cat >= VCHIQ_LOG_INFO) \ ++ printk(VCHIQ_LOG_PREFIX fmt "\n", ##__VA_ARGS__); } while (0) ++#endif ++#ifndef vchiq_log_trace ++#define vchiq_log_trace(cat, fmt, ...) \ ++ do { if (cat >= VCHIQ_LOG_TRACE) \ ++ printk(VCHIQ_LOG_PREFIX fmt "\n", ##__VA_ARGS__); } while (0) ++#endif ++ ++#define vchiq_loud_error(...) \ ++ vchiq_log_error(vchiq_core_log_level, "===== " __VA_ARGS__) ++ ++#ifndef vchiq_static_assert ++#define vchiq_static_assert(cond) __attribute__((unused)) \ ++ extern int vchiq_static_assert[(cond) ? 1 : -1] ++#endif ++ ++#define IS_POW2(x) (x && ((x & (x - 1)) == 0)) ++ ++/* Ensure that the slot size and maximum number of slots are powers of 2 */ ++vchiq_static_assert(IS_POW2(VCHIQ_SLOT_SIZE)); ++vchiq_static_assert(IS_POW2(VCHIQ_MAX_SLOTS)); ++vchiq_static_assert(IS_POW2(VCHIQ_MAX_SLOTS_PER_SIDE)); ++ ++#define VCHIQ_SLOT_MASK (VCHIQ_SLOT_SIZE - 1) ++#define VCHIQ_SLOT_QUEUE_MASK (VCHIQ_MAX_SLOTS_PER_SIDE - 1) ++#define VCHIQ_SLOT_ZERO_SLOTS ((sizeof(VCHIQ_SLOT_ZERO_T) + \ ++ VCHIQ_SLOT_SIZE - 1) / VCHIQ_SLOT_SIZE) ++ ++#define VCHIQ_MSG_PADDING 0 /* - */ ++#define VCHIQ_MSG_CONNECT 1 /* - */ ++#define VCHIQ_MSG_OPEN 2 /* + (srcport, -), fourcc, client_id */ ++#define VCHIQ_MSG_OPENACK 3 /* + (srcport, dstport) */ ++#define VCHIQ_MSG_CLOSE 4 /* + (srcport, dstport) */ ++#define VCHIQ_MSG_DATA 5 /* + (srcport, dstport) */ ++#define VCHIQ_MSG_BULK_RX 6 /* + (srcport, dstport), data, size */ ++#define VCHIQ_MSG_BULK_TX 7 /* + (srcport, dstport), data, size */ ++#define VCHIQ_MSG_BULK_RX_DONE 8 /* + (srcport, dstport), actual */ ++#define VCHIQ_MSG_BULK_TX_DONE 9 /* + (srcport, dstport), actual */ ++#define VCHIQ_MSG_PAUSE 10 /* - */ ++#define VCHIQ_MSG_RESUME 11 /* - */ ++#define VCHIQ_MSG_REMOTE_USE 12 /* - */ ++#define VCHIQ_MSG_REMOTE_RELEASE 13 /* - */ ++#define VCHIQ_MSG_REMOTE_USE_ACTIVE 14 /* - */ ++ ++#define VCHIQ_PORT_MAX (VCHIQ_MAX_SERVICES - 1) ++#define VCHIQ_PORT_FREE 0x1000 ++#define VCHIQ_PORT_IS_VALID(port) (port < VCHIQ_PORT_FREE) ++#define VCHIQ_MAKE_MSG(type, srcport, dstport) \ ++ ((type<<24) | (srcport<<12) | (dstport<<0)) ++#define VCHIQ_MSG_TYPE(msgid) ((unsigned int)msgid >> 24) ++#define VCHIQ_MSG_SRCPORT(msgid) \ ++ (unsigned short)(((unsigned int)msgid >> 12) & 0xfff) ++#define VCHIQ_MSG_DSTPORT(msgid) \ ++ ((unsigned short)msgid & 0xfff) ++ ++#define VCHIQ_FOURCC_AS_4CHARS(fourcc) \ ++ ((fourcc) >> 24) & 0xff, \ ++ ((fourcc) >> 16) & 0xff, \ ++ ((fourcc) >> 8) & 0xff, \ ++ (fourcc) & 0xff ++ ++/* Ensure the fields are wide enough */ ++vchiq_static_assert(VCHIQ_MSG_SRCPORT(VCHIQ_MAKE_MSG(0, 0, VCHIQ_PORT_MAX)) ++ == 0); ++vchiq_static_assert(VCHIQ_MSG_TYPE(VCHIQ_MAKE_MSG(0, VCHIQ_PORT_MAX, 0)) == 0); ++vchiq_static_assert((unsigned int)VCHIQ_PORT_MAX < ++ (unsigned int)VCHIQ_PORT_FREE); ++ ++#define VCHIQ_MSGID_PADDING VCHIQ_MAKE_MSG(VCHIQ_MSG_PADDING, 0, 0) ++#define VCHIQ_MSGID_CLAIMED 0x40000000 ++ ++#define VCHIQ_FOURCC_INVALID 0x00000000 ++#define VCHIQ_FOURCC_IS_LEGAL(fourcc) (fourcc != VCHIQ_FOURCC_INVALID) ++ ++#define VCHIQ_BULK_ACTUAL_ABORTED -1 ++ ++typedef uint32_t BITSET_T; ++ ++vchiq_static_assert((sizeof(BITSET_T) * 8) == 32); ++ ++#define BITSET_SIZE(b) ((b + 31) >> 5) ++#define BITSET_WORD(b) (b >> 5) ++#define BITSET_BIT(b) (1 << (b & 31)) ++#define BITSET_ZERO(bs) memset(bs, 0, sizeof(bs)) ++#define BITSET_IS_SET(bs, b) (bs[BITSET_WORD(b)] & BITSET_BIT(b)) ++#define BITSET_SET(bs, b) (bs[BITSET_WORD(b)] |= BITSET_BIT(b)) ++#define BITSET_CLR(bs, b) (bs[BITSET_WORD(b)] &= ~BITSET_BIT(b)) ++ ++#if VCHIQ_ENABLE_STATS ++#define VCHIQ_STATS_INC(state, stat) (state->stats. stat++) ++#define VCHIQ_SERVICE_STATS_INC(service, stat) (service->stats. stat++) ++#define VCHIQ_SERVICE_STATS_ADD(service, stat, addend) \ ++ (service->stats. stat += addend) ++#else ++#define VCHIQ_STATS_INC(state, stat) ((void)0) ++#define VCHIQ_SERVICE_STATS_INC(service, stat) ((void)0) ++#define VCHIQ_SERVICE_STATS_ADD(service, stat, addend) ((void)0) ++#endif ++ ++enum { ++ DEBUG_ENTRIES, ++#if VCHIQ_ENABLE_DEBUG ++ DEBUG_SLOT_HANDLER_COUNT, ++ DEBUG_SLOT_HANDLER_LINE, ++ DEBUG_PARSE_LINE, ++ DEBUG_PARSE_HEADER, ++ DEBUG_PARSE_MSGID, ++ DEBUG_AWAIT_COMPLETION_LINE, ++ DEBUG_DEQUEUE_MESSAGE_LINE, ++ DEBUG_SERVICE_CALLBACK_LINE, ++ DEBUG_MSG_QUEUE_FULL_COUNT, ++ DEBUG_COMPLETION_QUEUE_FULL_COUNT, ++#endif ++ DEBUG_MAX ++}; ++ ++#if VCHIQ_ENABLE_DEBUG ++ ++#define DEBUG_INITIALISE(local) int *debug_ptr = (local)->debug; ++#define DEBUG_TRACE(d) \ ++ do { debug_ptr[DEBUG_ ## d] = __LINE__; dsb(); } while (0) ++#define DEBUG_VALUE(d, v) \ ++ do { debug_ptr[DEBUG_ ## d] = (v); dsb(); } while (0) ++#define DEBUG_COUNT(d) \ ++ do { debug_ptr[DEBUG_ ## d]++; dsb(); } while (0) ++ ++#else /* VCHIQ_ENABLE_DEBUG */ ++ ++#define DEBUG_INITIALISE(local) ++#define DEBUG_TRACE(d) ++#define DEBUG_VALUE(d, v) ++#define DEBUG_COUNT(d) ++ ++#endif /* VCHIQ_ENABLE_DEBUG */ ++ ++typedef enum { ++ VCHIQ_CONNSTATE_DISCONNECTED, ++ VCHIQ_CONNSTATE_CONNECTING, ++ VCHIQ_CONNSTATE_CONNECTED, ++ VCHIQ_CONNSTATE_PAUSING, ++ VCHIQ_CONNSTATE_PAUSE_SENT, ++ VCHIQ_CONNSTATE_PAUSED, ++ VCHIQ_CONNSTATE_RESUMING, ++ VCHIQ_CONNSTATE_PAUSE_TIMEOUT, ++ VCHIQ_CONNSTATE_RESUME_TIMEOUT ++} VCHIQ_CONNSTATE_T; ++ ++enum { ++ VCHIQ_SRVSTATE_FREE, ++ VCHIQ_SRVSTATE_HIDDEN, ++ VCHIQ_SRVSTATE_LISTENING, ++ VCHIQ_SRVSTATE_OPENING, ++ VCHIQ_SRVSTATE_OPEN, ++ VCHIQ_SRVSTATE_OPENSYNC, ++ VCHIQ_SRVSTATE_CLOSESENT, ++ VCHIQ_SRVSTATE_CLOSERECVD, ++ VCHIQ_SRVSTATE_CLOSEWAIT, ++ VCHIQ_SRVSTATE_CLOSED ++}; ++ ++enum { ++ VCHIQ_POLL_TERMINATE, ++ VCHIQ_POLL_REMOVE, ++ VCHIQ_POLL_TXNOTIFY, ++ VCHIQ_POLL_RXNOTIFY, ++ VCHIQ_POLL_COUNT ++}; ++ ++typedef enum { ++ VCHIQ_BULK_TRANSMIT, ++ VCHIQ_BULK_RECEIVE ++} VCHIQ_BULK_DIR_T; ++ ++typedef void (*VCHIQ_USERDATA_TERM_T)(void *userdata); ++ ++typedef struct vchiq_bulk_struct { ++ short mode; ++ short dir; ++ void *userdata; ++ VCHI_MEM_HANDLE_T handle; ++ void *data; ++ int size; ++ void *remote_data; ++ int remote_size; ++ int actual; ++} VCHIQ_BULK_T; ++ ++typedef struct vchiq_bulk_queue_struct { ++ int local_insert; /* Where to insert the next local bulk */ ++ int remote_insert; /* Where to insert the next remote bulk (master) */ ++ int process; /* Bulk to transfer next */ ++ int remote_notify; /* Bulk to notify the remote client of next (mstr) */ ++ int remove; /* Bulk to notify the local client of, and remove, ++ ** next */ ++ VCHIQ_BULK_T bulks[VCHIQ_NUM_SERVICE_BULKS]; ++} VCHIQ_BULK_QUEUE_T; ++ ++typedef struct remote_event_struct { ++ int armed; ++ int fired; ++ struct semaphore *event; ++} REMOTE_EVENT_T; ++ ++typedef struct opaque_platform_state_t *VCHIQ_PLATFORM_STATE_T; ++ ++typedef struct vchiq_state_struct VCHIQ_STATE_T; ++ ++typedef struct vchiq_slot_struct { ++ char data[VCHIQ_SLOT_SIZE]; ++} VCHIQ_SLOT_T; ++ ++typedef struct vchiq_slot_info_struct { ++ /* Use two counters rather than one to avoid the need for a mutex. */ ++ short use_count; ++ short release_count; ++} VCHIQ_SLOT_INFO_T; ++ ++typedef struct vchiq_service_struct { ++ VCHIQ_SERVICE_BASE_T base; ++ VCHIQ_SERVICE_HANDLE_T handle; ++ unsigned int ref_count; ++ int srvstate; ++ VCHIQ_USERDATA_TERM_T userdata_term; ++ unsigned int localport; ++ unsigned int remoteport; ++ int public_fourcc; ++ int client_id; ++ char auto_close; ++ char sync; ++ char closing; ++ char trace; ++ atomic_t poll_flags; ++ short version; ++ short version_min; ++ short peer_version; ++ ++ VCHIQ_STATE_T *state; ++ VCHIQ_INSTANCE_T instance; ++ ++ int service_use_count; ++ ++ VCHIQ_BULK_QUEUE_T bulk_tx; ++ VCHIQ_BULK_QUEUE_T bulk_rx; ++ ++ struct semaphore remove_event; ++ struct semaphore bulk_remove_event; ++ struct mutex bulk_mutex; ++ ++ struct service_stats_struct { ++ int quota_stalls; ++ int slot_stalls; ++ int bulk_stalls; ++ int error_count; ++ int ctrl_tx_count; ++ int ctrl_rx_count; ++ int bulk_tx_count; ++ int bulk_rx_count; ++ int bulk_aborted_count; ++ uint64_t ctrl_tx_bytes; ++ uint64_t ctrl_rx_bytes; ++ uint64_t bulk_tx_bytes; ++ uint64_t bulk_rx_bytes; ++ } stats; ++} VCHIQ_SERVICE_T; ++ ++/* The quota information is outside VCHIQ_SERVICE_T so that it can be ++ statically allocated, since for accounting reasons a service's slot ++ usage is carried over between users of the same port number. ++ */ ++typedef struct vchiq_service_quota_struct { ++ unsigned short slot_quota; ++ unsigned short slot_use_count; ++ unsigned short message_quota; ++ unsigned short message_use_count; ++ struct semaphore quota_event; ++ int previous_tx_index; ++} VCHIQ_SERVICE_QUOTA_T; ++ ++typedef struct vchiq_shared_state_struct { ++ ++ /* A non-zero value here indicates that the content is valid. */ ++ int initialised; ++ ++ /* The first and last (inclusive) slots allocated to the owner. */ ++ int slot_first; ++ int slot_last; ++ ++ /* The slot allocated to synchronous messages from the owner. */ ++ int slot_sync; ++ ++ /* Signalling this event indicates that owner's slot handler thread ++ ** should run. */ ++ REMOTE_EVENT_T trigger; ++ ++ /* Indicates the byte position within the stream where the next message ++ ** will be written. The least significant bits are an index into the ++ ** slot. The next bits are the index of the slot in slot_queue. */ ++ int tx_pos; ++ ++ /* This event should be signalled when a slot is recycled. */ ++ REMOTE_EVENT_T recycle; ++ ++ /* The slot_queue index where the next recycled slot will be written. */ ++ int slot_queue_recycle; ++ ++ /* This event should be signalled when a synchronous message is sent. */ ++ REMOTE_EVENT_T sync_trigger; ++ ++ /* This event should be signalled when a synchronous message has been ++ ** released. */ ++ REMOTE_EVENT_T sync_release; ++ ++ /* A circular buffer of slot indexes. */ ++ int slot_queue[VCHIQ_MAX_SLOTS_PER_SIDE]; ++ ++ /* Debugging state */ ++ int debug[DEBUG_MAX]; ++} VCHIQ_SHARED_STATE_T; ++ ++typedef struct vchiq_slot_zero_struct { ++ int magic; ++ short version; ++ short version_min; ++ int slot_zero_size; ++ int slot_size; ++ int max_slots; ++ int max_slots_per_side; ++ int platform_data[2]; ++ VCHIQ_SHARED_STATE_T master; ++ VCHIQ_SHARED_STATE_T slave; ++ VCHIQ_SLOT_INFO_T slots[VCHIQ_MAX_SLOTS]; ++} VCHIQ_SLOT_ZERO_T; ++ ++struct vchiq_state_struct { ++ int id; ++ int initialised; ++ VCHIQ_CONNSTATE_T conn_state; ++ int is_master; ++ short version_common; ++ ++ VCHIQ_SHARED_STATE_T *local; ++ VCHIQ_SHARED_STATE_T *remote; ++ VCHIQ_SLOT_T *slot_data; ++ ++ unsigned short default_slot_quota; ++ unsigned short default_message_quota; ++ ++ /* Event indicating connect message received */ ++ struct semaphore connect; ++ ++ /* Mutex protecting services */ ++ struct mutex mutex; ++ VCHIQ_INSTANCE_T *instance; ++ ++ /* Processes incoming messages */ ++ struct task_struct *slot_handler_thread; ++ ++ /* Processes recycled slots */ ++ struct task_struct *recycle_thread; ++ ++ /* Processes synchronous messages */ ++ struct task_struct *sync_thread; ++ ++ /* Local implementation of the trigger remote event */ ++ struct semaphore trigger_event; ++ ++ /* Local implementation of the recycle remote event */ ++ struct semaphore recycle_event; ++ ++ /* Local implementation of the sync trigger remote event */ ++ struct semaphore sync_trigger_event; ++ ++ /* Local implementation of the sync release remote event */ ++ struct semaphore sync_release_event; ++ ++ char *tx_data; ++ char *rx_data; ++ VCHIQ_SLOT_INFO_T *rx_info; ++ ++ struct mutex slot_mutex; ++ ++ struct mutex recycle_mutex; ++ ++ struct mutex sync_mutex; ++ ++ struct mutex bulk_transfer_mutex; ++ ++ /* Indicates the byte position within the stream from where the next ++ ** message will be read. The least significant bits are an index into ++ ** the slot.The next bits are the index of the slot in ++ ** remote->slot_queue. */ ++ int rx_pos; ++ ++ /* A cached copy of local->tx_pos. Only write to local->tx_pos, and read ++ from remote->tx_pos. */ ++ int local_tx_pos; ++ ++ /* The slot_queue index of the slot to become available next. */ ++ int slot_queue_available; ++ ++ /* A flag to indicate if any poll has been requested */ ++ int poll_needed; ++ ++ /* Ths index of the previous slot used for data messages. */ ++ int previous_data_index; ++ ++ /* The number of slots occupied by data messages. */ ++ unsigned short data_use_count; ++ ++ /* The maximum number of slots to be occupied by data messages. */ ++ unsigned short data_quota; ++ ++ /* An array of bit sets indicating which services must be polled. */ ++ atomic_t poll_services[BITSET_SIZE(VCHIQ_MAX_SERVICES)]; ++ ++ /* The number of the first unused service */ ++ int unused_service; ++ ++ /* Signalled when a free slot becomes available. */ ++ struct semaphore slot_available_event; ++ ++ struct semaphore slot_remove_event; ++ ++ /* Signalled when a free data slot becomes available. */ ++ struct semaphore data_quota_event; ++ ++ /* Incremented when there are bulk transfers which cannot be processed ++ * whilst paused and must be processed on resume */ ++ int deferred_bulks; ++ ++ struct state_stats_struct { ++ int slot_stalls; ++ int data_stalls; ++ int ctrl_tx_count; ++ int ctrl_rx_count; ++ int error_count; ++ } stats; ++ ++ VCHIQ_SERVICE_T * services[VCHIQ_MAX_SERVICES]; ++ VCHIQ_SERVICE_QUOTA_T service_quotas[VCHIQ_MAX_SERVICES]; ++ VCHIQ_SLOT_INFO_T slot_info[VCHIQ_MAX_SLOTS]; ++ ++ VCHIQ_PLATFORM_STATE_T platform_state; ++}; ++ ++struct bulk_waiter { ++ VCHIQ_BULK_T *bulk; ++ struct semaphore event; ++ int actual; ++}; ++ ++extern spinlock_t bulk_waiter_spinlock; ++ ++extern int vchiq_core_log_level; ++extern int vchiq_core_msg_log_level; ++extern int vchiq_sync_log_level; ++ ++extern VCHIQ_STATE_T *vchiq_states[VCHIQ_MAX_STATES]; ++ ++extern const char * ++get_conn_state_name(VCHIQ_CONNSTATE_T conn_state); ++ ++extern VCHIQ_SLOT_ZERO_T * ++vchiq_init_slots(void *mem_base, int mem_size); ++ ++extern VCHIQ_STATUS_T ++vchiq_init_state(VCHIQ_STATE_T *state, VCHIQ_SLOT_ZERO_T *slot_zero, ++ int is_master); ++ ++extern VCHIQ_STATUS_T ++vchiq_connect_internal(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance); ++ ++extern VCHIQ_SERVICE_T * ++vchiq_add_service_internal(VCHIQ_STATE_T *state, ++ const VCHIQ_SERVICE_PARAMS_T *params, int srvstate, ++ VCHIQ_INSTANCE_T instance, VCHIQ_USERDATA_TERM_T userdata_term); ++ ++extern VCHIQ_STATUS_T ++vchiq_open_service_internal(VCHIQ_SERVICE_T *service, int client_id); ++ ++extern VCHIQ_STATUS_T ++vchiq_close_service_internal(VCHIQ_SERVICE_T *service, int close_recvd); ++ ++extern void ++vchiq_terminate_service_internal(VCHIQ_SERVICE_T *service); ++ ++extern void ++vchiq_free_service_internal(VCHIQ_SERVICE_T *service); ++ ++extern VCHIQ_STATUS_T ++vchiq_shutdown_internal(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance); ++ ++extern VCHIQ_STATUS_T ++vchiq_pause_internal(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATUS_T ++vchiq_resume_internal(VCHIQ_STATE_T *state); ++ ++extern void ++remote_event_pollall(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATUS_T ++vchiq_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle, ++ VCHI_MEM_HANDLE_T memhandle, void *offset, int size, void *userdata, ++ VCHIQ_BULK_MODE_T mode, VCHIQ_BULK_DIR_T dir); ++ ++extern void ++vchiq_dump_state(void *dump_context, VCHIQ_STATE_T *state); ++ ++extern void ++vchiq_dump_service_state(void *dump_context, VCHIQ_SERVICE_T *service); ++ ++extern void ++vchiq_loud_error_header(void); ++ ++extern void ++vchiq_loud_error_footer(void); ++ ++extern void ++request_poll(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, int poll_type); ++ ++static inline VCHIQ_SERVICE_T * ++handle_to_service(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ VCHIQ_STATE_T *state = vchiq_states[(handle / VCHIQ_MAX_SERVICES) & ++ (VCHIQ_MAX_STATES - 1)]; ++ if (!state) ++ return NULL; ++ ++ return state->services[handle & (VCHIQ_MAX_SERVICES - 1)]; ++} ++ ++extern VCHIQ_SERVICE_T * ++find_service_by_handle(VCHIQ_SERVICE_HANDLE_T handle); ++ ++extern VCHIQ_SERVICE_T * ++find_service_by_port(VCHIQ_STATE_T *state, int localport); ++ ++extern VCHIQ_SERVICE_T * ++find_service_for_instance(VCHIQ_INSTANCE_T instance, ++ VCHIQ_SERVICE_HANDLE_T handle); ++ ++extern VCHIQ_SERVICE_T * ++find_closed_service_for_instance(VCHIQ_INSTANCE_T instance, ++ VCHIQ_SERVICE_HANDLE_T handle); ++ ++extern VCHIQ_SERVICE_T * ++next_service_by_instance(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance, ++ int *pidx); ++ ++extern void ++lock_service(VCHIQ_SERVICE_T *service); ++ ++extern void ++unlock_service(VCHIQ_SERVICE_T *service); ++ ++/* The following functions are called from vchiq_core, and external ++** implementations must be provided. */ ++ ++extern VCHIQ_STATUS_T ++vchiq_prepare_bulk_data(VCHIQ_BULK_T *bulk, ++ VCHI_MEM_HANDLE_T memhandle, void *offset, int size, int dir); ++ ++extern void ++vchiq_transfer_bulk(VCHIQ_BULK_T *bulk); ++ ++extern void ++vchiq_complete_bulk(VCHIQ_BULK_T *bulk); ++ ++extern VCHIQ_STATUS_T ++vchiq_copy_from_user(void *dst, const void *src, int size); ++ ++extern void ++remote_event_signal(REMOTE_EVENT_T *event); ++ ++void ++vchiq_platform_check_suspend(VCHIQ_STATE_T *state); ++ ++extern void ++vchiq_platform_paused(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATUS_T ++vchiq_platform_resume(VCHIQ_STATE_T *state); ++ ++extern void ++vchiq_platform_resumed(VCHIQ_STATE_T *state); ++ ++extern void ++vchiq_dump(void *dump_context, const char *str, int len); ++ ++extern void ++vchiq_dump_platform_state(void *dump_context); ++ ++extern void ++vchiq_dump_platform_instances(void *dump_context); ++ ++extern void ++vchiq_dump_platform_service_state(void *dump_context, ++ VCHIQ_SERVICE_T *service); ++ ++extern VCHIQ_STATUS_T ++vchiq_use_service_internal(VCHIQ_SERVICE_T *service); ++ ++extern VCHIQ_STATUS_T ++vchiq_release_service_internal(VCHIQ_SERVICE_T *service); ++ ++extern void ++vchiq_on_remote_use(VCHIQ_STATE_T *state); ++ ++extern void ++vchiq_on_remote_release(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATUS_T ++vchiq_platform_init_state(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATUS_T ++vchiq_check_service(VCHIQ_SERVICE_T *service); ++ ++extern void ++vchiq_on_remote_use_active(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATUS_T ++vchiq_send_remote_use(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATUS_T ++vchiq_send_remote_release(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATUS_T ++vchiq_send_remote_use_active(VCHIQ_STATE_T *state); ++ ++extern void ++vchiq_platform_conn_state_changed(VCHIQ_STATE_T *state, ++ VCHIQ_CONNSTATE_T oldstate, VCHIQ_CONNSTATE_T newstate); ++ ++extern void ++vchiq_platform_handle_timeout(VCHIQ_STATE_T *state); ++ ++extern void ++vchiq_set_conn_state(VCHIQ_STATE_T *state, VCHIQ_CONNSTATE_T newstate); ++ ++ ++extern void ++vchiq_log_dump_mem(const char *label, uint32_t addr, const void *voidMem, ++ size_t numBytes); ++ ++#endif +diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.c +--- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.c 2015-11-29 09:42:38.075221210 +0100 +@@ -0,0 +1,383 @@ ++/** ++ * Copyright (c) 2014 Raspberry Pi (Trading) Ltd. All rights reserved. ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++ ++#include ++#include "vchiq_core.h" ++#include "vchiq_arm.h" ++#include "vchiq_debugfs.h" ++ ++#ifdef CONFIG_DEBUG_FS ++ ++/**************************************************************************** ++* ++* log category entries ++* ++***************************************************************************/ ++#define DEBUGFS_WRITE_BUF_SIZE 256 ++ ++#define VCHIQ_LOG_ERROR_STR "error" ++#define VCHIQ_LOG_WARNING_STR "warning" ++#define VCHIQ_LOG_INFO_STR "info" ++#define VCHIQ_LOG_TRACE_STR "trace" ++ ++ ++/* Top-level debug info */ ++struct vchiq_debugfs_info { ++ /* Global 'vchiq' debugfs entry used by all instances */ ++ struct dentry *vchiq_cfg_dir; ++ ++ /* one entry per client process */ ++ struct dentry *clients; ++ ++ /* log categories */ ++ struct dentry *log_categories; ++}; ++ ++static struct vchiq_debugfs_info debugfs_info; ++ ++/* Log category debugfs entries */ ++struct vchiq_debugfs_log_entry { ++ const char *name; ++ int *plevel; ++ struct dentry *dir; ++}; ++ ++static struct vchiq_debugfs_log_entry vchiq_debugfs_log_entries[] = { ++ { "core", &vchiq_core_log_level }, ++ { "msg", &vchiq_core_msg_log_level }, ++ { "sync", &vchiq_sync_log_level }, ++ { "susp", &vchiq_susp_log_level }, ++ { "arm", &vchiq_arm_log_level }, ++}; ++static int n_log_entries = ++ sizeof(vchiq_debugfs_log_entries)/sizeof(vchiq_debugfs_log_entries[0]); ++ ++ ++static struct dentry *vchiq_clients_top(void); ++static struct dentry *vchiq_debugfs_top(void); ++ ++static int debugfs_log_show(struct seq_file *f, void *offset) ++{ ++ int *levp = f->private; ++ char *log_value = NULL; ++ ++ switch (*levp) { ++ case VCHIQ_LOG_ERROR: ++ log_value = VCHIQ_LOG_ERROR_STR; ++ break; ++ case VCHIQ_LOG_WARNING: ++ log_value = VCHIQ_LOG_WARNING_STR; ++ break; ++ case VCHIQ_LOG_INFO: ++ log_value = VCHIQ_LOG_INFO_STR; ++ break; ++ case VCHIQ_LOG_TRACE: ++ log_value = VCHIQ_LOG_TRACE_STR; ++ break; ++ default: ++ break; ++ } ++ ++ seq_printf(f, "%s\n", log_value ? log_value : "(null)"); ++ ++ return 0; ++} ++ ++static int debugfs_log_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, debugfs_log_show, inode->i_private); ++} ++ ++static int debugfs_log_write(struct file *file, ++ const char __user *buffer, ++ size_t count, loff_t *ppos) ++{ ++ struct seq_file *f = (struct seq_file *)file->private_data; ++ int *levp = f->private; ++ char kbuf[DEBUGFS_WRITE_BUF_SIZE + 1]; ++ ++ memset(kbuf, 0, DEBUGFS_WRITE_BUF_SIZE + 1); ++ if (count >= DEBUGFS_WRITE_BUF_SIZE) ++ count = DEBUGFS_WRITE_BUF_SIZE; ++ ++ if (copy_from_user(kbuf, buffer, count) != 0) ++ return -EFAULT; ++ kbuf[count - 1] = 0; ++ ++ if (strncmp("error", kbuf, strlen("error")) == 0) ++ *levp = VCHIQ_LOG_ERROR; ++ else if (strncmp("warning", kbuf, strlen("warning")) == 0) ++ *levp = VCHIQ_LOG_WARNING; ++ else if (strncmp("info", kbuf, strlen("info")) == 0) ++ *levp = VCHIQ_LOG_INFO; ++ else if (strncmp("trace", kbuf, strlen("trace")) == 0) ++ *levp = VCHIQ_LOG_TRACE; ++ else ++ *levp = VCHIQ_LOG_DEFAULT; ++ ++ *ppos += count; ++ ++ return count; ++} ++ ++static const struct file_operations debugfs_log_fops = { ++ .owner = THIS_MODULE, ++ .open = debugfs_log_open, ++ .write = debugfs_log_write, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++/* create an entry under /vchiq/log for each log category */ ++static int vchiq_debugfs_create_log_entries(struct dentry *top) ++{ ++ struct dentry *dir; ++ size_t i; ++ int ret = 0; ++ dir = debugfs_create_dir("log", vchiq_debugfs_top()); ++ if (!dir) ++ return -ENOMEM; ++ debugfs_info.log_categories = dir; ++ ++ for (i = 0; i < n_log_entries; i++) { ++ void *levp = (void *)vchiq_debugfs_log_entries[i].plevel; ++ dir = debugfs_create_file(vchiq_debugfs_log_entries[i].name, ++ 0644, ++ debugfs_info.log_categories, ++ levp, ++ &debugfs_log_fops); ++ if (!dir) { ++ ret = -ENOMEM; ++ break; ++ } ++ ++ vchiq_debugfs_log_entries[i].dir = dir; ++ } ++ return ret; ++} ++ ++static int debugfs_usecount_show(struct seq_file *f, void *offset) ++{ ++ VCHIQ_INSTANCE_T instance = f->private; ++ int use_count; ++ ++ use_count = vchiq_instance_get_use_count(instance); ++ seq_printf(f, "%d\n", use_count); ++ ++ return 0; ++} ++ ++static int debugfs_usecount_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, debugfs_usecount_show, inode->i_private); ++} ++ ++static const struct file_operations debugfs_usecount_fops = { ++ .owner = THIS_MODULE, ++ .open = debugfs_usecount_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++static int debugfs_trace_show(struct seq_file *f, void *offset) ++{ ++ VCHIQ_INSTANCE_T instance = f->private; ++ int trace; ++ ++ trace = vchiq_instance_get_trace(instance); ++ seq_printf(f, "%s\n", trace ? "Y" : "N"); ++ ++ return 0; ++} ++ ++static int debugfs_trace_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, debugfs_trace_show, inode->i_private); ++} ++ ++static int debugfs_trace_write(struct file *file, ++ const char __user *buffer, ++ size_t count, loff_t *ppos) ++{ ++ struct seq_file *f = (struct seq_file *)file->private_data; ++ VCHIQ_INSTANCE_T instance = f->private; ++ char firstchar; ++ ++ if (copy_from_user(&firstchar, buffer, 1) != 0) ++ return -EFAULT; ++ ++ switch (firstchar) { ++ case 'Y': ++ case 'y': ++ case '1': ++ vchiq_instance_set_trace(instance, 1); ++ break; ++ case 'N': ++ case 'n': ++ case '0': ++ vchiq_instance_set_trace(instance, 0); ++ break; ++ default: ++ break; ++ } ++ ++ *ppos += count; ++ ++ return count; ++} ++ ++static const struct file_operations debugfs_trace_fops = { ++ .owner = THIS_MODULE, ++ .open = debugfs_trace_open, ++ .write = debugfs_trace_write, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++/* add an instance (process) to the debugfs entries */ ++int vchiq_debugfs_add_instance(VCHIQ_INSTANCE_T instance) ++{ ++ char pidstr[16]; ++ struct dentry *top, *use_count, *trace; ++ struct dentry *clients = vchiq_clients_top(); ++ ++ snprintf(pidstr, sizeof(pidstr), "%d", ++ vchiq_instance_get_pid(instance)); ++ ++ top = debugfs_create_dir(pidstr, clients); ++ if (!top) ++ goto fail_top; ++ ++ use_count = debugfs_create_file("use_count", ++ 0444, top, ++ instance, ++ &debugfs_usecount_fops); ++ if (!use_count) ++ goto fail_use_count; ++ ++ trace = debugfs_create_file("trace", ++ 0644, top, ++ instance, ++ &debugfs_trace_fops); ++ if (!trace) ++ goto fail_trace; ++ ++ vchiq_instance_get_debugfs_node(instance)->dentry = top; ++ ++ return 0; ++ ++fail_trace: ++ debugfs_remove(use_count); ++fail_use_count: ++ debugfs_remove(top); ++fail_top: ++ return -ENOMEM; ++} ++ ++void vchiq_debugfs_remove_instance(VCHIQ_INSTANCE_T instance) ++{ ++ VCHIQ_DEBUGFS_NODE_T *node = vchiq_instance_get_debugfs_node(instance); ++ debugfs_remove_recursive(node->dentry); ++} ++ ++ ++int vchiq_debugfs_init(void) ++{ ++ BUG_ON(debugfs_info.vchiq_cfg_dir != NULL); ++ ++ debugfs_info.vchiq_cfg_dir = debugfs_create_dir("vchiq", NULL); ++ if (debugfs_info.vchiq_cfg_dir == NULL) ++ goto fail; ++ ++ debugfs_info.clients = debugfs_create_dir("clients", ++ vchiq_debugfs_top()); ++ if (!debugfs_info.clients) ++ goto fail; ++ ++ if (vchiq_debugfs_create_log_entries(vchiq_debugfs_top()) != 0) ++ goto fail; ++ ++ return 0; ++ ++fail: ++ vchiq_debugfs_deinit(); ++ vchiq_log_error(vchiq_arm_log_level, ++ "%s: failed to create debugfs directory", ++ __func__); ++ ++ return -ENOMEM; ++} ++ ++/* remove all the debugfs entries */ ++void vchiq_debugfs_deinit(void) ++{ ++ debugfs_remove_recursive(vchiq_debugfs_top()); ++} ++ ++static struct dentry *vchiq_clients_top(void) ++{ ++ return debugfs_info.clients; ++} ++ ++static struct dentry *vchiq_debugfs_top(void) ++{ ++ BUG_ON(debugfs_info.vchiq_cfg_dir == NULL); ++ return debugfs_info.vchiq_cfg_dir; ++} ++ ++#else /* CONFIG_DEBUG_FS */ ++ ++int vchiq_debugfs_init(void) ++{ ++ return 0; ++} ++ ++void vchiq_debugfs_deinit(void) ++{ ++} ++ ++int vchiq_debugfs_add_instance(VCHIQ_INSTANCE_T instance) ++{ ++ return 0; ++} ++ ++void vchiq_debugfs_remove_instance(VCHIQ_INSTANCE_T instance) ++{ ++} ++ ++#endif /* CONFIG_DEBUG_FS */ +diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.h +--- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_debugfs.h 2015-11-29 09:42:38.075221210 +0100 +@@ -0,0 +1,52 @@ ++/** ++ * Copyright (c) 2014 Raspberry Pi (Trading) Ltd. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHIQ_DEBUGFS_H ++#define VCHIQ_DEBUGFS_H ++ ++#include "vchiq_core.h" ++ ++typedef struct vchiq_debugfs_node_struct ++{ ++ struct dentry *dentry; ++} VCHIQ_DEBUGFS_NODE_T; ++ ++int vchiq_debugfs_init(void); ++ ++void vchiq_debugfs_deinit(void); ++ ++int vchiq_debugfs_add_instance(VCHIQ_INSTANCE_T instance); ++ ++void vchiq_debugfs_remove_instance(VCHIQ_INSTANCE_T instance); ++ ++#endif /* VCHIQ_DEBUGFS_H */ +diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_genversion linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_genversion +--- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_genversion 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_genversion 2015-11-29 09:42:38.075221210 +0100 +@@ -0,0 +1,87 @@ ++#!/usr/bin/perl -w ++ ++use strict; ++ ++# ++# Generate a version from available information ++# ++ ++my $prefix = shift @ARGV; ++my $root = shift @ARGV; ++ ++ ++if ( not defined $root ) { ++ die "usage: $0 prefix root-dir\n"; ++} ++ ++if ( ! -d $root ) { ++ die "root directory $root not found\n"; ++} ++ ++my $version = "unknown"; ++my $tainted = ""; ++ ++if ( -d "$root/.git" ) { ++ # attempt to work out git version. only do so ++ # on a linux build host, as cygwin builds are ++ # already slow enough ++ ++ if ( -f "/usr/bin/git" || -f "/usr/local/bin/git" ) { ++ if (not open(F, "git --git-dir $root/.git rev-parse --verify HEAD|")) { ++ $version = "no git version"; ++ } ++ else { ++ $version = ; ++ $version =~ s/[ \r\n]*$//; # chomp may not be enough (cygwin). ++ $version =~ s/^[ \r\n]*//; # chomp may not be enough (cygwin). ++ } ++ ++ if (open(G, "git --git-dir $root/.git status --porcelain|")) { ++ $tainted = ; ++ $tainted =~ s/[ \r\n]*$//; # chomp may not be enough (cygwin). ++ $tainted =~ s/^[ \r\n]*//; # chomp may not be enough (cygwin). ++ if (length $tainted) { ++ $version = join ' ', $version, "(tainted)"; ++ } ++ else { ++ $version = join ' ', $version, "(clean)"; ++ } ++ } ++ } ++} ++ ++my $hostname = `hostname`; ++$hostname =~ s/[ \r\n]*$//; # chomp may not be enough (cygwin). ++$hostname =~ s/^[ \r\n]*//; # chomp may not be enough (cygwin). ++ ++ ++print STDERR "Version $version\n"; ++print < ++ ++VC_DEBUG_DECLARE_STRING_VAR( ${prefix}_build_hostname, "$hostname" ); ++VC_DEBUG_DECLARE_STRING_VAR( ${prefix}_build_version, "$version" ); ++VC_DEBUG_DECLARE_STRING_VAR( ${prefix}_build_time, __TIME__ ); ++VC_DEBUG_DECLARE_STRING_VAR( ${prefix}_build_date, __DATE__ ); ++ ++const char *vchiq_get_build_hostname( void ) ++{ ++ return vchiq_build_hostname; ++} ++ ++const char *vchiq_get_build_version( void ) ++{ ++ return vchiq_build_version; ++} ++ ++const char *vchiq_get_build_date( void ) ++{ ++ return vchiq_build_date; ++} ++ ++const char *vchiq_get_build_time( void ) ++{ ++ return vchiq_build_time; ++} ++EOF +diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq.h +--- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq.h 2015-11-29 09:42:38.059222273 +0100 +@@ -0,0 +1,40 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHIQ_VCHIQ_H ++#define VCHIQ_VCHIQ_H ++ ++#include "vchiq_if.h" ++#include "vchiq_util.h" ++ ++#endif +diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h +--- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h 2015-11-29 09:42:38.075221210 +0100 +@@ -0,0 +1,189 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHIQ_IF_H ++#define VCHIQ_IF_H ++ ++#include "interface/vchi/vchi_mh.h" ++ ++#define VCHIQ_SERVICE_HANDLE_INVALID 0 ++ ++#define VCHIQ_SLOT_SIZE 4096 ++#define VCHIQ_MAX_MSG_SIZE (VCHIQ_SLOT_SIZE - sizeof(VCHIQ_HEADER_T)) ++#define VCHIQ_CHANNEL_SIZE VCHIQ_MAX_MSG_SIZE /* For backwards compatibility */ ++ ++#define VCHIQ_MAKE_FOURCC(x0, x1, x2, x3) \ ++ (((x0) << 24) | ((x1) << 16) | ((x2) << 8) | (x3)) ++#define VCHIQ_GET_SERVICE_USERDATA(service) vchiq_get_service_userdata(service) ++#define VCHIQ_GET_SERVICE_FOURCC(service) vchiq_get_service_fourcc(service) ++ ++typedef enum { ++ VCHIQ_SERVICE_OPENED, /* service, -, - */ ++ VCHIQ_SERVICE_CLOSED, /* service, -, - */ ++ VCHIQ_MESSAGE_AVAILABLE, /* service, header, - */ ++ VCHIQ_BULK_TRANSMIT_DONE, /* service, -, bulk_userdata */ ++ VCHIQ_BULK_RECEIVE_DONE, /* service, -, bulk_userdata */ ++ VCHIQ_BULK_TRANSMIT_ABORTED, /* service, -, bulk_userdata */ ++ VCHIQ_BULK_RECEIVE_ABORTED /* service, -, bulk_userdata */ ++} VCHIQ_REASON_T; ++ ++typedef enum { ++ VCHIQ_ERROR = -1, ++ VCHIQ_SUCCESS = 0, ++ VCHIQ_RETRY = 1 ++} VCHIQ_STATUS_T; ++ ++typedef enum { ++ VCHIQ_BULK_MODE_CALLBACK, ++ VCHIQ_BULK_MODE_BLOCKING, ++ VCHIQ_BULK_MODE_NOCALLBACK, ++ VCHIQ_BULK_MODE_WAITING /* Reserved for internal use */ ++} VCHIQ_BULK_MODE_T; ++ ++typedef enum { ++ VCHIQ_SERVICE_OPTION_AUTOCLOSE, ++ VCHIQ_SERVICE_OPTION_SLOT_QUOTA, ++ VCHIQ_SERVICE_OPTION_MESSAGE_QUOTA, ++ VCHIQ_SERVICE_OPTION_SYNCHRONOUS, ++ VCHIQ_SERVICE_OPTION_TRACE ++} VCHIQ_SERVICE_OPTION_T; ++ ++typedef struct vchiq_header_struct { ++ /* The message identifier - opaque to applications. */ ++ int msgid; ++ ++ /* Size of message data. */ ++ unsigned int size; ++ ++ char data[0]; /* message */ ++} VCHIQ_HEADER_T; ++ ++typedef struct { ++ const void *data; ++ unsigned int size; ++} VCHIQ_ELEMENT_T; ++ ++typedef unsigned int VCHIQ_SERVICE_HANDLE_T; ++ ++typedef VCHIQ_STATUS_T (*VCHIQ_CALLBACK_T)(VCHIQ_REASON_T, VCHIQ_HEADER_T *, ++ VCHIQ_SERVICE_HANDLE_T, void *); ++ ++typedef struct vchiq_service_base_struct { ++ int fourcc; ++ VCHIQ_CALLBACK_T callback; ++ void *userdata; ++} VCHIQ_SERVICE_BASE_T; ++ ++typedef struct vchiq_service_params_struct { ++ int fourcc; ++ VCHIQ_CALLBACK_T callback; ++ void *userdata; ++ short version; /* Increment for non-trivial changes */ ++ short version_min; /* Update for incompatible changes */ ++} VCHIQ_SERVICE_PARAMS_T; ++ ++typedef struct vchiq_config_struct { ++ unsigned int max_msg_size; ++ unsigned int bulk_threshold; /* The message size above which it ++ is better to use a bulk transfer ++ (<= max_msg_size) */ ++ unsigned int max_outstanding_bulks; ++ unsigned int max_services; ++ short version; /* The version of VCHIQ */ ++ short version_min; /* The minimum compatible version of VCHIQ */ ++} VCHIQ_CONFIG_T; ++ ++typedef struct vchiq_instance_struct *VCHIQ_INSTANCE_T; ++typedef void (*VCHIQ_REMOTE_USE_CALLBACK_T)(void *cb_arg); ++ ++extern VCHIQ_STATUS_T vchiq_initialise(VCHIQ_INSTANCE_T *pinstance); ++extern VCHIQ_STATUS_T vchiq_shutdown(VCHIQ_INSTANCE_T instance); ++extern VCHIQ_STATUS_T vchiq_connect(VCHIQ_INSTANCE_T instance); ++extern VCHIQ_STATUS_T vchiq_add_service(VCHIQ_INSTANCE_T instance, ++ const VCHIQ_SERVICE_PARAMS_T *params, ++ VCHIQ_SERVICE_HANDLE_T *pservice); ++extern VCHIQ_STATUS_T vchiq_open_service(VCHIQ_INSTANCE_T instance, ++ const VCHIQ_SERVICE_PARAMS_T *params, ++ VCHIQ_SERVICE_HANDLE_T *pservice); ++extern VCHIQ_STATUS_T vchiq_close_service(VCHIQ_SERVICE_HANDLE_T service); ++extern VCHIQ_STATUS_T vchiq_remove_service(VCHIQ_SERVICE_HANDLE_T service); ++extern VCHIQ_STATUS_T vchiq_use_service(VCHIQ_SERVICE_HANDLE_T service); ++extern VCHIQ_STATUS_T vchiq_use_service_no_resume( ++ VCHIQ_SERVICE_HANDLE_T service); ++extern VCHIQ_STATUS_T vchiq_release_service(VCHIQ_SERVICE_HANDLE_T service); ++ ++extern VCHIQ_STATUS_T vchiq_queue_message(VCHIQ_SERVICE_HANDLE_T service, ++ const VCHIQ_ELEMENT_T *elements, unsigned int count); ++extern void vchiq_release_message(VCHIQ_SERVICE_HANDLE_T service, ++ VCHIQ_HEADER_T *header); ++extern VCHIQ_STATUS_T vchiq_queue_bulk_transmit(VCHIQ_SERVICE_HANDLE_T service, ++ const void *data, unsigned int size, void *userdata); ++extern VCHIQ_STATUS_T vchiq_queue_bulk_receive(VCHIQ_SERVICE_HANDLE_T service, ++ void *data, unsigned int size, void *userdata); ++extern VCHIQ_STATUS_T vchiq_queue_bulk_transmit_handle( ++ VCHIQ_SERVICE_HANDLE_T service, VCHI_MEM_HANDLE_T handle, ++ const void *offset, unsigned int size, void *userdata); ++extern VCHIQ_STATUS_T vchiq_queue_bulk_receive_handle( ++ VCHIQ_SERVICE_HANDLE_T service, VCHI_MEM_HANDLE_T handle, ++ void *offset, unsigned int size, void *userdata); ++extern VCHIQ_STATUS_T vchiq_bulk_transmit(VCHIQ_SERVICE_HANDLE_T service, ++ const void *data, unsigned int size, void *userdata, ++ VCHIQ_BULK_MODE_T mode); ++extern VCHIQ_STATUS_T vchiq_bulk_receive(VCHIQ_SERVICE_HANDLE_T service, ++ void *data, unsigned int size, void *userdata, ++ VCHIQ_BULK_MODE_T mode); ++extern VCHIQ_STATUS_T vchiq_bulk_transmit_handle(VCHIQ_SERVICE_HANDLE_T service, ++ VCHI_MEM_HANDLE_T handle, const void *offset, unsigned int size, ++ void *userdata, VCHIQ_BULK_MODE_T mode); ++extern VCHIQ_STATUS_T vchiq_bulk_receive_handle(VCHIQ_SERVICE_HANDLE_T service, ++ VCHI_MEM_HANDLE_T handle, void *offset, unsigned int size, ++ void *userdata, VCHIQ_BULK_MODE_T mode); ++extern int vchiq_get_client_id(VCHIQ_SERVICE_HANDLE_T service); ++extern void *vchiq_get_service_userdata(VCHIQ_SERVICE_HANDLE_T service); ++extern int vchiq_get_service_fourcc(VCHIQ_SERVICE_HANDLE_T service); ++extern VCHIQ_STATUS_T vchiq_get_config(VCHIQ_INSTANCE_T instance, ++ int config_size, VCHIQ_CONFIG_T *pconfig); ++extern VCHIQ_STATUS_T vchiq_set_service_option(VCHIQ_SERVICE_HANDLE_T service, ++ VCHIQ_SERVICE_OPTION_T option, int value); ++ ++extern VCHIQ_STATUS_T vchiq_remote_use(VCHIQ_INSTANCE_T instance, ++ VCHIQ_REMOTE_USE_CALLBACK_T callback, void *cb_arg); ++extern VCHIQ_STATUS_T vchiq_remote_release(VCHIQ_INSTANCE_T instance); ++ ++extern VCHIQ_STATUS_T vchiq_dump_phys_mem(VCHIQ_SERVICE_HANDLE_T service, ++ void *ptr, size_t num_bytes); ++ ++extern VCHIQ_STATUS_T vchiq_get_peer_version(VCHIQ_SERVICE_HANDLE_T handle, ++ short *peer_version); ++ ++#endif /* VCHIQ_IF_H */ +diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h +--- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h 2015-11-29 09:42:38.075221210 +0100 +@@ -0,0 +1,131 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHIQ_IOCTLS_H ++#define VCHIQ_IOCTLS_H ++ ++#include ++#include "vchiq_if.h" ++ ++#define VCHIQ_IOC_MAGIC 0xc4 ++#define VCHIQ_INVALID_HANDLE (~0) ++ ++typedef struct { ++ VCHIQ_SERVICE_PARAMS_T params; ++ int is_open; ++ int is_vchi; ++ unsigned int handle; /* OUT */ ++} VCHIQ_CREATE_SERVICE_T; ++ ++typedef struct { ++ unsigned int handle; ++ unsigned int count; ++ const VCHIQ_ELEMENT_T *elements; ++} VCHIQ_QUEUE_MESSAGE_T; ++ ++typedef struct { ++ unsigned int handle; ++ void *data; ++ unsigned int size; ++ void *userdata; ++ VCHIQ_BULK_MODE_T mode; ++} VCHIQ_QUEUE_BULK_TRANSFER_T; ++ ++typedef struct { ++ VCHIQ_REASON_T reason; ++ VCHIQ_HEADER_T *header; ++ void *service_userdata; ++ void *bulk_userdata; ++} VCHIQ_COMPLETION_DATA_T; ++ ++typedef struct { ++ unsigned int count; ++ VCHIQ_COMPLETION_DATA_T *buf; ++ unsigned int msgbufsize; ++ unsigned int msgbufcount; /* IN/OUT */ ++ void **msgbufs; ++} VCHIQ_AWAIT_COMPLETION_T; ++ ++typedef struct { ++ unsigned int handle; ++ int blocking; ++ unsigned int bufsize; ++ void *buf; ++} VCHIQ_DEQUEUE_MESSAGE_T; ++ ++typedef struct { ++ unsigned int config_size; ++ VCHIQ_CONFIG_T *pconfig; ++} VCHIQ_GET_CONFIG_T; ++ ++typedef struct { ++ unsigned int handle; ++ VCHIQ_SERVICE_OPTION_T option; ++ int value; ++} VCHIQ_SET_SERVICE_OPTION_T; ++ ++typedef struct { ++ void *virt_addr; ++ size_t num_bytes; ++} VCHIQ_DUMP_MEM_T; ++ ++#define VCHIQ_IOC_CONNECT _IO(VCHIQ_IOC_MAGIC, 0) ++#define VCHIQ_IOC_SHUTDOWN _IO(VCHIQ_IOC_MAGIC, 1) ++#define VCHIQ_IOC_CREATE_SERVICE \ ++ _IOWR(VCHIQ_IOC_MAGIC, 2, VCHIQ_CREATE_SERVICE_T) ++#define VCHIQ_IOC_REMOVE_SERVICE _IO(VCHIQ_IOC_MAGIC, 3) ++#define VCHIQ_IOC_QUEUE_MESSAGE \ ++ _IOW(VCHIQ_IOC_MAGIC, 4, VCHIQ_QUEUE_MESSAGE_T) ++#define VCHIQ_IOC_QUEUE_BULK_TRANSMIT \ ++ _IOWR(VCHIQ_IOC_MAGIC, 5, VCHIQ_QUEUE_BULK_TRANSFER_T) ++#define VCHIQ_IOC_QUEUE_BULK_RECEIVE \ ++ _IOWR(VCHIQ_IOC_MAGIC, 6, VCHIQ_QUEUE_BULK_TRANSFER_T) ++#define VCHIQ_IOC_AWAIT_COMPLETION \ ++ _IOWR(VCHIQ_IOC_MAGIC, 7, VCHIQ_AWAIT_COMPLETION_T) ++#define VCHIQ_IOC_DEQUEUE_MESSAGE \ ++ _IOWR(VCHIQ_IOC_MAGIC, 8, VCHIQ_DEQUEUE_MESSAGE_T) ++#define VCHIQ_IOC_GET_CLIENT_ID _IO(VCHIQ_IOC_MAGIC, 9) ++#define VCHIQ_IOC_GET_CONFIG \ ++ _IOWR(VCHIQ_IOC_MAGIC, 10, VCHIQ_GET_CONFIG_T) ++#define VCHIQ_IOC_CLOSE_SERVICE _IO(VCHIQ_IOC_MAGIC, 11) ++#define VCHIQ_IOC_USE_SERVICE _IO(VCHIQ_IOC_MAGIC, 12) ++#define VCHIQ_IOC_RELEASE_SERVICE _IO(VCHIQ_IOC_MAGIC, 13) ++#define VCHIQ_IOC_SET_SERVICE_OPTION \ ++ _IOW(VCHIQ_IOC_MAGIC, 14, VCHIQ_SET_SERVICE_OPTION_T) ++#define VCHIQ_IOC_DUMP_PHYS_MEM \ ++ _IOW(VCHIQ_IOC_MAGIC, 15, VCHIQ_DUMP_MEM_T) ++#define VCHIQ_IOC_LIB_VERSION _IO(VCHIQ_IOC_MAGIC, 16) ++#define VCHIQ_IOC_CLOSE_DELIVERED _IO(VCHIQ_IOC_MAGIC, 17) ++#define VCHIQ_IOC_MAX 17 ++ ++#endif +diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c +--- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c 2015-11-29 09:42:38.075221210 +0100 +@@ -0,0 +1,458 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/* ---- Include Files ---------------------------------------------------- */ ++ ++#include ++#include ++#include ++ ++#include "vchiq_core.h" ++#include "vchiq_arm.h" ++#include "vchiq_killable.h" ++ ++/* ---- Public Variables ------------------------------------------------- */ ++ ++/* ---- Private Constants and Types -------------------------------------- */ ++ ++struct bulk_waiter_node { ++ struct bulk_waiter bulk_waiter; ++ int pid; ++ struct list_head list; ++}; ++ ++struct vchiq_instance_struct { ++ VCHIQ_STATE_T *state; ++ ++ int connected; ++ ++ struct list_head bulk_waiter_list; ++ struct mutex bulk_waiter_list_mutex; ++}; ++ ++static VCHIQ_STATUS_T ++vchiq_blocking_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle, void *data, ++ unsigned int size, VCHIQ_BULK_DIR_T dir); ++ ++/**************************************************************************** ++* ++* vchiq_initialise ++* ++***************************************************************************/ ++#define VCHIQ_INIT_RETRIES 10 ++VCHIQ_STATUS_T vchiq_initialise(VCHIQ_INSTANCE_T *instanceOut) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_ERROR; ++ VCHIQ_STATE_T *state; ++ VCHIQ_INSTANCE_T instance = NULL; ++ int i; ++ ++ vchiq_log_trace(vchiq_core_log_level, "%s called", __func__); ++ ++ /* VideoCore may not be ready due to boot up timing. ++ It may never be ready if kernel and firmware are mismatched, so don't block forever. */ ++ for (i=0; i0) { ++ vchiq_log_warning(vchiq_core_log_level, ++ "%s: videocore initialized after %d retries\n", __func__, i); ++ } ++ ++ instance = kzalloc(sizeof(*instance), GFP_KERNEL); ++ if (!instance) { ++ vchiq_log_error(vchiq_core_log_level, ++ "%s: error allocating vchiq instance\n", __func__); ++ goto failed; ++ } ++ ++ instance->connected = 0; ++ instance->state = state; ++ mutex_init(&instance->bulk_waiter_list_mutex); ++ INIT_LIST_HEAD(&instance->bulk_waiter_list); ++ ++ *instanceOut = instance; ++ ++ status = VCHIQ_SUCCESS; ++ ++failed: ++ vchiq_log_trace(vchiq_core_log_level, ++ "%s(%p): returning %d", __func__, instance, status); ++ ++ return status; ++} ++EXPORT_SYMBOL(vchiq_initialise); ++ ++/**************************************************************************** ++* ++* vchiq_shutdown ++* ++***************************************************************************/ ++ ++VCHIQ_STATUS_T vchiq_shutdown(VCHIQ_INSTANCE_T instance) ++{ ++ VCHIQ_STATUS_T status; ++ VCHIQ_STATE_T *state = instance->state; ++ ++ vchiq_log_trace(vchiq_core_log_level, ++ "%s(%p) called", __func__, instance); ++ ++ if (mutex_lock_interruptible(&state->mutex) != 0) ++ return VCHIQ_RETRY; ++ ++ /* Remove all services */ ++ status = vchiq_shutdown_internal(state, instance); ++ ++ mutex_unlock(&state->mutex); ++ ++ vchiq_log_trace(vchiq_core_log_level, ++ "%s(%p): returning %d", __func__, instance, status); ++ ++ if (status == VCHIQ_SUCCESS) { ++ struct list_head *pos, *next; ++ list_for_each_safe(pos, next, ++ &instance->bulk_waiter_list) { ++ struct bulk_waiter_node *waiter; ++ waiter = list_entry(pos, ++ struct bulk_waiter_node, ++ list); ++ list_del(pos); ++ vchiq_log_info(vchiq_arm_log_level, ++ "bulk_waiter - cleaned up %x " ++ "for pid %d", ++ (unsigned int)waiter, waiter->pid); ++ kfree(waiter); ++ } ++ kfree(instance); ++ } ++ ++ return status; ++} ++EXPORT_SYMBOL(vchiq_shutdown); ++ ++/**************************************************************************** ++* ++* vchiq_is_connected ++* ++***************************************************************************/ ++ ++int vchiq_is_connected(VCHIQ_INSTANCE_T instance) ++{ ++ return instance->connected; ++} ++ ++/**************************************************************************** ++* ++* vchiq_connect ++* ++***************************************************************************/ ++ ++VCHIQ_STATUS_T vchiq_connect(VCHIQ_INSTANCE_T instance) ++{ ++ VCHIQ_STATUS_T status; ++ VCHIQ_STATE_T *state = instance->state; ++ ++ vchiq_log_trace(vchiq_core_log_level, ++ "%s(%p) called", __func__, instance); ++ ++ if (mutex_lock_interruptible(&state->mutex) != 0) { ++ vchiq_log_trace(vchiq_core_log_level, ++ "%s: call to mutex_lock failed", __func__); ++ status = VCHIQ_RETRY; ++ goto failed; ++ } ++ status = vchiq_connect_internal(state, instance); ++ ++ if (status == VCHIQ_SUCCESS) ++ instance->connected = 1; ++ ++ mutex_unlock(&state->mutex); ++ ++failed: ++ vchiq_log_trace(vchiq_core_log_level, ++ "%s(%p): returning %d", __func__, instance, status); ++ ++ return status; ++} ++EXPORT_SYMBOL(vchiq_connect); ++ ++/**************************************************************************** ++* ++* vchiq_add_service ++* ++***************************************************************************/ ++ ++VCHIQ_STATUS_T vchiq_add_service( ++ VCHIQ_INSTANCE_T instance, ++ const VCHIQ_SERVICE_PARAMS_T *params, ++ VCHIQ_SERVICE_HANDLE_T *phandle) ++{ ++ VCHIQ_STATUS_T status; ++ VCHIQ_STATE_T *state = instance->state; ++ VCHIQ_SERVICE_T *service = NULL; ++ int srvstate; ++ ++ vchiq_log_trace(vchiq_core_log_level, ++ "%s(%p) called", __func__, instance); ++ ++ *phandle = VCHIQ_SERVICE_HANDLE_INVALID; ++ ++ srvstate = vchiq_is_connected(instance) ++ ? VCHIQ_SRVSTATE_LISTENING ++ : VCHIQ_SRVSTATE_HIDDEN; ++ ++ service = vchiq_add_service_internal( ++ state, ++ params, ++ srvstate, ++ instance, ++ NULL); ++ ++ if (service) { ++ *phandle = service->handle; ++ status = VCHIQ_SUCCESS; ++ } else ++ status = VCHIQ_ERROR; ++ ++ vchiq_log_trace(vchiq_core_log_level, ++ "%s(%p): returning %d", __func__, instance, status); ++ ++ return status; ++} ++EXPORT_SYMBOL(vchiq_add_service); ++ ++/**************************************************************************** ++* ++* vchiq_open_service ++* ++***************************************************************************/ ++ ++VCHIQ_STATUS_T vchiq_open_service( ++ VCHIQ_INSTANCE_T instance, ++ const VCHIQ_SERVICE_PARAMS_T *params, ++ VCHIQ_SERVICE_HANDLE_T *phandle) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_ERROR; ++ VCHIQ_STATE_T *state = instance->state; ++ VCHIQ_SERVICE_T *service = NULL; ++ ++ vchiq_log_trace(vchiq_core_log_level, ++ "%s(%p) called", __func__, instance); ++ ++ *phandle = VCHIQ_SERVICE_HANDLE_INVALID; ++ ++ if (!vchiq_is_connected(instance)) ++ goto failed; ++ ++ service = vchiq_add_service_internal(state, ++ params, ++ VCHIQ_SRVSTATE_OPENING, ++ instance, ++ NULL); ++ ++ if (service) { ++ *phandle = service->handle; ++ status = vchiq_open_service_internal(service, current->pid); ++ if (status != VCHIQ_SUCCESS) { ++ vchiq_remove_service(service->handle); ++ *phandle = VCHIQ_SERVICE_HANDLE_INVALID; ++ } ++ } ++ ++failed: ++ vchiq_log_trace(vchiq_core_log_level, ++ "%s(%p): returning %d", __func__, instance, status); ++ ++ return status; ++} ++EXPORT_SYMBOL(vchiq_open_service); ++ ++VCHIQ_STATUS_T ++vchiq_queue_bulk_transmit(VCHIQ_SERVICE_HANDLE_T handle, ++ const void *data, unsigned int size, void *userdata) ++{ ++ return vchiq_bulk_transfer(handle, ++ VCHI_MEM_HANDLE_INVALID, (void *)data, size, userdata, ++ VCHIQ_BULK_MODE_CALLBACK, VCHIQ_BULK_TRANSMIT); ++} ++EXPORT_SYMBOL(vchiq_queue_bulk_transmit); ++ ++VCHIQ_STATUS_T ++vchiq_queue_bulk_receive(VCHIQ_SERVICE_HANDLE_T handle, void *data, ++ unsigned int size, void *userdata) ++{ ++ return vchiq_bulk_transfer(handle, ++ VCHI_MEM_HANDLE_INVALID, data, size, userdata, ++ VCHIQ_BULK_MODE_CALLBACK, VCHIQ_BULK_RECEIVE); ++} ++EXPORT_SYMBOL(vchiq_queue_bulk_receive); ++ ++VCHIQ_STATUS_T ++vchiq_bulk_transmit(VCHIQ_SERVICE_HANDLE_T handle, const void *data, ++ unsigned int size, void *userdata, VCHIQ_BULK_MODE_T mode) ++{ ++ VCHIQ_STATUS_T status; ++ ++ switch (mode) { ++ case VCHIQ_BULK_MODE_NOCALLBACK: ++ case VCHIQ_BULK_MODE_CALLBACK: ++ status = vchiq_bulk_transfer(handle, ++ VCHI_MEM_HANDLE_INVALID, (void *)data, size, userdata, ++ mode, VCHIQ_BULK_TRANSMIT); ++ break; ++ case VCHIQ_BULK_MODE_BLOCKING: ++ status = vchiq_blocking_bulk_transfer(handle, ++ (void *)data, size, VCHIQ_BULK_TRANSMIT); ++ break; ++ default: ++ return VCHIQ_ERROR; ++ } ++ ++ return status; ++} ++EXPORT_SYMBOL(vchiq_bulk_transmit); ++ ++VCHIQ_STATUS_T ++vchiq_bulk_receive(VCHIQ_SERVICE_HANDLE_T handle, void *data, ++ unsigned int size, void *userdata, VCHIQ_BULK_MODE_T mode) ++{ ++ VCHIQ_STATUS_T status; ++ ++ switch (mode) { ++ case VCHIQ_BULK_MODE_NOCALLBACK: ++ case VCHIQ_BULK_MODE_CALLBACK: ++ status = vchiq_bulk_transfer(handle, ++ VCHI_MEM_HANDLE_INVALID, data, size, userdata, ++ mode, VCHIQ_BULK_RECEIVE); ++ break; ++ case VCHIQ_BULK_MODE_BLOCKING: ++ status = vchiq_blocking_bulk_transfer(handle, ++ (void *)data, size, VCHIQ_BULK_RECEIVE); ++ break; ++ default: ++ return VCHIQ_ERROR; ++ } ++ ++ return status; ++} ++EXPORT_SYMBOL(vchiq_bulk_receive); ++ ++static VCHIQ_STATUS_T ++vchiq_blocking_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle, void *data, ++ unsigned int size, VCHIQ_BULK_DIR_T dir) ++{ ++ VCHIQ_INSTANCE_T instance; ++ VCHIQ_SERVICE_T *service; ++ VCHIQ_STATUS_T status; ++ struct bulk_waiter_node *waiter = NULL; ++ struct list_head *pos; ++ ++ service = find_service_by_handle(handle); ++ if (!service) ++ return VCHIQ_ERROR; ++ ++ instance = service->instance; ++ ++ unlock_service(service); ++ ++ mutex_lock(&instance->bulk_waiter_list_mutex); ++ list_for_each(pos, &instance->bulk_waiter_list) { ++ if (list_entry(pos, struct bulk_waiter_node, ++ list)->pid == current->pid) { ++ waiter = list_entry(pos, ++ struct bulk_waiter_node, ++ list); ++ list_del(pos); ++ break; ++ } ++ } ++ mutex_unlock(&instance->bulk_waiter_list_mutex); ++ ++ if (waiter) { ++ VCHIQ_BULK_T *bulk = waiter->bulk_waiter.bulk; ++ if (bulk) { ++ /* This thread has an outstanding bulk transfer. */ ++ if ((bulk->data != data) || ++ (bulk->size != size)) { ++ /* This is not a retry of the previous one. ++ ** Cancel the signal when the transfer ++ ** completes. */ ++ spin_lock(&bulk_waiter_spinlock); ++ bulk->userdata = NULL; ++ spin_unlock(&bulk_waiter_spinlock); ++ } ++ } ++ } ++ ++ if (!waiter) { ++ waiter = kzalloc(sizeof(struct bulk_waiter_node), GFP_KERNEL); ++ if (!waiter) { ++ vchiq_log_error(vchiq_core_log_level, ++ "%s - out of memory", __func__); ++ return VCHIQ_ERROR; ++ } ++ } ++ ++ status = vchiq_bulk_transfer(handle, VCHI_MEM_HANDLE_INVALID, ++ data, size, &waiter->bulk_waiter, VCHIQ_BULK_MODE_BLOCKING, ++ dir); ++ if ((status != VCHIQ_RETRY) || fatal_signal_pending(current) || ++ !waiter->bulk_waiter.bulk) { ++ VCHIQ_BULK_T *bulk = waiter->bulk_waiter.bulk; ++ if (bulk) { ++ /* Cancel the signal when the transfer ++ ** completes. */ ++ spin_lock(&bulk_waiter_spinlock); ++ bulk->userdata = NULL; ++ spin_unlock(&bulk_waiter_spinlock); ++ } ++ kfree(waiter); ++ } else { ++ waiter->pid = current->pid; ++ mutex_lock(&instance->bulk_waiter_list_mutex); ++ list_add(&waiter->list, &instance->bulk_waiter_list); ++ mutex_unlock(&instance->bulk_waiter_list_mutex); ++ vchiq_log_info(vchiq_arm_log_level, ++ "saved bulk_waiter %x for pid %d", ++ (unsigned int)waiter, current->pid); ++ } ++ ++ return status; ++} +diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_killable.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_killable.h +--- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_killable.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_killable.h 2015-11-29 09:42:38.075221210 +0100 +@@ -0,0 +1,69 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHIQ_KILLABLE_H ++#define VCHIQ_KILLABLE_H ++ ++#include ++#include ++ ++#define SHUTDOWN_SIGS (sigmask(SIGKILL) | sigmask(SIGINT) | sigmask(SIGQUIT) | sigmask(SIGTRAP) | sigmask(SIGSTOP) | sigmask(SIGCONT)) ++ ++static inline int __must_check down_interruptible_killable(struct semaphore *sem) ++{ ++ /* Allow interception of killable signals only. We don't want to be interrupted by harmless signals like SIGALRM */ ++ int ret; ++ sigset_t blocked, oldset; ++ siginitsetinv(&blocked, SHUTDOWN_SIGS); ++ sigprocmask(SIG_SETMASK, &blocked, &oldset); ++ ret = down_interruptible(sem); ++ sigprocmask(SIG_SETMASK, &oldset, NULL); ++ return ret; ++} ++#define down_interruptible down_interruptible_killable ++ ++ ++static inline int __must_check mutex_lock_interruptible_killable(struct mutex *lock) ++{ ++ /* Allow interception of killable signals only. We don't want to be interrupted by harmless signals like SIGALRM */ ++ int ret; ++ sigset_t blocked, oldset; ++ siginitsetinv(&blocked, SHUTDOWN_SIGS); ++ sigprocmask(SIG_SETMASK, &blocked, &oldset); ++ ret = mutex_lock_interruptible(lock); ++ sigprocmask(SIG_SETMASK, &oldset, NULL); ++ return ret; ++} ++#define mutex_lock_interruptible mutex_lock_interruptible_killable ++ ++#endif +diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_memdrv.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_memdrv.h +--- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_memdrv.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_memdrv.h 2015-11-29 09:42:38.075221210 +0100 +@@ -0,0 +1,71 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHIQ_MEMDRV_H ++#define VCHIQ_MEMDRV_H ++ ++/* ---- Include Files ----------------------------------------------------- */ ++ ++#include ++#include "vchiq_if.h" ++ ++/* ---- Constants and Types ---------------------------------------------- */ ++ ++typedef struct { ++ void *armSharedMemVirt; ++ dma_addr_t armSharedMemPhys; ++ size_t armSharedMemSize; ++ ++ void *vcSharedMemVirt; ++ dma_addr_t vcSharedMemPhys; ++ size_t vcSharedMemSize; ++} VCHIQ_SHARED_MEM_INFO_T; ++ ++/* ---- Variable Externs ------------------------------------------------- */ ++ ++/* ---- Function Prototypes ---------------------------------------------- */ ++ ++void vchiq_get_shared_mem_info(VCHIQ_SHARED_MEM_INFO_T *info); ++ ++VCHIQ_STATUS_T vchiq_memdrv_initialise(void); ++ ++VCHIQ_STATUS_T vchiq_userdrv_create_instance( ++ const VCHIQ_PLATFORM_DATA_T * platform_data); ++ ++VCHIQ_STATUS_T vchiq_userdrv_suspend( ++ const VCHIQ_PLATFORM_DATA_T * platform_data); ++ ++VCHIQ_STATUS_T vchiq_userdrv_resume( ++ const VCHIQ_PLATFORM_DATA_T * platform_data); ++ ++#endif +diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_pagelist.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_pagelist.h +--- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_pagelist.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_pagelist.h 2015-11-29 09:42:38.075221210 +0100 +@@ -0,0 +1,58 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHIQ_PAGELIST_H ++#define VCHIQ_PAGELIST_H ++ ++#ifndef PAGE_SIZE ++#define PAGE_SIZE 4096 ++#endif ++#define CACHE_LINE_SIZE 32 ++#define PAGELIST_WRITE 0 ++#define PAGELIST_READ 1 ++#define PAGELIST_READ_WITH_FRAGMENTS 2 ++ ++typedef struct pagelist_struct { ++ unsigned long length; ++ unsigned short type; ++ unsigned short offset; ++ unsigned long addrs[1]; /* N.B. 12 LSBs hold the number of following ++ pages at consecutive addresses. */ ++} PAGELIST_T; ++ ++typedef struct fragments_struct { ++ char headbuf[CACHE_LINE_SIZE]; ++ char tailbuf[CACHE_LINE_SIZE]; ++} FRAGMENTS_T; ++ ++#endif /* VCHIQ_PAGELIST_H */ +diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c +--- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c 2015-11-29 09:42:38.075221210 +0100 +@@ -0,0 +1,860 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++#include ++#include ++ ++#include "interface/vchi/vchi.h" ++#include "vchiq.h" ++#include "vchiq_core.h" ++ ++#include "vchiq_util.h" ++ ++#include ++ ++#define vchiq_status_to_vchi(status) ((int32_t)status) ++ ++typedef struct { ++ VCHIQ_SERVICE_HANDLE_T handle; ++ ++ VCHIU_QUEUE_T queue; ++ ++ VCHI_CALLBACK_T callback; ++ void *callback_param; ++} SHIM_SERVICE_T; ++ ++/* ---------------------------------------------------------------------- ++ * return pointer to the mphi message driver function table ++ * -------------------------------------------------------------------- */ ++const VCHI_MESSAGE_DRIVER_T * ++vchi_mphi_message_driver_func_table(void) ++{ ++ return NULL; ++} ++ ++/* ---------------------------------------------------------------------- ++ * return a pointer to the 'single' connection driver fops ++ * -------------------------------------------------------------------- */ ++const VCHI_CONNECTION_API_T * ++single_get_func_table(void) ++{ ++ return NULL; ++} ++ ++VCHI_CONNECTION_T *vchi_create_connection( ++ const VCHI_CONNECTION_API_T *function_table, ++ const VCHI_MESSAGE_DRIVER_T *low_level) ++{ ++ (void)function_table; ++ (void)low_level; ++ return NULL; ++} ++ ++/*********************************************************** ++ * Name: vchi_msg_peek ++ * ++ * Arguments: const VCHI_SERVICE_HANDLE_T handle, ++ * void **data, ++ * uint32_t *msg_size, ++ ++ ++ * VCHI_FLAGS_T flags ++ * ++ * Description: Routine to return a pointer to the current message (to allow in ++ * place processing). The message can be removed using ++ * vchi_msg_remove when you're finished ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t vchi_msg_peek(VCHI_SERVICE_HANDLE_T handle, ++ void **data, ++ uint32_t *msg_size, ++ VCHI_FLAGS_T flags) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_HEADER_T *header; ++ ++ WARN_ON((flags != VCHI_FLAGS_NONE) && ++ (flags != VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE)); ++ ++ if (flags == VCHI_FLAGS_NONE) ++ if (vchiu_queue_is_empty(&service->queue)) ++ return -1; ++ ++ header = vchiu_queue_peek(&service->queue); ++ ++ *data = header->data; ++ *msg_size = header->size; ++ ++ return 0; ++} ++EXPORT_SYMBOL(vchi_msg_peek); ++ ++/*********************************************************** ++ * Name: vchi_msg_remove ++ * ++ * Arguments: const VCHI_SERVICE_HANDLE_T handle, ++ * ++ * Description: Routine to remove a message (after it has been read with ++ * vchi_msg_peek) ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t vchi_msg_remove(VCHI_SERVICE_HANDLE_T handle) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_HEADER_T *header; ++ ++ header = vchiu_queue_pop(&service->queue); ++ ++ vchiq_release_message(service->handle, header); ++ ++ return 0; ++} ++EXPORT_SYMBOL(vchi_msg_remove); ++ ++/*********************************************************** ++ * Name: vchi_msg_queue ++ * ++ * Arguments: VCHI_SERVICE_HANDLE_T handle, ++ * const void *data, ++ * uint32_t data_size, ++ * VCHI_FLAGS_T flags, ++ * void *msg_handle, ++ * ++ * Description: Thin wrapper to queue a message onto a connection ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t vchi_msg_queue(VCHI_SERVICE_HANDLE_T handle, ++ const void *data, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void *msg_handle) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_ELEMENT_T element = {data, data_size}; ++ VCHIQ_STATUS_T status; ++ ++ (void)msg_handle; ++ ++ WARN_ON(flags != VCHI_FLAGS_BLOCK_UNTIL_QUEUED); ++ ++ status = vchiq_queue_message(service->handle, &element, 1); ++ ++ /* vchiq_queue_message() may return VCHIQ_RETRY, so we need to ++ ** implement a retry mechanism since this function is supposed ++ ** to block until queued ++ */ ++ while (status == VCHIQ_RETRY) { ++ msleep(1); ++ status = vchiq_queue_message(service->handle, &element, 1); ++ } ++ ++ return vchiq_status_to_vchi(status); ++} ++EXPORT_SYMBOL(vchi_msg_queue); ++ ++/*********************************************************** ++ * Name: vchi_bulk_queue_receive ++ * ++ * Arguments: VCHI_BULK_HANDLE_T handle, ++ * void *data_dst, ++ * const uint32_t data_size, ++ * VCHI_FLAGS_T flags ++ * void *bulk_handle ++ * ++ * Description: Routine to setup a rcv buffer ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t vchi_bulk_queue_receive(VCHI_SERVICE_HANDLE_T handle, ++ void *data_dst, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void *bulk_handle) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_BULK_MODE_T mode; ++ VCHIQ_STATUS_T status; ++ ++ switch ((int)flags) { ++ case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE ++ | VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ WARN_ON(!service->callback); ++ mode = VCHIQ_BULK_MODE_CALLBACK; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE: ++ mode = VCHIQ_BULK_MODE_BLOCKING; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ case VCHI_FLAGS_NONE: ++ mode = VCHIQ_BULK_MODE_NOCALLBACK; ++ break; ++ default: ++ WARN(1, "unsupported message\n"); ++ return vchiq_status_to_vchi(VCHIQ_ERROR); ++ } ++ ++ status = vchiq_bulk_receive(service->handle, data_dst, data_size, ++ bulk_handle, mode); ++ ++ /* vchiq_bulk_receive() may return VCHIQ_RETRY, so we need to ++ ** implement a retry mechanism since this function is supposed ++ ** to block until queued ++ */ ++ while (status == VCHIQ_RETRY) { ++ msleep(1); ++ status = vchiq_bulk_receive(service->handle, data_dst, ++ data_size, bulk_handle, mode); ++ } ++ ++ return vchiq_status_to_vchi(status); ++} ++EXPORT_SYMBOL(vchi_bulk_queue_receive); ++ ++/*********************************************************** ++ * Name: vchi_bulk_queue_transmit ++ * ++ * Arguments: VCHI_BULK_HANDLE_T handle, ++ * const void *data_src, ++ * uint32_t data_size, ++ * VCHI_FLAGS_T flags, ++ * void *bulk_handle ++ * ++ * Description: Routine to transmit some data ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t vchi_bulk_queue_transmit(VCHI_SERVICE_HANDLE_T handle, ++ const void *data_src, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void *bulk_handle) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_BULK_MODE_T mode; ++ VCHIQ_STATUS_T status; ++ ++ switch ((int)flags) { ++ case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE ++ | VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ WARN_ON(!service->callback); ++ mode = VCHIQ_BULK_MODE_CALLBACK; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_DATA_READ: ++ case VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE: ++ mode = VCHIQ_BULK_MODE_BLOCKING; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ case VCHI_FLAGS_NONE: ++ mode = VCHIQ_BULK_MODE_NOCALLBACK; ++ break; ++ default: ++ WARN(1, "unsupported message\n"); ++ return vchiq_status_to_vchi(VCHIQ_ERROR); ++ } ++ ++ status = vchiq_bulk_transmit(service->handle, data_src, data_size, ++ bulk_handle, mode); ++ ++ /* vchiq_bulk_transmit() may return VCHIQ_RETRY, so we need to ++ ** implement a retry mechanism since this function is supposed ++ ** to block until queued ++ */ ++ while (status == VCHIQ_RETRY) { ++ msleep(1); ++ status = vchiq_bulk_transmit(service->handle, data_src, ++ data_size, bulk_handle, mode); ++ } ++ ++ return vchiq_status_to_vchi(status); ++} ++EXPORT_SYMBOL(vchi_bulk_queue_transmit); ++ ++/*********************************************************** ++ * Name: vchi_msg_dequeue ++ * ++ * Arguments: VCHI_SERVICE_HANDLE_T handle, ++ * void *data, ++ * uint32_t max_data_size_to_read, ++ * uint32_t *actual_msg_size ++ * VCHI_FLAGS_T flags ++ * ++ * Description: Routine to dequeue a message into the supplied buffer ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t vchi_msg_dequeue(VCHI_SERVICE_HANDLE_T handle, ++ void *data, ++ uint32_t max_data_size_to_read, ++ uint32_t *actual_msg_size, ++ VCHI_FLAGS_T flags) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_HEADER_T *header; ++ ++ WARN_ON((flags != VCHI_FLAGS_NONE) && ++ (flags != VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE)); ++ ++ if (flags == VCHI_FLAGS_NONE) ++ if (vchiu_queue_is_empty(&service->queue)) ++ return -1; ++ ++ header = vchiu_queue_pop(&service->queue); ++ ++ memcpy(data, header->data, header->size < max_data_size_to_read ? ++ header->size : max_data_size_to_read); ++ ++ *actual_msg_size = header->size; ++ ++ vchiq_release_message(service->handle, header); ++ ++ return 0; ++} ++EXPORT_SYMBOL(vchi_msg_dequeue); ++ ++/*********************************************************** ++ * Name: vchi_msg_queuev ++ * ++ * Arguments: VCHI_SERVICE_HANDLE_T handle, ++ * VCHI_MSG_VECTOR_T *vector, ++ * uint32_t count, ++ * VCHI_FLAGS_T flags, ++ * void *msg_handle ++ * ++ * Description: Thin wrapper to queue a message onto a connection ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++ ++vchiq_static_assert(sizeof(VCHI_MSG_VECTOR_T) == sizeof(VCHIQ_ELEMENT_T)); ++vchiq_static_assert(offsetof(VCHI_MSG_VECTOR_T, vec_base) == ++ offsetof(VCHIQ_ELEMENT_T, data)); ++vchiq_static_assert(offsetof(VCHI_MSG_VECTOR_T, vec_len) == ++ offsetof(VCHIQ_ELEMENT_T, size)); ++ ++int32_t vchi_msg_queuev(VCHI_SERVICE_HANDLE_T handle, ++ VCHI_MSG_VECTOR_T *vector, ++ uint32_t count, ++ VCHI_FLAGS_T flags, ++ void *msg_handle) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ ++ (void)msg_handle; ++ ++ WARN_ON(flags != VCHI_FLAGS_BLOCK_UNTIL_QUEUED); ++ ++ return vchiq_status_to_vchi(vchiq_queue_message(service->handle, ++ (const VCHIQ_ELEMENT_T *)vector, count)); ++} ++EXPORT_SYMBOL(vchi_msg_queuev); ++ ++/*********************************************************** ++ * Name: vchi_held_msg_release ++ * ++ * Arguments: VCHI_HELD_MSG_T *message ++ * ++ * Description: Routine to release a held message (after it has been read with ++ * vchi_msg_hold) ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t vchi_held_msg_release(VCHI_HELD_MSG_T *message) ++{ ++ vchiq_release_message((VCHIQ_SERVICE_HANDLE_T)message->service, ++ (VCHIQ_HEADER_T *)message->message); ++ ++ return 0; ++} ++EXPORT_SYMBOL(vchi_held_msg_release); ++ ++/*********************************************************** ++ * Name: vchi_msg_hold ++ * ++ * Arguments: VCHI_SERVICE_HANDLE_T handle, ++ * void **data, ++ * uint32_t *msg_size, ++ * VCHI_FLAGS_T flags, ++ * VCHI_HELD_MSG_T *message_handle ++ * ++ * Description: Routine to return a pointer to the current message (to allow ++ * in place processing). The message is dequeued - don't forget ++ * to release the message using vchi_held_msg_release when you're ++ * finished. ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t vchi_msg_hold(VCHI_SERVICE_HANDLE_T handle, ++ void **data, ++ uint32_t *msg_size, ++ VCHI_FLAGS_T flags, ++ VCHI_HELD_MSG_T *message_handle) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_HEADER_T *header; ++ ++ WARN_ON((flags != VCHI_FLAGS_NONE) && ++ (flags != VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE)); ++ ++ if (flags == VCHI_FLAGS_NONE) ++ if (vchiu_queue_is_empty(&service->queue)) ++ return -1; ++ ++ header = vchiu_queue_pop(&service->queue); ++ ++ *data = header->data; ++ *msg_size = header->size; ++ ++ message_handle->service = ++ (struct opaque_vchi_service_t *)service->handle; ++ message_handle->message = header; ++ ++ return 0; ++} ++EXPORT_SYMBOL(vchi_msg_hold); ++ ++/*********************************************************** ++ * Name: vchi_initialise ++ * ++ * Arguments: VCHI_INSTANCE_T *instance_handle ++ * ++ * Description: Initialises the hardware but does not transmit anything ++ * When run as a Host App this will be called twice hence the need ++ * to malloc the state information ++ * ++ * Returns: 0 if successful, failure otherwise ++ * ++ ***********************************************************/ ++ ++int32_t vchi_initialise(VCHI_INSTANCE_T *instance_handle) ++{ ++ VCHIQ_INSTANCE_T instance; ++ VCHIQ_STATUS_T status; ++ ++ status = vchiq_initialise(&instance); ++ ++ *instance_handle = (VCHI_INSTANCE_T)instance; ++ ++ return vchiq_status_to_vchi(status); ++} ++EXPORT_SYMBOL(vchi_initialise); ++ ++/*********************************************************** ++ * Name: vchi_connect ++ * ++ * Arguments: VCHI_CONNECTION_T **connections ++ * const uint32_t num_connections ++ * VCHI_INSTANCE_T instance_handle) ++ * ++ * Description: Starts the command service on each connection, ++ * causing INIT messages to be pinged back and forth ++ * ++ * Returns: 0 if successful, failure otherwise ++ * ++ ***********************************************************/ ++int32_t vchi_connect(VCHI_CONNECTION_T **connections, ++ const uint32_t num_connections, ++ VCHI_INSTANCE_T instance_handle) ++{ ++ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle; ++ ++ (void)connections; ++ (void)num_connections; ++ ++ return vchiq_connect(instance); ++} ++EXPORT_SYMBOL(vchi_connect); ++ ++ ++/*********************************************************** ++ * Name: vchi_disconnect ++ * ++ * Arguments: VCHI_INSTANCE_T instance_handle ++ * ++ * Description: Stops the command service on each connection, ++ * causing DE-INIT messages to be pinged back and forth ++ * ++ * Returns: 0 if successful, failure otherwise ++ * ++ ***********************************************************/ ++int32_t vchi_disconnect(VCHI_INSTANCE_T instance_handle) ++{ ++ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle; ++ return vchiq_status_to_vchi(vchiq_shutdown(instance)); ++} ++EXPORT_SYMBOL(vchi_disconnect); ++ ++ ++/*********************************************************** ++ * Name: vchi_service_open ++ * Name: vchi_service_create ++ * ++ * Arguments: VCHI_INSTANCE_T *instance_handle ++ * SERVICE_CREATION_T *setup, ++ * VCHI_SERVICE_HANDLE_T *handle ++ * ++ * Description: Routine to open a service ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++ ++static VCHIQ_STATUS_T shim_callback(VCHIQ_REASON_T reason, ++ VCHIQ_HEADER_T *header, VCHIQ_SERVICE_HANDLE_T handle, void *bulk_user) ++{ ++ SHIM_SERVICE_T *service = ++ (SHIM_SERVICE_T *)VCHIQ_GET_SERVICE_USERDATA(handle); ++ ++ if (!service->callback) ++ goto release; ++ ++ switch (reason) { ++ case VCHIQ_MESSAGE_AVAILABLE: ++ vchiu_queue_push(&service->queue, header); ++ ++ service->callback(service->callback_param, ++ VCHI_CALLBACK_MSG_AVAILABLE, NULL); ++ ++ goto done; ++ break; ++ ++ case VCHIQ_BULK_TRANSMIT_DONE: ++ service->callback(service->callback_param, ++ VCHI_CALLBACK_BULK_SENT, bulk_user); ++ break; ++ ++ case VCHIQ_BULK_RECEIVE_DONE: ++ service->callback(service->callback_param, ++ VCHI_CALLBACK_BULK_RECEIVED, bulk_user); ++ break; ++ ++ case VCHIQ_SERVICE_CLOSED: ++ service->callback(service->callback_param, ++ VCHI_CALLBACK_SERVICE_CLOSED, NULL); ++ break; ++ ++ case VCHIQ_SERVICE_OPENED: ++ /* No equivalent VCHI reason */ ++ break; ++ ++ case VCHIQ_BULK_TRANSMIT_ABORTED: ++ service->callback(service->callback_param, ++ VCHI_CALLBACK_BULK_TRANSMIT_ABORTED, ++ bulk_user); ++ break; ++ ++ case VCHIQ_BULK_RECEIVE_ABORTED: ++ service->callback(service->callback_param, ++ VCHI_CALLBACK_BULK_RECEIVE_ABORTED, ++ bulk_user); ++ break; ++ ++ default: ++ WARN(1, "not supported\n"); ++ break; ++ } ++ ++release: ++ vchiq_release_message(service->handle, header); ++done: ++ return VCHIQ_SUCCESS; ++} ++ ++static SHIM_SERVICE_T *service_alloc(VCHIQ_INSTANCE_T instance, ++ SERVICE_CREATION_T *setup) ++{ ++ SHIM_SERVICE_T *service = kzalloc(sizeof(SHIM_SERVICE_T), GFP_KERNEL); ++ ++ (void)instance; ++ ++ if (service) { ++ if (vchiu_queue_init(&service->queue, 64)) { ++ service->callback = setup->callback; ++ service->callback_param = setup->callback_param; ++ } else { ++ kfree(service); ++ service = NULL; ++ } ++ } ++ ++ return service; ++} ++ ++static void service_free(SHIM_SERVICE_T *service) ++{ ++ if (service) { ++ vchiu_queue_delete(&service->queue); ++ kfree(service); ++ } ++} ++ ++int32_t vchi_service_open(VCHI_INSTANCE_T instance_handle, ++ SERVICE_CREATION_T *setup, ++ VCHI_SERVICE_HANDLE_T *handle) ++{ ++ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle; ++ SHIM_SERVICE_T *service = service_alloc(instance, setup); ++ ++ *handle = (VCHI_SERVICE_HANDLE_T)service; ++ ++ if (service) { ++ VCHIQ_SERVICE_PARAMS_T params; ++ VCHIQ_STATUS_T status; ++ ++ memset(¶ms, 0, sizeof(params)); ++ params.fourcc = setup->service_id; ++ params.callback = shim_callback; ++ params.userdata = service; ++ params.version = setup->version.version; ++ params.version_min = setup->version.version_min; ++ ++ status = vchiq_open_service(instance, ¶ms, ++ &service->handle); ++ if (status != VCHIQ_SUCCESS) { ++ service_free(service); ++ service = NULL; ++ *handle = NULL; ++ } ++ } ++ ++ return (service != NULL) ? 0 : -1; ++} ++EXPORT_SYMBOL(vchi_service_open); ++ ++int32_t vchi_service_create(VCHI_INSTANCE_T instance_handle, ++ SERVICE_CREATION_T *setup, ++ VCHI_SERVICE_HANDLE_T *handle) ++{ ++ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle; ++ SHIM_SERVICE_T *service = service_alloc(instance, setup); ++ ++ *handle = (VCHI_SERVICE_HANDLE_T)service; ++ ++ if (service) { ++ VCHIQ_SERVICE_PARAMS_T params; ++ VCHIQ_STATUS_T status; ++ ++ memset(¶ms, 0, sizeof(params)); ++ params.fourcc = setup->service_id; ++ params.callback = shim_callback; ++ params.userdata = service; ++ params.version = setup->version.version; ++ params.version_min = setup->version.version_min; ++ status = vchiq_add_service(instance, ¶ms, &service->handle); ++ ++ if (status != VCHIQ_SUCCESS) { ++ service_free(service); ++ service = NULL; ++ *handle = NULL; ++ } ++ } ++ ++ return (service != NULL) ? 0 : -1; ++} ++EXPORT_SYMBOL(vchi_service_create); ++ ++int32_t vchi_service_close(const VCHI_SERVICE_HANDLE_T handle) ++{ ++ int32_t ret = -1; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ if (service) { ++ VCHIQ_STATUS_T status = vchiq_close_service(service->handle); ++ if (status == VCHIQ_SUCCESS) { ++ service_free(service); ++ service = NULL; ++ } ++ ++ ret = vchiq_status_to_vchi(status); ++ } ++ return ret; ++} ++EXPORT_SYMBOL(vchi_service_close); ++ ++int32_t vchi_service_destroy(const VCHI_SERVICE_HANDLE_T handle) ++{ ++ int32_t ret = -1; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ if (service) { ++ VCHIQ_STATUS_T status = vchiq_remove_service(service->handle); ++ if (status == VCHIQ_SUCCESS) { ++ service_free(service); ++ service = NULL; ++ } ++ ++ ret = vchiq_status_to_vchi(status); ++ } ++ return ret; ++} ++EXPORT_SYMBOL(vchi_service_destroy); ++ ++int32_t vchi_service_set_option(const VCHI_SERVICE_HANDLE_T handle, ++ VCHI_SERVICE_OPTION_T option, ++ int value) ++{ ++ int32_t ret = -1; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_SERVICE_OPTION_T vchiq_option; ++ switch (option) { ++ case VCHI_SERVICE_OPTION_TRACE: ++ vchiq_option = VCHIQ_SERVICE_OPTION_TRACE; ++ break; ++ case VCHI_SERVICE_OPTION_SYNCHRONOUS: ++ vchiq_option = VCHIQ_SERVICE_OPTION_SYNCHRONOUS; ++ break; ++ default: ++ service = NULL; ++ break; ++ } ++ if (service) { ++ VCHIQ_STATUS_T status = ++ vchiq_set_service_option(service->handle, ++ vchiq_option, ++ value); ++ ++ ret = vchiq_status_to_vchi(status); ++ } ++ return ret; ++} ++EXPORT_SYMBOL(vchi_service_set_option); ++ ++int32_t vchi_get_peer_version( const VCHI_SERVICE_HANDLE_T handle, short *peer_version ) ++{ ++ int32_t ret = -1; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ if(service) ++ { ++ VCHIQ_STATUS_T status = vchiq_get_peer_version(service->handle, peer_version); ++ ret = vchiq_status_to_vchi( status ); ++ } ++ return ret; ++} ++EXPORT_SYMBOL(vchi_get_peer_version); ++ ++/* ---------------------------------------------------------------------- ++ * read a uint32_t from buffer. ++ * network format is defined to be little endian ++ * -------------------------------------------------------------------- */ ++uint32_t ++vchi_readbuf_uint32(const void *_ptr) ++{ ++ const unsigned char *ptr = _ptr; ++ return ptr[0] | (ptr[1] << 8) | (ptr[2] << 16) | (ptr[3] << 24); ++} ++ ++/* ---------------------------------------------------------------------- ++ * write a uint32_t to buffer. ++ * network format is defined to be little endian ++ * -------------------------------------------------------------------- */ ++void ++vchi_writebuf_uint32(void *_ptr, uint32_t value) ++{ ++ unsigned char *ptr = _ptr; ++ ptr[0] = (unsigned char)((value >> 0) & 0xFF); ++ ptr[1] = (unsigned char)((value >> 8) & 0xFF); ++ ptr[2] = (unsigned char)((value >> 16) & 0xFF); ++ ptr[3] = (unsigned char)((value >> 24) & 0xFF); ++} ++ ++/* ---------------------------------------------------------------------- ++ * read a uint16_t from buffer. ++ * network format is defined to be little endian ++ * -------------------------------------------------------------------- */ ++uint16_t ++vchi_readbuf_uint16(const void *_ptr) ++{ ++ const unsigned char *ptr = _ptr; ++ return ptr[0] | (ptr[1] << 8); ++} ++ ++/* ---------------------------------------------------------------------- ++ * write a uint16_t into the buffer. ++ * network format is defined to be little endian ++ * -------------------------------------------------------------------- */ ++void ++vchi_writebuf_uint16(void *_ptr, uint16_t value) ++{ ++ unsigned char *ptr = _ptr; ++ ptr[0] = (value >> 0) & 0xFF; ++ ptr[1] = (value >> 8) & 0xFF; ++} ++ ++/*********************************************************** ++ * Name: vchi_service_use ++ * ++ * Arguments: const VCHI_SERVICE_HANDLE_T handle ++ * ++ * Description: Routine to increment refcount on a service ++ * ++ * Returns: void ++ * ++ ***********************************************************/ ++int32_t vchi_service_use(const VCHI_SERVICE_HANDLE_T handle) ++{ ++ int32_t ret = -1; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ if (service) ++ ret = vchiq_status_to_vchi(vchiq_use_service(service->handle)); ++ return ret; ++} ++EXPORT_SYMBOL(vchi_service_use); ++ ++/*********************************************************** ++ * Name: vchi_service_release ++ * ++ * Arguments: const VCHI_SERVICE_HANDLE_T handle ++ * ++ * Description: Routine to decrement refcount on a service ++ * ++ * Returns: void ++ * ++ ***********************************************************/ ++int32_t vchi_service_release(const VCHI_SERVICE_HANDLE_T handle) ++{ ++ int32_t ret = -1; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ if (service) ++ ret = vchiq_status_to_vchi( ++ vchiq_release_service(service->handle)); ++ return ret; ++} ++EXPORT_SYMBOL(vchi_service_release); +diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c +--- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c 2015-11-29 09:42:38.075221210 +0100 +@@ -0,0 +1,156 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include "vchiq_util.h" ++#include "vchiq_killable.h" ++ ++static inline int is_pow2(int i) ++{ ++ return i && !(i & (i - 1)); ++} ++ ++int vchiu_queue_init(VCHIU_QUEUE_T *queue, int size) ++{ ++ WARN_ON(!is_pow2(size)); ++ ++ queue->size = size; ++ queue->read = 0; ++ queue->write = 0; ++ queue->initialized = 1; ++ ++ sema_init(&queue->pop, 0); ++ sema_init(&queue->push, 0); ++ ++ queue->storage = kzalloc(size * sizeof(VCHIQ_HEADER_T *), GFP_KERNEL); ++ if (queue->storage == NULL) { ++ vchiu_queue_delete(queue); ++ return 0; ++ } ++ return 1; ++} ++ ++void vchiu_queue_delete(VCHIU_QUEUE_T *queue) ++{ ++ if (queue->storage != NULL) ++ kfree(queue->storage); ++} ++ ++int vchiu_queue_is_empty(VCHIU_QUEUE_T *queue) ++{ ++ return queue->read == queue->write; ++} ++ ++int vchiu_queue_is_full(VCHIU_QUEUE_T *queue) ++{ ++ return queue->write == queue->read + queue->size; ++} ++ ++void vchiu_queue_push(VCHIU_QUEUE_T *queue, VCHIQ_HEADER_T *header) ++{ ++ if (!queue->initialized) ++ return; ++ ++ while (queue->write == queue->read + queue->size) { ++ if (down_interruptible(&queue->pop) != 0) { ++ flush_signals(current); ++ } ++ } ++ ++ /* ++ * Write to queue->storage must be visible after read from ++ * queue->read ++ */ ++ smp_mb(); ++ ++ queue->storage[queue->write & (queue->size - 1)] = header; ++ ++ /* ++ * Write to queue->storage must be visible before write to ++ * queue->write ++ */ ++ smp_wmb(); ++ ++ queue->write++; ++ ++ up(&queue->push); ++} ++ ++VCHIQ_HEADER_T *vchiu_queue_peek(VCHIU_QUEUE_T *queue) ++{ ++ while (queue->write == queue->read) { ++ if (down_interruptible(&queue->push) != 0) { ++ flush_signals(current); ++ } ++ } ++ ++ up(&queue->push); // We haven't removed anything from the queue. ++ ++ /* ++ * Read from queue->storage must be visible after read from ++ * queue->write ++ */ ++ smp_rmb(); ++ ++ return queue->storage[queue->read & (queue->size - 1)]; ++} ++ ++VCHIQ_HEADER_T *vchiu_queue_pop(VCHIU_QUEUE_T *queue) ++{ ++ VCHIQ_HEADER_T *header; ++ ++ while (queue->write == queue->read) { ++ if (down_interruptible(&queue->push) != 0) { ++ flush_signals(current); ++ } ++ } ++ ++ /* ++ * Read from queue->storage must be visible after read from ++ * queue->write ++ */ ++ smp_rmb(); ++ ++ header = queue->storage[queue->read & (queue->size - 1)]; ++ ++ /* ++ * Read from queue->storage must be visible before write to ++ * queue->read ++ */ ++ smp_mb(); ++ ++ queue->read++; ++ ++ up(&queue->pop); ++ ++ return header; ++} +diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.h linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.h +--- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.h 2015-11-29 09:42:38.075221210 +0100 +@@ -0,0 +1,82 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef VCHIQ_UTIL_H ++#define VCHIQ_UTIL_H ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* for time_t */ ++#include ++#include ++ ++#include "vchiq_if.h" ++ ++typedef struct { ++ int size; ++ int read; ++ int write; ++ int initialized; ++ ++ struct semaphore pop; ++ struct semaphore push; ++ ++ VCHIQ_HEADER_T **storage; ++} VCHIU_QUEUE_T; ++ ++extern int vchiu_queue_init(VCHIU_QUEUE_T *queue, int size); ++extern void vchiu_queue_delete(VCHIU_QUEUE_T *queue); ++ ++extern int vchiu_queue_is_empty(VCHIU_QUEUE_T *queue); ++extern int vchiu_queue_is_full(VCHIU_QUEUE_T *queue); ++ ++extern void vchiu_queue_push(VCHIU_QUEUE_T *queue, VCHIQ_HEADER_T *header); ++ ++extern VCHIQ_HEADER_T *vchiu_queue_peek(VCHIU_QUEUE_T *queue); ++extern VCHIQ_HEADER_T *vchiu_queue_pop(VCHIU_QUEUE_T *queue); ++ ++#endif +diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_version.c linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_version.c +--- linux-4.1.13.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_version.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_version.c 2015-11-29 09:42:38.075221210 +0100 +@@ -0,0 +1,59 @@ ++/** ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++#include "vchiq_build_info.h" ++#include ++ ++VC_DEBUG_DECLARE_STRING_VAR( vchiq_build_hostname, "dc4-arm-01" ); ++VC_DEBUG_DECLARE_STRING_VAR( vchiq_build_version, "9245b4c35b99b3870e1f7dc598c5692b3c66a6f0 (tainted)" ); ++VC_DEBUG_DECLARE_STRING_VAR( vchiq_build_time, __TIME__ ); ++VC_DEBUG_DECLARE_STRING_VAR( vchiq_build_date, __DATE__ ); ++ ++const char *vchiq_get_build_hostname( void ) ++{ ++ return vchiq_build_hostname; ++} ++ ++const char *vchiq_get_build_version( void ) ++{ ++ return vchiq_build_version; ++} ++ ++const char *vchiq_get_build_date( void ) ++{ ++ return vchiq_build_date; ++} ++ ++const char *vchiq_get_build_time( void ) ++{ ++ return vchiq_build_time; ++} +diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/Kconfig linux-rpi/drivers/misc/vc04_services/Kconfig +--- linux-4.1.13.orig/drivers/misc/vc04_services/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/misc/vc04_services/Kconfig 2015-11-29 09:42:38.059222273 +0100 +@@ -0,0 +1,9 @@ ++config BCM2708_VCHIQ ++ tristate "Videocore VCHIQ" ++ depends on RASPBERRYPI_FIRMWARE ++ default y ++ help ++ Kernel to VideoCore communication interface for the ++ BCM2708 family of products. ++ Defaults to Y when the Broadcom Videocore services ++ are included in the build, N otherwise. +diff -Nur linux-4.1.13.orig/drivers/misc/vc04_services/Makefile linux-rpi/drivers/misc/vc04_services/Makefile +--- linux-4.1.13.orig/drivers/misc/vc04_services/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/misc/vc04_services/Makefile 2015-11-29 09:42:38.059222273 +0100 +@@ -0,0 +1,14 @@ ++obj-$(CONFIG_BCM2708_VCHIQ) += vchiq.o ++ ++vchiq-objs := \ ++ interface/vchiq_arm/vchiq_core.o \ ++ interface/vchiq_arm/vchiq_arm.o \ ++ interface/vchiq_arm/vchiq_kern_lib.o \ ++ interface/vchiq_arm/vchiq_2835_arm.o \ ++ interface/vchiq_arm/vchiq_debugfs.o \ ++ interface/vchiq_arm/vchiq_shim.o \ ++ interface/vchiq_arm/vchiq_util.o \ ++ interface/vchiq_arm/vchiq_connected.o \ ++ ++ccflags-y += -DVCOS_VERIFY_BKPTS=1 -Idrivers/misc/vc04_services -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 ++ +diff -Nur linux-4.1.13.orig/drivers/mmc/card/block.c linux-rpi/drivers/mmc/card/block.c +--- linux-4.1.13.orig/drivers/mmc/card/block.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/mmc/card/block.c 2015-11-29 09:42:38.079220944 +0100 +@@ -1415,6 +1415,7 @@ + brq->data.blocks = card->host->ops->multi_io_quirk(card, + (rq_data_dir(req) == READ) ? + MMC_DATA_READ : MMC_DATA_WRITE, ++ blk_rq_pos(req), + brq->data.blocks); + } + +diff -Nur linux-4.1.13.orig/drivers/mmc/core/quirks.c linux-rpi/drivers/mmc/core/quirks.c +--- linux-4.1.13.orig/drivers/mmc/core/quirks.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/mmc/core/quirks.c 2015-11-29 09:42:38.083220679 +0100 +@@ -71,6 +71,7 @@ + + void mmc_fixup_device(struct mmc_card *card, const struct mmc_fixup *table) + { ++ extern unsigned mmc_debug; + const struct mmc_fixup *f; + u64 rev = cid_rev_card(card); + +@@ -95,5 +96,10 @@ + f->vendor_fixup(card, f->data); + } + } ++ /* SDHCI on BCM2708 - bug causes a certain sequence of CMD23 operations to fail. ++ * Disable this flag for all cards (fall-back to CMD25/CMD18 multi-block transfers). ++ */ ++ if (mmc_debug & (1<<13)) ++ card->quirks |= MMC_QUIRK_BLK_NO_CMD23; + } + EXPORT_SYMBOL(mmc_fixup_device); +diff -Nur linux-4.1.13.orig/drivers/mmc/host/bcm2835-mmc.c linux-rpi/drivers/mmc/host/bcm2835-mmc.c +--- linux-4.1.13.orig/drivers/mmc/host/bcm2835-mmc.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/mmc/host/bcm2835-mmc.c 2015-11-29 09:42:38.087220413 +0100 +@@ -0,0 +1,1559 @@ ++/* ++ * BCM2835 MMC host driver. ++ * ++ * Author: Gellert Weisz ++ * Copyright 2014 ++ * ++ * Based on ++ * sdhci-bcm2708.c by Broadcom ++ * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko ++ * sdhci.c and sdhci-pci.c by Pierre Ossman ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "sdhci.h" ++ ++ ++#define DRIVER_NAME "mmc-bcm2835" ++ ++#define DBG(f, x...) \ ++pr_debug(DRIVER_NAME " [%s()]: " f, __func__, ## x) ++ ++#ifndef CONFIG_MMC_BCM2835_DMA ++ #define FORCE_PIO ++#endif ++ ++ ++/* the inclusive limit in bytes under which PIO will be used instead of DMA */ ++#ifdef CONFIG_MMC_BCM2835_PIO_DMA_BARRIER ++#define PIO_DMA_BARRIER CONFIG_MMC_BCM2835_PIO_DMA_BARRIER ++#else ++#define PIO_DMA_BARRIER 00 ++#endif ++ ++#define MIN_FREQ 400000 ++#define TIMEOUT_VAL 0xE ++#define BCM2835_SDHCI_WRITE_DELAY(f) (((2 * 1000000) / f) + 1) ++ ++#ifndef BCM2708_PERI_BASE ++ #define BCM2708_PERI_BASE 0x20000000 ++#endif ++ ++/* FIXME: Needs IOMMU support */ ++#define BCM2835_VCMMU_SHIFT (0x7E000000 - BCM2708_PERI_BASE) ++ ++ ++unsigned mmc_debug; ++unsigned mmc_debug2; ++ ++struct bcm2835_host { ++ spinlock_t lock; ++ ++ void __iomem *ioaddr; ++ u32 phys_addr; ++ ++ struct mmc_host *mmc; ++ ++ u32 timeout; ++ ++ int clock; /* Current clock speed */ ++ u8 pwr; /* Current voltage */ ++ ++ unsigned int max_clk; /* Max possible freq */ ++ unsigned int timeout_clk; /* Timeout freq (KHz) */ ++ unsigned int clk_mul; /* Clock Muliplier value */ ++ ++ struct tasklet_struct finish_tasklet; /* Tasklet structures */ ++ ++ struct timer_list timer; /* Timer for timeouts */ ++ ++ struct sg_mapping_iter sg_miter; /* SG state for PIO */ ++ unsigned int blocks; /* remaining PIO blocks */ ++ ++ int irq; /* Device IRQ */ ++ ++ ++ u32 ier; /* cached registers */ ++ ++ struct mmc_request *mrq; /* Current request */ ++ struct mmc_command *cmd; /* Current command */ ++ struct mmc_data *data; /* Current data request */ ++ unsigned int data_early:1; /* Data finished before cmd */ ++ ++ wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */ ++ ++ u32 thread_isr; ++ ++ u32 shadow; ++ ++ /*DMA part*/ ++ struct dma_chan *dma_chan_rx; /* DMA channel for reads */ ++ struct dma_chan *dma_chan_tx; /* DMA channel for writes */ ++ struct dma_async_tx_descriptor *tx_desc; /* descriptor */ ++ ++ bool have_dma; ++ bool use_dma; ++ /*end of DMA part*/ ++ ++ int max_delay; /* maximum length of time spent waiting */ ++ ++ int flags; /* Host attributes */ ++#define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */ ++#define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */ ++#define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */ ++#define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */ ++#define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */ ++ ++ u32 overclock_50; /* frequency to use when 50MHz is requested (in MHz) */ ++ u32 max_overclock; /* Highest reported */ ++}; ++ ++ ++static inline void bcm2835_mmc_writel(struct bcm2835_host *host, u32 val, int reg, int from) ++{ ++ unsigned delay; ++ lockdep_assert_held_once(&host->lock); ++ writel(val, host->ioaddr + reg); ++ udelay(BCM2835_SDHCI_WRITE_DELAY(max(host->clock, MIN_FREQ))); ++ ++ delay = ((mmc_debug >> 16) & 0xf) << ((mmc_debug >> 20) & 0xf); ++ if (delay && !((1<lock); ++ writel(val, host->ioaddr + reg); ++ ++ delay = ((mmc_debug >> 24) & 0xf) << ((mmc_debug >> 28) & 0xf); ++ if (delay) ++ udelay(delay); ++} ++ ++static inline u32 bcm2835_mmc_readl(struct bcm2835_host *host, int reg) ++{ ++ lockdep_assert_held_once(&host->lock); ++ return readl(host->ioaddr + reg); ++} ++ ++static inline void bcm2835_mmc_writew(struct bcm2835_host *host, u16 val, int reg) ++{ ++ u32 oldval = (reg == SDHCI_COMMAND) ? host->shadow : ++ bcm2835_mmc_readl(host, reg & ~3); ++ u32 word_num = (reg >> 1) & 1; ++ u32 word_shift = word_num * 16; ++ u32 mask = 0xffff << word_shift; ++ u32 newval = (oldval & ~mask) | (val << word_shift); ++ ++ if (reg == SDHCI_TRANSFER_MODE) ++ host->shadow = newval; ++ else ++ bcm2835_mmc_writel(host, newval, reg & ~3, 0); ++ ++} ++ ++static inline void bcm2835_mmc_writeb(struct bcm2835_host *host, u8 val, int reg) ++{ ++ u32 oldval = bcm2835_mmc_readl(host, reg & ~3); ++ u32 byte_num = reg & 3; ++ u32 byte_shift = byte_num * 8; ++ u32 mask = 0xff << byte_shift; ++ u32 newval = (oldval & ~mask) | (val << byte_shift); ++ ++ bcm2835_mmc_writel(host, newval, reg & ~3, 1); ++} ++ ++ ++static inline u16 bcm2835_mmc_readw(struct bcm2835_host *host, int reg) ++{ ++ u32 val = bcm2835_mmc_readl(host, (reg & ~3)); ++ u32 word_num = (reg >> 1) & 1; ++ u32 word_shift = word_num * 16; ++ u32 word = (val >> word_shift) & 0xffff; ++ ++ return word; ++} ++ ++static inline u8 bcm2835_mmc_readb(struct bcm2835_host *host, int reg) ++{ ++ u32 val = bcm2835_mmc_readl(host, (reg & ~3)); ++ u32 byte_num = reg & 3; ++ u32 byte_shift = byte_num * 8; ++ u32 byte = (val >> byte_shift) & 0xff; ++ ++ return byte; ++} ++ ++static void bcm2835_mmc_unsignal_irqs(struct bcm2835_host *host, u32 clear) ++{ ++ u32 ier; ++ ++ ier = bcm2835_mmc_readl(host, SDHCI_SIGNAL_ENABLE); ++ ier &= ~clear; ++ /* change which requests generate IRQs - makes no difference to ++ the content of SDHCI_INT_STATUS, or the need to acknowledge IRQs */ ++ bcm2835_mmc_writel(host, ier, SDHCI_SIGNAL_ENABLE, 2); ++} ++ ++ ++static void bcm2835_mmc_dumpregs(struct bcm2835_host *host) ++{ ++ pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", ++ mmc_hostname(host->mmc)); ++ ++ pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", ++ bcm2835_mmc_readl(host, SDHCI_DMA_ADDRESS), ++ bcm2835_mmc_readw(host, SDHCI_HOST_VERSION)); ++ pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", ++ bcm2835_mmc_readw(host, SDHCI_BLOCK_SIZE), ++ bcm2835_mmc_readw(host, SDHCI_BLOCK_COUNT)); ++ pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", ++ bcm2835_mmc_readl(host, SDHCI_ARGUMENT), ++ bcm2835_mmc_readw(host, SDHCI_TRANSFER_MODE)); ++ pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", ++ bcm2835_mmc_readl(host, SDHCI_PRESENT_STATE), ++ bcm2835_mmc_readb(host, SDHCI_HOST_CONTROL)); ++ pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", ++ bcm2835_mmc_readb(host, SDHCI_POWER_CONTROL), ++ bcm2835_mmc_readb(host, SDHCI_BLOCK_GAP_CONTROL)); ++ pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", ++ bcm2835_mmc_readb(host, SDHCI_WAKE_UP_CONTROL), ++ bcm2835_mmc_readw(host, SDHCI_CLOCK_CONTROL)); ++ pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", ++ bcm2835_mmc_readb(host, SDHCI_TIMEOUT_CONTROL), ++ bcm2835_mmc_readl(host, SDHCI_INT_STATUS)); ++ pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", ++ bcm2835_mmc_readl(host, SDHCI_INT_ENABLE), ++ bcm2835_mmc_readl(host, SDHCI_SIGNAL_ENABLE)); ++ pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", ++ bcm2835_mmc_readw(host, SDHCI_ACMD12_ERR), ++ bcm2835_mmc_readw(host, SDHCI_SLOT_INT_STATUS)); ++ pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", ++ bcm2835_mmc_readl(host, SDHCI_CAPABILITIES), ++ bcm2835_mmc_readl(host, SDHCI_CAPABILITIES_1)); ++ pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", ++ bcm2835_mmc_readw(host, SDHCI_COMMAND), ++ bcm2835_mmc_readl(host, SDHCI_MAX_CURRENT)); ++ pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n", ++ bcm2835_mmc_readw(host, SDHCI_HOST_CONTROL2)); ++ ++ pr_debug(DRIVER_NAME ": ===========================================\n"); ++} ++ ++ ++static void bcm2835_mmc_reset(struct bcm2835_host *host, u8 mask) ++{ ++ unsigned long timeout; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&host->lock, flags); ++ bcm2835_mmc_writeb(host, mask, SDHCI_SOFTWARE_RESET); ++ ++ if (mask & SDHCI_RESET_ALL) ++ host->clock = 0; ++ ++ /* Wait max 100 ms */ ++ timeout = 100; ++ ++ /* hw clears the bit when it's done */ ++ while (bcm2835_mmc_readb(host, SDHCI_SOFTWARE_RESET) & mask) { ++ if (timeout == 0) { ++ pr_err("%s: Reset 0x%x never completed.\n", ++ mmc_hostname(host->mmc), (int)mask); ++ bcm2835_mmc_dumpregs(host); ++ return; ++ } ++ timeout--; ++ spin_unlock_irqrestore(&host->lock, flags); ++ mdelay(1); ++ spin_lock_irqsave(&host->lock, flags); ++ } ++ ++ if (100-timeout > 10 && 100-timeout > host->max_delay) { ++ host->max_delay = 100-timeout; ++ pr_warning("Warning: MMC controller hung for %d ms\n", host->max_delay); ++ } ++ spin_unlock_irqrestore(&host->lock, flags); ++} ++ ++static void bcm2835_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); ++ ++static void bcm2835_mmc_init(struct bcm2835_host *host, int soft) ++{ ++ unsigned long flags; ++ if (soft) ++ bcm2835_mmc_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); ++ else ++ bcm2835_mmc_reset(host, SDHCI_RESET_ALL); ++ ++ host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | ++ SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | ++ SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | ++ SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END | ++ SDHCI_INT_RESPONSE; ++ ++ spin_lock_irqsave(&host->lock, flags); ++ bcm2835_mmc_writel(host, host->ier, SDHCI_INT_ENABLE, 3); ++ bcm2835_mmc_writel(host, host->ier, SDHCI_SIGNAL_ENABLE, 3); ++ spin_unlock_irqrestore(&host->lock, flags); ++ ++ if (soft) { ++ /* force clock reconfiguration */ ++ host->clock = 0; ++ bcm2835_mmc_set_ios(host->mmc, &host->mmc->ios); ++ } ++} ++ ++ ++ ++static void bcm2835_mmc_finish_data(struct bcm2835_host *host); ++ ++static void bcm2835_mmc_dma_complete(void *param) ++{ ++ struct bcm2835_host *host = param; ++ struct dma_chan *dma_chan; ++ unsigned long flags; ++ u32 dir_data; ++ ++ spin_lock_irqsave(&host->lock, flags); ++ ++ if (host->data && !(host->data->flags & MMC_DATA_WRITE)) { ++ /* otherwise handled in SDHCI IRQ */ ++ dma_chan = host->dma_chan_rx; ++ dir_data = DMA_FROM_DEVICE; ++ ++ dma_unmap_sg(dma_chan->device->dev, ++ host->data->sg, host->data->sg_len, ++ dir_data); ++ ++ bcm2835_mmc_finish_data(host); ++ } ++ ++ spin_unlock_irqrestore(&host->lock, flags); ++} ++ ++static void bcm2835_bcm2835_mmc_read_block_pio(struct bcm2835_host *host) ++{ ++ unsigned long flags; ++ size_t blksize, len, chunk; ++ ++ u32 uninitialized_var(scratch); ++ u8 *buf; ++ ++ blksize = host->data->blksz; ++ chunk = 0; ++ ++ local_irq_save(flags); ++ ++ while (blksize) { ++ if (!sg_miter_next(&host->sg_miter)) ++ BUG(); ++ ++ len = min(host->sg_miter.length, blksize); ++ ++ blksize -= len; ++ host->sg_miter.consumed = len; ++ ++ buf = host->sg_miter.addr; ++ ++ while (len) { ++ if (chunk == 0) { ++ scratch = bcm2835_mmc_readl(host, SDHCI_BUFFER); ++ chunk = 4; ++ } ++ ++ *buf = scratch & 0xFF; ++ ++ buf++; ++ scratch >>= 8; ++ chunk--; ++ len--; ++ } ++ } ++ ++ sg_miter_stop(&host->sg_miter); ++ ++ local_irq_restore(flags); ++} ++ ++static void bcm2835_bcm2835_mmc_write_block_pio(struct bcm2835_host *host) ++{ ++ unsigned long flags; ++ size_t blksize, len, chunk; ++ u32 scratch; ++ u8 *buf; ++ ++ blksize = host->data->blksz; ++ chunk = 0; ++ chunk = 0; ++ scratch = 0; ++ ++ local_irq_save(flags); ++ ++ while (blksize) { ++ if (!sg_miter_next(&host->sg_miter)) ++ BUG(); ++ ++ len = min(host->sg_miter.length, blksize); ++ ++ blksize -= len; ++ host->sg_miter.consumed = len; ++ ++ buf = host->sg_miter.addr; ++ ++ while (len) { ++ scratch |= (u32)*buf << (chunk * 8); ++ ++ buf++; ++ chunk++; ++ len--; ++ ++ if ((chunk == 4) || ((len == 0) && (blksize == 0))) { ++ mmc_raw_writel(host, scratch, SDHCI_BUFFER); ++ chunk = 0; ++ scratch = 0; ++ } ++ } ++ } ++ ++ sg_miter_stop(&host->sg_miter); ++ ++ local_irq_restore(flags); ++} ++ ++ ++static void bcm2835_mmc_transfer_pio(struct bcm2835_host *host) ++{ ++ u32 mask; ++ ++ BUG_ON(!host->data); ++ ++ if (host->blocks == 0) ++ return; ++ ++ if (host->data->flags & MMC_DATA_READ) ++ mask = SDHCI_DATA_AVAILABLE; ++ else ++ mask = SDHCI_SPACE_AVAILABLE; ++ ++ while (bcm2835_mmc_readl(host, SDHCI_PRESENT_STATE) & mask) { ++ ++ if (host->data->flags & MMC_DATA_READ) ++ bcm2835_bcm2835_mmc_read_block_pio(host); ++ else ++ bcm2835_bcm2835_mmc_write_block_pio(host); ++ ++ host->blocks--; ++ ++ /* QUIRK used in sdhci.c removes the 'if' */ ++ /* but it seems this is unnecessary */ ++ if (host->blocks == 0) ++ break; ++ ++ ++ } ++} ++ ++ ++static void bcm2835_mmc_transfer_dma(struct bcm2835_host *host) ++{ ++ u32 len, dir_data, dir_slave; ++ struct dma_async_tx_descriptor *desc = NULL; ++ struct dma_chan *dma_chan; ++ ++ ++ WARN_ON(!host->data); ++ ++ if (!host->data) ++ return; ++ ++ if (host->blocks == 0) ++ return; ++ ++ if (host->data->flags & MMC_DATA_READ) { ++ dma_chan = host->dma_chan_rx; ++ dir_data = DMA_FROM_DEVICE; ++ dir_slave = DMA_DEV_TO_MEM; ++ } else { ++ dma_chan = host->dma_chan_tx; ++ dir_data = DMA_TO_DEVICE; ++ dir_slave = DMA_MEM_TO_DEV; ++ } ++ ++ BUG_ON(!dma_chan->device); ++ BUG_ON(!dma_chan->device->dev); ++ BUG_ON(!host->data->sg); ++ ++ len = dma_map_sg(dma_chan->device->dev, host->data->sg, ++ host->data->sg_len, dir_data); ++ if (len > 0) { ++ desc = dmaengine_prep_slave_sg(dma_chan, host->data->sg, ++ len, dir_slave, ++ DMA_PREP_INTERRUPT | DMA_CTRL_ACK); ++ } else { ++ dev_err(mmc_dev(host->mmc), "dma_map_sg returned zero length\n"); ++ } ++ if (desc) { ++ unsigned long flags; ++ spin_lock_irqsave(&host->lock, flags); ++ bcm2835_mmc_unsignal_irqs(host, SDHCI_INT_DATA_AVAIL | ++ SDHCI_INT_SPACE_AVAIL); ++ host->tx_desc = desc; ++ desc->callback = bcm2835_mmc_dma_complete; ++ desc->callback_param = host; ++ spin_unlock_irqrestore(&host->lock, flags); ++ dmaengine_submit(desc); ++ dma_async_issue_pending(dma_chan); ++ } ++ ++} ++ ++ ++ ++static void bcm2835_mmc_set_transfer_irqs(struct bcm2835_host *host) ++{ ++ u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; ++ u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; ++ ++ if (host->use_dma) ++ host->ier = (host->ier & ~pio_irqs) | dma_irqs; ++ else ++ host->ier = (host->ier & ~dma_irqs) | pio_irqs; ++ ++ bcm2835_mmc_writel(host, host->ier, SDHCI_INT_ENABLE, 4); ++ bcm2835_mmc_writel(host, host->ier, SDHCI_SIGNAL_ENABLE, 4); ++} ++ ++ ++static void bcm2835_mmc_prepare_data(struct bcm2835_host *host, struct mmc_command *cmd) ++{ ++ u8 count; ++ struct mmc_data *data = cmd->data; ++ ++ WARN_ON(host->data); ++ ++ if (data || (cmd->flags & MMC_RSP_BUSY)) { ++ count = TIMEOUT_VAL; ++ bcm2835_mmc_writeb(host, count, SDHCI_TIMEOUT_CONTROL); ++ } ++ ++ if (!data) ++ return; ++ ++ /* Sanity checks */ ++ BUG_ON(data->blksz * data->blocks > 524288); ++ BUG_ON(data->blksz > host->mmc->max_blk_size); ++ BUG_ON(data->blocks > 65535); ++ ++ host->data = data; ++ host->data_early = 0; ++ host->data->bytes_xfered = 0; ++ ++ ++ if (!(host->flags & SDHCI_REQ_USE_DMA)) { ++ int flags; ++ ++ flags = SG_MITER_ATOMIC; ++ if (host->data->flags & MMC_DATA_READ) ++ flags |= SG_MITER_TO_SG; ++ else ++ flags |= SG_MITER_FROM_SG; ++ sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); ++ host->blocks = data->blocks; ++ } ++ ++ host->use_dma = host->have_dma && data->blocks > PIO_DMA_BARRIER; ++ ++ bcm2835_mmc_set_transfer_irqs(host); ++ ++ /* Set the DMA boundary value and block size */ ++ bcm2835_mmc_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, ++ data->blksz), SDHCI_BLOCK_SIZE); ++ bcm2835_mmc_writew(host, data->blocks, SDHCI_BLOCK_COUNT); ++ ++ BUG_ON(!host->data); ++} ++ ++static void bcm2835_mmc_set_transfer_mode(struct bcm2835_host *host, ++ struct mmc_command *cmd) ++{ ++ u16 mode; ++ struct mmc_data *data = cmd->data; ++ ++ if (data == NULL) { ++ /* clear Auto CMD settings for no data CMDs */ ++ mode = bcm2835_mmc_readw(host, SDHCI_TRANSFER_MODE); ++ bcm2835_mmc_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 | ++ SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE); ++ return; ++ } ++ ++ WARN_ON(!host->data); ++ ++ mode = SDHCI_TRNS_BLK_CNT_EN; ++ ++ if ((mmc_op_multi(cmd->opcode) || data->blocks > 1)) { ++ mode |= SDHCI_TRNS_MULTI; ++ ++ /* ++ * If we are sending CMD23, CMD12 never gets sent ++ * on successful completion (so no Auto-CMD12). ++ */ ++ if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) ++ mode |= SDHCI_TRNS_AUTO_CMD12; ++ else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { ++ mode |= SDHCI_TRNS_AUTO_CMD23; ++ bcm2835_mmc_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2, 5); ++ } ++ } ++ ++ if (data->flags & MMC_DATA_READ) ++ mode |= SDHCI_TRNS_READ; ++ if (host->flags & SDHCI_REQ_USE_DMA) ++ mode |= SDHCI_TRNS_DMA; ++ ++ bcm2835_mmc_writew(host, mode, SDHCI_TRANSFER_MODE); ++} ++ ++void bcm2835_mmc_send_command(struct bcm2835_host *host, struct mmc_command *cmd) ++{ ++ int flags; ++ u32 mask; ++ unsigned long timeout; ++ ++ WARN_ON(host->cmd); ++ ++ /* Wait max 10 ms */ ++ timeout = 1000; ++ ++ mask = SDHCI_CMD_INHIBIT; ++ if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) ++ mask |= SDHCI_DATA_INHIBIT; ++ ++ /* We shouldn't wait for data inihibit for stop commands, even ++ though they might use busy signaling */ ++ if (host->mrq->data && (cmd == host->mrq->data->stop)) ++ mask &= ~SDHCI_DATA_INHIBIT; ++ ++ while (bcm2835_mmc_readl(host, SDHCI_PRESENT_STATE) & mask) { ++ if (timeout == 0) { ++ pr_err("%s: Controller never released inhibit bit(s).\n", ++ mmc_hostname(host->mmc)); ++ bcm2835_mmc_dumpregs(host); ++ cmd->error = -EIO; ++ tasklet_schedule(&host->finish_tasklet); ++ return; ++ } ++ timeout--; ++ udelay(10); ++ } ++ ++ if ((1000-timeout)/100 > 1 && (1000-timeout)/100 > host->max_delay) { ++ host->max_delay = (1000-timeout)/100; ++ pr_warning("Warning: MMC controller hung for %d ms\n", host->max_delay); ++ } ++ ++ timeout = jiffies; ++#ifdef CONFIG_ARCH_BCM2835 ++ if (!cmd->data && cmd->busy_timeout > 9000) ++ timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; ++ else ++#endif ++ timeout += 10 * HZ; ++ mod_timer(&host->timer, timeout); ++ ++ host->cmd = cmd; ++ ++ bcm2835_mmc_prepare_data(host, cmd); ++ ++ bcm2835_mmc_writel(host, cmd->arg, SDHCI_ARGUMENT, 6); ++ ++ bcm2835_mmc_set_transfer_mode(host, cmd); ++ ++ if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { ++ pr_err("%s: Unsupported response type!\n", ++ mmc_hostname(host->mmc)); ++ cmd->error = -EINVAL; ++ tasklet_schedule(&host->finish_tasklet); ++ return; ++ } ++ ++ if (!(cmd->flags & MMC_RSP_PRESENT)) ++ flags = SDHCI_CMD_RESP_NONE; ++ else if (cmd->flags & MMC_RSP_136) ++ flags = SDHCI_CMD_RESP_LONG; ++ else if (cmd->flags & MMC_RSP_BUSY) ++ flags = SDHCI_CMD_RESP_SHORT_BUSY; ++ else ++ flags = SDHCI_CMD_RESP_SHORT; ++ ++ if (cmd->flags & MMC_RSP_CRC) ++ flags |= SDHCI_CMD_CRC; ++ if (cmd->flags & MMC_RSP_OPCODE) ++ flags |= SDHCI_CMD_INDEX; ++ ++ if (cmd->data) ++ flags |= SDHCI_CMD_DATA; ++ ++ bcm2835_mmc_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); ++} ++ ++ ++static void bcm2835_mmc_finish_data(struct bcm2835_host *host) ++{ ++ struct mmc_data *data; ++ ++ BUG_ON(!host->data); ++ ++ data = host->data; ++ host->data = NULL; ++ ++ if (data->error) ++ data->bytes_xfered = 0; ++ else ++ data->bytes_xfered = data->blksz * data->blocks; ++ ++ /* ++ * Need to send CMD12 if - ++ * a) open-ended multiblock transfer (no CMD23) ++ * b) error in multiblock transfer ++ */ ++ if (data->stop && ++ (data->error || ++ !host->mrq->sbc)) { ++ ++ /* ++ * The controller needs a reset of internal state machines ++ * upon error conditions. ++ */ ++ if (data->error) { ++ bcm2835_mmc_reset(host, SDHCI_RESET_CMD); ++ bcm2835_mmc_reset(host, SDHCI_RESET_DATA); ++ } ++ ++ bcm2835_mmc_send_command(host, data->stop); ++ } else ++ tasklet_schedule(&host->finish_tasklet); ++} ++ ++static void bcm2835_mmc_finish_command(struct bcm2835_host *host) ++{ ++ int i; ++ ++ BUG_ON(host->cmd == NULL); ++ ++ if (host->cmd->flags & MMC_RSP_PRESENT) { ++ if (host->cmd->flags & MMC_RSP_136) { ++ /* CRC is stripped so we need to do some shifting. */ ++ for (i = 0; i < 4; i++) { ++ host->cmd->resp[i] = bcm2835_mmc_readl(host, ++ SDHCI_RESPONSE + (3-i)*4) << 8; ++ if (i != 3) ++ host->cmd->resp[i] |= ++ bcm2835_mmc_readb(host, ++ SDHCI_RESPONSE + (3-i)*4-1); ++ } ++ } else { ++ host->cmd->resp[0] = bcm2835_mmc_readl(host, SDHCI_RESPONSE); ++ } ++ } ++ ++ host->cmd->error = 0; ++ ++ /* Finished CMD23, now send actual command. */ ++ if (host->cmd == host->mrq->sbc) { ++ host->cmd = NULL; ++ bcm2835_mmc_send_command(host, host->mrq->cmd); ++ ++ if (host->mrq->cmd->data && host->use_dma) { ++ /* DMA transfer starts now, PIO starts after interrupt */ ++ bcm2835_mmc_transfer_dma(host); ++ } ++ } else { ++ ++ /* Processed actual command. */ ++ if (host->data && host->data_early) ++ bcm2835_mmc_finish_data(host); ++ ++ if (!host->cmd->data) ++ tasklet_schedule(&host->finish_tasklet); ++ ++ host->cmd = NULL; ++ } ++} ++ ++ ++static void bcm2835_mmc_timeout_timer(unsigned long data) ++{ ++ struct bcm2835_host *host; ++ unsigned long flags; ++ ++ host = (struct bcm2835_host *)data; ++ ++ spin_lock_irqsave(&host->lock, flags); ++ ++ if (host->mrq) { ++ pr_err("%s: Timeout waiting for hardware interrupt.\n", ++ mmc_hostname(host->mmc)); ++ bcm2835_mmc_dumpregs(host); ++ ++ if (host->data) { ++ host->data->error = -ETIMEDOUT; ++ bcm2835_mmc_finish_data(host); ++ } else { ++ if (host->cmd) ++ host->cmd->error = -ETIMEDOUT; ++ else ++ host->mrq->cmd->error = -ETIMEDOUT; ++ ++ tasklet_schedule(&host->finish_tasklet); ++ } ++ } ++ ++ mmiowb(); ++ spin_unlock_irqrestore(&host->lock, flags); ++} ++ ++ ++static void bcm2835_mmc_enable_sdio_irq_nolock(struct bcm2835_host *host, int enable) ++{ ++ if (!(host->flags & SDHCI_DEVICE_DEAD)) { ++ if (enable) ++ host->ier |= SDHCI_INT_CARD_INT; ++ else ++ host->ier &= ~SDHCI_INT_CARD_INT; ++ ++ bcm2835_mmc_writel(host, host->ier, SDHCI_INT_ENABLE, 7); ++ bcm2835_mmc_writel(host, host->ier, SDHCI_SIGNAL_ENABLE, 7); ++ mmiowb(); ++ } ++} ++ ++static void bcm2835_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) ++{ ++ struct bcm2835_host *host = mmc_priv(mmc); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&host->lock, flags); ++ if (enable) ++ host->flags |= SDHCI_SDIO_IRQ_ENABLED; ++ else ++ host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; ++ ++ bcm2835_mmc_enable_sdio_irq_nolock(host, enable); ++ spin_unlock_irqrestore(&host->lock, flags); ++} ++ ++static void bcm2835_mmc_cmd_irq(struct bcm2835_host *host, u32 intmask) ++{ ++ ++ BUG_ON(intmask == 0); ++ ++ if (!host->cmd) { ++ pr_err("%s: Got command interrupt 0x%08x even " ++ "though no command operation was in progress.\n", ++ mmc_hostname(host->mmc), (unsigned)intmask); ++ bcm2835_mmc_dumpregs(host); ++ return; ++ } ++ ++ if (intmask & SDHCI_INT_TIMEOUT) ++ host->cmd->error = -ETIMEDOUT; ++ else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT | ++ SDHCI_INT_INDEX)) { ++ host->cmd->error = -EILSEQ; ++ } ++ ++ if (host->cmd->error) { ++ tasklet_schedule(&host->finish_tasklet); ++ return; ++ } ++ ++ if (intmask & SDHCI_INT_RESPONSE) ++ bcm2835_mmc_finish_command(host); ++ ++} ++ ++static void bcm2835_mmc_data_irq(struct bcm2835_host *host, u32 intmask) ++{ ++ struct dma_chan *dma_chan; ++ u32 dir_data; ++ ++ BUG_ON(intmask == 0); ++ ++ if (!host->data) { ++ /* ++ * The "data complete" interrupt is also used to ++ * indicate that a busy state has ended. See comment ++ * above in sdhci_cmd_irq(). ++ */ ++ if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { ++ if (intmask & SDHCI_INT_DATA_END) { ++ bcm2835_mmc_finish_command(host); ++ return; ++ } ++ } ++ ++ pr_debug("%s: Got data interrupt 0x%08x even " ++ "though no data operation was in progress.\n", ++ mmc_hostname(host->mmc), (unsigned)intmask); ++ bcm2835_mmc_dumpregs(host); ++ ++ return; ++ } ++ ++ if (intmask & SDHCI_INT_DATA_TIMEOUT) ++ host->data->error = -ETIMEDOUT; ++ else if (intmask & SDHCI_INT_DATA_END_BIT) ++ host->data->error = -EILSEQ; ++ else if ((intmask & SDHCI_INT_DATA_CRC) && ++ SDHCI_GET_CMD(bcm2835_mmc_readw(host, SDHCI_COMMAND)) ++ != MMC_BUS_TEST_R) ++ host->data->error = -EILSEQ; ++ ++ if (host->use_dma) { ++ if (host->data->flags & MMC_DATA_WRITE) { ++ /* IRQ handled here */ ++ ++ dma_chan = host->dma_chan_tx; ++ dir_data = DMA_TO_DEVICE; ++ dma_unmap_sg(dma_chan->device->dev, ++ host->data->sg, host->data->sg_len, ++ dir_data); ++ ++ bcm2835_mmc_finish_data(host); ++ } ++ ++ } else { ++ if (host->data->error) ++ bcm2835_mmc_finish_data(host); ++ else { ++ if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) ++ bcm2835_mmc_transfer_pio(host); ++ ++ if (intmask & SDHCI_INT_DATA_END) { ++ if (host->cmd) { ++ /* ++ * Data managed to finish before the ++ * command completed. Make sure we do ++ * things in the proper order. ++ */ ++ host->data_early = 1; ++ } else { ++ bcm2835_mmc_finish_data(host); ++ } ++ } ++ } ++ } ++} ++ ++ ++static irqreturn_t bcm2835_mmc_irq(int irq, void *dev_id) ++{ ++ irqreturn_t result = IRQ_NONE; ++ struct bcm2835_host *host = dev_id; ++ u32 intmask, mask, unexpected = 0; ++ int max_loops = 16; ++#ifndef CONFIG_ARCH_BCM2835 ++ int cardint = 0; ++#endif ++ ++ spin_lock(&host->lock); ++ ++ intmask = bcm2835_mmc_readl(host, SDHCI_INT_STATUS); ++ ++ if (!intmask || intmask == 0xffffffff) { ++ result = IRQ_NONE; ++ goto out; ++ } ++ ++ do { ++ /* Clear selected interrupts. */ ++ mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | ++ SDHCI_INT_BUS_POWER); ++ bcm2835_mmc_writel(host, mask, SDHCI_INT_STATUS, 8); ++ ++ ++ if (intmask & SDHCI_INT_CMD_MASK) ++ bcm2835_mmc_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); ++ ++ if (intmask & SDHCI_INT_DATA_MASK) ++ bcm2835_mmc_data_irq(host, intmask & SDHCI_INT_DATA_MASK); ++ ++ if (intmask & SDHCI_INT_BUS_POWER) ++ pr_err("%s: Card is consuming too much power!\n", ++ mmc_hostname(host->mmc)); ++ ++ if (intmask & SDHCI_INT_CARD_INT) { ++#ifndef CONFIG_ARCH_BCM2835 ++ cardint = 1; ++#else ++ bcm2835_mmc_enable_sdio_irq_nolock(host, false); ++ host->thread_isr |= SDHCI_INT_CARD_INT; ++ result = IRQ_WAKE_THREAD; ++#endif ++ } ++ ++ intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | ++ SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | ++ SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER | ++ SDHCI_INT_CARD_INT); ++ ++ if (intmask) { ++ unexpected |= intmask; ++ bcm2835_mmc_writel(host, intmask, SDHCI_INT_STATUS, 9); ++ } ++ ++ if (result == IRQ_NONE) ++ result = IRQ_HANDLED; ++ ++ intmask = bcm2835_mmc_readl(host, SDHCI_INT_STATUS); ++ } while (intmask && --max_loops); ++out: ++ spin_unlock(&host->lock); ++ ++ if (unexpected) { ++ pr_err("%s: Unexpected interrupt 0x%08x.\n", ++ mmc_hostname(host->mmc), unexpected); ++ bcm2835_mmc_dumpregs(host); ++ } ++ ++#ifndef CONFIG_ARCH_BCM2835 ++ if (cardint) ++ mmc_signal_sdio_irq(host->mmc); ++#endif ++ ++ return result; ++} ++ ++#ifdef CONFIG_ARCH_BCM2835 ++static irqreturn_t bcm2835_mmc_thread_irq(int irq, void *dev_id) ++{ ++ struct bcm2835_host *host = dev_id; ++ unsigned long flags; ++ u32 isr; ++ ++ spin_lock_irqsave(&host->lock, flags); ++ isr = host->thread_isr; ++ host->thread_isr = 0; ++ spin_unlock_irqrestore(&host->lock, flags); ++ ++ if (isr & SDHCI_INT_CARD_INT) { ++ sdio_run_irqs(host->mmc); ++ ++ spin_lock_irqsave(&host->lock, flags); ++ if (host->flags & SDHCI_SDIO_IRQ_ENABLED) ++ bcm2835_mmc_enable_sdio_irq_nolock(host, true); ++ spin_unlock_irqrestore(&host->lock, flags); ++ } ++ ++ return isr ? IRQ_HANDLED : IRQ_NONE; ++} ++#endif ++ ++ ++ ++void bcm2835_mmc_set_clock(struct bcm2835_host *host, unsigned int clock) ++{ ++ int div = 0; /* Initialized for compiler warning */ ++ int real_div = div, clk_mul = 1; ++ u16 clk = 0; ++ unsigned long timeout; ++ unsigned int input_clock = clock; ++ ++ if (host->overclock_50 && (clock == 50000000)) ++ clock = host->overclock_50 * 1000000 + 999999; ++ ++ host->mmc->actual_clock = 0; ++ ++ bcm2835_mmc_writew(host, 0, SDHCI_CLOCK_CONTROL); ++ ++ if (clock == 0) ++ return; ++ ++ /* Version 3.00 divisors must be a multiple of 2. */ ++ if (host->max_clk <= clock) ++ div = 1; ++ else { ++ for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; ++ div += 2) { ++ if ((host->max_clk / div) <= clock) ++ break; ++ } ++ } ++ ++ real_div = div; ++ div >>= 1; ++ ++ if (real_div) ++ clock = (host->max_clk * clk_mul) / real_div; ++ host->mmc->actual_clock = clock; ++ ++ if ((clock > input_clock) && (clock > host->max_overclock)) { ++ pr_warn("%s: Overclocking to %dHz\n", ++ mmc_hostname(host->mmc), clock); ++ host->max_overclock = clock; ++ } ++ ++ clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; ++ clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) ++ << SDHCI_DIVIDER_HI_SHIFT; ++ clk |= SDHCI_CLOCK_INT_EN; ++ bcm2835_mmc_writew(host, clk, SDHCI_CLOCK_CONTROL); ++ ++ /* Wait max 20 ms */ ++ timeout = 20; ++ while (!((clk = bcm2835_mmc_readw(host, SDHCI_CLOCK_CONTROL)) ++ & SDHCI_CLOCK_INT_STABLE)) { ++ if (timeout == 0) { ++ pr_err("%s: Internal clock never " ++ "stabilised.\n", mmc_hostname(host->mmc)); ++ bcm2835_mmc_dumpregs(host); ++ return; ++ } ++ timeout--; ++ mdelay(1); ++ } ++ ++ if (20-timeout > 10 && 20-timeout > host->max_delay) { ++ host->max_delay = 20-timeout; ++ pr_warning("Warning: MMC controller hung for %d ms\n", host->max_delay); ++ } ++ ++ clk |= SDHCI_CLOCK_CARD_EN; ++ bcm2835_mmc_writew(host, clk, SDHCI_CLOCK_CONTROL); ++} ++ ++static void bcm2835_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) ++{ ++ struct bcm2835_host *host; ++ unsigned long flags; ++ ++ host = mmc_priv(mmc); ++ ++ spin_lock_irqsave(&host->lock, flags); ++ ++ WARN_ON(host->mrq != NULL); ++ ++ host->mrq = mrq; ++ ++ if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) ++ bcm2835_mmc_send_command(host, mrq->sbc); ++ else ++ bcm2835_mmc_send_command(host, mrq->cmd); ++ ++ mmiowb(); ++ spin_unlock_irqrestore(&host->lock, flags); ++ ++ if (!(mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) && mrq->cmd->data && host->use_dma) { ++ /* DMA transfer starts now, PIO starts after interrupt */ ++ bcm2835_mmc_transfer_dma(host); ++ } ++} ++ ++ ++static void bcm2835_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) ++{ ++ ++ struct bcm2835_host *host = mmc_priv(mmc); ++ unsigned long flags; ++ u8 ctrl; ++ u16 clk, ctrl_2; ++ ++ pr_debug("bcm2835_mmc_set_ios: clock %d, pwr %d, bus_width %d, timing %d, vdd %d, drv_type %d\n", ++ ios->clock, ios->power_mode, ios->bus_width, ++ ios->timing, ios->signal_voltage, ios->drv_type); ++ ++ spin_lock_irqsave(&host->lock, flags); ++ ++ if (!ios->clock || ios->clock != host->clock) { ++ bcm2835_mmc_set_clock(host, ios->clock); ++ host->clock = ios->clock; ++ } ++ ++ if (host->pwr != SDHCI_POWER_330) { ++ host->pwr = SDHCI_POWER_330; ++ bcm2835_mmc_writeb(host, SDHCI_POWER_330 | SDHCI_POWER_ON, SDHCI_POWER_CONTROL); ++ } ++ ++ ctrl = bcm2835_mmc_readb(host, SDHCI_HOST_CONTROL); ++ ++ /* set bus width */ ++ ctrl &= ~SDHCI_CTRL_8BITBUS; ++ if (ios->bus_width == MMC_BUS_WIDTH_4) ++ ctrl |= SDHCI_CTRL_4BITBUS; ++ else ++ ctrl &= ~SDHCI_CTRL_4BITBUS; ++ ++ ctrl &= ~SDHCI_CTRL_HISPD; /* NO_HISPD_BIT */ ++ ++ ++ bcm2835_mmc_writeb(host, ctrl, SDHCI_HOST_CONTROL); ++ /* ++ * We only need to set Driver Strength if the ++ * preset value enable is not set. ++ */ ++ ctrl_2 = bcm2835_mmc_readw(host, SDHCI_HOST_CONTROL2); ++ ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; ++ if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) ++ ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; ++ else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) ++ ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; ++ ++ bcm2835_mmc_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); ++ ++ /* Reset SD Clock Enable */ ++ clk = bcm2835_mmc_readw(host, SDHCI_CLOCK_CONTROL); ++ clk &= ~SDHCI_CLOCK_CARD_EN; ++ bcm2835_mmc_writew(host, clk, SDHCI_CLOCK_CONTROL); ++ ++ /* Re-enable SD Clock */ ++ bcm2835_mmc_set_clock(host, host->clock); ++ bcm2835_mmc_writeb(host, ctrl, SDHCI_HOST_CONTROL); ++ ++ mmiowb(); ++ ++ spin_unlock_irqrestore(&host->lock, flags); ++} ++ ++ ++static struct mmc_host_ops bcm2835_ops = { ++ .request = bcm2835_mmc_request, ++ .set_ios = bcm2835_mmc_set_ios, ++ .enable_sdio_irq = bcm2835_mmc_enable_sdio_irq, ++}; ++ ++ ++static void bcm2835_mmc_tasklet_finish(unsigned long param) ++{ ++ struct bcm2835_host *host; ++ unsigned long flags; ++ struct mmc_request *mrq; ++ ++ host = (struct bcm2835_host *)param; ++ ++ spin_lock_irqsave(&host->lock, flags); ++ ++ /* ++ * If this tasklet gets rescheduled while running, it will ++ * be run again afterwards but without any active request. ++ */ ++ if (!host->mrq) { ++ spin_unlock_irqrestore(&host->lock, flags); ++ return; ++ } ++ ++ del_timer(&host->timer); ++ ++ mrq = host->mrq; ++ ++ /* ++ * The controller needs a reset of internal state machines ++ * upon error conditions. ++ */ ++ if (!(host->flags & SDHCI_DEVICE_DEAD) && ++ ((mrq->cmd && mrq->cmd->error) || ++ (mrq->data && (mrq->data->error || ++ (mrq->data->stop && mrq->data->stop->error))))) { ++ ++ spin_unlock_irqrestore(&host->lock, flags); ++ bcm2835_mmc_reset(host, SDHCI_RESET_CMD); ++ bcm2835_mmc_reset(host, SDHCI_RESET_DATA); ++ spin_lock_irqsave(&host->lock, flags); ++ } ++ ++ host->mrq = NULL; ++ host->cmd = NULL; ++ host->data = NULL; ++ ++ mmiowb(); ++ ++ spin_unlock_irqrestore(&host->lock, flags); ++ mmc_request_done(host->mmc, mrq); ++} ++ ++ ++ ++static int bcm2835_mmc_add_host(struct bcm2835_host *host) ++{ ++ struct mmc_host *mmc = host->mmc; ++ struct device *dev = mmc->parent; ++#ifndef FORCE_PIO ++ struct dma_slave_config cfg; ++#endif ++ int ret; ++ ++ bcm2835_mmc_reset(host, SDHCI_RESET_ALL); ++ ++ host->clk_mul = 0; ++ ++ mmc->f_max = host->max_clk; ++ mmc->f_max = host->max_clk; ++ mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; ++ ++ /* SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK */ ++ host->timeout_clk = mmc->f_max / 1000; ++#ifdef CONFIG_ARCH_BCM2835 ++ mmc->max_busy_timeout = (1 << 27) / host->timeout_clk; ++#endif ++ /* host controller capabilities */ ++ mmc->caps |= MMC_CAP_CMD23 | MMC_CAP_ERASE | MMC_CAP_NEEDS_POLL | ++ MMC_CAP_SDIO_IRQ | MMC_CAP_SD_HIGHSPEED | ++ MMC_CAP_MMC_HIGHSPEED | MMC_CAP_4_BIT_DATA; ++ ++ host->flags = SDHCI_AUTO_CMD23; ++ ++ dev_info(dev, "mmc_debug:%x mmc_debug2:%x\n", mmc_debug, mmc_debug2); ++#ifdef FORCE_PIO ++ dev_info(dev, "Forcing PIO mode\n"); ++ host->have_dma = false; ++#else ++ if (IS_ERR_OR_NULL(host->dma_chan_tx) || ++ IS_ERR_OR_NULL(host->dma_chan_rx)) { ++ dev_err(dev, "%s: Unable to initialise DMA channels. Falling back to PIO\n", ++ DRIVER_NAME); ++ host->have_dma = false; ++ } else { ++ dev_info(dev, "DMA channels allocated"); ++ host->have_dma = true; ++ ++ cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ cfg.slave_id = 11; /* DREQ channel */ ++ ++ cfg.direction = DMA_MEM_TO_DEV; ++ cfg.src_addr = 0; ++ cfg.dst_addr = host->phys_addr + SDHCI_BUFFER; ++ ret = dmaengine_slave_config(host->dma_chan_tx, &cfg); ++ ++ cfg.direction = DMA_DEV_TO_MEM; ++ cfg.src_addr = host->phys_addr + SDHCI_BUFFER; ++ cfg.dst_addr = 0; ++ ret = dmaengine_slave_config(host->dma_chan_rx, &cfg); ++ } ++#endif ++ mmc->max_segs = 128; ++ mmc->max_req_size = 524288; ++ mmc->max_seg_size = mmc->max_req_size; ++ mmc->max_blk_size = 512; ++ mmc->max_blk_count = 65535; ++ ++ /* report supported voltage ranges */ ++ mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; ++ ++ tasklet_init(&host->finish_tasklet, ++ bcm2835_mmc_tasklet_finish, (unsigned long)host); ++ ++ setup_timer(&host->timer, bcm2835_mmc_timeout_timer, (unsigned long)host); ++ init_waitqueue_head(&host->buf_ready_int); ++ ++ bcm2835_mmc_init(host, 0); ++#ifndef CONFIG_ARCH_BCM2835 ++ ret = devm_request_irq(dev, host->irq, bcm2835_mmc_irq, 0, ++ mmc_hostname(mmc), host); ++#else ++ ret = devm_request_threaded_irq(dev, host->irq, bcm2835_mmc_irq, ++ bcm2835_mmc_thread_irq, IRQF_SHARED, ++ mmc_hostname(mmc), host); ++#endif ++ if (ret) { ++ dev_err(dev, "Failed to request IRQ %d: %d\n", host->irq, ret); ++ goto untasklet; ++ } ++ ++ mmiowb(); ++ mmc_add_host(mmc); ++ ++ return 0; ++ ++untasklet: ++ tasklet_kill(&host->finish_tasklet); ++ ++ return ret; ++} ++ ++static int bcm2835_mmc_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct device_node *node = dev->of_node; ++ struct clk *clk; ++ struct resource *iomem; ++ struct bcm2835_host *host; ++ struct mmc_host *mmc; ++ int ret; ++ ++ mmc = mmc_alloc_host(sizeof(*host), dev); ++ if (!mmc) ++ return -ENOMEM; ++ ++ mmc->ops = &bcm2835_ops; ++ host = mmc_priv(mmc); ++ host->mmc = mmc; ++ host->timeout = msecs_to_jiffies(1000); ++ spin_lock_init(&host->lock); ++ ++ iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ host->ioaddr = devm_ioremap_resource(dev, iomem); ++ if (IS_ERR(host->ioaddr)) { ++ ret = PTR_ERR(host->ioaddr); ++ goto err; ++ } ++ ++ host->phys_addr = iomem->start + BCM2835_VCMMU_SHIFT; ++ ++#ifndef FORCE_PIO ++ if (node) { ++ host->dma_chan_tx = dma_request_slave_channel(dev, "tx"); ++ host->dma_chan_rx = dma_request_slave_channel(dev, "rx"); ++ } else { ++ dma_cap_mask_t mask; ++ ++ dma_cap_zero(mask); ++ /* we don't care about the channel, any would work */ ++ dma_cap_set(DMA_SLAVE, mask); ++ host->dma_chan_tx = dma_request_channel(mask, NULL, NULL); ++ host->dma_chan_rx = dma_request_channel(mask, NULL, NULL); ++ } ++#endif ++ clk = devm_clk_get(dev, NULL); ++ if (IS_ERR(clk)) { ++ dev_err(dev, "could not get clk\n"); ++ ret = PTR_ERR(clk); ++ goto err; ++ } ++ ++ host->max_clk = clk_get_rate(clk); ++ ++ host->irq = platform_get_irq(pdev, 0); ++ if (host->irq <= 0) { ++ dev_err(dev, "get IRQ failed\n"); ++ ret = -EINVAL; ++ goto err; ++ } ++ ++ if (node) { ++ mmc_of_parse(mmc); ++ ++ /* Read any custom properties */ ++ of_property_read_u32(node, ++ "brcm,overclock-50", ++ &host->overclock_50); ++ } else { ++ mmc->caps |= MMC_CAP_4_BIT_DATA; ++ } ++ ++ ret = bcm2835_mmc_add_host(host); ++ if (ret) ++ goto err; ++ ++ platform_set_drvdata(pdev, host); ++ ++ return 0; ++err: ++ mmc_free_host(mmc); ++ ++ return ret; ++} ++ ++static int bcm2835_mmc_remove(struct platform_device *pdev) ++{ ++ struct bcm2835_host *host = platform_get_drvdata(pdev); ++ unsigned long flags; ++ int dead; ++ u32 scratch; ++ ++ dead = 0; ++ scratch = bcm2835_mmc_readl(host, SDHCI_INT_STATUS); ++ if (scratch == (u32)-1) ++ dead = 1; ++ ++ ++ if (dead) { ++ spin_lock_irqsave(&host->lock, flags); ++ ++ host->flags |= SDHCI_DEVICE_DEAD; ++ ++ if (host->mrq) { ++ pr_err("%s: Controller removed during " ++ " transfer!\n", mmc_hostname(host->mmc)); ++ ++ host->mrq->cmd->error = -ENOMEDIUM; ++ tasklet_schedule(&host->finish_tasklet); ++ } ++ ++ spin_unlock_irqrestore(&host->lock, flags); ++ } ++ ++ mmc_remove_host(host->mmc); ++ ++ if (!dead) ++ bcm2835_mmc_reset(host, SDHCI_RESET_ALL); ++ ++ free_irq(host->irq, host); ++ ++ del_timer_sync(&host->timer); ++ ++ tasklet_kill(&host->finish_tasklet); ++ ++ mmc_free_host(host->mmc); ++ platform_set_drvdata(pdev, NULL); ++ ++ return 0; ++} ++ ++ ++static const struct of_device_id bcm2835_mmc_match[] = { ++ { .compatible = "brcm,bcm2835-mmc" }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, bcm2835_mmc_match); ++ ++ ++ ++static struct platform_driver bcm2835_mmc_driver = { ++ .probe = bcm2835_mmc_probe, ++ .remove = bcm2835_mmc_remove, ++ .driver = { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = bcm2835_mmc_match, ++ }, ++}; ++module_platform_driver(bcm2835_mmc_driver); ++ ++module_param(mmc_debug, uint, 0644); ++module_param(mmc_debug2, uint, 0644); ++MODULE_ALIAS("platform:mmc-bcm2835"); ++MODULE_DESCRIPTION("BCM2835 SDHCI driver"); ++MODULE_LICENSE("GPL v2"); ++MODULE_AUTHOR("Gellert Weisz"); +diff -Nur linux-4.1.13.orig/drivers/mmc/host/bcm2835-sdhost.c linux-rpi/drivers/mmc/host/bcm2835-sdhost.c +--- linux-4.1.13.orig/drivers/mmc/host/bcm2835-sdhost.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/mmc/host/bcm2835-sdhost.c 2015-11-29 09:42:38.087220413 +0100 +@@ -0,0 +1,1930 @@ ++/* ++ * BCM2835 SD host driver. ++ * ++ * Author: Phil Elwell ++ * Copyright 2015 ++ * ++ * Based on ++ * mmc-bcm2835.c by Gellert Weisz ++ * which is, in turn, based on ++ * sdhci-bcm2708.c by Broadcom ++ * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko ++ * sdhci.c and sdhci-pci.c by Pierre Ossman ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ ++ ++#define SAFE_READ_THRESHOLD 4 ++#define SAFE_WRITE_THRESHOLD 4 ++#define ALLOW_DMA 1 ++#define ALLOW_CMD23 0 ++#define ALLOW_FAST 1 ++#define USE_BLOCK_IRQ 1 ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define DRIVER_NAME "sdhost-bcm2835" ++ ++#define SDCMD 0x00 /* Command to SD card - 16 R/W */ ++#define SDARG 0x04 /* Argument to SD card - 32 R/W */ ++#define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */ ++#define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */ ++#define SDRSP0 0x10 /* SD card response (31:0) - 32 R */ ++#define SDRSP1 0x14 /* SD card response (63:32) - 32 R */ ++#define SDRSP2 0x18 /* SD card response (95:64) - 32 R */ ++#define SDRSP3 0x1c /* SD card response (127:96) - 32 R */ ++#define SDHSTS 0x20 /* SD host status - 11 R */ ++#define SDVDD 0x30 /* SD card power control - 1 R/W */ ++#define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */ ++#define SDHCFG 0x38 /* Host configuration - 2 R/W */ ++#define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */ ++#define SDDATA 0x40 /* Data to/from SD card - 32 R/W */ ++#define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */ ++ ++#define SDCMD_NEW_FLAG 0x8000 ++#define SDCMD_FAIL_FLAG 0x4000 ++#define SDCMD_BUSYWAIT 0x800 ++#define SDCMD_NO_RESPONSE 0x400 ++#define SDCMD_LONG_RESPONSE 0x200 ++#define SDCMD_WRITE_CMD 0x80 ++#define SDCMD_READ_CMD 0x40 ++#define SDCMD_CMD_MASK 0x3f ++ ++#define SDCDIV_MAX_CDIV 0x7ff ++ ++#define SDHSTS_BUSY_IRPT 0x400 ++#define SDHSTS_BLOCK_IRPT 0x200 ++#define SDHSTS_SDIO_IRPT 0x100 ++#define SDHSTS_REW_TIME_OUT 0x80 ++#define SDHSTS_CMD_TIME_OUT 0x40 ++#define SDHSTS_CRC16_ERROR 0x20 ++#define SDHSTS_CRC7_ERROR 0x10 ++#define SDHSTS_FIFO_ERROR 0x08 ++/* Reserved */ ++/* Reserved */ ++#define SDHSTS_DATA_FLAG 0x01 ++ ++#define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR|SDHSTS_CRC16_ERROR|SDHSTS_REW_TIME_OUT|SDHSTS_FIFO_ERROR) ++#define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT|SDHSTS_TRANSFER_ERROR_MASK) ++ ++#define SDHCFG_BUSY_IRPT_EN (1<<10) ++#define SDHCFG_BLOCK_IRPT_EN (1<<8) ++#define SDHCFG_SDIO_IRPT_EN (1<<5) ++#define SDHCFG_DATA_IRPT_EN (1<<4) ++#define SDHCFG_SLOW_CARD (1<<3) ++#define SDHCFG_WIDE_EXT_BUS (1<<2) ++#define SDHCFG_WIDE_INT_BUS (1<<1) ++#define SDHCFG_REL_CMD_LINE (1<<0) ++ ++#define SDEDM_FORCE_DATA_MODE (1<<19) ++#define SDEDM_CLOCK_PULSE (1<<20) ++#define SDEDM_BYPASS (1<<21) ++ ++#define SDEDM_WRITE_THRESHOLD_SHIFT 9 ++#define SDEDM_READ_THRESHOLD_SHIFT 14 ++#define SDEDM_THRESHOLD_MASK 0x1f ++ ++#define MHZ 1000000 ++ ++#ifndef BCM2708_PERI_BASE ++ #define BCM2708_PERI_BASE 0x20000000 ++#endif ++ ++/* FIXME: Needs IOMMU support */ ++#define BCM2835_VCMMU_SHIFT (0x7E000000 - BCM2708_PERI_BASE) ++ ++ ++struct bcm2835_host { ++ spinlock_t lock; ++ ++ void __iomem *ioaddr; ++ u32 phys_addr; ++ ++ struct mmc_host *mmc; ++ ++ u32 pio_timeout; /* In jiffies */ ++ ++ int clock; /* Current clock speed */ ++ ++ bool slow_card; /* Force 11-bit divisor */ ++ ++ unsigned int max_clk; /* Max possible freq */ ++ ++ struct tasklet_struct finish_tasklet; /* Tasklet structures */ ++ ++ struct timer_list timer; /* Timer for timeouts */ ++ ++ struct timer_list pio_timer; /* PIO error detection timer */ ++ ++ struct sg_mapping_iter sg_miter; /* SG state for PIO */ ++ unsigned int blocks; /* remaining PIO blocks */ ++ ++ int irq; /* Device IRQ */ ++ ++ ++ /* cached registers */ ++ u32 hcfg; ++ u32 cdiv; ++ ++ struct mmc_request *mrq; /* Current request */ ++ struct mmc_command *cmd; /* Current command */ ++ struct mmc_data *data; /* Current data request */ ++ unsigned int data_complete:1; /* Data finished before cmd */ ++ ++ unsigned int flush_fifo:1; /* Drain the fifo when finishing */ ++ ++ unsigned int use_busy:1; /* Wait for busy interrupt */ ++ ++ unsigned int debug:1; /* Enable debug output */ ++ ++ u32 thread_isr; ++ ++ /*DMA part*/ ++ struct dma_chan *dma_chan_rx; /* DMA channel for reads */ ++ struct dma_chan *dma_chan_tx; /* DMA channel for writes */ ++ ++ bool allow_dma; ++ bool have_dma; ++ bool use_dma; ++ /*end of DMA part*/ ++ ++ int max_delay; /* maximum length of time spent waiting */ ++ struct timeval stop_time; /* when the last stop was issued */ ++ u32 delay_after_stop; /* minimum time between stop and subsequent data transfer */ ++ u32 overclock_50; /* frequency to use when 50MHz is requested (in MHz) */ ++ u32 overclock; /* Current frequency if overclocked, else zero */ ++ u32 pio_limit; /* Maximum block count for PIO (0 = always DMA) */ ++}; ++ ++ ++static inline void bcm2835_sdhost_write(struct bcm2835_host *host, u32 val, int reg) ++{ ++ writel(val, host->ioaddr + reg); ++} ++ ++static inline u32 bcm2835_sdhost_read(struct bcm2835_host *host, int reg) ++{ ++ return readl(host->ioaddr + reg); ++} ++ ++static inline u32 bcm2835_sdhost_read_relaxed(struct bcm2835_host *host, int reg) ++{ ++ return readl_relaxed(host->ioaddr + reg); ++} ++ ++static void bcm2835_sdhost_dumpcmd(struct bcm2835_host *host, ++ struct mmc_command *cmd, ++ const char *label) ++{ ++ if (cmd) ++ pr_info("%s:%c%s op %d arg 0x%x flags 0x%x - resp %08x %08x %08x %08x, err %d\n", ++ mmc_hostname(host->mmc), ++ (cmd == host->cmd) ? '>' : ' ', ++ label, cmd->opcode, cmd->arg, cmd->flags, ++ cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3], ++ cmd->error); ++} ++ ++static void bcm2835_sdhost_dumpregs(struct bcm2835_host *host) ++{ ++ bcm2835_sdhost_dumpcmd(host, host->mrq->sbc, "sbc"); ++ bcm2835_sdhost_dumpcmd(host, host->mrq->cmd, "cmd"); ++ if (host->mrq->data) ++ pr_err("%s: data blocks %x blksz %x - err %d\n", ++ mmc_hostname(host->mmc), ++ host->mrq->data->blocks, ++ host->mrq->data->blksz, ++ host->mrq->data->error); ++ bcm2835_sdhost_dumpcmd(host, host->mrq->stop, "stop"); ++ ++ pr_info("%s: =========== REGISTER DUMP ===========\n", ++ mmc_hostname(host->mmc)); ++ ++ pr_info("%s: SDCMD 0x%08x\n", ++ mmc_hostname(host->mmc), ++ bcm2835_sdhost_read(host, SDCMD)); ++ pr_info("%s: SDARG 0x%08x\n", ++ mmc_hostname(host->mmc), ++ bcm2835_sdhost_read(host, SDARG)); ++ pr_info("%s: SDTOUT 0x%08x\n", ++ mmc_hostname(host->mmc), ++ bcm2835_sdhost_read(host, SDTOUT)); ++ pr_info("%s: SDCDIV 0x%08x\n", ++ mmc_hostname(host->mmc), ++ bcm2835_sdhost_read(host, SDCDIV)); ++ pr_info("%s: SDRSP0 0x%08x\n", ++ mmc_hostname(host->mmc), ++ bcm2835_sdhost_read(host, SDRSP0)); ++ pr_info("%s: SDRSP1 0x%08x\n", ++ mmc_hostname(host->mmc), ++ bcm2835_sdhost_read(host, SDRSP1)); ++ pr_info("%s: SDRSP2 0x%08x\n", ++ mmc_hostname(host->mmc), ++ bcm2835_sdhost_read(host, SDRSP2)); ++ pr_info("%s: SDRSP3 0x%08x\n", ++ mmc_hostname(host->mmc), ++ bcm2835_sdhost_read(host, SDRSP3)); ++ pr_info("%s: SDHSTS 0x%08x\n", ++ mmc_hostname(host->mmc), ++ bcm2835_sdhost_read(host, SDHSTS)); ++ pr_info("%s: SDVDD 0x%08x\n", ++ mmc_hostname(host->mmc), ++ bcm2835_sdhost_read(host, SDVDD)); ++ pr_info("%s: SDEDM 0x%08x\n", ++ mmc_hostname(host->mmc), ++ bcm2835_sdhost_read(host, SDEDM)); ++ pr_info("%s: SDHCFG 0x%08x\n", ++ mmc_hostname(host->mmc), ++ bcm2835_sdhost_read(host, SDHCFG)); ++ pr_info("%s: SDHBCT 0x%08x\n", ++ mmc_hostname(host->mmc), ++ bcm2835_sdhost_read(host, SDHBCT)); ++ pr_info("%s: SDHBLC 0x%08x\n", ++ mmc_hostname(host->mmc), ++ bcm2835_sdhost_read(host, SDHBLC)); ++ ++ pr_info("%s: ===========================================\n", ++ mmc_hostname(host->mmc)); ++} ++ ++ ++static void bcm2835_sdhost_set_power(struct bcm2835_host *host, bool on) ++{ ++ bcm2835_sdhost_write(host, on ? 1 : 0, SDVDD); ++} ++ ++ ++static void bcm2835_sdhost_reset_internal(struct bcm2835_host *host) ++{ ++ u32 temp; ++ ++ bcm2835_sdhost_set_power(host, false); ++ ++ bcm2835_sdhost_write(host, 0, SDCMD); ++ bcm2835_sdhost_write(host, 0, SDARG); ++ bcm2835_sdhost_write(host, 0xf00000, SDTOUT); ++ bcm2835_sdhost_write(host, 0, SDCDIV); ++ bcm2835_sdhost_write(host, 0x7f8, SDHSTS); /* Write 1s to clear */ ++ bcm2835_sdhost_write(host, 0, SDHCFG); ++ bcm2835_sdhost_write(host, 0, SDHBCT); ++ bcm2835_sdhost_write(host, 0, SDHBLC); ++ ++ /* Limit fifo usage due to silicon bug */ ++ temp = bcm2835_sdhost_read(host, SDEDM); ++ temp &= ~((SDEDM_THRESHOLD_MASK<clock = 0; ++ bcm2835_sdhost_write(host, host->hcfg, SDHCFG); ++ bcm2835_sdhost_write(host, host->cdiv, SDCDIV); ++ mmiowb(); ++} ++ ++ ++static void bcm2835_sdhost_reset(struct mmc_host *mmc) ++{ ++ struct bcm2835_host *host = mmc_priv(mmc); ++ unsigned long flags; ++ if (host->debug) ++ pr_info("%s: reset\n", mmc_hostname(mmc)); ++ spin_lock_irqsave(&host->lock, flags); ++ ++ bcm2835_sdhost_reset_internal(host); ++ ++ spin_unlock_irqrestore(&host->lock, flags); ++} ++ ++static void bcm2835_sdhost_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); ++ ++static void bcm2835_sdhost_init(struct bcm2835_host *host, int soft) ++{ ++ pr_debug("bcm2835_sdhost_init(%d)\n", soft); ++ ++ /* Set interrupt enables */ ++ host->hcfg = SDHCFG_BUSY_IRPT_EN; ++ ++ bcm2835_sdhost_reset_internal(host); ++ ++ if (soft) { ++ /* force clock reconfiguration */ ++ host->clock = 0; ++ bcm2835_sdhost_set_ios(host->mmc, &host->mmc->ios); ++ } ++} ++ ++static bool bcm2835_sdhost_is_write_complete(struct bcm2835_host *host) ++{ ++ bool write_complete = ((bcm2835_sdhost_read(host, SDEDM) & 0xf) == 1); ++ ++ if (!write_complete) { ++ /* Request an IRQ for the last block */ ++ host->hcfg |= SDHCFG_BLOCK_IRPT_EN; ++ bcm2835_sdhost_write(host, host->hcfg, SDHCFG); ++ if ((bcm2835_sdhost_read(host, SDEDM) & 0xf) == 1) { ++ /* The write has now completed. Disable the interrupt ++ and clear the status flag */ ++ host->hcfg &= ~SDHCFG_BLOCK_IRPT_EN; ++ bcm2835_sdhost_write(host, host->hcfg, SDHCFG); ++ bcm2835_sdhost_write(host, SDHSTS_BLOCK_IRPT, SDHSTS); ++ write_complete = true; ++ } ++ } ++ ++ return write_complete; ++} ++ ++static void bcm2835_sdhost_wait_write_complete(struct bcm2835_host *host) ++{ ++ int timediff; ++#ifdef DEBUG ++ static struct timeval start_time; ++ static int max_stall_time = 0; ++ static int total_stall_time = 0; ++ struct timeval before, after; ++ ++ do_gettimeofday(&before); ++ if (max_stall_time == 0) ++ start_time = before; ++#endif ++ ++ timediff = 0; ++ ++ while (1) { ++ u32 edm = bcm2835_sdhost_read(host, SDEDM); ++ if ((edm & 0xf) == 1) ++ break; ++ timediff++; ++ if (timediff > 5000000) { ++#ifdef DEBUG ++ do_gettimeofday(&after); ++ timediff = (after.tv_sec - before.tv_sec)*1000000 + ++ (after.tv_usec - before.tv_usec); ++ ++ pr_err(" wait_write_complete - still waiting after %dus\n", ++ timediff); ++#else ++ pr_err(" wait_write_complete - still waiting after %d retries\n", ++ timediff); ++#endif ++ bcm2835_sdhost_dumpregs(host); ++ host->data->error = -ETIMEDOUT; ++ return; ++ } ++ } ++ ++#ifdef DEBUG ++ do_gettimeofday(&after); ++ timediff = (after.tv_sec - before.tv_sec)*1000000 + (after.tv_usec - before.tv_usec); ++ ++ total_stall_time += timediff; ++ if (timediff > max_stall_time) ++ max_stall_time = timediff; ++ ++ if ((after.tv_sec - start_time.tv_sec) > 10) { ++ pr_debug(" wait_write_complete - max wait %dus, total %dus\n", ++ max_stall_time, total_stall_time); ++ start_time = after; ++ max_stall_time = 0; ++ total_stall_time = 0; ++ } ++#endif ++} ++ ++static void bcm2835_sdhost_finish_data(struct bcm2835_host *host); ++ ++static void bcm2835_sdhost_dma_complete(void *param) ++{ ++ struct bcm2835_host *host = param; ++ struct dma_chan *dma_chan; ++ unsigned long flags; ++ u32 dir_data; ++ ++ spin_lock_irqsave(&host->lock, flags); ++ ++ if (host->data) { ++ bool write_complete; ++ if (USE_BLOCK_IRQ) ++ write_complete = bcm2835_sdhost_is_write_complete(host); ++ else { ++ bcm2835_sdhost_wait_write_complete(host); ++ write_complete = true; ++ } ++ pr_debug("dma_complete() - write_complete=%d\n", ++ write_complete); ++ ++ if (write_complete || (host->data->flags & MMC_DATA_READ)) ++ { ++ if (write_complete) { ++ dma_chan = host->dma_chan_tx; ++ dir_data = DMA_TO_DEVICE; ++ } else { ++ dma_chan = host->dma_chan_rx; ++ dir_data = DMA_FROM_DEVICE; ++ } ++ ++ dma_unmap_sg(dma_chan->device->dev, ++ host->data->sg, host->data->sg_len, ++ dir_data); ++ ++ bcm2835_sdhost_finish_data(host); ++ } ++ } ++ ++ spin_unlock_irqrestore(&host->lock, flags); ++} ++ ++static bool data_transfer_wait(struct bcm2835_host *host) ++{ ++ unsigned long timeout = 1000000; ++ while (timeout) ++ { ++ u32 sdhsts = bcm2835_sdhost_read(host, SDHSTS); ++ if (sdhsts & SDHSTS_DATA_FLAG) { ++ bcm2835_sdhost_write(host, SDHSTS_DATA_FLAG, SDHSTS); ++ break; ++ } ++ timeout--; ++ } ++ if (timeout == 0) { ++ pr_err("%s: Data %s timeout\n", ++ mmc_hostname(host->mmc), ++ (host->data->flags & MMC_DATA_READ) ? "read" : "write"); ++ bcm2835_sdhost_dumpregs(host); ++ host->data->error = -ETIMEDOUT; ++ return false; ++ } ++ return true; ++} ++ ++static void bcm2835_sdhost_read_block_pio(struct bcm2835_host *host) ++{ ++ unsigned long flags; ++ size_t blksize, len; ++ u32 *buf; ++ ++ blksize = host->data->blksz; ++ ++ local_irq_save(flags); ++ ++ while (blksize) { ++ if (!sg_miter_next(&host->sg_miter)) ++ BUG(); ++ ++ len = min(host->sg_miter.length, blksize); ++ BUG_ON(len % 4); ++ ++ blksize -= len; ++ host->sg_miter.consumed = len; ++ ++ buf = (u32 *)host->sg_miter.addr; ++ ++ while (len) { ++ if (!data_transfer_wait(host)) ++ break; ++ ++ *(buf++) = bcm2835_sdhost_read(host, SDDATA); ++ len -= 4; ++ } ++ ++ if (host->data->error) ++ break; ++ } ++ ++ sg_miter_stop(&host->sg_miter); ++ ++ local_irq_restore(flags); ++} ++ ++static void bcm2835_sdhost_write_block_pio(struct bcm2835_host *host) ++{ ++ unsigned long flags; ++ size_t blksize, len; ++ u32 *buf; ++ ++ blksize = host->data->blksz; ++ ++ local_irq_save(flags); ++ ++ while (blksize) { ++ if (!sg_miter_next(&host->sg_miter)) ++ BUG(); ++ ++ len = min(host->sg_miter.length, blksize); ++ BUG_ON(len % 4); ++ ++ blksize -= len; ++ host->sg_miter.consumed = len; ++ ++ buf = host->sg_miter.addr; ++ ++ while (len) { ++ if (!data_transfer_wait(host)) ++ break; ++ ++ bcm2835_sdhost_write(host, *(buf++), SDDATA); ++ len -= 4; ++ } ++ ++ if (host->data->error) ++ break; ++ } ++ ++ sg_miter_stop(&host->sg_miter); ++ ++ local_irq_restore(flags); ++} ++ ++ ++static void bcm2835_sdhost_transfer_pio(struct bcm2835_host *host) ++{ ++ u32 sdhsts; ++ bool is_read; ++ BUG_ON(!host->data); ++ ++ is_read = (host->data->flags & MMC_DATA_READ) != 0; ++ if (is_read) ++ bcm2835_sdhost_read_block_pio(host); ++ else ++ bcm2835_sdhost_write_block_pio(host); ++ ++ sdhsts = bcm2835_sdhost_read(host, SDHSTS); ++ if (sdhsts & (SDHSTS_CRC16_ERROR | ++ SDHSTS_CRC7_ERROR | ++ SDHSTS_FIFO_ERROR)) { ++ pr_err("%s: %s transfer error - HSTS %x\n", ++ mmc_hostname(host->mmc), ++ is_read ? "read" : "write", ++ sdhsts); ++ host->data->error = -EILSEQ; ++ } else if ((sdhsts & (SDHSTS_CMD_TIME_OUT | ++ SDHSTS_REW_TIME_OUT))) { ++ pr_err("%s: %s timeout error - HSTS %x\n", ++ mmc_hostname(host->mmc), ++ is_read ? "read" : "write", ++ sdhsts); ++ host->data->error = -ETIMEDOUT; ++ } else if (!is_read && !host->data->error) { ++ /* Start a timer in case a transfer error occurs because ++ there is no error interrupt */ ++ mod_timer(&host->pio_timer, jiffies + host->pio_timeout); ++ } ++} ++ ++ ++static void bcm2835_sdhost_transfer_dma(struct bcm2835_host *host) ++{ ++ u32 len, dir_data, dir_slave; ++ struct dma_async_tx_descriptor *desc = NULL; ++ struct dma_chan *dma_chan; ++ ++ pr_debug("bcm2835_sdhost_transfer_dma()\n"); ++ ++ WARN_ON(!host->data); ++ ++ if (!host->data) ++ return; ++ ++ if (host->data->flags & MMC_DATA_READ) { ++ dma_chan = host->dma_chan_rx; ++ dir_data = DMA_FROM_DEVICE; ++ dir_slave = DMA_DEV_TO_MEM; ++ } else { ++ dma_chan = host->dma_chan_tx; ++ dir_data = DMA_TO_DEVICE; ++ dir_slave = DMA_MEM_TO_DEV; ++ } ++ ++ BUG_ON(!dma_chan->device); ++ BUG_ON(!dma_chan->device->dev); ++ BUG_ON(!host->data->sg); ++ ++ len = dma_map_sg(dma_chan->device->dev, host->data->sg, ++ host->data->sg_len, dir_data); ++ if (len > 0) { ++ desc = dmaengine_prep_slave_sg(dma_chan, host->data->sg, ++ len, dir_slave, ++ DMA_PREP_INTERRUPT | DMA_CTRL_ACK); ++ } else { ++ dev_err(mmc_dev(host->mmc), "dma_map_sg returned zero length\n"); ++ } ++ if (desc) { ++ desc->callback = bcm2835_sdhost_dma_complete; ++ desc->callback_param = host; ++ dmaengine_submit(desc); ++ dma_async_issue_pending(dma_chan); ++ } ++ ++} ++ ++ ++static void bcm2835_sdhost_set_transfer_irqs(struct bcm2835_host *host) ++{ ++ u32 all_irqs = SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN | ++ SDHCFG_BUSY_IRPT_EN; ++ if (host->use_dma) ++ host->hcfg = (host->hcfg & ~all_irqs) | ++ SDHCFG_BUSY_IRPT_EN; ++ else ++ host->hcfg = (host->hcfg & ~all_irqs) | ++ SDHCFG_DATA_IRPT_EN | ++ SDHCFG_BUSY_IRPT_EN; ++ ++ bcm2835_sdhost_write(host, host->hcfg, SDHCFG); ++} ++ ++ ++static void bcm2835_sdhost_prepare_data(struct bcm2835_host *host, struct mmc_command *cmd) ++{ ++ struct mmc_data *data = cmd->data; ++ ++ WARN_ON(host->data); ++ ++ if (!data) ++ return; ++ ++ /* Sanity checks */ ++ BUG_ON(data->blksz * data->blocks > 524288); ++ BUG_ON(data->blksz > host->mmc->max_blk_size); ++ BUG_ON(data->blocks > 65535); ++ ++ host->data = data; ++ host->data_complete = 0; ++ host->flush_fifo = 0; ++ host->data->bytes_xfered = 0; ++ ++ host->use_dma = host->have_dma && (data->blocks > host->pio_limit); ++ if (!host->use_dma) { ++ int flags; ++ ++ flags = SG_MITER_ATOMIC; ++ if (data->flags & MMC_DATA_READ) ++ flags |= SG_MITER_TO_SG; ++ else ++ flags |= SG_MITER_FROM_SG; ++ sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); ++ host->blocks = data->blocks; ++ } ++ ++ bcm2835_sdhost_set_transfer_irqs(host); ++ ++ bcm2835_sdhost_write(host, data->blksz, SDHBCT); ++ bcm2835_sdhost_write(host, host->use_dma ? data->blocks : 0, SDHBLC); ++ ++ BUG_ON(!host->data); ++} ++ ++ ++void bcm2835_sdhost_send_command(struct bcm2835_host *host, struct mmc_command *cmd) ++{ ++ u32 sdcmd, sdhsts; ++ unsigned long timeout; ++ int delay; ++ ++ WARN_ON(host->cmd); ++ ++ if (cmd->data) ++ pr_debug("%s: send_command %d 0x%x " ++ "(flags 0x%x) - %s %d*%d\n", ++ mmc_hostname(host->mmc), ++ cmd->opcode, cmd->arg, cmd->flags, ++ (cmd->data->flags & MMC_DATA_READ) ? ++ "read" : "write", cmd->data->blocks, ++ cmd->data->blksz); ++ else ++ pr_debug("%s: send_command %d 0x%x (flags 0x%x)\n", ++ mmc_hostname(host->mmc), ++ cmd->opcode, cmd->arg, cmd->flags); ++ ++ /* Wait max 100 ms */ ++ timeout = 10000; ++ ++ while (bcm2835_sdhost_read(host, SDCMD) & SDCMD_NEW_FLAG) { ++ if (timeout == 0) { ++ pr_err("%s: previous command never completed.\n", ++ mmc_hostname(host->mmc)); ++ bcm2835_sdhost_dumpregs(host); ++ cmd->error = -EIO; ++ tasklet_schedule(&host->finish_tasklet); ++ return; ++ } ++ timeout--; ++ udelay(10); ++ } ++ ++ delay = (10000 - timeout)/100; ++ if (delay > host->max_delay) { ++ host->max_delay = delay; ++ pr_warning("%s: controller hung for %d ms\n", ++ mmc_hostname(host->mmc), ++ host->max_delay); ++ } ++ ++ timeout = jiffies; ++ if (!cmd->data && cmd->busy_timeout > 9000) ++ timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; ++ else ++ timeout += 10 * HZ; ++ mod_timer(&host->timer, timeout); ++ ++ host->cmd = cmd; ++ ++ /* Clear any error flags */ ++ sdhsts = bcm2835_sdhost_read(host, SDHSTS); ++ if (sdhsts & SDHSTS_ERROR_MASK) ++ bcm2835_sdhost_write(host, sdhsts, SDHSTS); ++ ++ bcm2835_sdhost_prepare_data(host, cmd); ++ ++ bcm2835_sdhost_write(host, cmd->arg, SDARG); ++ ++ if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { ++ pr_err("%s: unsupported response type!\n", ++ mmc_hostname(host->mmc)); ++ cmd->error = -EINVAL; ++ tasklet_schedule(&host->finish_tasklet); ++ return; ++ } ++ ++ sdcmd = cmd->opcode & SDCMD_CMD_MASK; ++ ++ if (!(cmd->flags & MMC_RSP_PRESENT)) ++ sdcmd |= SDCMD_NO_RESPONSE; ++ else { ++ if (cmd->flags & MMC_RSP_136) ++ sdcmd |= SDCMD_LONG_RESPONSE; ++ if (cmd->flags & MMC_RSP_BUSY) { ++ sdcmd |= SDCMD_BUSYWAIT; ++ host->use_busy = 1; ++ } ++ } ++ ++ if (cmd->data) { ++ if (host->delay_after_stop) { ++ struct timeval now; ++ int time_since_stop; ++ do_gettimeofday(&now); ++ time_since_stop = (now.tv_sec - host->stop_time.tv_sec); ++ if (time_since_stop < 2) { ++ /* Possibly less than one second */ ++ time_since_stop = time_since_stop * 1000000 + ++ (now.tv_usec - host->stop_time.tv_usec); ++ if (time_since_stop < host->delay_after_stop) ++ udelay(host->delay_after_stop - ++ time_since_stop); ++ } ++ } ++ ++ if (cmd->data->flags & MMC_DATA_WRITE) ++ sdcmd |= SDCMD_WRITE_CMD; ++ if (cmd->data->flags & MMC_DATA_READ) ++ sdcmd |= SDCMD_READ_CMD; ++ } ++ ++ bcm2835_sdhost_write(host, sdcmd | SDCMD_NEW_FLAG, SDCMD); ++} ++ ++ ++static void bcm2835_sdhost_finish_command(struct bcm2835_host *host); ++static void bcm2835_sdhost_transfer_complete(struct bcm2835_host *host); ++ ++static void bcm2835_sdhost_finish_data(struct bcm2835_host *host) ++{ ++ struct mmc_data *data; ++ ++ data = host->data; ++ BUG_ON(!data); ++ ++ pr_debug("finish_data(error %d, stop %d, sbc %d)\n", ++ data->error, data->stop ? 1 : 0, ++ host->mrq->sbc ? 1 : 0); ++ ++ host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN); ++ bcm2835_sdhost_write(host, host->hcfg, SDHCFG); ++ ++ if (data->error) { ++ data->bytes_xfered = 0; ++ } else ++ data->bytes_xfered = data->blksz * data->blocks; ++ ++ host->data_complete = 1; ++ ++ if (host->cmd) { ++ /* ++ * Data managed to finish before the ++ * command completed. Make sure we do ++ * things in the proper order. ++ */ ++ pr_debug("Finished early - HSTS %x\n", ++ bcm2835_sdhost_read(host, SDHSTS)); ++ } ++ else ++ bcm2835_sdhost_transfer_complete(host); ++} ++ ++ ++static void bcm2835_sdhost_transfer_complete(struct bcm2835_host *host) ++{ ++ struct mmc_data *data; ++ ++ BUG_ON(host->cmd); ++ BUG_ON(!host->data); ++ BUG_ON(!host->data_complete); ++ ++ data = host->data; ++ host->data = NULL; ++ ++ pr_debug("transfer_complete(error %d, stop %d)\n", ++ data->error, data->stop ? 1 : 0); ++ ++ /* ++ * Need to send CMD12 if - ++ * a) open-ended multiblock transfer (no CMD23) ++ * b) error in multiblock transfer ++ */ ++ if (data->stop && ++ (data->error || ++ !host->mrq->sbc)) { ++ host->flush_fifo = 1; ++ bcm2835_sdhost_send_command(host, data->stop); ++ if (host->delay_after_stop) ++ do_gettimeofday(&host->stop_time); ++ if (!host->use_busy) ++ bcm2835_sdhost_finish_command(host); ++ } else { ++ tasklet_schedule(&host->finish_tasklet); ++ } ++} ++ ++static void bcm2835_sdhost_finish_command(struct bcm2835_host *host) ++{ ++ u32 sdcmd; ++ unsigned long timeout; ++#ifdef DEBUG ++ struct timeval before, after; ++ int timediff = 0; ++#endif ++ ++ pr_debug("finish_command(%x)\n", bcm2835_sdhost_read(host, SDCMD)); ++ ++ BUG_ON(!host->cmd || !host->mrq); ++ ++#ifdef DEBUG ++ do_gettimeofday(&before); ++#endif ++ /* Wait max 100 ms */ ++ timeout = 10000; ++ for (sdcmd = bcm2835_sdhost_read(host, SDCMD); ++ (sdcmd & SDCMD_NEW_FLAG) && timeout; ++ timeout--) { ++ if (host->flush_fifo) { ++ while (bcm2835_sdhost_read(host, SDHSTS) & ++ SDHSTS_DATA_FLAG) ++ (void)bcm2835_sdhost_read(host, SDDATA); ++ } ++ udelay(10); ++ sdcmd = bcm2835_sdhost_read(host, SDCMD); ++ } ++#ifdef DEBUG ++ do_gettimeofday(&after); ++ timediff = (after.tv_sec - before.tv_sec)*1000000 + ++ (after.tv_usec - before.tv_usec); ++ ++ pr_debug(" finish_command - waited %dus\n", timediff); ++#endif ++ ++ if (timeout == 0) { ++ pr_err("%s: command never completed.\n", ++ mmc_hostname(host->mmc)); ++ bcm2835_sdhost_dumpregs(host); ++ host->cmd->error = -EIO; ++ tasklet_schedule(&host->finish_tasklet); ++ return; ++ } ++ ++ if (host->flush_fifo) { ++ for (timeout = 100; ++ (bcm2835_sdhost_read(host, SDHSTS) & SDHSTS_DATA_FLAG) && timeout; ++ timeout--) { ++ (void)bcm2835_sdhost_read(host, SDDATA); ++ } ++ host->flush_fifo = 0; ++ if (timeout == 0) { ++ pr_err("%s: FIFO never drained.\n", ++ mmc_hostname(host->mmc)); ++ bcm2835_sdhost_dumpregs(host); ++ host->cmd->error = -EIO; ++ tasklet_schedule(&host->finish_tasklet); ++ return; ++ } ++ } ++ ++ /* Check for errors */ ++ if (sdcmd & SDCMD_FAIL_FLAG) ++ { ++ u32 sdhsts = bcm2835_sdhost_read(host, SDHSTS); ++ ++ if (host->debug) ++ pr_info("%s: error detected - CMD %x, HSTS %03x, EDM %x\n", ++ mmc_hostname(host->mmc), sdcmd, sdhsts, ++ bcm2835_sdhost_read(host, SDEDM)); ++ ++ if ((sdhsts & SDHSTS_CRC7_ERROR) && ++ (host->cmd->opcode == 1)) { ++ if (host->debug) ++ pr_info("%s: ignoring CRC7 error for CMD1\n", ++ mmc_hostname(host->mmc)); ++ } else { ++ if (sdhsts & SDHSTS_CMD_TIME_OUT) { ++ switch (host->cmd->opcode) { ++ case 5: case 52: case 53: ++ /* Don't warn about SDIO commands */ ++ break; ++ default: ++ pr_err("%s: command timeout\n", ++ mmc_hostname(host->mmc)); ++ break; ++ } ++ host->cmd->error = -ETIMEDOUT; ++ } else { ++ pr_err("%s: unexpected command error\n", ++ mmc_hostname(host->mmc)); ++ bcm2835_sdhost_dumpregs(host); ++ host->cmd->error = -EIO; ++ } ++ tasklet_schedule(&host->finish_tasklet); ++ return; ++ } ++ } ++ ++ if (host->cmd->flags & MMC_RSP_PRESENT) { ++ if (host->cmd->flags & MMC_RSP_136) { ++ int i; ++ for (i = 0; i < 4; i++) ++ host->cmd->resp[3 - i] = bcm2835_sdhost_read(host, SDRSP0 + i*4); ++ pr_debug("%s: finish_command %08x %08x %08x %08x\n", ++ mmc_hostname(host->mmc), ++ host->cmd->resp[0], host->cmd->resp[1], host->cmd->resp[2], host->cmd->resp[3]); ++ } else { ++ host->cmd->resp[0] = bcm2835_sdhost_read(host, SDRSP0); ++ pr_debug("%s: finish_command %08x\n", ++ mmc_hostname(host->mmc), ++ host->cmd->resp[0]); ++ } ++ } ++ ++ host->cmd->error = 0; ++ ++ if (host->cmd == host->mrq->sbc) { ++ /* Finished CMD23, now send actual command. */ ++ host->cmd = NULL; ++ bcm2835_sdhost_send_command(host, host->mrq->cmd); ++ ++ if (host->cmd->data && host->use_dma) ++ /* DMA transfer starts now, PIO starts after irq */ ++ bcm2835_sdhost_transfer_dma(host); ++ ++ if (!host->use_busy) ++ bcm2835_sdhost_finish_command(host); ++ } else if (host->cmd == host->mrq->stop) ++ /* Finished CMD12 */ ++ tasklet_schedule(&host->finish_tasklet); ++ else { ++ /* Processed actual command. */ ++ host->cmd = NULL; ++ if (!host->data) ++ tasklet_schedule(&host->finish_tasklet); ++ else if (host->data_complete) ++ bcm2835_sdhost_transfer_complete(host); ++ } ++} ++ ++static void bcm2835_sdhost_timeout(unsigned long data) ++{ ++ struct bcm2835_host *host; ++ unsigned long flags; ++ ++ host = (struct bcm2835_host *)data; ++ ++ spin_lock_irqsave(&host->lock, flags); ++ ++ if (host->mrq) { ++ pr_err("%s: timeout waiting for hardware interrupt.\n", ++ mmc_hostname(host->mmc)); ++ bcm2835_sdhost_dumpregs(host); ++ ++ if (host->data) { ++ host->data->error = -ETIMEDOUT; ++ bcm2835_sdhost_finish_data(host); ++ } else { ++ if (host->cmd) ++ host->cmd->error = -ETIMEDOUT; ++ else ++ host->mrq->cmd->error = -ETIMEDOUT; ++ ++ pr_debug("timeout_timer tasklet_schedule\n"); ++ tasklet_schedule(&host->finish_tasklet); ++ } ++ } ++ ++ mmiowb(); ++ spin_unlock_irqrestore(&host->lock, flags); ++} ++ ++static void bcm2835_sdhost_pio_timeout(unsigned long data) ++{ ++ struct bcm2835_host *host; ++ unsigned long flags; ++ ++ host = (struct bcm2835_host *)data; ++ ++ spin_lock_irqsave(&host->lock, flags); ++ ++ if (host->data) { ++ u32 sdhsts = bcm2835_sdhost_read(host, SDHSTS); ++ ++ if (sdhsts & SDHSTS_REW_TIME_OUT) { ++ pr_err("%s: transfer timeout\n", ++ mmc_hostname(host->mmc)); ++ if (host->debug) ++ bcm2835_sdhost_dumpregs(host); ++ } else { ++ pr_err("%s: unexpected transfer timeout\n", ++ mmc_hostname(host->mmc)); ++ bcm2835_sdhost_dumpregs(host); ++ } ++ ++ bcm2835_sdhost_write(host, SDHSTS_TRANSFER_ERROR_MASK, ++ SDHSTS); ++ ++ host->data->error = -ETIMEDOUT; ++ ++ bcm2835_sdhost_finish_data(host); ++ } ++ ++ mmiowb(); ++ spin_unlock_irqrestore(&host->lock, flags); ++} ++ ++static void bcm2835_sdhost_enable_sdio_irq_nolock(struct bcm2835_host *host, int enable) ++{ ++ if (enable) ++ host->hcfg |= SDHCFG_SDIO_IRPT_EN; ++ else ++ host->hcfg &= ~SDHCFG_SDIO_IRPT_EN; ++ bcm2835_sdhost_write(host, host->hcfg, SDHCFG); ++ mmiowb(); ++} ++ ++static void bcm2835_sdhost_enable_sdio_irq(struct mmc_host *mmc, int enable) ++{ ++ struct bcm2835_host *host = mmc_priv(mmc); ++ unsigned long flags; ++ ++ pr_debug("%s: enable_sdio_irq(%d)\n", mmc_hostname(mmc), enable); ++ spin_lock_irqsave(&host->lock, flags); ++ bcm2835_sdhost_enable_sdio_irq_nolock(host, enable); ++ spin_unlock_irqrestore(&host->lock, flags); ++} ++ ++static u32 bcm2835_sdhost_busy_irq(struct bcm2835_host *host, u32 intmask) ++{ ++ const u32 handled = (SDHSTS_REW_TIME_OUT | SDHSTS_CMD_TIME_OUT | ++ SDHSTS_CRC16_ERROR | SDHSTS_CRC7_ERROR | ++ SDHSTS_FIFO_ERROR); ++ ++ if (!host->cmd) { ++ pr_err("%s: got command busy interrupt 0x%08x even " ++ "though no command operation was in progress.\n", ++ mmc_hostname(host->mmc), (unsigned)intmask); ++ bcm2835_sdhost_dumpregs(host); ++ return 0; ++ } ++ ++ if (!host->use_busy) { ++ pr_err("%s: got command busy interrupt 0x%08x even " ++ "though not expecting one.\n", ++ mmc_hostname(host->mmc), (unsigned)intmask); ++ bcm2835_sdhost_dumpregs(host); ++ return 0; ++ } ++ host->use_busy = 0; ++ ++ if (intmask & SDHSTS_ERROR_MASK) ++ { ++ pr_err("sdhost_busy_irq: intmask %x, data %p\n", intmask, host->mrq->data); ++ if (intmask & SDHSTS_CRC7_ERROR) ++ host->cmd->error = -EILSEQ; ++ else if (intmask & (SDHSTS_CRC16_ERROR | ++ SDHSTS_FIFO_ERROR)) { ++ if (host->mrq->data) ++ host->mrq->data->error = -EILSEQ; ++ else ++ host->cmd->error = -EILSEQ; ++ } else if (intmask & SDHSTS_REW_TIME_OUT) { ++ if (host->mrq->data) ++ host->mrq->data->error = -ETIMEDOUT; ++ else ++ host->cmd->error = -ETIMEDOUT; ++ } else if (intmask & SDHSTS_CMD_TIME_OUT) ++ host->cmd->error = -ETIMEDOUT; ++ ++ bcm2835_sdhost_dumpregs(host); ++ tasklet_schedule(&host->finish_tasklet); ++ } ++ else ++ bcm2835_sdhost_finish_command(host); ++ ++ return handled; ++} ++ ++static u32 bcm2835_sdhost_data_irq(struct bcm2835_host *host, u32 intmask) ++{ ++ const u32 handled = (SDHSTS_REW_TIME_OUT | ++ SDHSTS_CRC16_ERROR | ++ SDHSTS_FIFO_ERROR); ++ ++ /* There are no dedicated data/space available interrupt ++ status bits, so it is necessary to use the single shared ++ data/space available FIFO status bits. It is therefore not ++ an error to get here when there is no data transfer in ++ progress. */ ++ if (!host->data) ++ return 0; ++ ++ if (intmask & (SDHSTS_CRC16_ERROR | ++ SDHSTS_FIFO_ERROR | ++ SDHSTS_REW_TIME_OUT)) { ++ if (intmask & (SDHSTS_CRC16_ERROR | ++ SDHSTS_FIFO_ERROR)) ++ host->data->error = -EILSEQ; ++ else ++ host->data->error = -ETIMEDOUT; ++ ++ bcm2835_sdhost_dumpregs(host); ++ tasklet_schedule(&host->finish_tasklet); ++ return handled; ++ } ++ ++ /* Use the block interrupt for writes after the first block */ ++ if (host->data->flags & MMC_DATA_WRITE) { ++ host->hcfg &= ~(SDHCFG_DATA_IRPT_EN); ++ host->hcfg |= SDHCFG_BLOCK_IRPT_EN; ++ bcm2835_sdhost_write(host, host->hcfg, SDHCFG); ++ if (host->data->error) ++ bcm2835_sdhost_finish_data(host); ++ else ++ bcm2835_sdhost_transfer_pio(host); ++ } else { ++ if (!host->data->error) { ++ bcm2835_sdhost_transfer_pio(host); ++ host->blocks--; ++ } ++ if ((host->blocks == 0) || host->data->error) ++ bcm2835_sdhost_finish_data(host); ++ } ++ ++ return handled; ++} ++ ++static u32 bcm2835_sdhost_block_irq(struct bcm2835_host *host, u32 intmask) ++{ ++ struct dma_chan *dma_chan; ++ u32 dir_data; ++ const u32 handled = (SDHSTS_REW_TIME_OUT | ++ SDHSTS_CRC16_ERROR | ++ SDHSTS_FIFO_ERROR); ++ ++ if (!host->data) { ++ pr_err("%s: got block interrupt 0x%08x even " ++ "though no data operation was in progress.\n", ++ mmc_hostname(host->mmc), (unsigned)intmask); ++ bcm2835_sdhost_dumpregs(host); ++ return handled; ++ } ++ ++ if (intmask & (SDHSTS_CRC16_ERROR | ++ SDHSTS_FIFO_ERROR | ++ SDHSTS_REW_TIME_OUT)) { ++ if (intmask & (SDHSTS_CRC16_ERROR | ++ SDHSTS_FIFO_ERROR)) ++ host->data->error = -EILSEQ; ++ else ++ host->data->error = -ETIMEDOUT; ++ ++ if (host->debug) ++ bcm2835_sdhost_dumpregs(host); ++ tasklet_schedule(&host->finish_tasklet); ++ return handled; ++ } ++ ++ if (!host->use_dma) { ++ BUG_ON(!host->blocks); ++ host->blocks--; ++ if ((host->blocks == 0) || host->data->error) { ++ /* Cancel the timer */ ++ del_timer(&host->pio_timer); ++ ++ bcm2835_sdhost_finish_data(host); ++ } else { ++ bcm2835_sdhost_transfer_pio(host); ++ ++ /* Reset the timer */ ++ mod_timer(&host->pio_timer, ++ jiffies + host->pio_timeout); ++ } ++ } else if (host->data->flags & MMC_DATA_WRITE) { ++ dma_chan = host->dma_chan_tx; ++ dir_data = DMA_TO_DEVICE; ++ dma_unmap_sg(dma_chan->device->dev, ++ host->data->sg, host->data->sg_len, ++ dir_data); ++ ++ bcm2835_sdhost_finish_data(host); ++ } ++ ++ return handled; ++} ++ ++ ++static irqreturn_t bcm2835_sdhost_irq(int irq, void *dev_id) ++{ ++ irqreturn_t result = IRQ_NONE; ++ struct bcm2835_host *host = dev_id; ++ u32 unexpected = 0, early = 0; ++ int loops = 0; ++#ifndef CONFIG_ARCH_BCM2835 ++ int cardint = 0; ++#endif ++ spin_lock(&host->lock); ++ ++ for (loops = 0; loops < 1; loops++) { ++ u32 intmask, handled; ++ ++ intmask = bcm2835_sdhost_read(host, SDHSTS); ++ handled = intmask & (SDHSTS_BUSY_IRPT | ++ SDHSTS_BLOCK_IRPT | ++ SDHSTS_SDIO_IRPT | ++ SDHSTS_DATA_FLAG); ++ if ((handled == SDHSTS_DATA_FLAG) && ++ (loops == 0) && !host->data) { ++ pr_err("%s: sdhost_irq data interrupt 0x%08x even " ++ "though no data operation was in progress.\n", ++ mmc_hostname(host->mmc), ++ (unsigned)intmask); ++ ++ bcm2835_sdhost_dumpregs(host); ++ } ++ ++ if (!handled) ++ break; ++ ++ if (loops) ++ early |= handled; ++ ++ result = IRQ_HANDLED; ++ ++ /* Clear all interrupts and notifications */ ++ bcm2835_sdhost_write(host, intmask, SDHSTS); ++ ++ if (intmask & SDHSTS_BUSY_IRPT) ++ handled |= bcm2835_sdhost_busy_irq(host, intmask); ++ ++ /* There is no true data interrupt status bit, so it is ++ necessary to qualify the data flag with the interrupt ++ enable bit */ ++ if ((intmask & SDHSTS_DATA_FLAG) && ++ (host->hcfg & SDHCFG_DATA_IRPT_EN)) ++ handled |= bcm2835_sdhost_data_irq(host, intmask); ++ ++ if (intmask & SDHSTS_BLOCK_IRPT) ++ handled |= bcm2835_sdhost_block_irq(host, intmask); ++ ++ if (intmask & SDHSTS_SDIO_IRPT) { ++#ifndef CONFIG_ARCH_BCM2835 ++ cardint = 1; ++#else ++ bcm2835_sdhost_enable_sdio_irq_nolock(host, false); ++ host->thread_isr |= SDHSTS_SDIO_IRPT; ++ result = IRQ_WAKE_THREAD; ++#endif ++ } ++ ++ unexpected |= (intmask & ~handled); ++ } ++ ++ mmiowb(); ++ ++ spin_unlock(&host->lock); ++ ++ if (early) ++ pr_debug("%s: early %x (loops %d)\n", ++ mmc_hostname(host->mmc), early, loops); ++ ++ if (unexpected) { ++ pr_err("%s: unexpected interrupt 0x%08x.\n", ++ mmc_hostname(host->mmc), unexpected); ++ bcm2835_sdhost_dumpregs(host); ++ } ++ ++#ifndef CONFIG_ARCH_BCM2835 ++ if (cardint) ++ mmc_signal_sdio_irq(host->mmc); ++#endif ++ ++ return result; ++} ++ ++#ifdef CONFIG_ARCH_BCM2835 ++static irqreturn_t bcm2835_sdhost_thread_irq(int irq, void *dev_id) ++{ ++ struct bcm2835_host *host = dev_id; ++ unsigned long flags; ++ u32 isr; ++ ++ spin_lock_irqsave(&host->lock, flags); ++ isr = host->thread_isr; ++ host->thread_isr = 0; ++ spin_unlock_irqrestore(&host->lock, flags); ++ ++ if (isr & SDHSTS_SDIO_IRPT) { ++ sdio_run_irqs(host->mmc); ++ ++/* Is this necessary? Why re-enable an interrupt which is enabled? ++ spin_lock_irqsave(&host->lock, flags); ++ if (host->flags & SDHSTS_SDIO_IRPT_ENABLED) ++ bcm2835_sdhost_enable_sdio_irq_nolock(host, true); ++ spin_unlock_irqrestore(&host->lock, flags); ++*/ ++ } ++ ++ return isr ? IRQ_HANDLED : IRQ_NONE; ++} ++#endif ++ ++ ++ ++void bcm2835_sdhost_set_clock(struct bcm2835_host *host, unsigned int clock) ++{ ++ int div = 0; /* Initialized for compiler warning */ ++ unsigned int input_clock = clock; ++ ++ if (host->debug) ++ pr_info("%s: set_clock(%d)\n", mmc_hostname(host->mmc), clock); ++ ++ if ((host->overclock_50 > 50) && ++ (clock == 50*MHZ)) { ++ clock = host->overclock_50 * MHZ + (MHZ - 1); ++ } ++ ++ /* The SDCDIV register has 11 bits, and holds (div - 2). ++ But in data mode the max is 50MHz wihout a minimum, and only the ++ bottom 3 bits are used. Since the switch over is automatic (unless ++ we have marked the card as slow...), chosen values have to make ++ sense in both modes. ++ Ident mode must be 100-400KHz, so can range check the requested ++ clock. CMD15 must be used to return to data mode, so this can be ++ monitored. ++ ++ clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz ++ 4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz ++ ++ 623->400KHz/27.8MHz ++ reset value (507)->491159/50MHz ++ ++ BUT, the 3-bit clock divisor in data mode is too small if the ++ core clock is higher than 250MHz, so instead use the SLOW_CARD ++ configuration bit to force the use of the ident clock divisor ++ at all times. ++ */ ++ ++ host->mmc->actual_clock = 0; ++ ++ if (clock < 100000) { ++ /* Can't stop the clock, but make it as slow as possible ++ * to show willing ++ */ ++ host->cdiv = SDCDIV_MAX_CDIV; ++ bcm2835_sdhost_write(host, host->cdiv, SDCDIV); ++ return; ++ } ++ ++ div = host->max_clk / clock; ++ if (div < 2) ++ div = 2; ++ if ((host->max_clk / div) > clock) ++ div++; ++ div -= 2; ++ ++ if (div > SDCDIV_MAX_CDIV) ++ div = SDCDIV_MAX_CDIV; ++ ++ clock = host->max_clk / (div + 2); ++ host->mmc->actual_clock = clock; ++ ++ if (clock > input_clock) { ++ /* Save the closest value, to make it easier ++ to reduce in the event of error */ ++ host->overclock_50 = (clock/MHZ); ++ ++ if (clock != host->overclock) { ++ pr_warn("%s: overclocking to %dHz\n", ++ mmc_hostname(host->mmc), clock); ++ host->overclock = clock; ++ } ++ } ++ else if (host->overclock) ++ { ++ host->overclock = 0; ++ if (clock == 50 * MHZ) ++ pr_warn("%s: cancelling overclock\n", ++ mmc_hostname(host->mmc)); ++ } ++ ++ host->cdiv = div; ++ bcm2835_sdhost_write(host, host->cdiv, SDCDIV); ++ ++ /* Set the timeout to 500ms */ ++ bcm2835_sdhost_write(host, host->mmc->actual_clock/2, SDTOUT); ++ ++ if (host->debug) ++ pr_info("%s: clock=%d -> max_clk=%d, cdiv=%x (actual clock %d)\n", ++ mmc_hostname(host->mmc), input_clock, ++ host->max_clk, host->cdiv, host->mmc->actual_clock); ++} ++ ++static void bcm2835_sdhost_request(struct mmc_host *mmc, struct mmc_request *mrq) ++{ ++ struct bcm2835_host *host; ++ unsigned long flags; ++ ++ host = mmc_priv(mmc); ++ ++ if (host->debug) { ++ struct mmc_command *cmd = mrq->cmd; ++ BUG_ON(!cmd); ++ if (cmd->data) ++ pr_info("%s: cmd %d 0x%x (flags 0x%x) - %s %d*%d\n", ++ mmc_hostname(mmc), ++ cmd->opcode, cmd->arg, cmd->flags, ++ (cmd->data->flags & MMC_DATA_READ) ? ++ "read" : "write", cmd->data->blocks, ++ cmd->data->blksz); ++ else ++ pr_info("%s: cmd %d 0x%x (flags 0x%x)\n", ++ mmc_hostname(mmc), ++ cmd->opcode, cmd->arg, cmd->flags); ++ } ++ ++ /* Reset the error statuses in case this is a retry */ ++ if (mrq->cmd) ++ mrq->cmd->error = 0; ++ if (mrq->data) ++ mrq->data->error = 0; ++ if (mrq->stop) ++ mrq->stop->error = 0; ++ ++ if (mrq->data && !is_power_of_2(mrq->data->blksz)) { ++ pr_err("%s: unsupported block size (%d bytes)\n", ++ mmc_hostname(mmc), mrq->data->blksz); ++ mrq->cmd->error = -EINVAL; ++ mmc_request_done(mmc, mrq); ++ return; ++ } ++ ++ spin_lock_irqsave(&host->lock, flags); ++ ++ WARN_ON(host->mrq != NULL); ++ ++ host->mrq = mrq; ++ ++ if (mrq->sbc) ++ bcm2835_sdhost_send_command(host, mrq->sbc); ++ else ++ bcm2835_sdhost_send_command(host, mrq->cmd); ++ ++ mmiowb(); ++ spin_unlock_irqrestore(&host->lock, flags); ++ ++ if (!mrq->sbc && mrq->cmd->data && host->use_dma) ++ /* DMA transfer starts now, PIO starts after irq */ ++ bcm2835_sdhost_transfer_dma(host); ++ ++ if (!host->use_busy) ++ bcm2835_sdhost_finish_command(host); ++} ++ ++ ++static void bcm2835_sdhost_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) ++{ ++ ++ struct bcm2835_host *host = mmc_priv(mmc); ++ unsigned long flags; ++ ++ if (host->debug) ++ pr_info("%s: ios clock %d, pwr %d, bus_width %d, " ++ "timing %d, vdd %d, drv_type %d\n", ++ mmc_hostname(mmc), ++ ios->clock, ios->power_mode, ios->bus_width, ++ ios->timing, ios->signal_voltage, ios->drv_type); ++ ++ spin_lock_irqsave(&host->lock, flags); ++ ++ if (!ios->clock || ios->clock != host->clock) { ++ bcm2835_sdhost_set_clock(host, ios->clock); ++ host->clock = ios->clock; ++ } ++ ++ /* set bus width */ ++ host->hcfg &= ~SDHCFG_WIDE_EXT_BUS; ++ if (ios->bus_width == MMC_BUS_WIDTH_4) ++ host->hcfg |= SDHCFG_WIDE_EXT_BUS; ++ ++ host->hcfg |= SDHCFG_WIDE_INT_BUS; ++ ++ /* Disable clever clock switching, to cope with fast core clocks */ ++ host->hcfg |= SDHCFG_SLOW_CARD; ++ ++ bcm2835_sdhost_write(host, host->hcfg, SDHCFG); ++ ++ mmiowb(); ++ ++ spin_unlock_irqrestore(&host->lock, flags); ++} ++ ++static int bcm2835_sdhost_multi_io_quirk(struct mmc_card *card, ++ unsigned int direction, ++ u32 blk_pos, int blk_size) ++{ ++ /* There is a bug in the host controller hardware that makes ++ reading the final sector of the card as part of a multiple read ++ problematic. Detect that case and shorten the read accordingly. ++ */ ++ /* csd.capacity is in weird units - convert to sectors */ ++ u32 card_sectors = (card->csd.capacity << (card->csd.read_blkbits - 9)); ++ ++ if ((direction == MMC_DATA_READ) && ++ ((blk_pos + blk_size) == card_sectors)) ++ blk_size--; ++ ++ return blk_size; ++} ++ ++ ++static struct mmc_host_ops bcm2835_sdhost_ops = { ++ .request = bcm2835_sdhost_request, ++ .set_ios = bcm2835_sdhost_set_ios, ++ .enable_sdio_irq = bcm2835_sdhost_enable_sdio_irq, ++ .hw_reset = bcm2835_sdhost_reset, ++ .multi_io_quirk = bcm2835_sdhost_multi_io_quirk, ++}; ++ ++ ++static void bcm2835_sdhost_tasklet_finish(unsigned long param) ++{ ++ struct bcm2835_host *host; ++ unsigned long flags; ++ struct mmc_request *mrq; ++ ++ host = (struct bcm2835_host *)param; ++ ++ spin_lock_irqsave(&host->lock, flags); ++ ++ /* ++ * If this tasklet gets rescheduled while running, it will ++ * be run again afterwards but without any active request. ++ */ ++ if (!host->mrq) { ++ spin_unlock_irqrestore(&host->lock, flags); ++ return; ++ } ++ ++ del_timer(&host->timer); ++ ++ mrq = host->mrq; ++ ++ /* Drop the overclock after any data corruption, or after any ++ error overclocked */ ++ if (host->overclock) { ++ if ((mrq->cmd && mrq->cmd->error) || ++ (mrq->data && mrq->data->error) || ++ (mrq->stop && mrq->stop->error)) { ++ host->overclock_50--; ++ pr_warn("%s: reducing overclock due to errors\n", ++ mmc_hostname(host->mmc)); ++ bcm2835_sdhost_set_clock(host,50*MHZ); ++ mrq->cmd->error = -EILSEQ; ++ mrq->cmd->retries = 1; ++ } ++ } ++ ++ host->mrq = NULL; ++ host->cmd = NULL; ++ host->data = NULL; ++ ++ mmiowb(); ++ ++ spin_unlock_irqrestore(&host->lock, flags); ++ mmc_request_done(host->mmc, mrq); ++} ++ ++ ++ ++int bcm2835_sdhost_add_host(struct bcm2835_host *host) ++{ ++ struct mmc_host *mmc; ++ struct dma_slave_config cfg; ++ char pio_limit_string[20]; ++ int ret; ++ ++ mmc = host->mmc; ++ ++ bcm2835_sdhost_reset_internal(host); ++ ++ mmc->f_max = host->max_clk; ++ mmc->f_min = host->max_clk / SDCDIV_MAX_CDIV; ++ ++ mmc->max_busy_timeout = (~(unsigned int)0)/(mmc->f_max/1000); ++ ++ pr_debug("f_max %d, f_min %d, max_busy_timeout %d\n", ++ mmc->f_max, mmc->f_min, mmc->max_busy_timeout); ++ ++ /* host controller capabilities */ ++ mmc->caps |= /* MMC_CAP_SDIO_IRQ |*/ MMC_CAP_4_BIT_DATA | ++ MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | ++ MMC_CAP_NEEDS_POLL | MMC_CAP_HW_RESET | MMC_CAP_ERASE | ++ (ALLOW_CMD23 * MMC_CAP_CMD23); ++ ++ spin_lock_init(&host->lock); ++ ++ if (host->allow_dma) { ++ if (IS_ERR_OR_NULL(host->dma_chan_tx) || ++ IS_ERR_OR_NULL(host->dma_chan_rx)) { ++ pr_err("%s: unable to initialise DMA channels. " ++ "Falling back to PIO\n", ++ mmc_hostname(mmc)); ++ host->have_dma = false; ++ } else { ++ host->have_dma = true; ++ ++ cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ cfg.slave_id = 13; /* DREQ channel */ ++ ++ cfg.direction = DMA_MEM_TO_DEV; ++ cfg.src_addr = 0; ++ cfg.dst_addr = host->phys_addr + SDDATA; ++ ret = dmaengine_slave_config(host->dma_chan_tx, &cfg); ++ ++ cfg.direction = DMA_DEV_TO_MEM; ++ cfg.src_addr = host->phys_addr + SDDATA; ++ cfg.dst_addr = 0; ++ ret = dmaengine_slave_config(host->dma_chan_rx, &cfg); ++ } ++ } else { ++ host->have_dma = false; ++ } ++ ++ mmc->max_segs = 128; ++ mmc->max_req_size = 524288; ++ mmc->max_seg_size = mmc->max_req_size; ++ mmc->max_blk_size = 512; ++ mmc->max_blk_count = 65535; ++ ++ /* report supported voltage ranges */ ++ mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; ++ ++ tasklet_init(&host->finish_tasklet, ++ bcm2835_sdhost_tasklet_finish, (unsigned long)host); ++ ++ setup_timer(&host->timer, bcm2835_sdhost_timeout, ++ (unsigned long)host); ++ ++ setup_timer(&host->pio_timer, bcm2835_sdhost_pio_timeout, ++ (unsigned long)host); ++ ++ bcm2835_sdhost_init(host, 0); ++#ifndef CONFIG_ARCH_BCM2835 ++ ret = request_irq(host->irq, bcm2835_sdhost_irq, 0 /*IRQF_SHARED*/, ++ mmc_hostname(mmc), host); ++#else ++ ret = request_threaded_irq(host->irq, bcm2835_sdhost_irq, ++ bcm2835_sdhost_thread_irq, ++ IRQF_SHARED, mmc_hostname(mmc), host); ++#endif ++ if (ret) { ++ pr_err("%s: failed to request IRQ %d: %d\n", ++ mmc_hostname(mmc), host->irq, ret); ++ goto untasklet; ++ } ++ ++ mmiowb(); ++ mmc_add_host(mmc); ++ ++ pio_limit_string[0] = '\0'; ++ if (host->have_dma && (host->pio_limit > 0)) ++ sprintf(pio_limit_string, " (>%d)", host->pio_limit); ++ pr_info("%s: %s loaded - DMA %s%s\n", ++ mmc_hostname(mmc), DRIVER_NAME, ++ host->have_dma ? "enabled" : "disabled", ++ pio_limit_string); ++ ++ return 0; ++ ++untasklet: ++ tasklet_kill(&host->finish_tasklet); ++ ++ return ret; ++} ++ ++static int bcm2835_sdhost_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct device_node *node = dev->of_node; ++ struct clk *clk; ++ struct resource *iomem; ++ struct bcm2835_host *host; ++ struct mmc_host *mmc; ++ int ret; ++ ++ pr_debug("bcm2835_sdhost_probe\n"); ++ mmc = mmc_alloc_host(sizeof(*host), dev); ++ if (!mmc) ++ return -ENOMEM; ++ ++ mmc->ops = &bcm2835_sdhost_ops; ++ host = mmc_priv(mmc); ++ host->mmc = mmc; ++ host->pio_timeout = msecs_to_jiffies(500); ++ host->max_delay = 1; /* Warn if over 1ms */ ++ spin_lock_init(&host->lock); ++ ++ iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ host->ioaddr = devm_ioremap_resource(dev, iomem); ++ if (IS_ERR(host->ioaddr)) { ++ ret = PTR_ERR(host->ioaddr); ++ goto err; ++ } ++ ++ host->phys_addr = iomem->start + BCM2835_VCMMU_SHIFT; ++ pr_debug(" - ioaddr %lx, iomem->start %lx, phys_addr %lx\n", ++ (unsigned long)host->ioaddr, ++ (unsigned long)iomem->start, ++ (unsigned long)host->phys_addr); ++ ++ host->allow_dma = ALLOW_DMA; ++ ++ if (node) { ++ /* Read any custom properties */ ++ of_property_read_u32(node, ++ "brcm,delay-after-stop", ++ &host->delay_after_stop); ++ of_property_read_u32(node, ++ "brcm,overclock-50", ++ &host->overclock_50); ++ of_property_read_u32(node, ++ "brcm,pio-limit", ++ &host->pio_limit); ++ host->allow_dma = ALLOW_DMA && ++ !of_property_read_bool(node, "brcm,force-pio"); ++ host->debug = of_property_read_bool(node, "brcm,debug"); ++ } ++ ++ if (host->allow_dma) { ++ if (node) { ++ host->dma_chan_tx = ++ dma_request_slave_channel(dev, "tx"); ++ host->dma_chan_rx = ++ dma_request_slave_channel(dev, "rx"); ++ } else { ++ dma_cap_mask_t mask; ++ ++ dma_cap_zero(mask); ++ /* we don't care about the channel, any would work */ ++ dma_cap_set(DMA_SLAVE, mask); ++ host->dma_chan_tx = ++ dma_request_channel(mask, NULL, NULL); ++ host->dma_chan_rx = ++ dma_request_channel(mask, NULL, NULL); ++ } ++ } ++ ++ clk = devm_clk_get(dev, NULL); ++ if (IS_ERR(clk)) { ++ dev_err(dev, "could not get clk\n"); ++ ret = PTR_ERR(clk); ++ goto err; ++ } ++ ++ host->max_clk = clk_get_rate(clk); ++ ++ host->irq = platform_get_irq(pdev, 0); ++ if (host->irq <= 0) { ++ dev_err(dev, "get IRQ failed\n"); ++ ret = -EINVAL; ++ goto err; ++ } ++ ++ pr_debug(" - max_clk %lx, irq %d\n", ++ (unsigned long)host->max_clk, ++ (int)host->irq); ++ ++ if (node) ++ mmc_of_parse(mmc); ++ else ++ mmc->caps |= MMC_CAP_4_BIT_DATA; ++ ++ ret = bcm2835_sdhost_add_host(host); ++ if (ret) ++ goto err; ++ ++ platform_set_drvdata(pdev, host); ++ ++ pr_debug("bcm2835_sdhost_probe -> OK\n"); ++ ++ return 0; ++ ++err: ++ pr_debug("bcm2835_sdhost_probe -> err %d\n", ret); ++ mmc_free_host(mmc); ++ ++ return ret; ++} ++ ++static int bcm2835_sdhost_remove(struct platform_device *pdev) ++{ ++ struct bcm2835_host *host = platform_get_drvdata(pdev); ++ ++ pr_debug("bcm2835_sdhost_remove\n"); ++ ++ mmc_remove_host(host->mmc); ++ ++ bcm2835_sdhost_set_power(host, false); ++ ++ free_irq(host->irq, host); ++ ++ del_timer_sync(&host->timer); ++ ++ tasklet_kill(&host->finish_tasklet); ++ ++ mmc_free_host(host->mmc); ++ platform_set_drvdata(pdev, NULL); ++ ++ pr_debug("bcm2835_sdhost_remove - OK\n"); ++ return 0; ++} ++ ++ ++static const struct of_device_id bcm2835_sdhost_match[] = { ++ { .compatible = "brcm,bcm2835-sdhost" }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, bcm2835_sdhost_match); ++ ++ ++ ++static struct platform_driver bcm2835_sdhost_driver = { ++ .probe = bcm2835_sdhost_probe, ++ .remove = bcm2835_sdhost_remove, ++ .driver = { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = bcm2835_sdhost_match, ++ }, ++}; ++module_platform_driver(bcm2835_sdhost_driver); ++ ++MODULE_ALIAS("platform:sdhost-bcm2835"); ++MODULE_DESCRIPTION("BCM2835 SDHost driver"); ++MODULE_LICENSE("GPL v2"); ++MODULE_AUTHOR("Phil Elwell"); +diff -Nur linux-4.1.13.orig/drivers/mmc/host/Kconfig linux-rpi/drivers/mmc/host/Kconfig +--- linux-4.1.13.orig/drivers/mmc/host/Kconfig 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/mmc/host/Kconfig 2015-11-29 09:42:38.087220413 +0100 +@@ -4,6 +4,45 @@ + + comment "MMC/SD/SDIO Host Controller Drivers" + ++config MMC_BCM2835 ++ tristate "MMC support on BCM2835" ++ depends on MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835 ++ help ++ This selects the MMC Interface on BCM2835. ++ ++ If you have a controller with this interface, say Y or M here. ++ ++ If unsure, say N. ++ ++config MMC_BCM2835_DMA ++ bool "DMA support on BCM2835 Arasan controller" ++ depends on MMC_BCM2835 ++ help ++ Enable DMA support on the Arasan SDHCI controller in Broadcom 2708 ++ based chips. ++ ++ If unsure, say N. ++ ++config MMC_BCM2835_PIO_DMA_BARRIER ++ int "Block count limit for PIO transfers" ++ depends on MMC_BCM2835 && MMC_BCM2835_DMA ++ range 0 256 ++ default 2 ++ help ++ The inclusive limit in bytes under which PIO will be used instead of DMA ++ ++ If unsure, say 2 here. ++ ++config MMC_BCM2835_SDHOST ++ tristate "Support for the SDHost controller on BCM2708/9" ++ depends on MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835 ++ help ++ This selects the SDHost controller on BCM2835/6. ++ ++ If you have a controller with this interface, say Y or M here. ++ ++ If unsure, say N. ++ + config MMC_ARMMMCI + tristate "ARM AMBA Multimedia Card Interface support" + depends on ARM_AMBA +diff -Nur linux-4.1.13.orig/drivers/mmc/host/Makefile linux-rpi/drivers/mmc/host/Makefile +--- linux-4.1.13.orig/drivers/mmc/host/Makefile 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/mmc/host/Makefile 2015-11-29 09:42:38.087220413 +0100 +@@ -18,6 +18,8 @@ + obj-$(CONFIG_MMC_SDHCI_SIRF) += sdhci-sirf.o + obj-$(CONFIG_MMC_SDHCI_F_SDH30) += sdhci_f_sdh30.o + obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o ++obj-$(CONFIG_MMC_BCM2835_SDHOST) += bcm2835-sdhost.o ++obj-$(CONFIG_MMC_BCM2835) += bcm2835-mmc.o + obj-$(CONFIG_MMC_WBSD) += wbsd.o + obj-$(CONFIG_MMC_AU1X) += au1xmmc.o + obj-$(CONFIG_MMC_OMAP) += omap.o +diff -Nur linux-4.1.13.orig/drivers/mmc/host/omap_hsmmc.c linux-rpi/drivers/mmc/host/omap_hsmmc.c +--- linux-4.1.13.orig/drivers/mmc/host/omap_hsmmc.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/mmc/host/omap_hsmmc.c 2015-11-29 09:42:38.095219881 +0100 +@@ -1749,7 +1749,9 @@ + } + + static int omap_hsmmc_multi_io_quirk(struct mmc_card *card, +- unsigned int direction, int blk_size) ++ unsigned int direction, ++ u32 blk_pos, ++ int blk_size) + { + /* This controller can't do multiblock reads due to hw bugs */ + if (direction == MMC_DATA_READ) +diff -Nur linux-4.1.13.orig/drivers/mmc/host/sh_mobile_sdhi.c linux-rpi/drivers/mmc/host/sh_mobile_sdhi.c +--- linux-4.1.13.orig/drivers/mmc/host/sh_mobile_sdhi.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/mmc/host/sh_mobile_sdhi.c 2015-11-29 09:42:38.099219616 +0100 +@@ -170,7 +170,9 @@ + } + + static int sh_mobile_sdhi_multi_io_quirk(struct mmc_card *card, +- unsigned int direction, int blk_size) ++ unsigned int direction, ++ u32 blk_pos, ++ int blk_size) + { + /* + * In Renesas controllers, when performing a +diff -Nur linux-4.1.13.orig/drivers/mmc/host/tmio_mmc_pio.c linux-rpi/drivers/mmc/host/tmio_mmc_pio.c +--- linux-4.1.13.orig/drivers/mmc/host/tmio_mmc_pio.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/mmc/host/tmio_mmc_pio.c 2015-11-29 09:42:38.103219350 +0100 +@@ -1001,7 +1001,9 @@ + } + + static int tmio_multi_io_quirk(struct mmc_card *card, +- unsigned int direction, int blk_size) ++ unsigned int direction, ++ u32 blk_pos, ++ int blk_size) + { + struct tmio_mmc_host *host = mmc_priv(card->host); + +diff -Nur linux-4.1.13.orig/drivers/mtd/nand/bcm2835_smi_nand.c linux-rpi/drivers/mtd/nand/bcm2835_smi_nand.c +--- linux-4.1.13.orig/drivers/mtd/nand/bcm2835_smi_nand.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/mtd/nand/bcm2835_smi_nand.c 2015-11-29 09:42:38.147216426 +0100 +@@ -0,0 +1,268 @@ ++/** ++ * NAND flash driver for Broadcom Secondary Memory Interface ++ * ++ * Written by Luke Wren ++ * Copyright (c) 2015, Raspberry Pi (Trading) Ltd. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define DEVICE_NAME "bcm2835-smi-nand" ++#define DRIVER_NAME "smi-nand-bcm2835" ++ ++struct bcm2835_smi_nand_host { ++ struct bcm2835_smi_instance *smi_inst; ++ struct nand_chip nand_chip; ++ struct mtd_info mtd; ++ struct device *dev; ++}; ++ ++/**************************************************************************** ++* ++* NAND functionality implementation ++* ++****************************************************************************/ ++ ++#define SMI_NAND_CLE_PIN 0x01 ++#define SMI_NAND_ALE_PIN 0x02 ++ ++static inline void bcm2835_smi_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, ++ unsigned int ctrl) ++{ ++ uint32_t cmd32 = cmd; ++ uint32_t addr = ~(SMI_NAND_CLE_PIN | SMI_NAND_ALE_PIN); ++ struct bcm2835_smi_nand_host *host = dev_get_drvdata(mtd->dev.parent); ++ struct bcm2835_smi_instance *inst = host->smi_inst; ++ ++ if (ctrl & NAND_CLE) ++ addr |= SMI_NAND_CLE_PIN; ++ if (ctrl & NAND_ALE) ++ addr |= SMI_NAND_ALE_PIN; ++ /* Lower ALL the CS pins! */ ++ if (ctrl & NAND_NCE) ++ addr &= (SMI_NAND_CLE_PIN | SMI_NAND_ALE_PIN); ++ ++ bcm2835_smi_set_address(inst, addr); ++ ++ if (cmd != NAND_CMD_NONE) ++ bcm2835_smi_write_buf(inst, &cmd32, 1); ++} ++ ++static inline uint8_t bcm2835_smi_nand_read_byte(struct mtd_info *mtd) ++{ ++ uint8_t byte; ++ struct bcm2835_smi_nand_host *host = dev_get_drvdata(mtd->dev.parent); ++ struct bcm2835_smi_instance *inst = host->smi_inst; ++ ++ bcm2835_smi_read_buf(inst, &byte, 1); ++ return byte; ++} ++ ++static inline void bcm2835_smi_nand_write_byte(struct mtd_info *mtd, ++ uint8_t byte) ++{ ++ struct bcm2835_smi_nand_host *host = dev_get_drvdata(mtd->dev.parent); ++ struct bcm2835_smi_instance *inst = host->smi_inst; ++ ++ bcm2835_smi_write_buf(inst, &byte, 1); ++} ++ ++static inline void bcm2835_smi_nand_write_buf(struct mtd_info *mtd, ++ const uint8_t *buf, int len) ++{ ++ struct bcm2835_smi_nand_host *host = dev_get_drvdata(mtd->dev.parent); ++ struct bcm2835_smi_instance *inst = host->smi_inst; ++ ++ bcm2835_smi_write_buf(inst, buf, len); ++} ++ ++static inline void bcm2835_smi_nand_read_buf(struct mtd_info *mtd, ++ uint8_t *buf, int len) ++{ ++ struct bcm2835_smi_nand_host *host = dev_get_drvdata(mtd->dev.parent); ++ struct bcm2835_smi_instance *inst = host->smi_inst; ++ ++ bcm2835_smi_read_buf(inst, buf, len); ++} ++ ++/**************************************************************************** ++* ++* Probe and remove functions ++* ++***************************************************************************/ ++ ++static int bcm2835_smi_nand_probe(struct platform_device *pdev) ++{ ++ struct bcm2835_smi_nand_host *host; ++ struct nand_chip *this; ++ struct mtd_info *mtd; ++ struct device *dev = &pdev->dev; ++ struct device_node *node = dev->of_node, *smi_node; ++ struct mtd_part_parser_data ppdata; ++ struct smi_settings *smi_settings; ++ struct bcm2835_smi_instance *smi_inst; ++ int ret = -ENXIO; ++ ++ if (!node) { ++ dev_err(dev, "No device tree node supplied!"); ++ return -EINVAL; ++ } ++ ++ smi_node = of_parse_phandle(node, "smi_handle", 0); ++ ++ /* Request use of SMI peripheral: */ ++ smi_inst = bcm2835_smi_get(smi_node); ++ ++ if (!smi_inst) { ++ dev_err(dev, "Could not register with SMI."); ++ return -EPROBE_DEFER; ++ } ++ ++ /* Set SMI timing and bus width */ ++ ++ smi_settings = bcm2835_smi_get_settings_from_regs(smi_inst); ++ ++ smi_settings->data_width = SMI_WIDTH_8BIT; ++ smi_settings->read_setup_time = 2; ++ smi_settings->read_hold_time = 1; ++ smi_settings->read_pace_time = 1; ++ smi_settings->read_strobe_time = 3; ++ ++ smi_settings->write_setup_time = 2; ++ smi_settings->write_hold_time = 1; ++ smi_settings->write_pace_time = 1; ++ smi_settings->write_strobe_time = 3; ++ ++ bcm2835_smi_set_regs_from_settings(smi_inst); ++ ++ host = devm_kzalloc(dev, sizeof(struct bcm2835_smi_nand_host), ++ GFP_KERNEL); ++ if (!host) ++ return -ENOMEM; ++ ++ host->dev = dev; ++ host->smi_inst = smi_inst; ++ ++ platform_set_drvdata(pdev, host); ++ ++ /* Link the structures together */ ++ ++ this = &host->nand_chip; ++ mtd = &host->mtd; ++ mtd->priv = this; ++ mtd->owner = THIS_MODULE; ++ mtd->dev.parent = dev; ++ mtd->name = DRIVER_NAME; ++ ppdata.of_node = node; ++ ++ /* 20 us command delay time... */ ++ this->chip_delay = 20; ++ ++ this->priv = host; ++ this->cmd_ctrl = bcm2835_smi_nand_cmd_ctrl; ++ this->read_byte = bcm2835_smi_nand_read_byte; ++ this->write_byte = bcm2835_smi_nand_write_byte; ++ this->write_buf = bcm2835_smi_nand_write_buf; ++ this->read_buf = bcm2835_smi_nand_read_buf; ++ ++ this->ecc.mode = NAND_ECC_SOFT; ++ ++ /* Should never be accessed directly: */ ++ ++ this->IO_ADDR_R = (void *)0xdeadbeef; ++ this->IO_ADDR_W = (void *)0xdeadbeef; ++ ++ /* First scan to find the device and get the page size */ ++ ++ if (nand_scan_ident(mtd, 1, NULL)) ++ return -ENXIO; ++ ++ /* Second phase scan */ ++ ++ if (nand_scan_tail(mtd)) ++ return -ENXIO; ++ ++ ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0); ++ if (!ret) ++ return 0; ++ ++ nand_release(mtd); ++ return -EINVAL; ++} ++ ++static int bcm2835_smi_nand_remove(struct platform_device *pdev) ++{ ++ struct bcm2835_smi_nand_host *host = platform_get_drvdata(pdev); ++ ++ nand_release(&host->mtd); ++ ++ return 0; ++} ++ ++/**************************************************************************** ++* ++* Register the driver with device tree ++* ++***************************************************************************/ ++ ++static const struct of_device_id bcm2835_smi_nand_of_match[] = { ++ {.compatible = "brcm,bcm2835-smi-nand",}, ++ { /* sentinel */ } ++}; ++ ++MODULE_DEVICE_TABLE(of, bcm2835_smi_nand_of_match); ++ ++static struct platform_driver bcm2835_smi_nand_driver = { ++ .probe = bcm2835_smi_nand_probe, ++ .remove = bcm2835_smi_nand_remove, ++ .driver = { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = bcm2835_smi_nand_of_match, ++ }, ++}; ++ ++module_platform_driver(bcm2835_smi_nand_driver); ++ ++MODULE_ALIAS("platform:smi-nand-bcm2835"); ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION ++ ("Driver for NAND chips using Broadcom Secondary Memory Interface"); ++MODULE_AUTHOR("Luke Wren "); +diff -Nur linux-4.1.13.orig/drivers/mtd/nand/Kconfig linux-rpi/drivers/mtd/nand/Kconfig +--- linux-4.1.13.orig/drivers/mtd/nand/Kconfig 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/mtd/nand/Kconfig 2015-11-29 09:42:38.143216692 +0100 +@@ -41,6 +41,13 @@ + tristate + default n + ++config MTD_NAND_BCM2835_SMI ++ tristate "Use Broadcom's Secondary Memory Interface as a NAND controller (BCM283x)" ++ depends on (MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835) && BCM2835_SMI && MTD_NAND ++ default m ++ help ++ Uses the BCM2835's SMI peripheral as a NAND controller. ++ + config MTD_NAND_DENALI + tristate "Support Denali NAND controller" + depends on HAS_DMA +diff -Nur linux-4.1.13.orig/drivers/mtd/nand/Makefile linux-rpi/drivers/mtd/nand/Makefile +--- linux-4.1.13.orig/drivers/mtd/nand/Makefile 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/mtd/nand/Makefile 2015-11-29 09:42:38.143216692 +0100 +@@ -14,6 +14,7 @@ + obj-$(CONFIG_MTD_NAND_DENALI_PCI) += denali_pci.o + obj-$(CONFIG_MTD_NAND_DENALI_DT) += denali_dt.o + obj-$(CONFIG_MTD_NAND_AU1550) += au1550nd.o ++obj-$(CONFIG_MTD_NAND_BCM2835_SMI) += bcm2835_smi_nand.o + obj-$(CONFIG_MTD_NAND_BF5XX) += bf5xx_nand.o + obj-$(CONFIG_MTD_NAND_S3C2410) += s3c2410.o + obj-$(CONFIG_MTD_NAND_DAVINCI) += davinci_nand.o +diff -Nur linux-4.1.13.orig/drivers/net/ethernet/microchip/enc28j60.c linux-rpi/drivers/net/ethernet/microchip/enc28j60.c +--- linux-4.1.13.orig/drivers/net/ethernet/microchip/enc28j60.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/net/ethernet/microchip/enc28j60.c 2015-11-29 09:42:38.431197557 +0100 +@@ -1630,10 +1630,21 @@ + return 0; + } + ++#ifdef CONFIG_OF ++static const struct of_device_id enc28j60_of_match[] = { ++ { .compatible = "microchip,enc28j60", }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, enc28j60_of_match); ++#endif ++ + static struct spi_driver enc28j60_driver = { + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, ++#ifdef CONFIG_OF ++ .of_match_table = enc28j60_of_match, ++#endif + }, + .probe = enc28j60_probe, + .remove = enc28j60_remove, +diff -Nur linux-4.1.13.orig/drivers/net/usb/smsc95xx.c linux-rpi/drivers/net/usb/smsc95xx.c +--- linux-4.1.13.orig/drivers/net/usb/smsc95xx.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/net/usb/smsc95xx.c 2015-11-29 09:42:38.627184535 +0100 +@@ -59,6 +59,7 @@ + #define SUSPEND_SUSPEND3 (0x08) + #define SUSPEND_ALLMODES (SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \ + SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3) ++#define MAC_ADDR_LEN (6) + + struct smsc95xx_priv { + u32 mac_cr; +@@ -70,10 +71,14 @@ + u8 suspend_flags; + }; + +-static bool turbo_mode = true; ++static bool turbo_mode = false; + module_param(turbo_mode, bool, 0644); + MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction"); + ++static char *macaddr = ":"; ++module_param(macaddr, charp, 0); ++MODULE_PARM_DESC(macaddr, "MAC address"); ++ + static int __must_check __smsc95xx_read_reg(struct usbnet *dev, u32 index, + u32 *data, int in_pm) + { +@@ -763,8 +768,59 @@ + return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); + } + ++/* Check the macaddr module parameter for a MAC address */ ++static int smsc95xx_is_macaddr_param(struct usbnet *dev, u8 *dev_mac) ++{ ++ int i, j, got_num, num; ++ u8 mtbl[MAC_ADDR_LEN]; ++ ++ if (macaddr[0] == ':') ++ return 0; ++ ++ i = 0; ++ j = 0; ++ num = 0; ++ got_num = 0; ++ while (j < MAC_ADDR_LEN) { ++ if (macaddr[i] && macaddr[i] != ':') { ++ got_num++; ++ if ('0' <= macaddr[i] && macaddr[i] <= '9') ++ num = num * 16 + macaddr[i] - '0'; ++ else if ('A' <= macaddr[i] && macaddr[i] <= 'F') ++ num = num * 16 + 10 + macaddr[i] - 'A'; ++ else if ('a' <= macaddr[i] && macaddr[i] <= 'f') ++ num = num * 16 + 10 + macaddr[i] - 'a'; ++ else ++ break; ++ i++; ++ } else if (got_num == 2) { ++ mtbl[j++] = (u8) num; ++ num = 0; ++ got_num = 0; ++ i++; ++ } else { ++ break; ++ } ++ } ++ ++ if (j == MAC_ADDR_LEN) { ++ netif_dbg(dev, ifup, dev->net, "Overriding MAC address with: " ++ "%02x:%02x:%02x:%02x:%02x:%02x\n", mtbl[0], mtbl[1], mtbl[2], ++ mtbl[3], mtbl[4], mtbl[5]); ++ for (i = 0; i < MAC_ADDR_LEN; i++) ++ dev_mac[i] = mtbl[i]; ++ return 1; ++ } else { ++ return 0; ++ } ++} ++ + static void smsc95xx_init_mac_address(struct usbnet *dev) + { ++ /* Check module parameters */ ++ if (smsc95xx_is_macaddr_param(dev, dev->net->dev_addr)) ++ return; ++ + /* try reading mac address from EEPROM */ + if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN, + dev->net->dev_addr) == 0) { +@@ -1785,7 +1841,6 @@ + if (dev->net->features & NETIF_F_RXCSUM) + smsc95xx_rx_csum_offload(skb); + skb_trim(skb, skb->len - 4); /* remove fcs */ +- skb->truesize = size + sizeof(struct sk_buff); + + return 1; + } +@@ -1803,7 +1858,6 @@ + if (dev->net->features & NETIF_F_RXCSUM) + smsc95xx_rx_csum_offload(ax_skb); + skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */ +- ax_skb->truesize = size + sizeof(struct sk_buff); + + usbnet_skb_return(dev, ax_skb); + } +diff -Nur linux-4.1.13.orig/drivers/net/wireless/Kconfig linux-rpi/drivers/net/wireless/Kconfig +--- linux-4.1.13.orig/drivers/net/wireless/Kconfig 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/net/wireless/Kconfig 2015-11-29 09:43:36.719324606 +0100 +@@ -277,6 +277,7 @@ + source "drivers/net/wireless/orinoco/Kconfig" + source "drivers/net/wireless/p54/Kconfig" + source "drivers/net/wireless/rt2x00/Kconfig" ++source "drivers/net/wireless/mediatek/Kconfig" + source "drivers/net/wireless/rtlwifi/Kconfig" + source "drivers/net/wireless/ti/Kconfig" + source "drivers/net/wireless/zd1211rw/Kconfig" +diff -Nur linux-4.1.13.orig/drivers/net/wireless/Makefile linux-rpi/drivers/net/wireless/Makefile +--- linux-4.1.13.orig/drivers/net/wireless/Makefile 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/net/wireless/Makefile 2015-11-29 09:43:52.726261026 +0100 +@@ -45,6 +45,8 @@ + obj-$(CONFIG_IWLEGACY) += iwlegacy/ + obj-$(CONFIG_RT2X00) += rt2x00/ + ++obj-$(CONFIG_WL_MEDIATEK) += mediatek/ ++ + obj-$(CONFIG_P54_COMMON) += p54/ + + obj-$(CONFIG_ATH_CARDS) += ath/ +diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/Kconfig linux-rpi/drivers/net/wireless/mediatek/Kconfig +--- linux-4.1.13.orig/drivers/net/wireless/mediatek/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/net/wireless/mediatek/Kconfig 2015-11-29 09:42:38.887167260 +0100 +@@ -0,0 +1,10 @@ ++menuconfig WL_MEDIATEK ++ bool "Mediatek Wireless LAN support" ++ ---help--- ++ Enable community drivers for MediaTek WiFi devices. ++ Those drivers make use of the Linux mac80211 stack. ++ ++ ++if WL_MEDIATEK ++source "drivers/net/wireless/mediatek/mt7601u/Kconfig" ++endif # WL_MEDIATEK +diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/Makefile linux-rpi/drivers/net/wireless/mediatek/Makefile +--- linux-4.1.13.orig/drivers/net/wireless/mediatek/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/net/wireless/mediatek/Makefile 2015-11-29 09:42:38.887167260 +0100 +@@ -0,0 +1 @@ ++obj-$(CONFIG_MT7601U) += mt7601u/ +diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/core.c linux-rpi/drivers/net/wireless/mediatek/mt7601u/core.c +--- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/core.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/core.c 2015-11-29 09:42:38.887167260 +0100 +@@ -0,0 +1,78 @@ ++/* ++ * Copyright (C) 2014 Felix Fietkau ++ * Copyright (C) 2015 Jakub Kicinski ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 ++ * as published by the Free Software Foundation ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include "mt7601u.h" ++ ++int mt7601u_wait_asic_ready(struct mt7601u_dev *dev) ++{ ++ int i = 100; ++ u32 val; ++ ++ do { ++ if (test_bit(MT7601U_STATE_REMOVED, &dev->state)) ++ return -EIO; ++ ++ val = mt7601u_rr(dev, MT_MAC_CSR0); ++ if (val && ~val) ++ return 0; ++ ++ udelay(10); ++ } while (i--); ++ ++ return -EIO; ++} ++ ++bool mt76_poll(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val, ++ int timeout) ++{ ++ u32 cur; ++ ++ timeout /= 10; ++ do { ++ if (test_bit(MT7601U_STATE_REMOVED, &dev->state)) ++ return false; ++ ++ cur = mt7601u_rr(dev, offset) & mask; ++ if (cur == val) ++ return true; ++ ++ udelay(10); ++ } while (timeout-- > 0); ++ ++ dev_err(dev->dev, "Error: Time out with reg %08x\n", offset); ++ ++ return false; ++} ++ ++bool mt76_poll_msec(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val, ++ int timeout) ++{ ++ u32 cur; ++ ++ timeout /= 10; ++ do { ++ if (test_bit(MT7601U_STATE_REMOVED, &dev->state)) ++ return false; ++ ++ cur = mt7601u_rr(dev, offset) & mask; ++ if (cur == val) ++ return true; ++ ++ msleep(10); ++ } while (timeout-- > 0); ++ ++ dev_err(dev->dev, "Error: Time out with reg %08x\n", offset); ++ ++ return false; ++} +diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/debugfs.c linux-rpi/drivers/net/wireless/mediatek/mt7601u/debugfs.c +--- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/debugfs.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/debugfs.c 2015-11-29 09:42:38.887167260 +0100 +@@ -0,0 +1,172 @@ ++/* ++ * Copyright (C) 2014 Felix Fietkau ++ * Copyright (C) 2015 Jakub Kicinski ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 ++ * as published by the Free Software Foundation ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++ ++#include "mt7601u.h" ++#include "eeprom.h" ++ ++static int ++mt76_reg_set(void *data, u64 val) ++{ ++ struct mt7601u_dev *dev = data; ++ ++ mt76_wr(dev, dev->debugfs_reg, val); ++ return 0; ++} ++ ++static int ++mt76_reg_get(void *data, u64 *val) ++{ ++ struct mt7601u_dev *dev = data; ++ ++ *val = mt76_rr(dev, dev->debugfs_reg); ++ return 0; ++} ++ ++DEFINE_SIMPLE_ATTRIBUTE(fops_regval, mt76_reg_get, mt76_reg_set, "0x%08llx\n"); ++ ++static int ++mt7601u_ampdu_stat_read(struct seq_file *file, void *data) ++{ ++ struct mt7601u_dev *dev = file->private; ++ int i, j; ++ ++#define stat_printf(grp, off, name) \ ++ seq_printf(file, #name ":\t%llu\n", dev->stats.grp[off]) ++ ++ stat_printf(rx_stat, 0, rx_crc_err); ++ stat_printf(rx_stat, 1, rx_phy_err); ++ stat_printf(rx_stat, 2, rx_false_cca); ++ stat_printf(rx_stat, 3, rx_plcp_err); ++ stat_printf(rx_stat, 4, rx_fifo_overflow); ++ stat_printf(rx_stat, 5, rx_duplicate); ++ ++ stat_printf(tx_stat, 0, tx_fail_cnt); ++ stat_printf(tx_stat, 1, tx_bcn_cnt); ++ stat_printf(tx_stat, 2, tx_success); ++ stat_printf(tx_stat, 3, tx_retransmit); ++ stat_printf(tx_stat, 4, tx_zero_len); ++ stat_printf(tx_stat, 5, tx_underflow); ++ ++ stat_printf(aggr_stat, 0, non_aggr_tx); ++ stat_printf(aggr_stat, 1, aggr_tx); ++ ++ stat_printf(zero_len_del, 0, tx_zero_len_del); ++ stat_printf(zero_len_del, 1, rx_zero_len_del); ++#undef stat_printf ++ ++ seq_puts(file, "Aggregations stats:\n"); ++ for (i = 0; i < 4; i++) { ++ for (j = 0; j < 8; j++) ++ seq_printf(file, "%08llx ", ++ dev->stats.aggr_n[i * 8 + j]); ++ seq_putc(file, '\n'); ++ } ++ ++ seq_printf(file, "recent average AMPDU len: %d\n", ++ atomic_read(&dev->avg_ampdu_len)); ++ ++ return 0; ++} ++ ++static int ++mt7601u_ampdu_stat_open(struct inode *inode, struct file *f) ++{ ++ return single_open(f, mt7601u_ampdu_stat_read, inode->i_private); ++} ++ ++static const struct file_operations fops_ampdu_stat = { ++ .open = mt7601u_ampdu_stat_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++static int ++mt7601u_eeprom_param_read(struct seq_file *file, void *data) ++{ ++ struct mt7601u_dev *dev = file->private; ++ struct mt7601u_rate_power *rp = &dev->ee->power_rate_table; ++ struct tssi_data *td = &dev->ee->tssi_data; ++ int i; ++ ++ seq_printf(file, "RF freq offset: %hhx\n", dev->ee->rf_freq_off); ++ seq_printf(file, "RSSI offset: %hhx %hhx\n", ++ dev->ee->rssi_offset[0], dev->ee->rssi_offset[1]); ++ seq_printf(file, "Reference temp: %hhx\n", dev->ee->ref_temp); ++ seq_printf(file, "LNA gain: %hhx\n", dev->ee->lna_gain); ++ seq_printf(file, "Reg channels: %hhu-%hhu\n", dev->ee->reg.start, ++ dev->ee->reg.start + dev->ee->reg.num - 1); ++ ++ seq_puts(file, "Per rate power:\n"); ++ for (i = 0; i < 2; i++) ++ seq_printf(file, "\t raw:%02hhx bw20:%02hhx bw40:%02hhx\n", ++ rp->cck[i].raw, rp->cck[i].bw20, rp->cck[i].bw40); ++ for (i = 0; i < 4; i++) ++ seq_printf(file, "\t raw:%02hhx bw20:%02hhx bw40:%02hhx\n", ++ rp->ofdm[i].raw, rp->ofdm[i].bw20, rp->ofdm[i].bw40); ++ for (i = 0; i < 4; i++) ++ seq_printf(file, "\t raw:%02hhx bw20:%02hhx bw40:%02hhx\n", ++ rp->ht[i].raw, rp->ht[i].bw20, rp->ht[i].bw40); ++ ++ seq_puts(file, "Per channel power:\n"); ++ for (i = 0; i < 7; i++) ++ seq_printf(file, "\t tx_power ch%u:%02hhx ch%u:%02hhx\n", ++ i * 2 + 1, dev->ee->chan_pwr[i * 2], ++ i * 2 + 2, dev->ee->chan_pwr[i * 2 + 1]); ++ ++ if (!dev->ee->tssi_enabled) ++ return 0; ++ ++ seq_puts(file, "TSSI:\n"); ++ seq_printf(file, "\t slope:%02hhx\n", td->slope); ++ seq_printf(file, "\t offset=%02hhx %02hhx %02hhx\n", ++ td->offset[0], td->offset[1], td->offset[2]); ++ seq_printf(file, "\t delta_off:%08x\n", td->tx0_delta_offset); ++ ++ return 0; ++} ++ ++static int ++mt7601u_eeprom_param_open(struct inode *inode, struct file *f) ++{ ++ return single_open(f, mt7601u_eeprom_param_read, inode->i_private); ++} ++ ++static const struct file_operations fops_eeprom_param = { ++ .open = mt7601u_eeprom_param_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++void mt7601u_init_debugfs(struct mt7601u_dev *dev) ++{ ++ struct dentry *dir; ++ ++ dir = debugfs_create_dir("mt7601u", dev->hw->wiphy->debugfsdir); ++ if (!dir) ++ return; ++ ++ debugfs_create_u8("temperature", S_IRUSR, dir, &dev->raw_temp); ++ debugfs_create_u32("temp_mode", S_IRUSR, dir, &dev->temp_mode); ++ ++ debugfs_create_u32("regidx", S_IRUSR | S_IWUSR, dir, &dev->debugfs_reg); ++ debugfs_create_file("regval", S_IRUSR | S_IWUSR, dir, dev, ++ &fops_regval); ++ debugfs_create_file("ampdu_stat", S_IRUSR, dir, dev, &fops_ampdu_stat); ++ debugfs_create_file("eeprom_param", S_IRUSR, dir, dev, ++ &fops_eeprom_param); ++} +diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/dma.c linux-rpi/drivers/net/wireless/mediatek/mt7601u/dma.c +--- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/dma.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/dma.c 2015-11-29 09:42:38.887167260 +0100 +@@ -0,0 +1,529 @@ ++/* ++ * Copyright (C) 2015 Jakub Kicinski ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 ++ * as published by the Free Software Foundation ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include "mt7601u.h" ++#include "dma.h" ++#include "usb.h" ++#include "trace.h" ++ ++static int mt7601u_submit_rx_buf(struct mt7601u_dev *dev, ++ struct mt7601u_dma_buf_rx *e, gfp_t gfp); ++ ++static unsigned int ieee80211_get_hdrlen_from_buf(const u8 *data, unsigned len) ++{ ++ const struct ieee80211_hdr *hdr = (const struct ieee80211_hdr *)data; ++ unsigned int hdrlen; ++ ++ if (unlikely(len < 10)) ++ return 0; ++ hdrlen = ieee80211_hdrlen(hdr->frame_control); ++ if (unlikely(hdrlen > len)) ++ return 0; ++ return hdrlen; ++} ++ ++static struct sk_buff * ++mt7601u_rx_skb_from_seg(struct mt7601u_dev *dev, struct mt7601u_rxwi *rxwi, ++ void *data, u32 seg_len, u32 truesize, struct page *p) ++{ ++ struct sk_buff *skb; ++ u32 true_len, hdr_len = 0, copy, frag; ++ ++ skb = alloc_skb(p ? 128 : seg_len, GFP_ATOMIC); ++ if (!skb) ++ return NULL; ++ ++ true_len = mt76_mac_process_rx(dev, skb, data, rxwi); ++ if (!true_len || true_len > seg_len) ++ goto bad_frame; ++ ++ hdr_len = ieee80211_get_hdrlen_from_buf(data, true_len); ++ if (!hdr_len) ++ goto bad_frame; ++ ++ if (rxwi->rxinfo & cpu_to_le32(MT_RXINFO_L2PAD)) { ++ memcpy(skb_put(skb, hdr_len), data, hdr_len); ++ ++ data += hdr_len + 2; ++ true_len -= hdr_len; ++ hdr_len = 0; ++ } ++ ++ /* If not doing paged RX allocated skb will always have enough space */ ++ copy = (true_len <= skb_tailroom(skb)) ? true_len : hdr_len + 8; ++ frag = true_len - copy; ++ ++ memcpy(skb_put(skb, copy), data, copy); ++ data += copy; ++ ++ if (frag) { ++ skb_add_rx_frag(skb, 0, p, data - page_address(p), ++ frag, truesize); ++ get_page(p); ++ } ++ ++ return skb; ++ ++bad_frame: ++ dev_err_ratelimited(dev->dev, "Error: incorrect frame len:%u hdr:%u\n", ++ true_len, hdr_len); ++ dev_kfree_skb(skb); ++ return NULL; ++} ++ ++static void mt7601u_rx_process_seg(struct mt7601u_dev *dev, u8 *data, ++ u32 seg_len, struct page *p) ++{ ++ struct sk_buff *skb; ++ struct mt7601u_rxwi *rxwi; ++ u32 fce_info, truesize = seg_len; ++ ++ /* DMA_INFO field at the beginning of the segment contains only some of ++ * the information, we need to read the FCE descriptor from the end. ++ */ ++ fce_info = get_unaligned_le32(data + seg_len - MT_FCE_INFO_LEN); ++ seg_len -= MT_FCE_INFO_LEN; ++ ++ data += MT_DMA_HDR_LEN; ++ seg_len -= MT_DMA_HDR_LEN; ++ ++ rxwi = (struct mt7601u_rxwi *) data; ++ data += sizeof(struct mt7601u_rxwi); ++ seg_len -= sizeof(struct mt7601u_rxwi); ++ ++ if (unlikely(rxwi->zero[0] || rxwi->zero[1] || rxwi->zero[2])) ++ dev_err_once(dev->dev, "Error: RXWI zero fields are set\n"); ++ if (unlikely(MT76_GET(MT_RXD_INFO_TYPE, fce_info))) ++ dev_err_once(dev->dev, "Error: RX path seen a non-pkt urb\n"); ++ ++ trace_mt_rx(dev, rxwi, fce_info); ++ ++ skb = mt7601u_rx_skb_from_seg(dev, rxwi, data, seg_len, truesize, p); ++ if (!skb) ++ return; ++ ++ spin_lock(&dev->mac_lock); ++ ieee80211_rx(dev->hw, skb); ++ spin_unlock(&dev->mac_lock); ++} ++ ++static u16 mt7601u_rx_next_seg_len(u8 *data, u32 data_len) ++{ ++ u32 min_seg_len = MT_DMA_HDR_LEN + MT_RX_INFO_LEN + ++ sizeof(struct mt7601u_rxwi) + MT_FCE_INFO_LEN; ++ u16 dma_len = get_unaligned_le16(data); ++ ++ if (data_len < min_seg_len || ++ WARN_ON(!dma_len) || ++ WARN_ON(dma_len + MT_DMA_HDRS > data_len) || ++ WARN_ON(dma_len & 0x3)) ++ return 0; ++ ++ return MT_DMA_HDRS + dma_len; ++} ++ ++static void ++mt7601u_rx_process_entry(struct mt7601u_dev *dev, struct mt7601u_dma_buf_rx *e) ++{ ++ u32 seg_len, data_len = e->urb->actual_length; ++ u8 *data = page_address(e->p); ++ struct page *new_p = NULL; ++ int cnt = 0; ++ ++ if (!test_bit(MT7601U_STATE_INITIALIZED, &dev->state)) ++ return; ++ ++ /* Copy if there is very little data in the buffer. */ ++ if (data_len > 512) ++ new_p = dev_alloc_pages(MT_RX_ORDER); ++ ++ while ((seg_len = mt7601u_rx_next_seg_len(data, data_len))) { ++ mt7601u_rx_process_seg(dev, data, seg_len, new_p ? e->p : NULL); ++ ++ data_len -= seg_len; ++ data += seg_len; ++ cnt++; ++ } ++ ++ if (cnt > 1) ++ trace_mt_rx_dma_aggr(dev, cnt, !!new_p); ++ ++ if (new_p) { ++ /* we have one extra ref from the allocator */ ++ __free_pages(e->p, MT_RX_ORDER); ++ ++ e->p = new_p; ++ } ++} ++ ++static struct mt7601u_dma_buf_rx * ++mt7601u_rx_get_pending_entry(struct mt7601u_dev *dev) ++{ ++ struct mt7601u_rx_queue *q = &dev->rx_q; ++ struct mt7601u_dma_buf_rx *buf = NULL; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&dev->rx_lock, flags); ++ ++ if (!q->pending) ++ goto out; ++ ++ buf = &q->e[q->start]; ++ q->pending--; ++ q->start = (q->start + 1) % q->entries; ++out: ++ spin_unlock_irqrestore(&dev->rx_lock, flags); ++ ++ return buf; ++} ++ ++static void mt7601u_complete_rx(struct urb *urb) ++{ ++ struct mt7601u_dev *dev = urb->context; ++ struct mt7601u_rx_queue *q = &dev->rx_q; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&dev->rx_lock, flags); ++ ++ if (mt7601u_urb_has_error(urb)) ++ dev_err(dev->dev, "Error: RX urb failed:%d\n", urb->status); ++ if (WARN_ONCE(q->e[q->end].urb != urb, "RX urb mismatch")) ++ goto out; ++ ++ q->end = (q->end + 1) % q->entries; ++ q->pending++; ++ tasklet_schedule(&dev->rx_tasklet); ++out: ++ spin_unlock_irqrestore(&dev->rx_lock, flags); ++} ++ ++static void mt7601u_rx_tasklet(unsigned long data) ++{ ++ struct mt7601u_dev *dev = (struct mt7601u_dev *) data; ++ struct mt7601u_dma_buf_rx *e; ++ ++ while ((e = mt7601u_rx_get_pending_entry(dev))) { ++ if (e->urb->status) ++ continue; ++ ++ mt7601u_rx_process_entry(dev, e); ++ mt7601u_submit_rx_buf(dev, e, GFP_ATOMIC); ++ } ++} ++ ++static void mt7601u_complete_tx(struct urb *urb) ++{ ++ struct mt7601u_tx_queue *q = urb->context; ++ struct mt7601u_dev *dev = q->dev; ++ struct sk_buff *skb; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&dev->tx_lock, flags); ++ ++ if (mt7601u_urb_has_error(urb)) ++ dev_err(dev->dev, "Error: TX urb failed:%d\n", urb->status); ++ if (WARN_ONCE(q->e[q->start].urb != urb, "TX urb mismatch")) ++ goto out; ++ ++ skb = q->e[q->start].skb; ++ trace_mt_tx_dma_done(dev, skb); ++ ++ __skb_queue_tail(&dev->tx_skb_done, skb); ++ tasklet_schedule(&dev->tx_tasklet); ++ ++ if (q->used == q->entries - q->entries / 8) ++ ieee80211_wake_queue(dev->hw, skb_get_queue_mapping(skb)); ++ ++ q->start = (q->start + 1) % q->entries; ++ q->used--; ++out: ++ spin_unlock_irqrestore(&dev->tx_lock, flags); ++} ++ ++static void mt7601u_tx_tasklet(unsigned long data) ++{ ++ struct mt7601u_dev *dev = (struct mt7601u_dev *) data; ++ struct sk_buff_head skbs; ++ unsigned long flags; ++ ++ __skb_queue_head_init(&skbs); ++ ++ spin_lock_irqsave(&dev->tx_lock, flags); ++ ++ set_bit(MT7601U_STATE_MORE_STATS, &dev->state); ++ if (!test_and_set_bit(MT7601U_STATE_READING_STATS, &dev->state)) ++ queue_delayed_work(dev->stat_wq, &dev->stat_work, ++ msecs_to_jiffies(10)); ++ ++ skb_queue_splice_init(&dev->tx_skb_done, &skbs); ++ ++ spin_unlock_irqrestore(&dev->tx_lock, flags); ++ ++ while (!skb_queue_empty(&skbs)) { ++ struct sk_buff *skb = __skb_dequeue(&skbs); ++ ++ mt7601u_tx_status(dev, skb); ++ } ++} ++ ++static int mt7601u_dma_submit_tx(struct mt7601u_dev *dev, ++ struct sk_buff *skb, u8 ep) ++{ ++ struct usb_device *usb_dev = mt7601u_to_usb_dev(dev); ++ unsigned snd_pipe = usb_sndbulkpipe(usb_dev, dev->out_eps[ep]); ++ struct mt7601u_dma_buf_tx *e; ++ struct mt7601u_tx_queue *q = &dev->tx_q[ep]; ++ unsigned long flags; ++ int ret; ++ ++ spin_lock_irqsave(&dev->tx_lock, flags); ++ ++ if (WARN_ON(q->entries <= q->used)) { ++ ret = -ENOSPC; ++ goto out; ++ } ++ ++ e = &q->e[q->end]; ++ e->skb = skb; ++ usb_fill_bulk_urb(e->urb, usb_dev, snd_pipe, skb->data, skb->len, ++ mt7601u_complete_tx, q); ++ ret = usb_submit_urb(e->urb, GFP_ATOMIC); ++ if (ret) { ++ /* Special-handle ENODEV from TX urb submission because it will ++ * often be the first ENODEV we see after device is removed. ++ */ ++ if (ret == -ENODEV) ++ set_bit(MT7601U_STATE_REMOVED, &dev->state); ++ else ++ dev_err(dev->dev, "Error: TX urb submit failed:%d\n", ++ ret); ++ goto out; ++ } ++ ++ q->end = (q->end + 1) % q->entries; ++ q->used++; ++ ++ if (q->used >= q->entries) ++ ieee80211_stop_queue(dev->hw, skb_get_queue_mapping(skb)); ++out: ++ spin_unlock_irqrestore(&dev->tx_lock, flags); ++ ++ return ret; ++} ++ ++/* Map hardware Q to USB endpoint number */ ++static u8 q2ep(u8 qid) ++{ ++ /* TODO: take management packets to queue 5 */ ++ return qid + 1; ++} ++ ++/* Map USB endpoint number to Q id in the DMA engine */ ++static enum mt76_qsel ep2dmaq(u8 ep) ++{ ++ if (ep == 5) ++ return MT_QSEL_MGMT; ++ return MT_QSEL_EDCA; ++} ++ ++int mt7601u_dma_enqueue_tx(struct mt7601u_dev *dev, struct sk_buff *skb, ++ struct mt76_wcid *wcid, int hw_q) ++{ ++ u8 ep = q2ep(hw_q); ++ u32 dma_flags; ++ int ret; ++ ++ dma_flags = MT_TXD_PKT_INFO_80211; ++ if (wcid->hw_key_idx == 0xff) ++ dma_flags |= MT_TXD_PKT_INFO_WIV; ++ ++ ret = mt7601u_dma_skb_wrap_pkt(skb, ep2dmaq(ep), dma_flags); ++ if (ret) ++ return ret; ++ ++ ret = mt7601u_dma_submit_tx(dev, skb, ep); ++ if (ret) { ++ ieee80211_free_txskb(dev->hw, skb); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static void mt7601u_kill_rx(struct mt7601u_dev *dev) ++{ ++ int i; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&dev->rx_lock, flags); ++ ++ for (i = 0; i < dev->rx_q.entries; i++) { ++ int next = dev->rx_q.end; ++ ++ spin_unlock_irqrestore(&dev->rx_lock, flags); ++ usb_poison_urb(dev->rx_q.e[next].urb); ++ spin_lock_irqsave(&dev->rx_lock, flags); ++ } ++ ++ spin_unlock_irqrestore(&dev->rx_lock, flags); ++} ++ ++static int mt7601u_submit_rx_buf(struct mt7601u_dev *dev, ++ struct mt7601u_dma_buf_rx *e, gfp_t gfp) ++{ ++ struct usb_device *usb_dev = mt7601u_to_usb_dev(dev); ++ u8 *buf = page_address(e->p); ++ unsigned pipe; ++ int ret; ++ ++ pipe = usb_rcvbulkpipe(usb_dev, dev->in_eps[MT_EP_IN_PKT_RX]); ++ ++ usb_fill_bulk_urb(e->urb, usb_dev, pipe, buf, MT_RX_URB_SIZE, ++ mt7601u_complete_rx, dev); ++ ++ trace_mt_submit_urb(dev, e->urb); ++ ret = usb_submit_urb(e->urb, gfp); ++ if (ret) ++ dev_err(dev->dev, "Error: submit RX URB failed:%d\n", ret); ++ ++ return ret; ++} ++ ++static int mt7601u_submit_rx(struct mt7601u_dev *dev) ++{ ++ int i, ret; ++ ++ for (i = 0; i < dev->rx_q.entries; i++) { ++ ret = mt7601u_submit_rx_buf(dev, &dev->rx_q.e[i], GFP_KERNEL); ++ if (ret) ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static void mt7601u_free_rx(struct mt7601u_dev *dev) ++{ ++ int i; ++ ++ for (i = 0; i < dev->rx_q.entries; i++) { ++ __free_pages(dev->rx_q.e[i].p, MT_RX_ORDER); ++ usb_free_urb(dev->rx_q.e[i].urb); ++ } ++} ++ ++static int mt7601u_alloc_rx(struct mt7601u_dev *dev) ++{ ++ int i; ++ ++ memset(&dev->rx_q, 0, sizeof(dev->rx_q)); ++ dev->rx_q.dev = dev; ++ dev->rx_q.entries = N_RX_ENTRIES; ++ ++ for (i = 0; i < N_RX_ENTRIES; i++) { ++ dev->rx_q.e[i].urb = usb_alloc_urb(0, GFP_KERNEL); ++ dev->rx_q.e[i].p = dev_alloc_pages(MT_RX_ORDER); ++ ++ if (!dev->rx_q.e[i].urb || !dev->rx_q.e[i].p) ++ return -ENOMEM; ++ } ++ ++ return 0; ++} ++ ++static void mt7601u_free_tx_queue(struct mt7601u_tx_queue *q) ++{ ++ int i; ++ ++ WARN_ON(q->used); ++ ++ for (i = 0; i < q->entries; i++) { ++ usb_poison_urb(q->e[i].urb); ++ usb_free_urb(q->e[i].urb); ++ } ++} ++ ++static void mt7601u_free_tx(struct mt7601u_dev *dev) ++{ ++ int i; ++ ++ for (i = 0; i < __MT_EP_OUT_MAX; i++) ++ mt7601u_free_tx_queue(&dev->tx_q[i]); ++} ++ ++static int mt7601u_alloc_tx_queue(struct mt7601u_dev *dev, ++ struct mt7601u_tx_queue *q) ++{ ++ int i; ++ ++ q->dev = dev; ++ q->entries = N_TX_ENTRIES; ++ ++ for (i = 0; i < N_TX_ENTRIES; i++) { ++ q->e[i].urb = usb_alloc_urb(0, GFP_KERNEL); ++ if (!q->e[i].urb) ++ return -ENOMEM; ++ } ++ ++ return 0; ++} ++ ++static int mt7601u_alloc_tx(struct mt7601u_dev *dev) ++{ ++ int i; ++ ++ dev->tx_q = devm_kcalloc(dev->dev, __MT_EP_OUT_MAX, ++ sizeof(*dev->tx_q), GFP_KERNEL); ++ ++ for (i = 0; i < __MT_EP_OUT_MAX; i++) ++ if (mt7601u_alloc_tx_queue(dev, &dev->tx_q[i])) ++ return -ENOMEM; ++ ++ return 0; ++} ++ ++int mt7601u_dma_init(struct mt7601u_dev *dev) ++{ ++ int ret = -ENOMEM; ++ ++ tasklet_init(&dev->tx_tasklet, mt7601u_tx_tasklet, (unsigned long) dev); ++ tasklet_init(&dev->rx_tasklet, mt7601u_rx_tasklet, (unsigned long) dev); ++ ++ ret = mt7601u_alloc_tx(dev); ++ if (ret) ++ goto err; ++ ret = mt7601u_alloc_rx(dev); ++ if (ret) ++ goto err; ++ ++ ret = mt7601u_submit_rx(dev); ++ if (ret) ++ goto err; ++ ++ return 0; ++err: ++ mt7601u_dma_cleanup(dev); ++ return ret; ++} ++ ++void mt7601u_dma_cleanup(struct mt7601u_dev *dev) ++{ ++ mt7601u_kill_rx(dev); ++ ++ tasklet_kill(&dev->rx_tasklet); ++ ++ mt7601u_free_rx(dev); ++ mt7601u_free_tx(dev); ++ ++ tasklet_kill(&dev->tx_tasklet); ++} +diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/dma.h linux-rpi/drivers/net/wireless/mediatek/mt7601u/dma.h +--- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/dma.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/dma.h 2015-11-29 09:42:38.887167260 +0100 +@@ -0,0 +1,127 @@ ++/* ++ * Copyright (C) 2014 Felix Fietkau ++ * Copyright (C) 2015 Jakub Kicinski ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 ++ * as published by the Free Software Foundation ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef __MT7601U_DMA_H ++#define __MT7601U_DMA_H ++ ++#include ++#include ++ ++#include "util.h" ++ ++#define MT_DMA_HDR_LEN 4 ++#define MT_RX_INFO_LEN 4 ++#define MT_FCE_INFO_LEN 4 ++#define MT_DMA_HDRS (MT_DMA_HDR_LEN + MT_RX_INFO_LEN) ++ ++/* Common Tx DMA descriptor fields */ ++#define MT_TXD_INFO_LEN GENMASK(15, 0) ++#define MT_TXD_INFO_D_PORT GENMASK(29, 27) ++#define MT_TXD_INFO_TYPE GENMASK(31, 30) ++ ++enum mt76_msg_port { ++ WLAN_PORT, ++ CPU_RX_PORT, ++ CPU_TX_PORT, ++ HOST_PORT, ++ VIRTUAL_CPU_RX_PORT, ++ VIRTUAL_CPU_TX_PORT, ++ DISCARD, ++}; ++ ++enum mt76_info_type { ++ DMA_PACKET, ++ DMA_COMMAND, ++}; ++ ++/* Tx DMA packet specific flags */ ++#define MT_TXD_PKT_INFO_NEXT_VLD BIT(16) ++#define MT_TXD_PKT_INFO_TX_BURST BIT(17) ++#define MT_TXD_PKT_INFO_80211 BIT(19) ++#define MT_TXD_PKT_INFO_TSO BIT(20) ++#define MT_TXD_PKT_INFO_CSO BIT(21) ++#define MT_TXD_PKT_INFO_WIV BIT(24) ++#define MT_TXD_PKT_INFO_QSEL GENMASK(26, 25) ++ ++enum mt76_qsel { ++ MT_QSEL_MGMT, ++ MT_QSEL_HCCA, ++ MT_QSEL_EDCA, ++ MT_QSEL_EDCA_2, ++}; ++ ++/* Tx DMA MCU command specific flags */ ++#define MT_TXD_CMD_INFO_SEQ GENMASK(19, 16) ++#define MT_TXD_CMD_INFO_TYPE GENMASK(26, 20) ++ ++static inline int mt7601u_dma_skb_wrap(struct sk_buff *skb, ++ enum mt76_msg_port d_port, ++ enum mt76_info_type type, u32 flags) ++{ ++ u32 info; ++ ++ /* Buffer layout: ++ * | 4B | xfer len | pad | 4B | ++ * | TXINFO | pkt/cmd | zero pad to 4B | zero | ++ * ++ * length field of TXINFO should be set to 'xfer len'. ++ */ ++ ++ info = flags | ++ MT76_SET(MT_TXD_INFO_LEN, round_up(skb->len, 4)) | ++ MT76_SET(MT_TXD_INFO_D_PORT, d_port) | ++ MT76_SET(MT_TXD_INFO_TYPE, type); ++ ++ put_unaligned_le32(info, skb_push(skb, sizeof(info))); ++ return skb_put_padto(skb, round_up(skb->len, 4) + 4); ++} ++ ++static inline int ++mt7601u_dma_skb_wrap_pkt(struct sk_buff *skb, enum mt76_qsel qsel, u32 flags) ++{ ++ flags |= MT76_SET(MT_TXD_PKT_INFO_QSEL, qsel); ++ return mt7601u_dma_skb_wrap(skb, WLAN_PORT, DMA_PACKET, flags); ++} ++ ++/* Common Rx DMA descriptor fields */ ++#define MT_RXD_INFO_LEN GENMASK(13, 0) ++#define MT_RXD_INFO_PCIE_INTR BIT(24) ++#define MT_RXD_INFO_QSEL GENMASK(26, 25) ++#define MT_RXD_INFO_PORT GENMASK(29, 27) ++#define MT_RXD_INFO_TYPE GENMASK(31, 30) ++ ++/* Rx DMA packet specific flags */ ++#define MT_RXD_PKT_INFO_UDP_ERR BIT(16) ++#define MT_RXD_PKT_INFO_TCP_ERR BIT(17) ++#define MT_RXD_PKT_INFO_IP_ERR BIT(18) ++#define MT_RXD_PKT_INFO_PKT_80211 BIT(19) ++#define MT_RXD_PKT_INFO_L3L4_DONE BIT(20) ++#define MT_RXD_PKT_INFO_MAC_LEN GENMASK(23, 21) ++ ++/* Rx DMA MCU command specific flags */ ++#define MT_RXD_CMD_INFO_SELF_GEN BIT(15) ++#define MT_RXD_CMD_INFO_CMD_SEQ GENMASK(19, 16) ++#define MT_RXD_CMD_INFO_EVT_TYPE GENMASK(23, 20) ++ ++enum mt76_evt_type { ++ CMD_DONE, ++ CMD_ERROR, ++ CMD_RETRY, ++ EVENT_PWR_RSP, ++ EVENT_WOW_RSP, ++ EVENT_CARRIER_DETECT_RSP, ++ EVENT_DFS_DETECT_RSP, ++}; ++ ++#endif +diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/eeprom.c linux-rpi/drivers/net/wireless/mediatek/mt7601u/eeprom.c +--- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/eeprom.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/eeprom.c 2015-11-29 09:42:38.887167260 +0100 +@@ -0,0 +1,418 @@ ++/* ++ * Copyright (C) 2014 Felix Fietkau ++ * Copyright (C) 2015 Jakub Kicinski ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 ++ * as published by the Free Software Foundation ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include "mt7601u.h" ++#include "eeprom.h" ++ ++static bool ++field_valid(u8 val) ++{ ++ return val != 0xff; ++} ++ ++static s8 ++field_validate(u8 val) ++{ ++ if (!field_valid(val)) ++ return 0; ++ ++ return val; ++} ++ ++static int ++mt7601u_efuse_read(struct mt7601u_dev *dev, u16 addr, u8 *data, ++ enum mt7601u_eeprom_access_modes mode) ++{ ++ u32 val; ++ int i; ++ ++ val = mt76_rr(dev, MT_EFUSE_CTRL); ++ val &= ~(MT_EFUSE_CTRL_AIN | ++ MT_EFUSE_CTRL_MODE); ++ val |= MT76_SET(MT_EFUSE_CTRL_AIN, addr & ~0xf) | ++ MT76_SET(MT_EFUSE_CTRL_MODE, mode) | ++ MT_EFUSE_CTRL_KICK; ++ mt76_wr(dev, MT_EFUSE_CTRL, val); ++ ++ if (!mt76_poll(dev, MT_EFUSE_CTRL, MT_EFUSE_CTRL_KICK, 0, 1000)) ++ return -ETIMEDOUT; ++ ++ val = mt76_rr(dev, MT_EFUSE_CTRL); ++ if ((val & MT_EFUSE_CTRL_AOUT) == MT_EFUSE_CTRL_AOUT) { ++ /* Parts of eeprom not in the usage map (0x80-0xc0,0xf0) ++ * will not return valid data but it's ok. ++ */ ++ memset(data, 0xff, 16); ++ return 0; ++ } ++ ++ for (i = 0; i < 4; i++) { ++ val = mt76_rr(dev, MT_EFUSE_DATA(i)); ++ put_unaligned_le32(val, data + 4 * i); ++ } ++ ++ return 0; ++} ++ ++static int ++mt7601u_efuse_physical_size_check(struct mt7601u_dev *dev) ++{ ++ const int map_reads = DIV_ROUND_UP(MT_EFUSE_USAGE_MAP_SIZE, 16); ++ u8 data[map_reads * 16]; ++ int ret, i; ++ u32 start = 0, end = 0, cnt_free; ++ ++ for (i = 0; i < map_reads; i++) { ++ ret = mt7601u_efuse_read(dev, MT_EE_USAGE_MAP_START + i * 16, ++ data + i * 16, MT_EE_PHYSICAL_READ); ++ if (ret) ++ return ret; ++ } ++ ++ for (i = 0; i < MT_EFUSE_USAGE_MAP_SIZE; i++) ++ if (!data[i]) { ++ if (!start) ++ start = MT_EE_USAGE_MAP_START + i; ++ end = MT_EE_USAGE_MAP_START + i; ++ } ++ cnt_free = end - start + 1; ++ ++ if (MT_EFUSE_USAGE_MAP_SIZE - cnt_free < 5) { ++ dev_err(dev->dev, "Error: your device needs default EEPROM file and this driver doesn't support it!\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static bool ++mt7601u_has_tssi(struct mt7601u_dev *dev, u8 *eeprom) ++{ ++ u16 nic_conf1 = get_unaligned_le16(eeprom + MT_EE_NIC_CONF_1); ++ ++ return ~nic_conf1 && (nic_conf1 & MT_EE_NIC_CONF_1_TX_ALC_EN); ++} ++ ++static void ++mt7601u_set_chip_cap(struct mt7601u_dev *dev, u8 *eeprom) ++{ ++ u16 nic_conf0 = get_unaligned_le16(eeprom + MT_EE_NIC_CONF_0); ++ u16 nic_conf1 = get_unaligned_le16(eeprom + MT_EE_NIC_CONF_1); ++ ++ if (!field_valid(nic_conf1 & 0xff)) ++ nic_conf1 &= 0xff00; ++ ++ dev->ee->tssi_enabled = mt7601u_has_tssi(dev, eeprom) && ++ !(nic_conf1 & MT_EE_NIC_CONF_1_TEMP_TX_ALC); ++ ++ if (nic_conf1 & MT_EE_NIC_CONF_1_HW_RF_CTRL) ++ dev_err(dev->dev, ++ "Error: this driver does not support HW RF ctrl\n"); ++ ++ if (!field_valid(nic_conf0 >> 8)) ++ return; ++ ++ if (MT76_GET(MT_EE_NIC_CONF_0_RX_PATH, nic_conf0) > 1 || ++ MT76_GET(MT_EE_NIC_CONF_0_TX_PATH, nic_conf0) > 1) ++ dev_err(dev->dev, ++ "Error: device has more than 1 RX/TX stream!\n"); ++} ++ ++static int ++mt7601u_set_macaddr(struct mt7601u_dev *dev, const u8 *eeprom) ++{ ++ const void *src = eeprom + MT_EE_MAC_ADDR; ++ ++ ether_addr_copy(dev->macaddr, src); ++ ++ if (!is_valid_ether_addr(dev->macaddr)) { ++ eth_random_addr(dev->macaddr); ++ dev_info(dev->dev, ++ "Invalid MAC address, using random address %pM\n", ++ dev->macaddr); ++ } ++ ++ mt76_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(dev->macaddr)); ++ mt76_wr(dev, MT_MAC_ADDR_DW1, get_unaligned_le16(dev->macaddr + 4) | ++ MT76_SET(MT_MAC_ADDR_DW1_U2ME_MASK, 0xff)); ++ ++ return 0; ++} ++ ++static void mt7601u_set_channel_target_power(struct mt7601u_dev *dev, ++ u8 *eeprom, u8 max_pwr) ++{ ++ u8 trgt_pwr = eeprom[MT_EE_TX_TSSI_TARGET_POWER]; ++ ++ if (trgt_pwr > max_pwr || !trgt_pwr) { ++ dev_warn(dev->dev, "Error: EEPROM trgt power invalid %hhx!\n", ++ trgt_pwr); ++ trgt_pwr = 0x20; ++ } ++ ++ memset(dev->ee->chan_pwr, trgt_pwr, sizeof(dev->ee->chan_pwr)); ++} ++ ++static void ++mt7601u_set_channel_power(struct mt7601u_dev *dev, u8 *eeprom) ++{ ++ u32 i, val; ++ u8 max_pwr; ++ ++ val = mt7601u_rr(dev, MT_TX_ALC_CFG_0); ++ max_pwr = MT76_GET(MT_TX_ALC_CFG_0_LIMIT_0, val); ++ ++ if (mt7601u_has_tssi(dev, eeprom)) { ++ mt7601u_set_channel_target_power(dev, eeprom, max_pwr); ++ return; ++ } ++ ++ for (i = 0; i < 14; i++) { ++ s8 power = field_validate(eeprom[MT_EE_TX_POWER_OFFSET + i]); ++ ++ if (power > max_pwr || power < 0) ++ power = MT7601U_DEFAULT_TX_POWER; ++ ++ dev->ee->chan_pwr[i] = power; ++ } ++} ++ ++static void ++mt7601u_set_country_reg(struct mt7601u_dev *dev, u8 *eeprom) ++{ ++ /* Note: - region 31 is not valid for mt7601u (see rtmp_init.c) ++ * - comments in rtmp_def.h are incorrect (see rt_channel.c) ++ */ ++ static const struct reg_channel_bounds chan_bounds[] = { ++ /* EEPROM country regions 0 - 7 */ ++ { 1, 11 }, { 1, 13 }, { 10, 2 }, { 10, 4 }, ++ { 14, 1 }, { 1, 14 }, { 3, 7 }, { 5, 9 }, ++ /* EEPROM country regions 32 - 33 */ ++ { 1, 11 }, { 1, 14 } ++ }; ++ u8 val = eeprom[MT_EE_COUNTRY_REGION]; ++ int idx = -1; ++ ++ if (val < 8) ++ idx = val; ++ if (val > 31 && val < 33) ++ idx = val - 32 + 8; ++ ++ if (idx != -1) ++ dev_info(dev->dev, ++ "EEPROM country region %02hhx (channels %hhd-%hhd)\n", ++ val, chan_bounds[idx].start, ++ chan_bounds[idx].start + chan_bounds[idx].num - 1); ++ else ++ idx = 5; /* channels 1 - 14 */ ++ ++ dev->ee->reg = chan_bounds[idx]; ++ ++ /* TODO: country region 33 is special - phy should be set to B-mode ++ * before entering channel 14 (see sta/connect.c) ++ */ ++} ++ ++static void ++mt7601u_set_rf_freq_off(struct mt7601u_dev *dev, u8 *eeprom) ++{ ++ u8 comp; ++ ++ dev->ee->rf_freq_off = field_validate(eeprom[MT_EE_FREQ_OFFSET]); ++ comp = field_validate(eeprom[MT_EE_FREQ_OFFSET_COMPENSATION]); ++ ++ if (comp & BIT(7)) ++ dev->ee->rf_freq_off -= comp & 0x7f; ++ else ++ dev->ee->rf_freq_off += comp; ++} ++ ++static void ++mt7601u_set_rssi_offset(struct mt7601u_dev *dev, u8 *eeprom) ++{ ++ int i; ++ s8 *rssi_offset = dev->ee->rssi_offset; ++ ++ for (i = 0; i < 2; i++) { ++ rssi_offset[i] = eeprom[MT_EE_RSSI_OFFSET + i]; ++ ++ if (rssi_offset[i] < -10 || rssi_offset[i] > 10) { ++ dev_warn(dev->dev, ++ "Warning: EEPROM RSSI is invalid %02hhx\n", ++ rssi_offset[i]); ++ rssi_offset[i] = 0; ++ } ++ } ++} ++ ++static void ++mt7601u_extra_power_over_mac(struct mt7601u_dev *dev) ++{ ++ u32 val; ++ ++ val = ((mt7601u_rr(dev, MT_TX_PWR_CFG_1) & 0x0000ff00) >> 8); ++ val |= ((mt7601u_rr(dev, MT_TX_PWR_CFG_2) & 0x0000ff00) << 8); ++ mt7601u_wr(dev, MT_TX_PWR_CFG_7, val); ++ ++ val = ((mt7601u_rr(dev, MT_TX_PWR_CFG_4) & 0x0000ff00) >> 8); ++ mt7601u_wr(dev, MT_TX_PWR_CFG_9, val); ++} ++ ++static void ++mt7601u_set_power_rate(struct power_per_rate *rate, s8 delta, u8 value) ++{ ++ /* Invalid? Note: vendor driver does not handle this */ ++ if (value == 0xff) ++ return; ++ ++ rate->raw = s6_validate(value); ++ rate->bw20 = s6_to_int(value); ++ /* Note: vendor driver does cap the value to s6 right away */ ++ rate->bw40 = rate->bw20 + delta; ++} ++ ++static void ++mt7601u_save_power_rate(struct mt7601u_dev *dev, s8 delta, u32 val, int i) ++{ ++ struct mt7601u_rate_power *t = &dev->ee->power_rate_table; ++ ++ switch (i) { ++ case 0: ++ mt7601u_set_power_rate(&t->cck[0], delta, (val >> 0) & 0xff); ++ mt7601u_set_power_rate(&t->cck[1], delta, (val >> 8) & 0xff); ++ /* Save cck bw20 for fixups of channel 14 */ ++ dev->ee->real_cck_bw20[0] = t->cck[0].bw20; ++ dev->ee->real_cck_bw20[1] = t->cck[1].bw20; ++ ++ mt7601u_set_power_rate(&t->ofdm[0], delta, (val >> 16) & 0xff); ++ mt7601u_set_power_rate(&t->ofdm[1], delta, (val >> 24) & 0xff); ++ break; ++ case 1: ++ mt7601u_set_power_rate(&t->ofdm[2], delta, (val >> 0) & 0xff); ++ mt7601u_set_power_rate(&t->ofdm[3], delta, (val >> 8) & 0xff); ++ mt7601u_set_power_rate(&t->ht[0], delta, (val >> 16) & 0xff); ++ mt7601u_set_power_rate(&t->ht[1], delta, (val >> 24) & 0xff); ++ break; ++ case 2: ++ mt7601u_set_power_rate(&t->ht[2], delta, (val >> 0) & 0xff); ++ mt7601u_set_power_rate(&t->ht[3], delta, (val >> 8) & 0xff); ++ break; ++ } ++} ++ ++static s8 ++get_delta(u8 val) ++{ ++ s8 ret; ++ ++ if (!field_valid(val) || !(val & BIT(7))) ++ return 0; ++ ++ ret = val & 0x1f; ++ if (ret > 8) ++ ret = 8; ++ if (val & BIT(6)) ++ ret = -ret; ++ ++ return ret; ++} ++ ++static void ++mt7601u_config_tx_power_per_rate(struct mt7601u_dev *dev, u8 *eeprom) ++{ ++ u32 val; ++ s8 bw40_delta; ++ int i; ++ ++ bw40_delta = get_delta(eeprom[MT_EE_TX_POWER_DELTA_BW40]); ++ ++ for (i = 0; i < 5; i++) { ++ val = get_unaligned_le32(eeprom + MT_EE_TX_POWER_BYRATE(i)); ++ ++ mt7601u_save_power_rate(dev, bw40_delta, val, i); ++ ++ if (~val) ++ mt7601u_wr(dev, MT_TX_PWR_CFG_0 + i * 4, val); ++ } ++ ++ mt7601u_extra_power_over_mac(dev); ++} ++ ++static void ++mt7601u_init_tssi_params(struct mt7601u_dev *dev, u8 *eeprom) ++{ ++ struct tssi_data *d = &dev->ee->tssi_data; ++ ++ if (!dev->ee->tssi_enabled) ++ return; ++ ++ d->slope = eeprom[MT_EE_TX_TSSI_SLOPE]; ++ d->tx0_delta_offset = eeprom[MT_EE_TX_TSSI_OFFSET] * 1024; ++ d->offset[0] = eeprom[MT_EE_TX_TSSI_OFFSET_GROUP]; ++ d->offset[1] = eeprom[MT_EE_TX_TSSI_OFFSET_GROUP + 1]; ++ d->offset[2] = eeprom[MT_EE_TX_TSSI_OFFSET_GROUP + 2]; ++} ++ ++int ++mt7601u_eeprom_init(struct mt7601u_dev *dev) ++{ ++ u8 *eeprom; ++ int i, ret; ++ ++ ret = mt7601u_efuse_physical_size_check(dev); ++ if (ret) ++ return ret; ++ ++ dev->ee = devm_kzalloc(dev->dev, sizeof(*dev->ee), GFP_KERNEL); ++ if (!dev->ee) ++ return -ENOMEM; ++ ++ eeprom = kmalloc(MT7601U_EEPROM_SIZE, GFP_KERNEL); ++ if (!eeprom) ++ return -ENOMEM; ++ ++ for (i = 0; i + 16 <= MT7601U_EEPROM_SIZE; i += 16) { ++ ret = mt7601u_efuse_read(dev, i, eeprom + i, MT_EE_READ); ++ if (ret) ++ goto out; ++ } ++ ++ if (eeprom[MT_EE_VERSION_EE] > MT7601U_EE_MAX_VER) ++ dev_warn(dev->dev, ++ "Warning: unsupported EEPROM version %02hhx\n", ++ eeprom[MT_EE_VERSION_EE]); ++ dev_info(dev->dev, "EEPROM ver:%02hhx fae:%02hhx\n", ++ eeprom[MT_EE_VERSION_EE], eeprom[MT_EE_VERSION_FAE]); ++ ++ mt7601u_set_macaddr(dev, eeprom); ++ mt7601u_set_chip_cap(dev, eeprom); ++ mt7601u_set_channel_power(dev, eeprom); ++ mt7601u_set_country_reg(dev, eeprom); ++ mt7601u_set_rf_freq_off(dev, eeprom); ++ mt7601u_set_rssi_offset(dev, eeprom); ++ dev->ee->ref_temp = eeprom[MT_EE_REF_TEMP]; ++ dev->ee->lna_gain = eeprom[MT_EE_LNA_GAIN]; ++ ++ mt7601u_config_tx_power_per_rate(dev, eeprom); ++ ++ mt7601u_init_tssi_params(dev, eeprom); ++out: ++ kfree(eeprom); ++ return ret; ++} +diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/eeprom.h linux-rpi/drivers/net/wireless/mediatek/mt7601u/eeprom.h +--- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/eeprom.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/eeprom.h 2015-11-29 09:42:38.887167260 +0100 +@@ -0,0 +1,151 @@ ++/* ++ * Copyright (C) 2014 Felix Fietkau ++ * Copyright (C) 2015 Jakub Kicinski ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 ++ * as published by the Free Software Foundation ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef __MT7601U_EEPROM_H ++#define __MT7601U_EEPROM_H ++ ++struct mt7601u_dev; ++ ++#define MT7601U_EE_MAX_VER 0x0c ++#define MT7601U_EEPROM_SIZE 256 ++ ++#define MT7601U_DEFAULT_TX_POWER 6 ++ ++enum mt76_eeprom_field { ++ MT_EE_CHIP_ID = 0x00, ++ MT_EE_VERSION_FAE = 0x02, ++ MT_EE_VERSION_EE = 0x03, ++ MT_EE_MAC_ADDR = 0x04, ++ MT_EE_NIC_CONF_0 = 0x34, ++ MT_EE_NIC_CONF_1 = 0x36, ++ MT_EE_COUNTRY_REGION = 0x39, ++ MT_EE_FREQ_OFFSET = 0x3a, ++ MT_EE_NIC_CONF_2 = 0x42, ++ ++ MT_EE_LNA_GAIN = 0x44, ++ MT_EE_RSSI_OFFSET = 0x46, ++ ++ MT_EE_TX_POWER_DELTA_BW40 = 0x50, ++ MT_EE_TX_POWER_OFFSET = 0x52, ++ ++ MT_EE_TX_TSSI_SLOPE = 0x6e, ++ MT_EE_TX_TSSI_OFFSET_GROUP = 0x6f, ++ MT_EE_TX_TSSI_OFFSET = 0x76, ++ ++ MT_EE_TX_TSSI_TARGET_POWER = 0xd0, ++ MT_EE_REF_TEMP = 0xd1, ++ MT_EE_FREQ_OFFSET_COMPENSATION = 0xdb, ++ MT_EE_TX_POWER_BYRATE_BASE = 0xde, ++ ++ MT_EE_USAGE_MAP_START = 0x1e0, ++ MT_EE_USAGE_MAP_END = 0x1fc, ++}; ++ ++#define MT_EE_NIC_CONF_0_RX_PATH GENMASK(3, 0) ++#define MT_EE_NIC_CONF_0_TX_PATH GENMASK(7, 4) ++#define MT_EE_NIC_CONF_0_BOARD_TYPE GENMASK(13, 12) ++ ++#define MT_EE_NIC_CONF_1_HW_RF_CTRL BIT(0) ++#define MT_EE_NIC_CONF_1_TEMP_TX_ALC BIT(1) ++#define MT_EE_NIC_CONF_1_LNA_EXT_2G BIT(2) ++#define MT_EE_NIC_CONF_1_LNA_EXT_5G BIT(3) ++#define MT_EE_NIC_CONF_1_TX_ALC_EN BIT(13) ++ ++#define MT_EE_NIC_CONF_2_RX_STREAM GENMASK(3, 0) ++#define MT_EE_NIC_CONF_2_TX_STREAM GENMASK(7, 4) ++#define MT_EE_NIC_CONF_2_HW_ANTDIV BIT(8) ++#define MT_EE_NIC_CONF_2_XTAL_OPTION GENMASK(10, 9) ++#define MT_EE_NIC_CONF_2_TEMP_DISABLE BIT(11) ++#define MT_EE_NIC_CONF_2_COEX_METHOD GENMASK(15, 13) ++ ++#define MT_EE_TX_POWER_BYRATE(i) (MT_EE_TX_POWER_BYRATE_BASE + \ ++ (i) * 4) ++ ++#define MT_EFUSE_USAGE_MAP_SIZE (MT_EE_USAGE_MAP_END - \ ++ MT_EE_USAGE_MAP_START + 1) ++ ++enum mt7601u_eeprom_access_modes { ++ MT_EE_READ = 0, ++ MT_EE_PHYSICAL_READ = 1, ++}; ++ ++struct power_per_rate { ++ u8 raw; /* validated s6 value */ ++ s8 bw20; /* sign-extended int */ ++ s8 bw40; /* sign-extended int */ ++}; ++ ++/* Power per rate - one value per two rates */ ++struct mt7601u_rate_power { ++ struct power_per_rate cck[2]; ++ struct power_per_rate ofdm[4]; ++ struct power_per_rate ht[4]; ++}; ++ ++struct reg_channel_bounds { ++ u8 start; ++ u8 num; ++}; ++ ++struct mt7601u_eeprom_params { ++ bool tssi_enabled; ++ u8 rf_freq_off; ++ s8 rssi_offset[2]; ++ s8 ref_temp; ++ s8 lna_gain; ++ ++ u8 chan_pwr[14]; ++ struct mt7601u_rate_power power_rate_table; ++ s8 real_cck_bw20[2]; ++ ++ /* TSSI stuff - only with internal TX ALC */ ++ struct tssi_data { ++ int tx0_delta_offset; ++ u8 slope; ++ u8 offset[3]; ++ } tssi_data; ++ ++ struct reg_channel_bounds reg; ++}; ++ ++int mt7601u_eeprom_init(struct mt7601u_dev *dev); ++ ++static inline u32 s6_validate(u32 reg) ++{ ++ WARN_ON(reg & ~GENMASK(5, 0)); ++ return reg & GENMASK(5, 0); ++} ++ ++static inline int s6_to_int(u32 reg) ++{ ++ int s6; ++ ++ s6 = s6_validate(reg); ++ if (s6 & BIT(5)) ++ s6 -= BIT(6); ++ ++ return s6; ++} ++ ++static inline u32 int_to_s6(int val) ++{ ++ if (val < -0x20) ++ return 0x20; ++ if (val > 0x1f) ++ return 0x1f; ++ ++ return val & 0x3f; ++} ++ ++#endif +diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/init.c linux-rpi/drivers/net/wireless/mediatek/mt7601u/init.c +--- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/init.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/init.c 2015-11-29 09:42:38.887167260 +0100 +@@ -0,0 +1,630 @@ ++/* ++ * (c) Copyright 2002-2010, Ralink Technology, Inc. ++ * Copyright (C) 2014 Felix Fietkau ++ * Copyright (C) 2015 Jakub Kicinski ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 ++ * as published by the Free Software Foundation ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include "mt7601u.h" ++#include "eeprom.h" ++#include "trace.h" ++#include "mcu.h" ++ ++#include "initvals.h" ++ ++static void ++mt7601u_set_wlan_state(struct mt7601u_dev *dev, u32 val, bool enable) ++{ ++ int i; ++ ++ /* Note: we don't turn off WLAN_CLK because that makes the device ++ * not respond properly on the probe path. ++ * In case anyone (PSM?) wants to use this function we can ++ * bring the clock stuff back and fixup the probe path. ++ */ ++ ++ if (enable) ++ val |= (MT_WLAN_FUN_CTRL_WLAN_EN | ++ MT_WLAN_FUN_CTRL_WLAN_CLK_EN); ++ else ++ val &= ~(MT_WLAN_FUN_CTRL_WLAN_EN); ++ ++ mt7601u_wr(dev, MT_WLAN_FUN_CTRL, val); ++ udelay(20); ++ ++ if (enable) { ++ set_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state); ++ } else { ++ clear_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state); ++ return; ++ } ++ ++ for (i = 200; i; i--) { ++ val = mt7601u_rr(dev, MT_CMB_CTRL); ++ ++ if (val & MT_CMB_CTRL_XTAL_RDY && val & MT_CMB_CTRL_PLL_LD) ++ break; ++ ++ udelay(20); ++ } ++ ++ /* Note: vendor driver tries to disable/enable wlan here and retry ++ * but the code which does it is so buggy it must have never ++ * triggered, so don't bother. ++ */ ++ if (!i) ++ dev_err(dev->dev, "Error: PLL and XTAL check failed!\n"); ++} ++ ++static void mt7601u_chip_onoff(struct mt7601u_dev *dev, bool enable, bool reset) ++{ ++ u32 val; ++ ++ mutex_lock(&dev->hw_atomic_mutex); ++ ++ val = mt7601u_rr(dev, MT_WLAN_FUN_CTRL); ++ ++ if (reset) { ++ val |= MT_WLAN_FUN_CTRL_GPIO_OUT_EN; ++ val &= ~MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL; ++ ++ if (val & MT_WLAN_FUN_CTRL_WLAN_EN) { ++ val |= (MT_WLAN_FUN_CTRL_WLAN_RESET | ++ MT_WLAN_FUN_CTRL_WLAN_RESET_RF); ++ mt7601u_wr(dev, MT_WLAN_FUN_CTRL, val); ++ udelay(20); ++ ++ val &= ~(MT_WLAN_FUN_CTRL_WLAN_RESET | ++ MT_WLAN_FUN_CTRL_WLAN_RESET_RF); ++ } ++ } ++ ++ mt7601u_wr(dev, MT_WLAN_FUN_CTRL, val); ++ udelay(20); ++ ++ mt7601u_set_wlan_state(dev, val, enable); ++ ++ mutex_unlock(&dev->hw_atomic_mutex); ++} ++ ++static void mt7601u_reset_csr_bbp(struct mt7601u_dev *dev) ++{ ++ mt7601u_wr(dev, MT_MAC_SYS_CTRL, (MT_MAC_SYS_CTRL_RESET_CSR | ++ MT_MAC_SYS_CTRL_RESET_BBP)); ++ mt7601u_wr(dev, MT_USB_DMA_CFG, 0); ++ msleep(1); ++ mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0); ++} ++ ++static void mt7601u_init_usb_dma(struct mt7601u_dev *dev) ++{ ++ u32 val; ++ ++ val = MT76_SET(MT_USB_DMA_CFG_RX_BULK_AGG_TOUT, MT_USB_AGGR_TIMEOUT) | ++ MT76_SET(MT_USB_DMA_CFG_RX_BULK_AGG_LMT, MT_USB_AGGR_SIZE_LIMIT) | ++ MT_USB_DMA_CFG_RX_BULK_EN | ++ MT_USB_DMA_CFG_TX_BULK_EN; ++ if (dev->in_max_packet == 512) ++ val |= MT_USB_DMA_CFG_RX_BULK_AGG_EN; ++ mt7601u_wr(dev, MT_USB_DMA_CFG, val); ++ ++ val |= MT_USB_DMA_CFG_UDMA_RX_WL_DROP; ++ mt7601u_wr(dev, MT_USB_DMA_CFG, val); ++ val &= ~MT_USB_DMA_CFG_UDMA_RX_WL_DROP; ++ mt7601u_wr(dev, MT_USB_DMA_CFG, val); ++} ++ ++static int mt7601u_init_bbp(struct mt7601u_dev *dev) ++{ ++ int ret; ++ ++ ret = mt7601u_wait_bbp_ready(dev); ++ if (ret) ++ return ret; ++ ++ ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, bbp_common_vals, ++ ARRAY_SIZE(bbp_common_vals)); ++ if (ret) ++ return ret; ++ ++ return mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, bbp_chip_vals, ++ ARRAY_SIZE(bbp_chip_vals)); ++} ++ ++static void ++mt76_init_beacon_offsets(struct mt7601u_dev *dev) ++{ ++ u16 base = MT_BEACON_BASE; ++ u32 regs[4] = {}; ++ int i; ++ ++ for (i = 0; i < 16; i++) { ++ u16 addr = dev->beacon_offsets[i]; ++ ++ regs[i / 4] |= ((addr - base) / 64) << (8 * (i % 4)); ++ } ++ ++ for (i = 0; i < 4; i++) ++ mt7601u_wr(dev, MT_BCN_OFFSET(i), regs[i]); ++} ++ ++static int mt7601u_write_mac_initvals(struct mt7601u_dev *dev) ++{ ++ int ret; ++ ++ ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_WLAN, mac_common_vals, ++ ARRAY_SIZE(mac_common_vals)); ++ if (ret) ++ return ret; ++ ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_WLAN, ++ mac_chip_vals, ARRAY_SIZE(mac_chip_vals)); ++ if (ret) ++ return ret; ++ ++ mt76_init_beacon_offsets(dev); ++ ++ mt7601u_wr(dev, MT_AUX_CLK_CFG, 0); ++ ++ return 0; ++} ++ ++static int mt7601u_init_wcid_mem(struct mt7601u_dev *dev) ++{ ++ u32 *vals; ++ int i, ret; ++ ++ vals = kmalloc(sizeof(*vals) * N_WCIDS * 2, GFP_KERNEL); ++ if (!vals) ++ return -ENOMEM; ++ ++ for (i = 0; i < N_WCIDS; i++) { ++ vals[i * 2] = 0xffffffff; ++ vals[i * 2 + 1] = 0x00ffffff; ++ } ++ ++ ret = mt7601u_burst_write_regs(dev, MT_WCID_ADDR_BASE, ++ vals, N_WCIDS * 2); ++ kfree(vals); ++ ++ return ret; ++} ++ ++static int mt7601u_init_key_mem(struct mt7601u_dev *dev) ++{ ++ u32 vals[4] = {}; ++ ++ return mt7601u_burst_write_regs(dev, MT_SKEY_MODE_BASE_0, ++ vals, ARRAY_SIZE(vals)); ++} ++ ++static int mt7601u_init_wcid_attr_mem(struct mt7601u_dev *dev) ++{ ++ u32 *vals; ++ int i, ret; ++ ++ vals = kmalloc(sizeof(*vals) * N_WCIDS * 2, GFP_KERNEL); ++ if (!vals) ++ return -ENOMEM; ++ ++ for (i = 0; i < N_WCIDS * 2; i++) ++ vals[i] = 1; ++ ++ ret = mt7601u_burst_write_regs(dev, MT_WCID_ATTR_BASE, ++ vals, N_WCIDS * 2); ++ kfree(vals); ++ ++ return ret; ++} ++ ++static void mt7601u_reset_counters(struct mt7601u_dev *dev) ++{ ++ mt7601u_rr(dev, MT_RX_STA_CNT0); ++ mt7601u_rr(dev, MT_RX_STA_CNT1); ++ mt7601u_rr(dev, MT_RX_STA_CNT2); ++ mt7601u_rr(dev, MT_TX_STA_CNT0); ++ mt7601u_rr(dev, MT_TX_STA_CNT1); ++ mt7601u_rr(dev, MT_TX_STA_CNT2); ++} ++ ++int mt7601u_mac_start(struct mt7601u_dev *dev) ++{ ++ mt7601u_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX); ++ ++ if (!mt76_poll(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_DMA_BUSY | ++ MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 200000)) ++ return -ETIMEDOUT; ++ ++ dev->rxfilter = MT_RX_FILTR_CFG_CRC_ERR | ++ MT_RX_FILTR_CFG_PHY_ERR | MT_RX_FILTR_CFG_PROMISC | ++ MT_RX_FILTR_CFG_VER_ERR | MT_RX_FILTR_CFG_DUP | ++ MT_RX_FILTR_CFG_CFACK | MT_RX_FILTR_CFG_CFEND | ++ MT_RX_FILTR_CFG_ACK | MT_RX_FILTR_CFG_CTS | ++ MT_RX_FILTR_CFG_RTS | MT_RX_FILTR_CFG_PSPOLL | ++ MT_RX_FILTR_CFG_BA | MT_RX_FILTR_CFG_CTRL_RSV; ++ mt7601u_wr(dev, MT_RX_FILTR_CFG, dev->rxfilter); ++ ++ mt7601u_wr(dev, MT_MAC_SYS_CTRL, ++ MT_MAC_SYS_CTRL_ENABLE_TX | MT_MAC_SYS_CTRL_ENABLE_RX); ++ ++ if (!mt76_poll(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_DMA_BUSY | ++ MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 50)) ++ return -ETIMEDOUT; ++ ++ return 0; ++} ++ ++static void mt7601u_mac_stop_hw(struct mt7601u_dev *dev) ++{ ++ int i, ok; ++ ++ if (test_bit(MT7601U_STATE_REMOVED, &dev->state)) ++ return; ++ ++ mt76_clear(dev, MT_BEACON_TIME_CFG, MT_BEACON_TIME_CFG_TIMER_EN | ++ MT_BEACON_TIME_CFG_SYNC_MODE | MT_BEACON_TIME_CFG_TBTT_EN | ++ MT_BEACON_TIME_CFG_BEACON_TX); ++ ++ if (!mt76_poll(dev, MT_USB_DMA_CFG, MT_USB_DMA_CFG_TX_BUSY, 0, 1000)) ++ dev_warn(dev->dev, "Warning: TX DMA did not stop!\n"); ++ ++ /* Page count on TxQ */ ++ i = 200; ++ while (i-- && ((mt76_rr(dev, 0x0438) & 0xffffffff) || ++ (mt76_rr(dev, 0x0a30) & 0x000000ff) || ++ (mt76_rr(dev, 0x0a34) & 0x00ff00ff))) ++ msleep(10); ++ ++ if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_TX, 0, 1000)) ++ dev_warn(dev->dev, "Warning: MAC TX did not stop!\n"); ++ ++ mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX | ++ MT_MAC_SYS_CTRL_ENABLE_TX); ++ ++ /* Page count on RxQ */ ++ ok = 0; ++ i = 200; ++ while (i--) { ++ if ((mt76_rr(dev, 0x0430) & 0x00ff0000) || ++ (mt76_rr(dev, 0x0a30) & 0xffffffff) || ++ (mt76_rr(dev, 0x0a34) & 0xffffffff)) ++ ok++; ++ if (ok > 6) ++ break; ++ ++ msleep(1); ++ } ++ ++ if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_RX, 0, 1000)) ++ dev_warn(dev->dev, "Warning: MAC RX did not stop!\n"); ++ ++ if (!mt76_poll(dev, MT_USB_DMA_CFG, MT_USB_DMA_CFG_RX_BUSY, 0, 1000)) ++ dev_warn(dev->dev, "Warning: RX DMA did not stop!\n"); ++} ++ ++void mt7601u_mac_stop(struct mt7601u_dev *dev) ++{ ++ mt7601u_mac_stop_hw(dev); ++ flush_delayed_work(&dev->stat_work); ++ cancel_delayed_work_sync(&dev->stat_work); ++} ++ ++static void mt7601u_stop_hardware(struct mt7601u_dev *dev) ++{ ++ mt7601u_chip_onoff(dev, false, false); ++} ++ ++int mt7601u_init_hardware(struct mt7601u_dev *dev) ++{ ++ static const u16 beacon_offsets[16] = { ++ /* 512 byte per beacon */ ++ 0xc000, 0xc200, 0xc400, 0xc600, ++ 0xc800, 0xca00, 0xcc00, 0xce00, ++ 0xd000, 0xd200, 0xd400, 0xd600, ++ 0xd800, 0xda00, 0xdc00, 0xde00 ++ }; ++ int ret; ++ ++ dev->beacon_offsets = beacon_offsets; ++ ++ mt7601u_chip_onoff(dev, true, false); ++ ++ ret = mt7601u_wait_asic_ready(dev); ++ if (ret) ++ goto err; ++ ret = mt7601u_mcu_init(dev); ++ if (ret) ++ goto err; ++ ++ if (!mt76_poll_msec(dev, MT_WPDMA_GLO_CFG, ++ MT_WPDMA_GLO_CFG_TX_DMA_BUSY | ++ MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 100)) { ++ ret = -EIO; ++ goto err; ++ } ++ ++ /* Wait for ASIC ready after FW load. */ ++ ret = mt7601u_wait_asic_ready(dev); ++ if (ret) ++ goto err; ++ ++ mt7601u_reset_csr_bbp(dev); ++ mt7601u_init_usb_dma(dev); ++ ++ ret = mt7601u_mcu_cmd_init(dev); ++ if (ret) ++ goto err; ++ ret = mt7601u_dma_init(dev); ++ if (ret) ++ goto err_mcu; ++ ret = mt7601u_write_mac_initvals(dev); ++ if (ret) ++ goto err_rx; ++ ++ if (!mt76_poll_msec(dev, MT_MAC_STATUS, ++ MT_MAC_STATUS_TX | MT_MAC_STATUS_RX, 0, 100)) { ++ ret = -EIO; ++ goto err_rx; ++ } ++ ++ ret = mt7601u_init_bbp(dev); ++ if (ret) ++ goto err_rx; ++ ret = mt7601u_init_wcid_mem(dev); ++ if (ret) ++ goto err_rx; ++ ret = mt7601u_init_key_mem(dev); ++ if (ret) ++ goto err_rx; ++ ret = mt7601u_init_wcid_attr_mem(dev); ++ if (ret) ++ goto err_rx; ++ ++ mt76_clear(dev, MT_BEACON_TIME_CFG, (MT_BEACON_TIME_CFG_TIMER_EN | ++ MT_BEACON_TIME_CFG_SYNC_MODE | ++ MT_BEACON_TIME_CFG_TBTT_EN | ++ MT_BEACON_TIME_CFG_BEACON_TX)); ++ ++ mt7601u_reset_counters(dev); ++ ++ mt7601u_rmw(dev, MT_US_CYC_CFG, MT_US_CYC_CNT, 0x1e); ++ ++ mt7601u_wr(dev, MT_TXOP_CTRL_CFG, MT76_SET(MT_TXOP_TRUN_EN, 0x3f) | ++ MT76_SET(MT_TXOP_EXT_CCA_DLY, 0x58)); ++ ++ ret = mt7601u_eeprom_init(dev); ++ if (ret) ++ goto err_rx; ++ ++ ret = mt7601u_phy_init(dev); ++ if (ret) ++ goto err_rx; ++ ++ mt7601u_set_rx_path(dev, 0); ++ mt7601u_set_tx_dac(dev, 0); ++ ++ mt7601u_mac_set_ctrlch(dev, false); ++ mt7601u_bbp_set_ctrlch(dev, false); ++ mt7601u_bbp_set_bw(dev, MT_BW_20); ++ ++ return 0; ++ ++err_rx: ++ mt7601u_dma_cleanup(dev); ++err_mcu: ++ mt7601u_mcu_cmd_deinit(dev); ++err: ++ mt7601u_chip_onoff(dev, false, false); ++ return ret; ++} ++ ++void mt7601u_cleanup(struct mt7601u_dev *dev) ++{ ++ if (!test_and_clear_bit(MT7601U_STATE_INITIALIZED, &dev->state)) ++ return; ++ ++ mt7601u_stop_hardware(dev); ++ mt7601u_dma_cleanup(dev); ++ mt7601u_mcu_cmd_deinit(dev); ++} ++ ++struct mt7601u_dev *mt7601u_alloc_device(struct device *pdev) ++{ ++ struct ieee80211_hw *hw; ++ struct mt7601u_dev *dev; ++ ++ hw = ieee80211_alloc_hw(sizeof(*dev), &mt7601u_ops); ++ if (!hw) ++ return NULL; ++ ++ dev = hw->priv; ++ dev->dev = pdev; ++ dev->hw = hw; ++ mutex_init(&dev->vendor_req_mutex); ++ mutex_init(&dev->reg_atomic_mutex); ++ mutex_init(&dev->hw_atomic_mutex); ++ mutex_init(&dev->mutex); ++ spin_lock_init(&dev->tx_lock); ++ spin_lock_init(&dev->rx_lock); ++ spin_lock_init(&dev->lock); ++ spin_lock_init(&dev->mac_lock); ++ spin_lock_init(&dev->con_mon_lock); ++ atomic_set(&dev->avg_ampdu_len, 1); ++ skb_queue_head_init(&dev->tx_skb_done); ++ ++ dev->stat_wq = alloc_workqueue("mt7601u", WQ_UNBOUND, 0); ++ if (!dev->stat_wq) { ++ ieee80211_free_hw(hw); ++ return NULL; ++ } ++ ++ return dev; ++} ++ ++#define CHAN2G(_idx, _freq) { \ ++ .band = IEEE80211_BAND_2GHZ, \ ++ .center_freq = (_freq), \ ++ .hw_value = (_idx), \ ++ .max_power = 30, \ ++} ++ ++static const struct ieee80211_channel mt76_channels_2ghz[] = { ++ CHAN2G(1, 2412), ++ CHAN2G(2, 2417), ++ CHAN2G(3, 2422), ++ CHAN2G(4, 2427), ++ CHAN2G(5, 2432), ++ CHAN2G(6, 2437), ++ CHAN2G(7, 2442), ++ CHAN2G(8, 2447), ++ CHAN2G(9, 2452), ++ CHAN2G(10, 2457), ++ CHAN2G(11, 2462), ++ CHAN2G(12, 2467), ++ CHAN2G(13, 2472), ++ CHAN2G(14, 2484), ++}; ++ ++#define CCK_RATE(_idx, _rate) { \ ++ .bitrate = _rate, \ ++ .flags = IEEE80211_RATE_SHORT_PREAMBLE, \ ++ .hw_value = (MT_PHY_TYPE_CCK << 8) | _idx, \ ++ .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (8 + _idx), \ ++} ++ ++#define OFDM_RATE(_idx, _rate) { \ ++ .bitrate = _rate, \ ++ .hw_value = (MT_PHY_TYPE_OFDM << 8) | _idx, \ ++ .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | _idx, \ ++} ++ ++static struct ieee80211_rate mt76_rates[] = { ++ CCK_RATE(0, 10), ++ CCK_RATE(1, 20), ++ CCK_RATE(2, 55), ++ CCK_RATE(3, 110), ++ OFDM_RATE(0, 60), ++ OFDM_RATE(1, 90), ++ OFDM_RATE(2, 120), ++ OFDM_RATE(3, 180), ++ OFDM_RATE(4, 240), ++ OFDM_RATE(5, 360), ++ OFDM_RATE(6, 480), ++ OFDM_RATE(7, 540), ++}; ++ ++static int ++mt76_init_sband(struct mt7601u_dev *dev, struct ieee80211_supported_band *sband, ++ const struct ieee80211_channel *chan, int n_chan, ++ struct ieee80211_rate *rates, int n_rates) ++{ ++ struct ieee80211_sta_ht_cap *ht_cap; ++ void *chanlist; ++ int size; ++ ++ size = n_chan * sizeof(*chan); ++ chanlist = devm_kmemdup(dev->dev, chan, size, GFP_KERNEL); ++ if (!chanlist) ++ return -ENOMEM; ++ ++ sband->channels = chanlist; ++ sband->n_channels = n_chan; ++ sband->bitrates = rates; ++ sband->n_bitrates = n_rates; ++ ++ ht_cap = &sband->ht_cap; ++ ht_cap->ht_supported = true; ++ ht_cap->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | ++ IEEE80211_HT_CAP_GRN_FLD | ++ IEEE80211_HT_CAP_SGI_20 | ++ IEEE80211_HT_CAP_SGI_40 | ++ (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); ++ ++ ht_cap->mcs.rx_mask[0] = 0xff; ++ ht_cap->mcs.rx_mask[4] = 0x1; ++ ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; ++ ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; ++ ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_2; ++ ++ dev->chandef.chan = &sband->channels[0]; ++ ++ return 0; ++} ++ ++static int ++mt76_init_sband_2g(struct mt7601u_dev *dev) ++{ ++ dev->sband_2g = devm_kzalloc(dev->dev, sizeof(*dev->sband_2g), ++ GFP_KERNEL); ++ dev->hw->wiphy->bands[IEEE80211_BAND_2GHZ] = dev->sband_2g; ++ ++ WARN_ON(dev->ee->reg.start - 1 + dev->ee->reg.num > ++ ARRAY_SIZE(mt76_channels_2ghz)); ++ ++ return mt76_init_sband(dev, dev->sband_2g, ++ &mt76_channels_2ghz[dev->ee->reg.start - 1], ++ dev->ee->reg.num, ++ mt76_rates, ARRAY_SIZE(mt76_rates)); ++} ++ ++int mt7601u_register_device(struct mt7601u_dev *dev) ++{ ++ struct ieee80211_hw *hw = dev->hw; ++ struct wiphy *wiphy = hw->wiphy; ++ int ret; ++ ++ /* Reserve WCID 0 for mcast - thanks to this APs WCID will go to ++ * entry no. 1 like it does in the vendor driver. ++ */ ++ dev->wcid_mask[0] |= 1; ++ ++ /* init fake wcid for monitor interfaces */ ++ dev->mon_wcid = devm_kmalloc(dev->dev, sizeof(*dev->mon_wcid), ++ GFP_KERNEL); ++ if (!dev->mon_wcid) ++ return -ENOMEM; ++ dev->mon_wcid->idx = 0xff; ++ dev->mon_wcid->hw_key_idx = -1; ++ ++ SET_IEEE80211_DEV(hw, dev->dev); ++ ++ hw->queues = 4; ++ hw->flags = IEEE80211_HW_SIGNAL_DBM | ++ IEEE80211_HW_PS_NULLFUNC_STACK | ++ IEEE80211_HW_SUPPORTS_HT_CCK_RATES | ++ IEEE80211_HW_AMPDU_AGGREGATION | ++ IEEE80211_HW_SUPPORTS_RC_TABLE; ++ hw->max_rates = 1; ++ hw->max_report_rates = 7; ++ hw->max_rate_tries = 1; ++ ++ hw->sta_data_size = sizeof(struct mt76_sta); ++ hw->vif_data_size = sizeof(struct mt76_vif); ++ ++ SET_IEEE80211_PERM_ADDR(hw, dev->macaddr); ++ ++ wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR; ++ wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); ++ ++ ret = mt76_init_sband_2g(dev); ++ if (ret) ++ return ret; ++ ++ INIT_DELAYED_WORK(&dev->mac_work, mt7601u_mac_work); ++ INIT_DELAYED_WORK(&dev->stat_work, mt7601u_tx_stat); ++ ++ ret = ieee80211_register_hw(hw); ++ if (ret) ++ return ret; ++ ++ mt7601u_init_debugfs(dev); ++ ++ return 0; ++} +diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/initvals.h linux-rpi/drivers/net/wireless/mediatek/mt7601u/initvals.h +--- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/initvals.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/initvals.h 2015-11-29 09:42:38.887167260 +0100 +@@ -0,0 +1,164 @@ ++/* ++ * (c) Copyright 2002-2010, Ralink Technology, Inc. ++ * Copyright (C) 2015 Jakub Kicinski ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 ++ * as published by the Free Software Foundation ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef __MT7601U_INITVALS_H ++#define __MT7601U_INITVALS_H ++ ++static const struct mt76_reg_pair bbp_common_vals[] = { ++ { 65, 0x2c }, ++ { 66, 0x38 }, ++ { 68, 0x0b }, ++ { 69, 0x12 }, ++ { 70, 0x0a }, ++ { 73, 0x10 }, ++ { 81, 0x37 }, ++ { 82, 0x62 }, ++ { 83, 0x6a }, ++ { 84, 0x99 }, ++ { 86, 0x00 }, ++ { 91, 0x04 }, ++ { 92, 0x00 }, ++ { 103, 0x00 }, ++ { 105, 0x05 }, ++ { 106, 0x35 }, ++}; ++ ++static const struct mt76_reg_pair bbp_chip_vals[] = { ++ { 1, 0x04 }, { 4, 0x40 }, { 20, 0x06 }, { 31, 0x08 }, ++ /* CCK Tx Control */ ++ { 178, 0xff }, ++ /* AGC/Sync controls */ ++ { 66, 0x14 }, { 68, 0x8b }, { 69, 0x12 }, { 70, 0x09 }, ++ { 73, 0x11 }, { 75, 0x60 }, { 76, 0x44 }, { 84, 0x9a }, ++ { 86, 0x38 }, { 91, 0x07 }, { 92, 0x02 }, ++ /* Rx Path Controls */ ++ { 99, 0x50 }, { 101, 0x00 }, { 103, 0xc0 }, { 104, 0x92 }, ++ { 105, 0x3c }, { 106, 0x03 }, { 128, 0x12 }, ++ /* Change RXWI content: Gain Report */ ++ { 142, 0x04 }, { 143, 0x37 }, ++ /* Change RXWI content: Antenna Report */ ++ { 142, 0x03 }, { 143, 0x99 }, ++ /* Calibration Index Register */ ++ /* CCK Receiver Control */ ++ { 160, 0xeb }, { 161, 0xc4 }, { 162, 0x77 }, { 163, 0xf9 }, ++ { 164, 0x88 }, { 165, 0x80 }, { 166, 0xff }, { 167, 0xe4 }, ++ /* Added AGC controls - these AGC/GLRT registers are accessed ++ * through R195 and R196. ++ */ ++ { 195, 0x00 }, { 196, 0x00 }, ++ { 195, 0x01 }, { 196, 0x04 }, ++ { 195, 0x02 }, { 196, 0x20 }, ++ { 195, 0x03 }, { 196, 0x0a }, ++ { 195, 0x06 }, { 196, 0x16 }, ++ { 195, 0x07 }, { 196, 0x05 }, ++ { 195, 0x08 }, { 196, 0x37 }, ++ { 195, 0x0a }, { 196, 0x15 }, ++ { 195, 0x0b }, { 196, 0x17 }, ++ { 195, 0x0c }, { 196, 0x06 }, ++ { 195, 0x0d }, { 196, 0x09 }, ++ { 195, 0x0e }, { 196, 0x05 }, ++ { 195, 0x0f }, { 196, 0x09 }, ++ { 195, 0x10 }, { 196, 0x20 }, ++ { 195, 0x20 }, { 196, 0x17 }, ++ { 195, 0x21 }, { 196, 0x06 }, ++ { 195, 0x22 }, { 196, 0x09 }, ++ { 195, 0x23 }, { 196, 0x17 }, ++ { 195, 0x24 }, { 196, 0x06 }, ++ { 195, 0x25 }, { 196, 0x09 }, ++ { 195, 0x26 }, { 196, 0x17 }, ++ { 195, 0x27 }, { 196, 0x06 }, ++ { 195, 0x28 }, { 196, 0x09 }, ++ { 195, 0x29 }, { 196, 0x05 }, ++ { 195, 0x2a }, { 196, 0x09 }, ++ { 195, 0x80 }, { 196, 0x8b }, ++ { 195, 0x81 }, { 196, 0x12 }, ++ { 195, 0x82 }, { 196, 0x09 }, ++ { 195, 0x83 }, { 196, 0x17 }, ++ { 195, 0x84 }, { 196, 0x11 }, ++ { 195, 0x85 }, { 196, 0x00 }, ++ { 195, 0x86 }, { 196, 0x00 }, ++ { 195, 0x87 }, { 196, 0x18 }, ++ { 195, 0x88 }, { 196, 0x60 }, ++ { 195, 0x89 }, { 196, 0x44 }, ++ { 195, 0x8a }, { 196, 0x8b }, ++ { 195, 0x8b }, { 196, 0x8b }, ++ { 195, 0x8c }, { 196, 0x8b }, ++ { 195, 0x8d }, { 196, 0x8b }, ++ { 195, 0x8e }, { 196, 0x09 }, ++ { 195, 0x8f }, { 196, 0x09 }, ++ { 195, 0x90 }, { 196, 0x09 }, ++ { 195, 0x91 }, { 196, 0x09 }, ++ { 195, 0x92 }, { 196, 0x11 }, ++ { 195, 0x93 }, { 196, 0x11 }, ++ { 195, 0x94 }, { 196, 0x11 }, ++ { 195, 0x95 }, { 196, 0x11 }, ++ /* PPAD */ ++ { 47, 0x80 }, { 60, 0x80 }, { 150, 0xd2 }, { 151, 0x32 }, ++ { 152, 0x23 }, { 153, 0x41 }, { 154, 0x00 }, { 155, 0x4f }, ++ { 253, 0x7e }, { 195, 0x30 }, { 196, 0x32 }, { 195, 0x31 }, ++ { 196, 0x23 }, { 195, 0x32 }, { 196, 0x45 }, { 195, 0x35 }, ++ { 196, 0x4a }, { 195, 0x36 }, { 196, 0x5a }, { 195, 0x37 }, ++ { 196, 0x5a }, ++}; ++ ++static const struct mt76_reg_pair mac_common_vals[] = { ++ { MT_LEGACY_BASIC_RATE, 0x0000013f }, ++ { MT_HT_BASIC_RATE, 0x00008003 }, ++ { MT_MAC_SYS_CTRL, 0x00000000 }, ++ { MT_RX_FILTR_CFG, 0x00017f97 }, ++ { MT_BKOFF_SLOT_CFG, 0x00000209 }, ++ { MT_TX_SW_CFG0, 0x00000000 }, ++ { MT_TX_SW_CFG1, 0x00080606 }, ++ { MT_TX_LINK_CFG, 0x00001020 }, ++ { MT_TX_TIMEOUT_CFG, 0x000a2090 }, ++ { MT_MAX_LEN_CFG, 0x00003fff }, ++ { MT_PBF_TX_MAX_PCNT, 0x1fbf1f1f }, ++ { MT_PBF_RX_MAX_PCNT, 0x0000009f }, ++ { MT_TX_RETRY_CFG, 0x47d01f0f }, ++ { MT_AUTO_RSP_CFG, 0x00000013 }, ++ { MT_CCK_PROT_CFG, 0x05740003 }, ++ { MT_OFDM_PROT_CFG, 0x05740003 }, ++ { MT_MM40_PROT_CFG, 0x03f44084 }, ++ { MT_GF20_PROT_CFG, 0x01744004 }, ++ { MT_GF40_PROT_CFG, 0x03f44084 }, ++ { MT_MM20_PROT_CFG, 0x01744004 }, ++ { MT_TXOP_CTRL_CFG, 0x0000583f }, ++ { MT_TX_RTS_CFG, 0x01092b20 }, ++ { MT_EXP_ACK_TIME, 0x002400ca }, ++ { MT_TXOP_HLDR_ET, 0x00000002 }, ++ { MT_XIFS_TIME_CFG, 0x33a41010 }, ++ { MT_PWR_PIN_CFG, 0x00000000 }, ++}; ++ ++static const struct mt76_reg_pair mac_chip_vals[] = { ++ { MT_TSO_CTRL, 0x00006050 }, ++ { MT_BCN_OFFSET(0), 0x18100800 }, ++ { MT_BCN_OFFSET(1), 0x38302820 }, ++ { MT_PBF_SYS_CTRL, 0x00080c00 }, ++ { MT_PBF_CFG, 0x7f723c1f }, ++ { MT_FCE_PSE_CTRL, 0x00000001 }, ++ { MT_PAUSE_ENABLE_CONTROL1, 0x00000000 }, ++ { MT_TX0_RF_GAIN_CORR, 0x003b0005 }, ++ { MT_TX0_RF_GAIN_ATTEN, 0x00006900 }, ++ { MT_TX0_BB_GAIN_ATTEN, 0x00000400 }, ++ { MT_TX_ALC_VGA3, 0x00060006 }, ++ { MT_TX_SW_CFG0, 0x00000402 }, ++ { MT_TX_SW_CFG1, 0x00000000 }, ++ { MT_TX_SW_CFG2, 0x00000000 }, ++ { MT_HEADER_TRANS_CTRL_REG, 0x00000000 }, ++ { MT_FCE_CSO, 0x0000030f }, ++ { MT_FCE_PARAMETERS, 0x00256f0f }, ++}; ++ ++#endif +diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/initvals_phy.h linux-rpi/drivers/net/wireless/mediatek/mt7601u/initvals_phy.h +--- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/initvals_phy.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/initvals_phy.h 2015-11-29 09:42:38.887167260 +0100 +@@ -0,0 +1,291 @@ ++/* ++ * (c) Copyright 2002-2010, Ralink Technology, Inc. ++ * Copyright (C) 2015 Jakub Kicinski ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 ++ * as published by the Free Software Foundation ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef __MT7601U_PHY_INITVALS_H ++#define __MT7601U_PHY_INITVALS_H ++ ++#define RF_REG_PAIR(bank, reg, value) \ ++ { MT_MCU_MEMMAP_RF | (bank) << 16 | (reg), value } ++ ++static const struct mt76_reg_pair rf_central[] = { ++ /* Bank 0 - for central blocks: BG, PLL, XTAL, LO, ADC/DAC */ ++ RF_REG_PAIR(0, 0, 0x02), ++ RF_REG_PAIR(0, 1, 0x01), ++ RF_REG_PAIR(0, 2, 0x11), ++ RF_REG_PAIR(0, 3, 0xff), ++ RF_REG_PAIR(0, 4, 0x0a), ++ RF_REG_PAIR(0, 5, 0x20), ++ RF_REG_PAIR(0, 6, 0x00), ++ /* B/G */ ++ RF_REG_PAIR(0, 7, 0x00), ++ RF_REG_PAIR(0, 8, 0x00), ++ RF_REG_PAIR(0, 9, 0x00), ++ RF_REG_PAIR(0, 10, 0x00), ++ RF_REG_PAIR(0, 11, 0x21), ++ /* XO */ ++ RF_REG_PAIR(0, 13, 0x00), /* 40mhz xtal */ ++ /* RF_REG_PAIR(0, 13, 0x13), */ /* 20mhz xtal */ ++ RF_REG_PAIR(0, 14, 0x7c), ++ RF_REG_PAIR(0, 15, 0x22), ++ RF_REG_PAIR(0, 16, 0x80), ++ /* PLL */ ++ RF_REG_PAIR(0, 17, 0x99), ++ RF_REG_PAIR(0, 18, 0x99), ++ RF_REG_PAIR(0, 19, 0x09), ++ RF_REG_PAIR(0, 20, 0x50), ++ RF_REG_PAIR(0, 21, 0xb0), ++ RF_REG_PAIR(0, 22, 0x00), ++ RF_REG_PAIR(0, 23, 0xc5), ++ RF_REG_PAIR(0, 24, 0xfc), ++ RF_REG_PAIR(0, 25, 0x40), ++ RF_REG_PAIR(0, 26, 0x4d), ++ RF_REG_PAIR(0, 27, 0x02), ++ RF_REG_PAIR(0, 28, 0x72), ++ RF_REG_PAIR(0, 29, 0x01), ++ RF_REG_PAIR(0, 30, 0x00), ++ RF_REG_PAIR(0, 31, 0x00), ++ /* test ports */ ++ RF_REG_PAIR(0, 32, 0x00), ++ RF_REG_PAIR(0, 33, 0x00), ++ RF_REG_PAIR(0, 34, 0x23), ++ RF_REG_PAIR(0, 35, 0x01), /* change setting to reduce spurs */ ++ RF_REG_PAIR(0, 36, 0x00), ++ RF_REG_PAIR(0, 37, 0x00), ++ /* ADC/DAC */ ++ RF_REG_PAIR(0, 38, 0x00), ++ RF_REG_PAIR(0, 39, 0x20), ++ RF_REG_PAIR(0, 40, 0x00), ++ RF_REG_PAIR(0, 41, 0xd0), ++ RF_REG_PAIR(0, 42, 0x1b), ++ RF_REG_PAIR(0, 43, 0x02), ++ RF_REG_PAIR(0, 44, 0x00), ++}; ++ ++static const struct mt76_reg_pair rf_channel[] = { ++ RF_REG_PAIR(4, 0, 0x01), ++ RF_REG_PAIR(4, 1, 0x00), ++ RF_REG_PAIR(4, 2, 0x00), ++ RF_REG_PAIR(4, 3, 0x00), ++ /* LDO */ ++ RF_REG_PAIR(4, 4, 0x00), ++ RF_REG_PAIR(4, 5, 0x08), ++ RF_REG_PAIR(4, 6, 0x00), ++ /* RX */ ++ RF_REG_PAIR(4, 7, 0x5b), ++ RF_REG_PAIR(4, 8, 0x52), ++ RF_REG_PAIR(4, 9, 0xb6), ++ RF_REG_PAIR(4, 10, 0x57), ++ RF_REG_PAIR(4, 11, 0x33), ++ RF_REG_PAIR(4, 12, 0x22), ++ RF_REG_PAIR(4, 13, 0x3d), ++ RF_REG_PAIR(4, 14, 0x3e), ++ RF_REG_PAIR(4, 15, 0x13), ++ RF_REG_PAIR(4, 16, 0x22), ++ RF_REG_PAIR(4, 17, 0x23), ++ RF_REG_PAIR(4, 18, 0x02), ++ RF_REG_PAIR(4, 19, 0xa4), ++ RF_REG_PAIR(4, 20, 0x01), ++ RF_REG_PAIR(4, 21, 0x12), ++ RF_REG_PAIR(4, 22, 0x80), ++ RF_REG_PAIR(4, 23, 0xb3), ++ RF_REG_PAIR(4, 24, 0x00), /* reserved */ ++ RF_REG_PAIR(4, 25, 0x00), /* reserved */ ++ RF_REG_PAIR(4, 26, 0x00), /* reserved */ ++ RF_REG_PAIR(4, 27, 0x00), /* reserved */ ++ /* LOGEN */ ++ RF_REG_PAIR(4, 28, 0x18), ++ RF_REG_PAIR(4, 29, 0xee), ++ RF_REG_PAIR(4, 30, 0x6b), ++ RF_REG_PAIR(4, 31, 0x31), ++ RF_REG_PAIR(4, 32, 0x5d), ++ RF_REG_PAIR(4, 33, 0x00), /* reserved */ ++ /* TX */ ++ RF_REG_PAIR(4, 34, 0x96), ++ RF_REG_PAIR(4, 35, 0x55), ++ RF_REG_PAIR(4, 36, 0x08), ++ RF_REG_PAIR(4, 37, 0xbb), ++ RF_REG_PAIR(4, 38, 0xb3), ++ RF_REG_PAIR(4, 39, 0xb3), ++ RF_REG_PAIR(4, 40, 0x03), ++ RF_REG_PAIR(4, 41, 0x00), /* reserved */ ++ RF_REG_PAIR(4, 42, 0x00), /* reserved */ ++ RF_REG_PAIR(4, 43, 0xc5), ++ RF_REG_PAIR(4, 44, 0xc5), ++ RF_REG_PAIR(4, 45, 0xc5), ++ RF_REG_PAIR(4, 46, 0x07), ++ RF_REG_PAIR(4, 47, 0xa8), ++ RF_REG_PAIR(4, 48, 0xef), ++ RF_REG_PAIR(4, 49, 0x1a), ++ /* PA */ ++ RF_REG_PAIR(4, 54, 0x07), ++ RF_REG_PAIR(4, 55, 0xa7), ++ RF_REG_PAIR(4, 56, 0xcc), ++ RF_REG_PAIR(4, 57, 0x14), ++ RF_REG_PAIR(4, 58, 0x07), ++ RF_REG_PAIR(4, 59, 0xa8), ++ RF_REG_PAIR(4, 60, 0xd7), ++ RF_REG_PAIR(4, 61, 0x10), ++ RF_REG_PAIR(4, 62, 0x1c), ++ RF_REG_PAIR(4, 63, 0x00), /* reserved */ ++}; ++ ++static const struct mt76_reg_pair rf_vga[] = { ++ RF_REG_PAIR(5, 0, 0x47), ++ RF_REG_PAIR(5, 1, 0x00), ++ RF_REG_PAIR(5, 2, 0x00), ++ RF_REG_PAIR(5, 3, 0x08), ++ RF_REG_PAIR(5, 4, 0x04), ++ RF_REG_PAIR(5, 5, 0x20), ++ RF_REG_PAIR(5, 6, 0x3a), ++ RF_REG_PAIR(5, 7, 0x3a), ++ RF_REG_PAIR(5, 8, 0x00), ++ RF_REG_PAIR(5, 9, 0x00), ++ RF_REG_PAIR(5, 10, 0x10), ++ RF_REG_PAIR(5, 11, 0x10), ++ RF_REG_PAIR(5, 12, 0x10), ++ RF_REG_PAIR(5, 13, 0x10), ++ RF_REG_PAIR(5, 14, 0x10), ++ RF_REG_PAIR(5, 15, 0x20), ++ RF_REG_PAIR(5, 16, 0x22), ++ RF_REG_PAIR(5, 17, 0x7c), ++ RF_REG_PAIR(5, 18, 0x00), ++ RF_REG_PAIR(5, 19, 0x00), ++ RF_REG_PAIR(5, 20, 0x00), ++ RF_REG_PAIR(5, 21, 0xf1), ++ RF_REG_PAIR(5, 22, 0x11), ++ RF_REG_PAIR(5, 23, 0x02), ++ RF_REG_PAIR(5, 24, 0x41), ++ RF_REG_PAIR(5, 25, 0x20), ++ RF_REG_PAIR(5, 26, 0x00), ++ RF_REG_PAIR(5, 27, 0xd7), ++ RF_REG_PAIR(5, 28, 0xa2), ++ RF_REG_PAIR(5, 29, 0x20), ++ RF_REG_PAIR(5, 30, 0x49), ++ RF_REG_PAIR(5, 31, 0x20), ++ RF_REG_PAIR(5, 32, 0x04), ++ RF_REG_PAIR(5, 33, 0xf1), ++ RF_REG_PAIR(5, 34, 0xa1), ++ RF_REG_PAIR(5, 35, 0x01), ++ RF_REG_PAIR(5, 41, 0x00), ++ RF_REG_PAIR(5, 42, 0x00), ++ RF_REG_PAIR(5, 43, 0x00), ++ RF_REG_PAIR(5, 44, 0x00), ++ RF_REG_PAIR(5, 45, 0x00), ++ RF_REG_PAIR(5, 46, 0x00), ++ RF_REG_PAIR(5, 47, 0x00), ++ RF_REG_PAIR(5, 48, 0x00), ++ RF_REG_PAIR(5, 49, 0x00), ++ RF_REG_PAIR(5, 50, 0x00), ++ RF_REG_PAIR(5, 51, 0x00), ++ RF_REG_PAIR(5, 52, 0x00), ++ RF_REG_PAIR(5, 53, 0x00), ++ RF_REG_PAIR(5, 54, 0x00), ++ RF_REG_PAIR(5, 55, 0x00), ++ RF_REG_PAIR(5, 56, 0x00), ++ RF_REG_PAIR(5, 57, 0x00), ++ RF_REG_PAIR(5, 58, 0x31), ++ RF_REG_PAIR(5, 59, 0x31), ++ RF_REG_PAIR(5, 60, 0x0a), ++ RF_REG_PAIR(5, 61, 0x02), ++ RF_REG_PAIR(5, 62, 0x00), ++ RF_REG_PAIR(5, 63, 0x00), ++}; ++ ++/* TODO: BBP178 is set to 0xff for "CCK CH14 OBW" which overrides the settings ++ * from channel switching. Seems stupid at best. ++ */ ++static const struct mt76_reg_pair bbp_high_temp[] = { ++ { 75, 0x60 }, ++ { 92, 0x02 }, ++ { 178, 0xff }, /* For CCK CH14 OBW */ ++ { 195, 0x88 }, { 196, 0x60 }, ++}, bbp_high_temp_bw20[] = { ++ { 69, 0x12 }, ++ { 91, 0x07 }, ++ { 195, 0x23 }, { 196, 0x17 }, ++ { 195, 0x24 }, { 196, 0x06 }, ++ { 195, 0x81 }, { 196, 0x12 }, ++ { 195, 0x83 }, { 196, 0x17 }, ++}, bbp_high_temp_bw40[] = { ++ { 69, 0x15 }, ++ { 91, 0x04 }, ++ { 195, 0x23 }, { 196, 0x12 }, ++ { 195, 0x24 }, { 196, 0x08 }, ++ { 195, 0x81 }, { 196, 0x15 }, ++ { 195, 0x83 }, { 196, 0x16 }, ++}, bbp_low_temp[] = { ++ { 178, 0xff }, /* For CCK CH14 OBW */ ++}, bbp_low_temp_bw20[] = { ++ { 69, 0x12 }, ++ { 75, 0x5e }, ++ { 91, 0x07 }, ++ { 92, 0x02 }, ++ { 195, 0x23 }, { 196, 0x17 }, ++ { 195, 0x24 }, { 196, 0x06 }, ++ { 195, 0x81 }, { 196, 0x12 }, ++ { 195, 0x83 }, { 196, 0x17 }, ++ { 195, 0x88 }, { 196, 0x5e }, ++}, bbp_low_temp_bw40[] = { ++ { 69, 0x15 }, ++ { 75, 0x5c }, ++ { 91, 0x04 }, ++ { 92, 0x03 }, ++ { 195, 0x23 }, { 196, 0x10 }, ++ { 195, 0x24 }, { 196, 0x08 }, ++ { 195, 0x81 }, { 196, 0x15 }, ++ { 195, 0x83 }, { 196, 0x16 }, ++ { 195, 0x88 }, { 196, 0x5b }, ++}, bbp_normal_temp[] = { ++ { 75, 0x60 }, ++ { 92, 0x02 }, ++ { 178, 0xff }, /* For CCK CH14 OBW */ ++ { 195, 0x88 }, { 196, 0x60 }, ++}, bbp_normal_temp_bw20[] = { ++ { 69, 0x12 }, ++ { 91, 0x07 }, ++ { 195, 0x23 }, { 196, 0x17 }, ++ { 195, 0x24 }, { 196, 0x06 }, ++ { 195, 0x81 }, { 196, 0x12 }, ++ { 195, 0x83 }, { 196, 0x17 }, ++}, bbp_normal_temp_bw40[] = { ++ { 69, 0x15 }, ++ { 91, 0x04 }, ++ { 195, 0x23 }, { 196, 0x12 }, ++ { 195, 0x24 }, { 196, 0x08 }, ++ { 195, 0x81 }, { 196, 0x15 }, ++ { 195, 0x83 }, { 196, 0x16 }, ++}; ++ ++#define BBP_TABLE(arr) { arr, ARRAY_SIZE(arr), } ++ ++static const struct reg_table { ++ const struct mt76_reg_pair *regs; ++ size_t n; ++} bbp_mode_table[3][3] = { ++ { ++ BBP_TABLE(bbp_normal_temp_bw20), ++ BBP_TABLE(bbp_normal_temp_bw40), ++ BBP_TABLE(bbp_normal_temp), ++ }, { ++ BBP_TABLE(bbp_high_temp_bw20), ++ BBP_TABLE(bbp_high_temp_bw40), ++ BBP_TABLE(bbp_high_temp), ++ }, { ++ BBP_TABLE(bbp_low_temp_bw20), ++ BBP_TABLE(bbp_low_temp_bw40), ++ BBP_TABLE(bbp_low_temp), ++ } ++}; ++ ++#endif +diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/Kconfig linux-rpi/drivers/net/wireless/mediatek/mt7601u/Kconfig +--- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/Kconfig 2015-11-29 09:42:38.887167260 +0100 +@@ -0,0 +1,6 @@ ++config MT7601U ++ tristate "MediaTek MT7601U (USB) support" ++ depends on MAC80211 ++ depends on USB ++ ---help--- ++ This adds support for MT7601U-based wireless USB dongles. +diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/mac.c linux-rpi/drivers/net/wireless/mediatek/mt7601u/mac.c +--- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/mac.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/mac.c 2015-11-29 09:42:38.887167260 +0100 +@@ -0,0 +1,577 @@ ++/* ++ * Copyright (C) 2014 Felix Fietkau ++ * Copyright (C) 2015 Jakub Kicinski ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 ++ * as published by the Free Software Foundation ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include "mt7601u.h" ++#include "trace.h" ++#include ++ ++static void ++mt76_mac_process_tx_rate(struct ieee80211_tx_rate *txrate, u16 rate) ++{ ++ u8 idx = MT76_GET(MT_TXWI_RATE_MCS, rate); ++ ++ txrate->idx = 0; ++ txrate->flags = 0; ++ txrate->count = 1; ++ ++ switch (MT76_GET(MT_TXWI_RATE_PHY_MODE, rate)) { ++ case MT_PHY_TYPE_OFDM: ++ txrate->idx = idx + 4; ++ return; ++ case MT_PHY_TYPE_CCK: ++ if (idx >= 8) ++ idx -= 8; ++ ++ txrate->idx = idx; ++ return; ++ case MT_PHY_TYPE_HT_GF: ++ txrate->flags |= IEEE80211_TX_RC_GREEN_FIELD; ++ /* fall through */ ++ case MT_PHY_TYPE_HT: ++ txrate->flags |= IEEE80211_TX_RC_MCS; ++ txrate->idx = idx; ++ break; ++ default: ++ WARN_ON(1); ++ return; ++ } ++ ++ if (MT76_GET(MT_TXWI_RATE_BW, rate) == MT_PHY_BW_40) ++ txrate->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH; ++ ++ if (rate & MT_TXWI_RATE_SGI) ++ txrate->flags |= IEEE80211_TX_RC_SHORT_GI; ++} ++ ++static void ++mt76_mac_fill_tx_status(struct mt7601u_dev *dev, struct ieee80211_tx_info *info, ++ struct mt76_tx_status *st) ++{ ++ struct ieee80211_tx_rate *rate = info->status.rates; ++ int cur_idx, last_rate; ++ int i; ++ ++ last_rate = min_t(int, st->retry, IEEE80211_TX_MAX_RATES - 1); ++ mt76_mac_process_tx_rate(&rate[last_rate], st->rate); ++ if (last_rate < IEEE80211_TX_MAX_RATES - 1) ++ rate[last_rate + 1].idx = -1; ++ ++ cur_idx = rate[last_rate].idx + st->retry; ++ for (i = 0; i <= last_rate; i++) { ++ rate[i].flags = rate[last_rate].flags; ++ rate[i].idx = max_t(int, 0, cur_idx - i); ++ rate[i].count = 1; ++ } ++ ++ if (last_rate > 0) ++ rate[last_rate - 1].count = st->retry + 1 - last_rate; ++ ++ info->status.ampdu_len = 1; ++ info->status.ampdu_ack_len = st->success; ++ ++ if (st->is_probe) ++ info->flags |= IEEE80211_TX_CTL_RATE_CTRL_PROBE; ++ ++ if (st->aggr) ++ info->flags |= IEEE80211_TX_CTL_AMPDU | ++ IEEE80211_TX_STAT_AMPDU; ++ ++ if (!st->ack_req) ++ info->flags |= IEEE80211_TX_CTL_NO_ACK; ++ else if (st->success) ++ info->flags |= IEEE80211_TX_STAT_ACK; ++} ++ ++u16 mt76_mac_tx_rate_val(struct mt7601u_dev *dev, ++ const struct ieee80211_tx_rate *rate, u8 *nss_val) ++{ ++ u16 rateval; ++ u8 phy, rate_idx; ++ u8 nss = 1; ++ u8 bw = 0; ++ ++ if (rate->flags & IEEE80211_TX_RC_MCS) { ++ rate_idx = rate->idx; ++ nss = 1 + (rate->idx >> 3); ++ phy = MT_PHY_TYPE_HT; ++ if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD) ++ phy = MT_PHY_TYPE_HT_GF; ++ if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ++ bw = 1; ++ } else { ++ const struct ieee80211_rate *r; ++ int band = dev->chandef.chan->band; ++ u16 val; ++ ++ r = &dev->hw->wiphy->bands[band]->bitrates[rate->idx]; ++ if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ++ val = r->hw_value_short; ++ else ++ val = r->hw_value; ++ ++ phy = val >> 8; ++ rate_idx = val & 0xff; ++ bw = 0; ++ } ++ ++ rateval = MT76_SET(MT_RXWI_RATE_MCS, rate_idx); ++ rateval |= MT76_SET(MT_RXWI_RATE_PHY, phy); ++ rateval |= MT76_SET(MT_RXWI_RATE_BW, bw); ++ if (rate->flags & IEEE80211_TX_RC_SHORT_GI) ++ rateval |= MT_RXWI_RATE_SGI; ++ ++ *nss_val = nss; ++ return rateval; ++} ++ ++void mt76_mac_wcid_set_rate(struct mt7601u_dev *dev, struct mt76_wcid *wcid, ++ const struct ieee80211_tx_rate *rate) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&dev->lock, flags); ++ wcid->tx_rate = mt76_mac_tx_rate_val(dev, rate, &wcid->tx_rate_nss); ++ wcid->tx_rate_set = true; ++ spin_unlock_irqrestore(&dev->lock, flags); ++} ++ ++struct mt76_tx_status mt7601u_mac_fetch_tx_status(struct mt7601u_dev *dev) ++{ ++ struct mt76_tx_status stat = {}; ++ u32 val; ++ ++ val = mt7601u_rr(dev, MT_TX_STAT_FIFO); ++ stat.valid = !!(val & MT_TX_STAT_FIFO_VALID); ++ stat.success = !!(val & MT_TX_STAT_FIFO_SUCCESS); ++ stat.aggr = !!(val & MT_TX_STAT_FIFO_AGGR); ++ stat.ack_req = !!(val & MT_TX_STAT_FIFO_ACKREQ); ++ stat.pktid = MT76_GET(MT_TX_STAT_FIFO_PID_TYPE, val); ++ stat.wcid = MT76_GET(MT_TX_STAT_FIFO_WCID, val); ++ stat.rate = MT76_GET(MT_TX_STAT_FIFO_RATE, val); ++ ++ return stat; ++} ++ ++void mt76_send_tx_status(struct mt7601u_dev *dev, struct mt76_tx_status *stat) ++{ ++ struct ieee80211_tx_info info = {}; ++ struct ieee80211_sta *sta = NULL; ++ struct mt76_wcid *wcid = NULL; ++ void *msta; ++ ++ rcu_read_lock(); ++ if (stat->wcid < ARRAY_SIZE(dev->wcid)) ++ wcid = rcu_dereference(dev->wcid[stat->wcid]); ++ ++ if (wcid) { ++ msta = container_of(wcid, struct mt76_sta, wcid); ++ sta = container_of(msta, struct ieee80211_sta, ++ drv_priv); ++ } ++ ++ mt76_mac_fill_tx_status(dev, &info, stat); ++ ++ spin_lock_bh(&dev->mac_lock); ++ ieee80211_tx_status_noskb(dev->hw, sta, &info); ++ spin_unlock_bh(&dev->mac_lock); ++ ++ rcu_read_unlock(); ++} ++ ++void mt7601u_mac_set_protection(struct mt7601u_dev *dev, bool legacy_prot, ++ int ht_mode) ++{ ++ int mode = ht_mode & IEEE80211_HT_OP_MODE_PROTECTION; ++ bool non_gf = !!(ht_mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT); ++ u32 prot[6]; ++ bool ht_rts[4] = {}; ++ int i; ++ ++ prot[0] = MT_PROT_NAV_SHORT | ++ MT_PROT_TXOP_ALLOW_ALL | ++ MT_PROT_RTS_THR_EN; ++ prot[1] = prot[0]; ++ if (legacy_prot) ++ prot[1] |= MT_PROT_CTRL_CTS2SELF; ++ ++ prot[2] = prot[4] = MT_PROT_NAV_SHORT | MT_PROT_TXOP_ALLOW_BW20; ++ prot[3] = prot[5] = MT_PROT_NAV_SHORT | MT_PROT_TXOP_ALLOW_ALL; ++ ++ if (legacy_prot) { ++ prot[2] |= MT_PROT_RATE_CCK_11; ++ prot[3] |= MT_PROT_RATE_CCK_11; ++ prot[4] |= MT_PROT_RATE_CCK_11; ++ prot[5] |= MT_PROT_RATE_CCK_11; ++ } else { ++ prot[2] |= MT_PROT_RATE_OFDM_24; ++ prot[3] |= MT_PROT_RATE_DUP_OFDM_24; ++ prot[4] |= MT_PROT_RATE_OFDM_24; ++ prot[5] |= MT_PROT_RATE_DUP_OFDM_24; ++ } ++ ++ switch (mode) { ++ case IEEE80211_HT_OP_MODE_PROTECTION_NONE: ++ break; ++ ++ case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER: ++ ht_rts[0] = ht_rts[1] = ht_rts[2] = ht_rts[3] = true; ++ break; ++ ++ case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ: ++ ht_rts[1] = ht_rts[3] = true; ++ break; ++ ++ case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED: ++ ht_rts[0] = ht_rts[1] = ht_rts[2] = ht_rts[3] = true; ++ break; ++ } ++ ++ if (non_gf) ++ ht_rts[2] = ht_rts[3] = true; ++ ++ for (i = 0; i < 4; i++) ++ if (ht_rts[i]) ++ prot[i + 2] |= MT_PROT_CTRL_RTS_CTS; ++ ++ for (i = 0; i < 6; i++) ++ mt7601u_wr(dev, MT_CCK_PROT_CFG + i * 4, prot[i]); ++} ++ ++void mt7601u_mac_set_short_preamble(struct mt7601u_dev *dev, bool short_preamb) ++{ ++ if (short_preamb) ++ mt76_set(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_PREAMB_SHORT); ++ else ++ mt76_clear(dev, MT_AUTO_RSP_CFG, MT_AUTO_RSP_PREAMB_SHORT); ++} ++ ++void mt7601u_mac_config_tsf(struct mt7601u_dev *dev, bool enable, int interval) ++{ ++ u32 val = mt7601u_rr(dev, MT_BEACON_TIME_CFG); ++ ++ val &= ~(MT_BEACON_TIME_CFG_TIMER_EN | ++ MT_BEACON_TIME_CFG_SYNC_MODE | ++ MT_BEACON_TIME_CFG_TBTT_EN); ++ ++ if (!enable) { ++ mt7601u_wr(dev, MT_BEACON_TIME_CFG, val); ++ return; ++ } ++ ++ val &= ~MT_BEACON_TIME_CFG_INTVAL; ++ val |= MT76_SET(MT_BEACON_TIME_CFG_INTVAL, interval << 4) | ++ MT_BEACON_TIME_CFG_TIMER_EN | ++ MT_BEACON_TIME_CFG_SYNC_MODE | ++ MT_BEACON_TIME_CFG_TBTT_EN; ++} ++ ++static void mt7601u_check_mac_err(struct mt7601u_dev *dev) ++{ ++ u32 val = mt7601u_rr(dev, 0x10f4); ++ ++ if (!(val & BIT(29)) || !(val & (BIT(7) | BIT(5)))) ++ return; ++ ++ dev_err(dev->dev, "Error: MAC specific condition occurred\n"); ++ ++ mt76_set(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_RESET_CSR); ++ udelay(10); ++ mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_RESET_CSR); ++} ++ ++void mt7601u_mac_work(struct work_struct *work) ++{ ++ struct mt7601u_dev *dev = container_of(work, struct mt7601u_dev, ++ mac_work.work); ++ struct { ++ u32 addr_base; ++ u32 span; ++ u64 *stat_base; ++ } spans[] = { ++ { MT_RX_STA_CNT0, 3, dev->stats.rx_stat }, ++ { MT_TX_STA_CNT0, 3, dev->stats.tx_stat }, ++ { MT_TX_AGG_STAT, 1, dev->stats.aggr_stat }, ++ { MT_MPDU_DENSITY_CNT, 1, dev->stats.zero_len_del }, ++ { MT_TX_AGG_CNT_BASE0, 8, &dev->stats.aggr_n[0] }, ++ { MT_TX_AGG_CNT_BASE1, 8, &dev->stats.aggr_n[16] }, ++ }; ++ u32 sum, n; ++ int i, j, k; ++ ++ /* Note: using MCU_RANDOM_READ is actually slower then reading all the ++ * registers by hand. MCU takes ca. 20ms to complete read of 24 ++ * registers while reading them one by one will takes roughly ++ * 24*200us =~ 5ms. ++ */ ++ ++ k = 0; ++ n = 0; ++ sum = 0; ++ for (i = 0; i < ARRAY_SIZE(spans); i++) ++ for (j = 0; j < spans[i].span; j++) { ++ u32 val = mt7601u_rr(dev, spans[i].addr_base + j * 4); ++ ++ spans[i].stat_base[j * 2] += val & 0xffff; ++ spans[i].stat_base[j * 2 + 1] += val >> 16; ++ ++ /* Calculate average AMPDU length */ ++ if (spans[i].addr_base != MT_TX_AGG_CNT_BASE0 && ++ spans[i].addr_base != MT_TX_AGG_CNT_BASE1) ++ continue; ++ ++ n += (val >> 16) + (val & 0xffff); ++ sum += (val & 0xffff) * (1 + k * 2) + ++ (val >> 16) * (2 + k * 2); ++ k++; ++ } ++ ++ atomic_set(&dev->avg_ampdu_len, n ? DIV_ROUND_CLOSEST(sum, n) : 1); ++ ++ mt7601u_check_mac_err(dev); ++ ++ ieee80211_queue_delayed_work(dev->hw, &dev->mac_work, 10 * HZ); ++} ++ ++void ++mt7601u_mac_wcid_setup(struct mt7601u_dev *dev, u8 idx, u8 vif_idx, u8 *mac) ++{ ++ u8 zmac[ETH_ALEN] = {}; ++ u32 attr; ++ ++ attr = MT76_SET(MT_WCID_ATTR_BSS_IDX, vif_idx & 7) | ++ MT76_SET(MT_WCID_ATTR_BSS_IDX_EXT, !!(vif_idx & 8)); ++ ++ mt76_wr(dev, MT_WCID_ATTR(idx), attr); ++ ++ if (mac) ++ memcpy(zmac, mac, sizeof(zmac)); ++ ++ mt7601u_addr_wr(dev, MT_WCID_ADDR(idx), zmac); ++} ++ ++void mt7601u_mac_set_ampdu_factor(struct mt7601u_dev *dev) ++{ ++ struct ieee80211_sta *sta; ++ struct mt76_wcid *wcid; ++ void *msta; ++ u8 min_factor = 3; ++ int i; ++ ++ rcu_read_lock(); ++ for (i = 0; i < ARRAY_SIZE(dev->wcid); i++) { ++ wcid = rcu_dereference(dev->wcid[i]); ++ if (!wcid) ++ continue; ++ ++ msta = container_of(wcid, struct mt76_sta, wcid); ++ sta = container_of(msta, struct ieee80211_sta, drv_priv); ++ ++ min_factor = min(min_factor, sta->ht_cap.ampdu_factor); ++ } ++ rcu_read_unlock(); ++ ++ mt7601u_wr(dev, MT_MAX_LEN_CFG, 0xa0fff | ++ MT76_SET(MT_MAX_LEN_CFG_AMPDU, min_factor)); ++} ++ ++static void ++mt76_mac_process_rate(struct ieee80211_rx_status *status, u16 rate) ++{ ++ u8 idx = MT76_GET(MT_RXWI_RATE_MCS, rate); ++ ++ switch (MT76_GET(MT_RXWI_RATE_PHY, rate)) { ++ case MT_PHY_TYPE_OFDM: ++ if (WARN_ON(idx >= 8)) ++ idx = 0; ++ idx += 4; ++ ++ status->rate_idx = idx; ++ return; ++ case MT_PHY_TYPE_CCK: ++ if (idx >= 8) { ++ idx -= 8; ++ status->flag |= RX_FLAG_SHORTPRE; ++ } ++ ++ if (WARN_ON(idx >= 4)) ++ idx = 0; ++ ++ status->rate_idx = idx; ++ return; ++ case MT_PHY_TYPE_HT_GF: ++ status->flag |= RX_FLAG_HT_GF; ++ /* fall through */ ++ case MT_PHY_TYPE_HT: ++ status->flag |= RX_FLAG_HT; ++ status->rate_idx = idx; ++ break; ++ default: ++ WARN_ON(1); ++ return; ++ } ++ ++ if (rate & MT_RXWI_RATE_SGI) ++ status->flag |= RX_FLAG_SHORT_GI; ++ ++ if (rate & MT_RXWI_RATE_STBC) ++ status->flag |= 1 << RX_FLAG_STBC_SHIFT; ++ ++ if (rate & MT_RXWI_RATE_BW) ++ status->flag |= RX_FLAG_40MHZ; ++} ++ ++static void ++mt7601u_rx_monitor_beacon(struct mt7601u_dev *dev, struct mt7601u_rxwi *rxwi, ++ u16 rate, int rssi) ++{ ++ dev->bcn_freq_off = rxwi->freq_off; ++ dev->bcn_phy_mode = MT76_GET(MT_RXWI_RATE_PHY, rate); ++ dev->avg_rssi = (dev->avg_rssi * 15) / 16 + (rssi << 8); ++} ++ ++static int ++mt7601u_rx_is_our_beacon(struct mt7601u_dev *dev, u8 *data) ++{ ++ struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)data; ++ ++ return ieee80211_is_beacon(hdr->frame_control) && ++ ether_addr_equal(hdr->addr2, dev->ap_bssid); ++} ++ ++u32 mt76_mac_process_rx(struct mt7601u_dev *dev, struct sk_buff *skb, ++ u8 *data, void *rxi) ++{ ++ struct ieee80211_rx_status *status = IEEE80211_SKB_RXCB(skb); ++ struct mt7601u_rxwi *rxwi = rxi; ++ u32 len, ctl = le32_to_cpu(rxwi->ctl); ++ u16 rate = le16_to_cpu(rxwi->rate); ++ int rssi; ++ ++ len = MT76_GET(MT_RXWI_CTL_MPDU_LEN, ctl); ++ if (len < 10) ++ return 0; ++ ++ if (rxwi->rxinfo & cpu_to_le32(MT_RXINFO_DECRYPT)) { ++ status->flag |= RX_FLAG_DECRYPTED; ++ status->flag |= RX_FLAG_IV_STRIPPED | RX_FLAG_MMIC_STRIPPED; ++ } ++ ++ status->chains = BIT(0); ++ rssi = mt7601u_phy_get_rssi(dev, rxwi, rate); ++ status->chain_signal[0] = status->signal = rssi; ++ status->freq = dev->chandef.chan->center_freq; ++ status->band = dev->chandef.chan->band; ++ ++ mt76_mac_process_rate(status, rate); ++ ++ spin_lock_bh(&dev->con_mon_lock); ++ if (mt7601u_rx_is_our_beacon(dev, data)) ++ mt7601u_rx_monitor_beacon(dev, rxwi, rate, rssi); ++ else if (rxwi->rxinfo & cpu_to_le32(MT_RXINFO_U2M)) ++ dev->avg_rssi = (dev->avg_rssi * 15) / 16 + (rssi << 8); ++ spin_unlock_bh(&dev->con_mon_lock); ++ ++ return len; ++} ++ ++static enum mt76_cipher_type ++mt76_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data) ++{ ++ memset(key_data, 0, 32); ++ if (!key) ++ return MT_CIPHER_NONE; ++ ++ if (key->keylen > 32) ++ return MT_CIPHER_NONE; ++ ++ memcpy(key_data, key->key, key->keylen); ++ ++ switch (key->cipher) { ++ case WLAN_CIPHER_SUITE_WEP40: ++ return MT_CIPHER_WEP40; ++ case WLAN_CIPHER_SUITE_WEP104: ++ return MT_CIPHER_WEP104; ++ case WLAN_CIPHER_SUITE_TKIP: ++ return MT_CIPHER_TKIP; ++ case WLAN_CIPHER_SUITE_CCMP: ++ return MT_CIPHER_AES_CCMP; ++ default: ++ return MT_CIPHER_NONE; ++ } ++} ++ ++int mt76_mac_wcid_set_key(struct mt7601u_dev *dev, u8 idx, ++ struct ieee80211_key_conf *key) ++{ ++ enum mt76_cipher_type cipher; ++ u8 key_data[32]; ++ u8 iv_data[8]; ++ u32 val; ++ ++ cipher = mt76_mac_get_key_info(key, key_data); ++ if (cipher == MT_CIPHER_NONE && key) ++ return -EINVAL; ++ ++ trace_set_key(dev, idx); ++ ++ mt7601u_wr_copy(dev, MT_WCID_KEY(idx), key_data, sizeof(key_data)); ++ ++ memset(iv_data, 0, sizeof(iv_data)); ++ if (key) { ++ iv_data[3] = key->keyidx << 6; ++ if (cipher >= MT_CIPHER_TKIP) { ++ /* Note: start with 1 to comply with spec, ++ * (see comment on common/cmm_wpa.c:4291). ++ */ ++ iv_data[0] |= 1; ++ iv_data[3] |= 0x20; ++ } ++ } ++ mt7601u_wr_copy(dev, MT_WCID_IV(idx), iv_data, sizeof(iv_data)); ++ ++ val = mt7601u_rr(dev, MT_WCID_ATTR(idx)); ++ val &= ~MT_WCID_ATTR_PKEY_MODE & ~MT_WCID_ATTR_PKEY_MODE_EXT; ++ val |= MT76_SET(MT_WCID_ATTR_PKEY_MODE, cipher & 7) | ++ MT76_SET(MT_WCID_ATTR_PKEY_MODE_EXT, cipher >> 3); ++ val &= ~MT_WCID_ATTR_PAIRWISE; ++ val |= MT_WCID_ATTR_PAIRWISE * ++ !!(key && key->flags & IEEE80211_KEY_FLAG_PAIRWISE); ++ mt7601u_wr(dev, MT_WCID_ATTR(idx), val); ++ ++ return 0; ++} ++ ++int mt76_mac_shared_key_setup(struct mt7601u_dev *dev, u8 vif_idx, u8 key_idx, ++ struct ieee80211_key_conf *key) ++{ ++ enum mt76_cipher_type cipher; ++ u8 key_data[32]; ++ u32 val; ++ ++ cipher = mt76_mac_get_key_info(key, key_data); ++ if (cipher == MT_CIPHER_NONE && key) ++ return -EINVAL; ++ ++ trace_set_shared_key(dev, vif_idx, key_idx); ++ ++ mt7601u_wr_copy(dev, MT_SKEY(vif_idx, key_idx), ++ key_data, sizeof(key_data)); ++ ++ val = mt76_rr(dev, MT_SKEY_MODE(vif_idx)); ++ val &= ~(MT_SKEY_MODE_MASK << MT_SKEY_MODE_SHIFT(vif_idx, key_idx)); ++ val |= cipher << MT_SKEY_MODE_SHIFT(vif_idx, key_idx); ++ mt76_wr(dev, MT_SKEY_MODE(vif_idx), val); ++ ++ return 0; ++} +diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/mac.h linux-rpi/drivers/net/wireless/mediatek/mt7601u/mac.h +--- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/mac.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/mac.h 2015-11-29 09:42:38.887167260 +0100 +@@ -0,0 +1,178 @@ ++/* ++ * Copyright (C) 2014 Felix Fietkau ++ * Copyright (C) 2015 Jakub Kicinski ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 ++ * as published by the Free Software Foundation ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef __MT76_MAC_H ++#define __MT76_MAC_H ++ ++struct mt76_tx_status { ++ u8 valid:1; ++ u8 success:1; ++ u8 aggr:1; ++ u8 ack_req:1; ++ u8 is_probe:1; ++ u8 wcid; ++ u8 pktid; ++ u8 retry; ++ u16 rate; ++} __packed __aligned(2); ++ ++/* Note: values in original "RSSI" and "SNR" fields are not actually what they ++ * are called for MT7601U, names used by this driver are educated guesses ++ * (see vendor mac/ral_omac.c). ++ */ ++struct mt7601u_rxwi { ++ __le32 rxinfo; ++ ++ __le32 ctl; ++ ++ __le16 frag_sn; ++ __le16 rate; ++ ++ u8 unknown; ++ u8 zero[3]; ++ ++ u8 snr; ++ u8 ant; ++ u8 gain; ++ u8 freq_off; ++ ++ __le32 resv2; ++ __le32 expert_ant; ++} __packed __aligned(4); ++ ++#define MT_RXINFO_BA BIT(0) ++#define MT_RXINFO_DATA BIT(1) ++#define MT_RXINFO_NULL BIT(2) ++#define MT_RXINFO_FRAG BIT(3) ++#define MT_RXINFO_U2M BIT(4) ++#define MT_RXINFO_MULTICAST BIT(5) ++#define MT_RXINFO_BROADCAST BIT(6) ++#define MT_RXINFO_MYBSS BIT(7) ++#define MT_RXINFO_CRCERR BIT(8) ++#define MT_RXINFO_ICVERR BIT(9) ++#define MT_RXINFO_MICERR BIT(10) ++#define MT_RXINFO_AMSDU BIT(11) ++#define MT_RXINFO_HTC BIT(12) ++#define MT_RXINFO_RSSI BIT(13) ++#define MT_RXINFO_L2PAD BIT(14) ++#define MT_RXINFO_AMPDU BIT(15) ++#define MT_RXINFO_DECRYPT BIT(16) ++#define MT_RXINFO_BSSIDX3 BIT(17) ++#define MT_RXINFO_WAPI_KEY BIT(18) ++#define MT_RXINFO_PN_LEN GENMASK(21, 19) ++#define MT_RXINFO_SW_PKT_80211 BIT(22) ++#define MT_RXINFO_TCP_SUM_BYPASS BIT(28) ++#define MT_RXINFO_IP_SUM_BYPASS BIT(29) ++#define MT_RXINFO_TCP_SUM_ERR BIT(30) ++#define MT_RXINFO_IP_SUM_ERR BIT(31) ++ ++#define MT_RXWI_CTL_WCID GENMASK(7, 0) ++#define MT_RXWI_CTL_KEY_IDX GENMASK(9, 8) ++#define MT_RXWI_CTL_BSS_IDX GENMASK(12, 10) ++#define MT_RXWI_CTL_UDF GENMASK(15, 13) ++#define MT_RXWI_CTL_MPDU_LEN GENMASK(27, 16) ++#define MT_RXWI_CTL_TID GENMASK(31, 28) ++ ++#define MT_RXWI_FRAG GENMASK(3, 0) ++#define MT_RXWI_SN GENMASK(15, 4) ++ ++#define MT_RXWI_RATE_MCS GENMASK(6, 0) ++#define MT_RXWI_RATE_BW BIT(7) ++#define MT_RXWI_RATE_SGI BIT(8) ++#define MT_RXWI_RATE_STBC GENMASK(10, 9) ++#define MT_RXWI_RATE_ETXBF BIT(11) ++#define MT_RXWI_RATE_SND BIT(12) ++#define MT_RXWI_RATE_ITXBF BIT(13) ++#define MT_RXWI_RATE_PHY GENMASK(15, 14) ++ ++#define MT_RXWI_GAIN_RSSI_VAL GENMASK(5, 0) ++#define MT_RXWI_GAIN_RSSI_LNA_ID GENMASK(7, 6) ++#define MT_RXWI_ANT_AUX_LNA BIT(7) ++ ++#define MT_RXWI_EANT_ENC_ANT_ID GENMASK(7, 0) ++ ++enum mt76_phy_type { ++ MT_PHY_TYPE_CCK, ++ MT_PHY_TYPE_OFDM, ++ MT_PHY_TYPE_HT, ++ MT_PHY_TYPE_HT_GF, ++}; ++ ++enum mt76_phy_bandwidth { ++ MT_PHY_BW_20, ++ MT_PHY_BW_40, ++}; ++ ++struct mt76_txwi { ++ __le16 flags; ++ __le16 rate_ctl; ++ ++ u8 ack_ctl; ++ u8 wcid; ++ __le16 len_ctl; ++ ++ __le32 iv; ++ ++ __le32 eiv; ++ ++ u8 aid; ++ u8 txstream; ++ __le16 ctl; ++} __packed __aligned(4); ++ ++#define MT_TXWI_FLAGS_FRAG BIT(0) ++#define MT_TXWI_FLAGS_MMPS BIT(1) ++#define MT_TXWI_FLAGS_CFACK BIT(2) ++#define MT_TXWI_FLAGS_TS BIT(3) ++#define MT_TXWI_FLAGS_AMPDU BIT(4) ++#define MT_TXWI_FLAGS_MPDU_DENSITY GENMASK(7, 5) ++#define MT_TXWI_FLAGS_TXOP GENMASK(9, 8) ++#define MT_TXWI_FLAGS_CWMIN GENMASK(12, 10) ++#define MT_TXWI_FLAGS_NO_RATE_FALLBACK BIT(13) ++#define MT_TXWI_FLAGS_TX_RPT BIT(14) ++#define MT_TXWI_FLAGS_TX_RATE_LUT BIT(15) ++ ++#define MT_TXWI_RATE_MCS GENMASK(6, 0) ++#define MT_TXWI_RATE_BW BIT(7) ++#define MT_TXWI_RATE_SGI BIT(8) ++#define MT_TXWI_RATE_STBC GENMASK(10, 9) ++#define MT_TXWI_RATE_PHY_MODE GENMASK(15, 14) ++ ++#define MT_TXWI_ACK_CTL_REQ BIT(0) ++#define MT_TXWI_ACK_CTL_NSEQ BIT(1) ++#define MT_TXWI_ACK_CTL_BA_WINDOW GENMASK(7, 2) ++ ++#define MT_TXWI_LEN_BYTE_CNT GENMASK(11, 0) ++#define MT_TXWI_LEN_PKTID GENMASK(15, 12) ++ ++#define MT_TXWI_CTL_TX_POWER_ADJ GENMASK(3, 0) ++#define MT_TXWI_CTL_CHAN_CHECK_PKT BIT(4) ++#define MT_TXWI_CTL_PIFS_REV BIT(6) ++ ++u32 mt76_mac_process_rx(struct mt7601u_dev *dev, struct sk_buff *skb, ++ u8 *data, void *rxi); ++int mt76_mac_wcid_set_key(struct mt7601u_dev *dev, u8 idx, ++ struct ieee80211_key_conf *key); ++void mt76_mac_wcid_set_rate(struct mt7601u_dev *dev, struct mt76_wcid *wcid, ++ const struct ieee80211_tx_rate *rate); ++ ++int mt76_mac_shared_key_setup(struct mt7601u_dev *dev, u8 vif_idx, u8 key_idx, ++ struct ieee80211_key_conf *key); ++u16 mt76_mac_tx_rate_val(struct mt7601u_dev *dev, ++ const struct ieee80211_tx_rate *rate, u8 *nss_val); ++struct mt76_tx_status ++mt7601u_mac_fetch_tx_status(struct mt7601u_dev *dev); ++void mt76_send_tx_status(struct mt7601u_dev *dev, struct mt76_tx_status *stat); ++ ++#endif +diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/main.c linux-rpi/drivers/net/wireless/mediatek/mt7601u/main.c +--- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/main.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/main.c 2015-11-29 09:42:38.887167260 +0100 +@@ -0,0 +1,413 @@ ++/* ++ * Copyright (C) 2014 Felix Fietkau ++ * Copyright (C) 2015 Jakub Kicinski ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 ++ * as published by the Free Software Foundation ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include "mt7601u.h" ++#include "mac.h" ++#include ++#include ++ ++static int mt7601u_start(struct ieee80211_hw *hw) ++{ ++ struct mt7601u_dev *dev = hw->priv; ++ int ret; ++ ++ mutex_lock(&dev->mutex); ++ ++ ret = mt7601u_mac_start(dev); ++ if (ret) ++ goto out; ++ ++ ieee80211_queue_delayed_work(dev->hw, &dev->mac_work, ++ MT_CALIBRATE_INTERVAL); ++ ieee80211_queue_delayed_work(dev->hw, &dev->cal_work, ++ MT_CALIBRATE_INTERVAL); ++out: ++ mutex_unlock(&dev->mutex); ++ return ret; ++} ++ ++static void mt7601u_stop(struct ieee80211_hw *hw) ++{ ++ struct mt7601u_dev *dev = hw->priv; ++ ++ mutex_lock(&dev->mutex); ++ ++ cancel_delayed_work_sync(&dev->cal_work); ++ cancel_delayed_work_sync(&dev->mac_work); ++ mt7601u_mac_stop(dev); ++ ++ mutex_unlock(&dev->mutex); ++} ++ ++static int mt7601u_add_interface(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif) ++{ ++ struct mt7601u_dev *dev = hw->priv; ++ struct mt76_vif *mvif = (struct mt76_vif *) vif->drv_priv; ++ unsigned int idx = 0; ++ unsigned int wcid = GROUP_WCID(idx); ++ ++ /* Note: for AP do the AP-STA things mt76 does: ++ * - beacon offsets ++ * - do mac address tricks ++ * - shift vif idx ++ */ ++ mvif->idx = idx; ++ ++ if (dev->wcid_mask[wcid / BITS_PER_LONG] & BIT(wcid % BITS_PER_LONG)) ++ return -ENOSPC; ++ dev->wcid_mask[wcid / BITS_PER_LONG] |= BIT(wcid % BITS_PER_LONG); ++ mvif->group_wcid.idx = wcid; ++ mvif->group_wcid.hw_key_idx = -1; ++ ++ return 0; ++} ++ ++static void mt7601u_remove_interface(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif) ++{ ++ struct mt7601u_dev *dev = hw->priv; ++ struct mt76_vif *mvif = (struct mt76_vif *) vif->drv_priv; ++ unsigned int wcid = mvif->group_wcid.idx; ++ ++ dev->wcid_mask[wcid / BITS_PER_LONG] &= ~BIT(wcid % BITS_PER_LONG); ++} ++ ++static int mt7601u_config(struct ieee80211_hw *hw, u32 changed) ++{ ++ struct mt7601u_dev *dev = hw->priv; ++ int ret = 0; ++ ++ mutex_lock(&dev->mutex); ++ ++ if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { ++ ieee80211_stop_queues(hw); ++ ret = mt7601u_phy_set_channel(dev, &hw->conf.chandef); ++ ieee80211_wake_queues(hw); ++ } ++ ++ mutex_unlock(&dev->mutex); ++ ++ return ret; ++} ++ ++static void ++mt76_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags, ++ unsigned int *total_flags, u64 multicast) ++{ ++ struct mt7601u_dev *dev = hw->priv; ++ u32 flags = 0; ++ ++#define MT76_FILTER(_flag, _hw) do { \ ++ flags |= *total_flags & FIF_##_flag; \ ++ dev->rxfilter &= ~(_hw); \ ++ dev->rxfilter |= !(flags & FIF_##_flag) * (_hw); \ ++ } while (0) ++ ++ mutex_lock(&dev->mutex); ++ ++ dev->rxfilter &= ~MT_RX_FILTR_CFG_OTHER_BSS; ++ ++ MT76_FILTER(OTHER_BSS, MT_RX_FILTR_CFG_PROMISC); ++ MT76_FILTER(FCSFAIL, MT_RX_FILTR_CFG_CRC_ERR); ++ MT76_FILTER(PLCPFAIL, MT_RX_FILTR_CFG_PHY_ERR); ++ MT76_FILTER(CONTROL, MT_RX_FILTR_CFG_ACK | ++ MT_RX_FILTR_CFG_CTS | ++ MT_RX_FILTR_CFG_CFEND | ++ MT_RX_FILTR_CFG_CFACK | ++ MT_RX_FILTR_CFG_BA | ++ MT_RX_FILTR_CFG_CTRL_RSV); ++ MT76_FILTER(PSPOLL, MT_RX_FILTR_CFG_PSPOLL); ++ ++ *total_flags = flags; ++ mt76_wr(dev, MT_RX_FILTR_CFG, dev->rxfilter); ++ ++ mutex_unlock(&dev->mutex); ++} ++ ++static void ++mt7601u_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif, ++ struct ieee80211_bss_conf *info, u32 changed) ++{ ++ struct mt7601u_dev *dev = hw->priv; ++ ++ mutex_lock(&dev->mutex); ++ ++ if (changed & BSS_CHANGED_ASSOC) ++ mt7601u_phy_con_cal_onoff(dev, info); ++ ++ if (changed & BSS_CHANGED_BSSID) { ++ mt7601u_addr_wr(dev, MT_MAC_BSSID_DW0, info->bssid); ++ ++ /* Note: this is a hack because beacon_int is not changed ++ * on leave nor is any more appropriate event generated. ++ * rt2x00 doesn't seem to be bothered though. ++ */ ++ if (is_zero_ether_addr(info->bssid)) ++ mt7601u_mac_config_tsf(dev, false, 0); ++ } ++ ++ if (changed & BSS_CHANGED_BASIC_RATES) { ++ mt7601u_wr(dev, MT_LEGACY_BASIC_RATE, info->basic_rates); ++ mt7601u_wr(dev, MT_HT_FBK_CFG0, 0x65432100); ++ mt7601u_wr(dev, MT_HT_FBK_CFG1, 0xedcba980); ++ mt7601u_wr(dev, MT_LG_FBK_CFG0, 0xedcba988); ++ mt7601u_wr(dev, MT_LG_FBK_CFG1, 0x00002100); ++ } ++ ++ if (changed & BSS_CHANGED_BEACON_INT) ++ mt7601u_mac_config_tsf(dev, true, info->beacon_int); ++ ++ if (changed & BSS_CHANGED_HT || changed & BSS_CHANGED_ERP_CTS_PROT) ++ mt7601u_mac_set_protection(dev, info->use_cts_prot, ++ info->ht_operation_mode); ++ ++ if (changed & BSS_CHANGED_ERP_PREAMBLE) ++ mt7601u_mac_set_short_preamble(dev, info->use_short_preamble); ++ ++ if (changed & BSS_CHANGED_ERP_SLOT) { ++ int slottime = info->use_short_slot ? 9 : 20; ++ ++ mt76_rmw_field(dev, MT_BKOFF_SLOT_CFG, ++ MT_BKOFF_SLOT_CFG_SLOTTIME, slottime); ++ } ++ ++ if (changed & BSS_CHANGED_ASSOC) ++ mt7601u_phy_recalibrate_after_assoc(dev); ++ ++ mutex_unlock(&dev->mutex); ++} ++ ++static int ++mt76_wcid_alloc(struct mt7601u_dev *dev) ++{ ++ int i, idx = 0; ++ ++ for (i = 0; i < ARRAY_SIZE(dev->wcid_mask); i++) { ++ idx = ffs(~dev->wcid_mask[i]); ++ if (!idx) ++ continue; ++ ++ idx--; ++ dev->wcid_mask[i] |= BIT(idx); ++ break; ++ } ++ ++ idx = i * BITS_PER_LONG + idx; ++ if (idx > 119) ++ return -1; ++ ++ return idx; ++} ++ ++static int ++mt7601u_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta) ++{ ++ struct mt7601u_dev *dev = hw->priv; ++ struct mt76_sta *msta = (struct mt76_sta *) sta->drv_priv; ++ struct mt76_vif *mvif = (struct mt76_vif *) vif->drv_priv; ++ int ret = 0; ++ int idx = 0; ++ ++ mutex_lock(&dev->mutex); ++ ++ idx = mt76_wcid_alloc(dev); ++ if (idx < 0) { ++ ret = -ENOSPC; ++ goto out; ++ } ++ ++ msta->wcid.idx = idx; ++ msta->wcid.hw_key_idx = -1; ++ mt7601u_mac_wcid_setup(dev, idx, mvif->idx, sta->addr); ++ mt76_clear(dev, MT_WCID_DROP(idx), MT_WCID_DROP_MASK(idx)); ++ rcu_assign_pointer(dev->wcid[idx], &msta->wcid); ++ mt7601u_mac_set_ampdu_factor(dev); ++ ++out: ++ mutex_unlock(&dev->mutex); ++ ++ return ret; ++} ++ ++static int ++mt7601u_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta) ++{ ++ struct mt7601u_dev *dev = hw->priv; ++ struct mt76_sta *msta = (struct mt76_sta *) sta->drv_priv; ++ int idx = msta->wcid.idx; ++ ++ mutex_lock(&dev->mutex); ++ rcu_assign_pointer(dev->wcid[idx], NULL); ++ mt76_set(dev, MT_WCID_DROP(idx), MT_WCID_DROP_MASK(idx)); ++ dev->wcid_mask[idx / BITS_PER_LONG] &= ~BIT(idx % BITS_PER_LONG); ++ mt7601u_mac_wcid_setup(dev, idx, 0, NULL); ++ mt7601u_mac_set_ampdu_factor(dev); ++ mutex_unlock(&dev->mutex); ++ ++ return 0; ++} ++ ++static void ++mt7601u_sta_notify(struct ieee80211_hw *hw, struct ieee80211_vif *vif, ++ enum sta_notify_cmd cmd, struct ieee80211_sta *sta) ++{ ++} ++ ++static void ++mt7601u_sw_scan(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif, ++ const u8 *mac_addr) ++{ ++ struct mt7601u_dev *dev = hw->priv; ++ ++ mt7601u_agc_save(dev); ++ set_bit(MT7601U_STATE_SCANNING, &dev->state); ++} ++ ++static void ++mt7601u_sw_scan_complete(struct ieee80211_hw *hw, ++ struct ieee80211_vif *vif) ++{ ++ struct mt7601u_dev *dev = hw->priv; ++ ++ mt7601u_agc_restore(dev); ++ clear_bit(MT7601U_STATE_SCANNING, &dev->state); ++} ++ ++static int ++mt7601u_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, ++ struct ieee80211_vif *vif, struct ieee80211_sta *sta, ++ struct ieee80211_key_conf *key) ++{ ++ struct mt7601u_dev *dev = hw->priv; ++ struct mt76_vif *mvif = (struct mt76_vif *) vif->drv_priv; ++ struct mt76_sta *msta = sta ? (struct mt76_sta *) sta->drv_priv : NULL; ++ struct mt76_wcid *wcid = msta ? &msta->wcid : &mvif->group_wcid; ++ int idx = key->keyidx; ++ int ret; ++ ++ if (cmd == SET_KEY) { ++ key->hw_key_idx = wcid->idx; ++ wcid->hw_key_idx = idx; ++ } else { ++ if (idx == wcid->hw_key_idx) ++ wcid->hw_key_idx = -1; ++ ++ key = NULL; ++ } ++ ++ if (!msta) { ++ if (key || wcid->hw_key_idx == idx) { ++ ret = mt76_mac_wcid_set_key(dev, wcid->idx, key); ++ if (ret) ++ return ret; ++ } ++ ++ return mt76_mac_shared_key_setup(dev, mvif->idx, idx, key); ++ } ++ ++ return mt76_mac_wcid_set_key(dev, msta->wcid.idx, key); ++} ++ ++static int mt7601u_set_rts_threshold(struct ieee80211_hw *hw, u32 value) ++{ ++ struct mt7601u_dev *dev = hw->priv; ++ ++ mt76_rmw_field(dev, MT_TX_RTS_CFG, MT_TX_RTS_CFG_THRESH, value); ++ ++ return 0; ++} ++ ++static int ++mt76_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, ++ enum ieee80211_ampdu_mlme_action action, ++ struct ieee80211_sta *sta, u16 tid, u16 *ssn, u8 buf_size) ++{ ++ struct mt7601u_dev *dev = hw->priv; ++ struct mt76_sta *msta = (struct mt76_sta *) sta->drv_priv; ++ ++ WARN_ON(msta->wcid.idx > GROUP_WCID(0)); ++ ++ switch (action) { ++ case IEEE80211_AMPDU_RX_START: ++ mt76_set(dev, MT_WCID_ADDR(msta->wcid.idx) + 4, BIT(16 + tid)); ++ break; ++ case IEEE80211_AMPDU_RX_STOP: ++ mt76_clear(dev, MT_WCID_ADDR(msta->wcid.idx) + 4, ++ BIT(16 + tid)); ++ break; ++ case IEEE80211_AMPDU_TX_OPERATIONAL: ++ ieee80211_send_bar(vif, sta->addr, tid, msta->agg_ssn[tid]); ++ break; ++ case IEEE80211_AMPDU_TX_STOP_FLUSH: ++ case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: ++ break; ++ case IEEE80211_AMPDU_TX_START: ++ msta->agg_ssn[tid] = *ssn << 4; ++ ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid); ++ break; ++ case IEEE80211_AMPDU_TX_STOP_CONT: ++ ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); ++ break; ++ } ++ ++ return 0; ++} ++ ++static void ++mt76_sta_rate_tbl_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif, ++ struct ieee80211_sta *sta) ++{ ++ struct mt7601u_dev *dev = hw->priv; ++ struct mt76_sta *msta = (struct mt76_sta *) sta->drv_priv; ++ struct ieee80211_sta_rates *rates; ++ struct ieee80211_tx_rate rate = {}; ++ ++ rcu_read_lock(); ++ rates = rcu_dereference(sta->rates); ++ ++ if (!rates) ++ goto out; ++ ++ rate.idx = rates->rate[0].idx; ++ rate.flags = rates->rate[0].flags; ++ mt76_mac_wcid_set_rate(dev, &msta->wcid, &rate); ++ ++out: ++ rcu_read_unlock(); ++} ++ ++const struct ieee80211_ops mt7601u_ops = { ++ .tx = mt7601u_tx, ++ .start = mt7601u_start, ++ .stop = mt7601u_stop, ++ .add_interface = mt7601u_add_interface, ++ .remove_interface = mt7601u_remove_interface, ++ .config = mt7601u_config, ++ .configure_filter = mt76_configure_filter, ++ .bss_info_changed = mt7601u_bss_info_changed, ++ .sta_add = mt7601u_sta_add, ++ .sta_remove = mt7601u_sta_remove, ++ .sta_notify = mt7601u_sta_notify, ++ .set_key = mt7601u_set_key, ++ .conf_tx = mt7601u_conf_tx, ++ .sw_scan_start = mt7601u_sw_scan, ++ .sw_scan_complete = mt7601u_sw_scan_complete, ++ .ampdu_action = mt76_ampdu_action, ++ .sta_rate_tbl_update = mt76_sta_rate_tbl_update, ++ .set_rts_threshold = mt7601u_set_rts_threshold, ++}; +diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/Makefile linux-rpi/drivers/net/wireless/mediatek/mt7601u/Makefile +--- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/Makefile 2015-11-29 09:42:38.887167260 +0100 +@@ -0,0 +1,9 @@ ++ccflags-y += -D__CHECK_ENDIAN__ ++ ++obj-$(CONFIG_MT7601U) += mt7601u.o ++ ++mt7601u-objs = \ ++ usb.o init.o main.o mcu.o trace.o dma.o core.o eeprom.o phy.o \ ++ mac.o util.o debugfs.o tx.o ++ ++CFLAGS_trace.o := -I$(src) +diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/mcu.c linux-rpi/drivers/net/wireless/mediatek/mt7601u/mcu.c +--- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/mcu.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/mcu.c 2015-11-29 09:42:38.887167260 +0100 +@@ -0,0 +1,534 @@ ++/* ++ * (c) Copyright 2002-2010, Ralink Technology, Inc. ++ * Copyright (C) 2014 Felix Fietkau ++ * Copyright (C) 2015 Jakub Kicinski ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 ++ * as published by the Free Software Foundation ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "mt7601u.h" ++#include "dma.h" ++#include "mcu.h" ++#include "usb.h" ++#include "trace.h" ++ ++#define MCU_FW_URB_MAX_PAYLOAD 0x3800 ++#define MCU_FW_URB_SIZE (MCU_FW_URB_MAX_PAYLOAD + 12) ++#define MCU_RESP_URB_SIZE 1024 ++ ++static inline int firmware_running(struct mt7601u_dev *dev) ++{ ++ return mt7601u_rr(dev, MT_MCU_COM_REG0) == 1; ++} ++ ++static inline void skb_put_le32(struct sk_buff *skb, u32 val) ++{ ++ put_unaligned_le32(val, skb_put(skb, 4)); ++} ++ ++static inline void mt7601u_dma_skb_wrap_cmd(struct sk_buff *skb, ++ u8 seq, enum mcu_cmd cmd) ++{ ++ WARN_ON(mt7601u_dma_skb_wrap(skb, CPU_TX_PORT, DMA_COMMAND, ++ MT76_SET(MT_TXD_CMD_INFO_SEQ, seq) | ++ MT76_SET(MT_TXD_CMD_INFO_TYPE, cmd))); ++} ++ ++static inline void trace_mt_mcu_msg_send_cs(struct mt7601u_dev *dev, ++ struct sk_buff *skb, bool need_resp) ++{ ++ u32 i, csum = 0; ++ ++ for (i = 0; i < skb->len / 4; i++) ++ csum ^= get_unaligned_le32(skb->data + i * 4); ++ ++ trace_mt_mcu_msg_send(dev, skb, csum, need_resp); ++} ++ ++static struct sk_buff * ++mt7601u_mcu_msg_alloc(struct mt7601u_dev *dev, const void *data, int len) ++{ ++ struct sk_buff *skb; ++ ++ WARN_ON(len % 4); /* if length is not divisible by 4 we need to pad */ ++ ++ skb = alloc_skb(len + MT_DMA_HDR_LEN + 4, GFP_KERNEL); ++ skb_reserve(skb, MT_DMA_HDR_LEN); ++ memcpy(skb_put(skb, len), data, len); ++ ++ return skb; ++} ++ ++static int mt7601u_mcu_wait_resp(struct mt7601u_dev *dev, u8 seq) ++{ ++ struct urb *urb = dev->mcu.resp.urb; ++ u32 rxfce; ++ int urb_status, ret, i = 5; ++ ++ while (i--) { ++ if (!wait_for_completion_timeout(&dev->mcu.resp_cmpl, ++ msecs_to_jiffies(300))) { ++ dev_warn(dev->dev, "Warning: %s retrying\n", __func__); ++ continue; ++ } ++ ++ /* Make copies of important data before reusing the urb */ ++ rxfce = get_unaligned_le32(dev->mcu.resp.buf); ++ urb_status = urb->status * mt7601u_urb_has_error(urb); ++ ++ ret = mt7601u_usb_submit_buf(dev, USB_DIR_IN, MT_EP_IN_CMD_RESP, ++ &dev->mcu.resp, GFP_KERNEL, ++ mt7601u_complete_urb, ++ &dev->mcu.resp_cmpl); ++ if (ret) ++ return ret; ++ ++ if (urb_status) ++ dev_err(dev->dev, "Error: MCU resp urb failed:%d\n", ++ urb_status); ++ ++ if (MT76_GET(MT_RXD_CMD_INFO_CMD_SEQ, rxfce) == seq && ++ MT76_GET(MT_RXD_CMD_INFO_EVT_TYPE, rxfce) == CMD_DONE) ++ return 0; ++ ++ dev_err(dev->dev, "Error: MCU resp evt:%hhx seq:%hhx-%hhx!\n", ++ MT76_GET(MT_RXD_CMD_INFO_EVT_TYPE, rxfce), ++ seq, MT76_GET(MT_RXD_CMD_INFO_CMD_SEQ, rxfce)); ++ } ++ ++ dev_err(dev->dev, "Error: %s timed out\n", __func__); ++ return -ETIMEDOUT; ++} ++ ++static int ++mt7601u_mcu_msg_send(struct mt7601u_dev *dev, struct sk_buff *skb, ++ enum mcu_cmd cmd, bool wait_resp) ++{ ++ struct usb_device *usb_dev = mt7601u_to_usb_dev(dev); ++ unsigned cmd_pipe = usb_sndbulkpipe(usb_dev, ++ dev->out_eps[MT_EP_OUT_INBAND_CMD]); ++ int sent, ret; ++ u8 seq = 0; ++ ++ if (test_bit(MT7601U_STATE_REMOVED, &dev->state)) ++ return 0; ++ ++ mutex_lock(&dev->mcu.mutex); ++ ++ if (wait_resp) ++ while (!seq) ++ seq = ++dev->mcu.msg_seq & 0xf; ++ ++ mt7601u_dma_skb_wrap_cmd(skb, seq, cmd); ++ ++ if (dev->mcu.resp_cmpl.done) ++ dev_err(dev->dev, "Error: MCU response pre-completed!\n"); ++ ++ trace_mt_mcu_msg_send_cs(dev, skb, wait_resp); ++ trace_mt_submit_urb_sync(dev, cmd_pipe, skb->len); ++ ret = usb_bulk_msg(usb_dev, cmd_pipe, skb->data, skb->len, &sent, 500); ++ if (ret) { ++ dev_err(dev->dev, "Error: send MCU cmd failed:%d\n", ret); ++ goto out; ++ } ++ if (sent != skb->len) ++ dev_err(dev->dev, "Error: %s sent != skb->len\n", __func__); ++ ++ if (wait_resp) ++ ret = mt7601u_mcu_wait_resp(dev, seq); ++out: ++ mutex_unlock(&dev->mcu.mutex); ++ ++ consume_skb(skb); ++ ++ return ret; ++} ++ ++static int mt7601u_mcu_function_select(struct mt7601u_dev *dev, ++ enum mcu_function func, u32 val) ++{ ++ struct sk_buff *skb; ++ struct { ++ __le32 id; ++ __le32 value; ++ } __packed __aligned(4) msg = { ++ .id = cpu_to_le32(func), ++ .value = cpu_to_le32(val), ++ }; ++ ++ skb = mt7601u_mcu_msg_alloc(dev, &msg, sizeof(msg)); ++ return mt7601u_mcu_msg_send(dev, skb, CMD_FUN_SET_OP, func == 5); ++} ++ ++int mt7601u_mcu_tssi_read_kick(struct mt7601u_dev *dev, int use_hvga) ++{ ++ int ret; ++ ++ if (!test_bit(MT7601U_STATE_MCU_RUNNING, &dev->state)) ++ return 0; ++ ++ ret = mt7601u_mcu_function_select(dev, ATOMIC_TSSI_SETTING, ++ use_hvga); ++ if (ret) { ++ dev_warn(dev->dev, "Warning: MCU TSSI read kick failed\n"); ++ return ret; ++ } ++ ++ dev->tssi_read_trig = true; ++ ++ return 0; ++} ++ ++int ++mt7601u_mcu_calibrate(struct mt7601u_dev *dev, enum mcu_calibrate cal, u32 val) ++{ ++ struct sk_buff *skb; ++ struct { ++ __le32 id; ++ __le32 value; ++ } __packed __aligned(4) msg = { ++ .id = cpu_to_le32(cal), ++ .value = cpu_to_le32(val), ++ }; ++ ++ skb = mt7601u_mcu_msg_alloc(dev, &msg, sizeof(msg)); ++ return mt7601u_mcu_msg_send(dev, skb, CMD_CALIBRATION_OP, true); ++} ++ ++int mt7601u_write_reg_pairs(struct mt7601u_dev *dev, u32 base, ++ const struct mt76_reg_pair *data, int n) ++{ ++ const int max_vals_per_cmd = INBAND_PACKET_MAX_LEN / 8; ++ struct sk_buff *skb; ++ int cnt, i, ret; ++ ++ if (!n) ++ return 0; ++ ++ cnt = min(max_vals_per_cmd, n); ++ ++ skb = alloc_skb(cnt * 8 + MT_DMA_HDR_LEN + 4, GFP_KERNEL); ++ if (!skb) ++ return -ENOMEM; ++ skb_reserve(skb, MT_DMA_HDR_LEN); ++ ++ for (i = 0; i < cnt; i++) { ++ skb_put_le32(skb, base + data[i].reg); ++ skb_put_le32(skb, data[i].value); ++ } ++ ++ ret = mt7601u_mcu_msg_send(dev, skb, CMD_RANDOM_WRITE, cnt == n); ++ if (ret) ++ return ret; ++ ++ return mt7601u_write_reg_pairs(dev, base, data + cnt, n - cnt); ++} ++ ++int mt7601u_burst_write_regs(struct mt7601u_dev *dev, u32 offset, ++ const u32 *data, int n) ++{ ++ const int max_regs_per_cmd = INBAND_PACKET_MAX_LEN / 4 - 1; ++ struct sk_buff *skb; ++ int cnt, i, ret; ++ ++ if (!n) ++ return 0; ++ ++ cnt = min(max_regs_per_cmd, n); ++ ++ skb = alloc_skb(cnt * 4 + MT_DMA_HDR_LEN + 4, GFP_KERNEL); ++ if (!skb) ++ return -ENOMEM; ++ skb_reserve(skb, MT_DMA_HDR_LEN); ++ ++ skb_put_le32(skb, MT_MCU_MEMMAP_WLAN + offset); ++ for (i = 0; i < cnt; i++) ++ skb_put_le32(skb, data[i]); ++ ++ ret = mt7601u_mcu_msg_send(dev, skb, CMD_BURST_WRITE, cnt == n); ++ if (ret) ++ return ret; ++ ++ return mt7601u_burst_write_regs(dev, offset + cnt * 4, ++ data + cnt, n - cnt); ++} ++ ++struct mt76_fw_header { ++ __le32 ilm_len; ++ __le32 dlm_len; ++ __le16 build_ver; ++ __le16 fw_ver; ++ u8 pad[4]; ++ char build_time[16]; ++}; ++ ++struct mt76_fw { ++ struct mt76_fw_header hdr; ++ u8 ivb[MT_MCU_IVB_SIZE]; ++ u8 ilm[]; ++}; ++ ++static int __mt7601u_dma_fw(struct mt7601u_dev *dev, ++ const struct mt7601u_dma_buf *dma_buf, ++ const void *data, u32 len, u32 dst_addr) ++{ ++ DECLARE_COMPLETION_ONSTACK(cmpl); ++ struct mt7601u_dma_buf buf = *dma_buf; /* we need to fake length */ ++ __le32 reg; ++ u32 val; ++ int ret; ++ ++ reg = cpu_to_le32(MT76_SET(MT_TXD_INFO_TYPE, DMA_PACKET) | ++ MT76_SET(MT_TXD_INFO_D_PORT, CPU_TX_PORT) | ++ MT76_SET(MT_TXD_INFO_LEN, len)); ++ memcpy(buf.buf, ®, sizeof(reg)); ++ memcpy(buf.buf + sizeof(reg), data, len); ++ memset(buf.buf + sizeof(reg) + len, 0, 8); ++ ++ ret = mt7601u_vendor_single_wr(dev, MT_VEND_WRITE_FCE, ++ MT_FCE_DMA_ADDR, dst_addr); ++ if (ret) ++ return ret; ++ len = roundup(len, 4); ++ ret = mt7601u_vendor_single_wr(dev, MT_VEND_WRITE_FCE, ++ MT_FCE_DMA_LEN, len << 16); ++ if (ret) ++ return ret; ++ ++ buf.len = MT_DMA_HDR_LEN + len + 4; ++ ret = mt7601u_usb_submit_buf(dev, USB_DIR_OUT, MT_EP_OUT_INBAND_CMD, ++ &buf, GFP_KERNEL, ++ mt7601u_complete_urb, &cmpl); ++ if (ret) ++ return ret; ++ ++ if (!wait_for_completion_timeout(&cmpl, msecs_to_jiffies(1000))) { ++ dev_err(dev->dev, "Error: firmware upload timed out\n"); ++ usb_kill_urb(buf.urb); ++ return -ETIMEDOUT; ++ } ++ if (mt7601u_urb_has_error(buf.urb)) { ++ dev_err(dev->dev, "Error: firmware upload urb failed:%d\n", ++ buf.urb->status); ++ return buf.urb->status; ++ } ++ ++ val = mt7601u_rr(dev, MT_TX_CPU_FROM_FCE_CPU_DESC_IDX); ++ val++; ++ mt7601u_wr(dev, MT_TX_CPU_FROM_FCE_CPU_DESC_IDX, val); ++ ++ return 0; ++} ++ ++static int ++mt7601u_dma_fw(struct mt7601u_dev *dev, struct mt7601u_dma_buf *dma_buf, ++ const void *data, int len, u32 dst_addr) ++{ ++ int n, ret; ++ ++ if (len == 0) ++ return 0; ++ ++ n = min(MCU_FW_URB_MAX_PAYLOAD, len); ++ ret = __mt7601u_dma_fw(dev, dma_buf, data, n, dst_addr); ++ if (ret) ++ return ret; ++ ++ if (!mt76_poll_msec(dev, MT_MCU_COM_REG1, BIT(31), BIT(31), 500)) ++ return -ETIMEDOUT; ++ ++ return mt7601u_dma_fw(dev, dma_buf, data + n, len - n, dst_addr + n); ++} ++ ++static int ++mt7601u_upload_firmware(struct mt7601u_dev *dev, const struct mt76_fw *fw) ++{ ++ struct mt7601u_dma_buf dma_buf; ++ void *ivb; ++ u32 ilm_len, dlm_len; ++ int i, ret; ++ ++ ivb = kmemdup(fw->ivb, sizeof(fw->ivb), GFP_KERNEL); ++ if (!ivb || mt7601u_usb_alloc_buf(dev, MCU_FW_URB_SIZE, &dma_buf)) { ++ ret = -ENOMEM; ++ goto error; ++ } ++ ++ ilm_len = le32_to_cpu(fw->hdr.ilm_len) - sizeof(fw->ivb); ++ dev_dbg(dev->dev, "loading FW - ILM %u + IVB %zu\n", ++ ilm_len, sizeof(fw->ivb)); ++ ret = mt7601u_dma_fw(dev, &dma_buf, fw->ilm, ilm_len, sizeof(fw->ivb)); ++ if (ret) ++ goto error; ++ ++ dlm_len = le32_to_cpu(fw->hdr.dlm_len); ++ dev_dbg(dev->dev, "loading FW - DLM %u\n", dlm_len); ++ ret = mt7601u_dma_fw(dev, &dma_buf, fw->ilm + ilm_len, ++ dlm_len, MT_MCU_DLM_OFFSET); ++ if (ret) ++ goto error; ++ ++ ret = mt7601u_vendor_request(dev, MT_VEND_DEV_MODE, USB_DIR_OUT, ++ 0x12, 0, ivb, sizeof(fw->ivb)); ++ if (ret < 0) ++ goto error; ++ ret = 0; ++ ++ for (i = 100; i && !firmware_running(dev); i--) ++ msleep(10); ++ if (!i) { ++ ret = -ETIMEDOUT; ++ goto error; ++ } ++ ++ dev_dbg(dev->dev, "Firmware running!\n"); ++error: ++ kfree(ivb); ++ mt7601u_usb_free_buf(dev, &dma_buf); ++ ++ return ret; ++} ++ ++static int mt7601u_load_firmware(struct mt7601u_dev *dev) ++{ ++ const struct firmware *fw; ++ const struct mt76_fw_header *hdr; ++ int len, ret; ++ u32 val; ++ ++ mt7601u_wr(dev, MT_USB_DMA_CFG, (MT_USB_DMA_CFG_RX_BULK_EN | ++ MT_USB_DMA_CFG_TX_BULK_EN)); ++ ++ if (firmware_running(dev)) ++ return 0; ++ ++ ret = request_firmware(&fw, MT7601U_FIRMWARE, dev->dev); ++ if (ret) ++ return ret; ++ ++ if (!fw || !fw->data || fw->size < sizeof(*hdr)) ++ goto err_inv_fw; ++ ++ hdr = (const struct mt76_fw_header *) fw->data; ++ ++ if (le32_to_cpu(hdr->ilm_len) <= MT_MCU_IVB_SIZE) ++ goto err_inv_fw; ++ ++ len = sizeof(*hdr); ++ len += le32_to_cpu(hdr->ilm_len); ++ len += le32_to_cpu(hdr->dlm_len); ++ ++ if (fw->size != len) ++ goto err_inv_fw; ++ ++ val = le16_to_cpu(hdr->fw_ver); ++ dev_info(dev->dev, ++ "Firmware Version: %d.%d.%02d Build: %x Build time: %.16s\n", ++ (val >> 12) & 0xf, (val >> 8) & 0xf, val & 0xf, ++ le16_to_cpu(hdr->build_ver), hdr->build_time); ++ ++ len = le32_to_cpu(hdr->ilm_len); ++ ++ mt7601u_wr(dev, 0x94c, 0); ++ mt7601u_wr(dev, MT_FCE_PSE_CTRL, 0); ++ ++ mt7601u_vendor_reset(dev); ++ msleep(5); ++ ++ mt7601u_wr(dev, 0xa44, 0); ++ mt7601u_wr(dev, 0x230, 0x84210); ++ mt7601u_wr(dev, 0x400, 0x80c00); ++ mt7601u_wr(dev, 0x800, 1); ++ ++ mt7601u_rmw(dev, MT_PBF_CFG, 0, (MT_PBF_CFG_TX0Q_EN | ++ MT_PBF_CFG_TX1Q_EN | ++ MT_PBF_CFG_TX2Q_EN | ++ MT_PBF_CFG_TX3Q_EN)); ++ ++ mt7601u_wr(dev, MT_FCE_PSE_CTRL, 1); ++ ++ mt7601u_wr(dev, MT_USB_DMA_CFG, (MT_USB_DMA_CFG_RX_BULK_EN | ++ MT_USB_DMA_CFG_TX_BULK_EN)); ++ val = mt76_set(dev, MT_USB_DMA_CFG, MT_USB_DMA_CFG_TX_CLR); ++ val &= ~MT_USB_DMA_CFG_TX_CLR; ++ mt7601u_wr(dev, MT_USB_DMA_CFG, val); ++ ++ /* FCE tx_fs_base_ptr */ ++ mt7601u_wr(dev, MT_TX_CPU_FROM_FCE_BASE_PTR, 0x400230); ++ /* FCE tx_fs_max_cnt */ ++ mt7601u_wr(dev, MT_TX_CPU_FROM_FCE_MAX_COUNT, 1); ++ /* FCE pdma enable */ ++ mt7601u_wr(dev, MT_FCE_PDMA_GLOBAL_CONF, 0x44); ++ /* FCE skip_fs_en */ ++ mt7601u_wr(dev, MT_FCE_SKIP_FS, 3); ++ ++ ret = mt7601u_upload_firmware(dev, (const struct mt76_fw *)fw->data); ++ ++ release_firmware(fw); ++ ++ return ret; ++ ++err_inv_fw: ++ dev_err(dev->dev, "Invalid firmware image\n"); ++ release_firmware(fw); ++ return -ENOENT; ++} ++ ++int mt7601u_mcu_init(struct mt7601u_dev *dev) ++{ ++ int ret; ++ ++ mutex_init(&dev->mcu.mutex); ++ ++ ret = mt7601u_load_firmware(dev); ++ if (ret) ++ return ret; ++ ++ set_bit(MT7601U_STATE_MCU_RUNNING, &dev->state); ++ ++ return 0; ++} ++ ++int mt7601u_mcu_cmd_init(struct mt7601u_dev *dev) ++{ ++ int ret; ++ ++ ret = mt7601u_mcu_function_select(dev, Q_SELECT, 1); ++ if (ret) ++ return ret; ++ ++ init_completion(&dev->mcu.resp_cmpl); ++ if (mt7601u_usb_alloc_buf(dev, MCU_RESP_URB_SIZE, &dev->mcu.resp)) { ++ mt7601u_usb_free_buf(dev, &dev->mcu.resp); ++ return -ENOMEM; ++ } ++ ++ ret = mt7601u_usb_submit_buf(dev, USB_DIR_IN, MT_EP_IN_CMD_RESP, ++ &dev->mcu.resp, GFP_KERNEL, ++ mt7601u_complete_urb, &dev->mcu.resp_cmpl); ++ if (ret) { ++ mt7601u_usb_free_buf(dev, &dev->mcu.resp); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++void mt7601u_mcu_cmd_deinit(struct mt7601u_dev *dev) ++{ ++ usb_kill_urb(dev->mcu.resp.urb); ++ mt7601u_usb_free_buf(dev, &dev->mcu.resp); ++} +diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/mcu.h linux-rpi/drivers/net/wireless/mediatek/mt7601u/mcu.h +--- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/mcu.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/mcu.h 2015-11-29 09:42:38.887167260 +0100 +@@ -0,0 +1,94 @@ ++/* ++ * Copyright (C) 2014 Felix Fietkau ++ * Copyright (C) 2015 Jakub Kicinski ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 ++ * as published by the Free Software Foundation ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef __MT7601U_MCU_H ++#define __MT7601U_MCU_H ++ ++struct mt7601u_dev; ++ ++/* Register definitions */ ++#define MT_MCU_RESET_CTL 0x070C ++#define MT_MCU_INT_LEVEL 0x0718 ++#define MT_MCU_COM_REG0 0x0730 ++#define MT_MCU_COM_REG1 0x0734 ++#define MT_MCU_COM_REG2 0x0738 ++#define MT_MCU_COM_REG3 0x073C ++ ++#define MT_MCU_IVB_SIZE 0x40 ++#define MT_MCU_DLM_OFFSET 0x80000 ++ ++#define MT_MCU_MEMMAP_WLAN 0x00410000 ++#define MT_MCU_MEMMAP_BBP 0x40000000 ++#define MT_MCU_MEMMAP_RF 0x80000000 ++ ++#define INBAND_PACKET_MAX_LEN 192 ++ ++enum mcu_cmd { ++ CMD_FUN_SET_OP = 1, ++ CMD_LOAD_CR = 2, ++ CMD_INIT_GAIN_OP = 3, ++ CMD_DYNC_VGA_OP = 6, ++ CMD_TDLS_CH_SW = 7, ++ CMD_BURST_WRITE = 8, ++ CMD_READ_MODIFY_WRITE = 9, ++ CMD_RANDOM_READ = 10, ++ CMD_BURST_READ = 11, ++ CMD_RANDOM_WRITE = 12, ++ CMD_LED_MODE_OP = 16, ++ CMD_POWER_SAVING_OP = 20, ++ CMD_WOW_CONFIG = 21, ++ CMD_WOW_QUERY = 22, ++ CMD_WOW_FEATURE = 24, ++ CMD_CARRIER_DETECT_OP = 28, ++ CMD_RADOR_DETECT_OP = 29, ++ CMD_SWITCH_CHANNEL_OP = 30, ++ CMD_CALIBRATION_OP = 31, ++ CMD_BEACON_OP = 32, ++ CMD_ANTENNA_OP = 33, ++}; ++ ++enum mcu_function { ++ Q_SELECT = 1, ++ ATOMIC_TSSI_SETTING = 5, ++}; ++ ++enum mcu_power_mode { ++ RADIO_OFF = 0x30, ++ RADIO_ON = 0x31, ++ RADIO_OFF_AUTO_WAKEUP = 0x32, ++ RADIO_OFF_ADVANCE = 0x33, ++ RADIO_ON_ADVANCE = 0x34, ++}; ++ ++enum mcu_calibrate { ++ MCU_CAL_R = 1, ++ MCU_CAL_DCOC, ++ MCU_CAL_LC, ++ MCU_CAL_LOFT, ++ MCU_CAL_TXIQ, ++ MCU_CAL_BW, ++ MCU_CAL_DPD, ++ MCU_CAL_RXIQ, ++ MCU_CAL_TXDCOC, ++}; ++ ++int mt7601u_mcu_init(struct mt7601u_dev *dev); ++int mt7601u_mcu_cmd_init(struct mt7601u_dev *dev); ++void mt7601u_mcu_cmd_deinit(struct mt7601u_dev *dev); ++ ++int ++mt7601u_mcu_calibrate(struct mt7601u_dev *dev, enum mcu_calibrate cal, u32 val); ++int mt7601u_mcu_tssi_read_kick(struct mt7601u_dev *dev, int use_hvga); ++ ++#endif +diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/mt7601u.h linux-rpi/drivers/net/wireless/mediatek/mt7601u/mt7601u.h +--- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/mt7601u.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/mt7601u.h 2015-11-29 09:42:38.887167260 +0100 +@@ -0,0 +1,396 @@ ++/* ++ * Copyright (C) 2014 Felix Fietkau ++ * Copyright (C) 2015 Jakub Kicinski ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 ++ * as published by the Free Software Foundation ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef MT7601U_H ++#define MT7601U_H ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "regs.h" ++#include "util.h" ++ ++#define MT_CALIBRATE_INTERVAL (4 * HZ) ++ ++#define MT_FREQ_CAL_INIT_DELAY (30 * HZ) ++#define MT_FREQ_CAL_CHECK_INTERVAL (10 * HZ) ++#define MT_FREQ_CAL_ADJ_INTERVAL (HZ / 2) ++ ++#define MT_BBP_REG_VERSION 0x00 ++ ++#define MT_USB_AGGR_SIZE_LIMIT 28 /* * 1024B */ ++#define MT_USB_AGGR_TIMEOUT 0x80 /* * 33ns */ ++#define MT_RX_ORDER 3 ++#define MT_RX_URB_SIZE (PAGE_SIZE << MT_RX_ORDER) ++ ++struct mt7601u_dma_buf { ++ struct urb *urb; ++ void *buf; ++ dma_addr_t dma; ++ size_t len; ++}; ++ ++struct mt7601u_mcu { ++ struct mutex mutex; ++ ++ u8 msg_seq; ++ ++ struct mt7601u_dma_buf resp; ++ struct completion resp_cmpl; ++}; ++ ++struct mt7601u_freq_cal { ++ struct delayed_work work; ++ u8 freq; ++ bool enabled; ++ bool adjusting; ++}; ++ ++struct mac_stats { ++ u64 rx_stat[6]; ++ u64 tx_stat[6]; ++ u64 aggr_stat[2]; ++ u64 aggr_n[32]; ++ u64 zero_len_del[2]; ++}; ++ ++#define N_RX_ENTRIES 16 ++struct mt7601u_rx_queue { ++ struct mt7601u_dev *dev; ++ ++ struct mt7601u_dma_buf_rx { ++ struct urb *urb; ++ struct page *p; ++ } e[N_RX_ENTRIES]; ++ ++ unsigned int start; ++ unsigned int end; ++ unsigned int entries; ++ unsigned int pending; ++}; ++ ++#define N_TX_ENTRIES 64 ++ ++struct mt7601u_tx_queue { ++ struct mt7601u_dev *dev; ++ ++ struct mt7601u_dma_buf_tx { ++ struct urb *urb; ++ struct sk_buff *skb; ++ } e[N_TX_ENTRIES]; ++ ++ unsigned int start; ++ unsigned int end; ++ unsigned int entries; ++ unsigned int used; ++ unsigned int fifo_seq; ++}; ++ ++/* WCID allocation: ++ * 0: mcast wcid ++ * 1: bssid wcid ++ * 1...: STAs ++ * ...7e: group wcids ++ * 7f: reserved ++ */ ++#define N_WCIDS 128 ++#define GROUP_WCID(idx) (N_WCIDS - 2 - idx) ++ ++struct mt7601u_eeprom_params; ++ ++#define MT_EE_TEMPERATURE_SLOPE 39 ++#define MT_FREQ_OFFSET_INVALID -128 ++ ++enum mt_temp_mode { ++ MT_TEMP_MODE_NORMAL, ++ MT_TEMP_MODE_HIGH, ++ MT_TEMP_MODE_LOW, ++}; ++ ++enum mt_bw { ++ MT_BW_20, ++ MT_BW_40, ++}; ++ ++enum { ++ MT7601U_STATE_INITIALIZED, ++ MT7601U_STATE_REMOVED, ++ MT7601U_STATE_WLAN_RUNNING, ++ MT7601U_STATE_MCU_RUNNING, ++ MT7601U_STATE_SCANNING, ++ MT7601U_STATE_READING_STATS, ++ MT7601U_STATE_MORE_STATS, ++}; ++ ++/** ++ * struct mt7601u_dev - adapter structure ++ * @lock: protects @wcid->tx_rate. ++ * @mac_lock: locks out mac80211's tx status and rx paths. ++ * @tx_lock: protects @tx_q and changes of MT7601U_STATE_*_STATS ++ * flags in @state. ++ * @rx_lock: protects @rx_q. ++ * @con_mon_lock: protects @ap_bssid, @bcn_*, @avg_rssi. ++ * @mutex: ensures exclusive access from mac80211 callbacks. ++ * @vendor_req_mutex: protects @vend_buf, ensures atomicity of split writes. ++ * @reg_atomic_mutex: ensures atomicity of indirect register accesses ++ * (accesses to RF and BBP). ++ * @hw_atomic_mutex: ensures exclusive access to HW during critical ++ * operations (power management, channel switch). ++ */ ++struct mt7601u_dev { ++ struct ieee80211_hw *hw; ++ struct device *dev; ++ ++ unsigned long state; ++ ++ struct mutex mutex; ++ ++ unsigned long wcid_mask[N_WCIDS / BITS_PER_LONG]; ++ ++ struct cfg80211_chan_def chandef; ++ struct ieee80211_supported_band *sband_2g; ++ ++ struct mt7601u_mcu mcu; ++ ++ struct delayed_work cal_work; ++ struct delayed_work mac_work; ++ ++ struct workqueue_struct *stat_wq; ++ struct delayed_work stat_work; ++ ++ struct mt76_wcid *mon_wcid; ++ struct mt76_wcid __rcu *wcid[N_WCIDS]; ++ ++ spinlock_t lock; ++ spinlock_t mac_lock; ++ ++ const u16 *beacon_offsets; ++ ++ u8 macaddr[ETH_ALEN]; ++ struct mt7601u_eeprom_params *ee; ++ ++ struct mutex vendor_req_mutex; ++ void *vend_buf; ++ ++ struct mutex reg_atomic_mutex; ++ struct mutex hw_atomic_mutex; ++ ++ u32 rxfilter; ++ u32 debugfs_reg; ++ ++ u8 out_eps[8]; ++ u8 in_eps[8]; ++ u16 out_max_packet; ++ u16 in_max_packet; ++ ++ /* TX */ ++ spinlock_t tx_lock; ++ struct tasklet_struct tx_tasklet; ++ struct mt7601u_tx_queue *tx_q; ++ struct sk_buff_head tx_skb_done; ++ ++ atomic_t avg_ampdu_len; ++ ++ /* RX */ ++ spinlock_t rx_lock; ++ struct tasklet_struct rx_tasklet; ++ struct mt7601u_rx_queue rx_q; ++ ++ /* Connection monitoring things */ ++ spinlock_t con_mon_lock; ++ u8 ap_bssid[ETH_ALEN]; ++ ++ s8 bcn_freq_off; ++ u8 bcn_phy_mode; ++ ++ int avg_rssi; /* starts at 0 and converges */ ++ ++ u8 agc_save; ++ ++ struct mt7601u_freq_cal freq_cal; ++ ++ bool tssi_read_trig; ++ ++ s8 tssi_init; ++ s8 tssi_init_hvga; ++ s16 tssi_init_hvga_offset_db; ++ ++ int prev_pwr_diff; ++ ++ enum mt_temp_mode temp_mode; ++ int curr_temp; ++ int dpd_temp; ++ s8 raw_temp; ++ bool pll_lock_protect; ++ ++ u8 bw; ++ bool chan_ext_below; ++ ++ /* PA mode */ ++ u32 rf_pa_mode[2]; ++ ++ struct mac_stats stats; ++}; ++ ++struct mt7601u_tssi_params { ++ char tssi0; ++ int trgt_power; ++}; ++ ++struct mt76_wcid { ++ u8 idx; ++ u8 hw_key_idx; ++ ++ u16 tx_rate; ++ bool tx_rate_set; ++ u8 tx_rate_nss; ++}; ++ ++struct mt76_vif { ++ u8 idx; ++ ++ struct mt76_wcid group_wcid; ++}; ++ ++struct mt76_sta { ++ struct mt76_wcid wcid; ++ u16 agg_ssn[IEEE80211_NUM_TIDS]; ++}; ++ ++struct mt76_reg_pair { ++ u32 reg; ++ u32 value; ++}; ++ ++struct mt7601u_rxwi; ++ ++extern const struct ieee80211_ops mt7601u_ops; ++ ++void mt7601u_init_debugfs(struct mt7601u_dev *dev); ++ ++u32 mt7601u_rr(struct mt7601u_dev *dev, u32 offset); ++void mt7601u_wr(struct mt7601u_dev *dev, u32 offset, u32 val); ++u32 mt7601u_rmw(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val); ++u32 mt7601u_rmc(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val); ++void mt7601u_wr_copy(struct mt7601u_dev *dev, u32 offset, ++ const void *data, int len); ++ ++int mt7601u_wait_asic_ready(struct mt7601u_dev *dev); ++bool mt76_poll(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val, ++ int timeout); ++bool mt76_poll_msec(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val, ++ int timeout); ++ ++/* Compatibility with mt76 */ ++#define mt76_rmw_field(_dev, _reg, _field, _val) \ ++ mt76_rmw(_dev, _reg, _field, MT76_SET(_field, _val)) ++ ++static inline u32 mt76_rr(struct mt7601u_dev *dev, u32 offset) ++{ ++ return mt7601u_rr(dev, offset); ++} ++ ++static inline void mt76_wr(struct mt7601u_dev *dev, u32 offset, u32 val) ++{ ++ return mt7601u_wr(dev, offset, val); ++} ++ ++static inline u32 ++mt76_rmw(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val) ++{ ++ return mt7601u_rmw(dev, offset, mask, val); ++} ++ ++static inline u32 mt76_set(struct mt7601u_dev *dev, u32 offset, u32 val) ++{ ++ return mt76_rmw(dev, offset, 0, val); ++} ++ ++static inline u32 mt76_clear(struct mt7601u_dev *dev, u32 offset, u32 val) ++{ ++ return mt76_rmw(dev, offset, val, 0); ++} ++ ++int mt7601u_write_reg_pairs(struct mt7601u_dev *dev, u32 base, ++ const struct mt76_reg_pair *data, int len); ++int mt7601u_burst_write_regs(struct mt7601u_dev *dev, u32 offset, ++ const u32 *data, int n); ++void mt7601u_addr_wr(struct mt7601u_dev *dev, const u32 offset, const u8 *addr); ++ ++/* Init */ ++struct mt7601u_dev *mt7601u_alloc_device(struct device *dev); ++int mt7601u_init_hardware(struct mt7601u_dev *dev); ++int mt7601u_register_device(struct mt7601u_dev *dev); ++void mt7601u_cleanup(struct mt7601u_dev *dev); ++ ++int mt7601u_mac_start(struct mt7601u_dev *dev); ++void mt7601u_mac_stop(struct mt7601u_dev *dev); ++ ++/* PHY */ ++int mt7601u_phy_init(struct mt7601u_dev *dev); ++int mt7601u_wait_bbp_ready(struct mt7601u_dev *dev); ++void mt7601u_set_rx_path(struct mt7601u_dev *dev, u8 path); ++void mt7601u_set_tx_dac(struct mt7601u_dev *dev, u8 path); ++int mt7601u_bbp_set_bw(struct mt7601u_dev *dev, int bw); ++void mt7601u_agc_save(struct mt7601u_dev *dev); ++void mt7601u_agc_restore(struct mt7601u_dev *dev); ++int mt7601u_phy_set_channel(struct mt7601u_dev *dev, ++ struct cfg80211_chan_def *chandef); ++void mt7601u_phy_recalibrate_after_assoc(struct mt7601u_dev *dev); ++int mt7601u_phy_get_rssi(struct mt7601u_dev *dev, ++ struct mt7601u_rxwi *rxwi, u16 rate); ++void mt7601u_phy_con_cal_onoff(struct mt7601u_dev *dev, ++ struct ieee80211_bss_conf *info); ++ ++/* MAC */ ++void mt7601u_mac_work(struct work_struct *work); ++void mt7601u_mac_set_protection(struct mt7601u_dev *dev, bool legacy_prot, ++ int ht_mode); ++void mt7601u_mac_set_short_preamble(struct mt7601u_dev *dev, bool short_preamb); ++void mt7601u_mac_config_tsf(struct mt7601u_dev *dev, bool enable, int interval); ++void ++mt7601u_mac_wcid_setup(struct mt7601u_dev *dev, u8 idx, u8 vif_idx, u8 *mac); ++void mt7601u_mac_set_ampdu_factor(struct mt7601u_dev *dev); ++ ++/* TX */ ++void mt7601u_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control, ++ struct sk_buff *skb); ++int mt7601u_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, ++ u16 queue, const struct ieee80211_tx_queue_params *params); ++void mt7601u_tx_status(struct mt7601u_dev *dev, struct sk_buff *skb); ++void mt7601u_tx_stat(struct work_struct *work); ++ ++/* util */ ++void mt76_remove_hdr_pad(struct sk_buff *skb); ++int mt76_insert_hdr_pad(struct sk_buff *skb); ++ ++u32 mt7601u_bbp_set_ctrlch(struct mt7601u_dev *dev, bool below); ++ ++static inline u32 mt7601u_mac_set_ctrlch(struct mt7601u_dev *dev, bool below) ++{ ++ return mt7601u_rmc(dev, MT_TX_BAND_CFG, 1, below); ++} ++ ++int mt7601u_dma_init(struct mt7601u_dev *dev); ++void mt7601u_dma_cleanup(struct mt7601u_dev *dev); ++ ++int mt7601u_dma_enqueue_tx(struct mt7601u_dev *dev, struct sk_buff *skb, ++ struct mt76_wcid *wcid, int hw_q); ++ ++#endif +diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/phy.c linux-rpi/drivers/net/wireless/mediatek/mt7601u/phy.c +--- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/phy.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/phy.c 2015-11-29 09:42:38.887167260 +0100 +@@ -0,0 +1,1251 @@ ++/* ++ * (c) Copyright 2002-2010, Ralink Technology, Inc. ++ * Copyright (C) 2014 Felix Fietkau ++ * Copyright (C) 2015 Jakub Kicinski ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 ++ * as published by the Free Software Foundation ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include "mt7601u.h" ++#include "mcu.h" ++#include "eeprom.h" ++#include "trace.h" ++#include "initvals_phy.h" ++ ++#include ++ ++static void mt7601u_agc_reset(struct mt7601u_dev *dev); ++ ++static int ++mt7601u_rf_wr(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 value) ++{ ++ int ret = 0; ++ ++ if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state)) || ++ WARN_ON(offset > 63)) ++ return -EINVAL; ++ if (test_bit(MT7601U_STATE_REMOVED, &dev->state)) ++ return 0; ++ ++ mutex_lock(&dev->reg_atomic_mutex); ++ ++ if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100)) { ++ ret = -ETIMEDOUT; ++ goto out; ++ } ++ ++ mt7601u_wr(dev, MT_RF_CSR_CFG, MT76_SET(MT_RF_CSR_CFG_DATA, value) | ++ MT76_SET(MT_RF_CSR_CFG_REG_BANK, bank) | ++ MT76_SET(MT_RF_CSR_CFG_REG_ID, offset) | ++ MT_RF_CSR_CFG_WR | ++ MT_RF_CSR_CFG_KICK); ++ trace_rf_write(dev, bank, offset, value); ++out: ++ mutex_unlock(&dev->reg_atomic_mutex); ++ ++ if (ret < 0) ++ dev_err(dev->dev, "Error: RF write %02hhx:%02hhx failed:%d!!\n", ++ bank, offset, ret); ++ ++ return ret; ++} ++ ++static int ++mt7601u_rf_rr(struct mt7601u_dev *dev, u8 bank, u8 offset) ++{ ++ int ret = -ETIMEDOUT; ++ u32 val; ++ ++ if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state)) || ++ WARN_ON(offset > 63)) ++ return -EINVAL; ++ if (test_bit(MT7601U_STATE_REMOVED, &dev->state)) ++ return 0xff; ++ ++ mutex_lock(&dev->reg_atomic_mutex); ++ ++ if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100)) ++ goto out; ++ ++ mt7601u_wr(dev, MT_RF_CSR_CFG, MT76_SET(MT_RF_CSR_CFG_REG_BANK, bank) | ++ MT76_SET(MT_RF_CSR_CFG_REG_ID, offset) | ++ MT_RF_CSR_CFG_KICK); ++ ++ if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100)) ++ goto out; ++ ++ val = mt7601u_rr(dev, MT_RF_CSR_CFG); ++ if (MT76_GET(MT_RF_CSR_CFG_REG_ID, val) == offset && ++ MT76_GET(MT_RF_CSR_CFG_REG_BANK, val) == bank) { ++ ret = MT76_GET(MT_RF_CSR_CFG_DATA, val); ++ trace_rf_read(dev, bank, offset, ret); ++ } ++out: ++ mutex_unlock(&dev->reg_atomic_mutex); ++ ++ if (ret < 0) ++ dev_err(dev->dev, "Error: RF read %02hhx:%02hhx failed:%d!!\n", ++ bank, offset, ret); ++ ++ return ret; ++} ++ ++static int ++mt7601u_rf_rmw(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 mask, u8 val) ++{ ++ int ret; ++ ++ ret = mt7601u_rf_rr(dev, bank, offset); ++ if (ret < 0) ++ return ret; ++ val |= ret & ~mask; ++ ret = mt7601u_rf_wr(dev, bank, offset, val); ++ if (ret) ++ return ret; ++ ++ return val; ++} ++ ++static int ++mt7601u_rf_set(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 val) ++{ ++ return mt7601u_rf_rmw(dev, bank, offset, 0, val); ++} ++ ++static int ++mt7601u_rf_clear(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 mask) ++{ ++ return mt7601u_rf_rmw(dev, bank, offset, mask, 0); ++} ++ ++static void mt7601u_bbp_wr(struct mt7601u_dev *dev, u8 offset, u8 val) ++{ ++ if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state)) || ++ test_bit(MT7601U_STATE_REMOVED, &dev->state)) ++ return; ++ ++ mutex_lock(&dev->reg_atomic_mutex); ++ ++ if (!mt76_poll(dev, MT_BBP_CSR_CFG, MT_BBP_CSR_CFG_BUSY, 0, 1000)) { ++ dev_err(dev->dev, "Error: BBP write %02hhx failed!!\n", offset); ++ goto out; ++ } ++ ++ mt7601u_wr(dev, MT_BBP_CSR_CFG, ++ MT76_SET(MT_BBP_CSR_CFG_VAL, val) | ++ MT76_SET(MT_BBP_CSR_CFG_REG_NUM, offset) | ++ MT_BBP_CSR_CFG_RW_MODE | MT_BBP_CSR_CFG_BUSY); ++ trace_bbp_write(dev, offset, val); ++out: ++ mutex_unlock(&dev->reg_atomic_mutex); ++} ++ ++static int mt7601u_bbp_rr(struct mt7601u_dev *dev, u8 offset) ++{ ++ u32 val; ++ int ret = -ETIMEDOUT; ++ ++ if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state))) ++ return -EINVAL; ++ if (test_bit(MT7601U_STATE_REMOVED, &dev->state)) ++ return 0xff; ++ ++ mutex_lock(&dev->reg_atomic_mutex); ++ ++ if (!mt76_poll(dev, MT_BBP_CSR_CFG, MT_BBP_CSR_CFG_BUSY, 0, 1000)) ++ goto out; ++ ++ mt7601u_wr(dev, MT_BBP_CSR_CFG, ++ MT76_SET(MT_BBP_CSR_CFG_REG_NUM, offset) | ++ MT_BBP_CSR_CFG_RW_MODE | MT_BBP_CSR_CFG_BUSY | ++ MT_BBP_CSR_CFG_READ); ++ ++ if (!mt76_poll(dev, MT_BBP_CSR_CFG, MT_BBP_CSR_CFG_BUSY, 0, 1000)) ++ goto out; ++ ++ val = mt7601u_rr(dev, MT_BBP_CSR_CFG); ++ if (MT76_GET(MT_BBP_CSR_CFG_REG_NUM, val) == offset) { ++ ret = MT76_GET(MT_BBP_CSR_CFG_VAL, val); ++ trace_bbp_read(dev, offset, ret); ++ } ++out: ++ mutex_unlock(&dev->reg_atomic_mutex); ++ ++ if (ret < 0) ++ dev_err(dev->dev, "Error: BBP read %02hhx failed:%d!!\n", ++ offset, ret); ++ ++ return ret; ++} ++ ++static int mt7601u_bbp_rmw(struct mt7601u_dev *dev, u8 offset, u8 mask, u8 val) ++{ ++ int ret; ++ ++ ret = mt7601u_bbp_rr(dev, offset); ++ if (ret < 0) ++ return ret; ++ val |= ret & ~mask; ++ mt7601u_bbp_wr(dev, offset, val); ++ ++ return val; ++} ++ ++static u8 mt7601u_bbp_rmc(struct mt7601u_dev *dev, u8 offset, u8 mask, u8 val) ++{ ++ int ret; ++ ++ ret = mt7601u_bbp_rr(dev, offset); ++ if (ret < 0) ++ return ret; ++ val |= ret & ~mask; ++ if (ret != val) ++ mt7601u_bbp_wr(dev, offset, val); ++ ++ return val; ++} ++ ++int mt7601u_wait_bbp_ready(struct mt7601u_dev *dev) ++{ ++ int i = 20; ++ u8 val; ++ ++ do { ++ val = mt7601u_bbp_rr(dev, MT_BBP_REG_VERSION); ++ if (val && ~val) ++ break; ++ } while (--i); ++ ++ if (!i) { ++ dev_err(dev->dev, "Error: BBP is not ready\n"); ++ return -EIO; ++ } ++ ++ return 0; ++} ++ ++u32 mt7601u_bbp_set_ctrlch(struct mt7601u_dev *dev, bool below) ++{ ++ return mt7601u_bbp_rmc(dev, 3, 0x20, below ? 0x20 : 0); ++} ++ ++int mt7601u_phy_get_rssi(struct mt7601u_dev *dev, ++ struct mt7601u_rxwi *rxwi, u16 rate) ++{ ++ static const s8 lna[2][2][3] = { ++ /* main LNA */ { ++ /* bw20 */ { -2, 15, 33 }, ++ /* bw40 */ { 0, 16, 34 } ++ }, ++ /* aux LNA */ { ++ /* bw20 */ { -2, 15, 33 }, ++ /* bw40 */ { -2, 16, 34 } ++ } ++ }; ++ int bw = MT76_GET(MT_RXWI_RATE_BW, rate); ++ int aux_lna = MT76_GET(MT_RXWI_ANT_AUX_LNA, rxwi->ant); ++ int lna_id = MT76_GET(MT_RXWI_GAIN_RSSI_LNA_ID, rxwi->gain); ++ int val; ++ ++ if (lna_id) /* LNA id can be 0, 2, 3. */ ++ lna_id--; ++ ++ val = 8; ++ val -= lna[aux_lna][bw][lna_id]; ++ val -= MT76_GET(MT_RXWI_GAIN_RSSI_VAL, rxwi->gain); ++ val -= dev->ee->lna_gain; ++ val -= dev->ee->rssi_offset[0]; ++ ++ return val; ++} ++ ++static void mt7601u_vco_cal(struct mt7601u_dev *dev) ++{ ++ mt7601u_rf_wr(dev, 0, 4, 0x0a); ++ mt7601u_rf_wr(dev, 0, 5, 0x20); ++ mt7601u_rf_set(dev, 0, 4, BIT(7)); ++ msleep(2); ++} ++ ++static int mt7601u_set_bw_filter(struct mt7601u_dev *dev, bool cal) ++{ ++ u32 filter = 0; ++ int ret; ++ ++ if (!cal) ++ filter |= 0x10000; ++ if (dev->bw != MT_BW_20) ++ filter |= 0x00100; ++ ++ /* TX */ ++ ret = mt7601u_mcu_calibrate(dev, MCU_CAL_BW, filter | 1); ++ if (ret) ++ return ret; ++ /* RX */ ++ return mt7601u_mcu_calibrate(dev, MCU_CAL_BW, filter); ++} ++ ++static int mt7601u_load_bbp_temp_table_bw(struct mt7601u_dev *dev) ++{ ++ const struct reg_table *t; ++ ++ if (WARN_ON(dev->temp_mode > MT_TEMP_MODE_LOW)) ++ return -EINVAL; ++ ++ t = &bbp_mode_table[dev->temp_mode][dev->bw]; ++ ++ return mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, t->regs, t->n); ++} ++ ++static int mt7601u_bbp_temp(struct mt7601u_dev *dev, int mode, const char *name) ++{ ++ const struct reg_table *t; ++ int ret; ++ ++ if (dev->temp_mode == mode) ++ return 0; ++ ++ dev->temp_mode = mode; ++ trace_temp_mode(dev, mode); ++ ++ t = bbp_mode_table[dev->temp_mode]; ++ ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, ++ t[2].regs, t[2].n); ++ if (ret) ++ return ret; ++ ++ return mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, ++ t[dev->bw].regs, t[dev->bw].n); ++} ++ ++static void mt7601u_apply_ch14_fixup(struct mt7601u_dev *dev, int hw_chan) ++{ ++ struct mt7601u_rate_power *t = &dev->ee->power_rate_table; ++ ++ if (hw_chan != 14 || dev->bw != MT_BW_20) { ++ mt7601u_bbp_rmw(dev, 4, 0x20, 0); ++ mt7601u_bbp_wr(dev, 178, 0xff); ++ ++ t->cck[0].bw20 = dev->ee->real_cck_bw20[0]; ++ t->cck[1].bw20 = dev->ee->real_cck_bw20[1]; ++ } else { /* Apply CH14 OBW fixup */ ++ mt7601u_bbp_wr(dev, 4, 0x60); ++ mt7601u_bbp_wr(dev, 178, 0); ++ ++ /* Note: vendor code is buggy here for negative values */ ++ t->cck[0].bw20 = dev->ee->real_cck_bw20[0] - 2; ++ t->cck[1].bw20 = dev->ee->real_cck_bw20[1] - 2; ++ } ++} ++ ++static int __mt7601u_phy_set_channel(struct mt7601u_dev *dev, ++ struct cfg80211_chan_def *chandef) ++{ ++#define FREQ_PLAN_REGS 4 ++ static const u8 freq_plan[14][FREQ_PLAN_REGS] = { ++ { 0x99, 0x99, 0x09, 0x50 }, ++ { 0x46, 0x44, 0x0a, 0x50 }, ++ { 0xec, 0xee, 0x0a, 0x50 }, ++ { 0x99, 0x99, 0x0b, 0x50 }, ++ { 0x46, 0x44, 0x08, 0x51 }, ++ { 0xec, 0xee, 0x08, 0x51 }, ++ { 0x99, 0x99, 0x09, 0x51 }, ++ { 0x46, 0x44, 0x0a, 0x51 }, ++ { 0xec, 0xee, 0x0a, 0x51 }, ++ { 0x99, 0x99, 0x0b, 0x51 }, ++ { 0x46, 0x44, 0x08, 0x52 }, ++ { 0xec, 0xee, 0x08, 0x52 }, ++ { 0x99, 0x99, 0x09, 0x52 }, ++ { 0x33, 0x33, 0x0b, 0x52 }, ++ }; ++ struct mt76_reg_pair channel_freq_plan[FREQ_PLAN_REGS] = { ++ { 17, 0 }, { 18, 0 }, { 19, 0 }, { 20, 0 }, ++ }; ++ struct mt76_reg_pair bbp_settings[3] = { ++ { 62, 0x37 - dev->ee->lna_gain }, ++ { 63, 0x37 - dev->ee->lna_gain }, ++ { 64, 0x37 - dev->ee->lna_gain }, ++ }; ++ ++ struct ieee80211_channel *chan = chandef->chan; ++ enum nl80211_channel_type chan_type = ++ cfg80211_get_chandef_type(chandef); ++ struct mt7601u_rate_power *t = &dev->ee->power_rate_table; ++ int chan_idx; ++ bool chan_ext_below; ++ u8 bw; ++ int i, ret; ++ ++ bw = MT_BW_20; ++ chan_ext_below = (chan_type == NL80211_CHAN_HT40MINUS); ++ chan_idx = chan->hw_value - 1; ++ ++ if (chandef->width == NL80211_CHAN_WIDTH_40) { ++ bw = MT_BW_40; ++ ++ if (chan_idx > 1 && chan_type == NL80211_CHAN_HT40MINUS) ++ chan_idx -= 2; ++ else if (chan_idx < 12 && chan_type == NL80211_CHAN_HT40PLUS) ++ chan_idx += 2; ++ else ++ dev_err(dev->dev, "Error: invalid 40MHz channel!!\n"); ++ } ++ ++ if (bw != dev->bw || chan_ext_below != dev->chan_ext_below) { ++ dev_dbg(dev->dev, "Info: switching HT mode bw:%d below:%d\n", ++ bw, chan_ext_below); ++ ++ mt7601u_bbp_set_bw(dev, bw); ++ ++ mt7601u_bbp_set_ctrlch(dev, chan_ext_below); ++ mt7601u_mac_set_ctrlch(dev, chan_ext_below); ++ dev->chan_ext_below = chan_ext_below; ++ } ++ ++ for (i = 0; i < FREQ_PLAN_REGS; i++) ++ channel_freq_plan[i].value = freq_plan[chan_idx][i]; ++ ++ ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_RF, ++ channel_freq_plan, FREQ_PLAN_REGS); ++ if (ret) ++ return ret; ++ ++ mt7601u_rmw(dev, MT_TX_ALC_CFG_0, 0x3f3f, ++ dev->ee->chan_pwr[chan_idx] & 0x3f); ++ ++ ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, ++ bbp_settings, ARRAY_SIZE(bbp_settings)); ++ if (ret) ++ return ret; ++ ++ mt7601u_vco_cal(dev); ++ mt7601u_bbp_set_bw(dev, bw); ++ ret = mt7601u_set_bw_filter(dev, false); ++ if (ret) ++ return ret; ++ ++ mt7601u_apply_ch14_fixup(dev, chan->hw_value); ++ mt7601u_wr(dev, MT_TX_PWR_CFG_0, int_to_s6(t->ofdm[1].bw20) << 24 | ++ int_to_s6(t->ofdm[0].bw20) << 16 | ++ int_to_s6(t->cck[1].bw20) << 8 | ++ int_to_s6(t->cck[0].bw20)); ++ ++ if (test_bit(MT7601U_STATE_SCANNING, &dev->state)) ++ mt7601u_agc_reset(dev); ++ ++ dev->chandef = *chandef; ++ ++ return 0; ++} ++ ++int mt7601u_phy_set_channel(struct mt7601u_dev *dev, ++ struct cfg80211_chan_def *chandef) ++{ ++ int ret; ++ ++ cancel_delayed_work_sync(&dev->cal_work); ++ cancel_delayed_work_sync(&dev->freq_cal.work); ++ ++ mutex_lock(&dev->hw_atomic_mutex); ++ ret = __mt7601u_phy_set_channel(dev, chandef); ++ mutex_unlock(&dev->hw_atomic_mutex); ++ if (ret) ++ return ret; ++ ++ if (test_bit(MT7601U_STATE_SCANNING, &dev->state)) ++ return 0; ++ ++ ieee80211_queue_delayed_work(dev->hw, &dev->cal_work, ++ MT_CALIBRATE_INTERVAL); ++ if (dev->freq_cal.enabled) ++ ieee80211_queue_delayed_work(dev->hw, &dev->freq_cal.work, ++ MT_FREQ_CAL_INIT_DELAY); ++ return 0; ++} ++ ++#define BBP_R47_FLAG GENMASK(2, 0) ++#define BBP_R47_F_TSSI 0 ++#define BBP_R47_F_PKT_T 1 ++#define BBP_R47_F_TX_RATE 2 ++#define BBP_R47_F_TEMP 4 ++/** ++ * mt7601u_bbp_r47_get - read value through BBP R47/R49 pair ++ * @dev: pointer to adapter structure ++ * @reg: value of BBP R47 before the operation ++ * @flag: one of the BBP_R47_F_* flags ++ * ++ * Convenience helper for reading values through BBP R47/R49 pair. ++ * Takes old value of BBP R47 as @reg, because callers usually have it ++ * cached already. ++ * ++ * Return: value of BBP R49. ++ */ ++static u8 mt7601u_bbp_r47_get(struct mt7601u_dev *dev, u8 reg, u8 flag) ++{ ++ flag |= reg & ~BBP_R47_FLAG; ++ mt7601u_bbp_wr(dev, 47, flag); ++ usleep_range(500, 700); ++ return mt7601u_bbp_rr(dev, 49); ++} ++ ++static s8 mt7601u_read_bootup_temp(struct mt7601u_dev *dev) ++{ ++ u8 bbp_val, temp; ++ u32 rf_bp, rf_set; ++ int i; ++ ++ rf_set = mt7601u_rr(dev, MT_RF_SETTING_0); ++ rf_bp = mt7601u_rr(dev, MT_RF_BYPASS_0); ++ ++ mt7601u_wr(dev, MT_RF_BYPASS_0, 0); ++ mt7601u_wr(dev, MT_RF_SETTING_0, 0x00000010); ++ mt7601u_wr(dev, MT_RF_BYPASS_0, 0x00000010); ++ ++ bbp_val = mt7601u_bbp_rmw(dev, 47, 0, 0x10); ++ ++ mt7601u_bbp_wr(dev, 22, 0x40); ++ ++ for (i = 100; i && (bbp_val & 0x10); i--) ++ bbp_val = mt7601u_bbp_rr(dev, 47); ++ ++ temp = mt7601u_bbp_r47_get(dev, bbp_val, BBP_R47_F_TEMP); ++ ++ mt7601u_bbp_wr(dev, 22, 0); ++ ++ bbp_val = mt7601u_bbp_rr(dev, 21); ++ bbp_val |= 0x02; ++ mt7601u_bbp_wr(dev, 21, bbp_val); ++ bbp_val &= ~0x02; ++ mt7601u_bbp_wr(dev, 21, bbp_val); ++ ++ mt7601u_wr(dev, MT_RF_BYPASS_0, 0); ++ mt7601u_wr(dev, MT_RF_SETTING_0, rf_set); ++ mt7601u_wr(dev, MT_RF_BYPASS_0, rf_bp); ++ ++ trace_read_temp(dev, temp); ++ return temp; ++} ++ ++static s8 mt7601u_read_temp(struct mt7601u_dev *dev) ++{ ++ int i; ++ u8 val; ++ s8 temp; ++ ++ val = mt7601u_bbp_rmw(dev, 47, 0x7f, 0x10); ++ ++ /* Note: this rarely succeeds, temp can change even if it fails. */ ++ for (i = 100; i && (val & 0x10); i--) ++ val = mt7601u_bbp_rr(dev, 47); ++ ++ temp = mt7601u_bbp_r47_get(dev, val, BBP_R47_F_TEMP); ++ ++ trace_read_temp(dev, temp); ++ return temp; ++} ++ ++static void mt7601u_rxdc_cal(struct mt7601u_dev *dev) ++{ ++ static const struct mt76_reg_pair intro[] = { ++ { 158, 0x8d }, { 159, 0xfc }, ++ { 158, 0x8c }, { 159, 0x4c }, ++ }, outro[] = { ++ { 158, 0x8d }, { 159, 0xe0 }, ++ }; ++ u32 mac_ctrl; ++ int i, ret; ++ ++ mac_ctrl = mt7601u_rr(dev, MT_MAC_SYS_CTRL); ++ mt7601u_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX); ++ ++ ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, ++ intro, ARRAY_SIZE(intro)); ++ if (ret) ++ dev_err(dev->dev, "%s intro failed:%d\n", __func__, ret); ++ ++ for (i = 20; i; i--) { ++ usleep_range(300, 500); ++ ++ mt7601u_bbp_wr(dev, 158, 0x8c); ++ if (mt7601u_bbp_rr(dev, 159) == 0x0c) ++ break; ++ } ++ if (!i) ++ dev_err(dev->dev, "%s timed out\n", __func__); ++ ++ mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0); ++ ++ ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, ++ outro, ARRAY_SIZE(outro)); ++ if (ret) ++ dev_err(dev->dev, "%s outro failed:%d\n", __func__, ret); ++ ++ mt7601u_wr(dev, MT_MAC_SYS_CTRL, mac_ctrl); ++} ++ ++void mt7601u_phy_recalibrate_after_assoc(struct mt7601u_dev *dev) ++{ ++ mt7601u_mcu_calibrate(dev, MCU_CAL_DPD, dev->curr_temp); ++ ++ mt7601u_rxdc_cal(dev); ++} ++ ++/* Note: function copied from vendor driver */ ++static s16 lin2dBd(u16 linear) ++{ ++ short exp = 0; ++ unsigned int mantisa; ++ int app, dBd; ++ ++ if (WARN_ON(!linear)) ++ return -10000; ++ ++ mantisa = linear; ++ ++ exp = fls(mantisa) - 16; ++ if (exp > 0) ++ mantisa >>= exp; ++ else ++ mantisa <<= abs(exp); ++ ++ if (mantisa <= 0xb800) ++ app = (mantisa + (mantisa >> 3) + (mantisa >> 4) - 0x9600); ++ else ++ app = (mantisa - (mantisa >> 3) - (mantisa >> 6) - 0x5a00); ++ if (app < 0) ++ app = 0; ++ ++ dBd = ((15 + exp) << 15) + app; ++ dBd = (dBd << 2) + (dBd << 1) + (dBd >> 6) + (dBd >> 7); ++ dBd = (dBd >> 10); ++ ++ return dBd; ++} ++ ++static void ++mt7601u_set_initial_tssi(struct mt7601u_dev *dev, s16 tssi_db, s16 tssi_hvga_db) ++{ ++ struct tssi_data *d = &dev->ee->tssi_data; ++ int init_offset; ++ ++ init_offset = -((tssi_db * d->slope + d->offset[1]) / 4096) + 10; ++ ++ mt76_rmw(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP, ++ int_to_s6(init_offset) & MT_TX_ALC_CFG_1_TEMP_COMP); ++} ++ ++static void mt7601u_tssi_dc_gain_cal(struct mt7601u_dev *dev) ++{ ++ u8 rf_vga, rf_mixer, bbp_r47; ++ int i, j; ++ s8 res[4]; ++ s16 tssi_init_db, tssi_init_hvga_db; ++ ++ mt7601u_wr(dev, MT_RF_SETTING_0, 0x00000030); ++ mt7601u_wr(dev, MT_RF_BYPASS_0, 0x000c0030); ++ mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0); ++ ++ mt7601u_bbp_wr(dev, 58, 0); ++ mt7601u_bbp_wr(dev, 241, 0x2); ++ mt7601u_bbp_wr(dev, 23, 0x8); ++ bbp_r47 = mt7601u_bbp_rr(dev, 47); ++ ++ /* Set VGA gain */ ++ rf_vga = mt7601u_rf_rr(dev, 5, 3); ++ mt7601u_rf_wr(dev, 5, 3, 8); ++ ++ /* Mixer disable */ ++ rf_mixer = mt7601u_rf_rr(dev, 4, 39); ++ mt7601u_rf_wr(dev, 4, 39, 0); ++ ++ for (i = 0; i < 4; i++) { ++ mt7601u_rf_wr(dev, 4, 39, (i & 1) ? rf_mixer : 0); ++ ++ mt7601u_bbp_wr(dev, 23, (i < 2) ? 0x08 : 0x02); ++ mt7601u_rf_wr(dev, 5, 3, (i < 2) ? 0x08 : 0x11); ++ ++ /* BBP TSSI initial and soft reset */ ++ mt7601u_bbp_wr(dev, 22, 0); ++ mt7601u_bbp_wr(dev, 244, 0); ++ ++ mt7601u_bbp_wr(dev, 21, 1); ++ udelay(1); ++ mt7601u_bbp_wr(dev, 21, 0); ++ ++ /* TSSI measurement */ ++ mt7601u_bbp_wr(dev, 47, 0x50); ++ mt7601u_bbp_wr(dev, (i & 1) ? 244 : 22, (i & 1) ? 0x31 : 0x40); ++ ++ for (j = 20; j; j--) ++ if (!(mt7601u_bbp_rr(dev, 47) & 0x10)) ++ break; ++ if (!j) ++ dev_err(dev->dev, "%s timed out\n", __func__); ++ ++ /* TSSI read */ ++ mt7601u_bbp_wr(dev, 47, 0x40); ++ res[i] = mt7601u_bbp_rr(dev, 49); ++ } ++ ++ tssi_init_db = lin2dBd((short)res[1] - res[0]); ++ tssi_init_hvga_db = lin2dBd(((short)res[3] - res[2]) * 4); ++ dev->tssi_init = res[0]; ++ dev->tssi_init_hvga = res[2]; ++ dev->tssi_init_hvga_offset_db = tssi_init_hvga_db - tssi_init_db; ++ ++ dev_dbg(dev->dev, ++ "TSSI_init:%hhx db:%hx hvga:%hhx hvga_db:%hx off_db:%hx\n", ++ dev->tssi_init, tssi_init_db, dev->tssi_init_hvga, ++ tssi_init_hvga_db, dev->tssi_init_hvga_offset_db); ++ ++ mt7601u_bbp_wr(dev, 22, 0); ++ mt7601u_bbp_wr(dev, 244, 0); ++ ++ mt7601u_bbp_wr(dev, 21, 1); ++ udelay(1); ++ mt7601u_bbp_wr(dev, 21, 0); ++ ++ mt7601u_wr(dev, MT_RF_BYPASS_0, 0); ++ mt7601u_wr(dev, MT_RF_SETTING_0, 0); ++ ++ mt7601u_rf_wr(dev, 5, 3, rf_vga); ++ mt7601u_rf_wr(dev, 4, 39, rf_mixer); ++ mt7601u_bbp_wr(dev, 47, bbp_r47); ++ ++ mt7601u_set_initial_tssi(dev, tssi_init_db, tssi_init_hvga_db); ++} ++ ++static int mt7601u_temp_comp(struct mt7601u_dev *dev, bool on) ++{ ++ int ret, temp, hi_temp = 400, lo_temp = -200; ++ ++ temp = (dev->raw_temp - dev->ee->ref_temp) * MT_EE_TEMPERATURE_SLOPE; ++ dev->curr_temp = temp; ++ ++ /* DPD Calibration */ ++ if (temp - dev->dpd_temp > 450 || temp - dev->dpd_temp < -450) { ++ dev->dpd_temp = temp; ++ ++ ret = mt7601u_mcu_calibrate(dev, MCU_CAL_DPD, dev->dpd_temp); ++ if (ret) ++ return ret; ++ ++ mt7601u_vco_cal(dev); ++ ++ dev_dbg(dev->dev, "Recalibrate DPD\n"); ++ } ++ ++ /* PLL Lock Protect */ ++ if (temp < -50 && !dev->pll_lock_protect) { /* < 20C */ ++ dev->pll_lock_protect = true; ++ ++ mt7601u_rf_wr(dev, 4, 4, 6); ++ mt7601u_rf_clear(dev, 4, 10, 0x30); ++ ++ dev_dbg(dev->dev, "PLL lock protect on - too cold\n"); ++ } else if (temp > 50 && dev->pll_lock_protect) { /* > 30C */ ++ dev->pll_lock_protect = false; ++ ++ mt7601u_rf_wr(dev, 4, 4, 0); ++ mt7601u_rf_rmw(dev, 4, 10, 0x30, 0x10); ++ ++ dev_dbg(dev->dev, "PLL lock protect off\n"); ++ } ++ ++ if (on) { ++ hi_temp -= 50; ++ lo_temp -= 50; ++ } ++ ++ /* BBP CR for H, L, N temperature */ ++ if (temp > hi_temp) ++ return mt7601u_bbp_temp(dev, MT_TEMP_MODE_HIGH, "high"); ++ else if (temp > lo_temp) ++ return mt7601u_bbp_temp(dev, MT_TEMP_MODE_NORMAL, "normal"); ++ else ++ return mt7601u_bbp_temp(dev, MT_TEMP_MODE_LOW, "low"); ++} ++ ++/* Note: this is used only with TSSI, we can just use trgt_pwr from eeprom. */ ++static int mt7601u_current_tx_power(struct mt7601u_dev *dev) ++{ ++ return dev->ee->chan_pwr[dev->chandef.chan->hw_value - 1]; ++} ++ ++static bool mt7601u_use_hvga(struct mt7601u_dev *dev) ++{ ++ return !(mt7601u_current_tx_power(dev) > 20); ++} ++ ++static s16 ++mt7601u_phy_rf_pa_mode_val(struct mt7601u_dev *dev, int phy_mode, int tx_rate) ++{ ++ static const s16 decode_tb[] = { 0, 8847, -5734, -5734 }; ++ u32 reg; ++ ++ switch (phy_mode) { ++ case MT_PHY_TYPE_OFDM: ++ tx_rate += 4; ++ case MT_PHY_TYPE_CCK: ++ reg = dev->rf_pa_mode[0]; ++ break; ++ default: ++ reg = dev->rf_pa_mode[1]; ++ break; ++ } ++ ++ return decode_tb[(reg >> (tx_rate * 2)) & 0x3]; ++} ++ ++static struct mt7601u_tssi_params ++mt7601u_tssi_params_get(struct mt7601u_dev *dev) ++{ ++ static const u8 ofdm_pkt2rate[8] = { 6, 4, 2, 0, 7, 5, 3, 1 }; ++ static const int static_power[4] = { 0, -49152, -98304, 49152 }; ++ struct mt7601u_tssi_params p; ++ u8 bbp_r47, pkt_type, tx_rate; ++ struct power_per_rate *rate_table; ++ ++ bbp_r47 = mt7601u_bbp_rr(dev, 47); ++ ++ p.tssi0 = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_TSSI); ++ dev->raw_temp = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_TEMP); ++ pkt_type = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_PKT_T); ++ ++ p.trgt_power = mt7601u_current_tx_power(dev); ++ ++ switch (pkt_type & 0x03) { ++ case MT_PHY_TYPE_CCK: ++ tx_rate = (pkt_type >> 4) & 0x03; ++ rate_table = dev->ee->power_rate_table.cck; ++ break; ++ ++ case MT_PHY_TYPE_OFDM: ++ tx_rate = ofdm_pkt2rate[(pkt_type >> 4) & 0x07]; ++ rate_table = dev->ee->power_rate_table.ofdm; ++ break; ++ ++ default: ++ tx_rate = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_TX_RATE); ++ tx_rate &= 0x7f; ++ rate_table = dev->ee->power_rate_table.ht; ++ break; ++ } ++ ++ if (dev->bw == MT_BW_20) ++ p.trgt_power += rate_table[tx_rate / 2].bw20; ++ else ++ p.trgt_power += rate_table[tx_rate / 2].bw40; ++ ++ p.trgt_power <<= 12; ++ ++ dev_dbg(dev->dev, "tx_rate:%02hhx pwr:%08x\n", tx_rate, p.trgt_power); ++ ++ p.trgt_power += mt7601u_phy_rf_pa_mode_val(dev, pkt_type & 0x03, ++ tx_rate); ++ ++ /* Channel 14, cck, bw20 */ ++ if ((pkt_type & 0x03) == MT_PHY_TYPE_CCK) { ++ if (mt7601u_bbp_rr(dev, 4) & 0x20) ++ p.trgt_power += mt7601u_bbp_rr(dev, 178) ? 18022 : 9830; ++ else ++ p.trgt_power += mt7601u_bbp_rr(dev, 178) ? 819 : 24576; ++ } ++ ++ p.trgt_power += static_power[mt7601u_bbp_rr(dev, 1) & 0x03]; ++ ++ p.trgt_power += dev->ee->tssi_data.tx0_delta_offset; ++ ++ dev_dbg(dev->dev, ++ "tssi:%02hhx t_power:%08x temp:%02hhx pkt_type:%02hhx\n", ++ p.tssi0, p.trgt_power, dev->raw_temp, pkt_type); ++ ++ return p; ++} ++ ++static bool mt7601u_tssi_read_ready(struct mt7601u_dev *dev) ++{ ++ return !(mt7601u_bbp_rr(dev, 47) & 0x10); ++} ++ ++static int mt7601u_tssi_cal(struct mt7601u_dev *dev) ++{ ++ struct mt7601u_tssi_params params; ++ int curr_pwr, diff_pwr; ++ char tssi_offset; ++ s8 tssi_init; ++ s16 tssi_m_dc, tssi_db; ++ bool hvga; ++ u32 val; ++ ++ if (!dev->ee->tssi_enabled) ++ return 0; ++ ++ hvga = mt7601u_use_hvga(dev); ++ if (!dev->tssi_read_trig) ++ return mt7601u_mcu_tssi_read_kick(dev, hvga); ++ ++ if (!mt7601u_tssi_read_ready(dev)) ++ return 0; ++ ++ params = mt7601u_tssi_params_get(dev); ++ ++ tssi_init = (hvga ? dev->tssi_init_hvga : dev->tssi_init); ++ tssi_m_dc = params.tssi0 - tssi_init; ++ tssi_db = lin2dBd(tssi_m_dc); ++ dev_dbg(dev->dev, "tssi dc:%04hx db:%04hx hvga:%d\n", ++ tssi_m_dc, tssi_db, hvga); ++ ++ if (dev->chandef.chan->hw_value < 5) ++ tssi_offset = dev->ee->tssi_data.offset[0]; ++ else if (dev->chandef.chan->hw_value < 9) ++ tssi_offset = dev->ee->tssi_data.offset[1]; ++ else ++ tssi_offset = dev->ee->tssi_data.offset[2]; ++ ++ if (hvga) ++ tssi_db -= dev->tssi_init_hvga_offset_db; ++ ++ curr_pwr = tssi_db * dev->ee->tssi_data.slope + (tssi_offset << 9); ++ diff_pwr = params.trgt_power - curr_pwr; ++ dev_dbg(dev->dev, "Power curr:%08x diff:%08x\n", curr_pwr, diff_pwr); ++ ++ if (params.tssi0 > 126 && diff_pwr > 0) { ++ dev_err(dev->dev, "Error: TSSI upper saturation\n"); ++ diff_pwr = 0; ++ } ++ if (params.tssi0 - tssi_init < 1 && diff_pwr < 0) { ++ dev_err(dev->dev, "Error: TSSI lower saturation\n"); ++ diff_pwr = 0; ++ } ++ ++ if ((dev->prev_pwr_diff ^ diff_pwr) < 0 && abs(diff_pwr) < 4096 && ++ (abs(diff_pwr) > abs(dev->prev_pwr_diff) || ++ (diff_pwr > 0 && diff_pwr == -dev->prev_pwr_diff))) ++ diff_pwr = 0; ++ else ++ dev->prev_pwr_diff = diff_pwr; ++ ++ diff_pwr += (diff_pwr > 0) ? 2048 : -2048; ++ diff_pwr /= 4096; ++ ++ dev_dbg(dev->dev, "final diff: %08x\n", diff_pwr); ++ ++ val = mt7601u_rr(dev, MT_TX_ALC_CFG_1); ++ curr_pwr = s6_to_int(MT76_GET(MT_TX_ALC_CFG_1_TEMP_COMP, val)); ++ diff_pwr += curr_pwr; ++ val = (val & ~MT_TX_ALC_CFG_1_TEMP_COMP) | int_to_s6(diff_pwr); ++ mt7601u_wr(dev, MT_TX_ALC_CFG_1, val); ++ ++ return mt7601u_mcu_tssi_read_kick(dev, hvga); ++} ++ ++static u8 mt7601u_agc_default(struct mt7601u_dev *dev) ++{ ++ return (dev->ee->lna_gain - 8) * 2 + 0x34; ++} ++ ++static void mt7601u_agc_reset(struct mt7601u_dev *dev) ++{ ++ u8 agc = mt7601u_agc_default(dev); ++ ++ mt7601u_bbp_wr(dev, 66, agc); ++} ++ ++void mt7601u_agc_save(struct mt7601u_dev *dev) ++{ ++ dev->agc_save = mt7601u_bbp_rr(dev, 66); ++} ++ ++void mt7601u_agc_restore(struct mt7601u_dev *dev) ++{ ++ mt7601u_bbp_wr(dev, 66, dev->agc_save); ++} ++ ++static void mt7601u_agc_tune(struct mt7601u_dev *dev) ++{ ++ u8 val = mt7601u_agc_default(dev); ++ ++ if (test_bit(MT7601U_STATE_SCANNING, &dev->state)) ++ return; ++ ++ /* Note: only in STA mode and not dozing; perhaps do this only if ++ * there is enough rssi updates since last run? ++ * Rssi updates are only on beacons and U2M so should work... ++ */ ++ spin_lock_bh(&dev->con_mon_lock); ++ if (dev->avg_rssi <= -70) ++ val -= 0x20; ++ else if (dev->avg_rssi <= -60) ++ val -= 0x10; ++ spin_unlock_bh(&dev->con_mon_lock); ++ ++ if (val != mt7601u_bbp_rr(dev, 66)) ++ mt7601u_bbp_wr(dev, 66, val); ++ ++ /* TODO: also if lost a lot of beacons try resetting ++ * (see RTMPSetAGCInitValue() call in mlme.c). ++ */ ++} ++ ++static void mt7601u_phy_calibrate(struct work_struct *work) ++{ ++ struct mt7601u_dev *dev = container_of(work, struct mt7601u_dev, ++ cal_work.work); ++ ++ mt7601u_agc_tune(dev); ++ mt7601u_tssi_cal(dev); ++ /* If TSSI calibration was run it already updated temperature. */ ++ if (!dev->ee->tssi_enabled) ++ dev->raw_temp = mt7601u_read_temp(dev); ++ mt7601u_temp_comp(dev, true); /* TODO: find right value for @on */ ++ ++ ieee80211_queue_delayed_work(dev->hw, &dev->cal_work, ++ MT_CALIBRATE_INTERVAL); ++} ++ ++static unsigned long ++__mt7601u_phy_freq_cal(struct mt7601u_dev *dev, s8 last_offset, u8 phy_mode) ++{ ++ u8 activate_threshold, deactivate_threshold; ++ ++ trace_freq_cal_offset(dev, phy_mode, last_offset); ++ ++ /* No beacons received - reschedule soon */ ++ if (last_offset == MT_FREQ_OFFSET_INVALID) ++ return MT_FREQ_CAL_ADJ_INTERVAL; ++ ++ switch (phy_mode) { ++ case MT_PHY_TYPE_CCK: ++ activate_threshold = 19; ++ deactivate_threshold = 5; ++ break; ++ case MT_PHY_TYPE_OFDM: ++ activate_threshold = 102; ++ deactivate_threshold = 32; ++ break; ++ case MT_PHY_TYPE_HT: ++ case MT_PHY_TYPE_HT_GF: ++ activate_threshold = 82; ++ deactivate_threshold = 20; ++ break; ++ default: ++ WARN_ON(1); ++ return MT_FREQ_CAL_CHECK_INTERVAL; ++ } ++ ++ if (abs(last_offset) >= activate_threshold) ++ dev->freq_cal.adjusting = true; ++ else if (abs(last_offset) <= deactivate_threshold) ++ dev->freq_cal.adjusting = false; ++ ++ if (!dev->freq_cal.adjusting) ++ return MT_FREQ_CAL_CHECK_INTERVAL; ++ ++ if (last_offset > deactivate_threshold) { ++ if (dev->freq_cal.freq > 0) ++ dev->freq_cal.freq--; ++ else ++ dev->freq_cal.adjusting = false; ++ } else if (last_offset < -deactivate_threshold) { ++ if (dev->freq_cal.freq < 0xbf) ++ dev->freq_cal.freq++; ++ else ++ dev->freq_cal.adjusting = false; ++ } ++ ++ trace_freq_cal_adjust(dev, dev->freq_cal.freq); ++ mt7601u_rf_wr(dev, 0, 12, dev->freq_cal.freq); ++ mt7601u_vco_cal(dev); ++ ++ return dev->freq_cal.adjusting ? MT_FREQ_CAL_ADJ_INTERVAL : ++ MT_FREQ_CAL_CHECK_INTERVAL; ++} ++ ++static void mt7601u_phy_freq_cal(struct work_struct *work) ++{ ++ struct mt7601u_dev *dev = container_of(work, struct mt7601u_dev, ++ freq_cal.work.work); ++ s8 last_offset; ++ u8 phy_mode; ++ unsigned long delay; ++ ++ spin_lock_bh(&dev->con_mon_lock); ++ last_offset = dev->bcn_freq_off; ++ phy_mode = dev->bcn_phy_mode; ++ spin_unlock_bh(&dev->con_mon_lock); ++ ++ delay = __mt7601u_phy_freq_cal(dev, last_offset, phy_mode); ++ ieee80211_queue_delayed_work(dev->hw, &dev->freq_cal.work, delay); ++ ++ spin_lock_bh(&dev->con_mon_lock); ++ dev->bcn_freq_off = MT_FREQ_OFFSET_INVALID; ++ spin_unlock_bh(&dev->con_mon_lock); ++} ++ ++void mt7601u_phy_con_cal_onoff(struct mt7601u_dev *dev, ++ struct ieee80211_bss_conf *info) ++{ ++ if (!info->assoc) ++ cancel_delayed_work_sync(&dev->freq_cal.work); ++ ++ /* Start/stop collecting beacon data */ ++ spin_lock_bh(&dev->con_mon_lock); ++ ether_addr_copy(dev->ap_bssid, info->bssid); ++ dev->avg_rssi = 0; ++ dev->bcn_freq_off = MT_FREQ_OFFSET_INVALID; ++ spin_unlock_bh(&dev->con_mon_lock); ++ ++ dev->freq_cal.freq = dev->ee->rf_freq_off; ++ dev->freq_cal.enabled = info->assoc; ++ dev->freq_cal.adjusting = false; ++ ++ if (info->assoc) ++ ieee80211_queue_delayed_work(dev->hw, &dev->freq_cal.work, ++ MT_FREQ_CAL_INIT_DELAY); ++} ++ ++static int mt7601u_init_cal(struct mt7601u_dev *dev) ++{ ++ u32 mac_ctrl; ++ int ret; ++ ++ dev->raw_temp = mt7601u_read_bootup_temp(dev); ++ dev->curr_temp = (dev->raw_temp - dev->ee->ref_temp) * ++ MT_EE_TEMPERATURE_SLOPE; ++ dev->dpd_temp = dev->curr_temp; ++ ++ mac_ctrl = mt7601u_rr(dev, MT_MAC_SYS_CTRL); ++ ++ ret = mt7601u_mcu_calibrate(dev, MCU_CAL_R, 0); ++ if (ret) ++ return ret; ++ ++ ret = mt7601u_rf_rr(dev, 0, 4); ++ if (ret < 0) ++ return ret; ++ ret |= 0x80; ++ ret = mt7601u_rf_wr(dev, 0, 4, ret); ++ if (ret) ++ return ret; ++ msleep(2); ++ ++ ret = mt7601u_mcu_calibrate(dev, MCU_CAL_TXDCOC, 0); ++ if (ret) ++ return ret; ++ ++ mt7601u_rxdc_cal(dev); ++ ++ ret = mt7601u_set_bw_filter(dev, true); ++ if (ret) ++ return ret; ++ ret = mt7601u_mcu_calibrate(dev, MCU_CAL_LOFT, 0); ++ if (ret) ++ return ret; ++ ret = mt7601u_mcu_calibrate(dev, MCU_CAL_TXIQ, 0); ++ if (ret) ++ return ret; ++ ret = mt7601u_mcu_calibrate(dev, MCU_CAL_RXIQ, 0); ++ if (ret) ++ return ret; ++ ret = mt7601u_mcu_calibrate(dev, MCU_CAL_DPD, dev->dpd_temp); ++ if (ret) ++ return ret; ++ ++ mt7601u_rxdc_cal(dev); ++ ++ mt7601u_tssi_dc_gain_cal(dev); ++ ++ mt7601u_wr(dev, MT_MAC_SYS_CTRL, mac_ctrl); ++ ++ mt7601u_temp_comp(dev, true); ++ ++ return 0; ++} ++ ++int mt7601u_bbp_set_bw(struct mt7601u_dev *dev, int bw) ++{ ++ u32 val, old; ++ ++ if (bw == dev->bw) { ++ /* Vendor driver does the rmc even when no change is needed. */ ++ mt7601u_bbp_rmc(dev, 4, 0x18, bw == MT_BW_20 ? 0 : 0x10); ++ ++ return 0; ++ } ++ dev->bw = bw; ++ ++ /* Stop MAC for the time of bw change */ ++ old = mt7601u_rr(dev, MT_MAC_SYS_CTRL); ++ val = old & ~(MT_MAC_SYS_CTRL_ENABLE_TX | MT_MAC_SYS_CTRL_ENABLE_RX); ++ mt7601u_wr(dev, MT_MAC_SYS_CTRL, val); ++ mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_TX | MT_MAC_STATUS_RX, ++ 0, 500000); ++ ++ mt7601u_bbp_rmc(dev, 4, 0x18, bw == MT_BW_20 ? 0 : 0x10); ++ ++ mt7601u_wr(dev, MT_MAC_SYS_CTRL, old); ++ ++ return mt7601u_load_bbp_temp_table_bw(dev); ++} ++ ++/** ++ * mt7601u_set_rx_path - set rx path in BBP ++ * @dev: pointer to adapter structure ++ * @path: rx path to set values are 0-based ++ */ ++void mt7601u_set_rx_path(struct mt7601u_dev *dev, u8 path) ++{ ++ mt7601u_bbp_rmw(dev, 3, 0x18, path << 3); ++} ++ ++/** ++ * mt7601u_set_tx_dac - set which tx DAC to use ++ * @dev: pointer to adapter structure ++ * @path: DAC index, values are 0-based ++ */ ++void mt7601u_set_tx_dac(struct mt7601u_dev *dev, u8 dac) ++{ ++ mt7601u_bbp_rmc(dev, 1, 0x18, dac << 3); ++} ++ ++int mt7601u_phy_init(struct mt7601u_dev *dev) ++{ ++ int ret; ++ ++ dev->rf_pa_mode[0] = mt7601u_rr(dev, MT_RF_PA_MODE_CFG0); ++ dev->rf_pa_mode[1] = mt7601u_rr(dev, MT_RF_PA_MODE_CFG1); ++ ++ ret = mt7601u_rf_wr(dev, 0, 12, dev->ee->rf_freq_off); ++ if (ret) ++ return ret; ++ ret = mt7601u_write_reg_pairs(dev, 0, rf_central, ++ ARRAY_SIZE(rf_central)); ++ if (ret) ++ return ret; ++ ret = mt7601u_write_reg_pairs(dev, 0, rf_channel, ++ ARRAY_SIZE(rf_channel)); ++ if (ret) ++ return ret; ++ ret = mt7601u_write_reg_pairs(dev, 0, rf_vga, ARRAY_SIZE(rf_vga)); ++ if (ret) ++ return ret; ++ ++ ret = mt7601u_init_cal(dev); ++ if (ret) ++ return ret; ++ ++ dev->prev_pwr_diff = 100; ++ ++ INIT_DELAYED_WORK(&dev->cal_work, mt7601u_phy_calibrate); ++ INIT_DELAYED_WORK(&dev->freq_cal.work, mt7601u_phy_freq_cal); ++ ++ return 0; ++} +diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/regs.h linux-rpi/drivers/net/wireless/mediatek/mt7601u/regs.h +--- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/regs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/regs.h 2015-11-29 09:42:38.887167260 +0100 +@@ -0,0 +1,636 @@ ++/* ++ * Copyright (C) 2014 Felix Fietkau ++ * Copyright (C) 2015 Jakub Kicinski ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 ++ * as published by the Free Software Foundation ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef __MT76_REGS_H ++#define __MT76_REGS_H ++ ++#include ++ ++#ifndef GENMASK ++#define GENMASK(h, l) (((U32_C(1) << ((h) - (l) + 1)) - 1) << (l)) ++#endif ++ ++#define MT_ASIC_VERSION 0x0000 ++ ++#define MT76XX_REV_E3 0x22 ++#define MT76XX_REV_E4 0x33 ++ ++#define MT_CMB_CTRL 0x0020 ++#define MT_CMB_CTRL_XTAL_RDY BIT(22) ++#define MT_CMB_CTRL_PLL_LD BIT(23) ++ ++#define MT_EFUSE_CTRL 0x0024 ++#define MT_EFUSE_CTRL_AOUT GENMASK(5, 0) ++#define MT_EFUSE_CTRL_MODE GENMASK(7, 6) ++#define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8) ++#define MT_EFUSE_CTRL_LDO_ON_TIME GENMASK(15, 14) ++#define MT_EFUSE_CTRL_AIN GENMASK(25, 16) ++#define MT_EFUSE_CTRL_KICK BIT(30) ++#define MT_EFUSE_CTRL_SEL BIT(31) ++ ++#define MT_EFUSE_DATA_BASE 0x0028 ++#define MT_EFUSE_DATA(_n) (MT_EFUSE_DATA_BASE + ((_n) << 2)) ++ ++#define MT_COEXCFG0 0x0040 ++#define MT_COEXCFG0_COEX_EN BIT(0) ++ ++#define MT_WLAN_FUN_CTRL 0x0080 ++#define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0) ++#define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1) ++#define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2) ++ ++#define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3) /* MT76x0 */ ++#define MT_WLAN_FUN_CTRL_CSR_F20M_CKEN BIT(3) /* MT76x2 */ ++ ++#define MT_WLAN_FUN_CTRL_PCIE_CLK_REQ BIT(4) ++#define MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL BIT(5) ++#define MT_WLAN_FUN_CTRL_INV_ANT_SEL BIT(6) ++#define MT_WLAN_FUN_CTRL_WAKE_HOST BIT(7) ++ ++#define MT_WLAN_FUN_CTRL_THERM_RST BIT(8) /* MT76x2 */ ++#define MT_WLAN_FUN_CTRL_THERM_CKEN BIT(9) /* MT76x2 */ ++ ++#define MT_WLAN_FUN_CTRL_GPIO_IN GENMASK(15, 8) /* MT76x0 */ ++#define MT_WLAN_FUN_CTRL_GPIO_OUT GENMASK(23, 16) /* MT76x0 */ ++#define MT_WLAN_FUN_CTRL_GPIO_OUT_EN GENMASK(31, 24) /* MT76x0 */ ++ ++#define MT_XO_CTRL0 0x0100 ++#define MT_XO_CTRL1 0x0104 ++#define MT_XO_CTRL2 0x0108 ++#define MT_XO_CTRL3 0x010c ++#define MT_XO_CTRL4 0x0110 ++ ++#define MT_XO_CTRL5 0x0114 ++#define MT_XO_CTRL5_C2_VAL GENMASK(14, 8) ++ ++#define MT_XO_CTRL6 0x0118 ++#define MT_XO_CTRL6_C2_CTRL GENMASK(14, 8) ++ ++#define MT_XO_CTRL7 0x011c ++ ++#define MT_WLAN_MTC_CTRL 0x10148 ++#define MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP BIT(0) ++#define MT_WLAN_MTC_CTRL_PWR_ACK BIT(12) ++#define MT_WLAN_MTC_CTRL_PWR_ACK_S BIT(13) ++#define MT_WLAN_MTC_CTRL_BBP_MEM_PD GENMASK(19, 16) ++#define MT_WLAN_MTC_CTRL_PBF_MEM_PD BIT(20) ++#define MT_WLAN_MTC_CTRL_FCE_MEM_PD BIT(21) ++#define MT_WLAN_MTC_CTRL_TSO_MEM_PD BIT(22) ++#define MT_WLAN_MTC_CTRL_BBP_MEM_RB BIT(24) ++#define MT_WLAN_MTC_CTRL_PBF_MEM_RB BIT(25) ++#define MT_WLAN_MTC_CTRL_FCE_MEM_RB BIT(26) ++#define MT_WLAN_MTC_CTRL_TSO_MEM_RB BIT(27) ++#define MT_WLAN_MTC_CTRL_STATE_UP BIT(28) ++ ++#define MT_INT_SOURCE_CSR 0x0200 ++#define MT_INT_MASK_CSR 0x0204 ++ ++#define MT_INT_RX_DONE(_n) BIT(_n) ++#define MT_INT_RX_DONE_ALL GENMASK(1, 0) ++#define MT_INT_TX_DONE_ALL GENMASK(13, 4) ++#define MT_INT_TX_DONE(_n) BIT(_n + 4) ++#define MT_INT_RX_COHERENT BIT(16) ++#define MT_INT_TX_COHERENT BIT(17) ++#define MT_INT_ANY_COHERENT BIT(18) ++#define MT_INT_MCU_CMD BIT(19) ++#define MT_INT_TBTT BIT(20) ++#define MT_INT_PRE_TBTT BIT(21) ++#define MT_INT_TX_STAT BIT(22) ++#define MT_INT_AUTO_WAKEUP BIT(23) ++#define MT_INT_GPTIMER BIT(24) ++#define MT_INT_RXDELAYINT BIT(26) ++#define MT_INT_TXDELAYINT BIT(27) ++ ++#define MT_WPDMA_GLO_CFG 0x0208 ++#define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0) ++#define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1) ++#define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2) ++#define MT_WPDMA_GLO_CFG_RX_DMA_BUSY BIT(3) ++#define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4) ++#define MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE BIT(6) ++#define MT_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7) ++#define MT_WPDMA_GLO_CFG_HDR_SEG_LEN GENMASK(15, 8) ++#define MT_WPDMA_GLO_CFG_CLK_GATE_DIS BIT(30) ++#define MT_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31) ++ ++#define MT_WPDMA_RST_IDX 0x020c ++ ++#define MT_WPDMA_DELAY_INT_CFG 0x0210 ++ ++#define MT_WMM_AIFSN 0x0214 ++#define MT_WMM_AIFSN_MASK GENMASK(3, 0) ++#define MT_WMM_AIFSN_SHIFT(_n) ((_n) * 4) ++ ++#define MT_WMM_CWMIN 0x0218 ++#define MT_WMM_CWMIN_MASK GENMASK(3, 0) ++#define MT_WMM_CWMIN_SHIFT(_n) ((_n) * 4) ++ ++#define MT_WMM_CWMAX 0x021c ++#define MT_WMM_CWMAX_MASK GENMASK(3, 0) ++#define MT_WMM_CWMAX_SHIFT(_n) ((_n) * 4) ++ ++#define MT_WMM_TXOP_BASE 0x0220 ++#define MT_WMM_TXOP(_n) (MT_WMM_TXOP_BASE + (((_n) / 2) << 2)) ++#define MT_WMM_TXOP_SHIFT(_n) ((_n & 1) * 16) ++#define MT_WMM_TXOP_MASK GENMASK(15, 0) ++ ++#define MT_FCE_DMA_ADDR 0x0230 ++#define MT_FCE_DMA_LEN 0x0234 ++ ++#define MT_USB_DMA_CFG 0x238 ++#define MT_USB_DMA_CFG_RX_BULK_AGG_TOUT GENMASK(7, 0) ++#define MT_USB_DMA_CFG_RX_BULK_AGG_LMT GENMASK(15, 8) ++#define MT_USB_DMA_CFG_PHY_CLR BIT(16) ++#define MT_USB_DMA_CFG_TX_CLR BIT(19) ++#define MT_USB_DMA_CFG_TXOP_HALT BIT(20) ++#define MT_USB_DMA_CFG_RX_BULK_AGG_EN BIT(21) ++#define MT_USB_DMA_CFG_RX_BULK_EN BIT(22) ++#define MT_USB_DMA_CFG_TX_BULK_EN BIT(23) ++#define MT_USB_DMA_CFG_UDMA_RX_WL_DROP BIT(25) ++#define MT_USB_DMA_CFG_EP_OUT_VALID GENMASK(29, 27) ++#define MT_USB_DMA_CFG_RX_BUSY BIT(30) ++#define MT_USB_DMA_CFG_TX_BUSY BIT(31) ++ ++#define MT_TSO_CTRL 0x0250 ++#define MT_HEADER_TRANS_CTRL_REG 0x0260 ++ ++#define MT_US_CYC_CFG 0x02a4 ++#define MT_US_CYC_CNT GENMASK(7, 0) ++ ++#define MT_TX_RING_BASE 0x0300 ++#define MT_RX_RING_BASE 0x03c0 ++#define MT_RING_SIZE 0x10 ++ ++#define MT_TX_HW_QUEUE_MCU 8 ++#define MT_TX_HW_QUEUE_MGMT 9 ++ ++#define MT_PBF_SYS_CTRL 0x0400 ++#define MT_PBF_SYS_CTRL_MCU_RESET BIT(0) ++#define MT_PBF_SYS_CTRL_DMA_RESET BIT(1) ++#define MT_PBF_SYS_CTRL_MAC_RESET BIT(2) ++#define MT_PBF_SYS_CTRL_PBF_RESET BIT(3) ++#define MT_PBF_SYS_CTRL_ASY_RESET BIT(4) ++ ++#define MT_PBF_CFG 0x0404 ++#define MT_PBF_CFG_TX0Q_EN BIT(0) ++#define MT_PBF_CFG_TX1Q_EN BIT(1) ++#define MT_PBF_CFG_TX2Q_EN BIT(2) ++#define MT_PBF_CFG_TX3Q_EN BIT(3) ++#define MT_PBF_CFG_RX0Q_EN BIT(4) ++#define MT_PBF_CFG_RX_DROP_EN BIT(8) ++ ++#define MT_PBF_TX_MAX_PCNT 0x0408 ++#define MT_PBF_RX_MAX_PCNT 0x040c ++ ++#define MT_BCN_OFFSET_BASE 0x041c ++#define MT_BCN_OFFSET(_n) (MT_BCN_OFFSET_BASE + ((_n) << 2)) ++ ++#define MT_RF_CSR_CFG 0x0500 ++#define MT_RF_CSR_CFG_DATA GENMASK(7, 0) ++#define MT_RF_CSR_CFG_REG_ID GENMASK(13, 8) ++#define MT_RF_CSR_CFG_REG_BANK GENMASK(17, 14) ++#define MT_RF_CSR_CFG_WR BIT(30) ++#define MT_RF_CSR_CFG_KICK BIT(31) ++ ++#define MT_RF_BYPASS_0 0x0504 ++#define MT_RF_BYPASS_1 0x0508 ++#define MT_RF_SETTING_0 0x050c ++ ++#define MT_RF_DATA_WRITE 0x0524 ++ ++#define MT_RF_CTRL 0x0528 ++#define MT_RF_CTRL_ADDR GENMASK(11, 0) ++#define MT_RF_CTRL_WRITE BIT(12) ++#define MT_RF_CTRL_BUSY BIT(13) ++#define MT_RF_CTRL_IDX BIT(16) ++ ++#define MT_RF_DATA_READ 0x052c ++ ++#define MT_FCE_PSE_CTRL 0x0800 ++#define MT_FCE_PARAMETERS 0x0804 ++#define MT_FCE_CSO 0x0808 ++ ++#define MT_FCE_L2_STUFF 0x080c ++#define MT_FCE_L2_STUFF_HT_L2_EN BIT(0) ++#define MT_FCE_L2_STUFF_QOS_L2_EN BIT(1) ++#define MT_FCE_L2_STUFF_RX_STUFF_EN BIT(2) ++#define MT_FCE_L2_STUFF_TX_STUFF_EN BIT(3) ++#define MT_FCE_L2_STUFF_WR_MPDU_LEN_EN BIT(4) ++#define MT_FCE_L2_STUFF_MVINV_BSWAP BIT(5) ++#define MT_FCE_L2_STUFF_TS_CMD_QSEL_EN GENMASK(15, 8) ++#define MT_FCE_L2_STUFF_TS_LEN_EN GENMASK(23, 16) ++#define MT_FCE_L2_STUFF_OTHER_PORT GENMASK(25, 24) ++ ++#define MT_FCE_WLAN_FLOW_CONTROL1 0x0824 ++ ++#define MT_TX_CPU_FROM_FCE_BASE_PTR 0x09a0 ++#define MT_TX_CPU_FROM_FCE_MAX_COUNT 0x09a4 ++#define MT_TX_CPU_FROM_FCE_CPU_DESC_IDX 0x09a8 ++ ++#define MT_FCE_PDMA_GLOBAL_CONF 0x09c4 ++ ++#define MT_PAUSE_ENABLE_CONTROL1 0x0a38 ++ ++#define MT_FCE_SKIP_FS 0x0a6c ++ ++#define MT_MAC_CSR0 0x1000 ++ ++#define MT_MAC_SYS_CTRL 0x1004 ++#define MT_MAC_SYS_CTRL_RESET_CSR BIT(0) ++#define MT_MAC_SYS_CTRL_RESET_BBP BIT(1) ++#define MT_MAC_SYS_CTRL_ENABLE_TX BIT(2) ++#define MT_MAC_SYS_CTRL_ENABLE_RX BIT(3) ++ ++#define MT_MAC_ADDR_DW0 0x1008 ++#define MT_MAC_ADDR_DW1 0x100c ++#define MT_MAC_ADDR_DW1_U2ME_MASK GENMASK(23, 16) ++ ++#define MT_MAC_BSSID_DW0 0x1010 ++#define MT_MAC_BSSID_DW1 0x1014 ++#define MT_MAC_BSSID_DW1_ADDR GENMASK(15, 0) ++#define MT_MAC_BSSID_DW1_MBSS_MODE GENMASK(17, 16) ++#define MT_MAC_BSSID_DW1_MBEACON_N GENMASK(20, 18) ++#define MT_MAC_BSSID_DW1_MBSS_LOCAL_BIT BIT(21) ++#define MT_MAC_BSSID_DW1_MBSS_MODE_B2 BIT(22) ++#define MT_MAC_BSSID_DW1_MBEACON_N_B3 BIT(23) ++#define MT_MAC_BSSID_DW1_MBSS_IDX_BYTE GENMASK(26, 24) ++ ++#define MT_MAX_LEN_CFG 0x1018 ++#define MT_MAX_LEN_CFG_AMPDU GENMASK(13, 12) ++ ++#define MT_BBP_CSR_CFG 0x101c ++#define MT_BBP_CSR_CFG_VAL GENMASK(7, 0) ++#define MT_BBP_CSR_CFG_REG_NUM GENMASK(15, 8) ++#define MT_BBP_CSR_CFG_READ BIT(16) ++#define MT_BBP_CSR_CFG_BUSY BIT(17) ++#define MT_BBP_CSR_CFG_PAR_DUR BIT(18) ++#define MT_BBP_CSR_CFG_RW_MODE BIT(19) ++ ++#define MT_AMPDU_MAX_LEN_20M1S 0x1030 ++#define MT_AMPDU_MAX_LEN_20M2S 0x1034 ++#define MT_AMPDU_MAX_LEN_40M1S 0x1038 ++#define MT_AMPDU_MAX_LEN_40M2S 0x103c ++#define MT_AMPDU_MAX_LEN 0x1040 ++ ++#define MT_WCID_DROP_BASE 0x106c ++#define MT_WCID_DROP(_n) (MT_WCID_DROP_BASE + ((_n) >> 5) * 4) ++#define MT_WCID_DROP_MASK(_n) BIT((_n) % 32) ++ ++#define MT_BCN_BYPASS_MASK 0x108c ++ ++#define MT_MAC_APC_BSSID_BASE 0x1090 ++#define MT_MAC_APC_BSSID_L(_n) (MT_MAC_APC_BSSID_BASE + ((_n) * 8)) ++#define MT_MAC_APC_BSSID_H(_n) (MT_MAC_APC_BSSID_BASE + ((_n) * 8 + 4)) ++#define MT_MAC_APC_BSSID_H_ADDR GENMASK(15, 0) ++#define MT_MAC_APC_BSSID0_H_EN BIT(16) ++ ++#define MT_XIFS_TIME_CFG 0x1100 ++#define MT_XIFS_TIME_CFG_CCK_SIFS GENMASK(7, 0) ++#define MT_XIFS_TIME_CFG_OFDM_SIFS GENMASK(15, 8) ++#define MT_XIFS_TIME_CFG_OFDM_XIFS GENMASK(19, 16) ++#define MT_XIFS_TIME_CFG_EIFS GENMASK(28, 20) ++#define MT_XIFS_TIME_CFG_BB_RXEND_EN BIT(29) ++ ++#define MT_BKOFF_SLOT_CFG 0x1104 ++#define MT_BKOFF_SLOT_CFG_SLOTTIME GENMASK(7, 0) ++#define MT_BKOFF_SLOT_CFG_CC_DELAY GENMASK(11, 8) ++ ++#define MT_BEACON_TIME_CFG 0x1114 ++#define MT_BEACON_TIME_CFG_INTVAL GENMASK(15, 0) ++#define MT_BEACON_TIME_CFG_TIMER_EN BIT(16) ++#define MT_BEACON_TIME_CFG_SYNC_MODE GENMASK(18, 17) ++#define MT_BEACON_TIME_CFG_TBTT_EN BIT(19) ++#define MT_BEACON_TIME_CFG_BEACON_TX BIT(20) ++#define MT_BEACON_TIME_CFG_TSF_COMP GENMASK(31, 24) ++ ++#define MT_TBTT_SYNC_CFG 0x1118 ++#define MT_TBTT_TIMER_CFG 0x1124 ++ ++#define MT_INT_TIMER_CFG 0x1128 ++#define MT_INT_TIMER_CFG_PRE_TBTT GENMASK(15, 0) ++#define MT_INT_TIMER_CFG_GP_TIMER GENMASK(31, 16) ++ ++#define MT_INT_TIMER_EN 0x112c ++#define MT_INT_TIMER_EN_PRE_TBTT_EN BIT(0) ++#define MT_INT_TIMER_EN_GP_TIMER_EN BIT(1) ++ ++#define MT_MAC_STATUS 0x1200 ++#define MT_MAC_STATUS_TX BIT(0) ++#define MT_MAC_STATUS_RX BIT(1) ++ ++#define MT_PWR_PIN_CFG 0x1204 ++#define MT_AUX_CLK_CFG 0x120c ++ ++#define MT_BB_PA_MODE_CFG0 0x1214 ++#define MT_BB_PA_MODE_CFG1 0x1218 ++#define MT_RF_PA_MODE_CFG0 0x121c ++#define MT_RF_PA_MODE_CFG1 0x1220 ++ ++#define MT_RF_PA_MODE_ADJ0 0x1228 ++#define MT_RF_PA_MODE_ADJ1 0x122c ++ ++#define MT_DACCLK_EN_DLY_CFG 0x1264 ++ ++#define MT_EDCA_CFG_BASE 0x1300 ++#define MT_EDCA_CFG_AC(_n) (MT_EDCA_CFG_BASE + ((_n) << 2)) ++#define MT_EDCA_CFG_TXOP GENMASK(7, 0) ++#define MT_EDCA_CFG_AIFSN GENMASK(11, 8) ++#define MT_EDCA_CFG_CWMIN GENMASK(15, 12) ++#define MT_EDCA_CFG_CWMAX GENMASK(19, 16) ++ ++#define MT_TX_PWR_CFG_0 0x1314 ++#define MT_TX_PWR_CFG_1 0x1318 ++#define MT_TX_PWR_CFG_2 0x131c ++#define MT_TX_PWR_CFG_3 0x1320 ++#define MT_TX_PWR_CFG_4 0x1324 ++ ++#define MT_TX_BAND_CFG 0x132c ++#define MT_TX_BAND_CFG_UPPER_40M BIT(0) ++#define MT_TX_BAND_CFG_5G BIT(1) ++#define MT_TX_BAND_CFG_2G BIT(2) ++ ++#define MT_HT_FBK_TO_LEGACY 0x1384 ++#define MT_TX_MPDU_ADJ_INT 0x1388 ++ ++#define MT_TX_PWR_CFG_7 0x13d4 ++#define MT_TX_PWR_CFG_8 0x13d8 ++#define MT_TX_PWR_CFG_9 0x13dc ++ ++#define MT_TX_SW_CFG0 0x1330 ++#define MT_TX_SW_CFG1 0x1334 ++#define MT_TX_SW_CFG2 0x1338 ++ ++#define MT_TXOP_CTRL_CFG 0x1340 ++#define MT_TXOP_TRUN_EN GENMASK(5, 0) ++#define MT_TXOP_EXT_CCA_DLY GENMASK(15, 8) ++#define MT_TXOP_CTRL ++ ++#define MT_TX_RTS_CFG 0x1344 ++#define MT_TX_RTS_CFG_RETRY_LIMIT GENMASK(7, 0) ++#define MT_TX_RTS_CFG_THRESH GENMASK(23, 8) ++#define MT_TX_RTS_FALLBACK BIT(24) ++ ++#define MT_TX_TIMEOUT_CFG 0x1348 ++#define MT_TX_RETRY_CFG 0x134c ++#define MT_TX_LINK_CFG 0x1350 ++#define MT_HT_FBK_CFG0 0x1354 ++#define MT_HT_FBK_CFG1 0x1358 ++#define MT_LG_FBK_CFG0 0x135c ++#define MT_LG_FBK_CFG1 0x1360 ++ ++#define MT_CCK_PROT_CFG 0x1364 ++#define MT_OFDM_PROT_CFG 0x1368 ++#define MT_MM20_PROT_CFG 0x136c ++#define MT_MM40_PROT_CFG 0x1370 ++#define MT_GF20_PROT_CFG 0x1374 ++#define MT_GF40_PROT_CFG 0x1378 ++ ++#define MT_PROT_RATE GENMASK(15, 0) ++#define MT_PROT_CTRL_RTS_CTS BIT(16) ++#define MT_PROT_CTRL_CTS2SELF BIT(17) ++#define MT_PROT_NAV_SHORT BIT(18) ++#define MT_PROT_NAV_LONG BIT(19) ++#define MT_PROT_TXOP_ALLOW_CCK BIT(20) ++#define MT_PROT_TXOP_ALLOW_OFDM BIT(21) ++#define MT_PROT_TXOP_ALLOW_MM20 BIT(22) ++#define MT_PROT_TXOP_ALLOW_MM40 BIT(23) ++#define MT_PROT_TXOP_ALLOW_GF20 BIT(24) ++#define MT_PROT_TXOP_ALLOW_GF40 BIT(25) ++#define MT_PROT_RTS_THR_EN BIT(26) ++#define MT_PROT_RATE_CCK_11 0x0003 ++#define MT_PROT_RATE_OFDM_6 0x4000 ++#define MT_PROT_RATE_OFDM_24 0x4004 ++#define MT_PROT_RATE_DUP_OFDM_24 0x4084 ++#define MT_PROT_TXOP_ALLOW_ALL GENMASK(25, 20) ++#define MT_PROT_TXOP_ALLOW_BW20 (MT_PROT_TXOP_ALLOW_ALL & \ ++ ~MT_PROT_TXOP_ALLOW_MM40 & \ ++ ~MT_PROT_TXOP_ALLOW_GF40) ++ ++#define MT_EXP_ACK_TIME 0x1380 ++ ++#define MT_TX_PWR_CFG_0_EXT 0x1390 ++#define MT_TX_PWR_CFG_1_EXT 0x1394 ++ ++#define MT_TX_FBK_LIMIT 0x1398 ++#define MT_TX_FBK_LIMIT_MPDU_FBK GENMASK(7, 0) ++#define MT_TX_FBK_LIMIT_AMPDU_FBK GENMASK(15, 8) ++#define MT_TX_FBK_LIMIT_MPDU_UP_CLEAR BIT(16) ++#define MT_TX_FBK_LIMIT_AMPDU_UP_CLEAR BIT(17) ++#define MT_TX_FBK_LIMIT_RATE_LUT BIT(18) ++ ++#define MT_TX0_RF_GAIN_CORR 0x13a0 ++#define MT_TX1_RF_GAIN_CORR 0x13a4 ++#define MT_TX0_RF_GAIN_ATTEN 0x13a8 ++ ++#define MT_TX_ALC_CFG_0 0x13b0 ++#define MT_TX_ALC_CFG_0_CH_INIT_0 GENMASK(5, 0) ++#define MT_TX_ALC_CFG_0_CH_INIT_1 GENMASK(13, 8) ++#define MT_TX_ALC_CFG_0_LIMIT_0 GENMASK(21, 16) ++#define MT_TX_ALC_CFG_0_LIMIT_1 GENMASK(29, 24) ++ ++#define MT_TX_ALC_CFG_1 0x13b4 ++#define MT_TX_ALC_CFG_1_TEMP_COMP GENMASK(5, 0) ++ ++#define MT_TX_ALC_CFG_2 0x13a8 ++#define MT_TX_ALC_CFG_2_TEMP_COMP GENMASK(5, 0) ++ ++#define MT_TX0_BB_GAIN_ATTEN 0x13c0 ++ ++#define MT_TX_ALC_VGA3 0x13c8 ++ ++#define MT_TX_PROT_CFG6 0x13e0 ++#define MT_TX_PROT_CFG7 0x13e4 ++#define MT_TX_PROT_CFG8 0x13e8 ++ ++#define MT_PIFS_TX_CFG 0x13ec ++ ++#define MT_RX_FILTR_CFG 0x1400 ++ ++#define MT_RX_FILTR_CFG_CRC_ERR BIT(0) ++#define MT_RX_FILTR_CFG_PHY_ERR BIT(1) ++#define MT_RX_FILTR_CFG_PROMISC BIT(2) ++#define MT_RX_FILTR_CFG_OTHER_BSS BIT(3) ++#define MT_RX_FILTR_CFG_VER_ERR BIT(4) ++#define MT_RX_FILTR_CFG_MCAST BIT(5) ++#define MT_RX_FILTR_CFG_BCAST BIT(6) ++#define MT_RX_FILTR_CFG_DUP BIT(7) ++#define MT_RX_FILTR_CFG_CFACK BIT(8) ++#define MT_RX_FILTR_CFG_CFEND BIT(9) ++#define MT_RX_FILTR_CFG_ACK BIT(10) ++#define MT_RX_FILTR_CFG_CTS BIT(11) ++#define MT_RX_FILTR_CFG_RTS BIT(12) ++#define MT_RX_FILTR_CFG_PSPOLL BIT(13) ++#define MT_RX_FILTR_CFG_BA BIT(14) ++#define MT_RX_FILTR_CFG_BAR BIT(15) ++#define MT_RX_FILTR_CFG_CTRL_RSV BIT(16) ++ ++#define MT_AUTO_RSP_CFG 0x1404 ++ ++#define MT_AUTO_RSP_PREAMB_SHORT BIT(4) ++ ++#define MT_LEGACY_BASIC_RATE 0x1408 ++#define MT_HT_BASIC_RATE 0x140c ++ ++#define MT_RX_PARSER_CFG 0x1418 ++#define MT_RX_PARSER_RX_SET_NAV_ALL BIT(0) ++ ++#define MT_EXT_CCA_CFG 0x141c ++#define MT_EXT_CCA_CFG_CCA0 GENMASK(1, 0) ++#define MT_EXT_CCA_CFG_CCA1 GENMASK(3, 2) ++#define MT_EXT_CCA_CFG_CCA2 GENMASK(5, 4) ++#define MT_EXT_CCA_CFG_CCA3 GENMASK(7, 6) ++#define MT_EXT_CCA_CFG_CCA_MASK GENMASK(11, 8) ++#define MT_EXT_CCA_CFG_ED_CCA_MASK GENMASK(15, 12) ++ ++#define MT_TX_SW_CFG3 0x1478 ++ ++#define MT_PN_PAD_MODE 0x150c ++ ++#define MT_TXOP_HLDR_ET 0x1608 ++ ++#define MT_PROT_AUTO_TX_CFG 0x1648 ++ ++#define MT_RX_STA_CNT0 0x1700 ++#define MT_RX_STA_CNT1 0x1704 ++#define MT_RX_STA_CNT2 0x1708 ++#define MT_TX_STA_CNT0 0x170c ++#define MT_TX_STA_CNT1 0x1710 ++#define MT_TX_STA_CNT2 0x1714 ++ ++/* Vendor driver defines content of the second word of STAT_FIFO as follows: ++ * MT_TX_STAT_FIFO_RATE GENMASK(26, 16) ++ * MT_TX_STAT_FIFO_ETXBF BIT(27) ++ * MT_TX_STAT_FIFO_SND BIT(28) ++ * MT_TX_STAT_FIFO_ITXBF BIT(29) ++ * However, tests show that b16-31 have the same layout as TXWI rate_ctl ++ * with rate set to rate at which frame was acked. ++ */ ++#define MT_TX_STAT_FIFO 0x1718 ++#define MT_TX_STAT_FIFO_VALID BIT(0) ++#define MT_TX_STAT_FIFO_PID_TYPE GENMASK(4, 1) ++#define MT_TX_STAT_FIFO_SUCCESS BIT(5) ++#define MT_TX_STAT_FIFO_AGGR BIT(6) ++#define MT_TX_STAT_FIFO_ACKREQ BIT(7) ++#define MT_TX_STAT_FIFO_WCID GENMASK(15, 8) ++#define MT_TX_STAT_FIFO_RATE GENMASK(31, 16) ++ ++#define MT_TX_AGG_STAT 0x171c ++ ++#define MT_TX_AGG_CNT_BASE0 0x1720 ++ ++#define MT_MPDU_DENSITY_CNT 0x1740 ++ ++#define MT_TX_AGG_CNT_BASE1 0x174c ++ ++#define MT_TX_AGG_CNT(_id) ((_id) < 8 ? \ ++ MT_TX_AGG_CNT_BASE0 + ((_id) << 2) : \ ++ MT_TX_AGG_CNT_BASE1 + ((_id - 8) << 2)) ++ ++#define MT_TX_STAT_FIFO_EXT 0x1798 ++#define MT_TX_STAT_FIFO_EXT_RETRY GENMASK(7, 0) ++ ++#define MT_BBP_CORE_BASE 0x2000 ++#define MT_BBP_IBI_BASE 0x2100 ++#define MT_BBP_AGC_BASE 0x2300 ++#define MT_BBP_TXC_BASE 0x2400 ++#define MT_BBP_RXC_BASE 0x2500 ++#define MT_BBP_TXO_BASE 0x2600 ++#define MT_BBP_TXBE_BASE 0x2700 ++#define MT_BBP_RXFE_BASE 0x2800 ++#define MT_BBP_RXO_BASE 0x2900 ++#define MT_BBP_DFS_BASE 0x2a00 ++#define MT_BBP_TR_BASE 0x2b00 ++#define MT_BBP_CAL_BASE 0x2c00 ++#define MT_BBP_DSC_BASE 0x2e00 ++#define MT_BBP_PFMU_BASE 0x2f00 ++ ++#define MT_BBP(_type, _n) (MT_BBP_##_type##_BASE + ((_n) << 2)) ++ ++#define MT_BBP_CORE_R1_BW GENMASK(4, 3) ++ ++#define MT_BBP_AGC_R0_CTRL_CHAN GENMASK(9, 8) ++#define MT_BBP_AGC_R0_BW GENMASK(14, 12) ++ ++/* AGC, R4/R5 */ ++#define MT_BBP_AGC_LNA_GAIN GENMASK(21, 16) ++ ++/* AGC, R8/R9 */ ++#define MT_BBP_AGC_GAIN GENMASK(14, 8) ++ ++#define MT_BBP_AGC20_RSSI0 GENMASK(7, 0) ++#define MT_BBP_AGC20_RSSI1 GENMASK(15, 8) ++ ++#define MT_BBP_TXBE_R0_CTRL_CHAN GENMASK(1, 0) ++ ++#define MT_WCID_ADDR_BASE 0x1800 ++#define MT_WCID_ADDR(_n) (MT_WCID_ADDR_BASE + (_n) * 8) ++ ++#define MT_SRAM_BASE 0x4000 ++ ++#define MT_WCID_KEY_BASE 0x8000 ++#define MT_WCID_KEY(_n) (MT_WCID_KEY_BASE + (_n) * 32) ++ ++#define MT_WCID_IV_BASE 0xa000 ++#define MT_WCID_IV(_n) (MT_WCID_IV_BASE + (_n) * 8) ++ ++#define MT_WCID_ATTR_BASE 0xa800 ++#define MT_WCID_ATTR(_n) (MT_WCID_ATTR_BASE + (_n) * 4) ++ ++#define MT_WCID_ATTR_PAIRWISE BIT(0) ++#define MT_WCID_ATTR_PKEY_MODE GENMASK(3, 1) ++#define MT_WCID_ATTR_BSS_IDX GENMASK(6, 4) ++#define MT_WCID_ATTR_RXWI_UDF GENMASK(9, 7) ++#define MT_WCID_ATTR_PKEY_MODE_EXT BIT(10) ++#define MT_WCID_ATTR_BSS_IDX_EXT BIT(11) ++#define MT_WCID_ATTR_WAPI_MCBC BIT(15) ++#define MT_WCID_ATTR_WAPI_KEYID GENMASK(31, 24) ++ ++#define MT_SKEY_BASE_0 0xac00 ++#define MT_SKEY_BASE_1 0xb400 ++#define MT_SKEY_0(_bss, _idx) \ ++ (MT_SKEY_BASE_0 + (4 * (_bss) + _idx) * 32) ++#define MT_SKEY_1(_bss, _idx) \ ++ (MT_SKEY_BASE_1 + (4 * ((_bss) & 7) + _idx) * 32) ++#define MT_SKEY(_bss, _idx) \ ++ ((_bss & 8) ? MT_SKEY_1(_bss, _idx) : MT_SKEY_0(_bss, _idx)) ++ ++#define MT_SKEY_MODE_BASE_0 0xb000 ++#define MT_SKEY_MODE_BASE_1 0xb3f0 ++#define MT_SKEY_MODE_0(_bss) \ ++ (MT_SKEY_MODE_BASE_0 + ((_bss / 2) << 2)) ++#define MT_SKEY_MODE_1(_bss) \ ++ (MT_SKEY_MODE_BASE_1 + ((((_bss) & 7) / 2) << 2)) ++#define MT_SKEY_MODE(_bss) \ ++ ((_bss & 8) ? MT_SKEY_MODE_1(_bss) : MT_SKEY_MODE_0(_bss)) ++#define MT_SKEY_MODE_MASK GENMASK(3, 0) ++#define MT_SKEY_MODE_SHIFT(_bss, _idx) (4 * ((_idx) + 4 * (_bss & 1))) ++ ++#define MT_BEACON_BASE 0xc000 ++ ++#define MT_TEMP_SENSOR 0x1d000 ++#define MT_TEMP_SENSOR_VAL GENMASK(6, 0) ++ ++enum mt76_cipher_type { ++ MT_CIPHER_NONE, ++ MT_CIPHER_WEP40, ++ MT_CIPHER_WEP104, ++ MT_CIPHER_TKIP, ++ MT_CIPHER_AES_CCMP, ++ MT_CIPHER_CKIP40, ++ MT_CIPHER_CKIP104, ++ MT_CIPHER_CKIP128, ++ MT_CIPHER_WAPI, ++}; ++ ++#endif +diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/trace.c linux-rpi/drivers/net/wireless/mediatek/mt7601u/trace.c +--- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/trace.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/trace.c 2015-11-29 09:42:38.887167260 +0100 +@@ -0,0 +1,21 @@ ++/* ++ * Copyright (C) 2014 Felix Fietkau ++ * Copyright (C) 2015 Jakub Kicinski ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 ++ * as published by the Free Software Foundation ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++ ++#ifndef __CHECKER__ ++#define CREATE_TRACE_POINTS ++#include "trace.h" ++ ++#endif +diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/trace.h linux-rpi/drivers/net/wireless/mediatek/mt7601u/trace.h +--- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/trace.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/trace.h 2015-11-29 09:42:38.887167260 +0100 +@@ -0,0 +1,400 @@ ++/* ++ * Copyright (C) 2014 Felix Fietkau ++ * Copyright (C) 2015 Jakub Kicinski ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 ++ * as published by the Free Software Foundation ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#if !defined(__MT7601U_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) ++#define __MT7601U_TRACE_H ++ ++#include ++#include "mt7601u.h" ++#include "mac.h" ++ ++#undef TRACE_SYSTEM ++#define TRACE_SYSTEM mt7601u ++ ++#define MAXNAME 32 ++#define DEV_ENTRY __array(char, wiphy_name, 32) ++#define DEV_ASSIGN strlcpy(__entry->wiphy_name, \ ++ wiphy_name(dev->hw->wiphy), MAXNAME) ++#define DEV_PR_FMT "%s " ++#define DEV_PR_ARG __entry->wiphy_name ++ ++#define REG_ENTRY __field(u32, reg) __field(u32, val) ++#define REG_ASSIGN __entry->reg = reg; __entry->val = val ++#define REG_PR_FMT "%04x=%08x" ++#define REG_PR_ARG __entry->reg, __entry->val ++ ++DECLARE_EVENT_CLASS(dev_reg_evt, ++ TP_PROTO(struct mt7601u_dev *dev, u32 reg, u32 val), ++ TP_ARGS(dev, reg, val), ++ TP_STRUCT__entry( ++ DEV_ENTRY ++ REG_ENTRY ++ ), ++ TP_fast_assign( ++ DEV_ASSIGN; ++ REG_ASSIGN; ++ ), ++ TP_printk( ++ DEV_PR_FMT REG_PR_FMT, ++ DEV_PR_ARG, REG_PR_ARG ++ ) ++); ++ ++DEFINE_EVENT(dev_reg_evt, reg_read, ++ TP_PROTO(struct mt7601u_dev *dev, u32 reg, u32 val), ++ TP_ARGS(dev, reg, val) ++); ++ ++DEFINE_EVENT(dev_reg_evt, reg_write, ++ TP_PROTO(struct mt7601u_dev *dev, u32 reg, u32 val), ++ TP_ARGS(dev, reg, val) ++); ++ ++TRACE_EVENT(mt_submit_urb, ++ TP_PROTO(struct mt7601u_dev *dev, struct urb *u), ++ TP_ARGS(dev, u), ++ TP_STRUCT__entry( ++ DEV_ENTRY __field(unsigned, pipe) __field(u32, len) ++ ), ++ TP_fast_assign( ++ DEV_ASSIGN; ++ __entry->pipe = u->pipe; ++ __entry->len = u->transfer_buffer_length; ++ ), ++ TP_printk(DEV_PR_FMT "p:%08x len:%u", ++ DEV_PR_ARG, __entry->pipe, __entry->len) ++); ++ ++#define trace_mt_submit_urb_sync(__dev, __pipe, __len) ({ \ ++ struct urb u; \ ++ u.pipe = __pipe; \ ++ u.transfer_buffer_length = __len; \ ++ trace_mt_submit_urb(__dev, &u); \ ++}) ++ ++TRACE_EVENT(mt_mcu_msg_send, ++ TP_PROTO(struct mt7601u_dev *dev, ++ struct sk_buff *skb, u32 csum, bool resp), ++ TP_ARGS(dev, skb, csum, resp), ++ TP_STRUCT__entry( ++ DEV_ENTRY ++ __field(u32, info) ++ __field(u32, csum) ++ __field(bool, resp) ++ ), ++ TP_fast_assign( ++ DEV_ASSIGN; ++ __entry->info = *(u32 *)skb->data; ++ __entry->csum = csum; ++ __entry->resp = resp; ++ ), ++ TP_printk(DEV_PR_FMT "i:%08x c:%08x r:%d", ++ DEV_PR_ARG, __entry->info, __entry->csum, __entry->resp) ++); ++ ++TRACE_EVENT(mt_vend_req, ++ TP_PROTO(struct mt7601u_dev *dev, unsigned pipe, u8 req, u8 req_type, ++ u16 val, u16 offset, void *buf, size_t buflen, int ret), ++ TP_ARGS(dev, pipe, req, req_type, val, offset, buf, buflen, ret), ++ TP_STRUCT__entry( ++ DEV_ENTRY ++ __field(unsigned, pipe) __field(u8, req) __field(u8, req_type) ++ __field(u16, val) __field(u16, offset) __field(void*, buf) ++ __field(int, buflen) __field(int, ret) ++ ), ++ TP_fast_assign( ++ DEV_ASSIGN; ++ __entry->pipe = pipe; ++ __entry->req = req; ++ __entry->req_type = req_type; ++ __entry->val = val; ++ __entry->offset = offset; ++ __entry->buf = buf; ++ __entry->buflen = buflen; ++ __entry->ret = ret; ++ ), ++ TP_printk(DEV_PR_FMT ++ "%d p:%08x req:%02hhx %02hhx val:%04hx %04hx buf:%d %d", ++ DEV_PR_ARG, __entry->ret, __entry->pipe, __entry->req, ++ __entry->req_type, __entry->val, __entry->offset, ++ !!__entry->buf, __entry->buflen) ++); ++ ++TRACE_EVENT(ee_read, ++ TP_PROTO(struct mt7601u_dev *dev, int offset, u16 val), ++ TP_ARGS(dev, offset, val), ++ TP_STRUCT__entry( ++ DEV_ENTRY ++ __field(int, o) __field(u16, v) ++ ), ++ TP_fast_assign( ++ DEV_ASSIGN; ++ __entry->o = offset; ++ __entry->v = val; ++ ), ++ TP_printk(DEV_PR_FMT "%04x=%04x", DEV_PR_ARG, __entry->o, __entry->v) ++); ++ ++DECLARE_EVENT_CLASS(dev_rf_reg_evt, ++ TP_PROTO(struct mt7601u_dev *dev, u8 bank, u8 reg, u8 val), ++ TP_ARGS(dev, bank, reg, val), ++ TP_STRUCT__entry( ++ DEV_ENTRY ++ __field(u8, bank) ++ __field(u8, reg) ++ __field(u8, val) ++ ), ++ TP_fast_assign( ++ DEV_ASSIGN; ++ REG_ASSIGN; ++ __entry->bank = bank; ++ ), ++ TP_printk( ++ DEV_PR_FMT "%02hhx:%02hhx=%02hhx", ++ DEV_PR_ARG, __entry->bank, __entry->reg, __entry->val ++ ) ++); ++ ++DEFINE_EVENT(dev_rf_reg_evt, rf_read, ++ TP_PROTO(struct mt7601u_dev *dev, u8 bank, u8 reg, u8 val), ++ TP_ARGS(dev, bank, reg, val) ++); ++ ++DEFINE_EVENT(dev_rf_reg_evt, rf_write, ++ TP_PROTO(struct mt7601u_dev *dev, u8 bank, u8 reg, u8 val), ++ TP_ARGS(dev, bank, reg, val) ++); ++ ++DECLARE_EVENT_CLASS(dev_bbp_reg_evt, ++ TP_PROTO(struct mt7601u_dev *dev, u8 reg, u8 val), ++ TP_ARGS(dev, reg, val), ++ TP_STRUCT__entry( ++ DEV_ENTRY ++ __field(u8, reg) ++ __field(u8, val) ++ ), ++ TP_fast_assign( ++ DEV_ASSIGN; ++ REG_ASSIGN; ++ ), ++ TP_printk( ++ DEV_PR_FMT "%02hhx=%02hhx", ++ DEV_PR_ARG, __entry->reg, __entry->val ++ ) ++); ++ ++DEFINE_EVENT(dev_bbp_reg_evt, bbp_read, ++ TP_PROTO(struct mt7601u_dev *dev, u8 reg, u8 val), ++ TP_ARGS(dev, reg, val) ++); ++ ++DEFINE_EVENT(dev_bbp_reg_evt, bbp_write, ++ TP_PROTO(struct mt7601u_dev *dev, u8 reg, u8 val), ++ TP_ARGS(dev, reg, val) ++); ++ ++DECLARE_EVENT_CLASS(dev_simple_evt, ++ TP_PROTO(struct mt7601u_dev *dev, u8 val), ++ TP_ARGS(dev, val), ++ TP_STRUCT__entry( ++ DEV_ENTRY ++ __field(u8, val) ++ ), ++ TP_fast_assign( ++ DEV_ASSIGN; ++ __entry->val = val; ++ ), ++ TP_printk( ++ DEV_PR_FMT "%02hhx", DEV_PR_ARG, __entry->val ++ ) ++); ++ ++DEFINE_EVENT(dev_simple_evt, temp_mode, ++ TP_PROTO(struct mt7601u_dev *dev, u8 val), ++ TP_ARGS(dev, val) ++); ++ ++DEFINE_EVENT(dev_simple_evt, read_temp, ++ TP_PROTO(struct mt7601u_dev *dev, u8 val), ++ TP_ARGS(dev, val) ++); ++ ++DEFINE_EVENT(dev_simple_evt, freq_cal_adjust, ++ TP_PROTO(struct mt7601u_dev *dev, u8 val), ++ TP_ARGS(dev, val) ++); ++ ++TRACE_EVENT(freq_cal_offset, ++ TP_PROTO(struct mt7601u_dev *dev, u8 phy_mode, s8 freq_off), ++ TP_ARGS(dev, phy_mode, freq_off), ++ TP_STRUCT__entry( ++ DEV_ENTRY ++ __field(u8, phy_mode) ++ __field(s8, freq_off) ++ ), ++ TP_fast_assign( ++ DEV_ASSIGN; ++ __entry->phy_mode = phy_mode; ++ __entry->freq_off = freq_off; ++ ), ++ TP_printk(DEV_PR_FMT "phy:%02hhx off:%02hhx", ++ DEV_PR_ARG, __entry->phy_mode, __entry->freq_off) ++); ++ ++TRACE_EVENT(mt_rx, ++ TP_PROTO(struct mt7601u_dev *dev, struct mt7601u_rxwi *rxwi, u32 f), ++ TP_ARGS(dev, rxwi, f), ++ TP_STRUCT__entry( ++ DEV_ENTRY ++ __field_struct(struct mt7601u_rxwi, rxwi) ++ __field(u32, fce_info) ++ ), ++ TP_fast_assign( ++ DEV_ASSIGN; ++ __entry->rxwi = *rxwi; ++ __entry->fce_info = f; ++ ), ++ TP_printk(DEV_PR_FMT "rxi:%08x ctl:%08x frag_sn:%04hx rate:%04hx " ++ "uknw:%02hhx z:%02hhx%02hhx%02hhx snr:%02hhx " ++ "ant:%02hhx gain:%02hhx freq_o:%02hhx " ++ "r:%08x ea:%08x fce:%08x", DEV_PR_ARG, ++ le32_to_cpu(__entry->rxwi.rxinfo), ++ le32_to_cpu(__entry->rxwi.ctl), ++ le16_to_cpu(__entry->rxwi.frag_sn), ++ le16_to_cpu(__entry->rxwi.rate), ++ __entry->rxwi.unknown, ++ __entry->rxwi.zero[0], __entry->rxwi.zero[1], ++ __entry->rxwi.zero[2], ++ __entry->rxwi.snr, __entry->rxwi.ant, ++ __entry->rxwi.gain, __entry->rxwi.freq_off, ++ __entry->rxwi.resv2, __entry->rxwi.expert_ant, ++ __entry->fce_info) ++); ++ ++TRACE_EVENT(mt_tx, ++ TP_PROTO(struct mt7601u_dev *dev, struct sk_buff *skb, ++ struct mt76_sta *sta, struct mt76_txwi *h), ++ TP_ARGS(dev, skb, sta, h), ++ TP_STRUCT__entry( ++ DEV_ENTRY ++ __field_struct(struct mt76_txwi, h) ++ __field(struct sk_buff *, skb) ++ __field(struct mt76_sta *, sta) ++ ), ++ TP_fast_assign( ++ DEV_ASSIGN; ++ __entry->h = *h; ++ __entry->skb = skb; ++ __entry->sta = sta; ++ ), ++ TP_printk(DEV_PR_FMT "skb:%p sta:%p flg:%04hx rate_ctl:%04hx " ++ "ack:%02hhx wcid:%02hhx len_ctl:%05hx", DEV_PR_ARG, ++ __entry->skb, __entry->sta, ++ le16_to_cpu(__entry->h.flags), ++ le16_to_cpu(__entry->h.rate_ctl), ++ __entry->h.ack_ctl, __entry->h.wcid, ++ le16_to_cpu(__entry->h.len_ctl)) ++); ++ ++TRACE_EVENT(mt_tx_dma_done, ++ TP_PROTO(struct mt7601u_dev *dev, struct sk_buff *skb), ++ TP_ARGS(dev, skb), ++ TP_STRUCT__entry( ++ DEV_ENTRY ++ __field(struct sk_buff *, skb) ++ ), ++ TP_fast_assign( ++ DEV_ASSIGN; ++ __entry->skb = skb; ++ ), ++ TP_printk(DEV_PR_FMT "%p", DEV_PR_ARG, __entry->skb) ++); ++ ++TRACE_EVENT(mt_tx_status_cleaned, ++ TP_PROTO(struct mt7601u_dev *dev, int cleaned), ++ TP_ARGS(dev, cleaned), ++ TP_STRUCT__entry( ++ DEV_ENTRY ++ __field(int, cleaned) ++ ), ++ TP_fast_assign( ++ DEV_ASSIGN; ++ __entry->cleaned = cleaned; ++ ), ++ TP_printk(DEV_PR_FMT "%d", DEV_PR_ARG, __entry->cleaned) ++); ++ ++TRACE_EVENT(mt_tx_status, ++ TP_PROTO(struct mt7601u_dev *dev, u32 stat1, u32 stat2), ++ TP_ARGS(dev, stat1, stat2), ++ TP_STRUCT__entry( ++ DEV_ENTRY ++ __field(u32, stat1) __field(u32, stat2) ++ ), ++ TP_fast_assign( ++ DEV_ASSIGN; ++ __entry->stat1 = stat1; ++ __entry->stat2 = stat2; ++ ), ++ TP_printk(DEV_PR_FMT "%08x %08x", ++ DEV_PR_ARG, __entry->stat1, __entry->stat2) ++); ++ ++TRACE_EVENT(mt_rx_dma_aggr, ++ TP_PROTO(struct mt7601u_dev *dev, int cnt, bool paged), ++ TP_ARGS(dev, cnt, paged), ++ TP_STRUCT__entry( ++ DEV_ENTRY ++ __field(u8, cnt) ++ __field(bool, paged) ++ ), ++ TP_fast_assign( ++ DEV_ASSIGN; ++ __entry->cnt = cnt; ++ __entry->paged = paged; ++ ), ++ TP_printk(DEV_PR_FMT "cnt:%d paged:%d", ++ DEV_PR_ARG, __entry->cnt, __entry->paged) ++); ++ ++DEFINE_EVENT(dev_simple_evt, set_key, ++ TP_PROTO(struct mt7601u_dev *dev, u8 val), ++ TP_ARGS(dev, val) ++); ++ ++TRACE_EVENT(set_shared_key, ++ TP_PROTO(struct mt7601u_dev *dev, u8 vid, u8 key), ++ TP_ARGS(dev, vid, key), ++ TP_STRUCT__entry( ++ DEV_ENTRY ++ __field(u8, vid) ++ __field(u8, key) ++ ), ++ TP_fast_assign( ++ DEV_ASSIGN; ++ __entry->vid = vid; ++ __entry->key = key; ++ ), ++ TP_printk(DEV_PR_FMT "phy:%02hhx off:%02hhx", ++ DEV_PR_ARG, __entry->vid, __entry->key) ++); ++ ++#endif ++ ++#undef TRACE_INCLUDE_PATH ++#define TRACE_INCLUDE_PATH . ++#undef TRACE_INCLUDE_FILE ++#define TRACE_INCLUDE_FILE trace ++ ++#include +diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/tx.c linux-rpi/drivers/net/wireless/mediatek/mt7601u/tx.c +--- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/tx.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/tx.c 2015-11-29 09:42:38.887167260 +0100 +@@ -0,0 +1,322 @@ ++/* ++ * Copyright (C) 2014 Felix Fietkau ++ * Copyright (C) 2015 Jakub Kicinski ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 ++ * as published by the Free Software Foundation ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include "mt7601u.h" ++#include "trace.h" ++ ++enum mt76_txq_id { ++ MT_TXQ_VO = IEEE80211_AC_VO, ++ MT_TXQ_VI = IEEE80211_AC_VI, ++ MT_TXQ_BE = IEEE80211_AC_BE, ++ MT_TXQ_BK = IEEE80211_AC_BK, ++ MT_TXQ_PSD, ++ MT_TXQ_MCU, ++ __MT_TXQ_MAX ++}; ++ ++/* Hardware uses mirrored order of queues with Q0 having the highest priority */ ++static u8 q2hwq(u8 q) ++{ ++ return q ^ 0x3; ++} ++ ++/* Take mac80211 Q id from the skb and translate it to hardware Q id */ ++static u8 skb2q(struct sk_buff *skb) ++{ ++ int qid = skb_get_queue_mapping(skb); ++ ++ if (WARN_ON(qid >= MT_TXQ_PSD)) { ++ qid = MT_TXQ_BE; ++ skb_set_queue_mapping(skb, qid); ++ } ++ ++ return q2hwq(qid); ++} ++ ++/* Note: TX retry reporting is a bit broken. ++ * Retries are reported only once per AMPDU and often come a frame early ++ * i.e. they are reported in the last status preceding the AMPDU. Apart ++ * from the fact that it's hard to know the length of the AMPDU (which is ++ * required to know to how many consecutive frames retries should be ++ * applied), if status comes early on full FIFO it gets lost and retries ++ * of the whole AMPDU become invisible. ++ * As a work-around encode the desired rate in PKT_ID of TX descriptor ++ * and based on that guess the retries (every rate is tried once). ++ * Only downside here is that for MCS0 we have to rely solely on ++ * transmission failures as no retries can ever be reported. ++ * Not having to read EXT_FIFO has a nice effect of doubling the number ++ * of reports which can be fetched. ++ * Also the vendor driver never uses the EXT_FIFO register so it may be ++ * undertested. ++ */ ++static u8 mt7601u_tx_pktid_enc(struct mt7601u_dev *dev, u8 rate, bool is_probe) ++{ ++ u8 encoded = (rate + 1) + is_probe * 8; ++ ++ /* Because PKT_ID 0 disables status reporting only 15 values are ++ * available but 16 are needed (8 MCS * 2 for encoding is_probe) ++ * - we need to cram together two rates. MCS0 and MCS7 with is_probe ++ * share PKT_ID 9. ++ */ ++ if (is_probe && rate == 7) ++ return encoded - 7; ++ ++ return encoded; ++} ++ ++static void ++mt7601u_tx_pktid_dec(struct mt7601u_dev *dev, struct mt76_tx_status *stat) ++{ ++ u8 req_rate = stat->pktid; ++ u8 eff_rate = stat->rate & 0x7; ++ ++ req_rate -= 1; ++ ++ if (req_rate > 7) { ++ stat->is_probe = true; ++ req_rate -= 8; ++ ++ /* Decide between MCS0 and MCS7 which share pktid 9 */ ++ if (!req_rate && eff_rate) ++ req_rate = 7; ++ } ++ ++ stat->retry = req_rate - eff_rate; ++} ++ ++static void mt7601u_tx_skb_remove_dma_overhead(struct sk_buff *skb, ++ struct ieee80211_tx_info *info) ++{ ++ int pkt_len = (unsigned long)info->status.status_driver_data[0]; ++ ++ skb_pull(skb, sizeof(struct mt76_txwi) + 4); ++ if (ieee80211_get_hdrlen_from_skb(skb) % 4) ++ mt76_remove_hdr_pad(skb); ++ ++ skb_trim(skb, pkt_len); ++} ++ ++void mt7601u_tx_status(struct mt7601u_dev *dev, struct sk_buff *skb) ++{ ++ struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); ++ ++ mt7601u_tx_skb_remove_dma_overhead(skb, info); ++ ++ ieee80211_tx_info_clear_status(info); ++ info->status.rates[0].idx = -1; ++ info->flags |= IEEE80211_TX_STAT_ACK; ++ ++ spin_lock(&dev->mac_lock); ++ ieee80211_tx_status(dev->hw, skb); ++ spin_unlock(&dev->mac_lock); ++} ++ ++static int mt7601u_skb_rooms(struct mt7601u_dev *dev, struct sk_buff *skb) ++{ ++ int hdr_len = ieee80211_get_hdrlen_from_skb(skb); ++ u32 need_head; ++ ++ need_head = sizeof(struct mt76_txwi) + 4; ++ if (hdr_len % 4) ++ need_head += 2; ++ ++ return skb_cow(skb, need_head); ++} ++ ++static struct mt76_txwi * ++mt7601u_push_txwi(struct mt7601u_dev *dev, struct sk_buff *skb, ++ struct ieee80211_sta *sta, struct mt76_wcid *wcid, ++ int pkt_len) ++{ ++ struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); ++ struct ieee80211_tx_rate *rate = &info->control.rates[0]; ++ struct mt76_txwi *txwi; ++ unsigned long flags; ++ bool is_probe; ++ u32 pkt_id; ++ u16 rate_ctl; ++ u8 nss; ++ ++ txwi = (struct mt76_txwi *)skb_push(skb, sizeof(struct mt76_txwi)); ++ memset(txwi, 0, sizeof(*txwi)); ++ ++ if (!wcid->tx_rate_set) ++ ieee80211_get_tx_rates(info->control.vif, sta, skb, ++ info->control.rates, 1); ++ ++ spin_lock_irqsave(&dev->lock, flags); ++ if (rate->idx < 0 || !rate->count) ++ rate_ctl = wcid->tx_rate; ++ else ++ rate_ctl = mt76_mac_tx_rate_val(dev, rate, &nss); ++ spin_unlock_irqrestore(&dev->lock, flags); ++ txwi->rate_ctl = cpu_to_le16(rate_ctl); ++ ++ if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) ++ txwi->ack_ctl |= MT_TXWI_ACK_CTL_REQ; ++ if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) ++ txwi->ack_ctl |= MT_TXWI_ACK_CTL_NSEQ; ++ ++ if ((info->flags & IEEE80211_TX_CTL_AMPDU) && sta) { ++ u8 ba_size = IEEE80211_MIN_AMPDU_BUF; ++ ++ ba_size <<= sta->ht_cap.ampdu_factor; ++ ba_size = min_t(int, 63, ba_size); ++ if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ++ ba_size = 0; ++ txwi->ack_ctl |= MT76_SET(MT_TXWI_ACK_CTL_BA_WINDOW, ba_size); ++ ++ txwi->flags = cpu_to_le16(MT_TXWI_FLAGS_AMPDU | ++ MT76_SET(MT_TXWI_FLAGS_MPDU_DENSITY, ++ sta->ht_cap.ampdu_density)); ++ if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ++ txwi->flags = 0; ++ } ++ ++ txwi->wcid = wcid->idx; ++ ++ is_probe = !!(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE); ++ pkt_id = mt7601u_tx_pktid_enc(dev, rate_ctl & 0x7, is_probe); ++ pkt_len |= MT76_SET(MT_TXWI_LEN_PKTID, pkt_id); ++ txwi->len_ctl = cpu_to_le16(pkt_len); ++ ++ return txwi; ++} ++ ++void mt7601u_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control, ++ struct sk_buff *skb) ++{ ++ struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); ++ struct mt7601u_dev *dev = hw->priv; ++ struct ieee80211_vif *vif = info->control.vif; ++ struct ieee80211_sta *sta = control->sta; ++ struct mt76_sta *msta = NULL; ++ struct mt76_wcid *wcid = dev->mon_wcid; ++ struct mt76_txwi *txwi; ++ int pkt_len = skb->len; ++ int hw_q = skb2q(skb); ++ ++ BUILD_BUG_ON(ARRAY_SIZE(info->status.status_driver_data) < 1); ++ info->status.status_driver_data[0] = (void *)(unsigned long)pkt_len; ++ ++ if (mt7601u_skb_rooms(dev, skb) || mt76_insert_hdr_pad(skb)) { ++ ieee80211_free_txskb(dev->hw, skb); ++ return; ++ } ++ ++ if (sta) { ++ msta = (struct mt76_sta *) sta->drv_priv; ++ wcid = &msta->wcid; ++ } else if (vif) { ++ struct mt76_vif *mvif = (struct mt76_vif *)vif->drv_priv; ++ ++ wcid = &mvif->group_wcid; ++ } ++ ++ txwi = mt7601u_push_txwi(dev, skb, sta, wcid, pkt_len); ++ ++ if (mt7601u_dma_enqueue_tx(dev, skb, wcid, hw_q)) ++ return; ++ ++ trace_mt_tx(dev, skb, msta, txwi); ++} ++ ++void mt7601u_tx_stat(struct work_struct *work) ++{ ++ struct mt7601u_dev *dev = container_of(work, struct mt7601u_dev, ++ stat_work.work); ++ struct mt76_tx_status stat; ++ unsigned long flags; ++ int cleaned = 0; ++ ++ while (!test_bit(MT7601U_STATE_REMOVED, &dev->state)) { ++ stat = mt7601u_mac_fetch_tx_status(dev); ++ if (!stat.valid) ++ break; ++ ++ mt7601u_tx_pktid_dec(dev, &stat); ++ mt76_send_tx_status(dev, &stat); ++ ++ cleaned++; ++ } ++ trace_mt_tx_status_cleaned(dev, cleaned); ++ ++ spin_lock_irqsave(&dev->tx_lock, flags); ++ if (cleaned) ++ queue_delayed_work(dev->stat_wq, &dev->stat_work, ++ msecs_to_jiffies(10)); ++ else if (test_and_clear_bit(MT7601U_STATE_MORE_STATS, &dev->state)) ++ queue_delayed_work(dev->stat_wq, &dev->stat_work, ++ msecs_to_jiffies(20)); ++ else ++ clear_bit(MT7601U_STATE_READING_STATS, &dev->state); ++ spin_unlock_irqrestore(&dev->tx_lock, flags); ++} ++ ++int mt7601u_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif, ++ u16 queue, const struct ieee80211_tx_queue_params *params) ++{ ++ struct mt7601u_dev *dev = hw->priv; ++ u8 cw_min = 5, cw_max = 10, hw_q = q2hwq(queue); ++ u32 val; ++ ++ /* TODO: should we do funny things with the parameters? ++ * See what mt7601u_set_default_edca() used to do in init.c. ++ */ ++ ++ if (params->cw_min) ++ cw_min = fls(params->cw_min); ++ if (params->cw_max) ++ cw_max = fls(params->cw_max); ++ ++ WARN_ON(params->txop > 0xff); ++ WARN_ON(params->aifs > 0xf); ++ WARN_ON(cw_min > 0xf); ++ WARN_ON(cw_max > 0xf); ++ ++ val = MT76_SET(MT_EDCA_CFG_AIFSN, params->aifs) | ++ MT76_SET(MT_EDCA_CFG_CWMIN, cw_min) | ++ MT76_SET(MT_EDCA_CFG_CWMAX, cw_max); ++ /* TODO: based on user-controlled EnableTxBurst var vendor drv sets ++ * a really long txop on AC0 (see connect.c:2009) but only on ++ * connect? When not connected should be 0. ++ */ ++ if (!hw_q) ++ val |= 0x60; ++ else ++ val |= MT76_SET(MT_EDCA_CFG_TXOP, params->txop); ++ mt76_wr(dev, MT_EDCA_CFG_AC(hw_q), val); ++ ++ val = mt76_rr(dev, MT_WMM_TXOP(hw_q)); ++ val &= ~(MT_WMM_TXOP_MASK << MT_WMM_TXOP_SHIFT(hw_q)); ++ val |= params->txop << MT_WMM_TXOP_SHIFT(hw_q); ++ mt76_wr(dev, MT_WMM_TXOP(hw_q), val); ++ ++ val = mt76_rr(dev, MT_WMM_AIFSN); ++ val &= ~(MT_WMM_AIFSN_MASK << MT_WMM_AIFSN_SHIFT(hw_q)); ++ val |= params->aifs << MT_WMM_AIFSN_SHIFT(hw_q); ++ mt76_wr(dev, MT_WMM_AIFSN, val); ++ ++ val = mt76_rr(dev, MT_WMM_CWMIN); ++ val &= ~(MT_WMM_CWMIN_MASK << MT_WMM_CWMIN_SHIFT(hw_q)); ++ val |= cw_min << MT_WMM_CWMIN_SHIFT(hw_q); ++ mt76_wr(dev, MT_WMM_CWMIN, val); ++ ++ val = mt76_rr(dev, MT_WMM_CWMAX); ++ val &= ~(MT_WMM_CWMAX_MASK << MT_WMM_CWMAX_SHIFT(hw_q)); ++ val |= cw_max << MT_WMM_CWMAX_SHIFT(hw_q); ++ mt76_wr(dev, MT_WMM_CWMAX, val); ++ ++ return 0; ++} +diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/usb.c linux-rpi/drivers/net/wireless/mediatek/mt7601u/usb.c +--- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/usb.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/usb.c 2015-11-29 09:42:38.887167260 +0100 +@@ -0,0 +1,362 @@ ++/* ++ * Copyright (C) 2015 Jakub Kicinski ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 ++ * as published by the Free Software Foundation ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++ ++#include "mt7601u.h" ++#include "usb.h" ++#include "trace.h" ++ ++static struct usb_device_id mt7601u_device_table[] = { ++ { USB_DEVICE(0x0b05, 0x17d3) }, ++ { USB_DEVICE(0x0e8d, 0x760a) }, ++ { USB_DEVICE(0x0e8d, 0x760b) }, ++ { USB_DEVICE(0x13d3, 0x3431) }, ++ { USB_DEVICE(0x13d3, 0x3434) }, ++ { USB_DEVICE(0x148f, 0x7601) }, ++ { USB_DEVICE(0x148f, 0x760a) }, ++ { USB_DEVICE(0x148f, 0x760b) }, ++ { USB_DEVICE(0x148f, 0x760c) }, ++ { USB_DEVICE(0x148f, 0x760d) }, ++ { USB_DEVICE(0x2001, 0x3d04) }, ++ { USB_DEVICE(0x2717, 0x4106) }, ++ { USB_DEVICE(0x2955, 0x0001) }, ++ { USB_DEVICE(0x2955, 0x1001) }, ++ { USB_DEVICE(0x2a5f, 0x1000) }, ++ { USB_DEVICE(0x7392, 0x7710) }, ++ { 0, } ++}; ++ ++bool mt7601u_usb_alloc_buf(struct mt7601u_dev *dev, size_t len, ++ struct mt7601u_dma_buf *buf) ++{ ++ struct usb_device *usb_dev = mt7601u_to_usb_dev(dev); ++ ++ buf->len = len; ++ buf->urb = usb_alloc_urb(0, GFP_KERNEL); ++ buf->buf = usb_alloc_coherent(usb_dev, buf->len, GFP_KERNEL, &buf->dma); ++ ++ return !buf->urb || !buf->buf; ++} ++ ++void mt7601u_usb_free_buf(struct mt7601u_dev *dev, struct mt7601u_dma_buf *buf) ++{ ++ struct usb_device *usb_dev = mt7601u_to_usb_dev(dev); ++ ++ usb_free_coherent(usb_dev, buf->len, buf->buf, buf->dma); ++ usb_free_urb(buf->urb); ++} ++ ++int mt7601u_usb_submit_buf(struct mt7601u_dev *dev, int dir, int ep_idx, ++ struct mt7601u_dma_buf *buf, gfp_t gfp, ++ usb_complete_t complete_fn, void *context) ++{ ++ struct usb_device *usb_dev = mt7601u_to_usb_dev(dev); ++ unsigned pipe; ++ int ret; ++ ++ if (dir == USB_DIR_IN) ++ pipe = usb_rcvbulkpipe(usb_dev, dev->in_eps[ep_idx]); ++ else ++ pipe = usb_sndbulkpipe(usb_dev, dev->out_eps[ep_idx]); ++ ++ usb_fill_bulk_urb(buf->urb, usb_dev, pipe, buf->buf, buf->len, ++ complete_fn, context); ++ buf->urb->transfer_dma = buf->dma; ++ buf->urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; ++ ++ trace_mt_submit_urb(dev, buf->urb); ++ ret = usb_submit_urb(buf->urb, gfp); ++ if (ret) ++ dev_err(dev->dev, "Error: submit URB dir:%d ep:%d failed:%d\n", ++ dir, ep_idx, ret); ++ return ret; ++} ++ ++void mt7601u_complete_urb(struct urb *urb) ++{ ++ struct completion *cmpl = urb->context; ++ ++ complete(cmpl); ++} ++ ++int mt7601u_vendor_request(struct mt7601u_dev *dev, const u8 req, ++ const u8 direction, const u16 val, const u16 offset, ++ void *buf, const size_t buflen) ++{ ++ int i, ret; ++ struct usb_device *usb_dev = mt7601u_to_usb_dev(dev); ++ const u8 req_type = direction | USB_TYPE_VENDOR | USB_RECIP_DEVICE; ++ const unsigned int pipe = (direction == USB_DIR_IN) ? ++ usb_rcvctrlpipe(usb_dev, 0) : usb_sndctrlpipe(usb_dev, 0); ++ ++ for (i = 0; i < MT_VEND_REQ_MAX_RETRY; i++) { ++ ret = usb_control_msg(usb_dev, pipe, req, req_type, ++ val, offset, buf, buflen, ++ MT_VEND_REQ_TOUT_MS); ++ trace_mt_vend_req(dev, pipe, req, req_type, val, offset, ++ buf, buflen, ret); ++ ++ if (ret == -ENODEV) ++ set_bit(MT7601U_STATE_REMOVED, &dev->state); ++ if (ret >= 0 || ret == -ENODEV) ++ return ret; ++ ++ msleep(5); ++ } ++ ++ dev_err(dev->dev, "Vendor request req:%02x off:%04x failed:%d\n", ++ req, offset, ret); ++ ++ return ret; ++} ++ ++void mt7601u_vendor_reset(struct mt7601u_dev *dev) ++{ ++ mt7601u_vendor_request(dev, MT_VEND_DEV_MODE, USB_DIR_OUT, ++ MT_VEND_DEV_MODE_RESET, 0, NULL, 0); ++} ++ ++u32 mt7601u_rr(struct mt7601u_dev *dev, u32 offset) ++{ ++ int ret; ++ u32 val = ~0; ++ ++ WARN_ONCE(offset > USHRT_MAX, "read high off:%08x", offset); ++ ++ mutex_lock(&dev->vendor_req_mutex); ++ ++ ret = mt7601u_vendor_request(dev, MT_VEND_MULTI_READ, USB_DIR_IN, ++ 0, offset, dev->vend_buf, MT_VEND_BUF); ++ if (ret == MT_VEND_BUF) ++ val = get_unaligned_le32(dev->vend_buf); ++ else if (ret > 0) ++ dev_err(dev->dev, "Error: wrong size read:%d off:%08x\n", ++ ret, offset); ++ ++ mutex_unlock(&dev->vendor_req_mutex); ++ ++ trace_reg_read(dev, offset, val); ++ return val; ++} ++ ++int mt7601u_vendor_single_wr(struct mt7601u_dev *dev, const u8 req, ++ const u16 offset, const u32 val) ++{ ++ int ret; ++ ++ mutex_lock(&dev->vendor_req_mutex); ++ ++ ret = mt7601u_vendor_request(dev, req, USB_DIR_OUT, ++ val & 0xffff, offset, NULL, 0); ++ if (!ret) ++ ret = mt7601u_vendor_request(dev, req, USB_DIR_OUT, ++ val >> 16, offset + 2, NULL, 0); ++ ++ mutex_unlock(&dev->vendor_req_mutex); ++ ++ return ret; ++} ++ ++void mt7601u_wr(struct mt7601u_dev *dev, u32 offset, u32 val) ++{ ++ WARN_ONCE(offset > USHRT_MAX, "write high off:%08x", offset); ++ ++ mt7601u_vendor_single_wr(dev, MT_VEND_WRITE, offset, val); ++ trace_reg_write(dev, offset, val); ++} ++ ++u32 mt7601u_rmw(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val) ++{ ++ val |= mt7601u_rr(dev, offset) & ~mask; ++ mt7601u_wr(dev, offset, val); ++ return val; ++} ++ ++u32 mt7601u_rmc(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val) ++{ ++ u32 reg = mt7601u_rr(dev, offset); ++ ++ val |= reg & ~mask; ++ if (reg != val) ++ mt7601u_wr(dev, offset, val); ++ return val; ++} ++ ++void mt7601u_wr_copy(struct mt7601u_dev *dev, u32 offset, ++ const void *data, int len) ++{ ++ WARN_ONCE(offset & 3, "unaligned write copy off:%08x", offset); ++ WARN_ONCE(len & 3, "short write copy off:%08x", offset); ++ ++ mt7601u_burst_write_regs(dev, offset, data, len / 4); ++} ++ ++void mt7601u_addr_wr(struct mt7601u_dev *dev, const u32 offset, const u8 *addr) ++{ ++ mt7601u_wr(dev, offset, get_unaligned_le32(addr)); ++ mt7601u_wr(dev, offset + 4, addr[4] | addr[5] << 8); ++} ++ ++static int mt7601u_assign_pipes(struct usb_interface *usb_intf, ++ struct mt7601u_dev *dev) ++{ ++ struct usb_endpoint_descriptor *ep_desc; ++ struct usb_host_interface *intf_desc = usb_intf->cur_altsetting; ++ unsigned i, ep_i = 0, ep_o = 0; ++ ++ BUILD_BUG_ON(sizeof(dev->in_eps) < __MT_EP_IN_MAX); ++ BUILD_BUG_ON(sizeof(dev->out_eps) < __MT_EP_OUT_MAX); ++ ++ for (i = 0; i < intf_desc->desc.bNumEndpoints; i++) { ++ ep_desc = &intf_desc->endpoint[i].desc; ++ ++ if (usb_endpoint_is_bulk_in(ep_desc) && ++ ep_i++ < __MT_EP_IN_MAX) { ++ dev->in_eps[ep_i - 1] = usb_endpoint_num(ep_desc); ++ dev->in_max_packet = usb_endpoint_maxp(ep_desc); ++ /* Note: this is ignored by usb sub-system but vendor ++ * code does it. We can drop this at some point. ++ */ ++ dev->in_eps[ep_i - 1] |= USB_DIR_IN; ++ } else if (usb_endpoint_is_bulk_out(ep_desc) && ++ ep_o++ < __MT_EP_OUT_MAX) { ++ dev->out_eps[ep_o - 1] = usb_endpoint_num(ep_desc); ++ dev->out_max_packet = usb_endpoint_maxp(ep_desc); ++ } ++ } ++ ++ if (ep_i != __MT_EP_IN_MAX || ep_o != __MT_EP_OUT_MAX) { ++ dev_err(dev->dev, "Error: wrong pipe number in:%d out:%d\n", ++ ep_i, ep_o); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int mt7601u_probe(struct usb_interface *usb_intf, ++ const struct usb_device_id *id) ++{ ++ struct usb_device *usb_dev = interface_to_usbdev(usb_intf); ++ struct mt7601u_dev *dev; ++ u32 asic_rev, mac_rev; ++ int ret; ++ ++ dev = mt7601u_alloc_device(&usb_intf->dev); ++ if (!dev) ++ return -ENOMEM; ++ ++ usb_dev = usb_get_dev(usb_dev); ++ usb_reset_device(usb_dev); ++ ++ usb_set_intfdata(usb_intf, dev); ++ ++ dev->vend_buf = devm_kmalloc(dev->dev, MT_VEND_BUF, GFP_KERNEL); ++ if (!dev->vend_buf) { ++ ret = -ENOMEM; ++ goto err; ++ } ++ ++ ret = mt7601u_assign_pipes(usb_intf, dev); ++ if (ret) ++ goto err; ++ ret = mt7601u_wait_asic_ready(dev); ++ if (ret) ++ goto err; ++ ++ asic_rev = mt7601u_rr(dev, MT_ASIC_VERSION); ++ mac_rev = mt7601u_rr(dev, MT_MAC_CSR0); ++ dev_info(dev->dev, "ASIC revision: %08x MAC revision: %08x\n", ++ asic_rev, mac_rev); ++ ++ /* Note: vendor driver skips this check for MT7601U */ ++ if (!(mt7601u_rr(dev, MT_EFUSE_CTRL) & MT_EFUSE_CTRL_SEL)) ++ dev_warn(dev->dev, "Warning: eFUSE not present\n"); ++ ++ ret = mt7601u_init_hardware(dev); ++ if (ret) ++ goto err; ++ ret = mt7601u_register_device(dev); ++ if (ret) ++ goto err_hw; ++ ++ set_bit(MT7601U_STATE_INITIALIZED, &dev->state); ++ ++ return 0; ++err_hw: ++ mt7601u_cleanup(dev); ++err: ++ usb_set_intfdata(usb_intf, NULL); ++ usb_put_dev(interface_to_usbdev(usb_intf)); ++ ++ destroy_workqueue(dev->stat_wq); ++ ieee80211_free_hw(dev->hw); ++ return ret; ++} ++ ++static void mt7601u_disconnect(struct usb_interface *usb_intf) ++{ ++ struct mt7601u_dev *dev = usb_get_intfdata(usb_intf); ++ ++ ieee80211_unregister_hw(dev->hw); ++ mt7601u_cleanup(dev); ++ ++ usb_set_intfdata(usb_intf, NULL); ++ usb_put_dev(interface_to_usbdev(usb_intf)); ++ ++ destroy_workqueue(dev->stat_wq); ++ ieee80211_free_hw(dev->hw); ++} ++ ++static int mt7601u_suspend(struct usb_interface *usb_intf, pm_message_t state) ++{ ++ struct mt7601u_dev *dev = usb_get_intfdata(usb_intf); ++ ++ mt7601u_cleanup(dev); ++ ++ return 0; ++} ++ ++static int mt7601u_resume(struct usb_interface *usb_intf) ++{ ++ struct mt7601u_dev *dev = usb_get_intfdata(usb_intf); ++ int ret; ++ ++ ret = mt7601u_init_hardware(dev); ++ if (ret) ++ return ret; ++ ++ set_bit(MT7601U_STATE_INITIALIZED, &dev->state); ++ ++ return 0; ++} ++ ++MODULE_DEVICE_TABLE(usb, mt7601u_device_table); ++MODULE_FIRMWARE(MT7601U_FIRMWARE); ++MODULE_LICENSE("GPL"); ++ ++static struct usb_driver mt7601u_driver = { ++ .name = KBUILD_MODNAME, ++ .id_table = mt7601u_device_table, ++ .probe = mt7601u_probe, ++ .disconnect = mt7601u_disconnect, ++ .suspend = mt7601u_suspend, ++ .resume = mt7601u_resume, ++ .reset_resume = mt7601u_resume, ++ .soft_unbind = 1, ++ .disable_hub_initiated_lpm = 1, ++}; ++module_usb_driver(mt7601u_driver); +diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/usb.h linux-rpi/drivers/net/wireless/mediatek/mt7601u/usb.h +--- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/usb.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/usb.h 2015-11-29 09:42:38.887167260 +0100 +@@ -0,0 +1,79 @@ ++/* ++ * Copyright (C) 2015 Jakub Kicinski ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 ++ * as published by the Free Software Foundation ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef __MT7601U_USB_H ++#define __MT7601U_USB_H ++ ++#include "mt7601u.h" ++ ++#define MT7601U_FIRMWARE "mt7601u.bin" ++ ++#define MT_VEND_REQ_MAX_RETRY 10 ++#define MT_VEND_REQ_TOUT_MS 300 ++ ++#define MT_VEND_DEV_MODE_RESET 1 ++ ++#define MT_VEND_BUF sizeof(__le32) ++ ++enum mt_vendor_req { ++ MT_VEND_DEV_MODE = 1, ++ MT_VEND_WRITE = 2, ++ MT_VEND_MULTI_READ = 7, ++ MT_VEND_WRITE_FCE = 0x42, ++}; ++ ++enum mt_usb_ep_in { ++ MT_EP_IN_PKT_RX, ++ MT_EP_IN_CMD_RESP, ++ __MT_EP_IN_MAX, ++}; ++ ++enum mt_usb_ep_out { ++ MT_EP_OUT_INBAND_CMD, ++ MT_EP_OUT_AC_BK, ++ MT_EP_OUT_AC_BE, ++ MT_EP_OUT_AC_VI, ++ MT_EP_OUT_AC_VO, ++ MT_EP_OUT_HCCA, ++ __MT_EP_OUT_MAX, ++}; ++ ++static inline struct usb_device *mt7601u_to_usb_dev(struct mt7601u_dev *mt7601u) ++{ ++ return interface_to_usbdev(to_usb_interface(mt7601u->dev)); ++} ++ ++static inline bool mt7601u_urb_has_error(struct urb *urb) ++{ ++ return urb->status && ++ urb->status != -ENOENT && ++ urb->status != -ECONNRESET && ++ urb->status != -ESHUTDOWN; ++} ++ ++bool mt7601u_usb_alloc_buf(struct mt7601u_dev *dev, size_t len, ++ struct mt7601u_dma_buf *buf); ++void mt7601u_usb_free_buf(struct mt7601u_dev *dev, struct mt7601u_dma_buf *buf); ++int mt7601u_usb_submit_buf(struct mt7601u_dev *dev, int dir, int ep_idx, ++ struct mt7601u_dma_buf *buf, gfp_t gfp, ++ usb_complete_t complete_fn, void *context); ++void mt7601u_complete_urb(struct urb *urb); ++ ++int mt7601u_vendor_request(struct mt7601u_dev *dev, const u8 req, ++ const u8 direction, const u16 val, const u16 offset, ++ void *buf, const size_t buflen); ++void mt7601u_vendor_reset(struct mt7601u_dev *dev); ++int mt7601u_vendor_single_wr(struct mt7601u_dev *dev, const u8 req, ++ const u16 offset, const u32 val); ++ ++#endif +diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/util.c linux-rpi/drivers/net/wireless/mediatek/mt7601u/util.c +--- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/util.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/util.c 2015-11-29 09:42:38.887167260 +0100 +@@ -0,0 +1,42 @@ ++/* ++ * Copyright (C) 2014 Felix Fietkau ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 ++ * as published by the Free Software Foundation ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include "mt7601u.h" ++ ++void mt76_remove_hdr_pad(struct sk_buff *skb) ++{ ++ int len = ieee80211_get_hdrlen_from_skb(skb); ++ ++ memmove(skb->data + 2, skb->data, len); ++ skb_pull(skb, 2); ++} ++ ++int mt76_insert_hdr_pad(struct sk_buff *skb) ++{ ++ int len = ieee80211_get_hdrlen_from_skb(skb); ++ int ret; ++ ++ if (len % 4 == 0) ++ return 0; ++ ++ ret = skb_cow(skb, 2); ++ if (ret) ++ return ret; ++ ++ skb_push(skb, 2); ++ memmove(skb->data, skb->data + 2, len); ++ ++ skb->data[len] = 0; ++ skb->data[len + 1] = 0; ++ return 0; ++} +diff -Nur linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/util.h linux-rpi/drivers/net/wireless/mediatek/mt7601u/util.h +--- linux-4.1.13.orig/drivers/net/wireless/mediatek/mt7601u/util.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/net/wireless/mediatek/mt7601u/util.h 2015-11-29 09:42:38.887167260 +0100 +@@ -0,0 +1,77 @@ ++/* ++ * Copyright (C) 2014 Felix Fietkau ++ * Copyright (C) 2004 - 2009 Ivo van Doorn ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 ++ * as published by the Free Software Foundation ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef __MT76_UTIL_H ++#define __MT76_UTIL_H ++ ++/* ++ * Power of two check, this will check ++ * if the mask that has been given contains and contiguous set of bits. ++ * Note that we cannot use the is_power_of_2() function since this ++ * check must be done at compile-time. ++ */ ++#define is_power_of_two(x) ( !((x) & ((x)-1)) ) ++#define low_bit_mask(x) ( ((x)-1) & ~(x) ) ++#define is_valid_mask(x) is_power_of_two(1LU + (x) + low_bit_mask(x)) ++ ++/* ++ * Macros to find first set bit in a variable. ++ * These macros behave the same as the __ffs() functions but ++ * the most important difference that this is done during ++ * compile-time rather then run-time. ++ */ ++#define compile_ffs2(__x) \ ++ __builtin_choose_expr(((__x) & 0x1), 0, 1) ++ ++#define compile_ffs4(__x) \ ++ __builtin_choose_expr(((__x) & 0x3), \ ++ (compile_ffs2((__x))), \ ++ (compile_ffs2((__x) >> 2) + 2)) ++ ++#define compile_ffs8(__x) \ ++ __builtin_choose_expr(((__x) & 0xf), \ ++ (compile_ffs4((__x))), \ ++ (compile_ffs4((__x) >> 4) + 4)) ++ ++#define compile_ffs16(__x) \ ++ __builtin_choose_expr(((__x) & 0xff), \ ++ (compile_ffs8((__x))), \ ++ (compile_ffs8((__x) >> 8) + 8)) ++ ++#define compile_ffs32(__x) \ ++ __builtin_choose_expr(((__x) & 0xffff), \ ++ (compile_ffs16((__x))), \ ++ (compile_ffs16((__x) >> 16) + 16)) ++ ++/* ++ * This macro will check the requirements for the FIELD{8,16,32} macros ++ * The mask should be a constant non-zero contiguous set of bits which ++ * does not exceed the given typelimit. ++ */ ++#define FIELD_CHECK(__mask) \ ++ BUILD_BUG_ON(!(__mask) || !is_valid_mask(__mask)) ++ ++#define MT76_SET(_mask, _val) \ ++ ({ \ ++ FIELD_CHECK(_mask); \ ++ (((u32) (_val)) << compile_ffs32(_mask)) & _mask; \ ++ }) ++ ++#define MT76_GET(_mask, _val) \ ++ ({ \ ++ FIELD_CHECK(_mask); \ ++ (u32) (((_val) & _mask) >> compile_ffs32(_mask)); \ ++ }) ++ ++#endif +diff -Nur linux-4.1.13.orig/drivers/of/fdt.c linux-rpi/drivers/of/fdt.c +--- linux-4.1.13.orig/drivers/of/fdt.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/of/fdt.c 2015-11-29 09:42:39.031157693 +0100 +@@ -933,19 +933,38 @@ + + /* Retrieve command line */ + p = of_get_flat_dt_prop(node, "bootargs", &l); +- if (p != NULL && l > 0) +- strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE)); + + /* + * CONFIG_CMDLINE is meant to be a default in case nothing else + * managed to set the command line, unless CONFIG_CMDLINE_FORCE + * is set in which case we override whatever was found earlier. ++ * ++ * However, it can be useful to be able to treat the default as ++ * a starting point to be extended using CONFIG_CMDLINE_EXTEND. + */ ++ ((char *)data)[0] = '\0'; ++ + #ifdef CONFIG_CMDLINE +-#ifndef CONFIG_CMDLINE_FORCE +- if (!((char *)data)[0]) ++ strlcpy(data, CONFIG_CMDLINE, COMMAND_LINE_SIZE); ++ ++ if (p != NULL && l > 0) { ++#if defined(CONFIG_CMDLINE_EXTEND) ++ int len = strlen(data); ++ if (len > 0) { ++ strlcat(data, " ", COMMAND_LINE_SIZE); ++ len++; ++ } ++ strlcpy((char *)data + len, p, min((int)l, COMMAND_LINE_SIZE - len)); ++#elif defined(CONFIG_CMDLINE_FORCE) ++ pr_warning("Ignoring bootargs property (using the default kernel command line)\n"); ++#else ++ /* Neither extend nor force - just override */ ++ strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE)); + #endif +- strlcpy(data, CONFIG_CMDLINE, COMMAND_LINE_SIZE); ++ } ++#else /* CONFIG_CMDLINE */ ++ if (p != NULL && l > 0) { ++ strlcpy(data, p, min((int)l, COMMAND_LINE_SIZE)); + #endif /* CONFIG_CMDLINE */ + + pr_debug("Command line is: %s\n", (char*)data); +diff -Nur linux-4.1.13.orig/drivers/pinctrl/bcm/pinctrl-bcm2835.c linux-rpi/drivers/pinctrl/bcm/pinctrl-bcm2835.c +--- linux-4.1.13.orig/drivers/pinctrl/bcm/pinctrl-bcm2835.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/pinctrl/bcm/pinctrl-bcm2835.c 2015-11-29 09:42:39.071155035 +0100 +@@ -47,6 +47,7 @@ + #define MODULE_NAME "pinctrl-bcm2835" + #define BCM2835_NUM_GPIOS 54 + #define BCM2835_NUM_BANKS 2 ++#define BCM2835_NUM_IRQS 3 + + #define BCM2835_PIN_BITMAP_SZ \ + DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8) +@@ -88,13 +89,13 @@ + + struct bcm2835_gpio_irqdata { + struct bcm2835_pinctrl *pc; +- int bank; ++ int irqgroup; + }; + + struct bcm2835_pinctrl { + struct device *dev; + void __iomem *base; +- int irq[BCM2835_NUM_BANKS]; ++ int irq[BCM2835_NUM_IRQS]; + + /* note: locking assumes each bank will have its own unsigned long */ + unsigned long enabled_irq_map[BCM2835_NUM_BANKS]; +@@ -105,7 +106,7 @@ + struct gpio_chip gpio_chip; + struct pinctrl_gpio_range gpio_range; + +- struct bcm2835_gpio_irqdata irq_data[BCM2835_NUM_BANKS]; ++ struct bcm2835_gpio_irqdata irq_data[BCM2835_NUM_IRQS]; + spinlock_t irq_lock[BCM2835_NUM_BANKS]; + }; + +@@ -355,7 +356,14 @@ + static int bcm2835_gpio_direction_output(struct gpio_chip *chip, + unsigned offset, int value) + { +- return pinctrl_gpio_direction_output(chip->base + offset); ++ struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev); ++ int ret; ++ ++ ret = pinctrl_gpio_direction_output(chip->base + offset); ++ if (ret >= 0) ++ bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset); ++ ++ return ret; + } + + static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value) +@@ -382,22 +390,21 @@ + .get = bcm2835_gpio_get, + .set = bcm2835_gpio_set, + .to_irq = bcm2835_gpio_to_irq, +- .base = -1, ++ .base = 0, + .ngpio = BCM2835_NUM_GPIOS, + .can_sleep = false, + }; + +-static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id) ++static int bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc, ++ unsigned int bank, u32 mask) + { +- struct bcm2835_gpio_irqdata *irqdata = dev_id; +- struct bcm2835_pinctrl *pc = irqdata->pc; +- int bank = irqdata->bank; + unsigned long events; + unsigned offset; + unsigned gpio; + unsigned int type; + + events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4); ++ events &= mask; + events &= pc->enabled_irq_map[bank]; + for_each_set_bit(offset, &events, 32) { + gpio = (32 * bank) + offset; +@@ -405,7 +412,30 @@ + + generic_handle_irq(irq_linear_revmap(pc->irq_domain, gpio)); + } +- return events ? IRQ_HANDLED : IRQ_NONE; ++ ++ return (events != 0); ++} ++ ++static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id) ++{ ++ struct bcm2835_gpio_irqdata *irqdata = dev_id; ++ struct bcm2835_pinctrl *pc = irqdata->pc; ++ int handled = 0; ++ ++ switch (irqdata->irqgroup) { ++ case 0: /* IRQ0 covers GPIOs 0-27 */ ++ handled = bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff); ++ break; ++ case 1: /* IRQ1 covers GPIOs 28-45 */ ++ handled = bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000) | ++ bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff); ++ break; ++ case 2: /* IRQ2 covers GPIOs 46-53 */ ++ handled = bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000); ++ break; ++ } ++ ++ return handled ? IRQ_HANDLED : IRQ_NONE; + } + + static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc, +@@ -473,6 +503,8 @@ + + spin_lock_irqsave(&pc->irq_lock[bank], flags); + bcm2835_gpio_irq_config(pc, gpio, false); ++ /* Clear events that were latched prior to clearing event sources */ ++ bcm2835_gpio_set_bit(pc, GPEDS0, gpio); + clear_bit(offset, &pc->enabled_irq_map[bank]); + spin_unlock_irqrestore(&pc->irq_lock[bank], flags); + } +@@ -993,8 +1025,6 @@ + for (i = 0; i < BCM2835_NUM_BANKS; i++) { + unsigned long events; + unsigned offset; +- int len; +- char *name; + + /* clear event detection flags */ + bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0); +@@ -1009,10 +1039,17 @@ + for_each_set_bit(offset, &events, 32) + bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset)); + ++ spin_lock_init(&pc->irq_lock[i]); ++ } ++ ++ for (i = 0; i < BCM2835_NUM_IRQS; i++) { ++ int len; ++ char *name; + pc->irq[i] = irq_of_parse_and_map(np, i); ++ if (pc->irq[i] == 0) ++ break; + pc->irq_data[i].pc = pc; +- pc->irq_data[i].bank = i; +- spin_lock_init(&pc->irq_lock[i]); ++ pc->irq_data[i].irqgroup = i; + + len = strlen(dev_name(pc->dev)) + 16; + name = devm_kzalloc(pc->dev, len, GFP_KERNEL); +@@ -1070,6 +1107,7 @@ + .remove = bcm2835_pinctrl_remove, + .driver = { + .name = MODULE_NAME, ++ .owner = THIS_MODULE, + .of_match_table = bcm2835_pinctrl_match, + }, + }; +diff -Nur linux-4.1.13.orig/drivers/pinctrl/Makefile linux-rpi/drivers/pinctrl/Makefile +--- linux-4.1.13.orig/drivers/pinctrl/Makefile 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/pinctrl/Makefile 2015-11-29 09:42:39.071155035 +0100 +@@ -38,6 +38,7 @@ + obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o + obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o + ++obj-$(CONFIG_ARCH_BCM2708)$(CONFIG_ARCH_BCM2709) += bcm/ + obj-$(CONFIG_ARCH_BCM) += bcm/ + obj-$(CONFIG_ARCH_BERLIN) += berlin/ + obj-y += freescale/ +diff -Nur linux-4.1.13.orig/drivers/power/reset/gpio-poweroff.c linux-rpi/drivers/power/reset/gpio-poweroff.c +--- linux-4.1.13.orig/drivers/power/reset/gpio-poweroff.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/power/reset/gpio-poweroff.c 2015-11-29 09:42:39.131151049 +0100 +@@ -48,9 +48,11 @@ + static int gpio_poweroff_probe(struct platform_device *pdev) + { + bool input = false; ++ bool force = false; + + /* If a pm_power_off function has already been added, leave it alone */ +- if (pm_power_off != NULL) { ++ force = of_property_read_bool(pdev->dev.of_node, "force"); ++ if (!force && (pm_power_off != NULL)) { + dev_err(&pdev->dev, + "%s: pm_power_off function already registered", + __func__); +diff -Nur linux-4.1.13.orig/drivers/pwm/Kconfig linux-rpi/drivers/pwm/Kconfig +--- linux-4.1.13.orig/drivers/pwm/Kconfig 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/pwm/Kconfig 2015-11-29 09:42:39.139150517 +0100 +@@ -85,7 +85,7 @@ + + config PWM_BCM2835 + tristate "BCM2835 PWM support" +- depends on ARCH_BCM2835 ++ depends on ARCH_BCM2835 || ARCH_BCM2708 || ARCH_BCM2709 + help + PWM framework driver for BCM2835 controller (Raspberry Pi) + +diff -Nur linux-4.1.13.orig/drivers/rtc/rtc-ds1307.c linux-rpi/drivers/rtc/rtc-ds1307.c +--- linux-4.1.13.orig/drivers/rtc/rtc-ds1307.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/rtc/rtc-ds1307.c 2015-11-29 09:42:39.163148923 +0100 +@@ -1242,6 +1242,14 @@ + return 0; + } + ++#ifdef CONFIG_OF ++static const struct of_device_id ds1307_of_match[] = { ++ { .compatible = "maxim,ds1307" }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, ds1307_of_match); ++#endif ++ + static struct i2c_driver ds1307_driver = { + .driver = { + .name = "rtc-ds1307", +diff -Nur linux-4.1.13.orig/drivers/spi/Kconfig linux-rpi/drivers/spi/Kconfig +--- linux-4.1.13.orig/drivers/spi/Kconfig 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/spi/Kconfig 2015-11-29 09:42:39.435130851 +0100 +@@ -77,7 +77,7 @@ + + config SPI_BCM2835 + tristate "BCM2835 SPI controller" +- depends on ARCH_BCM2835 || COMPILE_TEST ++ depends on ARCH_BCM2835 || ARCH_BCM2708 || ARCH_BCM2709 || COMPILE_TEST + depends on GPIOLIB + help + This selects a driver for the Broadcom BCM2835 SPI master. +@@ -87,6 +87,14 @@ + is for the regular SPI controller. Slave mode operation is not also + not supported. + ++config SPI_BCM2708 ++ tristate "BCM2708 SPI controller driver (SPI0)" ++ depends on MACH_BCM2708 || MACH_BCM2709 ++ help ++ This selects a driver for the Broadcom BCM2708 SPI master (SPI0). This ++ driver is not compatible with the "Universal SPI Master" or the SPI slave ++ device. ++ + config SPI_BFIN5XX + tristate "SPI controller driver for ADI Blackfin5xx" + depends on BLACKFIN && !BF60x +diff -Nur linux-4.1.13.orig/drivers/spi/Makefile linux-rpi/drivers/spi/Makefile +--- linux-4.1.13.orig/drivers/spi/Makefile 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/spi/Makefile 2015-11-29 09:42:39.435130851 +0100 +@@ -20,6 +20,7 @@ + obj-$(CONFIG_SPI_BCM63XX_HSSPI) += spi-bcm63xx-hsspi.o + obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o + obj-$(CONFIG_SPI_ADI_V3) += spi-adi-v3.o ++obj-$(CONFIG_SPI_BCM2708) += spi-bcm2708.o + obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o + obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o + obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o +diff -Nur linux-4.1.13.orig/drivers/spi/spi-bcm2708.c linux-rpi/drivers/spi/spi-bcm2708.c +--- linux-4.1.13.orig/drivers/spi/spi-bcm2708.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/spi/spi-bcm2708.c 2015-11-29 09:42:39.435130851 +0100 +@@ -0,0 +1,628 @@ ++/* ++ * Driver for Broadcom BCM2708 SPI Controllers ++ * ++ * Copyright (C) 2012 Chris Boot ++ * ++ * This driver is inspired by: ++ * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos ++ * spi-atmel.c, Copyright (C) 2006 Atmel Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* SPI register offsets */ ++#define SPI_CS 0x00 ++#define SPI_FIFO 0x04 ++#define SPI_CLK 0x08 ++#define SPI_DLEN 0x0c ++#define SPI_LTOH 0x10 ++#define SPI_DC 0x14 ++ ++/* Bitfields in CS */ ++#define SPI_CS_LEN_LONG 0x02000000 ++#define SPI_CS_DMA_LEN 0x01000000 ++#define SPI_CS_CSPOL2 0x00800000 ++#define SPI_CS_CSPOL1 0x00400000 ++#define SPI_CS_CSPOL0 0x00200000 ++#define SPI_CS_RXF 0x00100000 ++#define SPI_CS_RXR 0x00080000 ++#define SPI_CS_TXD 0x00040000 ++#define SPI_CS_RXD 0x00020000 ++#define SPI_CS_DONE 0x00010000 ++#define SPI_CS_LEN 0x00002000 ++#define SPI_CS_REN 0x00001000 ++#define SPI_CS_ADCS 0x00000800 ++#define SPI_CS_INTR 0x00000400 ++#define SPI_CS_INTD 0x00000200 ++#define SPI_CS_DMAEN 0x00000100 ++#define SPI_CS_TA 0x00000080 ++#define SPI_CS_CSPOL 0x00000040 ++#define SPI_CS_CLEAR_RX 0x00000020 ++#define SPI_CS_CLEAR_TX 0x00000010 ++#define SPI_CS_CPOL 0x00000008 ++#define SPI_CS_CPHA 0x00000004 ++#define SPI_CS_CS_10 0x00000002 ++#define SPI_CS_CS_01 0x00000001 ++ ++#define SPI_TIMEOUT_MS 1000 ++ ++#define DRV_NAME "bcm2708_spi" ++ ++struct bcm2708_spi { ++ spinlock_t lock; ++ void __iomem *base; ++ int irq; ++ struct clk *clk; ++ bool stopping; ++ ++ struct list_head queue; ++ struct workqueue_struct *workq; ++ struct work_struct work; ++ struct completion done; ++ ++ const u8 *tx_buf; ++ u8 *rx_buf; ++ int len; ++}; ++ ++struct bcm2708_spi_state { ++ u32 cs; ++ u16 cdiv; ++}; ++ ++/* ++ * This function sets the ALT mode on the SPI pins so that we can use them with ++ * the SPI hardware. ++ * ++ * FIXME: This is a hack. Use pinmux / pinctrl. ++ */ ++static void bcm2708_init_pinmode(void) ++{ ++#define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3)) ++#define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3)) ++ ++ int pin; ++ u32 *gpio = ioremap(GPIO_BASE, SZ_16K); ++ ++ /* SPI is on GPIO 7..11 */ ++ for (pin = 7; pin <= 11; pin++) { ++ INP_GPIO(pin); /* set mode to GPIO input first */ ++ SET_GPIO_ALT(pin, 0); /* set mode to ALT 0 */ ++ } ++ ++ iounmap(gpio); ++ ++#undef INP_GPIO ++#undef SET_GPIO_ALT ++} ++ ++static inline u32 bcm2708_rd(struct bcm2708_spi *bs, unsigned reg) ++{ ++ return readl(bs->base + reg); ++} ++ ++static inline void bcm2708_wr(struct bcm2708_spi *bs, unsigned reg, u32 val) ++{ ++ writel(val, bs->base + reg); ++} ++ ++static inline void bcm2708_rd_fifo(struct bcm2708_spi *bs, int len) ++{ ++ u8 byte; ++ ++ while (len--) { ++ byte = bcm2708_rd(bs, SPI_FIFO); ++ if (bs->rx_buf) ++ *bs->rx_buf++ = byte; ++ } ++} ++ ++static inline void bcm2708_wr_fifo(struct bcm2708_spi *bs, int len) ++{ ++ u8 byte; ++ u16 val; ++ ++ if (len > bs->len) ++ len = bs->len; ++ ++ if (unlikely(bcm2708_rd(bs, SPI_CS) & SPI_CS_LEN)) { ++ /* LoSSI mode */ ++ if (unlikely(len % 2)) { ++ printk(KERN_ERR"bcm2708_wr_fifo: length must be even, skipping.\n"); ++ bs->len = 0; ++ return; ++ } ++ while (len) { ++ if (bs->tx_buf) { ++ val = *(const u16 *)bs->tx_buf; ++ bs->tx_buf += 2; ++ } else ++ val = 0; ++ bcm2708_wr(bs, SPI_FIFO, val); ++ bs->len -= 2; ++ len -= 2; ++ } ++ return; ++ } ++ ++ while (len--) { ++ byte = bs->tx_buf ? *bs->tx_buf++ : 0; ++ bcm2708_wr(bs, SPI_FIFO, byte); ++ bs->len--; ++ } ++} ++ ++static irqreturn_t bcm2708_spi_interrupt(int irq, void *dev_id) ++{ ++ struct spi_master *master = dev_id; ++ struct bcm2708_spi *bs = spi_master_get_devdata(master); ++ u32 cs; ++ ++ spin_lock(&bs->lock); ++ ++ cs = bcm2708_rd(bs, SPI_CS); ++ ++ if (cs & SPI_CS_DONE) { ++ if (bs->len) { /* first interrupt in a transfer */ ++ /* fill the TX fifo with up to 16 bytes */ ++ bcm2708_wr_fifo(bs, 16); ++ } else { /* transfer complete */ ++ /* disable interrupts */ ++ cs &= ~(SPI_CS_INTR | SPI_CS_INTD); ++ bcm2708_wr(bs, SPI_CS, cs); ++ ++ /* drain RX FIFO */ ++ while (cs & SPI_CS_RXD) { ++ bcm2708_rd_fifo(bs, 1); ++ cs = bcm2708_rd(bs, SPI_CS); ++ } ++ ++ /* wake up our bh */ ++ complete(&bs->done); ++ } ++ } else if (cs & SPI_CS_RXR) { ++ /* read 12 bytes of data */ ++ bcm2708_rd_fifo(bs, 12); ++ ++ /* write up to 12 bytes */ ++ bcm2708_wr_fifo(bs, 12); ++ } ++ ++ spin_unlock(&bs->lock); ++ ++ return IRQ_HANDLED; ++} ++ ++static int bcm2708_setup_state(struct spi_master *master, ++ struct device *dev, struct bcm2708_spi_state *state, ++ u32 hz, u8 csel, u8 mode, u8 bpw) ++{ ++ struct bcm2708_spi *bs = spi_master_get_devdata(master); ++ int cdiv; ++ unsigned long bus_hz; ++ u32 cs = 0; ++ ++ bus_hz = clk_get_rate(bs->clk); ++ ++ if (hz >= bus_hz) { ++ cdiv = 2; /* bus_hz / 2 is as fast as we can go */ ++ } else if (hz) { ++ cdiv = DIV_ROUND_UP(bus_hz, hz); ++ ++ /* CDIV must be a power of 2, so round up */ ++ cdiv = roundup_pow_of_two(cdiv); ++ ++ if (cdiv > 65536) { ++ dev_dbg(dev, ++ "setup: %d Hz too slow, cdiv %u; min %ld Hz\n", ++ hz, cdiv, bus_hz / 65536); ++ return -EINVAL; ++ } else if (cdiv == 65536) { ++ cdiv = 0; ++ } else if (cdiv == 1) { ++ cdiv = 2; /* 1 gets rounded down to 0; == 65536 */ ++ } ++ } else { ++ cdiv = 0; ++ } ++ ++ switch (bpw) { ++ case 8: ++ break; ++ case 9: ++ /* Reading in LoSSI mode is a special case. See 'BCM2835 ARM Peripherals' datasheet */ ++ cs |= SPI_CS_LEN; ++ break; ++ default: ++ dev_dbg(dev, "setup: invalid bits_per_word %u (must be 8 or 9)\n", ++ bpw); ++ return -EINVAL; ++ } ++ ++ if (mode & SPI_CPOL) ++ cs |= SPI_CS_CPOL; ++ if (mode & SPI_CPHA) ++ cs |= SPI_CS_CPHA; ++ ++ if (!(mode & SPI_NO_CS)) { ++ if (mode & SPI_CS_HIGH) { ++ cs |= SPI_CS_CSPOL; ++ cs |= SPI_CS_CSPOL0 << csel; ++ } ++ ++ cs |= csel; ++ } else { ++ cs |= SPI_CS_CS_10 | SPI_CS_CS_01; ++ } ++ ++ if (state) { ++ state->cs = cs; ++ state->cdiv = cdiv; ++ dev_dbg(dev, "setup: want %d Hz; " ++ "bus_hz=%lu / cdiv=%u == %lu Hz; " ++ "mode %u: cs 0x%08X\n", ++ hz, bus_hz, cdiv, bus_hz/cdiv, mode, cs); ++ } ++ ++ return 0; ++} ++ ++static int bcm2708_process_transfer(struct bcm2708_spi *bs, ++ struct spi_message *msg, struct spi_transfer *xfer) ++{ ++ struct spi_device *spi = msg->spi; ++ struct bcm2708_spi_state state, *stp; ++ int ret; ++ u32 cs; ++ ++ if (bs->stopping) ++ return -ESHUTDOWN; ++ ++ if (xfer->bits_per_word || xfer->speed_hz) { ++ ret = bcm2708_setup_state(spi->master, &spi->dev, &state, ++ xfer->speed_hz ? xfer->speed_hz : spi->max_speed_hz, ++ spi->chip_select, spi->mode, ++ xfer->bits_per_word ? xfer->bits_per_word : ++ spi->bits_per_word); ++ if (ret) ++ return ret; ++ ++ stp = &state; ++ } else { ++ stp = spi->controller_state; ++ } ++ ++ reinit_completion(&bs->done); ++ bs->tx_buf = xfer->tx_buf; ++ bs->rx_buf = xfer->rx_buf; ++ bs->len = xfer->len; ++ ++ cs = stp->cs | SPI_CS_INTR | SPI_CS_INTD | SPI_CS_TA; ++ ++ bcm2708_wr(bs, SPI_CLK, stp->cdiv); ++ bcm2708_wr(bs, SPI_CS, cs); ++ ++ ret = wait_for_completion_timeout(&bs->done, ++ msecs_to_jiffies(SPI_TIMEOUT_MS)); ++ if (ret == 0) { ++ dev_err(&spi->dev, "transfer timed out\n"); ++ return -ETIMEDOUT; ++ } ++ ++ if (xfer->delay_usecs) ++ udelay(xfer->delay_usecs); ++ ++ if (list_is_last(&xfer->transfer_list, &msg->transfers) || ++ xfer->cs_change) { ++ /* clear TA and interrupt flags */ ++ bcm2708_wr(bs, SPI_CS, stp->cs); ++ } ++ ++ msg->actual_length += (xfer->len - bs->len); ++ ++ return 0; ++} ++ ++static void bcm2708_work(struct work_struct *work) ++{ ++ struct bcm2708_spi *bs = container_of(work, struct bcm2708_spi, work); ++ unsigned long flags; ++ struct spi_message *msg; ++ struct spi_transfer *xfer; ++ int status = 0; ++ ++ spin_lock_irqsave(&bs->lock, flags); ++ while (!list_empty(&bs->queue)) { ++ msg = list_first_entry(&bs->queue, struct spi_message, queue); ++ list_del_init(&msg->queue); ++ spin_unlock_irqrestore(&bs->lock, flags); ++ ++ list_for_each_entry(xfer, &msg->transfers, transfer_list) { ++ status = bcm2708_process_transfer(bs, msg, xfer); ++ if (status) ++ break; ++ } ++ ++ msg->status = status; ++ msg->complete(msg->context); ++ ++ spin_lock_irqsave(&bs->lock, flags); ++ } ++ spin_unlock_irqrestore(&bs->lock, flags); ++} ++ ++static int bcm2708_spi_setup(struct spi_device *spi) ++{ ++ struct bcm2708_spi *bs = spi_master_get_devdata(spi->master); ++ struct bcm2708_spi_state *state; ++ int ret; ++ ++ if (bs->stopping) ++ return -ESHUTDOWN; ++ ++ state = spi->controller_state; ++ if (!state) { ++ state = kzalloc(sizeof(*state), GFP_KERNEL); ++ if (!state) ++ return -ENOMEM; ++ ++ spi->controller_state = state; ++ } ++ ++ ret = bcm2708_setup_state(spi->master, &spi->dev, state, ++ spi->max_speed_hz, spi->chip_select, spi->mode, ++ spi->bits_per_word); ++ if (ret < 0) { ++ kfree(state); ++ spi->controller_state = NULL; ++ return ret; ++ } ++ ++ dev_dbg(&spi->dev, ++ "setup: cd %d: %d Hz, bpw %u, mode 0x%x -> CS=%08x CDIV=%04x\n", ++ spi->chip_select, spi->max_speed_hz, spi->bits_per_word, ++ spi->mode, state->cs, state->cdiv); ++ ++ return 0; ++} ++ ++static int bcm2708_spi_transfer(struct spi_device *spi, struct spi_message *msg) ++{ ++ struct bcm2708_spi *bs = spi_master_get_devdata(spi->master); ++ struct spi_transfer *xfer; ++ int ret; ++ unsigned long flags; ++ ++ if (unlikely(list_empty(&msg->transfers))) ++ return -EINVAL; ++ ++ if (bs->stopping) ++ return -ESHUTDOWN; ++ ++ list_for_each_entry(xfer, &msg->transfers, transfer_list) { ++ if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) { ++ dev_dbg(&spi->dev, "missing rx or tx buf\n"); ++ return -EINVAL; ++ } ++ ++ if (!xfer->bits_per_word || xfer->speed_hz) ++ continue; ++ ++ ret = bcm2708_setup_state(spi->master, &spi->dev, NULL, ++ xfer->speed_hz ? xfer->speed_hz : spi->max_speed_hz, ++ spi->chip_select, spi->mode, ++ xfer->bits_per_word ? xfer->bits_per_word : ++ spi->bits_per_word); ++ if (ret) ++ return ret; ++ } ++ ++ msg->status = -EINPROGRESS; ++ msg->actual_length = 0; ++ ++ spin_lock_irqsave(&bs->lock, flags); ++ list_add_tail(&msg->queue, &bs->queue); ++ queue_work(bs->workq, &bs->work); ++ spin_unlock_irqrestore(&bs->lock, flags); ++ ++ return 0; ++} ++ ++static void bcm2708_spi_cleanup(struct spi_device *spi) ++{ ++ if (spi->controller_state) { ++ kfree(spi->controller_state); ++ spi->controller_state = NULL; ++ } ++} ++ ++static int bcm2708_spi_probe(struct platform_device *pdev) ++{ ++ struct resource *regs; ++ int irq, err = -ENOMEM; ++ struct clk *clk; ++ struct spi_master *master; ++ struct bcm2708_spi *bs; ++ ++ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!regs) { ++ dev_err(&pdev->dev, "could not get IO memory\n"); ++ return -ENXIO; ++ } ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) { ++ dev_err(&pdev->dev, "could not get IRQ\n"); ++ return irq; ++ } ++ ++ clk = clk_get(&pdev->dev, NULL); ++ if (IS_ERR(clk)) { ++ dev_err(&pdev->dev, "could not find clk: %ld\n", PTR_ERR(clk)); ++ return PTR_ERR(clk); ++ } ++ ++ if (!pdev->dev.of_node) ++ bcm2708_init_pinmode(); ++ ++ master = spi_alloc_master(&pdev->dev, sizeof(*bs)); ++ if (!master) { ++ dev_err(&pdev->dev, "spi_alloc_master() failed\n"); ++ goto out_clk_put; ++ } ++ ++ /* the spi->mode bits understood by this driver: */ ++ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS; ++ ++ master->bus_num = pdev->id; ++ master->num_chipselect = 3; ++ master->setup = bcm2708_spi_setup; ++ master->transfer = bcm2708_spi_transfer; ++ master->cleanup = bcm2708_spi_cleanup; ++ master->dev.of_node = pdev->dev.of_node; ++ platform_set_drvdata(pdev, master); ++ ++ bs = spi_master_get_devdata(master); ++ ++ spin_lock_init(&bs->lock); ++ INIT_LIST_HEAD(&bs->queue); ++ init_completion(&bs->done); ++ INIT_WORK(&bs->work, bcm2708_work); ++ ++ bs->base = ioremap(regs->start, resource_size(regs)); ++ if (!bs->base) { ++ dev_err(&pdev->dev, "could not remap memory\n"); ++ goto out_master_put; ++ } ++ ++ bs->workq = create_singlethread_workqueue(dev_name(&pdev->dev)); ++ if (!bs->workq) { ++ dev_err(&pdev->dev, "could not create workqueue\n"); ++ goto out_iounmap; ++ } ++ ++ bs->irq = irq; ++ bs->clk = clk; ++ bs->stopping = false; ++ ++ err = request_irq(irq, bcm2708_spi_interrupt, 0, dev_name(&pdev->dev), ++ master); ++ if (err) { ++ dev_err(&pdev->dev, "could not request IRQ: %d\n", err); ++ goto out_workqueue; ++ } ++ ++ /* initialise the hardware */ ++ clk_prepare_enable(clk); ++ bcm2708_wr(bs, SPI_CS, SPI_CS_REN | SPI_CS_CLEAR_RX | SPI_CS_CLEAR_TX); ++ ++ err = spi_register_master(master); ++ if (err) { ++ dev_err(&pdev->dev, "could not register SPI master: %d\n", err); ++ goto out_free_irq; ++ } ++ ++ dev_info(&pdev->dev, "SPI Controller at 0x%08lx (irq %d)\n", ++ (unsigned long)regs->start, irq); ++ ++ return 0; ++ ++out_free_irq: ++ free_irq(bs->irq, master); ++ clk_disable_unprepare(bs->clk); ++out_workqueue: ++ destroy_workqueue(bs->workq); ++out_iounmap: ++ iounmap(bs->base); ++out_master_put: ++ spi_master_put(master); ++out_clk_put: ++ clk_put(clk); ++ return err; ++} ++ ++static int bcm2708_spi_remove(struct platform_device *pdev) ++{ ++ struct spi_master *master = platform_get_drvdata(pdev); ++ struct bcm2708_spi *bs = spi_master_get_devdata(master); ++ ++ /* reset the hardware and block queue progress */ ++ spin_lock_irq(&bs->lock); ++ bs->stopping = true; ++ bcm2708_wr(bs, SPI_CS, SPI_CS_CLEAR_RX | SPI_CS_CLEAR_TX); ++ spin_unlock_irq(&bs->lock); ++ ++ flush_work(&bs->work); ++ ++ clk_disable_unprepare(bs->clk); ++ clk_put(bs->clk); ++ free_irq(bs->irq, master); ++ iounmap(bs->base); ++ ++ spi_unregister_master(master); ++ ++ return 0; ++} ++ ++static const struct of_device_id bcm2708_spi_match[] = { ++ { .compatible = "brcm,bcm2708-spi", }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, bcm2708_spi_match); ++ ++static struct platform_driver bcm2708_spi_driver = { ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = bcm2708_spi_match, ++ }, ++ .probe = bcm2708_spi_probe, ++ .remove = bcm2708_spi_remove, ++}; ++ ++ ++static int __init bcm2708_spi_init(void) ++{ ++ return platform_driver_probe(&bcm2708_spi_driver, bcm2708_spi_probe); ++} ++module_init(bcm2708_spi_init); ++ ++static void __exit bcm2708_spi_exit(void) ++{ ++ platform_driver_unregister(&bcm2708_spi_driver); ++} ++module_exit(bcm2708_spi_exit); ++ ++ ++//module_platform_driver(bcm2708_spi_driver); ++ ++MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2708"); ++MODULE_AUTHOR("Chris Boot "); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:" DRV_NAME); +diff -Nur linux-4.1.13.orig/drivers/spi/spi-bcm2835.c linux-rpi/drivers/spi/spi-bcm2835.c +--- linux-4.1.13.orig/drivers/spi/spi-bcm2835.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/spi/spi-bcm2835.c 2015-11-29 09:42:39.435130851 +0100 +@@ -20,18 +20,22 @@ + * GNU General Public License for more details. + */ + ++#include + #include + #include + #include ++#include ++#include + #include + #include + #include + #include + #include + #include +-#include +-#include ++#include + #include ++#include ++#include + #include + + /* SPI register offsets */ +@@ -69,7 +73,8 @@ + #define BCM2835_SPI_CS_CS_01 0x00000001 + + #define BCM2835_SPI_POLLING_LIMIT_US 30 +-#define BCM2835_SPI_TIMEOUT_MS 30000 ++#define BCM2835_SPI_POLLING_JIFFIES 2 ++#define BCM2835_SPI_DMA_MIN_LENGTH 96 + #define BCM2835_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \ + | SPI_NO_CS | SPI_3WIRE) + +@@ -83,6 +88,7 @@ + u8 *rx_buf; + int tx_len; + int rx_len; ++ bool dma_pending; + }; + + static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg) +@@ -128,12 +134,15 @@ + /* Disable SPI interrupts and transfer */ + cs &= ~(BCM2835_SPI_CS_INTR | + BCM2835_SPI_CS_INTD | ++ BCM2835_SPI_CS_DMAEN | + BCM2835_SPI_CS_TA); + /* and reset RX/TX FIFOS */ + cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX; + + /* and reset the SPI_HW */ + bcm2835_wr(bs, BCM2835_SPI_CS, cs); ++ /* as well as DLEN */ ++ bcm2835_wr(bs, BCM2835_SPI_DLEN, 0); + } + + static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id) +@@ -157,42 +166,6 @@ + return IRQ_HANDLED; + } + +-static int bcm2835_spi_transfer_one_poll(struct spi_master *master, +- struct spi_device *spi, +- struct spi_transfer *tfr, +- u32 cs, +- unsigned long xfer_time_us) +-{ +- struct bcm2835_spi *bs = spi_master_get_devdata(master); +- /* set timeout to 1 second of maximum polling */ +- unsigned long timeout = jiffies + HZ; +- +- /* enable HW block without interrupts */ +- bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA); +- +- /* loop until finished the transfer */ +- while (bs->rx_len) { +- /* read from fifo as much as possible */ +- bcm2835_rd_fifo(bs); +- /* fill in tx fifo as much as possible */ +- bcm2835_wr_fifo(bs); +- /* if we still expect some data after the read, +- * check for a possible timeout +- */ +- if (bs->rx_len && time_after(jiffies, timeout)) { +- /* Transfer complete - reset SPI HW */ +- bcm2835_spi_reset_hw(master); +- /* and return timeout */ +- return -ETIMEDOUT; +- } +- } +- +- /* Transfer complete - reset SPI HW */ +- bcm2835_spi_reset_hw(master); +- /* and return without waiting for completion */ +- return 0; +-} +- + static int bcm2835_spi_transfer_one_irq(struct spi_master *master, + struct spi_device *spi, + struct spi_transfer *tfr, +@@ -229,13 +202,337 @@ + return 1; + } + ++/* ++ * DMA support ++ * ++ * this implementation has currently a few issues in so far as it does ++ * not work arrount limitations of the HW. ++ * ++ * the main one being that DMA transfers are limited to 16 bit ++ * (so 0 to 65535 bytes) by the SPI HW due to BCM2835_SPI_DLEN ++ * ++ * also we currently assume that the scatter-gather fragments are ++ * all multiple of 4 (except the last) - otherwise we would need ++ * to reset the FIFO before subsequent transfers... ++ * this also means that tx/rx transfers sg's need to be of equal size! ++ * ++ * there may be a few more border-cases we may need to address as well ++ * but unfortunately this would mean splitting up the scatter-gather ++ * list making it slightly unpractical... ++ */ ++static void bcm2835_spi_dma_done(void *data) ++{ ++ struct spi_master *master = data; ++ struct bcm2835_spi *bs = spi_master_get_devdata(master); ++ ++ /* reset fifo and HW */ ++ bcm2835_spi_reset_hw(master); ++ ++ /* and terminate tx-dma as we do not have an irq for it ++ * because when the rx dma will terminate and this callback ++ * is called the tx-dma must have finished - can't get to this ++ * situation otherwise... ++ */ ++ dmaengine_terminate_all(master->dma_tx); ++ ++ /* mark as no longer pending */ ++ bs->dma_pending = 0; ++ ++ /* and mark as completed */; ++ complete(&master->xfer_completion); ++} ++ ++static int bcm2835_spi_prepare_sg(struct spi_master *master, ++ struct spi_transfer *tfr, ++ bool is_tx) ++{ ++ struct dma_chan *chan; ++ struct scatterlist *sgl; ++ unsigned int nents; ++ enum dma_transfer_direction dir; ++ unsigned long flags; ++ ++ struct dma_async_tx_descriptor *desc; ++ dma_cookie_t cookie; ++ ++ if (is_tx) { ++ dir = DMA_MEM_TO_DEV; ++ chan = master->dma_tx; ++ nents = tfr->tx_sg.nents; ++ sgl = tfr->tx_sg.sgl; ++ flags = 0 /* no tx interrupt */; ++ ++ } else { ++ dir = DMA_DEV_TO_MEM; ++ chan = master->dma_rx; ++ nents = tfr->rx_sg.nents; ++ sgl = tfr->rx_sg.sgl; ++ flags = DMA_PREP_INTERRUPT; ++ } ++ /* prepare the channel */ ++ desc = dmaengine_prep_slave_sg(chan, sgl, nents, dir, flags); ++ if (!desc) ++ return -EINVAL; ++ ++ /* set callback for rx */ ++ if (!is_tx) { ++ desc->callback = bcm2835_spi_dma_done; ++ desc->callback_param = master; ++ } ++ ++ /* submit it to DMA-engine */ ++ cookie = dmaengine_submit(desc); ++ ++ return dma_submit_error(cookie); ++} ++ ++static inline int bcm2835_check_sg_length(struct sg_table *sgt) ++{ ++ int i; ++ struct scatterlist *sgl; ++ ++ /* check that the sg entries are word-sized (except for last) */ ++ for_each_sg(sgt->sgl, sgl, (int)sgt->nents - 1, i) { ++ if (sg_dma_len(sgl) % 4) ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++static int bcm2835_spi_transfer_one_dma(struct spi_master *master, ++ struct spi_device *spi, ++ struct spi_transfer *tfr, ++ u32 cs) ++{ ++ struct bcm2835_spi *bs = spi_master_get_devdata(master); ++ int ret; ++ ++ /* check that the scatter gather segments are all a multiple of 4 */ ++ if (bcm2835_check_sg_length(&tfr->tx_sg) || ++ bcm2835_check_sg_length(&tfr->rx_sg)) { ++ dev_warn_once(&spi->dev, ++ "scatter gather segment length is not a multiple of 4 - falling back to interrupt mode\n"); ++ return bcm2835_spi_transfer_one_irq(master, spi, tfr, cs); ++ } ++ ++ /* setup tx-DMA */ ++ ret = bcm2835_spi_prepare_sg(master, tfr, true); ++ if (ret) ++ return ret; ++ ++ /* start TX early */ ++ dma_async_issue_pending(master->dma_tx); ++ ++ /* mark as dma pending */ ++ bs->dma_pending = 1; ++ ++ /* set the DMA length */ ++ bcm2835_wr(bs, BCM2835_SPI_DLEN, tfr->len); ++ ++ /* start the HW */ ++ bcm2835_wr(bs, BCM2835_SPI_CS, ++ cs | BCM2835_SPI_CS_TA | BCM2835_SPI_CS_DMAEN); ++ ++ /* setup rx-DMA late - to run transfers while ++ * mapping of the rx buffers still takes place ++ * this saves 10us or more. ++ */ ++ ret = bcm2835_spi_prepare_sg(master, tfr, false); ++ if (ret) { ++ /* need to reset on errors */ ++ dmaengine_terminate_all(master->dma_tx); ++ bcm2835_spi_reset_hw(master); ++ return ret; ++ } ++ ++ /* start rx dma late */ ++ dma_async_issue_pending(master->dma_rx); ++ ++ /* wait for wakeup in framework */ ++ return 1; ++} ++ ++static bool bcm2835_spi_can_dma(struct spi_master *master, ++ struct spi_device *spi, ++ struct spi_transfer *tfr) ++{ ++ /* only run for gpio_cs */ ++ if (!gpio_is_valid(spi->cs_gpio)) ++ return false; ++ ++ /* we start DMA efforts only on bigger transfers */ ++ if (tfr->len < BCM2835_SPI_DMA_MIN_LENGTH) ++ return false; ++ ++ /* BCM2835_SPI_DLEN has defined a max transfer size as ++ * 16 bit, so max is 65535 ++ * we can revisit this by using an alternative transfer ++ * method - ideally this would get done without any more ++ * interaction... ++ */ ++ if (tfr->len > 65535) { ++ dev_warn_once(&spi->dev, ++ "transfer size of %d too big for dma-transfer\n", ++ tfr->len); ++ return false; ++ } ++ ++ /* if we run rx/tx_buf with word aligned addresses then we are OK */ ++ if ((((size_t)tfr->rx_buf & 3) == 0) && ++ (((size_t)tfr->tx_buf & 3) == 0)) ++ return true; ++ ++ /* otherwise we only allow transfers within the same page ++ * to avoid wasting time on dma_mapping when it is not practical ++ */ ++ if (((size_t)tfr->tx_buf & (PAGE_SIZE - 1)) + tfr->len > PAGE_SIZE) { ++ dev_warn_once(&spi->dev, ++ "Unaligned spi tx-transfer bridging page\n"); ++ return false; ++ } ++ if (((size_t)tfr->rx_buf & (PAGE_SIZE - 1)) + tfr->len > PAGE_SIZE) { ++ dev_warn_once(&spi->dev, ++ "Unaligned spi rx-transfer bridging page\n"); ++ return false; ++ } ++ ++ /* return OK */ ++ return true; ++} ++ ++static void bcm2835_dma_release(struct spi_master *master) ++{ ++ if (master->dma_tx) { ++ dmaengine_terminate_all(master->dma_tx); ++ dma_release_channel(master->dma_tx); ++ master->dma_tx = NULL; ++ } ++ if (master->dma_rx) { ++ dmaengine_terminate_all(master->dma_rx); ++ dma_release_channel(master->dma_rx); ++ master->dma_rx = NULL; ++ } ++} ++ ++static void bcm2835_dma_init(struct spi_master *master, struct device *dev) ++{ ++ struct dma_slave_config slave_config; ++ const __be32 *addr; ++ dma_addr_t dma_reg_base; ++ int ret; ++ ++ /* base address in dma-space */ ++ addr = of_get_address(master->dev.of_node, 0, NULL, NULL); ++ if (!addr) { ++ dev_err(dev, "could not get DMA-register address - not using dma mode\n"); ++ goto err; ++ } ++ dma_reg_base = be32_to_cpup(addr); ++ ++ /* get tx/rx dma */ ++ master->dma_tx = dma_request_slave_channel(dev, "tx"); ++ if (!master->dma_tx) { ++ dev_err(dev, "no tx-dma configuration found - not using dma mode\n"); ++ goto err; ++ } ++ master->dma_rx = dma_request_slave_channel(dev, "rx"); ++ if (!master->dma_rx) { ++ dev_err(dev, "no rx-dma configuration found - not using dma mode\n"); ++ goto err_release; ++ } ++ ++ /* configure DMAs */ ++ slave_config.direction = DMA_MEM_TO_DEV; ++ slave_config.dst_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO); ++ slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ ++ ret = dmaengine_slave_config(master->dma_tx, &slave_config); ++ if (ret) ++ goto err_config; ++ ++ slave_config.direction = DMA_DEV_TO_MEM; ++ slave_config.src_addr = (u32)(dma_reg_base + BCM2835_SPI_FIFO); ++ slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ ++ ret = dmaengine_slave_config(master->dma_rx, &slave_config); ++ if (ret) ++ goto err_config; ++ ++ /* all went well, so set can_dma */ ++ master->can_dma = bcm2835_spi_can_dma; ++ master->max_dma_len = 65535; /* limitation by BCM2835_SPI_DLEN */ ++ /* need to do TX AND RX DMA, so we need dummy buffers */ ++ master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX; ++ ++ return; ++ ++err_config: ++ dev_err(dev, "issue configuring dma: %d - not using DMA mode\n", ++ ret); ++err_release: ++ bcm2835_dma_release(master); ++err: ++ return; ++} ++ ++static int bcm2835_spi_transfer_one_poll(struct spi_master *master, ++ struct spi_device *spi, ++ struct spi_transfer *tfr, ++ u32 cs, ++ unsigned long long xfer_time_us) ++{ ++ struct bcm2835_spi *bs = spi_master_get_devdata(master); ++ unsigned long timeout; ++ ++ /* enable HW block without interrupts */ ++ bcm2835_wr(bs, BCM2835_SPI_CS, cs | BCM2835_SPI_CS_TA); ++ ++ /* fill in the fifo before timeout calculations ++ * if we are interrupted here, then the data is ++ * getting transferred by the HW while we are interrupted ++ */ ++ bcm2835_wr_fifo(bs); ++ ++ /* set the timeout */ ++ timeout = jiffies + BCM2835_SPI_POLLING_JIFFIES; ++ ++ /* loop until finished the transfer */ ++ while (bs->rx_len) { ++ /* fill in tx fifo with remaining data */ ++ bcm2835_wr_fifo(bs); ++ ++ /* read from fifo as much as possible */ ++ bcm2835_rd_fifo(bs); ++ ++ /* if there is still data pending to read ++ * then check the timeout ++ */ ++ if (bs->rx_len && time_after(jiffies, timeout)) { ++ dev_dbg_ratelimited(&spi->dev, ++ "timeout period reached: jiffies: %lu remaining tx/rx: %d/%d - falling back to interrupt mode\n", ++ jiffies - timeout, ++ bs->tx_len, bs->rx_len); ++ /* fall back to interrupt mode */ ++ return bcm2835_spi_transfer_one_irq(master, spi, ++ tfr, cs); ++ } ++ } ++ ++ /* Transfer complete - reset SPI HW */ ++ bcm2835_spi_reset_hw(master); ++ /* and return without waiting for completion */ ++ return 0; ++} ++ + static int bcm2835_spi_transfer_one(struct spi_master *master, + struct spi_device *spi, + struct spi_transfer *tfr) + { + struct bcm2835_spi *bs = spi_master_get_devdata(master); + unsigned long spi_hz, clk_hz, cdiv; +- unsigned long spi_used_hz, xfer_time_us; ++ unsigned long spi_used_hz; ++ unsigned long long xfer_time_us; + u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS); + + /* set clock */ +@@ -277,15 +574,21 @@ + bs->rx_len = tfr->len; + + /* calculate the estimated time in us the transfer runs */ +- xfer_time_us = tfr->len ++ xfer_time_us = (unsigned long long)tfr->len + * 9 /* clocks/byte - SPI-HW waits 1 clock after each byte */ +- * 1000000 / spi_used_hz; ++ * 1000000; ++ do_div(xfer_time_us, spi_used_hz); + + /* for short requests run polling*/ + if (xfer_time_us <= BCM2835_SPI_POLLING_LIMIT_US) + return bcm2835_spi_transfer_one_poll(master, spi, tfr, + cs, xfer_time_us); + ++ /* run in dma mode if conditions are right */ ++ if (master->can_dma && bcm2835_spi_can_dma(master, spi, tfr)) ++ return bcm2835_spi_transfer_one_dma(master, spi, tfr, cs); ++ ++ /* run in interrupt-mode */ + return bcm2835_spi_transfer_one_irq(master, spi, tfr, cs); + } + +@@ -311,6 +614,15 @@ + static void bcm2835_spi_handle_err(struct spi_master *master, + struct spi_message *msg) + { ++ struct bcm2835_spi *bs = spi_master_get_devdata(master); ++ ++ /* if an error occurred and we have an active dma, then terminate */ ++ if (bs->dma_pending) { ++ dmaengine_terminate_all(master->dma_tx); ++ dmaengine_terminate_all(master->dma_rx); ++ bs->dma_pending = 0; ++ } ++ /* and reset */ + bcm2835_spi_reset_hw(master); + } + +@@ -376,6 +688,8 @@ + { + int err; + struct gpio_chip *chip; ++ struct device_node *pins; ++ u32 pingroup_index; + /* + * sanity checking the native-chipselects + */ +@@ -392,15 +706,42 @@ + "setup: only two native chip-selects are supported\n"); + return -EINVAL; + } +- /* now translate native cs to GPIO */ + +- /* get the gpio chip for the base */ +- chip = gpiochip_find("pinctrl-bcm2835", chip_match_name); +- if (!chip) +- return 0; ++ /* now translate native cs to GPIO */ ++ /* first look for chip select pins in the devices pin groups */ ++ for (pingroup_index = 0; ++ (pins = of_parse_phandle(spi->master->dev.of_node, ++ "pinctrl-0", ++ pingroup_index)) != 0; ++ pingroup_index++) { ++ u32 pin; ++ u32 pin_index; ++ for (pin_index = 0; ++ of_property_read_u32_index(pins, ++ "brcm,pins", ++ pin_index, ++ &pin) == 0; ++ pin_index++) { ++ if (((spi->chip_select == 0) && ++ ((pin == 8) || (pin == 36) || (pin == 46))) || ++ ((spi->chip_select == 1) && ++ ((pin == 7) || (pin == 35)))) { ++ spi->cs_gpio = pin; ++ break; ++ } ++ } ++ of_node_put(pins); ++ } ++ /* if that fails, assume GPIOs 7-11 are used */ ++ if (!gpio_is_valid(spi->cs_gpio) ) { ++ /* get the gpio chip for the base */ ++ chip = gpiochip_find("pinctrl-bcm2835", chip_match_name); ++ if (!chip) ++ return 0; + +- /* and calculate the real CS */ +- spi->cs_gpio = chip->base + 8 - spi->chip_select; ++ /* and calculate the real CS */ ++ spi->cs_gpio = chip->base + 8 - spi->chip_select; ++ } + + /* and set up the "mode" and level */ + dev_info(&spi->dev, "setting up native-CS%i as GPIO %i\n", +@@ -481,6 +822,8 @@ + goto out_clk_disable; + } + ++ bcm2835_dma_init(master, &pdev->dev); ++ + /* initialise the hardware with the default polarities */ + bcm2835_wr(bs, BCM2835_SPI_CS, + BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX); +@@ -511,6 +854,8 @@ + + clk_disable_unprepare(bs->clk); + ++ bcm2835_dma_release(master); ++ + return 0; + } + +diff -Nur linux-4.1.13.orig/drivers/spi/spidev.c linux-rpi/drivers/spi/spidev.c +--- linux-4.1.13.orig/drivers/spi/spidev.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/spi/spidev.c 2015-11-29 09:42:39.447130054 +0100 +@@ -707,6 +707,7 @@ + #ifdef CONFIG_OF + static const struct of_device_id spidev_dt_ids[] = { + { .compatible = "rohm,dh2228fv" }, ++ { .compatible = "spidev" }, + {}, + }; + MODULE_DEVICE_TABLE(of, spidev_dt_ids); +diff -Nur linux-4.1.13.orig/drivers/staging/fbtft/fbtft-core.c linux-rpi/drivers/staging/fbtft/fbtft-core.c +--- linux-4.1.13.orig/drivers/staging/fbtft/fbtft-core.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/staging/fbtft/fbtft-core.c 2015-11-29 09:42:39.491127130 +0100 +@@ -1074,6 +1074,11 @@ + p = of_prop_next_u32(prop, NULL, &val); + if (!p) + return -EINVAL; ++ ++ par->fbtftops.reset(par); ++ if (par->gpio.cs != -1) ++ gpio_set_value(par->gpio.cs, 0); /* Activate chip */ ++ + while (p) { + if (val & FBTFT_OF_INIT_CMD) { + val &= 0xFFFF; +diff -Nur linux-4.1.13.orig/drivers/staging/media/lirc/Kconfig linux-rpi/drivers/staging/media/lirc/Kconfig +--- linux-4.1.13.orig/drivers/staging/media/lirc/Kconfig 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/staging/media/lirc/Kconfig 2015-11-29 09:42:39.643117031 +0100 +@@ -32,6 +32,12 @@ + help + Driver for Homebrew Parallel Port Receivers + ++config LIRC_RPI ++ tristate "Homebrew GPIO Port Receiver/Transmitter for the RaspberryPi" ++ depends on LIRC ++ help ++ Driver for Homebrew GPIO Port Receiver/Transmitter for the RaspberryPi ++ + config LIRC_SASEM + tristate "Sasem USB IR Remote" + depends on LIRC && USB +diff -Nur linux-4.1.13.orig/drivers/staging/media/lirc/lirc_rpi.c linux-rpi/drivers/staging/media/lirc/lirc_rpi.c +--- linux-4.1.13.orig/drivers/staging/media/lirc/lirc_rpi.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/staging/media/lirc/lirc_rpi.c 2015-11-29 09:42:39.643117031 +0100 +@@ -0,0 +1,765 @@ ++/* ++ * lirc_rpi.c ++ * ++ * lirc_rpi - Device driver that records pulse- and pause-lengths ++ * (space-lengths) (just like the lirc_serial driver does) ++ * between GPIO interrupt events on the Raspberry Pi. ++ * Lots of code has been taken from the lirc_serial module, ++ * so I would like say thanks to the authors. ++ * ++ * Copyright (C) 2012 Aron Robert Szabo , ++ * Michael Bishop ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define LIRC_DRIVER_NAME "lirc_rpi" ++#define RBUF_LEN 256 ++#define LIRC_TRANSMITTER_LATENCY 50 ++ ++#ifndef MAX_UDELAY_MS ++#define MAX_UDELAY_US 5000 ++#else ++#define MAX_UDELAY_US (MAX_UDELAY_MS*1000) ++#endif ++ ++#define dprintk(fmt, args...) \ ++ do { \ ++ if (debug) \ ++ printk(KERN_DEBUG LIRC_DRIVER_NAME ": " \ ++ fmt, ## args); \ ++ } while (0) ++ ++/* module parameters */ ++ ++/* set the default GPIO input pin */ ++static int gpio_in_pin = 18; ++/* set the default pull behaviour for input pin */ ++static int gpio_in_pull = BCM2708_PULL_DOWN; ++/* set the default GPIO output pin */ ++static int gpio_out_pin = 17; ++/* enable debugging messages */ ++static bool debug; ++/* -1 = auto, 0 = active high, 1 = active low */ ++static int sense = -1; ++/* use softcarrier by default */ ++static bool softcarrier = 1; ++/* 0 = do not invert output, 1 = invert output */ ++static bool invert = 0; ++ ++struct gpio_chip *gpiochip; ++static int irq_num; ++ ++/* forward declarations */ ++static long send_pulse(unsigned long length); ++static void send_space(long length); ++static void lirc_rpi_exit(void); ++ ++static struct platform_device *lirc_rpi_dev; ++static struct timeval lasttv = { 0, 0 }; ++static struct lirc_buffer rbuf; ++static spinlock_t lock; ++ ++/* initialized/set in init_timing_params() */ ++static unsigned int freq = 38000; ++static unsigned int duty_cycle = 50; ++static unsigned long period; ++static unsigned long pulse_width; ++static unsigned long space_width; ++ ++static void safe_udelay(unsigned long usecs) ++{ ++ while (usecs > MAX_UDELAY_US) { ++ udelay(MAX_UDELAY_US); ++ usecs -= MAX_UDELAY_US; ++ } ++ udelay(usecs); ++} ++ ++static unsigned long read_current_us(void) ++{ ++ struct timespec now; ++ getnstimeofday(&now); ++ return (now.tv_sec * 1000000) + (now.tv_nsec/1000); ++} ++ ++static int init_timing_params(unsigned int new_duty_cycle, ++ unsigned int new_freq) ++{ ++ if (1000 * 1000000L / new_freq * new_duty_cycle / 100 <= ++ LIRC_TRANSMITTER_LATENCY) ++ return -EINVAL; ++ if (1000 * 1000000L / new_freq * (100 - new_duty_cycle) / 100 <= ++ LIRC_TRANSMITTER_LATENCY) ++ return -EINVAL; ++ duty_cycle = new_duty_cycle; ++ freq = new_freq; ++ period = 1000 * 1000000L / freq; ++ pulse_width = period * duty_cycle / 100; ++ space_width = period - pulse_width; ++ dprintk("in init_timing_params, freq=%d pulse=%ld, " ++ "space=%ld\n", freq, pulse_width, space_width); ++ return 0; ++} ++ ++static long send_pulse_softcarrier(unsigned long length) ++{ ++ int flag; ++ unsigned long actual, target; ++ unsigned long actual_us, initial_us, target_us; ++ ++ length *= 1000; ++ ++ actual = 0; target = 0; flag = 0; ++ actual_us = read_current_us(); ++ ++ while (actual < length) { ++ if (flag) { ++ gpiochip->set(gpiochip, gpio_out_pin, invert); ++ target += space_width; ++ } else { ++ gpiochip->set(gpiochip, gpio_out_pin, !invert); ++ target += pulse_width; ++ } ++ initial_us = actual_us; ++ target_us = actual_us + (target - actual) / 1000; ++ /* ++ * Note - we've checked in ioctl that the pulse/space ++ * widths are big enough so that d is > 0 ++ */ ++ if ((int)(target_us - actual_us) > 0) ++ udelay(target_us - actual_us); ++ actual_us = read_current_us(); ++ actual += (actual_us - initial_us) * 1000; ++ flag = !flag; ++ } ++ return (actual-length) / 1000; ++} ++ ++static long send_pulse(unsigned long length) ++{ ++ if (length <= 0) ++ return 0; ++ ++ if (softcarrier) { ++ return send_pulse_softcarrier(length); ++ } else { ++ gpiochip->set(gpiochip, gpio_out_pin, !invert); ++ safe_udelay(length); ++ return 0; ++ } ++} ++ ++static void send_space(long length) ++{ ++ gpiochip->set(gpiochip, gpio_out_pin, invert); ++ if (length <= 0) ++ return; ++ safe_udelay(length); ++} ++ ++static void rbwrite(int l) ++{ ++ if (lirc_buffer_full(&rbuf)) { ++ /* no new signals will be accepted */ ++ dprintk("Buffer overrun\n"); ++ return; ++ } ++ lirc_buffer_write(&rbuf, (void *)&l); ++} ++ ++static void frbwrite(int l) ++{ ++ /* simple noise filter */ ++ static int pulse, space; ++ static unsigned int ptr; ++ ++ if (ptr > 0 && (l & PULSE_BIT)) { ++ pulse += l & PULSE_MASK; ++ if (pulse > 250) { ++ rbwrite(space); ++ rbwrite(pulse | PULSE_BIT); ++ ptr = 0; ++ pulse = 0; ++ } ++ return; ++ } ++ if (!(l & PULSE_BIT)) { ++ if (ptr == 0) { ++ if (l > 20000) { ++ space = l; ++ ptr++; ++ return; ++ } ++ } else { ++ if (l > 20000) { ++ space += pulse; ++ if (space > PULSE_MASK) ++ space = PULSE_MASK; ++ space += l; ++ if (space > PULSE_MASK) ++ space = PULSE_MASK; ++ pulse = 0; ++ return; ++ } ++ rbwrite(space); ++ rbwrite(pulse | PULSE_BIT); ++ ptr = 0; ++ pulse = 0; ++ } ++ } ++ rbwrite(l); ++} ++ ++static irqreturn_t irq_handler(int i, void *blah, struct pt_regs *regs) ++{ ++ struct timeval tv; ++ long deltv; ++ int data; ++ int signal; ++ ++ /* use the GPIO signal level */ ++ signal = gpiochip->get(gpiochip, gpio_in_pin); ++ ++ if (sense != -1) { ++ /* get current time */ ++ do_gettimeofday(&tv); ++ ++ /* calc time since last interrupt in microseconds */ ++ deltv = tv.tv_sec-lasttv.tv_sec; ++ if (tv.tv_sec < lasttv.tv_sec || ++ (tv.tv_sec == lasttv.tv_sec && ++ tv.tv_usec < lasttv.tv_usec)) { ++ printk(KERN_WARNING LIRC_DRIVER_NAME ++ ": AIEEEE: your clock just jumped backwards\n"); ++ printk(KERN_WARNING LIRC_DRIVER_NAME ++ ": %d %d %lx %lx %lx %lx\n", signal, sense, ++ tv.tv_sec, lasttv.tv_sec, ++ tv.tv_usec, lasttv.tv_usec); ++ data = PULSE_MASK; ++ } else if (deltv > 15) { ++ data = PULSE_MASK; /* really long time */ ++ if (!(signal^sense)) { ++ /* sanity check */ ++ printk(KERN_WARNING LIRC_DRIVER_NAME ++ ": AIEEEE: %d %d %lx %lx %lx %lx\n", ++ signal, sense, tv.tv_sec, lasttv.tv_sec, ++ tv.tv_usec, lasttv.tv_usec); ++ /* ++ * detecting pulse while this ++ * MUST be a space! ++ */ ++ sense = sense ? 0 : 1; ++ } ++ } else { ++ data = (int) (deltv*1000000 + ++ (tv.tv_usec - lasttv.tv_usec)); ++ } ++ frbwrite(signal^sense ? data : (data|PULSE_BIT)); ++ lasttv = tv; ++ wake_up_interruptible(&rbuf.wait_poll); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static int is_right_chip(struct gpio_chip *chip, void *data) ++{ ++ dprintk("is_right_chip %s %d\n", chip->label, strcmp(data, chip->label)); ++ ++ if (strcmp(data, chip->label) == 0) ++ return 1; ++ return 0; ++} ++ ++static inline int read_bool_property(const struct device_node *np, ++ const char *propname, ++ bool *out_value) ++{ ++ u32 value = 0; ++ int err = of_property_read_u32(np, propname, &value); ++ if (err == 0) ++ *out_value = (value != 0); ++ return err; ++} ++ ++static void read_pin_settings(struct device_node *node) ++{ ++ u32 pin; ++ int index; ++ ++ for (index = 0; ++ of_property_read_u32_index( ++ node, ++ "brcm,pins", ++ index, ++ &pin) == 0; ++ index++) { ++ u32 function; ++ int err; ++ err = of_property_read_u32_index( ++ node, ++ "brcm,function", ++ index, ++ &function); ++ if (err == 0) { ++ if (function == 1) /* Output */ ++ gpio_out_pin = pin; ++ else if (function == 0) /* Input */ ++ gpio_in_pin = pin; ++ } ++ } ++} ++ ++static int init_port(void) ++{ ++ int i, nlow, nhigh, ret; ++ struct device_node *node; ++ ++ node = lirc_rpi_dev->dev.of_node; ++ ++ gpiochip = gpiochip_find("bcm2708_gpio", is_right_chip); ++ ++ /* ++ * Because of the lack of a setpull function, only support ++ * pinctrl-bcm2835 if using device tree. ++ */ ++ if (!gpiochip && node) ++ gpiochip = gpiochip_find("pinctrl-bcm2835", is_right_chip); ++ ++ if (!gpiochip) { ++ pr_err(LIRC_DRIVER_NAME ": gpio chip not found!\n"); ++ return -ENODEV; ++ } ++ ++ if (node) { ++ struct device_node *pins_node; ++ ++ pins_node = of_parse_phandle(node, "pinctrl-0", 0); ++ if (!pins_node) { ++ printk(KERN_ERR LIRC_DRIVER_NAME ++ ": pinctrl settings not found!\n"); ++ ret = -EINVAL; ++ goto exit_init_port; ++ } ++ ++ read_pin_settings(pins_node); ++ ++ of_property_read_u32(node, "rpi,sense", &sense); ++ ++ read_bool_property(node, "rpi,softcarrier", &softcarrier); ++ ++ read_bool_property(node, "rpi,invert", &invert); ++ ++ read_bool_property(node, "rpi,debug", &debug); ++ ++ } ++ else ++ { ++ if (gpio_in_pin >= BCM2708_NR_GPIOS || ++ gpio_out_pin >= BCM2708_NR_GPIOS) { ++ ret = -EINVAL; ++ printk(KERN_ERR LIRC_DRIVER_NAME ++ ": invalid GPIO pin(s) specified!\n"); ++ goto exit_init_port; ++ } ++ ++ if (gpio_request(gpio_out_pin, LIRC_DRIVER_NAME " ir/out")) { ++ printk(KERN_ALERT LIRC_DRIVER_NAME ++ ": cant claim gpio pin %d\n", gpio_out_pin); ++ ret = -ENODEV; ++ goto exit_init_port; ++ } ++ ++ if (gpio_request(gpio_in_pin, LIRC_DRIVER_NAME " ir/in")) { ++ printk(KERN_ALERT LIRC_DRIVER_NAME ++ ": cant claim gpio pin %d\n", gpio_in_pin); ++ ret = -ENODEV; ++ goto exit_gpio_free_out_pin; ++ } ++ ++ bcm2708_gpio_setpull(gpiochip, gpio_in_pin, gpio_in_pull); ++ gpiochip->direction_input(gpiochip, gpio_in_pin); ++ gpiochip->direction_output(gpiochip, gpio_out_pin, 1); ++ } ++ ++ gpiochip->set(gpiochip, gpio_out_pin, invert); ++ ++ irq_num = gpiochip->to_irq(gpiochip, gpio_in_pin); ++ dprintk("to_irq %d\n", irq_num); ++ ++ /* if pin is high, then this must be an active low receiver. */ ++ if (sense == -1) { ++ /* wait 1/2 sec for the power supply */ ++ msleep(500); ++ ++ /* ++ * probe 9 times every 0.04s, collect "votes" for ++ * active high/low ++ */ ++ nlow = 0; ++ nhigh = 0; ++ for (i = 0; i < 9; i++) { ++ if (gpiochip->get(gpiochip, gpio_in_pin)) ++ nlow++; ++ else ++ nhigh++; ++ msleep(40); ++ } ++ sense = (nlow >= nhigh ? 1 : 0); ++ printk(KERN_INFO LIRC_DRIVER_NAME ++ ": auto-detected active %s receiver on GPIO pin %d\n", ++ sense ? "low" : "high", gpio_in_pin); ++ } else { ++ printk(KERN_INFO LIRC_DRIVER_NAME ++ ": manually using active %s receiver on GPIO pin %d\n", ++ sense ? "low" : "high", gpio_in_pin); ++ } ++ ++ return 0; ++ ++ exit_gpio_free_out_pin: ++ gpio_free(gpio_out_pin); ++ ++ exit_init_port: ++ return ret; ++} ++ ++// called when the character device is opened ++static int set_use_inc(void *data) ++{ ++ int result; ++ ++ /* initialize timestamp */ ++ do_gettimeofday(&lasttv); ++ ++ result = request_irq(irq_num, ++ (irq_handler_t) irq_handler, ++ IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING, ++ LIRC_DRIVER_NAME, (void*) 0); ++ ++ switch (result) { ++ case -EBUSY: ++ printk(KERN_ERR LIRC_DRIVER_NAME ++ ": IRQ %d is busy\n", ++ irq_num); ++ return -EBUSY; ++ case -EINVAL: ++ printk(KERN_ERR LIRC_DRIVER_NAME ++ ": Bad irq number or handler\n"); ++ return -EINVAL; ++ default: ++ dprintk("Interrupt %d obtained\n", ++ irq_num); ++ break; ++ }; ++ ++ /* initialize pulse/space widths */ ++ init_timing_params(duty_cycle, freq); ++ ++ return 0; ++} ++ ++static void set_use_dec(void *data) ++{ ++ /* GPIO Pin Falling/Rising Edge Detect Disable */ ++ irq_set_irq_type(irq_num, 0); ++ disable_irq(irq_num); ++ ++ free_irq(irq_num, (void *) 0); ++ ++ dprintk(KERN_INFO LIRC_DRIVER_NAME ++ ": freed IRQ %d\n", irq_num); ++} ++ ++static ssize_t lirc_write(struct file *file, const char *buf, ++ size_t n, loff_t *ppos) ++{ ++ int i, count; ++ unsigned long flags; ++ long delta = 0; ++ int *wbuf; ++ ++ count = n / sizeof(int); ++ if (n % sizeof(int) || count % 2 == 0) ++ return -EINVAL; ++ wbuf = memdup_user(buf, n); ++ if (IS_ERR(wbuf)) ++ return PTR_ERR(wbuf); ++ spin_lock_irqsave(&lock, flags); ++ ++ for (i = 0; i < count; i++) { ++ if (i%2) ++ send_space(wbuf[i] - delta); ++ else ++ delta = send_pulse(wbuf[i]); ++ } ++ gpiochip->set(gpiochip, gpio_out_pin, invert); ++ ++ spin_unlock_irqrestore(&lock, flags); ++ kfree(wbuf); ++ return n; ++} ++ ++static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) ++{ ++ int result; ++ __u32 value; ++ ++ switch (cmd) { ++ case LIRC_GET_SEND_MODE: ++ return -ENOIOCTLCMD; ++ break; ++ ++ case LIRC_SET_SEND_MODE: ++ result = get_user(value, (__u32 *) arg); ++ if (result) ++ return result; ++ /* only LIRC_MODE_PULSE supported */ ++ if (value != LIRC_MODE_PULSE) ++ return -ENOSYS; ++ break; ++ ++ case LIRC_GET_LENGTH: ++ return -ENOSYS; ++ break; ++ ++ case LIRC_SET_SEND_DUTY_CYCLE: ++ dprintk("SET_SEND_DUTY_CYCLE\n"); ++ result = get_user(value, (__u32 *) arg); ++ if (result) ++ return result; ++ if (value <= 0 || value > 100) ++ return -EINVAL; ++ return init_timing_params(value, freq); ++ break; ++ ++ case LIRC_SET_SEND_CARRIER: ++ dprintk("SET_SEND_CARRIER\n"); ++ result = get_user(value, (__u32 *) arg); ++ if (result) ++ return result; ++ if (value > 500000 || value < 20000) ++ return -EINVAL; ++ return init_timing_params(duty_cycle, value); ++ break; ++ ++ default: ++ return lirc_dev_fop_ioctl(filep, cmd, arg); ++ } ++ return 0; ++} ++ ++static const struct file_operations lirc_fops = { ++ .owner = THIS_MODULE, ++ .write = lirc_write, ++ .unlocked_ioctl = lirc_ioctl, ++ .read = lirc_dev_fop_read, ++ .poll = lirc_dev_fop_poll, ++ .open = lirc_dev_fop_open, ++ .release = lirc_dev_fop_close, ++ .llseek = no_llseek, ++}; ++ ++static struct lirc_driver driver = { ++ .name = LIRC_DRIVER_NAME, ++ .minor = -1, ++ .code_length = 1, ++ .sample_rate = 0, ++ .data = NULL, ++ .add_to_buf = NULL, ++ .rbuf = &rbuf, ++ .set_use_inc = set_use_inc, ++ .set_use_dec = set_use_dec, ++ .fops = &lirc_fops, ++ .dev = NULL, ++ .owner = THIS_MODULE, ++}; ++ ++static const struct of_device_id lirc_rpi_of_match[] = { ++ { .compatible = "rpi,lirc-rpi", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, lirc_rpi_of_match); ++ ++static struct platform_driver lirc_rpi_driver = { ++ .driver = { ++ .name = LIRC_DRIVER_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(lirc_rpi_of_match), ++ }, ++}; ++ ++static int __init lirc_rpi_init(void) ++{ ++ struct device_node *node; ++ int result; ++ ++ /* Init read buffer. */ ++ result = lirc_buffer_init(&rbuf, sizeof(int), RBUF_LEN); ++ if (result < 0) ++ return -ENOMEM; ++ ++ result = platform_driver_register(&lirc_rpi_driver); ++ if (result) { ++ printk(KERN_ERR LIRC_DRIVER_NAME ++ ": lirc register returned %d\n", result); ++ goto exit_buffer_free; ++ } ++ ++ node = of_find_compatible_node(NULL, NULL, ++ lirc_rpi_of_match[0].compatible); ++ ++ if (node) { ++ /* DT-enabled */ ++ lirc_rpi_dev = of_find_device_by_node(node); ++ WARN_ON(lirc_rpi_dev->dev.of_node != node); ++ of_node_put(node); ++ } ++ else { ++ lirc_rpi_dev = platform_device_alloc(LIRC_DRIVER_NAME, 0); ++ if (!lirc_rpi_dev) { ++ result = -ENOMEM; ++ goto exit_driver_unregister; ++ } ++ ++ result = platform_device_add(lirc_rpi_dev); ++ if (result) ++ goto exit_device_put; ++ } ++ ++ return 0; ++ ++ exit_device_put: ++ platform_device_put(lirc_rpi_dev); ++ ++ exit_driver_unregister: ++ platform_driver_unregister(&lirc_rpi_driver); ++ ++ exit_buffer_free: ++ lirc_buffer_free(&rbuf); ++ ++ return result; ++} ++ ++static void lirc_rpi_exit(void) ++{ ++ if (!lirc_rpi_dev->dev.of_node) ++ platform_device_unregister(lirc_rpi_dev); ++ platform_driver_unregister(&lirc_rpi_driver); ++ lirc_buffer_free(&rbuf); ++} ++ ++static int __init lirc_rpi_init_module(void) ++{ ++ int result; ++ ++ result = lirc_rpi_init(); ++ if (result) ++ return result; ++ ++ result = init_port(); ++ if (result < 0) ++ goto exit_rpi; ++ ++ driver.features = LIRC_CAN_SET_SEND_DUTY_CYCLE | ++ LIRC_CAN_SET_SEND_CARRIER | ++ LIRC_CAN_SEND_PULSE | ++ LIRC_CAN_REC_MODE2; ++ ++ driver.dev = &lirc_rpi_dev->dev; ++ driver.minor = lirc_register_driver(&driver); ++ ++ if (driver.minor < 0) { ++ printk(KERN_ERR LIRC_DRIVER_NAME ++ ": device registration failed with %d\n", result); ++ result = -EIO; ++ goto exit_rpi; ++ } ++ ++ printk(KERN_INFO LIRC_DRIVER_NAME ": driver registered!\n"); ++ ++ return 0; ++ ++ exit_rpi: ++ lirc_rpi_exit(); ++ ++ return result; ++} ++ ++static void __exit lirc_rpi_exit_module(void) ++{ ++ lirc_unregister_driver(driver.minor); ++ ++ gpio_free(gpio_out_pin); ++ gpio_free(gpio_in_pin); ++ ++ lirc_rpi_exit(); ++ ++ printk(KERN_INFO LIRC_DRIVER_NAME ": cleaned up module\n"); ++} ++ ++module_init(lirc_rpi_init_module); ++module_exit(lirc_rpi_exit_module); ++ ++MODULE_DESCRIPTION("Infra-red receiver and blaster driver for Raspberry Pi GPIO."); ++MODULE_AUTHOR("Aron Robert Szabo "); ++MODULE_AUTHOR("Michael Bishop "); ++MODULE_LICENSE("GPL"); ++ ++module_param(gpio_out_pin, int, S_IRUGO); ++MODULE_PARM_DESC(gpio_out_pin, "GPIO output/transmitter pin number of the BCM" ++ " processor. (default 17"); ++ ++module_param(gpio_in_pin, int, S_IRUGO); ++MODULE_PARM_DESC(gpio_in_pin, "GPIO input pin number of the BCM processor." ++ " (default 18"); ++ ++module_param(gpio_in_pull, int, S_IRUGO); ++MODULE_PARM_DESC(gpio_in_pull, "GPIO input pin pull configuration." ++ " (0 = off, 1 = up, 2 = down, default down)"); ++ ++module_param(sense, int, S_IRUGO); ++MODULE_PARM_DESC(sense, "Override autodetection of IR receiver circuit" ++ " (0 = active high, 1 = active low )"); ++ ++module_param(softcarrier, bool, S_IRUGO); ++MODULE_PARM_DESC(softcarrier, "Software carrier (0 = off, 1 = on, default on)"); ++ ++module_param(invert, bool, S_IRUGO); ++MODULE_PARM_DESC(invert, "Invert output (0 = off, 1 = on, default off"); ++ ++module_param(debug, bool, S_IRUGO | S_IWUSR); ++MODULE_PARM_DESC(debug, "Enable debugging messages"); +diff -Nur linux-4.1.13.orig/drivers/staging/media/lirc/Makefile linux-rpi/drivers/staging/media/lirc/Makefile +--- linux-4.1.13.orig/drivers/staging/media/lirc/Makefile 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/staging/media/lirc/Makefile 2015-11-29 09:42:39.643117031 +0100 +@@ -6,6 +6,7 @@ + obj-$(CONFIG_LIRC_BT829) += lirc_bt829.o + obj-$(CONFIG_LIRC_IMON) += lirc_imon.o + obj-$(CONFIG_LIRC_PARALLEL) += lirc_parallel.o ++obj-$(CONFIG_LIRC_RPI) += lirc_rpi.o + obj-$(CONFIG_LIRC_SASEM) += lirc_sasem.o + obj-$(CONFIG_LIRC_SERIAL) += lirc_serial.o + obj-$(CONFIG_LIRC_SIR) += lirc_sir.o +diff -Nur linux-4.1.13.orig/drivers/thermal/bcm2835-thermal.c linux-rpi/drivers/thermal/bcm2835-thermal.c +--- linux-4.1.13.orig/drivers/thermal/bcm2835-thermal.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/thermal/bcm2835-thermal.c 2015-11-29 09:42:39.795106932 +0100 +@@ -0,0 +1,141 @@ ++/***************************************************************************** ++* Copyright 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#include ++#include ++#include ++#include ++ ++static int bcm2835_thermal_get_property(struct thermal_zone_device *tz, ++ unsigned long *temp, u32 tag) ++{ ++ struct rpi_firmware *fw = tz->devdata; ++ struct { ++ u32 id; ++ u32 val; ++ } packet; ++ int ret; ++ ++ *temp = 0; ++ packet.id = 0; ++ ret = rpi_firmware_property(fw, tag, &packet, sizeof(packet)); ++ if (ret) { ++ dev_err(&tz->device, "Failed to get temperature\n"); ++ return ret; ++ } ++ ++ *temp = packet.val; ++ dev_dbg(&tz->device, "%stemp=%lu\n", ++ tag == RPI_FIRMWARE_GET_MAX_TEMPERATURE ? "max" : "", *temp); ++ ++ return 0; ++} ++ ++static int bcm2835_thermal_get_temp(struct thermal_zone_device *tz, ++ unsigned long *temp) ++{ ++ return bcm2835_thermal_get_property(tz, temp, ++ RPI_FIRMWARE_GET_TEMPERATURE); ++} ++ ++static int bcm2835_thermal_get_max_temp(struct thermal_zone_device *tz, ++ int trip, unsigned long *temp) ++{ ++ /* ++ * The maximum safe temperature of the SoC. ++ * Overclock may be disabled above this temperature. ++ */ ++ return bcm2835_thermal_get_property(tz, temp, ++ RPI_FIRMWARE_GET_MAX_TEMPERATURE); ++} ++ ++static int bcm2835_thermal_get_trip_type(struct thermal_zone_device *tz, ++ int trip, enum thermal_trip_type *type) ++{ ++ *type = THERMAL_TRIP_HOT; ++ ++ return 0; ++} ++ ++static int bcm2835_thermal_get_mode(struct thermal_zone_device *tz, ++ enum thermal_device_mode *mode) ++{ ++ *mode = THERMAL_DEVICE_ENABLED; ++ ++ return 0; ++} ++ ++static struct thermal_zone_device_ops ops = { ++ .get_temp = bcm2835_thermal_get_temp, ++ .get_trip_temp = bcm2835_thermal_get_max_temp, ++ .get_trip_type = bcm2835_thermal_get_trip_type, ++ .get_mode = bcm2835_thermal_get_mode, ++}; ++ ++static int bcm2835_thermal_probe(struct platform_device *pdev) ++{ ++ struct device_node *fw_np; ++ struct rpi_firmware *fw; ++ struct thermal_zone_device *tz; ++ ++ fw_np = of_parse_phandle(pdev->dev.of_node, "firmware", 0); ++/* Remove comment when booting without Device Tree is no longer supported ++ if (!fw_np) { ++ dev_err(&pdev->dev, "Missing firmware node\n"); ++ return -ENOENT; ++ } ++*/ ++ fw = rpi_firmware_get(fw_np); ++ if (!fw) ++ return -EPROBE_DEFER; ++ ++ tz = thermal_zone_device_register("bcm2835_thermal", 1, 0, fw, &ops, ++ NULL, 0, 0); ++ if (IS_ERR(tz)) { ++ dev_err(&pdev->dev, "Failed to register the thermal device\n"); ++ return PTR_ERR(tz); ++ } ++ ++ platform_set_drvdata(pdev, tz); ++ ++ return 0; ++} ++ ++static int bcm2835_thermal_remove(struct platform_device *pdev) ++{ ++ thermal_zone_device_unregister(platform_get_drvdata(pdev)); ++ ++ return 0; ++} ++ ++static const struct of_device_id bcm2835_thermal_of_match_table[] = { ++ { .compatible = "brcm,bcm2835-thermal", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, bcm2835_thermal_of_match_table); ++ ++static struct platform_driver bcm2835_thermal_driver = { ++ .probe = bcm2835_thermal_probe, ++ .remove = bcm2835_thermal_remove, ++ .driver = { ++ .name = "bcm2835_thermal", ++ .of_match_table = bcm2835_thermal_of_match_table, ++ }, ++}; ++module_platform_driver(bcm2835_thermal_driver); ++ ++MODULE_AUTHOR("Dorian Peake"); ++MODULE_AUTHOR("Noralf Trønnes"); ++MODULE_DESCRIPTION("Thermal driver for bcm2835 chip"); ++MODULE_LICENSE("GPL"); +diff -Nur linux-4.1.13.orig/drivers/thermal/Kconfig linux-rpi/drivers/thermal/Kconfig +--- linux-4.1.13.orig/drivers/thermal/Kconfig 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/thermal/Kconfig 2015-11-29 09:42:39.795106932 +0100 +@@ -238,6 +238,13 @@ + enforce idle time which results in more package C-state residency. The + user interface is exposed via generic thermal framework. + ++config THERMAL_BCM2835 ++ depends on RASPBERRYPI_FIRMWARE ++ tristate "BCM2835 Thermal Driver" ++ help ++ This will enable temperature monitoring for the Broadcom BCM2835 ++ chip. If built as a module, it will be called 'bcm2835-thermal'. ++ + config X86_PKG_TEMP_THERMAL + tristate "X86 package temperature thermal driver" + depends on X86_THERMAL_VECTOR +diff -Nur linux-4.1.13.orig/drivers/thermal/Makefile linux-rpi/drivers/thermal/Makefile +--- linux-4.1.13.orig/drivers/thermal/Makefile 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/thermal/Makefile 2015-11-29 09:42:39.795106932 +0100 +@@ -33,6 +33,7 @@ + obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o + obj-$(CONFIG_DB8500_CPUFREQ_COOLING) += db8500_cpufreq_cooling.o + obj-$(CONFIG_INTEL_POWERCLAMP) += intel_powerclamp.o ++obj-$(CONFIG_THERMAL_BCM2835) += bcm2835-thermal.o + obj-$(CONFIG_X86_PKG_TEMP_THERMAL) += x86_pkg_temp_thermal.o + obj-$(CONFIG_INTEL_SOC_DTS_THERMAL) += intel_soc_dts_thermal.o + obj-$(CONFIG_TI_SOC_THERMAL) += ti-soc-thermal/ +diff -Nur linux-4.1.13.orig/drivers/tty/serial/8250/8250_core.c linux-rpi/drivers/tty/serial/8250/8250_core.c +--- linux-4.1.13.orig/drivers/tty/serial/8250/8250_core.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/tty/serial/8250/8250_core.c 2015-11-29 09:42:39.811105869 +0100 +@@ -3270,6 +3270,8 @@ + + if (nr_uarts > UART_NR) + nr_uarts = UART_NR; ++ if (!nr_uarts) ++ return; + + for (i = 0; i < nr_uarts; i++) { + struct uart_8250_port *up = &serial8250_ports[i]; +diff -Nur linux-4.1.13.orig/drivers/tty/serial/amba-pl011.c linux-rpi/drivers/tty/serial/amba-pl011.c +--- linux-4.1.13.orig/drivers/tty/serial/amba-pl011.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/tty/serial/amba-pl011.c 2015-11-29 09:42:39.815105604 +0100 +@@ -85,7 +85,7 @@ + + static unsigned int get_fifosize_arm(struct amba_device *dev) + { +- return amba_rev(dev) < 3 ? 16 : 32; ++ return 16; //TODO: fix: amba_rev(dev) < 3 ? 16 : 32; + } + + static struct vendor_data vendor_arm = { +diff -Nur linux-4.1.13.orig/drivers/usb/core/generic.c linux-rpi/drivers/usb/core/generic.c +--- linux-4.1.13.orig/drivers/usb/core/generic.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/usb/core/generic.c 2015-11-29 09:42:39.871101883 +0100 +@@ -152,6 +152,7 @@ + dev_warn(&udev->dev, + "no configuration chosen from %d choice%s\n", + num_configs, plural(num_configs)); ++ dev_warn(&udev->dev, "No support over %dmA\n", udev->bus_mA); + } + return i; + } +diff -Nur linux-4.1.13.orig/drivers/usb/core/hub.c linux-rpi/drivers/usb/core/hub.c +--- linux-4.1.13.orig/drivers/usb/core/hub.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/usb/core/hub.c 2015-11-29 09:42:39.875101617 +0100 +@@ -4906,7 +4906,7 @@ + if (portchange & USB_PORT_STAT_C_OVERCURRENT) { + u16 status = 0, unused; + +- dev_dbg(&port_dev->dev, "over-current change\n"); ++ dev_notice(&port_dev->dev, "over-current change\n"); + usb_clear_port_feature(hdev, port1, + USB_PORT_FEAT_C_OVER_CURRENT); + msleep(100); /* Cool down */ +diff -Nur linux-4.1.13.orig/drivers/usb/core/message.c linux-rpi/drivers/usb/core/message.c +--- linux-4.1.13.orig/drivers/usb/core/message.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/usb/core/message.c 2015-11-29 09:42:39.875101617 +0100 +@@ -1872,6 +1872,85 @@ + if (cp->string == NULL && + !(dev->quirks & USB_QUIRK_CONFIG_INTF_STRINGS)) + cp->string = usb_cache_string(dev, cp->desc.iConfiguration); ++/* Uncomment this define to enable the HS Electrical Test support */ ++#define DWC_HS_ELECT_TST 1 ++#ifdef DWC_HS_ELECT_TST ++ /* Here we implement the HS Electrical Test support. The ++ * tester uses a vendor ID of 0x1A0A to indicate we should ++ * run a special test sequence. The product ID tells us ++ * which sequence to run. We invoke the test sequence by ++ * sending a non-standard SetFeature command to our root ++ * hub port. Our dwc_otg_hcd_hub_control() routine will ++ * recognize the command and perform the desired test ++ * sequence. ++ */ ++ if (dev->descriptor.idVendor == 0x1A0A) { ++ /* HSOTG Electrical Test */ ++ dev_warn(&dev->dev, "VID from HSOTG Electrical Test Fixture\n"); ++ ++ if (dev->bus && dev->bus->root_hub) { ++ struct usb_device *hdev = dev->bus->root_hub; ++ dev_warn(&dev->dev, "Got PID 0x%x\n", dev->descriptor.idProduct); ++ ++ switch (dev->descriptor.idProduct) { ++ case 0x0101: /* TEST_SE0_NAK */ ++ dev_warn(&dev->dev, "TEST_SE0_NAK\n"); ++ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0), ++ USB_REQ_SET_FEATURE, USB_RT_PORT, ++ USB_PORT_FEAT_TEST, 0x300, NULL, 0, HZ); ++ break; ++ ++ case 0x0102: /* TEST_J */ ++ dev_warn(&dev->dev, "TEST_J\n"); ++ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0), ++ USB_REQ_SET_FEATURE, USB_RT_PORT, ++ USB_PORT_FEAT_TEST, 0x100, NULL, 0, HZ); ++ break; ++ ++ case 0x0103: /* TEST_K */ ++ dev_warn(&dev->dev, "TEST_K\n"); ++ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0), ++ USB_REQ_SET_FEATURE, USB_RT_PORT, ++ USB_PORT_FEAT_TEST, 0x200, NULL, 0, HZ); ++ break; ++ ++ case 0x0104: /* TEST_PACKET */ ++ dev_warn(&dev->dev, "TEST_PACKET\n"); ++ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0), ++ USB_REQ_SET_FEATURE, USB_RT_PORT, ++ USB_PORT_FEAT_TEST, 0x400, NULL, 0, HZ); ++ break; ++ ++ case 0x0105: /* TEST_FORCE_ENABLE */ ++ dev_warn(&dev->dev, "TEST_FORCE_ENABLE\n"); ++ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0), ++ USB_REQ_SET_FEATURE, USB_RT_PORT, ++ USB_PORT_FEAT_TEST, 0x500, NULL, 0, HZ); ++ break; ++ ++ case 0x0106: /* HS_HOST_PORT_SUSPEND_RESUME */ ++ dev_warn(&dev->dev, "HS_HOST_PORT_SUSPEND_RESUME\n"); ++ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0), ++ USB_REQ_SET_FEATURE, USB_RT_PORT, ++ USB_PORT_FEAT_TEST, 0x600, NULL, 0, 40 * HZ); ++ break; ++ ++ case 0x0107: /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */ ++ dev_warn(&dev->dev, "SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup\n"); ++ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0), ++ USB_REQ_SET_FEATURE, USB_RT_PORT, ++ USB_PORT_FEAT_TEST, 0x700, NULL, 0, 40 * HZ); ++ break; ++ ++ case 0x0108: /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */ ++ dev_warn(&dev->dev, "SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute\n"); ++ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0), ++ USB_REQ_SET_FEATURE, USB_RT_PORT, ++ USB_PORT_FEAT_TEST, 0x800, NULL, 0, 40 * HZ); ++ } ++ } ++ } ++#endif /* DWC_HS_ELECT_TST */ + + /* Now that the interfaces are installed, re-enable LPM. */ + usb_unlocked_enable_lpm(dev); +diff -Nur linux-4.1.13.orig/drivers/usb/core/otg_whitelist.h linux-rpi/drivers/usb/core/otg_whitelist.h +--- linux-4.1.13.orig/drivers/usb/core/otg_whitelist.h 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/usb/core/otg_whitelist.h 2015-11-29 09:42:39.875101617 +0100 +@@ -19,33 +19,82 @@ + static struct usb_device_id whitelist_table [] = { + + /* hubs are optional in OTG, but very handy ... */ ++#define CERT_WITHOUT_HUBS ++#if defined(CERT_WITHOUT_HUBS) ++{ USB_DEVICE( 0x0000, 0x0000 ), }, /* Root HUB Only*/ ++#else + { USB_DEVICE_INFO(USB_CLASS_HUB, 0, 0), }, + { USB_DEVICE_INFO(USB_CLASS_HUB, 0, 1), }, ++{ USB_DEVICE_INFO(USB_CLASS_HUB, 0, 2), }, ++#endif + + #ifdef CONFIG_USB_PRINTER /* ignoring nonstatic linkage! */ + /* FIXME actually, printers are NOT supposed to use device classes; + * they're supposed to use interface classes... + */ +-{ USB_DEVICE_INFO(7, 1, 1) }, +-{ USB_DEVICE_INFO(7, 1, 2) }, +-{ USB_DEVICE_INFO(7, 1, 3) }, ++//{ USB_DEVICE_INFO(7, 1, 1) }, ++//{ USB_DEVICE_INFO(7, 1, 2) }, ++//{ USB_DEVICE_INFO(7, 1, 3) }, + #endif + + #ifdef CONFIG_USB_NET_CDCETHER + /* Linux-USB CDC Ethernet gadget */ +-{ USB_DEVICE(0x0525, 0xa4a1), }, ++//{ USB_DEVICE(0x0525, 0xa4a1), }, + /* Linux-USB CDC Ethernet + RNDIS gadget */ +-{ USB_DEVICE(0x0525, 0xa4a2), }, ++//{ USB_DEVICE(0x0525, 0xa4a2), }, + #endif + + #if defined(CONFIG_USB_TEST) || defined(CONFIG_USB_TEST_MODULE) + /* gadget zero, for testing */ +-{ USB_DEVICE(0x0525, 0xa4a0), }, ++//{ USB_DEVICE(0x0525, 0xa4a0), }, + #endif + ++/* OPT Tester */ ++{ USB_DEVICE( 0x1a0a, 0x0101 ), }, /* TEST_SE0_NAK */ ++{ USB_DEVICE( 0x1a0a, 0x0102 ), }, /* Test_J */ ++{ USB_DEVICE( 0x1a0a, 0x0103 ), }, /* Test_K */ ++{ USB_DEVICE( 0x1a0a, 0x0104 ), }, /* Test_PACKET */ ++{ USB_DEVICE( 0x1a0a, 0x0105 ), }, /* Test_FORCE_ENABLE */ ++{ USB_DEVICE( 0x1a0a, 0x0106 ), }, /* HS_PORT_SUSPEND_RESUME */ ++{ USB_DEVICE( 0x1a0a, 0x0107 ), }, /* SINGLE_STEP_GET_DESCRIPTOR setup */ ++{ USB_DEVICE( 0x1a0a, 0x0108 ), }, /* SINGLE_STEP_GET_DESCRIPTOR execute */ ++ ++/* Sony cameras */ ++{ USB_DEVICE_VER(0x054c,0x0010,0x0410, 0x0500), }, ++ ++/* Memory Devices */ ++//{ USB_DEVICE( 0x0781, 0x5150 ), }, /* SanDisk */ ++//{ USB_DEVICE( 0x05DC, 0x0080 ), }, /* Lexar */ ++//{ USB_DEVICE( 0x4146, 0x9281 ), }, /* IOMEGA */ ++//{ USB_DEVICE( 0x067b, 0x2507 ), }, /* Hammer 20GB External HD */ ++{ USB_DEVICE( 0x0EA0, 0x2168 ), }, /* Ours Technology Inc. (BUFFALO ClipDrive)*/ ++//{ USB_DEVICE( 0x0457, 0x0150 ), }, /* Silicon Integrated Systems Corp. */ ++ ++/* HP Printers */ ++//{ USB_DEVICE( 0x03F0, 0x1102 ), }, /* HP Photosmart 245 */ ++//{ USB_DEVICE( 0x03F0, 0x1302 ), }, /* HP Photosmart 370 Series */ ++ ++/* Speakers */ ++//{ USB_DEVICE( 0x0499, 0x3002 ), }, /* YAMAHA YST-MS35D USB Speakers */ ++//{ USB_DEVICE( 0x0672, 0x1041 ), }, /* Labtec USB Headset */ ++ + { } /* Terminating entry */ + }; + ++static inline void report_errors(struct usb_device *dev) ++{ ++ /* OTG MESSAGE: report errors here, customize to match your product */ ++ dev_info(&dev->dev, "device Vendor:%04x Product:%04x is not supported\n", ++ le16_to_cpu(dev->descriptor.idVendor), ++ le16_to_cpu(dev->descriptor.idProduct)); ++ if (USB_CLASS_HUB == dev->descriptor.bDeviceClass){ ++ dev_printk(KERN_CRIT, &dev->dev, "Unsupported Hub Topology\n"); ++ } else { ++ dev_printk(KERN_CRIT, &dev->dev, "Attached Device is not Supported\n"); ++ } ++} ++ ++ + static int is_targeted(struct usb_device *dev) + { + struct usb_device_id *id = whitelist_table; +@@ -95,16 +144,57 @@ + continue; + + return 1; +- } ++ /* NOTE: can't use usb_match_id() since interface caches ++ * aren't set up yet. this is cut/paste from that code. ++ */ ++ for (id = whitelist_table; id->match_flags; id++) { ++#ifdef DEBUG ++ dev_dbg(&dev->dev, ++ "ID: V:%04x P:%04x DC:%04x SC:%04x PR:%04x \n", ++ id->idVendor, ++ id->idProduct, ++ id->bDeviceClass, ++ id->bDeviceSubClass, ++ id->bDeviceProtocol); ++#endif + +- /* add other match criteria here ... */ ++ if ((id->match_flags & USB_DEVICE_ID_MATCH_VENDOR) && ++ id->idVendor != le16_to_cpu(dev->descriptor.idVendor)) ++ continue; ++ ++ if ((id->match_flags & USB_DEVICE_ID_MATCH_PRODUCT) && ++ id->idProduct != le16_to_cpu(dev->descriptor.idProduct)) ++ continue; ++ ++ /* No need to test id->bcdDevice_lo != 0, since 0 is never ++ greater than any unsigned number. */ ++ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_LO) && ++ (id->bcdDevice_lo > le16_to_cpu(dev->descriptor.bcdDevice))) ++ continue; ++ ++ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_HI) && ++ (id->bcdDevice_hi < le16_to_cpu(dev->descriptor.bcdDevice))) ++ continue; ++ ++ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_CLASS) && ++ (id->bDeviceClass != dev->descriptor.bDeviceClass)) ++ continue; ++ ++ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_SUBCLASS) && ++ (id->bDeviceSubClass != dev->descriptor.bDeviceSubClass)) ++ continue; ++ ++ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_PROTOCOL) && ++ (id->bDeviceProtocol != dev->descriptor.bDeviceProtocol)) ++ continue; + ++ return 1; ++ } ++ } + +- /* OTG MESSAGE: report errors here, customize to match your product */ +- dev_err(&dev->dev, "device v%04x p%04x is not supported\n", +- le16_to_cpu(dev->descriptor.idVendor), +- le16_to_cpu(dev->descriptor.idProduct)); ++ /* add other match criteria here ... */ + ++ report_errors(dev); + return 0; + } + +diff -Nur linux-4.1.13.orig/drivers/usb/gadget/file_storage.c linux-rpi/drivers/usb/gadget/file_storage.c +--- linux-4.1.13.orig/drivers/usb/gadget/file_storage.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/gadget/file_storage.c 2015-11-29 09:42:39.887100820 +0100 +@@ -0,0 +1,3676 @@ ++/* ++ * file_storage.c -- File-backed USB Storage Gadget, for USB development ++ * ++ * Copyright (C) 2003-2008 Alan Stern ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") as published by the Free Software ++ * Foundation, either version 2 of that License or (at your option) any ++ * later version. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++ ++/* ++ * The File-backed Storage Gadget acts as a USB Mass Storage device, ++ * appearing to the host as a disk drive or as a CD-ROM drive. In addition ++ * to providing an example of a genuinely useful gadget driver for a USB ++ * device, it also illustrates a technique of double-buffering for increased ++ * throughput. Last but not least, it gives an easy way to probe the ++ * behavior of the Mass Storage drivers in a USB host. ++ * ++ * Backing storage is provided by a regular file or a block device, specified ++ * by the "file" module parameter. Access can be limited to read-only by ++ * setting the optional "ro" module parameter. (For CD-ROM emulation, ++ * access is always read-only.) The gadget will indicate that it has ++ * removable media if the optional "removable" module parameter is set. ++ * ++ * The gadget supports the Control-Bulk (CB), Control-Bulk-Interrupt (CBI), ++ * and Bulk-Only (also known as Bulk-Bulk-Bulk or BBB) transports, selected ++ * by the optional "transport" module parameter. It also supports the ++ * following protocols: RBC (0x01), ATAPI or SFF-8020i (0x02), QIC-157 (0c03), ++ * UFI (0x04), SFF-8070i (0x05), and transparent SCSI (0x06), selected by ++ * the optional "protocol" module parameter. In addition, the default ++ * Vendor ID, Product ID, release number and serial number can be overridden. ++ * ++ * There is support for multiple logical units (LUNs), each of which has ++ * its own backing file. The number of LUNs can be set using the optional ++ * "luns" module parameter (anywhere from 1 to 8), and the corresponding ++ * files are specified using comma-separated lists for "file" and "ro". ++ * The default number of LUNs is taken from the number of "file" elements; ++ * it is 1 if "file" is not given. If "removable" is not set then a backing ++ * file must be specified for each LUN. If it is set, then an unspecified ++ * or empty backing filename means the LUN's medium is not loaded. Ideally ++ * each LUN would be settable independently as a disk drive or a CD-ROM ++ * drive, but currently all LUNs have to be the same type. The CD-ROM ++ * emulation includes a single data track and no audio tracks; hence there ++ * need be only one backing file per LUN. ++ * ++ * Requirements are modest; only a bulk-in and a bulk-out endpoint are ++ * needed (an interrupt-out endpoint is also needed for CBI). The memory ++ * requirement amounts to two 16K buffers, size configurable by a parameter. ++ * Support is included for both full-speed and high-speed operation. ++ * ++ * Note that the driver is slightly non-portable in that it assumes a ++ * single memory/DMA buffer will be useable for bulk-in, bulk-out, and ++ * interrupt-in endpoints. With most device controllers this isn't an ++ * issue, but there may be some with hardware restrictions that prevent ++ * a buffer from being used by more than one endpoint. ++ * ++ * Module options: ++ * ++ * file=filename[,filename...] ++ * Required if "removable" is not set, names of ++ * the files or block devices used for ++ * backing storage ++ * serial=HHHH... Required serial number (string of hex chars) ++ * ro=b[,b...] Default false, booleans for read-only access ++ * removable Default false, boolean for removable media ++ * luns=N Default N = number of filenames, number of ++ * LUNs to support ++ * nofua=b[,b...] Default false, booleans for ignore FUA flag ++ * in SCSI WRITE(10,12) commands ++ * stall Default determined according to the type of ++ * USB device controller (usually true), ++ * boolean to permit the driver to halt ++ * bulk endpoints ++ * cdrom Default false, boolean for whether to emulate ++ * a CD-ROM drive ++ * transport=XXX Default BBB, transport name (CB, CBI, or BBB) ++ * protocol=YYY Default SCSI, protocol name (RBC, 8020 or ++ * ATAPI, QIC, UFI, 8070, or SCSI; ++ * also 1 - 6) ++ * vendor=0xVVVV Default 0x0525 (NetChip), USB Vendor ID ++ * product=0xPPPP Default 0xa4a5 (FSG), USB Product ID ++ * release=0xRRRR Override the USB release number (bcdDevice) ++ * buflen=N Default N=16384, buffer size used (will be ++ * rounded down to a multiple of ++ * PAGE_CACHE_SIZE) ++ * ++ * If CONFIG_USB_FILE_STORAGE_TEST is not set, only the "file", "serial", "ro", ++ * "removable", "luns", "nofua", "stall", and "cdrom" options are available; ++ * default values are used for everything else. ++ * ++ * The pathnames of the backing files and the ro settings are available in ++ * the attribute files "file", "nofua", and "ro" in the lun subdirectory of ++ * the gadget's sysfs directory. If the "removable" option is set, writing to ++ * these files will simulate ejecting/loading the medium (writing an empty ++ * line means eject) and adjusting a write-enable tab. Changes to the ro ++ * setting are not allowed when the medium is loaded or if CD-ROM emulation ++ * is being used. ++ * ++ * This gadget driver is heavily based on "Gadget Zero" by David Brownell. ++ * The driver's SCSI command interface was based on the "Information ++ * technology - Small Computer System Interface - 2" document from ++ * X3T9.2 Project 375D, Revision 10L, 7-SEP-93, available at ++ * . The single exception ++ * is opcode 0x23 (READ FORMAT CAPACITIES), which was based on the ++ * "Universal Serial Bus Mass Storage Class UFI Command Specification" ++ * document, Revision 1.0, December 14, 1998, available at ++ * . ++ */ ++ ++ ++/* ++ * Driver Design ++ * ++ * The FSG driver is fairly straightforward. There is a main kernel ++ * thread that handles most of the work. Interrupt routines field ++ * callbacks from the controller driver: bulk- and interrupt-request ++ * completion notifications, endpoint-0 events, and disconnect events. ++ * Completion events are passed to the main thread by wakeup calls. Many ++ * ep0 requests are handled at interrupt time, but SetInterface, ++ * SetConfiguration, and device reset requests are forwarded to the ++ * thread in the form of "exceptions" using SIGUSR1 signals (since they ++ * should interrupt any ongoing file I/O operations). ++ * ++ * The thread's main routine implements the standard command/data/status ++ * parts of a SCSI interaction. It and its subroutines are full of tests ++ * for pending signals/exceptions -- all this polling is necessary since ++ * the kernel has no setjmp/longjmp equivalents. (Maybe this is an ++ * indication that the driver really wants to be running in userspace.) ++ * An important point is that so long as the thread is alive it keeps an ++ * open reference to the backing file. This will prevent unmounting ++ * the backing file's underlying filesystem and could cause problems ++ * during system shutdown, for example. To prevent such problems, the ++ * thread catches INT, TERM, and KILL signals and converts them into ++ * an EXIT exception. ++ * ++ * In normal operation the main thread is started during the gadget's ++ * fsg_bind() callback and stopped during fsg_unbind(). But it can also ++ * exit when it receives a signal, and there's no point leaving the ++ * gadget running when the thread is dead. So just before the thread ++ * exits, it deregisters the gadget driver. This makes things a little ++ * tricky: The driver is deregistered at two places, and the exiting ++ * thread can indirectly call fsg_unbind() which in turn can tell the ++ * thread to exit. The first problem is resolved through the use of the ++ * REGISTERED atomic bitflag; the driver will only be deregistered once. ++ * The second problem is resolved by having fsg_unbind() check ++ * fsg->state; it won't try to stop the thread if the state is already ++ * FSG_STATE_TERMINATED. ++ * ++ * To provide maximum throughput, the driver uses a circular pipeline of ++ * buffer heads (struct fsg_buffhd). In principle the pipeline can be ++ * arbitrarily long; in practice the benefits don't justify having more ++ * than 2 stages (i.e., double buffering). But it helps to think of the ++ * pipeline as being a long one. Each buffer head contains a bulk-in and ++ * a bulk-out request pointer (since the buffer can be used for both ++ * output and input -- directions always are given from the host's ++ * point of view) as well as a pointer to the buffer and various state ++ * variables. ++ * ++ * Use of the pipeline follows a simple protocol. There is a variable ++ * (fsg->next_buffhd_to_fill) that points to the next buffer head to use. ++ * At any time that buffer head may still be in use from an earlier ++ * request, so each buffer head has a state variable indicating whether ++ * it is EMPTY, FULL, or BUSY. Typical use involves waiting for the ++ * buffer head to be EMPTY, filling the buffer either by file I/O or by ++ * USB I/O (during which the buffer head is BUSY), and marking the buffer ++ * head FULL when the I/O is complete. Then the buffer will be emptied ++ * (again possibly by USB I/O, during which it is marked BUSY) and ++ * finally marked EMPTY again (possibly by a completion routine). ++ * ++ * A module parameter tells the driver to avoid stalling the bulk ++ * endpoints wherever the transport specification allows. This is ++ * necessary for some UDCs like the SuperH, which cannot reliably clear a ++ * halt on a bulk endpoint. However, under certain circumstances the ++ * Bulk-only specification requires a stall. In such cases the driver ++ * will halt the endpoint and set a flag indicating that it should clear ++ * the halt in software during the next device reset. Hopefully this ++ * will permit everything to work correctly. Furthermore, although the ++ * specification allows the bulk-out endpoint to halt when the host sends ++ * too much data, implementing this would cause an unavoidable race. ++ * The driver will always use the "no-stall" approach for OUT transfers. ++ * ++ * One subtle point concerns sending status-stage responses for ep0 ++ * requests. Some of these requests, such as device reset, can involve ++ * interrupting an ongoing file I/O operation, which might take an ++ * arbitrarily long time. During that delay the host might give up on ++ * the original ep0 request and issue a new one. When that happens the ++ * driver should not notify the host about completion of the original ++ * request, as the host will no longer be waiting for it. So the driver ++ * assigns to each ep0 request a unique tag, and it keeps track of the ++ * tag value of the request associated with a long-running exception ++ * (device-reset, interface-change, or configuration-change). When the ++ * exception handler is finished, the status-stage response is submitted ++ * only if the current ep0 request tag is equal to the exception request ++ * tag. Thus only the most recently received ep0 request will get a ++ * status-stage response. ++ * ++ * Warning: This driver source file is too long. It ought to be split up ++ * into a header file plus about 3 separate .c files, to handle the details ++ * of the Gadget, USB Mass Storage, and SCSI protocols. ++ */ ++ ++ ++/* #define VERBOSE_DEBUG */ ++/* #define DUMP_MSGS */ ++ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "gadget_chips.h" ++ ++ ++ ++/* ++ * Kbuild is not very cooperative with respect to linking separately ++ * compiled library objects into one module. So for now we won't use ++ * separate compilation ... ensuring init/exit sections work to shrink ++ * the runtime footprint, and giving us at least some parts of what ++ * a "gcc --combine ... part1.c part2.c part3.c ... " build would. ++ */ ++#include "usbstring.c" ++#include "config.c" ++#include "epautoconf.c" ++ ++/*-------------------------------------------------------------------------*/ ++ ++#define DRIVER_DESC "File-backed Storage Gadget" ++#define DRIVER_NAME "g_file_storage" ++#define DRIVER_VERSION "1 September 2010" ++ ++static char fsg_string_manufacturer[64]; ++static const char fsg_string_product[] = DRIVER_DESC; ++static const char fsg_string_config[] = "Self-powered"; ++static const char fsg_string_interface[] = "Mass Storage"; ++ ++ ++#include "storage_common.c" ++ ++ ++MODULE_DESCRIPTION(DRIVER_DESC); ++MODULE_AUTHOR("Alan Stern"); ++MODULE_LICENSE("Dual BSD/GPL"); ++ ++/* ++ * This driver assumes self-powered hardware and has no way for users to ++ * trigger remote wakeup. It uses autoconfiguration to select endpoints ++ * and endpoint addresses. ++ */ ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++ ++/* Encapsulate the module parameter settings */ ++ ++static struct { ++ char *file[FSG_MAX_LUNS]; ++ char *serial; ++ bool ro[FSG_MAX_LUNS]; ++ bool nofua[FSG_MAX_LUNS]; ++ unsigned int num_filenames; ++ unsigned int num_ros; ++ unsigned int num_nofuas; ++ unsigned int nluns; ++ ++ bool removable; ++ bool can_stall; ++ bool cdrom; ++ ++ char *transport_parm; ++ char *protocol_parm; ++ unsigned short vendor; ++ unsigned short product; ++ unsigned short release; ++ unsigned int buflen; ++ ++ int transport_type; ++ char *transport_name; ++ int protocol_type; ++ char *protocol_name; ++ ++} mod_data = { // Default values ++ .transport_parm = "BBB", ++ .protocol_parm = "SCSI", ++ .removable = 0, ++ .can_stall = 1, ++ .cdrom = 0, ++ .vendor = FSG_VENDOR_ID, ++ .product = FSG_PRODUCT_ID, ++ .release = 0xffff, // Use controller chip type ++ .buflen = 16384, ++ }; ++ ++ ++module_param_array_named(file, mod_data.file, charp, &mod_data.num_filenames, ++ S_IRUGO); ++MODULE_PARM_DESC(file, "names of backing files or devices"); ++ ++module_param_named(serial, mod_data.serial, charp, S_IRUGO); ++MODULE_PARM_DESC(serial, "USB serial number"); ++ ++module_param_array_named(ro, mod_data.ro, bool, &mod_data.num_ros, S_IRUGO); ++MODULE_PARM_DESC(ro, "true to force read-only"); ++ ++module_param_array_named(nofua, mod_data.nofua, bool, &mod_data.num_nofuas, ++ S_IRUGO); ++MODULE_PARM_DESC(nofua, "true to ignore SCSI WRITE(10,12) FUA bit"); ++ ++module_param_named(luns, mod_data.nluns, uint, S_IRUGO); ++MODULE_PARM_DESC(luns, "number of LUNs"); ++ ++module_param_named(removable, mod_data.removable, bool, S_IRUGO); ++MODULE_PARM_DESC(removable, "true to simulate removable media"); ++ ++module_param_named(stall, mod_data.can_stall, bool, S_IRUGO); ++MODULE_PARM_DESC(stall, "false to prevent bulk stalls"); ++ ++module_param_named(cdrom, mod_data.cdrom, bool, S_IRUGO); ++MODULE_PARM_DESC(cdrom, "true to emulate cdrom instead of disk"); ++ ++/* In the non-TEST version, only the module parameters listed above ++ * are available. */ ++#ifdef CONFIG_USB_FILE_STORAGE_TEST ++ ++module_param_named(transport, mod_data.transport_parm, charp, S_IRUGO); ++MODULE_PARM_DESC(transport, "type of transport (BBB, CBI, or CB)"); ++ ++module_param_named(protocol, mod_data.protocol_parm, charp, S_IRUGO); ++MODULE_PARM_DESC(protocol, "type of protocol (RBC, 8020, QIC, UFI, " ++ "8070, or SCSI)"); ++ ++module_param_named(vendor, mod_data.vendor, ushort, S_IRUGO); ++MODULE_PARM_DESC(vendor, "USB Vendor ID"); ++ ++module_param_named(product, mod_data.product, ushort, S_IRUGO); ++MODULE_PARM_DESC(product, "USB Product ID"); ++ ++module_param_named(release, mod_data.release, ushort, S_IRUGO); ++MODULE_PARM_DESC(release, "USB release number"); ++ ++module_param_named(buflen, mod_data.buflen, uint, S_IRUGO); ++MODULE_PARM_DESC(buflen, "I/O buffer size"); ++ ++#endif /* CONFIG_USB_FILE_STORAGE_TEST */ ++ ++ ++/* ++ * These definitions will permit the compiler to avoid generating code for ++ * parts of the driver that aren't used in the non-TEST version. Even gcc ++ * can recognize when a test of a constant expression yields a dead code ++ * path. ++ */ ++ ++#ifdef CONFIG_USB_FILE_STORAGE_TEST ++ ++#define transport_is_bbb() (mod_data.transport_type == USB_PR_BULK) ++#define transport_is_cbi() (mod_data.transport_type == USB_PR_CBI) ++#define protocol_is_scsi() (mod_data.protocol_type == USB_SC_SCSI) ++ ++#else ++ ++#define transport_is_bbb() 1 ++#define transport_is_cbi() 0 ++#define protocol_is_scsi() 1 ++ ++#endif /* CONFIG_USB_FILE_STORAGE_TEST */ ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++ ++struct fsg_dev { ++ /* lock protects: state, all the req_busy's, and cbbuf_cmnd */ ++ spinlock_t lock; ++ struct usb_gadget *gadget; ++ ++ /* filesem protects: backing files in use */ ++ struct rw_semaphore filesem; ++ ++ /* reference counting: wait until all LUNs are released */ ++ struct kref ref; ++ ++ struct usb_ep *ep0; // Handy copy of gadget->ep0 ++ struct usb_request *ep0req; // For control responses ++ unsigned int ep0_req_tag; ++ const char *ep0req_name; ++ ++ struct usb_request *intreq; // For interrupt responses ++ int intreq_busy; ++ struct fsg_buffhd *intr_buffhd; ++ ++ unsigned int bulk_out_maxpacket; ++ enum fsg_state state; // For exception handling ++ unsigned int exception_req_tag; ++ ++ u8 config, new_config; ++ ++ unsigned int running : 1; ++ unsigned int bulk_in_enabled : 1; ++ unsigned int bulk_out_enabled : 1; ++ unsigned int intr_in_enabled : 1; ++ unsigned int phase_error : 1; ++ unsigned int short_packet_received : 1; ++ unsigned int bad_lun_okay : 1; ++ ++ unsigned long atomic_bitflags; ++#define REGISTERED 0 ++#define IGNORE_BULK_OUT 1 ++#define SUSPENDED 2 ++ ++ struct usb_ep *bulk_in; ++ struct usb_ep *bulk_out; ++ struct usb_ep *intr_in; ++ ++ struct fsg_buffhd *next_buffhd_to_fill; ++ struct fsg_buffhd *next_buffhd_to_drain; ++ ++ int thread_wakeup_needed; ++ struct completion thread_notifier; ++ struct task_struct *thread_task; ++ ++ int cmnd_size; ++ u8 cmnd[MAX_COMMAND_SIZE]; ++ enum data_direction data_dir; ++ u32 data_size; ++ u32 data_size_from_cmnd; ++ u32 tag; ++ unsigned int lun; ++ u32 residue; ++ u32 usb_amount_left; ++ ++ /* The CB protocol offers no way for a host to know when a command ++ * has completed. As a result the next command may arrive early, ++ * and we will still have to handle it. For that reason we need ++ * a buffer to store new commands when using CB (or CBI, which ++ * does not oblige a host to wait for command completion either). */ ++ int cbbuf_cmnd_size; ++ u8 cbbuf_cmnd[MAX_COMMAND_SIZE]; ++ ++ unsigned int nluns; ++ struct fsg_lun *luns; ++ struct fsg_lun *curlun; ++ /* Must be the last entry */ ++ struct fsg_buffhd buffhds[]; ++}; ++ ++typedef void (*fsg_routine_t)(struct fsg_dev *); ++ ++static int exception_in_progress(struct fsg_dev *fsg) ++{ ++ return (fsg->state > FSG_STATE_IDLE); ++} ++ ++/* Make bulk-out requests be divisible by the maxpacket size */ ++static void set_bulk_out_req_length(struct fsg_dev *fsg, ++ struct fsg_buffhd *bh, unsigned int length) ++{ ++ unsigned int rem; ++ ++ bh->bulk_out_intended_length = length; ++ rem = length % fsg->bulk_out_maxpacket; ++ if (rem > 0) ++ length += fsg->bulk_out_maxpacket - rem; ++ bh->outreq->length = length; ++} ++ ++static struct fsg_dev *the_fsg; ++static struct usb_gadget_driver fsg_driver; ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++static int fsg_set_halt(struct fsg_dev *fsg, struct usb_ep *ep) ++{ ++ const char *name; ++ ++ if (ep == fsg->bulk_in) ++ name = "bulk-in"; ++ else if (ep == fsg->bulk_out) ++ name = "bulk-out"; ++ else ++ name = ep->name; ++ DBG(fsg, "%s set halt\n", name); ++ return usb_ep_set_halt(ep); ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* ++ * DESCRIPTORS ... most are static, but strings and (full) configuration ++ * descriptors are built on demand. Also the (static) config and interface ++ * descriptors are adjusted during fsg_bind(). ++ */ ++ ++/* There is only one configuration. */ ++#define CONFIG_VALUE 1 ++ ++static struct usb_device_descriptor ++device_desc = { ++ .bLength = sizeof device_desc, ++ .bDescriptorType = USB_DT_DEVICE, ++ ++ .bcdUSB = cpu_to_le16(0x0200), ++ .bDeviceClass = USB_CLASS_PER_INTERFACE, ++ ++ /* The next three values can be overridden by module parameters */ ++ .idVendor = cpu_to_le16(FSG_VENDOR_ID), ++ .idProduct = cpu_to_le16(FSG_PRODUCT_ID), ++ .bcdDevice = cpu_to_le16(0xffff), ++ ++ .iManufacturer = FSG_STRING_MANUFACTURER, ++ .iProduct = FSG_STRING_PRODUCT, ++ .iSerialNumber = FSG_STRING_SERIAL, ++ .bNumConfigurations = 1, ++}; ++ ++static struct usb_config_descriptor ++config_desc = { ++ .bLength = sizeof config_desc, ++ .bDescriptorType = USB_DT_CONFIG, ++ ++ /* wTotalLength computed by usb_gadget_config_buf() */ ++ .bNumInterfaces = 1, ++ .bConfigurationValue = CONFIG_VALUE, ++ .iConfiguration = FSG_STRING_CONFIG, ++ .bmAttributes = USB_CONFIG_ATT_ONE | USB_CONFIG_ATT_SELFPOWER, ++ .bMaxPower = CONFIG_USB_GADGET_VBUS_DRAW / 2, ++}; ++ ++ ++static struct usb_qualifier_descriptor ++dev_qualifier = { ++ .bLength = sizeof dev_qualifier, ++ .bDescriptorType = USB_DT_DEVICE_QUALIFIER, ++ ++ .bcdUSB = cpu_to_le16(0x0200), ++ .bDeviceClass = USB_CLASS_PER_INTERFACE, ++ ++ .bNumConfigurations = 1, ++}; ++ ++static int populate_bos(struct fsg_dev *fsg, u8 *buf) ++{ ++ memcpy(buf, &fsg_bos_desc, USB_DT_BOS_SIZE); ++ buf += USB_DT_BOS_SIZE; ++ ++ memcpy(buf, &fsg_ext_cap_desc, USB_DT_USB_EXT_CAP_SIZE); ++ buf += USB_DT_USB_EXT_CAP_SIZE; ++ ++ memcpy(buf, &fsg_ss_cap_desc, USB_DT_USB_SS_CAP_SIZE); ++ ++ return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE ++ + USB_DT_USB_EXT_CAP_SIZE; ++} ++ ++/* ++ * Config descriptors must agree with the code that sets configurations ++ * and with code managing interfaces and their altsettings. They must ++ * also handle different speeds and other-speed requests. ++ */ ++static int populate_config_buf(struct usb_gadget *gadget, ++ u8 *buf, u8 type, unsigned index) ++{ ++ enum usb_device_speed speed = gadget->speed; ++ int len; ++ const struct usb_descriptor_header **function; ++ ++ if (index > 0) ++ return -EINVAL; ++ ++ if (gadget_is_dualspeed(gadget) && type == USB_DT_OTHER_SPEED_CONFIG) ++ speed = (USB_SPEED_FULL + USB_SPEED_HIGH) - speed; ++ function = gadget_is_dualspeed(gadget) && speed == USB_SPEED_HIGH ++ ? (const struct usb_descriptor_header **)fsg_hs_function ++ : (const struct usb_descriptor_header **)fsg_fs_function; ++ ++ /* for now, don't advertise srp-only devices */ ++ if (!gadget_is_otg(gadget)) ++ function++; ++ ++ len = usb_gadget_config_buf(&config_desc, buf, EP0_BUFSIZE, function); ++ ((struct usb_config_descriptor *) buf)->bDescriptorType = type; ++ return len; ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* These routines may be called in process context or in_irq */ ++ ++/* Caller must hold fsg->lock */ ++static void wakeup_thread(struct fsg_dev *fsg) ++{ ++ /* Tell the main thread that something has happened */ ++ fsg->thread_wakeup_needed = 1; ++ if (fsg->thread_task) ++ wake_up_process(fsg->thread_task); ++} ++ ++ ++static void raise_exception(struct fsg_dev *fsg, enum fsg_state new_state) ++{ ++ unsigned long flags; ++ ++ /* Do nothing if a higher-priority exception is already in progress. ++ * If a lower-or-equal priority exception is in progress, preempt it ++ * and notify the main thread by sending it a signal. */ ++ spin_lock_irqsave(&fsg->lock, flags); ++ if (fsg->state <= new_state) { ++ fsg->exception_req_tag = fsg->ep0_req_tag; ++ fsg->state = new_state; ++ if (fsg->thread_task) ++ send_sig_info(SIGUSR1, SEND_SIG_FORCED, ++ fsg->thread_task); ++ } ++ spin_unlock_irqrestore(&fsg->lock, flags); ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* The disconnect callback and ep0 routines. These always run in_irq, ++ * except that ep0_queue() is called in the main thread to acknowledge ++ * completion of various requests: set config, set interface, and ++ * Bulk-only device reset. */ ++ ++static void fsg_disconnect(struct usb_gadget *gadget) ++{ ++ struct fsg_dev *fsg = get_gadget_data(gadget); ++ ++ DBG(fsg, "disconnect or port reset\n"); ++ raise_exception(fsg, FSG_STATE_DISCONNECT); ++} ++ ++ ++static int ep0_queue(struct fsg_dev *fsg) ++{ ++ int rc; ++ ++ rc = usb_ep_queue(fsg->ep0, fsg->ep0req, GFP_ATOMIC); ++ if (rc != 0 && rc != -ESHUTDOWN) { ++ ++ /* We can't do much more than wait for a reset */ ++ WARNING(fsg, "error in submission: %s --> %d\n", ++ fsg->ep0->name, rc); ++ } ++ return rc; ++} ++ ++static void ep0_complete(struct usb_ep *ep, struct usb_request *req) ++{ ++ struct fsg_dev *fsg = ep->driver_data; ++ ++ if (req->actual > 0) ++ dump_msg(fsg, fsg->ep0req_name, req->buf, req->actual); ++ if (req->status || req->actual != req->length) ++ DBG(fsg, "%s --> %d, %u/%u\n", __func__, ++ req->status, req->actual, req->length); ++ if (req->status == -ECONNRESET) // Request was cancelled ++ usb_ep_fifo_flush(ep); ++ ++ if (req->status == 0 && req->context) ++ ((fsg_routine_t) (req->context))(fsg); ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* Bulk and interrupt endpoint completion handlers. ++ * These always run in_irq. */ ++ ++static void bulk_in_complete(struct usb_ep *ep, struct usb_request *req) ++{ ++ struct fsg_dev *fsg = ep->driver_data; ++ struct fsg_buffhd *bh = req->context; ++ ++ if (req->status || req->actual != req->length) ++ DBG(fsg, "%s --> %d, %u/%u\n", __func__, ++ req->status, req->actual, req->length); ++ if (req->status == -ECONNRESET) // Request was cancelled ++ usb_ep_fifo_flush(ep); ++ ++ /* Hold the lock while we update the request and buffer states */ ++ smp_wmb(); ++ spin_lock(&fsg->lock); ++ bh->inreq_busy = 0; ++ bh->state = BUF_STATE_EMPTY; ++ wakeup_thread(fsg); ++ spin_unlock(&fsg->lock); ++} ++ ++static void bulk_out_complete(struct usb_ep *ep, struct usb_request *req) ++{ ++ struct fsg_dev *fsg = ep->driver_data; ++ struct fsg_buffhd *bh = req->context; ++ ++ dump_msg(fsg, "bulk-out", req->buf, req->actual); ++ if (req->status || req->actual != bh->bulk_out_intended_length) ++ DBG(fsg, "%s --> %d, %u/%u\n", __func__, ++ req->status, req->actual, ++ bh->bulk_out_intended_length); ++ if (req->status == -ECONNRESET) // Request was cancelled ++ usb_ep_fifo_flush(ep); ++ ++ /* Hold the lock while we update the request and buffer states */ ++ smp_wmb(); ++ spin_lock(&fsg->lock); ++ bh->outreq_busy = 0; ++ bh->state = BUF_STATE_FULL; ++ wakeup_thread(fsg); ++ spin_unlock(&fsg->lock); ++} ++ ++ ++#ifdef CONFIG_USB_FILE_STORAGE_TEST ++static void intr_in_complete(struct usb_ep *ep, struct usb_request *req) ++{ ++ struct fsg_dev *fsg = ep->driver_data; ++ struct fsg_buffhd *bh = req->context; ++ ++ if (req->status || req->actual != req->length) ++ DBG(fsg, "%s --> %d, %u/%u\n", __func__, ++ req->status, req->actual, req->length); ++ if (req->status == -ECONNRESET) // Request was cancelled ++ usb_ep_fifo_flush(ep); ++ ++ /* Hold the lock while we update the request and buffer states */ ++ smp_wmb(); ++ spin_lock(&fsg->lock); ++ fsg->intreq_busy = 0; ++ bh->state = BUF_STATE_EMPTY; ++ wakeup_thread(fsg); ++ spin_unlock(&fsg->lock); ++} ++ ++#else ++static void intr_in_complete(struct usb_ep *ep, struct usb_request *req) ++{} ++#endif /* CONFIG_USB_FILE_STORAGE_TEST */ ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* Ep0 class-specific handlers. These always run in_irq. */ ++ ++#ifdef CONFIG_USB_FILE_STORAGE_TEST ++static void received_cbi_adsc(struct fsg_dev *fsg, struct fsg_buffhd *bh) ++{ ++ struct usb_request *req = fsg->ep0req; ++ static u8 cbi_reset_cmnd[6] = { ++ SEND_DIAGNOSTIC, 4, 0xff, 0xff, 0xff, 0xff}; ++ ++ /* Error in command transfer? */ ++ if (req->status || req->length != req->actual || ++ req->actual < 6 || req->actual > MAX_COMMAND_SIZE) { ++ ++ /* Not all controllers allow a protocol stall after ++ * receiving control-out data, but we'll try anyway. */ ++ fsg_set_halt(fsg, fsg->ep0); ++ return; // Wait for reset ++ } ++ ++ /* Is it the special reset command? */ ++ if (req->actual >= sizeof cbi_reset_cmnd && ++ memcmp(req->buf, cbi_reset_cmnd, ++ sizeof cbi_reset_cmnd) == 0) { ++ ++ /* Raise an exception to stop the current operation ++ * and reinitialize our state. */ ++ DBG(fsg, "cbi reset request\n"); ++ raise_exception(fsg, FSG_STATE_RESET); ++ return; ++ } ++ ++ VDBG(fsg, "CB[I] accept device-specific command\n"); ++ spin_lock(&fsg->lock); ++ ++ /* Save the command for later */ ++ if (fsg->cbbuf_cmnd_size) ++ WARNING(fsg, "CB[I] overwriting previous command\n"); ++ fsg->cbbuf_cmnd_size = req->actual; ++ memcpy(fsg->cbbuf_cmnd, req->buf, fsg->cbbuf_cmnd_size); ++ ++ wakeup_thread(fsg); ++ spin_unlock(&fsg->lock); ++} ++ ++#else ++static void received_cbi_adsc(struct fsg_dev *fsg, struct fsg_buffhd *bh) ++{} ++#endif /* CONFIG_USB_FILE_STORAGE_TEST */ ++ ++ ++static int class_setup_req(struct fsg_dev *fsg, ++ const struct usb_ctrlrequest *ctrl) ++{ ++ struct usb_request *req = fsg->ep0req; ++ int value = -EOPNOTSUPP; ++ u16 w_index = le16_to_cpu(ctrl->wIndex); ++ u16 w_value = le16_to_cpu(ctrl->wValue); ++ u16 w_length = le16_to_cpu(ctrl->wLength); ++ ++ if (!fsg->config) ++ return value; ++ ++ /* Handle Bulk-only class-specific requests */ ++ if (transport_is_bbb()) { ++ switch (ctrl->bRequest) { ++ ++ case US_BULK_RESET_REQUEST: ++ if (ctrl->bRequestType != (USB_DIR_OUT | ++ USB_TYPE_CLASS | USB_RECIP_INTERFACE)) ++ break; ++ if (w_index != 0 || w_value != 0 || w_length != 0) { ++ value = -EDOM; ++ break; ++ } ++ ++ /* Raise an exception to stop the current operation ++ * and reinitialize our state. */ ++ DBG(fsg, "bulk reset request\n"); ++ raise_exception(fsg, FSG_STATE_RESET); ++ value = DELAYED_STATUS; ++ break; ++ ++ case US_BULK_GET_MAX_LUN: ++ if (ctrl->bRequestType != (USB_DIR_IN | ++ USB_TYPE_CLASS | USB_RECIP_INTERFACE)) ++ break; ++ if (w_index != 0 || w_value != 0 || w_length != 1) { ++ value = -EDOM; ++ break; ++ } ++ VDBG(fsg, "get max LUN\n"); ++ *(u8 *) req->buf = fsg->nluns - 1; ++ value = 1; ++ break; ++ } ++ } ++ ++ /* Handle CBI class-specific requests */ ++ else { ++ switch (ctrl->bRequest) { ++ ++ case USB_CBI_ADSC_REQUEST: ++ if (ctrl->bRequestType != (USB_DIR_OUT | ++ USB_TYPE_CLASS | USB_RECIP_INTERFACE)) ++ break; ++ if (w_index != 0 || w_value != 0) { ++ value = -EDOM; ++ break; ++ } ++ if (w_length > MAX_COMMAND_SIZE) { ++ value = -EOVERFLOW; ++ break; ++ } ++ value = w_length; ++ fsg->ep0req->context = received_cbi_adsc; ++ break; ++ } ++ } ++ ++ if (value == -EOPNOTSUPP) ++ VDBG(fsg, ++ "unknown class-specific control req " ++ "%02x.%02x v%04x i%04x l%u\n", ++ ctrl->bRequestType, ctrl->bRequest, ++ le16_to_cpu(ctrl->wValue), w_index, w_length); ++ return value; ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* Ep0 standard request handlers. These always run in_irq. */ ++ ++static int standard_setup_req(struct fsg_dev *fsg, ++ const struct usb_ctrlrequest *ctrl) ++{ ++ struct usb_request *req = fsg->ep0req; ++ int value = -EOPNOTSUPP; ++ u16 w_index = le16_to_cpu(ctrl->wIndex); ++ u16 w_value = le16_to_cpu(ctrl->wValue); ++ ++ /* Usually this just stores reply data in the pre-allocated ep0 buffer, ++ * but config change events will also reconfigure hardware. */ ++ switch (ctrl->bRequest) { ++ ++ case USB_REQ_GET_DESCRIPTOR: ++ if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD | ++ USB_RECIP_DEVICE)) ++ break; ++ switch (w_value >> 8) { ++ ++ case USB_DT_DEVICE: ++ VDBG(fsg, "get device descriptor\n"); ++ device_desc.bMaxPacketSize0 = fsg->ep0->maxpacket; ++ value = sizeof device_desc; ++ memcpy(req->buf, &device_desc, value); ++ break; ++ case USB_DT_DEVICE_QUALIFIER: ++ VDBG(fsg, "get device qualifier\n"); ++ if (!gadget_is_dualspeed(fsg->gadget) || ++ fsg->gadget->speed == USB_SPEED_SUPER) ++ break; ++ /* ++ * Assume ep0 uses the same maxpacket value for both ++ * speeds ++ */ ++ dev_qualifier.bMaxPacketSize0 = fsg->ep0->maxpacket; ++ value = sizeof dev_qualifier; ++ memcpy(req->buf, &dev_qualifier, value); ++ break; ++ ++ case USB_DT_OTHER_SPEED_CONFIG: ++ VDBG(fsg, "get other-speed config descriptor\n"); ++ if (!gadget_is_dualspeed(fsg->gadget) || ++ fsg->gadget->speed == USB_SPEED_SUPER) ++ break; ++ goto get_config; ++ case USB_DT_CONFIG: ++ VDBG(fsg, "get configuration descriptor\n"); ++get_config: ++ value = populate_config_buf(fsg->gadget, ++ req->buf, ++ w_value >> 8, ++ w_value & 0xff); ++ break; ++ ++ case USB_DT_STRING: ++ VDBG(fsg, "get string descriptor\n"); ++ ++ /* wIndex == language code */ ++ value = usb_gadget_get_string(&fsg_stringtab, ++ w_value & 0xff, req->buf); ++ break; ++ ++ case USB_DT_BOS: ++ VDBG(fsg, "get bos descriptor\n"); ++ ++ if (gadget_is_superspeed(fsg->gadget)) ++ value = populate_bos(fsg, req->buf); ++ break; ++ } ++ ++ break; ++ ++ /* One config, two speeds */ ++ case USB_REQ_SET_CONFIGURATION: ++ if (ctrl->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD | ++ USB_RECIP_DEVICE)) ++ break; ++ VDBG(fsg, "set configuration\n"); ++ if (w_value == CONFIG_VALUE || w_value == 0) { ++ fsg->new_config = w_value; ++ ++ /* Raise an exception to wipe out previous transaction ++ * state (queued bufs, etc) and set the new config. */ ++ raise_exception(fsg, FSG_STATE_CONFIG_CHANGE); ++ value = DELAYED_STATUS; ++ } ++ break; ++ case USB_REQ_GET_CONFIGURATION: ++ if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD | ++ USB_RECIP_DEVICE)) ++ break; ++ VDBG(fsg, "get configuration\n"); ++ *(u8 *) req->buf = fsg->config; ++ value = 1; ++ break; ++ ++ case USB_REQ_SET_INTERFACE: ++ if (ctrl->bRequestType != (USB_DIR_OUT| USB_TYPE_STANDARD | ++ USB_RECIP_INTERFACE)) ++ break; ++ if (fsg->config && w_index == 0) { ++ ++ /* Raise an exception to wipe out previous transaction ++ * state (queued bufs, etc) and install the new ++ * interface altsetting. */ ++ raise_exception(fsg, FSG_STATE_INTERFACE_CHANGE); ++ value = DELAYED_STATUS; ++ } ++ break; ++ case USB_REQ_GET_INTERFACE: ++ if (ctrl->bRequestType != (USB_DIR_IN | USB_TYPE_STANDARD | ++ USB_RECIP_INTERFACE)) ++ break; ++ if (!fsg->config) ++ break; ++ if (w_index != 0) { ++ value = -EDOM; ++ break; ++ } ++ VDBG(fsg, "get interface\n"); ++ *(u8 *) req->buf = 0; ++ value = 1; ++ break; ++ ++ default: ++ VDBG(fsg, ++ "unknown control req %02x.%02x v%04x i%04x l%u\n", ++ ctrl->bRequestType, ctrl->bRequest, ++ w_value, w_index, le16_to_cpu(ctrl->wLength)); ++ } ++ ++ return value; ++} ++ ++ ++static int fsg_setup(struct usb_gadget *gadget, ++ const struct usb_ctrlrequest *ctrl) ++{ ++ struct fsg_dev *fsg = get_gadget_data(gadget); ++ int rc; ++ int w_length = le16_to_cpu(ctrl->wLength); ++ ++ ++fsg->ep0_req_tag; // Record arrival of a new request ++ fsg->ep0req->context = NULL; ++ fsg->ep0req->length = 0; ++ dump_msg(fsg, "ep0-setup", (u8 *) ctrl, sizeof(*ctrl)); ++ ++ if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_CLASS) ++ rc = class_setup_req(fsg, ctrl); ++ else ++ rc = standard_setup_req(fsg, ctrl); ++ ++ /* Respond with data/status or defer until later? */ ++ if (rc >= 0 && rc != DELAYED_STATUS) { ++ rc = min(rc, w_length); ++ fsg->ep0req->length = rc; ++ fsg->ep0req->zero = rc < w_length; ++ fsg->ep0req_name = (ctrl->bRequestType & USB_DIR_IN ? ++ "ep0-in" : "ep0-out"); ++ rc = ep0_queue(fsg); ++ } ++ ++ /* Device either stalls (rc < 0) or reports success */ ++ return rc; ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* All the following routines run in process context */ ++ ++ ++/* Use this for bulk or interrupt transfers, not ep0 */ ++static void start_transfer(struct fsg_dev *fsg, struct usb_ep *ep, ++ struct usb_request *req, int *pbusy, ++ enum fsg_buffer_state *state) ++{ ++ int rc; ++ ++ if (ep == fsg->bulk_in) ++ dump_msg(fsg, "bulk-in", req->buf, req->length); ++ else if (ep == fsg->intr_in) ++ dump_msg(fsg, "intr-in", req->buf, req->length); ++ ++ spin_lock_irq(&fsg->lock); ++ *pbusy = 1; ++ *state = BUF_STATE_BUSY; ++ spin_unlock_irq(&fsg->lock); ++ rc = usb_ep_queue(ep, req, GFP_KERNEL); ++ if (rc != 0) { ++ *pbusy = 0; ++ *state = BUF_STATE_EMPTY; ++ ++ /* We can't do much more than wait for a reset */ ++ ++ /* Note: currently the net2280 driver fails zero-length ++ * submissions if DMA is enabled. */ ++ if (rc != -ESHUTDOWN && !(rc == -EOPNOTSUPP && ++ req->length == 0)) ++ WARNING(fsg, "error in submission: %s --> %d\n", ++ ep->name, rc); ++ } ++} ++ ++ ++static int sleep_thread(struct fsg_dev *fsg) ++{ ++ int rc = 0; ++ ++ /* Wait until a signal arrives or we are woken up */ ++ for (;;) { ++ try_to_freeze(); ++ set_current_state(TASK_INTERRUPTIBLE); ++ if (signal_pending(current)) { ++ rc = -EINTR; ++ break; ++ } ++ if (fsg->thread_wakeup_needed) ++ break; ++ schedule(); ++ } ++ __set_current_state(TASK_RUNNING); ++ fsg->thread_wakeup_needed = 0; ++ return rc; ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++static int do_read(struct fsg_dev *fsg) ++{ ++ struct fsg_lun *curlun = fsg->curlun; ++ u32 lba; ++ struct fsg_buffhd *bh; ++ int rc; ++ u32 amount_left; ++ loff_t file_offset, file_offset_tmp; ++ unsigned int amount; ++ ssize_t nread; ++ ++ /* Get the starting Logical Block Address and check that it's ++ * not too big */ ++ if (fsg->cmnd[0] == READ_6) ++ lba = get_unaligned_be24(&fsg->cmnd[1]); ++ else { ++ lba = get_unaligned_be32(&fsg->cmnd[2]); ++ ++ /* We allow DPO (Disable Page Out = don't save data in the ++ * cache) and FUA (Force Unit Access = don't read from the ++ * cache), but we don't implement them. */ ++ if ((fsg->cmnd[1] & ~0x18) != 0) { ++ curlun->sense_data = SS_INVALID_FIELD_IN_CDB; ++ return -EINVAL; ++ } ++ } ++ if (lba >= curlun->num_sectors) { ++ curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; ++ return -EINVAL; ++ } ++ file_offset = ((loff_t) lba) << curlun->blkbits; ++ ++ /* Carry out the file reads */ ++ amount_left = fsg->data_size_from_cmnd; ++ if (unlikely(amount_left == 0)) ++ return -EIO; // No default reply ++ ++ for (;;) { ++ ++ /* Figure out how much we need to read: ++ * Try to read the remaining amount. ++ * But don't read more than the buffer size. ++ * And don't try to read past the end of the file. ++ */ ++ amount = min((unsigned int) amount_left, mod_data.buflen); ++ amount = min((loff_t) amount, ++ curlun->file_length - file_offset); ++ ++ /* Wait for the next buffer to become available */ ++ bh = fsg->next_buffhd_to_fill; ++ while (bh->state != BUF_STATE_EMPTY) { ++ rc = sleep_thread(fsg); ++ if (rc) ++ return rc; ++ } ++ ++ /* If we were asked to read past the end of file, ++ * end with an empty buffer. */ ++ if (amount == 0) { ++ curlun->sense_data = ++ SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; ++ curlun->sense_data_info = file_offset >> curlun->blkbits; ++ curlun->info_valid = 1; ++ bh->inreq->length = 0; ++ bh->state = BUF_STATE_FULL; ++ break; ++ } ++ ++ /* Perform the read */ ++ file_offset_tmp = file_offset; ++ nread = vfs_read(curlun->filp, ++ (char __user *) bh->buf, ++ amount, &file_offset_tmp); ++ VLDBG(curlun, "file read %u @ %llu -> %d\n", amount, ++ (unsigned long long) file_offset, ++ (int) nread); ++ if (signal_pending(current)) ++ return -EINTR; ++ ++ if (nread < 0) { ++ LDBG(curlun, "error in file read: %d\n", ++ (int) nread); ++ nread = 0; ++ } else if (nread < amount) { ++ LDBG(curlun, "partial file read: %d/%u\n", ++ (int) nread, amount); ++ nread = round_down(nread, curlun->blksize); ++ } ++ file_offset += nread; ++ amount_left -= nread; ++ fsg->residue -= nread; ++ ++ /* Except at the end of the transfer, nread will be ++ * equal to the buffer size, which is divisible by the ++ * bulk-in maxpacket size. ++ */ ++ bh->inreq->length = nread; ++ bh->state = BUF_STATE_FULL; ++ ++ /* If an error occurred, report it and its position */ ++ if (nread < amount) { ++ curlun->sense_data = SS_UNRECOVERED_READ_ERROR; ++ curlun->sense_data_info = file_offset >> curlun->blkbits; ++ curlun->info_valid = 1; ++ break; ++ } ++ ++ if (amount_left == 0) ++ break; // No more left to read ++ ++ /* Send this buffer and go read some more */ ++ bh->inreq->zero = 0; ++ start_transfer(fsg, fsg->bulk_in, bh->inreq, ++ &bh->inreq_busy, &bh->state); ++ fsg->next_buffhd_to_fill = bh->next; ++ } ++ ++ return -EIO; // No default reply ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++static int do_write(struct fsg_dev *fsg) ++{ ++ struct fsg_lun *curlun = fsg->curlun; ++ u32 lba; ++ struct fsg_buffhd *bh; ++ int get_some_more; ++ u32 amount_left_to_req, amount_left_to_write; ++ loff_t usb_offset, file_offset, file_offset_tmp; ++ unsigned int amount; ++ ssize_t nwritten; ++ int rc; ++ ++ if (curlun->ro) { ++ curlun->sense_data = SS_WRITE_PROTECTED; ++ return -EINVAL; ++ } ++ spin_lock(&curlun->filp->f_lock); ++ curlun->filp->f_flags &= ~O_SYNC; // Default is not to wait ++ spin_unlock(&curlun->filp->f_lock); ++ ++ /* Get the starting Logical Block Address and check that it's ++ * not too big */ ++ if (fsg->cmnd[0] == WRITE_6) ++ lba = get_unaligned_be24(&fsg->cmnd[1]); ++ else { ++ lba = get_unaligned_be32(&fsg->cmnd[2]); ++ ++ /* We allow DPO (Disable Page Out = don't save data in the ++ * cache) and FUA (Force Unit Access = write directly to the ++ * medium). We don't implement DPO; we implement FUA by ++ * performing synchronous output. */ ++ if ((fsg->cmnd[1] & ~0x18) != 0) { ++ curlun->sense_data = SS_INVALID_FIELD_IN_CDB; ++ return -EINVAL; ++ } ++ /* FUA */ ++ if (!curlun->nofua && (fsg->cmnd[1] & 0x08)) { ++ spin_lock(&curlun->filp->f_lock); ++ curlun->filp->f_flags |= O_DSYNC; ++ spin_unlock(&curlun->filp->f_lock); ++ } ++ } ++ if (lba >= curlun->num_sectors) { ++ curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; ++ return -EINVAL; ++ } ++ ++ /* Carry out the file writes */ ++ get_some_more = 1; ++ file_offset = usb_offset = ((loff_t) lba) << curlun->blkbits; ++ amount_left_to_req = amount_left_to_write = fsg->data_size_from_cmnd; ++ ++ while (amount_left_to_write > 0) { ++ ++ /* Queue a request for more data from the host */ ++ bh = fsg->next_buffhd_to_fill; ++ if (bh->state == BUF_STATE_EMPTY && get_some_more) { ++ ++ /* Figure out how much we want to get: ++ * Try to get the remaining amount, ++ * but not more than the buffer size. ++ */ ++ amount = min(amount_left_to_req, mod_data.buflen); ++ ++ /* Beyond the end of the backing file? */ ++ if (usb_offset >= curlun->file_length) { ++ get_some_more = 0; ++ curlun->sense_data = ++ SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; ++ curlun->sense_data_info = usb_offset >> curlun->blkbits; ++ curlun->info_valid = 1; ++ continue; ++ } ++ ++ /* Get the next buffer */ ++ usb_offset += amount; ++ fsg->usb_amount_left -= amount; ++ amount_left_to_req -= amount; ++ if (amount_left_to_req == 0) ++ get_some_more = 0; ++ ++ /* Except at the end of the transfer, amount will be ++ * equal to the buffer size, which is divisible by ++ * the bulk-out maxpacket size. ++ */ ++ set_bulk_out_req_length(fsg, bh, amount); ++ start_transfer(fsg, fsg->bulk_out, bh->outreq, ++ &bh->outreq_busy, &bh->state); ++ fsg->next_buffhd_to_fill = bh->next; ++ continue; ++ } ++ ++ /* Write the received data to the backing file */ ++ bh = fsg->next_buffhd_to_drain; ++ if (bh->state == BUF_STATE_EMPTY && !get_some_more) ++ break; // We stopped early ++ if (bh->state == BUF_STATE_FULL) { ++ smp_rmb(); ++ fsg->next_buffhd_to_drain = bh->next; ++ bh->state = BUF_STATE_EMPTY; ++ ++ /* Did something go wrong with the transfer? */ ++ if (bh->outreq->status != 0) { ++ curlun->sense_data = SS_COMMUNICATION_FAILURE; ++ curlun->sense_data_info = file_offset >> curlun->blkbits; ++ curlun->info_valid = 1; ++ break; ++ } ++ ++ amount = bh->outreq->actual; ++ if (curlun->file_length - file_offset < amount) { ++ LERROR(curlun, ++ "write %u @ %llu beyond end %llu\n", ++ amount, (unsigned long long) file_offset, ++ (unsigned long long) curlun->file_length); ++ amount = curlun->file_length - file_offset; ++ } ++ ++ /* Don't accept excess data. The spec doesn't say ++ * what to do in this case. We'll ignore the error. ++ */ ++ amount = min(amount, bh->bulk_out_intended_length); ++ ++ /* Don't write a partial block */ ++ amount = round_down(amount, curlun->blksize); ++ if (amount == 0) ++ goto empty_write; ++ ++ /* Perform the write */ ++ file_offset_tmp = file_offset; ++ nwritten = vfs_write(curlun->filp, ++ (char __user *) bh->buf, ++ amount, &file_offset_tmp); ++ VLDBG(curlun, "file write %u @ %llu -> %d\n", amount, ++ (unsigned long long) file_offset, ++ (int) nwritten); ++ if (signal_pending(current)) ++ return -EINTR; // Interrupted! ++ ++ if (nwritten < 0) { ++ LDBG(curlun, "error in file write: %d\n", ++ (int) nwritten); ++ nwritten = 0; ++ } else if (nwritten < amount) { ++ LDBG(curlun, "partial file write: %d/%u\n", ++ (int) nwritten, amount); ++ nwritten = round_down(nwritten, curlun->blksize); ++ } ++ file_offset += nwritten; ++ amount_left_to_write -= nwritten; ++ fsg->residue -= nwritten; ++ ++ /* If an error occurred, report it and its position */ ++ if (nwritten < amount) { ++ curlun->sense_data = SS_WRITE_ERROR; ++ curlun->sense_data_info = file_offset >> curlun->blkbits; ++ curlun->info_valid = 1; ++ break; ++ } ++ ++ empty_write: ++ /* Did the host decide to stop early? */ ++ if (bh->outreq->actual < bh->bulk_out_intended_length) { ++ fsg->short_packet_received = 1; ++ break; ++ } ++ continue; ++ } ++ ++ /* Wait for something to happen */ ++ rc = sleep_thread(fsg); ++ if (rc) ++ return rc; ++ } ++ ++ return -EIO; // No default reply ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++static int do_synchronize_cache(struct fsg_dev *fsg) ++{ ++ struct fsg_lun *curlun = fsg->curlun; ++ int rc; ++ ++ /* We ignore the requested LBA and write out all file's ++ * dirty data buffers. */ ++ rc = fsg_lun_fsync_sub(curlun); ++ if (rc) ++ curlun->sense_data = SS_WRITE_ERROR; ++ return 0; ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++static void invalidate_sub(struct fsg_lun *curlun) ++{ ++ struct file *filp = curlun->filp; ++ struct inode *inode = filp->f_path.dentry->d_inode; ++ unsigned long rc; ++ ++ rc = invalidate_mapping_pages(inode->i_mapping, 0, -1); ++ VLDBG(curlun, "invalidate_mapping_pages -> %ld\n", rc); ++} ++ ++static int do_verify(struct fsg_dev *fsg) ++{ ++ struct fsg_lun *curlun = fsg->curlun; ++ u32 lba; ++ u32 verification_length; ++ struct fsg_buffhd *bh = fsg->next_buffhd_to_fill; ++ loff_t file_offset, file_offset_tmp; ++ u32 amount_left; ++ unsigned int amount; ++ ssize_t nread; ++ ++ /* Get the starting Logical Block Address and check that it's ++ * not too big */ ++ lba = get_unaligned_be32(&fsg->cmnd[2]); ++ if (lba >= curlun->num_sectors) { ++ curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; ++ return -EINVAL; ++ } ++ ++ /* We allow DPO (Disable Page Out = don't save data in the ++ * cache) but we don't implement it. */ ++ if ((fsg->cmnd[1] & ~0x10) != 0) { ++ curlun->sense_data = SS_INVALID_FIELD_IN_CDB; ++ return -EINVAL; ++ } ++ ++ verification_length = get_unaligned_be16(&fsg->cmnd[7]); ++ if (unlikely(verification_length == 0)) ++ return -EIO; // No default reply ++ ++ /* Prepare to carry out the file verify */ ++ amount_left = verification_length << curlun->blkbits; ++ file_offset = ((loff_t) lba) << curlun->blkbits; ++ ++ /* Write out all the dirty buffers before invalidating them */ ++ fsg_lun_fsync_sub(curlun); ++ if (signal_pending(current)) ++ return -EINTR; ++ ++ invalidate_sub(curlun); ++ if (signal_pending(current)) ++ return -EINTR; ++ ++ /* Just try to read the requested blocks */ ++ while (amount_left > 0) { ++ ++ /* Figure out how much we need to read: ++ * Try to read the remaining amount, but not more than ++ * the buffer size. ++ * And don't try to read past the end of the file. ++ */ ++ amount = min((unsigned int) amount_left, mod_data.buflen); ++ amount = min((loff_t) amount, ++ curlun->file_length - file_offset); ++ if (amount == 0) { ++ curlun->sense_data = ++ SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; ++ curlun->sense_data_info = file_offset >> curlun->blkbits; ++ curlun->info_valid = 1; ++ break; ++ } ++ ++ /* Perform the read */ ++ file_offset_tmp = file_offset; ++ nread = vfs_read(curlun->filp, ++ (char __user *) bh->buf, ++ amount, &file_offset_tmp); ++ VLDBG(curlun, "file read %u @ %llu -> %d\n", amount, ++ (unsigned long long) file_offset, ++ (int) nread); ++ if (signal_pending(current)) ++ return -EINTR; ++ ++ if (nread < 0) { ++ LDBG(curlun, "error in file verify: %d\n", ++ (int) nread); ++ nread = 0; ++ } else if (nread < amount) { ++ LDBG(curlun, "partial file verify: %d/%u\n", ++ (int) nread, amount); ++ nread = round_down(nread, curlun->blksize); ++ } ++ if (nread == 0) { ++ curlun->sense_data = SS_UNRECOVERED_READ_ERROR; ++ curlun->sense_data_info = file_offset >> curlun->blkbits; ++ curlun->info_valid = 1; ++ break; ++ } ++ file_offset += nread; ++ amount_left -= nread; ++ } ++ return 0; ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++static int do_inquiry(struct fsg_dev *fsg, struct fsg_buffhd *bh) ++{ ++ u8 *buf = (u8 *) bh->buf; ++ ++ static char vendor_id[] = "Linux "; ++ static char product_disk_id[] = "File-Stor Gadget"; ++ static char product_cdrom_id[] = "File-CD Gadget "; ++ ++ if (!fsg->curlun) { // Unsupported LUNs are okay ++ fsg->bad_lun_okay = 1; ++ memset(buf, 0, 36); ++ buf[0] = 0x7f; // Unsupported, no device-type ++ buf[4] = 31; // Additional length ++ return 36; ++ } ++ ++ memset(buf, 0, 8); ++ buf[0] = (mod_data.cdrom ? TYPE_ROM : TYPE_DISK); ++ if (mod_data.removable) ++ buf[1] = 0x80; ++ buf[2] = 2; // ANSI SCSI level 2 ++ buf[3] = 2; // SCSI-2 INQUIRY data format ++ buf[4] = 31; // Additional length ++ // No special options ++ sprintf(buf + 8, "%-8s%-16s%04x", vendor_id, ++ (mod_data.cdrom ? product_cdrom_id : ++ product_disk_id), ++ mod_data.release); ++ return 36; ++} ++ ++ ++static int do_request_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh) ++{ ++ struct fsg_lun *curlun = fsg->curlun; ++ u8 *buf = (u8 *) bh->buf; ++ u32 sd, sdinfo; ++ int valid; ++ ++ /* ++ * From the SCSI-2 spec., section 7.9 (Unit attention condition): ++ * ++ * If a REQUEST SENSE command is received from an initiator ++ * with a pending unit attention condition (before the target ++ * generates the contingent allegiance condition), then the ++ * target shall either: ++ * a) report any pending sense data and preserve the unit ++ * attention condition on the logical unit, or, ++ * b) report the unit attention condition, may discard any ++ * pending sense data, and clear the unit attention ++ * condition on the logical unit for that initiator. ++ * ++ * FSG normally uses option a); enable this code to use option b). ++ */ ++#if 0 ++ if (curlun && curlun->unit_attention_data != SS_NO_SENSE) { ++ curlun->sense_data = curlun->unit_attention_data; ++ curlun->unit_attention_data = SS_NO_SENSE; ++ } ++#endif ++ ++ if (!curlun) { // Unsupported LUNs are okay ++ fsg->bad_lun_okay = 1; ++ sd = SS_LOGICAL_UNIT_NOT_SUPPORTED; ++ sdinfo = 0; ++ valid = 0; ++ } else { ++ sd = curlun->sense_data; ++ sdinfo = curlun->sense_data_info; ++ valid = curlun->info_valid << 7; ++ curlun->sense_data = SS_NO_SENSE; ++ curlun->sense_data_info = 0; ++ curlun->info_valid = 0; ++ } ++ ++ memset(buf, 0, 18); ++ buf[0] = valid | 0x70; // Valid, current error ++ buf[2] = SK(sd); ++ put_unaligned_be32(sdinfo, &buf[3]); /* Sense information */ ++ buf[7] = 18 - 8; // Additional sense length ++ buf[12] = ASC(sd); ++ buf[13] = ASCQ(sd); ++ return 18; ++} ++ ++ ++static int do_read_capacity(struct fsg_dev *fsg, struct fsg_buffhd *bh) ++{ ++ struct fsg_lun *curlun = fsg->curlun; ++ u32 lba = get_unaligned_be32(&fsg->cmnd[2]); ++ int pmi = fsg->cmnd[8]; ++ u8 *buf = (u8 *) bh->buf; ++ ++ /* Check the PMI and LBA fields */ ++ if (pmi > 1 || (pmi == 0 && lba != 0)) { ++ curlun->sense_data = SS_INVALID_FIELD_IN_CDB; ++ return -EINVAL; ++ } ++ ++ put_unaligned_be32(curlun->num_sectors - 1, &buf[0]); ++ /* Max logical block */ ++ put_unaligned_be32(curlun->blksize, &buf[4]); /* Block length */ ++ return 8; ++} ++ ++ ++static int do_read_header(struct fsg_dev *fsg, struct fsg_buffhd *bh) ++{ ++ struct fsg_lun *curlun = fsg->curlun; ++ int msf = fsg->cmnd[1] & 0x02; ++ u32 lba = get_unaligned_be32(&fsg->cmnd[2]); ++ u8 *buf = (u8 *) bh->buf; ++ ++ if ((fsg->cmnd[1] & ~0x02) != 0) { /* Mask away MSF */ ++ curlun->sense_data = SS_INVALID_FIELD_IN_CDB; ++ return -EINVAL; ++ } ++ if (lba >= curlun->num_sectors) { ++ curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; ++ return -EINVAL; ++ } ++ ++ memset(buf, 0, 8); ++ buf[0] = 0x01; /* 2048 bytes of user data, rest is EC */ ++ store_cdrom_address(&buf[4], msf, lba); ++ return 8; ++} ++ ++ ++static int do_read_toc(struct fsg_dev *fsg, struct fsg_buffhd *bh) ++{ ++ struct fsg_lun *curlun = fsg->curlun; ++ int msf = fsg->cmnd[1] & 0x02; ++ int start_track = fsg->cmnd[6]; ++ u8 *buf = (u8 *) bh->buf; ++ ++ if ((fsg->cmnd[1] & ~0x02) != 0 || /* Mask away MSF */ ++ start_track > 1) { ++ curlun->sense_data = SS_INVALID_FIELD_IN_CDB; ++ return -EINVAL; ++ } ++ ++ memset(buf, 0, 20); ++ buf[1] = (20-2); /* TOC data length */ ++ buf[2] = 1; /* First track number */ ++ buf[3] = 1; /* Last track number */ ++ buf[5] = 0x16; /* Data track, copying allowed */ ++ buf[6] = 0x01; /* Only track is number 1 */ ++ store_cdrom_address(&buf[8], msf, 0); ++ ++ buf[13] = 0x16; /* Lead-out track is data */ ++ buf[14] = 0xAA; /* Lead-out track number */ ++ store_cdrom_address(&buf[16], msf, curlun->num_sectors); ++ return 20; ++} ++ ++ ++static int do_mode_sense(struct fsg_dev *fsg, struct fsg_buffhd *bh) ++{ ++ struct fsg_lun *curlun = fsg->curlun; ++ int mscmnd = fsg->cmnd[0]; ++ u8 *buf = (u8 *) bh->buf; ++ u8 *buf0 = buf; ++ int pc, page_code; ++ int changeable_values, all_pages; ++ int valid_page = 0; ++ int len, limit; ++ ++ if ((fsg->cmnd[1] & ~0x08) != 0) { // Mask away DBD ++ curlun->sense_data = SS_INVALID_FIELD_IN_CDB; ++ return -EINVAL; ++ } ++ pc = fsg->cmnd[2] >> 6; ++ page_code = fsg->cmnd[2] & 0x3f; ++ if (pc == 3) { ++ curlun->sense_data = SS_SAVING_PARAMETERS_NOT_SUPPORTED; ++ return -EINVAL; ++ } ++ changeable_values = (pc == 1); ++ all_pages = (page_code == 0x3f); ++ ++ /* Write the mode parameter header. Fixed values are: default ++ * medium type, no cache control (DPOFUA), and no block descriptors. ++ * The only variable value is the WriteProtect bit. We will fill in ++ * the mode data length later. */ ++ memset(buf, 0, 8); ++ if (mscmnd == MODE_SENSE) { ++ buf[2] = (curlun->ro ? 0x80 : 0x00); // WP, DPOFUA ++ buf += 4; ++ limit = 255; ++ } else { // MODE_SENSE_10 ++ buf[3] = (curlun->ro ? 0x80 : 0x00); // WP, DPOFUA ++ buf += 8; ++ limit = 65535; // Should really be mod_data.buflen ++ } ++ ++ /* No block descriptors */ ++ ++ /* The mode pages, in numerical order. The only page we support ++ * is the Caching page. */ ++ if (page_code == 0x08 || all_pages) { ++ valid_page = 1; ++ buf[0] = 0x08; // Page code ++ buf[1] = 10; // Page length ++ memset(buf+2, 0, 10); // None of the fields are changeable ++ ++ if (!changeable_values) { ++ buf[2] = 0x04; // Write cache enable, ++ // Read cache not disabled ++ // No cache retention priorities ++ put_unaligned_be16(0xffff, &buf[4]); ++ /* Don't disable prefetch */ ++ /* Minimum prefetch = 0 */ ++ put_unaligned_be16(0xffff, &buf[8]); ++ /* Maximum prefetch */ ++ put_unaligned_be16(0xffff, &buf[10]); ++ /* Maximum prefetch ceiling */ ++ } ++ buf += 12; ++ } ++ ++ /* Check that a valid page was requested and the mode data length ++ * isn't too long. */ ++ len = buf - buf0; ++ if (!valid_page || len > limit) { ++ curlun->sense_data = SS_INVALID_FIELD_IN_CDB; ++ return -EINVAL; ++ } ++ ++ /* Store the mode data length */ ++ if (mscmnd == MODE_SENSE) ++ buf0[0] = len - 1; ++ else ++ put_unaligned_be16(len - 2, buf0); ++ return len; ++} ++ ++ ++static int do_start_stop(struct fsg_dev *fsg) ++{ ++ struct fsg_lun *curlun = fsg->curlun; ++ int loej, start; ++ ++ if (!mod_data.removable) { ++ curlun->sense_data = SS_INVALID_COMMAND; ++ return -EINVAL; ++ } ++ ++ // int immed = fsg->cmnd[1] & 0x01; ++ loej = fsg->cmnd[4] & 0x02; ++ start = fsg->cmnd[4] & 0x01; ++ ++#ifdef CONFIG_USB_FILE_STORAGE_TEST ++ if ((fsg->cmnd[1] & ~0x01) != 0 || // Mask away Immed ++ (fsg->cmnd[4] & ~0x03) != 0) { // Mask LoEj, Start ++ curlun->sense_data = SS_INVALID_FIELD_IN_CDB; ++ return -EINVAL; ++ } ++ ++ if (!start) { ++ ++ /* Are we allowed to unload the media? */ ++ if (curlun->prevent_medium_removal) { ++ LDBG(curlun, "unload attempt prevented\n"); ++ curlun->sense_data = SS_MEDIUM_REMOVAL_PREVENTED; ++ return -EINVAL; ++ } ++ if (loej) { // Simulate an unload/eject ++ up_read(&fsg->filesem); ++ down_write(&fsg->filesem); ++ fsg_lun_close(curlun); ++ up_write(&fsg->filesem); ++ down_read(&fsg->filesem); ++ } ++ } else { ++ ++ /* Our emulation doesn't support mounting; the medium is ++ * available for use as soon as it is loaded. */ ++ if (!fsg_lun_is_open(curlun)) { ++ curlun->sense_data = SS_MEDIUM_NOT_PRESENT; ++ return -EINVAL; ++ } ++ } ++#endif ++ return 0; ++} ++ ++ ++static int do_prevent_allow(struct fsg_dev *fsg) ++{ ++ struct fsg_lun *curlun = fsg->curlun; ++ int prevent; ++ ++ if (!mod_data.removable) { ++ curlun->sense_data = SS_INVALID_COMMAND; ++ return -EINVAL; ++ } ++ ++ prevent = fsg->cmnd[4] & 0x01; ++ if ((fsg->cmnd[4] & ~0x01) != 0) { // Mask away Prevent ++ curlun->sense_data = SS_INVALID_FIELD_IN_CDB; ++ return -EINVAL; ++ } ++ ++ if (curlun->prevent_medium_removal && !prevent) ++ fsg_lun_fsync_sub(curlun); ++ curlun->prevent_medium_removal = prevent; ++ return 0; ++} ++ ++ ++static int do_read_format_capacities(struct fsg_dev *fsg, ++ struct fsg_buffhd *bh) ++{ ++ struct fsg_lun *curlun = fsg->curlun; ++ u8 *buf = (u8 *) bh->buf; ++ ++ buf[0] = buf[1] = buf[2] = 0; ++ buf[3] = 8; // Only the Current/Maximum Capacity Descriptor ++ buf += 4; ++ ++ put_unaligned_be32(curlun->num_sectors, &buf[0]); ++ /* Number of blocks */ ++ put_unaligned_be32(curlun->blksize, &buf[4]); /* Block length */ ++ buf[4] = 0x02; /* Current capacity */ ++ return 12; ++} ++ ++ ++static int do_mode_select(struct fsg_dev *fsg, struct fsg_buffhd *bh) ++{ ++ struct fsg_lun *curlun = fsg->curlun; ++ ++ /* We don't support MODE SELECT */ ++ curlun->sense_data = SS_INVALID_COMMAND; ++ return -EINVAL; ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++static int halt_bulk_in_endpoint(struct fsg_dev *fsg) ++{ ++ int rc; ++ ++ rc = fsg_set_halt(fsg, fsg->bulk_in); ++ if (rc == -EAGAIN) ++ VDBG(fsg, "delayed bulk-in endpoint halt\n"); ++ while (rc != 0) { ++ if (rc != -EAGAIN) { ++ WARNING(fsg, "usb_ep_set_halt -> %d\n", rc); ++ rc = 0; ++ break; ++ } ++ ++ /* Wait for a short time and then try again */ ++ if (msleep_interruptible(100) != 0) ++ return -EINTR; ++ rc = usb_ep_set_halt(fsg->bulk_in); ++ } ++ return rc; ++} ++ ++static int wedge_bulk_in_endpoint(struct fsg_dev *fsg) ++{ ++ int rc; ++ ++ DBG(fsg, "bulk-in set wedge\n"); ++ rc = usb_ep_set_wedge(fsg->bulk_in); ++ if (rc == -EAGAIN) ++ VDBG(fsg, "delayed bulk-in endpoint wedge\n"); ++ while (rc != 0) { ++ if (rc != -EAGAIN) { ++ WARNING(fsg, "usb_ep_set_wedge -> %d\n", rc); ++ rc = 0; ++ break; ++ } ++ ++ /* Wait for a short time and then try again */ ++ if (msleep_interruptible(100) != 0) ++ return -EINTR; ++ rc = usb_ep_set_wedge(fsg->bulk_in); ++ } ++ return rc; ++} ++ ++static int throw_away_data(struct fsg_dev *fsg) ++{ ++ struct fsg_buffhd *bh; ++ u32 amount; ++ int rc; ++ ++ while ((bh = fsg->next_buffhd_to_drain)->state != BUF_STATE_EMPTY || ++ fsg->usb_amount_left > 0) { ++ ++ /* Throw away the data in a filled buffer */ ++ if (bh->state == BUF_STATE_FULL) { ++ smp_rmb(); ++ bh->state = BUF_STATE_EMPTY; ++ fsg->next_buffhd_to_drain = bh->next; ++ ++ /* A short packet or an error ends everything */ ++ if (bh->outreq->actual < bh->bulk_out_intended_length || ++ bh->outreq->status != 0) { ++ raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT); ++ return -EINTR; ++ } ++ continue; ++ } ++ ++ /* Try to submit another request if we need one */ ++ bh = fsg->next_buffhd_to_fill; ++ if (bh->state == BUF_STATE_EMPTY && fsg->usb_amount_left > 0) { ++ amount = min(fsg->usb_amount_left, ++ (u32) mod_data.buflen); ++ ++ /* Except at the end of the transfer, amount will be ++ * equal to the buffer size, which is divisible by ++ * the bulk-out maxpacket size. ++ */ ++ set_bulk_out_req_length(fsg, bh, amount); ++ start_transfer(fsg, fsg->bulk_out, bh->outreq, ++ &bh->outreq_busy, &bh->state); ++ fsg->next_buffhd_to_fill = bh->next; ++ fsg->usb_amount_left -= amount; ++ continue; ++ } ++ ++ /* Otherwise wait for something to happen */ ++ rc = sleep_thread(fsg); ++ if (rc) ++ return rc; ++ } ++ return 0; ++} ++ ++ ++static int finish_reply(struct fsg_dev *fsg) ++{ ++ struct fsg_buffhd *bh = fsg->next_buffhd_to_fill; ++ int rc = 0; ++ ++ switch (fsg->data_dir) { ++ case DATA_DIR_NONE: ++ break; // Nothing to send ++ ++ /* If we don't know whether the host wants to read or write, ++ * this must be CB or CBI with an unknown command. We mustn't ++ * try to send or receive any data. So stall both bulk pipes ++ * if we can and wait for a reset. */ ++ case DATA_DIR_UNKNOWN: ++ if (mod_data.can_stall) { ++ fsg_set_halt(fsg, fsg->bulk_out); ++ rc = halt_bulk_in_endpoint(fsg); ++ } ++ break; ++ ++ /* All but the last buffer of data must have already been sent */ ++ case DATA_DIR_TO_HOST: ++ if (fsg->data_size == 0) ++ ; // Nothing to send ++ ++ /* If there's no residue, simply send the last buffer */ ++ else if (fsg->residue == 0) { ++ bh->inreq->zero = 0; ++ start_transfer(fsg, fsg->bulk_in, bh->inreq, ++ &bh->inreq_busy, &bh->state); ++ fsg->next_buffhd_to_fill = bh->next; ++ } ++ ++ /* There is a residue. For CB and CBI, simply mark the end ++ * of the data with a short packet. However, if we are ++ * allowed to stall, there was no data at all (residue == ++ * data_size), and the command failed (invalid LUN or ++ * sense data is set), then halt the bulk-in endpoint ++ * instead. */ ++ else if (!transport_is_bbb()) { ++ if (mod_data.can_stall && ++ fsg->residue == fsg->data_size && ++ (!fsg->curlun || fsg->curlun->sense_data != SS_NO_SENSE)) { ++ bh->state = BUF_STATE_EMPTY; ++ rc = halt_bulk_in_endpoint(fsg); ++ } else { ++ bh->inreq->zero = 1; ++ start_transfer(fsg, fsg->bulk_in, bh->inreq, ++ &bh->inreq_busy, &bh->state); ++ fsg->next_buffhd_to_fill = bh->next; ++ } ++ } ++ ++ /* ++ * For Bulk-only, mark the end of the data with a short ++ * packet. If we are allowed to stall, halt the bulk-in ++ * endpoint. (Note: This violates the Bulk-Only Transport ++ * specification, which requires us to pad the data if we ++ * don't halt the endpoint. Presumably nobody will mind.) ++ */ ++ else { ++ bh->inreq->zero = 1; ++ start_transfer(fsg, fsg->bulk_in, bh->inreq, ++ &bh->inreq_busy, &bh->state); ++ fsg->next_buffhd_to_fill = bh->next; ++ if (mod_data.can_stall) ++ rc = halt_bulk_in_endpoint(fsg); ++ } ++ break; ++ ++ /* We have processed all we want from the data the host has sent. ++ * There may still be outstanding bulk-out requests. */ ++ case DATA_DIR_FROM_HOST: ++ if (fsg->residue == 0) ++ ; // Nothing to receive ++ ++ /* Did the host stop sending unexpectedly early? */ ++ else if (fsg->short_packet_received) { ++ raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT); ++ rc = -EINTR; ++ } ++ ++ /* We haven't processed all the incoming data. Even though ++ * we may be allowed to stall, doing so would cause a race. ++ * The controller may already have ACK'ed all the remaining ++ * bulk-out packets, in which case the host wouldn't see a ++ * STALL. Not realizing the endpoint was halted, it wouldn't ++ * clear the halt -- leading to problems later on. */ ++#if 0 ++ else if (mod_data.can_stall) { ++ fsg_set_halt(fsg, fsg->bulk_out); ++ raise_exception(fsg, FSG_STATE_ABORT_BULK_OUT); ++ rc = -EINTR; ++ } ++#endif ++ ++ /* We can't stall. Read in the excess data and throw it ++ * all away. */ ++ else ++ rc = throw_away_data(fsg); ++ break; ++ } ++ return rc; ++} ++ ++ ++static int send_status(struct fsg_dev *fsg) ++{ ++ struct fsg_lun *curlun = fsg->curlun; ++ struct fsg_buffhd *bh; ++ int rc; ++ u8 status = US_BULK_STAT_OK; ++ u32 sd, sdinfo = 0; ++ ++ /* Wait for the next buffer to become available */ ++ bh = fsg->next_buffhd_to_fill; ++ while (bh->state != BUF_STATE_EMPTY) { ++ rc = sleep_thread(fsg); ++ if (rc) ++ return rc; ++ } ++ ++ if (curlun) { ++ sd = curlun->sense_data; ++ sdinfo = curlun->sense_data_info; ++ } else if (fsg->bad_lun_okay) ++ sd = SS_NO_SENSE; ++ else ++ sd = SS_LOGICAL_UNIT_NOT_SUPPORTED; ++ ++ if (fsg->phase_error) { ++ DBG(fsg, "sending phase-error status\n"); ++ status = US_BULK_STAT_PHASE; ++ sd = SS_INVALID_COMMAND; ++ } else if (sd != SS_NO_SENSE) { ++ DBG(fsg, "sending command-failure status\n"); ++ status = US_BULK_STAT_FAIL; ++ VDBG(fsg, " sense data: SK x%02x, ASC x%02x, ASCQ x%02x;" ++ " info x%x\n", ++ SK(sd), ASC(sd), ASCQ(sd), sdinfo); ++ } ++ ++ if (transport_is_bbb()) { ++ struct bulk_cs_wrap *csw = bh->buf; ++ ++ /* Store and send the Bulk-only CSW */ ++ csw->Signature = cpu_to_le32(US_BULK_CS_SIGN); ++ csw->Tag = fsg->tag; ++ csw->Residue = cpu_to_le32(fsg->residue); ++ csw->Status = status; ++ ++ bh->inreq->length = US_BULK_CS_WRAP_LEN; ++ bh->inreq->zero = 0; ++ start_transfer(fsg, fsg->bulk_in, bh->inreq, ++ &bh->inreq_busy, &bh->state); ++ ++ } else if (mod_data.transport_type == USB_PR_CB) { ++ ++ /* Control-Bulk transport has no status phase! */ ++ return 0; ++ ++ } else { // USB_PR_CBI ++ struct interrupt_data *buf = bh->buf; ++ ++ /* Store and send the Interrupt data. UFI sends the ASC ++ * and ASCQ bytes. Everything else sends a Type (which ++ * is always 0) and the status Value. */ ++ if (mod_data.protocol_type == USB_SC_UFI) { ++ buf->bType = ASC(sd); ++ buf->bValue = ASCQ(sd); ++ } else { ++ buf->bType = 0; ++ buf->bValue = status; ++ } ++ fsg->intreq->length = CBI_INTERRUPT_DATA_LEN; ++ ++ fsg->intr_buffhd = bh; // Point to the right buffhd ++ fsg->intreq->buf = bh->inreq->buf; ++ fsg->intreq->context = bh; ++ start_transfer(fsg, fsg->intr_in, fsg->intreq, ++ &fsg->intreq_busy, &bh->state); ++ } ++ ++ fsg->next_buffhd_to_fill = bh->next; ++ return 0; ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* Check whether the command is properly formed and whether its data size ++ * and direction agree with the values we already have. */ ++static int check_command(struct fsg_dev *fsg, int cmnd_size, ++ enum data_direction data_dir, unsigned int mask, ++ int needs_medium, const char *name) ++{ ++ int i; ++ int lun = fsg->cmnd[1] >> 5; ++ static const char dirletter[4] = {'u', 'o', 'i', 'n'}; ++ char hdlen[20]; ++ struct fsg_lun *curlun; ++ ++ /* Adjust the expected cmnd_size for protocol encapsulation padding. ++ * Transparent SCSI doesn't pad. */ ++ if (protocol_is_scsi()) ++ ; ++ ++ /* There's some disagreement as to whether RBC pads commands or not. ++ * We'll play it safe and accept either form. */ ++ else if (mod_data.protocol_type == USB_SC_RBC) { ++ if (fsg->cmnd_size == 12) ++ cmnd_size = 12; ++ ++ /* All the other protocols pad to 12 bytes */ ++ } else ++ cmnd_size = 12; ++ ++ hdlen[0] = 0; ++ if (fsg->data_dir != DATA_DIR_UNKNOWN) ++ sprintf(hdlen, ", H%c=%u", dirletter[(int) fsg->data_dir], ++ fsg->data_size); ++ VDBG(fsg, "SCSI command: %s; Dc=%d, D%c=%u; Hc=%d%s\n", ++ name, cmnd_size, dirletter[(int) data_dir], ++ fsg->data_size_from_cmnd, fsg->cmnd_size, hdlen); ++ ++ /* We can't reply at all until we know the correct data direction ++ * and size. */ ++ if (fsg->data_size_from_cmnd == 0) ++ data_dir = DATA_DIR_NONE; ++ if (fsg->data_dir == DATA_DIR_UNKNOWN) { // CB or CBI ++ fsg->data_dir = data_dir; ++ fsg->data_size = fsg->data_size_from_cmnd; ++ ++ } else { // Bulk-only ++ if (fsg->data_size < fsg->data_size_from_cmnd) { ++ ++ /* Host data size < Device data size is a phase error. ++ * Carry out the command, but only transfer as much ++ * as we are allowed. */ ++ fsg->data_size_from_cmnd = fsg->data_size; ++ fsg->phase_error = 1; ++ } ++ } ++ fsg->residue = fsg->usb_amount_left = fsg->data_size; ++ ++ /* Conflicting data directions is a phase error */ ++ if (fsg->data_dir != data_dir && fsg->data_size_from_cmnd > 0) { ++ fsg->phase_error = 1; ++ return -EINVAL; ++ } ++ ++ /* Verify the length of the command itself */ ++ if (cmnd_size != fsg->cmnd_size) { ++ ++ /* Special case workaround: There are plenty of buggy SCSI ++ * implementations. Many have issues with cbw->Length ++ * field passing a wrong command size. For those cases we ++ * always try to work around the problem by using the length ++ * sent by the host side provided it is at least as large ++ * as the correct command length. ++ * Examples of such cases would be MS-Windows, which issues ++ * REQUEST SENSE with cbw->Length == 12 where it should ++ * be 6, and xbox360 issuing INQUIRY, TEST UNIT READY and ++ * REQUEST SENSE with cbw->Length == 10 where it should ++ * be 6 as well. ++ */ ++ if (cmnd_size <= fsg->cmnd_size) { ++ DBG(fsg, "%s is buggy! Expected length %d " ++ "but we got %d\n", name, ++ cmnd_size, fsg->cmnd_size); ++ cmnd_size = fsg->cmnd_size; ++ } else { ++ fsg->phase_error = 1; ++ return -EINVAL; ++ } ++ } ++ ++ /* Check that the LUN values are consistent */ ++ if (transport_is_bbb()) { ++ if (fsg->lun != lun) ++ DBG(fsg, "using LUN %d from CBW, " ++ "not LUN %d from CDB\n", ++ fsg->lun, lun); ++ } ++ ++ /* Check the LUN */ ++ curlun = fsg->curlun; ++ if (curlun) { ++ if (fsg->cmnd[0] != REQUEST_SENSE) { ++ curlun->sense_data = SS_NO_SENSE; ++ curlun->sense_data_info = 0; ++ curlun->info_valid = 0; ++ } ++ } else { ++ fsg->bad_lun_okay = 0; ++ ++ /* INQUIRY and REQUEST SENSE commands are explicitly allowed ++ * to use unsupported LUNs; all others may not. */ ++ if (fsg->cmnd[0] != INQUIRY && ++ fsg->cmnd[0] != REQUEST_SENSE) { ++ DBG(fsg, "unsupported LUN %d\n", fsg->lun); ++ return -EINVAL; ++ } ++ } ++ ++ /* If a unit attention condition exists, only INQUIRY and ++ * REQUEST SENSE commands are allowed; anything else must fail. */ ++ if (curlun && curlun->unit_attention_data != SS_NO_SENSE && ++ fsg->cmnd[0] != INQUIRY && ++ fsg->cmnd[0] != REQUEST_SENSE) { ++ curlun->sense_data = curlun->unit_attention_data; ++ curlun->unit_attention_data = SS_NO_SENSE; ++ return -EINVAL; ++ } ++ ++ /* Check that only command bytes listed in the mask are non-zero */ ++ fsg->cmnd[1] &= 0x1f; // Mask away the LUN ++ for (i = 1; i < cmnd_size; ++i) { ++ if (fsg->cmnd[i] && !(mask & (1 << i))) { ++ if (curlun) ++ curlun->sense_data = SS_INVALID_FIELD_IN_CDB; ++ return -EINVAL; ++ } ++ } ++ ++ /* If the medium isn't mounted and the command needs to access ++ * it, return an error. */ ++ if (curlun && !fsg_lun_is_open(curlun) && needs_medium) { ++ curlun->sense_data = SS_MEDIUM_NOT_PRESENT; ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++/* wrapper of check_command for data size in blocks handling */ ++static int check_command_size_in_blocks(struct fsg_dev *fsg, int cmnd_size, ++ enum data_direction data_dir, unsigned int mask, ++ int needs_medium, const char *name) ++{ ++ if (fsg->curlun) ++ fsg->data_size_from_cmnd <<= fsg->curlun->blkbits; ++ return check_command(fsg, cmnd_size, data_dir, ++ mask, needs_medium, name); ++} ++ ++static int do_scsi_command(struct fsg_dev *fsg) ++{ ++ struct fsg_buffhd *bh; ++ int rc; ++ int reply = -EINVAL; ++ int i; ++ static char unknown[16]; ++ ++ dump_cdb(fsg); ++ ++ /* Wait for the next buffer to become available for data or status */ ++ bh = fsg->next_buffhd_to_drain = fsg->next_buffhd_to_fill; ++ while (bh->state != BUF_STATE_EMPTY) { ++ rc = sleep_thread(fsg); ++ if (rc) ++ return rc; ++ } ++ fsg->phase_error = 0; ++ fsg->short_packet_received = 0; ++ ++ down_read(&fsg->filesem); // We're using the backing file ++ switch (fsg->cmnd[0]) { ++ ++ case INQUIRY: ++ fsg->data_size_from_cmnd = fsg->cmnd[4]; ++ if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST, ++ (1<<4), 0, ++ "INQUIRY")) == 0) ++ reply = do_inquiry(fsg, bh); ++ break; ++ ++ case MODE_SELECT: ++ fsg->data_size_from_cmnd = fsg->cmnd[4]; ++ if ((reply = check_command(fsg, 6, DATA_DIR_FROM_HOST, ++ (1<<1) | (1<<4), 0, ++ "MODE SELECT(6)")) == 0) ++ reply = do_mode_select(fsg, bh); ++ break; ++ ++ case MODE_SELECT_10: ++ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]); ++ if ((reply = check_command(fsg, 10, DATA_DIR_FROM_HOST, ++ (1<<1) | (3<<7), 0, ++ "MODE SELECT(10)")) == 0) ++ reply = do_mode_select(fsg, bh); ++ break; ++ ++ case MODE_SENSE: ++ fsg->data_size_from_cmnd = fsg->cmnd[4]; ++ if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST, ++ (1<<1) | (1<<2) | (1<<4), 0, ++ "MODE SENSE(6)")) == 0) ++ reply = do_mode_sense(fsg, bh); ++ break; ++ ++ case MODE_SENSE_10: ++ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]); ++ if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST, ++ (1<<1) | (1<<2) | (3<<7), 0, ++ "MODE SENSE(10)")) == 0) ++ reply = do_mode_sense(fsg, bh); ++ break; ++ ++ case ALLOW_MEDIUM_REMOVAL: ++ fsg->data_size_from_cmnd = 0; ++ if ((reply = check_command(fsg, 6, DATA_DIR_NONE, ++ (1<<4), 0, ++ "PREVENT-ALLOW MEDIUM REMOVAL")) == 0) ++ reply = do_prevent_allow(fsg); ++ break; ++ ++ case READ_6: ++ i = fsg->cmnd[4]; ++ fsg->data_size_from_cmnd = (i == 0) ? 256 : i; ++ if ((reply = check_command_size_in_blocks(fsg, 6, ++ DATA_DIR_TO_HOST, ++ (7<<1) | (1<<4), 1, ++ "READ(6)")) == 0) ++ reply = do_read(fsg); ++ break; ++ ++ case READ_10: ++ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]); ++ if ((reply = check_command_size_in_blocks(fsg, 10, ++ DATA_DIR_TO_HOST, ++ (1<<1) | (0xf<<2) | (3<<7), 1, ++ "READ(10)")) == 0) ++ reply = do_read(fsg); ++ break; ++ ++ case READ_12: ++ fsg->data_size_from_cmnd = get_unaligned_be32(&fsg->cmnd[6]); ++ if ((reply = check_command_size_in_blocks(fsg, 12, ++ DATA_DIR_TO_HOST, ++ (1<<1) | (0xf<<2) | (0xf<<6), 1, ++ "READ(12)")) == 0) ++ reply = do_read(fsg); ++ break; ++ ++ case READ_CAPACITY: ++ fsg->data_size_from_cmnd = 8; ++ if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST, ++ (0xf<<2) | (1<<8), 1, ++ "READ CAPACITY")) == 0) ++ reply = do_read_capacity(fsg, bh); ++ break; ++ ++ case READ_HEADER: ++ if (!mod_data.cdrom) ++ goto unknown_cmnd; ++ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]); ++ if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST, ++ (3<<7) | (0x1f<<1), 1, ++ "READ HEADER")) == 0) ++ reply = do_read_header(fsg, bh); ++ break; ++ ++ case READ_TOC: ++ if (!mod_data.cdrom) ++ goto unknown_cmnd; ++ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]); ++ if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST, ++ (7<<6) | (1<<1), 1, ++ "READ TOC")) == 0) ++ reply = do_read_toc(fsg, bh); ++ break; ++ ++ case READ_FORMAT_CAPACITIES: ++ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]); ++ if ((reply = check_command(fsg, 10, DATA_DIR_TO_HOST, ++ (3<<7), 1, ++ "READ FORMAT CAPACITIES")) == 0) ++ reply = do_read_format_capacities(fsg, bh); ++ break; ++ ++ case REQUEST_SENSE: ++ fsg->data_size_from_cmnd = fsg->cmnd[4]; ++ if ((reply = check_command(fsg, 6, DATA_DIR_TO_HOST, ++ (1<<4), 0, ++ "REQUEST SENSE")) == 0) ++ reply = do_request_sense(fsg, bh); ++ break; ++ ++ case START_STOP: ++ fsg->data_size_from_cmnd = 0; ++ if ((reply = check_command(fsg, 6, DATA_DIR_NONE, ++ (1<<1) | (1<<4), 0, ++ "START-STOP UNIT")) == 0) ++ reply = do_start_stop(fsg); ++ break; ++ ++ case SYNCHRONIZE_CACHE: ++ fsg->data_size_from_cmnd = 0; ++ if ((reply = check_command(fsg, 10, DATA_DIR_NONE, ++ (0xf<<2) | (3<<7), 1, ++ "SYNCHRONIZE CACHE")) == 0) ++ reply = do_synchronize_cache(fsg); ++ break; ++ ++ case TEST_UNIT_READY: ++ fsg->data_size_from_cmnd = 0; ++ reply = check_command(fsg, 6, DATA_DIR_NONE, ++ 0, 1, ++ "TEST UNIT READY"); ++ break; ++ ++ /* Although optional, this command is used by MS-Windows. We ++ * support a minimal version: BytChk must be 0. */ ++ case VERIFY: ++ fsg->data_size_from_cmnd = 0; ++ if ((reply = check_command(fsg, 10, DATA_DIR_NONE, ++ (1<<1) | (0xf<<2) | (3<<7), 1, ++ "VERIFY")) == 0) ++ reply = do_verify(fsg); ++ break; ++ ++ case WRITE_6: ++ i = fsg->cmnd[4]; ++ fsg->data_size_from_cmnd = (i == 0) ? 256 : i; ++ if ((reply = check_command_size_in_blocks(fsg, 6, ++ DATA_DIR_FROM_HOST, ++ (7<<1) | (1<<4), 1, ++ "WRITE(6)")) == 0) ++ reply = do_write(fsg); ++ break; ++ ++ case WRITE_10: ++ fsg->data_size_from_cmnd = get_unaligned_be16(&fsg->cmnd[7]); ++ if ((reply = check_command_size_in_blocks(fsg, 10, ++ DATA_DIR_FROM_HOST, ++ (1<<1) | (0xf<<2) | (3<<7), 1, ++ "WRITE(10)")) == 0) ++ reply = do_write(fsg); ++ break; ++ ++ case WRITE_12: ++ fsg->data_size_from_cmnd = get_unaligned_be32(&fsg->cmnd[6]); ++ if ((reply = check_command_size_in_blocks(fsg, 12, ++ DATA_DIR_FROM_HOST, ++ (1<<1) | (0xf<<2) | (0xf<<6), 1, ++ "WRITE(12)")) == 0) ++ reply = do_write(fsg); ++ break; ++ ++ /* Some mandatory commands that we recognize but don't implement. ++ * They don't mean much in this setting. It's left as an exercise ++ * for anyone interested to implement RESERVE and RELEASE in terms ++ * of Posix locks. */ ++ case FORMAT_UNIT: ++ case RELEASE: ++ case RESERVE: ++ case SEND_DIAGNOSTIC: ++ // Fall through ++ ++ default: ++ unknown_cmnd: ++ fsg->data_size_from_cmnd = 0; ++ sprintf(unknown, "Unknown x%02x", fsg->cmnd[0]); ++ if ((reply = check_command(fsg, fsg->cmnd_size, ++ DATA_DIR_UNKNOWN, ~0, 0, unknown)) == 0) { ++ fsg->curlun->sense_data = SS_INVALID_COMMAND; ++ reply = -EINVAL; ++ } ++ break; ++ } ++ up_read(&fsg->filesem); ++ ++ if (reply == -EINTR || signal_pending(current)) ++ return -EINTR; ++ ++ /* Set up the single reply buffer for finish_reply() */ ++ if (reply == -EINVAL) ++ reply = 0; // Error reply length ++ if (reply >= 0 && fsg->data_dir == DATA_DIR_TO_HOST) { ++ reply = min((u32) reply, fsg->data_size_from_cmnd); ++ bh->inreq->length = reply; ++ bh->state = BUF_STATE_FULL; ++ fsg->residue -= reply; ++ } // Otherwise it's already set ++ ++ return 0; ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++static int received_cbw(struct fsg_dev *fsg, struct fsg_buffhd *bh) ++{ ++ struct usb_request *req = bh->outreq; ++ struct bulk_cb_wrap *cbw = req->buf; ++ ++ /* Was this a real packet? Should it be ignored? */ ++ if (req->status || test_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags)) ++ return -EINVAL; ++ ++ /* Is the CBW valid? */ ++ if (req->actual != US_BULK_CB_WRAP_LEN || ++ cbw->Signature != cpu_to_le32( ++ US_BULK_CB_SIGN)) { ++ DBG(fsg, "invalid CBW: len %u sig 0x%x\n", ++ req->actual, ++ le32_to_cpu(cbw->Signature)); ++ ++ /* The Bulk-only spec says we MUST stall the IN endpoint ++ * (6.6.1), so it's unavoidable. It also says we must ++ * retain this state until the next reset, but there's ++ * no way to tell the controller driver it should ignore ++ * Clear-Feature(HALT) requests. ++ * ++ * We aren't required to halt the OUT endpoint; instead ++ * we can simply accept and discard any data received ++ * until the next reset. */ ++ wedge_bulk_in_endpoint(fsg); ++ set_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags); ++ return -EINVAL; ++ } ++ ++ /* Is the CBW meaningful? */ ++ if (cbw->Lun >= FSG_MAX_LUNS || cbw->Flags & ~US_BULK_FLAG_IN || ++ cbw->Length <= 0 || cbw->Length > MAX_COMMAND_SIZE) { ++ DBG(fsg, "non-meaningful CBW: lun = %u, flags = 0x%x, " ++ "cmdlen %u\n", ++ cbw->Lun, cbw->Flags, cbw->Length); ++ ++ /* We can do anything we want here, so let's stall the ++ * bulk pipes if we are allowed to. */ ++ if (mod_data.can_stall) { ++ fsg_set_halt(fsg, fsg->bulk_out); ++ halt_bulk_in_endpoint(fsg); ++ } ++ return -EINVAL; ++ } ++ ++ /* Save the command for later */ ++ fsg->cmnd_size = cbw->Length; ++ memcpy(fsg->cmnd, cbw->CDB, fsg->cmnd_size); ++ if (cbw->Flags & US_BULK_FLAG_IN) ++ fsg->data_dir = DATA_DIR_TO_HOST; ++ else ++ fsg->data_dir = DATA_DIR_FROM_HOST; ++ fsg->data_size = le32_to_cpu(cbw->DataTransferLength); ++ if (fsg->data_size == 0) ++ fsg->data_dir = DATA_DIR_NONE; ++ fsg->lun = cbw->Lun; ++ fsg->tag = cbw->Tag; ++ return 0; ++} ++ ++ ++static int get_next_command(struct fsg_dev *fsg) ++{ ++ struct fsg_buffhd *bh; ++ int rc = 0; ++ ++ if (transport_is_bbb()) { ++ ++ /* Wait for the next buffer to become available */ ++ bh = fsg->next_buffhd_to_fill; ++ while (bh->state != BUF_STATE_EMPTY) { ++ rc = sleep_thread(fsg); ++ if (rc) ++ return rc; ++ } ++ ++ /* Queue a request to read a Bulk-only CBW */ ++ set_bulk_out_req_length(fsg, bh, US_BULK_CB_WRAP_LEN); ++ start_transfer(fsg, fsg->bulk_out, bh->outreq, ++ &bh->outreq_busy, &bh->state); ++ ++ /* We will drain the buffer in software, which means we ++ * can reuse it for the next filling. No need to advance ++ * next_buffhd_to_fill. */ ++ ++ /* Wait for the CBW to arrive */ ++ while (bh->state != BUF_STATE_FULL) { ++ rc = sleep_thread(fsg); ++ if (rc) ++ return rc; ++ } ++ smp_rmb(); ++ rc = received_cbw(fsg, bh); ++ bh->state = BUF_STATE_EMPTY; ++ ++ } else { // USB_PR_CB or USB_PR_CBI ++ ++ /* Wait for the next command to arrive */ ++ while (fsg->cbbuf_cmnd_size == 0) { ++ rc = sleep_thread(fsg); ++ if (rc) ++ return rc; ++ } ++ ++ /* Is the previous status interrupt request still busy? ++ * The host is allowed to skip reading the status, ++ * so we must cancel it. */ ++ if (fsg->intreq_busy) ++ usb_ep_dequeue(fsg->intr_in, fsg->intreq); ++ ++ /* Copy the command and mark the buffer empty */ ++ fsg->data_dir = DATA_DIR_UNKNOWN; ++ spin_lock_irq(&fsg->lock); ++ fsg->cmnd_size = fsg->cbbuf_cmnd_size; ++ memcpy(fsg->cmnd, fsg->cbbuf_cmnd, fsg->cmnd_size); ++ fsg->cbbuf_cmnd_size = 0; ++ spin_unlock_irq(&fsg->lock); ++ ++ /* Use LUN from the command */ ++ fsg->lun = fsg->cmnd[1] >> 5; ++ } ++ ++ /* Update current lun */ ++ if (fsg->lun >= 0 && fsg->lun < fsg->nluns) ++ fsg->curlun = &fsg->luns[fsg->lun]; ++ else ++ fsg->curlun = NULL; ++ ++ return rc; ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++static int enable_endpoint(struct fsg_dev *fsg, struct usb_ep *ep, ++ const struct usb_endpoint_descriptor *d) ++{ ++ int rc; ++ ++ ep->driver_data = fsg; ++ ep->desc = d; ++ rc = usb_ep_enable(ep); ++ if (rc) ++ ERROR(fsg, "can't enable %s, result %d\n", ep->name, rc); ++ return rc; ++} ++ ++static int alloc_request(struct fsg_dev *fsg, struct usb_ep *ep, ++ struct usb_request **preq) ++{ ++ *preq = usb_ep_alloc_request(ep, GFP_ATOMIC); ++ if (*preq) ++ return 0; ++ ERROR(fsg, "can't allocate request for %s\n", ep->name); ++ return -ENOMEM; ++} ++ ++/* ++ * Reset interface setting and re-init endpoint state (toggle etc). ++ * Call with altsetting < 0 to disable the interface. The only other ++ * available altsetting is 0, which enables the interface. ++ */ ++static int do_set_interface(struct fsg_dev *fsg, int altsetting) ++{ ++ int rc = 0; ++ int i; ++ const struct usb_endpoint_descriptor *d; ++ ++ if (fsg->running) ++ DBG(fsg, "reset interface\n"); ++ ++reset: ++ /* Deallocate the requests */ ++ for (i = 0; i < fsg_num_buffers; ++i) { ++ struct fsg_buffhd *bh = &fsg->buffhds[i]; ++ ++ if (bh->inreq) { ++ usb_ep_free_request(fsg->bulk_in, bh->inreq); ++ bh->inreq = NULL; ++ } ++ if (bh->outreq) { ++ usb_ep_free_request(fsg->bulk_out, bh->outreq); ++ bh->outreq = NULL; ++ } ++ } ++ if (fsg->intreq) { ++ usb_ep_free_request(fsg->intr_in, fsg->intreq); ++ fsg->intreq = NULL; ++ } ++ ++ /* Disable the endpoints */ ++ if (fsg->bulk_in_enabled) { ++ usb_ep_disable(fsg->bulk_in); ++ fsg->bulk_in_enabled = 0; ++ } ++ if (fsg->bulk_out_enabled) { ++ usb_ep_disable(fsg->bulk_out); ++ fsg->bulk_out_enabled = 0; ++ } ++ if (fsg->intr_in_enabled) { ++ usb_ep_disable(fsg->intr_in); ++ fsg->intr_in_enabled = 0; ++ } ++ ++ fsg->running = 0; ++ if (altsetting < 0 || rc != 0) ++ return rc; ++ ++ DBG(fsg, "set interface %d\n", altsetting); ++ ++ /* Enable the endpoints */ ++ d = fsg_ep_desc(fsg->gadget, ++ &fsg_fs_bulk_in_desc, &fsg_hs_bulk_in_desc, ++ &fsg_ss_bulk_in_desc); ++ if ((rc = enable_endpoint(fsg, fsg->bulk_in, d)) != 0) ++ goto reset; ++ fsg->bulk_in_enabled = 1; ++ ++ d = fsg_ep_desc(fsg->gadget, ++ &fsg_fs_bulk_out_desc, &fsg_hs_bulk_out_desc, ++ &fsg_ss_bulk_out_desc); ++ if ((rc = enable_endpoint(fsg, fsg->bulk_out, d)) != 0) ++ goto reset; ++ fsg->bulk_out_enabled = 1; ++ fsg->bulk_out_maxpacket = usb_endpoint_maxp(d); ++ clear_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags); ++ ++ if (transport_is_cbi()) { ++ d = fsg_ep_desc(fsg->gadget, ++ &fsg_fs_intr_in_desc, &fsg_hs_intr_in_desc, ++ &fsg_ss_intr_in_desc); ++ if ((rc = enable_endpoint(fsg, fsg->intr_in, d)) != 0) ++ goto reset; ++ fsg->intr_in_enabled = 1; ++ } ++ ++ /* Allocate the requests */ ++ for (i = 0; i < fsg_num_buffers; ++i) { ++ struct fsg_buffhd *bh = &fsg->buffhds[i]; ++ ++ if ((rc = alloc_request(fsg, fsg->bulk_in, &bh->inreq)) != 0) ++ goto reset; ++ if ((rc = alloc_request(fsg, fsg->bulk_out, &bh->outreq)) != 0) ++ goto reset; ++ bh->inreq->buf = bh->outreq->buf = bh->buf; ++ bh->inreq->context = bh->outreq->context = bh; ++ bh->inreq->complete = bulk_in_complete; ++ bh->outreq->complete = bulk_out_complete; ++ } ++ if (transport_is_cbi()) { ++ if ((rc = alloc_request(fsg, fsg->intr_in, &fsg->intreq)) != 0) ++ goto reset; ++ fsg->intreq->complete = intr_in_complete; ++ } ++ ++ fsg->running = 1; ++ for (i = 0; i < fsg->nluns; ++i) ++ fsg->luns[i].unit_attention_data = SS_RESET_OCCURRED; ++ return rc; ++} ++ ++ ++/* ++ * Change our operational configuration. This code must agree with the code ++ * that returns config descriptors, and with interface altsetting code. ++ * ++ * It's also responsible for power management interactions. Some ++ * configurations might not work with our current power sources. ++ * For now we just assume the gadget is always self-powered. ++ */ ++static int do_set_config(struct fsg_dev *fsg, u8 new_config) ++{ ++ int rc = 0; ++ ++ /* Disable the single interface */ ++ if (fsg->config != 0) { ++ DBG(fsg, "reset config\n"); ++ fsg->config = 0; ++ rc = do_set_interface(fsg, -1); ++ } ++ ++ /* Enable the interface */ ++ if (new_config != 0) { ++ fsg->config = new_config; ++ if ((rc = do_set_interface(fsg, 0)) != 0) ++ fsg->config = 0; // Reset on errors ++ else ++ INFO(fsg, "%s config #%d\n", ++ usb_speed_string(fsg->gadget->speed), ++ fsg->config); ++ } ++ return rc; ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++static void handle_exception(struct fsg_dev *fsg) ++{ ++ siginfo_t info; ++ int sig; ++ int i; ++ int num_active; ++ struct fsg_buffhd *bh; ++ enum fsg_state old_state; ++ u8 new_config; ++ struct fsg_lun *curlun; ++ unsigned int exception_req_tag; ++ int rc; ++ ++ /* Clear the existing signals. Anything but SIGUSR1 is converted ++ * into a high-priority EXIT exception. */ ++ for (;;) { ++ sig = dequeue_signal_lock(current, ¤t->blocked, &info); ++ if (!sig) ++ break; ++ if (sig != SIGUSR1) { ++ if (fsg->state < FSG_STATE_EXIT) ++ DBG(fsg, "Main thread exiting on signal\n"); ++ raise_exception(fsg, FSG_STATE_EXIT); ++ } ++ } ++ ++ /* Cancel all the pending transfers */ ++ if (fsg->intreq_busy) ++ usb_ep_dequeue(fsg->intr_in, fsg->intreq); ++ for (i = 0; i < fsg_num_buffers; ++i) { ++ bh = &fsg->buffhds[i]; ++ if (bh->inreq_busy) ++ usb_ep_dequeue(fsg->bulk_in, bh->inreq); ++ if (bh->outreq_busy) ++ usb_ep_dequeue(fsg->bulk_out, bh->outreq); ++ } ++ ++ /* Wait until everything is idle */ ++ for (;;) { ++ num_active = fsg->intreq_busy; ++ for (i = 0; i < fsg_num_buffers; ++i) { ++ bh = &fsg->buffhds[i]; ++ num_active += bh->inreq_busy + bh->outreq_busy; ++ } ++ if (num_active == 0) ++ break; ++ if (sleep_thread(fsg)) ++ return; ++ } ++ ++ /* Clear out the controller's fifos */ ++ if (fsg->bulk_in_enabled) ++ usb_ep_fifo_flush(fsg->bulk_in); ++ if (fsg->bulk_out_enabled) ++ usb_ep_fifo_flush(fsg->bulk_out); ++ if (fsg->intr_in_enabled) ++ usb_ep_fifo_flush(fsg->intr_in); ++ ++ /* Reset the I/O buffer states and pointers, the SCSI ++ * state, and the exception. Then invoke the handler. */ ++ spin_lock_irq(&fsg->lock); ++ ++ for (i = 0; i < fsg_num_buffers; ++i) { ++ bh = &fsg->buffhds[i]; ++ bh->state = BUF_STATE_EMPTY; ++ } ++ fsg->next_buffhd_to_fill = fsg->next_buffhd_to_drain = ++ &fsg->buffhds[0]; ++ ++ exception_req_tag = fsg->exception_req_tag; ++ new_config = fsg->new_config; ++ old_state = fsg->state; ++ ++ if (old_state == FSG_STATE_ABORT_BULK_OUT) ++ fsg->state = FSG_STATE_STATUS_PHASE; ++ else { ++ for (i = 0; i < fsg->nluns; ++i) { ++ curlun = &fsg->luns[i]; ++ curlun->prevent_medium_removal = 0; ++ curlun->sense_data = curlun->unit_attention_data = ++ SS_NO_SENSE; ++ curlun->sense_data_info = 0; ++ curlun->info_valid = 0; ++ } ++ fsg->state = FSG_STATE_IDLE; ++ } ++ spin_unlock_irq(&fsg->lock); ++ ++ /* Carry out any extra actions required for the exception */ ++ switch (old_state) { ++ default: ++ break; ++ ++ case FSG_STATE_ABORT_BULK_OUT: ++ send_status(fsg); ++ spin_lock_irq(&fsg->lock); ++ if (fsg->state == FSG_STATE_STATUS_PHASE) ++ fsg->state = FSG_STATE_IDLE; ++ spin_unlock_irq(&fsg->lock); ++ break; ++ ++ case FSG_STATE_RESET: ++ /* In case we were forced against our will to halt a ++ * bulk endpoint, clear the halt now. (The SuperH UDC ++ * requires this.) */ ++ if (test_and_clear_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags)) ++ usb_ep_clear_halt(fsg->bulk_in); ++ ++ if (transport_is_bbb()) { ++ if (fsg->ep0_req_tag == exception_req_tag) ++ ep0_queue(fsg); // Complete the status stage ++ ++ } else if (transport_is_cbi()) ++ send_status(fsg); // Status by interrupt pipe ++ ++ /* Technically this should go here, but it would only be ++ * a waste of time. Ditto for the INTERFACE_CHANGE and ++ * CONFIG_CHANGE cases. */ ++ // for (i = 0; i < fsg->nluns; ++i) ++ // fsg->luns[i].unit_attention_data = SS_RESET_OCCURRED; ++ break; ++ ++ case FSG_STATE_INTERFACE_CHANGE: ++ rc = do_set_interface(fsg, 0); ++ if (fsg->ep0_req_tag != exception_req_tag) ++ break; ++ if (rc != 0) // STALL on errors ++ fsg_set_halt(fsg, fsg->ep0); ++ else // Complete the status stage ++ ep0_queue(fsg); ++ break; ++ ++ case FSG_STATE_CONFIG_CHANGE: ++ rc = do_set_config(fsg, new_config); ++ if (fsg->ep0_req_tag != exception_req_tag) ++ break; ++ if (rc != 0) // STALL on errors ++ fsg_set_halt(fsg, fsg->ep0); ++ else // Complete the status stage ++ ep0_queue(fsg); ++ break; ++ ++ case FSG_STATE_DISCONNECT: ++ for (i = 0; i < fsg->nluns; ++i) ++ fsg_lun_fsync_sub(fsg->luns + i); ++ do_set_config(fsg, 0); // Unconfigured state ++ break; ++ ++ case FSG_STATE_EXIT: ++ case FSG_STATE_TERMINATED: ++ do_set_config(fsg, 0); // Free resources ++ spin_lock_irq(&fsg->lock); ++ fsg->state = FSG_STATE_TERMINATED; // Stop the thread ++ spin_unlock_irq(&fsg->lock); ++ break; ++ } ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++static int fsg_main_thread(void *fsg_) ++{ ++ struct fsg_dev *fsg = fsg_; ++ ++ /* Allow the thread to be killed by a signal, but set the signal mask ++ * to block everything but INT, TERM, KILL, and USR1. */ ++ allow_signal(SIGINT); ++ allow_signal(SIGTERM); ++ allow_signal(SIGKILL); ++ allow_signal(SIGUSR1); ++ ++ /* Allow the thread to be frozen */ ++ set_freezable(); ++ ++ /* Arrange for userspace references to be interpreted as kernel ++ * pointers. That way we can pass a kernel pointer to a routine ++ * that expects a __user pointer and it will work okay. */ ++ set_fs(get_ds()); ++ ++ /* The main loop */ ++ while (fsg->state != FSG_STATE_TERMINATED) { ++ if (exception_in_progress(fsg) || signal_pending(current)) { ++ handle_exception(fsg); ++ continue; ++ } ++ ++ if (!fsg->running) { ++ sleep_thread(fsg); ++ continue; ++ } ++ ++ if (get_next_command(fsg)) ++ continue; ++ ++ spin_lock_irq(&fsg->lock); ++ if (!exception_in_progress(fsg)) ++ fsg->state = FSG_STATE_DATA_PHASE; ++ spin_unlock_irq(&fsg->lock); ++ ++ if (do_scsi_command(fsg) || finish_reply(fsg)) ++ continue; ++ ++ spin_lock_irq(&fsg->lock); ++ if (!exception_in_progress(fsg)) ++ fsg->state = FSG_STATE_STATUS_PHASE; ++ spin_unlock_irq(&fsg->lock); ++ ++ if (send_status(fsg)) ++ continue; ++ ++ spin_lock_irq(&fsg->lock); ++ if (!exception_in_progress(fsg)) ++ fsg->state = FSG_STATE_IDLE; ++ spin_unlock_irq(&fsg->lock); ++ } ++ ++ spin_lock_irq(&fsg->lock); ++ fsg->thread_task = NULL; ++ spin_unlock_irq(&fsg->lock); ++ ++ /* If we are exiting because of a signal, unregister the ++ * gadget driver. */ ++ if (test_and_clear_bit(REGISTERED, &fsg->atomic_bitflags)) ++ usb_gadget_unregister_driver(&fsg_driver); ++ ++ /* Let the unbind and cleanup routines know the thread has exited */ ++ complete_and_exit(&fsg->thread_notifier, 0); ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++ ++/* The write permissions and store_xxx pointers are set in fsg_bind() */ ++static DEVICE_ATTR(ro, 0444, fsg_show_ro, NULL); ++static DEVICE_ATTR(nofua, 0644, fsg_show_nofua, NULL); ++static DEVICE_ATTR(file, 0444, fsg_show_file, NULL); ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++static void fsg_release(struct kref *ref) ++{ ++ struct fsg_dev *fsg = container_of(ref, struct fsg_dev, ref); ++ ++ kfree(fsg->luns); ++ kfree(fsg); ++} ++ ++static void lun_release(struct device *dev) ++{ ++ struct rw_semaphore *filesem = dev_get_drvdata(dev); ++ struct fsg_dev *fsg = ++ container_of(filesem, struct fsg_dev, filesem); ++ ++ kref_put(&fsg->ref, fsg_release); ++} ++ ++static void /* __init_or_exit */ fsg_unbind(struct usb_gadget *gadget) ++{ ++ struct fsg_dev *fsg = get_gadget_data(gadget); ++ int i; ++ struct fsg_lun *curlun; ++ struct usb_request *req = fsg->ep0req; ++ ++ DBG(fsg, "unbind\n"); ++ clear_bit(REGISTERED, &fsg->atomic_bitflags); ++ ++ /* If the thread isn't already dead, tell it to exit now */ ++ if (fsg->state != FSG_STATE_TERMINATED) { ++ raise_exception(fsg, FSG_STATE_EXIT); ++ wait_for_completion(&fsg->thread_notifier); ++ ++ /* The cleanup routine waits for this completion also */ ++ complete(&fsg->thread_notifier); ++ } ++ ++ /* Unregister the sysfs attribute files and the LUNs */ ++ for (i = 0; i < fsg->nluns; ++i) { ++ curlun = &fsg->luns[i]; ++ if (curlun->registered) { ++ device_remove_file(&curlun->dev, &dev_attr_nofua); ++ device_remove_file(&curlun->dev, &dev_attr_ro); ++ device_remove_file(&curlun->dev, &dev_attr_file); ++ fsg_lun_close(curlun); ++ device_unregister(&curlun->dev); ++ curlun->registered = 0; ++ } ++ } ++ ++ /* Free the data buffers */ ++ for (i = 0; i < fsg_num_buffers; ++i) ++ kfree(fsg->buffhds[i].buf); ++ ++ /* Free the request and buffer for endpoint 0 */ ++ if (req) { ++ kfree(req->buf); ++ usb_ep_free_request(fsg->ep0, req); ++ } ++ ++ set_gadget_data(gadget, NULL); ++} ++ ++ ++static int __init check_parameters(struct fsg_dev *fsg) ++{ ++ int prot; ++ int gcnum; ++ ++ /* Store the default values */ ++ mod_data.transport_type = USB_PR_BULK; ++ mod_data.transport_name = "Bulk-only"; ++ mod_data.protocol_type = USB_SC_SCSI; ++ mod_data.protocol_name = "Transparent SCSI"; ++ ++ /* Some peripheral controllers are known not to be able to ++ * halt bulk endpoints correctly. If one of them is present, ++ * disable stalls. ++ */ ++ if (gadget_is_at91(fsg->gadget)) ++ mod_data.can_stall = 0; ++ ++ if (mod_data.release == 0xffff) { // Parameter wasn't set ++ gcnum = usb_gadget_controller_number(fsg->gadget); ++ if (gcnum >= 0) ++ mod_data.release = 0x0300 + gcnum; ++ else { ++ WARNING(fsg, "controller '%s' not recognized\n", ++ fsg->gadget->name); ++ mod_data.release = 0x0399; ++ } ++ } ++ ++ prot = simple_strtol(mod_data.protocol_parm, NULL, 0); ++ ++#ifdef CONFIG_USB_FILE_STORAGE_TEST ++ if (strnicmp(mod_data.transport_parm, "BBB", 10) == 0) { ++ ; // Use default setting ++ } else if (strnicmp(mod_data.transport_parm, "CB", 10) == 0) { ++ mod_data.transport_type = USB_PR_CB; ++ mod_data.transport_name = "Control-Bulk"; ++ } else if (strnicmp(mod_data.transport_parm, "CBI", 10) == 0) { ++ mod_data.transport_type = USB_PR_CBI; ++ mod_data.transport_name = "Control-Bulk-Interrupt"; ++ } else { ++ ERROR(fsg, "invalid transport: %s\n", mod_data.transport_parm); ++ return -EINVAL; ++ } ++ ++ if (strnicmp(mod_data.protocol_parm, "SCSI", 10) == 0 || ++ prot == USB_SC_SCSI) { ++ ; // Use default setting ++ } else if (strnicmp(mod_data.protocol_parm, "RBC", 10) == 0 || ++ prot == USB_SC_RBC) { ++ mod_data.protocol_type = USB_SC_RBC; ++ mod_data.protocol_name = "RBC"; ++ } else if (strnicmp(mod_data.protocol_parm, "8020", 4) == 0 || ++ strnicmp(mod_data.protocol_parm, "ATAPI", 10) == 0 || ++ prot == USB_SC_8020) { ++ mod_data.protocol_type = USB_SC_8020; ++ mod_data.protocol_name = "8020i (ATAPI)"; ++ } else if (strnicmp(mod_data.protocol_parm, "QIC", 3) == 0 || ++ prot == USB_SC_QIC) { ++ mod_data.protocol_type = USB_SC_QIC; ++ mod_data.protocol_name = "QIC-157"; ++ } else if (strnicmp(mod_data.protocol_parm, "UFI", 10) == 0 || ++ prot == USB_SC_UFI) { ++ mod_data.protocol_type = USB_SC_UFI; ++ mod_data.protocol_name = "UFI"; ++ } else if (strnicmp(mod_data.protocol_parm, "8070", 4) == 0 || ++ prot == USB_SC_8070) { ++ mod_data.protocol_type = USB_SC_8070; ++ mod_data.protocol_name = "8070i"; ++ } else { ++ ERROR(fsg, "invalid protocol: %s\n", mod_data.protocol_parm); ++ return -EINVAL; ++ } ++ ++ mod_data.buflen &= PAGE_CACHE_MASK; ++ if (mod_data.buflen <= 0) { ++ ERROR(fsg, "invalid buflen\n"); ++ return -ETOOSMALL; ++ } ++ ++#endif /* CONFIG_USB_FILE_STORAGE_TEST */ ++ ++ /* Serial string handling. ++ * On a real device, the serial string would be loaded ++ * from permanent storage. */ ++ if (mod_data.serial) { ++ const char *ch; ++ unsigned len = 0; ++ ++ /* Sanity check : ++ * The CB[I] specification limits the serial string to ++ * 12 uppercase hexadecimal characters. ++ * BBB need at least 12 uppercase hexadecimal characters, ++ * with a maximum of 126. */ ++ for (ch = mod_data.serial; *ch; ++ch) { ++ ++len; ++ if ((*ch < '0' || *ch > '9') && ++ (*ch < 'A' || *ch > 'F')) { /* not uppercase hex */ ++ WARNING(fsg, ++ "Invalid serial string character: %c\n", ++ *ch); ++ goto no_serial; ++ } ++ } ++ if (len > 126 || ++ (mod_data.transport_type == USB_PR_BULK && len < 12) || ++ (mod_data.transport_type != USB_PR_BULK && len > 12)) { ++ WARNING(fsg, "Invalid serial string length!\n"); ++ goto no_serial; ++ } ++ fsg_strings[FSG_STRING_SERIAL - 1].s = mod_data.serial; ++ } else { ++ WARNING(fsg, "No serial-number string provided!\n"); ++ no_serial: ++ device_desc.iSerialNumber = 0; ++ } ++ ++ return 0; ++} ++ ++ ++static int __init fsg_bind(struct usb_gadget *gadget) ++{ ++ struct fsg_dev *fsg = the_fsg; ++ int rc; ++ int i; ++ struct fsg_lun *curlun; ++ struct usb_ep *ep; ++ struct usb_request *req; ++ char *pathbuf, *p; ++ ++ fsg->gadget = gadget; ++ set_gadget_data(gadget, fsg); ++ fsg->ep0 = gadget->ep0; ++ fsg->ep0->driver_data = fsg; ++ ++ if ((rc = check_parameters(fsg)) != 0) ++ goto out; ++ ++ if (mod_data.removable) { // Enable the store_xxx attributes ++ dev_attr_file.attr.mode = 0644; ++ dev_attr_file.store = fsg_store_file; ++ if (!mod_data.cdrom) { ++ dev_attr_ro.attr.mode = 0644; ++ dev_attr_ro.store = fsg_store_ro; ++ } ++ } ++ ++ /* Only for removable media? */ ++ dev_attr_nofua.attr.mode = 0644; ++ dev_attr_nofua.store = fsg_store_nofua; ++ ++ /* Find out how many LUNs there should be */ ++ i = mod_data.nluns; ++ if (i == 0) ++ i = max(mod_data.num_filenames, 1u); ++ if (i > FSG_MAX_LUNS) { ++ ERROR(fsg, "invalid number of LUNs: %d\n", i); ++ rc = -EINVAL; ++ goto out; ++ } ++ ++ /* Create the LUNs, open their backing files, and register the ++ * LUN devices in sysfs. */ ++ fsg->luns = kzalloc(i * sizeof(struct fsg_lun), GFP_KERNEL); ++ if (!fsg->luns) { ++ rc = -ENOMEM; ++ goto out; ++ } ++ fsg->nluns = i; ++ ++ for (i = 0; i < fsg->nluns; ++i) { ++ curlun = &fsg->luns[i]; ++ curlun->cdrom = !!mod_data.cdrom; ++ curlun->ro = mod_data.cdrom || mod_data.ro[i]; ++ curlun->initially_ro = curlun->ro; ++ curlun->removable = mod_data.removable; ++ curlun->nofua = mod_data.nofua[i]; ++ curlun->dev.release = lun_release; ++ curlun->dev.parent = &gadget->dev; ++ curlun->dev.driver = &fsg_driver.driver; ++ dev_set_drvdata(&curlun->dev, &fsg->filesem); ++ dev_set_name(&curlun->dev,"%s-lun%d", ++ dev_name(&gadget->dev), i); ++ ++ kref_get(&fsg->ref); ++ rc = device_register(&curlun->dev); ++ if (rc) { ++ INFO(fsg, "failed to register LUN%d: %d\n", i, rc); ++ put_device(&curlun->dev); ++ goto out; ++ } ++ curlun->registered = 1; ++ ++ rc = device_create_file(&curlun->dev, &dev_attr_ro); ++ if (rc) ++ goto out; ++ rc = device_create_file(&curlun->dev, &dev_attr_nofua); ++ if (rc) ++ goto out; ++ rc = device_create_file(&curlun->dev, &dev_attr_file); ++ if (rc) ++ goto out; ++ ++ if (mod_data.file[i] && *mod_data.file[i]) { ++ rc = fsg_lun_open(curlun, mod_data.file[i]); ++ if (rc) ++ goto out; ++ } else if (!mod_data.removable) { ++ ERROR(fsg, "no file given for LUN%d\n", i); ++ rc = -EINVAL; ++ goto out; ++ } ++ } ++ ++ /* Find all the endpoints we will use */ ++ usb_ep_autoconfig_reset(gadget); ++ ep = usb_ep_autoconfig(gadget, &fsg_fs_bulk_in_desc); ++ if (!ep) ++ goto autoconf_fail; ++ ep->driver_data = fsg; // claim the endpoint ++ fsg->bulk_in = ep; ++ ++ ep = usb_ep_autoconfig(gadget, &fsg_fs_bulk_out_desc); ++ if (!ep) ++ goto autoconf_fail; ++ ep->driver_data = fsg; // claim the endpoint ++ fsg->bulk_out = ep; ++ ++ if (transport_is_cbi()) { ++ ep = usb_ep_autoconfig(gadget, &fsg_fs_intr_in_desc); ++ if (!ep) ++ goto autoconf_fail; ++ ep->driver_data = fsg; // claim the endpoint ++ fsg->intr_in = ep; ++ } ++ ++ /* Fix up the descriptors */ ++ device_desc.idVendor = cpu_to_le16(mod_data.vendor); ++ device_desc.idProduct = cpu_to_le16(mod_data.product); ++ device_desc.bcdDevice = cpu_to_le16(mod_data.release); ++ ++ i = (transport_is_cbi() ? 3 : 2); // Number of endpoints ++ fsg_intf_desc.bNumEndpoints = i; ++ fsg_intf_desc.bInterfaceSubClass = mod_data.protocol_type; ++ fsg_intf_desc.bInterfaceProtocol = mod_data.transport_type; ++ fsg_fs_function[i + FSG_FS_FUNCTION_PRE_EP_ENTRIES] = NULL; ++ ++ if (gadget_is_dualspeed(gadget)) { ++ fsg_hs_function[i + FSG_HS_FUNCTION_PRE_EP_ENTRIES] = NULL; ++ ++ /* Assume endpoint addresses are the same for both speeds */ ++ fsg_hs_bulk_in_desc.bEndpointAddress = ++ fsg_fs_bulk_in_desc.bEndpointAddress; ++ fsg_hs_bulk_out_desc.bEndpointAddress = ++ fsg_fs_bulk_out_desc.bEndpointAddress; ++ fsg_hs_intr_in_desc.bEndpointAddress = ++ fsg_fs_intr_in_desc.bEndpointAddress; ++ } ++ ++ if (gadget_is_superspeed(gadget)) { ++ unsigned max_burst; ++ ++ fsg_ss_function[i + FSG_SS_FUNCTION_PRE_EP_ENTRIES] = NULL; ++ ++ /* Calculate bMaxBurst, we know packet size is 1024 */ ++ max_burst = min_t(unsigned, mod_data.buflen / 1024, 15); ++ ++ /* Assume endpoint addresses are the same for both speeds */ ++ fsg_ss_bulk_in_desc.bEndpointAddress = ++ fsg_fs_bulk_in_desc.bEndpointAddress; ++ fsg_ss_bulk_in_comp_desc.bMaxBurst = max_burst; ++ ++ fsg_ss_bulk_out_desc.bEndpointAddress = ++ fsg_fs_bulk_out_desc.bEndpointAddress; ++ fsg_ss_bulk_out_comp_desc.bMaxBurst = max_burst; ++ } ++ ++ if (gadget_is_otg(gadget)) ++ fsg_otg_desc.bmAttributes |= USB_OTG_HNP; ++ ++ rc = -ENOMEM; ++ ++ /* Allocate the request and buffer for endpoint 0 */ ++ fsg->ep0req = req = usb_ep_alloc_request(fsg->ep0, GFP_KERNEL); ++ if (!req) ++ goto out; ++ req->buf = kmalloc(EP0_BUFSIZE, GFP_KERNEL); ++ if (!req->buf) ++ goto out; ++ req->complete = ep0_complete; ++ ++ /* Allocate the data buffers */ ++ for (i = 0; i < fsg_num_buffers; ++i) { ++ struct fsg_buffhd *bh = &fsg->buffhds[i]; ++ ++ /* Allocate for the bulk-in endpoint. We assume that ++ * the buffer will also work with the bulk-out (and ++ * interrupt-in) endpoint. */ ++ bh->buf = kmalloc(mod_data.buflen, GFP_KERNEL); ++ if (!bh->buf) ++ goto out; ++ bh->next = bh + 1; ++ } ++ fsg->buffhds[fsg_num_buffers - 1].next = &fsg->buffhds[0]; ++ ++ /* This should reflect the actual gadget power source */ ++ usb_gadget_set_selfpowered(gadget); ++ ++ snprintf(fsg_string_manufacturer, sizeof fsg_string_manufacturer, ++ "%s %s with %s", ++ init_utsname()->sysname, init_utsname()->release, ++ gadget->name); ++ ++ fsg->thread_task = kthread_create(fsg_main_thread, fsg, ++ "file-storage-gadget"); ++ if (IS_ERR(fsg->thread_task)) { ++ rc = PTR_ERR(fsg->thread_task); ++ goto out; ++ } ++ ++ INFO(fsg, DRIVER_DESC ", version: " DRIVER_VERSION "\n"); ++ INFO(fsg, "NOTE: This driver is deprecated. " ++ "Consider using g_mass_storage instead.\n"); ++ INFO(fsg, "Number of LUNs=%d\n", fsg->nluns); ++ ++ pathbuf = kmalloc(PATH_MAX, GFP_KERNEL); ++ for (i = 0; i < fsg->nluns; ++i) { ++ curlun = &fsg->luns[i]; ++ if (fsg_lun_is_open(curlun)) { ++ p = NULL; ++ if (pathbuf) { ++ p = d_path(&curlun->filp->f_path, ++ pathbuf, PATH_MAX); ++ if (IS_ERR(p)) ++ p = NULL; ++ } ++ LINFO(curlun, "ro=%d, nofua=%d, file: %s\n", ++ curlun->ro, curlun->nofua, (p ? p : "(error)")); ++ } ++ } ++ kfree(pathbuf); ++ ++ DBG(fsg, "transport=%s (x%02x)\n", ++ mod_data.transport_name, mod_data.transport_type); ++ DBG(fsg, "protocol=%s (x%02x)\n", ++ mod_data.protocol_name, mod_data.protocol_type); ++ DBG(fsg, "VendorID=x%04x, ProductID=x%04x, Release=x%04x\n", ++ mod_data.vendor, mod_data.product, mod_data.release); ++ DBG(fsg, "removable=%d, stall=%d, cdrom=%d, buflen=%u\n", ++ mod_data.removable, mod_data.can_stall, ++ mod_data.cdrom, mod_data.buflen); ++ DBG(fsg, "I/O thread pid: %d\n", task_pid_nr(fsg->thread_task)); ++ ++ set_bit(REGISTERED, &fsg->atomic_bitflags); ++ ++ /* Tell the thread to start working */ ++ wake_up_process(fsg->thread_task); ++ return 0; ++ ++autoconf_fail: ++ ERROR(fsg, "unable to autoconfigure all endpoints\n"); ++ rc = -ENOTSUPP; ++ ++out: ++ fsg->state = FSG_STATE_TERMINATED; // The thread is dead ++ fsg_unbind(gadget); ++ complete(&fsg->thread_notifier); ++ return rc; ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++static void fsg_suspend(struct usb_gadget *gadget) ++{ ++ struct fsg_dev *fsg = get_gadget_data(gadget); ++ ++ DBG(fsg, "suspend\n"); ++ set_bit(SUSPENDED, &fsg->atomic_bitflags); ++} ++ ++static void fsg_resume(struct usb_gadget *gadget) ++{ ++ struct fsg_dev *fsg = get_gadget_data(gadget); ++ ++ DBG(fsg, "resume\n"); ++ clear_bit(SUSPENDED, &fsg->atomic_bitflags); ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++static struct usb_gadget_driver fsg_driver = { ++ .max_speed = USB_SPEED_SUPER, ++ .function = (char *) fsg_string_product, ++ .unbind = fsg_unbind, ++ .disconnect = fsg_disconnect, ++ .setup = fsg_setup, ++ .suspend = fsg_suspend, ++ .resume = fsg_resume, ++ ++ .driver = { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ // .release = ... ++ // .suspend = ... ++ // .resume = ... ++ }, ++}; ++ ++ ++static int __init fsg_alloc(void) ++{ ++ struct fsg_dev *fsg; ++ ++ fsg = kzalloc(sizeof *fsg + ++ fsg_num_buffers * sizeof *(fsg->buffhds), GFP_KERNEL); ++ ++ if (!fsg) ++ return -ENOMEM; ++ spin_lock_init(&fsg->lock); ++ init_rwsem(&fsg->filesem); ++ kref_init(&fsg->ref); ++ init_completion(&fsg->thread_notifier); ++ ++ the_fsg = fsg; ++ return 0; ++} ++ ++ ++static int __init fsg_init(void) ++{ ++ int rc; ++ struct fsg_dev *fsg; ++ ++ rc = fsg_num_buffers_validate(); ++ if (rc != 0) ++ return rc; ++ ++ if ((rc = fsg_alloc()) != 0) ++ return rc; ++ fsg = the_fsg; ++ if ((rc = usb_gadget_probe_driver(&fsg_driver, fsg_bind)) != 0) ++ kref_put(&fsg->ref, fsg_release); ++ return rc; ++} ++module_init(fsg_init); ++ ++ ++static void __exit fsg_cleanup(void) ++{ ++ struct fsg_dev *fsg = the_fsg; ++ ++ /* Unregister the driver iff the thread hasn't already done so */ ++ if (test_and_clear_bit(REGISTERED, &fsg->atomic_bitflags)) ++ usb_gadget_unregister_driver(&fsg_driver); ++ ++ /* Wait for the thread to finish up */ ++ wait_for_completion(&fsg->thread_notifier); ++ ++ kref_put(&fsg->ref, fsg_release); ++} ++module_exit(fsg_cleanup); +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/changes.txt linux-rpi/drivers/usb/host/dwc_common_port/changes.txt +--- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/changes.txt 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_common_port/changes.txt 2015-11-29 09:42:39.915098960 +0100 +@@ -0,0 +1,174 @@ ++ ++dwc_read_reg32() and friends now take an additional parameter, a pointer to an ++IO context struct. The IO context struct should live in an os-dependent struct ++in your driver. As an example, the dwc_usb3 driver has an os-dependent struct ++named 'os_dep' embedded in the main device struct. So there these calls look ++like this: ++ ++ dwc_read_reg32(&usb3_dev->os_dep.ioctx, &pcd->dev_global_regs->dcfg); ++ ++ dwc_write_reg32(&usb3_dev->os_dep.ioctx, ++ &pcd->dev_global_regs->dcfg, 0); ++ ++Note that for the existing Linux driver ports, it is not necessary to actually ++define the 'ioctx' member in the os-dependent struct. Since Linux does not ++require an IO context, its macros for dwc_read_reg32() and friends do not ++use the context pointer, so it is optimized away by the compiler. But it is ++necessary to add the pointer parameter to all of the call sites, to be ready ++for any future ports (such as FreeBSD) which do require an IO context. ++ ++ ++Similarly, dwc_alloc(), dwc_alloc_atomic(), dwc_strdup(), and dwc_free() now ++take an additional parameter, a pointer to a memory context. Examples: ++ ++ addr = dwc_alloc(&usb3_dev->os_dep.memctx, size); ++ ++ dwc_free(&usb3_dev->os_dep.memctx, addr); ++ ++Again, for the Linux ports, it is not necessary to actually define the memctx ++member, but it is necessary to add the pointer parameter to all of the call ++sites. ++ ++ ++Same for dwc_dma_alloc() and dwc_dma_free(). Examples: ++ ++ virt_addr = dwc_dma_alloc(&usb3_dev->os_dep.dmactx, size, &phys_addr); ++ ++ dwc_dma_free(&usb3_dev->os_dep.dmactx, size, virt_addr, phys_addr); ++ ++ ++Same for dwc_mutex_alloc() and dwc_mutex_free(). Examples: ++ ++ mutex = dwc_mutex_alloc(&usb3_dev->os_dep.mtxctx); ++ ++ dwc_mutex_free(&usb3_dev->os_dep.mtxctx, mutex); ++ ++ ++Same for dwc_spinlock_alloc() and dwc_spinlock_free(). Examples: ++ ++ lock = dwc_spinlock_alloc(&usb3_dev->osdep.splctx); ++ ++ dwc_spinlock_free(&usb3_dev->osdep.splctx, lock); ++ ++ ++Same for dwc_timer_alloc(). Example: ++ ++ timer = dwc_timer_alloc(&usb3_dev->os_dep.tmrctx, "dwc_usb3_tmr1", ++ cb_func, cb_data); ++ ++ ++Same for dwc_waitq_alloc(). Example: ++ ++ waitq = dwc_waitq_alloc(&usb3_dev->os_dep.wtqctx); ++ ++ ++Same for dwc_thread_run(). Example: ++ ++ thread = dwc_thread_run(&usb3_dev->os_dep.thdctx, func, ++ "dwc_usb3_thd1", data); ++ ++ ++Same for dwc_workq_alloc(). Example: ++ ++ workq = dwc_workq_alloc(&usb3_dev->osdep.wkqctx, "dwc_usb3_wkq1"); ++ ++ ++Same for dwc_task_alloc(). Example: ++ ++ task = dwc_task_alloc(&usb3_dev->os_dep.tskctx, "dwc_usb3_tsk1", ++ cb_func, cb_data); ++ ++ ++In addition to the context pointer additions, a few core functions have had ++other changes made to their parameters: ++ ++The 'flags' parameter to dwc_spinlock_irqsave() and dwc_spinunlock_irqrestore() ++has been changed from a uint64_t to a dwc_irqflags_t. ++ ++dwc_thread_should_stop() now takes a 'dwc_thread_t *' parameter, because the ++FreeBSD equivalent of that function requires it. ++ ++And, in addition to the context pointer, dwc_task_alloc() also adds a ++'char *name' parameter, to be consistent with dwc_thread_run() and ++dwc_workq_alloc(), and because the FreeBSD equivalent of that function ++requires a unique name. ++ ++ ++Here is a complete list of the core functions that now take a pointer to a ++context as their first parameter: ++ ++ dwc_read_reg32 ++ dwc_read_reg64 ++ dwc_write_reg32 ++ dwc_write_reg64 ++ dwc_modify_reg32 ++ dwc_modify_reg64 ++ dwc_alloc ++ dwc_alloc_atomic ++ dwc_strdup ++ dwc_free ++ dwc_dma_alloc ++ dwc_dma_free ++ dwc_mutex_alloc ++ dwc_mutex_free ++ dwc_spinlock_alloc ++ dwc_spinlock_free ++ dwc_timer_alloc ++ dwc_waitq_alloc ++ dwc_thread_run ++ dwc_workq_alloc ++ dwc_task_alloc Also adds a 'char *name' as its 2nd parameter ++ ++And here are the core functions that have other changes to their parameters: ++ ++ dwc_spinlock_irqsave 'flags' param is now a 'dwc_irqflags_t *' ++ dwc_spinunlock_irqrestore 'flags' param is now a 'dwc_irqflags_t' ++ dwc_thread_should_stop Adds a 'dwc_thread_t *' parameter ++ ++ ++ ++The changes to the core functions also require some of the other library ++functions to change: ++ ++ dwc_cc_if_alloc() and dwc_cc_if_free() now take a 'void *memctx' ++ (for memory allocation) as the 1st param and a 'void *mtxctx' ++ (for mutex allocation) as the 2nd param. ++ ++ dwc_cc_clear(), dwc_cc_add(), dwc_cc_change(), dwc_cc_remove(), ++ dwc_cc_data_for_save(), and dwc_cc_restore_from_data() now take a ++ 'void *memctx' as the 1st param. ++ ++ dwc_dh_modpow(), dwc_dh_pk(), and dwc_dh_derive_keys() now take a ++ 'void *memctx' as the 1st param. ++ ++ dwc_modpow() now takes a 'void *memctx' as the 1st param. ++ ++ dwc_alloc_notification_manager() now takes a 'void *memctx' as the ++ 1st param and a 'void *wkqctx' (for work queue allocation) as the 2nd ++ param, and also now returns an integer value that is non-zero if ++ allocation of its data structures or work queue fails. ++ ++ dwc_register_notifier() now takes a 'void *memctx' as the 1st param. ++ ++ dwc_memory_debug_start() now takes a 'void *mem_ctx' as the first ++ param, and also now returns an integer value that is non-zero if ++ allocation of its data structures fails. ++ ++ ++ ++Other miscellaneous changes: ++ ++The DEBUG_MEMORY and DEBUG_REGS #define's have been renamed to ++DWC_DEBUG_MEMORY and DWC_DEBUG_REGS. ++ ++The following #define's have been added to allow selectively compiling library ++features: ++ ++ DWC_CCLIB ++ DWC_CRYPTOLIB ++ DWC_NOTIFYLIB ++ DWC_UTFLIB ++ ++A DWC_LIBMODULE #define has also been added. If this is not defined, then the ++module code in dwc_common_linux.c is not compiled in. This allows linking the ++library code directly into a driver module, instead of as a standalone module. +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/doc/doxygen.cfg linux-rpi/drivers/usb/host/dwc_common_port/doc/doxygen.cfg +--- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/doc/doxygen.cfg 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_common_port/doc/doxygen.cfg 2015-11-29 09:42:39.915098960 +0100 +@@ -0,0 +1,270 @@ ++# Doxyfile 1.4.5 ++ ++#--------------------------------------------------------------------------- ++# Project related configuration options ++#--------------------------------------------------------------------------- ++PROJECT_NAME = "Synopsys DWC Portability and Common Library for UWB" ++PROJECT_NUMBER = ++OUTPUT_DIRECTORY = doc ++CREATE_SUBDIRS = NO ++OUTPUT_LANGUAGE = English ++BRIEF_MEMBER_DESC = YES ++REPEAT_BRIEF = YES ++ABBREVIATE_BRIEF = "The $name class" \ ++ "The $name widget" \ ++ "The $name file" \ ++ is \ ++ provides \ ++ specifies \ ++ contains \ ++ represents \ ++ a \ ++ an \ ++ the ++ALWAYS_DETAILED_SEC = YES ++INLINE_INHERITED_MEMB = NO ++FULL_PATH_NAMES = NO ++STRIP_FROM_PATH = .. ++STRIP_FROM_INC_PATH = ++SHORT_NAMES = NO ++JAVADOC_AUTOBRIEF = YES ++MULTILINE_CPP_IS_BRIEF = NO ++DETAILS_AT_TOP = YES ++INHERIT_DOCS = YES ++SEPARATE_MEMBER_PAGES = NO ++TAB_SIZE = 8 ++ALIASES = ++OPTIMIZE_OUTPUT_FOR_C = YES ++OPTIMIZE_OUTPUT_JAVA = NO ++BUILTIN_STL_SUPPORT = NO ++DISTRIBUTE_GROUP_DOC = NO ++SUBGROUPING = NO ++#--------------------------------------------------------------------------- ++# Build related configuration options ++#--------------------------------------------------------------------------- ++EXTRACT_ALL = NO ++EXTRACT_PRIVATE = NO ++EXTRACT_STATIC = YES ++EXTRACT_LOCAL_CLASSES = NO ++EXTRACT_LOCAL_METHODS = NO ++HIDE_UNDOC_MEMBERS = NO ++HIDE_UNDOC_CLASSES = NO ++HIDE_FRIEND_COMPOUNDS = NO ++HIDE_IN_BODY_DOCS = NO ++INTERNAL_DOCS = NO ++CASE_SENSE_NAMES = YES ++HIDE_SCOPE_NAMES = NO ++SHOW_INCLUDE_FILES = NO ++INLINE_INFO = YES ++SORT_MEMBER_DOCS = NO ++SORT_BRIEF_DOCS = NO ++SORT_BY_SCOPE_NAME = NO ++GENERATE_TODOLIST = YES ++GENERATE_TESTLIST = YES ++GENERATE_BUGLIST = YES ++GENERATE_DEPRECATEDLIST= YES ++ENABLED_SECTIONS = ++MAX_INITIALIZER_LINES = 30 ++SHOW_USED_FILES = YES ++SHOW_DIRECTORIES = YES ++FILE_VERSION_FILTER = ++#--------------------------------------------------------------------------- ++# configuration options related to warning and progress messages ++#--------------------------------------------------------------------------- ++QUIET = YES ++WARNINGS = YES ++WARN_IF_UNDOCUMENTED = NO ++WARN_IF_DOC_ERROR = YES ++WARN_NO_PARAMDOC = YES ++WARN_FORMAT = "$file:$line: $text" ++WARN_LOGFILE = ++#--------------------------------------------------------------------------- ++# configuration options related to the input files ++#--------------------------------------------------------------------------- ++INPUT = . ++FILE_PATTERNS = *.c \ ++ *.cc \ ++ *.cxx \ ++ *.cpp \ ++ *.c++ \ ++ *.d \ ++ *.java \ ++ *.ii \ ++ *.ixx \ ++ *.ipp \ ++ *.i++ \ ++ *.inl \ ++ *.h \ ++ *.hh \ ++ *.hxx \ ++ *.hpp \ ++ *.h++ \ ++ *.idl \ ++ *.odl \ ++ *.cs \ ++ *.php \ ++ *.php3 \ ++ *.inc \ ++ *.m \ ++ *.mm \ ++ *.dox \ ++ *.py \ ++ *.C \ ++ *.CC \ ++ *.C++ \ ++ *.II \ ++ *.I++ \ ++ *.H \ ++ *.HH \ ++ *.H++ \ ++ *.CS \ ++ *.PHP \ ++ *.PHP3 \ ++ *.M \ ++ *.MM \ ++ *.PY ++RECURSIVE = NO ++EXCLUDE = ++EXCLUDE_SYMLINKS = NO ++EXCLUDE_PATTERNS = ++EXAMPLE_PATH = ++EXAMPLE_PATTERNS = * ++EXAMPLE_RECURSIVE = NO ++IMAGE_PATH = ++INPUT_FILTER = ++FILTER_PATTERNS = ++FILTER_SOURCE_FILES = NO ++#--------------------------------------------------------------------------- ++# configuration options related to source browsing ++#--------------------------------------------------------------------------- ++SOURCE_BROWSER = NO ++INLINE_SOURCES = NO ++STRIP_CODE_COMMENTS = YES ++REFERENCED_BY_RELATION = YES ++REFERENCES_RELATION = YES ++USE_HTAGS = NO ++VERBATIM_HEADERS = NO ++#--------------------------------------------------------------------------- ++# configuration options related to the alphabetical class index ++#--------------------------------------------------------------------------- ++ALPHABETICAL_INDEX = NO ++COLS_IN_ALPHA_INDEX = 5 ++IGNORE_PREFIX = ++#--------------------------------------------------------------------------- ++# configuration options related to the HTML output ++#--------------------------------------------------------------------------- ++GENERATE_HTML = YES ++HTML_OUTPUT = html ++HTML_FILE_EXTENSION = .html ++HTML_HEADER = ++HTML_FOOTER = ++HTML_STYLESHEET = ++HTML_ALIGN_MEMBERS = YES ++GENERATE_HTMLHELP = NO ++CHM_FILE = ++HHC_LOCATION = ++GENERATE_CHI = NO ++BINARY_TOC = NO ++TOC_EXPAND = NO ++DISABLE_INDEX = NO ++ENUM_VALUES_PER_LINE = 4 ++GENERATE_TREEVIEW = YES ++TREEVIEW_WIDTH = 250 ++#--------------------------------------------------------------------------- ++# configuration options related to the LaTeX output ++#--------------------------------------------------------------------------- ++GENERATE_LATEX = NO ++LATEX_OUTPUT = latex ++LATEX_CMD_NAME = latex ++MAKEINDEX_CMD_NAME = makeindex ++COMPACT_LATEX = NO ++PAPER_TYPE = a4wide ++EXTRA_PACKAGES = ++LATEX_HEADER = ++PDF_HYPERLINKS = NO ++USE_PDFLATEX = NO ++LATEX_BATCHMODE = NO ++LATEX_HIDE_INDICES = NO ++#--------------------------------------------------------------------------- ++# configuration options related to the RTF output ++#--------------------------------------------------------------------------- ++GENERATE_RTF = NO ++RTF_OUTPUT = rtf ++COMPACT_RTF = NO ++RTF_HYPERLINKS = NO ++RTF_STYLESHEET_FILE = ++RTF_EXTENSIONS_FILE = ++#--------------------------------------------------------------------------- ++# configuration options related to the man page output ++#--------------------------------------------------------------------------- ++GENERATE_MAN = NO ++MAN_OUTPUT = man ++MAN_EXTENSION = .3 ++MAN_LINKS = NO ++#--------------------------------------------------------------------------- ++# configuration options related to the XML output ++#--------------------------------------------------------------------------- ++GENERATE_XML = NO ++XML_OUTPUT = xml ++XML_SCHEMA = ++XML_DTD = ++XML_PROGRAMLISTING = YES ++#--------------------------------------------------------------------------- ++# configuration options for the AutoGen Definitions output ++#--------------------------------------------------------------------------- ++GENERATE_AUTOGEN_DEF = NO ++#--------------------------------------------------------------------------- ++# configuration options related to the Perl module output ++#--------------------------------------------------------------------------- ++GENERATE_PERLMOD = NO ++PERLMOD_LATEX = NO ++PERLMOD_PRETTY = YES ++PERLMOD_MAKEVAR_PREFIX = ++#--------------------------------------------------------------------------- ++# Configuration options related to the preprocessor ++#--------------------------------------------------------------------------- ++ENABLE_PREPROCESSING = YES ++MACRO_EXPANSION = NO ++EXPAND_ONLY_PREDEF = NO ++SEARCH_INCLUDES = YES ++INCLUDE_PATH = ++INCLUDE_FILE_PATTERNS = ++PREDEFINED = DEBUG DEBUG_MEMORY ++EXPAND_AS_DEFINED = ++SKIP_FUNCTION_MACROS = YES ++#--------------------------------------------------------------------------- ++# Configuration::additions related to external references ++#--------------------------------------------------------------------------- ++TAGFILES = ++GENERATE_TAGFILE = ++ALLEXTERNALS = NO ++EXTERNAL_GROUPS = YES ++PERL_PATH = /usr/bin/perl ++#--------------------------------------------------------------------------- ++# Configuration options related to the dot tool ++#--------------------------------------------------------------------------- ++CLASS_DIAGRAMS = YES ++HIDE_UNDOC_RELATIONS = YES ++HAVE_DOT = NO ++CLASS_GRAPH = YES ++COLLABORATION_GRAPH = YES ++GROUP_GRAPHS = YES ++UML_LOOK = NO ++TEMPLATE_RELATIONS = NO ++INCLUDE_GRAPH = NO ++INCLUDED_BY_GRAPH = YES ++CALL_GRAPH = NO ++GRAPHICAL_HIERARCHY = YES ++DIRECTORY_GRAPH = YES ++DOT_IMAGE_FORMAT = png ++DOT_PATH = ++DOTFILE_DIRS = ++MAX_DOT_GRAPH_DEPTH = 1000 ++DOT_TRANSPARENT = NO ++DOT_MULTI_TARGETS = NO ++GENERATE_LEGEND = YES ++DOT_CLEANUP = YES ++#--------------------------------------------------------------------------- ++# Configuration::additions related to the search engine ++#--------------------------------------------------------------------------- ++SEARCHENGINE = NO +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_cc.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_cc.c +--- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_cc.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_cc.c 2015-11-29 09:42:39.915098960 +0100 +@@ -0,0 +1,532 @@ ++/* ========================================================================= ++ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_cc.c $ ++ * $Revision: #4 $ ++ * $Date: 2010/11/04 $ ++ * $Change: 1621692 $ ++ * ++ * Synopsys Portability Library Software and documentation ++ * (hereinafter, "Software") is an Unsupported proprietary work of ++ * Synopsys, Inc. unless otherwise expressly agreed to in writing ++ * between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for ++ * Licensed Product with Synopsys or any supplement thereto. You are ++ * permitted to use and redistribute this Software in source and binary ++ * forms, with or without modification, provided that redistributions ++ * of source code must retain this notice. You may not view, use, ++ * disclose, copy or distribute this file or any information contained ++ * herein except pursuant to this license grant from Synopsys. If you ++ * do not agree with this notice, including the disclaimer below, then ++ * you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ++ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL ++ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY ++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE ++ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================= */ ++#ifdef DWC_CCLIB ++ ++#include "dwc_cc.h" ++ ++typedef struct dwc_cc ++{ ++ uint32_t uid; ++ uint8_t chid[16]; ++ uint8_t cdid[16]; ++ uint8_t ck[16]; ++ uint8_t *name; ++ uint8_t length; ++ DWC_CIRCLEQ_ENTRY(dwc_cc) list_entry; ++} dwc_cc_t; ++ ++DWC_CIRCLEQ_HEAD(context_list, dwc_cc); ++ ++/** The main structure for CC management. */ ++struct dwc_cc_if ++{ ++ dwc_mutex_t *mutex; ++ char *filename; ++ ++ unsigned is_host:1; ++ ++ dwc_notifier_t *notifier; ++ ++ struct context_list list; ++}; ++ ++#ifdef DEBUG ++static inline void dump_bytes(char *name, uint8_t *bytes, int len) ++{ ++ int i; ++ DWC_PRINTF("%s: ", name); ++ for (i=0; ilength = length; ++ cc->name = dwc_alloc(mem_ctx, length); ++ if (!cc->name) { ++ dwc_free(mem_ctx, cc); ++ return NULL; ++ } ++ ++ DWC_MEMCPY(cc->name, name, length); ++ } ++ ++ return cc; ++} ++ ++static void free_cc(void *mem_ctx, dwc_cc_t *cc) ++{ ++ if (cc->name) { ++ dwc_free(mem_ctx, cc->name); ++ } ++ dwc_free(mem_ctx, cc); ++} ++ ++static uint32_t next_uid(dwc_cc_if_t *cc_if) ++{ ++ uint32_t uid = 0; ++ dwc_cc_t *cc; ++ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) { ++ if (cc->uid > uid) { ++ uid = cc->uid; ++ } ++ } ++ ++ if (uid == 0) { ++ uid = 255; ++ } ++ ++ return uid + 1; ++} ++ ++static dwc_cc_t *cc_find(dwc_cc_if_t *cc_if, uint32_t uid) ++{ ++ dwc_cc_t *cc; ++ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) { ++ if (cc->uid == uid) { ++ return cc; ++ } ++ } ++ return NULL; ++} ++ ++static unsigned int cc_data_size(dwc_cc_if_t *cc_if) ++{ ++ unsigned int size = 0; ++ dwc_cc_t *cc; ++ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) { ++ size += (48 + 1); ++ if (cc->name) { ++ size += cc->length; ++ } ++ } ++ return size; ++} ++ ++static uint32_t cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid) ++{ ++ uint32_t uid = 0; ++ dwc_cc_t *cc; ++ ++ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) { ++ if (DWC_MEMCMP(cc->chid, chid, 16) == 0) { ++ uid = cc->uid; ++ break; ++ } ++ } ++ return uid; ++} ++static uint32_t cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid) ++{ ++ uint32_t uid = 0; ++ dwc_cc_t *cc; ++ ++ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) { ++ if (DWC_MEMCMP(cc->cdid, cdid, 16) == 0) { ++ uid = cc->uid; ++ break; ++ } ++ } ++ return uid; ++} ++ ++/* Internal cc_add */ ++static int32_t cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid, ++ uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length) ++{ ++ dwc_cc_t *cc; ++ uint32_t uid; ++ ++ if (cc_if->is_host) { ++ uid = cc_match_cdid(cc_if, cdid); ++ } ++ else { ++ uid = cc_match_chid(cc_if, chid); ++ } ++ ++ if (uid) { ++ DWC_DEBUGC("Replacing previous connection context id=%d name=%p name_len=%d", uid, name, length); ++ cc = cc_find(cc_if, uid); ++ } ++ else { ++ cc = alloc_cc(mem_ctx, name, length); ++ cc->uid = next_uid(cc_if); ++ DWC_CIRCLEQ_INSERT_TAIL(&cc_if->list, cc, list_entry); ++ } ++ ++ DWC_MEMCPY(&(cc->chid[0]), chid, 16); ++ DWC_MEMCPY(&(cc->cdid[0]), cdid, 16); ++ DWC_MEMCPY(&(cc->ck[0]), ck, 16); ++ ++ DWC_DEBUGC("Added connection context id=%d name=%p name_len=%d", cc->uid, name, length); ++ dump_bytes("CHID", cc->chid, 16); ++ dump_bytes("CDID", cc->cdid, 16); ++ dump_bytes("CK", cc->ck, 16); ++ return cc->uid; ++} ++ ++/* Internal cc_clear */ ++static void cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if) ++{ ++ while (!DWC_CIRCLEQ_EMPTY(&cc_if->list)) { ++ dwc_cc_t *cc = DWC_CIRCLEQ_FIRST(&cc_if->list); ++ DWC_CIRCLEQ_REMOVE_INIT(&cc_if->list, cc, list_entry); ++ free_cc(mem_ctx, cc); ++ } ++} ++ ++dwc_cc_if_t *dwc_cc_if_alloc(void *mem_ctx, void *mtx_ctx, ++ dwc_notifier_t *notifier, unsigned is_host) ++{ ++ dwc_cc_if_t *cc_if = NULL; ++ ++ /* Allocate a common_cc_if structure */ ++ cc_if = dwc_alloc(mem_ctx, sizeof(dwc_cc_if_t)); ++ ++ if (!cc_if) ++ return NULL; ++ ++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)) ++ DWC_MUTEX_ALLOC_LINUX_DEBUG(cc_if->mutex); ++#else ++ cc_if->mutex = dwc_mutex_alloc(mtx_ctx); ++#endif ++ if (!cc_if->mutex) { ++ dwc_free(mem_ctx, cc_if); ++ return NULL; ++ } ++ ++ DWC_CIRCLEQ_INIT(&cc_if->list); ++ cc_if->is_host = is_host; ++ cc_if->notifier = notifier; ++ return cc_if; ++} ++ ++void dwc_cc_if_free(void *mem_ctx, void *mtx_ctx, dwc_cc_if_t *cc_if) ++{ ++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)) ++ DWC_MUTEX_FREE(cc_if->mutex); ++#else ++ dwc_mutex_free(mtx_ctx, cc_if->mutex); ++#endif ++ cc_clear(mem_ctx, cc_if); ++ dwc_free(mem_ctx, cc_if); ++} ++ ++static void cc_changed(dwc_cc_if_t *cc_if) ++{ ++ if (cc_if->notifier) { ++ dwc_notify(cc_if->notifier, DWC_CC_LIST_CHANGED_NOTIFICATION, cc_if); ++ } ++} ++ ++void dwc_cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if) ++{ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ cc_clear(mem_ctx, cc_if); ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ cc_changed(cc_if); ++} ++ ++int32_t dwc_cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid, ++ uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length) ++{ ++ uint32_t uid; ++ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ uid = cc_add(mem_ctx, cc_if, chid, cdid, ck, name, length); ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ cc_changed(cc_if); ++ ++ return uid; ++} ++ ++void dwc_cc_change(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id, uint8_t *chid, ++ uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length) ++{ ++ dwc_cc_t* cc; ++ ++ DWC_DEBUGC("Change connection context %d", id); ++ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ cc = cc_find(cc_if, id); ++ if (!cc) { ++ DWC_ERROR("Uid %d not found in cc list\n", id); ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ return; ++ } ++ ++ if (chid) { ++ DWC_MEMCPY(&(cc->chid[0]), chid, 16); ++ } ++ if (cdid) { ++ DWC_MEMCPY(&(cc->cdid[0]), cdid, 16); ++ } ++ if (ck) { ++ DWC_MEMCPY(&(cc->ck[0]), ck, 16); ++ } ++ ++ if (name) { ++ if (cc->name) { ++ dwc_free(mem_ctx, cc->name); ++ } ++ cc->name = dwc_alloc(mem_ctx, length); ++ if (!cc->name) { ++ DWC_ERROR("Out of memory in dwc_cc_change()\n"); ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ return; ++ } ++ cc->length = length; ++ DWC_MEMCPY(cc->name, name, length); ++ } ++ ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ ++ cc_changed(cc_if); ++ ++ DWC_DEBUGC("Changed connection context id=%d\n", id); ++ dump_bytes("New CHID", cc->chid, 16); ++ dump_bytes("New CDID", cc->cdid, 16); ++ dump_bytes("New CK", cc->ck, 16); ++} ++ ++void dwc_cc_remove(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id) ++{ ++ dwc_cc_t *cc; ++ ++ DWC_DEBUGC("Removing connection context %d", id); ++ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ cc = cc_find(cc_if, id); ++ if (!cc) { ++ DWC_ERROR("Uid %d not found in cc list\n", id); ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ return; ++ } ++ ++ DWC_CIRCLEQ_REMOVE_INIT(&cc_if->list, cc, list_entry); ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ free_cc(mem_ctx, cc); ++ ++ cc_changed(cc_if); ++} ++ ++uint8_t *dwc_cc_data_for_save(void *mem_ctx, dwc_cc_if_t *cc_if, unsigned int *length) ++{ ++ uint8_t *buf, *x; ++ uint8_t zero = 0; ++ dwc_cc_t *cc; ++ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ *length = cc_data_size(cc_if); ++ if (!(*length)) { ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ return NULL; ++ } ++ ++ DWC_DEBUGC("Creating data for saving (length=%d)", *length); ++ ++ buf = dwc_alloc(mem_ctx, *length); ++ if (!buf) { ++ *length = 0; ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ return NULL; ++ } ++ ++ x = buf; ++ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) { ++ DWC_MEMCPY(x, cc->chid, 16); ++ x += 16; ++ DWC_MEMCPY(x, cc->cdid, 16); ++ x += 16; ++ DWC_MEMCPY(x, cc->ck, 16); ++ x += 16; ++ if (cc->name) { ++ DWC_MEMCPY(x, &cc->length, 1); ++ x += 1; ++ DWC_MEMCPY(x, cc->name, cc->length); ++ x += cc->length; ++ } ++ else { ++ DWC_MEMCPY(x, &zero, 1); ++ x += 1; ++ } ++ } ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ ++ return buf; ++} ++ ++void dwc_cc_restore_from_data(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *data, uint32_t length) ++{ ++ uint8_t name_length; ++ uint8_t *name; ++ uint8_t *chid; ++ uint8_t *cdid; ++ uint8_t *ck; ++ uint32_t i = 0; ++ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ cc_clear(mem_ctx, cc_if); ++ ++ while (i < length) { ++ chid = &data[i]; ++ i += 16; ++ cdid = &data[i]; ++ i += 16; ++ ck = &data[i]; ++ i += 16; ++ ++ name_length = data[i]; ++ i ++; ++ ++ if (name_length) { ++ name = &data[i]; ++ i += name_length; ++ } ++ else { ++ name = NULL; ++ } ++ ++ /* check to see if we haven't overflown the buffer */ ++ if (i > length) { ++ DWC_ERROR("Data format error while attempting to load CCs " ++ "(nlen=%d, iter=%d, buflen=%d).\n", name_length, i, length); ++ break; ++ } ++ ++ cc_add(mem_ctx, cc_if, chid, cdid, ck, name, name_length); ++ } ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ ++ cc_changed(cc_if); ++} ++ ++uint32_t dwc_cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid) ++{ ++ uint32_t uid = 0; ++ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ uid = cc_match_chid(cc_if, chid); ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ return uid; ++} ++uint32_t dwc_cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid) ++{ ++ uint32_t uid = 0; ++ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ uid = cc_match_cdid(cc_if, cdid); ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ return uid; ++} ++ ++uint8_t *dwc_cc_ck(dwc_cc_if_t *cc_if, int32_t id) ++{ ++ uint8_t *ck = NULL; ++ dwc_cc_t *cc; ++ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ cc = cc_find(cc_if, id); ++ if (cc) { ++ ck = cc->ck; ++ } ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ ++ return ck; ++ ++} ++ ++uint8_t *dwc_cc_chid(dwc_cc_if_t *cc_if, int32_t id) ++{ ++ uint8_t *retval = NULL; ++ dwc_cc_t *cc; ++ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ cc = cc_find(cc_if, id); ++ if (cc) { ++ retval = cc->chid; ++ } ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ ++ return retval; ++} ++ ++uint8_t *dwc_cc_cdid(dwc_cc_if_t *cc_if, int32_t id) ++{ ++ uint8_t *retval = NULL; ++ dwc_cc_t *cc; ++ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ cc = cc_find(cc_if, id); ++ if (cc) { ++ retval = cc->cdid; ++ } ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ ++ return retval; ++} ++ ++uint8_t *dwc_cc_name(dwc_cc_if_t *cc_if, int32_t id, uint8_t *length) ++{ ++ uint8_t *retval = NULL; ++ dwc_cc_t *cc; ++ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ *length = 0; ++ cc = cc_find(cc_if, id); ++ if (cc) { ++ *length = cc->length; ++ retval = cc->name; ++ } ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ ++ return retval; ++} ++ ++#endif /* DWC_CCLIB */ +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_cc.h linux-rpi/drivers/usb/host/dwc_common_port/dwc_cc.h +--- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_cc.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_cc.h 2015-11-29 09:42:39.915098960 +0100 +@@ -0,0 +1,224 @@ ++/* ========================================================================= ++ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_cc.h $ ++ * $Revision: #4 $ ++ * $Date: 2010/09/28 $ ++ * $Change: 1596182 $ ++ * ++ * Synopsys Portability Library Software and documentation ++ * (hereinafter, "Software") is an Unsupported proprietary work of ++ * Synopsys, Inc. unless otherwise expressly agreed to in writing ++ * between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for ++ * Licensed Product with Synopsys or any supplement thereto. You are ++ * permitted to use and redistribute this Software in source and binary ++ * forms, with or without modification, provided that redistributions ++ * of source code must retain this notice. You may not view, use, ++ * disclose, copy or distribute this file or any information contained ++ * herein except pursuant to this license grant from Synopsys. If you ++ * do not agree with this notice, including the disclaimer below, then ++ * you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ++ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL ++ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY ++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE ++ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================= */ ++#ifndef _DWC_CC_H_ ++#define _DWC_CC_H_ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/** @file ++ * ++ * This file defines the Context Context library. ++ * ++ * The main data structure is dwc_cc_if_t which is returned by either the ++ * dwc_cc_if_alloc function or returned by the module to the user via a provided ++ * function. The data structure is opaque and should only be manipulated via the ++ * functions provied in this API. ++ * ++ * It manages a list of connection contexts and operations can be performed to ++ * add, remove, query, search, and change, those contexts. Additionally, ++ * a dwc_notifier_t object can be requested from the manager so that ++ * the user can be notified whenever the context list has changed. ++ */ ++ ++#include "dwc_os.h" ++#include "dwc_list.h" ++#include "dwc_notifier.h" ++ ++ ++/* Notifications */ ++#define DWC_CC_LIST_CHANGED_NOTIFICATION "DWC_CC_LIST_CHANGED_NOTIFICATION" ++ ++struct dwc_cc_if; ++typedef struct dwc_cc_if dwc_cc_if_t; ++ ++ ++/** @name Connection Context Operations */ ++/** @{ */ ++ ++/** This function allocates memory for a dwc_cc_if_t structure, initializes ++ * fields to default values, and returns a pointer to the structure or NULL on ++ * error. */ ++extern dwc_cc_if_t *dwc_cc_if_alloc(void *mem_ctx, void *mtx_ctx, ++ dwc_notifier_t *notifier, unsigned is_host); ++ ++/** Frees the memory for the specified CC structure allocated from ++ * dwc_cc_if_alloc(). */ ++extern void dwc_cc_if_free(void *mem_ctx, void *mtx_ctx, dwc_cc_if_t *cc_if); ++ ++/** Removes all contexts from the connection context list */ ++extern void dwc_cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if); ++ ++/** Adds a connection context (CHID, CK, CDID, Name) to the connection context list. ++ * If a CHID already exists, the CK and name are overwritten. Statistics are ++ * not overwritten. ++ * ++ * @param cc_if The cc_if structure. ++ * @param chid A pointer to the 16-byte CHID. This value will be copied. ++ * @param ck A pointer to the 16-byte CK. This value will be copied. ++ * @param cdid A pointer to the 16-byte CDID. This value will be copied. ++ * @param name An optional host friendly name as defined in the association model ++ * spec. Must be a UTF16-LE unicode string. Can be NULL to indicated no name. ++ * @param length The length othe unicode string. ++ * @return A unique identifier used to refer to this context that is valid for ++ * as long as this context is still in the list. */ ++extern int32_t dwc_cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid, ++ uint8_t *cdid, uint8_t *ck, uint8_t *name, ++ uint8_t length); ++ ++/** Changes the CHID, CK, CDID, or Name values of a connection context in the ++ * list, preserving any accumulated statistics. This would typically be called ++ * if the host decideds to change the context with a SET_CONNECTION request. ++ * ++ * @param cc_if The cc_if structure. ++ * @param id The identifier of the connection context. ++ * @param chid A pointer to the 16-byte CHID. This value will be copied. NULL ++ * indicates no change. ++ * @param cdid A pointer to the 16-byte CDID. This value will be copied. NULL ++ * indicates no change. ++ * @param ck A pointer to the 16-byte CK. This value will be copied. NULL ++ * indicates no change. ++ * @param name Host friendly name UTF16-LE. NULL indicates no change. ++ * @param length Length of name. */ ++extern void dwc_cc_change(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id, ++ uint8_t *chid, uint8_t *cdid, uint8_t *ck, ++ uint8_t *name, uint8_t length); ++ ++/** Remove the specified connection context. ++ * @param cc_if The cc_if structure. ++ * @param id The identifier of the connection context to remove. */ ++extern void dwc_cc_remove(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id); ++ ++/** Get a binary block of data for the connection context list and attributes. ++ * This data can be used by the OS specific driver to save the connection ++ * context list into non-volatile memory. ++ * ++ * @param cc_if The cc_if structure. ++ * @param length Return the length of the data buffer. ++ * @return A pointer to the data buffer. The memory for this buffer should be ++ * freed with DWC_FREE() after use. */ ++extern uint8_t *dwc_cc_data_for_save(void *mem_ctx, dwc_cc_if_t *cc_if, ++ unsigned int *length); ++ ++/** Restore the connection context list from the binary data that was previously ++ * returned from a call to dwc_cc_data_for_save. This can be used by the OS specific ++ * driver to load a connection context list from non-volatile memory. ++ * ++ * @param cc_if The cc_if structure. ++ * @param data The data bytes as returned from dwc_cc_data_for_save. ++ * @param length The length of the data. */ ++extern void dwc_cc_restore_from_data(void *mem_ctx, dwc_cc_if_t *cc_if, ++ uint8_t *data, unsigned int length); ++ ++/** Find the connection context from the specified CHID. ++ * ++ * @param cc_if The cc_if structure. ++ * @param chid A pointer to the CHID data. ++ * @return A non-zero identifier of the connection context if the CHID matches. ++ * Otherwise returns 0. */ ++extern uint32_t dwc_cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid); ++ ++/** Find the connection context from the specified CDID. ++ * ++ * @param cc_if The cc_if structure. ++ * @param cdid A pointer to the CDID data. ++ * @return A non-zero identifier of the connection context if the CHID matches. ++ * Otherwise returns 0. */ ++extern uint32_t dwc_cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid); ++ ++/** Retrieve the CK from the specified connection context. ++ * ++ * @param cc_if The cc_if structure. ++ * @param id The identifier of the connection context. ++ * @return A pointer to the CK data. The memory does not need to be freed. */ ++extern uint8_t *dwc_cc_ck(dwc_cc_if_t *cc_if, int32_t id); ++ ++/** Retrieve the CHID from the specified connection context. ++ * ++ * @param cc_if The cc_if structure. ++ * @param id The identifier of the connection context. ++ * @return A pointer to the CHID data. The memory does not need to be freed. */ ++extern uint8_t *dwc_cc_chid(dwc_cc_if_t *cc_if, int32_t id); ++ ++/** Retrieve the CDID from the specified connection context. ++ * ++ * @param cc_if The cc_if structure. ++ * @param id The identifier of the connection context. ++ * @return A pointer to the CDID data. The memory does not need to be freed. */ ++extern uint8_t *dwc_cc_cdid(dwc_cc_if_t *cc_if, int32_t id); ++ ++extern uint8_t *dwc_cc_name(dwc_cc_if_t *cc_if, int32_t id, uint8_t *length); ++ ++/** Checks a buffer for non-zero. ++ * @param id A pointer to a 16 byte buffer. ++ * @return true if the 16 byte value is non-zero. */ ++static inline unsigned dwc_assoc_is_not_zero_id(uint8_t *id) { ++ int i; ++ for (i=0; i<16; i++) { ++ if (id[i]) return 1; ++ } ++ return 0; ++} ++ ++/** Checks a buffer for zero. ++ * @param id A pointer to a 16 byte buffer. ++ * @return true if the 16 byte value is zero. */ ++static inline unsigned dwc_assoc_is_zero_id(uint8_t *id) { ++ return !dwc_assoc_is_not_zero_id(id); ++} ++ ++/** Prints an ASCII representation for the 16-byte chid, cdid, or ck, into ++ * buffer. */ ++static inline int dwc_print_id_string(char *buffer, uint8_t *id) { ++ char *ptr = buffer; ++ int i; ++ for (i=0; i<16; i++) { ++ ptr += DWC_SPRINTF(ptr, "%02x", id[i]); ++ if (i < 15) { ++ ptr += DWC_SPRINTF(ptr, " "); ++ } ++ } ++ return ptr - buffer; ++} ++ ++/** @} */ ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif /* _DWC_CC_H_ */ +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_common_fbsd.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_common_fbsd.c +--- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_common_fbsd.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_common_fbsd.c 2015-11-29 09:42:39.915098960 +0100 +@@ -0,0 +1,1308 @@ ++#include "dwc_os.h" ++#include "dwc_list.h" ++ ++#ifdef DWC_CCLIB ++# include "dwc_cc.h" ++#endif ++ ++#ifdef DWC_CRYPTOLIB ++# include "dwc_modpow.h" ++# include "dwc_dh.h" ++# include "dwc_crypto.h" ++#endif ++ ++#ifdef DWC_NOTIFYLIB ++# include "dwc_notifier.h" ++#endif ++ ++/* OS-Level Implementations */ ++ ++/* This is the FreeBSD 7.0 kernel implementation of the DWC platform library. */ ++ ++ ++/* MISC */ ++ ++void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size) ++{ ++ return memset(dest, byte, size); ++} ++ ++void *DWC_MEMCPY(void *dest, void const *src, uint32_t size) ++{ ++ return memcpy(dest, src, size); ++} ++ ++void *DWC_MEMMOVE(void *dest, void *src, uint32_t size) ++{ ++ bcopy(src, dest, size); ++ return dest; ++} ++ ++int DWC_MEMCMP(void *m1, void *m2, uint32_t size) ++{ ++ return memcmp(m1, m2, size); ++} ++ ++int DWC_STRNCMP(void *s1, void *s2, uint32_t size) ++{ ++ return strncmp(s1, s2, size); ++} ++ ++int DWC_STRCMP(void *s1, void *s2) ++{ ++ return strcmp(s1, s2); ++} ++ ++int DWC_STRLEN(char const *str) ++{ ++ return strlen(str); ++} ++ ++char *DWC_STRCPY(char *to, char const *from) ++{ ++ return strcpy(to, from); ++} ++ ++char *DWC_STRDUP(char const *str) ++{ ++ int len = DWC_STRLEN(str) + 1; ++ char *new = DWC_ALLOC_ATOMIC(len); ++ ++ if (!new) { ++ return NULL; ++ } ++ ++ DWC_MEMCPY(new, str, len); ++ return new; ++} ++ ++int DWC_ATOI(char *str, int32_t *value) ++{ ++ char *end = NULL; ++ ++ *value = strtol(str, &end, 0); ++ if (*end == '\0') { ++ return 0; ++ } ++ ++ return -1; ++} ++ ++int DWC_ATOUI(char *str, uint32_t *value) ++{ ++ char *end = NULL; ++ ++ *value = strtoul(str, &end, 0); ++ if (*end == '\0') { ++ return 0; ++ } ++ ++ return -1; ++} ++ ++ ++#ifdef DWC_UTFLIB ++/* From usbstring.c */ ++ ++int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len) ++{ ++ int count = 0; ++ u8 c; ++ u16 uchar; ++ ++ /* this insists on correct encodings, though not minimal ones. ++ * BUT it currently rejects legit 4-byte UTF-8 code points, ++ * which need surrogate pairs. (Unicode 3.1 can use them.) ++ */ ++ while (len != 0 && (c = (u8) *s++) != 0) { ++ if (unlikely(c & 0x80)) { ++ // 2-byte sequence: ++ // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx ++ if ((c & 0xe0) == 0xc0) { ++ uchar = (c & 0x1f) << 6; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c; ++ ++ // 3-byte sequence (most CJKV characters): ++ // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx ++ } else if ((c & 0xf0) == 0xe0) { ++ uchar = (c & 0x0f) << 12; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c << 6; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c; ++ ++ /* no bogus surrogates */ ++ if (0xd800 <= uchar && uchar <= 0xdfff) ++ goto fail; ++ ++ // 4-byte sequence (surrogate pairs, currently rare): ++ // 11101110wwwwzzzzyy + 110111yyyyxxxxxx ++ // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx ++ // (uuuuu = wwww + 1) ++ // FIXME accept the surrogate code points (only) ++ } else ++ goto fail; ++ } else ++ uchar = c; ++ put_unaligned (cpu_to_le16 (uchar), cp++); ++ count++; ++ len--; ++ } ++ return count; ++fail: ++ return -1; ++} ++ ++#endif /* DWC_UTFLIB */ ++ ++ ++/* dwc_debug.h */ ++ ++dwc_bool_t DWC_IN_IRQ(void) ++{ ++// return in_irq(); ++ return 0; ++} ++ ++dwc_bool_t DWC_IN_BH(void) ++{ ++// return in_softirq(); ++ return 0; ++} ++ ++void DWC_VPRINTF(char *format, va_list args) ++{ ++ vprintf(format, args); ++} ++ ++int DWC_VSNPRINTF(char *str, int size, char *format, va_list args) ++{ ++ return vsnprintf(str, size, format, args); ++} ++ ++void DWC_PRINTF(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++ ++int DWC_SPRINTF(char *buffer, char *format, ...) ++{ ++ int retval; ++ va_list args; ++ ++ va_start(args, format); ++ retval = vsprintf(buffer, format, args); ++ va_end(args); ++ return retval; ++} ++ ++int DWC_SNPRINTF(char *buffer, int size, char *format, ...) ++{ ++ int retval; ++ va_list args; ++ ++ va_start(args, format); ++ retval = vsnprintf(buffer, size, format, args); ++ va_end(args); ++ return retval; ++} ++ ++void __DWC_WARN(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++ ++void __DWC_ERROR(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++ ++void DWC_EXCEPTION(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++// BUG_ON(1); ??? ++} ++ ++#ifdef DEBUG ++void __DWC_DEBUG(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++#endif ++ ++ ++/* dwc_mem.h */ ++ ++#if 0 ++dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size, ++ uint32_t align, ++ uint32_t alloc) ++{ ++ struct dma_pool *pool = dma_pool_create("Pool", NULL, ++ size, align, alloc); ++ return (dwc_pool_t *)pool; ++} ++ ++void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool) ++{ ++ dma_pool_destroy((struct dma_pool *)pool); ++} ++ ++void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr) ++{ ++// return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr); ++ return dma_pool_alloc((struct dma_pool *)pool, M_WAITOK, dma_addr); ++} ++ ++void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr) ++{ ++ void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr); ++ memset(..); ++} ++ ++void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr) ++{ ++ dma_pool_free(pool, vaddr, daddr); ++} ++#endif ++ ++static void dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) ++{ ++ if (error) ++ return; ++ *(bus_addr_t *)arg = segs[0].ds_addr; ++} ++ ++void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr) ++{ ++ dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx; ++ int error; ++ ++ error = bus_dma_tag_create( ++#if __FreeBSD_version >= 700000 ++ bus_get_dma_tag(dma->dev), /* parent */ ++#else ++ NULL, /* parent */ ++#endif ++ 4, 0, /* alignment, bounds */ ++ BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ ++ BUS_SPACE_MAXADDR, /* highaddr */ ++ NULL, NULL, /* filter, filterarg */ ++ size, /* maxsize */ ++ 1, /* nsegments */ ++ size, /* maxsegsize */ ++ 0, /* flags */ ++ NULL, /* lockfunc */ ++ NULL, /* lockarg */ ++ &dma->dma_tag); ++ if (error) { ++ device_printf(dma->dev, "%s: bus_dma_tag_create failed: %d\n", ++ __func__, error); ++ goto fail_0; ++ } ++ ++ error = bus_dmamem_alloc(dma->dma_tag, &dma->dma_vaddr, ++ BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map); ++ if (error) { ++ device_printf(dma->dev, "%s: bus_dmamem_alloc(%ju) failed: %d\n", ++ __func__, (uintmax_t)size, error); ++ goto fail_1; ++ } ++ ++ dma->dma_paddr = 0; ++ error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, size, ++ dmamap_cb, &dma->dma_paddr, BUS_DMA_NOWAIT); ++ if (error || dma->dma_paddr == 0) { ++ device_printf(dma->dev, "%s: bus_dmamap_load failed: %d\n", ++ __func__, error); ++ goto fail_2; ++ } ++ ++ *dma_addr = dma->dma_paddr; ++ return dma->dma_vaddr; ++ ++fail_2: ++ bus_dmamap_unload(dma->dma_tag, dma->dma_map); ++fail_1: ++ bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); ++ bus_dma_tag_destroy(dma->dma_tag); ++fail_0: ++ dma->dma_map = NULL; ++ dma->dma_tag = NULL; ++ ++ return NULL; ++} ++ ++void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr) ++{ ++ dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx; ++ ++ if (dma->dma_tag == NULL) ++ return; ++ if (dma->dma_map != NULL) { ++ bus_dmamap_sync(dma->dma_tag, dma->dma_map, ++ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); ++ bus_dmamap_unload(dma->dma_tag, dma->dma_map); ++ bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); ++ dma->dma_map = NULL; ++ } ++ ++ bus_dma_tag_destroy(dma->dma_tag); ++ dma->dma_tag = NULL; ++} ++ ++void *__DWC_ALLOC(void *mem_ctx, uint32_t size) ++{ ++ return malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); ++} ++ ++void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size) ++{ ++ return malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO); ++} ++ ++void __DWC_FREE(void *mem_ctx, void *addr) ++{ ++ free(addr, M_DEVBUF); ++} ++ ++ ++#ifdef DWC_CRYPTOLIB ++/* dwc_crypto.h */ ++ ++void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length) ++{ ++ get_random_bytes(buffer, length); ++} ++ ++int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out) ++{ ++ struct crypto_blkcipher *tfm; ++ struct blkcipher_desc desc; ++ struct scatterlist sgd; ++ struct scatterlist sgs; ++ ++ tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC); ++ if (tfm == NULL) { ++ printk("failed to load transform for aes CBC\n"); ++ return -1; ++ } ++ ++ crypto_blkcipher_setkey(tfm, key, keylen); ++ crypto_blkcipher_set_iv(tfm, iv, 16); ++ ++ sg_init_one(&sgd, out, messagelen); ++ sg_init_one(&sgs, message, messagelen); ++ ++ desc.tfm = tfm; ++ desc.flags = 0; ++ ++ if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) { ++ crypto_free_blkcipher(tfm); ++ DWC_ERROR("AES CBC encryption failed"); ++ return -1; ++ } ++ ++ crypto_free_blkcipher(tfm); ++ return 0; ++} ++ ++int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out) ++{ ++ struct crypto_hash *tfm; ++ struct hash_desc desc; ++ struct scatterlist sg; ++ ++ tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC); ++ if (IS_ERR(tfm)) { ++ DWC_ERROR("Failed to load transform for sha256: %ld", PTR_ERR(tfm)); ++ return 0; ++ } ++ desc.tfm = tfm; ++ desc.flags = 0; ++ ++ sg_init_one(&sg, message, len); ++ crypto_hash_digest(&desc, &sg, len, out); ++ crypto_free_hash(tfm); ++ ++ return 1; ++} ++ ++int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen, ++ uint8_t *key, uint32_t keylen, uint8_t *out) ++{ ++ struct crypto_hash *tfm; ++ struct hash_desc desc; ++ struct scatterlist sg; ++ ++ tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC); ++ if (IS_ERR(tfm)) { ++ DWC_ERROR("Failed to load transform for hmac(sha256): %ld", PTR_ERR(tfm)); ++ return 0; ++ } ++ desc.tfm = tfm; ++ desc.flags = 0; ++ ++ sg_init_one(&sg, message, messagelen); ++ crypto_hash_setkey(tfm, key, keylen); ++ crypto_hash_digest(&desc, &sg, messagelen, out); ++ crypto_free_hash(tfm); ++ ++ return 1; ++} ++ ++#endif /* DWC_CRYPTOLIB */ ++ ++ ++/* Byte Ordering Conversions */ ++ ++uint32_t DWC_CPU_TO_LE32(uint32_t *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++ ++uint32_t DWC_CPU_TO_BE32(uint32_t *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++ ++uint32_t DWC_LE32_TO_CPU(uint32_t *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++ ++uint32_t DWC_BE32_TO_CPU(uint32_t *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++ ++uint16_t DWC_CPU_TO_LE16(uint16_t *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++ ++uint16_t DWC_CPU_TO_BE16(uint16_t *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++ ++uint16_t DWC_LE16_TO_CPU(uint16_t *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++ ++uint16_t DWC_BE16_TO_CPU(uint16_t *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++ ++ ++/* Registers */ ++ ++uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ return bus_space_read_4(io->iot, io->ioh, ior); ++} ++ ++#if 0 ++uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ return bus_space_read_8(io->iot, io->ioh, ior); ++} ++#endif ++ ++void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ bus_space_write_4(io->iot, io->ioh, ior, value); ++} ++ ++#if 0 ++void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ bus_space_write_8(io->iot, io->ioh, ior, value); ++} ++#endif ++ ++void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask, ++ uint32_t set_mask) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ bus_space_write_4(io->iot, io->ioh, ior, ++ (bus_space_read_4(io->iot, io->ioh, ior) & ++ ~clear_mask) | set_mask); ++} ++ ++#if 0 ++void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask, ++ uint64_t set_mask) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ bus_space_write_8(io->iot, io->ioh, ior, ++ (bus_space_read_8(io->iot, io->ioh, ior) & ++ ~clear_mask) | set_mask); ++} ++#endif ++ ++ ++/* Locking */ ++ ++dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void) ++{ ++ struct mtx *sl = DWC_ALLOC(sizeof(*sl)); ++ ++ if (!sl) { ++ DWC_ERROR("Cannot allocate memory for spinlock"); ++ return NULL; ++ } ++ ++ mtx_init(sl, "dw3spn", NULL, MTX_SPIN); ++ return (dwc_spinlock_t *)sl; ++} ++ ++void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock) ++{ ++ struct mtx *sl = (struct mtx *)lock; ++ ++ mtx_destroy(sl); ++ DWC_FREE(sl); ++} ++ ++void DWC_SPINLOCK(dwc_spinlock_t *lock) ++{ ++ mtx_lock_spin((struct mtx *)lock); // ??? ++} ++ ++void DWC_SPINUNLOCK(dwc_spinlock_t *lock) ++{ ++ mtx_unlock_spin((struct mtx *)lock); // ??? ++} ++ ++void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags) ++{ ++ mtx_lock_spin((struct mtx *)lock); ++} ++ ++void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags) ++{ ++ mtx_unlock_spin((struct mtx *)lock); ++} ++ ++dwc_mutex_t *DWC_MUTEX_ALLOC(void) ++{ ++ struct mtx *m; ++ dwc_mutex_t *mutex = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mtx)); ++ ++ if (!mutex) { ++ DWC_ERROR("Cannot allocate memory for mutex"); ++ return NULL; ++ } ++ ++ m = (struct mtx *)mutex; ++ mtx_init(m, "dw3mtx", NULL, MTX_DEF); ++ return mutex; ++} ++ ++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)) ++#else ++void DWC_MUTEX_FREE(dwc_mutex_t *mutex) ++{ ++ mtx_destroy((struct mtx *)mutex); ++ DWC_FREE(mutex); ++} ++#endif ++ ++void DWC_MUTEX_LOCK(dwc_mutex_t *mutex) ++{ ++ struct mtx *m = (struct mtx *)mutex; ++ ++ mtx_lock(m); ++} ++ ++int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex) ++{ ++ struct mtx *m = (struct mtx *)mutex; ++ ++ return mtx_trylock(m); ++} ++ ++void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex) ++{ ++ struct mtx *m = (struct mtx *)mutex; ++ ++ mtx_unlock(m); ++} ++ ++ ++/* Timing */ ++ ++void DWC_UDELAY(uint32_t usecs) ++{ ++ DELAY(usecs); ++} ++ ++void DWC_MDELAY(uint32_t msecs) ++{ ++ do { ++ DELAY(1000); ++ } while (--msecs); ++} ++ ++void DWC_MSLEEP(uint32_t msecs) ++{ ++ struct timeval tv; ++ ++ tv.tv_sec = msecs / 1000; ++ tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000; ++ pause("dw3slp", tvtohz(&tv)); ++} ++ ++uint32_t DWC_TIME(void) ++{ ++ struct timeval tv; ++ ++ microuptime(&tv); // or getmicrouptime? (less precise, but faster) ++ return tv.tv_sec * 1000 + tv.tv_usec / 1000; ++} ++ ++ ++/* Timers */ ++ ++struct dwc_timer { ++ struct callout t; ++ char *name; ++ dwc_spinlock_t *lock; ++ dwc_timer_callback_t cb; ++ void *data; ++}; ++ ++dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data) ++{ ++ dwc_timer_t *t = DWC_ALLOC(sizeof(*t)); ++ ++ if (!t) { ++ DWC_ERROR("Cannot allocate memory for timer"); ++ return NULL; ++ } ++ ++ callout_init(&t->t, 1); ++ ++ t->name = DWC_STRDUP(name); ++ if (!t->name) { ++ DWC_ERROR("Cannot allocate memory for timer->name"); ++ goto no_name; ++ } ++ ++ t->lock = DWC_SPINLOCK_ALLOC(); ++ if (!t->lock) { ++ DWC_ERROR("Cannot allocate memory for lock"); ++ goto no_lock; ++ } ++ ++ t->cb = cb; ++ t->data = data; ++ ++ return t; ++ ++ no_lock: ++ DWC_FREE(t->name); ++ no_name: ++ DWC_FREE(t); ++ ++ return NULL; ++} ++ ++void DWC_TIMER_FREE(dwc_timer_t *timer) ++{ ++ callout_stop(&timer->t); ++ DWC_SPINLOCK_FREE(timer->lock); ++ DWC_FREE(timer->name); ++ DWC_FREE(timer); ++} ++ ++void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time) ++{ ++ struct timeval tv; ++ ++ tv.tv_sec = time / 1000; ++ tv.tv_usec = (time - tv.tv_sec * 1000) * 1000; ++ callout_reset(&timer->t, tvtohz(&tv), timer->cb, timer->data); ++} ++ ++void DWC_TIMER_CANCEL(dwc_timer_t *timer) ++{ ++ callout_stop(&timer->t); ++} ++ ++ ++/* Wait Queues */ ++ ++struct dwc_waitq { ++ struct mtx lock; ++ int abort; ++}; ++ ++dwc_waitq_t *DWC_WAITQ_ALLOC(void) ++{ ++ dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq)); ++ ++ if (!wq) { ++ DWC_ERROR("Cannot allocate memory for waitqueue"); ++ return NULL; ++ } ++ ++ mtx_init(&wq->lock, "dw3wtq", NULL, MTX_DEF); ++ wq->abort = 0; ++ ++ return wq; ++} ++ ++void DWC_WAITQ_FREE(dwc_waitq_t *wq) ++{ ++ mtx_destroy(&wq->lock); ++ DWC_FREE(wq); ++} ++ ++int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data) ++{ ++// intrmask_t ipl; ++ int result = 0; ++ ++ mtx_lock(&wq->lock); ++// ipl = splbio(); ++ ++ /* Skip the sleep if already aborted or triggered */ ++ if (!wq->abort && !cond(data)) { ++// splx(ipl); ++ result = msleep(wq, &wq->lock, PCATCH, "dw3wat", 0); // infinite timeout ++// ipl = splbio(); ++ } ++ ++ if (result == ERESTART) { // signaled - restart ++ result = -DWC_E_RESTART; ++ ++ } else if (result == EINTR) { // signaled - interrupt ++ result = -DWC_E_ABORT; ++ ++ } else if (wq->abort) { ++ result = -DWC_E_ABORT; ++ ++ } else { ++ result = 0; ++ } ++ ++ wq->abort = 0; ++// splx(ipl); ++ mtx_unlock(&wq->lock); ++ return result; ++} ++ ++int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, ++ void *data, int32_t msecs) ++{ ++ struct timeval tv, tv1, tv2; ++// intrmask_t ipl; ++ int result = 0; ++ ++ tv.tv_sec = msecs / 1000; ++ tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000; ++ ++ mtx_lock(&wq->lock); ++// ipl = splbio(); ++ ++ /* Skip the sleep if already aborted or triggered */ ++ if (!wq->abort && !cond(data)) { ++// splx(ipl); ++ getmicrouptime(&tv1); ++ result = msleep(wq, &wq->lock, PCATCH, "dw3wto", tvtohz(&tv)); ++ getmicrouptime(&tv2); ++// ipl = splbio(); ++ } ++ ++ if (result == 0) { // awoken ++ if (wq->abort) { ++ result = -DWC_E_ABORT; ++ } else { ++ tv2.tv_usec -= tv1.tv_usec; ++ if (tv2.tv_usec < 0) { ++ tv2.tv_usec += 1000000; ++ tv2.tv_sec--; ++ } ++ ++ tv2.tv_sec -= tv1.tv_sec; ++ result = tv2.tv_sec * 1000 + tv2.tv_usec / 1000; ++ result = msecs - result; ++ if (result <= 0) ++ result = 1; ++ } ++ } else if (result == ERESTART) { // signaled - restart ++ result = -DWC_E_RESTART; ++ ++ } else if (result == EINTR) { // signaled - interrupt ++ result = -DWC_E_ABORT; ++ ++ } else { // timed out ++ result = -DWC_E_TIMEOUT; ++ } ++ ++ wq->abort = 0; ++// splx(ipl); ++ mtx_unlock(&wq->lock); ++ return result; ++} ++ ++void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq) ++{ ++ wakeup(wq); ++} ++ ++void DWC_WAITQ_ABORT(dwc_waitq_t *wq) ++{ ++// intrmask_t ipl; ++ ++ mtx_lock(&wq->lock); ++// ipl = splbio(); ++ wq->abort = 1; ++ wakeup(wq); ++// splx(ipl); ++ mtx_unlock(&wq->lock); ++} ++ ++ ++/* Threading */ ++ ++struct dwc_thread { ++ struct proc *proc; ++ int abort; ++}; ++ ++dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data) ++{ ++ int retval; ++ dwc_thread_t *thread = DWC_ALLOC(sizeof(*thread)); ++ ++ if (!thread) { ++ return NULL; ++ } ++ ++ thread->abort = 0; ++ retval = kthread_create((void (*)(void *))func, data, &thread->proc, ++ RFPROC | RFNOWAIT, 0, "%s", name); ++ if (retval) { ++ DWC_FREE(thread); ++ return NULL; ++ } ++ ++ return thread; ++} ++ ++int DWC_THREAD_STOP(dwc_thread_t *thread) ++{ ++ int retval; ++ ++ thread->abort = 1; ++ retval = tsleep(&thread->abort, 0, "dw3stp", 60 * hz); ++ ++ if (retval == 0) { ++ /* DWC_THREAD_EXIT() will free the thread struct */ ++ return 0; ++ } ++ ++ /* NOTE: We leak the thread struct if thread doesn't die */ ++ ++ if (retval == EWOULDBLOCK) { ++ return -DWC_E_TIMEOUT; ++ } ++ ++ return -DWC_E_UNKNOWN; ++} ++ ++dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread) ++{ ++ return thread->abort; ++} ++ ++void DWC_THREAD_EXIT(dwc_thread_t *thread) ++{ ++ wakeup(&thread->abort); ++ DWC_FREE(thread); ++ kthread_exit(0); ++} ++ ++ ++/* tasklets ++ - Runs in interrupt context (cannot sleep) ++ - Each tasklet runs on a single CPU [ How can we ensure this on FreeBSD? Does it matter? ] ++ - Different tasklets can be running simultaneously on different CPUs [ shouldn't matter ] ++ */ ++struct dwc_tasklet { ++ struct task t; ++ dwc_tasklet_callback_t cb; ++ void *data; ++}; ++ ++static void tasklet_callback(void *data, int pending) // what to do with pending ??? ++{ ++ dwc_tasklet_t *task = (dwc_tasklet_t *)data; ++ ++ task->cb(task->data); ++} ++ ++dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data) ++{ ++ dwc_tasklet_t *task = DWC_ALLOC(sizeof(*task)); ++ ++ if (task) { ++ task->cb = cb; ++ task->data = data; ++ TASK_INIT(&task->t, 0, tasklet_callback, task); ++ } else { ++ DWC_ERROR("Cannot allocate memory for tasklet"); ++ } ++ ++ return task; ++} ++ ++void DWC_TASK_FREE(dwc_tasklet_t *task) ++{ ++ taskqueue_drain(taskqueue_fast, &task->t); // ??? ++ DWC_FREE(task); ++} ++ ++void DWC_TASK_SCHEDULE(dwc_tasklet_t *task) ++{ ++ /* Uses predefined system queue */ ++ taskqueue_enqueue_fast(taskqueue_fast, &task->t); ++} ++ ++ ++/* workqueues ++ - Runs in process context (can sleep) ++ */ ++typedef struct work_container { ++ dwc_work_callback_t cb; ++ void *data; ++ dwc_workq_t *wq; ++ char *name; ++ int hz; ++ ++#ifdef DEBUG ++ DWC_CIRCLEQ_ENTRY(work_container) entry; ++#endif ++ struct task task; ++} work_container_t; ++ ++#ifdef DEBUG ++DWC_CIRCLEQ_HEAD(work_container_queue, work_container); ++#endif ++ ++struct dwc_workq { ++ struct taskqueue *taskq; ++ dwc_spinlock_t *lock; ++ dwc_waitq_t *waitq; ++ int pending; ++ ++#ifdef DEBUG ++ struct work_container_queue entries; ++#endif ++}; ++ ++static void do_work(void *data, int pending) // what to do with pending ??? ++{ ++ work_container_t *container = (work_container_t *)data; ++ dwc_workq_t *wq = container->wq; ++ dwc_irqflags_t flags; ++ ++ if (container->hz) { ++ pause("dw3wrk", container->hz); ++ } ++ ++ container->cb(container->data); ++ DWC_DEBUG("Work done: %s, container=%p", container->name, container); ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ ++#ifdef DEBUG ++ DWC_CIRCLEQ_REMOVE(&wq->entries, container, entry); ++#endif ++ if (container->name) ++ DWC_FREE(container->name); ++ DWC_FREE(container); ++ wq->pending--; ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++ DWC_WAITQ_TRIGGER(wq->waitq); ++} ++ ++static int work_done(void *data) ++{ ++ dwc_workq_t *workq = (dwc_workq_t *)data; ++ ++ return workq->pending == 0; ++} ++ ++int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout) ++{ ++ return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout); ++} ++ ++dwc_workq_t *DWC_WORKQ_ALLOC(char *name) ++{ ++ dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq)); ++ ++ if (!wq) { ++ DWC_ERROR("Cannot allocate memory for workqueue"); ++ return NULL; ++ } ++ ++ wq->taskq = taskqueue_create(name, M_NOWAIT, taskqueue_thread_enqueue, &wq->taskq); ++ if (!wq->taskq) { ++ DWC_ERROR("Cannot allocate memory for taskqueue"); ++ goto no_taskq; ++ } ++ ++ wq->pending = 0; ++ ++ wq->lock = DWC_SPINLOCK_ALLOC(); ++ if (!wq->lock) { ++ DWC_ERROR("Cannot allocate memory for spinlock"); ++ goto no_lock; ++ } ++ ++ wq->waitq = DWC_WAITQ_ALLOC(); ++ if (!wq->waitq) { ++ DWC_ERROR("Cannot allocate memory for waitqueue"); ++ goto no_waitq; ++ } ++ ++ taskqueue_start_threads(&wq->taskq, 1, PWAIT, "%s taskq", "dw3tsk"); ++ ++#ifdef DEBUG ++ DWC_CIRCLEQ_INIT(&wq->entries); ++#endif ++ return wq; ++ ++ no_waitq: ++ DWC_SPINLOCK_FREE(wq->lock); ++ no_lock: ++ taskqueue_free(wq->taskq); ++ no_taskq: ++ DWC_FREE(wq); ++ ++ return NULL; ++} ++ ++void DWC_WORKQ_FREE(dwc_workq_t *wq) ++{ ++#ifdef DEBUG ++ dwc_irqflags_t flags; ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ ++ if (wq->pending != 0) { ++ struct work_container *container; ++ ++ DWC_ERROR("Destroying work queue with pending work"); ++ ++ DWC_CIRCLEQ_FOREACH(container, &wq->entries, entry) { ++ DWC_ERROR("Work %s still pending", container->name); ++ } ++ } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++#endif ++ DWC_WAITQ_FREE(wq->waitq); ++ DWC_SPINLOCK_FREE(wq->lock); ++ taskqueue_free(wq->taskq); ++ DWC_FREE(wq); ++} ++ ++void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data, ++ char *format, ...) ++{ ++ dwc_irqflags_t flags; ++ work_container_t *container; ++ static char name[128]; ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VSNPRINTF(name, 128, format, args); ++ va_end(args); ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ wq->pending++; ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++ DWC_WAITQ_TRIGGER(wq->waitq); ++ ++ container = DWC_ALLOC_ATOMIC(sizeof(*container)); ++ if (!container) { ++ DWC_ERROR("Cannot allocate memory for container"); ++ return; ++ } ++ ++ container->name = DWC_STRDUP(name); ++ if (!container->name) { ++ DWC_ERROR("Cannot allocate memory for container->name"); ++ DWC_FREE(container); ++ return; ++ } ++ ++ container->cb = cb; ++ container->data = data; ++ container->wq = wq; ++ container->hz = 0; ++ ++ DWC_DEBUG("Queueing work: %s, container=%p", container->name, container); ++ ++ TASK_INIT(&container->task, 0, do_work, container); ++ ++#ifdef DEBUG ++ DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry); ++#endif ++ taskqueue_enqueue_fast(wq->taskq, &container->task); ++} ++ ++void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb, ++ void *data, uint32_t time, char *format, ...) ++{ ++ dwc_irqflags_t flags; ++ work_container_t *container; ++ static char name[128]; ++ struct timeval tv; ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VSNPRINTF(name, 128, format, args); ++ va_end(args); ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ wq->pending++; ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++ DWC_WAITQ_TRIGGER(wq->waitq); ++ ++ container = DWC_ALLOC_ATOMIC(sizeof(*container)); ++ if (!container) { ++ DWC_ERROR("Cannot allocate memory for container"); ++ return; ++ } ++ ++ container->name = DWC_STRDUP(name); ++ if (!container->name) { ++ DWC_ERROR("Cannot allocate memory for container->name"); ++ DWC_FREE(container); ++ return; ++ } ++ ++ container->cb = cb; ++ container->data = data; ++ container->wq = wq; ++ ++ tv.tv_sec = time / 1000; ++ tv.tv_usec = (time - tv.tv_sec * 1000) * 1000; ++ container->hz = tvtohz(&tv); ++ ++ DWC_DEBUG("Queueing work: %s, container=%p", container->name, container); ++ ++ TASK_INIT(&container->task, 0, do_work, container); ++ ++#ifdef DEBUG ++ DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry); ++#endif ++ taskqueue_enqueue_fast(wq->taskq, &container->task); ++} ++ ++int DWC_WORKQ_PENDING(dwc_workq_t *wq) ++{ ++ return wq->pending; ++} +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_common_linux.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_common_linux.c +--- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_common_linux.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_common_linux.c 2015-11-29 09:42:39.915098960 +0100 +@@ -0,0 +1,1434 @@ ++#include ++#include ++#include ++#include ++ ++#ifdef DWC_CCLIB ++# include "dwc_cc.h" ++#endif ++ ++#ifdef DWC_CRYPTOLIB ++# include "dwc_modpow.h" ++# include "dwc_dh.h" ++# include "dwc_crypto.h" ++#endif ++ ++#ifdef DWC_NOTIFYLIB ++# include "dwc_notifier.h" ++#endif ++ ++/* OS-Level Implementations */ ++ ++/* This is the Linux kernel implementation of the DWC platform library. */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24) ++# include ++#else ++# include ++#endif ++ ++#include ++#include ++#include ++#include ++ ++#include "dwc_os.h" ++#include "dwc_list.h" ++ ++ ++/* MISC */ ++ ++void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size) ++{ ++ return memset(dest, byte, size); ++} ++ ++void *DWC_MEMCPY(void *dest, void const *src, uint32_t size) ++{ ++ return memcpy(dest, src, size); ++} ++ ++void *DWC_MEMMOVE(void *dest, void *src, uint32_t size) ++{ ++ return memmove(dest, src, size); ++} ++ ++int DWC_MEMCMP(void *m1, void *m2, uint32_t size) ++{ ++ return memcmp(m1, m2, size); ++} ++ ++int DWC_STRNCMP(void *s1, void *s2, uint32_t size) ++{ ++ return strncmp(s1, s2, size); ++} ++ ++int DWC_STRCMP(void *s1, void *s2) ++{ ++ return strcmp(s1, s2); ++} ++ ++int DWC_STRLEN(char const *str) ++{ ++ return strlen(str); ++} ++ ++char *DWC_STRCPY(char *to, char const *from) ++{ ++ return strcpy(to, from); ++} ++ ++char *DWC_STRDUP(char const *str) ++{ ++ int len = DWC_STRLEN(str) + 1; ++ char *new = DWC_ALLOC_ATOMIC(len); ++ ++ if (!new) { ++ return NULL; ++ } ++ ++ DWC_MEMCPY(new, str, len); ++ return new; ++} ++ ++int DWC_ATOI(const char *str, int32_t *value) ++{ ++ char *end = NULL; ++ ++ *value = simple_strtol(str, &end, 0); ++ if (*end == '\0') { ++ return 0; ++ } ++ ++ return -1; ++} ++ ++int DWC_ATOUI(const char *str, uint32_t *value) ++{ ++ char *end = NULL; ++ ++ *value = simple_strtoul(str, &end, 0); ++ if (*end == '\0') { ++ return 0; ++ } ++ ++ return -1; ++} ++ ++ ++#ifdef DWC_UTFLIB ++/* From usbstring.c */ ++ ++int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len) ++{ ++ int count = 0; ++ u8 c; ++ u16 uchar; ++ ++ /* this insists on correct encodings, though not minimal ones. ++ * BUT it currently rejects legit 4-byte UTF-8 code points, ++ * which need surrogate pairs. (Unicode 3.1 can use them.) ++ */ ++ while (len != 0 && (c = (u8) *s++) != 0) { ++ if (unlikely(c & 0x80)) { ++ // 2-byte sequence: ++ // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx ++ if ((c & 0xe0) == 0xc0) { ++ uchar = (c & 0x1f) << 6; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c; ++ ++ // 3-byte sequence (most CJKV characters): ++ // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx ++ } else if ((c & 0xf0) == 0xe0) { ++ uchar = (c & 0x0f) << 12; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c << 6; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c; ++ ++ /* no bogus surrogates */ ++ if (0xd800 <= uchar && uchar <= 0xdfff) ++ goto fail; ++ ++ // 4-byte sequence (surrogate pairs, currently rare): ++ // 11101110wwwwzzzzyy + 110111yyyyxxxxxx ++ // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx ++ // (uuuuu = wwww + 1) ++ // FIXME accept the surrogate code points (only) ++ } else ++ goto fail; ++ } else ++ uchar = c; ++ put_unaligned (cpu_to_le16 (uchar), cp++); ++ count++; ++ len--; ++ } ++ return count; ++fail: ++ return -1; ++} ++#endif /* DWC_UTFLIB */ ++ ++ ++/* dwc_debug.h */ ++ ++dwc_bool_t DWC_IN_IRQ(void) ++{ ++ return in_irq(); ++} ++ ++dwc_bool_t DWC_IN_BH(void) ++{ ++ return in_softirq(); ++} ++ ++void DWC_VPRINTF(char *format, va_list args) ++{ ++ vprintk(format, args); ++} ++ ++int DWC_VSNPRINTF(char *str, int size, char *format, va_list args) ++{ ++ return vsnprintf(str, size, format, args); ++} ++ ++void DWC_PRINTF(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++ ++int DWC_SPRINTF(char *buffer, char *format, ...) ++{ ++ int retval; ++ va_list args; ++ ++ va_start(args, format); ++ retval = vsprintf(buffer, format, args); ++ va_end(args); ++ return retval; ++} ++ ++int DWC_SNPRINTF(char *buffer, int size, char *format, ...) ++{ ++ int retval; ++ va_list args; ++ ++ va_start(args, format); ++ retval = vsnprintf(buffer, size, format, args); ++ va_end(args); ++ return retval; ++} ++ ++void __DWC_WARN(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_PRINTF(KERN_WARNING); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++ ++void __DWC_ERROR(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_PRINTF(KERN_ERR); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++ ++void DWC_EXCEPTION(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_PRINTF(KERN_ERR); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++ BUG_ON(1); ++} ++ ++#ifdef DEBUG ++void __DWC_DEBUG(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_PRINTF(KERN_DEBUG); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++#endif ++ ++ ++/* dwc_mem.h */ ++ ++#if 0 ++dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size, ++ uint32_t align, ++ uint32_t alloc) ++{ ++ struct dma_pool *pool = dma_pool_create("Pool", NULL, ++ size, align, alloc); ++ return (dwc_pool_t *)pool; ++} ++ ++void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool) ++{ ++ dma_pool_destroy((struct dma_pool *)pool); ++} ++ ++void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr) ++{ ++ return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr); ++} ++ ++void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr) ++{ ++ void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr); ++ memset(..); ++} ++ ++void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr) ++{ ++ dma_pool_free(pool, vaddr, daddr); ++} ++#endif ++ ++void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr) ++{ ++#ifdef xxCOSIM /* Only works for 32-bit cosim */ ++ void *buf = dma_alloc_coherent(dma_ctx, (size_t)size, dma_addr, GFP_KERNEL); ++#else ++ void *buf = dma_alloc_coherent(dma_ctx, (size_t)size, dma_addr, GFP_KERNEL | GFP_DMA32); ++#endif ++ if (!buf) { ++ return NULL; ++ } ++ ++ memset(buf, 0, (size_t)size); ++ return buf; ++} ++ ++void *__DWC_DMA_ALLOC_ATOMIC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr) ++{ ++ void *buf = dma_alloc_coherent(NULL, (size_t)size, dma_addr, GFP_ATOMIC); ++ if (!buf) { ++ return NULL; ++ } ++ memset(buf, 0, (size_t)size); ++ return buf; ++} ++ ++void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr) ++{ ++ dma_free_coherent(dma_ctx, size, virt_addr, dma_addr); ++} ++ ++void *__DWC_ALLOC(void *mem_ctx, uint32_t size) ++{ ++ return kzalloc(size, GFP_KERNEL); ++} ++ ++void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size) ++{ ++ return kzalloc(size, GFP_ATOMIC); ++} ++ ++void __DWC_FREE(void *mem_ctx, void *addr) ++{ ++ kfree(addr); ++} ++ ++ ++#ifdef DWC_CRYPTOLIB ++/* dwc_crypto.h */ ++ ++void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length) ++{ ++ get_random_bytes(buffer, length); ++} ++ ++int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out) ++{ ++ struct crypto_blkcipher *tfm; ++ struct blkcipher_desc desc; ++ struct scatterlist sgd; ++ struct scatterlist sgs; ++ ++ tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC); ++ if (tfm == NULL) { ++ printk("failed to load transform for aes CBC\n"); ++ return -1; ++ } ++ ++ crypto_blkcipher_setkey(tfm, key, keylen); ++ crypto_blkcipher_set_iv(tfm, iv, 16); ++ ++ sg_init_one(&sgd, out, messagelen); ++ sg_init_one(&sgs, message, messagelen); ++ ++ desc.tfm = tfm; ++ desc.flags = 0; ++ ++ if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) { ++ crypto_free_blkcipher(tfm); ++ DWC_ERROR("AES CBC encryption failed"); ++ return -1; ++ } ++ ++ crypto_free_blkcipher(tfm); ++ return 0; ++} ++ ++int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out) ++{ ++ struct crypto_hash *tfm; ++ struct hash_desc desc; ++ struct scatterlist sg; ++ ++ tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC); ++ if (IS_ERR(tfm)) { ++ DWC_ERROR("Failed to load transform for sha256: %ld\n", PTR_ERR(tfm)); ++ return 0; ++ } ++ desc.tfm = tfm; ++ desc.flags = 0; ++ ++ sg_init_one(&sg, message, len); ++ crypto_hash_digest(&desc, &sg, len, out); ++ crypto_free_hash(tfm); ++ ++ return 1; ++} ++ ++int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen, ++ uint8_t *key, uint32_t keylen, uint8_t *out) ++{ ++ struct crypto_hash *tfm; ++ struct hash_desc desc; ++ struct scatterlist sg; ++ ++ tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC); ++ if (IS_ERR(tfm)) { ++ DWC_ERROR("Failed to load transform for hmac(sha256): %ld\n", PTR_ERR(tfm)); ++ return 0; ++ } ++ desc.tfm = tfm; ++ desc.flags = 0; ++ ++ sg_init_one(&sg, message, messagelen); ++ crypto_hash_setkey(tfm, key, keylen); ++ crypto_hash_digest(&desc, &sg, messagelen, out); ++ crypto_free_hash(tfm); ++ ++ return 1; ++} ++#endif /* DWC_CRYPTOLIB */ ++ ++ ++/* Byte Ordering Conversions */ ++ ++uint32_t DWC_CPU_TO_LE32(uint32_t *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++ ++uint32_t DWC_CPU_TO_BE32(uint32_t *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++ ++uint32_t DWC_LE32_TO_CPU(uint32_t *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++ ++uint32_t DWC_BE32_TO_CPU(uint32_t *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++ ++uint16_t DWC_CPU_TO_LE16(uint16_t *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++ ++uint16_t DWC_CPU_TO_BE16(uint16_t *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++ ++uint16_t DWC_LE16_TO_CPU(uint16_t *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++ ++uint16_t DWC_BE16_TO_CPU(uint16_t *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++ ++ ++/* Registers */ ++ ++uint32_t DWC_READ_REG32(uint32_t volatile *reg) ++{ ++ return readl(reg); ++} ++ ++#if 0 ++uint64_t DWC_READ_REG64(uint64_t volatile *reg) ++{ ++} ++#endif ++ ++void DWC_WRITE_REG32(uint32_t volatile *reg, uint32_t value) ++{ ++ writel(value, reg); ++} ++ ++#if 0 ++void DWC_WRITE_REG64(uint64_t volatile *reg, uint64_t value) ++{ ++} ++#endif ++ ++void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask) ++{ ++ writel((readl(reg) & ~clear_mask) | set_mask, reg); ++} ++ ++#if 0 ++void DWC_MODIFY_REG64(uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask) ++{ ++} ++#endif ++ ++ ++/* Locking */ ++ ++dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void) ++{ ++ spinlock_t *sl = (spinlock_t *)1; ++ ++#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) ++ sl = DWC_ALLOC(sizeof(*sl)); ++ if (!sl) { ++ DWC_ERROR("Cannot allocate memory for spinlock\n"); ++ return NULL; ++ } ++ ++ spin_lock_init(sl); ++#endif ++ return (dwc_spinlock_t *)sl; ++} ++ ++void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock) ++{ ++#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) ++ DWC_FREE(lock); ++#endif ++} ++ ++void DWC_SPINLOCK(dwc_spinlock_t *lock) ++{ ++#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) ++ spin_lock((spinlock_t *)lock); ++#endif ++} ++ ++void DWC_SPINUNLOCK(dwc_spinlock_t *lock) ++{ ++#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) ++ spin_unlock((spinlock_t *)lock); ++#endif ++} ++ ++void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags) ++{ ++ dwc_irqflags_t f; ++ ++#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) ++ spin_lock_irqsave((spinlock_t *)lock, f); ++#else ++ local_irq_save(f); ++#endif ++ *flags = f; ++} ++ ++void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags) ++{ ++#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) ++ spin_unlock_irqrestore((spinlock_t *)lock, flags); ++#else ++ local_irq_restore(flags); ++#endif ++} ++ ++dwc_mutex_t *DWC_MUTEX_ALLOC(void) ++{ ++ struct mutex *m; ++ dwc_mutex_t *mutex = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mutex)); ++ ++ if (!mutex) { ++ DWC_ERROR("Cannot allocate memory for mutex\n"); ++ return NULL; ++ } ++ ++ m = (struct mutex *)mutex; ++ mutex_init(m); ++ return mutex; ++} ++ ++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)) ++#else ++void DWC_MUTEX_FREE(dwc_mutex_t *mutex) ++{ ++ mutex_destroy((struct mutex *)mutex); ++ DWC_FREE(mutex); ++} ++#endif ++ ++void DWC_MUTEX_LOCK(dwc_mutex_t *mutex) ++{ ++ struct mutex *m = (struct mutex *)mutex; ++ mutex_lock(m); ++} ++ ++int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex) ++{ ++ struct mutex *m = (struct mutex *)mutex; ++ return mutex_trylock(m); ++} ++ ++void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex) ++{ ++ struct mutex *m = (struct mutex *)mutex; ++ mutex_unlock(m); ++} ++ ++ ++/* Timing */ ++ ++void DWC_UDELAY(uint32_t usecs) ++{ ++ udelay(usecs); ++} ++ ++void DWC_MDELAY(uint32_t msecs) ++{ ++ mdelay(msecs); ++} ++ ++void DWC_MSLEEP(uint32_t msecs) ++{ ++ msleep(msecs); ++} ++ ++uint32_t DWC_TIME(void) ++{ ++ return jiffies_to_msecs(jiffies); ++} ++ ++ ++/* Timers */ ++ ++struct dwc_timer { ++ struct timer_list *t; ++ char *name; ++ dwc_timer_callback_t cb; ++ void *data; ++ uint8_t scheduled; ++ dwc_spinlock_t *lock; ++}; ++ ++static void timer_callback(unsigned long data) ++{ ++ dwc_timer_t *timer = (dwc_timer_t *)data; ++ dwc_irqflags_t flags; ++ ++ DWC_SPINLOCK_IRQSAVE(timer->lock, &flags); ++ timer->scheduled = 0; ++ DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags); ++ DWC_DEBUGC("Timer %s callback", timer->name); ++ timer->cb(timer->data); ++} ++ ++dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data) ++{ ++ dwc_timer_t *t = DWC_ALLOC(sizeof(*t)); ++ ++ if (!t) { ++ DWC_ERROR("Cannot allocate memory for timer"); ++ return NULL; ++ } ++ ++ t->t = DWC_ALLOC(sizeof(*t->t)); ++ if (!t->t) { ++ DWC_ERROR("Cannot allocate memory for timer->t"); ++ goto no_timer; ++ } ++ ++ t->name = DWC_STRDUP(name); ++ if (!t->name) { ++ DWC_ERROR("Cannot allocate memory for timer->name"); ++ goto no_name; ++ } ++ ++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK)) ++ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(t->lock); ++#else ++ t->lock = DWC_SPINLOCK_ALLOC(); ++#endif ++ if (!t->lock) { ++ DWC_ERROR("Cannot allocate memory for lock"); ++ goto no_lock; ++ } ++ ++ t->scheduled = 0; ++ t->t->base = &boot_tvec_bases; ++ t->t->expires = jiffies; ++ setup_timer(t->t, timer_callback, (unsigned long)t); ++ ++ t->cb = cb; ++ t->data = data; ++ ++ return t; ++ ++ no_lock: ++ DWC_FREE(t->name); ++ no_name: ++ DWC_FREE(t->t); ++ no_timer: ++ DWC_FREE(t); ++ return NULL; ++} ++ ++void DWC_TIMER_FREE(dwc_timer_t *timer) ++{ ++ dwc_irqflags_t flags; ++ ++ DWC_SPINLOCK_IRQSAVE(timer->lock, &flags); ++ ++ if (timer->scheduled) { ++ del_timer(timer->t); ++ timer->scheduled = 0; ++ } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags); ++ DWC_SPINLOCK_FREE(timer->lock); ++ DWC_FREE(timer->t); ++ DWC_FREE(timer->name); ++ DWC_FREE(timer); ++} ++ ++void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time) ++{ ++ dwc_irqflags_t flags; ++ ++ DWC_SPINLOCK_IRQSAVE(timer->lock, &flags); ++ ++ if (!timer->scheduled) { ++ timer->scheduled = 1; ++ DWC_DEBUGC("Scheduling timer %s to expire in +%d msec", timer->name, time); ++ timer->t->expires = jiffies + msecs_to_jiffies(time); ++ add_timer(timer->t); ++ } else { ++ DWC_DEBUGC("Modifying timer %s to expire in +%d msec", timer->name, time); ++ mod_timer(timer->t, jiffies + msecs_to_jiffies(time)); ++ } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags); ++} ++ ++void DWC_TIMER_CANCEL(dwc_timer_t *timer) ++{ ++ del_timer(timer->t); ++} ++ ++ ++/* Wait Queues */ ++ ++struct dwc_waitq { ++ wait_queue_head_t queue; ++ int abort; ++}; ++ ++dwc_waitq_t *DWC_WAITQ_ALLOC(void) ++{ ++ dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq)); ++ ++ if (!wq) { ++ DWC_ERROR("Cannot allocate memory for waitqueue\n"); ++ return NULL; ++ } ++ ++ init_waitqueue_head(&wq->queue); ++ wq->abort = 0; ++ return wq; ++} ++ ++void DWC_WAITQ_FREE(dwc_waitq_t *wq) ++{ ++ DWC_FREE(wq); ++} ++ ++int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data) ++{ ++ int result = wait_event_interruptible(wq->queue, ++ cond(data) || wq->abort); ++ if (result == -ERESTARTSYS) { ++ wq->abort = 0; ++ return -DWC_E_RESTART; ++ } ++ ++ if (wq->abort == 1) { ++ wq->abort = 0; ++ return -DWC_E_ABORT; ++ } ++ ++ wq->abort = 0; ++ ++ if (result == 0) { ++ return 0; ++ } ++ ++ return -DWC_E_UNKNOWN; ++} ++ ++int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, ++ void *data, int32_t msecs) ++{ ++ int32_t tmsecs; ++ int result = wait_event_interruptible_timeout(wq->queue, ++ cond(data) || wq->abort, ++ msecs_to_jiffies(msecs)); ++ if (result == -ERESTARTSYS) { ++ wq->abort = 0; ++ return -DWC_E_RESTART; ++ } ++ ++ if (wq->abort == 1) { ++ wq->abort = 0; ++ return -DWC_E_ABORT; ++ } ++ ++ wq->abort = 0; ++ ++ if (result > 0) { ++ tmsecs = jiffies_to_msecs(result); ++ if (!tmsecs) { ++ return 1; ++ } ++ ++ return tmsecs; ++ } ++ ++ if (result == 0) { ++ return -DWC_E_TIMEOUT; ++ } ++ ++ return -DWC_E_UNKNOWN; ++} ++ ++void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq) ++{ ++ wq->abort = 0; ++ wake_up_interruptible(&wq->queue); ++} ++ ++void DWC_WAITQ_ABORT(dwc_waitq_t *wq) ++{ ++ wq->abort = 1; ++ wake_up_interruptible(&wq->queue); ++} ++ ++ ++/* Threading */ ++ ++dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data) ++{ ++ struct task_struct *thread = kthread_run(func, data, name); ++ ++ if (thread == ERR_PTR(-ENOMEM)) { ++ return NULL; ++ } ++ ++ return (dwc_thread_t *)thread; ++} ++ ++int DWC_THREAD_STOP(dwc_thread_t *thread) ++{ ++ return kthread_stop((struct task_struct *)thread); ++} ++ ++dwc_bool_t DWC_THREAD_SHOULD_STOP(void) ++{ ++ return kthread_should_stop(); ++} ++ ++ ++/* tasklets ++ - run in interrupt context (cannot sleep) ++ - each tasklet runs on a single CPU ++ - different tasklets can be running simultaneously on different CPUs ++ */ ++struct dwc_tasklet { ++ struct tasklet_struct t; ++ dwc_tasklet_callback_t cb; ++ void *data; ++}; ++ ++static void tasklet_callback(unsigned long data) ++{ ++ dwc_tasklet_t *t = (dwc_tasklet_t *)data; ++ t->cb(t->data); ++} ++ ++dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data) ++{ ++ dwc_tasklet_t *t = DWC_ALLOC(sizeof(*t)); ++ ++ if (t) { ++ t->cb = cb; ++ t->data = data; ++ tasklet_init(&t->t, tasklet_callback, (unsigned long)t); ++ } else { ++ DWC_ERROR("Cannot allocate memory for tasklet\n"); ++ } ++ ++ return t; ++} ++ ++void DWC_TASK_FREE(dwc_tasklet_t *task) ++{ ++ DWC_FREE(task); ++} ++ ++void DWC_TASK_SCHEDULE(dwc_tasklet_t *task) ++{ ++ tasklet_schedule(&task->t); ++} ++ ++void DWC_TASK_HI_SCHEDULE(dwc_tasklet_t *task) ++{ ++ tasklet_hi_schedule(&task->t); ++} ++ ++ ++/* workqueues ++ - run in process context (can sleep) ++ */ ++typedef struct work_container { ++ dwc_work_callback_t cb; ++ void *data; ++ dwc_workq_t *wq; ++ char *name; ++ ++#ifdef DEBUG ++ DWC_CIRCLEQ_ENTRY(work_container) entry; ++#endif ++ struct delayed_work work; ++} work_container_t; ++ ++#ifdef DEBUG ++DWC_CIRCLEQ_HEAD(work_container_queue, work_container); ++#endif ++ ++struct dwc_workq { ++ struct workqueue_struct *wq; ++ dwc_spinlock_t *lock; ++ dwc_waitq_t *waitq; ++ int pending; ++ ++#ifdef DEBUG ++ struct work_container_queue entries; ++#endif ++}; ++ ++static void do_work(struct work_struct *work) ++{ ++ dwc_irqflags_t flags; ++ struct delayed_work *dw = container_of(work, struct delayed_work, work); ++ work_container_t *container = container_of(dw, struct work_container, work); ++ dwc_workq_t *wq = container->wq; ++ ++ container->cb(container->data); ++ ++#ifdef DEBUG ++ DWC_CIRCLEQ_REMOVE(&wq->entries, container, entry); ++#endif ++ DWC_DEBUGC("Work done: %s, container=%p", container->name, container); ++ if (container->name) { ++ DWC_FREE(container->name); ++ } ++ DWC_FREE(container); ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ wq->pending--; ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++ DWC_WAITQ_TRIGGER(wq->waitq); ++} ++ ++static int work_done(void *data) ++{ ++ dwc_workq_t *workq = (dwc_workq_t *)data; ++ return workq->pending == 0; ++} ++ ++int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout) ++{ ++ return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout); ++} ++ ++dwc_workq_t *DWC_WORKQ_ALLOC(char *name) ++{ ++ dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq)); ++ ++ if (!wq) { ++ return NULL; ++ } ++ ++ wq->wq = create_singlethread_workqueue(name); ++ if (!wq->wq) { ++ goto no_wq; ++ } ++ ++ wq->pending = 0; ++ ++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK)) ++ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(wq->lock); ++#else ++ wq->lock = DWC_SPINLOCK_ALLOC(); ++#endif ++ if (!wq->lock) { ++ goto no_lock; ++ } ++ ++ wq->waitq = DWC_WAITQ_ALLOC(); ++ if (!wq->waitq) { ++ goto no_waitq; ++ } ++ ++#ifdef DEBUG ++ DWC_CIRCLEQ_INIT(&wq->entries); ++#endif ++ return wq; ++ ++ no_waitq: ++ DWC_SPINLOCK_FREE(wq->lock); ++ no_lock: ++ destroy_workqueue(wq->wq); ++ no_wq: ++ DWC_FREE(wq); ++ ++ return NULL; ++} ++ ++void DWC_WORKQ_FREE(dwc_workq_t *wq) ++{ ++#ifdef DEBUG ++ if (wq->pending != 0) { ++ struct work_container *wc; ++ DWC_ERROR("Destroying work queue with pending work"); ++ DWC_CIRCLEQ_FOREACH(wc, &wq->entries, entry) { ++ DWC_ERROR("Work %s still pending", wc->name); ++ } ++ } ++#endif ++ destroy_workqueue(wq->wq); ++ DWC_SPINLOCK_FREE(wq->lock); ++ DWC_WAITQ_FREE(wq->waitq); ++ DWC_FREE(wq); ++} ++ ++void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data, ++ char *format, ...) ++{ ++ dwc_irqflags_t flags; ++ work_container_t *container; ++ static char name[128]; ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VSNPRINTF(name, 128, format, args); ++ va_end(args); ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ wq->pending++; ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++ DWC_WAITQ_TRIGGER(wq->waitq); ++ ++ container = DWC_ALLOC_ATOMIC(sizeof(*container)); ++ if (!container) { ++ DWC_ERROR("Cannot allocate memory for container\n"); ++ return; ++ } ++ ++ container->name = DWC_STRDUP(name); ++ if (!container->name) { ++ DWC_ERROR("Cannot allocate memory for container->name\n"); ++ DWC_FREE(container); ++ return; ++ } ++ ++ container->cb = cb; ++ container->data = data; ++ container->wq = wq; ++ DWC_DEBUGC("Queueing work: %s, container=%p", container->name, container); ++ INIT_WORK(&container->work.work, do_work); ++ ++#ifdef DEBUG ++ DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry); ++#endif ++ queue_work(wq->wq, &container->work.work); ++} ++ ++void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb, ++ void *data, uint32_t time, char *format, ...) ++{ ++ dwc_irqflags_t flags; ++ work_container_t *container; ++ static char name[128]; ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VSNPRINTF(name, 128, format, args); ++ va_end(args); ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ wq->pending++; ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++ DWC_WAITQ_TRIGGER(wq->waitq); ++ ++ container = DWC_ALLOC_ATOMIC(sizeof(*container)); ++ if (!container) { ++ DWC_ERROR("Cannot allocate memory for container\n"); ++ return; ++ } ++ ++ container->name = DWC_STRDUP(name); ++ if (!container->name) { ++ DWC_ERROR("Cannot allocate memory for container->name\n"); ++ DWC_FREE(container); ++ return; ++ } ++ ++ container->cb = cb; ++ container->data = data; ++ container->wq = wq; ++ DWC_DEBUGC("Queueing work: %s, container=%p", container->name, container); ++ INIT_DELAYED_WORK(&container->work, do_work); ++ ++#ifdef DEBUG ++ DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry); ++#endif ++ queue_delayed_work(wq->wq, &container->work, msecs_to_jiffies(time)); ++} ++ ++int DWC_WORKQ_PENDING(dwc_workq_t *wq) ++{ ++ return wq->pending; ++} ++ ++ ++#ifdef DWC_LIBMODULE ++ ++#ifdef DWC_CCLIB ++/* CC */ ++EXPORT_SYMBOL(dwc_cc_if_alloc); ++EXPORT_SYMBOL(dwc_cc_if_free); ++EXPORT_SYMBOL(dwc_cc_clear); ++EXPORT_SYMBOL(dwc_cc_add); ++EXPORT_SYMBOL(dwc_cc_remove); ++EXPORT_SYMBOL(dwc_cc_change); ++EXPORT_SYMBOL(dwc_cc_data_for_save); ++EXPORT_SYMBOL(dwc_cc_restore_from_data); ++EXPORT_SYMBOL(dwc_cc_match_chid); ++EXPORT_SYMBOL(dwc_cc_match_cdid); ++EXPORT_SYMBOL(dwc_cc_ck); ++EXPORT_SYMBOL(dwc_cc_chid); ++EXPORT_SYMBOL(dwc_cc_cdid); ++EXPORT_SYMBOL(dwc_cc_name); ++#endif /* DWC_CCLIB */ ++ ++#ifdef DWC_CRYPTOLIB ++# ifndef CONFIG_MACH_IPMATE ++/* Modpow */ ++EXPORT_SYMBOL(dwc_modpow); ++ ++/* DH */ ++EXPORT_SYMBOL(dwc_dh_modpow); ++EXPORT_SYMBOL(dwc_dh_derive_keys); ++EXPORT_SYMBOL(dwc_dh_pk); ++# endif /* CONFIG_MACH_IPMATE */ ++ ++/* Crypto */ ++EXPORT_SYMBOL(dwc_wusb_aes_encrypt); ++EXPORT_SYMBOL(dwc_wusb_cmf); ++EXPORT_SYMBOL(dwc_wusb_prf); ++EXPORT_SYMBOL(dwc_wusb_fill_ccm_nonce); ++EXPORT_SYMBOL(dwc_wusb_gen_nonce); ++EXPORT_SYMBOL(dwc_wusb_gen_key); ++EXPORT_SYMBOL(dwc_wusb_gen_mic); ++#endif /* DWC_CRYPTOLIB */ ++ ++/* Notification */ ++#ifdef DWC_NOTIFYLIB ++EXPORT_SYMBOL(dwc_alloc_notification_manager); ++EXPORT_SYMBOL(dwc_free_notification_manager); ++EXPORT_SYMBOL(dwc_register_notifier); ++EXPORT_SYMBOL(dwc_unregister_notifier); ++EXPORT_SYMBOL(dwc_add_observer); ++EXPORT_SYMBOL(dwc_remove_observer); ++EXPORT_SYMBOL(dwc_notify); ++#endif ++ ++/* Memory Debugging Routines */ ++#ifdef DWC_DEBUG_MEMORY ++EXPORT_SYMBOL(dwc_alloc_debug); ++EXPORT_SYMBOL(dwc_alloc_atomic_debug); ++EXPORT_SYMBOL(dwc_free_debug); ++EXPORT_SYMBOL(dwc_dma_alloc_debug); ++EXPORT_SYMBOL(dwc_dma_free_debug); ++#endif ++ ++EXPORT_SYMBOL(DWC_MEMSET); ++EXPORT_SYMBOL(DWC_MEMCPY); ++EXPORT_SYMBOL(DWC_MEMMOVE); ++EXPORT_SYMBOL(DWC_MEMCMP); ++EXPORT_SYMBOL(DWC_STRNCMP); ++EXPORT_SYMBOL(DWC_STRCMP); ++EXPORT_SYMBOL(DWC_STRLEN); ++EXPORT_SYMBOL(DWC_STRCPY); ++EXPORT_SYMBOL(DWC_STRDUP); ++EXPORT_SYMBOL(DWC_ATOI); ++EXPORT_SYMBOL(DWC_ATOUI); ++ ++#ifdef DWC_UTFLIB ++EXPORT_SYMBOL(DWC_UTF8_TO_UTF16LE); ++#endif /* DWC_UTFLIB */ ++ ++EXPORT_SYMBOL(DWC_IN_IRQ); ++EXPORT_SYMBOL(DWC_IN_BH); ++EXPORT_SYMBOL(DWC_VPRINTF); ++EXPORT_SYMBOL(DWC_VSNPRINTF); ++EXPORT_SYMBOL(DWC_PRINTF); ++EXPORT_SYMBOL(DWC_SPRINTF); ++EXPORT_SYMBOL(DWC_SNPRINTF); ++EXPORT_SYMBOL(__DWC_WARN); ++EXPORT_SYMBOL(__DWC_ERROR); ++EXPORT_SYMBOL(DWC_EXCEPTION); ++ ++#ifdef DEBUG ++EXPORT_SYMBOL(__DWC_DEBUG); ++#endif ++ ++EXPORT_SYMBOL(__DWC_DMA_ALLOC); ++EXPORT_SYMBOL(__DWC_DMA_ALLOC_ATOMIC); ++EXPORT_SYMBOL(__DWC_DMA_FREE); ++EXPORT_SYMBOL(__DWC_ALLOC); ++EXPORT_SYMBOL(__DWC_ALLOC_ATOMIC); ++EXPORT_SYMBOL(__DWC_FREE); ++ ++#ifdef DWC_CRYPTOLIB ++EXPORT_SYMBOL(DWC_RANDOM_BYTES); ++EXPORT_SYMBOL(DWC_AES_CBC); ++EXPORT_SYMBOL(DWC_SHA256); ++EXPORT_SYMBOL(DWC_HMAC_SHA256); ++#endif ++ ++EXPORT_SYMBOL(DWC_CPU_TO_LE32); ++EXPORT_SYMBOL(DWC_CPU_TO_BE32); ++EXPORT_SYMBOL(DWC_LE32_TO_CPU); ++EXPORT_SYMBOL(DWC_BE32_TO_CPU); ++EXPORT_SYMBOL(DWC_CPU_TO_LE16); ++EXPORT_SYMBOL(DWC_CPU_TO_BE16); ++EXPORT_SYMBOL(DWC_LE16_TO_CPU); ++EXPORT_SYMBOL(DWC_BE16_TO_CPU); ++EXPORT_SYMBOL(DWC_READ_REG32); ++EXPORT_SYMBOL(DWC_WRITE_REG32); ++EXPORT_SYMBOL(DWC_MODIFY_REG32); ++ ++#if 0 ++EXPORT_SYMBOL(DWC_READ_REG64); ++EXPORT_SYMBOL(DWC_WRITE_REG64); ++EXPORT_SYMBOL(DWC_MODIFY_REG64); ++#endif ++ ++EXPORT_SYMBOL(DWC_SPINLOCK_ALLOC); ++EXPORT_SYMBOL(DWC_SPINLOCK_FREE); ++EXPORT_SYMBOL(DWC_SPINLOCK); ++EXPORT_SYMBOL(DWC_SPINUNLOCK); ++EXPORT_SYMBOL(DWC_SPINLOCK_IRQSAVE); ++EXPORT_SYMBOL(DWC_SPINUNLOCK_IRQRESTORE); ++EXPORT_SYMBOL(DWC_MUTEX_ALLOC); ++ ++#if (!defined(DWC_LINUX) || !defined(CONFIG_DEBUG_MUTEXES)) ++EXPORT_SYMBOL(DWC_MUTEX_FREE); ++#endif ++ ++EXPORT_SYMBOL(DWC_MUTEX_LOCK); ++EXPORT_SYMBOL(DWC_MUTEX_TRYLOCK); ++EXPORT_SYMBOL(DWC_MUTEX_UNLOCK); ++EXPORT_SYMBOL(DWC_UDELAY); ++EXPORT_SYMBOL(DWC_MDELAY); ++EXPORT_SYMBOL(DWC_MSLEEP); ++EXPORT_SYMBOL(DWC_TIME); ++EXPORT_SYMBOL(DWC_TIMER_ALLOC); ++EXPORT_SYMBOL(DWC_TIMER_FREE); ++EXPORT_SYMBOL(DWC_TIMER_SCHEDULE); ++EXPORT_SYMBOL(DWC_TIMER_CANCEL); ++EXPORT_SYMBOL(DWC_WAITQ_ALLOC); ++EXPORT_SYMBOL(DWC_WAITQ_FREE); ++EXPORT_SYMBOL(DWC_WAITQ_WAIT); ++EXPORT_SYMBOL(DWC_WAITQ_WAIT_TIMEOUT); ++EXPORT_SYMBOL(DWC_WAITQ_TRIGGER); ++EXPORT_SYMBOL(DWC_WAITQ_ABORT); ++EXPORT_SYMBOL(DWC_THREAD_RUN); ++EXPORT_SYMBOL(DWC_THREAD_STOP); ++EXPORT_SYMBOL(DWC_THREAD_SHOULD_STOP); ++EXPORT_SYMBOL(DWC_TASK_ALLOC); ++EXPORT_SYMBOL(DWC_TASK_FREE); ++EXPORT_SYMBOL(DWC_TASK_SCHEDULE); ++EXPORT_SYMBOL(DWC_WORKQ_WAIT_WORK_DONE); ++EXPORT_SYMBOL(DWC_WORKQ_ALLOC); ++EXPORT_SYMBOL(DWC_WORKQ_FREE); ++EXPORT_SYMBOL(DWC_WORKQ_SCHEDULE); ++EXPORT_SYMBOL(DWC_WORKQ_SCHEDULE_DELAYED); ++EXPORT_SYMBOL(DWC_WORKQ_PENDING); ++ ++static int dwc_common_port_init_module(void) ++{ ++ int result = 0; ++ ++ printk(KERN_DEBUG "Module dwc_common_port init\n" ); ++ ++#ifdef DWC_DEBUG_MEMORY ++ result = dwc_memory_debug_start(NULL); ++ if (result) { ++ printk(KERN_ERR ++ "dwc_memory_debug_start() failed with error %d\n", ++ result); ++ return result; ++ } ++#endif ++ ++#ifdef DWC_NOTIFYLIB ++ result = dwc_alloc_notification_manager(NULL, NULL); ++ if (result) { ++ printk(KERN_ERR ++ "dwc_alloc_notification_manager() failed with error %d\n", ++ result); ++ return result; ++ } ++#endif ++ return result; ++} ++ ++static void dwc_common_port_exit_module(void) ++{ ++ printk(KERN_DEBUG "Module dwc_common_port exit\n" ); ++ ++#ifdef DWC_NOTIFYLIB ++ dwc_free_notification_manager(); ++#endif ++ ++#ifdef DWC_DEBUG_MEMORY ++ dwc_memory_debug_stop(); ++#endif ++} ++ ++module_init(dwc_common_port_init_module); ++module_exit(dwc_common_port_exit_module); ++ ++MODULE_DESCRIPTION("DWC Common Library - Portable version"); ++MODULE_AUTHOR("Synopsys Inc."); ++MODULE_LICENSE ("GPL"); ++ ++#endif /* DWC_LIBMODULE */ +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_common_nbsd.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_common_nbsd.c +--- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_common_nbsd.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_common_nbsd.c 2015-11-29 09:42:39.915098960 +0100 +@@ -0,0 +1,1275 @@ ++#include "dwc_os.h" ++#include "dwc_list.h" ++ ++#ifdef DWC_CCLIB ++# include "dwc_cc.h" ++#endif ++ ++#ifdef DWC_CRYPTOLIB ++# include "dwc_modpow.h" ++# include "dwc_dh.h" ++# include "dwc_crypto.h" ++#endif ++ ++#ifdef DWC_NOTIFYLIB ++# include "dwc_notifier.h" ++#endif ++ ++/* OS-Level Implementations */ ++ ++/* This is the NetBSD 4.0.1 kernel implementation of the DWC platform library. */ ++ ++ ++/* MISC */ ++ ++void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size) ++{ ++ return memset(dest, byte, size); ++} ++ ++void *DWC_MEMCPY(void *dest, void const *src, uint32_t size) ++{ ++ return memcpy(dest, src, size); ++} ++ ++void *DWC_MEMMOVE(void *dest, void *src, uint32_t size) ++{ ++ bcopy(src, dest, size); ++ return dest; ++} ++ ++int DWC_MEMCMP(void *m1, void *m2, uint32_t size) ++{ ++ return memcmp(m1, m2, size); ++} ++ ++int DWC_STRNCMP(void *s1, void *s2, uint32_t size) ++{ ++ return strncmp(s1, s2, size); ++} ++ ++int DWC_STRCMP(void *s1, void *s2) ++{ ++ return strcmp(s1, s2); ++} ++ ++int DWC_STRLEN(char const *str) ++{ ++ return strlen(str); ++} ++ ++char *DWC_STRCPY(char *to, char const *from) ++{ ++ return strcpy(to, from); ++} ++ ++char *DWC_STRDUP(char const *str) ++{ ++ int len = DWC_STRLEN(str) + 1; ++ char *new = DWC_ALLOC_ATOMIC(len); ++ ++ if (!new) { ++ return NULL; ++ } ++ ++ DWC_MEMCPY(new, str, len); ++ return new; ++} ++ ++int DWC_ATOI(char *str, int32_t *value) ++{ ++ char *end = NULL; ++ ++ /* NetBSD doesn't have 'strtol' in the kernel, but 'strtoul' ++ * should be equivalent on 2's complement machines ++ */ ++ *value = strtoul(str, &end, 0); ++ if (*end == '\0') { ++ return 0; ++ } ++ ++ return -1; ++} ++ ++int DWC_ATOUI(char *str, uint32_t *value) ++{ ++ char *end = NULL; ++ ++ *value = strtoul(str, &end, 0); ++ if (*end == '\0') { ++ return 0; ++ } ++ ++ return -1; ++} ++ ++ ++#ifdef DWC_UTFLIB ++/* From usbstring.c */ ++ ++int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len) ++{ ++ int count = 0; ++ u8 c; ++ u16 uchar; ++ ++ /* this insists on correct encodings, though not minimal ones. ++ * BUT it currently rejects legit 4-byte UTF-8 code points, ++ * which need surrogate pairs. (Unicode 3.1 can use them.) ++ */ ++ while (len != 0 && (c = (u8) *s++) != 0) { ++ if (unlikely(c & 0x80)) { ++ // 2-byte sequence: ++ // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx ++ if ((c & 0xe0) == 0xc0) { ++ uchar = (c & 0x1f) << 6; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c; ++ ++ // 3-byte sequence (most CJKV characters): ++ // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx ++ } else if ((c & 0xf0) == 0xe0) { ++ uchar = (c & 0x0f) << 12; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c << 6; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c; ++ ++ /* no bogus surrogates */ ++ if (0xd800 <= uchar && uchar <= 0xdfff) ++ goto fail; ++ ++ // 4-byte sequence (surrogate pairs, currently rare): ++ // 11101110wwwwzzzzyy + 110111yyyyxxxxxx ++ // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx ++ // (uuuuu = wwww + 1) ++ // FIXME accept the surrogate code points (only) ++ } else ++ goto fail; ++ } else ++ uchar = c; ++ put_unaligned (cpu_to_le16 (uchar), cp++); ++ count++; ++ len--; ++ } ++ return count; ++fail: ++ return -1; ++} ++ ++#endif /* DWC_UTFLIB */ ++ ++ ++/* dwc_debug.h */ ++ ++dwc_bool_t DWC_IN_IRQ(void) ++{ ++// return in_irq(); ++ return 0; ++} ++ ++dwc_bool_t DWC_IN_BH(void) ++{ ++// return in_softirq(); ++ return 0; ++} ++ ++void DWC_VPRINTF(char *format, va_list args) ++{ ++ vprintf(format, args); ++} ++ ++int DWC_VSNPRINTF(char *str, int size, char *format, va_list args) ++{ ++ return vsnprintf(str, size, format, args); ++} ++ ++void DWC_PRINTF(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++ ++int DWC_SPRINTF(char *buffer, char *format, ...) ++{ ++ int retval; ++ va_list args; ++ ++ va_start(args, format); ++ retval = vsprintf(buffer, format, args); ++ va_end(args); ++ return retval; ++} ++ ++int DWC_SNPRINTF(char *buffer, int size, char *format, ...) ++{ ++ int retval; ++ va_list args; ++ ++ va_start(args, format); ++ retval = vsnprintf(buffer, size, format, args); ++ va_end(args); ++ return retval; ++} ++ ++void __DWC_WARN(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++ ++void __DWC_ERROR(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++ ++void DWC_EXCEPTION(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++// BUG_ON(1); ??? ++} ++ ++#ifdef DEBUG ++void __DWC_DEBUG(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++#endif ++ ++ ++/* dwc_mem.h */ ++ ++#if 0 ++dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size, ++ uint32_t align, ++ uint32_t alloc) ++{ ++ struct dma_pool *pool = dma_pool_create("Pool", NULL, ++ size, align, alloc); ++ return (dwc_pool_t *)pool; ++} ++ ++void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool) ++{ ++ dma_pool_destroy((struct dma_pool *)pool); ++} ++ ++void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr) ++{ ++// return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr); ++ return dma_pool_alloc((struct dma_pool *)pool, M_WAITOK, dma_addr); ++} ++ ++void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr) ++{ ++ void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr); ++ memset(..); ++} ++ ++void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr) ++{ ++ dma_pool_free(pool, vaddr, daddr); ++} ++#endif ++ ++void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr) ++{ ++ dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx; ++ int error; ++ ++ error = bus_dmamem_alloc(dma->dma_tag, size, 1, size, dma->segs, ++ sizeof(dma->segs) / sizeof(dma->segs[0]), ++ &dma->nsegs, BUS_DMA_NOWAIT); ++ if (error) { ++ printf("%s: bus_dmamem_alloc(%ju) failed: %d\n", __func__, ++ (uintmax_t)size, error); ++ goto fail_0; ++ } ++ ++ error = bus_dmamem_map(dma->dma_tag, dma->segs, dma->nsegs, size, ++ (caddr_t *)&dma->dma_vaddr, ++ BUS_DMA_NOWAIT | BUS_DMA_COHERENT); ++ if (error) { ++ printf("%s: bus_dmamem_map failed: %d\n", __func__, error); ++ goto fail_1; ++ } ++ ++ error = bus_dmamap_create(dma->dma_tag, size, 1, size, 0, ++ BUS_DMA_NOWAIT, &dma->dma_map); ++ if (error) { ++ printf("%s: bus_dmamap_create failed: %d\n", __func__, error); ++ goto fail_2; ++ } ++ ++ error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, ++ size, NULL, BUS_DMA_NOWAIT); ++ if (error) { ++ printf("%s: bus_dmamap_load failed: %d\n", __func__, error); ++ goto fail_3; ++ } ++ ++ dma->dma_paddr = (bus_addr_t)dma->segs[0].ds_addr; ++ *dma_addr = dma->dma_paddr; ++ return dma->dma_vaddr; ++ ++fail_3: ++ bus_dmamap_destroy(dma->dma_tag, dma->dma_map); ++fail_2: ++ bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size); ++fail_1: ++ bus_dmamem_free(dma->dma_tag, dma->segs, dma->nsegs); ++fail_0: ++ dma->dma_map = NULL; ++ dma->dma_vaddr = NULL; ++ dma->nsegs = 0; ++ ++ return NULL; ++} ++ ++void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr) ++{ ++ dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx; ++ ++ if (dma->dma_map != NULL) { ++ bus_dmamap_sync(dma->dma_tag, dma->dma_map, 0, size, ++ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); ++ bus_dmamap_unload(dma->dma_tag, dma->dma_map); ++ bus_dmamap_destroy(dma->dma_tag, dma->dma_map); ++ bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size); ++ bus_dmamem_free(dma->dma_tag, dma->segs, dma->nsegs); ++ dma->dma_paddr = 0; ++ dma->dma_map = NULL; ++ dma->dma_vaddr = NULL; ++ dma->nsegs = 0; ++ } ++} ++ ++void *__DWC_ALLOC(void *mem_ctx, uint32_t size) ++{ ++ return malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); ++} ++ ++void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size) ++{ ++ return malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO); ++} ++ ++void __DWC_FREE(void *mem_ctx, void *addr) ++{ ++ free(addr, M_DEVBUF); ++} ++ ++ ++#ifdef DWC_CRYPTOLIB ++/* dwc_crypto.h */ ++ ++void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length) ++{ ++ get_random_bytes(buffer, length); ++} ++ ++int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out) ++{ ++ struct crypto_blkcipher *tfm; ++ struct blkcipher_desc desc; ++ struct scatterlist sgd; ++ struct scatterlist sgs; ++ ++ tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC); ++ if (tfm == NULL) { ++ printk("failed to load transform for aes CBC\n"); ++ return -1; ++ } ++ ++ crypto_blkcipher_setkey(tfm, key, keylen); ++ crypto_blkcipher_set_iv(tfm, iv, 16); ++ ++ sg_init_one(&sgd, out, messagelen); ++ sg_init_one(&sgs, message, messagelen); ++ ++ desc.tfm = tfm; ++ desc.flags = 0; ++ ++ if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) { ++ crypto_free_blkcipher(tfm); ++ DWC_ERROR("AES CBC encryption failed"); ++ return -1; ++ } ++ ++ crypto_free_blkcipher(tfm); ++ return 0; ++} ++ ++int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out) ++{ ++ struct crypto_hash *tfm; ++ struct hash_desc desc; ++ struct scatterlist sg; ++ ++ tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC); ++ if (IS_ERR(tfm)) { ++ DWC_ERROR("Failed to load transform for sha256: %ld", PTR_ERR(tfm)); ++ return 0; ++ } ++ desc.tfm = tfm; ++ desc.flags = 0; ++ ++ sg_init_one(&sg, message, len); ++ crypto_hash_digest(&desc, &sg, len, out); ++ crypto_free_hash(tfm); ++ ++ return 1; ++} ++ ++int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen, ++ uint8_t *key, uint32_t keylen, uint8_t *out) ++{ ++ struct crypto_hash *tfm; ++ struct hash_desc desc; ++ struct scatterlist sg; ++ ++ tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC); ++ if (IS_ERR(tfm)) { ++ DWC_ERROR("Failed to load transform for hmac(sha256): %ld", PTR_ERR(tfm)); ++ return 0; ++ } ++ desc.tfm = tfm; ++ desc.flags = 0; ++ ++ sg_init_one(&sg, message, messagelen); ++ crypto_hash_setkey(tfm, key, keylen); ++ crypto_hash_digest(&desc, &sg, messagelen, out); ++ crypto_free_hash(tfm); ++ ++ return 1; ++} ++ ++#endif /* DWC_CRYPTOLIB */ ++ ++ ++/* Byte Ordering Conversions */ ++ ++uint32_t DWC_CPU_TO_LE32(uint32_t *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++ ++uint32_t DWC_CPU_TO_BE32(uint32_t *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++ ++uint32_t DWC_LE32_TO_CPU(uint32_t *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++ ++uint32_t DWC_BE32_TO_CPU(uint32_t *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++ ++uint16_t DWC_CPU_TO_LE16(uint16_t *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++ ++uint16_t DWC_CPU_TO_BE16(uint16_t *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++ ++uint16_t DWC_LE16_TO_CPU(uint16_t *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++ ++uint16_t DWC_BE16_TO_CPU(uint16_t *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++ ++ ++/* Registers */ ++ ++uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ return bus_space_read_4(io->iot, io->ioh, ior); ++} ++ ++#if 0 ++uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ return bus_space_read_8(io->iot, io->ioh, ior); ++} ++#endif ++ ++void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ bus_space_write_4(io->iot, io->ioh, ior, value); ++} ++ ++#if 0 ++void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ bus_space_write_8(io->iot, io->ioh, ior, value); ++} ++#endif ++ ++void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask, ++ uint32_t set_mask) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ bus_space_write_4(io->iot, io->ioh, ior, ++ (bus_space_read_4(io->iot, io->ioh, ior) & ++ ~clear_mask) | set_mask); ++} ++ ++#if 0 ++void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask, ++ uint64_t set_mask) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ bus_space_write_8(io->iot, io->ioh, ior, ++ (bus_space_read_8(io->iot, io->ioh, ior) & ++ ~clear_mask) | set_mask); ++} ++#endif ++ ++ ++/* Locking */ ++ ++dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void) ++{ ++ struct simplelock *sl = DWC_ALLOC(sizeof(*sl)); ++ ++ if (!sl) { ++ DWC_ERROR("Cannot allocate memory for spinlock"); ++ return NULL; ++ } ++ ++ simple_lock_init(sl); ++ return (dwc_spinlock_t *)sl; ++} ++ ++void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock) ++{ ++ struct simplelock *sl = (struct simplelock *)lock; ++ ++ DWC_FREE(sl); ++} ++ ++void DWC_SPINLOCK(dwc_spinlock_t *lock) ++{ ++ simple_lock((struct simplelock *)lock); ++} ++ ++void DWC_SPINUNLOCK(dwc_spinlock_t *lock) ++{ ++ simple_unlock((struct simplelock *)lock); ++} ++ ++void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags) ++{ ++ simple_lock((struct simplelock *)lock); ++ *flags = splbio(); ++} ++ ++void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags) ++{ ++ splx(flags); ++ simple_unlock((struct simplelock *)lock); ++} ++ ++dwc_mutex_t *DWC_MUTEX_ALLOC(void) ++{ ++ dwc_mutex_t *mutex = DWC_ALLOC(sizeof(struct lock)); ++ ++ if (!mutex) { ++ DWC_ERROR("Cannot allocate memory for mutex"); ++ return NULL; ++ } ++ ++ lockinit((struct lock *)mutex, 0, "dw3mtx", 0, 0); ++ return mutex; ++} ++ ++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)) ++#else ++void DWC_MUTEX_FREE(dwc_mutex_t *mutex) ++{ ++ DWC_FREE(mutex); ++} ++#endif ++ ++void DWC_MUTEX_LOCK(dwc_mutex_t *mutex) ++{ ++ lockmgr((struct lock *)mutex, LK_EXCLUSIVE, NULL); ++} ++ ++int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex) ++{ ++ int status; ++ ++ status = lockmgr((struct lock *)mutex, LK_EXCLUSIVE | LK_NOWAIT, NULL); ++ return status == 0; ++} ++ ++void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex) ++{ ++ lockmgr((struct lock *)mutex, LK_RELEASE, NULL); ++} ++ ++ ++/* Timing */ ++ ++void DWC_UDELAY(uint32_t usecs) ++{ ++ DELAY(usecs); ++} ++ ++void DWC_MDELAY(uint32_t msecs) ++{ ++ do { ++ DELAY(1000); ++ } while (--msecs); ++} ++ ++void DWC_MSLEEP(uint32_t msecs) ++{ ++ struct timeval tv; ++ ++ tv.tv_sec = msecs / 1000; ++ tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000; ++ tsleep(&tv, 0, "dw3slp", tvtohz(&tv)); ++} ++ ++uint32_t DWC_TIME(void) ++{ ++ struct timeval tv; ++ ++ microuptime(&tv); // or getmicrouptime? (less precise, but faster) ++ return tv.tv_sec * 1000 + tv.tv_usec / 1000; ++} ++ ++ ++/* Timers */ ++ ++struct dwc_timer { ++ struct callout t; ++ char *name; ++ dwc_spinlock_t *lock; ++ dwc_timer_callback_t cb; ++ void *data; ++}; ++ ++dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data) ++{ ++ dwc_timer_t *t = DWC_ALLOC(sizeof(*t)); ++ ++ if (!t) { ++ DWC_ERROR("Cannot allocate memory for timer"); ++ return NULL; ++ } ++ ++ callout_init(&t->t); ++ ++ t->name = DWC_STRDUP(name); ++ if (!t->name) { ++ DWC_ERROR("Cannot allocate memory for timer->name"); ++ goto no_name; ++ } ++ ++ t->lock = DWC_SPINLOCK_ALLOC(); ++ if (!t->lock) { ++ DWC_ERROR("Cannot allocate memory for timer->lock"); ++ goto no_lock; ++ } ++ ++ t->cb = cb; ++ t->data = data; ++ ++ return t; ++ ++ no_lock: ++ DWC_FREE(t->name); ++ no_name: ++ DWC_FREE(t); ++ ++ return NULL; ++} ++ ++void DWC_TIMER_FREE(dwc_timer_t *timer) ++{ ++ callout_stop(&timer->t); ++ DWC_SPINLOCK_FREE(timer->lock); ++ DWC_FREE(timer->name); ++ DWC_FREE(timer); ++} ++ ++void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time) ++{ ++ struct timeval tv; ++ ++ tv.tv_sec = time / 1000; ++ tv.tv_usec = (time - tv.tv_sec * 1000) * 1000; ++ callout_reset(&timer->t, tvtohz(&tv), timer->cb, timer->data); ++} ++ ++void DWC_TIMER_CANCEL(dwc_timer_t *timer) ++{ ++ callout_stop(&timer->t); ++} ++ ++ ++/* Wait Queues */ ++ ++struct dwc_waitq { ++ struct simplelock lock; ++ int abort; ++}; ++ ++dwc_waitq_t *DWC_WAITQ_ALLOC(void) ++{ ++ dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq)); ++ ++ if (!wq) { ++ DWC_ERROR("Cannot allocate memory for waitqueue"); ++ return NULL; ++ } ++ ++ simple_lock_init(&wq->lock); ++ wq->abort = 0; ++ ++ return wq; ++} ++ ++void DWC_WAITQ_FREE(dwc_waitq_t *wq) ++{ ++ DWC_FREE(wq); ++} ++ ++int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data) ++{ ++ int ipl; ++ int result = 0; ++ ++ simple_lock(&wq->lock); ++ ipl = splbio(); ++ ++ /* Skip the sleep if already aborted or triggered */ ++ if (!wq->abort && !cond(data)) { ++ splx(ipl); ++ result = ltsleep(wq, PCATCH, "dw3wat", 0, &wq->lock); // infinite timeout ++ ipl = splbio(); ++ } ++ ++ if (result == 0) { // awoken ++ if (wq->abort) { ++ wq->abort = 0; ++ result = -DWC_E_ABORT; ++ } else { ++ result = 0; ++ } ++ ++ splx(ipl); ++ simple_unlock(&wq->lock); ++ } else { ++ wq->abort = 0; ++ splx(ipl); ++ simple_unlock(&wq->lock); ++ ++ if (result == ERESTART) { // signaled - restart ++ result = -DWC_E_RESTART; ++ } else { // signaled - must be EINTR ++ result = -DWC_E_ABORT; ++ } ++ } ++ ++ return result; ++} ++ ++int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, ++ void *data, int32_t msecs) ++{ ++ struct timeval tv, tv1, tv2; ++ int ipl; ++ int result = 0; ++ ++ tv.tv_sec = msecs / 1000; ++ tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000; ++ ++ simple_lock(&wq->lock); ++ ipl = splbio(); ++ ++ /* Skip the sleep if already aborted or triggered */ ++ if (!wq->abort && !cond(data)) { ++ splx(ipl); ++ getmicrouptime(&tv1); ++ result = ltsleep(wq, PCATCH, "dw3wto", tvtohz(&tv), &wq->lock); ++ getmicrouptime(&tv2); ++ ipl = splbio(); ++ } ++ ++ if (result == 0) { // awoken ++ if (wq->abort) { ++ wq->abort = 0; ++ splx(ipl); ++ simple_unlock(&wq->lock); ++ result = -DWC_E_ABORT; ++ } else { ++ splx(ipl); ++ simple_unlock(&wq->lock); ++ ++ tv2.tv_usec -= tv1.tv_usec; ++ if (tv2.tv_usec < 0) { ++ tv2.tv_usec += 1000000; ++ tv2.tv_sec--; ++ } ++ ++ tv2.tv_sec -= tv1.tv_sec; ++ result = tv2.tv_sec * 1000 + tv2.tv_usec / 1000; ++ result = msecs - result; ++ if (result <= 0) ++ result = 1; ++ } ++ } else { ++ wq->abort = 0; ++ splx(ipl); ++ simple_unlock(&wq->lock); ++ ++ if (result == ERESTART) { // signaled - restart ++ result = -DWC_E_RESTART; ++ ++ } else if (result == EINTR) { // signaled - interrupt ++ result = -DWC_E_ABORT; ++ ++ } else { // timed out ++ result = -DWC_E_TIMEOUT; ++ } ++ } ++ ++ return result; ++} ++ ++void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq) ++{ ++ wakeup(wq); ++} ++ ++void DWC_WAITQ_ABORT(dwc_waitq_t *wq) ++{ ++ int ipl; ++ ++ simple_lock(&wq->lock); ++ ipl = splbio(); ++ wq->abort = 1; ++ wakeup(wq); ++ splx(ipl); ++ simple_unlock(&wq->lock); ++} ++ ++ ++/* Threading */ ++ ++struct dwc_thread { ++ struct proc *proc; ++ int abort; ++}; ++ ++dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data) ++{ ++ int retval; ++ dwc_thread_t *thread = DWC_ALLOC(sizeof(*thread)); ++ ++ if (!thread) { ++ return NULL; ++ } ++ ++ thread->abort = 0; ++ retval = kthread_create1((void (*)(void *))func, data, &thread->proc, ++ "%s", name); ++ if (retval) { ++ DWC_FREE(thread); ++ return NULL; ++ } ++ ++ return thread; ++} ++ ++int DWC_THREAD_STOP(dwc_thread_t *thread) ++{ ++ int retval; ++ ++ thread->abort = 1; ++ retval = tsleep(&thread->abort, 0, "dw3stp", 60 * hz); ++ ++ if (retval == 0) { ++ /* DWC_THREAD_EXIT() will free the thread struct */ ++ return 0; ++ } ++ ++ /* NOTE: We leak the thread struct if thread doesn't die */ ++ ++ if (retval == EWOULDBLOCK) { ++ return -DWC_E_TIMEOUT; ++ } ++ ++ return -DWC_E_UNKNOWN; ++} ++ ++dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread) ++{ ++ return thread->abort; ++} ++ ++void DWC_THREAD_EXIT(dwc_thread_t *thread) ++{ ++ wakeup(&thread->abort); ++ DWC_FREE(thread); ++ kthread_exit(0); ++} ++ ++/* tasklets ++ - Runs in interrupt context (cannot sleep) ++ - Each tasklet runs on a single CPU ++ - Different tasklets can be running simultaneously on different CPUs ++ [ On NetBSD there is no corresponding mechanism, drivers don't have bottom- ++ halves. So we just call the callback directly from DWC_TASK_SCHEDULE() ] ++ */ ++struct dwc_tasklet { ++ dwc_tasklet_callback_t cb; ++ void *data; ++}; ++ ++static void tasklet_callback(void *data) ++{ ++ dwc_tasklet_t *task = (dwc_tasklet_t *)data; ++ ++ task->cb(task->data); ++} ++ ++dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data) ++{ ++ dwc_tasklet_t *task = DWC_ALLOC(sizeof(*task)); ++ ++ if (task) { ++ task->cb = cb; ++ task->data = data; ++ } else { ++ DWC_ERROR("Cannot allocate memory for tasklet"); ++ } ++ ++ return task; ++} ++ ++void DWC_TASK_FREE(dwc_tasklet_t *task) ++{ ++ DWC_FREE(task); ++} ++ ++void DWC_TASK_SCHEDULE(dwc_tasklet_t *task) ++{ ++ tasklet_callback(task); ++} ++ ++ ++/* workqueues ++ - Runs in process context (can sleep) ++ */ ++typedef struct work_container { ++ dwc_work_callback_t cb; ++ void *data; ++ dwc_workq_t *wq; ++ char *name; ++ int hz; ++ struct work task; ++} work_container_t; ++ ++struct dwc_workq { ++ struct workqueue *taskq; ++ dwc_spinlock_t *lock; ++ dwc_waitq_t *waitq; ++ int pending; ++ struct work_container *container; ++}; ++ ++static void do_work(struct work *task, void *data) ++{ ++ dwc_workq_t *wq = (dwc_workq_t *)data; ++ work_container_t *container = wq->container; ++ dwc_irqflags_t flags; ++ ++ if (container->hz) { ++ tsleep(container, 0, "dw3wrk", container->hz); ++ } ++ ++ container->cb(container->data); ++ DWC_DEBUG("Work done: %s, container=%p", container->name, container); ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ if (container->name) ++ DWC_FREE(container->name); ++ DWC_FREE(container); ++ wq->pending--; ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++ DWC_WAITQ_TRIGGER(wq->waitq); ++} ++ ++static int work_done(void *data) ++{ ++ dwc_workq_t *workq = (dwc_workq_t *)data; ++ ++ return workq->pending == 0; ++} ++ ++int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout) ++{ ++ return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout); ++} ++ ++dwc_workq_t *DWC_WORKQ_ALLOC(char *name) ++{ ++ int result; ++ dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq)); ++ ++ if (!wq) { ++ DWC_ERROR("Cannot allocate memory for workqueue"); ++ return NULL; ++ } ++ ++ result = workqueue_create(&wq->taskq, name, do_work, wq, 0 /*PWAIT*/, ++ IPL_BIO, 0); ++ if (result) { ++ DWC_ERROR("Cannot create workqueue"); ++ goto no_taskq; ++ } ++ ++ wq->pending = 0; ++ ++ wq->lock = DWC_SPINLOCK_ALLOC(); ++ if (!wq->lock) { ++ DWC_ERROR("Cannot allocate memory for spinlock"); ++ goto no_lock; ++ } ++ ++ wq->waitq = DWC_WAITQ_ALLOC(); ++ if (!wq->waitq) { ++ DWC_ERROR("Cannot allocate memory for waitqueue"); ++ goto no_waitq; ++ } ++ ++ return wq; ++ ++ no_waitq: ++ DWC_SPINLOCK_FREE(wq->lock); ++ no_lock: ++ workqueue_destroy(wq->taskq); ++ no_taskq: ++ DWC_FREE(wq); ++ ++ return NULL; ++} ++ ++void DWC_WORKQ_FREE(dwc_workq_t *wq) ++{ ++#ifdef DEBUG ++ dwc_irqflags_t flags; ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ ++ if (wq->pending != 0) { ++ struct work_container *container = wq->container; ++ ++ DWC_ERROR("Destroying work queue with pending work"); ++ ++ if (container && container->name) { ++ DWC_ERROR("Work %s still pending", container->name); ++ } ++ } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++#endif ++ DWC_WAITQ_FREE(wq->waitq); ++ DWC_SPINLOCK_FREE(wq->lock); ++ workqueue_destroy(wq->taskq); ++ DWC_FREE(wq); ++} ++ ++void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data, ++ char *format, ...) ++{ ++ dwc_irqflags_t flags; ++ work_container_t *container; ++ static char name[128]; ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VSNPRINTF(name, 128, format, args); ++ va_end(args); ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ wq->pending++; ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++ DWC_WAITQ_TRIGGER(wq->waitq); ++ ++ container = DWC_ALLOC_ATOMIC(sizeof(*container)); ++ if (!container) { ++ DWC_ERROR("Cannot allocate memory for container"); ++ return; ++ } ++ ++ container->name = DWC_STRDUP(name); ++ if (!container->name) { ++ DWC_ERROR("Cannot allocate memory for container->name"); ++ DWC_FREE(container); ++ return; ++ } ++ ++ container->cb = cb; ++ container->data = data; ++ container->wq = wq; ++ container->hz = 0; ++ wq->container = container; ++ ++ DWC_DEBUG("Queueing work: %s, container=%p", container->name, container); ++ workqueue_enqueue(wq->taskq, &container->task); ++} ++ ++void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb, ++ void *data, uint32_t time, char *format, ...) ++{ ++ dwc_irqflags_t flags; ++ work_container_t *container; ++ static char name[128]; ++ struct timeval tv; ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VSNPRINTF(name, 128, format, args); ++ va_end(args); ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ wq->pending++; ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++ DWC_WAITQ_TRIGGER(wq->waitq); ++ ++ container = DWC_ALLOC_ATOMIC(sizeof(*container)); ++ if (!container) { ++ DWC_ERROR("Cannot allocate memory for container"); ++ return; ++ } ++ ++ container->name = DWC_STRDUP(name); ++ if (!container->name) { ++ DWC_ERROR("Cannot allocate memory for container->name"); ++ DWC_FREE(container); ++ return; ++ } ++ ++ container->cb = cb; ++ container->data = data; ++ container->wq = wq; ++ tv.tv_sec = time / 1000; ++ tv.tv_usec = (time - tv.tv_sec * 1000) * 1000; ++ container->hz = tvtohz(&tv); ++ wq->container = container; ++ ++ DWC_DEBUG("Queueing work: %s, container=%p", container->name, container); ++ workqueue_enqueue(wq->taskq, &container->task); ++} ++ ++int DWC_WORKQ_PENDING(dwc_workq_t *wq) ++{ ++ return wq->pending; ++} +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_crypto.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_crypto.c +--- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_crypto.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_crypto.c 2015-11-29 09:42:39.915098960 +0100 +@@ -0,0 +1,308 @@ ++/* ========================================================================= ++ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_crypto.c $ ++ * $Revision: #5 $ ++ * $Date: 2010/09/28 $ ++ * $Change: 1596182 $ ++ * ++ * Synopsys Portability Library Software and documentation ++ * (hereinafter, "Software") is an Unsupported proprietary work of ++ * Synopsys, Inc. unless otherwise expressly agreed to in writing ++ * between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for ++ * Licensed Product with Synopsys or any supplement thereto. You are ++ * permitted to use and redistribute this Software in source and binary ++ * forms, with or without modification, provided that redistributions ++ * of source code must retain this notice. You may not view, use, ++ * disclose, copy or distribute this file or any information contained ++ * herein except pursuant to this license grant from Synopsys. If you ++ * do not agree with this notice, including the disclaimer below, then ++ * you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ++ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL ++ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY ++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE ++ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================= */ ++ ++/** @file ++ * This file contains the WUSB cryptographic routines. ++ */ ++ ++#ifdef DWC_CRYPTOLIB ++ ++#include "dwc_crypto.h" ++#include "usb.h" ++ ++#ifdef DEBUG ++static inline void dump_bytes(char *name, uint8_t *bytes, int len) ++{ ++ int i; ++ DWC_PRINTF("%s: ", name); ++ for (i=0; idst == src, then the bytes will be encrypted ++ * in-place. ++ * ++ * @return 0 on success, negative error code on error. ++ */ ++int dwc_wusb_aes_encrypt(u8 *src, u8 *key, u8 *dst) ++{ ++ u8 block_t[16]; ++ DWC_MEMSET(block_t, 0, 16); ++ ++ return DWC_AES_CBC(src, 16, key, 16, block_t, dst); ++} ++ ++/** ++ * The CCM-MAC-FUNCTION described in section 6.5 of the WUSB spec. ++ * This function takes a data string and returns the encrypted CBC ++ * Counter-mode MIC. ++ * ++ * @param key The 128-bit symmetric key. ++ * @param nonce The CCM nonce. ++ * @param label The unique 14-byte ASCII text label. ++ * @param bytes The byte array to be encrypted. ++ * @param len Length of the byte array. ++ * @param result Byte array to receive the 8-byte encrypted MIC. ++ */ ++void dwc_wusb_cmf(u8 *key, u8 *nonce, ++ char *label, u8 *bytes, int len, u8 *result) ++{ ++ u8 block_m[16]; ++ u8 block_x[16]; ++ u8 block_t[8]; ++ int idx, blkNum; ++ u16 la = (u16)(len + 14); ++ ++ /* Set the AES-128 key */ ++ //dwc_aes_setkey(tfm, key, 16); ++ ++ /* Fill block B0 from flags = 0x59, N, and l(m) = 0 */ ++ block_m[0] = 0x59; ++ for (idx = 0; idx < 13; idx++) ++ block_m[idx + 1] = nonce[idx]; ++ block_m[14] = 0; ++ block_m[15] = 0; ++ ++ /* Produce the CBC IV */ ++ dwc_wusb_aes_encrypt(block_m, key, block_x); ++ show_block(block_m, "CBC IV in: ", "\n", 0); ++ show_block(block_x, "CBC IV out:", "\n", 0); ++ ++ /* Fill block B1 from l(a) = Blen + 14, and A */ ++ block_x[0] ^= (u8)(la >> 8); ++ block_x[1] ^= (u8)la; ++ for (idx = 0; idx < 14; idx++) ++ block_x[idx + 2] ^= label[idx]; ++ show_block(block_x, "After xor: ", "b1\n", 16); ++ ++ dwc_wusb_aes_encrypt(block_x, key, block_x); ++ show_block(block_x, "After AES: ", "b1\n", 16); ++ ++ idx = 0; ++ blkNum = 0; ++ ++ /* Fill remaining blocks with B */ ++ while (len-- > 0) { ++ block_x[idx] ^= *bytes++; ++ if (++idx >= 16) { ++ idx = 0; ++ show_block(block_x, "After xor: ", "\n", blkNum); ++ dwc_wusb_aes_encrypt(block_x, key, block_x); ++ show_block(block_x, "After AES: ", "\n", blkNum); ++ blkNum++; ++ } ++ } ++ ++ /* Handle partial last block */ ++ if (idx > 0) { ++ show_block(block_x, "After xor: ", "\n", blkNum); ++ dwc_wusb_aes_encrypt(block_x, key, block_x); ++ show_block(block_x, "After AES: ", "\n", blkNum); ++ } ++ ++ /* Save the MIC tag */ ++ DWC_MEMCPY(block_t, block_x, 8); ++ show_block(block_t, "MIC tag : ", NULL, 8); ++ ++ /* Fill block A0 from flags = 0x01, N, and counter = 0 */ ++ block_m[0] = 0x01; ++ block_m[14] = 0; ++ block_m[15] = 0; ++ ++ /* Encrypt the counter */ ++ dwc_wusb_aes_encrypt(block_m, key, block_x); ++ show_block(block_x, "CTR[MIC] : ", NULL, 8); ++ ++ /* XOR with MIC tag */ ++ for (idx = 0; idx < 8; idx++) { ++ block_t[idx] ^= block_x[idx]; ++ } ++ ++ /* Return result to caller */ ++ DWC_MEMCPY(result, block_t, 8); ++ show_block(result, "CCM-MIC : ", NULL, 8); ++ ++} ++ ++/** ++ * The PRF function described in section 6.5 of the WUSB spec. This function ++ * concatenates MIC values returned from dwc_cmf() to create a value of ++ * the requested length. ++ * ++ * @param prf_len Length of the PRF function in bits (64, 128, or 256). ++ * @param key, nonce, label, bytes, len Same as for dwc_cmf(). ++ * @param result Byte array to receive the result. ++ */ ++void dwc_wusb_prf(int prf_len, u8 *key, ++ u8 *nonce, char *label, u8 *bytes, int len, u8 *result) ++{ ++ int i; ++ ++ nonce[0] = 0; ++ for (i = 0; i < prf_len >> 6; i++, nonce[0]++) { ++ dwc_wusb_cmf(key, nonce, label, bytes, len, result); ++ result += 8; ++ } ++} ++ ++/** ++ * Fills in CCM Nonce per the WUSB spec. ++ * ++ * @param[in] haddr Host address. ++ * @param[in] daddr Device address. ++ * @param[in] tkid Session Key(PTK) identifier. ++ * @param[out] nonce Pointer to where the CCM Nonce output is to be written. ++ */ ++void dwc_wusb_fill_ccm_nonce(uint16_t haddr, uint16_t daddr, uint8_t *tkid, ++ uint8_t *nonce) ++{ ++ ++ DWC_DEBUG("%s %x %x\n", __func__, daddr, haddr); ++ ++ DWC_MEMSET(&nonce[0], 0, 16); ++ ++ DWC_MEMCPY(&nonce[6], tkid, 3); ++ nonce[9] = daddr & 0xFF; ++ nonce[10] = (daddr >> 8) & 0xFF; ++ nonce[11] = haddr & 0xFF; ++ nonce[12] = (haddr >> 8) & 0xFF; ++ ++ dump_bytes("CCM nonce", nonce, 16); ++} ++ ++/** ++ * Generates a 16-byte cryptographic-grade random number for the Host/Device ++ * Nonce. ++ */ ++void dwc_wusb_gen_nonce(uint16_t addr, uint8_t *nonce) ++{ ++ uint8_t inonce[16]; ++ uint32_t temp[4]; ++ ++ /* Fill in the Nonce */ ++ DWC_MEMSET(&inonce[0], 0, sizeof(inonce)); ++ inonce[9] = addr & 0xFF; ++ inonce[10] = (addr >> 8) & 0xFF; ++ inonce[11] = inonce[9]; ++ inonce[12] = inonce[10]; ++ ++ /* Collect "randomness samples" */ ++ DWC_RANDOM_BYTES((uint8_t *)temp, 16); ++ ++ dwc_wusb_prf_128((uint8_t *)temp, nonce, ++ "Random Numbers", (uint8_t *)temp, sizeof(temp), ++ nonce); ++} ++ ++/** ++ * Generates the Session Key (PTK) and Key Confirmation Key (KCK) per the ++ * WUSB spec. ++ * ++ * @param[in] ccm_nonce Pointer to CCM Nonce. ++ * @param[in] mk Master Key to derive the session from ++ * @param[in] hnonce Pointer to Host Nonce. ++ * @param[in] dnonce Pointer to Device Nonce. ++ * @param[out] kck Pointer to where the KCK output is to be written. ++ * @param[out] ptk Pointer to where the PTK output is to be written. ++ */ ++void dwc_wusb_gen_key(uint8_t *ccm_nonce, uint8_t *mk, uint8_t *hnonce, ++ uint8_t *dnonce, uint8_t *kck, uint8_t *ptk) ++{ ++ uint8_t idata[32]; ++ uint8_t odata[32]; ++ ++ dump_bytes("ck", mk, 16); ++ dump_bytes("hnonce", hnonce, 16); ++ dump_bytes("dnonce", dnonce, 16); ++ ++ /* The data is the HNonce and DNonce concatenated */ ++ DWC_MEMCPY(&idata[0], hnonce, 16); ++ DWC_MEMCPY(&idata[16], dnonce, 16); ++ ++ dwc_wusb_prf_256(mk, ccm_nonce, "Pair-wise keys", idata, 32, odata); ++ ++ /* Low 16 bytes of the result is the KCK, high 16 is the PTK */ ++ DWC_MEMCPY(kck, &odata[0], 16); ++ DWC_MEMCPY(ptk, &odata[16], 16); ++ ++ dump_bytes("kck", kck, 16); ++ dump_bytes("ptk", ptk, 16); ++} ++ ++/** ++ * Generates the Message Integrity Code over the Handshake data per the ++ * WUSB spec. ++ * ++ * @param ccm_nonce Pointer to CCM Nonce. ++ * @param kck Pointer to Key Confirmation Key. ++ * @param data Pointer to Handshake data to be checked. ++ * @param mic Pointer to where the MIC output is to be written. ++ */ ++void dwc_wusb_gen_mic(uint8_t *ccm_nonce, uint8_t *kck, ++ uint8_t *data, uint8_t *mic) ++{ ++ ++ dwc_wusb_prf_64(kck, ccm_nonce, "out-of-bandMIC", ++ data, WUSB_HANDSHAKE_LEN_FOR_MIC, mic); ++} ++ ++#endif /* DWC_CRYPTOLIB */ +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_crypto.h linux-rpi/drivers/usb/host/dwc_common_port/dwc_crypto.h +--- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_crypto.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_crypto.h 2015-11-29 09:42:39.915098960 +0100 +@@ -0,0 +1,111 @@ ++/* ========================================================================= ++ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_crypto.h $ ++ * $Revision: #3 $ ++ * $Date: 2010/09/28 $ ++ * $Change: 1596182 $ ++ * ++ * Synopsys Portability Library Software and documentation ++ * (hereinafter, "Software") is an Unsupported proprietary work of ++ * Synopsys, Inc. unless otherwise expressly agreed to in writing ++ * between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for ++ * Licensed Product with Synopsys or any supplement thereto. You are ++ * permitted to use and redistribute this Software in source and binary ++ * forms, with or without modification, provided that redistributions ++ * of source code must retain this notice. You may not view, use, ++ * disclose, copy or distribute this file or any information contained ++ * herein except pursuant to this license grant from Synopsys. If you ++ * do not agree with this notice, including the disclaimer below, then ++ * you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ++ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL ++ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY ++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE ++ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================= */ ++ ++#ifndef _DWC_CRYPTO_H_ ++#define _DWC_CRYPTO_H_ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/** @file ++ * ++ * This file contains declarations for the WUSB Cryptographic routines as ++ * defined in the WUSB spec. They are only to be used internally by the DWC UWB ++ * modules. ++ */ ++ ++#include "dwc_os.h" ++ ++int dwc_wusb_aes_encrypt(u8 *src, u8 *key, u8 *dst); ++ ++void dwc_wusb_cmf(u8 *key, u8 *nonce, ++ char *label, u8 *bytes, int len, u8 *result); ++void dwc_wusb_prf(int prf_len, u8 *key, ++ u8 *nonce, char *label, u8 *bytes, int len, u8 *result); ++ ++/** ++ * The PRF-64 function described in section 6.5 of the WUSB spec. ++ * ++ * @param key, nonce, label, bytes, len, result Same as for dwc_prf(). ++ */ ++static inline void dwc_wusb_prf_64(u8 *key, u8 *nonce, ++ char *label, u8 *bytes, int len, u8 *result) ++{ ++ dwc_wusb_prf(64, key, nonce, label, bytes, len, result); ++} ++ ++/** ++ * The PRF-128 function described in section 6.5 of the WUSB spec. ++ * ++ * @param key, nonce, label, bytes, len, result Same as for dwc_prf(). ++ */ ++static inline void dwc_wusb_prf_128(u8 *key, u8 *nonce, ++ char *label, u8 *bytes, int len, u8 *result) ++{ ++ dwc_wusb_prf(128, key, nonce, label, bytes, len, result); ++} ++ ++/** ++ * The PRF-256 function described in section 6.5 of the WUSB spec. ++ * ++ * @param key, nonce, label, bytes, len, result Same as for dwc_prf(). ++ */ ++static inline void dwc_wusb_prf_256(u8 *key, u8 *nonce, ++ char *label, u8 *bytes, int len, u8 *result) ++{ ++ dwc_wusb_prf(256, key, nonce, label, bytes, len, result); ++} ++ ++ ++void dwc_wusb_fill_ccm_nonce(uint16_t haddr, uint16_t daddr, uint8_t *tkid, ++ uint8_t *nonce); ++void dwc_wusb_gen_nonce(uint16_t addr, ++ uint8_t *nonce); ++ ++void dwc_wusb_gen_key(uint8_t *ccm_nonce, uint8_t *mk, ++ uint8_t *hnonce, uint8_t *dnonce, ++ uint8_t *kck, uint8_t *ptk); ++ ++ ++void dwc_wusb_gen_mic(uint8_t *ccm_nonce, uint8_t ++ *kck, uint8_t *data, uint8_t *mic); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif /* _DWC_CRYPTO_H_ */ +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_dh.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_dh.c +--- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_dh.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_dh.c 2015-11-29 09:42:39.915098960 +0100 +@@ -0,0 +1,291 @@ ++/* ========================================================================= ++ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_dh.c $ ++ * $Revision: #3 $ ++ * $Date: 2010/09/28 $ ++ * $Change: 1596182 $ ++ * ++ * Synopsys Portability Library Software and documentation ++ * (hereinafter, "Software") is an Unsupported proprietary work of ++ * Synopsys, Inc. unless otherwise expressly agreed to in writing ++ * between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for ++ * Licensed Product with Synopsys or any supplement thereto. You are ++ * permitted to use and redistribute this Software in source and binary ++ * forms, with or without modification, provided that redistributions ++ * of source code must retain this notice. You may not view, use, ++ * disclose, copy or distribute this file or any information contained ++ * herein except pursuant to this license grant from Synopsys. If you ++ * do not agree with this notice, including the disclaimer below, then ++ * you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ++ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL ++ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY ++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE ++ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================= */ ++#ifdef DWC_CRYPTOLIB ++ ++#ifndef CONFIG_MACH_IPMATE ++ ++#include "dwc_dh.h" ++#include "dwc_modpow.h" ++ ++#ifdef DEBUG ++/* This function prints out a buffer in the format described in the Association ++ * Model specification. */ ++static void dh_dump(char *str, void *_num, int len) ++{ ++ uint8_t *num = _num; ++ int i; ++ DWC_PRINTF("%s\n", str); ++ for (i = 0; i < len; i ++) { ++ DWC_PRINTF("%02x", num[i]); ++ if (((i + 1) % 2) == 0) DWC_PRINTF(" "); ++ if (((i + 1) % 26) == 0) DWC_PRINTF("\n"); ++ } ++ ++ DWC_PRINTF("\n"); ++} ++#else ++#define dh_dump(_x...) do {; } while(0) ++#endif ++ ++/* Constant g value */ ++static __u32 dh_g[] = { ++ 0x02000000, ++}; ++ ++/* Constant p value */ ++static __u32 dh_p[] = { ++ 0xFFFFFFFF, 0xFFFFFFFF, 0xA2DA0FC9, 0x34C26821, 0x8B62C6C4, 0xD11CDC80, 0x084E0229, 0x74CC678A, ++ 0xA6BE0B02, 0x229B133B, 0x79084A51, 0xDD04348E, 0xB31995EF, 0x1B433ACD, 0x6D0A2B30, 0x37145FF2, ++ 0x6D35E14F, 0x45C2516D, 0x76B585E4, 0xC67E5E62, 0xE9424CF4, 0x6BED37A6, 0xB65CFF0B, 0xEDB706F4, ++ 0xFB6B38EE, 0xA59F895A, 0x11249FAE, 0xE61F4B7C, 0x51662849, 0x3D5BE4EC, 0xB87C00C2, 0x05BF63A1, ++ 0x3648DA98, 0x9AD3551C, 0xA83F1669, 0x5FCF24FD, 0x235D6583, 0x96ADA3DC, 0x56F3621C, 0xBB528520, ++ 0x0729D59E, 0x6D969670, 0x4E350C67, 0x0498BC4A, 0x086C74F1, 0x7C2118CA, 0x465E9032, 0x3BCE362E, ++ 0x2C779EE3, 0x03860E18, 0xA283279B, 0x8FA207EC, 0xF05DC5B5, 0xC9524C6F, 0xF6CB2BDE, 0x18175895, ++ 0x7C499539, 0xE56A95EA, 0x1826D215, 0x1005FA98, 0x5A8E7215, 0x2DC4AA8A, 0x0D1733AD, 0x337A5004, ++ 0xAB2155A8, 0x64BA1CDF, 0x0485FBEC, 0x0AEFDB58, 0x5771EA8A, 0x7D0C065D, 0x850F97B3, 0xC7E4E1A6, ++ 0x8CAEF5AB, 0xD73309DB, 0xE0948C1E, 0x9D61254A, 0x26D2E3CE, 0x6BEED21A, 0x06FA2FF1, 0x64088AD9, ++ 0x730276D8, 0x646AC83E, 0x182B1F52, 0x0C207B17, 0x5717E1BB, 0x6C5D617A, 0xC0880977, 0xE246D9BA, ++ 0xA04FE208, 0x31ABE574, 0xFC5BDB43, 0x8E10FDE0, 0x20D1824B, 0xCAD23AA9, 0xFFFFFFFF, 0xFFFFFFFF, ++}; ++ ++static void dh_swap_bytes(void *_in, void *_out, uint32_t len) ++{ ++ uint8_t *in = _in; ++ uint8_t *out = _out; ++ int i; ++ for (i=0; inext = (link); \ ++ (link)->prev = (link); \ ++} while (0) ++ ++#define DWC_LIST_FIRST(link) ((link)->next) ++#define DWC_LIST_LAST(link) ((link)->prev) ++#define DWC_LIST_END(link) (link) ++#define DWC_LIST_NEXT(link) ((link)->next) ++#define DWC_LIST_PREV(link) ((link)->prev) ++#define DWC_LIST_EMPTY(link) \ ++ (DWC_LIST_FIRST(link) == DWC_LIST_END(link)) ++#define DWC_LIST_ENTRY(link, type, field) \ ++ (type *)((uint8_t *)(link) - (size_t)(&((type *)0)->field)) ++ ++#if 0 ++#define DWC_LIST_INSERT_HEAD(list, link) do { \ ++ (link)->next = (list)->next; \ ++ (link)->prev = (list); \ ++ (list)->next->prev = (link); \ ++ (list)->next = (link); \ ++} while (0) ++ ++#define DWC_LIST_INSERT_TAIL(list, link) do { \ ++ (link)->next = (list); \ ++ (link)->prev = (list)->prev; \ ++ (list)->prev->next = (link); \ ++ (list)->prev = (link); \ ++} while (0) ++#else ++#define DWC_LIST_INSERT_HEAD(list, link) do { \ ++ dwc_list_link_t *__next__ = (list)->next; \ ++ __next__->prev = (link); \ ++ (link)->next = __next__; \ ++ (link)->prev = (list); \ ++ (list)->next = (link); \ ++} while (0) ++ ++#define DWC_LIST_INSERT_TAIL(list, link) do { \ ++ dwc_list_link_t *__prev__ = (list)->prev; \ ++ (list)->prev = (link); \ ++ (link)->next = (list); \ ++ (link)->prev = __prev__; \ ++ __prev__->next = (link); \ ++} while (0) ++#endif ++ ++#if 0 ++static inline void __list_add(struct list_head *new, ++ struct list_head *prev, ++ struct list_head *next) ++{ ++ next->prev = new; ++ new->next = next; ++ new->prev = prev; ++ prev->next = new; ++} ++ ++static inline void list_add(struct list_head *new, struct list_head *head) ++{ ++ __list_add(new, head, head->next); ++} ++ ++static inline void list_add_tail(struct list_head *new, struct list_head *head) ++{ ++ __list_add(new, head->prev, head); ++} ++ ++static inline void __list_del(struct list_head * prev, struct list_head * next) ++{ ++ next->prev = prev; ++ prev->next = next; ++} ++ ++static inline void list_del(struct list_head *entry) ++{ ++ __list_del(entry->prev, entry->next); ++ entry->next = LIST_POISON1; ++ entry->prev = LIST_POISON2; ++} ++#endif ++ ++#define DWC_LIST_REMOVE(link) do { \ ++ (link)->next->prev = (link)->prev; \ ++ (link)->prev->next = (link)->next; \ ++} while (0) ++ ++#define DWC_LIST_REMOVE_INIT(link) do { \ ++ DWC_LIST_REMOVE(link); \ ++ DWC_LIST_INIT(link); \ ++} while (0) ++ ++#define DWC_LIST_MOVE_HEAD(list, link) do { \ ++ DWC_LIST_REMOVE(link); \ ++ DWC_LIST_INSERT_HEAD(list, link); \ ++} while (0) ++ ++#define DWC_LIST_MOVE_TAIL(list, link) do { \ ++ DWC_LIST_REMOVE(link); \ ++ DWC_LIST_INSERT_TAIL(list, link); \ ++} while (0) ++ ++#define DWC_LIST_FOREACH(var, list) \ ++ for((var) = DWC_LIST_FIRST(list); \ ++ (var) != DWC_LIST_END(list); \ ++ (var) = DWC_LIST_NEXT(var)) ++ ++#define DWC_LIST_FOREACH_SAFE(var, var2, list) \ ++ for((var) = DWC_LIST_FIRST(list), (var2) = DWC_LIST_NEXT(var); \ ++ (var) != DWC_LIST_END(list); \ ++ (var) = (var2), (var2) = DWC_LIST_NEXT(var2)) ++ ++#define DWC_LIST_FOREACH_REVERSE(var, list) \ ++ for((var) = DWC_LIST_LAST(list); \ ++ (var) != DWC_LIST_END(list); \ ++ (var) = DWC_LIST_PREV(var)) ++ ++/* ++ * Singly-linked List definitions. ++ */ ++#define DWC_SLIST_HEAD(name, type) \ ++struct name { \ ++ struct type *slh_first; /* first element */ \ ++} ++ ++#define DWC_SLIST_HEAD_INITIALIZER(head) \ ++ { NULL } ++ ++#define DWC_SLIST_ENTRY(type) \ ++struct { \ ++ struct type *sle_next; /* next element */ \ ++} ++ ++/* ++ * Singly-linked List access methods. ++ */ ++#define DWC_SLIST_FIRST(head) ((head)->slh_first) ++#define DWC_SLIST_END(head) NULL ++#define DWC_SLIST_EMPTY(head) (SLIST_FIRST(head) == SLIST_END(head)) ++#define DWC_SLIST_NEXT(elm, field) ((elm)->field.sle_next) ++ ++#define DWC_SLIST_FOREACH(var, head, field) \ ++ for((var) = SLIST_FIRST(head); \ ++ (var) != SLIST_END(head); \ ++ (var) = SLIST_NEXT(var, field)) ++ ++#define DWC_SLIST_FOREACH_PREVPTR(var, varp, head, field) \ ++ for((varp) = &SLIST_FIRST((head)); \ ++ ((var) = *(varp)) != SLIST_END(head); \ ++ (varp) = &SLIST_NEXT((var), field)) ++ ++/* ++ * Singly-linked List functions. ++ */ ++#define DWC_SLIST_INIT(head) { \ ++ SLIST_FIRST(head) = SLIST_END(head); \ ++} ++ ++#define DWC_SLIST_INSERT_AFTER(slistelm, elm, field) do { \ ++ (elm)->field.sle_next = (slistelm)->field.sle_next; \ ++ (slistelm)->field.sle_next = (elm); \ ++} while (0) ++ ++#define DWC_SLIST_INSERT_HEAD(head, elm, field) do { \ ++ (elm)->field.sle_next = (head)->slh_first; \ ++ (head)->slh_first = (elm); \ ++} while (0) ++ ++#define DWC_SLIST_REMOVE_NEXT(head, elm, field) do { \ ++ (elm)->field.sle_next = (elm)->field.sle_next->field.sle_next; \ ++} while (0) ++ ++#define DWC_SLIST_REMOVE_HEAD(head, field) do { \ ++ (head)->slh_first = (head)->slh_first->field.sle_next; \ ++} while (0) ++ ++#define DWC_SLIST_REMOVE(head, elm, type, field) do { \ ++ if ((head)->slh_first == (elm)) { \ ++ SLIST_REMOVE_HEAD((head), field); \ ++ } \ ++ else { \ ++ struct type *curelm = (head)->slh_first; \ ++ while( curelm->field.sle_next != (elm) ) \ ++ curelm = curelm->field.sle_next; \ ++ curelm->field.sle_next = \ ++ curelm->field.sle_next->field.sle_next; \ ++ } \ ++} while (0) ++ ++/* ++ * Simple queue definitions. ++ */ ++#define DWC_SIMPLEQ_HEAD(name, type) \ ++struct name { \ ++ struct type *sqh_first; /* first element */ \ ++ struct type **sqh_last; /* addr of last next element */ \ ++} ++ ++#define DWC_SIMPLEQ_HEAD_INITIALIZER(head) \ ++ { NULL, &(head).sqh_first } ++ ++#define DWC_SIMPLEQ_ENTRY(type) \ ++struct { \ ++ struct type *sqe_next; /* next element */ \ ++} ++ ++/* ++ * Simple queue access methods. ++ */ ++#define DWC_SIMPLEQ_FIRST(head) ((head)->sqh_first) ++#define DWC_SIMPLEQ_END(head) NULL ++#define DWC_SIMPLEQ_EMPTY(head) (SIMPLEQ_FIRST(head) == SIMPLEQ_END(head)) ++#define DWC_SIMPLEQ_NEXT(elm, field) ((elm)->field.sqe_next) ++ ++#define DWC_SIMPLEQ_FOREACH(var, head, field) \ ++ for((var) = SIMPLEQ_FIRST(head); \ ++ (var) != SIMPLEQ_END(head); \ ++ (var) = SIMPLEQ_NEXT(var, field)) ++ ++/* ++ * Simple queue functions. ++ */ ++#define DWC_SIMPLEQ_INIT(head) do { \ ++ (head)->sqh_first = NULL; \ ++ (head)->sqh_last = &(head)->sqh_first; \ ++} while (0) ++ ++#define DWC_SIMPLEQ_INSERT_HEAD(head, elm, field) do { \ ++ if (((elm)->field.sqe_next = (head)->sqh_first) == NULL) \ ++ (head)->sqh_last = &(elm)->field.sqe_next; \ ++ (head)->sqh_first = (elm); \ ++} while (0) ++ ++#define DWC_SIMPLEQ_INSERT_TAIL(head, elm, field) do { \ ++ (elm)->field.sqe_next = NULL; \ ++ *(head)->sqh_last = (elm); \ ++ (head)->sqh_last = &(elm)->field.sqe_next; \ ++} while (0) ++ ++#define DWC_SIMPLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ ++ if (((elm)->field.sqe_next = (listelm)->field.sqe_next) == NULL)\ ++ (head)->sqh_last = &(elm)->field.sqe_next; \ ++ (listelm)->field.sqe_next = (elm); \ ++} while (0) ++ ++#define DWC_SIMPLEQ_REMOVE_HEAD(head, field) do { \ ++ if (((head)->sqh_first = (head)->sqh_first->field.sqe_next) == NULL) \ ++ (head)->sqh_last = &(head)->sqh_first; \ ++} while (0) ++ ++/* ++ * Tail queue definitions. ++ */ ++#define DWC_TAILQ_HEAD(name, type) \ ++struct name { \ ++ struct type *tqh_first; /* first element */ \ ++ struct type **tqh_last; /* addr of last next element */ \ ++} ++ ++#define DWC_TAILQ_HEAD_INITIALIZER(head) \ ++ { NULL, &(head).tqh_first } ++ ++#define DWC_TAILQ_ENTRY(type) \ ++struct { \ ++ struct type *tqe_next; /* next element */ \ ++ struct type **tqe_prev; /* address of previous next element */ \ ++} ++ ++/* ++ * tail queue access methods ++ */ ++#define DWC_TAILQ_FIRST(head) ((head)->tqh_first) ++#define DWC_TAILQ_END(head) NULL ++#define DWC_TAILQ_NEXT(elm, field) ((elm)->field.tqe_next) ++#define DWC_TAILQ_LAST(head, headname) \ ++ (*(((struct headname *)((head)->tqh_last))->tqh_last)) ++/* XXX */ ++#define DWC_TAILQ_PREV(elm, headname, field) \ ++ (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last)) ++#define DWC_TAILQ_EMPTY(head) \ ++ (DWC_TAILQ_FIRST(head) == DWC_TAILQ_END(head)) ++ ++#define DWC_TAILQ_FOREACH(var, head, field) \ ++ for ((var) = DWC_TAILQ_FIRST(head); \ ++ (var) != DWC_TAILQ_END(head); \ ++ (var) = DWC_TAILQ_NEXT(var, field)) ++ ++#define DWC_TAILQ_FOREACH_REVERSE(var, head, headname, field) \ ++ for ((var) = DWC_TAILQ_LAST(head, headname); \ ++ (var) != DWC_TAILQ_END(head); \ ++ (var) = DWC_TAILQ_PREV(var, headname, field)) ++ ++/* ++ * Tail queue functions. ++ */ ++#define DWC_TAILQ_INIT(head) do { \ ++ (head)->tqh_first = NULL; \ ++ (head)->tqh_last = &(head)->tqh_first; \ ++} while (0) ++ ++#define DWC_TAILQ_INSERT_HEAD(head, elm, field) do { \ ++ if (((elm)->field.tqe_next = (head)->tqh_first) != NULL) \ ++ (head)->tqh_first->field.tqe_prev = \ ++ &(elm)->field.tqe_next; \ ++ else \ ++ (head)->tqh_last = &(elm)->field.tqe_next; \ ++ (head)->tqh_first = (elm); \ ++ (elm)->field.tqe_prev = &(head)->tqh_first; \ ++} while (0) ++ ++#define DWC_TAILQ_INSERT_TAIL(head, elm, field) do { \ ++ (elm)->field.tqe_next = NULL; \ ++ (elm)->field.tqe_prev = (head)->tqh_last; \ ++ *(head)->tqh_last = (elm); \ ++ (head)->tqh_last = &(elm)->field.tqe_next; \ ++} while (0) ++ ++#define DWC_TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \ ++ if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL)\ ++ (elm)->field.tqe_next->field.tqe_prev = \ ++ &(elm)->field.tqe_next; \ ++ else \ ++ (head)->tqh_last = &(elm)->field.tqe_next; \ ++ (listelm)->field.tqe_next = (elm); \ ++ (elm)->field.tqe_prev = &(listelm)->field.tqe_next; \ ++} while (0) ++ ++#define DWC_TAILQ_INSERT_BEFORE(listelm, elm, field) do { \ ++ (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \ ++ (elm)->field.tqe_next = (listelm); \ ++ *(listelm)->field.tqe_prev = (elm); \ ++ (listelm)->field.tqe_prev = &(elm)->field.tqe_next; \ ++} while (0) ++ ++#define DWC_TAILQ_REMOVE(head, elm, field) do { \ ++ if (((elm)->field.tqe_next) != NULL) \ ++ (elm)->field.tqe_next->field.tqe_prev = \ ++ (elm)->field.tqe_prev; \ ++ else \ ++ (head)->tqh_last = (elm)->field.tqe_prev; \ ++ *(elm)->field.tqe_prev = (elm)->field.tqe_next; \ ++} while (0) ++ ++#define DWC_TAILQ_REPLACE(head, elm, elm2, field) do { \ ++ if (((elm2)->field.tqe_next = (elm)->field.tqe_next) != NULL) \ ++ (elm2)->field.tqe_next->field.tqe_prev = \ ++ &(elm2)->field.tqe_next; \ ++ else \ ++ (head)->tqh_last = &(elm2)->field.tqe_next; \ ++ (elm2)->field.tqe_prev = (elm)->field.tqe_prev; \ ++ *(elm2)->field.tqe_prev = (elm2); \ ++} while (0) ++ ++/* ++ * Circular queue definitions. ++ */ ++#define DWC_CIRCLEQ_HEAD(name, type) \ ++struct name { \ ++ struct type *cqh_first; /* first element */ \ ++ struct type *cqh_last; /* last element */ \ ++} ++ ++#define DWC_CIRCLEQ_HEAD_INITIALIZER(head) \ ++ { DWC_CIRCLEQ_END(&head), DWC_CIRCLEQ_END(&head) } ++ ++#define DWC_CIRCLEQ_ENTRY(type) \ ++struct { \ ++ struct type *cqe_next; /* next element */ \ ++ struct type *cqe_prev; /* previous element */ \ ++} ++ ++/* ++ * Circular queue access methods ++ */ ++#define DWC_CIRCLEQ_FIRST(head) ((head)->cqh_first) ++#define DWC_CIRCLEQ_LAST(head) ((head)->cqh_last) ++#define DWC_CIRCLEQ_END(head) ((void *)(head)) ++#define DWC_CIRCLEQ_NEXT(elm, field) ((elm)->field.cqe_next) ++#define DWC_CIRCLEQ_PREV(elm, field) ((elm)->field.cqe_prev) ++#define DWC_CIRCLEQ_EMPTY(head) \ ++ (DWC_CIRCLEQ_FIRST(head) == DWC_CIRCLEQ_END(head)) ++ ++#define DWC_CIRCLEQ_EMPTY_ENTRY(elm, field) (((elm)->field.cqe_next == NULL) && ((elm)->field.cqe_prev == NULL)) ++ ++#define DWC_CIRCLEQ_FOREACH(var, head, field) \ ++ for((var) = DWC_CIRCLEQ_FIRST(head); \ ++ (var) != DWC_CIRCLEQ_END(head); \ ++ (var) = DWC_CIRCLEQ_NEXT(var, field)) ++ ++#define DWC_CIRCLEQ_FOREACH_SAFE(var, var2, head, field) \ ++ for((var) = DWC_CIRCLEQ_FIRST(head), var2 = DWC_CIRCLEQ_NEXT(var, field); \ ++ (var) != DWC_CIRCLEQ_END(head); \ ++ (var) = var2, var2 = DWC_CIRCLEQ_NEXT(var, field)) ++ ++#define DWC_CIRCLEQ_FOREACH_REVERSE(var, head, field) \ ++ for((var) = DWC_CIRCLEQ_LAST(head); \ ++ (var) != DWC_CIRCLEQ_END(head); \ ++ (var) = DWC_CIRCLEQ_PREV(var, field)) ++ ++/* ++ * Circular queue functions. ++ */ ++#define DWC_CIRCLEQ_INIT(head) do { \ ++ (head)->cqh_first = DWC_CIRCLEQ_END(head); \ ++ (head)->cqh_last = DWC_CIRCLEQ_END(head); \ ++} while (0) ++ ++#define DWC_CIRCLEQ_INIT_ENTRY(elm, field) do { \ ++ (elm)->field.cqe_next = NULL; \ ++ (elm)->field.cqe_prev = NULL; \ ++} while (0) ++ ++#define DWC_CIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ ++ (elm)->field.cqe_next = (listelm)->field.cqe_next; \ ++ (elm)->field.cqe_prev = (listelm); \ ++ if ((listelm)->field.cqe_next == DWC_CIRCLEQ_END(head)) \ ++ (head)->cqh_last = (elm); \ ++ else \ ++ (listelm)->field.cqe_next->field.cqe_prev = (elm); \ ++ (listelm)->field.cqe_next = (elm); \ ++} while (0) ++ ++#define DWC_CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do { \ ++ (elm)->field.cqe_next = (listelm); \ ++ (elm)->field.cqe_prev = (listelm)->field.cqe_prev; \ ++ if ((listelm)->field.cqe_prev == DWC_CIRCLEQ_END(head)) \ ++ (head)->cqh_first = (elm); \ ++ else \ ++ (listelm)->field.cqe_prev->field.cqe_next = (elm); \ ++ (listelm)->field.cqe_prev = (elm); \ ++} while (0) ++ ++#define DWC_CIRCLEQ_INSERT_HEAD(head, elm, field) do { \ ++ (elm)->field.cqe_next = (head)->cqh_first; \ ++ (elm)->field.cqe_prev = DWC_CIRCLEQ_END(head); \ ++ if ((head)->cqh_last == DWC_CIRCLEQ_END(head)) \ ++ (head)->cqh_last = (elm); \ ++ else \ ++ (head)->cqh_first->field.cqe_prev = (elm); \ ++ (head)->cqh_first = (elm); \ ++} while (0) ++ ++#define DWC_CIRCLEQ_INSERT_TAIL(head, elm, field) do { \ ++ (elm)->field.cqe_next = DWC_CIRCLEQ_END(head); \ ++ (elm)->field.cqe_prev = (head)->cqh_last; \ ++ if ((head)->cqh_first == DWC_CIRCLEQ_END(head)) \ ++ (head)->cqh_first = (elm); \ ++ else \ ++ (head)->cqh_last->field.cqe_next = (elm); \ ++ (head)->cqh_last = (elm); \ ++} while (0) ++ ++#define DWC_CIRCLEQ_REMOVE(head, elm, field) do { \ ++ if ((elm)->field.cqe_next == DWC_CIRCLEQ_END(head)) \ ++ (head)->cqh_last = (elm)->field.cqe_prev; \ ++ else \ ++ (elm)->field.cqe_next->field.cqe_prev = \ ++ (elm)->field.cqe_prev; \ ++ if ((elm)->field.cqe_prev == DWC_CIRCLEQ_END(head)) \ ++ (head)->cqh_first = (elm)->field.cqe_next; \ ++ else \ ++ (elm)->field.cqe_prev->field.cqe_next = \ ++ (elm)->field.cqe_next; \ ++} while (0) ++ ++#define DWC_CIRCLEQ_REMOVE_INIT(head, elm, field) do { \ ++ DWC_CIRCLEQ_REMOVE(head, elm, field); \ ++ DWC_CIRCLEQ_INIT_ENTRY(elm, field); \ ++} while (0) ++ ++#define DWC_CIRCLEQ_REPLACE(head, elm, elm2, field) do { \ ++ if (((elm2)->field.cqe_next = (elm)->field.cqe_next) == \ ++ DWC_CIRCLEQ_END(head)) \ ++ (head).cqh_last = (elm2); \ ++ else \ ++ (elm2)->field.cqe_next->field.cqe_prev = (elm2); \ ++ if (((elm2)->field.cqe_prev = (elm)->field.cqe_prev) == \ ++ DWC_CIRCLEQ_END(head)) \ ++ (head).cqh_first = (elm2); \ ++ else \ ++ (elm2)->field.cqe_prev->field.cqe_next = (elm2); \ ++} while (0) ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif /* _DWC_LIST_H_ */ +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_mem.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_mem.c +--- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_mem.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_mem.c 2015-11-29 09:42:39.915098960 +0100 +@@ -0,0 +1,245 @@ ++/* Memory Debugging */ ++#ifdef DWC_DEBUG_MEMORY ++ ++#include "dwc_os.h" ++#include "dwc_list.h" ++ ++struct allocation { ++ void *addr; ++ void *ctx; ++ char *func; ++ int line; ++ uint32_t size; ++ int dma; ++ DWC_CIRCLEQ_ENTRY(allocation) entry; ++}; ++ ++DWC_CIRCLEQ_HEAD(allocation_queue, allocation); ++ ++struct allocation_manager { ++ void *mem_ctx; ++ struct allocation_queue allocations; ++ ++ /* statistics */ ++ int num; ++ int num_freed; ++ int num_active; ++ uint32_t total; ++ uint32_t cur; ++ uint32_t max; ++}; ++ ++static struct allocation_manager *manager = NULL; ++ ++static int add_allocation(void *ctx, uint32_t size, char const *func, int line, void *addr, ++ int dma) ++{ ++ struct allocation *a; ++ ++ DWC_ASSERT(manager != NULL, "manager not allocated"); ++ ++ a = __DWC_ALLOC_ATOMIC(manager->mem_ctx, sizeof(*a)); ++ if (!a) { ++ return -DWC_E_NO_MEMORY; ++ } ++ ++ a->func = __DWC_ALLOC_ATOMIC(manager->mem_ctx, DWC_STRLEN(func) + 1); ++ if (!a->func) { ++ __DWC_FREE(manager->mem_ctx, a); ++ return -DWC_E_NO_MEMORY; ++ } ++ ++ DWC_MEMCPY(a->func, func, DWC_STRLEN(func) + 1); ++ a->addr = addr; ++ a->ctx = ctx; ++ a->line = line; ++ a->size = size; ++ a->dma = dma; ++ DWC_CIRCLEQ_INSERT_TAIL(&manager->allocations, a, entry); ++ ++ /* Update stats */ ++ manager->num++; ++ manager->num_active++; ++ manager->total += size; ++ manager->cur += size; ++ ++ if (manager->max < manager->cur) { ++ manager->max = manager->cur; ++ } ++ ++ return 0; ++} ++ ++static struct allocation *find_allocation(void *ctx, void *addr) ++{ ++ struct allocation *a; ++ ++ DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) { ++ if (a->ctx == ctx && a->addr == addr) { ++ return a; ++ } ++ } ++ ++ return NULL; ++} ++ ++static void free_allocation(void *ctx, void *addr, char const *func, int line) ++{ ++ struct allocation *a = find_allocation(ctx, addr); ++ ++ if (!a) { ++ DWC_ASSERT(0, ++ "Free of address %p that was never allocated or already freed %s:%d", ++ addr, func, line); ++ return; ++ } ++ ++ DWC_CIRCLEQ_REMOVE(&manager->allocations, a, entry); ++ ++ manager->num_active--; ++ manager->num_freed++; ++ manager->cur -= a->size; ++ __DWC_FREE(manager->mem_ctx, a->func); ++ __DWC_FREE(manager->mem_ctx, a); ++} ++ ++int dwc_memory_debug_start(void *mem_ctx) ++{ ++ DWC_ASSERT(manager == NULL, "Memory debugging has already started\n"); ++ ++ if (manager) { ++ return -DWC_E_BUSY; ++ } ++ ++ manager = __DWC_ALLOC(mem_ctx, sizeof(*manager)); ++ if (!manager) { ++ return -DWC_E_NO_MEMORY; ++ } ++ ++ DWC_CIRCLEQ_INIT(&manager->allocations); ++ manager->mem_ctx = mem_ctx; ++ manager->num = 0; ++ manager->num_freed = 0; ++ manager->num_active = 0; ++ manager->total = 0; ++ manager->cur = 0; ++ manager->max = 0; ++ ++ return 0; ++} ++ ++void dwc_memory_debug_stop(void) ++{ ++ struct allocation *a; ++ ++ dwc_memory_debug_report(); ++ ++ DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) { ++ DWC_ERROR("Memory leaked from %s:%d\n", a->func, a->line); ++ free_allocation(a->ctx, a->addr, NULL, -1); ++ } ++ ++ __DWC_FREE(manager->mem_ctx, manager); ++} ++ ++void dwc_memory_debug_report(void) ++{ ++ struct allocation *a; ++ ++ DWC_PRINTF("\n\n\n----------------- Memory Debugging Report -----------------\n\n"); ++ DWC_PRINTF("Num Allocations = %d\n", manager->num); ++ DWC_PRINTF("Freed = %d\n", manager->num_freed); ++ DWC_PRINTF("Active = %d\n", manager->num_active); ++ DWC_PRINTF("Current Memory Used = %d\n", manager->cur); ++ DWC_PRINTF("Total Memory Used = %d\n", manager->total); ++ DWC_PRINTF("Maximum Memory Used at Once = %d\n", manager->max); ++ DWC_PRINTF("Unfreed allocations:\n"); ++ ++ DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) { ++ DWC_PRINTF(" addr=%p, size=%d from %s:%d, DMA=%d\n", ++ a->addr, a->size, a->func, a->line, a->dma); ++ } ++} ++ ++/* The replacement functions */ ++void *dwc_alloc_debug(void *mem_ctx, uint32_t size, char const *func, int line) ++{ ++ void *addr = __DWC_ALLOC(mem_ctx, size); ++ ++ if (!addr) { ++ return NULL; ++ } ++ ++ if (add_allocation(mem_ctx, size, func, line, addr, 0)) { ++ __DWC_FREE(mem_ctx, addr); ++ return NULL; ++ } ++ ++ return addr; ++} ++ ++void *dwc_alloc_atomic_debug(void *mem_ctx, uint32_t size, char const *func, ++ int line) ++{ ++ void *addr = __DWC_ALLOC_ATOMIC(mem_ctx, size); ++ ++ if (!addr) { ++ return NULL; ++ } ++ ++ if (add_allocation(mem_ctx, size, func, line, addr, 0)) { ++ __DWC_FREE(mem_ctx, addr); ++ return NULL; ++ } ++ ++ return addr; ++} ++ ++void dwc_free_debug(void *mem_ctx, void *addr, char const *func, int line) ++{ ++ free_allocation(mem_ctx, addr, func, line); ++ __DWC_FREE(mem_ctx, addr); ++} ++ ++void *dwc_dma_alloc_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr, ++ char const *func, int line) ++{ ++ void *addr = __DWC_DMA_ALLOC(dma_ctx, size, dma_addr); ++ ++ if (!addr) { ++ return NULL; ++ } ++ ++ if (add_allocation(dma_ctx, size, func, line, addr, 1)) { ++ __DWC_DMA_FREE(dma_ctx, size, addr, *dma_addr); ++ return NULL; ++ } ++ ++ return addr; ++} ++ ++void *dwc_dma_alloc_atomic_debug(void *dma_ctx, uint32_t size, ++ dwc_dma_t *dma_addr, char const *func, int line) ++{ ++ void *addr = __DWC_DMA_ALLOC_ATOMIC(dma_ctx, size, dma_addr); ++ ++ if (!addr) { ++ return NULL; ++ } ++ ++ if (add_allocation(dma_ctx, size, func, line, addr, 1)) { ++ __DWC_DMA_FREE(dma_ctx, size, addr, *dma_addr); ++ return NULL; ++ } ++ ++ return addr; ++} ++ ++void dwc_dma_free_debug(void *dma_ctx, uint32_t size, void *virt_addr, ++ dwc_dma_t dma_addr, char const *func, int line) ++{ ++ free_allocation(dma_ctx, virt_addr, func, line); ++ __DWC_DMA_FREE(dma_ctx, size, virt_addr, dma_addr); ++} ++ ++#endif /* DWC_DEBUG_MEMORY */ +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_modpow.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_modpow.c +--- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_modpow.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_modpow.c 2015-11-29 09:42:39.915098960 +0100 +@@ -0,0 +1,636 @@ ++/* Bignum routines adapted from PUTTY sources. PuTTY copyright notice follows. ++ * ++ * PuTTY is copyright 1997-2007 Simon Tatham. ++ * ++ * Portions copyright Robert de Bath, Joris van Rantwijk, Delian ++ * Delchev, Andreas Schultz, Jeroen Massar, Wez Furlong, Nicolas Barry, ++ * Justin Bradford, Ben Harris, Malcolm Smith, Ahmad Khalifa, Markus ++ * Kuhn, and CORE SDI S.A. ++ * ++ * Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation files ++ * (the "Software"), to deal in the Software without restriction, ++ * including without limitation the rights to use, copy, modify, merge, ++ * publish, distribute, sublicense, and/or sell copies of the Software, ++ * and to permit persons to whom the Software is furnished to do so, ++ * subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE ++ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF ++ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION ++ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++#ifdef DWC_CRYPTOLIB ++ ++#ifndef CONFIG_MACH_IPMATE ++ ++#include "dwc_modpow.h" ++ ++#define BIGNUM_INT_MASK 0xFFFFFFFFUL ++#define BIGNUM_TOP_BIT 0x80000000UL ++#define BIGNUM_INT_BITS 32 ++ ++ ++static void *snmalloc(void *mem_ctx, size_t n, size_t size) ++{ ++ void *p; ++ size *= n; ++ if (size == 0) size = 1; ++ p = dwc_alloc(mem_ctx, size); ++ return p; ++} ++ ++#define snewn(ctx, n, type) ((type *)snmalloc((ctx), (n), sizeof(type))) ++#define sfree dwc_free ++ ++/* ++ * Usage notes: ++ * * Do not call the DIVMOD_WORD macro with expressions such as array ++ * subscripts, as some implementations object to this (see below). ++ * * Note that none of the division methods below will cope if the ++ * quotient won't fit into BIGNUM_INT_BITS. Callers should be careful ++ * to avoid this case. ++ * If this condition occurs, in the case of the x86 DIV instruction, ++ * an overflow exception will occur, which (according to a correspondent) ++ * will manifest on Windows as something like ++ * 0xC0000095: Integer overflow ++ * The C variant won't give the right answer, either. ++ */ ++ ++#define MUL_WORD(w1, w2) ((BignumDblInt)w1 * w2) ++ ++#if defined __GNUC__ && defined __i386__ ++#define DIVMOD_WORD(q, r, hi, lo, w) \ ++ __asm__("div %2" : \ ++ "=d" (r), "=a" (q) : \ ++ "r" (w), "d" (hi), "a" (lo)) ++#else ++#define DIVMOD_WORD(q, r, hi, lo, w) do { \ ++ BignumDblInt n = (((BignumDblInt)hi) << BIGNUM_INT_BITS) | lo; \ ++ q = n / w; \ ++ r = n % w; \ ++} while (0) ++#endif ++ ++// q = n / w; ++// r = n % w; ++ ++#define BIGNUM_INT_BYTES (BIGNUM_INT_BITS / 8) ++ ++#define BIGNUM_INTERNAL ++ ++static Bignum newbn(void *mem_ctx, int length) ++{ ++ Bignum b = snewn(mem_ctx, length + 1, BignumInt); ++ //if (!b) ++ //abort(); /* FIXME */ ++ DWC_MEMSET(b, 0, (length + 1) * sizeof(*b)); ++ b[0] = length; ++ return b; ++} ++ ++void freebn(void *mem_ctx, Bignum b) ++{ ++ /* ++ * Burn the evidence, just in case. ++ */ ++ DWC_MEMSET(b, 0, sizeof(b[0]) * (b[0] + 1)); ++ sfree(mem_ctx, b); ++} ++ ++/* ++ * Compute c = a * b. ++ * Input is in the first len words of a and b. ++ * Result is returned in the first 2*len words of c. ++ */ ++static void internal_mul(BignumInt *a, BignumInt *b, ++ BignumInt *c, int len) ++{ ++ int i, j; ++ BignumDblInt t; ++ ++ for (j = 0; j < 2 * len; j++) ++ c[j] = 0; ++ ++ for (i = len - 1; i >= 0; i--) { ++ t = 0; ++ for (j = len - 1; j >= 0; j--) { ++ t += MUL_WORD(a[i], (BignumDblInt) b[j]); ++ t += (BignumDblInt) c[i + j + 1]; ++ c[i + j + 1] = (BignumInt) t; ++ t = t >> BIGNUM_INT_BITS; ++ } ++ c[i] = (BignumInt) t; ++ } ++} ++ ++static void internal_add_shifted(BignumInt *number, ++ unsigned n, int shift) ++{ ++ int word = 1 + (shift / BIGNUM_INT_BITS); ++ int bshift = shift % BIGNUM_INT_BITS; ++ BignumDblInt addend; ++ ++ addend = (BignumDblInt)n << bshift; ++ ++ while (addend) { ++ addend += number[word]; ++ number[word] = (BignumInt) addend & BIGNUM_INT_MASK; ++ addend >>= BIGNUM_INT_BITS; ++ word++; ++ } ++} ++ ++/* ++ * Compute a = a % m. ++ * Input in first alen words of a and first mlen words of m. ++ * Output in first alen words of a ++ * (of which first alen-mlen words will be zero). ++ * The MSW of m MUST have its high bit set. ++ * Quotient is accumulated in the `quotient' array, which is a Bignum ++ * rather than the internal bigendian format. Quotient parts are shifted ++ * left by `qshift' before adding into quot. ++ */ ++static void internal_mod(BignumInt *a, int alen, ++ BignumInt *m, int mlen, ++ BignumInt *quot, int qshift) ++{ ++ BignumInt m0, m1; ++ unsigned int h; ++ int i, k; ++ ++ m0 = m[0]; ++ if (mlen > 1) ++ m1 = m[1]; ++ else ++ m1 = 0; ++ ++ for (i = 0; i <= alen - mlen; i++) { ++ BignumDblInt t; ++ unsigned int q, r, c, ai1; ++ ++ if (i == 0) { ++ h = 0; ++ } else { ++ h = a[i - 1]; ++ a[i - 1] = 0; ++ } ++ ++ if (i == alen - 1) ++ ai1 = 0; ++ else ++ ai1 = a[i + 1]; ++ ++ /* Find q = h:a[i] / m0 */ ++ if (h >= m0) { ++ /* ++ * Special case. ++ * ++ * To illustrate it, suppose a BignumInt is 8 bits, and ++ * we are dividing (say) A1:23:45:67 by A1:B2:C3. Then ++ * our initial division will be 0xA123 / 0xA1, which ++ * will give a quotient of 0x100 and a divide overflow. ++ * However, the invariants in this division algorithm ++ * are not violated, since the full number A1:23:... is ++ * _less_ than the quotient prefix A1:B2:... and so the ++ * following correction loop would have sorted it out. ++ * ++ * In this situation we set q to be the largest ++ * quotient we _can_ stomach (0xFF, of course). ++ */ ++ q = BIGNUM_INT_MASK; ++ } else { ++ /* Macro doesn't want an array subscript expression passed ++ * into it (see definition), so use a temporary. */ ++ BignumInt tmplo = a[i]; ++ DIVMOD_WORD(q, r, h, tmplo, m0); ++ ++ /* Refine our estimate of q by looking at ++ h:a[i]:a[i+1] / m0:m1 */ ++ t = MUL_WORD(m1, q); ++ if (t > ((BignumDblInt) r << BIGNUM_INT_BITS) + ai1) { ++ q--; ++ t -= m1; ++ r = (r + m0) & BIGNUM_INT_MASK; /* overflow? */ ++ if (r >= (BignumDblInt) m0 && ++ t > ((BignumDblInt) r << BIGNUM_INT_BITS) + ai1) q--; ++ } ++ } ++ ++ /* Subtract q * m from a[i...] */ ++ c = 0; ++ for (k = mlen - 1; k >= 0; k--) { ++ t = MUL_WORD(q, m[k]); ++ t += c; ++ c = (unsigned)(t >> BIGNUM_INT_BITS); ++ if ((BignumInt) t > a[i + k]) ++ c++; ++ a[i + k] -= (BignumInt) t; ++ } ++ ++ /* Add back m in case of borrow */ ++ if (c != h) { ++ t = 0; ++ for (k = mlen - 1; k >= 0; k--) { ++ t += m[k]; ++ t += a[i + k]; ++ a[i + k] = (BignumInt) t; ++ t = t >> BIGNUM_INT_BITS; ++ } ++ q--; ++ } ++ if (quot) ++ internal_add_shifted(quot, q, qshift + BIGNUM_INT_BITS * (alen - mlen - i)); ++ } ++} ++ ++/* ++ * Compute p % mod. ++ * The most significant word of mod MUST be non-zero. ++ * We assume that the result array is the same size as the mod array. ++ * We optionally write out a quotient if `quotient' is non-NULL. ++ * We can avoid writing out the result if `result' is NULL. ++ */ ++void bigdivmod(void *mem_ctx, Bignum p, Bignum mod, Bignum result, Bignum quotient) ++{ ++ BignumInt *n, *m; ++ int mshift; ++ int plen, mlen, i, j; ++ ++ /* Allocate m of size mlen, copy mod to m */ ++ /* We use big endian internally */ ++ mlen = mod[0]; ++ m = snewn(mem_ctx, mlen, BignumInt); ++ //if (!m) ++ //abort(); /* FIXME */ ++ for (j = 0; j < mlen; j++) ++ m[j] = mod[mod[0] - j]; ++ ++ /* Shift m left to make msb bit set */ ++ for (mshift = 0; mshift < BIGNUM_INT_BITS-1; mshift++) ++ if ((m[0] << mshift) & BIGNUM_TOP_BIT) ++ break; ++ if (mshift) { ++ for (i = 0; i < mlen - 1; i++) ++ m[i] = (m[i] << mshift) | (m[i + 1] >> (BIGNUM_INT_BITS - mshift)); ++ m[mlen - 1] = m[mlen - 1] << mshift; ++ } ++ ++ plen = p[0]; ++ /* Ensure plen > mlen */ ++ if (plen <= mlen) ++ plen = mlen + 1; ++ ++ /* Allocate n of size plen, copy p to n */ ++ n = snewn(mem_ctx, plen, BignumInt); ++ //if (!n) ++ //abort(); /* FIXME */ ++ for (j = 0; j < plen; j++) ++ n[j] = 0; ++ for (j = 1; j <= (int)p[0]; j++) ++ n[plen - j] = p[j]; ++ ++ /* Main computation */ ++ internal_mod(n, plen, m, mlen, quotient, mshift); ++ ++ /* Fixup result in case the modulus was shifted */ ++ if (mshift) { ++ for (i = plen - mlen - 1; i < plen - 1; i++) ++ n[i] = (n[i] << mshift) | (n[i + 1] >> (BIGNUM_INT_BITS - mshift)); ++ n[plen - 1] = n[plen - 1] << mshift; ++ internal_mod(n, plen, m, mlen, quotient, 0); ++ for (i = plen - 1; i >= plen - mlen; i--) ++ n[i] = (n[i] >> mshift) | (n[i - 1] << (BIGNUM_INT_BITS - mshift)); ++ } ++ ++ /* Copy result to buffer */ ++ if (result) { ++ for (i = 1; i <= (int)result[0]; i++) { ++ int j = plen - i; ++ result[i] = j >= 0 ? n[j] : 0; ++ } ++ } ++ ++ /* Free temporary arrays */ ++ for (i = 0; i < mlen; i++) ++ m[i] = 0; ++ sfree(mem_ctx, m); ++ for (i = 0; i < plen; i++) ++ n[i] = 0; ++ sfree(mem_ctx, n); ++} ++ ++/* ++ * Simple remainder. ++ */ ++Bignum bigmod(void *mem_ctx, Bignum a, Bignum b) ++{ ++ Bignum r = newbn(mem_ctx, b[0]); ++ bigdivmod(mem_ctx, a, b, r, NULL); ++ return r; ++} ++ ++/* ++ * Compute (base ^ exp) % mod. ++ */ ++Bignum dwc_modpow(void *mem_ctx, Bignum base_in, Bignum exp, Bignum mod) ++{ ++ BignumInt *a, *b, *n, *m; ++ int mshift; ++ int mlen, i, j; ++ Bignum base, result; ++ ++ /* ++ * The most significant word of mod needs to be non-zero. It ++ * should already be, but let's make sure. ++ */ ++ //assert(mod[mod[0]] != 0); ++ ++ /* ++ * Make sure the base is smaller than the modulus, by reducing ++ * it modulo the modulus if not. ++ */ ++ base = bigmod(mem_ctx, base_in, mod); ++ ++ /* Allocate m of size mlen, copy mod to m */ ++ /* We use big endian internally */ ++ mlen = mod[0]; ++ m = snewn(mem_ctx, mlen, BignumInt); ++ //if (!m) ++ //abort(); /* FIXME */ ++ for (j = 0; j < mlen; j++) ++ m[j] = mod[mod[0] - j]; ++ ++ /* Shift m left to make msb bit set */ ++ for (mshift = 0; mshift < BIGNUM_INT_BITS - 1; mshift++) ++ if ((m[0] << mshift) & BIGNUM_TOP_BIT) ++ break; ++ if (mshift) { ++ for (i = 0; i < mlen - 1; i++) ++ m[i] = ++ (m[i] << mshift) | (m[i + 1] >> ++ (BIGNUM_INT_BITS - mshift)); ++ m[mlen - 1] = m[mlen - 1] << mshift; ++ } ++ ++ /* Allocate n of size mlen, copy base to n */ ++ n = snewn(mem_ctx, mlen, BignumInt); ++ //if (!n) ++ //abort(); /* FIXME */ ++ i = mlen - base[0]; ++ for (j = 0; j < i; j++) ++ n[j] = 0; ++ for (j = 0; j < base[0]; j++) ++ n[i + j] = base[base[0] - j]; ++ ++ /* Allocate a and b of size 2*mlen. Set a = 1 */ ++ a = snewn(mem_ctx, 2 * mlen, BignumInt); ++ //if (!a) ++ //abort(); /* FIXME */ ++ b = snewn(mem_ctx, 2 * mlen, BignumInt); ++ //if (!b) ++ //abort(); /* FIXME */ ++ for (i = 0; i < 2 * mlen; i++) ++ a[i] = 0; ++ a[2 * mlen - 1] = 1; ++ ++ /* Skip leading zero bits of exp. */ ++ i = 0; ++ j = BIGNUM_INT_BITS - 1; ++ while (i < exp[0] && (exp[exp[0] - i] & (1 << j)) == 0) { ++ j--; ++ if (j < 0) { ++ i++; ++ j = BIGNUM_INT_BITS - 1; ++ } ++ } ++ ++ /* Main computation */ ++ while (i < exp[0]) { ++ while (j >= 0) { ++ internal_mul(a + mlen, a + mlen, b, mlen); ++ internal_mod(b, mlen * 2, m, mlen, NULL, 0); ++ if ((exp[exp[0] - i] & (1 << j)) != 0) { ++ internal_mul(b + mlen, n, a, mlen); ++ internal_mod(a, mlen * 2, m, mlen, NULL, 0); ++ } else { ++ BignumInt *t; ++ t = a; ++ a = b; ++ b = t; ++ } ++ j--; ++ } ++ i++; ++ j = BIGNUM_INT_BITS - 1; ++ } ++ ++ /* Fixup result in case the modulus was shifted */ ++ if (mshift) { ++ for (i = mlen - 1; i < 2 * mlen - 1; i++) ++ a[i] = ++ (a[i] << mshift) | (a[i + 1] >> ++ (BIGNUM_INT_BITS - mshift)); ++ a[2 * mlen - 1] = a[2 * mlen - 1] << mshift; ++ internal_mod(a, mlen * 2, m, mlen, NULL, 0); ++ for (i = 2 * mlen - 1; i >= mlen; i--) ++ a[i] = ++ (a[i] >> mshift) | (a[i - 1] << ++ (BIGNUM_INT_BITS - mshift)); ++ } ++ ++ /* Copy result to buffer */ ++ result = newbn(mem_ctx, mod[0]); ++ for (i = 0; i < mlen; i++) ++ result[result[0] - i] = a[i + mlen]; ++ while (result[0] > 1 && result[result[0]] == 0) ++ result[0]--; ++ ++ /* Free temporary arrays */ ++ for (i = 0; i < 2 * mlen; i++) ++ a[i] = 0; ++ sfree(mem_ctx, a); ++ for (i = 0; i < 2 * mlen; i++) ++ b[i] = 0; ++ sfree(mem_ctx, b); ++ for (i = 0; i < mlen; i++) ++ m[i] = 0; ++ sfree(mem_ctx, m); ++ for (i = 0; i < mlen; i++) ++ n[i] = 0; ++ sfree(mem_ctx, n); ++ ++ freebn(mem_ctx, base); ++ ++ return result; ++} ++ ++ ++#ifdef UNITTEST ++ ++static __u32 dh_p[] = { ++ 96, ++ 0xFFFFFFFF, ++ 0xFFFFFFFF, ++ 0xA93AD2CA, ++ 0x4B82D120, ++ 0xE0FD108E, ++ 0x43DB5BFC, ++ 0x74E5AB31, ++ 0x08E24FA0, ++ 0xBAD946E2, ++ 0x770988C0, ++ 0x7A615D6C, ++ 0xBBE11757, ++ 0x177B200C, ++ 0x521F2B18, ++ 0x3EC86A64, ++ 0xD8760273, ++ 0xD98A0864, ++ 0xF12FFA06, ++ 0x1AD2EE6B, ++ 0xCEE3D226, ++ 0x4A25619D, ++ 0x1E8C94E0, ++ 0xDB0933D7, ++ 0xABF5AE8C, ++ 0xA6E1E4C7, ++ 0xB3970F85, ++ 0x5D060C7D, ++ 0x8AEA7157, ++ 0x58DBEF0A, ++ 0xECFB8504, ++ 0xDF1CBA64, ++ 0xA85521AB, ++ 0x04507A33, ++ 0xAD33170D, ++ 0x8AAAC42D, ++ 0x15728E5A, ++ 0x98FA0510, ++ 0x15D22618, ++ 0xEA956AE5, ++ 0x3995497C, ++ 0x95581718, ++ 0xDE2BCBF6, ++ 0x6F4C52C9, ++ 0xB5C55DF0, ++ 0xEC07A28F, ++ 0x9B2783A2, ++ 0x180E8603, ++ 0xE39E772C, ++ 0x2E36CE3B, ++ 0x32905E46, ++ 0xCA18217C, ++ 0xF1746C08, ++ 0x4ABC9804, ++ 0x670C354E, ++ 0x7096966D, ++ 0x9ED52907, ++ 0x208552BB, ++ 0x1C62F356, ++ 0xDCA3AD96, ++ 0x83655D23, ++ 0xFD24CF5F, ++ 0x69163FA8, ++ 0x1C55D39A, ++ 0x98DA4836, ++ 0xA163BF05, ++ 0xC2007CB8, ++ 0xECE45B3D, ++ 0x49286651, ++ 0x7C4B1FE6, ++ 0xAE9F2411, ++ 0x5A899FA5, ++ 0xEE386BFB, ++ 0xF406B7ED, ++ 0x0BFF5CB6, ++ 0xA637ED6B, ++ 0xF44C42E9, ++ 0x625E7EC6, ++ 0xE485B576, ++ 0x6D51C245, ++ 0x4FE1356D, ++ 0xF25F1437, ++ 0x302B0A6D, ++ 0xCD3A431B, ++ 0xEF9519B3, ++ 0x8E3404DD, ++ 0x514A0879, ++ 0x3B139B22, ++ 0x020BBEA6, ++ 0x8A67CC74, ++ 0x29024E08, ++ 0x80DC1CD1, ++ 0xC4C6628B, ++ 0x2168C234, ++ 0xC90FDAA2, ++ 0xFFFFFFFF, ++ 0xFFFFFFFF, ++}; ++ ++static __u32 dh_a[] = { ++ 8, ++ 0xdf367516, ++ 0x86459caa, ++ 0xe2d459a4, ++ 0xd910dae0, ++ 0x8a8b5e37, ++ 0x67ab31c6, ++ 0xf0b55ea9, ++ 0x440051d6, ++}; ++ ++static __u32 dh_b[] = { ++ 8, ++ 0xded92656, ++ 0xe07a048a, ++ 0x6fa452cd, ++ 0x2df89d30, ++ 0xc75f1b0f, ++ 0x8ce3578f, ++ 0x7980a324, ++ 0x5daec786, ++}; ++ ++static __u32 dh_g[] = { ++ 1, ++ 2, ++}; ++ ++int main(void) ++{ ++ int i; ++ __u32 *k; ++ k = dwc_modpow(NULL, dh_g, dh_a, dh_p); ++ ++ printf("\n\n"); ++ for (i=0; i> 16; ++ printf("%04x %04x ", m, l); ++ if (!((i + 1)%13)) printf("\n"); ++ } ++ printf("\n\n"); ++ ++ if ((k[0] == 0x60) && (k[1] == 0x28e490e5) && (k[0x60] == 0x5a0d3d4e)) { ++ printf("PASS\n\n"); ++ } ++ else { ++ printf("FAIL\n\n"); ++ } ++ ++} ++ ++#endif /* UNITTEST */ ++ ++#endif /* CONFIG_MACH_IPMATE */ ++ ++#endif /*DWC_CRYPTOLIB */ +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_modpow.h linux-rpi/drivers/usb/host/dwc_common_port/dwc_modpow.h +--- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_modpow.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_modpow.h 2015-11-29 09:42:39.915098960 +0100 +@@ -0,0 +1,34 @@ ++/* ++ * dwc_modpow.h ++ * See dwc_modpow.c for license and changes ++ */ ++#ifndef _DWC_MODPOW_H ++#define _DWC_MODPOW_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "dwc_os.h" ++ ++/** @file ++ * ++ * This file defines the module exponentiation function which is only used ++ * internally by the DWC UWB modules for calculation of PKs during numeric ++ * association. The routine is taken from the PUTTY, an open source terminal ++ * emulator. The PUTTY License is preserved in the dwc_modpow.c file. ++ * ++ */ ++ ++typedef uint32_t BignumInt; ++typedef uint64_t BignumDblInt; ++typedef BignumInt *Bignum; ++ ++/* Compute modular exponentiaion */ ++extern Bignum dwc_modpow(void *mem_ctx, Bignum base_in, Bignum exp, Bignum mod); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif /* _LINUX_BIGNUM_H */ +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_notifier.c linux-rpi/drivers/usb/host/dwc_common_port/dwc_notifier.c +--- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_notifier.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_notifier.c 2015-11-29 09:42:39.915098960 +0100 +@@ -0,0 +1,319 @@ ++#ifdef DWC_NOTIFYLIB ++ ++#include "dwc_notifier.h" ++#include "dwc_list.h" ++ ++typedef struct dwc_observer { ++ void *observer; ++ dwc_notifier_callback_t callback; ++ void *data; ++ char *notification; ++ DWC_CIRCLEQ_ENTRY(dwc_observer) list_entry; ++} observer_t; ++ ++DWC_CIRCLEQ_HEAD(observer_queue, dwc_observer); ++ ++typedef struct dwc_notifier { ++ void *mem_ctx; ++ void *object; ++ struct observer_queue observers; ++ DWC_CIRCLEQ_ENTRY(dwc_notifier) list_entry; ++} notifier_t; ++ ++DWC_CIRCLEQ_HEAD(notifier_queue, dwc_notifier); ++ ++typedef struct manager { ++ void *mem_ctx; ++ void *wkq_ctx; ++ dwc_workq_t *wq; ++// dwc_mutex_t *mutex; ++ struct notifier_queue notifiers; ++} manager_t; ++ ++static manager_t *manager = NULL; ++ ++static int create_manager(void *mem_ctx, void *wkq_ctx) ++{ ++ manager = dwc_alloc(mem_ctx, sizeof(manager_t)); ++ if (!manager) { ++ return -DWC_E_NO_MEMORY; ++ } ++ ++ DWC_CIRCLEQ_INIT(&manager->notifiers); ++ ++ manager->wq = dwc_workq_alloc(wkq_ctx, "DWC Notification WorkQ"); ++ if (!manager->wq) { ++ return -DWC_E_NO_MEMORY; ++ } ++ ++ return 0; ++} ++ ++static void free_manager(void) ++{ ++ dwc_workq_free(manager->wq); ++ ++ /* All notifiers must have unregistered themselves before this module ++ * can be removed. Hitting this assertion indicates a programmer ++ * error. */ ++ DWC_ASSERT(DWC_CIRCLEQ_EMPTY(&manager->notifiers), ++ "Notification manager being freed before all notifiers have been removed"); ++ dwc_free(manager->mem_ctx, manager); ++} ++ ++#ifdef DEBUG ++static void dump_manager(void) ++{ ++ notifier_t *n; ++ observer_t *o; ++ ++ DWC_ASSERT(manager, "Notification manager not found"); ++ ++ DWC_DEBUG("List of all notifiers and observers:\n"); ++ DWC_CIRCLEQ_FOREACH(n, &manager->notifiers, list_entry) { ++ DWC_DEBUG("Notifier %p has observers:\n", n->object); ++ DWC_CIRCLEQ_FOREACH(o, &n->observers, list_entry) { ++ DWC_DEBUG(" %p watching %s\n", o->observer, o->notification); ++ } ++ } ++} ++#else ++#define dump_manager(...) ++#endif ++ ++static observer_t *alloc_observer(void *mem_ctx, void *observer, char *notification, ++ dwc_notifier_callback_t callback, void *data) ++{ ++ observer_t *new_observer = dwc_alloc(mem_ctx, sizeof(observer_t)); ++ ++ if (!new_observer) { ++ return NULL; ++ } ++ ++ DWC_CIRCLEQ_INIT_ENTRY(new_observer, list_entry); ++ new_observer->observer = observer; ++ new_observer->notification = notification; ++ new_observer->callback = callback; ++ new_observer->data = data; ++ return new_observer; ++} ++ ++static void free_observer(void *mem_ctx, observer_t *observer) ++{ ++ dwc_free(mem_ctx, observer); ++} ++ ++static notifier_t *alloc_notifier(void *mem_ctx, void *object) ++{ ++ notifier_t *notifier; ++ ++ if (!object) { ++ return NULL; ++ } ++ ++ notifier = dwc_alloc(mem_ctx, sizeof(notifier_t)); ++ if (!notifier) { ++ return NULL; ++ } ++ ++ DWC_CIRCLEQ_INIT(¬ifier->observers); ++ DWC_CIRCLEQ_INIT_ENTRY(notifier, list_entry); ++ ++ notifier->mem_ctx = mem_ctx; ++ notifier->object = object; ++ return notifier; ++} ++ ++static void free_notifier(notifier_t *notifier) ++{ ++ observer_t *observer; ++ ++ DWC_CIRCLEQ_FOREACH(observer, ¬ifier->observers, list_entry) { ++ free_observer(notifier->mem_ctx, observer); ++ } ++ ++ dwc_free(notifier->mem_ctx, notifier); ++} ++ ++static notifier_t *find_notifier(void *object) ++{ ++ notifier_t *notifier; ++ ++ DWC_ASSERT(manager, "Notification manager not found"); ++ ++ if (!object) { ++ return NULL; ++ } ++ ++ DWC_CIRCLEQ_FOREACH(notifier, &manager->notifiers, list_entry) { ++ if (notifier->object == object) { ++ return notifier; ++ } ++ } ++ ++ return NULL; ++} ++ ++int dwc_alloc_notification_manager(void *mem_ctx, void *wkq_ctx) ++{ ++ return create_manager(mem_ctx, wkq_ctx); ++} ++ ++void dwc_free_notification_manager(void) ++{ ++ free_manager(); ++} ++ ++dwc_notifier_t *dwc_register_notifier(void *mem_ctx, void *object) ++{ ++ notifier_t *notifier; ++ ++ DWC_ASSERT(manager, "Notification manager not found"); ++ ++ notifier = find_notifier(object); ++ if (notifier) { ++ DWC_ERROR("Notifier %p is already registered\n", object); ++ return NULL; ++ } ++ ++ notifier = alloc_notifier(mem_ctx, object); ++ if (!notifier) { ++ return NULL; ++ } ++ ++ DWC_CIRCLEQ_INSERT_TAIL(&manager->notifiers, notifier, list_entry); ++ ++ DWC_INFO("Notifier %p registered", object); ++ dump_manager(); ++ ++ return notifier; ++} ++ ++void dwc_unregister_notifier(dwc_notifier_t *notifier) ++{ ++ DWC_ASSERT(manager, "Notification manager not found"); ++ ++ if (!DWC_CIRCLEQ_EMPTY(¬ifier->observers)) { ++ observer_t *o; ++ ++ DWC_ERROR("Notifier %p has active observers when removing\n", notifier->object); ++ DWC_CIRCLEQ_FOREACH(o, ¬ifier->observers, list_entry) { ++ DWC_DEBUGC(" %p watching %s\n", o->observer, o->notification); ++ } ++ ++ DWC_ASSERT(DWC_CIRCLEQ_EMPTY(¬ifier->observers), ++ "Notifier %p has active observers when removing", notifier); ++ } ++ ++ DWC_CIRCLEQ_REMOVE_INIT(&manager->notifiers, notifier, list_entry); ++ free_notifier(notifier); ++ ++ DWC_INFO("Notifier unregistered"); ++ dump_manager(); ++} ++ ++/* Add an observer to observe the notifier for a particular state, event, or notification. */ ++int dwc_add_observer(void *observer, void *object, char *notification, ++ dwc_notifier_callback_t callback, void *data) ++{ ++ notifier_t *notifier = find_notifier(object); ++ observer_t *new_observer; ++ ++ if (!notifier) { ++ DWC_ERROR("Notifier %p is not found when adding observer\n", object); ++ return -DWC_E_INVALID; ++ } ++ ++ new_observer = alloc_observer(notifier->mem_ctx, observer, notification, callback, data); ++ if (!new_observer) { ++ return -DWC_E_NO_MEMORY; ++ } ++ ++ DWC_CIRCLEQ_INSERT_TAIL(¬ifier->observers, new_observer, list_entry); ++ ++ DWC_INFO("Added observer %p to notifier %p observing notification %s, callback=%p, data=%p", ++ observer, object, notification, callback, data); ++ ++ dump_manager(); ++ return 0; ++} ++ ++int dwc_remove_observer(void *observer) ++{ ++ notifier_t *n; ++ ++ DWC_ASSERT(manager, "Notification manager not found"); ++ ++ DWC_CIRCLEQ_FOREACH(n, &manager->notifiers, list_entry) { ++ observer_t *o; ++ observer_t *o2; ++ ++ DWC_CIRCLEQ_FOREACH_SAFE(o, o2, &n->observers, list_entry) { ++ if (o->observer == observer) { ++ DWC_CIRCLEQ_REMOVE_INIT(&n->observers, o, list_entry); ++ DWC_INFO("Removing observer %p from notifier %p watching notification %s:", ++ o->observer, n->object, o->notification); ++ free_observer(n->mem_ctx, o); ++ } ++ } ++ } ++ ++ dump_manager(); ++ return 0; ++} ++ ++typedef struct callback_data { ++ void *mem_ctx; ++ dwc_notifier_callback_t cb; ++ void *observer; ++ void *data; ++ void *object; ++ char *notification; ++ void *notification_data; ++} cb_data_t; ++ ++static void cb_task(void *data) ++{ ++ cb_data_t *cb = (cb_data_t *)data; ++ ++ cb->cb(cb->object, cb->notification, cb->observer, cb->notification_data, cb->data); ++ dwc_free(cb->mem_ctx, cb); ++} ++ ++void dwc_notify(dwc_notifier_t *notifier, char *notification, void *notification_data) ++{ ++ observer_t *o; ++ ++ DWC_ASSERT(manager, "Notification manager not found"); ++ ++ DWC_CIRCLEQ_FOREACH(o, ¬ifier->observers, list_entry) { ++ int len = DWC_STRLEN(notification); ++ ++ if (DWC_STRLEN(o->notification) != len) { ++ continue; ++ } ++ ++ if (DWC_STRNCMP(o->notification, notification, len) == 0) { ++ cb_data_t *cb_data = dwc_alloc(notifier->mem_ctx, sizeof(cb_data_t)); ++ ++ if (!cb_data) { ++ DWC_ERROR("Failed to allocate callback data\n"); ++ return; ++ } ++ ++ cb_data->mem_ctx = notifier->mem_ctx; ++ cb_data->cb = o->callback; ++ cb_data->observer = o->observer; ++ cb_data->data = o->data; ++ cb_data->object = notifier->object; ++ cb_data->notification = notification; ++ cb_data->notification_data = notification_data; ++ DWC_DEBUGC("Observer found %p for notification %s\n", o->observer, notification); ++ DWC_WORKQ_SCHEDULE(manager->wq, cb_task, cb_data, ++ "Notify callback from %p for Notification %s, to observer %p", ++ cb_data->object, notification, cb_data->observer); ++ } ++ } ++} ++ ++#endif /* DWC_NOTIFYLIB */ +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_notifier.h linux-rpi/drivers/usb/host/dwc_common_port/dwc_notifier.h +--- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_notifier.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_notifier.h 2015-11-29 09:42:39.915098960 +0100 +@@ -0,0 +1,122 @@ ++ ++#ifndef __DWC_NOTIFIER_H__ ++#define __DWC_NOTIFIER_H__ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "dwc_os.h" ++ ++/** @file ++ * ++ * A simple implementation of the Observer pattern. Any "module" can ++ * register as an observer or notifier. The notion of "module" is abstract and ++ * can mean anything used to identify either an observer or notifier. Usually ++ * it will be a pointer to a data structure which contains some state, ie an ++ * object. ++ * ++ * Before any notifiers can be added, the global notification manager must be ++ * brought up with dwc_alloc_notification_manager(). ++ * dwc_free_notification_manager() will bring it down and free all resources. ++ * These would typically be called upon module load and unload. The ++ * notification manager is a single global instance that handles all registered ++ * observable modules and observers so this should be done only once. ++ * ++ * A module can be observable by using Notifications to publicize some general ++ * information about it's state or operation. It does not care who listens, or ++ * even if anyone listens, or what they do with the information. The observable ++ * modules do not need to know any information about it's observers or their ++ * interface, or their state or data. ++ * ++ * Any module can register to emit Notifications. It should publish a list of ++ * notifications that it can emit and their behavior, such as when they will get ++ * triggered, and what information will be provided to the observer. Then it ++ * should register itself as an observable module. See dwc_register_notifier(). ++ * ++ * Any module can observe any observable, registered module, provided it has a ++ * handle to the other module and knows what notifications to observe. See ++ * dwc_add_observer(). ++ * ++ * A function of type dwc_notifier_callback_t is called whenever a notification ++ * is triggered with one or more observers observing it. This function is ++ * called in it's own process so it may sleep or block if needed. It is ++ * guaranteed to be called sometime after the notification has occurred and will ++ * be called once per each time the notification is triggered. It will NOT be ++ * called in the same process context used to trigger the notification. ++ * ++ * @section Limitiations ++ * ++ * Keep in mind that Notifications that can be triggered in rapid sucession may ++ * schedule too many processes too handle. Be aware of this limitation when ++ * designing to use notifications, and only add notifications for appropriate ++ * observable information. ++ * ++ * Also Notification callbacks are not synchronous. If you need to synchronize ++ * the behavior between module/observer you must use other means. And perhaps ++ * that will mean Notifications are not the proper solution. ++ */ ++ ++struct dwc_notifier; ++typedef struct dwc_notifier dwc_notifier_t; ++ ++/** The callback function must be of this type. ++ * ++ * @param object This is the object that is being observed. ++ * @param notification This is the notification that was triggered. ++ * @param observer This is the observer ++ * @param notification_data This is notification-specific data that the notifier ++ * has included in this notification. The value of this should be published in ++ * the documentation of the observable module with the notifications. ++ * @param user_data This is any custom data that the observer provided when ++ * adding itself as an observer to the notification. */ ++typedef void (*dwc_notifier_callback_t)(void *object, char *notification, void *observer, ++ void *notification_data, void *user_data); ++ ++/** Brings up the notification manager. */ ++extern int dwc_alloc_notification_manager(void *mem_ctx, void *wkq_ctx); ++/** Brings down the notification manager. */ ++extern void dwc_free_notification_manager(void); ++ ++/** This function registers an observable module. A dwc_notifier_t object is ++ * returned to the observable module. This is an opaque object that is used by ++ * the observable module to trigger notifications. This object should only be ++ * accessible to functions that are authorized to trigger notifications for this ++ * module. Observers do not need this object. */ ++extern dwc_notifier_t *dwc_register_notifier(void *mem_ctx, void *object); ++ ++/** This function unregisters an observable module. All observers have to be ++ * removed prior to unregistration. */ ++extern void dwc_unregister_notifier(dwc_notifier_t *notifier); ++ ++/** Add a module as an observer to the observable module. The observable module ++ * needs to have previously registered with the notification manager. ++ * ++ * @param observer The observer module ++ * @param object The module to observe ++ * @param notification The notification to observe ++ * @param callback The callback function to call ++ * @param user_data Any additional user data to pass into the callback function */ ++extern int dwc_add_observer(void *observer, void *object, char *notification, ++ dwc_notifier_callback_t callback, void *user_data); ++ ++/** Removes the specified observer from all notifications that it is currently ++ * observing. */ ++extern int dwc_remove_observer(void *observer); ++ ++/** This function triggers a Notification. It should be called by the ++ * observable module, or any module or library which the observable module ++ * allows to trigger notification on it's behalf. Such as the dwc_cc_t. ++ * ++ * dwc_notify is a non-blocking function. Callbacks are scheduled called in ++ * their own process context for each trigger. Callbacks can be blocking. ++ * dwc_notify can be called from interrupt context if needed. ++ * ++ */ ++void dwc_notify(dwc_notifier_t *notifier, char *notification, void *notification_data); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif /* __DWC_NOTIFIER_H__ */ +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_os.h linux-rpi/drivers/usb/host/dwc_common_port/dwc_os.h +--- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/dwc_os.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_common_port/dwc_os.h 2015-11-29 09:42:39.915098960 +0100 +@@ -0,0 +1,1276 @@ ++/* ========================================================================= ++ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_os.h $ ++ * $Revision: #14 $ ++ * $Date: 2010/11/04 $ ++ * $Change: 1621695 $ ++ * ++ * Synopsys Portability Library Software and documentation ++ * (hereinafter, "Software") is an Unsupported proprietary work of ++ * Synopsys, Inc. unless otherwise expressly agreed to in writing ++ * between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for ++ * Licensed Product with Synopsys or any supplement thereto. You are ++ * permitted to use and redistribute this Software in source and binary ++ * forms, with or without modification, provided that redistributions ++ * of source code must retain this notice. You may not view, use, ++ * disclose, copy or distribute this file or any information contained ++ * herein except pursuant to this license grant from Synopsys. If you ++ * do not agree with this notice, including the disclaimer below, then ++ * you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ++ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL ++ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY ++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE ++ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================= */ ++#ifndef _DWC_OS_H_ ++#define _DWC_OS_H_ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/** @file ++ * ++ * DWC portability library, low level os-wrapper functions ++ * ++ */ ++ ++/* These basic types need to be defined by some OS header file or custom header ++ * file for your specific target architecture. ++ * ++ * uint8_t, int8_t, uint16_t, int16_t, uint32_t, int32_t, uint64_t, int64_t ++ * ++ * Any custom or alternate header file must be added and enabled here. ++ */ ++ ++#ifdef DWC_LINUX ++# include ++# ifdef CONFIG_DEBUG_MUTEXES ++# include ++# endif ++# include ++# include ++# include ++#endif ++ ++#if defined(DWC_FREEBSD) || defined(DWC_NETBSD) ++# include ++#endif ++ ++ ++/** @name Primitive Types and Values */ ++ ++/** We define a boolean type for consistency. Can be either YES or NO */ ++typedef uint8_t dwc_bool_t; ++#define YES 1 ++#define NO 0 ++ ++#ifdef DWC_LINUX ++ ++/** @name Error Codes */ ++#define DWC_E_INVALID EINVAL ++#define DWC_E_NO_MEMORY ENOMEM ++#define DWC_E_NO_DEVICE ENODEV ++#define DWC_E_NOT_SUPPORTED EOPNOTSUPP ++#define DWC_E_TIMEOUT ETIMEDOUT ++#define DWC_E_BUSY EBUSY ++#define DWC_E_AGAIN EAGAIN ++#define DWC_E_RESTART ERESTART ++#define DWC_E_ABORT ECONNABORTED ++#define DWC_E_SHUTDOWN ESHUTDOWN ++#define DWC_E_NO_DATA ENODATA ++#define DWC_E_DISCONNECT ECONNRESET ++#define DWC_E_UNKNOWN EINVAL ++#define DWC_E_NO_STREAM_RES ENOSR ++#define DWC_E_COMMUNICATION ECOMM ++#define DWC_E_OVERFLOW EOVERFLOW ++#define DWC_E_PROTOCOL EPROTO ++#define DWC_E_IN_PROGRESS EINPROGRESS ++#define DWC_E_PIPE EPIPE ++#define DWC_E_IO EIO ++#define DWC_E_NO_SPACE ENOSPC ++ ++#else ++ ++/** @name Error Codes */ ++#define DWC_E_INVALID 1001 ++#define DWC_E_NO_MEMORY 1002 ++#define DWC_E_NO_DEVICE 1003 ++#define DWC_E_NOT_SUPPORTED 1004 ++#define DWC_E_TIMEOUT 1005 ++#define DWC_E_BUSY 1006 ++#define DWC_E_AGAIN 1007 ++#define DWC_E_RESTART 1008 ++#define DWC_E_ABORT 1009 ++#define DWC_E_SHUTDOWN 1010 ++#define DWC_E_NO_DATA 1011 ++#define DWC_E_DISCONNECT 2000 ++#define DWC_E_UNKNOWN 3000 ++#define DWC_E_NO_STREAM_RES 4001 ++#define DWC_E_COMMUNICATION 4002 ++#define DWC_E_OVERFLOW 4003 ++#define DWC_E_PROTOCOL 4004 ++#define DWC_E_IN_PROGRESS 4005 ++#define DWC_E_PIPE 4006 ++#define DWC_E_IO 4007 ++#define DWC_E_NO_SPACE 4008 ++ ++#endif ++ ++ ++/** @name Tracing/Logging Functions ++ * ++ * These function provide the capability to add tracing, debugging, and error ++ * messages, as well exceptions as assertions. The WUDEV uses these ++ * extensively. These could be logged to the main console, the serial port, an ++ * internal buffer, etc. These functions could also be no-op if they are too ++ * expensive on your system. By default undefining the DEBUG macro already ++ * no-ops some of these functions. */ ++ ++/** Returns non-zero if in interrupt context. */ ++extern dwc_bool_t DWC_IN_IRQ(void); ++#define dwc_in_irq DWC_IN_IRQ ++ ++/** Returns "IRQ" if DWC_IN_IRQ is true. */ ++static inline char *dwc_irq(void) { ++ return DWC_IN_IRQ() ? "IRQ" : ""; ++} ++ ++/** Returns non-zero if in bottom-half context. */ ++extern dwc_bool_t DWC_IN_BH(void); ++#define dwc_in_bh DWC_IN_BH ++ ++/** Returns "BH" if DWC_IN_BH is true. */ ++static inline char *dwc_bh(void) { ++ return DWC_IN_BH() ? "BH" : ""; ++} ++ ++/** ++ * A vprintf() clone. Just call vprintf if you've got it. ++ */ ++extern void DWC_VPRINTF(char *format, va_list args); ++#define dwc_vprintf DWC_VPRINTF ++ ++/** ++ * A vsnprintf() clone. Just call vprintf if you've got it. ++ */ ++extern int DWC_VSNPRINTF(char *str, int size, char *format, va_list args); ++#define dwc_vsnprintf DWC_VSNPRINTF ++ ++/** ++ * printf() clone. Just call printf if you've go it. ++ */ ++extern void DWC_PRINTF(char *format, ...) ++/* This provides compiler level static checking of the parameters if you're ++ * using GCC. */ ++#ifdef __GNUC__ ++ __attribute__ ((format(printf, 1, 2))); ++#else ++ ; ++#endif ++#define dwc_printf DWC_PRINTF ++ ++/** ++ * sprintf() clone. Just call sprintf if you've got it. ++ */ ++extern int DWC_SPRINTF(char *string, char *format, ...) ++#ifdef __GNUC__ ++ __attribute__ ((format(printf, 2, 3))); ++#else ++ ; ++#endif ++#define dwc_sprintf DWC_SPRINTF ++ ++/** ++ * snprintf() clone. Just call snprintf if you've got it. ++ */ ++extern int DWC_SNPRINTF(char *string, int size, char *format, ...) ++#ifdef __GNUC__ ++ __attribute__ ((format(printf, 3, 4))); ++#else ++ ; ++#endif ++#define dwc_snprintf DWC_SNPRINTF ++ ++/** ++ * Prints a WARNING message. On systems that don't differentiate between ++ * warnings and regular log messages, just print it. Indicates that something ++ * may be wrong with the driver. Works like printf(). ++ * ++ * Use the DWC_WARN macro to call this function. ++ */ ++extern void __DWC_WARN(char *format, ...) ++#ifdef __GNUC__ ++ __attribute__ ((format(printf, 1, 2))); ++#else ++ ; ++#endif ++ ++/** ++ * Prints an error message. On systems that don't differentiate between errors ++ * and regular log messages, just print it. Indicates that something went wrong ++ * with the driver. Works like printf(). ++ * ++ * Use the DWC_ERROR macro to call this function. ++ */ ++extern void __DWC_ERROR(char *format, ...) ++#ifdef __GNUC__ ++ __attribute__ ((format(printf, 1, 2))); ++#else ++ ; ++#endif ++ ++/** ++ * Prints an exception error message and takes some user-defined action such as ++ * print out a backtrace or trigger a breakpoint. Indicates that something went ++ * abnormally wrong with the driver such as programmer error, or other ++ * exceptional condition. It should not be ignored so even on systems without ++ * printing capability, some action should be taken to notify the developer of ++ * it. Works like printf(). ++ */ ++extern void DWC_EXCEPTION(char *format, ...) ++#ifdef __GNUC__ ++ __attribute__ ((format(printf, 1, 2))); ++#else ++ ; ++#endif ++#define dwc_exception DWC_EXCEPTION ++ ++#ifndef DWC_OTG_DEBUG_LEV ++#define DWC_OTG_DEBUG_LEV 0 ++#endif ++ ++#ifdef DEBUG ++/** ++ * Prints out a debug message. Used for logging/trace messages. ++ * ++ * Use the DWC_DEBUG macro to call this function ++ */ ++extern void __DWC_DEBUG(char *format, ...) ++#ifdef __GNUC__ ++ __attribute__ ((format(printf, 1, 2))); ++#else ++ ; ++#endif ++#else ++#define __DWC_DEBUG printk ++#endif ++ ++/** ++ * Prints out a Debug message. ++ */ ++#define DWC_DEBUG(_format, _args...) __DWC_DEBUG("DEBUG:%s:%s: " _format "\n", \ ++ __func__, dwc_irq(), ## _args) ++#define dwc_debug DWC_DEBUG ++/** ++ * Prints out a Debug message if enabled at compile time. ++ */ ++#if DWC_OTG_DEBUG_LEV > 0 ++#define DWC_DEBUGC(_format, _args...) DWC_DEBUG(_format, ##_args ) ++#else ++#define DWC_DEBUGC(_format, _args...) ++#endif ++#define dwc_debugc DWC_DEBUGC ++/** ++ * Prints out an informative message. ++ */ ++#define DWC_INFO(_format, _args...) DWC_PRINTF("INFO:%s: " _format "\n", \ ++ dwc_irq(), ## _args) ++#define dwc_info DWC_INFO ++/** ++ * Prints out an informative message if enabled at compile time. ++ */ ++#if DWC_OTG_DEBUG_LEV > 1 ++#define DWC_INFOC(_format, _args...) DWC_INFO(_format, ##_args ) ++#else ++#define DWC_INFOC(_format, _args...) ++#endif ++#define dwc_infoc DWC_INFOC ++/** ++ * Prints out a warning message. ++ */ ++#define DWC_WARN(_format, _args...) __DWC_WARN("WARN:%s:%s:%d: " _format "\n", \ ++ dwc_irq(), __func__, __LINE__, ## _args) ++#define dwc_warn DWC_WARN ++/** ++ * Prints out an error message. ++ */ ++#define DWC_ERROR(_format, _args...) __DWC_ERROR("ERROR:%s:%s:%d: " _format "\n", \ ++ dwc_irq(), __func__, __LINE__, ## _args) ++#define dwc_error DWC_ERROR ++ ++#define DWC_PROTO_ERROR(_format, _args...) __DWC_WARN("ERROR:%s:%s:%d: " _format "\n", \ ++ dwc_irq(), __func__, __LINE__, ## _args) ++#define dwc_proto_error DWC_PROTO_ERROR ++ ++#ifdef DEBUG ++/** Prints out a exception error message if the _expr expression fails. Disabled ++ * if DEBUG is not enabled. */ ++#define DWC_ASSERT(_expr, _format, _args...) do { \ ++ if (!(_expr)) { DWC_EXCEPTION("%s:%s:%d: " _format "\n", dwc_irq(), \ ++ __FILE__, __LINE__, ## _args); } \ ++ } while (0) ++#else ++#define DWC_ASSERT(_x...) ++#endif ++#define dwc_assert DWC_ASSERT ++ ++ ++/** @name Byte Ordering ++ * The following functions are for conversions between processor's byte ordering ++ * and specific ordering you want. ++ */ ++ ++/** Converts 32 bit data in CPU byte ordering to little endian. */ ++extern uint32_t DWC_CPU_TO_LE32(uint32_t *p); ++#define dwc_cpu_to_le32 DWC_CPU_TO_LE32 ++ ++/** Converts 32 bit data in CPU byte orderint to big endian. */ ++extern uint32_t DWC_CPU_TO_BE32(uint32_t *p); ++#define dwc_cpu_to_be32 DWC_CPU_TO_BE32 ++ ++/** Converts 32 bit little endian data to CPU byte ordering. */ ++extern uint32_t DWC_LE32_TO_CPU(uint32_t *p); ++#define dwc_le32_to_cpu DWC_LE32_TO_CPU ++ ++/** Converts 32 bit big endian data to CPU byte ordering. */ ++extern uint32_t DWC_BE32_TO_CPU(uint32_t *p); ++#define dwc_be32_to_cpu DWC_BE32_TO_CPU ++ ++/** Converts 16 bit data in CPU byte ordering to little endian. */ ++extern uint16_t DWC_CPU_TO_LE16(uint16_t *p); ++#define dwc_cpu_to_le16 DWC_CPU_TO_LE16 ++ ++/** Converts 16 bit data in CPU byte orderint to big endian. */ ++extern uint16_t DWC_CPU_TO_BE16(uint16_t *p); ++#define dwc_cpu_to_be16 DWC_CPU_TO_BE16 ++ ++/** Converts 16 bit little endian data to CPU byte ordering. */ ++extern uint16_t DWC_LE16_TO_CPU(uint16_t *p); ++#define dwc_le16_to_cpu DWC_LE16_TO_CPU ++ ++/** Converts 16 bit bi endian data to CPU byte ordering. */ ++extern uint16_t DWC_BE16_TO_CPU(uint16_t *p); ++#define dwc_be16_to_cpu DWC_BE16_TO_CPU ++ ++ ++/** @name Register Read/Write ++ * ++ * The following six functions should be implemented to read/write registers of ++ * 32-bit and 64-bit sizes. All modules use this to read/write register values. ++ * The reg value is a pointer to the register calculated from the void *base ++ * variable passed into the driver when it is started. */ ++ ++#ifdef DWC_LINUX ++/* Linux doesn't need any extra parameters for register read/write, so we ++ * just throw away the IO context parameter. ++ */ ++/** Reads the content of a 32-bit register. */ ++extern uint32_t DWC_READ_REG32(uint32_t volatile *reg); ++#define dwc_read_reg32(_ctx_,_reg_) DWC_READ_REG32(_reg_) ++ ++/** Reads the content of a 64-bit register. */ ++extern uint64_t DWC_READ_REG64(uint64_t volatile *reg); ++#define dwc_read_reg64(_ctx_,_reg_) DWC_READ_REG64(_reg_) ++ ++/** Writes to a 32-bit register. */ ++extern void DWC_WRITE_REG32(uint32_t volatile *reg, uint32_t value); ++#define dwc_write_reg32(_ctx_,_reg_,_val_) DWC_WRITE_REG32(_reg_, _val_) ++ ++/** Writes to a 64-bit register. */ ++extern void DWC_WRITE_REG64(uint64_t volatile *reg, uint64_t value); ++#define dwc_write_reg64(_ctx_,_reg_,_val_) DWC_WRITE_REG64(_reg_, _val_) ++ ++/** ++ * Modify bit values in a register. Using the ++ * algorithm: (reg_contents & ~clear_mask) | set_mask. ++ */ ++extern void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask); ++#define dwc_modify_reg32(_ctx_,_reg_,_cmsk_,_smsk_) DWC_MODIFY_REG32(_reg_,_cmsk_,_smsk_) ++extern void DWC_MODIFY_REG64(uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask); ++#define dwc_modify_reg64(_ctx_,_reg_,_cmsk_,_smsk_) DWC_MODIFY_REG64(_reg_,_cmsk_,_smsk_) ++ ++#endif /* DWC_LINUX */ ++ ++#if defined(DWC_FREEBSD) || defined(DWC_NETBSD) ++typedef struct dwc_ioctx { ++ struct device *dev; ++ bus_space_tag_t iot; ++ bus_space_handle_t ioh; ++} dwc_ioctx_t; ++ ++/** BSD needs two extra parameters for register read/write, so we pass ++ * them in using the IO context parameter. ++ */ ++/** Reads the content of a 32-bit register. */ ++extern uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg); ++#define dwc_read_reg32 DWC_READ_REG32 ++ ++/** Reads the content of a 64-bit register. */ ++extern uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg); ++#define dwc_read_reg64 DWC_READ_REG64 ++ ++/** Writes to a 32-bit register. */ ++extern void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value); ++#define dwc_write_reg32 DWC_WRITE_REG32 ++ ++/** Writes to a 64-bit register. */ ++extern void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value); ++#define dwc_write_reg64 DWC_WRITE_REG64 ++ ++/** ++ * Modify bit values in a register. Using the ++ * algorithm: (reg_contents & ~clear_mask) | set_mask. ++ */ ++extern void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask); ++#define dwc_modify_reg32 DWC_MODIFY_REG32 ++extern void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask); ++#define dwc_modify_reg64 DWC_MODIFY_REG64 ++ ++#endif /* DWC_FREEBSD || DWC_NETBSD */ ++ ++/** @cond */ ++ ++/** @name Some convenience MACROS used internally. Define DWC_DEBUG_REGS to log the ++ * register writes. */ ++ ++#ifdef DWC_LINUX ++ ++# ifdef DWC_DEBUG_REGS ++ ++#define dwc_define_read_write_reg_n(_reg,_container_type) \ ++static inline uint32_t dwc_read_##_reg##_n(_container_type *container, int num) { \ ++ return DWC_READ_REG32(&container->regs->_reg[num]); \ ++} \ ++static inline void dwc_write_##_reg##_n(_container_type *container, int num, uint32_t data) { \ ++ DWC_DEBUG("WRITING %8s[%d]: %p: %08x", #_reg, num, \ ++ &(((uint32_t*)container->regs->_reg)[num]), data); \ ++ DWC_WRITE_REG32(&(((uint32_t*)container->regs->_reg)[num]), data); \ ++} ++ ++#define dwc_define_read_write_reg(_reg,_container_type) \ ++static inline uint32_t dwc_read_##_reg(_container_type *container) { \ ++ return DWC_READ_REG32(&container->regs->_reg); \ ++} \ ++static inline void dwc_write_##_reg(_container_type *container, uint32_t data) { \ ++ DWC_DEBUG("WRITING %11s: %p: %08x", #_reg, &container->regs->_reg, data); \ ++ DWC_WRITE_REG32(&container->regs->_reg, data); \ ++} ++ ++# else /* DWC_DEBUG_REGS */ ++ ++#define dwc_define_read_write_reg_n(_reg,_container_type) \ ++static inline uint32_t dwc_read_##_reg##_n(_container_type *container, int num) { \ ++ return DWC_READ_REG32(&container->regs->_reg[num]); \ ++} \ ++static inline void dwc_write_##_reg##_n(_container_type *container, int num, uint32_t data) { \ ++ DWC_WRITE_REG32(&(((uint32_t*)container->regs->_reg)[num]), data); \ ++} ++ ++#define dwc_define_read_write_reg(_reg,_container_type) \ ++static inline uint32_t dwc_read_##_reg(_container_type *container) { \ ++ return DWC_READ_REG32(&container->regs->_reg); \ ++} \ ++static inline void dwc_write_##_reg(_container_type *container, uint32_t data) { \ ++ DWC_WRITE_REG32(&container->regs->_reg, data); \ ++} ++ ++# endif /* DWC_DEBUG_REGS */ ++ ++#endif /* DWC_LINUX */ ++ ++#if defined(DWC_FREEBSD) || defined(DWC_NETBSD) ++ ++# ifdef DWC_DEBUG_REGS ++ ++#define dwc_define_read_write_reg_n(_reg,_container_type) \ ++static inline uint32_t dwc_read_##_reg##_n(void *io_ctx, _container_type *container, int num) { \ ++ return DWC_READ_REG32(io_ctx, &container->regs->_reg[num]); \ ++} \ ++static inline void dwc_write_##_reg##_n(void *io_ctx, _container_type *container, int num, uint32_t data) { \ ++ DWC_DEBUG("WRITING %8s[%d]: %p: %08x", #_reg, num, \ ++ &(((uint32_t*)container->regs->_reg)[num]), data); \ ++ DWC_WRITE_REG32(io_ctx, &(((uint32_t*)container->regs->_reg)[num]), data); \ ++} ++ ++#define dwc_define_read_write_reg(_reg,_container_type) \ ++static inline uint32_t dwc_read_##_reg(void *io_ctx, _container_type *container) { \ ++ return DWC_READ_REG32(io_ctx, &container->regs->_reg); \ ++} \ ++static inline void dwc_write_##_reg(void *io_ctx, _container_type *container, uint32_t data) { \ ++ DWC_DEBUG("WRITING %11s: %p: %08x", #_reg, &container->regs->_reg, data); \ ++ DWC_WRITE_REG32(io_ctx, &container->regs->_reg, data); \ ++} ++ ++# else /* DWC_DEBUG_REGS */ ++ ++#define dwc_define_read_write_reg_n(_reg,_container_type) \ ++static inline uint32_t dwc_read_##_reg##_n(void *io_ctx, _container_type *container, int num) { \ ++ return DWC_READ_REG32(io_ctx, &container->regs->_reg[num]); \ ++} \ ++static inline void dwc_write_##_reg##_n(void *io_ctx, _container_type *container, int num, uint32_t data) { \ ++ DWC_WRITE_REG32(io_ctx, &(((uint32_t*)container->regs->_reg)[num]), data); \ ++} ++ ++#define dwc_define_read_write_reg(_reg,_container_type) \ ++static inline uint32_t dwc_read_##_reg(void *io_ctx, _container_type *container) { \ ++ return DWC_READ_REG32(io_ctx, &container->regs->_reg); \ ++} \ ++static inline void dwc_write_##_reg(void *io_ctx, _container_type *container, uint32_t data) { \ ++ DWC_WRITE_REG32(io_ctx, &container->regs->_reg, data); \ ++} ++ ++# endif /* DWC_DEBUG_REGS */ ++ ++#endif /* DWC_FREEBSD || DWC_NETBSD */ ++ ++/** @endcond */ ++ ++ ++#ifdef DWC_CRYPTOLIB ++/** @name Crypto Functions ++ * ++ * These are the low-level cryptographic functions used by the driver. */ ++ ++/** Perform AES CBC */ ++extern int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out); ++#define dwc_aes_cbc DWC_AES_CBC ++ ++/** Fill the provided buffer with random bytes. These should be cryptographic grade random numbers. */ ++extern void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length); ++#define dwc_random_bytes DWC_RANDOM_BYTES ++ ++/** Perform the SHA-256 hash function */ ++extern int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out); ++#define dwc_sha256 DWC_SHA256 ++ ++/** Calculated the HMAC-SHA256 */ ++extern int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t *out); ++#define dwc_hmac_sha256 DWC_HMAC_SHA256 ++ ++#endif /* DWC_CRYPTOLIB */ ++ ++ ++/** @name Memory Allocation ++ * ++ * These function provide access to memory allocation. There are only 2 DMA ++ * functions and 3 Regular memory functions that need to be implemented. None ++ * of the memory debugging routines need to be implemented. The allocation ++ * routines all ZERO the contents of the memory. ++ * ++ * Defining DWC_DEBUG_MEMORY turns on memory debugging and statistic gathering. ++ * This checks for memory leaks, keeping track of alloc/free pairs. It also ++ * keeps track of how much memory the driver is using at any given time. */ ++ ++#define DWC_PAGE_SIZE 4096 ++#define DWC_PAGE_OFFSET(addr) (((uint32_t)addr) & 0xfff) ++#define DWC_PAGE_ALIGNED(addr) ((((uint32_t)addr) & 0xfff) == 0) ++ ++#define DWC_INVALID_DMA_ADDR 0x0 ++ ++#ifdef DWC_LINUX ++/** Type for a DMA address */ ++typedef dma_addr_t dwc_dma_t; ++#endif ++ ++#if defined(DWC_FREEBSD) || defined(DWC_NETBSD) ++typedef bus_addr_t dwc_dma_t; ++#endif ++ ++#ifdef DWC_FREEBSD ++typedef struct dwc_dmactx { ++ struct device *dev; ++ bus_dma_tag_t dma_tag; ++ bus_dmamap_t dma_map; ++ bus_addr_t dma_paddr; ++ void *dma_vaddr; ++} dwc_dmactx_t; ++#endif ++ ++#ifdef DWC_NETBSD ++typedef struct dwc_dmactx { ++ struct device *dev; ++ bus_dma_tag_t dma_tag; ++ bus_dmamap_t dma_map; ++ bus_dma_segment_t segs[1]; ++ int nsegs; ++ bus_addr_t dma_paddr; ++ void *dma_vaddr; ++} dwc_dmactx_t; ++#endif ++ ++/* @todo these functions will be added in the future */ ++#if 0 ++/** ++ * Creates a DMA pool from which you can allocate DMA buffers. Buffers ++ * allocated from this pool will be guaranteed to meet the size, alignment, and ++ * boundary requirements specified. ++ * ++ * @param[in] size Specifies the size of the buffers that will be allocated from ++ * this pool. ++ * @param[in] align Specifies the byte alignment requirements of the buffers ++ * allocated from this pool. Must be a power of 2. ++ * @param[in] boundary Specifies the N-byte boundary that buffers allocated from ++ * this pool must not cross. ++ * ++ * @returns A pointer to an internal opaque structure which is not to be ++ * accessed outside of these library functions. Use this handle to specify ++ * which pools to allocate/free DMA buffers from and also to destroy the pool, ++ * when you are done with it. ++ */ ++extern dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size, uint32_t align, uint32_t boundary); ++ ++/** ++ * Destroy a DMA pool. All buffers allocated from that pool must be freed first. ++ */ ++extern void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool); ++ ++/** ++ * Allocate a buffer from the specified DMA pool and zeros its contents. ++ */ ++extern void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr); ++ ++/** ++ * Free a previously allocated buffer from the DMA pool. ++ */ ++extern void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr); ++#endif ++ ++/** Allocates a DMA capable buffer and zeroes its contents. */ ++extern void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr); ++ ++/** Allocates a DMA capable buffer and zeroes its contents in atomic contest */ ++extern void *__DWC_DMA_ALLOC_ATOMIC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr); ++ ++/** Frees a previously allocated buffer. */ ++extern void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr); ++ ++/** Allocates a block of memory and zeroes its contents. */ ++extern void *__DWC_ALLOC(void *mem_ctx, uint32_t size); ++ ++/** Allocates a block of memory and zeroes its contents, in an atomic manner ++ * which can be used inside interrupt context. The size should be sufficiently ++ * small, a few KB at most, such that failures are not likely to occur. Can just call ++ * __DWC_ALLOC if it is atomic. */ ++extern void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size); ++ ++/** Frees a previously allocated buffer. */ ++extern void __DWC_FREE(void *mem_ctx, void *addr); ++ ++#ifndef DWC_DEBUG_MEMORY ++ ++#define DWC_ALLOC(_size_) __DWC_ALLOC(NULL, _size_) ++#define DWC_ALLOC_ATOMIC(_size_) __DWC_ALLOC_ATOMIC(NULL, _size_) ++#define DWC_FREE(_addr_) __DWC_FREE(NULL, _addr_) ++ ++# ifdef DWC_LINUX ++#define DWC_DMA_ALLOC(_size_,_dma_) __DWC_DMA_ALLOC(NULL, _size_, _dma_) ++#define DWC_DMA_ALLOC_ATOMIC(_size_,_dma_) __DWC_DMA_ALLOC_ATOMIC(NULL, _size_,_dma_) ++#define DWC_DMA_FREE(_size_,_virt_,_dma_) __DWC_DMA_FREE(NULL, _size_, _virt_, _dma_) ++# endif ++ ++# if defined(DWC_FREEBSD) || defined(DWC_NETBSD) ++#define DWC_DMA_ALLOC __DWC_DMA_ALLOC ++#define DWC_DMA_FREE __DWC_DMA_FREE ++# endif ++extern void *dwc_dma_alloc_atomic_debug(uint32_t size, dwc_dma_t *dma_addr, char const *func, int line); ++ ++#else /* DWC_DEBUG_MEMORY */ ++ ++extern void *dwc_alloc_debug(void *mem_ctx, uint32_t size, char const *func, int line); ++extern void *dwc_alloc_atomic_debug(void *mem_ctx, uint32_t size, char const *func, int line); ++extern void dwc_free_debug(void *mem_ctx, void *addr, char const *func, int line); ++extern void *dwc_dma_alloc_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr, ++ char const *func, int line); ++extern void *dwc_dma_alloc_atomic_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr, ++ char const *func, int line); ++extern void dwc_dma_free_debug(void *dma_ctx, uint32_t size, void *virt_addr, ++ dwc_dma_t dma_addr, char const *func, int line); ++ ++extern int dwc_memory_debug_start(void *mem_ctx); ++extern void dwc_memory_debug_stop(void); ++extern void dwc_memory_debug_report(void); ++ ++#define DWC_ALLOC(_size_) dwc_alloc_debug(NULL, _size_, __func__, __LINE__) ++#define DWC_ALLOC_ATOMIC(_size_) dwc_alloc_atomic_debug(NULL, _size_, \ ++ __func__, __LINE__) ++#define DWC_FREE(_addr_) dwc_free_debug(NULL, _addr_, __func__, __LINE__) ++ ++# ifdef DWC_LINUX ++#define DWC_DMA_ALLOC(_size_,_dma_) dwc_dma_alloc_debug(NULL, _size_, \ ++ _dma_, __func__, __LINE__) ++#define DWC_DMA_ALLOC_ATOMIC(_size_,_dma_) dwc_dma_alloc_atomic_debug(NULL, _size_, \ ++ _dma_, __func__, __LINE__) ++#define DWC_DMA_FREE(_size_,_virt_,_dma_) dwc_dma_free_debug(NULL, _size_, \ ++ _virt_, _dma_, __func__, __LINE__) ++# endif ++ ++# if defined(DWC_FREEBSD) || defined(DWC_NETBSD) ++#define DWC_DMA_ALLOC(_ctx_,_size_,_dma_) dwc_dma_alloc_debug(_ctx_, _size_, \ ++ _dma_, __func__, __LINE__) ++#define DWC_DMA_FREE(_ctx_,_size_,_virt_,_dma_) dwc_dma_free_debug(_ctx_, _size_, \ ++ _virt_, _dma_, __func__, __LINE__) ++# endif ++ ++#endif /* DWC_DEBUG_MEMORY */ ++ ++#define dwc_alloc(_ctx_,_size_) DWC_ALLOC(_size_) ++#define dwc_alloc_atomic(_ctx_,_size_) DWC_ALLOC_ATOMIC(_size_) ++#define dwc_free(_ctx_,_addr_) DWC_FREE(_addr_) ++ ++#ifdef DWC_LINUX ++/* Linux doesn't need any extra parameters for DMA buffer allocation, so we ++ * just throw away the DMA context parameter. ++ */ ++#define dwc_dma_alloc(_ctx_,_size_,_dma_) DWC_DMA_ALLOC(_size_, _dma_) ++#define dwc_dma_alloc_atomic(_ctx_,_size_,_dma_) DWC_DMA_ALLOC_ATOMIC(_size_, _dma_) ++#define dwc_dma_free(_ctx_,_size_,_virt_,_dma_) DWC_DMA_FREE(_size_, _virt_, _dma_) ++#endif ++ ++#if defined(DWC_FREEBSD) || defined(DWC_NETBSD) ++/** BSD needs several extra parameters for DMA buffer allocation, so we pass ++ * them in using the DMA context parameter. ++ */ ++#define dwc_dma_alloc DWC_DMA_ALLOC ++#define dwc_dma_free DWC_DMA_FREE ++#endif ++ ++ ++/** @name Memory and String Processing */ ++ ++/** memset() clone */ ++extern void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size); ++#define dwc_memset DWC_MEMSET ++ ++/** memcpy() clone */ ++extern void *DWC_MEMCPY(void *dest, void const *src, uint32_t size); ++#define dwc_memcpy DWC_MEMCPY ++ ++/** memmove() clone */ ++extern void *DWC_MEMMOVE(void *dest, void *src, uint32_t size); ++#define dwc_memmove DWC_MEMMOVE ++ ++/** memcmp() clone */ ++extern int DWC_MEMCMP(void *m1, void *m2, uint32_t size); ++#define dwc_memcmp DWC_MEMCMP ++ ++/** strcmp() clone */ ++extern int DWC_STRCMP(void *s1, void *s2); ++#define dwc_strcmp DWC_STRCMP ++ ++/** strncmp() clone */ ++extern int DWC_STRNCMP(void *s1, void *s2, uint32_t size); ++#define dwc_strncmp DWC_STRNCMP ++ ++/** strlen() clone, for NULL terminated ASCII strings */ ++extern int DWC_STRLEN(char const *str); ++#define dwc_strlen DWC_STRLEN ++ ++/** strcpy() clone, for NULL terminated ASCII strings */ ++extern char *DWC_STRCPY(char *to, const char *from); ++#define dwc_strcpy DWC_STRCPY ++ ++/** strdup() clone. If you wish to use memory allocation debugging, this ++ * implementation of strdup should use the DWC_* memory routines instead of ++ * calling a predefined strdup. Otherwise the memory allocated by this routine ++ * will not be seen by the debugging routines. */ ++extern char *DWC_STRDUP(char const *str); ++#define dwc_strdup(_ctx_,_str_) DWC_STRDUP(_str_) ++ ++/** NOT an atoi() clone. Read the description carefully. Returns an integer ++ * converted from the string str in base 10 unless the string begins with a "0x" ++ * in which case it is base 16. String must be a NULL terminated sequence of ++ * ASCII characters and may optionally begin with whitespace, a + or -, and a ++ * "0x" prefix if base 16. The remaining characters must be valid digits for ++ * the number and end with a NULL character. If any invalid characters are ++ * encountered or it returns with a negative error code and the results of the ++ * conversion are undefined. On sucess it returns 0. Overflow conditions are ++ * undefined. An example implementation using atoi() can be referenced from the ++ * Linux implementation. */ ++extern int DWC_ATOI(const char *str, int32_t *value); ++#define dwc_atoi DWC_ATOI ++ ++/** Same as above but for unsigned. */ ++extern int DWC_ATOUI(const char *str, uint32_t *value); ++#define dwc_atoui DWC_ATOUI ++ ++#ifdef DWC_UTFLIB ++/** This routine returns a UTF16LE unicode encoded string from a UTF8 string. */ ++extern int DWC_UTF8_TO_UTF16LE(uint8_t const *utf8string, uint16_t *utf16string, unsigned len); ++#define dwc_utf8_to_utf16le DWC_UTF8_TO_UTF16LE ++#endif ++ ++ ++/** @name Wait queues ++ * ++ * Wait queues provide a means of synchronizing between threads or processes. A ++ * process can block on a waitq if some condition is not true, waiting for it to ++ * become true. When the waitq is triggered all waiting process will get ++ * unblocked and the condition will be check again. Waitqs should be triggered ++ * every time a condition can potentially change.*/ ++struct dwc_waitq; ++ ++/** Type for a waitq */ ++typedef struct dwc_waitq dwc_waitq_t; ++ ++/** The type of waitq condition callback function. This is called every time ++ * condition is evaluated. */ ++typedef int (*dwc_waitq_condition_t)(void *data); ++ ++/** Allocate a waitq */ ++extern dwc_waitq_t *DWC_WAITQ_ALLOC(void); ++#define dwc_waitq_alloc(_ctx_) DWC_WAITQ_ALLOC() ++ ++/** Free a waitq */ ++extern void DWC_WAITQ_FREE(dwc_waitq_t *wq); ++#define dwc_waitq_free DWC_WAITQ_FREE ++ ++/** Check the condition and if it is false, block on the waitq. When unblocked, check the ++ * condition again. The function returns when the condition becomes true. The return value ++ * is 0 on condition true, DWC_WAITQ_ABORTED on abort or killed, or DWC_WAITQ_UNKNOWN on error. */ ++extern int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data); ++#define dwc_waitq_wait DWC_WAITQ_WAIT ++ ++/** Check the condition and if it is false, block on the waitq. When unblocked, ++ * check the condition again. The function returns when the condition become ++ * true or the timeout has passed. The return value is 0 on condition true or ++ * DWC_TIMED_OUT on timeout, or DWC_WAITQ_ABORTED, or DWC_WAITQ_UNKNOWN on ++ * error. */ ++extern int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, ++ void *data, int32_t msecs); ++#define dwc_waitq_wait_timeout DWC_WAITQ_WAIT_TIMEOUT ++ ++/** Trigger a waitq, unblocking all processes. This should be called whenever a condition ++ * has potentially changed. */ ++extern void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq); ++#define dwc_waitq_trigger DWC_WAITQ_TRIGGER ++ ++/** Unblock all processes waiting on the waitq with an ABORTED result. */ ++extern void DWC_WAITQ_ABORT(dwc_waitq_t *wq); ++#define dwc_waitq_abort DWC_WAITQ_ABORT ++ ++ ++/** @name Threads ++ * ++ * A thread must be explicitly stopped. It must check DWC_THREAD_SHOULD_STOP ++ * whenever it is woken up, and then return. The DWC_THREAD_STOP function ++ * returns the value from the thread. ++ */ ++ ++struct dwc_thread; ++ ++/** Type for a thread */ ++typedef struct dwc_thread dwc_thread_t; ++ ++/** The thread function */ ++typedef int (*dwc_thread_function_t)(void *data); ++ ++/** Create a thread and start it running the thread_function. Returns a handle ++ * to the thread */ ++extern dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data); ++#define dwc_thread_run(_ctx_,_func_,_name_,_data_) DWC_THREAD_RUN(_func_, _name_, _data_) ++ ++/** Stops a thread. Return the value returned by the thread. Or will return ++ * DWC_ABORT if the thread never started. */ ++extern int DWC_THREAD_STOP(dwc_thread_t *thread); ++#define dwc_thread_stop DWC_THREAD_STOP ++ ++/** Signifies to the thread that it must stop. */ ++#ifdef DWC_LINUX ++/* Linux doesn't need any parameters for kthread_should_stop() */ ++extern dwc_bool_t DWC_THREAD_SHOULD_STOP(void); ++#define dwc_thread_should_stop(_thrd_) DWC_THREAD_SHOULD_STOP() ++ ++/* No thread_exit function in Linux */ ++#define dwc_thread_exit(_thrd_) ++#endif ++ ++#if defined(DWC_FREEBSD) || defined(DWC_NETBSD) ++/** BSD needs the thread pointer for kthread_suspend_check() */ ++extern dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread); ++#define dwc_thread_should_stop DWC_THREAD_SHOULD_STOP ++ ++/** The thread must call this to exit. */ ++extern void DWC_THREAD_EXIT(dwc_thread_t *thread); ++#define dwc_thread_exit DWC_THREAD_EXIT ++#endif ++ ++ ++/** @name Work queues ++ * ++ * Workqs are used to queue a callback function to be called at some later time, ++ * in another thread. */ ++struct dwc_workq; ++ ++/** Type for a workq */ ++typedef struct dwc_workq dwc_workq_t; ++ ++/** The type of the callback function to be called. */ ++typedef void (*dwc_work_callback_t)(void *data); ++ ++/** Allocate a workq */ ++extern dwc_workq_t *DWC_WORKQ_ALLOC(char *name); ++#define dwc_workq_alloc(_ctx_,_name_) DWC_WORKQ_ALLOC(_name_) ++ ++/** Free a workq. All work must be completed before being freed. */ ++extern void DWC_WORKQ_FREE(dwc_workq_t *workq); ++#define dwc_workq_free DWC_WORKQ_FREE ++ ++/** Schedule a callback on the workq, passing in data. The function will be ++ * scheduled at some later time. */ ++extern void DWC_WORKQ_SCHEDULE(dwc_workq_t *workq, dwc_work_callback_t cb, ++ void *data, char *format, ...) ++#ifdef __GNUC__ ++ __attribute__ ((format(printf, 4, 5))); ++#else ++ ; ++#endif ++#define dwc_workq_schedule DWC_WORKQ_SCHEDULE ++ ++/** Schedule a callback on the workq, that will be called until at least ++ * given number miliseconds have passed. */ ++extern void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *workq, dwc_work_callback_t cb, ++ void *data, uint32_t time, char *format, ...) ++#ifdef __GNUC__ ++ __attribute__ ((format(printf, 5, 6))); ++#else ++ ; ++#endif ++#define dwc_workq_schedule_delayed DWC_WORKQ_SCHEDULE_DELAYED ++ ++/** The number of processes in the workq */ ++extern int DWC_WORKQ_PENDING(dwc_workq_t *workq); ++#define dwc_workq_pending DWC_WORKQ_PENDING ++ ++/** Blocks until all the work in the workq is complete or timed out. Returns < ++ * 0 on timeout. */ ++extern int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout); ++#define dwc_workq_wait_work_done DWC_WORKQ_WAIT_WORK_DONE ++ ++ ++/** @name Tasklets ++ * ++ */ ++struct dwc_tasklet; ++ ++/** Type for a tasklet */ ++typedef struct dwc_tasklet dwc_tasklet_t; ++ ++/** The type of the callback function to be called */ ++typedef void (*dwc_tasklet_callback_t)(void *data); ++ ++/** Allocates a tasklet */ ++extern dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data); ++#define dwc_task_alloc(_ctx_,_name_,_cb_,_data_) DWC_TASK_ALLOC(_name_, _cb_, _data_) ++ ++/** Frees a tasklet */ ++extern void DWC_TASK_FREE(dwc_tasklet_t *task); ++#define dwc_task_free DWC_TASK_FREE ++ ++/** Schedules a tasklet to run */ ++extern void DWC_TASK_SCHEDULE(dwc_tasklet_t *task); ++#define dwc_task_schedule DWC_TASK_SCHEDULE ++ ++extern void DWC_TASK_HI_SCHEDULE(dwc_tasklet_t *task); ++#define dwc_task_hi_schedule DWC_TASK_HI_SCHEDULE ++ ++/** @name Timer ++ * ++ * Callbacks must be small and atomic. ++ */ ++struct dwc_timer; ++ ++/** Type for a timer */ ++typedef struct dwc_timer dwc_timer_t; ++ ++/** The type of the callback function to be called */ ++typedef void (*dwc_timer_callback_t)(void *data); ++ ++/** Allocates a timer */ ++extern dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data); ++#define dwc_timer_alloc(_ctx_,_name_,_cb_,_data_) DWC_TIMER_ALLOC(_name_,_cb_,_data_) ++ ++/** Frees a timer */ ++extern void DWC_TIMER_FREE(dwc_timer_t *timer); ++#define dwc_timer_free DWC_TIMER_FREE ++ ++/** Schedules the timer to run at time ms from now. And will repeat at every ++ * repeat_interval msec therafter ++ * ++ * Modifies a timer that is still awaiting execution to a new expiration time. ++ * The mod_time is added to the old time. */ ++extern void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time); ++#define dwc_timer_schedule DWC_TIMER_SCHEDULE ++ ++/** Disables the timer from execution. */ ++extern void DWC_TIMER_CANCEL(dwc_timer_t *timer); ++#define dwc_timer_cancel DWC_TIMER_CANCEL ++ ++ ++/** @name Spinlocks ++ * ++ * These locks are used when the work between the lock/unlock is atomic and ++ * short. Interrupts are also disabled during the lock/unlock and thus they are ++ * suitable to lock between interrupt/non-interrupt context. They also lock ++ * between processes if you have multiple CPUs or Preemption. If you don't have ++ * multiple CPUS or Preemption, then the you can simply implement the ++ * DWC_SPINLOCK and DWC_SPINUNLOCK to disable and enable interrupts. Because ++ * the work between the lock/unlock is atomic, the process context will never ++ * change, and so you never have to lock between processes. */ ++ ++struct dwc_spinlock; ++ ++/** Type for a spinlock */ ++typedef struct dwc_spinlock dwc_spinlock_t; ++ ++/** Type for the 'flags' argument to spinlock funtions */ ++typedef unsigned long dwc_irqflags_t; ++ ++/** Returns an initialized lock variable. This function should allocate and ++ * initialize the OS-specific data structure used for locking. This data ++ * structure is to be used for the DWC_LOCK and DWC_UNLOCK functions and should ++ * be freed by the DWC_FREE_LOCK when it is no longer used. ++ * ++ * For Linux Spinlock Debugging make it macro because the debugging routines use ++ * the symbol name to determine recursive locking. Using a wrapper function ++ * makes it falsely think recursive locking occurs. */ ++#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK) ++#define DWC_SPINLOCK_ALLOC_LINUX_DEBUG(lock) ({ \ ++ lock = DWC_ALLOC(sizeof(spinlock_t)); \ ++ if (lock) { \ ++ spin_lock_init((spinlock_t *)lock); \ ++ } \ ++}) ++#else ++extern dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void); ++#define dwc_spinlock_alloc(_ctx_) DWC_SPINLOCK_ALLOC() ++#endif ++ ++/** Frees an initialized lock variable. */ ++extern void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock); ++#define dwc_spinlock_free(_ctx_,_lock_) DWC_SPINLOCK_FREE(_lock_) ++ ++/** Disables interrupts and blocks until it acquires the lock. ++ * ++ * @param lock Pointer to the spinlock. ++ * @param flags Unsigned long for irq flags storage. ++ */ ++extern void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags); ++#define dwc_spinlock_irqsave DWC_SPINLOCK_IRQSAVE ++ ++/** Re-enables the interrupt and releases the lock. ++ * ++ * @param lock Pointer to the spinlock. ++ * @param flags Unsigned long for irq flags storage. Must be the same as was ++ * passed into DWC_LOCK. ++ */ ++extern void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags); ++#define dwc_spinunlock_irqrestore DWC_SPINUNLOCK_IRQRESTORE ++ ++/** Blocks until it acquires the lock. ++ * ++ * @param lock Pointer to the spinlock. ++ */ ++extern void DWC_SPINLOCK(dwc_spinlock_t *lock); ++#define dwc_spinlock DWC_SPINLOCK ++ ++/** Releases the lock. ++ * ++ * @param lock Pointer to the spinlock. ++ */ ++extern void DWC_SPINUNLOCK(dwc_spinlock_t *lock); ++#define dwc_spinunlock DWC_SPINUNLOCK ++ ++ ++/** @name Mutexes ++ * ++ * Unlike spinlocks Mutexes lock only between processes and the work between the ++ * lock/unlock CAN block, therefore it CANNOT be called from interrupt context. ++ */ ++ ++struct dwc_mutex; ++ ++/** Type for a mutex */ ++typedef struct dwc_mutex dwc_mutex_t; ++ ++/* For Linux Mutex Debugging make it inline because the debugging routines use ++ * the symbol to determine recursive locking. This makes it falsely think ++ * recursive locking occurs. */ ++#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES) ++#define DWC_MUTEX_ALLOC_LINUX_DEBUG(__mutexp) ({ \ ++ __mutexp = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mutex)); \ ++ mutex_init((struct mutex *)__mutexp); \ ++}) ++#endif ++ ++/** Allocate a mutex */ ++extern dwc_mutex_t *DWC_MUTEX_ALLOC(void); ++#define dwc_mutex_alloc(_ctx_) DWC_MUTEX_ALLOC() ++ ++/* For memory leak debugging when using Linux Mutex Debugging */ ++#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES) ++#define DWC_MUTEX_FREE(__mutexp) do { \ ++ mutex_destroy((struct mutex *)__mutexp); \ ++ DWC_FREE(__mutexp); \ ++} while(0) ++#else ++/** Free a mutex */ ++extern void DWC_MUTEX_FREE(dwc_mutex_t *mutex); ++#define dwc_mutex_free(_ctx_,_mutex_) DWC_MUTEX_FREE(_mutex_) ++#endif ++ ++/** Lock a mutex */ ++extern void DWC_MUTEX_LOCK(dwc_mutex_t *mutex); ++#define dwc_mutex_lock DWC_MUTEX_LOCK ++ ++/** Non-blocking lock returns 1 on successful lock. */ ++extern int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex); ++#define dwc_mutex_trylock DWC_MUTEX_TRYLOCK ++ ++/** Unlock a mutex */ ++extern void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex); ++#define dwc_mutex_unlock DWC_MUTEX_UNLOCK ++ ++ ++/** @name Time */ ++ ++/** Microsecond delay. ++ * ++ * @param usecs Microseconds to delay. ++ */ ++extern void DWC_UDELAY(uint32_t usecs); ++#define dwc_udelay DWC_UDELAY ++ ++/** Millisecond delay. ++ * ++ * @param msecs Milliseconds to delay. ++ */ ++extern void DWC_MDELAY(uint32_t msecs); ++#define dwc_mdelay DWC_MDELAY ++ ++/** Non-busy waiting. ++ * Sleeps for specified number of milliseconds. ++ * ++ * @param msecs Milliseconds to sleep. ++ */ ++extern void DWC_MSLEEP(uint32_t msecs); ++#define dwc_msleep DWC_MSLEEP ++ ++/** ++ * Returns number of milliseconds since boot. ++ */ ++extern uint32_t DWC_TIME(void); ++#define dwc_time DWC_TIME ++ ++ ++ ++ ++/* @mainpage DWC Portability and Common Library ++ * ++ * This is the documentation for the DWC Portability and Common Library. ++ * ++ * @section intro Introduction ++ * ++ * The DWC Portability library consists of wrapper calls and data structures to ++ * all low-level functions which are typically provided by the OS. The WUDEV ++ * driver uses only these functions. In order to port the WUDEV driver, only ++ * the functions in this library need to be re-implemented, with the same ++ * behavior as documented here. ++ * ++ * The Common library consists of higher level functions, which rely only on ++ * calling the functions from the DWC Portability library. These common ++ * routines are shared across modules. Some of the common libraries need to be ++ * used directly by the driver programmer when porting WUDEV. Such as the ++ * parameter and notification libraries. ++ * ++ * @section low Portability Library OS Wrapper Functions ++ * ++ * Any function starting with DWC and in all CAPS is a low-level OS-wrapper that ++ * needs to be implemented when porting, for example DWC_MUTEX_ALLOC(). All of ++ * these functions are included in the dwc_os.h file. ++ * ++ * There are many functions here covering a wide array of OS services. Please ++ * see dwc_os.h for details, and implementation notes for each function. ++ * ++ * @section common Common Library Functions ++ * ++ * Any function starting with dwc and in all lowercase is a common library ++ * routine. These functions have a portable implementation and do not need to ++ * be reimplemented when porting. The common routines can be used by any ++ * driver, and some must be used by the end user to control the drivers. For ++ * example, you must use the Parameter common library in order to set the ++ * parameters in the WUDEV module. ++ * ++ * The common libraries consist of the following: ++ * ++ * - Connection Contexts - Used internally and can be used by end-user. See dwc_cc.h ++ * - Parameters - Used internally and can be used by end-user. See dwc_params.h ++ * - Notifications - Used internally and can be used by end-user. See dwc_notifier.h ++ * - Lists - Used internally and can be used by end-user. See dwc_list.h ++ * - Memory Debugging - Used internally and can be used by end-user. See dwc_os.h ++ * - Modpow - Used internally only. See dwc_modpow.h ++ * - DH - Used internally only. See dwc_dh.h ++ * - Crypto - Used internally only. See dwc_crypto.h ++ * ++ * ++ * @section prereq Prerequistes For dwc_os.h ++ * @subsection types Data Types ++ * ++ * The dwc_os.h file assumes that several low-level data types are pre defined for the ++ * compilation environment. These data types are: ++ * ++ * - uint8_t - unsigned 8-bit data type ++ * - int8_t - signed 8-bit data type ++ * - uint16_t - unsigned 16-bit data type ++ * - int16_t - signed 16-bit data type ++ * - uint32_t - unsigned 32-bit data type ++ * - int32_t - signed 32-bit data type ++ * - uint64_t - unsigned 64-bit data type ++ * - int64_t - signed 64-bit data type ++ * ++ * Ensure that these are defined before using dwc_os.h. The easiest way to do ++ * that is to modify the top of the file to include the appropriate header. ++ * This is already done for the Linux environment. If the DWC_LINUX macro is ++ * defined, the correct header will be added. A standard header is ++ * also used for environments where standard C headers are available. ++ * ++ * @subsection stdarg Variable Arguments ++ * ++ * Variable arguments are provided by a standard C header . it is ++ * available in Both the Linux and ANSI C enviornment. An equivalent must be ++ * provided in your enviornment in order to use dwc_os.h with the debug and ++ * tracing message functionality. ++ * ++ * @subsection thread Threading ++ * ++ * WUDEV Core must be run on an operating system that provides for multiple ++ * threads/processes. Threading can be implemented in many ways, even in ++ * embedded systems without an operating system. At the bare minimum, the ++ * system should be able to start any number of processes at any time to handle ++ * special work. It need not be a pre-emptive system. Process context can ++ * change upon a call to a blocking function. The hardware interrupt context ++ * that calls the module's ISR() function must be differentiable from process ++ * context, even if your processes are impemented via a hardware interrupt. ++ * Further locking mechanism between process must exist (or be implemented), and ++ * process context must have a way to disable interrupts for a period of time to ++ * lock them out. If all of this exists, the functions in dwc_os.h related to ++ * threading should be able to be implemented with the defined behavior. ++ * ++ */ ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif /* _DWC_OS_H_ */ +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/Makefile linux-rpi/drivers/usb/host/dwc_common_port/Makefile +--- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_common_port/Makefile 2015-11-29 09:42:39.915098960 +0100 +@@ -0,0 +1,58 @@ ++# ++# Makefile for DWC_common library ++# ++ ++ifneq ($(KERNELRELEASE),) ++ ++ccflags-y += -DDWC_LINUX ++#ccflags-y += -DDEBUG ++#ccflags-y += -DDWC_DEBUG_REGS ++#ccflags-y += -DDWC_DEBUG_MEMORY ++ ++ccflags-y += -DDWC_LIBMODULE ++ccflags-y += -DDWC_CCLIB ++#ccflags-y += -DDWC_CRYPTOLIB ++ccflags-y += -DDWC_NOTIFYLIB ++ccflags-y += -DDWC_UTFLIB ++ ++obj-$(CONFIG_USB_DWCOTG) += dwc_common_port_lib.o ++dwc_common_port_lib-objs := dwc_cc.o dwc_modpow.o dwc_dh.o \ ++ dwc_crypto.o dwc_notifier.o \ ++ dwc_common_linux.o dwc_mem.o ++ ++kernrelwd := $(subst ., ,$(KERNELRELEASE)) ++kernrel3 := $(word 1,$(kernrelwd)).$(word 2,$(kernrelwd)).$(word 3,$(kernrelwd)) ++ ++ifneq ($(kernrel3),2.6.20) ++# grayg - I only know that we use ccflags-y in 2.6.31 actually ++ccflags-y += $(CPPFLAGS) ++endif ++ ++else ++ ++#ifeq ($(KDIR),) ++#$(error Must give "KDIR=/path/to/kernel/source" on command line or in environment) ++#endif ++ ++ifeq ($(ARCH),) ++$(error Must give "ARCH=" on command line or in environment. Also, if \ ++ cross-compiling, must give "CROSS_COMPILE=/path/to/compiler/plus/tool-prefix-") ++endif ++ ++ifeq ($(DOXYGEN),) ++DOXYGEN := doxygen ++endif ++ ++default: ++ $(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules ++ ++docs: $(wildcard *.[hc]) doc/doxygen.cfg ++ $(DOXYGEN) doc/doxygen.cfg ++ ++tags: $(wildcard *.[hc]) ++ $(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h) ++ ++endif ++ ++clean: ++ rm -rf *.o *.ko .*.cmd *.mod.c .*.o.d .*.o.tmp modules.order Module.markers Module.symvers .tmp_versions/ +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/Makefile.fbsd linux-rpi/drivers/usb/host/dwc_common_port/Makefile.fbsd +--- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/Makefile.fbsd 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_common_port/Makefile.fbsd 2015-11-29 09:42:39.915098960 +0100 +@@ -0,0 +1,17 @@ ++CFLAGS += -I/sys/i386/compile/GENERIC -I/sys/i386/include -I/usr/include ++CFLAGS += -DDWC_FREEBSD ++CFLAGS += -DDEBUG ++#CFLAGS += -DDWC_DEBUG_REGS ++#CFLAGS += -DDWC_DEBUG_MEMORY ++ ++#CFLAGS += -DDWC_LIBMODULE ++#CFLAGS += -DDWC_CCLIB ++#CFLAGS += -DDWC_CRYPTOLIB ++#CFLAGS += -DDWC_NOTIFYLIB ++#CFLAGS += -DDWC_UTFLIB ++ ++KMOD = dwc_common_port_lib ++SRCS = dwc_cc.c dwc_modpow.c dwc_dh.c dwc_crypto.c dwc_notifier.c \ ++ dwc_common_fbsd.c dwc_mem.c ++ ++.include +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/Makefile.linux linux-rpi/drivers/usb/host/dwc_common_port/Makefile.linux +--- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/Makefile.linux 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_common_port/Makefile.linux 2015-11-29 09:42:39.915098960 +0100 +@@ -0,0 +1,49 @@ ++# ++# Makefile for DWC_common library ++# ++ifneq ($(KERNELRELEASE),) ++ ++ccflags-y += -DDWC_LINUX ++#ccflags-y += -DDEBUG ++#ccflags-y += -DDWC_DEBUG_REGS ++#ccflags-y += -DDWC_DEBUG_MEMORY ++ ++ccflags-y += -DDWC_LIBMODULE ++ccflags-y += -DDWC_CCLIB ++ccflags-y += -DDWC_CRYPTOLIB ++ccflags-y += -DDWC_NOTIFYLIB ++ccflags-y += -DDWC_UTFLIB ++ ++obj-m := dwc_common_port_lib.o ++dwc_common_port_lib-objs := dwc_cc.o dwc_modpow.o dwc_dh.o \ ++ dwc_crypto.o dwc_notifier.o \ ++ dwc_common_linux.o dwc_mem.o ++ ++else ++ ++ifeq ($(KDIR),) ++$(error Must give "KDIR=/path/to/kernel/source" on command line or in environment) ++endif ++ ++ifeq ($(ARCH),) ++$(error Must give "ARCH=" on command line or in environment. Also, if \ ++ cross-compiling, must give "CROSS_COMPILE=/path/to/compiler/plus/tool-prefix-") ++endif ++ ++ifeq ($(DOXYGEN),) ++DOXYGEN := doxygen ++endif ++ ++default: ++ $(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules ++ ++docs: $(wildcard *.[hc]) doc/doxygen.cfg ++ $(DOXYGEN) doc/doxygen.cfg ++ ++tags: $(wildcard *.[hc]) ++ $(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h) ++ ++endif ++ ++clean: ++ rm -rf *.o *.ko .*.cmd *.mod.c .*.o.d .*.o.tmp modules.order Module.markers Module.symvers .tmp_versions/ +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_common_port/usb.h linux-rpi/drivers/usb/host/dwc_common_port/usb.h +--- linux-4.1.13.orig/drivers/usb/host/dwc_common_port/usb.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_common_port/usb.h 2015-11-29 09:42:39.915098960 +0100 +@@ -0,0 +1,946 @@ ++/* ++ * Copyright (c) 1998 The NetBSD Foundation, Inc. ++ * All rights reserved. ++ * ++ * This code is derived from software contributed to The NetBSD Foundation ++ * by Lennart Augustsson (lennart@augustsson.net) at ++ * Carlstedt Research & Technology. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. All advertising materials mentioning features or use of this software ++ * must display the following acknowledgement: ++ * This product includes software developed by the NetBSD ++ * Foundation, Inc. and its contributors. ++ * 4. Neither the name of The NetBSD Foundation nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS ++ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS ++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/* Modified by Synopsys, Inc, 12/12/2007 */ ++ ++ ++#ifndef _USB_H_ ++#define _USB_H_ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++ * The USB records contain some unaligned little-endian word ++ * components. The U[SG]ETW macros take care of both the alignment ++ * and endian problem and should always be used to access non-byte ++ * values. ++ */ ++typedef u_int8_t uByte; ++typedef u_int8_t uWord[2]; ++typedef u_int8_t uDWord[4]; ++ ++#define USETW2(w,h,l) ((w)[0] = (u_int8_t)(l), (w)[1] = (u_int8_t)(h)) ++#define UCONSTW(x) { (x) & 0xff, ((x) >> 8) & 0xff } ++#define UCONSTDW(x) { (x) & 0xff, ((x) >> 8) & 0xff, \ ++ ((x) >> 16) & 0xff, ((x) >> 24) & 0xff } ++ ++#if 1 ++#define UGETW(w) ((w)[0] | ((w)[1] << 8)) ++#define USETW(w,v) ((w)[0] = (u_int8_t)(v), (w)[1] = (u_int8_t)((v) >> 8)) ++#define UGETDW(w) ((w)[0] | ((w)[1] << 8) | ((w)[2] << 16) | ((w)[3] << 24)) ++#define USETDW(w,v) ((w)[0] = (u_int8_t)(v), \ ++ (w)[1] = (u_int8_t)((v) >> 8), \ ++ (w)[2] = (u_int8_t)((v) >> 16), \ ++ (w)[3] = (u_int8_t)((v) >> 24)) ++#else ++/* ++ * On little-endian machines that can handle unanliged accesses ++ * (e.g. i386) these macros can be replaced by the following. ++ */ ++#define UGETW(w) (*(u_int16_t *)(w)) ++#define USETW(w,v) (*(u_int16_t *)(w) = (v)) ++#define UGETDW(w) (*(u_int32_t *)(w)) ++#define USETDW(w,v) (*(u_int32_t *)(w) = (v)) ++#endif ++ ++/* ++ * Macros for accessing UAS IU fields, which are big-endian ++ */ ++#define IUSETW2(w,h,l) ((w)[0] = (u_int8_t)(h), (w)[1] = (u_int8_t)(l)) ++#define IUCONSTW(x) { ((x) >> 8) & 0xff, (x) & 0xff } ++#define IUCONSTDW(x) { ((x) >> 24) & 0xff, ((x) >> 16) & 0xff, \ ++ ((x) >> 8) & 0xff, (x) & 0xff } ++#define IUGETW(w) (((w)[0] << 8) | (w)[1]) ++#define IUSETW(w,v) ((w)[0] = (u_int8_t)((v) >> 8), (w)[1] = (u_int8_t)(v)) ++#define IUGETDW(w) (((w)[0] << 24) | ((w)[1] << 16) | ((w)[2] << 8) | (w)[3]) ++#define IUSETDW(w,v) ((w)[0] = (u_int8_t)((v) >> 24), \ ++ (w)[1] = (u_int8_t)((v) >> 16), \ ++ (w)[2] = (u_int8_t)((v) >> 8), \ ++ (w)[3] = (u_int8_t)(v)) ++ ++#define UPACKED __attribute__((__packed__)) ++ ++typedef struct { ++ uByte bmRequestType; ++ uByte bRequest; ++ uWord wValue; ++ uWord wIndex; ++ uWord wLength; ++} UPACKED usb_device_request_t; ++ ++#define UT_GET_DIR(a) ((a) & 0x80) ++#define UT_WRITE 0x00 ++#define UT_READ 0x80 ++ ++#define UT_GET_TYPE(a) ((a) & 0x60) ++#define UT_STANDARD 0x00 ++#define UT_CLASS 0x20 ++#define UT_VENDOR 0x40 ++ ++#define UT_GET_RECIPIENT(a) ((a) & 0x1f) ++#define UT_DEVICE 0x00 ++#define UT_INTERFACE 0x01 ++#define UT_ENDPOINT 0x02 ++#define UT_OTHER 0x03 ++ ++#define UT_READ_DEVICE (UT_READ | UT_STANDARD | UT_DEVICE) ++#define UT_READ_INTERFACE (UT_READ | UT_STANDARD | UT_INTERFACE) ++#define UT_READ_ENDPOINT (UT_READ | UT_STANDARD | UT_ENDPOINT) ++#define UT_WRITE_DEVICE (UT_WRITE | UT_STANDARD | UT_DEVICE) ++#define UT_WRITE_INTERFACE (UT_WRITE | UT_STANDARD | UT_INTERFACE) ++#define UT_WRITE_ENDPOINT (UT_WRITE | UT_STANDARD | UT_ENDPOINT) ++#define UT_READ_CLASS_DEVICE (UT_READ | UT_CLASS | UT_DEVICE) ++#define UT_READ_CLASS_INTERFACE (UT_READ | UT_CLASS | UT_INTERFACE) ++#define UT_READ_CLASS_OTHER (UT_READ | UT_CLASS | UT_OTHER) ++#define UT_READ_CLASS_ENDPOINT (UT_READ | UT_CLASS | UT_ENDPOINT) ++#define UT_WRITE_CLASS_DEVICE (UT_WRITE | UT_CLASS | UT_DEVICE) ++#define UT_WRITE_CLASS_INTERFACE (UT_WRITE | UT_CLASS | UT_INTERFACE) ++#define UT_WRITE_CLASS_OTHER (UT_WRITE | UT_CLASS | UT_OTHER) ++#define UT_WRITE_CLASS_ENDPOINT (UT_WRITE | UT_CLASS | UT_ENDPOINT) ++#define UT_READ_VENDOR_DEVICE (UT_READ | UT_VENDOR | UT_DEVICE) ++#define UT_READ_VENDOR_INTERFACE (UT_READ | UT_VENDOR | UT_INTERFACE) ++#define UT_READ_VENDOR_OTHER (UT_READ | UT_VENDOR | UT_OTHER) ++#define UT_READ_VENDOR_ENDPOINT (UT_READ | UT_VENDOR | UT_ENDPOINT) ++#define UT_WRITE_VENDOR_DEVICE (UT_WRITE | UT_VENDOR | UT_DEVICE) ++#define UT_WRITE_VENDOR_INTERFACE (UT_WRITE | UT_VENDOR | UT_INTERFACE) ++#define UT_WRITE_VENDOR_OTHER (UT_WRITE | UT_VENDOR | UT_OTHER) ++#define UT_WRITE_VENDOR_ENDPOINT (UT_WRITE | UT_VENDOR | UT_ENDPOINT) ++ ++/* Requests */ ++#define UR_GET_STATUS 0x00 ++#define USTAT_STANDARD_STATUS 0x00 ++#define WUSTAT_WUSB_FEATURE 0x01 ++#define WUSTAT_CHANNEL_INFO 0x02 ++#define WUSTAT_RECEIVED_DATA 0x03 ++#define WUSTAT_MAS_AVAILABILITY 0x04 ++#define WUSTAT_CURRENT_TRANSMIT_POWER 0x05 ++#define UR_CLEAR_FEATURE 0x01 ++#define UR_SET_FEATURE 0x03 ++#define UR_SET_AND_TEST_FEATURE 0x0c ++#define UR_SET_ADDRESS 0x05 ++#define UR_GET_DESCRIPTOR 0x06 ++#define UDESC_DEVICE 0x01 ++#define UDESC_CONFIG 0x02 ++#define UDESC_STRING 0x03 ++#define UDESC_INTERFACE 0x04 ++#define UDESC_ENDPOINT 0x05 ++#define UDESC_SS_USB_COMPANION 0x30 ++#define UDESC_DEVICE_QUALIFIER 0x06 ++#define UDESC_OTHER_SPEED_CONFIGURATION 0x07 ++#define UDESC_INTERFACE_POWER 0x08 ++#define UDESC_OTG 0x09 ++#define WUDESC_SECURITY 0x0c ++#define WUDESC_KEY 0x0d ++#define WUD_GET_KEY_INDEX(_wValue_) ((_wValue_) & 0xf) ++#define WUD_GET_KEY_TYPE(_wValue_) (((_wValue_) & 0x30) >> 4) ++#define WUD_KEY_TYPE_ASSOC 0x01 ++#define WUD_KEY_TYPE_GTK 0x02 ++#define WUD_GET_KEY_ORIGIN(_wValue_) (((_wValue_) & 0x40) >> 6) ++#define WUD_KEY_ORIGIN_HOST 0x00 ++#define WUD_KEY_ORIGIN_DEVICE 0x01 ++#define WUDESC_ENCRYPTION_TYPE 0x0e ++#define WUDESC_BOS 0x0f ++#define WUDESC_DEVICE_CAPABILITY 0x10 ++#define WUDESC_WIRELESS_ENDPOINT_COMPANION 0x11 ++#define UDESC_BOS 0x0f ++#define UDESC_DEVICE_CAPABILITY 0x10 ++#define UDESC_CS_DEVICE 0x21 /* class specific */ ++#define UDESC_CS_CONFIG 0x22 ++#define UDESC_CS_STRING 0x23 ++#define UDESC_CS_INTERFACE 0x24 ++#define UDESC_CS_ENDPOINT 0x25 ++#define UDESC_HUB 0x29 ++#define UR_SET_DESCRIPTOR 0x07 ++#define UR_GET_CONFIG 0x08 ++#define UR_SET_CONFIG 0x09 ++#define UR_GET_INTERFACE 0x0a ++#define UR_SET_INTERFACE 0x0b ++#define UR_SYNCH_FRAME 0x0c ++#define WUR_SET_ENCRYPTION 0x0d ++#define WUR_GET_ENCRYPTION 0x0e ++#define WUR_SET_HANDSHAKE 0x0f ++#define WUR_GET_HANDSHAKE 0x10 ++#define WUR_SET_CONNECTION 0x11 ++#define WUR_SET_SECURITY_DATA 0x12 ++#define WUR_GET_SECURITY_DATA 0x13 ++#define WUR_SET_WUSB_DATA 0x14 ++#define WUDATA_DRPIE_INFO 0x01 ++#define WUDATA_TRANSMIT_DATA 0x02 ++#define WUDATA_TRANSMIT_PARAMS 0x03 ++#define WUDATA_RECEIVE_PARAMS 0x04 ++#define WUDATA_TRANSMIT_POWER 0x05 ++#define WUR_LOOPBACK_DATA_WRITE 0x15 ++#define WUR_LOOPBACK_DATA_READ 0x16 ++#define WUR_SET_INTERFACE_DS 0x17 ++ ++/* Feature numbers */ ++#define UF_ENDPOINT_HALT 0 ++#define UF_DEVICE_REMOTE_WAKEUP 1 ++#define UF_TEST_MODE 2 ++#define UF_DEVICE_B_HNP_ENABLE 3 ++#define UF_DEVICE_A_HNP_SUPPORT 4 ++#define UF_DEVICE_A_ALT_HNP_SUPPORT 5 ++#define WUF_WUSB 3 ++#define WUF_TX_DRPIE 0x0 ++#define WUF_DEV_XMIT_PACKET 0x1 ++#define WUF_COUNT_PACKETS 0x2 ++#define WUF_CAPTURE_PACKETS 0x3 ++#define UF_FUNCTION_SUSPEND 0 ++#define UF_U1_ENABLE 48 ++#define UF_U2_ENABLE 49 ++#define UF_LTM_ENABLE 50 ++ ++/* Class requests from the USB 2.0 hub spec, table 11-15 */ ++#define UCR_CLEAR_HUB_FEATURE (0x2000 | UR_CLEAR_FEATURE) ++#define UCR_CLEAR_PORT_FEATURE (0x2300 | UR_CLEAR_FEATURE) ++#define UCR_GET_HUB_DESCRIPTOR (0xa000 | UR_GET_DESCRIPTOR) ++#define UCR_GET_HUB_STATUS (0xa000 | UR_GET_STATUS) ++#define UCR_GET_PORT_STATUS (0xa300 | UR_GET_STATUS) ++#define UCR_SET_HUB_FEATURE (0x2000 | UR_SET_FEATURE) ++#define UCR_SET_PORT_FEATURE (0x2300 | UR_SET_FEATURE) ++#define UCR_SET_AND_TEST_PORT_FEATURE (0xa300 | UR_SET_AND_TEST_FEATURE) ++ ++#ifdef _MSC_VER ++#include ++#endif ++ ++typedef struct { ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte bDescriptorSubtype; ++} UPACKED usb_descriptor_t; ++ ++typedef struct { ++ uByte bLength; ++ uByte bDescriptorType; ++} UPACKED usb_descriptor_header_t; ++ ++typedef struct { ++ uByte bLength; ++ uByte bDescriptorType; ++ uWord bcdUSB; ++#define UD_USB_2_0 0x0200 ++#define UD_IS_USB2(d) (UGETW((d)->bcdUSB) >= UD_USB_2_0) ++ uByte bDeviceClass; ++ uByte bDeviceSubClass; ++ uByte bDeviceProtocol; ++ uByte bMaxPacketSize; ++ /* The fields below are not part of the initial descriptor. */ ++ uWord idVendor; ++ uWord idProduct; ++ uWord bcdDevice; ++ uByte iManufacturer; ++ uByte iProduct; ++ uByte iSerialNumber; ++ uByte bNumConfigurations; ++} UPACKED usb_device_descriptor_t; ++#define USB_DEVICE_DESCRIPTOR_SIZE 18 ++ ++typedef struct { ++ uByte bLength; ++ uByte bDescriptorType; ++ uWord wTotalLength; ++ uByte bNumInterface; ++ uByte bConfigurationValue; ++ uByte iConfiguration; ++#define UC_ATT_ONE (1 << 7) /* must be set */ ++#define UC_ATT_SELFPOWER (1 << 6) /* self powered */ ++#define UC_ATT_WAKEUP (1 << 5) /* can wakeup */ ++#define UC_ATT_BATTERY (1 << 4) /* battery powered */ ++ uByte bmAttributes; ++#define UC_BUS_POWERED 0x80 ++#define UC_SELF_POWERED 0x40 ++#define UC_REMOTE_WAKEUP 0x20 ++ uByte bMaxPower; /* max current in 2 mA units */ ++#define UC_POWER_FACTOR 2 ++} UPACKED usb_config_descriptor_t; ++#define USB_CONFIG_DESCRIPTOR_SIZE 9 ++ ++typedef struct { ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte bInterfaceNumber; ++ uByte bAlternateSetting; ++ uByte bNumEndpoints; ++ uByte bInterfaceClass; ++ uByte bInterfaceSubClass; ++ uByte bInterfaceProtocol; ++ uByte iInterface; ++} UPACKED usb_interface_descriptor_t; ++#define USB_INTERFACE_DESCRIPTOR_SIZE 9 ++ ++typedef struct { ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte bEndpointAddress; ++#define UE_GET_DIR(a) ((a) & 0x80) ++#define UE_SET_DIR(a,d) ((a) | (((d)&1) << 7)) ++#define UE_DIR_IN 0x80 ++#define UE_DIR_OUT 0x00 ++#define UE_ADDR 0x0f ++#define UE_GET_ADDR(a) ((a) & UE_ADDR) ++ uByte bmAttributes; ++#define UE_XFERTYPE 0x03 ++#define UE_CONTROL 0x00 ++#define UE_ISOCHRONOUS 0x01 ++#define UE_BULK 0x02 ++#define UE_INTERRUPT 0x03 ++#define UE_GET_XFERTYPE(a) ((a) & UE_XFERTYPE) ++#define UE_ISO_TYPE 0x0c ++#define UE_ISO_ASYNC 0x04 ++#define UE_ISO_ADAPT 0x08 ++#define UE_ISO_SYNC 0x0c ++#define UE_GET_ISO_TYPE(a) ((a) & UE_ISO_TYPE) ++ uWord wMaxPacketSize; ++ uByte bInterval; ++} UPACKED usb_endpoint_descriptor_t; ++#define USB_ENDPOINT_DESCRIPTOR_SIZE 7 ++ ++typedef struct ss_endpoint_companion_descriptor { ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte bMaxBurst; ++#define USSE_GET_MAX_STREAMS(a) ((a) & 0x1f) ++#define USSE_SET_MAX_STREAMS(a, b) ((a) | ((b) & 0x1f)) ++#define USSE_GET_MAX_PACKET_NUM(a) ((a) & 0x03) ++#define USSE_SET_MAX_PACKET_NUM(a, b) ((a) | ((b) & 0x03)) ++ uByte bmAttributes; ++ uWord wBytesPerInterval; ++} UPACKED ss_endpoint_companion_descriptor_t; ++#define USB_SS_ENDPOINT_COMPANION_DESCRIPTOR_SIZE 6 ++ ++typedef struct { ++ uByte bLength; ++ uByte bDescriptorType; ++ uWord bString[127]; ++} UPACKED usb_string_descriptor_t; ++#define USB_MAX_STRING_LEN 128 ++#define USB_LANGUAGE_TABLE 0 /* # of the string language id table */ ++ ++/* Hub specific request */ ++#define UR_GET_BUS_STATE 0x02 ++#define UR_CLEAR_TT_BUFFER 0x08 ++#define UR_RESET_TT 0x09 ++#define UR_GET_TT_STATE 0x0a ++#define UR_STOP_TT 0x0b ++ ++/* Hub features */ ++#define UHF_C_HUB_LOCAL_POWER 0 ++#define UHF_C_HUB_OVER_CURRENT 1 ++#define UHF_PORT_CONNECTION 0 ++#define UHF_PORT_ENABLE 1 ++#define UHF_PORT_SUSPEND 2 ++#define UHF_PORT_OVER_CURRENT 3 ++#define UHF_PORT_RESET 4 ++#define UHF_PORT_L1 5 ++#define UHF_PORT_POWER 8 ++#define UHF_PORT_LOW_SPEED 9 ++#define UHF_PORT_HIGH_SPEED 10 ++#define UHF_C_PORT_CONNECTION 16 ++#define UHF_C_PORT_ENABLE 17 ++#define UHF_C_PORT_SUSPEND 18 ++#define UHF_C_PORT_OVER_CURRENT 19 ++#define UHF_C_PORT_RESET 20 ++#define UHF_C_PORT_L1 23 ++#define UHF_PORT_TEST 21 ++#define UHF_PORT_INDICATOR 22 ++ ++typedef struct { ++ uByte bDescLength; ++ uByte bDescriptorType; ++ uByte bNbrPorts; ++ uWord wHubCharacteristics; ++#define UHD_PWR 0x0003 ++#define UHD_PWR_GANGED 0x0000 ++#define UHD_PWR_INDIVIDUAL 0x0001 ++#define UHD_PWR_NO_SWITCH 0x0002 ++#define UHD_COMPOUND 0x0004 ++#define UHD_OC 0x0018 ++#define UHD_OC_GLOBAL 0x0000 ++#define UHD_OC_INDIVIDUAL 0x0008 ++#define UHD_OC_NONE 0x0010 ++#define UHD_TT_THINK 0x0060 ++#define UHD_TT_THINK_8 0x0000 ++#define UHD_TT_THINK_16 0x0020 ++#define UHD_TT_THINK_24 0x0040 ++#define UHD_TT_THINK_32 0x0060 ++#define UHD_PORT_IND 0x0080 ++ uByte bPwrOn2PwrGood; /* delay in 2 ms units */ ++#define UHD_PWRON_FACTOR 2 ++ uByte bHubContrCurrent; ++ uByte DeviceRemovable[32]; /* max 255 ports */ ++#define UHD_NOT_REMOV(desc, i) \ ++ (((desc)->DeviceRemovable[(i)/8] >> ((i) % 8)) & 1) ++ /* deprecated */ uByte PortPowerCtrlMask[1]; ++} UPACKED usb_hub_descriptor_t; ++#define USB_HUB_DESCRIPTOR_SIZE 9 /* includes deprecated PortPowerCtrlMask */ ++ ++typedef struct { ++ uByte bLength; ++ uByte bDescriptorType; ++ uWord bcdUSB; ++ uByte bDeviceClass; ++ uByte bDeviceSubClass; ++ uByte bDeviceProtocol; ++ uByte bMaxPacketSize0; ++ uByte bNumConfigurations; ++ uByte bReserved; ++} UPACKED usb_device_qualifier_t; ++#define USB_DEVICE_QUALIFIER_SIZE 10 ++ ++typedef struct { ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte bmAttributes; ++#define UOTG_SRP 0x01 ++#define UOTG_HNP 0x02 ++} UPACKED usb_otg_descriptor_t; ++ ++/* OTG feature selectors */ ++#define UOTG_B_HNP_ENABLE 3 ++#define UOTG_A_HNP_SUPPORT 4 ++#define UOTG_A_ALT_HNP_SUPPORT 5 ++ ++typedef struct { ++ uWord wStatus; ++/* Device status flags */ ++#define UDS_SELF_POWERED 0x0001 ++#define UDS_REMOTE_WAKEUP 0x0002 ++/* Endpoint status flags */ ++#define UES_HALT 0x0001 ++} UPACKED usb_status_t; ++ ++typedef struct { ++ uWord wHubStatus; ++#define UHS_LOCAL_POWER 0x0001 ++#define UHS_OVER_CURRENT 0x0002 ++ uWord wHubChange; ++} UPACKED usb_hub_status_t; ++ ++typedef struct { ++ uWord wPortStatus; ++#define UPS_CURRENT_CONNECT_STATUS 0x0001 ++#define UPS_PORT_ENABLED 0x0002 ++#define UPS_SUSPEND 0x0004 ++#define UPS_OVERCURRENT_INDICATOR 0x0008 ++#define UPS_RESET 0x0010 ++#define UPS_PORT_POWER 0x0100 ++#define UPS_LOW_SPEED 0x0200 ++#define UPS_HIGH_SPEED 0x0400 ++#define UPS_PORT_TEST 0x0800 ++#define UPS_PORT_INDICATOR 0x1000 ++ uWord wPortChange; ++#define UPS_C_CONNECT_STATUS 0x0001 ++#define UPS_C_PORT_ENABLED 0x0002 ++#define UPS_C_SUSPEND 0x0004 ++#define UPS_C_OVERCURRENT_INDICATOR 0x0008 ++#define UPS_C_PORT_RESET 0x0010 ++} UPACKED usb_port_status_t; ++ ++#ifdef _MSC_VER ++#include ++#endif ++ ++/* Device class codes */ ++#define UDCLASS_IN_INTERFACE 0x00 ++#define UDCLASS_COMM 0x02 ++#define UDCLASS_HUB 0x09 ++#define UDSUBCLASS_HUB 0x00 ++#define UDPROTO_FSHUB 0x00 ++#define UDPROTO_HSHUBSTT 0x01 ++#define UDPROTO_HSHUBMTT 0x02 ++#define UDCLASS_DIAGNOSTIC 0xdc ++#define UDCLASS_WIRELESS 0xe0 ++#define UDSUBCLASS_RF 0x01 ++#define UDPROTO_BLUETOOTH 0x01 ++#define UDCLASS_VENDOR 0xff ++ ++/* Interface class codes */ ++#define UICLASS_UNSPEC 0x00 ++ ++#define UICLASS_AUDIO 0x01 ++#define UISUBCLASS_AUDIOCONTROL 1 ++#define UISUBCLASS_AUDIOSTREAM 2 ++#define UISUBCLASS_MIDISTREAM 3 ++ ++#define UICLASS_CDC 0x02 /* communication */ ++#define UISUBCLASS_DIRECT_LINE_CONTROL_MODEL 1 ++#define UISUBCLASS_ABSTRACT_CONTROL_MODEL 2 ++#define UISUBCLASS_TELEPHONE_CONTROL_MODEL 3 ++#define UISUBCLASS_MULTICHANNEL_CONTROL_MODEL 4 ++#define UISUBCLASS_CAPI_CONTROLMODEL 5 ++#define UISUBCLASS_ETHERNET_NETWORKING_CONTROL_MODEL 6 ++#define UISUBCLASS_ATM_NETWORKING_CONTROL_MODEL 7 ++#define UIPROTO_CDC_AT 1 ++ ++#define UICLASS_HID 0x03 ++#define UISUBCLASS_BOOT 1 ++#define UIPROTO_BOOT_KEYBOARD 1 ++ ++#define UICLASS_PHYSICAL 0x05 ++ ++#define UICLASS_IMAGE 0x06 ++ ++#define UICLASS_PRINTER 0x07 ++#define UISUBCLASS_PRINTER 1 ++#define UIPROTO_PRINTER_UNI 1 ++#define UIPROTO_PRINTER_BI 2 ++#define UIPROTO_PRINTER_1284 3 ++ ++#define UICLASS_MASS 0x08 ++#define UISUBCLASS_RBC 1 ++#define UISUBCLASS_SFF8020I 2 ++#define UISUBCLASS_QIC157 3 ++#define UISUBCLASS_UFI 4 ++#define UISUBCLASS_SFF8070I 5 ++#define UISUBCLASS_SCSI 6 ++#define UIPROTO_MASS_CBI_I 0 ++#define UIPROTO_MASS_CBI 1 ++#define UIPROTO_MASS_BBB_OLD 2 /* Not in the spec anymore */ ++#define UIPROTO_MASS_BBB 80 /* 'P' for the Iomega Zip drive */ ++ ++#define UICLASS_HUB 0x09 ++#define UISUBCLASS_HUB 0 ++#define UIPROTO_FSHUB 0 ++#define UIPROTO_HSHUBSTT 0 /* Yes, same as previous */ ++#define UIPROTO_HSHUBMTT 1 ++ ++#define UICLASS_CDC_DATA 0x0a ++#define UISUBCLASS_DATA 0 ++#define UIPROTO_DATA_ISDNBRI 0x30 /* Physical iface */ ++#define UIPROTO_DATA_HDLC 0x31 /* HDLC */ ++#define UIPROTO_DATA_TRANSPARENT 0x32 /* Transparent */ ++#define UIPROTO_DATA_Q921M 0x50 /* Management for Q921 */ ++#define UIPROTO_DATA_Q921 0x51 /* Data for Q921 */ ++#define UIPROTO_DATA_Q921TM 0x52 /* TEI multiplexer for Q921 */ ++#define UIPROTO_DATA_V42BIS 0x90 /* Data compression */ ++#define UIPROTO_DATA_Q931 0x91 /* Euro-ISDN */ ++#define UIPROTO_DATA_V120 0x92 /* V.24 rate adaption */ ++#define UIPROTO_DATA_CAPI 0x93 /* CAPI 2.0 commands */ ++#define UIPROTO_DATA_HOST_BASED 0xfd /* Host based driver */ ++#define UIPROTO_DATA_PUF 0xfe /* see Prot. Unit Func. Desc.*/ ++#define UIPROTO_DATA_VENDOR 0xff /* Vendor specific */ ++ ++#define UICLASS_SMARTCARD 0x0b ++ ++/*#define UICLASS_FIRM_UPD 0x0c*/ ++ ++#define UICLASS_SECURITY 0x0d ++ ++#define UICLASS_DIAGNOSTIC 0xdc ++ ++#define UICLASS_WIRELESS 0xe0 ++#define UISUBCLASS_RF 0x01 ++#define UIPROTO_BLUETOOTH 0x01 ++ ++#define UICLASS_APPL_SPEC 0xfe ++#define UISUBCLASS_FIRMWARE_DOWNLOAD 1 ++#define UISUBCLASS_IRDA 2 ++#define UIPROTO_IRDA 0 ++ ++#define UICLASS_VENDOR 0xff ++ ++#define USB_HUB_MAX_DEPTH 5 ++ ++/* ++ * Minimum time a device needs to be powered down to go through ++ * a power cycle. XXX Are these time in the spec? ++ */ ++#define USB_POWER_DOWN_TIME 200 /* ms */ ++#define USB_PORT_POWER_DOWN_TIME 100 /* ms */ ++ ++#if 0 ++/* These are the values from the spec. */ ++#define USB_PORT_RESET_DELAY 10 /* ms */ ++#define USB_PORT_ROOT_RESET_DELAY 50 /* ms */ ++#define USB_PORT_RESET_RECOVERY 10 /* ms */ ++#define USB_PORT_POWERUP_DELAY 100 /* ms */ ++#define USB_SET_ADDRESS_SETTLE 2 /* ms */ ++#define USB_RESUME_DELAY (20*5) /* ms */ ++#define USB_RESUME_WAIT 10 /* ms */ ++#define USB_RESUME_RECOVERY 10 /* ms */ ++#define USB_EXTRA_POWER_UP_TIME 0 /* ms */ ++#else ++/* Allow for marginal (i.e. non-conforming) devices. */ ++#define USB_PORT_RESET_DELAY 50 /* ms */ ++#define USB_PORT_ROOT_RESET_DELAY 250 /* ms */ ++#define USB_PORT_RESET_RECOVERY 250 /* ms */ ++#define USB_PORT_POWERUP_DELAY 300 /* ms */ ++#define USB_SET_ADDRESS_SETTLE 10 /* ms */ ++#define USB_RESUME_DELAY (50*5) /* ms */ ++#define USB_RESUME_WAIT 50 /* ms */ ++#define USB_RESUME_RECOVERY 50 /* ms */ ++#define USB_EXTRA_POWER_UP_TIME 20 /* ms */ ++#endif ++ ++#define USB_MIN_POWER 100 /* mA */ ++#define USB_MAX_POWER 500 /* mA */ ++ ++#define USB_BUS_RESET_DELAY 100 /* ms XXX?*/ ++ ++#define USB_UNCONFIG_NO 0 ++#define USB_UNCONFIG_INDEX (-1) ++ ++/*** ioctl() related stuff ***/ ++ ++struct usb_ctl_request { ++ int ucr_addr; ++ usb_device_request_t ucr_request; ++ void *ucr_data; ++ int ucr_flags; ++#define USBD_SHORT_XFER_OK 0x04 /* allow short reads */ ++ int ucr_actlen; /* actual length transferred */ ++}; ++ ++struct usb_alt_interface { ++ int uai_config_index; ++ int uai_interface_index; ++ int uai_alt_no; ++}; ++ ++#define USB_CURRENT_CONFIG_INDEX (-1) ++#define USB_CURRENT_ALT_INDEX (-1) ++ ++struct usb_config_desc { ++ int ucd_config_index; ++ usb_config_descriptor_t ucd_desc; ++}; ++ ++struct usb_interface_desc { ++ int uid_config_index; ++ int uid_interface_index; ++ int uid_alt_index; ++ usb_interface_descriptor_t uid_desc; ++}; ++ ++struct usb_endpoint_desc { ++ int ued_config_index; ++ int ued_interface_index; ++ int ued_alt_index; ++ int ued_endpoint_index; ++ usb_endpoint_descriptor_t ued_desc; ++}; ++ ++struct usb_full_desc { ++ int ufd_config_index; ++ u_int ufd_size; ++ u_char *ufd_data; ++}; ++ ++struct usb_string_desc { ++ int usd_string_index; ++ int usd_language_id; ++ usb_string_descriptor_t usd_desc; ++}; ++ ++struct usb_ctl_report_desc { ++ int ucrd_size; ++ u_char ucrd_data[1024]; /* filled data size will vary */ ++}; ++ ++typedef struct { u_int32_t cookie; } usb_event_cookie_t; ++ ++#define USB_MAX_DEVNAMES 4 ++#define USB_MAX_DEVNAMELEN 16 ++struct usb_device_info { ++ u_int8_t udi_bus; ++ u_int8_t udi_addr; /* device address */ ++ usb_event_cookie_t udi_cookie; ++ char udi_product[USB_MAX_STRING_LEN]; ++ char udi_vendor[USB_MAX_STRING_LEN]; ++ char udi_release[8]; ++ u_int16_t udi_productNo; ++ u_int16_t udi_vendorNo; ++ u_int16_t udi_releaseNo; ++ u_int8_t udi_class; ++ u_int8_t udi_subclass; ++ u_int8_t udi_protocol; ++ u_int8_t udi_config; ++ u_int8_t udi_speed; ++#define USB_SPEED_UNKNOWN 0 ++#define USB_SPEED_LOW 1 ++#define USB_SPEED_FULL 2 ++#define USB_SPEED_HIGH 3 ++#define USB_SPEED_VARIABLE 4 ++#define USB_SPEED_SUPER 5 ++ int udi_power; /* power consumption in mA, 0 if selfpowered */ ++ int udi_nports; ++ char udi_devnames[USB_MAX_DEVNAMES][USB_MAX_DEVNAMELEN]; ++ u_int8_t udi_ports[16];/* hub only: addresses of devices on ports */ ++#define USB_PORT_ENABLED 0xff ++#define USB_PORT_SUSPENDED 0xfe ++#define USB_PORT_POWERED 0xfd ++#define USB_PORT_DISABLED 0xfc ++}; ++ ++struct usb_ctl_report { ++ int ucr_report; ++ u_char ucr_data[1024]; /* filled data size will vary */ ++}; ++ ++struct usb_device_stats { ++ u_long uds_requests[4]; /* indexed by transfer type UE_* */ ++}; ++ ++#define WUSB_MIN_IE 0x80 ++#define WUSB_WCTA_IE 0x80 ++#define WUSB_WCONNECTACK_IE 0x81 ++#define WUSB_WHOSTINFO_IE 0x82 ++#define WUHI_GET_CA(_bmAttributes_) ((_bmAttributes_) & 0x3) ++#define WUHI_CA_RECONN 0x00 ++#define WUHI_CA_LIMITED 0x01 ++#define WUHI_CA_ALL 0x03 ++#define WUHI_GET_MLSI(_bmAttributes_) (((_bmAttributes_) & 0x38) >> 3) ++#define WUSB_WCHCHANGEANNOUNCE_IE 0x83 ++#define WUSB_WDEV_DISCONNECT_IE 0x84 ++#define WUSB_WHOST_DISCONNECT_IE 0x85 ++#define WUSB_WRELEASE_CHANNEL_IE 0x86 ++#define WUSB_WWORK_IE 0x87 ++#define WUSB_WCHANNEL_STOP_IE 0x88 ++#define WUSB_WDEV_KEEPALIVE_IE 0x89 ++#define WUSB_WISOCH_DISCARD_IE 0x8A ++#define WUSB_WRESETDEVICE_IE 0x8B ++#define WUSB_WXMIT_PACKET_ADJUST_IE 0x8C ++#define WUSB_MAX_IE 0x8C ++ ++/* Device Notification Types */ ++ ++#define WUSB_DN_MIN 0x01 ++#define WUSB_DN_CONNECT 0x01 ++# define WUSB_DA_OLDCONN 0x00 ++# define WUSB_DA_NEWCONN 0x01 ++# define WUSB_DA_SELF_BEACON 0x02 ++# define WUSB_DA_DIR_BEACON 0x04 ++# define WUSB_DA_NO_BEACON 0x06 ++#define WUSB_DN_DISCONNECT 0x02 ++#define WUSB_DN_EPRDY 0x03 ++#define WUSB_DN_MASAVAILCHANGED 0x04 ++#define WUSB_DN_REMOTEWAKEUP 0x05 ++#define WUSB_DN_SLEEP 0x06 ++#define WUSB_DN_ALIVE 0x07 ++#define WUSB_DN_MAX 0x07 ++ ++#ifdef _MSC_VER ++#include ++#endif ++ ++/* WUSB Handshake Data. Used during the SET/GET HANDSHAKE requests */ ++typedef struct wusb_hndshk_data { ++ uByte bMessageNumber; ++ uByte bStatus; ++ uByte tTKID[3]; ++ uByte bReserved; ++ uByte CDID[16]; ++ uByte Nonce[16]; ++ uByte MIC[8]; ++} UPACKED wusb_hndshk_data_t; ++#define WUSB_HANDSHAKE_LEN_FOR_MIC 38 ++ ++/* WUSB Connection Context */ ++typedef struct wusb_conn_context { ++ uByte CHID [16]; ++ uByte CDID [16]; ++ uByte CK [16]; ++} UPACKED wusb_conn_context_t; ++ ++/* WUSB Security Descriptor */ ++typedef struct wusb_security_desc { ++ uByte bLength; ++ uByte bDescriptorType; ++ uWord wTotalLength; ++ uByte bNumEncryptionTypes; ++} UPACKED wusb_security_desc_t; ++ ++/* WUSB Encryption Type Descriptor */ ++typedef struct wusb_encrypt_type_desc { ++ uByte bLength; ++ uByte bDescriptorType; ++ ++ uByte bEncryptionType; ++#define WUETD_UNSECURE 0 ++#define WUETD_WIRED 1 ++#define WUETD_CCM_1 2 ++#define WUETD_RSA_1 3 ++ ++ uByte bEncryptionValue; ++ uByte bAuthKeyIndex; ++} UPACKED wusb_encrypt_type_desc_t; ++ ++/* WUSB Key Descriptor */ ++typedef struct wusb_key_desc { ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte tTKID[3]; ++ uByte bReserved; ++ uByte KeyData[1]; /* variable length */ ++} UPACKED wusb_key_desc_t; ++ ++/* WUSB BOS Descriptor (Binary device Object Store) */ ++typedef struct wusb_bos_desc { ++ uByte bLength; ++ uByte bDescriptorType; ++ uWord wTotalLength; ++ uByte bNumDeviceCaps; ++} UPACKED wusb_bos_desc_t; ++ ++#define USB_DEVICE_CAPABILITY_20_EXTENSION 0x02 ++typedef struct usb_dev_cap_20_ext_desc { ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte bDevCapabilityType; ++#define USB_20_EXT_LPM 0x02 ++ uDWord bmAttributes; ++} UPACKED usb_dev_cap_20_ext_desc_t; ++ ++#define USB_DEVICE_CAPABILITY_SS_USB 0x03 ++typedef struct usb_dev_cap_ss_usb { ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte bDevCapabilityType; ++#define USB_DC_SS_USB_LTM_CAPABLE 0x02 ++ uByte bmAttributes; ++#define USB_DC_SS_USB_SPEED_SUPPORT_LOW 0x01 ++#define USB_DC_SS_USB_SPEED_SUPPORT_FULL 0x02 ++#define USB_DC_SS_USB_SPEED_SUPPORT_HIGH 0x04 ++#define USB_DC_SS_USB_SPEED_SUPPORT_SS 0x08 ++ uWord wSpeedsSupported; ++ uByte bFunctionalitySupport; ++ uByte bU1DevExitLat; ++ uWord wU2DevExitLat; ++} UPACKED usb_dev_cap_ss_usb_t; ++ ++#define USB_DEVICE_CAPABILITY_CONTAINER_ID 0x04 ++typedef struct usb_dev_cap_container_id { ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte bDevCapabilityType; ++ uByte bReserved; ++ uByte containerID[16]; ++} UPACKED usb_dev_cap_container_id_t; ++ ++/* Device Capability Type Codes */ ++#define WUSB_DEVICE_CAPABILITY_WIRELESS_USB 0x01 ++ ++/* Device Capability Descriptor */ ++typedef struct wusb_dev_cap_desc { ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte bDevCapabilityType; ++ uByte caps[1]; /* Variable length */ ++} UPACKED wusb_dev_cap_desc_t; ++ ++/* Device Capability Descriptor */ ++typedef struct wusb_dev_cap_uwb_desc { ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte bDevCapabilityType; ++ uByte bmAttributes; ++ uWord wPHYRates; /* Bitmap */ ++ uByte bmTFITXPowerInfo; ++ uByte bmFFITXPowerInfo; ++ uWord bmBandGroup; ++ uByte bReserved; ++} UPACKED wusb_dev_cap_uwb_desc_t; ++ ++/* Wireless USB Endpoint Companion Descriptor */ ++typedef struct wusb_endpoint_companion_desc { ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte bMaxBurst; ++ uByte bMaxSequence; ++ uWord wMaxStreamDelay; ++ uWord wOverTheAirPacketSize; ++ uByte bOverTheAirInterval; ++ uByte bmCompAttributes; ++} UPACKED wusb_endpoint_companion_desc_t; ++ ++/* Wireless USB Numeric Association M1 Data Structure */ ++typedef struct wusb_m1_data { ++ uByte version; ++ uWord langId; ++ uByte deviceFriendlyNameLength; ++ uByte sha_256_m3[32]; ++ uByte deviceFriendlyName[256]; ++} UPACKED wusb_m1_data_t; ++ ++typedef struct wusb_m2_data { ++ uByte version; ++ uWord langId; ++ uByte hostFriendlyNameLength; ++ uByte pkh[384]; ++ uByte hostFriendlyName[256]; ++} UPACKED wusb_m2_data_t; ++ ++typedef struct wusb_m3_data { ++ uByte pkd[384]; ++ uByte nd; ++} UPACKED wusb_m3_data_t; ++ ++typedef struct wusb_m4_data { ++ uDWord _attributeTypeIdAndLength_1; ++ uWord associationTypeId; ++ ++ uDWord _attributeTypeIdAndLength_2; ++ uWord associationSubTypeId; ++ ++ uDWord _attributeTypeIdAndLength_3; ++ uDWord length; ++ ++ uDWord _attributeTypeIdAndLength_4; ++ uDWord associationStatus; ++ ++ uDWord _attributeTypeIdAndLength_5; ++ uByte chid[16]; ++ ++ uDWord _attributeTypeIdAndLength_6; ++ uByte cdid[16]; ++ ++ uDWord _attributeTypeIdAndLength_7; ++ uByte bandGroups[2]; ++} UPACKED wusb_m4_data_t; ++ ++#ifdef _MSC_VER ++#include ++#endif ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif /* _USB_H_ */ +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/doc/doxygen.cfg linux-rpi/drivers/usb/host/dwc_otg/doc/doxygen.cfg +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/doc/doxygen.cfg 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/doc/doxygen.cfg 2015-11-29 09:42:39.915098960 +0100 +@@ -0,0 +1,224 @@ ++# Doxyfile 1.3.9.1 ++ ++#--------------------------------------------------------------------------- ++# Project related configuration options ++#--------------------------------------------------------------------------- ++PROJECT_NAME = "DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver" ++PROJECT_NUMBER = v3.00a ++OUTPUT_DIRECTORY = ./doc/ ++CREATE_SUBDIRS = NO ++OUTPUT_LANGUAGE = English ++BRIEF_MEMBER_DESC = YES ++REPEAT_BRIEF = YES ++ABBREVIATE_BRIEF = "The $name class" \ ++ "The $name widget" \ ++ "The $name file" \ ++ is \ ++ provides \ ++ specifies \ ++ contains \ ++ represents \ ++ a \ ++ an \ ++ the ++ALWAYS_DETAILED_SEC = NO ++INLINE_INHERITED_MEMB = NO ++FULL_PATH_NAMES = NO ++STRIP_FROM_PATH = ++STRIP_FROM_INC_PATH = ++SHORT_NAMES = NO ++JAVADOC_AUTOBRIEF = YES ++MULTILINE_CPP_IS_BRIEF = NO ++INHERIT_DOCS = YES ++DISTRIBUTE_GROUP_DOC = NO ++TAB_SIZE = 8 ++ALIASES = ++OPTIMIZE_OUTPUT_FOR_C = YES ++OPTIMIZE_OUTPUT_JAVA = NO ++SUBGROUPING = YES ++#--------------------------------------------------------------------------- ++# Build related configuration options ++#--------------------------------------------------------------------------- ++EXTRACT_ALL = NO ++EXTRACT_PRIVATE = YES ++EXTRACT_STATIC = YES ++EXTRACT_LOCAL_CLASSES = YES ++EXTRACT_LOCAL_METHODS = NO ++HIDE_UNDOC_MEMBERS = NO ++HIDE_UNDOC_CLASSES = NO ++HIDE_FRIEND_COMPOUNDS = NO ++HIDE_IN_BODY_DOCS = NO ++INTERNAL_DOCS = NO ++CASE_SENSE_NAMES = NO ++HIDE_SCOPE_NAMES = NO ++SHOW_INCLUDE_FILES = YES ++INLINE_INFO = YES ++SORT_MEMBER_DOCS = NO ++SORT_BRIEF_DOCS = NO ++SORT_BY_SCOPE_NAME = NO ++GENERATE_TODOLIST = YES ++GENERATE_TESTLIST = YES ++GENERATE_BUGLIST = YES ++GENERATE_DEPRECATEDLIST= YES ++ENABLED_SECTIONS = ++MAX_INITIALIZER_LINES = 30 ++SHOW_USED_FILES = YES ++SHOW_DIRECTORIES = YES ++#--------------------------------------------------------------------------- ++# configuration options related to warning and progress messages ++#--------------------------------------------------------------------------- ++QUIET = YES ++WARNINGS = YES ++WARN_IF_UNDOCUMENTED = NO ++WARN_IF_DOC_ERROR = YES ++WARN_FORMAT = "$file:$line: $text" ++WARN_LOGFILE = ++#--------------------------------------------------------------------------- ++# configuration options related to the input files ++#--------------------------------------------------------------------------- ++INPUT = . ++FILE_PATTERNS = *.c \ ++ *.h \ ++ ./linux/*.c \ ++ ./linux/*.h ++RECURSIVE = NO ++EXCLUDE = ./test/ \ ++ ./dwc_otg/.AppleDouble/ ++EXCLUDE_SYMLINKS = YES ++EXCLUDE_PATTERNS = *.mod.* ++EXAMPLE_PATH = ++EXAMPLE_PATTERNS = * ++EXAMPLE_RECURSIVE = NO ++IMAGE_PATH = ++INPUT_FILTER = ++FILTER_PATTERNS = ++FILTER_SOURCE_FILES = NO ++#--------------------------------------------------------------------------- ++# configuration options related to source browsing ++#--------------------------------------------------------------------------- ++SOURCE_BROWSER = YES ++INLINE_SOURCES = NO ++STRIP_CODE_COMMENTS = YES ++REFERENCED_BY_RELATION = NO ++REFERENCES_RELATION = NO ++VERBATIM_HEADERS = NO ++#--------------------------------------------------------------------------- ++# configuration options related to the alphabetical class index ++#--------------------------------------------------------------------------- ++ALPHABETICAL_INDEX = NO ++COLS_IN_ALPHA_INDEX = 5 ++IGNORE_PREFIX = ++#--------------------------------------------------------------------------- ++# configuration options related to the HTML output ++#--------------------------------------------------------------------------- ++GENERATE_HTML = YES ++HTML_OUTPUT = html ++HTML_FILE_EXTENSION = .html ++HTML_HEADER = ++HTML_FOOTER = ++HTML_STYLESHEET = ++HTML_ALIGN_MEMBERS = YES ++GENERATE_HTMLHELP = NO ++CHM_FILE = ++HHC_LOCATION = ++GENERATE_CHI = NO ++BINARY_TOC = NO ++TOC_EXPAND = NO ++DISABLE_INDEX = NO ++ENUM_VALUES_PER_LINE = 4 ++GENERATE_TREEVIEW = YES ++TREEVIEW_WIDTH = 250 ++#--------------------------------------------------------------------------- ++# configuration options related to the LaTeX output ++#--------------------------------------------------------------------------- ++GENERATE_LATEX = NO ++LATEX_OUTPUT = latex ++LATEX_CMD_NAME = latex ++MAKEINDEX_CMD_NAME = makeindex ++COMPACT_LATEX = NO ++PAPER_TYPE = a4wide ++EXTRA_PACKAGES = ++LATEX_HEADER = ++PDF_HYPERLINKS = NO ++USE_PDFLATEX = NO ++LATEX_BATCHMODE = NO ++LATEX_HIDE_INDICES = NO ++#--------------------------------------------------------------------------- ++# configuration options related to the RTF output ++#--------------------------------------------------------------------------- ++GENERATE_RTF = NO ++RTF_OUTPUT = rtf ++COMPACT_RTF = NO ++RTF_HYPERLINKS = NO ++RTF_STYLESHEET_FILE = ++RTF_EXTENSIONS_FILE = ++#--------------------------------------------------------------------------- ++# configuration options related to the man page output ++#--------------------------------------------------------------------------- ++GENERATE_MAN = NO ++MAN_OUTPUT = man ++MAN_EXTENSION = .3 ++MAN_LINKS = NO ++#--------------------------------------------------------------------------- ++# configuration options related to the XML output ++#--------------------------------------------------------------------------- ++GENERATE_XML = NO ++XML_OUTPUT = xml ++XML_SCHEMA = ++XML_DTD = ++XML_PROGRAMLISTING = YES ++#--------------------------------------------------------------------------- ++# configuration options for the AutoGen Definitions output ++#--------------------------------------------------------------------------- ++GENERATE_AUTOGEN_DEF = NO ++#--------------------------------------------------------------------------- ++# configuration options related to the Perl module output ++#--------------------------------------------------------------------------- ++GENERATE_PERLMOD = NO ++PERLMOD_LATEX = NO ++PERLMOD_PRETTY = YES ++PERLMOD_MAKEVAR_PREFIX = ++#--------------------------------------------------------------------------- ++# Configuration options related to the preprocessor ++#--------------------------------------------------------------------------- ++ENABLE_PREPROCESSING = YES ++MACRO_EXPANSION = YES ++EXPAND_ONLY_PREDEF = YES ++SEARCH_INCLUDES = YES ++INCLUDE_PATH = ++INCLUDE_FILE_PATTERNS = ++PREDEFINED = DEVICE_ATTR DWC_EN_ISOC ++EXPAND_AS_DEFINED = DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW DWC_OTG_DEVICE_ATTR_BITFIELD_STORE DWC_OTG_DEVICE_ATTR_BITFIELD_RW DWC_OTG_DEVICE_ATTR_BITFIELD_RO DWC_OTG_DEVICE_ATTR_REG_SHOW DWC_OTG_DEVICE_ATTR_REG_STORE DWC_OTG_DEVICE_ATTR_REG32_RW DWC_OTG_DEVICE_ATTR_REG32_RO DWC_EN_ISOC ++SKIP_FUNCTION_MACROS = NO ++#--------------------------------------------------------------------------- ++# Configuration::additions related to external references ++#--------------------------------------------------------------------------- ++TAGFILES = ++GENERATE_TAGFILE = ++ALLEXTERNALS = NO ++EXTERNAL_GROUPS = YES ++PERL_PATH = /usr/bin/perl ++#--------------------------------------------------------------------------- ++# Configuration options related to the dot tool ++#--------------------------------------------------------------------------- ++CLASS_DIAGRAMS = YES ++HIDE_UNDOC_RELATIONS = YES ++HAVE_DOT = NO ++CLASS_GRAPH = YES ++COLLABORATION_GRAPH = YES ++UML_LOOK = NO ++TEMPLATE_RELATIONS = NO ++INCLUDE_GRAPH = YES ++INCLUDED_BY_GRAPH = YES ++CALL_GRAPH = NO ++GRAPHICAL_HIERARCHY = YES ++DOT_IMAGE_FORMAT = png ++DOT_PATH = ++DOTFILE_DIRS = ++MAX_DOT_GRAPH_DEPTH = 1000 ++GENERATE_LEGEND = YES ++DOT_CLEANUP = YES ++#--------------------------------------------------------------------------- ++# Configuration::additions related to the search engine ++#--------------------------------------------------------------------------- ++SEARCHENGINE = NO +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dummy_audio.c linux-rpi/drivers/usb/host/dwc_otg/dummy_audio.c +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dummy_audio.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/dummy_audio.c 2015-11-29 09:42:39.915098960 +0100 +@@ -0,0 +1,1575 @@ ++/* ++ * zero.c -- Gadget Zero, for USB development ++ * ++ * Copyright (C) 2003-2004 David Brownell ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") as published by the Free Software ++ * Foundation, either version 2 of that License or (at your option) any ++ * later version. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++ ++/* ++ * Gadget Zero only needs two bulk endpoints, and is an example of how you ++ * can write a hardware-agnostic gadget driver running inside a USB device. ++ * ++ * Hardware details are visible (see CONFIG_USB_ZERO_* below) but don't ++ * affect most of the driver. ++ * ++ * Use it with the Linux host/master side "usbtest" driver to get a basic ++ * functional test of your device-side usb stack, or with "usb-skeleton". ++ * ++ * It supports two similar configurations. One sinks whatever the usb host ++ * writes, and in return sources zeroes. The other loops whatever the host ++ * writes back, so the host can read it. Module options include: ++ * ++ * buflen=N default N=4096, buffer size used ++ * qlen=N default N=32, how many buffers in the loopback queue ++ * loopdefault default false, list loopback config first ++ * ++ * Many drivers will only have one configuration, letting them be much ++ * simpler if they also don't support high speed operation (like this ++ * driver does). ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21) ++# include ++#else ++# include ++#endif ++ ++#include ++ ++ ++/*-------------------------------------------------------------------------*/ ++/*-------------------------------------------------------------------------*/ ++ ++ ++static int utf8_to_utf16le(const char *s, u16 *cp, unsigned len) ++{ ++ int count = 0; ++ u8 c; ++ u16 uchar; ++ ++ /* this insists on correct encodings, though not minimal ones. ++ * BUT it currently rejects legit 4-byte UTF-8 code points, ++ * which need surrogate pairs. (Unicode 3.1 can use them.) ++ */ ++ while (len != 0 && (c = (u8) *s++) != 0) { ++ if (unlikely(c & 0x80)) { ++ // 2-byte sequence: ++ // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx ++ if ((c & 0xe0) == 0xc0) { ++ uchar = (c & 0x1f) << 6; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c; ++ ++ // 3-byte sequence (most CJKV characters): ++ // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx ++ } else if ((c & 0xf0) == 0xe0) { ++ uchar = (c & 0x0f) << 12; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c << 6; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c; ++ ++ /* no bogus surrogates */ ++ if (0xd800 <= uchar && uchar <= 0xdfff) ++ goto fail; ++ ++ // 4-byte sequence (surrogate pairs, currently rare): ++ // 11101110wwwwzzzzyy + 110111yyyyxxxxxx ++ // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx ++ // (uuuuu = wwww + 1) ++ // FIXME accept the surrogate code points (only) ++ ++ } else ++ goto fail; ++ } else ++ uchar = c; ++ put_unaligned (cpu_to_le16 (uchar), cp++); ++ count++; ++ len--; ++ } ++ return count; ++fail: ++ return -1; ++} ++ ++ ++/** ++ * usb_gadget_get_string - fill out a string descriptor ++ * @table: of c strings encoded using UTF-8 ++ * @id: string id, from low byte of wValue in get string descriptor ++ * @buf: at least 256 bytes ++ * ++ * Finds the UTF-8 string matching the ID, and converts it into a ++ * string descriptor in utf16-le. ++ * Returns length of descriptor (always even) or negative errno ++ * ++ * If your driver needs stings in multiple languages, you'll probably ++ * "switch (wIndex) { ... }" in your ep0 string descriptor logic, ++ * using this routine after choosing which set of UTF-8 strings to use. ++ * Note that US-ASCII is a strict subset of UTF-8; any string bytes with ++ * the eighth bit set will be multibyte UTF-8 characters, not ISO-8859/1 ++ * characters (which are also widely used in C strings). ++ */ ++int ++usb_gadget_get_string (struct usb_gadget_strings *table, int id, u8 *buf) ++{ ++ struct usb_string *s; ++ int len; ++ ++ /* descriptor 0 has the language id */ ++ if (id == 0) { ++ buf [0] = 4; ++ buf [1] = USB_DT_STRING; ++ buf [2] = (u8) table->language; ++ buf [3] = (u8) (table->language >> 8); ++ return 4; ++ } ++ for (s = table->strings; s && s->s; s++) ++ if (s->id == id) ++ break; ++ ++ /* unrecognized: stall. */ ++ if (!s || !s->s) ++ return -EINVAL; ++ ++ /* string descriptors have length, tag, then UTF16-LE text */ ++ len = min ((size_t) 126, strlen (s->s)); ++ memset (buf + 2, 0, 2 * len); /* zero all the bytes */ ++ len = utf8_to_utf16le(s->s, (u16 *)&buf[2], len); ++ if (len < 0) ++ return -EINVAL; ++ buf [0] = (len + 1) * 2; ++ buf [1] = USB_DT_STRING; ++ return buf [0]; ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++/*-------------------------------------------------------------------------*/ ++ ++ ++/** ++ * usb_descriptor_fillbuf - fill buffer with descriptors ++ * @buf: Buffer to be filled ++ * @buflen: Size of buf ++ * @src: Array of descriptor pointers, terminated by null pointer. ++ * ++ * Copies descriptors into the buffer, returning the length or a ++ * negative error code if they can't all be copied. Useful when ++ * assembling descriptors for an associated set of interfaces used ++ * as part of configuring a composite device; or in other cases where ++ * sets of descriptors need to be marshaled. ++ */ ++int ++usb_descriptor_fillbuf(void *buf, unsigned buflen, ++ const struct usb_descriptor_header **src) ++{ ++ u8 *dest = buf; ++ ++ if (!src) ++ return -EINVAL; ++ ++ /* fill buffer from src[] until null descriptor ptr */ ++ for (; 0 != *src; src++) { ++ unsigned len = (*src)->bLength; ++ ++ if (len > buflen) ++ return -EINVAL; ++ memcpy(dest, *src, len); ++ buflen -= len; ++ dest += len; ++ } ++ return dest - (u8 *)buf; ++} ++ ++ ++/** ++ * usb_gadget_config_buf - builts a complete configuration descriptor ++ * @config: Header for the descriptor, including characteristics such ++ * as power requirements and number of interfaces. ++ * @desc: Null-terminated vector of pointers to the descriptors (interface, ++ * endpoint, etc) defining all functions in this device configuration. ++ * @buf: Buffer for the resulting configuration descriptor. ++ * @length: Length of buffer. If this is not big enough to hold the ++ * entire configuration descriptor, an error code will be returned. ++ * ++ * This copies descriptors into the response buffer, building a descriptor ++ * for that configuration. It returns the buffer length or a negative ++ * status code. The config.wTotalLength field is set to match the length ++ * of the result, but other descriptor fields (including power usage and ++ * interface count) must be set by the caller. ++ * ++ * Gadget drivers could use this when constructing a config descriptor ++ * in response to USB_REQ_GET_DESCRIPTOR. They will need to patch the ++ * resulting bDescriptorType value if USB_DT_OTHER_SPEED_CONFIG is needed. ++ */ ++int usb_gadget_config_buf( ++ const struct usb_config_descriptor *config, ++ void *buf, ++ unsigned length, ++ const struct usb_descriptor_header **desc ++) ++{ ++ struct usb_config_descriptor *cp = buf; ++ int len; ++ ++ /* config descriptor first */ ++ if (length < USB_DT_CONFIG_SIZE || !desc) ++ return -EINVAL; ++ *cp = *config; ++ ++ /* then interface/endpoint/class/vendor/... */ ++ len = usb_descriptor_fillbuf(USB_DT_CONFIG_SIZE + (u8*)buf, ++ length - USB_DT_CONFIG_SIZE, desc); ++ if (len < 0) ++ return len; ++ len += USB_DT_CONFIG_SIZE; ++ if (len > 0xffff) ++ return -EINVAL; ++ ++ /* patch up the config descriptor */ ++ cp->bLength = USB_DT_CONFIG_SIZE; ++ cp->bDescriptorType = USB_DT_CONFIG; ++ cp->wTotalLength = cpu_to_le16(len); ++ cp->bmAttributes |= USB_CONFIG_ATT_ONE; ++ return len; ++} ++ ++/*-------------------------------------------------------------------------*/ ++/*-------------------------------------------------------------------------*/ ++ ++ ++#define RBUF_LEN (1024*1024) ++static int rbuf_start; ++static int rbuf_len; ++static __u8 rbuf[RBUF_LEN]; ++ ++/*-------------------------------------------------------------------------*/ ++ ++#define DRIVER_VERSION "St Patrick's Day 2004" ++ ++static const char shortname [] = "zero"; ++static const char longname [] = "YAMAHA YST-MS35D USB Speaker "; ++ ++static const char source_sink [] = "source and sink data"; ++static const char loopback [] = "loop input to output"; ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* ++ * driver assumes self-powered hardware, and ++ * has no way for users to trigger remote wakeup. ++ * ++ * this version autoconfigures as much as possible, ++ * which is reasonable for most "bulk-only" drivers. ++ */ ++static const char *EP_IN_NAME; /* source */ ++static const char *EP_OUT_NAME; /* sink */ ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* big enough to hold our biggest descriptor */ ++#define USB_BUFSIZ 512 ++ ++struct zero_dev { ++ spinlock_t lock; ++ struct usb_gadget *gadget; ++ struct usb_request *req; /* for control responses */ ++ ++ /* when configured, we have one of two configs: ++ * - source data (in to host) and sink it (out from host) ++ * - or loop it back (out from host back in to host) ++ */ ++ u8 config; ++ struct usb_ep *in_ep, *out_ep; ++ ++ /* autoresume timer */ ++ struct timer_list resume; ++}; ++ ++#define xprintk(d,level,fmt,args...) \ ++ dev_printk(level , &(d)->gadget->dev , fmt , ## args) ++ ++#ifdef DEBUG ++#define DBG(dev,fmt,args...) \ ++ xprintk(dev , KERN_DEBUG , fmt , ## args) ++#else ++#define DBG(dev,fmt,args...) \ ++ do { } while (0) ++#endif /* DEBUG */ ++ ++#ifdef VERBOSE ++#define VDBG DBG ++#else ++#define VDBG(dev,fmt,args...) \ ++ do { } while (0) ++#endif /* VERBOSE */ ++ ++#define ERROR(dev,fmt,args...) \ ++ xprintk(dev , KERN_ERR , fmt , ## args) ++#define WARN(dev,fmt,args...) \ ++ xprintk(dev , KERN_WARNING , fmt , ## args) ++#define INFO(dev,fmt,args...) \ ++ xprintk(dev , KERN_INFO , fmt , ## args) ++ ++/*-------------------------------------------------------------------------*/ ++ ++static unsigned buflen = 4096; ++static unsigned qlen = 32; ++static unsigned pattern = 0; ++ ++module_param (buflen, uint, S_IRUGO|S_IWUSR); ++module_param (qlen, uint, S_IRUGO|S_IWUSR); ++module_param (pattern, uint, S_IRUGO|S_IWUSR); ++ ++/* ++ * if it's nonzero, autoresume says how many seconds to wait ++ * before trying to wake up the host after suspend. ++ */ ++static unsigned autoresume = 0; ++module_param (autoresume, uint, 0); ++ ++/* ++ * Normally the "loopback" configuration is second (index 1) so ++ * it's not the default. Here's where to change that order, to ++ * work better with hosts where config changes are problematic. ++ * Or controllers (like superh) that only support one config. ++ */ ++static int loopdefault = 0; ++ ++module_param (loopdefault, bool, S_IRUGO|S_IWUSR); ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* Thanks to NetChip Technologies for donating this product ID. ++ * ++ * DO NOT REUSE THESE IDs with a protocol-incompatible driver!! Ever!! ++ * Instead: allocate your own, using normal USB-IF procedures. ++ */ ++#ifndef CONFIG_USB_ZERO_HNPTEST ++#define DRIVER_VENDOR_NUM 0x0525 /* NetChip */ ++#define DRIVER_PRODUCT_NUM 0xa4a0 /* Linux-USB "Gadget Zero" */ ++#else ++#define DRIVER_VENDOR_NUM 0x1a0a /* OTG test device IDs */ ++#define DRIVER_PRODUCT_NUM 0xbadd ++#endif ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* ++ * DESCRIPTORS ... most are static, but strings and (full) ++ * configuration descriptors are built on demand. ++ */ ++ ++/* ++#define STRING_MANUFACTURER 25 ++#define STRING_PRODUCT 42 ++#define STRING_SERIAL 101 ++*/ ++#define STRING_MANUFACTURER 1 ++#define STRING_PRODUCT 2 ++#define STRING_SERIAL 3 ++ ++#define STRING_SOURCE_SINK 250 ++#define STRING_LOOPBACK 251 ++ ++/* ++ * This device advertises two configurations; these numbers work ++ * on a pxa250 as well as more flexible hardware. ++ */ ++#define CONFIG_SOURCE_SINK 3 ++#define CONFIG_LOOPBACK 2 ++ ++/* ++static struct usb_device_descriptor ++device_desc = { ++ .bLength = sizeof device_desc, ++ .bDescriptorType = USB_DT_DEVICE, ++ ++ .bcdUSB = __constant_cpu_to_le16 (0x0200), ++ .bDeviceClass = USB_CLASS_VENDOR_SPEC, ++ ++ .idVendor = __constant_cpu_to_le16 (DRIVER_VENDOR_NUM), ++ .idProduct = __constant_cpu_to_le16 (DRIVER_PRODUCT_NUM), ++ .iManufacturer = STRING_MANUFACTURER, ++ .iProduct = STRING_PRODUCT, ++ .iSerialNumber = STRING_SERIAL, ++ .bNumConfigurations = 2, ++}; ++*/ ++static struct usb_device_descriptor ++device_desc = { ++ .bLength = sizeof device_desc, ++ .bDescriptorType = USB_DT_DEVICE, ++ .bcdUSB = __constant_cpu_to_le16 (0x0100), ++ .bDeviceClass = USB_CLASS_PER_INTERFACE, ++ .bDeviceSubClass = 0, ++ .bDeviceProtocol = 0, ++ .bMaxPacketSize0 = 64, ++ .bcdDevice = __constant_cpu_to_le16 (0x0100), ++ .idVendor = __constant_cpu_to_le16 (0x0499), ++ .idProduct = __constant_cpu_to_le16 (0x3002), ++ .iManufacturer = STRING_MANUFACTURER, ++ .iProduct = STRING_PRODUCT, ++ .iSerialNumber = STRING_SERIAL, ++ .bNumConfigurations = 1, ++}; ++ ++static struct usb_config_descriptor ++z_config = { ++ .bLength = sizeof z_config, ++ .bDescriptorType = USB_DT_CONFIG, ++ ++ /* compute wTotalLength on the fly */ ++ .bNumInterfaces = 2, ++ .bConfigurationValue = 1, ++ .iConfiguration = 0, ++ .bmAttributes = 0x40, ++ .bMaxPower = 0, /* self-powered */ ++}; ++ ++ ++static struct usb_otg_descriptor ++otg_descriptor = { ++ .bLength = sizeof otg_descriptor, ++ .bDescriptorType = USB_DT_OTG, ++ ++ .bmAttributes = USB_OTG_SRP, ++}; ++ ++/* one interface in each configuration */ ++#ifdef CONFIG_USB_GADGET_DUALSPEED ++ ++/* ++ * usb 2.0 devices need to expose both high speed and full speed ++ * descriptors, unless they only run at full speed. ++ * ++ * that means alternate endpoint descriptors (bigger packets) ++ * and a "device qualifier" ... plus more construction options ++ * for the config descriptor. ++ */ ++ ++static struct usb_qualifier_descriptor ++dev_qualifier = { ++ .bLength = sizeof dev_qualifier, ++ .bDescriptorType = USB_DT_DEVICE_QUALIFIER, ++ ++ .bcdUSB = __constant_cpu_to_le16 (0x0200), ++ .bDeviceClass = USB_CLASS_VENDOR_SPEC, ++ ++ .bNumConfigurations = 2, ++}; ++ ++ ++struct usb_cs_as_general_descriptor { ++ __u8 bLength; ++ __u8 bDescriptorType; ++ ++ __u8 bDescriptorSubType; ++ __u8 bTerminalLink; ++ __u8 bDelay; ++ __u16 wFormatTag; ++} __attribute__ ((packed)); ++ ++struct usb_cs_as_format_descriptor { ++ __u8 bLength; ++ __u8 bDescriptorType; ++ ++ __u8 bDescriptorSubType; ++ __u8 bFormatType; ++ __u8 bNrChannels; ++ __u8 bSubframeSize; ++ __u8 bBitResolution; ++ __u8 bSamfreqType; ++ __u8 tLowerSamFreq[3]; ++ __u8 tUpperSamFreq[3]; ++} __attribute__ ((packed)); ++ ++static const struct usb_interface_descriptor ++z_audio_control_if_desc = { ++ .bLength = sizeof z_audio_control_if_desc, ++ .bDescriptorType = USB_DT_INTERFACE, ++ .bInterfaceNumber = 0, ++ .bAlternateSetting = 0, ++ .bNumEndpoints = 0, ++ .bInterfaceClass = USB_CLASS_AUDIO, ++ .bInterfaceSubClass = 0x1, ++ .bInterfaceProtocol = 0, ++ .iInterface = 0, ++}; ++ ++static const struct usb_interface_descriptor ++z_audio_if_desc = { ++ .bLength = sizeof z_audio_if_desc, ++ .bDescriptorType = USB_DT_INTERFACE, ++ .bInterfaceNumber = 1, ++ .bAlternateSetting = 0, ++ .bNumEndpoints = 0, ++ .bInterfaceClass = USB_CLASS_AUDIO, ++ .bInterfaceSubClass = 0x2, ++ .bInterfaceProtocol = 0, ++ .iInterface = 0, ++}; ++ ++static const struct usb_interface_descriptor ++z_audio_if_desc2 = { ++ .bLength = sizeof z_audio_if_desc, ++ .bDescriptorType = USB_DT_INTERFACE, ++ .bInterfaceNumber = 1, ++ .bAlternateSetting = 1, ++ .bNumEndpoints = 1, ++ .bInterfaceClass = USB_CLASS_AUDIO, ++ .bInterfaceSubClass = 0x2, ++ .bInterfaceProtocol = 0, ++ .iInterface = 0, ++}; ++ ++static const struct usb_cs_as_general_descriptor ++z_audio_cs_as_if_desc = { ++ .bLength = 7, ++ .bDescriptorType = 0x24, ++ ++ .bDescriptorSubType = 0x01, ++ .bTerminalLink = 0x01, ++ .bDelay = 0x0, ++ .wFormatTag = __constant_cpu_to_le16 (0x0001) ++}; ++ ++ ++static const struct usb_cs_as_format_descriptor ++z_audio_cs_as_format_desc = { ++ .bLength = 0xe, ++ .bDescriptorType = 0x24, ++ ++ .bDescriptorSubType = 2, ++ .bFormatType = 1, ++ .bNrChannels = 1, ++ .bSubframeSize = 1, ++ .bBitResolution = 8, ++ .bSamfreqType = 0, ++ .tLowerSamFreq = {0x7e, 0x13, 0x00}, ++ .tUpperSamFreq = {0xe2, 0xd6, 0x00}, ++}; ++ ++static const struct usb_endpoint_descriptor ++z_iso_ep = { ++ .bLength = 0x09, ++ .bDescriptorType = 0x05, ++ .bEndpointAddress = 0x04, ++ .bmAttributes = 0x09, ++ .wMaxPacketSize = 0x0038, ++ .bInterval = 0x01, ++ .bRefresh = 0x00, ++ .bSynchAddress = 0x00, ++}; ++ ++static char z_iso_ep2[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; ++ ++// 9 bytes ++static char z_ac_interface_header_desc[] = ++{ 0x09, 0x24, 0x01, 0x00, 0x01, 0x2b, 0x00, 0x01, 0x01 }; ++ ++// 12 bytes ++static char z_0[] = {0x0c, 0x24, 0x02, 0x01, 0x01, 0x01, 0x00, 0x02, ++ 0x03, 0x00, 0x00, 0x00}; ++// 13 bytes ++static char z_1[] = {0x0d, 0x24, 0x06, 0x02, 0x01, 0x02, 0x15, 0x00, ++ 0x02, 0x00, 0x02, 0x00, 0x00}; ++// 9 bytes ++static char z_2[] = {0x09, 0x24, 0x03, 0x03, 0x01, 0x03, 0x00, 0x02, ++ 0x00}; ++ ++static char za_0[] = {0x09, 0x04, 0x01, 0x02, 0x01, 0x01, 0x02, 0x00, ++ 0x00}; ++ ++static char za_1[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00}; ++ ++static char za_2[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x01, 0x08, 0x00, ++ 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00}; ++ ++static char za_3[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00, ++ 0x00}; ++ ++static char za_4[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; ++ ++static char za_5[] = {0x09, 0x04, 0x01, 0x03, 0x01, 0x01, 0x02, 0x00, ++ 0x00}; ++ ++static char za_6[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00}; ++ ++static char za_7[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x02, 0x10, 0x00, ++ 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00}; ++ ++static char za_8[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00, ++ 0x00}; ++ ++static char za_9[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; ++ ++static char za_10[] = {0x09, 0x04, 0x01, 0x04, 0x01, 0x01, 0x02, 0x00, ++ 0x00}; ++ ++static char za_11[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00}; ++ ++static char za_12[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x02, 0x10, 0x00, ++ 0x73, 0x13, 0x00, 0xe2, 0xd6, 0x00}; ++ ++static char za_13[] = {0x09, 0x05, 0x04, 0x09, 0xe0, 0x00, 0x01, 0x00, ++ 0x00}; ++ ++static char za_14[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; ++ ++static char za_15[] = {0x09, 0x04, 0x01, 0x05, 0x01, 0x01, 0x02, 0x00, ++ 0x00}; ++ ++static char za_16[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00}; ++ ++static char za_17[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x03, 0x14, 0x00, ++ 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00}; ++ ++static char za_18[] = {0x09, 0x05, 0x04, 0x09, 0xa8, 0x00, 0x01, 0x00, ++ 0x00}; ++ ++static char za_19[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; ++ ++static char za_20[] = {0x09, 0x04, 0x01, 0x06, 0x01, 0x01, 0x02, 0x00, ++ 0x00}; ++ ++static char za_21[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00}; ++ ++static char za_22[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x03, 0x14, 0x00, ++ 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00}; ++ ++static char za_23[] = {0x09, 0x05, 0x04, 0x09, 0x50, 0x01, 0x01, 0x00, ++ 0x00}; ++ ++static char za_24[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; ++ ++ ++ ++static const struct usb_descriptor_header *z_function [] = { ++ (struct usb_descriptor_header *) &z_audio_control_if_desc, ++ (struct usb_descriptor_header *) &z_ac_interface_header_desc, ++ (struct usb_descriptor_header *) &z_0, ++ (struct usb_descriptor_header *) &z_1, ++ (struct usb_descriptor_header *) &z_2, ++ (struct usb_descriptor_header *) &z_audio_if_desc, ++ (struct usb_descriptor_header *) &z_audio_if_desc2, ++ (struct usb_descriptor_header *) &z_audio_cs_as_if_desc, ++ (struct usb_descriptor_header *) &z_audio_cs_as_format_desc, ++ (struct usb_descriptor_header *) &z_iso_ep, ++ (struct usb_descriptor_header *) &z_iso_ep2, ++ (struct usb_descriptor_header *) &za_0, ++ (struct usb_descriptor_header *) &za_1, ++ (struct usb_descriptor_header *) &za_2, ++ (struct usb_descriptor_header *) &za_3, ++ (struct usb_descriptor_header *) &za_4, ++ (struct usb_descriptor_header *) &za_5, ++ (struct usb_descriptor_header *) &za_6, ++ (struct usb_descriptor_header *) &za_7, ++ (struct usb_descriptor_header *) &za_8, ++ (struct usb_descriptor_header *) &za_9, ++ (struct usb_descriptor_header *) &za_10, ++ (struct usb_descriptor_header *) &za_11, ++ (struct usb_descriptor_header *) &za_12, ++ (struct usb_descriptor_header *) &za_13, ++ (struct usb_descriptor_header *) &za_14, ++ (struct usb_descriptor_header *) &za_15, ++ (struct usb_descriptor_header *) &za_16, ++ (struct usb_descriptor_header *) &za_17, ++ (struct usb_descriptor_header *) &za_18, ++ (struct usb_descriptor_header *) &za_19, ++ (struct usb_descriptor_header *) &za_20, ++ (struct usb_descriptor_header *) &za_21, ++ (struct usb_descriptor_header *) &za_22, ++ (struct usb_descriptor_header *) &za_23, ++ (struct usb_descriptor_header *) &za_24, ++ NULL, ++}; ++ ++/* maxpacket and other transfer characteristics vary by speed. */ ++#define ep_desc(g,hs,fs) (((g)->speed==USB_SPEED_HIGH)?(hs):(fs)) ++ ++#else ++ ++/* if there's no high speed support, maxpacket doesn't change. */ ++#define ep_desc(g,hs,fs) fs ++ ++#endif /* !CONFIG_USB_GADGET_DUALSPEED */ ++ ++static char manufacturer [40]; ++//static char serial [40]; ++static char serial [] = "Ser 00 em"; ++ ++/* static strings, in UTF-8 */ ++static struct usb_string strings [] = { ++ { STRING_MANUFACTURER, manufacturer, }, ++ { STRING_PRODUCT, longname, }, ++ { STRING_SERIAL, serial, }, ++ { STRING_LOOPBACK, loopback, }, ++ { STRING_SOURCE_SINK, source_sink, }, ++ { } /* end of list */ ++}; ++ ++static struct usb_gadget_strings stringtab = { ++ .language = 0x0409, /* en-us */ ++ .strings = strings, ++}; ++ ++/* ++ * config descriptors are also handcrafted. these must agree with code ++ * that sets configurations, and with code managing interfaces and their ++ * altsettings. other complexity may come from: ++ * ++ * - high speed support, including "other speed config" rules ++ * - multiple configurations ++ * - interfaces with alternate settings ++ * - embedded class or vendor-specific descriptors ++ * ++ * this handles high speed, and has a second config that could as easily ++ * have been an alternate interface setting (on most hardware). ++ * ++ * NOTE: to demonstrate (and test) more USB capabilities, this driver ++ * should include an altsetting to test interrupt transfers, including ++ * high bandwidth modes at high speed. (Maybe work like Intel's test ++ * device?) ++ */ ++static int ++config_buf (struct usb_gadget *gadget, u8 *buf, u8 type, unsigned index) ++{ ++ int len; ++ const struct usb_descriptor_header **function; ++ ++ function = z_function; ++ len = usb_gadget_config_buf (&z_config, buf, USB_BUFSIZ, function); ++ if (len < 0) ++ return len; ++ ((struct usb_config_descriptor *) buf)->bDescriptorType = type; ++ return len; ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++static struct usb_request * ++alloc_ep_req (struct usb_ep *ep, unsigned length) ++{ ++ struct usb_request *req; ++ ++ req = usb_ep_alloc_request (ep, GFP_ATOMIC); ++ if (req) { ++ req->length = length; ++ req->buf = usb_ep_alloc_buffer (ep, length, ++ &req->dma, GFP_ATOMIC); ++ if (!req->buf) { ++ usb_ep_free_request (ep, req); ++ req = NULL; ++ } ++ } ++ return req; ++} ++ ++static void free_ep_req (struct usb_ep *ep, struct usb_request *req) ++{ ++ if (req->buf) ++ usb_ep_free_buffer (ep, req->buf, req->dma, req->length); ++ usb_ep_free_request (ep, req); ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* optionally require specific source/sink data patterns */ ++ ++static int ++check_read_data ( ++ struct zero_dev *dev, ++ struct usb_ep *ep, ++ struct usb_request *req ++) ++{ ++ unsigned i; ++ u8 *buf = req->buf; ++ ++ for (i = 0; i < req->actual; i++, buf++) { ++ switch (pattern) { ++ /* all-zeroes has no synchronization issues */ ++ case 0: ++ if (*buf == 0) ++ continue; ++ break; ++ /* mod63 stays in sync with short-terminated transfers, ++ * or otherwise when host and gadget agree on how large ++ * each usb transfer request should be. resync is done ++ * with set_interface or set_config. ++ */ ++ case 1: ++ if (*buf == (u8)(i % 63)) ++ continue; ++ break; ++ } ++ ERROR (dev, "bad OUT byte, buf [%d] = %d\n", i, *buf); ++ usb_ep_set_halt (ep); ++ return -EINVAL; ++ } ++ return 0; ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++static void zero_reset_config (struct zero_dev *dev) ++{ ++ if (dev->config == 0) ++ return; ++ ++ DBG (dev, "reset config\n"); ++ ++ /* just disable endpoints, forcing completion of pending i/o. ++ * all our completion handlers free their requests in this case. ++ */ ++ if (dev->in_ep) { ++ usb_ep_disable (dev->in_ep); ++ dev->in_ep = NULL; ++ } ++ if (dev->out_ep) { ++ usb_ep_disable (dev->out_ep); ++ dev->out_ep = NULL; ++ } ++ dev->config = 0; ++ del_timer (&dev->resume); ++} ++ ++#define _write(f, buf, sz) (f->f_op->write(f, buf, sz, &f->f_pos)) ++ ++static void ++zero_isoc_complete (struct usb_ep *ep, struct usb_request *req) ++{ ++ struct zero_dev *dev = ep->driver_data; ++ int status = req->status; ++ int i, j; ++ ++ switch (status) { ++ ++ case 0: /* normal completion? */ ++ //printk ("\nzero ---------------> isoc normal completion %d bytes\n", req->actual); ++ for (i=0, j=rbuf_start; iactual; i++) { ++ //printk ("%02x ", ((__u8*)req->buf)[i]); ++ rbuf[j] = ((__u8*)req->buf)[i]; ++ j++; ++ if (j >= RBUF_LEN) j=0; ++ } ++ rbuf_start = j; ++ //printk ("\n\n"); ++ ++ if (rbuf_len < RBUF_LEN) { ++ rbuf_len += req->actual; ++ if (rbuf_len > RBUF_LEN) { ++ rbuf_len = RBUF_LEN; ++ } ++ } ++ ++ break; ++ ++ /* this endpoint is normally active while we're configured */ ++ case -ECONNABORTED: /* hardware forced ep reset */ ++ case -ECONNRESET: /* request dequeued */ ++ case -ESHUTDOWN: /* disconnect from host */ ++ VDBG (dev, "%s gone (%d), %d/%d\n", ep->name, status, ++ req->actual, req->length); ++ if (ep == dev->out_ep) ++ check_read_data (dev, ep, req); ++ free_ep_req (ep, req); ++ return; ++ ++ case -EOVERFLOW: /* buffer overrun on read means that ++ * we didn't provide a big enough ++ * buffer. ++ */ ++ default: ++#if 1 ++ DBG (dev, "%s complete --> %d, %d/%d\n", ep->name, ++ status, req->actual, req->length); ++#endif ++ case -EREMOTEIO: /* short read */ ++ break; ++ } ++ ++ status = usb_ep_queue (ep, req, GFP_ATOMIC); ++ if (status) { ++ ERROR (dev, "kill %s: resubmit %d bytes --> %d\n", ++ ep->name, req->length, status); ++ usb_ep_set_halt (ep); ++ /* FIXME recover later ... somehow */ ++ } ++} ++ ++static struct usb_request * ++zero_start_isoc_ep (struct usb_ep *ep, int gfp_flags) ++{ ++ struct usb_request *req; ++ int status; ++ ++ req = alloc_ep_req (ep, 512); ++ if (!req) ++ return NULL; ++ ++ req->complete = zero_isoc_complete; ++ ++ status = usb_ep_queue (ep, req, gfp_flags); ++ if (status) { ++ struct zero_dev *dev = ep->driver_data; ++ ++ ERROR (dev, "start %s --> %d\n", ep->name, status); ++ free_ep_req (ep, req); ++ req = NULL; ++ } ++ ++ return req; ++} ++ ++/* change our operational config. this code must agree with the code ++ * that returns config descriptors, and altsetting code. ++ * ++ * it's also responsible for power management interactions. some ++ * configurations might not work with our current power sources. ++ * ++ * note that some device controller hardware will constrain what this ++ * code can do, perhaps by disallowing more than one configuration or ++ * by limiting configuration choices (like the pxa2xx). ++ */ ++static int ++zero_set_config (struct zero_dev *dev, unsigned number, int gfp_flags) ++{ ++ int result = 0; ++ struct usb_gadget *gadget = dev->gadget; ++ const struct usb_endpoint_descriptor *d; ++ struct usb_ep *ep; ++ ++ if (number == dev->config) ++ return 0; ++ ++ zero_reset_config (dev); ++ ++ gadget_for_each_ep (ep, gadget) { ++ ++ if (strcmp (ep->name, "ep4") == 0) { ++ ++ d = (struct usb_endpoint_descripter *)&za_23; // isoc ep desc for audio i/f alt setting 6 ++ result = usb_ep_enable (ep, d); ++ ++ if (result == 0) { ++ ep->driver_data = dev; ++ dev->in_ep = ep; ++ ++ if (zero_start_isoc_ep (ep, gfp_flags) != 0) { ++ ++ dev->in_ep = ep; ++ continue; ++ } ++ ++ usb_ep_disable (ep); ++ result = -EIO; ++ } ++ } ++ ++ } ++ ++ dev->config = number; ++ return result; ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++static void zero_setup_complete (struct usb_ep *ep, struct usb_request *req) ++{ ++ if (req->status || req->actual != req->length) ++ DBG ((struct zero_dev *) ep->driver_data, ++ "setup complete --> %d, %d/%d\n", ++ req->status, req->actual, req->length); ++} ++ ++/* ++ * The setup() callback implements all the ep0 functionality that's ++ * not handled lower down, in hardware or the hardware driver (like ++ * device and endpoint feature flags, and their status). It's all ++ * housekeeping for the gadget function we're implementing. Most of ++ * the work is in config-specific setup. ++ */ ++static int ++zero_setup (struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl) ++{ ++ struct zero_dev *dev = get_gadget_data (gadget); ++ struct usb_request *req = dev->req; ++ int value = -EOPNOTSUPP; ++ ++ /* usually this stores reply data in the pre-allocated ep0 buffer, ++ * but config change events will reconfigure hardware. ++ */ ++ req->zero = 0; ++ switch (ctrl->bRequest) { ++ ++ case USB_REQ_GET_DESCRIPTOR: ++ ++ switch (ctrl->wValue >> 8) { ++ ++ case USB_DT_DEVICE: ++ value = min (ctrl->wLength, (u16) sizeof device_desc); ++ memcpy (req->buf, &device_desc, value); ++ break; ++#ifdef CONFIG_USB_GADGET_DUALSPEED ++ case USB_DT_DEVICE_QUALIFIER: ++ if (!gadget->is_dualspeed) ++ break; ++ value = min (ctrl->wLength, (u16) sizeof dev_qualifier); ++ memcpy (req->buf, &dev_qualifier, value); ++ break; ++ ++ case USB_DT_OTHER_SPEED_CONFIG: ++ if (!gadget->is_dualspeed) ++ break; ++ // FALLTHROUGH ++#endif /* CONFIG_USB_GADGET_DUALSPEED */ ++ case USB_DT_CONFIG: ++ value = config_buf (gadget, req->buf, ++ ctrl->wValue >> 8, ++ ctrl->wValue & 0xff); ++ if (value >= 0) ++ value = min (ctrl->wLength, (u16) value); ++ break; ++ ++ case USB_DT_STRING: ++ /* wIndex == language code. ++ * this driver only handles one language, you can ++ * add string tables for other languages, using ++ * any UTF-8 characters ++ */ ++ value = usb_gadget_get_string (&stringtab, ++ ctrl->wValue & 0xff, req->buf); ++ if (value >= 0) { ++ value = min (ctrl->wLength, (u16) value); ++ } ++ break; ++ } ++ break; ++ ++ /* currently two configs, two speeds */ ++ case USB_REQ_SET_CONFIGURATION: ++ if (ctrl->bRequestType != 0) ++ goto unknown; ++ ++ spin_lock (&dev->lock); ++ value = zero_set_config (dev, ctrl->wValue, GFP_ATOMIC); ++ spin_unlock (&dev->lock); ++ break; ++ case USB_REQ_GET_CONFIGURATION: ++ if (ctrl->bRequestType != USB_DIR_IN) ++ goto unknown; ++ *(u8 *)req->buf = dev->config; ++ value = min (ctrl->wLength, (u16) 1); ++ break; ++ ++ /* until we add altsetting support, or other interfaces, ++ * only 0/0 are possible. pxa2xx only supports 0/0 (poorly) ++ * and already killed pending endpoint I/O. ++ */ ++ case USB_REQ_SET_INTERFACE: ++ ++ if (ctrl->bRequestType != USB_RECIP_INTERFACE) ++ goto unknown; ++ spin_lock (&dev->lock); ++ if (dev->config) { ++ u8 config = dev->config; ++ ++ /* resets interface configuration, forgets about ++ * previous transaction state (queued bufs, etc) ++ * and re-inits endpoint state (toggle etc) ++ * no response queued, just zero status == success. ++ * if we had more than one interface we couldn't ++ * use this "reset the config" shortcut. ++ */ ++ zero_reset_config (dev); ++ zero_set_config (dev, config, GFP_ATOMIC); ++ value = 0; ++ } ++ spin_unlock (&dev->lock); ++ break; ++ case USB_REQ_GET_INTERFACE: ++ if ((ctrl->bRequestType == 0x21) && (ctrl->wIndex == 0x02)) { ++ value = ctrl->wLength; ++ break; ++ } ++ else { ++ if (ctrl->bRequestType != (USB_DIR_IN|USB_RECIP_INTERFACE)) ++ goto unknown; ++ if (!dev->config) ++ break; ++ if (ctrl->wIndex != 0) { ++ value = -EDOM; ++ break; ++ } ++ *(u8 *)req->buf = 0; ++ value = min (ctrl->wLength, (u16) 1); ++ } ++ break; ++ ++ /* ++ * These are the same vendor-specific requests supported by ++ * Intel's USB 2.0 compliance test devices. We exceed that ++ * device spec by allowing multiple-packet requests. ++ */ ++ case 0x5b: /* control WRITE test -- fill the buffer */ ++ if (ctrl->bRequestType != (USB_DIR_OUT|USB_TYPE_VENDOR)) ++ goto unknown; ++ if (ctrl->wValue || ctrl->wIndex) ++ break; ++ /* just read that many bytes into the buffer */ ++ if (ctrl->wLength > USB_BUFSIZ) ++ break; ++ value = ctrl->wLength; ++ break; ++ case 0x5c: /* control READ test -- return the buffer */ ++ if (ctrl->bRequestType != (USB_DIR_IN|USB_TYPE_VENDOR)) ++ goto unknown; ++ if (ctrl->wValue || ctrl->wIndex) ++ break; ++ /* expect those bytes are still in the buffer; send back */ ++ if (ctrl->wLength > USB_BUFSIZ ++ || ctrl->wLength != req->length) ++ break; ++ value = ctrl->wLength; ++ break; ++ ++ case 0x01: // SET_CUR ++ case 0x02: ++ case 0x03: ++ case 0x04: ++ case 0x05: ++ value = ctrl->wLength; ++ break; ++ case 0x81: ++ switch (ctrl->wValue) { ++ case 0x0201: ++ case 0x0202: ++ ((u8*)req->buf)[0] = 0x00; ++ ((u8*)req->buf)[1] = 0xe3; ++ break; ++ case 0x0300: ++ case 0x0500: ++ ((u8*)req->buf)[0] = 0x00; ++ break; ++ } ++ //((u8*)req->buf)[0] = 0x81; ++ //((u8*)req->buf)[1] = 0x81; ++ value = ctrl->wLength; ++ break; ++ case 0x82: ++ switch (ctrl->wValue) { ++ case 0x0201: ++ case 0x0202: ++ ((u8*)req->buf)[0] = 0x00; ++ ((u8*)req->buf)[1] = 0xc3; ++ break; ++ case 0x0300: ++ case 0x0500: ++ ((u8*)req->buf)[0] = 0x00; ++ break; ++ } ++ //((u8*)req->buf)[0] = 0x82; ++ //((u8*)req->buf)[1] = 0x82; ++ value = ctrl->wLength; ++ break; ++ case 0x83: ++ switch (ctrl->wValue) { ++ case 0x0201: ++ case 0x0202: ++ ((u8*)req->buf)[0] = 0x00; ++ ((u8*)req->buf)[1] = 0x00; ++ break; ++ case 0x0300: ++ ((u8*)req->buf)[0] = 0x60; ++ break; ++ case 0x0500: ++ ((u8*)req->buf)[0] = 0x18; ++ break; ++ } ++ //((u8*)req->buf)[0] = 0x83; ++ //((u8*)req->buf)[1] = 0x83; ++ value = ctrl->wLength; ++ break; ++ case 0x84: ++ switch (ctrl->wValue) { ++ case 0x0201: ++ case 0x0202: ++ ((u8*)req->buf)[0] = 0x00; ++ ((u8*)req->buf)[1] = 0x01; ++ break; ++ case 0x0300: ++ case 0x0500: ++ ((u8*)req->buf)[0] = 0x08; ++ break; ++ } ++ //((u8*)req->buf)[0] = 0x84; ++ //((u8*)req->buf)[1] = 0x84; ++ value = ctrl->wLength; ++ break; ++ case 0x85: ++ ((u8*)req->buf)[0] = 0x85; ++ ((u8*)req->buf)[1] = 0x85; ++ value = ctrl->wLength; ++ break; ++ ++ ++ default: ++unknown: ++ printk("unknown control req%02x.%02x v%04x i%04x l%d\n", ++ ctrl->bRequestType, ctrl->bRequest, ++ ctrl->wValue, ctrl->wIndex, ctrl->wLength); ++ } ++ ++ /* respond with data transfer before status phase? */ ++ if (value >= 0) { ++ req->length = value; ++ req->zero = value < ctrl->wLength ++ && (value % gadget->ep0->maxpacket) == 0; ++ value = usb_ep_queue (gadget->ep0, req, GFP_ATOMIC); ++ if (value < 0) { ++ DBG (dev, "ep_queue < 0 --> %d\n", value); ++ req->status = 0; ++ zero_setup_complete (gadget->ep0, req); ++ } ++ } ++ ++ /* device either stalls (value < 0) or reports success */ ++ return value; ++} ++ ++static void ++zero_disconnect (struct usb_gadget *gadget) ++{ ++ struct zero_dev *dev = get_gadget_data (gadget); ++ unsigned long flags; ++ ++ spin_lock_irqsave (&dev->lock, flags); ++ zero_reset_config (dev); ++ ++ /* a more significant application might have some non-usb ++ * activities to quiesce here, saving resources like power ++ * or pushing the notification up a network stack. ++ */ ++ spin_unlock_irqrestore (&dev->lock, flags); ++ ++ /* next we may get setup() calls to enumerate new connections; ++ * or an unbind() during shutdown (including removing module). ++ */ ++} ++ ++static void ++zero_autoresume (unsigned long _dev) ++{ ++ struct zero_dev *dev = (struct zero_dev *) _dev; ++ int status; ++ ++ /* normally the host would be woken up for something ++ * more significant than just a timer firing... ++ */ ++ if (dev->gadget->speed != USB_SPEED_UNKNOWN) { ++ status = usb_gadget_wakeup (dev->gadget); ++ DBG (dev, "wakeup --> %d\n", status); ++ } ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++static void ++zero_unbind (struct usb_gadget *gadget) ++{ ++ struct zero_dev *dev = get_gadget_data (gadget); ++ ++ DBG (dev, "unbind\n"); ++ ++ /* we've already been disconnected ... no i/o is active */ ++ if (dev->req) ++ free_ep_req (gadget->ep0, dev->req); ++ del_timer_sync (&dev->resume); ++ kfree (dev); ++ set_gadget_data (gadget, NULL); ++} ++ ++static int ++zero_bind (struct usb_gadget *gadget) ++{ ++ struct zero_dev *dev; ++ //struct usb_ep *ep; ++ ++ printk("binding\n"); ++ /* ++ * DRIVER POLICY CHOICE: you may want to do this differently. ++ * One thing to avoid is reusing a bcdDevice revision code ++ * with different host-visible configurations or behavior ++ * restrictions -- using ep1in/ep2out vs ep1out/ep3in, etc ++ */ ++ //device_desc.bcdDevice = __constant_cpu_to_le16 (0x0201); ++ ++ ++ /* ok, we made sense of the hardware ... */ ++ dev = kmalloc (sizeof *dev, SLAB_KERNEL); ++ if (!dev) ++ return -ENOMEM; ++ memset (dev, 0, sizeof *dev); ++ spin_lock_init (&dev->lock); ++ dev->gadget = gadget; ++ set_gadget_data (gadget, dev); ++ ++ /* preallocate control response and buffer */ ++ dev->req = usb_ep_alloc_request (gadget->ep0, GFP_KERNEL); ++ if (!dev->req) ++ goto enomem; ++ dev->req->buf = usb_ep_alloc_buffer (gadget->ep0, USB_BUFSIZ, ++ &dev->req->dma, GFP_KERNEL); ++ if (!dev->req->buf) ++ goto enomem; ++ ++ dev->req->complete = zero_setup_complete; ++ ++ device_desc.bMaxPacketSize0 = gadget->ep0->maxpacket; ++ ++#ifdef CONFIG_USB_GADGET_DUALSPEED ++ /* assume ep0 uses the same value for both speeds ... */ ++ dev_qualifier.bMaxPacketSize0 = device_desc.bMaxPacketSize0; ++ ++ /* and that all endpoints are dual-speed */ ++ //hs_source_desc.bEndpointAddress = fs_source_desc.bEndpointAddress; ++ //hs_sink_desc.bEndpointAddress = fs_sink_desc.bEndpointAddress; ++#endif ++ ++ usb_gadget_set_selfpowered (gadget); ++ ++ init_timer (&dev->resume); ++ dev->resume.function = zero_autoresume; ++ dev->resume.data = (unsigned long) dev; ++ ++ gadget->ep0->driver_data = dev; ++ ++ INFO (dev, "%s, version: " DRIVER_VERSION "\n", longname); ++ INFO (dev, "using %s, OUT %s IN %s\n", gadget->name, ++ EP_OUT_NAME, EP_IN_NAME); ++ ++ snprintf (manufacturer, sizeof manufacturer, ++ UTS_SYSNAME " " UTS_RELEASE " with %s", ++ gadget->name); ++ ++ return 0; ++ ++enomem: ++ zero_unbind (gadget); ++ return -ENOMEM; ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++static void ++zero_suspend (struct usb_gadget *gadget) ++{ ++ struct zero_dev *dev = get_gadget_data (gadget); ++ ++ if (gadget->speed == USB_SPEED_UNKNOWN) ++ return; ++ ++ if (autoresume) { ++ mod_timer (&dev->resume, jiffies + (HZ * autoresume)); ++ DBG (dev, "suspend, wakeup in %d seconds\n", autoresume); ++ } else ++ DBG (dev, "suspend\n"); ++} ++ ++static void ++zero_resume (struct usb_gadget *gadget) ++{ ++ struct zero_dev *dev = get_gadget_data (gadget); ++ ++ DBG (dev, "resume\n"); ++ del_timer (&dev->resume); ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++static struct usb_gadget_driver zero_driver = { ++#ifdef CONFIG_USB_GADGET_DUALSPEED ++ .speed = USB_SPEED_HIGH, ++#else ++ .speed = USB_SPEED_FULL, ++#endif ++ .function = (char *) longname, ++ .bind = zero_bind, ++ .unbind = zero_unbind, ++ ++ .setup = zero_setup, ++ .disconnect = zero_disconnect, ++ ++ .suspend = zero_suspend, ++ .resume = zero_resume, ++ ++ .driver = { ++ .name = (char *) shortname, ++ // .shutdown = ... ++ // .suspend = ... ++ // .resume = ... ++ }, ++}; ++ ++MODULE_AUTHOR ("David Brownell"); ++MODULE_LICENSE ("Dual BSD/GPL"); ++ ++static struct proc_dir_entry *pdir, *pfile; ++ ++static int isoc_read_data (char *page, char **start, ++ off_t off, int count, ++ int *eof, void *data) ++{ ++ int i; ++ static int c = 0; ++ static int done = 0; ++ static int s = 0; ++ ++/* ++ printk ("\ncount: %d\n", count); ++ printk ("rbuf_start: %d\n", rbuf_start); ++ printk ("rbuf_len: %d\n", rbuf_len); ++ printk ("off: %d\n", off); ++ printk ("start: %p\n\n", *start); ++*/ ++ if (done) { ++ c = 0; ++ done = 0; ++ *eof = 1; ++ return 0; ++ } ++ ++ if (c == 0) { ++ if (rbuf_len == RBUF_LEN) ++ s = rbuf_start; ++ else s = 0; ++ } ++ ++ for (i=0; i= rbuf_len) { ++ *eof = 1; ++ done = 1; ++ } ++ ++ ++ return i; ++} ++ ++static int __init init (void) ++{ ++ ++ int retval = 0; ++ ++ pdir = proc_mkdir("isoc_test", NULL); ++ if(pdir == NULL) { ++ retval = -ENOMEM; ++ printk("Error creating dir\n"); ++ goto done; ++ } ++ pdir->owner = THIS_MODULE; ++ ++ pfile = create_proc_read_entry("isoc_data", ++ 0444, pdir, ++ isoc_read_data, ++ NULL); ++ if (pfile == NULL) { ++ retval = -ENOMEM; ++ printk("Error creating file\n"); ++ goto no_file; ++ } ++ pfile->owner = THIS_MODULE; ++ ++ return usb_gadget_register_driver (&zero_driver); ++ ++ no_file: ++ remove_proc_entry("isoc_data", NULL); ++ done: ++ return retval; ++} ++module_init (init); ++ ++static void __exit cleanup (void) ++{ ++ ++ usb_gadget_unregister_driver (&zero_driver); ++ ++ remove_proc_entry("isoc_data", pdir); ++ remove_proc_entry("isoc_test", NULL); ++} ++module_exit (cleanup); +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_cfi_common.h linux-rpi/drivers/usb/host/dwc_otg/dwc_cfi_common.h +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_cfi_common.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/dwc_cfi_common.h 2015-11-29 09:42:39.915098960 +0100 +@@ -0,0 +1,142 @@ ++/* ========================================================================== ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++#if !defined(__DWC_CFI_COMMON_H__) ++#define __DWC_CFI_COMMON_H__ ++ ++//#include ++ ++/** ++ * @file ++ * ++ * This file contains the CFI specific common constants, interfaces ++ * (functions and macros) and structures for Linux. No PCD specific ++ * data structure or definition is to be included in this file. ++ * ++ */ ++ ++/** This is a request for all Core Features */ ++#define VEN_CORE_GET_FEATURES 0xB1 ++ ++/** This is a request to get the value of a specific Core Feature */ ++#define VEN_CORE_GET_FEATURE 0xB2 ++ ++/** This command allows the host to set the value of a specific Core Feature */ ++#define VEN_CORE_SET_FEATURE 0xB3 ++ ++/** This command allows the host to set the default values of ++ * either all or any specific Core Feature ++ */ ++#define VEN_CORE_RESET_FEATURES 0xB4 ++ ++/** This command forces the PCD to write the deferred values of a Core Features */ ++#define VEN_CORE_ACTIVATE_FEATURES 0xB5 ++ ++/** This request reads a DWORD value from a register at the specified offset */ ++#define VEN_CORE_READ_REGISTER 0xB6 ++ ++/** This request writes a DWORD value into a register at the specified offset */ ++#define VEN_CORE_WRITE_REGISTER 0xB7 ++ ++/** This structure is the header of the Core Features dataset returned to ++ * the Host ++ */ ++struct cfi_all_features_header { ++/** The features header structure length is */ ++#define CFI_ALL_FEATURES_HDR_LEN 8 ++ /** ++ * The total length of the features dataset returned to the Host ++ */ ++ uint16_t wTotalLen; ++ ++ /** ++ * CFI version number inBinary-Coded Decimal (i.e., 1.00 is 100H). ++ * This field identifies the version of the CFI Specification with which ++ * the device is compliant. ++ */ ++ uint16_t wVersion; ++ ++ /** The ID of the Core */ ++ uint16_t wCoreID; ++#define CFI_CORE_ID_UDC 1 ++#define CFI_CORE_ID_OTG 2 ++#define CFI_CORE_ID_WUDEV 3 ++ ++ /** Number of features returned by VEN_CORE_GET_FEATURES request */ ++ uint16_t wNumFeatures; ++} UPACKED; ++ ++typedef struct cfi_all_features_header cfi_all_features_header_t; ++ ++/** This structure is a header of the Core Feature descriptor dataset returned to ++ * the Host after the VEN_CORE_GET_FEATURES request ++ */ ++struct cfi_feature_desc_header { ++#define CFI_FEATURE_DESC_HDR_LEN 8 ++ ++ /** The feature ID */ ++ uint16_t wFeatureID; ++ ++ /** Length of this feature descriptor in bytes - including the ++ * length of the feature name string ++ */ ++ uint16_t wLength; ++ ++ /** The data length of this feature in bytes */ ++ uint16_t wDataLength; ++ ++ /** ++ * Attributes of this features ++ * D0: Access rights ++ * 0 - Read/Write ++ * 1 - Read only ++ */ ++ uint8_t bmAttributes; ++#define CFI_FEATURE_ATTR_RO 1 ++#define CFI_FEATURE_ATTR_RW 0 ++ ++ /** Length of the feature name in bytes */ ++ uint8_t bNameLen; ++ ++ /** The feature name buffer */ ++ //uint8_t *name; ++} UPACKED; ++ ++typedef struct cfi_feature_desc_header cfi_feature_desc_header_t; ++ ++/** ++ * This structure describes a NULL terminated string referenced by its id field. ++ * It is very similar to usb_string structure but has the id field type set to 16-bit. ++ */ ++struct cfi_string { ++ uint16_t id; ++ const uint8_t *s; ++}; ++typedef struct cfi_string cfi_string_t; ++ ++#endif +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_adp.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_adp.c +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_adp.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_adp.c 2015-11-29 09:42:39.915098960 +0100 +@@ -0,0 +1,854 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.c $ ++ * $Revision: #12 $ ++ * $Date: 2011/10/26 $ ++ * $Change: 1873028 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++#include "dwc_os.h" ++#include "dwc_otg_regs.h" ++#include "dwc_otg_cil.h" ++#include "dwc_otg_adp.h" ++ ++/** @file ++ * ++ * This file contains the most of the Attach Detect Protocol implementation for ++ * the driver to support OTG Rev2.0. ++ * ++ */ ++ ++void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value) ++{ ++ adpctl_data_t adpctl; ++ ++ adpctl.d32 = value; ++ adpctl.b.ar = 0x2; ++ ++ DWC_WRITE_REG32(&core_if->core_global_regs->adpctl, adpctl.d32); ++ ++ while (adpctl.b.ar) { ++ adpctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->adpctl); ++ } ++ ++} ++ ++/** ++ * Function is called to read ADP registers ++ */ ++uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if) ++{ ++ adpctl_data_t adpctl; ++ ++ adpctl.d32 = 0; ++ adpctl.b.ar = 0x1; ++ ++ DWC_WRITE_REG32(&core_if->core_global_regs->adpctl, adpctl.d32); ++ ++ while (adpctl.b.ar) { ++ adpctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->adpctl); ++ } ++ ++ return adpctl.d32; ++} ++ ++/** ++ * Function is called to read ADPCTL register and filter Write-clear bits ++ */ ++uint32_t dwc_otg_adp_read_reg_filter(dwc_otg_core_if_t * core_if) ++{ ++ adpctl_data_t adpctl; ++ ++ adpctl.d32 = dwc_otg_adp_read_reg(core_if); ++ adpctl.b.adp_tmout_int = 0; ++ adpctl.b.adp_prb_int = 0; ++ adpctl.b.adp_tmout_int = 0; ++ ++ return adpctl.d32; ++} ++ ++/** ++ * Function is called to write ADP registers ++ */ ++void dwc_otg_adp_modify_reg(dwc_otg_core_if_t * core_if, uint32_t clr, ++ uint32_t set) ++{ ++ dwc_otg_adp_write_reg(core_if, ++ (dwc_otg_adp_read_reg(core_if) & (~clr)) | set); ++} ++ ++static void adp_sense_timeout(void *ptr) ++{ ++ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr; ++ core_if->adp.sense_timer_started = 0; ++ DWC_PRINTF("ADP SENSE TIMEOUT\n"); ++ if (core_if->adp_enable) { ++ dwc_otg_adp_sense_stop(core_if); ++ dwc_otg_adp_probe_start(core_if); ++ } ++} ++ ++/** ++ * This function is called when the ADP vbus timer expires. Timeout is 1.1s. ++ */ ++static void adp_vbuson_timeout(void *ptr) ++{ ++ gpwrdn_data_t gpwrdn; ++ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr; ++ hprt0_data_t hprt0 = {.d32 = 0 }; ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ DWC_PRINTF("%s: 1.1 seconds expire after turning on VBUS\n",__FUNCTION__); ++ if (core_if) { ++ core_if->adp.vbuson_timer_started = 0; ++ /* Turn off vbus */ ++ hprt0.b.prtpwr = 1; ++ DWC_MODIFY_REG32(core_if->host_if->hprt0, hprt0.d32, 0); ++ gpwrdn.d32 = 0; ++ ++ /* Power off the core */ ++ if (core_if->power_down == 2) { ++ /* Enable Wakeup Logic */ ++// gpwrdn.b.wkupactiv = 1; ++ gpwrdn.b.pmuactv = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ gpwrdn.b.pwrdnclmp = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, ++ gpwrdn.d32); ++ ++ /* Suspend the Phy Clock */ ++ pcgcctl.b.stoppclk = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32); ++ ++ /* Switch on VDD */ ++// gpwrdn.b.wkupactiv = 1; ++ gpwrdn.b.pmuactv = 1; ++ gpwrdn.b.pwrdnrstn = 1; ++ gpwrdn.b.pwrdnclmp = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, ++ gpwrdn.d32); ++ } else { ++ /* Enable Power Down Logic */ ++ gpwrdn.b.pmuintsel = 1; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ } ++ ++ /* Power off the core */ ++ if (core_if->power_down == 2) { ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, ++ gpwrdn.d32, 0); ++ } ++ ++ /* Unmask SRP detected interrupt from Power Down Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.srp_det_msk = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ ++ dwc_otg_adp_probe_start(core_if); ++ dwc_otg_dump_global_registers(core_if); ++ dwc_otg_dump_host_registers(core_if); ++ } ++ ++} ++ ++/** ++ * Start the ADP Initial Probe timer to detect if Port Connected interrupt is ++ * not asserted within 1.1 seconds. ++ * ++ * @param core_if the pointer to core_if strucure. ++ */ ++void dwc_otg_adp_vbuson_timer_start(dwc_otg_core_if_t * core_if) ++{ ++ core_if->adp.vbuson_timer_started = 1; ++ if (core_if->adp.vbuson_timer) ++ { ++ DWC_PRINTF("SCHEDULING VBUSON TIMER\n"); ++ /* 1.1 secs + 60ms necessary for cil_hcd_start*/ ++ DWC_TIMER_SCHEDULE(core_if->adp.vbuson_timer, 1160); ++ } else { ++ DWC_WARN("VBUSON_TIMER = %p\n",core_if->adp.vbuson_timer); ++ } ++} ++ ++#if 0 ++/** ++ * Masks all DWC OTG core interrupts ++ * ++ */ ++static void mask_all_interrupts(dwc_otg_core_if_t * core_if) ++{ ++ int i; ++ gahbcfg_data_t ahbcfg = {.d32 = 0 }; ++ ++ /* Mask Host Interrupts */ ++ ++ /* Clear and disable HCINTs */ ++ for (i = 0; i < core_if->core_params->host_channels; i++) { ++ DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk, 0); ++ DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcint, 0xFFFFFFFF); ++ ++ } ++ ++ /* Clear and disable HAINT */ ++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk, 0x0000); ++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haint, 0xFFFFFFFF); ++ ++ /* Mask Device Interrupts */ ++ if (!core_if->multiproc_int_enable) { ++ /* Clear and disable IN Endpoint interrupts */ ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, 0); ++ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) { ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]-> ++ diepint, 0xFFFFFFFF); ++ } ++ ++ /* Clear and disable OUT Endpoint interrupts */ ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, 0); ++ for (i = 0; i <= core_if->dev_if->num_out_eps; i++) { ++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]-> ++ doepint, 0xFFFFFFFF); ++ } ++ ++ /* Clear and disable DAINT */ ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daint, ++ 0xFFFFFFFF); ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, 0); ++ } else { ++ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) { ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs-> ++ diepeachintmsk[i], 0); ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]-> ++ diepint, 0xFFFFFFFF); ++ } ++ ++ for (i = 0; i < core_if->dev_if->num_out_eps; ++i) { ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs-> ++ doepeachintmsk[i], 0); ++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]-> ++ doepint, 0xFFFFFFFF); ++ } ++ ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachintmsk, ++ 0); ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachint, ++ 0xFFFFFFFF); ++ ++ } ++ ++ /* Disable interrupts */ ++ ahbcfg.b.glblintrmsk = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0); ++ ++ /* Disable all interrupts. */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0); ++ ++ /* Clear any pending interrupts */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); ++ ++ /* Clear any pending OTG Interrupts */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gotgint, 0xFFFFFFFF); ++} ++ ++/** ++ * Unmask Port Connection Detected interrupt ++ * ++ */ ++static void unmask_conn_det_intr(dwc_otg_core_if_t * core_if) ++{ ++ gintmsk_data_t gintmsk = {.d32 = 0,.b.portintr = 1 }; ++ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32); ++} ++#endif ++ ++/** ++ * Starts the ADP Probing ++ * ++ * @param core_if the pointer to core_if structure. ++ */ ++uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if) ++{ ++ ++ adpctl_data_t adpctl = {.d32 = 0}; ++ gpwrdn_data_t gpwrdn; ++#if 0 ++ adpctl_data_t adpctl_int = {.d32 = 0, .b.adp_prb_int = 1, ++ .b.adp_sns_int = 1, b.adp_tmout_int}; ++#endif ++ dwc_otg_disable_global_interrupts(core_if); ++ DWC_PRINTF("ADP Probe Start\n"); ++ core_if->adp.probe_enabled = 1; ++ ++ adpctl.b.adpres = 1; ++ dwc_otg_adp_write_reg(core_if, adpctl.d32); ++ ++ while (adpctl.b.adpres) { ++ adpctl.d32 = dwc_otg_adp_read_reg(core_if); ++ } ++ ++ adpctl.d32 = 0; ++ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ ++ /* In Host mode unmask SRP detected interrupt */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.sts_chngint_msk = 1; ++ if (!gpwrdn.b.idsts) { ++ gpwrdn.b.srp_det_msk = 1; ++ } ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ ++ adpctl.b.adp_tmout_int_msk = 1; ++ adpctl.b.adp_prb_int_msk = 1; ++ adpctl.b.prb_dschg = 1; ++ adpctl.b.prb_delta = 1; ++ adpctl.b.prb_per = 1; ++ adpctl.b.adpen = 1; ++ adpctl.b.enaprb = 1; ++ ++ dwc_otg_adp_write_reg(core_if, adpctl.d32); ++ DWC_PRINTF("ADP Probe Finish\n"); ++ return 0; ++} ++ ++/** ++ * Starts the ADP Sense timer to detect if ADP Sense interrupt is not asserted ++ * within 3 seconds. ++ * ++ * @param core_if the pointer to core_if strucure. ++ */ ++void dwc_otg_adp_sense_timer_start(dwc_otg_core_if_t * core_if) ++{ ++ core_if->adp.sense_timer_started = 1; ++ DWC_TIMER_SCHEDULE(core_if->adp.sense_timer, 3000 /* 3 secs */ ); ++} ++ ++/** ++ * Starts the ADP Sense ++ * ++ * @param core_if the pointer to core_if strucure. ++ */ ++uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if) ++{ ++ adpctl_data_t adpctl; ++ ++ DWC_PRINTF("ADP Sense Start\n"); ++ ++ /* Unmask ADP sense interrupt and mask all other from the core */ ++ adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if); ++ adpctl.b.adp_sns_int_msk = 1; ++ dwc_otg_adp_write_reg(core_if, adpctl.d32); ++ dwc_otg_disable_global_interrupts(core_if); // vahrama ++ ++ /* Set ADP reset bit*/ ++ adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if); ++ adpctl.b.adpres = 1; ++ dwc_otg_adp_write_reg(core_if, adpctl.d32); ++ ++ while (adpctl.b.adpres) { ++ adpctl.d32 = dwc_otg_adp_read_reg(core_if); ++ } ++ ++ adpctl.b.adpres = 0; ++ adpctl.b.adpen = 1; ++ adpctl.b.enasns = 1; ++ dwc_otg_adp_write_reg(core_if, adpctl.d32); ++ ++ dwc_otg_adp_sense_timer_start(core_if); ++ ++ return 0; ++} ++ ++/** ++ * Stops the ADP Probing ++ * ++ * @param core_if the pointer to core_if strucure. ++ */ ++uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if) ++{ ++ ++ adpctl_data_t adpctl; ++ DWC_PRINTF("Stop ADP probe\n"); ++ core_if->adp.probe_enabled = 0; ++ core_if->adp.probe_counter = 0; ++ adpctl.d32 = dwc_otg_adp_read_reg(core_if); ++ ++ adpctl.b.adpen = 0; ++ adpctl.b.adp_prb_int = 1; ++ adpctl.b.adp_tmout_int = 1; ++ adpctl.b.adp_sns_int = 1; ++ dwc_otg_adp_write_reg(core_if, adpctl.d32); ++ ++ return 0; ++} ++ ++/** ++ * Stops the ADP Sensing ++ * ++ * @param core_if the pointer to core_if strucure. ++ */ ++uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if) ++{ ++ adpctl_data_t adpctl; ++ ++ core_if->adp.sense_enabled = 0; ++ ++ adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if); ++ adpctl.b.enasns = 0; ++ adpctl.b.adp_sns_int = 1; ++ dwc_otg_adp_write_reg(core_if, adpctl.d32); ++ ++ return 0; ++} ++ ++/** ++ * Called to turn on the VBUS after initial ADP probe in host mode. ++ * If port power was already enabled in cil_hcd_start function then ++ * only schedule a timer. ++ * ++ * @param core_if the pointer to core_if structure. ++ */ ++void dwc_otg_adp_turnon_vbus(dwc_otg_core_if_t * core_if) ++{ ++ hprt0_data_t hprt0 = {.d32 = 0 }; ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ DWC_PRINTF("Turn on VBUS for 1.1s, port power is %d\n", hprt0.b.prtpwr); ++ ++ if (hprt0.b.prtpwr == 0) { ++ hprt0.b.prtpwr = 1; ++ //DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ } ++ ++ dwc_otg_adp_vbuson_timer_start(core_if); ++} ++ ++/** ++ * Called right after driver is loaded ++ * to perform initial actions for ADP ++ * ++ * @param core_if the pointer to core_if structure. ++ * @param is_host - flag for current mode of operation either from GINTSTS or GPWRDN ++ */ ++void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host) ++{ ++ gpwrdn_data_t gpwrdn; ++ ++ DWC_PRINTF("ADP Initial Start\n"); ++ core_if->adp.adp_started = 1; ++ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); ++ dwc_otg_disable_global_interrupts(core_if); ++ if (is_host) { ++ DWC_PRINTF("HOST MODE\n"); ++ /* Enable Power Down Logic Interrupt*/ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ /* Initialize first ADP probe to obtain Ramp Time value */ ++ core_if->adp.initial_probe = 1; ++ dwc_otg_adp_probe_start(core_if); ++ } else { ++ gotgctl_data_t gotgctl; ++ gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl); ++ DWC_PRINTF("DEVICE MODE\n"); ++ if (gotgctl.b.bsesvld == 0) { ++ /* Enable Power Down Logic Interrupt*/ ++ gpwrdn.d32 = 0; ++ DWC_PRINTF("VBUS is not valid - start ADP probe\n"); ++ gpwrdn.b.pmuintsel = 1; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ core_if->adp.initial_probe = 1; ++ dwc_otg_adp_probe_start(core_if); ++ } else { ++ DWC_PRINTF("VBUS is valid - initialize core as a Device\n"); ++ core_if->op_state = B_PERIPHERAL; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_pcd_start(core_if); ++ dwc_otg_dump_global_registers(core_if); ++ dwc_otg_dump_dev_registers(core_if); ++ } ++ } ++} ++ ++void dwc_otg_adp_init(dwc_otg_core_if_t * core_if) ++{ ++ core_if->adp.adp_started = 0; ++ core_if->adp.initial_probe = 0; ++ core_if->adp.probe_timer_values[0] = -1; ++ core_if->adp.probe_timer_values[1] = -1; ++ core_if->adp.probe_enabled = 0; ++ core_if->adp.sense_enabled = 0; ++ core_if->adp.sense_timer_started = 0; ++ core_if->adp.vbuson_timer_started = 0; ++ core_if->adp.probe_counter = 0; ++ core_if->adp.gpwrdn = 0; ++ core_if->adp.attached = DWC_OTG_ADP_UNKOWN; ++ /* Initialize timers */ ++ core_if->adp.sense_timer = ++ DWC_TIMER_ALLOC("ADP SENSE TIMER", adp_sense_timeout, core_if); ++ core_if->adp.vbuson_timer = ++ DWC_TIMER_ALLOC("ADP VBUS ON TIMER", adp_vbuson_timeout, core_if); ++ if (!core_if->adp.sense_timer || !core_if->adp.vbuson_timer) ++ { ++ DWC_ERROR("Could not allocate memory for ADP timers\n"); ++ } ++} ++ ++void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if) ++{ ++ gpwrdn_data_t gpwrdn = { .d32 = 0 }; ++ gpwrdn.b.pmuintsel = 1; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ if (core_if->adp.probe_enabled) ++ dwc_otg_adp_probe_stop(core_if); ++ if (core_if->adp.sense_enabled) ++ dwc_otg_adp_sense_stop(core_if); ++ if (core_if->adp.sense_timer_started) ++ DWC_TIMER_CANCEL(core_if->adp.sense_timer); ++ if (core_if->adp.vbuson_timer_started) ++ DWC_TIMER_CANCEL(core_if->adp.vbuson_timer); ++ DWC_TIMER_FREE(core_if->adp.sense_timer); ++ DWC_TIMER_FREE(core_if->adp.vbuson_timer); ++} ++ ++///////////////////////////////////////////////////////////////////// ++////////////// ADP Interrupt Handlers /////////////////////////////// ++///////////////////////////////////////////////////////////////////// ++/** ++ * This function sets Ramp Timer values ++ */ ++static uint32_t set_timer_value(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ if (core_if->adp.probe_timer_values[0] == -1) { ++ core_if->adp.probe_timer_values[0] = val; ++ core_if->adp.probe_timer_values[1] = -1; ++ return 1; ++ } else { ++ core_if->adp.probe_timer_values[1] = ++ core_if->adp.probe_timer_values[0]; ++ core_if->adp.probe_timer_values[0] = val; ++ return 0; ++ } ++} ++ ++/** ++ * This function compares Ramp Timer values ++ */ ++static uint32_t compare_timer_values(dwc_otg_core_if_t * core_if) ++{ ++ uint32_t diff; ++ if (core_if->adp.probe_timer_values[0]>=core_if->adp.probe_timer_values[1]) ++ diff = core_if->adp.probe_timer_values[0]-core_if->adp.probe_timer_values[1]; ++ else ++ diff = core_if->adp.probe_timer_values[1]-core_if->adp.probe_timer_values[0]; ++ if(diff < 2) { ++ return 0; ++ } else { ++ return 1; ++ } ++} ++ ++/** ++ * This function handles ADP Probe Interrupts ++ */ ++static int32_t dwc_otg_adp_handle_prb_intr(dwc_otg_core_if_t * core_if, ++ uint32_t val) ++{ ++ adpctl_data_t adpctl = {.d32 = 0 }; ++ gpwrdn_data_t gpwrdn, temp; ++ adpctl.d32 = val; ++ ++ temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ core_if->adp.probe_counter++; ++ core_if->adp.gpwrdn = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ if (adpctl.b.rtim == 0 && !temp.b.idsts){ ++ DWC_PRINTF("RTIM value is 0\n"); ++ goto exit; ++ } ++ if (set_timer_value(core_if, adpctl.b.rtim) && ++ core_if->adp.initial_probe) { ++ core_if->adp.initial_probe = 0; ++ dwc_otg_adp_probe_stop(core_if); ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 1; ++ gpwrdn.b.pmuintsel = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); ++ ++ /* check which value is for device mode and which for Host mode */ ++ if (!temp.b.idsts) { /* considered host mode value is 0 */ ++ /* ++ * Turn on VBUS after initial ADP probe. ++ */ ++ core_if->op_state = A_HOST; ++ dwc_otg_enable_global_interrupts(core_if); ++ DWC_SPINUNLOCK(core_if->lock); ++ cil_hcd_start(core_if); ++ dwc_otg_adp_turnon_vbus(core_if); ++ DWC_SPINLOCK(core_if->lock); ++ } else { ++ /* ++ * Initiate SRP after initial ADP probe. ++ */ ++ dwc_otg_enable_global_interrupts(core_if); ++ dwc_otg_initiate_srp(core_if); ++ } ++ } else if (core_if->adp.probe_counter > 2){ ++ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ if (compare_timer_values(core_if)) { ++ DWC_PRINTF("Difference in timer values !!! \n"); ++// core_if->adp.attached = DWC_OTG_ADP_ATTACHED; ++ dwc_otg_adp_probe_stop(core_if); ++ ++ /* Power on the core */ ++ if (core_if->power_down == 2) { ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ } ++ ++ /* check which value is for device mode and which for Host mode */ ++ if (!temp.b.idsts) { /* considered host mode value is 0 */ ++ /* Disable Interrupt from Power Down Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, gpwrdn.d32, 0); ++ ++ /* ++ * Initialize the Core for Host mode. ++ */ ++ core_if->op_state = A_HOST; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_hcd_start(core_if); ++ } else { ++ gotgctl_data_t gotgctl; ++ /* Mask SRP detected interrupt from Power Down Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.srp_det_msk = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, gpwrdn.d32, 0); ++ ++ /* Disable Power Down Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, gpwrdn.d32, 0); ++ ++ /* ++ * Initialize the Core for Device mode. ++ */ ++ core_if->op_state = B_PERIPHERAL; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_pcd_start(core_if); ++ ++ gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl); ++ if (!gotgctl.b.bsesvld) { ++ dwc_otg_initiate_srp(core_if); ++ } ++ } ++ } ++ if (core_if->power_down == 2) { ++ if (gpwrdn.b.bsessvld) { ++ /* Mask SRP detected interrupt from Power Down Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.srp_det_msk = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /* Disable Power Down Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /* ++ * Initialize the Core for Device mode. ++ */ ++ core_if->op_state = B_PERIPHERAL; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_pcd_start(core_if); ++ } ++ } ++ } ++exit: ++ /* Clear interrupt */ ++ adpctl.d32 = dwc_otg_adp_read_reg(core_if); ++ adpctl.b.adp_prb_int = 1; ++ dwc_otg_adp_write_reg(core_if, adpctl.d32); ++ ++ return 0; ++} ++ ++/** ++ * This function hadles ADP Sense Interrupt ++ */ ++static int32_t dwc_otg_adp_handle_sns_intr(dwc_otg_core_if_t * core_if) ++{ ++ adpctl_data_t adpctl; ++ /* Stop ADP Sense timer */ ++ DWC_TIMER_CANCEL(core_if->adp.sense_timer); ++ ++ /* Restart ADP Sense timer */ ++ dwc_otg_adp_sense_timer_start(core_if); ++ ++ /* Clear interrupt */ ++ adpctl.d32 = dwc_otg_adp_read_reg(core_if); ++ adpctl.b.adp_sns_int = 1; ++ dwc_otg_adp_write_reg(core_if, adpctl.d32); ++ ++ return 0; ++} ++ ++/** ++ * This function handles ADP Probe Interrupts ++ */ ++static int32_t dwc_otg_adp_handle_prb_tmout_intr(dwc_otg_core_if_t * core_if, ++ uint32_t val) ++{ ++ adpctl_data_t adpctl = {.d32 = 0 }; ++ adpctl.d32 = val; ++ set_timer_value(core_if, adpctl.b.rtim); ++ ++ /* Clear interrupt */ ++ adpctl.d32 = dwc_otg_adp_read_reg(core_if); ++ adpctl.b.adp_tmout_int = 1; ++ dwc_otg_adp_write_reg(core_if, adpctl.d32); ++ ++ return 0; ++} ++ ++/** ++ * ADP Interrupt handler. ++ * ++ */ ++int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if) ++{ ++ int retval = 0; ++ adpctl_data_t adpctl = {.d32 = 0}; ++ ++ adpctl.d32 = dwc_otg_adp_read_reg(core_if); ++ DWC_PRINTF("ADPCTL = %08x\n",adpctl.d32); ++ ++ if (adpctl.b.adp_sns_int & adpctl.b.adp_sns_int_msk) { ++ DWC_PRINTF("ADP Sense interrupt\n"); ++ retval |= dwc_otg_adp_handle_sns_intr(core_if); ++ } ++ if (adpctl.b.adp_tmout_int & adpctl.b.adp_tmout_int_msk) { ++ DWC_PRINTF("ADP timeout interrupt\n"); ++ retval |= dwc_otg_adp_handle_prb_tmout_intr(core_if, adpctl.d32); ++ } ++ if (adpctl.b.adp_prb_int & adpctl.b.adp_prb_int_msk) { ++ DWC_PRINTF("ADP Probe interrupt\n"); ++ adpctl.b.adp_prb_int = 1; ++ retval |= dwc_otg_adp_handle_prb_intr(core_if, adpctl.d32); ++ } ++ ++// dwc_otg_adp_modify_reg(core_if, adpctl.d32, 0); ++ //dwc_otg_adp_write_reg(core_if, adpctl.d32); ++ DWC_PRINTF("RETURN FROM ADP ISR\n"); ++ ++ return retval; ++} ++ ++/** ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if) ++{ ++ ++#ifndef DWC_HOST_ONLY ++ hprt0_data_t hprt0; ++ gpwrdn_data_t gpwrdn; ++ DWC_DEBUGPL(DBG_ANY, "++ Power Down Logic Session Request Interrupt++\n"); ++ ++ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ /* check which value is for device mode and which for Host mode */ ++ if (!gpwrdn.b.idsts) { /* considered host mode value is 0 */ ++ DWC_PRINTF("SRP: Host mode\n"); ++ ++ if (core_if->adp_enable) { ++ dwc_otg_adp_probe_stop(core_if); ++ ++ /* Power on the core */ ++ if (core_if->power_down == 2) { ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ } ++ ++ core_if->op_state = A_HOST; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_hcd_start(core_if); ++ } ++ ++ /* Turn on the port power bit. */ ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtpwr = 1; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ ++ /* Start the Connection timer. So a message can be displayed ++ * if connect does not occur within 10 seconds. */ ++ cil_hcd_session_start(core_if); ++ } else { ++ DWC_PRINTF("SRP: Device mode %s\n", __FUNCTION__); ++ if (core_if->adp_enable) { ++ dwc_otg_adp_probe_stop(core_if); ++ ++ /* Power on the core */ ++ if (core_if->power_down == 2) { ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ } ++ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 0; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, ++ gpwrdn.d32); ++ ++ core_if->op_state = B_PERIPHERAL; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_pcd_start(core_if); ++ } ++ } ++#endif ++ return 1; ++} +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_adp.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_adp.h +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_adp.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_adp.h 2015-11-29 09:42:39.915098960 +0100 +@@ -0,0 +1,80 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.h $ ++ * $Revision: #7 $ ++ * $Date: 2011/10/24 $ ++ * $Change: 1871159 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++#ifndef __DWC_OTG_ADP_H__ ++#define __DWC_OTG_ADP_H__ ++ ++/** ++ * @file ++ * ++ * This file contains the Attach Detect Protocol interfaces and defines ++ * (functions) and structures for Linux. ++ * ++ */ ++ ++#define DWC_OTG_ADP_UNATTACHED 0 ++#define DWC_OTG_ADP_ATTACHED 1 ++#define DWC_OTG_ADP_UNKOWN 2 ++ ++typedef struct dwc_otg_adp { ++ uint32_t adp_started; ++ uint32_t initial_probe; ++ int32_t probe_timer_values[2]; ++ uint32_t probe_enabled; ++ uint32_t sense_enabled; ++ dwc_timer_t *sense_timer; ++ uint32_t sense_timer_started; ++ dwc_timer_t *vbuson_timer; ++ uint32_t vbuson_timer_started; ++ uint32_t attached; ++ uint32_t probe_counter; ++ uint32_t gpwrdn; ++} dwc_otg_adp_t; ++ ++/** ++ * Attach Detect Protocol functions ++ */ ++ ++extern void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value); ++extern uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if); ++extern uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if); ++extern uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if); ++extern uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if); ++extern uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if); ++extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host); ++extern void dwc_otg_adp_init(dwc_otg_core_if_t * core_if); ++extern void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if); ++extern int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if); ++extern int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if); ++ ++#endif //__DWC_OTG_ADP_H__ +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_attr.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_attr.c +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_attr.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_attr.c 2015-11-29 09:42:39.915098960 +0100 +@@ -0,0 +1,1210 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.c $ ++ * $Revision: #44 $ ++ * $Date: 2010/11/29 $ ++ * $Change: 1636033 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++/** @file ++ * ++ * The diagnostic interface will provide access to the controller for ++ * bringing up the hardware and testing. The Linux driver attributes ++ * feature will be used to provide the Linux Diagnostic ++ * Interface. These attributes are accessed through sysfs. ++ */ ++ ++/** @page "Linux Module Attributes" ++ * ++ * The Linux module attributes feature is used to provide the Linux ++ * Diagnostic Interface. These attributes are accessed through sysfs. ++ * The diagnostic interface will provide access to the controller for ++ * bringing up the hardware and testing. ++ ++ The following table shows the attributes. ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
Name Description Access
mode Returns the current mode: 0 for device mode, 1 for host mode Read
hnpcapable Gets or sets the "HNP-capable" bit in the Core USB Configuraton Register. ++ Read returns the current value. Read/Write
srpcapable Gets or sets the "SRP-capable" bit in the Core USB Configuraton Register. ++ Read returns the current value. Read/Write
hsic_connect Gets or sets the "HSIC-Connect" bit in the GLPMCFG Register. ++ Read returns the current value. Read/Write
inv_sel_hsic Gets or sets the "Invert Select HSIC" bit in the GLPMFG Register. ++ Read returns the current value. Read/Write
hnp Initiates the Host Negotiation Protocol. Read returns the status. Read/Write
srp Initiates the Session Request Protocol. Read returns the status. Read/Write
buspower Gets or sets the Power State of the bus (0 - Off or 1 - On) Read/Write
bussuspend Suspends the USB bus. Read/Write
busconnected Gets the connection status of the bus Read
gotgctl Gets or sets the Core Control Status Register. Read/Write
gusbcfg Gets or sets the Core USB Configuration Register Read/Write
grxfsiz Gets or sets the Receive FIFO Size Register Read/Write
gnptxfsiz Gets or sets the non-periodic Transmit Size Register Read/Write
gpvndctl Gets or sets the PHY Vendor Control Register Read/Write
ggpio Gets the value in the lower 16-bits of the General Purpose IO Register ++ or sets the upper 16 bits. Read/Write
guid Gets or sets the value of the User ID Register Read/Write
gsnpsid Gets the value of the Synopsys ID Regester Read
devspeed Gets or sets the device speed setting in the DCFG register Read/Write
enumspeed Gets the device enumeration Speed. Read
hptxfsiz Gets the value of the Host Periodic Transmit FIFO Read
hprt0 Gets or sets the value in the Host Port Control and Status Register Read/Write
regoffset Sets the register offset for the next Register Access Read/Write
regvalue Gets or sets the value of the register at the offset in the regoffset attribute. Read/Write
remote_wakeup On read, shows the status of Remote Wakeup. On write, initiates a remote ++ wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote ++ Wakeup signalling bit in the Device Control Register is set for 1 ++ milli-second. Read/Write
rem_wakeup_pwrdn On read, shows the status core - hibernated or not. On write, initiates ++ a remote wakeup of the device from Hibernation. Read/Write
mode_ch_tim_en This bit is used to enable or disable the host core to wait for 200 PHY ++ clock cycles at the end of Resume to change the opmode signal to the PHY to 00 ++ after Suspend or LPM. Read/Write
fr_interval On read, shows the value of HFIR Frame Interval. On write, dynamically ++ reload HFIR register during runtime. The application can write a value to this ++ register only after the Port Enable bit of the Host Port Control and Status ++ register (HPRT.PrtEnaPort) has been set Read/Write
disconnect_us On read, shows the status of disconnect_device_us. On write, sets disconnect_us ++ which causes soft disconnect for 100us. Applicable only for device mode of operation. Read/Write
regdump Dumps the contents of core registers. Read
spramdump Dumps the contents of core registers. Read
hcddump Dumps the current HCD state. Read
hcd_frrem Shows the average value of the Frame Remaining ++ field in the Host Frame Number/Frame Remaining register when an SOF interrupt ++ occurs. This can be used to determine the average interrupt latency. Also ++ shows the average Frame Remaining value for start_transfer and the "a" and ++ "b" sample points. The "a" and "b" sample points may be used during debugging ++ bto determine how long it takes to execute a section of the HCD code. Read
rd_reg_test Displays the time required to read the GNPTXFSIZ register many times ++ (the output shows the number of times the register is read). ++ Read
wr_reg_test Displays the time required to write the GNPTXFSIZ register many times ++ (the output shows the number of times the register is written). ++ Read
lpm_response Gets or sets lpm_response mode. Applicable only in device mode. ++ Write
sleep_status Shows sleep status of device. ++ Read
++ ++ Example usage: ++ To get the current mode: ++ cat /sys/devices/lm0/mode ++ ++ To power down the USB: ++ echo 0 > /sys/devices/lm0/buspower ++ */ ++ ++#include "dwc_otg_os_dep.h" ++#include "dwc_os.h" ++#include "dwc_otg_driver.h" ++#include "dwc_otg_attr.h" ++#include "dwc_otg_core_if.h" ++#include "dwc_otg_pcd_if.h" ++#include "dwc_otg_hcd_if.h" ++ ++/* ++ * MACROs for defining sysfs attribute ++ */ ++#ifdef LM_INTERFACE ++ ++#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \ ++{ \ ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \ ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \ ++ uint32_t val; \ ++ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \ ++ return sprintf (buf, "%s = 0x%x\n", _string_, val); \ ++} ++#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \ ++ const char *buf, size_t count) \ ++{ \ ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \ ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \ ++ uint32_t set = simple_strtoul(buf, NULL, 16); \ ++ dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\ ++ return count; \ ++} ++ ++#elif defined(PCI_INTERFACE) ++ ++#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \ ++{ \ ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \ ++ uint32_t val; \ ++ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \ ++ return sprintf (buf, "%s = 0x%x\n", _string_, val); \ ++} ++#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \ ++ const char *buf, size_t count) \ ++{ \ ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \ ++ uint32_t set = simple_strtoul(buf, NULL, 16); \ ++ dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\ ++ return count; \ ++} ++ ++#elif defined(PLATFORM_INTERFACE) ++ ++#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \ ++{ \ ++ struct platform_device *platform_dev = \ ++ container_of(_dev, struct platform_device, dev); \ ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \ ++ uint32_t val; \ ++ DWC_PRINTF("%s(%p) -> platform_dev %p, otg_dev %p\n", \ ++ __func__, _dev, platform_dev, otg_dev); \ ++ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \ ++ return sprintf (buf, "%s = 0x%x\n", _string_, val); \ ++} ++#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \ ++ const char *buf, size_t count) \ ++{ \ ++ struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \ ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \ ++ uint32_t set = simple_strtoul(buf, NULL, 16); \ ++ dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\ ++ return count; \ ++} ++#endif ++ ++/* ++ * MACROs for defining sysfs attribute for 32-bit registers ++ */ ++#ifdef LM_INTERFACE ++#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \ ++{ \ ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \ ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \ ++ uint32_t val; \ ++ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \ ++ return sprintf (buf, "%s = 0x%08x\n", _string_, val); \ ++} ++#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \ ++ const char *buf, size_t count) \ ++{ \ ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \ ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \ ++ uint32_t val = simple_strtoul(buf, NULL, 16); \ ++ dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \ ++ return count; \ ++} ++#elif defined(PCI_INTERFACE) ++#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \ ++{ \ ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \ ++ uint32_t val; \ ++ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \ ++ return sprintf (buf, "%s = 0x%08x\n", _string_, val); \ ++} ++#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \ ++ const char *buf, size_t count) \ ++{ \ ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \ ++ uint32_t val = simple_strtoul(buf, NULL, 16); \ ++ dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \ ++ return count; \ ++} ++ ++#elif defined(PLATFORM_INTERFACE) ++#include "dwc_otg_dbg.h" ++#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \ ++{ \ ++ struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \ ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \ ++ uint32_t val; \ ++ DWC_PRINTF("%s(%p) -> platform_dev %p, otg_dev %p\n", \ ++ __func__, _dev, platform_dev, otg_dev); \ ++ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \ ++ return sprintf (buf, "%s = 0x%08x\n", _string_, val); \ ++} ++#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \ ++ const char *buf, size_t count) \ ++{ \ ++ struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \ ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \ ++ uint32_t val = simple_strtoul(buf, NULL, 16); \ ++ dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \ ++ return count; \ ++} ++ ++#endif ++ ++#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_string_) \ ++DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \ ++DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \ ++DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store); ++ ++#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_string_) \ ++DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \ ++DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL); ++ ++#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \ ++DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \ ++DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \ ++DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store); ++ ++#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \ ++DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \ ++DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL); ++ ++/** @name Functions for Show/Store of Attributes */ ++/**@{*/ ++ ++/** ++ * Helper function returning the otg_device structure of the given device ++ */ ++static dwc_otg_device_t *dwc_otg_drvdev(struct device *_dev) ++{ ++ dwc_otg_device_t *otg_dev; ++ DWC_OTG_GETDRVDEV(otg_dev, _dev); ++ return otg_dev; ++} ++ ++/** ++ * Show the register offset of the Register Access. ++ */ ++static ssize_t regoffset_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ return snprintf(buf, sizeof("0xFFFFFFFF\n") + 1, "0x%08x\n", ++ otg_dev->os_dep.reg_offset); ++} ++ ++/** ++ * Set the register offset for the next Register Access Read/Write ++ */ ++static ssize_t regoffset_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ uint32_t offset = simple_strtoul(buf, NULL, 16); ++#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE) ++ if (offset < SZ_256K) { ++#elif defined(PCI_INTERFACE) ++ if (offset < 0x00040000) { ++#endif ++ otg_dev->os_dep.reg_offset = offset; ++ } else { ++ dev_err(_dev, "invalid offset\n"); ++ } ++ ++ return count; ++} ++ ++DEVICE_ATTR(regoffset, S_IRUGO | S_IWUSR, regoffset_show, regoffset_store); ++ ++/** ++ * Show the value of the register at the offset in the reg_offset ++ * attribute. ++ */ ++static ssize_t regvalue_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ uint32_t val; ++ volatile uint32_t *addr; ++ ++ if (otg_dev->os_dep.reg_offset != 0xFFFFFFFF && 0 != otg_dev->os_dep.base) { ++ /* Calculate the address */ ++ addr = (uint32_t *) (otg_dev->os_dep.reg_offset + ++ (uint8_t *) otg_dev->os_dep.base); ++ val = DWC_READ_REG32(addr); ++ return snprintf(buf, ++ sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n") + 1, ++ "Reg@0x%06x = 0x%08x\n", otg_dev->os_dep.reg_offset, ++ val); ++ } else { ++ dev_err(_dev, "Invalid offset (0x%0x)\n", otg_dev->os_dep.reg_offset); ++ return sprintf(buf, "invalid offset\n"); ++ } ++} ++ ++/** ++ * Store the value in the register at the offset in the reg_offset ++ * attribute. ++ * ++ */ ++static ssize_t regvalue_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ volatile uint32_t *addr; ++ uint32_t val = simple_strtoul(buf, NULL, 16); ++ //dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val); ++ if (otg_dev->os_dep.reg_offset != 0xFFFFFFFF && 0 != otg_dev->os_dep.base) { ++ /* Calculate the address */ ++ addr = (uint32_t *) (otg_dev->os_dep.reg_offset + ++ (uint8_t *) otg_dev->os_dep.base); ++ DWC_WRITE_REG32(addr, val); ++ } else { ++ dev_err(_dev, "Invalid Register Offset (0x%08x)\n", ++ otg_dev->os_dep.reg_offset); ++ } ++ return count; ++} ++ ++DEVICE_ATTR(regvalue, S_IRUGO | S_IWUSR, regvalue_show, regvalue_store); ++ ++/* ++ * Attributes ++ */ ++DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode, "Mode"); ++DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable, "HNPCapable"); ++DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable, "SRPCapable"); ++DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hsic_connect, "HSIC Connect"); ++DWC_OTG_DEVICE_ATTR_BITFIELD_RW(inv_sel_hsic, "Invert Select HSIC"); ++ ++//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode"); ++//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode"); ++DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected, "Bus Connected"); ++ ++DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl, 0, "GOTGCTL"); ++DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg, ++ &(otg_dev->core_if->core_global_regs->gusbcfg), ++ "GUSBCFG"); ++DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz, ++ &(otg_dev->core_if->core_global_regs->grxfsiz), ++ "GRXFSIZ"); ++DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz, ++ &(otg_dev->core_if->core_global_regs->gnptxfsiz), ++ "GNPTXFSIZ"); ++DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl, ++ &(otg_dev->core_if->core_global_regs->gpvndctl), ++ "GPVNDCTL"); ++DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio, ++ &(otg_dev->core_if->core_global_regs->ggpio), ++ "GGPIO"); ++DWC_OTG_DEVICE_ATTR_REG32_RW(guid, &(otg_dev->core_if->core_global_regs->guid), ++ "GUID"); ++DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid, ++ &(otg_dev->core_if->core_global_regs->gsnpsid), ++ "GSNPSID"); ++DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed, "Device Speed"); ++DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed, "Device Enumeration Speed"); ++ ++DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz, ++ &(otg_dev->core_if->core_global_regs->hptxfsiz), ++ "HPTXFSIZ"); ++DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0, otg_dev->core_if->host_if->hprt0, "HPRT0"); ++ ++/** ++ * @todo Add code to initiate the HNP. ++ */ ++/** ++ * Show the HNP status bit ++ */ ++static ssize_t hnp_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ return sprintf(buf, "HstNegScs = 0x%x\n", ++ dwc_otg_get_hnpstatus(otg_dev->core_if)); ++} ++ ++/** ++ * Set the HNP Request bit ++ */ ++static ssize_t hnp_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ uint32_t in = simple_strtoul(buf, NULL, 16); ++ dwc_otg_set_hnpreq(otg_dev->core_if, in); ++ return count; ++} ++ ++DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store); ++ ++/** ++ * @todo Add code to initiate the SRP. ++ */ ++/** ++ * Show the SRP status bit ++ */ ++static ssize_t srp_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++#ifndef DWC_HOST_ONLY ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ return sprintf(buf, "SesReqScs = 0x%x\n", ++ dwc_otg_get_srpstatus(otg_dev->core_if)); ++#else ++ return sprintf(buf, "Host Only Mode!\n"); ++#endif ++} ++ ++/** ++ * Set the SRP Request bit ++ */ ++static ssize_t srp_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++#ifndef DWC_HOST_ONLY ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ dwc_otg_pcd_initiate_srp(otg_dev->pcd); ++#endif ++ return count; ++} ++ ++DEVICE_ATTR(srp, 0644, srp_show, srp_store); ++ ++/** ++ * @todo Need to do more for power on/off? ++ */ ++/** ++ * Show the Bus Power status ++ */ ++static ssize_t buspower_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ return sprintf(buf, "Bus Power = 0x%x\n", ++ dwc_otg_get_prtpower(otg_dev->core_if)); ++} ++ ++/** ++ * Set the Bus Power status ++ */ ++static ssize_t buspower_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ uint32_t on = simple_strtoul(buf, NULL, 16); ++ dwc_otg_set_prtpower(otg_dev->core_if, on); ++ return count; ++} ++ ++DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store); ++ ++/** ++ * @todo Need to do more for suspend? ++ */ ++/** ++ * Show the Bus Suspend status ++ */ ++static ssize_t bussuspend_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ return sprintf(buf, "Bus Suspend = 0x%x\n", ++ dwc_otg_get_prtsuspend(otg_dev->core_if)); ++} ++ ++/** ++ * Set the Bus Suspend status ++ */ ++static ssize_t bussuspend_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ uint32_t in = simple_strtoul(buf, NULL, 16); ++ dwc_otg_set_prtsuspend(otg_dev->core_if, in); ++ return count; ++} ++ ++DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store); ++ ++/** ++ * Show the Mode Change Ready Timer status ++ */ ++static ssize_t mode_ch_tim_en_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ return sprintf(buf, "Mode Change Ready Timer Enable = 0x%x\n", ++ dwc_otg_get_mode_ch_tim(otg_dev->core_if)); ++} ++ ++/** ++ * Set the Mode Change Ready Timer status ++ */ ++static ssize_t mode_ch_tim_en_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ uint32_t in = simple_strtoul(buf, NULL, 16); ++ dwc_otg_set_mode_ch_tim(otg_dev->core_if, in); ++ return count; ++} ++ ++DEVICE_ATTR(mode_ch_tim_en, 0644, mode_ch_tim_en_show, mode_ch_tim_en_store); ++ ++/** ++ * Show the value of HFIR Frame Interval bitfield ++ */ ++static ssize_t fr_interval_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ return sprintf(buf, "Frame Interval = 0x%x\n", ++ dwc_otg_get_fr_interval(otg_dev->core_if)); ++} ++ ++/** ++ * Set the HFIR Frame Interval value ++ */ ++static ssize_t fr_interval_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ uint32_t in = simple_strtoul(buf, NULL, 10); ++ dwc_otg_set_fr_interval(otg_dev->core_if, in); ++ return count; ++} ++ ++DEVICE_ATTR(fr_interval, 0644, fr_interval_show, fr_interval_store); ++ ++/** ++ * Show the status of Remote Wakeup. ++ */ ++static ssize_t remote_wakeup_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++#ifndef DWC_HOST_ONLY ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ ++ return sprintf(buf, ++ "Remote Wakeup Sig = %d Enabled = %d LPM Remote Wakeup = %d\n", ++ dwc_otg_get_remotewakesig(otg_dev->core_if), ++ dwc_otg_pcd_get_rmwkup_enable(otg_dev->pcd), ++ dwc_otg_get_lpm_remotewakeenabled(otg_dev->core_if)); ++#else ++ return sprintf(buf, "Host Only Mode!\n"); ++#endif /* DWC_HOST_ONLY */ ++} ++ ++/** ++ * Initiate a remote wakeup of the host. The Device control register ++ * Remote Wakeup Signal bit is written if the PCD Remote wakeup enable ++ * flag is set. ++ * ++ */ ++static ssize_t remote_wakeup_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++#ifndef DWC_HOST_ONLY ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ uint32_t val = simple_strtoul(buf, NULL, 16); ++ ++ if (val & 1) { ++ dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1); ++ } else { ++ dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0); ++ } ++#endif /* DWC_HOST_ONLY */ ++ return count; ++} ++ ++DEVICE_ATTR(remote_wakeup, S_IRUGO | S_IWUSR, remote_wakeup_show, ++ remote_wakeup_store); ++ ++/** ++ * Show the whether core is hibernated or not. ++ */ ++static ssize_t rem_wakeup_pwrdn_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++#ifndef DWC_HOST_ONLY ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ ++ if (dwc_otg_get_core_state(otg_dev->core_if)) { ++ DWC_PRINTF("Core is in hibernation\n"); ++ } else { ++ DWC_PRINTF("Core is not in hibernation\n"); ++ } ++#endif /* DWC_HOST_ONLY */ ++ return 0; ++} ++ ++extern int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if, ++ int rem_wakeup, int reset); ++ ++/** ++ * Initiate a remote wakeup of the device to exit from hibernation. ++ */ ++static ssize_t rem_wakeup_pwrdn_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++#ifndef DWC_HOST_ONLY ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ dwc_otg_device_hibernation_restore(otg_dev->core_if, 1, 0); ++#endif ++ return count; ++} ++ ++DEVICE_ATTR(rem_wakeup_pwrdn, S_IRUGO | S_IWUSR, rem_wakeup_pwrdn_show, ++ rem_wakeup_pwrdn_store); ++ ++static ssize_t disconnect_us(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ ++#ifndef DWC_HOST_ONLY ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ uint32_t val = simple_strtoul(buf, NULL, 16); ++ DWC_PRINTF("The Passed value is %04x\n", val); ++ ++ dwc_otg_pcd_disconnect_us(otg_dev->pcd, 50); ++ ++#endif /* DWC_HOST_ONLY */ ++ return count; ++} ++ ++DEVICE_ATTR(disconnect_us, S_IWUSR, 0, disconnect_us); ++ ++/** ++ * Dump global registers and either host or device registers (depending on the ++ * current mode of the core). ++ */ ++static ssize_t regdump_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ ++ dwc_otg_dump_global_registers(otg_dev->core_if); ++ if (dwc_otg_is_host_mode(otg_dev->core_if)) { ++ dwc_otg_dump_host_registers(otg_dev->core_if); ++ } else { ++ dwc_otg_dump_dev_registers(otg_dev->core_if); ++ ++ } ++ return sprintf(buf, "Register Dump\n"); ++} ++ ++DEVICE_ATTR(regdump, S_IRUGO, regdump_show, 0); ++ ++/** ++ * Dump global registers and either host or device registers (depending on the ++ * current mode of the core). ++ */ ++static ssize_t spramdump_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ ++ //dwc_otg_dump_spram(otg_dev->core_if); ++ ++ return sprintf(buf, "SPRAM Dump\n"); ++} ++ ++DEVICE_ATTR(spramdump, S_IRUGO, spramdump_show, 0); ++ ++/** ++ * Dump the current hcd state. ++ */ ++static ssize_t hcddump_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++#ifndef DWC_DEVICE_ONLY ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ dwc_otg_hcd_dump_state(otg_dev->hcd); ++#endif /* DWC_DEVICE_ONLY */ ++ return sprintf(buf, "HCD Dump\n"); ++} ++ ++DEVICE_ATTR(hcddump, S_IRUGO, hcddump_show, 0); ++ ++/** ++ * Dump the average frame remaining at SOF. This can be used to ++ * determine average interrupt latency. Frame remaining is also shown for ++ * start transfer and two additional sample points. ++ */ ++static ssize_t hcd_frrem_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++#ifndef DWC_DEVICE_ONLY ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ ++ dwc_otg_hcd_dump_frrem(otg_dev->hcd); ++#endif /* DWC_DEVICE_ONLY */ ++ return sprintf(buf, "HCD Dump Frame Remaining\n"); ++} ++ ++DEVICE_ATTR(hcd_frrem, S_IRUGO, hcd_frrem_show, 0); ++ ++/** ++ * Displays the time required to read the GNPTXFSIZ register many times (the ++ * output shows the number of times the register is read). ++ */ ++#define RW_REG_COUNT 10000000 ++#define MSEC_PER_JIFFIE 1000/HZ ++static ssize_t rd_reg_test_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ int i; ++ int time; ++ int start_jiffies; ++ ++ printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n", ++ HZ, MSEC_PER_JIFFIE, loops_per_jiffy); ++ start_jiffies = jiffies; ++ for (i = 0; i < RW_REG_COUNT; i++) { ++ dwc_otg_get_gnptxfsiz(otg_dev->core_if); ++ } ++ time = jiffies - start_jiffies; ++ return sprintf(buf, ++ "Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n", ++ RW_REG_COUNT, time * MSEC_PER_JIFFIE, time); ++} ++ ++DEVICE_ATTR(rd_reg_test, S_IRUGO, rd_reg_test_show, 0); ++ ++/** ++ * Displays the time required to write the GNPTXFSIZ register many times (the ++ * output shows the number of times the register is written). ++ */ ++static ssize_t wr_reg_test_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ uint32_t reg_val; ++ int i; ++ int time; ++ int start_jiffies; ++ ++ printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n", ++ HZ, MSEC_PER_JIFFIE, loops_per_jiffy); ++ reg_val = dwc_otg_get_gnptxfsiz(otg_dev->core_if); ++ start_jiffies = jiffies; ++ for (i = 0; i < RW_REG_COUNT; i++) { ++ dwc_otg_set_gnptxfsiz(otg_dev->core_if, reg_val); ++ } ++ time = jiffies - start_jiffies; ++ return sprintf(buf, ++ "Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n", ++ RW_REG_COUNT, time * MSEC_PER_JIFFIE, time); ++} ++ ++DEVICE_ATTR(wr_reg_test, S_IRUGO, wr_reg_test_show, 0); ++ ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ ++/** ++* Show the lpm_response attribute. ++*/ ++static ssize_t lpmresp_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ ++ if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if)) ++ return sprintf(buf, "** LPM is DISABLED **\n"); ++ ++ if (!dwc_otg_is_device_mode(otg_dev->core_if)) { ++ return sprintf(buf, "** Current mode is not device mode\n"); ++ } ++ return sprintf(buf, "lpm_response = %d\n", ++ dwc_otg_get_lpmresponse(otg_dev->core_if)); ++} ++ ++/** ++* Store the lpm_response attribute. ++*/ ++static ssize_t lpmresp_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ uint32_t val = simple_strtoul(buf, NULL, 16); ++ ++ if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if)) { ++ return 0; ++ } ++ ++ if (!dwc_otg_is_device_mode(otg_dev->core_if)) { ++ return 0; ++ } ++ ++ dwc_otg_set_lpmresponse(otg_dev->core_if, val); ++ return count; ++} ++ ++DEVICE_ATTR(lpm_response, S_IRUGO | S_IWUSR, lpmresp_show, lpmresp_store); ++ ++/** ++* Show the sleep_status attribute. ++*/ ++static ssize_t sleepstatus_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ return sprintf(buf, "Sleep Status = %d\n", ++ dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if)); ++} ++ ++/** ++ * Store the sleep_status attribure. ++ */ ++static ssize_t sleepstatus_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ dwc_otg_core_if_t *core_if = otg_dev->core_if; ++ ++ if (dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if)) { ++ if (dwc_otg_is_host_mode(core_if)) { ++ ++ DWC_PRINTF("Host initiated resume\n"); ++ dwc_otg_set_prtresume(otg_dev->core_if, 1); ++ } ++ } ++ ++ return count; ++} ++ ++DEVICE_ATTR(sleep_status, S_IRUGO | S_IWUSR, sleepstatus_show, ++ sleepstatus_store); ++ ++#endif /* CONFIG_USB_DWC_OTG_LPM_ENABLE */ ++ ++/**@}*/ ++ ++/** ++ * Create the device files ++ */ ++void dwc_otg_attr_create( ++#ifdef LM_INTERFACE ++ struct lm_device *dev ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *dev ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *dev ++#endif ++ ) ++{ ++ int error; ++ ++ error = device_create_file(&dev->dev, &dev_attr_regoffset); ++ error = device_create_file(&dev->dev, &dev_attr_regvalue); ++ error = device_create_file(&dev->dev, &dev_attr_mode); ++ error = device_create_file(&dev->dev, &dev_attr_hnpcapable); ++ error = device_create_file(&dev->dev, &dev_attr_srpcapable); ++ error = device_create_file(&dev->dev, &dev_attr_hsic_connect); ++ error = device_create_file(&dev->dev, &dev_attr_inv_sel_hsic); ++ error = device_create_file(&dev->dev, &dev_attr_hnp); ++ error = device_create_file(&dev->dev, &dev_attr_srp); ++ error = device_create_file(&dev->dev, &dev_attr_buspower); ++ error = device_create_file(&dev->dev, &dev_attr_bussuspend); ++ error = device_create_file(&dev->dev, &dev_attr_mode_ch_tim_en); ++ error = device_create_file(&dev->dev, &dev_attr_fr_interval); ++ error = device_create_file(&dev->dev, &dev_attr_busconnected); ++ error = device_create_file(&dev->dev, &dev_attr_gotgctl); ++ error = device_create_file(&dev->dev, &dev_attr_gusbcfg); ++ error = device_create_file(&dev->dev, &dev_attr_grxfsiz); ++ error = device_create_file(&dev->dev, &dev_attr_gnptxfsiz); ++ error = device_create_file(&dev->dev, &dev_attr_gpvndctl); ++ error = device_create_file(&dev->dev, &dev_attr_ggpio); ++ error = device_create_file(&dev->dev, &dev_attr_guid); ++ error = device_create_file(&dev->dev, &dev_attr_gsnpsid); ++ error = device_create_file(&dev->dev, &dev_attr_devspeed); ++ error = device_create_file(&dev->dev, &dev_attr_enumspeed); ++ error = device_create_file(&dev->dev, &dev_attr_hptxfsiz); ++ error = device_create_file(&dev->dev, &dev_attr_hprt0); ++ error = device_create_file(&dev->dev, &dev_attr_remote_wakeup); ++ error = device_create_file(&dev->dev, &dev_attr_rem_wakeup_pwrdn); ++ error = device_create_file(&dev->dev, &dev_attr_disconnect_us); ++ error = device_create_file(&dev->dev, &dev_attr_regdump); ++ error = device_create_file(&dev->dev, &dev_attr_spramdump); ++ error = device_create_file(&dev->dev, &dev_attr_hcddump); ++ error = device_create_file(&dev->dev, &dev_attr_hcd_frrem); ++ error = device_create_file(&dev->dev, &dev_attr_rd_reg_test); ++ error = device_create_file(&dev->dev, &dev_attr_wr_reg_test); ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ error = device_create_file(&dev->dev, &dev_attr_lpm_response); ++ error = device_create_file(&dev->dev, &dev_attr_sleep_status); ++#endif ++} ++ ++/** ++ * Remove the device files ++ */ ++void dwc_otg_attr_remove( ++#ifdef LM_INTERFACE ++ struct lm_device *dev ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *dev ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *dev ++#endif ++ ) ++{ ++ device_remove_file(&dev->dev, &dev_attr_regoffset); ++ device_remove_file(&dev->dev, &dev_attr_regvalue); ++ device_remove_file(&dev->dev, &dev_attr_mode); ++ device_remove_file(&dev->dev, &dev_attr_hnpcapable); ++ device_remove_file(&dev->dev, &dev_attr_srpcapable); ++ device_remove_file(&dev->dev, &dev_attr_hsic_connect); ++ device_remove_file(&dev->dev, &dev_attr_inv_sel_hsic); ++ device_remove_file(&dev->dev, &dev_attr_hnp); ++ device_remove_file(&dev->dev, &dev_attr_srp); ++ device_remove_file(&dev->dev, &dev_attr_buspower); ++ device_remove_file(&dev->dev, &dev_attr_bussuspend); ++ device_remove_file(&dev->dev, &dev_attr_mode_ch_tim_en); ++ device_remove_file(&dev->dev, &dev_attr_fr_interval); ++ device_remove_file(&dev->dev, &dev_attr_busconnected); ++ device_remove_file(&dev->dev, &dev_attr_gotgctl); ++ device_remove_file(&dev->dev, &dev_attr_gusbcfg); ++ device_remove_file(&dev->dev, &dev_attr_grxfsiz); ++ device_remove_file(&dev->dev, &dev_attr_gnptxfsiz); ++ device_remove_file(&dev->dev, &dev_attr_gpvndctl); ++ device_remove_file(&dev->dev, &dev_attr_ggpio); ++ device_remove_file(&dev->dev, &dev_attr_guid); ++ device_remove_file(&dev->dev, &dev_attr_gsnpsid); ++ device_remove_file(&dev->dev, &dev_attr_devspeed); ++ device_remove_file(&dev->dev, &dev_attr_enumspeed); ++ device_remove_file(&dev->dev, &dev_attr_hptxfsiz); ++ device_remove_file(&dev->dev, &dev_attr_hprt0); ++ device_remove_file(&dev->dev, &dev_attr_remote_wakeup); ++ device_remove_file(&dev->dev, &dev_attr_rem_wakeup_pwrdn); ++ device_remove_file(&dev->dev, &dev_attr_disconnect_us); ++ device_remove_file(&dev->dev, &dev_attr_regdump); ++ device_remove_file(&dev->dev, &dev_attr_spramdump); ++ device_remove_file(&dev->dev, &dev_attr_hcddump); ++ device_remove_file(&dev->dev, &dev_attr_hcd_frrem); ++ device_remove_file(&dev->dev, &dev_attr_rd_reg_test); ++ device_remove_file(&dev->dev, &dev_attr_wr_reg_test); ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ device_remove_file(&dev->dev, &dev_attr_lpm_response); ++ device_remove_file(&dev->dev, &dev_attr_sleep_status); ++#endif ++} +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_attr.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_attr.h +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_attr.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_attr.h 2015-11-29 09:42:39.915098960 +0100 +@@ -0,0 +1,89 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.h $ ++ * $Revision: #13 $ ++ * $Date: 2010/06/21 $ ++ * $Change: 1532021 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++#if !defined(__DWC_OTG_ATTR_H__) ++#define __DWC_OTG_ATTR_H__ ++ ++/** @file ++ * This file contains the interface to the Linux device attributes. ++ */ ++extern struct device_attribute dev_attr_regoffset; ++extern struct device_attribute dev_attr_regvalue; ++ ++extern struct device_attribute dev_attr_mode; ++extern struct device_attribute dev_attr_hnpcapable; ++extern struct device_attribute dev_attr_srpcapable; ++extern struct device_attribute dev_attr_hnp; ++extern struct device_attribute dev_attr_srp; ++extern struct device_attribute dev_attr_buspower; ++extern struct device_attribute dev_attr_bussuspend; ++extern struct device_attribute dev_attr_mode_ch_tim_en; ++extern struct device_attribute dev_attr_fr_interval; ++extern struct device_attribute dev_attr_busconnected; ++extern struct device_attribute dev_attr_gotgctl; ++extern struct device_attribute dev_attr_gusbcfg; ++extern struct device_attribute dev_attr_grxfsiz; ++extern struct device_attribute dev_attr_gnptxfsiz; ++extern struct device_attribute dev_attr_gpvndctl; ++extern struct device_attribute dev_attr_ggpio; ++extern struct device_attribute dev_attr_guid; ++extern struct device_attribute dev_attr_gsnpsid; ++extern struct device_attribute dev_attr_devspeed; ++extern struct device_attribute dev_attr_enumspeed; ++extern struct device_attribute dev_attr_hptxfsiz; ++extern struct device_attribute dev_attr_hprt0; ++#ifdef CONFIG_USB_DWC_OTG_LPM ++extern struct device_attribute dev_attr_lpm_response; ++extern struct device_attribute devi_attr_sleep_status; ++#endif ++ ++void dwc_otg_attr_create( ++#ifdef LM_INTERFACE ++ struct lm_device *dev ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *dev ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *dev ++#endif ++ ); ++ ++void dwc_otg_attr_remove( ++#ifdef LM_INTERFACE ++ struct lm_device *dev ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *dev ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *dev ++#endif ++ ); ++#endif +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_cfi.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cfi.c +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_cfi.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cfi.c 2015-11-29 09:42:39.915098960 +0100 +@@ -0,0 +1,1876 @@ ++/* ========================================================================== ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++/** @file ++ * ++ * This file contains the most of the CFI(Core Feature Interface) ++ * implementation for the OTG. ++ */ ++ ++#ifdef DWC_UTE_CFI ++ ++#include "dwc_otg_pcd.h" ++#include "dwc_otg_cfi.h" ++ ++/** This definition should actually migrate to the Portability Library */ ++#define DWC_CONSTANT_CPU_TO_LE16(x) (x) ++ ++extern dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex); ++ ++static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen); ++static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen, ++ struct dwc_otg_pcd *pcd, ++ struct cfi_usb_ctrlrequest *ctrl_req); ++static int cfi_set_feature_value(struct dwc_otg_pcd *pcd); ++static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd, ++ struct cfi_usb_ctrlrequest *req); ++static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd, ++ struct cfi_usb_ctrlrequest *req); ++static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd, ++ struct cfi_usb_ctrlrequest *req); ++static int cfi_preproc_reset(struct dwc_otg_pcd *pcd, ++ struct cfi_usb_ctrlrequest *req); ++static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep); ++ ++static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if); ++static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue); ++static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue); ++ ++static uint8_t resize_fifos(dwc_otg_core_if_t * core_if); ++ ++/** This is the header of the all features descriptor */ ++static cfi_all_features_header_t all_props_desc_header = { ++ .wVersion = DWC_CONSTANT_CPU_TO_LE16(0x100), ++ .wCoreID = DWC_CONSTANT_CPU_TO_LE16(CFI_CORE_ID_OTG), ++ .wNumFeatures = DWC_CONSTANT_CPU_TO_LE16(9), ++}; ++ ++/** This is an array of statically allocated feature descriptors */ ++static cfi_feature_desc_header_t prop_descs[] = { ++ ++ /* FT_ID_DMA_MODE */ ++ { ++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_MODE), ++ .bmAttributes = CFI_FEATURE_ATTR_RW, ++ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(1), ++ }, ++ ++ /* FT_ID_DMA_BUFFER_SETUP */ ++ { ++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFFER_SETUP), ++ .bmAttributes = CFI_FEATURE_ATTR_RW, ++ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6), ++ }, ++ ++ /* FT_ID_DMA_BUFF_ALIGN */ ++ { ++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFF_ALIGN), ++ .bmAttributes = CFI_FEATURE_ATTR_RW, ++ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2), ++ }, ++ ++ /* FT_ID_DMA_CONCAT_SETUP */ ++ { ++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CONCAT_SETUP), ++ .bmAttributes = CFI_FEATURE_ATTR_RW, ++ //.wDataLength = DWC_CONSTANT_CPU_TO_LE16(6), ++ }, ++ ++ /* FT_ID_DMA_CIRCULAR */ ++ { ++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CIRCULAR), ++ .bmAttributes = CFI_FEATURE_ATTR_RW, ++ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6), ++ }, ++ ++ /* FT_ID_THRESHOLD_SETUP */ ++ { ++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_THRESHOLD_SETUP), ++ .bmAttributes = CFI_FEATURE_ATTR_RW, ++ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6), ++ }, ++ ++ /* FT_ID_DFIFO_DEPTH */ ++ { ++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DFIFO_DEPTH), ++ .bmAttributes = CFI_FEATURE_ATTR_RO, ++ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2), ++ }, ++ ++ /* FT_ID_TX_FIFO_DEPTH */ ++ { ++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_TX_FIFO_DEPTH), ++ .bmAttributes = CFI_FEATURE_ATTR_RW, ++ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2), ++ }, ++ ++ /* FT_ID_RX_FIFO_DEPTH */ ++ { ++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_RX_FIFO_DEPTH), ++ .bmAttributes = CFI_FEATURE_ATTR_RW, ++ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2), ++ } ++}; ++ ++/** The table of feature names */ ++cfi_string_t prop_name_table[] = { ++ {FT_ID_DMA_MODE, "dma_mode"}, ++ {FT_ID_DMA_BUFFER_SETUP, "buffer_setup"}, ++ {FT_ID_DMA_BUFF_ALIGN, "buffer_align"}, ++ {FT_ID_DMA_CONCAT_SETUP, "concat_setup"}, ++ {FT_ID_DMA_CIRCULAR, "buffer_circular"}, ++ {FT_ID_THRESHOLD_SETUP, "threshold_setup"}, ++ {FT_ID_DFIFO_DEPTH, "dfifo_depth"}, ++ {FT_ID_TX_FIFO_DEPTH, "txfifo_depth"}, ++ {FT_ID_RX_FIFO_DEPTH, "rxfifo_depth"}, ++ {} ++}; ++ ++/************************************************************************/ ++ ++/** ++ * Returns the name of the feature by its ID ++ * or NULL if no featute ID matches. ++ * ++ */ ++const uint8_t *get_prop_name(uint16_t prop_id, int *len) ++{ ++ cfi_string_t *pstr; ++ *len = 0; ++ ++ for (pstr = prop_name_table; pstr && pstr->s; pstr++) { ++ if (pstr->id == prop_id) { ++ *len = DWC_STRLEN(pstr->s); ++ return pstr->s; ++ } ++ } ++ return NULL; ++} ++ ++/** ++ * This function handles all CFI specific control requests. ++ * ++ * Return a negative value to stall the DCE. ++ */ ++int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl) ++{ ++ int retval = 0; ++ dwc_otg_pcd_ep_t *ep = NULL; ++ cfiobject_t *cfi = pcd->cfi; ++ struct dwc_otg_core_if *coreif = GET_CORE_IF(pcd); ++ uint16_t wLen = DWC_LE16_TO_CPU(&ctrl->wLength); ++ uint16_t wValue = DWC_LE16_TO_CPU(&ctrl->wValue); ++ uint16_t wIndex = DWC_LE16_TO_CPU(&ctrl->wIndex); ++ uint32_t regaddr = 0; ++ uint32_t regval = 0; ++ ++ /* Save this Control Request in the CFI object. ++ * The data field will be assigned in the data stage completion CB function. ++ */ ++ cfi->ctrl_req = *ctrl; ++ cfi->ctrl_req.data = NULL; ++ ++ cfi->need_gadget_att = 0; ++ cfi->need_status_in_complete = 0; ++ ++ switch (ctrl->bRequest) { ++ case VEN_CORE_GET_FEATURES: ++ retval = cfi_core_features_buf(cfi->buf_in.buf, CFI_IN_BUF_LEN); ++ if (retval >= 0) { ++ //dump_msg(cfi->buf_in.buf, retval); ++ ep = &pcd->ep0; ++ ++ retval = min((uint16_t) retval, wLen); ++ /* Transfer this buffer to the host through the EP0-IN EP */ ++ ep->dwc_ep.dma_addr = cfi->buf_in.addr; ++ ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf; ++ ep->dwc_ep.xfer_buff = cfi->buf_in.buf; ++ ep->dwc_ep.xfer_len = retval; ++ ep->dwc_ep.xfer_count = 0; ++ ep->dwc_ep.sent_zlp = 0; ++ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len; ++ ++ pcd->ep0_pending = 1; ++ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep); ++ } ++ retval = 0; ++ break; ++ ++ case VEN_CORE_GET_FEATURE: ++ CFI_INFO("VEN_CORE_GET_FEATURE\n"); ++ retval = cfi_get_feature_value(cfi->buf_in.buf, CFI_IN_BUF_LEN, ++ pcd, ctrl); ++ if (retval >= 0) { ++ ep = &pcd->ep0; ++ ++ retval = min((uint16_t) retval, wLen); ++ /* Transfer this buffer to the host through the EP0-IN EP */ ++ ep->dwc_ep.dma_addr = cfi->buf_in.addr; ++ ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf; ++ ep->dwc_ep.xfer_buff = cfi->buf_in.buf; ++ ep->dwc_ep.xfer_len = retval; ++ ep->dwc_ep.xfer_count = 0; ++ ep->dwc_ep.sent_zlp = 0; ++ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len; ++ ++ pcd->ep0_pending = 1; ++ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep); ++ } ++ CFI_INFO("VEN_CORE_GET_FEATURE=%d\n", retval); ++ dump_msg(cfi->buf_in.buf, retval); ++ break; ++ ++ case VEN_CORE_SET_FEATURE: ++ CFI_INFO("VEN_CORE_SET_FEATURE\n"); ++ /* Set up an XFER to get the data stage of the control request, ++ * which is the new value of the feature to be modified. ++ */ ++ ep = &pcd->ep0; ++ ep->dwc_ep.is_in = 0; ++ ep->dwc_ep.dma_addr = cfi->buf_out.addr; ++ ep->dwc_ep.start_xfer_buff = cfi->buf_out.buf; ++ ep->dwc_ep.xfer_buff = cfi->buf_out.buf; ++ ep->dwc_ep.xfer_len = wLen; ++ ep->dwc_ep.xfer_count = 0; ++ ep->dwc_ep.sent_zlp = 0; ++ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len; ++ ++ pcd->ep0_pending = 1; ++ /* Read the control write's data stage */ ++ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep); ++ retval = 0; ++ break; ++ ++ case VEN_CORE_RESET_FEATURES: ++ CFI_INFO("VEN_CORE_RESET_FEATURES\n"); ++ cfi->need_gadget_att = 1; ++ cfi->need_status_in_complete = 1; ++ retval = cfi_preproc_reset(pcd, ctrl); ++ CFI_INFO("VEN_CORE_RESET_FEATURES = (%d)\n", retval); ++ break; ++ ++ case VEN_CORE_ACTIVATE_FEATURES: ++ CFI_INFO("VEN_CORE_ACTIVATE_FEATURES\n"); ++ break; ++ ++ case VEN_CORE_READ_REGISTER: ++ CFI_INFO("VEN_CORE_READ_REGISTER\n"); ++ /* wValue optionally contains the HI WORD of the register offset and ++ * wIndex contains the LOW WORD of the register offset ++ */ ++ if (wValue == 0) { ++ /* @TODO - MAS - fix the access to the base field */ ++ regaddr = 0; ++ //regaddr = (uint32_t) pcd->otg_dev->os_dep.base; ++ //GET_CORE_IF(pcd)->co ++ regaddr |= wIndex; ++ } else { ++ regaddr = (wValue << 16) | wIndex; ++ } ++ ++ /* Read a 32-bit value of the memory at the regaddr */ ++ regval = DWC_READ_REG32((uint32_t *) regaddr); ++ ++ ep = &pcd->ep0; ++ dwc_memcpy(cfi->buf_in.buf, ®val, sizeof(uint32_t)); ++ ep->dwc_ep.is_in = 1; ++ ep->dwc_ep.dma_addr = cfi->buf_in.addr; ++ ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf; ++ ep->dwc_ep.xfer_buff = cfi->buf_in.buf; ++ ep->dwc_ep.xfer_len = wLen; ++ ep->dwc_ep.xfer_count = 0; ++ ep->dwc_ep.sent_zlp = 0; ++ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len; ++ ++ pcd->ep0_pending = 1; ++ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep); ++ cfi->need_gadget_att = 0; ++ retval = 0; ++ break; ++ ++ case VEN_CORE_WRITE_REGISTER: ++ CFI_INFO("VEN_CORE_WRITE_REGISTER\n"); ++ /* Set up an XFER to get the data stage of the control request, ++ * which is the new value of the register to be modified. ++ */ ++ ep = &pcd->ep0; ++ ep->dwc_ep.is_in = 0; ++ ep->dwc_ep.dma_addr = cfi->buf_out.addr; ++ ep->dwc_ep.start_xfer_buff = cfi->buf_out.buf; ++ ep->dwc_ep.xfer_buff = cfi->buf_out.buf; ++ ep->dwc_ep.xfer_len = wLen; ++ ep->dwc_ep.xfer_count = 0; ++ ep->dwc_ep.sent_zlp = 0; ++ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len; ++ ++ pcd->ep0_pending = 1; ++ /* Read the control write's data stage */ ++ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep); ++ retval = 0; ++ break; ++ ++ default: ++ retval = -DWC_E_NOT_SUPPORTED; ++ break; ++ } ++ ++ return retval; ++} ++ ++/** ++ * This function prepares the core features descriptors and copies its ++ * raw representation into the buffer . ++ * ++ * The buffer structure is as follows: ++ * all_features_header (8 bytes) ++ * features_#1 (8 bytes + feature name string length) ++ * features_#2 (8 bytes + feature name string length) ++ * ..... ++ * features_#n - where n=the total count of feature descriptors ++ */ ++static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen) ++{ ++ cfi_feature_desc_header_t *prop_hdr = prop_descs; ++ cfi_feature_desc_header_t *prop; ++ cfi_all_features_header_t *all_props_hdr = &all_props_desc_header; ++ cfi_all_features_header_t *tmp; ++ uint8_t *tmpbuf = buf; ++ const uint8_t *pname = NULL; ++ int i, j, namelen = 0, totlen; ++ ++ /* Prepare and copy the core features into the buffer */ ++ CFI_INFO("%s:\n", __func__); ++ ++ tmp = (cfi_all_features_header_t *) tmpbuf; ++ *tmp = *all_props_hdr; ++ tmpbuf += CFI_ALL_FEATURES_HDR_LEN; ++ ++ j = sizeof(prop_descs) / sizeof(cfi_all_features_header_t); ++ for (i = 0; i < j; i++, prop_hdr++) { ++ pname = get_prop_name(prop_hdr->wFeatureID, &namelen); ++ prop = (cfi_feature_desc_header_t *) tmpbuf; ++ *prop = *prop_hdr; ++ ++ prop->bNameLen = namelen; ++ prop->wLength = ++ DWC_CONSTANT_CPU_TO_LE16(CFI_FEATURE_DESC_HDR_LEN + ++ namelen); ++ ++ tmpbuf += CFI_FEATURE_DESC_HDR_LEN; ++ dwc_memcpy(tmpbuf, pname, namelen); ++ tmpbuf += namelen; ++ } ++ ++ totlen = tmpbuf - buf; ++ ++ if (totlen > 0) { ++ tmp = (cfi_all_features_header_t *) buf; ++ tmp->wTotalLen = DWC_CONSTANT_CPU_TO_LE16(totlen); ++ } ++ ++ return totlen; ++} ++ ++/** ++ * This function releases all the dynamic memory in the CFI object. ++ */ ++static void cfi_release(cfiobject_t * cfiobj) ++{ ++ cfi_ep_t *cfiep; ++ dwc_list_link_t *tmp; ++ ++ CFI_INFO("%s\n", __func__); ++ ++ if (cfiobj->buf_in.buf) { ++ DWC_DMA_FREE(CFI_IN_BUF_LEN, cfiobj->buf_in.buf, ++ cfiobj->buf_in.addr); ++ cfiobj->buf_in.buf = NULL; ++ } ++ ++ if (cfiobj->buf_out.buf) { ++ DWC_DMA_FREE(CFI_OUT_BUF_LEN, cfiobj->buf_out.buf, ++ cfiobj->buf_out.addr); ++ cfiobj->buf_out.buf = NULL; ++ } ++ ++ /* Free the Buffer Setup values for each EP */ ++ //list_for_each_entry(cfiep, &cfiobj->active_eps, lh) { ++ DWC_LIST_FOREACH(tmp, &cfiobj->active_eps) { ++ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh); ++ cfi_free_ep_bs_dyn_data(cfiep); ++ } ++} ++ ++/** ++ * This function frees the dynamically allocated EP buffer setup data. ++ */ ++static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep) ++{ ++ if (cfiep->bm_sg) { ++ DWC_FREE(cfiep->bm_sg); ++ cfiep->bm_sg = NULL; ++ } ++ ++ if (cfiep->bm_align) { ++ DWC_FREE(cfiep->bm_align); ++ cfiep->bm_align = NULL; ++ } ++ ++ if (cfiep->bm_concat) { ++ if (NULL != cfiep->bm_concat->wTxBytes) { ++ DWC_FREE(cfiep->bm_concat->wTxBytes); ++ cfiep->bm_concat->wTxBytes = NULL; ++ } ++ DWC_FREE(cfiep->bm_concat); ++ cfiep->bm_concat = NULL; ++ } ++} ++ ++/** ++ * This function initializes the default values of the features ++ * for a specific endpoint and should be called only once when ++ * the EP is enabled first time. ++ */ ++static int cfi_ep_init_defaults(struct dwc_otg_pcd *pcd, cfi_ep_t * cfiep) ++{ ++ int retval = 0; ++ ++ cfiep->bm_sg = DWC_ALLOC(sizeof(ddma_sg_buffer_setup_t)); ++ if (NULL == cfiep->bm_sg) { ++ CFI_INFO("Failed to allocate memory for SG feature value\n"); ++ return -DWC_E_NO_MEMORY; ++ } ++ dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t)); ++ ++ /* For the Concatenation feature's default value we do not allocate ++ * memory for the wTxBytes field - it will be done in the set_feature_value ++ * request handler. ++ */ ++ cfiep->bm_concat = DWC_ALLOC(sizeof(ddma_concat_buffer_setup_t)); ++ if (NULL == cfiep->bm_concat) { ++ CFI_INFO ++ ("Failed to allocate memory for CONCATENATION feature value\n"); ++ DWC_FREE(cfiep->bm_sg); ++ return -DWC_E_NO_MEMORY; ++ } ++ dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t)); ++ ++ cfiep->bm_align = DWC_ALLOC(sizeof(ddma_align_buffer_setup_t)); ++ if (NULL == cfiep->bm_align) { ++ CFI_INFO ++ ("Failed to allocate memory for Alignment feature value\n"); ++ DWC_FREE(cfiep->bm_sg); ++ DWC_FREE(cfiep->bm_concat); ++ return -DWC_E_NO_MEMORY; ++ } ++ dwc_memset(cfiep->bm_align, 0, sizeof(ddma_align_buffer_setup_t)); ++ ++ return retval; ++} ++ ++/** ++ * The callback function that notifies the CFI on the activation of ++ * an endpoint in the PCD. The following steps are done in this function: ++ * ++ * Create a dynamically allocated cfi_ep_t object (a CFI wrapper to the PCD's ++ * active endpoint) ++ * Create MAX_DMA_DESCS_PER_EP count DMA Descriptors for the EP ++ * Set the Buffer Mode to standard ++ * Initialize the default values for all EP modes (SG, Circular, Concat, Align) ++ * Add the cfi_ep_t object to the list of active endpoints in the CFI object ++ */ ++static int cfi_ep_enable(struct cfiobject *cfi, struct dwc_otg_pcd *pcd, ++ struct dwc_otg_pcd_ep *ep) ++{ ++ cfi_ep_t *cfiep; ++ int retval = -DWC_E_NOT_SUPPORTED; ++ ++ CFI_INFO("%s: epname=%s; epnum=0x%02x\n", __func__, ++ "EP_" /*ep->ep.name */ , ep->desc->bEndpointAddress); ++ /* MAS - Check whether this endpoint already is in the list */ ++ cfiep = get_cfi_ep_by_pcd_ep(cfi, ep); ++ ++ if (NULL == cfiep) { ++ /* Allocate a cfi_ep_t object */ ++ cfiep = DWC_ALLOC(sizeof(cfi_ep_t)); ++ if (NULL == cfiep) { ++ CFI_INFO ++ ("Unable to allocate memory for in function %s\n", ++ __func__); ++ return -DWC_E_NO_MEMORY; ++ } ++ dwc_memset(cfiep, 0, sizeof(cfi_ep_t)); ++ ++ /* Save the dwc_otg_pcd_ep pointer in the cfiep object */ ++ cfiep->ep = ep; ++ ++ /* Allocate the DMA Descriptors chain of MAX_DMA_DESCS_PER_EP count */ ++ ep->dwc_ep.descs = ++ DWC_DMA_ALLOC(MAX_DMA_DESCS_PER_EP * ++ sizeof(dwc_otg_dma_desc_t), ++ &ep->dwc_ep.descs_dma_addr); ++ ++ if (NULL == ep->dwc_ep.descs) { ++ DWC_FREE(cfiep); ++ return -DWC_E_NO_MEMORY; ++ } ++ ++ DWC_LIST_INIT(&cfiep->lh); ++ ++ /* Set the buffer mode to BM_STANDARD. It will be modified ++ * when building descriptors for a specific buffer mode */ ++ ep->dwc_ep.buff_mode = BM_STANDARD; ++ ++ /* Create and initialize the default values for this EP's Buffer modes */ ++ if ((retval = cfi_ep_init_defaults(pcd, cfiep)) < 0) ++ return retval; ++ ++ /* Add the cfi_ep_t object to the CFI object's list of active endpoints */ ++ DWC_LIST_INSERT_TAIL(&cfi->active_eps, &cfiep->lh); ++ retval = 0; ++ } else { /* The sought EP already is in the list */ ++ CFI_INFO("%s: The sought EP already is in the list\n", ++ __func__); ++ } ++ ++ return retval; ++} ++ ++/** ++ * This function is called when the data stage of a 3-stage Control Write request ++ * is complete. ++ * ++ */ ++static int cfi_ctrl_write_complete(struct cfiobject *cfi, ++ struct dwc_otg_pcd *pcd) ++{ ++ uint32_t addr, reg_value; ++ uint16_t wIndex, wValue; ++ uint8_t bRequest; ++ uint8_t *buf = cfi->buf_out.buf; ++ //struct usb_ctrlrequest *ctrl_req = &cfi->ctrl_req_saved; ++ struct cfi_usb_ctrlrequest *ctrl_req = &cfi->ctrl_req; ++ int retval = -DWC_E_NOT_SUPPORTED; ++ ++ CFI_INFO("%s\n", __func__); ++ ++ bRequest = ctrl_req->bRequest; ++ wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex); ++ wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue); ++ ++ /* ++ * Save the pointer to the data stage in the ctrl_req's field. ++ * The request should be already saved in the command stage by now. ++ */ ++ ctrl_req->data = cfi->buf_out.buf; ++ cfi->need_status_in_complete = 0; ++ cfi->need_gadget_att = 0; ++ ++ switch (bRequest) { ++ case VEN_CORE_WRITE_REGISTER: ++ /* The buffer contains raw data of the new value for the register */ ++ reg_value = *((uint32_t *) buf); ++ if (wValue == 0) { ++ addr = 0; ++ //addr = (uint32_t) pcd->otg_dev->os_dep.base; ++ addr += wIndex; ++ } else { ++ addr = (wValue << 16) | wIndex; ++ } ++ ++ //writel(reg_value, addr); ++ ++ retval = 0; ++ cfi->need_status_in_complete = 1; ++ break; ++ ++ case VEN_CORE_SET_FEATURE: ++ /* The buffer contains raw data of the new value of the feature */ ++ retval = cfi_set_feature_value(pcd); ++ if (retval < 0) ++ return retval; ++ ++ cfi->need_status_in_complete = 1; ++ break; ++ ++ default: ++ break; ++ } ++ ++ return retval; ++} ++ ++/** ++ * This function builds the DMA descriptors for the SG buffer mode. ++ */ ++static void cfi_build_sg_descs(struct cfiobject *cfi, cfi_ep_t * cfiep, ++ dwc_otg_pcd_request_t * req) ++{ ++ struct dwc_otg_pcd_ep *ep = cfiep->ep; ++ ddma_sg_buffer_setup_t *sgval = cfiep->bm_sg; ++ struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs; ++ struct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs; ++ dma_addr_t buff_addr = req->dma; ++ int i; ++ uint32_t txsize, off; ++ ++ txsize = sgval->wSize; ++ off = sgval->bOffset; ++ ++// CFI_INFO("%s: %s TXSIZE=0x%08x; OFFSET=0x%08x\n", ++// __func__, cfiep->ep->ep.name, txsize, off); ++ ++ for (i = 0; i < sgval->bCount; i++) { ++ desc->status.b.bs = BS_HOST_BUSY; ++ desc->buf = buff_addr; ++ desc->status.b.l = 0; ++ desc->status.b.ioc = 0; ++ desc->status.b.sp = 0; ++ desc->status.b.bytes = txsize; ++ desc->status.b.bs = BS_HOST_READY; ++ ++ /* Set the next address of the buffer */ ++ buff_addr += txsize + off; ++ desc_last = desc; ++ desc++; ++ } ++ ++ /* Set the last, ioc and sp bits on the Last DMA Descriptor */ ++ desc_last->status.b.l = 1; ++ desc_last->status.b.ioc = 1; ++ desc_last->status.b.sp = ep->dwc_ep.sent_zlp; ++ /* Save the last DMA descriptor pointer */ ++ cfiep->dma_desc_last = desc_last; ++ cfiep->desc_count = sgval->bCount; ++} ++ ++/** ++ * This function builds the DMA descriptors for the Concatenation buffer mode. ++ */ ++static void cfi_build_concat_descs(struct cfiobject *cfi, cfi_ep_t * cfiep, ++ dwc_otg_pcd_request_t * req) ++{ ++ struct dwc_otg_pcd_ep *ep = cfiep->ep; ++ ddma_concat_buffer_setup_t *concatval = cfiep->bm_concat; ++ struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs; ++ struct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs; ++ dma_addr_t buff_addr = req->dma; ++ int i; ++ uint16_t *txsize; ++ ++ txsize = concatval->wTxBytes; ++ ++ for (i = 0; i < concatval->hdr.bDescCount; i++) { ++ desc->buf = buff_addr; ++ desc->status.b.bs = BS_HOST_BUSY; ++ desc->status.b.l = 0; ++ desc->status.b.ioc = 0; ++ desc->status.b.sp = 0; ++ desc->status.b.bytes = *txsize; ++ desc->status.b.bs = BS_HOST_READY; ++ ++ txsize++; ++ /* Set the next address of the buffer */ ++ buff_addr += UGETW(ep->desc->wMaxPacketSize); ++ desc_last = desc; ++ desc++; ++ } ++ ++ /* Set the last, ioc and sp bits on the Last DMA Descriptor */ ++ desc_last->status.b.l = 1; ++ desc_last->status.b.ioc = 1; ++ desc_last->status.b.sp = ep->dwc_ep.sent_zlp; ++ cfiep->dma_desc_last = desc_last; ++ cfiep->desc_count = concatval->hdr.bDescCount; ++} ++ ++/** ++ * This function builds the DMA descriptors for the Circular buffer mode ++ */ ++static void cfi_build_circ_descs(struct cfiobject *cfi, cfi_ep_t * cfiep, ++ dwc_otg_pcd_request_t * req) ++{ ++ /* @todo: MAS - add implementation when this feature needs to be tested */ ++} ++ ++/** ++ * This function builds the DMA descriptors for the Alignment buffer mode ++ */ ++static void cfi_build_align_descs(struct cfiobject *cfi, cfi_ep_t * cfiep, ++ dwc_otg_pcd_request_t * req) ++{ ++ struct dwc_otg_pcd_ep *ep = cfiep->ep; ++ ddma_align_buffer_setup_t *alignval = cfiep->bm_align; ++ struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs; ++ dma_addr_t buff_addr = req->dma; ++ ++ desc->status.b.bs = BS_HOST_BUSY; ++ desc->status.b.l = 1; ++ desc->status.b.ioc = 1; ++ desc->status.b.sp = ep->dwc_ep.sent_zlp; ++ desc->status.b.bytes = req->length; ++ /* Adjust the buffer alignment */ ++ desc->buf = (buff_addr + alignval->bAlign); ++ desc->status.b.bs = BS_HOST_READY; ++ cfiep->dma_desc_last = desc; ++ cfiep->desc_count = 1; ++} ++ ++/** ++ * This function builds the DMA descriptors chain for different modes of the ++ * buffer setup of an endpoint. ++ */ ++static void cfi_build_descriptors(struct cfiobject *cfi, ++ struct dwc_otg_pcd *pcd, ++ struct dwc_otg_pcd_ep *ep, ++ dwc_otg_pcd_request_t * req) ++{ ++ cfi_ep_t *cfiep; ++ ++ /* Get the cfiep by the dwc_otg_pcd_ep */ ++ cfiep = get_cfi_ep_by_pcd_ep(cfi, ep); ++ if (NULL == cfiep) { ++ CFI_INFO("%s: Unable to find a matching active endpoint\n", ++ __func__); ++ return; ++ } ++ ++ cfiep->xfer_len = req->length; ++ ++ /* Iterate through all the DMA descriptors */ ++ switch (cfiep->ep->dwc_ep.buff_mode) { ++ case BM_SG: ++ cfi_build_sg_descs(cfi, cfiep, req); ++ break; ++ ++ case BM_CONCAT: ++ cfi_build_concat_descs(cfi, cfiep, req); ++ break; ++ ++ case BM_CIRCULAR: ++ cfi_build_circ_descs(cfi, cfiep, req); ++ break; ++ ++ case BM_ALIGN: ++ cfi_build_align_descs(cfi, cfiep, req); ++ break; ++ ++ default: ++ break; ++ } ++} ++ ++/** ++ * Allocate DMA buffer for different Buffer modes. ++ */ ++static void *cfi_ep_alloc_buf(struct cfiobject *cfi, struct dwc_otg_pcd *pcd, ++ struct dwc_otg_pcd_ep *ep, dma_addr_t * dma, ++ unsigned size, gfp_t flags) ++{ ++ return DWC_DMA_ALLOC(size, dma); ++} ++ ++/** ++ * This function initializes the CFI object. ++ */ ++int init_cfi(cfiobject_t * cfiobj) ++{ ++ CFI_INFO("%s\n", __func__); ++ ++ /* Allocate a buffer for IN XFERs */ ++ cfiobj->buf_in.buf = ++ DWC_DMA_ALLOC(CFI_IN_BUF_LEN, &cfiobj->buf_in.addr); ++ if (NULL == cfiobj->buf_in.buf) { ++ CFI_INFO("Unable to allocate buffer for INs\n"); ++ return -DWC_E_NO_MEMORY; ++ } ++ ++ /* Allocate a buffer for OUT XFERs */ ++ cfiobj->buf_out.buf = ++ DWC_DMA_ALLOC(CFI_OUT_BUF_LEN, &cfiobj->buf_out.addr); ++ if (NULL == cfiobj->buf_out.buf) { ++ CFI_INFO("Unable to allocate buffer for OUT\n"); ++ return -DWC_E_NO_MEMORY; ++ } ++ ++ /* Initialize the callback function pointers */ ++ cfiobj->ops.release = cfi_release; ++ cfiobj->ops.ep_enable = cfi_ep_enable; ++ cfiobj->ops.ctrl_write_complete = cfi_ctrl_write_complete; ++ cfiobj->ops.build_descriptors = cfi_build_descriptors; ++ cfiobj->ops.ep_alloc_buf = cfi_ep_alloc_buf; ++ ++ /* Initialize the list of active endpoints in the CFI object */ ++ DWC_LIST_INIT(&cfiobj->active_eps); ++ ++ return 0; ++} ++ ++/** ++ * This function reads the required feature's current value into the buffer ++ * ++ * @retval: Returns negative as error, or the data length of the feature ++ */ ++static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen, ++ struct dwc_otg_pcd *pcd, ++ struct cfi_usb_ctrlrequest *ctrl_req) ++{ ++ int retval = -DWC_E_NOT_SUPPORTED; ++ struct dwc_otg_core_if *coreif = GET_CORE_IF(pcd); ++ uint16_t dfifo, rxfifo, txfifo; ++ ++ switch (ctrl_req->wIndex) { ++ /* Whether the DDMA is enabled or not */ ++ case FT_ID_DMA_MODE: ++ *buf = (coreif->dma_enable && coreif->dma_desc_enable) ? 1 : 0; ++ retval = 1; ++ break; ++ ++ case FT_ID_DMA_BUFFER_SETUP: ++ retval = cfi_ep_get_sg_val(buf, pcd, ctrl_req); ++ break; ++ ++ case FT_ID_DMA_BUFF_ALIGN: ++ retval = cfi_ep_get_align_val(buf, pcd, ctrl_req); ++ break; ++ ++ case FT_ID_DMA_CONCAT_SETUP: ++ retval = cfi_ep_get_concat_val(buf, pcd, ctrl_req); ++ break; ++ ++ case FT_ID_DMA_CIRCULAR: ++ CFI_INFO("GetFeature value (FT_ID_DMA_CIRCULAR)\n"); ++ break; ++ ++ case FT_ID_THRESHOLD_SETUP: ++ CFI_INFO("GetFeature value (FT_ID_THRESHOLD_SETUP)\n"); ++ break; ++ ++ case FT_ID_DFIFO_DEPTH: ++ dfifo = get_dfifo_size(coreif); ++ *((uint16_t *) buf) = dfifo; ++ retval = sizeof(uint16_t); ++ break; ++ ++ case FT_ID_TX_FIFO_DEPTH: ++ retval = get_txfifo_size(pcd, ctrl_req->wValue); ++ if (retval >= 0) { ++ txfifo = retval; ++ *((uint16_t *) buf) = txfifo; ++ retval = sizeof(uint16_t); ++ } ++ break; ++ ++ case FT_ID_RX_FIFO_DEPTH: ++ retval = get_rxfifo_size(coreif, ctrl_req->wValue); ++ if (retval >= 0) { ++ rxfifo = retval; ++ *((uint16_t *) buf) = rxfifo; ++ retval = sizeof(uint16_t); ++ } ++ break; ++ } ++ ++ return retval; ++} ++ ++/** ++ * This function resets the SG for the specified EP to its default value ++ */ ++static int cfi_reset_sg_val(cfi_ep_t * cfiep) ++{ ++ dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t)); ++ return 0; ++} ++ ++/** ++ * This function resets the Alignment for the specified EP to its default value ++ */ ++static int cfi_reset_align_val(cfi_ep_t * cfiep) ++{ ++ dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t)); ++ return 0; ++} ++ ++/** ++ * This function resets the Concatenation for the specified EP to its default value ++ * This function will also set the value of the wTxBytes field to NULL after ++ * freeing the memory previously allocated for this field. ++ */ ++static int cfi_reset_concat_val(cfi_ep_t * cfiep) ++{ ++ /* First we need to free the wTxBytes field */ ++ if (cfiep->bm_concat->wTxBytes) { ++ DWC_FREE(cfiep->bm_concat->wTxBytes); ++ cfiep->bm_concat->wTxBytes = NULL; ++ } ++ ++ dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t)); ++ return 0; ++} ++ ++/** ++ * This function resets all the buffer setups of the specified endpoint ++ */ ++static int cfi_ep_reset_all_setup_vals(cfi_ep_t * cfiep) ++{ ++ cfi_reset_sg_val(cfiep); ++ cfi_reset_align_val(cfiep); ++ cfi_reset_concat_val(cfiep); ++ return 0; ++} ++ ++static int cfi_handle_reset_fifo_val(struct dwc_otg_pcd *pcd, uint8_t ep_addr, ++ uint8_t rx_rst, uint8_t tx_rst) ++{ ++ int retval = -DWC_E_INVALID; ++ uint16_t tx_siz[15]; ++ uint16_t rx_siz = 0; ++ dwc_otg_pcd_ep_t *ep = NULL; ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params; ++ ++ if (rx_rst) { ++ rx_siz = params->dev_rx_fifo_size; ++ params->dev_rx_fifo_size = GET_CORE_IF(pcd)->init_rxfsiz; ++ } ++ ++ if (tx_rst) { ++ if (ep_addr == 0) { ++ int i; ++ ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { ++ tx_siz[i] = ++ core_if->core_params->dev_tx_fifo_size[i]; ++ core_if->core_params->dev_tx_fifo_size[i] = ++ core_if->init_txfsiz[i]; ++ } ++ } else { ++ ++ ep = get_ep_by_addr(pcd, ep_addr); ++ ++ if (NULL == ep) { ++ CFI_INFO ++ ("%s: Unable to get the endpoint addr=0x%02x\n", ++ __func__, ep_addr); ++ return -DWC_E_INVALID; ++ } ++ ++ tx_siz[0] = ++ params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - ++ 1]; ++ params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = ++ GET_CORE_IF(pcd)->init_txfsiz[ep-> ++ dwc_ep.tx_fifo_num - ++ 1]; ++ } ++ } ++ ++ if (resize_fifos(GET_CORE_IF(pcd))) { ++ retval = 0; ++ } else { ++ CFI_INFO ++ ("%s: Error resetting the feature Reset All(FIFO size)\n", ++ __func__); ++ if (rx_rst) { ++ params->dev_rx_fifo_size = rx_siz; ++ } ++ ++ if (tx_rst) { ++ if (ep_addr == 0) { ++ int i; ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; ++ i++) { ++ core_if-> ++ core_params->dev_tx_fifo_size[i] = ++ tx_siz[i]; ++ } ++ } else { ++ params->dev_tx_fifo_size[ep-> ++ dwc_ep.tx_fifo_num - ++ 1] = tx_siz[0]; ++ } ++ } ++ retval = -DWC_E_INVALID; ++ } ++ return retval; ++} ++ ++static int cfi_handle_reset_all(struct dwc_otg_pcd *pcd, uint8_t addr) ++{ ++ int retval = 0; ++ cfi_ep_t *cfiep; ++ cfiobject_t *cfi = pcd->cfi; ++ dwc_list_link_t *tmp; ++ ++ retval = cfi_handle_reset_fifo_val(pcd, addr, 1, 1); ++ if (retval < 0) { ++ return retval; ++ } ++ ++ /* If the EP address is known then reset the features for only that EP */ ++ if (addr) { ++ cfiep = get_cfi_ep_by_addr(pcd->cfi, addr); ++ if (NULL == cfiep) { ++ CFI_INFO("%s: Error getting the EP address 0x%02x\n", ++ __func__, addr); ++ return -DWC_E_INVALID; ++ } ++ retval = cfi_ep_reset_all_setup_vals(cfiep); ++ cfiep->ep->dwc_ep.buff_mode = BM_STANDARD; ++ } ++ /* Otherwise (wValue == 0), reset all features of all EP's */ ++ else { ++ /* Traverse all the active EP's and reset the feature(s) value(s) */ ++ //list_for_each_entry(cfiep, &cfi->active_eps, lh) { ++ DWC_LIST_FOREACH(tmp, &cfi->active_eps) { ++ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh); ++ retval = cfi_ep_reset_all_setup_vals(cfiep); ++ cfiep->ep->dwc_ep.buff_mode = BM_STANDARD; ++ if (retval < 0) { ++ CFI_INFO ++ ("%s: Error resetting the feature Reset All\n", ++ __func__); ++ return retval; ++ } ++ } ++ } ++ return retval; ++} ++ ++static int cfi_handle_reset_dma_buff_setup(struct dwc_otg_pcd *pcd, ++ uint8_t addr) ++{ ++ int retval = 0; ++ cfi_ep_t *cfiep; ++ cfiobject_t *cfi = pcd->cfi; ++ dwc_list_link_t *tmp; ++ ++ /* If the EP address is known then reset the features for only that EP */ ++ if (addr) { ++ cfiep = get_cfi_ep_by_addr(pcd->cfi, addr); ++ if (NULL == cfiep) { ++ CFI_INFO("%s: Error getting the EP address 0x%02x\n", ++ __func__, addr); ++ return -DWC_E_INVALID; ++ } ++ retval = cfi_reset_sg_val(cfiep); ++ } ++ /* Otherwise (wValue == 0), reset all features of all EP's */ ++ else { ++ /* Traverse all the active EP's and reset the feature(s) value(s) */ ++ //list_for_each_entry(cfiep, &cfi->active_eps, lh) { ++ DWC_LIST_FOREACH(tmp, &cfi->active_eps) { ++ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh); ++ retval = cfi_reset_sg_val(cfiep); ++ if (retval < 0) { ++ CFI_INFO ++ ("%s: Error resetting the feature Buffer Setup\n", ++ __func__); ++ return retval; ++ } ++ } ++ } ++ return retval; ++} ++ ++static int cfi_handle_reset_concat_val(struct dwc_otg_pcd *pcd, uint8_t addr) ++{ ++ int retval = 0; ++ cfi_ep_t *cfiep; ++ cfiobject_t *cfi = pcd->cfi; ++ dwc_list_link_t *tmp; ++ ++ /* If the EP address is known then reset the features for only that EP */ ++ if (addr) { ++ cfiep = get_cfi_ep_by_addr(pcd->cfi, addr); ++ if (NULL == cfiep) { ++ CFI_INFO("%s: Error getting the EP address 0x%02x\n", ++ __func__, addr); ++ return -DWC_E_INVALID; ++ } ++ retval = cfi_reset_concat_val(cfiep); ++ } ++ /* Otherwise (wValue == 0), reset all features of all EP's */ ++ else { ++ /* Traverse all the active EP's and reset the feature(s) value(s) */ ++ //list_for_each_entry(cfiep, &cfi->active_eps, lh) { ++ DWC_LIST_FOREACH(tmp, &cfi->active_eps) { ++ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh); ++ retval = cfi_reset_concat_val(cfiep); ++ if (retval < 0) { ++ CFI_INFO ++ ("%s: Error resetting the feature Concatenation Value\n", ++ __func__); ++ return retval; ++ } ++ } ++ } ++ return retval; ++} ++ ++static int cfi_handle_reset_align_val(struct dwc_otg_pcd *pcd, uint8_t addr) ++{ ++ int retval = 0; ++ cfi_ep_t *cfiep; ++ cfiobject_t *cfi = pcd->cfi; ++ dwc_list_link_t *tmp; ++ ++ /* If the EP address is known then reset the features for only that EP */ ++ if (addr) { ++ cfiep = get_cfi_ep_by_addr(pcd->cfi, addr); ++ if (NULL == cfiep) { ++ CFI_INFO("%s: Error getting the EP address 0x%02x\n", ++ __func__, addr); ++ return -DWC_E_INVALID; ++ } ++ retval = cfi_reset_align_val(cfiep); ++ } ++ /* Otherwise (wValue == 0), reset all features of all EP's */ ++ else { ++ /* Traverse all the active EP's and reset the feature(s) value(s) */ ++ //list_for_each_entry(cfiep, &cfi->active_eps, lh) { ++ DWC_LIST_FOREACH(tmp, &cfi->active_eps) { ++ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh); ++ retval = cfi_reset_align_val(cfiep); ++ if (retval < 0) { ++ CFI_INFO ++ ("%s: Error resetting the feature Aliignment Value\n", ++ __func__); ++ return retval; ++ } ++ } ++ } ++ return retval; ++ ++} ++ ++static int cfi_preproc_reset(struct dwc_otg_pcd *pcd, ++ struct cfi_usb_ctrlrequest *req) ++{ ++ int retval = 0; ++ ++ switch (req->wIndex) { ++ case 0: ++ /* Reset all features */ ++ retval = cfi_handle_reset_all(pcd, req->wValue & 0xff); ++ break; ++ ++ case FT_ID_DMA_BUFFER_SETUP: ++ /* Reset the SG buffer setup */ ++ retval = ++ cfi_handle_reset_dma_buff_setup(pcd, req->wValue & 0xff); ++ break; ++ ++ case FT_ID_DMA_CONCAT_SETUP: ++ /* Reset the Concatenation buffer setup */ ++ retval = cfi_handle_reset_concat_val(pcd, req->wValue & 0xff); ++ break; ++ ++ case FT_ID_DMA_BUFF_ALIGN: ++ /* Reset the Alignment buffer setup */ ++ retval = cfi_handle_reset_align_val(pcd, req->wValue & 0xff); ++ break; ++ ++ case FT_ID_TX_FIFO_DEPTH: ++ retval = ++ cfi_handle_reset_fifo_val(pcd, req->wValue & 0xff, 0, 1); ++ pcd->cfi->need_gadget_att = 0; ++ break; ++ ++ case FT_ID_RX_FIFO_DEPTH: ++ retval = cfi_handle_reset_fifo_val(pcd, 0, 1, 0); ++ pcd->cfi->need_gadget_att = 0; ++ break; ++ default: ++ break; ++ } ++ return retval; ++} ++ ++/** ++ * This function sets a new value for the SG buffer setup. ++ */ ++static int cfi_ep_set_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd) ++{ ++ uint8_t inaddr, outaddr; ++ cfi_ep_t *epin, *epout; ++ ddma_sg_buffer_setup_t *psgval; ++ uint32_t desccount, size; ++ ++ CFI_INFO("%s\n", __func__); ++ ++ psgval = (ddma_sg_buffer_setup_t *) buf; ++ desccount = (uint32_t) psgval->bCount; ++ size = (uint32_t) psgval->wSize; ++ ++ /* Check the DMA descriptor count */ ++ if ((desccount > MAX_DMA_DESCS_PER_EP) || (desccount == 0)) { ++ CFI_INFO ++ ("%s: The count of DMA Descriptors should be between 1 and %d\n", ++ __func__, MAX_DMA_DESCS_PER_EP); ++ return -DWC_E_INVALID; ++ } ++ ++ /* Check the DMA descriptor count */ ++ ++ if (size == 0) { ++ ++ CFI_INFO("%s: The transfer size should be at least 1 byte\n", ++ __func__); ++ ++ return -DWC_E_INVALID; ++ ++ } ++ ++ inaddr = psgval->bInEndpointAddress; ++ outaddr = psgval->bOutEndpointAddress; ++ ++ epin = get_cfi_ep_by_addr(pcd->cfi, inaddr); ++ epout = get_cfi_ep_by_addr(pcd->cfi, outaddr); ++ ++ if (NULL == epin || NULL == epout) { ++ CFI_INFO ++ ("%s: Unable to get the endpoints inaddr=0x%02x outaddr=0x%02x\n", ++ __func__, inaddr, outaddr); ++ return -DWC_E_INVALID; ++ } ++ ++ epin->ep->dwc_ep.buff_mode = BM_SG; ++ dwc_memcpy(epin->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t)); ++ ++ epout->ep->dwc_ep.buff_mode = BM_SG; ++ dwc_memcpy(epout->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t)); ++ ++ return 0; ++} ++ ++/** ++ * This function sets a new value for the buffer Alignment setup. ++ */ ++static int cfi_ep_set_alignment_val(uint8_t * buf, struct dwc_otg_pcd *pcd) ++{ ++ cfi_ep_t *ep; ++ uint8_t addr; ++ ddma_align_buffer_setup_t *palignval; ++ ++ palignval = (ddma_align_buffer_setup_t *) buf; ++ addr = palignval->bEndpointAddress; ++ ++ ep = get_cfi_ep_by_addr(pcd->cfi, addr); ++ ++ if (NULL == ep) { ++ CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n", ++ __func__, addr); ++ return -DWC_E_INVALID; ++ } ++ ++ ep->ep->dwc_ep.buff_mode = BM_ALIGN; ++ dwc_memcpy(ep->bm_align, palignval, sizeof(ddma_align_buffer_setup_t)); ++ ++ return 0; ++} ++ ++/** ++ * This function sets a new value for the Concatenation buffer setup. ++ */ ++static int cfi_ep_set_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd) ++{ ++ uint8_t addr; ++ cfi_ep_t *ep; ++ struct _ddma_concat_buffer_setup_hdr *pConcatValHdr; ++ uint16_t *pVals; ++ uint32_t desccount; ++ int i; ++ uint16_t mps; ++ ++ pConcatValHdr = (struct _ddma_concat_buffer_setup_hdr *)buf; ++ desccount = (uint32_t) pConcatValHdr->bDescCount; ++ pVals = (uint16_t *) (buf + BS_CONCAT_VAL_HDR_LEN); ++ ++ /* Check the DMA descriptor count */ ++ if (desccount > MAX_DMA_DESCS_PER_EP) { ++ CFI_INFO("%s: Maximum DMA Descriptor count should be %d\n", ++ __func__, MAX_DMA_DESCS_PER_EP); ++ return -DWC_E_INVALID; ++ } ++ ++ addr = pConcatValHdr->bEndpointAddress; ++ ep = get_cfi_ep_by_addr(pcd->cfi, addr); ++ if (NULL == ep) { ++ CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n", ++ __func__, addr); ++ return -DWC_E_INVALID; ++ } ++ ++ mps = UGETW(ep->ep->desc->wMaxPacketSize); ++ ++#if 0 ++ for (i = 0; i < desccount; i++) { ++ CFI_INFO("%s: wTxSize[%d]=0x%04x\n", __func__, i, pVals[i]); ++ } ++ CFI_INFO("%s: epname=%s; mps=%d\n", __func__, ep->ep->ep.name, mps); ++#endif ++ ++ /* Check the wTxSizes to be less than or equal to the mps */ ++ for (i = 0; i < desccount; i++) { ++ if (pVals[i] > mps) { ++ CFI_INFO ++ ("%s: ERROR - the wTxSize[%d] should be <= MPS (wTxSize=%d)\n", ++ __func__, i, pVals[i]); ++ return -DWC_E_INVALID; ++ } ++ } ++ ++ ep->ep->dwc_ep.buff_mode = BM_CONCAT; ++ dwc_memcpy(ep->bm_concat, pConcatValHdr, BS_CONCAT_VAL_HDR_LEN); ++ ++ /* Free the previously allocated storage for the wTxBytes */ ++ if (ep->bm_concat->wTxBytes) { ++ DWC_FREE(ep->bm_concat->wTxBytes); ++ } ++ ++ /* Allocate a new storage for the wTxBytes field */ ++ ep->bm_concat->wTxBytes = ++ DWC_ALLOC(sizeof(uint16_t) * pConcatValHdr->bDescCount); ++ if (NULL == ep->bm_concat->wTxBytes) { ++ CFI_INFO("%s: Unable to allocate memory\n", __func__); ++ return -DWC_E_NO_MEMORY; ++ } ++ ++ /* Copy the new values into the wTxBytes filed */ ++ dwc_memcpy(ep->bm_concat->wTxBytes, buf + BS_CONCAT_VAL_HDR_LEN, ++ sizeof(uint16_t) * pConcatValHdr->bDescCount); ++ ++ return 0; ++} ++ ++/** ++ * This function calculates the total of all FIFO sizes ++ * ++ * @param core_if Programming view of DWC_otg controller ++ * ++ * @return The total of data FIFO sizes. ++ * ++ */ ++static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if) ++{ ++ dwc_otg_core_params_t *params = core_if->core_params; ++ uint16_t dfifo_total = 0; ++ int i; ++ ++ /* The shared RxFIFO size */ ++ dfifo_total = ++ params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size; ++ ++ /* Add up each TxFIFO size to the total */ ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { ++ dfifo_total += params->dev_tx_fifo_size[i]; ++ } ++ ++ return dfifo_total; ++} ++ ++/** ++ * This function returns Rx FIFO size ++ * ++ * @param core_if Programming view of DWC_otg controller ++ * ++ * @return The total of data FIFO sizes. ++ * ++ */ ++static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue) ++{ ++ switch (wValue >> 8) { ++ case 0: ++ return (core_if->pwron_rxfsiz < ++ 32768) ? core_if->pwron_rxfsiz : 32768; ++ break; ++ case 1: ++ return core_if->core_params->dev_rx_fifo_size; ++ break; ++ default: ++ return -DWC_E_INVALID; ++ break; ++ } ++} ++ ++/** ++ * This function returns Tx FIFO size for IN EP ++ * ++ * @param core_if Programming view of DWC_otg controller ++ * ++ * @return The total of data FIFO sizes. ++ * ++ */ ++static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue) ++{ ++ dwc_otg_pcd_ep_t *ep; ++ ++ ep = get_ep_by_addr(pcd, wValue & 0xff); ++ ++ if (NULL == ep) { ++ CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n", ++ __func__, wValue & 0xff); ++ return -DWC_E_INVALID; ++ } ++ ++ if (!ep->dwc_ep.is_in) { ++ CFI_INFO ++ ("%s: No Tx FIFO assingned to the Out endpoint addr=0x%02x\n", ++ __func__, wValue & 0xff); ++ return -DWC_E_INVALID; ++ } ++ ++ switch (wValue >> 8) { ++ case 0: ++ return (GET_CORE_IF(pcd)->pwron_txfsiz ++ [ep->dwc_ep.tx_fifo_num - 1] < ++ 768) ? GET_CORE_IF(pcd)->pwron_txfsiz[ep-> ++ dwc_ep.tx_fifo_num ++ - 1] : 32768; ++ break; ++ case 1: ++ return GET_CORE_IF(pcd)->core_params-> ++ dev_tx_fifo_size[ep->dwc_ep.num - 1]; ++ break; ++ default: ++ return -DWC_E_INVALID; ++ break; ++ } ++} ++ ++/** ++ * This function checks if the submitted combination of ++ * device mode FIFO sizes is possible or not. ++ * ++ * @param core_if Programming view of DWC_otg controller ++ * ++ * @return 1 if possible, 0 otherwise. ++ * ++ */ ++static uint8_t check_fifo_sizes(dwc_otg_core_if_t * core_if) ++{ ++ uint16_t dfifo_actual = 0; ++ dwc_otg_core_params_t *params = core_if->core_params; ++ uint16_t start_addr = 0; ++ int i; ++ ++ dfifo_actual = ++ params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size; ++ ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { ++ dfifo_actual += params->dev_tx_fifo_size[i]; ++ } ++ ++ if (dfifo_actual > core_if->total_fifo_size) { ++ return 0; ++ } ++ ++ if (params->dev_rx_fifo_size > 32768 || params->dev_rx_fifo_size < 16) ++ return 0; ++ ++ if (params->dev_nperio_tx_fifo_size > 32768 ++ || params->dev_nperio_tx_fifo_size < 16) ++ return 0; ++ ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { ++ ++ if (params->dev_tx_fifo_size[i] > 768 ++ || params->dev_tx_fifo_size[i] < 4) ++ return 0; ++ } ++ ++ if (params->dev_rx_fifo_size > core_if->pwron_rxfsiz) ++ return 0; ++ start_addr = params->dev_rx_fifo_size; ++ ++ if (params->dev_nperio_tx_fifo_size > core_if->pwron_gnptxfsiz) ++ return 0; ++ start_addr += params->dev_nperio_tx_fifo_size; ++ ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { ++ ++ if (params->dev_tx_fifo_size[i] > core_if->pwron_txfsiz[i]) ++ return 0; ++ start_addr += params->dev_tx_fifo_size[i]; ++ } ++ ++ return 1; ++} ++ ++/** ++ * This function resizes Device mode FIFOs ++ * ++ * @param core_if Programming view of DWC_otg controller ++ * ++ * @return 1 if successful, 0 otherwise ++ * ++ */ ++static uint8_t resize_fifos(dwc_otg_core_if_t * core_if) ++{ ++ int i = 0; ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ dwc_otg_core_params_t *params = core_if->core_params; ++ uint32_t rx_fifo_size; ++ fifosize_data_t nptxfifosize; ++ fifosize_data_t txfifosize[15]; ++ ++ uint32_t rx_fsz_bak; ++ uint32_t nptxfsz_bak; ++ uint32_t txfsz_bak[15]; ++ ++ uint16_t start_address; ++ uint8_t retval = 1; ++ ++ if (!check_fifo_sizes(core_if)) { ++ return 0; ++ } ++ ++ /* Configure data FIFO sizes */ ++ if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) { ++ rx_fsz_bak = DWC_READ_REG32(&global_regs->grxfsiz); ++ rx_fifo_size = params->dev_rx_fifo_size; ++ DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fifo_size); ++ ++ /* ++ * Tx FIFOs These FIFOs are numbered from 1 to 15. ++ * Indexes of the FIFO size module parameters in the ++ * dev_tx_fifo_size array and the FIFO size registers in ++ * the dtxfsiz array run from 0 to 14. ++ */ ++ ++ /* Non-periodic Tx FIFO */ ++ nptxfsz_bak = DWC_READ_REG32(&global_regs->gnptxfsiz); ++ nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size; ++ start_address = params->dev_rx_fifo_size; ++ nptxfifosize.b.startaddr = start_address; ++ ++ DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32); ++ ++ start_address += nptxfifosize.b.depth; ++ ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { ++ txfsz_bak[i] = DWC_READ_REG32(&global_regs->dtxfsiz[i]); ++ ++ txfifosize[i].b.depth = params->dev_tx_fifo_size[i]; ++ txfifosize[i].b.startaddr = start_address; ++ DWC_WRITE_REG32(&global_regs->dtxfsiz[i], ++ txfifosize[i].d32); ++ ++ start_address += txfifosize[i].b.depth; ++ } ++ ++ /** Check if register values are set correctly */ ++ if (rx_fifo_size != DWC_READ_REG32(&global_regs->grxfsiz)) { ++ retval = 0; ++ } ++ ++ if (nptxfifosize.d32 != DWC_READ_REG32(&global_regs->gnptxfsiz)) { ++ retval = 0; ++ } ++ ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { ++ if (txfifosize[i].d32 != ++ DWC_READ_REG32(&global_regs->dtxfsiz[i])) { ++ retval = 0; ++ } ++ } ++ ++ /** If register values are not set correctly, reset old values */ ++ if (retval == 0) { ++ DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fsz_bak); ++ ++ /* Non-periodic Tx FIFO */ ++ DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfsz_bak); ++ ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { ++ DWC_WRITE_REG32(&global_regs->dtxfsiz[i], ++ txfsz_bak[i]); ++ } ++ } ++ } else { ++ return 0; ++ } ++ ++ /* Flush the FIFOs */ ++ dwc_otg_flush_tx_fifo(core_if, 0x10); /* all Tx FIFOs */ ++ dwc_otg_flush_rx_fifo(core_if); ++ ++ return retval; ++} ++ ++/** ++ * This function sets a new value for the buffer Alignment setup. ++ */ ++static int cfi_ep_set_tx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd) ++{ ++ int retval; ++ uint32_t fsiz; ++ uint16_t size; ++ uint16_t ep_addr; ++ dwc_otg_pcd_ep_t *ep; ++ dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params; ++ tx_fifo_size_setup_t *ptxfifoval; ++ ++ ptxfifoval = (tx_fifo_size_setup_t *) buf; ++ ep_addr = ptxfifoval->bEndpointAddress; ++ size = ptxfifoval->wDepth; ++ ++ ep = get_ep_by_addr(pcd, ep_addr); ++ ++ CFI_INFO ++ ("%s: Set Tx FIFO size: endpoint addr=0x%02x, depth=%d, FIFO Num=%d\n", ++ __func__, ep_addr, size, ep->dwc_ep.tx_fifo_num); ++ ++ if (NULL == ep) { ++ CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n", ++ __func__, ep_addr); ++ return -DWC_E_INVALID; ++ } ++ ++ fsiz = params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1]; ++ params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = size; ++ ++ if (resize_fifos(GET_CORE_IF(pcd))) { ++ retval = 0; ++ } else { ++ CFI_INFO ++ ("%s: Error setting the feature Tx FIFO Size for EP%d\n", ++ __func__, ep_addr); ++ params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = fsiz; ++ retval = -DWC_E_INVALID; ++ } ++ ++ return retval; ++} ++ ++/** ++ * This function sets a new value for the buffer Alignment setup. ++ */ ++static int cfi_set_rx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd) ++{ ++ int retval; ++ uint32_t fsiz; ++ uint16_t size; ++ dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params; ++ rx_fifo_size_setup_t *prxfifoval; ++ ++ prxfifoval = (rx_fifo_size_setup_t *) buf; ++ size = prxfifoval->wDepth; ++ ++ fsiz = params->dev_rx_fifo_size; ++ params->dev_rx_fifo_size = size; ++ ++ if (resize_fifos(GET_CORE_IF(pcd))) { ++ retval = 0; ++ } else { ++ CFI_INFO("%s: Error setting the feature Rx FIFO Size\n", ++ __func__); ++ params->dev_rx_fifo_size = fsiz; ++ retval = -DWC_E_INVALID; ++ } ++ ++ return retval; ++} ++ ++/** ++ * This function reads the SG of an EP's buffer setup into the buffer buf ++ */ ++static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd, ++ struct cfi_usb_ctrlrequest *req) ++{ ++ int retval = -DWC_E_INVALID; ++ uint8_t addr; ++ cfi_ep_t *ep; ++ ++ /* The Low Byte of the wValue contains a non-zero address of the endpoint */ ++ addr = req->wValue & 0xFF; ++ if (addr == 0) /* The address should be non-zero */ ++ return retval; ++ ++ ep = get_cfi_ep_by_addr(pcd->cfi, addr); ++ if (NULL == ep) { ++ CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n", ++ __func__, addr); ++ return retval; ++ } ++ ++ dwc_memcpy(buf, ep->bm_sg, BS_SG_VAL_DESC_LEN); ++ retval = BS_SG_VAL_DESC_LEN; ++ return retval; ++} ++ ++/** ++ * This function reads the Concatenation value of an EP's buffer mode into ++ * the buffer buf ++ */ ++static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd, ++ struct cfi_usb_ctrlrequest *req) ++{ ++ int retval = -DWC_E_INVALID; ++ uint8_t addr; ++ cfi_ep_t *ep; ++ uint8_t desc_count; ++ ++ /* The Low Byte of the wValue contains a non-zero address of the endpoint */ ++ addr = req->wValue & 0xFF; ++ if (addr == 0) /* The address should be non-zero */ ++ return retval; ++ ++ ep = get_cfi_ep_by_addr(pcd->cfi, addr); ++ if (NULL == ep) { ++ CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n", ++ __func__, addr); ++ return retval; ++ } ++ ++ /* Copy the header to the buffer */ ++ dwc_memcpy(buf, ep->bm_concat, BS_CONCAT_VAL_HDR_LEN); ++ /* Advance the buffer pointer by the header size */ ++ buf += BS_CONCAT_VAL_HDR_LEN; ++ ++ desc_count = ep->bm_concat->hdr.bDescCount; ++ /* Copy alll the wTxBytes to the buffer */ ++ dwc_memcpy(buf, ep->bm_concat->wTxBytes, sizeof(uid16_t) * desc_count); ++ ++ retval = BS_CONCAT_VAL_HDR_LEN + sizeof(uid16_t) * desc_count; ++ return retval; ++} ++ ++/** ++ * This function reads the buffer Alignment value of an EP's buffer mode into ++ * the buffer buf ++ * ++ * @return The total number of bytes copied to the buffer or negative error code. ++ */ ++static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd, ++ struct cfi_usb_ctrlrequest *req) ++{ ++ int retval = -DWC_E_INVALID; ++ uint8_t addr; ++ cfi_ep_t *ep; ++ ++ /* The Low Byte of the wValue contains a non-zero address of the endpoint */ ++ addr = req->wValue & 0xFF; ++ if (addr == 0) /* The address should be non-zero */ ++ return retval; ++ ++ ep = get_cfi_ep_by_addr(pcd->cfi, addr); ++ if (NULL == ep) { ++ CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n", ++ __func__, addr); ++ return retval; ++ } ++ ++ dwc_memcpy(buf, ep->bm_align, BS_ALIGN_VAL_HDR_LEN); ++ retval = BS_ALIGN_VAL_HDR_LEN; ++ ++ return retval; ++} ++ ++/** ++ * This function sets a new value for the specified feature ++ * ++ * @param pcd A pointer to the PCD object ++ * ++ * @return 0 if successful, negative error code otherwise to stall the DCE. ++ */ ++static int cfi_set_feature_value(struct dwc_otg_pcd *pcd) ++{ ++ int retval = -DWC_E_NOT_SUPPORTED; ++ uint16_t wIndex, wValue; ++ uint8_t bRequest; ++ struct dwc_otg_core_if *coreif; ++ cfiobject_t *cfi = pcd->cfi; ++ struct cfi_usb_ctrlrequest *ctrl_req; ++ uint8_t *buf; ++ ctrl_req = &cfi->ctrl_req; ++ ++ buf = pcd->cfi->ctrl_req.data; ++ ++ coreif = GET_CORE_IF(pcd); ++ bRequest = ctrl_req->bRequest; ++ wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex); ++ wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue); ++ ++ /* See which feature is to be modified */ ++ switch (wIndex) { ++ case FT_ID_DMA_BUFFER_SETUP: ++ /* Modify the feature */ ++ if ((retval = cfi_ep_set_sg_val(buf, pcd)) < 0) ++ return retval; ++ ++ /* And send this request to the gadget */ ++ cfi->need_gadget_att = 1; ++ break; ++ ++ case FT_ID_DMA_BUFF_ALIGN: ++ if ((retval = cfi_ep_set_alignment_val(buf, pcd)) < 0) ++ return retval; ++ cfi->need_gadget_att = 1; ++ break; ++ ++ case FT_ID_DMA_CONCAT_SETUP: ++ /* Modify the feature */ ++ if ((retval = cfi_ep_set_concat_val(buf, pcd)) < 0) ++ return retval; ++ cfi->need_gadget_att = 1; ++ break; ++ ++ case FT_ID_DMA_CIRCULAR: ++ CFI_INFO("FT_ID_DMA_CIRCULAR\n"); ++ break; ++ ++ case FT_ID_THRESHOLD_SETUP: ++ CFI_INFO("FT_ID_THRESHOLD_SETUP\n"); ++ break; ++ ++ case FT_ID_DFIFO_DEPTH: ++ CFI_INFO("FT_ID_DFIFO_DEPTH\n"); ++ break; ++ ++ case FT_ID_TX_FIFO_DEPTH: ++ CFI_INFO("FT_ID_TX_FIFO_DEPTH\n"); ++ if ((retval = cfi_ep_set_tx_fifo_val(buf, pcd)) < 0) ++ return retval; ++ cfi->need_gadget_att = 0; ++ break; ++ ++ case FT_ID_RX_FIFO_DEPTH: ++ CFI_INFO("FT_ID_RX_FIFO_DEPTH\n"); ++ if ((retval = cfi_set_rx_fifo_val(buf, pcd)) < 0) ++ return retval; ++ cfi->need_gadget_att = 0; ++ break; ++ } ++ ++ return retval; ++} ++ ++#endif //DWC_UTE_CFI +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_cfi.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cfi.h +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_cfi.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cfi.h 2015-11-29 09:42:39.915098960 +0100 +@@ -0,0 +1,320 @@ ++/* ========================================================================== ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++#if !defined(__DWC_OTG_CFI_H__) ++#define __DWC_OTG_CFI_H__ ++ ++#include "dwc_otg_pcd.h" ++#include "dwc_cfi_common.h" ++ ++/** ++ * @file ++ * This file contains the CFI related OTG PCD specific common constants, ++ * interfaces(functions and macros) and data structures.The CFI Protocol is an ++ * optional interface for internal testing purposes that a DUT may implement to ++ * support testing of configurable features. ++ * ++ */ ++ ++struct dwc_otg_pcd; ++struct dwc_otg_pcd_ep; ++ ++/** OTG CFI Features (properties) ID constants */ ++/** This is a request for all Core Features */ ++#define FT_ID_DMA_MODE 0x0001 ++#define FT_ID_DMA_BUFFER_SETUP 0x0002 ++#define FT_ID_DMA_BUFF_ALIGN 0x0003 ++#define FT_ID_DMA_CONCAT_SETUP 0x0004 ++#define FT_ID_DMA_CIRCULAR 0x0005 ++#define FT_ID_THRESHOLD_SETUP 0x0006 ++#define FT_ID_DFIFO_DEPTH 0x0007 ++#define FT_ID_TX_FIFO_DEPTH 0x0008 ++#define FT_ID_RX_FIFO_DEPTH 0x0009 ++ ++/**********************************************************/ ++#define CFI_INFO_DEF ++ ++#ifdef CFI_INFO_DEF ++#define CFI_INFO(fmt...) DWC_PRINTF("CFI: " fmt); ++#else ++#define CFI_INFO(fmt...) ++#endif ++ ++#define min(x,y) ({ \ ++ x < y ? x : y; }) ++ ++#define max(x,y) ({ \ ++ x > y ? x : y; }) ++ ++/** ++ * Descriptor DMA SG Buffer setup structure (SG buffer). This structure is ++ * also used for setting up a buffer for Circular DDMA. ++ */ ++struct _ddma_sg_buffer_setup { ++#define BS_SG_VAL_DESC_LEN 6 ++ /* The OUT EP address */ ++ uint8_t bOutEndpointAddress; ++ /* The IN EP address */ ++ uint8_t bInEndpointAddress; ++ /* Number of bytes to put between transfer segments (must be DWORD boundaries) */ ++ uint8_t bOffset; ++ /* The number of transfer segments (a DMA descriptors per each segment) */ ++ uint8_t bCount; ++ /* Size (in byte) of each transfer segment */ ++ uint16_t wSize; ++} __attribute__ ((packed)); ++typedef struct _ddma_sg_buffer_setup ddma_sg_buffer_setup_t; ++ ++/** Descriptor DMA Concatenation Buffer setup structure */ ++struct _ddma_concat_buffer_setup_hdr { ++#define BS_CONCAT_VAL_HDR_LEN 4 ++ /* The endpoint for which the buffer is to be set up */ ++ uint8_t bEndpointAddress; ++ /* The count of descriptors to be used */ ++ uint8_t bDescCount; ++ /* The total size of the transfer */ ++ uint16_t wSize; ++} __attribute__ ((packed)); ++typedef struct _ddma_concat_buffer_setup_hdr ddma_concat_buffer_setup_hdr_t; ++ ++/** Descriptor DMA Concatenation Buffer setup structure */ ++struct _ddma_concat_buffer_setup { ++ /* The SG header */ ++ ddma_concat_buffer_setup_hdr_t hdr; ++ ++ /* The XFER sizes pointer (allocated dynamically) */ ++ uint16_t *wTxBytes; ++} __attribute__ ((packed)); ++typedef struct _ddma_concat_buffer_setup ddma_concat_buffer_setup_t; ++ ++/** Descriptor DMA Alignment Buffer setup structure */ ++struct _ddma_align_buffer_setup { ++#define BS_ALIGN_VAL_HDR_LEN 2 ++ uint8_t bEndpointAddress; ++ uint8_t bAlign; ++} __attribute__ ((packed)); ++typedef struct _ddma_align_buffer_setup ddma_align_buffer_setup_t; ++ ++/** Transmit FIFO Size setup structure */ ++struct _tx_fifo_size_setup { ++ uint8_t bEndpointAddress; ++ uint16_t wDepth; ++} __attribute__ ((packed)); ++typedef struct _tx_fifo_size_setup tx_fifo_size_setup_t; ++ ++/** Transmit FIFO Size setup structure */ ++struct _rx_fifo_size_setup { ++ uint16_t wDepth; ++} __attribute__ ((packed)); ++typedef struct _rx_fifo_size_setup rx_fifo_size_setup_t; ++ ++/** ++ * struct cfi_usb_ctrlrequest - the CFI implementation of the struct usb_ctrlrequest ++ * This structure encapsulates the standard usb_ctrlrequest and adds a pointer ++ * to the data returned in the data stage of a 3-stage Control Write requests. ++ */ ++struct cfi_usb_ctrlrequest { ++ uint8_t bRequestType; ++ uint8_t bRequest; ++ uint16_t wValue; ++ uint16_t wIndex; ++ uint16_t wLength; ++ uint8_t *data; ++} UPACKED; ++ ++/*---------------------------------------------------------------------------*/ ++ ++/** ++ * The CFI wrapper of the enabled and activated dwc_otg_pcd_ep structures. ++ * This structure is used to store the buffer setup data for any ++ * enabled endpoint in the PCD. ++ */ ++struct cfi_ep { ++ /* Entry for the list container */ ++ dwc_list_link_t lh; ++ /* Pointer to the active PCD endpoint structure */ ++ struct dwc_otg_pcd_ep *ep; ++ /* The last descriptor in the chain of DMA descriptors of the endpoint */ ++ struct dwc_otg_dma_desc *dma_desc_last; ++ /* The SG feature value */ ++ ddma_sg_buffer_setup_t *bm_sg; ++ /* The Circular feature value */ ++ ddma_sg_buffer_setup_t *bm_circ; ++ /* The Concatenation feature value */ ++ ddma_concat_buffer_setup_t *bm_concat; ++ /* The Alignment feature value */ ++ ddma_align_buffer_setup_t *bm_align; ++ /* XFER length */ ++ uint32_t xfer_len; ++ /* ++ * Count of DMA descriptors currently used. ++ * The total should not exceed the MAX_DMA_DESCS_PER_EP value ++ * defined in the dwc_otg_cil.h ++ */ ++ uint32_t desc_count; ++}; ++typedef struct cfi_ep cfi_ep_t; ++ ++typedef struct cfi_dma_buff { ++#define CFI_IN_BUF_LEN 1024 ++#define CFI_OUT_BUF_LEN 1024 ++ dma_addr_t addr; ++ uint8_t *buf; ++} cfi_dma_buff_t; ++ ++struct cfiobject; ++ ++/** ++ * This is the interface for the CFI operations. ++ * ++ * @param ep_enable Called when any endpoint is enabled and activated. ++ * @param release Called when the CFI object is released and it needs to correctly ++ * deallocate the dynamic memory ++ * @param ctrl_write_complete Called when the data stage of the request is complete ++ */ ++typedef struct cfi_ops { ++ int (*ep_enable) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd, ++ struct dwc_otg_pcd_ep * ep); ++ void *(*ep_alloc_buf) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd, ++ struct dwc_otg_pcd_ep * ep, dma_addr_t * dma, ++ unsigned size, gfp_t flags); ++ void (*release) (struct cfiobject * cfi); ++ int (*ctrl_write_complete) (struct cfiobject * cfi, ++ struct dwc_otg_pcd * pcd); ++ void (*build_descriptors) (struct cfiobject * cfi, ++ struct dwc_otg_pcd * pcd, ++ struct dwc_otg_pcd_ep * ep, ++ dwc_otg_pcd_request_t * req); ++} cfi_ops_t; ++ ++struct cfiobject { ++ cfi_ops_t ops; ++ struct dwc_otg_pcd *pcd; ++ struct usb_gadget *gadget; ++ ++ /* Buffers used to send/receive CFI-related request data */ ++ cfi_dma_buff_t buf_in; ++ cfi_dma_buff_t buf_out; ++ ++ /* CFI specific Control request wrapper */ ++ struct cfi_usb_ctrlrequest ctrl_req; ++ ++ /* The list of active EP's in the PCD of type cfi_ep_t */ ++ dwc_list_link_t active_eps; ++ ++ /* This flag shall control the propagation of a specific request ++ * to the gadget's processing routines. ++ * 0 - no gadget handling ++ * 1 - the gadget needs to know about this request (w/o completing a status ++ * phase - just return a 0 to the _setup callback) ++ */ ++ uint8_t need_gadget_att; ++ ++ /* Flag indicating whether the status IN phase needs to be ++ * completed by the PCD ++ */ ++ uint8_t need_status_in_complete; ++}; ++typedef struct cfiobject cfiobject_t; ++ ++#define DUMP_MSG ++ ++#if defined(DUMP_MSG) ++static inline void dump_msg(const u8 * buf, unsigned int length) ++{ ++ unsigned int start, num, i; ++ char line[52], *p; ++ ++ if (length >= 512) ++ return; ++ ++ start = 0; ++ while (length > 0) { ++ num = min(length, 16u); ++ p = line; ++ for (i = 0; i < num; ++i) { ++ if (i == 8) ++ *p++ = ' '; ++ DWC_SPRINTF(p, " %02x", buf[i]); ++ p += 3; ++ } ++ *p = 0; ++ DWC_DEBUG("%6x: %s\n", start, line); ++ buf += num; ++ start += num; ++ length -= num; ++ } ++} ++#else ++static inline void dump_msg(const u8 * buf, unsigned int length) ++{ ++} ++#endif ++ ++/** ++ * This function returns a pointer to cfi_ep_t object with the addr address. ++ */ ++static inline struct cfi_ep *get_cfi_ep_by_addr(struct cfiobject *cfi, ++ uint8_t addr) ++{ ++ struct cfi_ep *pcfiep; ++ dwc_list_link_t *tmp; ++ ++ DWC_LIST_FOREACH(tmp, &cfi->active_eps) { ++ pcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh); ++ ++ if (pcfiep->ep->desc->bEndpointAddress == addr) { ++ return pcfiep; ++ } ++ } ++ ++ return NULL; ++} ++ ++/** ++ * This function returns a pointer to cfi_ep_t object that matches ++ * the dwc_otg_pcd_ep object. ++ */ ++static inline struct cfi_ep *get_cfi_ep_by_pcd_ep(struct cfiobject *cfi, ++ struct dwc_otg_pcd_ep *ep) ++{ ++ struct cfi_ep *pcfiep = NULL; ++ dwc_list_link_t *tmp; ++ ++ DWC_LIST_FOREACH(tmp, &cfi->active_eps) { ++ pcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh); ++ if (pcfiep->ep == ep) { ++ return pcfiep; ++ } ++ } ++ return NULL; ++} ++ ++int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl); ++ ++#endif /* (__DWC_OTG_CFI_H__) */ +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_cil.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cil.c +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_cil.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cil.c 2015-11-29 09:42:39.919098694 +0100 +@@ -0,0 +1,7141 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.c $ ++ * $Revision: #191 $ ++ * $Date: 2012/08/10 $ ++ * $Change: 2047372 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++/** @file ++ * ++ * The Core Interface Layer provides basic services for accessing and ++ * managing the DWC_otg hardware. These services are used by both the ++ * Host Controller Driver and the Peripheral Controller Driver. ++ * ++ * The CIL manages the memory map for the core so that the HCD and PCD ++ * don't have to do this separately. It also handles basic tasks like ++ * reading/writing the registers and data FIFOs in the controller. ++ * Some of the data access functions provide encapsulation of several ++ * operations required to perform a task, such as writing multiple ++ * registers to start a transfer. Finally, the CIL performs basic ++ * services that are not specific to either the host or device modes ++ * of operation. These services include management of the OTG Host ++ * Negotiation Protocol (HNP) and Session Request Protocol (SRP). A ++ * Diagnostic API is also provided to allow testing of the controller ++ * hardware. ++ * ++ * The Core Interface Layer has the following requirements: ++ * - Provides basic controller operations. ++ * - Minimal use of OS services. ++ * - The OS services used will be abstracted by using inline functions ++ * or macros. ++ * ++ */ ++ ++#include "dwc_os.h" ++#include "dwc_otg_regs.h" ++#include "dwc_otg_cil.h" ++ ++static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if); ++ ++/** ++ * This function is called to initialize the DWC_otg CSR data ++ * structures. The register addresses in the device and host ++ * structures are initialized from the base address supplied by the ++ * caller. The calling function must make the OS calls to get the ++ * base address of the DWC_otg controller registers. The core_params ++ * argument holds the parameters that specify how the core should be ++ * configured. ++ * ++ * @param reg_base_addr Base address of DWC_otg core registers ++ * ++ */ ++dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * reg_base_addr) ++{ ++ dwc_otg_core_if_t *core_if = 0; ++ dwc_otg_dev_if_t *dev_if = 0; ++ dwc_otg_host_if_t *host_if = 0; ++ uint8_t *reg_base = (uint8_t *) reg_base_addr; ++ int i = 0; ++ ++ DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, reg_base_addr); ++ ++ core_if = DWC_ALLOC(sizeof(dwc_otg_core_if_t)); ++ ++ if (core_if == NULL) { ++ DWC_DEBUGPL(DBG_CIL, ++ "Allocation of dwc_otg_core_if_t failed\n"); ++ return 0; ++ } ++ core_if->core_global_regs = (dwc_otg_core_global_regs_t *) reg_base; ++ ++ /* ++ * Allocate the Device Mode structures. ++ */ ++ dev_if = DWC_ALLOC(sizeof(dwc_otg_dev_if_t)); ++ ++ if (dev_if == NULL) { ++ DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n"); ++ DWC_FREE(core_if); ++ return 0; ++ } ++ ++ dev_if->dev_global_regs = ++ (dwc_otg_device_global_regs_t *) (reg_base + ++ DWC_DEV_GLOBAL_REG_OFFSET); ++ ++ for (i = 0; i < MAX_EPS_CHANNELS; i++) { ++ dev_if->in_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *) ++ (reg_base + DWC_DEV_IN_EP_REG_OFFSET + ++ (i * DWC_EP_REG_OFFSET)); ++ ++ dev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *) ++ (reg_base + DWC_DEV_OUT_EP_REG_OFFSET + ++ (i * DWC_EP_REG_OFFSET)); ++ DWC_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p\n", ++ i, &dev_if->in_ep_regs[i]->diepctl); ++ DWC_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p\n", ++ i, &dev_if->out_ep_regs[i]->doepctl); ++ } ++ ++ dev_if->speed = 0; // unknown ++ ++ core_if->dev_if = dev_if; ++ ++ /* ++ * Allocate the Host Mode structures. ++ */ ++ host_if = DWC_ALLOC(sizeof(dwc_otg_host_if_t)); ++ ++ if (host_if == NULL) { ++ DWC_DEBUGPL(DBG_CIL, ++ "Allocation of dwc_otg_host_if_t failed\n"); ++ DWC_FREE(dev_if); ++ DWC_FREE(core_if); ++ return 0; ++ } ++ ++ host_if->host_global_regs = (dwc_otg_host_global_regs_t *) ++ (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET); ++ ++ host_if->hprt0 = ++ (uint32_t *) (reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET); ++ ++ for (i = 0; i < MAX_EPS_CHANNELS; i++) { ++ host_if->hc_regs[i] = (dwc_otg_hc_regs_t *) ++ (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET + ++ (i * DWC_OTG_CHAN_REGS_OFFSET)); ++ DWC_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n", ++ i, &host_if->hc_regs[i]->hcchar); ++ } ++ ++ host_if->num_host_channels = MAX_EPS_CHANNELS; ++ core_if->host_if = host_if; ++ ++ for (i = 0; i < MAX_EPS_CHANNELS; i++) { ++ core_if->data_fifo[i] = ++ (uint32_t *) (reg_base + DWC_OTG_DATA_FIFO_OFFSET + ++ (i * DWC_OTG_DATA_FIFO_SIZE)); ++ DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08lx\n", ++ i, (unsigned long)core_if->data_fifo[i]); ++ } ++ ++ core_if->pcgcctl = (uint32_t *) (reg_base + DWC_OTG_PCGCCTL_OFFSET); ++ ++ /* Initiate lx_state to L3 disconnected state */ ++ core_if->lx_state = DWC_OTG_L3; ++ /* ++ * Store the contents of the hardware configuration registers here for ++ * easy access later. ++ */ ++ core_if->hwcfg1.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->ghwcfg1); ++ core_if->hwcfg2.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2); ++ core_if->hwcfg3.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->ghwcfg3); ++ core_if->hwcfg4.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4); ++ ++ /* Force host mode to get HPTXFSIZ exact power on value */ ++ { ++ gusbcfg_data_t gusbcfg = {.d32 = 0 }; ++ gusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); ++ gusbcfg.b.force_host_mode = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32); ++ dwc_mdelay(100); ++ core_if->hptxfsiz.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz); ++ gusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); ++ gusbcfg.b.force_host_mode = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32); ++ dwc_mdelay(100); ++ } ++ ++ DWC_DEBUGPL(DBG_CILV, "hwcfg1=%08x\n", core_if->hwcfg1.d32); ++ DWC_DEBUGPL(DBG_CILV, "hwcfg2=%08x\n", core_if->hwcfg2.d32); ++ DWC_DEBUGPL(DBG_CILV, "hwcfg3=%08x\n", core_if->hwcfg3.d32); ++ DWC_DEBUGPL(DBG_CILV, "hwcfg4=%08x\n", core_if->hwcfg4.d32); ++ ++ core_if->hcfg.d32 = ++ DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg); ++ core_if->dcfg.d32 = ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); ++ ++ DWC_DEBUGPL(DBG_CILV, "hcfg=%08x\n", core_if->hcfg.d32); ++ DWC_DEBUGPL(DBG_CILV, "dcfg=%08x\n", core_if->dcfg.d32); ++ ++ DWC_DEBUGPL(DBG_CILV, "op_mode=%0x\n", core_if->hwcfg2.b.op_mode); ++ DWC_DEBUGPL(DBG_CILV, "arch=%0x\n", core_if->hwcfg2.b.architecture); ++ DWC_DEBUGPL(DBG_CILV, "num_dev_ep=%d\n", core_if->hwcfg2.b.num_dev_ep); ++ DWC_DEBUGPL(DBG_CILV, "num_host_chan=%d\n", ++ core_if->hwcfg2.b.num_host_chan); ++ DWC_DEBUGPL(DBG_CILV, "nonperio_tx_q_depth=0x%0x\n", ++ core_if->hwcfg2.b.nonperio_tx_q_depth); ++ DWC_DEBUGPL(DBG_CILV, "host_perio_tx_q_depth=0x%0x\n", ++ core_if->hwcfg2.b.host_perio_tx_q_depth); ++ DWC_DEBUGPL(DBG_CILV, "dev_token_q_depth=0x%0x\n", ++ core_if->hwcfg2.b.dev_token_q_depth); ++ ++ DWC_DEBUGPL(DBG_CILV, "Total FIFO SZ=%d\n", ++ core_if->hwcfg3.b.dfifo_depth); ++ DWC_DEBUGPL(DBG_CILV, "xfer_size_cntr_width=%0x\n", ++ core_if->hwcfg3.b.xfer_size_cntr_width); ++ ++ /* ++ * Set the SRP sucess bit for FS-I2c ++ */ ++ core_if->srp_success = 0; ++ core_if->srp_timer_started = 0; ++ ++ /* ++ * Create new workqueue and init works ++ */ ++ core_if->wq_otg = DWC_WORKQ_ALLOC("dwc_otg"); ++ if (core_if->wq_otg == 0) { ++ DWC_WARN("DWC_WORKQ_ALLOC failed\n"); ++ DWC_FREE(host_if); ++ DWC_FREE(dev_if); ++ DWC_FREE(core_if); ++ return 0; ++ } ++ ++ core_if->snpsid = DWC_READ_REG32(&core_if->core_global_regs->gsnpsid); ++ ++ DWC_PRINTF("Core Release: %x.%x%x%x\n", ++ (core_if->snpsid >> 12 & 0xF), ++ (core_if->snpsid >> 8 & 0xF), ++ (core_if->snpsid >> 4 & 0xF), (core_if->snpsid & 0xF)); ++ ++ core_if->wkp_timer = DWC_TIMER_ALLOC("Wake Up Timer", ++ w_wakeup_detected, core_if); ++ if (core_if->wkp_timer == 0) { ++ DWC_WARN("DWC_TIMER_ALLOC failed\n"); ++ DWC_FREE(host_if); ++ DWC_FREE(dev_if); ++ DWC_WORKQ_FREE(core_if->wq_otg); ++ DWC_FREE(core_if); ++ return 0; ++ } ++ ++ if (dwc_otg_setup_params(core_if)) { ++ DWC_WARN("Error while setting core params\n"); ++ } ++ ++ core_if->hibernation_suspend = 0; ++ ++ /** ADP initialization */ ++ dwc_otg_adp_init(core_if); ++ ++ return core_if; ++} ++ ++/** ++ * This function frees the structures allocated by dwc_otg_cil_init(). ++ * ++ * @param core_if The core interface pointer returned from ++ * dwc_otg_cil_init(). ++ * ++ */ ++void dwc_otg_cil_remove(dwc_otg_core_if_t * core_if) ++{ ++ dctl_data_t dctl = {.d32 = 0 }; ++ DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if); ++ ++ /* Disable all interrupts */ ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 1, 0); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0); ++ ++ dctl.b.sftdiscon = 1; ++ if (core_if->snpsid >= OTG_CORE_REV_3_00a) { ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, ++ dctl.d32); ++ } ++ ++ if (core_if->wq_otg) { ++ DWC_WORKQ_WAIT_WORK_DONE(core_if->wq_otg, 500); ++ DWC_WORKQ_FREE(core_if->wq_otg); ++ } ++ if (core_if->dev_if) { ++ DWC_FREE(core_if->dev_if); ++ } ++ if (core_if->host_if) { ++ DWC_FREE(core_if->host_if); ++ } ++ ++ /** Remove ADP Stuff */ ++ dwc_otg_adp_remove(core_if); ++ if (core_if->core_params) { ++ DWC_FREE(core_if->core_params); ++ } ++ if (core_if->wkp_timer) { ++ DWC_TIMER_FREE(core_if->wkp_timer); ++ } ++ if (core_if->srp_timer) { ++ DWC_TIMER_FREE(core_if->srp_timer); ++ } ++ DWC_FREE(core_if); ++} ++ ++/** ++ * This function enables the controller's Global Interrupt in the AHB Config ++ * register. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * core_if) ++{ ++ gahbcfg_data_t ahbcfg = {.d32 = 0 }; ++ ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32); ++} ++ ++/** ++ * This function disables the controller's Global Interrupt in the AHB Config ++ * register. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * core_if) ++{ ++ gahbcfg_data_t ahbcfg = {.d32 = 0 }; ++ ahbcfg.b.glblintrmsk = 1; /* Disable interrupts */ ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0); ++} ++ ++/** ++ * This function initializes the commmon interrupts, used in both ++ * device and host modes. ++ * ++ * @param core_if Programming view of the DWC_otg controller ++ * ++ */ ++static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t * core_if) ++{ ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ /* Clear any pending OTG Interrupts */ ++ DWC_WRITE_REG32(&global_regs->gotgint, 0xFFFFFFFF); ++ ++ /* Clear any pending interrupts */ ++ DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF); ++ ++ /* ++ * Enable the interrupts in the GINTMSK. ++ */ ++ intr_mask.b.modemismatch = 1; ++ intr_mask.b.otgintr = 1; ++ ++ if (!core_if->dma_enable) { ++ intr_mask.b.rxstsqlvl = 1; ++ } ++ ++ intr_mask.b.conidstschng = 1; ++ intr_mask.b.wkupintr = 1; ++ intr_mask.b.disconnect = 0; ++ intr_mask.b.usbsuspend = 1; ++ intr_mask.b.sessreqintr = 1; ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ if (core_if->core_params->lpm_enable) { ++ intr_mask.b.lpmtranrcvd = 1; ++ } ++#endif ++ DWC_WRITE_REG32(&global_regs->gintmsk, intr_mask.d32); ++} ++ ++/* ++ * The restore operation is modified to support Synopsys Emulated Powerdown and ++ * Hibernation. This function is for exiting from Device mode hibernation by ++ * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup. ++ * @param core_if Programming view of DWC_otg controller. ++ * @param rem_wakeup - indicates whether resume is initiated by Device or Host. ++ * @param reset - indicates whether resume is initiated by Reset. ++ */ ++int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if, ++ int rem_wakeup, int reset) ++{ ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ dctl_data_t dctl = {.d32 = 0 }; ++ ++ int timeout = 2000; ++ ++ if (!core_if->hibernation_suspend) { ++ DWC_PRINTF("Already exited from Hibernation\n"); ++ return 1; ++ } ++ ++ DWC_DEBUGPL(DBG_PCD, "%s called\n", __FUNCTION__); ++ /* Switch-on voltage to the core */ ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Reset core */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Assert Restore signal */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.restore = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Disable power clamps */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnclmp = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ if (rem_wakeup) { ++ dwc_udelay(70); ++ } ++ ++ /* Deassert Reset core */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Disable PMU interrupt */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /* Mask interrupts from gpwrdn */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.connect_det_msk = 1; ++ gpwrdn.b.srp_det_msk = 1; ++ gpwrdn.b.disconn_det_msk = 1; ++ gpwrdn.b.rst_det_msk = 1; ++ gpwrdn.b.lnstchng_msk = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /* Indicates that we are going out from hibernation */ ++ core_if->hibernation_suspend = 0; ++ ++ /* ++ * Set Restore Essential Regs bit in PCGCCTL register, restore_mode = 1 ++ * indicates restore from remote_wakeup ++ */ ++ restore_essential_regs(core_if, rem_wakeup, 0); ++ ++ /* ++ * Wait a little for seeing new value of variable hibernation_suspend if ++ * Restore done interrupt received before polling ++ */ ++ dwc_udelay(10); ++ ++ if (core_if->hibernation_suspend == 0) { ++ /* ++ * Wait For Restore_done Interrupt. This mechanism of polling the ++ * interrupt is introduced to avoid any possible race conditions ++ */ ++ do { ++ gintsts_data_t gintsts; ++ gintsts.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->gintsts); ++ if (gintsts.b.restoredone) { ++ gintsts.d32 = 0; ++ gintsts.b.restoredone = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs-> ++ gintsts, gintsts.d32); ++ DWC_PRINTF("Restore Done Interrupt seen\n"); ++ break; ++ } ++ dwc_udelay(10); ++ } while (--timeout); ++ if (!timeout) { ++ DWC_PRINTF("Restore Done interrupt wasn't generated here\n"); ++ } ++ } ++ /* Clear all pending interupts */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); ++ ++ /* De-assert Restore */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.restore = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ if (!rem_wakeup) { ++ pcgcctl.d32 = 0; ++ pcgcctl.b.rstpdwnmodule = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0); ++ } ++ ++ /* Restore GUSBCFG and DCFG */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, ++ core_if->gr_backup->gusbcfg_local); ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, ++ core_if->dr_backup->dcfg); ++ ++ /* De-assert Wakeup Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ if (!rem_wakeup) { ++ /* Set Device programming done bit */ ++ dctl.b.pwronprgdone = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32); ++ } else { ++ /* Start Remote Wakeup Signaling */ ++ dctl.d32 = core_if->dr_backup->dctl; ++ dctl.b.rmtwkupsig = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32); ++ } ++ ++ dwc_mdelay(2); ++ /* Clear all pending interupts */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); ++ ++ /* Restore global registers */ ++ dwc_otg_restore_global_regs(core_if); ++ /* Restore device global registers */ ++ dwc_otg_restore_dev_regs(core_if, rem_wakeup); ++ ++ if (rem_wakeup) { ++ dwc_mdelay(7); ++ dctl.d32 = 0; ++ dctl.b.rmtwkupsig = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0); ++ } ++ ++ core_if->hibernation_suspend = 0; ++ /* The core will be in ON STATE */ ++ core_if->lx_state = DWC_OTG_L0; ++ DWC_PRINTF("Hibernation recovery completes here\n"); ++ ++ return 1; ++} ++ ++/* ++ * The restore operation is modified to support Synopsys Emulated Powerdown and ++ * Hibernation. This function is for exiting from Host mode hibernation by ++ * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup. ++ * @param core_if Programming view of DWC_otg controller. ++ * @param rem_wakeup - indicates whether resume is initiated by Device or Host. ++ * @param reset - indicates whether resume is initiated by Reset. ++ */ ++int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if, ++ int rem_wakeup, int reset) ++{ ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ hprt0_data_t hprt0 = {.d32 = 0 }; ++ ++ int timeout = 2000; ++ ++ DWC_DEBUGPL(DBG_HCD, "%s called\n", __FUNCTION__); ++ /* Switch-on voltage to the core */ ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Reset core */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Assert Restore signal */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.restore = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Disable power clamps */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnclmp = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ if (!rem_wakeup) { ++ dwc_udelay(50); ++ } ++ ++ /* Deassert Reset core */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Disable PMU interrupt */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.connect_det_msk = 1; ++ gpwrdn.b.srp_det_msk = 1; ++ gpwrdn.b.disconn_det_msk = 1; ++ gpwrdn.b.rst_det_msk = 1; ++ gpwrdn.b.lnstchng_msk = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /* Indicates that we are going out from hibernation */ ++ core_if->hibernation_suspend = 0; ++ ++ /* Set Restore Essential Regs bit in PCGCCTL register */ ++ restore_essential_regs(core_if, rem_wakeup, 1); ++ ++ /* Wait a little for seeing new value of variable hibernation_suspend if ++ * Restore done interrupt received before polling */ ++ dwc_udelay(10); ++ ++ if (core_if->hibernation_suspend == 0) { ++ /* Wait For Restore_done Interrupt. This mechanism of polling the ++ * interrupt is introduced to avoid any possible race conditions ++ */ ++ do { ++ gintsts_data_t gintsts; ++ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts); ++ if (gintsts.b.restoredone) { ++ gintsts.d32 = 0; ++ gintsts.b.restoredone = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ DWC_DEBUGPL(DBG_HCD,"Restore Done Interrupt seen\n"); ++ break; ++ } ++ dwc_udelay(10); ++ } while (--timeout); ++ if (!timeout) { ++ DWC_WARN("Restore Done interrupt wasn't generated\n"); ++ } ++ } ++ ++ /* Set the flag's value to 0 again after receiving restore done interrupt */ ++ core_if->hibernation_suspend = 0; ++ ++ /* This step is not described in functional spec but if not wait for this ++ * delay, mismatch interrupts occurred because just after restore core is ++ * in Device mode(gintsts.curmode == 0) */ ++ dwc_mdelay(100); ++ ++ /* Clear all pending interrupts */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); ++ ++ /* De-assert Restore */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.restore = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Restore GUSBCFG and HCFG */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, ++ core_if->gr_backup->gusbcfg_local); ++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, ++ core_if->hr_backup->hcfg_local); ++ ++ /* De-assert Wakeup Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Start the Resume operation by programming HPRT0 */ ++ hprt0.d32 = core_if->hr_backup->hprt0_local; ++ hprt0.b.prtpwr = 1; ++ hprt0.b.prtena = 0; ++ hprt0.b.prtsusp = 0; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ ++ DWC_PRINTF("Resume Starts Now\n"); ++ if (!reset) { // Indicates it is Resume Operation ++ hprt0.d32 = core_if->hr_backup->hprt0_local; ++ hprt0.b.prtres = 1; ++ hprt0.b.prtpwr = 1; ++ hprt0.b.prtena = 0; ++ hprt0.b.prtsusp = 0; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ ++ if (!rem_wakeup) ++ hprt0.b.prtres = 0; ++ /* Wait for Resume time and then program HPRT again */ ++ dwc_mdelay(100); ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ ++ } else { // Indicates it is Reset Operation ++ hprt0.d32 = core_if->hr_backup->hprt0_local; ++ hprt0.b.prtrst = 1; ++ hprt0.b.prtpwr = 1; ++ hprt0.b.prtena = 0; ++ hprt0.b.prtsusp = 0; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ /* Wait for Reset time and then program HPRT again */ ++ dwc_mdelay(60); ++ hprt0.b.prtrst = 0; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ } ++ /* Clear all interrupt status */ ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtconndet = 1; ++ hprt0.b.prtenchng = 1; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ ++ /* Clear all pending interupts */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); ++ ++ /* Restore global registers */ ++ dwc_otg_restore_global_regs(core_if); ++ /* Restore host global registers */ ++ dwc_otg_restore_host_regs(core_if, reset); ++ ++ /* The core will be in ON STATE */ ++ core_if->lx_state = DWC_OTG_L0; ++ DWC_PRINTF("Hibernation recovery is complete here\n"); ++ return 0; ++} ++ ++/** Saves some register values into system memory. */ ++int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if) ++{ ++ struct dwc_otg_global_regs_backup *gr; ++ int i; ++ ++ gr = core_if->gr_backup; ++ if (!gr) { ++ gr = DWC_ALLOC(sizeof(*gr)); ++ if (!gr) { ++ return -DWC_E_NO_MEMORY; ++ } ++ core_if->gr_backup = gr; ++ } ++ ++ gr->gotgctl_local = DWC_READ_REG32(&core_if->core_global_regs->gotgctl); ++ gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk); ++ gr->gahbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg); ++ gr->gusbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); ++ gr->grxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz); ++ gr->gnptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz); ++ gr->hptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz); ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ gr->glpmcfg_local = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++#endif ++ gr->gi2cctl_local = DWC_READ_REG32(&core_if->core_global_regs->gi2cctl); ++ gr->pcgcctl_local = DWC_READ_REG32(core_if->pcgcctl); ++ gr->gdfifocfg_local = ++ DWC_READ_REG32(&core_if->core_global_regs->gdfifocfg); ++ for (i = 0; i < MAX_EPS_CHANNELS; i++) { ++ gr->dtxfsiz_local[i] = ++ DWC_READ_REG32(&(core_if->core_global_regs->dtxfsiz[i])); ++ } ++ ++ DWC_DEBUGPL(DBG_ANY, "===========Backing Global registers==========\n"); ++ DWC_DEBUGPL(DBG_ANY, "Backed up gotgctl = %08x\n", gr->gotgctl_local); ++ DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk = %08x\n", gr->gintmsk_local); ++ DWC_DEBUGPL(DBG_ANY, "Backed up gahbcfg = %08x\n", gr->gahbcfg_local); ++ DWC_DEBUGPL(DBG_ANY, "Backed up gusbcfg = %08x\n", gr->gusbcfg_local); ++ DWC_DEBUGPL(DBG_ANY, "Backed up grxfsiz = %08x\n", gr->grxfsiz_local); ++ DWC_DEBUGPL(DBG_ANY, "Backed up gnptxfsiz = %08x\n", ++ gr->gnptxfsiz_local); ++ DWC_DEBUGPL(DBG_ANY, "Backed up hptxfsiz = %08x\n", ++ gr->hptxfsiz_local); ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ DWC_DEBUGPL(DBG_ANY, "Backed up glpmcfg = %08x\n", gr->glpmcfg_local); ++#endif ++ DWC_DEBUGPL(DBG_ANY, "Backed up gi2cctl = %08x\n", gr->gi2cctl_local); ++ DWC_DEBUGPL(DBG_ANY, "Backed up pcgcctl = %08x\n", gr->pcgcctl_local); ++ DWC_DEBUGPL(DBG_ANY,"Backed up gdfifocfg = %08x\n",gr->gdfifocfg_local); ++ ++ return 0; ++} ++ ++/** Saves GINTMSK register before setting the msk bits. */ ++int dwc_otg_save_gintmsk_reg(dwc_otg_core_if_t * core_if) ++{ ++ struct dwc_otg_global_regs_backup *gr; ++ ++ gr = core_if->gr_backup; ++ if (!gr) { ++ gr = DWC_ALLOC(sizeof(*gr)); ++ if (!gr) { ++ return -DWC_E_NO_MEMORY; ++ } ++ core_if->gr_backup = gr; ++ } ++ ++ gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk); ++ ++ DWC_DEBUGPL(DBG_ANY,"=============Backing GINTMSK registers============\n"); ++ DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk = %08x\n", gr->gintmsk_local); ++ ++ return 0; ++} ++ ++int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if) ++{ ++ struct dwc_otg_dev_regs_backup *dr; ++ int i; ++ ++ dr = core_if->dr_backup; ++ if (!dr) { ++ dr = DWC_ALLOC(sizeof(*dr)); ++ if (!dr) { ++ return -DWC_E_NO_MEMORY; ++ } ++ core_if->dr_backup = dr; ++ } ++ ++ dr->dcfg = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); ++ dr->dctl = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl); ++ dr->daintmsk = ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk); ++ dr->diepmsk = ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->diepmsk); ++ dr->doepmsk = ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->doepmsk); ++ ++ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) { ++ dr->diepctl[i] = ++ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl); ++ dr->dieptsiz[i] = ++ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz); ++ dr->diepdma[i] = ++ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma); ++ } ++ ++ DWC_DEBUGPL(DBG_ANY, ++ "=============Backing Host registers==============\n"); ++ DWC_DEBUGPL(DBG_ANY, "Backed up dcfg = %08x\n", dr->dcfg); ++ DWC_DEBUGPL(DBG_ANY, "Backed up dctl = %08x\n", dr->dctl); ++ DWC_DEBUGPL(DBG_ANY, "Backed up daintmsk = %08x\n", ++ dr->daintmsk); ++ DWC_DEBUGPL(DBG_ANY, "Backed up diepmsk = %08x\n", dr->diepmsk); ++ DWC_DEBUGPL(DBG_ANY, "Backed up doepmsk = %08x\n", dr->doepmsk); ++ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) { ++ DWC_DEBUGPL(DBG_ANY, "Backed up diepctl[%d] = %08x\n", i, ++ dr->diepctl[i]); ++ DWC_DEBUGPL(DBG_ANY, "Backed up dieptsiz[%d] = %08x\n", ++ i, dr->dieptsiz[i]); ++ DWC_DEBUGPL(DBG_ANY, "Backed up diepdma[%d] = %08x\n", i, ++ dr->diepdma[i]); ++ } ++ ++ return 0; ++} ++ ++int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if) ++{ ++ struct dwc_otg_host_regs_backup *hr; ++ int i; ++ ++ hr = core_if->hr_backup; ++ if (!hr) { ++ hr = DWC_ALLOC(sizeof(*hr)); ++ if (!hr) { ++ return -DWC_E_NO_MEMORY; ++ } ++ core_if->hr_backup = hr; ++ } ++ ++ hr->hcfg_local = ++ DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg); ++ hr->haintmsk_local = ++ DWC_READ_REG32(&core_if->host_if->host_global_regs->haintmsk); ++ for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) { ++ hr->hcintmsk_local[i] = ++ DWC_READ_REG32(&core_if->host_if->hc_regs[i]->hcintmsk); ++ } ++ hr->hprt0_local = DWC_READ_REG32(core_if->host_if->hprt0); ++ hr->hfir_local = ++ DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir); ++ ++ DWC_DEBUGPL(DBG_ANY, ++ "=============Backing Host registers===============\n"); ++ DWC_DEBUGPL(DBG_ANY, "Backed up hcfg = %08x\n", ++ hr->hcfg_local); ++ DWC_DEBUGPL(DBG_ANY, "Backed up haintmsk = %08x\n", hr->haintmsk_local); ++ for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) { ++ DWC_DEBUGPL(DBG_ANY, "Backed up hcintmsk[%02d]=%08x\n", i, ++ hr->hcintmsk_local[i]); ++ } ++ DWC_DEBUGPL(DBG_ANY, "Backed up hprt0 = %08x\n", ++ hr->hprt0_local); ++ DWC_DEBUGPL(DBG_ANY, "Backed up hfir = %08x\n", ++ hr->hfir_local); ++ ++ return 0; ++} ++ ++int dwc_otg_restore_global_regs(dwc_otg_core_if_t *core_if) ++{ ++ struct dwc_otg_global_regs_backup *gr; ++ int i; ++ ++ gr = core_if->gr_backup; ++ if (!gr) { ++ return -DWC_E_INVALID; ++ } ++ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, gr->gotgctl_local); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gr->gintmsk_local); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gr->gusbcfg_local); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gr->gahbcfg_local); ++ DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, gr->grxfsiz_local); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz, ++ gr->gnptxfsiz_local); ++ DWC_WRITE_REG32(&core_if->core_global_regs->hptxfsiz, ++ gr->hptxfsiz_local); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gdfifocfg, ++ gr->gdfifocfg_local); ++ for (i = 0; i < MAX_EPS_CHANNELS; i++) { ++ DWC_WRITE_REG32(&core_if->core_global_regs->dtxfsiz[i], ++ gr->dtxfsiz_local[i]); ++ } ++ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); ++ DWC_WRITE_REG32(core_if->host_if->hprt0, 0x0000100A); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, ++ (gr->gahbcfg_local)); ++ return 0; ++} ++ ++int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if, int rem_wakeup) ++{ ++ struct dwc_otg_dev_regs_backup *dr; ++ int i; ++ ++ dr = core_if->dr_backup; ++ ++ if (!dr) { ++ return -DWC_E_INVALID; ++ } ++ ++ if (!rem_wakeup) { ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, ++ dr->dctl); ++ } ++ ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, dr->daintmsk); ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, dr->diepmsk); ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, dr->doepmsk); ++ ++ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) { ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz, dr->dieptsiz[i]); ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma, dr->diepdma[i]); ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl, dr->diepctl[i]); ++ } ++ ++ return 0; ++} ++ ++int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset) ++{ ++ struct dwc_otg_host_regs_backup *hr; ++ int i; ++ hr = core_if->hr_backup; ++ ++ if (!hr) { ++ return -DWC_E_INVALID; ++ } ++ ++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hr->hcfg_local); ++ //if (!reset) ++ //{ ++ // DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hr->hfir_local); ++ //} ++ ++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk, ++ hr->haintmsk_local); ++ for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) { ++ DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk, ++ hr->hcintmsk_local[i]); ++ } ++ ++ return 0; ++} ++ ++int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if) ++{ ++ struct dwc_otg_global_regs_backup *gr; ++ ++ gr = core_if->gr_backup; ++ ++ /* Restore values for LPM and I2C */ ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, gr->glpmcfg_local); ++#endif ++ DWC_WRITE_REG32(&core_if->core_global_regs->gi2cctl, gr->gi2cctl_local); ++ ++ return 0; ++} ++ ++int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode, int is_host) ++{ ++ struct dwc_otg_global_regs_backup *gr; ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ gahbcfg_data_t gahbcfg = {.d32 = 0 }; ++ gusbcfg_data_t gusbcfg = {.d32 = 0 }; ++ gintmsk_data_t gintmsk = {.d32 = 0 }; ++ ++ /* Restore LPM and I2C registers */ ++ restore_lpm_i2c_regs(core_if); ++ ++ /* Set PCGCCTL to 0 */ ++ DWC_WRITE_REG32(core_if->pcgcctl, 0x00000000); ++ ++ gr = core_if->gr_backup; ++ /* Load restore values for [31:14] bits */ ++ DWC_WRITE_REG32(core_if->pcgcctl, ++ ((gr->pcgcctl_local & 0xffffc000) | 0x00020000)); ++ ++ /* Umnask global Interrupt in GAHBCFG and restore it */ ++ gahbcfg.d32 = gr->gahbcfg_local; ++ gahbcfg.b.glblintrmsk = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gahbcfg.d32); ++ ++ /* Clear all pending interupts */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); ++ ++ /* Unmask restore done interrupt */ ++ gintmsk.b.restoredone = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32); ++ ++ /* Restore GUSBCFG and HCFG/DCFG */ ++ gusbcfg.d32 = core_if->gr_backup->gusbcfg_local; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32); ++ ++ if (is_host) { ++ hcfg_data_t hcfg = {.d32 = 0 }; ++ hcfg.d32 = core_if->hr_backup->hcfg_local; ++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, ++ hcfg.d32); ++ ++ /* Load restore values for [31:14] bits */ ++ pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000; ++ pcgcctl.d32 = gr->pcgcctl_local | 0x00020000; ++ ++ if (rmode) ++ pcgcctl.b.restoremode = 1; ++ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32); ++ dwc_udelay(10); ++ ++ /* Load restore values for [31:14] bits and set EssRegRestored bit */ ++ pcgcctl.d32 = gr->pcgcctl_local | 0xffffc000; ++ pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000; ++ pcgcctl.b.ess_reg_restored = 1; ++ if (rmode) ++ pcgcctl.b.restoremode = 1; ++ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32); ++ } else { ++ dcfg_data_t dcfg = {.d32 = 0 }; ++ dcfg.d32 = core_if->dr_backup->dcfg; ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32); ++ ++ /* Load restore values for [31:14] bits */ ++ pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000; ++ pcgcctl.d32 = gr->pcgcctl_local | 0x00020000; ++ if (!rmode) { ++ pcgcctl.d32 |= 0x208; ++ } ++ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32); ++ dwc_udelay(10); ++ ++ /* Load restore values for [31:14] bits */ ++ pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000; ++ pcgcctl.d32 = gr->pcgcctl_local | 0x00020000; ++ pcgcctl.b.ess_reg_restored = 1; ++ if (!rmode) ++ pcgcctl.d32 |= 0x208; ++ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32); ++ } ++ ++ return 0; ++} ++ ++/** ++ * Initializes the FSLSPClkSel field of the HCFG register depending on the PHY ++ * type. ++ */ ++static void init_fslspclksel(dwc_otg_core_if_t * core_if) ++{ ++ uint32_t val; ++ hcfg_data_t hcfg; ++ ++ if (((core_if->hwcfg2.b.hs_phy_type == 2) && ++ (core_if->hwcfg2.b.fs_phy_type == 1) && ++ (core_if->core_params->ulpi_fs_ls)) || ++ (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) { ++ /* Full speed PHY */ ++ val = DWC_HCFG_48_MHZ; ++ } else { ++ /* High speed PHY running at full speed or high speed */ ++ val = DWC_HCFG_30_60_MHZ; ++ } ++ ++ DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val); ++ hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg); ++ hcfg.b.fslspclksel = val; ++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32); ++} ++ ++/** ++ * Initializes the DevSpd field of the DCFG register depending on the PHY type ++ * and the enumeration speed of the device. ++ */ ++static void init_devspd(dwc_otg_core_if_t * core_if) ++{ ++ uint32_t val; ++ dcfg_data_t dcfg; ++ ++ if (((core_if->hwcfg2.b.hs_phy_type == 2) && ++ (core_if->hwcfg2.b.fs_phy_type == 1) && ++ (core_if->core_params->ulpi_fs_ls)) || ++ (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) { ++ /* Full speed PHY */ ++ val = 0x3; ++ } else if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) { ++ /* High speed PHY running at full speed */ ++ val = 0x1; ++ } else { ++ /* High speed PHY running at high speed */ ++ val = 0x0; ++ } ++ ++ DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val); ++ ++ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); ++ dcfg.b.devspd = val; ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32); ++} ++ ++/** ++ * This function calculates the number of IN EPS ++ * using GHWCFG1 and GHWCFG2 registers values ++ * ++ * @param core_if Programming view of the DWC_otg controller ++ */ ++static uint32_t calc_num_in_eps(dwc_otg_core_if_t * core_if) ++{ ++ uint32_t num_in_eps = 0; ++ uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep; ++ uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 3; ++ uint32_t num_tx_fifos = core_if->hwcfg4.b.num_in_eps; ++ int i; ++ ++ for (i = 0; i < num_eps; ++i) { ++ if (!(hwcfg1 & 0x1)) ++ num_in_eps++; ++ ++ hwcfg1 >>= 2; ++ } ++ ++ if (core_if->hwcfg4.b.ded_fifo_en) { ++ num_in_eps = ++ (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps; ++ } ++ ++ return num_in_eps; ++} ++ ++/** ++ * This function calculates the number of OUT EPS ++ * using GHWCFG1 and GHWCFG2 registers values ++ * ++ * @param core_if Programming view of the DWC_otg controller ++ */ ++static uint32_t calc_num_out_eps(dwc_otg_core_if_t * core_if) ++{ ++ uint32_t num_out_eps = 0; ++ uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep; ++ uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 2; ++ int i; ++ ++ for (i = 0; i < num_eps; ++i) { ++ if (!(hwcfg1 & 0x1)) ++ num_out_eps++; ++ ++ hwcfg1 >>= 2; ++ } ++ return num_out_eps; ++} ++ ++/** ++ * This function initializes the DWC_otg controller registers and ++ * prepares the core for device mode or host mode operation. ++ * ++ * @param core_if Programming view of the DWC_otg controller ++ * ++ */ ++void dwc_otg_core_init(dwc_otg_core_if_t * core_if) ++{ ++ int i = 0; ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ gahbcfg_data_t ahbcfg = {.d32 = 0 }; ++ gusbcfg_data_t usbcfg = {.d32 = 0 }; ++ gi2cctl_data_t i2cctl = {.d32 = 0 }; ++ ++ DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p) regs at %p\n", ++ core_if, global_regs); ++ ++ /* Common Initialization */ ++ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg); ++ ++ /* Program the ULPI External VBUS bit if needed */ ++ usbcfg.b.ulpi_ext_vbus_drv = ++ (core_if->core_params->phy_ulpi_ext_vbus == ++ DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0; ++ ++ /* Set external TS Dline pulsing */ ++ usbcfg.b.term_sel_dl_pulse = ++ (core_if->core_params->ts_dline == 1) ? 1 : 0; ++ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32); ++ ++ /* Reset the Controller */ ++ dwc_otg_core_reset(core_if); ++ ++ core_if->adp_enable = core_if->core_params->adp_supp_enable; ++ core_if->power_down = core_if->core_params->power_down; ++ core_if->otg_sts = 0; ++ ++ /* Initialize parameters from Hardware configuration registers. */ ++ dev_if->num_in_eps = calc_num_in_eps(core_if); ++ dev_if->num_out_eps = calc_num_out_eps(core_if); ++ ++ DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n", ++ core_if->hwcfg4.b.num_dev_perio_in_ep); ++ ++ for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) { ++ dev_if->perio_tx_fifo_size[i] = ++ DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16; ++ DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n", ++ i, dev_if->perio_tx_fifo_size[i]); ++ } ++ ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { ++ dev_if->tx_fifo_size[i] = ++ DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16; ++ DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n", ++ i, dev_if->tx_fifo_size[i]); ++ } ++ ++ core_if->total_fifo_size = core_if->hwcfg3.b.dfifo_depth; ++ core_if->rx_fifo_size = DWC_READ_REG32(&global_regs->grxfsiz); ++ core_if->nperio_tx_fifo_size = ++ DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16; ++ ++ DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", core_if->total_fifo_size); ++ DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", core_if->rx_fifo_size); ++ DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n", ++ core_if->nperio_tx_fifo_size); ++ ++ /* This programming sequence needs to happen in FS mode before any other ++ * programming occurs */ ++ if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) && ++ (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) { ++ /* If FS mode with FS PHY */ ++ ++ /* core_init() is now called on every switch so only call the ++ * following for the first time through. */ ++ if (!core_if->phy_init_done) { ++ core_if->phy_init_done = 1; ++ DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n"); ++ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg); ++ usbcfg.b.physel = 1; ++ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32); ++ ++ /* Reset after a PHY select */ ++ dwc_otg_core_reset(core_if); ++ } ++ ++ /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also ++ * do this on HNP Dev/Host mode switches (done in dev_init and ++ * host_init). */ ++ if (dwc_otg_is_host_mode(core_if)) { ++ init_fslspclksel(core_if); ++ } else { ++ init_devspd(core_if); ++ } ++ ++ if (core_if->core_params->i2c_enable) { ++ DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n"); ++ /* Program GUSBCFG.OtgUtmifsSel to I2C */ ++ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg); ++ usbcfg.b.otgutmifssel = 1; ++ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32); ++ ++ /* Program GI2CCTL.I2CEn */ ++ i2cctl.d32 = DWC_READ_REG32(&global_regs->gi2cctl); ++ i2cctl.b.i2cdevaddr = 1; ++ i2cctl.b.i2cen = 0; ++ DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32); ++ i2cctl.b.i2cen = 1; ++ DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32); ++ } ++ ++ } /* endif speed == DWC_SPEED_PARAM_FULL */ ++ else { ++ /* High speed PHY. */ ++ if (!core_if->phy_init_done) { ++ core_if->phy_init_done = 1; ++ /* HS PHY parameters. These parameters are preserved ++ * during soft reset so only program the first time. Do ++ * a soft reset immediately after setting phyif. */ ++ ++ if (core_if->core_params->phy_type == 2) { ++ /* ULPI interface */ ++ usbcfg.b.ulpi_utmi_sel = 1; ++ usbcfg.b.phyif = 0; ++ usbcfg.b.ddrsel = ++ core_if->core_params->phy_ulpi_ddr; ++ } else if (core_if->core_params->phy_type == 1) { ++ /* UTMI+ interface */ ++ usbcfg.b.ulpi_utmi_sel = 0; ++ if (core_if->core_params->phy_utmi_width == 16) { ++ usbcfg.b.phyif = 1; ++ ++ } else { ++ usbcfg.b.phyif = 0; ++ } ++ } else { ++ DWC_ERROR("FS PHY TYPE\n"); ++ } ++ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32); ++ /* Reset after setting the PHY parameters */ ++ dwc_otg_core_reset(core_if); ++ } ++ } ++ ++ if ((core_if->hwcfg2.b.hs_phy_type == 2) && ++ (core_if->hwcfg2.b.fs_phy_type == 1) && ++ (core_if->core_params->ulpi_fs_ls)) { ++ DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n"); ++ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg); ++ usbcfg.b.ulpi_fsls = 1; ++ usbcfg.b.ulpi_clk_sus_m = 1; ++ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32); ++ } else { ++ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg); ++ usbcfg.b.ulpi_fsls = 0; ++ usbcfg.b.ulpi_clk_sus_m = 0; ++ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32); ++ } ++ ++ /* Program the GAHBCFG Register. */ ++ switch (core_if->hwcfg2.b.architecture) { ++ ++ case DWC_SLAVE_ONLY_ARCH: ++ DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n"); ++ ahbcfg.b.nptxfemplvl_txfemplvl = ++ DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY; ++ ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY; ++ core_if->dma_enable = 0; ++ core_if->dma_desc_enable = 0; ++ break; ++ ++ case DWC_EXT_DMA_ARCH: ++ DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n"); ++ { ++ uint8_t brst_sz = core_if->core_params->dma_burst_size; ++ ahbcfg.b.hburstlen = 0; ++ while (brst_sz > 1) { ++ ahbcfg.b.hburstlen++; ++ brst_sz >>= 1; ++ } ++ } ++ core_if->dma_enable = (core_if->core_params->dma_enable != 0); ++ core_if->dma_desc_enable = ++ (core_if->core_params->dma_desc_enable != 0); ++ break; ++ ++ case DWC_INT_DMA_ARCH: ++ DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n"); ++ /* Old value was DWC_GAHBCFG_INT_DMA_BURST_INCR - done for ++ Host mode ISOC in issue fix - vahrama */ ++ /* Broadcom had altered to (1<<3)|(0<<0) - WRESP=1, max 4 beats */ ++ ahbcfg.b.hburstlen = (1<<3)|(0<<0);//DWC_GAHBCFG_INT_DMA_BURST_INCR4; ++ core_if->dma_enable = (core_if->core_params->dma_enable != 0); ++ core_if->dma_desc_enable = ++ (core_if->core_params->dma_desc_enable != 0); ++ break; ++ ++ } ++ if (core_if->dma_enable) { ++ if (core_if->dma_desc_enable) { ++ DWC_PRINTF("Using Descriptor DMA mode\n"); ++ } else { ++ DWC_PRINTF("Using Buffer DMA mode\n"); ++ ++ } ++ } else { ++ DWC_PRINTF("Using Slave mode\n"); ++ core_if->dma_desc_enable = 0; ++ } ++ ++ if (core_if->core_params->ahb_single) { ++ ahbcfg.b.ahbsingle = 1; ++ } ++ ++ ahbcfg.b.dmaenable = core_if->dma_enable; ++ DWC_WRITE_REG32(&global_regs->gahbcfg, ahbcfg.d32); ++ ++ core_if->en_multiple_tx_fifo = core_if->hwcfg4.b.ded_fifo_en; ++ ++ core_if->pti_enh_enable = core_if->core_params->pti_enable != 0; ++ core_if->multiproc_int_enable = core_if->core_params->mpi_enable; ++ DWC_PRINTF("Periodic Transfer Interrupt Enhancement - %s\n", ++ ((core_if->pti_enh_enable) ? "enabled" : "disabled")); ++ DWC_PRINTF("Multiprocessor Interrupt Enhancement - %s\n", ++ ((core_if->multiproc_int_enable) ? "enabled" : "disabled")); ++ ++ /* ++ * Program the GUSBCFG register. ++ */ ++ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg); ++ ++ switch (core_if->hwcfg2.b.op_mode) { ++ case DWC_MODE_HNP_SRP_CAPABLE: ++ usbcfg.b.hnpcap = (core_if->core_params->otg_cap == ++ DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE); ++ usbcfg.b.srpcap = (core_if->core_params->otg_cap != ++ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); ++ break; ++ ++ case DWC_MODE_SRP_ONLY_CAPABLE: ++ usbcfg.b.hnpcap = 0; ++ usbcfg.b.srpcap = (core_if->core_params->otg_cap != ++ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); ++ break; ++ ++ case DWC_MODE_NO_HNP_SRP_CAPABLE: ++ usbcfg.b.hnpcap = 0; ++ usbcfg.b.srpcap = 0; ++ break; ++ ++ case DWC_MODE_SRP_CAPABLE_DEVICE: ++ usbcfg.b.hnpcap = 0; ++ usbcfg.b.srpcap = (core_if->core_params->otg_cap != ++ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); ++ break; ++ ++ case DWC_MODE_NO_SRP_CAPABLE_DEVICE: ++ usbcfg.b.hnpcap = 0; ++ usbcfg.b.srpcap = 0; ++ break; ++ ++ case DWC_MODE_SRP_CAPABLE_HOST: ++ usbcfg.b.hnpcap = 0; ++ usbcfg.b.srpcap = (core_if->core_params->otg_cap != ++ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); ++ break; ++ ++ case DWC_MODE_NO_SRP_CAPABLE_HOST: ++ usbcfg.b.hnpcap = 0; ++ usbcfg.b.srpcap = 0; ++ break; ++ } ++ ++ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32); ++ ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ if (core_if->core_params->lpm_enable) { ++ glpmcfg_data_t lpmcfg = {.d32 = 0 }; ++ ++ /* To enable LPM support set lpm_cap_en bit */ ++ lpmcfg.b.lpm_cap_en = 1; ++ ++ /* Make AppL1Res ACK */ ++ lpmcfg.b.appl_resp = 1; ++ ++ /* Retry 3 times */ ++ lpmcfg.b.retry_count = 3; ++ ++ DWC_MODIFY_REG32(&core_if->core_global_regs->glpmcfg, ++ 0, lpmcfg.d32); ++ ++ } ++#endif ++ if (core_if->core_params->ic_usb_cap) { ++ gusbcfg_data_t gusbcfg = {.d32 = 0 }; ++ gusbcfg.b.ic_usb_cap = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gusbcfg, ++ 0, gusbcfg.d32); ++ } ++ { ++ gotgctl_data_t gotgctl = {.d32 = 0 }; ++ gotgctl.b.otgver = core_if->core_params->otg_ver; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl, 0, ++ gotgctl.d32); ++ /* Set OTG version supported */ ++ core_if->otg_ver = core_if->core_params->otg_ver; ++ DWC_PRINTF("OTG VER PARAM: %d, OTG VER FLAG: %d\n", ++ core_if->core_params->otg_ver, core_if->otg_ver); ++ } ++ ++ ++ /* Enable common interrupts */ ++ dwc_otg_enable_common_interrupts(core_if); ++ ++ /* Do device or host intialization based on mode during PCD ++ * and HCD initialization */ ++ if (dwc_otg_is_host_mode(core_if)) { ++ DWC_DEBUGPL(DBG_ANY, "Host Mode\n"); ++ core_if->op_state = A_HOST; ++ } else { ++ DWC_DEBUGPL(DBG_ANY, "Device Mode\n"); ++ core_if->op_state = B_PERIPHERAL; ++#ifdef DWC_DEVICE_ONLY ++ dwc_otg_core_dev_init(core_if); ++#endif ++ } ++} ++ ++/** ++ * This function enables the Device mode interrupts. ++ * ++ * @param core_if Programming view of DWC_otg controller ++ */ ++void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * core_if) ++{ ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ ++ DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__); ++ ++ /* Disable all interrupts. */ ++ DWC_WRITE_REG32(&global_regs->gintmsk, 0); ++ ++ /* Clear any pending interrupts */ ++ DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF); ++ ++ /* Enable the common interrupts */ ++ dwc_otg_enable_common_interrupts(core_if); ++ ++ /* Enable interrupts */ ++ intr_mask.b.usbreset = 1; ++ intr_mask.b.enumdone = 1; ++ /* Disable Disconnect interrupt in Device mode */ ++ intr_mask.b.disconnect = 0; ++ ++ if (!core_if->multiproc_int_enable) { ++ intr_mask.b.inepintr = 1; ++ intr_mask.b.outepintr = 1; ++ } ++ ++ intr_mask.b.erlysuspend = 1; ++ ++ if (core_if->en_multiple_tx_fifo == 0) { ++ intr_mask.b.epmismatch = 1; ++ } ++ ++ //intr_mask.b.incomplisoout = 1; ++ intr_mask.b.incomplisoin = 1; ++ ++/* Enable the ignore frame number for ISOC xfers - MAS */ ++/* Disable to support high bandwith ISOC transfers - manukz */ ++#if 0 ++#ifdef DWC_UTE_PER_IO ++ if (core_if->dma_enable) { ++ if (core_if->dma_desc_enable) { ++ dctl_data_t dctl1 = {.d32 = 0 }; ++ dctl1.b.ifrmnum = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> ++ dctl, 0, dctl1.d32); ++ DWC_DEBUG("----Enabled Ignore frame number (0x%08x)", ++ DWC_READ_REG32(&core_if->dev_if-> ++ dev_global_regs->dctl)); ++ } ++ } ++#endif ++#endif ++#ifdef DWC_EN_ISOC ++ if (core_if->dma_enable) { ++ if (core_if->dma_desc_enable == 0) { ++ if (core_if->pti_enh_enable) { ++ dctl_data_t dctl = {.d32 = 0 }; ++ dctl.b.ifrmnum = 1; ++ DWC_MODIFY_REG32(&core_if-> ++ dev_if->dev_global_regs->dctl, ++ 0, dctl.d32); ++ } else { ++ intr_mask.b.incomplisoin = 1; ++ intr_mask.b.incomplisoout = 1; ++ } ++ } ++ } else { ++ intr_mask.b.incomplisoin = 1; ++ intr_mask.b.incomplisoout = 1; ++ } ++#endif /* DWC_EN_ISOC */ ++ ++ /** @todo NGS: Should this be a module parameter? */ ++#ifdef USE_PERIODIC_EP ++ intr_mask.b.isooutdrop = 1; ++ intr_mask.b.eopframe = 1; ++ intr_mask.b.incomplisoin = 1; ++ intr_mask.b.incomplisoout = 1; ++#endif ++ ++ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32); ++ ++ DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__, ++ DWC_READ_REG32(&global_regs->gintmsk)); ++} ++ ++/** ++ * This function initializes the DWC_otg controller registers for ++ * device mode. ++ * ++ * @param core_if Programming view of DWC_otg controller ++ * ++ */ ++void dwc_otg_core_dev_init(dwc_otg_core_if_t * core_if) ++{ ++ int i; ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ dwc_otg_core_params_t *params = core_if->core_params; ++ dcfg_data_t dcfg = {.d32 = 0 }; ++ depctl_data_t diepctl = {.d32 = 0 }; ++ grstctl_t resetctl = {.d32 = 0 }; ++ uint32_t rx_fifo_size; ++ fifosize_data_t nptxfifosize; ++ fifosize_data_t txfifosize; ++ dthrctl_data_t dthrctl; ++ fifosize_data_t ptxfifosize; ++ uint16_t rxfsiz, nptxfsiz; ++ gdfifocfg_data_t gdfifocfg = {.d32 = 0 }; ++ hwcfg3_data_t hwcfg3 = {.d32 = 0 }; ++ ++ /* Restart the Phy Clock */ ++ DWC_WRITE_REG32(core_if->pcgcctl, 0); ++ ++ /* Device configuration register */ ++ init_devspd(core_if); ++ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg); ++ dcfg.b.descdma = (core_if->dma_desc_enable) ? 1 : 0; ++ dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80; ++ /* Enable Device OUT NAK in case of DDMA mode*/ ++ if (core_if->core_params->dev_out_nak) { ++ dcfg.b.endevoutnak = 1; ++ } ++ ++ if (core_if->core_params->cont_on_bna) { ++ dctl_data_t dctl = {.d32 = 0 }; ++ dctl.b.encontonbna = 1; ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32); ++ } ++ ++ ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32); ++ ++ /* Configure data FIFO sizes */ ++ if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) { ++ DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n", ++ core_if->total_fifo_size); ++ DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n", ++ params->dev_rx_fifo_size); ++ DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n", ++ params->dev_nperio_tx_fifo_size); ++ ++ /* Rx FIFO */ ++ DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n", ++ DWC_READ_REG32(&global_regs->grxfsiz)); ++ ++#ifdef DWC_UTE_CFI ++ core_if->pwron_rxfsiz = DWC_READ_REG32(&global_regs->grxfsiz); ++ core_if->init_rxfsiz = params->dev_rx_fifo_size; ++#endif ++ rx_fifo_size = params->dev_rx_fifo_size; ++ DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fifo_size); ++ ++ DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n", ++ DWC_READ_REG32(&global_regs->grxfsiz)); ++ ++ /** Set Periodic Tx FIFO Mask all bits 0 */ ++ core_if->p_tx_msk = 0; ++ ++ /** Set Tx FIFO Mask all bits 0 */ ++ core_if->tx_msk = 0; ++ ++ if (core_if->en_multiple_tx_fifo == 0) { ++ /* Non-periodic Tx FIFO */ ++ DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n", ++ DWC_READ_REG32(&global_regs->gnptxfsiz)); ++ ++ nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size; ++ nptxfifosize.b.startaddr = params->dev_rx_fifo_size; ++ ++ DWC_WRITE_REG32(&global_regs->gnptxfsiz, ++ nptxfifosize.d32); ++ ++ DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n", ++ DWC_READ_REG32(&global_regs->gnptxfsiz)); ++ ++ /**@todo NGS: Fix Periodic FIFO Sizing! */ ++ /* ++ * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15. ++ * Indexes of the FIFO size module parameters in the ++ * dev_perio_tx_fifo_size array and the FIFO size registers in ++ * the dptxfsiz array run from 0 to 14. ++ */ ++ /** @todo Finish debug of this */ ++ ptxfifosize.b.startaddr = ++ nptxfifosize.b.startaddr + nptxfifosize.b.depth; ++ for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) { ++ ptxfifosize.b.depth = ++ params->dev_perio_tx_fifo_size[i]; ++ DWC_DEBUGPL(DBG_CIL, ++ "initial dtxfsiz[%d]=%08x\n", i, ++ DWC_READ_REG32(&global_regs->dtxfsiz ++ [i])); ++ DWC_WRITE_REG32(&global_regs->dtxfsiz[i], ++ ptxfifosize.d32); ++ DWC_DEBUGPL(DBG_CIL, "new dtxfsiz[%d]=%08x\n", ++ i, ++ DWC_READ_REG32(&global_regs->dtxfsiz ++ [i])); ++ ptxfifosize.b.startaddr += ptxfifosize.b.depth; ++ } ++ } else { ++ /* ++ * Tx FIFOs These FIFOs are numbered from 1 to 15. ++ * Indexes of the FIFO size module parameters in the ++ * dev_tx_fifo_size array and the FIFO size registers in ++ * the dtxfsiz array run from 0 to 14. ++ */ ++ ++ /* Non-periodic Tx FIFO */ ++ DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n", ++ DWC_READ_REG32(&global_regs->gnptxfsiz)); ++ ++#ifdef DWC_UTE_CFI ++ core_if->pwron_gnptxfsiz = ++ (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16); ++ core_if->init_gnptxfsiz = ++ params->dev_nperio_tx_fifo_size; ++#endif ++ nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size; ++ nptxfifosize.b.startaddr = params->dev_rx_fifo_size; ++ ++ DWC_WRITE_REG32(&global_regs->gnptxfsiz, ++ nptxfifosize.d32); ++ ++ DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n", ++ DWC_READ_REG32(&global_regs->gnptxfsiz)); ++ ++ txfifosize.b.startaddr = ++ nptxfifosize.b.startaddr + nptxfifosize.b.depth; ++ ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { ++ ++ txfifosize.b.depth = ++ params->dev_tx_fifo_size[i]; ++ ++ DWC_DEBUGPL(DBG_CIL, ++ "initial dtxfsiz[%d]=%08x\n", ++ i, ++ DWC_READ_REG32(&global_regs->dtxfsiz ++ [i])); ++ ++#ifdef DWC_UTE_CFI ++ core_if->pwron_txfsiz[i] = ++ (DWC_READ_REG32 ++ (&global_regs->dtxfsiz[i]) >> 16); ++ core_if->init_txfsiz[i] = ++ params->dev_tx_fifo_size[i]; ++#endif ++ DWC_WRITE_REG32(&global_regs->dtxfsiz[i], ++ txfifosize.d32); ++ ++ DWC_DEBUGPL(DBG_CIL, ++ "new dtxfsiz[%d]=%08x\n", ++ i, ++ DWC_READ_REG32(&global_regs->dtxfsiz ++ [i])); ++ ++ txfifosize.b.startaddr += txfifosize.b.depth; ++ } ++ if (core_if->snpsid <= OTG_CORE_REV_2_94a) { ++ /* Calculating DFIFOCFG for Device mode to include RxFIFO and NPTXFIFO */ ++ gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg); ++ hwcfg3.d32 = DWC_READ_REG32(&global_regs->ghwcfg3); ++ gdfifocfg.b.gdfifocfg = (DWC_READ_REG32(&global_regs->ghwcfg3) >> 16); ++ DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32); ++ rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff); ++ nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16); ++ gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz; ++ DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32); ++ } ++ } ++ ++ /* Flush the FIFOs */ ++ dwc_otg_flush_tx_fifo(core_if, 0x10); /* all Tx FIFOs */ ++ dwc_otg_flush_rx_fifo(core_if); ++ ++ /* Flush the Learning Queue. */ ++ resetctl.b.intknqflsh = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32); ++ ++ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) { ++ core_if->start_predict = 0; ++ for (i = 0; i<= core_if->dev_if->num_in_eps; ++i) { ++ core_if->nextep_seq[i] = 0xff; // 0xff - EP not active ++ } ++ core_if->nextep_seq[0] = 0; ++ core_if->first_in_nextep_seq = 0; ++ diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl); ++ diepctl.b.nextep = 0; ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32); ++ ++ /* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */ ++ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg); ++ dcfg.b.epmscnt = 2; ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32); ++ ++ DWC_DEBUGPL(DBG_CILV,"%s first_in_nextep_seq= %2d; nextep_seq[]:\n", ++ __func__, core_if->first_in_nextep_seq); ++ for (i=0; i <= core_if->dev_if->num_in_eps; i++) { ++ DWC_DEBUGPL(DBG_CILV, "%2d ", core_if->nextep_seq[i]); ++ } ++ DWC_DEBUGPL(DBG_CILV,"\n"); ++ } ++ ++ /* Clear all pending Device Interrupts */ ++ /** @todo - if the condition needed to be checked ++ * or in any case all pending interrutps should be cleared? ++ */ ++ if (core_if->multiproc_int_enable) { ++ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) { ++ DWC_WRITE_REG32(&dev_if-> ++ dev_global_regs->diepeachintmsk[i], 0); ++ } ++ } ++ ++ for (i = 0; i < core_if->dev_if->num_out_eps; ++i) { ++ DWC_WRITE_REG32(&dev_if-> ++ dev_global_regs->doepeachintmsk[i], 0); ++ } ++ ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->deachint, 0xFFFFFFFF); ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk, 0); ++ } else { ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, 0); ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, 0); ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->daint, 0xFFFFFFFF); ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk, 0); ++ } ++ ++ for (i = 0; i <= dev_if->num_in_eps; i++) { ++ depctl_data_t depctl; ++ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); ++ if (depctl.b.epena) { ++ depctl.d32 = 0; ++ depctl.b.epdis = 1; ++ depctl.b.snak = 1; ++ } else { ++ depctl.d32 = 0; ++ } ++ ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32); ++ ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, 0); ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, 0); ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepint, 0xFF); ++ } ++ ++ for (i = 0; i <= dev_if->num_out_eps; i++) { ++ depctl_data_t depctl; ++ depctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl); ++ if (depctl.b.epena) { ++ dctl_data_t dctl = {.d32 = 0 }; ++ gintmsk_data_t gintsts = {.d32 = 0 }; ++ doepint_data_t doepint = {.d32 = 0 }; ++ dctl.b.sgoutnak = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32); ++ do { ++ dwc_udelay(10); ++ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts); ++ } while (!gintsts.b.goutnakeff); ++ gintsts.d32 = 0; ++ gintsts.b.goutnakeff = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ depctl.d32 = 0; ++ depctl.b.epdis = 1; ++ depctl.b.snak = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->doepctl, depctl.d32); ++ do { ++ dwc_udelay(10); ++ doepint.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[i]->doepint); ++ } while (!doepint.b.epdisabled); ++ ++ doepint.b.epdisabled = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->doepint, doepint.d32); ++ ++ dctl.d32 = 0; ++ dctl.b.cgoutnak = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32); ++ } else { ++ depctl.d32 = 0; ++ } ++ ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, depctl.d32); ++ ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doeptsiz, 0); ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepdma, 0); ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepint, 0xFF); ++ } ++ ++ if (core_if->en_multiple_tx_fifo && core_if->dma_enable) { ++ dev_if->non_iso_tx_thr_en = params->thr_ctl & 0x1; ++ dev_if->iso_tx_thr_en = (params->thr_ctl >> 1) & 0x1; ++ dev_if->rx_thr_en = (params->thr_ctl >> 2) & 0x1; ++ ++ dev_if->rx_thr_length = params->rx_thr_length; ++ dev_if->tx_thr_length = params->tx_thr_length; ++ ++ dev_if->setup_desc_index = 0; ++ ++ dthrctl.d32 = 0; ++ dthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en; ++ dthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en; ++ dthrctl.b.tx_thr_len = dev_if->tx_thr_length; ++ dthrctl.b.rx_thr_en = dev_if->rx_thr_en; ++ dthrctl.b.rx_thr_len = dev_if->rx_thr_length; ++ dthrctl.b.ahb_thr_ratio = params->ahb_thr_ratio; ++ ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->dtknqr3_dthrctl, ++ dthrctl.d32); ++ ++ DWC_DEBUGPL(DBG_CIL, ++ "Non ISO Tx Thr - %d\nISO Tx Thr - %d\nRx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n", ++ dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en, ++ dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len, ++ dthrctl.b.rx_thr_len); ++ ++ } ++ ++ dwc_otg_enable_device_interrupts(core_if); ++ ++ { ++ diepmsk_data_t msk = {.d32 = 0 }; ++ msk.b.txfifoundrn = 1; ++ if (core_if->multiproc_int_enable) { ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs-> ++ diepeachintmsk[0], msk.d32, msk.d32); ++ } else { ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk, ++ msk.d32, msk.d32); ++ } ++ } ++ ++ if (core_if->multiproc_int_enable) { ++ /* Set NAK on Babble */ ++ dctl_data_t dctl = {.d32 = 0 }; ++ dctl.b.nakonbble = 1; ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32); ++ } ++ ++ if (core_if->snpsid >= OTG_CORE_REV_2_94a) { ++ dctl_data_t dctl = {.d32 = 0 }; ++ dctl.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dctl); ++ dctl.b.sftdiscon = 0; ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->dctl, dctl.d32); ++ } ++} ++ ++/** ++ * This function enables the Host mode interrupts. ++ * ++ * @param core_if Programming view of DWC_otg controller ++ */ ++void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * core_if) ++{ ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ DWC_DEBUGPL(DBG_CIL, "%s(%p)\n", __func__, core_if); ++ ++ /* Disable all interrupts. */ ++ DWC_WRITE_REG32(&global_regs->gintmsk, 0); ++ ++ /* Clear any pending interrupts. */ ++ DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF); ++ ++ /* Enable the common interrupts */ ++ dwc_otg_enable_common_interrupts(core_if); ++ ++ /* ++ * Enable host mode interrupts without disturbing common ++ * interrupts. ++ */ ++ ++ intr_mask.b.disconnect = 1; ++ intr_mask.b.portintr = 1; ++ intr_mask.b.hcintr = 1; ++ ++ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32); ++} ++ ++/** ++ * This function disables the Host Mode interrupts. ++ * ++ * @param core_if Programming view of DWC_otg controller ++ */ ++void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * core_if) ++{ ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__); ++ ++ /* ++ * Disable host mode interrupts without disturbing common ++ * interrupts. ++ */ ++ intr_mask.b.sofintr = 1; ++ intr_mask.b.portintr = 1; ++ intr_mask.b.hcintr = 1; ++ intr_mask.b.ptxfempty = 1; ++ intr_mask.b.nptxfempty = 1; ++ ++ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, 0); ++} ++ ++/** ++ * This function initializes the DWC_otg controller registers for ++ * host mode. ++ * ++ * This function flushes the Tx and Rx FIFOs and it flushes any entries in the ++ * request queues. Host channels are reset to ensure that they are ready for ++ * performing transfers. ++ * ++ * @param core_if Programming view of DWC_otg controller ++ * ++ */ ++void dwc_otg_core_host_init(dwc_otg_core_if_t * core_if) ++{ ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ dwc_otg_host_if_t *host_if = core_if->host_if; ++ dwc_otg_core_params_t *params = core_if->core_params; ++ hprt0_data_t hprt0 = {.d32 = 0 }; ++ fifosize_data_t nptxfifosize; ++ fifosize_data_t ptxfifosize; ++ uint16_t rxfsiz, nptxfsiz, hptxfsiz; ++ gdfifocfg_data_t gdfifocfg = {.d32 = 0 }; ++ int i; ++ hcchar_data_t hcchar; ++ hcfg_data_t hcfg; ++ hfir_data_t hfir; ++ dwc_otg_hc_regs_t *hc_regs; ++ int num_channels; ++ gotgctl_data_t gotgctl = {.d32 = 0 }; ++ ++ DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if); ++ ++ /* Restart the Phy Clock */ ++ DWC_WRITE_REG32(core_if->pcgcctl, 0); ++ ++ /* Initialize Host Configuration Register */ ++ init_fslspclksel(core_if); ++ if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) { ++ hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg); ++ hcfg.b.fslssupp = 1; ++ DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32); ++ ++ } ++ ++ /* This bit allows dynamic reloading of the HFIR register ++ * during runtime. This bit needs to be programmed during ++ * initial configuration and its value must not be changed ++ * during runtime.*/ ++ if (core_if->core_params->reload_ctl == 1) { ++ hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir); ++ hfir.b.hfirrldctrl = 1; ++ DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32); ++ } ++ ++ if (core_if->core_params->dma_desc_enable) { ++ uint8_t op_mode = core_if->hwcfg2.b.op_mode; ++ if (! ++ (core_if->hwcfg4.b.desc_dma ++ && (core_if->snpsid >= OTG_CORE_REV_2_90a) ++ && ((op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) ++ || (op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) ++ || (op_mode == ++ DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG) ++ || (op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST) ++ || (op_mode == ++ DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST)))) { ++ ++ DWC_ERROR("Host can't operate in Descriptor DMA mode.\n" ++ "Either core version is below 2.90a or " ++ "GHWCFG2, GHWCFG4 registers' values do not allow Descriptor DMA in host mode.\n" ++ "To run the driver in Buffer DMA host mode set dma_desc_enable " ++ "module parameter to 0.\n"); ++ return; ++ } ++ hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg); ++ hcfg.b.descdma = 1; ++ DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32); ++ } ++ ++ /* Configure data FIFO sizes */ ++ if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) { ++ DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n", ++ core_if->total_fifo_size); ++ DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n", ++ params->host_rx_fifo_size); ++ DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n", ++ params->host_nperio_tx_fifo_size); ++ DWC_DEBUGPL(DBG_CIL, "P Tx FIFO Size=%d\n", ++ params->host_perio_tx_fifo_size); ++ ++ /* Rx FIFO */ ++ DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n", ++ DWC_READ_REG32(&global_regs->grxfsiz)); ++ DWC_WRITE_REG32(&global_regs->grxfsiz, ++ params->host_rx_fifo_size); ++ DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n", ++ DWC_READ_REG32(&global_regs->grxfsiz)); ++ ++ /* Non-periodic Tx FIFO */ ++ DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n", ++ DWC_READ_REG32(&global_regs->gnptxfsiz)); ++ nptxfifosize.b.depth = params->host_nperio_tx_fifo_size; ++ nptxfifosize.b.startaddr = params->host_rx_fifo_size; ++ DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32); ++ DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n", ++ DWC_READ_REG32(&global_regs->gnptxfsiz)); ++ ++ /* Periodic Tx FIFO */ ++ DWC_DEBUGPL(DBG_CIL, "initial hptxfsiz=%08x\n", ++ DWC_READ_REG32(&global_regs->hptxfsiz)); ++ ptxfifosize.b.depth = params->host_perio_tx_fifo_size; ++ ptxfifosize.b.startaddr = ++ nptxfifosize.b.startaddr + nptxfifosize.b.depth; ++ DWC_WRITE_REG32(&global_regs->hptxfsiz, ptxfifosize.d32); ++ DWC_DEBUGPL(DBG_CIL, "new hptxfsiz=%08x\n", ++ DWC_READ_REG32(&global_regs->hptxfsiz)); ++ ++ if (core_if->en_multiple_tx_fifo ++ && core_if->snpsid <= OTG_CORE_REV_2_94a) { ++ /* Global DFIFOCFG calculation for Host mode - include RxFIFO, NPTXFIFO and HPTXFIFO */ ++ gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg); ++ rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff); ++ nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16); ++ hptxfsiz = (DWC_READ_REG32(&global_regs->hptxfsiz) >> 16); ++ gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz + hptxfsiz; ++ DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32); ++ } ++ } ++ ++ /* TODO - check this */ ++ /* Clear Host Set HNP Enable in the OTG Control Register */ ++ gotgctl.b.hstsethnpen = 1; ++ DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0); ++ /* Make sure the FIFOs are flushed. */ ++ dwc_otg_flush_tx_fifo(core_if, 0x10 /* all TX FIFOs */ ); ++ dwc_otg_flush_rx_fifo(core_if); ++ ++ /* Clear Host Set HNP Enable in the OTG Control Register */ ++ gotgctl.b.hstsethnpen = 1; ++ DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0); ++ ++ if (!core_if->core_params->dma_desc_enable) { ++ /* Flush out any leftover queued requests. */ ++ num_channels = core_if->core_params->host_channels; ++ ++ for (i = 0; i < num_channels; i++) { ++ hc_regs = core_if->host_if->hc_regs[i]; ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ hcchar.b.chen = 0; ++ hcchar.b.chdis = 1; ++ hcchar.b.epdir = 0; ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); ++ } ++ ++ /* Halt all channels to put them into a known state. */ ++ for (i = 0; i < num_channels; i++) { ++ int count = 0; ++ hc_regs = core_if->host_if->hc_regs[i]; ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ hcchar.b.chen = 1; ++ hcchar.b.chdis = 1; ++ hcchar.b.epdir = 0; ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); ++ DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d regs %p\n", __func__, i, hc_regs); ++ do { ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ if (++count > 1000) { ++ DWC_ERROR ++ ("%s: Unable to clear halt on channel %d (timeout HCCHAR 0x%X @%p)\n", ++ __func__, i, hcchar.d32, &hc_regs->hcchar); ++ break; ++ } ++ dwc_udelay(1); ++ } while (hcchar.b.chen); ++ } ++ } ++ ++ /* Turn on the vbus power. */ ++ DWC_PRINTF("Init: Port Power? op_state=%d\n", core_if->op_state); ++ if (core_if->op_state == A_HOST) { ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ DWC_PRINTF("Init: Power Port (%d)\n", hprt0.b.prtpwr); ++ if (hprt0.b.prtpwr == 0) { ++ hprt0.b.prtpwr = 1; ++ DWC_WRITE_REG32(host_if->hprt0, hprt0.d32); ++ } ++ } ++ ++ dwc_otg_enable_host_interrupts(core_if); ++} ++ ++/** ++ * Prepares a host channel for transferring packets to/from a specific ++ * endpoint. The HCCHARn register is set up with the characteristics specified ++ * in _hc. Host channel interrupts that may need to be serviced while this ++ * transfer is in progress are enabled. ++ * ++ * @param core_if Programming view of DWC_otg controller ++ * @param hc Information needed to initialize the host channel ++ */ ++void dwc_otg_hc_init(dwc_otg_core_if_t * core_if, dwc_hc_t * hc) ++{ ++ hcintmsk_data_t hc_intr_mask; ++ hcchar_data_t hcchar; ++ hcsplt_data_t hcsplt; ++ ++ uint8_t hc_num = hc->hc_num; ++ dwc_otg_host_if_t *host_if = core_if->host_if; ++ dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num]; ++ ++ /* Clear old interrupt conditions for this host channel. */ ++ hc_intr_mask.d32 = 0xFFFFFFFF; ++ hc_intr_mask.b.reserved14_31 = 0; ++ DWC_WRITE_REG32(&hc_regs->hcint, hc_intr_mask.d32); ++ ++ /* Enable channel interrupts required for this transfer. */ ++ hc_intr_mask.d32 = 0; ++ hc_intr_mask.b.chhltd = 1; ++ if (core_if->dma_enable) { ++ /* For Descriptor DMA mode core halts the channel on AHB error. Interrupt is not required */ ++ if (!core_if->dma_desc_enable) ++ hc_intr_mask.b.ahberr = 1; ++ else { ++ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) ++ hc_intr_mask.b.xfercompl = 1; ++ } ++ ++ if (hc->error_state && !hc->do_split && ++ hc->ep_type != DWC_OTG_EP_TYPE_ISOC) { ++ hc_intr_mask.b.ack = 1; ++ if (hc->ep_is_in) { ++ hc_intr_mask.b.datatglerr = 1; ++ if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) { ++ hc_intr_mask.b.nak = 1; ++ } ++ } ++ } ++ } else { ++ switch (hc->ep_type) { ++ case DWC_OTG_EP_TYPE_CONTROL: ++ case DWC_OTG_EP_TYPE_BULK: ++ hc_intr_mask.b.xfercompl = 1; ++ hc_intr_mask.b.stall = 1; ++ hc_intr_mask.b.xacterr = 1; ++ hc_intr_mask.b.datatglerr = 1; ++ if (hc->ep_is_in) { ++ hc_intr_mask.b.bblerr = 1; ++ } else { ++ hc_intr_mask.b.nak = 1; ++ hc_intr_mask.b.nyet = 1; ++ if (hc->do_ping) { ++ hc_intr_mask.b.ack = 1; ++ } ++ } ++ ++ if (hc->do_split) { ++ hc_intr_mask.b.nak = 1; ++ if (hc->complete_split) { ++ hc_intr_mask.b.nyet = 1; ++ } else { ++ hc_intr_mask.b.ack = 1; ++ } ++ } ++ ++ if (hc->error_state) { ++ hc_intr_mask.b.ack = 1; ++ } ++ break; ++ case DWC_OTG_EP_TYPE_INTR: ++ hc_intr_mask.b.xfercompl = 1; ++ hc_intr_mask.b.nak = 1; ++ hc_intr_mask.b.stall = 1; ++ hc_intr_mask.b.xacterr = 1; ++ hc_intr_mask.b.datatglerr = 1; ++ hc_intr_mask.b.frmovrun = 1; ++ ++ if (hc->ep_is_in) { ++ hc_intr_mask.b.bblerr = 1; ++ } ++ if (hc->error_state) { ++ hc_intr_mask.b.ack = 1; ++ } ++ if (hc->do_split) { ++ if (hc->complete_split) { ++ hc_intr_mask.b.nyet = 1; ++ } else { ++ hc_intr_mask.b.ack = 1; ++ } ++ } ++ break; ++ case DWC_OTG_EP_TYPE_ISOC: ++ hc_intr_mask.b.xfercompl = 1; ++ hc_intr_mask.b.frmovrun = 1; ++ hc_intr_mask.b.ack = 1; ++ ++ if (hc->ep_is_in) { ++ hc_intr_mask.b.xacterr = 1; ++ hc_intr_mask.b.bblerr = 1; ++ } ++ break; ++ } ++ } ++ DWC_WRITE_REG32(&hc_regs->hcintmsk, hc_intr_mask.d32); ++ ++ /* ++ * Program the HCCHARn register with the endpoint characteristics for ++ * the current transfer. ++ */ ++ hcchar.d32 = 0; ++ hcchar.b.devaddr = hc->dev_addr; ++ hcchar.b.epnum = hc->ep_num; ++ hcchar.b.epdir = hc->ep_is_in; ++ hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW); ++ hcchar.b.eptype = hc->ep_type; ++ hcchar.b.mps = hc->max_packet; ++ ++ DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32); ++ ++ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d, Dev Addr %d, EP #%d\n", ++ __func__, hc->hc_num, hcchar.b.devaddr, hcchar.b.epnum); ++ DWC_DEBUGPL(DBG_HCDV, " Is In %d, Is Low Speed %d, EP Type %d, " ++ "Max Pkt %d, Multi Cnt %d\n", ++ hcchar.b.epdir, hcchar.b.lspddev, hcchar.b.eptype, ++ hcchar.b.mps, hcchar.b.multicnt); ++ ++ /* ++ * Program the HCSPLIT register for SPLITs ++ */ ++ hcsplt.d32 = 0; ++ if (hc->do_split) { ++ DWC_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n", ++ hc->hc_num, ++ hc->complete_split ? "CSPLIT" : "SSPLIT"); ++ hcsplt.b.compsplt = hc->complete_split; ++ hcsplt.b.xactpos = hc->xact_pos; ++ hcsplt.b.hubaddr = hc->hub_addr; ++ hcsplt.b.prtaddr = hc->port_addr; ++ DWC_DEBUGPL(DBG_HCDV, "\t comp split %d\n", hc->complete_split); ++ DWC_DEBUGPL(DBG_HCDV, "\t xact pos %d\n", hc->xact_pos); ++ DWC_DEBUGPL(DBG_HCDV, "\t hub addr %d\n", hc->hub_addr); ++ DWC_DEBUGPL(DBG_HCDV, "\t port addr %d\n", hc->port_addr); ++ DWC_DEBUGPL(DBG_HCDV, "\t is_in %d\n", hc->ep_is_in); ++ DWC_DEBUGPL(DBG_HCDV, "\t Max Pkt: %d\n", hcchar.b.mps); ++ DWC_DEBUGPL(DBG_HCDV, "\t xferlen: %d\n", hc->xfer_len); ++ } ++ DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32); ++ ++} ++ ++/** ++ * Attempts to halt a host channel. This function should only be called in ++ * Slave mode or to abort a transfer in either Slave mode or DMA mode. Under ++ * normal circumstances in DMA mode, the controller halts the channel when the ++ * transfer is complete or a condition occurs that requires application ++ * intervention. ++ * ++ * In slave mode, checks for a free request queue entry, then sets the Channel ++ * Enable and Channel Disable bits of the Host Channel Characteristics ++ * register of the specified channel to intiate the halt. If there is no free ++ * request queue entry, sets only the Channel Disable bit of the HCCHARn ++ * register to flush requests for this channel. In the latter case, sets a ++ * flag to indicate that the host channel needs to be halted when a request ++ * queue slot is open. ++ * ++ * In DMA mode, always sets the Channel Enable and Channel Disable bits of the ++ * HCCHARn register. The controller ensures there is space in the request ++ * queue before submitting the halt request. ++ * ++ * Some time may elapse before the core flushes any posted requests for this ++ * host channel and halts. The Channel Halted interrupt handler completes the ++ * deactivation of the host channel. ++ * ++ * @param core_if Controller register interface. ++ * @param hc Host channel to halt. ++ * @param halt_status Reason for halting the channel. ++ */ ++void dwc_otg_hc_halt(dwc_otg_core_if_t * core_if, ++ dwc_hc_t * hc, dwc_otg_halt_status_e halt_status) ++{ ++ gnptxsts_data_t nptxsts; ++ hptxsts_data_t hptxsts; ++ hcchar_data_t hcchar; ++ dwc_otg_hc_regs_t *hc_regs; ++ dwc_otg_core_global_regs_t *global_regs; ++ dwc_otg_host_global_regs_t *host_global_regs; ++ ++ hc_regs = core_if->host_if->hc_regs[hc->hc_num]; ++ global_regs = core_if->core_global_regs; ++ host_global_regs = core_if->host_if->host_global_regs; ++ ++ DWC_ASSERT(!(halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS), ++ "halt_status = %d\n", halt_status); ++ ++ if (halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE || ++ halt_status == DWC_OTG_HC_XFER_AHB_ERR) { ++ /* ++ * Disable all channel interrupts except Ch Halted. The QTD ++ * and QH state associated with this transfer has been cleared ++ * (in the case of URB_DEQUEUE), so the channel needs to be ++ * shut down carefully to prevent crashes. ++ */ ++ hcintmsk_data_t hcintmsk; ++ hcintmsk.d32 = 0; ++ hcintmsk.b.chhltd = 1; ++ DWC_WRITE_REG32(&hc_regs->hcintmsk, hcintmsk.d32); ++ ++ /* ++ * Make sure no other interrupts besides halt are currently ++ * pending. Handling another interrupt could cause a crash due ++ * to the QTD and QH state. ++ */ ++ DWC_WRITE_REG32(&hc_regs->hcint, ~hcintmsk.d32); ++ ++ /* ++ * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR ++ * even if the channel was already halted for some other ++ * reason. ++ */ ++ hc->halt_status = halt_status; ++ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ if (hcchar.b.chen == 0) { ++ /* ++ * The channel is either already halted or it hasn't ++ * started yet. In DMA mode, the transfer may halt if ++ * it finishes normally or a condition occurs that ++ * requires driver intervention. Don't want to halt ++ * the channel again. In either Slave or DMA mode, ++ * it's possible that the transfer has been assigned ++ * to a channel, but not started yet when an URB is ++ * dequeued. Don't want to halt a channel that hasn't ++ * started yet. ++ */ ++ return; ++ } ++ } ++ if (hc->halt_pending) { ++ /* ++ * A halt has already been issued for this channel. This might ++ * happen when a transfer is aborted by a higher level in ++ * the stack. ++ */ ++#ifdef DEBUG ++ DWC_PRINTF ++ ("*** %s: Channel %d, _hc->halt_pending already set ***\n", ++ __func__, hc->hc_num); ++ ++#endif ++ return; ++ } ++ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ ++ /* No need to set the bit in DDMA for disabling the channel */ ++ //TODO check it everywhere channel is disabled ++ if (!core_if->core_params->dma_desc_enable) ++ hcchar.b.chen = 1; ++ hcchar.b.chdis = 1; ++ ++ if (!core_if->dma_enable) { ++ /* Check for space in the request queue to issue the halt. */ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL || ++ hc->ep_type == DWC_OTG_EP_TYPE_BULK) { ++ nptxsts.d32 = DWC_READ_REG32(&global_regs->gnptxsts); ++ if (nptxsts.b.nptxqspcavail == 0) { ++ hcchar.b.chen = 0; ++ } ++ } else { ++ hptxsts.d32 = ++ DWC_READ_REG32(&host_global_regs->hptxsts); ++ if ((hptxsts.b.ptxqspcavail == 0) ++ || (core_if->queuing_high_bandwidth)) { ++ hcchar.b.chen = 0; ++ } ++ } ++ } ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); ++ ++ hc->halt_status = halt_status; ++ ++ if (hcchar.b.chen) { ++ hc->halt_pending = 1; ++ hc->halt_on_queue = 0; ++ } else { ++ hc->halt_on_queue = 1; ++ } ++ ++ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num); ++ DWC_DEBUGPL(DBG_HCDV, " hcchar: 0x%08x\n", hcchar.d32); ++ DWC_DEBUGPL(DBG_HCDV, " halt_pending: %d\n", hc->halt_pending); ++ DWC_DEBUGPL(DBG_HCDV, " halt_on_queue: %d\n", hc->halt_on_queue); ++ DWC_DEBUGPL(DBG_HCDV, " halt_status: %d\n", hc->halt_status); ++ ++ return; ++} ++ ++/** ++ * Clears the transfer state for a host channel. This function is normally ++ * called after a transfer is done and the host channel is being released. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param hc Identifies the host channel to clean up. ++ */ ++void dwc_otg_hc_cleanup(dwc_otg_core_if_t * core_if, dwc_hc_t * hc) ++{ ++ dwc_otg_hc_regs_t *hc_regs; ++ ++ hc->xfer_started = 0; ++ ++ /* ++ * Clear channel interrupt enables and any unhandled channel interrupt ++ * conditions. ++ */ ++ hc_regs = core_if->host_if->hc_regs[hc->hc_num]; ++ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0); ++ DWC_WRITE_REG32(&hc_regs->hcint, 0xFFFFFFFF); ++#ifdef DEBUG ++ DWC_TIMER_CANCEL(core_if->hc_xfer_timer[hc->hc_num]); ++#endif ++} ++ ++/** ++ * Sets the channel property that indicates in which frame a periodic transfer ++ * should occur. This is always set to the _next_ frame. This function has no ++ * effect on non-periodic transfers. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param hc Identifies the host channel to set up and its properties. ++ * @param hcchar Current value of the HCCHAR register for the specified host ++ * channel. ++ */ ++static inline void hc_set_even_odd_frame(dwc_otg_core_if_t * core_if, ++ dwc_hc_t * hc, hcchar_data_t * hcchar) ++{ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || ++ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { ++ hfnum_data_t hfnum; ++ hfnum.d32 = ++ DWC_READ_REG32(&core_if->host_if->host_global_regs->hfnum); ++ ++ /* 1 if _next_ frame is odd, 0 if it's even */ ++ hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1; ++#ifdef DEBUG ++ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR && hc->do_split ++ && !hc->complete_split) { ++ switch (hfnum.b.frnum & 0x7) { ++ case 7: ++ core_if->hfnum_7_samples++; ++ core_if->hfnum_7_frrem_accum += hfnum.b.frrem; ++ break; ++ case 0: ++ core_if->hfnum_0_samples++; ++ core_if->hfnum_0_frrem_accum += hfnum.b.frrem; ++ break; ++ default: ++ core_if->hfnum_other_samples++; ++ core_if->hfnum_other_frrem_accum += ++ hfnum.b.frrem; ++ break; ++ } ++ } ++#endif ++ } ++} ++ ++#ifdef DEBUG ++void hc_xfer_timeout(void *ptr) ++{ ++ hc_xfer_info_t *xfer_info = NULL; ++ int hc_num = 0; ++ ++ if (ptr) ++ xfer_info = (hc_xfer_info_t *) ptr; ++ ++ if (!xfer_info->hc) { ++ DWC_ERROR("xfer_info->hc = %p\n", xfer_info->hc); ++ return; ++ } ++ ++ hc_num = xfer_info->hc->hc_num; ++ DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num); ++ DWC_WARN(" start_hcchar_val 0x%08x\n", ++ xfer_info->core_if->start_hcchar_val[hc_num]); ++} ++#endif ++ ++void ep_xfer_timeout(void *ptr) ++{ ++ ep_xfer_info_t *xfer_info = NULL; ++ int ep_num = 0; ++ dctl_data_t dctl = {.d32 = 0 }; ++ gintsts_data_t gintsts = {.d32 = 0 }; ++ gintmsk_data_t gintmsk = {.d32 = 0 }; ++ ++ if (ptr) ++ xfer_info = (ep_xfer_info_t *) ptr; ++ ++ if (!xfer_info->ep) { ++ DWC_ERROR("xfer_info->ep = %p\n", xfer_info->ep); ++ return; ++ } ++ ++ ep_num = xfer_info->ep->num; ++ DWC_WARN("%s: timeout on endpoit %d\n", __func__, ep_num); ++ /* Put the sate to 2 as it was time outed */ ++ xfer_info->state = 2; ++ ++ dctl.d32 = ++ DWC_READ_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl); ++ gintsts.d32 = ++ DWC_READ_REG32(&xfer_info->core_if->core_global_regs->gintsts); ++ gintmsk.d32 = ++ DWC_READ_REG32(&xfer_info->core_if->core_global_regs->gintmsk); ++ ++ if (!gintmsk.b.goutnakeff) { ++ /* Unmask it */ ++ gintmsk.b.goutnakeff = 1; ++ DWC_WRITE_REG32(&xfer_info->core_if->core_global_regs->gintmsk, ++ gintmsk.d32); ++ ++ } ++ ++ if (!gintsts.b.goutnakeff) { ++ dctl.b.sgoutnak = 1; ++ } ++ DWC_WRITE_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl, ++ dctl.d32); ++ ++} ++ ++void set_pid_isoc(dwc_hc_t * hc) ++{ ++ /* Set up the initial PID for the transfer. */ ++ if (hc->speed == DWC_OTG_EP_SPEED_HIGH) { ++ if (hc->ep_is_in) { ++ if (hc->multi_count == 1) { ++ hc->data_pid_start = DWC_OTG_HC_PID_DATA0; ++ } else if (hc->multi_count == 2) { ++ hc->data_pid_start = DWC_OTG_HC_PID_DATA1; ++ } else { ++ hc->data_pid_start = DWC_OTG_HC_PID_DATA2; ++ } ++ } else { ++ if (hc->multi_count == 1) { ++ hc->data_pid_start = DWC_OTG_HC_PID_DATA0; ++ } else { ++ hc->data_pid_start = DWC_OTG_HC_PID_MDATA; ++ } ++ } ++ } else { ++ hc->data_pid_start = DWC_OTG_HC_PID_DATA0; ++ } ++} ++ ++/** ++ * This function does the setup for a data transfer for a host channel and ++ * starts the transfer. May be called in either Slave mode or DMA mode. In ++ * Slave mode, the caller must ensure that there is sufficient space in the ++ * request queue and Tx Data FIFO. ++ * ++ * For an OUT transfer in Slave mode, it loads a data packet into the ++ * appropriate FIFO. If necessary, additional data packets will be loaded in ++ * the Host ISR. ++ * ++ * For an IN transfer in Slave mode, a data packet is requested. The data ++ * packets are unloaded from the Rx FIFO in the Host ISR. If necessary, ++ * additional data packets are requested in the Host ISR. ++ * ++ * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ ++ * register along with a packet count of 1 and the channel is enabled. This ++ * causes a single PING transaction to occur. Other fields in HCTSIZ are ++ * simply set to 0 since no data transfer occurs in this case. ++ * ++ * For a PING transfer in DMA mode, the HCTSIZ register is initialized with ++ * all the information required to perform the subsequent data transfer. In ++ * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the ++ * controller performs the entire PING protocol, then starts the data ++ * transfer. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param hc Information needed to initialize the host channel. The xfer_len ++ * value may be reduced to accommodate the max widths of the XferSize and ++ * PktCnt fields in the HCTSIZn register. The multi_count value may be changed ++ * to reflect the final xfer_len value. ++ */ ++void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc) ++{ ++ hcchar_data_t hcchar; ++ hctsiz_data_t hctsiz; ++ uint16_t num_packets; ++ uint32_t max_hc_xfer_size = core_if->core_params->max_transfer_size; ++ uint16_t max_hc_pkt_count = core_if->core_params->max_packet_count; ++ dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num]; ++ ++ hctsiz.d32 = 0; ++ ++ if (hc->do_ping) { ++ if (!core_if->dma_enable) { ++ dwc_otg_hc_do_ping(core_if, hc); ++ hc->xfer_started = 1; ++ return; ++ } else { ++ hctsiz.b.dopng = 1; ++ } ++ } ++ ++ if (hc->do_split) { ++ num_packets = 1; ++ ++ if (hc->complete_split && !hc->ep_is_in) { ++ /* For CSPLIT OUT Transfer, set the size to 0 so the ++ * core doesn't expect any data written to the FIFO */ ++ hc->xfer_len = 0; ++ } else if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) { ++ hc->xfer_len = hc->max_packet; ++ } else if (!hc->ep_is_in && (hc->xfer_len > 188)) { ++ hc->xfer_len = 188; ++ } ++ ++ hctsiz.b.xfersize = hc->xfer_len; ++ } else { ++ /* ++ * Ensure that the transfer length and packet count will fit ++ * in the widths allocated for them in the HCTSIZn register. ++ */ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || ++ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { ++ /* ++ * Make sure the transfer size is no larger than one ++ * (micro)frame's worth of data. (A check was done ++ * when the periodic transfer was accepted to ensure ++ * that a (micro)frame's worth of data can be ++ * programmed into a channel.) ++ */ ++ uint32_t max_periodic_len = ++ hc->multi_count * hc->max_packet; ++ if (hc->xfer_len > max_periodic_len) { ++ hc->xfer_len = max_periodic_len; ++ } else { ++ } ++ } else if (hc->xfer_len > max_hc_xfer_size) { ++ /* Make sure that xfer_len is a multiple of max packet size. */ ++ hc->xfer_len = max_hc_xfer_size - hc->max_packet + 1; ++ } ++ ++ if (hc->xfer_len > 0) { ++ num_packets = ++ (hc->xfer_len + hc->max_packet - ++ 1) / hc->max_packet; ++ if (num_packets > max_hc_pkt_count) { ++ num_packets = max_hc_pkt_count; ++ hc->xfer_len = num_packets * hc->max_packet; ++ } ++ } else { ++ /* Need 1 packet for transfer length of 0. */ ++ num_packets = 1; ++ } ++ ++ if (hc->ep_is_in) { ++ /* Always program an integral # of max packets for IN transfers. */ ++ hc->xfer_len = num_packets * hc->max_packet; ++ } ++ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || ++ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { ++ /* ++ * Make sure that the multi_count field matches the ++ * actual transfer length. ++ */ ++ hc->multi_count = num_packets; ++ } ++ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) ++ set_pid_isoc(hc); ++ ++ hctsiz.b.xfersize = hc->xfer_len; ++ } ++ ++ hc->start_pkt_count = num_packets; ++ hctsiz.b.pktcnt = num_packets; ++ hctsiz.b.pid = hc->data_pid_start; ++ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32); ++ ++ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num); ++ DWC_DEBUGPL(DBG_HCDV, " Xfer Size: %d\n", hctsiz.b.xfersize); ++ DWC_DEBUGPL(DBG_HCDV, " Num Pkts: %d\n", hctsiz.b.pktcnt); ++ DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid); ++ ++ if (core_if->dma_enable) { ++ dwc_dma_t dma_addr; ++ if (hc->align_buff) { ++ dma_addr = hc->align_buff; ++ } else { ++ dma_addr = ((unsigned long)hc->xfer_buff & 0xffffffff); ++ } ++ DWC_WRITE_REG32(&hc_regs->hcdma, dma_addr); ++ } ++ ++ /* Start the split */ ++ if (hc->do_split) { ++ hcsplt_data_t hcsplt; ++ hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt); ++ hcsplt.b.spltena = 1; ++ DWC_WRITE_REG32(&hc_regs->hcsplt, hcsplt.d32); ++ } ++ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ hcchar.b.multicnt = hc->multi_count; ++ hc_set_even_odd_frame(core_if, hc, &hcchar); ++#ifdef DEBUG ++ core_if->start_hcchar_val[hc->hc_num] = hcchar.d32; ++ if (hcchar.b.chdis) { ++ DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n", ++ __func__, hc->hc_num, hcchar.d32); ++ } ++#endif ++ ++ /* Set host channel enable after all other setup is complete. */ ++ hcchar.b.chen = 1; ++ hcchar.b.chdis = 0; ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); ++ ++ hc->xfer_started = 1; ++ hc->requests++; ++ ++ if (!core_if->dma_enable && !hc->ep_is_in && hc->xfer_len > 0) { ++ /* Load OUT packet into the appropriate Tx FIFO. */ ++ dwc_otg_hc_write_packet(core_if, hc); ++ } ++#ifdef DEBUG ++ if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) { ++ DWC_DEBUGPL(DBG_HCDV, "transfer %d from core_if %p\n", ++ hc->hc_num, core_if);//GRAYG ++ core_if->hc_xfer_info[hc->hc_num].core_if = core_if; ++ core_if->hc_xfer_info[hc->hc_num].hc = hc; ++ ++ /* Start a timer for this transfer. */ ++ DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000); ++ } ++#endif ++} ++ ++/** ++ * This function does the setup for a data transfer for a host channel ++ * and starts the transfer in Descriptor DMA mode. ++ * ++ * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set. ++ * Sets PID and NTD values. For periodic transfers ++ * initializes SCHED_INFO field with micro-frame bitmap. ++ * ++ * Initializes HCDMA register with descriptor list address and CTD value ++ * then starts the transfer via enabling the channel. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param hc Information needed to initialize the host channel. ++ */ ++void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if, dwc_hc_t * hc) ++{ ++ dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num]; ++ hcchar_data_t hcchar; ++ hctsiz_data_t hctsiz; ++ hcdma_data_t hcdma; ++ ++ hctsiz.d32 = 0; ++ ++ if (hc->do_ping) ++ hctsiz.b_ddma.dopng = 1; ++ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) ++ set_pid_isoc(hc); ++ ++ /* Packet Count and Xfer Size are not used in Descriptor DMA mode */ ++ hctsiz.b_ddma.pid = hc->data_pid_start; ++ hctsiz.b_ddma.ntd = hc->ntd - 1; /* 0 - 1 descriptor, 1 - 2 descriptors, etc. */ ++ hctsiz.b_ddma.schinfo = hc->schinfo; /* Non-zero only for high-speed interrupt endpoints */ ++ ++ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num); ++ DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid); ++ DWC_DEBUGPL(DBG_HCDV, " NTD: %d\n", hctsiz.b_ddma.ntd); ++ ++ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32); ++ ++ hcdma.d32 = 0; ++ hcdma.b.dma_addr = ((uint32_t) hc->desc_list_addr) >> 11; ++ ++ /* Always start from first descriptor. */ ++ hcdma.b.ctd = 0; ++ DWC_WRITE_REG32(&hc_regs->hcdma, hcdma.d32); ++ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ hcchar.b.multicnt = hc->multi_count; ++ ++#ifdef DEBUG ++ core_if->start_hcchar_val[hc->hc_num] = hcchar.d32; ++ if (hcchar.b.chdis) { ++ DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n", ++ __func__, hc->hc_num, hcchar.d32); ++ } ++#endif ++ ++ /* Set host channel enable after all other setup is complete. */ ++ hcchar.b.chen = 1; ++ hcchar.b.chdis = 0; ++ ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); ++ ++ hc->xfer_started = 1; ++ hc->requests++; ++ ++#ifdef DEBUG ++ if ((hc->ep_type != DWC_OTG_EP_TYPE_INTR) ++ && (hc->ep_type != DWC_OTG_EP_TYPE_ISOC)) { ++ DWC_DEBUGPL(DBG_HCDV, "DMA transfer %d from core_if %p\n", ++ hc->hc_num, core_if);//GRAYG ++ core_if->hc_xfer_info[hc->hc_num].core_if = core_if; ++ core_if->hc_xfer_info[hc->hc_num].hc = hc; ++ /* Start a timer for this transfer. */ ++ DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000); ++ } ++#endif ++ ++} ++ ++/** ++ * This function continues a data transfer that was started by previous call ++ * to dwc_otg_hc_start_transfer. The caller must ensure there is ++ * sufficient space in the request queue and Tx Data FIFO. This function ++ * should only be called in Slave mode. In DMA mode, the controller acts ++ * autonomously to complete transfers programmed to a host channel. ++ * ++ * For an OUT transfer, a new data packet is loaded into the appropriate FIFO ++ * if there is any data remaining to be queued. For an IN transfer, another ++ * data packet is always requested. For the SETUP phase of a control transfer, ++ * this function does nothing. ++ * ++ * @return 1 if a new request is queued, 0 if no more requests are required ++ * for this transfer. ++ */ ++int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc) ++{ ++ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num); ++ ++ if (hc->do_split) { ++ /* SPLITs always queue just once per channel */ ++ return 0; ++ } else if (hc->data_pid_start == DWC_OTG_HC_PID_SETUP) { ++ /* SETUPs are queued only once since they can't be NAKed. */ ++ return 0; ++ } else if (hc->ep_is_in) { ++ /* ++ * Always queue another request for other IN transfers. If ++ * back-to-back INs are issued and NAKs are received for both, ++ * the driver may still be processing the first NAK when the ++ * second NAK is received. When the interrupt handler clears ++ * the NAK interrupt for the first NAK, the second NAK will ++ * not be seen. So we can't depend on the NAK interrupt ++ * handler to requeue a NAKed request. Instead, IN requests ++ * are issued each time this function is called. When the ++ * transfer completes, the extra requests for the channel will ++ * be flushed. ++ */ ++ hcchar_data_t hcchar; ++ dwc_otg_hc_regs_t *hc_regs = ++ core_if->host_if->hc_regs[hc->hc_num]; ++ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ hc_set_even_odd_frame(core_if, hc, &hcchar); ++ hcchar.b.chen = 1; ++ hcchar.b.chdis = 0; ++ DWC_DEBUGPL(DBG_HCDV, " IN xfer: hcchar = 0x%08x\n", ++ hcchar.d32); ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); ++ hc->requests++; ++ return 1; ++ } else { ++ /* OUT transfers. */ ++ if (hc->xfer_count < hc->xfer_len) { ++ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || ++ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { ++ hcchar_data_t hcchar; ++ dwc_otg_hc_regs_t *hc_regs; ++ hc_regs = core_if->host_if->hc_regs[hc->hc_num]; ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ hc_set_even_odd_frame(core_if, hc, &hcchar); ++ } ++ ++ /* Load OUT packet into the appropriate Tx FIFO. */ ++ dwc_otg_hc_write_packet(core_if, hc); ++ hc->requests++; ++ return 1; ++ } else { ++ return 0; ++ } ++ } ++} ++ ++/** ++ * Starts a PING transfer. This function should only be called in Slave mode. ++ * The Do Ping bit is set in the HCTSIZ register, then the channel is enabled. ++ */ ++void dwc_otg_hc_do_ping(dwc_otg_core_if_t * core_if, dwc_hc_t * hc) ++{ ++ hcchar_data_t hcchar; ++ hctsiz_data_t hctsiz; ++ dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num]; ++ ++ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num); ++ ++ hctsiz.d32 = 0; ++ hctsiz.b.dopng = 1; ++ hctsiz.b.pktcnt = 1; ++ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32); ++ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ hcchar.b.chen = 1; ++ hcchar.b.chdis = 0; ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); ++} ++ ++/* ++ * This function writes a packet into the Tx FIFO associated with the Host ++ * Channel. For a channel associated with a non-periodic EP, the non-periodic ++ * Tx FIFO is written. For a channel associated with a periodic EP, the ++ * periodic Tx FIFO is written. This function should only be called in Slave ++ * mode. ++ * ++ * Upon return the xfer_buff and xfer_count fields in _hc are incremented by ++ * then number of bytes written to the Tx FIFO. ++ */ ++void dwc_otg_hc_write_packet(dwc_otg_core_if_t * core_if, dwc_hc_t * hc) ++{ ++ uint32_t i; ++ uint32_t remaining_count; ++ uint32_t byte_count; ++ uint32_t dword_count; ++ ++ uint32_t *data_buff = (uint32_t *) (hc->xfer_buff); ++ uint32_t *data_fifo = core_if->data_fifo[hc->hc_num]; ++ ++ remaining_count = hc->xfer_len - hc->xfer_count; ++ if (remaining_count > hc->max_packet) { ++ byte_count = hc->max_packet; ++ } else { ++ byte_count = remaining_count; ++ } ++ ++ dword_count = (byte_count + 3) / 4; ++ ++ if ((((unsigned long)data_buff) & 0x3) == 0) { ++ /* xfer_buff is DWORD aligned. */ ++ for (i = 0; i < dword_count; i++, data_buff++) { ++ DWC_WRITE_REG32(data_fifo, *data_buff); ++ } ++ } else { ++ /* xfer_buff is not DWORD aligned. */ ++ for (i = 0; i < dword_count; i++, data_buff++) { ++ uint32_t data; ++ data = ++ (data_buff[0] | data_buff[1] << 8 | data_buff[2] << ++ 16 | data_buff[3] << 24); ++ DWC_WRITE_REG32(data_fifo, data); ++ } ++ } ++ ++ hc->xfer_count += byte_count; ++ hc->xfer_buff += byte_count; ++} ++ ++/** ++ * Gets the current USB frame number. This is the frame number from the last ++ * SOF packet. ++ */ ++uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * core_if) ++{ ++ dsts_data_t dsts; ++ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); ++ ++ /* read current frame/microframe number from DSTS register */ ++ return dsts.b.soffn; ++} ++ ++/** ++ * Calculates and gets the frame Interval value of HFIR register according PHY ++ * type and speed.The application can modify a value of HFIR register only after ++ * the Port Enable bit of the Host Port Control and Status register ++ * (HPRT.PrtEnaPort) has been set. ++*/ ++ ++uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if) ++{ ++ gusbcfg_data_t usbcfg; ++ hwcfg2_data_t hwcfg2; ++ hprt0_data_t hprt0; ++ int clock = 60; // default value ++ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); ++ hwcfg2.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2); ++ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0); ++ if (!usbcfg.b.physel && usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif) ++ clock = 60; ++ if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 3) ++ clock = 48; ++ if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel && ++ !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif) ++ clock = 30; ++ if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel && ++ !usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif) ++ clock = 60; ++ if (usbcfg.b.phylpwrclksel && !usbcfg.b.physel && ++ !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif) ++ clock = 48; ++ if (usbcfg.b.physel && !usbcfg.b.phyif && hwcfg2.b.fs_phy_type == 2) ++ clock = 48; ++ if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 1) ++ clock = 48; ++ if (hprt0.b.prtspd == 0) ++ /* High speed case */ ++ return 125 * clock; ++ else ++ /* FS/LS case */ ++ return 1000 * clock; ++} ++ ++/** ++ * This function reads a setup packet from the Rx FIFO into the destination ++ * buffer. This function is called from the Rx Status Queue Level (RxStsQLvl) ++ * Interrupt routine when a SETUP packet has been received in Slave mode. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param dest Destination buffer for packet data. ++ */ ++void dwc_otg_read_setup_packet(dwc_otg_core_if_t * core_if, uint32_t * dest) ++{ ++ device_grxsts_data_t status; ++ /* Get the 8 bytes of a setup transaction data */ ++ ++ /* Pop 2 DWORDS off the receive data FIFO into memory */ ++ dest[0] = DWC_READ_REG32(core_if->data_fifo[0]); ++ dest[1] = DWC_READ_REG32(core_if->data_fifo[0]); ++ if (core_if->snpsid >= OTG_CORE_REV_3_00a) { ++ status.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->grxstsp); ++ DWC_DEBUGPL(DBG_ANY, ++ "EP:%d BCnt:%d " "pktsts:%x Frame:%d(0x%0x)\n", ++ status.b.epnum, status.b.bcnt, status.b.pktsts, ++ status.b.fn, status.b.fn); ++ } ++} ++ ++/** ++ * This function enables EP0 OUT to receive SETUP packets and configures EP0 ++ * IN for transmitting packets. It is normally called when the ++ * "Enumeration Done" interrupt occurs. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP0 data. ++ */ ++void dwc_otg_ep0_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ dsts_data_t dsts; ++ depctl_data_t diepctl; ++ depctl_data_t doepctl; ++ dctl_data_t dctl = {.d32 = 0 }; ++ ++ ep->stp_rollover = 0; ++ /* Read the Device Status and Endpoint 0 Control registers */ ++ dsts.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dsts); ++ diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl); ++ doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl); ++ ++ /* Set the MPS of the IN EP based on the enumeration speed */ ++ switch (dsts.b.enumspd) { ++ case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: ++ case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: ++ case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ: ++ diepctl.b.mps = DWC_DEP0CTL_MPS_64; ++ break; ++ case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ: ++ diepctl.b.mps = DWC_DEP0CTL_MPS_8; ++ break; ++ } ++ ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32); ++ ++ /* Enable OUT EP for receive */ ++ if (core_if->snpsid <= OTG_CORE_REV_2_94a) { ++ doepctl.b.epena = 1; ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32); ++ } ++#ifdef VERBOSE ++ DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n", ++ DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl)); ++ DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n", ++ DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl)); ++#endif ++ dctl.b.cgnpinnak = 1; ++ ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); ++ DWC_DEBUGPL(DBG_PCDV, "dctl=%0x\n", ++ DWC_READ_REG32(&dev_if->dev_global_regs->dctl)); ++ ++} ++ ++/** ++ * This function activates an EP. The Device EP control register for ++ * the EP is configured as defined in the ep structure. Note: This ++ * function is not used for EP0. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to activate. ++ */ ++void dwc_otg_ep_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ depctl_data_t depctl; ++ volatile uint32_t *addr; ++ daint_data_t daintmsk = {.d32 = 0 }; ++ dcfg_data_t dcfg; ++ uint8_t i; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, ep->num, ++ (ep->is_in ? "IN" : "OUT")); ++ ++#ifdef DWC_UTE_PER_IO ++ ep->xiso_frame_num = 0xFFFFFFFF; ++ ep->xiso_active_xfers = 0; ++ ep->xiso_queued_xfers = 0; ++#endif ++ /* Read DEPCTLn register */ ++ if (ep->is_in == 1) { ++ addr = &dev_if->in_ep_regs[ep->num]->diepctl; ++ daintmsk.ep.in = 1 << ep->num; ++ } else { ++ addr = &dev_if->out_ep_regs[ep->num]->doepctl; ++ daintmsk.ep.out = 1 << ep->num; ++ } ++ ++ /* If the EP is already active don't change the EP Control ++ * register. */ ++ depctl.d32 = DWC_READ_REG32(addr); ++ if (!depctl.b.usbactep) { ++ depctl.b.mps = ep->maxpacket; ++ depctl.b.eptype = ep->type; ++ depctl.b.txfnum = ep->tx_fifo_num; ++ ++ if (ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ depctl.b.setd0pid = 1; // ??? ++ } else { ++ depctl.b.setd0pid = 1; ++ } ++ depctl.b.usbactep = 1; ++ ++ /* Update nextep_seq array and EPMSCNT in DCFG*/ ++ if (!(depctl.b.eptype & 1) && (ep->is_in == 1)) { // NP IN EP ++ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) { ++ if (core_if->nextep_seq[i] == core_if->first_in_nextep_seq) ++ break; ++ } ++ core_if->nextep_seq[i] = ep->num; ++ core_if->nextep_seq[ep->num] = core_if->first_in_nextep_seq; ++ depctl.b.nextep = core_if->nextep_seq[ep->num]; ++ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg); ++ dcfg.b.epmscnt++; ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32); ++ ++ DWC_DEBUGPL(DBG_PCDV, ++ "%s first_in_nextep_seq= %2d; nextep_seq[]:\n", ++ __func__, core_if->first_in_nextep_seq); ++ for (i=0; i <= core_if->dev_if->num_in_eps; i++) { ++ DWC_DEBUGPL(DBG_PCDV, "%2d\n", ++ core_if->nextep_seq[i]); ++ } ++ ++ } ++ ++ ++ DWC_WRITE_REG32(addr, depctl.d32); ++ DWC_DEBUGPL(DBG_PCDV, "DEPCTL=%08x\n", DWC_READ_REG32(addr)); ++ } ++ ++ /* Enable the Interrupt for this EP */ ++ if (core_if->multiproc_int_enable) { ++ if (ep->is_in == 1) { ++ diepmsk_data_t diepmsk = {.d32 = 0 }; ++ diepmsk.b.xfercompl = 1; ++ diepmsk.b.timeout = 1; ++ diepmsk.b.epdisabled = 1; ++ diepmsk.b.ahberr = 1; ++ diepmsk.b.intknepmis = 1; ++ if (!core_if->en_multiple_tx_fifo && core_if->dma_enable) ++ diepmsk.b.intknepmis = 0; ++ diepmsk.b.txfifoundrn = 1; //????? ++ if (ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ diepmsk.b.nak = 1; ++ } ++ ++ ++ ++/* ++ if (core_if->dma_desc_enable) { ++ diepmsk.b.bna = 1; ++ } ++*/ ++/* ++ if (core_if->dma_enable) { ++ doepmsk.b.nak = 1; ++ } ++*/ ++ DWC_WRITE_REG32(&dev_if->dev_global_regs-> ++ diepeachintmsk[ep->num], diepmsk.d32); ++ ++ } else { ++ doepmsk_data_t doepmsk = {.d32 = 0 }; ++ doepmsk.b.xfercompl = 1; ++ doepmsk.b.ahberr = 1; ++ doepmsk.b.epdisabled = 1; ++ if (ep->type == DWC_OTG_EP_TYPE_ISOC) ++ doepmsk.b.outtknepdis = 1; ++ ++/* ++ ++ if (core_if->dma_desc_enable) { ++ doepmsk.b.bna = 1; ++ } ++*/ ++/* ++ doepmsk.b.babble = 1; ++ doepmsk.b.nyet = 1; ++ doepmsk.b.nak = 1; ++*/ ++ DWC_WRITE_REG32(&dev_if->dev_global_regs-> ++ doepeachintmsk[ep->num], doepmsk.d32); ++ } ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->deachintmsk, ++ 0, daintmsk.d32); ++ } else { ++ if (ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ if (ep->is_in) { ++ diepmsk_data_t diepmsk = {.d32 = 0 }; ++ diepmsk.b.nak = 1; ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk, 0, diepmsk.d32); ++ } else { ++ doepmsk_data_t doepmsk = {.d32 = 0 }; ++ doepmsk.b.outtknepdis = 1; ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->doepmsk, 0, doepmsk.d32); ++ } ++ } ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->daintmsk, ++ 0, daintmsk.d32); ++ } ++ ++ DWC_DEBUGPL(DBG_PCDV, "DAINTMSK=%0x\n", ++ DWC_READ_REG32(&dev_if->dev_global_regs->daintmsk)); ++ ++ ep->stall_clear_flag = 0; ++ ++ return; ++} ++ ++/** ++ * This function deactivates an EP. This is done by clearing the USB Active ++ * EP bit in the Device EP control register. Note: This function is not used ++ * for EP0. EP0 cannot be deactivated. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to deactivate. ++ */ ++void dwc_otg_ep_deactivate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ depctl_data_t depctl = {.d32 = 0 }; ++ volatile uint32_t *addr; ++ daint_data_t daintmsk = {.d32 = 0 }; ++ dcfg_data_t dcfg; ++ uint8_t i = 0; ++ ++#ifdef DWC_UTE_PER_IO ++ ep->xiso_frame_num = 0xFFFFFFFF; ++ ep->xiso_active_xfers = 0; ++ ep->xiso_queued_xfers = 0; ++#endif ++ ++ /* Read DEPCTLn register */ ++ if (ep->is_in == 1) { ++ addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl; ++ daintmsk.ep.in = 1 << ep->num; ++ } else { ++ addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl; ++ daintmsk.ep.out = 1 << ep->num; ++ } ++ ++ depctl.d32 = DWC_READ_REG32(addr); ++ ++ depctl.b.usbactep = 0; ++ ++ /* Update nextep_seq array and EPMSCNT in DCFG*/ ++ if (!(depctl.b.eptype & 1) && ep->is_in == 1) { // NP EP IN ++ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) { ++ if (core_if->nextep_seq[i] == ep->num) ++ break; ++ } ++ core_if->nextep_seq[i] = core_if->nextep_seq[ep->num]; ++ if (core_if->first_in_nextep_seq == ep->num) ++ core_if->first_in_nextep_seq = i; ++ core_if->nextep_seq[ep->num] = 0xff; ++ depctl.b.nextep = 0; ++ dcfg.d32 = ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); ++ dcfg.b.epmscnt--; ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, ++ dcfg.d32); ++ ++ DWC_DEBUGPL(DBG_PCDV, ++ "%s first_in_nextep_seq= %2d; nextep_seq[]:\n", ++ __func__, core_if->first_in_nextep_seq); ++ for (i=0; i <= core_if->dev_if->num_in_eps; i++) { ++ DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]); ++ } ++ } ++ ++ if (ep->is_in == 1) ++ depctl.b.txfnum = 0; ++ ++ if (core_if->dma_desc_enable) ++ depctl.b.epdis = 1; ++ ++ DWC_WRITE_REG32(addr, depctl.d32); ++ depctl.d32 = DWC_READ_REG32(addr); ++ if (core_if->dma_enable && ep->type == DWC_OTG_EP_TYPE_ISOC ++ && depctl.b.epena) { ++ depctl_data_t depctl = {.d32 = 0}; ++ if (ep->is_in) { ++ diepint_data_t diepint = {.d32 = 0}; ++ ++ depctl.b.snak = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]-> ++ diepctl, depctl.d32); ++ do { ++ dwc_udelay(10); ++ diepint.d32 = ++ DWC_READ_REG32(&core_if-> ++ dev_if->in_ep_regs[ep->num]-> ++ diepint); ++ } while (!diepint.b.inepnakeff); ++ diepint.b.inepnakeff = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]-> ++ diepint, diepint.d32); ++ depctl.d32 = 0; ++ depctl.b.epdis = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]-> ++ diepctl, depctl.d32); ++ do { ++ dwc_udelay(10); ++ diepint.d32 = ++ DWC_READ_REG32(&core_if-> ++ dev_if->in_ep_regs[ep->num]-> ++ diepint); ++ } while (!diepint.b.epdisabled); ++ diepint.b.epdisabled = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]-> ++ diepint, diepint.d32); ++ } else { ++ dctl_data_t dctl = {.d32 = 0}; ++ gintmsk_data_t gintsts = {.d32 = 0}; ++ doepint_data_t doepint = {.d32 = 0}; ++ dctl.b.sgoutnak = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> ++ dctl, 0, dctl.d32); ++ do { ++ dwc_udelay(10); ++ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts); ++ } while (!gintsts.b.goutnakeff); ++ gintsts.d32 = 0; ++ gintsts.b.goutnakeff = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ depctl.d32 = 0; ++ depctl.b.epdis = 1; ++ depctl.b.snak = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepctl, depctl.d32); ++ do ++ { ++ dwc_udelay(10); ++ doepint.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[ep->num]->doepint); ++ } while (!doepint.b.epdisabled); ++ ++ doepint.b.epdisabled = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepint, doepint.d32); ++ ++ dctl.d32 = 0; ++ dctl.b.cgoutnak = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32); ++ } ++ } ++ ++ /* Disable the Interrupt for this EP */ ++ if (core_if->multiproc_int_enable) { ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->deachintmsk, ++ daintmsk.d32, 0); ++ ++ if (ep->is_in == 1) { ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs-> ++ diepeachintmsk[ep->num], 0); ++ } else { ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs-> ++ doepeachintmsk[ep->num], 0); ++ } ++ } else { ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->daintmsk, ++ daintmsk.d32, 0); ++ } ++ ++} ++ ++/** ++ * This function initializes dma descriptor chain. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to start the transfer on. ++ */ ++static void init_dma_desc_chain(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ dwc_otg_dev_dma_desc_t *dma_desc; ++ uint32_t offset; ++ uint32_t xfer_est; ++ int i; ++ unsigned maxxfer_local, total_len; ++ ++ if (!ep->is_in && ep->type == DWC_OTG_EP_TYPE_INTR && ++ (ep->maxpacket%4)) { ++ maxxfer_local = ep->maxpacket; ++ total_len = ep->xfer_len; ++ } else { ++ maxxfer_local = ep->maxxfer; ++ total_len = ep->total_len; ++ } ++ ++ ep->desc_cnt = (total_len / maxxfer_local) + ++ ((total_len % maxxfer_local) ? 1 : 0); ++ ++ if (!ep->desc_cnt) ++ ep->desc_cnt = 1; ++ ++ if (ep->desc_cnt > MAX_DMA_DESC_CNT) ++ ep->desc_cnt = MAX_DMA_DESC_CNT; ++ ++ dma_desc = ep->desc_addr; ++ if (maxxfer_local == ep->maxpacket) { ++ if ((total_len % maxxfer_local) && ++ (total_len/maxxfer_local < MAX_DMA_DESC_CNT)) { ++ xfer_est = (ep->desc_cnt - 1) * maxxfer_local + ++ (total_len % maxxfer_local); ++ } else ++ xfer_est = ep->desc_cnt * maxxfer_local; ++ } else ++ xfer_est = total_len; ++ offset = 0; ++ for (i = 0; i < ep->desc_cnt; ++i) { ++ /** DMA Descriptor Setup */ ++ if (xfer_est > maxxfer_local) { ++ dma_desc->status.b.bs = BS_HOST_BUSY; ++ dma_desc->status.b.l = 0; ++ dma_desc->status.b.ioc = 0; ++ dma_desc->status.b.sp = 0; ++ dma_desc->status.b.bytes = maxxfer_local; ++ dma_desc->buf = ep->dma_addr + offset; ++ dma_desc->status.b.sts = 0; ++ dma_desc->status.b.bs = BS_HOST_READY; ++ ++ xfer_est -= maxxfer_local; ++ offset += maxxfer_local; ++ } else { ++ dma_desc->status.b.bs = BS_HOST_BUSY; ++ dma_desc->status.b.l = 1; ++ dma_desc->status.b.ioc = 1; ++ if (ep->is_in) { ++ dma_desc->status.b.sp = ++ (xfer_est % ++ ep->maxpacket) ? 1 : ((ep-> ++ sent_zlp) ? 1 : 0); ++ dma_desc->status.b.bytes = xfer_est; ++ } else { ++ if (maxxfer_local == ep->maxpacket) ++ dma_desc->status.b.bytes = xfer_est; ++ else ++ dma_desc->status.b.bytes = ++ xfer_est + ((4 - (xfer_est & 0x3)) & 0x3); ++ } ++ ++ dma_desc->buf = ep->dma_addr + offset; ++ dma_desc->status.b.sts = 0; ++ dma_desc->status.b.bs = BS_HOST_READY; ++ } ++ dma_desc++; ++ } ++} ++/** ++ * This function is called when to write ISOC data into appropriate dedicated ++ * periodic FIFO. ++ */ ++static int32_t write_isoc_tx_fifo(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep) ++{ ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ dwc_otg_dev_in_ep_regs_t *ep_regs; ++ dtxfsts_data_t txstatus = {.d32 = 0 }; ++ uint32_t len = 0; ++ int epnum = dwc_ep->num; ++ int dwords; ++ ++ DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum); ++ ++ ep_regs = core_if->dev_if->in_ep_regs[epnum]; ++ ++ len = dwc_ep->xfer_len - dwc_ep->xfer_count; ++ ++ if (len > dwc_ep->maxpacket) { ++ len = dwc_ep->maxpacket; ++ } ++ ++ dwords = (len + 3) / 4; ++ ++ /* While there is space in the queue and space in the FIFO and ++ * More data to tranfer, Write packets to the Tx FIFO */ ++ txstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts); ++ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32); ++ ++ while (txstatus.b.txfspcavail > dwords && ++ dwc_ep->xfer_count < dwc_ep->xfer_len && dwc_ep->xfer_len != 0) { ++ /* Write the FIFO */ ++ dwc_otg_ep_write_packet(core_if, dwc_ep, 0); ++ ++ len = dwc_ep->xfer_len - dwc_ep->xfer_count; ++ if (len > dwc_ep->maxpacket) { ++ len = dwc_ep->maxpacket; ++ } ++ ++ dwords = (len + 3) / 4; ++ txstatus.d32 = ++ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts); ++ DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum, ++ txstatus.d32); ++ } ++ ++ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, ++ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts)); ++ ++ return 1; ++} ++/** ++ * This function does the setup for a data transfer for an EP and ++ * starts the transfer. For an IN transfer, the packets will be ++ * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, ++ * the packets are unloaded from the Rx FIFO in the ISR. the ISR. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to start the transfer on. ++ */ ++ ++void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ depctl_data_t depctl; ++ deptsiz_data_t deptsiz; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__); ++ DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d " ++ "xfer_buff=%p start_xfer_buff=%p, total_len = %d\n", ++ ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len, ++ ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff, ++ ep->total_len); ++ /* IN endpoint */ ++ if (ep->is_in == 1) { ++ dwc_otg_dev_in_ep_regs_t *in_regs = ++ core_if->dev_if->in_ep_regs[ep->num]; ++ ++ gnptxsts_data_t gtxstatus; ++ ++ gtxstatus.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->gnptxsts); ++ ++ if (core_if->en_multiple_tx_fifo == 0 ++ && gtxstatus.b.nptxqspcavail == 0 && !core_if->dma_enable) { ++#ifdef DEBUG ++ DWC_PRINTF("TX Queue Full (0x%0x)\n", gtxstatus.d32); ++#endif ++ return; ++ } ++ ++ depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl)); ++ deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz)); ++ ++ if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT) ++ ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ? ++ ep->maxxfer : (ep->total_len - ep->xfer_len); ++ else ++ ep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len - ep->xfer_len)) ? ++ MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len); ++ ++ ++ /* Zero Length Packet? */ ++ if ((ep->xfer_len - ep->xfer_count) == 0) { ++ deptsiz.b.xfersize = 0; ++ deptsiz.b.pktcnt = 1; ++ } else { ++ /* Program the transfer size and packet count ++ * as follows: xfersize = N * maxpacket + ++ * short_packet pktcnt = N + (short_packet ++ * exist ? 1 : 0) ++ */ ++ deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count; ++ deptsiz.b.pktcnt = ++ (ep->xfer_len - ep->xfer_count - 1 + ++ ep->maxpacket) / ep->maxpacket; ++ if (deptsiz.b.pktcnt > MAX_PKT_CNT) { ++ deptsiz.b.pktcnt = MAX_PKT_CNT; ++ deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket; ++ } ++ if (ep->type == DWC_OTG_EP_TYPE_ISOC) ++ deptsiz.b.mc = deptsiz.b.pktcnt; ++ } ++ ++ /* Write the DMA register */ ++ if (core_if->dma_enable) { ++ if (core_if->dma_desc_enable == 0) { ++ if (ep->type != DWC_OTG_EP_TYPE_ISOC) ++ deptsiz.b.mc = 1; ++ DWC_WRITE_REG32(&in_regs->dieptsiz, ++ deptsiz.d32); ++ DWC_WRITE_REG32(&(in_regs->diepdma), ++ (uint32_t) ep->dma_addr); ++ } else { ++#ifdef DWC_UTE_CFI ++ /* The descriptor chain should be already initialized by now */ ++ if (ep->buff_mode != BM_STANDARD) { ++ DWC_WRITE_REG32(&in_regs->diepdma, ++ ep->descs_dma_addr); ++ } else { ++#endif ++ init_dma_desc_chain(core_if, ep); ++ /** DIEPDMAn Register write */ ++ DWC_WRITE_REG32(&in_regs->diepdma, ++ ep->dma_desc_addr); ++#ifdef DWC_UTE_CFI ++ } ++#endif ++ } ++ } else { ++ DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32); ++ if (ep->type != DWC_OTG_EP_TYPE_ISOC) { ++ /** ++ * Enable the Non-Periodic Tx FIFO empty interrupt, ++ * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, ++ * the data will be written into the fifo by the ISR. ++ */ ++ if (core_if->en_multiple_tx_fifo == 0) { ++ intr_mask.b.nptxfempty = 1; ++ DWC_MODIFY_REG32 ++ (&core_if->core_global_regs->gintmsk, ++ intr_mask.d32, intr_mask.d32); ++ } else { ++ /* Enable the Tx FIFO Empty Interrupt for this EP */ ++ if (ep->xfer_len > 0) { ++ uint32_t fifoemptymsk = 0; ++ fifoemptymsk = 1 << ep->num; ++ DWC_MODIFY_REG32 ++ (&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk, ++ 0, fifoemptymsk); ++ ++ } ++ } ++ } else { ++ write_isoc_tx_fifo(core_if, ep); ++ } ++ } ++ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) ++ depctl.b.nextep = core_if->nextep_seq[ep->num]; ++ ++ if (ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ dsts_data_t dsts = {.d32 = 0}; ++ if (ep->bInterval == 1) { ++ dsts.d32 = ++ DWC_READ_REG32(&core_if->dev_if-> ++ dev_global_regs->dsts); ++ ep->frame_num = dsts.b.soffn + ep->bInterval; ++ if (ep->frame_num > 0x3FFF) { ++ ep->frm_overrun = 1; ++ ep->frame_num &= 0x3FFF; ++ } else ++ ep->frm_overrun = 0; ++ if (ep->frame_num & 0x1) { ++ depctl.b.setd1pid = 1; ++ } else { ++ depctl.b.setd0pid = 1; ++ } ++ } ++ } ++ /* EP enable, IN data in FIFO */ ++ depctl.b.cnak = 1; ++ depctl.b.epena = 1; ++ DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32); ++ ++ } else { ++ /* OUT endpoint */ ++ dwc_otg_dev_out_ep_regs_t *out_regs = ++ core_if->dev_if->out_ep_regs[ep->num]; ++ ++ depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl)); ++ deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz)); ++ ++ if (!core_if->dma_desc_enable) { ++ if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT) ++ ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ? ++ ep->maxxfer : (ep->total_len - ep->xfer_len); ++ else ++ ep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len ++ - ep->xfer_len)) ? MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len); ++ } ++ ++ /* Program the transfer size and packet count as follows: ++ * ++ * pktcnt = N ++ * xfersize = N * maxpacket ++ */ ++ if ((ep->xfer_len - ep->xfer_count) == 0) { ++ /* Zero Length Packet */ ++ deptsiz.b.xfersize = ep->maxpacket; ++ deptsiz.b.pktcnt = 1; ++ } else { ++ deptsiz.b.pktcnt = ++ (ep->xfer_len - ep->xfer_count + ++ (ep->maxpacket - 1)) / ep->maxpacket; ++ if (deptsiz.b.pktcnt > MAX_PKT_CNT) { ++ deptsiz.b.pktcnt = MAX_PKT_CNT; ++ } ++ if (!core_if->dma_desc_enable) { ++ ep->xfer_len = ++ deptsiz.b.pktcnt * ep->maxpacket + ep->xfer_count; ++ } ++ deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count; ++ } ++ ++ DWC_DEBUGPL(DBG_PCDV, "ep%d xfersize=%d pktcnt=%d\n", ++ ep->num, deptsiz.b.xfersize, deptsiz.b.pktcnt); ++ ++ if (core_if->dma_enable) { ++ if (!core_if->dma_desc_enable) { ++ DWC_WRITE_REG32(&out_regs->doeptsiz, ++ deptsiz.d32); ++ ++ DWC_WRITE_REG32(&(out_regs->doepdma), ++ (uint32_t) ep->dma_addr); ++ } else { ++#ifdef DWC_UTE_CFI ++ /* The descriptor chain should be already initialized by now */ ++ if (ep->buff_mode != BM_STANDARD) { ++ DWC_WRITE_REG32(&out_regs->doepdma, ++ ep->descs_dma_addr); ++ } else { ++#endif ++ /** This is used for interrupt out transfers*/ ++ if (!ep->xfer_len) ++ ep->xfer_len = ep->total_len; ++ init_dma_desc_chain(core_if, ep); ++ ++ if (core_if->core_params->dev_out_nak) { ++ if (ep->type == DWC_OTG_EP_TYPE_BULK) { ++ deptsiz.b.pktcnt = (ep->total_len + ++ (ep->maxpacket - 1)) / ep->maxpacket; ++ deptsiz.b.xfersize = ep->total_len; ++ /* Remember initial value of doeptsiz */ ++ core_if->start_doeptsiz_val[ep->num] = deptsiz.d32; ++ DWC_WRITE_REG32(&out_regs->doeptsiz, ++ deptsiz.d32); ++ } ++ } ++ /** DOEPDMAn Register write */ ++ DWC_WRITE_REG32(&out_regs->doepdma, ++ ep->dma_desc_addr); ++#ifdef DWC_UTE_CFI ++ } ++#endif ++ } ++ } else { ++ DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32); ++ } ++ ++ if (ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ dsts_data_t dsts = {.d32 = 0}; ++ if (ep->bInterval == 1) { ++ dsts.d32 = ++ DWC_READ_REG32(&core_if->dev_if-> ++ dev_global_regs->dsts); ++ ep->frame_num = dsts.b.soffn + ep->bInterval; ++ if (ep->frame_num > 0x3FFF) { ++ ep->frm_overrun = 1; ++ ep->frame_num &= 0x3FFF; ++ } else ++ ep->frm_overrun = 0; ++ ++ if (ep->frame_num & 0x1) { ++ depctl.b.setd1pid = 1; ++ } else { ++ depctl.b.setd0pid = 1; ++ } ++ } ++ } ++ ++ /* EP enable */ ++ depctl.b.cnak = 1; ++ depctl.b.epena = 1; ++ ++ DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32); ++ ++ DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n", ++ DWC_READ_REG32(&out_regs->doepctl), ++ DWC_READ_REG32(&out_regs->doeptsiz)); ++ DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n", ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs-> ++ daintmsk), ++ DWC_READ_REG32(&core_if->core_global_regs-> ++ gintmsk)); ++ ++ /* Timer is scheduling only for out bulk transfers for ++ * "Device DDMA OUT NAK Enhancement" feature to inform user ++ * about received data payload in case of timeout ++ */ ++ if (core_if->core_params->dev_out_nak) { ++ if (ep->type == DWC_OTG_EP_TYPE_BULK) { ++ core_if->ep_xfer_info[ep->num].core_if = core_if; ++ core_if->ep_xfer_info[ep->num].ep = ep; ++ core_if->ep_xfer_info[ep->num].state = 1; ++ ++ /* Start a timer for this transfer. */ ++ DWC_TIMER_SCHEDULE(core_if->ep_xfer_timer[ep->num], 10000); ++ } ++ } ++ } ++} ++ ++/** ++ * This function setup a zero length transfer in Buffer DMA and ++ * Slave modes for usb requests with zero field set ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to start the transfer on. ++ * ++ */ ++void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ ++ depctl_data_t depctl; ++ deptsiz_data_t deptsiz; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__); ++ DWC_PRINTF("zero length transfer is called\n"); ++ ++ /* IN endpoint */ ++ if (ep->is_in == 1) { ++ dwc_otg_dev_in_ep_regs_t *in_regs = ++ core_if->dev_if->in_ep_regs[ep->num]; ++ ++ depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl)); ++ deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz)); ++ ++ deptsiz.b.xfersize = 0; ++ deptsiz.b.pktcnt = 1; ++ ++ /* Write the DMA register */ ++ if (core_if->dma_enable) { ++ if (core_if->dma_desc_enable == 0) { ++ deptsiz.b.mc = 1; ++ DWC_WRITE_REG32(&in_regs->dieptsiz, ++ deptsiz.d32); ++ DWC_WRITE_REG32(&(in_regs->diepdma), ++ (uint32_t) ep->dma_addr); ++ } ++ } else { ++ DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32); ++ /** ++ * Enable the Non-Periodic Tx FIFO empty interrupt, ++ * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, ++ * the data will be written into the fifo by the ISR. ++ */ ++ if (core_if->en_multiple_tx_fifo == 0) { ++ intr_mask.b.nptxfempty = 1; ++ DWC_MODIFY_REG32(&core_if-> ++ core_global_regs->gintmsk, ++ intr_mask.d32, intr_mask.d32); ++ } else { ++ /* Enable the Tx FIFO Empty Interrupt for this EP */ ++ if (ep->xfer_len > 0) { ++ uint32_t fifoemptymsk = 0; ++ fifoemptymsk = 1 << ep->num; ++ DWC_MODIFY_REG32(&core_if-> ++ dev_if->dev_global_regs->dtknqr4_fifoemptymsk, ++ 0, fifoemptymsk); ++ } ++ } ++ } ++ ++ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) ++ depctl.b.nextep = core_if->nextep_seq[ep->num]; ++ /* EP enable, IN data in FIFO */ ++ depctl.b.cnak = 1; ++ depctl.b.epena = 1; ++ DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32); ++ ++ } else { ++ /* OUT endpoint */ ++ dwc_otg_dev_out_ep_regs_t *out_regs = ++ core_if->dev_if->out_ep_regs[ep->num]; ++ ++ depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl)); ++ deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz)); ++ ++ /* Zero Length Packet */ ++ deptsiz.b.xfersize = ep->maxpacket; ++ deptsiz.b.pktcnt = 1; ++ ++ if (core_if->dma_enable) { ++ if (!core_if->dma_desc_enable) { ++ DWC_WRITE_REG32(&out_regs->doeptsiz, ++ deptsiz.d32); ++ ++ DWC_WRITE_REG32(&(out_regs->doepdma), ++ (uint32_t) ep->dma_addr); ++ } ++ } else { ++ DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32); ++ } ++ ++ /* EP enable */ ++ depctl.b.cnak = 1; ++ depctl.b.epena = 1; ++ ++ DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32); ++ ++ } ++} ++ ++/** ++ * This function does the setup for a data transfer for EP0 and starts ++ * the transfer. For an IN transfer, the packets will be loaded into ++ * the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are ++ * unloaded from the Rx FIFO in the ISR. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP0 data. ++ */ ++void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ depctl_data_t depctl; ++ deptsiz0_data_t deptsiz; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ dwc_otg_dev_dma_desc_t *dma_desc; ++ ++ DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d " ++ "xfer_buff=%p start_xfer_buff=%p \n", ++ ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len, ++ ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff); ++ ++ ep->total_len = ep->xfer_len; ++ ++ /* IN endpoint */ ++ if (ep->is_in == 1) { ++ dwc_otg_dev_in_ep_regs_t *in_regs = ++ core_if->dev_if->in_ep_regs[0]; ++ ++ gnptxsts_data_t gtxstatus; ++ ++ if (core_if->snpsid >= OTG_CORE_REV_3_00a) { ++ depctl.d32 = DWC_READ_REG32(&in_regs->diepctl); ++ if (depctl.b.epena) ++ return; ++ } ++ ++ gtxstatus.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->gnptxsts); ++ ++ /* If dedicated FIFO every time flush fifo before enable ep*/ ++ if (core_if->en_multiple_tx_fifo && core_if->snpsid >= OTG_CORE_REV_3_00a) ++ dwc_otg_flush_tx_fifo(core_if, ep->tx_fifo_num); ++ ++ if (core_if->en_multiple_tx_fifo == 0 ++ && gtxstatus.b.nptxqspcavail == 0 ++ && !core_if->dma_enable) { ++#ifdef DEBUG ++ deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz); ++ DWC_DEBUGPL(DBG_PCD, "DIEPCTL0=%0x\n", ++ DWC_READ_REG32(&in_regs->diepctl)); ++ DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n", ++ deptsiz.d32, ++ deptsiz.b.xfersize, deptsiz.b.pktcnt); ++ DWC_PRINTF("TX Queue or FIFO Full (0x%0x)\n", ++ gtxstatus.d32); ++#endif ++ return; ++ } ++ ++ depctl.d32 = DWC_READ_REG32(&in_regs->diepctl); ++ deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz); ++ ++ /* Zero Length Packet? */ ++ if (ep->xfer_len == 0) { ++ deptsiz.b.xfersize = 0; ++ deptsiz.b.pktcnt = 1; ++ } else { ++ /* Program the transfer size and packet count ++ * as follows: xfersize = N * maxpacket + ++ * short_packet pktcnt = N + (short_packet ++ * exist ? 1 : 0) ++ */ ++ if (ep->xfer_len > ep->maxpacket) { ++ ep->xfer_len = ep->maxpacket; ++ deptsiz.b.xfersize = ep->maxpacket; ++ } else { ++ deptsiz.b.xfersize = ep->xfer_len; ++ } ++ deptsiz.b.pktcnt = 1; ++ ++ } ++ DWC_DEBUGPL(DBG_PCDV, ++ "IN len=%d xfersize=%d pktcnt=%d [%08x]\n", ++ ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt, ++ deptsiz.d32); ++ ++ /* Write the DMA register */ ++ if (core_if->dma_enable) { ++ if (core_if->dma_desc_enable == 0) { ++ DWC_WRITE_REG32(&in_regs->dieptsiz, ++ deptsiz.d32); ++ ++ DWC_WRITE_REG32(&(in_regs->diepdma), ++ (uint32_t) ep->dma_addr); ++ } else { ++ dma_desc = core_if->dev_if->in_desc_addr; ++ ++ /** DMA Descriptor Setup */ ++ dma_desc->status.b.bs = BS_HOST_BUSY; ++ dma_desc->status.b.l = 1; ++ dma_desc->status.b.ioc = 1; ++ dma_desc->status.b.sp = ++ (ep->xfer_len == ep->maxpacket) ? 0 : 1; ++ dma_desc->status.b.bytes = ep->xfer_len; ++ dma_desc->buf = ep->dma_addr; ++ dma_desc->status.b.sts = 0; ++ dma_desc->status.b.bs = BS_HOST_READY; ++ ++ /** DIEPDMA0 Register write */ ++ DWC_WRITE_REG32(&in_regs->diepdma, ++ core_if-> ++ dev_if->dma_in_desc_addr); ++ } ++ } else { ++ DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32); ++ } ++ ++ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) ++ depctl.b.nextep = core_if->nextep_seq[ep->num]; ++ /* EP enable, IN data in FIFO */ ++ depctl.b.cnak = 1; ++ depctl.b.epena = 1; ++ DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32); ++ ++ /** ++ * Enable the Non-Periodic Tx FIFO empty interrupt, the ++ * data will be written into the fifo by the ISR. ++ */ ++ if (!core_if->dma_enable) { ++ if (core_if->en_multiple_tx_fifo == 0) { ++ intr_mask.b.nptxfempty = 1; ++ DWC_MODIFY_REG32(&core_if-> ++ core_global_regs->gintmsk, ++ intr_mask.d32, intr_mask.d32); ++ } else { ++ /* Enable the Tx FIFO Empty Interrupt for this EP */ ++ if (ep->xfer_len > 0) { ++ uint32_t fifoemptymsk = 0; ++ fifoemptymsk |= 1 << ep->num; ++ DWC_MODIFY_REG32(&core_if-> ++ dev_if->dev_global_regs->dtknqr4_fifoemptymsk, ++ 0, fifoemptymsk); ++ } ++ } ++ } ++ } else { ++ /* OUT endpoint */ ++ dwc_otg_dev_out_ep_regs_t *out_regs = ++ core_if->dev_if->out_ep_regs[0]; ++ ++ depctl.d32 = DWC_READ_REG32(&out_regs->doepctl); ++ deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz); ++ ++ /* Program the transfer size and packet count as follows: ++ * xfersize = N * (maxpacket + 4 - (maxpacket % 4)) ++ * pktcnt = N */ ++ /* Zero Length Packet */ ++ deptsiz.b.xfersize = ep->maxpacket; ++ deptsiz.b.pktcnt = 1; ++ if (core_if->snpsid >= OTG_CORE_REV_3_00a) ++ deptsiz.b.supcnt = 3; ++ ++ DWC_DEBUGPL(DBG_PCDV, "len=%d xfersize=%d pktcnt=%d\n", ++ ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt); ++ ++ if (core_if->dma_enable) { ++ if (!core_if->dma_desc_enable) { ++ DWC_WRITE_REG32(&out_regs->doeptsiz, ++ deptsiz.d32); ++ ++ DWC_WRITE_REG32(&(out_regs->doepdma), ++ (uint32_t) ep->dma_addr); ++ } else { ++ dma_desc = core_if->dev_if->out_desc_addr; ++ ++ /** DMA Descriptor Setup */ ++ dma_desc->status.b.bs = BS_HOST_BUSY; ++ if (core_if->snpsid >= OTG_CORE_REV_3_00a) { ++ dma_desc->status.b.mtrf = 0; ++ dma_desc->status.b.sr = 0; ++ } ++ dma_desc->status.b.l = 1; ++ dma_desc->status.b.ioc = 1; ++ dma_desc->status.b.bytes = ep->maxpacket; ++ dma_desc->buf = ep->dma_addr; ++ dma_desc->status.b.sts = 0; ++ dma_desc->status.b.bs = BS_HOST_READY; ++ ++ /** DOEPDMA0 Register write */ ++ DWC_WRITE_REG32(&out_regs->doepdma, ++ core_if->dev_if-> ++ dma_out_desc_addr); ++ } ++ } else { ++ DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32); ++ } ++ ++ /* EP enable */ ++ depctl.b.cnak = 1; ++ depctl.b.epena = 1; ++ DWC_WRITE_REG32(&(out_regs->doepctl), depctl.d32); ++ } ++} ++ ++/** ++ * This function continues control IN transfers started by ++ * dwc_otg_ep0_start_transfer, when the transfer does not fit in a ++ * single packet. NOTE: The DIEPCTL0/DOEPCTL0 registers only have one ++ * bit for the packet count. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP0 data. ++ */ ++void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ depctl_data_t depctl; ++ deptsiz0_data_t deptsiz; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ dwc_otg_dev_dma_desc_t *dma_desc; ++ ++ if (ep->is_in == 1) { ++ dwc_otg_dev_in_ep_regs_t *in_regs = ++ core_if->dev_if->in_ep_regs[0]; ++ gnptxsts_data_t tx_status = {.d32 = 0 }; ++ ++ tx_status.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->gnptxsts); ++ /** @todo Should there be check for room in the Tx ++ * Status Queue. If not remove the code above this comment. */ ++ ++ depctl.d32 = DWC_READ_REG32(&in_regs->diepctl); ++ deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz); ++ ++ /* Program the transfer size and packet count ++ * as follows: xfersize = N * maxpacket + ++ * short_packet pktcnt = N + (short_packet ++ * exist ? 1 : 0) ++ */ ++ ++ if (core_if->dma_desc_enable == 0) { ++ deptsiz.b.xfersize = ++ (ep->total_len - ep->xfer_count) > ++ ep->maxpacket ? ep->maxpacket : (ep->total_len - ++ ep->xfer_count); ++ deptsiz.b.pktcnt = 1; ++ if (core_if->dma_enable == 0) { ++ ep->xfer_len += deptsiz.b.xfersize; ++ } else { ++ ep->xfer_len = deptsiz.b.xfersize; ++ } ++ DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32); ++ } else { ++ ep->xfer_len = ++ (ep->total_len - ep->xfer_count) > ++ ep->maxpacket ? ep->maxpacket : (ep->total_len - ++ ep->xfer_count); ++ ++ dma_desc = core_if->dev_if->in_desc_addr; ++ ++ /** DMA Descriptor Setup */ ++ dma_desc->status.b.bs = BS_HOST_BUSY; ++ dma_desc->status.b.l = 1; ++ dma_desc->status.b.ioc = 1; ++ dma_desc->status.b.sp = ++ (ep->xfer_len == ep->maxpacket) ? 0 : 1; ++ dma_desc->status.b.bytes = ep->xfer_len; ++ dma_desc->buf = ep->dma_addr; ++ dma_desc->status.b.sts = 0; ++ dma_desc->status.b.bs = BS_HOST_READY; ++ ++ /** DIEPDMA0 Register write */ ++ DWC_WRITE_REG32(&in_regs->diepdma, ++ core_if->dev_if->dma_in_desc_addr); ++ } ++ ++ DWC_DEBUGPL(DBG_PCDV, ++ "IN len=%d xfersize=%d pktcnt=%d [%08x]\n", ++ ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt, ++ deptsiz.d32); ++ ++ /* Write the DMA register */ ++ if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) { ++ if (core_if->dma_desc_enable == 0) ++ DWC_WRITE_REG32(&(in_regs->diepdma), ++ (uint32_t) ep->dma_addr); ++ } ++ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) ++ depctl.b.nextep = core_if->nextep_seq[ep->num]; ++ /* EP enable, IN data in FIFO */ ++ depctl.b.cnak = 1; ++ depctl.b.epena = 1; ++ DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32); ++ ++ /** ++ * Enable the Non-Periodic Tx FIFO empty interrupt, the ++ * data will be written into the fifo by the ISR. ++ */ ++ if (!core_if->dma_enable) { ++ if (core_if->en_multiple_tx_fifo == 0) { ++ /* First clear it from GINTSTS */ ++ intr_mask.b.nptxfempty = 1; ++ DWC_MODIFY_REG32(&core_if-> ++ core_global_regs->gintmsk, ++ intr_mask.d32, intr_mask.d32); ++ ++ } else { ++ /* Enable the Tx FIFO Empty Interrupt for this EP */ ++ if (ep->xfer_len > 0) { ++ uint32_t fifoemptymsk = 0; ++ fifoemptymsk |= 1 << ep->num; ++ DWC_MODIFY_REG32(&core_if-> ++ dev_if->dev_global_regs->dtknqr4_fifoemptymsk, ++ 0, fifoemptymsk); ++ } ++ } ++ } ++ } else { ++ dwc_otg_dev_out_ep_regs_t *out_regs = ++ core_if->dev_if->out_ep_regs[0]; ++ ++ depctl.d32 = DWC_READ_REG32(&out_regs->doepctl); ++ deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz); ++ ++ /* Program the transfer size and packet count ++ * as follows: xfersize = N * maxpacket + ++ * short_packet pktcnt = N + (short_packet ++ * exist ? 1 : 0) ++ */ ++ deptsiz.b.xfersize = ep->maxpacket; ++ deptsiz.b.pktcnt = 1; ++ ++ if (core_if->dma_desc_enable == 0) { ++ DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32); ++ } else { ++ dma_desc = core_if->dev_if->out_desc_addr; ++ ++ /** DMA Descriptor Setup */ ++ dma_desc->status.b.bs = BS_HOST_BUSY; ++ dma_desc->status.b.l = 1; ++ dma_desc->status.b.ioc = 1; ++ dma_desc->status.b.bytes = ep->maxpacket; ++ dma_desc->buf = ep->dma_addr; ++ dma_desc->status.b.sts = 0; ++ dma_desc->status.b.bs = BS_HOST_READY; ++ ++ /** DOEPDMA0 Register write */ ++ DWC_WRITE_REG32(&out_regs->doepdma, ++ core_if->dev_if->dma_out_desc_addr); ++ } ++ ++ DWC_DEBUGPL(DBG_PCDV, ++ "IN len=%d xfersize=%d pktcnt=%d [%08x]\n", ++ ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt, ++ deptsiz.d32); ++ ++ /* Write the DMA register */ ++ if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) { ++ if (core_if->dma_desc_enable == 0) ++ DWC_WRITE_REG32(&(out_regs->doepdma), ++ (uint32_t) ep->dma_addr); ++ ++ } ++ ++ /* EP enable, IN data in FIFO */ ++ depctl.b.cnak = 1; ++ depctl.b.epena = 1; ++ DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32); ++ ++ } ++} ++ ++#ifdef DEBUG ++void dump_msg(const u8 * buf, unsigned int length) ++{ ++ unsigned int start, num, i; ++ char line[52], *p; ++ ++ if (length >= 512) ++ return; ++ start = 0; ++ while (length > 0) { ++ num = length < 16u ? length : 16u; ++ p = line; ++ for (i = 0; i < num; ++i) { ++ if (i == 8) ++ *p++ = ' '; ++ DWC_SPRINTF(p, " %02x", buf[i]); ++ p += 3; ++ } ++ *p = 0; ++ DWC_PRINTF("%6x: %s\n", start, line); ++ buf += num; ++ start += num; ++ length -= num; ++ } ++} ++#else ++static inline void dump_msg(const u8 * buf, unsigned int length) ++{ ++} ++#endif ++ ++/** ++ * This function writes a packet into the Tx FIFO associated with the ++ * EP. For non-periodic EPs the non-periodic Tx FIFO is written. For ++ * periodic EPs the periodic Tx FIFO associated with the EP is written ++ * with all packets for the next micro-frame. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to write packet for. ++ * @param dma Indicates if DMA is being used. ++ */ ++void dwc_otg_ep_write_packet(dwc_otg_core_if_t * core_if, dwc_ep_t * ep, ++ int dma) ++{ ++ /** ++ * The buffer is padded to DWORD on a per packet basis in ++ * slave/dma mode if the MPS is not DWORD aligned. The last ++ * packet, if short, is also padded to a multiple of DWORD. ++ * ++ * ep->xfer_buff always starts DWORD aligned in memory and is a ++ * multiple of DWORD in length ++ * ++ * ep->xfer_len can be any number of bytes ++ * ++ * ep->xfer_count is a multiple of ep->maxpacket until the last ++ * packet ++ * ++ * FIFO access is DWORD */ ++ ++ uint32_t i; ++ uint32_t byte_count; ++ uint32_t dword_count; ++ uint32_t *fifo; ++ uint32_t *data_buff = (uint32_t *) ep->xfer_buff; ++ ++ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p)\n", __func__, core_if, ++ ep); ++ if (ep->xfer_count >= ep->xfer_len) { ++ DWC_WARN("%s() No data for EP%d!!!\n", __func__, ep->num); ++ return; ++ } ++ ++ /* Find the byte length of the packet either short packet or MPS */ ++ if ((ep->xfer_len - ep->xfer_count) < ep->maxpacket) { ++ byte_count = ep->xfer_len - ep->xfer_count; ++ } else { ++ byte_count = ep->maxpacket; ++ } ++ ++ /* Find the DWORD length, padded by extra bytes as neccessary if MPS ++ * is not a multiple of DWORD */ ++ dword_count = (byte_count + 3) / 4; ++ ++#ifdef VERBOSE ++ dump_msg(ep->xfer_buff, byte_count); ++#endif ++ ++ /**@todo NGS Where are the Periodic Tx FIFO addresses ++ * intialized? What should this be? */ ++ ++ fifo = core_if->data_fifo[ep->num]; ++ ++ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "fifo=%p buff=%p *p=%08x bc=%d\n", ++ fifo, data_buff, *data_buff, byte_count); ++ ++ if (!dma) { ++ for (i = 0; i < dword_count; i++, data_buff++) { ++ DWC_WRITE_REG32(fifo, *data_buff); ++ } ++ } ++ ++ ep->xfer_count += byte_count; ++ ep->xfer_buff += byte_count; ++ ep->dma_addr += byte_count; ++} ++ ++/** ++ * Set the EP STALL. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to set the stall on. ++ */ ++void dwc_otg_ep_set_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ depctl_data_t depctl; ++ volatile uint32_t *depctl_addr; ++ ++ DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num, ++ (ep->is_in ? "IN" : "OUT")); ++ ++ if (ep->is_in == 1) { ++ depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl); ++ depctl.d32 = DWC_READ_REG32(depctl_addr); ++ ++ /* set the disable and stall bits */ ++ if (depctl.b.epena) { ++ depctl.b.epdis = 1; ++ } ++ depctl.b.stall = 1; ++ DWC_WRITE_REG32(depctl_addr, depctl.d32); ++ } else { ++ depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl); ++ depctl.d32 = DWC_READ_REG32(depctl_addr); ++ ++ /* set the stall bit */ ++ depctl.b.stall = 1; ++ DWC_WRITE_REG32(depctl_addr, depctl.d32); ++ } ++ ++ DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr)); ++ ++ return; ++} ++ ++/** ++ * Clear the EP STALL. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to clear stall from. ++ */ ++void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ depctl_data_t depctl; ++ volatile uint32_t *depctl_addr; ++ ++ DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num, ++ (ep->is_in ? "IN" : "OUT")); ++ ++ if (ep->is_in == 1) { ++ depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl); ++ } else { ++ depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl); ++ } ++ ++ depctl.d32 = DWC_READ_REG32(depctl_addr); ++ ++ /* clear the stall bits */ ++ depctl.b.stall = 0; ++ ++ /* ++ * USB Spec 9.4.5: For endpoints using data toggle, regardless ++ * of whether an endpoint has the Halt feature set, a ++ * ClearFeature(ENDPOINT_HALT) request always results in the ++ * data toggle being reinitialized to DATA0. ++ */ ++ if (ep->type == DWC_OTG_EP_TYPE_INTR || ++ ep->type == DWC_OTG_EP_TYPE_BULK) { ++ depctl.b.setd0pid = 1; /* DATA0 */ ++ } ++ ++ DWC_WRITE_REG32(depctl_addr, depctl.d32); ++ DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr)); ++ return; ++} ++ ++/** ++ * This function reads a packet from the Rx FIFO into the destination ++ * buffer. To read SETUP data use dwc_otg_read_setup_packet. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param dest Destination buffer for the packet. ++ * @param bytes Number of bytes to copy to the destination. ++ */ ++void dwc_otg_read_packet(dwc_otg_core_if_t * core_if, ++ uint8_t * dest, uint16_t bytes) ++{ ++ int i; ++ int word_count = (bytes + 3) / 4; ++ ++ volatile uint32_t *fifo = core_if->data_fifo[0]; ++ uint32_t *data_buff = (uint32_t *) dest; ++ ++ /** ++ * @todo Account for the case where _dest is not dword aligned. This ++ * requires reading data from the FIFO into a uint32_t temp buffer, ++ * then moving it into the data buffer. ++ */ ++ ++ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__, ++ core_if, dest, bytes); ++ ++ for (i = 0; i < word_count; i++, data_buff++) { ++ *data_buff = DWC_READ_REG32(fifo); ++ } ++ ++ return; ++} ++ ++/** ++ * This functions reads the device registers and prints them ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * core_if) ++{ ++ int i; ++ volatile uint32_t *addr; ++ ++ DWC_PRINTF("Device Global Registers\n"); ++ addr = &core_if->dev_if->dev_global_regs->dcfg; ++ DWC_PRINTF("DCFG @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->dev_if->dev_global_regs->dctl; ++ DWC_PRINTF("DCTL @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->dev_if->dev_global_regs->dsts; ++ DWC_PRINTF("DSTS @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->dev_if->dev_global_regs->diepmsk; ++ DWC_PRINTF("DIEPMSK @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->dev_if->dev_global_regs->doepmsk; ++ DWC_PRINTF("DOEPMSK @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->dev_if->dev_global_regs->daint; ++ DWC_PRINTF("DAINT @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->dev_if->dev_global_regs->daintmsk; ++ DWC_PRINTF("DAINTMSK @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->dev_if->dev_global_regs->dtknqr1; ++ DWC_PRINTF("DTKNQR1 @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ if (core_if->hwcfg2.b.dev_token_q_depth > 6) { ++ addr = &core_if->dev_if->dev_global_regs->dtknqr2; ++ DWC_PRINTF("DTKNQR2 @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ } ++ ++ addr = &core_if->dev_if->dev_global_regs->dvbusdis; ++ DWC_PRINTF("DVBUSID @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ ++ addr = &core_if->dev_if->dev_global_regs->dvbuspulse; ++ DWC_PRINTF("DVBUSPULSE @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ ++ addr = &core_if->dev_if->dev_global_regs->dtknqr3_dthrctl; ++ DWC_PRINTF("DTKNQR3_DTHRCTL @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ ++ if (core_if->hwcfg2.b.dev_token_q_depth > 22) { ++ addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk; ++ DWC_PRINTF("DTKNQR4 @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ } ++ ++ addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk; ++ DWC_PRINTF("FIFOEMPMSK @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ ++ if (core_if->hwcfg2.b.multi_proc_int) { ++ ++ addr = &core_if->dev_if->dev_global_regs->deachint; ++ DWC_PRINTF("DEACHINT @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->dev_if->dev_global_regs->deachintmsk; ++ DWC_PRINTF("DEACHINTMSK @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ ++ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) { ++ addr = ++ &core_if->dev_if-> ++ dev_global_regs->diepeachintmsk[i]; ++ DWC_PRINTF("DIEPEACHINTMSK[%d] @0x%08lX : 0x%08X\n", ++ i, (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ } ++ ++ for (i = 0; i <= core_if->dev_if->num_out_eps; i++) { ++ addr = ++ &core_if->dev_if-> ++ dev_global_regs->doepeachintmsk[i]; ++ DWC_PRINTF("DOEPEACHINTMSK[%d] @0x%08lX : 0x%08X\n", ++ i, (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ } ++ } ++ ++ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) { ++ DWC_PRINTF("Device IN EP %d Registers\n", i); ++ addr = &core_if->dev_if->in_ep_regs[i]->diepctl; ++ DWC_PRINTF("DIEPCTL @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->dev_if->in_ep_regs[i]->diepint; ++ DWC_PRINTF("DIEPINT @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->dev_if->in_ep_regs[i]->dieptsiz; ++ DWC_PRINTF("DIETSIZ @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->dev_if->in_ep_regs[i]->diepdma; ++ DWC_PRINTF("DIEPDMA @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->dev_if->in_ep_regs[i]->dtxfsts; ++ DWC_PRINTF("DTXFSTS @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->dev_if->in_ep_regs[i]->diepdmab; ++ DWC_PRINTF("DIEPDMAB @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, 0 /*DWC_READ_REG32(addr) */ ); ++ } ++ ++ for (i = 0; i <= core_if->dev_if->num_out_eps; i++) { ++ DWC_PRINTF("Device OUT EP %d Registers\n", i); ++ addr = &core_if->dev_if->out_ep_regs[i]->doepctl; ++ DWC_PRINTF("DOEPCTL @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->dev_if->out_ep_regs[i]->doepint; ++ DWC_PRINTF("DOEPINT @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->dev_if->out_ep_regs[i]->doeptsiz; ++ DWC_PRINTF("DOETSIZ @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->dev_if->out_ep_regs[i]->doepdma; ++ DWC_PRINTF("DOEPDMA @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ if (core_if->dma_enable) { /* Don't access this register in SLAVE mode */ ++ addr = &core_if->dev_if->out_ep_regs[i]->doepdmab; ++ DWC_PRINTF("DOEPDMAB @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ } ++ ++ } ++} ++ ++/** ++ * This functions reads the SPRAM and prints its content ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++void dwc_otg_dump_spram(dwc_otg_core_if_t * core_if) ++{ ++ volatile uint8_t *addr, *start_addr, *end_addr; ++ ++ DWC_PRINTF("SPRAM Data:\n"); ++ start_addr = (void *)core_if->core_global_regs; ++ DWC_PRINTF("Base Address: 0x%8lX\n", (unsigned long)start_addr); ++ start_addr += 0x00028000; ++ end_addr = (void *)core_if->core_global_regs; ++ end_addr += 0x000280e0; ++ ++ for (addr = start_addr; addr < end_addr; addr += 16) { ++ DWC_PRINTF ++ ("0x%8lX:\t%2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X\n", ++ (unsigned long)addr, addr[0], addr[1], addr[2], addr[3], ++ addr[4], addr[5], addr[6], addr[7], addr[8], addr[9], ++ addr[10], addr[11], addr[12], addr[13], addr[14], addr[15] ++ ); ++ } ++ ++ return; ++} ++ ++/** ++ * This function reads the host registers and prints them ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++void dwc_otg_dump_host_registers(dwc_otg_core_if_t * core_if) ++{ ++ int i; ++ volatile uint32_t *addr; ++ ++ DWC_PRINTF("Host Global Registers\n"); ++ addr = &core_if->host_if->host_global_regs->hcfg; ++ DWC_PRINTF("HCFG @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->host_if->host_global_regs->hfir; ++ DWC_PRINTF("HFIR @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->host_if->host_global_regs->hfnum; ++ DWC_PRINTF("HFNUM @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->host_if->host_global_regs->hptxsts; ++ DWC_PRINTF("HPTXSTS @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->host_if->host_global_regs->haint; ++ DWC_PRINTF("HAINT @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->host_if->host_global_regs->haintmsk; ++ DWC_PRINTF("HAINTMSK @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ if (core_if->dma_desc_enable) { ++ addr = &core_if->host_if->host_global_regs->hflbaddr; ++ DWC_PRINTF("HFLBADDR @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ } ++ ++ addr = core_if->host_if->hprt0; ++ DWC_PRINTF("HPRT0 @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ ++ for (i = 0; i < core_if->core_params->host_channels; i++) { ++ DWC_PRINTF("Host Channel %d Specific Registers\n", i); ++ addr = &core_if->host_if->hc_regs[i]->hcchar; ++ DWC_PRINTF("HCCHAR @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->host_if->hc_regs[i]->hcsplt; ++ DWC_PRINTF("HCSPLT @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->host_if->hc_regs[i]->hcint; ++ DWC_PRINTF("HCINT @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->host_if->hc_regs[i]->hcintmsk; ++ DWC_PRINTF("HCINTMSK @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->host_if->hc_regs[i]->hctsiz; ++ DWC_PRINTF("HCTSIZ @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->host_if->hc_regs[i]->hcdma; ++ DWC_PRINTF("HCDMA @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ if (core_if->dma_desc_enable) { ++ addr = &core_if->host_if->hc_regs[i]->hcdmab; ++ DWC_PRINTF("HCDMAB @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ } ++ ++ } ++ return; ++} ++ ++/** ++ * This function reads the core global registers and prints them ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++void dwc_otg_dump_global_registers(dwc_otg_core_if_t * core_if) ++{ ++ int i, ep_num; ++ volatile uint32_t *addr; ++ char *txfsiz; ++ ++ DWC_PRINTF("Core Global Registers\n"); ++ addr = &core_if->core_global_regs->gotgctl; ++ DWC_PRINTF("GOTGCTL @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->gotgint; ++ DWC_PRINTF("GOTGINT @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->gahbcfg; ++ DWC_PRINTF("GAHBCFG @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->gusbcfg; ++ DWC_PRINTF("GUSBCFG @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->grstctl; ++ DWC_PRINTF("GRSTCTL @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->gintsts; ++ DWC_PRINTF("GINTSTS @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->gintmsk; ++ DWC_PRINTF("GINTMSK @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->grxstsr; ++ DWC_PRINTF("GRXSTSR @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->grxfsiz; ++ DWC_PRINTF("GRXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->gnptxfsiz; ++ DWC_PRINTF("GNPTXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->gnptxsts; ++ DWC_PRINTF("GNPTXSTS @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->gi2cctl; ++ DWC_PRINTF("GI2CCTL @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->gpvndctl; ++ DWC_PRINTF("GPVNDCTL @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->ggpio; ++ DWC_PRINTF("GGPIO @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->guid; ++ DWC_PRINTF("GUID @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->gsnpsid; ++ DWC_PRINTF("GSNPSID @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->ghwcfg1; ++ DWC_PRINTF("GHWCFG1 @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->ghwcfg2; ++ DWC_PRINTF("GHWCFG2 @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->ghwcfg3; ++ DWC_PRINTF("GHWCFG3 @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->ghwcfg4; ++ DWC_PRINTF("GHWCFG4 @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->glpmcfg; ++ DWC_PRINTF("GLPMCFG @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->gpwrdn; ++ DWC_PRINTF("GPWRDN @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->gdfifocfg; ++ DWC_PRINTF("GDFIFOCFG @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->adpctl; ++ DWC_PRINTF("ADPCTL @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ dwc_otg_adp_read_reg(core_if)); ++ addr = &core_if->core_global_regs->hptxfsiz; ++ DWC_PRINTF("HPTXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ ++ if (core_if->en_multiple_tx_fifo == 0) { ++ ep_num = core_if->hwcfg4.b.num_dev_perio_in_ep; ++ txfsiz = "DPTXFSIZ"; ++ } else { ++ ep_num = core_if->hwcfg4.b.num_in_eps; ++ txfsiz = "DIENPTXF"; ++ } ++ for (i = 0; i < ep_num; i++) { ++ addr = &core_if->core_global_regs->dtxfsiz[i]; ++ DWC_PRINTF("%s[%d] @0x%08lX : 0x%08X\n", txfsiz, i + 1, ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ } ++ addr = core_if->pcgcctl; ++ DWC_PRINTF("PCGCCTL @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++} ++ ++/** ++ * Flush a Tx FIFO. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param num Tx FIFO to flush. ++ */ ++void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * core_if, const int num) ++{ ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ volatile grstctl_t greset = {.d32 = 0 }; ++ int count = 0; ++ ++ DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "Flush Tx FIFO %d\n", num); ++ ++ greset.b.txfflsh = 1; ++ greset.b.txfnum = num; ++ DWC_WRITE_REG32(&global_regs->grstctl, greset.d32); ++ ++ do { ++ greset.d32 = DWC_READ_REG32(&global_regs->grstctl); ++ if (++count > 10000) { ++ DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n", ++ __func__, greset.d32, ++ DWC_READ_REG32(&global_regs->gnptxsts)); ++ break; ++ } ++ dwc_udelay(1); ++ } while (greset.b.txfflsh == 1); ++ ++ /* Wait for 3 PHY Clocks */ ++ dwc_udelay(1); ++} ++ ++/** ++ * Flush Rx FIFO. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * core_if) ++{ ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ volatile grstctl_t greset = {.d32 = 0 }; ++ int count = 0; ++ ++ DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "%s\n", __func__); ++ /* ++ * ++ */ ++ greset.b.rxfflsh = 1; ++ DWC_WRITE_REG32(&global_regs->grstctl, greset.d32); ++ ++ do { ++ greset.d32 = DWC_READ_REG32(&global_regs->grstctl); ++ if (++count > 10000) { ++ DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__, ++ greset.d32); ++ break; ++ } ++ dwc_udelay(1); ++ } while (greset.b.rxfflsh == 1); ++ ++ /* Wait for 3 PHY Clocks */ ++ dwc_udelay(1); ++} ++ ++/** ++ * Do core a soft reset of the core. Be careful with this because it ++ * resets all the internal state machines of the core. ++ */ ++void dwc_otg_core_reset(dwc_otg_core_if_t * core_if) ++{ ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ volatile grstctl_t greset = {.d32 = 0 }; ++ int count = 0; ++ ++ DWC_DEBUGPL(DBG_CILV, "%s\n", __func__); ++ /* Wait for AHB master IDLE state. */ ++ do { ++ dwc_udelay(10); ++ greset.d32 = DWC_READ_REG32(&global_regs->grstctl); ++ if (++count > 100000) { ++ DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x\n", __func__, ++ greset.d32); ++ return; ++ } ++ } ++ while (greset.b.ahbidle == 0); ++ ++ /* Core Soft Reset */ ++ count = 0; ++ greset.b.csftrst = 1; ++ DWC_WRITE_REG32(&global_regs->grstctl, greset.d32); ++ do { ++ greset.d32 = DWC_READ_REG32(&global_regs->grstctl); ++ if (++count > 10000) { ++ DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n", ++ __func__, greset.d32); ++ break; ++ } ++ dwc_udelay(1); ++ } ++ while (greset.b.csftrst == 1); ++ ++ /* Wait for 3 PHY Clocks */ ++ dwc_mdelay(100); ++} ++ ++uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if) ++{ ++ return (dwc_otg_mode(_core_if) != DWC_HOST_MODE); ++} ++ ++uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if) ++{ ++ return (dwc_otg_mode(_core_if) == DWC_HOST_MODE); ++} ++ ++/** ++ * Register HCD callbacks. The callbacks are used to start and stop ++ * the HCD for interrupt processing. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param cb the HCD callback structure. ++ * @param p pointer to be passed to callback function (usb_hcd*). ++ */ ++void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * core_if, ++ dwc_otg_cil_callbacks_t * cb, void *p) ++{ ++ core_if->hcd_cb = cb; ++ cb->p = p; ++} ++ ++/** ++ * Register PCD callbacks. The callbacks are used to start and stop ++ * the PCD for interrupt processing. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param cb the PCD callback structure. ++ * @param p pointer to be passed to callback function (pcd*). ++ */ ++void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * core_if, ++ dwc_otg_cil_callbacks_t * cb, void *p) ++{ ++ core_if->pcd_cb = cb; ++ cb->p = p; ++} ++ ++#ifdef DWC_EN_ISOC ++ ++/** ++ * This function writes isoc data per 1 (micro)frame into tx fifo ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to start the transfer on. ++ * ++ */ ++void write_isoc_frame_data(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ dwc_otg_dev_in_ep_regs_t *ep_regs; ++ dtxfsts_data_t txstatus = {.d32 = 0 }; ++ uint32_t len = 0; ++ uint32_t dwords; ++ ++ ep->xfer_len = ep->data_per_frame; ++ ep->xfer_count = 0; ++ ++ ep_regs = core_if->dev_if->in_ep_regs[ep->num]; ++ ++ len = ep->xfer_len - ep->xfer_count; ++ ++ if (len > ep->maxpacket) { ++ len = ep->maxpacket; ++ } ++ ++ dwords = (len + 3) / 4; ++ ++ /* While there is space in the queue and space in the FIFO and ++ * More data to tranfer, Write packets to the Tx FIFO */ ++ txstatus.d32 = ++ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts); ++ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", ep->num, txstatus.d32); ++ ++ while (txstatus.b.txfspcavail > dwords && ++ ep->xfer_count < ep->xfer_len && ep->xfer_len != 0) { ++ /* Write the FIFO */ ++ dwc_otg_ep_write_packet(core_if, ep, 0); ++ ++ len = ep->xfer_len - ep->xfer_count; ++ if (len > ep->maxpacket) { ++ len = ep->maxpacket; ++ } ++ ++ dwords = (len + 3) / 4; ++ txstatus.d32 = ++ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]-> ++ dtxfsts); ++ DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", ep->num, ++ txstatus.d32); ++ } ++} ++ ++/** ++ * This function initializes a descriptor chain for Isochronous transfer ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to start the transfer on. ++ * ++ */ ++void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if, ++ dwc_ep_t * ep) ++{ ++ deptsiz_data_t deptsiz = {.d32 = 0 }; ++ depctl_data_t depctl = {.d32 = 0 }; ++ dsts_data_t dsts = {.d32 = 0 }; ++ volatile uint32_t *addr; ++ ++ if (ep->is_in) { ++ addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl; ++ } else { ++ addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl; ++ } ++ ++ ep->xfer_len = ep->data_per_frame; ++ ep->xfer_count = 0; ++ ep->xfer_buff = ep->cur_pkt_addr; ++ ep->dma_addr = ep->cur_pkt_dma_addr; ++ ++ if (ep->is_in) { ++ /* Program the transfer size and packet count ++ * as follows: xfersize = N * maxpacket + ++ * short_packet pktcnt = N + (short_packet ++ * exist ? 1 : 0) ++ */ ++ deptsiz.b.xfersize = ep->xfer_len; ++ deptsiz.b.pktcnt = ++ (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket; ++ deptsiz.b.mc = deptsiz.b.pktcnt; ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz, ++ deptsiz.d32); ++ ++ /* Write the DMA register */ ++ if (core_if->dma_enable) { ++ DWC_WRITE_REG32(& ++ (core_if->dev_if->in_ep_regs[ep->num]-> ++ diepdma), (uint32_t) ep->dma_addr); ++ } ++ } else { ++ deptsiz.b.pktcnt = ++ (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket; ++ deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket; ++ ++ DWC_WRITE_REG32(&core_if->dev_if-> ++ out_ep_regs[ep->num]->doeptsiz, deptsiz.d32); ++ ++ if (core_if->dma_enable) { ++ DWC_WRITE_REG32(& ++ (core_if->dev_if-> ++ out_ep_regs[ep->num]->doepdma), ++ (uint32_t) ep->dma_addr); ++ } ++ } ++ ++ /** Enable endpoint, clear nak */ ++ ++ depctl.d32 = 0; ++ if (ep->bInterval == 1) { ++ dsts.d32 = ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); ++ ep->next_frame = dsts.b.soffn + ep->bInterval; ++ ++ if (ep->next_frame & 0x1) { ++ depctl.b.setd1pid = 1; ++ } else { ++ depctl.b.setd0pid = 1; ++ } ++ } else { ++ ep->next_frame += ep->bInterval; ++ ++ if (ep->next_frame & 0x1) { ++ depctl.b.setd1pid = 1; ++ } else { ++ depctl.b.setd0pid = 1; ++ } ++ } ++ depctl.b.epena = 1; ++ depctl.b.cnak = 1; ++ ++ DWC_MODIFY_REG32(addr, 0, depctl.d32); ++ depctl.d32 = DWC_READ_REG32(addr); ++ ++ if (ep->is_in && core_if->dma_enable == 0) { ++ write_isoc_frame_data(core_if, ep); ++ } ++ ++} ++#endif /* DWC_EN_ISOC */ ++ ++static void dwc_otg_set_uninitialized(int32_t * p, int size) ++{ ++ int i; ++ for (i = 0; i < size; i++) { ++ p[i] = -1; ++ } ++} ++ ++static int dwc_otg_param_initialized(int32_t val) ++{ ++ return val != -1; ++} ++ ++static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if) ++{ ++ int i; ++ core_if->core_params = DWC_ALLOC(sizeof(*core_if->core_params)); ++ if (!core_if->core_params) { ++ return -DWC_E_NO_MEMORY; ++ } ++ dwc_otg_set_uninitialized((int32_t *) core_if->core_params, ++ sizeof(*core_if->core_params) / ++ sizeof(int32_t)); ++ DWC_PRINTF("Setting default values for core params\n"); ++ dwc_otg_set_param_otg_cap(core_if, dwc_param_otg_cap_default); ++ dwc_otg_set_param_dma_enable(core_if, dwc_param_dma_enable_default); ++ dwc_otg_set_param_dma_desc_enable(core_if, ++ dwc_param_dma_desc_enable_default); ++ dwc_otg_set_param_opt(core_if, dwc_param_opt_default); ++ dwc_otg_set_param_dma_burst_size(core_if, ++ dwc_param_dma_burst_size_default); ++ dwc_otg_set_param_host_support_fs_ls_low_power(core_if, ++ dwc_param_host_support_fs_ls_low_power_default); ++ dwc_otg_set_param_enable_dynamic_fifo(core_if, ++ dwc_param_enable_dynamic_fifo_default); ++ dwc_otg_set_param_data_fifo_size(core_if, ++ dwc_param_data_fifo_size_default); ++ dwc_otg_set_param_dev_rx_fifo_size(core_if, ++ dwc_param_dev_rx_fifo_size_default); ++ dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if, ++ dwc_param_dev_nperio_tx_fifo_size_default); ++ dwc_otg_set_param_host_rx_fifo_size(core_if, ++ dwc_param_host_rx_fifo_size_default); ++ dwc_otg_set_param_host_nperio_tx_fifo_size(core_if, ++ dwc_param_host_nperio_tx_fifo_size_default); ++ dwc_otg_set_param_host_perio_tx_fifo_size(core_if, ++ dwc_param_host_perio_tx_fifo_size_default); ++ dwc_otg_set_param_max_transfer_size(core_if, ++ dwc_param_max_transfer_size_default); ++ dwc_otg_set_param_max_packet_count(core_if, ++ dwc_param_max_packet_count_default); ++ dwc_otg_set_param_host_channels(core_if, ++ dwc_param_host_channels_default); ++ dwc_otg_set_param_dev_endpoints(core_if, ++ dwc_param_dev_endpoints_default); ++ dwc_otg_set_param_phy_type(core_if, dwc_param_phy_type_default); ++ dwc_otg_set_param_speed(core_if, dwc_param_speed_default); ++ dwc_otg_set_param_host_ls_low_power_phy_clk(core_if, ++ dwc_param_host_ls_low_power_phy_clk_default); ++ dwc_otg_set_param_phy_ulpi_ddr(core_if, dwc_param_phy_ulpi_ddr_default); ++ dwc_otg_set_param_phy_ulpi_ext_vbus(core_if, ++ dwc_param_phy_ulpi_ext_vbus_default); ++ dwc_otg_set_param_phy_utmi_width(core_if, ++ dwc_param_phy_utmi_width_default); ++ dwc_otg_set_param_ts_dline(core_if, dwc_param_ts_dline_default); ++ dwc_otg_set_param_i2c_enable(core_if, dwc_param_i2c_enable_default); ++ dwc_otg_set_param_ulpi_fs_ls(core_if, dwc_param_ulpi_fs_ls_default); ++ dwc_otg_set_param_en_multiple_tx_fifo(core_if, ++ dwc_param_en_multiple_tx_fifo_default); ++ for (i = 0; i < 15; i++) { ++ dwc_otg_set_param_dev_perio_tx_fifo_size(core_if, ++ dwc_param_dev_perio_tx_fifo_size_default, ++ i); ++ } ++ ++ for (i = 0; i < 15; i++) { ++ dwc_otg_set_param_dev_tx_fifo_size(core_if, ++ dwc_param_dev_tx_fifo_size_default, ++ i); ++ } ++ dwc_otg_set_param_thr_ctl(core_if, dwc_param_thr_ctl_default); ++ dwc_otg_set_param_mpi_enable(core_if, dwc_param_mpi_enable_default); ++ dwc_otg_set_param_pti_enable(core_if, dwc_param_pti_enable_default); ++ dwc_otg_set_param_lpm_enable(core_if, dwc_param_lpm_enable_default); ++ dwc_otg_set_param_ic_usb_cap(core_if, dwc_param_ic_usb_cap_default); ++ dwc_otg_set_param_tx_thr_length(core_if, ++ dwc_param_tx_thr_length_default); ++ dwc_otg_set_param_rx_thr_length(core_if, ++ dwc_param_rx_thr_length_default); ++ dwc_otg_set_param_ahb_thr_ratio(core_if, ++ dwc_param_ahb_thr_ratio_default); ++ dwc_otg_set_param_power_down(core_if, dwc_param_power_down_default); ++ dwc_otg_set_param_reload_ctl(core_if, dwc_param_reload_ctl_default); ++ dwc_otg_set_param_dev_out_nak(core_if, dwc_param_dev_out_nak_default); ++ dwc_otg_set_param_cont_on_bna(core_if, dwc_param_cont_on_bna_default); ++ dwc_otg_set_param_ahb_single(core_if, dwc_param_ahb_single_default); ++ dwc_otg_set_param_otg_ver(core_if, dwc_param_otg_ver_default); ++ dwc_otg_set_param_adp_enable(core_if, dwc_param_adp_enable_default); ++ DWC_PRINTF("Finished setting default values for core params\n"); ++ ++ return 0; ++} ++ ++uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->dma_enable; ++} ++ ++/* Checks if the parameter is outside of its valid range of values */ ++#define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \ ++ (((_param_) < (_low_)) || \ ++ ((_param_) > (_high_))) ++ ++/* Parameter access functions */ ++int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int valid; ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 0, 2)) { ++ DWC_WARN("Wrong value for otg_cap parameter\n"); ++ DWC_WARN("otg_cap parameter must be 0,1 or 2\n"); ++ retval = -DWC_E_INVALID; ++ goto out; ++ } ++ ++ valid = 1; ++ switch (val) { ++ case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE: ++ if (core_if->hwcfg2.b.op_mode != ++ DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) ++ valid = 0; ++ break; ++ case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE: ++ if ((core_if->hwcfg2.b.op_mode != ++ DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) ++ && (core_if->hwcfg2.b.op_mode != ++ DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) ++ && (core_if->hwcfg2.b.op_mode != ++ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ++ && (core_if->hwcfg2.b.op_mode != ++ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) { ++ valid = 0; ++ } ++ break; ++ case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE: ++ /* always valid */ ++ break; ++ } ++ if (!valid) { ++ if (dwc_otg_param_initialized(core_if->core_params->otg_cap)) { ++ DWC_ERROR ++ ("%d invalid for otg_cap paremter. Check HW configuration.\n", ++ val); ++ } ++ val = ++ (((core_if->hwcfg2.b.op_mode == ++ DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) ++ || (core_if->hwcfg2.b.op_mode == ++ DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) ++ || (core_if->hwcfg2.b.op_mode == ++ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ++ || (core_if->hwcfg2.b.op_mode == ++ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ? ++ DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE : ++ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->otg_cap = val; ++out: ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->otg_cap; ++} ++ ++int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong value for opt parameter\n"); ++ return -DWC_E_INVALID; ++ } ++ core_if->core_params->opt = val; ++ return 0; ++} ++ ++int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->opt; ++} ++ ++int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong value for dma enable\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if ((val == 1) && (core_if->hwcfg2.b.architecture == 0)) { ++ if (dwc_otg_param_initialized(core_if->core_params->dma_enable)) { ++ DWC_ERROR ++ ("%d invalid for dma_enable paremter. Check HW configuration.\n", ++ val); ++ } ++ val = 0; ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->dma_enable = val; ++ if (val == 0) { ++ dwc_otg_set_param_dma_desc_enable(core_if, 0); ++ } ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->dma_enable; ++} ++ ++int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong value for dma_enable\n"); ++ DWC_WARN("dma_desc_enable must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if ((val == 1) ++ && ((dwc_otg_get_param_dma_enable(core_if) == 0) ++ || (core_if->hwcfg4.b.desc_dma == 0))) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->dma_desc_enable)) { ++ DWC_ERROR ++ ("%d invalid for dma_desc_enable paremter. Check HW configuration.\n", ++ val); ++ } ++ val = 0; ++ retval = -DWC_E_INVALID; ++ } ++ core_if->core_params->dma_desc_enable = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->dma_desc_enable; ++} ++ ++int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t * core_if, ++ int32_t val) ++{ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong value for host_support_fs_low_power\n"); ++ DWC_WARN("host_support_fs_low_power must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ core_if->core_params->host_support_fs_ls_low_power = val; ++ return 0; ++} ++ ++int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t * ++ core_if) ++{ ++ return core_if->core_params->host_support_fs_ls_low_power; ++} ++ ++int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if, ++ int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong value for enable_dynamic_fifo\n"); ++ DWC_WARN("enable_dynamic_fifo must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if ((val == 1) && (core_if->hwcfg2.b.dynamic_fifo == 0)) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->enable_dynamic_fifo)) { ++ DWC_ERROR ++ ("%d invalid for enable_dynamic_fifo paremter. Check HW configuration.\n", ++ val); ++ } ++ val = 0; ++ retval = -DWC_E_INVALID; ++ } ++ core_if->core_params->enable_dynamic_fifo = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->enable_dynamic_fifo; ++} ++ ++int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 32, 32768)) { ++ DWC_WARN("Wrong value for data_fifo_size\n"); ++ DWC_WARN("data_fifo_size must be 32-32768\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val > core_if->hwcfg3.b.dfifo_depth) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->data_fifo_size)) { ++ DWC_ERROR ++ ("%d invalid for data_fifo_size parameter. Check HW configuration.\n", ++ val); ++ } ++ val = core_if->hwcfg3.b.dfifo_depth; ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->data_fifo_size = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->data_fifo_size; ++} ++ ++int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) { ++ DWC_WARN("Wrong value for dev_rx_fifo_size\n"); ++ DWC_WARN("dev_rx_fifo_size must be 16-32768\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) { ++ if (dwc_otg_param_initialized(core_if->core_params->dev_rx_fifo_size)) { ++ DWC_WARN("%d invalid for dev_rx_fifo_size parameter\n", val); ++ } ++ val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz); ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->dev_rx_fifo_size = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->dev_rx_fifo_size; ++} ++ ++int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if, ++ int32_t val) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) { ++ DWC_WARN("Wrong value for dev_nperio_tx_fifo\n"); ++ DWC_WARN("dev_nperio_tx_fifo must be 16-32768\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->dev_nperio_tx_fifo_size)) { ++ DWC_ERROR ++ ("%d invalid for dev_nperio_tx_fifo_size. Check HW configuration.\n", ++ val); ++ } ++ val = ++ (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> ++ 16); ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->dev_nperio_tx_fifo_size = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->dev_nperio_tx_fifo_size; ++} ++ ++int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if, ++ int32_t val) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) { ++ DWC_WARN("Wrong value for host_rx_fifo_size\n"); ++ DWC_WARN("host_rx_fifo_size must be 16-32768\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->host_rx_fifo_size)) { ++ DWC_ERROR ++ ("%d invalid for host_rx_fifo_size. Check HW configuration.\n", ++ val); ++ } ++ val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz); ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->host_rx_fifo_size = val; ++ return retval; ++ ++} ++ ++int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->host_rx_fifo_size; ++} ++ ++int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if, ++ int32_t val) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) { ++ DWC_WARN("Wrong value for host_nperio_tx_fifo_size\n"); ++ DWC_WARN("host_nperio_tx_fifo_size must be 16-32768\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->host_nperio_tx_fifo_size)) { ++ DWC_ERROR ++ ("%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n", ++ val); ++ } ++ val = ++ (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> ++ 16); ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->host_nperio_tx_fifo_size = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->host_nperio_tx_fifo_size; ++} ++ ++int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if, ++ int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) { ++ DWC_WARN("Wrong value for host_perio_tx_fifo_size\n"); ++ DWC_WARN("host_perio_tx_fifo_size must be 16-32768\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val > ((core_if->hptxfsiz.d32) >> 16)) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->host_perio_tx_fifo_size)) { ++ DWC_ERROR ++ ("%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n", ++ val); ++ } ++ val = (core_if->hptxfsiz.d32) >> 16; ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->host_perio_tx_fifo_size = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->host_perio_tx_fifo_size; ++} ++ ++int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if, ++ int32_t val) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 2047, 524288)) { ++ DWC_WARN("Wrong value for max_transfer_size\n"); ++ DWC_WARN("max_transfer_size must be 2047-524288\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val >= (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->max_transfer_size)) { ++ DWC_ERROR ++ ("%d invalid for max_transfer_size. Check HW configuration.\n", ++ val); ++ } ++ val = ++ ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 11)) - ++ 1); ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->max_transfer_size = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->max_transfer_size; ++} ++ ++int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 15, 511)) { ++ DWC_WARN("Wrong value for max_packet_count\n"); ++ DWC_WARN("max_packet_count must be 15-511\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val > (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->max_packet_count)) { ++ DWC_ERROR ++ ("%d invalid for max_packet_count. Check HW configuration.\n", ++ val); ++ } ++ val = ++ ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1); ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->max_packet_count = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->max_packet_count; ++} ++ ++int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 1, 16)) { ++ DWC_WARN("Wrong value for host_channels\n"); ++ DWC_WARN("host_channels must be 1-16\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val > (core_if->hwcfg2.b.num_host_chan + 1)) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->host_channels)) { ++ DWC_ERROR ++ ("%d invalid for host_channels. Check HW configurations.\n", ++ val); ++ } ++ val = (core_if->hwcfg2.b.num_host_chan + 1); ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->host_channels = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->host_channels; ++} ++ ++int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 1, 15)) { ++ DWC_WARN("Wrong value for dev_endpoints\n"); ++ DWC_WARN("dev_endpoints must be 1-15\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val > (core_if->hwcfg2.b.num_dev_ep)) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->dev_endpoints)) { ++ DWC_ERROR ++ ("%d invalid for dev_endpoints. Check HW configurations.\n", ++ val); ++ } ++ val = core_if->hwcfg2.b.num_dev_ep; ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->dev_endpoints = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->dev_endpoints; ++} ++ ++int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ int valid = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 0, 2)) { ++ DWC_WARN("Wrong value for phy_type\n"); ++ DWC_WARN("phy_type must be 0,1 or 2\n"); ++ return -DWC_E_INVALID; ++ } ++#ifndef NO_FS_PHY_HW_CHECKS ++ if ((val == DWC_PHY_TYPE_PARAM_UTMI) && ++ ((core_if->hwcfg2.b.hs_phy_type == 1) || ++ (core_if->hwcfg2.b.hs_phy_type == 3))) { ++ valid = 1; ++ } else if ((val == DWC_PHY_TYPE_PARAM_ULPI) && ++ ((core_if->hwcfg2.b.hs_phy_type == 2) || ++ (core_if->hwcfg2.b.hs_phy_type == 3))) { ++ valid = 1; ++ } else if ((val == DWC_PHY_TYPE_PARAM_FS) && ++ (core_if->hwcfg2.b.fs_phy_type == 1)) { ++ valid = 1; ++ } ++ if (!valid) { ++ if (dwc_otg_param_initialized(core_if->core_params->phy_type)) { ++ DWC_ERROR ++ ("%d invalid for phy_type. Check HW configurations.\n", ++ val); ++ } ++ if (core_if->hwcfg2.b.hs_phy_type) { ++ if ((core_if->hwcfg2.b.hs_phy_type == 3) || ++ (core_if->hwcfg2.b.hs_phy_type == 1)) { ++ val = DWC_PHY_TYPE_PARAM_UTMI; ++ } else { ++ val = DWC_PHY_TYPE_PARAM_ULPI; ++ } ++ } ++ retval = -DWC_E_INVALID; ++ } ++#endif ++ core_if->core_params->phy_type = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->phy_type; ++} ++ ++int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong value for speed parameter\n"); ++ DWC_WARN("max_speed parameter must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ if ((val == 0) ++ && dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS) { ++ if (dwc_otg_param_initialized(core_if->core_params->speed)) { ++ DWC_ERROR ++ ("%d invalid for speed paremter. Check HW configuration.\n", ++ val); ++ } ++ val = ++ (dwc_otg_get_param_phy_type(core_if) == ++ DWC_PHY_TYPE_PARAM_FS ? 1 : 0); ++ retval = -DWC_E_INVALID; ++ } ++ core_if->core_params->speed = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->speed; ++} ++ ++int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if, ++ int32_t val) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN ++ ("Wrong value for host_ls_low_power_phy_clk parameter\n"); ++ DWC_WARN("host_ls_low_power_phy_clk must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if ((val == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ) ++ && (dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS)) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->host_ls_low_power_phy_clk)) { ++ DWC_ERROR ++ ("%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n", ++ val); ++ } ++ val = ++ (dwc_otg_get_param_phy_type(core_if) == ++ DWC_PHY_TYPE_PARAM_FS) ? ++ DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ : ++ DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ; ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->host_ls_low_power_phy_clk = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->host_ls_low_power_phy_clk; ++} ++ ++int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong value for phy_ulpi_ddr\n"); ++ DWC_WARN("phy_upli_ddr must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->phy_ulpi_ddr = val; ++ return 0; ++} ++ ++int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->phy_ulpi_ddr; ++} ++ ++int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if, ++ int32_t val) ++{ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong valaue for phy_ulpi_ext_vbus\n"); ++ DWC_WARN("phy_ulpi_ext_vbus must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->phy_ulpi_ext_vbus = val; ++ return 0; ++} ++ ++int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->phy_ulpi_ext_vbus; ++} ++ ++int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ if (DWC_OTG_PARAM_TEST(val, 8, 8) && DWC_OTG_PARAM_TEST(val, 16, 16)) { ++ DWC_WARN("Wrong valaue for phy_utmi_width\n"); ++ DWC_WARN("phy_utmi_width must be 8 or 16\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->phy_utmi_width = val; ++ return 0; ++} ++ ++int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->phy_utmi_width; ++} ++ ++int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong valaue for ulpi_fs_ls\n"); ++ DWC_WARN("ulpi_fs_ls must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->ulpi_fs_ls = val; ++ return 0; ++} ++ ++int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->ulpi_fs_ls; ++} ++ ++int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong valaue for ts_dline\n"); ++ DWC_WARN("ts_dline must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->ts_dline = val; ++ return 0; ++} ++ ++int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->ts_dline; ++} ++ ++int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong valaue for i2c_enable\n"); ++ DWC_WARN("i2c_enable must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++#ifndef NO_FS_PHY_HW_CHECK ++ if (val == 1 && core_if->hwcfg3.b.i2c == 0) { ++ if (dwc_otg_param_initialized(core_if->core_params->i2c_enable)) { ++ DWC_ERROR ++ ("%d invalid for i2c_enable. Check HW configuration.\n", ++ val); ++ } ++ val = 0; ++ retval = -DWC_E_INVALID; ++ } ++#endif ++ ++ core_if->core_params->i2c_enable = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->i2c_enable; ++} ++ ++int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if, ++ int32_t val, int fifo_num) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 4, 768)) { ++ DWC_WARN("Wrong value for dev_perio_tx_fifo_size\n"); ++ DWC_WARN("dev_perio_tx_fifo_size must be 4-768\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val > ++ (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]))) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->dev_perio_tx_fifo_size[fifo_num])) { ++ DWC_ERROR ++ ("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", ++ val, fifo_num); ++ } ++ val = (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num])); ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->dev_perio_tx_fifo_size[fifo_num] = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if, ++ int fifo_num) ++{ ++ return core_if->core_params->dev_perio_tx_fifo_size[fifo_num]; ++} ++ ++int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if, ++ int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong valaue for en_multiple_tx_fifo,\n"); ++ DWC_WARN("en_multiple_tx_fifo must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val == 1 && core_if->hwcfg4.b.ded_fifo_en == 0) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->en_multiple_tx_fifo)) { ++ DWC_ERROR ++ ("%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n", ++ val); ++ } ++ val = 0; ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->en_multiple_tx_fifo = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->en_multiple_tx_fifo; ++} ++ ++int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val, ++ int fifo_num) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 4, 768)) { ++ DWC_WARN("Wrong value for dev_tx_fifo_size\n"); ++ DWC_WARN("dev_tx_fifo_size must be 4-768\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val > ++ (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]))) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->dev_tx_fifo_size[fifo_num])) { ++ DWC_ERROR ++ ("`%d' invalid for parameter `dev_tx_fifo_size_%d'. Check HW configuration.\n", ++ val, fifo_num); ++ } ++ val = (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num])); ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->dev_tx_fifo_size[fifo_num] = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, ++ int fifo_num) ++{ ++ return core_if->core_params->dev_tx_fifo_size[fifo_num]; ++} ++ ++int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 0, 7)) { ++ DWC_WARN("Wrong value for thr_ctl\n"); ++ DWC_WARN("thr_ctl must be 0-7\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if ((val != 0) && ++ (!dwc_otg_get_param_dma_enable(core_if) || ++ !core_if->hwcfg4.b.ded_fifo_en)) { ++ if (dwc_otg_param_initialized(core_if->core_params->thr_ctl)) { ++ DWC_ERROR ++ ("%d invalid for parameter thr_ctl. Check HW configuration.\n", ++ val); ++ } ++ val = 0; ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->thr_ctl = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_thr_ctl(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->thr_ctl; ++} ++ ++int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong value for lpm_enable\n"); ++ DWC_WARN("lpm_enable must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val && !core_if->hwcfg3.b.otg_lpm_en) { ++ if (dwc_otg_param_initialized(core_if->core_params->lpm_enable)) { ++ DWC_ERROR ++ ("%d invalid for parameter lpm_enable. Check HW configuration.\n", ++ val); ++ } ++ val = 0; ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->lpm_enable = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->lpm_enable; ++} ++ ++int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ if (DWC_OTG_PARAM_TEST(val, 8, 128)) { ++ DWC_WARN("Wrong valaue for tx_thr_length\n"); ++ DWC_WARN("tx_thr_length must be 8 - 128\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->tx_thr_length = val; ++ return 0; ++} ++ ++int32_t dwc_otg_get_param_tx_thr_length(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->tx_thr_length; ++} ++ ++int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ if (DWC_OTG_PARAM_TEST(val, 8, 128)) { ++ DWC_WARN("Wrong valaue for rx_thr_length\n"); ++ DWC_WARN("rx_thr_length must be 8 - 128\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->rx_thr_length = val; ++ return 0; ++} ++ ++int32_t dwc_otg_get_param_rx_thr_length(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->rx_thr_length; ++} ++ ++int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ if (DWC_OTG_PARAM_TEST(val, 1, 1) && ++ DWC_OTG_PARAM_TEST(val, 4, 4) && ++ DWC_OTG_PARAM_TEST(val, 8, 8) && ++ DWC_OTG_PARAM_TEST(val, 16, 16) && ++ DWC_OTG_PARAM_TEST(val, 32, 32) && ++ DWC_OTG_PARAM_TEST(val, 64, 64) && ++ DWC_OTG_PARAM_TEST(val, 128, 128) && ++ DWC_OTG_PARAM_TEST(val, 256, 256)) { ++ DWC_WARN("`%d' invalid for parameter `dma_burst_size'\n", val); ++ return -DWC_E_INVALID; ++ } ++ core_if->core_params->dma_burst_size = val; ++ return 0; ++} ++ ++int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->dma_burst_size; ++} ++ ++int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("`%d' invalid for parameter `pti_enable'\n", val); ++ return -DWC_E_INVALID; ++ } ++ if (val && (core_if->snpsid < OTG_CORE_REV_2_72a)) { ++ if (dwc_otg_param_initialized(core_if->core_params->pti_enable)) { ++ DWC_ERROR ++ ("%d invalid for parameter pti_enable. Check HW configuration.\n", ++ val); ++ } ++ retval = -DWC_E_INVALID; ++ val = 0; ++ } ++ core_if->core_params->pti_enable = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->pti_enable; ++} ++ ++int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("`%d' invalid for parameter `mpi_enable'\n", val); ++ return -DWC_E_INVALID; ++ } ++ if (val && (core_if->hwcfg2.b.multi_proc_int == 0)) { ++ if (dwc_otg_param_initialized(core_if->core_params->mpi_enable)) { ++ DWC_ERROR ++ ("%d invalid for parameter mpi_enable. Check HW configuration.\n", ++ val); ++ } ++ retval = -DWC_E_INVALID; ++ val = 0; ++ } ++ core_if->core_params->mpi_enable = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->mpi_enable; ++} ++ ++int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("`%d' invalid for parameter `adp_enable'\n", val); ++ return -DWC_E_INVALID; ++ } ++ if (val && (core_if->hwcfg3.b.adp_supp == 0)) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->adp_supp_enable)) { ++ DWC_ERROR ++ ("%d invalid for parameter adp_enable. Check HW configuration.\n", ++ val); ++ } ++ retval = -DWC_E_INVALID; ++ val = 0; ++ } ++ core_if->core_params->adp_supp_enable = val; ++ /*Set OTG version 2.0 in case of enabling ADP*/ ++ if (val) ++ dwc_otg_set_param_otg_ver(core_if, 1); ++ ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->adp_supp_enable; ++} ++ ++int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("`%d' invalid for parameter `ic_usb_cap'\n", val); ++ DWC_WARN("ic_usb_cap must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val && (core_if->hwcfg2.b.otg_enable_ic_usb == 0)) { ++ if (dwc_otg_param_initialized(core_if->core_params->ic_usb_cap)) { ++ DWC_ERROR ++ ("%d invalid for parameter ic_usb_cap. Check HW configuration.\n", ++ val); ++ } ++ retval = -DWC_E_INVALID; ++ val = 0; ++ } ++ core_if->core_params->ic_usb_cap = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->ic_usb_cap; ++} ++ ++int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ int valid = 1; ++ ++ if (DWC_OTG_PARAM_TEST(val, 0, 3)) { ++ DWC_WARN("`%d' invalid for parameter `ahb_thr_ratio'\n", val); ++ DWC_WARN("ahb_thr_ratio must be 0 - 3\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val ++ && (core_if->snpsid < OTG_CORE_REV_2_81a ++ || !dwc_otg_get_param_thr_ctl(core_if))) { ++ valid = 0; ++ } else if (val ++ && ((dwc_otg_get_param_tx_thr_length(core_if) / (1 << val)) < ++ 4)) { ++ valid = 0; ++ } ++ if (valid == 0) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->ahb_thr_ratio)) { ++ DWC_ERROR ++ ("%d invalid for parameter ahb_thr_ratio. Check HW configuration.\n", ++ val); ++ } ++ retval = -DWC_E_INVALID; ++ val = 0; ++ } ++ ++ core_if->core_params->ahb_thr_ratio = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->ahb_thr_ratio; ++} ++ ++int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ int valid = 1; ++ hwcfg4_data_t hwcfg4 = {.d32 = 0 }; ++ hwcfg4.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4); ++ ++ if (DWC_OTG_PARAM_TEST(val, 0, 3)) { ++ DWC_WARN("`%d' invalid for parameter `power_down'\n", val); ++ DWC_WARN("power_down must be 0 - 2\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if ((val == 2) && (core_if->snpsid < OTG_CORE_REV_2_91a)) { ++ valid = 0; ++ } ++ if ((val == 3) ++ && ((core_if->snpsid < OTG_CORE_REV_3_00a) ++ || (hwcfg4.b.xhiber == 0))) { ++ valid = 0; ++ } ++ if (valid == 0) { ++ if (dwc_otg_param_initialized(core_if->core_params->power_down)) { ++ DWC_ERROR ++ ("%d invalid for parameter power_down. Check HW configuration.\n", ++ val); ++ } ++ retval = -DWC_E_INVALID; ++ val = 0; ++ } ++ core_if->core_params->power_down = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->power_down; ++} ++ ++int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ int valid = 1; ++ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("`%d' invalid for parameter `reload_ctl'\n", val); ++ DWC_WARN("reload_ctl must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_92a)) { ++ valid = 0; ++ } ++ if (valid == 0) { ++ if (dwc_otg_param_initialized(core_if->core_params->reload_ctl)) { ++ DWC_ERROR("%d invalid for parameter reload_ctl." ++ "Check HW configuration.\n", val); ++ } ++ retval = -DWC_E_INVALID; ++ val = 0; ++ } ++ core_if->core_params->reload_ctl = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->reload_ctl; ++} ++ ++int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ int valid = 1; ++ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("`%d' invalid for parameter `dev_out_nak'\n", val); ++ DWC_WARN("dev_out_nak must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_93a) || ++ !(core_if->core_params->dma_desc_enable))) { ++ valid = 0; ++ } ++ if (valid == 0) { ++ if (dwc_otg_param_initialized(core_if->core_params->dev_out_nak)) { ++ DWC_ERROR("%d invalid for parameter dev_out_nak." ++ "Check HW configuration.\n", val); ++ } ++ retval = -DWC_E_INVALID; ++ val = 0; ++ } ++ core_if->core_params->dev_out_nak = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->dev_out_nak; ++} ++ ++int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ int valid = 1; ++ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("`%d' invalid for parameter `cont_on_bna'\n", val); ++ DWC_WARN("cont_on_bna must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_94a) || ++ !(core_if->core_params->dma_desc_enable))) { ++ valid = 0; ++ } ++ if (valid == 0) { ++ if (dwc_otg_param_initialized(core_if->core_params->cont_on_bna)) { ++ DWC_ERROR("%d invalid for parameter cont_on_bna." ++ "Check HW configuration.\n", val); ++ } ++ retval = -DWC_E_INVALID; ++ val = 0; ++ } ++ core_if->core_params->cont_on_bna = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->cont_on_bna; ++} ++ ++int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ int valid = 1; ++ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("`%d' invalid for parameter `ahb_single'\n", val); ++ DWC_WARN("ahb_single must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_94a)) { ++ valid = 0; ++ } ++ if (valid == 0) { ++ if (dwc_otg_param_initialized(core_if->core_params->ahb_single)) { ++ DWC_ERROR("%d invalid for parameter ahb_single." ++ "Check HW configuration.\n", val); ++ } ++ retval = -DWC_E_INVALID; ++ val = 0; ++ } ++ core_if->core_params->ahb_single = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->ahb_single; ++} ++ ++int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("`%d' invalid for parameter `otg_ver'\n", val); ++ DWC_WARN ++ ("otg_ver must be 0(for OTG 1.3 support) or 1(for OTG 2.0 support)\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->otg_ver = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->otg_ver; ++} ++ ++uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if) ++{ ++ gotgctl_data_t otgctl; ++ otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl); ++ return otgctl.b.hstnegscs; ++} ++ ++uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if) ++{ ++ gotgctl_data_t otgctl; ++ otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl); ++ return otgctl.b.sesreqscs; ++} ++ ++void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ if(core_if->otg_ver == 0) { ++ gotgctl_data_t otgctl; ++ otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl); ++ otgctl.b.hnpreq = val; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, otgctl.d32); ++ } else { ++ core_if->otg_sts = val; ++ } ++} ++ ++uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->snpsid; ++} ++ ++uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if) ++{ ++ gintsts_data_t gintsts; ++ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts); ++ return gintsts.b.curmode; ++} ++ ++uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if) ++{ ++ gusbcfg_data_t usbcfg; ++ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); ++ return usbcfg.b.hnpcap; ++} ++ ++void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ gusbcfg_data_t usbcfg; ++ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); ++ usbcfg.b.hnpcap = val; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32); ++} ++ ++uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if) ++{ ++ gusbcfg_data_t usbcfg; ++ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); ++ return usbcfg.b.srpcap; ++} ++ ++void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ gusbcfg_data_t usbcfg; ++ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); ++ usbcfg.b.srpcap = val; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32); ++} ++ ++uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if) ++{ ++ dcfg_data_t dcfg; ++ /* originally: dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); */ ++ ++ dcfg.d32 = -1; //GRAYG ++ DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)\n", __func__, core_if); ++ if (NULL == core_if) ++ DWC_ERROR("reg request with NULL core_if\n"); ++ DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)->dev_if(%p)\n", __func__, ++ core_if, core_if->dev_if); ++ if (NULL == core_if->dev_if) ++ DWC_ERROR("reg request with NULL dev_if\n"); ++ DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)->dev_if(%p)->" ++ "dev_global_regs(%p)\n", __func__, ++ core_if, core_if->dev_if, ++ core_if->dev_if->dev_global_regs); ++ if (NULL == core_if->dev_if->dev_global_regs) ++ DWC_ERROR("reg request with NULL dev_global_regs\n"); ++ else { ++ DWC_DEBUGPL(DBG_CILV, "%s - &core_if(%p)->dev_if(%p)->" ++ "dev_global_regs(%p)->dcfg = %p\n", __func__, ++ core_if, core_if->dev_if, ++ core_if->dev_if->dev_global_regs, ++ &core_if->dev_if->dev_global_regs->dcfg); ++ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); ++ } ++ return dcfg.b.devspd; ++} ++ ++void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ dcfg_data_t dcfg; ++ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); ++ dcfg.b.devspd = val; ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32); ++} ++ ++uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if) ++{ ++ hprt0_data_t hprt0; ++ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0); ++ return hprt0.b.prtconnsts; ++} ++ ++uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if) ++{ ++ dsts_data_t dsts; ++ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); ++ return dsts.b.enumspd; ++} ++ ++uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if) ++{ ++ hprt0_data_t hprt0; ++ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0); ++ return hprt0.b.prtpwr; ++ ++} ++ ++uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->hibernation_suspend; ++} ++ ++void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ hprt0_data_t hprt0; ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtpwr = val; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++} ++ ++uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if) ++{ ++ hprt0_data_t hprt0; ++ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0); ++ return hprt0.b.prtsusp; ++ ++} ++ ++void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ hprt0_data_t hprt0; ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtsusp = val; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++} ++ ++uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if) ++{ ++ hfir_data_t hfir; ++ hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir); ++ return hfir.b.frint; ++ ++} ++ ++void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ hfir_data_t hfir; ++ uint32_t fram_int; ++ fram_int = calc_frame_interval(core_if); ++ hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir); ++ if (!core_if->core_params->reload_ctl) { ++ DWC_WARN("\nCannot reload HFIR register.HFIR.HFIRRldCtrl bit is" ++ "not set to 1.\nShould load driver with reload_ctl=1" ++ " module parameter\n"); ++ return; ++ } ++ switch (fram_int) { ++ case 3750: ++ if ((val < 3350) || (val > 4150)) { ++ DWC_WARN("HFIR interval for HS core and 30 MHz" ++ "clock freq should be from 3350 to 4150\n"); ++ return; ++ } ++ break; ++ case 30000: ++ if ((val < 26820) || (val > 33180)) { ++ DWC_WARN("HFIR interval for FS/LS core and 30 MHz" ++ "clock freq should be from 26820 to 33180\n"); ++ return; ++ } ++ break; ++ case 6000: ++ if ((val < 5360) || (val > 6640)) { ++ DWC_WARN("HFIR interval for HS core and 48 MHz" ++ "clock freq should be from 5360 to 6640\n"); ++ return; ++ } ++ break; ++ case 48000: ++ if ((val < 42912) || (val > 53088)) { ++ DWC_WARN("HFIR interval for FS/LS core and 48 MHz" ++ "clock freq should be from 42912 to 53088\n"); ++ return; ++ } ++ break; ++ case 7500: ++ if ((val < 6700) || (val > 8300)) { ++ DWC_WARN("HFIR interval for HS core and 60 MHz" ++ "clock freq should be from 6700 to 8300\n"); ++ return; ++ } ++ break; ++ case 60000: ++ if ((val < 53640) || (val > 65536)) { ++ DWC_WARN("HFIR interval for FS/LS core and 60 MHz" ++ "clock freq should be from 53640 to 65536\n"); ++ return; ++ } ++ break; ++ default: ++ DWC_WARN("Unknown frame interval\n"); ++ return; ++ break; ++ ++ } ++ hfir.b.frint = val; ++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hfir.d32); ++} ++ ++uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if) ++{ ++ hcfg_data_t hcfg; ++ hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg); ++ return hcfg.b.modechtimen; ++ ++} ++ ++void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ hcfg_data_t hcfg; ++ hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg); ++ hcfg.b.modechtimen = val; ++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32); ++} ++ ++void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ hprt0_data_t hprt0; ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtres = val; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++} ++ ++uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if) ++{ ++ dctl_data_t dctl; ++ dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl); ++ return dctl.b.rmtwkupsig; ++} ++ ++uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if) ++{ ++ glpmcfg_data_t lpmcfg; ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++ ++ DWC_ASSERT(! ++ ((core_if->lx_state == DWC_OTG_L1) ^ lpmcfg.b.prt_sleep_sts), ++ "lx_state = %d, lmpcfg.prt_sleep_sts = %d\n", ++ core_if->lx_state, lpmcfg.b.prt_sleep_sts); ++ ++ return lpmcfg.b.prt_sleep_sts; ++} ++ ++uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if) ++{ ++ glpmcfg_data_t lpmcfg; ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++ return lpmcfg.b.rem_wkup_en; ++} ++ ++uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if) ++{ ++ glpmcfg_data_t lpmcfg; ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++ return lpmcfg.b.appl_resp; ++} ++ ++void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ glpmcfg_data_t lpmcfg; ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++ lpmcfg.b.appl_resp = val; ++ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32); ++} ++ ++uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if) ++{ ++ glpmcfg_data_t lpmcfg; ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++ return lpmcfg.b.hsic_connect; ++} ++ ++void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ glpmcfg_data_t lpmcfg; ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++ lpmcfg.b.hsic_connect = val; ++ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32); ++} ++ ++uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if) ++{ ++ glpmcfg_data_t lpmcfg; ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++ return lpmcfg.b.inv_sel_hsic; ++ ++} ++ ++void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ glpmcfg_data_t lpmcfg; ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++ lpmcfg.b.inv_sel_hsic = val; ++ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32); ++} ++ ++uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if) ++{ ++ return DWC_READ_REG32(&core_if->core_global_regs->gotgctl); ++} ++ ++void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, val); ++} ++ ++uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if) ++{ ++ return DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); ++} ++ ++void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, val); ++} ++ ++uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if) ++{ ++ return DWC_READ_REG32(&core_if->core_global_regs->grxfsiz); ++} ++ ++void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, val); ++} ++ ++uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if) ++{ ++ return DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz); ++} ++ ++void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz, val); ++} ++ ++uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if) ++{ ++ return DWC_READ_REG32(&core_if->core_global_regs->gpvndctl); ++} ++ ++void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gpvndctl, val); ++} ++ ++uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if) ++{ ++ return DWC_READ_REG32(&core_if->core_global_regs->ggpio); ++} ++ ++void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, val); ++} ++ ++uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if) ++{ ++ return DWC_READ_REG32(core_if->host_if->hprt0); ++ ++} ++ ++void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ DWC_WRITE_REG32(core_if->host_if->hprt0, val); ++} ++ ++uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if) ++{ ++ return DWC_READ_REG32(&core_if->core_global_regs->guid); ++} ++ ++void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ DWC_WRITE_REG32(&core_if->core_global_regs->guid, val); ++} ++ ++uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if) ++{ ++ return DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz); ++} ++ ++uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if) ++{ ++ return ((core_if->otg_ver == 1) ? (uint16_t)0x0200 : (uint16_t)0x0103); ++} ++ ++/** ++ * Start the SRP timer to detect when the SRP does not complete within ++ * 6 seconds. ++ * ++ * @param core_if the pointer to core_if strucure. ++ */ ++void dwc_otg_pcd_start_srp_timer(dwc_otg_core_if_t * core_if) ++{ ++ core_if->srp_timer_started = 1; ++ DWC_TIMER_SCHEDULE(core_if->srp_timer, 6000 /* 6 secs */ ); ++} ++ ++void dwc_otg_initiate_srp(dwc_otg_core_if_t * core_if) ++{ ++ uint32_t *addr = (uint32_t *) & (core_if->core_global_regs->gotgctl); ++ gotgctl_data_t mem; ++ gotgctl_data_t val; ++ ++ val.d32 = DWC_READ_REG32(addr); ++ if (val.b.sesreq) { ++ DWC_ERROR("Session Request Already active!\n"); ++ return; ++ } ++ ++ DWC_INFO("Session Request Initated\n"); //NOTICE ++ mem.d32 = DWC_READ_REG32(addr); ++ mem.b.sesreq = 1; ++ DWC_WRITE_REG32(addr, mem.d32); ++ ++ /* Start the SRP timer */ ++ dwc_otg_pcd_start_srp_timer(core_if); ++ return; ++} +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_cil.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cil.h +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_cil.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cil.h 2015-11-29 09:42:39.919098694 +0100 +@@ -0,0 +1,1464 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $ ++ * $Revision: #123 $ ++ * $Date: 2012/08/10 $ ++ * $Change: 2047372 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++#if !defined(__DWC_CIL_H__) ++#define __DWC_CIL_H__ ++ ++#include "dwc_list.h" ++#include "dwc_otg_dbg.h" ++#include "dwc_otg_regs.h" ++ ++#include "dwc_otg_core_if.h" ++#include "dwc_otg_adp.h" ++ ++/** ++ * @file ++ * This file contains the interface to the Core Interface Layer. ++ */ ++ ++#ifdef DWC_UTE_CFI ++ ++#define MAX_DMA_DESCS_PER_EP 256 ++ ++/** ++ * Enumeration for the data buffer mode ++ */ ++typedef enum _data_buffer_mode { ++ BM_STANDARD = 0, /* data buffer is in normal mode */ ++ BM_SG = 1, /* data buffer uses the scatter/gather mode */ ++ BM_CONCAT = 2, /* data buffer uses the concatenation mode */ ++ BM_CIRCULAR = 3, /* data buffer uses the circular DMA mode */ ++ BM_ALIGN = 4 /* data buffer is in buffer alignment mode */ ++} data_buffer_mode_e; ++#endif //DWC_UTE_CFI ++ ++/** Macros defined for DWC OTG HW Release version */ ++ ++#define OTG_CORE_REV_2_60a 0x4F54260A ++#define OTG_CORE_REV_2_71a 0x4F54271A ++#define OTG_CORE_REV_2_72a 0x4F54272A ++#define OTG_CORE_REV_2_80a 0x4F54280A ++#define OTG_CORE_REV_2_81a 0x4F54281A ++#define OTG_CORE_REV_2_90a 0x4F54290A ++#define OTG_CORE_REV_2_91a 0x4F54291A ++#define OTG_CORE_REV_2_92a 0x4F54292A ++#define OTG_CORE_REV_2_93a 0x4F54293A ++#define OTG_CORE_REV_2_94a 0x4F54294A ++#define OTG_CORE_REV_3_00a 0x4F54300A ++ ++/** ++ * Information for each ISOC packet. ++ */ ++typedef struct iso_pkt_info { ++ uint32_t offset; ++ uint32_t length; ++ int32_t status; ++} iso_pkt_info_t; ++ ++/** ++ * The dwc_ep structure represents the state of a single ++ * endpoint when acting in device mode. It contains the data items ++ * needed for an endpoint to be activated and transfer packets. ++ */ ++typedef struct dwc_ep { ++ /** EP number used for register address lookup */ ++ uint8_t num; ++ /** EP direction 0 = OUT */ ++ unsigned is_in:1; ++ /** EP active. */ ++ unsigned active:1; ++ ++ /** ++ * Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic ++ * Tx FIFO. If dedicated Tx FIFOs are enabled Tx FIFO # FOR IN EPs*/ ++ unsigned tx_fifo_num:4; ++ /** EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR */ ++ unsigned type:2; ++#define DWC_OTG_EP_TYPE_CONTROL 0 ++#define DWC_OTG_EP_TYPE_ISOC 1 ++#define DWC_OTG_EP_TYPE_BULK 2 ++#define DWC_OTG_EP_TYPE_INTR 3 ++ ++ /** DATA start PID for INTR and BULK EP */ ++ unsigned data_pid_start:1; ++ /** Frame (even/odd) for ISOC EP */ ++ unsigned even_odd_frame:1; ++ /** Max Packet bytes */ ++ unsigned maxpacket:11; ++ ++ /** Max Transfer size */ ++ uint32_t maxxfer; ++ ++ /** @name Transfer state */ ++ /** @{ */ ++ ++ /** ++ * Pointer to the beginning of the transfer buffer -- do not modify ++ * during transfer. ++ */ ++ ++ dwc_dma_t dma_addr; ++ ++ dwc_dma_t dma_desc_addr; ++ dwc_otg_dev_dma_desc_t *desc_addr; ++ ++ uint8_t *start_xfer_buff; ++ /** pointer to the transfer buffer */ ++ uint8_t *xfer_buff; ++ /** Number of bytes to transfer */ ++ unsigned xfer_len:19; ++ /** Number of bytes transferred. */ ++ unsigned xfer_count:19; ++ /** Sent ZLP */ ++ unsigned sent_zlp:1; ++ /** Total len for control transfer */ ++ unsigned total_len:19; ++ ++ /** stall clear flag */ ++ unsigned stall_clear_flag:1; ++ ++ /** SETUP pkt cnt rollover flag for EP0 out*/ ++ unsigned stp_rollover; ++ ++#ifdef DWC_UTE_CFI ++ /* The buffer mode */ ++ data_buffer_mode_e buff_mode; ++ ++ /* The chain of DMA descriptors. ++ * MAX_DMA_DESCS_PER_EP will be allocated for each active EP. ++ */ ++ dwc_otg_dma_desc_t *descs; ++ ++ /* The DMA address of the descriptors chain start */ ++ dma_addr_t descs_dma_addr; ++ /** This variable stores the length of the last enqueued request */ ++ uint32_t cfi_req_len; ++#endif //DWC_UTE_CFI ++ ++/** Max DMA Descriptor count for any EP */ ++#define MAX_DMA_DESC_CNT 256 ++ /** Allocated DMA Desc count */ ++ uint32_t desc_cnt; ++ ++ /** bInterval */ ++ uint32_t bInterval; ++ /** Next frame num to setup next ISOC transfer */ ++ uint32_t frame_num; ++ /** Indicates SOF number overrun in DSTS */ ++ uint8_t frm_overrun; ++ ++#ifdef DWC_UTE_PER_IO ++ /** Next frame num for which will be setup DMA Desc */ ++ uint32_t xiso_frame_num; ++ /** bInterval */ ++ uint32_t xiso_bInterval; ++ /** Count of currently active transfers - shall be either 0 or 1 */ ++ int xiso_active_xfers; ++ int xiso_queued_xfers; ++#endif ++#ifdef DWC_EN_ISOC ++ /** ++ * Variables specific for ISOC EPs ++ * ++ */ ++ /** DMA addresses of ISOC buffers */ ++ dwc_dma_t dma_addr0; ++ dwc_dma_t dma_addr1; ++ ++ dwc_dma_t iso_dma_desc_addr; ++ dwc_otg_dev_dma_desc_t *iso_desc_addr; ++ ++ /** pointer to the transfer buffers */ ++ uint8_t *xfer_buff0; ++ uint8_t *xfer_buff1; ++ ++ /** number of ISOC Buffer is processing */ ++ uint32_t proc_buf_num; ++ /** Interval of ISOC Buffer processing */ ++ uint32_t buf_proc_intrvl; ++ /** Data size for regular frame */ ++ uint32_t data_per_frame; ++ ++ /* todo - pattern data support is to be implemented in the future */ ++ /** Data size for pattern frame */ ++ uint32_t data_pattern_frame; ++ /** Frame number of pattern data */ ++ uint32_t sync_frame; ++ ++ /** bInterval */ ++ uint32_t bInterval; ++ /** ISO Packet number per frame */ ++ uint32_t pkt_per_frm; ++ /** Next frame num for which will be setup DMA Desc */ ++ uint32_t next_frame; ++ /** Number of packets per buffer processing */ ++ uint32_t pkt_cnt; ++ /** Info for all isoc packets */ ++ iso_pkt_info_t *pkt_info; ++ /** current pkt number */ ++ uint32_t cur_pkt; ++ /** current pkt number */ ++ uint8_t *cur_pkt_addr; ++ /** current pkt number */ ++ uint32_t cur_pkt_dma_addr; ++#endif /* DWC_EN_ISOC */ ++ ++/** @} */ ++} dwc_ep_t; ++ ++/* ++ * Reasons for halting a host channel. ++ */ ++typedef enum dwc_otg_halt_status { ++ DWC_OTG_HC_XFER_NO_HALT_STATUS, ++ DWC_OTG_HC_XFER_COMPLETE, ++ DWC_OTG_HC_XFER_URB_COMPLETE, ++ DWC_OTG_HC_XFER_ACK, ++ DWC_OTG_HC_XFER_NAK, ++ DWC_OTG_HC_XFER_NYET, ++ DWC_OTG_HC_XFER_STALL, ++ DWC_OTG_HC_XFER_XACT_ERR, ++ DWC_OTG_HC_XFER_FRAME_OVERRUN, ++ DWC_OTG_HC_XFER_BABBLE_ERR, ++ DWC_OTG_HC_XFER_DATA_TOGGLE_ERR, ++ DWC_OTG_HC_XFER_AHB_ERR, ++ DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE, ++ DWC_OTG_HC_XFER_URB_DEQUEUE ++} dwc_otg_halt_status_e; ++ ++/** ++ * Host channel descriptor. This structure represents the state of a single ++ * host channel when acting in host mode. It contains the data items needed to ++ * transfer packets to an endpoint via a host channel. ++ */ ++typedef struct dwc_hc { ++ /** Host channel number used for register address lookup */ ++ uint8_t hc_num; ++ ++ /** Device to access */ ++ unsigned dev_addr:7; ++ ++ /** EP to access */ ++ unsigned ep_num:4; ++ ++ /** EP direction. 0: OUT, 1: IN */ ++ unsigned ep_is_in:1; ++ ++ /** ++ * EP speed. ++ * One of the following values: ++ * - DWC_OTG_EP_SPEED_LOW ++ * - DWC_OTG_EP_SPEED_FULL ++ * - DWC_OTG_EP_SPEED_HIGH ++ */ ++ unsigned speed:2; ++#define DWC_OTG_EP_SPEED_LOW 0 ++#define DWC_OTG_EP_SPEED_FULL 1 ++#define DWC_OTG_EP_SPEED_HIGH 2 ++ ++ /** ++ * Endpoint type. ++ * One of the following values: ++ * - DWC_OTG_EP_TYPE_CONTROL: 0 ++ * - DWC_OTG_EP_TYPE_ISOC: 1 ++ * - DWC_OTG_EP_TYPE_BULK: 2 ++ * - DWC_OTG_EP_TYPE_INTR: 3 ++ */ ++ unsigned ep_type:2; ++ ++ /** Max packet size in bytes */ ++ unsigned max_packet:11; ++ ++ /** ++ * PID for initial transaction. ++ * 0: DATA0,
++ * 1: DATA2,
++ * 2: DATA1,
++ * 3: MDATA (non-Control EP), ++ * SETUP (Control EP) ++ */ ++ unsigned data_pid_start:2; ++#define DWC_OTG_HC_PID_DATA0 0 ++#define DWC_OTG_HC_PID_DATA2 1 ++#define DWC_OTG_HC_PID_DATA1 2 ++#define DWC_OTG_HC_PID_MDATA 3 ++#define DWC_OTG_HC_PID_SETUP 3 ++ ++ /** Number of periodic transactions per (micro)frame */ ++ unsigned multi_count:2; ++ ++ /** @name Transfer State */ ++ /** @{ */ ++ ++ /** Pointer to the current transfer buffer position. */ ++ uint8_t *xfer_buff; ++ /** ++ * In Buffer DMA mode this buffer will be used ++ * if xfer_buff is not DWORD aligned. ++ */ ++ dwc_dma_t align_buff; ++ /** Total number of bytes to transfer. */ ++ uint32_t xfer_len; ++ /** Number of bytes transferred so far. */ ++ uint32_t xfer_count; ++ /** Packet count at start of transfer.*/ ++ uint16_t start_pkt_count; ++ ++ /** ++ * Flag to indicate whether the transfer has been started. Set to 1 if ++ * it has been started, 0 otherwise. ++ */ ++ uint8_t xfer_started; ++ ++ /** ++ * Set to 1 to indicate that a PING request should be issued on this ++ * channel. If 0, process normally. ++ */ ++ uint8_t do_ping; ++ ++ /** ++ * Set to 1 to indicate that the error count for this transaction is ++ * non-zero. Set to 0 if the error count is 0. ++ */ ++ uint8_t error_state; ++ ++ /** ++ * Set to 1 to indicate that this channel should be halted the next ++ * time a request is queued for the channel. This is necessary in ++ * slave mode if no request queue space is available when an attempt ++ * is made to halt the channel. ++ */ ++ uint8_t halt_on_queue; ++ ++ /** ++ * Set to 1 if the host channel has been halted, but the core is not ++ * finished flushing queued requests. Otherwise 0. ++ */ ++ uint8_t halt_pending; ++ ++ /** ++ * Reason for halting the host channel. ++ */ ++ dwc_otg_halt_status_e halt_status; ++ ++ /* ++ * Split settings for the host channel ++ */ ++ uint8_t do_split; /**< Enable split for the channel */ ++ uint8_t complete_split; /**< Enable complete split */ ++ uint8_t hub_addr; /**< Address of high speed hub */ ++ ++ uint8_t port_addr; /**< Port of the low/full speed device */ ++ /** Split transaction position ++ * One of the following values: ++ * - DWC_HCSPLIT_XACTPOS_MID ++ * - DWC_HCSPLIT_XACTPOS_BEGIN ++ * - DWC_HCSPLIT_XACTPOS_END ++ * - DWC_HCSPLIT_XACTPOS_ALL */ ++ uint8_t xact_pos; ++ ++ /** Set when the host channel does a short read. */ ++ uint8_t short_read; ++ ++ /** ++ * Number of requests issued for this channel since it was assigned to ++ * the current transfer (not counting PINGs). ++ */ ++ uint8_t requests; ++ ++ /** ++ * Queue Head for the transfer being processed by this channel. ++ */ ++ struct dwc_otg_qh *qh; ++ ++ /** @} */ ++ ++ /** Entry in list of host channels. */ ++ DWC_CIRCLEQ_ENTRY(dwc_hc) hc_list_entry; ++ ++ /** @name Descriptor DMA support */ ++ /** @{ */ ++ ++ /** Number of Transfer Descriptors */ ++ uint16_t ntd; ++ ++ /** Descriptor List DMA address */ ++ dwc_dma_t desc_list_addr; ++ ++ /** Scheduling micro-frame bitmap. */ ++ uint8_t schinfo; ++ ++ /** @} */ ++} dwc_hc_t; ++ ++/** ++ * The following parameters may be specified when starting the module. These ++ * parameters define how the DWC_otg controller should be configured. ++ */ ++typedef struct dwc_otg_core_params { ++ int32_t opt; ++ ++ /** ++ * Specifies the OTG capabilities. The driver will automatically ++ * detect the value for this parameter if none is specified. ++ * 0 - HNP and SRP capable (default) ++ * 1 - SRP Only capable ++ * 2 - No HNP/SRP capable ++ */ ++ int32_t otg_cap; ++ ++ /** ++ * Specifies whether to use slave or DMA mode for accessing the data ++ * FIFOs. The driver will automatically detect the value for this ++ * parameter if none is specified. ++ * 0 - Slave ++ * 1 - DMA (default, if available) ++ */ ++ int32_t dma_enable; ++ ++ /** ++ * When DMA mode is enabled specifies whether to use address DMA or DMA ++ * Descriptor mode for accessing the data FIFOs in device mode. The driver ++ * will automatically detect the value for this if none is specified. ++ * 0 - address DMA ++ * 1 - DMA Descriptor(default, if available) ++ */ ++ int32_t dma_desc_enable; ++ /** The DMA Burst size (applicable only for External DMA ++ * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32) ++ */ ++ int32_t dma_burst_size; /* Translate this to GAHBCFG values */ ++ ++ /** ++ * Specifies the maximum speed of operation in host and device mode. ++ * The actual speed depends on the speed of the attached device and ++ * the value of phy_type. The actual speed depends on the speed of the ++ * attached device. ++ * 0 - High Speed (default) ++ * 1 - Full Speed ++ */ ++ int32_t speed; ++ /** Specifies whether low power mode is supported when attached ++ * to a Full Speed or Low Speed device in host mode. ++ * 0 - Don't support low power mode (default) ++ * 1 - Support low power mode ++ */ ++ int32_t host_support_fs_ls_low_power; ++ ++ /** Specifies the PHY clock rate in low power mode when connected to a ++ * Low Speed device in host mode. This parameter is applicable only if ++ * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS ++ * then defaults to 6 MHZ otherwise 48 MHZ. ++ * ++ * 0 - 48 MHz ++ * 1 - 6 MHz ++ */ ++ int32_t host_ls_low_power_phy_clk; ++ ++ /** ++ * 0 - Use cC FIFO size parameters ++ * 1 - Allow dynamic FIFO sizing (default) ++ */ ++ int32_t enable_dynamic_fifo; ++ ++ /** Total number of 4-byte words in the data FIFO memory. This ++ * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic ++ * Tx FIFOs. ++ * 32 to 32768 (default 8192) ++ * Note: The total FIFO memory depth in the FPGA configuration is 8192. ++ */ ++ int32_t data_fifo_size; ++ ++ /** Number of 4-byte words in the Rx FIFO in device mode when dynamic ++ * FIFO sizing is enabled. ++ * 16 to 32768 (default 1064) ++ */ ++ int32_t dev_rx_fifo_size; ++ ++ /** Number of 4-byte words in the non-periodic Tx FIFO in device mode ++ * when dynamic FIFO sizing is enabled. ++ * 16 to 32768 (default 1024) ++ */ ++ int32_t dev_nperio_tx_fifo_size; ++ ++ /** Number of 4-byte words in each of the periodic Tx FIFOs in device ++ * mode when dynamic FIFO sizing is enabled. ++ * 4 to 768 (default 256) ++ */ ++ uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS]; ++ ++ /** Number of 4-byte words in the Rx FIFO in host mode when dynamic ++ * FIFO sizing is enabled. ++ * 16 to 32768 (default 1024) ++ */ ++ int32_t host_rx_fifo_size; ++ ++ /** Number of 4-byte words in the non-periodic Tx FIFO in host mode ++ * when Dynamic FIFO sizing is enabled in the core. ++ * 16 to 32768 (default 1024) ++ */ ++ int32_t host_nperio_tx_fifo_size; ++ ++ /** Number of 4-byte words in the host periodic Tx FIFO when dynamic ++ * FIFO sizing is enabled. ++ * 16 to 32768 (default 1024) ++ */ ++ int32_t host_perio_tx_fifo_size; ++ ++ /** The maximum transfer size supported in bytes. ++ * 2047 to 65,535 (default 65,535) ++ */ ++ int32_t max_transfer_size; ++ ++ /** The maximum number of packets in a transfer. ++ * 15 to 511 (default 511) ++ */ ++ int32_t max_packet_count; ++ ++ /** The number of host channel registers to use. ++ * 1 to 16 (default 12) ++ * Note: The FPGA configuration supports a maximum of 12 host channels. ++ */ ++ int32_t host_channels; ++ ++ /** The number of endpoints in addition to EP0 available for device ++ * mode operations. ++ * 1 to 15 (default 6 IN and OUT) ++ * Note: The FPGA configuration supports a maximum of 6 IN and OUT ++ * endpoints in addition to EP0. ++ */ ++ int32_t dev_endpoints; ++ ++ /** ++ * Specifies the type of PHY interface to use. By default, the driver ++ * will automatically detect the phy_type. ++ * ++ * 0 - Full Speed PHY ++ * 1 - UTMI+ (default) ++ * 2 - ULPI ++ */ ++ int32_t phy_type; ++ ++ /** ++ * Specifies the UTMI+ Data Width. This parameter is ++ * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI ++ * PHY_TYPE, this parameter indicates the data width between ++ * the MAC and the ULPI Wrapper.) Also, this parameter is ++ * applicable only if the OTG_HSPHY_WIDTH cC parameter was set ++ * to "8 and 16 bits", meaning that the core has been ++ * configured to work at either data path width. ++ * ++ * 8 or 16 bits (default 16) ++ */ ++ int32_t phy_utmi_width; ++ ++ /** ++ * Specifies whether the ULPI operates at double or single ++ * data rate. This parameter is only applicable if PHY_TYPE is ++ * ULPI. ++ * ++ * 0 - single data rate ULPI interface with 8 bit wide data ++ * bus (default) ++ * 1 - double data rate ULPI interface with 4 bit wide data ++ * bus ++ */ ++ int32_t phy_ulpi_ddr; ++ ++ /** ++ * Specifies whether to use the internal or external supply to ++ * drive the vbus with a ULPI phy. ++ */ ++ int32_t phy_ulpi_ext_vbus; ++ ++ /** ++ * Specifies whether to use the I2Cinterface for full speed PHY. This ++ * parameter is only applicable if PHY_TYPE is FS. ++ * 0 - No (default) ++ * 1 - Yes ++ */ ++ int32_t i2c_enable; ++ ++ int32_t ulpi_fs_ls; ++ ++ int32_t ts_dline; ++ ++ /** ++ * Specifies whether dedicated transmit FIFOs are ++ * enabled for non periodic IN endpoints in device mode ++ * 0 - No ++ * 1 - Yes ++ */ ++ int32_t en_multiple_tx_fifo; ++ ++ /** Number of 4-byte words in each of the Tx FIFOs in device ++ * mode when dynamic FIFO sizing is enabled. ++ * 4 to 768 (default 256) ++ */ ++ uint32_t dev_tx_fifo_size[MAX_TX_FIFOS]; ++ ++ /** Thresholding enable flag- ++ * bit 0 - enable non-ISO Tx thresholding ++ * bit 1 - enable ISO Tx thresholding ++ * bit 2 - enable Rx thresholding ++ */ ++ uint32_t thr_ctl; ++ ++ /** Thresholding length for Tx ++ * FIFOs in 32 bit DWORDs ++ */ ++ uint32_t tx_thr_length; ++ ++ /** Thresholding length for Rx ++ * FIFOs in 32 bit DWORDs ++ */ ++ uint32_t rx_thr_length; ++ ++ /** ++ * Specifies whether LPM (Link Power Management) support is enabled ++ */ ++ int32_t lpm_enable; ++ ++ /** Per Transfer Interrupt ++ * mode enable flag ++ * 1 - Enabled ++ * 0 - Disabled ++ */ ++ int32_t pti_enable; ++ ++ /** Multi Processor Interrupt ++ * mode enable flag ++ * 1 - Enabled ++ * 0 - Disabled ++ */ ++ int32_t mpi_enable; ++ ++ /** IS_USB Capability ++ * 1 - Enabled ++ * 0 - Disabled ++ */ ++ int32_t ic_usb_cap; ++ ++ /** AHB Threshold Ratio ++ * 2'b00 AHB Threshold = MAC Threshold ++ * 2'b01 AHB Threshold = 1/2 MAC Threshold ++ * 2'b10 AHB Threshold = 1/4 MAC Threshold ++ * 2'b11 AHB Threshold = 1/8 MAC Threshold ++ */ ++ int32_t ahb_thr_ratio; ++ ++ /** ADP Support ++ * 1 - Enabled ++ * 0 - Disabled ++ */ ++ int32_t adp_supp_enable; ++ ++ /** HFIR Reload Control ++ * 0 - The HFIR cannot be reloaded dynamically. ++ * 1 - Allow dynamic reloading of the HFIR register during runtime. ++ */ ++ int32_t reload_ctl; ++ ++ /** DCFG: Enable device Out NAK ++ * 0 - The core does not set NAK after Bulk Out transfer complete. ++ * 1 - The core sets NAK after Bulk OUT transfer complete. ++ */ ++ int32_t dev_out_nak; ++ ++ /** DCFG: Enable Continue on BNA ++ * After receiving BNA interrupt the core disables the endpoint,when the ++ * endpoint is re-enabled by the application the core starts processing ++ * 0 - from the DOEPDMA descriptor ++ * 1 - from the descriptor which received the BNA. ++ */ ++ int32_t cont_on_bna; ++ ++ /** GAHBCFG: AHB Single Support ++ * This bit when programmed supports SINGLE transfers for remainder ++ * data in a transfer for DMA mode of operation. ++ * 0 - in this case the remainder data will be sent using INCR burst size. ++ * 1 - in this case the remainder data will be sent using SINGLE burst size. ++ */ ++ int32_t ahb_single; ++ ++ /** Core Power down mode ++ * 0 - No Power Down is enabled ++ * 1 - Reserved ++ * 2 - Complete Power Down (Hibernation) ++ */ ++ int32_t power_down; ++ ++ /** OTG revision supported ++ * 0 - OTG 1.3 revision ++ * 1 - OTG 2.0 revision ++ */ ++ int32_t otg_ver; ++ ++} dwc_otg_core_params_t; ++ ++#ifdef DEBUG ++struct dwc_otg_core_if; ++typedef struct hc_xfer_info { ++ struct dwc_otg_core_if *core_if; ++ dwc_hc_t *hc; ++} hc_xfer_info_t; ++#endif ++ ++typedef struct ep_xfer_info { ++ struct dwc_otg_core_if *core_if; ++ dwc_ep_t *ep; ++ uint8_t state; ++} ep_xfer_info_t; ++/* ++ * Device States ++ */ ++typedef enum dwc_otg_lx_state { ++ /** On state */ ++ DWC_OTG_L0, ++ /** LPM sleep state*/ ++ DWC_OTG_L1, ++ /** USB suspend state*/ ++ DWC_OTG_L2, ++ /** Off state*/ ++ DWC_OTG_L3 ++} dwc_otg_lx_state_e; ++ ++struct dwc_otg_global_regs_backup { ++ uint32_t gotgctl_local; ++ uint32_t gintmsk_local; ++ uint32_t gahbcfg_local; ++ uint32_t gusbcfg_local; ++ uint32_t grxfsiz_local; ++ uint32_t gnptxfsiz_local; ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ uint32_t glpmcfg_local; ++#endif ++ uint32_t gi2cctl_local; ++ uint32_t hptxfsiz_local; ++ uint32_t pcgcctl_local; ++ uint32_t gdfifocfg_local; ++ uint32_t dtxfsiz_local[MAX_EPS_CHANNELS]; ++ uint32_t gpwrdn_local; ++ uint32_t xhib_pcgcctl; ++ uint32_t xhib_gpwrdn; ++}; ++ ++struct dwc_otg_host_regs_backup { ++ uint32_t hcfg_local; ++ uint32_t haintmsk_local; ++ uint32_t hcintmsk_local[MAX_EPS_CHANNELS]; ++ uint32_t hprt0_local; ++ uint32_t hfir_local; ++}; ++ ++struct dwc_otg_dev_regs_backup { ++ uint32_t dcfg; ++ uint32_t dctl; ++ uint32_t daintmsk; ++ uint32_t diepmsk; ++ uint32_t doepmsk; ++ uint32_t diepctl[MAX_EPS_CHANNELS]; ++ uint32_t dieptsiz[MAX_EPS_CHANNELS]; ++ uint32_t diepdma[MAX_EPS_CHANNELS]; ++}; ++/** ++ * The dwc_otg_core_if structure contains information needed to manage ++ * the DWC_otg controller acting in either host or device mode. It ++ * represents the programming view of the controller as a whole. ++ */ ++struct dwc_otg_core_if { ++ /** Parameters that define how the core should be configured.*/ ++ dwc_otg_core_params_t *core_params; ++ ++ /** Core Global registers starting at offset 000h. */ ++ dwc_otg_core_global_regs_t *core_global_regs; ++ ++ /** Device-specific information */ ++ dwc_otg_dev_if_t *dev_if; ++ /** Host-specific information */ ++ dwc_otg_host_if_t *host_if; ++ ++ /** Value from SNPSID register */ ++ uint32_t snpsid; ++ ++ /* ++ * Set to 1 if the core PHY interface bits in USBCFG have been ++ * initialized. ++ */ ++ uint8_t phy_init_done; ++ ++ /* ++ * SRP Success flag, set by srp success interrupt in FS I2C mode ++ */ ++ uint8_t srp_success; ++ uint8_t srp_timer_started; ++ /** Timer for SRP. If it expires before SRP is successful ++ * clear the SRP. */ ++ dwc_timer_t *srp_timer; ++ ++#ifdef DWC_DEV_SRPCAP ++ /* This timer is needed to power on the hibernated host core if SRP is not ++ * initiated on connected SRP capable device for limited period of time ++ */ ++ uint8_t pwron_timer_started; ++ dwc_timer_t *pwron_timer; ++#endif ++ /* Common configuration information */ ++ /** Power and Clock Gating Control Register */ ++ volatile uint32_t *pcgcctl; ++#define DWC_OTG_PCGCCTL_OFFSET 0xE00 ++ ++ /** Push/pop addresses for endpoints or host channels.*/ ++ uint32_t *data_fifo[MAX_EPS_CHANNELS]; ++#define DWC_OTG_DATA_FIFO_OFFSET 0x1000 ++#define DWC_OTG_DATA_FIFO_SIZE 0x1000 ++ ++ /** Total RAM for FIFOs (Bytes) */ ++ uint16_t total_fifo_size; ++ /** Size of Rx FIFO (Bytes) */ ++ uint16_t rx_fifo_size; ++ /** Size of Non-periodic Tx FIFO (Bytes) */ ++ uint16_t nperio_tx_fifo_size; ++ ++ /** 1 if DMA is enabled, 0 otherwise. */ ++ uint8_t dma_enable; ++ ++ /** 1 if DMA descriptor is enabled, 0 otherwise. */ ++ uint8_t dma_desc_enable; ++ ++ /** 1 if PTI Enhancement mode is enabled, 0 otherwise. */ ++ uint8_t pti_enh_enable; ++ ++ /** 1 if MPI Enhancement mode is enabled, 0 otherwise. */ ++ uint8_t multiproc_int_enable; ++ ++ /** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */ ++ uint8_t en_multiple_tx_fifo; ++ ++ /** Set to 1 if multiple packets of a high-bandwidth transfer is in ++ * process of being queued */ ++ uint8_t queuing_high_bandwidth; ++ ++ /** Hardware Configuration -- stored here for convenience.*/ ++ hwcfg1_data_t hwcfg1; ++ hwcfg2_data_t hwcfg2; ++ hwcfg3_data_t hwcfg3; ++ hwcfg4_data_t hwcfg4; ++ fifosize_data_t hptxfsiz; ++ ++ /** Host and Device Configuration -- stored here for convenience.*/ ++ hcfg_data_t hcfg; ++ dcfg_data_t dcfg; ++ ++ /** The operational State, during transations ++ * (a_host>>a_peripherial and b_device=>b_host) this may not ++ * match the core but allows the software to determine ++ * transitions. ++ */ ++ uint8_t op_state; ++ ++ /** ++ * Set to 1 if the HCD needs to be restarted on a session request ++ * interrupt. This is required if no connector ID status change has ++ * occurred since the HCD was last disconnected. ++ */ ++ uint8_t restart_hcd_on_session_req; ++ ++ /** HCD callbacks */ ++ /** A-Device is a_host */ ++#define A_HOST (1) ++ /** A-Device is a_suspend */ ++#define A_SUSPEND (2) ++ /** A-Device is a_peripherial */ ++#define A_PERIPHERAL (3) ++ /** B-Device is operating as a Peripheral. */ ++#define B_PERIPHERAL (4) ++ /** B-Device is operating as a Host. */ ++#define B_HOST (5) ++ ++ /** HCD callbacks */ ++ struct dwc_otg_cil_callbacks *hcd_cb; ++ /** PCD callbacks */ ++ struct dwc_otg_cil_callbacks *pcd_cb; ++ ++ /** Device mode Periodic Tx FIFO Mask */ ++ uint32_t p_tx_msk; ++ /** Device mode Periodic Tx FIFO Mask */ ++ uint32_t tx_msk; ++ ++ /** Workqueue object used for handling several interrupts */ ++ dwc_workq_t *wq_otg; ++ ++ /** Timer object used for handling "Wakeup Detected" Interrupt */ ++ dwc_timer_t *wkp_timer; ++ /** This arrays used for debug purposes for DEV OUT NAK enhancement */ ++ uint32_t start_doeptsiz_val[MAX_EPS_CHANNELS]; ++ ep_xfer_info_t ep_xfer_info[MAX_EPS_CHANNELS]; ++ dwc_timer_t *ep_xfer_timer[MAX_EPS_CHANNELS]; ++#ifdef DEBUG ++ uint32_t start_hcchar_val[MAX_EPS_CHANNELS]; ++ ++ hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS]; ++ dwc_timer_t *hc_xfer_timer[MAX_EPS_CHANNELS]; ++ ++ uint32_t hfnum_7_samples; ++ uint64_t hfnum_7_frrem_accum; ++ uint32_t hfnum_0_samples; ++ uint64_t hfnum_0_frrem_accum; ++ uint32_t hfnum_other_samples; ++ uint64_t hfnum_other_frrem_accum; ++#endif ++ ++#ifdef DWC_UTE_CFI ++ uint16_t pwron_rxfsiz; ++ uint16_t pwron_gnptxfsiz; ++ uint16_t pwron_txfsiz[15]; ++ ++ uint16_t init_rxfsiz; ++ uint16_t init_gnptxfsiz; ++ uint16_t init_txfsiz[15]; ++#endif ++ ++ /** Lx state of device */ ++ dwc_otg_lx_state_e lx_state; ++ ++ /** Saved Core Global registers */ ++ struct dwc_otg_global_regs_backup *gr_backup; ++ /** Saved Host registers */ ++ struct dwc_otg_host_regs_backup *hr_backup; ++ /** Saved Device registers */ ++ struct dwc_otg_dev_regs_backup *dr_backup; ++ ++ /** Power Down Enable */ ++ uint32_t power_down; ++ ++ /** ADP support Enable */ ++ uint32_t adp_enable; ++ ++ /** ADP structure object */ ++ dwc_otg_adp_t adp; ++ ++ /** hibernation/suspend flag */ ++ int hibernation_suspend; ++ ++ /** Device mode extended hibernation flag */ ++ int xhib; ++ ++ /** OTG revision supported */ ++ uint32_t otg_ver; ++ ++ /** OTG status flag used for HNP polling */ ++ uint8_t otg_sts; ++ ++ /** Pointer to either hcd->lock or pcd->lock */ ++ dwc_spinlock_t *lock; ++ ++ /** Start predict NextEP based on Learning Queue if equal 1, ++ * also used as counter of disabled NP IN EP's */ ++ uint8_t start_predict; ++ ++ /** NextEp sequence, including EP0: nextep_seq[] = EP if non-periodic and ++ * active, 0xff otherwise */ ++ uint8_t nextep_seq[MAX_EPS_CHANNELS]; ++ ++ /** Index of fisrt EP in nextep_seq array which should be re-enabled **/ ++ uint8_t first_in_nextep_seq; ++ ++ /** Frame number while entering to ISR - needed for ISOCs **/ ++ uint32_t frame_num; ++ ++}; ++ ++#ifdef DEBUG ++/* ++ * This function is called when transfer is timed out. ++ */ ++extern void hc_xfer_timeout(void *ptr); ++#endif ++ ++/* ++ * This function is called when transfer is timed out on endpoint. ++ */ ++extern void ep_xfer_timeout(void *ptr); ++ ++/* ++ * The following functions are functions for works ++ * using during handling some interrupts ++ */ ++extern void w_conn_id_status_change(void *p); ++ ++extern void w_wakeup_detected(void *p); ++ ++/** Saves global register values into system memory. */ ++extern int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if); ++/** Saves device register values into system memory. */ ++extern int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if); ++/** Saves host register values into system memory. */ ++extern int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if); ++/** Restore global register values. */ ++extern int dwc_otg_restore_global_regs(dwc_otg_core_if_t * core_if); ++/** Restore host register values. */ ++extern int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset); ++/** Restore device register values. */ ++extern int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if, ++ int rem_wakeup); ++extern int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if); ++extern int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode, ++ int is_host); ++ ++extern int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if, ++ int restore_mode, int reset); ++extern int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if, ++ int rem_wakeup, int reset); ++ ++/* ++ * The following functions support initialization of the CIL driver component ++ * and the DWC_otg controller. ++ */ ++extern void dwc_otg_core_host_init(dwc_otg_core_if_t * _core_if); ++extern void dwc_otg_core_dev_init(dwc_otg_core_if_t * _core_if); ++ ++/** @name Device CIL Functions ++ * The following functions support managing the DWC_otg controller in device ++ * mode. ++ */ ++/**@{*/ ++extern void dwc_otg_wakeup(dwc_otg_core_if_t * _core_if); ++extern void dwc_otg_read_setup_packet(dwc_otg_core_if_t * _core_if, ++ uint32_t * _dest); ++extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * _core_if); ++extern void dwc_otg_ep0_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep); ++extern void dwc_otg_ep_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep); ++extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep); ++extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * _core_if, ++ dwc_ep_t * _ep); ++extern void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * _core_if, ++ dwc_ep_t * _ep); ++extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * _core_if, ++ dwc_ep_t * _ep); ++extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * _core_if, ++ dwc_ep_t * _ep); ++extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t * _core_if, ++ dwc_ep_t * _ep, int _dma); ++extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep); ++extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * _core_if, ++ dwc_ep_t * _ep); ++extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * _core_if); ++ ++#ifdef DWC_EN_ISOC ++extern void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if, ++ dwc_ep_t * ep); ++extern void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if, ++ dwc_ep_t * ep); ++#endif /* DWC_EN_ISOC */ ++/**@}*/ ++ ++/** @name Host CIL Functions ++ * The following functions support managing the DWC_otg controller in host ++ * mode. ++ */ ++/**@{*/ ++extern void dwc_otg_hc_init(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc); ++extern void dwc_otg_hc_halt(dwc_otg_core_if_t * _core_if, ++ dwc_hc_t * _hc, dwc_otg_halt_status_e _halt_status); ++extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc); ++extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * _core_if, ++ dwc_hc_t * _hc); ++extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * _core_if, ++ dwc_hc_t * _hc); ++extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc); ++extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t * _core_if, ++ dwc_hc_t * _hc); ++extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * _core_if); ++extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * _core_if); ++ ++extern void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if, ++ dwc_hc_t * hc); ++ ++extern uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if); ++ ++/* Macro used to clear one channel interrupt */ ++#define clear_hc_int(_hc_regs_, _intr_) \ ++do { \ ++ hcint_data_t hcint_clear = {.d32 = 0}; \ ++ hcint_clear.b._intr_ = 1; \ ++ DWC_WRITE_REG32(&(_hc_regs_)->hcint, hcint_clear.d32); \ ++} while (0) ++ ++/* ++ * Macro used to disable one channel interrupt. Channel interrupts are ++ * disabled when the channel is halted or released by the interrupt handler. ++ * There is no need to handle further interrupts of that type until the ++ * channel is re-assigned. In fact, subsequent handling may cause crashes ++ * because the channel structures are cleaned up when the channel is released. ++ */ ++#define disable_hc_int(_hc_regs_, _intr_) \ ++do { \ ++ hcintmsk_data_t hcintmsk = {.d32 = 0}; \ ++ hcintmsk.b._intr_ = 1; \ ++ DWC_MODIFY_REG32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \ ++} while (0) ++ ++/** ++ * This function Reads HPRT0 in preparation to modify. It keeps the ++ * WC bits 0 so that if they are read as 1, they won't clear when you ++ * write it back ++ */ ++static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t * _core_if) ++{ ++ hprt0_data_t hprt0; ++ hprt0.d32 = DWC_READ_REG32(_core_if->host_if->hprt0); ++ hprt0.b.prtena = 0; ++ hprt0.b.prtconndet = 0; ++ hprt0.b.prtenchng = 0; ++ hprt0.b.prtovrcurrchng = 0; ++ return hprt0.d32; ++} ++ ++/**@}*/ ++ ++/** @name Common CIL Functions ++ * The following functions support managing the DWC_otg controller in either ++ * device or host mode. ++ */ ++/**@{*/ ++ ++extern void dwc_otg_read_packet(dwc_otg_core_if_t * core_if, ++ uint8_t * dest, uint16_t bytes); ++ ++extern void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * _core_if, const int _num); ++extern void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * _core_if); ++extern void dwc_otg_core_reset(dwc_otg_core_if_t * _core_if); ++ ++/** ++ * This function returns the Core Interrupt register. ++ */ ++static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t * core_if) ++{ ++ return (DWC_READ_REG32(&core_if->core_global_regs->gintsts) & ++ DWC_READ_REG32(&core_if->core_global_regs->gintmsk)); ++} ++ ++/** ++ * This function returns the OTG Interrupt register. ++ */ ++static inline uint32_t dwc_otg_read_otg_intr(dwc_otg_core_if_t * core_if) ++{ ++ return (DWC_READ_REG32(&core_if->core_global_regs->gotgint)); ++} ++ ++/** ++ * This function reads the Device All Endpoints Interrupt register and ++ * returns the IN endpoint interrupt bits. ++ */ ++static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t * ++ core_if) ++{ ++ ++ uint32_t v; ++ ++ if (core_if->multiproc_int_enable) { ++ v = DWC_READ_REG32(&core_if->dev_if-> ++ dev_global_regs->deachint) & ++ DWC_READ_REG32(&core_if-> ++ dev_if->dev_global_regs->deachintmsk); ++ } else { ++ v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) & ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk); ++ } ++ return (v & 0xffff); ++} ++ ++/** ++ * This function reads the Device All Endpoints Interrupt register and ++ * returns the OUT endpoint interrupt bits. ++ */ ++static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t * ++ core_if) ++{ ++ uint32_t v; ++ ++ if (core_if->multiproc_int_enable) { ++ v = DWC_READ_REG32(&core_if->dev_if-> ++ dev_global_regs->deachint) & ++ DWC_READ_REG32(&core_if-> ++ dev_if->dev_global_regs->deachintmsk); ++ } else { ++ v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) & ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk); ++ } ++ ++ return ((v & 0xffff0000) >> 16); ++} ++ ++/** ++ * This function returns the Device IN EP Interrupt register ++ */ ++static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t * core_if, ++ dwc_ep_t * ep) ++{ ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ uint32_t v, msk, emp; ++ ++ if (core_if->multiproc_int_enable) { ++ msk = ++ DWC_READ_REG32(&dev_if-> ++ dev_global_regs->diepeachintmsk[ep->num]); ++ emp = ++ DWC_READ_REG32(&dev_if-> ++ dev_global_regs->dtknqr4_fifoemptymsk); ++ msk |= ((emp >> ep->num) & 0x1) << 7; ++ v = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk; ++ } else { ++ msk = DWC_READ_REG32(&dev_if->dev_global_regs->diepmsk); ++ emp = ++ DWC_READ_REG32(&dev_if-> ++ dev_global_regs->dtknqr4_fifoemptymsk); ++ msk |= ((emp >> ep->num) & 0x1) << 7; ++ v = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk; ++ } ++ ++ return v; ++} ++ ++/** ++ * This function returns the Device OUT EP Interrupt register ++ */ ++static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t * ++ _core_if, dwc_ep_t * _ep) ++{ ++ dwc_otg_dev_if_t *dev_if = _core_if->dev_if; ++ uint32_t v; ++ doepmsk_data_t msk = {.d32 = 0 }; ++ ++ if (_core_if->multiproc_int_enable) { ++ msk.d32 = ++ DWC_READ_REG32(&dev_if-> ++ dev_global_regs->doepeachintmsk[_ep->num]); ++ if (_core_if->pti_enh_enable) { ++ msk.b.pktdrpsts = 1; ++ } ++ v = DWC_READ_REG32(&dev_if-> ++ out_ep_regs[_ep->num]->doepint) & msk.d32; ++ } else { ++ msk.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->doepmsk); ++ if (_core_if->pti_enh_enable) { ++ msk.b.pktdrpsts = 1; ++ } ++ v = DWC_READ_REG32(&dev_if-> ++ out_ep_regs[_ep->num]->doepint) & msk.d32; ++ } ++ return v; ++} ++ ++/** ++ * This function returns the Host All Channel Interrupt register ++ */ ++static inline uint32_t dwc_otg_read_host_all_channels_intr(dwc_otg_core_if_t * ++ _core_if) ++{ ++ return (DWC_READ_REG32(&_core_if->host_if->host_global_regs->haint)); ++} ++ ++static inline uint32_t dwc_otg_read_host_channel_intr(dwc_otg_core_if_t * ++ _core_if, dwc_hc_t * _hc) ++{ ++ return (DWC_READ_REG32 ++ (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint)); ++} ++ ++/** ++ * This function returns the mode of the operation, host or device. ++ * ++ * @return 0 - Device Mode, 1 - Host Mode ++ */ ++static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t * _core_if) ++{ ++ return (DWC_READ_REG32(&_core_if->core_global_regs->gintsts) & 0x1); ++} ++ ++/**@}*/ ++ ++/** ++ * DWC_otg CIL callback structure. This structure allows the HCD and ++ * PCD to register functions used for starting and stopping the PCD ++ * and HCD for role change on for a DRD. ++ */ ++typedef struct dwc_otg_cil_callbacks { ++ /** Start function for role change */ ++ int (*start) (void *_p); ++ /** Stop Function for role change */ ++ int (*stop) (void *_p); ++ /** Disconnect Function for role change */ ++ int (*disconnect) (void *_p); ++ /** Resume/Remote wakeup Function */ ++ int (*resume_wakeup) (void *_p); ++ /** Suspend function */ ++ int (*suspend) (void *_p); ++ /** Session Start (SRP) */ ++ int (*session_start) (void *_p); ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ /** Sleep (switch to L0 state) */ ++ int (*sleep) (void *_p); ++#endif ++ /** Pointer passed to start() and stop() */ ++ void *p; ++} dwc_otg_cil_callbacks_t; ++ ++extern void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * _core_if, ++ dwc_otg_cil_callbacks_t * _cb, ++ void *_p); ++extern void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * _core_if, ++ dwc_otg_cil_callbacks_t * _cb, ++ void *_p); ++ ++void dwc_otg_initiate_srp(dwc_otg_core_if_t * core_if); ++ ++////////////////////////////////////////////////////////////////////// ++/** Start the HCD. Helper function for using the HCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void cil_hcd_start(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->hcd_cb && core_if->hcd_cb->start) { ++ core_if->hcd_cb->start(core_if->hcd_cb->p); ++ } ++} ++ ++/** Stop the HCD. Helper function for using the HCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void cil_hcd_stop(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->hcd_cb && core_if->hcd_cb->stop) { ++ core_if->hcd_cb->stop(core_if->hcd_cb->p); ++ } ++} ++ ++/** Disconnect the HCD. Helper function for using the HCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void cil_hcd_disconnect(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->hcd_cb && core_if->hcd_cb->disconnect) { ++ core_if->hcd_cb->disconnect(core_if->hcd_cb->p); ++ } ++} ++ ++/** Inform the HCD the a New Session has begun. Helper function for ++ * using the HCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void cil_hcd_session_start(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->hcd_cb && core_if->hcd_cb->session_start) { ++ core_if->hcd_cb->session_start(core_if->hcd_cb->p); ++ } ++} ++ ++#ifdef CONFIG_USB_DWC_OTG_LPM ++/** ++ * Inform the HCD about LPM sleep. ++ * Helper function for using the HCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void cil_hcd_sleep(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->hcd_cb && core_if->hcd_cb->sleep) { ++ core_if->hcd_cb->sleep(core_if->hcd_cb->p); ++ } ++} ++#endif ++ ++/** Resume the HCD. Helper function for using the HCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void cil_hcd_resume(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->hcd_cb && core_if->hcd_cb->resume_wakeup) { ++ core_if->hcd_cb->resume_wakeup(core_if->hcd_cb->p); ++ } ++} ++ ++/** Start the PCD. Helper function for using the PCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void cil_pcd_start(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->pcd_cb && core_if->pcd_cb->start) { ++ core_if->pcd_cb->start(core_if->pcd_cb->p); ++ } ++} ++ ++/** Stop the PCD. Helper function for using the PCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void cil_pcd_stop(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->pcd_cb && core_if->pcd_cb->stop) { ++ core_if->pcd_cb->stop(core_if->pcd_cb->p); ++ } ++} ++ ++/** Suspend the PCD. Helper function for using the PCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void cil_pcd_suspend(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->pcd_cb && core_if->pcd_cb->suspend) { ++ core_if->pcd_cb->suspend(core_if->pcd_cb->p); ++ } ++} ++ ++/** Resume the PCD. Helper function for using the PCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void cil_pcd_resume(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) { ++ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p); ++ } ++} ++ ++////////////////////////////////////////////////////////////////////// ++ ++#endif +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c 2015-11-29 09:42:39.919098694 +0100 +@@ -0,0 +1,1594 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil_intr.c $ ++ * $Revision: #32 $ ++ * $Date: 2012/08/10 $ ++ * $Change: 2047372 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++/** @file ++ * ++ * The Core Interface Layer provides basic services for accessing and ++ * managing the DWC_otg hardware. These services are used by both the ++ * Host Controller Driver and the Peripheral Controller Driver. ++ * ++ * This file contains the Common Interrupt handlers. ++ */ ++#include "dwc_os.h" ++#include "dwc_otg_regs.h" ++#include "dwc_otg_cil.h" ++#include "dwc_otg_driver.h" ++#include "dwc_otg_pcd.h" ++#include "dwc_otg_hcd.h" ++ ++#ifdef DEBUG ++inline const char *op_state_str(dwc_otg_core_if_t * core_if) ++{ ++ return (core_if->op_state == A_HOST ? "a_host" : ++ (core_if->op_state == A_SUSPEND ? "a_suspend" : ++ (core_if->op_state == A_PERIPHERAL ? "a_peripheral" : ++ (core_if->op_state == B_PERIPHERAL ? "b_peripheral" : ++ (core_if->op_state == B_HOST ? "b_host" : "unknown"))))); ++} ++#endif ++ ++/** This function will log a debug message ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++int32_t dwc_otg_handle_mode_mismatch_intr(dwc_otg_core_if_t * core_if) ++{ ++ gintsts_data_t gintsts; ++ DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n", ++ dwc_otg_mode(core_if) ? "Host" : "Device"); ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.modemismatch = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ return 1; ++} ++ ++/** ++ * This function handles the OTG Interrupts. It reads the OTG ++ * Interrupt Register (GOTGINT) to determine what interrupt has ++ * occurred. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t * core_if) ++{ ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ gotgint_data_t gotgint; ++ gotgctl_data_t gotgctl; ++ gintmsk_data_t gintmsk; ++ gpwrdn_data_t gpwrdn; ++ ++ gotgint.d32 = DWC_READ_REG32(&global_regs->gotgint); ++ gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl); ++ DWC_DEBUGPL(DBG_CIL, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint.d32, ++ op_state_str(core_if)); ++ ++ if (gotgint.b.sesenddet) { ++ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " ++ "Session End Detected++ (%s)\n", ++ op_state_str(core_if)); ++ gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl); ++ ++ if (core_if->op_state == B_HOST) { ++ cil_pcd_start(core_if); ++ core_if->op_state = B_PERIPHERAL; ++ } else { ++ /* If not B_HOST and Device HNP still set. HNP ++ * Did not succeed!*/ ++ if (gotgctl.b.devhnpen) { ++ DWC_DEBUGPL(DBG_ANY, "Session End Detected\n"); ++ __DWC_ERROR("Device Not Connected/Responding!\n"); ++ } ++ ++ /* If Session End Detected the B-Cable has ++ * been disconnected. */ ++ /* Reset PCD and Gadget driver to a ++ * clean state. */ ++ core_if->lx_state = DWC_OTG_L0; ++ DWC_SPINUNLOCK(core_if->lock); ++ cil_pcd_stop(core_if); ++ DWC_SPINLOCK(core_if->lock); ++ ++ if (core_if->adp_enable) { ++ if (core_if->power_down == 2) { ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if-> ++ core_global_regs-> ++ gpwrdn, gpwrdn.d32, 0); ++ } ++ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ ++ dwc_otg_adp_sense_start(core_if); ++ } ++ } ++ ++ gotgctl.d32 = 0; ++ gotgctl.b.devhnpen = 1; ++ DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0); ++ } ++ if (gotgint.b.sesreqsucstschng) { ++ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " ++ "Session Reqeust Success Status Change++\n"); ++ gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl); ++ if (gotgctl.b.sesreqscs) { ++ ++ if ((core_if->core_params->phy_type == ++ DWC_PHY_TYPE_PARAM_FS) && (core_if->core_params->i2c_enable)) { ++ core_if->srp_success = 1; ++ } else { ++ DWC_SPINUNLOCK(core_if->lock); ++ cil_pcd_resume(core_if); ++ DWC_SPINLOCK(core_if->lock); ++ /* Clear Session Request */ ++ gotgctl.d32 = 0; ++ gotgctl.b.sesreq = 1; ++ DWC_MODIFY_REG32(&global_regs->gotgctl, ++ gotgctl.d32, 0); ++ } ++ } ++ } ++ if (gotgint.b.hstnegsucstschng) { ++ /* Print statements during the HNP interrupt handling ++ * can cause it to fail.*/ ++ gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl); ++ /* WA for 3.00a- HW is not setting cur_mode, even sometimes ++ * this does not help*/ ++ if (core_if->snpsid >= OTG_CORE_REV_3_00a) ++ dwc_udelay(100); ++ if (gotgctl.b.hstnegscs) { ++ if (dwc_otg_is_host_mode(core_if)) { ++ core_if->op_state = B_HOST; ++ /* ++ * Need to disable SOF interrupt immediately. ++ * When switching from device to host, the PCD ++ * interrupt handler won't handle the ++ * interrupt if host mode is already set. The ++ * HCD interrupt handler won't get called if ++ * the HCD state is HALT. This means that the ++ * interrupt does not get handled and Linux ++ * complains loudly. ++ */ ++ gintmsk.d32 = 0; ++ gintmsk.b.sofintr = 1; ++ DWC_MODIFY_REG32(&global_regs->gintmsk, ++ gintmsk.d32, 0); ++ /* Call callback function with spin lock released */ ++ DWC_SPINUNLOCK(core_if->lock); ++ cil_pcd_stop(core_if); ++ /* ++ * Initialize the Core for Host mode. ++ */ ++ cil_hcd_start(core_if); ++ DWC_SPINLOCK(core_if->lock); ++ core_if->op_state = B_HOST; ++ } ++ } else { ++ gotgctl.d32 = 0; ++ gotgctl.b.hnpreq = 1; ++ gotgctl.b.devhnpen = 1; ++ DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0); ++ DWC_DEBUGPL(DBG_ANY, "HNP Failed\n"); ++ __DWC_ERROR("Device Not Connected/Responding\n"); ++ } ++ } ++ if (gotgint.b.hstnegdet) { ++ /* The disconnect interrupt is set at the same time as ++ * Host Negotiation Detected. During the mode ++ * switch all interrupts are cleared so the disconnect ++ * interrupt handler will not get executed. ++ */ ++ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " ++ "Host Negotiation Detected++ (%s)\n", ++ (dwc_otg_is_host_mode(core_if) ? "Host" : ++ "Device")); ++ if (dwc_otg_is_device_mode(core_if)) { ++ DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n", ++ core_if->op_state); ++ DWC_SPINUNLOCK(core_if->lock); ++ cil_hcd_disconnect(core_if); ++ cil_pcd_start(core_if); ++ DWC_SPINLOCK(core_if->lock); ++ core_if->op_state = A_PERIPHERAL; ++ } else { ++ /* ++ * Need to disable SOF interrupt immediately. When ++ * switching from device to host, the PCD interrupt ++ * handler won't handle the interrupt if host mode is ++ * already set. The HCD interrupt handler won't get ++ * called if the HCD state is HALT. This means that ++ * the interrupt does not get handled and Linux ++ * complains loudly. ++ */ ++ gintmsk.d32 = 0; ++ gintmsk.b.sofintr = 1; ++ DWC_MODIFY_REG32(&global_regs->gintmsk, gintmsk.d32, 0); ++ DWC_SPINUNLOCK(core_if->lock); ++ cil_pcd_stop(core_if); ++ cil_hcd_start(core_if); ++ DWC_SPINLOCK(core_if->lock); ++ core_if->op_state = A_HOST; ++ } ++ } ++ if (gotgint.b.adevtoutchng) { ++ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " ++ "A-Device Timeout Change++\n"); ++ } ++ if (gotgint.b.debdone) { ++ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " "Debounce Done++\n"); ++ } ++ ++ /* Clear GOTGINT */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gotgint, gotgint.d32); ++ ++ return 1; ++} ++ ++void w_conn_id_status_change(void *p) ++{ ++ dwc_otg_core_if_t *core_if = p; ++ uint32_t count = 0; ++ gotgctl_data_t gotgctl = {.d32 = 0 }; ++ ++ gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl); ++ DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32); ++ DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts); ++ ++ /* B-Device connector (Device Mode) */ ++ if (gotgctl.b.conidsts) { ++ /* Wait for switch to device mode. */ ++ while (!dwc_otg_is_device_mode(core_if)) { ++ DWC_PRINTF("Waiting for Peripheral Mode, Mode=%s\n", ++ (dwc_otg_is_host_mode(core_if) ? "Host" : ++ "Peripheral")); ++ dwc_mdelay(100); ++ if (++count > 10000) ++ break; ++ } ++ DWC_ASSERT(++count < 10000, ++ "Connection id status change timed out"); ++ core_if->op_state = B_PERIPHERAL; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_pcd_start(core_if); ++ } else { ++ /* A-Device connector (Host Mode) */ ++ while (!dwc_otg_is_host_mode(core_if)) { ++ DWC_PRINTF("Waiting for Host Mode, Mode=%s\n", ++ (dwc_otg_is_host_mode(core_if) ? "Host" : ++ "Peripheral")); ++ dwc_mdelay(100); ++ if (++count > 10000) ++ break; ++ } ++ DWC_ASSERT(++count < 10000, ++ "Connection id status change timed out"); ++ core_if->op_state = A_HOST; ++ /* ++ * Initialize the Core for Host mode. ++ */ ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_hcd_start(core_if); ++ } ++} ++ ++/** ++ * This function handles the Connector ID Status Change Interrupt. It ++ * reads the OTG Interrupt Register (GOTCTL) to determine whether this ++ * is a Device to Host Mode transition or a Host Mode to Device ++ * Transition. ++ * ++ * This only occurs when the cable is connected/removed from the PHY ++ * connector. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t * core_if) ++{ ++ ++ /* ++ * Need to disable SOF interrupt immediately. If switching from device ++ * to host, the PCD interrupt handler won't handle the interrupt if ++ * host mode is already set. The HCD interrupt handler won't get ++ * called if the HCD state is HALT. This means that the interrupt does ++ * not get handled and Linux complains loudly. ++ */ ++ gintmsk_data_t gintmsk = {.d32 = 0 }; ++ gintsts_data_t gintsts = {.d32 = 0 }; ++ ++ gintmsk.b.sofintr = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0); ++ ++ DWC_DEBUGPL(DBG_CIL, ++ " ++Connector ID Status Change Interrupt++ (%s)\n", ++ (dwc_otg_is_host_mode(core_if) ? "Host" : "Device")); ++ ++ DWC_SPINUNLOCK(core_if->lock); ++ ++ /* ++ * Need to schedule a work, as there are possible DELAY function calls ++ * Release lock before scheduling workq as it holds spinlock during scheduling ++ */ ++ ++ DWC_WORKQ_SCHEDULE(core_if->wq_otg, w_conn_id_status_change, ++ core_if, "connection id status change"); ++ DWC_SPINLOCK(core_if->lock); ++ ++ /* Set flag and clear interrupt */ ++ gintsts.b.conidstschng = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * This interrupt indicates that a device is initiating the Session ++ * Request Protocol to request the host to turn on bus power so a new ++ * session can begin. The handler responds by turning on bus power. If ++ * the DWC_otg controller is in low power mode, the handler brings the ++ * controller out of low power mode before turning on bus power. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t * core_if) ++{ ++ gintsts_data_t gintsts; ++ ++#ifndef DWC_HOST_ONLY ++ DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n"); ++ ++ if (dwc_otg_is_device_mode(core_if)) { ++ DWC_PRINTF("SRP: Device mode\n"); ++ } else { ++ hprt0_data_t hprt0; ++ DWC_PRINTF("SRP: Host mode\n"); ++ ++ /* Turn on the port power bit. */ ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtpwr = 1; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ ++ /* Start the Connection timer. So a message can be displayed ++ * if connect does not occur within 10 seconds. */ ++ cil_hcd_session_start(core_if); ++ } ++#endif ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.sessreqintr = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ return 1; ++} ++ ++void w_wakeup_detected(void *p) ++{ ++ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) p; ++ /* ++ * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms ++ * so that OPT tests pass with all PHYs). ++ */ ++ hprt0_data_t hprt0 = {.d32 = 0 }; ++#if 0 ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ /* Restart the Phy Clock */ ++ pcgcctl.b.stoppclk = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0); ++ dwc_udelay(10); ++#endif //0 ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ DWC_DEBUGPL(DBG_ANY, "Resume: HPRT0=%0x\n", hprt0.d32); ++// dwc_mdelay(70); ++ hprt0.b.prtres = 0; /* Resume */ ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ DWC_DEBUGPL(DBG_ANY, "Clear Resume: HPRT0=%0x\n", ++ DWC_READ_REG32(core_if->host_if->hprt0)); ++ ++ cil_hcd_resume(core_if); ++ ++ /** Change to L0 state*/ ++ core_if->lx_state = DWC_OTG_L0; ++} ++ ++/** ++ * This interrupt indicates that the DWC_otg controller has detected a ++ * resume or remote wakeup sequence. If the DWC_otg controller is in ++ * low power mode, the handler must brings the controller out of low ++ * power mode. The controller automatically begins resume ++ * signaling. The handler schedules a time to stop resume signaling. ++ */ ++int32_t dwc_otg_handle_wakeup_detected_intr(dwc_otg_core_if_t * core_if) ++{ ++ gintsts_data_t gintsts; ++ ++ DWC_DEBUGPL(DBG_ANY, ++ "++Resume and Remote Wakeup Detected Interrupt++\n"); ++ ++ DWC_PRINTF("%s lxstate = %d\n", __func__, core_if->lx_state); ++ ++ if (dwc_otg_is_device_mode(core_if)) { ++ dctl_data_t dctl = {.d32 = 0 }; ++ DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs-> ++ dsts)); ++ if (core_if->lx_state == DWC_OTG_L2) { ++#ifdef PARTIAL_POWER_DOWN ++ if (core_if->hwcfg4.b.power_optimiz) { ++ pcgcctl_data_t power = {.d32 = 0 }; ++ ++ power.d32 = DWC_READ_REG32(core_if->pcgcctl); ++ DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n", ++ power.d32); ++ ++ power.b.stoppclk = 0; ++ DWC_WRITE_REG32(core_if->pcgcctl, power.d32); ++ ++ power.b.pwrclmp = 0; ++ DWC_WRITE_REG32(core_if->pcgcctl, power.d32); ++ ++ power.b.rstpdwnmodule = 0; ++ DWC_WRITE_REG32(core_if->pcgcctl, power.d32); ++ } ++#endif ++ /* Clear the Remote Wakeup Signaling */ ++ dctl.b.rmtwkupsig = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> ++ dctl, dctl.d32, 0); ++ ++ DWC_SPINUNLOCK(core_if->lock); ++ if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) { ++ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p); ++ } ++ DWC_SPINLOCK(core_if->lock); ++ } else { ++ glpmcfg_data_t lpmcfg; ++ lpmcfg.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++ lpmcfg.b.hird_thres &= (~(1 << 4)); ++ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, ++ lpmcfg.d32); ++ } ++ /** Change to L0 state*/ ++ core_if->lx_state = DWC_OTG_L0; ++ } else { ++ if (core_if->lx_state != DWC_OTG_L1) { ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ ++ /* Restart the Phy Clock */ ++ pcgcctl.b.stoppclk = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0); ++ DWC_TIMER_SCHEDULE(core_if->wkp_timer, 71); ++ } else { ++ /** Change to L0 state*/ ++ core_if->lx_state = DWC_OTG_L0; ++ } ++ } ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.wkupintr = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * This interrupt indicates that the Wakeup Logic has detected a ++ * Device disconnect. ++ */ ++static int32_t dwc_otg_handle_pwrdn_disconnect_intr(dwc_otg_core_if_t *core_if) ++{ ++ gpwrdn_data_t gpwrdn = { .d32 = 0 }; ++ gpwrdn_data_t gpwrdn_temp = { .d32 = 0 }; ++ gpwrdn_temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ ++ DWC_PRINTF("%s called\n", __FUNCTION__); ++ ++ if (!core_if->hibernation_suspend) { ++ DWC_PRINTF("Already exited from Hibernation\n"); ++ return 1; ++ } ++ ++ /* Switch on the voltage to the core */ ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Reset the core */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Disable power clamps*/ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnclmp = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /* Remove reset the core signal */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Disable PMU interrupt */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ core_if->hibernation_suspend = 0; ++ ++ /* Disable PMU */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ if (gpwrdn_temp.b.idsts) { ++ core_if->op_state = B_PERIPHERAL; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_pcd_start(core_if); ++ } else { ++ core_if->op_state = A_HOST; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_hcd_start(core_if); ++ } ++ ++ return 1; ++} ++ ++/** ++ * This interrupt indicates that the Wakeup Logic has detected a ++ * remote wakeup sequence. ++ */ ++static int32_t dwc_otg_handle_pwrdn_wakeup_detected_intr(dwc_otg_core_if_t * core_if) ++{ ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ DWC_DEBUGPL(DBG_ANY, ++ "++Powerdown Remote Wakeup Detected Interrupt++\n"); ++ ++ if (!core_if->hibernation_suspend) { ++ DWC_PRINTF("Already exited from Hibernation\n"); ++ return 1; ++ } ++ ++ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ if (gpwrdn.b.idsts) { // Device Mode ++ if ((core_if->power_down == 2) ++ && (core_if->hibernation_suspend == 1)) { ++ dwc_otg_device_hibernation_restore(core_if, 0, 0); ++ } ++ } else { ++ if ((core_if->power_down == 2) ++ && (core_if->hibernation_suspend == 1)) { ++ dwc_otg_host_hibernation_restore(core_if, 1, 0); ++ } ++ } ++ return 1; ++} ++ ++static int32_t dwc_otg_handle_pwrdn_idsts_change(dwc_otg_device_t *otg_dev) ++{ ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ gpwrdn_data_t gpwrdn_temp = {.d32 = 0 }; ++ dwc_otg_core_if_t *core_if = otg_dev->core_if; ++ ++ DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__); ++ gpwrdn_temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ if (core_if->power_down == 2) { ++ if (!core_if->hibernation_suspend) { ++ DWC_PRINTF("Already exited from Hibernation\n"); ++ return 1; ++ } ++ DWC_DEBUGPL(DBG_ANY, "Exit from hibernation on ID sts change\n"); ++ /* Switch on the voltage to the core */ ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Reset the core */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Disable power clamps */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnclmp = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /* Remove reset the core signal */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Disable PMU interrupt */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /*Indicates that we are exiting from hibernation */ ++ core_if->hibernation_suspend = 0; ++ ++ /* Disable PMU */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ gpwrdn.d32 = core_if->gr_backup->gpwrdn_local; ++ if (gpwrdn.b.dis_vbus == 1) { ++ gpwrdn.d32 = 0; ++ gpwrdn.b.dis_vbus = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ } ++ ++ if (gpwrdn_temp.b.idsts) { ++ core_if->op_state = B_PERIPHERAL; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_pcd_start(core_if); ++ } else { ++ core_if->op_state = A_HOST; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_hcd_start(core_if); ++ } ++ } ++ ++ if (core_if->adp_enable) { ++ uint8_t is_host = 0; ++ DWC_SPINUNLOCK(core_if->lock); ++ /* Change the core_if's lock to hcd/pcd lock depend on mode? */ ++#ifndef DWC_HOST_ONLY ++ if (gpwrdn_temp.b.idsts) ++ core_if->lock = otg_dev->pcd->lock; ++#endif ++#ifndef DWC_DEVICE_ONLY ++ if (!gpwrdn_temp.b.idsts) { ++ core_if->lock = otg_dev->hcd->lock; ++ is_host = 1; ++ } ++#endif ++ DWC_PRINTF("RESTART ADP\n"); ++ if (core_if->adp.probe_enabled) ++ dwc_otg_adp_probe_stop(core_if); ++ if (core_if->adp.sense_enabled) ++ dwc_otg_adp_sense_stop(core_if); ++ if (core_if->adp.sense_timer_started) ++ DWC_TIMER_CANCEL(core_if->adp.sense_timer); ++ if (core_if->adp.vbuson_timer_started) ++ DWC_TIMER_CANCEL(core_if->adp.vbuson_timer); ++ core_if->adp.probe_timer_values[0] = -1; ++ core_if->adp.probe_timer_values[1] = -1; ++ core_if->adp.sense_timer_started = 0; ++ core_if->adp.vbuson_timer_started = 0; ++ core_if->adp.probe_counter = 0; ++ core_if->adp.gpwrdn = 0; ++ ++ /* Disable PMU and restart ADP */ ++ gpwrdn_temp.d32 = 0; ++ gpwrdn_temp.b.pmuactv = 1; ++ gpwrdn_temp.b.pmuintsel = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ DWC_PRINTF("Check point 1\n"); ++ dwc_mdelay(110); ++ dwc_otg_adp_start(core_if, is_host); ++ DWC_SPINLOCK(core_if->lock); ++ } ++ ++ ++ return 1; ++} ++ ++static int32_t dwc_otg_handle_pwrdn_session_change(dwc_otg_core_if_t * core_if) ++{ ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ int32_t otg_cap_param = core_if->core_params->otg_cap; ++ DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__); ++ ++ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ if (core_if->power_down == 2) { ++ if (!core_if->hibernation_suspend) { ++ DWC_PRINTF("Already exited from Hibernation\n"); ++ return 1; ++ } ++ ++ if ((otg_cap_param != DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE || ++ otg_cap_param != DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE) && ++ gpwrdn.b.bsessvld == 0) { ++ /* Save gpwrdn register for further usage if stschng interrupt */ ++ core_if->gr_backup->gpwrdn_local = ++ DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ /*Exit from ISR and wait for stschng interrupt with bsessvld = 1 */ ++ return 1; ++ } ++ ++ /* Switch on the voltage to the core */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Reset the core */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Disable power clamps */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnclmp = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /* Remove reset the core signal */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Disable PMU interrupt */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /*Indicates that we are exiting from hibernation */ ++ core_if->hibernation_suspend = 0; ++ ++ /* Disable PMU */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ core_if->op_state = B_PERIPHERAL; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_pcd_start(core_if); ++ ++ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE || ++ otg_cap_param == DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE) { ++ /* ++ * Initiate SRP after initial ADP probe. ++ */ ++ dwc_otg_initiate_srp(core_if); ++ } ++ } ++ ++ return 1; ++} ++/** ++ * This interrupt indicates that the Wakeup Logic has detected a ++ * status change either on IDDIG or BSessVld. ++ */ ++static uint32_t dwc_otg_handle_pwrdn_stschng_intr(dwc_otg_device_t *otg_dev) ++{ ++ int retval; ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ gpwrdn_data_t gpwrdn_temp = {.d32 = 0 }; ++ dwc_otg_core_if_t *core_if = otg_dev->core_if; ++ ++ DWC_PRINTF("%s called\n", __FUNCTION__); ++ ++ if (core_if->power_down == 2) { ++ if (core_if->hibernation_suspend <= 0) { ++ DWC_PRINTF("Already exited from Hibernation\n"); ++ return 1; ++ } else ++ gpwrdn_temp.d32 = core_if->gr_backup->gpwrdn_local; ++ ++ } else { ++ gpwrdn_temp.d32 = core_if->adp.gpwrdn; ++ } ++ ++ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ ++ if (gpwrdn.b.idsts ^ gpwrdn_temp.b.idsts) { ++ retval = dwc_otg_handle_pwrdn_idsts_change(otg_dev); ++ } else if (gpwrdn.b.bsessvld ^ gpwrdn_temp.b.bsessvld) { ++ retval = dwc_otg_handle_pwrdn_session_change(core_if); ++ } ++ ++ return retval; ++} ++ ++/** ++ * This interrupt indicates that the Wakeup Logic has detected a ++ * SRP. ++ */ ++static int32_t dwc_otg_handle_pwrdn_srp_intr(dwc_otg_core_if_t * core_if) ++{ ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ ++ DWC_PRINTF("%s called\n", __FUNCTION__); ++ ++ if (!core_if->hibernation_suspend) { ++ DWC_PRINTF("Already exited from Hibernation\n"); ++ return 1; ++ } ++#ifdef DWC_DEV_SRPCAP ++ if (core_if->pwron_timer_started) { ++ core_if->pwron_timer_started = 0; ++ DWC_TIMER_CANCEL(core_if->pwron_timer); ++ } ++#endif ++ ++ /* Switch on the voltage to the core */ ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Reset the core */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Disable power clamps */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnclmp = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /* Remove reset the core signal */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Disable PMU interrupt */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /* Indicates that we are exiting from hibernation */ ++ core_if->hibernation_suspend = 0; ++ ++ /* Disable PMU */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Programm Disable VBUS to 0 */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.dis_vbus = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /*Initialize the core as Host */ ++ core_if->op_state = A_HOST; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_hcd_start(core_if); ++ ++ return 1; ++} ++ ++/** This interrupt indicates that restore command after Hibernation ++ * was completed by the core. */ ++int32_t dwc_otg_handle_restore_done_intr(dwc_otg_core_if_t * core_if) ++{ ++ pcgcctl_data_t pcgcctl; ++ DWC_DEBUGPL(DBG_ANY, "++Restore Done Interrupt++\n"); ++ ++ //TODO De-assert restore signal. 8.a ++ pcgcctl.d32 = DWC_READ_REG32(core_if->pcgcctl); ++ if (pcgcctl.b.restoremode == 1) { ++ gintmsk_data_t gintmsk = {.d32 = 0 }; ++ /* ++ * If restore mode is Remote Wakeup, ++ * unmask Remote Wakeup interrupt. ++ */ ++ gintmsk.b.wkupintr = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, ++ 0, gintmsk.d32); ++ } ++ ++ return 1; ++} ++ ++/** ++ * This interrupt indicates that a device has been disconnected from ++ * the root port. ++ */ ++int32_t dwc_otg_handle_disconnect_intr(dwc_otg_core_if_t * core_if) ++{ ++ gintsts_data_t gintsts; ++ ++ DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n", ++ (dwc_otg_is_host_mode(core_if) ? "Host" : "Device"), ++ op_state_str(core_if)); ++ ++/** @todo Consolidate this if statement. */ ++#ifndef DWC_HOST_ONLY ++ if (core_if->op_state == B_HOST) { ++ /* If in device mode Disconnect and stop the HCD, then ++ * start the PCD. */ ++ DWC_SPINUNLOCK(core_if->lock); ++ cil_hcd_disconnect(core_if); ++ cil_pcd_start(core_if); ++ DWC_SPINLOCK(core_if->lock); ++ core_if->op_state = B_PERIPHERAL; ++ } else if (dwc_otg_is_device_mode(core_if)) { ++ gotgctl_data_t gotgctl = {.d32 = 0 }; ++ gotgctl.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->gotgctl); ++ if (gotgctl.b.hstsethnpen == 1) { ++ /* Do nothing, if HNP in process the OTG ++ * interrupt "Host Negotiation Detected" ++ * interrupt will do the mode switch. ++ */ ++ } else if (gotgctl.b.devhnpen == 0) { ++ /* If in device mode Disconnect and stop the HCD, then ++ * start the PCD. */ ++ DWC_SPINUNLOCK(core_if->lock); ++ cil_hcd_disconnect(core_if); ++ cil_pcd_start(core_if); ++ DWC_SPINLOCK(core_if->lock); ++ core_if->op_state = B_PERIPHERAL; ++ } else { ++ DWC_DEBUGPL(DBG_ANY, "!a_peripheral && !devhnpen\n"); ++ } ++ } else { ++ if (core_if->op_state == A_HOST) { ++ /* A-Cable still connected but device disconnected. */ ++ cil_hcd_disconnect(core_if); ++ if (core_if->adp_enable) { ++ gpwrdn_data_t gpwrdn = { .d32 = 0 }; ++ cil_hcd_stop(core_if); ++ /* Enable Power Down Logic */ ++ gpwrdn.b.pmuintsel = 1; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ dwc_otg_adp_probe_start(core_if); ++ ++ /* Power off the core */ ++ if (core_if->power_down == 2) { ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32 ++ (&core_if->core_global_regs->gpwrdn, ++ gpwrdn.d32, 0); ++ } ++ } ++ } ++ } ++#endif ++ /* Change to L3(OFF) state */ ++ core_if->lx_state = DWC_OTG_L3; ++ ++ gintsts.d32 = 0; ++ gintsts.b.disconnect = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ return 1; ++} ++ ++/** ++ * This interrupt indicates that SUSPEND state has been detected on ++ * the USB. ++ * ++ * For HNP the USB Suspend interrupt signals the change from ++ * "a_peripheral" to "a_host". ++ * ++ * When power management is enabled the core will be put in low power ++ * mode. ++ */ ++int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t * core_if) ++{ ++ dsts_data_t dsts; ++ gintsts_data_t gintsts; ++ dcfg_data_t dcfg; ++ ++ DWC_DEBUGPL(DBG_ANY, "USB SUSPEND\n"); ++ ++ if (dwc_otg_is_device_mode(core_if)) { ++ /* Check the Device status register to determine if the Suspend ++ * state is active. */ ++ dsts.d32 = ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); ++ DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32); ++ DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d " ++ "HWCFG4.power Optimize=%d\n", ++ dsts.b.suspsts, core_if->hwcfg4.b.power_optimiz); ++ ++#ifdef PARTIAL_POWER_DOWN ++/** @todo Add a module parameter for power management. */ ++ ++ if (dsts.b.suspsts && core_if->hwcfg4.b.power_optimiz) { ++ pcgcctl_data_t power = {.d32 = 0 }; ++ DWC_DEBUGPL(DBG_CIL, "suspend\n"); ++ ++ power.b.pwrclmp = 1; ++ DWC_WRITE_REG32(core_if->pcgcctl, power.d32); ++ ++ power.b.rstpdwnmodule = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, power.d32); ++ ++ power.b.stoppclk = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, power.d32); ++ ++ } else { ++ DWC_DEBUGPL(DBG_ANY, "disconnect?\n"); ++ } ++#endif ++ /* PCD callback for suspend. Release the lock inside of callback function */ ++ cil_pcd_suspend(core_if); ++ if (core_if->power_down == 2) ++ { ++ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); ++ DWC_DEBUGPL(DBG_ANY,"lx_state = %08x\n",core_if->lx_state); ++ DWC_DEBUGPL(DBG_ANY," device address = %08d\n",dcfg.b.devaddr); ++ ++ if (core_if->lx_state != DWC_OTG_L3 && dcfg.b.devaddr) { ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ gusbcfg_data_t gusbcfg = {.d32 = 0 }; ++ ++ /* Change to L2(suspend) state */ ++ core_if->lx_state = DWC_OTG_L2; ++ ++ /* Clear interrupt in gintsts */ ++ gintsts.d32 = 0; ++ gintsts.b.usbsuspend = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs-> ++ gintsts, gintsts.d32); ++ DWC_PRINTF("Start of hibernation completed\n"); ++ dwc_otg_save_global_regs(core_if); ++ dwc_otg_save_dev_regs(core_if); ++ ++ gusbcfg.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs-> ++ gusbcfg); ++ if (gusbcfg.b.ulpi_utmi_sel == 1) { ++ /* ULPI interface */ ++ /* Suspend the Phy Clock */ ++ pcgcctl.d32 = 0; ++ pcgcctl.b.stoppclk = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, ++ pcgcctl.d32); ++ dwc_udelay(10); ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if-> ++ core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ } else { ++ /* UTMI+ Interface */ ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if-> ++ core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ pcgcctl.b.stoppclk = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, ++ pcgcctl.d32); ++ dwc_udelay(10); ++ } ++ ++ /* Set flag to indicate that we are in hibernation */ ++ core_if->hibernation_suspend = 1; ++ /* Enable interrupts from wake up logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Unmask device mode interrupts in GPWRDN */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.rst_det_msk = 1; ++ gpwrdn.b.lnstchng_msk = 1; ++ gpwrdn.b.sts_chngint_msk = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Enable Power Down Clamp */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnclmp = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Switch off VDD */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ ++ /* Save gpwrdn register for further usage if stschng interrupt */ ++ core_if->gr_backup->gpwrdn_local = ++ DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ DWC_PRINTF("Hibernation completed\n"); ++ ++ return 1; ++ } ++ } else if (core_if->power_down == 3) { ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); ++ DWC_DEBUGPL(DBG_ANY, "lx_state = %08x\n",core_if->lx_state); ++ DWC_DEBUGPL(DBG_ANY, " device address = %08d\n",dcfg.b.devaddr); ++ ++ if (core_if->lx_state != DWC_OTG_L3 && dcfg.b.devaddr) { ++ DWC_DEBUGPL(DBG_ANY, "Start entering to extended hibernation\n"); ++ core_if->xhib = 1; ++ ++ /* Clear interrupt in gintsts */ ++ gintsts.d32 = 0; ++ gintsts.b.usbsuspend = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs-> ++ gintsts, gintsts.d32); ++ ++ dwc_otg_save_global_regs(core_if); ++ dwc_otg_save_dev_regs(core_if); ++ ++ /* Wait for 10 PHY clocks */ ++ dwc_udelay(10); ++ ++ /* Program GPIO register while entering to xHib */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, 0x1); ++ ++ pcgcctl.b.enbl_extnd_hiber = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32); ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32); ++ ++ pcgcctl.d32 = 0; ++ pcgcctl.b.extnd_hiber_pwrclmp = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32); ++ ++ pcgcctl.d32 = 0; ++ pcgcctl.b.extnd_hiber_switch = 1; ++ core_if->gr_backup->xhib_gpwrdn = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ core_if->gr_backup->xhib_pcgcctl = DWC_READ_REG32(core_if->pcgcctl) | pcgcctl.d32; ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32); ++ ++ DWC_DEBUGPL(DBG_ANY, "Finished entering to extended hibernation\n"); ++ ++ return 1; ++ } ++ } ++ } else { ++ if (core_if->op_state == A_PERIPHERAL) { ++ DWC_DEBUGPL(DBG_ANY, "a_peripheral->a_host\n"); ++ /* Clear the a_peripheral flag, back to a_host. */ ++ DWC_SPINUNLOCK(core_if->lock); ++ cil_pcd_stop(core_if); ++ cil_hcd_start(core_if); ++ DWC_SPINLOCK(core_if->lock); ++ core_if->op_state = A_HOST; ++ } ++ } ++ ++ /* Change to L2(suspend) state */ ++ core_if->lx_state = DWC_OTG_L2; ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.usbsuspend = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ return 1; ++} ++ ++static int32_t dwc_otg_handle_xhib_exit_intr(dwc_otg_core_if_t * core_if) ++{ ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ gahbcfg_data_t gahbcfg = {.d32 = 0 }; ++ ++ dwc_udelay(10); ++ ++ /* Program GPIO register while entering to xHib */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, 0x0); ++ ++ pcgcctl.d32 = core_if->gr_backup->xhib_pcgcctl; ++ pcgcctl.b.extnd_hiber_pwrclmp = 0; ++ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32); ++ dwc_udelay(10); ++ ++ gpwrdn.d32 = core_if->gr_backup->xhib_gpwrdn; ++ gpwrdn.b.restore = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ restore_lpm_i2c_regs(core_if); ++ ++ pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14); ++ pcgcctl.b.max_xcvrselect = 1; ++ pcgcctl.b.ess_reg_restored = 0; ++ pcgcctl.b.extnd_hiber_switch = 0; ++ pcgcctl.b.extnd_hiber_pwrclmp = 0; ++ pcgcctl.b.enbl_extnd_hiber = 1; ++ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32); ++ ++ gahbcfg.d32 = core_if->gr_backup->gahbcfg_local; ++ gahbcfg.b.glblintrmsk = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gahbcfg.d32); ++ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0x1 << 16); ++ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, ++ core_if->gr_backup->gusbcfg_local); ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, ++ core_if->dr_backup->dcfg); ++ ++ pcgcctl.d32 = 0; ++ pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14); ++ pcgcctl.b.max_xcvrselect = 1; ++ pcgcctl.d32 |= 0x608; ++ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32); ++ dwc_udelay(10); ++ ++ pcgcctl.d32 = 0; ++ pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14); ++ pcgcctl.b.max_xcvrselect = 1; ++ pcgcctl.b.ess_reg_restored = 1; ++ pcgcctl.b.enbl_extnd_hiber = 1; ++ pcgcctl.b.rstpdwnmodule = 1; ++ pcgcctl.b.restoremode = 1; ++ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32); ++ ++ DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__); ++ ++ return 1; ++} ++ ++#ifdef CONFIG_USB_DWC_OTG_LPM ++/** ++ * This function hadles LPM transaction received interrupt. ++ */ ++static int32_t dwc_otg_handle_lpm_intr(dwc_otg_core_if_t * core_if) ++{ ++ glpmcfg_data_t lpmcfg; ++ gintsts_data_t gintsts; ++ ++ if (!core_if->core_params->lpm_enable) { ++ DWC_PRINTF("Unexpected LPM interrupt\n"); ++ } ++ ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++ DWC_PRINTF("LPM config register = 0x%08x\n", lpmcfg.d32); ++ ++ if (dwc_otg_is_host_mode(core_if)) { ++ cil_hcd_sleep(core_if); ++ } else { ++ lpmcfg.b.hird_thres |= (1 << 4); ++ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, ++ lpmcfg.d32); ++ } ++ ++ /* Examine prt_sleep_sts after TL1TokenTetry period max (10 us) */ ++ dwc_udelay(10); ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++ if (lpmcfg.b.prt_sleep_sts) { ++ /* Save the current state */ ++ core_if->lx_state = DWC_OTG_L1; ++ } ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.lpmtranrcvd = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ return 1; ++} ++#endif /* CONFIG_USB_DWC_OTG_LPM */ ++ ++/** ++ * This function returns the Core Interrupt register. ++ */ ++static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t * core_if, gintmsk_data_t *reenable_gintmsk, dwc_otg_hcd_t *hcd) ++{ ++ gahbcfg_data_t gahbcfg = {.d32 = 0 }; ++ gintsts_data_t gintsts; ++ gintmsk_data_t gintmsk; ++ gintmsk_data_t gintmsk_common = {.d32 = 0 }; ++ gintmsk_common.b.wkupintr = 1; ++ gintmsk_common.b.sessreqintr = 1; ++ gintmsk_common.b.conidstschng = 1; ++ gintmsk_common.b.otgintr = 1; ++ gintmsk_common.b.modemismatch = 1; ++ gintmsk_common.b.disconnect = 1; ++ gintmsk_common.b.usbsuspend = 1; ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ gintmsk_common.b.lpmtranrcvd = 1; ++#endif ++ gintmsk_common.b.restoredone = 1; ++ if(dwc_otg_is_device_mode(core_if)) ++ { ++ /** @todo: The port interrupt occurs while in device ++ * mode. Added code to CIL to clear the interrupt for now! ++ */ ++ gintmsk_common.b.portintr = 1; ++ } ++ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts); ++ gintmsk.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk); ++ if(fiq_enable) { ++ local_fiq_disable(); ++ /* Pull in the interrupts that the FIQ has masked */ ++ gintmsk.d32 |= ~(hcd->fiq_state->gintmsk_saved.d32); ++ gintmsk.d32 |= gintmsk_common.d32; ++ /* for the upstairs function to reenable - have to read it here in case FIQ triggers again */ ++ reenable_gintmsk->d32 = gintmsk.d32; ++ local_fiq_enable(); ++ } ++ ++ gahbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg); ++ ++#ifdef DEBUG ++ /* if any common interrupts set */ ++ if (gintsts.d32 & gintmsk_common.d32) { ++ DWC_DEBUGPL(DBG_ANY, "common_intr: gintsts=%08x gintmsk=%08x\n", ++ gintsts.d32, gintmsk.d32); ++ } ++#endif ++ if (!fiq_enable){ ++ if (gahbcfg.b.glblintrmsk) ++ return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32); ++ else ++ return 0; ++ } else { ++ /* Our IRQ kicker is no longer the USB hardware, it's the MPHI interface. ++ * Can't trust the global interrupt mask bit in this case. ++ */ ++ return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32); ++ } ++ ++} ++ ++/* MACRO for clearing interupt bits in GPWRDN register */ ++#define CLEAR_GPWRDN_INTR(__core_if,__intr) \ ++do { \ ++ gpwrdn_data_t gpwrdn = {.d32=0}; \ ++ gpwrdn.b.__intr = 1; \ ++ DWC_MODIFY_REG32(&__core_if->core_global_regs->gpwrdn, \ ++ 0, gpwrdn.d32); \ ++} while (0) ++ ++/** ++ * Common interrupt handler. ++ * ++ * The common interrupts are those that occur in both Host and Device mode. ++ * This handler handles the following interrupts: ++ * - Mode Mismatch Interrupt ++ * - Disconnect Interrupt ++ * - OTG Interrupt ++ * - Connector ID Status Change Interrupt ++ * - Session Request Interrupt. ++ * - Resume / Remote Wakeup Detected Interrupt. ++ * - LPM Transaction Received Interrupt ++ * - ADP Transaction Received Interrupt ++ * ++ */ ++int32_t dwc_otg_handle_common_intr(void *dev) ++{ ++ int retval = 0; ++ gintsts_data_t gintsts; ++ gintmsk_data_t gintmsk_reenable = { .d32 = 0 }; ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ dwc_otg_device_t *otg_dev = dev; ++ dwc_otg_core_if_t *core_if = otg_dev->core_if; ++ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ if (dwc_otg_is_device_mode(core_if)) ++ core_if->frame_num = dwc_otg_get_frame_number(core_if); ++ ++ if (core_if->lock) ++ DWC_SPINLOCK(core_if->lock); ++ ++ if (core_if->power_down == 3 && core_if->xhib == 1) { ++ DWC_DEBUGPL(DBG_ANY, "Exiting from xHIB state\n"); ++ retval |= dwc_otg_handle_xhib_exit_intr(core_if); ++ core_if->xhib = 2; ++ if (core_if->lock) ++ DWC_SPINUNLOCK(core_if->lock); ++ ++ return retval; ++ } ++ ++ if (core_if->hibernation_suspend <= 0) { ++ /* read_common will have to poke the FIQ's saved mask. We must then clear this mask at the end ++ * of this handler - god only knows why it's done like this ++ */ ++ gintsts.d32 = dwc_otg_read_common_intr(core_if, &gintmsk_reenable, otg_dev->hcd); ++ ++ if (gintsts.b.modemismatch) { ++ retval |= dwc_otg_handle_mode_mismatch_intr(core_if); ++ } ++ if (gintsts.b.otgintr) { ++ retval |= dwc_otg_handle_otg_intr(core_if); ++ } ++ if (gintsts.b.conidstschng) { ++ retval |= ++ dwc_otg_handle_conn_id_status_change_intr(core_if); ++ } ++ if (gintsts.b.disconnect) { ++ retval |= dwc_otg_handle_disconnect_intr(core_if); ++ } ++ if (gintsts.b.sessreqintr) { ++ retval |= dwc_otg_handle_session_req_intr(core_if); ++ } ++ if (gintsts.b.wkupintr) { ++ retval |= dwc_otg_handle_wakeup_detected_intr(core_if); ++ } ++ if (gintsts.b.usbsuspend) { ++ retval |= dwc_otg_handle_usb_suspend_intr(core_if); ++ } ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ if (gintsts.b.lpmtranrcvd) { ++ retval |= dwc_otg_handle_lpm_intr(core_if); ++ } ++#endif ++ if (gintsts.b.restoredone) { ++ gintsts.d32 = 0; ++ if (core_if->power_down == 2) ++ core_if->hibernation_suspend = -1; ++ else if (core_if->power_down == 3 && core_if->xhib == 2) { ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ dctl_data_t dctl = {.d32 = 0 }; ++ ++ DWC_WRITE_REG32(&core_if->core_global_regs-> ++ gintsts, 0xFFFFFFFF); ++ ++ DWC_DEBUGPL(DBG_ANY, ++ "RESTORE DONE generated\n"); ++ ++ gpwrdn.b.restore = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ pcgcctl.b.rstpdwnmodule = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0); ++ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, core_if->gr_backup->gusbcfg_local); ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, core_if->dr_backup->dcfg); ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, core_if->dr_backup->dctl); ++ dwc_udelay(50); ++ ++ dctl.b.pwronprgdone = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32); ++ dwc_udelay(10); ++ ++ dwc_otg_restore_global_regs(core_if); ++ dwc_otg_restore_dev_regs(core_if, 0); ++ ++ dctl.d32 = 0; ++ dctl.b.pwronprgdone = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0); ++ dwc_udelay(10); ++ ++ pcgcctl.d32 = 0; ++ pcgcctl.b.enbl_extnd_hiber = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0); ++ ++ /* The core will be in ON STATE */ ++ core_if->lx_state = DWC_OTG_L0; ++ core_if->xhib = 0; ++ ++ DWC_SPINUNLOCK(core_if->lock); ++ if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) { ++ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p); ++ } ++ DWC_SPINLOCK(core_if->lock); ++ ++ } ++ ++ gintsts.b.restoredone = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32); ++ DWC_PRINTF(" --Restore done interrupt received-- \n"); ++ retval |= 1; ++ } ++ if (gintsts.b.portintr && dwc_otg_is_device_mode(core_if)) { ++ /* The port interrupt occurs while in device mode with HPRT0 ++ * Port Enable/Disable. ++ */ ++ gintsts.d32 = 0; ++ gintsts.b.portintr = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32); ++ retval |= 1; ++ gintmsk_reenable.b.portintr = 1; ++ ++ } ++ /* Did we actually handle anything? if so, unmask the interrupt */ ++// fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "CILOUT %1d", retval); ++// fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "%08x", gintsts.d32); ++// fiq_print(FIQDBG_INT, otg_dev->hcd->fiq_state, "%08x", gintmsk_reenable.d32); ++ if (retval && fiq_enable) { ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk_reenable.d32); ++ } ++ ++ } else { ++ DWC_DEBUGPL(DBG_ANY, "gpwrdn=%08x\n", gpwrdn.d32); ++ ++ if (gpwrdn.b.disconn_det && gpwrdn.b.disconn_det_msk) { ++ CLEAR_GPWRDN_INTR(core_if, disconn_det); ++ if (gpwrdn.b.linestate == 0) { ++ dwc_otg_handle_pwrdn_disconnect_intr(core_if); ++ } else { ++ DWC_PRINTF("Disconnect detected while linestate is not 0\n"); ++ } ++ ++ retval |= 1; ++ } ++ if (gpwrdn.b.lnstschng && gpwrdn.b.lnstchng_msk) { ++ CLEAR_GPWRDN_INTR(core_if, lnstschng); ++ /* remote wakeup from hibernation */ ++ if (gpwrdn.b.linestate == 2 || gpwrdn.b.linestate == 1) { ++ dwc_otg_handle_pwrdn_wakeup_detected_intr(core_if); ++ } else { ++ DWC_PRINTF("gpwrdn.linestate = %d\n", gpwrdn.b.linestate); ++ } ++ retval |= 1; ++ } ++ if (gpwrdn.b.rst_det && gpwrdn.b.rst_det_msk) { ++ CLEAR_GPWRDN_INTR(core_if, rst_det); ++ if (gpwrdn.b.linestate == 0) { ++ DWC_PRINTF("Reset detected\n"); ++ retval |= dwc_otg_device_hibernation_restore(core_if, 0, 1); ++ } ++ } ++ if (gpwrdn.b.srp_det && gpwrdn.b.srp_det_msk) { ++ CLEAR_GPWRDN_INTR(core_if, srp_det); ++ dwc_otg_handle_pwrdn_srp_intr(core_if); ++ retval |= 1; ++ } ++ } ++ /* Handle ADP interrupt here */ ++ if (gpwrdn.b.adp_int) { ++ DWC_PRINTF("ADP interrupt\n"); ++ CLEAR_GPWRDN_INTR(core_if, adp_int); ++ dwc_otg_adp_handle_intr(core_if); ++ retval |= 1; ++ } ++ if (gpwrdn.b.sts_chngint && gpwrdn.b.sts_chngint_msk) { ++ DWC_PRINTF("STS CHNG interrupt asserted\n"); ++ CLEAR_GPWRDN_INTR(core_if, sts_chngint); ++ dwc_otg_handle_pwrdn_stschng_intr(otg_dev); ++ ++ retval |= 1; ++ } ++ if (core_if->lock) ++ DWC_SPINUNLOCK(core_if->lock); ++ return retval; ++} +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_core_if.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_core_if.h +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_core_if.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_core_if.h 2015-11-29 09:42:39.919098694 +0100 +@@ -0,0 +1,705 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_core_if.h $ ++ * $Revision: #13 $ ++ * $Date: 2012/08/10 $ ++ * $Change: 2047372 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#if !defined(__DWC_CORE_IF_H__) ++#define __DWC_CORE_IF_H__ ++ ++#include "dwc_os.h" ++ ++/** @file ++ * This file defines DWC_OTG Core API ++ */ ++ ++struct dwc_otg_core_if; ++typedef struct dwc_otg_core_if dwc_otg_core_if_t; ++ ++/** Maximum number of Periodic FIFOs */ ++#define MAX_PERIO_FIFOS 15 ++/** Maximum number of Periodic FIFOs */ ++#define MAX_TX_FIFOS 15 ++ ++/** Maximum number of Endpoints/HostChannels */ ++#define MAX_EPS_CHANNELS 16 ++ ++extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * _reg_base_addr); ++extern void dwc_otg_core_init(dwc_otg_core_if_t * _core_if); ++extern void dwc_otg_cil_remove(dwc_otg_core_if_t * _core_if); ++ ++extern void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * _core_if); ++extern void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * _core_if); ++ ++extern uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if); ++extern uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if); ++ ++extern uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if); ++ ++/** This function should be called on every hardware interrupt. */ ++extern int32_t dwc_otg_handle_common_intr(void *otg_dev); ++ ++/** @name OTG Core Parameters */ ++/** @{ */ ++ ++/** ++ * Specifies the OTG capabilities. The driver will automatically ++ * detect the value for this parameter if none is specified. ++ * 0 - HNP and SRP capable (default) ++ * 1 - SRP Only capable ++ * 2 - No HNP/SRP capable ++ */ ++extern int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val); ++extern int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if); ++#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0 ++#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1 ++#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 ++#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE ++ ++extern int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val); ++extern int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if); ++#define dwc_param_opt_default 1 ++ ++/** ++ * Specifies whether to use slave or DMA mode for accessing the data ++ * FIFOs. The driver will automatically detect the value for this ++ * parameter if none is specified. ++ * 0 - Slave ++ * 1 - DMA (default, if available) ++ */ ++extern int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if); ++#define dwc_param_dma_enable_default 1 ++ ++/** ++ * When DMA mode is enabled specifies whether to use ++ * address DMA or DMA Descritor mode for accessing the data ++ * FIFOs in device mode. The driver will automatically detect ++ * the value for this parameter if none is specified. ++ * 0 - address DMA ++ * 1 - DMA Descriptor(default, if available) ++ */ ++extern int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if); ++//#define dwc_param_dma_desc_enable_default 1 ++#define dwc_param_dma_desc_enable_default 0 // Broadcom BCM2708 ++ ++/** The DMA Burst size (applicable only for External DMA ++ * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32) ++ */ ++extern int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if); ++#define dwc_param_dma_burst_size_default 32 ++ ++/** ++ * Specifies the maximum speed of operation in host and device mode. ++ * The actual speed depends on the speed of the attached device and ++ * the value of phy_type. The actual speed depends on the speed of the ++ * attached device. ++ * 0 - High Speed (default) ++ * 1 - Full Speed ++ */ ++extern int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val); ++extern int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if); ++#define dwc_param_speed_default 0 ++#define DWC_SPEED_PARAM_HIGH 0 ++#define DWC_SPEED_PARAM_FULL 1 ++ ++/** Specifies whether low power mode is supported when attached ++ * to a Full Speed or Low Speed device in host mode. ++ * 0 - Don't support low power mode (default) ++ * 1 - Support low power mode ++ */ ++extern int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t * ++ core_if, int32_t val); ++extern int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t ++ * core_if); ++#define dwc_param_host_support_fs_ls_low_power_default 0 ++ ++/** Specifies the PHY clock rate in low power mode when connected to a ++ * Low Speed device in host mode. This parameter is applicable only if ++ * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS ++ * then defaults to 6 MHZ otherwise 48 MHZ. ++ * ++ * 0 - 48 MHz ++ * 1 - 6 MHz ++ */ ++extern int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * ++ core_if, int32_t val); ++extern int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * ++ core_if); ++#define dwc_param_host_ls_low_power_phy_clk_default 0 ++#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 ++#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 ++ ++/** ++ * 0 - Use cC FIFO size parameters ++ * 1 - Allow dynamic FIFO sizing (default) ++ */ ++extern int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t * ++ core_if); ++#define dwc_param_enable_dynamic_fifo_default 1 ++ ++/** Total number of 4-byte words in the data FIFO memory. This ++ * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic ++ * Tx FIFOs. ++ * 32 to 32768 (default 8192) ++ * Note: The total FIFO memory depth in the FPGA configuration is 8192. ++ */ ++extern int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if); ++//#define dwc_param_data_fifo_size_default 8192 ++#define dwc_param_data_fifo_size_default 0xFF0 // Broadcom BCM2708 ++ ++/** Number of 4-byte words in the Rx FIFO in device mode when dynamic ++ * FIFO sizing is enabled. ++ * 16 to 32768 (default 1064) ++ */ ++extern int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if); ++#define dwc_param_dev_rx_fifo_size_default 1064 ++ ++/** Number of 4-byte words in the non-periodic Tx FIFO in device mode ++ * when dynamic FIFO sizing is enabled. ++ * 16 to 32768 (default 1024) ++ */ ++extern int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * ++ core_if, int32_t val); ++extern int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * ++ core_if); ++#define dwc_param_dev_nperio_tx_fifo_size_default 1024 ++ ++/** Number of 4-byte words in each of the periodic Tx FIFOs in device ++ * mode when dynamic FIFO sizing is enabled. ++ * 4 to 768 (default 256) ++ */ ++extern int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if, ++ int32_t val, int fifo_num); ++extern int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * ++ core_if, int fifo_num); ++#define dwc_param_dev_perio_tx_fifo_size_default 256 ++ ++/** Number of 4-byte words in the Rx FIFO in host mode when dynamic ++ * FIFO sizing is enabled. ++ * 16 to 32768 (default 1024) ++ */ ++extern int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if); ++//#define dwc_param_host_rx_fifo_size_default 1024 ++#define dwc_param_host_rx_fifo_size_default 774 // Broadcom BCM2708 ++ ++/** Number of 4-byte words in the non-periodic Tx FIFO in host mode ++ * when Dynamic FIFO sizing is enabled in the core. ++ * 16 to 32768 (default 1024) ++ */ ++extern int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * ++ core_if, int32_t val); ++extern int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * ++ core_if); ++//#define dwc_param_host_nperio_tx_fifo_size_default 1024 ++#define dwc_param_host_nperio_tx_fifo_size_default 0x100 // Broadcom BCM2708 ++ ++/** Number of 4-byte words in the host periodic Tx FIFO when dynamic ++ * FIFO sizing is enabled. ++ * 16 to 32768 (default 1024) ++ */ ++extern int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * ++ core_if, int32_t val); ++extern int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * ++ core_if); ++//#define dwc_param_host_perio_tx_fifo_size_default 1024 ++#define dwc_param_host_perio_tx_fifo_size_default 0x200 // Broadcom BCM2708 ++ ++/** The maximum transfer size supported in bytes. ++ * 2047 to 65,535 (default 65,535) ++ */ ++extern int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if); ++#define dwc_param_max_transfer_size_default 65535 ++ ++/** The maximum number of packets in a transfer. ++ * 15 to 511 (default 511) ++ */ ++extern int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if); ++#define dwc_param_max_packet_count_default 511 ++ ++/** The number of host channel registers to use. ++ * 1 to 16 (default 12) ++ * Note: The FPGA configuration supports a maximum of 12 host channels. ++ */ ++extern int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if); ++//#define dwc_param_host_channels_default 12 ++#define dwc_param_host_channels_default 8 // Broadcom BCM2708 ++ ++/** The number of endpoints in addition to EP0 available for device ++ * mode operations. ++ * 1 to 15 (default 6 IN and OUT) ++ * Note: The FPGA configuration supports a maximum of 6 IN and OUT ++ * endpoints in addition to EP0. ++ */ ++extern int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if); ++#define dwc_param_dev_endpoints_default 6 ++ ++/** ++ * Specifies the type of PHY interface to use. By default, the driver ++ * will automatically detect the phy_type. ++ * ++ * 0 - Full Speed PHY ++ * 1 - UTMI+ (default) ++ * 2 - ULPI ++ */ ++extern int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val); ++extern int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if); ++#define DWC_PHY_TYPE_PARAM_FS 0 ++#define DWC_PHY_TYPE_PARAM_UTMI 1 ++#define DWC_PHY_TYPE_PARAM_ULPI 2 ++#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI ++ ++/** ++ * Specifies the UTMI+ Data Width. This parameter is ++ * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI ++ * PHY_TYPE, this parameter indicates the data width between ++ * the MAC and the ULPI Wrapper.) Also, this parameter is ++ * applicable only if the OTG_HSPHY_WIDTH cC parameter was set ++ * to "8 and 16 bits", meaning that the core has been ++ * configured to work at either data path width. ++ * ++ * 8 or 16 bits (default 16) ++ */ ++extern int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if); ++//#define dwc_param_phy_utmi_width_default 16 ++#define dwc_param_phy_utmi_width_default 8 // Broadcom BCM2708 ++ ++/** ++ * Specifies whether the ULPI operates at double or single ++ * data rate. This parameter is only applicable if PHY_TYPE is ++ * ULPI. ++ * ++ * 0 - single data rate ULPI interface with 8 bit wide data ++ * bus (default) ++ * 1 - double data rate ULPI interface with 4 bit wide data ++ * bus ++ */ ++extern int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if); ++#define dwc_param_phy_ulpi_ddr_default 0 ++ ++/** ++ * Specifies whether to use the internal or external supply to ++ * drive the vbus with a ULPI phy. ++ */ ++extern int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if); ++#define DWC_PHY_ULPI_INTERNAL_VBUS 0 ++#define DWC_PHY_ULPI_EXTERNAL_VBUS 1 ++#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS ++ ++/** ++ * Specifies whether to use the I2Cinterface for full speed PHY. This ++ * parameter is only applicable if PHY_TYPE is FS. ++ * 0 - No (default) ++ * 1 - Yes ++ */ ++extern int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if); ++#define dwc_param_i2c_enable_default 0 ++ ++extern int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if); ++#define dwc_param_ulpi_fs_ls_default 0 ++ ++extern int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val); ++extern int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if); ++#define dwc_param_ts_dline_default 0 ++ ++/** ++ * Specifies whether dedicated transmit FIFOs are ++ * enabled for non periodic IN endpoints in device mode ++ * 0 - No ++ * 1 - Yes ++ */ ++extern int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t * ++ core_if); ++#define dwc_param_en_multiple_tx_fifo_default 1 ++ ++/** Number of 4-byte words in each of the Tx FIFOs in device ++ * mode when dynamic FIFO sizing is enabled. ++ * 4 to 768 (default 256) ++ */ ++extern int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, ++ int fifo_num, int32_t val); ++extern int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, ++ int fifo_num); ++#define dwc_param_dev_tx_fifo_size_default 768 ++ ++/** Thresholding enable flag- ++ * bit 0 - enable non-ISO Tx thresholding ++ * bit 1 - enable ISO Tx thresholding ++ * bit 2 - enable Rx thresholding ++ */ ++extern int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val); ++extern int32_t dwc_otg_get_thr_ctl(dwc_otg_core_if_t * core_if, int fifo_num); ++#define dwc_param_thr_ctl_default 0 ++ ++/** Thresholding length for Tx ++ * FIFOs in 32 bit DWORDs ++ */ ++extern int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_tx_thr_length(dwc_otg_core_if_t * core_if); ++#define dwc_param_tx_thr_length_default 64 ++ ++/** Thresholding length for Rx ++ * FIFOs in 32 bit DWORDs ++ */ ++extern int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_rx_thr_length(dwc_otg_core_if_t * core_if); ++#define dwc_param_rx_thr_length_default 64 ++ ++/** ++ * Specifies whether LPM (Link Power Management) support is enabled ++ */ ++extern int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if); ++#define dwc_param_lpm_enable_default 1 ++ ++/** ++ * Specifies whether PTI enhancement is enabled ++ */ ++extern int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if); ++#define dwc_param_pti_enable_default 0 ++ ++/** ++ * Specifies whether MPI enhancement is enabled ++ */ ++extern int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if); ++#define dwc_param_mpi_enable_default 0 ++ ++/** ++ * Specifies whether ADP capability is enabled ++ */ ++extern int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if); ++#define dwc_param_adp_enable_default 0 ++ ++/** ++ * Specifies whether IC_USB capability is enabled ++ */ ++ ++extern int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if); ++#define dwc_param_ic_usb_cap_default 0 ++ ++extern int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if); ++#define dwc_param_ahb_thr_ratio_default 0 ++ ++extern int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if); ++#define dwc_param_power_down_default 0 ++ ++extern int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if); ++#define dwc_param_reload_ctl_default 0 ++ ++extern int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if); ++#define dwc_param_dev_out_nak_default 0 ++ ++extern int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if); ++#define dwc_param_cont_on_bna_default 0 ++ ++extern int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if); ++#define dwc_param_ahb_single_default 0 ++ ++extern int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val); ++extern int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if); ++#define dwc_param_otg_ver_default 0 ++ ++/** @} */ ++ ++/** @name Access to registers and bit-fields */ ++ ++/** ++ * Dump core registers and SPRAM ++ */ ++extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * _core_if); ++extern void dwc_otg_dump_spram(dwc_otg_core_if_t * _core_if); ++extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t * _core_if); ++extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t * _core_if); ++ ++/** ++ * Get host negotiation status. ++ */ ++extern uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if); ++ ++/** ++ * Get srp status ++ */ ++extern uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if); ++ ++/** ++ * Set hnpreq bit in the GOTGCTL register. ++ */ ++extern void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * Get Content of SNPSID register. ++ */ ++extern uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if); ++ ++/** ++ * Get current mode. ++ * Returns 0 if in device mode, and 1 if in host mode. ++ */ ++extern uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if); ++ ++/** ++ * Get value of hnpcapable field in the GUSBCFG register ++ */ ++extern uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if); ++/** ++ * Set value of hnpcapable field in the GUSBCFG register ++ */ ++extern void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * Get value of srpcapable field in the GUSBCFG register ++ */ ++extern uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if); ++/** ++ * Set value of srpcapable field in the GUSBCFG register ++ */ ++extern void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * Get value of devspeed field in the DCFG register ++ */ ++extern uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if); ++/** ++ * Set value of devspeed field in the DCFG register ++ */ ++extern void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * Get the value of busconnected field from the HPRT0 register ++ */ ++extern uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if); ++ ++/** ++ * Gets the device enumeration Speed. ++ */ ++extern uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if); ++ ++/** ++ * Get value of prtpwr field from the HPRT0 register ++ */ ++extern uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if); ++ ++/** ++ * Get value of flag indicating core state - hibernated or not ++ */ ++extern uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if); ++ ++/** ++ * Set value of prtpwr field from the HPRT0 register ++ */ ++extern void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * Get value of prtsusp field from the HPRT0 regsiter ++ */ ++extern uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if); ++/** ++ * Set value of prtpwr field from the HPRT0 register ++ */ ++extern void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * Get value of ModeChTimEn field from the HCFG regsiter ++ */ ++extern uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if); ++/** ++ * Set value of ModeChTimEn field from the HCFG regsiter ++ */ ++extern void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * Get value of Fram Interval field from the HFIR regsiter ++ */ ++extern uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if); ++/** ++ * Set value of Frame Interval field from the HFIR regsiter ++ */ ++extern void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * Set value of prtres field from the HPRT0 register ++ *FIXME Remove? ++ */ ++extern void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * Get value of rmtwkupsig bit in DCTL register ++ */ ++extern uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if); ++ ++/** ++ * Get value of prt_sleep_sts field from the GLPMCFG register ++ */ ++extern uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if); ++ ++/** ++ * Get value of rem_wkup_en field from the GLPMCFG register ++ */ ++extern uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if); ++ ++/** ++ * Get value of appl_resp field from the GLPMCFG register ++ */ ++extern uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if); ++/** ++ * Set value of appl_resp field from the GLPMCFG register ++ */ ++extern void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * Get value of hsic_connect field from the GLPMCFG register ++ */ ++extern uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if); ++/** ++ * Set value of hsic_connect field from the GLPMCFG register ++ */ ++extern void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * Get value of inv_sel_hsic field from the GLPMCFG register. ++ */ ++extern uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if); ++/** ++ * Set value of inv_sel_hsic field from the GLPMFG register. ++ */ ++extern void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/* ++ * Some functions for accessing registers ++ */ ++ ++/** ++ * GOTGCTL register ++ */ ++extern uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if); ++extern void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * GUSBCFG register ++ */ ++extern uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if); ++extern void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * GRXFSIZ register ++ */ ++extern uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if); ++extern void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * GNPTXFSIZ register ++ */ ++extern uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if); ++extern void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++extern uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if); ++extern void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * GGPIO register ++ */ ++extern uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if); ++extern void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * GUID register ++ */ ++extern uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if); ++extern void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * HPRT0 register ++ */ ++extern uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if); ++extern void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * GHPTXFSIZE ++ */ ++extern uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if); ++ ++/** @} */ ++ ++#endif /* __DWC_CORE_IF_H__ */ +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_dbg.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_dbg.h +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_dbg.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_dbg.h 2015-11-29 09:42:39.919098694 +0100 +@@ -0,0 +1,117 @@ ++/* ========================================================================== ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++#ifndef __DWC_OTG_DBG_H__ ++#define __DWC_OTG_DBG_H__ ++ ++/** @file ++ * This file defines debug levels. ++ * Debugging support vanishes in non-debug builds. ++ */ ++ ++/** ++ * The Debug Level bit-mask variable. ++ */ ++extern uint32_t g_dbg_lvl; ++/** ++ * Set the Debug Level variable. ++ */ ++static inline uint32_t SET_DEBUG_LEVEL(const uint32_t new) ++{ ++ uint32_t old = g_dbg_lvl; ++ g_dbg_lvl = new; ++ return old; ++} ++ ++#define DBG_USER (0x1) ++/** When debug level has the DBG_CIL bit set, display CIL Debug messages. */ ++#define DBG_CIL (0x2) ++/** When debug level has the DBG_CILV bit set, display CIL Verbose debug ++ * messages */ ++#define DBG_CILV (0x20) ++/** When debug level has the DBG_PCD bit set, display PCD (Device) debug ++ * messages */ ++#define DBG_PCD (0x4) ++/** When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug ++ * messages */ ++#define DBG_PCDV (0x40) ++/** When debug level has the DBG_HCD bit set, display Host debug messages */ ++#define DBG_HCD (0x8) ++/** When debug level has the DBG_HCDV bit set, display Verbose Host debug ++ * messages */ ++#define DBG_HCDV (0x80) ++/** When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host ++ * mode. */ ++#define DBG_HCD_URB (0x800) ++/** When debug level has the DBG_HCDI bit set, display host interrupt ++ * messages. */ ++#define DBG_HCDI (0x1000) ++ ++/** When debug level has any bit set, display debug messages */ ++#define DBG_ANY (0xFF) ++ ++/** All debug messages off */ ++#define DBG_OFF 0 ++ ++/** Prefix string for DWC_DEBUG print macros. */ ++#define USB_DWC "DWC_otg: " ++ ++/** ++ * Print a debug message when the Global debug level variable contains ++ * the bit defined in lvl. ++ * ++ * @param[in] lvl - Debug level, use one of the DBG_ constants above. ++ * @param[in] x - like printf ++ * ++ * Example:

++ * ++ * DWC_DEBUGPL( DBG_ANY, "%s(%p)\n", __func__, _reg_base_addr); ++ * ++ *
++ * results in:
++ * ++ * usb-DWC_otg: dwc_otg_cil_init(ca867000) ++ * ++ */ ++#ifdef DEBUG ++ ++# define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)__DWC_DEBUG(USB_DWC x ); }while(0) ++# define DWC_DEBUGP(x...) DWC_DEBUGPL(DBG_ANY, x ) ++ ++# define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl) ++ ++#else ++ ++# define DWC_DEBUGPL(lvl, x...) do{}while(0) ++# define DWC_DEBUGP(x...) ++ ++# define CHK_DEBUG_LEVEL(level) (0) ++ ++#endif /*DEBUG*/ ++#endif +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_driver.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_driver.c +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_driver.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_driver.c 2015-11-29 09:42:39.919098694 +0100 +@@ -0,0 +1,1757 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $ ++ * $Revision: #92 $ ++ * $Date: 2012/08/10 $ ++ * $Change: 2047372 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++/** @file ++ * The dwc_otg_driver module provides the initialization and cleanup entry ++ * points for the DWC_otg driver. This module will be dynamically installed ++ * after Linux is booted using the insmod command. When the module is ++ * installed, the dwc_otg_driver_init function is called. When the module is ++ * removed (using rmmod), the dwc_otg_driver_cleanup function is called. ++ * ++ * This module also defines a data structure for the dwc_otg_driver, which is ++ * used in conjunction with the standard ARM lm_device structure. These ++ * structures allow the OTG driver to comply with the standard Linux driver ++ * model in which devices and drivers are registered with a bus driver. This ++ * has the benefit that Linux can expose attributes of the driver and device ++ * in its special sysfs file system. Users can then read or write files in ++ * this file system to perform diagnostics on the driver components or the ++ * device. ++ */ ++ ++#include "dwc_otg_os_dep.h" ++#include "dwc_os.h" ++#include "dwc_otg_dbg.h" ++#include "dwc_otg_driver.h" ++#include "dwc_otg_attr.h" ++#include "dwc_otg_core_if.h" ++#include "dwc_otg_pcd_if.h" ++#include "dwc_otg_hcd_if.h" ++#include "dwc_otg_fiq_fsm.h" ++ ++#define DWC_DRIVER_VERSION "3.00a 10-AUG-2012" ++#define DWC_DRIVER_DESC "HS OTG USB Controller driver" ++ ++bool microframe_schedule=true; ++ ++static const char dwc_driver_name[] = "dwc_otg"; ++ ++ ++extern int pcd_init( ++#ifdef LM_INTERFACE ++ struct lm_device *_dev ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *_dev ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *dev ++#endif ++ ); ++extern int hcd_init( ++#ifdef LM_INTERFACE ++ struct lm_device *_dev ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *_dev ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *dev ++#endif ++ ); ++ ++extern int pcd_remove( ++#ifdef LM_INTERFACE ++ struct lm_device *_dev ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *_dev ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *_dev ++#endif ++ ); ++ ++extern void hcd_remove( ++#ifdef LM_INTERFACE ++ struct lm_device *_dev ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *_dev ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *_dev ++#endif ++ ); ++ ++extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host); ++ ++/*-------------------------------------------------------------------------*/ ++/* Encapsulate the module parameter settings */ ++ ++struct dwc_otg_driver_module_params { ++ int32_t opt; ++ int32_t otg_cap; ++ int32_t dma_enable; ++ int32_t dma_desc_enable; ++ int32_t dma_burst_size; ++ int32_t speed; ++ int32_t host_support_fs_ls_low_power; ++ int32_t host_ls_low_power_phy_clk; ++ int32_t enable_dynamic_fifo; ++ int32_t data_fifo_size; ++ int32_t dev_rx_fifo_size; ++ int32_t dev_nperio_tx_fifo_size; ++ uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS]; ++ int32_t host_rx_fifo_size; ++ int32_t host_nperio_tx_fifo_size; ++ int32_t host_perio_tx_fifo_size; ++ int32_t max_transfer_size; ++ int32_t max_packet_count; ++ int32_t host_channels; ++ int32_t dev_endpoints; ++ int32_t phy_type; ++ int32_t phy_utmi_width; ++ int32_t phy_ulpi_ddr; ++ int32_t phy_ulpi_ext_vbus; ++ int32_t i2c_enable; ++ int32_t ulpi_fs_ls; ++ int32_t ts_dline; ++ int32_t en_multiple_tx_fifo; ++ uint32_t dev_tx_fifo_size[MAX_TX_FIFOS]; ++ uint32_t thr_ctl; ++ uint32_t tx_thr_length; ++ uint32_t rx_thr_length; ++ int32_t pti_enable; ++ int32_t mpi_enable; ++ int32_t lpm_enable; ++ int32_t ic_usb_cap; ++ int32_t ahb_thr_ratio; ++ int32_t power_down; ++ int32_t reload_ctl; ++ int32_t dev_out_nak; ++ int32_t cont_on_bna; ++ int32_t ahb_single; ++ int32_t otg_ver; ++ int32_t adp_enable; ++}; ++ ++static struct dwc_otg_driver_module_params dwc_otg_module_params = { ++ .opt = -1, ++ .otg_cap = -1, ++ .dma_enable = -1, ++ .dma_desc_enable = -1, ++ .dma_burst_size = -1, ++ .speed = -1, ++ .host_support_fs_ls_low_power = -1, ++ .host_ls_low_power_phy_clk = -1, ++ .enable_dynamic_fifo = -1, ++ .data_fifo_size = -1, ++ .dev_rx_fifo_size = -1, ++ .dev_nperio_tx_fifo_size = -1, ++ .dev_perio_tx_fifo_size = { ++ /* dev_perio_tx_fifo_size_1 */ ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1 ++ /* 15 */ ++ }, ++ .host_rx_fifo_size = -1, ++ .host_nperio_tx_fifo_size = -1, ++ .host_perio_tx_fifo_size = -1, ++ .max_transfer_size = -1, ++ .max_packet_count = -1, ++ .host_channels = -1, ++ .dev_endpoints = -1, ++ .phy_type = -1, ++ .phy_utmi_width = -1, ++ .phy_ulpi_ddr = -1, ++ .phy_ulpi_ext_vbus = -1, ++ .i2c_enable = -1, ++ .ulpi_fs_ls = -1, ++ .ts_dline = -1, ++ .en_multiple_tx_fifo = -1, ++ .dev_tx_fifo_size = { ++ /* dev_tx_fifo_size */ ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1 ++ /* 15 */ ++ }, ++ .thr_ctl = -1, ++ .tx_thr_length = -1, ++ .rx_thr_length = -1, ++ .pti_enable = -1, ++ .mpi_enable = -1, ++ .lpm_enable = 0, ++ .ic_usb_cap = -1, ++ .ahb_thr_ratio = -1, ++ .power_down = -1, ++ .reload_ctl = -1, ++ .dev_out_nak = -1, ++ .cont_on_bna = -1, ++ .ahb_single = -1, ++ .otg_ver = -1, ++ .adp_enable = -1, ++}; ++ ++//Global variable to switch the fiq fix on or off ++bool fiq_enable = 1; ++// Global variable to enable the split transaction fix ++bool fiq_fsm_enable = true; ++//Bulk split-transaction NAK holdoff in microframes ++uint16_t nak_holdoff = 8; ++ ++unsigned short fiq_fsm_mask = 0x07; ++ ++/** ++ * This function shows the Driver Version. ++ */ ++static ssize_t version_show(struct device_driver *dev, char *buf) ++{ ++ return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n", ++ DWC_DRIVER_VERSION); ++} ++ ++static DRIVER_ATTR(version, S_IRUGO, version_show, NULL); ++ ++/** ++ * Global Debug Level Mask. ++ */ ++uint32_t g_dbg_lvl = 0; /* OFF */ ++ ++/** ++ * This function shows the driver Debug Level. ++ */ ++static ssize_t dbg_level_show(struct device_driver *drv, char *buf) ++{ ++ return sprintf(buf, "0x%0x\n", g_dbg_lvl); ++} ++ ++/** ++ * This function stores the driver Debug Level. ++ */ ++static ssize_t dbg_level_store(struct device_driver *drv, const char *buf, ++ size_t count) ++{ ++ g_dbg_lvl = simple_strtoul(buf, NULL, 16); ++ return count; ++} ++ ++static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show, ++ dbg_level_store); ++ ++/** ++ * This function is called during module intialization ++ * to pass module parameters to the DWC_OTG CORE. ++ */ ++static int set_parameters(dwc_otg_core_if_t * core_if) ++{ ++ int retval = 0; ++ int i; ++ ++ if (dwc_otg_module_params.otg_cap != -1) { ++ retval += ++ dwc_otg_set_param_otg_cap(core_if, ++ dwc_otg_module_params.otg_cap); ++ } ++ if (dwc_otg_module_params.dma_enable != -1) { ++ retval += ++ dwc_otg_set_param_dma_enable(core_if, ++ dwc_otg_module_params. ++ dma_enable); ++ } ++ if (dwc_otg_module_params.dma_desc_enable != -1) { ++ retval += ++ dwc_otg_set_param_dma_desc_enable(core_if, ++ dwc_otg_module_params. ++ dma_desc_enable); ++ } ++ if (dwc_otg_module_params.opt != -1) { ++ retval += ++ dwc_otg_set_param_opt(core_if, dwc_otg_module_params.opt); ++ } ++ if (dwc_otg_module_params.dma_burst_size != -1) { ++ retval += ++ dwc_otg_set_param_dma_burst_size(core_if, ++ dwc_otg_module_params. ++ dma_burst_size); ++ } ++ if (dwc_otg_module_params.host_support_fs_ls_low_power != -1) { ++ retval += ++ dwc_otg_set_param_host_support_fs_ls_low_power(core_if, ++ dwc_otg_module_params. ++ host_support_fs_ls_low_power); ++ } ++ if (dwc_otg_module_params.enable_dynamic_fifo != -1) { ++ retval += ++ dwc_otg_set_param_enable_dynamic_fifo(core_if, ++ dwc_otg_module_params. ++ enable_dynamic_fifo); ++ } ++ if (dwc_otg_module_params.data_fifo_size != -1) { ++ retval += ++ dwc_otg_set_param_data_fifo_size(core_if, ++ dwc_otg_module_params. ++ data_fifo_size); ++ } ++ if (dwc_otg_module_params.dev_rx_fifo_size != -1) { ++ retval += ++ dwc_otg_set_param_dev_rx_fifo_size(core_if, ++ dwc_otg_module_params. ++ dev_rx_fifo_size); ++ } ++ if (dwc_otg_module_params.dev_nperio_tx_fifo_size != -1) { ++ retval += ++ dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if, ++ dwc_otg_module_params. ++ dev_nperio_tx_fifo_size); ++ } ++ if (dwc_otg_module_params.host_rx_fifo_size != -1) { ++ retval += ++ dwc_otg_set_param_host_rx_fifo_size(core_if, ++ dwc_otg_module_params.host_rx_fifo_size); ++ } ++ if (dwc_otg_module_params.host_nperio_tx_fifo_size != -1) { ++ retval += ++ dwc_otg_set_param_host_nperio_tx_fifo_size(core_if, ++ dwc_otg_module_params. ++ host_nperio_tx_fifo_size); ++ } ++ if (dwc_otg_module_params.host_perio_tx_fifo_size != -1) { ++ retval += ++ dwc_otg_set_param_host_perio_tx_fifo_size(core_if, ++ dwc_otg_module_params. ++ host_perio_tx_fifo_size); ++ } ++ if (dwc_otg_module_params.max_transfer_size != -1) { ++ retval += ++ dwc_otg_set_param_max_transfer_size(core_if, ++ dwc_otg_module_params. ++ max_transfer_size); ++ } ++ if (dwc_otg_module_params.max_packet_count != -1) { ++ retval += ++ dwc_otg_set_param_max_packet_count(core_if, ++ dwc_otg_module_params. ++ max_packet_count); ++ } ++ if (dwc_otg_module_params.host_channels != -1) { ++ retval += ++ dwc_otg_set_param_host_channels(core_if, ++ dwc_otg_module_params. ++ host_channels); ++ } ++ if (dwc_otg_module_params.dev_endpoints != -1) { ++ retval += ++ dwc_otg_set_param_dev_endpoints(core_if, ++ dwc_otg_module_params. ++ dev_endpoints); ++ } ++ if (dwc_otg_module_params.phy_type != -1) { ++ retval += ++ dwc_otg_set_param_phy_type(core_if, ++ dwc_otg_module_params.phy_type); ++ } ++ if (dwc_otg_module_params.speed != -1) { ++ retval += ++ dwc_otg_set_param_speed(core_if, ++ dwc_otg_module_params.speed); ++ } ++ if (dwc_otg_module_params.host_ls_low_power_phy_clk != -1) { ++ retval += ++ dwc_otg_set_param_host_ls_low_power_phy_clk(core_if, ++ dwc_otg_module_params. ++ host_ls_low_power_phy_clk); ++ } ++ if (dwc_otg_module_params.phy_ulpi_ddr != -1) { ++ retval += ++ dwc_otg_set_param_phy_ulpi_ddr(core_if, ++ dwc_otg_module_params. ++ phy_ulpi_ddr); ++ } ++ if (dwc_otg_module_params.phy_ulpi_ext_vbus != -1) { ++ retval += ++ dwc_otg_set_param_phy_ulpi_ext_vbus(core_if, ++ dwc_otg_module_params. ++ phy_ulpi_ext_vbus); ++ } ++ if (dwc_otg_module_params.phy_utmi_width != -1) { ++ retval += ++ dwc_otg_set_param_phy_utmi_width(core_if, ++ dwc_otg_module_params. ++ phy_utmi_width); ++ } ++ if (dwc_otg_module_params.ulpi_fs_ls != -1) { ++ retval += ++ dwc_otg_set_param_ulpi_fs_ls(core_if, ++ dwc_otg_module_params.ulpi_fs_ls); ++ } ++ if (dwc_otg_module_params.ts_dline != -1) { ++ retval += ++ dwc_otg_set_param_ts_dline(core_if, ++ dwc_otg_module_params.ts_dline); ++ } ++ if (dwc_otg_module_params.i2c_enable != -1) { ++ retval += ++ dwc_otg_set_param_i2c_enable(core_if, ++ dwc_otg_module_params. ++ i2c_enable); ++ } ++ if (dwc_otg_module_params.en_multiple_tx_fifo != -1) { ++ retval += ++ dwc_otg_set_param_en_multiple_tx_fifo(core_if, ++ dwc_otg_module_params. ++ en_multiple_tx_fifo); ++ } ++ for (i = 0; i < 15; i++) { ++ if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) { ++ retval += ++ dwc_otg_set_param_dev_perio_tx_fifo_size(core_if, ++ dwc_otg_module_params. ++ dev_perio_tx_fifo_size ++ [i], i); ++ } ++ } ++ ++ for (i = 0; i < 15; i++) { ++ if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) { ++ retval += dwc_otg_set_param_dev_tx_fifo_size(core_if, ++ dwc_otg_module_params. ++ dev_tx_fifo_size ++ [i], i); ++ } ++ } ++ if (dwc_otg_module_params.thr_ctl != -1) { ++ retval += ++ dwc_otg_set_param_thr_ctl(core_if, ++ dwc_otg_module_params.thr_ctl); ++ } ++ if (dwc_otg_module_params.mpi_enable != -1) { ++ retval += ++ dwc_otg_set_param_mpi_enable(core_if, ++ dwc_otg_module_params. ++ mpi_enable); ++ } ++ if (dwc_otg_module_params.pti_enable != -1) { ++ retval += ++ dwc_otg_set_param_pti_enable(core_if, ++ dwc_otg_module_params. ++ pti_enable); ++ } ++ if (dwc_otg_module_params.lpm_enable != -1) { ++ retval += ++ dwc_otg_set_param_lpm_enable(core_if, ++ dwc_otg_module_params. ++ lpm_enable); ++ } ++ if (dwc_otg_module_params.ic_usb_cap != -1) { ++ retval += ++ dwc_otg_set_param_ic_usb_cap(core_if, ++ dwc_otg_module_params. ++ ic_usb_cap); ++ } ++ if (dwc_otg_module_params.tx_thr_length != -1) { ++ retval += ++ dwc_otg_set_param_tx_thr_length(core_if, ++ dwc_otg_module_params.tx_thr_length); ++ } ++ if (dwc_otg_module_params.rx_thr_length != -1) { ++ retval += ++ dwc_otg_set_param_rx_thr_length(core_if, ++ dwc_otg_module_params. ++ rx_thr_length); ++ } ++ if (dwc_otg_module_params.ahb_thr_ratio != -1) { ++ retval += ++ dwc_otg_set_param_ahb_thr_ratio(core_if, ++ dwc_otg_module_params.ahb_thr_ratio); ++ } ++ if (dwc_otg_module_params.power_down != -1) { ++ retval += ++ dwc_otg_set_param_power_down(core_if, ++ dwc_otg_module_params.power_down); ++ } ++ if (dwc_otg_module_params.reload_ctl != -1) { ++ retval += ++ dwc_otg_set_param_reload_ctl(core_if, ++ dwc_otg_module_params.reload_ctl); ++ } ++ ++ if (dwc_otg_module_params.dev_out_nak != -1) { ++ retval += ++ dwc_otg_set_param_dev_out_nak(core_if, ++ dwc_otg_module_params.dev_out_nak); ++ } ++ ++ if (dwc_otg_module_params.cont_on_bna != -1) { ++ retval += ++ dwc_otg_set_param_cont_on_bna(core_if, ++ dwc_otg_module_params.cont_on_bna); ++ } ++ ++ if (dwc_otg_module_params.ahb_single != -1) { ++ retval += ++ dwc_otg_set_param_ahb_single(core_if, ++ dwc_otg_module_params.ahb_single); ++ } ++ ++ if (dwc_otg_module_params.otg_ver != -1) { ++ retval += ++ dwc_otg_set_param_otg_ver(core_if, ++ dwc_otg_module_params.otg_ver); ++ } ++ if (dwc_otg_module_params.adp_enable != -1) { ++ retval += ++ dwc_otg_set_param_adp_enable(core_if, ++ dwc_otg_module_params. ++ adp_enable); ++ } ++ return retval; ++} ++ ++/** ++ * This function is the top level interrupt handler for the Common ++ * (Device and host modes) interrupts. ++ */ ++static irqreturn_t dwc_otg_common_irq(int irq, void *dev) ++{ ++ int32_t retval = IRQ_NONE; ++ ++ retval = dwc_otg_handle_common_intr(dev); ++ if (retval != 0) { ++ S3C2410X_CLEAR_EINTPEND(); ++ } ++ return IRQ_RETVAL(retval); ++} ++ ++/** ++ * This function is called when a lm_device is unregistered with the ++ * dwc_otg_driver. This happens, for example, when the rmmod command is ++ * executed. The device may or may not be electrically present. If it is ++ * present, the driver stops device processing. Any resources used on behalf ++ * of this device are freed. ++ * ++ * @param _dev ++ */ ++#ifdef LM_INTERFACE ++#define REM_RETVAL(n) ++static void dwc_otg_driver_remove( struct lm_device *_dev ) ++{ dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev); ++#elif defined(PCI_INTERFACE) ++#define REM_RETVAL(n) ++static void dwc_otg_driver_remove( struct pci_dev *_dev ) ++{ dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev); ++#elif defined(PLATFORM_INTERFACE) ++#define REM_RETVAL(n) n ++static int dwc_otg_driver_remove( struct platform_device *_dev ) ++{ dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev); ++#endif ++ ++ DWC_DEBUGPL(DBG_ANY, "%s(%p) otg_dev %p\n", __func__, _dev, otg_dev); ++ ++ if (!otg_dev) { ++ /* Memory allocation for the dwc_otg_device failed. */ ++ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__); ++ return REM_RETVAL(-ENOMEM); ++ } ++#ifndef DWC_DEVICE_ONLY ++ if (otg_dev->hcd) { ++ hcd_remove(_dev); ++ } else { ++ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__); ++ return REM_RETVAL(-EINVAL); ++ } ++#endif ++ ++#ifndef DWC_HOST_ONLY ++ if (otg_dev->pcd) { ++ pcd_remove(_dev); ++ } else { ++ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__); ++ return REM_RETVAL(-EINVAL); ++ } ++#endif ++ /* ++ * Free the IRQ ++ */ ++ if (otg_dev->common_irq_installed) { ++#ifdef PLATFORM_INTERFACE ++ free_irq(platform_get_irq(_dev, 0), otg_dev); ++#else ++ free_irq(_dev->irq, otg_dev); ++#endif ++ } else { ++ DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n", __func__); ++ return REM_RETVAL(-ENXIO); ++ } ++ ++ if (otg_dev->core_if) { ++ dwc_otg_cil_remove(otg_dev->core_if); ++ } else { ++ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__); ++ return REM_RETVAL(-ENXIO); ++ } ++ ++ /* ++ * Remove the device attributes ++ */ ++ dwc_otg_attr_remove(_dev); ++ ++ /* ++ * Return the memory. ++ */ ++ if (otg_dev->os_dep.base) { ++ iounmap(otg_dev->os_dep.base); ++ } ++ DWC_FREE(otg_dev); ++ ++ /* ++ * Clear the drvdata pointer. ++ */ ++#ifdef LM_INTERFACE ++ lm_set_drvdata(_dev, 0); ++#elif defined(PCI_INTERFACE) ++ release_mem_region(otg_dev->os_dep.rsrc_start, ++ otg_dev->os_dep.rsrc_len); ++ pci_set_drvdata(_dev, 0); ++#elif defined(PLATFORM_INTERFACE) ++ platform_set_drvdata(_dev, 0); ++#endif ++ return REM_RETVAL(0); ++} ++ ++/** ++ * This function is called when an lm_device is bound to a ++ * dwc_otg_driver. It creates the driver components required to ++ * control the device (CIL, HCD, and PCD) and it initializes the ++ * device. The driver components are stored in a dwc_otg_device ++ * structure. A reference to the dwc_otg_device is saved in the ++ * lm_device. This allows the driver to access the dwc_otg_device ++ * structure on subsequent calls to driver methods for this device. ++ * ++ * @param _dev Bus device ++ */ ++static int dwc_otg_driver_probe( ++#ifdef LM_INTERFACE ++ struct lm_device *_dev ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *_dev, ++ const struct pci_device_id *id ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *_dev ++#endif ++ ) ++{ ++ int retval = 0; ++ dwc_otg_device_t *dwc_otg_device; ++ int devirq; ++ ++ dev_dbg(&_dev->dev, "dwc_otg_driver_probe(%p)\n", _dev); ++#ifdef LM_INTERFACE ++ dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)_dev->resource.start); ++#elif defined(PCI_INTERFACE) ++ if (!id) { ++ DWC_ERROR("Invalid pci_device_id %p", id); ++ return -EINVAL; ++ } ++ ++ if (!_dev || (pci_enable_device(_dev) < 0)) { ++ DWC_ERROR("Invalid pci_device %p", _dev); ++ return -ENODEV; ++ } ++ dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)pci_resource_start(_dev,0)); ++ /* other stuff needed as well? */ ++ ++#elif defined(PLATFORM_INTERFACE) ++ dev_dbg(&_dev->dev, "start=0x%08x (len 0x%x)\n", ++ (unsigned)_dev->resource->start, ++ (unsigned)(_dev->resource->end - _dev->resource->start)); ++#endif ++ ++ dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t)); ++ ++ if (!dwc_otg_device) { ++ dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n"); ++ return -ENOMEM; ++ } ++ ++ memset(dwc_otg_device, 0, sizeof(*dwc_otg_device)); ++ dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF; ++ dwc_otg_device->os_dep.platformdev = _dev; ++ ++ /* ++ * Map the DWC_otg Core memory into virtual address space. ++ */ ++#ifdef LM_INTERFACE ++ dwc_otg_device->os_dep.base = ioremap(_dev->resource.start, SZ_256K); ++ ++ if (!dwc_otg_device->os_dep.base) { ++ dev_err(&_dev->dev, "ioremap() failed\n"); ++ DWC_FREE(dwc_otg_device); ++ return -ENOMEM; ++ } ++ dev_dbg(&_dev->dev, "base=0x%08x\n", ++ (unsigned)dwc_otg_device->os_dep.base); ++#elif defined(PCI_INTERFACE) ++ _dev->current_state = PCI_D0; ++ _dev->dev.power.power_state = PMSG_ON; ++ ++ if (!_dev->irq) { ++ DWC_ERROR("Found HC with no IRQ. Check BIOS/PCI %s setup!", ++ pci_name(_dev)); ++ iounmap(dwc_otg_device->os_dep.base); ++ DWC_FREE(dwc_otg_device); ++ return -ENODEV; ++ } ++ ++ dwc_otg_device->os_dep.rsrc_start = pci_resource_start(_dev, 0); ++ dwc_otg_device->os_dep.rsrc_len = pci_resource_len(_dev, 0); ++ DWC_DEBUGPL(DBG_ANY, "PCI resource: start=%08x, len=%08x\n", ++ (unsigned)dwc_otg_device->os_dep.rsrc_start, ++ (unsigned)dwc_otg_device->os_dep.rsrc_len); ++ if (!request_mem_region ++ (dwc_otg_device->os_dep.rsrc_start, dwc_otg_device->os_dep.rsrc_len, ++ "dwc_otg")) { ++ dev_dbg(&_dev->dev, "error requesting memory\n"); ++ iounmap(dwc_otg_device->os_dep.base); ++ DWC_FREE(dwc_otg_device); ++ return -EFAULT; ++ } ++ ++ dwc_otg_device->os_dep.base = ++ ioremap_nocache(dwc_otg_device->os_dep.rsrc_start, ++ dwc_otg_device->os_dep.rsrc_len); ++ if (dwc_otg_device->os_dep.base == NULL) { ++ dev_dbg(&_dev->dev, "error mapping memory\n"); ++ release_mem_region(dwc_otg_device->os_dep.rsrc_start, ++ dwc_otg_device->os_dep.rsrc_len); ++ iounmap(dwc_otg_device->os_dep.base); ++ DWC_FREE(dwc_otg_device); ++ return -EFAULT; ++ } ++ dev_dbg(&_dev->dev, "base=0x%p (before adjust) \n", ++ dwc_otg_device->os_dep.base); ++ dwc_otg_device->os_dep.base = (char *)dwc_otg_device->os_dep.base; ++ dev_dbg(&_dev->dev, "base=0x%p (after adjust) \n", ++ dwc_otg_device->os_dep.base); ++ dev_dbg(&_dev->dev, "%s: mapped PA 0x%x to VA 0x%p\n", __func__, ++ (unsigned)dwc_otg_device->os_dep.rsrc_start, ++ dwc_otg_device->os_dep.base); ++ ++ pci_set_master(_dev); ++ pci_set_drvdata(_dev, dwc_otg_device); ++#elif defined(PLATFORM_INTERFACE) ++ DWC_DEBUGPL(DBG_ANY,"Platform resource: start=%08x, len=%08x\n", ++ _dev->resource->start, ++ _dev->resource->end - _dev->resource->start + 1); ++#if 1 ++ if (!request_mem_region(_dev->resource[0].start, ++ _dev->resource[0].end - _dev->resource[0].start + 1, ++ "dwc_otg")) { ++ dev_dbg(&_dev->dev, "error reserving mapped memory\n"); ++ retval = -EFAULT; ++ goto fail; ++ } ++ ++ dwc_otg_device->os_dep.base = ioremap_nocache(_dev->resource[0].start, ++ _dev->resource[0].end - ++ _dev->resource[0].start+1); ++ if (fiq_enable) ++ { ++ if (!request_mem_region(_dev->resource[1].start, ++ _dev->resource[1].end - _dev->resource[1].start + 1, ++ "dwc_otg")) { ++ dev_dbg(&_dev->dev, "error reserving mapped memory\n"); ++ retval = -EFAULT; ++ goto fail; ++ } ++ ++ dwc_otg_device->os_dep.mphi_base = ioremap_nocache(_dev->resource[1].start, ++ _dev->resource[1].end - ++ _dev->resource[1].start + 1); ++ } ++ ++#else ++ { ++ struct map_desc desc = { ++ .virtual = IO_ADDRESS((unsigned)_dev->resource->start), ++ .pfn = __phys_to_pfn((unsigned)_dev->resource->start), ++ .length = SZ_128K, ++ .type = MT_DEVICE ++ }; ++ iotable_init(&desc, 1); ++ dwc_otg_device->os_dep.base = (void *)desc.virtual; ++ } ++#endif ++ if (!dwc_otg_device->os_dep.base) { ++ dev_err(&_dev->dev, "ioremap() failed\n"); ++ retval = -ENOMEM; ++ goto fail; ++ } ++ dev_dbg(&_dev->dev, "base=0x%08x\n", ++ (unsigned)dwc_otg_device->os_dep.base); ++#endif ++ ++ /* ++ * Initialize driver data to point to the global DWC_otg ++ * Device structure. ++ */ ++#ifdef LM_INTERFACE ++ lm_set_drvdata(_dev, dwc_otg_device); ++#elif defined(PLATFORM_INTERFACE) ++ platform_set_drvdata(_dev, dwc_otg_device); ++#endif ++ dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device); ++ ++ dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base); ++ DWC_DEBUGPL(DBG_HCDV, "probe of device %p given core_if %p\n", ++ dwc_otg_device, dwc_otg_device->core_if);//GRAYG ++ ++ if (!dwc_otg_device->core_if) { ++ dev_err(&_dev->dev, "CIL initialization failed!\n"); ++ retval = -ENOMEM; ++ goto fail; ++ } ++ ++ dev_dbg(&_dev->dev, "Calling get_gsnpsid\n"); ++ /* ++ * Attempt to ensure this device is really a DWC_otg Controller. ++ * Read and verify the SNPSID register contents. The value should be ++ * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3", ++ * as in "OTG version 2.XX" or "OTG version 3.XX". ++ */ ++ ++ if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F542000) && ++ ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F543000)) { ++ dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n", ++ dwc_otg_get_gsnpsid(dwc_otg_device->core_if)); ++ retval = -EINVAL; ++ goto fail; ++ } ++ ++ /* ++ * Validate parameter values. ++ */ ++ dev_dbg(&_dev->dev, "Calling set_parameters\n"); ++ if (set_parameters(dwc_otg_device->core_if)) { ++ retval = -EINVAL; ++ goto fail; ++ } ++ ++ /* ++ * Create Device Attributes in sysfs ++ */ ++ dev_dbg(&_dev->dev, "Calling attr_create\n"); ++ dwc_otg_attr_create(_dev); ++ ++ /* ++ * Disable the global interrupt until all the interrupt ++ * handlers are installed. ++ */ ++ dev_dbg(&_dev->dev, "Calling disable_global_interrupts\n"); ++ dwc_otg_disable_global_interrupts(dwc_otg_device->core_if); ++ ++ /* ++ * Install the interrupt handler for the common interrupts before ++ * enabling common interrupts in core_init below. ++ */ ++ ++#if defined(PLATFORM_INTERFACE) ++ devirq = platform_get_irq(_dev, fiq_enable ? 0 : 1); ++#else ++ devirq = _dev->irq; ++#endif ++ DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", ++ devirq); ++ dev_dbg(&_dev->dev, "Calling request_irq(%d)\n", devirq); ++ retval = request_irq(devirq, dwc_otg_common_irq, ++ IRQF_SHARED, ++ "dwc_otg", dwc_otg_device); ++ if (retval) { ++ DWC_ERROR("request of irq%d failed\n", devirq); ++ retval = -EBUSY; ++ goto fail; ++ } else { ++ dwc_otg_device->common_irq_installed = 1; ++ } ++ ++#ifndef IRQF_TRIGGER_LOW ++#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE) ++ dev_dbg(&_dev->dev, "Calling set_irq_type\n"); ++ set_irq_type(devirq, ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) ++ IRQT_LOW ++#else ++ IRQ_TYPE_LEVEL_LOW ++#endif ++ ); ++#endif ++#endif /*IRQF_TRIGGER_LOW*/ ++ ++ /* ++ * Initialize the DWC_otg core. ++ */ ++ dev_dbg(&_dev->dev, "Calling dwc_otg_core_init\n"); ++ dwc_otg_core_init(dwc_otg_device->core_if); ++ ++#ifndef DWC_HOST_ONLY ++ /* ++ * Initialize the PCD ++ */ ++ dev_dbg(&_dev->dev, "Calling pcd_init\n"); ++ retval = pcd_init(_dev); ++ if (retval != 0) { ++ DWC_ERROR("pcd_init failed\n"); ++ dwc_otg_device->pcd = NULL; ++ goto fail; ++ } ++#endif ++#ifndef DWC_DEVICE_ONLY ++ /* ++ * Initialize the HCD ++ */ ++ dev_dbg(&_dev->dev, "Calling hcd_init\n"); ++ retval = hcd_init(_dev); ++ if (retval != 0) { ++ DWC_ERROR("hcd_init failed\n"); ++ dwc_otg_device->hcd = NULL; ++ goto fail; ++ } ++#endif ++ /* Recover from drvdata having been overwritten by hcd_init() */ ++#ifdef LM_INTERFACE ++ lm_set_drvdata(_dev, dwc_otg_device); ++#elif defined(PLATFORM_INTERFACE) ++ platform_set_drvdata(_dev, dwc_otg_device); ++#elif defined(PCI_INTERFACE) ++ pci_set_drvdata(_dev, dwc_otg_device); ++ dwc_otg_device->os_dep.pcidev = _dev; ++#endif ++ ++ /* ++ * Enable the global interrupt after all the interrupt ++ * handlers are installed if there is no ADP support else ++ * perform initial actions required for Internal ADP logic. ++ */ ++ if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) { ++ dev_dbg(&_dev->dev, "Calling enable_global_interrupts\n"); ++ dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); ++ dev_dbg(&_dev->dev, "Done\n"); ++ } else ++ dwc_otg_adp_start(dwc_otg_device->core_if, ++ dwc_otg_is_host_mode(dwc_otg_device->core_if)); ++ ++ return 0; ++ ++fail: ++ dwc_otg_driver_remove(_dev); ++ return retval; ++} ++ ++/** ++ * This structure defines the methods to be called by a bus driver ++ * during the lifecycle of a device on that bus. Both drivers and ++ * devices are registered with a bus driver. The bus driver matches ++ * devices to drivers based on information in the device and driver ++ * structures. ++ * ++ * The probe function is called when the bus driver matches a device ++ * to this driver. The remove function is called when a device is ++ * unregistered with the bus driver. ++ */ ++#ifdef LM_INTERFACE ++static struct lm_driver dwc_otg_driver = { ++ .drv = {.name = (char *)dwc_driver_name,}, ++ .probe = dwc_otg_driver_probe, ++ .remove = dwc_otg_driver_remove, ++ // 'suspend' and 'resume' absent ++}; ++#elif defined(PCI_INTERFACE) ++static const struct pci_device_id pci_ids[] = { { ++ PCI_DEVICE(0x16c3, 0xabcd), ++ .driver_data = ++ (unsigned long)0xdeadbeef, ++ }, { /* end: all zeroes */ } ++}; ++ ++MODULE_DEVICE_TABLE(pci, pci_ids); ++ ++/* pci driver glue; this is a "new style" PCI driver module */ ++static struct pci_driver dwc_otg_driver = { ++ .name = "dwc_otg", ++ .id_table = pci_ids, ++ ++ .probe = dwc_otg_driver_probe, ++ .remove = dwc_otg_driver_remove, ++ ++ .driver = { ++ .name = (char *)dwc_driver_name, ++ }, ++}; ++#elif defined(PLATFORM_INTERFACE) ++static struct platform_device_id platform_ids[] = { ++ { ++ .name = "bcm2708_usb", ++ .driver_data = (kernel_ulong_t) 0xdeadbeef, ++ }, ++ { /* end: all zeroes */ } ++}; ++MODULE_DEVICE_TABLE(platform, platform_ids); ++ ++static const struct of_device_id dwc_otg_of_match_table[] = { ++ { .compatible = "brcm,bcm2708-usb", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, dwc_otg_of_match_table); ++ ++static struct platform_driver dwc_otg_driver = { ++ .driver = { ++ .name = (char *)dwc_driver_name, ++ .of_match_table = dwc_otg_of_match_table, ++ }, ++ .id_table = platform_ids, ++ ++ .probe = dwc_otg_driver_probe, ++ .remove = dwc_otg_driver_remove, ++ // no 'shutdown', 'suspend', 'resume', 'suspend_late' or 'resume_early' ++}; ++#endif ++ ++/** ++ * This function is called when the dwc_otg_driver is installed with the ++ * insmod command. It registers the dwc_otg_driver structure with the ++ * appropriate bus driver. This will cause the dwc_otg_driver_probe function ++ * to be called. In addition, the bus driver will automatically expose ++ * attributes defined for the device and driver in the special sysfs file ++ * system. ++ * ++ * @return ++ */ ++static int __init dwc_otg_driver_init(void) ++{ ++ int retval = 0; ++ int error; ++ struct device_driver *drv; ++ ++ if(fiq_fsm_enable && !fiq_enable) { ++ printk(KERN_WARNING "dwc_otg: fiq_fsm_enable was set without fiq_enable! Correcting.\n"); ++ fiq_enable = 1; ++ } ++ ++ printk(KERN_INFO "%s: version %s (%s bus)\n", dwc_driver_name, ++ DWC_DRIVER_VERSION, ++#ifdef LM_INTERFACE ++ "logicmodule"); ++ retval = lm_driver_register(&dwc_otg_driver); ++ drv = &dwc_otg_driver.drv; ++#elif defined(PCI_INTERFACE) ++ "pci"); ++ retval = pci_register_driver(&dwc_otg_driver); ++ drv = &dwc_otg_driver.driver; ++#elif defined(PLATFORM_INTERFACE) ++ "platform"); ++ retval = platform_driver_register(&dwc_otg_driver); ++ drv = &dwc_otg_driver.driver; ++#endif ++ if (retval < 0) { ++ printk(KERN_ERR "%s retval=%d\n", __func__, retval); ++ return retval; ++ } ++ printk(KERN_DEBUG "dwc_otg: FIQ %s\n", fiq_enable ? "enabled":"disabled"); ++ printk(KERN_DEBUG "dwc_otg: NAK holdoff %s\n", nak_holdoff ? "enabled":"disabled"); ++ printk(KERN_DEBUG "dwc_otg: FIQ split-transaction FSM %s\n", fiq_fsm_enable ? "enabled":"disabled"); ++ ++ error = driver_create_file(drv, &driver_attr_version); ++#ifdef DEBUG ++ error = driver_create_file(drv, &driver_attr_debuglevel); ++#endif ++ return retval; ++} ++ ++module_init(dwc_otg_driver_init); ++ ++/** ++ * This function is called when the driver is removed from the kernel ++ * with the rmmod command. The driver unregisters itself with its bus ++ * driver. ++ * ++ */ ++static void __exit dwc_otg_driver_cleanup(void) ++{ ++ printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n"); ++ ++#ifdef LM_INTERFACE ++ driver_remove_file(&dwc_otg_driver.drv, &driver_attr_debuglevel); ++ driver_remove_file(&dwc_otg_driver.drv, &driver_attr_version); ++ lm_driver_unregister(&dwc_otg_driver); ++#elif defined(PCI_INTERFACE) ++ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel); ++ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version); ++ pci_unregister_driver(&dwc_otg_driver); ++#elif defined(PLATFORM_INTERFACE) ++ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel); ++ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version); ++ platform_driver_unregister(&dwc_otg_driver); ++#endif ++ ++ printk(KERN_INFO "%s module removed\n", dwc_driver_name); ++} ++ ++module_exit(dwc_otg_driver_cleanup); ++ ++MODULE_DESCRIPTION(DWC_DRIVER_DESC); ++MODULE_AUTHOR("Synopsys Inc."); ++MODULE_LICENSE("GPL"); ++ ++module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444); ++MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None"); ++module_param_named(opt, dwc_otg_module_params.opt, int, 0444); ++MODULE_PARM_DESC(opt, "OPT Mode"); ++module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444); ++MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled"); ++ ++module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int, ++ 0444); ++MODULE_PARM_DESC(dma_desc_enable, ++ "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled"); ++ ++module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int, ++ 0444); ++MODULE_PARM_DESC(dma_burst_size, ++ "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256"); ++module_param_named(speed, dwc_otg_module_params.speed, int, 0444); ++MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed"); ++module_param_named(host_support_fs_ls_low_power, ++ dwc_otg_module_params.host_support_fs_ls_low_power, int, ++ 0444); ++MODULE_PARM_DESC(host_support_fs_ls_low_power, ++ "Support Low Power w/FS or LS 0=Support 1=Don't Support"); ++module_param_named(host_ls_low_power_phy_clk, ++ dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444); ++MODULE_PARM_DESC(host_ls_low_power_phy_clk, ++ "Low Speed Low Power Clock 0=48Mhz 1=6Mhz"); ++module_param_named(enable_dynamic_fifo, ++ dwc_otg_module_params.enable_dynamic_fifo, int, 0444); ++MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing"); ++module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int, ++ 0444); ++MODULE_PARM_DESC(data_fifo_size, ++ "Total number of words in the data FIFO memory 32-32768"); ++module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size, ++ int, 0444); ++MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768"); ++module_param_named(dev_nperio_tx_fifo_size, ++ dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444); ++MODULE_PARM_DESC(dev_nperio_tx_fifo_size, ++ "Number of words in the non-periodic Tx FIFO 16-32768"); ++module_param_named(dev_perio_tx_fifo_size_1, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_1, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_2, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_2, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_3, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_3, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_4, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_4, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_5, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_5, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_6, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_6, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_7, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_7, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_8, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_8, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_9, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_9, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_10, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_10, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_11, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_11, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_12, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_12, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_13, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_13, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_14, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_14, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_15, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_15, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size, ++ int, 0444); ++MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768"); ++module_param_named(host_nperio_tx_fifo_size, ++ dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444); ++MODULE_PARM_DESC(host_nperio_tx_fifo_size, ++ "Number of words in the non-periodic Tx FIFO 16-32768"); ++module_param_named(host_perio_tx_fifo_size, ++ dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444); ++MODULE_PARM_DESC(host_perio_tx_fifo_size, ++ "Number of words in the host periodic Tx FIFO 16-32768"); ++module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size, ++ int, 0444); ++/** @todo Set the max to 512K, modify checks */ ++MODULE_PARM_DESC(max_transfer_size, ++ "The maximum transfer size supported in bytes 2047-65535"); ++module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count, ++ int, 0444); ++MODULE_PARM_DESC(max_packet_count, ++ "The maximum number of packets in a transfer 15-511"); ++module_param_named(host_channels, dwc_otg_module_params.host_channels, int, ++ 0444); ++MODULE_PARM_DESC(host_channels, ++ "The number of host channel registers to use 1-16"); ++module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int, ++ 0444); ++MODULE_PARM_DESC(dev_endpoints, ++ "The number of endpoints in addition to EP0 available for device mode 1-15"); ++module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444); ++MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI"); ++module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int, ++ 0444); ++MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits"); ++module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444); ++MODULE_PARM_DESC(phy_ulpi_ddr, ++ "ULPI at double or single data rate 0=Single 1=Double"); ++module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus, ++ int, 0444); ++MODULE_PARM_DESC(phy_ulpi_ext_vbus, ++ "ULPI PHY using internal or external vbus 0=Internal"); ++module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444); ++MODULE_PARM_DESC(i2c_enable, "FS PHY Interface"); ++module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444); ++MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only"); ++module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444); ++MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs"); ++module_param_named(debug, g_dbg_lvl, int, 0444); ++MODULE_PARM_DESC(debug, ""); ++ ++module_param_named(en_multiple_tx_fifo, ++ dwc_otg_module_params.en_multiple_tx_fifo, int, 0444); ++MODULE_PARM_DESC(en_multiple_tx_fifo, ++ "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled"); ++module_param_named(dev_tx_fifo_size_1, ++ dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_2, ++ dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_3, ++ dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_4, ++ dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_5, ++ dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_6, ++ dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_7, ++ dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_8, ++ dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_9, ++ dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_10, ++ dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_11, ++ dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_12, ++ dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_13, ++ dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_14, ++ dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_15, ++ dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768"); ++ ++module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444); ++MODULE_PARM_DESC(thr_ctl, ++ "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled"); ++module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int, ++ 0444); ++MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs"); ++module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int, ++ 0444); ++MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs"); ++ ++module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444); ++module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444); ++module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444); ++MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled"); ++module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444); ++MODULE_PARM_DESC(ic_usb_cap, ++ "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled"); ++module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int, ++ 0444); ++MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio"); ++module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444); ++MODULE_PARM_DESC(power_down, "Power Down Mode"); ++module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444); ++MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control"); ++module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444); ++MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK"); ++module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444); ++MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA"); ++module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444); ++MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support"); ++module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444); ++MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled"); ++module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444); ++MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0"); ++module_param(microframe_schedule, bool, 0444); ++MODULE_PARM_DESC(microframe_schedule, "Enable the microframe scheduler"); ++ ++module_param(fiq_enable, bool, 0444); ++MODULE_PARM_DESC(fiq_enable, "Enable the FIQ"); ++module_param(nak_holdoff, ushort, 0644); ++MODULE_PARM_DESC(nak_holdoff, "Throttle duration for bulk split-transaction endpoints on a NAK. Default 8"); ++module_param(fiq_fsm_enable, bool, 0444); ++MODULE_PARM_DESC(fiq_fsm_enable, "Enable the FIQ to perform split transactions as defined by fiq_fsm_mask"); ++module_param(fiq_fsm_mask, ushort, 0444); ++MODULE_PARM_DESC(fiq_fsm_mask, "Bitmask of transactions to perform in the FIQ.\n" ++ "Bit 0 : Non-periodic split transactions\n" ++ "Bit 1 : Periodic split transactions\n" ++ "Bit 2 : High-speed multi-transfer isochronous\n" ++ "All other bits should be set 0."); ++ ++ ++/** @page "Module Parameters" ++ * ++ * The following parameters may be specified when starting the module. ++ * These parameters define how the DWC_otg controller should be ++ * configured. Parameter values are passed to the CIL initialization ++ * function dwc_otg_cil_init ++ * ++ * Example: modprobe dwc_otg speed=1 otg_cap=1 ++ * ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++*/ +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_driver.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_driver.h +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_driver.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_driver.h 2015-11-29 09:42:39.919098694 +0100 +@@ -0,0 +1,86 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.h $ ++ * $Revision: #19 $ ++ * $Date: 2010/11/15 $ ++ * $Change: 1627671 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++#ifndef __DWC_OTG_DRIVER_H__ ++#define __DWC_OTG_DRIVER_H__ ++ ++/** @file ++ * This file contains the interface to the Linux driver. ++ */ ++#include "dwc_otg_os_dep.h" ++#include "dwc_otg_core_if.h" ++ ++/* Type declarations */ ++struct dwc_otg_pcd; ++struct dwc_otg_hcd; ++ ++/** ++ * This structure is a wrapper that encapsulates the driver components used to ++ * manage a single DWC_otg controller. ++ */ ++typedef struct dwc_otg_device { ++ /** Structure containing OS-dependent stuff. KEEP THIS STRUCT AT THE ++ * VERY BEGINNING OF THE DEVICE STRUCT. OSes such as FreeBSD and NetBSD ++ * require this. */ ++ struct os_dependent os_dep; ++ ++ /** Pointer to the core interface structure. */ ++ dwc_otg_core_if_t *core_if; ++ ++ /** Pointer to the PCD structure. */ ++ struct dwc_otg_pcd *pcd; ++ ++ /** Pointer to the HCD structure. */ ++ struct dwc_otg_hcd *hcd; ++ ++ /** Flag to indicate whether the common IRQ handler is installed. */ ++ uint8_t common_irq_installed; ++ ++} dwc_otg_device_t; ++ ++/*We must clear S3C24XX_EINTPEND external interrupt register ++ * because after clearing in this register trigerred IRQ from ++ * H/W core in kernel interrupt can be occured again before OTG ++ * handlers clear all IRQ sources of Core registers because of ++ * timing latencies and Low Level IRQ Type. ++ */ ++#ifdef CONFIG_MACH_IPMATE ++#define S3C2410X_CLEAR_EINTPEND() \ ++do { \ ++ __raw_writel(1UL << 11,S3C24XX_EINTPEND); \ ++} while (0) ++#else ++#define S3C2410X_CLEAR_EINTPEND() do { } while (0) ++#endif ++ ++#endif +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c 2015-11-29 09:42:39.919098694 +0100 +@@ -0,0 +1,1355 @@ ++/* ++ * dwc_otg_fiq_fsm.c - The finite state machine FIQ ++ * ++ * Copyright (c) 2013 Raspberry Pi Foundation ++ * ++ * Author: Jonathan Bell ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of Raspberry Pi nor the ++ * names of its contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++ * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY ++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * This FIQ implements functionality that performs split transactions on ++ * the dwc_otg hardware without any outside intervention. A split transaction ++ * is "queued" by nominating a specific host channel to perform the entirety ++ * of a split transaction. This FIQ will then perform the microframe-precise ++ * scheduling required in each phase of the transaction until completion. ++ * ++ * The FIQ functionality is glued into the Synopsys driver via the entry point ++ * in the FSM enqueue function, and at the exit point in handling a HC interrupt ++ * for a FSM-enabled channel. ++ * ++ * NB: Large parts of this implementation have architecture-specific code. ++ * For porting this functionality to other ARM machines, the minimum is required: ++ * - An interrupt controller allowing the top-level dwc USB interrupt to be routed ++ * to the FIQ ++ * - A method of forcing a software generated interrupt from FIQ mode that then ++ * triggers an IRQ entry (with the dwc USB handler called by this IRQ number) ++ * - Guaranteed interrupt routing such that both the FIQ and SGI occur on the same ++ * processor core - there is no locking between the FIQ and IRQ (aside from ++ * local_fiq_disable) ++ * ++ */ ++ ++#include "dwc_otg_fiq_fsm.h" ++ ++ ++char buffer[1000*16]; ++int wptr; ++void notrace _fiq_print(enum fiq_debug_level dbg_lvl, volatile struct fiq_state *state, char *fmt, ...) ++{ ++ enum fiq_debug_level dbg_lvl_req = FIQDBG_ERR; ++ va_list args; ++ char text[17]; ++ hfnum_data_t hfnum = { .d32 = FIQ_READ(state->dwc_regs_base + 0x408) }; ++ ++ if((dbg_lvl & dbg_lvl_req) || dbg_lvl == FIQDBG_ERR) ++ { ++ snprintf(text, 9, " %4d:%1u ", hfnum.b.frnum/8, hfnum.b.frnum & 7); ++ va_start(args, fmt); ++ vsnprintf(text+8, 9, fmt, args); ++ va_end(args); ++ ++ memcpy(buffer + wptr, text, 16); ++ wptr = (wptr + 16) % sizeof(buffer); ++ } ++} ++ ++/** ++ * fiq_fsm_spin_lock() - ARMv6+ bare bones spinlock ++ * Must be called with local interrupts and FIQ disabled. ++ */ ++#if defined(CONFIG_ARCH_BCM2709) && defined(CONFIG_SMP) ++inline void fiq_fsm_spin_lock(fiq_lock_t *lock) ++{ ++ unsigned long tmp; ++ uint32_t newval; ++ fiq_lock_t lockval; ++ smp_mb__before_spinlock(); ++ /* Nested locking, yay. If we are on the same CPU as the fiq, then the disable ++ * will be sufficient. If we are on a different CPU, then the lock protects us. */ ++ prefetchw(&lock->slock); ++ asm volatile ( ++ "1: ldrex %0, [%3]\n" ++ " add %1, %0, %4\n" ++ " strex %2, %1, [%3]\n" ++ " teq %2, #0\n" ++ " bne 1b" ++ : "=&r" (lockval), "=&r" (newval), "=&r" (tmp) ++ : "r" (&lock->slock), "I" (1 << 16) ++ : "cc"); ++ ++ while (lockval.tickets.next != lockval.tickets.owner) { ++ wfe(); ++ lockval.tickets.owner = ACCESS_ONCE(lock->tickets.owner); ++ } ++ smp_mb(); ++} ++#else ++inline void fiq_fsm_spin_lock(fiq_lock_t *lock) { } ++#endif ++ ++/** ++ * fiq_fsm_spin_unlock() - ARMv6+ bare bones spinunlock ++ */ ++#if defined(CONFIG_ARCH_BCM2709) && defined(CONFIG_SMP) ++inline void fiq_fsm_spin_unlock(fiq_lock_t *lock) ++{ ++ smp_mb(); ++ lock->tickets.owner++; ++ dsb_sev(); ++} ++#else ++inline void fiq_fsm_spin_unlock(fiq_lock_t *lock) { } ++#endif ++ ++/** ++ * fiq_fsm_restart_channel() - Poke channel enable bit for a split transaction ++ * @channel: channel to re-enable ++ */ ++static void fiq_fsm_restart_channel(struct fiq_state *st, int n, int force) ++{ ++ hcchar_data_t hcchar = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR) }; ++ ++ hcchar.b.chen = 0; ++ if (st->channel[n].hcchar_copy.b.eptype & 0x1) { ++ hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) }; ++ /* Hardware bug workaround: update the ssplit index */ ++ if (st->channel[n].hcsplt_copy.b.spltena) ++ st->channel[n].expected_uframe = (hfnum.b.frnum + 1) & 0x3FFF; ++ ++ hcchar.b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1; ++ } ++ ++ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, hcchar.d32); ++ hcchar.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR); ++ hcchar.b.chen = 1; ++ ++ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, hcchar.d32); ++ fiq_print(FIQDBG_INT, st, "HCGO %01d %01d", n, force); ++} ++ ++/** ++ * fiq_fsm_setup_csplit() - Prepare a host channel for a CSplit transaction stage ++ * @st: Pointer to the channel's state ++ * @n : channel number ++ * ++ * Change host channel registers to perform a complete-split transaction. Being mindful of the ++ * endpoint direction, set control regs up correctly. ++ */ ++static void notrace fiq_fsm_setup_csplit(struct fiq_state *st, int n) ++{ ++ hcsplt_data_t hcsplt = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT) }; ++ hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) }; ++ ++ hcsplt.b.compsplt = 1; ++ if (st->channel[n].hcchar_copy.b.epdir == 1) { ++ // If IN, the CSPLIT result contains the data or a hub handshake. hctsiz = maxpacket. ++ hctsiz.b.xfersize = st->channel[n].hctsiz_copy.b.xfersize; ++ } else { ++ // If OUT, the CSPLIT result contains handshake only. ++ hctsiz.b.xfersize = 0; ++ } ++ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT, hcsplt.d32); ++ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32); ++ mb(); ++} ++ ++static inline int notrace fiq_get_xfer_len(struct fiq_state *st, int n) ++{ ++ /* The xfersize register is a bit wonky. For IN transfers, it decrements by the packet size. */ ++ hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) }; ++ ++ if (st->channel[n].hcchar_copy.b.epdir == 0) { ++ return st->channel[n].hctsiz_copy.b.xfersize; ++ } else { ++ return st->channel[n].hctsiz_copy.b.xfersize - hctsiz.b.xfersize; ++ } ++ ++} ++ ++ ++/** ++ * fiq_increment_dma_buf() - update DMA address for bounce buffers after a CSPLIT ++ * ++ * Of use only for IN periodic transfers. ++ */ ++static int notrace fiq_increment_dma_buf(struct fiq_state *st, int num_channels, int n) ++{ ++ hcdma_data_t hcdma; ++ int i = st->channel[n].dma_info.index; ++ int len; ++ struct fiq_dma_blob *blob = (struct fiq_dma_blob *) st->dma_base; ++ ++ len = fiq_get_xfer_len(st, n); ++ fiq_print(FIQDBG_INT, st, "LEN: %03d", len); ++ st->channel[n].dma_info.slot_len[i] = len; ++ i++; ++ if (i > 6) ++ BUG(); ++ ++ hcdma.d32 = (dma_addr_t) &blob->channel[n].index[i].buf[0]; ++ FIQ_WRITE(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32); ++ st->channel[n].dma_info.index = i; ++ return 0; ++} ++ ++/** ++ * fiq_reload_hctsiz() - for IN transactions, reset HCTSIZ ++ */ ++static void notrace fiq_fsm_reload_hctsiz(struct fiq_state *st, int n) ++{ ++ hctsiz_data_t hctsiz = { .d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ) }; ++ hctsiz.b.xfersize = st->channel[n].hctsiz_copy.b.xfersize; ++ hctsiz.b.pktcnt = 1; ++ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32); ++} ++ ++/** ++ * fiq_iso_out_advance() - update DMA address and split position bits ++ * for isochronous OUT transactions. ++ * ++ * Returns 1 if this is the last packet queued, 0 otherwise. Split-ALL and ++ * Split-BEGIN states are not handled - this is done when the transaction was queued. ++ * ++ * This function must only be called from the FIQ_ISO_OUT_ACTIVE state. ++ */ ++static int notrace fiq_iso_out_advance(struct fiq_state *st, int num_channels, int n) ++{ ++ hcsplt_data_t hcsplt; ++ hctsiz_data_t hctsiz; ++ hcdma_data_t hcdma; ++ struct fiq_dma_blob *blob = (struct fiq_dma_blob *) st->dma_base; ++ int last = 0; ++ int i = st->channel[n].dma_info.index; ++ ++ fiq_print(FIQDBG_INT, st, "ADV %01d %01d ", n, i); ++ i++; ++ if (i == 4) ++ last = 1; ++ if (st->channel[n].dma_info.slot_len[i+1] == 255) ++ last = 1; ++ ++ /* New DMA address - address of bounce buffer referred to in index */ ++ hcdma.d32 = (uint32_t) &blob->channel[n].index[i].buf[0]; ++ //hcdma.d32 = FIQ_READ(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n)); ++ //hcdma.d32 += st->channel[n].dma_info.slot_len[i]; ++ fiq_print(FIQDBG_INT, st, "LAST: %01d ", last); ++ fiq_print(FIQDBG_INT, st, "LEN: %03d", st->channel[n].dma_info.slot_len[i]); ++ hcsplt.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT); ++ hctsiz.d32 = FIQ_READ(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ); ++ hcsplt.b.xactpos = (last) ? ISOC_XACTPOS_END : ISOC_XACTPOS_MID; ++ /* Set up new packet length */ ++ hctsiz.b.pktcnt = 1; ++ hctsiz.b.xfersize = st->channel[n].dma_info.slot_len[i]; ++ fiq_print(FIQDBG_INT, st, "%08x", hctsiz.d32); ++ ++ st->channel[n].dma_info.index++; ++ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCSPLT, hcsplt.d32); ++ FIQ_WRITE(st->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, hctsiz.d32); ++ FIQ_WRITE(st->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32); ++ return last; ++} ++ ++/** ++ * fiq_fsm_tt_next_isoc() - queue next pending isochronous out start-split on a TT ++ * ++ * Despite the limitations of the DWC core, we can force a microframe pipeline of ++ * isochronous OUT start-split transactions while waiting for a corresponding other-type ++ * of endpoint to finish its CSPLITs. TTs have big periodic buffers therefore it ++ * is very unlikely that filling the start-split FIFO will cause data loss. ++ * This allows much better interleaving of transactions in an order-independent way- ++ * there is no requirement to prioritise isochronous, just a state-space search has ++ * to be performed on each periodic start-split complete interrupt. ++ */ ++static int notrace fiq_fsm_tt_next_isoc(struct fiq_state *st, int num_channels, int n) ++{ ++ int hub_addr = st->channel[n].hub_addr; ++ int port_addr = st->channel[n].port_addr; ++ int i, poked = 0; ++ for (i = 0; i < num_channels; i++) { ++ if (i == n || st->channel[i].fsm == FIQ_PASSTHROUGH) ++ continue; ++ if (st->channel[i].hub_addr == hub_addr && ++ st->channel[i].port_addr == port_addr) { ++ switch (st->channel[i].fsm) { ++ case FIQ_PER_ISO_OUT_PENDING: ++ if (st->channel[i].nrpackets == 1) { ++ st->channel[i].fsm = FIQ_PER_ISO_OUT_LAST; ++ } else { ++ st->channel[i].fsm = FIQ_PER_ISO_OUT_ACTIVE; ++ } ++ fiq_fsm_restart_channel(st, i, 0); ++ poked = 1; ++ break; ++ ++ default: ++ break; ++ } ++ } ++ if (poked) ++ break; ++ } ++ return poked; ++} ++ ++/** ++ * fiq_fsm_tt_in_use() - search for host channels using this TT ++ * @n: Channel to use as reference ++ * ++ */ ++int notrace noinline fiq_fsm_tt_in_use(struct fiq_state *st, int num_channels, int n) ++{ ++ int hub_addr = st->channel[n].hub_addr; ++ int port_addr = st->channel[n].port_addr; ++ int i, in_use = 0; ++ for (i = 0; i < num_channels; i++) { ++ if (i == n || st->channel[i].fsm == FIQ_PASSTHROUGH) ++ continue; ++ switch (st->channel[i].fsm) { ++ /* TT is reserved for channels that are in the middle of a periodic ++ * split transaction. ++ */ ++ case FIQ_PER_SSPLIT_STARTED: ++ case FIQ_PER_CSPLIT_WAIT: ++ case FIQ_PER_CSPLIT_NYET1: ++ //case FIQ_PER_CSPLIT_POLL: ++ case FIQ_PER_ISO_OUT_ACTIVE: ++ case FIQ_PER_ISO_OUT_LAST: ++ if (st->channel[i].hub_addr == hub_addr && ++ st->channel[i].port_addr == port_addr) { ++ in_use = 1; ++ } ++ break; ++ default: ++ break; ++ } ++ if (in_use) ++ break; ++ } ++ return in_use; ++} ++ ++/** ++ * fiq_fsm_more_csplits() - determine whether additional CSPLITs need ++ * to be issued for this IN transaction. ++ * ++ * We cannot tell the inbound PID of a data packet due to hardware limitations. ++ * we need to make an educated guess as to whether we need to queue another CSPLIT ++ * or not. A no-brainer is when we have received enough data to fill the endpoint ++ * size, but for endpoints that give variable-length data then we have to resort ++ * to heuristics. ++ * ++ * We also return whether this is the last CSPLIT to be queued, again based on ++ * heuristics. This is to allow a 1-uframe overlap of periodic split transactions. ++ * Note: requires at least 1 CSPLIT to have been performed prior to being called. ++ */ ++ ++/* ++ * We need some way of guaranteeing if a returned periodic packet of size X ++ * has a DATA0 PID. ++ * The heuristic value of 144 bytes assumes that the received data has maximal ++ * bit-stuffing and the clock frequency of the transmitting device is at the lowest ++ * permissible limit. If the transfer length results in a final packet size ++ * 144 < p <= 188, then an erroneous CSPLIT will be issued. ++ * Also used to ensure that an endpoint will nominally only return a single ++ * complete-split worth of data. ++ */ ++#define DATA0_PID_HEURISTIC 144 ++ ++static int notrace noinline fiq_fsm_more_csplits(struct fiq_state *state, int n, int *probably_last) ++{ ++ ++ int i; ++ int total_len = 0; ++ int more_needed = 1; ++ struct fiq_channel_state *st = &state->channel[n]; ++ ++ for (i = 0; i < st->dma_info.index; i++) { ++ total_len += st->dma_info.slot_len[i]; ++ } ++ ++ *probably_last = 0; ++ ++ if (st->hcchar_copy.b.eptype == 0x3) { ++ /* ++ * An interrupt endpoint will take max 2 CSPLITs. if we are receiving data ++ * then this is definitely the last CSPLIT. ++ */ ++ *probably_last = 1; ++ } else { ++ /* Isoc IN. This is a bit risky if we are the first transaction: ++ * we may have been held off slightly. */ ++ if (i > 1 && st->dma_info.slot_len[st->dma_info.index-1] <= DATA0_PID_HEURISTIC) { ++ more_needed = 0; ++ } ++ /* If in the next uframe we will receive enough data to fill the endpoint, ++ * then only issue 1 more csplit. ++ */ ++ if (st->hctsiz_copy.b.xfersize - total_len <= DATA0_PID_HEURISTIC) ++ *probably_last = 1; ++ } ++ ++ if (total_len >= st->hctsiz_copy.b.xfersize || ++ i == 6 || total_len == 0) ++ /* Note: due to bit stuffing it is possible to have > 6 CSPLITs for ++ * a single endpoint. Accepting more would completely break our scheduling mechanism though ++ * - in these extreme cases we will pass through a truncated packet. ++ */ ++ more_needed = 0; ++ ++ return more_needed; ++} ++ ++/** ++ * fiq_fsm_too_late() - Test transaction for lateness ++ * ++ * If a SSPLIT for a large IN transaction is issued too late in a frame, ++ * the hub will disable the port to the device and respond with ERR handshakes. ++ * The hub status endpoint will not reflect this change. ++ * Returns 1 if we will issue a SSPLIT that will result in a device babble. ++ */ ++int notrace fiq_fsm_too_late(struct fiq_state *st, int n) ++{ ++ int uframe; ++ hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) }; ++ uframe = hfnum.b.frnum & 0x7; ++ if ((uframe < 6) && (st->channel[n].nrpackets + 1 + uframe > 7)) { ++ return 1; ++ } else { ++ return 0; ++ } ++} ++ ++ ++/** ++ * fiq_fsm_start_next_periodic() - A half-arsed attempt at a microframe pipeline ++ * ++ * Search pending transactions in the start-split pending state and queue them. ++ * Don't queue packets in uframe .5 (comes out in .6) (USB2.0 11.18.4). ++ * Note: we specifically don't do isochronous OUT transactions first because better ++ * use of the TT's start-split fifo can be achieved by pipelining an IN before an OUT. ++ */ ++static void notrace noinline fiq_fsm_start_next_periodic(struct fiq_state *st, int num_channels) ++{ ++ int n; ++ hfnum_data_t hfnum = { .d32 = FIQ_READ(st->dwc_regs_base + HFNUM) }; ++ if ((hfnum.b.frnum & 0x7) == 5) ++ return; ++ for (n = 0; n < num_channels; n++) { ++ if (st->channel[n].fsm == FIQ_PER_SSPLIT_QUEUED) { ++ /* Check to see if any other transactions are using this TT */ ++ if(!fiq_fsm_tt_in_use(st, num_channels, n)) { ++ if (!fiq_fsm_too_late(st, n)) { ++ st->channel[n].fsm = FIQ_PER_SSPLIT_STARTED; ++ fiq_print(FIQDBG_INT, st, "NEXTPER "); ++ fiq_fsm_restart_channel(st, n, 0); ++ } else { ++ st->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT; ++ } ++ break; ++ } ++ } ++ } ++ for (n = 0; n < num_channels; n++) { ++ if (st->channel[n].fsm == FIQ_PER_ISO_OUT_PENDING) { ++ if (!fiq_fsm_tt_in_use(st, num_channels, n)) { ++ fiq_print(FIQDBG_INT, st, "NEXTISO "); ++ st->channel[n].fsm = FIQ_PER_ISO_OUT_ACTIVE; ++ fiq_fsm_restart_channel(st, n, 0); ++ break; ++ } ++ } ++ } ++} ++ ++/** ++ * fiq_fsm_update_hs_isoc() - update isochronous frame and transfer data ++ * @state: Pointer to fiq_state ++ * @n: Channel transaction is active on ++ * @hcint: Copy of host channel interrupt register ++ * ++ * Returns 0 if there are no more transactions for this HC to do, 1 ++ * otherwise. ++ */ ++static int notrace noinline fiq_fsm_update_hs_isoc(struct fiq_state *state, int n, hcint_data_t hcint) ++{ ++ struct fiq_channel_state *st = &state->channel[n]; ++ int xfer_len = 0, nrpackets = 0; ++ hcdma_data_t hcdma; ++ fiq_print(FIQDBG_INT, state, "HSISO %02d", n); ++ ++ xfer_len = fiq_get_xfer_len(state, n); ++ st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].actual_length = xfer_len; ++ ++ st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].status = hcint.d32; ++ ++ st->hs_isoc_info.index++; ++ if (st->hs_isoc_info.index == st->hs_isoc_info.nrframes) { ++ return 0; ++ } ++ ++ /* grab the next DMA address offset from the array */ ++ hcdma.d32 = st->hcdma_copy.d32 + st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].offset; ++ FIQ_WRITE(state->dwc_regs_base + HC_DMA + (HC_OFFSET * n), hcdma.d32); ++ ++ /* We need to set multi_count. This is a bit tricky - has to be set per-transaction as ++ * the core needs to be told to send the correct number. Caution: for IN transfers, ++ * this is always set to the maximum size of the endpoint. */ ++ xfer_len = st->hs_isoc_info.iso_desc[st->hs_isoc_info.index].length; ++ /* Integer divide in a FIQ: fun. FIXME: make this not suck */ ++ nrpackets = (xfer_len + st->hcchar_copy.b.mps - 1) / st->hcchar_copy.b.mps; ++ if (nrpackets == 0) ++ nrpackets = 1; ++ st->hcchar_copy.b.multicnt = nrpackets; ++ st->hctsiz_copy.b.pktcnt = nrpackets; ++ ++ /* Initial PID also needs to be set */ ++ if (st->hcchar_copy.b.epdir == 0) { ++ st->hctsiz_copy.b.xfersize = xfer_len; ++ switch (st->hcchar_copy.b.multicnt) { ++ case 1: ++ st->hctsiz_copy.b.pid = DWC_PID_DATA0; ++ break; ++ case 2: ++ case 3: ++ st->hctsiz_copy.b.pid = DWC_PID_MDATA; ++ break; ++ } ++ ++ } else { ++ switch (st->hcchar_copy.b.multicnt) { ++ st->hctsiz_copy.b.xfersize = nrpackets * st->hcchar_copy.b.mps; ++ case 1: ++ st->hctsiz_copy.b.pid = DWC_PID_DATA0; ++ break; ++ case 2: ++ st->hctsiz_copy.b.pid = DWC_PID_DATA1; ++ break; ++ case 3: ++ st->hctsiz_copy.b.pid = DWC_PID_DATA2; ++ break; ++ } ++ } ++ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCTSIZ, st->hctsiz_copy.d32); ++ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR, st->hcchar_copy.d32); ++ /* Channel is enabled on hcint handler exit */ ++ fiq_print(FIQDBG_INT, state, "HSISOOUT"); ++ return 1; ++} ++ ++ ++/** ++ * fiq_fsm_do_sof() - FSM start-of-frame interrupt handler ++ * @state: Pointer to the state struct passed from banked FIQ mode registers. ++ * @num_channels: set according to the DWC hardware configuration ++ * ++ * The SOF handler in FSM mode has two functions ++ * 1. Hold off SOF from causing schedule advancement in IRQ context if there's ++ * nothing to do ++ * 2. Advance certain FSM states that require either a microframe delay, or a microframe ++ * of holdoff. ++ * ++ * The second part is architecture-specific to mach-bcm2835 - ++ * a sane interrupt controller would have a mask register for ARM interrupt sources ++ * to be promoted to the nFIQ line, but it doesn't. Instead a single interrupt ++ * number (USB) can be enabled. This means that certain parts of the USB specification ++ * that require "wait a little while, then issue another packet" cannot be fulfilled with ++ * the timing granularity required to achieve optimal throughout. The workaround is to use ++ * the SOF "timer" (125uS) to perform this task. ++ */ ++static int notrace noinline fiq_fsm_do_sof(struct fiq_state *state, int num_channels) ++{ ++ hfnum_data_t hfnum = { .d32 = FIQ_READ(state->dwc_regs_base + HFNUM) }; ++ int n; ++ int kick_irq = 0; ++ ++ if ((hfnum.b.frnum & 0x7) == 1) { ++ /* We cannot issue csplits for transactions in the last frame past (n+1).1 ++ * Check to see if there are any transactions that are stale. ++ * Boot them out. ++ */ ++ for (n = 0; n < num_channels; n++) { ++ switch (state->channel[n].fsm) { ++ case FIQ_PER_CSPLIT_WAIT: ++ case FIQ_PER_CSPLIT_NYET1: ++ case FIQ_PER_CSPLIT_POLL: ++ case FIQ_PER_CSPLIT_LAST: ++ /* Check if we are no longer in the same full-speed frame. */ ++ if (((state->channel[n].expected_uframe & 0x3FFF) & ~0x7) < ++ (hfnum.b.frnum & ~0x7)) ++ state->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT; ++ break; ++ default: ++ break; ++ } ++ } ++ } ++ ++ for (n = 0; n < num_channels; n++) { ++ switch (state->channel[n].fsm) { ++ ++ case FIQ_NP_SSPLIT_RETRY: ++ case FIQ_NP_IN_CSPLIT_RETRY: ++ case FIQ_NP_OUT_CSPLIT_RETRY: ++ fiq_fsm_restart_channel(state, n, 0); ++ break; ++ ++ case FIQ_HS_ISOC_SLEEPING: ++ /* Is it time to wake this channel yet? */ ++ if (--state->channel[n].uframe_sleeps == 0) { ++ state->channel[n].fsm = FIQ_HS_ISOC_TURBO; ++ fiq_fsm_restart_channel(state, n, 0); ++ } ++ break; ++ ++ case FIQ_PER_SSPLIT_QUEUED: ++ if ((hfnum.b.frnum & 0x7) == 5) ++ break; ++ if(!fiq_fsm_tt_in_use(state, num_channels, n)) { ++ if (!fiq_fsm_too_late(state, n)) { ++ fiq_print(FIQDBG_INT, state, "SOF GO %01d", n); ++ fiq_fsm_restart_channel(state, n, 0); ++ state->channel[n].fsm = FIQ_PER_SSPLIT_STARTED; ++ } else { ++ /* Transaction cannot be started without risking a device babble error */ ++ state->channel[n].fsm = FIQ_PER_SPLIT_TIMEOUT; ++ state->haintmsk_saved.b2.chint &= ~(1 << n); ++ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, 0); ++ kick_irq |= 1; ++ } ++ } ++ break; ++ ++ case FIQ_PER_ISO_OUT_PENDING: ++ /* Ordinarily, this should be poked after the SSPLIT ++ * complete interrupt for a competing transfer on the same ++ * TT. Doesn't happen for aborted transactions though. ++ */ ++ if ((hfnum.b.frnum & 0x7) >= 5) ++ break; ++ if (!fiq_fsm_tt_in_use(state, num_channels, n)) { ++ /* Hardware bug. SOF can sometimes occur after the channel halt interrupt ++ * that caused this. ++ */ ++ fiq_fsm_restart_channel(state, n, 0); ++ fiq_print(FIQDBG_INT, state, "SOF ISOC"); ++ if (state->channel[n].nrpackets == 1) { ++ state->channel[n].fsm = FIQ_PER_ISO_OUT_LAST; ++ } else { ++ state->channel[n].fsm = FIQ_PER_ISO_OUT_ACTIVE; ++ } ++ } ++ break; ++ ++ case FIQ_PER_CSPLIT_WAIT: ++ /* we are guaranteed to be in this state if and only if the SSPLIT interrupt ++ * occurred when the bus transaction occurred. The SOF interrupt reversal bug ++ * will utterly bugger this up though. ++ */ ++ if (hfnum.b.frnum != state->channel[n].expected_uframe) { ++ fiq_print(FIQDBG_INT, state, "SOFCS %d ", n); ++ state->channel[n].fsm = FIQ_PER_CSPLIT_POLL; ++ fiq_fsm_restart_channel(state, n, 0); ++ fiq_fsm_start_next_periodic(state, num_channels); ++ ++ } ++ break; ++ ++ case FIQ_PER_SPLIT_TIMEOUT: ++ case FIQ_DEQUEUE_ISSUED: ++ /* Ugly: we have to force a HCD interrupt. ++ * Poke the mask for the channel in question. ++ * We will take a fake SOF because of this, but ++ * that's OK. ++ */ ++ state->haintmsk_saved.b2.chint &= ~(1 << n); ++ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, 0); ++ kick_irq |= 1; ++ break; ++ ++ default: ++ break; ++ } ++ } ++ ++ if (state->kick_np_queues || ++ dwc_frame_num_le(state->next_sched_frame, hfnum.b.frnum)) ++ kick_irq |= 1; ++ ++ return !kick_irq; ++} ++ ++ ++/** ++ * fiq_fsm_do_hcintr() - FSM host channel interrupt handler ++ * @state: Pointer to the FIQ state struct ++ * @num_channels: Number of channels as per hardware config ++ * @n: channel for which HAINT(i) was raised ++ * ++ * An important property is that only the CHHLT interrupt is unmasked. Unfortunately, AHBerr is as well. ++ */ ++static int notrace noinline fiq_fsm_do_hcintr(struct fiq_state *state, int num_channels, int n) ++{ ++ hcint_data_t hcint; ++ hcintmsk_data_t hcintmsk; ++ hcint_data_t hcint_probe; ++ hcchar_data_t hcchar; ++ int handled = 0; ++ int restart = 0; ++ int last_csplit = 0; ++ int start_next_periodic = 0; ++ struct fiq_channel_state *st = &state->channel[n]; ++ hfnum_data_t hfnum; ++ ++ hcint.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINT); ++ hcintmsk.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK); ++ hcint_probe.d32 = hcint.d32 & hcintmsk.d32; ++ ++ if (st->fsm != FIQ_PASSTHROUGH) { ++ fiq_print(FIQDBG_INT, state, "HC%01d ST%02d", n, st->fsm); ++ fiq_print(FIQDBG_INT, state, "%08x", hcint.d32); ++ } ++ ++ switch (st->fsm) { ++ ++ case FIQ_PASSTHROUGH: ++ case FIQ_DEQUEUE_ISSUED: ++ /* doesn't belong to us, kick it upstairs */ ++ break; ++ ++ case FIQ_PASSTHROUGH_ERRORSTATE: ++ /* We are here to emulate the error recovery mechanism of the dwc HCD. ++ * Several interrupts are unmasked if a previous transaction failed - it's ++ * death for the FIQ to attempt to handle them as the channel isn't halted. ++ * Emulate what the HCD does in this situation: mask and continue. ++ * The FSM has no other state setup so this has to be handled out-of-band. ++ */ ++ fiq_print(FIQDBG_ERR, state, "ERRST %02d", n); ++ if (hcint_probe.b.nak || hcint_probe.b.ack || hcint_probe.b.datatglerr) { ++ fiq_print(FIQDBG_ERR, state, "RESET %02d", n); ++ /* In some random cases we can get a NAK interrupt coincident with a Xacterr ++ * interrupt, after the device has disappeared. ++ */ ++ if (!hcint.b.xacterr) ++ st->nr_errors = 0; ++ hcintmsk.b.nak = 0; ++ hcintmsk.b.ack = 0; ++ hcintmsk.b.datatglerr = 0; ++ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINTMSK, hcintmsk.d32); ++ return 1; ++ } ++ if (hcint_probe.b.chhltd) { ++ fiq_print(FIQDBG_ERR, state, "CHHLT %02d", n); ++ fiq_print(FIQDBG_ERR, state, "%08x", hcint.d32); ++ return 0; ++ } ++ break; ++ ++ /* Non-periodic state groups */ ++ case FIQ_NP_SSPLIT_STARTED: ++ case FIQ_NP_SSPLIT_RETRY: ++ /* Got a HCINT for a NP SSPLIT. Expected ACK / NAK / fail */ ++ if (hcint.b.ack) { ++ /* SSPLIT complete. For OUT, the data has been sent. For IN, the LS transaction ++ * will start shortly. SOF needs to kick the transaction to prevent a NYET flood. ++ */ ++ if(st->hcchar_copy.b.epdir == 1) ++ st->fsm = FIQ_NP_IN_CSPLIT_RETRY; ++ else ++ st->fsm = FIQ_NP_OUT_CSPLIT_RETRY; ++ st->nr_errors = 0; ++ handled = 1; ++ fiq_fsm_setup_csplit(state, n); ++ } else if (hcint.b.nak) { ++ // No buffer space in TT. Retry on a uframe boundary. ++ st->fsm = FIQ_NP_SSPLIT_RETRY; ++ handled = 1; ++ } else if (hcint.b.xacterr) { ++ // The only other one we care about is xacterr. This implies HS bus error - retry. ++ st->nr_errors++; ++ st->fsm = FIQ_NP_SSPLIT_RETRY; ++ if (st->nr_errors >= 3) { ++ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; ++ } else { ++ handled = 1; ++ restart = 1; ++ } ++ } else { ++ st->fsm = FIQ_NP_SPLIT_LS_ABORTED; ++ handled = 0; ++ restart = 0; ++ } ++ break; ++ ++ case FIQ_NP_IN_CSPLIT_RETRY: ++ /* Received a CSPLIT done interrupt. ++ * Expected Data/NAK/STALL/NYET for IN. ++ */ ++ if (hcint.b.xfercomp) { ++ /* For IN, data is present. */ ++ st->fsm = FIQ_NP_SPLIT_DONE; ++ } else if (hcint.b.nak) { ++ /* no endpoint data. Punt it upstairs */ ++ st->fsm = FIQ_NP_SPLIT_DONE; ++ } else if (hcint.b.nyet) { ++ /* CSPLIT NYET - retry on a uframe boundary. */ ++ handled = 1; ++ st->nr_errors = 0; ++ } else if (hcint.b.datatglerr) { ++ /* data toggle errors do not set the xfercomp bit. */ ++ st->fsm = FIQ_NP_SPLIT_LS_ABORTED; ++ } else if (hcint.b.xacterr) { ++ /* HS error. Retry immediate */ ++ st->fsm = FIQ_NP_IN_CSPLIT_RETRY; ++ st->nr_errors++; ++ if (st->nr_errors >= 3) { ++ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; ++ } else { ++ handled = 1; ++ restart = 1; ++ } ++ } else if (hcint.b.stall || hcint.b.bblerr) { ++ /* A STALL implies either a LS bus error or a genuine STALL. */ ++ st->fsm = FIQ_NP_SPLIT_LS_ABORTED; ++ } else { ++ /* Hardware bug. It's possible in some cases to ++ * get a channel halt with nothing else set when ++ * the response was a NYET. Treat as local 3-strikes retry. ++ */ ++ hcint_data_t hcint_test = hcint; ++ hcint_test.b.chhltd = 0; ++ if (!hcint_test.d32) { ++ st->nr_errors++; ++ if (st->nr_errors >= 3) { ++ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; ++ } else { ++ handled = 1; ++ } ++ } else { ++ /* Bail out if something unexpected happened */ ++ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; ++ } ++ } ++ break; ++ ++ case FIQ_NP_OUT_CSPLIT_RETRY: ++ /* Received a CSPLIT done interrupt. ++ * Expected ACK/NAK/STALL/NYET/XFERCOMP for OUT.*/ ++ if (hcint.b.xfercomp) { ++ st->fsm = FIQ_NP_SPLIT_DONE; ++ } else if (hcint.b.nak) { ++ // The HCD will implement the holdoff on frame boundaries. ++ st->fsm = FIQ_NP_SPLIT_DONE; ++ } else if (hcint.b.nyet) { ++ // Hub still processing. ++ st->fsm = FIQ_NP_OUT_CSPLIT_RETRY; ++ handled = 1; ++ st->nr_errors = 0; ++ //restart = 1; ++ } else if (hcint.b.xacterr) { ++ /* HS error. retry immediate */ ++ st->fsm = FIQ_NP_OUT_CSPLIT_RETRY; ++ st->nr_errors++; ++ if (st->nr_errors >= 3) { ++ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; ++ } else { ++ handled = 1; ++ restart = 1; ++ } ++ } else if (hcint.b.stall) { ++ /* LS bus error or genuine stall */ ++ st->fsm = FIQ_NP_SPLIT_LS_ABORTED; ++ } else { ++ /* ++ * Hardware bug. It's possible in some cases to get a ++ * channel halt with nothing else set when the response was a NYET. ++ * Treat as local 3-strikes retry. ++ */ ++ hcint_data_t hcint_test = hcint; ++ hcint_test.b.chhltd = 0; ++ if (!hcint_test.d32) { ++ st->nr_errors++; ++ if (st->nr_errors >= 3) { ++ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; ++ } else { ++ handled = 1; ++ } ++ } else { ++ // Something unexpected happened. AHBerror or babble perhaps. Let the IRQ deal with it. ++ st->fsm = FIQ_NP_SPLIT_HS_ABORTED; ++ } ++ } ++ break; ++ ++ /* Periodic split states (except isoc out) */ ++ case FIQ_PER_SSPLIT_STARTED: ++ /* Expect an ACK or failure for SSPLIT */ ++ if (hcint.b.ack) { ++ /* ++ * SSPLIT transfer complete interrupt - the generation of this interrupt is fraught with bugs. ++ * For a packet queued in microframe n-3 to appear in n-2, if the channel is enabled near the EOF1 ++ * point for microframe n-3, the packet will not appear on the bus until microframe n. ++ * Additionally, the generation of the actual interrupt is dodgy. For a packet appearing on the bus ++ * in microframe n, sometimes the interrupt is generated immediately. Sometimes, it appears in n+1 ++ * coincident with SOF for n+1. ++ * SOF is also buggy. It can sometimes be raised AFTER the first bus transaction has taken place. ++ * These appear to be caused by timing/clock crossing bugs within the core itself. ++ * State machine workaround. ++ */ ++ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM); ++ hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR); ++ fiq_fsm_setup_csplit(state, n); ++ /* Poke the oddfrm bit. If we are equivalent, we received the interrupt at the correct ++ * time. If not, then we're in the next SOF. ++ */ ++ if ((hfnum.b.frnum & 0x1) == hcchar.b.oddfrm) { ++ fiq_print(FIQDBG_INT, state, "CSWAIT %01d", n); ++ st->expected_uframe = hfnum.b.frnum; ++ st->fsm = FIQ_PER_CSPLIT_WAIT; ++ } else { ++ fiq_print(FIQDBG_INT, state, "CSPOL %01d", n); ++ /* For isochronous IN endpoints, ++ * we need to hold off if we are expecting a lot of data */ ++ if (st->hcchar_copy.b.mps < DATA0_PID_HEURISTIC) { ++ start_next_periodic = 1; ++ } ++ /* Danger will robinson: we are in a broken state. If our first interrupt after ++ * this is a NYET, it will be delayed by 1 uframe and result in an unrecoverable ++ * lag. Unmask the NYET interrupt. ++ */ ++ st->expected_uframe = (hfnum.b.frnum + 1) & 0x3FFF; ++ st->fsm = FIQ_PER_CSPLIT_BROKEN_NYET1; ++ restart = 1; ++ } ++ handled = 1; ++ } else if (hcint.b.xacterr) { ++ /* 3-strikes retry is enabled, we have hit our max nr_errors */ ++ st->fsm = FIQ_PER_SPLIT_HS_ABORTED; ++ start_next_periodic = 1; ++ } else { ++ st->fsm = FIQ_PER_SPLIT_HS_ABORTED; ++ start_next_periodic = 1; ++ } ++ /* We can now queue the next isochronous OUT transaction, if one is pending. */ ++ if(fiq_fsm_tt_next_isoc(state, num_channels, n)) { ++ fiq_print(FIQDBG_INT, state, "NEXTISO "); ++ } ++ break; ++ ++ case FIQ_PER_CSPLIT_NYET1: ++ /* First CSPLIT attempt was a NYET. If we get a subsequent NYET, ++ * we are too late and the TT has dropped its CSPLIT fifo. ++ */ ++ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM); ++ hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR); ++ start_next_periodic = 1; ++ if (hcint.b.nak) { ++ st->fsm = FIQ_PER_SPLIT_DONE; ++ } else if (hcint.b.xfercomp) { ++ fiq_increment_dma_buf(state, num_channels, n); ++ st->fsm = FIQ_PER_CSPLIT_POLL; ++ st->nr_errors = 0; ++ if (fiq_fsm_more_csplits(state, n, &last_csplit)) { ++ handled = 1; ++ restart = 1; ++ if (!last_csplit) ++ start_next_periodic = 0; ++ } else { ++ st->fsm = FIQ_PER_SPLIT_DONE; ++ } ++ } else if (hcint.b.nyet) { ++ /* Doh. Data lost. */ ++ st->fsm = FIQ_PER_SPLIT_NYET_ABORTED; ++ } else if (hcint.b.xacterr || hcint.b.stall || hcint.b.bblerr) { ++ st->fsm = FIQ_PER_SPLIT_LS_ABORTED; ++ } else { ++ st->fsm = FIQ_PER_SPLIT_HS_ABORTED; ++ } ++ break; ++ ++ case FIQ_PER_CSPLIT_BROKEN_NYET1: ++ /* ++ * we got here because our host channel is in the delayed-interrupt ++ * state and we cannot take a NYET interrupt any later than when it ++ * occurred. Disable then re-enable the channel if this happens to force ++ * CSPLITs to occur at the right time. ++ */ ++ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM); ++ hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR); ++ fiq_print(FIQDBG_INT, state, "BROK: %01d ", n); ++ if (hcint.b.nak) { ++ st->fsm = FIQ_PER_SPLIT_DONE; ++ start_next_periodic = 1; ++ } else if (hcint.b.xfercomp) { ++ fiq_increment_dma_buf(state, num_channels, n); ++ if (fiq_fsm_more_csplits(state, n, &last_csplit)) { ++ st->fsm = FIQ_PER_CSPLIT_POLL; ++ handled = 1; ++ restart = 1; ++ start_next_periodic = 1; ++ /* Reload HCTSIZ for the next transfer */ ++ fiq_fsm_reload_hctsiz(state, n); ++ if (!last_csplit) ++ start_next_periodic = 0; ++ } else { ++ st->fsm = FIQ_PER_SPLIT_DONE; ++ } ++ } else if (hcint.b.nyet) { ++ st->fsm = FIQ_PER_SPLIT_NYET_ABORTED; ++ start_next_periodic = 1; ++ } else if (hcint.b.xacterr || hcint.b.stall || hcint.b.bblerr) { ++ /* Local 3-strikes retry is handled by the core. This is a ERR response.*/ ++ st->fsm = FIQ_PER_SPLIT_LS_ABORTED; ++ } else { ++ st->fsm = FIQ_PER_SPLIT_HS_ABORTED; ++ } ++ break; ++ ++ case FIQ_PER_CSPLIT_POLL: ++ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM); ++ hcchar.d32 = FIQ_READ(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCCHAR); ++ start_next_periodic = 1; ++ if (hcint.b.nak) { ++ st->fsm = FIQ_PER_SPLIT_DONE; ++ } else if (hcint.b.xfercomp) { ++ fiq_increment_dma_buf(state, num_channels, n); ++ if (fiq_fsm_more_csplits(state, n, &last_csplit)) { ++ handled = 1; ++ restart = 1; ++ /* Reload HCTSIZ for the next transfer */ ++ fiq_fsm_reload_hctsiz(state, n); ++ if (!last_csplit) ++ start_next_periodic = 0; ++ } else { ++ st->fsm = FIQ_PER_SPLIT_DONE; ++ } ++ } else if (hcint.b.nyet) { ++ /* Are we a NYET after the first data packet? */ ++ if (st->nrpackets == 0) { ++ st->fsm = FIQ_PER_CSPLIT_NYET1; ++ handled = 1; ++ restart = 1; ++ } else { ++ /* We got a NYET when polling CSPLITs. Can happen ++ * if our heuristic fails, or if someone disables us ++ * for any significant length of time. ++ */ ++ if (st->nr_errors >= 3) { ++ st->fsm = FIQ_PER_SPLIT_NYET_ABORTED; ++ } else { ++ st->fsm = FIQ_PER_SPLIT_DONE; ++ } ++ } ++ } else if (hcint.b.xacterr || hcint.b.stall || hcint.b.bblerr) { ++ /* For xacterr, Local 3-strikes retry is handled by the core. This is a ERR response.*/ ++ st->fsm = FIQ_PER_SPLIT_LS_ABORTED; ++ } else { ++ st->fsm = FIQ_PER_SPLIT_HS_ABORTED; ++ } ++ break; ++ ++ case FIQ_HS_ISOC_TURBO: ++ if (fiq_fsm_update_hs_isoc(state, n, hcint)) { ++ /* more transactions to come */ ++ handled = 1; ++ fiq_print(FIQDBG_INT, state, "HSISO M "); ++ /* For strided transfers, put ourselves to sleep */ ++ if (st->hs_isoc_info.stride > 1) { ++ st->uframe_sleeps = st->hs_isoc_info.stride - 1; ++ st->fsm = FIQ_HS_ISOC_SLEEPING; ++ } else { ++ restart = 1; ++ } ++ } else { ++ st->fsm = FIQ_HS_ISOC_DONE; ++ fiq_print(FIQDBG_INT, state, "HSISO F "); ++ } ++ break; ++ ++ case FIQ_HS_ISOC_ABORTED: ++ /* This abort is called by the driver rewriting the state mid-transaction ++ * which allows the dequeue mechanism to work more effectively. ++ */ ++ break; ++ ++ case FIQ_PER_ISO_OUT_ACTIVE: ++ if (hcint.b.ack) { ++ if(fiq_iso_out_advance(state, num_channels, n)) { ++ /* last OUT transfer */ ++ st->fsm = FIQ_PER_ISO_OUT_LAST; ++ /* ++ * Assuming the periodic FIFO in the dwc core ++ * actually does its job properly, we can queue ++ * the next ssplit now and in theory, the wire ++ * transactions will be in-order. ++ */ ++ // No it doesn't. It appears to process requests in host channel order. ++ //start_next_periodic = 1; ++ } ++ handled = 1; ++ restart = 1; ++ } else { ++ /* ++ * Isochronous transactions carry on regardless. Log the error ++ * and continue. ++ */ ++ //explode += 1; ++ st->nr_errors++; ++ if(fiq_iso_out_advance(state, num_channels, n)) { ++ st->fsm = FIQ_PER_ISO_OUT_LAST; ++ //start_next_periodic = 1; ++ } ++ handled = 1; ++ restart = 1; ++ } ++ break; ++ ++ case FIQ_PER_ISO_OUT_LAST: ++ if (hcint.b.ack) { ++ /* All done here */ ++ st->fsm = FIQ_PER_ISO_OUT_DONE; ++ } else { ++ st->fsm = FIQ_PER_ISO_OUT_DONE; ++ st->nr_errors++; ++ } ++ start_next_periodic = 1; ++ break; ++ ++ case FIQ_PER_SPLIT_TIMEOUT: ++ /* SOF kicked us because we overran. */ ++ start_next_periodic = 1; ++ break; ++ ++ default: ++ break; ++ } ++ ++ if (handled) { ++ FIQ_WRITE(state->dwc_regs_base + HC_START + (HC_OFFSET * n) + HCINT, hcint.d32); ++ } else { ++ /* Copy the regs into the state so the IRQ knows what to do */ ++ st->hcint_copy.d32 = hcint.d32; ++ } ++ ++ if (restart) { ++ /* Restart always implies handled. */ ++ if (restart == 2) { ++ /* For complete-split INs, the show must go on. ++ * Force a channel restart */ ++ fiq_fsm_restart_channel(state, n, 1); ++ } else { ++ fiq_fsm_restart_channel(state, n, 0); ++ } ++ } ++ if (start_next_periodic) { ++ fiq_fsm_start_next_periodic(state, num_channels); ++ } ++ if (st->fsm != FIQ_PASSTHROUGH) ++ fiq_print(FIQDBG_INT, state, "FSMOUT%02d", st->fsm); ++ ++ return handled; ++} ++ ++ ++/** ++ * dwc_otg_fiq_fsm() - Flying State Machine (monster) FIQ ++ * @state: pointer to state struct passed from the banked FIQ mode registers. ++ * @num_channels: set according to the DWC hardware configuration ++ * @dma: pointer to DMA bounce buffers for split transaction slots ++ * ++ * The FSM FIQ performs the low-level tasks that normally would be performed by the microcode ++ * inside an EHCI or similar host controller regarding split transactions. The DWC core ++ * interrupts each and every time a split transaction packet is received or sent successfully. ++ * This results in either an interrupt storm when everything is working "properly", or ++ * the interrupt latency of the system in general breaks time-sensitive periodic split ++ * transactions. Pushing the low-level, but relatively easy state machine work into the FIQ ++ * solves these problems. ++ * ++ * Return: void ++ */ ++void notrace dwc_otg_fiq_fsm(struct fiq_state *state, int num_channels) ++{ ++ gintsts_data_t gintsts, gintsts_handled; ++ gintmsk_data_t gintmsk; ++ //hfnum_data_t hfnum; ++ haint_data_t haint, haint_handled; ++ haintmsk_data_t haintmsk; ++ int kick_irq = 0; ++ ++ gintsts_handled.d32 = 0; ++ haint_handled.d32 = 0; ++ ++ fiq_fsm_spin_lock(&state->lock); ++ gintsts.d32 = FIQ_READ(state->dwc_regs_base + GINTSTS); ++ gintmsk.d32 = FIQ_READ(state->dwc_regs_base + GINTMSK); ++ gintsts.d32 &= gintmsk.d32; ++ ++ if (gintsts.b.sofintr) { ++ /* For FSM mode, SOF is required to keep the state machine advance for ++ * certain stages of the periodic pipeline. It's death to mask this ++ * interrupt in that case. ++ */ ++ ++ if (!fiq_fsm_do_sof(state, num_channels)) { ++ /* Kick IRQ once. Queue advancement means that all pending transactions ++ * will get serviced when the IRQ finally executes. ++ */ ++ if (state->gintmsk_saved.b.sofintr == 1) ++ kick_irq |= 1; ++ state->gintmsk_saved.b.sofintr = 0; ++ } ++ gintsts_handled.b.sofintr = 1; ++ } ++ ++ if (gintsts.b.hcintr) { ++ int i; ++ haint.d32 = FIQ_READ(state->dwc_regs_base + HAINT); ++ haintmsk.d32 = FIQ_READ(state->dwc_regs_base + HAINTMSK); ++ haint.d32 &= haintmsk.d32; ++ haint_handled.d32 = 0; ++ for (i=0; ihaintmsk_saved.b2.chint &= ~(1 << i); ++ } else { ++ /* do_hcintr cleaned up after itself, but clear haint */ ++ haint_handled.b2.chint |= (1 << i); ++ } ++ } ++ } ++ ++ if (haint_handled.b2.chint) { ++ FIQ_WRITE(state->dwc_regs_base + HAINT, haint_handled.d32); ++ } ++ ++ if (haintmsk.d32 != (haintmsk.d32 & state->haintmsk_saved.d32)) { ++ /* ++ * This is necessary to avoid multiple retriggers of the MPHI in the case ++ * where interrupts are held off and HCINTs start to pile up. ++ * Only wake up the IRQ if a new interrupt came in, was not handled and was ++ * masked. ++ */ ++ haintmsk.d32 &= state->haintmsk_saved.d32; ++ FIQ_WRITE(state->dwc_regs_base + HAINTMSK, haintmsk.d32); ++ kick_irq |= 1; ++ } ++ /* Top-Level interrupt - always handled because it's level-sensitive */ ++ gintsts_handled.b.hcintr = 1; ++ } ++ ++ ++ /* Clear the bits in the saved register that were not handled but were triggered. */ ++ state->gintmsk_saved.d32 &= ~(gintsts.d32 & ~gintsts_handled.d32); ++ ++ /* FIQ didn't handle something - mask has changed - write new mask */ ++ if (gintmsk.d32 != (gintmsk.d32 & state->gintmsk_saved.d32)) { ++ gintmsk.d32 &= state->gintmsk_saved.d32; ++ gintmsk.b.sofintr = 1; ++ FIQ_WRITE(state->dwc_regs_base + GINTMSK, gintmsk.d32); ++// fiq_print(FIQDBG_INT, state, "KICKGINT"); ++// fiq_print(FIQDBG_INT, state, "%08x", gintmsk.d32); ++// fiq_print(FIQDBG_INT, state, "%08x", state->gintmsk_saved.d32); ++ kick_irq |= 1; ++ } ++ ++ if (gintsts_handled.d32) { ++ /* Only applies to edge-sensitive bits in GINTSTS */ ++ FIQ_WRITE(state->dwc_regs_base + GINTSTS, gintsts_handled.d32); ++ } ++ ++ /* We got an interrupt, didn't handle it. */ ++ if (kick_irq) { ++ state->mphi_int_count++; ++ FIQ_WRITE(state->mphi_regs.outdda, (int) state->dummy_send); ++ FIQ_WRITE(state->mphi_regs.outddb, (1<<29)); ++ ++ } ++ state->fiq_done++; ++ mb(); ++ fiq_fsm_spin_unlock(&state->lock); ++} ++ ++ ++/** ++ * dwc_otg_fiq_nop() - FIQ "lite" ++ * @state: pointer to state struct passed from the banked FIQ mode registers. ++ * ++ * The "nop" handler does not intervene on any interrupts other than SOF. ++ * It is limited in scope to deciding at each SOF if the IRQ SOF handler (which deals ++ * with non-periodic/periodic queues) needs to be kicked. ++ * ++ * This is done to hold off the SOF interrupt, which occurs at a rate of 8000 per second. ++ * ++ * Return: void ++ */ ++void notrace dwc_otg_fiq_nop(struct fiq_state *state) ++{ ++ gintsts_data_t gintsts, gintsts_handled; ++ gintmsk_data_t gintmsk; ++ hfnum_data_t hfnum; ++ ++ fiq_fsm_spin_lock(&state->lock); ++ hfnum.d32 = FIQ_READ(state->dwc_regs_base + HFNUM); ++ gintsts.d32 = FIQ_READ(state->dwc_regs_base + GINTSTS); ++ gintmsk.d32 = FIQ_READ(state->dwc_regs_base + GINTMSK); ++ gintsts.d32 &= gintmsk.d32; ++ gintsts_handled.d32 = 0; ++ ++ if (gintsts.b.sofintr) { ++ if (!state->kick_np_queues && ++ dwc_frame_num_gt(state->next_sched_frame, hfnum.b.frnum)) { ++ /* SOF handled, no work to do, just ACK interrupt */ ++ gintsts_handled.b.sofintr = 1; ++ } else { ++ /* Kick IRQ */ ++ state->gintmsk_saved.b.sofintr = 0; ++ } ++ } ++ ++ /* Reset handled interrupts */ ++ if(gintsts_handled.d32) { ++ FIQ_WRITE(state->dwc_regs_base + GINTSTS, gintsts_handled.d32); ++ } ++ ++ /* Clear the bits in the saved register that were not handled but were triggered. */ ++ state->gintmsk_saved.d32 &= ~(gintsts.d32 & ~gintsts_handled.d32); ++ ++ /* We got an interrupt, didn't handle it and want to mask it */ ++ if (~(state->gintmsk_saved.d32)) { ++ state->mphi_int_count++; ++ gintmsk.d32 &= state->gintmsk_saved.d32; ++ FIQ_WRITE(state->dwc_regs_base + GINTMSK, gintmsk.d32); ++ /* Force a clear before another dummy send */ ++ FIQ_WRITE(state->mphi_regs.intstat, (1<<29)); ++ FIQ_WRITE(state->mphi_regs.outdda, (int) state->dummy_send); ++ FIQ_WRITE(state->mphi_regs.outddb, (1<<29)); ++ ++ } ++ state->fiq_done++; ++ mb(); ++ fiq_fsm_spin_unlock(&state->lock); ++} +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h 2015-11-29 09:42:39.919098694 +0100 +@@ -0,0 +1,370 @@ ++/* ++ * dwc_otg_fiq_fsm.h - Finite state machine FIQ header definitions ++ * ++ * Copyright (c) 2013 Raspberry Pi Foundation ++ * ++ * Author: Jonathan Bell ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of Raspberry Pi nor the ++ * names of its contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++ * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY ++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * This FIQ implements functionality that performs split transactions on ++ * the dwc_otg hardware without any outside intervention. A split transaction ++ * is "queued" by nominating a specific host channel to perform the entirety ++ * of a split transaction. This FIQ will then perform the microframe-precise ++ * scheduling required in each phase of the transaction until completion. ++ * ++ * The FIQ functionality has been surgically implanted into the Synopsys ++ * vendor-provided driver. ++ * ++ */ ++ ++#ifndef DWC_OTG_FIQ_FSM_H_ ++#define DWC_OTG_FIQ_FSM_H_ ++ ++#include "dwc_otg_regs.h" ++#include "dwc_otg_cil.h" ++#include "dwc_otg_hcd.h" ++#include ++#include ++#include ++#include ++ ++#if 0 ++#define FLAME_ON(x) \ ++do { \ ++ int gpioreg; \ ++ \ ++ gpioreg = readl(__io_address(0x20200000+0x8)); \ ++ gpioreg &= ~(7 << (x-20)*3); \ ++ gpioreg |= 0x1 << (x-20)*3; \ ++ writel(gpioreg, __io_address(0x20200000+0x8)); \ ++ \ ++ writel(1< 1, SOF wakes up the isochronous FSM */ ++ FIQ_HS_ISOC_SLEEPING = 24, ++ FIQ_HS_ISOC_DONE = 25, ++ FIQ_HS_ISOC_ABORTED = 26, ++ FIQ_DEQUEUE_ISSUED = 30, ++ FIQ_TEST = 32, ++}; ++ ++struct fiq_stack { ++ int magic1; ++ uint8_t stack[2048]; ++ int magic2; ++}; ++ ++ ++/** ++ * struct fiq_dma_info - DMA bounce buffer utilisation information (per-channel) ++ * @index: Number of slots reported used for IN transactions / number of slots ++ * transmitted for an OUT transaction ++ * @slot_len[6]: Number of actual transfer bytes in each slot (255 if unused) ++ * ++ * Split transaction transfers can have variable length depending on other bus ++ * traffic. The OTG core DMA engine requires 4-byte aligned addresses therefore ++ * each transaction needs a guaranteed aligned address. A maximum of 6 split transfers ++ * can happen per-frame. ++ */ ++struct fiq_dma_info { ++ u8 index; ++ u8 slot_len[6]; ++}; ++ ++struct __attribute__((packed)) fiq_split_dma_slot { ++ u8 buf[188]; ++}; ++ ++struct fiq_dma_channel { ++ struct __attribute__((packed)) fiq_split_dma_slot index[6]; ++}; ++ ++struct fiq_dma_blob { ++ struct __attribute__((packed)) fiq_dma_channel channel[0]; ++}; ++ ++/** ++ * struct fiq_hs_isoc_info - USB2.0 isochronous data ++ * @iso_frame: Pointer to the array of OTG URB iso_frame_descs. ++ * @nrframes: Total length of iso_frame_desc array ++ * @index: Current index (FIQ-maintained) ++ * @stride: Interval in uframes between HS isoc transactions ++ */ ++struct fiq_hs_isoc_info { ++ struct dwc_otg_hcd_iso_packet_desc *iso_desc; ++ unsigned int nrframes; ++ unsigned int index; ++ unsigned int stride; ++}; ++ ++/** ++ * struct fiq_channel_state - FIQ state machine storage ++ * @fsm: Current state of the channel as understood by the FIQ ++ * @nr_errors: Number of transaction errors on this split-transaction ++ * @hub_addr: SSPLIT/CSPLIT destination hub ++ * @port_addr: SSPLIT/CSPLIT destination port - always 1 if single TT hub ++ * @nrpackets: For isoc OUT, the number of split-OUT packets to transmit. For ++ * split-IN, number of CSPLIT data packets that were received. ++ * @hcchar_copy: ++ * @hcsplt_copy: ++ * @hcintmsk_copy: ++ * @hctsiz_copy: Copies of the host channel registers. ++ * For use as scratch, or for returning state. ++ * ++ * The fiq_channel_state is state storage between interrupts for a host channel. The ++ * FSM state is stored here. Members of this structure must only be set up by the ++ * driver prior to enabling the FIQ for this host channel, and not touched until the FIQ ++ * has updated the state to either a COMPLETE state group or ABORT state group. ++ */ ++ ++struct fiq_channel_state { ++ enum fiq_fsm_state fsm; ++ unsigned int nr_errors; ++ unsigned int hub_addr; ++ unsigned int port_addr; ++ /* Hardware bug workaround: sometimes channel halt interrupts are ++ * delayed until the next SOF. Keep track of when we expected to get interrupted. */ ++ unsigned int expected_uframe; ++ /* number of uframes remaining (for interval > 1 HS isoc transfers) before next transfer */ ++ unsigned int uframe_sleeps; ++ /* in/out for communicating number of dma buffers used, or number of ISOC to do */ ++ unsigned int nrpackets; ++ struct fiq_dma_info dma_info; ++ struct fiq_hs_isoc_info hs_isoc_info; ++ /* Copies of HC registers - in/out communication from/to IRQ handler ++ * and for ease of channel setup. A bit of mungeing is performed - for ++ * example the hctsiz.b.maxp is _always_ the max packet size of the endpoint. ++ */ ++ hcchar_data_t hcchar_copy; ++ hcsplt_data_t hcsplt_copy; ++ hcint_data_t hcint_copy; ++ hcintmsk_data_t hcintmsk_copy; ++ hctsiz_data_t hctsiz_copy; ++ hcdma_data_t hcdma_copy; ++}; ++ ++/** ++ * struct fiq_state - top-level FIQ state machine storage ++ * @mphi_regs: virtual address of the MPHI peripheral register file ++ * @dwc_regs_base: virtual address of the base of the DWC core register file ++ * @dma_base: physical address for the base of the DMA bounce buffers ++ * @dummy_send: Scratch area for sending a fake message to the MPHI peripheral ++ * @gintmsk_saved: Top-level mask of interrupts that the FIQ has not handled. ++ * Used for determining which interrupts fired to set off the IRQ handler. ++ * @haintmsk_saved: Mask of interrupts from host channels that the FIQ did not handle internally. ++ * @np_count: Non-periodic transactions in the active queue ++ * @np_sent: Count of non-periodic transactions that have completed ++ * @next_sched_frame: For periodic transactions handled by the driver's SOF-driven queuing mechanism, ++ * this is the next frame on which a SOF interrupt is required. Used to hold off ++ * passing SOF through to the driver until necessary. ++ * @channel[n]: Per-channel FIQ state. Allocated during init depending on the number of host ++ * channels configured into the core logic. ++ * ++ * This is passed as the first argument to the dwc_otg_fiq_fsm top-level FIQ handler from the asm stub. ++ * It contains top-level state information. ++ */ ++struct fiq_state { ++ fiq_lock_t lock; ++ mphi_regs_t mphi_regs; ++ void *dwc_regs_base; ++ dma_addr_t dma_base; ++ struct fiq_dma_blob *fiq_dmab; ++ void *dummy_send; ++ gintmsk_data_t gintmsk_saved; ++ haintmsk_data_t haintmsk_saved; ++ int mphi_int_count; ++ unsigned int fiq_done; ++ unsigned int kick_np_queues; ++ unsigned int next_sched_frame; ++#ifdef FIQ_DEBUG ++ char * buffer; ++ unsigned int bufsiz; ++#endif ++ struct fiq_channel_state channel[0]; ++}; ++ ++extern void fiq_fsm_spin_lock(fiq_lock_t *lock); ++ ++extern void fiq_fsm_spin_unlock(fiq_lock_t *lock); ++ ++extern int fiq_fsm_too_late(struct fiq_state *st, int n); ++ ++extern int fiq_fsm_tt_in_use(struct fiq_state *st, int num_channels, int n); ++ ++extern void dwc_otg_fiq_fsm(struct fiq_state *state, int num_channels); ++ ++extern void dwc_otg_fiq_nop(struct fiq_state *state); ++ ++#endif /* DWC_OTG_FIQ_FSM_H_ */ +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S 2015-11-29 09:42:39.919098694 +0100 +@@ -0,0 +1,80 @@ ++/* ++ * dwc_otg_fiq_fsm.S - assembly stub for the FSM FIQ ++ * ++ * Copyright (c) 2013 Raspberry Pi Foundation ++ * ++ * Author: Jonathan Bell ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * * Neither the name of Raspberry Pi nor the ++ * names of its contributors may be used to endorse or promote products ++ * derived from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ++ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ++ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++ * DISCLAIMED. IN NO EVENT SHALL BE LIABLE FOR ANY ++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++ ++#include ++#include ++ ++ ++.text ++ ++.global _dwc_otg_fiq_stub_end; ++ ++/** ++ * _dwc_otg_fiq_stub() - entry copied to the FIQ vector page to allow ++ * a C-style function call with arguments from the FIQ banked registers. ++ * r0 = &hcd->fiq_state ++ * r1 = &hcd->num_channels ++ * r2 = &hcd->dma_buffers ++ * Tramples: r0, r1, r2, r4, fp, ip ++ */ ++ ++ENTRY(_dwc_otg_fiq_stub) ++ /* Stash unbanked regs - SP will have been set up for us */ ++ mov ip, sp; ++ stmdb sp!, {r0-r12, lr}; ++#ifdef FIQ_DEBUG ++ // Cycle profiling - read cycle counter at start ++ mrc p15, 0, r5, c15, c12, 1; ++#endif ++ /* r11 = fp, don't trample it */ ++ mov r4, fp; ++ /* set EABI frame size */ ++ sub fp, ip, #512; ++ ++ /* for fiq NOP mode - just need state */ ++ mov r0, r8; ++ /* r9 = num_channels */ ++ mov r1, r9; ++ /* r10 = struct *dma_bufs */ ++// mov r2, r10; ++ ++ /* r4 = &fiq_c_function */ ++ blx r4; ++#ifdef FIQ_DEBUG ++ mrc p15, 0, r4, c15, c12, 1; ++ subs r5, r5, r4; ++ // r5 is now the cycle count time for executing the FIQ. Store it somewhere? ++#endif ++ ldmia sp!, {r0-r12, lr}; ++ subs pc, lr, #4; ++_dwc_otg_fiq_stub_end: ++END(_dwc_otg_fiq_stub) +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd.c +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd.c 2015-11-29 09:42:39.919098694 +0100 +@@ -0,0 +1,4257 @@ ++ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $ ++ * $Revision: #104 $ ++ * $Date: 2011/10/24 $ ++ * $Change: 1871159 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_DEVICE_ONLY ++ ++/** @file ++ * This file implements HCD Core. All code in this file is portable and doesn't ++ * use any OS specific functions. ++ * Interface provided by HCD Core is defined in ++ * header file. ++ */ ++ ++#include ++#include ++ ++#include "dwc_otg_hcd.h" ++#include "dwc_otg_regs.h" ++#include "dwc_otg_fiq_fsm.h" ++ ++extern bool microframe_schedule; ++extern uint16_t fiq_fsm_mask, nak_holdoff; ++ ++//#define DEBUG_HOST_CHANNELS ++#ifdef DEBUG_HOST_CHANNELS ++static int last_sel_trans_num_per_scheduled = 0; ++static int last_sel_trans_num_nonper_scheduled = 0; ++static int last_sel_trans_num_avail_hc_at_start = 0; ++static int last_sel_trans_num_avail_hc_at_end = 0; ++#endif /* DEBUG_HOST_CHANNELS */ ++ ++ ++dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void) ++{ ++ return DWC_ALLOC(sizeof(dwc_otg_hcd_t)); ++} ++ ++/** ++ * Connection timeout function. An OTG host is required to display a ++ * message if the device does not connect within 10 seconds. ++ */ ++void dwc_otg_hcd_connect_timeout(void *ptr) ++{ ++ DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, ptr); ++ DWC_PRINTF("Connect Timeout\n"); ++ __DWC_ERROR("Device Not Connected/Responding\n"); ++} ++ ++#if defined(DEBUG) ++static void dump_channel_info(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ if (qh->channel != NULL) { ++ dwc_hc_t *hc = qh->channel; ++ dwc_list_link_t *item; ++ dwc_otg_qh_t *qh_item; ++ int num_channels = hcd->core_if->core_params->host_channels; ++ int i; ++ ++ dwc_otg_hc_regs_t *hc_regs; ++ hcchar_data_t hcchar; ++ hcsplt_data_t hcsplt; ++ hctsiz_data_t hctsiz; ++ uint32_t hcdma; ++ ++ hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num]; ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt); ++ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz); ++ hcdma = DWC_READ_REG32(&hc_regs->hcdma); ++ ++ DWC_PRINTF(" Assigned to channel %p:\n", hc); ++ DWC_PRINTF(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, ++ hcsplt.d32); ++ DWC_PRINTF(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, ++ hcdma); ++ DWC_PRINTF(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n", ++ hc->dev_addr, hc->ep_num, hc->ep_is_in); ++ DWC_PRINTF(" ep_type: %d\n", hc->ep_type); ++ DWC_PRINTF(" max_packet: %d\n", hc->max_packet); ++ DWC_PRINTF(" data_pid_start: %d\n", hc->data_pid_start); ++ DWC_PRINTF(" xfer_started: %d\n", hc->xfer_started); ++ DWC_PRINTF(" halt_status: %d\n", hc->halt_status); ++ DWC_PRINTF(" xfer_buff: %p\n", hc->xfer_buff); ++ DWC_PRINTF(" xfer_len: %d\n", hc->xfer_len); ++ DWC_PRINTF(" qh: %p\n", hc->qh); ++ DWC_PRINTF(" NP inactive sched:\n"); ++ DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_inactive) { ++ qh_item = ++ DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry); ++ DWC_PRINTF(" %p\n", qh_item); ++ } ++ DWC_PRINTF(" NP active sched:\n"); ++ DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_active) { ++ qh_item = ++ DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry); ++ DWC_PRINTF(" %p\n", qh_item); ++ } ++ DWC_PRINTF(" Channels: \n"); ++ for (i = 0; i < num_channels; i++) { ++ dwc_hc_t *hc = hcd->hc_ptr_array[i]; ++ DWC_PRINTF(" %2d: %p\n", i, hc); ++ } ++ } ++} ++#else ++#define dump_channel_info(hcd, qh) ++#endif /* DEBUG */ ++ ++/** ++ * Work queue function for starting the HCD when A-Cable is connected. ++ * The hcd_start() must be called in a process context. ++ */ ++static void hcd_start_func(void *_vp) ++{ ++ dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) _vp; ++ ++ DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, hcd); ++ if (hcd) { ++ hcd->fops->start(hcd); ++ } ++} ++ ++static void del_xfer_timers(dwc_otg_hcd_t * hcd) ++{ ++#ifdef DEBUG ++ int i; ++ int num_channels = hcd->core_if->core_params->host_channels; ++ for (i = 0; i < num_channels; i++) { ++ DWC_TIMER_CANCEL(hcd->core_if->hc_xfer_timer[i]); ++ } ++#endif ++} ++ ++static void del_timers(dwc_otg_hcd_t * hcd) ++{ ++ del_xfer_timers(hcd); ++ DWC_TIMER_CANCEL(hcd->conn_timer); ++} ++ ++/** ++ * Processes all the URBs in a single list of QHs. Completes them with ++ * -ESHUTDOWN and frees the QTD. ++ */ ++static void kill_urbs_in_qh_list(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list) ++{ ++ dwc_list_link_t *qh_item, *qh_tmp; ++ dwc_otg_qh_t *qh; ++ dwc_otg_qtd_t *qtd, *qtd_tmp; ++ ++ DWC_LIST_FOREACH_SAFE(qh_item, qh_tmp, qh_list) { ++ qh = DWC_LIST_ENTRY(qh_item, dwc_otg_qh_t, qh_list_entry); ++ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, ++ &qh->qtd_list, qtd_list_entry) { ++ qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); ++ if (qtd->urb != NULL) { ++ hcd->fops->complete(hcd, qtd->urb->priv, ++ qtd->urb, -DWC_E_SHUTDOWN); ++ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh); ++ } ++ ++ } ++ if(qh->channel) { ++ /* Using hcchar.chen == 1 is not a reliable test. ++ * It is possible that the channel has already halted ++ * but not yet been through the IRQ handler. ++ */ ++ dwc_otg_hc_halt(hcd->core_if, qh->channel, ++ DWC_OTG_HC_XFER_URB_DEQUEUE); ++ if(microframe_schedule) ++ hcd->available_host_channels++; ++ qh->channel = NULL; ++ } ++ dwc_otg_hcd_qh_remove(hcd, qh); ++ } ++} ++ ++/** ++ * Responds with an error status of ESHUTDOWN to all URBs in the non-periodic ++ * and periodic schedules. The QTD associated with each URB is removed from ++ * the schedule and freed. This function may be called when a disconnect is ++ * detected or when the HCD is being stopped. ++ */ ++static void kill_all_urbs(dwc_otg_hcd_t * hcd) ++{ ++ kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive); ++ kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active); ++ kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive); ++ kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready); ++ kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned); ++ kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued); ++} ++ ++/** ++ * Start the connection timer. An OTG host is required to display a ++ * message if the device does not connect within 10 seconds. The ++ * timer is deleted if a port connect interrupt occurs before the ++ * timer expires. ++ */ ++static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t * hcd) ++{ ++ DWC_TIMER_SCHEDULE(hcd->conn_timer, 10000 /* 10 secs */ ); ++} ++ ++/** ++ * HCD Callback function for disconnect of the HCD. ++ * ++ * @param p void pointer to the struct usb_hcd ++ */ ++static int32_t dwc_otg_hcd_session_start_cb(void *p) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd; ++ DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p); ++ dwc_otg_hcd = p; ++ dwc_otg_hcd_start_connect_timer(dwc_otg_hcd); ++ return 1; ++} ++ ++/** ++ * HCD Callback function for starting the HCD when A-Cable is ++ * connected. ++ * ++ * @param p void pointer to the struct usb_hcd ++ */ ++static int32_t dwc_otg_hcd_start_cb(void *p) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd = p; ++ dwc_otg_core_if_t *core_if; ++ hprt0_data_t hprt0; ++ ++ core_if = dwc_otg_hcd->core_if; ++ ++ if (core_if->op_state == B_HOST) { ++ /* ++ * Reset the port. During a HNP mode switch the reset ++ * needs to occur within 1ms and have a duration of at ++ * least 50ms. ++ */ ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtrst = 1; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ } ++ DWC_WORKQ_SCHEDULE_DELAYED(core_if->wq_otg, ++ hcd_start_func, dwc_otg_hcd, 50, ++ "start hcd"); ++ ++ return 1; ++} ++ ++/** ++ * HCD Callback function for disconnect of the HCD. ++ * ++ * @param p void pointer to the struct usb_hcd ++ */ ++static int32_t dwc_otg_hcd_disconnect_cb(void *p) ++{ ++ gintsts_data_t intr; ++ dwc_otg_hcd_t *dwc_otg_hcd = p; ++ ++ /* ++ * Set status flags for the hub driver. ++ */ ++ dwc_otg_hcd->flags.b.port_connect_status_change = 1; ++ dwc_otg_hcd->flags.b.port_connect_status = 0; ++ if(fiq_enable) ++ local_fiq_disable(); ++ /* ++ * Shutdown any transfers in process by clearing the Tx FIFO Empty ++ * interrupt mask and status bits and disabling subsequent host ++ * channel interrupts. ++ */ ++ intr.d32 = 0; ++ intr.b.nptxfempty = 1; ++ intr.b.ptxfempty = 1; ++ intr.b.hcintr = 1; ++ DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, ++ intr.d32, 0); ++ DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintsts, ++ intr.d32, 0); ++ ++ del_timers(dwc_otg_hcd); ++ ++ /* ++ * Turn off the vbus power only if the core has transitioned to device ++ * mode. If still in host mode, need to keep power on to detect a ++ * reconnection. ++ */ ++ if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) { ++ if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) { ++ hprt0_data_t hprt0 = {.d32 = 0 }; ++ DWC_PRINTF("Disconnect: PortPower off\n"); ++ hprt0.b.prtpwr = 0; ++ DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, ++ hprt0.d32); ++ } ++ ++ dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if); ++ } ++ ++ /* Respond with an error status to all URBs in the schedule. */ ++ kill_all_urbs(dwc_otg_hcd); ++ ++ if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) { ++ /* Clean up any host channels that were in use. */ ++ int num_channels; ++ int i; ++ dwc_hc_t *channel; ++ dwc_otg_hc_regs_t *hc_regs; ++ hcchar_data_t hcchar; ++ ++ num_channels = dwc_otg_hcd->core_if->core_params->host_channels; ++ ++ if (!dwc_otg_hcd->core_if->dma_enable) { ++ /* Flush out any channel requests in slave mode. */ ++ for (i = 0; i < num_channels; i++) { ++ channel = dwc_otg_hcd->hc_ptr_array[i]; ++ if (DWC_CIRCLEQ_EMPTY_ENTRY ++ (channel, hc_list_entry)) { ++ hc_regs = ++ dwc_otg_hcd->core_if-> ++ host_if->hc_regs[i]; ++ hcchar.d32 = ++ DWC_READ_REG32(&hc_regs->hcchar); ++ if (hcchar.b.chen) { ++ hcchar.b.chen = 0; ++ hcchar.b.chdis = 1; ++ hcchar.b.epdir = 0; ++ DWC_WRITE_REG32 ++ (&hc_regs->hcchar, ++ hcchar.d32); ++ } ++ } ++ } ++ } ++ ++ for (i = 0; i < num_channels; i++) { ++ channel = dwc_otg_hcd->hc_ptr_array[i]; ++ if (DWC_CIRCLEQ_EMPTY_ENTRY(channel, hc_list_entry)) { ++ hc_regs = ++ dwc_otg_hcd->core_if->host_if->hc_regs[i]; ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ if (hcchar.b.chen) { ++ /* Halt the channel. */ ++ hcchar.b.chdis = 1; ++ DWC_WRITE_REG32(&hc_regs->hcchar, ++ hcchar.d32); ++ } ++ ++ dwc_otg_hc_cleanup(dwc_otg_hcd->core_if, ++ channel); ++ DWC_CIRCLEQ_INSERT_TAIL ++ (&dwc_otg_hcd->free_hc_list, channel, ++ hc_list_entry); ++ /* ++ * Added for Descriptor DMA to prevent channel double cleanup ++ * in release_channel_ddma(). Which called from ep_disable ++ * when device disconnect. ++ */ ++ channel->qh = NULL; ++ } ++ } ++ if(fiq_fsm_enable) { ++ for(i=0; i < 128; i++) { ++ dwc_otg_hcd->hub_port[i] = 0; ++ } ++ } ++ ++ } ++ ++ if(fiq_enable) ++ local_fiq_enable(); ++ ++ if (dwc_otg_hcd->fops->disconnect) { ++ dwc_otg_hcd->fops->disconnect(dwc_otg_hcd); ++ } ++ ++ return 1; ++} ++ ++/** ++ * HCD Callback function for stopping the HCD. ++ * ++ * @param p void pointer to the struct usb_hcd ++ */ ++static int32_t dwc_otg_hcd_stop_cb(void *p) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd = p; ++ ++ DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p); ++ dwc_otg_hcd_stop(dwc_otg_hcd); ++ return 1; ++} ++ ++#ifdef CONFIG_USB_DWC_OTG_LPM ++/** ++ * HCD Callback function for sleep of HCD. ++ * ++ * @param p void pointer to the struct usb_hcd ++ */ ++static int dwc_otg_hcd_sleep_cb(void *p) ++{ ++ dwc_otg_hcd_t *hcd = p; ++ ++ dwc_otg_hcd_free_hc_from_lpm(hcd); ++ ++ return 0; ++} ++#endif ++ ++ ++/** ++ * HCD Callback function for Remote Wakeup. ++ * ++ * @param p void pointer to the struct usb_hcd ++ */ ++static int dwc_otg_hcd_rem_wakeup_cb(void *p) ++{ ++ dwc_otg_hcd_t *hcd = p; ++ ++ if (hcd->core_if->lx_state == DWC_OTG_L2) { ++ hcd->flags.b.port_suspend_change = 1; ++ } ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ else { ++ hcd->flags.b.port_l1_change = 1; ++ } ++#endif ++ return 0; ++} ++ ++/** ++ * Halts the DWC_otg host mode operations in a clean manner. USB transfers are ++ * stopped. ++ */ ++void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd) ++{ ++ hprt0_data_t hprt0 = {.d32 = 0 }; ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n"); ++ ++ /* ++ * The root hub should be disconnected before this function is called. ++ * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) ++ * and the QH lists (via ..._hcd_endpoint_disable). ++ */ ++ ++ /* Turn off all host-specific interrupts. */ ++ dwc_otg_disable_host_interrupts(hcd->core_if); ++ ++ /* Turn off the vbus power */ ++ DWC_PRINTF("PortPower off\n"); ++ hprt0.b.prtpwr = 0; ++ DWC_WRITE_REG32(hcd->core_if->host_if->hprt0, hprt0.d32); ++ dwc_mdelay(1); ++} ++ ++int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * hcd, ++ dwc_otg_hcd_urb_t * dwc_otg_urb, void **ep_handle, ++ int atomic_alloc) ++{ ++ int retval = 0; ++ uint8_t needs_scheduling = 0; ++ dwc_otg_transaction_type_e tr_type; ++ dwc_otg_qtd_t *qtd; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ hprt0_data_t hprt0 = { .d32 = 0 }; ++ ++#ifdef DEBUG /* integrity checks (Broadcom) */ ++ if (NULL == hcd->core_if) { ++ DWC_ERROR("**** DWC OTG HCD URB Enqueue - HCD has NULL core_if\n"); ++ /* No longer connected. */ ++ return -DWC_E_INVALID; ++ } ++#endif ++ if (!hcd->flags.b.port_connect_status) { ++ /* No longer connected. */ ++ DWC_ERROR("Not connected\n"); ++ return -DWC_E_NO_DEVICE; ++ } ++ ++ /* Some core configurations cannot support LS traffic on a FS root port */ ++ if ((hcd->fops->speed(hcd, dwc_otg_urb->priv) == USB_SPEED_LOW) && ++ (hcd->core_if->hwcfg2.b.fs_phy_type == 1) && ++ (hcd->core_if->hwcfg2.b.hs_phy_type == 1)) { ++ hprt0.d32 = DWC_READ_REG32(hcd->core_if->host_if->hprt0); ++ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_FULL_SPEED) { ++ return -DWC_E_NO_DEVICE; ++ } ++ } ++ ++ qtd = dwc_otg_hcd_qtd_create(dwc_otg_urb, atomic_alloc); ++ if (qtd == NULL) { ++ DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n"); ++ return -DWC_E_NO_MEMORY; ++ } ++#ifdef DEBUG /* integrity checks (Broadcom) */ ++ if (qtd->urb == NULL) { ++ DWC_ERROR("**** DWC OTG HCD URB Enqueue created QTD with no URBs\n"); ++ return -DWC_E_NO_MEMORY; ++ } ++ if (qtd->urb->priv == NULL) { ++ DWC_ERROR("**** DWC OTG HCD URB Enqueue created QTD URB with no URB handle\n"); ++ return -DWC_E_NO_MEMORY; ++ } ++#endif ++ intr_mask.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->gintmsk); ++ if(!intr_mask.b.sofintr || fiq_enable) needs_scheduling = 1; ++ if((((dwc_otg_qh_t *)ep_handle)->ep_type == UE_BULK) && !(qtd->urb->flags & URB_GIVEBACK_ASAP)) ++ /* Do not schedule SG transactions until qtd has URB_GIVEBACK_ASAP set */ ++ needs_scheduling = 0; ++ ++ retval = dwc_otg_hcd_qtd_add(qtd, hcd, (dwc_otg_qh_t **) ep_handle, atomic_alloc); ++ // creates a new queue in ep_handle if it doesn't exist already ++ if (retval < 0) { ++ DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. " ++ "Error status %d\n", retval); ++ dwc_otg_hcd_qtd_free(qtd); ++ return retval; ++ } ++ ++ if(needs_scheduling) { ++ tr_type = dwc_otg_hcd_select_transactions(hcd); ++ if (tr_type != DWC_OTG_TRANSACTION_NONE) { ++ dwc_otg_hcd_queue_transactions(hcd, tr_type); ++ } ++ } ++ return retval; ++} ++ ++int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * hcd, ++ dwc_otg_hcd_urb_t * dwc_otg_urb) ++{ ++ dwc_otg_qh_t *qh; ++ dwc_otg_qtd_t *urb_qtd; ++ BUG_ON(!hcd); ++ BUG_ON(!dwc_otg_urb); ++ ++#ifdef DEBUG /* integrity checks (Broadcom) */ ++ ++ if (hcd == NULL) { ++ DWC_ERROR("**** DWC OTG HCD URB Dequeue has NULL HCD\n"); ++ return -DWC_E_INVALID; ++ } ++ if (dwc_otg_urb == NULL) { ++ DWC_ERROR("**** DWC OTG HCD URB Dequeue has NULL URB\n"); ++ return -DWC_E_INVALID; ++ } ++ if (dwc_otg_urb->qtd == NULL) { ++ DWC_ERROR("**** DWC OTG HCD URB Dequeue with NULL QTD\n"); ++ return -DWC_E_INVALID; ++ } ++ urb_qtd = dwc_otg_urb->qtd; ++ BUG_ON(!urb_qtd); ++ if (urb_qtd->qh == NULL) { ++ DWC_ERROR("**** DWC OTG HCD URB Dequeue with QTD with NULL Q handler\n"); ++ return -DWC_E_INVALID; ++ } ++#else ++ urb_qtd = dwc_otg_urb->qtd; ++ BUG_ON(!urb_qtd); ++#endif ++ qh = urb_qtd->qh; ++ BUG_ON(!qh); ++ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { ++ if (urb_qtd->in_process) { ++ dump_channel_info(hcd, qh); ++ } ++ } ++#ifdef DEBUG /* integrity checks (Broadcom) */ ++ if (hcd->core_if == NULL) { ++ DWC_ERROR("**** DWC OTG HCD URB Dequeue HCD has NULL core_if\n"); ++ return -DWC_E_INVALID; ++ } ++#endif ++ if (urb_qtd->in_process && qh->channel) { ++ /* The QTD is in process (it has been assigned to a channel). */ ++ if (hcd->flags.b.port_connect_status) { ++ int n = qh->channel->hc_num; ++ /* ++ * If still connected (i.e. in host mode), halt the ++ * channel so it can be used for other transfers. If ++ * no longer connected, the host registers can't be ++ * written to halt the channel since the core is in ++ * device mode. ++ */ ++ /* In FIQ FSM mode, we need to shut down carefully. ++ * The FIQ may attempt to restart a disabled channel */ ++ if (fiq_fsm_enable && (hcd->fiq_state->channel[n].fsm != FIQ_PASSTHROUGH)) { ++ qh->channel->halt_status = DWC_OTG_HC_XFER_URB_DEQUEUE; ++ qh->channel->halt_pending = 1; ++ hcd->fiq_state->channel[n].fsm = FIQ_DEQUEUE_ISSUED; ++ } else { ++ dwc_otg_hc_halt(hcd->core_if, qh->channel, ++ DWC_OTG_HC_XFER_URB_DEQUEUE); ++ } ++ } ++ } ++ ++ /* ++ * Free the QTD and clean up the associated QH. Leave the QH in the ++ * schedule if it has any remaining QTDs. ++ */ ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue - " ++ "delete %sQueue handler\n", ++ hcd->core_if->dma_desc_enable?"DMA ":""); ++ if (!hcd->core_if->dma_desc_enable) { ++ uint8_t b = urb_qtd->in_process; ++ dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh); ++ if (b) { ++ dwc_otg_hcd_qh_deactivate(hcd, qh, 0); ++ qh->channel = NULL; ++ } else if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) { ++ dwc_otg_hcd_qh_remove(hcd, qh); ++ } ++ } else { ++ dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh); ++ } ++ return 0; ++} ++ ++int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle, ++ int retry) ++{ ++ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle; ++ int retval = 0; ++ dwc_irqflags_t flags; ++ ++ if (retry < 0) { ++ retval = -DWC_E_INVALID; ++ goto done; ++ } ++ ++ if (!qh) { ++ retval = -DWC_E_INVALID; ++ goto done; ++ } ++ ++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); ++ ++ while (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list) && retry) { ++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); ++ retry--; ++ dwc_msleep(5); ++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); ++ } ++ ++ dwc_otg_hcd_qh_remove(hcd, qh); ++ ++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); ++ /* ++ * Split dwc_otg_hcd_qh_remove_and_free() into qh_remove ++ * and qh_free to prevent stack dump on DWC_DMA_FREE() with ++ * irq_disabled (spinlock_irqsave) in dwc_otg_hcd_desc_list_free() ++ * and dwc_otg_hcd_frame_list_alloc(). ++ */ ++ dwc_otg_hcd_qh_free(hcd, qh); ++ ++done: ++ return retval; ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30) ++int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle) ++{ ++ int retval = 0; ++ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle; ++ if (!qh) ++ return -DWC_E_INVALID; ++ ++ qh->data_toggle = DWC_OTG_HC_PID_DATA0; ++ return retval; ++} ++#endif ++ ++/** ++ * HCD Callback structure for handling mode switching. ++ */ ++static dwc_otg_cil_callbacks_t hcd_cil_callbacks = { ++ .start = dwc_otg_hcd_start_cb, ++ .stop = dwc_otg_hcd_stop_cb, ++ .disconnect = dwc_otg_hcd_disconnect_cb, ++ .session_start = dwc_otg_hcd_session_start_cb, ++ .resume_wakeup = dwc_otg_hcd_rem_wakeup_cb, ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ .sleep = dwc_otg_hcd_sleep_cb, ++#endif ++ .p = 0, ++}; ++ ++/** ++ * Reset tasklet function ++ */ ++static void reset_tasklet_func(void *data) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *) data; ++ dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; ++ hprt0_data_t hprt0; ++ ++ DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n"); ++ ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtrst = 1; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ dwc_mdelay(60); ++ ++ hprt0.b.prtrst = 0; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ dwc_otg_hcd->flags.b.port_reset_change = 1; ++} ++ ++static void completion_tasklet_func(void *ptr) ++{ ++ dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) ptr; ++ struct urb *urb; ++ urb_tq_entry_t *item; ++ dwc_irqflags_t flags; ++ ++ /* This could just be spin_lock_irq */ ++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); ++ while (!DWC_TAILQ_EMPTY(&hcd->completed_urb_list)) { ++ item = DWC_TAILQ_FIRST(&hcd->completed_urb_list); ++ urb = item->urb; ++ DWC_TAILQ_REMOVE(&hcd->completed_urb_list, item, ++ urb_tq_entries); ++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); ++ DWC_FREE(item); ++ ++ usb_hcd_giveback_urb(hcd->priv, urb, urb->status); ++ ++ ++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); ++ } ++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); ++ return; ++} ++ ++static void qh_list_free(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list) ++{ ++ dwc_list_link_t *item; ++ dwc_otg_qh_t *qh; ++ dwc_irqflags_t flags; ++ ++ if (!qh_list->next) { ++ /* The list hasn't been initialized yet. */ ++ return; ++ } ++ /* ++ * Hold spinlock here. Not needed in that case if bellow ++ * function is being called from ISR ++ */ ++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); ++ /* Ensure there are no QTDs or URBs left. */ ++ kill_urbs_in_qh_list(hcd, qh_list); ++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); ++ ++ DWC_LIST_FOREACH(item, qh_list) { ++ qh = DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry); ++ dwc_otg_hcd_qh_remove_and_free(hcd, qh); ++ } ++} ++ ++/** ++ * Exit from Hibernation if Host did not detect SRP from connected SRP capable ++ * Device during SRP time by host power up. ++ */ ++void dwc_otg_hcd_power_up(void *ptr) ++{ ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr; ++ ++ DWC_PRINTF("%s called\n", __FUNCTION__); ++ ++ if (!core_if->hibernation_suspend) { ++ DWC_PRINTF("Already exited from Hibernation\n"); ++ return; ++ } ++ ++ /* Switch on the voltage to the core */ ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Reset the core */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Disable power clamps */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnclmp = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /* Remove reset the core signal */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Disable PMU interrupt */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ core_if->hibernation_suspend = 0; ++ ++ /* Disable PMU */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Enable VBUS */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.dis_vbus = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ core_if->op_state = A_HOST; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_hcd_start(core_if); ++} ++ ++void dwc_otg_cleanup_fiq_channel(dwc_otg_hcd_t *hcd, uint32_t num) ++{ ++ struct fiq_channel_state *st = &hcd->fiq_state->channel[num]; ++ struct fiq_dma_blob *blob = hcd->fiq_dmab; ++ int i; ++ ++ st->fsm = FIQ_PASSTHROUGH; ++ st->hcchar_copy.d32 = 0; ++ st->hcsplt_copy.d32 = 0; ++ st->hcint_copy.d32 = 0; ++ st->hcintmsk_copy.d32 = 0; ++ st->hctsiz_copy.d32 = 0; ++ st->hcdma_copy.d32 = 0; ++ st->nr_errors = 0; ++ st->hub_addr = 0; ++ st->port_addr = 0; ++ st->expected_uframe = 0; ++ st->nrpackets = 0; ++ st->dma_info.index = 0; ++ for (i = 0; i < 6; i++) ++ st->dma_info.slot_len[i] = 255; ++ st->hs_isoc_info.index = 0; ++ st->hs_isoc_info.iso_desc = NULL; ++ st->hs_isoc_info.nrframes = 0; ++ ++ DWC_MEMSET(&blob->channel[num].index[0], 0x6b, 1128); ++} ++ ++/** ++ * Frees secondary storage associated with the dwc_otg_hcd structure contained ++ * in the struct usb_hcd field. ++ */ ++static void dwc_otg_hcd_free(dwc_otg_hcd_t * dwc_otg_hcd) ++{ ++ int i; ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n"); ++ ++ del_timers(dwc_otg_hcd); ++ ++ /* Free memory for QH/QTD lists */ ++ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive); ++ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active); ++ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive); ++ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready); ++ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned); ++ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued); ++ ++ /* Free memory for the host channels. */ ++ for (i = 0; i < MAX_EPS_CHANNELS; i++) { ++ dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i]; ++ ++#ifdef DEBUG ++ if (dwc_otg_hcd->core_if->hc_xfer_timer[i]) { ++ DWC_TIMER_FREE(dwc_otg_hcd->core_if->hc_xfer_timer[i]); ++ } ++#endif ++ if (hc != NULL) { ++ DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n", ++ i, hc); ++ DWC_FREE(hc); ++ } ++ } ++ ++ if (dwc_otg_hcd->core_if->dma_enable) { ++ if (dwc_otg_hcd->status_buf_dma) { ++ DWC_DMA_FREE(DWC_OTG_HCD_STATUS_BUF_SIZE, ++ dwc_otg_hcd->status_buf, ++ dwc_otg_hcd->status_buf_dma); ++ } ++ } else if (dwc_otg_hcd->status_buf != NULL) { ++ DWC_FREE(dwc_otg_hcd->status_buf); ++ } ++ DWC_SPINLOCK_FREE(dwc_otg_hcd->channel_lock); ++ DWC_SPINLOCK_FREE(dwc_otg_hcd->lock); ++ /* Set core_if's lock pointer to NULL */ ++ dwc_otg_hcd->core_if->lock = NULL; ++ ++ DWC_TIMER_FREE(dwc_otg_hcd->conn_timer); ++ DWC_TASK_FREE(dwc_otg_hcd->reset_tasklet); ++ DWC_TASK_FREE(dwc_otg_hcd->completion_tasklet); ++ DWC_FREE(dwc_otg_hcd->fiq_state); ++ ++#ifdef DWC_DEV_SRPCAP ++ if (dwc_otg_hcd->core_if->power_down == 2 && ++ dwc_otg_hcd->core_if->pwron_timer) { ++ DWC_TIMER_FREE(dwc_otg_hcd->core_if->pwron_timer); ++ } ++#endif ++ DWC_FREE(dwc_otg_hcd); ++} ++ ++int init_hcd_usecs(dwc_otg_hcd_t *_hcd); ++ ++int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if) ++{ ++ int retval = 0; ++ int num_channels; ++ int i; ++ dwc_hc_t *channel; ++ ++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK)) ++ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(hcd->lock); ++ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(hcd->channel_lock); ++#else ++ hcd->lock = DWC_SPINLOCK_ALLOC(); ++ hcd->channel_lock = DWC_SPINLOCK_ALLOC(); ++#endif ++ DWC_DEBUGPL(DBG_HCDV, "init of HCD %p given core_if %p\n", ++ hcd, core_if); ++ if (!hcd->lock) { ++ DWC_ERROR("Could not allocate lock for pcd"); ++ DWC_FREE(hcd); ++ retval = -DWC_E_NO_MEMORY; ++ goto out; ++ } ++ hcd->core_if = core_if; ++ ++ /* Register the HCD CIL Callbacks */ ++ dwc_otg_cil_register_hcd_callbacks(hcd->core_if, ++ &hcd_cil_callbacks, hcd); ++ ++ /* Initialize the non-periodic schedule. */ ++ DWC_LIST_INIT(&hcd->non_periodic_sched_inactive); ++ DWC_LIST_INIT(&hcd->non_periodic_sched_active); ++ ++ /* Initialize the periodic schedule. */ ++ DWC_LIST_INIT(&hcd->periodic_sched_inactive); ++ DWC_LIST_INIT(&hcd->periodic_sched_ready); ++ DWC_LIST_INIT(&hcd->periodic_sched_assigned); ++ DWC_LIST_INIT(&hcd->periodic_sched_queued); ++ DWC_TAILQ_INIT(&hcd->completed_urb_list); ++ /* ++ * Create a host channel descriptor for each host channel implemented ++ * in the controller. Initialize the channel descriptor array. ++ */ ++ DWC_CIRCLEQ_INIT(&hcd->free_hc_list); ++ num_channels = hcd->core_if->core_params->host_channels; ++ DWC_MEMSET(hcd->hc_ptr_array, 0, sizeof(hcd->hc_ptr_array)); ++ for (i = 0; i < num_channels; i++) { ++ channel = DWC_ALLOC(sizeof(dwc_hc_t)); ++ if (channel == NULL) { ++ retval = -DWC_E_NO_MEMORY; ++ DWC_ERROR("%s: host channel allocation failed\n", ++ __func__); ++ dwc_otg_hcd_free(hcd); ++ goto out; ++ } ++ channel->hc_num = i; ++ hcd->hc_ptr_array[i] = channel; ++#ifdef DEBUG ++ hcd->core_if->hc_xfer_timer[i] = ++ DWC_TIMER_ALLOC("hc timer", hc_xfer_timeout, ++ &hcd->core_if->hc_xfer_info[i]); ++#endif ++ DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, ++ channel); ++ } ++ ++ if (fiq_enable) { ++ hcd->fiq_state = DWC_ALLOC(sizeof(struct fiq_state) + (sizeof(struct fiq_channel_state) * num_channels)); ++ if (!hcd->fiq_state) { ++ retval = -DWC_E_NO_MEMORY; ++ DWC_ERROR("%s: cannot allocate fiq_state structure\n", __func__); ++ dwc_otg_hcd_free(hcd); ++ goto out; ++ } ++ DWC_MEMSET(hcd->fiq_state, 0, (sizeof(struct fiq_state) + (sizeof(struct fiq_channel_state) * num_channels))); ++ ++ for (i = 0; i < num_channels; i++) { ++ hcd->fiq_state->channel[i].fsm = FIQ_PASSTHROUGH; ++ } ++ hcd->fiq_state->dummy_send = DWC_ALLOC_ATOMIC(16); ++ ++ hcd->fiq_stack = DWC_ALLOC(sizeof(struct fiq_stack)); ++ if (!hcd->fiq_stack) { ++ retval = -DWC_E_NO_MEMORY; ++ DWC_ERROR("%s: cannot allocate fiq_stack structure\n", __func__); ++ dwc_otg_hcd_free(hcd); ++ goto out; ++ } ++ hcd->fiq_stack->magic1 = 0xDEADBEEF; ++ hcd->fiq_stack->magic2 = 0xD00DFEED; ++ hcd->fiq_state->gintmsk_saved.d32 = ~0; ++ hcd->fiq_state->haintmsk_saved.b2.chint = ~0; ++ ++ /* This bit is terrible and uses no API, but necessary. The FIQ has no concept of DMA pools ++ * (and if it did, would be a lot slower). This allocates a chunk of memory (~9kiB for 8 host channels) ++ * for use as transaction bounce buffers in a 2-D array. Our access into this chunk is done by some ++ * moderately readable array casts. ++ */ ++ hcd->fiq_dmab = DWC_DMA_ALLOC((sizeof(struct fiq_dma_channel) * num_channels), &hcd->fiq_state->dma_base); ++ DWC_WARN("FIQ DMA bounce buffers: virt = 0x%08x dma = 0x%08x len=%d", ++ (unsigned int)hcd->fiq_dmab, (unsigned int)hcd->fiq_state->dma_base, ++ sizeof(struct fiq_dma_channel) * num_channels); ++ ++ DWC_MEMSET(hcd->fiq_dmab, 0x6b, 9024); ++ ++ /* pointer for debug in fiq_print */ ++ hcd->fiq_state->fiq_dmab = hcd->fiq_dmab; ++ if (fiq_fsm_enable) { ++ int i; ++ for (i=0; i < hcd->core_if->core_params->host_channels; i++) { ++ dwc_otg_cleanup_fiq_channel(hcd, i); ++ } ++ DWC_PRINTF("FIQ FSM acceleration enabled for :\n%s%s%s%s", ++ (fiq_fsm_mask & 0x1) ? "Non-periodic Split Transactions\n" : "", ++ (fiq_fsm_mask & 0x2) ? "Periodic Split Transactions\n" : "", ++ (fiq_fsm_mask & 0x4) ? "High-Speed Isochronous Endpoints\n" : "", ++ (fiq_fsm_mask & 0x8) ? "Interrupt/Control Split Transaction hack enabled\n" : ""); ++ } ++ } ++ ++ /* Initialize the Connection timeout timer. */ ++ hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer", ++ dwc_otg_hcd_connect_timeout, 0); ++ ++ printk(KERN_DEBUG "dwc_otg: Microframe scheduler %s\n", microframe_schedule ? "enabled":"disabled"); ++ if (microframe_schedule) ++ init_hcd_usecs(hcd); ++ ++ /* Initialize reset tasklet. */ ++ hcd->reset_tasklet = DWC_TASK_ALLOC("reset_tasklet", reset_tasklet_func, hcd); ++ ++ hcd->completion_tasklet = DWC_TASK_ALLOC("completion_tasklet", ++ completion_tasklet_func, hcd); ++#ifdef DWC_DEV_SRPCAP ++ if (hcd->core_if->power_down == 2) { ++ /* Initialize Power on timer for Host power up in case hibernation */ ++ hcd->core_if->pwron_timer = DWC_TIMER_ALLOC("PWRON TIMER", ++ dwc_otg_hcd_power_up, core_if); ++ } ++#endif ++ ++ /* ++ * Allocate space for storing data on status transactions. Normally no ++ * data is sent, but this space acts as a bit bucket. This must be ++ * done after usb_add_hcd since that function allocates the DMA buffer ++ * pool. ++ */ ++ if (hcd->core_if->dma_enable) { ++ hcd->status_buf = ++ DWC_DMA_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE, ++ &hcd->status_buf_dma); ++ } else { ++ hcd->status_buf = DWC_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE); ++ } ++ if (!hcd->status_buf) { ++ retval = -DWC_E_NO_MEMORY; ++ DWC_ERROR("%s: status_buf allocation failed\n", __func__); ++ dwc_otg_hcd_free(hcd); ++ goto out; ++ } ++ ++ hcd->otg_port = 1; ++ hcd->frame_list = NULL; ++ hcd->frame_list_dma = 0; ++ hcd->periodic_qh_count = 0; ++ ++ DWC_MEMSET(hcd->hub_port, 0, sizeof(hcd->hub_port)); ++#ifdef FIQ_DEBUG ++ DWC_MEMSET(hcd->hub_port_alloc, -1, sizeof(hcd->hub_port_alloc)); ++#endif ++ ++out: ++ return retval; ++} ++ ++void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd) ++{ ++ /* Turn off all host-specific interrupts. */ ++ dwc_otg_disable_host_interrupts(hcd->core_if); ++ ++ dwc_otg_hcd_free(hcd); ++} ++ ++/** ++ * Initializes dynamic portions of the DWC_otg HCD state. ++ */ ++static void dwc_otg_hcd_reinit(dwc_otg_hcd_t * hcd) ++{ ++ int num_channels; ++ int i; ++ dwc_hc_t *channel; ++ dwc_hc_t *channel_tmp; ++ ++ hcd->flags.d32 = 0; ++ ++ hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active; ++ if (!microframe_schedule) { ++ hcd->non_periodic_channels = 0; ++ hcd->periodic_channels = 0; ++ } else { ++ hcd->available_host_channels = hcd->core_if->core_params->host_channels; ++ } ++ /* ++ * Put all channels in the free channel list and clean up channel ++ * states. ++ */ ++ DWC_CIRCLEQ_FOREACH_SAFE(channel, channel_tmp, ++ &hcd->free_hc_list, hc_list_entry) { ++ DWC_CIRCLEQ_REMOVE(&hcd->free_hc_list, channel, hc_list_entry); ++ } ++ ++ num_channels = hcd->core_if->core_params->host_channels; ++ for (i = 0; i < num_channels; i++) { ++ channel = hcd->hc_ptr_array[i]; ++ DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, channel, ++ hc_list_entry); ++ dwc_otg_hc_cleanup(hcd->core_if, channel); ++ } ++ ++ /* Initialize the DWC core for host mode operation. */ ++ dwc_otg_core_host_init(hcd->core_if); ++ ++ /* Set core_if's lock pointer to the hcd->lock */ ++ hcd->core_if->lock = hcd->lock; ++} ++ ++/** ++ * Assigns transactions from a QTD to a free host channel and initializes the ++ * host channel to perform the transactions. The host channel is removed from ++ * the free list. ++ * ++ * @param hcd The HCD state structure. ++ * @param qh Transactions from the first QTD for this QH are selected and ++ * assigned to a free host channel. ++ */ ++static void assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ dwc_hc_t *hc; ++ dwc_otg_qtd_t *qtd; ++ dwc_otg_hcd_urb_t *urb; ++ void* ptr = NULL; ++ uint32_t intr_enable; ++ unsigned long flags; ++ gintmsk_data_t gintmsk = { .d32 = 0, }; ++ ++ qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); ++ ++ urb = qtd->urb; ++ ++ DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p) - urb %x, actual_length %d\n", __func__, hcd, qh, (unsigned int)urb, urb->actual_length); ++ ++ if (((urb->actual_length < 0) || (urb->actual_length > urb->length)) && !dwc_otg_hcd_is_pipe_in(&urb->pipe_info)) ++ urb->actual_length = urb->length; ++ ++ ++ hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list); ++ ++ /* Remove the host channel from the free list. */ ++ DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry); ++ ++ qh->channel = hc; ++ ++ qtd->in_process = 1; ++ ++ /* ++ * Use usb_pipedevice to determine device address. This address is ++ * 0 before the SET_ADDRESS command and the correct address afterward. ++ */ ++ hc->dev_addr = dwc_otg_hcd_get_dev_addr(&urb->pipe_info); ++ hc->ep_num = dwc_otg_hcd_get_ep_num(&urb->pipe_info); ++ hc->speed = qh->dev_speed; ++ hc->max_packet = dwc_max_packet(qh->maxp); ++ ++ hc->xfer_started = 0; ++ hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS; ++ hc->error_state = (qtd->error_count > 0); ++ hc->halt_on_queue = 0; ++ hc->halt_pending = 0; ++ hc->requests = 0; ++ ++ /* ++ * The following values may be modified in the transfer type section ++ * below. The xfer_len value may be reduced when the transfer is ++ * started to accommodate the max widths of the XferSize and PktCnt ++ * fields in the HCTSIZn register. ++ */ ++ ++ hc->ep_is_in = (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) != 0); ++ if (hc->ep_is_in) { ++ hc->do_ping = 0; ++ } else { ++ hc->do_ping = qh->ping_state; ++ } ++ ++ hc->data_pid_start = qh->data_toggle; ++ hc->multi_count = 1; ++ ++ if (hcd->core_if->dma_enable) { ++ hc->xfer_buff = (uint8_t *) urb->dma + urb->actual_length; ++ ++ /* For non-dword aligned case */ ++ if (((unsigned long)hc->xfer_buff & 0x3) ++ && !hcd->core_if->dma_desc_enable) { ++ ptr = (uint8_t *) urb->buf + urb->actual_length; ++ } ++ } else { ++ hc->xfer_buff = (uint8_t *) urb->buf + urb->actual_length; ++ } ++ hc->xfer_len = urb->length - urb->actual_length; ++ hc->xfer_count = 0; ++ ++ /* ++ * Set the split attributes ++ */ ++ hc->do_split = 0; ++ if (qh->do_split) { ++ uint32_t hub_addr, port_addr; ++ hc->do_split = 1; ++ hc->xact_pos = qtd->isoc_split_pos; ++ /* We don't need to do complete splits anymore */ ++// if(fiq_fsm_enable) ++ if (0) ++ hc->complete_split = qtd->complete_split = 0; ++ else ++ hc->complete_split = qtd->complete_split; ++ ++ hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &port_addr); ++ hc->hub_addr = (uint8_t) hub_addr; ++ hc->port_addr = (uint8_t) port_addr; ++ } ++ ++ switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) { ++ case UE_CONTROL: ++ hc->ep_type = DWC_OTG_EP_TYPE_CONTROL; ++ switch (qtd->control_phase) { ++ case DWC_OTG_CONTROL_SETUP: ++ DWC_DEBUGPL(DBG_HCDV, " Control setup transaction\n"); ++ hc->do_ping = 0; ++ hc->ep_is_in = 0; ++ hc->data_pid_start = DWC_OTG_HC_PID_SETUP; ++ if (hcd->core_if->dma_enable) { ++ hc->xfer_buff = (uint8_t *) urb->setup_dma; ++ } else { ++ hc->xfer_buff = (uint8_t *) urb->setup_packet; ++ } ++ hc->xfer_len = 8; ++ ptr = NULL; ++ break; ++ case DWC_OTG_CONTROL_DATA: ++ DWC_DEBUGPL(DBG_HCDV, " Control data transaction\n"); ++ hc->data_pid_start = qtd->data_toggle; ++ break; ++ case DWC_OTG_CONTROL_STATUS: ++ /* ++ * Direction is opposite of data direction or IN if no ++ * data. ++ */ ++ DWC_DEBUGPL(DBG_HCDV, " Control status transaction\n"); ++ if (urb->length == 0) { ++ hc->ep_is_in = 1; ++ } else { ++ hc->ep_is_in = ++ dwc_otg_hcd_is_pipe_out(&urb->pipe_info); ++ } ++ if (hc->ep_is_in) { ++ hc->do_ping = 0; ++ } ++ ++ hc->data_pid_start = DWC_OTG_HC_PID_DATA1; ++ ++ hc->xfer_len = 0; ++ if (hcd->core_if->dma_enable) { ++ hc->xfer_buff = (uint8_t *) hcd->status_buf_dma; ++ } else { ++ hc->xfer_buff = (uint8_t *) hcd->status_buf; ++ } ++ ptr = NULL; ++ break; ++ } ++ break; ++ case UE_BULK: ++ hc->ep_type = DWC_OTG_EP_TYPE_BULK; ++ break; ++ case UE_INTERRUPT: ++ hc->ep_type = DWC_OTG_EP_TYPE_INTR; ++ break; ++ case UE_ISOCHRONOUS: ++ { ++ struct dwc_otg_hcd_iso_packet_desc *frame_desc; ++ ++ hc->ep_type = DWC_OTG_EP_TYPE_ISOC; ++ ++ if (hcd->core_if->dma_desc_enable) ++ break; ++ ++ frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; ++ ++ frame_desc->status = 0; ++ ++ if (hcd->core_if->dma_enable) { ++ hc->xfer_buff = (uint8_t *) urb->dma; ++ } else { ++ hc->xfer_buff = (uint8_t *) urb->buf; ++ } ++ hc->xfer_buff += ++ frame_desc->offset + qtd->isoc_split_offset; ++ hc->xfer_len = ++ frame_desc->length - qtd->isoc_split_offset; ++ ++ /* For non-dword aligned buffers */ ++ if (((unsigned long)hc->xfer_buff & 0x3) ++ && hcd->core_if->dma_enable) { ++ ptr = ++ (uint8_t *) urb->buf + frame_desc->offset + ++ qtd->isoc_split_offset; ++ } else ++ ptr = NULL; ++ ++ if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) { ++ if (hc->xfer_len <= 188) { ++ hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL; ++ } else { ++ hc->xact_pos = ++ DWC_HCSPLIT_XACTPOS_BEGIN; ++ } ++ } ++ } ++ break; ++ } ++ /* non DWORD-aligned buffer case */ ++ if (ptr) { ++ uint32_t buf_size; ++ if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) { ++ buf_size = hcd->core_if->core_params->max_transfer_size; ++ } else { ++ buf_size = 4096; ++ } ++ if (!qh->dw_align_buf) { ++ qh->dw_align_buf = DWC_DMA_ALLOC_ATOMIC(buf_size, ++ &qh->dw_align_buf_dma); ++ if (!qh->dw_align_buf) { ++ DWC_ERROR ++ ("%s: Failed to allocate memory to handle " ++ "non-dword aligned buffer case\n", ++ __func__); ++ return; ++ } ++ } ++ if (!hc->ep_is_in) { ++ dwc_memcpy(qh->dw_align_buf, ptr, hc->xfer_len); ++ } ++ hc->align_buff = qh->dw_align_buf_dma; ++ } else { ++ hc->align_buff = 0; ++ } ++ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || ++ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { ++ /* ++ * This value may be modified when the transfer is started to ++ * reflect the actual transfer length. ++ */ ++ hc->multi_count = dwc_hb_mult(qh->maxp); ++ } ++ ++ if (hcd->core_if->dma_desc_enable) ++ hc->desc_list_addr = qh->desc_list_dma; ++ ++ dwc_otg_hc_init(hcd->core_if, hc); ++ ++ local_irq_save(flags); ++ ++ if (fiq_enable) { ++ local_fiq_disable(); ++ fiq_fsm_spin_lock(&hcd->fiq_state->lock); ++ } ++ ++ /* Enable the top level host channel interrupt. */ ++ intr_enable = (1 << hc->hc_num); ++ DWC_MODIFY_REG32(&hcd->core_if->host_if->host_global_regs->haintmsk, 0, intr_enable); ++ ++ /* Make sure host channel interrupts are enabled. */ ++ gintmsk.b.hcintr = 1; ++ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32); ++ ++ if (fiq_enable) { ++ fiq_fsm_spin_unlock(&hcd->fiq_state->lock); ++ local_fiq_enable(); ++ } ++ ++ local_irq_restore(flags); ++ hc->qh = qh; ++} ++ ++ ++/** ++ * fiq_fsm_transaction_suitable() - Test a QH for compatibility with the FIQ ++ * @qh: pointer to the endpoint's queue head ++ * ++ * Transaction start/end control flow is grafted onto the existing dwc_otg ++ * mechanisms, to avoid spaghettifying the functions more than they already are. ++ * This function's eligibility check is altered by debug parameter. ++ * ++ * Returns: 0 for unsuitable, 1 implies the FIQ can be enabled for this transaction. ++ */ ++ ++int fiq_fsm_transaction_suitable(dwc_otg_qh_t *qh) ++{ ++ if (qh->do_split) { ++ switch (qh->ep_type) { ++ case UE_CONTROL: ++ case UE_BULK: ++ if (fiq_fsm_mask & (1 << 0)) ++ return 1; ++ break; ++ case UE_INTERRUPT: ++ case UE_ISOCHRONOUS: ++ if (fiq_fsm_mask & (1 << 1)) ++ return 1; ++ break; ++ default: ++ break; ++ } ++ } else if (qh->ep_type == UE_ISOCHRONOUS) { ++ if (fiq_fsm_mask & (1 << 2)) { ++ /* HS ISOCH support. We test for compatibility: ++ * - DWORD aligned buffers ++ * - Must be at least 2 transfers (otherwise pointless to use the FIQ) ++ * If yes, then the fsm enqueue function will handle the state machine setup. ++ */ ++ dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); ++ dwc_otg_hcd_urb_t *urb = qtd->urb; ++ struct dwc_otg_hcd_iso_packet_desc (*iso_descs)[0] = &urb->iso_descs; ++ int nr_iso_frames = urb->packet_count; ++ int i; ++ uint32_t ptr; ++ ++ if (nr_iso_frames < 2) ++ return 0; ++ for (i = 0; i < nr_iso_frames; i++) { ++ ptr = urb->dma + iso_descs[i]->offset; ++ if (ptr & 0x3) { ++ printk_ratelimited("%s: Non-Dword aligned isochronous frame offset." ++ " Cannot queue FIQ-accelerated transfer to device %d endpoint %d\n", ++ __FUNCTION__, qh->channel->dev_addr, qh->channel->ep_num); ++ return 0; ++ } ++ } ++ return 1; ++ } ++ } ++ return 0; ++} ++ ++/** ++ * fiq_fsm_setup_periodic_dma() - Set up DMA bounce buffers ++ * @hcd: Pointer to the dwc_otg_hcd struct ++ * @qh: Pointer to the endpoint's queue head ++ * ++ * Periodic split transactions are transmitted modulo 188 bytes. ++ * This necessitates slicing data up into buckets for isochronous out ++ * and fixing up the DMA address for all IN transfers. ++ * ++ * Returns 1 if the DMA bounce buffers have been used, 0 if the default ++ * HC buffer has been used. ++ */ ++int fiq_fsm_setup_periodic_dma(dwc_otg_hcd_t *hcd, struct fiq_channel_state *st, dwc_otg_qh_t *qh) ++ { ++ int frame_length, i = 0; ++ uint8_t *ptr = NULL; ++ dwc_hc_t *hc = qh->channel; ++ struct fiq_dma_blob *blob; ++ struct dwc_otg_hcd_iso_packet_desc *frame_desc; ++ ++ for (i = 0; i < 6; i++) { ++ st->dma_info.slot_len[i] = 255; ++ } ++ st->dma_info.index = 0; ++ i = 0; ++ if (hc->ep_is_in) { ++ /* ++ * Set dma_regs to bounce buffer. FIQ will update the ++ * state depending on transaction progress. ++ */ ++ blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base; ++ st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0]; ++ /* Calculate the max number of CSPLITS such that the FIQ can time out ++ * a transaction if it fails. ++ */ ++ frame_length = st->hcchar_copy.b.mps; ++ do { ++ i++; ++ frame_length -= 188; ++ } while (frame_length >= 0); ++ st->nrpackets = i; ++ return 1; ++ } else { ++ if (qh->ep_type == UE_ISOCHRONOUS) { ++ ++ dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); ++ ++ frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; ++ frame_length = frame_desc->length; ++ ++ /* Virtual address for bounce buffers */ ++ blob = hcd->fiq_dmab; ++ ++ ptr = qtd->urb->buf + frame_desc->offset; ++ if (frame_length == 0) { ++ /* ++ * for isochronous transactions, we must still transmit a packet ++ * even if the length is zero. ++ */ ++ st->dma_info.slot_len[0] = 0; ++ st->nrpackets = 1; ++ } else { ++ do { ++ if (frame_length <= 188) { ++ dwc_memcpy(&blob->channel[hc->hc_num].index[i].buf[0], ptr, frame_length); ++ st->dma_info.slot_len[i] = frame_length; ++ ptr += frame_length; ++ } else { ++ dwc_memcpy(&blob->channel[hc->hc_num].index[i].buf[0], ptr, 188); ++ st->dma_info.slot_len[i] = 188; ++ ptr += 188; ++ } ++ i++; ++ frame_length -= 188; ++ } while (frame_length > 0); ++ st->nrpackets = i; ++ } ++ ptr = qtd->urb->buf + frame_desc->offset; ++ /* Point the HC at the DMA address of the bounce buffers */ ++ blob = (struct fiq_dma_blob *) hcd->fiq_state->dma_base; ++ st->hcdma_copy.d32 = (uint32_t) &blob->channel[hc->hc_num].index[0].buf[0]; ++ ++ /* fixup xfersize to the actual packet size */ ++ st->hctsiz_copy.b.pid = 0; ++ st->hctsiz_copy.b.xfersize = st->dma_info.slot_len[0]; ++ return 1; ++ } else { ++ /* For interrupt, single OUT packet required, goes in the SSPLIT from hc_buff. */ ++ return 0; ++ } ++ } ++} ++ ++/* ++ * Pushing a periodic request into the queue near the EOF1 point ++ * in a microframe causes erroneous behaviour (frmovrun) interrupt. ++ * Usually, the request goes out on the bus causing a transfer but ++ * the core does not transfer the data to memory. ++ * This guard interval (in number of 60MHz clocks) is required which ++ * must cater for CPU latency between reading the value and enabling ++ * the channel. ++ */ ++#define PERIODIC_FRREM_BACKOFF 1000 ++ ++int fiq_fsm_queue_isoc_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) ++{ ++ dwc_hc_t *hc = qh->channel; ++ dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num]; ++ dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); ++ int frame; ++ struct fiq_channel_state *st = &hcd->fiq_state->channel[hc->hc_num]; ++ int xfer_len, nrpackets; ++ hcdma_data_t hcdma; ++ hfnum_data_t hfnum; ++ ++ if (st->fsm != FIQ_PASSTHROUGH) ++ return 0; ++ ++ st->nr_errors = 0; ++ ++ st->hcchar_copy.d32 = 0; ++ st->hcchar_copy.b.mps = hc->max_packet; ++ st->hcchar_copy.b.epdir = hc->ep_is_in; ++ st->hcchar_copy.b.devaddr = hc->dev_addr; ++ st->hcchar_copy.b.epnum = hc->ep_num; ++ st->hcchar_copy.b.eptype = hc->ep_type; ++ ++ st->hcintmsk_copy.b.chhltd = 1; ++ ++ frame = dwc_otg_hcd_get_frame_number(hcd); ++ st->hcchar_copy.b.oddfrm = (frame & 0x1) ? 0 : 1; ++ ++ st->hcchar_copy.b.lspddev = 0; ++ /* Enable the channel later as a final register write. */ ++ ++ st->hcsplt_copy.d32 = 0; ++ ++ st->hs_isoc_info.iso_desc = (struct dwc_otg_hcd_iso_packet_desc *) &qtd->urb->iso_descs; ++ st->hs_isoc_info.nrframes = qtd->urb->packet_count; ++ /* grab the next DMA address offset from the array */ ++ st->hcdma_copy.d32 = qtd->urb->dma; ++ hcdma.d32 = st->hcdma_copy.d32 + st->hs_isoc_info.iso_desc[0].offset; ++ ++ /* We need to set multi_count. This is a bit tricky - has to be set per-transaction as ++ * the core needs to be told to send the correct number. Caution: for IN transfers, ++ * this is always set to the maximum size of the endpoint. */ ++ xfer_len = st->hs_isoc_info.iso_desc[0].length; ++ nrpackets = (xfer_len + st->hcchar_copy.b.mps - 1) / st->hcchar_copy.b.mps; ++ if (nrpackets == 0) ++ nrpackets = 1; ++ st->hcchar_copy.b.multicnt = nrpackets; ++ st->hctsiz_copy.b.pktcnt = nrpackets; ++ ++ /* Initial PID also needs to be set */ ++ if (st->hcchar_copy.b.epdir == 0) { ++ st->hctsiz_copy.b.xfersize = xfer_len; ++ switch (st->hcchar_copy.b.multicnt) { ++ case 1: ++ st->hctsiz_copy.b.pid = DWC_PID_DATA0; ++ break; ++ case 2: ++ case 3: ++ st->hctsiz_copy.b.pid = DWC_PID_MDATA; ++ break; ++ } ++ ++ } else { ++ st->hctsiz_copy.b.xfersize = nrpackets * st->hcchar_copy.b.mps; ++ switch (st->hcchar_copy.b.multicnt) { ++ case 1: ++ st->hctsiz_copy.b.pid = DWC_PID_DATA0; ++ break; ++ case 2: ++ st->hctsiz_copy.b.pid = DWC_PID_DATA1; ++ break; ++ case 3: ++ st->hctsiz_copy.b.pid = DWC_PID_DATA2; ++ break; ++ } ++ } ++ ++ st->hs_isoc_info.stride = qh->interval; ++ st->uframe_sleeps = 0; ++ ++ fiq_print(FIQDBG_INT, hcd->fiq_state, "FSMQ %01d ", hc->hc_num); ++ fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcchar_copy.d32); ++ fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hctsiz_copy.d32); ++ fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcdma_copy.d32); ++ hfnum.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum); ++ local_fiq_disable(); ++ fiq_fsm_spin_lock(&hcd->fiq_state->lock); ++ DWC_WRITE_REG32(&hc_regs->hctsiz, st->hctsiz_copy.d32); ++ DWC_WRITE_REG32(&hc_regs->hcsplt, st->hcsplt_copy.d32); ++ DWC_WRITE_REG32(&hc_regs->hcdma, st->hcdma_copy.d32); ++ DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32); ++ DWC_WRITE_REG32(&hc_regs->hcintmsk, st->hcintmsk_copy.d32); ++ if (hfnum.b.frrem < PERIODIC_FRREM_BACKOFF) { ++ /* Prevent queueing near EOF1. Bad things happen if a periodic ++ * split transaction is queued very close to EOF. SOF interrupt handler ++ * will wake this channel at the next interrupt. ++ */ ++ st->fsm = FIQ_HS_ISOC_SLEEPING; ++ st->uframe_sleeps = 1; ++ } else { ++ st->fsm = FIQ_HS_ISOC_TURBO; ++ st->hcchar_copy.b.chen = 1; ++ DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32); ++ } ++ mb(); ++ st->hcchar_copy.b.chen = 0; ++ fiq_fsm_spin_unlock(&hcd->fiq_state->lock); ++ local_fiq_enable(); ++ return 0; ++} ++ ++ ++/** ++ * fiq_fsm_queue_split_transaction() - Set up a host channel and FIQ state ++ * @hcd: Pointer to the dwc_otg_hcd struct ++ * @qh: Pointer to the endpoint's queue head ++ * ++ * This overrides the dwc_otg driver's normal method of queueing a transaction. ++ * Called from dwc_otg_hcd_queue_transactions(), this performs specific setup ++ * for the nominated host channel. ++ * ++ * For periodic transfers, it also peeks at the FIQ state to see if an immediate ++ * start is possible. If not, then the FIQ is left to start the transfer. ++ */ ++int fiq_fsm_queue_split_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh) ++{ ++ int start_immediate = 1, i; ++ hfnum_data_t hfnum; ++ dwc_hc_t *hc = qh->channel; ++ dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num]; ++ /* Program HC registers, setup FIQ_state, examine FIQ if periodic, start transfer (not if uframe 5) */ ++ int hub_addr, port_addr, frame, uframe; ++ struct fiq_channel_state *st = &hcd->fiq_state->channel[hc->hc_num]; ++ ++ if (st->fsm != FIQ_PASSTHROUGH) ++ return 0; ++ st->nr_errors = 0; ++ ++ st->hcchar_copy.d32 = 0; ++ st->hcchar_copy.b.mps = hc->max_packet; ++ st->hcchar_copy.b.epdir = hc->ep_is_in; ++ st->hcchar_copy.b.devaddr = hc->dev_addr; ++ st->hcchar_copy.b.epnum = hc->ep_num; ++ st->hcchar_copy.b.eptype = hc->ep_type; ++ if (hc->ep_type & 0x1) { ++ if (hc->ep_is_in) ++ st->hcchar_copy.b.multicnt = 3; ++ else ++ /* Docs say set this to 1, but driver sets to 0! */ ++ st->hcchar_copy.b.multicnt = 0; ++ } else { ++ st->hcchar_copy.b.multicnt = 1; ++ st->hcchar_copy.b.oddfrm = 0; ++ } ++ st->hcchar_copy.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW) ? 1 : 0; ++ /* Enable the channel later as a final register write. */ ++ ++ st->hcsplt_copy.d32 = 0; ++ if(qh->do_split) { ++ hcd->fops->hub_info(hcd, DWC_CIRCLEQ_FIRST(&qh->qtd_list)->urb->priv, &hub_addr, &port_addr); ++ st->hcsplt_copy.b.compsplt = 0; ++ st->hcsplt_copy.b.spltena = 1; ++ // XACTPOS is for isoc-out only but needs initialising anyway. ++ st->hcsplt_copy.b.xactpos = ISOC_XACTPOS_ALL; ++ if((qh->ep_type == DWC_OTG_EP_TYPE_ISOC) && (!qh->ep_is_in)) { ++ /* For packetsize 0 < L < 188, ISOC_XACTPOS_ALL. ++ * for longer than this, ISOC_XACTPOS_BEGIN and the FIQ ++ * will update as necessary. ++ */ ++ if (hc->xfer_len > 188) { ++ st->hcsplt_copy.b.xactpos = ISOC_XACTPOS_BEGIN; ++ } ++ } ++ st->hcsplt_copy.b.hubaddr = (uint8_t) hub_addr; ++ st->hcsplt_copy.b.prtaddr = (uint8_t) port_addr; ++ st->hub_addr = hub_addr; ++ st->port_addr = port_addr; ++ } ++ ++ st->hctsiz_copy.d32 = 0; ++ st->hctsiz_copy.b.dopng = 0; ++ st->hctsiz_copy.b.pid = hc->data_pid_start; ++ ++ if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) { ++ hc->xfer_len = hc->max_packet; ++ } else if (!hc->ep_is_in && (hc->xfer_len > 188)) { ++ hc->xfer_len = 188; ++ } ++ st->hctsiz_copy.b.xfersize = hc->xfer_len; ++ ++ st->hctsiz_copy.b.pktcnt = 1; ++ ++ if (hc->ep_type & 0x1) { ++ /* ++ * For potentially multi-packet transfers, must use the DMA bounce buffers. For IN transfers, ++ * the DMA address is the address of the first 188byte slot buffer in the bounce buffer array. ++ * For multi-packet OUT transfers, we need to copy the data into the bounce buffer array so the FIQ can punt ++ * the right address out as necessary. hc->xfer_buff and hc->xfer_len have already been set ++ * in assign_and_init_hc(), but this is for the eventual transaction completion only. The FIQ ++ * must not touch internal driver state. ++ */ ++ if(!fiq_fsm_setup_periodic_dma(hcd, st, qh)) { ++ if (hc->align_buff) { ++ st->hcdma_copy.d32 = hc->align_buff; ++ } else { ++ st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF); ++ } ++ } ++ } else { ++ if (hc->align_buff) { ++ st->hcdma_copy.d32 = hc->align_buff; ++ } else { ++ st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF); ++ } ++ } ++ /* The FIQ depends upon no other interrupts being enabled except channel halt. ++ * Fixup channel interrupt mask. */ ++ st->hcintmsk_copy.d32 = 0; ++ st->hcintmsk_copy.b.chhltd = 1; ++ st->hcintmsk_copy.b.ahberr = 1; ++ ++ /* Hack courtesy of FreeBSD: apparently forcing Interrupt Split transactions ++ * as Control puts the transfer into the non-periodic request queue and the ++ * non-periodic handler in the hub. Makes things lots easier. ++ */ ++ if ((fiq_fsm_mask & 0x8) && hc->ep_type == UE_INTERRUPT) { ++ st->hcchar_copy.b.multicnt = 0; ++ st->hcchar_copy.b.oddfrm = 0; ++ st->hcchar_copy.b.eptype = UE_CONTROL; ++ if (hc->align_buff) { ++ st->hcdma_copy.d32 = hc->align_buff; ++ } else { ++ st->hcdma_copy.d32 = ((unsigned long) hc->xfer_buff & 0xFFFFFFFF); ++ } ++ } ++ DWC_WRITE_REG32(&hc_regs->hcdma, st->hcdma_copy.d32); ++ DWC_WRITE_REG32(&hc_regs->hctsiz, st->hctsiz_copy.d32); ++ DWC_WRITE_REG32(&hc_regs->hcsplt, st->hcsplt_copy.d32); ++ DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32); ++ DWC_WRITE_REG32(&hc_regs->hcintmsk, st->hcintmsk_copy.d32); ++ ++ local_fiq_disable(); ++ fiq_fsm_spin_lock(&hcd->fiq_state->lock); ++ ++ if (hc->ep_type & 0x1) { ++ hfnum.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum); ++ frame = (hfnum.b.frnum & ~0x7) >> 3; ++ uframe = hfnum.b.frnum & 0x7; ++ if (hfnum.b.frrem < PERIODIC_FRREM_BACKOFF) { ++ /* Prevent queueing near EOF1. Bad things happen if a periodic ++ * split transaction is queued very close to EOF. ++ */ ++ start_immediate = 0; ++ } else if (uframe == 5) { ++ start_immediate = 0; ++ } else if (hc->ep_type == UE_ISOCHRONOUS && !hc->ep_is_in) { ++ start_immediate = 0; ++ } else if (hc->ep_is_in && fiq_fsm_too_late(hcd->fiq_state, hc->hc_num)) { ++ start_immediate = 0; ++ } else { ++ /* Search through all host channels to determine if a transaction ++ * is currently in progress */ ++ for (i = 0; i < hcd->core_if->core_params->host_channels; i++) { ++ if (i == hc->hc_num || hcd->fiq_state->channel[i].fsm == FIQ_PASSTHROUGH) ++ continue; ++ switch (hcd->fiq_state->channel[i].fsm) { ++ /* TT is reserved for channels that are in the middle of a periodic ++ * split transaction. ++ */ ++ case FIQ_PER_SSPLIT_STARTED: ++ case FIQ_PER_CSPLIT_WAIT: ++ case FIQ_PER_CSPLIT_NYET1: ++ case FIQ_PER_CSPLIT_POLL: ++ case FIQ_PER_ISO_OUT_ACTIVE: ++ case FIQ_PER_ISO_OUT_LAST: ++ if (hcd->fiq_state->channel[i].hub_addr == hub_addr && ++ hcd->fiq_state->channel[i].port_addr == port_addr) { ++ start_immediate = 0; ++ } ++ break; ++ default: ++ break; ++ } ++ if (!start_immediate) ++ break; ++ } ++ } ++ } ++ if ((fiq_fsm_mask & 0x8) && hc->ep_type == UE_INTERRUPT) ++ start_immediate = 1; ++ ++ fiq_print(FIQDBG_INT, hcd->fiq_state, "FSMQ %01d %01d", hc->hc_num, start_immediate); ++ fiq_print(FIQDBG_INT, hcd->fiq_state, "%08d", hfnum.b.frrem); ++ //fiq_print(FIQDBG_INT, hcd->fiq_state, "H:%02dP:%02d", hub_addr, port_addr); ++ //fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hctsiz_copy.d32); ++ //fiq_print(FIQDBG_INT, hcd->fiq_state, "%08x", st->hcdma_copy.d32); ++ switch (hc->ep_type) { ++ case UE_CONTROL: ++ case UE_BULK: ++ st->fsm = FIQ_NP_SSPLIT_STARTED; ++ break; ++ case UE_ISOCHRONOUS: ++ if (hc->ep_is_in) { ++ if (start_immediate) { ++ st->fsm = FIQ_PER_SSPLIT_STARTED; ++ } else { ++ st->fsm = FIQ_PER_SSPLIT_QUEUED; ++ } ++ } else { ++ if (start_immediate) { ++ /* Single-isoc OUT packets don't require FIQ involvement */ ++ if (st->nrpackets == 1) { ++ st->fsm = FIQ_PER_ISO_OUT_LAST; ++ } else { ++ st->fsm = FIQ_PER_ISO_OUT_ACTIVE; ++ } ++ } else { ++ st->fsm = FIQ_PER_ISO_OUT_PENDING; ++ } ++ } ++ break; ++ case UE_INTERRUPT: ++ if (fiq_fsm_mask & 0x8) { ++ st->fsm = FIQ_NP_SSPLIT_STARTED; ++ } else if (start_immediate) { ++ st->fsm = FIQ_PER_SSPLIT_STARTED; ++ } else { ++ st->fsm = FIQ_PER_SSPLIT_QUEUED; ++ } ++ default: ++ break; ++ } ++ if (start_immediate) { ++ /* Set the oddfrm bit as close as possible to actual queueing */ ++ frame = dwc_otg_hcd_get_frame_number(hcd); ++ st->expected_uframe = (frame + 1) & 0x3FFF; ++ st->hcchar_copy.b.oddfrm = (frame & 0x1) ? 0 : 1; ++ st->hcchar_copy.b.chen = 1; ++ DWC_WRITE_REG32(&hc_regs->hcchar, st->hcchar_copy.d32); ++ } ++ mb(); ++ fiq_fsm_spin_unlock(&hcd->fiq_state->lock); ++ local_fiq_enable(); ++ return 0; ++} ++ ++ ++/** ++ * This function selects transactions from the HCD transfer schedule and ++ * assigns them to available host channels. It is called from HCD interrupt ++ * handler functions. ++ * ++ * @param hcd The HCD state structure. ++ * ++ * @return The types of new transactions that were assigned to host channels. ++ */ ++dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd) ++{ ++ dwc_list_link_t *qh_ptr; ++ dwc_otg_qh_t *qh; ++ int num_channels; ++ dwc_irqflags_t flags; ++ dwc_spinlock_t *channel_lock = hcd->channel_lock; ++ dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE; ++ ++#ifdef DEBUG_HOST_CHANNELS ++ last_sel_trans_num_per_scheduled = 0; ++ last_sel_trans_num_nonper_scheduled = 0; ++ last_sel_trans_num_avail_hc_at_start = hcd->available_host_channels; ++#endif /* DEBUG_HOST_CHANNELS */ ++ ++ /* Process entries in the periodic ready list. */ ++ qh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready); ++ ++ while (qh_ptr != &hcd->periodic_sched_ready && ++ !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) { ++ ++ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); ++ ++ if (microframe_schedule) { ++ // Make sure we leave one channel for non periodic transactions. ++ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags); ++ if (hcd->available_host_channels <= 1) { ++ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); ++ break; ++ } ++ hcd->available_host_channels--; ++ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); ++#ifdef DEBUG_HOST_CHANNELS ++ last_sel_trans_num_per_scheduled++; ++#endif /* DEBUG_HOST_CHANNELS */ ++ } ++ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); ++ assign_and_init_hc(hcd, qh); ++ ++ /* ++ * Move the QH from the periodic ready schedule to the ++ * periodic assigned schedule. ++ */ ++ qh_ptr = DWC_LIST_NEXT(qh_ptr); ++ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags); ++ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned, ++ &qh->qh_list_entry); ++ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); ++ } ++ ++ /* ++ * Process entries in the inactive portion of the non-periodic ++ * schedule. Some free host channels may not be used if they are ++ * reserved for periodic transfers. ++ */ ++ qh_ptr = hcd->non_periodic_sched_inactive.next; ++ num_channels = hcd->core_if->core_params->host_channels; ++ while (qh_ptr != &hcd->non_periodic_sched_inactive && ++ (microframe_schedule || hcd->non_periodic_channels < ++ num_channels - hcd->periodic_channels) && ++ !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) { ++ ++ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); ++ /* ++ * Check to see if this is a NAK'd retransmit, in which case ignore for retransmission ++ * we hold off on bulk retransmissions to reduce NAK interrupt overhead for full-speed ++ * cheeky devices that just hold off using NAKs ++ */ ++ if (fiq_enable && nak_holdoff && qh->do_split) { ++ if (qh->nak_frame != 0xffff) { ++ uint16_t next_frame = dwc_frame_num_inc(qh->nak_frame, (qh->ep_type == UE_BULK) ? nak_holdoff : 8); ++ uint16_t frame = dwc_otg_hcd_get_frame_number(hcd); ++ if (dwc_frame_num_le(frame, next_frame)) { ++ if(dwc_frame_num_le(next_frame, hcd->fiq_state->next_sched_frame)) { ++ hcd->fiq_state->next_sched_frame = next_frame; ++ } ++ qh_ptr = DWC_LIST_NEXT(qh_ptr); ++ continue; ++ } else { ++ qh->nak_frame = 0xFFFF; ++ } ++ } ++ } ++ ++ if (microframe_schedule) { ++ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags); ++ if (hcd->available_host_channels < 1) { ++ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); ++ break; ++ } ++ hcd->available_host_channels--; ++ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); ++#ifdef DEBUG_HOST_CHANNELS ++ last_sel_trans_num_nonper_scheduled++; ++#endif /* DEBUG_HOST_CHANNELS */ ++ } ++ ++ assign_and_init_hc(hcd, qh); ++ ++ /* ++ * Move the QH from the non-periodic inactive schedule to the ++ * non-periodic active schedule. ++ */ ++ qh_ptr = DWC_LIST_NEXT(qh_ptr); ++ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags); ++ DWC_LIST_MOVE_HEAD(&hcd->non_periodic_sched_active, ++ &qh->qh_list_entry); ++ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); ++ ++ ++ if (!microframe_schedule) ++ hcd->non_periodic_channels++; ++ } ++ /* we moved a non-periodic QH to the active schedule. If the inactive queue is empty, ++ * stop the FIQ from kicking us. We could potentially still have elements here if we ++ * ran out of host channels. ++ */ ++ if (fiq_enable) { ++ if (DWC_LIST_EMPTY(&hcd->non_periodic_sched_inactive)) { ++ hcd->fiq_state->kick_np_queues = 0; ++ } else { ++ /* For each entry remaining in the NP inactive queue, ++ * if this a NAK'd retransmit then don't set the kick flag. ++ */ ++ if(nak_holdoff) { ++ DWC_LIST_FOREACH(qh_ptr, &hcd->non_periodic_sched_inactive) { ++ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); ++ if (qh->nak_frame == 0xFFFF) { ++ hcd->fiq_state->kick_np_queues = 1; ++ } ++ } ++ } ++ } ++ } ++ if(!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) ++ ret_val |= DWC_OTG_TRANSACTION_PERIODIC; ++ ++ if(!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active)) ++ ret_val |= DWC_OTG_TRANSACTION_NON_PERIODIC; ++ ++ ++#ifdef DEBUG_HOST_CHANNELS ++ last_sel_trans_num_avail_hc_at_end = hcd->available_host_channels; ++#endif /* DEBUG_HOST_CHANNELS */ ++ return ret_val; ++} ++ ++/** ++ * Attempts to queue a single transaction request for a host channel ++ * associated with either a periodic or non-periodic transfer. This function ++ * assumes that there is space available in the appropriate request queue. For ++ * an OUT transfer or SETUP transaction in Slave mode, it checks whether space ++ * is available in the appropriate Tx FIFO. ++ * ++ * @param hcd The HCD state structure. ++ * @param hc Host channel descriptor associated with either a periodic or ++ * non-periodic transfer. ++ * @param fifo_dwords_avail Number of DWORDs available in the periodic Tx ++ * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic ++ * transfers. ++ * ++ * @return 1 if a request is queued and more requests may be needed to ++ * complete the transfer, 0 if no more requests are required for this ++ * transfer, -1 if there is insufficient space in the Tx FIFO. ++ */ ++static int queue_transaction(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, uint16_t fifo_dwords_avail) ++{ ++ int retval; ++ ++ if (hcd->core_if->dma_enable) { ++ if (hcd->core_if->dma_desc_enable) { ++ if (!hc->xfer_started ++ || (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) { ++ dwc_otg_hcd_start_xfer_ddma(hcd, hc->qh); ++ hc->qh->ping_state = 0; ++ } ++ } else if (!hc->xfer_started) { ++ if (fiq_fsm_enable && hc->error_state) { ++ hcd->fiq_state->channel[hc->hc_num].nr_errors = ++ DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list)->error_count; ++ hcd->fiq_state->channel[hc->hc_num].fsm = ++ FIQ_PASSTHROUGH_ERRORSTATE; ++ } ++ dwc_otg_hc_start_transfer(hcd->core_if, hc); ++ hc->qh->ping_state = 0; ++ } ++ retval = 0; ++ } else if (hc->halt_pending) { ++ /* Don't queue a request if the channel has been halted. */ ++ retval = 0; ++ } else if (hc->halt_on_queue) { ++ dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status); ++ retval = 0; ++ } else if (hc->do_ping) { ++ if (!hc->xfer_started) { ++ dwc_otg_hc_start_transfer(hcd->core_if, hc); ++ } ++ retval = 0; ++ } else if (!hc->ep_is_in || hc->data_pid_start == DWC_OTG_HC_PID_SETUP) { ++ if ((fifo_dwords_avail * 4) >= hc->max_packet) { ++ if (!hc->xfer_started) { ++ dwc_otg_hc_start_transfer(hcd->core_if, hc); ++ retval = 1; ++ } else { ++ retval = ++ dwc_otg_hc_continue_transfer(hcd->core_if, ++ hc); ++ } ++ } else { ++ retval = -1; ++ } ++ } else { ++ if (!hc->xfer_started) { ++ dwc_otg_hc_start_transfer(hcd->core_if, hc); ++ retval = 1; ++ } else { ++ retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc); ++ } ++ } ++ ++ return retval; ++} ++ ++/** ++ * Processes periodic channels for the next frame and queues transactions for ++ * these channels to the DWC_otg controller. After queueing transactions, the ++ * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions ++ * to queue as Periodic Tx FIFO or request queue space becomes available. ++ * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. ++ */ ++static void process_periodic_channels(dwc_otg_hcd_t * hcd) ++{ ++ hptxsts_data_t tx_status; ++ dwc_list_link_t *qh_ptr; ++ dwc_otg_qh_t *qh; ++ int status = 0; ++ int no_queue_space = 0; ++ int no_fifo_space = 0; ++ ++ dwc_otg_host_global_regs_t *host_regs; ++ host_regs = hcd->core_if->host_if->host_global_regs; ++ ++ DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n"); ++#ifdef DEBUG ++ tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts); ++ DWC_DEBUGPL(DBG_HCDV, ++ " P Tx Req Queue Space Avail (before queue): %d\n", ++ tx_status.b.ptxqspcavail); ++ DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (before queue): %d\n", ++ tx_status.b.ptxfspcavail); ++#endif ++ ++ qh_ptr = hcd->periodic_sched_assigned.next; ++ while (qh_ptr != &hcd->periodic_sched_assigned) { ++ tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts); ++ if (tx_status.b.ptxqspcavail == 0) { ++ no_queue_space = 1; ++ break; ++ } ++ ++ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); ++ ++ // Do not send a split start transaction any later than frame .6 ++ // Note, we have to schedule a periodic in .5 to make it go in .6 ++ if(fiq_fsm_enable && qh->do_split && ((dwc_otg_hcd_get_frame_number(hcd) + 1) & 7) > 6) ++ { ++ qh_ptr = qh_ptr->next; ++ hcd->fiq_state->next_sched_frame = dwc_otg_hcd_get_frame_number(hcd) | 7; ++ continue; ++ } ++ ++ if (fiq_fsm_enable && fiq_fsm_transaction_suitable(qh)) { ++ if (qh->do_split) ++ fiq_fsm_queue_split_transaction(hcd, qh); ++ else ++ fiq_fsm_queue_isoc_transaction(hcd, qh); ++ } else { ++ ++ /* ++ * Set a flag if we're queueing high-bandwidth in slave mode. ++ * The flag prevents any halts to get into the request queue in ++ * the middle of multiple high-bandwidth packets getting queued. ++ */ ++ if (!hcd->core_if->dma_enable && qh->channel->multi_count > 1) { ++ hcd->core_if->queuing_high_bandwidth = 1; ++ } ++ status = queue_transaction(hcd, qh->channel, ++ tx_status.b.ptxfspcavail); ++ if (status < 0) { ++ no_fifo_space = 1; ++ break; ++ } ++ } ++ ++ /* ++ * In Slave mode, stay on the current transfer until there is ++ * nothing more to do or the high-bandwidth request count is ++ * reached. In DMA mode, only need to queue one request. The ++ * controller automatically handles multiple packets for ++ * high-bandwidth transfers. ++ */ ++ if (hcd->core_if->dma_enable || status == 0 || ++ qh->channel->requests == qh->channel->multi_count) { ++ qh_ptr = qh_ptr->next; ++ /* ++ * Move the QH from the periodic assigned schedule to ++ * the periodic queued schedule. ++ */ ++ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_queued, ++ &qh->qh_list_entry); ++ ++ /* done queuing high bandwidth */ ++ hcd->core_if->queuing_high_bandwidth = 0; ++ } ++ } ++ ++ if (!hcd->core_if->dma_enable) { ++ dwc_otg_core_global_regs_t *global_regs; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ global_regs = hcd->core_if->core_global_regs; ++ intr_mask.b.ptxfempty = 1; ++#ifdef DEBUG ++ tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts); ++ DWC_DEBUGPL(DBG_HCDV, ++ " P Tx Req Queue Space Avail (after queue): %d\n", ++ tx_status.b.ptxqspcavail); ++ DWC_DEBUGPL(DBG_HCDV, ++ " P Tx FIFO Space Avail (after queue): %d\n", ++ tx_status.b.ptxfspcavail); ++#endif ++ if (!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned) || ++ no_queue_space || no_fifo_space) { ++ /* ++ * May need to queue more transactions as the request ++ * queue or Tx FIFO empties. Enable the periodic Tx ++ * FIFO empty interrupt. (Always use the half-empty ++ * level to ensure that new requests are loaded as ++ * soon as possible.) ++ */ ++ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, ++ intr_mask.d32); ++ } else { ++ /* ++ * Disable the Tx FIFO empty interrupt since there are ++ * no more transactions that need to be queued right ++ * now. This function is called from interrupt ++ * handlers to queue more transactions as transfer ++ * states change. ++ */ ++ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, ++ 0); ++ } ++ } ++} ++ ++/** ++ * Processes active non-periodic channels and queues transactions for these ++ * channels to the DWC_otg controller. After queueing transactions, the NP Tx ++ * FIFO Empty interrupt is enabled if there are more transactions to queue as ++ * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx ++ * FIFO Empty interrupt is disabled. ++ */ ++static void process_non_periodic_channels(dwc_otg_hcd_t * hcd) ++{ ++ gnptxsts_data_t tx_status; ++ dwc_list_link_t *orig_qh_ptr; ++ dwc_otg_qh_t *qh; ++ int status; ++ int no_queue_space = 0; ++ int no_fifo_space = 0; ++ int more_to_do = 0; ++ ++ dwc_otg_core_global_regs_t *global_regs = ++ hcd->core_if->core_global_regs; ++ ++ DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n"); ++#ifdef DEBUG ++ tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts); ++ DWC_DEBUGPL(DBG_HCDV, ++ " NP Tx Req Queue Space Avail (before queue): %d\n", ++ tx_status.b.nptxqspcavail); ++ DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (before queue): %d\n", ++ tx_status.b.nptxfspcavail); ++#endif ++ /* ++ * Keep track of the starting point. Skip over the start-of-list ++ * entry. ++ */ ++ if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) { ++ hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next; ++ } ++ orig_qh_ptr = hcd->non_periodic_qh_ptr; ++ ++ /* ++ * Process once through the active list or until no more space is ++ * available in the request queue or the Tx FIFO. ++ */ ++ do { ++ tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts); ++ if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) { ++ no_queue_space = 1; ++ break; ++ } ++ ++ qh = DWC_LIST_ENTRY(hcd->non_periodic_qh_ptr, dwc_otg_qh_t, ++ qh_list_entry); ++ ++ if(fiq_fsm_enable && fiq_fsm_transaction_suitable(qh)) { ++ fiq_fsm_queue_split_transaction(hcd, qh); ++ } else { ++ status = queue_transaction(hcd, qh->channel, ++ tx_status.b.nptxfspcavail); ++ ++ if (status > 0) { ++ more_to_do = 1; ++ } else if (status < 0) { ++ no_fifo_space = 1; ++ break; ++ } ++ } ++ /* Advance to next QH, skipping start-of-list entry. */ ++ hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next; ++ if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) { ++ hcd->non_periodic_qh_ptr = ++ hcd->non_periodic_qh_ptr->next; ++ } ++ ++ } while (hcd->non_periodic_qh_ptr != orig_qh_ptr); ++ ++ if (!hcd->core_if->dma_enable) { ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ intr_mask.b.nptxfempty = 1; ++ ++#ifdef DEBUG ++ tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts); ++ DWC_DEBUGPL(DBG_HCDV, ++ " NP Tx Req Queue Space Avail (after queue): %d\n", ++ tx_status.b.nptxqspcavail); ++ DWC_DEBUGPL(DBG_HCDV, ++ " NP Tx FIFO Space Avail (after queue): %d\n", ++ tx_status.b.nptxfspcavail); ++#endif ++ if (more_to_do || no_queue_space || no_fifo_space) { ++ /* ++ * May need to queue more transactions as the request ++ * queue or Tx FIFO empties. Enable the non-periodic ++ * Tx FIFO empty interrupt. (Always use the half-empty ++ * level to ensure that new requests are loaded as ++ * soon as possible.) ++ */ ++ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, ++ intr_mask.d32); ++ } else { ++ /* ++ * Disable the Tx FIFO empty interrupt since there are ++ * no more transactions that need to be queued right ++ * now. This function is called from interrupt ++ * handlers to queue more transactions as transfer ++ * states change. ++ */ ++ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, ++ 0); ++ } ++ } ++} ++ ++/** ++ * This function processes the currently active host channels and queues ++ * transactions for these channels to the DWC_otg controller. It is called ++ * from HCD interrupt handler functions. ++ * ++ * @param hcd The HCD state structure. ++ * @param tr_type The type(s) of transactions to queue (non-periodic, ++ * periodic, or both). ++ */ ++void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd, ++ dwc_otg_transaction_type_e tr_type) ++{ ++#ifdef DEBUG_SOF ++ DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n"); ++#endif ++ /* Process host channels associated with periodic transfers. */ ++ if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC || ++ tr_type == DWC_OTG_TRANSACTION_ALL) && ++ !DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) { ++ ++ process_periodic_channels(hcd); ++ } ++ ++ /* Process host channels associated with non-periodic transfers. */ ++ if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC || ++ tr_type == DWC_OTG_TRANSACTION_ALL) { ++ if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active)) { ++ process_non_periodic_channels(hcd); ++ } else { ++ /* ++ * Ensure NP Tx FIFO empty interrupt is disabled when ++ * there are no non-periodic transfers to process. ++ */ ++ gintmsk_data_t gintmsk = {.d32 = 0 }; ++ gintmsk.b.nptxfempty = 1; ++ ++ if (fiq_enable) { ++ local_fiq_disable(); ++ fiq_fsm_spin_lock(&hcd->fiq_state->lock); ++ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, gintmsk.d32, 0); ++ fiq_fsm_spin_unlock(&hcd->fiq_state->lock); ++ local_fiq_enable(); ++ } else { ++ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, gintmsk.d32, 0); ++ } ++ } ++ } ++} ++ ++#ifdef DWC_HS_ELECT_TST ++/* ++ * Quick and dirty hack to implement the HS Electrical Test ++ * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature. ++ * ++ * This code was copied from our userspace app "hset". It sends a ++ * Get Device Descriptor control sequence in two parts, first the ++ * Setup packet by itself, followed some time later by the In and ++ * Ack packets. Rather than trying to figure out how to add this ++ * functionality to the normal driver code, we just hijack the ++ * hardware, using these two function to drive the hardware ++ * directly. ++ */ ++ ++static dwc_otg_core_global_regs_t *global_regs; ++static dwc_otg_host_global_regs_t *hc_global_regs; ++static dwc_otg_hc_regs_t *hc_regs; ++static uint32_t *data_fifo; ++ ++static void do_setup(void) ++{ ++ gintsts_data_t gintsts; ++ hctsiz_data_t hctsiz; ++ hcchar_data_t hcchar; ++ haint_data_t haint; ++ hcint_data_t hcint; ++ ++ /* Enable HAINTs */ ++ DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001); ++ ++ /* Enable HCINTs */ ++ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ ++ /* Read HAINT */ ++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); ++ ++ /* Read HCINT */ ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ ++ /* Clear HCINT */ ++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ ++ /* ++ * Send Setup packet (Get Device Descriptor) ++ */ ++ ++ /* Make sure channel is disabled */ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ if (hcchar.b.chen) { ++ hcchar.b.chdis = 1; ++// hcchar.b.chen = 1; ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); ++ //sleep(1); ++ dwc_mdelay(1000); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ ++ /* Read HAINT */ ++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); ++ ++ /* Read HCINT */ ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ ++ /* Clear HCINT */ ++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); ++ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ } ++ ++ /* Set HCTSIZ */ ++ hctsiz.d32 = 0; ++ hctsiz.b.xfersize = 8; ++ hctsiz.b.pktcnt = 1; ++ hctsiz.b.pid = DWC_OTG_HC_PID_SETUP; ++ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32); ++ ++ /* Set HCCHAR */ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL; ++ hcchar.b.epdir = 0; ++ hcchar.b.epnum = 0; ++ hcchar.b.mps = 8; ++ hcchar.b.chen = 1; ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); ++ ++ /* Fill FIFO with Setup data for Get Device Descriptor */ ++ data_fifo = (uint32_t *) ((char *)global_regs + 0x1000); ++ DWC_WRITE_REG32(data_fifo++, 0x01000680); ++ DWC_WRITE_REG32(data_fifo++, 0x00080000); ++ ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ ++ /* Wait for host channel interrupt */ ++ do { ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ } while (gintsts.b.hcintr == 0); ++ ++ /* Disable HCINTs */ ++ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000); ++ ++ /* Disable HAINTs */ ++ DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000); ++ ++ /* Read HAINT */ ++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); ++ ++ /* Read HCINT */ ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ ++ /* Clear HCINT */ ++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++} ++ ++static void do_in_ack(void) ++{ ++ gintsts_data_t gintsts; ++ hctsiz_data_t hctsiz; ++ hcchar_data_t hcchar; ++ haint_data_t haint; ++ hcint_data_t hcint; ++ host_grxsts_data_t grxsts; ++ ++ /* Enable HAINTs */ ++ DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001); ++ ++ /* Enable HCINTs */ ++ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ ++ /* Read HAINT */ ++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); ++ ++ /* Read HCINT */ ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ ++ /* Clear HCINT */ ++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ ++ /* ++ * Receive Control In packet ++ */ ++ ++ /* Make sure channel is disabled */ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ if (hcchar.b.chen) { ++ hcchar.b.chdis = 1; ++ hcchar.b.chen = 1; ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); ++ //sleep(1); ++ dwc_mdelay(1000); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ ++ /* Read HAINT */ ++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); ++ ++ /* Read HCINT */ ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ ++ /* Clear HCINT */ ++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); ++ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ } ++ ++ /* Set HCTSIZ */ ++ hctsiz.d32 = 0; ++ hctsiz.b.xfersize = 8; ++ hctsiz.b.pktcnt = 1; ++ hctsiz.b.pid = DWC_OTG_HC_PID_DATA1; ++ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32); ++ ++ /* Set HCCHAR */ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL; ++ hcchar.b.epdir = 1; ++ hcchar.b.epnum = 0; ++ hcchar.b.mps = 8; ++ hcchar.b.chen = 1; ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); ++ ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ ++ /* Wait for receive status queue interrupt */ ++ do { ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ } while (gintsts.b.rxstsqlvl == 0); ++ ++ /* Read RXSTS */ ++ grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp); ++ ++ /* Clear RXSTSQLVL in GINTSTS */ ++ gintsts.d32 = 0; ++ gintsts.b.rxstsqlvl = 1; ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); ++ ++ switch (grxsts.b.pktsts) { ++ case DWC_GRXSTS_PKTSTS_IN: ++ /* Read the data into the host buffer */ ++ if (grxsts.b.bcnt > 0) { ++ int i; ++ int word_count = (grxsts.b.bcnt + 3) / 4; ++ ++ data_fifo = (uint32_t *) ((char *)global_regs + 0x1000); ++ ++ for (i = 0; i < word_count; i++) { ++ (void)DWC_READ_REG32(data_fifo++); ++ } ++ } ++ break; ++ ++ default: ++ break; ++ } ++ ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ ++ /* Wait for receive status queue interrupt */ ++ do { ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ } while (gintsts.b.rxstsqlvl == 0); ++ ++ /* Read RXSTS */ ++ grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp); ++ ++ /* Clear RXSTSQLVL in GINTSTS */ ++ gintsts.d32 = 0; ++ gintsts.b.rxstsqlvl = 1; ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); ++ ++ switch (grxsts.b.pktsts) { ++ case DWC_GRXSTS_PKTSTS_IN_XFER_COMP: ++ break; ++ ++ default: ++ break; ++ } ++ ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ ++ /* Wait for host channel interrupt */ ++ do { ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ } while (gintsts.b.hcintr == 0); ++ ++ /* Read HAINT */ ++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); ++ ++ /* Read HCINT */ ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ ++ /* Clear HCINT */ ++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ ++// usleep(100000); ++// mdelay(100); ++ dwc_mdelay(1); ++ ++ /* ++ * Send handshake packet ++ */ ++ ++ /* Read HAINT */ ++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); ++ ++ /* Read HCINT */ ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ ++ /* Clear HCINT */ ++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ ++ /* Make sure channel is disabled */ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ if (hcchar.b.chen) { ++ hcchar.b.chdis = 1; ++ hcchar.b.chen = 1; ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); ++ //sleep(1); ++ dwc_mdelay(1000); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ ++ /* Read HAINT */ ++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); ++ ++ /* Read HCINT */ ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ ++ /* Clear HCINT */ ++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); ++ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ } ++ ++ /* Set HCTSIZ */ ++ hctsiz.d32 = 0; ++ hctsiz.b.xfersize = 0; ++ hctsiz.b.pktcnt = 1; ++ hctsiz.b.pid = DWC_OTG_HC_PID_DATA1; ++ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32); ++ ++ /* Set HCCHAR */ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL; ++ hcchar.b.epdir = 0; ++ hcchar.b.epnum = 0; ++ hcchar.b.mps = 8; ++ hcchar.b.chen = 1; ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); ++ ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ ++ /* Wait for host channel interrupt */ ++ do { ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++ } while (gintsts.b.hcintr == 0); ++ ++ /* Disable HCINTs */ ++ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000); ++ ++ /* Disable HAINTs */ ++ DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000); ++ ++ /* Read HAINT */ ++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); ++ ++ /* Read HCINT */ ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ ++ /* Clear HCINT */ ++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); ++} ++#endif ++ ++/** Handles hub class-specific requests. */ ++int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd, ++ uint16_t typeReq, ++ uint16_t wValue, ++ uint16_t wIndex, uint8_t * buf, uint16_t wLength) ++{ ++ int retval = 0; ++ ++ dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; ++ usb_hub_descriptor_t *hub_desc; ++ hprt0_data_t hprt0 = {.d32 = 0 }; ++ ++ uint32_t port_status; ++ ++ switch (typeReq) { ++ case UCR_CLEAR_HUB_FEATURE: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearHubFeature 0x%x\n", wValue); ++ switch (wValue) { ++ case UHF_C_HUB_LOCAL_POWER: ++ case UHF_C_HUB_OVER_CURRENT: ++ /* Nothing required here */ ++ break; ++ default: ++ retval = -DWC_E_INVALID; ++ DWC_ERROR("DWC OTG HCD - " ++ "ClearHubFeature request %xh unknown\n", ++ wValue); ++ } ++ break; ++ case UCR_CLEAR_PORT_FEATURE: ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ if (wValue != UHF_PORT_L1) ++#endif ++ if (!wIndex || wIndex > 1) ++ goto error; ++ ++ switch (wValue) { ++ case UHF_PORT_ENABLE: ++ DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtena = 1; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ break; ++ case UHF_PORT_SUSPEND: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); ++ ++ if (core_if->power_down == 2) { ++ dwc_otg_host_hibernation_restore(core_if, 0, 0); ++ } else { ++ DWC_WRITE_REG32(core_if->pcgcctl, 0); ++ dwc_mdelay(5); ++ ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtres = 1; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ hprt0.b.prtsusp = 0; ++ /* Clear Resume bit */ ++ dwc_mdelay(100); ++ hprt0.b.prtres = 0; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ } ++ break; ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ case UHF_PORT_L1: ++ { ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ glpmcfg_data_t lpmcfg = {.d32 = 0 }; ++ ++ lpmcfg.d32 = ++ DWC_READ_REG32(&core_if-> ++ core_global_regs->glpmcfg); ++ lpmcfg.b.en_utmi_sleep = 0; ++ lpmcfg.b.hird_thres &= (~(1 << 4)); ++ lpmcfg.b.prt_sleep_sts = 1; ++ DWC_WRITE_REG32(&core_if-> ++ core_global_regs->glpmcfg, ++ lpmcfg.d32); ++ ++ /* Clear Enbl_L1Gating bit. */ ++ pcgcctl.b.enbl_sleep_gating = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, ++ 0); ++ ++ dwc_mdelay(5); ++ ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtres = 1; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, ++ hprt0.d32); ++ /* This bit will be cleared in wakeup interrupt handle */ ++ break; ++ } ++#endif ++ case UHF_PORT_POWER: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_POWER\n"); ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtpwr = 0; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ break; ++ case UHF_PORT_INDICATOR: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); ++ /* Port inidicator not supported */ ++ break; ++ case UHF_C_PORT_CONNECTION: ++ /* Clears drivers internal connect status change ++ * flag */ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); ++ dwc_otg_hcd->flags.b.port_connect_status_change = 0; ++ break; ++ case UHF_C_PORT_RESET: ++ /* Clears the driver's internal Port Reset Change ++ * flag */ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); ++ dwc_otg_hcd->flags.b.port_reset_change = 0; ++ break; ++ case UHF_C_PORT_ENABLE: ++ /* Clears the driver's internal Port ++ * Enable/Disable Change flag */ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); ++ dwc_otg_hcd->flags.b.port_enable_change = 0; ++ break; ++ case UHF_C_PORT_SUSPEND: ++ /* Clears the driver's internal Port Suspend ++ * Change flag, which is set when resume signaling on ++ * the host port is complete */ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); ++ dwc_otg_hcd->flags.b.port_suspend_change = 0; ++ break; ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ case UHF_C_PORT_L1: ++ dwc_otg_hcd->flags.b.port_l1_change = 0; ++ break; ++#endif ++ case UHF_C_PORT_OVER_CURRENT: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); ++ dwc_otg_hcd->flags.b.port_over_current_change = 0; ++ break; ++ default: ++ retval = -DWC_E_INVALID; ++ DWC_ERROR("DWC OTG HCD - " ++ "ClearPortFeature request %xh " ++ "unknown or unsupported\n", wValue); ++ } ++ break; ++ case UCR_GET_HUB_DESCRIPTOR: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "GetHubDescriptor\n"); ++ hub_desc = (usb_hub_descriptor_t *) buf; ++ hub_desc->bDescLength = 9; ++ hub_desc->bDescriptorType = 0x29; ++ hub_desc->bNbrPorts = 1; ++ USETW(hub_desc->wHubCharacteristics, 0x08); ++ hub_desc->bPwrOn2PwrGood = 1; ++ hub_desc->bHubContrCurrent = 0; ++ hub_desc->DeviceRemovable[0] = 0; ++ hub_desc->DeviceRemovable[1] = 0xff; ++ break; ++ case UCR_GET_HUB_STATUS: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "GetHubStatus\n"); ++ DWC_MEMSET(buf, 0, 4); ++ break; ++ case UCR_GET_PORT_STATUS: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "GetPortStatus wIndex = 0x%04x FLAGS=0x%08x\n", ++ wIndex, dwc_otg_hcd->flags.d32); ++ if (!wIndex || wIndex > 1) ++ goto error; ++ ++ port_status = 0; ++ ++ if (dwc_otg_hcd->flags.b.port_connect_status_change) ++ port_status |= (1 << UHF_C_PORT_CONNECTION); ++ ++ if (dwc_otg_hcd->flags.b.port_enable_change) ++ port_status |= (1 << UHF_C_PORT_ENABLE); ++ ++ if (dwc_otg_hcd->flags.b.port_suspend_change) ++ port_status |= (1 << UHF_C_PORT_SUSPEND); ++ ++ if (dwc_otg_hcd->flags.b.port_l1_change) ++ port_status |= (1 << UHF_C_PORT_L1); ++ ++ if (dwc_otg_hcd->flags.b.port_reset_change) { ++ port_status |= (1 << UHF_C_PORT_RESET); ++ } ++ ++ if (dwc_otg_hcd->flags.b.port_over_current_change) { ++ DWC_WARN("Overcurrent change detected\n"); ++ port_status |= (1 << UHF_C_PORT_OVER_CURRENT); ++ } ++ ++ if (!dwc_otg_hcd->flags.b.port_connect_status) { ++ /* ++ * The port is disconnected, which means the core is ++ * either in device mode or it soon will be. Just ++ * return 0's for the remainder of the port status ++ * since the port register can't be read if the core ++ * is in device mode. ++ */ ++ *((__le32 *) buf) = dwc_cpu_to_le32(&port_status); ++ break; ++ } ++ ++ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0); ++ DWC_DEBUGPL(DBG_HCDV, " HPRT0: 0x%08x\n", hprt0.d32); ++ ++ if (hprt0.b.prtconnsts) ++ port_status |= (1 << UHF_PORT_CONNECTION); ++ ++ if (hprt0.b.prtena) ++ port_status |= (1 << UHF_PORT_ENABLE); ++ ++ if (hprt0.b.prtsusp) ++ port_status |= (1 << UHF_PORT_SUSPEND); ++ ++ if (hprt0.b.prtovrcurract) ++ port_status |= (1 << UHF_PORT_OVER_CURRENT); ++ ++ if (hprt0.b.prtrst) ++ port_status |= (1 << UHF_PORT_RESET); ++ ++ if (hprt0.b.prtpwr) ++ port_status |= (1 << UHF_PORT_POWER); ++ ++ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) ++ port_status |= (1 << UHF_PORT_HIGH_SPEED); ++ else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED) ++ port_status |= (1 << UHF_PORT_LOW_SPEED); ++ ++ if (hprt0.b.prttstctl) ++ port_status |= (1 << UHF_PORT_TEST); ++ if (dwc_otg_get_lpm_portsleepstatus(dwc_otg_hcd->core_if)) { ++ port_status |= (1 << UHF_PORT_L1); ++ } ++ /* ++ For Synopsys HW emulation of Power down wkup_control asserts the ++ hreset_n and prst_n on suspned. This causes the HPRT0 to be zero. ++ We intentionally tell the software that port is in L2Suspend state. ++ Only for STE. ++ */ ++ if ((core_if->power_down == 2) ++ && (core_if->hibernation_suspend == 1)) { ++ port_status |= (1 << UHF_PORT_SUSPEND); ++ } ++ /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ ++ ++ *((__le32 *) buf) = dwc_cpu_to_le32(&port_status); ++ ++ break; ++ case UCR_SET_HUB_FEATURE: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "SetHubFeature\n"); ++ /* No HUB features supported */ ++ break; ++ case UCR_SET_PORT_FEATURE: ++ if (wValue != UHF_PORT_TEST && (!wIndex || wIndex > 1)) ++ goto error; ++ ++ if (!dwc_otg_hcd->flags.b.port_connect_status) { ++ /* ++ * The port is disconnected, which means the core is ++ * either in device mode or it soon will be. Just ++ * return without doing anything since the port ++ * register can't be written if the core is in device ++ * mode. ++ */ ++ break; ++ } ++ ++ switch (wValue) { ++ case UHF_PORT_SUSPEND: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); ++ if (dwc_otg_hcd_otg_port(dwc_otg_hcd) != wIndex) { ++ goto error; ++ } ++ if (core_if->power_down == 2) { ++ int timeout = 300; ++ dwc_irqflags_t flags; ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ gusbcfg_data_t gusbcfg = {.d32 = 0 }; ++#ifdef DWC_DEV_SRPCAP ++ int32_t otg_cap_param = core_if->core_params->otg_cap; ++#endif ++ DWC_PRINTF("Preparing for complete power-off\n"); ++ ++ /* Save registers before hibernation */ ++ dwc_otg_save_global_regs(core_if); ++ dwc_otg_save_host_regs(core_if); ++ ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtsusp = 1; ++ hprt0.b.prtena = 0; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ /* Spin hprt0.b.prtsusp to became 1 */ ++ do { ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ if (hprt0.b.prtsusp) { ++ break; ++ } ++ dwc_mdelay(1); ++ } while (--timeout); ++ if (!timeout) { ++ DWC_WARN("Suspend wasn't genereted\n"); ++ } ++ dwc_udelay(10); ++ ++ /* ++ * We need to disable interrupts to prevent servicing of any IRQ ++ * during going to hibernation ++ */ ++ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags); ++ core_if->lx_state = DWC_OTG_L2; ++#ifdef DWC_DEV_SRPCAP ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtpwr = 0; ++ hprt0.b.prtena = 0; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, ++ hprt0.d32); ++#endif ++ gusbcfg.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs-> ++ gusbcfg); ++ if (gusbcfg.b.ulpi_utmi_sel == 1) { ++ /* ULPI interface */ ++ /* Suspend the Phy Clock */ ++ pcgcctl.d32 = 0; ++ pcgcctl.b.stoppclk = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, ++ pcgcctl.d32); ++ dwc_udelay(10); ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if-> ++ core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ } else { ++ /* UTMI+ Interface */ ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if-> ++ core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ pcgcctl.b.stoppclk = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32); ++ dwc_udelay(10); ++ } ++#ifdef DWC_DEV_SRPCAP ++ gpwrdn.d32 = 0; ++ gpwrdn.b.dis_vbus = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++#endif ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ gpwrdn.d32 = 0; ++#ifdef DWC_DEV_SRPCAP ++ gpwrdn.b.srp_det_msk = 1; ++#endif ++ gpwrdn.b.disconn_det_msk = 1; ++ gpwrdn.b.lnstchng_msk = 1; ++ gpwrdn.b.sts_chngint_msk = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Enable Power Down Clamp and all interrupts in GPWRDN */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnclmp = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Switch off VDD */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ ++#ifdef DWC_DEV_SRPCAP ++ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) ++ { ++ core_if->pwron_timer_started = 1; ++ DWC_TIMER_SCHEDULE(core_if->pwron_timer, 6000 /* 6 secs */ ); ++ } ++#endif ++ /* Save gpwrdn register for further usage if stschng interrupt */ ++ core_if->gr_backup->gpwrdn_local = ++ DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ ++ /* Set flag to indicate that we are in hibernation */ ++ core_if->hibernation_suspend = 1; ++ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,flags); ++ ++ DWC_PRINTF("Host hibernation completed\n"); ++ // Exit from case statement ++ break; ++ ++ } ++ if (dwc_otg_hcd_otg_port(dwc_otg_hcd) == wIndex && ++ dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) { ++ gotgctl_data_t gotgctl = {.d32 = 0 }; ++ gotgctl.b.hstsethnpen = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gotgctl, 0, gotgctl.d32); ++ core_if->op_state = A_SUSPEND; ++ } ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtsusp = 1; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ { ++ dwc_irqflags_t flags; ++ /* Update lx_state */ ++ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags); ++ core_if->lx_state = DWC_OTG_L2; ++ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags); ++ } ++ /* Suspend the Phy Clock */ ++ { ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ pcgcctl.b.stoppclk = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, ++ pcgcctl.d32); ++ dwc_udelay(10); ++ } ++ ++ /* For HNP the bus must be suspended for at least 200ms. */ ++ if (dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) { ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ pcgcctl.b.stoppclk = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0); ++ dwc_mdelay(200); ++ } ++ ++ /** @todo - check how sw can wait for 1 sec to check asesvld??? */ ++#if 0 //vahrama !!!!!!!!!!!!!!!!!! ++ if (core_if->adp_enable) { ++ gotgctl_data_t gotgctl = {.d32 = 0 }; ++ gpwrdn_data_t gpwrdn; ++ ++ while (gotgctl.b.asesvld == 1) { ++ gotgctl.d32 = ++ DWC_READ_REG32(&core_if-> ++ core_global_regs-> ++ gotgctl); ++ dwc_mdelay(100); ++ } ++ ++ /* Enable Power Down Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ ++ /* Unmask SRP detected interrupt from Power Down Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.srp_det_msk = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ ++ dwc_otg_adp_probe_start(core_if); ++ } ++#endif ++ break; ++ case UHF_PORT_POWER: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "SetPortFeature - USB_PORT_FEAT_POWER\n"); ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtpwr = 1; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ break; ++ case UHF_PORT_RESET: ++ if ((core_if->power_down == 2) ++ && (core_if->hibernation_suspend == 1)) { ++ /* If we are going to exit from Hibernated ++ * state via USB RESET. ++ */ ++ dwc_otg_host_hibernation_restore(core_if, 0, 1); ++ } else { ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ ++ DWC_DEBUGPL(DBG_HCD, ++ "DWC OTG HCD HUB CONTROL - " ++ "SetPortFeature - USB_PORT_FEAT_RESET\n"); ++ { ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ pcgcctl.b.enbl_sleep_gating = 1; ++ pcgcctl.b.stoppclk = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0); ++ DWC_WRITE_REG32(core_if->pcgcctl, 0); ++ } ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ { ++ glpmcfg_data_t lpmcfg; ++ lpmcfg.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++ if (lpmcfg.b.prt_sleep_sts) { ++ lpmcfg.b.en_utmi_sleep = 0; ++ lpmcfg.b.hird_thres &= (~(1 << 4)); ++ DWC_WRITE_REG32 ++ (&core_if->core_global_regs->glpmcfg, ++ lpmcfg.d32); ++ dwc_mdelay(1); ++ } ++ } ++#endif ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ /* Clear suspend bit if resetting from suspended state. */ ++ hprt0.b.prtsusp = 0; ++ /* When B-Host the Port reset bit is set in ++ * the Start HCD Callback function, so that ++ * the reset is started within 1ms of the HNP ++ * success interrupt. */ ++ if (!dwc_otg_hcd_is_b_host(dwc_otg_hcd)) { ++ hprt0.b.prtpwr = 1; ++ hprt0.b.prtrst = 1; ++ DWC_PRINTF("Indeed it is in host mode hprt0 = %08x\n",hprt0.d32); ++ DWC_WRITE_REG32(core_if->host_if->hprt0, ++ hprt0.d32); ++ } ++ /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ ++ dwc_mdelay(60); ++ hprt0.b.prtrst = 0; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ core_if->lx_state = DWC_OTG_L0; /* Now back to the on state */ ++ } ++ break; ++#ifdef DWC_HS_ELECT_TST ++ case UHF_PORT_TEST: ++ { ++ uint32_t t; ++ gintmsk_data_t gintmsk; ++ ++ t = (wIndex >> 8); /* MSB wIndex USB */ ++ DWC_DEBUGPL(DBG_HCD, ++ "DWC OTG HCD HUB CONTROL - " ++ "SetPortFeature - USB_PORT_FEAT_TEST %d\n", ++ t); ++ DWC_WARN("USB_PORT_FEAT_TEST %d\n", t); ++ if (t < 6) { ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prttstctl = t; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, ++ hprt0.d32); ++ } else { ++ /* Setup global vars with reg addresses (quick and ++ * dirty hack, should be cleaned up) ++ */ ++ global_regs = core_if->core_global_regs; ++ hc_global_regs = ++ core_if->host_if->host_global_regs; ++ hc_regs = ++ (dwc_otg_hc_regs_t *) ((char *) ++ global_regs + ++ 0x500); ++ data_fifo = ++ (uint32_t *) ((char *)global_regs + ++ 0x1000); ++ ++ if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */ ++ /* Save current interrupt mask */ ++ gintmsk.d32 = ++ DWC_READ_REG32 ++ (&global_regs->gintmsk); ++ ++ /* Disable all interrupts while we muck with ++ * the hardware directly ++ */ ++ DWC_WRITE_REG32(&global_regs->gintmsk, 0); ++ ++ /* 15 second delay per the test spec */ ++ dwc_mdelay(15000); ++ ++ /* Drive suspend on the root port */ ++ hprt0.d32 = ++ dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtsusp = 1; ++ hprt0.b.prtres = 0; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ ++ /* 15 second delay per the test spec */ ++ dwc_mdelay(15000); ++ ++ /* Drive resume on the root port */ ++ hprt0.d32 = ++ dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtsusp = 0; ++ hprt0.b.prtres = 1; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ dwc_mdelay(100); ++ ++ /* Clear the resume bit */ ++ hprt0.b.prtres = 0; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ ++ /* Restore interrupts */ ++ DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32); ++ } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */ ++ /* Save current interrupt mask */ ++ gintmsk.d32 = ++ DWC_READ_REG32 ++ (&global_regs->gintmsk); ++ ++ /* Disable all interrupts while we muck with ++ * the hardware directly ++ */ ++ DWC_WRITE_REG32(&global_regs->gintmsk, 0); ++ ++ /* 15 second delay per the test spec */ ++ dwc_mdelay(15000); ++ ++ /* Send the Setup packet */ ++ do_setup(); ++ ++ /* 15 second delay so nothing else happens for awhile */ ++ dwc_mdelay(15000); ++ ++ /* Restore interrupts */ ++ DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32); ++ } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */ ++ /* Save current interrupt mask */ ++ gintmsk.d32 = ++ DWC_READ_REG32 ++ (&global_regs->gintmsk); ++ ++ /* Disable all interrupts while we muck with ++ * the hardware directly ++ */ ++ DWC_WRITE_REG32(&global_regs->gintmsk, 0); ++ ++ /* Send the Setup packet */ ++ do_setup(); ++ ++ /* 15 second delay so nothing else happens for awhile */ ++ dwc_mdelay(15000); ++ ++ /* Send the In and Ack packets */ ++ do_in_ack(); ++ ++ /* 15 second delay so nothing else happens for awhile */ ++ dwc_mdelay(15000); ++ ++ /* Restore interrupts */ ++ DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32); ++ } ++ } ++ break; ++ } ++#endif /* DWC_HS_ELECT_TST */ ++ ++ case UHF_PORT_INDICATOR: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); ++ /* Not supported */ ++ break; ++ default: ++ retval = -DWC_E_INVALID; ++ DWC_ERROR("DWC OTG HCD - " ++ "SetPortFeature request %xh " ++ "unknown or unsupported\n", wValue); ++ break; ++ } ++ break; ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ case UCR_SET_AND_TEST_PORT_FEATURE: ++ if (wValue != UHF_PORT_L1) { ++ goto error; ++ } ++ { ++ int portnum, hird, devaddr, remwake; ++ glpmcfg_data_t lpmcfg; ++ uint32_t time_usecs; ++ gintsts_data_t gintsts; ++ gintmsk_data_t gintmsk; ++ ++ if (!dwc_otg_get_param_lpm_enable(core_if)) { ++ goto error; ++ } ++ if (wValue != UHF_PORT_L1 || wLength != 1) { ++ goto error; ++ } ++ /* Check if the port currently is in SLEEP state */ ++ lpmcfg.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++ if (lpmcfg.b.prt_sleep_sts) { ++ DWC_INFO("Port is already in sleep mode\n"); ++ buf[0] = 0; /* Return success */ ++ break; ++ } ++ ++ portnum = wIndex & 0xf; ++ hird = (wIndex >> 4) & 0xf; ++ devaddr = (wIndex >> 8) & 0x7f; ++ remwake = (wIndex >> 15); ++ ++ if (portnum != 1) { ++ retval = -DWC_E_INVALID; ++ DWC_WARN ++ ("Wrong port number(%d) in SetandTestPortFeature request\n", ++ portnum); ++ break; ++ } ++ ++ DWC_PRINTF ++ ("SetandTestPortFeature request: portnum = %d, hird = %d, devaddr = %d, rewake = %d\n", ++ portnum, hird, devaddr, remwake); ++ /* Disable LPM interrupt */ ++ gintmsk.d32 = 0; ++ gintmsk.b.lpmtranrcvd = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, ++ gintmsk.d32, 0); ++ ++ if (dwc_otg_hcd_send_lpm ++ (dwc_otg_hcd, devaddr, hird, remwake)) { ++ retval = -DWC_E_INVALID; ++ break; ++ } ++ ++ time_usecs = 10 * (lpmcfg.b.retry_count + 1); ++ /* We will consider timeout if time_usecs microseconds pass, ++ * and we don't receive LPM transaction status. ++ * After receiving non-error responce(ACK/NYET/STALL) from device, ++ * core will set lpmtranrcvd bit. ++ */ ++ do { ++ gintsts.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->gintsts); ++ if (gintsts.b.lpmtranrcvd) { ++ break; ++ } ++ dwc_udelay(1); ++ } while (--time_usecs); ++ /* lpm_int bit will be cleared in LPM interrupt handler */ ++ ++ /* Now fill status ++ * 0x00 - Success ++ * 0x10 - NYET ++ * 0x11 - Timeout ++ */ ++ if (!gintsts.b.lpmtranrcvd) { ++ buf[0] = 0x3; /* Completion code is Timeout */ ++ dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd); ++ } else { ++ lpmcfg.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++ if (lpmcfg.b.lpm_resp == 0x3) { ++ /* ACK responce from the device */ ++ buf[0] = 0x00; /* Success */ ++ } else if (lpmcfg.b.lpm_resp == 0x2) { ++ /* NYET responce from the device */ ++ buf[0] = 0x2; ++ } else { ++ /* Otherwise responce with Timeout */ ++ buf[0] = 0x3; ++ } ++ } ++ DWC_PRINTF("Device responce to LPM trans is %x\n", ++ lpmcfg.b.lpm_resp); ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, ++ gintmsk.d32); ++ ++ break; ++ } ++#endif /* CONFIG_USB_DWC_OTG_LPM */ ++ default: ++error: ++ retval = -DWC_E_INVALID; ++ DWC_WARN("DWC OTG HCD - " ++ "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n", ++ typeReq, wIndex, wValue); ++ break; ++ } ++ ++ return retval; ++} ++ ++#ifdef CONFIG_USB_DWC_OTG_LPM ++/** Returns index of host channel to perform LPM transaction. */ ++int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd, uint8_t devaddr) ++{ ++ dwc_otg_core_if_t *core_if = hcd->core_if; ++ dwc_hc_t *hc; ++ hcchar_data_t hcchar; ++ gintmsk_data_t gintmsk = {.d32 = 0 }; ++ ++ if (DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) { ++ DWC_PRINTF("No free channel to select for LPM transaction\n"); ++ return -1; ++ } ++ ++ hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list); ++ ++ /* Mask host channel interrupts. */ ++ gintmsk.b.hcintr = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0); ++ ++ /* Fill fields that core needs for LPM transaction */ ++ hcchar.b.devaddr = devaddr; ++ hcchar.b.epnum = 0; ++ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL; ++ hcchar.b.mps = 64; ++ hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW); ++ hcchar.b.epdir = 0; /* OUT */ ++ DWC_WRITE_REG32(&core_if->host_if->hc_regs[hc->hc_num]->hcchar, ++ hcchar.d32); ++ ++ /* Remove the host channel from the free list. */ ++ DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry); ++ ++ DWC_PRINTF("hcnum = %d devaddr = %d\n", hc->hc_num, devaddr); ++ ++ return hc->hc_num; ++} ++ ++/** Release hc after performing LPM transaction */ ++void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd) ++{ ++ dwc_hc_t *hc; ++ glpmcfg_data_t lpmcfg; ++ uint8_t hc_num; ++ ++ lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg); ++ hc_num = lpmcfg.b.lpm_chan_index; ++ ++ hc = hcd->hc_ptr_array[hc_num]; ++ ++ DWC_PRINTF("Freeing channel %d after LPM\n", hc_num); ++ /* Return host channel to free list */ ++ DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry); ++} ++ ++int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr, uint8_t hird, ++ uint8_t bRemoteWake) ++{ ++ glpmcfg_data_t lpmcfg; ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ int channel; ++ ++ channel = dwc_otg_hcd_get_hc_for_lpm_tran(hcd, devaddr); ++ if (channel < 0) { ++ return channel; ++ } ++ ++ pcgcctl.b.enbl_sleep_gating = 1; ++ DWC_MODIFY_REG32(hcd->core_if->pcgcctl, 0, pcgcctl.d32); ++ ++ /* Read LPM config register */ ++ lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg); ++ ++ /* Program LPM transaction fields */ ++ lpmcfg.b.rem_wkup_en = bRemoteWake; ++ lpmcfg.b.hird = hird; ++ lpmcfg.b.hird_thres = 0x1c; ++ lpmcfg.b.lpm_chan_index = channel; ++ lpmcfg.b.en_utmi_sleep = 1; ++ /* Program LPM config register */ ++ DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32); ++ ++ /* Send LPM transaction */ ++ lpmcfg.b.send_lpm = 1; ++ DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32); ++ ++ return 0; ++} ++ ++#endif /* CONFIG_USB_DWC_OTG_LPM */ ++ ++int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port) ++{ ++ int retval; ++ ++ if (port != 1) { ++ return -DWC_E_INVALID; ++ } ++ ++ retval = (hcd->flags.b.port_connect_status_change || ++ hcd->flags.b.port_reset_change || ++ hcd->flags.b.port_enable_change || ++ hcd->flags.b.port_suspend_change || ++ hcd->flags.b.port_over_current_change); ++#ifdef DEBUG ++ if (retval) { ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:" ++ " Root port status changed\n"); ++ DWC_DEBUGPL(DBG_HCDV, " port_connect_status_change: %d\n", ++ hcd->flags.b.port_connect_status_change); ++ DWC_DEBUGPL(DBG_HCDV, " port_reset_change: %d\n", ++ hcd->flags.b.port_reset_change); ++ DWC_DEBUGPL(DBG_HCDV, " port_enable_change: %d\n", ++ hcd->flags.b.port_enable_change); ++ DWC_DEBUGPL(DBG_HCDV, " port_suspend_change: %d\n", ++ hcd->flags.b.port_suspend_change); ++ DWC_DEBUGPL(DBG_HCDV, " port_over_current_change: %d\n", ++ hcd->flags.b.port_over_current_change); ++ } ++#endif ++ return retval; ++} ++ ++int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * dwc_otg_hcd) ++{ ++ hfnum_data_t hfnum; ++ hfnum.d32 = ++ DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->host_global_regs-> ++ hfnum); ++ ++#ifdef DEBUG_SOF ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n", ++ hfnum.b.frnum); ++#endif ++ return hfnum.b.frnum; ++} ++ ++int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd, ++ struct dwc_otg_hcd_function_ops *fops) ++{ ++ int retval = 0; ++ ++ hcd->fops = fops; ++ if (!dwc_otg_is_device_mode(hcd->core_if) && ++ (!hcd->core_if->adp_enable || hcd->core_if->adp.adp_started)) { ++ dwc_otg_hcd_reinit(hcd); ++ } else { ++ retval = -DWC_E_NO_DEVICE; ++ } ++ ++ return retval; ++} ++ ++void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd) ++{ ++ return hcd->priv; ++} ++ ++void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data) ++{ ++ hcd->priv = priv_data; ++} ++ ++uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd) ++{ ++ return hcd->otg_port; ++} ++ ++uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd) ++{ ++ uint32_t is_b_host; ++ if (hcd->core_if->op_state == B_HOST) { ++ is_b_host = 1; ++ } else { ++ is_b_host = 0; ++ } ++ ++ return is_b_host; ++} ++ ++dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd, ++ int iso_desc_count, int atomic_alloc) ++{ ++ dwc_otg_hcd_urb_t *dwc_otg_urb; ++ uint32_t size; ++ ++ size = ++ sizeof(*dwc_otg_urb) + ++ iso_desc_count * sizeof(struct dwc_otg_hcd_iso_packet_desc); ++ if (atomic_alloc) ++ dwc_otg_urb = DWC_ALLOC_ATOMIC(size); ++ else ++ dwc_otg_urb = DWC_ALLOC(size); ++ ++ if (dwc_otg_urb) ++ dwc_otg_urb->packet_count = iso_desc_count; ++ else { ++ DWC_ERROR("**** DWC OTG HCD URB alloc - " ++ "%salloc of %db failed\n", ++ atomic_alloc?"atomic ":"", size); ++ } ++ return dwc_otg_urb; ++} ++ ++void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * dwc_otg_urb, ++ uint8_t dev_addr, uint8_t ep_num, ++ uint8_t ep_type, uint8_t ep_dir, uint16_t mps) ++{ ++ dwc_otg_hcd_fill_pipe(&dwc_otg_urb->pipe_info, dev_addr, ep_num, ++ ep_type, ep_dir, mps); ++#if 0 ++ DWC_PRINTF ++ ("addr = %d, ep_num = %d, ep_dir = 0x%x, ep_type = 0x%x, mps = %d\n", ++ dev_addr, ep_num, ep_dir, ep_type, mps); ++#endif ++} ++ ++void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * dwc_otg_urb, ++ void *urb_handle, void *buf, dwc_dma_t dma, ++ uint32_t buflen, void *setup_packet, ++ dwc_dma_t setup_dma, uint32_t flags, ++ uint16_t interval) ++{ ++ dwc_otg_urb->priv = urb_handle; ++ dwc_otg_urb->buf = buf; ++ dwc_otg_urb->dma = dma; ++ dwc_otg_urb->length = buflen; ++ dwc_otg_urb->setup_packet = setup_packet; ++ dwc_otg_urb->setup_dma = setup_dma; ++ dwc_otg_urb->flags = flags; ++ dwc_otg_urb->interval = interval; ++ dwc_otg_urb->status = -DWC_E_IN_PROGRESS; ++} ++ ++uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb) ++{ ++ return dwc_otg_urb->status; ++} ++ ++uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t * dwc_otg_urb) ++{ ++ return dwc_otg_urb->actual_length; ++} ++ ++uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t * dwc_otg_urb) ++{ ++ return dwc_otg_urb->error_count; ++} ++ ++void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb, ++ int desc_num, uint32_t offset, ++ uint32_t length) ++{ ++ dwc_otg_urb->iso_descs[desc_num].offset = offset; ++ dwc_otg_urb->iso_descs[desc_num].length = length; ++} ++ ++uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t * dwc_otg_urb, ++ int desc_num) ++{ ++ return dwc_otg_urb->iso_descs[desc_num].status; ++} ++ ++uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t * ++ dwc_otg_urb, int desc_num) ++{ ++ return dwc_otg_urb->iso_descs[desc_num].actual_length; ++} ++ ++int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd, void *ep_handle) ++{ ++ int allocated = 0; ++ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle; ++ ++ if (qh) { ++ if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) { ++ allocated = 1; ++ } ++ } ++ return allocated; ++} ++ ++int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle) ++{ ++ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle; ++ int freed = 0; ++ DWC_ASSERT(qh, "qh is not allocated\n"); ++ ++ if (DWC_LIST_EMPTY(&qh->qh_list_entry)) { ++ freed = 1; ++ } ++ ++ return freed; ++} ++ ++uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd, void *ep_handle) ++{ ++ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle; ++ DWC_ASSERT(qh, "qh is not allocated\n"); ++ return qh->usecs; ++} ++ ++void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd) ++{ ++#ifdef DEBUG ++ int num_channels; ++ int i; ++ gnptxsts_data_t np_tx_status; ++ hptxsts_data_t p_tx_status; ++ ++ num_channels = hcd->core_if->core_params->host_channels; ++ DWC_PRINTF("\n"); ++ DWC_PRINTF ++ ("************************************************************\n"); ++ DWC_PRINTF("HCD State:\n"); ++ DWC_PRINTF(" Num channels: %d\n", num_channels); ++ for (i = 0; i < num_channels; i++) { ++ dwc_hc_t *hc = hcd->hc_ptr_array[i]; ++ DWC_PRINTF(" Channel %d:\n", i); ++ DWC_PRINTF(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n", ++ hc->dev_addr, hc->ep_num, hc->ep_is_in); ++ DWC_PRINTF(" speed: %d\n", hc->speed); ++ DWC_PRINTF(" ep_type: %d\n", hc->ep_type); ++ DWC_PRINTF(" max_packet: %d\n", hc->max_packet); ++ DWC_PRINTF(" data_pid_start: %d\n", hc->data_pid_start); ++ DWC_PRINTF(" multi_count: %d\n", hc->multi_count); ++ DWC_PRINTF(" xfer_started: %d\n", hc->xfer_started); ++ DWC_PRINTF(" xfer_buff: %p\n", hc->xfer_buff); ++ DWC_PRINTF(" xfer_len: %d\n", hc->xfer_len); ++ DWC_PRINTF(" xfer_count: %d\n", hc->xfer_count); ++ DWC_PRINTF(" halt_on_queue: %d\n", hc->halt_on_queue); ++ DWC_PRINTF(" halt_pending: %d\n", hc->halt_pending); ++ DWC_PRINTF(" halt_status: %d\n", hc->halt_status); ++ DWC_PRINTF(" do_split: %d\n", hc->do_split); ++ DWC_PRINTF(" complete_split: %d\n", hc->complete_split); ++ DWC_PRINTF(" hub_addr: %d\n", hc->hub_addr); ++ DWC_PRINTF(" port_addr: %d\n", hc->port_addr); ++ DWC_PRINTF(" xact_pos: %d\n", hc->xact_pos); ++ DWC_PRINTF(" requests: %d\n", hc->requests); ++ DWC_PRINTF(" qh: %p\n", hc->qh); ++ if (hc->xfer_started) { ++ hfnum_data_t hfnum; ++ hcchar_data_t hcchar; ++ hctsiz_data_t hctsiz; ++ hcint_data_t hcint; ++ hcintmsk_data_t hcintmsk; ++ hfnum.d32 = ++ DWC_READ_REG32(&hcd->core_if-> ++ host_if->host_global_regs->hfnum); ++ hcchar.d32 = ++ DWC_READ_REG32(&hcd->core_if->host_if-> ++ hc_regs[i]->hcchar); ++ hctsiz.d32 = ++ DWC_READ_REG32(&hcd->core_if->host_if-> ++ hc_regs[i]->hctsiz); ++ hcint.d32 = ++ DWC_READ_REG32(&hcd->core_if->host_if-> ++ hc_regs[i]->hcint); ++ hcintmsk.d32 = ++ DWC_READ_REG32(&hcd->core_if->host_if-> ++ hc_regs[i]->hcintmsk); ++ DWC_PRINTF(" hfnum: 0x%08x\n", hfnum.d32); ++ DWC_PRINTF(" hcchar: 0x%08x\n", hcchar.d32); ++ DWC_PRINTF(" hctsiz: 0x%08x\n", hctsiz.d32); ++ DWC_PRINTF(" hcint: 0x%08x\n", hcint.d32); ++ DWC_PRINTF(" hcintmsk: 0x%08x\n", hcintmsk.d32); ++ } ++ if (hc->xfer_started && hc->qh) { ++ dwc_otg_qtd_t *qtd; ++ dwc_otg_hcd_urb_t *urb; ++ ++ DWC_CIRCLEQ_FOREACH(qtd, &hc->qh->qtd_list, qtd_list_entry) { ++ if (!qtd->in_process) ++ break; ++ ++ urb = qtd->urb; ++ DWC_PRINTF(" URB Info:\n"); ++ DWC_PRINTF(" qtd: %p, urb: %p\n", qtd, urb); ++ if (urb) { ++ DWC_PRINTF(" Dev: %d, EP: %d %s\n", ++ dwc_otg_hcd_get_dev_addr(&urb-> ++ pipe_info), ++ dwc_otg_hcd_get_ep_num(&urb-> ++ pipe_info), ++ dwc_otg_hcd_is_pipe_in(&urb-> ++ pipe_info) ? ++ "IN" : "OUT"); ++ DWC_PRINTF(" Max packet size: %d\n", ++ dwc_otg_hcd_get_mps(&urb-> ++ pipe_info)); ++ DWC_PRINTF(" transfer_buffer: %p\n", ++ urb->buf); ++ DWC_PRINTF(" transfer_dma: %p\n", ++ (void *)urb->dma); ++ DWC_PRINTF(" transfer_buffer_length: %d\n", ++ urb->length); ++ DWC_PRINTF(" actual_length: %d\n", ++ urb->actual_length); ++ } ++ } ++ } ++ } ++ DWC_PRINTF(" non_periodic_channels: %d\n", hcd->non_periodic_channels); ++ DWC_PRINTF(" periodic_channels: %d\n", hcd->periodic_channels); ++ DWC_PRINTF(" periodic_usecs: %d\n", hcd->periodic_usecs); ++ np_tx_status.d32 = ++ DWC_READ_REG32(&hcd->core_if->core_global_regs->gnptxsts); ++ DWC_PRINTF(" NP Tx Req Queue Space Avail: %d\n", ++ np_tx_status.b.nptxqspcavail); ++ DWC_PRINTF(" NP Tx FIFO Space Avail: %d\n", ++ np_tx_status.b.nptxfspcavail); ++ p_tx_status.d32 = ++ DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hptxsts); ++ DWC_PRINTF(" P Tx Req Queue Space Avail: %d\n", ++ p_tx_status.b.ptxqspcavail); ++ DWC_PRINTF(" P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail); ++ dwc_otg_hcd_dump_frrem(hcd); ++ dwc_otg_dump_global_registers(hcd->core_if); ++ dwc_otg_dump_host_registers(hcd->core_if); ++ DWC_PRINTF ++ ("************************************************************\n"); ++ DWC_PRINTF("\n"); ++#endif ++} ++ ++#ifdef DEBUG ++void dwc_print_setup_data(uint8_t * setup) ++{ ++ int i; ++ if (CHK_DEBUG_LEVEL(DBG_HCD)) { ++ DWC_PRINTF("Setup Data = MSB "); ++ for (i = 7; i >= 0; i--) ++ DWC_PRINTF("%02x ", setup[i]); ++ DWC_PRINTF("\n"); ++ DWC_PRINTF(" bmRequestType Tranfer = %s\n", ++ (setup[0] & 0x80) ? "Device-to-Host" : ++ "Host-to-Device"); ++ DWC_PRINTF(" bmRequestType Type = "); ++ switch ((setup[0] & 0x60) >> 5) { ++ case 0: ++ DWC_PRINTF("Standard\n"); ++ break; ++ case 1: ++ DWC_PRINTF("Class\n"); ++ break; ++ case 2: ++ DWC_PRINTF("Vendor\n"); ++ break; ++ case 3: ++ DWC_PRINTF("Reserved\n"); ++ break; ++ } ++ DWC_PRINTF(" bmRequestType Recipient = "); ++ switch (setup[0] & 0x1f) { ++ case 0: ++ DWC_PRINTF("Device\n"); ++ break; ++ case 1: ++ DWC_PRINTF("Interface\n"); ++ break; ++ case 2: ++ DWC_PRINTF("Endpoint\n"); ++ break; ++ case 3: ++ DWC_PRINTF("Other\n"); ++ break; ++ default: ++ DWC_PRINTF("Reserved\n"); ++ break; ++ } ++ DWC_PRINTF(" bRequest = 0x%0x\n", setup[1]); ++ DWC_PRINTF(" wValue = 0x%0x\n", *((uint16_t *) & setup[2])); ++ DWC_PRINTF(" wIndex = 0x%0x\n", *((uint16_t *) & setup[4])); ++ DWC_PRINTF(" wLength = 0x%0x\n\n", *((uint16_t *) & setup[6])); ++ } ++} ++#endif ++ ++void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd) ++{ ++#if 0 ++ DWC_PRINTF("Frame remaining at SOF:\n"); ++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", ++ hcd->frrem_samples, hcd->frrem_accum, ++ (hcd->frrem_samples > 0) ? ++ hcd->frrem_accum / hcd->frrem_samples : 0); ++ ++ DWC_PRINTF("\n"); ++ DWC_PRINTF("Frame remaining at start_transfer (uframe 7):\n"); ++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", ++ hcd->core_if->hfnum_7_samples, ++ hcd->core_if->hfnum_7_frrem_accum, ++ (hcd->core_if->hfnum_7_samples > ++ 0) ? hcd->core_if->hfnum_7_frrem_accum / ++ hcd->core_if->hfnum_7_samples : 0); ++ DWC_PRINTF("Frame remaining at start_transfer (uframe 0):\n"); ++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", ++ hcd->core_if->hfnum_0_samples, ++ hcd->core_if->hfnum_0_frrem_accum, ++ (hcd->core_if->hfnum_0_samples > ++ 0) ? hcd->core_if->hfnum_0_frrem_accum / ++ hcd->core_if->hfnum_0_samples : 0); ++ DWC_PRINTF("Frame remaining at start_transfer (uframe 1-6):\n"); ++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", ++ hcd->core_if->hfnum_other_samples, ++ hcd->core_if->hfnum_other_frrem_accum, ++ (hcd->core_if->hfnum_other_samples > ++ 0) ? hcd->core_if->hfnum_other_frrem_accum / ++ hcd->core_if->hfnum_other_samples : 0); ++ ++ DWC_PRINTF("\n"); ++ DWC_PRINTF("Frame remaining at sample point A (uframe 7):\n"); ++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", ++ hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a, ++ (hcd->hfnum_7_samples_a > 0) ? ++ hcd->hfnum_7_frrem_accum_a / hcd->hfnum_7_samples_a : 0); ++ DWC_PRINTF("Frame remaining at sample point A (uframe 0):\n"); ++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", ++ hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a, ++ (hcd->hfnum_0_samples_a > 0) ? ++ hcd->hfnum_0_frrem_accum_a / hcd->hfnum_0_samples_a : 0); ++ DWC_PRINTF("Frame remaining at sample point A (uframe 1-6):\n"); ++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", ++ hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a, ++ (hcd->hfnum_other_samples_a > 0) ? ++ hcd->hfnum_other_frrem_accum_a / ++ hcd->hfnum_other_samples_a : 0); ++ ++ DWC_PRINTF("\n"); ++ DWC_PRINTF("Frame remaining at sample point B (uframe 7):\n"); ++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", ++ hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b, ++ (hcd->hfnum_7_samples_b > 0) ? ++ hcd->hfnum_7_frrem_accum_b / hcd->hfnum_7_samples_b : 0); ++ DWC_PRINTF("Frame remaining at sample point B (uframe 0):\n"); ++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", ++ hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b, ++ (hcd->hfnum_0_samples_b > 0) ? ++ hcd->hfnum_0_frrem_accum_b / hcd->hfnum_0_samples_b : 0); ++ DWC_PRINTF("Frame remaining at sample point B (uframe 1-6):\n"); ++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", ++ hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b, ++ (hcd->hfnum_other_samples_b > 0) ? ++ hcd->hfnum_other_frrem_accum_b / ++ hcd->hfnum_other_samples_b : 0); ++#endif ++} ++ ++#endif /* DWC_DEVICE_ONLY */ +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c 2015-11-29 09:42:39.919098694 +0100 +@@ -0,0 +1,1132 @@ ++/*========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_ddma.c $ ++ * $Revision: #10 $ ++ * $Date: 2011/10/20 $ ++ * $Change: 1869464 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_DEVICE_ONLY ++ ++/** @file ++ * This file contains Descriptor DMA support implementation for host mode. ++ */ ++ ++#include "dwc_otg_hcd.h" ++#include "dwc_otg_regs.h" ++ ++extern bool microframe_schedule; ++ ++static inline uint8_t frame_list_idx(uint16_t frame) ++{ ++ return (frame & (MAX_FRLIST_EN_NUM - 1)); ++} ++ ++static inline uint16_t desclist_idx_inc(uint16_t idx, uint16_t inc, uint8_t speed) ++{ ++ return (idx + inc) & ++ (((speed == ++ DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC : ++ MAX_DMA_DESC_NUM_GENERIC) - 1); ++} ++ ++static inline uint16_t desclist_idx_dec(uint16_t idx, uint16_t inc, uint8_t speed) ++{ ++ return (idx - inc) & ++ (((speed == ++ DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC : ++ MAX_DMA_DESC_NUM_GENERIC) - 1); ++} ++ ++static inline uint16_t max_desc_num(dwc_otg_qh_t * qh) ++{ ++ return (((qh->ep_type == UE_ISOCHRONOUS) ++ && (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH)) ++ ? MAX_DMA_DESC_NUM_HS_ISOC : MAX_DMA_DESC_NUM_GENERIC); ++} ++static inline uint16_t frame_incr_val(dwc_otg_qh_t * qh) ++{ ++ return ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) ++ ? ((qh->interval + 8 - 1) / 8) ++ : qh->interval); ++} ++ ++static int desc_list_alloc(dwc_otg_qh_t * qh) ++{ ++ int retval = 0; ++ ++ qh->desc_list = (dwc_otg_host_dma_desc_t *) ++ DWC_DMA_ALLOC(sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh), ++ &qh->desc_list_dma); ++ ++ if (!qh->desc_list) { ++ retval = -DWC_E_NO_MEMORY; ++ DWC_ERROR("%s: DMA descriptor list allocation failed\n", __func__); ++ ++ } ++ ++ dwc_memset(qh->desc_list, 0x00, ++ sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh)); ++ ++ qh->n_bytes = ++ (uint32_t *) DWC_ALLOC(sizeof(uint32_t) * max_desc_num(qh)); ++ ++ if (!qh->n_bytes) { ++ retval = -DWC_E_NO_MEMORY; ++ DWC_ERROR ++ ("%s: Failed to allocate array for descriptors' size actual values\n", ++ __func__); ++ ++ } ++ return retval; ++ ++} ++ ++static void desc_list_free(dwc_otg_qh_t * qh) ++{ ++ if (qh->desc_list) { ++ DWC_DMA_FREE(max_desc_num(qh), qh->desc_list, ++ qh->desc_list_dma); ++ qh->desc_list = NULL; ++ } ++ ++ if (qh->n_bytes) { ++ DWC_FREE(qh->n_bytes); ++ qh->n_bytes = NULL; ++ } ++} ++ ++static int frame_list_alloc(dwc_otg_hcd_t * hcd) ++{ ++ int retval = 0; ++ if (hcd->frame_list) ++ return 0; ++ ++ hcd->frame_list = DWC_DMA_ALLOC(4 * MAX_FRLIST_EN_NUM, ++ &hcd->frame_list_dma); ++ if (!hcd->frame_list) { ++ retval = -DWC_E_NO_MEMORY; ++ DWC_ERROR("%s: Frame List allocation failed\n", __func__); ++ } ++ ++ dwc_memset(hcd->frame_list, 0x00, 4 * MAX_FRLIST_EN_NUM); ++ ++ return retval; ++} ++ ++static void frame_list_free(dwc_otg_hcd_t * hcd) ++{ ++ if (!hcd->frame_list) ++ return; ++ ++ DWC_DMA_FREE(4 * MAX_FRLIST_EN_NUM, hcd->frame_list, hcd->frame_list_dma); ++ hcd->frame_list = NULL; ++} ++ ++static void per_sched_enable(dwc_otg_hcd_t * hcd, uint16_t fr_list_en) ++{ ++ ++ hcfg_data_t hcfg; ++ ++ hcfg.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hcfg); ++ ++ if (hcfg.b.perschedena) { ++ /* already enabled */ ++ return; ++ } ++ ++ DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hflbaddr, ++ hcd->frame_list_dma); ++ ++ switch (fr_list_en) { ++ case 64: ++ hcfg.b.frlisten = 3; ++ break; ++ case 32: ++ hcfg.b.frlisten = 2; ++ break; ++ case 16: ++ hcfg.b.frlisten = 1; ++ break; ++ case 8: ++ hcfg.b.frlisten = 0; ++ break; ++ default: ++ break; ++ } ++ ++ hcfg.b.perschedena = 1; ++ ++ DWC_DEBUGPL(DBG_HCD, "Enabling Periodic schedule\n"); ++ DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32); ++ ++} ++ ++static void per_sched_disable(dwc_otg_hcd_t * hcd) ++{ ++ hcfg_data_t hcfg; ++ ++ hcfg.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hcfg); ++ ++ if (!hcfg.b.perschedena) { ++ /* already disabled */ ++ return; ++ } ++ hcfg.b.perschedena = 0; ++ ++ DWC_DEBUGPL(DBG_HCD, "Disabling Periodic schedule\n"); ++ DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32); ++} ++ ++/* ++ * Activates/Deactivates FrameList entries for the channel ++ * based on endpoint servicing period. ++ */ ++void update_frame_list(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, uint8_t enable) ++{ ++ uint16_t i, j, inc; ++ dwc_hc_t *hc = NULL; ++ ++ if (!qh->channel) { ++ DWC_ERROR("qh->channel = %p", qh->channel); ++ return; ++ } ++ ++ if (!hcd) { ++ DWC_ERROR("------hcd = %p", hcd); ++ return; ++ } ++ ++ if (!hcd->frame_list) { ++ DWC_ERROR("-------hcd->frame_list = %p", hcd->frame_list); ++ return; ++ } ++ ++ hc = qh->channel; ++ inc = frame_incr_val(qh); ++ if (qh->ep_type == UE_ISOCHRONOUS) ++ i = frame_list_idx(qh->sched_frame); ++ else ++ i = 0; ++ ++ j = i; ++ do { ++ if (enable) ++ hcd->frame_list[j] |= (1 << hc->hc_num); ++ else ++ hcd->frame_list[j] &= ~(1 << hc->hc_num); ++ j = (j + inc) & (MAX_FRLIST_EN_NUM - 1); ++ } ++ while (j != i); ++ if (!enable) ++ return; ++ hc->schinfo = 0; ++ if (qh->channel->speed == DWC_OTG_EP_SPEED_HIGH) { ++ j = 1; ++ /* TODO - check this */ ++ inc = (8 + qh->interval - 1) / qh->interval; ++ for (i = 0; i < inc; i++) { ++ hc->schinfo |= j; ++ j = j << qh->interval; ++ } ++ } else { ++ hc->schinfo = 0xff; ++ } ++} ++ ++#if 1 ++void dump_frame_list(dwc_otg_hcd_t * hcd) ++{ ++ int i = 0; ++ DWC_PRINTF("--FRAME LIST (hex) --\n"); ++ for (i = 0; i < MAX_FRLIST_EN_NUM; i++) { ++ DWC_PRINTF("%x\t", hcd->frame_list[i]); ++ if (!(i % 8) && i) ++ DWC_PRINTF("\n"); ++ } ++ DWC_PRINTF("\n----\n"); ++ ++} ++#endif ++ ++static void release_channel_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ dwc_irqflags_t flags; ++ dwc_spinlock_t *channel_lock = hcd->channel_lock; ++ ++ dwc_hc_t *hc = qh->channel; ++ if (dwc_qh_is_non_per(qh)) { ++ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags); ++ if (!microframe_schedule) ++ hcd->non_periodic_channels--; ++ else ++ hcd->available_host_channels++; ++ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); ++ } else ++ update_frame_list(hcd, qh, 0); ++ ++ /* ++ * The condition is added to prevent double cleanup try in case of device ++ * disconnect. See channel cleanup in dwc_otg_hcd_disconnect_cb(). ++ */ ++ if (hc->qh) { ++ dwc_otg_hc_cleanup(hcd->core_if, hc); ++ DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry); ++ hc->qh = NULL; ++ } ++ ++ qh->channel = NULL; ++ qh->ntd = 0; ++ ++ if (qh->desc_list) { ++ dwc_memset(qh->desc_list, 0x00, ++ sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh)); ++ } ++} ++ ++/** ++ * Initializes a QH structure's Descriptor DMA related members. ++ * Allocates memory for descriptor list. ++ * On first periodic QH, allocates memory for FrameList ++ * and enables periodic scheduling. ++ * ++ * @param hcd The HCD state structure for the DWC OTG controller. ++ * @param qh The QH to init. ++ * ++ * @return 0 if successful, negative error code otherwise. ++ */ ++int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ int retval = 0; ++ ++ if (qh->do_split) { ++ DWC_ERROR("SPLIT Transfers are not supported in Descriptor DMA.\n"); ++ return -1; ++ } ++ ++ retval = desc_list_alloc(qh); ++ ++ if ((retval == 0) ++ && (qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT)) { ++ if (!hcd->frame_list) { ++ retval = frame_list_alloc(hcd); ++ /* Enable periodic schedule on first periodic QH */ ++ if (retval == 0) ++ per_sched_enable(hcd, MAX_FRLIST_EN_NUM); ++ } ++ } ++ ++ qh->ntd = 0; ++ ++ return retval; ++} ++ ++/** ++ * Frees descriptor list memory associated with the QH. ++ * If QH is periodic and the last, frees FrameList memory ++ * and disables periodic scheduling. ++ * ++ * @param hcd The HCD state structure for the DWC OTG controller. ++ * @param qh The QH to init. ++ */ ++void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ desc_list_free(qh); ++ ++ /* ++ * Channel still assigned due to some reasons. ++ * Seen on Isoc URB dequeue. Channel halted but no subsequent ++ * ChHalted interrupt to release the channel. Afterwards ++ * when it comes here from endpoint disable routine ++ * channel remains assigned. ++ */ ++ if (qh->channel) ++ release_channel_ddma(hcd, qh); ++ ++ if ((qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT) ++ && (microframe_schedule || !hcd->periodic_channels) && hcd->frame_list) { ++ ++ per_sched_disable(hcd); ++ frame_list_free(hcd); ++ } ++} ++ ++static uint8_t frame_to_desc_idx(dwc_otg_qh_t * qh, uint16_t frame_idx) ++{ ++ if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) { ++ /* ++ * Descriptor set(8 descriptors) index ++ * which is 8-aligned. ++ */ ++ return (frame_idx & ((MAX_DMA_DESC_NUM_HS_ISOC / 8) - 1)) * 8; ++ } else { ++ return (frame_idx & (MAX_DMA_DESC_NUM_GENERIC - 1)); ++ } ++} ++ ++/* ++ * Determine starting frame for Isochronous transfer. ++ * Few frames skipped to prevent race condition with HC. ++ */ ++static uint8_t calc_starting_frame(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, ++ uint8_t * skip_frames) ++{ ++ uint16_t frame = 0; ++ hcd->frame_number = dwc_otg_hcd_get_frame_number(hcd); ++ ++ /* sched_frame is always frame number(not uFrame) both in FS and HS !! */ ++ ++ /* ++ * skip_frames is used to limit activated descriptors number ++ * to avoid the situation when HC services the last activated ++ * descriptor firstly. ++ * Example for FS: ++ * Current frame is 1, scheduled frame is 3. Since HC always fetches the descriptor ++ * corresponding to curr_frame+1, the descriptor corresponding to frame 2 ++ * will be fetched. If the number of descriptors is max=64 (or greather) the ++ * list will be fully programmed with Active descriptors and it is possible ++ * case(rare) that the latest descriptor(considering rollback) corresponding ++ * to frame 2 will be serviced first. HS case is more probable because, in fact, ++ * up to 11 uframes(16 in the code) may be skipped. ++ */ ++ if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) { ++ /* ++ * Consider uframe counter also, to start xfer asap. ++ * If half of the frame elapsed skip 2 frames otherwise ++ * just 1 frame. ++ * Starting descriptor index must be 8-aligned, so ++ * if the current frame is near to complete the next one ++ * is skipped as well. ++ */ ++ ++ if (dwc_micro_frame_num(hcd->frame_number) >= 5) { ++ *skip_frames = 2 * 8; ++ frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames); ++ } else { ++ *skip_frames = 1 * 8; ++ frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames); ++ } ++ ++ frame = dwc_full_frame_num(frame); ++ } else { ++ /* ++ * Two frames are skipped for FS - the current and the next. ++ * But for descriptor programming, 1 frame(descriptor) is enough, ++ * see example above. ++ */ ++ *skip_frames = 1; ++ frame = dwc_frame_num_inc(hcd->frame_number, 2); ++ } ++ ++ return frame; ++} ++ ++/* ++ * Calculate initial descriptor index for isochronous transfer ++ * based on scheduled frame. ++ */ ++static uint8_t recalc_initial_desc_idx(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ uint16_t frame = 0, fr_idx, fr_idx_tmp; ++ uint8_t skip_frames = 0; ++ /* ++ * With current ISOC processing algorithm the channel is being ++ * released when no more QTDs in the list(qh->ntd == 0). ++ * Thus this function is called only when qh->ntd == 0 and qh->channel == 0. ++ * ++ * So qh->channel != NULL branch is not used and just not removed from the ++ * source file. It is required for another possible approach which is, ++ * do not disable and release the channel when ISOC session completed, ++ * just move QH to inactive schedule until new QTD arrives. ++ * On new QTD, the QH moved back to 'ready' schedule, ++ * starting frame and therefore starting desc_index are recalculated. ++ * In this case channel is released only on ep_disable. ++ */ ++ ++ /* Calculate starting descriptor index. For INTERRUPT endpoint it is always 0. */ ++ if (qh->channel) { ++ frame = calc_starting_frame(hcd, qh, &skip_frames); ++ /* ++ * Calculate initial descriptor index based on FrameList current bitmap ++ * and servicing period. ++ */ ++ fr_idx_tmp = frame_list_idx(frame); ++ fr_idx = ++ (MAX_FRLIST_EN_NUM + frame_list_idx(qh->sched_frame) - ++ fr_idx_tmp) ++ % frame_incr_val(qh); ++ fr_idx = (fr_idx + fr_idx_tmp) % MAX_FRLIST_EN_NUM; ++ } else { ++ qh->sched_frame = calc_starting_frame(hcd, qh, &skip_frames); ++ fr_idx = frame_list_idx(qh->sched_frame); ++ } ++ ++ qh->td_first = qh->td_last = frame_to_desc_idx(qh, fr_idx); ++ ++ return skip_frames; ++} ++ ++#define ISOC_URB_GIVEBACK_ASAP ++ ++#define MAX_ISOC_XFER_SIZE_FS 1023 ++#define MAX_ISOC_XFER_SIZE_HS 3072 ++#define DESCNUM_THRESHOLD 4 ++ ++static void init_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, ++ uint8_t skip_frames) ++{ ++ struct dwc_otg_hcd_iso_packet_desc *frame_desc; ++ dwc_otg_qtd_t *qtd; ++ dwc_otg_host_dma_desc_t *dma_desc; ++ uint16_t idx, inc, n_desc, ntd_max, max_xfer_size; ++ ++ idx = qh->td_last; ++ inc = qh->interval; ++ n_desc = 0; ++ ++ ntd_max = (max_desc_num(qh) + qh->interval - 1) / qh->interval; ++ if (skip_frames && !qh->channel) ++ ntd_max = ntd_max - skip_frames / qh->interval; ++ ++ max_xfer_size = ++ (qh->dev_speed == ++ DWC_OTG_EP_SPEED_HIGH) ? MAX_ISOC_XFER_SIZE_HS : ++ MAX_ISOC_XFER_SIZE_FS; ++ ++ DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) { ++ while ((qh->ntd < ntd_max) ++ && (qtd->isoc_frame_index_last < ++ qtd->urb->packet_count)) { ++ ++ dma_desc = &qh->desc_list[idx]; ++ dwc_memset(dma_desc, 0x00, sizeof(dwc_otg_host_dma_desc_t)); ++ ++ frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index_last]; ++ ++ if (frame_desc->length > max_xfer_size) ++ qh->n_bytes[idx] = max_xfer_size; ++ else ++ qh->n_bytes[idx] = frame_desc->length; ++ dma_desc->status.b_isoc.n_bytes = qh->n_bytes[idx]; ++ dma_desc->status.b_isoc.a = 1; ++ dma_desc->status.b_isoc.sts = 0; ++ ++ dma_desc->buf = qtd->urb->dma + frame_desc->offset; ++ ++ qh->ntd++; ++ ++ qtd->isoc_frame_index_last++; ++ ++#ifdef ISOC_URB_GIVEBACK_ASAP ++ /* ++ * Set IOC for each descriptor corresponding to the ++ * last frame of the URB. ++ */ ++ if (qtd->isoc_frame_index_last == ++ qtd->urb->packet_count) ++ dma_desc->status.b_isoc.ioc = 1; ++ ++#endif ++ idx = desclist_idx_inc(idx, inc, qh->dev_speed); ++ n_desc++; ++ ++ } ++ qtd->in_process = 1; ++ } ++ ++ qh->td_last = idx; ++ ++#ifdef ISOC_URB_GIVEBACK_ASAP ++ /* Set IOC for the last descriptor if descriptor list is full */ ++ if (qh->ntd == ntd_max) { ++ idx = desclist_idx_dec(qh->td_last, inc, qh->dev_speed); ++ qh->desc_list[idx].status.b_isoc.ioc = 1; ++ } ++#else ++ /* ++ * Set IOC bit only for one descriptor. ++ * Always try to be ahead of HW processing, ++ * i.e. on IOC generation driver activates next descriptors but ++ * core continues to process descriptors followed the one with IOC set. ++ */ ++ ++ if (n_desc > DESCNUM_THRESHOLD) { ++ /* ++ * Move IOC "up". Required even if there is only one QTD ++ * in the list, cause QTDs migth continue to be queued, ++ * but during the activation it was only one queued. ++ * Actually more than one QTD might be in the list if this function called ++ * from XferCompletion - QTDs was queued during HW processing of the previous ++ * descriptor chunk. ++ */ ++ idx = dwc_desclist_idx_dec(idx, inc * ((qh->ntd + 1) / 2), qh->dev_speed); ++ } else { ++ /* ++ * Set the IOC for the latest descriptor ++ * if either number of descriptor is not greather than threshold ++ * or no more new descriptors activated. ++ */ ++ idx = dwc_desclist_idx_dec(qh->td_last, inc, qh->dev_speed); ++ } ++ ++ qh->desc_list[idx].status.b_isoc.ioc = 1; ++#endif ++} ++ ++static void init_non_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ ++ dwc_hc_t *hc; ++ dwc_otg_host_dma_desc_t *dma_desc; ++ dwc_otg_qtd_t *qtd; ++ int num_packets, len, n_desc = 0; ++ ++ hc = qh->channel; ++ ++ /* ++ * Start with hc->xfer_buff initialized in ++ * assign_and_init_hc(), then if SG transfer consists of multiple URBs, ++ * this pointer re-assigned to the buffer of the currently processed QTD. ++ * For non-SG request there is always one QTD active. ++ */ ++ ++ DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) { ++ ++ if (n_desc) { ++ /* SG request - more than 1 QTDs */ ++ hc->xfer_buff = (uint8_t *)qtd->urb->dma + qtd->urb->actual_length; ++ hc->xfer_len = qtd->urb->length - qtd->urb->actual_length; ++ } ++ ++ qtd->n_desc = 0; ++ ++ do { ++ dma_desc = &qh->desc_list[n_desc]; ++ len = hc->xfer_len; ++ ++ if (len > MAX_DMA_DESC_SIZE) ++ len = MAX_DMA_DESC_SIZE - hc->max_packet + 1; ++ ++ if (hc->ep_is_in) { ++ if (len > 0) { ++ num_packets = (len + hc->max_packet - 1) / hc->max_packet; ++ } else { ++ /* Need 1 packet for transfer length of 0. */ ++ num_packets = 1; ++ } ++ /* Always program an integral # of max packets for IN transfers. */ ++ len = num_packets * hc->max_packet; ++ } ++ ++ dma_desc->status.b.n_bytes = len; ++ ++ qh->n_bytes[n_desc] = len; ++ ++ if ((qh->ep_type == UE_CONTROL) ++ && (qtd->control_phase == DWC_OTG_CONTROL_SETUP)) ++ dma_desc->status.b.sup = 1; /* Setup Packet */ ++ ++ dma_desc->status.b.a = 1; /* Active descriptor */ ++ dma_desc->status.b.sts = 0; ++ ++ dma_desc->buf = ++ ((unsigned long)hc->xfer_buff & 0xffffffff); ++ ++ /* ++ * Last descriptor(or single) of IN transfer ++ * with actual size less than MaxPacket. ++ */ ++ if (len > hc->xfer_len) { ++ hc->xfer_len = 0; ++ } else { ++ hc->xfer_buff += len; ++ hc->xfer_len -= len; ++ } ++ ++ qtd->n_desc++; ++ n_desc++; ++ } ++ while ((hc->xfer_len > 0) && (n_desc != MAX_DMA_DESC_NUM_GENERIC)); ++ ++ ++ qtd->in_process = 1; ++ ++ if (qh->ep_type == UE_CONTROL) ++ break; ++ ++ if (n_desc == MAX_DMA_DESC_NUM_GENERIC) ++ break; ++ } ++ ++ if (n_desc) { ++ /* Request Transfer Complete interrupt for the last descriptor */ ++ qh->desc_list[n_desc - 1].status.b.ioc = 1; ++ /* End of List indicator */ ++ qh->desc_list[n_desc - 1].status.b.eol = 1; ++ ++ hc->ntd = n_desc; ++ } ++} ++ ++/** ++ * For Control and Bulk endpoints initializes descriptor list ++ * and starts the transfer. ++ * ++ * For Interrupt and Isochronous endpoints initializes descriptor list ++ * then updates FrameList, marking appropriate entries as active. ++ * In case of Isochronous, the starting descriptor index is calculated based ++ * on the scheduled frame, but only on the first transfer descriptor within a session. ++ * Then starts the transfer via enabling the channel. ++ * For Isochronous endpoint the channel is not halted on XferComplete ++ * interrupt so remains assigned to the endpoint(QH) until session is done. ++ * ++ * @param hcd The HCD state structure for the DWC OTG controller. ++ * @param qh The QH to init. ++ * ++ * @return 0 if successful, negative error code otherwise. ++ */ ++void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ /* Channel is already assigned */ ++ dwc_hc_t *hc = qh->channel; ++ uint8_t skip_frames = 0; ++ ++ switch (hc->ep_type) { ++ case DWC_OTG_EP_TYPE_CONTROL: ++ case DWC_OTG_EP_TYPE_BULK: ++ init_non_isoc_dma_desc(hcd, qh); ++ ++ dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc); ++ break; ++ case DWC_OTG_EP_TYPE_INTR: ++ init_non_isoc_dma_desc(hcd, qh); ++ ++ update_frame_list(hcd, qh, 1); ++ ++ dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc); ++ break; ++ case DWC_OTG_EP_TYPE_ISOC: ++ ++ if (!qh->ntd) ++ skip_frames = recalc_initial_desc_idx(hcd, qh); ++ ++ init_isoc_dma_desc(hcd, qh, skip_frames); ++ ++ if (!hc->xfer_started) { ++ ++ update_frame_list(hcd, qh, 1); ++ ++ /* ++ * Always set to max, instead of actual size. ++ * Otherwise ntd will be changed with ++ * channel being enabled. Not recommended. ++ * ++ */ ++ hc->ntd = max_desc_num(qh); ++ /* Enable channel only once for ISOC */ ++ dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc); ++ } ++ ++ break; ++ default: ++ ++ break; ++ } ++} ++ ++static void complete_isoc_xfer_ddma(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_halt_status_e halt_status) ++{ ++ struct dwc_otg_hcd_iso_packet_desc *frame_desc; ++ dwc_otg_qtd_t *qtd, *qtd_tmp; ++ dwc_otg_qh_t *qh; ++ dwc_otg_host_dma_desc_t *dma_desc; ++ uint16_t idx, remain; ++ uint8_t urb_compl; ++ ++ qh = hc->qh; ++ idx = qh->td_first; ++ ++ if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) { ++ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) ++ qtd->in_process = 0; ++ return; ++ } else if ((halt_status == DWC_OTG_HC_XFER_AHB_ERR) || ++ (halt_status == DWC_OTG_HC_XFER_BABBLE_ERR)) { ++ /* ++ * Channel is halted in these error cases. ++ * Considered as serious issues. ++ * Complete all URBs marking all frames as failed, ++ * irrespective whether some of the descriptors(frames) succeeded or no. ++ * Pass error code to completion routine as well, to ++ * update urb->status, some of class drivers might use it to stop ++ * queing transfer requests. ++ */ ++ int err = (halt_status == DWC_OTG_HC_XFER_AHB_ERR) ++ ? (-DWC_E_IO) ++ : (-DWC_E_OVERFLOW); ++ ++ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) { ++ for (idx = 0; idx < qtd->urb->packet_count; idx++) { ++ frame_desc = &qtd->urb->iso_descs[idx]; ++ frame_desc->status = err; ++ } ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, err); ++ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh); ++ } ++ return; ++ } ++ ++ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) { ++ ++ if (!qtd->in_process) ++ break; ++ ++ urb_compl = 0; ++ ++ do { ++ ++ dma_desc = &qh->desc_list[idx]; ++ ++ frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; ++ remain = hc->ep_is_in ? dma_desc->status.b_isoc.n_bytes : 0; ++ ++ if (dma_desc->status.b_isoc.sts == DMA_DESC_STS_PKTERR) { ++ /* ++ * XactError or, unable to complete all the transactions ++ * in the scheduled micro-frame/frame, ++ * both indicated by DMA_DESC_STS_PKTERR. ++ */ ++ qtd->urb->error_count++; ++ frame_desc->actual_length = qh->n_bytes[idx] - remain; ++ frame_desc->status = -DWC_E_PROTOCOL; ++ } else { ++ /* Success */ ++ ++ frame_desc->actual_length = qh->n_bytes[idx] - remain; ++ frame_desc->status = 0; ++ } ++ ++ if (++qtd->isoc_frame_index == qtd->urb->packet_count) { ++ /* ++ * urb->status is not used for isoc transfers here. ++ * The individual frame_desc status are used instead. ++ */ ++ ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); ++ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh); ++ ++ /* ++ * This check is necessary because urb_dequeue can be called ++ * from urb complete callback(sound driver example). ++ * All pending URBs are dequeued there, so no need for ++ * further processing. ++ */ ++ if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) { ++ return; ++ } ++ ++ urb_compl = 1; ++ ++ } ++ ++ qh->ntd--; ++ ++ /* Stop if IOC requested descriptor reached */ ++ if (dma_desc->status.b_isoc.ioc) { ++ idx = desclist_idx_inc(idx, qh->interval, hc->speed); ++ goto stop_scan; ++ } ++ ++ idx = desclist_idx_inc(idx, qh->interval, hc->speed); ++ ++ if (urb_compl) ++ break; ++ } ++ while (idx != qh->td_first); ++ } ++stop_scan: ++ qh->td_first = idx; ++} ++ ++uint8_t update_non_isoc_urb_state_ddma(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_qtd_t * qtd, ++ dwc_otg_host_dma_desc_t * dma_desc, ++ dwc_otg_halt_status_e halt_status, ++ uint32_t n_bytes, uint8_t * xfer_done) ++{ ++ ++ uint16_t remain = hc->ep_is_in ? dma_desc->status.b.n_bytes : 0; ++ dwc_otg_hcd_urb_t *urb = qtd->urb; ++ ++ if (halt_status == DWC_OTG_HC_XFER_AHB_ERR) { ++ urb->status = -DWC_E_IO; ++ return 1; ++ } ++ if (dma_desc->status.b.sts == DMA_DESC_STS_PKTERR) { ++ switch (halt_status) { ++ case DWC_OTG_HC_XFER_STALL: ++ urb->status = -DWC_E_PIPE; ++ break; ++ case DWC_OTG_HC_XFER_BABBLE_ERR: ++ urb->status = -DWC_E_OVERFLOW; ++ break; ++ case DWC_OTG_HC_XFER_XACT_ERR: ++ urb->status = -DWC_E_PROTOCOL; ++ break; ++ default: ++ DWC_ERROR("%s: Unhandled descriptor error status (%d)\n", __func__, ++ halt_status); ++ break; ++ } ++ return 1; ++ } ++ ++ if (dma_desc->status.b.a == 1) { ++ DWC_DEBUGPL(DBG_HCDV, ++ "Active descriptor encountered on channel %d\n", ++ hc->hc_num); ++ return 0; ++ } ++ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL) { ++ if (qtd->control_phase == DWC_OTG_CONTROL_DATA) { ++ urb->actual_length += n_bytes - remain; ++ if (remain || urb->actual_length == urb->length) { ++ /* ++ * For Control Data stage do not set urb->status=0 to prevent ++ * URB callback. Set it when Status phase done. See below. ++ */ ++ *xfer_done = 1; ++ } ++ ++ } else if (qtd->control_phase == DWC_OTG_CONTROL_STATUS) { ++ urb->status = 0; ++ *xfer_done = 1; ++ } ++ /* No handling for SETUP stage */ ++ } else { ++ /* BULK and INTR */ ++ urb->actual_length += n_bytes - remain; ++ if (remain || urb->actual_length == urb->length) { ++ urb->status = 0; ++ *xfer_done = 1; ++ } ++ } ++ ++ return 0; ++} ++ ++static void complete_non_isoc_xfer_ddma(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_halt_status_e halt_status) ++{ ++ dwc_otg_hcd_urb_t *urb = NULL; ++ dwc_otg_qtd_t *qtd, *qtd_tmp; ++ dwc_otg_qh_t *qh; ++ dwc_otg_host_dma_desc_t *dma_desc; ++ uint32_t n_bytes, n_desc, i; ++ uint8_t failed = 0, xfer_done; ++ ++ n_desc = 0; ++ ++ qh = hc->qh; ++ ++ if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) { ++ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) { ++ qtd->in_process = 0; ++ } ++ return; ++ } ++ ++ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) { ++ ++ urb = qtd->urb; ++ ++ n_bytes = 0; ++ xfer_done = 0; ++ ++ for (i = 0; i < qtd->n_desc; i++) { ++ dma_desc = &qh->desc_list[n_desc]; ++ ++ n_bytes = qh->n_bytes[n_desc]; ++ ++ failed = ++ update_non_isoc_urb_state_ddma(hcd, hc, qtd, ++ dma_desc, ++ halt_status, n_bytes, ++ &xfer_done); ++ ++ if (failed ++ || (xfer_done ++ && (urb->status != -DWC_E_IN_PROGRESS))) { ++ ++ hcd->fops->complete(hcd, urb->priv, urb, ++ urb->status); ++ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh); ++ ++ if (failed) ++ goto stop_scan; ++ } else if (qh->ep_type == UE_CONTROL) { ++ if (qtd->control_phase == DWC_OTG_CONTROL_SETUP) { ++ if (urb->length > 0) { ++ qtd->control_phase = DWC_OTG_CONTROL_DATA; ++ } else { ++ qtd->control_phase = DWC_OTG_CONTROL_STATUS; ++ } ++ DWC_DEBUGPL(DBG_HCDV, " Control setup transaction done\n"); ++ } else if (qtd->control_phase == DWC_OTG_CONTROL_DATA) { ++ if (xfer_done) { ++ qtd->control_phase = DWC_OTG_CONTROL_STATUS; ++ DWC_DEBUGPL(DBG_HCDV, " Control data transfer done\n"); ++ } else if (i + 1 == qtd->n_desc) { ++ /* ++ * Last descriptor for Control data stage which is ++ * not completed yet. ++ */ ++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); ++ } ++ } ++ } ++ ++ n_desc++; ++ } ++ ++ } ++ ++stop_scan: ++ ++ if (qh->ep_type != UE_CONTROL) { ++ /* ++ * Resetting the data toggle for bulk ++ * and interrupt endpoints in case of stall. See handle_hc_stall_intr() ++ */ ++ if (halt_status == DWC_OTG_HC_XFER_STALL) ++ qh->data_toggle = DWC_OTG_HC_PID_DATA0; ++ else ++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); ++ } ++ ++ if (halt_status == DWC_OTG_HC_XFER_COMPLETE) { ++ hcint_data_t hcint; ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); ++ if (hcint.b.nyet) { ++ /* ++ * Got a NYET on the last transaction of the transfer. It ++ * means that the endpoint should be in the PING state at the ++ * beginning of the next transfer. ++ */ ++ qh->ping_state = 1; ++ clear_hc_int(hc_regs, nyet); ++ } ++ ++ } ++ ++} ++ ++/** ++ * This function is called from interrupt handlers. ++ * Scans the descriptor list, updates URB's status and ++ * calls completion routine for the URB if it's done. ++ * Releases the channel to be used by other transfers. ++ * In case of Isochronous endpoint the channel is not halted until ++ * the end of the session, i.e. QTD list is empty. ++ * If periodic channel released the FrameList is updated accordingly. ++ * ++ * Calls transaction selection routines to activate pending transfers. ++ * ++ * @param hcd The HCD state structure for the DWC OTG controller. ++ * @param hc Host channel, the transfer is completed on. ++ * @param hc_regs Host channel registers. ++ * @param halt_status Reason the channel is being halted, ++ * or just XferComplete for isochronous transfer ++ */ ++void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_halt_status_e halt_status) ++{ ++ uint8_t continue_isoc_xfer = 0; ++ dwc_otg_transaction_type_e tr_type; ++ dwc_otg_qh_t *qh = hc->qh; ++ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { ++ ++ complete_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status); ++ ++ /* Release the channel if halted or session completed */ ++ if (halt_status != DWC_OTG_HC_XFER_COMPLETE || ++ DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) { ++ ++ /* Halt the channel if session completed */ ++ if (halt_status == DWC_OTG_HC_XFER_COMPLETE) { ++ dwc_otg_hc_halt(hcd->core_if, hc, halt_status); ++ } ++ ++ release_channel_ddma(hcd, qh); ++ dwc_otg_hcd_qh_remove(hcd, qh); ++ } else { ++ /* Keep in assigned schedule to continue transfer */ ++ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned, ++ &qh->qh_list_entry); ++ continue_isoc_xfer = 1; ++ ++ } ++ /** @todo Consider the case when period exceeds FrameList size. ++ * Frame Rollover interrupt should be used. ++ */ ++ } else { ++ /* Scan descriptor list to complete the URB(s), then release the channel */ ++ complete_non_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status); ++ ++ release_channel_ddma(hcd, qh); ++ dwc_otg_hcd_qh_remove(hcd, qh); ++ ++ if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) { ++ /* Add back to inactive non-periodic schedule on normal completion */ ++ dwc_otg_hcd_qh_add(hcd, qh); ++ } ++ ++ } ++ tr_type = dwc_otg_hcd_select_transactions(hcd); ++ if (tr_type != DWC_OTG_TRANSACTION_NONE || continue_isoc_xfer) { ++ if (continue_isoc_xfer) { ++ if (tr_type == DWC_OTG_TRANSACTION_NONE) { ++ tr_type = DWC_OTG_TRANSACTION_PERIODIC; ++ } else if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC) { ++ tr_type = DWC_OTG_TRANSACTION_ALL; ++ } ++ } ++ dwc_otg_hcd_queue_transactions(hcd, tr_type); ++ } ++} ++ ++#endif /* DWC_DEVICE_ONLY */ +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd.h +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd.h 2015-11-29 09:42:39.919098694 +0100 +@@ -0,0 +1,862 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $ ++ * $Revision: #58 $ ++ * $Date: 2011/09/15 $ ++ * $Change: 1846647 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_DEVICE_ONLY ++#ifndef __DWC_HCD_H__ ++#define __DWC_HCD_H__ ++ ++#include "dwc_otg_os_dep.h" ++#include "usb.h" ++#include "dwc_otg_hcd_if.h" ++#include "dwc_otg_core_if.h" ++#include "dwc_list.h" ++#include "dwc_otg_cil.h" ++#include "dwc_otg_fiq_fsm.h" ++ ++ ++/** ++ * @file ++ * ++ * This file contains the structures, constants, and interfaces for ++ * the Host Contoller Driver (HCD). ++ * ++ * The Host Controller Driver (HCD) is responsible for translating requests ++ * from the USB Driver into the appropriate actions on the DWC_otg controller. ++ * It isolates the USBD from the specifics of the controller by providing an ++ * API to the USBD. ++ */ ++ ++struct dwc_otg_hcd_pipe_info { ++ uint8_t dev_addr; ++ uint8_t ep_num; ++ uint8_t pipe_type; ++ uint8_t pipe_dir; ++ uint16_t mps; ++}; ++ ++struct dwc_otg_hcd_iso_packet_desc { ++ uint32_t offset; ++ uint32_t length; ++ uint32_t actual_length; ++ uint32_t status; ++}; ++ ++struct dwc_otg_qtd; ++ ++struct dwc_otg_hcd_urb { ++ void *priv; ++ struct dwc_otg_qtd *qtd; ++ void *buf; ++ dwc_dma_t dma; ++ void *setup_packet; ++ dwc_dma_t setup_dma; ++ uint32_t length; ++ uint32_t actual_length; ++ uint32_t status; ++ uint32_t error_count; ++ uint32_t packet_count; ++ uint32_t flags; ++ uint16_t interval; ++ struct dwc_otg_hcd_pipe_info pipe_info; ++ struct dwc_otg_hcd_iso_packet_desc iso_descs[0]; ++}; ++ ++static inline uint8_t dwc_otg_hcd_get_ep_num(struct dwc_otg_hcd_pipe_info *pipe) ++{ ++ return pipe->ep_num; ++} ++ ++static inline uint8_t dwc_otg_hcd_get_pipe_type(struct dwc_otg_hcd_pipe_info ++ *pipe) ++{ ++ return pipe->pipe_type; ++} ++ ++static inline uint16_t dwc_otg_hcd_get_mps(struct dwc_otg_hcd_pipe_info *pipe) ++{ ++ return pipe->mps; ++} ++ ++static inline uint8_t dwc_otg_hcd_get_dev_addr(struct dwc_otg_hcd_pipe_info ++ *pipe) ++{ ++ return pipe->dev_addr; ++} ++ ++static inline uint8_t dwc_otg_hcd_is_pipe_isoc(struct dwc_otg_hcd_pipe_info ++ *pipe) ++{ ++ return (pipe->pipe_type == UE_ISOCHRONOUS); ++} ++ ++static inline uint8_t dwc_otg_hcd_is_pipe_int(struct dwc_otg_hcd_pipe_info ++ *pipe) ++{ ++ return (pipe->pipe_type == UE_INTERRUPT); ++} ++ ++static inline uint8_t dwc_otg_hcd_is_pipe_bulk(struct dwc_otg_hcd_pipe_info ++ *pipe) ++{ ++ return (pipe->pipe_type == UE_BULK); ++} ++ ++static inline uint8_t dwc_otg_hcd_is_pipe_control(struct dwc_otg_hcd_pipe_info ++ *pipe) ++{ ++ return (pipe->pipe_type == UE_CONTROL); ++} ++ ++static inline uint8_t dwc_otg_hcd_is_pipe_in(struct dwc_otg_hcd_pipe_info *pipe) ++{ ++ return (pipe->pipe_dir == UE_DIR_IN); ++} ++ ++static inline uint8_t dwc_otg_hcd_is_pipe_out(struct dwc_otg_hcd_pipe_info ++ *pipe) ++{ ++ return (!dwc_otg_hcd_is_pipe_in(pipe)); ++} ++ ++static inline void dwc_otg_hcd_fill_pipe(struct dwc_otg_hcd_pipe_info *pipe, ++ uint8_t devaddr, uint8_t ep_num, ++ uint8_t pipe_type, uint8_t pipe_dir, ++ uint16_t mps) ++{ ++ pipe->dev_addr = devaddr; ++ pipe->ep_num = ep_num; ++ pipe->pipe_type = pipe_type; ++ pipe->pipe_dir = pipe_dir; ++ pipe->mps = mps; ++} ++ ++/** ++ * Phases for control transfers. ++ */ ++typedef enum dwc_otg_control_phase { ++ DWC_OTG_CONTROL_SETUP, ++ DWC_OTG_CONTROL_DATA, ++ DWC_OTG_CONTROL_STATUS ++} dwc_otg_control_phase_e; ++ ++/** Transaction types. */ ++typedef enum dwc_otg_transaction_type { ++ DWC_OTG_TRANSACTION_NONE = 0, ++ DWC_OTG_TRANSACTION_PERIODIC = 1, ++ DWC_OTG_TRANSACTION_NON_PERIODIC = 2, ++ DWC_OTG_TRANSACTION_ALL = DWC_OTG_TRANSACTION_PERIODIC + DWC_OTG_TRANSACTION_NON_PERIODIC ++} dwc_otg_transaction_type_e; ++ ++struct dwc_otg_qh; ++ ++/** ++ * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, ++ * interrupt, or isochronous transfer. A single QTD is created for each URB ++ * (of one of these types) submitted to the HCD. The transfer associated with ++ * a QTD may require one or multiple transactions. ++ * ++ * A QTD is linked to a Queue Head, which is entered in either the ++ * non-periodic or periodic schedule for execution. When a QTD is chosen for ++ * execution, some or all of its transactions may be executed. After ++ * execution, the state of the QTD is updated. The QTD may be retired if all ++ * its transactions are complete or if an error occurred. Otherwise, it ++ * remains in the schedule so more transactions can be executed later. ++ */ ++typedef struct dwc_otg_qtd { ++ /** ++ * Determines the PID of the next data packet for the data phase of ++ * control transfers. Ignored for other transfer types.
++ * One of the following values: ++ * - DWC_OTG_HC_PID_DATA0 ++ * - DWC_OTG_HC_PID_DATA1 ++ */ ++ uint8_t data_toggle; ++ ++ /** Current phase for control transfers (Setup, Data, or Status). */ ++ dwc_otg_control_phase_e control_phase; ++ ++ /** Keep track of the current split type ++ * for FS/LS endpoints on a HS Hub */ ++ uint8_t complete_split; ++ ++ /** How many bytes transferred during SSPLIT OUT */ ++ uint32_t ssplit_out_xfer_count; ++ ++ /** ++ * Holds the number of bus errors that have occurred for a transaction ++ * within this transfer. ++ */ ++ uint8_t error_count; ++ ++ /** ++ * Index of the next frame descriptor for an isochronous transfer. A ++ * frame descriptor describes the buffer position and length of the ++ * data to be transferred in the next scheduled (micro)frame of an ++ * isochronous transfer. It also holds status for that transaction. ++ * The frame index starts at 0. ++ */ ++ uint16_t isoc_frame_index; ++ ++ /** Position of the ISOC split on full/low speed */ ++ uint8_t isoc_split_pos; ++ ++ /** Position of the ISOC split in the buffer for the current frame */ ++ uint16_t isoc_split_offset; ++ ++ /** URB for this transfer */ ++ struct dwc_otg_hcd_urb *urb; ++ ++ struct dwc_otg_qh *qh; ++ ++ /** This list of QTDs */ ++ DWC_CIRCLEQ_ENTRY(dwc_otg_qtd) qtd_list_entry; ++ ++ /** Indicates if this QTD is currently processed by HW. */ ++ uint8_t in_process; ++ ++ /** Number of DMA descriptors for this QTD */ ++ uint8_t n_desc; ++ ++ /** ++ * Last activated frame(packet) index. ++ * Used in Descriptor DMA mode only. ++ */ ++ uint16_t isoc_frame_index_last; ++ ++} dwc_otg_qtd_t; ++ ++DWC_CIRCLEQ_HEAD(dwc_otg_qtd_list, dwc_otg_qtd); ++ ++/** ++ * A Queue Head (QH) holds the static characteristics of an endpoint and ++ * maintains a list of transfers (QTDs) for that endpoint. A QH structure may ++ * be entered in either the non-periodic or periodic schedule. ++ */ ++typedef struct dwc_otg_qh { ++ /** ++ * Endpoint type. ++ * One of the following values: ++ * - UE_CONTROL ++ * - UE_BULK ++ * - UE_INTERRUPT ++ * - UE_ISOCHRONOUS ++ */ ++ uint8_t ep_type; ++ uint8_t ep_is_in; ++ ++ /** wMaxPacketSize Field of Endpoint Descriptor. */ ++ uint16_t maxp; ++ ++ /** ++ * Device speed. ++ * One of the following values: ++ * - DWC_OTG_EP_SPEED_LOW ++ * - DWC_OTG_EP_SPEED_FULL ++ * - DWC_OTG_EP_SPEED_HIGH ++ */ ++ uint8_t dev_speed; ++ ++ /** ++ * Determines the PID of the next data packet for non-control ++ * transfers. Ignored for control transfers.
++ * One of the following values: ++ * - DWC_OTG_HC_PID_DATA0 ++ * - DWC_OTG_HC_PID_DATA1 ++ */ ++ uint8_t data_toggle; ++ ++ /** Ping state if 1. */ ++ uint8_t ping_state; ++ ++ /** ++ * List of QTDs for this QH. ++ */ ++ struct dwc_otg_qtd_list qtd_list; ++ ++ /** Host channel currently processing transfers for this QH. */ ++ struct dwc_hc *channel; ++ ++ /** Full/low speed endpoint on high-speed hub requires split. */ ++ uint8_t do_split; ++ ++ /** @name Periodic schedule information */ ++ /** @{ */ ++ ++ /** Bandwidth in microseconds per (micro)frame. */ ++ uint16_t usecs; ++ ++ /** Interval between transfers in (micro)frames. */ ++ uint16_t interval; ++ ++ /** ++ * (micro)frame to initialize a periodic transfer. The transfer ++ * executes in the following (micro)frame. ++ */ ++ uint16_t sched_frame; ++ ++ /* ++ ** Frame a NAK was received on this queue head, used to minimise NAK retransmission ++ */ ++ uint16_t nak_frame; ++ ++ /** (micro)frame at which last start split was initialized. */ ++ uint16_t start_split_frame; ++ ++ /** @} */ ++ ++ /** ++ * Used instead of original buffer if ++ * it(physical address) is not dword-aligned. ++ */ ++ uint8_t *dw_align_buf; ++ dwc_dma_t dw_align_buf_dma; ++ ++ /** Entry for QH in either the periodic or non-periodic schedule. */ ++ dwc_list_link_t qh_list_entry; ++ ++ /** @name Descriptor DMA support */ ++ /** @{ */ ++ ++ /** Descriptor List. */ ++ dwc_otg_host_dma_desc_t *desc_list; ++ ++ /** Descriptor List physical address. */ ++ dwc_dma_t desc_list_dma; ++ ++ /** ++ * Xfer Bytes array. ++ * Each element corresponds to a descriptor and indicates ++ * original XferSize size value for the descriptor. ++ */ ++ uint32_t *n_bytes; ++ ++ /** Actual number of transfer descriptors in a list. */ ++ uint16_t ntd; ++ ++ /** First activated isochronous transfer descriptor index. */ ++ uint8_t td_first; ++ /** Last activated isochronous transfer descriptor index. */ ++ uint8_t td_last; ++ ++ /** @} */ ++ ++ ++ uint16_t speed; ++ uint16_t frame_usecs[8]; ++ ++ uint32_t skip_count; ++} dwc_otg_qh_t; ++ ++DWC_CIRCLEQ_HEAD(hc_list, dwc_hc); ++ ++typedef struct urb_tq_entry { ++ struct urb *urb; ++ DWC_TAILQ_ENTRY(urb_tq_entry) urb_tq_entries; ++} urb_tq_entry_t; ++ ++DWC_TAILQ_HEAD(urb_list, urb_tq_entry); ++ ++/** ++ * This structure holds the state of the HCD, including the non-periodic and ++ * periodic schedules. ++ */ ++struct dwc_otg_hcd { ++ /** The DWC otg device pointer */ ++ struct dwc_otg_device *otg_dev; ++ /** DWC OTG Core Interface Layer */ ++ dwc_otg_core_if_t *core_if; ++ ++ /** Function HCD driver callbacks */ ++ struct dwc_otg_hcd_function_ops *fops; ++ ++ /** Internal DWC HCD Flags */ ++ volatile union dwc_otg_hcd_internal_flags { ++ uint32_t d32; ++ struct { ++ unsigned port_connect_status_change:1; ++ unsigned port_connect_status:1; ++ unsigned port_reset_change:1; ++ unsigned port_enable_change:1; ++ unsigned port_suspend_change:1; ++ unsigned port_over_current_change:1; ++ unsigned port_l1_change:1; ++ unsigned reserved:26; ++ } b; ++ } flags; ++ ++ /** ++ * Inactive items in the non-periodic schedule. This is a list of ++ * Queue Heads. Transfers associated with these Queue Heads are not ++ * currently assigned to a host channel. ++ */ ++ dwc_list_link_t non_periodic_sched_inactive; ++ ++ /** ++ * Active items in the non-periodic schedule. This is a list of ++ * Queue Heads. Transfers associated with these Queue Heads are ++ * currently assigned to a host channel. ++ */ ++ dwc_list_link_t non_periodic_sched_active; ++ ++ /** ++ * Pointer to the next Queue Head to process in the active ++ * non-periodic schedule. ++ */ ++ dwc_list_link_t *non_periodic_qh_ptr; ++ ++ /** ++ * Inactive items in the periodic schedule. This is a list of QHs for ++ * periodic transfers that are _not_ scheduled for the next frame. ++ * Each QH in the list has an interval counter that determines when it ++ * needs to be scheduled for execution. This scheduling mechanism ++ * allows only a simple calculation for periodic bandwidth used (i.e. ++ * must assume that all periodic transfers may need to execute in the ++ * same frame). However, it greatly simplifies scheduling and should ++ * be sufficient for the vast majority of OTG hosts, which need to ++ * connect to a small number of peripherals at one time. ++ * ++ * Items move from this list to periodic_sched_ready when the QH ++ * interval counter is 0 at SOF. ++ */ ++ dwc_list_link_t periodic_sched_inactive; ++ ++ /** ++ * List of periodic QHs that are ready for execution in the next ++ * frame, but have not yet been assigned to host channels. ++ * ++ * Items move from this list to periodic_sched_assigned as host ++ * channels become available during the current frame. ++ */ ++ dwc_list_link_t periodic_sched_ready; ++ ++ /** ++ * List of periodic QHs to be executed in the next frame that are ++ * assigned to host channels. ++ * ++ * Items move from this list to periodic_sched_queued as the ++ * transactions for the QH are queued to the DWC_otg controller. ++ */ ++ dwc_list_link_t periodic_sched_assigned; ++ ++ /** ++ * List of periodic QHs that have been queued for execution. ++ * ++ * Items move from this list to either periodic_sched_inactive or ++ * periodic_sched_ready when the channel associated with the transfer ++ * is released. If the interval for the QH is 1, the item moves to ++ * periodic_sched_ready because it must be rescheduled for the next ++ * frame. Otherwise, the item moves to periodic_sched_inactive. ++ */ ++ dwc_list_link_t periodic_sched_queued; ++ ++ /** ++ * Total bandwidth claimed so far for periodic transfers. This value ++ * is in microseconds per (micro)frame. The assumption is that all ++ * periodic transfers may occur in the same (micro)frame. ++ */ ++ uint16_t periodic_usecs; ++ ++ /** ++ * Total bandwidth claimed so far for all periodic transfers ++ * in a frame. ++ * This will include a mixture of HS and FS transfers. ++ * Units are microseconds per (micro)frame. ++ * We have a budget per frame and have to schedule ++ * transactions accordingly. ++ * Watch out for the fact that things are actually scheduled for the ++ * "next frame". ++ */ ++ uint16_t frame_usecs[8]; ++ ++ ++ /** ++ * Frame number read from the core at SOF. The value ranges from 0 to ++ * DWC_HFNUM_MAX_FRNUM. ++ */ ++ uint16_t frame_number; ++ ++ /** ++ * Count of periodic QHs, if using several eps. For SOF enable/disable. ++ */ ++ uint16_t periodic_qh_count; ++ ++ /** ++ * Free host channels in the controller. This is a list of ++ * dwc_hc_t items. ++ */ ++ struct hc_list free_hc_list; ++ /** ++ * Number of host channels assigned to periodic transfers. Currently ++ * assuming that there is a dedicated host channel for each periodic ++ * transaction and at least one host channel available for ++ * non-periodic transactions. ++ */ ++ int periodic_channels; /* microframe_schedule==0 */ ++ ++ /** ++ * Number of host channels assigned to non-periodic transfers. ++ */ ++ int non_periodic_channels; /* microframe_schedule==0 */ ++ ++ /** ++ * Number of host channels assigned to non-periodic transfers. ++ */ ++ int available_host_channels; ++ ++ /** ++ * Array of pointers to the host channel descriptors. Allows accessing ++ * a host channel descriptor given the host channel number. This is ++ * useful in interrupt handlers. ++ */ ++ struct dwc_hc *hc_ptr_array[MAX_EPS_CHANNELS]; ++ ++ /** ++ * Buffer to use for any data received during the status phase of a ++ * control transfer. Normally no data is transferred during the status ++ * phase. This buffer is used as a bit bucket. ++ */ ++ uint8_t *status_buf; ++ ++ /** ++ * DMA address for status_buf. ++ */ ++ dma_addr_t status_buf_dma; ++#define DWC_OTG_HCD_STATUS_BUF_SIZE 64 ++ ++ /** ++ * Connection timer. An OTG host must display a message if the device ++ * does not connect. Started when the VBus power is turned on via ++ * sysfs attribute "buspower". ++ */ ++ dwc_timer_t *conn_timer; ++ ++ /* Tasket to do a reset */ ++ dwc_tasklet_t *reset_tasklet; ++ ++ dwc_tasklet_t *completion_tasklet; ++ struct urb_list completed_urb_list; ++ ++ /* */ ++ dwc_spinlock_t *lock; ++ dwc_spinlock_t *channel_lock; ++ /** ++ * Private data that could be used by OS wrapper. ++ */ ++ void *priv; ++ ++ uint8_t otg_port; ++ ++ /** Frame List */ ++ uint32_t *frame_list; ++ ++ /** Hub - Port assignment */ ++ int hub_port[128]; ++#ifdef FIQ_DEBUG ++ int hub_port_alloc[2048]; ++#endif ++ ++ /** Frame List DMA address */ ++ dma_addr_t frame_list_dma; ++ ++ struct fiq_stack *fiq_stack; ++ struct fiq_state *fiq_state; ++ ++ /** Virtual address for split transaction DMA bounce buffers */ ++ struct fiq_dma_blob *fiq_dmab; ++ ++#ifdef DEBUG ++ uint32_t frrem_samples; ++ uint64_t frrem_accum; ++ ++ uint32_t hfnum_7_samples_a; ++ uint64_t hfnum_7_frrem_accum_a; ++ uint32_t hfnum_0_samples_a; ++ uint64_t hfnum_0_frrem_accum_a; ++ uint32_t hfnum_other_samples_a; ++ uint64_t hfnum_other_frrem_accum_a; ++ ++ uint32_t hfnum_7_samples_b; ++ uint64_t hfnum_7_frrem_accum_b; ++ uint32_t hfnum_0_samples_b; ++ uint64_t hfnum_0_frrem_accum_b; ++ uint32_t hfnum_other_samples_b; ++ uint64_t hfnum_other_frrem_accum_b; ++#endif ++}; ++ ++/** @name Transaction Execution Functions */ ++/** @{ */ ++extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t ++ * hcd); ++extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd, ++ dwc_otg_transaction_type_e tr_type); ++ ++int dwc_otg_hcd_allocate_port(dwc_otg_hcd_t * hcd, dwc_otg_qh_t *qh); ++void dwc_otg_hcd_release_port(dwc_otg_hcd_t * dwc_otg_hcd, dwc_otg_qh_t *qh); ++ ++extern int fiq_fsm_queue_transaction(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh); ++extern int fiq_fsm_transaction_suitable(dwc_otg_qh_t *qh); ++extern void dwc_otg_cleanup_fiq_channel(dwc_otg_hcd_t *hcd, uint32_t num); ++ ++/** @} */ ++ ++/** @name Interrupt Handler Functions */ ++/** @{ */ ++extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t * ++ dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t * ++ dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t * ++ dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t * ++ dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr(dwc_otg_hcd_t * ++ dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_disconnect_intr(dwc_otg_hcd_t * dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, ++ uint32_t num); ++extern int32_t dwc_otg_hcd_handle_session_req_intr(dwc_otg_hcd_t * dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr(dwc_otg_hcd_t * ++ dwc_otg_hcd); ++/** @} */ ++ ++/** @name Schedule Queue Functions */ ++/** @{ */ ++ ++/* Implemented in dwc_otg_hcd_queue.c */ ++extern dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd, ++ dwc_otg_hcd_urb_t * urb, int atomic_alloc); ++extern void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); ++extern int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); ++extern void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); ++extern void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, ++ int sched_csplit); ++ ++/** Remove and free a QH */ ++static inline void dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd_t * hcd, ++ dwc_otg_qh_t * qh) ++{ ++ dwc_irqflags_t flags; ++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); ++ dwc_otg_hcd_qh_remove(hcd, qh); ++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); ++ dwc_otg_hcd_qh_free(hcd, qh); ++} ++ ++/** Allocates memory for a QH structure. ++ * @return Returns the memory allocate or NULL on error. */ ++static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(int atomic_alloc) ++{ ++ if (atomic_alloc) ++ return (dwc_otg_qh_t *) DWC_ALLOC_ATOMIC(sizeof(dwc_otg_qh_t)); ++ else ++ return (dwc_otg_qh_t *) DWC_ALLOC(sizeof(dwc_otg_qh_t)); ++} ++ ++extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb, ++ int atomic_alloc); ++extern void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb); ++extern int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, dwc_otg_hcd_t * dwc_otg_hcd, ++ dwc_otg_qh_t ** qh, int atomic_alloc); ++ ++/** Allocates memory for a QTD structure. ++ * @return Returns the memory allocate or NULL on error. */ ++static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(int atomic_alloc) ++{ ++ if (atomic_alloc) ++ return (dwc_otg_qtd_t *) DWC_ALLOC_ATOMIC(sizeof(dwc_otg_qtd_t)); ++ else ++ return (dwc_otg_qtd_t *) DWC_ALLOC(sizeof(dwc_otg_qtd_t)); ++} ++ ++/** Frees the memory for a QTD structure. QTD should already be removed from ++ * list. ++ * @param qtd QTD to free.*/ ++static inline void dwc_otg_hcd_qtd_free(dwc_otg_qtd_t * qtd) ++{ ++ DWC_FREE(qtd); ++} ++ ++/** Removes a QTD from list. ++ * @param hcd HCD instance. ++ * @param qtd QTD to remove from list. ++ * @param qh QTD belongs to. ++ */ ++static inline void dwc_otg_hcd_qtd_remove(dwc_otg_hcd_t * hcd, ++ dwc_otg_qtd_t * qtd, ++ dwc_otg_qh_t * qh) ++{ ++ DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry); ++} ++ ++/** Remove and free a QTD ++ * Need to disable IRQ and hold hcd lock while calling this function out of ++ * interrupt servicing chain */ ++static inline void dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd_t * hcd, ++ dwc_otg_qtd_t * qtd, ++ dwc_otg_qh_t * qh) ++{ ++ dwc_otg_hcd_qtd_remove(hcd, qtd, qh); ++ dwc_otg_hcd_qtd_free(qtd); ++} ++ ++/** @} */ ++ ++/** @name Descriptor DMA Supporting Functions */ ++/** @{ */ ++ ++extern void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); ++extern void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_halt_status_e halt_status); ++ ++extern int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); ++extern void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); ++ ++/** @} */ ++ ++/** @name Internal Functions */ ++/** @{ */ ++dwc_otg_qh_t *dwc_urb_to_qh(dwc_otg_hcd_urb_t * urb); ++/** @} */ ++ ++#ifdef CONFIG_USB_DWC_OTG_LPM ++extern int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd, ++ uint8_t devaddr); ++extern void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd); ++#endif ++ ++/** Gets the QH that contains the list_head */ ++#define dwc_list_to_qh(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry) ++ ++/** Gets the QTD that contains the list_head */ ++#define dwc_list_to_qtd(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry) ++ ++/** Check if QH is non-periodic */ ++#define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == UE_BULK) || \ ++ (_qh_ptr_->ep_type == UE_CONTROL)) ++ ++/** High bandwidth multiplier as encoded in highspeed endpoint descriptors */ ++#define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03)) ++ ++/** Packet size for any kind of endpoint descriptor */ ++#define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) ++ ++/** ++ * Returns true if _frame1 is less than or equal to _frame2. The comparison is ++ * done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the ++ * frame number when the max frame number is reached. ++ */ ++static inline int dwc_frame_num_le(uint16_t frame1, uint16_t frame2) ++{ ++ return ((frame2 - frame1) & DWC_HFNUM_MAX_FRNUM) <= ++ (DWC_HFNUM_MAX_FRNUM >> 1); ++} ++ ++/** ++ * Returns true if _frame1 is greater than _frame2. The comparison is done ++ * modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame ++ * number when the max frame number is reached. ++ */ ++static inline int dwc_frame_num_gt(uint16_t frame1, uint16_t frame2) ++{ ++ return (frame1 != frame2) && ++ (((frame1 - frame2) & DWC_HFNUM_MAX_FRNUM) < ++ (DWC_HFNUM_MAX_FRNUM >> 1)); ++} ++ ++/** ++ * Increments _frame by the amount specified by _inc. The addition is done ++ * modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value. ++ */ ++static inline uint16_t dwc_frame_num_inc(uint16_t frame, uint16_t inc) ++{ ++ return (frame + inc) & DWC_HFNUM_MAX_FRNUM; ++} ++ ++static inline uint16_t dwc_full_frame_num(uint16_t frame) ++{ ++ return (frame & DWC_HFNUM_MAX_FRNUM) >> 3; ++} ++ ++static inline uint16_t dwc_micro_frame_num(uint16_t frame) ++{ ++ return frame & 0x7; ++} ++ ++void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd); ++ ++#ifdef DEBUG ++/** ++ * Macro to sample the remaining PHY clocks left in the current frame. This ++ * may be used during debugging to determine the average time it takes to ++ * execute sections of code. There are two possible sample points, "a" and ++ * "b", so the _letter argument must be one of these values. ++ * ++ * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For ++ * example, "cat /sys/devices/lm0/hcd_frrem". ++ */ ++#define dwc_sample_frrem(_hcd, _qh, _letter) \ ++{ \ ++ hfnum_data_t hfnum; \ ++ dwc_otg_qtd_t *qtd; \ ++ qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \ ++ if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \ ++ hfnum.d32 = DWC_READ_REG32(&_hcd->core_if->host_if->host_global_regs->hfnum); \ ++ switch (hfnum.b.frnum & 0x7) { \ ++ case 7: \ ++ _hcd->hfnum_7_samples_##_letter++; \ ++ _hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \ ++ break; \ ++ case 0: \ ++ _hcd->hfnum_0_samples_##_letter++; \ ++ _hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \ ++ break; \ ++ default: \ ++ _hcd->hfnum_other_samples_##_letter++; \ ++ _hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \ ++ break; \ ++ } \ ++ } \ ++} ++#else ++#define dwc_sample_frrem(_hcd, _qh, _letter) ++#endif ++#endif ++#endif /* DWC_DEVICE_ONLY */ +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h 2015-11-29 09:42:39.919098694 +0100 +@@ -0,0 +1,417 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_if.h $ ++ * $Revision: #12 $ ++ * $Date: 2011/10/26 $ ++ * $Change: 1873028 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_DEVICE_ONLY ++#ifndef __DWC_HCD_IF_H__ ++#define __DWC_HCD_IF_H__ ++ ++#include "dwc_otg_core_if.h" ++ ++/** @file ++ * This file defines DWC_OTG HCD Core API. ++ */ ++ ++struct dwc_otg_hcd; ++typedef struct dwc_otg_hcd dwc_otg_hcd_t; ++ ++struct dwc_otg_hcd_urb; ++typedef struct dwc_otg_hcd_urb dwc_otg_hcd_urb_t; ++ ++/** @name HCD Function Driver Callbacks */ ++/** @{ */ ++ ++/** This function is called whenever core switches to host mode. */ ++typedef int (*dwc_otg_hcd_start_cb_t) (dwc_otg_hcd_t * hcd); ++ ++/** This function is called when device has been disconnected */ ++typedef int (*dwc_otg_hcd_disconnect_cb_t) (dwc_otg_hcd_t * hcd); ++ ++/** Wrapper provides this function to HCD to core, so it can get hub information to which device is connected */ ++typedef int (*dwc_otg_hcd_hub_info_from_urb_cb_t) (dwc_otg_hcd_t * hcd, ++ void *urb_handle, ++ uint32_t * hub_addr, ++ uint32_t * port_addr); ++/** Via this function HCD core gets device speed */ ++typedef int (*dwc_otg_hcd_speed_from_urb_cb_t) (dwc_otg_hcd_t * hcd, ++ void *urb_handle); ++ ++/** This function is called when urb is completed */ ++typedef int (*dwc_otg_hcd_complete_urb_cb_t) (dwc_otg_hcd_t * hcd, ++ void *urb_handle, ++ dwc_otg_hcd_urb_t * dwc_otg_urb, ++ int32_t status); ++ ++/** Via this function HCD core gets b_hnp_enable parameter */ ++typedef int (*dwc_otg_hcd_get_b_hnp_enable) (dwc_otg_hcd_t * hcd); ++ ++struct dwc_otg_hcd_function_ops { ++ dwc_otg_hcd_start_cb_t start; ++ dwc_otg_hcd_disconnect_cb_t disconnect; ++ dwc_otg_hcd_hub_info_from_urb_cb_t hub_info; ++ dwc_otg_hcd_speed_from_urb_cb_t speed; ++ dwc_otg_hcd_complete_urb_cb_t complete; ++ dwc_otg_hcd_get_b_hnp_enable get_b_hnp_enable; ++}; ++/** @} */ ++ ++/** @name HCD Core API */ ++/** @{ */ ++/** This function allocates dwc_otg_hcd structure and returns pointer on it. */ ++extern dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void); ++ ++/** This function should be called to initiate HCD Core. ++ * ++ * @param hcd The HCD ++ * @param core_if The DWC_OTG Core ++ * ++ * Returns -DWC_E_NO_MEMORY if no enough memory. ++ * Returns 0 on success ++ */ ++extern int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if); ++ ++/** Frees HCD ++ * ++ * @param hcd The HCD ++ */ ++extern void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd); ++ ++/** This function should be called on every hardware interrupt. ++ * ++ * @param dwc_otg_hcd The HCD ++ * ++ * Returns non zero if interrupt is handled ++ * Return 0 if interrupt is not handled ++ */ ++extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd); ++ ++/** This function is used to handle the fast interrupt ++ * ++ */ ++extern void __attribute__ ((naked)) dwc_otg_hcd_handle_fiq(void); ++ ++/** ++ * Returns private data set by ++ * dwc_otg_hcd_set_priv_data function. ++ * ++ * @param hcd The HCD ++ */ ++extern void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd); ++ ++/** ++ * Set private data. ++ * ++ * @param hcd The HCD ++ * @param priv_data pointer to be stored in private data ++ */ ++extern void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data); ++ ++/** ++ * This function initializes the HCD Core. ++ * ++ * @param hcd The HCD ++ * @param fops The Function Driver Operations data structure containing pointers to all callbacks. ++ * ++ * Returns -DWC_E_NO_DEVICE if Core is currently is in device mode. ++ * Returns 0 on success ++ */ ++extern int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd, ++ struct dwc_otg_hcd_function_ops *fops); ++ ++/** ++ * Halts the DWC_otg host mode operations in a clean manner. USB transfers are ++ * stopped. ++ * ++ * @param hcd The HCD ++ */ ++extern void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd); ++ ++/** ++ * Handles hub class-specific requests. ++ * ++ * @param dwc_otg_hcd The HCD ++ * @param typeReq Request Type ++ * @param wValue wValue from control request ++ * @param wIndex wIndex from control request ++ * @param buf data buffer ++ * @param wLength data buffer length ++ * ++ * Returns -DWC_E_INVALID if invalid argument is passed ++ * Returns 0 on success ++ */ ++extern int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd, ++ uint16_t typeReq, uint16_t wValue, ++ uint16_t wIndex, uint8_t * buf, ++ uint16_t wLength); ++ ++/** ++ * Returns otg port number. ++ * ++ * @param hcd The HCD ++ */ ++extern uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd); ++ ++/** ++ * Returns OTG version - either 1.3 or 2.0. ++ * ++ * @param core_if The core_if structure pointer ++ */ ++extern uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if); ++ ++/** ++ * Returns 1 if currently core is acting as B host, and 0 otherwise. ++ * ++ * @param hcd The HCD ++ */ ++extern uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd); ++ ++/** ++ * Returns current frame number. ++ * ++ * @param hcd The HCD ++ */ ++extern int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * hcd); ++ ++/** ++ * Dumps hcd state. ++ * ++ * @param hcd The HCD ++ */ ++extern void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd); ++ ++/** ++ * Dump the average frame remaining at SOF. This can be used to ++ * determine average interrupt latency. Frame remaining is also shown for ++ * start transfer and two additional sample points. ++ * Currently this function is not implemented. ++ * ++ * @param hcd The HCD ++ */ ++extern void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd); ++ ++/** ++ * Sends LPM transaction to the local device. ++ * ++ * @param hcd The HCD ++ * @param devaddr Device Address ++ * @param hird Host initiated resume duration ++ * @param bRemoteWake Value of bRemoteWake field in LPM transaction ++ * ++ * Returns negative value if sending LPM transaction was not succeeded. ++ * Returns 0 on success. ++ */ ++extern int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr, ++ uint8_t hird, uint8_t bRemoteWake); ++ ++/* URB interface */ ++ ++/** ++ * Allocates memory for dwc_otg_hcd_urb structure. ++ * Allocated memory should be freed by call of DWC_FREE. ++ * ++ * @param hcd The HCD ++ * @param iso_desc_count Count of ISOC descriptors ++ * @param atomic_alloc Specefies whether to perform atomic allocation. ++ */ ++extern dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd, ++ int iso_desc_count, ++ int atomic_alloc); ++ ++/** ++ * Set pipe information in URB. ++ * ++ * @param hcd_urb DWC_OTG URB ++ * @param devaddr Device Address ++ * @param ep_num Endpoint Number ++ * @param ep_type Endpoint Type ++ * @param ep_dir Endpoint Direction ++ * @param mps Max Packet Size ++ */ ++extern void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * hcd_urb, ++ uint8_t devaddr, uint8_t ep_num, ++ uint8_t ep_type, uint8_t ep_dir, ++ uint16_t mps); ++ ++/* Transfer flags */ ++#define URB_GIVEBACK_ASAP 0x1 ++#define URB_SEND_ZERO_PACKET 0x2 ++ ++/** ++ * Sets dwc_otg_hcd_urb parameters. ++ * ++ * @param urb DWC_OTG URB allocated by dwc_otg_hcd_urb_alloc function. ++ * @param urb_handle Unique handle for request, this will be passed back ++ * to function driver in completion callback. ++ * @param buf The buffer for the data ++ * @param dma The DMA buffer for the data ++ * @param buflen Transfer length ++ * @param sp Buffer for setup data ++ * @param sp_dma DMA address of setup data buffer ++ * @param flags Transfer flags ++ * @param interval Polling interval for interrupt or isochronous transfers. ++ */ ++extern void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * urb, ++ void *urb_handle, void *buf, ++ dwc_dma_t dma, uint32_t buflen, void *sp, ++ dwc_dma_t sp_dma, uint32_t flags, ++ uint16_t interval); ++ ++/** Gets status from dwc_otg_hcd_urb ++ * ++ * @param dwc_otg_urb DWC_OTG URB ++ */ ++extern uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb); ++ ++/** Gets actual length from dwc_otg_hcd_urb ++ * ++ * @param dwc_otg_urb DWC_OTG URB ++ */ ++extern uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t * ++ dwc_otg_urb); ++ ++/** Gets error count from dwc_otg_hcd_urb. Only for ISOC URBs ++ * ++ * @param dwc_otg_urb DWC_OTG URB ++ */ ++extern uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t * ++ dwc_otg_urb); ++ ++/** Set ISOC descriptor offset and length ++ * ++ * @param dwc_otg_urb DWC_OTG URB ++ * @param desc_num ISOC descriptor number ++ * @param offset Offset from beginig of buffer. ++ * @param length Transaction length ++ */ ++extern void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb, ++ int desc_num, uint32_t offset, ++ uint32_t length); ++ ++/** Get status of ISOC descriptor, specified by desc_num ++ * ++ * @param dwc_otg_urb DWC_OTG URB ++ * @param desc_num ISOC descriptor number ++ */ ++extern uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t * ++ dwc_otg_urb, int desc_num); ++ ++/** Get actual length of ISOC descriptor, specified by desc_num ++ * ++ * @param dwc_otg_urb DWC_OTG URB ++ * @param desc_num ISOC descriptor number ++ */ ++extern uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t * ++ dwc_otg_urb, ++ int desc_num); ++ ++/** Queue URB. After transfer is completes, the complete callback will be called with the URB status ++ * ++ * @param dwc_otg_hcd The HCD ++ * @param dwc_otg_urb DWC_OTG URB ++ * @param ep_handle Out parameter for returning endpoint handle ++ * @param atomic_alloc Flag to do atomic allocation if needed ++ * ++ * Returns -DWC_E_NO_DEVICE if no device is connected. ++ * Returns -DWC_E_NO_MEMORY if there is no enough memory. ++ * Returns 0 on success. ++ */ ++extern int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * dwc_otg_hcd, ++ dwc_otg_hcd_urb_t * dwc_otg_urb, ++ void **ep_handle, int atomic_alloc); ++ ++/** De-queue the specified URB ++ * ++ * @param dwc_otg_hcd The HCD ++ * @param dwc_otg_urb DWC_OTG URB ++ */ ++extern int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * dwc_otg_hcd, ++ dwc_otg_hcd_urb_t * dwc_otg_urb); ++ ++/** Frees resources in the DWC_otg controller related to a given endpoint. ++ * Any URBs for the endpoint must already be dequeued. ++ * ++ * @param hcd The HCD ++ * @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function ++ * @param retry Number of retries if there are queued transfers. ++ * ++ * Returns -DWC_E_INVALID if invalid arguments are passed. ++ * Returns 0 on success ++ */ ++extern int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle, ++ int retry); ++ ++/* Resets the data toggle in qh structure. This function can be called from ++ * usb_clear_halt routine. ++ * ++ * @param hcd The HCD ++ * @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function ++ * ++ * Returns -DWC_E_INVALID if invalid arguments are passed. ++ * Returns 0 on success ++ */ ++extern int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle); ++ ++/** Returns 1 if status of specified port is changed and 0 otherwise. ++ * ++ * @param hcd The HCD ++ * @param port Port number ++ */ ++extern int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port); ++ ++/** Call this function to check if bandwidth was allocated for specified endpoint. ++ * Only for ISOC and INTERRUPT endpoints. ++ * ++ * @param hcd The HCD ++ * @param ep_handle Endpoint handle ++ */ ++extern int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd, ++ void *ep_handle); ++ ++/** Call this function to check if bandwidth was freed for specified endpoint. ++ * ++ * @param hcd The HCD ++ * @param ep_handle Endpoint handle ++ */ ++extern int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle); ++ ++/** Returns bandwidth allocated for specified endpoint in microseconds. ++ * Only for ISOC and INTERRUPT endpoints. ++ * ++ * @param hcd The HCD ++ * @param ep_handle Endpoint handle ++ */ ++extern uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd, ++ void *ep_handle); ++ ++/** @} */ ++ ++#endif /* __DWC_HCD_IF_H__ */ ++#endif /* DWC_DEVICE_ONLY */ +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c 2015-11-29 09:42:39.919098694 +0100 +@@ -0,0 +1,2714 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $ ++ * $Revision: #89 $ ++ * $Date: 2011/10/20 $ ++ * $Change: 1869487 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_DEVICE_ONLY ++ ++#include "dwc_otg_hcd.h" ++#include "dwc_otg_regs.h" ++ ++#include ++#include ++ ++ ++extern bool microframe_schedule; ++ ++/** @file ++ * This file contains the implementation of the HCD Interrupt handlers. ++ */ ++ ++int fiq_done, int_done; ++ ++#ifdef FIQ_DEBUG ++char buffer[1000*16]; ++int wptr; ++void notrace _fiq_print(FIQDBG_T dbg_lvl, char *fmt, ...) ++{ ++ FIQDBG_T dbg_lvl_req = FIQDBG_PORTHUB; ++ va_list args; ++ char text[17]; ++ hfnum_data_t hfnum = { .d32 = FIQ_READ(dwc_regs_base + 0x408) }; ++ ++ if(dbg_lvl & dbg_lvl_req || dbg_lvl == FIQDBG_ERR) ++ { ++ local_fiq_disable(); ++ snprintf(text, 9, "%4d%d:%d ", hfnum.b.frnum/8, hfnum.b.frnum%8, 8 - hfnum.b.frrem/937); ++ va_start(args, fmt); ++ vsnprintf(text+8, 9, fmt, args); ++ va_end(args); ++ ++ memcpy(buffer + wptr, text, 16); ++ wptr = (wptr + 16) % sizeof(buffer); ++ local_fiq_enable(); ++ } ++} ++#endif ++ ++/** This function handles interrupts for the HCD. */ ++int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd) ++{ ++ int retval = 0; ++ static int last_time; ++ dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; ++ gintsts_data_t gintsts; ++ gintmsk_data_t gintmsk; ++ hfnum_data_t hfnum; ++ haintmsk_data_t haintmsk; ++ ++#ifdef DEBUG ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ ++#endif ++ ++ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts); ++ gintmsk.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk); ++ ++ /* Exit from ISR if core is hibernated */ ++ if (core_if->hibernation_suspend == 1) { ++ goto exit_handler_routine; ++ } ++ DWC_SPINLOCK(dwc_otg_hcd->lock); ++ /* Check if HOST Mode */ ++ if (dwc_otg_is_host_mode(core_if)) { ++ if (fiq_enable) { ++ local_fiq_disable(); ++ fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock); ++ /* Pull in from the FIQ's disabled mask */ ++ gintmsk.d32 = gintmsk.d32 | ~(dwc_otg_hcd->fiq_state->gintmsk_saved.d32); ++ dwc_otg_hcd->fiq_state->gintmsk_saved.d32 = ~0; ++ } ++ ++ if (fiq_fsm_enable && ( 0x0000FFFF & ~(dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint))) { ++ gintsts.b.hcintr = 1; ++ } ++ ++ /* Danger will robinson: fake a SOF if necessary */ ++ if (fiq_fsm_enable && (dwc_otg_hcd->fiq_state->gintmsk_saved.b.sofintr == 1)) { ++ gintsts.b.sofintr = 1; ++ } ++ gintsts.d32 &= gintmsk.d32; ++ ++ if (fiq_enable) { ++ fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock); ++ local_fiq_enable(); ++ } ++ ++ if (!gintsts.d32) { ++ goto exit_handler_routine; ++ } ++ ++#ifdef DEBUG ++ // We should be OK doing this because the common interrupts should already have been serviced ++ /* Don't print debug message in the interrupt handler on SOF */ ++#ifndef DEBUG_SOF ++ if (gintsts.d32 != DWC_SOF_INTR_MASK) ++#endif ++ DWC_DEBUGPL(DBG_HCDI, "\n"); ++#endif ++ ++#ifdef DEBUG ++#ifndef DEBUG_SOF ++ if (gintsts.d32 != DWC_SOF_INTR_MASK) ++#endif ++ DWC_DEBUGPL(DBG_HCDI, ++ "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x core_if=%p\n", ++ gintsts.d32, core_if); ++#endif ++ hfnum.d32 = DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->host_global_regs->hfnum); ++ if (gintsts.b.sofintr) { ++ retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd); ++ } ++ ++ if (gintsts.b.rxstsqlvl) { ++ retval |= ++ dwc_otg_hcd_handle_rx_status_q_level_intr ++ (dwc_otg_hcd); ++ } ++ if (gintsts.b.nptxfempty) { ++ retval |= ++ dwc_otg_hcd_handle_np_tx_fifo_empty_intr ++ (dwc_otg_hcd); ++ } ++ if (gintsts.b.i2cintr) { ++ /** @todo Implement i2cintr handler. */ ++ } ++ if (gintsts.b.portintr) { ++ ++ gintmsk_data_t gintmsk = { .b.portintr = 1}; ++ retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd); ++ if (fiq_enable) { ++ local_fiq_disable(); ++ fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock); ++ DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32); ++ fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock); ++ local_fiq_enable(); ++ } else { ++ DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32); ++ } ++ } ++ if (gintsts.b.hcintr) { ++ retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd); ++ } ++ if (gintsts.b.ptxfempty) { ++ retval |= ++ dwc_otg_hcd_handle_perio_tx_fifo_empty_intr ++ (dwc_otg_hcd); ++ } ++#ifdef DEBUG ++#ifndef DEBUG_SOF ++ if (gintsts.d32 != DWC_SOF_INTR_MASK) ++#endif ++ { ++ DWC_DEBUGPL(DBG_HCDI, ++ "DWC OTG HCD Finished Servicing Interrupts\n"); ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n", ++ DWC_READ_REG32(&global_regs->gintsts)); ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n", ++ DWC_READ_REG32(&global_regs->gintmsk)); ++ } ++#endif ++ ++#ifdef DEBUG ++#ifndef DEBUG_SOF ++ if (gintsts.d32 != DWC_SOF_INTR_MASK) ++#endif ++ DWC_DEBUGPL(DBG_HCDI, "\n"); ++#endif ++ ++ } ++ ++exit_handler_routine: ++ if (fiq_enable) { ++ gintmsk_data_t gintmsk_new; ++ haintmsk_data_t haintmsk_new; ++ local_fiq_disable(); ++ fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock); ++ gintmsk_new.d32 = *(volatile uint32_t *)&dwc_otg_hcd->fiq_state->gintmsk_saved.d32; ++ if(fiq_fsm_enable) ++ haintmsk_new.d32 = *(volatile uint32_t *)&dwc_otg_hcd->fiq_state->haintmsk_saved.d32; ++ else ++ haintmsk_new.d32 = 0x0000FFFF; ++ ++ /* The FIQ could have sneaked another interrupt in. If so, don't clear MPHI */ ++ if ((gintmsk_new.d32 == ~0) && (haintmsk_new.d32 == 0x0000FFFF)) { ++ DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.intstat, (1<<16)); ++ if (dwc_otg_hcd->fiq_state->mphi_int_count >= 50) { ++ fiq_print(FIQDBG_INT, dwc_otg_hcd->fiq_state, "MPHI CLR"); ++ DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl, ((1<<31) + (1<<16))); ++ while (!(DWC_READ_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl) & (1 << 17))) ++ ; ++ DWC_WRITE_REG32(dwc_otg_hcd->fiq_state->mphi_regs.ctrl, (1<<31)); ++ dwc_otg_hcd->fiq_state->mphi_int_count = 0; ++ } ++ int_done++; ++ } ++ haintmsk.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->haintmsk); ++ /* Re-enable interrupts that the FIQ masked (first time round) */ ++ FIQ_WRITE(dwc_otg_hcd->fiq_state->dwc_regs_base + GINTMSK, gintmsk.d32); ++ fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock); ++ local_fiq_enable(); ++ ++ if ((jiffies / HZ) > last_time) { ++ //dwc_otg_qh_t *qh; ++ //dwc_list_link_t *cur; ++ /* Once a second output the fiq and irq numbers, useful for debug */ ++ last_time = jiffies / HZ; ++ // DWC_WARN("np_kick=%d AHC=%d sched_frame=%d cur_frame=%d int_done=%d fiq_done=%d", ++ // dwc_otg_hcd->fiq_state->kick_np_queues, dwc_otg_hcd->available_host_channels, ++ // dwc_otg_hcd->fiq_state->next_sched_frame, hfnum.b.frnum, int_done, dwc_otg_hcd->fiq_state->fiq_done); ++ //printk(KERN_WARNING "Periodic queues:\n"); ++ } ++ } ++ ++ DWC_SPINUNLOCK(dwc_otg_hcd->lock); ++ return retval; ++} ++ ++#ifdef DWC_TRACK_MISSED_SOFS ++ ++#warning Compiling code to track missed SOFs ++#define FRAME_NUM_ARRAY_SIZE 1000 ++/** ++ * This function is for debug only. ++ */ ++static inline void track_missed_sofs(uint16_t curr_frame_number) ++{ ++ static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE]; ++ static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE]; ++ static int frame_num_idx = 0; ++ static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM; ++ static int dumped_frame_num_array = 0; ++ ++ if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) { ++ if (((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) != ++ curr_frame_number) { ++ frame_num_array[frame_num_idx] = curr_frame_number; ++ last_frame_num_array[frame_num_idx++] = last_frame_num; ++ } ++ } else if (!dumped_frame_num_array) { ++ int i; ++ DWC_PRINTF("Frame Last Frame\n"); ++ DWC_PRINTF("----- ----------\n"); ++ for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) { ++ DWC_PRINTF("0x%04x 0x%04x\n", ++ frame_num_array[i], last_frame_num_array[i]); ++ } ++ dumped_frame_num_array = 1; ++ } ++ last_frame_num = curr_frame_number; ++} ++#endif ++ ++/** ++ * Handles the start-of-frame interrupt in host mode. Non-periodic ++ * transactions may be queued to the DWC_otg controller for the current ++ * (micro)frame. Periodic transactions may be queued to the controller for the ++ * next (micro)frame. ++ */ ++int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * hcd) ++{ ++ hfnum_data_t hfnum; ++ gintsts_data_t gintsts = { .d32 = 0 }; ++ dwc_list_link_t *qh_entry; ++ dwc_otg_qh_t *qh; ++ dwc_otg_transaction_type_e tr_type; ++ int did_something = 0; ++ int32_t next_sched_frame = -1; ++ ++ hfnum.d32 = ++ DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum); ++ ++#ifdef DEBUG_SOF ++ DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n"); ++#endif ++ hcd->frame_number = hfnum.b.frnum; ++ ++#ifdef DEBUG ++ hcd->frrem_accum += hfnum.b.frrem; ++ hcd->frrem_samples++; ++#endif ++ ++#ifdef DWC_TRACK_MISSED_SOFS ++ track_missed_sofs(hcd->frame_number); ++#endif ++ /* Determine whether any periodic QHs should be executed. */ ++ qh_entry = DWC_LIST_FIRST(&hcd->periodic_sched_inactive); ++ while (qh_entry != &hcd->periodic_sched_inactive) { ++ qh = DWC_LIST_ENTRY(qh_entry, dwc_otg_qh_t, qh_list_entry); ++ qh_entry = qh_entry->next; ++ if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) { ++ ++ /* ++ * Move QH to the ready list to be executed next ++ * (micro)frame. ++ */ ++ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready, ++ &qh->qh_list_entry); ++ ++ did_something = 1; ++ } ++ else ++ { ++ if(next_sched_frame < 0 || dwc_frame_num_le(qh->sched_frame, next_sched_frame)) ++ { ++ next_sched_frame = qh->sched_frame; ++ } ++ } ++ } ++ if (fiq_enable) ++ hcd->fiq_state->next_sched_frame = next_sched_frame; ++ ++ tr_type = dwc_otg_hcd_select_transactions(hcd); ++ if (tr_type != DWC_OTG_TRANSACTION_NONE) { ++ dwc_otg_hcd_queue_transactions(hcd, tr_type); ++ did_something = 1; ++ } ++ ++ /* Clear interrupt - but do not trample on the FIQ sof */ ++ if (!fiq_fsm_enable) { ++ gintsts.b.sofintr = 1; ++ DWC_WRITE_REG32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32); ++ } ++ return 1; ++} ++ ++/** Handles the Rx Status Queue Level Interrupt, which indicates that there is at ++ * least one packet in the Rx FIFO. The packets are moved from the FIFO to ++ * memory if the DWC_otg controller is operating in Slave mode. */ ++int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t * dwc_otg_hcd) ++{ ++ host_grxsts_data_t grxsts; ++ dwc_hc_t *hc = NULL; ++ ++ DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n"); ++ ++ grxsts.d32 = ++ DWC_READ_REG32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp); ++ ++ hc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum]; ++ if (!hc) { ++ DWC_ERROR("Unable to get corresponding channel\n"); ++ return 0; ++ } ++ ++ /* Packet Status */ ++ DWC_DEBUGPL(DBG_HCDV, " Ch num = %d\n", grxsts.b.chnum); ++ DWC_DEBUGPL(DBG_HCDV, " Count = %d\n", grxsts.b.bcnt); ++ DWC_DEBUGPL(DBG_HCDV, " DPID = %d, hc.dpid = %d\n", grxsts.b.dpid, ++ hc->data_pid_start); ++ DWC_DEBUGPL(DBG_HCDV, " PStatus = %d\n", grxsts.b.pktsts); ++ ++ switch (grxsts.b.pktsts) { ++ case DWC_GRXSTS_PKTSTS_IN: ++ /* Read the data into the host buffer. */ ++ if (grxsts.b.bcnt > 0) { ++ dwc_otg_read_packet(dwc_otg_hcd->core_if, ++ hc->xfer_buff, grxsts.b.bcnt); ++ ++ /* Update the HC fields for the next packet received. */ ++ hc->xfer_count += grxsts.b.bcnt; ++ hc->xfer_buff += grxsts.b.bcnt; ++ } ++ ++ case DWC_GRXSTS_PKTSTS_IN_XFER_COMP: ++ case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR: ++ case DWC_GRXSTS_PKTSTS_CH_HALTED: ++ /* Handled in interrupt, just ignore data */ ++ break; ++ default: ++ DWC_ERROR("RX_STS_Q Interrupt: Unknown status %d\n", ++ grxsts.b.pktsts); ++ break; ++ } ++ ++ return 1; ++} ++ ++/** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More ++ * data packets may be written to the FIFO for OUT transfers. More requests ++ * may be written to the non-periodic request queue for IN transfers. This ++ * interrupt is enabled only in Slave mode. */ ++int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd) ++{ ++ DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n"); ++ dwc_otg_hcd_queue_transactions(dwc_otg_hcd, ++ DWC_OTG_TRANSACTION_NON_PERIODIC); ++ return 1; ++} ++ ++/** This interrupt occurs when the periodic Tx FIFO is half-empty. More data ++ * packets may be written to the FIFO for OUT transfers. More requests may be ++ * written to the periodic request queue for IN transfers. This interrupt is ++ * enabled only in Slave mode. */ ++int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd) ++{ ++ DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n"); ++ dwc_otg_hcd_queue_transactions(dwc_otg_hcd, ++ DWC_OTG_TRANSACTION_PERIODIC); ++ return 1; ++} ++ ++/** There are multiple conditions that can cause a port interrupt. This function ++ * determines which interrupt conditions have occurred and handles them ++ * appropriately. */ ++int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd) ++{ ++ int retval = 0; ++ hprt0_data_t hprt0; ++ hprt0_data_t hprt0_modify; ++ ++ hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0); ++ hprt0_modify.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0); ++ ++ /* Clear appropriate bits in HPRT0 to clear the interrupt bit in ++ * GINTSTS */ ++ ++ hprt0_modify.b.prtena = 0; ++ hprt0_modify.b.prtconndet = 0; ++ hprt0_modify.b.prtenchng = 0; ++ hprt0_modify.b.prtovrcurrchng = 0; ++ ++ /* Port Connect Detected ++ * Set flag and clear if detected */ ++ if (dwc_otg_hcd->core_if->hibernation_suspend == 1) { ++ // Dont modify port status if we are in hibernation state ++ hprt0_modify.b.prtconndet = 1; ++ hprt0_modify.b.prtenchng = 1; ++ DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32); ++ hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0); ++ return retval; ++ } ++ ++ if (hprt0.b.prtconndet) { ++ /** @todo - check if steps performed in 'else' block should be perfromed regardles adp */ ++ if (dwc_otg_hcd->core_if->adp_enable && ++ dwc_otg_hcd->core_if->adp.vbuson_timer_started == 1) { ++ DWC_PRINTF("PORT CONNECT DETECTED ----------------\n"); ++ DWC_TIMER_CANCEL(dwc_otg_hcd->core_if->adp.vbuson_timer); ++ dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0; ++ /* TODO - check if this is required, as ++ * host initialization was already performed ++ * after initial ADP probing ++ */ ++ /*dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0; ++ dwc_otg_core_init(dwc_otg_hcd->core_if); ++ dwc_otg_enable_global_interrupts(dwc_otg_hcd->core_if); ++ cil_hcd_start(dwc_otg_hcd->core_if);*/ ++ } else { ++ ++ DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x " ++ "Port Connect Detected--\n", hprt0.d32); ++ dwc_otg_hcd->flags.b.port_connect_status_change = 1; ++ dwc_otg_hcd->flags.b.port_connect_status = 1; ++ hprt0_modify.b.prtconndet = 1; ++ ++ /* B-Device has connected, Delete the connection timer. */ ++ DWC_TIMER_CANCEL(dwc_otg_hcd->conn_timer); ++ } ++ /* The Hub driver asserts a reset when it sees port connect ++ * status change flag */ ++ retval |= 1; ++ } ++ ++ /* Port Enable Changed ++ * Clear if detected - Set internal flag if disabled */ ++ if (hprt0.b.prtenchng) { ++ DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x " ++ "Port Enable Changed--\n", hprt0.d32); ++ hprt0_modify.b.prtenchng = 1; ++ if (hprt0.b.prtena == 1) { ++ hfir_data_t hfir; ++ int do_reset = 0; ++ dwc_otg_core_params_t *params = ++ dwc_otg_hcd->core_if->core_params; ++ dwc_otg_core_global_regs_t *global_regs = ++ dwc_otg_hcd->core_if->core_global_regs; ++ dwc_otg_host_if_t *host_if = ++ dwc_otg_hcd->core_if->host_if; ++ ++ /* Every time when port enables calculate ++ * HFIR.FrInterval ++ */ ++ hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir); ++ hfir.b.frint = calc_frame_interval(dwc_otg_hcd->core_if); ++ DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32); ++ ++ /* Check if we need to adjust the PHY clock speed for ++ * low power and adjust it */ ++ if (params->host_support_fs_ls_low_power) { ++ gusbcfg_data_t usbcfg; ++ ++ usbcfg.d32 = ++ DWC_READ_REG32(&global_regs->gusbcfg); ++ ++ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED ++ || hprt0.b.prtspd == ++ DWC_HPRT0_PRTSPD_FULL_SPEED) { ++ /* ++ * Low power ++ */ ++ hcfg_data_t hcfg; ++ if (usbcfg.b.phylpwrclksel == 0) { ++ /* Set PHY low power clock select for FS/LS devices */ ++ usbcfg.b.phylpwrclksel = 1; ++ DWC_WRITE_REG32 ++ (&global_regs->gusbcfg, ++ usbcfg.d32); ++ do_reset = 1; ++ } ++ ++ hcfg.d32 = ++ DWC_READ_REG32 ++ (&host_if->host_global_regs->hcfg); ++ ++ if (hprt0.b.prtspd == ++ DWC_HPRT0_PRTSPD_LOW_SPEED ++ && params->host_ls_low_power_phy_clk ++ == ++ DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ) ++ { ++ /* 6 MHZ */ ++ DWC_DEBUGPL(DBG_CIL, ++ "FS_PHY programming HCFG to 6 MHz (Low Power)\n"); ++ if (hcfg.b.fslspclksel != ++ DWC_HCFG_6_MHZ) { ++ hcfg.b.fslspclksel = ++ DWC_HCFG_6_MHZ; ++ DWC_WRITE_REG32 ++ (&host_if->host_global_regs->hcfg, ++ hcfg.d32); ++ do_reset = 1; ++ } ++ } else { ++ /* 48 MHZ */ ++ DWC_DEBUGPL(DBG_CIL, ++ "FS_PHY programming HCFG to 48 MHz ()\n"); ++ if (hcfg.b.fslspclksel != ++ DWC_HCFG_48_MHZ) { ++ hcfg.b.fslspclksel = ++ DWC_HCFG_48_MHZ; ++ DWC_WRITE_REG32 ++ (&host_if->host_global_regs->hcfg, ++ hcfg.d32); ++ do_reset = 1; ++ } ++ } ++ } else { ++ /* ++ * Not low power ++ */ ++ if (usbcfg.b.phylpwrclksel == 1) { ++ usbcfg.b.phylpwrclksel = 0; ++ DWC_WRITE_REG32 ++ (&global_regs->gusbcfg, ++ usbcfg.d32); ++ do_reset = 1; ++ } ++ } ++ ++ if (do_reset) { ++ DWC_TASK_SCHEDULE(dwc_otg_hcd->reset_tasklet); ++ } ++ } ++ ++ if (!do_reset) { ++ /* Port has been enabled set the reset change flag */ ++ dwc_otg_hcd->flags.b.port_reset_change = 1; ++ } ++ } else { ++ dwc_otg_hcd->flags.b.port_enable_change = 1; ++ } ++ retval |= 1; ++ } ++ ++ /** Overcurrent Change Interrupt */ ++ if (hprt0.b.prtovrcurrchng) { ++ DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x " ++ "Port Overcurrent Changed--\n", hprt0.d32); ++ dwc_otg_hcd->flags.b.port_over_current_change = 1; ++ hprt0_modify.b.prtovrcurrchng = 1; ++ retval |= 1; ++ } ++ ++ /* Clear Port Interrupts */ ++ DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32); ++ ++ return retval; ++} ++ ++/** This interrupt indicates that one or more host channels has a pending ++ * interrupt. There are multiple conditions that can cause each host channel ++ * interrupt. This function determines which conditions have occurred for each ++ * host channel interrupt and handles them appropriately. */ ++int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd) ++{ ++ int i; ++ int retval = 0; ++ haint_data_t haint = { .d32 = 0 } ; ++ ++ /* Clear appropriate bits in HCINTn to clear the interrupt bit in ++ * GINTSTS */ ++ ++ if (!fiq_fsm_enable) ++ haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if); ++ ++ // Overwrite with saved interrupts from fiq handler ++ if(fiq_fsm_enable) ++ { ++ /* check the mask? */ ++ local_fiq_disable(); ++ fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock); ++ haint.b2.chint |= ~(dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint); ++ dwc_otg_hcd->fiq_state->haintmsk_saved.b2.chint = ~0; ++ fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock); ++ local_fiq_enable(); ++ } ++ ++ for (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) { ++ if (haint.b2.chint & (1 << i)) { ++ retval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i); ++ } ++ } ++ ++ return retval; ++} ++ ++/** ++ * Gets the actual length of a transfer after the transfer halts. _halt_status ++ * holds the reason for the halt. ++ * ++ * For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE, ++ * *short_read is set to 1 upon return if less than the requested ++ * number of bytes were transferred. Otherwise, *short_read is set to 0 upon ++ * return. short_read may also be NULL on entry, in which case it remains ++ * unchanged. ++ */ ++static uint32_t get_actual_xfer_length(dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd, ++ dwc_otg_halt_status_e halt_status, ++ int *short_read) ++{ ++ hctsiz_data_t hctsiz; ++ uint32_t length; ++ ++ if (short_read != NULL) { ++ *short_read = 0; ++ } ++ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz); ++ ++ if (halt_status == DWC_OTG_HC_XFER_COMPLETE) { ++ if (hc->ep_is_in) { ++ length = hc->xfer_len - hctsiz.b.xfersize; ++ if (short_read != NULL) { ++ *short_read = (hctsiz.b.xfersize != 0); ++ } ++ } else if (hc->qh->do_split) { ++ //length = split_out_xfersize[hc->hc_num]; ++ length = qtd->ssplit_out_xfer_count; ++ } else { ++ length = hc->xfer_len; ++ } ++ } else { ++ /* ++ * Must use the hctsiz.pktcnt field to determine how much data ++ * has been transferred. This field reflects the number of ++ * packets that have been transferred via the USB. This is ++ * always an integral number of packets if the transfer was ++ * halted before its normal completion. (Can't use the ++ * hctsiz.xfersize field because that reflects the number of ++ * bytes transferred via the AHB, not the USB). ++ */ ++ length = ++ (hc->start_pkt_count - hctsiz.b.pktcnt) * hc->max_packet; ++ } ++ ++ return length; ++} ++ ++/** ++ * Updates the state of the URB after a Transfer Complete interrupt on the ++ * host channel. Updates the actual_length field of the URB based on the ++ * number of bytes transferred via the host channel. Sets the URB status ++ * if the data transfer is finished. ++ * ++ * @return 1 if the data transfer specified by the URB is completely finished, ++ * 0 otherwise. ++ */ ++static int update_urb_state_xfer_comp(dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_hcd_urb_t * urb, ++ dwc_otg_qtd_t * qtd) ++{ ++ int xfer_done = 0; ++ int short_read = 0; ++ ++ int xfer_length; ++ ++ xfer_length = get_actual_xfer_length(hc, hc_regs, qtd, ++ DWC_OTG_HC_XFER_COMPLETE, ++ &short_read); ++ ++ /* non DWORD-aligned buffer case handling. */ ++ if (hc->align_buff && xfer_length && hc->ep_is_in) { ++ dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf, ++ xfer_length); ++ } ++ ++ urb->actual_length += xfer_length; ++ ++ if (xfer_length && (hc->ep_type == DWC_OTG_EP_TYPE_BULK) && ++ (urb->flags & URB_SEND_ZERO_PACKET) ++ && (urb->actual_length == urb->length) ++ && !(urb->length % hc->max_packet)) { ++ xfer_done = 0; ++ } else if (short_read || urb->actual_length >= urb->length) { ++ xfer_done = 1; ++ urb->status = 0; ++ } ++ ++#ifdef DEBUG ++ { ++ hctsiz_data_t hctsiz; ++ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz); ++ DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n", ++ __func__, (hc->ep_is_in ? "IN" : "OUT"), ++ hc->hc_num); ++ DWC_DEBUGPL(DBG_HCDV, " hc->xfer_len %d\n", hc->xfer_len); ++ DWC_DEBUGPL(DBG_HCDV, " hctsiz.xfersize %d\n", ++ hctsiz.b.xfersize); ++ DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n", ++ urb->length); ++ DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n", ++ urb->actual_length); ++ DWC_DEBUGPL(DBG_HCDV, " short_read %d, xfer_done %d\n", ++ short_read, xfer_done); ++ } ++#endif ++ ++ return xfer_done; ++} ++ ++/* ++ * Save the starting data toggle for the next transfer. The data toggle is ++ * saved in the QH for non-control transfers and it's saved in the QTD for ++ * control transfers. ++ */ ++void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, dwc_otg_qtd_t * qtd) ++{ ++ hctsiz_data_t hctsiz; ++ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz); ++ ++ if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) { ++ dwc_otg_qh_t *qh = hc->qh; ++ if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) { ++ qh->data_toggle = DWC_OTG_HC_PID_DATA0; ++ } else { ++ qh->data_toggle = DWC_OTG_HC_PID_DATA1; ++ } ++ } else { ++ if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) { ++ qtd->data_toggle = DWC_OTG_HC_PID_DATA0; ++ } else { ++ qtd->data_toggle = DWC_OTG_HC_PID_DATA1; ++ } ++ } ++} ++ ++/** ++ * Updates the state of an Isochronous URB when the transfer is stopped for ++ * any reason. The fields of the current entry in the frame descriptor array ++ * are set based on the transfer state and the input _halt_status. Completes ++ * the Isochronous URB if all the URB frames have been completed. ++ * ++ * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be ++ * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE. ++ */ ++static dwc_otg_halt_status_e ++update_isoc_urb_state(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status) ++{ ++ dwc_otg_hcd_urb_t *urb = qtd->urb; ++ dwc_otg_halt_status_e ret_val = halt_status; ++ struct dwc_otg_hcd_iso_packet_desc *frame_desc; ++ ++ frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; ++ switch (halt_status) { ++ case DWC_OTG_HC_XFER_COMPLETE: ++ frame_desc->status = 0; ++ frame_desc->actual_length = ++ get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL); ++ ++ /* non DWORD-aligned buffer case handling. */ ++ if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) { ++ dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset, ++ hc->qh->dw_align_buf, frame_desc->actual_length); ++ } ++ ++ break; ++ case DWC_OTG_HC_XFER_FRAME_OVERRUN: ++ urb->error_count++; ++ if (hc->ep_is_in) { ++ frame_desc->status = -DWC_E_NO_STREAM_RES; ++ } else { ++ frame_desc->status = -DWC_E_COMMUNICATION; ++ } ++ frame_desc->actual_length = 0; ++ break; ++ case DWC_OTG_HC_XFER_BABBLE_ERR: ++ urb->error_count++; ++ frame_desc->status = -DWC_E_OVERFLOW; ++ /* Don't need to update actual_length in this case. */ ++ break; ++ case DWC_OTG_HC_XFER_XACT_ERR: ++ urb->error_count++; ++ frame_desc->status = -DWC_E_PROTOCOL; ++ frame_desc->actual_length = ++ get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL); ++ ++ /* non DWORD-aligned buffer case handling. */ ++ if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) { ++ dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset, ++ hc->qh->dw_align_buf, frame_desc->actual_length); ++ } ++ /* Skip whole frame */ ++ if (hc->qh->do_split && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && ++ hc->ep_is_in && hcd->core_if->dma_enable) { ++ qtd->complete_split = 0; ++ qtd->isoc_split_offset = 0; ++ } ++ ++ break; ++ default: ++ DWC_ASSERT(1, "Unhandled _halt_status (%d)\n", halt_status); ++ break; ++ } ++ if (++qtd->isoc_frame_index == urb->packet_count) { ++ /* ++ * urb->status is not used for isoc transfers. ++ * The individual frame_desc statuses are used instead. ++ */ ++ hcd->fops->complete(hcd, urb->priv, urb, 0); ++ ret_val = DWC_OTG_HC_XFER_URB_COMPLETE; ++ } else { ++ ret_val = DWC_OTG_HC_XFER_COMPLETE; ++ } ++ return ret_val; ++} ++ ++/** ++ * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic ++ * QHs, removes the QH from the active non-periodic schedule. If any QTDs are ++ * still linked to the QH, the QH is added to the end of the inactive ++ * non-periodic schedule. For periodic QHs, removes the QH from the periodic ++ * schedule if no more QTDs are linked to the QH. ++ */ ++static void deactivate_qh(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, int free_qtd) ++{ ++ int continue_split = 0; ++ dwc_otg_qtd_t *qtd; ++ ++ DWC_DEBUGPL(DBG_HCDV, " %s(%p,%p,%d)\n", __func__, hcd, qh, free_qtd); ++ ++ qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); ++ ++ if (qtd->complete_split) { ++ continue_split = 1; ++ } else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID || ++ qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END) { ++ continue_split = 1; ++ } ++ ++ if (free_qtd) { ++ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh); ++ continue_split = 0; ++ } ++ ++ qh->channel = NULL; ++ dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split); ++} ++ ++/** ++ * Releases a host channel for use by other transfers. Attempts to select and ++ * queue more transactions since at least one host channel is available. ++ * ++ * @param hcd The HCD state structure. ++ * @param hc The host channel to release. ++ * @param qtd The QTD associated with the host channel. This QTD may be freed ++ * if the transfer is complete or an error has occurred. ++ * @param halt_status Reason the channel is being released. This status ++ * determines the actions taken by this function. ++ */ ++static void release_channel(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_qtd_t * qtd, ++ dwc_otg_halt_status_e halt_status) ++{ ++ dwc_otg_transaction_type_e tr_type; ++ int free_qtd; ++ dwc_irqflags_t flags; ++ dwc_spinlock_t *channel_lock = hcd->channel_lock; ++ ++ int hog_port = 0; ++ ++ DWC_DEBUGPL(DBG_HCDV, " %s: channel %d, halt_status %d, xfer_len %d\n", ++ __func__, hc->hc_num, halt_status, hc->xfer_len); ++ ++ if(fiq_fsm_enable && hc->do_split) { ++ if(!hc->ep_is_in && hc->ep_type == UE_ISOCHRONOUS) { ++ if(hc->xact_pos == DWC_HCSPLIT_XACTPOS_MID || ++ hc->xact_pos == DWC_HCSPLIT_XACTPOS_BEGIN) { ++ hog_port = 0; ++ } ++ } ++ } ++ ++ switch (halt_status) { ++ case DWC_OTG_HC_XFER_URB_COMPLETE: ++ free_qtd = 1; ++ break; ++ case DWC_OTG_HC_XFER_AHB_ERR: ++ case DWC_OTG_HC_XFER_STALL: ++ case DWC_OTG_HC_XFER_BABBLE_ERR: ++ free_qtd = 1; ++ break; ++ case DWC_OTG_HC_XFER_XACT_ERR: ++ if (qtd->error_count >= 3) { ++ DWC_DEBUGPL(DBG_HCDV, ++ " Complete URB with transaction error\n"); ++ free_qtd = 1; ++ qtd->urb->status = -DWC_E_PROTOCOL; ++ hcd->fops->complete(hcd, qtd->urb->priv, ++ qtd->urb, -DWC_E_PROTOCOL); ++ } else { ++ free_qtd = 0; ++ } ++ break; ++ case DWC_OTG_HC_XFER_URB_DEQUEUE: ++ /* ++ * The QTD has already been removed and the QH has been ++ * deactivated. Don't want to do anything except release the ++ * host channel and try to queue more transfers. ++ */ ++ goto cleanup; ++ case DWC_OTG_HC_XFER_NO_HALT_STATUS: ++ free_qtd = 0; ++ break; ++ case DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE: ++ DWC_DEBUGPL(DBG_HCDV, ++ " Complete URB with I/O error\n"); ++ free_qtd = 1; ++ qtd->urb->status = -DWC_E_IO; ++ hcd->fops->complete(hcd, qtd->urb->priv, ++ qtd->urb, -DWC_E_IO); ++ break; ++ default: ++ free_qtd = 0; ++ break; ++ } ++ ++ deactivate_qh(hcd, hc->qh, free_qtd); ++ ++cleanup: ++ /* ++ * Release the host channel for use by other transfers. The cleanup ++ * function clears the channel interrupt enables and conditions, so ++ * there's no need to clear the Channel Halted interrupt separately. ++ */ ++ if (fiq_fsm_enable && hcd->fiq_state->channel[hc->hc_num].fsm != FIQ_PASSTHROUGH) ++ dwc_otg_cleanup_fiq_channel(hcd, hc->hc_num); ++ dwc_otg_hc_cleanup(hcd->core_if, hc); ++ DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry); ++ ++ if (!microframe_schedule) { ++ switch (hc->ep_type) { ++ case DWC_OTG_EP_TYPE_CONTROL: ++ case DWC_OTG_EP_TYPE_BULK: ++ hcd->non_periodic_channels--; ++ break; ++ ++ default: ++ /* ++ * Don't release reservations for periodic channels here. ++ * That's done when a periodic transfer is descheduled (i.e. ++ * when the QH is removed from the periodic schedule). ++ */ ++ break; ++ } ++ } else { ++ ++ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags); ++ hcd->available_host_channels++; ++ fiq_print(FIQDBG_INT, hcd->fiq_state, "AHC = %d ", hcd->available_host_channels); ++ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); ++ } ++ ++ /* Try to queue more transfers now that there's a free channel. */ ++ tr_type = dwc_otg_hcd_select_transactions(hcd); ++ if (tr_type != DWC_OTG_TRANSACTION_NONE) { ++ dwc_otg_hcd_queue_transactions(hcd, tr_type); ++ } ++} ++ ++/** ++ * Halts a host channel. If the channel cannot be halted immediately because ++ * the request queue is full, this function ensures that the FIFO empty ++ * interrupt for the appropriate queue is enabled so that the halt request can ++ * be queued when there is space in the request queue. ++ * ++ * This function may also be called in DMA mode. In that case, the channel is ++ * simply released since the core always halts the channel automatically in ++ * DMA mode. ++ */ ++static void halt_channel(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status) ++{ ++ if (hcd->core_if->dma_enable) { ++ release_channel(hcd, hc, qtd, halt_status); ++ return; ++ } ++ ++ /* Slave mode processing... */ ++ dwc_otg_hc_halt(hcd->core_if, hc, halt_status); ++ ++ if (hc->halt_on_queue) { ++ gintmsk_data_t gintmsk = {.d32 = 0 }; ++ dwc_otg_core_global_regs_t *global_regs; ++ global_regs = hcd->core_if->core_global_regs; ++ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL || ++ hc->ep_type == DWC_OTG_EP_TYPE_BULK) { ++ /* ++ * Make sure the Non-periodic Tx FIFO empty interrupt ++ * is enabled so that the non-periodic schedule will ++ * be processed. ++ */ ++ gintmsk.b.nptxfempty = 1; ++ if (fiq_enable) { ++ local_fiq_disable(); ++ fiq_fsm_spin_lock(&hcd->fiq_state->lock); ++ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32); ++ fiq_fsm_spin_unlock(&hcd->fiq_state->lock); ++ local_fiq_enable(); ++ } else { ++ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32); ++ } ++ } else { ++ /* ++ * Move the QH from the periodic queued schedule to ++ * the periodic assigned schedule. This allows the ++ * halt to be queued when the periodic schedule is ++ * processed. ++ */ ++ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned, ++ &hc->qh->qh_list_entry); ++ ++ /* ++ * Make sure the Periodic Tx FIFO Empty interrupt is ++ * enabled so that the periodic schedule will be ++ * processed. ++ */ ++ gintmsk.b.ptxfempty = 1; ++ if (fiq_enable) { ++ local_fiq_disable(); ++ fiq_fsm_spin_lock(&hcd->fiq_state->lock); ++ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32); ++ fiq_fsm_spin_unlock(&hcd->fiq_state->lock); ++ local_fiq_enable(); ++ } else { ++ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32); ++ } ++ } ++ } ++} ++ ++/** ++ * Performs common cleanup for non-periodic transfers after a Transfer ++ * Complete interrupt. This function should be called after any endpoint type ++ * specific handling is finished to release the host channel. ++ */ ++static void complete_non_periodic_xfer(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd, ++ dwc_otg_halt_status_e halt_status) ++{ ++ hcint_data_t hcint; ++ ++ qtd->error_count = 0; ++ ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); ++ if (hcint.b.nyet) { ++ /* ++ * Got a NYET on the last transaction of the transfer. This ++ * means that the endpoint should be in the PING state at the ++ * beginning of the next transfer. ++ */ ++ hc->qh->ping_state = 1; ++ clear_hc_int(hc_regs, nyet); ++ } ++ ++ /* ++ * Always halt and release the host channel to make it available for ++ * more transfers. There may still be more phases for a control ++ * transfer or more data packets for a bulk transfer at this point, ++ * but the host channel is still halted. A channel will be reassigned ++ * to the transfer when the non-periodic schedule is processed after ++ * the channel is released. This allows transactions to be queued ++ * properly via dwc_otg_hcd_queue_transactions, which also enables the ++ * Tx FIFO Empty interrupt if necessary. ++ */ ++ if (hc->ep_is_in) { ++ /* ++ * IN transfers in Slave mode require an explicit disable to ++ * halt the channel. (In DMA mode, this call simply releases ++ * the channel.) ++ */ ++ halt_channel(hcd, hc, qtd, halt_status); ++ } else { ++ /* ++ * The channel is automatically disabled by the core for OUT ++ * transfers in Slave mode. ++ */ ++ release_channel(hcd, hc, qtd, halt_status); ++ } ++} ++ ++/** ++ * Performs common cleanup for periodic transfers after a Transfer Complete ++ * interrupt. This function should be called after any endpoint type specific ++ * handling is finished to release the host channel. ++ */ ++static void complete_periodic_xfer(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd, ++ dwc_otg_halt_status_e halt_status) ++{ ++ hctsiz_data_t hctsiz; ++ qtd->error_count = 0; ++ ++ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz); ++ if (!hc->ep_is_in || hctsiz.b.pktcnt == 0) { ++ /* Core halts channel in these cases. */ ++ release_channel(hcd, hc, qtd, halt_status); ++ } else { ++ /* Flush any outstanding requests from the Tx queue. */ ++ halt_channel(hcd, hc, qtd, halt_status); ++ } ++} ++ ++static int32_t handle_xfercomp_isoc_split_in(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ uint32_t len; ++ struct dwc_otg_hcd_iso_packet_desc *frame_desc; ++ frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; ++ ++ len = get_actual_xfer_length(hc, hc_regs, qtd, ++ DWC_OTG_HC_XFER_COMPLETE, NULL); ++ ++ if (!len) { ++ qtd->complete_split = 0; ++ qtd->isoc_split_offset = 0; ++ return 0; ++ } ++ frame_desc->actual_length += len; ++ ++ if (hc->align_buff && len) ++ dwc_memcpy(qtd->urb->buf + frame_desc->offset + ++ qtd->isoc_split_offset, hc->qh->dw_align_buf, len); ++ qtd->isoc_split_offset += len; ++ ++ if (frame_desc->length == frame_desc->actual_length) { ++ frame_desc->status = 0; ++ qtd->isoc_frame_index++; ++ qtd->complete_split = 0; ++ qtd->isoc_split_offset = 0; ++ } ++ ++ if (qtd->isoc_frame_index == qtd->urb->packet_count) { ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); ++ } else { ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS); ++ } ++ ++ return 1; /* Indicates that channel released */ ++} ++ ++/** ++ * Handles a host channel Transfer Complete interrupt. This handler may be ++ * called in either DMA mode or Slave mode. ++ */ ++static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ int urb_xfer_done; ++ dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE; ++ dwc_otg_hcd_urb_t *urb = qtd->urb; ++ int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info); ++ ++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " ++ "Transfer Complete--\n", hc->hc_num); ++ ++ if (hcd->core_if->dma_desc_enable) { ++ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, halt_status); ++ if (pipe_type == UE_ISOCHRONOUS) { ++ /* Do not disable the interrupt, just clear it */ ++ clear_hc_int(hc_regs, xfercomp); ++ return 1; ++ } ++ goto handle_xfercomp_done; ++ } ++ ++ /* ++ * Handle xfer complete on CSPLIT. ++ */ ++ ++ if (hc->qh->do_split) { ++ if ((hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && hc->ep_is_in ++ && hcd->core_if->dma_enable) { ++ if (qtd->complete_split ++ && handle_xfercomp_isoc_split_in(hcd, hc, hc_regs, ++ qtd)) ++ goto handle_xfercomp_done; ++ } else { ++ qtd->complete_split = 0; ++ } ++ } ++ ++ /* Update the QTD and URB states. */ ++ switch (pipe_type) { ++ case UE_CONTROL: ++ switch (qtd->control_phase) { ++ case DWC_OTG_CONTROL_SETUP: ++ if (urb->length > 0) { ++ qtd->control_phase = DWC_OTG_CONTROL_DATA; ++ } else { ++ qtd->control_phase = DWC_OTG_CONTROL_STATUS; ++ } ++ DWC_DEBUGPL(DBG_HCDV, ++ " Control setup transaction done\n"); ++ halt_status = DWC_OTG_HC_XFER_COMPLETE; ++ break; ++ case DWC_OTG_CONTROL_DATA:{ ++ urb_xfer_done = ++ update_urb_state_xfer_comp(hc, hc_regs, urb, ++ qtd); ++ if (urb_xfer_done) { ++ qtd->control_phase = ++ DWC_OTG_CONTROL_STATUS; ++ DWC_DEBUGPL(DBG_HCDV, ++ " Control data transfer done\n"); ++ } else { ++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); ++ } ++ halt_status = DWC_OTG_HC_XFER_COMPLETE; ++ break; ++ } ++ case DWC_OTG_CONTROL_STATUS: ++ DWC_DEBUGPL(DBG_HCDV, " Control transfer complete\n"); ++ if (urb->status == -DWC_E_IN_PROGRESS) { ++ urb->status = 0; ++ } ++ hcd->fops->complete(hcd, urb->priv, urb, urb->status); ++ halt_status = DWC_OTG_HC_XFER_URB_COMPLETE; ++ break; ++ } ++ ++ complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status); ++ break; ++ case UE_BULK: ++ DWC_DEBUGPL(DBG_HCDV, " Bulk transfer complete\n"); ++ urb_xfer_done = ++ update_urb_state_xfer_comp(hc, hc_regs, urb, qtd); ++ if (urb_xfer_done) { ++ hcd->fops->complete(hcd, urb->priv, urb, urb->status); ++ halt_status = DWC_OTG_HC_XFER_URB_COMPLETE; ++ } else { ++ halt_status = DWC_OTG_HC_XFER_COMPLETE; ++ } ++ ++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); ++ complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status); ++ break; ++ case UE_INTERRUPT: ++ DWC_DEBUGPL(DBG_HCDV, " Interrupt transfer complete\n"); ++ urb_xfer_done = ++ update_urb_state_xfer_comp(hc, hc_regs, urb, qtd); ++ ++ /* ++ * Interrupt URB is done on the first transfer complete ++ * interrupt. ++ */ ++ if (urb_xfer_done) { ++ hcd->fops->complete(hcd, urb->priv, urb, urb->status); ++ halt_status = DWC_OTG_HC_XFER_URB_COMPLETE; ++ } else { ++ halt_status = DWC_OTG_HC_XFER_COMPLETE; ++ } ++ ++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); ++ complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status); ++ break; ++ case UE_ISOCHRONOUS: ++ DWC_DEBUGPL(DBG_HCDV, " Isochronous transfer complete\n"); ++ if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) { ++ halt_status = ++ update_isoc_urb_state(hcd, hc, hc_regs, qtd, ++ DWC_OTG_HC_XFER_COMPLETE); ++ } ++ complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status); ++ break; ++ } ++ ++handle_xfercomp_done: ++ disable_hc_int(hc_regs, xfercompl); ++ ++ return 1; ++} ++ ++/** ++ * Handles a host channel STALL interrupt. This handler may be called in ++ * either DMA mode or Slave mode. ++ */ ++static int32_t handle_hc_stall_intr(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ dwc_otg_hcd_urb_t *urb = qtd->urb; ++ int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info); ++ ++ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " ++ "STALL Received--\n", hc->hc_num); ++ ++ if (hcd->core_if->dma_desc_enable) { ++ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_STALL); ++ goto handle_stall_done; ++ } ++ ++ if (pipe_type == UE_CONTROL) { ++ hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE); ++ } ++ ++ if (pipe_type == UE_BULK || pipe_type == UE_INTERRUPT) { ++ hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE); ++ /* ++ * USB protocol requires resetting the data toggle for bulk ++ * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT) ++ * setup command is issued to the endpoint. Anticipate the ++ * CLEAR_FEATURE command since a STALL has occurred and reset ++ * the data toggle now. ++ */ ++ hc->qh->data_toggle = 0; ++ } ++ ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL); ++ ++handle_stall_done: ++ disable_hc_int(hc_regs, stall); ++ ++ return 1; ++} ++ ++/* ++ * Updates the state of the URB when a transfer has been stopped due to an ++ * abnormal condition before the transfer completes. Modifies the ++ * actual_length field of the URB to reflect the number of bytes that have ++ * actually been transferred via the host channel. ++ */ ++static void update_urb_state_xfer_intr(dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_hcd_urb_t * urb, ++ dwc_otg_qtd_t * qtd, ++ dwc_otg_halt_status_e halt_status) ++{ ++ uint32_t bytes_transferred = get_actual_xfer_length(hc, hc_regs, qtd, ++ halt_status, NULL); ++ /* non DWORD-aligned buffer case handling. */ ++ if (hc->align_buff && bytes_transferred && hc->ep_is_in) { ++ dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf, ++ bytes_transferred); ++ } ++ ++ urb->actual_length += bytes_transferred; ++ ++#ifdef DEBUG ++ { ++ hctsiz_data_t hctsiz; ++ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz); ++ DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n", ++ __func__, (hc->ep_is_in ? "IN" : "OUT"), ++ hc->hc_num); ++ DWC_DEBUGPL(DBG_HCDV, " hc->start_pkt_count %d\n", ++ hc->start_pkt_count); ++ DWC_DEBUGPL(DBG_HCDV, " hctsiz.pktcnt %d\n", hctsiz.b.pktcnt); ++ DWC_DEBUGPL(DBG_HCDV, " hc->max_packet %d\n", hc->max_packet); ++ DWC_DEBUGPL(DBG_HCDV, " bytes_transferred %d\n", ++ bytes_transferred); ++ DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n", ++ urb->actual_length); ++ DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n", ++ urb->length); ++ } ++#endif ++} ++ ++/** ++ * Handles a host channel NAK interrupt. This handler may be called in either ++ * DMA mode or Slave mode. ++ */ ++static int32_t handle_hc_nak_intr(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " ++ "NAK Received--\n", hc->hc_num); ++ ++ /* ++ * When we get bulk NAKs then remember this so we holdoff on this qh until ++ * the beginning of the next frame ++ */ ++ switch(dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) { ++ case UE_BULK: ++ case UE_CONTROL: ++ if (nak_holdoff && qtd->qh->do_split) ++ hc->qh->nak_frame = dwc_otg_hcd_get_frame_number(hcd); ++ } ++ ++ /* ++ * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and ++ * interrupt. Re-start the SSPLIT transfer. ++ */ ++ if (hc->do_split) { ++ if (hc->complete_split) { ++ qtd->error_count = 0; ++ } ++ qtd->complete_split = 0; ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK); ++ goto handle_nak_done; ++ } ++ ++ switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) { ++ case UE_CONTROL: ++ case UE_BULK: ++ if (hcd->core_if->dma_enable && hc->ep_is_in) { ++ /* ++ * NAK interrupts are enabled on bulk/control IN ++ * transfers in DMA mode for the sole purpose of ++ * resetting the error count after a transaction error ++ * occurs. The core will continue transferring data. ++ * Disable other interrupts unmasked for the same ++ * reason. ++ */ ++ disable_hc_int(hc_regs, datatglerr); ++ disable_hc_int(hc_regs, ack); ++ qtd->error_count = 0; ++ goto handle_nak_done; ++ } ++ ++ /* ++ * NAK interrupts normally occur during OUT transfers in DMA ++ * or Slave mode. For IN transfers, more requests will be ++ * queued as request queue space is available. ++ */ ++ qtd->error_count = 0; ++ ++ if (!hc->qh->ping_state) { ++ update_urb_state_xfer_intr(hc, hc_regs, ++ qtd->urb, qtd, ++ DWC_OTG_HC_XFER_NAK); ++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); ++ ++ if (hc->speed == DWC_OTG_EP_SPEED_HIGH) ++ hc->qh->ping_state = 1; ++ } ++ ++ /* ++ * Halt the channel so the transfer can be re-started from ++ * the appropriate point or the PING protocol will ++ * start/continue. ++ */ ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK); ++ break; ++ case UE_INTERRUPT: ++ qtd->error_count = 0; ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK); ++ break; ++ case UE_ISOCHRONOUS: ++ /* Should never get called for isochronous transfers. */ ++ DWC_ASSERT(1, "NACK interrupt for ISOC transfer\n"); ++ break; ++ } ++ ++handle_nak_done: ++ disable_hc_int(hc_regs, nak); ++ ++ return 1; ++} ++ ++/** ++ * Handles a host channel ACK interrupt. This interrupt is enabled when ++ * performing the PING protocol in Slave mode, when errors occur during ++ * either Slave mode or DMA mode, and during Start Split transactions. ++ */ ++static int32_t handle_hc_ack_intr(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " ++ "ACK Received--\n", hc->hc_num); ++ ++ if (hc->do_split) { ++ /* ++ * Handle ACK on SSPLIT. ++ * ACK should not occur in CSPLIT. ++ */ ++ if (!hc->ep_is_in && hc->data_pid_start != DWC_OTG_HC_PID_SETUP) { ++ qtd->ssplit_out_xfer_count = hc->xfer_len; ++ } ++ if (!(hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)) { ++ /* Don't need complete for isochronous out transfers. */ ++ qtd->complete_split = 1; ++ } ++ ++ /* ISOC OUT */ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) { ++ switch (hc->xact_pos) { ++ case DWC_HCSPLIT_XACTPOS_ALL: ++ break; ++ case DWC_HCSPLIT_XACTPOS_END: ++ qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL; ++ qtd->isoc_split_offset = 0; ++ break; ++ case DWC_HCSPLIT_XACTPOS_BEGIN: ++ case DWC_HCSPLIT_XACTPOS_MID: ++ /* ++ * For BEGIN or MID, calculate the length for ++ * the next microframe to determine the correct ++ * SSPLIT token, either MID or END. ++ */ ++ { ++ struct dwc_otg_hcd_iso_packet_desc ++ *frame_desc; ++ ++ frame_desc = ++ &qtd->urb-> ++ iso_descs[qtd->isoc_frame_index]; ++ qtd->isoc_split_offset += 188; ++ ++ if ((frame_desc->length - ++ qtd->isoc_split_offset) <= 188) { ++ qtd->isoc_split_pos = ++ DWC_HCSPLIT_XACTPOS_END; ++ } else { ++ qtd->isoc_split_pos = ++ DWC_HCSPLIT_XACTPOS_MID; ++ } ++ ++ } ++ break; ++ } ++ } else { ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK); ++ } ++ } else { ++ /* ++ * An unmasked ACK on a non-split DMA transaction is ++ * for the sole purpose of resetting error counts. Disable other ++ * interrupts unmasked for the same reason. ++ */ ++ if(hcd->core_if->dma_enable) { ++ disable_hc_int(hc_regs, datatglerr); ++ disable_hc_int(hc_regs, nak); ++ } ++ qtd->error_count = 0; ++ ++ if (hc->qh->ping_state) { ++ hc->qh->ping_state = 0; ++ /* ++ * Halt the channel so the transfer can be re-started ++ * from the appropriate point. This only happens in ++ * Slave mode. In DMA mode, the ping_state is cleared ++ * when the transfer is started because the core ++ * automatically executes the PING, then the transfer. ++ */ ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK); ++ } ++ } ++ ++ /* ++ * If the ACK occurred when _not_ in the PING state, let the channel ++ * continue transferring data after clearing the error count. ++ */ ++ ++ disable_hc_int(hc_regs, ack); ++ ++ return 1; ++} ++ ++/** ++ * Handles a host channel NYET interrupt. This interrupt should only occur on ++ * Bulk and Control OUT endpoints and for complete split transactions. If a ++ * NYET occurs at the same time as a Transfer Complete interrupt, it is ++ * handled in the xfercomp interrupt handler, not here. This handler may be ++ * called in either DMA mode or Slave mode. ++ */ ++static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " ++ "NYET Received--\n", hc->hc_num); ++ ++ /* ++ * NYET on CSPLIT ++ * re-do the CSPLIT immediately on non-periodic ++ */ ++ if (hc->do_split && hc->complete_split) { ++ if (hc->ep_is_in && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) ++ && hcd->core_if->dma_enable) { ++ qtd->complete_split = 0; ++ qtd->isoc_split_offset = 0; ++ if (++qtd->isoc_frame_index == qtd->urb->packet_count) { ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); ++ } ++ else ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS); ++ goto handle_nyet_done; ++ } ++ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || ++ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { ++ int frnum = dwc_otg_hcd_get_frame_number(hcd); ++ ++ // With the FIQ running we only ever see the failed NYET ++ if (dwc_full_frame_num(frnum) != ++ dwc_full_frame_num(hc->qh->sched_frame) || ++ fiq_fsm_enable) { ++ /* ++ * No longer in the same full speed frame. ++ * Treat this as a transaction error. ++ */ ++#if 0 ++ /** @todo Fix system performance so this can ++ * be treated as an error. Right now complete ++ * splits cannot be scheduled precisely enough ++ * due to other system activity, so this error ++ * occurs regularly in Slave mode. ++ */ ++ qtd->error_count++; ++#endif ++ qtd->complete_split = 0; ++ halt_channel(hcd, hc, qtd, ++ DWC_OTG_HC_XFER_XACT_ERR); ++ /** @todo add support for isoc release */ ++ goto handle_nyet_done; ++ } ++ } ++ ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET); ++ goto handle_nyet_done; ++ } ++ ++ hc->qh->ping_state = 1; ++ qtd->error_count = 0; ++ ++ update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd, ++ DWC_OTG_HC_XFER_NYET); ++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); ++ ++ /* ++ * Halt the channel and re-start the transfer so the PING ++ * protocol will start. ++ */ ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET); ++ ++handle_nyet_done: ++ disable_hc_int(hc_regs, nyet); ++ return 1; ++} ++ ++/** ++ * Handles a host channel babble interrupt. This handler may be called in ++ * either DMA mode or Slave mode. ++ */ ++static int32_t handle_hc_babble_intr(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " ++ "Babble Error--\n", hc->hc_num); ++ ++ if (hcd->core_if->dma_desc_enable) { ++ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, ++ DWC_OTG_HC_XFER_BABBLE_ERR); ++ goto handle_babble_done; ++ } ++ ++ if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) { ++ hcd->fops->complete(hcd, qtd->urb->priv, ++ qtd->urb, -DWC_E_OVERFLOW); ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR); ++ } else { ++ dwc_otg_halt_status_e halt_status; ++ halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd, ++ DWC_OTG_HC_XFER_BABBLE_ERR); ++ halt_channel(hcd, hc, qtd, halt_status); ++ } ++ ++handle_babble_done: ++ disable_hc_int(hc_regs, bblerr); ++ return 1; ++} ++ ++/** ++ * Handles a host channel AHB error interrupt. This handler is only called in ++ * DMA mode. ++ */ ++static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ hcchar_data_t hcchar; ++ hcsplt_data_t hcsplt; ++ hctsiz_data_t hctsiz; ++ uint32_t hcdma; ++ char *pipetype, *speed; ++ ++ dwc_otg_hcd_urb_t *urb = qtd->urb; ++ ++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " ++ "AHB Error--\n", hc->hc_num); ++ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt); ++ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz); ++ hcdma = DWC_READ_REG32(&hc_regs->hcdma); ++ ++ DWC_ERROR("AHB ERROR, Channel %d\n", hc->hc_num); ++ DWC_ERROR(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32); ++ DWC_ERROR(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma); ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n"); ++ DWC_ERROR(" Device address: %d\n", ++ dwc_otg_hcd_get_dev_addr(&urb->pipe_info)); ++ DWC_ERROR(" Endpoint: %d, %s\n", ++ dwc_otg_hcd_get_ep_num(&urb->pipe_info), ++ (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT")); ++ ++ switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) { ++ case UE_CONTROL: ++ pipetype = "CONTROL"; ++ break; ++ case UE_BULK: ++ pipetype = "BULK"; ++ break; ++ case UE_INTERRUPT: ++ pipetype = "INTERRUPT"; ++ break; ++ case UE_ISOCHRONOUS: ++ pipetype = "ISOCHRONOUS"; ++ break; ++ default: ++ pipetype = "UNKNOWN"; ++ break; ++ } ++ ++ DWC_ERROR(" Endpoint type: %s\n", pipetype); ++ ++ switch (hc->speed) { ++ case DWC_OTG_EP_SPEED_HIGH: ++ speed = "HIGH"; ++ break; ++ case DWC_OTG_EP_SPEED_FULL: ++ speed = "FULL"; ++ break; ++ case DWC_OTG_EP_SPEED_LOW: ++ speed = "LOW"; ++ break; ++ default: ++ speed = "UNKNOWN"; ++ break; ++ }; ++ ++ DWC_ERROR(" Speed: %s\n", speed); ++ ++ DWC_ERROR(" Max packet size: %d\n", ++ dwc_otg_hcd_get_mps(&urb->pipe_info)); ++ DWC_ERROR(" Data buffer length: %d\n", urb->length); ++ DWC_ERROR(" Transfer buffer: %p, Transfer DMA: %p\n", ++ urb->buf, (void *)urb->dma); ++ DWC_ERROR(" Setup buffer: %p, Setup DMA: %p\n", ++ urb->setup_packet, (void *)urb->setup_dma); ++ DWC_ERROR(" Interval: %d\n", urb->interval); ++ ++ /* Core haltes the channel for Descriptor DMA mode */ ++ if (hcd->core_if->dma_desc_enable) { ++ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, ++ DWC_OTG_HC_XFER_AHB_ERR); ++ goto handle_ahberr_done; ++ } ++ ++ hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_IO); ++ ++ /* ++ * Force a channel halt. Don't call halt_channel because that won't ++ * write to the HCCHARn register in DMA mode to force the halt. ++ */ ++ dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_AHB_ERR); ++handle_ahberr_done: ++ disable_hc_int(hc_regs, ahberr); ++ return 1; ++} ++ ++/** ++ * Handles a host channel transaction error interrupt. This handler may be ++ * called in either DMA mode or Slave mode. ++ */ ++static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " ++ "Transaction Error--\n", hc->hc_num); ++ ++ if (hcd->core_if->dma_desc_enable) { ++ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, ++ DWC_OTG_HC_XFER_XACT_ERR); ++ goto handle_xacterr_done; ++ } ++ ++ switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) { ++ case UE_CONTROL: ++ case UE_BULK: ++ qtd->error_count++; ++ if (!hc->qh->ping_state) { ++ ++ update_urb_state_xfer_intr(hc, hc_regs, ++ qtd->urb, qtd, ++ DWC_OTG_HC_XFER_XACT_ERR); ++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); ++ if (!hc->ep_is_in && hc->speed == DWC_OTG_EP_SPEED_HIGH) { ++ hc->qh->ping_state = 1; ++ } ++ } ++ ++ /* ++ * Halt the channel so the transfer can be re-started from ++ * the appropriate point or the PING protocol will start. ++ */ ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR); ++ break; ++ case UE_INTERRUPT: ++ qtd->error_count++; ++ if (hc->do_split && hc->complete_split) { ++ qtd->complete_split = 0; ++ } ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR); ++ break; ++ case UE_ISOCHRONOUS: ++ { ++ dwc_otg_halt_status_e halt_status; ++ halt_status = ++ update_isoc_urb_state(hcd, hc, hc_regs, qtd, ++ DWC_OTG_HC_XFER_XACT_ERR); ++ ++ halt_channel(hcd, hc, qtd, halt_status); ++ } ++ break; ++ } ++handle_xacterr_done: ++ disable_hc_int(hc_regs, xacterr); ++ ++ return 1; ++} ++ ++/** ++ * Handles a host channel frame overrun interrupt. This handler may be called ++ * in either DMA mode or Slave mode. ++ */ ++static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " ++ "Frame Overrun--\n", hc->hc_num); ++ ++ switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) { ++ case UE_CONTROL: ++ case UE_BULK: ++ break; ++ case UE_INTERRUPT: ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN); ++ break; ++ case UE_ISOCHRONOUS: ++ { ++ dwc_otg_halt_status_e halt_status; ++ halt_status = ++ update_isoc_urb_state(hcd, hc, hc_regs, qtd, ++ DWC_OTG_HC_XFER_FRAME_OVERRUN); ++ ++ halt_channel(hcd, hc, qtd, halt_status); ++ } ++ break; ++ } ++ ++ disable_hc_int(hc_regs, frmovrun); ++ ++ return 1; ++} ++ ++/** ++ * Handles a host channel data toggle error interrupt. This handler may be ++ * called in either DMA mode or Slave mode. ++ */ ++static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " ++ "Data Toggle Error on %s transfer--\n", ++ hc->hc_num, (hc->ep_is_in ? "IN" : "OUT")); ++ ++ /* Data toggles on split transactions cause the hc to halt. ++ * restart transfer */ ++ if(hc->qh->do_split) ++ { ++ qtd->error_count++; ++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); ++ update_urb_state_xfer_intr(hc, hc_regs, ++ qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR); ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR); ++ } else if (hc->ep_is_in) { ++ /* An unmasked data toggle error on a non-split DMA transaction is ++ * for the sole purpose of resetting error counts. Disable other ++ * interrupts unmasked for the same reason. ++ */ ++ if(hcd->core_if->dma_enable) { ++ disable_hc_int(hc_regs, ack); ++ disable_hc_int(hc_regs, nak); ++ } ++ qtd->error_count = 0; ++ } ++ ++ disable_hc_int(hc_regs, datatglerr); ++ ++ return 1; ++} ++ ++#ifdef DEBUG ++/** ++ * This function is for debug only. It checks that a valid halt status is set ++ * and that HCCHARn.chdis is clear. If there's a problem, corrective action is ++ * taken and a warning is issued. ++ * @return 1 if halt status is ok, 0 otherwise. ++ */ ++static inline int halt_status_ok(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ hcchar_data_t hcchar; ++ hctsiz_data_t hctsiz; ++ hcint_data_t hcint; ++ hcintmsk_data_t hcintmsk; ++ hcsplt_data_t hcsplt; ++ ++ if (hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) { ++ /* ++ * This code is here only as a check. This condition should ++ * never happen. Ignore the halt if it does occur. ++ */ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz); ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); ++ hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk); ++ hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt); ++ DWC_WARN ++ ("%s: hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, " ++ "channel %d, hcchar 0x%08x, hctsiz 0x%08x, " ++ "hcint 0x%08x, hcintmsk 0x%08x, " ++ "hcsplt 0x%08x, qtd->complete_split %d\n", __func__, ++ hc->hc_num, hcchar.d32, hctsiz.d32, hcint.d32, ++ hcintmsk.d32, hcsplt.d32, qtd->complete_split); ++ ++ DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n", ++ __func__, hc->hc_num); ++ DWC_WARN("\n"); ++ clear_hc_int(hc_regs, chhltd); ++ return 0; ++ } ++ ++ /* ++ * This code is here only as a check. hcchar.chdis should ++ * never be set when the halt interrupt occurs. Halt the ++ * channel again if it does occur. ++ */ ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ if (hcchar.b.chdis) { ++ DWC_WARN("%s: hcchar.chdis set unexpectedly, " ++ "hcchar 0x%08x, trying to halt again\n", ++ __func__, hcchar.d32); ++ clear_hc_int(hc_regs, chhltd); ++ hc->halt_pending = 0; ++ halt_channel(hcd, hc, qtd, hc->halt_status); ++ return 0; ++ } ++ ++ return 1; ++} ++#endif ++ ++/** ++ * Handles a host Channel Halted interrupt in DMA mode. This handler ++ * determines the reason the channel halted and proceeds accordingly. ++ */ ++static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ int out_nak_enh = 0; ++ hcint_data_t hcint; ++ hcintmsk_data_t hcintmsk; ++ /* For core with OUT NAK enhancement, the flow for high- ++ * speed CONTROL/BULK OUT is handled a little differently. ++ */ ++ if (hcd->core_if->snpsid >= OTG_CORE_REV_2_71a) { ++ if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in && ++ (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL || ++ hc->ep_type == DWC_OTG_EP_TYPE_BULK)) { ++ out_nak_enh = 1; ++ } ++ } ++ ++ if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE || ++ (hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR ++ && !hcd->core_if->dma_desc_enable)) { ++ /* ++ * Just release the channel. A dequeue can happen on a ++ * transfer timeout. In the case of an AHB Error, the channel ++ * was forced to halt because there's no way to gracefully ++ * recover. ++ */ ++ if (hcd->core_if->dma_desc_enable) ++ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, ++ hc->halt_status); ++ else ++ release_channel(hcd, hc, qtd, hc->halt_status); ++ return; ++ } ++ ++ /* Read the HCINTn register to determine the cause for the halt. */ ++ ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); ++ hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk); ++ ++ if (hcint.b.xfercomp) { ++ /** @todo This is here because of a possible hardware bug. Spec ++ * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT ++ * interrupt w/ACK bit set should occur, but I only see the ++ * XFERCOMP bit, even with it masked out. This is a workaround ++ * for that behavior. Should fix this when hardware is fixed. ++ */ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) { ++ handle_hc_ack_intr(hcd, hc, hc_regs, qtd); ++ } ++ handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.stall) { ++ handle_hc_stall_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.xacterr && !hcd->core_if->dma_desc_enable) { ++ if (out_nak_enh) { ++ if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) { ++ DWC_DEBUGPL(DBG_HCD, "XactErr with NYET/NAK/ACK\n"); ++ qtd->error_count = 0; ++ } else { ++ DWC_DEBUGPL(DBG_HCD, "XactErr without NYET/NAK/ACK\n"); ++ } ++ } ++ ++ /* ++ * Must handle xacterr before nak or ack. Could get a xacterr ++ * at the same time as either of these on a BULK/CONTROL OUT ++ * that started with a PING. The xacterr takes precedence. ++ */ ++ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.xcs_xact && hcd->core_if->dma_desc_enable) { ++ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.ahberr && hcd->core_if->dma_desc_enable) { ++ handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.bblerr) { ++ handle_hc_babble_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.frmovrun) { ++ handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.datatglerr) { ++ handle_hc_datatglerr_intr(hcd, hc, hc_regs, qtd); ++ } else if (!out_nak_enh) { ++ if (hcint.b.nyet) { ++ /* ++ * Must handle nyet before nak or ack. Could get a nyet at the ++ * same time as either of those on a BULK/CONTROL OUT that ++ * started with a PING. The nyet takes precedence. ++ */ ++ handle_hc_nyet_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.nak && !hcintmsk.b.nak) { ++ /* ++ * If nak is not masked, it's because a non-split IN transfer ++ * is in an error state. In that case, the nak is handled by ++ * the nak interrupt handler, not here. Handle nak here for ++ * BULK/CONTROL OUT transfers, which halt on a NAK to allow ++ * rewinding the buffer pointer. ++ */ ++ handle_hc_nak_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.ack && !hcintmsk.b.ack) { ++ /* ++ * If ack is not masked, it's because a non-split IN transfer ++ * is in an error state. In that case, the ack is handled by ++ * the ack interrupt handler, not here. Handle ack here for ++ * split transfers. Start splits halt on ACK. ++ */ ++ handle_hc_ack_intr(hcd, hc, hc_regs, qtd); ++ } else { ++ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || ++ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { ++ /* ++ * A periodic transfer halted with no other channel ++ * interrupts set. Assume it was halted by the core ++ * because it could not be completed in its scheduled ++ * (micro)frame. ++ */ ++#ifdef DEBUG ++ DWC_PRINTF ++ ("%s: Halt channel %d (assume incomplete periodic transfer)\n", ++ __func__, hc->hc_num); ++#endif ++ halt_channel(hcd, hc, qtd, ++ DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE); ++ } else { ++ DWC_ERROR ++ ("%s: Channel %d, DMA Mode -- ChHltd set, but reason " ++ "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n", ++ __func__, hc->hc_num, hcint.d32, ++ DWC_READ_REG32(&hcd-> ++ core_if->core_global_regs-> ++ gintsts)); ++ /* Failthrough: use 3-strikes rule */ ++ qtd->error_count++; ++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); ++ update_urb_state_xfer_intr(hc, hc_regs, ++ qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR); ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR); ++ } ++ ++ } ++ } else { ++ DWC_PRINTF("NYET/NAK/ACK/other in non-error case, 0x%08x\n", ++ hcint.d32); ++ /* Failthrough: use 3-strikes rule */ ++ qtd->error_count++; ++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); ++ update_urb_state_xfer_intr(hc, hc_regs, ++ qtd->urb, qtd, DWC_OTG_HC_XFER_XACT_ERR); ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR); ++ } ++} ++ ++/** ++ * Handles a host channel Channel Halted interrupt. ++ * ++ * In slave mode, this handler is called only when the driver specifically ++ * requests a halt. This occurs during handling other host channel interrupts ++ * (e.g. nak, xacterr, stall, nyet, etc.). ++ * ++ * In DMA mode, this is the interrupt that occurs when the core has finished ++ * processing a transfer on a channel. Other host channel interrupts (except ++ * ahberr) are disabled in DMA mode. ++ */ ++static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " ++ "Channel Halted--\n", hc->hc_num); ++ ++ if (hcd->core_if->dma_enable) { ++ handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd); ++ } else { ++#ifdef DEBUG ++ if (!halt_status_ok(hcd, hc, hc_regs, qtd)) { ++ return 1; ++ } ++#endif ++ release_channel(hcd, hc, qtd, hc->halt_status); ++ } ++ ++ return 1; ++} ++ ++ ++/** ++ * dwc_otg_fiq_unmangle_isoc() - Update the iso_frame_desc structure on ++ * FIQ transfer completion ++ * @hcd: Pointer to dwc_otg_hcd struct ++ * @num: Host channel number ++ * ++ * 1. Un-mangle the status as recorded in each iso_frame_desc status ++ * 2. Copy it from the dwc_otg_urb into the real URB ++ */ ++void dwc_otg_fiq_unmangle_isoc(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_qtd_t *qtd, uint32_t num) ++{ ++ struct dwc_otg_hcd_urb *dwc_urb = qtd->urb; ++ int nr_frames = dwc_urb->packet_count; ++ int i; ++ hcint_data_t frame_hcint; ++ ++ for (i = 0; i < nr_frames; i++) { ++ frame_hcint.d32 = dwc_urb->iso_descs[i].status; ++ if (frame_hcint.b.xfercomp) { ++ dwc_urb->iso_descs[i].status = 0; ++ dwc_urb->actual_length += dwc_urb->iso_descs[i].actual_length; ++ } else if (frame_hcint.b.frmovrun) { ++ if (qh->ep_is_in) ++ dwc_urb->iso_descs[i].status = -DWC_E_NO_STREAM_RES; ++ else ++ dwc_urb->iso_descs[i].status = -DWC_E_COMMUNICATION; ++ dwc_urb->error_count++; ++ dwc_urb->iso_descs[i].actual_length = 0; ++ } else if (frame_hcint.b.xacterr) { ++ dwc_urb->iso_descs[i].status = -DWC_E_PROTOCOL; ++ dwc_urb->error_count++; ++ dwc_urb->iso_descs[i].actual_length = 0; ++ } else if (frame_hcint.b.bblerr) { ++ dwc_urb->iso_descs[i].status = -DWC_E_OVERFLOW; ++ dwc_urb->error_count++; ++ dwc_urb->iso_descs[i].actual_length = 0; ++ } else { ++ /* Something went wrong */ ++ dwc_urb->iso_descs[i].status = -1; ++ dwc_urb->iso_descs[i].actual_length = 0; ++ dwc_urb->error_count++; ++ } ++ } ++ qh->sched_frame = dwc_frame_num_inc(qh->sched_frame, qh->interval * (nr_frames - 1)); ++ ++ //printk_ratelimited(KERN_INFO "%s: HS isochronous of %d/%d frames with %d errors complete\n", ++ // __FUNCTION__, i, dwc_urb->packet_count, dwc_urb->error_count); ++} ++ ++/** ++ * dwc_otg_fiq_unsetup_per_dma() - Remove data from bounce buffers for split transactions ++ * @hcd: Pointer to dwc_otg_hcd struct ++ * @num: Host channel number ++ * ++ * Copies data from the FIQ bounce buffers into the URB's transfer buffer. Does not modify URB state. ++ * Returns total length of data or -1 if the buffers were not used. ++ * ++ */ ++int dwc_otg_fiq_unsetup_per_dma(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_qtd_t *qtd, uint32_t num) ++{ ++ dwc_hc_t *hc = qh->channel; ++ struct fiq_dma_blob *blob = hcd->fiq_dmab; ++ struct fiq_channel_state *st = &hcd->fiq_state->channel[num]; ++ uint8_t *ptr = NULL; ++ int index = 0, len = 0; ++ int i = 0; ++ if (hc->ep_is_in) { ++ /* Copy data out of the DMA bounce buffers to the URB's buffer. ++ * The align_buf is ignored as this is ignored on FSM enqueue. */ ++ ptr = qtd->urb->buf; ++ if (qh->ep_type == UE_ISOCHRONOUS) { ++ /* Isoc IN transactions - grab the offset of the iso_frame_desc into the URB transfer buffer */ ++ index = qtd->isoc_frame_index; ++ ptr += qtd->urb->iso_descs[index].offset; ++ } else { ++ /* Need to increment by actual_length for interrupt IN */ ++ ptr += qtd->urb->actual_length; ++ } ++ ++ for (i = 0; i < st->dma_info.index; i++) { ++ len += st->dma_info.slot_len[i]; ++ dwc_memcpy(ptr, &blob->channel[num].index[i].buf[0], st->dma_info.slot_len[i]); ++ ptr += st->dma_info.slot_len[i]; ++ } ++ return len; ++ } else { ++ /* OUT endpoints - nothing to do. */ ++ return -1; ++ } ++ ++} ++/** ++ * dwc_otg_hcd_handle_hc_fsm() - handle an unmasked channel interrupt ++ * from a channel handled in the FIQ ++ * @hcd: Pointer to dwc_otg_hcd struct ++ * @num: Host channel number ++ * ++ * If a host channel interrupt was received by the IRQ and this was a channel ++ * used by the FIQ, the execution flow for transfer completion is substantially ++ * different from the normal (messy) path. This function and its friends handles ++ * channel cleanup and transaction completion from a FIQ transaction. ++ */ ++void dwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd_t *hcd, uint32_t num) ++{ ++ struct fiq_channel_state *st = &hcd->fiq_state->channel[num]; ++ dwc_hc_t *hc = hcd->hc_ptr_array[num]; ++ dwc_otg_qtd_t *qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list); ++ dwc_otg_qh_t *qh = hc->qh; ++ dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[num]; ++ hcint_data_t hcint = hcd->fiq_state->channel[num].hcint_copy; ++ int hostchannels = 0; ++ fiq_print(FIQDBG_INT, hcd->fiq_state, "OUT %01d %01d ", num , st->fsm); ++ ++ hostchannels = hcd->available_host_channels; ++ switch (st->fsm) { ++ case FIQ_TEST: ++ break; ++ ++ case FIQ_DEQUEUE_ISSUED: ++ /* hc_halt was called. QTD no longer exists. */ ++ /* TODO: for a nonperiodic split transaction, need to issue a ++ * CLEAR_TT_BUFFER hub command if we were in the start-split phase. ++ */ ++ release_channel(hcd, hc, NULL, hc->halt_status); ++ break; ++ ++ case FIQ_NP_SPLIT_DONE: ++ /* Nonperiodic transaction complete. */ ++ if (!hc->ep_is_in) { ++ qtd->ssplit_out_xfer_count = hc->xfer_len; ++ } ++ if (hcint.b.xfercomp) { ++ handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.nak) { ++ handle_hc_nak_intr(hcd, hc, hc_regs, qtd); ++ } ++ break; ++ ++ case FIQ_NP_SPLIT_HS_ABORTED: ++ /* A HS abort is a 3-strikes on the HS bus at any point in the transaction. ++ * Normally a CLEAR_TT_BUFFER hub command would be required: we can't do that ++ * because there's no guarantee which order a non-periodic split happened in. ++ * We could end up clearing a perfectly good transaction out of the buffer. ++ */ ++ if (hcint.b.xacterr) { ++ qtd->error_count += st->nr_errors; ++ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.ahberr) { ++ handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd); ++ } else { ++ local_fiq_disable(); ++ BUG(); ++ } ++ break; ++ ++ case FIQ_NP_SPLIT_LS_ABORTED: ++ /* A few cases can cause this - either an unknown state on a SSPLIT or ++ * STALL/data toggle error response on a CSPLIT */ ++ if (hcint.b.stall) { ++ handle_hc_stall_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.datatglerr) { ++ handle_hc_datatglerr_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.bblerr) { ++ handle_hc_babble_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.ahberr) { ++ handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd); ++ } else { ++ local_fiq_disable(); ++ BUG(); ++ } ++ break; ++ ++ case FIQ_PER_SPLIT_DONE: ++ /* Isoc IN or Interrupt IN/OUT */ ++ ++ /* Flow control here is different from the normal execution by the driver. ++ * We need to completely ignore most of the driver's method of handling ++ * split transactions and do it ourselves. ++ */ ++ if (hc->ep_type == UE_INTERRUPT) { ++ if (hcint.b.nak) { ++ handle_hc_nak_intr(hcd, hc, hc_regs, qtd); ++ } else if (hc->ep_is_in) { ++ int len; ++ len = dwc_otg_fiq_unsetup_per_dma(hcd, hc->qh, qtd, num); ++ //printk(KERN_NOTICE "FIQ Transaction: hc=%d len=%d urb_len = %d\n", num, len, qtd->urb->length); ++ qtd->urb->actual_length += len; ++ if (qtd->urb->actual_length >= qtd->urb->length) { ++ qtd->urb->status = 0; ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); ++ } else { ++ /* Interrupt transfer not complete yet - is it a short read? */ ++ if (len < hc->max_packet) { ++ /* Interrupt transaction complete */ ++ qtd->urb->status = 0; ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); ++ } else { ++ /* Further transactions required */ ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE); ++ } ++ } ++ } else { ++ /* Interrupt OUT complete. */ ++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); ++ qtd->urb->actual_length += hc->xfer_len; ++ if (qtd->urb->actual_length >= qtd->urb->length) { ++ qtd->urb->status = 0; ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, qtd->urb->status); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); ++ } else { ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE); ++ } ++ } ++ } else { ++ /* ISOC IN complete. */ ++ struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; ++ int len = 0; ++ /* Record errors, update qtd. */ ++ if (st->nr_errors) { ++ frame_desc->actual_length = 0; ++ frame_desc->status = -DWC_E_PROTOCOL; ++ } else { ++ frame_desc->status = 0; ++ /* Unswizzle dma */ ++ len = dwc_otg_fiq_unsetup_per_dma(hcd, qh, qtd, num); ++ frame_desc->actual_length = len; ++ } ++ qtd->isoc_frame_index++; ++ if (qtd->isoc_frame_index == qtd->urb->packet_count) { ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); ++ } else { ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE); ++ } ++ } ++ break; ++ ++ case FIQ_PER_ISO_OUT_DONE: { ++ struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; ++ /* Record errors, update qtd. */ ++ if (st->nr_errors) { ++ frame_desc->actual_length = 0; ++ frame_desc->status = -DWC_E_PROTOCOL; ++ } else { ++ frame_desc->status = 0; ++ frame_desc->actual_length = frame_desc->length; ++ } ++ qtd->isoc_frame_index++; ++ qtd->isoc_split_offset = 0; ++ if (qtd->isoc_frame_index == qtd->urb->packet_count) { ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); ++ } else { ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE); ++ } ++ } ++ break; ++ ++ case FIQ_PER_SPLIT_NYET_ABORTED: ++ /* Doh. lost the data. */ ++ printk_ratelimited(KERN_INFO "Transfer to device %d endpoint 0x%x frame %d failed " ++ "- FIQ reported NYET. Data may have been lost.\n", ++ hc->dev_addr, hc->ep_num, dwc_otg_hcd_get_frame_number(hcd) >> 3); ++ if (hc->ep_type == UE_ISOCHRONOUS) { ++ struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; ++ /* Record errors, update qtd. */ ++ frame_desc->actual_length = 0; ++ frame_desc->status = -DWC_E_PROTOCOL; ++ qtd->isoc_frame_index++; ++ qtd->isoc_split_offset = 0; ++ if (qtd->isoc_frame_index == qtd->urb->packet_count) { ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); ++ } else { ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE); ++ } ++ } else { ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS); ++ } ++ break; ++ ++ case FIQ_HS_ISOC_DONE: ++ /* The FIQ has performed a whole pile of isochronous transactions. ++ * The status is recorded as the interrupt state should the transaction ++ * fail. ++ */ ++ dwc_otg_fiq_unmangle_isoc(hcd, qh, qtd, num); ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); ++ break; ++ ++ case FIQ_PER_SPLIT_LS_ABORTED: ++ if (hcint.b.xacterr) { ++ /* Hub has responded with an ERR packet. Device ++ * has been unplugged or the port has been disabled. ++ * TODO: need to issue a reset to the hub port. */ ++ qtd->error_count += 3; ++ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.stall) { ++ handle_hc_stall_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.bblerr) { ++ handle_hc_babble_intr(hcd, hc, hc_regs, qtd); ++ } else { ++ printk_ratelimited(KERN_INFO "Transfer to device %d endpoint 0x%x failed " ++ "- FIQ reported FSM=%d. Data may have been lost.\n", ++ st->fsm, hc->dev_addr, hc->ep_num); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS); ++ } ++ break; ++ ++ case FIQ_PER_SPLIT_HS_ABORTED: ++ /* Either the SSPLIT phase suffered transaction errors or something ++ * unexpected happened. ++ */ ++ qtd->error_count += 3; ++ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS); ++ break; ++ ++ case FIQ_PER_SPLIT_TIMEOUT: ++ /* Couldn't complete in the nominated frame */ ++ printk(KERN_INFO "Transfer to device %d endpoint 0x%x frame %d failed " ++ "- FIQ timed out. Data may have been lost.\n", ++ hc->dev_addr, hc->ep_num, dwc_otg_hcd_get_frame_number(hcd) >> 3); ++ if (hc->ep_type == UE_ISOCHRONOUS) { ++ struct dwc_otg_hcd_iso_packet_desc *frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; ++ /* Record errors, update qtd. */ ++ frame_desc->actual_length = 0; ++ if (hc->ep_is_in) { ++ frame_desc->status = -DWC_E_NO_STREAM_RES; ++ } else { ++ frame_desc->status = -DWC_E_COMMUNICATION; ++ } ++ qtd->isoc_frame_index++; ++ if (qtd->isoc_frame_index == qtd->urb->packet_count) { ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); ++ } else { ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_COMPLETE); ++ } ++ } else { ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS); ++ } ++ break; ++ ++ default: ++ DWC_WARN("Unexpected state received on hc=%d fsm=%d on transfer to device %d ep 0x%x", ++ hc->hc_num, st->fsm, hc->dev_addr, hc->ep_num); ++ qtd->error_count++; ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS); ++ } ++ return; ++} ++ ++/** Handles interrupt for a specific Host Channel */ ++int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, uint32_t num) ++{ ++ int retval = 0; ++ hcint_data_t hcint; ++ hcintmsk_data_t hcintmsk; ++ dwc_hc_t *hc; ++ dwc_otg_hc_regs_t *hc_regs; ++ dwc_otg_qtd_t *qtd; ++ ++ DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", num); ++ ++ hc = dwc_otg_hcd->hc_ptr_array[num]; ++ hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[num]; ++ if(hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) { ++ /* We are responding to a channel disable. Driver ++ * state is cleared - our qtd has gone away. ++ */ ++ release_channel(dwc_otg_hcd, hc, NULL, hc->halt_status); ++ return 1; ++ } ++ qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list); ++ ++ /* ++ * FSM mode: Check to see if this is a HC interrupt from a channel handled by the FIQ. ++ * Execution path is fundamentally different for the channels after a FIQ has completed ++ * a split transaction. ++ */ ++ if (fiq_fsm_enable) { ++ switch (dwc_otg_hcd->fiq_state->channel[num].fsm) { ++ case FIQ_PASSTHROUGH: ++ break; ++ case FIQ_PASSTHROUGH_ERRORSTATE: ++ /* Hook into the error count */ ++ fiq_print(FIQDBG_ERR, dwc_otg_hcd->fiq_state, "HCDERR%02d", num); ++ if (!dwc_otg_hcd->fiq_state->channel[num].nr_errors) { ++ qtd->error_count = 0; ++ fiq_print(FIQDBG_ERR, dwc_otg_hcd->fiq_state, "RESET "); ++ } ++ break; ++ default: ++ dwc_otg_hcd_handle_hc_fsm(dwc_otg_hcd, num); ++ return 1; ++ } ++ } ++ ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); ++ hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk); ++ hcint.d32 = hcint.d32 & hcintmsk.d32; ++ if (!dwc_otg_hcd->core_if->dma_enable) { ++ if (hcint.b.chhltd && hcint.d32 != 0x2) { ++ hcint.b.chhltd = 0; ++ } ++ } ++ ++ if (hcint.b.xfercomp) { ++ retval |= ++ handle_hc_xfercomp_intr(dwc_otg_hcd, hc, hc_regs, qtd); ++ /* ++ * If NYET occurred at same time as Xfer Complete, the NYET is ++ * handled by the Xfer Complete interrupt handler. Don't want ++ * to call the NYET interrupt handler in this case. ++ */ ++ hcint.b.nyet = 0; ++ } ++ if (hcint.b.chhltd) { ++ retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd); ++ } ++ if (hcint.b.ahberr) { ++ retval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd); ++ } ++ if (hcint.b.stall) { ++ retval |= handle_hc_stall_intr(dwc_otg_hcd, hc, hc_regs, qtd); ++ } ++ if (hcint.b.nak) { ++ retval |= handle_hc_nak_intr(dwc_otg_hcd, hc, hc_regs, qtd); ++ } ++ if (hcint.b.ack) { ++ if(!hcint.b.chhltd) ++ retval |= handle_hc_ack_intr(dwc_otg_hcd, hc, hc_regs, qtd); ++ } ++ if (hcint.b.nyet) { ++ retval |= handle_hc_nyet_intr(dwc_otg_hcd, hc, hc_regs, qtd); ++ } ++ if (hcint.b.xacterr) { ++ retval |= handle_hc_xacterr_intr(dwc_otg_hcd, hc, hc_regs, qtd); ++ } ++ if (hcint.b.bblerr) { ++ retval |= handle_hc_babble_intr(dwc_otg_hcd, hc, hc_regs, qtd); ++ } ++ if (hcint.b.frmovrun) { ++ retval |= ++ handle_hc_frmovrun_intr(dwc_otg_hcd, hc, hc_regs, qtd); ++ } ++ if (hcint.b.datatglerr) { ++ retval |= ++ handle_hc_datatglerr_intr(dwc_otg_hcd, hc, hc_regs, qtd); ++ } ++ ++ return retval; ++} ++#endif /* DWC_DEVICE_ONLY */ +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c 2015-11-29 09:42:39.919098694 +0100 +@@ -0,0 +1,999 @@ ++ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_linux.c $ ++ * $Revision: #20 $ ++ * $Date: 2011/10/26 $ ++ * $Change: 1872981 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_DEVICE_ONLY ++ ++/** ++ * @file ++ * ++ * This file contains the implementation of the HCD. In Linux, the HCD ++ * implements the hc_driver API. ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) ++#include <../drivers/usb/core/hcd.h> ++#else ++#include ++#endif ++#include ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)) ++#define USB_URB_EP_LINKING 1 ++#else ++#define USB_URB_EP_LINKING 0 ++#endif ++ ++#include "dwc_otg_hcd_if.h" ++#include "dwc_otg_dbg.h" ++#include "dwc_otg_driver.h" ++#include "dwc_otg_hcd.h" ++ ++extern unsigned char _dwc_otg_fiq_stub, _dwc_otg_fiq_stub_end; ++ ++/** ++ * Gets the endpoint number from a _bEndpointAddress argument. The endpoint is ++ * qualified with its direction (possible 32 endpoints per device). ++ */ ++#define dwc_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \ ++ ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4) ++ ++static const char dwc_otg_hcd_name[] = "dwc_otg_hcd"; ++ ++extern bool fiq_enable; ++ ++/** @name Linux HC Driver API Functions */ ++/** @{ */ ++/* manage i/o requests, device state */ ++static int dwc_otg_urb_enqueue(struct usb_hcd *hcd, ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ++ struct usb_host_endpoint *ep, ++#endif ++ struct urb *urb, gfp_t mem_flags); ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ++static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb); ++#endif ++#else /* kernels at or post 2.6.30 */ ++static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, ++ struct urb *urb, int status); ++#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) */ ++ ++static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30) ++static void endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep); ++#endif ++static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd); ++extern int hcd_start(struct usb_hcd *hcd); ++extern void hcd_stop(struct usb_hcd *hcd); ++static int get_frame_number(struct usb_hcd *hcd); ++extern int hub_status_data(struct usb_hcd *hcd, char *buf); ++extern int hub_control(struct usb_hcd *hcd, ++ u16 typeReq, ++ u16 wValue, u16 wIndex, char *buf, u16 wLength); ++ ++struct wrapper_priv_data { ++ dwc_otg_hcd_t *dwc_otg_hcd; ++}; ++ ++/** @} */ ++ ++static struct hc_driver dwc_otg_hc_driver = { ++ ++ .description = dwc_otg_hcd_name, ++ .product_desc = "DWC OTG Controller", ++ .hcd_priv_size = sizeof(struct wrapper_priv_data), ++ ++ .irq = dwc_otg_hcd_irq, ++ ++ .flags = HCD_MEMORY | HCD_USB2, ++ ++ //.reset = ++ .start = hcd_start, ++ //.suspend = ++ //.resume = ++ .stop = hcd_stop, ++ ++ .urb_enqueue = dwc_otg_urb_enqueue, ++ .urb_dequeue = dwc_otg_urb_dequeue, ++ .endpoint_disable = endpoint_disable, ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30) ++ .endpoint_reset = endpoint_reset, ++#endif ++ .get_frame_number = get_frame_number, ++ ++ .hub_status_data = hub_status_data, ++ .hub_control = hub_control, ++ //.bus_suspend = ++ //.bus_resume = ++}; ++ ++/** Gets the dwc_otg_hcd from a struct usb_hcd */ ++static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd) ++{ ++ struct wrapper_priv_data *p; ++ p = (struct wrapper_priv_data *)(hcd->hcd_priv); ++ return p->dwc_otg_hcd; ++} ++ ++/** Gets the struct usb_hcd that contains a dwc_otg_hcd_t. */ ++static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t * dwc_otg_hcd) ++{ ++ return dwc_otg_hcd_get_priv_data(dwc_otg_hcd); ++} ++ ++/** Gets the usb_host_endpoint associated with an URB. */ ++inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *urb) ++{ ++ struct usb_device *dev = urb->dev; ++ int ep_num = usb_pipeendpoint(urb->pipe); ++ ++ if (usb_pipein(urb->pipe)) ++ return dev->ep_in[ep_num]; ++ else ++ return dev->ep_out[ep_num]; ++} ++ ++static int _disconnect(dwc_otg_hcd_t * hcd) ++{ ++ struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd); ++ ++ usb_hcd->self.is_b_host = 0; ++ return 0; ++} ++ ++static int _start(dwc_otg_hcd_t * hcd) ++{ ++ struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd); ++ ++ usb_hcd->self.is_b_host = dwc_otg_hcd_is_b_host(hcd); ++ hcd_start(usb_hcd); ++ ++ return 0; ++} ++ ++static int _hub_info(dwc_otg_hcd_t * hcd, void *urb_handle, uint32_t * hub_addr, ++ uint32_t * port_addr) ++{ ++ struct urb *urb = (struct urb *)urb_handle; ++ struct usb_bus *bus; ++#if 1 //GRAYG - temporary ++ if (NULL == urb_handle) ++ DWC_ERROR("**** %s - NULL URB handle\n", __func__);//GRAYG ++ if (NULL == urb->dev) ++ DWC_ERROR("**** %s - URB has no device\n", __func__);//GRAYG ++ if (NULL == port_addr) ++ DWC_ERROR("**** %s - NULL port_address\n", __func__);//GRAYG ++#endif ++ if (urb->dev->tt) { ++ if (NULL == urb->dev->tt->hub) { ++ DWC_ERROR("**** %s - (URB's transactor has no TT - giving no hub)\n", ++ __func__); //GRAYG ++ //*hub_addr = (u8)usb_pipedevice(urb->pipe); //GRAYG ++ *hub_addr = 0; //GRAYG ++ // we probably shouldn't have a transaction translator if ++ // there's no associated hub? ++ } else { ++ bus = hcd_to_bus(dwc_otg_hcd_to_hcd(hcd)); ++ if (urb->dev->tt->hub == bus->root_hub) ++ *hub_addr = 0; ++ else ++ *hub_addr = urb->dev->tt->hub->devnum; ++ } ++ *port_addr = urb->dev->tt->multi ? urb->dev->ttport : 1; ++ } else { ++ *hub_addr = 0; ++ *port_addr = urb->dev->ttport; ++ } ++ return 0; ++} ++ ++static int _speed(dwc_otg_hcd_t * hcd, void *urb_handle) ++{ ++ struct urb *urb = (struct urb *)urb_handle; ++ return urb->dev->speed; ++} ++ ++static int _get_b_hnp_enable(dwc_otg_hcd_t * hcd) ++{ ++ struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd); ++ return usb_hcd->self.b_hnp_enable; ++} ++ ++static void allocate_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw, ++ struct urb *urb) ++{ ++ hcd_to_bus(hcd)->bandwidth_allocated += bw / urb->interval; ++ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { ++ hcd_to_bus(hcd)->bandwidth_isoc_reqs++; ++ } else { ++ hcd_to_bus(hcd)->bandwidth_int_reqs++; ++ } ++} ++ ++static void free_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw, ++ struct urb *urb) ++{ ++ hcd_to_bus(hcd)->bandwidth_allocated -= bw / urb->interval; ++ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { ++ hcd_to_bus(hcd)->bandwidth_isoc_reqs--; ++ } else { ++ hcd_to_bus(hcd)->bandwidth_int_reqs--; ++ } ++} ++ ++/** ++ * Sets the final status of an URB and returns it to the device driver. Any ++ * required cleanup of the URB is performed. The HCD lock should be held on ++ * entry. ++ */ ++static int _complete(dwc_otg_hcd_t * hcd, void *urb_handle, ++ dwc_otg_hcd_urb_t * dwc_otg_urb, int32_t status) ++{ ++ struct urb *urb = (struct urb *)urb_handle; ++ urb_tq_entry_t *new_entry; ++ int rc = 0; ++ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { ++ DWC_PRINTF("%s: urb %p, device %d, ep %d %s, status=%d\n", ++ __func__, urb, usb_pipedevice(urb->pipe), ++ usb_pipeendpoint(urb->pipe), ++ usb_pipein(urb->pipe) ? "IN" : "OUT", status); ++ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { ++ int i; ++ for (i = 0; i < urb->number_of_packets; i++) { ++ DWC_PRINTF(" ISO Desc %d status: %d\n", ++ i, urb->iso_frame_desc[i].status); ++ } ++ } ++ } ++ new_entry = DWC_ALLOC_ATOMIC(sizeof(urb_tq_entry_t)); ++ urb->actual_length = dwc_otg_hcd_urb_get_actual_length(dwc_otg_urb); ++ /* Convert status value. */ ++ switch (status) { ++ case -DWC_E_PROTOCOL: ++ status = -EPROTO; ++ break; ++ case -DWC_E_IN_PROGRESS: ++ status = -EINPROGRESS; ++ break; ++ case -DWC_E_PIPE: ++ status = -EPIPE; ++ break; ++ case -DWC_E_IO: ++ status = -EIO; ++ break; ++ case -DWC_E_TIMEOUT: ++ status = -ETIMEDOUT; ++ break; ++ case -DWC_E_OVERFLOW: ++ status = -EOVERFLOW; ++ break; ++ case -DWC_E_SHUTDOWN: ++ status = -ESHUTDOWN; ++ break; ++ default: ++ if (status) { ++ DWC_PRINTF("Uknown urb status %d\n", status); ++ ++ } ++ } ++ ++ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { ++ int i; ++ ++ urb->error_count = dwc_otg_hcd_urb_get_error_count(dwc_otg_urb); ++ for (i = 0; i < urb->number_of_packets; ++i) { ++ urb->iso_frame_desc[i].actual_length = ++ dwc_otg_hcd_urb_get_iso_desc_actual_length ++ (dwc_otg_urb, i); ++ urb->iso_frame_desc[i].status = ++ dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_urb, i); ++ } ++ } ++ ++ urb->status = status; ++ urb->hcpriv = NULL; ++ if (!status) { ++ if ((urb->transfer_flags & URB_SHORT_NOT_OK) && ++ (urb->actual_length < urb->transfer_buffer_length)) { ++ urb->status = -EREMOTEIO; ++ } ++ } ++ ++ if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) || ++ (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) { ++ struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb); ++ if (ep) { ++ free_bus_bandwidth(dwc_otg_hcd_to_hcd(hcd), ++ dwc_otg_hcd_get_ep_bandwidth(hcd, ++ ep->hcpriv), ++ urb); ++ } ++ } ++ DWC_FREE(dwc_otg_urb); ++ if (!new_entry) { ++ DWC_ERROR("dwc_otg_hcd: complete: cannot allocate URB TQ entry\n"); ++ urb->status = -EPROTO; ++ /* don't schedule the tasklet - ++ * directly return the packet here with error. */ ++#if USB_URB_EP_LINKING ++ usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(hcd), urb); ++#endif ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ++ usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb); ++#else ++ usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb, urb->status); ++#endif ++ } else { ++ new_entry->urb = urb; ++#if USB_URB_EP_LINKING ++ rc = usb_hcd_check_unlink_urb(dwc_otg_hcd_to_hcd(hcd), urb, urb->status); ++ if(0 == rc) { ++ usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(hcd), urb); ++ } ++#endif ++ if(0 == rc) { ++ DWC_TAILQ_INSERT_TAIL(&hcd->completed_urb_list, new_entry, ++ urb_tq_entries); ++ DWC_TASK_HI_SCHEDULE(hcd->completion_tasklet); ++ } ++ } ++ return 0; ++} ++ ++static struct dwc_otg_hcd_function_ops hcd_fops = { ++ .start = _start, ++ .disconnect = _disconnect, ++ .hub_info = _hub_info, ++ .speed = _speed, ++ .complete = _complete, ++ .get_b_hnp_enable = _get_b_hnp_enable, ++}; ++ ++static struct fiq_handler fh = { ++ .name = "usb_fiq", ++}; ++ ++static void hcd_init_fiq(void *cookie) ++{ ++ dwc_otg_device_t *otg_dev = cookie; ++ dwc_otg_hcd_t *dwc_otg_hcd = otg_dev->hcd; ++ struct pt_regs regs; ++ ++ if (claim_fiq(&fh)) { ++ DWC_ERROR("Can't claim FIQ"); ++ BUG(); ++ } ++ DWC_WARN("FIQ on core %d at 0x%08x", ++ smp_processor_id(), ++ (fiq_fsm_enable ? (int)&dwc_otg_fiq_fsm : (int)&dwc_otg_fiq_nop)); ++ DWC_WARN("FIQ ASM at 0x%08x length %d", (int)&_dwc_otg_fiq_stub, (int)(&_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub)); ++ set_fiq_handler((void *) &_dwc_otg_fiq_stub, &_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub); ++ memset(®s,0,sizeof(regs)); ++ ++ regs.ARM_r8 = (long) dwc_otg_hcd->fiq_state; ++ if (fiq_fsm_enable) { ++ regs.ARM_r9 = dwc_otg_hcd->core_if->core_params->host_channels; ++ //regs.ARM_r10 = dwc_otg_hcd->dma; ++ regs.ARM_fp = (long) dwc_otg_fiq_fsm; ++ } else { ++ regs.ARM_fp = (long) dwc_otg_fiq_nop; ++ } ++ ++ regs.ARM_sp = (long) dwc_otg_hcd->fiq_stack + (sizeof(struct fiq_stack) - 4); ++ ++// __show_regs(®s); ++ set_fiq_regs(®s); ++ ++ //Set the mphi periph to the required registers ++ dwc_otg_hcd->fiq_state->mphi_regs.base = otg_dev->os_dep.mphi_base; ++ dwc_otg_hcd->fiq_state->mphi_regs.ctrl = otg_dev->os_dep.mphi_base + 0x4c; ++ dwc_otg_hcd->fiq_state->mphi_regs.outdda = otg_dev->os_dep.mphi_base + 0x28; ++ dwc_otg_hcd->fiq_state->mphi_regs.outddb = otg_dev->os_dep.mphi_base + 0x2c; ++ dwc_otg_hcd->fiq_state->mphi_regs.intstat = otg_dev->os_dep.mphi_base + 0x50; ++ dwc_otg_hcd->fiq_state->dwc_regs_base = otg_dev->os_dep.base; ++ DWC_WARN("MPHI regs_base at 0x%08x", (int)dwc_otg_hcd->fiq_state->mphi_regs.base); ++ //Enable mphi peripheral ++ writel((1<<31),dwc_otg_hcd->fiq_state->mphi_regs.ctrl); ++#ifdef DEBUG ++ if (readl(dwc_otg_hcd->fiq_state->mphi_regs.ctrl) & 0x80000000) ++ DWC_WARN("MPHI periph has been enabled"); ++ else ++ DWC_WARN("MPHI periph has NOT been enabled"); ++#endif ++ // Enable FIQ interrupt from USB peripheral ++#ifdef CONFIG_ARCH_BCM2835 ++ enable_fiq(platform_get_irq(otg_dev->os_dep.platformdev, 1)); ++#else ++ enable_fiq(INTERRUPT_VC_USB); ++#endif ++ local_fiq_enable(); ++} ++ ++/** ++ * Initializes the HCD. This function allocates memory for and initializes the ++ * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the ++ * USB bus with the core and calls the hc_driver->start() function. It returns ++ * a negative error on failure. ++ */ ++int hcd_init(dwc_bus_dev_t *_dev) ++{ ++ struct usb_hcd *hcd = NULL; ++ dwc_otg_hcd_t *dwc_otg_hcd = NULL; ++ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev); ++ int retval = 0; ++ u64 dmamask; ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT otg_dev=%p\n", otg_dev); ++ ++ /* Set device flags indicating whether the HCD supports DMA. */ ++ if (dwc_otg_is_dma_enable(otg_dev->core_if)) ++ dmamask = DMA_BIT_MASK(32); ++ else ++ dmamask = 0; ++ ++#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE) ++ dma_set_mask(&_dev->dev, dmamask); ++ dma_set_coherent_mask(&_dev->dev, dmamask); ++#elif defined(PCI_INTERFACE) ++ pci_set_dma_mask(_dev, dmamask); ++ pci_set_consistent_dma_mask(_dev, dmamask); ++#endif ++ ++ /* ++ * Allocate memory for the base HCD plus the DWC OTG HCD. ++ * Initialize the base HCD. ++ */ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) ++ hcd = usb_create_hcd(&dwc_otg_hc_driver, &_dev->dev, _dev->dev.bus_id); ++#else ++ hcd = usb_create_hcd(&dwc_otg_hc_driver, &_dev->dev, dev_name(&_dev->dev)); ++ hcd->has_tt = 1; ++// hcd->uses_new_polling = 1; ++// hcd->poll_rh = 0; ++#endif ++ if (!hcd) { ++ retval = -ENOMEM; ++ goto error1; ++ } ++ ++ hcd->regs = otg_dev->os_dep.base; ++ ++ ++ /* Initialize the DWC OTG HCD. */ ++ dwc_otg_hcd = dwc_otg_hcd_alloc_hcd(); ++ if (!dwc_otg_hcd) { ++ goto error2; ++ } ++ ((struct wrapper_priv_data *)(hcd->hcd_priv))->dwc_otg_hcd = ++ dwc_otg_hcd; ++ otg_dev->hcd = dwc_otg_hcd; ++ ++ if (dwc_otg_hcd_init(dwc_otg_hcd, otg_dev->core_if)) { ++ goto error2; ++ } ++ ++ if (fiq_enable) { ++ if (num_online_cpus() > 1) { ++ /* bcm2709: can run the FIQ on a separate core to IRQs */ ++ smp_call_function_single(1, hcd_init_fiq, otg_dev, 1); ++ } else { ++ smp_call_function_single(0, hcd_init_fiq, otg_dev, 1); ++ } ++ } ++ ++ otg_dev->hcd->otg_dev = otg_dev; ++ hcd->self.otg_port = dwc_otg_hcd_otg_port(dwc_otg_hcd); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,33) //don't support for LM(with 2.6.20.1 kernel) ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) //version field absent later ++ hcd->self.otg_version = dwc_otg_get_otg_version(otg_dev->core_if); ++#endif ++ /* Don't support SG list at this point */ ++ hcd->self.sg_tablesize = 0; ++#endif ++ /* ++ * Finish generic HCD initialization and start the HCD. This function ++ * allocates the DMA buffer pool, registers the USB bus, requests the ++ * IRQ line, and calls hcd_start method. ++ */ ++#ifdef PLATFORM_INTERFACE ++ retval = usb_add_hcd(hcd, platform_get_irq(_dev, fiq_enable ? 0 : 1), IRQF_SHARED); ++#else ++ retval = usb_add_hcd(hcd, _dev->irq, IRQF_SHARED); ++#endif ++ if (retval < 0) { ++ goto error2; ++ } ++ ++ dwc_otg_hcd_set_priv_data(dwc_otg_hcd, hcd); ++ return 0; ++ ++error2: ++ usb_put_hcd(hcd); ++error1: ++ return retval; ++} ++ ++/** ++ * Removes the HCD. ++ * Frees memory and resources associated with the HCD and deregisters the bus. ++ */ ++void hcd_remove(dwc_bus_dev_t *_dev) ++{ ++ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev); ++ dwc_otg_hcd_t *dwc_otg_hcd; ++ struct usb_hcd *hcd; ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE otg_dev=%p\n", otg_dev); ++ ++ if (!otg_dev) { ++ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__); ++ return; ++ } ++ ++ dwc_otg_hcd = otg_dev->hcd; ++ ++ if (!dwc_otg_hcd) { ++ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__); ++ return; ++ } ++ ++ hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd); ++ ++ if (!hcd) { ++ DWC_DEBUGPL(DBG_ANY, ++ "%s: dwc_otg_hcd_to_hcd(dwc_otg_hcd) NULL!\n", ++ __func__); ++ return; ++ } ++ usb_remove_hcd(hcd); ++ dwc_otg_hcd_set_priv_data(dwc_otg_hcd, NULL); ++ dwc_otg_hcd_remove(dwc_otg_hcd); ++ usb_put_hcd(hcd); ++} ++ ++/* ========================================================================= ++ * Linux HC Driver Functions ++ * ========================================================================= */ ++ ++/** Initializes the DWC_otg controller and its root hub and prepares it for host ++ * mode operation. Activates the root port. Returns 0 on success and a negative ++ * error code on failure. */ ++int hcd_start(struct usb_hcd *hcd) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); ++ struct usb_bus *bus; ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n"); ++ bus = hcd_to_bus(hcd); ++ ++ hcd->state = HC_STATE_RUNNING; ++ if (dwc_otg_hcd_start(dwc_otg_hcd, &hcd_fops)) { ++ return 0; ++ } ++ ++ /* Initialize and connect root hub if one is not already attached */ ++ if (bus->root_hub) { ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n"); ++ /* Inform the HUB driver to resume. */ ++ usb_hcd_resume_root_hub(hcd); ++ } ++ ++ return 0; ++} ++ ++/** ++ * Halts the DWC_otg host mode operations in a clean manner. USB transfers are ++ * stopped. ++ */ ++void hcd_stop(struct usb_hcd *hcd) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); ++ ++ dwc_otg_hcd_stop(dwc_otg_hcd); ++} ++ ++/** Returns the current frame number. */ ++static int get_frame_number(struct usb_hcd *hcd) ++{ ++ hprt0_data_t hprt0; ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); ++ hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0); ++ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) ++ return dwc_otg_hcd_get_frame_number(dwc_otg_hcd) >> 3; ++ else ++ return dwc_otg_hcd_get_frame_number(dwc_otg_hcd); ++} ++ ++#ifdef DEBUG ++static void dump_urb_info(struct urb *urb, char *fn_name) ++{ ++ DWC_PRINTF("%s, urb %p\n", fn_name, urb); ++ DWC_PRINTF(" Device address: %d\n", usb_pipedevice(urb->pipe)); ++ DWC_PRINTF(" Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe), ++ (usb_pipein(urb->pipe) ? "IN" : "OUT")); ++ DWC_PRINTF(" Endpoint type: %s\n", ( { ++ char *pipetype; ++ switch (usb_pipetype(urb->pipe)) { ++case PIPE_CONTROL: ++pipetype = "CONTROL"; break; case PIPE_BULK: ++pipetype = "BULK"; break; case PIPE_INTERRUPT: ++pipetype = "INTERRUPT"; break; case PIPE_ISOCHRONOUS: ++pipetype = "ISOCHRONOUS"; break; default: ++ pipetype = "UNKNOWN"; break;}; ++ pipetype;} ++ )) ; ++ DWC_PRINTF(" Speed: %s\n", ( { ++ char *speed; switch (urb->dev->speed) { ++case USB_SPEED_HIGH: ++speed = "HIGH"; break; case USB_SPEED_FULL: ++speed = "FULL"; break; case USB_SPEED_LOW: ++speed = "LOW"; break; default: ++ speed = "UNKNOWN"; break;}; ++ speed;} ++ )) ; ++ DWC_PRINTF(" Max packet size: %d\n", ++ usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); ++ DWC_PRINTF(" Data buffer length: %d\n", urb->transfer_buffer_length); ++ DWC_PRINTF(" Transfer buffer: %p, Transfer DMA: %p\n", ++ urb->transfer_buffer, (void *)urb->transfer_dma); ++ DWC_PRINTF(" Setup buffer: %p, Setup DMA: %p\n", ++ urb->setup_packet, (void *)urb->setup_dma); ++ DWC_PRINTF(" Interval: %d\n", urb->interval); ++ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { ++ int i; ++ for (i = 0; i < urb->number_of_packets; i++) { ++ DWC_PRINTF(" ISO Desc %d:\n", i); ++ DWC_PRINTF(" offset: %d, length %d\n", ++ urb->iso_frame_desc[i].offset, ++ urb->iso_frame_desc[i].length); ++ } ++ } ++} ++#endif ++ ++/** Starts processing a USB transfer request specified by a USB Request Block ++ * (URB). mem_flags indicates the type of memory allocation to use while ++ * processing this URB. */ ++static int dwc_otg_urb_enqueue(struct usb_hcd *hcd, ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ++ struct usb_host_endpoint *ep, ++#endif ++ struct urb *urb, gfp_t mem_flags) ++{ ++ int retval = 0; ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28) ++ struct usb_host_endpoint *ep = urb->ep; ++#endif ++ dwc_irqflags_t irqflags; ++ void **ref_ep_hcpriv = &ep->hcpriv; ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); ++ dwc_otg_hcd_urb_t *dwc_otg_urb; ++ int i; ++ int alloc_bandwidth = 0; ++ uint8_t ep_type = 0; ++ uint32_t flags = 0; ++ void *buf; ++ ++#ifdef DEBUG ++ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { ++ dump_urb_info(urb, "dwc_otg_urb_enqueue"); ++ } ++#endif ++ ++ if (!urb->transfer_buffer && urb->transfer_buffer_length) ++ return -EINVAL; ++ ++ if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) ++ || (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) { ++ if (!dwc_otg_hcd_is_bandwidth_allocated ++ (dwc_otg_hcd, ref_ep_hcpriv)) { ++ alloc_bandwidth = 1; ++ } ++ } ++ ++ switch (usb_pipetype(urb->pipe)) { ++ case PIPE_CONTROL: ++ ep_type = USB_ENDPOINT_XFER_CONTROL; ++ break; ++ case PIPE_ISOCHRONOUS: ++ ep_type = USB_ENDPOINT_XFER_ISOC; ++ break; ++ case PIPE_BULK: ++ ep_type = USB_ENDPOINT_XFER_BULK; ++ break; ++ case PIPE_INTERRUPT: ++ ep_type = USB_ENDPOINT_XFER_INT; ++ break; ++ default: ++ DWC_WARN("Wrong EP type - %d\n", usb_pipetype(urb->pipe)); ++ } ++ ++ /* # of packets is often 0 - do we really need to call this then? */ ++ dwc_otg_urb = dwc_otg_hcd_urb_alloc(dwc_otg_hcd, ++ urb->number_of_packets, ++ mem_flags == GFP_ATOMIC ? 1 : 0); ++ ++ if(dwc_otg_urb == NULL) ++ return -ENOMEM; ++ ++ if (!dwc_otg_urb && urb->number_of_packets) ++ return -ENOMEM; ++ ++ dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_urb, usb_pipedevice(urb->pipe), ++ usb_pipeendpoint(urb->pipe), ep_type, ++ usb_pipein(urb->pipe), ++ usb_maxpacket(urb->dev, urb->pipe, ++ !(usb_pipein(urb->pipe)))); ++ ++ buf = urb->transfer_buffer; ++ if (hcd->self.uses_dma && !buf && urb->transfer_buffer_length) { ++ /* ++ * Calculate virtual address from physical address, ++ * because some class driver may not fill transfer_buffer. ++ * In Buffer DMA mode virual address is used, ++ * when handling non DWORD aligned buffers. ++ */ ++ buf = (void *)__bus_to_virt((unsigned long)urb->transfer_dma); ++ dev_warn_once(&urb->dev->dev, ++ "USB transfer_buffer was NULL, will use __bus_to_virt(%pad)=%p\n", ++ &urb->transfer_dma, buf); ++ } ++ ++ if (!(urb->transfer_flags & URB_NO_INTERRUPT)) ++ flags |= URB_GIVEBACK_ASAP; ++ if (urb->transfer_flags & URB_ZERO_PACKET) ++ flags |= URB_SEND_ZERO_PACKET; ++ ++ dwc_otg_hcd_urb_set_params(dwc_otg_urb, urb, buf, ++ urb->transfer_dma, ++ urb->transfer_buffer_length, ++ urb->setup_packet, ++ urb->setup_dma, flags, urb->interval); ++ ++ for (i = 0; i < urb->number_of_packets; ++i) { ++ dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_urb, i, ++ urb-> ++ iso_frame_desc[i].offset, ++ urb-> ++ iso_frame_desc[i].length); ++ } ++ ++ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &irqflags); ++ urb->hcpriv = dwc_otg_urb; ++#if USB_URB_EP_LINKING ++ retval = usb_hcd_link_urb_to_ep(hcd, urb); ++ if (0 == retval) ++#endif ++ { ++ retval = dwc_otg_hcd_urb_enqueue(dwc_otg_hcd, dwc_otg_urb, ++ /*(dwc_otg_qh_t **)*/ ++ ref_ep_hcpriv, 1); ++ if (0 == retval) { ++ if (alloc_bandwidth) { ++ allocate_bus_bandwidth(hcd, ++ dwc_otg_hcd_get_ep_bandwidth( ++ dwc_otg_hcd, *ref_ep_hcpriv), ++ urb); ++ } ++ } else { ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG dwc_otg_hcd_urb_enqueue failed rc %d\n", retval); ++#if USB_URB_EP_LINKING ++ usb_hcd_unlink_urb_from_ep(hcd, urb); ++#endif ++ DWC_FREE(dwc_otg_urb); ++ urb->hcpriv = NULL; ++ if (retval == -DWC_E_NO_DEVICE) ++ retval = -ENODEV; ++ } ++ } ++#if USB_URB_EP_LINKING ++ else ++ { ++ DWC_FREE(dwc_otg_urb); ++ urb->hcpriv = NULL; ++ } ++#endif ++ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, irqflags); ++ return retval; ++} ++ ++/** Aborts/cancels a USB transfer request. Always returns 0 to indicate ++ * success. */ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ++static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb) ++#else ++static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) ++#endif ++{ ++ dwc_irqflags_t flags; ++ dwc_otg_hcd_t *dwc_otg_hcd; ++ int rc; ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n"); ++ ++ dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); ++ ++#ifdef DEBUG ++ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { ++ dump_urb_info(urb, "dwc_otg_urb_dequeue"); ++ } ++#endif ++ ++ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags); ++ rc = usb_hcd_check_unlink_urb(hcd, urb, status); ++ if (0 == rc) { ++ if(urb->hcpriv != NULL) { ++ dwc_otg_hcd_urb_dequeue(dwc_otg_hcd, ++ (dwc_otg_hcd_urb_t *)urb->hcpriv); ++ ++ DWC_FREE(urb->hcpriv); ++ urb->hcpriv = NULL; ++ } ++ } ++ ++ if (0 == rc) { ++ /* Higher layer software sets URB status. */ ++#if USB_URB_EP_LINKING ++ usb_hcd_unlink_urb_from_ep(hcd, urb); ++#endif ++ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags); ++ ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ++ usb_hcd_giveback_urb(hcd, urb); ++#else ++ usb_hcd_giveback_urb(hcd, urb, status); ++#endif ++ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { ++ DWC_PRINTF("Called usb_hcd_giveback_urb() \n"); ++ DWC_PRINTF(" 1urb->status = %d\n", urb->status); ++ } ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue OK\n"); ++ } else { ++ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags); ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue failed - rc %d\n", ++ rc); ++ } ++ ++ return rc; ++} ++ ++/* Frees resources in the DWC_otg controller related to a given endpoint. Also ++ * clears state in the HCD related to the endpoint. Any URBs for the endpoint ++ * must already be dequeued. */ ++static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); ++ ++ DWC_DEBUGPL(DBG_HCD, ++ "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, " ++ "endpoint=%d\n", ep->desc.bEndpointAddress, ++ dwc_ep_addr_to_endpoint(ep->desc.bEndpointAddress)); ++ dwc_otg_hcd_endpoint_disable(dwc_otg_hcd, ep->hcpriv, 250); ++ ep->hcpriv = NULL; ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30) ++/* Resets endpoint specific parameter values, in current version used to reset ++ * the data toggle(as a WA). This function can be called from usb_clear_halt routine */ ++static void endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep) ++{ ++ dwc_irqflags_t flags; ++ struct usb_device *udev = NULL; ++ int epnum = usb_endpoint_num(&ep->desc); ++ int is_out = usb_endpoint_dir_out(&ep->desc); ++ int is_control = usb_endpoint_xfer_control(&ep->desc); ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); ++ struct device *dev = DWC_OTG_OS_GETDEV(dwc_otg_hcd->otg_dev->os_dep); ++ ++ if (dev) ++ udev = to_usb_device(dev); ++ else ++ return; ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP RESET: Endpoint Num=0x%02d\n", epnum); ++ ++ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags); ++ usb_settoggle(udev, epnum, is_out, 0); ++ if (is_control) ++ usb_settoggle(udev, epnum, !is_out, 0); ++ ++ if (ep->hcpriv) { ++ dwc_otg_hcd_endpoint_reset(dwc_otg_hcd, ep->hcpriv); ++ } ++ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags); ++} ++#endif ++ ++/** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if ++ * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid ++ * interrupt. ++ * ++ * This function is called by the USB core when an interrupt occurs */ ++static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); ++ int32_t retval = dwc_otg_hcd_handle_intr(dwc_otg_hcd); ++ if (retval != 0) { ++ S3C2410X_CLEAR_EINTPEND(); ++ } ++ return IRQ_RETVAL(retval); ++} ++ ++/** Creates Status Change bitmap for the root hub and root port. The bitmap is ++ * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 ++ * is the status change indicator for the single root port. Returns 1 if either ++ * change indicator is 1, otherwise returns 0. */ ++int hub_status_data(struct usb_hcd *hcd, char *buf) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); ++ ++ buf[0] = 0; ++ buf[0] |= (dwc_otg_hcd_is_status_changed(dwc_otg_hcd, 1)) << 1; ++ ++ return (buf[0] != 0); ++} ++ ++/** Handles hub class-specific requests. */ ++int hub_control(struct usb_hcd *hcd, ++ u16 typeReq, u16 wValue, u16 wIndex, char *buf, u16 wLength) ++{ ++ int retval; ++ ++ retval = dwc_otg_hcd_hub_control(hcd_to_dwc_otg_hcd(hcd), ++ typeReq, wValue, wIndex, buf, wLength); ++ ++ switch (retval) { ++ case -DWC_E_INVALID: ++ retval = -EINVAL; ++ break; ++ } ++ ++ return retval; ++} ++ ++#endif /* DWC_DEVICE_ONLY */ +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c 2015-11-29 09:42:39.919098694 +0100 +@@ -0,0 +1,957 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_queue.c $ ++ * $Revision: #44 $ ++ * $Date: 2011/10/26 $ ++ * $Change: 1873028 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_DEVICE_ONLY ++ ++/** ++ * @file ++ * ++ * This file contains the functions to manage Queue Heads and Queue ++ * Transfer Descriptors. ++ */ ++ ++#include "dwc_otg_hcd.h" ++#include "dwc_otg_regs.h" ++ ++extern bool microframe_schedule; ++ ++/** ++ * Free each QTD in the QH's QTD-list then free the QH. QH should already be ++ * removed from a list. QTD list should already be empty if called from URB ++ * Dequeue. ++ * ++ * @param hcd HCD instance. ++ * @param qh The QH to free. ++ */ ++void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ dwc_otg_qtd_t *qtd, *qtd_tmp; ++ dwc_irqflags_t flags; ++ ++ /* Free each QTD in the QTD list */ ++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); ++ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) { ++ DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry); ++ dwc_otg_hcd_qtd_free(qtd); ++ } ++ ++ if (hcd->core_if->dma_desc_enable) { ++ dwc_otg_hcd_qh_free_ddma(hcd, qh); ++ } else if (qh->dw_align_buf) { ++ uint32_t buf_size; ++ if (qh->ep_type == UE_ISOCHRONOUS) { ++ buf_size = 4096; ++ } else { ++ buf_size = hcd->core_if->core_params->max_transfer_size; ++ } ++ DWC_DMA_FREE(buf_size, qh->dw_align_buf, qh->dw_align_buf_dma); ++ } ++ ++ DWC_FREE(qh); ++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); ++ return; ++} ++ ++#define BitStuffTime(bytecount) ((8 * 7* bytecount) / 6) ++#define HS_HOST_DELAY 5 /* nanoseconds */ ++#define FS_LS_HOST_DELAY 1000 /* nanoseconds */ ++#define HUB_LS_SETUP 333 /* nanoseconds */ ++#define NS_TO_US(ns) ((ns + 500) / 1000) ++ /* convert & round nanoseconds to microseconds */ ++ ++static uint32_t calc_bus_time(int speed, int is_in, int is_isoc, int bytecount) ++{ ++ unsigned long retval; ++ ++ switch (speed) { ++ case USB_SPEED_HIGH: ++ if (is_isoc) { ++ retval = ++ ((38 * 8 * 2083) + ++ (2083 * (3 + BitStuffTime(bytecount)))) / 1000 + ++ HS_HOST_DELAY; ++ } else { ++ retval = ++ ((55 * 8 * 2083) + ++ (2083 * (3 + BitStuffTime(bytecount)))) / 1000 + ++ HS_HOST_DELAY; ++ } ++ break; ++ case USB_SPEED_FULL: ++ if (is_isoc) { ++ retval = ++ (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000; ++ if (is_in) { ++ retval = 7268 + FS_LS_HOST_DELAY + retval; ++ } else { ++ retval = 6265 + FS_LS_HOST_DELAY + retval; ++ } ++ } else { ++ retval = ++ (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000; ++ retval = 9107 + FS_LS_HOST_DELAY + retval; ++ } ++ break; ++ case USB_SPEED_LOW: ++ if (is_in) { ++ retval = ++ (67667 * (31 + 10 * BitStuffTime(bytecount))) / ++ 1000; ++ retval = ++ 64060 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY + ++ retval; ++ } else { ++ retval = ++ (66700 * (31 + 10 * BitStuffTime(bytecount))) / ++ 1000; ++ retval = ++ 64107 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY + ++ retval; ++ } ++ break; ++ default: ++ DWC_WARN("Unknown device speed\n"); ++ retval = -1; ++ } ++ ++ return NS_TO_US(retval); ++} ++ ++/** ++ * Initializes a QH structure. ++ * ++ * @param hcd The HCD state structure for the DWC OTG controller. ++ * @param qh The QH to init. ++ * @param urb Holds the information about the device/endpoint that we need ++ * to initialize the QH. ++ */ ++#define SCHEDULE_SLOP 10 ++void qh_init(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, dwc_otg_hcd_urb_t * urb) ++{ ++ char *speed, *type; ++ int dev_speed; ++ uint32_t hub_addr, hub_port; ++ ++ dwc_memset(qh, 0, sizeof(dwc_otg_qh_t)); ++ ++ /* Initialize QH */ ++ qh->ep_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info); ++ qh->ep_is_in = dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0; ++ ++ qh->data_toggle = DWC_OTG_HC_PID_DATA0; ++ qh->maxp = dwc_otg_hcd_get_mps(&urb->pipe_info); ++ DWC_CIRCLEQ_INIT(&qh->qtd_list); ++ DWC_LIST_INIT(&qh->qh_list_entry); ++ qh->channel = NULL; ++ ++ /* FS/LS Enpoint on HS Hub ++ * NOT virtual root hub */ ++ dev_speed = hcd->fops->speed(hcd, urb->priv); ++ ++ hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &hub_port); ++ qh->do_split = 0; ++ if (microframe_schedule) ++ qh->speed = dev_speed; ++ ++ qh->nak_frame = 0xffff; ++ ++ if (((dev_speed == USB_SPEED_LOW) || ++ (dev_speed == USB_SPEED_FULL)) && ++ (hub_addr != 0 && hub_addr != 1)) { ++ DWC_DEBUGPL(DBG_HCD, ++ "QH init: EP %d: TT found at hub addr %d, for port %d\n", ++ dwc_otg_hcd_get_ep_num(&urb->pipe_info), hub_addr, ++ hub_port); ++ qh->do_split = 1; ++ qh->skip_count = 0; ++ } ++ ++ if (qh->ep_type == UE_INTERRUPT || qh->ep_type == UE_ISOCHRONOUS) { ++ /* Compute scheduling parameters once and save them. */ ++ hprt0_data_t hprt; ++ ++ /** @todo Account for split transfers in the bus time. */ ++ int bytecount = ++ dwc_hb_mult(qh->maxp) * dwc_max_packet(qh->maxp); ++ ++ qh->usecs = ++ calc_bus_time((qh->do_split ? USB_SPEED_HIGH : dev_speed), ++ qh->ep_is_in, (qh->ep_type == UE_ISOCHRONOUS), ++ bytecount); ++ /* Start in a slightly future (micro)frame. */ ++ qh->sched_frame = dwc_frame_num_inc(hcd->frame_number, ++ SCHEDULE_SLOP); ++ qh->interval = urb->interval; ++ ++#if 0 ++ /* Increase interrupt polling rate for debugging. */ ++ if (qh->ep_type == UE_INTERRUPT) { ++ qh->interval = 8; ++ } ++#endif ++ hprt.d32 = DWC_READ_REG32(hcd->core_if->host_if->hprt0); ++ if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) && ++ ((dev_speed == USB_SPEED_LOW) || ++ (dev_speed == USB_SPEED_FULL))) { ++ qh->interval *= 8; ++ qh->sched_frame |= 0x7; ++ qh->start_split_frame = qh->sched_frame; ++ } ++ ++ } ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n"); ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - qh = %p\n", qh); ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Device Address = %d\n", ++ dwc_otg_hcd_get_dev_addr(&urb->pipe_info)); ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Endpoint %d, %s\n", ++ dwc_otg_hcd_get_ep_num(&urb->pipe_info), ++ dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"); ++ switch (dev_speed) { ++ case USB_SPEED_LOW: ++ qh->dev_speed = DWC_OTG_EP_SPEED_LOW; ++ speed = "low"; ++ break; ++ case USB_SPEED_FULL: ++ qh->dev_speed = DWC_OTG_EP_SPEED_FULL; ++ speed = "full"; ++ break; ++ case USB_SPEED_HIGH: ++ qh->dev_speed = DWC_OTG_EP_SPEED_HIGH; ++ speed = "high"; ++ break; ++ default: ++ speed = "?"; ++ break; ++ } ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Speed = %s\n", speed); ++ ++ switch (qh->ep_type) { ++ case UE_ISOCHRONOUS: ++ type = "isochronous"; ++ break; ++ case UE_INTERRUPT: ++ type = "interrupt"; ++ break; ++ case UE_CONTROL: ++ type = "control"; ++ break; ++ case UE_BULK: ++ type = "bulk"; ++ break; ++ default: ++ type = "?"; ++ break; ++ } ++ ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Type = %s\n", type); ++ ++#ifdef DEBUG ++ if (qh->ep_type == UE_INTERRUPT) { ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n", ++ qh->usecs); ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n", ++ qh->interval); ++ } ++#endif ++ ++} ++ ++/** ++ * This function allocates and initializes a QH. ++ * ++ * @param hcd The HCD state structure for the DWC OTG controller. ++ * @param urb Holds the information about the device/endpoint that we need ++ * to initialize the QH. ++ * @param atomic_alloc Flag to do atomic allocation if needed ++ * ++ * @return Returns pointer to the newly allocated QH, or NULL on error. */ ++dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd, ++ dwc_otg_hcd_urb_t * urb, int atomic_alloc) ++{ ++ dwc_otg_qh_t *qh; ++ ++ /* Allocate memory */ ++ /** @todo add memflags argument */ ++ qh = dwc_otg_hcd_qh_alloc(atomic_alloc); ++ if (qh == NULL) { ++ DWC_ERROR("qh allocation failed"); ++ return NULL; ++ } ++ ++ qh_init(hcd, qh, urb); ++ ++ if (hcd->core_if->dma_desc_enable ++ && (dwc_otg_hcd_qh_init_ddma(hcd, qh) < 0)) { ++ dwc_otg_hcd_qh_free(hcd, qh); ++ return NULL; ++ } ++ ++ return qh; ++} ++ ++/* microframe_schedule=0 start */ ++ ++/** ++ * Checks that a channel is available for a periodic transfer. ++ * ++ * @return 0 if successful, negative error code otherise. ++ */ ++static int periodic_channel_available(dwc_otg_hcd_t * hcd) ++{ ++ /* ++ * Currently assuming that there is a dedicated host channnel for each ++ * periodic transaction plus at least one host channel for ++ * non-periodic transactions. ++ */ ++ int status; ++ int num_channels; ++ ++ num_channels = hcd->core_if->core_params->host_channels; ++ if ((hcd->periodic_channels + hcd->non_periodic_channels < num_channels) ++ && (hcd->periodic_channels < num_channels - 1)) { ++ status = 0; ++ } else { ++ DWC_INFO("%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n", ++ __func__, num_channels, hcd->periodic_channels, hcd->non_periodic_channels); //NOTICE ++ status = -DWC_E_NO_SPACE; ++ } ++ ++ return status; ++} ++ ++/** ++ * Checks that there is sufficient bandwidth for the specified QH in the ++ * periodic schedule. For simplicity, this calculation assumes that all the ++ * transfers in the periodic schedule may occur in the same (micro)frame. ++ * ++ * @param hcd The HCD state structure for the DWC OTG controller. ++ * @param qh QH containing periodic bandwidth required. ++ * ++ * @return 0 if successful, negative error code otherwise. ++ */ ++static int check_periodic_bandwidth(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ int status; ++ int16_t max_claimed_usecs; ++ ++ status = 0; ++ ++ if ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) || qh->do_split) { ++ /* ++ * High speed mode. ++ * Max periodic usecs is 80% x 125 usec = 100 usec. ++ */ ++ ++ max_claimed_usecs = 100 - qh->usecs; ++ } else { ++ /* ++ * Full speed mode. ++ * Max periodic usecs is 90% x 1000 usec = 900 usec. ++ */ ++ max_claimed_usecs = 900 - qh->usecs; ++ } ++ ++ if (hcd->periodic_usecs > max_claimed_usecs) { ++ DWC_INFO("%s: already claimed usecs %d, required usecs %d\n", __func__, hcd->periodic_usecs, qh->usecs); //NOTICE ++ status = -DWC_E_NO_SPACE; ++ } ++ ++ return status; ++} ++ ++/* microframe_schedule=0 end */ ++ ++/** ++ * Microframe scheduler ++ * track the total use in hcd->frame_usecs ++ * keep each qh use in qh->frame_usecs ++ * when surrendering the qh then donate the time back ++ */ ++const unsigned short max_uframe_usecs[]={ 100, 100, 100, 100, 100, 100, 30, 0 }; ++ ++/* ++ * called from dwc_otg_hcd.c:dwc_otg_hcd_init ++ */ ++int init_hcd_usecs(dwc_otg_hcd_t *_hcd) ++{ ++ int i; ++ for (i=0; i<8; i++) { ++ _hcd->frame_usecs[i] = max_uframe_usecs[i]; ++ } ++ return 0; ++} ++ ++static int find_single_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh) ++{ ++ int i; ++ unsigned short utime; ++ int t_left; ++ int ret; ++ int done; ++ ++ ret = -1; ++ utime = _qh->usecs; ++ t_left = utime; ++ i = 0; ++ done = 0; ++ while (done == 0) { ++ /* At the start _hcd->frame_usecs[i] = max_uframe_usecs[i]; */ ++ if (utime <= _hcd->frame_usecs[i]) { ++ _hcd->frame_usecs[i] -= utime; ++ _qh->frame_usecs[i] += utime; ++ t_left -= utime; ++ ret = i; ++ done = 1; ++ return ret; ++ } else { ++ i++; ++ if (i == 8) { ++ done = 1; ++ ret = -1; ++ } ++ } ++ } ++ return ret; ++ } ++ ++/* ++ * use this for FS apps that can span multiple uframes ++ */ ++static int find_multi_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh) ++{ ++ int i; ++ int j; ++ unsigned short utime; ++ int t_left; ++ int ret; ++ int done; ++ unsigned short xtime; ++ ++ ret = -1; ++ utime = _qh->usecs; ++ t_left = utime; ++ i = 0; ++ done = 0; ++loop: ++ while (done == 0) { ++ if(_hcd->frame_usecs[i] <= 0) { ++ i++; ++ if (i == 8) { ++ done = 1; ++ ret = -1; ++ } ++ goto loop; ++ } ++ ++ /* ++ * we need n consecutive slots ++ * so use j as a start slot j plus j+1 must be enough time (for now) ++ */ ++ xtime= _hcd->frame_usecs[i]; ++ for (j = i+1 ; j < 8 ; j++ ) { ++ /* ++ * if we add this frame remaining time to xtime we may ++ * be OK, if not we need to test j for a complete frame ++ */ ++ if ((xtime+_hcd->frame_usecs[j]) < utime) { ++ if (_hcd->frame_usecs[j] < max_uframe_usecs[j]) { ++ j = 8; ++ ret = -1; ++ continue; ++ } ++ } ++ if (xtime >= utime) { ++ ret = i; ++ j = 8; /* stop loop with a good value ret */ ++ continue; ++ } ++ /* add the frame time to x time */ ++ xtime += _hcd->frame_usecs[j]; ++ /* we must have a fully available next frame or break */ ++ if ((xtime < utime) ++ && (_hcd->frame_usecs[j] == max_uframe_usecs[j])) { ++ ret = -1; ++ j = 8; /* stop loop with a bad value ret */ ++ continue; ++ } ++ } ++ if (ret >= 0) { ++ t_left = utime; ++ for (j = i; (t_left>0) && (j < 8); j++ ) { ++ t_left -= _hcd->frame_usecs[j]; ++ if ( t_left <= 0 ) { ++ _qh->frame_usecs[j] += _hcd->frame_usecs[j] + t_left; ++ _hcd->frame_usecs[j]= -t_left; ++ ret = i; ++ done = 1; ++ } else { ++ _qh->frame_usecs[j] += _hcd->frame_usecs[j]; ++ _hcd->frame_usecs[j] = 0; ++ } ++ } ++ } else { ++ i++; ++ if (i == 8) { ++ done = 1; ++ ret = -1; ++ } ++ } ++ } ++ return ret; ++} ++ ++static int find_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh) ++{ ++ int ret; ++ ret = -1; ++ ++ if (_qh->speed == USB_SPEED_HIGH) { ++ /* if this is a hs transaction we need a full frame */ ++ ret = find_single_uframe(_hcd, _qh); ++ } else { ++ /* if this is a fs transaction we may need a sequence of frames */ ++ ret = find_multi_uframe(_hcd, _qh); ++ } ++ return ret; ++} ++ ++/** ++ * Checks that the max transfer size allowed in a host channel is large enough ++ * to handle the maximum data transfer in a single (micro)frame for a periodic ++ * transfer. ++ * ++ * @param hcd The HCD state structure for the DWC OTG controller. ++ * @param qh QH for a periodic endpoint. ++ * ++ * @return 0 if successful, negative error code otherwise. ++ */ ++static int check_max_xfer_size(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ int status; ++ uint32_t max_xfer_size; ++ uint32_t max_channel_xfer_size; ++ ++ status = 0; ++ ++ max_xfer_size = dwc_max_packet(qh->maxp) * dwc_hb_mult(qh->maxp); ++ max_channel_xfer_size = hcd->core_if->core_params->max_transfer_size; ++ ++ if (max_xfer_size > max_channel_xfer_size) { ++ DWC_INFO("%s: Periodic xfer length %d > " "max xfer length for channel %d\n", ++ __func__, max_xfer_size, max_channel_xfer_size); //NOTICE ++ status = -DWC_E_NO_SPACE; ++ } ++ ++ return status; ++} ++ ++ ++ ++/** ++ * Schedules an interrupt or isochronous transfer in the periodic schedule. ++ * ++ * @param hcd The HCD state structure for the DWC OTG controller. ++ * @param qh QH for the periodic transfer. The QH should already contain the ++ * scheduling information. ++ * ++ * @return 0 if successful, negative error code otherwise. ++ */ ++static int schedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ int status = 0; ++ ++ if (microframe_schedule) { ++ int frame; ++ status = find_uframe(hcd, qh); ++ frame = -1; ++ if (status == 0) { ++ frame = 7; ++ } else { ++ if (status > 0 ) ++ frame = status-1; ++ } ++ ++ /* Set the new frame up */ ++ if (frame > -1) { ++ qh->sched_frame &= ~0x7; ++ qh->sched_frame |= (frame & 7); ++ } ++ ++ if (status != -1) ++ status = 0; ++ } else { ++ status = periodic_channel_available(hcd); ++ if (status) { ++ DWC_INFO("%s: No host channel available for periodic " "transfer.\n", __func__); //NOTICE ++ return status; ++ } ++ ++ status = check_periodic_bandwidth(hcd, qh); ++ } ++ if (status) { ++ DWC_INFO("%s: Insufficient periodic bandwidth for " ++ "periodic transfer.\n", __func__); ++ return status; ++ } ++ status = check_max_xfer_size(hcd, qh); ++ if (status) { ++ DWC_INFO("%s: Channel max transfer size too small " ++ "for periodic transfer.\n", __func__); ++ return status; ++ } ++ ++ if (hcd->core_if->dma_desc_enable) { ++ /* Don't rely on SOF and start in ready schedule */ ++ DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_ready, &qh->qh_list_entry); ++ } ++ else { ++ if(fiq_enable && (DWC_LIST_EMPTY(&hcd->periodic_sched_inactive) || dwc_frame_num_le(qh->sched_frame, hcd->fiq_state->next_sched_frame))) ++ { ++ hcd->fiq_state->next_sched_frame = qh->sched_frame; ++ ++ } ++ /* Always start in the inactive schedule. */ ++ DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_inactive, &qh->qh_list_entry); ++ } ++ ++ if (!microframe_schedule) { ++ /* Reserve the periodic channel. */ ++ hcd->periodic_channels++; ++ } ++ ++ /* Update claimed usecs per (micro)frame. */ ++ hcd->periodic_usecs += qh->usecs; ++ ++ return status; ++} ++ ++ ++/** ++ * This function adds a QH to either the non periodic or periodic schedule if ++ * it is not already in the schedule. If the QH is already in the schedule, no ++ * action is taken. ++ * ++ * @return 0 if successful, negative error code otherwise. ++ */ ++int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ int status = 0; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) { ++ /* QH already in a schedule. */ ++ return status; ++ } ++ ++ /* Add the new QH to the appropriate schedule */ ++ if (dwc_qh_is_non_per(qh)) { ++ /* Always start in the inactive schedule. */ ++ DWC_LIST_INSERT_TAIL(&hcd->non_periodic_sched_inactive, ++ &qh->qh_list_entry); ++ //hcd->fiq_state->kick_np_queues = 1; ++ } else { ++ status = schedule_periodic(hcd, qh); ++ if ( !hcd->periodic_qh_count ) { ++ intr_mask.b.sofintr = 1; ++ if (fiq_enable) { ++ local_fiq_disable(); ++ fiq_fsm_spin_lock(&hcd->fiq_state->lock); ++ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, intr_mask.d32); ++ fiq_fsm_spin_unlock(&hcd->fiq_state->lock); ++ local_fiq_enable(); ++ } else { ++ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, intr_mask.d32); ++ } ++ } ++ hcd->periodic_qh_count++; ++ } ++ ++ return status; ++} ++ ++/** ++ * Removes an interrupt or isochronous transfer from the periodic schedule. ++ * ++ * @param hcd The HCD state structure for the DWC OTG controller. ++ * @param qh QH for the periodic transfer. ++ */ ++static void deschedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ int i; ++ DWC_LIST_REMOVE_INIT(&qh->qh_list_entry); ++ ++ /* Update claimed usecs per (micro)frame. */ ++ hcd->periodic_usecs -= qh->usecs; ++ ++ if (!microframe_schedule) { ++ /* Release the periodic channel reservation. */ ++ hcd->periodic_channels--; ++ } else { ++ for (i = 0; i < 8; i++) { ++ hcd->frame_usecs[i] += qh->frame_usecs[i]; ++ qh->frame_usecs[i] = 0; ++ } ++ } ++} ++ ++/** ++ * Removes a QH from either the non-periodic or periodic schedule. Memory is ++ * not freed. ++ * ++ * @param hcd The HCD state structure. ++ * @param qh QH to remove from schedule. */ ++void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ if (DWC_LIST_EMPTY(&qh->qh_list_entry)) { ++ /* QH is not in a schedule. */ ++ return; ++ } ++ ++ if (dwc_qh_is_non_per(qh)) { ++ if (hcd->non_periodic_qh_ptr == &qh->qh_list_entry) { ++ hcd->non_periodic_qh_ptr = ++ hcd->non_periodic_qh_ptr->next; ++ } ++ DWC_LIST_REMOVE_INIT(&qh->qh_list_entry); ++ //if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_inactive)) ++ // hcd->fiq_state->kick_np_queues = 1; ++ } else { ++ deschedule_periodic(hcd, qh); ++ hcd->periodic_qh_count--; ++ if( !hcd->periodic_qh_count && !fiq_fsm_enable ) { ++ intr_mask.b.sofintr = 1; ++ if (fiq_enable) { ++ local_fiq_disable(); ++ fiq_fsm_spin_lock(&hcd->fiq_state->lock); ++ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, 0); ++ fiq_fsm_spin_unlock(&hcd->fiq_state->lock); ++ local_fiq_enable(); ++ } else { ++ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, 0); ++ } ++ } ++ } ++} ++ ++/** ++ * Deactivates a QH. For non-periodic QHs, removes the QH from the active ++ * non-periodic schedule. The QH is added to the inactive non-periodic ++ * schedule if any QTDs are still attached to the QH. ++ * ++ * For periodic QHs, the QH is removed from the periodic queued schedule. If ++ * there are any QTDs still attached to the QH, the QH is added to either the ++ * periodic inactive schedule or the periodic ready schedule and its next ++ * scheduled frame is calculated. The QH is placed in the ready schedule if ++ * the scheduled frame has been reached already. Otherwise it's placed in the ++ * inactive schedule. If there are no QTDs attached to the QH, the QH is ++ * completely removed from the periodic schedule. ++ */ ++void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, ++ int sched_next_periodic_split) ++{ ++ if (dwc_qh_is_non_per(qh)) { ++ dwc_otg_hcd_qh_remove(hcd, qh); ++ if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) { ++ /* Add back to inactive non-periodic schedule. */ ++ dwc_otg_hcd_qh_add(hcd, qh); ++ //hcd->fiq_state->kick_np_queues = 1; ++ } ++ } else { ++ uint16_t frame_number = dwc_otg_hcd_get_frame_number(hcd); ++ ++ if (qh->do_split) { ++ /* Schedule the next continuing periodic split transfer */ ++ if (sched_next_periodic_split) { ++ ++ qh->sched_frame = frame_number; ++ ++ if (dwc_frame_num_le(frame_number, ++ dwc_frame_num_inc ++ (qh->start_split_frame, ++ 1))) { ++ /* ++ * Allow one frame to elapse after start ++ * split microframe before scheduling ++ * complete split, but DONT if we are ++ * doing the next start split in the ++ * same frame for an ISOC out. ++ */ ++ if ((qh->ep_type != UE_ISOCHRONOUS) || ++ (qh->ep_is_in != 0)) { ++ qh->sched_frame = ++ dwc_frame_num_inc(qh->sched_frame, 1); ++ } ++ } ++ } else { ++ qh->sched_frame = ++ dwc_frame_num_inc(qh->start_split_frame, ++ qh->interval); ++ if (dwc_frame_num_le ++ (qh->sched_frame, frame_number)) { ++ qh->sched_frame = frame_number; ++ } ++ qh->sched_frame |= 0x7; ++ qh->start_split_frame = qh->sched_frame; ++ } ++ } else { ++ qh->sched_frame = ++ dwc_frame_num_inc(qh->sched_frame, qh->interval); ++ if (dwc_frame_num_le(qh->sched_frame, frame_number)) { ++ qh->sched_frame = frame_number; ++ } ++ } ++ ++ if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) { ++ dwc_otg_hcd_qh_remove(hcd, qh); ++ } else { ++ /* ++ * Remove from periodic_sched_queued and move to ++ * appropriate queue. ++ */ ++ if ((microframe_schedule && dwc_frame_num_le(qh->sched_frame, frame_number)) || ++ (!microframe_schedule && qh->sched_frame == frame_number)) { ++ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready, ++ &qh->qh_list_entry); ++ } else { ++ if(fiq_enable && !dwc_frame_num_le(hcd->fiq_state->next_sched_frame, qh->sched_frame)) ++ { ++ hcd->fiq_state->next_sched_frame = qh->sched_frame; ++ } ++ ++ DWC_LIST_MOVE_HEAD ++ (&hcd->periodic_sched_inactive, ++ &qh->qh_list_entry); ++ } ++ } ++ } ++} ++ ++/** ++ * This function allocates and initializes a QTD. ++ * ++ * @param urb The URB to create a QTD from. Each URB-QTD pair will end up ++ * pointing to each other so each pair should have a unique correlation. ++ * @param atomic_alloc Flag to do atomic alloc if needed ++ * ++ * @return Returns pointer to the newly allocated QTD, or NULL on error. */ ++dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb, int atomic_alloc) ++{ ++ dwc_otg_qtd_t *qtd; ++ ++ qtd = dwc_otg_hcd_qtd_alloc(atomic_alloc); ++ if (qtd == NULL) { ++ return NULL; ++ } ++ ++ dwc_otg_hcd_qtd_init(qtd, urb); ++ return qtd; ++} ++ ++/** ++ * Initializes a QTD structure. ++ * ++ * @param qtd The QTD to initialize. ++ * @param urb The URB to use for initialization. */ ++void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb) ++{ ++ dwc_memset(qtd, 0, sizeof(dwc_otg_qtd_t)); ++ qtd->urb = urb; ++ if (dwc_otg_hcd_get_pipe_type(&urb->pipe_info) == UE_CONTROL) { ++ /* ++ * The only time the QTD data toggle is used is on the data ++ * phase of control transfers. This phase always starts with ++ * DATA1. ++ */ ++ qtd->data_toggle = DWC_OTG_HC_PID_DATA1; ++ qtd->control_phase = DWC_OTG_CONTROL_SETUP; ++ } ++ ++ /* start split */ ++ qtd->complete_split = 0; ++ qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL; ++ qtd->isoc_split_offset = 0; ++ qtd->in_process = 0; ++ ++ /* Store the qtd ptr in the urb to reference what QTD. */ ++ urb->qtd = qtd; ++ return; ++} ++ ++/** ++ * This function adds a QTD to the QTD-list of a QH. It will find the correct ++ * QH to place the QTD into. If it does not find a QH, then it will create a ++ * new QH. If the QH to which the QTD is added is not currently scheduled, it ++ * is placed into the proper schedule based on its EP type. ++ * HCD lock must be held and interrupts must be disabled on entry ++ * ++ * @param[in] qtd The QTD to add ++ * @param[in] hcd The DWC HCD structure ++ * @param[out] qh out parameter to return queue head ++ * @param atomic_alloc Flag to do atomic alloc if needed ++ * ++ * @return 0 if successful, negative error code otherwise. ++ */ ++int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, ++ dwc_otg_hcd_t * hcd, dwc_otg_qh_t ** qh, int atomic_alloc) ++{ ++ int retval = 0; ++ dwc_otg_hcd_urb_t *urb = qtd->urb; ++ ++ /* ++ * Get the QH which holds the QTD-list to insert to. Create QH if it ++ * doesn't exist. ++ */ ++ if (*qh == NULL) { ++ *qh = dwc_otg_hcd_qh_create(hcd, urb, atomic_alloc); ++ if (*qh == NULL) { ++ retval = -DWC_E_NO_MEMORY; ++ goto done; ++ } else { ++ if (fiq_enable) ++ hcd->fiq_state->kick_np_queues = 1; ++ } ++ } ++ retval = dwc_otg_hcd_qh_add(hcd, *qh); ++ if (retval == 0) { ++ DWC_CIRCLEQ_INSERT_TAIL(&((*qh)->qtd_list), qtd, ++ qtd_list_entry); ++ qtd->qh = *qh; ++ } ++done: ++ ++ return retval; ++} ++ ++#endif /* DWC_DEVICE_ONLY */ +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h 2015-11-29 09:42:39.923098428 +0100 +@@ -0,0 +1,188 @@ ++#ifndef _DWC_OS_DEP_H_ ++#define _DWC_OS_DEP_H_ ++ ++/** ++ * @file ++ * ++ * This file contains OS dependent structures. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++# include ++#endif ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21) ++# include ++#else ++# include ++#endif ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24) ++# include ++#else ++# include ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) ++# include ++#endif ++ ++#ifdef PCI_INTERFACE ++# include ++#endif ++ ++#ifdef LM_INTERFACE ++# include ++# include ++# include ++# include ++# if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) ++# include ++# include ++# include ++# include ++# else ++/* in 2.6.31, at least, we seem to have lost the generic LM infrastructure - ++ here we assume that the machine architecture provides definitions ++ in its own header ++*/ ++# include ++# include ++# endif ++#endif ++ ++#ifdef PLATFORM_INTERFACE ++#include ++#include ++#endif ++ ++/** The OS page size */ ++#define DWC_OS_PAGE_SIZE PAGE_SIZE ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14) ++typedef int gfp_t; ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) ++# define IRQF_SHARED SA_SHIRQ ++#endif ++ ++typedef struct os_dependent { ++ /** Base address returned from ioremap() */ ++ void *base; ++ ++ /** Register offset for Diagnostic API */ ++ uint32_t reg_offset; ++ ++ /** Base address for MPHI peripheral */ ++ void *mphi_base; ++ ++#ifdef LM_INTERFACE ++ struct lm_device *lmdev; ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *pcidev; ++ ++ /** Start address of a PCI region */ ++ resource_size_t rsrc_start; ++ ++ /** Length address of a PCI region */ ++ resource_size_t rsrc_len; ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *platformdev; ++#endif ++ ++} os_dependent_t; ++ ++#ifdef __cplusplus ++} ++#endif ++ ++ ++ ++/* Type for the our device on the chosen bus */ ++#if defined(LM_INTERFACE) ++typedef struct lm_device dwc_bus_dev_t; ++#elif defined(PCI_INTERFACE) ++typedef struct pci_dev dwc_bus_dev_t; ++#elif defined(PLATFORM_INTERFACE) ++typedef struct platform_device dwc_bus_dev_t; ++#endif ++ ++/* Helper macro to retrieve drvdata from the device on the chosen bus */ ++#if defined(LM_INTERFACE) ++#define DWC_OTG_BUSDRVDATA(_dev) lm_get_drvdata(_dev) ++#elif defined(PCI_INTERFACE) ++#define DWC_OTG_BUSDRVDATA(_dev) pci_get_drvdata(_dev) ++#elif defined(PLATFORM_INTERFACE) ++#define DWC_OTG_BUSDRVDATA(_dev) platform_get_drvdata(_dev) ++#endif ++ ++/** ++ * Helper macro returning the otg_device structure of a given struct device ++ * ++ * c.f. static dwc_otg_device_t *dwc_otg_drvdev(struct device *_dev) ++ */ ++#ifdef LM_INTERFACE ++#define DWC_OTG_GETDRVDEV(_var, _dev) do { \ ++ struct lm_device *lm_dev = \ ++ container_of(_dev, struct lm_device, dev); \ ++ _var = lm_get_drvdata(lm_dev); \ ++ } while (0) ++ ++#elif defined(PCI_INTERFACE) ++#define DWC_OTG_GETDRVDEV(_var, _dev) do { \ ++ _var = dev_get_drvdata(_dev); \ ++ } while (0) ++ ++#elif defined(PLATFORM_INTERFACE) ++#define DWC_OTG_GETDRVDEV(_var, _dev) do { \ ++ struct platform_device *platform_dev = \ ++ container_of(_dev, struct platform_device, dev); \ ++ _var = platform_get_drvdata(platform_dev); \ ++ } while (0) ++#endif ++ ++ ++/** ++ * Helper macro returning the struct dev of the given struct os_dependent ++ * ++ * c.f. static struct device *dwc_otg_getdev(struct os_dependent *osdep) ++ */ ++#ifdef LM_INTERFACE ++#define DWC_OTG_OS_GETDEV(_osdep) \ ++ ((_osdep).lmdev == NULL? NULL: &(_osdep).lmdev->dev) ++#elif defined(PCI_INTERFACE) ++#define DWC_OTG_OS_GETDEV(_osdep) \ ++ ((_osdep).pci_dev == NULL? NULL: &(_osdep).pci_dev->dev) ++#elif defined(PLATFORM_INTERFACE) ++#define DWC_OTG_OS_GETDEV(_osdep) \ ++ ((_osdep).platformdev == NULL? NULL: &(_osdep).platformdev->dev) ++#endif ++ ++ ++ ++ ++#endif /* _DWC_OS_DEP_H_ */ +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_pcd.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd.c +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_pcd.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd.c 2015-11-29 09:42:39.923098428 +0100 +@@ -0,0 +1,2712 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.c $ ++ * $Revision: #101 $ ++ * $Date: 2012/08/10 $ ++ * $Change: 2047372 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_HOST_ONLY ++ ++/** @file ++ * This file implements PCD Core. All code in this file is portable and doesn't ++ * use any OS specific functions. ++ * PCD Core provides Interface, defined in ++ * header file, which can be used to implement OS specific PCD interface. ++ * ++ * An important function of the PCD is managing interrupts generated ++ * by the DWC_otg controller. The implementation of the DWC_otg device ++ * mode interrupt service routines is in dwc_otg_pcd_intr.c. ++ * ++ * @todo Add Device Mode test modes (Test J mode, Test K mode, etc). ++ * @todo Does it work when the request size is greater than DEPTSIZ ++ * transfer size ++ * ++ */ ++ ++#include "dwc_otg_pcd.h" ++ ++#ifdef DWC_UTE_CFI ++#include "dwc_otg_cfi.h" ++ ++extern int init_cfi(cfiobject_t * cfiobj); ++#endif ++ ++/** ++ * Choose endpoint from ep arrays using usb_ep structure. ++ */ ++static dwc_otg_pcd_ep_t *get_ep_from_handle(dwc_otg_pcd_t * pcd, void *handle) ++{ ++ int i; ++ if (pcd->ep0.priv == handle) { ++ return &pcd->ep0; ++ } ++ for (i = 0; i < MAX_EPS_CHANNELS - 1; i++) { ++ if (pcd->in_ep[i].priv == handle) ++ return &pcd->in_ep[i]; ++ if (pcd->out_ep[i].priv == handle) ++ return &pcd->out_ep[i]; ++ } ++ ++ return NULL; ++} ++ ++/** ++ * This function completes a request. It call's the request call back. ++ */ ++void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep, dwc_otg_pcd_request_t * req, ++ int32_t status) ++{ ++ unsigned stopped = ep->stopped; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(ep %p req %p)\n", __func__, ep, req); ++ DWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry); ++ ++ /* don't modify queue heads during completion callback */ ++ ep->stopped = 1; ++ /* spin_unlock/spin_lock now done in fops->complete() */ ++ ep->pcd->fops->complete(ep->pcd, ep->priv, req->priv, status, ++ req->actual); ++ ++ if (ep->pcd->request_pending > 0) { ++ --ep->pcd->request_pending; ++ } ++ ++ ep->stopped = stopped; ++ DWC_FREE(req); ++} ++ ++/** ++ * This function terminates all the requsts in the EP request queue. ++ */ ++void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep) ++{ ++ dwc_otg_pcd_request_t *req; ++ ++ ep->stopped = 1; ++ ++ /* called with irqs blocked?? */ ++ while (!DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ req = DWC_CIRCLEQ_FIRST(&ep->queue); ++ dwc_otg_request_done(ep, req, -DWC_E_SHUTDOWN); ++ } ++} ++ ++void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd, ++ const struct dwc_otg_pcd_function_ops *fops) ++{ ++ pcd->fops = fops; ++} ++ ++/** ++ * PCD Callback function for initializing the PCD when switching to ++ * device mode. ++ * ++ * @param p void pointer to the dwc_otg_pcd_t ++ */ ++static int32_t dwc_otg_pcd_start_cb(void *p) ++{ ++ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p; ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ ++ /* ++ * Initialized the Core for Device mode. ++ */ ++ if (dwc_otg_is_device_mode(core_if)) { ++ dwc_otg_core_dev_init(core_if); ++ /* Set core_if's lock pointer to the pcd->lock */ ++ core_if->lock = pcd->lock; ++ } ++ return 1; ++} ++ ++/** CFI-specific buffer allocation function for EP */ ++#ifdef DWC_UTE_CFI ++uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr, ++ size_t buflen, int flags) ++{ ++ dwc_otg_pcd_ep_t *ep; ++ ep = get_ep_from_handle(pcd, pep); ++ if (!ep) { ++ DWC_WARN("bad ep\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ return pcd->cfi->ops.ep_alloc_buf(pcd->cfi, pcd, ep, addr, buflen, ++ flags); ++} ++#else ++uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr, ++ size_t buflen, int flags); ++#endif ++ ++/** ++ * PCD Callback function for notifying the PCD when resuming from ++ * suspend. ++ * ++ * @param p void pointer to the dwc_otg_pcd_t ++ */ ++static int32_t dwc_otg_pcd_resume_cb(void *p) ++{ ++ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p; ++ ++ if (pcd->fops->resume) { ++ pcd->fops->resume(pcd); ++ } ++ ++ /* Stop the SRP timeout timer. */ ++ if ((GET_CORE_IF(pcd)->core_params->phy_type != DWC_PHY_TYPE_PARAM_FS) ++ || (!GET_CORE_IF(pcd)->core_params->i2c_enable)) { ++ if (GET_CORE_IF(pcd)->srp_timer_started) { ++ GET_CORE_IF(pcd)->srp_timer_started = 0; ++ DWC_TIMER_CANCEL(GET_CORE_IF(pcd)->srp_timer); ++ } ++ } ++ return 1; ++} ++ ++/** ++ * PCD Callback function for notifying the PCD device is suspended. ++ * ++ * @param p void pointer to the dwc_otg_pcd_t ++ */ ++static int32_t dwc_otg_pcd_suspend_cb(void *p) ++{ ++ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p; ++ ++ if (pcd->fops->suspend) { ++ DWC_SPINUNLOCK(pcd->lock); ++ pcd->fops->suspend(pcd); ++ DWC_SPINLOCK(pcd->lock); ++ } ++ ++ return 1; ++} ++ ++/** ++ * PCD Callback function for stopping the PCD when switching to Host ++ * mode. ++ * ++ * @param p void pointer to the dwc_otg_pcd_t ++ */ ++static int32_t dwc_otg_pcd_stop_cb(void *p) ++{ ++ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p; ++ extern void dwc_otg_pcd_stop(dwc_otg_pcd_t * _pcd); ++ ++ dwc_otg_pcd_stop(pcd); ++ return 1; ++} ++ ++/** ++ * PCD Callback structure for handling mode switching. ++ */ ++static dwc_otg_cil_callbacks_t pcd_callbacks = { ++ .start = dwc_otg_pcd_start_cb, ++ .stop = dwc_otg_pcd_stop_cb, ++ .suspend = dwc_otg_pcd_suspend_cb, ++ .resume_wakeup = dwc_otg_pcd_resume_cb, ++ .p = 0, /* Set at registration */ ++}; ++ ++/** ++ * This function allocates a DMA Descriptor chain for the Endpoint ++ * buffer to be used for a transfer to/from the specified endpoint. ++ */ ++dwc_otg_dev_dma_desc_t *dwc_otg_ep_alloc_desc_chain(dwc_dma_t * dma_desc_addr, ++ uint32_t count) ++{ ++ return DWC_DMA_ALLOC_ATOMIC(count * sizeof(dwc_otg_dev_dma_desc_t), ++ dma_desc_addr); ++} ++ ++/** ++ * This function frees a DMA Descriptor chain that was allocated by ep_alloc_desc. ++ */ ++void dwc_otg_ep_free_desc_chain(dwc_otg_dev_dma_desc_t * desc_addr, ++ uint32_t dma_desc_addr, uint32_t count) ++{ ++ DWC_DMA_FREE(count * sizeof(dwc_otg_dev_dma_desc_t), desc_addr, ++ dma_desc_addr); ++} ++ ++#ifdef DWC_EN_ISOC ++ ++/** ++ * This function initializes a descriptor chain for Isochronous transfer ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param dwc_ep The EP to start the transfer on. ++ * ++ */ ++void dwc_otg_iso_ep_start_ddma_transfer(dwc_otg_core_if_t * core_if, ++ dwc_ep_t * dwc_ep) ++{ ++ ++ dsts_data_t dsts = {.d32 = 0 }; ++ depctl_data_t depctl = {.d32 = 0 }; ++ volatile uint32_t *addr; ++ int i, j; ++ uint32_t len; ++ ++ if (dwc_ep->is_in) ++ dwc_ep->desc_cnt = dwc_ep->buf_proc_intrvl / dwc_ep->bInterval; ++ else ++ dwc_ep->desc_cnt = ++ dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm / ++ dwc_ep->bInterval; ++ ++ /** Allocate descriptors for double buffering */ ++ dwc_ep->iso_desc_addr = ++ dwc_otg_ep_alloc_desc_chain(&dwc_ep->iso_dma_desc_addr, ++ dwc_ep->desc_cnt * 2); ++ if (dwc_ep->desc_addr) { ++ DWC_WARN("%s, can't allocate DMA descriptor chain\n", __func__); ++ return; ++ } ++ ++ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); ++ ++ /** ISO OUT EP */ ++ if (dwc_ep->is_in == 0) { ++ dev_dma_desc_sts_t sts = {.d32 = 0 }; ++ dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr; ++ dma_addr_t dma_ad; ++ uint32_t data_per_desc; ++ dwc_otg_dev_out_ep_regs_t *out_regs = ++ core_if->dev_if->out_ep_regs[dwc_ep->num]; ++ int offset; ++ ++ addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl; ++ dma_ad = (dma_addr_t) DWC_READ_REG32(&(out_regs->doepdma)); ++ ++ /** Buffer 0 descriptors setup */ ++ dma_ad = dwc_ep->dma_addr0; ++ ++ sts.b_iso_out.bs = BS_HOST_READY; ++ sts.b_iso_out.rxsts = 0; ++ sts.b_iso_out.l = 0; ++ sts.b_iso_out.sp = 0; ++ sts.b_iso_out.ioc = 0; ++ sts.b_iso_out.pid = 0; ++ sts.b_iso_out.framenum = 0; ++ ++ offset = 0; ++ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; ++ i += dwc_ep->pkt_per_frm) { ++ ++ for (j = 0; j < dwc_ep->pkt_per_frm; ++j) { ++ uint32_t len = (j + 1) * dwc_ep->maxpacket; ++ if (len > dwc_ep->data_per_frame) ++ data_per_desc = ++ dwc_ep->data_per_frame - ++ j * dwc_ep->maxpacket; ++ else ++ data_per_desc = dwc_ep->maxpacket; ++ len = data_per_desc % 4; ++ if (len) ++ data_per_desc += 4 - len; ++ ++ sts.b_iso_out.rxbytes = data_per_desc; ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ ++ offset += data_per_desc; ++ dma_desc++; ++ dma_ad += data_per_desc; ++ } ++ } ++ ++ for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) { ++ uint32_t len = (j + 1) * dwc_ep->maxpacket; ++ if (len > dwc_ep->data_per_frame) ++ data_per_desc = ++ dwc_ep->data_per_frame - ++ j * dwc_ep->maxpacket; ++ else ++ data_per_desc = dwc_ep->maxpacket; ++ len = data_per_desc % 4; ++ if (len) ++ data_per_desc += 4 - len; ++ sts.b_iso_out.rxbytes = data_per_desc; ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ ++ offset += data_per_desc; ++ dma_desc++; ++ dma_ad += data_per_desc; ++ } ++ ++ sts.b_iso_out.ioc = 1; ++ len = (j + 1) * dwc_ep->maxpacket; ++ if (len > dwc_ep->data_per_frame) ++ data_per_desc = ++ dwc_ep->data_per_frame - j * dwc_ep->maxpacket; ++ else ++ data_per_desc = dwc_ep->maxpacket; ++ len = data_per_desc % 4; ++ if (len) ++ data_per_desc += 4 - len; ++ sts.b_iso_out.rxbytes = data_per_desc; ++ ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ dma_desc++; ++ ++ /** Buffer 1 descriptors setup */ ++ sts.b_iso_out.ioc = 0; ++ dma_ad = dwc_ep->dma_addr1; ++ ++ offset = 0; ++ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; ++ i += dwc_ep->pkt_per_frm) { ++ for (j = 0; j < dwc_ep->pkt_per_frm; ++j) { ++ uint32_t len = (j + 1) * dwc_ep->maxpacket; ++ if (len > dwc_ep->data_per_frame) ++ data_per_desc = ++ dwc_ep->data_per_frame - ++ j * dwc_ep->maxpacket; ++ else ++ data_per_desc = dwc_ep->maxpacket; ++ len = data_per_desc % 4; ++ if (len) ++ data_per_desc += 4 - len; ++ ++ data_per_desc = ++ sts.b_iso_out.rxbytes = data_per_desc; ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ ++ offset += data_per_desc; ++ dma_desc++; ++ dma_ad += data_per_desc; ++ } ++ } ++ for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) { ++ data_per_desc = ++ ((j + 1) * dwc_ep->maxpacket > ++ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame - ++ j * dwc_ep->maxpacket : dwc_ep->maxpacket; ++ data_per_desc += ++ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0; ++ sts.b_iso_out.rxbytes = data_per_desc; ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ ++ offset += data_per_desc; ++ dma_desc++; ++ dma_ad += data_per_desc; ++ } ++ ++ sts.b_iso_out.ioc = 1; ++ sts.b_iso_out.l = 1; ++ data_per_desc = ++ ((j + 1) * dwc_ep->maxpacket > ++ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame - ++ j * dwc_ep->maxpacket : dwc_ep->maxpacket; ++ data_per_desc += ++ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0; ++ sts.b_iso_out.rxbytes = data_per_desc; ++ ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ ++ dwc_ep->next_frame = 0; ++ ++ /** Write dma_ad into DOEPDMA register */ ++ DWC_WRITE_REG32(&(out_regs->doepdma), ++ (uint32_t) dwc_ep->iso_dma_desc_addr); ++ ++ } ++ /** ISO IN EP */ ++ else { ++ dev_dma_desc_sts_t sts = {.d32 = 0 }; ++ dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr; ++ dma_addr_t dma_ad; ++ dwc_otg_dev_in_ep_regs_t *in_regs = ++ core_if->dev_if->in_ep_regs[dwc_ep->num]; ++ unsigned int frmnumber; ++ fifosize_data_t txfifosize, rxfifosize; ++ ++ txfifosize.d32 = ++ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[dwc_ep->num]-> ++ dtxfsts); ++ rxfifosize.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->grxfsiz); ++ ++ addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl; ++ ++ dma_ad = dwc_ep->dma_addr0; ++ ++ dsts.d32 = ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); ++ ++ sts.b_iso_in.bs = BS_HOST_READY; ++ sts.b_iso_in.txsts = 0; ++ sts.b_iso_in.sp = ++ (dwc_ep->data_per_frame % dwc_ep->maxpacket) ? 1 : 0; ++ sts.b_iso_in.ioc = 0; ++ sts.b_iso_in.pid = dwc_ep->pkt_per_frm; ++ ++ frmnumber = dwc_ep->next_frame; ++ ++ sts.b_iso_in.framenum = frmnumber; ++ sts.b_iso_in.txbytes = dwc_ep->data_per_frame; ++ sts.b_iso_in.l = 0; ++ ++ /** Buffer 0 descriptors setup */ ++ for (i = 0; i < dwc_ep->desc_cnt - 1; i++) { ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ dma_desc++; ++ ++ dma_ad += dwc_ep->data_per_frame; ++ sts.b_iso_in.framenum += dwc_ep->bInterval; ++ } ++ ++ sts.b_iso_in.ioc = 1; ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ ++dma_desc; ++ ++ /** Buffer 1 descriptors setup */ ++ sts.b_iso_in.ioc = 0; ++ dma_ad = dwc_ep->dma_addr1; ++ ++ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; ++ i += dwc_ep->pkt_per_frm) { ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ dma_desc++; ++ ++ dma_ad += dwc_ep->data_per_frame; ++ sts.b_iso_in.framenum += dwc_ep->bInterval; ++ ++ sts.b_iso_in.ioc = 0; ++ } ++ sts.b_iso_in.ioc = 1; ++ sts.b_iso_in.l = 1; ++ ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ ++ dwc_ep->next_frame = sts.b_iso_in.framenum + dwc_ep->bInterval; ++ ++ /** Write dma_ad into diepdma register */ ++ DWC_WRITE_REG32(&(in_regs->diepdma), ++ (uint32_t) dwc_ep->iso_dma_desc_addr); ++ } ++ /** Enable endpoint, clear nak */ ++ depctl.d32 = 0; ++ depctl.b.epena = 1; ++ depctl.b.usbactep = 1; ++ depctl.b.cnak = 1; ++ ++ DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32); ++ depctl.d32 = DWC_READ_REG32(addr); ++} ++ ++/** ++ * This function initializes a descriptor chain for Isochronous transfer ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to start the transfer on. ++ * ++ */ ++void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if, ++ dwc_ep_t * ep) ++{ ++ depctl_data_t depctl = {.d32 = 0 }; ++ volatile uint32_t *addr; ++ ++ if (ep->is_in) { ++ addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl; ++ } else { ++ addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl; ++ } ++ ++ if (core_if->dma_enable == 0 || core_if->dma_desc_enable != 0) { ++ return; ++ } else { ++ deptsiz_data_t deptsiz = {.d32 = 0 }; ++ ++ ep->xfer_len = ++ ep->data_per_frame * ep->buf_proc_intrvl / ep->bInterval; ++ ep->pkt_cnt = ++ (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket; ++ ep->xfer_count = 0; ++ ep->xfer_buff = ++ (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0; ++ ep->dma_addr = ++ (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0; ++ ++ if (ep->is_in) { ++ /* Program the transfer size and packet count ++ * as follows: xfersize = N * maxpacket + ++ * short_packet pktcnt = N + (short_packet ++ * exist ? 1 : 0) ++ */ ++ deptsiz.b.mc = ep->pkt_per_frm; ++ deptsiz.b.xfersize = ep->xfer_len; ++ deptsiz.b.pktcnt = ++ (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket; ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]-> ++ dieptsiz, deptsiz.d32); ++ ++ /* Write the DMA register */ ++ DWC_WRITE_REG32(& ++ (core_if->dev_if->in_ep_regs[ep->num]-> ++ diepdma), (uint32_t) ep->dma_addr); ++ ++ } else { ++ deptsiz.b.pktcnt = ++ (ep->xfer_len + (ep->maxpacket - 1)) / ++ ep->maxpacket; ++ deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket; ++ ++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]-> ++ doeptsiz, deptsiz.d32); ++ ++ /* Write the DMA register */ ++ DWC_WRITE_REG32(& ++ (core_if->dev_if->out_ep_regs[ep->num]-> ++ doepdma), (uint32_t) ep->dma_addr); ++ ++ } ++ /** Enable endpoint, clear nak */ ++ depctl.d32 = 0; ++ depctl.b.epena = 1; ++ depctl.b.cnak = 1; ++ ++ DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32); ++ } ++} ++ ++/** ++ * This function does the setup for a data transfer for an EP and ++ * starts the transfer. For an IN transfer, the packets will be ++ * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, ++ * the packets are unloaded from the Rx FIFO in the ISR. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to start the transfer on. ++ */ ++ ++static void dwc_otg_iso_ep_start_transfer(dwc_otg_core_if_t * core_if, ++ dwc_ep_t * ep) ++{ ++ if (core_if->dma_enable) { ++ if (core_if->dma_desc_enable) { ++ if (ep->is_in) { ++ ep->desc_cnt = ep->pkt_cnt / ep->pkt_per_frm; ++ } else { ++ ep->desc_cnt = ep->pkt_cnt; ++ } ++ dwc_otg_iso_ep_start_ddma_transfer(core_if, ep); ++ } else { ++ if (core_if->pti_enh_enable) { ++ dwc_otg_iso_ep_start_buf_transfer(core_if, ep); ++ } else { ++ ep->cur_pkt_addr = ++ (ep->proc_buf_num) ? ep->xfer_buff1 : ep-> ++ xfer_buff0; ++ ep->cur_pkt_dma_addr = ++ (ep->proc_buf_num) ? ep->dma_addr1 : ep-> ++ dma_addr0; ++ dwc_otg_iso_ep_start_frm_transfer(core_if, ep); ++ } ++ } ++ } else { ++ ep->cur_pkt_addr = ++ (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0; ++ ep->cur_pkt_dma_addr = ++ (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0; ++ dwc_otg_iso_ep_start_frm_transfer(core_if, ep); ++ } ++} ++ ++/** ++ * This function stops transfer for an EP and ++ * resets the ep's variables. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to start the transfer on. ++ */ ++ ++void dwc_otg_iso_ep_stop_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ depctl_data_t depctl = {.d32 = 0 }; ++ volatile uint32_t *addr; ++ ++ if (ep->is_in == 1) { ++ addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl; ++ } else { ++ addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl; ++ } ++ ++ /* disable the ep */ ++ depctl.d32 = DWC_READ_REG32(addr); ++ ++ depctl.b.epdis = 1; ++ depctl.b.snak = 1; ++ ++ DWC_WRITE_REG32(addr, depctl.d32); ++ ++ if (core_if->dma_desc_enable && ++ ep->iso_desc_addr && ep->iso_dma_desc_addr) { ++ dwc_otg_ep_free_desc_chain(ep->iso_desc_addr, ++ ep->iso_dma_desc_addr, ++ ep->desc_cnt * 2); ++ } ++ ++ /* reset varibales */ ++ ep->dma_addr0 = 0; ++ ep->dma_addr1 = 0; ++ ep->xfer_buff0 = 0; ++ ep->xfer_buff1 = 0; ++ ep->data_per_frame = 0; ++ ep->data_pattern_frame = 0; ++ ep->sync_frame = 0; ++ ep->buf_proc_intrvl = 0; ++ ep->bInterval = 0; ++ ep->proc_buf_num = 0; ++ ep->pkt_per_frm = 0; ++ ep->pkt_per_frm = 0; ++ ep->desc_cnt = 0; ++ ep->iso_desc_addr = 0; ++ ep->iso_dma_desc_addr = 0; ++} ++ ++int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle, ++ uint8_t * buf0, uint8_t * buf1, dwc_dma_t dma0, ++ dwc_dma_t dma1, int sync_frame, int dp_frame, ++ int data_per_frame, int start_frame, ++ int buf_proc_intrvl, void *req_handle, ++ int atomic_alloc) ++{ ++ dwc_otg_pcd_ep_t *ep; ++ dwc_irqflags_t flags = 0; ++ dwc_ep_t *dwc_ep; ++ int32_t frm_data; ++ dsts_data_t dsts; ++ dwc_otg_core_if_t *core_if; ++ ++ ep = get_ep_from_handle(pcd, ep_handle); ++ ++ if (!ep || !ep->desc || ep->dwc_ep.num == 0) { ++ DWC_WARN("bad ep\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++ core_if = GET_CORE_IF(pcd); ++ dwc_ep = &ep->dwc_ep; ++ ++ if (ep->iso_req_handle) { ++ DWC_WARN("ISO request in progress\n"); ++ } ++ ++ dwc_ep->dma_addr0 = dma0; ++ dwc_ep->dma_addr1 = dma1; ++ ++ dwc_ep->xfer_buff0 = buf0; ++ dwc_ep->xfer_buff1 = buf1; ++ ++ dwc_ep->data_per_frame = data_per_frame; ++ ++ /** @todo - pattern data support is to be implemented in the future */ ++ dwc_ep->data_pattern_frame = dp_frame; ++ dwc_ep->sync_frame = sync_frame; ++ ++ dwc_ep->buf_proc_intrvl = buf_proc_intrvl; ++ ++ dwc_ep->bInterval = 1 << (ep->desc->bInterval - 1); ++ ++ dwc_ep->proc_buf_num = 0; ++ ++ dwc_ep->pkt_per_frm = 0; ++ frm_data = ep->dwc_ep.data_per_frame; ++ while (frm_data > 0) { ++ dwc_ep->pkt_per_frm++; ++ frm_data -= ep->dwc_ep.maxpacket; ++ } ++ ++ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); ++ ++ if (start_frame == -1) { ++ dwc_ep->next_frame = dsts.b.soffn + 1; ++ if (dwc_ep->bInterval != 1) { ++ dwc_ep->next_frame = ++ dwc_ep->next_frame + (dwc_ep->bInterval - 1 - ++ dwc_ep->next_frame % ++ dwc_ep->bInterval); ++ } ++ } else { ++ dwc_ep->next_frame = start_frame; ++ } ++ ++ if (!core_if->pti_enh_enable) { ++ dwc_ep->pkt_cnt = ++ dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm / ++ dwc_ep->bInterval; ++ } else { ++ dwc_ep->pkt_cnt = ++ (dwc_ep->data_per_frame * ++ (dwc_ep->buf_proc_intrvl / dwc_ep->bInterval) ++ - 1 + dwc_ep->maxpacket) / dwc_ep->maxpacket; ++ } ++ ++ if (core_if->dma_desc_enable) { ++ dwc_ep->desc_cnt = ++ dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm / ++ dwc_ep->bInterval; ++ } ++ ++ if (atomic_alloc) { ++ dwc_ep->pkt_info = ++ DWC_ALLOC_ATOMIC(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt); ++ } else { ++ dwc_ep->pkt_info = ++ DWC_ALLOC(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt); ++ } ++ if (!dwc_ep->pkt_info) { ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ return -DWC_E_NO_MEMORY; ++ } ++ if (core_if->pti_enh_enable) { ++ dwc_memset(dwc_ep->pkt_info, 0, ++ sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt); ++ } ++ ++ dwc_ep->cur_pkt = 0; ++ ep->iso_req_handle = req_handle; ++ ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ dwc_otg_iso_ep_start_transfer(core_if, dwc_ep); ++ return 0; ++} ++ ++int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *req_handle) ++{ ++ dwc_irqflags_t flags = 0; ++ dwc_otg_pcd_ep_t *ep; ++ dwc_ep_t *dwc_ep; ++ ++ ep = get_ep_from_handle(pcd, ep_handle); ++ if (!ep || !ep->desc || ep->dwc_ep.num == 0) { ++ DWC_WARN("bad ep\n"); ++ return -DWC_E_INVALID; ++ } ++ dwc_ep = &ep->dwc_ep; ++ ++ dwc_otg_iso_ep_stop_transfer(GET_CORE_IF(pcd), dwc_ep); ++ ++ DWC_FREE(dwc_ep->pkt_info); ++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++ if (ep->iso_req_handle != req_handle) { ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ return -DWC_E_INVALID; ++ } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ ++ ep->iso_req_handle = 0; ++ return 0; ++} ++ ++/** ++ * This function is used for perodical data exchnage between PCD and gadget drivers. ++ * for Isochronous EPs ++ * ++ * - Every time a sync period completes this function is called to ++ * perform data exchange between PCD and gadget ++ */ ++void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep, ++ void *req_handle) ++{ ++ int i; ++ dwc_ep_t *dwc_ep; ++ ++ dwc_ep = &ep->dwc_ep; ++ ++ DWC_SPINUNLOCK(ep->pcd->lock); ++ pcd->fops->isoc_complete(pcd, ep->priv, ep->iso_req_handle, ++ dwc_ep->proc_buf_num ^ 0x1); ++ DWC_SPINLOCK(ep->pcd->lock); ++ ++ for (i = 0; i < dwc_ep->pkt_cnt; ++i) { ++ dwc_ep->pkt_info[i].status = 0; ++ dwc_ep->pkt_info[i].offset = 0; ++ dwc_ep->pkt_info[i].length = 0; ++ } ++} ++ ++int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *iso_req_handle) ++{ ++ dwc_otg_pcd_ep_t *ep; ++ dwc_ep_t *dwc_ep; ++ ++ ep = get_ep_from_handle(pcd, ep_handle); ++ if (!ep->desc || ep->dwc_ep.num == 0) { ++ DWC_WARN("bad ep\n"); ++ return -DWC_E_INVALID; ++ } ++ dwc_ep = &ep->dwc_ep; ++ ++ return dwc_ep->pkt_cnt; ++} ++ ++void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *iso_req_handle, int packet, ++ int *status, int *actual, int *offset) ++{ ++ dwc_otg_pcd_ep_t *ep; ++ dwc_ep_t *dwc_ep; ++ ++ ep = get_ep_from_handle(pcd, ep_handle); ++ if (!ep) ++ DWC_WARN("bad ep\n"); ++ ++ dwc_ep = &ep->dwc_ep; ++ ++ *status = dwc_ep->pkt_info[packet].status; ++ *actual = dwc_ep->pkt_info[packet].length; ++ *offset = dwc_ep->pkt_info[packet].offset; ++} ++ ++#endif /* DWC_EN_ISOC */ ++ ++static void dwc_otg_pcd_init_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * pcd_ep, ++ uint32_t is_in, uint32_t ep_num) ++{ ++ /* Init EP structure */ ++ pcd_ep->desc = 0; ++ pcd_ep->pcd = pcd; ++ pcd_ep->stopped = 1; ++ pcd_ep->queue_sof = 0; ++ ++ /* Init DWC ep structure */ ++ pcd_ep->dwc_ep.is_in = is_in; ++ pcd_ep->dwc_ep.num = ep_num; ++ pcd_ep->dwc_ep.active = 0; ++ pcd_ep->dwc_ep.tx_fifo_num = 0; ++ /* Control until ep is actvated */ ++ pcd_ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL; ++ pcd_ep->dwc_ep.maxpacket = MAX_PACKET_SIZE; ++ pcd_ep->dwc_ep.dma_addr = 0; ++ pcd_ep->dwc_ep.start_xfer_buff = 0; ++ pcd_ep->dwc_ep.xfer_buff = 0; ++ pcd_ep->dwc_ep.xfer_len = 0; ++ pcd_ep->dwc_ep.xfer_count = 0; ++ pcd_ep->dwc_ep.sent_zlp = 0; ++ pcd_ep->dwc_ep.total_len = 0; ++ pcd_ep->dwc_ep.desc_addr = 0; ++ pcd_ep->dwc_ep.dma_desc_addr = 0; ++ DWC_CIRCLEQ_INIT(&pcd_ep->queue); ++} ++ ++/** ++ * Initialize ep's ++ */ ++static void dwc_otg_pcd_reinit(dwc_otg_pcd_t * pcd) ++{ ++ int i; ++ uint32_t hwcfg1; ++ dwc_otg_pcd_ep_t *ep; ++ int in_ep_cntr, out_ep_cntr; ++ uint32_t num_in_eps = (GET_CORE_IF(pcd))->dev_if->num_in_eps; ++ uint32_t num_out_eps = (GET_CORE_IF(pcd))->dev_if->num_out_eps; ++ ++ /** ++ * Initialize the EP0 structure. ++ */ ++ ep = &pcd->ep0; ++ dwc_otg_pcd_init_ep(pcd, ep, 0, 0); ++ ++ in_ep_cntr = 0; ++ hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 3; ++ for (i = 1; in_ep_cntr < num_in_eps; i++) { ++ if ((hwcfg1 & 0x1) == 0) { ++ dwc_otg_pcd_ep_t *ep = &pcd->in_ep[in_ep_cntr]; ++ in_ep_cntr++; ++ /** ++ * @todo NGS: Add direction to EP, based on contents ++ * of HWCFG1. Need a copy of HWCFG1 in pcd structure? ++ * sprintf(";r ++ */ ++ dwc_otg_pcd_init_ep(pcd, ep, 1 /* IN */ , i); ++ ++ DWC_CIRCLEQ_INIT(&ep->queue); ++ } ++ hwcfg1 >>= 2; ++ } ++ ++ out_ep_cntr = 0; ++ hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 2; ++ for (i = 1; out_ep_cntr < num_out_eps; i++) { ++ if ((hwcfg1 & 0x1) == 0) { ++ dwc_otg_pcd_ep_t *ep = &pcd->out_ep[out_ep_cntr]; ++ out_ep_cntr++; ++ /** ++ * @todo NGS: Add direction to EP, based on contents ++ * of HWCFG1. Need a copy of HWCFG1 in pcd structure? ++ * sprintf(";r ++ */ ++ dwc_otg_pcd_init_ep(pcd, ep, 0 /* OUT */ , i); ++ DWC_CIRCLEQ_INIT(&ep->queue); ++ } ++ hwcfg1 >>= 2; ++ } ++ ++ pcd->ep0state = EP0_DISCONNECT; ++ pcd->ep0.dwc_ep.maxpacket = MAX_EP0_SIZE; ++ pcd->ep0.dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL; ++} ++ ++/** ++ * This function is called when the SRP timer expires. The SRP should ++ * complete within 6 seconds. ++ */ ++static void srp_timeout(void *ptr) ++{ ++ gotgctl_data_t gotgctl; ++ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr; ++ volatile uint32_t *addr = &core_if->core_global_regs->gotgctl; ++ ++ gotgctl.d32 = DWC_READ_REG32(addr); ++ ++ core_if->srp_timer_started = 0; ++ ++ if (core_if->adp_enable) { ++ if (gotgctl.b.bsesvld == 0) { ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ DWC_PRINTF("SRP Timeout BSESSVLD = 0\n"); ++ /* Power off the core */ ++ if (core_if->power_down == 2) { ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if-> ++ core_global_regs->gpwrdn, ++ gpwrdn.d32, 0); ++ } ++ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, ++ gpwrdn.d32); ++ dwc_otg_adp_probe_start(core_if); ++ } else { ++ DWC_PRINTF("SRP Timeout BSESSVLD = 1\n"); ++ core_if->op_state = B_PERIPHERAL; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_pcd_start(core_if); ++ } ++ } ++ ++ if ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) && ++ (core_if->core_params->i2c_enable)) { ++ DWC_PRINTF("SRP Timeout\n"); ++ ++ if ((core_if->srp_success) && (gotgctl.b.bsesvld)) { ++ if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) { ++ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p); ++ } ++ ++ /* Clear Session Request */ ++ gotgctl.d32 = 0; ++ gotgctl.b.sesreq = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl, ++ gotgctl.d32, 0); ++ ++ core_if->srp_success = 0; ++ } else { ++ __DWC_ERROR("Device not connected/responding\n"); ++ gotgctl.b.sesreq = 0; ++ DWC_WRITE_REG32(addr, gotgctl.d32); ++ } ++ } else if (gotgctl.b.sesreq) { ++ DWC_PRINTF("SRP Timeout\n"); ++ ++ __DWC_ERROR("Device not connected/responding\n"); ++ gotgctl.b.sesreq = 0; ++ DWC_WRITE_REG32(addr, gotgctl.d32); ++ } else { ++ DWC_PRINTF(" SRP GOTGCTL=%0x\n", gotgctl.d32); ++ } ++} ++ ++/** ++ * Tasklet ++ * ++ */ ++extern void start_next_request(dwc_otg_pcd_ep_t * ep); ++ ++static void start_xfer_tasklet_func(void *data) ++{ ++ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data; ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ ++ int i; ++ depctl_data_t diepctl; ++ ++ DWC_DEBUGPL(DBG_PCDV, "Start xfer tasklet\n"); ++ ++ diepctl.d32 = DWC_READ_REG32(&core_if->dev_if->in_ep_regs[0]->diepctl); ++ ++ if (pcd->ep0.queue_sof) { ++ pcd->ep0.queue_sof = 0; ++ start_next_request(&pcd->ep0); ++ // break; ++ } ++ ++ for (i = 0; i < core_if->dev_if->num_in_eps; i++) { ++ depctl_data_t diepctl; ++ diepctl.d32 = ++ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl); ++ ++ if (pcd->in_ep[i].queue_sof) { ++ pcd->in_ep[i].queue_sof = 0; ++ start_next_request(&pcd->in_ep[i]); ++ // break; ++ } ++ } ++ ++ return; ++} ++ ++/** ++ * This function initialized the PCD portion of the driver. ++ * ++ */ ++dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if) ++{ ++ dwc_otg_pcd_t *pcd = NULL; ++ dwc_otg_dev_if_t *dev_if; ++ int i; ++ ++ /* ++ * Allocate PCD structure ++ */ ++ pcd = DWC_ALLOC(sizeof(dwc_otg_pcd_t)); ++ ++ if (pcd == NULL) { ++ return NULL; ++ } ++ ++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_SPINLOCK)) ++ DWC_SPINLOCK_ALLOC_LINUX_DEBUG(pcd->lock); ++#else ++ pcd->lock = DWC_SPINLOCK_ALLOC(); ++#endif ++ DWC_DEBUGPL(DBG_HCDV, "Init of PCD %p given core_if %p\n", ++ pcd, core_if);//GRAYG ++ if (!pcd->lock) { ++ DWC_ERROR("Could not allocate lock for pcd"); ++ DWC_FREE(pcd); ++ return NULL; ++ } ++ /* Set core_if's lock pointer to hcd->lock */ ++ core_if->lock = pcd->lock; ++ pcd->core_if = core_if; ++ ++ dev_if = core_if->dev_if; ++ dev_if->isoc_ep = NULL; ++ ++ if (core_if->hwcfg4.b.ded_fifo_en) { ++ DWC_PRINTF("Dedicated Tx FIFOs mode\n"); ++ } else { ++ DWC_PRINTF("Shared Tx FIFO mode\n"); ++ } ++ ++ /* ++ * Initialized the Core for Device mode here if there is nod ADP support. ++ * Otherwise it will be done later in dwc_otg_adp_start routine. ++ */ ++ if (dwc_otg_is_device_mode(core_if) /*&& !core_if->adp_enable*/) { ++ dwc_otg_core_dev_init(core_if); ++ } ++ ++ /* ++ * Register the PCD Callbacks. ++ */ ++ dwc_otg_cil_register_pcd_callbacks(core_if, &pcd_callbacks, pcd); ++ ++ /* ++ * Initialize the DMA buffer for SETUP packets ++ */ ++ if (GET_CORE_IF(pcd)->dma_enable) { ++ pcd->setup_pkt = ++ DWC_DMA_ALLOC(sizeof(*pcd->setup_pkt) * 5, ++ &pcd->setup_pkt_dma_handle); ++ if (pcd->setup_pkt == NULL) { ++ DWC_FREE(pcd); ++ return NULL; ++ } ++ ++ pcd->status_buf = ++ DWC_DMA_ALLOC(sizeof(uint16_t), ++ &pcd->status_buf_dma_handle); ++ if (pcd->status_buf == NULL) { ++ DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5, ++ pcd->setup_pkt, pcd->setup_pkt_dma_handle); ++ DWC_FREE(pcd); ++ return NULL; ++ } ++ ++ if (GET_CORE_IF(pcd)->dma_desc_enable) { ++ dev_if->setup_desc_addr[0] = ++ dwc_otg_ep_alloc_desc_chain ++ (&dev_if->dma_setup_desc_addr[0], 1); ++ dev_if->setup_desc_addr[1] = ++ dwc_otg_ep_alloc_desc_chain ++ (&dev_if->dma_setup_desc_addr[1], 1); ++ dev_if->in_desc_addr = ++ dwc_otg_ep_alloc_desc_chain ++ (&dev_if->dma_in_desc_addr, 1); ++ dev_if->out_desc_addr = ++ dwc_otg_ep_alloc_desc_chain ++ (&dev_if->dma_out_desc_addr, 1); ++ pcd->data_terminated = 0; ++ ++ if (dev_if->setup_desc_addr[0] == 0 ++ || dev_if->setup_desc_addr[1] == 0 ++ || dev_if->in_desc_addr == 0 ++ || dev_if->out_desc_addr == 0) { ++ ++ if (dev_if->out_desc_addr) ++ dwc_otg_ep_free_desc_chain ++ (dev_if->out_desc_addr, ++ dev_if->dma_out_desc_addr, 1); ++ if (dev_if->in_desc_addr) ++ dwc_otg_ep_free_desc_chain ++ (dev_if->in_desc_addr, ++ dev_if->dma_in_desc_addr, 1); ++ if (dev_if->setup_desc_addr[1]) ++ dwc_otg_ep_free_desc_chain ++ (dev_if->setup_desc_addr[1], ++ dev_if->dma_setup_desc_addr[1], 1); ++ if (dev_if->setup_desc_addr[0]) ++ dwc_otg_ep_free_desc_chain ++ (dev_if->setup_desc_addr[0], ++ dev_if->dma_setup_desc_addr[0], 1); ++ ++ DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5, ++ pcd->setup_pkt, ++ pcd->setup_pkt_dma_handle); ++ DWC_DMA_FREE(sizeof(*pcd->status_buf), ++ pcd->status_buf, ++ pcd->status_buf_dma_handle); ++ ++ DWC_FREE(pcd); ++ ++ return NULL; ++ } ++ } ++ } else { ++ pcd->setup_pkt = DWC_ALLOC(sizeof(*pcd->setup_pkt) * 5); ++ if (pcd->setup_pkt == NULL) { ++ DWC_FREE(pcd); ++ return NULL; ++ } ++ ++ pcd->status_buf = DWC_ALLOC(sizeof(uint16_t)); ++ if (pcd->status_buf == NULL) { ++ DWC_FREE(pcd->setup_pkt); ++ DWC_FREE(pcd); ++ return NULL; ++ } ++ } ++ ++ dwc_otg_pcd_reinit(pcd); ++ ++ /* Allocate the cfi object for the PCD */ ++#ifdef DWC_UTE_CFI ++ pcd->cfi = DWC_ALLOC(sizeof(cfiobject_t)); ++ if (NULL == pcd->cfi) ++ goto fail; ++ if (init_cfi(pcd->cfi)) { ++ CFI_INFO("%s: Failed to init the CFI object\n", __func__); ++ goto fail; ++ } ++#endif ++ ++ /* Initialize tasklets */ ++ pcd->start_xfer_tasklet = DWC_TASK_ALLOC("xfer_tasklet", ++ start_xfer_tasklet_func, pcd); ++ pcd->test_mode_tasklet = DWC_TASK_ALLOC("test_mode_tasklet", ++ do_test_mode, pcd); ++ ++ /* Initialize SRP timer */ ++ core_if->srp_timer = DWC_TIMER_ALLOC("SRP TIMER", srp_timeout, core_if); ++ ++ if (core_if->core_params->dev_out_nak) { ++ /** ++ * Initialize xfer timeout timer. Implemented for ++ * 2.93a feature "Device DDMA OUT NAK Enhancement" ++ */ ++ for(i = 0; i < MAX_EPS_CHANNELS; i++) { ++ pcd->core_if->ep_xfer_timer[i] = ++ DWC_TIMER_ALLOC("ep timer", ep_xfer_timeout, ++ &pcd->core_if->ep_xfer_info[i]); ++ } ++ } ++ ++ return pcd; ++#ifdef DWC_UTE_CFI ++fail: ++#endif ++ if (pcd->setup_pkt) ++ DWC_FREE(pcd->setup_pkt); ++ if (pcd->status_buf) ++ DWC_FREE(pcd->status_buf); ++#ifdef DWC_UTE_CFI ++ if (pcd->cfi) ++ DWC_FREE(pcd->cfi); ++#endif ++ if (pcd) ++ DWC_FREE(pcd); ++ return NULL; ++ ++} ++ ++/** ++ * Remove PCD specific data ++ */ ++void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if; ++ int i; ++ if (pcd->core_if->core_params->dev_out_nak) { ++ for (i = 0; i < MAX_EPS_CHANNELS; i++) { ++ DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[i]); ++ pcd->core_if->ep_xfer_info[i].state = 0; ++ } ++ } ++ ++ if (GET_CORE_IF(pcd)->dma_enable) { ++ DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5, pcd->setup_pkt, ++ pcd->setup_pkt_dma_handle); ++ DWC_DMA_FREE(sizeof(uint16_t), pcd->status_buf, ++ pcd->status_buf_dma_handle); ++ if (GET_CORE_IF(pcd)->dma_desc_enable) { ++ dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[0], ++ dev_if->dma_setup_desc_addr ++ [0], 1); ++ dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[1], ++ dev_if->dma_setup_desc_addr ++ [1], 1); ++ dwc_otg_ep_free_desc_chain(dev_if->in_desc_addr, ++ dev_if->dma_in_desc_addr, 1); ++ dwc_otg_ep_free_desc_chain(dev_if->out_desc_addr, ++ dev_if->dma_out_desc_addr, ++ 1); ++ } ++ } else { ++ DWC_FREE(pcd->setup_pkt); ++ DWC_FREE(pcd->status_buf); ++ } ++ DWC_SPINLOCK_FREE(pcd->lock); ++ /* Set core_if's lock pointer to NULL */ ++ pcd->core_if->lock = NULL; ++ ++ DWC_TASK_FREE(pcd->start_xfer_tasklet); ++ DWC_TASK_FREE(pcd->test_mode_tasklet); ++ if (pcd->core_if->core_params->dev_out_nak) { ++ for (i = 0; i < MAX_EPS_CHANNELS; i++) { ++ if (pcd->core_if->ep_xfer_timer[i]) { ++ DWC_TIMER_FREE(pcd->core_if->ep_xfer_timer[i]); ++ } ++ } ++ } ++ ++/* Release the CFI object's dynamic memory */ ++#ifdef DWC_UTE_CFI ++ if (pcd->cfi->ops.release) { ++ pcd->cfi->ops.release(pcd->cfi); ++ } ++#endif ++ ++ DWC_FREE(pcd); ++} ++ ++/** ++ * Returns whether registered pcd is dual speed or not ++ */ ++uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ ++ if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) || ++ ((core_if->hwcfg2.b.hs_phy_type == 2) && ++ (core_if->hwcfg2.b.fs_phy_type == 1) && ++ (core_if->core_params->ulpi_fs_ls))) { ++ return 0; ++ } ++ ++ return 1; ++} ++ ++/** ++ * Returns whether registered pcd is OTG capable or not ++ */ ++uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ gusbcfg_data_t usbcfg = {.d32 = 0 }; ++ ++ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); ++ if (!usbcfg.b.srpcap || !usbcfg.b.hnpcap) { ++ return 0; ++ } ++ ++ return 1; ++} ++ ++/** ++ * This function assigns periodic Tx FIFO to an periodic EP ++ * in shared Tx FIFO mode ++ */ ++static uint32_t assign_tx_fifo(dwc_otg_core_if_t * core_if) ++{ ++ uint32_t TxMsk = 1; ++ int i; ++ ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; ++i) { ++ if ((TxMsk & core_if->tx_msk) == 0) { ++ core_if->tx_msk |= TxMsk; ++ return i + 1; ++ } ++ TxMsk <<= 1; ++ } ++ return 0; ++} ++ ++/** ++ * This function assigns periodic Tx FIFO to an periodic EP ++ * in shared Tx FIFO mode ++ */ ++static uint32_t assign_perio_tx_fifo(dwc_otg_core_if_t * core_if) ++{ ++ uint32_t PerTxMsk = 1; ++ int i; ++ for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; ++i) { ++ if ((PerTxMsk & core_if->p_tx_msk) == 0) { ++ core_if->p_tx_msk |= PerTxMsk; ++ return i + 1; ++ } ++ PerTxMsk <<= 1; ++ } ++ return 0; ++} ++ ++/** ++ * This function releases periodic Tx FIFO ++ * in shared Tx FIFO mode ++ */ ++static void release_perio_tx_fifo(dwc_otg_core_if_t * core_if, ++ uint32_t fifo_num) ++{ ++ core_if->p_tx_msk = ++ (core_if->p_tx_msk & (1 << (fifo_num - 1))) ^ core_if->p_tx_msk; ++} ++ ++/** ++ * This function releases periodic Tx FIFO ++ * in shared Tx FIFO mode ++ */ ++static void release_tx_fifo(dwc_otg_core_if_t * core_if, uint32_t fifo_num) ++{ ++ core_if->tx_msk = ++ (core_if->tx_msk & (1 << (fifo_num - 1))) ^ core_if->tx_msk; ++} ++ ++/** ++ * This function is being called from gadget ++ * to enable PCD endpoint. ++ */ ++int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd, ++ const uint8_t * ep_desc, void *usb_ep) ++{ ++ int num, dir; ++ dwc_otg_pcd_ep_t *ep = NULL; ++ const usb_endpoint_descriptor_t *desc; ++ dwc_irqflags_t flags; ++ fifosize_data_t dptxfsiz = {.d32 = 0 }; ++ gdfifocfg_data_t gdfifocfg = {.d32 = 0 }; ++ gdfifocfg_data_t gdfifocfgbase = {.d32 = 0 }; ++ int retval = 0; ++ int i, epcount; ++ ++ desc = (const usb_endpoint_descriptor_t *)ep_desc; ++ ++ if (!desc) { ++ pcd->ep0.priv = usb_ep; ++ ep = &pcd->ep0; ++ retval = -DWC_E_INVALID; ++ goto out; ++ } ++ ++ num = UE_GET_ADDR(desc->bEndpointAddress); ++ dir = UE_GET_DIR(desc->bEndpointAddress); ++ ++ if (!desc->wMaxPacketSize) { ++ DWC_WARN("bad maxpacketsize\n"); ++ retval = -DWC_E_INVALID; ++ goto out; ++ } ++ ++ if (dir == UE_DIR_IN) { ++ epcount = pcd->core_if->dev_if->num_in_eps; ++ for (i = 0; i < epcount; i++) { ++ if (num == pcd->in_ep[i].dwc_ep.num) { ++ ep = &pcd->in_ep[i]; ++ break; ++ } ++ } ++ } else { ++ epcount = pcd->core_if->dev_if->num_out_eps; ++ for (i = 0; i < epcount; i++) { ++ if (num == pcd->out_ep[i].dwc_ep.num) { ++ ep = &pcd->out_ep[i]; ++ break; ++ } ++ } ++ } ++ ++ if (!ep) { ++ DWC_WARN("bad address\n"); ++ retval = -DWC_E_INVALID; ++ goto out; ++ } ++ ++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++ ++ ep->desc = desc; ++ ep->priv = usb_ep; ++ ++ /* ++ * Activate the EP ++ */ ++ ep->stopped = 0; ++ ++ ep->dwc_ep.is_in = (dir == UE_DIR_IN); ++ ep->dwc_ep.maxpacket = UGETW(desc->wMaxPacketSize); ++ ++ ep->dwc_ep.type = desc->bmAttributes & UE_XFERTYPE; ++ ++ if (ep->dwc_ep.is_in) { ++ if (!GET_CORE_IF(pcd)->en_multiple_tx_fifo) { ++ ep->dwc_ep.tx_fifo_num = 0; ++ ++ if (ep->dwc_ep.type == UE_ISOCHRONOUS) { ++ /* ++ * if ISOC EP then assign a Periodic Tx FIFO. ++ */ ++ ep->dwc_ep.tx_fifo_num = ++ assign_perio_tx_fifo(GET_CORE_IF(pcd)); ++ } ++ } else { ++ /* ++ * if Dedicated FIFOs mode is on then assign a Tx FIFO. ++ */ ++ ep->dwc_ep.tx_fifo_num = ++ assign_tx_fifo(GET_CORE_IF(pcd)); ++ } ++ ++ /* Calculating EP info controller base address */ ++ if (ep->dwc_ep.tx_fifo_num ++ && GET_CORE_IF(pcd)->en_multiple_tx_fifo) { ++ gdfifocfg.d32 = ++ DWC_READ_REG32(&GET_CORE_IF(pcd)-> ++ core_global_regs->gdfifocfg); ++ gdfifocfgbase.d32 = gdfifocfg.d32 >> 16; ++ dptxfsiz.d32 = ++ (DWC_READ_REG32 ++ (&GET_CORE_IF(pcd)->core_global_regs-> ++ dtxfsiz[ep->dwc_ep.tx_fifo_num - 1]) >> 16); ++ gdfifocfg.b.epinfobase = ++ gdfifocfgbase.d32 + dptxfsiz.d32; ++ if (GET_CORE_IF(pcd)->snpsid <= OTG_CORE_REV_2_94a) { ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)-> ++ core_global_regs->gdfifocfg, ++ gdfifocfg.d32); ++ } ++ } ++ } ++ /* Set initial data PID. */ ++ if (ep->dwc_ep.type == UE_BULK) { ++ ep->dwc_ep.data_pid_start = 0; ++ } ++ ++ /* Alloc DMA Descriptors */ ++ if (GET_CORE_IF(pcd)->dma_desc_enable) { ++#ifndef DWC_UTE_PER_IO ++ if (ep->dwc_ep.type != UE_ISOCHRONOUS) { ++#endif ++ ep->dwc_ep.desc_addr = ++ dwc_otg_ep_alloc_desc_chain(&ep-> ++ dwc_ep.dma_desc_addr, ++ MAX_DMA_DESC_CNT); ++ if (!ep->dwc_ep.desc_addr) { ++ DWC_WARN("%s, can't allocate DMA descriptor\n", ++ __func__); ++ retval = -DWC_E_SHUTDOWN; ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ goto out; ++ } ++#ifndef DWC_UTE_PER_IO ++ } ++#endif ++ } ++ ++ DWC_DEBUGPL(DBG_PCD, "Activate %s: type=%d, mps=%d desc=%p\n", ++ (ep->dwc_ep.is_in ? "IN" : "OUT"), ++ ep->dwc_ep.type, ep->dwc_ep.maxpacket, ep->desc); ++#ifdef DWC_UTE_PER_IO ++ ep->dwc_ep.xiso_bInterval = 1 << (ep->desc->bInterval - 1); ++#endif ++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) { ++ ep->dwc_ep.bInterval = 1 << (ep->desc->bInterval - 1); ++ ep->dwc_ep.frame_num = 0xFFFFFFFF; ++ } ++ ++ dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep); ++ ++#ifdef DWC_UTE_CFI ++ if (pcd->cfi->ops.ep_enable) { ++ pcd->cfi->ops.ep_enable(pcd->cfi, pcd, ep); ++ } ++#endif ++ ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ ++out: ++ return retval; ++} ++ ++/** ++ * This function is being called from gadget ++ * to disable PCD endpoint. ++ */ ++int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle) ++{ ++ dwc_otg_pcd_ep_t *ep; ++ dwc_irqflags_t flags; ++ dwc_otg_dev_dma_desc_t *desc_addr; ++ dwc_dma_t dma_desc_addr; ++ gdfifocfg_data_t gdfifocfgbase = {.d32 = 0 }; ++ gdfifocfg_data_t gdfifocfg = {.d32 = 0 }; ++ fifosize_data_t dptxfsiz = {.d32 = 0 }; ++ ++ ep = get_ep_from_handle(pcd, ep_handle); ++ ++ if (!ep || !ep->desc) { ++ DWC_DEBUGPL(DBG_PCD, "bad ep address\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++ ++ dwc_otg_request_nuke(ep); ++ ++ dwc_otg_ep_deactivate(GET_CORE_IF(pcd), &ep->dwc_ep); ++ if (pcd->core_if->core_params->dev_out_nak) { ++ DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[ep->dwc_ep.num]); ++ pcd->core_if->ep_xfer_info[ep->dwc_ep.num].state = 0; ++ } ++ ep->desc = NULL; ++ ep->stopped = 1; ++ ++ gdfifocfg.d32 = ++ DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs->gdfifocfg); ++ gdfifocfgbase.d32 = gdfifocfg.d32 >> 16; ++ ++ if (ep->dwc_ep.is_in) { ++ if (GET_CORE_IF(pcd)->en_multiple_tx_fifo) { ++ /* Flush the Tx FIFO */ ++ dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), ++ ep->dwc_ep.tx_fifo_num); ++ } ++ release_perio_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num); ++ release_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num); ++ if (GET_CORE_IF(pcd)->en_multiple_tx_fifo) { ++ /* Decreasing EPinfo Base Addr */ ++ dptxfsiz.d32 = ++ (DWC_READ_REG32 ++ (&GET_CORE_IF(pcd)-> ++ core_global_regs->dtxfsiz[ep->dwc_ep.tx_fifo_num-1]) >> 16); ++ gdfifocfg.b.epinfobase = gdfifocfgbase.d32 - dptxfsiz.d32; ++ if (GET_CORE_IF(pcd)->snpsid <= OTG_CORE_REV_2_94a) { ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gdfifocfg, ++ gdfifocfg.d32); ++ } ++ } ++ } ++ ++ /* Free DMA Descriptors */ ++ if (GET_CORE_IF(pcd)->dma_desc_enable) { ++ if (ep->dwc_ep.type != UE_ISOCHRONOUS) { ++ desc_addr = ep->dwc_ep.desc_addr; ++ dma_desc_addr = ep->dwc_ep.dma_desc_addr; ++ ++ /* Cannot call dma_free_coherent() with IRQs disabled */ ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ dwc_otg_ep_free_desc_chain(desc_addr, dma_desc_addr, ++ MAX_DMA_DESC_CNT); ++ ++ goto out_unlocked; ++ } ++ } ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ ++out_unlocked: ++ DWC_DEBUGPL(DBG_PCD, "%d %s disabled\n", ep->dwc_ep.num, ++ ep->dwc_ep.is_in ? "IN" : "OUT"); ++ return 0; ++ ++} ++ ++/******************************************************************************/ ++#ifdef DWC_UTE_PER_IO ++ ++/** ++ * Free the request and its extended parts ++ * ++ */ ++void dwc_pcd_xiso_ereq_free(dwc_otg_pcd_ep_t * ep, dwc_otg_pcd_request_t * req) ++{ ++ DWC_FREE(req->ext_req.per_io_frame_descs); ++ DWC_FREE(req); ++} ++ ++/** ++ * Start the next request in the endpoint's queue. ++ * ++ */ ++int dwc_otg_pcd_xiso_start_next_request(dwc_otg_pcd_t * pcd, ++ dwc_otg_pcd_ep_t * ep) ++{ ++ int i; ++ dwc_otg_pcd_request_t *req = NULL; ++ dwc_ep_t *dwcep = NULL; ++ struct dwc_iso_xreq_port *ereq = NULL; ++ struct dwc_iso_pkt_desc_port *ddesc_iso; ++ uint16_t nat; ++ depctl_data_t diepctl; ++ ++ dwcep = &ep->dwc_ep; ++ ++ if (dwcep->xiso_active_xfers > 0) { ++#if 0 //Disable this to decrease s/w overhead that is crucial for Isoc transfers ++ DWC_WARN("There are currently active transfers for EP%d \ ++ (active=%d; queued=%d)", dwcep->num, dwcep->xiso_active_xfers, ++ dwcep->xiso_queued_xfers); ++#endif ++ return 0; ++ } ++ ++ nat = UGETW(ep->desc->wMaxPacketSize); ++ nat = (nat >> 11) & 0x03; ++ ++ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ req = DWC_CIRCLEQ_FIRST(&ep->queue); ++ ereq = &req->ext_req; ++ ep->stopped = 0; ++ ++ /* Get the frame number */ ++ dwcep->xiso_frame_num = ++ dwc_otg_get_frame_number(GET_CORE_IF(pcd)); ++ DWC_DEBUG("FRM_NUM=%d", dwcep->xiso_frame_num); ++ ++ ddesc_iso = ereq->per_io_frame_descs; ++ ++ if (dwcep->is_in) { ++ /* Setup DMA Descriptor chain for IN Isoc request */ ++ for (i = 0; i < ereq->pio_pkt_count; i++) { ++ //if ((i % (nat + 1)) == 0) ++ if ( i > 0 ) ++ dwcep->xiso_frame_num = ++ (dwcep->xiso_bInterval + ++ dwcep->xiso_frame_num) & 0x3FFF; ++ dwcep->desc_addr[i].buf = ++ req->dma + ddesc_iso[i].offset; ++ dwcep->desc_addr[i].status.b_iso_in.txbytes = ++ ddesc_iso[i].length; ++ dwcep->desc_addr[i].status.b_iso_in.framenum = ++ dwcep->xiso_frame_num; ++ dwcep->desc_addr[i].status.b_iso_in.bs = ++ BS_HOST_READY; ++ dwcep->desc_addr[i].status.b_iso_in.txsts = 0; ++ dwcep->desc_addr[i].status.b_iso_in.sp = ++ (ddesc_iso[i].length % ++ dwcep->maxpacket) ? 1 : 0; ++ dwcep->desc_addr[i].status.b_iso_in.ioc = 0; ++ dwcep->desc_addr[i].status.b_iso_in.pid = nat + 1; ++ dwcep->desc_addr[i].status.b_iso_in.l = 0; ++ ++ /* Process the last descriptor */ ++ if (i == ereq->pio_pkt_count - 1) { ++ dwcep->desc_addr[i].status.b_iso_in.ioc = 1; ++ dwcep->desc_addr[i].status.b_iso_in.l = 1; ++ } ++ } ++ ++ /* Setup and start the transfer for this endpoint */ ++ dwcep->xiso_active_xfers++; ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->dev_if-> ++ in_ep_regs[dwcep->num]->diepdma, ++ dwcep->dma_desc_addr); ++ diepctl.d32 = 0; ++ diepctl.b.epena = 1; ++ diepctl.b.cnak = 1; ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->dev_if-> ++ in_ep_regs[dwcep->num]->diepctl, 0, ++ diepctl.d32); ++ } else { ++ /* Setup DMA Descriptor chain for OUT Isoc request */ ++ for (i = 0; i < ereq->pio_pkt_count; i++) { ++ //if ((i % (nat + 1)) == 0) ++ dwcep->xiso_frame_num = (dwcep->xiso_bInterval + ++ dwcep->xiso_frame_num) & 0x3FFF; ++ dwcep->desc_addr[i].buf = ++ req->dma + ddesc_iso[i].offset; ++ dwcep->desc_addr[i].status.b_iso_out.rxbytes = ++ ddesc_iso[i].length; ++ dwcep->desc_addr[i].status.b_iso_out.framenum = ++ dwcep->xiso_frame_num; ++ dwcep->desc_addr[i].status.b_iso_out.bs = ++ BS_HOST_READY; ++ dwcep->desc_addr[i].status.b_iso_out.rxsts = 0; ++ dwcep->desc_addr[i].status.b_iso_out.sp = ++ (ddesc_iso[i].length % ++ dwcep->maxpacket) ? 1 : 0; ++ dwcep->desc_addr[i].status.b_iso_out.ioc = 0; ++ dwcep->desc_addr[i].status.b_iso_out.pid = nat + 1; ++ dwcep->desc_addr[i].status.b_iso_out.l = 0; ++ ++ /* Process the last descriptor */ ++ if (i == ereq->pio_pkt_count - 1) { ++ dwcep->desc_addr[i].status.b_iso_out.ioc = 1; ++ dwcep->desc_addr[i].status.b_iso_out.l = 1; ++ } ++ } ++ ++ /* Setup and start the transfer for this endpoint */ ++ dwcep->xiso_active_xfers++; ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)-> ++ dev_if->out_ep_regs[dwcep->num]-> ++ doepdma, dwcep->dma_desc_addr); ++ diepctl.d32 = 0; ++ diepctl.b.epena = 1; ++ diepctl.b.cnak = 1; ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)-> ++ dev_if->out_ep_regs[dwcep->num]-> ++ doepctl, 0, diepctl.d32); ++ } ++ ++ } else { ++ ep->stopped = 1; ++ } ++ ++ return 0; ++} ++ ++/** ++ * - Remove the request from the queue ++ */ ++void complete_xiso_ep(dwc_otg_pcd_ep_t * ep) ++{ ++ dwc_otg_pcd_request_t *req = NULL; ++ struct dwc_iso_xreq_port *ereq = NULL; ++ struct dwc_iso_pkt_desc_port *ddesc_iso = NULL; ++ dwc_ep_t *dwcep = NULL; ++ int i; ++ ++ //DWC_DEBUG(); ++ dwcep = &ep->dwc_ep; ++ ++ /* Get the first pending request from the queue */ ++ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ req = DWC_CIRCLEQ_FIRST(&ep->queue); ++ if (!req) { ++ DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep); ++ return; ++ } ++ dwcep->xiso_active_xfers--; ++ dwcep->xiso_queued_xfers--; ++ /* Remove this request from the queue */ ++ DWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry); ++ } else { ++ DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep); ++ return; ++ } ++ ++ ep->stopped = 1; ++ ereq = &req->ext_req; ++ ddesc_iso = ereq->per_io_frame_descs; ++ ++ if (dwcep->xiso_active_xfers < 0) { ++ DWC_WARN("EP#%d (xiso_active_xfers=%d)", dwcep->num, ++ dwcep->xiso_active_xfers); ++ } ++ ++ /* Fill the Isoc descs of portable extended req from dma descriptors */ ++ for (i = 0; i < ereq->pio_pkt_count; i++) { ++ if (dwcep->is_in) { /* IN endpoints */ ++ ddesc_iso[i].actual_length = ddesc_iso[i].length - ++ dwcep->desc_addr[i].status.b_iso_in.txbytes; ++ ddesc_iso[i].status = ++ dwcep->desc_addr[i].status.b_iso_in.txsts; ++ } else { /* OUT endpoints */ ++ ddesc_iso[i].actual_length = ddesc_iso[i].length - ++ dwcep->desc_addr[i].status.b_iso_out.rxbytes; ++ ddesc_iso[i].status = ++ dwcep->desc_addr[i].status.b_iso_out.rxsts; ++ } ++ } ++ ++ DWC_SPINUNLOCK(ep->pcd->lock); ++ ++ /* Call the completion function in the non-portable logic */ ++ ep->pcd->fops->xisoc_complete(ep->pcd, ep->priv, req->priv, 0, ++ &req->ext_req); ++ ++ DWC_SPINLOCK(ep->pcd->lock); ++ ++ /* Free the request - specific freeing needed for extended request object */ ++ dwc_pcd_xiso_ereq_free(ep, req); ++ ++ /* Start the next request */ ++ dwc_otg_pcd_xiso_start_next_request(ep->pcd, ep); ++ ++ return; ++} ++ ++/** ++ * Create and initialize the Isoc pkt descriptors of the extended request. ++ * ++ */ ++static int dwc_otg_pcd_xiso_create_pkt_descs(dwc_otg_pcd_request_t * req, ++ void *ereq_nonport, ++ int atomic_alloc) ++{ ++ struct dwc_iso_xreq_port *ereq = NULL; ++ struct dwc_iso_xreq_port *req_mapped = NULL; ++ struct dwc_iso_pkt_desc_port *ipds = NULL; /* To be created in this function */ ++ uint32_t pkt_count; ++ int i; ++ ++ ereq = &req->ext_req; ++ req_mapped = (struct dwc_iso_xreq_port *)ereq_nonport; ++ pkt_count = req_mapped->pio_pkt_count; ++ ++ /* Create the isoc descs */ ++ if (atomic_alloc) { ++ ipds = DWC_ALLOC_ATOMIC(sizeof(*ipds) * pkt_count); ++ } else { ++ ipds = DWC_ALLOC(sizeof(*ipds) * pkt_count); ++ } ++ ++ if (!ipds) { ++ DWC_ERROR("Failed to allocate isoc descriptors"); ++ return -DWC_E_NO_MEMORY; ++ } ++ ++ /* Initialize the extended request fields */ ++ ereq->per_io_frame_descs = ipds; ++ ereq->error_count = 0; ++ ereq->pio_alloc_pkt_count = pkt_count; ++ ereq->pio_pkt_count = pkt_count; ++ ereq->tr_sub_flags = req_mapped->tr_sub_flags; ++ ++ /* Init the Isoc descriptors */ ++ for (i = 0; i < pkt_count; i++) { ++ ipds[i].length = req_mapped->per_io_frame_descs[i].length; ++ ipds[i].offset = req_mapped->per_io_frame_descs[i].offset; ++ ipds[i].status = req_mapped->per_io_frame_descs[i].status; /* 0 */ ++ ipds[i].actual_length = ++ req_mapped->per_io_frame_descs[i].actual_length; ++ } ++ ++ return 0; ++} ++ ++static void prn_ext_request(struct dwc_iso_xreq_port *ereq) ++{ ++ struct dwc_iso_pkt_desc_port *xfd = NULL; ++ int i; ++ ++ DWC_DEBUG("per_io_frame_descs=%p", ereq->per_io_frame_descs); ++ DWC_DEBUG("tr_sub_flags=%d", ereq->tr_sub_flags); ++ DWC_DEBUG("error_count=%d", ereq->error_count); ++ DWC_DEBUG("pio_alloc_pkt_count=%d", ereq->pio_alloc_pkt_count); ++ DWC_DEBUG("pio_pkt_count=%d", ereq->pio_pkt_count); ++ DWC_DEBUG("res=%d", ereq->res); ++ ++ for (i = 0; i < ereq->pio_pkt_count; i++) { ++ xfd = &ereq->per_io_frame_descs[0]; ++ DWC_DEBUG("FD #%d", i); ++ ++ DWC_DEBUG("xfd->actual_length=%d", xfd->actual_length); ++ DWC_DEBUG("xfd->length=%d", xfd->length); ++ DWC_DEBUG("xfd->offset=%d", xfd->offset); ++ DWC_DEBUG("xfd->status=%d", xfd->status); ++ } ++} ++ ++/** ++ * ++ */ ++int dwc_otg_pcd_xiso_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle, ++ uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen, ++ int zero, void *req_handle, int atomic_alloc, ++ void *ereq_nonport) ++{ ++ dwc_otg_pcd_request_t *req = NULL; ++ dwc_otg_pcd_ep_t *ep; ++ dwc_irqflags_t flags; ++ int res; ++ ++ ep = get_ep_from_handle(pcd, ep_handle); ++ if (!ep) { ++ DWC_WARN("bad ep\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ /* We support this extension only for DDMA mode */ ++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) ++ if (!GET_CORE_IF(pcd)->dma_desc_enable) ++ return -DWC_E_INVALID; ++ ++ /* Create a dwc_otg_pcd_request_t object */ ++ if (atomic_alloc) { ++ req = DWC_ALLOC_ATOMIC(sizeof(*req)); ++ } else { ++ req = DWC_ALLOC(sizeof(*req)); ++ } ++ ++ if (!req) { ++ return -DWC_E_NO_MEMORY; ++ } ++ ++ /* Create the Isoc descs for this request which shall be the exact match ++ * of the structure sent to us from the non-portable logic */ ++ res = ++ dwc_otg_pcd_xiso_create_pkt_descs(req, ereq_nonport, atomic_alloc); ++ if (res) { ++ DWC_WARN("Failed to init the Isoc descriptors"); ++ DWC_FREE(req); ++ return res; ++ } ++ ++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++ ++ DWC_CIRCLEQ_INIT_ENTRY(req, queue_entry); ++ req->buf = buf; ++ req->dma = dma_buf; ++ req->length = buflen; ++ req->sent_zlp = zero; ++ req->priv = req_handle; ++ ++ //DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++ ep->dwc_ep.dma_addr = dma_buf; ++ ep->dwc_ep.start_xfer_buff = buf; ++ ep->dwc_ep.xfer_buff = buf; ++ ep->dwc_ep.xfer_len = 0; ++ ep->dwc_ep.xfer_count = 0; ++ ep->dwc_ep.sent_zlp = 0; ++ ep->dwc_ep.total_len = buflen; ++ ++ /* Add this request to the tail */ ++ DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry); ++ ep->dwc_ep.xiso_queued_xfers++; ++ ++//DWC_DEBUG("CP_0"); ++//DWC_DEBUG("req->ext_req.tr_sub_flags=%d", req->ext_req.tr_sub_flags); ++//prn_ext_request((struct dwc_iso_xreq_port *) ereq_nonport); ++//prn_ext_request(&req->ext_req); ++ ++ //DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ ++ /* If the req->status == ASAP then check if there is any active transfer ++ * for this endpoint. If no active transfers, then get the first entry ++ * from the queue and start that transfer ++ */ ++ if (req->ext_req.tr_sub_flags == DWC_EREQ_TF_ASAP) { ++ res = dwc_otg_pcd_xiso_start_next_request(pcd, ep); ++ if (res) { ++ DWC_WARN("Failed to start the next Isoc transfer"); ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ DWC_FREE(req); ++ return res; ++ } ++ } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ return 0; ++} ++ ++#endif ++/* END ifdef DWC_UTE_PER_IO ***************************************************/ ++int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle, ++ uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen, ++ int zero, void *req_handle, int atomic_alloc) ++{ ++ dwc_irqflags_t flags; ++ dwc_otg_pcd_request_t *req; ++ dwc_otg_pcd_ep_t *ep; ++ uint32_t max_transfer; ++ ++ ep = get_ep_from_handle(pcd, ep_handle); ++ if (!ep || (!ep->desc && ep->dwc_ep.num != 0)) { ++ DWC_WARN("bad ep\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (atomic_alloc) { ++ req = DWC_ALLOC_ATOMIC(sizeof(*req)); ++ } else { ++ req = DWC_ALLOC(sizeof(*req)); ++ } ++ ++ if (!req) { ++ return -DWC_E_NO_MEMORY; ++ } ++ DWC_CIRCLEQ_INIT_ENTRY(req, queue_entry); ++ if (!GET_CORE_IF(pcd)->core_params->opt) { ++ if (ep->dwc_ep.num != 0) { ++ DWC_ERROR("queue req %p, len %d buf %p\n", ++ req_handle, buflen, buf); ++ } ++ } ++ ++ req->buf = buf; ++ req->dma = dma_buf; ++ req->length = buflen; ++ req->sent_zlp = zero; ++ req->priv = req_handle; ++ req->dw_align_buf = NULL; ++ if ((dma_buf & 0x3) && GET_CORE_IF(pcd)->dma_enable ++ && !GET_CORE_IF(pcd)->dma_desc_enable) ++ req->dw_align_buf = DWC_DMA_ALLOC(buflen, ++ &req->dw_align_buf_dma); ++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++ ++ /* ++ * After adding request to the queue for IN ISOC wait for In Token Received ++ * when TX FIFO is empty interrupt and for OUT ISOC wait for OUT Token ++ * Received when EP is disabled interrupt to obtain starting microframe ++ * (odd/even) start transfer ++ */ ++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) { ++ if (req != 0) { ++ depctl_data_t depctl = {.d32 = ++ DWC_READ_REG32(&pcd->core_if->dev_if-> ++ in_ep_regs[ep->dwc_ep.num]-> ++ diepctl) }; ++ ++pcd->request_pending; ++ ++ DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry); ++ if (ep->dwc_ep.is_in) { ++ depctl.b.cnak = 1; ++ DWC_WRITE_REG32(&pcd->core_if->dev_if-> ++ in_ep_regs[ep->dwc_ep.num]-> ++ diepctl, depctl.d32); ++ } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ } ++ return 0; ++ } ++ ++ /* ++ * For EP0 IN without premature status, zlp is required? ++ */ ++ if (ep->dwc_ep.num == 0 && ep->dwc_ep.is_in) { ++ DWC_DEBUGPL(DBG_PCDV, "%d-OUT ZLP\n", ep->dwc_ep.num); ++ //_req->zero = 1; ++ } ++ ++ /* Start the transfer */ ++ if (DWC_CIRCLEQ_EMPTY(&ep->queue) && !ep->stopped) { ++ /* EP0 Transfer? */ ++ if (ep->dwc_ep.num == 0) { ++ switch (pcd->ep0state) { ++ case EP0_IN_DATA_PHASE: ++ DWC_DEBUGPL(DBG_PCD, ++ "%s ep0: EP0_IN_DATA_PHASE\n", ++ __func__); ++ break; ++ ++ case EP0_OUT_DATA_PHASE: ++ DWC_DEBUGPL(DBG_PCD, ++ "%s ep0: EP0_OUT_DATA_PHASE\n", ++ __func__); ++ if (pcd->request_config) { ++ /* Complete STATUS PHASE */ ++ ep->dwc_ep.is_in = 1; ++ pcd->ep0state = EP0_IN_STATUS_PHASE; ++ } ++ break; ++ ++ case EP0_IN_STATUS_PHASE: ++ DWC_DEBUGPL(DBG_PCD, ++ "%s ep0: EP0_IN_STATUS_PHASE\n", ++ __func__); ++ break; ++ ++ default: ++ DWC_DEBUGPL(DBG_ANY, "ep0: odd state %d\n", ++ pcd->ep0state); ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ return -DWC_E_SHUTDOWN; ++ } ++ ++ ep->dwc_ep.dma_addr = dma_buf; ++ ep->dwc_ep.start_xfer_buff = buf; ++ ep->dwc_ep.xfer_buff = buf; ++ ep->dwc_ep.xfer_len = buflen; ++ ep->dwc_ep.xfer_count = 0; ++ ep->dwc_ep.sent_zlp = 0; ++ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len; ++ ++ if (zero) { ++ if ((ep->dwc_ep.xfer_len % ++ ep->dwc_ep.maxpacket == 0) ++ && (ep->dwc_ep.xfer_len != 0)) { ++ ep->dwc_ep.sent_zlp = 1; ++ } ++ ++ } ++ ++ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), ++ &ep->dwc_ep); ++ } // non-ep0 endpoints ++ else { ++#ifdef DWC_UTE_CFI ++ if (ep->dwc_ep.buff_mode != BM_STANDARD) { ++ /* store the request length */ ++ ep->dwc_ep.cfi_req_len = buflen; ++ pcd->cfi->ops.build_descriptors(pcd->cfi, pcd, ++ ep, req); ++ } else { ++#endif ++ max_transfer = ++ GET_CORE_IF(ep->pcd)->core_params-> ++ max_transfer_size; ++ ++ /* Setup and start the Transfer */ ++ if (req->dw_align_buf){ ++ if (ep->dwc_ep.is_in) ++ dwc_memcpy(req->dw_align_buf, ++ buf, buflen); ++ ep->dwc_ep.dma_addr = ++ req->dw_align_buf_dma; ++ ep->dwc_ep.start_xfer_buff = ++ req->dw_align_buf; ++ ep->dwc_ep.xfer_buff = ++ req->dw_align_buf; ++ } else { ++ ep->dwc_ep.dma_addr = dma_buf; ++ ep->dwc_ep.start_xfer_buff = buf; ++ ep->dwc_ep.xfer_buff = buf; ++ } ++ ep->dwc_ep.xfer_len = 0; ++ ep->dwc_ep.xfer_count = 0; ++ ep->dwc_ep.sent_zlp = 0; ++ ep->dwc_ep.total_len = buflen; ++ ++ ep->dwc_ep.maxxfer = max_transfer; ++ if (GET_CORE_IF(pcd)->dma_desc_enable) { ++ uint32_t out_max_xfer = ++ DDMA_MAX_TRANSFER_SIZE - ++ (DDMA_MAX_TRANSFER_SIZE % 4); ++ if (ep->dwc_ep.is_in) { ++ if (ep->dwc_ep.maxxfer > ++ DDMA_MAX_TRANSFER_SIZE) { ++ ep->dwc_ep.maxxfer = ++ DDMA_MAX_TRANSFER_SIZE; ++ } ++ } else { ++ if (ep->dwc_ep.maxxfer > ++ out_max_xfer) { ++ ep->dwc_ep.maxxfer = ++ out_max_xfer; ++ } ++ } ++ } ++ if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) { ++ ep->dwc_ep.maxxfer -= ++ (ep->dwc_ep.maxxfer % ++ ep->dwc_ep.maxpacket); ++ } ++ ++ if (zero) { ++ if ((ep->dwc_ep.total_len % ++ ep->dwc_ep.maxpacket == 0) ++ && (ep->dwc_ep.total_len != 0)) { ++ ep->dwc_ep.sent_zlp = 1; ++ } ++ } ++#ifdef DWC_UTE_CFI ++ } ++#endif ++ dwc_otg_ep_start_transfer(GET_CORE_IF(pcd), ++ &ep->dwc_ep); ++ } ++ } ++ ++ if (req != 0) { ++ ++pcd->request_pending; ++ DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry); ++ if (ep->dwc_ep.is_in && ep->stopped ++ && !(GET_CORE_IF(pcd)->dma_enable)) { ++ /** @todo NGS Create a function for this. */ ++ diepmsk_data_t diepmsk = {.d32 = 0 }; ++ diepmsk.b.intktxfemp = 1; ++ if (GET_CORE_IF(pcd)->multiproc_int_enable) { ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)-> ++ dev_if->dev_global_regs->diepeachintmsk ++ [ep->dwc_ep.num], 0, ++ diepmsk.d32); ++ } else { ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)-> ++ dev_if->dev_global_regs-> ++ diepmsk, 0, diepmsk.d32); ++ } ++ ++ } ++ } ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ ++ return 0; ++} ++ ++int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *req_handle) ++{ ++ dwc_irqflags_t flags; ++ dwc_otg_pcd_request_t *req; ++ dwc_otg_pcd_ep_t *ep; ++ ++ ep = get_ep_from_handle(pcd, ep_handle); ++ if (!ep || (!ep->desc && ep->dwc_ep.num != 0)) { ++ DWC_WARN("bad argument\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++ ++ /* make sure it's actually queued on this endpoint */ ++ DWC_CIRCLEQ_FOREACH(req, &ep->queue, queue_entry) { ++ if (req->priv == (void *)req_handle) { ++ break; ++ } ++ } ++ ++ if (req->priv != (void *)req_handle) { ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ return -DWC_E_INVALID; ++ } ++ ++ if (!DWC_CIRCLEQ_EMPTY_ENTRY(req, queue_entry)) { ++ dwc_otg_request_done(ep, req, -DWC_E_RESTART); ++ } else { ++ req = NULL; ++ } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ ++ return req ? 0 : -DWC_E_SHUTDOWN; ++ ++} ++ ++/** ++ * dwc_otg_pcd_ep_wedge - sets the halt feature and ignores clear requests ++ * ++ * Use this to stall an endpoint and ignore CLEAR_FEATURE(HALT_ENDPOINT) ++ * requests. If the gadget driver clears the halt status, it will ++ * automatically unwedge the endpoint. ++ * ++ * Returns zero on success, else negative DWC error code. ++ */ ++int dwc_otg_pcd_ep_wedge(dwc_otg_pcd_t * pcd, void *ep_handle) ++{ ++ dwc_otg_pcd_ep_t *ep; ++ dwc_irqflags_t flags; ++ int retval = 0; ++ ++ ep = get_ep_from_handle(pcd, ep_handle); ++ ++ if ((!ep->desc && ep != &pcd->ep0) || ++ (ep->desc && (ep->desc->bmAttributes == UE_ISOCHRONOUS))) { ++ DWC_WARN("%s, bad ep\n", __func__); ++ return -DWC_E_INVALID; ++ } ++ ++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ DWC_WARN("%d %s XFer In process\n", ep->dwc_ep.num, ++ ep->dwc_ep.is_in ? "IN" : "OUT"); ++ retval = -DWC_E_AGAIN; ++ } else { ++ /* This code needs to be reviewed */ ++ if (ep->dwc_ep.is_in == 1 && GET_CORE_IF(pcd)->dma_desc_enable) { ++ dtxfsts_data_t txstatus; ++ fifosize_data_t txfifosize; ++ ++ txfifosize.d32 = ++ DWC_READ_REG32(&GET_CORE_IF(pcd)-> ++ core_global_regs->dtxfsiz[ep->dwc_ep. ++ tx_fifo_num]); ++ txstatus.d32 = ++ DWC_READ_REG32(&GET_CORE_IF(pcd)-> ++ dev_if->in_ep_regs[ep->dwc_ep.num]-> ++ dtxfsts); ++ ++ if (txstatus.b.txfspcavail < txfifosize.b.depth) { ++ DWC_WARN("%s() Data In Tx Fifo\n", __func__); ++ retval = -DWC_E_AGAIN; ++ } else { ++ if (ep->dwc_ep.num == 0) { ++ pcd->ep0state = EP0_STALL; ++ } ++ ++ ep->stopped = 1; ++ dwc_otg_ep_set_stall(GET_CORE_IF(pcd), ++ &ep->dwc_ep); ++ } ++ } else { ++ if (ep->dwc_ep.num == 0) { ++ pcd->ep0state = EP0_STALL; ++ } ++ ++ ep->stopped = 1; ++ dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep->dwc_ep); ++ } ++ } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ ++ return retval; ++} ++ ++int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value) ++{ ++ dwc_otg_pcd_ep_t *ep; ++ dwc_irqflags_t flags; ++ int retval = 0; ++ ++ ep = get_ep_from_handle(pcd, ep_handle); ++ ++ if (!ep || (!ep->desc && ep != &pcd->ep0) || ++ (ep->desc && (ep->desc->bmAttributes == UE_ISOCHRONOUS))) { ++ DWC_WARN("%s, bad ep\n", __func__); ++ return -DWC_E_INVALID; ++ } ++ ++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ DWC_WARN("%d %s XFer In process\n", ep->dwc_ep.num, ++ ep->dwc_ep.is_in ? "IN" : "OUT"); ++ retval = -DWC_E_AGAIN; ++ } else if (value == 0) { ++ dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep); ++ } else if (value == 1) { ++ if (ep->dwc_ep.is_in == 1 && GET_CORE_IF(pcd)->dma_desc_enable) { ++ dtxfsts_data_t txstatus; ++ fifosize_data_t txfifosize; ++ ++ txfifosize.d32 = ++ DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs-> ++ dtxfsiz[ep->dwc_ep.tx_fifo_num]); ++ txstatus.d32 = ++ DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if-> ++ in_ep_regs[ep->dwc_ep.num]->dtxfsts); ++ ++ if (txstatus.b.txfspcavail < txfifosize.b.depth) { ++ DWC_WARN("%s() Data In Tx Fifo\n", __func__); ++ retval = -DWC_E_AGAIN; ++ } else { ++ if (ep->dwc_ep.num == 0) { ++ pcd->ep0state = EP0_STALL; ++ } ++ ++ ep->stopped = 1; ++ dwc_otg_ep_set_stall(GET_CORE_IF(pcd), ++ &ep->dwc_ep); ++ } ++ } else { ++ if (ep->dwc_ep.num == 0) { ++ pcd->ep0state = EP0_STALL; ++ } ++ ++ ep->stopped = 1; ++ dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep->dwc_ep); ++ } ++ } else if (value == 2) { ++ ep->dwc_ep.stall_clear_flag = 0; ++ } else if (value == 3) { ++ ep->dwc_ep.stall_clear_flag = 1; ++ } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ ++ return retval; ++} ++ ++/** ++ * This function initiates remote wakeup of the host from suspend state. ++ */ ++void dwc_otg_pcd_rem_wkup_from_suspend(dwc_otg_pcd_t * pcd, int set) ++{ ++ dctl_data_t dctl = { 0 }; ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dsts_data_t dsts; ++ ++ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); ++ if (!dsts.b.suspsts) { ++ DWC_WARN("Remote wakeup while is not in suspend state\n"); ++ } ++ /* Check if DEVICE_REMOTE_WAKEUP feature enabled */ ++ if (pcd->remote_wakeup_enable) { ++ if (set) { ++ ++ if (core_if->adp_enable) { ++ gpwrdn_data_t gpwrdn; ++ ++ dwc_otg_adp_probe_stop(core_if); ++ ++ /* Mask SRP detected interrupt from Power Down Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.srp_det_msk = 1; ++ DWC_MODIFY_REG32(&core_if-> ++ core_global_regs->gpwrdn, ++ gpwrdn.d32, 0); ++ ++ /* Disable Power Down Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if-> ++ core_global_regs->gpwrdn, ++ gpwrdn.d32, 0); ++ ++ /* ++ * Initialize the Core for Device mode. ++ */ ++ core_if->op_state = B_PERIPHERAL; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_pcd_start(core_if); ++ ++ dwc_otg_initiate_srp(core_if); ++ } ++ ++ dctl.b.rmtwkupsig = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> ++ dctl, 0, dctl.d32); ++ DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n"); ++ ++ dwc_mdelay(2); ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> ++ dctl, dctl.d32, 0); ++ DWC_DEBUGPL(DBG_PCD, "Clear Remote Wakeup\n"); ++ } ++ } else { ++ DWC_DEBUGPL(DBG_PCD, "Remote Wakeup is disabled\n"); ++ } ++} ++ ++#ifdef CONFIG_USB_DWC_OTG_LPM ++/** ++ * This function initiates remote wakeup of the host from L1 sleep state. ++ */ ++void dwc_otg_pcd_rem_wkup_from_sleep(dwc_otg_pcd_t * pcd, int set) ++{ ++ glpmcfg_data_t lpmcfg; ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++ ++ /* Check if we are in L1 state */ ++ if (!lpmcfg.b.prt_sleep_sts) { ++ DWC_DEBUGPL(DBG_PCD, "Device is not in sleep state\n"); ++ return; ++ } ++ ++ /* Check if host allows remote wakeup */ ++ if (!lpmcfg.b.rem_wkup_en) { ++ DWC_DEBUGPL(DBG_PCD, "Host does not allow remote wakeup\n"); ++ return; ++ } ++ ++ /* Check if Resume OK */ ++ if (!lpmcfg.b.sleep_state_resumeok) { ++ DWC_DEBUGPL(DBG_PCD, "Sleep state resume is not OK\n"); ++ return; ++ } ++ ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++ lpmcfg.b.en_utmi_sleep = 0; ++ lpmcfg.b.hird_thres &= (~(1 << 4)); ++ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32); ++ ++ if (set) { ++ dctl_data_t dctl = {.d32 = 0 }; ++ dctl.b.rmtwkupsig = 1; ++ /* Set RmtWkUpSig bit to start remote wakup signaling. ++ * Hardware will automatically clear this bit. ++ */ ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, ++ 0, dctl.d32); ++ DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n"); ++ } ++ ++} ++#endif ++ ++/** ++ * Performs remote wakeup. ++ */ ++void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_irqflags_t flags; ++ if (dwc_otg_is_device_mode(core_if)) { ++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ if (core_if->lx_state == DWC_OTG_L1) { ++ dwc_otg_pcd_rem_wkup_from_sleep(pcd, set); ++ } else { ++#endif ++ dwc_otg_pcd_rem_wkup_from_suspend(pcd, set); ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ } ++#endif ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ } ++ return; ++} ++ ++void dwc_otg_pcd_disconnect_us(dwc_otg_pcd_t * pcd, int no_of_usecs) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dctl_data_t dctl = { 0 }; ++ ++ if (dwc_otg_is_device_mode(core_if)) { ++ dctl.b.sftdiscon = 1; ++ DWC_PRINTF("Soft disconnect for %d useconds\n",no_of_usecs); ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32); ++ dwc_udelay(no_of_usecs); ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32,0); ++ ++ } else{ ++ DWC_PRINTF("NOT SUPPORTED IN HOST MODE\n"); ++ } ++ return; ++ ++} ++ ++int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd) ++{ ++ dsts_data_t dsts; ++ gotgctl_data_t gotgctl; ++ ++ /* ++ * This function starts the Protocol if no session is in progress. If ++ * a session is already in progress, but the device is suspended, ++ * remote wakeup signaling is started. ++ */ ++ ++ /* Check if valid session */ ++ gotgctl.d32 = ++ DWC_READ_REG32(&(GET_CORE_IF(pcd)->core_global_regs->gotgctl)); ++ if (gotgctl.b.bsesvld) { ++ /* Check if suspend state */ ++ dsts.d32 = ++ DWC_READ_REG32(& ++ (GET_CORE_IF(pcd)->dev_if-> ++ dev_global_regs->dsts)); ++ if (dsts.b.suspsts) { ++ dwc_otg_pcd_remote_wakeup(pcd, 1); ++ } ++ } else { ++ dwc_otg_pcd_initiate_srp(pcd); ++ } ++ ++ return 0; ++ ++} ++ ++/** ++ * Start the SRP timer to detect when the SRP does not complete within ++ * 6 seconds. ++ * ++ * @param pcd the pcd structure. ++ */ ++void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd) ++{ ++ dwc_irqflags_t flags; ++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++ dwc_otg_initiate_srp(GET_CORE_IF(pcd)); ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++} ++ ++int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd) ++{ ++ return dwc_otg_get_frame_number(GET_CORE_IF(pcd)); ++} ++ ++int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd) ++{ ++ return GET_CORE_IF(pcd)->core_params->lpm_enable; ++} ++ ++uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd) ++{ ++ return pcd->b_hnp_enable; ++} ++ ++uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd) ++{ ++ return pcd->a_hnp_support; ++} ++ ++uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd) ++{ ++ return pcd->a_alt_hnp_support; ++} ++ ++int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd) ++{ ++ return pcd->remote_wakeup_enable; ++} ++ ++#endif /* DWC_HOST_ONLY */ +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_pcd.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd.h +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_pcd.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd.h 2015-11-29 09:42:39.923098428 +0100 +@@ -0,0 +1,266 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.h $ ++ * $Revision: #48 $ ++ * $Date: 2012/08/10 $ ++ * $Change: 2047372 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_HOST_ONLY ++#if !defined(__DWC_PCD_H__) ++#define __DWC_PCD_H__ ++ ++#include "dwc_otg_os_dep.h" ++#include "usb.h" ++#include "dwc_otg_cil.h" ++#include "dwc_otg_pcd_if.h" ++struct cfiobject; ++ ++/** ++ * @file ++ * ++ * This file contains the structures, constants, and interfaces for ++ * the Perpherial Contoller Driver (PCD). ++ * ++ * The Peripheral Controller Driver (PCD) for Linux will implement the ++ * Gadget API, so that the existing Gadget drivers can be used. For ++ * the Mass Storage Function driver the File-backed USB Storage Gadget ++ * (FBS) driver will be used. The FBS driver supports the ++ * Control-Bulk (CB), Control-Bulk-Interrupt (CBI), and Bulk-Only ++ * transports. ++ * ++ */ ++ ++/** Invalid DMA Address */ ++#define DWC_DMA_ADDR_INVALID (~(dwc_dma_t)0) ++ ++/** Max Transfer size for any EP */ ++#define DDMA_MAX_TRANSFER_SIZE 65535 ++ ++/** ++ * Get the pointer to the core_if from the pcd pointer. ++ */ ++#define GET_CORE_IF( _pcd ) (_pcd->core_if) ++ ++/** ++ * States of EP0. ++ */ ++typedef enum ep0_state { ++ EP0_DISCONNECT, /* no host */ ++ EP0_IDLE, ++ EP0_IN_DATA_PHASE, ++ EP0_OUT_DATA_PHASE, ++ EP0_IN_STATUS_PHASE, ++ EP0_OUT_STATUS_PHASE, ++ EP0_STALL, ++} ep0state_e; ++ ++/** Fordward declaration.*/ ++struct dwc_otg_pcd; ++ ++/** DWC_otg iso request structure. ++ * ++ */ ++typedef struct usb_iso_request dwc_otg_pcd_iso_request_t; ++ ++#ifdef DWC_UTE_PER_IO ++ ++/** ++ * This shall be the exact analogy of the same type structure defined in the ++ * usb_gadget.h. Each descriptor contains ++ */ ++struct dwc_iso_pkt_desc_port { ++ uint32_t offset; ++ uint32_t length; /* expected length */ ++ uint32_t actual_length; ++ uint32_t status; ++}; ++ ++struct dwc_iso_xreq_port { ++ /** transfer/submission flag */ ++ uint32_t tr_sub_flags; ++ /** Start the request ASAP */ ++#define DWC_EREQ_TF_ASAP 0x00000002 ++ /** Just enqueue the request w/o initiating a transfer */ ++#define DWC_EREQ_TF_ENQUEUE 0x00000004 ++ ++ /** ++ * count of ISO packets attached to this request - shall ++ * not exceed the pio_alloc_pkt_count ++ */ ++ uint32_t pio_pkt_count; ++ /** count of ISO packets allocated for this request */ ++ uint32_t pio_alloc_pkt_count; ++ /** number of ISO packet errors */ ++ uint32_t error_count; ++ /** reserved for future extension */ ++ uint32_t res; ++ /** Will be allocated and freed in the UTE gadget and based on the CFC value */ ++ struct dwc_iso_pkt_desc_port *per_io_frame_descs; ++}; ++#endif ++/** DWC_otg request structure. ++ * This structure is a list of requests. ++ */ ++typedef struct dwc_otg_pcd_request { ++ void *priv; ++ void *buf; ++ dwc_dma_t dma; ++ uint32_t length; ++ uint32_t actual; ++ unsigned sent_zlp:1; ++ /** ++ * Used instead of original buffer if ++ * it(physical address) is not dword-aligned. ++ **/ ++ uint8_t *dw_align_buf; ++ dwc_dma_t dw_align_buf_dma; ++ ++ DWC_CIRCLEQ_ENTRY(dwc_otg_pcd_request) queue_entry; ++#ifdef DWC_UTE_PER_IO ++ struct dwc_iso_xreq_port ext_req; ++ //void *priv_ereq_nport; /* */ ++#endif ++} dwc_otg_pcd_request_t; ++ ++DWC_CIRCLEQ_HEAD(req_list, dwc_otg_pcd_request); ++ ++/** PCD EP structure. ++ * This structure describes an EP, there is an array of EPs in the PCD ++ * structure. ++ */ ++typedef struct dwc_otg_pcd_ep { ++ /** USB EP Descriptor */ ++ const usb_endpoint_descriptor_t *desc; ++ ++ /** queue of dwc_otg_pcd_requests. */ ++ struct req_list queue; ++ unsigned stopped:1; ++ unsigned disabling:1; ++ unsigned dma:1; ++ unsigned queue_sof:1; ++ ++#ifdef DWC_EN_ISOC ++ /** ISOC req handle passed */ ++ void *iso_req_handle; ++#endif //_EN_ISOC_ ++ ++ /** DWC_otg ep data. */ ++ dwc_ep_t dwc_ep; ++ ++ /** Pointer to PCD */ ++ struct dwc_otg_pcd *pcd; ++ ++ void *priv; ++} dwc_otg_pcd_ep_t; ++ ++/** DWC_otg PCD Structure. ++ * This structure encapsulates the data for the dwc_otg PCD. ++ */ ++struct dwc_otg_pcd { ++ const struct dwc_otg_pcd_function_ops *fops; ++ /** The DWC otg device pointer */ ++ struct dwc_otg_device *otg_dev; ++ /** Core Interface */ ++ dwc_otg_core_if_t *core_if; ++ /** State of EP0 */ ++ ep0state_e ep0state; ++ /** EP0 Request is pending */ ++ unsigned ep0_pending:1; ++ /** Indicates when SET CONFIGURATION Request is in process */ ++ unsigned request_config:1; ++ /** The state of the Remote Wakeup Enable. */ ++ unsigned remote_wakeup_enable:1; ++ /** The state of the B-Device HNP Enable. */ ++ unsigned b_hnp_enable:1; ++ /** The state of A-Device HNP Support. */ ++ unsigned a_hnp_support:1; ++ /** The state of the A-Device Alt HNP support. */ ++ unsigned a_alt_hnp_support:1; ++ /** Count of pending Requests */ ++ unsigned request_pending; ++ ++ /** SETUP packet for EP0 ++ * This structure is allocated as a DMA buffer on PCD initialization ++ * with enough space for up to 3 setup packets. ++ */ ++ union { ++ usb_device_request_t req; ++ uint32_t d32[2]; ++ } *setup_pkt; ++ ++ dwc_dma_t setup_pkt_dma_handle; ++ ++ /* Additional buffer and flag for CTRL_WR premature case */ ++ uint8_t *backup_buf; ++ unsigned data_terminated; ++ ++ /** 2-byte dma buffer used to return status from GET_STATUS */ ++ uint16_t *status_buf; ++ dwc_dma_t status_buf_dma_handle; ++ ++ /** EP0 */ ++ dwc_otg_pcd_ep_t ep0; ++ ++ /** Array of IN EPs. */ ++ dwc_otg_pcd_ep_t in_ep[MAX_EPS_CHANNELS - 1]; ++ /** Array of OUT EPs. */ ++ dwc_otg_pcd_ep_t out_ep[MAX_EPS_CHANNELS - 1]; ++ /** number of valid EPs in the above array. */ ++// unsigned num_eps : 4; ++ dwc_spinlock_t *lock; ++ ++ /** Tasklet to defer starting of TEST mode transmissions until ++ * Status Phase has been completed. ++ */ ++ dwc_tasklet_t *test_mode_tasklet; ++ ++ /** Tasklet to delay starting of xfer in DMA mode */ ++ dwc_tasklet_t *start_xfer_tasklet; ++ ++ /** The test mode to enter when the tasklet is executed. */ ++ unsigned test_mode; ++ /** The cfi_api structure that implements most of the CFI API ++ * and OTG specific core configuration functionality ++ */ ++#ifdef DWC_UTE_CFI ++ struct cfiobject *cfi; ++#endif ++ ++}; ++ ++//FIXME this functions should be static, and this prototypes should be removed ++extern void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep); ++extern void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep, ++ dwc_otg_pcd_request_t * req, int32_t status); ++ ++void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep, ++ void *req_handle); ++ ++extern void do_test_mode(void *data); ++#endif ++#endif /* DWC_HOST_ONLY */ +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h 2015-11-29 09:42:39.923098428 +0100 +@@ -0,0 +1,360 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_if.h $ ++ * $Revision: #11 $ ++ * $Date: 2011/10/26 $ ++ * $Change: 1873028 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_HOST_ONLY ++ ++#if !defined(__DWC_PCD_IF_H__) ++#define __DWC_PCD_IF_H__ ++ ++//#include "dwc_os.h" ++#include "dwc_otg_core_if.h" ++ ++/** @file ++ * This file defines DWC_OTG PCD Core API. ++ */ ++ ++struct dwc_otg_pcd; ++typedef struct dwc_otg_pcd dwc_otg_pcd_t; ++ ++/** Maxpacket size for EP0 */ ++#define MAX_EP0_SIZE 64 ++/** Maxpacket size for any EP */ ++#define MAX_PACKET_SIZE 1024 ++ ++/** @name Function Driver Callbacks */ ++/** @{ */ ++ ++/** This function will be called whenever a previously queued request has ++ * completed. The status value will be set to -DWC_E_SHUTDOWN to indicated a ++ * failed or aborted transfer, or -DWC_E_RESTART to indicate the device was reset, ++ * or -DWC_E_TIMEOUT to indicate it timed out, or -DWC_E_INVALID to indicate invalid ++ * parameters. */ ++typedef int (*dwc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *req_handle, int32_t status, ++ uint32_t actual); ++/** ++ * This function will be called whenever a previousle queued ISOC request has ++ * completed. Count of ISOC packets could be read using dwc_otg_pcd_get_iso_packet_count ++ * function. ++ * The status of each ISOC packet could be read using dwc_otg_pcd_get_iso_packet_* ++ * functions. ++ */ ++typedef int (*dwc_isoc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *req_handle, int proc_buf_num); ++/** This function should handle any SETUP request that cannot be handled by the ++ * PCD Core. This includes most GET_DESCRIPTORs, SET_CONFIGS, Any ++ * class-specific requests, etc. The function must non-blocking. ++ * ++ * Returns 0 on success. ++ * Returns -DWC_E_NOT_SUPPORTED if the request is not supported. ++ * Returns -DWC_E_INVALID if the setup request had invalid parameters or bytes. ++ * Returns -DWC_E_SHUTDOWN on any other error. */ ++typedef int (*dwc_setup_cb_t) (dwc_otg_pcd_t * pcd, uint8_t * bytes); ++/** This is called whenever the device has been disconnected. The function ++ * driver should take appropriate action to clean up all pending requests in the ++ * PCD Core, remove all endpoints (except ep0), and initialize back to reset ++ * state. */ ++typedef int (*dwc_disconnect_cb_t) (dwc_otg_pcd_t * pcd); ++/** This function is called when device has been connected. */ ++typedef int (*dwc_connect_cb_t) (dwc_otg_pcd_t * pcd, int speed); ++/** This function is called when device has been suspended */ ++typedef int (*dwc_suspend_cb_t) (dwc_otg_pcd_t * pcd); ++/** This function is called when device has received LPM tokens, i.e. ++ * device has been sent to sleep state. */ ++typedef int (*dwc_sleep_cb_t) (dwc_otg_pcd_t * pcd); ++/** This function is called when device has been resumed ++ * from suspend(L2) or L1 sleep state. */ ++typedef int (*dwc_resume_cb_t) (dwc_otg_pcd_t * pcd); ++/** This function is called whenever hnp params has been changed. ++ * User can call get_b_hnp_enable, get_a_hnp_support, get_a_alt_hnp_support functions ++ * to get hnp parameters. */ ++typedef int (*dwc_hnp_params_changed_cb_t) (dwc_otg_pcd_t * pcd); ++/** This function is called whenever USB RESET is detected. */ ++typedef int (*dwc_reset_cb_t) (dwc_otg_pcd_t * pcd); ++ ++typedef int (*cfi_setup_cb_t) (dwc_otg_pcd_t * pcd, void *ctrl_req_bytes); ++ ++/** ++ * ++ * @param ep_handle Void pointer to the usb_ep structure ++ * @param ereq_port Pointer to the extended request structure created in the ++ * portable part. ++ */ ++typedef int (*xiso_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *req_handle, int32_t status, ++ void *ereq_port); ++/** Function Driver Ops Data Structure */ ++struct dwc_otg_pcd_function_ops { ++ dwc_connect_cb_t connect; ++ dwc_disconnect_cb_t disconnect; ++ dwc_setup_cb_t setup; ++ dwc_completion_cb_t complete; ++ dwc_isoc_completion_cb_t isoc_complete; ++ dwc_suspend_cb_t suspend; ++ dwc_sleep_cb_t sleep; ++ dwc_resume_cb_t resume; ++ dwc_reset_cb_t reset; ++ dwc_hnp_params_changed_cb_t hnp_changed; ++ cfi_setup_cb_t cfi_setup; ++#ifdef DWC_UTE_PER_IO ++ xiso_completion_cb_t xisoc_complete; ++#endif ++}; ++/** @} */ ++ ++/** @name Function Driver Functions */ ++/** @{ */ ++ ++/** Call this function to get pointer on dwc_otg_pcd_t, ++ * this pointer will be used for all PCD API functions. ++ * ++ * @param core_if The DWC_OTG Core ++ */ ++extern dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if); ++ ++/** Frees PCD allocated by dwc_otg_pcd_init ++ * ++ * @param pcd The PCD ++ */ ++extern void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd); ++ ++/** Call this to bind the function driver to the PCD Core. ++ * ++ * @param pcd Pointer on dwc_otg_pcd_t returned by dwc_otg_pcd_init function. ++ * @param fops The Function Driver Ops data structure containing pointers to all callbacks. ++ */ ++extern void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd, ++ const struct dwc_otg_pcd_function_ops *fops); ++ ++/** Enables an endpoint for use. This function enables an endpoint in ++ * the PCD. The endpoint is described by the ep_desc which has the ++ * same format as a USB ep descriptor. The ep_handle parameter is used to refer ++ * to the endpoint from other API functions and in callbacks. Normally this ++ * should be called after a SET_CONFIGURATION/SET_INTERFACE to configure the ++ * core for that interface. ++ * ++ * Returns -DWC_E_INVALID if invalid parameters were passed. ++ * Returns -DWC_E_SHUTDOWN if any other error ocurred. ++ * Returns 0 on success. ++ * ++ * @param pcd The PCD ++ * @param ep_desc Endpoint descriptor ++ * @param usb_ep Handle on endpoint, that will be used to identify endpoint. ++ */ ++extern int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd, ++ const uint8_t * ep_desc, void *usb_ep); ++ ++/** Disable the endpoint referenced by ep_handle. ++ * ++ * Returns -DWC_E_INVALID if invalid parameters were passed. ++ * Returns -DWC_E_SHUTDOWN if any other error occurred. ++ * Returns 0 on success. */ ++extern int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle); ++ ++/** Queue a data transfer request on the endpoint referenced by ep_handle. ++ * After the transfer is completes, the complete callback will be called with ++ * the request status. ++ * ++ * @param pcd The PCD ++ * @param ep_handle The handle of the endpoint ++ * @param buf The buffer for the data ++ * @param dma_buf The DMA buffer for the data ++ * @param buflen The length of the data transfer ++ * @param zero Specifies whether to send zero length last packet. ++ * @param req_handle Set this handle to any value to use to reference this ++ * request in the ep_dequeue function or from the complete callback ++ * @param atomic_alloc If driver need to perform atomic allocations ++ * for internal data structures. ++ * ++ * Returns -DWC_E_INVALID if invalid parameters were passed. ++ * Returns -DWC_E_SHUTDOWN if any other error ocurred. ++ * Returns 0 on success. */ ++extern int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle, ++ uint8_t * buf, dwc_dma_t dma_buf, ++ uint32_t buflen, int zero, void *req_handle, ++ int atomic_alloc); ++#ifdef DWC_UTE_PER_IO ++/** ++ * ++ * @param ereq_nonport Pointer to the extended request part of the ++ * usb_request structure defined in usb_gadget.h file. ++ */ ++extern int dwc_otg_pcd_xiso_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle, ++ uint8_t * buf, dwc_dma_t dma_buf, ++ uint32_t buflen, int zero, ++ void *req_handle, int atomic_alloc, ++ void *ereq_nonport); ++ ++#endif ++ ++/** De-queue the specified data transfer that has not yet completed. ++ * ++ * Returns -DWC_E_INVALID if invalid parameters were passed. ++ * Returns -DWC_E_SHUTDOWN if any other error ocurred. ++ * Returns 0 on success. */ ++extern int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *req_handle); ++ ++/** Halt (STALL) an endpoint or clear it. ++ * ++ * Returns -DWC_E_INVALID if invalid parameters were passed. ++ * Returns -DWC_E_SHUTDOWN if any other error ocurred. ++ * Returns -DWC_E_AGAIN if the STALL cannot be sent and must be tried again later ++ * Returns 0 on success. */ ++extern int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value); ++ ++/** This function */ ++extern int dwc_otg_pcd_ep_wedge(dwc_otg_pcd_t * pcd, void *ep_handle); ++ ++/** This function should be called on every hardware interrupt */ ++extern int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd); ++ ++/** This function returns current frame number */ ++extern int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd); ++ ++/** ++ * Start isochronous transfers on the endpoint referenced by ep_handle. ++ * For isochronous transfers duble buffering is used. ++ * After processing each of buffers comlete callback will be called with ++ * status for each transaction. ++ * ++ * @param pcd The PCD ++ * @param ep_handle The handle of the endpoint ++ * @param buf0 The virtual address of first data buffer ++ * @param buf1 The virtual address of second data buffer ++ * @param dma0 The DMA address of first data buffer ++ * @param dma1 The DMA address of second data buffer ++ * @param sync_frame Data pattern frame number ++ * @param dp_frame Data size for pattern frame ++ * @param data_per_frame Data size for regular frame ++ * @param start_frame Frame number to start transfers, if -1 then start transfers ASAP. ++ * @param buf_proc_intrvl Interval of ISOC Buffer processing ++ * @param req_handle Handle of ISOC request ++ * @param atomic_alloc Specefies whether to perform atomic allocation for ++ * internal data structures. ++ * ++ * Returns -DWC_E_NO_MEMORY if there is no enough memory. ++ * Returns -DWC_E_INVALID if incorrect arguments are passed to the function. ++ * Returns -DW_E_SHUTDOWN for any other error. ++ * Returns 0 on success ++ */ ++extern int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle, ++ uint8_t * buf0, uint8_t * buf1, ++ dwc_dma_t dma0, dwc_dma_t dma1, ++ int sync_frame, int dp_frame, ++ int data_per_frame, int start_frame, ++ int buf_proc_intrvl, void *req_handle, ++ int atomic_alloc); ++ ++/** Stop ISOC transfers on endpoint referenced by ep_handle. ++ * ++ * @param pcd The PCD ++ * @param ep_handle The handle of the endpoint ++ * @param req_handle Handle of ISOC request ++ * ++ * Returns -DWC_E_INVALID if incorrect arguments are passed to the function ++ * Returns 0 on success ++ */ ++int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *req_handle); ++ ++/** Get ISOC packet status. ++ * ++ * @param pcd The PCD ++ * @param ep_handle The handle of the endpoint ++ * @param iso_req_handle Isochronoush request handle ++ * @param packet Number of packet ++ * @param status Out parameter for returning status ++ * @param actual Out parameter for returning actual length ++ * @param offset Out parameter for returning offset ++ * ++ */ ++extern void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd, ++ void *ep_handle, ++ void *iso_req_handle, int packet, ++ int *status, int *actual, ++ int *offset); ++ ++/** Get ISOC packet count. ++ * ++ * @param pcd The PCD ++ * @param ep_handle The handle of the endpoint ++ * @param iso_req_handle ++ */ ++extern int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd, ++ void *ep_handle, ++ void *iso_req_handle); ++ ++/** This function starts the SRP Protocol if no session is in progress. If ++ * a session is already in progress, but the device is suspended, ++ * remote wakeup signaling is started. ++ */ ++extern int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd); ++ ++/** This function returns 1 if LPM support is enabled, and 0 otherwise. */ ++extern int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd); ++ ++/** This function returns 1 if remote wakeup is allowed and 0, otherwise. */ ++extern int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd); ++ ++/** Initiate SRP */ ++extern void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd); ++ ++/** Starts remote wakeup signaling. */ ++extern void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set); ++ ++/** Starts micorsecond soft disconnect. */ ++extern void dwc_otg_pcd_disconnect_us(dwc_otg_pcd_t * pcd, int no_of_usecs); ++/** This function returns whether device is dualspeed.*/ ++extern uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd); ++ ++/** This function returns whether device is otg. */ ++extern uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd); ++ ++/** These functions allow to get hnp parameters */ ++extern uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd); ++extern uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd); ++extern uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd); ++ ++/** CFI specific Interface functions */ ++/** Allocate a cfi buffer */ ++extern uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, ++ dwc_dma_t * addr, size_t buflen, ++ int flags); ++ ++/******************************************************************************/ ++ ++/** @} */ ++ ++#endif /* __DWC_PCD_IF_H__ */ ++ ++#endif /* DWC_HOST_ONLY */ +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c 2015-11-29 09:42:39.923098428 +0100 +@@ -0,0 +1,5147 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_intr.c $ ++ * $Revision: #116 $ ++ * $Date: 2012/08/10 $ ++ * $Change: 2047372 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_HOST_ONLY ++ ++#include "dwc_otg_pcd.h" ++ ++#ifdef DWC_UTE_CFI ++#include "dwc_otg_cfi.h" ++#endif ++ ++#ifdef DWC_UTE_PER_IO ++extern void complete_xiso_ep(dwc_otg_pcd_ep_t * ep); ++#endif ++//#define PRINT_CFI_DMA_DESCS ++ ++#define DEBUG_EP0 ++ ++/** ++ * This function updates OTG. ++ */ ++static void dwc_otg_pcd_update_otg(dwc_otg_pcd_t * pcd, const unsigned reset) ++{ ++ ++ if (reset) { ++ pcd->b_hnp_enable = 0; ++ pcd->a_hnp_support = 0; ++ pcd->a_alt_hnp_support = 0; ++ } ++ ++ if (pcd->fops->hnp_changed) { ++ pcd->fops->hnp_changed(pcd); ++ } ++} ++ ++/** @file ++ * This file contains the implementation of the PCD Interrupt handlers. ++ * ++ * The PCD handles the device interrupts. Many conditions can cause a ++ * device interrupt. When an interrupt occurs, the device interrupt ++ * service routine determines the cause of the interrupt and ++ * dispatches handling to the appropriate function. These interrupt ++ * handling functions are described below. ++ * All interrupt registers are processed from LSB to MSB. ++ */ ++ ++/** ++ * This function prints the ep0 state for debug purposes. ++ */ ++static inline void print_ep0_state(dwc_otg_pcd_t * pcd) ++{ ++#ifdef DEBUG ++ char str[40]; ++ ++ switch (pcd->ep0state) { ++ case EP0_DISCONNECT: ++ dwc_strcpy(str, "EP0_DISCONNECT"); ++ break; ++ case EP0_IDLE: ++ dwc_strcpy(str, "EP0_IDLE"); ++ break; ++ case EP0_IN_DATA_PHASE: ++ dwc_strcpy(str, "EP0_IN_DATA_PHASE"); ++ break; ++ case EP0_OUT_DATA_PHASE: ++ dwc_strcpy(str, "EP0_OUT_DATA_PHASE"); ++ break; ++ case EP0_IN_STATUS_PHASE: ++ dwc_strcpy(str, "EP0_IN_STATUS_PHASE"); ++ break; ++ case EP0_OUT_STATUS_PHASE: ++ dwc_strcpy(str, "EP0_OUT_STATUS_PHASE"); ++ break; ++ case EP0_STALL: ++ dwc_strcpy(str, "EP0_STALL"); ++ break; ++ default: ++ dwc_strcpy(str, "EP0_INVALID"); ++ } ++ ++ DWC_DEBUGPL(DBG_ANY, "%s(%d)\n", str, pcd->ep0state); ++#endif ++} ++ ++/** ++ * This function calculate the size of the payload in the memory ++ * for out endpoints and prints size for debug purposes(used in ++ * 2.93a DevOutNak feature). ++ */ ++static inline void print_memory_payload(dwc_otg_pcd_t * pcd, dwc_ep_t * ep) ++{ ++#ifdef DEBUG ++ deptsiz_data_t deptsiz_init = {.d32 = 0 }; ++ deptsiz_data_t deptsiz_updt = {.d32 = 0 }; ++ int pack_num; ++ unsigned payload; ++ ++ deptsiz_init.d32 = pcd->core_if->start_doeptsiz_val[ep->num]; ++ deptsiz_updt.d32 = ++ DWC_READ_REG32(&pcd->core_if->dev_if-> ++ out_ep_regs[ep->num]->doeptsiz); ++ /* Payload will be */ ++ payload = deptsiz_init.b.xfersize - deptsiz_updt.b.xfersize; ++ /* Packet count is decremented every time a packet ++ * is written to the RxFIFO not in to the external memory ++ * So, if payload == 0, then it means no packet was sent to ext memory*/ ++ pack_num = (!payload) ? 0 : (deptsiz_init.b.pktcnt - deptsiz_updt.b.pktcnt); ++ DWC_DEBUGPL(DBG_PCDV, ++ "Payload for EP%d-%s\n", ++ ep->num, (ep->is_in ? "IN" : "OUT")); ++ DWC_DEBUGPL(DBG_PCDV, ++ "Number of transfered bytes = 0x%08x\n", payload); ++ DWC_DEBUGPL(DBG_PCDV, ++ "Number of transfered packets = %d\n", pack_num); ++#endif ++} ++ ++ ++#ifdef DWC_UTE_CFI ++static inline void print_desc(struct dwc_otg_dma_desc *ddesc, ++ const uint8_t * epname, int descnum) ++{ ++ CFI_INFO ++ ("%s DMA_DESC(%d) buf=0x%08x bytes=0x%04x; sp=0x%x; l=0x%x; sts=0x%02x; bs=0x%02x\n", ++ epname, descnum, ddesc->buf, ddesc->status.b.bytes, ++ ddesc->status.b.sp, ddesc->status.b.l, ddesc->status.b.sts, ++ ddesc->status.b.bs); ++} ++#endif ++ ++/** ++ * This function returns pointer to in ep struct with number ep_num ++ */ ++static inline dwc_otg_pcd_ep_t *get_in_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num) ++{ ++ int i; ++ int num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps; ++ if (ep_num == 0) { ++ return &pcd->ep0; ++ } else { ++ for (i = 0; i < num_in_eps; ++i) { ++ if (pcd->in_ep[i].dwc_ep.num == ep_num) ++ return &pcd->in_ep[i]; ++ } ++ return 0; ++ } ++} ++ ++/** ++ * This function returns pointer to out ep struct with number ep_num ++ */ ++static inline dwc_otg_pcd_ep_t *get_out_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num) ++{ ++ int i; ++ int num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps; ++ if (ep_num == 0) { ++ return &pcd->ep0; ++ } else { ++ for (i = 0; i < num_out_eps; ++i) { ++ if (pcd->out_ep[i].dwc_ep.num == ep_num) ++ return &pcd->out_ep[i]; ++ } ++ return 0; ++ } ++} ++ ++/** ++ * This functions gets a pointer to an EP from the wIndex address ++ * value of the control request. ++ */ ++dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex) ++{ ++ dwc_otg_pcd_ep_t *ep; ++ uint32_t ep_num = UE_GET_ADDR(wIndex); ++ ++ if (ep_num == 0) { ++ ep = &pcd->ep0; ++ } else if (UE_GET_DIR(wIndex) == UE_DIR_IN) { /* in ep */ ++ ep = &pcd->in_ep[ep_num - 1]; ++ } else { ++ ep = &pcd->out_ep[ep_num - 1]; ++ } ++ ++ return ep; ++} ++ ++/** ++ * This function checks the EP request queue, if the queue is not ++ * empty the next request is started. ++ */ ++void start_next_request(dwc_otg_pcd_ep_t * ep) ++{ ++ dwc_otg_pcd_request_t *req = 0; ++ uint32_t max_transfer = ++ GET_CORE_IF(ep->pcd)->core_params->max_transfer_size; ++ ++#ifdef DWC_UTE_CFI ++ struct dwc_otg_pcd *pcd; ++ pcd = ep->pcd; ++#endif ++ ++ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ req = DWC_CIRCLEQ_FIRST(&ep->queue); ++ ++#ifdef DWC_UTE_CFI ++ if (ep->dwc_ep.buff_mode != BM_STANDARD) { ++ ep->dwc_ep.cfi_req_len = req->length; ++ pcd->cfi->ops.build_descriptors(pcd->cfi, pcd, ep, req); ++ } else { ++#endif ++ /* Setup and start the Transfer */ ++ if (req->dw_align_buf) { ++ ep->dwc_ep.dma_addr = req->dw_align_buf_dma; ++ ep->dwc_ep.start_xfer_buff = req->dw_align_buf; ++ ep->dwc_ep.xfer_buff = req->dw_align_buf; ++ } else { ++ ep->dwc_ep.dma_addr = req->dma; ++ ep->dwc_ep.start_xfer_buff = req->buf; ++ ep->dwc_ep.xfer_buff = req->buf; ++ } ++ ep->dwc_ep.sent_zlp = 0; ++ ep->dwc_ep.total_len = req->length; ++ ep->dwc_ep.xfer_len = 0; ++ ep->dwc_ep.xfer_count = 0; ++ ++ ep->dwc_ep.maxxfer = max_transfer; ++ if (GET_CORE_IF(ep->pcd)->dma_desc_enable) { ++ uint32_t out_max_xfer = DDMA_MAX_TRANSFER_SIZE ++ - (DDMA_MAX_TRANSFER_SIZE % 4); ++ if (ep->dwc_ep.is_in) { ++ if (ep->dwc_ep.maxxfer > ++ DDMA_MAX_TRANSFER_SIZE) { ++ ep->dwc_ep.maxxfer = ++ DDMA_MAX_TRANSFER_SIZE; ++ } ++ } else { ++ if (ep->dwc_ep.maxxfer > out_max_xfer) { ++ ep->dwc_ep.maxxfer = ++ out_max_xfer; ++ } ++ } ++ } ++ if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) { ++ ep->dwc_ep.maxxfer -= ++ (ep->dwc_ep.maxxfer % ep->dwc_ep.maxpacket); ++ } ++ if (req->sent_zlp) { ++ if ((ep->dwc_ep.total_len % ++ ep->dwc_ep.maxpacket == 0) ++ && (ep->dwc_ep.total_len != 0)) { ++ ep->dwc_ep.sent_zlp = 1; ++ } ++ ++ } ++#ifdef DWC_UTE_CFI ++ } ++#endif ++ dwc_otg_ep_start_transfer(GET_CORE_IF(ep->pcd), &ep->dwc_ep); ++ } else if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) { ++ DWC_PRINTF("There are no more ISOC requests \n"); ++ ep->dwc_ep.frame_num = 0xFFFFFFFF; ++ } ++} ++ ++/** ++ * This function handles the SOF Interrupts. At this time the SOF ++ * Interrupt is disabled. ++ */ ++int32_t dwc_otg_pcd_handle_sof_intr(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ ++ gintsts_data_t gintsts; ++ ++ DWC_DEBUGPL(DBG_PCD, "SOF\n"); ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.sofintr = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * This function handles the Rx Status Queue Level Interrupt, which ++ * indicates that there is a least one packet in the Rx FIFO. The ++ * packets are moved from the FIFO to memory, where they will be ++ * processed when the Endpoint Interrupt Register indicates Transfer ++ * Complete or SETUP Phase Done. ++ * ++ * Repeat the following until the Rx Status Queue is empty: ++ * -# Read the Receive Status Pop Register (GRXSTSP) to get Packet ++ * info ++ * -# If Receive FIFO is empty then skip to step Clear the interrupt ++ * and exit ++ * -# If SETUP Packet call dwc_otg_read_setup_packet to copy the ++ * SETUP data to the buffer ++ * -# If OUT Data Packet call dwc_otg_read_packet to copy the data ++ * to the destination buffer ++ */ ++int32_t dwc_otg_pcd_handle_rx_status_q_level_intr(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ gintmsk_data_t gintmask = {.d32 = 0 }; ++ device_grxsts_data_t status; ++ dwc_otg_pcd_ep_t *ep; ++ gintsts_data_t gintsts; ++#ifdef DEBUG ++ static char *dpid_str[] = { "D0", "D2", "D1", "MDATA" }; ++#endif ++ ++ //DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _pcd); ++ /* Disable the Rx Status Queue Level interrupt */ ++ gintmask.b.rxstsqlvl = 1; ++ DWC_MODIFY_REG32(&global_regs->gintmsk, gintmask.d32, 0); ++ ++ /* Get the Status from the top of the FIFO */ ++ status.d32 = DWC_READ_REG32(&global_regs->grxstsp); ++ ++ DWC_DEBUGPL(DBG_PCD, "EP:%d BCnt:%d DPID:%s " ++ "pktsts:%x Frame:%d(0x%0x)\n", ++ status.b.epnum, status.b.bcnt, ++ dpid_str[status.b.dpid], ++ status.b.pktsts, status.b.fn, status.b.fn); ++ /* Get pointer to EP structure */ ++ ep = get_out_ep(pcd, status.b.epnum); ++ ++ switch (status.b.pktsts) { ++ case DWC_DSTS_GOUT_NAK: ++ DWC_DEBUGPL(DBG_PCDV, "Global OUT NAK\n"); ++ break; ++ case DWC_STS_DATA_UPDT: ++ DWC_DEBUGPL(DBG_PCDV, "OUT Data Packet\n"); ++ if (status.b.bcnt && ep->dwc_ep.xfer_buff) { ++ /** @todo NGS Check for buffer overflow? */ ++ dwc_otg_read_packet(core_if, ++ ep->dwc_ep.xfer_buff, ++ status.b.bcnt); ++ ep->dwc_ep.xfer_count += status.b.bcnt; ++ ep->dwc_ep.xfer_buff += status.b.bcnt; ++ } ++ break; ++ case DWC_STS_XFER_COMP: ++ DWC_DEBUGPL(DBG_PCDV, "OUT Complete\n"); ++ break; ++ case DWC_DSTS_SETUP_COMP: ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCDV, "Setup Complete\n"); ++#endif ++ break; ++ case DWC_DSTS_SETUP_UPDT: ++ dwc_otg_read_setup_packet(core_if, pcd->setup_pkt->d32); ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCD, ++ "SETUP PKT: %02x.%02x v%04x i%04x l%04x\n", ++ pcd->setup_pkt->req.bmRequestType, ++ pcd->setup_pkt->req.bRequest, ++ UGETW(pcd->setup_pkt->req.wValue), ++ UGETW(pcd->setup_pkt->req.wIndex), ++ UGETW(pcd->setup_pkt->req.wLength)); ++#endif ++ ep->dwc_ep.xfer_count += status.b.bcnt; ++ break; ++ default: ++ DWC_DEBUGPL(DBG_PCDV, "Invalid Packet Status (0x%0x)\n", ++ status.b.pktsts); ++ break; ++ } ++ ++ /* Enable the Rx Status Queue Level interrupt */ ++ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmask.d32); ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.rxstsqlvl = 1; ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); ++ ++ //DWC_DEBUGPL(DBG_PCDV, "EXIT: %s\n", __func__); ++ return 1; ++} ++ ++/** ++ * This function examines the Device IN Token Learning Queue to ++ * determine the EP number of the last IN token received. This ++ * implementation is for the Mass Storage device where there are only ++ * 2 IN EPs (Control-IN and BULK-IN). ++ * ++ * The EP numbers for the first six IN Tokens are in DTKNQR1 and there ++ * are 8 EP Numbers in each of the other possible DTKNQ Registers. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * ++ */ ++static inline int get_ep_of_last_in_token(dwc_otg_core_if_t * core_if) ++{ ++ dwc_otg_device_global_regs_t *dev_global_regs = ++ core_if->dev_if->dev_global_regs; ++ const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth; ++ /* Number of Token Queue Registers */ ++ const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8; ++ dtknq1_data_t dtknqr1; ++ uint32_t in_tkn_epnums[4]; ++ int ndx = 0; ++ int i = 0; ++ volatile uint32_t *addr = &dev_global_regs->dtknqr1; ++ int epnum = 0; ++ ++ //DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH); ++ ++ /* Read the DTKNQ Registers */ ++ for (i = 0; i < DTKNQ_REG_CNT; i++) { ++ in_tkn_epnums[i] = DWC_READ_REG32(addr); ++ DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i + 1, ++ in_tkn_epnums[i]); ++ if (addr == &dev_global_regs->dvbusdis) { ++ addr = &dev_global_regs->dtknqr3_dthrctl; ++ } else { ++ ++addr; ++ } ++ ++ } ++ ++ /* Copy the DTKNQR1 data to the bit field. */ ++ dtknqr1.d32 = in_tkn_epnums[0]; ++ /* Get the EP numbers */ ++ in_tkn_epnums[0] = dtknqr1.b.epnums0_5; ++ ndx = dtknqr1.b.intknwptr - 1; ++ ++ //DWC_DEBUGPL(DBG_PCDV,"ndx=%d\n",ndx); ++ if (ndx == -1) { ++ /** @todo Find a simpler way to calculate the max ++ * queue position.*/ ++ int cnt = TOKEN_Q_DEPTH; ++ if (TOKEN_Q_DEPTH <= 6) { ++ cnt = TOKEN_Q_DEPTH - 1; ++ } else if (TOKEN_Q_DEPTH <= 14) { ++ cnt = TOKEN_Q_DEPTH - 7; ++ } else if (TOKEN_Q_DEPTH <= 22) { ++ cnt = TOKEN_Q_DEPTH - 15; ++ } else { ++ cnt = TOKEN_Q_DEPTH - 23; ++ } ++ epnum = (in_tkn_epnums[DTKNQ_REG_CNT - 1] >> (cnt * 4)) & 0xF; ++ } else { ++ if (ndx <= 5) { ++ epnum = (in_tkn_epnums[0] >> (ndx * 4)) & 0xF; ++ } else if (ndx <= 13) { ++ ndx -= 6; ++ epnum = (in_tkn_epnums[1] >> (ndx * 4)) & 0xF; ++ } else if (ndx <= 21) { ++ ndx -= 14; ++ epnum = (in_tkn_epnums[2] >> (ndx * 4)) & 0xF; ++ } else if (ndx <= 29) { ++ ndx -= 22; ++ epnum = (in_tkn_epnums[3] >> (ndx * 4)) & 0xF; ++ } ++ } ++ //DWC_DEBUGPL(DBG_PCD,"epnum=%d\n",epnum); ++ return epnum; ++} ++ ++/** ++ * This interrupt occurs when the non-periodic Tx FIFO is half-empty. ++ * The active request is checked for the next packet to be loaded into ++ * the non-periodic Tx FIFO. ++ */ ++int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ dwc_otg_dev_in_ep_regs_t *ep_regs; ++ gnptxsts_data_t txstatus = {.d32 = 0 }; ++ gintsts_data_t gintsts; ++ ++ int epnum = 0; ++ dwc_otg_pcd_ep_t *ep = 0; ++ uint32_t len = 0; ++ int dwords; ++ ++ /* Get the epnum from the IN Token Learning Queue. */ ++ epnum = get_ep_of_last_in_token(core_if); ++ ep = get_in_ep(pcd, epnum); ++ ++ DWC_DEBUGPL(DBG_PCD, "NP TxFifo Empty: %d \n", epnum); ++ ++ ep_regs = core_if->dev_if->in_ep_regs[epnum]; ++ ++ len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count; ++ if (len > ep->dwc_ep.maxpacket) { ++ len = ep->dwc_ep.maxpacket; ++ } ++ dwords = (len + 3) / 4; ++ ++ /* While there is space in the queue and space in the FIFO and ++ * More data to tranfer, Write packets to the Tx FIFO */ ++ txstatus.d32 = DWC_READ_REG32(&global_regs->gnptxsts); ++ DWC_DEBUGPL(DBG_PCDV, "b4 GNPTXSTS=0x%08x\n", txstatus.d32); ++ ++ while (txstatus.b.nptxqspcavail > 0 && ++ txstatus.b.nptxfspcavail > dwords && ++ ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len) { ++ /* Write the FIFO */ ++ dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0); ++ len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count; ++ ++ if (len > ep->dwc_ep.maxpacket) { ++ len = ep->dwc_ep.maxpacket; ++ } ++ ++ dwords = (len + 3) / 4; ++ txstatus.d32 = DWC_READ_REG32(&global_regs->gnptxsts); ++ DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n", txstatus.d32); ++ } ++ ++ DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n", ++ DWC_READ_REG32(&global_regs->gnptxsts)); ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.nptxfempty = 1; ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * This function is called when dedicated Tx FIFO Empty interrupt occurs. ++ * The active request is checked for the next packet to be loaded into ++ * apropriate Tx FIFO. ++ */ ++static int32_t write_empty_tx_fifo(dwc_otg_pcd_t * pcd, uint32_t epnum) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ dwc_otg_dev_in_ep_regs_t *ep_regs; ++ dtxfsts_data_t txstatus = {.d32 = 0 }; ++ dwc_otg_pcd_ep_t *ep = 0; ++ uint32_t len = 0; ++ int dwords; ++ ++ ep = get_in_ep(pcd, epnum); ++ ++ DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum); ++ ++ ep_regs = core_if->dev_if->in_ep_regs[epnum]; ++ ++ len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count; ++ ++ if (len > ep->dwc_ep.maxpacket) { ++ len = ep->dwc_ep.maxpacket; ++ } ++ ++ dwords = (len + 3) / 4; ++ ++ /* While there is space in the queue and space in the FIFO and ++ * More data to tranfer, Write packets to the Tx FIFO */ ++ txstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts); ++ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32); ++ ++ while (txstatus.b.txfspcavail > dwords && ++ ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len && ++ ep->dwc_ep.xfer_len != 0) { ++ /* Write the FIFO */ ++ dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0); ++ ++ len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count; ++ if (len > ep->dwc_ep.maxpacket) { ++ len = ep->dwc_ep.maxpacket; ++ } ++ ++ dwords = (len + 3) / 4; ++ txstatus.d32 = ++ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts); ++ DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum, ++ txstatus.d32); ++ } ++ ++ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, ++ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts)); ++ ++ return 1; ++} ++ ++/** ++ * This function is called when the Device is disconnected. It stops ++ * any active requests and informs the Gadget driver of the ++ * disconnect. ++ */ ++void dwc_otg_pcd_stop(dwc_otg_pcd_t * pcd) ++{ ++ int i, num_in_eps, num_out_eps; ++ dwc_otg_pcd_ep_t *ep; ++ ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ DWC_SPINLOCK(pcd->lock); ++ ++ num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps; ++ num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s() \n", __func__); ++ /* don't disconnect drivers more than once */ ++ if (pcd->ep0state == EP0_DISCONNECT) { ++ DWC_DEBUGPL(DBG_ANY, "%s() Already Disconnected\n", __func__); ++ DWC_SPINUNLOCK(pcd->lock); ++ return; ++ } ++ pcd->ep0state = EP0_DISCONNECT; ++ ++ /* Reset the OTG state. */ ++ dwc_otg_pcd_update_otg(pcd, 1); ++ ++ /* Disable the NP Tx Fifo Empty Interrupt. */ ++ intr_mask.b.nptxfempty = 1; ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, ++ intr_mask.d32, 0); ++ ++ /* Flush the FIFOs */ ++ /**@todo NGS Flush Periodic FIFOs */ ++ dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), 0x10); ++ dwc_otg_flush_rx_fifo(GET_CORE_IF(pcd)); ++ ++ /* prevent new request submissions, kill any outstanding requests */ ++ ep = &pcd->ep0; ++ dwc_otg_request_nuke(ep); ++ /* prevent new request submissions, kill any outstanding requests */ ++ for (i = 0; i < num_in_eps; i++) { ++ dwc_otg_pcd_ep_t *ep = &pcd->in_ep[i]; ++ dwc_otg_request_nuke(ep); ++ } ++ /* prevent new request submissions, kill any outstanding requests */ ++ for (i = 0; i < num_out_eps; i++) { ++ dwc_otg_pcd_ep_t *ep = &pcd->out_ep[i]; ++ dwc_otg_request_nuke(ep); ++ } ++ ++ /* report disconnect; the driver is already quiesced */ ++ if (pcd->fops->disconnect) { ++ DWC_SPINUNLOCK(pcd->lock); ++ pcd->fops->disconnect(pcd); ++ DWC_SPINLOCK(pcd->lock); ++ } ++ DWC_SPINUNLOCK(pcd->lock); ++} ++ ++/** ++ * This interrupt indicates that ... ++ */ ++int32_t dwc_otg_pcd_handle_i2c_intr(dwc_otg_pcd_t * pcd) ++{ ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ gintsts_data_t gintsts; ++ ++ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "i2cintr"); ++ intr_mask.b.i2cintr = 1; ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, ++ intr_mask.d32, 0); ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.i2cintr = 1; ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ gintsts.d32); ++ return 1; ++} ++ ++/** ++ * This interrupt indicates that ... ++ */ ++int32_t dwc_otg_pcd_handle_early_suspend_intr(dwc_otg_pcd_t * pcd) ++{ ++ gintsts_data_t gintsts; ++#if defined(VERBOSE) ++ DWC_PRINTF("Early Suspend Detected\n"); ++#endif ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.erlysuspend = 1; ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ gintsts.d32); ++ return 1; ++} ++ ++/** ++ * This function configures EPO to receive SETUP packets. ++ * ++ * @todo NGS: Update the comments from the HW FS. ++ * ++ * -# Program the following fields in the endpoint specific registers ++ * for Control OUT EP 0, in order to receive a setup packet ++ * - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back ++ * setup packets) ++ * - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back ++ * to back setup packets) ++ * - In DMA mode, DOEPDMA0 Register with a memory address to ++ * store any setup packets received ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param pcd Programming view of the PCD. ++ */ ++static inline void ep0_out_start(dwc_otg_core_if_t * core_if, ++ dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ deptsiz0_data_t doeptsize0 = {.d32 = 0 }; ++ dwc_otg_dev_dma_desc_t *dma_desc; ++ depctl_data_t doepctl = {.d32 = 0 }; ++ ++#ifdef VERBOSE ++ DWC_DEBUGPL(DBG_PCDV, "%s() doepctl0=%0x\n", __func__, ++ DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl)); ++#endif ++ if (core_if->snpsid >= OTG_CORE_REV_3_00a) { ++ doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl); ++ if (doepctl.b.epena) { ++ return; ++ } ++ } ++ ++ doeptsize0.b.supcnt = 3; ++ doeptsize0.b.pktcnt = 1; ++ doeptsize0.b.xfersize = 8 * 3; ++ ++ if (core_if->dma_enable) { ++ if (!core_if->dma_desc_enable) { ++ /** put here as for Hermes mode deptisz register should not be written */ ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doeptsiz, ++ doeptsize0.d32); ++ ++ /** @todo dma needs to handle multiple setup packets (up to 3) */ ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepdma, ++ pcd->setup_pkt_dma_handle); ++ } else { ++ dev_if->setup_desc_index = ++ (dev_if->setup_desc_index + 1) & 1; ++ dma_desc = ++ dev_if->setup_desc_addr[dev_if->setup_desc_index]; ++ ++ /** DMA Descriptor Setup */ ++ dma_desc->status.b.bs = BS_HOST_BUSY; ++ if (core_if->snpsid >= OTG_CORE_REV_3_00a) { ++ dma_desc->status.b.sr = 0; ++ dma_desc->status.b.mtrf = 0; ++ } ++ dma_desc->status.b.l = 1; ++ dma_desc->status.b.ioc = 1; ++ dma_desc->status.b.bytes = pcd->ep0.dwc_ep.maxpacket; ++ dma_desc->buf = pcd->setup_pkt_dma_handle; ++ dma_desc->status.b.sts = 0; ++ dma_desc->status.b.bs = BS_HOST_READY; ++ ++ /** DOEPDMA0 Register write */ ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepdma, ++ dev_if->dma_setup_desc_addr ++ [dev_if->setup_desc_index]); ++ } ++ ++ } else { ++ /** put here as for Hermes mode deptisz register should not be written */ ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doeptsiz, ++ doeptsize0.d32); ++ } ++ ++ /** DOEPCTL0 Register write cnak will be set after setup interrupt */ ++ doepctl.d32 = 0; ++ doepctl.b.epena = 1; ++ if (core_if->snpsid <= OTG_CORE_REV_2_94a) { ++ doepctl.b.cnak = 1; ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32); ++ } else { ++ DWC_MODIFY_REG32(&dev_if->out_ep_regs[0]->doepctl, 0, doepctl.d32); ++ } ++ ++#ifdef VERBOSE ++ DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n", ++ DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl)); ++ DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n", ++ DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl)); ++#endif ++} ++ ++/** ++ * This interrupt occurs when a USB Reset is detected. When the USB ++ * Reset Interrupt occurs the device state is set to DEFAULT and the ++ * EP0 state is set to IDLE. ++ * -# Set the NAK bit for all OUT endpoints (DOEPCTLn.SNAK = 1) ++ * -# Unmask the following interrupt bits ++ * - DAINTMSK.INEP0 = 1 (Control 0 IN endpoint) ++ * - DAINTMSK.OUTEP0 = 1 (Control 0 OUT endpoint) ++ * - DOEPMSK.SETUP = 1 ++ * - DOEPMSK.XferCompl = 1 ++ * - DIEPMSK.XferCompl = 1 ++ * - DIEPMSK.TimeOut = 1 ++ * -# Program the following fields in the endpoint specific registers ++ * for Control OUT EP 0, in order to receive a setup packet ++ * - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back ++ * setup packets) ++ * - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back ++ * to back setup packets) ++ * - In DMA mode, DOEPDMA0 Register with a memory address to ++ * store any setup packets received ++ * At this point, all the required initialization, except for enabling ++ * the control 0 OUT endpoint is done, for receiving SETUP packets. ++ */ ++int32_t dwc_otg_pcd_handle_usb_reset_intr(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ depctl_data_t doepctl = {.d32 = 0 }; ++ depctl_data_t diepctl = {.d32 = 0 }; ++ daint_data_t daintmsk = {.d32 = 0 }; ++ doepmsk_data_t doepmsk = {.d32 = 0 }; ++ diepmsk_data_t diepmsk = {.d32 = 0 }; ++ dcfg_data_t dcfg = {.d32 = 0 }; ++ grstctl_t resetctl = {.d32 = 0 }; ++ dctl_data_t dctl = {.d32 = 0 }; ++ int i = 0; ++ gintsts_data_t gintsts; ++ pcgcctl_data_t power = {.d32 = 0 }; ++ ++ power.d32 = DWC_READ_REG32(core_if->pcgcctl); ++ if (power.b.stoppclk) { ++ power.d32 = 0; ++ power.b.stoppclk = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0); ++ ++ power.b.pwrclmp = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0); ++ ++ power.b.rstpdwnmodule = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0); ++ } ++ ++ core_if->lx_state = DWC_OTG_L0; ++ ++ DWC_PRINTF("USB RESET\n"); ++#ifdef DWC_EN_ISOC ++ for (i = 1; i < 16; ++i) { ++ dwc_otg_pcd_ep_t *ep; ++ dwc_ep_t *dwc_ep; ++ ep = get_in_ep(pcd, i); ++ if (ep != 0) { ++ dwc_ep = &ep->dwc_ep; ++ dwc_ep->next_frame = 0xffffffff; ++ } ++ } ++#endif /* DWC_EN_ISOC */ ++ ++ /* reset the HNP settings */ ++ dwc_otg_pcd_update_otg(pcd, 1); ++ ++ /* Clear the Remote Wakeup Signalling */ ++ dctl.b.rmtwkupsig = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0); ++ ++ /* Set NAK for all OUT EPs */ ++ doepctl.b.snak = 1; ++ for (i = 0; i <= dev_if->num_out_eps; i++) { ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32); ++ } ++ ++ /* Flush the NP Tx FIFO */ ++ dwc_otg_flush_tx_fifo(core_if, 0x10); ++ /* Flush the Learning Queue */ ++ resetctl.b.intknqflsh = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32); ++ ++ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) { ++ core_if->start_predict = 0; ++ for (i = 0; i<= core_if->dev_if->num_in_eps; ++i) { ++ core_if->nextep_seq[i] = 0xff; // 0xff - EP not active ++ } ++ core_if->nextep_seq[0] = 0; ++ core_if->first_in_nextep_seq = 0; ++ diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl); ++ diepctl.b.nextep = 0; ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32); ++ ++ /* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */ ++ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg); ++ dcfg.b.epmscnt = 2; ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32); ++ ++ DWC_DEBUGPL(DBG_PCDV, ++ "%s first_in_nextep_seq= %2d; nextep_seq[]:\n", ++ __func__, core_if->first_in_nextep_seq); ++ for (i=0; i <= core_if->dev_if->num_in_eps; i++) { ++ DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]); ++ } ++ } ++ ++ if (core_if->multiproc_int_enable) { ++ daintmsk.b.inep0 = 1; ++ daintmsk.b.outep0 = 1; ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk, ++ daintmsk.d32); ++ ++ doepmsk.b.setup = 1; ++ doepmsk.b.xfercompl = 1; ++ doepmsk.b.ahberr = 1; ++ doepmsk.b.epdisabled = 1; ++ ++ if ((core_if->dma_desc_enable) || ++ (core_if->dma_enable ++ && core_if->snpsid >= OTG_CORE_REV_3_00a)) { ++ doepmsk.b.stsphsercvd = 1; ++ } ++ if (core_if->dma_desc_enable) ++ doepmsk.b.bna = 1; ++/* ++ doepmsk.b.babble = 1; ++ doepmsk.b.nyet = 1; ++ ++ if (core_if->dma_enable) { ++ doepmsk.b.nak = 1; ++ } ++*/ ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->doepeachintmsk[0], ++ doepmsk.d32); ++ ++ diepmsk.b.xfercompl = 1; ++ diepmsk.b.timeout = 1; ++ diepmsk.b.epdisabled = 1; ++ diepmsk.b.ahberr = 1; ++ diepmsk.b.intknepmis = 1; ++ if (!core_if->en_multiple_tx_fifo && core_if->dma_enable) ++ diepmsk.b.intknepmis = 0; ++ ++/* if (core_if->dma_desc_enable) { ++ diepmsk.b.bna = 1; ++ } ++*/ ++/* ++ if (core_if->dma_enable) { ++ diepmsk.b.nak = 1; ++ } ++*/ ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->diepeachintmsk[0], ++ diepmsk.d32); ++ } else { ++ daintmsk.b.inep0 = 1; ++ daintmsk.b.outep0 = 1; ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk, ++ daintmsk.d32); ++ ++ doepmsk.b.setup = 1; ++ doepmsk.b.xfercompl = 1; ++ doepmsk.b.ahberr = 1; ++ doepmsk.b.epdisabled = 1; ++ ++ if ((core_if->dma_desc_enable) || ++ (core_if->dma_enable ++ && core_if->snpsid >= OTG_CORE_REV_3_00a)) { ++ doepmsk.b.stsphsercvd = 1; ++ } ++ if (core_if->dma_desc_enable) ++ doepmsk.b.bna = 1; ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, doepmsk.d32); ++ ++ diepmsk.b.xfercompl = 1; ++ diepmsk.b.timeout = 1; ++ diepmsk.b.epdisabled = 1; ++ diepmsk.b.ahberr = 1; ++ if (!core_if->en_multiple_tx_fifo && core_if->dma_enable) ++ diepmsk.b.intknepmis = 0; ++/* ++ if (core_if->dma_desc_enable) { ++ diepmsk.b.bna = 1; ++ } ++*/ ++ ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, diepmsk.d32); ++ } ++ ++ /* Reset Device Address */ ++ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg); ++ dcfg.b.devaddr = 0; ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32); ++ ++ /* setup EP0 to receive SETUP packets */ ++ if (core_if->snpsid <= OTG_CORE_REV_2_94a) ++ ep0_out_start(core_if, pcd); ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.usbreset = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * Get the device speed from the device status register and convert it ++ * to USB speed constant. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static int get_device_speed(dwc_otg_core_if_t * core_if) ++{ ++ dsts_data_t dsts; ++ int speed = 0; ++ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); ++ ++ switch (dsts.b.enumspd) { ++ case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: ++ speed = USB_SPEED_HIGH; ++ break; ++ case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: ++ case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ: ++ speed = USB_SPEED_FULL; ++ break; ++ ++ case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ: ++ speed = USB_SPEED_LOW; ++ break; ++ } ++ ++ return speed; ++} ++ ++/** ++ * Read the device status register and set the device speed in the ++ * data structure. ++ * Set up EP0 to receive SETUP packets by calling dwc_ep0_activate. ++ */ ++int32_t dwc_otg_pcd_handle_enum_done_intr(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; ++ gintsts_data_t gintsts; ++ gusbcfg_data_t gusbcfg; ++ dwc_otg_core_global_regs_t *global_regs = ++ GET_CORE_IF(pcd)->core_global_regs; ++ uint8_t utmi16b, utmi8b; ++ int speed; ++ DWC_DEBUGPL(DBG_PCD, "SPEED ENUM\n"); ++ ++ if (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_2_60a) { ++ utmi16b = 6; //vahrama old value was 6; ++ utmi8b = 9; ++ } else { ++ utmi16b = 4; ++ utmi8b = 8; ++ } ++ dwc_otg_ep0_activate(GET_CORE_IF(pcd), &ep0->dwc_ep); ++ if (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_3_00a) { ++ ep0_out_start(GET_CORE_IF(pcd), pcd); ++ } ++ ++#ifdef DEBUG_EP0 ++ print_ep0_state(pcd); ++#endif ++ ++ if (pcd->ep0state == EP0_DISCONNECT) { ++ pcd->ep0state = EP0_IDLE; ++ } else if (pcd->ep0state == EP0_STALL) { ++ pcd->ep0state = EP0_IDLE; ++ } ++ ++ pcd->ep0state = EP0_IDLE; ++ ++ ep0->stopped = 0; ++ ++ speed = get_device_speed(GET_CORE_IF(pcd)); ++ pcd->fops->connect(pcd, speed); ++ ++ /* Set USB turnaround time based on device speed and PHY interface. */ ++ gusbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg); ++ if (speed == USB_SPEED_HIGH) { ++ if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == ++ DWC_HWCFG2_HS_PHY_TYPE_ULPI) { ++ /* ULPI interface */ ++ gusbcfg.b.usbtrdtim = 9; ++ } ++ if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == ++ DWC_HWCFG2_HS_PHY_TYPE_UTMI) { ++ /* UTMI+ interface */ ++ if (GET_CORE_IF(pcd)->hwcfg4.b.utmi_phy_data_width == 0) { ++ gusbcfg.b.usbtrdtim = utmi8b; ++ } else if (GET_CORE_IF(pcd)->hwcfg4. ++ b.utmi_phy_data_width == 1) { ++ gusbcfg.b.usbtrdtim = utmi16b; ++ } else if (GET_CORE_IF(pcd)-> ++ core_params->phy_utmi_width == 8) { ++ gusbcfg.b.usbtrdtim = utmi8b; ++ } else { ++ gusbcfg.b.usbtrdtim = utmi16b; ++ } ++ } ++ if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == ++ DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI) { ++ /* UTMI+ OR ULPI interface */ ++ if (gusbcfg.b.ulpi_utmi_sel == 1) { ++ /* ULPI interface */ ++ gusbcfg.b.usbtrdtim = 9; ++ } else { ++ /* UTMI+ interface */ ++ if (GET_CORE_IF(pcd)-> ++ core_params->phy_utmi_width == 16) { ++ gusbcfg.b.usbtrdtim = utmi16b; ++ } else { ++ gusbcfg.b.usbtrdtim = utmi8b; ++ } ++ } ++ } ++ } else { ++ /* Full or low speed */ ++ gusbcfg.b.usbtrdtim = 9; ++ } ++ DWC_WRITE_REG32(&global_regs->gusbcfg, gusbcfg.d32); ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.enumdone = 1; ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ gintsts.d32); ++ return 1; ++} ++ ++/** ++ * This interrupt indicates that the ISO OUT Packet was dropped due to ++ * Rx FIFO full or Rx Status Queue Full. If this interrupt occurs ++ * read all the data from the Rx FIFO. ++ */ ++int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr(dwc_otg_pcd_t * pcd) ++{ ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ gintsts_data_t gintsts; ++ ++ DWC_WARN("INTERRUPT Handler not implemented for %s\n", ++ "ISOC Out Dropped"); ++ ++ intr_mask.b.isooutdrop = 1; ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, ++ intr_mask.d32, 0); ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.isooutdrop = 1; ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * This interrupt indicates the end of the portion of the micro-frame ++ * for periodic transactions. If there is a periodic transaction for ++ * the next frame, load the packets into the EP periodic Tx FIFO. ++ */ ++int32_t dwc_otg_pcd_handle_end_periodic_frame_intr(dwc_otg_pcd_t * pcd) ++{ ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ gintsts_data_t gintsts; ++ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "EOP"); ++ ++ intr_mask.b.eopframe = 1; ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, ++ intr_mask.d32, 0); ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.eopframe = 1; ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * This interrupt indicates that EP of the packet on the top of the ++ * non-periodic Tx FIFO does not match EP of the IN Token received. ++ * ++ * The "Device IN Token Queue" Registers are read to determine the ++ * order the IN Tokens have been received. The non-periodic Tx FIFO ++ * is flushed, so it can be reloaded in the order seen in the IN Token ++ * Queue. ++ */ ++int32_t dwc_otg_pcd_handle_ep_mismatch_intr(dwc_otg_pcd_t * pcd) ++{ ++ gintsts_data_t gintsts; ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dctl_data_t dctl; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ if (!core_if->en_multiple_tx_fifo && core_if->dma_enable) { ++ core_if->start_predict = 1; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if); ++ ++ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts); ++ if (!gintsts.b.ginnakeff) { ++ /* Disable EP Mismatch interrupt */ ++ intr_mask.d32 = 0; ++ intr_mask.b.epmismatch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, intr_mask.d32, 0); ++ /* Enable the Global IN NAK Effective Interrupt */ ++ intr_mask.d32 = 0; ++ intr_mask.b.ginnakeff = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32); ++ /* Set the global non-periodic IN NAK handshake */ ++ dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl); ++ dctl.b.sgnpinnak = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32); ++ } else { ++ DWC_PRINTF("gintsts.b.ginnakeff = 1! dctl.b.sgnpinnak not set\n"); ++ } ++ /* Disabling of all EP's will be done in dwc_otg_pcd_handle_in_nak_effective() ++ * handler after Global IN NAK Effective interrupt will be asserted */ ++ } ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.epmismatch = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * This interrupt is valid only in DMA mode. This interrupt indicates that the ++ * core has stopped fetching data for IN endpoints due to the unavailability of ++ * TxFIFO space or Request Queue space. This interrupt is used by the ++ * application for an endpoint mismatch algorithm. ++ * ++ * @param pcd The PCD ++ */ ++int32_t dwc_otg_pcd_handle_ep_fetsusp_intr(dwc_otg_pcd_t * pcd) ++{ ++ gintsts_data_t gintsts; ++ gintmsk_data_t gintmsk_data; ++ dctl_data_t dctl; ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if); ++ ++ /* Clear the global non-periodic IN NAK handshake */ ++ dctl.d32 = 0; ++ dctl.b.cgnpinnak = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); ++ ++ /* Mask GINTSTS.FETSUSP interrupt */ ++ gintmsk_data.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk); ++ gintmsk_data.b.fetsusp = 0; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk_data.d32); ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.fetsusp = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ return 1; ++} ++/** ++ * This funcion stalls EP0. ++ */ ++static inline void ep0_do_stall(dwc_otg_pcd_t * pcd, const int err_val) ++{ ++ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; ++ usb_device_request_t *ctrl = &pcd->setup_pkt->req; ++ DWC_WARN("req %02x.%02x protocol STALL; err %d\n", ++ ctrl->bmRequestType, ctrl->bRequest, err_val); ++ ++ ep0->dwc_ep.is_in = 1; ++ dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep0->dwc_ep); ++ pcd->ep0.stopped = 1; ++ pcd->ep0state = EP0_IDLE; ++ ep0_out_start(GET_CORE_IF(pcd), pcd); ++} ++ ++/** ++ * This functions delegates the setup command to the gadget driver. ++ */ ++static inline void do_gadget_setup(dwc_otg_pcd_t * pcd, ++ usb_device_request_t * ctrl) ++{ ++ int ret = 0; ++ DWC_SPINUNLOCK(pcd->lock); ++ ret = pcd->fops->setup(pcd, (uint8_t *) ctrl); ++ DWC_SPINLOCK(pcd->lock); ++ if (ret < 0) { ++ ep0_do_stall(pcd, ret); ++ } ++ ++ /** @todo This is a g_file_storage gadget driver specific ++ * workaround: a DELAYED_STATUS result from the fsg_setup ++ * routine will result in the gadget queueing a EP0 IN status ++ * phase for a two-stage control transfer. Exactly the same as ++ * a SET_CONFIGURATION/SET_INTERFACE except that this is a class ++ * specific request. Need a generic way to know when the gadget ++ * driver will queue the status phase. Can we assume when we ++ * call the gadget driver setup() function that it will always ++ * queue and require the following flag? Need to look into ++ * this. ++ */ ++ ++ if (ret == 256 + 999) { ++ pcd->request_config = 1; ++ } ++} ++ ++#ifdef DWC_UTE_CFI ++/** ++ * This functions delegates the CFI setup commands to the gadget driver. ++ * This function will return a negative value to indicate a failure. ++ */ ++static inline int cfi_gadget_setup(dwc_otg_pcd_t * pcd, ++ struct cfi_usb_ctrlrequest *ctrl_req) ++{ ++ int ret = 0; ++ ++ if (pcd->fops && pcd->fops->cfi_setup) { ++ DWC_SPINUNLOCK(pcd->lock); ++ ret = pcd->fops->cfi_setup(pcd, ctrl_req); ++ DWC_SPINLOCK(pcd->lock); ++ if (ret < 0) { ++ ep0_do_stall(pcd, ret); ++ return ret; ++ } ++ } ++ ++ return ret; ++} ++#endif ++ ++/** ++ * This function starts the Zero-Length Packet for the IN status phase ++ * of a 2 stage control transfer. ++ */ ++static inline void do_setup_in_status_phase(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; ++ if (pcd->ep0state == EP0_STALL) { ++ return; ++ } ++ ++ pcd->ep0state = EP0_IN_STATUS_PHASE; ++ ++ /* Prepare for more SETUP Packets */ ++ DWC_DEBUGPL(DBG_PCD, "EP0 IN ZLP\n"); ++ if ((GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_3_00a) ++ && (pcd->core_if->dma_desc_enable) ++ && (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len)) { ++ DWC_DEBUGPL(DBG_PCDV, ++ "Data terminated wait next packet in out_desc_addr\n"); ++ pcd->backup_buf = phys_to_virt(ep0->dwc_ep.dma_addr); ++ pcd->data_terminated = 1; ++ } ++ ep0->dwc_ep.xfer_len = 0; ++ ep0->dwc_ep.xfer_count = 0; ++ ep0->dwc_ep.is_in = 1; ++ ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle; ++ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep); ++ ++ /* Prepare for more SETUP Packets */ ++ //ep0_out_start(GET_CORE_IF(pcd), pcd); ++} ++ ++/** ++ * This function starts the Zero-Length Packet for the OUT status phase ++ * of a 2 stage control transfer. ++ */ ++static inline void do_setup_out_status_phase(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; ++ if (pcd->ep0state == EP0_STALL) { ++ DWC_DEBUGPL(DBG_PCD, "EP0 STALLED\n"); ++ return; ++ } ++ pcd->ep0state = EP0_OUT_STATUS_PHASE; ++ ++ DWC_DEBUGPL(DBG_PCD, "EP0 OUT ZLP\n"); ++ ep0->dwc_ep.xfer_len = 0; ++ ep0->dwc_ep.xfer_count = 0; ++ ep0->dwc_ep.is_in = 0; ++ ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle; ++ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep); ++ ++ /* Prepare for more SETUP Packets */ ++ if (GET_CORE_IF(pcd)->dma_enable == 0) { ++ ep0_out_start(GET_CORE_IF(pcd), pcd); ++ } ++} ++ ++/** ++ * Clear the EP halt (STALL) and if pending requests start the ++ * transfer. ++ */ ++static inline void pcd_clear_halt(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep) ++{ ++ if (ep->dwc_ep.stall_clear_flag == 0) ++ dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep); ++ ++ /* Reactive the EP */ ++ dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep); ++ if (ep->stopped) { ++ ep->stopped = 0; ++ /* If there is a request in the EP queue start it */ ++ ++ /** @todo FIXME: this causes an EP mismatch in DMA mode. ++ * epmismatch not yet implemented. */ ++ ++ /* ++ * Above fixme is solved by implmenting a tasklet to call the ++ * start_next_request(), outside of interrupt context at some ++ * time after the current time, after a clear-halt setup packet. ++ * Still need to implement ep mismatch in the future if a gadget ++ * ever uses more than one endpoint at once ++ */ ++ ep->queue_sof = 1; ++ DWC_TASK_SCHEDULE(pcd->start_xfer_tasklet); ++ } ++ /* Start Control Status Phase */ ++ do_setup_in_status_phase(pcd); ++} ++ ++/** ++ * This function is called when the SET_FEATURE TEST_MODE Setup packet ++ * is sent from the host. The Device Control register is written with ++ * the Test Mode bits set to the specified Test Mode. This is done as ++ * a tasklet so that the "Status" phase of the control transfer ++ * completes before transmitting the TEST packets. ++ * ++ * @todo This has not been tested since the tasklet struct was put ++ * into the PCD struct! ++ * ++ */ ++void do_test_mode(void *data) ++{ ++ dctl_data_t dctl; ++ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data; ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ int test_mode = pcd->test_mode; ++ ++// DWC_WARN("%s() has not been tested since being rewritten!\n", __func__); ++ ++ dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl); ++ switch (test_mode) { ++ case 1: // TEST_J ++ dctl.b.tstctl = 1; ++ break; ++ ++ case 2: // TEST_K ++ dctl.b.tstctl = 2; ++ break; ++ ++ case 3: // TEST_SE0_NAK ++ dctl.b.tstctl = 3; ++ break; ++ ++ case 4: // TEST_PACKET ++ dctl.b.tstctl = 4; ++ break; ++ ++ case 5: // TEST_FORCE_ENABLE ++ dctl.b.tstctl = 5; ++ break; ++ } ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32); ++} ++ ++/** ++ * This function process the GET_STATUS Setup Commands. ++ */ ++static inline void do_get_status(dwc_otg_pcd_t * pcd) ++{ ++ usb_device_request_t ctrl = pcd->setup_pkt->req; ++ dwc_otg_pcd_ep_t *ep; ++ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; ++ uint16_t *status = pcd->status_buf; ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCD, ++ "GET_STATUS %02x.%02x v%04x i%04x l%04x\n", ++ ctrl.bmRequestType, ctrl.bRequest, ++ UGETW(ctrl.wValue), UGETW(ctrl.wIndex), ++ UGETW(ctrl.wLength)); ++#endif ++ ++ switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) { ++ case UT_DEVICE: ++ if(UGETW(ctrl.wIndex) == 0xF000) { /* OTG Status selector */ ++ DWC_PRINTF("wIndex - %d\n", UGETW(ctrl.wIndex)); ++ DWC_PRINTF("OTG VERSION - %d\n", core_if->otg_ver); ++ DWC_PRINTF("OTG CAP - %d, %d\n", ++ core_if->core_params->otg_cap, ++ DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE); ++ if (core_if->otg_ver == 1 ++ && core_if->core_params->otg_cap == ++ DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) { ++ uint8_t *otgsts = (uint8_t*)pcd->status_buf; ++ *otgsts = (core_if->otg_sts & 0x1); ++ pcd->ep0_pending = 1; ++ ep0->dwc_ep.start_xfer_buff = ++ (uint8_t *) otgsts; ++ ep0->dwc_ep.xfer_buff = (uint8_t *) otgsts; ++ ep0->dwc_ep.dma_addr = ++ pcd->status_buf_dma_handle; ++ ep0->dwc_ep.xfer_len = 1; ++ ep0->dwc_ep.xfer_count = 0; ++ ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len; ++ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), ++ &ep0->dwc_ep); ++ return; ++ } else { ++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); ++ return; ++ } ++ break; ++ } else { ++ *status = 0x1; /* Self powered */ ++ *status |= pcd->remote_wakeup_enable << 1; ++ break; ++ } ++ case UT_INTERFACE: ++ *status = 0; ++ break; ++ ++ case UT_ENDPOINT: ++ ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex)); ++ if (ep == 0 || UGETW(ctrl.wLength) > 2) { ++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); ++ return; ++ } ++ /** @todo check for EP stall */ ++ *status = ep->stopped; ++ break; ++ } ++ pcd->ep0_pending = 1; ++ ep0->dwc_ep.start_xfer_buff = (uint8_t *) status; ++ ep0->dwc_ep.xfer_buff = (uint8_t *) status; ++ ep0->dwc_ep.dma_addr = pcd->status_buf_dma_handle; ++ ep0->dwc_ep.xfer_len = 2; ++ ep0->dwc_ep.xfer_count = 0; ++ ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len; ++ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep); ++} ++ ++/** ++ * This function process the SET_FEATURE Setup Commands. ++ */ ++static inline void do_set_feature(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ usb_device_request_t ctrl = pcd->setup_pkt->req; ++ dwc_otg_pcd_ep_t *ep = 0; ++ int32_t otg_cap_param = core_if->core_params->otg_cap; ++ gotgctl_data_t gotgctl = {.d32 = 0 }; ++ ++ DWC_DEBUGPL(DBG_PCD, "SET_FEATURE:%02x.%02x v%04x i%04x l%04x\n", ++ ctrl.bmRequestType, ctrl.bRequest, ++ UGETW(ctrl.wValue), UGETW(ctrl.wIndex), ++ UGETW(ctrl.wLength)); ++ DWC_DEBUGPL(DBG_PCD, "otg_cap=%d\n", otg_cap_param); ++ ++ switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) { ++ case UT_DEVICE: ++ switch (UGETW(ctrl.wValue)) { ++ case UF_DEVICE_REMOTE_WAKEUP: ++ pcd->remote_wakeup_enable = 1; ++ break; ++ ++ case UF_TEST_MODE: ++ /* Setup the Test Mode tasklet to do the Test ++ * Packet generation after the SETUP Status ++ * phase has completed. */ ++ ++ /** @todo This has not been tested since the ++ * tasklet struct was put into the PCD ++ * struct! */ ++ pcd->test_mode = UGETW(ctrl.wIndex) >> 8; ++ DWC_TASK_SCHEDULE(pcd->test_mode_tasklet); ++ break; ++ ++ case UF_DEVICE_B_HNP_ENABLE: ++ DWC_DEBUGPL(DBG_PCDV, ++ "SET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n"); ++ ++ /* dev may initiate HNP */ ++ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) { ++ pcd->b_hnp_enable = 1; ++ dwc_otg_pcd_update_otg(pcd, 0); ++ DWC_DEBUGPL(DBG_PCD, "Request B HNP\n"); ++ /**@todo Is the gotgctl.devhnpen cleared ++ * by a USB Reset? */ ++ gotgctl.b.devhnpen = 1; ++ gotgctl.b.hnpreq = 1; ++ DWC_WRITE_REG32(&global_regs->gotgctl, ++ gotgctl.d32); ++ } else { ++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); ++ return; ++ } ++ break; ++ ++ case UF_DEVICE_A_HNP_SUPPORT: ++ /* RH port supports HNP */ ++ DWC_DEBUGPL(DBG_PCDV, ++ "SET_FEATURE: USB_DEVICE_A_HNP_SUPPORT\n"); ++ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) { ++ pcd->a_hnp_support = 1; ++ dwc_otg_pcd_update_otg(pcd, 0); ++ } else { ++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); ++ return; ++ } ++ break; ++ ++ case UF_DEVICE_A_ALT_HNP_SUPPORT: ++ /* other RH port does */ ++ DWC_DEBUGPL(DBG_PCDV, ++ "SET_FEATURE: USB_DEVICE_A_ALT_HNP_SUPPORT\n"); ++ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) { ++ pcd->a_alt_hnp_support = 1; ++ dwc_otg_pcd_update_otg(pcd, 0); ++ } else { ++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); ++ return; ++ } ++ break; ++ ++ default: ++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); ++ return; ++ ++ } ++ do_setup_in_status_phase(pcd); ++ break; ++ ++ case UT_INTERFACE: ++ do_gadget_setup(pcd, &ctrl); ++ break; ++ ++ case UT_ENDPOINT: ++ if (UGETW(ctrl.wValue) == UF_ENDPOINT_HALT) { ++ ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex)); ++ if (ep == 0) { ++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); ++ return; ++ } ++ ep->stopped = 1; ++ dwc_otg_ep_set_stall(core_if, &ep->dwc_ep); ++ } ++ do_setup_in_status_phase(pcd); ++ break; ++ } ++} ++ ++/** ++ * This function process the CLEAR_FEATURE Setup Commands. ++ */ ++static inline void do_clear_feature(dwc_otg_pcd_t * pcd) ++{ ++ usb_device_request_t ctrl = pcd->setup_pkt->req; ++ dwc_otg_pcd_ep_t *ep = 0; ++ ++ DWC_DEBUGPL(DBG_PCD, ++ "CLEAR_FEATURE:%02x.%02x v%04x i%04x l%04x\n", ++ ctrl.bmRequestType, ctrl.bRequest, ++ UGETW(ctrl.wValue), UGETW(ctrl.wIndex), ++ UGETW(ctrl.wLength)); ++ ++ switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) { ++ case UT_DEVICE: ++ switch (UGETW(ctrl.wValue)) { ++ case UF_DEVICE_REMOTE_WAKEUP: ++ pcd->remote_wakeup_enable = 0; ++ break; ++ ++ case UF_TEST_MODE: ++ /** @todo Add CLEAR_FEATURE for TEST modes. */ ++ break; ++ ++ default: ++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); ++ return; ++ } ++ do_setup_in_status_phase(pcd); ++ break; ++ ++ case UT_ENDPOINT: ++ ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex)); ++ if (ep == 0) { ++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); ++ return; ++ } ++ ++ pcd_clear_halt(pcd, ep); ++ ++ break; ++ } ++} ++ ++/** ++ * This function process the SET_ADDRESS Setup Commands. ++ */ ++static inline void do_set_address(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if; ++ usb_device_request_t ctrl = pcd->setup_pkt->req; ++ ++ if (ctrl.bmRequestType == UT_DEVICE) { ++ dcfg_data_t dcfg = {.d32 = 0 }; ++ ++#ifdef DEBUG_EP0 ++// DWC_DEBUGPL(DBG_PCDV, "SET_ADDRESS:%d\n", ctrl.wValue); ++#endif ++ dcfg.b.devaddr = UGETW(ctrl.wValue); ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dcfg, 0, dcfg.d32); ++ do_setup_in_status_phase(pcd); ++ } ++} ++ ++/** ++ * This function processes SETUP commands. In Linux, the USB Command ++ * processing is done in two places - the first being the PCD and the ++ * second in the Gadget Driver (for example, the File-Backed Storage ++ * Gadget Driver). ++ * ++ *
Parameter NameMeaning
otg_capSpecifies the OTG capabilities. The driver will automatically detect the ++ value for this parameter if none is specified. ++ - 0: HNP and SRP capable (default, if available) ++ - 1: SRP Only capable ++ - 2: No HNP/SRP capable ++
dma_enableSpecifies whether to use slave or DMA mode for accessing the data FIFOs. ++ The driver will automatically detect the value for this parameter if none is ++ specified. ++ - 0: Slave ++ - 1: DMA (default, if available) ++
dma_burst_sizeThe DMA Burst size (applicable only for External DMA Mode). ++ - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32) ++
speedSpecifies the maximum speed of operation in host and device mode. The ++ actual speed depends on the speed of the attached device and the value of ++ phy_type. ++ - 0: High Speed (default) ++ - 1: Full Speed ++
host_support_fs_ls_low_powerSpecifies whether low power mode is supported when attached to a Full ++ Speed or Low Speed device in host mode. ++ - 0: Don't support low power mode (default) ++ - 1: Support low power mode ++
host_ls_low_power_phy_clkSpecifies the PHY clock rate in low power mode when connected to a Low ++ Speed device in host mode. This parameter is applicable only if ++ HOST_SUPPORT_FS_LS_LOW_POWER is enabled. ++ - 0: 48 MHz (default) ++ - 1: 6 MHz ++
enable_dynamic_fifo Specifies whether FIFOs may be resized by the driver software. ++ - 0: Use cC FIFO size parameters ++ - 1: Allow dynamic FIFO sizing (default) ++
data_fifo_sizeTotal number of 4-byte words in the data FIFO memory. This memory ++ includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs. ++ - Values: 32 to 32768 (default 8192) ++ ++ Note: The total FIFO memory depth in the FPGA configuration is 8192. ++
dev_rx_fifo_sizeNumber of 4-byte words in the Rx FIFO in device mode when dynamic ++ FIFO sizing is enabled. ++ - Values: 16 to 32768 (default 1064) ++
dev_nperio_tx_fifo_sizeNumber of 4-byte words in the non-periodic Tx FIFO in device mode when ++ dynamic FIFO sizing is enabled. ++ - Values: 16 to 32768 (default 1024) ++
dev_perio_tx_fifo_size_n (n = 1 to 15)Number of 4-byte words in each of the periodic Tx FIFOs in device mode ++ when dynamic FIFO sizing is enabled. ++ - Values: 4 to 768 (default 256) ++
host_rx_fifo_sizeNumber of 4-byte words in the Rx FIFO in host mode when dynamic FIFO ++ sizing is enabled. ++ - Values: 16 to 32768 (default 1024) ++
host_nperio_tx_fifo_sizeNumber of 4-byte words in the non-periodic Tx FIFO in host mode when ++ dynamic FIFO sizing is enabled in the core. ++ - Values: 16 to 32768 (default 1024) ++
host_perio_tx_fifo_sizeNumber of 4-byte words in the host periodic Tx FIFO when dynamic FIFO ++ sizing is enabled. ++ - Values: 16 to 32768 (default 1024) ++
max_transfer_sizeThe maximum transfer size supported in bytes. ++ - Values: 2047 to 65,535 (default 65,535) ++
max_packet_countThe maximum number of packets in a transfer. ++ - Values: 15 to 511 (default 511) ++
host_channelsThe number of host channel registers to use. ++ - Values: 1 to 16 (default 12) ++ ++ Note: The FPGA configuration supports a maximum of 12 host channels. ++
dev_endpointsThe number of endpoints in addition to EP0 available for device mode ++ operations. ++ - Values: 1 to 15 (default 6 IN and OUT) ++ ++ Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in ++ addition to EP0. ++
phy_typeSpecifies the type of PHY interface to use. By default, the driver will ++ automatically detect the phy_type. ++ - 0: Full Speed ++ - 1: UTMI+ (default, if available) ++ - 2: ULPI ++
phy_utmi_widthSpecifies the UTMI+ Data Width. This parameter is applicable for a ++ phy_type of UTMI+. Also, this parameter is applicable only if the ++ OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the ++ core has been configured to work at either data path width. ++ - Values: 8 or 16 bits (default 16) ++
phy_ulpi_ddrSpecifies whether the ULPI operates at double or single data rate. This ++ parameter is only applicable if phy_type is ULPI. ++ - 0: single data rate ULPI interface with 8 bit wide data bus (default) ++ - 1: double data rate ULPI interface with 4 bit wide data bus ++
i2c_enableSpecifies whether to use the I2C interface for full speed PHY. This ++ parameter is only applicable if PHY_TYPE is FS. ++ - 0: Disabled (default) ++ - 1: Enabled ++
ulpi_fs_lsSpecifies whether to use ULPI FS/LS mode only. ++ - 0: Disabled (default) ++ - 1: Enabled ++
ts_dlineSpecifies whether term select D-Line pulsing for all PHYs is enabled. ++ - 0: Disabled (default) ++ - 1: Enabled ++
en_multiple_tx_fifoSpecifies whether dedicatedto tx fifos are enabled for non periodic IN EPs. ++ The driver will automatically detect the value for this parameter if none is ++ specified. ++ - 0: Disabled ++ - 1: Enabled (default, if available) ++
dev_tx_fifo_size_n (n = 1 to 15)Number of 4-byte words in each of the Tx FIFOs in device mode ++ when dynamic FIFO sizing is enabled. ++ - Values: 4 to 768 (default 256) ++
tx_thr_lengthTransmit Threshold length in 32 bit double words ++ - Values: 8 to 128 (default 64) ++
rx_thr_lengthReceive Threshold length in 32 bit double words ++ - Values: 8 to 128 (default 64) ++
thr_ctlSpecifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of ++ this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and ++ Rx transfers accordingly. ++ The driver will automatically detect the value for this parameter if none is ++ specified. ++ - Values: 0 to 7 (default 0) ++ Bit values indicate: ++ - 0: Thresholding disabled ++ - 1: Thresholding enabled ++
dma_desc_enableSpecifies whether to enable Descriptor DMA mode. ++ The driver will automatically detect the value for this parameter if none is ++ specified. ++ - 0: Descriptor DMA disabled ++ - 1: Descriptor DMA (default, if available) ++
mpi_enableSpecifies whether to enable MPI enhancement mode. ++ The driver will automatically detect the value for this parameter if none is ++ specified. ++ - 0: MPI disabled (default) ++ - 1: MPI enable ++
pti_enableSpecifies whether to enable PTI enhancement support. ++ The driver will automatically detect the value for this parameter if none is ++ specified. ++ - 0: PTI disabled (default) ++ - 1: PTI enable ++
lpm_enableSpecifies whether to enable LPM support. ++ The driver will automatically detect the value for this parameter if none is ++ specified. ++ - 0: LPM disabled ++ - 1: LPM enable (default, if available) ++
ic_usb_capSpecifies whether to enable IC_USB capability. ++ The driver will automatically detect the value for this parameter if none is ++ specified. ++ - 0: IC_USB disabled (default, if available) ++ - 1: IC_USB enable ++
ahb_thr_ratioSpecifies AHB Threshold ratio. ++ - Values: 0 to 3 (default 0) ++
power_downSpecifies Power Down(Hibernation) Mode. ++ The driver will automatically detect the value for this parameter if none is ++ specified. ++ - 0: Power Down disabled (default) ++ - 2: Power Down enabled ++
reload_ctlSpecifies whether dynamic reloading of the HFIR register is allowed during ++ run time. The driver will automatically detect the value for this parameter if ++ none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0 ++ the core might misbehave. ++ - 0: Reload Control disabled (default) ++ - 1: Reload Control enabled ++
dev_out_nakSpecifies whether Device OUT NAK enhancement enabled or no. ++ The driver will automatically detect the value for this parameter if ++ none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1b1. ++ - 0: The core does not set NAK after Bulk OUT transfer complete (default) ++ - 1: The core sets NAK after Bulk OUT transfer complete ++
cont_on_bnaSpecifies whether Enable Continue on BNA enabled or no. ++ After receiving BNA interrupt the core disables the endpoint,when the ++ endpoint is re-enabled by the application the ++ - 0: Core starts processing from the DOEPDMA descriptor (default) ++ - 1: Core starts processing from the descriptor which received the BNA. ++ This parameter is valid only when OTG_EN_DESC_DMA == 1b1. ++
ahb_singleThis bit when programmed supports SINGLE transfers for remainder data ++ in a transfer for DMA mode of operation. ++ - 0: The remainder data will be sent using INCR burst size (default) ++ - 1: The remainder data will be sent using SINGLE burst size. ++
adp_enableSpecifies whether ADP feature is enabled. ++ The driver will automatically detect the value for this parameter if none is ++ specified. ++ - 0: ADP feature disabled (default) ++ - 1: ADP feature enabled ++
otg_verSpecifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3 ++ USB OTG device. ++ - 0: OTG 2.0 support disabled (default) ++ - 1: OTG 2.0 support enabled ++
++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ *
Command Driver Description
GET_STATUS PCD Command is processed as ++ * defined in chapter 9 of the USB 2.0 Specification chapter 9 ++ *
CLEAR_FEATURE PCD The Device and Endpoint ++ * requests are the ENDPOINT_HALT feature is procesed, all others the ++ * interface requests are ignored.
SET_FEATURE PCD The Device and Endpoint ++ * requests are processed by the PCD. Interface requests are passed ++ * to the Gadget Driver.
SET_ADDRESS PCD Program the DCFG reg, ++ * with device address received
GET_DESCRIPTOR Gadget Driver Return the ++ * requested descriptor
SET_DESCRIPTOR Gadget Driver Optional - ++ * not implemented by any of the existing Gadget Drivers.
SET_CONFIGURATION Gadget Driver Disable ++ * all EPs and enable EPs for new configuration.
GET_CONFIGURATION Gadget Driver Return ++ * the current configuration
SET_INTERFACE Gadget Driver Disable all ++ * EPs and enable EPs for new configuration.
GET_INTERFACE Gadget Driver Return the ++ * current interface.
SYNC_FRAME PCD Display debug ++ * message.
++ * ++ * When the SETUP Phase Done interrupt occurs, the PCD SETUP commands are ++ * processed by pcd_setup. Calling the Function Driver's setup function from ++ * pcd_setup processes the gadget SETUP commands. ++ */ ++static inline void pcd_setup(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ usb_device_request_t ctrl = pcd->setup_pkt->req; ++ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; ++ ++ deptsiz0_data_t doeptsize0 = {.d32 = 0 }; ++ ++#ifdef DWC_UTE_CFI ++ int retval = 0; ++ struct cfi_usb_ctrlrequest cfi_req; ++#endif ++ ++ doeptsize0.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doeptsiz); ++ ++ /** In BDMA more then 1 setup packet is not supported till 3.00a */ ++ if (core_if->dma_enable && core_if->dma_desc_enable == 0 ++ && (doeptsize0.b.supcnt < 2) ++ && (core_if->snpsid < OTG_CORE_REV_2_94a)) { ++ DWC_ERROR ++ ("\n\n----------- CANNOT handle > 1 setup packet in DMA mode\n\n"); ++ } ++ if ((core_if->snpsid >= OTG_CORE_REV_3_00a) ++ && (core_if->dma_enable == 1) && (core_if->dma_desc_enable == 0)) { ++ ctrl = ++ (pcd->setup_pkt + ++ (3 - doeptsize0.b.supcnt - 1 + ++ ep0->dwc_ep.stp_rollover))->req; ++ } ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCD, "SETUP %02x.%02x v%04x i%04x l%04x\n", ++ ctrl.bmRequestType, ctrl.bRequest, ++ UGETW(ctrl.wValue), UGETW(ctrl.wIndex), ++ UGETW(ctrl.wLength)); ++#endif ++ ++ /* Clean up the request queue */ ++ dwc_otg_request_nuke(ep0); ++ ep0->stopped = 0; ++ ++ if (ctrl.bmRequestType & UE_DIR_IN) { ++ ep0->dwc_ep.is_in = 1; ++ pcd->ep0state = EP0_IN_DATA_PHASE; ++ } else { ++ ep0->dwc_ep.is_in = 0; ++ pcd->ep0state = EP0_OUT_DATA_PHASE; ++ } ++ ++ if (UGETW(ctrl.wLength) == 0) { ++ ep0->dwc_ep.is_in = 1; ++ pcd->ep0state = EP0_IN_STATUS_PHASE; ++ } ++ ++ if (UT_GET_TYPE(ctrl.bmRequestType) != UT_STANDARD) { ++ ++#ifdef DWC_UTE_CFI ++ DWC_MEMCPY(&cfi_req, &ctrl, sizeof(usb_device_request_t)); ++ ++ //printk(KERN_ALERT "CFI: req_type=0x%02x; req=0x%02x\n", ++ ctrl.bRequestType, ctrl.bRequest); ++ if (UT_GET_TYPE(cfi_req.bRequestType) == UT_VENDOR) { ++ if (cfi_req.bRequest > 0xB0 && cfi_req.bRequest < 0xBF) { ++ retval = cfi_setup(pcd, &cfi_req); ++ if (retval < 0) { ++ ep0_do_stall(pcd, retval); ++ pcd->ep0_pending = 0; ++ return; ++ } ++ ++ /* if need gadget setup then call it and check the retval */ ++ if (pcd->cfi->need_gadget_att) { ++ retval = ++ cfi_gadget_setup(pcd, ++ &pcd-> ++ cfi->ctrl_req); ++ if (retval < 0) { ++ pcd->ep0_pending = 0; ++ return; ++ } ++ } ++ ++ if (pcd->cfi->need_status_in_complete) { ++ do_setup_in_status_phase(pcd); ++ } ++ return; ++ } ++ } ++#endif ++ ++ /* handle non-standard (class/vendor) requests in the gadget driver */ ++ do_gadget_setup(pcd, &ctrl); ++ return; ++ } ++ ++ /** @todo NGS: Handle bad setup packet? */ ++ ++/////////////////////////////////////////// ++//// --- Standard Request handling --- //// ++ ++ switch (ctrl.bRequest) { ++ case UR_GET_STATUS: ++ do_get_status(pcd); ++ break; ++ ++ case UR_CLEAR_FEATURE: ++ do_clear_feature(pcd); ++ break; ++ ++ case UR_SET_FEATURE: ++ do_set_feature(pcd); ++ break; ++ ++ case UR_SET_ADDRESS: ++ do_set_address(pcd); ++ break; ++ ++ case UR_SET_INTERFACE: ++ case UR_SET_CONFIG: ++// _pcd->request_config = 1; /* Configuration changed */ ++ do_gadget_setup(pcd, &ctrl); ++ break; ++ ++ case UR_SYNCH_FRAME: ++ do_gadget_setup(pcd, &ctrl); ++ break; ++ ++ default: ++ /* Call the Gadget Driver's setup functions */ ++ do_gadget_setup(pcd, &ctrl); ++ break; ++ } ++} ++ ++/** ++ * This function completes the ep0 control transfer. ++ */ ++static int32_t ep0_complete_request(dwc_otg_pcd_ep_t * ep) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd); ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ dwc_otg_dev_in_ep_regs_t *in_ep_regs = ++ dev_if->in_ep_regs[ep->dwc_ep.num]; ++#ifdef DEBUG_EP0 ++ dwc_otg_dev_out_ep_regs_t *out_ep_regs = ++ dev_if->out_ep_regs[ep->dwc_ep.num]; ++#endif ++ deptsiz0_data_t deptsiz; ++ dev_dma_desc_sts_t desc_sts; ++ dwc_otg_pcd_request_t *req; ++ int is_last = 0; ++ dwc_otg_pcd_t *pcd = ep->pcd; ++ ++#ifdef DWC_UTE_CFI ++ struct cfi_usb_ctrlrequest *ctrlreq; ++ int retval = -DWC_E_NOT_SUPPORTED; ++#endif ++ ++ desc_sts.b.bytes = 0; ++ ++ if (pcd->ep0_pending && DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ if (ep->dwc_ep.is_in) { ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCDV, "Do setup OUT status phase\n"); ++#endif ++ do_setup_out_status_phase(pcd); ++ } else { ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCDV, "Do setup IN status phase\n"); ++#endif ++ ++#ifdef DWC_UTE_CFI ++ ctrlreq = &pcd->cfi->ctrl_req; ++ ++ if (UT_GET_TYPE(ctrlreq->bRequestType) == UT_VENDOR) { ++ if (ctrlreq->bRequest > 0xB0 ++ && ctrlreq->bRequest < 0xBF) { ++ ++ /* Return if the PCD failed to handle the request */ ++ if ((retval = ++ pcd->cfi->ops. ++ ctrl_write_complete(pcd->cfi, ++ pcd)) < 0) { ++ CFI_INFO ++ ("ERROR setting a new value in the PCD(%d)\n", ++ retval); ++ ep0_do_stall(pcd, retval); ++ pcd->ep0_pending = 0; ++ return 0; ++ } ++ ++ /* If the gadget needs to be notified on the request */ ++ if (pcd->cfi->need_gadget_att == 1) { ++ //retval = do_gadget_setup(pcd, &pcd->cfi->ctrl_req); ++ retval = ++ cfi_gadget_setup(pcd, ++ &pcd->cfi-> ++ ctrl_req); ++ ++ /* Return from the function if the gadget failed to process ++ * the request properly - this should never happen !!! ++ */ ++ if (retval < 0) { ++ CFI_INFO ++ ("ERROR setting a new value in the gadget(%d)\n", ++ retval); ++ pcd->ep0_pending = 0; ++ return 0; ++ } ++ } ++ ++ CFI_INFO("%s: RETVAL=%d\n", __func__, ++ retval); ++ /* If we hit here then the PCD and the gadget has properly ++ * handled the request - so send the ZLP IN to the host. ++ */ ++ /* @todo: MAS - decide whether we need to start the setup ++ * stage based on the need_setup value of the cfi object ++ */ ++ do_setup_in_status_phase(pcd); ++ pcd->ep0_pending = 0; ++ return 1; ++ } ++ } ++#endif ++ ++ do_setup_in_status_phase(pcd); ++ } ++ pcd->ep0_pending = 0; ++ return 1; ++ } ++ ++ if (DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ return 0; ++ } ++ req = DWC_CIRCLEQ_FIRST(&ep->queue); ++ ++ if (pcd->ep0state == EP0_OUT_STATUS_PHASE ++ || pcd->ep0state == EP0_IN_STATUS_PHASE) { ++ is_last = 1; ++ } else if (ep->dwc_ep.is_in) { ++ deptsiz.d32 = DWC_READ_REG32(&in_ep_regs->dieptsiz); ++ if (core_if->dma_desc_enable != 0) ++ desc_sts = dev_if->in_desc_addr->status; ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCDV, "%d len=%d xfersize=%d pktcnt=%d\n", ++ ep->dwc_ep.num, ep->dwc_ep.xfer_len, ++ deptsiz.b.xfersize, deptsiz.b.pktcnt); ++#endif ++ ++ if (((core_if->dma_desc_enable == 0) ++ && (deptsiz.b.xfersize == 0)) ++ || ((core_if->dma_desc_enable != 0) ++ && (desc_sts.b.bytes == 0))) { ++ req->actual = ep->dwc_ep.xfer_count; ++ /* Is a Zero Len Packet needed? */ ++ if (req->sent_zlp) { ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCD, "Setup Rx ZLP\n"); ++#endif ++ req->sent_zlp = 0; ++ } ++ do_setup_out_status_phase(pcd); ++ } ++ } else { ++ /* ep0-OUT */ ++#ifdef DEBUG_EP0 ++ deptsiz.d32 = DWC_READ_REG32(&out_ep_regs->doeptsiz); ++ DWC_DEBUGPL(DBG_PCDV, "%d len=%d xsize=%d pktcnt=%d\n", ++ ep->dwc_ep.num, ep->dwc_ep.xfer_len, ++ deptsiz.b.xfersize, deptsiz.b.pktcnt); ++#endif ++ req->actual = ep->dwc_ep.xfer_count; ++ ++ /* Is a Zero Len Packet needed? */ ++ if (req->sent_zlp) { ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCDV, "Setup Tx ZLP\n"); ++#endif ++ req->sent_zlp = 0; ++ } ++ /* For older cores do setup in status phase in Slave/BDMA modes, ++ * starting from 3.00 do that only in slave, and for DMA modes ++ * just re-enable ep 0 OUT here*/ ++ if (core_if->dma_enable == 0 ++ || (core_if->dma_desc_enable == 0 ++ && core_if->snpsid <= OTG_CORE_REV_2_94a)) { ++ do_setup_in_status_phase(pcd); ++ } else if (core_if->snpsid >= OTG_CORE_REV_3_00a) { ++ DWC_DEBUGPL(DBG_PCDV, ++ "Enable out ep before in status phase\n"); ++ ep0_out_start(core_if, pcd); ++ } ++ } ++ ++ /* Complete the request */ ++ if (is_last) { ++ dwc_otg_request_done(ep, req, 0); ++ ep->dwc_ep.start_xfer_buff = 0; ++ ep->dwc_ep.xfer_buff = 0; ++ ep->dwc_ep.xfer_len = 0; ++ return 1; ++ } ++ return 0; ++} ++ ++#ifdef DWC_UTE_CFI ++/** ++ * This function calculates traverses all the CFI DMA descriptors and ++ * and accumulates the bytes that are left to be transfered. ++ * ++ * @return The total bytes left to transfered, or a negative value as failure ++ */ ++static inline int cfi_calc_desc_residue(dwc_otg_pcd_ep_t * ep) ++{ ++ int32_t ret = 0; ++ int i; ++ struct dwc_otg_dma_desc *ddesc = NULL; ++ struct cfi_ep *cfiep; ++ ++ /* See if the pcd_ep has its respective cfi_ep mapped */ ++ cfiep = get_cfi_ep_by_pcd_ep(ep->pcd->cfi, ep); ++ if (!cfiep) { ++ CFI_INFO("%s: Failed to find ep\n", __func__); ++ return -1; ++ } ++ ++ ddesc = ep->dwc_ep.descs; ++ ++ for (i = 0; (i < cfiep->desc_count) && (i < MAX_DMA_DESCS_PER_EP); i++) { ++ ++#if defined(PRINT_CFI_DMA_DESCS) ++ print_desc(ddesc, ep->ep.name, i); ++#endif ++ ret += ddesc->status.b.bytes; ++ ddesc++; ++ } ++ ++ if (ret) ++ CFI_INFO("!!!!!!!!!! WARNING (%s) - residue=%d\n", __func__, ++ ret); ++ ++ return ret; ++} ++#endif ++ ++/** ++ * This function completes the request for the EP. If there are ++ * additional requests for the EP in the queue they will be started. ++ */ ++static void complete_ep(dwc_otg_pcd_ep_t * ep) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd); ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ dwc_otg_dev_in_ep_regs_t *in_ep_regs = ++ dev_if->in_ep_regs[ep->dwc_ep.num]; ++ deptsiz_data_t deptsiz; ++ dev_dma_desc_sts_t desc_sts; ++ dwc_otg_pcd_request_t *req = 0; ++ dwc_otg_dev_dma_desc_t *dma_desc; ++ uint32_t byte_count = 0; ++ int is_last = 0; ++ int i; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s() %d-%s\n", __func__, ep->dwc_ep.num, ++ (ep->dwc_ep.is_in ? "IN" : "OUT")); ++ ++ /* Get any pending requests */ ++ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ req = DWC_CIRCLEQ_FIRST(&ep->queue); ++ if (!req) { ++ DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep); ++ return; ++ } ++ } else { ++ DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep); ++ return; ++ } ++ ++ DWC_DEBUGPL(DBG_PCD, "Requests %d\n", ep->pcd->request_pending); ++ ++ if (ep->dwc_ep.is_in) { ++ deptsiz.d32 = DWC_READ_REG32(&in_ep_regs->dieptsiz); ++ ++ if (core_if->dma_enable) { ++ if (core_if->dma_desc_enable == 0) { ++ if (deptsiz.b.xfersize == 0 ++ && deptsiz.b.pktcnt == 0) { ++ byte_count = ++ ep->dwc_ep.xfer_len - ++ ep->dwc_ep.xfer_count; ++ ++ ep->dwc_ep.xfer_buff += byte_count; ++ ep->dwc_ep.dma_addr += byte_count; ++ ep->dwc_ep.xfer_count += byte_count; ++ ++ DWC_DEBUGPL(DBG_PCDV, ++ "%d-%s len=%d xfersize=%d pktcnt=%d\n", ++ ep->dwc_ep.num, ++ (ep->dwc_ep. ++ is_in ? "IN" : "OUT"), ++ ep->dwc_ep.xfer_len, ++ deptsiz.b.xfersize, ++ deptsiz.b.pktcnt); ++ ++ if (ep->dwc_ep.xfer_len < ++ ep->dwc_ep.total_len) { ++ dwc_otg_ep_start_transfer ++ (core_if, &ep->dwc_ep); ++ } else if (ep->dwc_ep.sent_zlp) { ++ /* ++ * This fragment of code should initiate 0 ++ * length transfer in case if it is queued ++ * a transfer with size divisible to EPs max ++ * packet size and with usb_request zero field ++ * is set, which means that after data is transfered, ++ * it is also should be transfered ++ * a 0 length packet at the end. For Slave and ++ * Buffer DMA modes in this case SW has ++ * to initiate 2 transfers one with transfer size, ++ * and the second with 0 size. For Descriptor ++ * DMA mode SW is able to initiate a transfer, ++ * which will handle all the packets including ++ * the last 0 length. ++ */ ++ ep->dwc_ep.sent_zlp = 0; ++ dwc_otg_ep_start_zl_transfer ++ (core_if, &ep->dwc_ep); ++ } else { ++ is_last = 1; ++ } ++ } else { ++ if (ep->dwc_ep.type == ++ DWC_OTG_EP_TYPE_ISOC) { ++ req->actual = 0; ++ dwc_otg_request_done(ep, req, 0); ++ ++ ep->dwc_ep.start_xfer_buff = 0; ++ ep->dwc_ep.xfer_buff = 0; ++ ep->dwc_ep.xfer_len = 0; ++ ++ /* If there is a request in the queue start it. */ ++ start_next_request(ep); ++ } else ++ DWC_WARN ++ ("Incomplete transfer (%d - %s [siz=%d pkt=%d])\n", ++ ep->dwc_ep.num, ++ (ep->dwc_ep.is_in ? "IN" : "OUT"), ++ deptsiz.b.xfersize, ++ deptsiz.b.pktcnt); ++ } ++ } else { ++ dma_desc = ep->dwc_ep.desc_addr; ++ byte_count = 0; ++ ep->dwc_ep.sent_zlp = 0; ++ ++#ifdef DWC_UTE_CFI ++ CFI_INFO("%s: BUFFER_MODE=%d\n", __func__, ++ ep->dwc_ep.buff_mode); ++ if (ep->dwc_ep.buff_mode != BM_STANDARD) { ++ int residue; ++ ++ residue = cfi_calc_desc_residue(ep); ++ if (residue < 0) ++ return; ++ ++ byte_count = residue; ++ } else { ++#endif ++ for (i = 0; i < ep->dwc_ep.desc_cnt; ++ ++i) { ++ desc_sts = dma_desc->status; ++ byte_count += desc_sts.b.bytes; ++ dma_desc++; ++ } ++#ifdef DWC_UTE_CFI ++ } ++#endif ++ if (byte_count == 0) { ++ ep->dwc_ep.xfer_count = ++ ep->dwc_ep.total_len; ++ is_last = 1; ++ } else { ++ DWC_WARN("Incomplete transfer\n"); ++ } ++ } ++ } else { ++ if (deptsiz.b.xfersize == 0 && deptsiz.b.pktcnt == 0) { ++ DWC_DEBUGPL(DBG_PCDV, ++ "%d-%s len=%d xfersize=%d pktcnt=%d\n", ++ ep->dwc_ep.num, ++ ep->dwc_ep.is_in ? "IN" : "OUT", ++ ep->dwc_ep.xfer_len, ++ deptsiz.b.xfersize, ++ deptsiz.b.pktcnt); ++ ++ /* Check if the whole transfer was completed, ++ * if no, setup transfer for next portion of data ++ */ ++ if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) { ++ dwc_otg_ep_start_transfer(core_if, ++ &ep->dwc_ep); ++ } else if (ep->dwc_ep.sent_zlp) { ++ /* ++ * This fragment of code should initiate 0 ++ * length trasfer in case if it is queued ++ * a trasfer with size divisible to EPs max ++ * packet size and with usb_request zero field ++ * is set, which means that after data is transfered, ++ * it is also should be transfered ++ * a 0 length packet at the end. For Slave and ++ * Buffer DMA modes in this case SW has ++ * to initiate 2 transfers one with transfer size, ++ * and the second with 0 size. For Desriptor ++ * DMA mode SW is able to initiate a transfer, ++ * which will handle all the packets including ++ * the last 0 legth. ++ */ ++ ep->dwc_ep.sent_zlp = 0; ++ dwc_otg_ep_start_zl_transfer(core_if, ++ &ep->dwc_ep); ++ } else { ++ is_last = 1; ++ } ++ } else { ++ DWC_WARN ++ ("Incomplete transfer (%d-%s [siz=%d pkt=%d])\n", ++ ep->dwc_ep.num, ++ (ep->dwc_ep.is_in ? "IN" : "OUT"), ++ deptsiz.b.xfersize, deptsiz.b.pktcnt); ++ } ++ } ++ } else { ++ dwc_otg_dev_out_ep_regs_t *out_ep_regs = ++ dev_if->out_ep_regs[ep->dwc_ep.num]; ++ desc_sts.d32 = 0; ++ if (core_if->dma_enable) { ++ if (core_if->dma_desc_enable) { ++ dma_desc = ep->dwc_ep.desc_addr; ++ byte_count = 0; ++ ep->dwc_ep.sent_zlp = 0; ++ ++#ifdef DWC_UTE_CFI ++ CFI_INFO("%s: BUFFER_MODE=%d\n", __func__, ++ ep->dwc_ep.buff_mode); ++ if (ep->dwc_ep.buff_mode != BM_STANDARD) { ++ int residue; ++ residue = cfi_calc_desc_residue(ep); ++ if (residue < 0) ++ return; ++ byte_count = residue; ++ } else { ++#endif ++ ++ for (i = 0; i < ep->dwc_ep.desc_cnt; ++ ++i) { ++ desc_sts = dma_desc->status; ++ byte_count += desc_sts.b.bytes; ++ dma_desc++; ++ } ++ ++#ifdef DWC_UTE_CFI ++ } ++#endif ++ /* Checking for interrupt Out transfers with not ++ * dword aligned mps sizes ++ */ ++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_INTR && ++ (ep->dwc_ep.maxpacket%4)) { ++ ep->dwc_ep.xfer_count = ++ ep->dwc_ep.total_len - byte_count; ++ if ((ep->dwc_ep.xfer_len % ++ ep->dwc_ep.maxpacket) ++ && (ep->dwc_ep.xfer_len / ++ ep->dwc_ep.maxpacket < ++ MAX_DMA_DESC_CNT)) ++ ep->dwc_ep.xfer_len -= ++ (ep->dwc_ep.desc_cnt - ++ 1) * ep->dwc_ep.maxpacket + ++ ep->dwc_ep.xfer_len % ++ ep->dwc_ep.maxpacket; ++ else ++ ep->dwc_ep.xfer_len -= ++ ep->dwc_ep.desc_cnt * ++ ep->dwc_ep.maxpacket; ++ if (ep->dwc_ep.xfer_len > 0) { ++ dwc_otg_ep_start_transfer ++ (core_if, &ep->dwc_ep); ++ } else { ++ is_last = 1; ++ } ++ } else { ++ ep->dwc_ep.xfer_count = ++ ep->dwc_ep.total_len - byte_count + ++ ((4 - ++ (ep->dwc_ep. ++ total_len & 0x3)) & 0x3); ++ is_last = 1; ++ } ++ } else { ++ deptsiz.d32 = 0; ++ deptsiz.d32 = ++ DWC_READ_REG32(&out_ep_regs->doeptsiz); ++ ++ byte_count = (ep->dwc_ep.xfer_len - ++ ep->dwc_ep.xfer_count - ++ deptsiz.b.xfersize); ++ ep->dwc_ep.xfer_buff += byte_count; ++ ep->dwc_ep.dma_addr += byte_count; ++ ep->dwc_ep.xfer_count += byte_count; ++ ++ /* Check if the whole transfer was completed, ++ * if no, setup transfer for next portion of data ++ */ ++ if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) { ++ dwc_otg_ep_start_transfer(core_if, ++ &ep->dwc_ep); ++ } else if (ep->dwc_ep.sent_zlp) { ++ /* ++ * This fragment of code should initiate 0 ++ * length trasfer in case if it is queued ++ * a trasfer with size divisible to EPs max ++ * packet size and with usb_request zero field ++ * is set, which means that after data is transfered, ++ * it is also should be transfered ++ * a 0 length packet at the end. For Slave and ++ * Buffer DMA modes in this case SW has ++ * to initiate 2 transfers one with transfer size, ++ * and the second with 0 size. For Desriptor ++ * DMA mode SW is able to initiate a transfer, ++ * which will handle all the packets including ++ * the last 0 legth. ++ */ ++ ep->dwc_ep.sent_zlp = 0; ++ dwc_otg_ep_start_zl_transfer(core_if, ++ &ep->dwc_ep); ++ } else { ++ is_last = 1; ++ } ++ } ++ } else { ++ /* Check if the whole transfer was completed, ++ * if no, setup transfer for next portion of data ++ */ ++ if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) { ++ dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep); ++ } else if (ep->dwc_ep.sent_zlp) { ++ /* ++ * This fragment of code should initiate 0 ++ * length transfer in case if it is queued ++ * a transfer with size divisible to EPs max ++ * packet size and with usb_request zero field ++ * is set, which means that after data is transfered, ++ * it is also should be transfered ++ * a 0 length packet at the end. For Slave and ++ * Buffer DMA modes in this case SW has ++ * to initiate 2 transfers one with transfer size, ++ * and the second with 0 size. For Descriptor ++ * DMA mode SW is able to initiate a transfer, ++ * which will handle all the packets including ++ * the last 0 length. ++ */ ++ ep->dwc_ep.sent_zlp = 0; ++ dwc_otg_ep_start_zl_transfer(core_if, ++ &ep->dwc_ep); ++ } else { ++ is_last = 1; ++ } ++ } ++ ++ DWC_DEBUGPL(DBG_PCDV, ++ "addr %p, %d-%s len=%d cnt=%d xsize=%d pktcnt=%d\n", ++ &out_ep_regs->doeptsiz, ep->dwc_ep.num, ++ ep->dwc_ep.is_in ? "IN" : "OUT", ++ ep->dwc_ep.xfer_len, ep->dwc_ep.xfer_count, ++ deptsiz.b.xfersize, deptsiz.b.pktcnt); ++ } ++ ++ /* Complete the request */ ++ if (is_last) { ++#ifdef DWC_UTE_CFI ++ if (ep->dwc_ep.buff_mode != BM_STANDARD) { ++ req->actual = ep->dwc_ep.cfi_req_len - byte_count; ++ } else { ++#endif ++ req->actual = ep->dwc_ep.xfer_count; ++#ifdef DWC_UTE_CFI ++ } ++#endif ++ if (req->dw_align_buf) { ++ if (!ep->dwc_ep.is_in) { ++ dwc_memcpy(req->buf, req->dw_align_buf, req->length); ++ } ++ DWC_DMA_FREE(req->length, req->dw_align_buf, ++ req->dw_align_buf_dma); ++ } ++ ++ dwc_otg_request_done(ep, req, 0); ++ ++ ep->dwc_ep.start_xfer_buff = 0; ++ ep->dwc_ep.xfer_buff = 0; ++ ep->dwc_ep.xfer_len = 0; ++ ++ /* If there is a request in the queue start it. */ ++ start_next_request(ep); ++ } ++} ++ ++#ifdef DWC_EN_ISOC ++ ++/** ++ * This function BNA interrupt for Isochronous EPs ++ * ++ */ ++static void dwc_otg_pcd_handle_iso_bna(dwc_otg_pcd_ep_t * ep) ++{ ++ dwc_ep_t *dwc_ep = &ep->dwc_ep; ++ volatile uint32_t *addr; ++ depctl_data_t depctl = {.d32 = 0 }; ++ dwc_otg_pcd_t *pcd = ep->pcd; ++ dwc_otg_dev_dma_desc_t *dma_desc; ++ int i; ++ ++ dma_desc = ++ dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * (dwc_ep->proc_buf_num); ++ ++ if (dwc_ep->is_in) { ++ dev_dma_desc_sts_t sts = {.d32 = 0 }; ++ for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) { ++ sts.d32 = dma_desc->status.d32; ++ sts.b_iso_in.bs = BS_HOST_READY; ++ dma_desc->status.d32 = sts.d32; ++ } ++ } else { ++ dev_dma_desc_sts_t sts = {.d32 = 0 }; ++ for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) { ++ sts.d32 = dma_desc->status.d32; ++ sts.b_iso_out.bs = BS_HOST_READY; ++ dma_desc->status.d32 = sts.d32; ++ } ++ } ++ ++ if (dwc_ep->is_in == 0) { ++ addr = ++ &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep-> ++ num]->doepctl; ++ } else { ++ addr = ++ &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl; ++ } ++ depctl.b.epena = 1; ++ DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32); ++} ++ ++/** ++ * This function sets latest iso packet information(non-PTI mode) ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to start the transfer on. ++ * ++ */ ++void set_current_pkt_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ deptsiz_data_t deptsiz = {.d32 = 0 }; ++ dma_addr_t dma_addr; ++ uint32_t offset; ++ ++ if (ep->proc_buf_num) ++ dma_addr = ep->dma_addr1; ++ else ++ dma_addr = ep->dma_addr0; ++ ++ if (ep->is_in) { ++ deptsiz.d32 = ++ DWC_READ_REG32(&core_if->dev_if-> ++ in_ep_regs[ep->num]->dieptsiz); ++ offset = ep->data_per_frame; ++ } else { ++ deptsiz.d32 = ++ DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[ep->num]->doeptsiz); ++ offset = ++ ep->data_per_frame + ++ (0x4 & (0x4 - (ep->data_per_frame & 0x3))); ++ } ++ ++ if (!deptsiz.b.xfersize) { ++ ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame; ++ ep->pkt_info[ep->cur_pkt].offset = ++ ep->cur_pkt_dma_addr - dma_addr; ++ ep->pkt_info[ep->cur_pkt].status = 0; ++ } else { ++ ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame; ++ ep->pkt_info[ep->cur_pkt].offset = ++ ep->cur_pkt_dma_addr - dma_addr; ++ ep->pkt_info[ep->cur_pkt].status = -DWC_E_NO_DATA; ++ } ++ ep->cur_pkt_addr += offset; ++ ep->cur_pkt_dma_addr += offset; ++ ep->cur_pkt++; ++} ++ ++/** ++ * This function sets latest iso packet information(DDMA mode) ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param dwc_ep The EP to start the transfer on. ++ * ++ */ ++static void set_ddma_iso_pkts_info(dwc_otg_core_if_t * core_if, ++ dwc_ep_t * dwc_ep) ++{ ++ dwc_otg_dev_dma_desc_t *dma_desc; ++ dev_dma_desc_sts_t sts = {.d32 = 0 }; ++ iso_pkt_info_t *iso_packet; ++ uint32_t data_per_desc; ++ uint32_t offset; ++ int i, j; ++ ++ iso_packet = dwc_ep->pkt_info; ++ ++ /** Reinit closed DMA Descriptors*/ ++ /** ISO OUT EP */ ++ if (dwc_ep->is_in == 0) { ++ dma_desc = ++ dwc_ep->iso_desc_addr + ++ dwc_ep->desc_cnt * dwc_ep->proc_buf_num; ++ offset = 0; ++ ++ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; ++ i += dwc_ep->pkt_per_frm) { ++ for (j = 0; j < dwc_ep->pkt_per_frm; ++j) { ++ data_per_desc = ++ ((j + 1) * dwc_ep->maxpacket > ++ dwc_ep-> ++ data_per_frame) ? dwc_ep->data_per_frame - ++ j * dwc_ep->maxpacket : dwc_ep->maxpacket; ++ data_per_desc += ++ (data_per_desc % 4) ? (4 - ++ data_per_desc % ++ 4) : 0; ++ ++ sts.d32 = dma_desc->status.d32; ++ ++ /* Write status in iso_packet_decsriptor */ ++ iso_packet->status = ++ sts.b_iso_out.rxsts + ++ (sts.b_iso_out.bs ^ BS_DMA_DONE); ++ if (iso_packet->status) { ++ iso_packet->status = -DWC_E_NO_DATA; ++ } ++ ++ /* Received data length */ ++ if (!sts.b_iso_out.rxbytes) { ++ iso_packet->length = ++ data_per_desc - ++ sts.b_iso_out.rxbytes; ++ } else { ++ iso_packet->length = ++ data_per_desc - ++ sts.b_iso_out.rxbytes + (4 - ++ dwc_ep->data_per_frame ++ % 4); ++ } ++ ++ iso_packet->offset = offset; ++ ++ offset += data_per_desc; ++ dma_desc++; ++ iso_packet++; ++ } ++ } ++ ++ for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) { ++ data_per_desc = ++ ((j + 1) * dwc_ep->maxpacket > ++ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame - ++ j * dwc_ep->maxpacket : dwc_ep->maxpacket; ++ data_per_desc += ++ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0; ++ ++ sts.d32 = dma_desc->status.d32; ++ ++ /* Write status in iso_packet_decsriptor */ ++ iso_packet->status = ++ sts.b_iso_out.rxsts + ++ (sts.b_iso_out.bs ^ BS_DMA_DONE); ++ if (iso_packet->status) { ++ iso_packet->status = -DWC_E_NO_DATA; ++ } ++ ++ /* Received data length */ ++ iso_packet->length = ++ dwc_ep->data_per_frame - sts.b_iso_out.rxbytes; ++ ++ iso_packet->offset = offset; ++ ++ offset += data_per_desc; ++ iso_packet++; ++ dma_desc++; ++ } ++ ++ sts.d32 = dma_desc->status.d32; ++ ++ /* Write status in iso_packet_decsriptor */ ++ iso_packet->status = ++ sts.b_iso_out.rxsts + (sts.b_iso_out.bs ^ BS_DMA_DONE); ++ if (iso_packet->status) { ++ iso_packet->status = -DWC_E_NO_DATA; ++ } ++ /* Received data length */ ++ if (!sts.b_iso_out.rxbytes) { ++ iso_packet->length = ++ dwc_ep->data_per_frame - sts.b_iso_out.rxbytes; ++ } else { ++ iso_packet->length = ++ dwc_ep->data_per_frame - sts.b_iso_out.rxbytes + ++ (4 - dwc_ep->data_per_frame % 4); ++ } ++ ++ iso_packet->offset = offset; ++ } else { ++/** ISO IN EP */ ++ ++ dma_desc = ++ dwc_ep->iso_desc_addr + ++ dwc_ep->desc_cnt * dwc_ep->proc_buf_num; ++ ++ for (i = 0; i < dwc_ep->desc_cnt - 1; i++) { ++ sts.d32 = dma_desc->status.d32; ++ ++ /* Write status in iso packet descriptor */ ++ iso_packet->status = ++ sts.b_iso_in.txsts + ++ (sts.b_iso_in.bs ^ BS_DMA_DONE); ++ if (iso_packet->status != 0) { ++ iso_packet->status = -DWC_E_NO_DATA; ++ ++ } ++ /* Bytes has been transfered */ ++ iso_packet->length = ++ dwc_ep->data_per_frame - sts.b_iso_in.txbytes; ++ ++ dma_desc++; ++ iso_packet++; ++ } ++ ++ sts.d32 = dma_desc->status.d32; ++ while (sts.b_iso_in.bs == BS_DMA_BUSY) { ++ sts.d32 = dma_desc->status.d32; ++ } ++ ++ /* Write status in iso packet descriptor ??? do be done with ERROR codes */ ++ iso_packet->status = ++ sts.b_iso_in.txsts + (sts.b_iso_in.bs ^ BS_DMA_DONE); ++ if (iso_packet->status != 0) { ++ iso_packet->status = -DWC_E_NO_DATA; ++ } ++ ++ /* Bytes has been transfered */ ++ iso_packet->length = ++ dwc_ep->data_per_frame - sts.b_iso_in.txbytes; ++ } ++} ++ ++/** ++ * This function reinitialize DMA Descriptors for Isochronous transfer ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param dwc_ep The EP to start the transfer on. ++ * ++ */ ++static void reinit_ddma_iso_xfer(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep) ++{ ++ int i, j; ++ dwc_otg_dev_dma_desc_t *dma_desc; ++ dma_addr_t dma_ad; ++ volatile uint32_t *addr; ++ dev_dma_desc_sts_t sts = {.d32 = 0 }; ++ uint32_t data_per_desc; ++ ++ if (dwc_ep->is_in == 0) { ++ addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl; ++ } else { ++ addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl; ++ } ++ ++ if (dwc_ep->proc_buf_num == 0) { ++ /** Buffer 0 descriptors setup */ ++ dma_ad = dwc_ep->dma_addr0; ++ } else { ++ /** Buffer 1 descriptors setup */ ++ dma_ad = dwc_ep->dma_addr1; ++ } ++ ++ /** Reinit closed DMA Descriptors*/ ++ /** ISO OUT EP */ ++ if (dwc_ep->is_in == 0) { ++ dma_desc = ++ dwc_ep->iso_desc_addr + ++ dwc_ep->desc_cnt * dwc_ep->proc_buf_num; ++ ++ sts.b_iso_out.bs = BS_HOST_READY; ++ sts.b_iso_out.rxsts = 0; ++ sts.b_iso_out.l = 0; ++ sts.b_iso_out.sp = 0; ++ sts.b_iso_out.ioc = 0; ++ sts.b_iso_out.pid = 0; ++ sts.b_iso_out.framenum = 0; ++ ++ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; ++ i += dwc_ep->pkt_per_frm) { ++ for (j = 0; j < dwc_ep->pkt_per_frm; ++j) { ++ data_per_desc = ++ ((j + 1) * dwc_ep->maxpacket > ++ dwc_ep-> ++ data_per_frame) ? dwc_ep->data_per_frame - ++ j * dwc_ep->maxpacket : dwc_ep->maxpacket; ++ data_per_desc += ++ (data_per_desc % 4) ? (4 - ++ data_per_desc % ++ 4) : 0; ++ sts.b_iso_out.rxbytes = data_per_desc; ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ ++ dma_ad += data_per_desc; ++ dma_desc++; ++ } ++ } ++ ++ for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) { ++ ++ data_per_desc = ++ ((j + 1) * dwc_ep->maxpacket > ++ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame - ++ j * dwc_ep->maxpacket : dwc_ep->maxpacket; ++ data_per_desc += ++ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0; ++ sts.b_iso_out.rxbytes = data_per_desc; ++ ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ ++ dma_desc++; ++ dma_ad += data_per_desc; ++ } ++ ++ sts.b_iso_out.ioc = 1; ++ sts.b_iso_out.l = dwc_ep->proc_buf_num; ++ ++ data_per_desc = ++ ((j + 1) * dwc_ep->maxpacket > ++ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame - ++ j * dwc_ep->maxpacket : dwc_ep->maxpacket; ++ data_per_desc += ++ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0; ++ sts.b_iso_out.rxbytes = data_per_desc; ++ ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ } else { ++/** ISO IN EP */ ++ ++ dma_desc = ++ dwc_ep->iso_desc_addr + ++ dwc_ep->desc_cnt * dwc_ep->proc_buf_num; ++ ++ sts.b_iso_in.bs = BS_HOST_READY; ++ sts.b_iso_in.txsts = 0; ++ sts.b_iso_in.sp = 0; ++ sts.b_iso_in.ioc = 0; ++ sts.b_iso_in.pid = dwc_ep->pkt_per_frm; ++ sts.b_iso_in.framenum = dwc_ep->next_frame; ++ sts.b_iso_in.txbytes = dwc_ep->data_per_frame; ++ sts.b_iso_in.l = 0; ++ ++ for (i = 0; i < dwc_ep->desc_cnt - 1; i++) { ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ ++ sts.b_iso_in.framenum += dwc_ep->bInterval; ++ dma_ad += dwc_ep->data_per_frame; ++ dma_desc++; ++ } ++ ++ sts.b_iso_in.ioc = 1; ++ sts.b_iso_in.l = dwc_ep->proc_buf_num; ++ ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ ++ dwc_ep->next_frame = ++ sts.b_iso_in.framenum + dwc_ep->bInterval * 1; ++ } ++ dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1; ++} ++ ++/** ++ * This function is to handle Iso EP transfer complete interrupt ++ * in case Iso out packet was dropped ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param dwc_ep The EP for wihich transfer complete was asserted ++ * ++ */ ++static uint32_t handle_iso_out_pkt_dropped(dwc_otg_core_if_t * core_if, ++ dwc_ep_t * dwc_ep) ++{ ++ uint32_t dma_addr; ++ uint32_t drp_pkt; ++ uint32_t drp_pkt_cnt; ++ deptsiz_data_t deptsiz = {.d32 = 0 }; ++ depctl_data_t depctl = {.d32 = 0 }; ++ int i; ++ ++ deptsiz.d32 = ++ DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[dwc_ep->num]->doeptsiz); ++ ++ drp_pkt = dwc_ep->pkt_cnt - deptsiz.b.pktcnt; ++ drp_pkt_cnt = dwc_ep->pkt_per_frm - (drp_pkt % dwc_ep->pkt_per_frm); ++ ++ /* Setting dropped packets status */ ++ for (i = 0; i < drp_pkt_cnt; ++i) { ++ dwc_ep->pkt_info[drp_pkt].status = -DWC_E_NO_DATA; ++ drp_pkt++; ++ deptsiz.b.pktcnt--; ++ } ++ ++ if (deptsiz.b.pktcnt > 0) { ++ deptsiz.b.xfersize = ++ dwc_ep->xfer_len - (dwc_ep->pkt_cnt - ++ deptsiz.b.pktcnt) * dwc_ep->maxpacket; ++ } else { ++ deptsiz.b.xfersize = 0; ++ deptsiz.b.pktcnt = 0; ++ } ++ ++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz, ++ deptsiz.d32); ++ ++ if (deptsiz.b.pktcnt > 0) { ++ if (dwc_ep->proc_buf_num) { ++ dma_addr = ++ dwc_ep->dma_addr1 + dwc_ep->xfer_len - ++ deptsiz.b.xfersize; ++ } else { ++ dma_addr = ++ dwc_ep->dma_addr0 + dwc_ep->xfer_len - ++ deptsiz.b.xfersize;; ++ } ++ ++ DWC_WRITE_REG32(&core_if->dev_if-> ++ out_ep_regs[dwc_ep->num]->doepdma, dma_addr); ++ ++ /** Re-enable endpoint, clear nak */ ++ depctl.d32 = 0; ++ depctl.b.epena = 1; ++ depctl.b.cnak = 1; ++ ++ DWC_MODIFY_REG32(&core_if->dev_if-> ++ out_ep_regs[dwc_ep->num]->doepctl, depctl.d32, ++ depctl.d32); ++ return 0; ++ } else { ++ return 1; ++ } ++} ++ ++/** ++ * This function sets iso packets information(PTI mode) ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to start the transfer on. ++ * ++ */ ++static uint32_t set_iso_pkts_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ int i, j; ++ dma_addr_t dma_ad; ++ iso_pkt_info_t *packet_info = ep->pkt_info; ++ uint32_t offset; ++ uint32_t frame_data; ++ deptsiz_data_t deptsiz; ++ ++ if (ep->proc_buf_num == 0) { ++ /** Buffer 0 descriptors setup */ ++ dma_ad = ep->dma_addr0; ++ } else { ++ /** Buffer 1 descriptors setup */ ++ dma_ad = ep->dma_addr1; ++ } ++ ++ if (ep->is_in) { ++ deptsiz.d32 = ++ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]-> ++ dieptsiz); ++ } else { ++ deptsiz.d32 = ++ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[ep->num]-> ++ doeptsiz); ++ } ++ ++ if (!deptsiz.b.xfersize) { ++ offset = 0; ++ for (i = 0; i < ep->pkt_cnt; i += ep->pkt_per_frm) { ++ frame_data = ep->data_per_frame; ++ for (j = 0; j < ep->pkt_per_frm; ++j) { ++ ++ /* Packet status - is not set as initially ++ * it is set to 0 and if packet was sent ++ successfully, status field will remain 0*/ ++ ++ /* Bytes has been transfered */ ++ packet_info->length = ++ (ep->maxpacket < ++ frame_data) ? ep->maxpacket : frame_data; ++ ++ /* Received packet offset */ ++ packet_info->offset = offset; ++ offset += packet_info->length; ++ frame_data -= packet_info->length; ++ ++ packet_info++; ++ } ++ } ++ return 1; ++ } else { ++ /* This is a workaround for in case of Transfer Complete with ++ * PktDrpSts interrupts merging - in this case Transfer complete ++ * interrupt for Isoc Out Endpoint is asserted without PktDrpSts ++ * set and with DOEPTSIZ register non zero. Investigations showed, ++ * that this happens when Out packet is dropped, but because of ++ * interrupts merging during first interrupt handling PktDrpSts ++ * bit is cleared and for next merged interrupts it is not reset. ++ * In this case SW hadles the interrupt as if PktDrpSts bit is set. ++ */ ++ if (ep->is_in) { ++ return 1; ++ } else { ++ return handle_iso_out_pkt_dropped(core_if, ep); ++ } ++ } ++} ++ ++/** ++ * This function is to handle Iso EP transfer complete interrupt ++ * ++ * @param pcd The PCD ++ * @param ep The EP for which transfer complete was asserted ++ * ++ */ ++static void complete_iso_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd); ++ dwc_ep_t *dwc_ep = &ep->dwc_ep; ++ uint8_t is_last = 0; ++ ++ if (ep->dwc_ep.next_frame == 0xffffffff) { ++ DWC_WARN("Next frame is not set!\n"); ++ return; ++ } ++ ++ if (core_if->dma_enable) { ++ if (core_if->dma_desc_enable) { ++ set_ddma_iso_pkts_info(core_if, dwc_ep); ++ reinit_ddma_iso_xfer(core_if, dwc_ep); ++ is_last = 1; ++ } else { ++ if (core_if->pti_enh_enable) { ++ if (set_iso_pkts_info(core_if, dwc_ep)) { ++ dwc_ep->proc_buf_num = ++ (dwc_ep->proc_buf_num ^ 1) & 0x1; ++ dwc_otg_iso_ep_start_buf_transfer ++ (core_if, dwc_ep); ++ is_last = 1; ++ } ++ } else { ++ set_current_pkt_info(core_if, dwc_ep); ++ if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) { ++ is_last = 1; ++ dwc_ep->cur_pkt = 0; ++ dwc_ep->proc_buf_num = ++ (dwc_ep->proc_buf_num ^ 1) & 0x1; ++ if (dwc_ep->proc_buf_num) { ++ dwc_ep->cur_pkt_addr = ++ dwc_ep->xfer_buff1; ++ dwc_ep->cur_pkt_dma_addr = ++ dwc_ep->dma_addr1; ++ } else { ++ dwc_ep->cur_pkt_addr = ++ dwc_ep->xfer_buff0; ++ dwc_ep->cur_pkt_dma_addr = ++ dwc_ep->dma_addr0; ++ } ++ ++ } ++ dwc_otg_iso_ep_start_frm_transfer(core_if, ++ dwc_ep); ++ } ++ } ++ } else { ++ set_current_pkt_info(core_if, dwc_ep); ++ if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) { ++ is_last = 1; ++ dwc_ep->cur_pkt = 0; ++ dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1; ++ if (dwc_ep->proc_buf_num) { ++ dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1; ++ dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1; ++ } else { ++ dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0; ++ dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0; ++ } ++ ++ } ++ dwc_otg_iso_ep_start_frm_transfer(core_if, dwc_ep); ++ } ++ if (is_last) ++ dwc_otg_iso_buffer_done(pcd, ep, ep->iso_req_handle); ++} ++#endif /* DWC_EN_ISOC */ ++ ++/** ++ * This function handle BNA interrupt for Non Isochronous EPs ++ * ++ */ ++static void dwc_otg_pcd_handle_noniso_bna(dwc_otg_pcd_ep_t * ep) ++{ ++ dwc_ep_t *dwc_ep = &ep->dwc_ep; ++ volatile uint32_t *addr; ++ depctl_data_t depctl = {.d32 = 0 }; ++ dwc_otg_pcd_t *pcd = ep->pcd; ++ dwc_otg_dev_dma_desc_t *dma_desc; ++ dev_dma_desc_sts_t sts = {.d32 = 0 }; ++ dwc_otg_core_if_t *core_if = ep->pcd->core_if; ++ int i, start; ++ ++ if (!dwc_ep->desc_cnt) ++ DWC_WARN("Ep%d %s Descriptor count = %d \n", dwc_ep->num, ++ (dwc_ep->is_in ? "IN" : "OUT"), dwc_ep->desc_cnt); ++ ++ if (core_if->core_params->cont_on_bna && !dwc_ep->is_in ++ && dwc_ep->type != DWC_OTG_EP_TYPE_CONTROL) { ++ uint32_t doepdma; ++ dwc_otg_dev_out_ep_regs_t *out_regs = ++ core_if->dev_if->out_ep_regs[dwc_ep->num]; ++ doepdma = DWC_READ_REG32(&(out_regs->doepdma)); ++ start = (doepdma - dwc_ep->dma_desc_addr)/sizeof(dwc_otg_dev_dma_desc_t); ++ dma_desc = &(dwc_ep->desc_addr[start]); ++ } else { ++ start = 0; ++ dma_desc = dwc_ep->desc_addr; ++ } ++ ++ ++ for (i = start; i < dwc_ep->desc_cnt; ++i, ++dma_desc) { ++ sts.d32 = dma_desc->status.d32; ++ sts.b.bs = BS_HOST_READY; ++ dma_desc->status.d32 = sts.d32; ++ } ++ ++ if (dwc_ep->is_in == 0) { ++ addr = ++ &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->num]-> ++ doepctl; ++ } else { ++ addr = ++ &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl; ++ } ++ depctl.b.epena = 1; ++ depctl.b.cnak = 1; ++ DWC_MODIFY_REG32(addr, 0, depctl.d32); ++} ++ ++/** ++ * This function handles EP0 Control transfers. ++ * ++ * The state of the control transfers are tracked in ++ * ep0state. ++ */ ++static void handle_ep0(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; ++ dev_dma_desc_sts_t desc_sts; ++ deptsiz0_data_t deptsiz; ++ uint32_t byte_count; ++ ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__); ++ print_ep0_state(pcd); ++#endif ++ ++// DWC_PRINTF("HANDLE EP0\n"); ++ ++ switch (pcd->ep0state) { ++ case EP0_DISCONNECT: ++ break; ++ ++ case EP0_IDLE: ++ pcd->request_config = 0; ++ ++ pcd_setup(pcd); ++ break; ++ ++ case EP0_IN_DATA_PHASE: ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCD, "DATA_IN EP%d-%s: type=%d, mps=%d\n", ++ ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"), ++ ep0->dwc_ep.type, ep0->dwc_ep.maxpacket); ++#endif ++ ++ if (core_if->dma_enable != 0) { ++ /* ++ * For EP0 we can only program 1 packet at a time so we ++ * need to do the make calculations after each complete. ++ * Call write_packet to make the calculations, as in ++ * slave mode, and use those values to determine if we ++ * can complete. ++ */ ++ if (core_if->dma_desc_enable == 0) { ++ deptsiz.d32 = ++ DWC_READ_REG32(&core_if-> ++ dev_if->in_ep_regs[0]-> ++ dieptsiz); ++ byte_count = ++ ep0->dwc_ep.xfer_len - deptsiz.b.xfersize; ++ } else { ++ desc_sts = ++ core_if->dev_if->in_desc_addr->status; ++ byte_count = ++ ep0->dwc_ep.xfer_len - desc_sts.b.bytes; ++ } ++ ep0->dwc_ep.xfer_count += byte_count; ++ ep0->dwc_ep.xfer_buff += byte_count; ++ ep0->dwc_ep.dma_addr += byte_count; ++ } ++ if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) { ++ dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd), ++ &ep0->dwc_ep); ++ DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n"); ++ } else if (ep0->dwc_ep.sent_zlp) { ++ dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd), ++ &ep0->dwc_ep); ++ ep0->dwc_ep.sent_zlp = 0; ++ DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER sent zlp\n"); ++ } else { ++ ep0_complete_request(ep0); ++ DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n"); ++ } ++ break; ++ case EP0_OUT_DATA_PHASE: ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCD, "DATA_OUT EP%d-%s: type=%d, mps=%d\n", ++ ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"), ++ ep0->dwc_ep.type, ep0->dwc_ep.maxpacket); ++#endif ++ if (core_if->dma_enable != 0) { ++ if (core_if->dma_desc_enable == 0) { ++ deptsiz.d32 = ++ DWC_READ_REG32(&core_if-> ++ dev_if->out_ep_regs[0]-> ++ doeptsiz); ++ byte_count = ++ ep0->dwc_ep.maxpacket - deptsiz.b.xfersize; ++ } else { ++ desc_sts = ++ core_if->dev_if->out_desc_addr->status; ++ byte_count = ++ ep0->dwc_ep.maxpacket - desc_sts.b.bytes; ++ } ++ ep0->dwc_ep.xfer_count += byte_count; ++ ep0->dwc_ep.xfer_buff += byte_count; ++ ep0->dwc_ep.dma_addr += byte_count; ++ } ++ if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) { ++ dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd), ++ &ep0->dwc_ep); ++ DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n"); ++ } else if (ep0->dwc_ep.sent_zlp) { ++ dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd), ++ &ep0->dwc_ep); ++ ep0->dwc_ep.sent_zlp = 0; ++ DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER sent zlp\n"); ++ } else { ++ ep0_complete_request(ep0); ++ DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n"); ++ } ++ break; ++ ++ case EP0_IN_STATUS_PHASE: ++ case EP0_OUT_STATUS_PHASE: ++ DWC_DEBUGPL(DBG_PCD, "CASE: EP0_STATUS\n"); ++ ep0_complete_request(ep0); ++ pcd->ep0state = EP0_IDLE; ++ ep0->stopped = 1; ++ ep0->dwc_ep.is_in = 0; /* OUT for next SETUP */ ++ ++ /* Prepare for more SETUP Packets */ ++ if (core_if->dma_enable) { ++ ep0_out_start(core_if, pcd); ++ } ++ break; ++ ++ case EP0_STALL: ++ DWC_ERROR("EP0 STALLed, should not get here pcd_setup()\n"); ++ break; ++ } ++#ifdef DEBUG_EP0 ++ print_ep0_state(pcd); ++#endif ++} ++ ++/** ++ * Restart transfer ++ */ ++static void restart_transfer(dwc_otg_pcd_t * pcd, const uint32_t epnum) ++{ ++ dwc_otg_core_if_t *core_if; ++ dwc_otg_dev_if_t *dev_if; ++ deptsiz_data_t dieptsiz = {.d32 = 0 }; ++ dwc_otg_pcd_ep_t *ep; ++ ++ ep = get_in_ep(pcd, epnum); ++ ++#ifdef DWC_EN_ISOC ++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) { ++ return; ++ } ++#endif /* DWC_EN_ISOC */ ++ ++ core_if = GET_CORE_IF(pcd); ++ dev_if = core_if->dev_if; ++ ++ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dieptsiz); ++ ++ DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x xfer_len=%0x" ++ " stopped=%d\n", ep->dwc_ep.xfer_buff, ++ ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len, ep->stopped); ++ /* ++ * If xfersize is 0 and pktcnt in not 0, resend the last packet. ++ */ ++ if (dieptsiz.b.pktcnt && dieptsiz.b.xfersize == 0 && ++ ep->dwc_ep.start_xfer_buff != 0) { ++ if (ep->dwc_ep.total_len <= ep->dwc_ep.maxpacket) { ++ ep->dwc_ep.xfer_count = 0; ++ ep->dwc_ep.xfer_buff = ep->dwc_ep.start_xfer_buff; ++ ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count; ++ } else { ++ ep->dwc_ep.xfer_count -= ep->dwc_ep.maxpacket; ++ /* convert packet size to dwords. */ ++ ep->dwc_ep.xfer_buff -= ep->dwc_ep.maxpacket; ++ ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count; ++ } ++ ep->stopped = 0; ++ DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x " ++ "xfer_len=%0x stopped=%d\n", ++ ep->dwc_ep.xfer_buff, ++ ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len, ++ ep->stopped); ++ if (epnum == 0) { ++ dwc_otg_ep0_start_transfer(core_if, &ep->dwc_ep); ++ } else { ++ dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep); ++ } ++ } ++} ++ ++/* ++ * This function create new nextep sequnce based on Learn Queue. ++ * ++ * @param core_if Programming view of DWC_otg controller ++ */ ++void predict_nextep_seq( dwc_otg_core_if_t * core_if) ++{ ++ dwc_otg_device_global_regs_t *dev_global_regs = ++ core_if->dev_if->dev_global_regs; ++ const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth; ++ /* Number of Token Queue Registers */ ++ const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8; ++ dtknq1_data_t dtknqr1; ++ uint32_t in_tkn_epnums[4]; ++ uint8_t seqnum[MAX_EPS_CHANNELS]; ++ uint8_t intkn_seq[TOKEN_Q_DEPTH]; ++ grstctl_t resetctl = {.d32 = 0 }; ++ uint8_t temp; ++ int ndx = 0; ++ int start = 0; ++ int end = 0; ++ int sort_done = 0; ++ int i = 0; ++ volatile uint32_t *addr = &dev_global_regs->dtknqr1; ++ ++ ++ DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH); ++ ++ /* Read the DTKNQ Registers */ ++ for (i = 0; i < DTKNQ_REG_CNT; i++) { ++ in_tkn_epnums[i] = DWC_READ_REG32(addr); ++ DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i + 1, ++ in_tkn_epnums[i]); ++ if (addr == &dev_global_regs->dvbusdis) { ++ addr = &dev_global_regs->dtknqr3_dthrctl; ++ } else { ++ ++addr; ++ } ++ ++ } ++ ++ /* Copy the DTKNQR1 data to the bit field. */ ++ dtknqr1.d32 = in_tkn_epnums[0]; ++ if (dtknqr1.b.wrap_bit) { ++ ndx = dtknqr1.b.intknwptr; ++ end = ndx -1; ++ if (end < 0) ++ end = TOKEN_Q_DEPTH -1; ++ } else { ++ ndx = 0; ++ end = dtknqr1.b.intknwptr -1; ++ if (end < 0) ++ end = 0; ++ } ++ start = ndx; ++ ++ /* Fill seqnum[] by initial values: EP number + 31 */ ++ for (i=0; i <= core_if->dev_if->num_in_eps; i++) { ++ seqnum[i] = i +31; ++ } ++ ++ /* Fill intkn_seq[] from in_tkn_epnums[0] */ ++ for (i=0; i < 6; i++) ++ intkn_seq[i] = (in_tkn_epnums[0] >> ((7-i) * 4)) & 0xf; ++ ++ if (TOKEN_Q_DEPTH > 6) { ++ /* Fill intkn_seq[] from in_tkn_epnums[1] */ ++ for (i=6; i < 14; i++) ++ intkn_seq[i] = ++ (in_tkn_epnums[1] >> ((7 - (i - 6)) * 4)) & 0xf; ++ } ++ ++ if (TOKEN_Q_DEPTH > 14) { ++ /* Fill intkn_seq[] from in_tkn_epnums[1] */ ++ for (i=14; i < 22; i++) ++ intkn_seq[i] = ++ (in_tkn_epnums[2] >> ((7 - (i - 14)) * 4)) & 0xf; ++ } ++ ++ if (TOKEN_Q_DEPTH > 22) { ++ /* Fill intkn_seq[] from in_tkn_epnums[1] */ ++ for (i=22; i < 30; i++) ++ intkn_seq[i] = ++ (in_tkn_epnums[3] >> ((7 - (i - 22)) * 4)) & 0xf; ++ } ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s start=%d end=%d intkn_seq[]:\n", __func__, ++ start, end); ++ for (i=0; idev_if->num_in_eps; i++) { ++ if (core_if->nextep_seq[i] == 0xff ) ++ seqnum[i] = 0xff; ++ } ++ ++ /* Sort seqnum[] */ ++ sort_done = 0; ++ while (!sort_done) { ++ sort_done = 1; ++ for (i=0; idev_if->num_in_eps; i++) { ++ if (seqnum[i] > seqnum[i+1]) { ++ temp = seqnum[i]; ++ seqnum[i] = seqnum[i+1]; ++ seqnum[i+1] = temp; ++ sort_done = 0; ++ } ++ } ++ } ++ ++ ndx = start + seqnum[0]; ++ if (ndx >= TOKEN_Q_DEPTH) ++ ndx = ndx % TOKEN_Q_DEPTH; ++ core_if->first_in_nextep_seq = intkn_seq[ndx]; ++ ++ /* Update seqnum[] by EP numbers */ ++ for (i=0; i<=core_if->dev_if->num_in_eps; i++) { ++ ndx = start + i; ++ if (seqnum[i] < 31) { ++ ndx = start + seqnum[i]; ++ if (ndx >= TOKEN_Q_DEPTH) ++ ndx = ndx % TOKEN_Q_DEPTH; ++ seqnum[i] = intkn_seq[ndx]; ++ } else { ++ if (seqnum[i] < 0xff) { ++ seqnum[i] = seqnum[i] - 31; ++ } else { ++ break; ++ } ++ } ++ } ++ ++ /* Update nextep_seq[] based on seqnum[] */ ++ for (i=0; idev_if->num_in_eps; i++) { ++ if (seqnum[i] != 0xff) { ++ if (seqnum[i+1] != 0xff) { ++ core_if->nextep_seq[seqnum[i]] = seqnum[i+1]; ++ } else { ++ core_if->nextep_seq[seqnum[i]] = core_if->first_in_nextep_seq; ++ break; ++ } ++ } else { ++ break; ++ } ++ } ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s first_in_nextep_seq= %2d; nextep_seq[]:\n", ++ __func__, core_if->first_in_nextep_seq); ++ for (i=0; i <= core_if->dev_if->num_in_eps; i++) { ++ DWC_DEBUGPL(DBG_PCDV,"%2d\n", core_if->nextep_seq[i]); ++ } ++ ++ /* Flush the Learning Queue */ ++ resetctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->grstctl); ++ resetctl.b.intknqflsh = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32); ++ ++ ++} ++ ++/** ++ * handle the IN EP disable interrupt. ++ */ ++static inline void handle_in_ep_disable_intr(dwc_otg_pcd_t * pcd, ++ const uint32_t epnum) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ deptsiz_data_t dieptsiz = {.d32 = 0 }; ++ dctl_data_t dctl = {.d32 = 0 }; ++ dwc_otg_pcd_ep_t *ep; ++ dwc_ep_t *dwc_ep; ++ gintmsk_data_t gintmsk_data; ++ depctl_data_t depctl; ++ uint32_t diepdma; ++ uint32_t remain_to_transfer = 0; ++ uint8_t i; ++ uint32_t xfer_size; ++ ++ ep = get_in_ep(pcd, epnum); ++ dwc_ep = &ep->dwc_ep; ++ ++ if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num); ++ complete_ep(ep); ++ return; ++ } ++ ++ DWC_DEBUGPL(DBG_PCD, "diepctl%d=%0x\n", epnum, ++ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl)); ++ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dieptsiz); ++ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl); ++ ++ DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n", ++ dieptsiz.b.pktcnt, dieptsiz.b.xfersize); ++ ++ if ((core_if->start_predict == 0) || (depctl.b.eptype & 1)) { ++ if (ep->stopped) { ++ if (core_if->en_multiple_tx_fifo) ++ /* Flush the Tx FIFO */ ++ dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num); ++ /* Clear the Global IN NP NAK */ ++ dctl.d32 = 0; ++ dctl.b.cgnpinnak = 1; ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); ++ /* Restart the transaction */ ++ if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) { ++ restart_transfer(pcd, epnum); ++ } ++ } else { ++ /* Restart the transaction */ ++ if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) { ++ restart_transfer(pcd, epnum); ++ } ++ DWC_DEBUGPL(DBG_ANY, "STOPPED!!!\n"); ++ } ++ return; ++ } ++ ++ if (core_if->start_predict > 2) { // NP IN EP ++ core_if->start_predict--; ++ return; ++ } ++ ++ core_if->start_predict--; ++ ++ if (core_if->start_predict == 1) { // All NP IN Ep's disabled now ++ ++ predict_nextep_seq(core_if); ++ ++ /* Update all active IN EP's NextEP field based of nextep_seq[] */ ++ for ( i = 0; i <= core_if->dev_if->num_in_eps; i++) { ++ depctl.d32 = ++ DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); ++ if (core_if->nextep_seq[i] != 0xff) { // Active NP IN EP ++ depctl.b.nextep = core_if->nextep_seq[i]; ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32); ++ } ++ } ++ /* Flush Shared NP TxFIFO */ ++ dwc_otg_flush_tx_fifo(core_if, 0); ++ /* Rewind buffers */ ++ if (!core_if->dma_desc_enable) { ++ i = core_if->first_in_nextep_seq; ++ do { ++ ep = get_in_ep(pcd, i); ++ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz); ++ xfer_size = ep->dwc_ep.total_len - ep->dwc_ep.xfer_count; ++ if (xfer_size > ep->dwc_ep.maxxfer) ++ xfer_size = ep->dwc_ep.maxxfer; ++ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); ++ if (dieptsiz.b.pktcnt != 0) { ++ if (xfer_size == 0) { ++ remain_to_transfer = 0; ++ } else { ++ if ((xfer_size % ep->dwc_ep.maxpacket) == 0) { ++ remain_to_transfer = ++ dieptsiz.b.pktcnt * ep->dwc_ep.maxpacket; ++ } else { ++ remain_to_transfer = ((dieptsiz.b.pktcnt -1) * ep->dwc_ep.maxpacket) ++ + (xfer_size % ep->dwc_ep.maxpacket); ++ } ++ } ++ diepdma = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepdma); ++ dieptsiz.b.xfersize = remain_to_transfer; ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, dieptsiz.d32); ++ diepdma = ep->dwc_ep.dma_addr + (xfer_size - remain_to_transfer); ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, diepdma); ++ } ++ i = core_if->nextep_seq[i]; ++ } while (i != core_if->first_in_nextep_seq); ++ } else { // dma_desc_enable ++ DWC_PRINTF("%s Learning Queue not supported in DDMA\n", __func__); ++ } ++ ++ /* Restart transfers in predicted sequences */ ++ i = core_if->first_in_nextep_seq; ++ do { ++ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz); ++ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); ++ if (dieptsiz.b.pktcnt != 0) { ++ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); ++ depctl.b.epena = 1; ++ depctl.b.cnak = 1; ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32); ++ } ++ i = core_if->nextep_seq[i]; ++ } while (i != core_if->first_in_nextep_seq); ++ ++ /* Clear the global non-periodic IN NAK handshake */ ++ dctl.d32 = 0; ++ dctl.b.cgnpinnak = 1; ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); ++ ++ /* Unmask EP Mismatch interrupt */ ++ gintmsk_data.d32 = 0; ++ gintmsk_data.b.epmismatch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, gintmsk_data.d32); ++ ++ core_if->start_predict = 0; ++ ++ } ++} ++ ++/** ++ * Handler for the IN EP timeout handshake interrupt. ++ */ ++static inline void handle_in_ep_timeout_intr(dwc_otg_pcd_t * pcd, ++ const uint32_t epnum) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ ++#ifdef DEBUG ++ deptsiz_data_t dieptsiz = {.d32 = 0 }; ++ uint32_t num = 0; ++#endif ++ dctl_data_t dctl = {.d32 = 0 }; ++ dwc_otg_pcd_ep_t *ep; ++ ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ ep = get_in_ep(pcd, epnum); ++ ++ /* Disable the NP Tx Fifo Empty Interrrupt */ ++ if (!core_if->dma_enable) { ++ intr_mask.b.nptxfempty = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, ++ intr_mask.d32, 0); ++ } ++ /** @todo NGS Check EP type. ++ * Implement for Periodic EPs */ ++ /* ++ * Non-periodic EP ++ */ ++ /* Enable the Global IN NAK Effective Interrupt */ ++ intr_mask.b.ginnakeff = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32); ++ ++ /* Set Global IN NAK */ ++ dctl.b.sgnpinnak = 1; ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); ++ ++ ep->stopped = 1; ++ ++#ifdef DEBUG ++ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[num]->dieptsiz); ++ DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n", ++ dieptsiz.b.pktcnt, dieptsiz.b.xfersize); ++#endif ++ ++#ifdef DISABLE_PERIODIC_EP ++ /* ++ * Set the NAK bit for this EP to ++ * start the disable process. ++ */ ++ diepctl.d32 = 0; ++ diepctl.b.snak = 1; ++ DWC_MODIFY_REG32(&dev_if->in_ep_regs[num]->diepctl, diepctl.d32, ++ diepctl.d32); ++ ep->disabling = 1; ++ ep->stopped = 1; ++#endif ++} ++ ++/** ++ * Handler for the IN EP NAK interrupt. ++ */ ++static inline int32_t handle_in_ep_nak_intr(dwc_otg_pcd_t * pcd, ++ const uint32_t epnum) ++{ ++ /** @todo implement ISR */ ++ dwc_otg_core_if_t *core_if; ++ diepmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "IN EP NAK"); ++ core_if = GET_CORE_IF(pcd); ++ intr_mask.b.nak = 1; ++ ++ if (core_if->multiproc_int_enable) { ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> ++ diepeachintmsk[epnum], intr_mask.d32, 0); ++ } else { ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->diepmsk, ++ intr_mask.d32, 0); ++ } ++ ++ return 1; ++} ++ ++/** ++ * Handler for the OUT EP Babble interrupt. ++ */ ++static inline int32_t handle_out_ep_babble_intr(dwc_otg_pcd_t * pcd, ++ const uint32_t epnum) ++{ ++ /** @todo implement ISR */ ++ dwc_otg_core_if_t *core_if; ++ doepmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", ++ "OUT EP Babble"); ++ core_if = GET_CORE_IF(pcd); ++ intr_mask.b.babble = 1; ++ ++ if (core_if->multiproc_int_enable) { ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> ++ doepeachintmsk[epnum], intr_mask.d32, 0); ++ } else { ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk, ++ intr_mask.d32, 0); ++ } ++ ++ return 1; ++} ++ ++/** ++ * Handler for the OUT EP NAK interrupt. ++ */ ++static inline int32_t handle_out_ep_nak_intr(dwc_otg_pcd_t * pcd, ++ const uint32_t epnum) ++{ ++ /** @todo implement ISR */ ++ dwc_otg_core_if_t *core_if; ++ doepmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ DWC_DEBUGPL(DBG_ANY, "INTERRUPT Handler not implemented for %s\n", "OUT EP NAK"); ++ core_if = GET_CORE_IF(pcd); ++ intr_mask.b.nak = 1; ++ ++ if (core_if->multiproc_int_enable) { ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> ++ doepeachintmsk[epnum], intr_mask.d32, 0); ++ } else { ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk, ++ intr_mask.d32, 0); ++ } ++ ++ return 1; ++} ++ ++/** ++ * Handler for the OUT EP NYET interrupt. ++ */ ++static inline int32_t handle_out_ep_nyet_intr(dwc_otg_pcd_t * pcd, ++ const uint32_t epnum) ++{ ++ /** @todo implement ISR */ ++ dwc_otg_core_if_t *core_if; ++ doepmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "OUT EP NYET"); ++ core_if = GET_CORE_IF(pcd); ++ intr_mask.b.nyet = 1; ++ ++ if (core_if->multiproc_int_enable) { ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> ++ doepeachintmsk[epnum], intr_mask.d32, 0); ++ } else { ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk, ++ intr_mask.d32, 0); ++ } ++ ++ return 1; ++} ++ ++/** ++ * This interrupt indicates that an IN EP has a pending Interrupt. ++ * The sequence for handling the IN EP interrupt is shown below: ++ * -# Read the Device All Endpoint Interrupt register ++ * -# Repeat the following for each IN EP interrupt bit set (from ++ * LSB to MSB). ++ * -# Read the Device Endpoint Interrupt (DIEPINTn) register ++ * -# If "Transfer Complete" call the request complete function ++ * -# If "Endpoint Disabled" complete the EP disable procedure. ++ * -# If "AHB Error Interrupt" log error ++ * -# If "Time-out Handshake" log error ++ * -# If "IN Token Received when TxFIFO Empty" write packet to Tx ++ * FIFO. ++ * -# If "IN Token EP Mismatch" (disable, this is handled by EP ++ * Mismatch Interrupt) ++ */ ++static int32_t dwc_otg_pcd_handle_in_ep_intr(dwc_otg_pcd_t * pcd) ++{ ++#define CLEAR_IN_EP_INTR(__core_if,__epnum,__intr) \ ++do { \ ++ diepint_data_t diepint = {.d32=0}; \ ++ diepint.b.__intr = 1; \ ++ DWC_WRITE_REG32(&__core_if->dev_if->in_ep_regs[__epnum]->diepint, \ ++ diepint.d32); \ ++} while (0) ++ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ diepint_data_t diepint = {.d32 = 0 }; ++ depctl_data_t depctl = {.d32 = 0 }; ++ uint32_t ep_intr; ++ uint32_t epnum = 0; ++ dwc_otg_pcd_ep_t *ep; ++ dwc_ep_t *dwc_ep; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, pcd); ++ ++ /* Read in the device interrupt bits */ ++ ep_intr = dwc_otg_read_dev_all_in_ep_intr(core_if); ++ ++ /* Service the Device IN interrupts for each endpoint */ ++ while (ep_intr) { ++ if (ep_intr & 0x1) { ++ uint32_t empty_msk; ++ /* Get EP pointer */ ++ ep = get_in_ep(pcd, epnum); ++ dwc_ep = &ep->dwc_ep; ++ ++ depctl.d32 = ++ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl); ++ empty_msk = ++ DWC_READ_REG32(&dev_if-> ++ dev_global_regs->dtknqr4_fifoemptymsk); ++ ++ DWC_DEBUGPL(DBG_PCDV, ++ "IN EP INTERRUPT - %d\nepmty_msk - %8x diepctl - %8x\n", ++ epnum, empty_msk, depctl.d32); ++ ++ DWC_DEBUGPL(DBG_PCD, ++ "EP%d-%s: type=%d, mps=%d\n", ++ dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"), ++ dwc_ep->type, dwc_ep->maxpacket); ++ ++ diepint.d32 = ++ dwc_otg_read_dev_in_ep_intr(core_if, dwc_ep); ++ ++ DWC_DEBUGPL(DBG_PCDV, ++ "EP %d Interrupt Register - 0x%x\n", epnum, ++ diepint.d32); ++ /* Transfer complete */ ++ if (diepint.b.xfercompl) { ++ /* Disable the NP Tx FIFO Empty ++ * Interrupt */ ++ if (core_if->en_multiple_tx_fifo == 0) { ++ intr_mask.b.nptxfempty = 1; ++ DWC_MODIFY_REG32 ++ (&core_if->core_global_regs->gintmsk, ++ intr_mask.d32, 0); ++ } else { ++ /* Disable the Tx FIFO Empty Interrupt for this EP */ ++ uint32_t fifoemptymsk = ++ 0x1 << dwc_ep->num; ++ DWC_MODIFY_REG32(&core_if-> ++ dev_if->dev_global_regs->dtknqr4_fifoemptymsk, ++ fifoemptymsk, 0); ++ } ++ /* Clear the bit in DIEPINTn for this interrupt */ ++ CLEAR_IN_EP_INTR(core_if, epnum, xfercompl); ++ ++ /* Complete the transfer */ ++ if (epnum == 0) { ++ handle_ep0(pcd); ++ } ++#ifdef DWC_EN_ISOC ++ else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ if (!ep->stopped) ++ complete_iso_ep(pcd, ep); ++ } ++#endif /* DWC_EN_ISOC */ ++#ifdef DWC_UTE_PER_IO ++ else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ if (!ep->stopped) ++ complete_xiso_ep(ep); ++ } ++#endif /* DWC_UTE_PER_IO */ ++ else { ++ if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC && ++ dwc_ep->bInterval > 1) { ++ dwc_ep->frame_num += dwc_ep->bInterval; ++ if (dwc_ep->frame_num > 0x3FFF) ++ { ++ dwc_ep->frm_overrun = 1; ++ dwc_ep->frame_num &= 0x3FFF; ++ } else ++ dwc_ep->frm_overrun = 0; ++ } ++ complete_ep(ep); ++ if(diepint.b.nak) ++ CLEAR_IN_EP_INTR(core_if, epnum, nak); ++ } ++ } ++ /* Endpoint disable */ ++ if (diepint.b.epdisabled) { ++ DWC_DEBUGPL(DBG_ANY, "EP%d IN disabled\n", ++ epnum); ++ handle_in_ep_disable_intr(pcd, epnum); ++ ++ /* Clear the bit in DIEPINTn for this interrupt */ ++ CLEAR_IN_EP_INTR(core_if, epnum, epdisabled); ++ } ++ /* AHB Error */ ++ if (diepint.b.ahberr) { ++ DWC_ERROR("EP%d IN AHB Error\n", epnum); ++ /* Clear the bit in DIEPINTn for this interrupt */ ++ CLEAR_IN_EP_INTR(core_if, epnum, ahberr); ++ } ++ /* TimeOUT Handshake (non-ISOC IN EPs) */ ++ if (diepint.b.timeout) { ++ DWC_ERROR("EP%d IN Time-out\n", epnum); ++ handle_in_ep_timeout_intr(pcd, epnum); ++ ++ CLEAR_IN_EP_INTR(core_if, epnum, timeout); ++ } ++ /** IN Token received with TxF Empty */ ++ if (diepint.b.intktxfemp) { ++ DWC_DEBUGPL(DBG_ANY, ++ "EP%d IN TKN TxFifo Empty\n", ++ epnum); ++ if (!ep->stopped && epnum != 0) { ++ ++ diepmsk_data_t diepmsk = {.d32 = 0 }; ++ diepmsk.b.intktxfemp = 1; ++ ++ if (core_if->multiproc_int_enable) { ++ DWC_MODIFY_REG32 ++ (&dev_if->dev_global_regs->diepeachintmsk ++ [epnum], diepmsk.d32, 0); ++ } else { ++ DWC_MODIFY_REG32 ++ (&dev_if->dev_global_regs->diepmsk, ++ diepmsk.d32, 0); ++ } ++ } else if (core_if->dma_desc_enable ++ && epnum == 0 ++ && pcd->ep0state == ++ EP0_OUT_STATUS_PHASE) { ++ // EP0 IN set STALL ++ depctl.d32 = ++ DWC_READ_REG32(&dev_if->in_ep_regs ++ [epnum]->diepctl); ++ ++ /* set the disable and stall bits */ ++ if (depctl.b.epena) { ++ depctl.b.epdis = 1; ++ } ++ depctl.b.stall = 1; ++ DWC_WRITE_REG32(&dev_if->in_ep_regs ++ [epnum]->diepctl, ++ depctl.d32); ++ } ++ CLEAR_IN_EP_INTR(core_if, epnum, intktxfemp); ++ } ++ /** IN Token Received with EP mismatch */ ++ if (diepint.b.intknepmis) { ++ DWC_DEBUGPL(DBG_ANY, ++ "EP%d IN TKN EP Mismatch\n", epnum); ++ CLEAR_IN_EP_INTR(core_if, epnum, intknepmis); ++ } ++ /** IN Endpoint NAK Effective */ ++ if (diepint.b.inepnakeff) { ++ DWC_DEBUGPL(DBG_ANY, ++ "EP%d IN EP NAK Effective\n", ++ epnum); ++ /* Periodic EP */ ++ if (ep->disabling) { ++ depctl.d32 = 0; ++ depctl.b.snak = 1; ++ depctl.b.epdis = 1; ++ DWC_MODIFY_REG32(&dev_if->in_ep_regs ++ [epnum]->diepctl, ++ depctl.d32, ++ depctl.d32); ++ } ++ CLEAR_IN_EP_INTR(core_if, epnum, inepnakeff); ++ ++ } ++ ++ /** IN EP Tx FIFO Empty Intr */ ++ if (diepint.b.emptyintr) { ++ DWC_DEBUGPL(DBG_ANY, ++ "EP%d Tx FIFO Empty Intr \n", ++ epnum); ++ write_empty_tx_fifo(pcd, epnum); ++ ++ CLEAR_IN_EP_INTR(core_if, epnum, emptyintr); ++ ++ } ++ ++ /** IN EP BNA Intr */ ++ if (diepint.b.bna) { ++ CLEAR_IN_EP_INTR(core_if, epnum, bna); ++ if (core_if->dma_desc_enable) { ++#ifdef DWC_EN_ISOC ++ if (dwc_ep->type == ++ DWC_OTG_EP_TYPE_ISOC) { ++ /* ++ * This checking is performed to prevent first "false" BNA ++ * handling occuring right after reconnect ++ */ ++ if (dwc_ep->next_frame != ++ 0xffffffff) ++ dwc_otg_pcd_handle_iso_bna(ep); ++ } else ++#endif /* DWC_EN_ISOC */ ++ { ++ dwc_otg_pcd_handle_noniso_bna(ep); ++ } ++ } ++ } ++ /* NAK Interrutp */ ++ if (diepint.b.nak) { ++ DWC_DEBUGPL(DBG_ANY, "EP%d IN NAK Interrupt\n", ++ epnum); ++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) { ++ depctl_data_t depctl; ++ if (ep->dwc_ep.frame_num == 0xFFFFFFFF) { ++ ep->dwc_ep.frame_num = core_if->frame_num; ++ if (ep->dwc_ep.bInterval > 1) { ++ depctl.d32 = 0; ++ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl); ++ if (ep->dwc_ep.frame_num & 0x1) { ++ depctl.b.setd1pid = 1; ++ depctl.b.setd0pid = 0; ++ } else { ++ depctl.b.setd0pid = 1; ++ depctl.b.setd1pid = 0; ++ } ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[epnum]->diepctl, depctl.d32); ++ } ++ start_next_request(ep); ++ } ++ ep->dwc_ep.frame_num += ep->dwc_ep.bInterval; ++ if (dwc_ep->frame_num > 0x3FFF) { ++ dwc_ep->frm_overrun = 1; ++ dwc_ep->frame_num &= 0x3FFF; ++ } else ++ dwc_ep->frm_overrun = 0; ++ } ++ ++ CLEAR_IN_EP_INTR(core_if, epnum, nak); ++ } ++ } ++ epnum++; ++ ep_intr >>= 1; ++ } ++ ++ return 1; ++#undef CLEAR_IN_EP_INTR ++} ++ ++/** ++ * This interrupt indicates that an OUT EP has a pending Interrupt. ++ * The sequence for handling the OUT EP interrupt is shown below: ++ * -# Read the Device All Endpoint Interrupt register ++ * -# Repeat the following for each OUT EP interrupt bit set (from ++ * LSB to MSB). ++ * -# Read the Device Endpoint Interrupt (DOEPINTn) register ++ * -# If "Transfer Complete" call the request complete function ++ * -# If "Endpoint Disabled" complete the EP disable procedure. ++ * -# If "AHB Error Interrupt" log error ++ * -# If "Setup Phase Done" process Setup Packet (See Standard USB ++ * Command Processing) ++ */ ++static int32_t dwc_otg_pcd_handle_out_ep_intr(dwc_otg_pcd_t * pcd) ++{ ++#define CLEAR_OUT_EP_INTR(__core_if,__epnum,__intr) \ ++do { \ ++ doepint_data_t doepint = {.d32=0}; \ ++ doepint.b.__intr = 1; \ ++ DWC_WRITE_REG32(&__core_if->dev_if->out_ep_regs[__epnum]->doepint, \ ++ doepint.d32); \ ++} while (0) ++ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ uint32_t ep_intr; ++ doepint_data_t doepint = {.d32 = 0 }; ++ uint32_t epnum = 0; ++ dwc_otg_pcd_ep_t *ep; ++ dwc_ep_t *dwc_ep; ++ dctl_data_t dctl = {.d32 = 0 }; ++ gintmsk_data_t gintmsk = {.d32 = 0 }; ++ ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__); ++ ++ /* Read in the device interrupt bits */ ++ ep_intr = dwc_otg_read_dev_all_out_ep_intr(core_if); ++ ++ while (ep_intr) { ++ if (ep_intr & 0x1) { ++ /* Get EP pointer */ ++ ep = get_out_ep(pcd, epnum); ++ dwc_ep = &ep->dwc_ep; ++ ++#ifdef VERBOSE ++ DWC_DEBUGPL(DBG_PCDV, ++ "EP%d-%s: type=%d, mps=%d\n", ++ dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"), ++ dwc_ep->type, dwc_ep->maxpacket); ++#endif ++ doepint.d32 = ++ dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep); ++ /* Moved this interrupt upper due to core deffect of asserting ++ * OUT EP 0 xfercompl along with stsphsrcvd in BDMA */ ++ if (doepint.b.stsphsercvd) { ++ deptsiz0_data_t deptsiz; ++ CLEAR_OUT_EP_INTR(core_if, epnum, stsphsercvd); ++ deptsiz.d32 = ++ DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[0]->doeptsiz); ++ if (core_if->snpsid >= OTG_CORE_REV_3_00a ++ && core_if->dma_enable ++ && core_if->dma_desc_enable == 0 ++ && doepint.b.xfercompl ++ && deptsiz.b.xfersize == 24) { ++ CLEAR_OUT_EP_INTR(core_if, epnum, ++ xfercompl); ++ doepint.b.xfercompl = 0; ++ ep0_out_start(core_if, pcd); ++ } ++ if ((core_if->dma_desc_enable) || ++ (core_if->dma_enable ++ && core_if->snpsid >= ++ OTG_CORE_REV_3_00a)) { ++ do_setup_in_status_phase(pcd); ++ } ++ } ++ /* Transfer complete */ ++ if (doepint.b.xfercompl) { ++ ++ if (epnum == 0) { ++ /* Clear the bit in DOEPINTn for this interrupt */ ++ CLEAR_OUT_EP_INTR(core_if, epnum, xfercompl); ++ if (core_if->snpsid >= OTG_CORE_REV_3_00a) { ++ DWC_DEBUGPL(DBG_PCDV, "DOEPINT=%x doepint=%x\n", ++ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[0]->doepint), ++ doepint.d32); ++ DWC_DEBUGPL(DBG_PCDV, "DOEPCTL=%x \n", ++ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[0]->doepctl)); ++ ++ if (core_if->snpsid >= OTG_CORE_REV_3_00a ++ && core_if->dma_enable == 0) { ++ doepint_data_t doepint; ++ doepint.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[0]->doepint); ++ if (pcd->ep0state == EP0_IDLE && doepint.b.sr) { ++ CLEAR_OUT_EP_INTR(core_if, epnum, sr); ++ goto exit_xfercompl; ++ } ++ } ++ /* In case of DDMA look at SR bit to go to the Data Stage */ ++ if (core_if->dma_desc_enable) { ++ dev_dma_desc_sts_t status = {.d32 = 0}; ++ if (pcd->ep0state == EP0_IDLE) { ++ status.d32 = core_if->dev_if->setup_desc_addr[core_if-> ++ dev_if->setup_desc_index]->status.d32; ++ if(pcd->data_terminated) { ++ pcd->data_terminated = 0; ++ status.d32 = core_if->dev_if->out_desc_addr->status.d32; ++ dwc_memcpy(&pcd->setup_pkt->req, pcd->backup_buf, 8); ++ } ++ if (status.b.sr) { ++ if (doepint.b.setup) { ++ DWC_DEBUGPL(DBG_PCDV, "DMA DESC EP0_IDLE SR=1 setup=1\n"); ++ /* Already started data stage, clear setup */ ++ CLEAR_OUT_EP_INTR(core_if, epnum, setup); ++ doepint.b.setup = 0; ++ handle_ep0(pcd); ++ /* Prepare for more setup packets */ ++ if (pcd->ep0state == EP0_IN_STATUS_PHASE || ++ pcd->ep0state == EP0_IN_DATA_PHASE) { ++ ep0_out_start(core_if, pcd); ++ } ++ ++ goto exit_xfercompl; ++ } else { ++ /* Prepare for more setup packets */ ++ DWC_DEBUGPL(DBG_PCDV, ++ "EP0_IDLE SR=1 setup=0 new setup comes\n"); ++ ep0_out_start(core_if, pcd); ++ } ++ } ++ } else { ++ dwc_otg_pcd_request_t *req; ++ dev_dma_desc_sts_t status = {.d32 = 0}; ++ diepint_data_t diepint0; ++ diepint0.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ in_ep_regs[0]->diepint); ++ ++ if (pcd->ep0state == EP0_STALL || pcd->ep0state == EP0_DISCONNECT) { ++ DWC_ERROR("EP0 is stalled/disconnected\n"); ++ } ++ ++ /* Clear IN xfercompl if set */ ++ if (diepint0.b.xfercompl && (pcd->ep0state == EP0_IN_STATUS_PHASE ++ || pcd->ep0state == EP0_IN_DATA_PHASE)) { ++ DWC_WRITE_REG32(&core_if->dev_if-> ++ in_ep_regs[0]->diepint, diepint0.d32); ++ } ++ ++ status.d32 = core_if->dev_if->setup_desc_addr[core_if-> ++ dev_if->setup_desc_index]->status.d32; ++ ++ if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len ++ && (pcd->ep0state == EP0_OUT_DATA_PHASE)) ++ status.d32 = core_if->dev_if->out_desc_addr->status.d32; ++ if (pcd->ep0state == EP0_OUT_STATUS_PHASE) ++ status.d32 = core_if->dev_if-> ++ out_desc_addr->status.d32; ++ ++ if (status.b.sr) { ++ if (DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ DWC_DEBUGPL(DBG_PCDV, "Request queue empty!!\n"); ++ } else { ++ DWC_DEBUGPL(DBG_PCDV, "complete req!!\n"); ++ req = DWC_CIRCLEQ_FIRST(&ep->queue); ++ if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len && ++ pcd->ep0state == EP0_OUT_DATA_PHASE) { ++ /* Read arrived setup packet from req->buf */ ++ dwc_memcpy(&pcd->setup_pkt->req, ++ req->buf + ep->dwc_ep.xfer_count, 8); ++ } ++ req->actual = ep->dwc_ep.xfer_count; ++ dwc_otg_request_done(ep, req, -ECONNRESET); ++ ep->dwc_ep.start_xfer_buff = 0; ++ ep->dwc_ep.xfer_buff = 0; ++ ep->dwc_ep.xfer_len = 0; ++ } ++ pcd->ep0state = EP0_IDLE; ++ if (doepint.b.setup) { ++ DWC_DEBUGPL(DBG_PCDV, "EP0_IDLE SR=1 setup=1\n"); ++ /* Data stage started, clear setup */ ++ CLEAR_OUT_EP_INTR(core_if, epnum, setup); ++ doepint.b.setup = 0; ++ handle_ep0(pcd); ++ /* Prepare for setup packets if ep0in was enabled*/ ++ if (pcd->ep0state == EP0_IN_STATUS_PHASE) { ++ ep0_out_start(core_if, pcd); ++ } ++ ++ goto exit_xfercompl; ++ } else { ++ /* Prepare for more setup packets */ ++ DWC_DEBUGPL(DBG_PCDV, ++ "EP0_IDLE SR=1 setup=0 new setup comes 2\n"); ++ ep0_out_start(core_if, pcd); ++ } ++ } ++ } ++ } ++ if (core_if->snpsid >= OTG_CORE_REV_2_94a && core_if->dma_enable ++ && core_if->dma_desc_enable == 0) { ++ doepint_data_t doepint_temp = {.d32 = 0}; ++ deptsiz0_data_t doeptsize0 = {.d32 = 0 }; ++ doepint_temp.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[ep->dwc_ep.num]->doepint); ++ doeptsize0.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[ep->dwc_ep.num]->doeptsiz); ++ if (pcd->ep0state == EP0_IDLE) { ++ if (doepint_temp.b.sr) { ++ CLEAR_OUT_EP_INTR(core_if, epnum, sr); ++ } ++ doepint.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[0]->doepint); ++ if (doeptsize0.b.supcnt == 3) { ++ DWC_DEBUGPL(DBG_ANY, "Rolling over!!!!!!!\n"); ++ ep->dwc_ep.stp_rollover = 1; ++ } ++ if (doepint.b.setup) { ++retry: ++ /* Already started data stage, clear setup */ ++ CLEAR_OUT_EP_INTR(core_if, epnum, setup); ++ doepint.b.setup = 0; ++ handle_ep0(pcd); ++ ep->dwc_ep.stp_rollover = 0; ++ /* Prepare for more setup packets */ ++ if (pcd->ep0state == EP0_IN_STATUS_PHASE || ++ pcd->ep0state == EP0_IN_DATA_PHASE) { ++ ep0_out_start(core_if, pcd); ++ } ++ goto exit_xfercompl; ++ } else { ++ /* Prepare for more setup packets */ ++ DWC_DEBUGPL(DBG_ANY, ++ "EP0_IDLE SR=1 setup=0 new setup comes\n"); ++ doepint.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[0]->doepint); ++ if(doepint.b.setup) ++ goto retry; ++ ep0_out_start(core_if, pcd); ++ } ++ } else { ++ dwc_otg_pcd_request_t *req; ++ diepint_data_t diepint0 = {.d32 = 0}; ++ doepint_data_t doepint_temp = {.d32 = 0}; ++ depctl_data_t diepctl0; ++ diepint0.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ in_ep_regs[0]->diepint); ++ diepctl0.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ in_ep_regs[0]->diepctl); ++ ++ if (pcd->ep0state == EP0_IN_DATA_PHASE ++ || pcd->ep0state == EP0_IN_STATUS_PHASE) { ++ if (diepint0.b.xfercompl) { ++ DWC_WRITE_REG32(&core_if->dev_if-> ++ in_ep_regs[0]->diepint, diepint0.d32); ++ } ++ if (diepctl0.b.epena) { ++ diepint_data_t diepint = {.d32 = 0}; ++ diepctl0.b.snak = 1; ++ DWC_WRITE_REG32(&core_if->dev_if-> ++ in_ep_regs[0]->diepctl, diepctl0.d32); ++ do { ++ dwc_udelay(10); ++ diepint.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ in_ep_regs[0]->diepint); ++ } while (!diepint.b.inepnakeff); ++ diepint.b.inepnakeff = 1; ++ DWC_WRITE_REG32(&core_if->dev_if-> ++ in_ep_regs[0]->diepint, diepint.d32); ++ diepctl0.d32 = 0; ++ diepctl0.b.epdis = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[0]->diepctl, ++ diepctl0.d32); ++ do { ++ dwc_udelay(10); ++ diepint.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ in_ep_regs[0]->diepint); ++ } while (!diepint.b.epdisabled); ++ diepint.b.epdisabled = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[0]->diepint, ++ diepint.d32); ++ } ++ } ++ doepint_temp.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[ep->dwc_ep.num]->doepint); ++ if (doepint_temp.b.sr) { ++ CLEAR_OUT_EP_INTR(core_if, epnum, sr); ++ if (DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ DWC_DEBUGPL(DBG_PCDV, "Request queue empty!!\n"); ++ } else { ++ DWC_DEBUGPL(DBG_PCDV, "complete req!!\n"); ++ req = DWC_CIRCLEQ_FIRST(&ep->queue); ++ if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len && ++ pcd->ep0state == EP0_OUT_DATA_PHASE) { ++ /* Read arrived setup packet from req->buf */ ++ dwc_memcpy(&pcd->setup_pkt->req, ++ req->buf + ep->dwc_ep.xfer_count, 8); ++ } ++ req->actual = ep->dwc_ep.xfer_count; ++ dwc_otg_request_done(ep, req, -ECONNRESET); ++ ep->dwc_ep.start_xfer_buff = 0; ++ ep->dwc_ep.xfer_buff = 0; ++ ep->dwc_ep.xfer_len = 0; ++ } ++ pcd->ep0state = EP0_IDLE; ++ if (doepint.b.setup) { ++ DWC_DEBUGPL(DBG_PCDV, "EP0_IDLE SR=1 setup=1\n"); ++ /* Data stage started, clear setup */ ++ CLEAR_OUT_EP_INTR(core_if, epnum, setup); ++ doepint.b.setup = 0; ++ handle_ep0(pcd); ++ /* Prepare for setup packets if ep0in was enabled*/ ++ if (pcd->ep0state == EP0_IN_STATUS_PHASE) { ++ ep0_out_start(core_if, pcd); ++ } ++ goto exit_xfercompl; ++ } else { ++ /* Prepare for more setup packets */ ++ DWC_DEBUGPL(DBG_PCDV, ++ "EP0_IDLE SR=1 setup=0 new setup comes 2\n"); ++ ep0_out_start(core_if, pcd); ++ } ++ } ++ } ++ } ++ if (core_if->dma_enable == 0 || pcd->ep0state != EP0_IDLE) ++ handle_ep0(pcd); ++exit_xfercompl: ++ DWC_DEBUGPL(DBG_PCDV, "DOEPINT=%x doepint=%x\n", ++ dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep), doepint.d32); ++ } else { ++ if (core_if->dma_desc_enable == 0 ++ || pcd->ep0state != EP0_IDLE) ++ handle_ep0(pcd); ++ } ++#ifdef DWC_EN_ISOC ++ } else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ if (doepint.b.pktdrpsts == 0) { ++ /* Clear the bit in DOEPINTn for this interrupt */ ++ CLEAR_OUT_EP_INTR(core_if, ++ epnum, ++ xfercompl); ++ complete_iso_ep(pcd, ep); ++ } else { ++ ++ doepint_data_t doepint = {.d32 = 0 }; ++ doepint.b.xfercompl = 1; ++ doepint.b.pktdrpsts = 1; ++ DWC_WRITE_REG32 ++ (&core_if->dev_if->out_ep_regs ++ [epnum]->doepint, ++ doepint.d32); ++ if (handle_iso_out_pkt_dropped ++ (core_if, dwc_ep)) { ++ complete_iso_ep(pcd, ++ ep); ++ } ++ } ++#endif /* DWC_EN_ISOC */ ++#ifdef DWC_UTE_PER_IO ++ } else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ CLEAR_OUT_EP_INTR(core_if, epnum, xfercompl); ++ if (!ep->stopped) ++ complete_xiso_ep(ep); ++#endif /* DWC_UTE_PER_IO */ ++ } else { ++ /* Clear the bit in DOEPINTn for this interrupt */ ++ CLEAR_OUT_EP_INTR(core_if, epnum, ++ xfercompl); ++ ++ if (core_if->core_params->dev_out_nak) { ++ DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[epnum]); ++ pcd->core_if->ep_xfer_info[epnum].state = 0; ++#ifdef DEBUG ++ print_memory_payload(pcd, dwc_ep); ++#endif ++ } ++ complete_ep(ep); ++ } ++ ++ } ++ ++ /* Endpoint disable */ ++ if (doepint.b.epdisabled) { ++ ++ /* Clear the bit in DOEPINTn for this interrupt */ ++ CLEAR_OUT_EP_INTR(core_if, epnum, epdisabled); ++ if (core_if->core_params->dev_out_nak) { ++#ifdef DEBUG ++ print_memory_payload(pcd, dwc_ep); ++#endif ++ /* In case of timeout condition */ ++ if (core_if->ep_xfer_info[epnum].state == 2) { ++ dctl.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ dev_global_regs->dctl); ++ dctl.b.cgoutnak = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, ++ dctl.d32); ++ /* Unmask goutnakeff interrupt which was masked ++ * during handle nak out interrupt */ ++ gintmsk.b.goutnakeff = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, ++ 0, gintmsk.d32); ++ ++ complete_ep(ep); ++ } ++ } ++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) ++ { ++ dctl_data_t dctl; ++ gintmsk_data_t intr_mask = {.d32 = 0}; ++ dwc_otg_pcd_request_t *req = 0; ++ ++ dctl.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ dev_global_regs->dctl); ++ dctl.b.cgoutnak = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, ++ dctl.d32); ++ ++ intr_mask.d32 = 0; ++ intr_mask.b.incomplisoout = 1; ++ ++ /* Get any pending requests */ ++ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ req = DWC_CIRCLEQ_FIRST(&ep->queue); ++ if (!req) { ++ DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep); ++ } else { ++ dwc_otg_request_done(ep, req, 0); ++ start_next_request(ep); ++ } ++ } else { ++ DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep); ++ } ++ } ++ } ++ /* AHB Error */ ++ if (doepint.b.ahberr) { ++ DWC_ERROR("EP%d OUT AHB Error\n", epnum); ++ DWC_ERROR("EP%d DEPDMA=0x%08x \n", ++ epnum, core_if->dev_if->out_ep_regs[epnum]->doepdma); ++ CLEAR_OUT_EP_INTR(core_if, epnum, ahberr); ++ } ++ /* Setup Phase Done (contorl EPs) */ ++ if (doepint.b.setup) { ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCD, "EP%d SETUP Done\n", epnum); ++#endif ++ CLEAR_OUT_EP_INTR(core_if, epnum, setup); ++ ++ handle_ep0(pcd); ++ } ++ ++ /** OUT EP BNA Intr */ ++ if (doepint.b.bna) { ++ CLEAR_OUT_EP_INTR(core_if, epnum, bna); ++ if (core_if->dma_desc_enable) { ++#ifdef DWC_EN_ISOC ++ if (dwc_ep->type == ++ DWC_OTG_EP_TYPE_ISOC) { ++ /* ++ * This checking is performed to prevent first "false" BNA ++ * handling occuring right after reconnect ++ */ ++ if (dwc_ep->next_frame != ++ 0xffffffff) ++ dwc_otg_pcd_handle_iso_bna(ep); ++ } else ++#endif /* DWC_EN_ISOC */ ++ { ++ dwc_otg_pcd_handle_noniso_bna(ep); ++ } ++ } ++ } ++ /* Babble Interrupt */ ++ if (doepint.b.babble) { ++ DWC_DEBUGPL(DBG_ANY, "EP%d OUT Babble\n", ++ epnum); ++ handle_out_ep_babble_intr(pcd, epnum); ++ ++ CLEAR_OUT_EP_INTR(core_if, epnum, babble); ++ } ++ if (doepint.b.outtknepdis) { ++ DWC_DEBUGPL(DBG_ANY, "EP%d OUT Token received when EP is \ ++ disabled\n",epnum); ++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) { ++ doepmsk_data_t doepmsk = {.d32 = 0}; ++ ep->dwc_ep.frame_num = core_if->frame_num; ++ if (ep->dwc_ep.bInterval > 1) { ++ depctl_data_t depctl; ++ depctl.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[epnum]->doepctl); ++ if (ep->dwc_ep.frame_num & 0x1) { ++ depctl.b.setd1pid = 1; ++ depctl.b.setd0pid = 0; ++ } else { ++ depctl.b.setd0pid = 1; ++ depctl.b.setd1pid = 0; ++ } ++ DWC_WRITE_REG32(&core_if->dev_if-> ++ out_ep_regs[epnum]->doepctl, depctl.d32); ++ } ++ start_next_request(ep); ++ doepmsk.b.outtknepdis = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk, ++ doepmsk.d32, 0); ++ } ++ CLEAR_OUT_EP_INTR(core_if, epnum, outtknepdis); ++ } ++ ++ /* NAK Interrutp */ ++ if (doepint.b.nak) { ++ DWC_DEBUGPL(DBG_ANY, "EP%d OUT NAK\n", epnum); ++ handle_out_ep_nak_intr(pcd, epnum); ++ ++ CLEAR_OUT_EP_INTR(core_if, epnum, nak); ++ } ++ /* NYET Interrutp */ ++ if (doepint.b.nyet) { ++ DWC_DEBUGPL(DBG_ANY, "EP%d OUT NYET\n", epnum); ++ handle_out_ep_nyet_intr(pcd, epnum); ++ ++ CLEAR_OUT_EP_INTR(core_if, epnum, nyet); ++ } ++ } ++ ++ epnum++; ++ ep_intr >>= 1; ++ } ++ ++ return 1; ++ ++#undef CLEAR_OUT_EP_INTR ++} ++static int drop_transfer(uint32_t trgt_fr, uint32_t curr_fr, uint8_t frm_overrun) ++{ ++ int retval = 0; ++ if(!frm_overrun && curr_fr >= trgt_fr) ++ retval = 1; ++ else if (frm_overrun ++ && (curr_fr >= trgt_fr && ((curr_fr - trgt_fr) < 0x3FFF / 2))) ++ retval = 1; ++ return retval; ++} ++/** ++ * Incomplete ISO IN Transfer Interrupt. ++ * This interrupt indicates one of the following conditions occurred ++ * while transmitting an ISOC transaction. ++ * - Corrupted IN Token for ISOC EP. ++ * - Packet not complete in FIFO. ++ * The follow actions will be taken: ++ * -# Determine the EP ++ * -# Set incomplete flag in dwc_ep structure ++ * -# Disable EP; when "Endpoint Disabled" interrupt is received ++ * Flush FIFO ++ */ ++int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr(dwc_otg_pcd_t * pcd) ++{ ++ gintsts_data_t gintsts; ++ ++#ifdef DWC_EN_ISOC ++ dwc_otg_dev_if_t *dev_if; ++ deptsiz_data_t deptsiz = {.d32 = 0 }; ++ depctl_data_t depctl = {.d32 = 0 }; ++ dsts_data_t dsts = {.d32 = 0 }; ++ dwc_ep_t *dwc_ep; ++ int i; ++ ++ dev_if = GET_CORE_IF(pcd)->dev_if; ++ ++ for (i = 1; i <= dev_if->num_in_eps; ++i) { ++ dwc_ep = &pcd->in_ep[i].dwc_ep; ++ if (dwc_ep->active && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ deptsiz.d32 = ++ DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz); ++ depctl.d32 = ++ DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); ++ ++ if (depctl.b.epdis && deptsiz.d32) { ++ set_current_pkt_info(GET_CORE_IF(pcd), dwc_ep); ++ if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) { ++ dwc_ep->cur_pkt = 0; ++ dwc_ep->proc_buf_num = ++ (dwc_ep->proc_buf_num ^ 1) & 0x1; ++ ++ if (dwc_ep->proc_buf_num) { ++ dwc_ep->cur_pkt_addr = ++ dwc_ep->xfer_buff1; ++ dwc_ep->cur_pkt_dma_addr = ++ dwc_ep->dma_addr1; ++ } else { ++ dwc_ep->cur_pkt_addr = ++ dwc_ep->xfer_buff0; ++ dwc_ep->cur_pkt_dma_addr = ++ dwc_ep->dma_addr0; ++ } ++ ++ } ++ ++ dsts.d32 = ++ DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if-> ++ dev_global_regs->dsts); ++ dwc_ep->next_frame = dsts.b.soffn; ++ ++ dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF ++ (pcd), ++ dwc_ep); ++ } ++ } ++ } ++ ++#else ++ depctl_data_t depctl = {.d32 = 0 }; ++ dwc_ep_t *dwc_ep; ++ dwc_otg_dev_if_t *dev_if; ++ int i; ++ dev_if = GET_CORE_IF(pcd)->dev_if; ++ ++ DWC_DEBUGPL(DBG_PCD,"Incomplete ISO IN \n"); ++ ++ for (i = 1; i <= dev_if->num_in_eps; ++i) { ++ dwc_ep = &pcd->in_ep[i-1].dwc_ep; ++ depctl.d32 = ++ DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); ++ if (depctl.b.epena && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ if (drop_transfer(dwc_ep->frame_num, GET_CORE_IF(pcd)->frame_num, ++ dwc_ep->frm_overrun)) ++ { ++ depctl.d32 = ++ DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); ++ depctl.b.snak = 1; ++ depctl.b.epdis = 1; ++ DWC_MODIFY_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32, depctl.d32); ++ } ++ } ++ } ++ ++ /*intr_mask.b.incomplisoin = 1; ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, ++ intr_mask.d32, 0); */ ++#endif //DWC_EN_ISOC ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.incomplisoin = 1; ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * Incomplete ISO OUT Transfer Interrupt. ++ * ++ * This interrupt indicates that the core has dropped an ISO OUT ++ * packet. The following conditions can be the cause: ++ * - FIFO Full, the entire packet would not fit in the FIFO. ++ * - CRC Error ++ * - Corrupted Token ++ * The follow actions will be taken: ++ * -# Determine the EP ++ * -# Set incomplete flag in dwc_ep structure ++ * -# Read any data from the FIFO ++ * -# Disable EP. When "Endpoint Disabled" interrupt is received ++ * re-enable EP. ++ */ ++int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr(dwc_otg_pcd_t * pcd) ++{ ++ ++ gintsts_data_t gintsts; ++ ++#ifdef DWC_EN_ISOC ++ dwc_otg_dev_if_t *dev_if; ++ deptsiz_data_t deptsiz = {.d32 = 0 }; ++ depctl_data_t depctl = {.d32 = 0 }; ++ dsts_data_t dsts = {.d32 = 0 }; ++ dwc_ep_t *dwc_ep; ++ int i; ++ ++ dev_if = GET_CORE_IF(pcd)->dev_if; ++ ++ for (i = 1; i <= dev_if->num_out_eps; ++i) { ++ dwc_ep = &pcd->in_ep[i].dwc_ep; ++ if (pcd->out_ep[i].dwc_ep.active && ++ pcd->out_ep[i].dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) { ++ deptsiz.d32 = ++ DWC_READ_REG32(&dev_if->out_ep_regs[i]->doeptsiz); ++ depctl.d32 = ++ DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl); ++ ++ if (depctl.b.epdis && deptsiz.d32) { ++ set_current_pkt_info(GET_CORE_IF(pcd), ++ &pcd->out_ep[i].dwc_ep); ++ if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) { ++ dwc_ep->cur_pkt = 0; ++ dwc_ep->proc_buf_num = ++ (dwc_ep->proc_buf_num ^ 1) & 0x1; ++ ++ if (dwc_ep->proc_buf_num) { ++ dwc_ep->cur_pkt_addr = ++ dwc_ep->xfer_buff1; ++ dwc_ep->cur_pkt_dma_addr = ++ dwc_ep->dma_addr1; ++ } else { ++ dwc_ep->cur_pkt_addr = ++ dwc_ep->xfer_buff0; ++ dwc_ep->cur_pkt_dma_addr = ++ dwc_ep->dma_addr0; ++ } ++ ++ } ++ ++ dsts.d32 = ++ DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if-> ++ dev_global_regs->dsts); ++ dwc_ep->next_frame = dsts.b.soffn; ++ ++ dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF ++ (pcd), ++ dwc_ep); ++ } ++ } ++ } ++#else ++ /** @todo implement ISR */ ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ dwc_otg_core_if_t *core_if; ++ deptsiz_data_t deptsiz = {.d32 = 0 }; ++ depctl_data_t depctl = {.d32 = 0 }; ++ dctl_data_t dctl = {.d32 = 0 }; ++ dwc_ep_t *dwc_ep = NULL; ++ int i; ++ core_if = GET_CORE_IF(pcd); ++ ++ for (i = 0; i < core_if->dev_if->num_out_eps; ++i) { ++ dwc_ep = &pcd->out_ep[i].dwc_ep; ++ depctl.d32 = ++ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl); ++ if (depctl.b.epena && depctl.b.dpid == (core_if->frame_num & 0x1)) { ++ core_if->dev_if->isoc_ep = dwc_ep; ++ deptsiz.d32 = ++ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz); ++ break; ++ } ++ } ++ dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl); ++ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts); ++ intr_mask.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk); ++ ++ if (!intr_mask.b.goutnakeff) { ++ /* Unmask it */ ++ intr_mask.b.goutnakeff = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, intr_mask.d32); ++ } ++ if (!gintsts.b.goutnakeff) { ++ dctl.b.sgoutnak = 1; ++ } ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32); ++ ++ depctl.d32 = DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl); ++ if (depctl.b.epena) { ++ depctl.b.epdis = 1; ++ depctl.b.snak = 1; ++ } ++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl, depctl.d32); ++ ++ intr_mask.d32 = 0; ++ intr_mask.b.incomplisoout = 1; ++ ++#endif /* DWC_EN_ISOC */ ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.incomplisoout = 1; ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * This function handles the Global IN NAK Effective interrupt. ++ * ++ */ ++int32_t dwc_otg_pcd_handle_in_nak_effective(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if; ++ depctl_data_t diepctl = {.d32 = 0 }; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ gintsts_data_t gintsts; ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ int i; ++ ++ DWC_DEBUGPL(DBG_PCD, "Global IN NAK Effective\n"); ++ ++ /* Disable all active IN EPs */ ++ for (i = 0; i <= dev_if->num_in_eps; i++) { ++ diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); ++ if (!(diepctl.b.eptype & 1) && diepctl.b.epena) { ++ if (core_if->start_predict > 0) ++ core_if->start_predict++; ++ diepctl.b.epdis = 1; ++ diepctl.b.snak = 1; ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, diepctl.d32); ++ } ++ } ++ ++ ++ /* Disable the Global IN NAK Effective Interrupt */ ++ intr_mask.b.ginnakeff = 1; ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, ++ intr_mask.d32, 0); ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.ginnakeff = 1; ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * OUT NAK Effective. ++ * ++ */ ++int32_t dwc_otg_pcd_handle_out_nak_effective(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ gintsts_data_t gintsts; ++ depctl_data_t doepctl; ++ int i; ++ ++ /* Disable the Global OUT NAK Effective Interrupt */ ++ intr_mask.b.goutnakeff = 1; ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, ++ intr_mask.d32, 0); ++ ++ /* If DEV OUT NAK enabled*/ ++ if (pcd->core_if->core_params->dev_out_nak) { ++ /* Run over all out endpoints to determine the ep number on ++ * which the timeout has happened ++ */ ++ for (i = 0; i <= dev_if->num_out_eps; i++) { ++ if ( pcd->core_if->ep_xfer_info[i].state == 2 ) ++ break; ++ } ++ if (i > dev_if->num_out_eps) { ++ dctl_data_t dctl; ++ dctl.d32 = ++ DWC_READ_REG32(&dev_if->dev_global_regs->dctl); ++ dctl.b.cgoutnak = 1; ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->dctl, ++ dctl.d32); ++ goto out; ++ } ++ ++ /* Disable the endpoint */ ++ doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl); ++ if (doepctl.b.epena) { ++ doepctl.b.epdis = 1; ++ doepctl.b.snak = 1; ++ } ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32); ++ return 1; ++ } ++ /* We come here from Incomplete ISO OUT handler */ ++ if (dev_if->isoc_ep) { ++ dwc_ep_t *dwc_ep = (dwc_ep_t *)dev_if->isoc_ep; ++ uint32_t epnum = dwc_ep->num; ++ doepint_data_t doepint; ++ doepint.d32 = ++ DWC_READ_REG32(&dev_if->out_ep_regs[dwc_ep->num]->doepint); ++ dev_if->isoc_ep = NULL; ++ doepctl.d32 = ++ DWC_READ_REG32(&dev_if->out_ep_regs[epnum]->doepctl); ++ DWC_PRINTF("Before disable DOEPCTL = %08x\n", doepctl.d32); ++ if (doepctl.b.epena) { ++ doepctl.b.epdis = 1; ++ doepctl.b.snak = 1; ++ } ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[epnum]->doepctl, ++ doepctl.d32); ++ return 1; ++ } else ++ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", ++ "Global OUT NAK Effective\n"); ++ ++out: ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.goutnakeff = 1; ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * PCD interrupt handler. ++ * ++ * The PCD handles the device interrupts. Many conditions can cause a ++ * device interrupt. When an interrupt occurs, the device interrupt ++ * service routine determines the cause of the interrupt and ++ * dispatches handling to the appropriate function. These interrupt ++ * handling functions are described below. ++ * ++ * All interrupt registers are processed from LSB to MSB. ++ * ++ */ ++int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++#ifdef VERBOSE ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++#endif ++ gintsts_data_t gintr_status; ++ int32_t retval = 0; ++ ++ /* Exit from ISR if core is hibernated */ ++ if (core_if->hibernation_suspend == 1) { ++ return retval; ++ } ++#ifdef VERBOSE ++ DWC_DEBUGPL(DBG_ANY, "%s() gintsts=%08x gintmsk=%08x\n", ++ __func__, ++ DWC_READ_REG32(&global_regs->gintsts), ++ DWC_READ_REG32(&global_regs->gintmsk)); ++#endif ++ ++ if (dwc_otg_is_device_mode(core_if)) { ++ DWC_SPINLOCK(pcd->lock); ++#ifdef VERBOSE ++ DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%08x gintmsk=%08x\n", ++ __func__, ++ DWC_READ_REG32(&global_regs->gintsts), ++ DWC_READ_REG32(&global_regs->gintmsk)); ++#endif ++ ++ gintr_status.d32 = dwc_otg_read_core_intr(core_if); ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s: gintsts&gintmsk=%08x\n", ++ __func__, gintr_status.d32); ++ ++ if (gintr_status.b.sofintr) { ++ retval |= dwc_otg_pcd_handle_sof_intr(pcd); ++ } ++ if (gintr_status.b.rxstsqlvl) { ++ retval |= ++ dwc_otg_pcd_handle_rx_status_q_level_intr(pcd); ++ } ++ if (gintr_status.b.nptxfempty) { ++ retval |= dwc_otg_pcd_handle_np_tx_fifo_empty_intr(pcd); ++ } ++ if (gintr_status.b.goutnakeff) { ++ retval |= dwc_otg_pcd_handle_out_nak_effective(pcd); ++ } ++ if (gintr_status.b.i2cintr) { ++ retval |= dwc_otg_pcd_handle_i2c_intr(pcd); ++ } ++ if (gintr_status.b.erlysuspend) { ++ retval |= dwc_otg_pcd_handle_early_suspend_intr(pcd); ++ } ++ if (gintr_status.b.usbreset) { ++ retval |= dwc_otg_pcd_handle_usb_reset_intr(pcd); ++ } ++ if (gintr_status.b.enumdone) { ++ retval |= dwc_otg_pcd_handle_enum_done_intr(pcd); ++ } ++ if (gintr_status.b.isooutdrop) { ++ retval |= ++ dwc_otg_pcd_handle_isoc_out_packet_dropped_intr ++ (pcd); ++ } ++ if (gintr_status.b.eopframe) { ++ retval |= ++ dwc_otg_pcd_handle_end_periodic_frame_intr(pcd); ++ } ++ if (gintr_status.b.inepint) { ++ if (!core_if->multiproc_int_enable) { ++ retval |= dwc_otg_pcd_handle_in_ep_intr(pcd); ++ } ++ } ++ if (gintr_status.b.outepintr) { ++ if (!core_if->multiproc_int_enable) { ++ retval |= dwc_otg_pcd_handle_out_ep_intr(pcd); ++ } ++ } ++ if (gintr_status.b.epmismatch) { ++ retval |= dwc_otg_pcd_handle_ep_mismatch_intr(pcd); ++ } ++ if (gintr_status.b.fetsusp) { ++ retval |= dwc_otg_pcd_handle_ep_fetsusp_intr(pcd); ++ } ++ if (gintr_status.b.ginnakeff) { ++ retval |= dwc_otg_pcd_handle_in_nak_effective(pcd); ++ } ++ if (gintr_status.b.incomplisoin) { ++ retval |= ++ dwc_otg_pcd_handle_incomplete_isoc_in_intr(pcd); ++ } ++ if (gintr_status.b.incomplisoout) { ++ retval |= ++ dwc_otg_pcd_handle_incomplete_isoc_out_intr(pcd); ++ } ++ ++ /* In MPI mode Device Endpoints interrupts are asserted ++ * without setting outepintr and inepint bits set, so these ++ * Interrupt handlers are called without checking these bit-fields ++ */ ++ if (core_if->multiproc_int_enable) { ++ retval |= dwc_otg_pcd_handle_in_ep_intr(pcd); ++ retval |= dwc_otg_pcd_handle_out_ep_intr(pcd); ++ } ++#ifdef VERBOSE ++ DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%0x\n", __func__, ++ DWC_READ_REG32(&global_regs->gintsts)); ++#endif ++ DWC_SPINUNLOCK(pcd->lock); ++ } ++ return retval; ++} ++ ++#endif /* DWC_HOST_ONLY */ +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c 2015-11-29 09:42:39.923098428 +0100 +@@ -0,0 +1,1360 @@ ++ /* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_linux.c $ ++ * $Revision: #21 $ ++ * $Date: 2012/08/10 $ ++ * $Change: 2047372 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_HOST_ONLY ++ ++/** @file ++ * This file implements the Peripheral Controller Driver. ++ * ++ * The Peripheral Controller Driver (PCD) is responsible for ++ * translating requests from the Function Driver into the appropriate ++ * actions on the DWC_otg controller. It isolates the Function Driver ++ * from the specifics of the controller by providing an API to the ++ * Function Driver. ++ * ++ * The Peripheral Controller Driver for Linux will implement the ++ * Gadget API, so that the existing Gadget drivers can be used. ++ * (Gadget Driver is the Linux terminology for a Function Driver.) ++ * ++ * The Linux Gadget API is defined in the header file ++ * . The USB EP operations API is ++ * defined in the structure usb_ep_ops and the USB ++ * Controller API is defined in the structure ++ * usb_gadget_ops. ++ * ++ */ ++ ++#include "dwc_otg_os_dep.h" ++#include "dwc_otg_pcd_if.h" ++#include "dwc_otg_pcd.h" ++#include "dwc_otg_driver.h" ++#include "dwc_otg_dbg.h" ++ ++extern bool fiq_enable; ++ ++static struct gadget_wrapper { ++ dwc_otg_pcd_t *pcd; ++ ++ struct usb_gadget gadget; ++ struct usb_gadget_driver *driver; ++ ++ struct usb_ep ep0; ++ struct usb_ep in_ep[16]; ++ struct usb_ep out_ep[16]; ++ ++} *gadget_wrapper; ++ ++/* Display the contents of the buffer */ ++extern void dump_msg(const u8 * buf, unsigned int length); ++/** ++ * Get the dwc_otg_pcd_ep_t* from usb_ep* pointer - NULL in case ++ * if the endpoint is not found ++ */ ++static struct dwc_otg_pcd_ep *ep_from_handle(dwc_otg_pcd_t * pcd, void *handle) ++{ ++ int i; ++ if (pcd->ep0.priv == handle) { ++ return &pcd->ep0; ++ } ++ ++ for (i = 0; i < MAX_EPS_CHANNELS - 1; i++) { ++ if (pcd->in_ep[i].priv == handle) ++ return &pcd->in_ep[i]; ++ if (pcd->out_ep[i].priv == handle) ++ return &pcd->out_ep[i]; ++ } ++ ++ return NULL; ++} ++ ++/* USB Endpoint Operations */ ++/* ++ * The following sections briefly describe the behavior of the Gadget ++ * API endpoint operations implemented in the DWC_otg driver ++ * software. Detailed descriptions of the generic behavior of each of ++ * these functions can be found in the Linux header file ++ * include/linux/usb_gadget.h. ++ * ++ * The Gadget API provides wrapper functions for each of the function ++ * pointers defined in usb_ep_ops. The Gadget Driver calls the wrapper ++ * function, which then calls the underlying PCD function. The ++ * following sections are named according to the wrapper ++ * functions. Within each section, the corresponding DWC_otg PCD ++ * function name is specified. ++ * ++ */ ++ ++/** ++ * This function is called by the Gadget Driver for each EP to be ++ * configured for the current configuration (SET_CONFIGURATION). ++ * ++ * This function initializes the dwc_otg_ep_t data structure, and then ++ * calls dwc_otg_ep_activate. ++ */ ++static int ep_enable(struct usb_ep *usb_ep, ++ const struct usb_endpoint_descriptor *ep_desc) ++{ ++ int retval; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, usb_ep, ep_desc); ++ ++ if (!usb_ep || !ep_desc || ep_desc->bDescriptorType != USB_DT_ENDPOINT) { ++ DWC_WARN("%s, bad ep or descriptor\n", __func__); ++ return -EINVAL; ++ } ++ if (usb_ep == &gadget_wrapper->ep0) { ++ DWC_WARN("%s, bad ep(0)\n", __func__); ++ return -EINVAL; ++ } ++ ++ /* Check FIFO size? */ ++ if (!ep_desc->wMaxPacketSize) { ++ DWC_WARN("%s, bad %s maxpacket\n", __func__, usb_ep->name); ++ return -ERANGE; ++ } ++ ++ if (!gadget_wrapper->driver || ++ gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) { ++ DWC_WARN("%s, bogus device state\n", __func__); ++ return -ESHUTDOWN; ++ } ++ ++ /* Delete after check - MAS */ ++#if 0 ++ nat = (uint32_t) ep_desc->wMaxPacketSize; ++ printk(KERN_ALERT "%s: nat (before) =%d\n", __func__, nat); ++ nat = (nat >> 11) & 0x03; ++ printk(KERN_ALERT "%s: nat (after) =%d\n", __func__, nat); ++#endif ++ retval = dwc_otg_pcd_ep_enable(gadget_wrapper->pcd, ++ (const uint8_t *)ep_desc, ++ (void *)usb_ep); ++ if (retval) { ++ DWC_WARN("dwc_otg_pcd_ep_enable failed\n"); ++ return -EINVAL; ++ } ++ ++ usb_ep->maxpacket = le16_to_cpu(ep_desc->wMaxPacketSize); ++ ++ return 0; ++} ++ ++/** ++ * This function is called when an EP is disabled due to disconnect or ++ * change in configuration. Any pending requests will terminate with a ++ * status of -ESHUTDOWN. ++ * ++ * This function modifies the dwc_otg_ep_t data structure for this EP, ++ * and then calls dwc_otg_ep_deactivate. ++ */ ++static int ep_disable(struct usb_ep *usb_ep) ++{ ++ int retval; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, usb_ep); ++ if (!usb_ep) { ++ DWC_DEBUGPL(DBG_PCD, "%s, %s not enabled\n", __func__, ++ usb_ep ? usb_ep->name : NULL); ++ return -EINVAL; ++ } ++ ++ retval = dwc_otg_pcd_ep_disable(gadget_wrapper->pcd, usb_ep); ++ if (retval) { ++ retval = -EINVAL; ++ } ++ ++ return retval; ++} ++ ++/** ++ * This function allocates a request object to use with the specified ++ * endpoint. ++ * ++ * @param ep The endpoint to be used with with the request ++ * @param gfp_flags the GFP_* flags to use. ++ */ ++static struct usb_request *dwc_otg_pcd_alloc_request(struct usb_ep *ep, ++ gfp_t gfp_flags) ++{ ++ struct usb_request *usb_req; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%d)\n", __func__, ep, gfp_flags); ++ if (0 == ep) { ++ DWC_WARN("%s() %s\n", __func__, "Invalid EP!\n"); ++ return 0; ++ } ++ usb_req = kmalloc(sizeof(*usb_req), gfp_flags); ++ if (0 == usb_req) { ++ DWC_WARN("%s() %s\n", __func__, "request allocation failed!\n"); ++ return 0; ++ } ++ memset(usb_req, 0, sizeof(*usb_req)); ++ usb_req->dma = DWC_DMA_ADDR_INVALID; ++ ++ return usb_req; ++} ++ ++/** ++ * This function frees a request object. ++ * ++ * @param ep The endpoint associated with the request ++ * @param req The request being freed ++ */ ++static void dwc_otg_pcd_free_request(struct usb_ep *ep, struct usb_request *req) ++{ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, ep, req); ++ ++ if (0 == ep || 0 == req) { ++ DWC_WARN("%s() %s\n", __func__, ++ "Invalid ep or req argument!\n"); ++ return; ++ } ++ ++ kfree(req); ++} ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ++/** ++ * This function allocates an I/O buffer to be used for a transfer ++ * to/from the specified endpoint. ++ * ++ * @param usb_ep The endpoint to be used with with the request ++ * @param bytes The desired number of bytes for the buffer ++ * @param dma Pointer to the buffer's DMA address; must be valid ++ * @param gfp_flags the GFP_* flags to use. ++ * @return address of a new buffer or null is buffer could not be allocated. ++ */ ++static void *dwc_otg_pcd_alloc_buffer(struct usb_ep *usb_ep, unsigned bytes, ++ dma_addr_t * dma, gfp_t gfp_flags) ++{ ++ void *buf; ++ dwc_otg_pcd_t *pcd = 0; ++ ++ pcd = gadget_wrapper->pcd; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%d,%p,%0x)\n", __func__, usb_ep, bytes, ++ dma, gfp_flags); ++ ++ /* Check dword alignment */ ++ if ((bytes & 0x3UL) != 0) { ++ DWC_WARN("%s() Buffer size is not a multiple of" ++ "DWORD size (%d)", __func__, bytes); ++ } ++ ++ buf = dma_alloc_coherent(NULL, bytes, dma, gfp_flags); ++ ++ /* Check dword alignment */ ++ if (((int)buf & 0x3UL) != 0) { ++ DWC_WARN("%s() Buffer is not DWORD aligned (%p)", ++ __func__, buf); ++ } ++ ++ return buf; ++} ++ ++/** ++ * This function frees an I/O buffer that was allocated by alloc_buffer. ++ * ++ * @param usb_ep the endpoint associated with the buffer ++ * @param buf address of the buffer ++ * @param dma The buffer's DMA address ++ * @param bytes The number of bytes of the buffer ++ */ ++static void dwc_otg_pcd_free_buffer(struct usb_ep *usb_ep, void *buf, ++ dma_addr_t dma, unsigned bytes) ++{ ++ dwc_otg_pcd_t *pcd = 0; ++ ++ pcd = gadget_wrapper->pcd; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%0x,%d)\n", __func__, buf, dma, bytes); ++ ++ dma_free_coherent(NULL, bytes, buf, dma); ++} ++#endif ++ ++/** ++ * This function is used to submit an I/O Request to an EP. ++ * ++ * - When the request completes the request's completion callback ++ * is called to return the request to the driver. ++ * - An EP, except control EPs, may have multiple requests ++ * pending. ++ * - Once submitted the request cannot be examined or modified. ++ * - Each request is turned into one or more packets. ++ * - A BULK EP can queue any amount of data; the transfer is ++ * packetized. ++ * - Zero length Packets are specified with the request 'zero' ++ * flag. ++ */ ++static int ep_queue(struct usb_ep *usb_ep, struct usb_request *usb_req, ++ gfp_t gfp_flags) ++{ ++ dwc_otg_pcd_t *pcd; ++ struct dwc_otg_pcd_ep *ep = NULL; ++ int retval = 0, is_isoc_ep = 0; ++ dma_addr_t dma_addr = DWC_DMA_ADDR_INVALID; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p,%d)\n", ++ __func__, usb_ep, usb_req, gfp_flags); ++ ++ if (!usb_req || !usb_req->complete || !usb_req->buf) { ++ DWC_WARN("bad params\n"); ++ return -EINVAL; ++ } ++ ++ if (!usb_ep) { ++ DWC_WARN("bad ep\n"); ++ return -EINVAL; ++ } ++ ++ pcd = gadget_wrapper->pcd; ++ if (!gadget_wrapper->driver || ++ gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) { ++ DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n", ++ gadget_wrapper->gadget.speed); ++ DWC_WARN("bogus device state\n"); ++ return -ESHUTDOWN; ++ } ++ ++ DWC_DEBUGPL(DBG_PCD, "%s queue req %p, len %d buf %p\n", ++ usb_ep->name, usb_req, usb_req->length, usb_req->buf); ++ ++ usb_req->status = -EINPROGRESS; ++ usb_req->actual = 0; ++ ++ ep = ep_from_handle(pcd, usb_ep); ++ if (ep == NULL) ++ is_isoc_ep = 0; ++ else ++ is_isoc_ep = (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) ? 1 : 0; ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ++ dma_addr = usb_req->dma; ++#else ++ if (GET_CORE_IF(pcd)->dma_enable) { ++ dwc_otg_device_t *otg_dev = gadget_wrapper->pcd->otg_dev; ++ struct device *dev = NULL; ++ ++ if (otg_dev != NULL) ++ dev = DWC_OTG_OS_GETDEV(otg_dev->os_dep); ++ ++ if (usb_req->length != 0 && ++ usb_req->dma == DWC_DMA_ADDR_INVALID) { ++ dma_addr = dma_map_single(dev, usb_req->buf, ++ usb_req->length, ++ ep->dwc_ep.is_in ? ++ DMA_TO_DEVICE: ++ DMA_FROM_DEVICE); ++ } ++ } ++#endif ++ ++#ifdef DWC_UTE_PER_IO ++ if (is_isoc_ep == 1) { ++ retval = dwc_otg_pcd_xiso_ep_queue(pcd, usb_ep, usb_req->buf, dma_addr, ++ usb_req->length, usb_req->zero, usb_req, ++ gfp_flags == GFP_ATOMIC ? 1 : 0, &usb_req->ext_req); ++ if (retval) ++ return -EINVAL; ++ ++ return 0; ++ } ++#endif ++ retval = dwc_otg_pcd_ep_queue(pcd, usb_ep, usb_req->buf, dma_addr, ++ usb_req->length, usb_req->zero, usb_req, ++ gfp_flags == GFP_ATOMIC ? 1 : 0); ++ if (retval) { ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++/** ++ * This function cancels an I/O request from an EP. ++ */ ++static int ep_dequeue(struct usb_ep *usb_ep, struct usb_request *usb_req) ++{ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, usb_ep, usb_req); ++ ++ if (!usb_ep || !usb_req) { ++ DWC_WARN("bad argument\n"); ++ return -EINVAL; ++ } ++ if (!gadget_wrapper->driver || ++ gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) { ++ DWC_WARN("bogus device state\n"); ++ return -ESHUTDOWN; ++ } ++ if (dwc_otg_pcd_ep_dequeue(gadget_wrapper->pcd, usb_ep, usb_req)) { ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++/** ++ * usb_ep_set_halt stalls an endpoint. ++ * ++ * usb_ep_clear_halt clears an endpoint halt and resets its data ++ * toggle. ++ * ++ * Both of these functions are implemented with the same underlying ++ * function. The behavior depends on the value argument. ++ * ++ * @param[in] usb_ep the Endpoint to halt or clear halt. ++ * @param[in] value ++ * - 0 means clear_halt. ++ * - 1 means set_halt, ++ * - 2 means clear stall lock flag. ++ * - 3 means set stall lock flag. ++ */ ++static int ep_halt(struct usb_ep *usb_ep, int value) ++{ ++ int retval = 0; ++ ++ DWC_DEBUGPL(DBG_PCD, "HALT %s %d\n", usb_ep->name, value); ++ ++ if (!usb_ep) { ++ DWC_WARN("bad ep\n"); ++ return -EINVAL; ++ } ++ ++ retval = dwc_otg_pcd_ep_halt(gadget_wrapper->pcd, usb_ep, value); ++ if (retval == -DWC_E_AGAIN) { ++ return -EAGAIN; ++ } else if (retval) { ++ retval = -EINVAL; ++ } ++ ++ return retval; ++} ++ ++//#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)) ++#if 0 ++/** ++ * ep_wedge: sets the halt feature and ignores clear requests ++ * ++ * @usb_ep: the endpoint being wedged ++ * ++ * Use this to stall an endpoint and ignore CLEAR_FEATURE(HALT_ENDPOINT) ++ * requests. If the gadget driver clears the halt status, it will ++ * automatically unwedge the endpoint. ++ * ++ * Returns zero on success, else negative errno. * ++ * Check usb_ep_set_wedge() at "usb_gadget.h" for details ++ */ ++static int ep_wedge(struct usb_ep *usb_ep) ++{ ++ int retval = 0; ++ ++ DWC_DEBUGPL(DBG_PCD, "WEDGE %s\n", usb_ep->name); ++ ++ if (!usb_ep) { ++ DWC_WARN("bad ep\n"); ++ return -EINVAL; ++ } ++ ++ retval = dwc_otg_pcd_ep_wedge(gadget_wrapper->pcd, usb_ep); ++ if (retval == -DWC_E_AGAIN) { ++ retval = -EAGAIN; ++ } else if (retval) { ++ retval = -EINVAL; ++ } ++ ++ return retval; ++} ++#endif ++ ++#ifdef DWC_EN_ISOC ++/** ++ * This function is used to submit an ISOC Transfer Request to an EP. ++ * ++ * - Every time a sync period completes the request's completion callback ++ * is called to provide data to the gadget driver. ++ * - Once submitted the request cannot be modified. ++ * - Each request is turned into periodic data packets untill ISO ++ * Transfer is stopped.. ++ */ ++static int iso_ep_start(struct usb_ep *usb_ep, struct usb_iso_request *req, ++ gfp_t gfp_flags) ++{ ++ int retval = 0; ++ ++ if (!req || !req->process_buffer || !req->buf0 || !req->buf1) { ++ DWC_WARN("bad params\n"); ++ return -EINVAL; ++ } ++ ++ if (!usb_ep) { ++ DWC_PRINTF("bad params\n"); ++ return -EINVAL; ++ } ++ ++ req->status = -EINPROGRESS; ++ ++ retval = ++ dwc_otg_pcd_iso_ep_start(gadget_wrapper->pcd, usb_ep, req->buf0, ++ req->buf1, req->dma0, req->dma1, ++ req->sync_frame, req->data_pattern_frame, ++ req->data_per_frame, ++ req-> ++ flags & USB_REQ_ISO_ASAP ? -1 : ++ req->start_frame, req->buf_proc_intrvl, ++ req, gfp_flags == GFP_ATOMIC ? 1 : 0); ++ ++ if (retval) { ++ return -EINVAL; ++ } ++ ++ return retval; ++} ++ ++/** ++ * This function stops ISO EP Periodic Data Transfer. ++ */ ++static int iso_ep_stop(struct usb_ep *usb_ep, struct usb_iso_request *req) ++{ ++ int retval = 0; ++ if (!usb_ep) { ++ DWC_WARN("bad ep\n"); ++ } ++ ++ if (!gadget_wrapper->driver || ++ gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) { ++ DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n", ++ gadget_wrapper->gadget.speed); ++ DWC_WARN("bogus device state\n"); ++ } ++ ++ dwc_otg_pcd_iso_ep_stop(gadget_wrapper->pcd, usb_ep, req); ++ if (retval) { ++ retval = -EINVAL; ++ } ++ ++ return retval; ++} ++ ++static struct usb_iso_request *alloc_iso_request(struct usb_ep *ep, ++ int packets, gfp_t gfp_flags) ++{ ++ struct usb_iso_request *pReq = NULL; ++ uint32_t req_size; ++ ++ req_size = sizeof(struct usb_iso_request); ++ req_size += ++ (2 * packets * (sizeof(struct usb_gadget_iso_packet_descriptor))); ++ ++ pReq = kmalloc(req_size, gfp_flags); ++ if (!pReq) { ++ DWC_WARN("Can't allocate Iso Request\n"); ++ return 0; ++ } ++ pReq->iso_packet_desc0 = (void *)(pReq + 1); ++ ++ pReq->iso_packet_desc1 = pReq->iso_packet_desc0 + packets; ++ ++ return pReq; ++} ++ ++static void free_iso_request(struct usb_ep *ep, struct usb_iso_request *req) ++{ ++ kfree(req); ++} ++ ++static struct usb_isoc_ep_ops dwc_otg_pcd_ep_ops = { ++ .ep_ops = { ++ .enable = ep_enable, ++ .disable = ep_disable, ++ ++ .alloc_request = dwc_otg_pcd_alloc_request, ++ .free_request = dwc_otg_pcd_free_request, ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ++ .alloc_buffer = dwc_otg_pcd_alloc_buffer, ++ .free_buffer = dwc_otg_pcd_free_buffer, ++#endif ++ ++ .queue = ep_queue, ++ .dequeue = ep_dequeue, ++ ++ .set_halt = ep_halt, ++ .fifo_status = 0, ++ .fifo_flush = 0, ++ }, ++ .iso_ep_start = iso_ep_start, ++ .iso_ep_stop = iso_ep_stop, ++ .alloc_iso_request = alloc_iso_request, ++ .free_iso_request = free_iso_request, ++}; ++ ++#else ++ ++ int (*enable) (struct usb_ep *ep, ++ const struct usb_endpoint_descriptor *desc); ++ int (*disable) (struct usb_ep *ep); ++ ++ struct usb_request *(*alloc_request) (struct usb_ep *ep, ++ gfp_t gfp_flags); ++ void (*free_request) (struct usb_ep *ep, struct usb_request *req); ++ ++ int (*queue) (struct usb_ep *ep, struct usb_request *req, ++ gfp_t gfp_flags); ++ int (*dequeue) (struct usb_ep *ep, struct usb_request *req); ++ ++ int (*set_halt) (struct usb_ep *ep, int value); ++ int (*set_wedge) (struct usb_ep *ep); ++ ++ int (*fifo_status) (struct usb_ep *ep); ++ void (*fifo_flush) (struct usb_ep *ep); ++static struct usb_ep_ops dwc_otg_pcd_ep_ops = { ++ .enable = ep_enable, ++ .disable = ep_disable, ++ ++ .alloc_request = dwc_otg_pcd_alloc_request, ++ .free_request = dwc_otg_pcd_free_request, ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ++ .alloc_buffer = dwc_otg_pcd_alloc_buffer, ++ .free_buffer = dwc_otg_pcd_free_buffer, ++#else ++ /* .set_wedge = ep_wedge, */ ++ .set_wedge = NULL, /* uses set_halt instead */ ++#endif ++ ++ .queue = ep_queue, ++ .dequeue = ep_dequeue, ++ ++ .set_halt = ep_halt, ++ .fifo_status = 0, ++ .fifo_flush = 0, ++ ++}; ++ ++#endif /* _EN_ISOC_ */ ++/* Gadget Operations */ ++/** ++ * The following gadget operations will be implemented in the DWC_otg ++ * PCD. Functions in the API that are not described below are not ++ * implemented. ++ * ++ * The Gadget API provides wrapper functions for each of the function ++ * pointers defined in usb_gadget_ops. The Gadget Driver calls the ++ * wrapper function, which then calls the underlying PCD function. The ++ * following sections are named according to the wrapper functions ++ * (except for ioctl, which doesn't have a wrapper function). Within ++ * each section, the corresponding DWC_otg PCD function name is ++ * specified. ++ * ++ */ ++ ++/** ++ *Gets the USB Frame number of the last SOF. ++ */ ++static int get_frame_number(struct usb_gadget *gadget) ++{ ++ struct gadget_wrapper *d; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, gadget); ++ ++ if (gadget == 0) { ++ return -ENODEV; ++ } ++ ++ d = container_of(gadget, struct gadget_wrapper, gadget); ++ return dwc_otg_pcd_get_frame_number(d->pcd); ++} ++ ++#ifdef CONFIG_USB_DWC_OTG_LPM ++static int test_lpm_enabled(struct usb_gadget *gadget) ++{ ++ struct gadget_wrapper *d; ++ ++ d = container_of(gadget, struct gadget_wrapper, gadget); ++ ++ return dwc_otg_pcd_is_lpm_enabled(d->pcd); ++} ++#endif ++ ++/** ++ * Initiates Session Request Protocol (SRP) to wakeup the host if no ++ * session is in progress. If a session is already in progress, but ++ * the device is suspended, remote wakeup signaling is started. ++ * ++ */ ++static int wakeup(struct usb_gadget *gadget) ++{ ++ struct gadget_wrapper *d; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, gadget); ++ ++ if (gadget == 0) { ++ return -ENODEV; ++ } else { ++ d = container_of(gadget, struct gadget_wrapper, gadget); ++ } ++ dwc_otg_pcd_wakeup(d->pcd); ++ return 0; ++} ++ ++static const struct usb_gadget_ops dwc_otg_pcd_ops = { ++ .get_frame = get_frame_number, ++ .wakeup = wakeup, ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ .lpm_support = test_lpm_enabled, ++#endif ++ // current versions must always be self-powered ++}; ++ ++static int _setup(dwc_otg_pcd_t * pcd, uint8_t * bytes) ++{ ++ int retval = -DWC_E_NOT_SUPPORTED; ++ if (gadget_wrapper->driver && gadget_wrapper->driver->setup) { ++ retval = gadget_wrapper->driver->setup(&gadget_wrapper->gadget, ++ (struct usb_ctrlrequest ++ *)bytes); ++ } ++ ++ if (retval == -ENOTSUPP) { ++ retval = -DWC_E_NOT_SUPPORTED; ++ } else if (retval < 0) { ++ retval = -DWC_E_INVALID; ++ } ++ ++ return retval; ++} ++ ++#ifdef DWC_EN_ISOC ++static int _isoc_complete(dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *req_handle, int proc_buf_num) ++{ ++ int i, packet_count; ++ struct usb_gadget_iso_packet_descriptor *iso_packet = 0; ++ struct usb_iso_request *iso_req = req_handle; ++ ++ if (proc_buf_num) { ++ iso_packet = iso_req->iso_packet_desc1; ++ } else { ++ iso_packet = iso_req->iso_packet_desc0; ++ } ++ packet_count = ++ dwc_otg_pcd_get_iso_packet_count(pcd, ep_handle, req_handle); ++ for (i = 0; i < packet_count; ++i) { ++ int status; ++ int actual; ++ int offset; ++ dwc_otg_pcd_get_iso_packet_params(pcd, ep_handle, req_handle, ++ i, &status, &actual, &offset); ++ switch (status) { ++ case -DWC_E_NO_DATA: ++ status = -ENODATA; ++ break; ++ default: ++ if (status) { ++ DWC_PRINTF("unknown status in isoc packet\n"); ++ } ++ ++ } ++ iso_packet[i].status = status; ++ iso_packet[i].offset = offset; ++ iso_packet[i].actual_length = actual; ++ } ++ ++ iso_req->status = 0; ++ iso_req->process_buffer(ep_handle, iso_req); ++ ++ return 0; ++} ++#endif /* DWC_EN_ISOC */ ++ ++#ifdef DWC_UTE_PER_IO ++/** ++ * Copy the contents of the extended request to the Linux usb_request's ++ * extended part and call the gadget's completion. ++ * ++ * @param pcd Pointer to the pcd structure ++ * @param ep_handle Void pointer to the usb_ep structure ++ * @param req_handle Void pointer to the usb_request structure ++ * @param status Request status returned from the portable logic ++ * @param ereq_port Void pointer to the extended request structure ++ * created in the the portable part that contains the ++ * results of the processed iso packets. ++ */ ++static int _xisoc_complete(dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *req_handle, int32_t status, void *ereq_port) ++{ ++ struct dwc_ute_iso_req_ext *ereqorg = NULL; ++ struct dwc_iso_xreq_port *ereqport = NULL; ++ struct dwc_ute_iso_packet_descriptor *desc_org = NULL; ++ int i; ++ struct usb_request *req; ++ //struct dwc_ute_iso_packet_descriptor * ++ //int status = 0; ++ ++ req = (struct usb_request *)req_handle; ++ ereqorg = &req->ext_req; ++ ereqport = (struct dwc_iso_xreq_port *)ereq_port; ++ desc_org = ereqorg->per_io_frame_descs; ++ ++ if (req && req->complete) { ++ /* Copy the request data from the portable logic to our request */ ++ for (i = 0; i < ereqport->pio_pkt_count; i++) { ++ desc_org[i].actual_length = ++ ereqport->per_io_frame_descs[i].actual_length; ++ desc_org[i].status = ++ ereqport->per_io_frame_descs[i].status; ++ } ++ ++ switch (status) { ++ case -DWC_E_SHUTDOWN: ++ req->status = -ESHUTDOWN; ++ break; ++ case -DWC_E_RESTART: ++ req->status = -ECONNRESET; ++ break; ++ case -DWC_E_INVALID: ++ req->status = -EINVAL; ++ break; ++ case -DWC_E_TIMEOUT: ++ req->status = -ETIMEDOUT; ++ break; ++ default: ++ req->status = status; ++ } ++ ++ /* And call the gadget's completion */ ++ req->complete(ep_handle, req); ++ } ++ ++ return 0; ++} ++#endif /* DWC_UTE_PER_IO */ ++ ++static int _complete(dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *req_handle, int32_t status, uint32_t actual) ++{ ++ struct usb_request *req = (struct usb_request *)req_handle; ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27) ++ struct dwc_otg_pcd_ep *ep = NULL; ++#endif ++ ++ if (req && req->complete) { ++ switch (status) { ++ case -DWC_E_SHUTDOWN: ++ req->status = -ESHUTDOWN; ++ break; ++ case -DWC_E_RESTART: ++ req->status = -ECONNRESET; ++ break; ++ case -DWC_E_INVALID: ++ req->status = -EINVAL; ++ break; ++ case -DWC_E_TIMEOUT: ++ req->status = -ETIMEDOUT; ++ break; ++ default: ++ req->status = status; ++ ++ } ++ ++ req->actual = actual; ++ DWC_SPINUNLOCK(pcd->lock); ++ req->complete(ep_handle, req); ++ DWC_SPINLOCK(pcd->lock); ++ } ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27) ++ ep = ep_from_handle(pcd, ep_handle); ++ if (GET_CORE_IF(pcd)->dma_enable) { ++ if (req->length != 0) { ++ dwc_otg_device_t *otg_dev = gadget_wrapper->pcd->otg_dev; ++ struct device *dev = NULL; ++ ++ if (otg_dev != NULL) ++ dev = DWC_OTG_OS_GETDEV(otg_dev->os_dep); ++ ++ dma_unmap_single(dev, req->dma, req->length, ++ ep->dwc_ep.is_in ? ++ DMA_TO_DEVICE: DMA_FROM_DEVICE); ++ } ++ } ++#endif ++ ++ return 0; ++} ++ ++static int _connect(dwc_otg_pcd_t * pcd, int speed) ++{ ++ gadget_wrapper->gadget.speed = speed; ++ return 0; ++} ++ ++static int _disconnect(dwc_otg_pcd_t * pcd) ++{ ++ if (gadget_wrapper->driver && gadget_wrapper->driver->disconnect) { ++ gadget_wrapper->driver->disconnect(&gadget_wrapper->gadget); ++ } ++ return 0; ++} ++ ++static int _resume(dwc_otg_pcd_t * pcd) ++{ ++ if (gadget_wrapper->driver && gadget_wrapper->driver->resume) { ++ gadget_wrapper->driver->resume(&gadget_wrapper->gadget); ++ } ++ ++ return 0; ++} ++ ++static int _suspend(dwc_otg_pcd_t * pcd) ++{ ++ if (gadget_wrapper->driver && gadget_wrapper->driver->suspend) { ++ gadget_wrapper->driver->suspend(&gadget_wrapper->gadget); ++ } ++ return 0; ++} ++ ++/** ++ * This function updates the otg values in the gadget structure. ++ */ ++static int _hnp_changed(dwc_otg_pcd_t * pcd) ++{ ++ ++ if (!gadget_wrapper->gadget.is_otg) ++ return 0; ++ ++ gadget_wrapper->gadget.b_hnp_enable = get_b_hnp_enable(pcd); ++ gadget_wrapper->gadget.a_hnp_support = get_a_hnp_support(pcd); ++ gadget_wrapper->gadget.a_alt_hnp_support = get_a_alt_hnp_support(pcd); ++ return 0; ++} ++ ++static int _reset(dwc_otg_pcd_t * pcd) ++{ ++ return 0; ++} ++ ++#ifdef DWC_UTE_CFI ++static int _cfi_setup(dwc_otg_pcd_t * pcd, void *cfi_req) ++{ ++ int retval = -DWC_E_INVALID; ++ if (gadget_wrapper->driver->cfi_feature_setup) { ++ retval = ++ gadget_wrapper->driver-> ++ cfi_feature_setup(&gadget_wrapper->gadget, ++ (struct cfi_usb_ctrlrequest *)cfi_req); ++ } ++ ++ return retval; ++} ++#endif ++ ++static const struct dwc_otg_pcd_function_ops fops = { ++ .complete = _complete, ++#ifdef DWC_EN_ISOC ++ .isoc_complete = _isoc_complete, ++#endif ++ .setup = _setup, ++ .disconnect = _disconnect, ++ .connect = _connect, ++ .resume = _resume, ++ .suspend = _suspend, ++ .hnp_changed = _hnp_changed, ++ .reset = _reset, ++#ifdef DWC_UTE_CFI ++ .cfi_setup = _cfi_setup, ++#endif ++#ifdef DWC_UTE_PER_IO ++ .xisoc_complete = _xisoc_complete, ++#endif ++}; ++ ++/** ++ * This function is the top level PCD interrupt handler. ++ */ ++static irqreturn_t dwc_otg_pcd_irq(int irq, void *dev) ++{ ++ dwc_otg_pcd_t *pcd = dev; ++ int32_t retval = IRQ_NONE; ++ ++ retval = dwc_otg_pcd_handle_intr(pcd); ++ if (retval != 0) { ++ S3C2410X_CLEAR_EINTPEND(); ++ } ++ return IRQ_RETVAL(retval); ++} ++ ++/** ++ * This function initialized the usb_ep structures to there default ++ * state. ++ * ++ * @param d Pointer on gadget_wrapper. ++ */ ++void gadget_add_eps(struct gadget_wrapper *d) ++{ ++ static const char *names[] = { ++ ++ "ep0", ++ "ep1in", ++ "ep2in", ++ "ep3in", ++ "ep4in", ++ "ep5in", ++ "ep6in", ++ "ep7in", ++ "ep8in", ++ "ep9in", ++ "ep10in", ++ "ep11in", ++ "ep12in", ++ "ep13in", ++ "ep14in", ++ "ep15in", ++ "ep1out", ++ "ep2out", ++ "ep3out", ++ "ep4out", ++ "ep5out", ++ "ep6out", ++ "ep7out", ++ "ep8out", ++ "ep9out", ++ "ep10out", ++ "ep11out", ++ "ep12out", ++ "ep13out", ++ "ep14out", ++ "ep15out" ++ }; ++ ++ int i; ++ struct usb_ep *ep; ++ int8_t dev_endpoints; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s\n", __func__); ++ ++ INIT_LIST_HEAD(&d->gadget.ep_list); ++ d->gadget.ep0 = &d->ep0; ++ d->gadget.speed = USB_SPEED_UNKNOWN; ++ ++ INIT_LIST_HEAD(&d->gadget.ep0->ep_list); ++ ++ /** ++ * Initialize the EP0 structure. ++ */ ++ ep = &d->ep0; ++ ++ /* Init the usb_ep structure. */ ++ ep->name = names[0]; ++ ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops; ++ ++ /** ++ * @todo NGS: What should the max packet size be set to ++ * here? Before EP type is set? ++ */ ++ ep->maxpacket = MAX_PACKET_SIZE; ++ dwc_otg_pcd_ep_enable(d->pcd, NULL, ep); ++ ++ list_add_tail(&ep->ep_list, &d->gadget.ep_list); ++ ++ /** ++ * Initialize the EP structures. ++ */ ++ dev_endpoints = d->pcd->core_if->dev_if->num_in_eps; ++ ++ for (i = 0; i < dev_endpoints; i++) { ++ ep = &d->in_ep[i]; ++ ++ /* Init the usb_ep structure. */ ++ ep->name = names[d->pcd->in_ep[i].dwc_ep.num]; ++ ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops; ++ ++ /** ++ * @todo NGS: What should the max packet size be set to ++ * here? Before EP type is set? ++ */ ++ ep->maxpacket = MAX_PACKET_SIZE; ++ list_add_tail(&ep->ep_list, &d->gadget.ep_list); ++ } ++ ++ dev_endpoints = d->pcd->core_if->dev_if->num_out_eps; ++ ++ for (i = 0; i < dev_endpoints; i++) { ++ ep = &d->out_ep[i]; ++ ++ /* Init the usb_ep structure. */ ++ ep->name = names[15 + d->pcd->out_ep[i].dwc_ep.num]; ++ ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops; ++ ++ /** ++ * @todo NGS: What should the max packet size be set to ++ * here? Before EP type is set? ++ */ ++ ep->maxpacket = MAX_PACKET_SIZE; ++ ++ list_add_tail(&ep->ep_list, &d->gadget.ep_list); ++ } ++ ++ /* remove ep0 from the list. There is a ep0 pointer. */ ++ list_del_init(&d->ep0.ep_list); ++ ++ d->ep0.maxpacket = MAX_EP0_SIZE; ++} ++ ++/** ++ * This function releases the Gadget device. ++ * required by device_unregister(). ++ * ++ * @todo Should this do something? Should it free the PCD? ++ */ ++static void dwc_otg_pcd_gadget_release(struct device *dev) ++{ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, dev); ++} ++ ++static struct gadget_wrapper *alloc_wrapper(dwc_bus_dev_t *_dev) ++{ ++ static char pcd_name[] = "dwc_otg_pcd"; ++ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev); ++ struct gadget_wrapper *d; ++ int retval; ++ ++ d = DWC_ALLOC(sizeof(*d)); ++ if (d == NULL) { ++ return NULL; ++ } ++ ++ memset(d, 0, sizeof(*d)); ++ ++ d->gadget.name = pcd_name; ++ d->pcd = otg_dev->pcd; ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) ++ strcpy(d->gadget.dev.bus_id, "gadget"); ++#else ++ dev_set_name(&d->gadget.dev, "%s", "gadget"); ++#endif ++ ++ d->gadget.dev.parent = &_dev->dev; ++ d->gadget.dev.release = dwc_otg_pcd_gadget_release; ++ d->gadget.ops = &dwc_otg_pcd_ops; ++ d->gadget.max_speed = dwc_otg_pcd_is_dualspeed(otg_dev->pcd) ? USB_SPEED_HIGH:USB_SPEED_FULL; ++ d->gadget.is_otg = dwc_otg_pcd_is_otg(otg_dev->pcd); ++ ++ d->driver = 0; ++ /* Register the gadget device */ ++ retval = device_register(&d->gadget.dev); ++ if (retval != 0) { ++ DWC_ERROR("device_register failed\n"); ++ DWC_FREE(d); ++ return NULL; ++ } ++ ++ return d; ++} ++ ++static void free_wrapper(struct gadget_wrapper *d) ++{ ++ if (d->driver) { ++ /* should have been done already by driver model core */ ++ DWC_WARN("driver '%s' is still registered\n", ++ d->driver->driver.name); ++ usb_gadget_unregister_driver(d->driver); ++ } ++ ++ device_unregister(&d->gadget.dev); ++ DWC_FREE(d); ++} ++ ++/** ++ * This function initialized the PCD portion of the driver. ++ * ++ */ ++int pcd_init(dwc_bus_dev_t *_dev) ++{ ++ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev); ++ int retval = 0; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p) otg_dev=%p\n", __func__, _dev, otg_dev); ++ ++ otg_dev->pcd = dwc_otg_pcd_init(otg_dev->core_if); ++ ++ if (!otg_dev->pcd) { ++ DWC_ERROR("dwc_otg_pcd_init failed\n"); ++ return -ENOMEM; ++ } ++ ++ otg_dev->pcd->otg_dev = otg_dev; ++ gadget_wrapper = alloc_wrapper(_dev); ++ ++ /* ++ * Initialize EP structures ++ */ ++ gadget_add_eps(gadget_wrapper); ++ /* ++ * Setup interupt handler ++ */ ++#ifdef PLATFORM_INTERFACE ++ DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n", ++ platform_get_irq(_dev, fiq_enable ? 0 : 1)); ++ retval = request_irq(platform_get_irq(_dev, fiq_enable ? 0 : 1), dwc_otg_pcd_irq, ++ IRQF_SHARED, gadget_wrapper->gadget.name, ++ otg_dev->pcd); ++ if (retval != 0) { ++ DWC_ERROR("request of irq%d failed\n", ++ platform_get_irq(_dev, fiq_enable ? 0 : 1)); ++ free_wrapper(gadget_wrapper); ++ return -EBUSY; ++ } ++#else ++ DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n", ++ _dev->irq); ++ retval = request_irq(_dev->irq, dwc_otg_pcd_irq, ++ IRQF_SHARED | IRQF_DISABLED, ++ gadget_wrapper->gadget.name, otg_dev->pcd); ++ if (retval != 0) { ++ DWC_ERROR("request of irq%d failed\n", _dev->irq); ++ free_wrapper(gadget_wrapper); ++ return -EBUSY; ++ } ++#endif ++ ++ dwc_otg_pcd_start(gadget_wrapper->pcd, &fops); ++ ++ return retval; ++} ++ ++/** ++ * Cleanup the PCD. ++ */ ++void pcd_remove(dwc_bus_dev_t *_dev) ++{ ++ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev); ++ dwc_otg_pcd_t *pcd = otg_dev->pcd; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p) otg_dev %p\n", __func__, _dev, otg_dev); ++ ++ /* ++ * Free the IRQ ++ */ ++#ifdef PLATFORM_INTERFACE ++ free_irq(platform_get_irq(_dev, 0), pcd); ++#else ++ free_irq(_dev->irq, pcd); ++#endif ++ dwc_otg_pcd_remove(otg_dev->pcd); ++ free_wrapper(gadget_wrapper); ++ otg_dev->pcd = 0; ++} ++ ++/** ++ * This function registers a gadget driver with the PCD. ++ * ++ * When a driver is successfully registered, it will receive control ++ * requests including set_configuration(), which enables non-control ++ * requests. then usb traffic follows until a disconnect is reported. ++ * then a host may connect again, or the driver might get unbound. ++ * ++ * @param driver The driver being registered ++ * @param bind The bind function of gadget driver ++ */ ++ ++int usb_gadget_probe_driver(struct usb_gadget_driver *driver) ++{ ++ int retval; ++ ++ DWC_DEBUGPL(DBG_PCD, "registering gadget driver '%s'\n", ++ driver->driver.name); ++ ++ if (!driver || driver->max_speed == USB_SPEED_UNKNOWN || ++ !driver->bind || ++ !driver->unbind || !driver->disconnect || !driver->setup) { ++ DWC_DEBUGPL(DBG_PCDV, "EINVAL\n"); ++ return -EINVAL; ++ } ++ if (gadget_wrapper == 0) { ++ DWC_DEBUGPL(DBG_PCDV, "ENODEV\n"); ++ return -ENODEV; ++ } ++ if (gadget_wrapper->driver != 0) { ++ DWC_DEBUGPL(DBG_PCDV, "EBUSY (%p)\n", gadget_wrapper->driver); ++ return -EBUSY; ++ } ++ ++ /* hook up the driver */ ++ gadget_wrapper->driver = driver; ++ gadget_wrapper->gadget.dev.driver = &driver->driver; ++ ++ DWC_DEBUGPL(DBG_PCD, "bind to driver %s\n", driver->driver.name); ++ retval = driver->bind(&gadget_wrapper->gadget, gadget_wrapper->driver); ++ if (retval) { ++ DWC_ERROR("bind to driver %s --> error %d\n", ++ driver->driver.name, retval); ++ gadget_wrapper->driver = 0; ++ gadget_wrapper->gadget.dev.driver = 0; ++ return retval; ++ } ++ DWC_DEBUGPL(DBG_ANY, "registered gadget driver '%s'\n", ++ driver->driver.name); ++ return 0; ++} ++EXPORT_SYMBOL(usb_gadget_probe_driver); ++ ++/** ++ * This function unregisters a gadget driver ++ * ++ * @param driver The driver being unregistered ++ */ ++int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) ++{ ++ //DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, _driver); ++ ++ if (gadget_wrapper == 0) { ++ DWC_DEBUGPL(DBG_ANY, "%s Return(%d): s_pcd==0\n", __func__, ++ -ENODEV); ++ return -ENODEV; ++ } ++ if (driver == 0 || driver != gadget_wrapper->driver) { ++ DWC_DEBUGPL(DBG_ANY, "%s Return(%d): driver?\n", __func__, ++ -EINVAL); ++ return -EINVAL; ++ } ++ ++ driver->unbind(&gadget_wrapper->gadget); ++ gadget_wrapper->driver = 0; ++ ++ DWC_DEBUGPL(DBG_ANY, "unregistered driver '%s'\n", driver->driver.name); ++ return 0; ++} ++ ++EXPORT_SYMBOL(usb_gadget_unregister_driver); ++ ++#endif /* DWC_HOST_ONLY */ +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_regs.h linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_regs.h +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/dwc_otg_regs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/dwc_otg_regs.h 2015-11-29 09:42:39.923098428 +0100 +@@ -0,0 +1,2550 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $ ++ * $Revision: #98 $ ++ * $Date: 2012/08/10 $ ++ * $Change: 2047372 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++#ifndef __DWC_OTG_REGS_H__ ++#define __DWC_OTG_REGS_H__ ++ ++#include "dwc_otg_core_if.h" ++ ++/** ++ * @file ++ * ++ * This file contains the data structures for accessing the DWC_otg core registers. ++ * ++ * The application interfaces with the HS OTG core by reading from and ++ * writing to the Control and Status Register (CSR) space through the ++ * AHB Slave interface. These registers are 32 bits wide, and the ++ * addresses are 32-bit-block aligned. ++ * CSRs are classified as follows: ++ * - Core Global Registers ++ * - Device Mode Registers ++ * - Device Global Registers ++ * - Device Endpoint Specific Registers ++ * - Host Mode Registers ++ * - Host Global Registers ++ * - Host Port CSRs ++ * - Host Channel Specific Registers ++ * ++ * Only the Core Global registers can be accessed in both Device and ++ * Host modes. When the HS OTG core is operating in one mode, either ++ * Device or Host, the application must not access registers from the ++ * other mode. When the core switches from one mode to another, the ++ * registers in the new mode of operation must be reprogrammed as they ++ * would be after a power-on reset. ++ */ ++ ++/****************************************************************************/ ++/** DWC_otg Core registers . ++ * The dwc_otg_core_global_regs structure defines the size ++ * and relative field offsets for the Core Global registers. ++ */ ++typedef struct dwc_otg_core_global_regs { ++ /** OTG Control and Status Register. Offset: 000h */ ++ volatile uint32_t gotgctl; ++ /** OTG Interrupt Register. Offset: 004h */ ++ volatile uint32_t gotgint; ++ /**Core AHB Configuration Register. Offset: 008h */ ++ volatile uint32_t gahbcfg; ++ ++#define DWC_GLBINTRMASK 0x0001 ++#define DWC_DMAENABLE 0x0020 ++#define DWC_NPTXEMPTYLVL_EMPTY 0x0080 ++#define DWC_NPTXEMPTYLVL_HALFEMPTY 0x0000 ++#define DWC_PTXEMPTYLVL_EMPTY 0x0100 ++#define DWC_PTXEMPTYLVL_HALFEMPTY 0x0000 ++ ++ /**Core USB Configuration Register. Offset: 00Ch */ ++ volatile uint32_t gusbcfg; ++ /**Core Reset Register. Offset: 010h */ ++ volatile uint32_t grstctl; ++ /**Core Interrupt Register. Offset: 014h */ ++ volatile uint32_t gintsts; ++ /**Core Interrupt Mask Register. Offset: 018h */ ++ volatile uint32_t gintmsk; ++ /**Receive Status Queue Read Register (Read Only). Offset: 01Ch */ ++ volatile uint32_t grxstsr; ++ /**Receive Status Queue Read & POP Register (Read Only). Offset: 020h*/ ++ volatile uint32_t grxstsp; ++ /**Receive FIFO Size Register. Offset: 024h */ ++ volatile uint32_t grxfsiz; ++ /**Non Periodic Transmit FIFO Size Register. Offset: 028h */ ++ volatile uint32_t gnptxfsiz; ++ /**Non Periodic Transmit FIFO/Queue Status Register (Read ++ * Only). Offset: 02Ch */ ++ volatile uint32_t gnptxsts; ++ /**I2C Access Register. Offset: 030h */ ++ volatile uint32_t gi2cctl; ++ /**PHY Vendor Control Register. Offset: 034h */ ++ volatile uint32_t gpvndctl; ++ /**General Purpose Input/Output Register. Offset: 038h */ ++ volatile uint32_t ggpio; ++ /**User ID Register. Offset: 03Ch */ ++ volatile uint32_t guid; ++ /**Synopsys ID Register (Read Only). Offset: 040h */ ++ volatile uint32_t gsnpsid; ++ /**User HW Config1 Register (Read Only). Offset: 044h */ ++ volatile uint32_t ghwcfg1; ++ /**User HW Config2 Register (Read Only). Offset: 048h */ ++ volatile uint32_t ghwcfg2; ++#define DWC_SLAVE_ONLY_ARCH 0 ++#define DWC_EXT_DMA_ARCH 1 ++#define DWC_INT_DMA_ARCH 2 ++ ++#define DWC_MODE_HNP_SRP_CAPABLE 0 ++#define DWC_MODE_SRP_ONLY_CAPABLE 1 ++#define DWC_MODE_NO_HNP_SRP_CAPABLE 2 ++#define DWC_MODE_SRP_CAPABLE_DEVICE 3 ++#define DWC_MODE_NO_SRP_CAPABLE_DEVICE 4 ++#define DWC_MODE_SRP_CAPABLE_HOST 5 ++#define DWC_MODE_NO_SRP_CAPABLE_HOST 6 ++ ++ /**User HW Config3 Register (Read Only). Offset: 04Ch */ ++ volatile uint32_t ghwcfg3; ++ /**User HW Config4 Register (Read Only). Offset: 050h*/ ++ volatile uint32_t ghwcfg4; ++ /** Core LPM Configuration register Offset: 054h*/ ++ volatile uint32_t glpmcfg; ++ /** Global PowerDn Register Offset: 058h */ ++ volatile uint32_t gpwrdn; ++ /** Global DFIFO SW Config Register Offset: 05Ch */ ++ volatile uint32_t gdfifocfg; ++ /** ADP Control Register Offset: 060h */ ++ volatile uint32_t adpctl; ++ /** Reserved Offset: 064h-0FFh */ ++ volatile uint32_t reserved39[39]; ++ /** Host Periodic Transmit FIFO Size Register. Offset: 100h */ ++ volatile uint32_t hptxfsiz; ++ /** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled, ++ otherwise Device Transmit FIFO#n Register. ++ * Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15). */ ++ volatile uint32_t dtxfsiz[15]; ++} dwc_otg_core_global_regs_t; ++ ++/** ++ * This union represents the bit fields of the Core OTG Control ++ * and Status Register (GOTGCTL). Set the bits using the bit ++ * fields then write the d32 value to the register. ++ */ ++typedef union gotgctl_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned sesreqscs:1; ++ unsigned sesreq:1; ++ unsigned vbvalidoven:1; ++ unsigned vbvalidovval:1; ++ unsigned avalidoven:1; ++ unsigned avalidovval:1; ++ unsigned bvalidoven:1; ++ unsigned bvalidovval:1; ++ unsigned hstnegscs:1; ++ unsigned hnpreq:1; ++ unsigned hstsethnpen:1; ++ unsigned devhnpen:1; ++ unsigned reserved12_15:4; ++ unsigned conidsts:1; ++ unsigned dbnctime:1; ++ unsigned asesvld:1; ++ unsigned bsesvld:1; ++ unsigned otgver:1; ++ unsigned reserved1:1; ++ unsigned multvalidbc:5; ++ unsigned chirpen:1; ++ unsigned reserved28_31:4; ++ } b; ++} gotgctl_data_t; ++ ++/** ++ * This union represents the bit fields of the Core OTG Interrupt Register ++ * (GOTGINT). Set/clear the bits using the bit fields then write the d32 ++ * value to the register. ++ */ ++typedef union gotgint_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Current Mode */ ++ unsigned reserved0_1:2; ++ ++ /** Session End Detected */ ++ unsigned sesenddet:1; ++ ++ unsigned reserved3_7:5; ++ ++ /** Session Request Success Status Change */ ++ unsigned sesreqsucstschng:1; ++ /** Host Negotiation Success Status Change */ ++ unsigned hstnegsucstschng:1; ++ ++ unsigned reserved10_16:7; ++ ++ /** Host Negotiation Detected */ ++ unsigned hstnegdet:1; ++ /** A-Device Timeout Change */ ++ unsigned adevtoutchng:1; ++ /** Debounce Done */ ++ unsigned debdone:1; ++ /** Multi-Valued input changed */ ++ unsigned mvic:1; ++ ++ unsigned reserved31_21:11; ++ ++ } b; ++} gotgint_data_t; ++ ++/** ++ * This union represents the bit fields of the Core AHB Configuration ++ * Register (GAHBCFG). Set/clear the bits using the bit fields then ++ * write the d32 value to the register. ++ */ ++typedef union gahbcfg_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned glblintrmsk:1; ++#define DWC_GAHBCFG_GLBINT_ENABLE 1 ++ ++ unsigned hburstlen:4; ++#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0 ++#define DWC_GAHBCFG_INT_DMA_BURST_INCR 1 ++#define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3 ++#define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5 ++#define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7 ++ ++ unsigned dmaenable:1; ++#define DWC_GAHBCFG_DMAENABLE 1 ++ unsigned reserved:1; ++ unsigned nptxfemplvl_txfemplvl:1; ++ unsigned ptxfemplvl:1; ++#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY 1 ++#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0 ++ unsigned reserved9_20:12; ++ unsigned remmemsupp:1; ++ unsigned notialldmawrit:1; ++ unsigned ahbsingle:1; ++ unsigned reserved24_31:8; ++ } b; ++} gahbcfg_data_t; ++ ++/** ++ * This union represents the bit fields of the Core USB Configuration ++ * Register (GUSBCFG). Set the bits using the bit fields then write ++ * the d32 value to the register. ++ */ ++typedef union gusbcfg_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned toutcal:3; ++ unsigned phyif:1; ++ unsigned ulpi_utmi_sel:1; ++ unsigned fsintf:1; ++ unsigned physel:1; ++ unsigned ddrsel:1; ++ unsigned srpcap:1; ++ unsigned hnpcap:1; ++ unsigned usbtrdtim:4; ++ unsigned reserved1:1; ++ unsigned phylpwrclksel:1; ++ unsigned otgutmifssel:1; ++ unsigned ulpi_fsls:1; ++ unsigned ulpi_auto_res:1; ++ unsigned ulpi_clk_sus_m:1; ++ unsigned ulpi_ext_vbus_drv:1; ++ unsigned ulpi_int_vbus_indicator:1; ++ unsigned term_sel_dl_pulse:1; ++ unsigned indicator_complement:1; ++ unsigned indicator_pass_through:1; ++ unsigned ulpi_int_prot_dis:1; ++ unsigned ic_usb_cap:1; ++ unsigned ic_traffic_pull_remove:1; ++ unsigned tx_end_delay:1; ++ unsigned force_host_mode:1; ++ unsigned force_dev_mode:1; ++ unsigned reserved31:1; ++ } b; ++} gusbcfg_data_t; ++ ++/** ++ * This union represents the bit fields of the Core Reset Register ++ * (GRSTCTL). Set/clear the bits using the bit fields then write the ++ * d32 value to the register. ++ */ ++typedef union grstctl_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Core Soft Reset (CSftRst) (Device and Host) ++ * ++ * The application can flush the control logic in the ++ * entire core using this bit. This bit resets the ++ * pipelines in the AHB Clock domain as well as the ++ * PHY Clock domain. ++ * ++ * The state machines are reset to an IDLE state, the ++ * control bits in the CSRs are cleared, all the ++ * transmit FIFOs and the receive FIFO are flushed. ++ * ++ * The status mask bits that control the generation of ++ * the interrupt, are cleared, to clear the ++ * interrupt. The interrupt status bits are not ++ * cleared, so the application can get the status of ++ * any events that occurred in the core after it has ++ * set this bit. ++ * ++ * Any transactions on the AHB are terminated as soon ++ * as possible following the protocol. Any ++ * transactions on the USB are terminated immediately. ++ * ++ * The configuration settings in the CSRs are ++ * unchanged, so the software doesn't have to ++ * reprogram these registers (Device ++ * Configuration/Host Configuration/Core System ++ * Configuration/Core PHY Configuration). ++ * ++ * The application can write to this bit, any time it ++ * wants to reset the core. This is a self clearing ++ * bit and the core clears this bit after all the ++ * necessary logic is reset in the core, which may ++ * take several clocks, depending on the current state ++ * of the core. ++ */ ++ unsigned csftrst:1; ++ /** Hclk Soft Reset ++ * ++ * The application uses this bit to reset the control logic in ++ * the AHB clock domain. Only AHB clock domain pipelines are ++ * reset. ++ */ ++ unsigned hsftrst:1; ++ /** Host Frame Counter Reset (Host Only)
++ * ++ * The application can reset the (micro)frame number ++ * counter inside the core, using this bit. When the ++ * (micro)frame counter is reset, the subsequent SOF ++ * sent out by the core, will have a (micro)frame ++ * number of 0. ++ */ ++ unsigned hstfrm:1; ++ /** In Token Sequence Learning Queue Flush ++ * (INTknQFlsh) (Device Only) ++ */ ++ unsigned intknqflsh:1; ++ /** RxFIFO Flush (RxFFlsh) (Device and Host) ++ * ++ * The application can flush the entire Receive FIFO ++ * using this bit. The application must first ++ * ensure that the core is not in the middle of a ++ * transaction. The application should write into ++ * this bit, only after making sure that neither the ++ * DMA engine is reading from the RxFIFO nor the MAC ++ * is writing the data in to the FIFO. The ++ * application should wait until the bit is cleared ++ * before performing any other operations. This bit ++ * will takes 8 clocks (slowest of PHY or AHB clock) ++ * to clear. ++ */ ++ unsigned rxfflsh:1; ++ /** TxFIFO Flush (TxFFlsh) (Device and Host). ++ * ++ * This bit is used to selectively flush a single or ++ * all transmit FIFOs. The application must first ++ * ensure that the core is not in the middle of a ++ * transaction. The application should write into ++ * this bit, only after making sure that neither the ++ * DMA engine is writing into the TxFIFO nor the MAC ++ * is reading the data out of the FIFO. The ++ * application should wait until the core clears this ++ * bit, before performing any operations. This bit ++ * will takes 8 clocks (slowest of PHY or AHB clock) ++ * to clear. ++ */ ++ unsigned txfflsh:1; ++ ++ /** TxFIFO Number (TxFNum) (Device and Host). ++ * ++ * This is the FIFO number which needs to be flushed, ++ * using the TxFIFO Flush bit. This field should not ++ * be changed until the TxFIFO Flush bit is cleared by ++ * the core. ++ * - 0x0 : Non Periodic TxFIFO Flush ++ * - 0x1 : Periodic TxFIFO #1 Flush in device mode ++ * or Periodic TxFIFO in host mode ++ * - 0x2 : Periodic TxFIFO #2 Flush in device mode. ++ * - ... ++ * - 0xF : Periodic TxFIFO #15 Flush in device mode ++ * - 0x10: Flush all the Transmit NonPeriodic and ++ * Transmit Periodic FIFOs in the core ++ */ ++ unsigned txfnum:5; ++ /** Reserved */ ++ unsigned reserved11_29:19; ++ /** DMA Request Signal. Indicated DMA request is in ++ * probress. Used for debug purpose. */ ++ unsigned dmareq:1; ++ /** AHB Master Idle. Indicates the AHB Master State ++ * Machine is in IDLE condition. */ ++ unsigned ahbidle:1; ++ } b; ++} grstctl_t; ++ ++/** ++ * This union represents the bit fields of the Core Interrupt Mask ++ * Register (GINTMSK). Set/clear the bits using the bit fields then ++ * write the d32 value to the register. ++ */ ++typedef union gintmsk_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned reserved0:1; ++ unsigned modemismatch:1; ++ unsigned otgintr:1; ++ unsigned sofintr:1; ++ unsigned rxstsqlvl:1; ++ unsigned nptxfempty:1; ++ unsigned ginnakeff:1; ++ unsigned goutnakeff:1; ++ unsigned ulpickint:1; ++ unsigned i2cintr:1; ++ unsigned erlysuspend:1; ++ unsigned usbsuspend:1; ++ unsigned usbreset:1; ++ unsigned enumdone:1; ++ unsigned isooutdrop:1; ++ unsigned eopframe:1; ++ unsigned restoredone:1; ++ unsigned epmismatch:1; ++ unsigned inepintr:1; ++ unsigned outepintr:1; ++ unsigned incomplisoin:1; ++ unsigned incomplisoout:1; ++ unsigned fetsusp:1; ++ unsigned resetdet:1; ++ unsigned portintr:1; ++ unsigned hcintr:1; ++ unsigned ptxfempty:1; ++ unsigned lpmtranrcvd:1; ++ unsigned conidstschng:1; ++ unsigned disconnect:1; ++ unsigned sessreqintr:1; ++ unsigned wkupintr:1; ++ } b; ++} gintmsk_data_t; ++/** ++ * This union represents the bit fields of the Core Interrupt Register ++ * (GINTSTS). Set/clear the bits using the bit fields then write the ++ * d32 value to the register. ++ */ ++typedef union gintsts_data { ++ /** raw register data */ ++ uint32_t d32; ++#define DWC_SOF_INTR_MASK 0x0008 ++ /** register bits */ ++ struct { ++#define DWC_HOST_MODE 1 ++ unsigned curmode:1; ++ unsigned modemismatch:1; ++ unsigned otgintr:1; ++ unsigned sofintr:1; ++ unsigned rxstsqlvl:1; ++ unsigned nptxfempty:1; ++ unsigned ginnakeff:1; ++ unsigned goutnakeff:1; ++ unsigned ulpickint:1; ++ unsigned i2cintr:1; ++ unsigned erlysuspend:1; ++ unsigned usbsuspend:1; ++ unsigned usbreset:1; ++ unsigned enumdone:1; ++ unsigned isooutdrop:1; ++ unsigned eopframe:1; ++ unsigned restoredone:1; ++ unsigned epmismatch:1; ++ unsigned inepint:1; ++ unsigned outepintr:1; ++ unsigned incomplisoin:1; ++ unsigned incomplisoout:1; ++ unsigned fetsusp:1; ++ unsigned resetdet:1; ++ unsigned portintr:1; ++ unsigned hcintr:1; ++ unsigned ptxfempty:1; ++ unsigned lpmtranrcvd:1; ++ unsigned conidstschng:1; ++ unsigned disconnect:1; ++ unsigned sessreqintr:1; ++ unsigned wkupintr:1; ++ } b; ++} gintsts_data_t; ++ ++/** ++ * This union represents the bit fields in the Device Receive Status Read and ++ * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 ++ * element then read out the bits using the bit elements. ++ */ ++typedef union device_grxsts_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned epnum:4; ++ unsigned bcnt:11; ++ unsigned dpid:2; ++ ++#define DWC_STS_DATA_UPDT 0x2 // OUT Data Packet ++#define DWC_STS_XFER_COMP 0x3 // OUT Data Transfer Complete ++ ++#define DWC_DSTS_GOUT_NAK 0x1 // Global OUT NAK ++#define DWC_DSTS_SETUP_COMP 0x4 // Setup Phase Complete ++#define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet ++ unsigned pktsts:4; ++ unsigned fn:4; ++ unsigned reserved25_31:7; ++ } b; ++} device_grxsts_data_t; ++ ++/** ++ * This union represents the bit fields in the Host Receive Status Read and ++ * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 ++ * element then read out the bits using the bit elements. ++ */ ++typedef union host_grxsts_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned chnum:4; ++ unsigned bcnt:11; ++ unsigned dpid:2; ++ ++ unsigned pktsts:4; ++#define DWC_GRXSTS_PKTSTS_IN 0x2 ++#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP 0x3 ++#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5 ++#define DWC_GRXSTS_PKTSTS_CH_HALTED 0x7 ++ ++ unsigned reserved21_31:11; ++ } b; ++} host_grxsts_data_t; ++ ++/** ++ * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, ++ * GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). Read the register into the d32 element ++ * then read out the bits using the bit elements. ++ */ ++typedef union fifosize_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned startaddr:16; ++ unsigned depth:16; ++ } b; ++} fifosize_data_t; ++ ++/** ++ * This union represents the bit fields in the Non-Periodic Transmit ++ * FIFO/Queue Status Register (GNPTXSTS). Read the register into the ++ * d32 element then read out the bits using the bit ++ * elements. ++ */ ++typedef union gnptxsts_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned nptxfspcavail:16; ++ unsigned nptxqspcavail:8; ++ /** Top of the Non-Periodic Transmit Request Queue ++ * - bit 24 - Terminate (Last entry for the selected ++ * channel/EP) ++ * - bits 26:25 - Token Type ++ * - 2'b00 - IN/OUT ++ * - 2'b01 - Zero Length OUT ++ * - 2'b10 - PING/Complete Split ++ * - 2'b11 - Channel Halt ++ * - bits 30:27 - Channel/EP Number ++ */ ++ unsigned nptxqtop_terminate:1; ++ unsigned nptxqtop_token:2; ++ unsigned nptxqtop_chnep:4; ++ unsigned reserved:1; ++ } b; ++} gnptxsts_data_t; ++ ++/** ++ * This union represents the bit fields in the Transmit ++ * FIFO Status Register (DTXFSTS). Read the register into the ++ * d32 element then read out the bits using the bit ++ * elements. ++ */ ++typedef union dtxfsts_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned txfspcavail:16; ++ unsigned reserved:16; ++ } b; ++} dtxfsts_data_t; ++ ++/** ++ * This union represents the bit fields in the I2C Control Register ++ * (I2CCTL). Read the register into the d32 element then read out the ++ * bits using the bit elements. ++ */ ++typedef union gi2cctl_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned rwdata:8; ++ unsigned regaddr:8; ++ unsigned addr:7; ++ unsigned i2cen:1; ++ unsigned ack:1; ++ unsigned i2csuspctl:1; ++ unsigned i2cdevaddr:2; ++ unsigned i2cdatse0:1; ++ unsigned reserved:1; ++ unsigned rw:1; ++ unsigned bsydne:1; ++ } b; ++} gi2cctl_data_t; ++ ++/** ++ * This union represents the bit fields in the PHY Vendor Control Register ++ * (GPVNDCTL). Read the register into the d32 element then read out the ++ * bits using the bit elements. ++ */ ++typedef union gpvndctl_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned regdata:8; ++ unsigned vctrl:8; ++ unsigned regaddr16_21:6; ++ unsigned regwr:1; ++ unsigned reserved23_24:2; ++ unsigned newregreq:1; ++ unsigned vstsbsy:1; ++ unsigned vstsdone:1; ++ unsigned reserved28_30:3; ++ unsigned disulpidrvr:1; ++ } b; ++} gpvndctl_data_t; ++ ++/** ++ * This union represents the bit fields in the General Purpose ++ * Input/Output Register (GGPIO). ++ * Read the register into the d32 element then read out the ++ * bits using the bit elements. ++ */ ++typedef union ggpio_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned gpi:16; ++ unsigned gpo:16; ++ } b; ++} ggpio_data_t; ++ ++/** ++ * This union represents the bit fields in the User ID Register ++ * (GUID). Read the register into the d32 element then read out the ++ * bits using the bit elements. ++ */ ++typedef union guid_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned rwdata:32; ++ } b; ++} guid_data_t; ++ ++/** ++ * This union represents the bit fields in the Synopsys ID Register ++ * (GSNPSID). Read the register into the d32 element then read out the ++ * bits using the bit elements. ++ */ ++typedef union gsnpsid_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned rwdata:32; ++ } b; ++} gsnpsid_data_t; ++ ++/** ++ * This union represents the bit fields in the User HW Config1 ++ * Register. Read the register into the d32 element then read ++ * out the bits using the bit elements. ++ */ ++typedef union hwcfg1_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned ep_dir0:2; ++ unsigned ep_dir1:2; ++ unsigned ep_dir2:2; ++ unsigned ep_dir3:2; ++ unsigned ep_dir4:2; ++ unsigned ep_dir5:2; ++ unsigned ep_dir6:2; ++ unsigned ep_dir7:2; ++ unsigned ep_dir8:2; ++ unsigned ep_dir9:2; ++ unsigned ep_dir10:2; ++ unsigned ep_dir11:2; ++ unsigned ep_dir12:2; ++ unsigned ep_dir13:2; ++ unsigned ep_dir14:2; ++ unsigned ep_dir15:2; ++ } b; ++} hwcfg1_data_t; ++ ++/** ++ * This union represents the bit fields in the User HW Config2 ++ * Register. Read the register into the d32 element then read ++ * out the bits using the bit elements. ++ */ ++typedef union hwcfg2_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /* GHWCFG2 */ ++ unsigned op_mode:3; ++#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0 ++#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1 ++#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2 ++#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3 ++#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4 ++#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5 ++#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6 ++ ++ unsigned architecture:2; ++ unsigned point2point:1; ++ unsigned hs_phy_type:2; ++#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0 ++#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1 ++#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2 ++#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3 ++ ++ unsigned fs_phy_type:2; ++ unsigned num_dev_ep:4; ++ unsigned num_host_chan:4; ++ unsigned perio_ep_supported:1; ++ unsigned dynamic_fifo:1; ++ unsigned multi_proc_int:1; ++ unsigned reserved21:1; ++ unsigned nonperio_tx_q_depth:2; ++ unsigned host_perio_tx_q_depth:2; ++ unsigned dev_token_q_depth:5; ++ unsigned otg_enable_ic_usb:1; ++ } b; ++} hwcfg2_data_t; ++ ++/** ++ * This union represents the bit fields in the User HW Config3 ++ * Register. Read the register into the d32 element then read ++ * out the bits using the bit elements. ++ */ ++typedef union hwcfg3_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /* GHWCFG3 */ ++ unsigned xfer_size_cntr_width:4; ++ unsigned packet_size_cntr_width:3; ++ unsigned otg_func:1; ++ unsigned i2c:1; ++ unsigned vendor_ctrl_if:1; ++ unsigned optional_features:1; ++ unsigned synch_reset_type:1; ++ unsigned adp_supp:1; ++ unsigned otg_enable_hsic:1; ++ unsigned bc_support:1; ++ unsigned otg_lpm_en:1; ++ unsigned dfifo_depth:16; ++ } b; ++} hwcfg3_data_t; ++ ++/** ++ * This union represents the bit fields in the User HW Config4 ++ * Register. Read the register into the d32 element then read ++ * out the bits using the bit elements. ++ */ ++typedef union hwcfg4_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned num_dev_perio_in_ep:4; ++ unsigned power_optimiz:1; ++ unsigned min_ahb_freq:1; ++ unsigned hiber:1; ++ unsigned xhiber:1; ++ unsigned reserved:6; ++ unsigned utmi_phy_data_width:2; ++ unsigned num_dev_mode_ctrl_ep:4; ++ unsigned iddig_filt_en:1; ++ unsigned vbus_valid_filt_en:1; ++ unsigned a_valid_filt_en:1; ++ unsigned b_valid_filt_en:1; ++ unsigned session_end_filt_en:1; ++ unsigned ded_fifo_en:1; ++ unsigned num_in_eps:4; ++ unsigned desc_dma:1; ++ unsigned desc_dma_dyn:1; ++ } b; ++} hwcfg4_data_t; ++ ++/** ++ * This union represents the bit fields of the Core LPM Configuration ++ * Register (GLPMCFG). Set the bits using bit fields then write ++ * the d32 value to the register. ++ */ ++typedef union glpmctl_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** LPM-Capable (LPMCap) (Device and Host) ++ * The application uses this bit to control ++ * the DWC_otg core LPM capabilities. ++ */ ++ unsigned lpm_cap_en:1; ++ /** LPM response programmed by application (AppL1Res) (Device) ++ * Handshake response to LPM token pre-programmed ++ * by device application software. ++ */ ++ unsigned appl_resp:1; ++ /** Host Initiated Resume Duration (HIRD) (Device and Host) ++ * In Host mode this field indicates the value of HIRD ++ * to be sent in an LPM transaction. ++ * In Device mode this field is updated with the ++ * Received LPM Token HIRD bmAttribute ++ * when an ACK/NYET/STALL response is sent ++ * to an LPM transaction. ++ */ ++ unsigned hird:4; ++ /** RemoteWakeEnable (bRemoteWake) (Device and Host) ++ * In Host mode this bit indicates the value of remote ++ * wake up to be sent in wIndex field of LPM transaction. ++ * In Device mode this field is updated with the ++ * Received LPM Token bRemoteWake bmAttribute ++ * when an ACK/NYET/STALL response is sent ++ * to an LPM transaction. ++ */ ++ unsigned rem_wkup_en:1; ++ /** Enable utmi_sleep_n (EnblSlpM) (Device and Host) ++ * The application uses this bit to control ++ * the utmi_sleep_n assertion to the PHY when in L1 state. ++ */ ++ unsigned en_utmi_sleep:1; ++ /** HIRD Threshold (HIRD_Thres) (Device and Host) ++ */ ++ unsigned hird_thres:5; ++ /** LPM Response (CoreL1Res) (Device and Host) ++ * In Host mode this bit contains handsake response to ++ * LPM transaction. ++ * In Device mode the response of the core to ++ * LPM transaction received is reflected in these two bits. ++ - 0x0 : ERROR (No handshake response) ++ - 0x1 : STALL ++ - 0x2 : NYET ++ - 0x3 : ACK ++ */ ++ unsigned lpm_resp:2; ++ /** Port Sleep Status (SlpSts) (Device and Host) ++ * This bit is set as long as a Sleep condition ++ * is present on the USB bus. ++ */ ++ unsigned prt_sleep_sts:1; ++ /** Sleep State Resume OK (L1ResumeOK) (Device and Host) ++ * Indicates that the application or host ++ * can start resume from Sleep state. ++ */ ++ unsigned sleep_state_resumeok:1; ++ /** LPM channel Index (LPM_Chnl_Indx) (Host) ++ * The channel number on which the LPM transaction ++ * has to be applied while sending ++ * an LPM transaction to the local device. ++ */ ++ unsigned lpm_chan_index:4; ++ /** LPM Retry Count (LPM_Retry_Cnt) (Host) ++ * Number host retries that would be performed ++ * if the device response was not valid response. ++ */ ++ unsigned retry_count:3; ++ /** Send LPM Transaction (SndLPM) (Host) ++ * When set by application software, ++ * an LPM transaction containing two tokens ++ * is sent. ++ */ ++ unsigned send_lpm:1; ++ /** LPM Retry status (LPM_RetryCnt_Sts) (Host) ++ * Number of LPM Host Retries still remaining ++ * to be transmitted for the current LPM sequence ++ */ ++ unsigned retry_count_sts:3; ++ unsigned reserved28_29:2; ++ /** In host mode once this bit is set, the host ++ * configures to drive the HSIC Idle state on the bus. ++ * It then waits for the device to initiate the Connect sequence. ++ * In device mode once this bit is set, the device waits for ++ * the HSIC Idle line state on the bus. Upon receving the Idle ++ * line state, it initiates the HSIC Connect sequence. ++ */ ++ unsigned hsic_connect:1; ++ /** This bit overrides and functionally inverts ++ * the if_select_hsic input port signal. ++ */ ++ unsigned inv_sel_hsic:1; ++ } b; ++} glpmcfg_data_t; ++ ++/** ++ * This union represents the bit fields of the Core ADP Timer, Control and ++ * Status Register (ADPTIMCTLSTS). Set the bits using bit fields then write ++ * the d32 value to the register. ++ */ ++typedef union adpctl_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Probe Discharge (PRB_DSCHG) ++ * These bits set the times for TADP_DSCHG. ++ * These bits are defined as follows: ++ * 2'b00 - 4 msec ++ * 2'b01 - 8 msec ++ * 2'b10 - 16 msec ++ * 2'b11 - 32 msec ++ */ ++ unsigned prb_dschg:2; ++ /** Probe Delta (PRB_DELTA) ++ * These bits set the resolution for RTIM value. ++ * The bits are defined in units of 32 kHz clock cycles as follows: ++ * 2'b00 - 1 cycles ++ * 2'b01 - 2 cycles ++ * 2'b10 - 3 cycles ++ * 2'b11 - 4 cycles ++ * For example if this value is chosen to 2'b01, it means that RTIM ++ * increments for every 3(three) 32Khz clock cycles. ++ */ ++ unsigned prb_delta:2; ++ /** Probe Period (PRB_PER) ++ * These bits sets the TADP_PRD as shown in Figure 4 as follows: ++ * 2'b00 - 0.625 to 0.925 sec (typical 0.775 sec) ++ * 2'b01 - 1.25 to 1.85 sec (typical 1.55 sec) ++ * 2'b10 - 1.9 to 2.6 sec (typical 2.275 sec) ++ * 2'b11 - Reserved ++ */ ++ unsigned prb_per:2; ++ /** These bits capture the latest time it took for VBUS to ramp from ++ * VADP_SINK to VADP_PRB. ++ * 0x000 - 1 cycles ++ * 0x001 - 2 cycles ++ * 0x002 - 3 cycles ++ * etc ++ * 0x7FF - 2048 cycles ++ * A time of 1024 cycles at 32 kHz corresponds to a time of 32 msec. ++ */ ++ unsigned rtim:11; ++ /** Enable Probe (EnaPrb) ++ * When programmed to 1'b1, the core performs a probe operation. ++ * This bit is valid only if OTG_Ver = 1'b1. ++ */ ++ unsigned enaprb:1; ++ /** Enable Sense (EnaSns) ++ * When programmed to 1'b1, the core performs a Sense operation. ++ * This bit is valid only if OTG_Ver = 1'b1. ++ */ ++ unsigned enasns:1; ++ /** ADP Reset (ADPRes) ++ * When set, ADP controller is reset. ++ * This bit is valid only if OTG_Ver = 1'b1. ++ */ ++ unsigned adpres:1; ++ /** ADP Enable (ADPEn) ++ * When set, the core performs either ADP probing or sensing ++ * based on EnaPrb or EnaSns. ++ * This bit is valid only if OTG_Ver = 1'b1. ++ */ ++ unsigned adpen:1; ++ /** ADP Probe Interrupt (ADP_PRB_INT) ++ * When this bit is set, it means that the VBUS ++ * voltage is greater than VADP_PRB or VADP_PRB is reached. ++ * This bit is valid only if OTG_Ver = 1'b1. ++ */ ++ unsigned adp_prb_int:1; ++ /** ++ * ADP Sense Interrupt (ADP_SNS_INT) ++ * When this bit is set, it means that the VBUS voltage is greater than ++ * VADP_SNS value or VADP_SNS is reached. ++ * This bit is valid only if OTG_Ver = 1'b1. ++ */ ++ unsigned adp_sns_int:1; ++ /** ADP Tomeout Interrupt (ADP_TMOUT_INT) ++ * This bit is relevant only for an ADP probe. ++ * When this bit is set, it means that the ramp time has ++ * completed ie ADPCTL.RTIM has reached its terminal value ++ * of 0x7FF. This is a debug feature that allows software ++ * to read the ramp time after each cycle. ++ * This bit is valid only if OTG_Ver = 1'b1. ++ */ ++ unsigned adp_tmout_int:1; ++ /** ADP Probe Interrupt Mask (ADP_PRB_INT_MSK) ++ * When this bit is set, it unmasks the interrupt due to ADP_PRB_INT. ++ * This bit is valid only if OTG_Ver = 1'b1. ++ */ ++ unsigned adp_prb_int_msk:1; ++ /** ADP Sense Interrupt Mask (ADP_SNS_INT_MSK) ++ * When this bit is set, it unmasks the interrupt due to ADP_SNS_INT. ++ * This bit is valid only if OTG_Ver = 1'b1. ++ */ ++ unsigned adp_sns_int_msk:1; ++ /** ADP Timoeout Interrupt Mask (ADP_TMOUT_MSK) ++ * When this bit is set, it unmasks the interrupt due to ADP_TMOUT_INT. ++ * This bit is valid only if OTG_Ver = 1'b1. ++ */ ++ unsigned adp_tmout_int_msk:1; ++ /** Access Request ++ * 2'b00 - Read/Write Valid (updated by the core) ++ * 2'b01 - Read ++ * 2'b00 - Write ++ * 2'b00 - Reserved ++ */ ++ unsigned ar:2; ++ /** Reserved */ ++ unsigned reserved29_31:3; ++ } b; ++} adpctl_data_t; ++ ++//////////////////////////////////////////// ++// Device Registers ++/** ++ * Device Global Registers. Offsets 800h-BFFh ++ * ++ * The following structures define the size and relative field offsets ++ * for the Device Mode Registers. ++ * ++ * These registers are visible only in Device mode and must not be ++ * accessed in Host mode, as the results are unknown. ++ */ ++typedef struct dwc_otg_dev_global_regs { ++ /** Device Configuration Register. Offset 800h */ ++ volatile uint32_t dcfg; ++ /** Device Control Register. Offset: 804h */ ++ volatile uint32_t dctl; ++ /** Device Status Register (Read Only). Offset: 808h */ ++ volatile uint32_t dsts; ++ /** Reserved. Offset: 80Ch */ ++ uint32_t unused; ++ /** Device IN Endpoint Common Interrupt Mask ++ * Register. Offset: 810h */ ++ volatile uint32_t diepmsk; ++ /** Device OUT Endpoint Common Interrupt Mask ++ * Register. Offset: 814h */ ++ volatile uint32_t doepmsk; ++ /** Device All Endpoints Interrupt Register. Offset: 818h */ ++ volatile uint32_t daint; ++ /** Device All Endpoints Interrupt Mask Register. Offset: ++ * 81Ch */ ++ volatile uint32_t daintmsk; ++ /** Device IN Token Queue Read Register-1 (Read Only). ++ * Offset: 820h */ ++ volatile uint32_t dtknqr1; ++ /** Device IN Token Queue Read Register-2 (Read Only). ++ * Offset: 824h */ ++ volatile uint32_t dtknqr2; ++ /** Device VBUS discharge Register. Offset: 828h */ ++ volatile uint32_t dvbusdis; ++ /** Device VBUS Pulse Register. Offset: 82Ch */ ++ volatile uint32_t dvbuspulse; ++ /** Device IN Token Queue Read Register-3 (Read Only). / ++ * Device Thresholding control register (Read/Write) ++ * Offset: 830h */ ++ volatile uint32_t dtknqr3_dthrctl; ++ /** Device IN Token Queue Read Register-4 (Read Only). / ++ * Device IN EPs empty Inr. Mask Register (Read/Write) ++ * Offset: 834h */ ++ volatile uint32_t dtknqr4_fifoemptymsk; ++ /** Device Each Endpoint Interrupt Register (Read Only). / ++ * Offset: 838h */ ++ volatile uint32_t deachint; ++ /** Device Each Endpoint Interrupt mask Register (Read/Write). / ++ * Offset: 83Ch */ ++ volatile uint32_t deachintmsk; ++ /** Device Each In Endpoint Interrupt mask Register (Read/Write). / ++ * Offset: 840h */ ++ volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS]; ++ /** Device Each Out Endpoint Interrupt mask Register (Read/Write). / ++ * Offset: 880h */ ++ volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS]; ++} dwc_otg_device_global_regs_t; ++ ++/** ++ * This union represents the bit fields in the Device Configuration ++ * Register. Read the register into the d32 member then ++ * set/clear the bits using the bit elements. Write the ++ * d32 member to the dcfg register. ++ */ ++typedef union dcfg_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Device Speed */ ++ unsigned devspd:2; ++ /** Non Zero Length Status OUT Handshake */ ++ unsigned nzstsouthshk:1; ++#define DWC_DCFG_SEND_STALL 1 ++ ++ unsigned ena32khzs:1; ++ /** Device Addresses */ ++ unsigned devaddr:7; ++ /** Periodic Frame Interval */ ++ unsigned perfrint:2; ++#define DWC_DCFG_FRAME_INTERVAL_80 0 ++#define DWC_DCFG_FRAME_INTERVAL_85 1 ++#define DWC_DCFG_FRAME_INTERVAL_90 2 ++#define DWC_DCFG_FRAME_INTERVAL_95 3 ++ ++ /** Enable Device OUT NAK for bulk in DDMA mode */ ++ unsigned endevoutnak:1; ++ ++ unsigned reserved14_17:4; ++ /** In Endpoint Mis-match count */ ++ unsigned epmscnt:5; ++ /** Enable Descriptor DMA in Device mode */ ++ unsigned descdma:1; ++ unsigned perschintvl:2; ++ unsigned resvalid:6; ++ } b; ++} dcfg_data_t; ++ ++/** ++ * This union represents the bit fields in the Device Control ++ * Register. Read the register into the d32 member then ++ * set/clear the bits using the bit elements. ++ */ ++typedef union dctl_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Remote Wakeup */ ++ unsigned rmtwkupsig:1; ++ /** Soft Disconnect */ ++ unsigned sftdiscon:1; ++ /** Global Non-Periodic IN NAK Status */ ++ unsigned gnpinnaksts:1; ++ /** Global OUT NAK Status */ ++ unsigned goutnaksts:1; ++ /** Test Control */ ++ unsigned tstctl:3; ++ /** Set Global Non-Periodic IN NAK */ ++ unsigned sgnpinnak:1; ++ /** Clear Global Non-Periodic IN NAK */ ++ unsigned cgnpinnak:1; ++ /** Set Global OUT NAK */ ++ unsigned sgoutnak:1; ++ /** Clear Global OUT NAK */ ++ unsigned cgoutnak:1; ++ /** Power-On Programming Done */ ++ unsigned pwronprgdone:1; ++ /** Reserved */ ++ unsigned reserved:1; ++ /** Global Multi Count */ ++ unsigned gmc:2; ++ /** Ignore Frame Number for ISOC EPs */ ++ unsigned ifrmnum:1; ++ /** NAK on Babble */ ++ unsigned nakonbble:1; ++ /** Enable Continue on BNA */ ++ unsigned encontonbna:1; ++ ++ unsigned reserved18_31:14; ++ } b; ++} dctl_data_t; ++ ++/** ++ * This union represents the bit fields in the Device Status ++ * Register. Read the register into the d32 member then ++ * set/clear the bits using the bit elements. ++ */ ++typedef union dsts_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Suspend Status */ ++ unsigned suspsts:1; ++ /** Enumerated Speed */ ++ unsigned enumspd:2; ++#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 ++#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 ++#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ 2 ++#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ 3 ++ /** Erratic Error */ ++ unsigned errticerr:1; ++ unsigned reserved4_7:4; ++ /** Frame or Microframe Number of the received SOF */ ++ unsigned soffn:14; ++ unsigned reserved22_31:10; ++ } b; ++} dsts_data_t; ++ ++/** ++ * This union represents the bit fields in the Device IN EP Interrupt ++ * Register and the Device IN EP Common Mask Register. ++ * ++ * - Read the register into the d32 member then set/clear the ++ * bits using the bit elements. ++ */ ++typedef union diepint_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Transfer complete mask */ ++ unsigned xfercompl:1; ++ /** Endpoint disable mask */ ++ unsigned epdisabled:1; ++ /** AHB Error mask */ ++ unsigned ahberr:1; ++ /** TimeOUT Handshake mask (non-ISOC EPs) */ ++ unsigned timeout:1; ++ /** IN Token received with TxF Empty mask */ ++ unsigned intktxfemp:1; ++ /** IN Token Received with EP mismatch mask */ ++ unsigned intknepmis:1; ++ /** IN Endpoint NAK Effective mask */ ++ unsigned inepnakeff:1; ++ /** Reserved */ ++ unsigned emptyintr:1; ++ ++ unsigned txfifoundrn:1; ++ ++ /** BNA Interrupt mask */ ++ unsigned bna:1; ++ ++ unsigned reserved10_12:3; ++ /** BNA Interrupt mask */ ++ unsigned nak:1; ++ ++ unsigned reserved14_31:18; ++ } b; ++} diepint_data_t; ++ ++/** ++ * This union represents the bit fields in the Device IN EP ++ * Common/Dedicated Interrupt Mask Register. ++ */ ++typedef union diepint_data diepmsk_data_t; ++ ++/** ++ * This union represents the bit fields in the Device OUT EP Interrupt ++ * Registerand Device OUT EP Common Interrupt Mask Register. ++ * ++ * - Read the register into the d32 member then set/clear the ++ * bits using the bit elements. ++ */ ++typedef union doepint_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Transfer complete */ ++ unsigned xfercompl:1; ++ /** Endpoint disable */ ++ unsigned epdisabled:1; ++ /** AHB Error */ ++ unsigned ahberr:1; ++ /** Setup Phase Done (contorl EPs) */ ++ unsigned setup:1; ++ /** OUT Token Received when Endpoint Disabled */ ++ unsigned outtknepdis:1; ++ ++ unsigned stsphsercvd:1; ++ /** Back-to-Back SETUP Packets Received */ ++ unsigned back2backsetup:1; ++ ++ unsigned reserved7:1; ++ /** OUT packet Error */ ++ unsigned outpkterr:1; ++ /** BNA Interrupt */ ++ unsigned bna:1; ++ ++ unsigned reserved10:1; ++ /** Packet Drop Status */ ++ unsigned pktdrpsts:1; ++ /** Babble Interrupt */ ++ unsigned babble:1; ++ /** NAK Interrupt */ ++ unsigned nak:1; ++ /** NYET Interrupt */ ++ unsigned nyet:1; ++ /** Bit indicating setup packet received */ ++ unsigned sr:1; ++ ++ unsigned reserved16_31:16; ++ } b; ++} doepint_data_t; ++ ++/** ++ * This union represents the bit fields in the Device OUT EP ++ * Common/Dedicated Interrupt Mask Register. ++ */ ++typedef union doepint_data doepmsk_data_t; ++ ++/** ++ * This union represents the bit fields in the Device All EP Interrupt ++ * and Mask Registers. ++ * - Read the register into the d32 member then set/clear the ++ * bits using the bit elements. ++ */ ++typedef union daint_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** IN Endpoint bits */ ++ unsigned in:16; ++ /** OUT Endpoint bits */ ++ unsigned out:16; ++ } ep; ++ struct { ++ /** IN Endpoint bits */ ++ unsigned inep0:1; ++ unsigned inep1:1; ++ unsigned inep2:1; ++ unsigned inep3:1; ++ unsigned inep4:1; ++ unsigned inep5:1; ++ unsigned inep6:1; ++ unsigned inep7:1; ++ unsigned inep8:1; ++ unsigned inep9:1; ++ unsigned inep10:1; ++ unsigned inep11:1; ++ unsigned inep12:1; ++ unsigned inep13:1; ++ unsigned inep14:1; ++ unsigned inep15:1; ++ /** OUT Endpoint bits */ ++ unsigned outep0:1; ++ unsigned outep1:1; ++ unsigned outep2:1; ++ unsigned outep3:1; ++ unsigned outep4:1; ++ unsigned outep5:1; ++ unsigned outep6:1; ++ unsigned outep7:1; ++ unsigned outep8:1; ++ unsigned outep9:1; ++ unsigned outep10:1; ++ unsigned outep11:1; ++ unsigned outep12:1; ++ unsigned outep13:1; ++ unsigned outep14:1; ++ unsigned outep15:1; ++ } b; ++} daint_data_t; ++ ++/** ++ * This union represents the bit fields in the Device IN Token Queue ++ * Read Registers. ++ * - Read the register into the d32 member. ++ * - READ-ONLY Register ++ */ ++typedef union dtknq1_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** In Token Queue Write Pointer */ ++ unsigned intknwptr:5; ++ /** Reserved */ ++ unsigned reserved05_06:2; ++ /** write pointer has wrapped. */ ++ unsigned wrap_bit:1; ++ /** EP Numbers of IN Tokens 0 ... 4 */ ++ unsigned epnums0_5:24; ++ } b; ++} dtknq1_data_t; ++ ++/** ++ * This union represents Threshold control Register ++ * - Read and write the register into the d32 member. ++ * - READ-WRITABLE Register ++ */ ++typedef union dthrctl_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** non ISO Tx Thr. Enable */ ++ unsigned non_iso_thr_en:1; ++ /** ISO Tx Thr. Enable */ ++ unsigned iso_thr_en:1; ++ /** Tx Thr. Length */ ++ unsigned tx_thr_len:9; ++ /** AHB Threshold ratio */ ++ unsigned ahb_thr_ratio:2; ++ /** Reserved */ ++ unsigned reserved13_15:3; ++ /** Rx Thr. Enable */ ++ unsigned rx_thr_en:1; ++ /** Rx Thr. Length */ ++ unsigned rx_thr_len:9; ++ unsigned reserved26:1; ++ /** Arbiter Parking Enable*/ ++ unsigned arbprken:1; ++ /** Reserved */ ++ unsigned reserved28_31:4; ++ } b; ++} dthrctl_data_t; ++ ++/** ++ * Device Logical IN Endpoint-Specific Registers. Offsets ++ * 900h-AFCh ++ * ++ * There will be one set of endpoint registers per logical endpoint ++ * implemented. ++ * ++ * These registers are visible only in Device mode and must not be ++ * accessed in Host mode, as the results are unknown. ++ */ ++typedef struct dwc_otg_dev_in_ep_regs { ++ /** Device IN Endpoint Control Register. Offset:900h + ++ * (ep_num * 20h) + 00h */ ++ volatile uint32_t diepctl; ++ /** Reserved. Offset:900h + (ep_num * 20h) + 04h */ ++ uint32_t reserved04; ++ /** Device IN Endpoint Interrupt Register. Offset:900h + ++ * (ep_num * 20h) + 08h */ ++ volatile uint32_t diepint; ++ /** Reserved. Offset:900h + (ep_num * 20h) + 0Ch */ ++ uint32_t reserved0C; ++ /** Device IN Endpoint Transfer Size ++ * Register. Offset:900h + (ep_num * 20h) + 10h */ ++ volatile uint32_t dieptsiz; ++ /** Device IN Endpoint DMA Address Register. Offset:900h + ++ * (ep_num * 20h) + 14h */ ++ volatile uint32_t diepdma; ++ /** Device IN Endpoint Transmit FIFO Status Register. Offset:900h + ++ * (ep_num * 20h) + 18h */ ++ volatile uint32_t dtxfsts; ++ /** Device IN Endpoint DMA Buffer Register. Offset:900h + ++ * (ep_num * 20h) + 1Ch */ ++ volatile uint32_t diepdmab; ++} dwc_otg_dev_in_ep_regs_t; ++ ++/** ++ * Device Logical OUT Endpoint-Specific Registers. Offsets: ++ * B00h-CFCh ++ * ++ * There will be one set of endpoint registers per logical endpoint ++ * implemented. ++ * ++ * These registers are visible only in Device mode and must not be ++ * accessed in Host mode, as the results are unknown. ++ */ ++typedef struct dwc_otg_dev_out_ep_regs { ++ /** Device OUT Endpoint Control Register. Offset:B00h + ++ * (ep_num * 20h) + 00h */ ++ volatile uint32_t doepctl; ++ /** Reserved. Offset:B00h + (ep_num * 20h) + 04h */ ++ uint32_t reserved04; ++ /** Device OUT Endpoint Interrupt Register. Offset:B00h + ++ * (ep_num * 20h) + 08h */ ++ volatile uint32_t doepint; ++ /** Reserved. Offset:B00h + (ep_num * 20h) + 0Ch */ ++ uint32_t reserved0C; ++ /** Device OUT Endpoint Transfer Size Register. Offset: ++ * B00h + (ep_num * 20h) + 10h */ ++ volatile uint32_t doeptsiz; ++ /** Device OUT Endpoint DMA Address Register. Offset:B00h ++ * + (ep_num * 20h) + 14h */ ++ volatile uint32_t doepdma; ++ /** Reserved. Offset:B00h + * (ep_num * 20h) + 18h */ ++ uint32_t unused; ++ /** Device OUT Endpoint DMA Buffer Register. Offset:B00h ++ * + (ep_num * 20h) + 1Ch */ ++ uint32_t doepdmab; ++} dwc_otg_dev_out_ep_regs_t; ++ ++/** ++ * This union represents the bit fields in the Device EP Control ++ * Register. Read the register into the d32 member then ++ * set/clear the bits using the bit elements. ++ */ ++typedef union depctl_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Maximum Packet Size ++ * IN/OUT EPn ++ * IN/OUT EP0 - 2 bits ++ * 2'b00: 64 Bytes ++ * 2'b01: 32 ++ * 2'b10: 16 ++ * 2'b11: 8 */ ++ unsigned mps:11; ++#define DWC_DEP0CTL_MPS_64 0 ++#define DWC_DEP0CTL_MPS_32 1 ++#define DWC_DEP0CTL_MPS_16 2 ++#define DWC_DEP0CTL_MPS_8 3 ++ ++ /** Next Endpoint ++ * IN EPn/IN EP0 ++ * OUT EPn/OUT EP0 - reserved */ ++ unsigned nextep:4; ++ ++ /** USB Active Endpoint */ ++ unsigned usbactep:1; ++ ++ /** Endpoint DPID (INTR/Bulk IN and OUT endpoints) ++ * This field contains the PID of the packet going to ++ * be received or transmitted on this endpoint. The ++ * application should program the PID of the first ++ * packet going to be received or transmitted on this ++ * endpoint , after the endpoint is ++ * activated. Application use the SetD1PID and ++ * SetD0PID fields of this register to program either ++ * D0 or D1 PID. ++ * ++ * The encoding for this field is ++ * - 0: D0 ++ * - 1: D1 ++ */ ++ unsigned dpid:1; ++ ++ /** NAK Status */ ++ unsigned naksts:1; ++ ++ /** Endpoint Type ++ * 2'b00: Control ++ * 2'b01: Isochronous ++ * 2'b10: Bulk ++ * 2'b11: Interrupt */ ++ unsigned eptype:2; ++ ++ /** Snoop Mode ++ * OUT EPn/OUT EP0 ++ * IN EPn/IN EP0 - reserved */ ++ unsigned snp:1; ++ ++ /** Stall Handshake */ ++ unsigned stall:1; ++ ++ /** Tx Fifo Number ++ * IN EPn/IN EP0 ++ * OUT EPn/OUT EP0 - reserved */ ++ unsigned txfnum:4; ++ ++ /** Clear NAK */ ++ unsigned cnak:1; ++ /** Set NAK */ ++ unsigned snak:1; ++ /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints) ++ * Writing to this field sets the Endpoint DPID (DPID) ++ * field in this register to DATA0. Set Even ++ * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints) ++ * Writing to this field sets the Even/Odd ++ * (micro)frame (EO_FrNum) field to even (micro) ++ * frame. ++ */ ++ unsigned setd0pid:1; ++ /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints) ++ * Writing to this field sets the Endpoint DPID (DPID) ++ * field in this register to DATA1 Set Odd ++ * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints) ++ * Writing to this field sets the Even/Odd ++ * (micro)frame (EO_FrNum) field to odd (micro) frame. ++ */ ++ unsigned setd1pid:1; ++ ++ /** Endpoint Disable */ ++ unsigned epdis:1; ++ /** Endpoint Enable */ ++ unsigned epena:1; ++ } b; ++} depctl_data_t; ++ ++/** ++ * This union represents the bit fields in the Device EP Transfer ++ * Size Register. Read the register into the d32 member then ++ * set/clear the bits using the bit elements. ++ */ ++typedef union deptsiz_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Transfer size */ ++ unsigned xfersize:19; ++/** Max packet count for EP (pow(2,10)-1) */ ++#define MAX_PKT_CNT 1023 ++ /** Packet Count */ ++ unsigned pktcnt:10; ++ /** Multi Count - Periodic IN endpoints */ ++ unsigned mc:2; ++ unsigned reserved:1; ++ } b; ++} deptsiz_data_t; ++ ++/** ++ * This union represents the bit fields in the Device EP 0 Transfer ++ * Size Register. Read the register into the d32 member then ++ * set/clear the bits using the bit elements. ++ */ ++typedef union deptsiz0_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Transfer size */ ++ unsigned xfersize:7; ++ /** Reserved */ ++ unsigned reserved7_18:12; ++ /** Packet Count */ ++ unsigned pktcnt:2; ++ /** Reserved */ ++ unsigned reserved21_28:8; ++ /**Setup Packet Count (DOEPTSIZ0 Only) */ ++ unsigned supcnt:2; ++ unsigned reserved31; ++ } b; ++} deptsiz0_data_t; ++ ++///////////////////////////////////////////////// ++// DMA Descriptor Specific Structures ++// ++ ++/** Buffer status definitions */ ++ ++#define BS_HOST_READY 0x0 ++#define BS_DMA_BUSY 0x1 ++#define BS_DMA_DONE 0x2 ++#define BS_HOST_BUSY 0x3 ++ ++/** Receive/Transmit status definitions */ ++ ++#define RTS_SUCCESS 0x0 ++#define RTS_BUFFLUSH 0x1 ++#define RTS_RESERVED 0x2 ++#define RTS_BUFERR 0x3 ++ ++/** ++ * This union represents the bit fields in the DMA Descriptor ++ * status quadlet. Read the quadlet into the d32 member then ++ * set/clear the bits using the bit, b_iso_out and ++ * b_iso_in elements. ++ */ ++typedef union dev_dma_desc_sts { ++ /** raw register data */ ++ uint32_t d32; ++ /** quadlet bits */ ++ struct { ++ /** Received number of bytes */ ++ unsigned bytes:16; ++ /** NAK bit - only for OUT EPs */ ++ unsigned nak:1; ++ unsigned reserved17_22:6; ++ /** Multiple Transfer - only for OUT EPs */ ++ unsigned mtrf:1; ++ /** Setup Packet received - only for OUT EPs */ ++ unsigned sr:1; ++ /** Interrupt On Complete */ ++ unsigned ioc:1; ++ /** Short Packet */ ++ unsigned sp:1; ++ /** Last */ ++ unsigned l:1; ++ /** Receive Status */ ++ unsigned sts:2; ++ /** Buffer Status */ ++ unsigned bs:2; ++ } b; ++ ++//#ifdef DWC_EN_ISOC ++ /** iso out quadlet bits */ ++ struct { ++ /** Received number of bytes */ ++ unsigned rxbytes:11; ++ ++ unsigned reserved11:1; ++ /** Frame Number */ ++ unsigned framenum:11; ++ /** Received ISO Data PID */ ++ unsigned pid:2; ++ /** Interrupt On Complete */ ++ unsigned ioc:1; ++ /** Short Packet */ ++ unsigned sp:1; ++ /** Last */ ++ unsigned l:1; ++ /** Receive Status */ ++ unsigned rxsts:2; ++ /** Buffer Status */ ++ unsigned bs:2; ++ } b_iso_out; ++ ++ /** iso in quadlet bits */ ++ struct { ++ /** Transmited number of bytes */ ++ unsigned txbytes:12; ++ /** Frame Number */ ++ unsigned framenum:11; ++ /** Transmited ISO Data PID */ ++ unsigned pid:2; ++ /** Interrupt On Complete */ ++ unsigned ioc:1; ++ /** Short Packet */ ++ unsigned sp:1; ++ /** Last */ ++ unsigned l:1; ++ /** Transmit Status */ ++ unsigned txsts:2; ++ /** Buffer Status */ ++ unsigned bs:2; ++ } b_iso_in; ++//#endif /* DWC_EN_ISOC */ ++} dev_dma_desc_sts_t; ++ ++/** ++ * DMA Descriptor structure ++ * ++ * DMA Descriptor structure contains two quadlets: ++ * Status quadlet and Data buffer pointer. ++ */ ++typedef struct dwc_otg_dev_dma_desc { ++ /** DMA Descriptor status quadlet */ ++ dev_dma_desc_sts_t status; ++ /** DMA Descriptor data buffer pointer */ ++ uint32_t buf; ++} dwc_otg_dev_dma_desc_t; ++ ++/** ++ * The dwc_otg_dev_if structure contains information needed to manage ++ * the DWC_otg controller acting in device mode. It represents the ++ * programming view of the device-specific aspects of the controller. ++ */ ++typedef struct dwc_otg_dev_if { ++ /** Pointer to device Global registers. ++ * Device Global Registers starting at offset 800h ++ */ ++ dwc_otg_device_global_regs_t *dev_global_regs; ++#define DWC_DEV_GLOBAL_REG_OFFSET 0x800 ++ ++ /** ++ * Device Logical IN Endpoint-Specific Registers 900h-AFCh ++ */ ++ dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS]; ++#define DWC_DEV_IN_EP_REG_OFFSET 0x900 ++#define DWC_EP_REG_OFFSET 0x20 ++ ++ /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */ ++ dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS]; ++#define DWC_DEV_OUT_EP_REG_OFFSET 0xB00 ++ ++ /* Device configuration information */ ++ uint8_t speed; /**< Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS */ ++ uint8_t num_in_eps; /**< Number # of Tx EP range: 0-15 exept ep0 */ ++ uint8_t num_out_eps; /**< Number # of Rx EP range: 0-15 exept ep 0*/ ++ ++ /** Size of periodic FIFOs (Bytes) */ ++ uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS]; ++ ++ /** Size of Tx FIFOs (Bytes) */ ++ uint16_t tx_fifo_size[MAX_TX_FIFOS]; ++ ++ /** Thresholding enable flags and length varaiables **/ ++ uint16_t rx_thr_en; ++ uint16_t iso_tx_thr_en; ++ uint16_t non_iso_tx_thr_en; ++ ++ uint16_t rx_thr_length; ++ uint16_t tx_thr_length; ++ ++ /** ++ * Pointers to the DMA Descriptors for EP0 Control ++ * transfers (virtual and physical) ++ */ ++ ++ /** 2 descriptors for SETUP packets */ ++ dwc_dma_t dma_setup_desc_addr[2]; ++ dwc_otg_dev_dma_desc_t *setup_desc_addr[2]; ++ ++ /** Pointer to Descriptor with latest SETUP packet */ ++ dwc_otg_dev_dma_desc_t *psetup; ++ ++ /** Index of current SETUP handler descriptor */ ++ uint32_t setup_desc_index; ++ ++ /** Descriptor for Data In or Status In phases */ ++ dwc_dma_t dma_in_desc_addr; ++ dwc_otg_dev_dma_desc_t *in_desc_addr; ++ ++ /** Descriptor for Data Out or Status Out phases */ ++ dwc_dma_t dma_out_desc_addr; ++ dwc_otg_dev_dma_desc_t *out_desc_addr; ++ ++ /** Setup Packet Detected - if set clear NAK when queueing */ ++ uint32_t spd; ++ /** Isoc ep pointer on which incomplete happens */ ++ void *isoc_ep; ++ ++} dwc_otg_dev_if_t; ++ ++///////////////////////////////////////////////// ++// Host Mode Register Structures ++// ++/** ++ * The Host Global Registers structure defines the size and relative ++ * field offsets for the Host Mode Global Registers. Host Global ++ * Registers offsets 400h-7FFh. ++*/ ++typedef struct dwc_otg_host_global_regs { ++ /** Host Configuration Register. Offset: 400h */ ++ volatile uint32_t hcfg; ++ /** Host Frame Interval Register. Offset: 404h */ ++ volatile uint32_t hfir; ++ /** Host Frame Number / Frame Remaining Register. Offset: 408h */ ++ volatile uint32_t hfnum; ++ /** Reserved. Offset: 40Ch */ ++ uint32_t reserved40C; ++ /** Host Periodic Transmit FIFO/ Queue Status Register. Offset: 410h */ ++ volatile uint32_t hptxsts; ++ /** Host All Channels Interrupt Register. Offset: 414h */ ++ volatile uint32_t haint; ++ /** Host All Channels Interrupt Mask Register. Offset: 418h */ ++ volatile uint32_t haintmsk; ++ /** Host Frame List Base Address Register . Offset: 41Ch */ ++ volatile uint32_t hflbaddr; ++} dwc_otg_host_global_regs_t; ++ ++/** ++ * This union represents the bit fields in the Host Configuration Register. ++ * Read the register into the d32 member then set/clear the bits using ++ * the bit elements. Write the d32 member to the hcfg register. ++ */ ++typedef union hcfg_data { ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ /** FS/LS Phy Clock Select */ ++ unsigned fslspclksel:2; ++#define DWC_HCFG_30_60_MHZ 0 ++#define DWC_HCFG_48_MHZ 1 ++#define DWC_HCFG_6_MHZ 2 ++ ++ /** FS/LS Only Support */ ++ unsigned fslssupp:1; ++ unsigned reserved3_6:4; ++ /** Enable 32-KHz Suspend Mode */ ++ unsigned ena32khzs:1; ++ /** Resume Validation Periiod */ ++ unsigned resvalid:8; ++ unsigned reserved16_22:7; ++ /** Enable Scatter/gather DMA in Host mode */ ++ unsigned descdma:1; ++ /** Frame List Entries */ ++ unsigned frlisten:2; ++ /** Enable Periodic Scheduling */ ++ unsigned perschedena:1; ++ unsigned reserved27_30:4; ++ unsigned modechtimen:1; ++ } b; ++} hcfg_data_t; ++ ++/** ++ * This union represents the bit fields in the Host Frame Remaing/Number ++ * Register. ++ */ ++typedef union hfir_data { ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ unsigned frint:16; ++ unsigned hfirrldctrl:1; ++ unsigned reserved:15; ++ } b; ++} hfir_data_t; ++ ++/** ++ * This union represents the bit fields in the Host Frame Remaing/Number ++ * Register. ++ */ ++typedef union hfnum_data { ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ unsigned frnum:16; ++#define DWC_HFNUM_MAX_FRNUM 0x3FFF ++ unsigned frrem:16; ++ } b; ++} hfnum_data_t; ++ ++typedef union hptxsts_data { ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ unsigned ptxfspcavail:16; ++ unsigned ptxqspcavail:8; ++ /** Top of the Periodic Transmit Request Queue ++ * - bit 24 - Terminate (last entry for the selected channel) ++ * - bits 26:25 - Token Type ++ * - 2'b00 - Zero length ++ * - 2'b01 - Ping ++ * - 2'b10 - Disable ++ * - bits 30:27 - Channel Number ++ * - bit 31 - Odd/even microframe ++ */ ++ unsigned ptxqtop_terminate:1; ++ unsigned ptxqtop_token:2; ++ unsigned ptxqtop_chnum:4; ++ unsigned ptxqtop_odd:1; ++ } b; ++} hptxsts_data_t; ++ ++/** ++ * This union represents the bit fields in the Host Port Control and Status ++ * Register. Read the register into the d32 member then set/clear the ++ * bits using the bit elements. Write the d32 member to the ++ * hprt0 register. ++ */ ++typedef union hprt0_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned prtconnsts:1; ++ unsigned prtconndet:1; ++ unsigned prtena:1; ++ unsigned prtenchng:1; ++ unsigned prtovrcurract:1; ++ unsigned prtovrcurrchng:1; ++ unsigned prtres:1; ++ unsigned prtsusp:1; ++ unsigned prtrst:1; ++ unsigned reserved9:1; ++ unsigned prtlnsts:2; ++ unsigned prtpwr:1; ++ unsigned prttstctl:4; ++ unsigned prtspd:2; ++#define DWC_HPRT0_PRTSPD_HIGH_SPEED 0 ++#define DWC_HPRT0_PRTSPD_FULL_SPEED 1 ++#define DWC_HPRT0_PRTSPD_LOW_SPEED 2 ++ unsigned reserved19_31:13; ++ } b; ++} hprt0_data_t; ++ ++/** ++ * This union represents the bit fields in the Host All Interrupt ++ * Register. ++ */ ++typedef union haint_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned ch0:1; ++ unsigned ch1:1; ++ unsigned ch2:1; ++ unsigned ch3:1; ++ unsigned ch4:1; ++ unsigned ch5:1; ++ unsigned ch6:1; ++ unsigned ch7:1; ++ unsigned ch8:1; ++ unsigned ch9:1; ++ unsigned ch10:1; ++ unsigned ch11:1; ++ unsigned ch12:1; ++ unsigned ch13:1; ++ unsigned ch14:1; ++ unsigned ch15:1; ++ unsigned reserved:16; ++ } b; ++ ++ struct { ++ unsigned chint:16; ++ unsigned reserved:16; ++ } b2; ++} haint_data_t; ++ ++/** ++ * This union represents the bit fields in the Host All Interrupt ++ * Register. ++ */ ++typedef union haintmsk_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned ch0:1; ++ unsigned ch1:1; ++ unsigned ch2:1; ++ unsigned ch3:1; ++ unsigned ch4:1; ++ unsigned ch5:1; ++ unsigned ch6:1; ++ unsigned ch7:1; ++ unsigned ch8:1; ++ unsigned ch9:1; ++ unsigned ch10:1; ++ unsigned ch11:1; ++ unsigned ch12:1; ++ unsigned ch13:1; ++ unsigned ch14:1; ++ unsigned ch15:1; ++ unsigned reserved:16; ++ } b; ++ ++ struct { ++ unsigned chint:16; ++ unsigned reserved:16; ++ } b2; ++} haintmsk_data_t; ++ ++/** ++ * Host Channel Specific Registers. 500h-5FCh ++ */ ++typedef struct dwc_otg_hc_regs { ++ /** Host Channel 0 Characteristic Register. Offset: 500h + (chan_num * 20h) + 00h */ ++ volatile uint32_t hcchar; ++ /** Host Channel 0 Split Control Register. Offset: 500h + (chan_num * 20h) + 04h */ ++ volatile uint32_t hcsplt; ++ /** Host Channel 0 Interrupt Register. Offset: 500h + (chan_num * 20h) + 08h */ ++ volatile uint32_t hcint; ++ /** Host Channel 0 Interrupt Mask Register. Offset: 500h + (chan_num * 20h) + 0Ch */ ++ volatile uint32_t hcintmsk; ++ /** Host Channel 0 Transfer Size Register. Offset: 500h + (chan_num * 20h) + 10h */ ++ volatile uint32_t hctsiz; ++ /** Host Channel 0 DMA Address Register. Offset: 500h + (chan_num * 20h) + 14h */ ++ volatile uint32_t hcdma; ++ volatile uint32_t reserved; ++ /** Host Channel 0 DMA Buffer Address Register. Offset: 500h + (chan_num * 20h) + 1Ch */ ++ volatile uint32_t hcdmab; ++} dwc_otg_hc_regs_t; ++ ++/** ++ * This union represents the bit fields in the Host Channel Characteristics ++ * Register. Read the register into the d32 member then set/clear the ++ * bits using the bit elements. Write the d32 member to the ++ * hcchar register. ++ */ ++typedef union hcchar_data { ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ /** Maximum packet size in bytes */ ++ unsigned mps:11; ++ ++ /** Endpoint number */ ++ unsigned epnum:4; ++ ++ /** 0: OUT, 1: IN */ ++ unsigned epdir:1; ++ ++ unsigned reserved:1; ++ ++ /** 0: Full/high speed device, 1: Low speed device */ ++ unsigned lspddev:1; ++ ++ /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */ ++ unsigned eptype:2; ++ ++ /** Packets per frame for periodic transfers. 0 is reserved. */ ++ unsigned multicnt:2; ++ ++ /** Device address */ ++ unsigned devaddr:7; ++ ++ /** ++ * Frame to transmit periodic transaction. ++ * 0: even, 1: odd ++ */ ++ unsigned oddfrm:1; ++ ++ /** Channel disable */ ++ unsigned chdis:1; ++ ++ /** Channel enable */ ++ unsigned chen:1; ++ } b; ++} hcchar_data_t; ++ ++typedef union hcsplt_data { ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ /** Port Address */ ++ unsigned prtaddr:7; ++ ++ /** Hub Address */ ++ unsigned hubaddr:7; ++ ++ /** Transaction Position */ ++ unsigned xactpos:2; ++#define DWC_HCSPLIT_XACTPOS_MID 0 ++#define DWC_HCSPLIT_XACTPOS_END 1 ++#define DWC_HCSPLIT_XACTPOS_BEGIN 2 ++#define DWC_HCSPLIT_XACTPOS_ALL 3 ++ ++ /** Do Complete Split */ ++ unsigned compsplt:1; ++ ++ /** Reserved */ ++ unsigned reserved:14; ++ ++ /** Split Enble */ ++ unsigned spltena:1; ++ } b; ++} hcsplt_data_t; ++ ++/** ++ * This union represents the bit fields in the Host All Interrupt ++ * Register. ++ */ ++typedef union hcint_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Transfer Complete */ ++ unsigned xfercomp:1; ++ /** Channel Halted */ ++ unsigned chhltd:1; ++ /** AHB Error */ ++ unsigned ahberr:1; ++ /** STALL Response Received */ ++ unsigned stall:1; ++ /** NAK Response Received */ ++ unsigned nak:1; ++ /** ACK Response Received */ ++ unsigned ack:1; ++ /** NYET Response Received */ ++ unsigned nyet:1; ++ /** Transaction Err */ ++ unsigned xacterr:1; ++ /** Babble Error */ ++ unsigned bblerr:1; ++ /** Frame Overrun */ ++ unsigned frmovrun:1; ++ /** Data Toggle Error */ ++ unsigned datatglerr:1; ++ /** Buffer Not Available (only for DDMA mode) */ ++ unsigned bna:1; ++ /** Exessive transaction error (only for DDMA mode) */ ++ unsigned xcs_xact:1; ++ /** Frame List Rollover interrupt */ ++ unsigned frm_list_roll:1; ++ /** Reserved */ ++ unsigned reserved14_31:18; ++ } b; ++} hcint_data_t; ++ ++/** ++ * This union represents the bit fields in the Host Channel Interrupt Mask ++ * Register. Read the register into the d32 member then set/clear the ++ * bits using the bit elements. Write the d32 member to the ++ * hcintmsk register. ++ */ ++typedef union hcintmsk_data { ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ unsigned xfercompl:1; ++ unsigned chhltd:1; ++ unsigned ahberr:1; ++ unsigned stall:1; ++ unsigned nak:1; ++ unsigned ack:1; ++ unsigned nyet:1; ++ unsigned xacterr:1; ++ unsigned bblerr:1; ++ unsigned frmovrun:1; ++ unsigned datatglerr:1; ++ unsigned bna:1; ++ unsigned xcs_xact:1; ++ unsigned frm_list_roll:1; ++ unsigned reserved14_31:18; ++ } b; ++} hcintmsk_data_t; ++ ++/** ++ * This union represents the bit fields in the Host Channel Transfer Size ++ * Register. Read the register into the d32 member then set/clear the ++ * bits using the bit elements. Write the d32 member to the ++ * hcchar register. ++ */ ++ ++typedef union hctsiz_data { ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ /** Total transfer size in bytes */ ++ unsigned xfersize:19; ++ ++ /** Data packets to transfer */ ++ unsigned pktcnt:10; ++ ++ /** ++ * Packet ID for next data packet ++ * 0: DATA0 ++ * 1: DATA2 ++ * 2: DATA1 ++ * 3: MDATA (non-Control), SETUP (Control) ++ */ ++ unsigned pid:2; ++#define DWC_HCTSIZ_DATA0 0 ++#define DWC_HCTSIZ_DATA1 2 ++#define DWC_HCTSIZ_DATA2 1 ++#define DWC_HCTSIZ_MDATA 3 ++#define DWC_HCTSIZ_SETUP 3 ++ ++ /** Do PING protocol when 1 */ ++ unsigned dopng:1; ++ } b; ++ ++ /** register bits */ ++ struct { ++ /** Scheduling information */ ++ unsigned schinfo:8; ++ ++ /** Number of transfer descriptors. ++ * Max value: ++ * 64 in general, ++ * 256 only for HS isochronous endpoint. ++ */ ++ unsigned ntd:8; ++ ++ /** Data packets to transfer */ ++ unsigned reserved16_28:13; ++ ++ /** ++ * Packet ID for next data packet ++ * 0: DATA0 ++ * 1: DATA2 ++ * 2: DATA1 ++ * 3: MDATA (non-Control) ++ */ ++ unsigned pid:2; ++ ++ /** Do PING protocol when 1 */ ++ unsigned dopng:1; ++ } b_ddma; ++} hctsiz_data_t; ++ ++/** ++ * This union represents the bit fields in the Host DMA Address ++ * Register used in Descriptor DMA mode. ++ */ ++typedef union hcdma_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned reserved0_2:3; ++ /** Current Transfer Descriptor. Not used for ISOC */ ++ unsigned ctd:8; ++ /** Start Address of Descriptor List */ ++ unsigned dma_addr:21; ++ } b; ++} hcdma_data_t; ++ ++/** ++ * This union represents the bit fields in the DMA Descriptor ++ * status quadlet for host mode. Read the quadlet into the d32 member then ++ * set/clear the bits using the bit elements. ++ */ ++typedef union host_dma_desc_sts { ++ /** raw register data */ ++ uint32_t d32; ++ /** quadlet bits */ ++ ++ /* for non-isochronous */ ++ struct { ++ /** Number of bytes */ ++ unsigned n_bytes:17; ++ /** QTD offset to jump when Short Packet received - only for IN EPs */ ++ unsigned qtd_offset:6; ++ /** ++ * Set to request the core to jump to alternate QTD if ++ * Short Packet received - only for IN EPs ++ */ ++ unsigned a_qtd:1; ++ /** ++ * Setup Packet bit. When set indicates that buffer contains ++ * setup packet. ++ */ ++ unsigned sup:1; ++ /** Interrupt On Complete */ ++ unsigned ioc:1; ++ /** End of List */ ++ unsigned eol:1; ++ unsigned reserved27:1; ++ /** Rx/Tx Status */ ++ unsigned sts:2; ++#define DMA_DESC_STS_PKTERR 1 ++ unsigned reserved30:1; ++ /** Active Bit */ ++ unsigned a:1; ++ } b; ++ /* for isochronous */ ++ struct { ++ /** Number of bytes */ ++ unsigned n_bytes:12; ++ unsigned reserved12_24:13; ++ /** Interrupt On Complete */ ++ unsigned ioc:1; ++ unsigned reserved26_27:2; ++ /** Rx/Tx Status */ ++ unsigned sts:2; ++ unsigned reserved30:1; ++ /** Active Bit */ ++ unsigned a:1; ++ } b_isoc; ++} host_dma_desc_sts_t; ++ ++#define MAX_DMA_DESC_SIZE 131071 ++#define MAX_DMA_DESC_NUM_GENERIC 64 ++#define MAX_DMA_DESC_NUM_HS_ISOC 256 ++#define MAX_FRLIST_EN_NUM 64 ++/** ++ * Host-mode DMA Descriptor structure ++ * ++ * DMA Descriptor structure contains two quadlets: ++ * Status quadlet and Data buffer pointer. ++ */ ++typedef struct dwc_otg_host_dma_desc { ++ /** DMA Descriptor status quadlet */ ++ host_dma_desc_sts_t status; ++ /** DMA Descriptor data buffer pointer */ ++ uint32_t buf; ++} dwc_otg_host_dma_desc_t; ++ ++/** OTG Host Interface Structure. ++ * ++ * The OTG Host Interface Structure structure contains information ++ * needed to manage the DWC_otg controller acting in host mode. It ++ * represents the programming view of the host-specific aspects of the ++ * controller. ++ */ ++typedef struct dwc_otg_host_if { ++ /** Host Global Registers starting at offset 400h.*/ ++ dwc_otg_host_global_regs_t *host_global_regs; ++#define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400 ++ ++ /** Host Port 0 Control and Status Register */ ++ volatile uint32_t *hprt0; ++#define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440 ++ ++ /** Host Channel Specific Registers at offsets 500h-5FCh. */ ++ dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS]; ++#define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500 ++#define DWC_OTG_CHAN_REGS_OFFSET 0x20 ++ ++ /* Host configuration information */ ++ /** Number of Host Channels (range: 1-16) */ ++ uint8_t num_host_channels; ++ /** Periodic EPs supported (0: no, 1: yes) */ ++ uint8_t perio_eps_supported; ++ /** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */ ++ uint16_t perio_tx_fifo_size; ++ ++} dwc_otg_host_if_t; ++ ++/** ++ * This union represents the bit fields in the Power and Clock Gating Control ++ * Register. Read the register into the d32 member then set/clear the ++ * bits using the bit elements. ++ */ ++typedef union pcgcctl_data { ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ /** Stop Pclk */ ++ unsigned stoppclk:1; ++ /** Gate Hclk */ ++ unsigned gatehclk:1; ++ /** Power Clamp */ ++ unsigned pwrclmp:1; ++ /** Reset Power Down Modules */ ++ unsigned rstpdwnmodule:1; ++ /** Reserved */ ++ unsigned reserved:1; ++ /** Enable Sleep Clock Gating (Enbl_L1Gating) */ ++ unsigned enbl_sleep_gating:1; ++ /** PHY In Sleep (PhySleep) */ ++ unsigned phy_in_sleep:1; ++ /** Deep Sleep*/ ++ unsigned deep_sleep:1; ++ unsigned resetaftsusp:1; ++ unsigned restoremode:1; ++ unsigned enbl_extnd_hiber:1; ++ unsigned extnd_hiber_pwrclmp:1; ++ unsigned extnd_hiber_switch:1; ++ unsigned ess_reg_restored:1; ++ unsigned prt_clk_sel:2; ++ unsigned port_power:1; ++ unsigned max_xcvrselect:2; ++ unsigned max_termsel:1; ++ unsigned mac_dev_addr:7; ++ unsigned p2hd_dev_enum_spd:2; ++ unsigned p2hd_prt_spd:2; ++ unsigned if_dev_mode:1; ++ } b; ++} pcgcctl_data_t; ++ ++/** ++ * This union represents the bit fields in the Global Data FIFO Software ++ * Configuration Register. Read the register into the d32 member then ++ * set/clear the bits using the bit elements. ++ */ ++typedef union gdfifocfg_data { ++ /* raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** OTG Data FIFO depth */ ++ unsigned gdfifocfg:16; ++ /** Start address of EP info controller */ ++ unsigned epinfobase:16; ++ } b; ++} gdfifocfg_data_t; ++ ++/** ++ * This union represents the bit fields in the Global Power Down Register ++ * Register. Read the register into the d32 member then set/clear the ++ * bits using the bit elements. ++ */ ++typedef union gpwrdn_data { ++ /* raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ /** PMU Interrupt Select */ ++ unsigned pmuintsel:1; ++ /** PMU Active */ ++ unsigned pmuactv:1; ++ /** Restore */ ++ unsigned restore:1; ++ /** Power Down Clamp */ ++ unsigned pwrdnclmp:1; ++ /** Power Down Reset */ ++ unsigned pwrdnrstn:1; ++ /** Power Down Switch */ ++ unsigned pwrdnswtch:1; ++ /** Disable VBUS */ ++ unsigned dis_vbus:1; ++ /** Line State Change */ ++ unsigned lnstschng:1; ++ /** Line state change mask */ ++ unsigned lnstchng_msk:1; ++ /** Reset Detected */ ++ unsigned rst_det:1; ++ /** Reset Detect mask */ ++ unsigned rst_det_msk:1; ++ /** Disconnect Detected */ ++ unsigned disconn_det:1; ++ /** Disconnect Detect mask */ ++ unsigned disconn_det_msk:1; ++ /** Connect Detected*/ ++ unsigned connect_det:1; ++ /** Connect Detected Mask*/ ++ unsigned connect_det_msk:1; ++ /** SRP Detected */ ++ unsigned srp_det:1; ++ /** SRP Detect mask */ ++ unsigned srp_det_msk:1; ++ /** Status Change Interrupt */ ++ unsigned sts_chngint:1; ++ /** Status Change Interrupt Mask */ ++ unsigned sts_chngint_msk:1; ++ /** Line State */ ++ unsigned linestate:2; ++ /** Indicates current mode(status of IDDIG signal) */ ++ unsigned idsts:1; ++ /** B Session Valid signal status*/ ++ unsigned bsessvld:1; ++ /** ADP Event Detected */ ++ unsigned adp_int:1; ++ /** Multi Valued ID pin */ ++ unsigned mult_val_id_bc:5; ++ /** Reserved 24_31 */ ++ unsigned reserved29_31:3; ++ } b; ++} gpwrdn_data_t; ++ ++#endif +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/Makefile linux-rpi/drivers/usb/host/dwc_otg/Makefile +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/Makefile 2015-11-29 09:42:39.915098960 +0100 +@@ -0,0 +1,82 @@ ++# ++# Makefile for DWC_otg Highspeed USB controller driver ++# ++ ++ifneq ($(KERNELRELEASE),) ++ ++# Use the BUS_INTERFACE variable to compile the software for either ++# PCI(PCI_INTERFACE) or LM(LM_INTERFACE) bus. ++ifeq ($(BUS_INTERFACE),) ++# BUS_INTERFACE = -DPCI_INTERFACE ++# BUS_INTERFACE = -DLM_INTERFACE ++ BUS_INTERFACE = -DPLATFORM_INTERFACE ++endif ++ ++#ccflags-y += -DDEBUG ++#ccflags-y += -DDWC_OTG_DEBUGLEV=1 # reduce common debug msgs ++ ++# Use one of the following flags to compile the software in host-only or ++# device-only mode. ++#ccflags-y += -DDWC_HOST_ONLY ++#ccflags-y += -DDWC_DEVICE_ONLY ++ ++ccflags-y += -Dlinux -DDWC_HS_ELECT_TST ++#ccflags-y += -DDWC_EN_ISOC ++ccflags-y += -I$(obj)/../dwc_common_port ++#ccflags-y += -I$(PORTLIB) ++ccflags-y += -DDWC_LINUX ++ccflags-y += $(CFI) ++ccflags-y += $(BUS_INTERFACE) ++#ccflags-y += -DDWC_DEV_SRPCAP ++ ++obj-$(CONFIG_USB_DWCOTG) += dwc_otg.o ++ ++dwc_otg-objs := dwc_otg_driver.o dwc_otg_attr.o ++dwc_otg-objs += dwc_otg_cil.o dwc_otg_cil_intr.o ++dwc_otg-objs += dwc_otg_pcd_linux.o dwc_otg_pcd.o dwc_otg_pcd_intr.o ++dwc_otg-objs += dwc_otg_hcd.o dwc_otg_hcd_linux.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o dwc_otg_hcd_ddma.o ++dwc_otg-objs += dwc_otg_adp.o ++dwc_otg-objs += dwc_otg_fiq_fsm.o ++dwc_otg-objs += dwc_otg_fiq_stub.o ++ifneq ($(CFI),) ++dwc_otg-objs += dwc_otg_cfi.o ++endif ++ ++kernrelwd := $(subst ., ,$(KERNELRELEASE)) ++kernrel3 := $(word 1,$(kernrelwd)).$(word 2,$(kernrelwd)).$(word 3,$(kernrelwd)) ++ ++ifneq ($(kernrel3),2.6.20) ++ccflags-y += $(CPPFLAGS) ++endif ++ ++else ++ ++PWD := $(shell pwd) ++PORTLIB := $(PWD)/../dwc_common_port ++ ++# Command paths ++CTAGS := $(CTAGS) ++DOXYGEN := $(DOXYGEN) ++ ++default: portlib ++ $(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules ++ ++install: default ++ $(MAKE) -C$(KDIR) M=$(PORTLIB) modules_install ++ $(MAKE) -C$(KDIR) M=$(PWD) modules_install ++ ++portlib: ++ $(MAKE) -C$(KDIR) M=$(PORTLIB) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules ++ cp $(PORTLIB)/Module.symvers $(PWD)/ ++ ++docs: $(wildcard *.[hc]) doc/doxygen.cfg ++ $(DOXYGEN) doc/doxygen.cfg ++ ++tags: $(wildcard *.[hc]) ++ $(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h) ++ ++ ++clean: ++ rm -rf *.o *.ko .*cmd *.mod.c .tmp_versions Module.symvers ++ ++endif +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/test/dwc_otg_test.pm linux-rpi/drivers/usb/host/dwc_otg/test/dwc_otg_test.pm +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/test/dwc_otg_test.pm 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/test/dwc_otg_test.pm 2015-11-29 09:42:39.923098428 +0100 +@@ -0,0 +1,337 @@ ++package dwc_otg_test; ++ ++use strict; ++use Exporter (); ++ ++use vars qw(@ISA @EXPORT ++$sysfsdir $paramdir $errors $params ++); ++ ++@ISA = qw(Exporter); ++ ++# ++# Globals ++# ++$sysfsdir = "/sys/devices/lm0"; ++$paramdir = "/sys/module/dwc_otg"; ++$errors = 0; ++ ++$params = [ ++ { ++ NAME => "otg_cap", ++ DEFAULT => 0, ++ ENUM => [], ++ LOW => 0, ++ HIGH => 2 ++ }, ++ { ++ NAME => "dma_enable", ++ DEFAULT => 0, ++ ENUM => [], ++ LOW => 0, ++ HIGH => 1 ++ }, ++ { ++ NAME => "dma_burst_size", ++ DEFAULT => 32, ++ ENUM => [1, 4, 8, 16, 32, 64, 128, 256], ++ LOW => 1, ++ HIGH => 256 ++ }, ++ { ++ NAME => "host_speed", ++ DEFAULT => 0, ++ ENUM => [], ++ LOW => 0, ++ HIGH => 1 ++ }, ++ { ++ NAME => "host_support_fs_ls_low_power", ++ DEFAULT => 0, ++ ENUM => [], ++ LOW => 0, ++ HIGH => 1 ++ }, ++ { ++ NAME => "host_ls_low_power_phy_clk", ++ DEFAULT => 0, ++ ENUM => [], ++ LOW => 0, ++ HIGH => 1 ++ }, ++ { ++ NAME => "dev_speed", ++ DEFAULT => 0, ++ ENUM => [], ++ LOW => 0, ++ HIGH => 1 ++ }, ++ { ++ NAME => "enable_dynamic_fifo", ++ DEFAULT => 1, ++ ENUM => [], ++ LOW => 0, ++ HIGH => 1 ++ }, ++ { ++ NAME => "data_fifo_size", ++ DEFAULT => 8192, ++ ENUM => [], ++ LOW => 32, ++ HIGH => 32768 ++ }, ++ { ++ NAME => "dev_rx_fifo_size", ++ DEFAULT => 1064, ++ ENUM => [], ++ LOW => 16, ++ HIGH => 32768 ++ }, ++ { ++ NAME => "dev_nperio_tx_fifo_size", ++ DEFAULT => 1024, ++ ENUM => [], ++ LOW => 16, ++ HIGH => 32768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_1", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_2", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_3", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_4", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_5", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_6", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_7", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_8", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_9", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_10", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_11", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_12", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_13", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_14", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_15", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "host_rx_fifo_size", ++ DEFAULT => 1024, ++ ENUM => [], ++ LOW => 16, ++ HIGH => 32768 ++ }, ++ { ++ NAME => "host_nperio_tx_fifo_size", ++ DEFAULT => 1024, ++ ENUM => [], ++ LOW => 16, ++ HIGH => 32768 ++ }, ++ { ++ NAME => "host_perio_tx_fifo_size", ++ DEFAULT => 1024, ++ ENUM => [], ++ LOW => 16, ++ HIGH => 32768 ++ }, ++ { ++ NAME => "max_transfer_size", ++ DEFAULT => 65535, ++ ENUM => [], ++ LOW => 2047, ++ HIGH => 65535 ++ }, ++ { ++ NAME => "max_packet_count", ++ DEFAULT => 511, ++ ENUM => [], ++ LOW => 15, ++ HIGH => 511 ++ }, ++ { ++ NAME => "host_channels", ++ DEFAULT => 12, ++ ENUM => [], ++ LOW => 1, ++ HIGH => 16 ++ }, ++ { ++ NAME => "dev_endpoints", ++ DEFAULT => 6, ++ ENUM => [], ++ LOW => 1, ++ HIGH => 15 ++ }, ++ { ++ NAME => "phy_type", ++ DEFAULT => 1, ++ ENUM => [], ++ LOW => 0, ++ HIGH => 2 ++ }, ++ { ++ NAME => "phy_utmi_width", ++ DEFAULT => 16, ++ ENUM => [8, 16], ++ LOW => 8, ++ HIGH => 16 ++ }, ++ { ++ NAME => "phy_ulpi_ddr", ++ DEFAULT => 0, ++ ENUM => [], ++ LOW => 0, ++ HIGH => 1 ++ }, ++ ]; ++ ++ ++# ++# ++sub check_arch { ++ $_ = `uname -m`; ++ chomp; ++ unless (m/armv4tl/) { ++ warn "# \n# Can't execute on $_. Run on integrator platform.\n# \n"; ++ return 0; ++ } ++ return 1; ++} ++ ++# ++# ++sub load_module { ++ my $params = shift; ++ print "\nRemoving Module\n"; ++ system "rmmod dwc_otg"; ++ print "Loading Module\n"; ++ if ($params ne "") { ++ print "Module Parameters: $params\n"; ++ } ++ if (system("modprobe dwc_otg $params")) { ++ warn "Unable to load module\n"; ++ return 0; ++ } ++ return 1; ++} ++ ++# ++# ++sub test_status { ++ my $arg = shift; ++ ++ print "\n"; ++ ++ if (defined $arg) { ++ warn "WARNING: $arg\n"; ++ } ++ ++ if ($errors > 0) { ++ warn "TEST FAILED with $errors errors\n"; ++ return 0; ++ } else { ++ print "TEST PASSED\n"; ++ return 0 if (defined $arg); ++ } ++ return 1; ++} ++ ++# ++# ++@EXPORT = qw( ++$sysfsdir ++$paramdir ++$params ++$errors ++check_arch ++load_module ++test_status ++); ++ ++1; +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/test/Makefile linux-rpi/drivers/usb/host/dwc_otg/test/Makefile +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/test/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/test/Makefile 2015-11-29 09:42:39.923098428 +0100 +@@ -0,0 +1,16 @@ ++ ++PERL=/usr/bin/perl ++PL_TESTS=test_sysfs.pl test_mod_param.pl ++ ++.PHONY : test ++test : perl_tests ++ ++perl_tests : ++ @echo ++ @echo Running perl tests ++ @for test in $(PL_TESTS); do \ ++ if $(PERL) ./$$test ; then \ ++ echo "=======> $$test, PASSED" ; \ ++ else echo "=======> $$test, FAILED" ; \ ++ fi \ ++ done +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/test/test_mod_param.pl linux-rpi/drivers/usb/host/dwc_otg/test/test_mod_param.pl +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/test/test_mod_param.pl 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/test/test_mod_param.pl 2015-11-29 09:42:39.923098428 +0100 +@@ -0,0 +1,133 @@ ++#!/usr/bin/perl -w ++# ++# Run this program on the integrator. ++# ++# - Tests module parameter default values. ++# - Tests setting of valid module parameter values via modprobe. ++# - Tests invalid module parameter values. ++# ----------------------------------------------------------------------------- ++use strict; ++use dwc_otg_test; ++ ++check_arch() or die; ++ ++# ++# ++sub test { ++ my ($param,$expected) = @_; ++ my $value = get($param); ++ ++ if ($value == $expected) { ++ print "$param = $value, okay\n"; ++ } ++ ++ else { ++ warn "ERROR: value of $param != $expected, $value\n"; ++ $errors ++; ++ } ++} ++ ++# ++# ++sub get { ++ my $param = shift; ++ my $tmp = `cat $paramdir/$param`; ++ chomp $tmp; ++ return $tmp; ++} ++ ++# ++# ++sub test_main { ++ ++ print "\nTesting Module Parameters\n"; ++ ++ load_module("") or die; ++ ++ # Test initial values ++ print "\nTesting Default Values\n"; ++ foreach (@{$params}) { ++ test ($_->{NAME}, $_->{DEFAULT}); ++ } ++ ++ # Test low value ++ print "\nTesting Low Value\n"; ++ my $cmd_params = ""; ++ foreach (@{$params}) { ++ $cmd_params = $cmd_params . "$_->{NAME}=$_->{LOW} "; ++ } ++ load_module($cmd_params) or die; ++ ++ foreach (@{$params}) { ++ test ($_->{NAME}, $_->{LOW}); ++ } ++ ++ # Test high value ++ print "\nTesting High Value\n"; ++ $cmd_params = ""; ++ foreach (@{$params}) { ++ $cmd_params = $cmd_params . "$_->{NAME}=$_->{HIGH} "; ++ } ++ load_module($cmd_params) or die; ++ ++ foreach (@{$params}) { ++ test ($_->{NAME}, $_->{HIGH}); ++ } ++ ++ # Test Enum ++ print "\nTesting Enumerated\n"; ++ foreach (@{$params}) { ++ if (defined $_->{ENUM}) { ++ my $value; ++ foreach $value (@{$_->{ENUM}}) { ++ $cmd_params = "$_->{NAME}=$value"; ++ load_module($cmd_params) or die; ++ test ($_->{NAME}, $value); ++ } ++ } ++ } ++ ++ # Test Invalid Values ++ print "\nTesting Invalid Values\n"; ++ $cmd_params = ""; ++ foreach (@{$params}) { ++ $cmd_params = $cmd_params . sprintf "$_->{NAME}=%d ", $_->{LOW}-1; ++ } ++ load_module($cmd_params) or die; ++ ++ foreach (@{$params}) { ++ test ($_->{NAME}, $_->{DEFAULT}); ++ } ++ ++ $cmd_params = ""; ++ foreach (@{$params}) { ++ $cmd_params = $cmd_params . sprintf "$_->{NAME}=%d ", $_->{HIGH}+1; ++ } ++ load_module($cmd_params) or die; ++ ++ foreach (@{$params}) { ++ test ($_->{NAME}, $_->{DEFAULT}); ++ } ++ ++ print "\nTesting Enumerated\n"; ++ foreach (@{$params}) { ++ if (defined $_->{ENUM}) { ++ my $value; ++ foreach $value (@{$_->{ENUM}}) { ++ $value = $value + 1; ++ $cmd_params = "$_->{NAME}=$value"; ++ load_module($cmd_params) or die; ++ test ($_->{NAME}, $_->{DEFAULT}); ++ $value = $value - 2; ++ $cmd_params = "$_->{NAME}=$value"; ++ load_module($cmd_params) or die; ++ test ($_->{NAME}, $_->{DEFAULT}); ++ } ++ } ++ } ++ ++ test_status() or die; ++} ++ ++test_main(); ++0; +diff -Nur linux-4.1.13.orig/drivers/usb/host/dwc_otg/test/test_sysfs.pl linux-rpi/drivers/usb/host/dwc_otg/test/test_sysfs.pl +--- linux-4.1.13.orig/drivers/usb/host/dwc_otg/test/test_sysfs.pl 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/usb/host/dwc_otg/test/test_sysfs.pl 2015-11-29 09:42:39.923098428 +0100 +@@ -0,0 +1,193 @@ ++#!/usr/bin/perl -w ++# ++# Run this program on the integrator ++# - Tests select sysfs attributes. ++# - Todo ... test more attributes, hnp/srp, buspower/bussuspend, etc. ++# ----------------------------------------------------------------------------- ++use strict; ++use dwc_otg_test; ++ ++check_arch() or die; ++ ++# ++# ++sub test { ++ my ($attr,$expected) = @_; ++ my $string = get($attr); ++ ++ if ($string eq $expected) { ++ printf("$attr = $string, okay\n"); ++ } ++ else { ++ warn "ERROR: value of $attr != $expected, $string\n"; ++ $errors ++; ++ } ++} ++ ++# ++# ++sub set { ++ my ($reg, $value) = @_; ++ system "echo $value > $sysfsdir/$reg"; ++} ++ ++# ++# ++sub get { ++ my $attr = shift; ++ my $string = `cat $sysfsdir/$attr`; ++ chomp $string; ++ if ($string =~ m/\s\=\s/) { ++ my $tmp; ++ ($tmp, $string) = split /\s=\s/, $string; ++ } ++ return $string; ++} ++ ++# ++# ++sub test_main { ++ print("\nTesting Sysfs Attributes\n"); ++ ++ load_module("") or die; ++ ++ # Test initial values of regoffset/regvalue/guid/gsnpsid ++ print("\nTesting Default Values\n"); ++ ++ test("regoffset", "0xffffffff"); ++ test("regvalue", "invalid offset"); ++ test("guid", "0x12345678"); # this will fail if it has been changed ++ test("gsnpsid", "0x4f54200a"); ++ ++ # Test operation of regoffset/regvalue ++ print("\nTesting regoffset\n"); ++ set('regoffset', '5a5a5a5a'); ++ test("regoffset", "0xffffffff"); ++ ++ set('regoffset', '0'); ++ test("regoffset", "0x00000000"); ++ ++ set('regoffset', '40000'); ++ test("regoffset", "0x00000000"); ++ ++ set('regoffset', '3ffff'); ++ test("regoffset", "0x0003ffff"); ++ ++ set('regoffset', '1'); ++ test("regoffset", "0x00000001"); ++ ++ print("\nTesting regvalue\n"); ++ set('regoffset', '3c'); ++ test("regvalue", "0x12345678"); ++ set('regvalue', '5a5a5a5a'); ++ test("regvalue", "0x5a5a5a5a"); ++ set('regvalue','a5a5a5a5'); ++ test("regvalue", "0xa5a5a5a5"); ++ set('guid','12345678'); ++ ++ # Test HNP Capable ++ print("\nTesting HNP Capable bit\n"); ++ set('hnpcapable', '1'); ++ test("hnpcapable", "0x1"); ++ set('hnpcapable','0'); ++ test("hnpcapable", "0x0"); ++ ++ set('regoffset','0c'); ++ ++ my $old = get('gusbcfg'); ++ print("setting hnpcapable\n"); ++ set('hnpcapable', '1'); ++ test("hnpcapable", "0x1"); ++ test('gusbcfg', sprintf "0x%08x", (oct ($old) | (1<<9))); ++ test('regvalue', sprintf "0x%08x", (oct ($old) | (1<<9))); ++ ++ $old = get('gusbcfg'); ++ print("clearing hnpcapable\n"); ++ set('hnpcapable', '0'); ++ test("hnpcapable", "0x0"); ++ test ('gusbcfg', sprintf "0x%08x", oct ($old) & (~(1<<9))); ++ test ('regvalue', sprintf "0x%08x", oct ($old) & (~(1<<9))); ++ ++ # Test SRP Capable ++ print("\nTesting SRP Capable bit\n"); ++ set('srpcapable', '1'); ++ test("srpcapable", "0x1"); ++ set('srpcapable','0'); ++ test("srpcapable", "0x0"); ++ ++ set('regoffset','0c'); ++ ++ $old = get('gusbcfg'); ++ print("setting srpcapable\n"); ++ set('srpcapable', '1'); ++ test("srpcapable", "0x1"); ++ test('gusbcfg', sprintf "0x%08x", (oct ($old) | (1<<8))); ++ test('regvalue', sprintf "0x%08x", (oct ($old) | (1<<8))); ++ ++ $old = get('gusbcfg'); ++ print("clearing srpcapable\n"); ++ set('srpcapable', '0'); ++ test("srpcapable", "0x0"); ++ test('gusbcfg', sprintf "0x%08x", oct ($old) & (~(1<<8))); ++ test('regvalue', sprintf "0x%08x", oct ($old) & (~(1<<8))); ++ ++ # Test GGPIO ++ print("\nTesting GGPIO\n"); ++ set('ggpio','5a5a5a5a'); ++ test('ggpio','0x5a5a0000'); ++ set('ggpio','a5a5a5a5'); ++ test('ggpio','0xa5a50000'); ++ set('ggpio','11110000'); ++ test('ggpio','0x11110000'); ++ set('ggpio','00001111'); ++ test('ggpio','0x00000000'); ++ ++ # Test DEVSPEED ++ print("\nTesting DEVSPEED\n"); ++ set('regoffset','800'); ++ $old = get('regvalue'); ++ set('devspeed','0'); ++ test('devspeed','0x0'); ++ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3))); ++ set('devspeed','1'); ++ test('devspeed','0x1'); ++ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 1)); ++ set('devspeed','2'); ++ test('devspeed','0x2'); ++ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 2)); ++ set('devspeed','3'); ++ test('devspeed','0x3'); ++ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 3)); ++ set('devspeed','4'); ++ test('devspeed','0x0'); ++ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3))); ++ set('devspeed','5'); ++ test('devspeed','0x1'); ++ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 1)); ++ ++ ++ # mode Returns the current mode:0 for device mode1 for host mode Read ++ # hnp Initiate the Host Negotiation Protocol. Read returns the status. Read/Write ++ # srp Initiate the Session Request Protocol. Read returns the status. Read/Write ++ # buspower Get or Set the Power State of the bus (0 - Off or 1 - On) Read/Write ++ # bussuspend Suspend the USB bus. Read/Write ++ # busconnected Get the connection status of the bus Read ++ ++ # gotgctl Get or set the Core Control Status Register. Read/Write ++ ## gusbcfg Get or set the Core USB Configuration Register Read/Write ++ # grxfsiz Get or set the Receive FIFO Size Register Read/Write ++ # gnptxfsiz Get or set the non-periodic Transmit Size Register Read/Write ++ # gpvndctl Get or set the PHY Vendor Control Register Read/Write ++ ## ggpio Get the value in the lower 16-bits of the General Purpose IO Register or Set the upper 16 bits. Read/Write ++ ## guid Get or set the value of the User ID Register Read/Write ++ ## gsnpsid Get the value of the Synopsys ID Regester Read ++ ## devspeed Get or set the device speed setting in the DCFG register Read/Write ++ # enumspeed Gets the device enumeration Speed. Read ++ # hptxfsiz Get the value of the Host Periodic Transmit FIFO Read ++ # hprt0 Get or Set the value in the Host Port Control and Status Register Read/Write ++ ++ test_status("TEST NYI") or die; ++} ++ ++test_main(); ++0; +diff -Nur linux-4.1.13.orig/drivers/usb/host/Kconfig linux-rpi/drivers/usb/host/Kconfig +--- linux-4.1.13.orig/drivers/usb/host/Kconfig 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/usb/host/Kconfig 2015-11-29 09:42:39.915098960 +0100 +@@ -738,6 +738,19 @@ + To compile this driver a module, choose M here: the module + will be called "hwa-hc". + ++config USB_DWCOTG ++ tristate "Synopsis DWC host support" ++ depends on USB ++ help ++ The Synopsis DWC controller is a dual-role ++ host/peripheral/OTG ("On The Go") USB controllers. ++ ++ Enable this option to support this IP in host controller mode. ++ If unsure, say N. ++ ++ To compile this driver as a module, choose M here: the ++ modules built will be called dwc_otg and dwc_common_port. ++ + config USB_IMX21_HCD + tristate "i.MX21 HCD support" + depends on ARM && ARCH_MXC +diff -Nur linux-4.1.13.orig/drivers/usb/host/Makefile linux-rpi/drivers/usb/host/Makefile +--- linux-4.1.13.orig/drivers/usb/host/Makefile 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/usb/host/Makefile 2015-11-29 09:42:39.915098960 +0100 +@@ -68,6 +68,8 @@ + obj-$(CONFIG_USB_U132_HCD) += u132-hcd.o + obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o + obj-$(CONFIG_USB_HWA_HCD) += hwa-hc.o ++ ++obj-$(CONFIG_USB_DWCOTG) += dwc_otg/ dwc_common_port/ + obj-$(CONFIG_USB_IMX21_HCD) += imx21-hcd.o + obj-$(CONFIG_USB_FSL_MPH_DR_OF) += fsl-mph-dr-of.o + obj-$(CONFIG_USB_HCD_BCMA) += bcma-hcd.o +diff -Nur linux-4.1.13.orig/drivers/usb/Makefile linux-rpi/drivers/usb/Makefile +--- linux-4.1.13.orig/drivers/usb/Makefile 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/usb/Makefile 2015-11-29 09:42:39.847103478 +0100 +@@ -7,6 +7,7 @@ + obj-$(CONFIG_USB) += core/ + obj-$(CONFIG_USB_SUPPORT) += phy/ + ++obj-$(CONFIG_USB_DWCOTG) += host/ + obj-$(CONFIG_USB_DWC3) += dwc3/ + obj-$(CONFIG_USB_DWC2) += dwc2/ + obj-$(CONFIG_USB_ISP1760) += isp1760/ +diff -Nur linux-4.1.13.orig/drivers/video/backlight/Kconfig linux-rpi/drivers/video/backlight/Kconfig +--- linux-4.1.13.orig/drivers/video/backlight/Kconfig 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/video/backlight/Kconfig 2015-11-29 09:42:40.023091784 +0100 +@@ -263,6 +263,12 @@ + If you have a LCD backlight adjustable by PWM, say Y to enable + this driver. + ++config BACKLIGHT_RPI ++ tristate "Raspberry Pi display firmware driven backlight" ++ help ++ If you have the Raspberry Pi DSI touchscreen display, say Y to ++ enable the mailbox-controlled backlight driver. ++ + config BACKLIGHT_DA903X + tristate "Backlight Driver for DA9030/DA9034 using WLED" + depends on PMIC_DA903X +diff -Nur linux-4.1.13.orig/drivers/video/backlight/Makefile linux-rpi/drivers/video/backlight/Makefile +--- linux-4.1.13.orig/drivers/video/backlight/Makefile 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/video/backlight/Makefile 2015-11-29 09:42:40.023091784 +0100 +@@ -49,6 +49,7 @@ + obj-$(CONFIG_BACKLIGHT_PANDORA) += pandora_bl.o + obj-$(CONFIG_BACKLIGHT_PCF50633) += pcf50633-backlight.o + obj-$(CONFIG_BACKLIGHT_PWM) += pwm_bl.o ++obj-$(CONFIG_BACKLIGHT_RPI) += rpi_backlight.o + obj-$(CONFIG_BACKLIGHT_SAHARA) += kb3886_bl.o + obj-$(CONFIG_BACKLIGHT_SKY81452) += sky81452-backlight.o + obj-$(CONFIG_BACKLIGHT_TOSA) += tosa_bl.o +diff -Nur linux-4.1.13.orig/drivers/video/backlight/rpi_backlight.c linux-rpi/drivers/video/backlight/rpi_backlight.c +--- linux-4.1.13.orig/drivers/video/backlight/rpi_backlight.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/video/backlight/rpi_backlight.c 2015-11-29 09:42:40.027091518 +0100 +@@ -0,0 +1,119 @@ ++/* ++ * rpi_bl.c - Backlight controller through VPU ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++struct rpi_backlight { ++ struct device *dev; ++ struct device *fbdev; ++ struct rpi_firmware *fw; ++}; ++ ++static int rpi_backlight_update_status(struct backlight_device *bl) ++{ ++ struct rpi_backlight *gbl = bl_get_data(bl); ++ int brightness = bl->props.brightness; ++ int ret; ++ ++ if (bl->props.power != FB_BLANK_UNBLANK || ++ bl->props.fb_blank != FB_BLANK_UNBLANK || ++ bl->props.state & (BL_CORE_SUSPENDED | BL_CORE_FBBLANK)) ++ brightness = 0; ++ ++ ret = rpi_firmware_property(gbl->fw, ++ RPI_FIRMWARE_FRAMEBUFFER_SET_BACKLIGHT, ++ &brightness, sizeof(brightness)); ++ if (ret) { ++ dev_err(gbl->dev, "Failed to set brightness\n"); ++ return ret; ++ } ++ ++ if (brightness < 0) { ++ dev_err(gbl->dev, "Backlight change failed\n"); ++ return -EAGAIN; ++ } ++ ++ return 0; ++} ++ ++static const struct backlight_ops rpi_backlight_ops = { ++ .options = BL_CORE_SUSPENDRESUME, ++ .update_status = rpi_backlight_update_status, ++}; ++ ++static int rpi_backlight_probe(struct platform_device *pdev) ++{ ++ struct backlight_properties props; ++ struct backlight_device *bl; ++ struct rpi_backlight *gbl; ++ struct device_node *fw_node; ++ ++ gbl = devm_kzalloc(&pdev->dev, sizeof(*gbl), GFP_KERNEL); ++ if (gbl == NULL) ++ return -ENOMEM; ++ ++ gbl->dev = &pdev->dev; ++ ++ fw_node = of_parse_phandle(pdev->dev.of_node, "firmware", 0); ++ if (!fw_node) { ++ dev_err(&pdev->dev, "Missing firmware node\n"); ++ return -ENOENT; ++ } ++ ++ gbl->fw = rpi_firmware_get(fw_node); ++ if (!gbl->fw) ++ return -EPROBE_DEFER; ++ ++ memset(&props, 0, sizeof(props)); ++ props.type = BACKLIGHT_RAW; ++ props.max_brightness = 255; ++ bl = devm_backlight_device_register(&pdev->dev, dev_name(&pdev->dev), ++ &pdev->dev, gbl, &rpi_backlight_ops, ++ &props); ++ if (IS_ERR(bl)) { ++ dev_err(&pdev->dev, "failed to register backlight\n"); ++ return PTR_ERR(bl); ++ } ++ ++ bl->props.brightness = 255; ++ backlight_update_status(bl); ++ ++ platform_set_drvdata(pdev, bl); ++ return 0; ++} ++ ++static const struct of_device_id rpi_backlight_of_match[] = { ++ { .compatible = "raspberrypi,rpi-backlight" }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, rpi_backlight_of_match); ++ ++static struct platform_driver rpi_backlight_driver = { ++ .driver = { ++ .name = "rpi-backlight", ++ .of_match_table = of_match_ptr(rpi_backlight_of_match), ++ }, ++ .probe = rpi_backlight_probe, ++}; ++ ++module_platform_driver(rpi_backlight_driver); ++ ++MODULE_AUTHOR("Gordon Hollingworth "); ++MODULE_DESCRIPTION("Raspberry Pi mailbox based Backlight Driver"); ++MODULE_LICENSE("GPL"); +diff -Nur linux-4.1.13.orig/drivers/video/fbdev/bcm2708_fb.c linux-rpi/drivers/video/fbdev/bcm2708_fb.c +--- linux-4.1.13.orig/drivers/video/fbdev/bcm2708_fb.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/video/fbdev/bcm2708_fb.c 2015-11-29 09:42:40.071088595 +0100 +@@ -0,0 +1,847 @@ ++/* ++ * linux/drivers/video/bcm2708_fb.c ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ * ++ * Broadcom simple framebuffer driver ++ * ++ * This file is derived from cirrusfb.c ++ * Copyright 1999-2001 Jeff Garzik ++ * ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++//#define BCM2708_FB_DEBUG ++#define MODULE_NAME "bcm2708_fb" ++ ++#ifdef BCM2708_FB_DEBUG ++#define print_debug(fmt,...) pr_debug("%s:%s:%d: "fmt, MODULE_NAME, __func__, __LINE__, ##__VA_ARGS__) ++#else ++#define print_debug(fmt,...) ++#endif ++ ++/* This is limited to 16 characters when displayed by X startup */ ++static const char *bcm2708_name = "BCM2708 FB"; ++ ++#define DRIVER_NAME "bcm2708_fb" ++ ++static int fbwidth = 800; /* module parameter */ ++static int fbheight = 480; /* module parameter */ ++static int fbdepth = 16; /* module parameter */ ++static int fbswap = 0; /* module parameter */ ++ ++static u32 dma_busy_wait_threshold = 1<<15; ++module_param(dma_busy_wait_threshold, int, 0644); ++MODULE_PARM_DESC(dma_busy_wait_threshold, "Busy-wait for DMA completion below this area"); ++ ++struct fb_alloc_tags { ++ struct rpi_firmware_property_tag_header tag1; ++ u32 xres, yres; ++ struct rpi_firmware_property_tag_header tag2; ++ u32 xres_virtual, yres_virtual; ++ struct rpi_firmware_property_tag_header tag3; ++ u32 bpp; ++ struct rpi_firmware_property_tag_header tag4; ++ u32 xoffset, yoffset; ++ struct rpi_firmware_property_tag_header tag5; ++ u32 base, screen_size; ++ struct rpi_firmware_property_tag_header tag6; ++ u32 pitch; ++}; ++ ++struct bcm2708_fb_stats { ++ struct debugfs_regset32 regset; ++ u32 dma_copies; ++ u32 dma_irqs; ++}; ++ ++struct bcm2708_fb { ++ struct fb_info fb; ++ struct platform_device *dev; ++ struct rpi_firmware *fw; ++ u32 cmap[16]; ++ u32 gpu_cmap[256]; ++ int dma_chan; ++ int dma_irq; ++ void __iomem *dma_chan_base; ++ void *cb_base; /* DMA control blocks */ ++ dma_addr_t cb_handle; ++ struct dentry *debugfs_dir; ++ wait_queue_head_t dma_waitq; ++ struct bcm2708_fb_stats stats; ++ unsigned long fb_bus_address; ++}; ++ ++#define to_bcm2708(info) container_of(info, struct bcm2708_fb, fb) ++ ++static void bcm2708_fb_debugfs_deinit(struct bcm2708_fb *fb) ++{ ++ debugfs_remove_recursive(fb->debugfs_dir); ++ fb->debugfs_dir = NULL; ++} ++ ++static int bcm2708_fb_debugfs_init(struct bcm2708_fb *fb) ++{ ++ static struct debugfs_reg32 stats_registers[] = { ++ { ++ "dma_copies", ++ offsetof(struct bcm2708_fb_stats, dma_copies) ++ }, ++ { ++ "dma_irqs", ++ offsetof(struct bcm2708_fb_stats, dma_irqs) ++ }, ++ }; ++ ++ fb->debugfs_dir = debugfs_create_dir(DRIVER_NAME, NULL); ++ if (!fb->debugfs_dir) { ++ pr_warn("%s: could not create debugfs entry\n", ++ __func__); ++ return -EFAULT; ++ } ++ ++ fb->stats.regset.regs = stats_registers; ++ fb->stats.regset.nregs = ARRAY_SIZE(stats_registers); ++ fb->stats.regset.base = &fb->stats; ++ ++ if (!debugfs_create_regset32( ++ "stats", 0444, fb->debugfs_dir, &fb->stats.regset)) { ++ pr_warn("%s: could not create statistics registers\n", ++ __func__); ++ goto fail; ++ } ++ return 0; ++ ++fail: ++ bcm2708_fb_debugfs_deinit(fb); ++ return -EFAULT; ++} ++ ++static int bcm2708_fb_set_bitfields(struct fb_var_screeninfo *var) ++{ ++ int ret = 0; ++ ++ memset(&var->transp, 0, sizeof(var->transp)); ++ ++ var->red.msb_right = 0; ++ var->green.msb_right = 0; ++ var->blue.msb_right = 0; ++ ++ switch (var->bits_per_pixel) { ++ case 1: ++ case 2: ++ case 4: ++ case 8: ++ var->red.length = var->bits_per_pixel; ++ var->red.offset = 0; ++ var->green.length = var->bits_per_pixel; ++ var->green.offset = 0; ++ var->blue.length = var->bits_per_pixel; ++ var->blue.offset = 0; ++ break; ++ case 16: ++ var->red.length = 5; ++ var->blue.length = 5; ++ /* ++ * Green length can be 5 or 6 depending whether ++ * we're operating in RGB555 or RGB565 mode. ++ */ ++ if (var->green.length != 5 && var->green.length != 6) ++ var->green.length = 6; ++ break; ++ case 24: ++ var->red.length = 8; ++ var->blue.length = 8; ++ var->green.length = 8; ++ break; ++ case 32: ++ var->red.length = 8; ++ var->green.length = 8; ++ var->blue.length = 8; ++ var->transp.length = 8; ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ ++ /* ++ * >= 16bpp displays have separate colour component bitfields ++ * encoded in the pixel data. Calculate their position from ++ * the bitfield length defined above. ++ */ ++ if (ret == 0 && var->bits_per_pixel >= 24 && fbswap) { ++ var->blue.offset = 0; ++ var->green.offset = var->blue.offset + var->blue.length; ++ var->red.offset = var->green.offset + var->green.length; ++ var->transp.offset = var->red.offset + var->red.length; ++ } else if (ret == 0 && var->bits_per_pixel >= 24) { ++ var->red.offset = 0; ++ var->green.offset = var->red.offset + var->red.length; ++ var->blue.offset = var->green.offset + var->green.length; ++ var->transp.offset = var->blue.offset + var->blue.length; ++ } else if (ret == 0 && var->bits_per_pixel >= 16) { ++ var->blue.offset = 0; ++ var->green.offset = var->blue.offset + var->blue.length; ++ var->red.offset = var->green.offset + var->green.length; ++ var->transp.offset = var->red.offset + var->red.length; ++ } ++ ++ return ret; ++} ++ ++static int bcm2708_fb_check_var(struct fb_var_screeninfo *var, ++ struct fb_info *info) ++{ ++ /* info input, var output */ ++ int yres; ++ ++ /* info input, var output */ ++ print_debug("bcm2708_fb_check_var info(%p) %dx%d (%dx%d), %d, %d\n", info, ++ info->var.xres, info->var.yres, info->var.xres_virtual, ++ info->var.yres_virtual, (int)info->screen_size, ++ info->var.bits_per_pixel); ++ print_debug("bcm2708_fb_check_var var(%p) %dx%d (%dx%d), %d\n", var, ++ var->xres, var->yres, var->xres_virtual, var->yres_virtual, ++ var->bits_per_pixel); ++ ++ if (!var->bits_per_pixel) ++ var->bits_per_pixel = 16; ++ ++ if (bcm2708_fb_set_bitfields(var) != 0) { ++ pr_err("bcm2708_fb_check_var: invalid bits_per_pixel %d\n", ++ var->bits_per_pixel); ++ return -EINVAL; ++ } ++ ++ ++ if (var->xres_virtual < var->xres) ++ var->xres_virtual = var->xres; ++ /* use highest possible virtual resolution */ ++ if (var->yres_virtual == -1) { ++ var->yres_virtual = 480; ++ ++ pr_err ++ ("bcm2708_fb_check_var: virtual resolution set to maximum of %dx%d\n", ++ var->xres_virtual, var->yres_virtual); ++ } ++ if (var->yres_virtual < var->yres) ++ var->yres_virtual = var->yres; ++ ++ if (var->xoffset < 0) ++ var->xoffset = 0; ++ if (var->yoffset < 0) ++ var->yoffset = 0; ++ ++ /* truncate xoffset and yoffset to maximum if too high */ ++ if (var->xoffset > var->xres_virtual - var->xres) ++ var->xoffset = var->xres_virtual - var->xres - 1; ++ if (var->yoffset > var->yres_virtual - var->yres) ++ var->yoffset = var->yres_virtual - var->yres - 1; ++ ++ return 0; ++} ++ ++static int bcm2708_fb_set_par(struct fb_info *info) ++{ ++ struct bcm2708_fb *fb = to_bcm2708(info); ++ struct fb_alloc_tags fbinfo = { ++ .tag1 = { RPI_FIRMWARE_FRAMEBUFFER_SET_PHYSICAL_WIDTH_HEIGHT, ++ 8, 0, }, ++ .xres = info->var.xres, ++ .yres = info->var.yres, ++ .tag2 = { RPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_WIDTH_HEIGHT, ++ 8, 0, }, ++ .xres_virtual = info->var.xres_virtual, ++ .yres_virtual = info->var.yres_virtual, ++ .tag3 = { RPI_FIRMWARE_FRAMEBUFFER_SET_DEPTH, 4, 0 }, ++ .bpp = info->var.bits_per_pixel, ++ .tag4 = { RPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_OFFSET, 8, 0 }, ++ .xoffset = info->var.xoffset, ++ .yoffset = info->var.yoffset, ++ .tag5 = { RPI_FIRMWARE_FRAMEBUFFER_ALLOCATE, 8, 0 }, ++ .base = 0, ++ .screen_size = 0, ++ .tag6 = { RPI_FIRMWARE_FRAMEBUFFER_GET_PITCH, 4, 0 }, ++ .pitch = 0, ++ }; ++ int ret; ++ ++ print_debug("bcm2708_fb_set_par info(%p) %dx%d (%dx%d), %d, %d\n", info, ++ info->var.xres, info->var.yres, info->var.xres_virtual, ++ info->var.yres_virtual, (int)info->screen_size, ++ info->var.bits_per_pixel); ++ ++ ret = rpi_firmware_property_list(fb->fw, &fbinfo, sizeof(fbinfo)); ++ if (ret) { ++ dev_err(info->device, ++ "Failed to allocate GPU framebuffer (%d)\n", ret); ++ return ret; ++ } ++ ++ if (info->var.bits_per_pixel <= 8) ++ fb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR; ++ else ++ fb->fb.fix.visual = FB_VISUAL_TRUECOLOR; ++ ++ fb->fb.fix.line_length = fbinfo.pitch; ++ fbinfo.base |= 0x40000000; ++ fb->fb_bus_address = fbinfo.base; ++ fbinfo.base &= ~0xc0000000; ++ fb->fb.fix.smem_start = fbinfo.base; ++ fb->fb.fix.smem_len = fbinfo.pitch * fbinfo.yres_virtual; ++ fb->fb.screen_size = fbinfo.screen_size; ++ if (fb->fb.screen_base) ++ iounmap(fb->fb.screen_base); ++ fb->fb.screen_base = ioremap_wc(fbinfo.base, fb->fb.screen_size); ++ if (!fb->fb.screen_base) { ++ /* the console may currently be locked */ ++ console_trylock(); ++ console_unlock(); ++ dev_err(info->device, "Failed to set screen_base\n"); ++ return -ENOMEM; ++ } ++ ++ print_debug ++ ("BCM2708FB: start = %p,%p width=%d, height=%d, bpp=%d, pitch=%d size=%d\n", ++ (void *)fb->fb.screen_base, (void *)fb->fb_bus_address, ++ fbinfo.xres, fbinfo.yres, fbinfo.bpp, ++ fbinfo.pitch, (int)fb->fb.screen_size); ++ ++ return 0; ++} ++ ++static inline u32 convert_bitfield(int val, struct fb_bitfield *bf) ++{ ++ unsigned int mask = (1 << bf->length) - 1; ++ ++ return (val >> (16 - bf->length) & mask) << bf->offset; ++} ++ ++ ++static int bcm2708_fb_setcolreg(unsigned int regno, unsigned int red, ++ unsigned int green, unsigned int blue, ++ unsigned int transp, struct fb_info *info) ++{ ++ struct bcm2708_fb *fb = to_bcm2708(info); ++ ++ /*print_debug("BCM2708FB: setcolreg %d:(%02x,%02x,%02x,%02x) %x\n", regno, red, green, blue, transp, fb->fb.fix.visual);*/ ++ if (fb->fb.var.bits_per_pixel <= 8) { ++ if (regno < 256) { ++ /* blue [23:16], green [15:8], red [7:0] */ ++ fb->gpu_cmap[regno] = ((red >> 8) & 0xff) << 0 | ++ ((green >> 8) & 0xff) << 8 | ++ ((blue >> 8) & 0xff) << 16; ++ } ++ /* Hack: we need to tell GPU the palette has changed, but currently bcm2708_fb_set_par takes noticable time when called for every (256) colour */ ++ /* So just call it for what looks like the last colour in a list for now. */ ++ if (regno == 15 || regno == 255) { ++ struct packet { ++ u32 offset; ++ u32 length; ++ u32 cmap[256]; ++ } *packet; ++ int ret; ++ ++ packet = kmalloc(sizeof(*packet), GFP_KERNEL); ++ if (!packet) ++ return -ENOMEM; ++ packet->offset = 0; ++ packet->length = regno + 1; ++ memcpy(packet->cmap, fb->gpu_cmap, sizeof(packet->cmap)); ++ ret = rpi_firmware_property(fb->fw, RPI_FIRMWARE_FRAMEBUFFER_SET_PALETTE, ++ packet, (2 + packet->length) * sizeof(u32)); ++ if (ret || packet->offset) ++ dev_err(info->device, "Failed to set palette (%d,%u)\n", ++ ret, packet->offset); ++ kfree(packet); ++ } ++ } else if (regno < 16) { ++ fb->cmap[regno] = convert_bitfield(transp, &fb->fb.var.transp) | ++ convert_bitfield(blue, &fb->fb.var.blue) | ++ convert_bitfield(green, &fb->fb.var.green) | ++ convert_bitfield(red, &fb->fb.var.red); ++ } ++ return regno > 255; ++} ++ ++static int bcm2708_fb_blank(int blank_mode, struct fb_info *info) ++{ ++ struct bcm2708_fb *fb = to_bcm2708(info); ++ u32 value; ++ int ret; ++ ++ switch (blank_mode) { ++ case FB_BLANK_UNBLANK: ++ value = 0; ++ break; ++ case FB_BLANK_NORMAL: ++ case FB_BLANK_VSYNC_SUSPEND: ++ case FB_BLANK_HSYNC_SUSPEND: ++ case FB_BLANK_POWERDOWN: ++ value = 1; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ ret = rpi_firmware_property(fb->fw, RPI_FIRMWARE_FRAMEBUFFER_BLANK, ++ &value, sizeof(value)); ++ if (ret) ++ dev_err(info->device, "bcm2708_fb_blank(%d) failed: %d\n", ++ blank_mode, ret); ++ ++ return ret; ++} ++ ++static int bcm2708_fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) ++{ ++ s32 result; ++ info->var.xoffset = var->xoffset; ++ info->var.yoffset = var->yoffset; ++ result = bcm2708_fb_set_par(info); ++ if (result != 0) ++ pr_err("bcm2708_fb_pan_display(%d,%d) returns=%d\n", var->xoffset, var->yoffset, result); ++ return result; ++} ++ ++static int bcm2708_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg) ++{ ++ struct bcm2708_fb *fb = to_bcm2708(info); ++ u32 dummy = 0; ++ int ret; ++ ++ switch (cmd) { ++ case FBIO_WAITFORVSYNC: ++ ret = rpi_firmware_property(fb->fw, ++ RPI_FIRMWARE_FRAMEBUFFER_SET_VSYNC, ++ &dummy, sizeof(dummy)); ++ break; ++ default: ++ dev_dbg(info->device, "Unknown ioctl 0x%x\n", cmd); ++ return -ENOTTY; ++ } ++ ++ if (ret) ++ dev_err(info->device, "ioctl 0x%x failed (%d)\n", cmd, ret); ++ ++ return ret; ++} ++static void bcm2708_fb_fillrect(struct fb_info *info, ++ const struct fb_fillrect *rect) ++{ ++ /* (is called) print_debug("bcm2708_fb_fillrect\n"); */ ++ cfb_fillrect(info, rect); ++} ++ ++/* A helper function for configuring dma control block */ ++static void set_dma_cb(struct bcm2708_dma_cb *cb, ++ int burst_size, ++ dma_addr_t dst, ++ int dst_stride, ++ dma_addr_t src, ++ int src_stride, ++ int w, ++ int h) ++{ ++ cb->info = BCM2708_DMA_BURST(burst_size) | BCM2708_DMA_S_WIDTH | ++ BCM2708_DMA_S_INC | BCM2708_DMA_D_WIDTH | ++ BCM2708_DMA_D_INC | BCM2708_DMA_TDMODE; ++ cb->dst = dst; ++ cb->src = src; ++ /* ++ * This is not really obvious from the DMA documentation, ++ * but the top 16 bits must be programmmed to "height -1" ++ * and not "height" in 2D mode. ++ */ ++ cb->length = ((h - 1) << 16) | w; ++ cb->stride = ((dst_stride - w) << 16) | (u16)(src_stride - w); ++ cb->pad[0] = 0; ++ cb->pad[1] = 0; ++} ++ ++static void bcm2708_fb_copyarea(struct fb_info *info, ++ const struct fb_copyarea *region) ++{ ++ struct bcm2708_fb *fb = to_bcm2708(info); ++ struct bcm2708_dma_cb *cb = fb->cb_base; ++ int bytes_per_pixel = (info->var.bits_per_pixel + 7) >> 3; ++ /* Channel 0 supports larger bursts and is a bit faster */ ++ int burst_size = (fb->dma_chan == 0) ? 8 : 2; ++ int pixels = region->width * region->height; ++ ++ /* Fallback to cfb_copyarea() if we don't like something */ ++ if (in_atomic() || ++ bytes_per_pixel > 4 || ++ info->var.xres * info->var.yres > 1920 * 1200 || ++ region->width <= 0 || region->width > info->var.xres || ++ region->height <= 0 || region->height > info->var.yres || ++ region->sx < 0 || region->sx >= info->var.xres || ++ region->sy < 0 || region->sy >= info->var.yres || ++ region->dx < 0 || region->dx >= info->var.xres || ++ region->dy < 0 || region->dy >= info->var.yres || ++ region->sx + region->width > info->var.xres || ++ region->dx + region->width > info->var.xres || ++ region->sy + region->height > info->var.yres || ++ region->dy + region->height > info->var.yres) { ++ cfb_copyarea(info, region); ++ return; ++ } ++ ++ if (region->dy == region->sy && region->dx > region->sx) { ++ /* ++ * A difficult case of overlapped copy. Because DMA can't ++ * copy individual scanlines in backwards direction, we need ++ * two-pass processing. We do it by programming a chain of dma ++ * control blocks in the first 16K part of the buffer and use ++ * the remaining 48K as the intermediate temporary scratch ++ * buffer. The buffer size is sufficient to handle up to ++ * 1920x1200 resolution at 32bpp pixel depth. ++ */ ++ int y; ++ dma_addr_t control_block_pa = fb->cb_handle; ++ dma_addr_t scratchbuf = fb->cb_handle + 16 * 1024; ++ int scanline_size = bytes_per_pixel * region->width; ++ int scanlines_per_cb = (64 * 1024 - 16 * 1024) / scanline_size; ++ ++ for (y = 0; y < region->height; y += scanlines_per_cb) { ++ dma_addr_t src = ++ fb->fb_bus_address + ++ bytes_per_pixel * region->sx + ++ (region->sy + y) * fb->fb.fix.line_length; ++ dma_addr_t dst = ++ fb->fb_bus_address + ++ bytes_per_pixel * region->dx + ++ (region->dy + y) * fb->fb.fix.line_length; ++ ++ if (region->height - y < scanlines_per_cb) ++ scanlines_per_cb = region->height - y; ++ ++ set_dma_cb(cb, burst_size, scratchbuf, scanline_size, ++ src, fb->fb.fix.line_length, ++ scanline_size, scanlines_per_cb); ++ control_block_pa += sizeof(struct bcm2708_dma_cb); ++ cb->next = control_block_pa; ++ cb++; ++ ++ set_dma_cb(cb, burst_size, dst, fb->fb.fix.line_length, ++ scratchbuf, scanline_size, ++ scanline_size, scanlines_per_cb); ++ control_block_pa += sizeof(struct bcm2708_dma_cb); ++ cb->next = control_block_pa; ++ cb++; ++ } ++ /* move the pointer back to the last dma control block */ ++ cb--; ++ } else { ++ /* A single dma control block is enough. */ ++ int sy, dy, stride; ++ if (region->dy <= region->sy) { ++ /* processing from top to bottom */ ++ dy = region->dy; ++ sy = region->sy; ++ stride = fb->fb.fix.line_length; ++ } else { ++ /* processing from bottom to top */ ++ dy = region->dy + region->height - 1; ++ sy = region->sy + region->height - 1; ++ stride = -fb->fb.fix.line_length; ++ } ++ set_dma_cb(cb, burst_size, ++ fb->fb_bus_address + dy * fb->fb.fix.line_length + ++ bytes_per_pixel * region->dx, ++ stride, ++ fb->fb_bus_address + sy * fb->fb.fix.line_length + ++ bytes_per_pixel * region->sx, ++ stride, ++ region->width * bytes_per_pixel, ++ region->height); ++ } ++ ++ /* end of dma control blocks chain */ ++ cb->next = 0; ++ ++ ++ if (pixels < dma_busy_wait_threshold) { ++ bcm_dma_start(fb->dma_chan_base, fb->cb_handle); ++ bcm_dma_wait_idle(fb->dma_chan_base); ++ } else { ++ void __iomem *dma_chan = fb->dma_chan_base; ++ cb->info |= BCM2708_DMA_INT_EN; ++ bcm_dma_start(fb->dma_chan_base, fb->cb_handle); ++ while (bcm_dma_is_busy(dma_chan)) { ++ wait_event_interruptible( ++ fb->dma_waitq, ++ !bcm_dma_is_busy(dma_chan)); ++ } ++ fb->stats.dma_irqs++; ++ } ++ fb->stats.dma_copies++; ++} ++ ++static void bcm2708_fb_imageblit(struct fb_info *info, ++ const struct fb_image *image) ++{ ++ /* (is called) print_debug("bcm2708_fb_imageblit\n"); */ ++ cfb_imageblit(info, image); ++} ++ ++static irqreturn_t bcm2708_fb_dma_irq(int irq, void *cxt) ++{ ++ struct bcm2708_fb *fb = cxt; ++ ++ /* FIXME: should read status register to check if this is ++ * actually interrupting us or not, in case this interrupt ++ * ever becomes shared amongst several DMA channels ++ * ++ * readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_IRQ; ++ */ ++ ++ /* acknowledge the interrupt */ ++ writel(BCM2708_DMA_INT, fb->dma_chan_base + BCM2708_DMA_CS); ++ ++ wake_up(&fb->dma_waitq); ++ return IRQ_HANDLED; ++} ++ ++static struct fb_ops bcm2708_fb_ops = { ++ .owner = THIS_MODULE, ++ .fb_check_var = bcm2708_fb_check_var, ++ .fb_set_par = bcm2708_fb_set_par, ++ .fb_setcolreg = bcm2708_fb_setcolreg, ++ .fb_blank = bcm2708_fb_blank, ++ .fb_fillrect = bcm2708_fb_fillrect, ++ .fb_copyarea = bcm2708_fb_copyarea, ++ .fb_imageblit = bcm2708_fb_imageblit, ++ .fb_pan_display = bcm2708_fb_pan_display, ++ .fb_ioctl = bcm2708_ioctl, ++}; ++ ++static int bcm2708_fb_register(struct bcm2708_fb *fb) ++{ ++ int ret; ++ ++ fb->fb.fbops = &bcm2708_fb_ops; ++ fb->fb.flags = FBINFO_FLAG_DEFAULT | FBINFO_HWACCEL_COPYAREA; ++ fb->fb.pseudo_palette = fb->cmap; ++ ++ strncpy(fb->fb.fix.id, bcm2708_name, sizeof(fb->fb.fix.id)); ++ fb->fb.fix.type = FB_TYPE_PACKED_PIXELS; ++ fb->fb.fix.type_aux = 0; ++ fb->fb.fix.xpanstep = 1; ++ fb->fb.fix.ypanstep = 1; ++ fb->fb.fix.ywrapstep = 0; ++ fb->fb.fix.accel = FB_ACCEL_NONE; ++ ++ fb->fb.var.xres = fbwidth; ++ fb->fb.var.yres = fbheight; ++ fb->fb.var.xres_virtual = fbwidth; ++ fb->fb.var.yres_virtual = fbheight; ++ fb->fb.var.bits_per_pixel = fbdepth; ++ fb->fb.var.vmode = FB_VMODE_NONINTERLACED; ++ fb->fb.var.activate = FB_ACTIVATE_NOW; ++ fb->fb.var.nonstd = 0; ++ fb->fb.var.height = -1; /* height of picture in mm */ ++ fb->fb.var.width = -1; /* width of picture in mm */ ++ fb->fb.var.accel_flags = 0; ++ ++ fb->fb.monspecs.hfmin = 0; ++ fb->fb.monspecs.hfmax = 100000; ++ fb->fb.monspecs.vfmin = 0; ++ fb->fb.monspecs.vfmax = 400; ++ fb->fb.monspecs.dclkmin = 1000000; ++ fb->fb.monspecs.dclkmax = 100000000; ++ ++ bcm2708_fb_set_bitfields(&fb->fb.var); ++ init_waitqueue_head(&fb->dma_waitq); ++ ++ /* ++ * Allocate colourmap. ++ */ ++ ++ fb_set_var(&fb->fb, &fb->fb.var); ++ ret = bcm2708_fb_set_par(&fb->fb); ++ if (ret) ++ return ret; ++ ++ print_debug("BCM2708FB: registering framebuffer (%dx%d@%d) (%d)\n", fbwidth, ++ fbheight, fbdepth, fbswap); ++ ++ ret = register_framebuffer(&fb->fb); ++ print_debug("BCM2708FB: register framebuffer (%d)\n", ret); ++ if (ret == 0) ++ goto out; ++ ++ print_debug("BCM2708FB: cannot register framebuffer (%d)\n", ret); ++out: ++ return ret; ++} ++ ++static int bcm2708_fb_probe(struct platform_device *dev) ++{ ++ struct device_node *fw_np; ++ struct rpi_firmware *fw; ++ struct bcm2708_fb *fb; ++ int ret; ++ ++ fw_np = of_parse_phandle(dev->dev.of_node, "firmware", 0); ++/* Remove comment when booting without Device Tree is no longer supported ++ if (!fw_np) { ++ dev_err(&dev->dev, "Missing firmware node\n"); ++ return -ENOENT; ++ } ++*/ ++ fw = rpi_firmware_get(fw_np); ++ if (!fw) ++ return -EPROBE_DEFER; ++ ++ fb = kzalloc(sizeof(struct bcm2708_fb), GFP_KERNEL); ++ if (!fb) { ++ dev_err(&dev->dev, ++ "could not allocate new bcm2708_fb struct\n"); ++ ret = -ENOMEM; ++ goto free_region; ++ } ++ ++ fb->fw = fw; ++ bcm2708_fb_debugfs_init(fb); ++ ++ fb->cb_base = dma_alloc_writecombine(&dev->dev, SZ_64K, ++ &fb->cb_handle, GFP_KERNEL); ++ if (!fb->cb_base) { ++ dev_err(&dev->dev, "cannot allocate DMA CBs\n"); ++ ret = -ENOMEM; ++ goto free_fb; ++ } ++ ++ pr_info("BCM2708FB: allocated DMA memory %08x\n", ++ fb->cb_handle); ++ ++ ret = bcm_dma_chan_alloc(BCM_DMA_FEATURE_BULK, ++ &fb->dma_chan_base, &fb->dma_irq); ++ if (ret < 0) { ++ dev_err(&dev->dev, "couldn't allocate a DMA channel\n"); ++ goto free_cb; ++ } ++ fb->dma_chan = ret; ++ ++ ret = request_irq(fb->dma_irq, bcm2708_fb_dma_irq, ++ 0, "bcm2708_fb dma", fb); ++ if (ret) { ++ pr_err("%s: failed to request DMA irq\n", __func__); ++ goto free_dma_chan; ++ } ++ ++ ++ pr_info("BCM2708FB: allocated DMA channel %d @ %p\n", ++ fb->dma_chan, fb->dma_chan_base); ++ ++ fb->dev = dev; ++ fb->fb.device = &dev->dev; ++ ++ ret = bcm2708_fb_register(fb); ++ if (ret == 0) { ++ platform_set_drvdata(dev, fb); ++ goto out; ++ } ++ ++free_dma_chan: ++ bcm_dma_chan_free(fb->dma_chan); ++free_cb: ++ dma_free_writecombine(&dev->dev, SZ_64K, fb->cb_base, fb->cb_handle); ++free_fb: ++ kfree(fb); ++free_region: ++ dev_err(&dev->dev, "probe failed, err %d\n", ret); ++out: ++ return ret; ++} ++ ++static int bcm2708_fb_remove(struct platform_device *dev) ++{ ++ struct bcm2708_fb *fb = platform_get_drvdata(dev); ++ ++ platform_set_drvdata(dev, NULL); ++ ++ if (fb->fb.screen_base) ++ iounmap(fb->fb.screen_base); ++ unregister_framebuffer(&fb->fb); ++ ++ dma_free_writecombine(&dev->dev, SZ_64K, fb->cb_base, fb->cb_handle); ++ bcm_dma_chan_free(fb->dma_chan); ++ ++ bcm2708_fb_debugfs_deinit(fb); ++ ++ free_irq(fb->dma_irq, fb); ++ ++ kfree(fb); ++ ++ return 0; ++} ++ ++static const struct of_device_id bcm2708_fb_of_match_table[] = { ++ { .compatible = "brcm,bcm2708-fb", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, bcm2708_fb_of_match_table); ++ ++static struct platform_driver bcm2708_fb_driver = { ++ .probe = bcm2708_fb_probe, ++ .remove = bcm2708_fb_remove, ++ .driver = { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = bcm2708_fb_of_match_table, ++ }, ++}; ++ ++static int __init bcm2708_fb_init(void) ++{ ++ return platform_driver_register(&bcm2708_fb_driver); ++} ++ ++module_init(bcm2708_fb_init); ++ ++static void __exit bcm2708_fb_exit(void) ++{ ++ platform_driver_unregister(&bcm2708_fb_driver); ++} ++ ++module_exit(bcm2708_fb_exit); ++ ++module_param(fbwidth, int, 0644); ++module_param(fbheight, int, 0644); ++module_param(fbdepth, int, 0644); ++module_param(fbswap, int, 0644); ++ ++MODULE_DESCRIPTION("BCM2708 framebuffer driver"); ++MODULE_LICENSE("GPL"); ++ ++MODULE_PARM_DESC(fbwidth, "Width of ARM Framebuffer"); ++MODULE_PARM_DESC(fbheight, "Height of ARM Framebuffer"); ++MODULE_PARM_DESC(fbdepth, "Bit depth of ARM Framebuffer"); ++MODULE_PARM_DESC(fbswap, "Swap order of red and blue in 24 and 32 bit modes"); +diff -Nur linux-4.1.13.orig/drivers/video/fbdev/core/cfbimgblt.c linux-rpi/drivers/video/fbdev/core/cfbimgblt.c +--- linux-4.1.13.orig/drivers/video/fbdev/core/cfbimgblt.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/video/fbdev/core/cfbimgblt.c 2015-11-29 09:42:40.075088329 +0100 +@@ -28,6 +28,11 @@ + * + * Also need to add code to deal with cards endians that are different than + * the native cpu endians. I also need to deal with MSB position in the word. ++ * Modified by Harm Hanemaaijer (fgenfb@yahoo.com) 2013: ++ * - Provide optimized versions of fast_imageblit for 16 and 32bpp that are ++ * significantly faster than the previous implementation. ++ * - Simplify the fast/slow_imageblit selection code, avoiding integer ++ * divides. + */ + #include + #include +@@ -262,6 +267,133 @@ + } + } + ++/* ++ * Optimized fast_imageblit for bpp == 16. ppw = 2, bit_mask = 3 folded ++ * into the code, main loop unrolled. ++ */ ++ ++static inline void fast_imageblit16(const struct fb_image *image, ++ struct fb_info *p, u8 __iomem * dst1, ++ u32 fgcolor, u32 bgcolor) ++{ ++ u32 fgx = fgcolor, bgx = bgcolor; ++ u32 spitch = (image->width + 7) / 8; ++ u32 end_mask, eorx; ++ const char *s = image->data, *src; ++ u32 __iomem *dst; ++ const u32 *tab = NULL; ++ int i, j, k; ++ ++ tab = fb_be_math(p) ? cfb_tab16_be : cfb_tab16_le; ++ ++ fgx <<= 16; ++ bgx <<= 16; ++ fgx |= fgcolor; ++ bgx |= bgcolor; ++ ++ eorx = fgx ^ bgx; ++ k = image->width / 2; ++ ++ for (i = image->height; i--;) { ++ dst = (u32 __iomem *) dst1; ++ src = s; ++ ++ j = k; ++ while (j >= 4) { ++ u8 bits = *src; ++ end_mask = tab[(bits >> 6) & 3]; ++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); ++ end_mask = tab[(bits >> 4) & 3]; ++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); ++ end_mask = tab[(bits >> 2) & 3]; ++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); ++ end_mask = tab[bits & 3]; ++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); ++ src++; ++ j -= 4; ++ } ++ if (j != 0) { ++ u8 bits = *src; ++ end_mask = tab[(bits >> 6) & 3]; ++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); ++ if (j >= 2) { ++ end_mask = tab[(bits >> 4) & 3]; ++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); ++ if (j == 3) { ++ end_mask = tab[(bits >> 2) & 3]; ++ FB_WRITEL((end_mask & eorx) ^ bgx, dst); ++ } ++ } ++ } ++ dst1 += p->fix.line_length; ++ s += spitch; ++ } ++} ++ ++/* ++ * Optimized fast_imageblit for bpp == 32. ppw = 1, bit_mask = 1 folded ++ * into the code, main loop unrolled. ++ */ ++ ++static inline void fast_imageblit32(const struct fb_image *image, ++ struct fb_info *p, u8 __iomem * dst1, ++ u32 fgcolor, u32 bgcolor) ++{ ++ u32 fgx = fgcolor, bgx = bgcolor; ++ u32 spitch = (image->width + 7) / 8; ++ u32 end_mask, eorx; ++ const char *s = image->data, *src; ++ u32 __iomem *dst; ++ const u32 *tab = NULL; ++ int i, j, k; ++ ++ tab = cfb_tab32; ++ ++ eorx = fgx ^ bgx; ++ k = image->width; ++ ++ for (i = image->height; i--;) { ++ dst = (u32 __iomem *) dst1; ++ src = s; ++ ++ j = k; ++ while (j >= 8) { ++ u8 bits = *src; ++ end_mask = tab[(bits >> 7) & 1]; ++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); ++ end_mask = tab[(bits >> 6) & 1]; ++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); ++ end_mask = tab[(bits >> 5) & 1]; ++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); ++ end_mask = tab[(bits >> 4) & 1]; ++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); ++ end_mask = tab[(bits >> 3) & 1]; ++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); ++ end_mask = tab[(bits >> 2) & 1]; ++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); ++ end_mask = tab[(bits >> 1) & 1]; ++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); ++ end_mask = tab[bits & 1]; ++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); ++ src++; ++ j -= 8; ++ } ++ if (j != 0) { ++ u32 bits = (u32) * src; ++ while (j > 1) { ++ end_mask = tab[(bits >> 7) & 1]; ++ FB_WRITEL((end_mask & eorx) ^ bgx, dst++); ++ bits <<= 1; ++ j--; ++ } ++ end_mask = tab[(bits >> 7) & 1]; ++ FB_WRITEL((end_mask & eorx) ^ bgx, dst); ++ } ++ dst1 += p->fix.line_length; ++ s += spitch; ++ } ++} ++ + void cfb_imageblit(struct fb_info *p, const struct fb_image *image) + { + u32 fgcolor, bgcolor, start_index, bitstart, pitch_index = 0; +@@ -294,11 +426,21 @@ + bgcolor = image->bg_color; + } + +- if (32 % bpp == 0 && !start_index && !pitch_index && +- ((width & (32/bpp-1)) == 0) && +- bpp >= 8 && bpp <= 32) +- fast_imageblit(image, p, dst1, fgcolor, bgcolor); +- else ++ if (!start_index && !pitch_index) { ++ if (bpp == 32) ++ fast_imageblit32(image, p, dst1, fgcolor, ++ bgcolor); ++ else if (bpp == 16 && (width & 1) == 0) ++ fast_imageblit16(image, p, dst1, fgcolor, ++ bgcolor); ++ else if (bpp == 8 && (width & 3) == 0) ++ fast_imageblit(image, p, dst1, fgcolor, ++ bgcolor); ++ else ++ slow_imageblit(image, p, dst1, fgcolor, ++ bgcolor, ++ start_index, pitch_index); ++ } else + slow_imageblit(image, p, dst1, fgcolor, bgcolor, + start_index, pitch_index); + } else +diff -Nur linux-4.1.13.orig/drivers/video/fbdev/core/fbmem.c linux-rpi/drivers/video/fbdev/core/fbmem.c +--- linux-4.1.13.orig/drivers/video/fbdev/core/fbmem.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/video/fbdev/core/fbmem.c 2015-11-29 09:42:40.075088329 +0100 +@@ -1084,6 +1084,25 @@ + } + EXPORT_SYMBOL(fb_blank); + ++static int fb_copyarea_user(struct fb_info *info, ++ struct fb_copyarea *copy) ++{ ++ int ret = 0; ++ if (!lock_fb_info(info)) ++ return -ENODEV; ++ if (copy->dx + copy->width > info->var.xres || ++ copy->sx + copy->width > info->var.xres || ++ copy->dy + copy->height > info->var.yres || ++ copy->sy + copy->height > info->var.yres) { ++ ret = -EINVAL; ++ goto out; ++ } ++ info->fbops->fb_copyarea(info, copy); ++out: ++ unlock_fb_info(info); ++ return ret; ++} ++ + static long do_fb_ioctl(struct fb_info *info, unsigned int cmd, + unsigned long arg) + { +@@ -1094,6 +1113,7 @@ + struct fb_cmap cmap_from; + struct fb_cmap_user cmap; + struct fb_event event; ++ struct fb_copyarea copy; + void __user *argp = (void __user *)arg; + long ret = 0; + +@@ -1211,6 +1231,15 @@ + unlock_fb_info(info); + console_unlock(); + break; ++ case FBIOCOPYAREA: ++ if (info->flags & FBINFO_HWACCEL_COPYAREA) { ++ /* only provide this ioctl if it is accelerated */ ++ if (copy_from_user(©, argp, sizeof(copy))) ++ return -EFAULT; ++ ret = fb_copyarea_user(info, ©); ++ break; ++ } ++ /* fall through */ + default: + if (!lock_fb_info(info)) + return -ENODEV; +@@ -1365,6 +1394,7 @@ + case FBIOPAN_DISPLAY: + case FBIOGET_CON2FBMAP: + case FBIOPUT_CON2FBMAP: ++ case FBIOCOPYAREA: + arg = (unsigned long) compat_ptr(arg); + case FBIOBLANK: + ret = do_fb_ioctl(info, cmd, arg); +diff -Nur linux-4.1.13.orig/drivers/video/fbdev/Kconfig linux-rpi/drivers/video/fbdev/Kconfig +--- linux-4.1.13.orig/drivers/video/fbdev/Kconfig 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/video/fbdev/Kconfig 2015-11-29 09:42:40.031091253 +0100 +@@ -224,6 +224,20 @@ + comment "Frame buffer hardware drivers" + depends on FB + ++config FB_BCM2708 ++ tristate "BCM2708 framebuffer support" ++ depends on FB && RASPBERRYPI_FIRMWARE ++ select FB_CFB_FILLRECT ++ select FB_CFB_COPYAREA ++ select FB_CFB_IMAGEBLIT ++ help ++ This framebuffer device driver is for the BCM2708 framebuffer. ++ ++ If you want to compile this as a module (=code which can be ++ inserted into and removed from the running kernel), say M ++ here and read . The module ++ will be called bcm2708_fb. ++ + config FB_GRVGA + tristate "Aeroflex Gaisler framebuffer support" + depends on FB && SPARC +@@ -2481,3 +2495,16 @@ + help + This driver implements support for the Solomon SSD1307 + OLED controller over I2C. ++ ++config FB_RPISENSE ++ tristate "Raspberry Pi Sense HAT framebuffer" ++ depends on FB ++ select MFD_RPISENSE_CORE ++ select FB_SYS_FOPS ++ select FB_SYS_FILLRECT ++ select FB_SYS_COPYAREA ++ select FB_SYS_IMAGEBLIT ++ select FB_DEFERRED_IO ++ ++ help ++ This is the framebuffer driver for the Raspberry Pi Sense HAT +diff -Nur linux-4.1.13.orig/drivers/video/fbdev/Makefile linux-rpi/drivers/video/fbdev/Makefile +--- linux-4.1.13.orig/drivers/video/fbdev/Makefile 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/video/fbdev/Makefile 2015-11-29 09:42:40.031091253 +0100 +@@ -12,6 +12,7 @@ + obj-$(CONFIG_FB_WMT_GE_ROPS) += wmt_ge_rops.o + + # Hardware specific drivers go first ++obj-$(CONFIG_FB_BCM2708) += bcm2708_fb.o + obj-$(CONFIG_FB_AMIGA) += amifb.o c2p_planar.o + obj-$(CONFIG_FB_ARC) += arcfb.o + obj-$(CONFIG_FB_CLPS711X) += clps711x-fb.o +@@ -149,6 +150,7 @@ + obj-$(CONFIG_FB_MXS) += mxsfb.o + obj-$(CONFIG_FB_SSD1307) += ssd1307fb.o + obj-$(CONFIG_FB_SIMPLE) += simplefb.o ++obj-$(CONFIG_FB_RPISENSE) += rpisense-fb.o + + # the test framebuffer is last + obj-$(CONFIG_FB_VIRTUAL) += vfb.o +diff -Nur linux-4.1.13.orig/drivers/video/fbdev/rpisense-fb.c linux-rpi/drivers/video/fbdev/rpisense-fb.c +--- linux-4.1.13.orig/drivers/video/fbdev/rpisense-fb.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/video/fbdev/rpisense-fb.c 2015-11-29 09:42:40.111085937 +0100 +@@ -0,0 +1,293 @@ ++/* ++ * Raspberry Pi Sense HAT framebuffer driver ++ * http://raspberrypi.org ++ * ++ * Copyright (C) 2015 Raspberry Pi ++ * ++ * Author: Serge Schneider ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++static bool lowlight; ++module_param(lowlight, bool, 0); ++MODULE_PARM_DESC(lowlight, "Reduce LED matrix brightness to one third"); ++ ++struct rpisense *rpisense; ++ ++struct rpisense_fb_param { ++ char __iomem *vmem; ++ u8 *vmem_work; ++ u32 vmemsize; ++ u8 *gamma; ++}; ++ ++static u8 gamma_default[32] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, ++ 0x02, 0x02, 0x03, 0x03, 0x04, 0x05, 0x06, 0x07, ++ 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0E, 0x0F, 0x11, ++ 0x12, 0x14, 0x15, 0x17, 0x19, 0x1B, 0x1D, 0x1F,}; ++ ++static u8 gamma_low[32] = {0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, ++ 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x02, 0x02, ++ 0x03, 0x03, 0x03, 0x04, 0x04, 0x05, 0x05, 0x06, ++ 0x06, 0x07, 0x07, 0x08, 0x08, 0x09, 0x0A, 0x0A,}; ++ ++static u8 gamma_user[32]; ++ ++static struct rpisense_fb_param rpisense_fb_param = { ++ .vmem = NULL, ++ .vmemsize = 128, ++ .gamma = gamma_default, ++}; ++ ++static struct fb_deferred_io rpisense_fb_defio; ++ ++static struct fb_fix_screeninfo rpisense_fb_fix = { ++ .id = "RPi-Sense FB", ++ .type = FB_TYPE_PACKED_PIXELS, ++ .visual = FB_VISUAL_TRUECOLOR, ++ .xpanstep = 0, ++ .ypanstep = 0, ++ .ywrapstep = 0, ++ .accel = FB_ACCEL_NONE, ++ .line_length = 16, ++}; ++ ++static struct fb_var_screeninfo rpisense_fb_var = { ++ .xres = 8, ++ .yres = 8, ++ .xres_virtual = 8, ++ .yres_virtual = 8, ++ .bits_per_pixel = 16, ++ .red = {11, 5, 0}, ++ .green = {5, 6, 0}, ++ .blue = {0, 5, 0}, ++}; ++ ++static ssize_t rpisense_fb_write(struct fb_info *info, ++ const char __user *buf, size_t count, ++ loff_t *ppos) ++{ ++ ssize_t res = fb_sys_write(info, buf, count, ppos); ++ ++ schedule_delayed_work(&info->deferred_work, rpisense_fb_defio.delay); ++ return res; ++} ++ ++static void rpisense_fb_fillrect(struct fb_info *info, ++ const struct fb_fillrect *rect) ++{ ++ sys_fillrect(info, rect); ++ schedule_delayed_work(&info->deferred_work, rpisense_fb_defio.delay); ++} ++ ++static void rpisense_fb_copyarea(struct fb_info *info, ++ const struct fb_copyarea *area) ++{ ++ sys_copyarea(info, area); ++ schedule_delayed_work(&info->deferred_work, rpisense_fb_defio.delay); ++} ++ ++static void rpisense_fb_imageblit(struct fb_info *info, ++ const struct fb_image *image) ++{ ++ sys_imageblit(info, image); ++ schedule_delayed_work(&info->deferred_work, rpisense_fb_defio.delay); ++} ++ ++static void rpisense_fb_deferred_io(struct fb_info *info, ++ struct list_head *pagelist) ++{ ++ int i; ++ int j; ++ u8 *vmem_work = rpisense_fb_param.vmem_work; ++ u16 *mem = (u16 *)rpisense_fb_param.vmem; ++ u8 *gamma = rpisense_fb_param.gamma; ++ ++ vmem_work[0] = 0; ++ for (j = 0; j < 8; j++) { ++ for (i = 0; i < 8; i++) { ++ vmem_work[(j * 24) + i + 1] = ++ gamma[(mem[(j * 8) + i] >> 11) & 0x1F]; ++ vmem_work[(j * 24) + (i + 8) + 1] = ++ gamma[(mem[(j * 8) + i] >> 6) & 0x1F]; ++ vmem_work[(j * 24) + (i + 16) + 1] = ++ gamma[(mem[(j * 8) + i]) & 0x1F]; ++ } ++ } ++ rpisense_block_write(rpisense, vmem_work, 193); ++} ++ ++static struct fb_deferred_io rpisense_fb_defio = { ++ .delay = HZ/100, ++ .deferred_io = rpisense_fb_deferred_io, ++}; ++ ++static int rpisense_fb_ioctl(struct fb_info *info, unsigned int cmd, ++ unsigned long arg) ++{ ++ switch (cmd) { ++ case SENSEFB_FBIOGET_GAMMA: ++ if (copy_to_user((void __user *) arg, rpisense_fb_param.gamma, ++ sizeof(u8[32]))) ++ return -EFAULT; ++ return 0; ++ case SENSEFB_FBIOSET_GAMMA: ++ if (copy_from_user(gamma_user, (void __user *)arg, ++ sizeof(u8[32]))) ++ return -EFAULT; ++ rpisense_fb_param.gamma = gamma_user; ++ schedule_delayed_work(&info->deferred_work, ++ rpisense_fb_defio.delay); ++ return 0; ++ case SENSEFB_FBIORESET_GAMMA: ++ switch (arg) { ++ case 0: ++ rpisense_fb_param.gamma = gamma_default; ++ break; ++ case 1: ++ rpisense_fb_param.gamma = gamma_low; ++ break; ++ case 2: ++ rpisense_fb_param.gamma = gamma_user; ++ break; ++ default: ++ return -EINVAL; ++ } ++ schedule_delayed_work(&info->deferred_work, ++ rpisense_fb_defio.delay); ++ break; ++ default: ++ return -EINVAL; ++ } ++ return 0; ++} ++ ++static struct fb_ops rpisense_fb_ops = { ++ .owner = THIS_MODULE, ++ .fb_read = fb_sys_read, ++ .fb_write = rpisense_fb_write, ++ .fb_fillrect = rpisense_fb_fillrect, ++ .fb_copyarea = rpisense_fb_copyarea, ++ .fb_imageblit = rpisense_fb_imageblit, ++ .fb_ioctl = rpisense_fb_ioctl, ++}; ++ ++static int rpisense_fb_probe(struct platform_device *pdev) ++{ ++ struct fb_info *info; ++ int ret = -ENOMEM; ++ struct rpisense_fb *rpisense_fb; ++ ++ rpisense = rpisense_get_dev(); ++ rpisense_fb = &rpisense->framebuffer; ++ ++ rpisense_fb_param.vmem = vzalloc(rpisense_fb_param.vmemsize); ++ if (!rpisense_fb_param.vmem) ++ return ret; ++ ++ rpisense_fb_param.vmem_work = devm_kmalloc(&pdev->dev, 193, GFP_KERNEL); ++ if (!rpisense_fb_param.vmem_work) ++ goto err_malloc; ++ ++ info = framebuffer_alloc(0, &pdev->dev); ++ if (!info) { ++ dev_err(&pdev->dev, "Could not allocate framebuffer.\n"); ++ goto err_malloc; ++ } ++ rpisense_fb->info = info; ++ ++ rpisense_fb_fix.smem_start = (unsigned long)rpisense_fb_param.vmem; ++ rpisense_fb_fix.smem_len = rpisense_fb_param.vmemsize; ++ ++ info->fbops = &rpisense_fb_ops; ++ info->fix = rpisense_fb_fix; ++ info->var = rpisense_fb_var; ++ info->fbdefio = &rpisense_fb_defio; ++ info->flags = FBINFO_FLAG_DEFAULT | FBINFO_VIRTFB; ++ info->screen_base = rpisense_fb_param.vmem; ++ info->screen_size = rpisense_fb_param.vmemsize; ++ ++ if (lowlight) ++ rpisense_fb_param.gamma = gamma_low; ++ ++ fb_deferred_io_init(info); ++ ++ ret = register_framebuffer(info); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "Could not register framebuffer.\n"); ++ goto err_fballoc; ++ } ++ ++ fb_info(info, "%s frame buffer device\n", info->fix.id); ++ schedule_delayed_work(&info->deferred_work, rpisense_fb_defio.delay); ++ return 0; ++err_fballoc: ++ framebuffer_release(info); ++err_malloc: ++ vfree(rpisense_fb_param.vmem); ++ return ret; ++} ++ ++static int rpisense_fb_remove(struct platform_device *pdev) ++{ ++ struct rpisense_fb *rpisense_fb = &rpisense->framebuffer; ++ struct fb_info *info = rpisense_fb->info; ++ ++ if (info) { ++ unregister_framebuffer(info); ++ fb_deferred_io_cleanup(info); ++ framebuffer_release(info); ++ vfree(rpisense_fb_param.vmem); ++ } ++ ++ return 0; ++} ++ ++#ifdef CONFIG_OF ++static const struct of_device_id rpisense_fb_id[] = { ++ { .compatible = "rpi,rpi-sense-fb" }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, rpisense_fb_id); ++#endif ++ ++static struct platform_device_id rpisense_fb_device_id[] = { ++ { .name = "rpi-sense-fb" }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(platform, rpisense_fb_device_id); ++ ++static struct platform_driver rpisense_fb_driver = { ++ .probe = rpisense_fb_probe, ++ .remove = rpisense_fb_remove, ++ .driver = { ++ .name = "rpi-sense-fb", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++module_platform_driver(rpisense_fb_driver); ++ ++MODULE_DESCRIPTION("Raspberry Pi Sense HAT framebuffer driver"); ++MODULE_AUTHOR("Serge Schneider "); ++MODULE_LICENSE("GPL"); ++ +diff -Nur linux-4.1.13.orig/drivers/video/logo/logo_linux_clut224.ppm linux-rpi/drivers/video/logo/logo_linux_clut224.ppm +--- linux-4.1.13.orig/drivers/video/logo/logo_linux_clut224.ppm 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/video/logo/logo_linux_clut224.ppm 2015-11-29 09:42:40.131084608 +0100 +@@ -1,1604 +1,883 @@ + P3 +-# Standard 224-color Linux logo +-80 80 ++63 80 + 255 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 6 6 6 6 6 6 10 10 10 10 10 10 +- 10 10 10 6 6 6 6 6 6 6 6 6 +- 0 0 0 0 0 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146 13 51 10 1 4 ++0 0 0 38 3 13 166 15 58 190 17 67 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++183 17 64 52 5 18 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 13 1 5 154 14 54 190 17 67 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++186 17 65 79 7 28 0 0 0 0 0 0 14 1 5 156 14 54 ++190 17 67 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 191 17 67 124 11 43 2 0 1 ++5 0 2 122 11 43 191 17 67 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++182 16 64 47 4 16 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 3 0 1 126 14 44 191 17 67 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++190 17 67 158 14 55 23 2 8 0 0 0 1 0 0 113 10 40 ++191 17 67 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 78 7 27 0 0 0 ++47 4 16 177 16 62 189 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 189 17 66 ++173 16 61 34 3 12 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 85 8 30 189 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 79 7 28 0 0 0 0 0 0 47 4 16 ++175 16 62 189 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 190 17 67 156 14 55 22 2 8 0 0 0 ++109 10 38 191 17 67 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 190 17 67 ++151 14 53 13 1 5 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 35 3 12 173 16 61 189 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 191 17 67 134 12 47 7 1 2 0 0 0 3 0 1 ++99 9 35 188 17 66 189 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 189 17 66 181 16 63 68 6 24 0 0 0 18 2 6 ++156 14 55 190 17 67 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 190 17 67 ++101 9 35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 3 0 1 118 13 41 191 17 67 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 189 17 66 168 15 59 28 3 10 0 0 0 0 0 0 ++12 1 4 113 10 40 187 17 66 189 17 67 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++190 17 67 180 16 63 88 8 31 4 0 1 0 0 0 47 4 16 ++180 16 63 189 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 190 17 67 168 15 59 ++36 3 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 38 3 13 164 15 58 190 17 67 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 182 16 64 50 5 17 0 0 0 0 0 0 ++0 0 0 11 1 4 90 8 32 169 15 59 190 17 67 190 17 67 ++189 17 66 189 17 66 189 17 66 189 17 66 191 17 67 189 17 66 ++158 14 55 68 6 24 4 0 1 0 0 0 0 0 0 73 7 26 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 189 17 66 185 17 65 83 8 29 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 65 6 23 174 16 61 ++190 17 67 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 185 17 65 56 5 19 0 0 0 0 0 0 ++0 0 0 0 0 0 2 0 1 35 3 12 99 9 35 146 13 51 ++170 15 60 177 16 62 177 16 62 166 15 58 141 13 49 85 8 30 ++24 2 8 0 0 0 0 0 0 0 0 0 0 0 0 85 8 30 ++190 17 67 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 189 17 66 112 10 39 8 1 3 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 68 6 24 ++170 15 60 191 17 67 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 182 16 64 50 5 17 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 11 1 4 ++28 3 10 40 4 14 38 3 13 25 2 9 8 1 3 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 78 7 27 ++189 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 189 17 66 187 17 66 113 10 40 14 1 5 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 ++47 4 16 141 13 49 186 17 65 191 17 67 190 17 67 189 17 66 ++189 17 66 191 17 67 156 14 55 20 2 7 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 44 4 15 ++178 16 62 190 17 67 188 17 66 188 17 66 188 17 66 190 17 67 ++191 17 67 173 16 61 90 8 32 10 1 4 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 14 1 5 68 6 24 131 12 46 162 15 57 174 16 61 ++171 15 60 146 13 51 56 5 19 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 3 0 1 14 1 5 29 3 10 ++41 4 14 47 4 16 50 5 17 45 4 16 34 3 12 18 2 6 ++5 0 2 0 0 0 0 0 0 0 0 0 0 0 0 5 0 2 ++90 8 32 169 15 59 185 17 65 187 17 66 182 16 64 163 15 57 ++113 10 40 41 4 14 2 0 1 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 5 0 2 21 2 7 34 3 12 ++29 3 10 11 1 4 0 0 0 0 0 0 0 0 0 0 0 0 ++3 0 1 32 3 11 79 7 28 124 11 43 154 14 54 171 15 60 ++180 16 63 182 16 64 182 16 64 180 16 63 174 16 61 159 14 56 ++132 12 46 88 8 31 34 3 12 3 0 1 0 0 0 0 0 0 ++3 0 1 29 3 10 56 5 19 65 6 23 50 5 17 23 2 8 ++3 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 2 9 ++109 10 38 169 15 59 189 17 66 191 17 67 190 17 67 189 17 66 ++189 17 66 188 17 66 188 17 66 188 17 66 189 17 66 190 17 67 ++191 17 67 190 17 67 171 15 60 98 9 34 10 1 3 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 14 1 5 141 13 49 ++191 17 67 189 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 189 17 67 186 17 65 65 6 23 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 23 2 8 166 15 58 ++190 17 67 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 189 17 66 176 16 62 45 4 16 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 83 8 29 ++183 17 64 189 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 189 17 66 185 17 65 95 9 33 3 0 1 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 2 ++85 8 30 176 16 62 191 17 67 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++191 17 67 180 16 63 95 9 33 7 1 3 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++2 0 1 52 5 18 141 13 49 185 17 65 191 17 67 189 17 67 ++189 17 66 188 17 66 188 17 66 189 17 66 191 17 67 187 17 66 ++146 13 51 56 5 19 4 0 1 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 14 1 5 68 6 24 131 12 46 166 15 58 ++180 16 63 183 17 64 180 16 63 168 15 59 134 12 47 75 7 26 ++17 2 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 5 0 2 24 2 8 ++44 4 15 52 5 18 45 4 16 26 2 9 6 1 2 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 +diff -Nur linux-4.1.13.orig/drivers/w1/masters/w1-gpio.c linux-rpi/drivers/w1/masters/w1-gpio.c +--- linux-4.1.13.orig/drivers/w1/masters/w1-gpio.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/w1/masters/w1-gpio.c 2015-11-29 09:42:40.139084077 +0100 +@@ -23,6 +23,19 @@ + #include "../w1.h" + #include "../w1_int.h" + ++static int w1_gpio_pullup = 0; ++static int w1_gpio_pullup_orig = 0; ++module_param_named(pullup, w1_gpio_pullup, int, 0); ++MODULE_PARM_DESC(pullup, "Enable parasitic power (power on data) mode"); ++static int w1_gpio_pullup_pin = -1; ++static int w1_gpio_pullup_pin_orig = -1; ++module_param_named(extpullup, w1_gpio_pullup_pin, int, 0); ++MODULE_PARM_DESC(extpullup, "GPIO external pullup pin number"); ++static int w1_gpio_pin = -1; ++static int w1_gpio_pin_orig = -1; ++module_param_named(gpiopin, w1_gpio_pin, int, 0); ++MODULE_PARM_DESC(gpiopin, "GPIO pin number"); ++ + static u8 w1_gpio_set_pullup(void *data, int delay) + { + struct w1_gpio_platform_data *pdata = data; +@@ -67,6 +80,16 @@ + return gpio_get_value(pdata->pin) ? 1 : 0; + } + ++static void w1_gpio_bitbang_pullup(void *data, u8 on) ++{ ++ struct w1_gpio_platform_data *pdata = data; ++ ++ if (on) ++ gpio_direction_output(pdata->pin, 1); ++ else ++ gpio_direction_input(pdata->pin); ++} ++ + #if defined(CONFIG_OF) + static const struct of_device_id w1_gpio_dt_ids[] = { + { .compatible = "w1-gpio" }, +@@ -80,6 +103,7 @@ + struct w1_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev); + struct device_node *np = pdev->dev.of_node; + int gpio; ++ u32 value; + + pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); + if (!pdata) +@@ -88,6 +112,9 @@ + if (of_get_property(np, "linux,open-drain", NULL)) + pdata->is_open_drain = 1; + ++ if (of_property_read_u32(np, "rpi,parasitic-power", &value) == 0) ++ pdata->parasitic_power = (value != 0); ++ + gpio = of_get_gpio(np, 0); + if (gpio < 0) { + if (gpio != -EPROBE_DEFER) +@@ -103,7 +130,7 @@ + if (gpio == -EPROBE_DEFER) + return gpio; + /* ignore other errors as the pullup gpio is optional */ +- pdata->ext_pullup_enable_pin = gpio; ++ pdata->ext_pullup_enable_pin = (gpio >= 0) ? gpio : -1; + + pdev->dev.platform_data = pdata; + +@@ -113,13 +140,15 @@ + static int w1_gpio_probe(struct platform_device *pdev) + { + struct w1_bus_master *master; +- struct w1_gpio_platform_data *pdata; ++ struct w1_gpio_platform_data *pdata = pdev->dev.platform_data; + int err; + +- if (of_have_populated_dt()) { +- err = w1_gpio_probe_dt(pdev); +- if (err < 0) +- return err; ++ if(pdata == NULL) { ++ if (of_have_populated_dt()) { ++ err = w1_gpio_probe_dt(pdev); ++ if (err < 0) ++ return err; ++ } + } + + pdata = dev_get_platdata(&pdev->dev); +@@ -136,6 +165,22 @@ + return -ENOMEM; + } + ++ w1_gpio_pin_orig = pdata->pin; ++ w1_gpio_pullup_pin_orig = pdata->ext_pullup_enable_pin; ++ w1_gpio_pullup_orig = pdata->parasitic_power; ++ ++ if(gpio_is_valid(w1_gpio_pin)) { ++ pdata->pin = w1_gpio_pin; ++ pdata->ext_pullup_enable_pin = -1; ++ pdata->parasitic_power = -1; ++ } ++ pdata->parasitic_power |= w1_gpio_pullup; ++ if(gpio_is_valid(w1_gpio_pullup_pin)) { ++ pdata->ext_pullup_enable_pin = w1_gpio_pullup_pin; ++ } ++ ++ dev_info(&pdev->dev, "gpio pin %d, external pullup pin %d, parasitic power %d\n", pdata->pin, pdata->ext_pullup_enable_pin, pdata->parasitic_power); ++ + err = devm_gpio_request(&pdev->dev, pdata->pin, "w1"); + if (err) { + dev_err(&pdev->dev, "gpio_request (pin) failed\n"); +@@ -165,6 +210,14 @@ + master->set_pullup = w1_gpio_set_pullup; + } + ++ if (pdata->parasitic_power) { ++ if (pdata->is_open_drain) ++ printk(KERN_ERR "w1-gpio 'pullup'(parasitic power) " ++ "option doesn't work with open drain GPIO\n"); ++ else ++ master->bitbang_pullup = w1_gpio_bitbang_pullup; ++ } ++ + err = w1_add_master_device(master); + if (err) { + dev_err(&pdev->dev, "w1_add_master device failed\n"); +@@ -195,6 +248,10 @@ + + w1_remove_master_device(master); + ++ pdata->pin = w1_gpio_pin_orig; ++ pdata->ext_pullup_enable_pin = w1_gpio_pullup_pin_orig; ++ pdata->parasitic_power = w1_gpio_pullup_orig; ++ + return 0; + } + +diff -Nur linux-4.1.13.orig/drivers/w1/slaves/w1_therm.c linux-rpi/drivers/w1/slaves/w1_therm.c +--- linux-4.1.13.orig/drivers/w1/slaves/w1_therm.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/w1/slaves/w1_therm.c 2015-11-29 09:42:40.139084077 +0100 +@@ -92,13 +92,24 @@ + static ssize_t w1_slave_show(struct device *device, + struct device_attribute *attr, char *buf); + ++static ssize_t w1_seq_show(struct device *device, ++ struct device_attribute *attr, char *buf); ++ + static DEVICE_ATTR_RO(w1_slave); ++static DEVICE_ATTR_RO(w1_seq); + + static struct attribute *w1_therm_attrs[] = { + &dev_attr_w1_slave.attr, + NULL, + }; ++ ++static struct attribute *w1_ds28ea00_attrs[] = { ++ &dev_attr_w1_slave.attr, ++ &dev_attr_w1_seq.attr, ++ NULL, ++}; + ATTRIBUTE_GROUPS(w1_therm); ++ATTRIBUTE_GROUPS(w1_ds28ea00); + + static struct w1_family_ops w1_therm_fops = { + .add_slave = w1_therm_add_slave, +@@ -106,6 +117,12 @@ + .groups = w1_therm_groups, + }; + ++static struct w1_family_ops w1_ds28ea00_fops = { ++ .add_slave = w1_therm_add_slave, ++ .remove_slave = w1_therm_remove_slave, ++ .groups = w1_ds28ea00_groups, ++}; ++ + static struct w1_family w1_therm_family_DS18S20 = { + .fid = W1_THERM_DS18S20, + .fops = &w1_therm_fops, +@@ -123,7 +140,7 @@ + + static struct w1_family w1_therm_family_DS28EA00 = { + .fid = W1_THERM_DS28EA00, +- .fops = &w1_therm_fops, ++ .fops = &w1_ds28ea00_fops, + }; + + static struct w1_family w1_therm_family_DS1825 = { +@@ -316,6 +333,89 @@ + return ret; + } + ++#define W1_42_CHAIN 0x99 ++#define W1_42_CHAIN_OFF 0x3C ++#define W1_42_CHAIN_OFF_INV 0xC3 ++#define W1_42_CHAIN_ON 0x5A ++#define W1_42_CHAIN_ON_INV 0xA5 ++#define W1_42_CHAIN_DONE 0x96 ++#define W1_42_CHAIN_DONE_INV 0x69 ++#define W1_42_COND_READ 0x0F ++#define W1_42_SUCCESS_CONFIRM_BYTE 0xAA ++#define W1_42_FINISHED_BYTE 0xFF ++static ssize_t w1_seq_show(struct device *device, ++ struct device_attribute *attr, char *buf) ++{ ++ struct w1_slave *sl = dev_to_w1_slave(device); ++ ssize_t c = PAGE_SIZE; ++ int rv; ++ int i; ++ u8 ack; ++ u64 rn; ++ struct w1_reg_num *reg_num; ++ int seq = 0; ++ ++ mutex_lock(&sl->master->bus_mutex); ++ /* Place all devices in CHAIN state */ ++ if (w1_reset_bus(sl->master)) ++ goto error; ++ w1_write_8(sl->master, W1_SKIP_ROM); ++ w1_write_8(sl->master, W1_42_CHAIN); ++ w1_write_8(sl->master, W1_42_CHAIN_ON); ++ w1_write_8(sl->master, W1_42_CHAIN_ON_INV); ++ msleep(sl->master->pullup_duration); ++ ++ /* check for acknowledgment */ ++ ack = w1_read_8(sl->master); ++ if (ack != W1_42_SUCCESS_CONFIRM_BYTE) ++ goto error; ++ ++ /* In case the bus fails to send 0xFF, limit*/ ++ for (i = 0; i <= 64; i++) { ++ if (w1_reset_bus(sl->master)) ++ goto error; ++ ++ w1_write_8(sl->master, W1_42_COND_READ); ++ rv = w1_read_block(sl->master, (u8 *)&rn, 8); ++ reg_num = (struct w1_reg_num *) &rn; ++ if (reg_num->family == W1_42_FINISHED_BYTE) ++ break; ++ if (sl->reg_num.id == reg_num->id) ++ seq = i; ++ ++ w1_write_8(sl->master, W1_42_CHAIN); ++ w1_write_8(sl->master, W1_42_CHAIN_DONE); ++ w1_write_8(sl->master, W1_42_CHAIN_DONE_INV); ++ w1_read_block(sl->master, &ack, sizeof(ack)); ++ ++ /* check for acknowledgment */ ++ ack = w1_read_8(sl->master); ++ if (ack != W1_42_SUCCESS_CONFIRM_BYTE) ++ goto error; ++ ++ } ++ ++ /* Exit from CHAIN state */ ++ if (w1_reset_bus(sl->master)) ++ goto error; ++ w1_write_8(sl->master, W1_SKIP_ROM); ++ w1_write_8(sl->master, W1_42_CHAIN); ++ w1_write_8(sl->master, W1_42_CHAIN_OFF); ++ w1_write_8(sl->master, W1_42_CHAIN_OFF_INV); ++ ++ /* check for acknowledgment */ ++ ack = w1_read_8(sl->master); ++ if (ack != W1_42_SUCCESS_CONFIRM_BYTE) ++ goto error; ++ mutex_unlock(&sl->master->bus_mutex); ++ ++ c -= snprintf(buf + PAGE_SIZE - c, c, "%d\n", seq); ++ return PAGE_SIZE - c; ++error: ++ mutex_unlock(&sl->master->bus_mutex); ++ return -EIO; ++} ++ + static int __init w1_therm_init(void) + { + int err, i; +diff -Nur linux-4.1.13.orig/drivers/w1/w1.h linux-rpi/drivers/w1/w1.h +--- linux-4.1.13.orig/drivers/w1/w1.h 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/w1/w1.h 2015-11-29 09:42:40.139084077 +0100 +@@ -171,6 +171,12 @@ + + u8 (*set_pullup)(void *, int); + ++ /** ++ * Turns the pullup on/off in bitbanging mode, takes an on/off argument. ++ * @return -1=Error, 0=completed ++ */ ++ void (*bitbang_pullup) (void *, u8); ++ + void (*search)(void *, struct w1_master *, + u8, w1_slave_found_callback); + }; +diff -Nur linux-4.1.13.orig/drivers/w1/w1_int.c linux-rpi/drivers/w1/w1_int.c +--- linux-4.1.13.orig/drivers/w1/w1_int.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/w1/w1_int.c 2015-11-29 09:42:40.139084077 +0100 +@@ -123,6 +123,20 @@ + return(-EINVAL); + } + ++ /* bitbanging hardware uses bitbang_pullup, other hardware uses set_pullup ++ * and takes care of timing itself */ ++ if (!master->write_byte && !master->touch_bit && master->set_pullup) { ++ printk(KERN_ERR "w1_add_master_device: set_pullup requires " ++ "write_byte or touch_bit, disabling\n"); ++ master->set_pullup = NULL; ++ } ++ ++ if (master->set_pullup && master->bitbang_pullup) { ++ printk(KERN_ERR "w1_add_master_device: set_pullup should not " ++ "be set when bitbang_pullup is used, disabling\n"); ++ master->set_pullup = NULL; ++ } ++ + /* Lock until the device is added (or not) to w1_masters. */ + mutex_lock(&w1_mlock); + /* Search for the first available id (starting at 1). */ +diff -Nur linux-4.1.13.orig/drivers/w1/w1_io.c linux-rpi/drivers/w1/w1_io.c +--- linux-4.1.13.orig/drivers/w1/w1_io.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/w1/w1_io.c 2015-11-29 09:42:40.139084077 +0100 +@@ -134,10 +134,22 @@ + static void w1_post_write(struct w1_master *dev) + { + if (dev->pullup_duration) { +- if (dev->enable_pullup && dev->bus_master->set_pullup) +- dev->bus_master->set_pullup(dev->bus_master->data, 0); +- else ++ if (dev->enable_pullup) { ++ if (dev->bus_master->set_pullup) { ++ dev->bus_master->set_pullup(dev-> ++ bus_master->data, ++ 0); ++ } else if (dev->bus_master->bitbang_pullup) { ++ dev->bus_master-> ++ bitbang_pullup(dev->bus_master->data, 1); + msleep(dev->pullup_duration); ++ dev->bus_master-> ++ bitbang_pullup(dev->bus_master->data, 0); ++ } ++ } else { ++ msleep(dev->pullup_duration); ++ } ++ + dev->pullup_duration = 0; + } + } +diff -Nur linux-4.1.13.orig/drivers/watchdog/bcm2708_wdog.c linux-rpi/drivers/watchdog/bcm2708_wdog.c +--- linux-4.1.13.orig/drivers/watchdog/bcm2708_wdog.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/drivers/watchdog/bcm2708_wdog.c 2015-11-29 09:42:40.139084077 +0100 +@@ -0,0 +1,382 @@ ++/* ++ * Broadcom BCM2708 watchdog driver. ++ * ++ * (c) Copyright 2010 Broadcom Europe Ltd ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version ++ * 2 of the License, or (at your option) any later version. ++ * ++ * BCM2708 watchdog driver. Loosely based on wdt driver. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define SECS_TO_WDOG_TICKS(x) ((x) << 16) ++#define WDOG_TICKS_TO_SECS(x) ((x) >> 16) ++ ++static unsigned long wdog_is_open; ++static uint32_t wdog_ticks; /* Ticks to load into wdog timer */ ++static char expect_close; ++ ++/* ++ * Module parameters ++ */ ++ ++#define WD_TIMO 10 /* Default heartbeat = 60 seconds */ ++static int heartbeat = WD_TIMO; /* Heartbeat in seconds */ ++ ++module_param(heartbeat, int, 0); ++MODULE_PARM_DESC(heartbeat, ++ "Watchdog heartbeat in seconds. (0 < heartbeat < 65536, default=" ++ __MODULE_STRING(WD_TIMO) ")"); ++ ++static int nowayout = WATCHDOG_NOWAYOUT; ++module_param(nowayout, int, 0); ++MODULE_PARM_DESC(nowayout, ++ "Watchdog cannot be stopped once started (default=" ++ __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); ++ ++static DEFINE_SPINLOCK(wdog_lock); ++ ++/** ++ * Start the watchdog driver. ++ */ ++ ++static int wdog_start(unsigned long timeout) ++{ ++ uint32_t cur; ++ unsigned long flags; ++ spin_lock_irqsave(&wdog_lock, flags); ++ ++ /* enable the watchdog */ ++ iowrite32(PM_PASSWORD | (timeout & PM_WDOG_TIME_SET), ++ __io_address(PM_WDOG)); ++ cur = ioread32(__io_address(PM_RSTC)); ++ iowrite32(PM_PASSWORD | (cur & PM_RSTC_WRCFG_CLR) | ++ PM_RSTC_WRCFG_FULL_RESET, __io_address(PM_RSTC)); ++ ++ spin_unlock_irqrestore(&wdog_lock, flags); ++ return 0; ++} ++ ++/** ++ * Stop the watchdog driver. ++ */ ++ ++static int wdog_stop(void) ++{ ++ iowrite32(PM_PASSWORD | PM_RSTC_RESET, __io_address(PM_RSTC)); ++ printk(KERN_INFO "watchdog stopped\n"); ++ return 0; ++} ++ ++/** ++ * Reload counter one with the watchdog heartbeat. We don't bother ++ * reloading the cascade counter. ++ */ ++ ++static void wdog_ping(void) ++{ ++ wdog_start(wdog_ticks); ++} ++ ++/** ++ * @t: the new heartbeat value that needs to be set. ++ * ++ * Set a new heartbeat value for the watchdog device. If the heartbeat ++ * value is incorrect we keep the old value and return -EINVAL. If ++ * successful we return 0. ++ */ ++ ++static int wdog_set_heartbeat(int t) ++{ ++ if (t < 1 || t > WDOG_TICKS_TO_SECS(PM_WDOG_TIME_SET)) ++ return -EINVAL; ++ ++ heartbeat = t; ++ wdog_ticks = SECS_TO_WDOG_TICKS(t); ++ return 0; ++} ++ ++/** ++ * @file: file handle to the watchdog ++ * @buf: buffer to write (unused as data does not matter here ++ * @count: count of bytes ++ * @ppos: pointer to the position to write. No seeks allowed ++ * ++ * A write to a watchdog device is defined as a keepalive signal. ++ * ++ * if 'nowayout' is set then normally a close() is ignored. But ++ * if you write 'V' first then the close() will stop the timer. ++ */ ++ ++static ssize_t wdog_write(struct file *file, const char __user *buf, ++ size_t count, loff_t *ppos) ++{ ++ if (count) { ++ if (!nowayout) { ++ size_t i; ++ ++ /* In case it was set long ago */ ++ expect_close = 0; ++ ++ for (i = 0; i != count; i++) { ++ char c; ++ if (get_user(c, buf + i)) ++ return -EFAULT; ++ if (c == 'V') ++ expect_close = 42; ++ } ++ } ++ wdog_ping(); ++ } ++ return count; ++} ++ ++static int wdog_get_status(void) ++{ ++ unsigned long flags; ++ int status = 0; ++ spin_lock_irqsave(&wdog_lock, flags); ++ /* FIXME: readback reset reason */ ++ spin_unlock_irqrestore(&wdog_lock, flags); ++ return status; ++} ++ ++static uint32_t wdog_get_remaining(void) ++{ ++ uint32_t ret = ioread32(__io_address(PM_WDOG)); ++ return ret & PM_WDOG_TIME_SET; ++} ++ ++/** ++ * @file: file handle to the device ++ * @cmd: watchdog command ++ * @arg: argument pointer ++ * ++ * The watchdog API defines a common set of functions for all watchdogs ++ * according to their available features. We only actually usefully support ++ * querying capabilities and current status. ++ */ ++ ++static long wdog_ioctl(struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ void __user *argp = (void __user *)arg; ++ int __user *p = argp; ++ int new_heartbeat; ++ int status; ++ int options; ++ uint32_t remaining; ++ ++ struct watchdog_info ident = { ++ .options = WDIOF_SETTIMEOUT| ++ WDIOF_MAGICCLOSE| ++ WDIOF_KEEPALIVEPING, ++ .firmware_version = 1, ++ .identity = "BCM2708", ++ }; ++ ++ switch (cmd) { ++ case WDIOC_GETSUPPORT: ++ return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; ++ case WDIOC_GETSTATUS: ++ status = wdog_get_status(); ++ return put_user(status, p); ++ case WDIOC_GETBOOTSTATUS: ++ return put_user(0, p); ++ case WDIOC_KEEPALIVE: ++ wdog_ping(); ++ return 0; ++ case WDIOC_SETTIMEOUT: ++ if (get_user(new_heartbeat, p)) ++ return -EFAULT; ++ if (wdog_set_heartbeat(new_heartbeat)) ++ return -EINVAL; ++ wdog_ping(); ++ /* Fall */ ++ case WDIOC_GETTIMEOUT: ++ return put_user(heartbeat, p); ++ case WDIOC_GETTIMELEFT: ++ remaining = WDOG_TICKS_TO_SECS(wdog_get_remaining()); ++ return put_user(remaining, p); ++ case WDIOC_SETOPTIONS: ++ if (get_user(options, p)) ++ return -EFAULT; ++ if (options & WDIOS_DISABLECARD) ++ wdog_stop(); ++ if (options & WDIOS_ENABLECARD) ++ wdog_start(wdog_ticks); ++ return 0; ++ default: ++ return -ENOTTY; ++ } ++} ++ ++/** ++ * @inode: inode of device ++ * @file: file handle to device ++ * ++ * The watchdog device has been opened. The watchdog device is single ++ * open and on opening we load the counters. ++ */ ++ ++static int wdog_open(struct inode *inode, struct file *file) ++{ ++ if (test_and_set_bit(0, &wdog_is_open)) ++ return -EBUSY; ++ /* ++ * Activate ++ */ ++ wdog_start(wdog_ticks); ++ return nonseekable_open(inode, file); ++} ++ ++/** ++ * @inode: inode to board ++ * @file: file handle to board ++ * ++ * The watchdog has a configurable API. There is a religious dispute ++ * between people who want their watchdog to be able to shut down and ++ * those who want to be sure if the watchdog manager dies the machine ++ * reboots. In the former case we disable the counters, in the latter ++ * case you have to open it again very soon. ++ */ ++ ++static int wdog_release(struct inode *inode, struct file *file) ++{ ++ if (expect_close == 42) { ++ wdog_stop(); ++ } else { ++ printk(KERN_CRIT ++ "wdt: WDT device closed unexpectedly. WDT will not stop!\n"); ++ wdog_ping(); ++ } ++ clear_bit(0, &wdog_is_open); ++ expect_close = 0; ++ return 0; ++} ++ ++/** ++ * @this: our notifier block ++ * @code: the event being reported ++ * @unused: unused ++ * ++ * Our notifier is called on system shutdowns. Turn the watchdog ++ * off so that it does not fire during the next reboot. ++ */ ++ ++static int wdog_notify_sys(struct notifier_block *this, unsigned long code, ++ void *unused) ++{ ++ if (code == SYS_DOWN || code == SYS_HALT) ++ wdog_stop(); ++ return NOTIFY_DONE; ++} ++ ++/* ++ * Kernel Interfaces ++ */ ++ ++ ++static const struct file_operations wdog_fops = { ++ .owner = THIS_MODULE, ++ .llseek = no_llseek, ++ .write = wdog_write, ++ .unlocked_ioctl = wdog_ioctl, ++ .open = wdog_open, ++ .release = wdog_release, ++}; ++ ++static struct miscdevice wdog_miscdev = { ++ .minor = WATCHDOG_MINOR, ++ .name = "watchdog", ++ .fops = &wdog_fops, ++}; ++ ++/* ++ * The WDT card needs to learn about soft shutdowns in order to ++ * turn the timebomb registers off. ++ */ ++ ++static struct notifier_block wdog_notifier = { ++ .notifier_call = wdog_notify_sys, ++}; ++ ++/** ++ * cleanup_module: ++ * ++ * Unload the watchdog. You cannot do this with any file handles open. ++ * If your watchdog is set to continue ticking on close and you unload ++ * it, well it keeps ticking. We won't get the interrupt but the board ++ * will not touch PC memory so all is fine. You just have to load a new ++ * module in 60 seconds or reboot. ++ */ ++ ++static void __exit wdog_exit(void) ++{ ++ misc_deregister(&wdog_miscdev); ++ unregister_reboot_notifier(&wdog_notifier); ++} ++ ++static int __init wdog_init(void) ++{ ++ int ret; ++ ++ /* Check that the heartbeat value is within it's range; ++ if not reset to the default */ ++ if (wdog_set_heartbeat(heartbeat)) { ++ wdog_set_heartbeat(WD_TIMO); ++ printk(KERN_INFO "bcm2708_wdog: heartbeat value must be " ++ "0 < heartbeat < %d, using %d\n", ++ WDOG_TICKS_TO_SECS(PM_WDOG_TIME_SET), ++ WD_TIMO); ++ } ++ ++ ret = register_reboot_notifier(&wdog_notifier); ++ if (ret) { ++ printk(KERN_ERR ++ "wdt: cannot register reboot notifier (err=%d)\n", ret); ++ goto out_reboot; ++ } ++ ++ ret = misc_register(&wdog_miscdev); ++ if (ret) { ++ printk(KERN_ERR ++ "wdt: cannot register miscdev on minor=%d (err=%d)\n", ++ WATCHDOG_MINOR, ret); ++ goto out_misc; ++ } ++ ++ printk(KERN_INFO "bcm2708 watchdog, heartbeat=%d sec (nowayout=%d)\n", ++ heartbeat, nowayout); ++ return 0; ++ ++out_misc: ++ unregister_reboot_notifier(&wdog_notifier); ++out_reboot: ++ return ret; ++} ++ ++module_init(wdog_init); ++module_exit(wdog_exit); ++ ++MODULE_AUTHOR("Luke Diamand"); ++MODULE_DESCRIPTION("Driver for BCM2708 watchdog"); ++MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); ++MODULE_ALIAS_MISCDEV(TEMP_MINOR); ++MODULE_LICENSE("GPL"); +diff -Nur linux-4.1.13.orig/drivers/watchdog/Kconfig linux-rpi/drivers/watchdog/Kconfig +--- linux-4.1.13.orig/drivers/watchdog/Kconfig 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/watchdog/Kconfig 2015-11-29 09:42:40.139084077 +0100 +@@ -451,6 +451,12 @@ + To compile this driver as a module, choose M here: the + module will be called retu_wdt. + ++config BCM2708_WDT ++ tristate "BCM2708 Watchdog" ++ depends on ARCH_BCM2708 || ARCH_BCM2709 ++ help ++ Enables BCM2708 watchdog support. ++ + config MOXART_WDT + tristate "MOXART watchdog" + depends on ARCH_MOXART +@@ -1216,7 +1222,7 @@ + + config BCM2835_WDT + tristate "Broadcom BCM2835 hardware watchdog" +- depends on ARCH_BCM2835 ++ depends on ARCH_BCM2835 || ARCH_BCM2708 || ARCH_BCM2709 + select WATCHDOG_CORE + help + Watchdog driver for the built in watchdog hardware in Broadcom +diff -Nur linux-4.1.13.orig/drivers/watchdog/Makefile linux-rpi/drivers/watchdog/Makefile +--- linux-4.1.13.orig/drivers/watchdog/Makefile 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/drivers/watchdog/Makefile 2015-11-29 09:42:40.139084077 +0100 +@@ -56,6 +56,7 @@ + obj-$(CONFIG_IMX2_WDT) += imx2_wdt.o + obj-$(CONFIG_UX500_WATCHDOG) += ux500_wdt.o + obj-$(CONFIG_RETU_WATCHDOG) += retu_wdt.o ++obj-$(CONFIG_BCM2708_WDT) += bcm2708_wdog.o + obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o + obj-$(CONFIG_MOXART_WDT) += moxart_wdt.o + obj-$(CONFIG_SIRFSOC_WATCHDOG) += sirfsoc_wdt.o +diff -Nur linux-4.1.13.orig/include/linux/broadcom/bcm2835_smi.h linux-rpi/include/linux/broadcom/bcm2835_smi.h +--- linux-4.1.13.orig/include/linux/broadcom/bcm2835_smi.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/include/linux/broadcom/bcm2835_smi.h 2015-11-29 09:42:40.679048199 +0100 +@@ -0,0 +1,391 @@ ++/** ++ * Declarations and definitions for Broadcom's Secondary Memory Interface ++ * ++ * Written by Luke Wren ++ * Copyright (c) 2015, Raspberry Pi (Trading) Ltd. ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") version 2, as published by the Free ++ * Software Foundation. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#ifndef BCM2835_SMI_H ++#define BCM2835_SMI_H ++ ++#include ++ ++#ifndef __KERNEL__ ++#include ++#include ++#endif ++ ++#define BCM2835_SMI_IOC_MAGIC 0x1 ++#define BCM2835_SMI_INVALID_HANDLE (~0) ++ ++/* IOCTLs 0x100...0x1ff are not device-specific - we can use them */ ++#define BCM2835_SMI_IOC_GET_SETTINGS _IO(BCM2835_SMI_IOC_MAGIC, 0) ++#define BCM2835_SMI_IOC_WRITE_SETTINGS _IO(BCM2835_SMI_IOC_MAGIC, 1) ++#define BCM2835_SMI_IOC_ADDRESS _IO(BCM2835_SMI_IOC_MAGIC, 2) ++#define BCM2835_SMI_IOC_MAX 2 ++ ++#define SMI_WIDTH_8BIT 0 ++#define SMI_WIDTH_16BIT 1 ++#define SMI_WIDTH_9BIT 2 ++#define SMI_WIDTH_18BIT 3 ++ ++/* max number of bytes where DMA will not be used */ ++#define DMA_THRESHOLD_BYTES 128 ++#define DMA_BOUNCE_BUFFER_SIZE (1024 * 1024 / 2) ++#define DMA_BOUNCE_BUFFER_COUNT 3 ++ ++ ++struct smi_settings { ++ int data_width; ++ /* Whether or not to pack multiple SMI transfers into a ++ single 32 bit FIFO word */ ++ bool pack_data; ++ ++ /* Timing for reads (writes the same but for WE) ++ * ++ * OE ----------+ +-------------------- ++ * | | ++ * +----------+ ++ * SD -<==============================>----------- ++ * SA -<=========================================>- ++ * <-setup-> <-strobe -> <-hold -> <- pace -> ++ */ ++ ++ int read_setup_time; ++ int read_hold_time; ++ int read_pace_time; ++ int read_strobe_time; ++ ++ int write_setup_time; ++ int write_hold_time; ++ int write_pace_time; ++ int write_strobe_time; ++ ++ bool dma_enable; /* DREQs */ ++ bool dma_passthrough_enable; /* External DREQs */ ++ int dma_read_thresh; ++ int dma_write_thresh; ++ int dma_panic_read_thresh; ++ int dma_panic_write_thresh; ++}; ++ ++/**************************************************************************** ++* ++* Declare exported SMI functions ++* ++***************************************************************************/ ++ ++#ifdef __KERNEL__ ++ ++#include /* for enum dma_transfer_direction */ ++#include ++#include ++ ++struct bcm2835_smi_instance; ++ ++struct bcm2835_smi_bounce_info { ++ struct semaphore callback_sem; ++ void *buffer[DMA_BOUNCE_BUFFER_COUNT]; ++ dma_addr_t phys[DMA_BOUNCE_BUFFER_COUNT]; ++ struct scatterlist sgl[DMA_BOUNCE_BUFFER_COUNT]; ++}; ++ ++ ++void bcm2835_smi_set_regs_from_settings(struct bcm2835_smi_instance *); ++ ++struct smi_settings *bcm2835_smi_get_settings_from_regs( ++ struct bcm2835_smi_instance *inst); ++ ++void bcm2835_smi_write_buf( ++ struct bcm2835_smi_instance *inst, ++ const void *buf, ++ size_t n_bytes); ++ ++void bcm2835_smi_read_buf( ++ struct bcm2835_smi_instance *inst, ++ void *buf, ++ size_t n_bytes); ++ ++void bcm2835_smi_set_address(struct bcm2835_smi_instance *inst, ++ unsigned int address); ++ ++ssize_t bcm2835_smi_user_dma( ++ struct bcm2835_smi_instance *inst, ++ enum dma_transfer_direction dma_dir, ++ char __user *user_ptr, ++ size_t count, ++ struct bcm2835_smi_bounce_info **bounce); ++ ++struct bcm2835_smi_instance *bcm2835_smi_get(struct device_node *node); ++ ++#endif /* __KERNEL__ */ ++ ++/**************************************************************** ++* ++* Implementation-only declarations ++* ++****************************************************************/ ++ ++#ifdef BCM2835_SMI_IMPLEMENTATION ++ ++/* Clock manager registers for SMI clock: */ ++#define CM_SMI_BASE_ADDRESS ((BCM2708_PERI_BASE) + 0x1010b0) ++/* Clock manager "password" to protect registers from spurious writes */ ++#define CM_PWD (0x5a << 24) ++ ++#define CM_SMI_CTL 0x00 ++#define CM_SMI_DIV 0x04 ++ ++#define CM_SMI_CTL_FLIP (1 << 8) ++#define CM_SMI_CTL_BUSY (1 << 7) ++#define CM_SMI_CTL_KILL (1 << 5) ++#define CM_SMI_CTL_ENAB (1 << 4) ++#define CM_SMI_CTL_SRC_MASK (0xf) ++#define CM_SMI_CTL_SRC_OFFS (0) ++ ++#define CM_SMI_DIV_DIVI_MASK (0xf << 12) ++#define CM_SMI_DIV_DIVI_OFFS (12) ++#define CM_SMI_DIV_DIVF_MASK (0xff << 4) ++#define CM_SMI_DIV_DIVF_OFFS (4) ++ ++/* SMI register mapping:*/ ++#define SMI_BASE_ADDRESS ((BCM2708_PERI_BASE) + 0x600000) ++ ++#define SMICS 0x00 /* control + status register */ ++#define SMIL 0x04 /* length/count (n external txfers) */ ++#define SMIA 0x08 /* address register */ ++#define SMID 0x0c /* data register */ ++#define SMIDSR0 0x10 /* device 0 read settings */ ++#define SMIDSW0 0x14 /* device 0 write settings */ ++#define SMIDSR1 0x18 /* device 1 read settings */ ++#define SMIDSW1 0x1c /* device 1 write settings */ ++#define SMIDSR2 0x20 /* device 2 read settings */ ++#define SMIDSW2 0x24 /* device 2 write settings */ ++#define SMIDSR3 0x28 /* device 3 read settings */ ++#define SMIDSW3 0x2c /* device 3 write settings */ ++#define SMIDC 0x30 /* DMA control registers */ ++#define SMIDCS 0x34 /* direct control/status register */ ++#define SMIDA 0x38 /* direct address register */ ++#define SMIDD 0x3c /* direct data registers */ ++#define SMIFD 0x40 /* FIFO debug register */ ++ ++ ++ ++/* Control and Status register bits: ++ * SMICS_RXF : RX fifo full: 1 when RX fifo is full ++ * SMICS_TXE : TX fifo empty: 1 when empty. ++ * SMICS_RXD : RX fifo contains data: 1 when there is data. ++ * SMICS_TXD : TX fifo can accept data: 1 when true. ++ * SMICS_RXR : RX fifo needs reading: 1 when fifo more than 3/4 full, or ++ * when "DONE" and fifo not emptied. ++ * SMICS_TXW : TX fifo needs writing: 1 when less than 1/4 full. ++ * SMICS_AFERR : AXI FIFO error: 1 when fifo read when empty or written ++ * when full. Write 1 to clear. ++ * SMICS_EDREQ : 1 when external DREQ received. ++ * SMICS_PXLDAT : Pixel data: write 1 to enable pixel transfer modes. ++ * SMICS_SETERR : 1 if there was an error writing to setup regs (e.g. ++ * tx was in progress). Write 1 to clear. ++ * SMICS_PVMODE : Set to 1 to enable pixel valve mode. ++ * SMICS_INTR : Set to 1 to enable interrupt on RX. ++ * SMICS_INTT : Set to 1 to enable interrupt on TX. ++ * SMICS_INTD : Set to 1 to enable interrupt on DONE condition. ++ * SMICS_TEEN : Tear effect mode enabled: Programmed transfers will wait ++ * for a TE trigger before writing. ++ * SMICS_PAD1 : Padding settings for external transfers. For writes: the ++ * number of bytes initially written to the TX fifo that ++ * SMICS_PAD0 : should be ignored. For reads: the number of bytes that will ++ * be read before the data, and should be dropped. ++ * SMICS_WRITE : Transfer direction: 1 = write to external device, 0 = read ++ * SMICS_CLEAR : Write 1 to clear the FIFOs. ++ * SMICS_START : Write 1 to start the programmed transfer. ++ * SMICS_ACTIVE : Reads as 1 when a programmed transfer is underway. ++ * SMICS_DONE : Reads as 1 when transfer finished. For RX, not set until ++ * FIFO emptied. ++ * SMICS_ENABLE : Set to 1 to enable the SMI peripheral, 0 to disable. ++ */ ++ ++#define SMICS_RXF (1 << 31) ++#define SMICS_TXE (1 << 30) ++#define SMICS_RXD (1 << 29) ++#define SMICS_TXD (1 << 28) ++#define SMICS_RXR (1 << 27) ++#define SMICS_TXW (1 << 26) ++#define SMICS_AFERR (1 << 25) ++#define SMICS_EDREQ (1 << 15) ++#define SMICS_PXLDAT (1 << 14) ++#define SMICS_SETERR (1 << 13) ++#define SMICS_PVMODE (1 << 12) ++#define SMICS_INTR (1 << 11) ++#define SMICS_INTT (1 << 10) ++#define SMICS_INTD (1 << 9) ++#define SMICS_TEEN (1 << 8) ++#define SMICS_PAD1 (1 << 7) ++#define SMICS_PAD0 (1 << 6) ++#define SMICS_WRITE (1 << 5) ++#define SMICS_CLEAR (1 << 4) ++#define SMICS_START (1 << 3) ++#define SMICS_ACTIVE (1 << 2) ++#define SMICS_DONE (1 << 1) ++#define SMICS_ENABLE (1 << 0) ++ ++/* Address register bits: */ ++ ++#define SMIA_DEVICE_MASK ((1 << 9) | (1 << 8)) ++#define SMIA_DEVICE_OFFS (8) ++#define SMIA_ADDR_MASK (0x3f) /* bits 5 -> 0 */ ++#define SMIA_ADDR_OFFS (0) ++ ++/* DMA control register bits: ++ * SMIDC_DMAEN : DMA enable: set 1: DMA requests will be issued. ++ * SMIDC_DMAP : DMA passthrough: when set to 0, top two data pins are used by ++ * SMI as usual. When set to 1, the top two pins are used for ++ * external DREQs: pin 16 read request, 17 write. ++ * SMIDC_PANIC* : Threshold at which DMA will panic during read/write. ++ * SMIDC_REQ* : Threshold at which DMA will generate a DREQ. ++ */ ++ ++#define SMIDC_DMAEN (1 << 28) ++#define SMIDC_DMAP (1 << 24) ++#define SMIDC_PANICR_MASK (0x3f << 18) ++#define SMIDC_PANICR_OFFS (18) ++#define SMIDC_PANICW_MASK (0x3f << 12) ++#define SMIDC_PANICW_OFFS (12) ++#define SMIDC_REQR_MASK (0x3f << 6) ++#define SMIDC_REQR_OFFS (6) ++#define SMIDC_REQW_MASK (0x3f) ++#define SMIDC_REQW_OFFS (0) ++ ++/* Device settings register bits: same for all 4 (or 3?) device register sets. ++ * Device read settings: ++ * SMIDSR_RWIDTH : Read transfer width. 00 = 8bit, 01 = 16bit, ++ * 10 = 18bit, 11 = 9bit. ++ * SMIDSR_RSETUP : Read setup time: number of core cycles between chip ++ * select/address and read strobe. Min 1, max 64. ++ * SMIDSR_MODE68 : 1 for System 68 mode (i.e. enable + direction pins, ++ * rather than OE + WE pin) ++ * SMIDSR_FSETUP : If set to 1, setup time only applies to first ++ * transfer after address change. ++ * SMIDSR_RHOLD : Number of core cycles between read strobe going ++ * inactive and CS/address going inactive. Min 1, max 64 ++ * SMIDSR_RPACEALL : When set to 1, this device's RPACE value will always ++ * be used for the next transaction, even if it is not ++ * to this device. ++ * SMIDSR_RPACE : Number of core cycles spent waiting between CS ++ * deassert and start of next transfer. Min 1, max 128 ++ * SMIDSR_RDREQ : 1 = use external DMA request on SD16 to pace reads ++ * from device. Must also set DMAP in SMICS. ++ * SMIDSR_RSTROBE : Number of cycles to assert the read strobe. ++ * min 1, max 128. ++ */ ++#define SMIDSR_RWIDTH_MASK ((1<<31)|(1<<30)) ++#define SMIDSR_RWIDTH_OFFS (30) ++#define SMIDSR_RSETUP_MASK (0x3f << 24) ++#define SMIDSR_RSETUP_OFFS (24) ++#define SMIDSR_MODE68 (1 << 23) ++#define SMIDSR_FSETUP (1 << 22) ++#define SMIDSR_RHOLD_MASK (0x3f << 16) ++#define SMIDSR_RHOLD_OFFS (16) ++#define SMIDSR_RPACEALL (1 << 15) ++#define SMIDSR_RPACE_MASK (0x7f << 8) ++#define SMIDSR_RPACE_OFFS (8) ++#define SMIDSR_RDREQ (1 << 7) ++#define SMIDSR_RSTROBE_MASK (0x7f) ++#define SMIDSR_RSTROBE_OFFS (0) ++ ++/* Device write settings: ++ * SMIDSW_WWIDTH : Write transfer width. 00 = 8bit, 01 = 16bit, ++ * 10= 18bit, 11 = 9bit. ++ * SMIDSW_WSETUP : Number of cycles between CS assert and write strobe. ++ * Min 1, max 64. ++ * SMIDSW_WFORMAT : Pixel format of input. 0 = 16bit RGB 565, ++ * 1 = 32bit RGBA 8888 ++ * SMIDSW_WSWAP : 1 = swap pixel data bits. (Use with SMICS_PXLDAT) ++ * SMIDSW_WHOLD : Time between WE deassert and CS deassert. 1 to 64 ++ * SMIDSW_WPACEALL : 1: this device's WPACE will be used for the next ++ * transfer, regardless of that transfer's device. ++ * SMIDSW_WPACE : Cycles between CS deassert and next CS assert. ++ * Min 1, max 128 ++ * SMIDSW_WDREQ : Use external DREQ on pin 17 to pace writes. DMAP must ++ * be set in SMICS. ++ * SMIDSW_WSTROBE : Number of cycles to assert the write strobe. ++ * Min 1, max 128 ++ */ ++#define SMIDSW_WWIDTH_MASK ((1<<31)|(1<<30)) ++#define SMIDSW_WWIDTH_OFFS (30) ++#define SMIDSW_WSETUP_MASK (0x3f << 24) ++#define SMIDSW_WSETUP_OFFS (24) ++#define SMIDSW_WFORMAT (1 << 23) ++#define SMIDSW_WSWAP (1 << 22) ++#define SMIDSW_WHOLD_MASK (0x3f << 16) ++#define SMIDSW_WHOLD_OFFS (16) ++#define SMIDSW_WPACEALL (1 << 15) ++#define SMIDSW_WPACE_MASK (0x7f << 8) ++#define SMIDSW_WPACE_OFFS (8) ++#define SMIDSW_WDREQ (1 << 7) ++#define SMIDSW_WSTROBE_MASK (0x7f) ++#define SMIDSW_WSTROBE_OFFS (0) ++ ++/* Direct transfer control + status register ++ * SMIDCS_WRITE : Direction of transfer: 1 -> write, 0 -> read ++ * SMIDCS_DONE : 1 when a transfer has finished. Write 1 to clear. ++ * SMIDCS_START : Write 1 to start a transfer, if one is not already underway. ++ * SMIDCE_ENABLE: Write 1 to enable SMI in direct mode. ++ */ ++ ++#define SMIDCS_WRITE (1 << 3) ++#define SMIDCS_DONE (1 << 2) ++#define SMIDCS_START (1 << 1) ++#define SMIDCS_ENABLE (1 << 0) ++ ++/* Direct transfer address register ++ * SMIDA_DEVICE : Indicates which of the device settings banks should be used. ++ * SMIDA_ADDR : The value to be asserted on the address pins. ++ */ ++ ++#define SMIDA_DEVICE_MASK ((1<<9)|(1<<8)) ++#define SMIDA_DEVICE_OFFS (8) ++#define SMIDA_ADDR_MASK (0x3f) ++#define SMIDA_ADDR_OFFS (0) ++ ++/* FIFO debug register ++ * SMIFD_FLVL : The high-tide mark of FIFO count during the most recent txfer ++ * SMIFD_FCNT : The current FIFO count. ++ */ ++#define SMIFD_FLVL_MASK (0x3f << 8) ++#define SMIFD_FLVL_OFFS (8) ++#define SMIFD_FCNT_MASK (0x3f) ++#define SMIFD_FCNT_OFFS (0) ++ ++#endif /* BCM2835_SMI_IMPLEMENTATION */ ++ ++#endif /* BCM2835_SMI_H */ +diff -Nur linux-4.1.13.orig/include/linux/broadcom/vc_cma.h linux-rpi/include/linux/broadcom/vc_cma.h +--- linux-4.1.13.orig/include/linux/broadcom/vc_cma.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/include/linux/broadcom/vc_cma.h 2015-11-29 09:42:40.679048199 +0100 +@@ -0,0 +1,29 @@ ++/***************************************************************************** ++* Copyright 2012 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#if !defined( VC_CMA_H ) ++#define VC_CMA_H ++ ++#include ++ ++#define VC_CMA_IOC_MAGIC 0xc5 ++ ++#define VC_CMA_IOC_RESERVE _IO(VC_CMA_IOC_MAGIC, 0) ++ ++#ifdef __KERNEL__ ++extern void __init vc_cma_early_init(void); ++extern void __init vc_cma_reserve(void); ++#endif ++ ++#endif /* VC_CMA_H */ +diff -Nur linux-4.1.13.orig/include/linux/broadcom/vc_mem.h linux-rpi/include/linux/broadcom/vc_mem.h +--- linux-4.1.13.orig/include/linux/broadcom/vc_mem.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/include/linux/broadcom/vc_mem.h 2015-11-29 09:42:40.679048199 +0100 +@@ -0,0 +1,35 @@ ++/***************************************************************************** ++* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#ifndef _VC_MEM_H ++#define _VC_MEM_H ++ ++#include ++ ++#define VC_MEM_IOC_MAGIC 'v' ++ ++#define VC_MEM_IOC_MEM_PHYS_ADDR _IOR( VC_MEM_IOC_MAGIC, 0, unsigned long ) ++#define VC_MEM_IOC_MEM_SIZE _IOR( VC_MEM_IOC_MAGIC, 1, unsigned int ) ++#define VC_MEM_IOC_MEM_BASE _IOR( VC_MEM_IOC_MAGIC, 2, unsigned int ) ++#define VC_MEM_IOC_MEM_LOAD _IOR( VC_MEM_IOC_MAGIC, 3, unsigned int ) ++ ++#if defined( __KERNEL__ ) ++#define VC_MEM_TO_ARM_ADDR_MASK 0x3FFFFFFF ++ ++extern unsigned long mm_vc_mem_phys_addr; ++extern unsigned int mm_vc_mem_size; ++extern int vc_mem_get_current_size( void ); ++#endif ++ ++#endif /* _VC_MEM_H */ +diff -Nur linux-4.1.13.orig/include/linux/leds.h linux-rpi/include/linux/leds.h +--- linux-4.1.13.orig/include/linux/leds.h 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/include/linux/leds.h 2015-11-29 09:42:40.723045276 +0100 +@@ -47,6 +47,9 @@ + #define SET_BRIGHTNESS_ASYNC (1 << 21) + #define SET_BRIGHTNESS_SYNC (1 << 22) + #define LED_DEV_CAP_FLASH (1 << 23) ++ /* Additions for Raspberry Pi PWR LED */ ++#define SET_GPIO_INPUT (1 << 30) ++#define SET_GPIO_OUTPUT (1 << 31) + + /* Set LED brightness level */ + /* Must not sleep, use a workqueue if needed */ +diff -Nur linux-4.1.13.orig/include/linux/mfd/rpisense/core.h linux-rpi/include/linux/mfd/rpisense/core.h +--- linux-4.1.13.orig/include/linux/mfd/rpisense/core.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/include/linux/mfd/rpisense/core.h 2015-11-29 09:42:40.747043681 +0100 +@@ -0,0 +1,47 @@ ++/* ++ * Raspberry Pi Sense HAT core driver ++ * http://raspberrypi.org ++ * ++ * Copyright (C) 2015 Raspberry Pi ++ * ++ * Author: Serge Schneider ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++ ++#ifndef __LINUX_MFD_RPISENSE_CORE_H_ ++#define __LINUX_MFD_RPISENSE_CORE_H_ ++ ++#include ++#include ++ ++/* ++ * Register values. ++ */ ++#define RPISENSE_FB 0x00 ++#define RPISENSE_WAI 0xF0 ++#define RPISENSE_VER 0xF1 ++#define RPISENSE_KEYS 0xF2 ++#define RPISENSE_EE_WP 0xF3 ++ ++#define RPISENSE_ID 's' ++ ++struct rpisense { ++ struct device *dev; ++ struct i2c_client *i2c_client; ++ ++ /* Client devices */ ++ struct rpisense_js joystick; ++ struct rpisense_fb framebuffer; ++}; ++ ++struct rpisense *rpisense_get_dev(void); ++s32 rpisense_reg_read(struct rpisense *rpisense, int reg); ++int rpisense_reg_write(struct rpisense *rpisense, int reg, u16 val); ++int rpisense_block_write(struct rpisense *rpisense, const char *buf, int count); ++ ++#endif +diff -Nur linux-4.1.13.orig/include/linux/mfd/rpisense/framebuffer.h linux-rpi/include/linux/mfd/rpisense/framebuffer.h +--- linux-4.1.13.orig/include/linux/mfd/rpisense/framebuffer.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/include/linux/mfd/rpisense/framebuffer.h 2015-11-29 09:42:40.747043681 +0100 +@@ -0,0 +1,32 @@ ++/* ++ * Raspberry Pi Sense HAT framebuffer driver ++ * http://raspberrypi.org ++ * ++ * Copyright (C) 2015 Raspberry Pi ++ * ++ * Author: Serge Schneider ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++ ++#ifndef __LINUX_RPISENSE_FB_H_ ++#define __LINUX_RPISENSE_FB_H_ ++ ++#define SENSEFB_FBIO_IOC_MAGIC 0xF1 ++ ++#define SENSEFB_FBIOGET_GAMMA _IO(SENSEFB_FBIO_IOC_MAGIC, 0) ++#define SENSEFB_FBIOSET_GAMMA _IO(SENSEFB_FBIO_IOC_MAGIC, 1) ++#define SENSEFB_FBIORESET_GAMMA _IO(SENSEFB_FBIO_IOC_MAGIC, 2) ++ ++struct rpisense; ++ ++struct rpisense_fb { ++ struct platform_device *pdev; ++ struct fb_info *info; ++}; ++ ++#endif +diff -Nur linux-4.1.13.orig/include/linux/mfd/rpisense/joystick.h linux-rpi/include/linux/mfd/rpisense/joystick.h +--- linux-4.1.13.orig/include/linux/mfd/rpisense/joystick.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/include/linux/mfd/rpisense/joystick.h 2015-11-29 09:42:40.747043681 +0100 +@@ -0,0 +1,35 @@ ++/* ++ * Raspberry Pi Sense HAT joystick driver ++ * http://raspberrypi.org ++ * ++ * Copyright (C) 2015 Raspberry Pi ++ * ++ * Author: Serge Schneider ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ */ ++ ++#ifndef __LINUX_RPISENSE_JOYSTICK_H_ ++#define __LINUX_RPISENSE_JOYSTICK_H_ ++ ++#include ++#include ++#include ++#include ++ ++struct rpisense; ++ ++struct rpisense_js { ++ struct platform_device *pdev; ++ struct input_dev *keys_dev; ++ struct gpio_desc *keys_desc; ++ struct work_struct keys_work_s; ++ int keys_irq; ++}; ++ ++ ++#endif +diff -Nur linux-4.1.13.orig/include/linux/mmc/host.h linux-rpi/include/linux/mmc/host.h +--- linux-4.1.13.orig/include/linux/mmc/host.h 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/include/linux/mmc/host.h 2015-11-29 09:42:40.759042884 +0100 +@@ -140,7 +140,9 @@ + * I/O. Returns the number of supported blocks for the request. + */ + int (*multi_io_quirk)(struct mmc_card *card, +- unsigned int direction, int blk_size); ++ unsigned int direction, ++ u32 blk_pos, ++ int blk_size); + }; + + struct mmc_card; +@@ -285,6 +287,7 @@ + MMC_CAP2_HS400_1_2V) + #define MMC_CAP2_HSX00_1_2V (MMC_CAP2_HS200_1_2V_SDR | MMC_CAP2_HS400_1_2V) + #define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17) ++#define MMC_CAP2_FORCE_MULTIBLOCK (1 << 31) /* Always use multiblock transfers */ + + mmc_pm_flag_t pm_caps; /* supported pm features */ + +diff -Nur linux-4.1.13.orig/include/linux/platform_data/bcm2708.h linux-rpi/include/linux/platform_data/bcm2708.h +--- linux-4.1.13.orig/include/linux/platform_data/bcm2708.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/include/linux/platform_data/bcm2708.h 2015-11-29 09:42:40.779041555 +0100 +@@ -0,0 +1,23 @@ ++/* ++ * include/linux/platform_data/bcm2708.h ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * (C) 2014 Julian Scheel ++ * ++ */ ++#ifndef __BCM2708_H_ ++#define __BCM2708_H_ ++ ++typedef enum { ++ BCM2708_PULL_OFF, ++ BCM2708_PULL_UP, ++ BCM2708_PULL_DOWN ++} bcm2708_gpio_pull_t; ++ ++extern int bcm2708_gpio_setpull(struct gpio_chip *gc, unsigned offset, ++ bcm2708_gpio_pull_t value); ++ ++#endif +diff -Nur linux-4.1.13.orig/include/linux/platform_data/dma-bcm2708.h linux-rpi/include/linux/platform_data/dma-bcm2708.h +--- linux-4.1.13.orig/include/linux/platform_data/dma-bcm2708.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/include/linux/platform_data/dma-bcm2708.h 2015-11-29 09:42:40.779041555 +0100 +@@ -0,0 +1,127 @@ ++/* ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#ifndef _PLAT_BCM2708_DMA_H ++#define _PLAT_BCM2708_DMA_H ++ ++/* DMA CS Control and Status bits */ ++#define BCM2708_DMA_ACTIVE BIT(0) ++#define BCM2708_DMA_INT BIT(2) ++#define BCM2708_DMA_ISPAUSED BIT(4) /* Pause requested or not active */ ++#define BCM2708_DMA_ISHELD BIT(5) /* Is held by DREQ flow control */ ++#define BCM2708_DMA_ERR BIT(8) ++#define BCM2708_DMA_ABORT BIT(30) /* stop current CB, go to next, WO */ ++#define BCM2708_DMA_RESET BIT(31) /* WO, self clearing */ ++ ++/* DMA control block "info" field bits */ ++#define BCM2708_DMA_INT_EN BIT(0) ++#define BCM2708_DMA_TDMODE BIT(1) ++#define BCM2708_DMA_WAIT_RESP BIT(3) ++#define BCM2708_DMA_D_INC BIT(4) ++#define BCM2708_DMA_D_WIDTH BIT(5) ++#define BCM2708_DMA_D_DREQ BIT(6) ++#define BCM2708_DMA_S_INC BIT(8) ++#define BCM2708_DMA_S_WIDTH BIT(9) ++#define BCM2708_DMA_S_DREQ BIT(10) ++ ++#define BCM2708_DMA_BURST(x) (((x) & 0xf) << 12) ++#define BCM2708_DMA_PER_MAP(x) ((x) << 16) ++#define BCM2708_DMA_WAITS(x) (((x) & 0x1f) << 21) ++ ++#define BCM2708_DMA_DREQ_EMMC 11 ++#define BCM2708_DMA_DREQ_SDHOST 13 ++ ++#define BCM2708_DMA_CS 0x00 /* Control and Status */ ++#define BCM2708_DMA_ADDR 0x04 ++/* the current control block appears in the following registers - read only */ ++#define BCM2708_DMA_INFO 0x08 ++#define BCM2708_DMA_SOURCE_AD 0x0c ++#define BCM2708_DMA_DEST_AD 0x10 ++#define BCM2708_DMA_NEXTCB 0x1C ++#define BCM2708_DMA_DEBUG 0x20 ++ ++#define BCM2708_DMA4_CS (BCM2708_DMA_CHAN(4) + BCM2708_DMA_CS) ++#define BCM2708_DMA4_ADDR (BCM2708_DMA_CHAN(4) + BCM2708_DMA_ADDR) ++ ++#define BCM2708_DMA_TDMODE_LEN(w, h) ((h) << 16 | (w)) ++ ++/* When listing features we can ask for when allocating DMA channels give ++ those with higher priority smaller ordinal numbers */ ++#define BCM_DMA_FEATURE_FAST_ORD 0 ++#define BCM_DMA_FEATURE_BULK_ORD 1 ++#define BCM_DMA_FEATURE_NORMAL_ORD 2 ++#define BCM_DMA_FEATURE_LITE_ORD 3 ++#define BCM_DMA_FEATURE_FAST BIT(BCM_DMA_FEATURE_FAST_ORD) ++#define BCM_DMA_FEATURE_BULK BIT(BCM_DMA_FEATURE_BULK_ORD) ++#define BCM_DMA_FEATURE_NORMAL BIT(BCM_DMA_FEATURE_NORMAL_ORD) ++#define BCM_DMA_FEATURE_LITE BIT(BCM_DMA_FEATURE_LITE_ORD) ++#define BCM_DMA_FEATURE_COUNT 4 ++ ++struct bcm2708_dma_cb { ++ unsigned long info; ++ unsigned long src; ++ unsigned long dst; ++ unsigned long length; ++ unsigned long stride; ++ unsigned long next; ++ unsigned long pad[2]; ++}; ++ ++struct scatterlist; ++ ++#ifdef CONFIG_DMA_BCM2708_LEGACY ++ ++int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len); ++void bcm_dma_start(void __iomem *dma_chan_base, dma_addr_t control_block); ++void bcm_dma_wait_idle(void __iomem *dma_chan_base); ++bool bcm_dma_is_busy(void __iomem *dma_chan_base); ++int bcm_dma_abort(void __iomem *dma_chan_base); ++ ++/* return channel no or -ve error */ ++int bcm_dma_chan_alloc(unsigned preferred_feature_set, ++ void __iomem **out_dma_base, int *out_dma_irq); ++int bcm_dma_chan_free(int channel); ++ ++#else /* CONFIG_DMA_BCM2708_LEGACY */ ++ ++static inline int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, ++ int sg_len) ++{ ++ return 0; ++} ++ ++static inline void bcm_dma_start(void __iomem *dma_chan_base, ++ dma_addr_t control_block) { } ++ ++static inline void bcm_dma_wait_idle(void __iomem *dma_chan_base) { } ++ ++static inline bool bcm_dma_is_busy(void __iomem *dma_chan_base) ++{ ++ return false; ++} ++ ++static inline int bcm_dma_abort(void __iomem *dma_chan_base) ++{ ++ return -EINVAL; ++} ++ ++static inline int bcm_dma_chan_alloc(unsigned preferred_feature_set, ++ void __iomem **out_dma_base, ++ int *out_dma_irq) ++{ ++ return -EINVAL; ++} ++ ++static inline int bcm_dma_chan_free(int channel) ++{ ++ return -EINVAL; ++} ++ ++#endif /* CONFIG_DMA_BCM2708_LEGACY */ ++ ++#endif /* _PLAT_BCM2708_DMA_H */ +diff -Nur linux-4.1.13.orig/include/linux/vmstat.h linux-rpi/include/linux/vmstat.h +--- linux-4.1.13.orig/include/linux/vmstat.h 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/include/linux/vmstat.h 2015-11-29 09:42:40.827038366 +0100 +@@ -241,7 +241,11 @@ + static inline void __dec_zone_state(struct zone *zone, enum zone_stat_item item) + { + atomic_long_dec(&zone->vm_stat[item]); ++ if (item == NR_FILE_DIRTY && unlikely(atomic_long_read(&zone->vm_stat[item]) < 0)) ++ atomic_long_set(&zone->vm_stat[item], 0); + atomic_long_dec(&vm_stat[item]); ++ if (item == NR_FILE_DIRTY && unlikely(atomic_long_read(&vm_stat[item]) < 0)) ++ atomic_long_set(&vm_stat[item], 0); + } + + static inline void __inc_zone_page_state(struct page *page, +diff -Nur linux-4.1.13.orig/include/linux/w1-gpio.h linux-rpi/include/linux/w1-gpio.h +--- linux-4.1.13.orig/include/linux/w1-gpio.h 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/include/linux/w1-gpio.h 2015-11-29 09:42:40.827038366 +0100 +@@ -18,6 +18,7 @@ + struct w1_gpio_platform_data { + unsigned int pin; + unsigned int is_open_drain:1; ++ unsigned int parasitic_power:1; + void (*enable_external_pullup)(int enable); + unsigned int ext_pullup_enable_pin; + unsigned int pullup_duration; +diff -Nur linux-4.1.13.orig/include/soc/bcm2835/raspberrypi-firmware.h linux-rpi/include/soc/bcm2835/raspberrypi-firmware.h +--- linux-4.1.13.orig/include/soc/bcm2835/raspberrypi-firmware.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/include/soc/bcm2835/raspberrypi-firmware.h 2015-11-29 09:42:40.871035442 +0100 +@@ -0,0 +1,124 @@ ++/* ++ * Copyright © 2015 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++struct rpi_firmware; ++ ++enum rpi_firmware_property_status { ++ RPI_FIRMWARE_STATUS_REQUEST = 0, ++ RPI_FIRMWARE_STATUS_SUCCESS = 0x80000000, ++ RPI_FIRMWARE_STATUS_ERROR = 0x80000001, ++}; ++ ++/** ++ * struct rpi_firmware_property_tag_header - Firmware property tag header ++ * @tag: One of enum_mbox_property_tag. ++ * @buf_size: The number of bytes in the value buffer following this ++ * struct. ++ * @req_resp_size: On submit, the length of the request (though it doesn't ++ * appear to be currently used by the firmware). On return, ++ * the length of the response (always 4 byte aligned), with ++ * the low bit set. ++ */ ++struct rpi_firmware_property_tag_header { ++ u32 tag; ++ u32 buf_size; ++ u32 req_resp_size; ++}; ++ ++enum rpi_firmware_property_tag { ++ RPI_FIRMWARE_PROPERTY_END = 0, ++ RPI_FIRMWARE_GET_FIRMWARE_REVISION = 0x00000001, ++ ++ RPI_FIRMWARE_SET_CURSOR_INFO = 0x00008010, ++ RPI_FIRMWARE_SET_CURSOR_STATE = 0x00008011, ++ ++ RPI_FIRMWARE_GET_BOARD_MODEL = 0x00010001, ++ RPI_FIRMWARE_GET_BOARD_REVISION = 0x00010002, ++ RPI_FIRMWARE_GET_BOARD_MAC_ADDRESS = 0x00010003, ++ RPI_FIRMWARE_GET_BOARD_SERIAL = 0x00010004, ++ RPI_FIRMWARE_GET_ARM_MEMORY = 0x00010005, ++ RPI_FIRMWARE_GET_VC_MEMORY = 0x00010006, ++ RPI_FIRMWARE_GET_CLOCKS = 0x00010007, ++ RPI_FIRMWARE_GET_POWER_STATE = 0x00020001, ++ RPI_FIRMWARE_GET_TIMING = 0x00020002, ++ RPI_FIRMWARE_SET_POWER_STATE = 0x00028001, ++ RPI_FIRMWARE_GET_CLOCK_STATE = 0x00030001, ++ RPI_FIRMWARE_GET_CLOCK_RATE = 0x00030002, ++ RPI_FIRMWARE_GET_VOLTAGE = 0x00030003, ++ RPI_FIRMWARE_GET_MAX_CLOCK_RATE = 0x00030004, ++ RPI_FIRMWARE_GET_MAX_VOLTAGE = 0x00030005, ++ RPI_FIRMWARE_GET_TEMPERATURE = 0x00030006, ++ RPI_FIRMWARE_GET_MIN_CLOCK_RATE = 0x00030007, ++ RPI_FIRMWARE_GET_MIN_VOLTAGE = 0x00030008, ++ RPI_FIRMWARE_GET_TURBO = 0x00030009, ++ RPI_FIRMWARE_GET_MAX_TEMPERATURE = 0x0003000a, ++ RPI_FIRMWARE_GET_STC = 0x0003000b, ++ RPI_FIRMWARE_ALLOCATE_MEMORY = 0x0003000c, ++ RPI_FIRMWARE_LOCK_MEMORY = 0x0003000d, ++ RPI_FIRMWARE_UNLOCK_MEMORY = 0x0003000e, ++ RPI_FIRMWARE_RELEASE_MEMORY = 0x0003000f, ++ RPI_FIRMWARE_EXECUTE_CODE = 0x00030010, ++ RPI_FIRMWARE_EXECUTE_QPU = 0x00030011, ++ RPI_FIRMWARE_SET_ENABLE_QPU = 0x00030012, ++ RPI_FIRMWARE_GET_DISPMANX_RESOURCE_MEM_HANDLE = 0x00030014, ++ RPI_FIRMWARE_GET_EDID_BLOCK = 0x00030020, ++ RPI_FIRMWARE_GET_CUSTOMER_OTP = 0x00030021, ++ RPI_FIRMWARE_SET_CLOCK_STATE = 0x00038001, ++ RPI_FIRMWARE_SET_CLOCK_RATE = 0x00038002, ++ RPI_FIRMWARE_SET_VOLTAGE = 0x00038003, ++ RPI_FIRMWARE_SET_TURBO = 0x00038009, ++ RPI_FIRMWARE_SET_CUSTOMER_OTP = 0x00038021, ++ ++ /* Dispmanx TAGS */ ++ RPI_FIRMWARE_FRAMEBUFFER_ALLOCATE = 0x00040001, ++ RPI_FIRMWARE_FRAMEBUFFER_BLANK = 0x00040002, ++ RPI_FIRMWARE_FRAMEBUFFER_GET_PHYSICAL_WIDTH_HEIGHT = 0x00040003, ++ RPI_FIRMWARE_FRAMEBUFFER_GET_VIRTUAL_WIDTH_HEIGHT = 0x00040004, ++ RPI_FIRMWARE_FRAMEBUFFER_GET_DEPTH = 0x00040005, ++ RPI_FIRMWARE_FRAMEBUFFER_GET_PIXEL_ORDER = 0x00040006, ++ RPI_FIRMWARE_FRAMEBUFFER_GET_ALPHA_MODE = 0x00040007, ++ RPI_FIRMWARE_FRAMEBUFFER_GET_PITCH = 0x00040008, ++ RPI_FIRMWARE_FRAMEBUFFER_GET_VIRTUAL_OFFSET = 0x00040009, ++ RPI_FIRMWARE_FRAMEBUFFER_GET_OVERSCAN = 0x0004000a, ++ RPI_FIRMWARE_FRAMEBUFFER_GET_PALETTE = 0x0004000b, ++ RPI_FIRMWARE_FRAMEBUFFER_GET_TOUCHBUF = 0x0004000f, ++ RPI_FIRMWARE_FRAMEBUFFER_RELEASE = 0x00048001, ++ RPI_FIRMWARE_FRAMEBUFFER_TEST_PHYSICAL_WIDTH_HEIGHT = 0x00044003, ++ RPI_FIRMWARE_FRAMEBUFFER_TEST_VIRTUAL_WIDTH_HEIGHT = 0x00044004, ++ RPI_FIRMWARE_FRAMEBUFFER_TEST_DEPTH = 0x00044005, ++ RPI_FIRMWARE_FRAMEBUFFER_TEST_PIXEL_ORDER = 0x00044006, ++ RPI_FIRMWARE_FRAMEBUFFER_TEST_ALPHA_MODE = 0x00044007, ++ RPI_FIRMWARE_FRAMEBUFFER_TEST_VIRTUAL_OFFSET = 0x00044009, ++ RPI_FIRMWARE_FRAMEBUFFER_TEST_OVERSCAN = 0x0004400a, ++ RPI_FIRMWARE_FRAMEBUFFER_TEST_PALETTE = 0x0004400b, ++ RPI_FIRMWARE_FRAMEBUFFER_TEST_VSYNC = 0x0004400e, ++ RPI_FIRMWARE_FRAMEBUFFER_SET_PHYSICAL_WIDTH_HEIGHT = 0x00048003, ++ RPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_WIDTH_HEIGHT = 0x00048004, ++ RPI_FIRMWARE_FRAMEBUFFER_SET_DEPTH = 0x00048005, ++ RPI_FIRMWARE_FRAMEBUFFER_SET_PIXEL_ORDER = 0x00048006, ++ RPI_FIRMWARE_FRAMEBUFFER_SET_ALPHA_MODE = 0x00048007, ++ RPI_FIRMWARE_FRAMEBUFFER_SET_VIRTUAL_OFFSET = 0x00048009, ++ RPI_FIRMWARE_FRAMEBUFFER_SET_OVERSCAN = 0x0004800a, ++ RPI_FIRMWARE_FRAMEBUFFER_SET_PALETTE = 0x0004800b, ++ RPI_FIRMWARE_FRAMEBUFFER_SET_VSYNC = 0x0004800e, ++ RPI_FIRMWARE_FRAMEBUFFER_SET_BACKLIGHT = 0x0004800f, ++ ++ RPI_FIRMWARE_VCHIQ_INIT = 0x00048010, ++ ++ RPI_FIRMWARE_GET_COMMAND_LINE = 0x00050001, ++ RPI_FIRMWARE_GET_DMA_CHANNELS = 0x00060001, ++}; ++ ++int rpi_firmware_property(struct rpi_firmware *fw, ++ u32 tag, void *data, size_t len); ++int rpi_firmware_property_list(struct rpi_firmware *fw, ++ void *data, size_t tag_size); ++struct rpi_firmware *rpi_firmware_get(struct device_node *firmware_node); +diff -Nur linux-4.1.13.orig/include/uapi/linux/fb.h linux-rpi/include/uapi/linux/fb.h +--- linux-4.1.13.orig/include/uapi/linux/fb.h 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/include/uapi/linux/fb.h 2015-11-29 09:42:40.943030659 +0100 +@@ -34,6 +34,11 @@ + #define FBIOPUT_MODEINFO 0x4617 + #define FBIOGET_DISPINFO 0x4618 + #define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32) ++/* ++ * HACK: use 'z' in order not to clash with any other ioctl numbers which might ++ * be concurrently added to the mainline kernel ++ */ ++#define FBIOCOPYAREA _IOW('z', 0x21, struct fb_copyarea) + + #define FB_TYPE_PACKED_PIXELS 0 /* Packed Pixels */ + #define FB_TYPE_PLANES 1 /* Non interleaved planes */ +diff -Nur linux-4.1.13.orig/kernel/cgroup.c linux-rpi/kernel/cgroup.c +--- linux-4.1.13.orig/kernel/cgroup.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/kernel/cgroup.c 2015-11-29 09:42:41.015025875 +0100 +@@ -5394,6 +5394,29 @@ + } + __setup("cgroup_disable=", cgroup_disable); + ++static int __init cgroup_enable(char *str) ++{ ++ struct cgroup_subsys *ss; ++ char *token; ++ int i; ++ ++ while ((token = strsep(&str, ",")) != NULL) { ++ if (!*token) ++ continue; ++ ++ for_each_subsys(ss, i) { ++ if (!strcmp(token, ss->name)) { ++ ss->disabled = 0; ++ printk(KERN_INFO "Enabling %s control group" ++ " subsystem\n", ss->name); ++ break; ++ } ++ } ++ } ++ return 1; ++} ++__setup("cgroup_enable=", cgroup_enable); ++ + static int __init cgroup_set_legacy_files_on_dfl(char *str) + { + printk("cgroup: using legacy files on the default hierarchy\n"); +diff -Nur linux-4.1.13.orig/mm/memcontrol.c linux-rpi/mm/memcontrol.c +--- linux-4.1.13.orig/mm/memcontrol.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/mm/memcontrol.c 2015-11-29 09:42:41.131018168 +0100 +@@ -5389,6 +5389,7 @@ + .dfl_cftypes = memory_files, + .legacy_cftypes = mem_cgroup_legacy_files, + .early_init = 0, ++ .disabled = 1, + }; + + /** +diff -Nur linux-4.1.13.orig/scripts/dtc/checks.c linux-rpi/scripts/dtc/checks.c +--- linux-4.1.13.orig/scripts/dtc/checks.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/scripts/dtc/checks.c 2015-11-29 09:42:41.403000096 +0100 +@@ -53,7 +53,7 @@ + void *data; + bool warn, error; + enum checkstatus status; +- int inprogress; ++ bool inprogress; + int num_prereqs; + struct check **prereq; + }; +@@ -113,6 +113,7 @@ + vfprintf(stderr, fmt, ap); + fprintf(stderr, "\n"); + } ++ va_end(ap); + } + + #define FAIL(c, ...) \ +@@ -141,9 +142,9 @@ + check_nodes_props(c, dt, child); + } + +-static int run_check(struct check *c, struct node *dt) ++static bool run_check(struct check *c, struct node *dt) + { +- int error = 0; ++ bool error = false; + int i; + + assert(!c->inprogress); +@@ -151,11 +152,11 @@ + if (c->status != UNCHECKED) + goto out; + +- c->inprogress = 1; ++ c->inprogress = true; + + for (i = 0; i < c->num_prereqs; i++) { + struct check *prq = c->prereq[i]; +- error |= run_check(prq, dt); ++ error = error || run_check(prq, dt); + if (prq->status != PASSED) { + c->status = PREREQ; + check_msg(c, "Failed prerequisite '%s'", +@@ -177,9 +178,9 @@ + TRACE(c, "\tCompleted, status %d", c->status); + + out: +- c->inprogress = 0; ++ c->inprogress = false; + if ((c->status != PASSED) && (c->error)) +- error = 1; ++ error = true; + return error; + } + +@@ -457,22 +458,93 @@ + struct node *node, struct property *prop) + { + struct marker *m = prop->val.markers; ++ struct fixup *f, **fp; ++ struct fixup_entry *fe, **fep; + struct node *refnode; + cell_t phandle; ++ int has_phandle_refs; ++ ++ has_phandle_refs = 0; ++ for_each_marker_of_type(m, REF_PHANDLE) { ++ has_phandle_refs = 1; ++ break; ++ } ++ ++ if (!has_phandle_refs) ++ return; + + for_each_marker_of_type(m, REF_PHANDLE) { + assert(m->offset + sizeof(cell_t) <= prop->val.len); + + refnode = get_node_by_ref(dt, m->ref); +- if (! refnode) { ++ if (!refnode && !symbol_fixup_support) { + FAIL(c, "Reference to non-existent node or label \"%s\"\n", +- m->ref); ++ m->ref); + continue; + } + +- phandle = get_node_phandle(dt, refnode); +- *((cell_t *)(prop->val.val + m->offset)) = cpu_to_fdt32(phandle); ++ if (!refnode) { ++ /* allocate fixup entry */ ++ fe = xmalloc(sizeof(*fe)); ++ ++ fe->node = node; ++ fe->prop = prop; ++ fe->offset = m->offset; ++ fe->next = NULL; ++ ++ /* search for an already existing fixup */ ++ for_each_fixup(dt, f) ++ if (strcmp(f->ref, m->ref) == 0) ++ break; ++ ++ /* no fixup found, add new */ ++ if (f == NULL) { ++ f = xmalloc(sizeof(*f)); ++ f->ref = m->ref; ++ f->entries = NULL; ++ f->next = NULL; ++ ++ /* add it to the tree */ ++ fp = &dt->fixups; ++ while (*fp) ++ fp = &(*fp)->next; ++ *fp = f; ++ } ++ ++ /* and now append fixup entry */ ++ fep = &f->entries; ++ while (*fep) ++ fep = &(*fep)->next; ++ *fep = fe; ++ ++ /* mark the entry as unresolved */ ++ phandle = 0xdeadbeef; ++ } else { ++ phandle = get_node_phandle(dt, refnode); ++ ++ /* if it's a plugin, we need to record it */ ++ if (symbol_fixup_support && dt->is_plugin) { ++ ++ /* allocate a new local fixup entry */ ++ fe = xmalloc(sizeof(*fe)); ++ ++ fe->node = node; ++ fe->prop = prop; ++ fe->offset = m->offset; ++ fe->next = NULL; ++ ++ /* append it to the local fixups */ ++ fep = &dt->local_fixups; ++ while (*fep) ++ fep = &(*fep)->next; ++ *fep = fe; ++ } ++ } ++ ++ *((cell_t *)(prop->val.val + m->offset)) = ++ cpu_to_fdt32(phandle); + } ++ + } + ERROR(phandle_references, NULL, NULL, fixup_phandle_references, NULL, + &duplicate_node_names, &explicit_phandles); +@@ -624,11 +696,11 @@ + if (!reg && !ranges) + return; + +- if ((node->parent->addr_cells == -1)) ++ if (node->parent->addr_cells == -1) + FAIL(c, "Relying on default #address-cells value for %s", + node->fullpath); + +- if ((node->parent->size_cells == -1)) ++ if (node->parent->size_cells == -1) + FAIL(c, "Relying on default #size-cells value for %s", + node->fullpath); + } +@@ -651,6 +723,45 @@ + } + TREE_WARNING(obsolete_chosen_interrupt_controller, NULL); + ++static void check_auto_label_phandles(struct check *c, struct node *dt, ++ struct node *node) ++{ ++ struct label *l; ++ struct symbol *s, **sp; ++ int has_label; ++ ++ if (!symbol_fixup_support) ++ return; ++ ++ has_label = 0; ++ for_each_label(node->labels, l) { ++ has_label = 1; ++ break; ++ } ++ ++ if (!has_label) ++ return; ++ ++ /* force allocation of a phandle for this node */ ++ (void)get_node_phandle(dt, node); ++ ++ /* add the symbol */ ++ for_each_label(node->labels, l) { ++ ++ s = xmalloc(sizeof(*s)); ++ s->label = l; ++ s->node = node; ++ s->next = NULL; ++ ++ /* add it to the symbols list */ ++ sp = &dt->symbols; ++ while (*sp) ++ sp = &((*sp)->next); ++ *sp = s; ++ } ++} ++NODE_WARNING(auto_label_phandles, NULL); ++ + static struct check *check_table[] = { + &duplicate_node_names, &duplicate_property_names, + &node_name_chars, &node_name_format, &property_name_chars, +@@ -669,6 +780,8 @@ + &avoid_default_addr_size, + &obsolete_chosen_interrupt_controller, + ++ &auto_label_phandles, ++ + &always_fail, + }; + +@@ -706,15 +819,15 @@ + c->error = c->error && !error; + } + +-void parse_checks_option(bool warn, bool error, const char *optarg) ++void parse_checks_option(bool warn, bool error, const char *arg) + { + int i; +- const char *name = optarg; ++ const char *name = arg; + bool enable = true; + +- if ((strncmp(optarg, "no-", 3) == 0) +- || (strncmp(optarg, "no_", 3) == 0)) { +- name = optarg + 3; ++ if ((strncmp(arg, "no-", 3) == 0) ++ || (strncmp(arg, "no_", 3) == 0)) { ++ name = arg + 3; + enable = false; + } + +@@ -733,7 +846,7 @@ + die("Unrecognized check name \"%s\"\n", name); + } + +-void process_checks(int force, struct boot_info *bi) ++void process_checks(bool force, struct boot_info *bi) + { + struct node *dt = bi->dt; + int i; +diff -Nur linux-4.1.13.orig/scripts/dtc/data.c linux-rpi/scripts/dtc/data.c +--- linux-4.1.13.orig/scripts/dtc/data.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/scripts/dtc/data.c 2015-11-29 09:42:41.403000096 +0100 +@@ -74,7 +74,7 @@ + struct data d; + char *q; + +- d = data_grow_for(empty_data, strlen(s)+1); ++ d = data_grow_for(empty_data, len + 1); + + q = d.val; + while (i < len) { +@@ -250,20 +250,20 @@ + return data_append_markers(d, m); + } + +-int data_is_one_string(struct data d) ++bool data_is_one_string(struct data d) + { + int i; + int len = d.len; + + if (len == 0) +- return 0; ++ return false; + + for (i = 0; i < len-1; i++) + if (d.val[i] == '\0') +- return 0; ++ return false; + + if (d.val[len-1] != '\0') +- return 0; ++ return false; + +- return 1; ++ return true; + } +diff -Nur linux-4.1.13.orig/scripts/dtc/dtc.c linux-rpi/scripts/dtc/dtc.c +--- linux-4.1.13.orig/scripts/dtc/dtc.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/scripts/dtc/dtc.c 2015-11-29 09:42:41.406999830 +0100 +@@ -29,6 +29,7 @@ + int minsize; /* Minimum blob size */ + int padsize; /* Additional padding to blob */ + int phandle_format = PHANDLE_BOTH; /* Use linux,phandle or phandle properties */ ++int symbol_fixup_support = 0; + + static void fill_fullpaths(struct node *tree, const char *prefix) + { +@@ -48,8 +49,10 @@ + } + + /* Usage related data. */ ++#define FDT_VERSION(version) _FDT_VERSION(version) ++#define _FDT_VERSION(version) #version + static const char usage_synopsis[] = "dtc [options] "; +-static const char usage_short_opts[] = "qI:O:o:V:d:R:S:p:fb:i:H:sW:E:hv"; ++static const char usage_short_opts[] = "qI:O:o:V:d:R:S:p:fb:i:H:sW:E:hv@"; + static struct option const usage_long_opts[] = { + {"quiet", no_argument, NULL, 'q'}, + {"in-format", a_argument, NULL, 'I'}, +@@ -67,6 +70,7 @@ + {"phandle", a_argument, NULL, 'H'}, + {"warning", a_argument, NULL, 'W'}, + {"error", a_argument, NULL, 'E'}, ++ {"symbols", a_argument, NULL, '@'}, + {"help", no_argument, NULL, 'h'}, + {"version", no_argument, NULL, 'v'}, + {NULL, no_argument, NULL, 0x0}, +@@ -82,9 +86,9 @@ + "\t\tdts - device tree source text\n" + "\t\tdtb - device tree blob\n" + "\t\tasm - assembler source", +- "\n\tBlob version to produce, defaults to %d (for dtb and asm output)", //, DEFAULT_FDT_VERSION); ++ "\n\tBlob version to produce, defaults to "FDT_VERSION(DEFAULT_FDT_VERSION)" (for dtb and asm output)", + "\n\tOutput dependency file", +- "\n\ttMake space for reserve map entries (for dtb and asm output)", ++ "\n\tMake space for reserve map entries (for dtb and asm output)", + "\n\tMake the blob at least long (extra space)", + "\n\tAdd padding to the blob of long (extra space)", + "\n\tSet the physical boot cpu", +@@ -97,6 +101,7 @@ + "\t\tboth - Both \"linux,phandle\" and \"phandle\" properties", + "\n\tEnable/disable warnings (prefix with \"no-\")", + "\n\tEnable/disable errors (prefix with \"no-\")", ++ "\n\tSymbols and Fixups support", + "\n\tPrint this help and exit", + "\n\tPrint version and exit", + NULL, +@@ -109,7 +114,7 @@ + const char *outform = "dts"; + const char *outname = "-"; + const char *depname = NULL; +- int force = 0, sort = 0; ++ bool force = false, sort = false; + const char *arg; + int opt; + FILE *outf = NULL; +@@ -148,7 +153,7 @@ + padsize = strtol(optarg, NULL, 0); + break; + case 'f': +- force = 1; ++ force = true; + break; + case 'q': + quiet++; +@@ -174,7 +179,7 @@ + break; + + case 's': +- sort = 1; ++ sort = true; + break; + + case 'W': +@@ -184,7 +189,9 @@ + case 'E': + parse_checks_option(false, true, optarg); + break; +- ++ case '@': ++ symbol_fixup_support = 1; ++ break; + case 'h': + usage(NULL); + default: +@@ -237,7 +244,7 @@ + if (streq(outname, "-")) { + outf = stdout; + } else { +- outf = fopen(outname, "w"); ++ outf = fopen(outname, "wb"); + if (! outf) + die("Couldn't open output file %s: %s\n", + outname, strerror(errno)); +diff -Nur linux-4.1.13.orig/scripts/dtc/dtc.h linux-rpi/scripts/dtc/dtc.h +--- linux-4.1.13.orig/scripts/dtc/dtc.h 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/scripts/dtc/dtc.h 2015-11-29 09:42:41.406999830 +0100 +@@ -38,9 +38,9 @@ + #include "util.h" + + #ifdef DEBUG +-#define debug(fmt,args...) printf(fmt, ##args) ++#define debug(...) printf(__VA_ARGS__) + #else +-#define debug(fmt,args...) ++#define debug(...) + #endif + + +@@ -54,6 +54,7 @@ + extern int minsize; /* Minimum blob size */ + extern int padsize; /* Additional padding to blob */ + extern int phandle_format; /* Use linux,phandle or phandle properties */ ++extern int symbol_fixup_support;/* enable symbols & fixup support */ + + #define PHANDLE_LEGACY 0x1 + #define PHANDLE_EPAPR 0x2 +@@ -88,7 +89,7 @@ + }; + + +-#define empty_data ((struct data){ /* all .members = 0 or NULL */ }) ++#define empty_data ((struct data){ 0 /* all .members = 0 or NULL */ }) + + #define for_each_marker(m) \ + for (; (m); (m) = (m)->next) +@@ -118,7 +119,7 @@ + + struct data data_add_marker(struct data d, enum markertype type, char *ref); + +-int data_is_one_string(struct data d); ++bool data_is_one_string(struct data d); + + /* DT constraints */ + +@@ -127,13 +128,32 @@ + + /* Live trees */ + struct label { +- int deleted; ++ bool deleted; + char *label; + struct label *next; + }; + ++struct fixup_entry { ++ int offset; ++ struct node *node; ++ struct property *prop; ++ struct fixup_entry *next; ++}; ++ ++struct fixup { ++ char *ref; ++ struct fixup_entry *entries; ++ struct fixup *next; ++}; ++ ++struct symbol { ++ struct label *label; ++ struct node *node; ++ struct symbol *next; ++}; ++ + struct property { +- int deleted; ++ bool deleted; + char *name; + struct data val; + +@@ -143,7 +163,7 @@ + }; + + struct node { +- int deleted; ++ bool deleted; + char *name; + struct property *proplist; + struct node *children; +@@ -158,6 +178,12 @@ + int addr_cells, size_cells; + + struct label *labels; ++ ++ int is_root; ++ int is_plugin; ++ struct fixup *fixups; ++ struct symbol *symbols; ++ struct fixup_entry *local_fixups; + }; + + #define for_each_label_withdel(l0, l) \ +@@ -181,6 +207,18 @@ + for_each_child_withdel(n, c) \ + if (!(c)->deleted) + ++#define for_each_fixup(n, f) \ ++ for ((f) = (n)->fixups; (f); (f) = (f)->next) ++ ++#define for_each_fixup_entry(f, fe) \ ++ for ((fe) = (f)->entries; (fe); (fe) = (fe)->next) ++ ++#define for_each_symbol(n, s) \ ++ for ((s) = (n)->symbols; (s); (s) = (s)->next) ++ ++#define for_each_local_fixup_entry(n, fe) \ ++ for ((fe) = (n)->local_fixups; (fe); (fe) = (fe)->next) ++ + void add_label(struct label **labels, char *label); + void delete_labels(struct label **labels); + +@@ -247,8 +285,8 @@ + + /* Checks */ + +-void parse_checks_option(bool warn, bool error, const char *optarg); +-void process_checks(int force, struct boot_info *bi); ++void parse_checks_option(bool warn, bool error, const char *arg); ++void process_checks(bool force, struct boot_info *bi); + + /* Flattened trees */ + +diff -Nur linux-4.1.13.orig/scripts/dtc/dtc-lexer.l linux-rpi/scripts/dtc/dtc-lexer.l +--- linux-4.1.13.orig/scripts/dtc/dtc-lexer.l 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/scripts/dtc/dtc-lexer.l 2015-11-29 09:42:41.403000096 +0100 +@@ -20,7 +20,6 @@ + + %option noyywrap nounput noinput never-interactive + +-%x INCLUDE + %x BYTESTRING + %x PROPNODENAME + %s V1 +@@ -40,6 +39,7 @@ + #include "dtc-parser.tab.h" + + YYLTYPE yylloc; ++extern bool treesource_error; + + /* CAUTION: this will stop working if we ever use yyless() or yyunput() */ + #define YY_USER_ACTION \ +@@ -61,7 +61,8 @@ + BEGIN(V1); \ + + static void push_input_file(const char *filename); +-static int pop_input_file(void); ++static bool pop_input_file(void); ++static void lexical_error(const char *fmt, ...); + %} + + %% +@@ -75,11 +76,11 @@ + char *line, *tmp, *fn; + /* skip text before line # */ + line = yytext; +- while (!isdigit(*line)) ++ while (!isdigit((unsigned char)*line)) + line++; + /* skip digits in line # */ + tmp = line; +- while (!isspace(*tmp)) ++ while (!isspace((unsigned char)*tmp)) + tmp++; + /* "NULL"-terminate line # */ + *tmp = '\0'; +@@ -112,6 +113,11 @@ + return DT_V1; + } + ++<*>"/plugin/" { ++ DPRINT("Keyword: /plugin/\n"); ++ return DT_PLUGIN; ++ } ++ + <*>"/memreserve/" { + DPRINT("Keyword: /memreserve/\n"); + BEGIN_DEFAULT(); +@@ -146,15 +152,42 @@ + } + + ([0-9]+|0[xX][0-9a-fA-F]+)(U|L|UL|LL|ULL)? { +- yylval.literal = xstrdup(yytext); +- DPRINT("Literal: '%s'\n", yylval.literal); ++ char *e; ++ DPRINT("Integer Literal: '%s'\n", yytext); ++ ++ errno = 0; ++ yylval.integer = strtoull(yytext, &e, 0); ++ ++ assert(!(*e) || !e[strspn(e, "UL")]); ++ ++ if (errno == ERANGE) ++ lexical_error("Integer literal '%s' out of range", ++ yytext); ++ else ++ /* ERANGE is the only strtoull error triggerable ++ * by strings matching the pattern */ ++ assert(errno == 0); + return DT_LITERAL; + } + + <*>{CHAR_LITERAL} { +- yytext[yyleng-1] = '\0'; +- yylval.literal = xstrdup(yytext+1); +- DPRINT("Character literal: %s\n", yylval.literal); ++ struct data d; ++ DPRINT("Character literal: %s\n", yytext); ++ ++ d = data_copy_escape_string(yytext+1, yyleng-2); ++ if (d.len == 1) { ++ lexical_error("Empty character literal"); ++ yylval.integer = 0; ++ return DT_CHAR_LITERAL; ++ } ++ ++ yylval.integer = (unsigned char)d.val[0]; ++ ++ if (d.len > 2) ++ lexical_error("Character literal has %d" ++ " characters instead of 1", ++ d.len - 1); ++ + return DT_CHAR_LITERAL; + } + +@@ -164,7 +197,7 @@ + return DT_REF; + } + +-<*>"&{/"{PATHCHAR}+\} { /* new-style path reference */ ++<*>"&{/"{PATHCHAR}*\} { /* new-style path reference */ + yytext[yyleng-1] = '\0'; + DPRINT("Ref: %s\n", yytext+2); + yylval.labelref = xstrdup(yytext+2); +@@ -238,13 +271,24 @@ + } + + +-static int pop_input_file(void) ++static bool pop_input_file(void) + { + if (srcfile_pop() == 0) +- return 0; ++ return false; + + yypop_buffer_state(); + yyin = current_srcfile->f; + +- return 1; ++ return true; ++} ++ ++static void lexical_error(const char *fmt, ...) ++{ ++ va_list ap; ++ ++ va_start(ap, fmt); ++ srcpos_verror(&yylloc, "Lexical error", fmt, ap); ++ va_end(ap); ++ ++ treesource_error = true; + } +diff -Nur linux-4.1.13.orig/scripts/dtc/dtc-lexer.lex.c_shipped linux-rpi/scripts/dtc/dtc-lexer.lex.c_shipped +--- linux-4.1.13.orig/scripts/dtc/dtc-lexer.lex.c_shipped 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/scripts/dtc/dtc-lexer.lex.c_shipped 2015-11-29 09:42:41.406999830 +0100 +@@ -372,8 +372,8 @@ + *yy_cp = '\0'; \ + (yy_c_buf_p) = yy_cp; + +-#define YY_NUM_RULES 30 +-#define YY_END_OF_BUFFER 31 ++#define YY_NUM_RULES 31 ++#define YY_END_OF_BUFFER 32 + /* This struct is not used in this scanner, + but its presence is necessary. */ + struct yy_trans_info +@@ -381,25 +381,26 @@ + flex_int32_t yy_verify; + flex_int32_t yy_nxt; + }; +-static yyconst flex_int16_t yy_accept[161] = ++static yyconst flex_int16_t yy_accept[166] = + { 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 32, 30, ++ 19, 19, 30, 30, 30, 30, 30, 30, 30, 30, ++ 30, 30, 30, 30, 30, 30, 16, 17, 17, 30, ++ 17, 11, 11, 19, 27, 0, 3, 0, 28, 13, ++ 0, 0, 12, 0, 0, 0, 0, 0, 0, 0, ++ 0, 22, 24, 26, 25, 23, 0, 10, 29, 0, ++ 0, 0, 15, 15, 17, 17, 17, 11, 11, 11, ++ 0, 13, 0, 12, 0, 0, 0, 21, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 17, 11, 11, ++ 11, 0, 14, 20, 0, 0, 0, 0, 0, 0, ++ ++ 0, 0, 0, 0, 17, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 17, 7, 0, 0, 0, ++ 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 4, 18, 0, 0, 5, 2, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +- 31, 29, 18, 18, 29, 29, 29, 29, 29, 29, +- 29, 29, 29, 29, 29, 29, 29, 29, 15, 16, +- 16, 29, 16, 10, 10, 18, 26, 0, 3, 0, +- 27, 12, 0, 0, 11, 0, 0, 0, 0, 0, +- 0, 0, 21, 23, 25, 24, 22, 0, 9, 28, +- 0, 0, 0, 14, 14, 16, 16, 16, 10, 10, +- 10, 0, 12, 0, 11, 0, 0, 0, 20, 0, +- 0, 0, 0, 0, 0, 0, 0, 16, 10, 10, +- 10, 0, 19, 0, 0, 0, 0, 0, 0, 0, +- +- 0, 0, 16, 13, 0, 0, 0, 0, 0, 0, +- 0, 0, 0, 16, 6, 0, 0, 0, 0, 0, +- 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, +- 4, 17, 0, 0, 2, 0, 0, 0, 0, 0, +- 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, +- 0, 0, 5, 8, 0, 0, 0, 0, 7, 0 ++ 0, 0, 1, 0, 0, 0, 0, 6, 9, 0, ++ 0, 0, 0, 8, 0 + } ; + + static yyconst flex_int32_t yy_ec[256] = +@@ -415,9 +416,9 @@ + 22, 22, 22, 22, 24, 22, 22, 25, 22, 22, + 1, 26, 27, 1, 22, 1, 21, 28, 29, 30, + +- 31, 21, 22, 22, 32, 22, 22, 33, 34, 35, +- 36, 37, 22, 38, 39, 40, 41, 42, 22, 25, +- 43, 22, 44, 45, 46, 1, 1, 1, 1, 1, ++ 31, 21, 32, 22, 33, 22, 22, 34, 35, 36, ++ 37, 38, 22, 39, 40, 41, 42, 43, 22, 25, ++ 44, 22, 45, 46, 47, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, +@@ -434,163 +435,165 @@ + 1, 1, 1, 1, 1 + } ; + +-static yyconst flex_int32_t yy_meta[47] = ++static yyconst flex_int32_t yy_meta[48] = + { 0, + 1, 1, 1, 1, 1, 1, 2, 3, 1, 2, + 2, 2, 4, 5, 5, 5, 6, 1, 1, 1, + 7, 8, 8, 8, 8, 1, 1, 7, 7, 7, + 7, 8, 8, 8, 8, 8, 8, 8, 8, 8, +- 8, 8, 8, 3, 1, 1 ++ 8, 8, 8, 8, 3, 1, 4 + } ; + +-static yyconst flex_int16_t yy_base[175] = ++static yyconst flex_int16_t yy_base[180] = + { 0, +- 0, 385, 378, 40, 41, 383, 72, 382, 34, 44, +- 388, 393, 61, 117, 368, 116, 115, 115, 115, 48, +- 367, 107, 368, 339, 127, 120, 0, 147, 393, 0, +- 127, 0, 133, 156, 168, 153, 393, 125, 393, 380, +- 393, 0, 369, 127, 393, 160, 371, 377, 347, 21, +- 343, 346, 393, 393, 393, 393, 393, 359, 393, 393, +- 183, 343, 339, 393, 356, 0, 183, 340, 187, 348, +- 347, 0, 0, 0, 178, 359, 195, 365, 354, 326, +- 332, 325, 334, 328, 204, 326, 331, 324, 393, 335, +- 150, 311, 343, 342, 315, 322, 340, 179, 313, 207, +- +- 319, 316, 317, 393, 337, 333, 305, 302, 311, 301, +- 310, 190, 338, 337, 393, 307, 322, 301, 305, 277, +- 208, 311, 307, 278, 271, 270, 248, 246, 213, 130, +- 393, 393, 263, 235, 207, 221, 218, 229, 213, 213, +- 206, 234, 218, 210, 208, 193, 219, 393, 223, 204, +- 176, 157, 393, 393, 120, 106, 97, 119, 393, 393, +- 245, 251, 259, 263, 267, 273, 280, 284, 292, 300, +- 304, 310, 318, 326 ++ 0, 393, 35, 392, 66, 391, 38, 107, 397, 401, ++ 55, 113, 377, 112, 111, 111, 114, 42, 376, 106, ++ 377, 347, 126, 120, 0, 147, 401, 0, 124, 0, ++ 137, 158, 170, 163, 401, 153, 401, 389, 401, 0, ++ 378, 120, 401, 131, 380, 386, 355, 139, 351, 355, ++ 351, 401, 401, 401, 401, 401, 367, 401, 401, 185, ++ 350, 346, 401, 364, 0, 185, 347, 189, 356, 355, ++ 0, 0, 330, 180, 366, 141, 372, 361, 332, 338, ++ 331, 341, 334, 326, 205, 331, 337, 329, 401, 341, ++ 167, 316, 401, 349, 348, 320, 328, 346, 180, 318, ++ ++ 324, 209, 324, 320, 322, 342, 338, 309, 306, 315, ++ 305, 315, 312, 192, 342, 341, 401, 293, 306, 282, ++ 268, 252, 255, 203, 285, 282, 272, 268, 252, 233, ++ 232, 239, 208, 107, 401, 401, 238, 211, 401, 211, ++ 212, 208, 228, 203, 215, 207, 233, 222, 212, 211, ++ 203, 227, 401, 237, 225, 204, 185, 401, 401, 149, ++ 128, 88, 42, 401, 401, 253, 259, 267, 271, 275, ++ 281, 288, 292, 300, 308, 312, 318, 326, 334 + } ; + +-static yyconst flex_int16_t yy_def[175] = ++static yyconst flex_int16_t yy_def[180] = + { 0, +- 160, 1, 1, 1, 1, 5, 160, 7, 1, 1, +- 160, 160, 160, 160, 160, 161, 162, 163, 160, 160, +- 160, 160, 164, 160, 160, 160, 165, 164, 160, 166, +- 167, 166, 166, 160, 160, 160, 160, 161, 160, 161, +- 160, 168, 160, 163, 160, 163, 169, 170, 160, 160, +- 160, 160, 160, 160, 160, 160, 160, 164, 160, 160, +- 160, 160, 160, 160, 164, 166, 167, 166, 160, 160, +- 160, 171, 168, 172, 163, 169, 169, 170, 160, 160, +- 160, 160, 160, 160, 160, 160, 160, 166, 160, 160, +- 171, 172, 160, 160, 160, 160, 160, 160, 160, 160, +- +- 160, 160, 166, 160, 160, 160, 160, 160, 160, 160, +- 160, 173, 160, 166, 160, 160, 160, 160, 160, 160, +- 173, 160, 173, 160, 160, 160, 160, 160, 160, 160, +- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, +- 160, 160, 174, 160, 160, 160, 174, 160, 174, 160, +- 160, 160, 160, 160, 160, 160, 160, 160, 160, 0, +- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, +- 160, 160, 160, 160 ++ 165, 1, 1, 3, 165, 5, 1, 1, 165, 165, ++ 165, 165, 165, 166, 167, 168, 165, 165, 165, 165, ++ 169, 165, 165, 165, 170, 169, 165, 171, 172, 171, ++ 171, 165, 165, 165, 165, 166, 165, 166, 165, 173, ++ 165, 168, 165, 168, 174, 175, 165, 165, 165, 165, ++ 165, 165, 165, 165, 165, 165, 169, 165, 165, 165, ++ 165, 165, 165, 169, 171, 172, 171, 165, 165, 165, ++ 176, 173, 177, 168, 174, 174, 175, 165, 165, 165, ++ 165, 165, 165, 165, 165, 165, 165, 171, 165, 165, ++ 176, 177, 165, 165, 165, 165, 165, 165, 165, 165, ++ ++ 165, 165, 165, 165, 171, 165, 165, 165, 165, 165, ++ 165, 165, 165, 178, 165, 171, 165, 165, 165, 165, ++ 165, 165, 165, 178, 165, 178, 165, 165, 165, 165, ++ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165, ++ 165, 165, 165, 165, 165, 165, 165, 179, 165, 165, ++ 165, 179, 165, 179, 165, 165, 165, 165, 165, 165, ++ 165, 165, 165, 165, 0, 165, 165, 165, 165, 165, ++ 165, 165, 165, 165, 165, 165, 165, 165, 165 + } ; + +-static yyconst flex_int16_t yy_nxt[440] = ++static yyconst flex_int16_t yy_nxt[449] = + { 0, +- 12, 13, 14, 13, 15, 16, 12, 17, 18, 12, +- 12, 12, 19, 12, 12, 12, 12, 20, 21, 22, +- 23, 23, 23, 23, 23, 12, 12, 23, 23, 23, +- 23, 23, 23, 23, 23, 23, 23, 23, 23, 23, +- 23, 23, 23, 12, 24, 12, 25, 34, 35, 35, +- 25, 81, 26, 26, 27, 27, 27, 34, 35, 35, +- 82, 28, 36, 36, 36, 53, 54, 29, 28, 28, +- 28, 28, 12, 13, 14, 13, 15, 16, 30, 17, +- 18, 30, 30, 30, 26, 30, 30, 30, 12, 20, +- 21, 22, 31, 31, 31, 31, 31, 32, 12, 31, +- +- 31, 31, 31, 31, 31, 31, 31, 31, 31, 31, +- 31, 31, 31, 31, 31, 12, 24, 12, 36, 36, +- 36, 39, 41, 45, 47, 56, 57, 48, 61, 47, +- 39, 159, 48, 66, 61, 45, 66, 66, 66, 158, +- 46, 40, 49, 59, 50, 157, 51, 49, 52, 50, +- 40, 63, 46, 52, 36, 36, 36, 156, 43, 62, +- 65, 65, 65, 59, 136, 68, 137, 65, 75, 69, +- 69, 69, 70, 71, 65, 65, 65, 65, 70, 71, +- 72, 69, 69, 69, 61, 46, 45, 155, 154, 66, +- 70, 71, 66, 66, 66, 122, 85, 85, 85, 59, +- +- 69, 69, 69, 46, 77, 100, 109, 93, 100, 70, +- 71, 110, 112, 122, 129, 123, 153, 85, 85, 85, +- 135, 135, 135, 148, 148, 160, 135, 135, 135, 152, +- 142, 142, 142, 123, 143, 142, 142, 142, 151, 143, +- 150, 146, 145, 149, 149, 38, 38, 38, 38, 38, +- 38, 38, 38, 42, 144, 141, 140, 42, 42, 44, +- 44, 44, 44, 44, 44, 44, 44, 58, 58, 58, +- 58, 64, 139, 64, 66, 138, 134, 66, 133, 66, +- 66, 67, 132, 131, 67, 67, 67, 67, 73, 130, +- 73, 73, 76, 76, 76, 76, 76, 76, 76, 76, +- +- 78, 78, 78, 78, 78, 78, 78, 78, 91, 160, +- 91, 92, 129, 92, 92, 128, 92, 92, 121, 121, +- 121, 121, 121, 121, 121, 121, 147, 147, 147, 147, +- 147, 147, 147, 147, 127, 126, 125, 124, 61, 61, +- 120, 119, 118, 117, 116, 115, 47, 114, 110, 113, +- 111, 108, 107, 106, 48, 105, 104, 89, 103, 102, +- 101, 99, 98, 97, 96, 95, 94, 79, 77, 90, +- 89, 88, 59, 87, 86, 59, 84, 83, 80, 79, +- 77, 74, 160, 60, 59, 55, 37, 160, 33, 25, +- 26, 25, 11, 160, 160, 160, 160, 160, 160, 160, +- +- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, +- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, +- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, +- 160, 160, 160, 160, 160, 160, 160, 160, 160 ++ 10, 11, 12, 11, 13, 14, 10, 15, 16, 10, ++ 10, 10, 17, 10, 10, 10, 10, 18, 19, 20, ++ 21, 21, 21, 21, 21, 10, 10, 21, 21, 21, ++ 21, 21, 21, 21, 21, 21, 21, 21, 21, 21, ++ 21, 21, 21, 21, 10, 22, 10, 24, 25, 25, ++ 25, 32, 33, 33, 164, 26, 34, 34, 34, 52, ++ 53, 27, 26, 26, 26, 26, 10, 11, 12, 11, ++ 13, 14, 28, 15, 16, 28, 28, 28, 24, 28, ++ 28, 28, 10, 18, 19, 20, 29, 29, 29, 29, ++ 29, 30, 10, 29, 29, 29, 29, 29, 29, 29, ++ ++ 29, 29, 29, 29, 29, 29, 29, 29, 29, 29, ++ 10, 22, 10, 23, 34, 34, 34, 37, 39, 43, ++ 32, 33, 33, 45, 55, 56, 46, 60, 43, 45, ++ 65, 163, 46, 65, 65, 65, 44, 38, 60, 74, ++ 58, 47, 141, 48, 142, 44, 49, 47, 50, 48, ++ 76, 51, 62, 94, 50, 41, 44, 51, 37, 61, ++ 64, 64, 64, 58, 34, 34, 34, 64, 162, 80, ++ 67, 68, 68, 68, 64, 64, 64, 64, 38, 81, ++ 69, 70, 71, 68, 68, 68, 60, 161, 43, 69, ++ 70, 65, 69, 70, 65, 65, 65, 125, 85, 85, ++ ++ 85, 58, 68, 68, 68, 44, 102, 110, 125, 133, ++ 102, 69, 70, 111, 114, 160, 159, 126, 85, 85, ++ 85, 140, 140, 140, 140, 140, 140, 153, 126, 147, ++ 147, 147, 153, 148, 147, 147, 147, 158, 148, 165, ++ 157, 156, 155, 151, 150, 149, 146, 154, 145, 144, ++ 143, 139, 154, 36, 36, 36, 36, 36, 36, 36, ++ 36, 40, 138, 137, 136, 40, 40, 42, 42, 42, ++ 42, 42, 42, 42, 42, 57, 57, 57, 57, 63, ++ 135, 63, 65, 134, 165, 65, 133, 65, 65, 66, ++ 132, 131, 66, 66, 66, 66, 72, 130, 72, 72, ++ ++ 75, 75, 75, 75, 75, 75, 75, 75, 77, 77, ++ 77, 77, 77, 77, 77, 77, 91, 129, 91, 92, ++ 128, 92, 92, 127, 92, 92, 124, 124, 124, 124, ++ 124, 124, 124, 124, 152, 152, 152, 152, 152, 152, ++ 152, 152, 60, 60, 123, 122, 121, 120, 119, 118, ++ 117, 45, 116, 111, 115, 113, 112, 109, 108, 107, ++ 46, 106, 93, 89, 105, 104, 103, 101, 100, 99, ++ 98, 97, 96, 95, 78, 76, 93, 90, 89, 88, ++ 58, 87, 86, 58, 84, 83, 82, 79, 78, 76, ++ 73, 165, 59, 58, 54, 35, 165, 31, 23, 23, ++ ++ 9, 165, 165, 165, 165, 165, 165, 165, 165, 165, ++ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165, ++ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165, ++ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165, ++ 165, 165, 165, 165, 165, 165, 165, 165 + } ; + +-static yyconst flex_int16_t yy_chk[440] = ++static yyconst flex_int16_t yy_chk[449] = + { 0, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, +- 1, 1, 1, 1, 1, 1, 4, 9, 9, 9, +- 10, 50, 4, 5, 5, 5, 5, 10, 10, 10, +- 50, 5, 13, 13, 13, 20, 20, 5, 5, 5, +- 5, 5, 7, 7, 7, 7, 7, 7, 7, 7, +- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, +- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, +- +- 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, +- 7, 7, 7, 7, 7, 7, 7, 7, 14, 14, +- 14, 16, 17, 18, 19, 22, 22, 19, 25, 26, +- 38, 158, 26, 31, 33, 44, 31, 31, 31, 157, +- 18, 16, 19, 31, 19, 156, 19, 26, 19, 26, +- 38, 26, 44, 26, 36, 36, 36, 155, 17, 25, +- 28, 28, 28, 28, 130, 33, 130, 28, 46, 34, +- 34, 34, 91, 91, 28, 28, 28, 28, 34, 34, +- 34, 35, 35, 35, 61, 46, 75, 152, 151, 67, +- 35, 35, 67, 67, 67, 112, 61, 61, 61, 67, +- +- 69, 69, 69, 75, 77, 85, 98, 77, 100, 69, +- 69, 98, 100, 121, 129, 112, 150, 85, 85, 85, +- 135, 135, 135, 143, 147, 149, 129, 129, 129, 146, +- 138, 138, 138, 121, 138, 142, 142, 142, 145, 142, +- 144, 141, 140, 143, 147, 161, 161, 161, 161, 161, +- 161, 161, 161, 162, 139, 137, 136, 162, 162, 163, +- 163, 163, 163, 163, 163, 163, 163, 164, 164, 164, +- 164, 165, 134, 165, 166, 133, 128, 166, 127, 166, +- 166, 167, 126, 125, 167, 167, 167, 167, 168, 124, +- 168, 168, 169, 169, 169, 169, 169, 169, 169, 169, +- +- 170, 170, 170, 170, 170, 170, 170, 170, 171, 123, +- 171, 172, 122, 172, 172, 120, 172, 172, 173, 173, +- 173, 173, 173, 173, 173, 173, 174, 174, 174, 174, +- 174, 174, 174, 174, 119, 118, 117, 116, 114, 113, +- 111, 110, 109, 108, 107, 106, 105, 103, 102, 101, +- 99, 97, 96, 95, 94, 93, 92, 90, 88, 87, +- 86, 84, 83, 82, 81, 80, 79, 78, 76, 71, +- 70, 68, 65, 63, 62, 58, 52, 51, 49, 48, +- 47, 43, 40, 24, 23, 21, 15, 11, 8, 6, +- 3, 2, 160, 160, 160, 160, 160, 160, 160, 160, +- +- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, +- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, +- 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, +- 160, 160, 160, 160, 160, 160, 160, 160, 160 ++ 1, 1, 1, 1, 1, 1, 1, 3, 3, 3, ++ 3, 7, 7, 7, 163, 3, 11, 11, 11, 18, ++ 18, 3, 3, 3, 3, 3, 5, 5, 5, 5, ++ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, ++ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, ++ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, ++ ++ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, ++ 5, 5, 5, 8, 12, 12, 12, 14, 15, 16, ++ 8, 8, 8, 17, 20, 20, 17, 23, 42, 24, ++ 29, 162, 24, 29, 29, 29, 16, 14, 31, 44, ++ 29, 17, 134, 17, 134, 42, 17, 24, 17, 24, ++ 76, 17, 24, 76, 24, 15, 44, 24, 36, 23, ++ 26, 26, 26, 26, 34, 34, 34, 26, 161, 48, ++ 31, 32, 32, 32, 26, 26, 26, 26, 36, 48, ++ 32, 32, 32, 33, 33, 33, 60, 160, 74, 91, ++ 91, 66, 33, 33, 66, 66, 66, 114, 60, 60, ++ ++ 60, 66, 68, 68, 68, 74, 85, 99, 124, 133, ++ 102, 68, 68, 99, 102, 157, 156, 114, 85, 85, ++ 85, 133, 133, 133, 140, 140, 140, 148, 124, 143, ++ 143, 143, 152, 143, 147, 147, 147, 155, 147, 154, ++ 151, 150, 149, 146, 145, 144, 142, 148, 141, 138, ++ 137, 132, 152, 166, 166, 166, 166, 166, 166, 166, ++ 166, 167, 131, 130, 129, 167, 167, 168, 168, 168, ++ 168, 168, 168, 168, 168, 169, 169, 169, 169, 170, ++ 128, 170, 171, 127, 126, 171, 125, 171, 171, 172, ++ 123, 122, 172, 172, 172, 172, 173, 121, 173, 173, ++ ++ 174, 174, 174, 174, 174, 174, 174, 174, 175, 175, ++ 175, 175, 175, 175, 175, 175, 176, 120, 176, 177, ++ 119, 177, 177, 118, 177, 177, 178, 178, 178, 178, ++ 178, 178, 178, 178, 179, 179, 179, 179, 179, 179, ++ 179, 179, 116, 115, 113, 112, 111, 110, 109, 108, ++ 107, 106, 105, 104, 103, 101, 100, 98, 97, 96, ++ 95, 94, 92, 90, 88, 87, 86, 84, 83, 82, ++ 81, 80, 79, 78, 77, 75, 73, 70, 69, 67, ++ 64, 62, 61, 57, 51, 50, 49, 47, 46, 45, ++ 41, 38, 22, 21, 19, 13, 9, 6, 4, 2, ++ ++ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165, ++ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165, ++ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165, ++ 165, 165, 165, 165, 165, 165, 165, 165, 165, 165, ++ 165, 165, 165, 165, 165, 165, 165, 165 + } ; + + static yy_state_type yy_last_accepting_state; +@@ -631,13 +634,13 @@ + + + +- +-#line 38 "dtc-lexer.l" ++#line 37 "dtc-lexer.l" + #include "dtc.h" + #include "srcpos.h" + #include "dtc-parser.tab.h" + + YYLTYPE yylloc; ++extern bool treesource_error; + + /* CAUTION: this will stop working if we ever use yyless() or yyunput() */ + #define YY_USER_ACTION \ +@@ -659,14 +662,14 @@ + BEGIN(V1); \ + + static void push_input_file(const char *filename); +-static int pop_input_file(void); +-#line 664 "dtc-lexer.lex.c" ++static bool pop_input_file(void); ++static void lexical_error(const char *fmt, ...); ++#line 668 "dtc-lexer.lex.c" + + #define INITIAL 0 +-#define INCLUDE 1 +-#define BYTESTRING 2 +-#define PROPNODENAME 3 +-#define V1 4 ++#define BYTESTRING 1 ++#define PROPNODENAME 2 ++#define V1 3 + + #ifndef YY_NO_UNISTD_H + /* Special case for "unistd.h", since it is non-ANSI. We include it way +@@ -852,9 +855,9 @@ + register char *yy_cp, *yy_bp; + register int yy_act; + +-#line 67 "dtc-lexer.l" ++#line 68 "dtc-lexer.l" + +-#line 858 "dtc-lexer.lex.c" ++#line 861 "dtc-lexer.lex.c" + + if ( !(yy_init) ) + { +@@ -908,13 +911,13 @@ + while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) + { + yy_current_state = (int) yy_def[yy_current_state]; +- if ( yy_current_state >= 161 ) ++ if ( yy_current_state >= 166 ) + yy_c = yy_meta[(unsigned int) yy_c]; + } + yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c]; + ++yy_cp; + } +- while ( yy_current_state != 160 ); ++ while ( yy_current_state != 165 ); + yy_cp = (yy_last_accepting_cpos); + yy_current_state = (yy_last_accepting_state); + +@@ -937,7 +940,7 @@ + case 1: + /* rule 1 can match eol */ + YY_RULE_SETUP +-#line 68 "dtc-lexer.l" ++#line 69 "dtc-lexer.l" + { + char *name = strchr(yytext, '\"') + 1; + yytext[yyleng-1] = '\0'; +@@ -947,16 +950,16 @@ + case 2: + /* rule 2 can match eol */ + YY_RULE_SETUP +-#line 74 "dtc-lexer.l" ++#line 75 "dtc-lexer.l" + { + char *line, *tmp, *fn; + /* skip text before line # */ + line = yytext; +- while (!isdigit(*line)) ++ while (!isdigit((unsigned char)*line)) + line++; + /* skip digits in line # */ + tmp = line; +- while (!isspace(*tmp)) ++ while (!isspace((unsigned char)*tmp)) + tmp++; + /* "NULL"-terminate line # */ + *tmp = '\0'; +@@ -970,11 +973,10 @@ + } + YY_BREAK + case YY_STATE_EOF(INITIAL): +-case YY_STATE_EOF(INCLUDE): + case YY_STATE_EOF(BYTESTRING): + case YY_STATE_EOF(PROPNODENAME): + case YY_STATE_EOF(V1): +-#line 95 "dtc-lexer.l" ++#line 96 "dtc-lexer.l" + { + if (!pop_input_file()) { + yyterminate(); +@@ -984,7 +986,7 @@ + case 3: + /* rule 3 can match eol */ + YY_RULE_SETUP +-#line 101 "dtc-lexer.l" ++#line 102 "dtc-lexer.l" + { + DPRINT("String: %s\n", yytext); + yylval.data = data_copy_escape_string(yytext+1, +@@ -994,7 +996,7 @@ + YY_BREAK + case 4: + YY_RULE_SETUP +-#line 108 "dtc-lexer.l" ++#line 109 "dtc-lexer.l" + { + DPRINT("Keyword: /dts-v1/\n"); + dts_version = 1; +@@ -1004,25 +1006,33 @@ + YY_BREAK + case 5: + YY_RULE_SETUP +-#line 115 "dtc-lexer.l" ++#line 116 "dtc-lexer.l" ++{ ++ DPRINT("Keyword: /plugin/\n"); ++ return DT_PLUGIN; ++ } ++ YY_BREAK ++case 6: ++YY_RULE_SETUP ++#line 121 "dtc-lexer.l" + { + DPRINT("Keyword: /memreserve/\n"); + BEGIN_DEFAULT(); + return DT_MEMRESERVE; + } + YY_BREAK +-case 6: ++case 7: + YY_RULE_SETUP +-#line 121 "dtc-lexer.l" ++#line 127 "dtc-lexer.l" + { + DPRINT("Keyword: /bits/\n"); + BEGIN_DEFAULT(); + return DT_BITS; + } + YY_BREAK +-case 7: ++case 8: + YY_RULE_SETUP +-#line 127 "dtc-lexer.l" ++#line 133 "dtc-lexer.l" + { + DPRINT("Keyword: /delete-property/\n"); + DPRINT("\n"); +@@ -1030,9 +1040,9 @@ + return DT_DEL_PROP; + } + YY_BREAK +-case 8: ++case 9: + YY_RULE_SETUP +-#line 134 "dtc-lexer.l" ++#line 140 "dtc-lexer.l" + { + DPRINT("Keyword: /delete-node/\n"); + DPRINT("\n"); +@@ -1040,9 +1050,9 @@ + return DT_DEL_NODE; + } + YY_BREAK +-case 9: ++case 10: + YY_RULE_SETUP +-#line 141 "dtc-lexer.l" ++#line 147 "dtc-lexer.l" + { + DPRINT("Label: %s\n", yytext); + yylval.labelref = xstrdup(yytext); +@@ -1050,38 +1060,65 @@ + return DT_LABEL; + } + YY_BREAK +-case 10: ++case 11: + YY_RULE_SETUP +-#line 148 "dtc-lexer.l" ++#line 154 "dtc-lexer.l" + { +- yylval.literal = xstrdup(yytext); +- DPRINT("Literal: '%s'\n", yylval.literal); ++ char *e; ++ DPRINT("Integer Literal: '%s'\n", yytext); ++ ++ errno = 0; ++ yylval.integer = strtoull(yytext, &e, 0); ++ ++ assert(!(*e) || !e[strspn(e, "UL")]); ++ ++ if (errno == ERANGE) ++ lexical_error("Integer literal '%s' out of range", ++ yytext); ++ else ++ /* ERANGE is the only strtoull error triggerable ++ * by strings matching the pattern */ ++ assert(errno == 0); + return DT_LITERAL; + } + YY_BREAK +-case 11: +-/* rule 11 can match eol */ ++case 12: ++/* rule 12 can match eol */ + YY_RULE_SETUP +-#line 154 "dtc-lexer.l" ++#line 173 "dtc-lexer.l" + { +- yytext[yyleng-1] = '\0'; +- yylval.literal = xstrdup(yytext+1); +- DPRINT("Character literal: %s\n", yylval.literal); ++ struct data d; ++ DPRINT("Character literal: %s\n", yytext); ++ ++ d = data_copy_escape_string(yytext+1, yyleng-2); ++ if (d.len == 1) { ++ lexical_error("Empty character literal"); ++ yylval.integer = 0; ++ return DT_CHAR_LITERAL; ++ } ++ ++ yylval.integer = (unsigned char)d.val[0]; ++ ++ if (d.len > 2) ++ lexical_error("Character literal has %d" ++ " characters instead of 1", ++ d.len - 1); ++ + return DT_CHAR_LITERAL; + } + YY_BREAK +-case 12: ++case 13: + YY_RULE_SETUP +-#line 161 "dtc-lexer.l" ++#line 194 "dtc-lexer.l" + { /* label reference */ + DPRINT("Ref: %s\n", yytext+1); + yylval.labelref = xstrdup(yytext+1); + return DT_REF; + } + YY_BREAK +-case 13: ++case 14: + YY_RULE_SETUP +-#line 167 "dtc-lexer.l" ++#line 200 "dtc-lexer.l" + { /* new-style path reference */ + yytext[yyleng-1] = '\0'; + DPRINT("Ref: %s\n", yytext+2); +@@ -1089,27 +1126,27 @@ + return DT_REF; + } + YY_BREAK +-case 14: ++case 15: + YY_RULE_SETUP +-#line 174 "dtc-lexer.l" ++#line 207 "dtc-lexer.l" + { + yylval.byte = strtol(yytext, NULL, 16); + DPRINT("Byte: %02x\n", (int)yylval.byte); + return DT_BYTE; + } + YY_BREAK +-case 15: ++case 16: + YY_RULE_SETUP +-#line 180 "dtc-lexer.l" ++#line 213 "dtc-lexer.l" + { + DPRINT("/BYTESTRING\n"); + BEGIN_DEFAULT(); + return ']'; + } + YY_BREAK +-case 16: ++case 17: + YY_RULE_SETUP +-#line 186 "dtc-lexer.l" ++#line 219 "dtc-lexer.l" + { + DPRINT("PropNodeName: %s\n", yytext); + yylval.propnodename = xstrdup((yytext[0] == '\\') ? +@@ -1118,75 +1155,75 @@ + return DT_PROPNODENAME; + } + YY_BREAK +-case 17: ++case 18: + YY_RULE_SETUP +-#line 194 "dtc-lexer.l" ++#line 227 "dtc-lexer.l" + { + DPRINT("Binary Include\n"); + return DT_INCBIN; + } + YY_BREAK +-case 18: +-/* rule 18 can match eol */ +-YY_RULE_SETUP +-#line 199 "dtc-lexer.l" +-/* eat whitespace */ +- YY_BREAK + case 19: + /* rule 19 can match eol */ + YY_RULE_SETUP +-#line 200 "dtc-lexer.l" +-/* eat C-style comments */ ++#line 232 "dtc-lexer.l" ++/* eat whitespace */ + YY_BREAK + case 20: + /* rule 20 can match eol */ + YY_RULE_SETUP +-#line 201 "dtc-lexer.l" +-/* eat C++-style comments */ ++#line 233 "dtc-lexer.l" ++/* eat C-style comments */ + YY_BREAK + case 21: ++/* rule 21 can match eol */ + YY_RULE_SETUP +-#line 203 "dtc-lexer.l" +-{ return DT_LSHIFT; }; ++#line 234 "dtc-lexer.l" ++/* eat C++-style comments */ + YY_BREAK + case 22: + YY_RULE_SETUP +-#line 204 "dtc-lexer.l" +-{ return DT_RSHIFT; }; ++#line 236 "dtc-lexer.l" ++{ return DT_LSHIFT; }; + YY_BREAK + case 23: + YY_RULE_SETUP +-#line 205 "dtc-lexer.l" +-{ return DT_LE; }; ++#line 237 "dtc-lexer.l" ++{ return DT_RSHIFT; }; + YY_BREAK + case 24: + YY_RULE_SETUP +-#line 206 "dtc-lexer.l" +-{ return DT_GE; }; ++#line 238 "dtc-lexer.l" ++{ return DT_LE; }; + YY_BREAK + case 25: + YY_RULE_SETUP +-#line 207 "dtc-lexer.l" +-{ return DT_EQ; }; ++#line 239 "dtc-lexer.l" ++{ return DT_GE; }; + YY_BREAK + case 26: + YY_RULE_SETUP +-#line 208 "dtc-lexer.l" +-{ return DT_NE; }; ++#line 240 "dtc-lexer.l" ++{ return DT_EQ; }; + YY_BREAK + case 27: + YY_RULE_SETUP +-#line 209 "dtc-lexer.l" +-{ return DT_AND; }; ++#line 241 "dtc-lexer.l" ++{ return DT_NE; }; + YY_BREAK + case 28: + YY_RULE_SETUP +-#line 210 "dtc-lexer.l" +-{ return DT_OR; }; ++#line 242 "dtc-lexer.l" ++{ return DT_AND; }; + YY_BREAK + case 29: + YY_RULE_SETUP +-#line 212 "dtc-lexer.l" ++#line 243 "dtc-lexer.l" ++{ return DT_OR; }; ++ YY_BREAK ++case 30: ++YY_RULE_SETUP ++#line 245 "dtc-lexer.l" + { + DPRINT("Char: %c (\\x%02x)\n", yytext[0], + (unsigned)yytext[0]); +@@ -1202,12 +1239,12 @@ + return yytext[0]; + } + YY_BREAK +-case 30: ++case 31: + YY_RULE_SETUP +-#line 227 "dtc-lexer.l" ++#line 260 "dtc-lexer.l" + ECHO; + YY_BREAK +-#line 1211 "dtc-lexer.lex.c" ++#line 1248 "dtc-lexer.lex.c" + + case YY_END_OF_BUFFER: + { +@@ -1499,7 +1536,7 @@ + while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) + { + yy_current_state = (int) yy_def[yy_current_state]; +- if ( yy_current_state >= 161 ) ++ if ( yy_current_state >= 166 ) + yy_c = yy_meta[(unsigned int) yy_c]; + } + yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c]; +@@ -1527,11 +1564,11 @@ + while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) + { + yy_current_state = (int) yy_def[yy_current_state]; +- if ( yy_current_state >= 161 ) ++ if ( yy_current_state >= 166 ) + yy_c = yy_meta[(unsigned int) yy_c]; + } + yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c]; +- yy_is_jam = (yy_current_state == 160); ++ yy_is_jam = (yy_current_state == 165); + + return yy_is_jam ? 0 : yy_current_state; + } +@@ -2166,7 +2203,7 @@ + + #define YYTABLES_NAME "yytables" + +-#line 227 "dtc-lexer.l" ++#line 260 "dtc-lexer.l" + + + +@@ -2182,14 +2219,25 @@ + } + + +-static int pop_input_file(void) ++static bool pop_input_file(void) + { + if (srcfile_pop() == 0) +- return 0; ++ return false; + + yypop_buffer_state(); + yyin = current_srcfile->f; + +- return 1; ++ return true; ++} ++ ++static void lexical_error(const char *fmt, ...) ++{ ++ va_list ap; ++ ++ va_start(ap, fmt); ++ srcpos_verror(&yylloc, "Lexical error", fmt, ap); ++ va_end(ap); ++ ++ treesource_error = true; + } + +diff -Nur linux-4.1.13.orig/scripts/dtc/dtc-parser.tab.c_shipped linux-rpi/scripts/dtc/dtc-parser.tab.c_shipped +--- linux-4.1.13.orig/scripts/dtc/dtc-parser.tab.c_shipped 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/scripts/dtc/dtc-parser.tab.c_shipped 2015-11-29 09:42:41.406999830 +0100 +@@ -1,19 +1,19 @@ +-/* A Bison parser, made by GNU Bison 2.7.12-4996. */ ++/* A Bison parser, made by GNU Bison 3.0.2. */ + + /* Bison implementation for Yacc-like parsers in C +- +- Copyright (C) 1984, 1989-1990, 2000-2013 Free Software Foundation, Inc. +- ++ ++ Copyright (C) 1984, 1989-1990, 2000-2013 Free Software Foundation, Inc. ++ + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. +- ++ + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. +- ++ + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +@@ -26,7 +26,7 @@ + special exception, which will cause the skeleton and the resulting + Bison output files to be licensed under the GNU General Public + License without this special exception. +- ++ + This special exception was added by the Free Software Foundation in + version 2.2 of Bison. */ + +@@ -44,7 +44,7 @@ + #define YYBISON 1 + + /* Bison version. */ +-#define YYBISON_VERSION "2.7.12-4996" ++#define YYBISON_VERSION "3.0.2" + + /* Skeleton name. */ + #define YYSKELETON_NAME "yacc.c" +@@ -62,34 +62,32 @@ + + + /* Copy the first part of user declarations. */ +-/* Line 371 of yacc.c */ +-#line 21 "dtc-parser.y" ++#line 20 "dtc-parser.y" /* yacc.c:339 */ + + #include ++#include + + #include "dtc.h" + #include "srcpos.h" + +-YYLTYPE yylloc; +- + extern int yylex(void); +-extern void print_error(char const *fmt, ...); + extern void yyerror(char const *s); ++#define ERROR(loc, ...) \ ++ do { \ ++ srcpos_error((loc), "Error", __VA_ARGS__); \ ++ treesource_error = true; \ ++ } while (0) + + extern struct boot_info *the_boot_info; +-extern int treesource_error; +- +-static unsigned long long eval_literal(const char *s, int base, int bits); +-static unsigned char eval_char_literal(const char *s); ++extern bool treesource_error; + +-/* Line 371 of yacc.c */ +-#line 87 "dtc-parser.tab.c" ++#line 85 "dtc-parser.tab.c" /* yacc.c:339 */ + +-# ifndef YY_NULL ++# ifndef YY_NULLPTR + # if defined __cplusplus && 201103L <= __cplusplus +-# define YY_NULL nullptr ++# define YY_NULLPTR nullptr + # else +-# define YY_NULL 0 ++# define YY_NULLPTR 0 + # endif + # endif + +@@ -105,7 +103,7 @@ + by #include "dtc-parser.tab.h". */ + #ifndef YY_YY_DTC_PARSER_TAB_H_INCLUDED + # define YY_YY_DTC_PARSER_TAB_H_INCLUDED +-/* Enabling traces. */ ++/* Debug traces. */ + #ifndef YYDEBUG + # define YYDEBUG 0 + #endif +@@ -113,48 +111,45 @@ + extern int yydebug; + #endif + +-/* Tokens. */ ++/* Token type. */ + #ifndef YYTOKENTYPE + # define YYTOKENTYPE +- /* Put the tokens into the symbol table, so that GDB and other debuggers +- know about them. */ +- enum yytokentype { +- DT_V1 = 258, +- DT_MEMRESERVE = 259, +- DT_LSHIFT = 260, +- DT_RSHIFT = 261, +- DT_LE = 262, +- DT_GE = 263, +- DT_EQ = 264, +- DT_NE = 265, +- DT_AND = 266, +- DT_OR = 267, +- DT_BITS = 268, +- DT_DEL_PROP = 269, +- DT_DEL_NODE = 270, +- DT_PROPNODENAME = 271, +- DT_LITERAL = 272, +- DT_CHAR_LITERAL = 273, +- DT_BASE = 274, +- DT_BYTE = 275, +- DT_STRING = 276, +- DT_LABEL = 277, +- DT_REF = 278, +- DT_INCBIN = 279 +- }; ++ enum yytokentype ++ { ++ DT_V1 = 258, ++ DT_PLUGIN = 259, ++ DT_MEMRESERVE = 260, ++ DT_LSHIFT = 261, ++ DT_RSHIFT = 262, ++ DT_LE = 263, ++ DT_GE = 264, ++ DT_EQ = 265, ++ DT_NE = 266, ++ DT_AND = 267, ++ DT_OR = 268, ++ DT_BITS = 269, ++ DT_DEL_PROP = 270, ++ DT_DEL_NODE = 271, ++ DT_PROPNODENAME = 272, ++ DT_LITERAL = 273, ++ DT_CHAR_LITERAL = 274, ++ DT_BYTE = 275, ++ DT_STRING = 276, ++ DT_LABEL = 277, ++ DT_REF = 278, ++ DT_INCBIN = 279 ++ }; + #endif + +- ++/* Value type. */ + #if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED +-typedef union YYSTYPE ++typedef union YYSTYPE YYSTYPE; ++union YYSTYPE + { +-/* Line 387 of yacc.c */ +-#line 40 "dtc-parser.y" ++#line 39 "dtc-parser.y" /* yacc.c:355 */ + + char *propnodename; +- char *literal; + char *labelref; +- unsigned int cbase; + uint8_t byte; + struct data data; + +@@ -169,38 +164,38 @@ + struct node *nodelist; + struct reserve_info *re; + uint64_t integer; ++ int is_plugin; + +- +-/* Line 387 of yacc.c */ +-#line 176 "dtc-parser.tab.c" +-} YYSTYPE; ++#line 170 "dtc-parser.tab.c" /* yacc.c:355 */ ++}; + # define YYSTYPE_IS_TRIVIAL 1 +-# define yystype YYSTYPE /* obsolescent; will be withdrawn */ + # define YYSTYPE_IS_DECLARED 1 + #endif + +-extern YYSTYPE yylval; +- +-#ifdef YYPARSE_PARAM +-#if defined __STDC__ || defined __cplusplus +-int yyparse (void *YYPARSE_PARAM); +-#else +-int yyparse (); ++/* Location type. */ ++#if ! defined YYLTYPE && ! defined YYLTYPE_IS_DECLARED ++typedef struct YYLTYPE YYLTYPE; ++struct YYLTYPE ++{ ++ int first_line; ++ int first_column; ++ int last_line; ++ int last_column; ++}; ++# define YYLTYPE_IS_DECLARED 1 ++# define YYLTYPE_IS_TRIVIAL 1 + #endif +-#else /* ! YYPARSE_PARAM */ +-#if defined __STDC__ || defined __cplusplus ++ ++ ++extern YYSTYPE yylval; ++extern YYLTYPE yylloc; + int yyparse (void); +-#else +-int yyparse (); +-#endif +-#endif /* ! YYPARSE_PARAM */ + + #endif /* !YY_YY_DTC_PARSER_TAB_H_INCLUDED */ + + /* Copy the second part of user declarations. */ + +-/* Line 390 of yacc.c */ +-#line 204 "dtc-parser.tab.c" ++#line 199 "dtc-parser.tab.c" /* yacc.c:358 */ + + #ifdef short + # undef short +@@ -214,11 +209,8 @@ + + #ifdef YYTYPE_INT8 + typedef YYTYPE_INT8 yytype_int8; +-#elif (defined __STDC__ || defined __C99__FUNC__ \ +- || defined __cplusplus || defined _MSC_VER) +-typedef signed char yytype_int8; + #else +-typedef short int yytype_int8; ++typedef signed char yytype_int8; + #endif + + #ifdef YYTYPE_UINT16 +@@ -238,8 +230,7 @@ + # define YYSIZE_T __SIZE_TYPE__ + # elif defined size_t + # define YYSIZE_T size_t +-# elif ! defined YYSIZE_T && (defined __STDC__ || defined __C99__FUNC__ \ +- || defined __cplusplus || defined _MSC_VER) ++# elif ! defined YYSIZE_T + # include /* INFRINGES ON USER NAME SPACE */ + # define YYSIZE_T size_t + # else +@@ -261,11 +252,30 @@ + # endif + #endif + +-#ifndef __attribute__ +-/* This feature is available in gcc versions 2.5 and later. */ +-# if (! defined __GNUC__ || __GNUC__ < 2 \ +- || (__GNUC__ == 2 && __GNUC_MINOR__ < 5)) +-# define __attribute__(Spec) /* empty */ ++#ifndef YY_ATTRIBUTE ++# if (defined __GNUC__ \ ++ && (2 < __GNUC__ || (__GNUC__ == 2 && 96 <= __GNUC_MINOR__))) \ ++ || defined __SUNPRO_C && 0x5110 <= __SUNPRO_C ++# define YY_ATTRIBUTE(Spec) __attribute__(Spec) ++# else ++# define YY_ATTRIBUTE(Spec) /* empty */ ++# endif ++#endif ++ ++#ifndef YY_ATTRIBUTE_PURE ++# define YY_ATTRIBUTE_PURE YY_ATTRIBUTE ((__pure__)) ++#endif ++ ++#ifndef YY_ATTRIBUTE_UNUSED ++# define YY_ATTRIBUTE_UNUSED YY_ATTRIBUTE ((__unused__)) ++#endif ++ ++#if !defined _Noreturn \ ++ && (!defined __STDC_VERSION__ || __STDC_VERSION__ < 201112) ++# if defined _MSC_VER && 1200 <= _MSC_VER ++# define _Noreturn __declspec (noreturn) ++# else ++# define _Noreturn YY_ATTRIBUTE ((__noreturn__)) + # endif + #endif + +@@ -276,24 +286,25 @@ + # define YYUSE(E) /* empty */ + #endif + +- +-/* Identity function, used to suppress warnings about constant conditions. */ +-#ifndef lint +-# define YYID(N) (N) +-#else +-#if (defined __STDC__ || defined __C99__FUNC__ \ +- || defined __cplusplus || defined _MSC_VER) +-static int +-YYID (int yyi) ++#if defined __GNUC__ && 407 <= __GNUC__ * 100 + __GNUC_MINOR__ ++/* Suppress an incorrect diagnostic about yylval being uninitialized. */ ++# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \ ++ _Pragma ("GCC diagnostic push") \ ++ _Pragma ("GCC diagnostic ignored \"-Wuninitialized\"")\ ++ _Pragma ("GCC diagnostic ignored \"-Wmaybe-uninitialized\"") ++# define YY_IGNORE_MAYBE_UNINITIALIZED_END \ ++ _Pragma ("GCC diagnostic pop") + #else +-static int +-YYID (yyi) +- int yyi; ++# define YY_INITIAL_VALUE(Value) Value + #endif +-{ +- return yyi; +-} ++#ifndef YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN ++# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN ++# define YY_IGNORE_MAYBE_UNINITIALIZED_END + #endif ++#ifndef YY_INITIAL_VALUE ++# define YY_INITIAL_VALUE(Value) /* Nothing. */ ++#endif ++ + + #if ! defined yyoverflow || YYERROR_VERBOSE + +@@ -312,8 +323,7 @@ + # define alloca _alloca + # else + # define YYSTACK_ALLOC alloca +-# if ! defined _ALLOCA_H && ! defined EXIT_SUCCESS && (defined __STDC__ || defined __C99__FUNC__ \ +- || defined __cplusplus || defined _MSC_VER) ++# if ! defined _ALLOCA_H && ! defined EXIT_SUCCESS + # include /* INFRINGES ON USER NAME SPACE */ + /* Use EXIT_SUCCESS as a witness for stdlib.h. */ + # ifndef EXIT_SUCCESS +@@ -325,8 +335,8 @@ + # endif + + # ifdef YYSTACK_ALLOC +- /* Pacify GCC's `empty if-body' warning. */ +-# define YYSTACK_FREE(Ptr) do { /* empty */; } while (YYID (0)) ++ /* Pacify GCC's 'empty if-body' warning. */ ++# define YYSTACK_FREE(Ptr) do { /* empty */; } while (0) + # ifndef YYSTACK_ALLOC_MAXIMUM + /* The OS might guarantee only one guard page at the bottom of the stack, + and a page size can be as small as 4096 bytes. So we cannot safely +@@ -342,7 +352,7 @@ + # endif + # if (defined __cplusplus && ! defined EXIT_SUCCESS \ + && ! ((defined YYMALLOC || defined malloc) \ +- && (defined YYFREE || defined free))) ++ && (defined YYFREE || defined free))) + # include /* INFRINGES ON USER NAME SPACE */ + # ifndef EXIT_SUCCESS + # define EXIT_SUCCESS 0 +@@ -350,15 +360,13 @@ + # endif + # ifndef YYMALLOC + # define YYMALLOC malloc +-# if ! defined malloc && ! defined EXIT_SUCCESS && (defined __STDC__ || defined __C99__FUNC__ \ +- || defined __cplusplus || defined _MSC_VER) ++# if ! defined malloc && ! defined EXIT_SUCCESS + void *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */ + # endif + # endif + # ifndef YYFREE + # define YYFREE free +-# if ! defined free && ! defined EXIT_SUCCESS && (defined __STDC__ || defined __C99__FUNC__ \ +- || defined __cplusplus || defined _MSC_VER) ++# if ! defined free && ! defined EXIT_SUCCESS + void free (void *); /* INFRINGES ON USER NAME SPACE */ + # endif + # endif +@@ -368,13 +376,15 @@ + + #if (! defined yyoverflow \ + && (! defined __cplusplus \ +- || (defined YYSTYPE_IS_TRIVIAL && YYSTYPE_IS_TRIVIAL))) ++ || (defined YYLTYPE_IS_TRIVIAL && YYLTYPE_IS_TRIVIAL \ ++ && defined YYSTYPE_IS_TRIVIAL && YYSTYPE_IS_TRIVIAL))) + + /* A type that is properly aligned for any stack member. */ + union yyalloc + { + yytype_int16 yyss_alloc; + YYSTYPE yyvs_alloc; ++ YYLTYPE yyls_alloc; + }; + + /* The size of the maximum gap between one aligned stack and the next. */ +@@ -383,8 +393,8 @@ + /* The size of an array large to enough to hold all stacks, each with + N elements. */ + # define YYSTACK_BYTES(N) \ +- ((N) * (sizeof (yytype_int16) + sizeof (YYSTYPE)) \ +- + YYSTACK_GAP_MAXIMUM) ++ ((N) * (sizeof (yytype_int16) + sizeof (YYSTYPE) + sizeof (YYLTYPE)) \ ++ + 2 * YYSTACK_GAP_MAXIMUM) + + # define YYCOPY_NEEDED 1 + +@@ -393,16 +403,16 @@ + elements in the stack, and YYPTR gives the new location of the + stack. Advance YYPTR to a properly aligned location for the next + stack. */ +-# define YYSTACK_RELOCATE(Stack_alloc, Stack) \ +- do \ +- { \ +- YYSIZE_T yynewbytes; \ +- YYCOPY (&yyptr->Stack_alloc, Stack, yysize); \ +- Stack = &yyptr->Stack_alloc; \ +- yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \ +- yyptr += yynewbytes / sizeof (*yyptr); \ +- } \ +- while (YYID (0)) ++# define YYSTACK_RELOCATE(Stack_alloc, Stack) \ ++ do \ ++ { \ ++ YYSIZE_T yynewbytes; \ ++ YYCOPY (&yyptr->Stack_alloc, Stack, yysize); \ ++ Stack = &yyptr->Stack_alloc; \ ++ yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \ ++ yyptr += yynewbytes / sizeof (*yyptr); \ ++ } \ ++ while (0) + + #endif + +@@ -421,7 +431,7 @@ + for (yyi = 0; yyi < (Count); yyi++) \ + (Dst)[yyi] = (Src)[yyi]; \ + } \ +- while (YYID (0)) ++ while (0) + # endif + # endif + #endif /* !YYCOPY_NEEDED */ +@@ -429,25 +439,27 @@ + /* YYFINAL -- State number of the termination state. */ + #define YYFINAL 4 + /* YYLAST -- Last index in YYTABLE. */ +-#define YYLAST 133 ++#define YYLAST 135 + + /* YYNTOKENS -- Number of terminals. */ + #define YYNTOKENS 48 + /* YYNNTS -- Number of nonterminals. */ +-#define YYNNTS 28 ++#define YYNNTS 29 + /* YYNRULES -- Number of rules. */ +-#define YYNRULES 79 +-/* YYNRULES -- Number of states. */ +-#define YYNSTATES 141 ++#define YYNRULES 81 ++/* YYNSTATES -- Number of states. */ ++#define YYNSTATES 144 + +-/* YYTRANSLATE(YYLEX) -- Bison symbol number corresponding to YYLEX. */ ++/* YYTRANSLATE[YYX] -- Symbol number corresponding to YYX as returned ++ by yylex, with out-of-bounds checking. */ + #define YYUNDEFTOK 2 + #define YYMAXUTOK 279 + +-#define YYTRANSLATE(YYX) \ ++#define YYTRANSLATE(YYX) \ + ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK) + +-/* YYTRANSLATE[YYLEX] -- Bison symbol number corresponding to YYLEX. */ ++/* YYTRANSLATE[TOKEN-NUM] -- Symbol number corresponding to TOKEN-NUM ++ as returned by yylex, without out-of-bounds checking. */ + static const yytype_uint8 yytranslate[] = + { + 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, +@@ -481,63 +493,18 @@ + }; + + #if YYDEBUG +-/* YYPRHS[YYN] -- Index of the first RHS symbol of rule number YYN in +- YYRHS. */ +-static const yytype_uint16 yyprhs[] = +-{ +- 0, 0, 3, 8, 9, 12, 17, 20, 23, 27, +- 31, 36, 42, 43, 46, 51, 54, 58, 61, 64, +- 68, 73, 76, 86, 92, 95, 96, 99, 102, 106, +- 108, 111, 114, 117, 119, 121, 125, 127, 129, 135, +- 137, 141, 143, 147, 149, 153, 155, 159, 161, 165, +- 167, 171, 175, 177, 181, 185, 189, 193, 197, 201, +- 203, 207, 211, 213, 217, 221, 225, 227, 229, 232, +- 235, 238, 239, 242, 245, 246, 249, 252, 255, 259 +-}; +- +-/* YYRHS -- A `-1'-separated list of the rules' RHS. */ +-static const yytype_int8 yyrhs[] = +-{ +- 49, 0, -1, 3, 25, 50, 52, -1, -1, 51, +- 50, -1, 4, 59, 59, 25, -1, 22, 51, -1, +- 26, 53, -1, 52, 26, 53, -1, 52, 23, 53, +- -1, 52, 15, 23, 25, -1, 27, 54, 74, 28, +- 25, -1, -1, 54, 55, -1, 16, 29, 56, 25, +- -1, 16, 25, -1, 14, 16, 25, -1, 22, 55, +- -1, 57, 21, -1, 57, 58, 30, -1, 57, 31, +- 73, 32, -1, 57, 23, -1, 57, 24, 33, 21, +- 34, 59, 34, 59, 35, -1, 57, 24, 33, 21, +- 35, -1, 56, 22, -1, -1, 56, 34, -1, 57, +- 22, -1, 13, 17, 36, -1, 36, -1, 58, 59, +- -1, 58, 23, -1, 58, 22, -1, 17, -1, 18, +- -1, 33, 60, 35, -1, 61, -1, 62, -1, 62, +- 37, 60, 38, 61, -1, 63, -1, 62, 12, 63, +- -1, 64, -1, 63, 11, 64, -1, 65, -1, 64, +- 39, 65, -1, 66, -1, 65, 40, 66, -1, 67, +- -1, 66, 41, 67, -1, 68, -1, 67, 9, 68, +- -1, 67, 10, 68, -1, 69, -1, 68, 36, 69, +- -1, 68, 30, 69, -1, 68, 7, 69, -1, 68, +- 8, 69, -1, 69, 5, 70, -1, 69, 6, 70, +- -1, 70, -1, 70, 42, 71, -1, 70, 43, 71, +- -1, 71, -1, 71, 44, 72, -1, 71, 26, 72, +- -1, 71, 45, 72, -1, 72, -1, 59, -1, 43, +- 72, -1, 46, 72, -1, 47, 72, -1, -1, 73, +- 20, -1, 73, 22, -1, -1, 75, 74, -1, 75, +- 55, -1, 16, 53, -1, 15, 16, 25, -1, 22, +- 75, -1 +-}; +- +-/* YYRLINE[YYN] -- source line where rule number YYN was defined. */ ++ /* YYRLINE[YYN] -- Source line where rule number YYN was defined. */ + static const yytype_uint16 yyrline[] = + { +- 0, 109, 109, 118, 121, 128, 132, 140, 144, 148, +- 158, 172, 180, 183, 190, 194, 198, 202, 210, 214, +- 218, 222, 226, 243, 253, 261, 264, 268, 275, 290, +- 295, 315, 329, 336, 340, 344, 351, 355, 356, 360, +- 361, 365, 366, 370, 371, 375, 376, 380, 381, 385, +- 386, 387, 391, 392, 393, 394, 395, 399, 400, 401, +- 405, 406, 407, 411, 412, 413, 414, 418, 419, 420, +- 421, 426, 429, 433, 441, 444, 448, 456, 460, 464 ++ 0, 108, 108, 119, 122, 130, 133, 140, 144, 152, ++ 156, 160, 170, 185, 193, 196, 203, 207, 211, 215, ++ 223, 227, 231, 235, 239, 255, 265, 273, 276, 280, ++ 287, 303, 308, 327, 341, 348, 349, 350, 357, 361, ++ 362, 366, 367, 371, 372, 376, 377, 381, 382, 386, ++ 387, 391, 392, 393, 397, 398, 399, 400, 401, 405, ++ 406, 407, 411, 412, 413, 417, 418, 419, 420, 424, ++ 425, 426, 427, 432, 435, 439, 447, 450, 454, 462, ++ 466, 470 + }; + #endif + +@@ -546,25 +513,25 @@ + First, the terminals, then, starting at YYNTOKENS, nonterminals. */ + static const char *const yytname[] = + { +- "$end", "error", "$undefined", "DT_V1", "DT_MEMRESERVE", "DT_LSHIFT", +- "DT_RSHIFT", "DT_LE", "DT_GE", "DT_EQ", "DT_NE", "DT_AND", "DT_OR", +- "DT_BITS", "DT_DEL_PROP", "DT_DEL_NODE", "DT_PROPNODENAME", "DT_LITERAL", +- "DT_CHAR_LITERAL", "DT_BASE", "DT_BYTE", "DT_STRING", "DT_LABEL", ++ "$end", "error", "$undefined", "DT_V1", "DT_PLUGIN", "DT_MEMRESERVE", ++ "DT_LSHIFT", "DT_RSHIFT", "DT_LE", "DT_GE", "DT_EQ", "DT_NE", "DT_AND", ++ "DT_OR", "DT_BITS", "DT_DEL_PROP", "DT_DEL_NODE", "DT_PROPNODENAME", ++ "DT_LITERAL", "DT_CHAR_LITERAL", "DT_BYTE", "DT_STRING", "DT_LABEL", + "DT_REF", "DT_INCBIN", "';'", "'/'", "'{'", "'}'", "'='", "'>'", "'['", + "']'", "'('", "','", "')'", "'<'", "'?'", "':'", "'|'", "'^'", "'&'", + "'+'", "'-'", "'*'", "'%'", "'~'", "'!'", "$accept", "sourcefile", +- "memreserves", "memreserve", "devicetree", "nodedef", "proplist", +- "propdef", "propdata", "propdataprefix", "arrayprefix", "integer_prim", +- "integer_expr", "integer_trinary", "integer_or", "integer_and", +- "integer_bitor", "integer_bitxor", "integer_bitand", "integer_eq", +- "integer_rela", "integer_shift", "integer_add", "integer_mul", +- "integer_unary", "bytestring", "subnodes", "subnode", YY_NULL ++ "plugindecl", "memreserves", "memreserve", "devicetree", "nodedef", ++ "proplist", "propdef", "propdata", "propdataprefix", "arrayprefix", ++ "integer_prim", "integer_expr", "integer_trinary", "integer_or", ++ "integer_and", "integer_bitor", "integer_bitxor", "integer_bitand", ++ "integer_eq", "integer_rela", "integer_shift", "integer_add", ++ "integer_mul", "integer_unary", "bytestring", "subnodes", "subnode", YY_NULLPTR + }; + #endif + + # ifdef YYPRINT +-/* YYTOKNUM[YYLEX-NUM] -- Internal token number corresponding to +- token YYLEX-NUM. */ ++/* YYTOKNUM[NUM] -- (External) token number corresponding to the ++ (internal) symbol number NUM (which must be that of a token). */ + static const yytype_uint16 yytoknum[] = + { + 0, 256, 257, 258, 259, 260, 261, 262, 263, 264, +@@ -575,183 +542,173 @@ + }; + # endif + +-/* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */ +-static const yytype_uint8 yyr1[] = +-{ +- 0, 48, 49, 50, 50, 51, 51, 52, 52, 52, +- 52, 53, 54, 54, 55, 55, 55, 55, 56, 56, +- 56, 56, 56, 56, 56, 57, 57, 57, 58, 58, +- 58, 58, 58, 59, 59, 59, 60, 61, 61, 62, +- 62, 63, 63, 64, 64, 65, 65, 66, 66, 67, +- 67, 67, 68, 68, 68, 68, 68, 69, 69, 69, +- 70, 70, 70, 71, 71, 71, 71, 72, 72, 72, +- 72, 73, 73, 73, 74, 74, 74, 75, 75, 75 +-}; ++#define YYPACT_NINF -41 + +-/* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN. */ +-static const yytype_uint8 yyr2[] = ++#define yypact_value_is_default(Yystate) \ ++ (!!((Yystate) == (-41))) ++ ++#define YYTABLE_NINF -1 ++ ++#define yytable_value_is_error(Yytable_value) \ ++ 0 ++ ++ /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing ++ STATE-NUM. */ ++static const yytype_int8 yypact[] = + { +- 0, 2, 4, 0, 2, 4, 2, 2, 3, 3, +- 4, 5, 0, 2, 4, 2, 3, 2, 2, 3, +- 4, 2, 9, 5, 2, 0, 2, 2, 3, 1, +- 2, 2, 2, 1, 1, 3, 1, 1, 5, 1, +- 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, +- 3, 3, 1, 3, 3, 3, 3, 3, 3, 1, +- 3, 3, 1, 3, 3, 3, 1, 1, 2, 2, +- 2, 0, 2, 2, 0, 2, 2, 2, 3, 2 ++ 37, 10, 24, 78, -41, 20, 9, -41, 8, 9, ++ 59, 9, -41, -41, -10, 8, -41, 60, 39, -41, ++ -10, -10, -10, -41, 51, -41, -7, 76, 50, 52, ++ 53, 49, 2, 65, 32, -1, -41, 66, -41, -41, ++ 67, 60, 60, -41, -41, -41, -41, -10, -10, -10, ++ -10, -10, -10, -10, -10, -10, -10, -10, -10, -10, ++ -10, -10, -10, -10, -10, -10, -41, 41, 68, -41, ++ -41, 76, 57, 50, 52, 53, 49, 2, 2, 65, ++ 65, 65, 65, 32, 32, -1, -1, -41, -41, -41, ++ 79, 80, -12, 41, -41, 70, 41, -41, -10, 74, ++ 75, -41, -41, -41, -41, -41, 77, -41, -41, -41, ++ -41, -41, 17, -2, -41, -41, -41, -41, 83, -41, ++ -41, -41, 71, -41, -41, 31, 69, 82, -4, -41, ++ -41, -41, -41, -41, 42, -41, -41, -41, 8, -41, ++ 72, 8, 73, -41 + }; + +-/* YYDEFACT[STATE-NAME] -- Default reduction number in state STATE-NUM. +- Performed when YYTABLE doesn't specify something else to do. Zero +- means the default is an error. */ ++ /* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM. ++ Performed when YYTABLE does not specify something else to do. Zero ++ means the default is an error. */ + static const yytype_uint8 yydefact[] = + { +- 0, 0, 0, 3, 1, 0, 0, 0, 3, 33, +- 34, 0, 0, 6, 0, 2, 4, 0, 0, 0, +- 67, 0, 36, 37, 39, 41, 43, 45, 47, 49, +- 52, 59, 62, 66, 0, 12, 7, 0, 0, 0, +- 68, 69, 70, 35, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 3, 1, 0, 5, 4, 0, 0, ++ 0, 5, 35, 36, 0, 0, 8, 0, 2, 6, ++ 0, 0, 0, 69, 0, 38, 39, 41, 43, 45, ++ 47, 49, 51, 54, 61, 64, 68, 0, 14, 9, ++ 0, 0, 0, 70, 71, 72, 37, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +- 0, 0, 0, 5, 74, 0, 9, 8, 40, 0, +- 42, 44, 46, 48, 50, 51, 55, 56, 54, 53, +- 57, 58, 60, 61, 64, 63, 65, 0, 0, 0, +- 0, 13, 0, 74, 10, 0, 0, 0, 15, 25, +- 77, 17, 79, 0, 76, 75, 38, 16, 78, 0, +- 0, 11, 24, 14, 26, 0, 18, 27, 21, 0, +- 71, 29, 0, 0, 0, 0, 32, 31, 19, 30, +- 28, 0, 72, 73, 20, 0, 23, 0, 0, 0, +- 22 ++ 0, 0, 0, 0, 0, 0, 7, 76, 0, 11, ++ 10, 42, 0, 44, 46, 48, 50, 52, 53, 57, ++ 58, 56, 55, 59, 60, 62, 63, 66, 65, 67, ++ 0, 0, 0, 0, 15, 0, 76, 12, 0, 0, ++ 0, 17, 27, 79, 19, 81, 0, 78, 77, 40, ++ 18, 80, 0, 0, 13, 26, 16, 28, 0, 20, ++ 29, 23, 0, 73, 31, 0, 0, 0, 0, 34, ++ 33, 21, 32, 30, 0, 74, 75, 22, 0, 25, ++ 0, 0, 0, 24 + }; + +-/* YYDEFGOTO[NTERM-NUM]. */ +-static const yytype_int8 yydefgoto[] = ++ /* YYPGOTO[NTERM-NUM]. */ ++static const yytype_int8 yypgoto[] = + { +- -1, 2, 7, 8, 15, 36, 64, 91, 109, 110, +- 122, 20, 21, 22, 23, 24, 25, 26, 27, 28, +- 29, 30, 31, 32, 33, 125, 92, 93 ++ -41, -41, -41, 96, 100, -41, -40, -41, -23, -41, ++ -41, -41, -8, 62, 13, -41, 81, 63, 64, 84, ++ 61, 25, 11, 21, 22, -17, -41, 19, 23 + }; + +-/* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing +- STATE-NUM. */ +-#define YYPACT_NINF -78 +-static const yytype_int8 yypact[] = ++ /* YYDEFGOTO[NTERM-NUM]. */ ++static const yytype_int16 yydefgoto[] = + { +- 22, 11, 51, 10, -78, 23, 10, 2, 10, -78, +- -78, -9, 23, -78, 30, 38, -78, -9, -9, -9, +- -78, 35, -78, -6, 52, 29, 48, 49, 33, 3, +- 71, 36, 0, -78, 64, -78, -78, 68, 30, 30, +- -78, -78, -78, -78, -9, -9, -9, -9, -9, -9, +- -9, -9, -9, -9, -9, -9, -9, -9, -9, -9, +- -9, -9, -9, -78, 44, 67, -78, -78, 52, 55, +- 29, 48, 49, 33, 3, 3, 71, 71, 71, 71, +- 36, 36, 0, 0, -78, -78, -78, 78, 79, 42, +- 44, -78, 69, 44, -78, -9, 73, 74, -78, -78, +- -78, -78, -78, 75, -78, -78, -78, -78, -78, -7, +- -1, -78, -78, -78, -78, 84, -78, -78, -78, 63, +- -78, -78, 32, 66, 82, -3, -78, -78, -78, -78, +- -78, 46, -78, -78, -78, 23, -78, 70, 23, 72, +- -78 ++ -1, 2, 6, 10, 11, 18, 39, 67, 94, 112, ++ 113, 125, 23, 24, 25, 26, 27, 28, 29, 30, ++ 31, 32, 33, 34, 35, 36, 128, 95, 96 + }; + +-/* YYPGOTO[NTERM-NUM]. */ +-static const yytype_int8 yypgoto[] = ++ /* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM. If ++ positive, shift that token. If negative, reduce the rule whose ++ number is the opposite. If YYTABLE_NINF, syntax error. */ ++static const yytype_uint8 yytable[] = + { +- -78, -78, 97, 100, -78, -37, -78, -77, -78, -78, +- -78, -5, 65, 13, -78, 76, 77, 62, 80, 83, +- 34, 20, 26, 28, -14, -78, 18, 24 ++ 15, 69, 70, 43, 44, 45, 47, 37, 12, 13, ++ 55, 56, 118, 101, 8, 38, 135, 102, 136, 119, ++ 120, 121, 122, 14, 4, 63, 12, 13, 137, 123, ++ 48, 9, 57, 20, 124, 3, 21, 22, 58, 115, ++ 1, 14, 116, 64, 65, 7, 87, 88, 89, 12, ++ 13, 117, 103, 129, 130, 40, 90, 91, 92, 53, ++ 54, 131, 41, 93, 14, 42, 79, 80, 81, 82, ++ 104, 59, 60, 107, 61, 62, 138, 139, 77, 78, ++ 83, 84, 5, 85, 86, 17, 46, 38, 49, 50, ++ 68, 66, 51, 97, 52, 98, 99, 100, 106, 110, ++ 111, 126, 114, 134, 127, 133, 141, 19, 143, 16, ++ 72, 109, 73, 76, 74, 108, 105, 132, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 71, 0, ++ 140, 0, 0, 142, 0, 75 + }; + +-/* YYTABLE[YYPACT[STATE-NUM]]. What to do in state STATE-NUM. If +- positive, shift that token. If negative, reduce the rule which +- number is the opposite. If YYTABLE_NINF, syntax error. */ +-#define YYTABLE_NINF -1 +-static const yytype_uint8 yytable[] = ++static const yytype_int16 yycheck[] = + { +- 12, 66, 67, 40, 41, 42, 44, 34, 9, 10, +- 52, 53, 115, 101, 5, 112, 104, 132, 113, 133, +- 116, 117, 118, 119, 11, 1, 60, 114, 14, 134, +- 120, 45, 6, 54, 17, 121, 3, 18, 19, 55, +- 9, 10, 50, 51, 61, 62, 84, 85, 86, 9, +- 10, 4, 100, 37, 126, 127, 11, 35, 87, 88, +- 89, 38, 128, 46, 39, 11, 90, 98, 47, 35, +- 43, 99, 76, 77, 78, 79, 56, 57, 58, 59, +- 135, 136, 80, 81, 74, 75, 82, 83, 48, 63, +- 49, 65, 94, 95, 96, 97, 124, 103, 107, 108, +- 111, 123, 130, 131, 138, 16, 13, 140, 106, 71, +- 69, 105, 0, 0, 102, 0, 0, 129, 0, 0, +- 68, 0, 0, 70, 0, 0, 0, 0, 72, 0, +- 137, 0, 73, 139 ++ 8, 41, 42, 20, 21, 22, 13, 15, 18, 19, ++ 8, 9, 14, 25, 5, 27, 20, 29, 22, 21, ++ 22, 23, 24, 33, 0, 26, 18, 19, 32, 31, ++ 37, 22, 30, 43, 36, 25, 46, 47, 36, 22, ++ 3, 33, 25, 44, 45, 25, 63, 64, 65, 18, ++ 19, 34, 92, 22, 23, 16, 15, 16, 17, 10, ++ 11, 30, 23, 22, 33, 26, 55, 56, 57, 58, ++ 93, 6, 7, 96, 42, 43, 34, 35, 53, 54, ++ 59, 60, 4, 61, 62, 26, 35, 27, 12, 39, ++ 23, 25, 40, 25, 41, 38, 17, 17, 28, 25, ++ 25, 18, 25, 21, 33, 36, 34, 11, 35, 9, ++ 48, 98, 49, 52, 50, 96, 93, 125, -1, -1, ++ -1, -1, -1, -1, -1, -1, -1, -1, 47, -1, ++ 138, -1, -1, 141, -1, 51 + }; + +-#define yypact_value_is_default(Yystate) \ +- (!!((Yystate) == (-78))) +- +-#define yytable_value_is_error(Yytable_value) \ +- YYID (0) ++ /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing ++ symbol of state STATE-NUM. */ ++static const yytype_uint8 yystos[] = ++{ ++ 0, 3, 49, 25, 0, 4, 50, 25, 5, 22, ++ 51, 52, 18, 19, 33, 60, 52, 26, 53, 51, ++ 43, 46, 47, 60, 61, 62, 63, 64, 65, 66, ++ 67, 68, 69, 70, 71, 72, 73, 60, 27, 54, ++ 16, 23, 26, 73, 73, 73, 35, 13, 37, 12, ++ 39, 40, 41, 10, 11, 8, 9, 30, 36, 6, ++ 7, 42, 43, 26, 44, 45, 25, 55, 23, 54, ++ 54, 64, 61, 65, 66, 67, 68, 69, 69, 70, ++ 70, 70, 70, 71, 71, 72, 72, 73, 73, 73, ++ 15, 16, 17, 22, 56, 75, 76, 25, 38, 17, ++ 17, 25, 29, 54, 56, 76, 28, 56, 75, 62, ++ 25, 25, 57, 58, 25, 22, 25, 34, 14, 21, ++ 22, 23, 24, 31, 36, 59, 18, 33, 74, 22, ++ 23, 30, 60, 36, 21, 20, 22, 32, 34, 35, ++ 60, 34, 60, 35 ++}; + +-static const yytype_int16 yycheck[] = ++ /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */ ++static const yytype_uint8 yyr1[] = + { +- 5, 38, 39, 17, 18, 19, 12, 12, 17, 18, +- 7, 8, 13, 90, 4, 22, 93, 20, 25, 22, +- 21, 22, 23, 24, 33, 3, 26, 34, 26, 32, +- 31, 37, 22, 30, 43, 36, 25, 46, 47, 36, +- 17, 18, 9, 10, 44, 45, 60, 61, 62, 17, +- 18, 0, 89, 15, 22, 23, 33, 27, 14, 15, +- 16, 23, 30, 11, 26, 33, 22, 25, 39, 27, +- 35, 29, 52, 53, 54, 55, 5, 6, 42, 43, +- 34, 35, 56, 57, 50, 51, 58, 59, 40, 25, +- 41, 23, 25, 38, 16, 16, 33, 28, 25, 25, +- 25, 17, 36, 21, 34, 8, 6, 35, 95, 47, +- 45, 93, -1, -1, 90, -1, -1, 122, -1, -1, +- 44, -1, -1, 46, -1, -1, -1, -1, 48, -1, +- 135, -1, 49, 138 ++ 0, 48, 49, 50, 50, 51, 51, 52, 52, 53, ++ 53, 53, 53, 54, 55, 55, 56, 56, 56, 56, ++ 57, 57, 57, 57, 57, 57, 57, 58, 58, 58, ++ 59, 59, 59, 59, 59, 60, 60, 60, 61, 62, ++ 62, 63, 63, 64, 64, 65, 65, 66, 66, 67, ++ 67, 68, 68, 68, 69, 69, 69, 69, 69, 70, ++ 70, 70, 71, 71, 71, 72, 72, 72, 72, 73, ++ 73, 73, 73, 74, 74, 74, 75, 75, 75, 76, ++ 76, 76 + }; + +-/* YYSTOS[STATE-NUM] -- The (internal number of the) accessing +- symbol of state STATE-NUM. */ +-static const yytype_uint8 yystos[] = ++ /* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN. */ ++static const yytype_uint8 yyr2[] = + { +- 0, 3, 49, 25, 0, 4, 22, 50, 51, 17, +- 18, 33, 59, 51, 26, 52, 50, 43, 46, 47, +- 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, +- 69, 70, 71, 72, 59, 27, 53, 15, 23, 26, +- 72, 72, 72, 35, 12, 37, 11, 39, 40, 41, +- 9, 10, 7, 8, 30, 36, 5, 6, 42, 43, +- 26, 44, 45, 25, 54, 23, 53, 53, 63, 60, +- 64, 65, 66, 67, 68, 68, 69, 69, 69, 69, +- 70, 70, 71, 71, 72, 72, 72, 14, 15, 16, +- 22, 55, 74, 75, 25, 38, 16, 16, 25, 29, +- 53, 55, 75, 28, 55, 74, 61, 25, 25, 56, +- 57, 25, 22, 25, 34, 13, 21, 22, 23, 24, +- 31, 36, 58, 17, 33, 73, 22, 23, 30, 59, +- 36, 21, 20, 22, 32, 34, 35, 59, 34, 59, +- 35 ++ 0, 2, 5, 0, 2, 0, 2, 4, 2, 2, ++ 3, 3, 4, 5, 0, 2, 4, 2, 3, 2, ++ 2, 3, 4, 2, 9, 5, 2, 0, 2, 2, ++ 3, 1, 2, 2, 2, 1, 1, 3, 1, 1, ++ 5, 1, 3, 1, 3, 1, 3, 1, 3, 1, ++ 3, 1, 3, 3, 1, 3, 3, 3, 3, 3, ++ 3, 1, 3, 3, 1, 3, 3, 3, 1, 1, ++ 2, 2, 2, 0, 2, 2, 0, 2, 2, 2, ++ 3, 2 + }; + +-#define yyerrok (yyerrstatus = 0) +-#define yyclearin (yychar = YYEMPTY) +-#define YYEMPTY (-2) +-#define YYEOF 0 +- +-#define YYACCEPT goto yyacceptlab +-#define YYABORT goto yyabortlab +-#define YYERROR goto yyerrorlab +- +- +-/* Like YYERROR except do call yyerror. This remains here temporarily +- to ease the transition to the new meaning of YYERROR, for GCC. +- Once GCC version 2 has supplanted version 1, this can go. However, +- YYFAIL appears to be in use. Nevertheless, it is formally deprecated +- in Bison 2.4.2's NEWS entry, where a plan to phase it out is +- discussed. */ +- +-#define YYFAIL goto yyerrlab +-#if defined YYFAIL +- /* This is here to suppress warnings from the GCC cpp's +- -Wunused-macros. Normally we don't worry about that warning, but +- some users do, and we want to make it easy for users to remove +- YYFAIL uses, which will produce warnings from Bison 2.5. */ +-#endif ++ ++#define yyerrok (yyerrstatus = 0) ++#define yyclearin (yychar = YYEMPTY) ++#define YYEMPTY (-2) ++#define YYEOF 0 ++ ++#define YYACCEPT goto yyacceptlab ++#define YYABORT goto yyabortlab ++#define YYERROR goto yyerrorlab ++ + + #define YYRECOVERING() (!!yyerrstatus) + +@@ -768,27 +725,41 @@ + else \ + { \ + yyerror (YY_("syntax error: cannot back up")); \ +- YYERROR; \ +- } \ +-while (YYID (0)) ++ YYERROR; \ ++ } \ ++while (0) + + /* Error token number */ +-#define YYTERROR 1 +-#define YYERRCODE 256 ++#define YYTERROR 1 ++#define YYERRCODE 256 + + +-/* This macro is provided for backward compatibility. */ +-#ifndef YY_LOCATION_PRINT +-# define YY_LOCATION_PRINT(File, Loc) ((void) 0) ++/* YYLLOC_DEFAULT -- Set CURRENT to span from RHS[1] to RHS[N]. ++ If N is 0, then set CURRENT to the empty location which ends ++ the previous symbol: RHS[0] (always defined). */ ++ ++#ifndef YYLLOC_DEFAULT ++# define YYLLOC_DEFAULT(Current, Rhs, N) \ ++ do \ ++ if (N) \ ++ { \ ++ (Current).first_line = YYRHSLOC (Rhs, 1).first_line; \ ++ (Current).first_column = YYRHSLOC (Rhs, 1).first_column; \ ++ (Current).last_line = YYRHSLOC (Rhs, N).last_line; \ ++ (Current).last_column = YYRHSLOC (Rhs, N).last_column; \ ++ } \ ++ else \ ++ { \ ++ (Current).first_line = (Current).last_line = \ ++ YYRHSLOC (Rhs, 0).last_line; \ ++ (Current).first_column = (Current).last_column = \ ++ YYRHSLOC (Rhs, 0).last_column; \ ++ } \ ++ while (0) + #endif + ++#define YYRHSLOC(Rhs, K) ((Rhs)[K]) + +-/* YYLEX -- calling `yylex' with the right arguments. */ +-#ifdef YYLEX_PARAM +-# define YYLEX yylex (YYLEX_PARAM) +-#else +-# define YYLEX yylex () +-#endif + + /* Enable debugging if requested. */ + #if YYDEBUG +@@ -798,50 +769,84 @@ + # define YYFPRINTF fprintf + # endif + +-# define YYDPRINTF(Args) \ +-do { \ +- if (yydebug) \ +- YYFPRINTF Args; \ +-} while (YYID (0)) +- +-# define YY_SYMBOL_PRINT(Title, Type, Value, Location) \ +-do { \ +- if (yydebug) \ +- { \ +- YYFPRINTF (stderr, "%s ", Title); \ +- yy_symbol_print (stderr, \ +- Type, Value); \ +- YYFPRINTF (stderr, "\n"); \ +- } \ +-} while (YYID (0)) ++# define YYDPRINTF(Args) \ ++do { \ ++ if (yydebug) \ ++ YYFPRINTF Args; \ ++} while (0) + + +-/*--------------------------------. +-| Print this symbol on YYOUTPUT. | +-`--------------------------------*/ ++/* YY_LOCATION_PRINT -- Print the location on the stream. ++ This macro was not mandated originally: define only if we know ++ we won't break user code: when these are the locations we know. */ + +-/*ARGSUSED*/ +-#if (defined __STDC__ || defined __C99__FUNC__ \ +- || defined __cplusplus || defined _MSC_VER) +-static void +-yy_symbol_value_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep) +-#else +-static void +-yy_symbol_value_print (yyoutput, yytype, yyvaluep) +- FILE *yyoutput; +- int yytype; +- YYSTYPE const * const yyvaluep; ++#ifndef YY_LOCATION_PRINT ++# if defined YYLTYPE_IS_TRIVIAL && YYLTYPE_IS_TRIVIAL ++ ++/* Print *YYLOCP on YYO. Private, do not rely on its existence. */ ++ ++YY_ATTRIBUTE_UNUSED ++static unsigned ++yy_location_print_ (FILE *yyo, YYLTYPE const * const yylocp) ++{ ++ unsigned res = 0; ++ int end_col = 0 != yylocp->last_column ? yylocp->last_column - 1 : 0; ++ if (0 <= yylocp->first_line) ++ { ++ res += YYFPRINTF (yyo, "%d", yylocp->first_line); ++ if (0 <= yylocp->first_column) ++ res += YYFPRINTF (yyo, ".%d", yylocp->first_column); ++ } ++ if (0 <= yylocp->last_line) ++ { ++ if (yylocp->first_line < yylocp->last_line) ++ { ++ res += YYFPRINTF (yyo, "-%d", yylocp->last_line); ++ if (0 <= end_col) ++ res += YYFPRINTF (yyo, ".%d", end_col); ++ } ++ else if (0 <= end_col && yylocp->first_column < end_col) ++ res += YYFPRINTF (yyo, "-%d", end_col); ++ } ++ return res; ++ } ++ ++# define YY_LOCATION_PRINT(File, Loc) \ ++ yy_location_print_ (File, &(Loc)) ++ ++# else ++# define YY_LOCATION_PRINT(File, Loc) ((void) 0) ++# endif + #endif ++ ++ ++# define YY_SYMBOL_PRINT(Title, Type, Value, Location) \ ++do { \ ++ if (yydebug) \ ++ { \ ++ YYFPRINTF (stderr, "%s ", Title); \ ++ yy_symbol_print (stderr, \ ++ Type, Value, Location); \ ++ YYFPRINTF (stderr, "\n"); \ ++ } \ ++} while (0) ++ ++ ++/*----------------------------------------. ++| Print this symbol's value on YYOUTPUT. | ++`----------------------------------------*/ ++ ++static void ++yy_symbol_value_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep, YYLTYPE const * const yylocationp) + { + FILE *yyo = yyoutput; + YYUSE (yyo); ++ YYUSE (yylocationp); + if (!yyvaluep) + return; + # ifdef YYPRINT + if (yytype < YYNTOKENS) + YYPRINT (yyoutput, yytoknum[yytype], *yyvaluep); +-# else +- YYUSE (yyoutput); + # endif + YYUSE (yytype); + } +@@ -851,24 +856,15 @@ + | Print this symbol on YYOUTPUT. | + `--------------------------------*/ + +-#if (defined __STDC__ || defined __C99__FUNC__ \ +- || defined __cplusplus || defined _MSC_VER) +-static void +-yy_symbol_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep) +-#else + static void +-yy_symbol_print (yyoutput, yytype, yyvaluep) +- FILE *yyoutput; +- int yytype; +- YYSTYPE const * const yyvaluep; +-#endif ++yy_symbol_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep, YYLTYPE const * const yylocationp) + { +- if (yytype < YYNTOKENS) +- YYFPRINTF (yyoutput, "token %s (", yytname[yytype]); +- else +- YYFPRINTF (yyoutput, "nterm %s (", yytname[yytype]); ++ YYFPRINTF (yyoutput, "%s %s (", ++ yytype < YYNTOKENS ? "token" : "nterm", yytname[yytype]); + +- yy_symbol_value_print (yyoutput, yytype, yyvaluep); ++ YY_LOCATION_PRINT (yyoutput, *yylocationp); ++ YYFPRINTF (yyoutput, ": "); ++ yy_symbol_value_print (yyoutput, yytype, yyvaluep, yylocationp); + YYFPRINTF (yyoutput, ")"); + } + +@@ -877,16 +873,8 @@ + | TOP (included). | + `------------------------------------------------------------------*/ + +-#if (defined __STDC__ || defined __C99__FUNC__ \ +- || defined __cplusplus || defined _MSC_VER) + static void + yy_stack_print (yytype_int16 *yybottom, yytype_int16 *yytop) +-#else +-static void +-yy_stack_print (yybottom, yytop) +- yytype_int16 *yybottom; +- yytype_int16 *yytop; +-#endif + { + YYFPRINTF (stderr, "Stack now"); + for (; yybottom <= yytop; yybottom++) +@@ -897,49 +885,42 @@ + YYFPRINTF (stderr, "\n"); + } + +-# define YY_STACK_PRINT(Bottom, Top) \ +-do { \ +- if (yydebug) \ +- yy_stack_print ((Bottom), (Top)); \ +-} while (YYID (0)) ++# define YY_STACK_PRINT(Bottom, Top) \ ++do { \ ++ if (yydebug) \ ++ yy_stack_print ((Bottom), (Top)); \ ++} while (0) + + + /*------------------------------------------------. + | Report that the YYRULE is going to be reduced. | + `------------------------------------------------*/ + +-#if (defined __STDC__ || defined __C99__FUNC__ \ +- || defined __cplusplus || defined _MSC_VER) +-static void +-yy_reduce_print (YYSTYPE *yyvsp, int yyrule) +-#else + static void +-yy_reduce_print (yyvsp, yyrule) +- YYSTYPE *yyvsp; +- int yyrule; +-#endif ++yy_reduce_print (yytype_int16 *yyssp, YYSTYPE *yyvsp, YYLTYPE *yylsp, int yyrule) + { ++ unsigned long int yylno = yyrline[yyrule]; + int yynrhs = yyr2[yyrule]; + int yyi; +- unsigned long int yylno = yyrline[yyrule]; + YYFPRINTF (stderr, "Reducing stack by rule %d (line %lu):\n", +- yyrule - 1, yylno); ++ yyrule - 1, yylno); + /* The symbols being reduced. */ + for (yyi = 0; yyi < yynrhs; yyi++) + { + YYFPRINTF (stderr, " $%d = ", yyi + 1); +- yy_symbol_print (stderr, yyrhs[yyprhs[yyrule] + yyi], +- &(yyvsp[(yyi + 1) - (yynrhs)]) +- ); ++ yy_symbol_print (stderr, ++ yystos[yyssp[yyi + 1 - yynrhs]], ++ &(yyvsp[(yyi + 1) - (yynrhs)]) ++ , &(yylsp[(yyi + 1) - (yynrhs)]) ); + YYFPRINTF (stderr, "\n"); + } + } + +-# define YY_REDUCE_PRINT(Rule) \ +-do { \ +- if (yydebug) \ +- yy_reduce_print (yyvsp, Rule); \ +-} while (YYID (0)) ++# define YY_REDUCE_PRINT(Rule) \ ++do { \ ++ if (yydebug) \ ++ yy_reduce_print (yyssp, yyvsp, yylsp, Rule); \ ++} while (0) + + /* Nonzero means print parse trace. It is left uninitialized so that + multiple parsers can coexist. */ +@@ -953,7 +934,7 @@ + + + /* YYINITDEPTH -- initial size of the parser's stacks. */ +-#ifndef YYINITDEPTH ++#ifndef YYINITDEPTH + # define YYINITDEPTH 200 + #endif + +@@ -976,15 +957,8 @@ + # define yystrlen strlen + # else + /* Return the length of YYSTR. */ +-#if (defined __STDC__ || defined __C99__FUNC__ \ +- || defined __cplusplus || defined _MSC_VER) + static YYSIZE_T + yystrlen (const char *yystr) +-#else +-static YYSIZE_T +-yystrlen (yystr) +- const char *yystr; +-#endif + { + YYSIZE_T yylen; + for (yylen = 0; yystr[yylen]; yylen++) +@@ -1000,16 +974,8 @@ + # else + /* Copy YYSRC to YYDEST, returning the address of the terminating '\0' in + YYDEST. */ +-#if (defined __STDC__ || defined __C99__FUNC__ \ +- || defined __cplusplus || defined _MSC_VER) + static char * + yystpcpy (char *yydest, const char *yysrc) +-#else +-static char * +-yystpcpy (yydest, yysrc) +- char *yydest; +- const char *yysrc; +-#endif + { + char *yyd = yydest; + const char *yys = yysrc; +@@ -1039,27 +1005,27 @@ + char const *yyp = yystr; + + for (;;) +- switch (*++yyp) +- { +- case '\'': +- case ',': +- goto do_not_strip_quotes; +- +- case '\\': +- if (*++yyp != '\\') +- goto do_not_strip_quotes; +- /* Fall through. */ +- default: +- if (yyres) +- yyres[yyn] = *yyp; +- yyn++; +- break; +- +- case '"': +- if (yyres) +- yyres[yyn] = '\0'; +- return yyn; +- } ++ switch (*++yyp) ++ { ++ case '\'': ++ case ',': ++ goto do_not_strip_quotes; ++ ++ case '\\': ++ if (*++yyp != '\\') ++ goto do_not_strip_quotes; ++ /* Fall through. */ ++ default: ++ if (yyres) ++ yyres[yyn] = *yyp; ++ yyn++; ++ break; ++ ++ case '"': ++ if (yyres) ++ yyres[yyn] = '\0'; ++ return yyn; ++ } + do_not_strip_quotes: ; + } + +@@ -1082,11 +1048,11 @@ + yysyntax_error (YYSIZE_T *yymsg_alloc, char **yymsg, + yytype_int16 *yyssp, int yytoken) + { +- YYSIZE_T yysize0 = yytnamerr (YY_NULL, yytname[yytoken]); ++ YYSIZE_T yysize0 = yytnamerr (YY_NULLPTR, yytname[yytoken]); + YYSIZE_T yysize = yysize0; + enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 }; + /* Internationalized format string. */ +- const char *yyformat = YY_NULL; ++ const char *yyformat = YY_NULLPTR; + /* Arguments of yyformat. */ + char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM]; + /* Number of reported tokens (one for the "unexpected", one per +@@ -1094,10 +1060,6 @@ + int yycount = 0; + + /* There are many possibilities here to consider: +- - Assume YYFAIL is not used. It's too flawed to consider. See +- +- for details. YYERROR is fine as it does not invoke this +- function. + - If this state is a consistent state with a default action, then + the only way this function was invoked is if the default action + is an error action. In that case, don't check for expected +@@ -1147,7 +1109,7 @@ + } + yyarg[yycount++] = yytname[yyx]; + { +- YYSIZE_T yysize1 = yysize + yytnamerr (YY_NULL, yytname[yyx]); ++ YYSIZE_T yysize1 = yysize + yytnamerr (YY_NULLPTR, yytname[yyx]); + if (! (yysize <= yysize1 + && yysize1 <= YYSTACK_ALLOC_MAXIMUM)) + return 2; +@@ -1214,26 +1176,18 @@ + | Release the memory associated to this symbol. | + `-----------------------------------------------*/ + +-/*ARGSUSED*/ +-#if (defined __STDC__ || defined __C99__FUNC__ \ +- || defined __cplusplus || defined _MSC_VER) +-static void +-yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep) +-#else + static void +-yydestruct (yymsg, yytype, yyvaluep) +- const char *yymsg; +- int yytype; +- YYSTYPE *yyvaluep; +-#endif ++yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep, YYLTYPE *yylocationp) + { + YYUSE (yyvaluep); +- ++ YYUSE (yylocationp); + if (!yymsg) + yymsg = "Deleting"; + YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp); + ++ YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN + YYUSE (yytype); ++ YY_IGNORE_MAYBE_UNINITIALIZED_END + } + + +@@ -1242,18 +1196,14 @@ + /* The lookahead symbol. */ + int yychar; + +- +-#ifndef YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN +-# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN +-# define YY_IGNORE_MAYBE_UNINITIALIZED_END +-#endif +-#ifndef YY_INITIAL_VALUE +-# define YY_INITIAL_VALUE(Value) /* Nothing. */ +-#endif +- + /* The semantic value of the lookahead symbol. */ +-YYSTYPE yylval YY_INITIAL_VALUE(yyval_default); +- ++YYSTYPE yylval; ++/* Location data for the lookahead symbol. */ ++YYLTYPE yylloc ++# if defined YYLTYPE_IS_TRIVIAL && YYLTYPE_IS_TRIVIAL ++ = { 1, 1, 1, 1 } ++# endif ++; + /* Number of syntax errors so far. */ + int yynerrs; + +@@ -1262,35 +1212,17 @@ + | yyparse. | + `----------*/ + +-#ifdef YYPARSE_PARAM +-#if (defined __STDC__ || defined __C99__FUNC__ \ +- || defined __cplusplus || defined _MSC_VER) +-int +-yyparse (void *YYPARSE_PARAM) +-#else +-int +-yyparse (YYPARSE_PARAM) +- void *YYPARSE_PARAM; +-#endif +-#else /* ! YYPARSE_PARAM */ +-#if (defined __STDC__ || defined __C99__FUNC__ \ +- || defined __cplusplus || defined _MSC_VER) + int + yyparse (void) +-#else +-int +-yyparse () +- +-#endif +-#endif + { + int yystate; + /* Number of tokens to shift before error messages enabled. */ + int yyerrstatus; + + /* The stacks and their tools: +- `yyss': related to states. +- `yyvs': related to semantic values. ++ 'yyss': related to states. ++ 'yyvs': related to semantic values. ++ 'yyls': related to locations. + + Refer to the stacks through separate pointers, to allow yyoverflow + to reallocate them elsewhere. */ +@@ -1305,6 +1237,14 @@ + YYSTYPE *yyvs; + YYSTYPE *yyvsp; + ++ /* The location stack. */ ++ YYLTYPE yylsa[YYINITDEPTH]; ++ YYLTYPE *yyls; ++ YYLTYPE *yylsp; ++ ++ /* The locations where the error started and ended. */ ++ YYLTYPE yyerror_range[3]; ++ + YYSIZE_T yystacksize; + + int yyn; +@@ -1314,6 +1254,7 @@ + /* The variables used to return semantic value and location from the + action routines. */ + YYSTYPE yyval; ++ YYLTYPE yyloc; + + #if YYERROR_VERBOSE + /* Buffer for error messages, and its allocated size. */ +@@ -1322,7 +1263,7 @@ + YYSIZE_T yymsg_alloc = sizeof yymsgbuf; + #endif + +-#define YYPOPSTACK(N) (yyvsp -= (N), yyssp -= (N)) ++#define YYPOPSTACK(N) (yyvsp -= (N), yyssp -= (N), yylsp -= (N)) + + /* The number of symbols on the RHS of the reduced rule. + Keep to zero when no symbol should be popped. */ +@@ -1330,6 +1271,7 @@ + + yyssp = yyss = yyssa; + yyvsp = yyvs = yyvsa; ++ yylsp = yyls = yylsa; + yystacksize = YYINITDEPTH; + + YYDPRINTF ((stderr, "Starting parse\n")); +@@ -1338,6 +1280,7 @@ + yyerrstatus = 0; + yynerrs = 0; + yychar = YYEMPTY; /* Cause a token to be read. */ ++ yylsp[0] = yylloc; + goto yysetstate; + + /*------------------------------------------------------------. +@@ -1358,23 +1301,26 @@ + + #ifdef yyoverflow + { +- /* Give user a chance to reallocate the stack. Use copies of +- these so that the &'s don't force the real ones into +- memory. */ +- YYSTYPE *yyvs1 = yyvs; +- yytype_int16 *yyss1 = yyss; +- +- /* Each stack pointer address is followed by the size of the +- data in use in that stack, in bytes. This used to be a +- conditional around just the two extra args, but that might +- be undefined if yyoverflow is a macro. */ +- yyoverflow (YY_("memory exhausted"), +- &yyss1, yysize * sizeof (*yyssp), +- &yyvs1, yysize * sizeof (*yyvsp), +- &yystacksize); +- +- yyss = yyss1; +- yyvs = yyvs1; ++ /* Give user a chance to reallocate the stack. Use copies of ++ these so that the &'s don't force the real ones into ++ memory. */ ++ YYSTYPE *yyvs1 = yyvs; ++ yytype_int16 *yyss1 = yyss; ++ YYLTYPE *yyls1 = yyls; ++ ++ /* Each stack pointer address is followed by the size of the ++ data in use in that stack, in bytes. This used to be a ++ conditional around just the two extra args, but that might ++ be undefined if yyoverflow is a macro. */ ++ yyoverflow (YY_("memory exhausted"), ++ &yyss1, yysize * sizeof (*yyssp), ++ &yyvs1, yysize * sizeof (*yyvsp), ++ &yyls1, yysize * sizeof (*yylsp), ++ &yystacksize); ++ ++ yyls = yyls1; ++ yyss = yyss1; ++ yyvs = yyvs1; + } + #else /* no yyoverflow */ + # ifndef YYSTACK_RELOCATE +@@ -1382,34 +1328,36 @@ + # else + /* Extend the stack our own way. */ + if (YYMAXDEPTH <= yystacksize) +- goto yyexhaustedlab; ++ goto yyexhaustedlab; + yystacksize *= 2; + if (YYMAXDEPTH < yystacksize) +- yystacksize = YYMAXDEPTH; ++ yystacksize = YYMAXDEPTH; + + { +- yytype_int16 *yyss1 = yyss; +- union yyalloc *yyptr = +- (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize)); +- if (! yyptr) +- goto yyexhaustedlab; +- YYSTACK_RELOCATE (yyss_alloc, yyss); +- YYSTACK_RELOCATE (yyvs_alloc, yyvs); ++ yytype_int16 *yyss1 = yyss; ++ union yyalloc *yyptr = ++ (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize)); ++ if (! yyptr) ++ goto yyexhaustedlab; ++ YYSTACK_RELOCATE (yyss_alloc, yyss); ++ YYSTACK_RELOCATE (yyvs_alloc, yyvs); ++ YYSTACK_RELOCATE (yyls_alloc, yyls); + # undef YYSTACK_RELOCATE +- if (yyss1 != yyssa) +- YYSTACK_FREE (yyss1); ++ if (yyss1 != yyssa) ++ YYSTACK_FREE (yyss1); + } + # endif + #endif /* no yyoverflow */ + + yyssp = yyss + yysize - 1; + yyvsp = yyvs + yysize - 1; ++ yylsp = yyls + yysize - 1; + + YYDPRINTF ((stderr, "Stack size increased to %lu\n", +- (unsigned long int) yystacksize)); ++ (unsigned long int) yystacksize)); + + if (yyss + yystacksize - 1 <= yyssp) +- YYABORT; ++ YYABORT; + } + + YYDPRINTF ((stderr, "Entering state %d\n", yystate)); +@@ -1438,7 +1386,7 @@ + if (yychar == YYEMPTY) + { + YYDPRINTF ((stderr, "Reading a token: ")); +- yychar = YYLEX; ++ yychar = yylex (); + } + + if (yychar <= YYEOF) +@@ -1481,7 +1429,7 @@ + YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN + *++yyvsp = yylval; + YY_IGNORE_MAYBE_UNINITIALIZED_END +- ++ *++yylsp = yylloc; + goto yynewstate; + + +@@ -1503,7 +1451,7 @@ + yylen = yyr2[yyn]; + + /* If YYLEN is nonzero, implement the default value of the action: +- `$$ = $1'. ++ '$$ = $1'. + + Otherwise, the following line sets YYVAL to garbage. + This behavior is undocumented and Bison +@@ -1512,287 +1460,306 @@ + GCC warning that YYVAL may be used uninitialized. */ + yyval = yyvsp[1-yylen]; + +- ++ /* Default location. */ ++ YYLLOC_DEFAULT (yyloc, (yylsp - yylen), yylen); + YY_REDUCE_PRINT (yyn); + switch (yyn) + { + case 2: +-/* Line 1787 of yacc.c */ +-#line 110 "dtc-parser.y" ++#line 109 "dtc-parser.y" /* yacc.c:1646 */ + { +- the_boot_info = build_boot_info((yyvsp[(3) - (4)].re), (yyvsp[(4) - (4)].node), +- guess_boot_cpuid((yyvsp[(4) - (4)].node))); ++ (yyvsp[0].node)->is_plugin = (yyvsp[-2].is_plugin); ++ (yyvsp[0].node)->is_root = 1; ++ the_boot_info = build_boot_info((yyvsp[-1].re), (yyvsp[0].node), ++ guess_boot_cpuid((yyvsp[0].node))); + } ++#line 1477 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 3: +-/* Line 1787 of yacc.c */ +-#line 118 "dtc-parser.y" ++#line 119 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.re) = NULL; ++ (yyval.is_plugin) = 0; + } ++#line 1485 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 4: +-/* Line 1787 of yacc.c */ +-#line 122 "dtc-parser.y" ++#line 123 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.re) = chain_reserve_entry((yyvsp[(1) - (2)].re), (yyvsp[(2) - (2)].re)); ++ (yyval.is_plugin) = 1; + } ++#line 1493 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 5: +-/* Line 1787 of yacc.c */ +-#line 129 "dtc-parser.y" ++#line 130 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.re) = build_reserve_entry((yyvsp[(2) - (4)].integer), (yyvsp[(3) - (4)].integer)); ++ (yyval.re) = NULL; + } ++#line 1501 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 6: +-/* Line 1787 of yacc.c */ +-#line 133 "dtc-parser.y" ++#line 134 "dtc-parser.y" /* yacc.c:1646 */ + { +- add_label(&(yyvsp[(2) - (2)].re)->labels, (yyvsp[(1) - (2)].labelref)); +- (yyval.re) = (yyvsp[(2) - (2)].re); ++ (yyval.re) = chain_reserve_entry((yyvsp[-1].re), (yyvsp[0].re)); + } ++#line 1509 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 7: +-/* Line 1787 of yacc.c */ +-#line 141 "dtc-parser.y" ++#line 141 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.node) = name_node((yyvsp[(2) - (2)].node), ""); ++ (yyval.re) = build_reserve_entry((yyvsp[-2].integer), (yyvsp[-1].integer)); + } ++#line 1517 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 8: +-/* Line 1787 of yacc.c */ +-#line 145 "dtc-parser.y" ++#line 145 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.node) = merge_nodes((yyvsp[(1) - (3)].node), (yyvsp[(3) - (3)].node)); ++ add_label(&(yyvsp[0].re)->labels, (yyvsp[-1].labelref)); ++ (yyval.re) = (yyvsp[0].re); + } ++#line 1526 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 9: +-/* Line 1787 of yacc.c */ +-#line 149 "dtc-parser.y" ++#line 153 "dtc-parser.y" /* yacc.c:1646 */ + { +- struct node *target = get_node_by_ref((yyvsp[(1) - (3)].node), (yyvsp[(2) - (3)].labelref)); +- +- if (target) +- merge_nodes(target, (yyvsp[(3) - (3)].node)); +- else +- print_error("label or path, '%s', not found", (yyvsp[(2) - (3)].labelref)); +- (yyval.node) = (yyvsp[(1) - (3)].node); ++ (yyval.node) = name_node((yyvsp[0].node), ""); + } ++#line 1534 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 10: +-/* Line 1787 of yacc.c */ +-#line 159 "dtc-parser.y" ++#line 157 "dtc-parser.y" /* yacc.c:1646 */ + { +- struct node *target = get_node_by_ref((yyvsp[(1) - (4)].node), (yyvsp[(3) - (4)].labelref)); +- +- if (!target) +- print_error("label or path, '%s', not found", (yyvsp[(3) - (4)].labelref)); +- else +- delete_node(target); +- +- (yyval.node) = (yyvsp[(1) - (4)].node); ++ (yyval.node) = merge_nodes((yyvsp[-2].node), (yyvsp[0].node)); + } ++#line 1542 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 11: +-/* Line 1787 of yacc.c */ +-#line 173 "dtc-parser.y" ++#line 161 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.node) = build_node((yyvsp[(2) - (5)].proplist), (yyvsp[(3) - (5)].nodelist)); ++ struct node *target = get_node_by_ref((yyvsp[-2].node), (yyvsp[-1].labelref)); ++ ++ if (target) ++ merge_nodes(target, (yyvsp[0].node)); ++ else ++ ERROR(&(yylsp[-1]), "Label or path %s not found", (yyvsp[-1].labelref)); ++ (yyval.node) = (yyvsp[-2].node); + } ++#line 1556 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 12: +-/* Line 1787 of yacc.c */ +-#line 180 "dtc-parser.y" ++#line 171 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.proplist) = NULL; ++ struct node *target = get_node_by_ref((yyvsp[-3].node), (yyvsp[-1].labelref)); ++ ++ if (target) ++ delete_node(target); ++ else ++ ERROR(&(yylsp[-1]), "Label or path %s not found", (yyvsp[-1].labelref)); ++ ++ ++ (yyval.node) = (yyvsp[-3].node); + } ++#line 1572 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 13: +-/* Line 1787 of yacc.c */ +-#line 184 "dtc-parser.y" ++#line 186 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.proplist) = chain_property((yyvsp[(2) - (2)].prop), (yyvsp[(1) - (2)].proplist)); ++ (yyval.node) = build_node((yyvsp[-3].proplist), (yyvsp[-2].nodelist)); + } ++#line 1580 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 14: +-/* Line 1787 of yacc.c */ +-#line 191 "dtc-parser.y" ++#line 193 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.prop) = build_property((yyvsp[(1) - (4)].propnodename), (yyvsp[(3) - (4)].data)); ++ (yyval.proplist) = NULL; + } ++#line 1588 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 15: +-/* Line 1787 of yacc.c */ +-#line 195 "dtc-parser.y" ++#line 197 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.prop) = build_property((yyvsp[(1) - (2)].propnodename), empty_data); ++ (yyval.proplist) = chain_property((yyvsp[0].prop), (yyvsp[-1].proplist)); + } ++#line 1596 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 16: +-/* Line 1787 of yacc.c */ +-#line 199 "dtc-parser.y" ++#line 204 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.prop) = build_property_delete((yyvsp[(2) - (3)].propnodename)); ++ (yyval.prop) = build_property((yyvsp[-3].propnodename), (yyvsp[-1].data)); + } ++#line 1604 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 17: +-/* Line 1787 of yacc.c */ +-#line 203 "dtc-parser.y" ++#line 208 "dtc-parser.y" /* yacc.c:1646 */ + { +- add_label(&(yyvsp[(2) - (2)].prop)->labels, (yyvsp[(1) - (2)].labelref)); +- (yyval.prop) = (yyvsp[(2) - (2)].prop); ++ (yyval.prop) = build_property((yyvsp[-1].propnodename), empty_data); + } ++#line 1612 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 18: +-/* Line 1787 of yacc.c */ +-#line 211 "dtc-parser.y" ++#line 212 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.data) = data_merge((yyvsp[(1) - (2)].data), (yyvsp[(2) - (2)].data)); ++ (yyval.prop) = build_property_delete((yyvsp[-1].propnodename)); + } ++#line 1620 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 19: +-/* Line 1787 of yacc.c */ +-#line 215 "dtc-parser.y" ++#line 216 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.data) = data_merge((yyvsp[(1) - (3)].data), (yyvsp[(2) - (3)].array).data); ++ add_label(&(yyvsp[0].prop)->labels, (yyvsp[-1].labelref)); ++ (yyval.prop) = (yyvsp[0].prop); + } ++#line 1629 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 20: +-/* Line 1787 of yacc.c */ +-#line 219 "dtc-parser.y" ++#line 224 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.data) = data_merge((yyvsp[(1) - (4)].data), (yyvsp[(3) - (4)].data)); ++ (yyval.data) = data_merge((yyvsp[-1].data), (yyvsp[0].data)); + } ++#line 1637 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 21: +-/* Line 1787 of yacc.c */ +-#line 223 "dtc-parser.y" ++#line 228 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.data) = data_add_marker((yyvsp[(1) - (2)].data), REF_PATH, (yyvsp[(2) - (2)].labelref)); ++ (yyval.data) = data_merge((yyvsp[-2].data), (yyvsp[-1].array).data); + } ++#line 1645 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 22: +-/* Line 1787 of yacc.c */ +-#line 227 "dtc-parser.y" ++#line 232 "dtc-parser.y" /* yacc.c:1646 */ + { +- FILE *f = srcfile_relative_open((yyvsp[(4) - (9)].data).val, NULL); ++ (yyval.data) = data_merge((yyvsp[-3].data), (yyvsp[-1].data)); ++ } ++#line 1653 "dtc-parser.tab.c" /* yacc.c:1646 */ ++ break; ++ ++ case 23: ++#line 236 "dtc-parser.y" /* yacc.c:1646 */ ++ { ++ (yyval.data) = data_add_marker((yyvsp[-1].data), REF_PATH, (yyvsp[0].labelref)); ++ } ++#line 1661 "dtc-parser.tab.c" /* yacc.c:1646 */ ++ break; ++ ++ case 24: ++#line 240 "dtc-parser.y" /* yacc.c:1646 */ ++ { ++ FILE *f = srcfile_relative_open((yyvsp[-5].data).val, NULL); + struct data d; + +- if ((yyvsp[(6) - (9)].integer) != 0) +- if (fseek(f, (yyvsp[(6) - (9)].integer), SEEK_SET) != 0) +- print_error("Couldn't seek to offset %llu in \"%s\": %s", +- (unsigned long long)(yyvsp[(6) - (9)].integer), +- (yyvsp[(4) - (9)].data).val, +- strerror(errno)); ++ if ((yyvsp[-3].integer) != 0) ++ if (fseek(f, (yyvsp[-3].integer), SEEK_SET) != 0) ++ die("Couldn't seek to offset %llu in \"%s\": %s", ++ (unsigned long long)(yyvsp[-3].integer), (yyvsp[-5].data).val, ++ strerror(errno)); + +- d = data_copy_file(f, (yyvsp[(8) - (9)].integer)); ++ d = data_copy_file(f, (yyvsp[-1].integer)); + +- (yyval.data) = data_merge((yyvsp[(1) - (9)].data), d); ++ (yyval.data) = data_merge((yyvsp[-8].data), d); + fclose(f); + } ++#line 1681 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + +- case 23: +-/* Line 1787 of yacc.c */ +-#line 244 "dtc-parser.y" ++ case 25: ++#line 256 "dtc-parser.y" /* yacc.c:1646 */ + { +- FILE *f = srcfile_relative_open((yyvsp[(4) - (5)].data).val, NULL); ++ FILE *f = srcfile_relative_open((yyvsp[-1].data).val, NULL); + struct data d = empty_data; + + d = data_copy_file(f, -1); + +- (yyval.data) = data_merge((yyvsp[(1) - (5)].data), d); ++ (yyval.data) = data_merge((yyvsp[-4].data), d); + fclose(f); + } ++#line 1695 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + +- case 24: +-/* Line 1787 of yacc.c */ +-#line 254 "dtc-parser.y" ++ case 26: ++#line 266 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.data) = data_add_marker((yyvsp[(1) - (2)].data), LABEL, (yyvsp[(2) - (2)].labelref)); ++ (yyval.data) = data_add_marker((yyvsp[-1].data), LABEL, (yyvsp[0].labelref)); + } ++#line 1703 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + +- case 25: +-/* Line 1787 of yacc.c */ +-#line 261 "dtc-parser.y" ++ case 27: ++#line 273 "dtc-parser.y" /* yacc.c:1646 */ + { + (yyval.data) = empty_data; + } ++#line 1711 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + +- case 26: +-/* Line 1787 of yacc.c */ +-#line 265 "dtc-parser.y" ++ case 28: ++#line 277 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.data) = (yyvsp[(1) - (2)].data); ++ (yyval.data) = (yyvsp[-1].data); + } ++#line 1719 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + +- case 27: +-/* Line 1787 of yacc.c */ +-#line 269 "dtc-parser.y" ++ case 29: ++#line 281 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.data) = data_add_marker((yyvsp[(1) - (2)].data), LABEL, (yyvsp[(2) - (2)].labelref)); ++ (yyval.data) = data_add_marker((yyvsp[-1].data), LABEL, (yyvsp[0].labelref)); + } ++#line 1727 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + +- case 28: +-/* Line 1787 of yacc.c */ +-#line 276 "dtc-parser.y" ++ case 30: ++#line 288 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.array).data = empty_data; +- (yyval.array).bits = eval_literal((yyvsp[(2) - (3)].literal), 0, 7); ++ unsigned long long bits; + +- if (((yyval.array).bits != 8) && +- ((yyval.array).bits != 16) && +- ((yyval.array).bits != 32) && +- ((yyval.array).bits != 64)) +- { +- print_error("Only 8, 16, 32 and 64-bit elements" +- " are currently supported"); +- (yyval.array).bits = 32; ++ bits = (yyvsp[-1].integer); ++ ++ if ((bits != 8) && (bits != 16) && ++ (bits != 32) && (bits != 64)) { ++ ERROR(&(yylsp[-1]), "Array elements must be" ++ " 8, 16, 32 or 64-bits"); ++ bits = 32; + } ++ ++ (yyval.array).data = empty_data; ++ (yyval.array).bits = bits; + } ++#line 1747 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + +- case 29: +-/* Line 1787 of yacc.c */ +-#line 291 "dtc-parser.y" ++ case 31: ++#line 304 "dtc-parser.y" /* yacc.c:1646 */ + { + (yyval.array).data = empty_data; + (yyval.array).bits = 32; + } ++#line 1756 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + +- case 30: +-/* Line 1787 of yacc.c */ +-#line 296 "dtc-parser.y" ++ case 32: ++#line 309 "dtc-parser.y" /* yacc.c:1646 */ + { +- if ((yyvsp[(1) - (2)].array).bits < 64) { +- uint64_t mask = (1ULL << (yyvsp[(1) - (2)].array).bits) - 1; ++ if ((yyvsp[-1].array).bits < 64) { ++ uint64_t mask = (1ULL << (yyvsp[-1].array).bits) - 1; + /* + * Bits above mask must either be all zero + * (positive within range of mask) or all one +@@ -1801,275 +1768,258 @@ + * within the mask to one (i.e. | in the + * mask), all bits are one. + */ +- if (((yyvsp[(2) - (2)].integer) > mask) && (((yyvsp[(2) - (2)].integer) | mask) != -1ULL)) +- print_error( +- "integer value out of range " +- "%016lx (%d bits)", (yyvsp[(1) - (2)].array).bits); ++ if (((yyvsp[0].integer) > mask) && (((yyvsp[0].integer) | mask) != -1ULL)) ++ ERROR(&(yylsp[0]), "Value out of range for" ++ " %d-bit array element", (yyvsp[-1].array).bits); + } + +- (yyval.array).data = data_append_integer((yyvsp[(1) - (2)].array).data, (yyvsp[(2) - (2)].integer), (yyvsp[(1) - (2)].array).bits); ++ (yyval.array).data = data_append_integer((yyvsp[-1].array).data, (yyvsp[0].integer), (yyvsp[-1].array).bits); + } ++#line 1779 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + +- case 31: +-/* Line 1787 of yacc.c */ +-#line 316 "dtc-parser.y" ++ case 33: ++#line 328 "dtc-parser.y" /* yacc.c:1646 */ + { +- uint64_t val = ~0ULL >> (64 - (yyvsp[(1) - (2)].array).bits); ++ uint64_t val = ~0ULL >> (64 - (yyvsp[-1].array).bits); + +- if ((yyvsp[(1) - (2)].array).bits == 32) +- (yyvsp[(1) - (2)].array).data = data_add_marker((yyvsp[(1) - (2)].array).data, ++ if ((yyvsp[-1].array).bits == 32) ++ (yyvsp[-1].array).data = data_add_marker((yyvsp[-1].array).data, + REF_PHANDLE, +- (yyvsp[(2) - (2)].labelref)); ++ (yyvsp[0].labelref)); + else +- print_error("References are only allowed in " ++ ERROR(&(yylsp[0]), "References are only allowed in " + "arrays with 32-bit elements."); + +- (yyval.array).data = data_append_integer((yyvsp[(1) - (2)].array).data, val, (yyvsp[(1) - (2)].array).bits); +- } +- break; +- +- case 32: +-/* Line 1787 of yacc.c */ +-#line 330 "dtc-parser.y" +- { +- (yyval.array).data = data_add_marker((yyvsp[(1) - (2)].array).data, LABEL, (yyvsp[(2) - (2)].labelref)); +- } +- break; +- +- case 33: +-/* Line 1787 of yacc.c */ +-#line 337 "dtc-parser.y" +- { +- (yyval.integer) = eval_literal((yyvsp[(1) - (1)].literal), 0, 64); ++ (yyval.array).data = data_append_integer((yyvsp[-1].array).data, val, (yyvsp[-1].array).bits); + } ++#line 1797 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 34: +-/* Line 1787 of yacc.c */ +-#line 341 "dtc-parser.y" ++#line 342 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.integer) = eval_char_literal((yyvsp[(1) - (1)].literal)); ++ (yyval.array).data = data_add_marker((yyvsp[-1].array).data, LABEL, (yyvsp[0].labelref)); + } ++#line 1805 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + +- case 35: +-/* Line 1787 of yacc.c */ +-#line 345 "dtc-parser.y" ++ case 37: ++#line 351 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.integer) = (yyvsp[(2) - (3)].integer); ++ (yyval.integer) = (yyvsp[-1].integer); + } +- break; +- +- case 38: +-/* Line 1787 of yacc.c */ +-#line 356 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (5)].integer) ? (yyvsp[(3) - (5)].integer) : (yyvsp[(5) - (5)].integer); } ++#line 1813 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 40: +-/* Line 1787 of yacc.c */ +-#line 361 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) || (yyvsp[(3) - (3)].integer); } ++#line 362 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-4].integer) ? (yyvsp[-2].integer) : (yyvsp[0].integer); } ++#line 1819 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 42: +-/* Line 1787 of yacc.c */ +-#line 366 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) && (yyvsp[(3) - (3)].integer); } ++#line 367 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) || (yyvsp[0].integer); } ++#line 1825 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 44: +-/* Line 1787 of yacc.c */ +-#line 371 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) | (yyvsp[(3) - (3)].integer); } ++#line 372 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) && (yyvsp[0].integer); } ++#line 1831 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 46: +-/* Line 1787 of yacc.c */ +-#line 376 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) ^ (yyvsp[(3) - (3)].integer); } ++#line 377 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) | (yyvsp[0].integer); } ++#line 1837 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 48: +-/* Line 1787 of yacc.c */ +-#line 381 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) & (yyvsp[(3) - (3)].integer); } ++#line 382 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) ^ (yyvsp[0].integer); } ++#line 1843 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 50: +-/* Line 1787 of yacc.c */ +-#line 386 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) == (yyvsp[(3) - (3)].integer); } ++#line 387 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) & (yyvsp[0].integer); } ++#line 1849 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + +- case 51: +-/* Line 1787 of yacc.c */ +-#line 387 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) != (yyvsp[(3) - (3)].integer); } ++ case 52: ++#line 392 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) == (yyvsp[0].integer); } ++#line 1855 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 53: +-/* Line 1787 of yacc.c */ +-#line 392 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) < (yyvsp[(3) - (3)].integer); } +- break; +- +- case 54: +-/* Line 1787 of yacc.c */ +-#line 393 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) > (yyvsp[(3) - (3)].integer); } ++#line 393 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) != (yyvsp[0].integer); } ++#line 1861 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 55: +-/* Line 1787 of yacc.c */ +-#line 394 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) <= (yyvsp[(3) - (3)].integer); } ++#line 398 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) < (yyvsp[0].integer); } ++#line 1867 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 56: +-/* Line 1787 of yacc.c */ +-#line 395 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) >= (yyvsp[(3) - (3)].integer); } ++#line 399 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) > (yyvsp[0].integer); } ++#line 1873 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 57: +-/* Line 1787 of yacc.c */ +-#line 399 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) << (yyvsp[(3) - (3)].integer); } ++#line 400 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) <= (yyvsp[0].integer); } ++#line 1879 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 58: +-/* Line 1787 of yacc.c */ +-#line 400 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) >> (yyvsp[(3) - (3)].integer); } ++#line 401 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) >= (yyvsp[0].integer); } ++#line 1885 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + +- case 60: +-/* Line 1787 of yacc.c */ +-#line 405 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) + (yyvsp[(3) - (3)].integer); } ++ case 59: ++#line 405 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) << (yyvsp[0].integer); } ++#line 1891 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + +- case 61: +-/* Line 1787 of yacc.c */ +-#line 406 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) - (yyvsp[(3) - (3)].integer); } ++ case 60: ++#line 406 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) >> (yyvsp[0].integer); } ++#line 1897 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + +- case 63: +-/* Line 1787 of yacc.c */ +-#line 411 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) * (yyvsp[(3) - (3)].integer); } ++ case 62: ++#line 411 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) + (yyvsp[0].integer); } ++#line 1903 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + +- case 64: +-/* Line 1787 of yacc.c */ +-#line 412 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) / (yyvsp[(3) - (3)].integer); } ++ case 63: ++#line 412 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) - (yyvsp[0].integer); } ++#line 1909 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 65: +-/* Line 1787 of yacc.c */ +-#line 413 "dtc-parser.y" +- { (yyval.integer) = (yyvsp[(1) - (3)].integer) % (yyvsp[(3) - (3)].integer); } ++#line 417 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) * (yyvsp[0].integer); } ++#line 1915 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + +- case 68: +-/* Line 1787 of yacc.c */ +-#line 419 "dtc-parser.y" +- { (yyval.integer) = -(yyvsp[(2) - (2)].integer); } ++ case 66: ++#line 418 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) / (yyvsp[0].integer); } ++#line 1921 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + +- case 69: +-/* Line 1787 of yacc.c */ +-#line 420 "dtc-parser.y" +- { (yyval.integer) = ~(yyvsp[(2) - (2)].integer); } ++ case 67: ++#line 419 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = (yyvsp[-2].integer) % (yyvsp[0].integer); } ++#line 1927 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 70: +-/* Line 1787 of yacc.c */ +-#line 421 "dtc-parser.y" +- { (yyval.integer) = !(yyvsp[(2) - (2)].integer); } ++#line 425 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = -(yyvsp[0].integer); } ++#line 1933 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 71: +-/* Line 1787 of yacc.c */ +-#line 426 "dtc-parser.y" +- { +- (yyval.data) = empty_data; +- } ++#line 426 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = ~(yyvsp[0].integer); } ++#line 1939 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 72: +-/* Line 1787 of yacc.c */ +-#line 430 "dtc-parser.y" +- { +- (yyval.data) = data_append_byte((yyvsp[(1) - (2)].data), (yyvsp[(2) - (2)].byte)); +- } ++#line 427 "dtc-parser.y" /* yacc.c:1646 */ ++ { (yyval.integer) = !(yyvsp[0].integer); } ++#line 1945 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 73: +-/* Line 1787 of yacc.c */ +-#line 434 "dtc-parser.y" ++#line 432 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.data) = data_add_marker((yyvsp[(1) - (2)].data), LABEL, (yyvsp[(2) - (2)].labelref)); ++ (yyval.data) = empty_data; + } ++#line 1953 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 74: +-/* Line 1787 of yacc.c */ +-#line 441 "dtc-parser.y" ++#line 436 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.nodelist) = NULL; ++ (yyval.data) = data_append_byte((yyvsp[-1].data), (yyvsp[0].byte)); + } ++#line 1961 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 75: +-/* Line 1787 of yacc.c */ +-#line 445 "dtc-parser.y" ++#line 440 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.nodelist) = chain_node((yyvsp[(1) - (2)].node), (yyvsp[(2) - (2)].nodelist)); ++ (yyval.data) = data_add_marker((yyvsp[-1].data), LABEL, (yyvsp[0].labelref)); + } ++#line 1969 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 76: +-/* Line 1787 of yacc.c */ +-#line 449 "dtc-parser.y" ++#line 447 "dtc-parser.y" /* yacc.c:1646 */ + { +- print_error("syntax error: properties must precede subnodes"); +- YYERROR; ++ (yyval.nodelist) = NULL; + } ++#line 1977 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 77: +-/* Line 1787 of yacc.c */ +-#line 457 "dtc-parser.y" ++#line 451 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.node) = name_node((yyvsp[(2) - (2)].node), (yyvsp[(1) - (2)].propnodename)); ++ (yyval.nodelist) = chain_node((yyvsp[-1].node), (yyvsp[0].nodelist)); + } ++#line 1985 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 78: +-/* Line 1787 of yacc.c */ +-#line 461 "dtc-parser.y" ++#line 455 "dtc-parser.y" /* yacc.c:1646 */ + { +- (yyval.node) = name_node(build_node_delete(), (yyvsp[(2) - (3)].propnodename)); ++ ERROR(&(yylsp[0]), "Properties must precede subnodes"); ++ YYERROR; + } ++#line 1994 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + + case 79: +-/* Line 1787 of yacc.c */ +-#line 465 "dtc-parser.y" ++#line 463 "dtc-parser.y" /* yacc.c:1646 */ + { +- add_label(&(yyvsp[(2) - (2)].node)->labels, (yyvsp[(1) - (2)].labelref)); +- (yyval.node) = (yyvsp[(2) - (2)].node); ++ (yyval.node) = name_node((yyvsp[0].node), (yyvsp[-1].propnodename)); + } ++#line 2002 "dtc-parser.tab.c" /* yacc.c:1646 */ + break; + ++ case 80: ++#line 467 "dtc-parser.y" /* yacc.c:1646 */ ++ { ++ (yyval.node) = name_node(build_node_delete(), (yyvsp[-1].propnodename)); ++ } ++#line 2010 "dtc-parser.tab.c" /* yacc.c:1646 */ ++ break; ++ ++ case 81: ++#line 471 "dtc-parser.y" /* yacc.c:1646 */ ++ { ++ add_label(&(yyvsp[0].node)->labels, (yyvsp[-1].labelref)); ++ (yyval.node) = (yyvsp[0].node); ++ } ++#line 2019 "dtc-parser.tab.c" /* yacc.c:1646 */ ++ break; + +-/* Line 1787 of yacc.c */ +-#line 2073 "dtc-parser.tab.c" ++ ++#line 2023 "dtc-parser.tab.c" /* yacc.c:1646 */ + default: break; + } + /* User semantic actions sometimes alter yychar, and that requires +@@ -2090,8 +2040,9 @@ + YY_STACK_PRINT (yyss, yyssp); + + *++yyvsp = yyval; ++ *++yylsp = yyloc; + +- /* Now `shift' the result of the reduction. Determine what state ++ /* Now 'shift' the result of the reduction. Determine what state + that goes to, based on the state we popped back to and the rule + number reduced by. */ + +@@ -2106,9 +2057,9 @@ + goto yynewstate; + + +-/*------------------------------------. +-| yyerrlab -- here on detecting error | +-`------------------------------------*/ ++/*--------------------------------------. ++| yyerrlab -- here on detecting error. | ++`--------------------------------------*/ + yyerrlab: + /* Make sure we have latest lookahead translation. See comments at + user semantic actions for why this is necessary. */ +@@ -2154,25 +2105,25 @@ + #endif + } + +- ++ yyerror_range[1] = yylloc; + + if (yyerrstatus == 3) + { + /* If just tried and failed to reuse lookahead token after an +- error, discard it. */ ++ error, discard it. */ + + if (yychar <= YYEOF) +- { +- /* Return failure if at end of input. */ +- if (yychar == YYEOF) +- YYABORT; +- } ++ { ++ /* Return failure if at end of input. */ ++ if (yychar == YYEOF) ++ YYABORT; ++ } + else +- { +- yydestruct ("Error: discarding", +- yytoken, &yylval); +- yychar = YYEMPTY; +- } ++ { ++ yydestruct ("Error: discarding", ++ yytoken, &yylval, &yylloc); ++ yychar = YYEMPTY; ++ } + } + + /* Else will try to reuse lookahead token after shifting the error +@@ -2191,7 +2142,8 @@ + if (/*CONSTCOND*/ 0) + goto yyerrorlab; + +- /* Do not reclaim the symbols of the rule which action triggered ++ yyerror_range[1] = yylsp[1-yylen]; ++ /* Do not reclaim the symbols of the rule whose action triggered + this YYERROR. */ + YYPOPSTACK (yylen); + yylen = 0; +@@ -2204,29 +2156,29 @@ + | yyerrlab1 -- common code for both syntax error and YYERROR. | + `-------------------------------------------------------------*/ + yyerrlab1: +- yyerrstatus = 3; /* Each real token shifted decrements this. */ ++ yyerrstatus = 3; /* Each real token shifted decrements this. */ + + for (;;) + { + yyn = yypact[yystate]; + if (!yypact_value_is_default (yyn)) +- { +- yyn += YYTERROR; +- if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR) +- { +- yyn = yytable[yyn]; +- if (0 < yyn) +- break; +- } +- } ++ { ++ yyn += YYTERROR; ++ if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR) ++ { ++ yyn = yytable[yyn]; ++ if (0 < yyn) ++ break; ++ } ++ } + + /* Pop the current state because it cannot handle the error token. */ + if (yyssp == yyss) +- YYABORT; +- ++ YYABORT; + ++ yyerror_range[1] = *yylsp; + yydestruct ("Error: popping", +- yystos[yystate], yyvsp); ++ yystos[yystate], yyvsp, yylsp); + YYPOPSTACK (1); + yystate = *yyssp; + YY_STACK_PRINT (yyss, yyssp); +@@ -2236,6 +2188,11 @@ + *++yyvsp = yylval; + YY_IGNORE_MAYBE_UNINITIALIZED_END + ++ yyerror_range[2] = yylloc; ++ /* Using YYLLOC is tempting, but would change the location of ++ the lookahead. YYLOC is available though. */ ++ YYLLOC_DEFAULT (yyloc, yyerror_range, 2); ++ *++yylsp = yyloc; + + /* Shift the error token. */ + YY_SYMBOL_PRINT ("Shifting", yystos[yyn], yyvsp, yylsp); +@@ -2275,16 +2232,16 @@ + user semantic actions for why this is necessary. */ + yytoken = YYTRANSLATE (yychar); + yydestruct ("Cleanup: discarding lookahead", +- yytoken, &yylval); ++ yytoken, &yylval, &yylloc); + } +- /* Do not reclaim the symbols of the rule which action triggered ++ /* Do not reclaim the symbols of the rule whose action triggered + this YYABORT or YYACCEPT. */ + YYPOPSTACK (yylen); + YY_STACK_PRINT (yyss, yyssp); + while (yyssp != yyss) + { + yydestruct ("Cleanup: popping", +- yystos[*yyssp], yyvsp); ++ yystos[*yyssp], yyvsp, yylsp); + YYPOPSTACK (1); + } + #ifndef yyoverflow +@@ -2295,72 +2252,12 @@ + if (yymsg != yymsgbuf) + YYSTACK_FREE (yymsg); + #endif +- /* Make sure YYID is used. */ +- return YYID (yyresult); ++ return yyresult; + } ++#line 477 "dtc-parser.y" /* yacc.c:1906 */ + + +-/* Line 2050 of yacc.c */ +-#line 471 "dtc-parser.y" +- +- +-void print_error(char const *fmt, ...) ++void yyerror(char const *s) + { +- va_list va; +- +- va_start(va, fmt); +- srcpos_verror(&yylloc, fmt, va); +- va_end(va); +- +- treesource_error = 1; +-} +- +-void yyerror(char const *s) { +- print_error("%s", s); +-} +- +-static unsigned long long eval_literal(const char *s, int base, int bits) +-{ +- unsigned long long val; +- char *e; +- +- errno = 0; +- val = strtoull(s, &e, base); +- if (*e) { +- size_t uls = strspn(e, "UL"); +- if (e[uls]) +- print_error("bad characters in literal"); +- } +- if ((errno == ERANGE) +- || ((bits < 64) && (val >= (1ULL << bits)))) +- print_error("literal out of range"); +- else if (errno != 0) +- print_error("bad literal"); +- return val; +-} +- +-static unsigned char eval_char_literal(const char *s) +-{ +- int i = 1; +- char c = s[0]; +- +- if (c == '\0') +- { +- print_error("empty character literal"); +- return 0; +- } +- +- /* +- * If the first character in the character literal is a \ then process +- * the remaining characters as an escape encoding. If the first +- * character is neither an escape or a terminator it should be the only +- * character in the literal and will be returned. +- */ +- if (c == '\\') +- c = get_escape_char(s, &i); +- +- if (s[i] != '\0') +- print_error("malformed character literal"); +- +- return c; ++ ERROR(&yylloc, "%s", s); + } +diff -Nur linux-4.1.13.orig/scripts/dtc/dtc-parser.tab.h_shipped linux-rpi/scripts/dtc/dtc-parser.tab.h_shipped +--- linux-4.1.13.orig/scripts/dtc/dtc-parser.tab.h_shipped 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/scripts/dtc/dtc-parser.tab.h_shipped 2015-11-29 09:42:41.406999830 +0100 +@@ -1,19 +1,19 @@ +-/* A Bison parser, made by GNU Bison 2.7.12-4996. */ ++/* A Bison parser, made by GNU Bison 3.0.2. */ + + /* Bison interface for Yacc-like parsers in C +- +- Copyright (C) 1984, 1989-1990, 2000-2013 Free Software Foundation, Inc. +- ++ ++ Copyright (C) 1984, 1989-1990, 2000-2013 Free Software Foundation, Inc. ++ + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. +- ++ + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. +- ++ + You should have received a copy of the GNU General Public License + along with this program. If not, see . */ + +@@ -26,13 +26,13 @@ + special exception, which will cause the skeleton and the resulting + Bison output files to be licensed under the GNU General Public + License without this special exception. +- ++ + This special exception was added by the Free Software Foundation in + version 2.2 of Bison. */ + + #ifndef YY_YY_DTC_PARSER_TAB_H_INCLUDED + # define YY_YY_DTC_PARSER_TAB_H_INCLUDED +-/* Enabling traces. */ ++/* Debug traces. */ + #ifndef YYDEBUG + # define YYDEBUG 0 + #endif +@@ -40,48 +40,45 @@ + extern int yydebug; + #endif + +-/* Tokens. */ ++/* Token type. */ + #ifndef YYTOKENTYPE + # define YYTOKENTYPE +- /* Put the tokens into the symbol table, so that GDB and other debuggers +- know about them. */ +- enum yytokentype { +- DT_V1 = 258, +- DT_MEMRESERVE = 259, +- DT_LSHIFT = 260, +- DT_RSHIFT = 261, +- DT_LE = 262, +- DT_GE = 263, +- DT_EQ = 264, +- DT_NE = 265, +- DT_AND = 266, +- DT_OR = 267, +- DT_BITS = 268, +- DT_DEL_PROP = 269, +- DT_DEL_NODE = 270, +- DT_PROPNODENAME = 271, +- DT_LITERAL = 272, +- DT_CHAR_LITERAL = 273, +- DT_BASE = 274, +- DT_BYTE = 275, +- DT_STRING = 276, +- DT_LABEL = 277, +- DT_REF = 278, +- DT_INCBIN = 279 +- }; ++ enum yytokentype ++ { ++ DT_V1 = 258, ++ DT_PLUGIN = 259, ++ DT_MEMRESERVE = 260, ++ DT_LSHIFT = 261, ++ DT_RSHIFT = 262, ++ DT_LE = 263, ++ DT_GE = 264, ++ DT_EQ = 265, ++ DT_NE = 266, ++ DT_AND = 267, ++ DT_OR = 268, ++ DT_BITS = 269, ++ DT_DEL_PROP = 270, ++ DT_DEL_NODE = 271, ++ DT_PROPNODENAME = 272, ++ DT_LITERAL = 273, ++ DT_CHAR_LITERAL = 274, ++ DT_BYTE = 275, ++ DT_STRING = 276, ++ DT_LABEL = 277, ++ DT_REF = 278, ++ DT_INCBIN = 279 ++ }; + #endif + +- ++/* Value type. */ + #if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED +-typedef union YYSTYPE ++typedef union YYSTYPE YYSTYPE; ++union YYSTYPE + { +-/* Line 2053 of yacc.c */ +-#line 40 "dtc-parser.y" ++#line 39 "dtc-parser.y" /* yacc.c:1909 */ + + char *propnodename; +- char *literal; + char *labelref; +- unsigned int cbase; + uint8_t byte; + struct data data; + +@@ -96,30 +93,31 @@ + struct node *nodelist; + struct reserve_info *re; + uint64_t integer; ++ int is_plugin; + +- +-/* Line 2053 of yacc.c */ +-#line 103 "dtc-parser.tab.h" +-} YYSTYPE; ++#line 99 "dtc-parser.tab.h" /* yacc.c:1909 */ ++}; + # define YYSTYPE_IS_TRIVIAL 1 +-# define yystype YYSTYPE /* obsolescent; will be withdrawn */ + # define YYSTYPE_IS_DECLARED 1 + #endif + +-extern YYSTYPE yylval; +- +-#ifdef YYPARSE_PARAM +-#if defined __STDC__ || defined __cplusplus +-int yyparse (void *YYPARSE_PARAM); +-#else +-int yyparse (); ++/* Location type. */ ++#if ! defined YYLTYPE && ! defined YYLTYPE_IS_DECLARED ++typedef struct YYLTYPE YYLTYPE; ++struct YYLTYPE ++{ ++ int first_line; ++ int first_column; ++ int last_line; ++ int last_column; ++}; ++# define YYLTYPE_IS_DECLARED 1 ++# define YYLTYPE_IS_TRIVIAL 1 + #endif +-#else /* ! YYPARSE_PARAM */ +-#if defined __STDC__ || defined __cplusplus ++ ++ ++extern YYSTYPE yylval; ++extern YYLTYPE yylloc; + int yyparse (void); +-#else +-int yyparse (); +-#endif +-#endif /* ! YYPARSE_PARAM */ + + #endif /* !YY_YY_DTC_PARSER_TAB_H_INCLUDED */ +diff -Nur linux-4.1.13.orig/scripts/dtc/dtc-parser.y linux-rpi/scripts/dtc/dtc-parser.y +--- linux-4.1.13.orig/scripts/dtc/dtc-parser.y 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/scripts/dtc/dtc-parser.y 2015-11-29 09:42:41.406999830 +0100 +@@ -17,31 +17,28 @@ + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 + * USA + */ +- + %{ + #include ++#include + + #include "dtc.h" + #include "srcpos.h" + +-YYLTYPE yylloc; +- + extern int yylex(void); +-extern void print_error(char const *fmt, ...); + extern void yyerror(char const *s); ++#define ERROR(loc, ...) \ ++ do { \ ++ srcpos_error((loc), "Error", __VA_ARGS__); \ ++ treesource_error = true; \ ++ } while (0) + + extern struct boot_info *the_boot_info; +-extern int treesource_error; +- +-static unsigned long long eval_literal(const char *s, int base, int bits); +-static unsigned char eval_char_literal(const char *s); ++extern bool treesource_error; + %} + + %union { + char *propnodename; +- char *literal; + char *labelref; +- unsigned int cbase; + uint8_t byte; + struct data data; + +@@ -56,18 +53,19 @@ + struct node *nodelist; + struct reserve_info *re; + uint64_t integer; ++ int is_plugin; + } + + %token DT_V1 ++%token DT_PLUGIN + %token DT_MEMRESERVE + %token DT_LSHIFT DT_RSHIFT DT_LE DT_GE DT_EQ DT_NE DT_AND DT_OR + %token DT_BITS + %token DT_DEL_PROP + %token DT_DEL_NODE + %token DT_PROPNODENAME +-%token DT_LITERAL +-%token DT_CHAR_LITERAL +-%token DT_BASE ++%token DT_LITERAL ++%token DT_CHAR_LITERAL + %token DT_BYTE + %token DT_STRING + %token DT_LABEL +@@ -76,6 +74,7 @@ + + %type propdata + %type propdataprefix ++%type plugindecl + %type memreserve + %type memreserves + %type arrayprefix +@@ -106,10 +105,23 @@ + %% + + sourcefile: +- DT_V1 ';' memreserves devicetree ++ DT_V1 ';' plugindecl memreserves devicetree ++ { ++ $5->is_plugin = $3; ++ $5->is_root = 1; ++ the_boot_info = build_boot_info($4, $5, ++ guess_boot_cpuid($5)); ++ } ++ ; ++ ++plugindecl: ++ /* empty */ ++ { ++ $$ = 0; ++ } ++ | DT_PLUGIN ';' + { +- the_boot_info = build_boot_info($3, $4, +- guess_boot_cpuid($4)); ++ $$ = 1; + } + ; + +@@ -152,17 +164,18 @@ + if (target) + merge_nodes(target, $3); + else +- print_error("label or path, '%s', not found", $2); ++ ERROR(&@2, "Label or path %s not found", $2); + $$ = $1; + } + | devicetree DT_DEL_NODE DT_REF ';' + { + struct node *target = get_node_by_ref($1, $3); + +- if (!target) +- print_error("label or path, '%s', not found", $3); +- else ++ if (target) + delete_node(target); ++ else ++ ERROR(&@3, "Label or path %s not found", $3); ++ + + $$ = $1; + } +@@ -230,10 +243,9 @@ + + if ($6 != 0) + if (fseek(f, $6, SEEK_SET) != 0) +- print_error("Couldn't seek to offset %llu in \"%s\": %s", +- (unsigned long long)$6, +- $4.val, +- strerror(errno)); ++ die("Couldn't seek to offset %llu in \"%s\": %s", ++ (unsigned long long)$6, $4.val, ++ strerror(errno)); + + d = data_copy_file(f, $8); + +@@ -274,18 +286,19 @@ + arrayprefix: + DT_BITS DT_LITERAL '<' + { +- $$.data = empty_data; +- $$.bits = eval_literal($2, 0, 7); ++ unsigned long long bits; + +- if (($$.bits != 8) && +- ($$.bits != 16) && +- ($$.bits != 32) && +- ($$.bits != 64)) +- { +- print_error("Only 8, 16, 32 and 64-bit elements" +- " are currently supported"); +- $$.bits = 32; ++ bits = $2; ++ ++ if ((bits != 8) && (bits != 16) && ++ (bits != 32) && (bits != 64)) { ++ ERROR(&@2, "Array elements must be" ++ " 8, 16, 32 or 64-bits"); ++ bits = 32; + } ++ ++ $$.data = empty_data; ++ $$.bits = bits; + } + | '<' + { +@@ -305,9 +318,8 @@ + * mask), all bits are one. + */ + if (($2 > mask) && (($2 | mask) != -1ULL)) +- print_error( +- "integer value out of range " +- "%016lx (%d bits)", $1.bits); ++ ERROR(&@2, "Value out of range for" ++ " %d-bit array element", $1.bits); + } + + $$.data = data_append_integer($1.data, $2, $1.bits); +@@ -321,7 +333,7 @@ + REF_PHANDLE, + $2); + else +- print_error("References are only allowed in " ++ ERROR(&@2, "References are only allowed in " + "arrays with 32-bit elements."); + + $$.data = data_append_integer($1.data, val, $1.bits); +@@ -334,13 +346,7 @@ + + integer_prim: + DT_LITERAL +- { +- $$ = eval_literal($1, 0, 64); +- } + | DT_CHAR_LITERAL +- { +- $$ = eval_char_literal($1); +- } + | '(' integer_expr ')' + { + $$ = $2; +@@ -447,7 +453,7 @@ + } + | subnode propdef + { +- print_error("syntax error: properties must precede subnodes"); ++ ERROR(&@2, "Properties must precede subnodes"); + YYERROR; + } + ; +@@ -470,63 +476,7 @@ + + %% + +-void print_error(char const *fmt, ...) ++void yyerror(char const *s) + { +- va_list va; +- +- va_start(va, fmt); +- srcpos_verror(&yylloc, fmt, va); +- va_end(va); +- +- treesource_error = 1; +-} +- +-void yyerror(char const *s) { +- print_error("%s", s); +-} +- +-static unsigned long long eval_literal(const char *s, int base, int bits) +-{ +- unsigned long long val; +- char *e; +- +- errno = 0; +- val = strtoull(s, &e, base); +- if (*e) { +- size_t uls = strspn(e, "UL"); +- if (e[uls]) +- print_error("bad characters in literal"); +- } +- if ((errno == ERANGE) +- || ((bits < 64) && (val >= (1ULL << bits)))) +- print_error("literal out of range"); +- else if (errno != 0) +- print_error("bad literal"); +- return val; +-} +- +-static unsigned char eval_char_literal(const char *s) +-{ +- int i = 1; +- char c = s[0]; +- +- if (c == '\0') +- { +- print_error("empty character literal"); +- return 0; +- } +- +- /* +- * If the first character in the character literal is a \ then process +- * the remaining characters as an escape encoding. If the first +- * character is neither an escape or a terminator it should be the only +- * character in the literal and will be returned. +- */ +- if (c == '\\') +- c = get_escape_char(s, &i); +- +- if (s[i] != '\0') +- print_error("malformed character literal"); +- +- return c; ++ ERROR(&yylloc, "%s", s); + } +diff -Nur linux-4.1.13.orig/scripts/dtc/flattree.c linux-rpi/scripts/dtc/flattree.c +--- linux-4.1.13.orig/scripts/dtc/flattree.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/scripts/dtc/flattree.c 2015-11-29 09:42:41.406999830 +0100 +@@ -261,7 +261,13 @@ + { + struct property *prop; + struct node *child; +- int seen_name_prop = 0; ++ bool seen_name_prop = false; ++ struct symbol *sym; ++ struct fixup *f; ++ struct fixup_entry *fe; ++ char *name, *s; ++ const char *fullpath; ++ int namesz, nameoff, vallen; + + if (tree->deleted) + return; +@@ -276,10 +282,8 @@ + emit->align(etarget, sizeof(cell_t)); + + for_each_property(tree, prop) { +- int nameoff; +- + if (streq(prop->name, "name")) +- seen_name_prop = 1; ++ seen_name_prop = true; + + nameoff = stringtable_insert(strbuf, prop->name); + +@@ -310,6 +314,139 @@ + flatten_tree(child, emit, etarget, strbuf, vi); + } + ++ if (!symbol_fixup_support) ++ goto no_symbols; ++ ++ /* add the symbol nodes (if any) */ ++ if (tree->symbols) { ++ ++ emit->beginnode(etarget, NULL); ++ emit->string(etarget, "__symbols__", 0); ++ emit->align(etarget, sizeof(cell_t)); ++ ++ for_each_symbol(tree, sym) { ++ ++ vallen = strlen(sym->node->fullpath); ++ ++ nameoff = stringtable_insert(strbuf, sym->label->label); ++ ++ emit->property(etarget, NULL); ++ emit->cell(etarget, vallen + 1); ++ emit->cell(etarget, nameoff); ++ ++ if ((vi->flags & FTF_VARALIGN) && vallen >= 8) ++ emit->align(etarget, 8); ++ ++ emit->string(etarget, sym->node->fullpath, ++ strlen(sym->node->fullpath)); ++ emit->align(etarget, sizeof(cell_t)); ++ } ++ ++ emit->endnode(etarget, NULL); ++ } ++ ++ /* add the fixup nodes */ ++ if (tree->fixups) { ++ ++ /* emit the external fixups */ ++ emit->beginnode(etarget, NULL); ++ emit->string(etarget, "__fixups__", 0); ++ emit->align(etarget, sizeof(cell_t)); ++ ++ for_each_fixup(tree, f) { ++ ++ namesz = 0; ++ for_each_fixup_entry(f, fe) { ++ fullpath = fe->node->fullpath; ++ if (fullpath[0] == '\0') ++ fullpath = "/"; ++ namesz += strlen(fullpath) + 1; ++ namesz += strlen(fe->prop->name) + 1; ++ namesz += 32; /* space for : + '\0' */ ++ } ++ ++ name = xmalloc(namesz); ++ ++ s = name; ++ for_each_fixup_entry(f, fe) { ++ fullpath = fe->node->fullpath; ++ if (fullpath[0] == '\0') ++ fullpath = "/"; ++ snprintf(s, name + namesz - s, "%s:%s:%d", ++ fullpath, ++ fe->prop->name, fe->offset); ++ s += strlen(s) + 1; ++ } ++ ++ nameoff = stringtable_insert(strbuf, f->ref); ++ vallen = s - name - 1; ++ ++ emit->property(etarget, NULL); ++ emit->cell(etarget, vallen + 1); ++ emit->cell(etarget, nameoff); ++ ++ if ((vi->flags & FTF_VARALIGN) && vallen >= 8) ++ emit->align(etarget, 8); ++ ++ emit->string(etarget, name, vallen); ++ emit->align(etarget, sizeof(cell_t)); ++ ++ free(name); ++ } ++ ++ emit->endnode(etarget, tree->labels); ++ } ++ ++ /* add the local fixup property */ ++ if (tree->local_fixups) { ++ ++ /* emit the external fixups */ ++ emit->beginnode(etarget, NULL); ++ emit->string(etarget, "__local_fixups__", 0); ++ emit->align(etarget, sizeof(cell_t)); ++ ++ namesz = 0; ++ for_each_local_fixup_entry(tree, fe) { ++ fullpath = fe->node->fullpath; ++ if (fullpath[0] == '\0') ++ fullpath = "/"; ++ namesz += strlen(fullpath) + 1; ++ namesz += strlen(fe->prop->name) + 1; ++ namesz += 32; /* space for : + '\0' */ ++ } ++ ++ name = xmalloc(namesz); ++ ++ s = name; ++ for_each_local_fixup_entry(tree, fe) { ++ fullpath = fe->node->fullpath; ++ if (fullpath[0] == '\0') ++ fullpath = "/"; ++ snprintf(s, name + namesz - s, "%s:%s:%d", ++ fullpath, fe->prop->name, ++ fe->offset); ++ s += strlen(s) + 1; ++ } ++ ++ nameoff = stringtable_insert(strbuf, "fixup"); ++ vallen = s - name - 1; ++ ++ emit->property(etarget, NULL); ++ emit->cell(etarget, vallen + 1); ++ emit->cell(etarget, nameoff); ++ ++ if ((vi->flags & FTF_VARALIGN) && vallen >= 8) ++ emit->align(etarget, 8); ++ ++ emit->string(etarget, name, vallen); ++ emit->align(etarget, sizeof(cell_t)); ++ ++ free(name); ++ ++ emit->endnode(etarget, tree->labels); ++ } ++ ++no_symbols: + emit->endnode(etarget, tree->labels); + } + +diff -Nur linux-4.1.13.orig/scripts/dtc/fstree.c linux-rpi/scripts/dtc/fstree.c +--- linux-4.1.13.orig/scripts/dtc/fstree.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/scripts/dtc/fstree.c 2015-11-29 09:42:41.406999830 +0100 +@@ -37,26 +37,26 @@ + tree = build_node(NULL, NULL); + + while ((de = readdir(d)) != NULL) { +- char *tmpnam; ++ char *tmpname; + + if (streq(de->d_name, ".") + || streq(de->d_name, "..")) + continue; + +- tmpnam = join_path(dirname, de->d_name); ++ tmpname = join_path(dirname, de->d_name); + +- if (lstat(tmpnam, &st) < 0) +- die("stat(%s): %s\n", tmpnam, strerror(errno)); ++ if (lstat(tmpname, &st) < 0) ++ die("stat(%s): %s\n", tmpname, strerror(errno)); + + if (S_ISREG(st.st_mode)) { + struct property *prop; + FILE *pfile; + +- pfile = fopen(tmpnam, "r"); ++ pfile = fopen(tmpname, "rb"); + if (! pfile) { + fprintf(stderr, + "WARNING: Cannot open %s: %s\n", +- tmpnam, strerror(errno)); ++ tmpname, strerror(errno)); + } else { + prop = build_property(xstrdup(de->d_name), + data_copy_file(pfile, +@@ -67,12 +67,12 @@ + } else if (S_ISDIR(st.st_mode)) { + struct node *newchild; + +- newchild = read_fstree(tmpnam); ++ newchild = read_fstree(tmpname); + newchild = name_node(newchild, xstrdup(de->d_name)); + add_child(tree, newchild); + } + +- free(tmpnam); ++ free(tmpname); + } + + closedir(d); +diff -Nur linux-4.1.13.orig/scripts/dtc/livetree.c linux-rpi/scripts/dtc/livetree.c +--- linux-4.1.13.orig/scripts/dtc/livetree.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/scripts/dtc/livetree.c 2015-11-29 09:42:41.410999565 +0100 +@@ -511,7 +511,9 @@ + + struct node *get_node_by_ref(struct node *tree, const char *ref) + { +- if (ref[0] == '/') ++ if (streq(ref, "/")) ++ return tree; ++ else if (ref[0] == '/') + return get_node_by_path(tree, ref); + else + return get_node_by_label(tree, ref); +diff -Nur linux-4.1.13.orig/scripts/dtc/srcpos.c linux-rpi/scripts/dtc/srcpos.c +--- linux-4.1.13.orig/scripts/dtc/srcpos.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/scripts/dtc/srcpos.c 2015-11-29 09:42:41.410999565 +0100 +@@ -34,7 +34,7 @@ + static struct search_path *search_path_head, **search_path_tail; + + +-static char *dirname(const char *path) ++static char *get_dirname(const char *path) + { + const char *slash = strrchr(path, '/'); + +@@ -77,7 +77,7 @@ + else + fullname = join_path(dirname, fname); + +- *fp = fopen(fullname, "r"); ++ *fp = fopen(fullname, "rb"); + if (!*fp) { + free(fullname); + fullname = NULL; +@@ -150,7 +150,7 @@ + srcfile = xmalloc(sizeof(*srcfile)); + + srcfile->f = srcfile_relative_open(fname, &srcfile->name); +- srcfile->dir = dirname(srcfile->name); ++ srcfile->dir = get_dirname(srcfile->name); + srcfile->prev = current_srcfile; + + srcfile->lineno = 1; +@@ -159,7 +159,7 @@ + current_srcfile = srcfile; + } + +-int srcfile_pop(void) ++bool srcfile_pop(void) + { + struct srcfile_state *srcfile = current_srcfile; + +@@ -177,7 +177,7 @@ + * fix this we could either allocate all the files from a + * table, or use a pool allocator. */ + +- return current_srcfile ? 1 : 0; ++ return current_srcfile ? true : false; + } + + void srcfile_add_search_path(const char *dirname) +@@ -290,42 +290,27 @@ + return pos_str; + } + +-void +-srcpos_verror(struct srcpos *pos, char const *fmt, va_list va) ++void srcpos_verror(struct srcpos *pos, const char *prefix, ++ const char *fmt, va_list va) + { +- const char *srcstr; +- +- srcstr = srcpos_string(pos); ++ char *srcstr; + +- fprintf(stderr, "Error: %s ", srcstr); +- vfprintf(stderr, fmt, va); +- fprintf(stderr, "\n"); +-} ++ srcstr = srcpos_string(pos); + +-void +-srcpos_error(struct srcpos *pos, char const *fmt, ...) +-{ +- va_list va; ++ fprintf(stderr, "%s: %s ", prefix, srcstr); ++ vfprintf(stderr, fmt, va); ++ fprintf(stderr, "\n"); + +- va_start(va, fmt); +- srcpos_verror(pos, fmt, va); +- va_end(va); ++ free(srcstr); + } + +- +-void +-srcpos_warn(struct srcpos *pos, char const *fmt, ...) ++void srcpos_error(struct srcpos *pos, const char *prefix, ++ const char *fmt, ...) + { +- const char *srcstr; + va_list va; +- va_start(va, fmt); +- +- srcstr = srcpos_string(pos); +- +- fprintf(stderr, "Warning: %s ", srcstr); +- vfprintf(stderr, fmt, va); +- fprintf(stderr, "\n"); + ++ va_start(va, fmt); ++ srcpos_verror(pos, prefix, fmt, va); + va_end(va); + } + +diff -Nur linux-4.1.13.orig/scripts/dtc/srcpos.h linux-rpi/scripts/dtc/srcpos.h +--- linux-4.1.13.orig/scripts/dtc/srcpos.h 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/scripts/dtc/srcpos.h 2015-11-29 09:42:41.410999565 +0100 +@@ -21,6 +21,7 @@ + #define _SRCPOS_H_ + + #include ++#include + + struct srcfile_state { + FILE *f; +@@ -55,7 +56,7 @@ + FILE *srcfile_relative_open(const char *fname, char **fullnamep); + + void srcfile_push(const char *fname); +-int srcfile_pop(void); ++bool srcfile_pop(void); + + /** + * Add a new directory to the search path for input files +@@ -106,12 +107,12 @@ + extern char *srcpos_string(struct srcpos *pos); + extern void srcpos_dump(struct srcpos *pos); + +-extern void srcpos_verror(struct srcpos *pos, char const *, va_list va) +- __attribute__((format(printf, 2, 0))); +-extern void srcpos_error(struct srcpos *pos, char const *, ...) +- __attribute__((format(printf, 2, 3))); +-extern void srcpos_warn(struct srcpos *pos, char const *, ...) +- __attribute__((format(printf, 2, 3))); ++extern void srcpos_verror(struct srcpos *pos, const char *prefix, ++ const char *fmt, va_list va) ++ __attribute__((format(printf, 3, 0))); ++extern void srcpos_error(struct srcpos *pos, const char *prefix, ++ const char *fmt, ...) ++ __attribute__((format(printf, 3, 4))); + + extern void srcpos_set_line(char *f, int l); + +diff -Nur linux-4.1.13.orig/scripts/dtc/treesource.c linux-rpi/scripts/dtc/treesource.c +--- linux-4.1.13.orig/scripts/dtc/treesource.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/scripts/dtc/treesource.c 2015-11-29 09:42:41.410999565 +0100 +@@ -26,12 +26,12 @@ + extern YYLTYPE yylloc; + + struct boot_info *the_boot_info; +-int treesource_error; ++bool treesource_error; + + struct boot_info *dt_from_source(const char *fname) + { + the_boot_info = NULL; +- treesource_error = 0; ++ treesource_error = false; + + srcfile_push(fname); + yyin = current_srcfile->f; +@@ -54,9 +54,9 @@ + fputc('\t', f); + } + +-static int isstring(char c) ++static bool isstring(char c) + { +- return (isprint(c) ++ return (isprint((unsigned char)c) + || (c == '\0') + || strchr("\a\b\t\n\v\f\r", c)); + } +@@ -109,7 +109,7 @@ + break; + case '\0': + fprintf(f, "\", "); +- while (m && (m->offset < i)) { ++ while (m && (m->offset <= (i + 1))) { + if (m->type == LABEL) { + assert(m->offset == (i+1)); + fprintf(f, "%s: ", m->ref); +@@ -119,7 +119,7 @@ + fprintf(f, "\""); + break; + default: +- if (isprint(c)) ++ if (isprint((unsigned char)c)) + fprintf(f, "%c", c); + else + fprintf(f, "\\x%02hhx", c); +@@ -178,7 +178,7 @@ + m = m->next; + } + +- fprintf(f, "%02hhx", *bp++); ++ fprintf(f, "%02hhx", (unsigned char)(*bp++)); + if ((const void *)bp >= propend) + break; + fprintf(f, " "); +diff -Nur linux-4.1.13.orig/scripts/dtc/util.c linux-rpi/scripts/dtc/util.c +--- linux-4.1.13.orig/scripts/dtc/util.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/scripts/dtc/util.c 2015-11-29 09:42:41.410999565 +0100 +@@ -39,11 +39,11 @@ + char *xstrdup(const char *s) + { + int len = strlen(s) + 1; +- char *dup = xmalloc(len); ++ char *d = xmalloc(len); + +- memcpy(dup, s, len); ++ memcpy(d, s, len); + +- return dup; ++ return d; + } + + char *join_path(const char *path, const char *name) +@@ -70,7 +70,7 @@ + return str; + } + +-int util_is_printable_string(const void *data, int len) ++bool util_is_printable_string(const void *data, int len) + { + const char *s = data; + const char *ss, *se; +@@ -87,7 +87,7 @@ + + while (s < se) { + ss = s; +- while (s < se && *s && isprint(*s)) ++ while (s < se && *s && isprint((unsigned char)*s)) + s++; + + /* not zero, or not done yet */ +@@ -219,10 +219,6 @@ + if (offset == bufsize) { + bufsize *= 2; + buf = xrealloc(buf, bufsize); +- if (!buf) { +- ret = ENOMEM; +- break; +- } + } + + ret = read(fd, &buf[offset], bufsize - offset); +@@ -375,9 +371,9 @@ + const uint32_t *cell = (const uint32_t *)data; + + printf(" = <"); +- for (i = 0; i < len; i += 4) ++ for (i = 0, len /= 4; i < len; i++) + printf("0x%08x%s", fdt32_to_cpu(cell[i]), +- i < (len - 4) ? " " : ""); ++ i < (len - 1) ? " " : ""); + printf(">"); + } else { + printf(" = ["); +diff -Nur linux-4.1.13.orig/scripts/dtc/util.h linux-rpi/scripts/dtc/util.h +--- linux-4.1.13.orig/scripts/dtc/util.h 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/scripts/dtc/util.h 2015-11-29 09:42:41.410999565 +0100 +@@ -2,6 +2,7 @@ + #define _UTIL_H + + #include ++#include + #include + + /* +@@ -33,6 +34,7 @@ + va_start(ap, str); + fprintf(stderr, "FATAL ERROR: "); + vfprintf(stderr, str, ap); ++ va_end(ap); + exit(1); + } + +@@ -68,7 +70,7 @@ + * @param len The string length including terminator + * @return 1 if a valid printable string, 0 if not + */ +-int util_is_printable_string(const void *data, int len); ++bool util_is_printable_string(const void *data, int len); + + /* + * Parse an escaped character starting at index i in string s. The resulting +diff -Nur linux-4.1.13.orig/scripts/dtc/version_gen.h linux-rpi/scripts/dtc/version_gen.h +--- linux-4.1.13.orig/scripts/dtc/version_gen.h 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/scripts/dtc/version_gen.h 2015-11-29 09:42:41.410999565 +0100 +@@ -1 +1 @@ +-#define DTC_VERSION "DTC 1.4.0-dirty" ++#define DTC_VERSION "DTC 1.4.1-g36c70742" +diff -Nur linux-4.1.13.orig/scripts/knlinfo linux-rpi/scripts/knlinfo +--- linux-4.1.13.orig/scripts/knlinfo 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/scripts/knlinfo 2015-11-29 09:42:41.418999033 +0100 +@@ -0,0 +1,168 @@ ++#!/usr/bin/env perl ++# ---------------------------------------------------------------------- ++# knlinfo by Phil Elwell for Raspberry Pi ++# ++# (c) 2014,2015 Raspberry Pi (Trading) Limited ++# ++# Licensed under the terms of the GNU General Public License. ++# ---------------------------------------------------------------------- ++ ++use strict; ++use integer; ++ ++use Fcntl ":seek"; ++ ++my $trailer_magic = 'RPTL'; ++ ++my %atom_formats = ++( ++ 'DTOK' => \&format_bool, ++ 'KVer' => \&format_string, ++ '283x' => \&format_bool, ++); ++ ++if (@ARGV != 1) ++{ ++ print ("Usage: knlinfo \n"); ++ exit(1); ++} ++ ++my $kernel_file = $ARGV[0]; ++ ++ ++my ($atoms, $pos) = read_trailer($kernel_file); ++ ++exit(1) if (!$atoms); ++ ++printf("Kernel trailer found at %d/0x%x:\n", $pos, $pos); ++ ++foreach my $atom (@$atoms) ++{ ++ printf(" %s: %s\n", $atom->[0], format_atom($atom)); ++} ++ ++exit(0); ++ ++sub read_trailer ++{ ++ my ($kernel_file) = @_; ++ my $fh; ++ ++ if (!open($fh, '<', $kernel_file)) ++ { ++ print ("* Failed to open '$kernel_file'\n"); ++ return undef; ++ } ++ ++ if (!seek($fh, -12, SEEK_END)) ++ { ++ print ("* seek error in '$kernel_file'\n"); ++ return undef; ++ } ++ ++ my $last_bytes; ++ sysread($fh, $last_bytes, 12); ++ ++ my ($trailer_len, $data_len, $magic) = unpack('VVa4', $last_bytes); ++ ++ if (($magic ne $trailer_magic) || ($data_len != 4)) ++ { ++ print ("* no trailer\n"); ++ return undef; ++ } ++ if (!seek($fh, -12, SEEK_END)) ++ { ++ print ("* seek error in '$kernel_file'\n"); ++ return undef; ++ } ++ ++ $trailer_len -= 12; ++ ++ while ($trailer_len > 0) ++ { ++ if ($trailer_len < 8) ++ { ++ print ("* truncated atom header in trailer\n"); ++ return undef; ++ } ++ if (!seek($fh, -8, SEEK_CUR)) ++ { ++ print ("* seek error in '$kernel_file'\n"); ++ return undef; ++ } ++ $trailer_len -= 8; ++ ++ my $atom_hdr; ++ sysread($fh, $atom_hdr, 8); ++ my ($atom_len, $atom_type) = unpack('Va4', $atom_hdr); ++ ++ if ($trailer_len < $atom_len) ++ { ++ print ("* truncated atom data in trailer\n"); ++ return undef; ++ } ++ ++ my $rounded_len = (($atom_len + 3) & ~3); ++ if (!seek($fh, -(8 + $rounded_len), SEEK_CUR)) ++ { ++ print ("* seek error in '$kernel_file'\n"); ++ return undef; ++ } ++ $trailer_len -= $rounded_len; ++ ++ my $atom_data; ++ sysread($fh, $atom_data, $atom_len); ++ ++ if (!seek($fh, -$atom_len, SEEK_CUR)) ++ { ++ print ("* seek error in '$kernel_file'\n"); ++ return undef; ++ } ++ ++ push @$atoms, [ $atom_type, $atom_data ]; ++ } ++ ++ if (($$atoms[-1][0] eq "\x00\x00\x00\x00") && ++ ($$atoms[-1][1] eq "")) ++ { ++ pop @$atoms; ++ } ++ else ++ { ++ print ("* end marker missing from trailer\n"); ++ } ++ ++ return ($atoms, tell($fh)); ++} ++ ++sub format_atom ++{ ++ my ($atom) = @_; ++ ++ my $format_func = $atom_formats{$atom->[0]} || \&format_hex; ++ return $format_func->($atom->[1]); ++} ++ ++sub format_bool ++{ ++ my ($data) = @_; ++ return unpack('V', $data) ? 'true' : 'false'; ++} ++ ++sub format_int ++{ ++ my ($data) = @_; ++ return unpack('V', $data); ++} ++ ++sub format_string ++{ ++ my ($data) = @_; ++ return '"'.$data.'"'; ++} ++ ++sub format_hex ++{ ++ my ($data) = @_; ++ return unpack('H*', $data); ++} +diff -Nur linux-4.1.13.orig/scripts/mkknlimg linux-rpi/scripts/mkknlimg +--- linux-4.1.13.orig/scripts/mkknlimg 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/scripts/mkknlimg 2015-11-29 09:42:41.422998767 +0100 +@@ -0,0 +1,244 @@ ++#!/usr/bin/env perl ++# ---------------------------------------------------------------------- ++# mkknlimg by Phil Elwell for Raspberry Pi ++# based on extract-ikconfig by Dick Streefland ++# ++# (c) 2009,2010 Dick Streefland ++# (c) 2014,2015 Raspberry Pi (Trading) Limited ++# ++# Licensed under the terms of the GNU General Public License. ++# ---------------------------------------------------------------------- ++ ++use strict; ++use warnings; ++use integer; ++ ++my $trailer_magic = 'RPTL'; ++ ++my $tmpfile1 = "/tmp/mkknlimg_$$.1"; ++my $tmpfile2 = "/tmp/mkknlimg_$$.2"; ++ ++my $dtok = 0; ++my $is_283x = 0; ++ ++while (@ARGV && ($ARGV[0] =~ /^-/)) ++{ ++ my $arg = shift(@ARGV); ++ if ($arg eq '--dtok') ++ { ++ $dtok = 1; ++ } ++ elsif ($arg eq '--283x') ++ { ++ $is_283x = 1; ++ } ++ else ++ { ++ print ("* Unknown option '$arg'\n"); ++ usage(); ++ } ++} ++ ++usage() if (@ARGV != 2); ++ ++my $kernel_file = $ARGV[0]; ++my $out_file = $ARGV[1]; ++ ++if (! -r $kernel_file) ++{ ++ print ("* File '$kernel_file' not found\n"); ++ usage(); ++} ++ ++my @wanted_strings = ++( ++ 'bcm2708_fb', ++ 'brcm,bcm2835-mmc', ++ 'brcm,bcm2835-sdhost', ++ 'brcm,bcm2708-pinctrl', ++ 'brcm,bcm2835-gpio', ++ 'brcm,bcm2835', ++ 'brcm,bcm2836' ++); ++ ++my $res = try_extract($kernel_file, $tmpfile1); ++$res = try_decompress('\037\213\010', 'xy', 'gunzip', 0, ++ $kernel_file, $tmpfile1, $tmpfile2) if (!$res); ++$res = try_decompress('\3757zXZ\000', 'abcde', 'unxz --single-stream', -1, ++ $kernel_file, $tmpfile1, $tmpfile2) if (!$res); ++$res = try_decompress('BZh', 'xy', 'bunzip2', 0, ++ $kernel_file, $tmpfile1, $tmpfile2) if (!$res); ++$res = try_decompress('\135\0\0\0', 'xxx', 'unlzma', 0, ++ $kernel_file, $tmpfile1, $tmpfile2) if (!$res); ++$res = try_decompress('\211\114\132', 'xy', 'lzop -d', 0, ++ $kernel_file, $tmpfile1, $tmpfile2) if (!$res); ++$res = try_decompress('\002\041\114\030', 'xy', 'lz4 -d', 1, ++ $kernel_file, $tmpfile1, $tmpfile2) if (!$res); ++ ++my $append_trailer; ++my $trailer; ++my $kver = '?'; ++ ++$append_trailer = $dtok; ++ ++if ($res) ++{ ++ $kver = $res->{''} || '?'; ++ print("Version: $kver\n"); ++ ++ $append_trailer = $dtok; ++ if (!$dtok) ++ { ++ if (config_bool($res, 'bcm2708_fb') || ++ config_bool($res, 'brcm,bcm2835-mmc') || ++ config_bool($res, 'brcm,bcm2835-sdhost')) ++ { ++ $dtok ||= config_bool($res, 'brcm,bcm2708-pinctrl'); ++ $dtok ||= config_bool($res, 'brcm,bcm2835-gpio'); ++ $is_283x ||= config_bool($res, 'brcm,bcm2835'); ++ $is_283x ||= config_bool($res, 'brcm,bcm2836'); ++ $dtok ||= $is_283x; ++ $append_trailer = 1; ++ } ++ else ++ { ++ print ("* This doesn't look like a Raspberry Pi kernel. In pass-through mode.\n"); ++ } ++ } ++} ++elsif (!$dtok) ++{ ++ print ("* Is this a valid kernel? In pass-through mode.\n"); ++} ++ ++if ($append_trailer) ++{ ++ printf("DT: %s\n", $dtok ? "y" : "n"); ++ printf("283x: %s\n", $is_283x ? "y" : "n"); ++ ++ my @atoms; ++ ++ push @atoms, [ $trailer_magic, pack('V', 0) ]; ++ push @atoms, [ 'KVer', $kver ]; ++ push @atoms, [ 'DTOK', pack('V', $dtok) ]; ++ push @atoms, [ '283x', pack('V', $is_283x) ]; ++ ++ $trailer = pack_trailer(\@atoms); ++ $atoms[0]->[1] = pack('V', length($trailer)); ++ ++ $trailer = pack_trailer(\@atoms); ++} ++ ++my $ofh; ++my $total_len = 0; ++ ++if ($out_file eq $kernel_file) ++{ ++ die "* Failed to open '$out_file' for append\n" ++ if (!open($ofh, '>>', $out_file)); ++ $total_len = tell($ofh); ++} ++else ++{ ++ die "* Failed to open '$kernel_file'\n" ++ if (!open(my $ifh, '<', $kernel_file)); ++ die "* Failed to create '$out_file'\n" ++ if (!open($ofh, '>', $out_file)); ++ ++ my $copybuf; ++ while (1) ++ { ++ my $bytes = sysread($ifh, $copybuf, 64*1024); ++ last if (!$bytes); ++ syswrite($ofh, $copybuf, $bytes); ++ $total_len += $bytes; ++ } ++ close($ifh); ++} ++ ++if ($trailer) ++{ ++ # Pad to word-alignment ++ syswrite($ofh, "\x000\x000\x000", (-$total_len & 0x3)); ++ syswrite($ofh, $trailer); ++} ++ ++close($ofh); ++ ++exit($trailer ? 0 : 1); ++ ++END { ++ unlink($tmpfile1) if ($tmpfile1); ++ unlink($tmpfile2) if ($tmpfile2); ++} ++ ++ ++sub usage ++{ ++ print ("Usage: mkknlimg [--dtok] [--283x] \n"); ++ exit(1); ++} ++ ++sub try_extract ++{ ++ my ($knl, $tmp) = @_; ++ ++ my $ver = `strings "$knl" | grep -a -E "^Linux version [1-9]"`; ++ ++ return undef if (!$ver); ++ ++ chomp($ver); ++ ++ my $res = { ''=>$ver }; ++ my $string_pattern = '^('.join('|', @wanted_strings).')$'; ++ ++ my @matches = `strings \"$knl\" | grep -E \"$string_pattern\"`; ++ foreach my $match (@matches) ++ { ++ chomp($match); ++ $res->{$match} = 1; ++ } ++ ++ return $res; ++} ++ ++ ++sub try_decompress ++{ ++ my ($magic, $subst, $zcat, $idx, $knl, $tmp1, $tmp2) = @_; ++ ++ my $pos = `tr "$magic\n$subst" "\n$subst=" < "$knl" | grep -abo "^$subst"`; ++ if ($pos) ++ { ++ chomp($pos); ++ $pos = (split(/[\r\n]+/, $pos))[$idx]; ++ return undef if (!defined($pos)); ++ $pos =~ s/:.*[\r\n]*$//s; ++ my $cmd = "tail -c+$pos \"$knl\" | $zcat > $tmp2 2> /dev/null"; ++ my $err = (system($cmd) >> 8); ++ return undef if (($err != 0) && ($err != 2)); ++ ++ return try_extract($tmp2, $tmp1); ++ } ++ ++ return undef; ++} ++ ++sub pack_trailer ++{ ++ my ($atoms) = @_; ++ my $trailer = pack('VV', 0, 0); ++ for (my $i = $#$atoms; $i>=0; $i--) ++ { ++ my $atom = $atoms->[$i]; ++ $trailer .= pack('a*x!4Va4', $atom->[1], length($atom->[1]), $atom->[0]); ++ } ++ return $trailer; ++} ++ ++sub config_bool ++{ ++ my ($configs, $wanted) = @_; ++ my $val = $configs->{$wanted} || 'n'; ++ return (($val eq 'y') || ($val eq '1')); ++} +diff -Nur linux-4.1.13.orig/sound/arm/bcm2835.c linux-rpi/sound/arm/bcm2835.c +--- linux-4.1.13.orig/sound/arm/bcm2835.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/sound/arm/bcm2835.c 2015-11-29 09:42:41.446997173 +0100 +@@ -0,0 +1,511 @@ ++/***************************************************************************** ++* Copyright 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "bcm2835.h" ++ ++/* module parameters (see "Module Parameters") */ ++/* SNDRV_CARDS: maximum number of cards supported by this module */ ++static int index[MAX_SUBSTREAMS] = {[0 ... (MAX_SUBSTREAMS - 1)] = -1 }; ++static char *id[MAX_SUBSTREAMS] = {[0 ... (MAX_SUBSTREAMS - 1)] = NULL }; ++static int enable[MAX_SUBSTREAMS] = {[0 ... (MAX_SUBSTREAMS - 1)] = 1 }; ++ ++/* HACKY global pointers needed for successive probes to work : ssp ++ * But compared against the changes we will have to do in VC audio_ipc code ++ * to export 8 audio_ipc devices as a single IPC device and then monitor all ++ * four devices in a thread, this gets things done quickly and should be easier ++ * to debug if we run into issues ++ */ ++ ++static struct snd_card *g_card = NULL; ++static bcm2835_chip_t *g_chip = NULL; ++ ++static int snd_bcm2835_free(bcm2835_chip_t * chip) ++{ ++ kfree(chip); ++ return 0; ++} ++ ++/* component-destructor ++ * (see "Management of Cards and Components") ++ */ ++static int snd_bcm2835_dev_free(struct snd_device *device) ++{ ++ return snd_bcm2835_free(device->device_data); ++} ++ ++/* chip-specific constructor ++ * (see "Management of Cards and Components") ++ */ ++static int snd_bcm2835_create(struct snd_card *card, ++ struct platform_device *pdev, ++ bcm2835_chip_t ** rchip) ++{ ++ bcm2835_chip_t *chip; ++ int err; ++ static struct snd_device_ops ops = { ++ .dev_free = snd_bcm2835_dev_free, ++ }; ++ ++ *rchip = NULL; ++ ++ chip = kzalloc(sizeof(*chip), GFP_KERNEL); ++ if (chip == NULL) ++ return -ENOMEM; ++ ++ chip->card = card; ++ ++ err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); ++ if (err < 0) { ++ snd_bcm2835_free(chip); ++ return err; ++ } ++ ++ *rchip = chip; ++ return 0; ++} ++ ++static int snd_bcm2835_alsa_probe_dt(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ bcm2835_chip_t *chip; ++ struct snd_card *card; ++ u32 numchans; ++ int err, i; ++ ++ err = of_property_read_u32(dev->of_node, "brcm,pwm-channels", ++ &numchans); ++ if (err) { ++ dev_err(dev, "Failed to get DT property 'brcm,pwm-channels'"); ++ return err; ++ } ++ ++ if (numchans == 0 || numchans > MAX_SUBSTREAMS) { ++ numchans = MAX_SUBSTREAMS; ++ dev_warn(dev, "Illegal 'brcm,pwm-channels' value, will use %u\n", ++ numchans); ++ } ++ ++ err = snd_card_new(NULL, -1, NULL, THIS_MODULE, 0, &card); ++ if (err) { ++ dev_err(dev, "Failed to create soundcard structure\n"); ++ return err; ++ } ++ ++ snd_card_set_dev(card, dev); ++ strcpy(card->driver, "bcm2835"); ++ strcpy(card->shortname, "bcm2835 ALSA"); ++ sprintf(card->longname, "%s", card->shortname); ++ ++ err = snd_bcm2835_create(card, pdev, &chip); ++ if (err < 0) { ++ dev_err(dev, "Failed to create bcm2835 chip\n"); ++ goto err_free; ++ } ++ ++ err = snd_bcm2835_new_pcm(chip); ++ if (err < 0) { ++ dev_err(dev, "Failed to create new bcm2835 pcm device\n"); ++ goto err_free; ++ } ++ ++ err = snd_bcm2835_new_spdif_pcm(chip); ++ if (err < 0) { ++ dev_err(dev, "Failed to create new bcm2835 spdif pcm device\n"); ++ goto err_free; ++ } ++ ++ err = snd_bcm2835_new_ctl(chip); ++ if (err < 0) { ++ dev_err(dev, "Failed to create new bcm2835 ctl\n"); ++ goto err_free; ++ } ++ ++ for (i = 0; i < numchans; i++) { ++ chip->avail_substreams |= (1 << i); ++ chip->pdev[i] = pdev; ++ } ++ ++ err = snd_card_register(card); ++ if (err) { ++ dev_err(dev, "Failed to register bcm2835 ALSA card \n"); ++ goto err_free; ++ } ++ ++ g_card = card; ++ g_chip = chip; ++ platform_set_drvdata(pdev, card); ++ audio_info("bcm2835 ALSA card created with %u channels\n", numchans); ++ ++ return 0; ++ ++err_free: ++ snd_card_free(card); ++ ++ return err; ++} ++ ++static int snd_bcm2835_alsa_probe(struct platform_device *pdev) ++{ ++ static int dev; ++ bcm2835_chip_t *chip; ++ struct snd_card *card; ++ int err; ++ ++ if (pdev->dev.of_node) ++ return snd_bcm2835_alsa_probe_dt(pdev); ++ ++ if (dev >= MAX_SUBSTREAMS) ++ return -ENODEV; ++ ++ if (!enable[dev]) { ++ dev++; ++ return -ENOENT; ++ } ++ ++ if (dev > 0) ++ goto add_register_map; ++ ++ err = snd_card_new(NULL, index[dev], id[dev], THIS_MODULE, 0, &g_card); ++ if (err < 0) ++ goto out; ++ ++ snd_card_set_dev(g_card, &pdev->dev); ++ strcpy(g_card->driver, "bcm2835"); ++ strcpy(g_card->shortname, "bcm2835 ALSA"); ++ sprintf(g_card->longname, "%s", g_card->shortname); ++ ++ err = snd_bcm2835_create(g_card, pdev, &chip); ++ if (err < 0) { ++ dev_err(&pdev->dev, "Failed to create bcm2835 chip\n"); ++ goto out_bcm2835_create; ++ } ++ ++ g_chip = chip; ++ err = snd_bcm2835_new_pcm(chip); ++ if (err < 0) { ++ dev_err(&pdev->dev, "Failed to create new BCM2835 pcm device\n"); ++ goto out_bcm2835_new_pcm; ++ } ++ ++ err = snd_bcm2835_new_spdif_pcm(chip); ++ if (err < 0) { ++ dev_err(&pdev->dev, "Failed to create new BCM2835 spdif pcm device\n"); ++ goto out_bcm2835_new_spdif; ++ } ++ ++ err = snd_bcm2835_new_ctl(chip); ++ if (err < 0) { ++ dev_err(&pdev->dev, "Failed to create new BCM2835 ctl\n"); ++ goto out_bcm2835_new_ctl; ++ } ++ ++add_register_map: ++ card = g_card; ++ chip = g_chip; ++ ++ BUG_ON(!(card && chip)); ++ ++ chip->avail_substreams |= (1 << dev); ++ chip->pdev[dev] = pdev; ++ ++ if (dev == 0) { ++ err = snd_card_register(card); ++ if (err < 0) { ++ dev_err(&pdev->dev, ++ "Failed to register bcm2835 ALSA card \n"); ++ goto out_card_register; ++ } ++ platform_set_drvdata(pdev, card); ++ audio_info("bcm2835 ALSA card created!\n"); ++ } else { ++ audio_info("bcm2835 ALSA chip created!\n"); ++ platform_set_drvdata(pdev, (void *)dev); ++ } ++ ++ dev++; ++ ++ return 0; ++ ++out_card_register: ++out_bcm2835_new_ctl: ++out_bcm2835_new_spdif: ++out_bcm2835_new_pcm: ++out_bcm2835_create: ++ BUG_ON(!g_card); ++ if (snd_card_free(g_card)) ++ dev_err(&pdev->dev, "Failed to free Registered alsa card\n"); ++ g_card = NULL; ++out: ++ dev = SNDRV_CARDS; /* stop more avail_substreams from being probed */ ++ dev_err(&pdev->dev, "BCM2835 ALSA Probe failed !!\n"); ++ return err; ++} ++ ++static int snd_bcm2835_alsa_remove(struct platform_device *pdev) ++{ ++ uint32_t idx; ++ void *drv_data; ++ ++ drv_data = platform_get_drvdata(pdev); ++ ++ if (drv_data == (void *)g_card) { ++ /* This is the card device */ ++ snd_card_free((struct snd_card *)drv_data); ++ g_card = NULL; ++ g_chip = NULL; ++ } else { ++ idx = (uint32_t) drv_data; ++ if (g_card != NULL) { ++ BUG_ON(!g_chip); ++ /* We pass chip device numbers in audio ipc devices ++ * other than the one we registered our card with ++ */ ++ idx = (uint32_t) drv_data; ++ BUG_ON(!idx || idx > MAX_SUBSTREAMS); ++ g_chip->avail_substreams &= ~(1 << idx); ++ /* There should be atleast one substream registered ++ * after we are done here, as it wil be removed when ++ * the *remove* is called for the card device ++ */ ++ BUG_ON(!g_chip->avail_substreams); ++ } ++ } ++ ++ platform_set_drvdata(pdev, NULL); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int snd_bcm2835_alsa_suspend(struct platform_device *pdev, ++ pm_message_t state) ++{ ++ return 0; ++} ++ ++static int snd_bcm2835_alsa_resume(struct platform_device *pdev) ++{ ++ return 0; ++} ++ ++#endif ++ ++static const struct of_device_id snd_bcm2835_of_match_table[] = { ++ { .compatible = "brcm,bcm2835-audio", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, snd_bcm2835_of_match_table); ++ ++static struct platform_driver bcm2835_alsa0_driver = { ++ .probe = snd_bcm2835_alsa_probe, ++ .remove = snd_bcm2835_alsa_remove, ++#ifdef CONFIG_PM ++ .suspend = snd_bcm2835_alsa_suspend, ++ .resume = snd_bcm2835_alsa_resume, ++#endif ++ .driver = { ++ .name = "bcm2835_AUD0", ++ .owner = THIS_MODULE, ++ .of_match_table = snd_bcm2835_of_match_table, ++ }, ++}; ++ ++static struct platform_driver bcm2835_alsa1_driver = { ++ .probe = snd_bcm2835_alsa_probe, ++ .remove = snd_bcm2835_alsa_remove, ++#ifdef CONFIG_PM ++ .suspend = snd_bcm2835_alsa_suspend, ++ .resume = snd_bcm2835_alsa_resume, ++#endif ++ .driver = { ++ .name = "bcm2835_AUD1", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static struct platform_driver bcm2835_alsa2_driver = { ++ .probe = snd_bcm2835_alsa_probe, ++ .remove = snd_bcm2835_alsa_remove, ++#ifdef CONFIG_PM ++ .suspend = snd_bcm2835_alsa_suspend, ++ .resume = snd_bcm2835_alsa_resume, ++#endif ++ .driver = { ++ .name = "bcm2835_AUD2", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static struct platform_driver bcm2835_alsa3_driver = { ++ .probe = snd_bcm2835_alsa_probe, ++ .remove = snd_bcm2835_alsa_remove, ++#ifdef CONFIG_PM ++ .suspend = snd_bcm2835_alsa_suspend, ++ .resume = snd_bcm2835_alsa_resume, ++#endif ++ .driver = { ++ .name = "bcm2835_AUD3", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static struct platform_driver bcm2835_alsa4_driver = { ++ .probe = snd_bcm2835_alsa_probe, ++ .remove = snd_bcm2835_alsa_remove, ++#ifdef CONFIG_PM ++ .suspend = snd_bcm2835_alsa_suspend, ++ .resume = snd_bcm2835_alsa_resume, ++#endif ++ .driver = { ++ .name = "bcm2835_AUD4", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static struct platform_driver bcm2835_alsa5_driver = { ++ .probe = snd_bcm2835_alsa_probe, ++ .remove = snd_bcm2835_alsa_remove, ++#ifdef CONFIG_PM ++ .suspend = snd_bcm2835_alsa_suspend, ++ .resume = snd_bcm2835_alsa_resume, ++#endif ++ .driver = { ++ .name = "bcm2835_AUD5", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static struct platform_driver bcm2835_alsa6_driver = { ++ .probe = snd_bcm2835_alsa_probe, ++ .remove = snd_bcm2835_alsa_remove, ++#ifdef CONFIG_PM ++ .suspend = snd_bcm2835_alsa_suspend, ++ .resume = snd_bcm2835_alsa_resume, ++#endif ++ .driver = { ++ .name = "bcm2835_AUD6", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static struct platform_driver bcm2835_alsa7_driver = { ++ .probe = snd_bcm2835_alsa_probe, ++ .remove = snd_bcm2835_alsa_remove, ++#ifdef CONFIG_PM ++ .suspend = snd_bcm2835_alsa_suspend, ++ .resume = snd_bcm2835_alsa_resume, ++#endif ++ .driver = { ++ .name = "bcm2835_AUD7", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int bcm2835_alsa_device_init(void) ++{ ++ int err; ++ err = platform_driver_register(&bcm2835_alsa0_driver); ++ if (err) { ++ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err); ++ goto out; ++ } ++ ++ err = platform_driver_register(&bcm2835_alsa1_driver); ++ if (err) { ++ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err); ++ goto unregister_0; ++ } ++ ++ err = platform_driver_register(&bcm2835_alsa2_driver); ++ if (err) { ++ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err); ++ goto unregister_1; ++ } ++ ++ err = platform_driver_register(&bcm2835_alsa3_driver); ++ if (err) { ++ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err); ++ goto unregister_2; ++ } ++ ++ err = platform_driver_register(&bcm2835_alsa4_driver); ++ if (err) { ++ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err); ++ goto unregister_3; ++ } ++ ++ err = platform_driver_register(&bcm2835_alsa5_driver); ++ if (err) { ++ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err); ++ goto unregister_4; ++ } ++ ++ err = platform_driver_register(&bcm2835_alsa6_driver); ++ if (err) { ++ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err); ++ goto unregister_5; ++ } ++ ++ err = platform_driver_register(&bcm2835_alsa7_driver); ++ if (err) { ++ pr_err("Error registering bcm2835_alsa0_driver %d .\n", err); ++ goto unregister_6; ++ } ++ ++ return 0; ++ ++unregister_6: ++ platform_driver_unregister(&bcm2835_alsa6_driver); ++unregister_5: ++ platform_driver_unregister(&bcm2835_alsa5_driver); ++unregister_4: ++ platform_driver_unregister(&bcm2835_alsa4_driver); ++unregister_3: ++ platform_driver_unregister(&bcm2835_alsa3_driver); ++unregister_2: ++ platform_driver_unregister(&bcm2835_alsa2_driver); ++unregister_1: ++ platform_driver_unregister(&bcm2835_alsa1_driver); ++unregister_0: ++ platform_driver_unregister(&bcm2835_alsa0_driver); ++out: ++ return err; ++} ++ ++static void bcm2835_alsa_device_exit(void) ++{ ++ platform_driver_unregister(&bcm2835_alsa0_driver); ++ platform_driver_unregister(&bcm2835_alsa1_driver); ++ platform_driver_unregister(&bcm2835_alsa2_driver); ++ platform_driver_unregister(&bcm2835_alsa3_driver); ++ platform_driver_unregister(&bcm2835_alsa4_driver); ++ platform_driver_unregister(&bcm2835_alsa5_driver); ++ platform_driver_unregister(&bcm2835_alsa6_driver); ++ platform_driver_unregister(&bcm2835_alsa7_driver); ++} ++ ++late_initcall(bcm2835_alsa_device_init); ++module_exit(bcm2835_alsa_device_exit); ++ ++MODULE_AUTHOR("Dom Cobley"); ++MODULE_DESCRIPTION("Alsa driver for BCM2835 chip"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:bcm2835_alsa"); +diff -Nur linux-4.1.13.orig/sound/arm/bcm2835-ctl.c linux-rpi/sound/arm/bcm2835-ctl.c +--- linux-4.1.13.orig/sound/arm/bcm2835-ctl.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/sound/arm/bcm2835-ctl.c 2015-11-29 09:42:41.446997173 +0100 +@@ -0,0 +1,323 @@ ++/***************************************************************************** ++* Copyright 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "bcm2835.h" ++ ++/* volume maximum and minimum in terms of 0.01dB */ ++#define CTRL_VOL_MAX 400 ++#define CTRL_VOL_MIN -10239 /* originally -10240 */ ++ ++ ++static int snd_bcm2835_ctl_info(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_info *uinfo) ++{ ++ audio_info(" ... IN\n"); ++ if (kcontrol->private_value == PCM_PLAYBACK_VOLUME) { ++ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; ++ uinfo->count = 1; ++ uinfo->value.integer.min = CTRL_VOL_MIN; ++ uinfo->value.integer.max = CTRL_VOL_MAX; /* 2303 */ ++ } else if (kcontrol->private_value == PCM_PLAYBACK_MUTE) { ++ uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; ++ uinfo->count = 1; ++ uinfo->value.integer.min = 0; ++ uinfo->value.integer.max = 1; ++ } else if (kcontrol->private_value == PCM_PLAYBACK_DEVICE) { ++ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; ++ uinfo->count = 1; ++ uinfo->value.integer.min = 0; ++ uinfo->value.integer.max = AUDIO_DEST_MAX-1; ++ } ++ audio_info(" ... OUT\n"); ++ return 0; ++} ++ ++/* toggles mute on or off depending on the value of nmute, and returns ++ * 1 if the mute value was changed, otherwise 0 ++ */ ++static int toggle_mute(struct bcm2835_chip *chip, int nmute) ++{ ++ /* if settings are ok, just return 0 */ ++ if(chip->mute == nmute) ++ return 0; ++ ++ /* if the sound is muted then we need to unmute */ ++ if(chip->mute == CTRL_VOL_MUTE) ++ { ++ chip->volume = chip->old_volume; /* copy the old volume back */ ++ audio_info("Unmuting, old_volume = %d, volume = %d ...\n", chip->old_volume, chip->volume); ++ } ++ else /* otherwise we mute */ ++ { ++ chip->old_volume = chip->volume; ++ chip->volume = 26214; /* set volume to minimum level AKA mute */ ++ audio_info("Muting, old_volume = %d, volume = %d ...\n", chip->old_volume, chip->volume); ++ } ++ ++ chip->mute = nmute; ++ return 1; ++} ++ ++static int snd_bcm2835_ctl_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol); ++ ++ BUG_ON(!chip && !(chip->avail_substreams & AVAIL_SUBSTREAMS_MASK)); ++ ++ if (kcontrol->private_value == PCM_PLAYBACK_VOLUME) ++ ucontrol->value.integer.value[0] = chip2alsa(chip->volume); ++ else if (kcontrol->private_value == PCM_PLAYBACK_MUTE) ++ ucontrol->value.integer.value[0] = chip->mute; ++ else if (kcontrol->private_value == PCM_PLAYBACK_DEVICE) ++ ucontrol->value.integer.value[0] = chip->dest; ++ ++ return 0; ++} ++ ++static int snd_bcm2835_ctl_put(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol); ++ int changed = 0; ++ ++ if (kcontrol->private_value == PCM_PLAYBACK_VOLUME) { ++ audio_info("Volume change attempted.. volume = %d new_volume = %d\n", chip->volume, (int)ucontrol->value.integer.value[0]); ++ if (chip->mute == CTRL_VOL_MUTE) { ++ /* changed = toggle_mute(chip, CTRL_VOL_UNMUTE); */ ++ return 1; /* should return 0 to signify no change but the mixer takes this as the opposite sign (no idea why) */ ++ } ++ if (changed ++ || (ucontrol->value.integer.value[0] != chip2alsa(chip->volume))) { ++ ++ chip->volume = alsa2chip(ucontrol->value.integer.value[0]); ++ changed = 1; ++ } ++ ++ } else if (kcontrol->private_value == PCM_PLAYBACK_MUTE) { ++ /* Now implemented */ ++ audio_info(" Mute attempted\n"); ++ changed = toggle_mute(chip, ucontrol->value.integer.value[0]); ++ ++ } else if (kcontrol->private_value == PCM_PLAYBACK_DEVICE) { ++ if (ucontrol->value.integer.value[0] != chip->dest) { ++ chip->dest = ucontrol->value.integer.value[0]; ++ changed = 1; ++ } ++ } ++ ++ if (changed) { ++ if (bcm2835_audio_set_ctls(chip)) ++ printk(KERN_ERR "Failed to set ALSA controls..\n"); ++ } ++ ++ return changed; ++} ++ ++static DECLARE_TLV_DB_SCALE(snd_bcm2835_db_scale, CTRL_VOL_MIN, 1, 1); ++ ++static struct snd_kcontrol_new snd_bcm2835_ctl[] = { ++ { ++ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, ++ .name = "PCM Playback Volume", ++ .index = 0, ++ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, ++ .private_value = PCM_PLAYBACK_VOLUME, ++ .info = snd_bcm2835_ctl_info, ++ .get = snd_bcm2835_ctl_get, ++ .put = snd_bcm2835_ctl_put, ++ .count = 1, ++ .tlv = {.p = snd_bcm2835_db_scale} ++ }, ++ { ++ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, ++ .name = "PCM Playback Switch", ++ .index = 0, ++ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, ++ .private_value = PCM_PLAYBACK_MUTE, ++ .info = snd_bcm2835_ctl_info, ++ .get = snd_bcm2835_ctl_get, ++ .put = snd_bcm2835_ctl_put, ++ .count = 1, ++ }, ++ { ++ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, ++ .name = "PCM Playback Route", ++ .index = 0, ++ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, ++ .private_value = PCM_PLAYBACK_DEVICE, ++ .info = snd_bcm2835_ctl_info, ++ .get = snd_bcm2835_ctl_get, ++ .put = snd_bcm2835_ctl_put, ++ .count = 1, ++ }, ++}; ++ ++static int snd_bcm2835_spdif_default_info(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_info *uinfo) ++{ ++ uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; ++ uinfo->count = 1; ++ return 0; ++} ++ ++static int snd_bcm2835_spdif_default_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol); ++ int i; ++ ++ for (i = 0; i < 4; i++) ++ ucontrol->value.iec958.status[i] = ++ (chip->spdif_status >> (i * 8)) && 0xff; ++ ++ return 0; ++} ++ ++static int snd_bcm2835_spdif_default_put(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol); ++ unsigned int val = 0; ++ int i, change; ++ ++ for (i = 0; i < 4; i++) ++ val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8); ++ ++ change = val != chip->spdif_status; ++ chip->spdif_status = val; ++ ++ return change; ++} ++ ++static int snd_bcm2835_spdif_mask_info(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_info *uinfo) ++{ ++ uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; ++ uinfo->count = 1; ++ return 0; ++} ++ ++static int snd_bcm2835_spdif_mask_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ /* bcm2835 supports only consumer mode and sets all other format flags ++ * automatically. So the only thing left is signalling non-audio ++ * content */ ++ ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO; ++ return 0; ++} ++ ++static int snd_bcm2835_spdif_stream_info(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_info *uinfo) ++{ ++ uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; ++ uinfo->count = 1; ++ return 0; ++} ++ ++static int snd_bcm2835_spdif_stream_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol); ++ int i; ++ ++ for (i = 0; i < 4; i++) ++ ucontrol->value.iec958.status[i] = ++ (chip->spdif_status >> (i * 8)) & 0xff; ++ return 0; ++} ++ ++static int snd_bcm2835_spdif_stream_put(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol); ++ unsigned int val = 0; ++ int i, change; ++ ++ for (i = 0; i < 4; i++) ++ val |= (unsigned int)ucontrol->value.iec958.status[i] << (i * 8); ++ change = val != chip->spdif_status; ++ chip->spdif_status = val; ++ ++ return change; ++} ++ ++static struct snd_kcontrol_new snd_bcm2835_spdif[] = { ++ { ++ .iface = SNDRV_CTL_ELEM_IFACE_PCM, ++ .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), ++ .info = snd_bcm2835_spdif_default_info, ++ .get = snd_bcm2835_spdif_default_get, ++ .put = snd_bcm2835_spdif_default_put ++ }, ++ { ++ .access = SNDRV_CTL_ELEM_ACCESS_READ, ++ .iface = SNDRV_CTL_ELEM_IFACE_PCM, ++ .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK), ++ .info = snd_bcm2835_spdif_mask_info, ++ .get = snd_bcm2835_spdif_mask_get, ++ }, ++ { ++ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | ++ SNDRV_CTL_ELEM_ACCESS_INACTIVE, ++ .iface = SNDRV_CTL_ELEM_IFACE_PCM, ++ .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM), ++ .info = snd_bcm2835_spdif_stream_info, ++ .get = snd_bcm2835_spdif_stream_get, ++ .put = snd_bcm2835_spdif_stream_put, ++ }, ++}; ++ ++int snd_bcm2835_new_ctl(bcm2835_chip_t * chip) ++{ ++ int err; ++ unsigned int idx; ++ ++ strcpy(chip->card->mixername, "Broadcom Mixer"); ++ for (idx = 0; idx < ARRAY_SIZE(snd_bcm2835_ctl); idx++) { ++ err = ++ snd_ctl_add(chip->card, ++ snd_ctl_new1(&snd_bcm2835_ctl[idx], chip)); ++ if (err < 0) ++ return err; ++ } ++ for (idx = 0; idx < ARRAY_SIZE(snd_bcm2835_spdif); idx++) { ++ err = snd_ctl_add(chip->card, ++ snd_ctl_new1(&snd_bcm2835_spdif[idx], chip)); ++ if (err < 0) ++ return err; ++ } ++ return 0; ++} +diff -Nur linux-4.1.13.orig/sound/arm/bcm2835.h linux-rpi/sound/arm/bcm2835.h +--- linux-4.1.13.orig/sound/arm/bcm2835.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/sound/arm/bcm2835.h 2015-11-29 09:42:41.446997173 +0100 +@@ -0,0 +1,167 @@ ++/***************************************************************************** ++* Copyright 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#ifndef __SOUND_ARM_BCM2835_H ++#define __SOUND_ARM_BCM2835_H ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* ++#define AUDIO_DEBUG_ENABLE ++#define AUDIO_VERBOSE_DEBUG_ENABLE ++*/ ++ ++/* Debug macros */ ++ ++#ifdef AUDIO_DEBUG_ENABLE ++#ifdef AUDIO_VERBOSE_DEBUG_ENABLE ++ ++#define audio_debug(fmt, arg...) \ ++ printk(KERN_INFO"%s:%d " fmt, __func__, __LINE__, ##arg) ++ ++#define audio_info(fmt, arg...) \ ++ printk(KERN_INFO"%s:%d " fmt, __func__, __LINE__, ##arg) ++ ++#else ++ ++#define audio_debug(fmt, arg...) ++ ++#define audio_info(fmt, arg...) ++ ++#endif /* AUDIO_VERBOSE_DEBUG_ENABLE */ ++ ++#else ++ ++#define audio_debug(fmt, arg...) ++ ++#define audio_info(fmt, arg...) ++ ++#endif /* AUDIO_DEBUG_ENABLE */ ++ ++#define audio_error(fmt, arg...) \ ++ printk(KERN_ERR"%s:%d " fmt, __func__, __LINE__, ##arg) ++ ++#define audio_warning(fmt, arg...) \ ++ printk(KERN_WARNING"%s:%d " fmt, __func__, __LINE__, ##arg) ++ ++#define audio_alert(fmt, arg...) \ ++ printk(KERN_ALERT"%s:%d " fmt, __func__, __LINE__, ##arg) ++ ++#define MAX_SUBSTREAMS (8) ++#define AVAIL_SUBSTREAMS_MASK (0xff) ++enum { ++ CTRL_VOL_MUTE, ++ CTRL_VOL_UNMUTE ++}; ++ ++/* macros for alsa2chip and chip2alsa, instead of functions */ ++ ++#define alsa2chip(vol) (uint)(-((vol << 8) / 100)) /* convert alsa to chip volume (defined as macro rather than function call) */ ++#define chip2alsa(vol) -((vol * 100) >> 8) /* convert chip to alsa volume */ ++ ++/* Some constants for values .. */ ++typedef enum { ++ AUDIO_DEST_AUTO = 0, ++ AUDIO_DEST_HEADPHONES = 1, ++ AUDIO_DEST_HDMI = 2, ++ AUDIO_DEST_MAX, ++} SND_BCM2835_ROUTE_T; ++ ++typedef enum { ++ PCM_PLAYBACK_VOLUME, ++ PCM_PLAYBACK_MUTE, ++ PCM_PLAYBACK_DEVICE, ++} SND_BCM2835_CTRL_T; ++ ++/* definition of the chip-specific record */ ++typedef struct bcm2835_chip { ++ struct snd_card *card; ++ struct snd_pcm *pcm; ++ struct snd_pcm *pcm_spdif; ++ /* Bitmat for valid reg_base and irq numbers */ ++ uint32_t avail_substreams; ++ struct platform_device *pdev[MAX_SUBSTREAMS]; ++ struct bcm2835_alsa_stream *alsa_stream[MAX_SUBSTREAMS]; ++ ++ int volume; ++ int old_volume; /* stores the volume value whist muted */ ++ int dest; ++ int mute; ++ ++ unsigned int opened; ++ unsigned int spdif_status; ++ struct mutex audio_mutex; ++} bcm2835_chip_t; ++ ++typedef struct bcm2835_alsa_stream { ++ bcm2835_chip_t *chip; ++ struct snd_pcm_substream *substream; ++ struct snd_pcm_indirect pcm_indirect; ++ ++ struct semaphore buffers_update_sem; ++ struct semaphore control_sem; ++ spinlock_t lock; ++ volatile uint32_t control; ++ volatile uint32_t status; ++ ++ int open; ++ int running; ++ int draining; ++ ++ int channels; ++ int params_rate; ++ int pcm_format_width; ++ ++ unsigned int pos; ++ unsigned int buffer_size; ++ unsigned int period_size; ++ ++ uint32_t enable_fifo_irq; ++ irq_handler_t fifo_irq_handler; ++ ++ atomic_t retrieved; ++ struct opaque_AUDIO_INSTANCE_T *instance; ++ struct workqueue_struct *my_wq; ++ int idx; ++} bcm2835_alsa_stream_t; ++ ++int snd_bcm2835_new_ctl(bcm2835_chip_t * chip); ++int snd_bcm2835_new_pcm(bcm2835_chip_t * chip); ++int snd_bcm2835_new_spdif_pcm(bcm2835_chip_t * chip); ++ ++int bcm2835_audio_open(bcm2835_alsa_stream_t * alsa_stream); ++int bcm2835_audio_close(bcm2835_alsa_stream_t * alsa_stream); ++int bcm2835_audio_set_params(bcm2835_alsa_stream_t * alsa_stream, ++ uint32_t channels, uint32_t samplerate, ++ uint32_t bps); ++int bcm2835_audio_setup(bcm2835_alsa_stream_t * alsa_stream); ++int bcm2835_audio_start(bcm2835_alsa_stream_t * alsa_stream); ++int bcm2835_audio_stop(bcm2835_alsa_stream_t * alsa_stream); ++int bcm2835_audio_set_ctls(bcm2835_chip_t * chip); ++int bcm2835_audio_write(bcm2835_alsa_stream_t * alsa_stream, uint32_t count, ++ void *src); ++uint32_t bcm2835_audio_retrieve_buffers(bcm2835_alsa_stream_t * alsa_stream); ++void bcm2835_audio_flush_buffers(bcm2835_alsa_stream_t * alsa_stream); ++void bcm2835_audio_flush_playback_buffers(bcm2835_alsa_stream_t * alsa_stream); ++ ++#endif /* __SOUND_ARM_BCM2835_H */ +diff -Nur linux-4.1.13.orig/sound/arm/bcm2835-pcm.c linux-rpi/sound/arm/bcm2835-pcm.c +--- linux-4.1.13.orig/sound/arm/bcm2835-pcm.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/sound/arm/bcm2835-pcm.c 2015-11-29 09:42:41.446997173 +0100 +@@ -0,0 +1,557 @@ ++/***************************************************************************** ++* Copyright 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#include ++#include ++ ++#include ++ ++#include "bcm2835.h" ++ ++/* hardware definition */ ++static struct snd_pcm_hardware snd_bcm2835_playback_hw = { ++ .info = (SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | ++ SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID), ++ .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, ++ .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, ++ .rate_min = 8000, ++ .rate_max = 48000, ++ .channels_min = 1, ++ .channels_max = 2, ++ .buffer_bytes_max = 128 * 1024, ++ .period_bytes_min = 1 * 1024, ++ .period_bytes_max = 128 * 1024, ++ .periods_min = 1, ++ .periods_max = 128, ++}; ++ ++static struct snd_pcm_hardware snd_bcm2835_playback_spdif_hw = { ++ .info = (SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER | ++ SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID), ++ .formats = SNDRV_PCM_FMTBIT_S16_LE, ++ .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_44100 | ++ SNDRV_PCM_RATE_48000, ++ .rate_min = 44100, ++ .rate_max = 48000, ++ .channels_min = 2, ++ .channels_max = 2, ++ .buffer_bytes_max = 128 * 1024, ++ .period_bytes_min = 1 * 1024, ++ .period_bytes_max = 128 * 1024, ++ .periods_min = 1, ++ .periods_max = 128, ++}; ++ ++static void snd_bcm2835_playback_free(struct snd_pcm_runtime *runtime) ++{ ++ audio_info("Freeing up alsa stream here ..\n"); ++ if (runtime->private_data) ++ kfree(runtime->private_data); ++ runtime->private_data = NULL; ++} ++ ++static irqreturn_t bcm2835_playback_fifo_irq(int irq, void *dev_id) ++{ ++ bcm2835_alsa_stream_t *alsa_stream = (bcm2835_alsa_stream_t *) dev_id; ++ uint32_t consumed = 0; ++ int new_period = 0; ++ ++ audio_info(" .. IN\n"); ++ ++ audio_info("alsa_stream=%p substream=%p\n", alsa_stream, ++ alsa_stream ? alsa_stream->substream : 0); ++ ++ if (alsa_stream->open) ++ consumed = bcm2835_audio_retrieve_buffers(alsa_stream); ++ ++ /* We get called only if playback was triggered, So, the number of buffers we retrieve in ++ * each iteration are the buffers that have been played out already ++ */ ++ ++ if (alsa_stream->period_size) { ++ if ((alsa_stream->pos / alsa_stream->period_size) != ++ ((alsa_stream->pos + consumed) / alsa_stream->period_size)) ++ new_period = 1; ++ } ++ audio_debug("updating pos cur: %d + %d max:%d period_bytes:%d, hw_ptr: %d new_period:%d\n", ++ alsa_stream->pos, ++ consumed, ++ alsa_stream->buffer_size, ++ (int)(alsa_stream->period_size*alsa_stream->substream->runtime->periods), ++ frames_to_bytes(alsa_stream->substream->runtime, alsa_stream->substream->runtime->status->hw_ptr), ++ new_period); ++ if (alsa_stream->buffer_size) { ++ alsa_stream->pos += consumed &~ (1<<30); ++ alsa_stream->pos %= alsa_stream->buffer_size; ++ } ++ ++ if (alsa_stream->substream) { ++ if (new_period) ++ snd_pcm_period_elapsed(alsa_stream->substream); ++ } else { ++ audio_warning(" unexpected NULL substream\n"); ++ } ++ audio_info(" .. OUT\n"); ++ ++ return IRQ_HANDLED; ++} ++ ++/* open callback */ ++static int snd_bcm2835_playback_open_generic( ++ struct snd_pcm_substream *substream, int spdif) ++{ ++ bcm2835_chip_t *chip = snd_pcm_substream_chip(substream); ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ bcm2835_alsa_stream_t *alsa_stream; ++ int idx; ++ int err; ++ ++ audio_info(" .. IN (%d)\n", substream->number); ++ ++ if(mutex_lock_interruptible(&chip->audio_mutex)) ++ { ++ audio_error("Interrupted whilst waiting for lock\n"); ++ return -EINTR; ++ } ++ audio_info("Alsa open (%d)\n", substream->number); ++ idx = substream->number; ++ ++ if (spdif && chip->opened != 0) { ++ err = -EBUSY; ++ goto out; ++ } ++ else if (!spdif && (chip->opened & (1 << idx))) { ++ err = -EBUSY; ++ goto out; ++ } ++ if (idx > MAX_SUBSTREAMS) { ++ audio_error ++ ("substream(%d) device doesn't exist max(%d) substreams allowed\n", ++ idx, MAX_SUBSTREAMS); ++ err = -ENODEV; ++ goto out; ++ } ++ ++ /* Check if we are ready */ ++ if (!(chip->avail_substreams & (1 << idx))) { ++ /* We are not ready yet */ ++ audio_error("substream(%d) device is not ready yet\n", idx); ++ err = -EAGAIN; ++ goto out; ++ } ++ ++ alsa_stream = kzalloc(sizeof(bcm2835_alsa_stream_t), GFP_KERNEL); ++ if (alsa_stream == NULL) { ++ err = -ENOMEM; ++ goto out; ++ } ++ ++ /* Initialise alsa_stream */ ++ alsa_stream->chip = chip; ++ alsa_stream->substream = substream; ++ alsa_stream->idx = idx; ++ ++ sema_init(&alsa_stream->buffers_update_sem, 0); ++ sema_init(&alsa_stream->control_sem, 0); ++ spin_lock_init(&alsa_stream->lock); ++ ++ /* Enabled in start trigger, called on each "fifo irq" after that */ ++ alsa_stream->enable_fifo_irq = 0; ++ alsa_stream->fifo_irq_handler = bcm2835_playback_fifo_irq; ++ ++ err = bcm2835_audio_open(alsa_stream); ++ if (err != 0) { ++ kfree(alsa_stream); ++ goto out; ++ } ++ runtime->private_data = alsa_stream; ++ runtime->private_free = snd_bcm2835_playback_free; ++ if (spdif) { ++ runtime->hw = snd_bcm2835_playback_spdif_hw; ++ } else { ++ /* clear spdif status, as we are not in spdif mode */ ++ chip->spdif_status = 0; ++ runtime->hw = snd_bcm2835_playback_hw; ++ } ++ /* minimum 16 bytes alignment (for vchiq bulk transfers) */ ++ snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, ++ 16); ++ ++ chip->alsa_stream[idx] = alsa_stream; ++ ++ chip->opened |= (1 << idx); ++ alsa_stream->open = 1; ++ alsa_stream->draining = 1; ++ ++out: ++ mutex_unlock(&chip->audio_mutex); ++ ++ audio_info(" .. OUT =%d\n", err); ++ ++ return err; ++} ++ ++static int snd_bcm2835_playback_open(struct snd_pcm_substream *substream) ++{ ++ return snd_bcm2835_playback_open_generic(substream, 0); ++} ++ ++static int snd_bcm2835_playback_spdif_open(struct snd_pcm_substream *substream) ++{ ++ return snd_bcm2835_playback_open_generic(substream, 1); ++} ++ ++/* close callback */ ++static int snd_bcm2835_playback_close(struct snd_pcm_substream *substream) ++{ ++ /* the hardware-specific codes will be here */ ++ ++ bcm2835_chip_t *chip; ++ struct snd_pcm_runtime *runtime; ++ bcm2835_alsa_stream_t *alsa_stream; ++ ++ audio_info(" .. IN\n"); ++ ++ chip = snd_pcm_substream_chip(substream); ++ if(mutex_lock_interruptible(&chip->audio_mutex)) ++ { ++ audio_error("Interrupted whilst waiting for lock\n"); ++ return -EINTR; ++ } ++ runtime = substream->runtime; ++ alsa_stream = runtime->private_data; ++ ++ audio_info("Alsa close\n"); ++ ++ /* ++ * Call stop if it's still running. This happens when app ++ * is force killed and we don't get a stop trigger. ++ */ ++ if (alsa_stream->running) { ++ int err; ++ err = bcm2835_audio_stop(alsa_stream); ++ alsa_stream->running = 0; ++ if (err != 0) ++ audio_error(" Failed to STOP alsa device\n"); ++ } ++ ++ alsa_stream->period_size = 0; ++ alsa_stream->buffer_size = 0; ++ ++ if (alsa_stream->open) { ++ alsa_stream->open = 0; ++ bcm2835_audio_close(alsa_stream); ++ } ++ if (alsa_stream->chip) ++ alsa_stream->chip->alsa_stream[alsa_stream->idx] = NULL; ++ /* ++ * Do not free up alsa_stream here, it will be freed up by ++ * runtime->private_free callback we registered in *_open above ++ */ ++ ++ chip->opened &= ~(1 << substream->number); ++ ++ mutex_unlock(&chip->audio_mutex); ++ audio_info(" .. OUT\n"); ++ ++ return 0; ++} ++ ++/* hw_params callback */ ++static int snd_bcm2835_pcm_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data; ++ int err; ++ ++ audio_info(" .. IN\n"); ++ ++ err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params)); ++ if (err < 0) { ++ audio_error ++ (" pcm_lib_malloc failed to allocated pages for buffers\n"); ++ return err; ++ } ++ ++ alsa_stream->channels = params_channels(params); ++ alsa_stream->params_rate = params_rate(params); ++ alsa_stream->pcm_format_width = snd_pcm_format_width(params_format (params)); ++ audio_info(" .. OUT\n"); ++ ++ return err; ++} ++ ++/* hw_free callback */ ++static int snd_bcm2835_pcm_hw_free(struct snd_pcm_substream *substream) ++{ ++ audio_info(" .. IN\n"); ++ return snd_pcm_lib_free_pages(substream); ++} ++ ++/* prepare callback */ ++static int snd_bcm2835_pcm_prepare(struct snd_pcm_substream *substream) ++{ ++ bcm2835_chip_t *chip = snd_pcm_substream_chip(substream); ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data; ++ int channels; ++ int err; ++ ++ audio_info(" .. IN\n"); ++ ++ /* notify the vchiq that it should enter spdif passthrough mode by ++ * setting channels=0 (see ++ * https://github.com/raspberrypi/linux/issues/528) */ ++ if (chip->spdif_status & IEC958_AES0_NONAUDIO) ++ channels = 0; ++ else ++ channels = alsa_stream->channels; ++ ++ err = bcm2835_audio_set_params(alsa_stream, channels, ++ alsa_stream->params_rate, ++ alsa_stream->pcm_format_width); ++ if (err < 0) { ++ audio_error(" error setting hw params\n"); ++ } ++ ++ bcm2835_audio_setup(alsa_stream); ++ ++ /* in preparation of the stream, set the controls (volume level) of the stream */ ++ bcm2835_audio_set_ctls(alsa_stream->chip); ++ ++ ++ memset(&alsa_stream->pcm_indirect, 0, sizeof(alsa_stream->pcm_indirect)); ++ ++ alsa_stream->pcm_indirect.hw_buffer_size = ++ alsa_stream->pcm_indirect.sw_buffer_size = ++ snd_pcm_lib_buffer_bytes(substream); ++ ++ alsa_stream->buffer_size = snd_pcm_lib_buffer_bytes(substream); ++ alsa_stream->period_size = snd_pcm_lib_period_bytes(substream); ++ alsa_stream->pos = 0; ++ ++ audio_debug("buffer_size=%d, period_size=%d pos=%d frame_bits=%d\n", ++ alsa_stream->buffer_size, alsa_stream->period_size, ++ alsa_stream->pos, runtime->frame_bits); ++ ++ audio_info(" .. OUT\n"); ++ return 0; ++} ++ ++static void snd_bcm2835_pcm_transfer(struct snd_pcm_substream *substream, ++ struct snd_pcm_indirect *rec, size_t bytes) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data; ++ void *src = (void *)(substream->runtime->dma_area + rec->sw_data); ++ int err; ++ ++ err = bcm2835_audio_write(alsa_stream, bytes, src); ++ if (err) ++ audio_error(" Failed to transfer to alsa device (%d)\n", err); ++ ++} ++ ++static int snd_bcm2835_pcm_ack(struct snd_pcm_substream *substream) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data; ++ struct snd_pcm_indirect *pcm_indirect = &alsa_stream->pcm_indirect; ++ ++ pcm_indirect->hw_queue_size = runtime->hw.buffer_bytes_max; ++ snd_pcm_indirect_playback_transfer(substream, pcm_indirect, ++ snd_bcm2835_pcm_transfer); ++ return 0; ++} ++ ++/* trigger callback */ ++static int snd_bcm2835_pcm_trigger(struct snd_pcm_substream *substream, int cmd) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data; ++ int err = 0; ++ ++ audio_info(" .. IN\n"); ++ ++ switch (cmd) { ++ case SNDRV_PCM_TRIGGER_START: ++ audio_debug("bcm2835_AUDIO_TRIGGER_START running=%d\n", ++ alsa_stream->running); ++ if (!alsa_stream->running) { ++ err = bcm2835_audio_start(alsa_stream); ++ if (err == 0) { ++ alsa_stream->pcm_indirect.hw_io = ++ alsa_stream->pcm_indirect.hw_data = ++ bytes_to_frames(runtime, ++ alsa_stream->pos); ++ substream->ops->ack(substream); ++ alsa_stream->running = 1; ++ alsa_stream->draining = 1; ++ } else { ++ audio_error(" Failed to START alsa device (%d)\n", err); ++ } ++ } ++ break; ++ case SNDRV_PCM_TRIGGER_STOP: ++ audio_debug ++ ("bcm2835_AUDIO_TRIGGER_STOP running=%d draining=%d\n", ++ alsa_stream->running, runtime->status->state == SNDRV_PCM_STATE_DRAINING); ++ if (runtime->status->state == SNDRV_PCM_STATE_DRAINING) { ++ audio_info("DRAINING\n"); ++ alsa_stream->draining = 1; ++ } else { ++ audio_info("DROPPING\n"); ++ alsa_stream->draining = 0; ++ } ++ if (alsa_stream->running) { ++ err = bcm2835_audio_stop(alsa_stream); ++ if (err != 0) ++ audio_error(" Failed to STOP alsa device (%d)\n", err); ++ alsa_stream->running = 0; ++ } ++ break; ++ default: ++ err = -EINVAL; ++ } ++ ++ audio_info(" .. OUT\n"); ++ return err; ++} ++ ++/* pointer callback */ ++static snd_pcm_uframes_t ++snd_bcm2835_pcm_pointer(struct snd_pcm_substream *substream) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data; ++ ++ audio_info(" .. IN\n"); ++ ++ audio_debug("pcm_pointer... (%d) hwptr=%d appl=%d pos=%d\n", 0, ++ frames_to_bytes(runtime, runtime->status->hw_ptr), ++ frames_to_bytes(runtime, runtime->control->appl_ptr), ++ alsa_stream->pos); ++ ++ audio_info(" .. OUT\n"); ++ return snd_pcm_indirect_playback_pointer(substream, ++ &alsa_stream->pcm_indirect, ++ alsa_stream->pos); ++} ++ ++static int snd_bcm2835_pcm_lib_ioctl(struct snd_pcm_substream *substream, ++ unsigned int cmd, void *arg) ++{ ++ int ret = snd_pcm_lib_ioctl(substream, cmd, arg); ++ audio_info(" .. substream=%p, cmd=%d, arg=%p (%x) ret=%d\n", substream, ++ cmd, arg, arg ? *(unsigned *)arg : 0, ret); ++ return ret; ++} ++ ++/* operators */ ++static struct snd_pcm_ops snd_bcm2835_playback_ops = { ++ .open = snd_bcm2835_playback_open, ++ .close = snd_bcm2835_playback_close, ++ .ioctl = snd_bcm2835_pcm_lib_ioctl, ++ .hw_params = snd_bcm2835_pcm_hw_params, ++ .hw_free = snd_bcm2835_pcm_hw_free, ++ .prepare = snd_bcm2835_pcm_prepare, ++ .trigger = snd_bcm2835_pcm_trigger, ++ .pointer = snd_bcm2835_pcm_pointer, ++ .ack = snd_bcm2835_pcm_ack, ++}; ++ ++static struct snd_pcm_ops snd_bcm2835_playback_spdif_ops = { ++ .open = snd_bcm2835_playback_spdif_open, ++ .close = snd_bcm2835_playback_close, ++ .ioctl = snd_bcm2835_pcm_lib_ioctl, ++ .hw_params = snd_bcm2835_pcm_hw_params, ++ .hw_free = snd_bcm2835_pcm_hw_free, ++ .prepare = snd_bcm2835_pcm_prepare, ++ .trigger = snd_bcm2835_pcm_trigger, ++ .pointer = snd_bcm2835_pcm_pointer, ++ .ack = snd_bcm2835_pcm_ack, ++}; ++ ++/* create a pcm device */ ++int snd_bcm2835_new_pcm(bcm2835_chip_t * chip) ++{ ++ struct snd_pcm *pcm; ++ int err; ++ ++ audio_info(" .. IN\n"); ++ mutex_init(&chip->audio_mutex); ++ if(mutex_lock_interruptible(&chip->audio_mutex)) ++ { ++ audio_error("Interrupted whilst waiting for lock\n"); ++ return -EINTR; ++ } ++ err = ++ snd_pcm_new(chip->card, "bcm2835 ALSA", 0, MAX_SUBSTREAMS, 0, &pcm); ++ if (err < 0) ++ goto out; ++ pcm->private_data = chip; ++ strcpy(pcm->name, "bcm2835 ALSA"); ++ chip->pcm = pcm; ++ chip->dest = AUDIO_DEST_AUTO; ++ chip->volume = alsa2chip(0); ++ chip->mute = CTRL_VOL_UNMUTE; /*disable mute on startup */ ++ /* set operators */ ++ snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, ++ &snd_bcm2835_playback_ops); ++ ++ /* pre-allocation of buffers */ ++ /* NOTE: this may fail */ ++ snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS, ++ snd_dma_continuous_data ++ (GFP_KERNEL), 64 * 1024, ++ 64 * 1024); ++ ++out: ++ mutex_unlock(&chip->audio_mutex); ++ audio_info(" .. OUT\n"); ++ ++ return 0; ++} ++ ++int snd_bcm2835_new_spdif_pcm(bcm2835_chip_t * chip) ++{ ++ struct snd_pcm *pcm; ++ int err; ++ ++ audio_info(" .. IN\n"); ++ if(mutex_lock_interruptible(&chip->audio_mutex)) ++ { ++ audio_error("Interrupted whilst waiting for lock\n"); ++ return -EINTR; ++ } ++ err = snd_pcm_new(chip->card, "bcm2835 ALSA", 1, 1, 0, &pcm); ++ if (err < 0) ++ goto out; ++ ++ pcm->private_data = chip; ++ strcpy(pcm->name, "bcm2835 IEC958/HDMI"); ++ chip->pcm_spdif = pcm; ++ snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, ++ &snd_bcm2835_playback_spdif_ops); ++ ++ snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS, ++ snd_dma_continuous_data (GFP_KERNEL), ++ 64 * 1024, 64 * 1024); ++out: ++ mutex_unlock(&chip->audio_mutex); ++ audio_info(" .. OUT\n"); ++ ++ return 0; ++} +diff -Nur linux-4.1.13.orig/sound/arm/bcm2835-vchiq.c linux-rpi/sound/arm/bcm2835-vchiq.c +--- linux-4.1.13.orig/sound/arm/bcm2835-vchiq.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/sound/arm/bcm2835-vchiq.c 2015-11-29 09:42:41.446997173 +0100 +@@ -0,0 +1,902 @@ ++/***************************************************************************** ++* Copyright 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "bcm2835.h" ++ ++/* ---- Include Files -------------------------------------------------------- */ ++ ++#include "interface/vchi/vchi.h" ++#include "vc_vchi_audioserv_defs.h" ++ ++/* ---- Private Constants and Types ------------------------------------------ */ ++ ++#define BCM2835_AUDIO_STOP 0 ++#define BCM2835_AUDIO_START 1 ++#define BCM2835_AUDIO_WRITE 2 ++ ++/* Logging macros (for remapping to other logging mechanisms, i.e., printf) */ ++#ifdef AUDIO_DEBUG_ENABLE ++ #define LOG_ERR( fmt, arg... ) pr_err( "%s:%d " fmt, __func__, __LINE__, ##arg) ++ #define LOG_WARN( fmt, arg... ) pr_info( "%s:%d " fmt, __func__, __LINE__, ##arg) ++ #define LOG_INFO( fmt, arg... ) pr_info( "%s:%d " fmt, __func__, __LINE__, ##arg) ++ #define LOG_DBG( fmt, arg... ) pr_info( "%s:%d " fmt, __func__, __LINE__, ##arg) ++#else ++ #define LOG_ERR( fmt, arg... ) pr_err( "%s:%d " fmt, __func__, __LINE__, ##arg) ++ #define LOG_WARN( fmt, arg... ) ++ #define LOG_INFO( fmt, arg... ) ++ #define LOG_DBG( fmt, arg... ) ++#endif ++ ++typedef struct opaque_AUDIO_INSTANCE_T { ++ uint32_t num_connections; ++ VCHI_SERVICE_HANDLE_T vchi_handle[VCHI_MAX_NUM_CONNECTIONS]; ++ struct completion msg_avail_comp; ++ struct mutex vchi_mutex; ++ bcm2835_alsa_stream_t *alsa_stream; ++ int32_t result; ++ short peer_version; ++} AUDIO_INSTANCE_T; ++ ++bool force_bulk = false; ++ ++/* ---- Private Variables ---------------------------------------------------- */ ++ ++/* ---- Private Function Prototypes ------------------------------------------ */ ++ ++/* ---- Private Functions ---------------------------------------------------- */ ++ ++static int bcm2835_audio_stop_worker(bcm2835_alsa_stream_t * alsa_stream); ++static int bcm2835_audio_start_worker(bcm2835_alsa_stream_t * alsa_stream); ++static int bcm2835_audio_write_worker(bcm2835_alsa_stream_t *alsa_stream, ++ uint32_t count, void *src); ++ ++typedef struct { ++ struct work_struct my_work; ++ bcm2835_alsa_stream_t *alsa_stream; ++ int cmd; ++ void *src; ++ uint32_t count; ++} my_work_t; ++ ++static void my_wq_function(struct work_struct *work) ++{ ++ my_work_t *w = (my_work_t *) work; ++ int ret = -9; ++ LOG_DBG(" .. IN %p:%d\n", w->alsa_stream, w->cmd); ++ switch (w->cmd) { ++ case BCM2835_AUDIO_START: ++ ret = bcm2835_audio_start_worker(w->alsa_stream); ++ break; ++ case BCM2835_AUDIO_STOP: ++ ret = bcm2835_audio_stop_worker(w->alsa_stream); ++ break; ++ case BCM2835_AUDIO_WRITE: ++ ret = bcm2835_audio_write_worker(w->alsa_stream, w->count, ++ w->src); ++ break; ++ default: ++ LOG_ERR(" Unexpected work: %p:%d\n", w->alsa_stream, w->cmd); ++ break; ++ } ++ kfree((void *)work); ++ LOG_DBG(" .. OUT %d\n", ret); ++} ++ ++int bcm2835_audio_start(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ int ret = -1; ++ LOG_DBG(" .. IN\n"); ++ if (alsa_stream->my_wq) { ++ my_work_t *work = kmalloc(sizeof(my_work_t), GFP_ATOMIC); ++ /*--- Queue some work (item 1) ---*/ ++ if (work) { ++ INIT_WORK((struct work_struct *)work, my_wq_function); ++ work->alsa_stream = alsa_stream; ++ work->cmd = BCM2835_AUDIO_START; ++ if (queue_work ++ (alsa_stream->my_wq, (struct work_struct *)work)) ++ ret = 0; ++ } else ++ LOG_ERR(" .. Error: NULL work kmalloc\n"); ++ } ++ LOG_DBG(" .. OUT %d\n", ret); ++ return ret; ++} ++ ++int bcm2835_audio_stop(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ int ret = -1; ++ LOG_DBG(" .. IN\n"); ++ if (alsa_stream->my_wq) { ++ my_work_t *work = kmalloc(sizeof(my_work_t), GFP_ATOMIC); ++ /*--- Queue some work (item 1) ---*/ ++ if (work) { ++ INIT_WORK((struct work_struct *)work, my_wq_function); ++ work->alsa_stream = alsa_stream; ++ work->cmd = BCM2835_AUDIO_STOP; ++ if (queue_work ++ (alsa_stream->my_wq, (struct work_struct *)work)) ++ ret = 0; ++ } else ++ LOG_ERR(" .. Error: NULL work kmalloc\n"); ++ } ++ LOG_DBG(" .. OUT %d\n", ret); ++ return ret; ++} ++ ++int bcm2835_audio_write(bcm2835_alsa_stream_t *alsa_stream, ++ uint32_t count, void *src) ++{ ++ int ret = -1; ++ LOG_DBG(" .. IN\n"); ++ if (alsa_stream->my_wq) { ++ my_work_t *work = kmalloc(sizeof(my_work_t), GFP_ATOMIC); ++ /*--- Queue some work (item 1) ---*/ ++ if (work) { ++ INIT_WORK((struct work_struct *)work, my_wq_function); ++ work->alsa_stream = alsa_stream; ++ work->cmd = BCM2835_AUDIO_WRITE; ++ work->src = src; ++ work->count = count; ++ if (queue_work ++ (alsa_stream->my_wq, (struct work_struct *)work)) ++ ret = 0; ++ } else ++ LOG_ERR(" .. Error: NULL work kmalloc\n"); ++ } ++ LOG_DBG(" .. OUT %d\n", ret); ++ return ret; ++} ++ ++void my_workqueue_init(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ alsa_stream->my_wq = alloc_workqueue("my_queue", WQ_HIGHPRI, 1); ++ return; ++} ++ ++void my_workqueue_quit(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ if (alsa_stream->my_wq) { ++ flush_workqueue(alsa_stream->my_wq); ++ destroy_workqueue(alsa_stream->my_wq); ++ alsa_stream->my_wq = NULL; ++ } ++ return; ++} ++ ++static void audio_vchi_callback(void *param, ++ const VCHI_CALLBACK_REASON_T reason, ++ void *msg_handle) ++{ ++ AUDIO_INSTANCE_T *instance = (AUDIO_INSTANCE_T *) param; ++ int32_t status; ++ int32_t msg_len; ++ VC_AUDIO_MSG_T m; ++ LOG_DBG(" .. IN instance=%p, handle=%p, alsa=%p, reason=%d, handle=%p\n", ++ instance, instance ? instance->vchi_handle[0] : NULL, instance ? instance->alsa_stream : NULL, reason, msg_handle); ++ ++ if (reason != VCHI_CALLBACK_MSG_AVAILABLE) { ++ return; ++ } ++ if (!instance) { ++ LOG_ERR(" .. instance is null\n"); ++ BUG(); ++ return; ++ } ++ if (!instance->vchi_handle[0]) { ++ LOG_ERR(" .. instance->vchi_handle[0] is null\n"); ++ BUG(); ++ return; ++ } ++ status = vchi_msg_dequeue(instance->vchi_handle[0], ++ &m, sizeof m, &msg_len, VCHI_FLAGS_NONE); ++ if (m.type == VC_AUDIO_MSG_TYPE_RESULT) { ++ LOG_DBG ++ (" .. instance=%p, m.type=VC_AUDIO_MSG_TYPE_RESULT, success=%d\n", ++ instance, m.u.result.success); ++ instance->result = m.u.result.success; ++ complete(&instance->msg_avail_comp); ++ } else if (m.type == VC_AUDIO_MSG_TYPE_COMPLETE) { ++ bcm2835_alsa_stream_t *alsa_stream = instance->alsa_stream; ++ irq_handler_t callback = (irq_handler_t) m.u.complete.callback; ++ LOG_DBG ++ (" .. instance=%p, m.type=VC_AUDIO_MSG_TYPE_COMPLETE, complete=%d\n", ++ instance, m.u.complete.count); ++ if (alsa_stream && callback) { ++ atomic_add(m.u.complete.count, &alsa_stream->retrieved); ++ callback(0, alsa_stream); ++ } else { ++ LOG_ERR(" .. unexpected alsa_stream=%p, callback=%p\n", ++ alsa_stream, callback); ++ } ++ } else { ++ LOG_ERR(" .. unexpected m.type=%d\n", m.type); ++ } ++ LOG_DBG(" .. OUT\n"); ++} ++ ++static AUDIO_INSTANCE_T *vc_vchi_audio_init(VCHI_INSTANCE_T vchi_instance, ++ VCHI_CONNECTION_T ** ++ vchi_connections, ++ uint32_t num_connections) ++{ ++ uint32_t i; ++ AUDIO_INSTANCE_T *instance; ++ int status; ++ ++ LOG_DBG("%s: start", __func__); ++ ++ if (num_connections > VCHI_MAX_NUM_CONNECTIONS) { ++ LOG_ERR("%s: unsupported number of connections %u (max=%u)\n", ++ __func__, num_connections, VCHI_MAX_NUM_CONNECTIONS); ++ ++ return NULL; ++ } ++ /* Allocate memory for this instance */ ++ instance = kmalloc(sizeof(*instance), GFP_KERNEL); ++ if (!instance) ++ return NULL; ++ ++ memset(instance, 0, sizeof(*instance)); ++ instance->num_connections = num_connections; ++ ++ /* Create a lock for exclusive, serialized VCHI connection access */ ++ mutex_init(&instance->vchi_mutex); ++ /* Open the VCHI service connections */ ++ for (i = 0; i < num_connections; i++) { ++ SERVICE_CREATION_T params = { ++ VCHI_VERSION_EX(VC_AUDIOSERV_VER, VC_AUDIOSERV_MIN_VER), ++ VC_AUDIO_SERVER_NAME, // 4cc service code ++ vchi_connections[i], // passed in fn pointers ++ 0, // rx fifo size (unused) ++ 0, // tx fifo size (unused) ++ audio_vchi_callback, // service callback ++ instance, // service callback parameter ++ 1, //TODO: remove VCOS_FALSE, // unaligned bulk recieves ++ 1, //TODO: remove VCOS_FALSE, // unaligned bulk transmits ++ 0 // want crc check on bulk transfers ++ }; ++ ++ LOG_DBG("%s: about to open %i\n", __func__, i); ++ status = vchi_service_open(vchi_instance, ¶ms, ++ &instance->vchi_handle[i]); ++ LOG_DBG("%s: opened %i: %p=%d\n", __func__, i, instance->vchi_handle[i], status); ++ if (status) { ++ LOG_ERR ++ ("%s: failed to open VCHI service connection (status=%d)\n", ++ __func__, status); ++ ++ goto err_close_services; ++ } ++ /* Finished with the service for now */ ++ vchi_service_release(instance->vchi_handle[i]); ++ } ++ ++ LOG_DBG("%s: okay\n", __func__); ++ return instance; ++ ++err_close_services: ++ for (i = 0; i < instance->num_connections; i++) { ++ LOG_ERR("%s: closing %i: %p\n", __func__, i, instance->vchi_handle[i]); ++ if (instance->vchi_handle[i]) ++ vchi_service_close(instance->vchi_handle[i]); ++ } ++ ++ kfree(instance); ++ LOG_ERR("%s: error\n", __func__); ++ ++ return NULL; ++} ++ ++static int32_t vc_vchi_audio_deinit(AUDIO_INSTANCE_T * instance) ++{ ++ uint32_t i; ++ ++ LOG_DBG(" .. IN\n"); ++ ++ if (instance == NULL) { ++ LOG_ERR("%s: invalid handle %p\n", __func__, instance); ++ ++ return -1; ++ } ++ ++ LOG_DBG(" .. about to lock (%d)\n", instance->num_connections); ++ if(mutex_lock_interruptible(&instance->vchi_mutex)) ++ { ++ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections); ++ return -EINTR; ++ } ++ ++ /* Close all VCHI service connections */ ++ for (i = 0; i < instance->num_connections; i++) { ++ int32_t success; ++ LOG_DBG(" .. %i:closing %p\n", i, instance->vchi_handle[i]); ++ vchi_service_use(instance->vchi_handle[i]); ++ ++ success = vchi_service_close(instance->vchi_handle[i]); ++ if (success != 0) { ++ LOG_DBG ++ ("%s: failed to close VCHI service connection (status=%d)\n", ++ __func__, success); ++ } ++ } ++ ++ mutex_unlock(&instance->vchi_mutex); ++ ++ kfree(instance); ++ ++ LOG_DBG(" .. OUT\n"); ++ ++ return 0; ++} ++ ++static int bcm2835_audio_open_connection(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ static VCHI_INSTANCE_T vchi_instance; ++ static VCHI_CONNECTION_T *vchi_connection; ++ static int initted; ++ AUDIO_INSTANCE_T *instance = alsa_stream->instance; ++ int ret; ++ LOG_DBG(" .. IN\n"); ++ ++ LOG_INFO("%s: start\n", __func__); ++ BUG_ON(instance); ++ if (instance) { ++ LOG_ERR("%s: VCHI instance already open (%p)\n", ++ __func__, instance); ++ instance->alsa_stream = alsa_stream; ++ alsa_stream->instance = instance; ++ ret = 0; // xxx todo -1; ++ goto err_free_mem; ++ } ++ ++ /* Initialize and create a VCHI connection */ ++ if (!initted) { ++ ret = vchi_initialise(&vchi_instance); ++ if (ret != 0) { ++ LOG_ERR("%s: failed to initialise VCHI instance (ret=%d)\n", ++ __func__, ret); ++ ++ ret = -EIO; ++ goto err_free_mem; ++ } ++ ret = vchi_connect(NULL, 0, vchi_instance); ++ if (ret != 0) { ++ LOG_ERR("%s: failed to connect VCHI instance (ret=%d)\n", ++ __func__, ret); ++ ++ ret = -EIO; ++ goto err_free_mem; ++ } ++ initted = 1; ++ } ++ ++ /* Initialize an instance of the audio service */ ++ instance = vc_vchi_audio_init(vchi_instance, &vchi_connection, 1); ++ ++ if (instance == NULL) { ++ LOG_ERR("%s: failed to initialize audio service\n", __func__); ++ ++ ret = -EPERM; ++ goto err_free_mem; ++ } ++ ++ instance->alsa_stream = alsa_stream; ++ alsa_stream->instance = instance; ++ ++ LOG_DBG(" success !\n"); ++err_free_mem: ++ LOG_DBG(" .. OUT\n"); ++ ++ return ret; ++} ++ ++int bcm2835_audio_open(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ AUDIO_INSTANCE_T *instance; ++ VC_AUDIO_MSG_T m; ++ int32_t success; ++ int ret; ++ LOG_DBG(" .. IN\n"); ++ ++ my_workqueue_init(alsa_stream); ++ ++ ret = bcm2835_audio_open_connection(alsa_stream); ++ if (ret != 0) { ++ ret = -1; ++ goto exit; ++ } ++ instance = alsa_stream->instance; ++ LOG_DBG(" instance (%p)\n", instance); ++ ++ if(mutex_lock_interruptible(&instance->vchi_mutex)) ++ { ++ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections); ++ return -EINTR; ++ } ++ vchi_service_use(instance->vchi_handle[0]); ++ ++ m.type = VC_AUDIO_MSG_TYPE_OPEN; ++ ++ /* Send the message to the videocore */ ++ success = vchi_msg_queue(instance->vchi_handle[0], ++ &m, sizeof m, ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); ++ ++ if (success != 0) { ++ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n", ++ __func__, success); ++ ++ ret = -1; ++ goto unlock; ++ } ++ ++ ret = 0; ++ ++unlock: ++ vchi_service_release(instance->vchi_handle[0]); ++ mutex_unlock(&instance->vchi_mutex); ++exit: ++ LOG_DBG(" .. OUT\n"); ++ return ret; ++} ++ ++static int bcm2835_audio_set_ctls_chan(bcm2835_alsa_stream_t * alsa_stream, ++ bcm2835_chip_t * chip) ++{ ++ VC_AUDIO_MSG_T m; ++ AUDIO_INSTANCE_T *instance = alsa_stream->instance; ++ int32_t success; ++ int ret; ++ LOG_DBG(" .. IN\n"); ++ ++ LOG_INFO ++ (" Setting ALSA dest(%d), volume(%d)\n", chip->dest, chip->volume); ++ ++ if(mutex_lock_interruptible(&instance->vchi_mutex)) ++ { ++ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections); ++ return -EINTR; ++ } ++ vchi_service_use(instance->vchi_handle[0]); ++ ++ instance->result = -1; ++ ++ m.type = VC_AUDIO_MSG_TYPE_CONTROL; ++ m.u.control.dest = chip->dest; ++ m.u.control.volume = chip->volume; ++ ++ /* Create the message available completion */ ++ init_completion(&instance->msg_avail_comp); ++ ++ /* Send the message to the videocore */ ++ success = vchi_msg_queue(instance->vchi_handle[0], ++ &m, sizeof m, ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); ++ ++ if (success != 0) { ++ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n", ++ __func__, success); ++ ++ ret = -1; ++ goto unlock; ++ } ++ ++ /* We are expecting a reply from the videocore */ ++ ret = wait_for_completion_interruptible(&instance->msg_avail_comp); ++ if (ret) { ++ LOG_DBG("%s: failed on waiting for event (status=%d)\n", ++ __func__, success); ++ goto unlock; ++ } ++ ++ if (instance->result != 0) { ++ LOG_ERR("%s: result=%d\n", __func__, instance->result); ++ ++ ret = -1; ++ goto unlock; ++ } ++ ++ ret = 0; ++ ++unlock: ++ vchi_service_release(instance->vchi_handle[0]); ++ mutex_unlock(&instance->vchi_mutex); ++ ++ LOG_DBG(" .. OUT\n"); ++ return ret; ++} ++ ++int bcm2835_audio_set_ctls(bcm2835_chip_t * chip) ++{ ++ int i; ++ int ret = 0; ++ LOG_DBG(" .. IN\n"); ++ LOG_DBG(" Setting ALSA dest(%d), volume(%d)\n", chip->dest, chip->volume); ++ ++ /* change ctls for all substreams */ ++ for (i = 0; i < MAX_SUBSTREAMS; i++) { ++ if (chip->avail_substreams & (1 << i)) { ++ if (!chip->alsa_stream[i]) ++ { ++ LOG_DBG(" No ALSA stream available?! %i:%p (%x)\n", i, chip->alsa_stream[i], chip->avail_substreams); ++ ret = 0; ++ } ++ else if (bcm2835_audio_set_ctls_chan /* returns 0 on success */ ++ (chip->alsa_stream[i], chip) != 0) ++ { ++ LOG_ERR("Couldn't set the controls for stream %d\n", i); ++ ret = -1; ++ } ++ else LOG_DBG(" Controls set for stream %d\n", i); ++ } ++ } ++ LOG_DBG(" .. OUT ret=%d\n", ret); ++ return ret; ++} ++ ++int bcm2835_audio_set_params(bcm2835_alsa_stream_t * alsa_stream, ++ uint32_t channels, uint32_t samplerate, ++ uint32_t bps) ++{ ++ VC_AUDIO_MSG_T m; ++ AUDIO_INSTANCE_T *instance = alsa_stream->instance; ++ int32_t success; ++ int ret; ++ LOG_DBG(" .. IN\n"); ++ ++ LOG_INFO ++ (" Setting ALSA channels(%d), samplerate(%d), bits-per-sample(%d)\n", ++ channels, samplerate, bps); ++ ++ /* resend ctls - alsa_stream may not have been open when first send */ ++ ret = bcm2835_audio_set_ctls_chan(alsa_stream, alsa_stream->chip); ++ if (ret != 0) { ++ LOG_ERR(" Alsa controls not supported\n"); ++ return -EINVAL; ++ } ++ ++ if(mutex_lock_interruptible(&instance->vchi_mutex)) ++ { ++ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections); ++ return -EINTR; ++ } ++ vchi_service_use(instance->vchi_handle[0]); ++ ++ instance->result = -1; ++ ++ m.type = VC_AUDIO_MSG_TYPE_CONFIG; ++ m.u.config.channels = channels; ++ m.u.config.samplerate = samplerate; ++ m.u.config.bps = bps; ++ ++ /* Create the message available completion */ ++ init_completion(&instance->msg_avail_comp); ++ ++ /* Send the message to the videocore */ ++ success = vchi_msg_queue(instance->vchi_handle[0], ++ &m, sizeof m, ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); ++ ++ if (success != 0) { ++ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n", ++ __func__, success); ++ ++ ret = -1; ++ goto unlock; ++ } ++ ++ /* We are expecting a reply from the videocore */ ++ ret = wait_for_completion_interruptible(&instance->msg_avail_comp); ++ if (ret) { ++ LOG_DBG("%s: failed on waiting for event (status=%d)\n", ++ __func__, success); ++ goto unlock; ++ } ++ ++ if (instance->result != 0) { ++ LOG_ERR("%s: result=%d", __func__, instance->result); ++ ++ ret = -1; ++ goto unlock; ++ } ++ ++ ret = 0; ++ ++unlock: ++ vchi_service_release(instance->vchi_handle[0]); ++ mutex_unlock(&instance->vchi_mutex); ++ ++ LOG_DBG(" .. OUT\n"); ++ return ret; ++} ++ ++int bcm2835_audio_setup(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ LOG_DBG(" .. IN\n"); ++ ++ LOG_DBG(" .. OUT\n"); ++ ++ return 0; ++} ++ ++static int bcm2835_audio_start_worker(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ VC_AUDIO_MSG_T m; ++ AUDIO_INSTANCE_T *instance = alsa_stream->instance; ++ int32_t success; ++ int ret; ++ LOG_DBG(" .. IN\n"); ++ ++ if(mutex_lock_interruptible(&instance->vchi_mutex)) ++ { ++ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections); ++ return -EINTR; ++ } ++ vchi_service_use(instance->vchi_handle[0]); ++ ++ m.type = VC_AUDIO_MSG_TYPE_START; ++ ++ /* Send the message to the videocore */ ++ success = vchi_msg_queue(instance->vchi_handle[0], ++ &m, sizeof m, ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); ++ ++ if (success != 0) { ++ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n", ++ __func__, success); ++ ++ ret = -1; ++ goto unlock; ++ } ++ ++ ret = 0; ++ ++unlock: ++ vchi_service_release(instance->vchi_handle[0]); ++ mutex_unlock(&instance->vchi_mutex); ++ LOG_DBG(" .. OUT\n"); ++ return ret; ++} ++ ++static int bcm2835_audio_stop_worker(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ VC_AUDIO_MSG_T m; ++ AUDIO_INSTANCE_T *instance = alsa_stream->instance; ++ int32_t success; ++ int ret; ++ LOG_DBG(" .. IN\n"); ++ ++ if(mutex_lock_interruptible(&instance->vchi_mutex)) ++ { ++ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections); ++ return -EINTR; ++ } ++ vchi_service_use(instance->vchi_handle[0]); ++ ++ m.type = VC_AUDIO_MSG_TYPE_STOP; ++ m.u.stop.draining = alsa_stream->draining; ++ ++ /* Send the message to the videocore */ ++ success = vchi_msg_queue(instance->vchi_handle[0], ++ &m, sizeof m, ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); ++ ++ if (success != 0) { ++ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n", ++ __func__, success); ++ ++ ret = -1; ++ goto unlock; ++ } ++ ++ ret = 0; ++ ++unlock: ++ vchi_service_release(instance->vchi_handle[0]); ++ mutex_unlock(&instance->vchi_mutex); ++ LOG_DBG(" .. OUT\n"); ++ return ret; ++} ++ ++int bcm2835_audio_close(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ VC_AUDIO_MSG_T m; ++ AUDIO_INSTANCE_T *instance = alsa_stream->instance; ++ int32_t success; ++ int ret; ++ LOG_DBG(" .. IN\n"); ++ ++ my_workqueue_quit(alsa_stream); ++ ++ if(mutex_lock_interruptible(&instance->vchi_mutex)) ++ { ++ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections); ++ return -EINTR; ++ } ++ vchi_service_use(instance->vchi_handle[0]); ++ ++ m.type = VC_AUDIO_MSG_TYPE_CLOSE; ++ ++ /* Create the message available completion */ ++ init_completion(&instance->msg_avail_comp); ++ ++ /* Send the message to the videocore */ ++ success = vchi_msg_queue(instance->vchi_handle[0], ++ &m, sizeof m, ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); ++ ++ if (success != 0) { ++ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n", ++ __func__, success); ++ ret = -1; ++ goto unlock; ++ } ++ ++ ret = wait_for_completion_interruptible(&instance->msg_avail_comp); ++ if (ret) { ++ LOG_DBG("%s: failed on waiting for event (status=%d)\n", ++ __func__, success); ++ goto unlock; ++ } ++ if (instance->result != 0) { ++ LOG_ERR("%s: failed result (status=%d)\n", ++ __func__, instance->result); ++ ++ ret = -1; ++ goto unlock; ++ } ++ ++ ret = 0; ++ ++unlock: ++ vchi_service_release(instance->vchi_handle[0]); ++ mutex_unlock(&instance->vchi_mutex); ++ ++ /* Stop the audio service */ ++ if (instance) { ++ vc_vchi_audio_deinit(instance); ++ alsa_stream->instance = NULL; ++ } ++ LOG_DBG(" .. OUT\n"); ++ return ret; ++} ++ ++int bcm2835_audio_write_worker(bcm2835_alsa_stream_t *alsa_stream, ++ uint32_t count, void *src) ++{ ++ VC_AUDIO_MSG_T m; ++ AUDIO_INSTANCE_T *instance = alsa_stream->instance; ++ int32_t success; ++ int ret; ++ ++ LOG_DBG(" .. IN\n"); ++ ++ LOG_INFO(" Writing %d bytes from %p\n", count, src); ++ ++ if(mutex_lock_interruptible(&instance->vchi_mutex)) ++ { ++ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections); ++ return -EINTR; ++ } ++ vchi_service_use(instance->vchi_handle[0]); ++ ++ if ( instance->peer_version==0 && vchi_get_peer_version(instance->vchi_handle[0], &instance->peer_version) == 0 ) { ++ LOG_DBG("%s: client version %d connected\n", __func__, instance->peer_version); ++ } ++ m.type = VC_AUDIO_MSG_TYPE_WRITE; ++ m.u.write.count = count; ++ // old version uses bulk, new version uses control ++ m.u.write.max_packet = instance->peer_version < 2 || force_bulk ? 0:4000; ++ m.u.write.callback = alsa_stream->fifo_irq_handler; ++ m.u.write.cookie = alsa_stream; ++ m.u.write.silence = src == NULL; ++ ++ /* Send the message to the videocore */ ++ success = vchi_msg_queue(instance->vchi_handle[0], ++ &m, sizeof m, ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); ++ ++ if (success != 0) { ++ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)\n", ++ __func__, success); ++ ++ ret = -1; ++ goto unlock; ++ } ++ if (!m.u.write.silence) { ++ if (m.u.write.max_packet == 0) { ++ /* Send the message to the videocore */ ++ success = vchi_bulk_queue_transmit(instance->vchi_handle[0], ++ src, count, ++ 0 * ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED ++ + ++ 1 * ++ VCHI_FLAGS_BLOCK_UNTIL_DATA_READ, ++ NULL); ++ } else { ++ while (count > 0) { ++ int bytes = min((int)m.u.write.max_packet, (int)count); ++ success = vchi_msg_queue(instance->vchi_handle[0], ++ src, bytes, ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); ++ src = (char *)src + bytes; ++ count -= bytes; ++ } ++ } ++ if (success != 0) { ++ LOG_ERR ++ ("%s: failed on vchi_bulk_queue_transmit (status=%d)\n", ++ __func__, success); ++ ++ ret = -1; ++ goto unlock; ++ } ++ } ++ ret = 0; ++ ++unlock: ++ vchi_service_release(instance->vchi_handle[0]); ++ mutex_unlock(&instance->vchi_mutex); ++ LOG_DBG(" .. OUT\n"); ++ return ret; ++} ++ ++/** ++ * Returns all buffers from arm->vc ++ */ ++void bcm2835_audio_flush_buffers(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ LOG_DBG(" .. IN\n"); ++ LOG_DBG(" .. OUT\n"); ++ return; ++} ++ ++/** ++ * Forces VC to flush(drop) its filled playback buffers and ++ * return them the us. (VC->ARM) ++ */ ++void bcm2835_audio_flush_playback_buffers(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ LOG_DBG(" .. IN\n"); ++ LOG_DBG(" .. OUT\n"); ++} ++ ++uint32_t bcm2835_audio_retrieve_buffers(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ uint32_t count = atomic_read(&alsa_stream->retrieved); ++ atomic_sub(count, &alsa_stream->retrieved); ++ return count; ++} ++ ++module_param(force_bulk, bool, 0444); ++MODULE_PARM_DESC(force_bulk, "Force use of vchiq bulk for audio"); +diff -Nur linux-4.1.13.orig/sound/arm/Kconfig linux-rpi/sound/arm/Kconfig +--- linux-4.1.13.orig/sound/arm/Kconfig 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/sound/arm/Kconfig 2015-11-29 09:42:41.446997173 +0100 +@@ -40,5 +40,13 @@ + Say Y or M if you want to support any AC97 codec attached to + the PXA2xx AC97 interface. + ++config SND_BCM2835 ++ tristate "BCM2835 ALSA driver" ++ depends on (ARCH_BCM2708 || ARCH_BCM2709 || ARCH_BCM2835) \ ++ && BCM2708_VCHIQ && SND ++ select SND_PCM ++ help ++ Say Y or M if you want to support BCM2835 Alsa pcm card driver ++ + endif # SND_ARM + +diff -Nur linux-4.1.13.orig/sound/arm/Makefile linux-rpi/sound/arm/Makefile +--- linux-4.1.13.orig/sound/arm/Makefile 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/sound/arm/Makefile 2015-11-29 09:42:41.446997173 +0100 +@@ -14,3 +14,8 @@ + + obj-$(CONFIG_SND_PXA2XX_AC97) += snd-pxa2xx-ac97.o + snd-pxa2xx-ac97-objs := pxa2xx-ac97.o ++ ++obj-$(CONFIG_SND_BCM2835) += snd-bcm2835.o ++snd-bcm2835-objs := bcm2835.o bcm2835-ctl.o bcm2835-pcm.o bcm2835-vchiq.o ++ ++ccflags-y += -Idrivers/misc/vc04_services -Idrivers/misc/vc04_services/interface/vcos/linuxkernel -D__VCCOREVER__=0x04000000 +diff -Nur linux-4.1.13.orig/sound/arm/vc_vchi_audioserv_defs.h linux-rpi/sound/arm/vc_vchi_audioserv_defs.h +--- linux-4.1.13.orig/sound/arm/vc_vchi_audioserv_defs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/sound/arm/vc_vchi_audioserv_defs.h 2015-11-29 09:42:41.446997173 +0100 +@@ -0,0 +1,116 @@ ++/***************************************************************************** ++* Copyright 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#ifndef _VC_AUDIO_DEFS_H_ ++#define _VC_AUDIO_DEFS_H_ ++ ++#define VC_AUDIOSERV_MIN_VER 1 ++#define VC_AUDIOSERV_VER 2 ++ ++// FourCC code used for VCHI connection ++#define VC_AUDIO_SERVER_NAME MAKE_FOURCC("AUDS") ++ ++// Maximum message length ++#define VC_AUDIO_MAX_MSG_LEN (sizeof( VC_AUDIO_MSG_T )) ++ ++// List of screens that are currently supported ++// All message types supported for HOST->VC direction ++typedef enum { ++ VC_AUDIO_MSG_TYPE_RESULT, // Generic result ++ VC_AUDIO_MSG_TYPE_COMPLETE, // Generic result ++ VC_AUDIO_MSG_TYPE_CONFIG, // Configure audio ++ VC_AUDIO_MSG_TYPE_CONTROL, // Configure audio ++ VC_AUDIO_MSG_TYPE_OPEN, // Configure audio ++ VC_AUDIO_MSG_TYPE_CLOSE, // Configure audio ++ VC_AUDIO_MSG_TYPE_START, // Configure audio ++ VC_AUDIO_MSG_TYPE_STOP, // Configure audio ++ VC_AUDIO_MSG_TYPE_WRITE, // Configure audio ++ VC_AUDIO_MSG_TYPE_MAX ++} VC_AUDIO_MSG_TYPE; ++ ++// configure the audio ++typedef struct { ++ uint32_t channels; ++ uint32_t samplerate; ++ uint32_t bps; ++ ++} VC_AUDIO_CONFIG_T; ++ ++typedef struct { ++ uint32_t volume; ++ uint32_t dest; ++ ++} VC_AUDIO_CONTROL_T; ++ ++// audio ++typedef struct { ++ uint32_t dummy; ++ ++} VC_AUDIO_OPEN_T; ++ ++// audio ++typedef struct { ++ uint32_t dummy; ++ ++} VC_AUDIO_CLOSE_T; ++// audio ++typedef struct { ++ uint32_t dummy; ++ ++} VC_AUDIO_START_T; ++// audio ++typedef struct { ++ uint32_t draining; ++ ++} VC_AUDIO_STOP_T; ++ ++// configure the write audio samples ++typedef struct { ++ uint32_t count; // in bytes ++ void *callback; ++ void *cookie; ++ uint16_t silence; ++ uint16_t max_packet; ++} VC_AUDIO_WRITE_T; ++ ++// Generic result for a request (VC->HOST) ++typedef struct { ++ int32_t success; // Success value ++ ++} VC_AUDIO_RESULT_T; ++ ++// Generic result for a request (VC->HOST) ++typedef struct { ++ int32_t count; // Success value ++ void *callback; ++ void *cookie; ++} VC_AUDIO_COMPLETE_T; ++ ++// Message header for all messages in HOST->VC direction ++typedef struct { ++ int32_t type; // Message type (VC_AUDIO_MSG_TYPE) ++ union { ++ VC_AUDIO_CONFIG_T config; ++ VC_AUDIO_CONTROL_T control; ++ VC_AUDIO_OPEN_T open; ++ VC_AUDIO_CLOSE_T close; ++ VC_AUDIO_START_T start; ++ VC_AUDIO_STOP_T stop; ++ VC_AUDIO_WRITE_T write; ++ VC_AUDIO_RESULT_T result; ++ VC_AUDIO_COMPLETE_T complete; ++ } u; ++} VC_AUDIO_MSG_T; ++ ++#endif // _VC_AUDIO_DEFS_H_ +diff -Nur linux-4.1.13.orig/sound/soc/bcm/bcm2708-i2s.c linux-rpi/sound/soc/bcm/bcm2708-i2s.c +--- linux-4.1.13.orig/sound/soc/bcm/bcm2708-i2s.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/sound/soc/bcm/bcm2708-i2s.c 2015-11-29 09:42:41.558989731 +0100 +@@ -0,0 +1,1014 @@ ++/* ++ * ALSA SoC I2S Audio Layer for Broadcom BCM2708 SoC ++ * ++ * Author: Florian Meier ++ * Copyright 2013 ++ * ++ * Based on ++ * Raspberry Pi PCM I2S ALSA Driver ++ * Copyright (c) by Phil Poole 2013 ++ * ++ * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor ++ * Vladimir Barinov, ++ * Copyright (C) 2007 MontaVista Software, Inc., ++ * ++ * OMAP ALSA SoC DAI driver using McBSP port ++ * Copyright (C) 2008 Nokia Corporation ++ * Contact: Jarkko Nikula ++ * Peter Ujfalusi ++ * ++ * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver ++ * Author: Timur Tabi ++ * Copyright 2007-2010 Freescale Semiconductor, Inc. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ */ ++ ++#include "bcm2708-i2s.h" ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++/* Clock registers */ ++#define BCM2708_CLK_PCMCTL_REG 0x00 ++#define BCM2708_CLK_PCMDIV_REG 0x04 ++ ++/* Clock register settings */ ++#define BCM2708_CLK_PASSWD (0x5a000000) ++#define BCM2708_CLK_PASSWD_MASK (0xff000000) ++#define BCM2708_CLK_MASH(v) ((v) << 9) ++#define BCM2708_CLK_FLIP BIT(8) ++#define BCM2708_CLK_BUSY BIT(7) ++#define BCM2708_CLK_KILL BIT(5) ++#define BCM2708_CLK_ENAB BIT(4) ++#define BCM2708_CLK_SRC(v) (v) ++ ++#define BCM2708_CLK_SHIFT (12) ++#define BCM2708_CLK_DIVI(v) ((v) << BCM2708_CLK_SHIFT) ++#define BCM2708_CLK_DIVF(v) (v) ++#define BCM2708_CLK_DIVF_MASK (0xFFF) ++ ++enum { ++ BCM2708_CLK_MASH_0 = 0, ++ BCM2708_CLK_MASH_1, ++ BCM2708_CLK_MASH_2, ++ BCM2708_CLK_MASH_3, ++}; ++ ++enum { ++ BCM2708_CLK_SRC_GND = 0, ++ BCM2708_CLK_SRC_OSC, ++ BCM2708_CLK_SRC_DBG0, ++ BCM2708_CLK_SRC_DBG1, ++ BCM2708_CLK_SRC_PLLA, ++ BCM2708_CLK_SRC_PLLC, ++ BCM2708_CLK_SRC_PLLD, ++ BCM2708_CLK_SRC_HDMI, ++}; ++ ++/* Most clocks are not useable (freq = 0) */ ++static const unsigned int bcm2708_clk_freq[BCM2708_CLK_SRC_HDMI+1] = { ++ [BCM2708_CLK_SRC_GND] = 0, ++ [BCM2708_CLK_SRC_OSC] = 19200000, ++ [BCM2708_CLK_SRC_DBG0] = 0, ++ [BCM2708_CLK_SRC_DBG1] = 0, ++ [BCM2708_CLK_SRC_PLLA] = 0, ++ [BCM2708_CLK_SRC_PLLC] = 0, ++ [BCM2708_CLK_SRC_PLLD] = 500000000, ++ [BCM2708_CLK_SRC_HDMI] = 0, ++}; ++ ++/* I2S registers */ ++#define BCM2708_I2S_CS_A_REG 0x00 ++#define BCM2708_I2S_FIFO_A_REG 0x04 ++#define BCM2708_I2S_MODE_A_REG 0x08 ++#define BCM2708_I2S_RXC_A_REG 0x0c ++#define BCM2708_I2S_TXC_A_REG 0x10 ++#define BCM2708_I2S_DREQ_A_REG 0x14 ++#define BCM2708_I2S_INTEN_A_REG 0x18 ++#define BCM2708_I2S_INTSTC_A_REG 0x1c ++#define BCM2708_I2S_GRAY_REG 0x20 ++ ++/* I2S register settings */ ++#define BCM2708_I2S_STBY BIT(25) ++#define BCM2708_I2S_SYNC BIT(24) ++#define BCM2708_I2S_RXSEX BIT(23) ++#define BCM2708_I2S_RXF BIT(22) ++#define BCM2708_I2S_TXE BIT(21) ++#define BCM2708_I2S_RXD BIT(20) ++#define BCM2708_I2S_TXD BIT(19) ++#define BCM2708_I2S_RXR BIT(18) ++#define BCM2708_I2S_TXW BIT(17) ++#define BCM2708_I2S_CS_RXERR BIT(16) ++#define BCM2708_I2S_CS_TXERR BIT(15) ++#define BCM2708_I2S_RXSYNC BIT(14) ++#define BCM2708_I2S_TXSYNC BIT(13) ++#define BCM2708_I2S_DMAEN BIT(9) ++#define BCM2708_I2S_RXTHR(v) ((v) << 7) ++#define BCM2708_I2S_TXTHR(v) ((v) << 5) ++#define BCM2708_I2S_RXCLR BIT(4) ++#define BCM2708_I2S_TXCLR BIT(3) ++#define BCM2708_I2S_TXON BIT(2) ++#define BCM2708_I2S_RXON BIT(1) ++#define BCM2708_I2S_EN (1) ++ ++#define BCM2708_I2S_CLKDIS BIT(28) ++#define BCM2708_I2S_PDMN BIT(27) ++#define BCM2708_I2S_PDME BIT(26) ++#define BCM2708_I2S_FRXP BIT(25) ++#define BCM2708_I2S_FTXP BIT(24) ++#define BCM2708_I2S_CLKM BIT(23) ++#define BCM2708_I2S_CLKI BIT(22) ++#define BCM2708_I2S_FSM BIT(21) ++#define BCM2708_I2S_FSI BIT(20) ++#define BCM2708_I2S_FLEN(v) ((v) << 10) ++#define BCM2708_I2S_FSLEN(v) (v) ++ ++#define BCM2708_I2S_CHWEX BIT(15) ++#define BCM2708_I2S_CHEN BIT(14) ++#define BCM2708_I2S_CHPOS(v) ((v) << 4) ++#define BCM2708_I2S_CHWID(v) (v) ++#define BCM2708_I2S_CH1(v) ((v) << 16) ++#define BCM2708_I2S_CH2(v) (v) ++ ++#define BCM2708_I2S_TX_PANIC(v) ((v) << 24) ++#define BCM2708_I2S_RX_PANIC(v) ((v) << 16) ++#define BCM2708_I2S_TX(v) ((v) << 8) ++#define BCM2708_I2S_RX(v) (v) ++ ++#define BCM2708_I2S_INT_RXERR BIT(3) ++#define BCM2708_I2S_INT_TXERR BIT(2) ++#define BCM2708_I2S_INT_RXR BIT(1) ++#define BCM2708_I2S_INT_TXW BIT(0) ++ ++/* I2S DMA interface */ ++#define BCM2708_I2S_FIFO_PHYSICAL_ADDR 0x7E203004 ++#define BCM2708_DMA_DREQ_PCM_TX 2 ++#define BCM2708_DMA_DREQ_PCM_RX 3 ++ ++/* I2S pin configuration */ ++static int bcm2708_i2s_gpio=BCM2708_I2S_GPIO_AUTO; ++ ++/* General device struct */ ++struct bcm2708_i2s_dev { ++ struct device *dev; ++ struct snd_dmaengine_dai_dma_data dma_data[2]; ++ unsigned int fmt; ++ unsigned int bclk_ratio; ++ ++ struct regmap *i2s_regmap; ++ struct regmap *clk_regmap; ++}; ++ ++void bcm2708_i2s_set_gpio(int gpio) { ++ bcm2708_i2s_gpio=gpio; ++} ++EXPORT_SYMBOL(bcm2708_i2s_set_gpio); ++ ++ ++static void bcm2708_i2s_start_clock(struct bcm2708_i2s_dev *dev) ++{ ++ /* Start the clock if in master mode */ ++ unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK; ++ ++ switch (master) { ++ case SND_SOC_DAIFMT_CBS_CFS: ++ case SND_SOC_DAIFMT_CBS_CFM: ++ regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, ++ BCM2708_CLK_PASSWD_MASK | BCM2708_CLK_ENAB, ++ BCM2708_CLK_PASSWD | BCM2708_CLK_ENAB); ++ break; ++ default: ++ break; ++ } ++} ++ ++static void bcm2708_i2s_stop_clock(struct bcm2708_i2s_dev *dev) ++{ ++ uint32_t clkreg; ++ int timeout = 1000; ++ ++ /* Stop clock */ ++ regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, ++ BCM2708_CLK_PASSWD_MASK | BCM2708_CLK_ENAB, ++ BCM2708_CLK_PASSWD); ++ ++ /* Wait for the BUSY flag going down */ ++ while (--timeout) { ++ regmap_read(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, &clkreg); ++ if (!(clkreg & BCM2708_CLK_BUSY)) ++ break; ++ } ++ ++ if (!timeout) { ++ /* KILL the clock */ ++ dev_err(dev->dev, "I2S clock didn't stop. Kill the clock!\n"); ++ regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, ++ BCM2708_CLK_KILL | BCM2708_CLK_PASSWD_MASK, ++ BCM2708_CLK_KILL | BCM2708_CLK_PASSWD); ++ } ++} ++ ++static void bcm2708_i2s_clear_fifos(struct bcm2708_i2s_dev *dev, ++ bool tx, bool rx) ++{ ++ int timeout = 1000; ++ uint32_t syncval; ++ uint32_t csreg; ++ uint32_t i2s_active_state; ++ uint32_t clkreg; ++ uint32_t clk_active_state; ++ uint32_t off; ++ uint32_t clr; ++ ++ off = tx ? BCM2708_I2S_TXON : 0; ++ off |= rx ? BCM2708_I2S_RXON : 0; ++ ++ clr = tx ? BCM2708_I2S_TXCLR : 0; ++ clr |= rx ? BCM2708_I2S_RXCLR : 0; ++ ++ /* Backup the current state */ ++ regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &csreg); ++ i2s_active_state = csreg & (BCM2708_I2S_RXON | BCM2708_I2S_TXON); ++ ++ regmap_read(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, &clkreg); ++ clk_active_state = clkreg & BCM2708_CLK_ENAB; ++ ++ /* Start clock if not running */ ++ if (!clk_active_state) { ++ regmap_update_bits(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, ++ BCM2708_CLK_PASSWD_MASK | BCM2708_CLK_ENAB, ++ BCM2708_CLK_PASSWD | BCM2708_CLK_ENAB); ++ } ++ ++ /* Stop I2S module */ ++ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, off, 0); ++ ++ /* ++ * Clear the FIFOs ++ * Requires at least 2 PCM clock cycles to take effect ++ */ ++ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, clr, clr); ++ ++ /* Wait for 2 PCM clock cycles */ ++ ++ /* ++ * Toggle the SYNC flag. After 2 PCM clock cycles it can be read back ++ * FIXME: This does not seem to work for slave mode! ++ */ ++ regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &syncval); ++ syncval &= BCM2708_I2S_SYNC; ++ ++ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, ++ BCM2708_I2S_SYNC, ~syncval); ++ ++ /* Wait for the SYNC flag changing it's state */ ++ while (--timeout) { ++ regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &csreg); ++ if ((csreg & BCM2708_I2S_SYNC) != syncval) ++ break; ++ } ++ ++ if (!timeout) ++ dev_err(dev->dev, "I2S SYNC error!\n"); ++ ++ /* Stop clock if it was not running before */ ++ if (!clk_active_state) ++ bcm2708_i2s_stop_clock(dev); ++ ++ /* Restore I2S state */ ++ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, ++ BCM2708_I2S_RXON | BCM2708_I2S_TXON, i2s_active_state); ++} ++ ++static int bcm2708_i2s_set_dai_fmt(struct snd_soc_dai *dai, ++ unsigned int fmt) ++{ ++ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); ++ dev->fmt = fmt; ++ return 0; ++} ++ ++static int bcm2708_i2s_set_dai_bclk_ratio(struct snd_soc_dai *dai, ++ unsigned int ratio) ++{ ++ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); ++ dev->bclk_ratio = ratio; ++ return 0; ++} ++ ++ ++static int bcm2708_i2s_set_function(unsigned offset, int function) ++{ ++ #define GPIOFSEL(x) (0x00+(x)*4) ++ void __iomem *gpio = __io_address(GPIO_BASE); ++ unsigned alt = function <= 3 ? function + 4: function == 4 ? 3 : 2; ++ unsigned gpiodir; ++ unsigned gpio_bank = offset / 10; ++ unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3; ++ ++ if (offset >= BCM2708_NR_GPIOS) ++ return -EINVAL; ++ ++ gpiodir = readl(gpio + GPIOFSEL(gpio_bank)); ++ gpiodir &= ~(7 << gpio_field_offset); ++ gpiodir |= alt << gpio_field_offset; ++ writel(gpiodir, gpio + GPIOFSEL(gpio_bank)); ++ return 0; ++} ++ ++static void bcm2708_i2s_setup_gpio(void) ++{ ++ /* ++ * This is the common way to handle the GPIO pins for ++ * the Raspberry Pi. ++ * TODO Better way would be to handle ++ * this in the device tree! ++ */ ++ int pin,pinconfig,startpin,alt; ++ ++ /* SPI is on different GPIOs on different boards */ ++ /* for Raspberry Pi B+, this is pin GPIO18-21, for original on 28-31 */ ++ if (bcm2708_i2s_gpio==BCM2708_I2S_GPIO_AUTO) { ++ if ((system_rev & 0xffffff) >= 0x10) { ++ /* Model B+ */ ++ pinconfig=BCM2708_I2S_GPIO_PIN18; ++ } else { ++ /* original */ ++ pinconfig=BCM2708_I2S_GPIO_PIN28; ++ } ++ } else { ++ pinconfig=bcm2708_i2s_gpio; ++ } ++ ++ if (pinconfig==BCM2708_I2S_GPIO_PIN18) { ++ startpin=18; ++ alt=BCM2708_I2S_GPIO_PIN18_ALT; ++ } else if (pinconfig==BCM2708_I2S_GPIO_PIN28) { ++ startpin=28; ++ alt=BCM2708_I2S_GPIO_PIN28_ALT; ++ } else { ++ printk(KERN_INFO "Can't configure I2S GPIOs, unknown pin mode for I2S: %i\n",pinconfig); ++ return; ++ } ++ ++ /* configure I2S pins to correct ALT mode */ ++ for (pin = startpin; pin <= startpin+3; pin++) { ++ bcm2708_i2s_set_function(pin, alt); ++ } ++} ++ ++static int bcm2708_i2s_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params, ++ struct snd_soc_dai *dai) ++{ ++ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); ++ ++ unsigned int sampling_rate = params_rate(params); ++ unsigned int data_length, data_delay, bclk_ratio; ++ unsigned int ch1pos, ch2pos, mode, format; ++ unsigned int mash = BCM2708_CLK_MASH_1; ++ unsigned int divi, divf, target_frequency; ++ int clk_src = -1; ++ unsigned int master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK; ++ bool bit_master = (master == SND_SOC_DAIFMT_CBS_CFS ++ || master == SND_SOC_DAIFMT_CBS_CFM); ++ ++ bool frame_master = (master == SND_SOC_DAIFMT_CBS_CFS ++ || master == SND_SOC_DAIFMT_CBM_CFS); ++ uint32_t csreg; ++ ++ /* ++ * If a stream is already enabled, ++ * the registers are already set properly. ++ */ ++ regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &csreg); ++ ++ if (csreg & (BCM2708_I2S_TXON | BCM2708_I2S_RXON)) ++ return 0; ++ ++ if (!dev->dev->of_node) ++ bcm2708_i2s_setup_gpio(); ++ ++ /* ++ * Adjust the data length according to the format. ++ * We prefill the half frame length with an integer ++ * divider of 2400 as explained at the clock settings. ++ * Maybe it is overwritten there, if the Integer mode ++ * does not apply. ++ */ ++ switch (params_format(params)) { ++ case SNDRV_PCM_FORMAT_S16_LE: ++ data_length = 16; ++ bclk_ratio = 50; ++ break; ++ case SNDRV_PCM_FORMAT_S24_LE: ++ data_length = 24; ++ bclk_ratio = 50; ++ break; ++ case SNDRV_PCM_FORMAT_S32_LE: ++ data_length = 32; ++ bclk_ratio = 100; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ /* If bclk_ratio already set, use that one. */ ++ if (dev->bclk_ratio) ++ bclk_ratio = dev->bclk_ratio; ++ ++ /* ++ * Clock Settings ++ * ++ * The target frequency of the bit clock is ++ * sampling rate * frame length ++ * ++ * Integer mode: ++ * Sampling rates that are multiples of 8000 kHz ++ * can be driven by the oscillator of 19.2 MHz ++ * with an integer divider as long as the frame length ++ * is an integer divider of 19200000/8000=2400 as set up above. ++ * This is no longer possible if the sampling rate ++ * is too high (e.g. 192 kHz), because the oscillator is too slow. ++ * ++ * MASH mode: ++ * For all other sampling rates, it is not possible to ++ * have an integer divider. Approximate the clock ++ * with the MASH module that induces a slight frequency ++ * variance. To minimize that it is best to have the fastest ++ * clock here. That is PLLD with 500 MHz. ++ */ ++ target_frequency = sampling_rate * bclk_ratio; ++ clk_src = BCM2708_CLK_SRC_OSC; ++ mash = BCM2708_CLK_MASH_0; ++ ++ if (bcm2708_clk_freq[clk_src] % target_frequency == 0 ++ && bit_master && frame_master) { ++ divi = bcm2708_clk_freq[clk_src] / target_frequency; ++ divf = 0; ++ } else { ++ uint64_t dividend; ++ ++ if (!dev->bclk_ratio) { ++ /* ++ * Overwrite bclk_ratio, because the ++ * above trick is not needed or can ++ * not be used. ++ */ ++ bclk_ratio = 2 * data_length; ++ } ++ ++ target_frequency = sampling_rate * bclk_ratio; ++ ++ clk_src = BCM2708_CLK_SRC_PLLD; ++ mash = BCM2708_CLK_MASH_1; ++ ++ dividend = bcm2708_clk_freq[clk_src]; ++ dividend <<= BCM2708_CLK_SHIFT; ++ do_div(dividend, target_frequency); ++ divi = dividend >> BCM2708_CLK_SHIFT; ++ divf = dividend & BCM2708_CLK_DIVF_MASK; ++ } ++ ++ /* Clock should only be set up here if CPU is clock master */ ++ if (((dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBS_CFS) || ++ ((dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBS_CFM)) { ++ /* Set clock divider */ ++ regmap_write(dev->clk_regmap, BCM2708_CLK_PCMDIV_REG, BCM2708_CLK_PASSWD ++ | BCM2708_CLK_DIVI(divi) ++ | BCM2708_CLK_DIVF(divf)); ++ ++ /* Setup clock, but don't start it yet */ ++ regmap_write(dev->clk_regmap, BCM2708_CLK_PCMCTL_REG, BCM2708_CLK_PASSWD ++ | BCM2708_CLK_MASH(mash) ++ | BCM2708_CLK_SRC(clk_src)); ++ } ++ ++ /* Setup the frame format */ ++ format = BCM2708_I2S_CHEN; ++ ++ if (data_length >= 24) ++ format |= BCM2708_I2S_CHWEX; ++ ++ format |= BCM2708_I2S_CHWID((data_length-8)&0xf); ++ ++ switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) { ++ case SND_SOC_DAIFMT_I2S: ++ data_delay = 1; ++ break; ++ default: ++ /* ++ * TODO ++ * Others are possible but are not implemented at the moment. ++ */ ++ dev_err(dev->dev, "%s:bad format\n", __func__); ++ return -EINVAL; ++ } ++ ++ ch1pos = data_delay; ++ ch2pos = bclk_ratio / 2 + data_delay; ++ ++ switch (params_channels(params)) { ++ case 2: ++ format = BCM2708_I2S_CH1(format) | BCM2708_I2S_CH2(format); ++ format |= BCM2708_I2S_CH1(BCM2708_I2S_CHPOS(ch1pos)); ++ format |= BCM2708_I2S_CH2(BCM2708_I2S_CHPOS(ch2pos)); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ /* ++ * Set format for both streams. ++ * We cannot set another frame length ++ * (and therefore word length) anyway, ++ * so the format will be the same. ++ */ ++ regmap_write(dev->i2s_regmap, BCM2708_I2S_RXC_A_REG, format); ++ regmap_write(dev->i2s_regmap, BCM2708_I2S_TXC_A_REG, format); ++ ++ /* Setup the I2S mode */ ++ mode = 0; ++ ++ if (data_length <= 16) { ++ /* ++ * Use frame packed mode (2 channels per 32 bit word) ++ * We cannot set another frame length in the second stream ++ * (and therefore word length) anyway, ++ * so the format will be the same. ++ */ ++ mode |= BCM2708_I2S_FTXP | BCM2708_I2S_FRXP; ++ } ++ ++ mode |= BCM2708_I2S_FLEN(bclk_ratio - 1); ++ mode |= BCM2708_I2S_FSLEN(bclk_ratio / 2); ++ ++ /* Master or slave? */ ++ switch (dev->fmt & SND_SOC_DAIFMT_MASTER_MASK) { ++ case SND_SOC_DAIFMT_CBS_CFS: ++ /* CPU is master */ ++ break; ++ case SND_SOC_DAIFMT_CBM_CFS: ++ /* ++ * CODEC is bit clock master ++ * CPU is frame master ++ */ ++ mode |= BCM2708_I2S_CLKM; ++ break; ++ case SND_SOC_DAIFMT_CBS_CFM: ++ /* ++ * CODEC is frame master ++ * CPU is bit clock master ++ */ ++ mode |= BCM2708_I2S_FSM; ++ break; ++ case SND_SOC_DAIFMT_CBM_CFM: ++ /* CODEC is master */ ++ mode |= BCM2708_I2S_CLKM; ++ mode |= BCM2708_I2S_FSM; ++ break; ++ default: ++ dev_err(dev->dev, "%s:bad master\n", __func__); ++ return -EINVAL; ++ } ++ ++ /* ++ * Invert clocks? ++ * ++ * The BCM approach seems to be inverted to the classical I2S approach. ++ */ ++ switch (dev->fmt & SND_SOC_DAIFMT_INV_MASK) { ++ case SND_SOC_DAIFMT_NB_NF: ++ /* None. Therefore, both for BCM */ ++ mode |= BCM2708_I2S_CLKI; ++ mode |= BCM2708_I2S_FSI; ++ break; ++ case SND_SOC_DAIFMT_IB_IF: ++ /* Both. Therefore, none for BCM */ ++ break; ++ case SND_SOC_DAIFMT_NB_IF: ++ /* ++ * Invert only frame sync. Therefore, ++ * invert only bit clock for BCM ++ */ ++ mode |= BCM2708_I2S_CLKI; ++ break; ++ case SND_SOC_DAIFMT_IB_NF: ++ /* ++ * Invert only bit clock. Therefore, ++ * invert only frame sync for BCM ++ */ ++ mode |= BCM2708_I2S_FSI; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ regmap_write(dev->i2s_regmap, BCM2708_I2S_MODE_A_REG, mode); ++ ++ /* Setup the DMA parameters */ ++ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, ++ BCM2708_I2S_RXTHR(1) ++ | BCM2708_I2S_TXTHR(1) ++ | BCM2708_I2S_DMAEN, 0xffffffff); ++ ++ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_DREQ_A_REG, ++ BCM2708_I2S_TX_PANIC(0x10) ++ | BCM2708_I2S_RX_PANIC(0x30) ++ | BCM2708_I2S_TX(0x30) ++ | BCM2708_I2S_RX(0x20), 0xffffffff); ++ ++ /* Clear FIFOs */ ++ bcm2708_i2s_clear_fifos(dev, true, true); ++ ++ return 0; ++} ++ ++static int bcm2708_i2s_prepare(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *dai) ++{ ++ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); ++ uint32_t cs_reg; ++ ++ bcm2708_i2s_start_clock(dev); ++ ++ /* ++ * Clear both FIFOs if the one that should be started ++ * is not empty at the moment. This should only happen ++ * after overrun. Otherwise, hw_params would have cleared ++ * the FIFO. ++ */ ++ regmap_read(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, &cs_reg); ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ++ && !(cs_reg & BCM2708_I2S_TXE)) ++ bcm2708_i2s_clear_fifos(dev, true, false); ++ else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE ++ && (cs_reg & BCM2708_I2S_RXD)) ++ bcm2708_i2s_clear_fifos(dev, false, true); ++ ++ return 0; ++} ++ ++static void bcm2708_i2s_stop(struct bcm2708_i2s_dev *dev, ++ struct snd_pcm_substream *substream, ++ struct snd_soc_dai *dai) ++{ ++ uint32_t mask; ++ ++ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) ++ mask = BCM2708_I2S_RXON; ++ else ++ mask = BCM2708_I2S_TXON; ++ ++ regmap_update_bits(dev->i2s_regmap, ++ BCM2708_I2S_CS_A_REG, mask, 0); ++ ++ /* Stop also the clock when not SND_SOC_DAIFMT_CONT */ ++ if (!dai->active && !(dev->fmt & SND_SOC_DAIFMT_CONT)) ++ bcm2708_i2s_stop_clock(dev); ++} ++ ++static int bcm2708_i2s_trigger(struct snd_pcm_substream *substream, int cmd, ++ struct snd_soc_dai *dai) ++{ ++ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); ++ uint32_t mask; ++ ++ switch (cmd) { ++ case SNDRV_PCM_TRIGGER_START: ++ case SNDRV_PCM_TRIGGER_RESUME: ++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: ++ bcm2708_i2s_start_clock(dev); ++ ++ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) ++ mask = BCM2708_I2S_RXON; ++ else ++ mask = BCM2708_I2S_TXON; ++ ++ regmap_update_bits(dev->i2s_regmap, ++ BCM2708_I2S_CS_A_REG, mask, mask); ++ break; ++ ++ case SNDRV_PCM_TRIGGER_STOP: ++ case SNDRV_PCM_TRIGGER_SUSPEND: ++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH: ++ bcm2708_i2s_stop(dev, substream, dai); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int bcm2708_i2s_startup(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *dai) ++{ ++ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); ++ ++ if (dai->active) ++ return 0; ++ ++ /* Should this still be running stop it */ ++ bcm2708_i2s_stop_clock(dev); ++ ++ /* Enable PCM block */ ++ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, ++ BCM2708_I2S_EN, BCM2708_I2S_EN); ++ ++ /* ++ * Disable STBY. ++ * Requires at least 4 PCM clock cycles to take effect. ++ */ ++ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, ++ BCM2708_I2S_STBY, BCM2708_I2S_STBY); ++ ++ return 0; ++} ++ ++static void bcm2708_i2s_shutdown(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *dai) ++{ ++ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); ++ ++ bcm2708_i2s_stop(dev, substream, dai); ++ ++ /* If both streams are stopped, disable module and clock */ ++ if (dai->active) ++ return; ++ ++ /* Disable the module */ ++ regmap_update_bits(dev->i2s_regmap, BCM2708_I2S_CS_A_REG, ++ BCM2708_I2S_EN, 0); ++ ++ /* ++ * Stopping clock is necessary, because stop does ++ * not stop the clock when SND_SOC_DAIFMT_CONT ++ */ ++ bcm2708_i2s_stop_clock(dev); ++} ++ ++static const struct snd_soc_dai_ops bcm2708_i2s_dai_ops = { ++ .startup = bcm2708_i2s_startup, ++ .shutdown = bcm2708_i2s_shutdown, ++ .prepare = bcm2708_i2s_prepare, ++ .trigger = bcm2708_i2s_trigger, ++ .hw_params = bcm2708_i2s_hw_params, ++ .set_fmt = bcm2708_i2s_set_dai_fmt, ++ .set_bclk_ratio = bcm2708_i2s_set_dai_bclk_ratio ++}; ++ ++static int bcm2708_i2s_dai_probe(struct snd_soc_dai *dai) ++{ ++ struct bcm2708_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); ++ ++ dai->playback_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK]; ++ dai->capture_dma_data = &dev->dma_data[SNDRV_PCM_STREAM_CAPTURE]; ++ ++ return 0; ++} ++ ++static struct snd_soc_dai_driver bcm2708_i2s_dai = { ++ .name = "bcm2708-i2s", ++ .probe = bcm2708_i2s_dai_probe, ++ .playback = { ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = SNDRV_PCM_RATE_8000_192000, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE ++ | SNDRV_PCM_FMTBIT_S24_LE ++ | SNDRV_PCM_FMTBIT_S32_LE ++ }, ++ .capture = { ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = SNDRV_PCM_RATE_8000_192000, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE ++ | SNDRV_PCM_FMTBIT_S24_LE ++ | SNDRV_PCM_FMTBIT_S32_LE ++ }, ++ .ops = &bcm2708_i2s_dai_ops, ++ .symmetric_rates = 1 ++}; ++ ++static bool bcm2708_i2s_volatile_reg(struct device *dev, unsigned int reg) ++{ ++ switch (reg) { ++ case BCM2708_I2S_CS_A_REG: ++ case BCM2708_I2S_FIFO_A_REG: ++ case BCM2708_I2S_INTSTC_A_REG: ++ case BCM2708_I2S_GRAY_REG: ++ return true; ++ default: ++ return false; ++ }; ++} ++ ++static bool bcm2708_i2s_precious_reg(struct device *dev, unsigned int reg) ++{ ++ switch (reg) { ++ case BCM2708_I2S_FIFO_A_REG: ++ return true; ++ default: ++ return false; ++ }; ++} ++ ++static bool bcm2708_clk_volatile_reg(struct device *dev, unsigned int reg) ++{ ++ switch (reg) { ++ case BCM2708_CLK_PCMCTL_REG: ++ return true; ++ default: ++ return false; ++ }; ++} ++ ++static const struct regmap_config bcm2708_regmap_config[] = { ++ { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = BCM2708_I2S_GRAY_REG, ++ .precious_reg = bcm2708_i2s_precious_reg, ++ .volatile_reg = bcm2708_i2s_volatile_reg, ++ .cache_type = REGCACHE_RBTREE, ++ .name = "i2s", ++ }, ++ { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = BCM2708_CLK_PCMDIV_REG, ++ .volatile_reg = bcm2708_clk_volatile_reg, ++ .cache_type = REGCACHE_RBTREE, ++ .name = "clk", ++ }, ++}; ++ ++static const struct snd_soc_component_driver bcm2708_i2s_component = { ++ .name = "bcm2708-i2s-comp", ++}; ++ ++static struct snd_pcm_hardware bcm2708_pcm_hardware = { ++ .info = SNDRV_PCM_INFO_INTERLEAVED | ++ SNDRV_PCM_INFO_JOINT_DUPLEX, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE | ++ SNDRV_PCM_FMTBIT_S24_LE | ++ SNDRV_PCM_FMTBIT_S32_LE, ++ .period_bytes_min = 32, ++ .period_bytes_max = 64 * PAGE_SIZE, ++ .periods_min = 2, ++ .periods_max = 255, ++ .buffer_bytes_max = 128 * PAGE_SIZE, ++}; ++ ++static const struct snd_dmaengine_pcm_config bcm2708_dmaengine_pcm_config = { ++ .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, ++ .pcm_hardware = &bcm2708_pcm_hardware, ++ .prealloc_buffer_size = 256 * PAGE_SIZE, ++}; ++ ++ ++static int bcm2708_i2s_probe(struct platform_device *pdev) ++{ ++ struct bcm2708_i2s_dev *dev; ++ int i; ++ int ret; ++ struct regmap *regmap[2]; ++ struct resource *mem[2]; ++ ++ if (of_property_read_bool(pdev->dev.of_node, "brcm,enable-mmap")) ++ bcm2708_pcm_hardware.info |= ++ SNDRV_PCM_INFO_MMAP | ++ SNDRV_PCM_INFO_MMAP_VALID; ++ ++ /* Request both ioareas */ ++ for (i = 0; i <= 1; i++) { ++ void __iomem *base; ++ ++ mem[i] = platform_get_resource(pdev, IORESOURCE_MEM, i); ++ base = devm_ioremap_resource(&pdev->dev, mem[i]); ++ if (IS_ERR(base)) ++ return PTR_ERR(base); ++ ++ regmap[i] = devm_regmap_init_mmio(&pdev->dev, base, ++ &bcm2708_regmap_config[i]); ++ if (IS_ERR(regmap[i])) { ++ dev_err(&pdev->dev, "I2S probe: regmap init failed\n"); ++ return PTR_ERR(regmap[i]); ++ } ++ } ++ ++ dev = devm_kzalloc(&pdev->dev, sizeof(*dev), ++ GFP_KERNEL); ++ if (IS_ERR(dev)) ++ return PTR_ERR(dev); ++ ++ dev->i2s_regmap = regmap[0]; ++ dev->clk_regmap = regmap[1]; ++ ++ /* Set the DMA address */ ++ dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr = ++ (dma_addr_t)BCM2708_I2S_FIFO_PHYSICAL_ADDR; ++ ++ dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr = ++ (dma_addr_t)BCM2708_I2S_FIFO_PHYSICAL_ADDR; ++ ++ /* Set the DREQ */ ++ dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].slave_id = ++ BCM2708_DMA_DREQ_PCM_TX; ++ dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].slave_id = ++ BCM2708_DMA_DREQ_PCM_RX; ++ ++ /* Set the bus width */ ++ dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr_width = ++ DMA_SLAVE_BUSWIDTH_4_BYTES; ++ dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr_width = ++ DMA_SLAVE_BUSWIDTH_4_BYTES; ++ ++ /* Set burst */ ++ dev->dma_data[SNDRV_PCM_STREAM_PLAYBACK].maxburst = 2; ++ dev->dma_data[SNDRV_PCM_STREAM_CAPTURE].maxburst = 2; ++ ++ /* BCLK ratio - use default */ ++ dev->bclk_ratio = 0; ++ ++ /* Store the pdev */ ++ dev->dev = &pdev->dev; ++ dev_set_drvdata(&pdev->dev, dev); ++ ++ ret = snd_soc_register_component(&pdev->dev, ++ &bcm2708_i2s_component, &bcm2708_i2s_dai, 1); ++ ++ if (ret) { ++ dev_err(&pdev->dev, "Could not register DAI: %d\n", ret); ++ ret = -ENOMEM; ++ return ret; ++ } ++ ++ ret = snd_dmaengine_pcm_register(&pdev->dev, ++ &bcm2708_dmaengine_pcm_config, ++ SND_DMAENGINE_PCM_FLAG_COMPAT); ++ if (ret) { ++ dev_err(&pdev->dev, "Could not register PCM: %d\n", ret); ++ snd_soc_unregister_component(&pdev->dev); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int bcm2708_i2s_remove(struct platform_device *pdev) ++{ ++ snd_dmaengine_pcm_unregister(&pdev->dev); ++ snd_soc_unregister_component(&pdev->dev); ++ return 0; ++} ++ ++static const struct of_device_id bcm2708_i2s_of_match[] = { ++ { .compatible = "brcm,bcm2708-i2s", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, bcm2708_i2s_of_match); ++ ++static struct platform_driver bcm2708_i2s_driver = { ++ .probe = bcm2708_i2s_probe, ++ .remove = bcm2708_i2s_remove, ++ .driver = { ++ .name = "bcm2708-i2s", ++ .owner = THIS_MODULE, ++ .of_match_table = bcm2708_i2s_of_match, ++ }, ++}; ++ ++module_platform_driver(bcm2708_i2s_driver); ++ ++MODULE_ALIAS("platform:bcm2708-i2s"); ++MODULE_DESCRIPTION("BCM2708 I2S interface"); ++MODULE_AUTHOR("Florian Meier "); ++MODULE_LICENSE("GPL v2"); +diff -Nur linux-4.1.13.orig/sound/soc/bcm/bcm2708-i2s.h linux-rpi/sound/soc/bcm/bcm2708-i2s.h +--- linux-4.1.13.orig/sound/soc/bcm/bcm2708-i2s.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/sound/soc/bcm/bcm2708-i2s.h 2015-11-29 09:42:41.558989731 +0100 +@@ -0,0 +1,35 @@ ++/* ++ * I2S configuration for sound cards. ++ * ++ * Copyright (c) 2014 Daniel Matuschek ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef BCM2708_I2S_H ++#define BCM2708_I2S_H ++ ++/* I2S pin assignment */ ++#define BCM2708_I2S_GPIO_AUTO 0 ++#define BCM2708_I2S_GPIO_PIN18 1 ++#define BCM2708_I2S_GPIO_PIN28 2 ++ ++/* Alt mode to enable I2S */ ++#define BCM2708_I2S_GPIO_PIN18_ALT 0 ++#define BCM2708_I2S_GPIO_PIN28_ALT 2 ++ ++extern void bcm2708_i2s_set_gpio(int gpio); ++ ++#endif +diff -Nur linux-4.1.13.orig/sound/soc/bcm/bcm2835-i2s.c linux-rpi/sound/soc/bcm/bcm2835-i2s.c +--- linux-4.1.13.orig/sound/soc/bcm/bcm2835-i2s.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/sound/soc/bcm/bcm2835-i2s.c 2015-11-29 09:42:41.558989731 +0100 +@@ -861,6 +861,7 @@ + { .compatible = "brcm,bcm2835-i2s", }, + {}, + }; ++MODULE_DEVICE_TABLE(of, bcm2835_i2s_of_match); + + static struct platform_driver bcm2835_i2s_driver = { + .probe = bcm2835_i2s_probe, +diff -Nur linux-4.1.13.orig/sound/soc/bcm/hifiberry_amp.c linux-rpi/sound/soc/bcm/hifiberry_amp.c +--- linux-4.1.13.orig/sound/soc/bcm/hifiberry_amp.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/sound/soc/bcm/hifiberry_amp.c 2015-11-29 09:42:41.558989731 +0100 +@@ -0,0 +1,127 @@ ++/* ++ * ASoC Driver for HifiBerry AMP ++ * ++ * Author: Sebastian Eickhoff ++ * Copyright 2014 ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ */ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++static int snd_rpi_hifiberry_amp_init(struct snd_soc_pcm_runtime *rtd) ++{ ++ // ToDo: init of the dsp-registers. ++ return 0; ++} ++ ++static int snd_rpi_hifiberry_amp_hw_params( struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params ) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai; ++ ++ return snd_soc_dai_set_bclk_ratio(cpu_dai, 64); ++} ++ ++static struct snd_soc_ops snd_rpi_hifiberry_amp_ops = { ++ .hw_params = snd_rpi_hifiberry_amp_hw_params, ++}; ++ ++static struct snd_soc_dai_link snd_rpi_hifiberry_amp_dai[] = { ++ { ++ .name = "HifiBerry AMP", ++ .stream_name = "HifiBerry AMP HiFi", ++ .cpu_dai_name = "bcm2708-i2s.0", ++ .codec_dai_name = "tas5713-hifi", ++ .platform_name = "bcm2708-i2s.0", ++ .codec_name = "tas5713.1-001b", ++ .dai_fmt = SND_SOC_DAIFMT_I2S | ++ SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBS_CFS, ++ .ops = &snd_rpi_hifiberry_amp_ops, ++ .init = snd_rpi_hifiberry_amp_init, ++ }, ++}; ++ ++ ++static struct snd_soc_card snd_rpi_hifiberry_amp = { ++ .name = "snd_rpi_hifiberry_amp", ++ .dai_link = snd_rpi_hifiberry_amp_dai, ++ .num_links = ARRAY_SIZE(snd_rpi_hifiberry_amp_dai), ++}; ++ ++static const struct of_device_id snd_rpi_hifiberry_amp_of_match[] = { ++ { .compatible = "hifiberry,hifiberry-amp", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_amp_of_match); ++ ++ ++static int snd_rpi_hifiberry_amp_probe(struct platform_device *pdev) ++{ ++ int ret = 0; ++ ++ snd_rpi_hifiberry_amp.dev = &pdev->dev; ++ ++ if (pdev->dev.of_node) { ++ struct device_node *i2s_node; ++ struct snd_soc_dai_link *dai = &snd_rpi_hifiberry_amp_dai[0]; ++ i2s_node = of_parse_phandle(pdev->dev.of_node, ++ "i2s-controller", 0); ++ ++ if (i2s_node) { ++ dai->cpu_dai_name = NULL; ++ dai->cpu_of_node = i2s_node; ++ dai->platform_name = NULL; ++ dai->platform_of_node = i2s_node; ++ } ++ } ++ ++ ret = snd_soc_register_card(&snd_rpi_hifiberry_amp); ++ ++ if (ret != 0) { ++ dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret); ++ } ++ ++ return ret; ++} ++ ++ ++static int snd_rpi_hifiberry_amp_remove(struct platform_device *pdev) ++{ ++ return snd_soc_unregister_card(&snd_rpi_hifiberry_amp); ++} ++ ++ ++static struct platform_driver snd_rpi_hifiberry_amp_driver = { ++ .driver = { ++ .name = "snd-hifiberry-amp", ++ .owner = THIS_MODULE, ++ .of_match_table = snd_rpi_hifiberry_amp_of_match, ++ }, ++ .probe = snd_rpi_hifiberry_amp_probe, ++ .remove = snd_rpi_hifiberry_amp_remove, ++}; ++ ++ ++module_platform_driver(snd_rpi_hifiberry_amp_driver); ++ ++ ++MODULE_AUTHOR("Sebastian Eickhoff "); ++MODULE_DESCRIPTION("ASoC driver for HiFiBerry-AMP"); ++MODULE_LICENSE("GPL v2"); +diff -Nur linux-4.1.13.orig/sound/soc/bcm/hifiberry_dac.c linux-rpi/sound/soc/bcm/hifiberry_dac.c +--- linux-4.1.13.orig/sound/soc/bcm/hifiberry_dac.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/sound/soc/bcm/hifiberry_dac.c 2015-11-29 09:42:41.558989731 +0100 +@@ -0,0 +1,122 @@ ++/* ++ * ASoC Driver for HifiBerry DAC ++ * ++ * Author: Florian Meier ++ * Copyright 2013 ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ */ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++static int snd_rpi_hifiberry_dac_init(struct snd_soc_pcm_runtime *rtd) ++{ ++ return 0; ++} ++ ++static int snd_rpi_hifiberry_dac_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai; ++ ++ unsigned int sample_bits = ++ snd_pcm_format_physical_width(params_format(params)); ++ ++ return snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2); ++} ++ ++/* machine stream operations */ ++static struct snd_soc_ops snd_rpi_hifiberry_dac_ops = { ++ .hw_params = snd_rpi_hifiberry_dac_hw_params, ++}; ++ ++static struct snd_soc_dai_link snd_rpi_hifiberry_dac_dai[] = { ++{ ++ .name = "HifiBerry DAC", ++ .stream_name = "HifiBerry DAC HiFi", ++ .cpu_dai_name = "bcm2708-i2s.0", ++ .codec_dai_name = "pcm5102a-hifi", ++ .platform_name = "bcm2708-i2s.0", ++ .codec_name = "pcm5102a-codec", ++ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBS_CFS, ++ .ops = &snd_rpi_hifiberry_dac_ops, ++ .init = snd_rpi_hifiberry_dac_init, ++}, ++}; ++ ++/* audio machine driver */ ++static struct snd_soc_card snd_rpi_hifiberry_dac = { ++ .name = "snd_rpi_hifiberry_dac", ++ .dai_link = snd_rpi_hifiberry_dac_dai, ++ .num_links = ARRAY_SIZE(snd_rpi_hifiberry_dac_dai), ++}; ++ ++static int snd_rpi_hifiberry_dac_probe(struct platform_device *pdev) ++{ ++ int ret = 0; ++ ++ snd_rpi_hifiberry_dac.dev = &pdev->dev; ++ ++ if (pdev->dev.of_node) { ++ struct device_node *i2s_node; ++ struct snd_soc_dai_link *dai = &snd_rpi_hifiberry_dac_dai[0]; ++ i2s_node = of_parse_phandle(pdev->dev.of_node, ++ "i2s-controller", 0); ++ ++ if (i2s_node) { ++ dai->cpu_dai_name = NULL; ++ dai->cpu_of_node = i2s_node; ++ dai->platform_name = NULL; ++ dai->platform_of_node = i2s_node; ++ } ++ } ++ ++ ret = snd_soc_register_card(&snd_rpi_hifiberry_dac); ++ if (ret) ++ dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret); ++ ++ return ret; ++} ++ ++static int snd_rpi_hifiberry_dac_remove(struct platform_device *pdev) ++{ ++ return snd_soc_unregister_card(&snd_rpi_hifiberry_dac); ++} ++ ++static const struct of_device_id snd_rpi_hifiberry_dac_of_match[] = { ++ { .compatible = "hifiberry,hifiberry-dac", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_dac_of_match); ++ ++static struct platform_driver snd_rpi_hifiberry_dac_driver = { ++ .driver = { ++ .name = "snd-hifiberry-dac", ++ .owner = THIS_MODULE, ++ .of_match_table = snd_rpi_hifiberry_dac_of_match, ++ }, ++ .probe = snd_rpi_hifiberry_dac_probe, ++ .remove = snd_rpi_hifiberry_dac_remove, ++}; ++ ++module_platform_driver(snd_rpi_hifiberry_dac_driver); ++ ++MODULE_AUTHOR("Florian Meier "); ++MODULE_DESCRIPTION("ASoC Driver for HifiBerry DAC"); ++MODULE_LICENSE("GPL v2"); +diff -Nur linux-4.1.13.orig/sound/soc/bcm/hifiberry_dacplus.c linux-rpi/sound/soc/bcm/hifiberry_dacplus.c +--- linux-4.1.13.orig/sound/soc/bcm/hifiberry_dacplus.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/sound/soc/bcm/hifiberry_dacplus.c 2015-11-29 09:42:41.558989731 +0100 +@@ -0,0 +1,337 @@ ++/* ++ * ASoC Driver for HiFiBerry DAC+ / DAC Pro ++ * ++ * Author: Daniel Matuschek, Stuart MacLean ++ * Copyright 2014-2015 ++ * based on code by Florian Meier ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "../codecs/pcm512x.h" ++ ++#define HIFIBERRY_DACPRO_NOCLOCK 0 ++#define HIFIBERRY_DACPRO_CLK44EN 1 ++#define HIFIBERRY_DACPRO_CLK48EN 2 ++ ++struct pcm512x_priv { ++ struct regmap *regmap; ++ struct clk *sclk; ++}; ++ ++/* Clock rate of CLK44EN attached to GPIO6 pin */ ++#define CLK_44EN_RATE 22579200UL ++/* Clock rate of CLK48EN attached to GPIO3 pin */ ++#define CLK_48EN_RATE 24576000UL ++ ++static bool snd_rpi_hifiberry_is_dacpro; ++ ++static void snd_rpi_hifiberry_dacplus_select_clk(struct snd_soc_codec *codec, ++ int clk_id) ++{ ++ switch (clk_id) { ++ case HIFIBERRY_DACPRO_NOCLOCK: ++ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x24, 0x00); ++ break; ++ case HIFIBERRY_DACPRO_CLK44EN: ++ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x24, 0x20); ++ break; ++ case HIFIBERRY_DACPRO_CLK48EN: ++ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x24, 0x04); ++ break; ++ } ++} ++ ++static void snd_rpi_hifiberry_dacplus_clk_gpio(struct snd_soc_codec *codec) ++{ ++ snd_soc_update_bits(codec, PCM512x_GPIO_EN, 0x24, 0x24); ++ snd_soc_update_bits(codec, PCM512x_GPIO_OUTPUT_3, 0x0f, 0x02); ++ snd_soc_update_bits(codec, PCM512x_GPIO_OUTPUT_6, 0x0f, 0x02); ++} ++ ++static bool snd_rpi_hifiberry_dacplus_is_sclk(struct snd_soc_codec *codec) ++{ ++ int sck; ++ ++ sck = snd_soc_read(codec, PCM512x_RATE_DET_4); ++ return (!(sck & 0x40)); ++} ++ ++static bool snd_rpi_hifiberry_dacplus_is_sclk_sleep( ++ struct snd_soc_codec *codec) ++{ ++ msleep(2); ++ return snd_rpi_hifiberry_dacplus_is_sclk(codec); ++} ++ ++static bool snd_rpi_hifiberry_dacplus_is_pro_card(struct snd_soc_codec *codec) ++{ ++ bool isClk44EN, isClk48En, isNoClk; ++ ++ snd_rpi_hifiberry_dacplus_clk_gpio(codec); ++ ++ snd_rpi_hifiberry_dacplus_select_clk(codec, HIFIBERRY_DACPRO_CLK44EN); ++ isClk44EN = snd_rpi_hifiberry_dacplus_is_sclk_sleep(codec); ++ ++ snd_rpi_hifiberry_dacplus_select_clk(codec, HIFIBERRY_DACPRO_NOCLOCK); ++ isNoClk = snd_rpi_hifiberry_dacplus_is_sclk_sleep(codec); ++ ++ snd_rpi_hifiberry_dacplus_select_clk(codec, HIFIBERRY_DACPRO_CLK48EN); ++ isClk48En = snd_rpi_hifiberry_dacplus_is_sclk_sleep(codec); ++ ++ return (isClk44EN && isClk48En && !isNoClk); ++} ++ ++static int snd_rpi_hifiberry_dacplus_clk_for_rate(int sample_rate) ++{ ++ int type; ++ ++ switch (sample_rate) { ++ case 11025: ++ case 22050: ++ case 44100: ++ case 88200: ++ case 176400: ++ type = HIFIBERRY_DACPRO_CLK44EN; ++ break; ++ default: ++ type = HIFIBERRY_DACPRO_CLK48EN; ++ break; ++ } ++ return type; ++} ++ ++static void snd_rpi_hifiberry_dacplus_set_sclk(struct snd_soc_codec *codec, ++ int sample_rate) ++{ ++ struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); ++ ++ if (!IS_ERR(pcm512x->sclk)) { ++ int ctype; ++ ++ ctype = snd_rpi_hifiberry_dacplus_clk_for_rate(sample_rate); ++ clk_set_rate(pcm512x->sclk, (ctype == HIFIBERRY_DACPRO_CLK44EN) ++ ? CLK_44EN_RATE : CLK_48EN_RATE); ++ snd_rpi_hifiberry_dacplus_select_clk(codec, ctype); ++ } ++} ++ ++static int snd_rpi_hifiberry_dacplus_init(struct snd_soc_pcm_runtime *rtd) ++{ ++ struct snd_soc_codec *codec = rtd->codec; ++ struct pcm512x_priv *priv; ++ ++ snd_rpi_hifiberry_is_dacpro ++ = snd_rpi_hifiberry_dacplus_is_pro_card(codec); ++ ++ if (snd_rpi_hifiberry_is_dacpro) { ++ struct snd_soc_dai_link *dai = rtd->dai_link; ++ ++ dai->name = "HiFiBerry DAC+ Pro"; ++ dai->stream_name = "HiFiBerry DAC+ Pro HiFi"; ++ dai->dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF ++ | SND_SOC_DAIFMT_CBM_CFM; ++ ++ snd_soc_update_bits(codec, PCM512x_BCLK_LRCLK_CFG, 0x31, 0x11); ++ snd_soc_update_bits(codec, PCM512x_MASTER_MODE, 0x03, 0x03); ++ snd_soc_update_bits(codec, PCM512x_MASTER_CLKDIV_2, 0x7f, 63); ++ } else { ++ priv = snd_soc_codec_get_drvdata(codec); ++ priv->sclk = ERR_PTR(-ENOENT); ++ } ++ ++ snd_soc_update_bits(codec, PCM512x_GPIO_EN, 0x08, 0x08); ++ snd_soc_update_bits(codec, PCM512x_GPIO_OUTPUT_4, 0x0f, 0x02); ++ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08, 0x08); ++ ++ return 0; ++} ++ ++static int snd_rpi_hifiberry_dacplus_update_rate_den( ++ struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_codec *codec = rtd->codec; ++ struct pcm512x_priv *pcm512x = snd_soc_codec_get_drvdata(codec); ++ struct snd_ratnum *rats_no_pll; ++ unsigned int num = 0, den = 0; ++ int err; ++ ++ rats_no_pll = devm_kzalloc(rtd->dev, sizeof(*rats_no_pll), GFP_KERNEL); ++ if (!rats_no_pll) ++ return -ENOMEM; ++ ++ rats_no_pll->num = clk_get_rate(pcm512x->sclk) / 64; ++ rats_no_pll->den_min = 1; ++ rats_no_pll->den_max = 128; ++ rats_no_pll->den_step = 1; ++ ++ err = snd_interval_ratnum(hw_param_interval(params, ++ SNDRV_PCM_HW_PARAM_RATE), 1, rats_no_pll, &num, &den); ++ if (err >= 0 && den) { ++ params->rate_num = num; ++ params->rate_den = den; ++ } ++ ++ devm_kfree(rtd->dev, rats_no_pll); ++ return 0; ++} ++ ++static int snd_rpi_hifiberry_dacplus_set_bclk_ratio_pro( ++ struct snd_soc_dai *cpu_dai, struct snd_pcm_hw_params *params) ++{ ++ int bratio = snd_pcm_format_physical_width(params_format(params)) ++ * params_channels(params); ++ return snd_soc_dai_set_bclk_ratio(cpu_dai, bratio); ++} ++ ++static int snd_rpi_hifiberry_dacplus_hw_params( ++ struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) ++{ ++ int ret; ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai; ++ ++ if (snd_rpi_hifiberry_is_dacpro) { ++ struct snd_soc_codec *codec = rtd->codec; ++ ++ snd_rpi_hifiberry_dacplus_set_sclk(codec, ++ params_rate(params)); ++ ++ ret = snd_rpi_hifiberry_dacplus_set_bclk_ratio_pro(cpu_dai, ++ params); ++ if (!ret) ++ ret = snd_rpi_hifiberry_dacplus_update_rate_den( ++ substream, params); ++ } else { ++ ret = snd_soc_dai_set_bclk_ratio(cpu_dai, 64); ++ } ++ return ret; ++} ++ ++static int snd_rpi_hifiberry_dacplus_startup( ++ struct snd_pcm_substream *substream) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_codec *codec = rtd->codec; ++ ++ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08, 0x08); ++ return 0; ++} ++ ++static void snd_rpi_hifiberry_dacplus_shutdown( ++ struct snd_pcm_substream *substream) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_codec *codec = rtd->codec; ++ ++ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08, 0x00); ++} ++ ++/* machine stream operations */ ++static struct snd_soc_ops snd_rpi_hifiberry_dacplus_ops = { ++ .hw_params = snd_rpi_hifiberry_dacplus_hw_params, ++ .startup = snd_rpi_hifiberry_dacplus_startup, ++ .shutdown = snd_rpi_hifiberry_dacplus_shutdown, ++}; ++ ++static struct snd_soc_dai_link snd_rpi_hifiberry_dacplus_dai[] = { ++{ ++ .name = "HiFiBerry DAC+", ++ .stream_name = "HiFiBerry DAC+ HiFi", ++ .cpu_dai_name = "bcm2708-i2s.0", ++ .codec_dai_name = "pcm512x-hifi", ++ .platform_name = "bcm2708-i2s.0", ++ .codec_name = "pcm512x.1-004d", ++ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBS_CFS, ++ .ops = &snd_rpi_hifiberry_dacplus_ops, ++ .init = snd_rpi_hifiberry_dacplus_init, ++}, ++}; ++ ++/* audio machine driver */ ++static struct snd_soc_card snd_rpi_hifiberry_dacplus = { ++ .name = "snd_rpi_hifiberry_dacplus", ++ .dai_link = snd_rpi_hifiberry_dacplus_dai, ++ .num_links = ARRAY_SIZE(snd_rpi_hifiberry_dacplus_dai), ++}; ++ ++static int snd_rpi_hifiberry_dacplus_probe(struct platform_device *pdev) ++{ ++ int ret = 0; ++ ++ snd_rpi_hifiberry_dacplus.dev = &pdev->dev; ++ if (pdev->dev.of_node) { ++ struct device_node *i2s_node; ++ struct snd_soc_dai_link *dai; ++ ++ dai = &snd_rpi_hifiberry_dacplus_dai[0]; ++ i2s_node = of_parse_phandle(pdev->dev.of_node, ++ "i2s-controller", 0); ++ ++ if (i2s_node) { ++ dai->cpu_dai_name = NULL; ++ dai->cpu_of_node = i2s_node; ++ dai->platform_name = NULL; ++ dai->platform_of_node = i2s_node; ++ } ++ } ++ ++ ret = snd_soc_register_card(&snd_rpi_hifiberry_dacplus); ++ if (ret) ++ dev_err(&pdev->dev, ++ "snd_soc_register_card() failed: %d\n", ret); ++ ++ return ret; ++} ++ ++static int snd_rpi_hifiberry_dacplus_remove(struct platform_device *pdev) ++{ ++ return snd_soc_unregister_card(&snd_rpi_hifiberry_dacplus); ++} ++ ++static const struct of_device_id snd_rpi_hifiberry_dacplus_of_match[] = { ++ { .compatible = "hifiberry,hifiberry-dacplus", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_dacplus_of_match); ++ ++static struct platform_driver snd_rpi_hifiberry_dacplus_driver = { ++ .driver = { ++ .name = "snd-rpi-hifiberry-dacplus", ++ .owner = THIS_MODULE, ++ .of_match_table = snd_rpi_hifiberry_dacplus_of_match, ++ }, ++ .probe = snd_rpi_hifiberry_dacplus_probe, ++ .remove = snd_rpi_hifiberry_dacplus_remove, ++}; ++ ++module_platform_driver(snd_rpi_hifiberry_dacplus_driver); ++ ++MODULE_AUTHOR("Daniel Matuschek "); ++MODULE_DESCRIPTION("ASoC Driver for HiFiBerry DAC+"); ++MODULE_LICENSE("GPL v2"); +diff -Nur linux-4.1.13.orig/sound/soc/bcm/hifiberry_digi.c linux-rpi/sound/soc/bcm/hifiberry_digi.c +--- linux-4.1.13.orig/sound/soc/bcm/hifiberry_digi.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/sound/soc/bcm/hifiberry_digi.c 2015-11-29 09:42:41.558989731 +0100 +@@ -0,0 +1,223 @@ ++/* ++ * ASoC Driver for HifiBerry Digi ++ * ++ * Author: Daniel Matuschek ++ * based on the HifiBerry DAC driver by Florian Meier ++ * Copyright 2013 ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ */ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "../codecs/wm8804.h" ++ ++static short int auto_shutdown_output = 0; ++module_param(auto_shutdown_output, short, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP); ++MODULE_PARM_DESC(auto_shutdown_output, "Shutdown SP/DIF output if playback is stopped"); ++ ++ ++static int samplerate=44100; ++ ++static int snd_rpi_hifiberry_digi_init(struct snd_soc_pcm_runtime *rtd) ++{ ++ struct snd_soc_codec *codec = rtd->codec; ++ ++ /* enable TX output */ ++ snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, 0x0); ++ ++ return 0; ++} ++ ++static int snd_rpi_hifiberry_digi_startup(struct snd_pcm_substream *substream) { ++ /* turn on digital output */ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_codec *codec = rtd->codec; ++ snd_soc_update_bits(codec, WM8804_PWRDN, 0x3c, 0x00); ++ return 0; ++} ++ ++static void snd_rpi_hifiberry_digi_shutdown(struct snd_pcm_substream *substream) { ++ /* turn off output */ ++ if (auto_shutdown_output) { ++ /* turn off output */ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_codec *codec = rtd->codec; ++ snd_soc_update_bits(codec, WM8804_PWRDN, 0x3c, 0x3c); ++ } ++} ++ ++ ++static int snd_rpi_hifiberry_digi_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_dai *codec_dai = rtd->codec_dai; ++ struct snd_soc_codec *codec = rtd->codec; ++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai; ++ ++ int sysclk = 27000000; /* This is fixed on this board */ ++ ++ long mclk_freq=0; ++ int mclk_div=1; ++ int sampling_freq=1; ++ ++ int ret; ++ ++ samplerate = params_rate(params); ++ ++ if (samplerate<=96000) { ++ mclk_freq=samplerate*256; ++ mclk_div=WM8804_MCLKDIV_256FS; ++ } else { ++ mclk_freq=samplerate*128; ++ mclk_div=WM8804_MCLKDIV_128FS; ++ } ++ ++ switch (samplerate) { ++ case 32000: ++ sampling_freq=0x03; ++ break; ++ case 44100: ++ sampling_freq=0x00; ++ break; ++ case 48000: ++ sampling_freq=0x02; ++ break; ++ case 88200: ++ sampling_freq=0x08; ++ break; ++ case 96000: ++ sampling_freq=0x0a; ++ break; ++ case 176400: ++ sampling_freq=0x0c; ++ break; ++ case 192000: ++ sampling_freq=0x0e; ++ break; ++ default: ++ dev_err(codec->dev, ++ "Failed to set WM8804 SYSCLK, unsupported samplerate %d\n", ++ samplerate); ++ } ++ ++ snd_soc_dai_set_clkdiv(codec_dai, WM8804_MCLK_DIV, mclk_div); ++ snd_soc_dai_set_pll(codec_dai, 0, 0, sysclk, mclk_freq); ++ ++ ret = snd_soc_dai_set_sysclk(codec_dai, WM8804_TX_CLKSRC_PLL, ++ sysclk, SND_SOC_CLOCK_OUT); ++ if (ret < 0) { ++ dev_err(codec->dev, ++ "Failed to set WM8804 SYSCLK: %d\n", ret); ++ return ret; ++ } ++ ++ /* Enable TX output */ ++ snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, 0x0); ++ ++ /* Power on */ ++ snd_soc_update_bits(codec, WM8804_PWRDN, 0x9, 0); ++ ++ /* set sampling frequency status bits */ ++ snd_soc_update_bits(codec, WM8804_SPDTX4, 0x0f, sampling_freq); ++ ++ return snd_soc_dai_set_bclk_ratio(cpu_dai,64); ++} ++ ++/* machine stream operations */ ++static struct snd_soc_ops snd_rpi_hifiberry_digi_ops = { ++ .hw_params = snd_rpi_hifiberry_digi_hw_params, ++ .startup = snd_rpi_hifiberry_digi_startup, ++ .shutdown = snd_rpi_hifiberry_digi_shutdown, ++}; ++ ++static struct snd_soc_dai_link snd_rpi_hifiberry_digi_dai[] = { ++{ ++ .name = "HifiBerry Digi", ++ .stream_name = "HifiBerry Digi HiFi", ++ .cpu_dai_name = "bcm2708-i2s.0", ++ .codec_dai_name = "wm8804-spdif", ++ .platform_name = "bcm2708-i2s.0", ++ .codec_name = "wm8804.1-003b", ++ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBM_CFM, ++ .ops = &snd_rpi_hifiberry_digi_ops, ++ .init = snd_rpi_hifiberry_digi_init, ++}, ++}; ++ ++/* audio machine driver */ ++static struct snd_soc_card snd_rpi_hifiberry_digi = { ++ .name = "snd_rpi_hifiberry_digi", ++ .dai_link = snd_rpi_hifiberry_digi_dai, ++ .num_links = ARRAY_SIZE(snd_rpi_hifiberry_digi_dai), ++}; ++ ++static int snd_rpi_hifiberry_digi_probe(struct platform_device *pdev) ++{ ++ int ret = 0; ++ ++ snd_rpi_hifiberry_digi.dev = &pdev->dev; ++ ++ if (pdev->dev.of_node) { ++ struct device_node *i2s_node; ++ struct snd_soc_dai_link *dai = &snd_rpi_hifiberry_digi_dai[0]; ++ i2s_node = of_parse_phandle(pdev->dev.of_node, ++ "i2s-controller", 0); ++ ++ if (i2s_node) { ++ dai->cpu_dai_name = NULL; ++ dai->cpu_of_node = i2s_node; ++ dai->platform_name = NULL; ++ dai->platform_of_node = i2s_node; ++ } ++ } ++ ++ ret = snd_soc_register_card(&snd_rpi_hifiberry_digi); ++ if (ret) ++ dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret); ++ ++ return ret; ++} ++ ++static int snd_rpi_hifiberry_digi_remove(struct platform_device *pdev) ++{ ++ return snd_soc_unregister_card(&snd_rpi_hifiberry_digi); ++} ++ ++static const struct of_device_id snd_rpi_hifiberry_digi_of_match[] = { ++ { .compatible = "hifiberry,hifiberry-digi", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, snd_rpi_hifiberry_digi_of_match); ++ ++static struct platform_driver snd_rpi_hifiberry_digi_driver = { ++ .driver = { ++ .name = "snd-hifiberry-digi", ++ .owner = THIS_MODULE, ++ .of_match_table = snd_rpi_hifiberry_digi_of_match, ++ }, ++ .probe = snd_rpi_hifiberry_digi_probe, ++ .remove = snd_rpi_hifiberry_digi_remove, ++}; ++ ++module_platform_driver(snd_rpi_hifiberry_digi_driver); ++ ++MODULE_AUTHOR("Daniel Matuschek "); ++MODULE_DESCRIPTION("ASoC Driver for HifiBerry Digi"); ++MODULE_LICENSE("GPL v2"); +diff -Nur linux-4.1.13.orig/sound/soc/bcm/iqaudio-dac.c linux-rpi/sound/soc/bcm/iqaudio-dac.c +--- linux-4.1.13.orig/sound/soc/bcm/iqaudio-dac.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/sound/soc/bcm/iqaudio-dac.c 2015-11-29 09:42:41.558989731 +0100 +@@ -0,0 +1,133 @@ ++/* ++ * ASoC Driver for IQaudIO DAC ++ * ++ * Author: Florian Meier ++ * Copyright 2013 ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ */ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++static int snd_rpi_iqaudio_dac_init(struct snd_soc_pcm_runtime *rtd) ++{ ++ int ret; ++ struct snd_soc_card *card = rtd->card; ++ struct snd_soc_codec *codec = rtd->codec; ++ ++ ret = snd_soc_limit_volume(codec, "Digital Playback Volume", 207); ++ if (ret < 0) ++ dev_warn(card->dev, "Failed to set volume limit: %d\n", ret); ++ ++ return 0; ++} ++ ++static int snd_rpi_iqaudio_dac_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++// NOT USED struct snd_soc_dai *codec_dai = rtd->codec_dai; ++// NOT USED struct snd_soc_codec *codec = rtd->codec; ++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai; ++ ++ unsigned int sample_bits = ++ snd_pcm_format_physical_width(params_format(params)); ++ ++ return snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2); ++} ++ ++/* machine stream operations */ ++static struct snd_soc_ops snd_rpi_iqaudio_dac_ops = { ++ .hw_params = snd_rpi_iqaudio_dac_hw_params, ++}; ++ ++static struct snd_soc_dai_link snd_rpi_iqaudio_dac_dai[] = { ++{ ++ .name = "IQaudIO DAC", ++ .stream_name = "IQaudIO DAC HiFi", ++ .cpu_dai_name = "bcm2708-i2s.0", ++ .codec_dai_name = "pcm512x-hifi", ++ .platform_name = "bcm2708-i2s.0", ++ .codec_name = "pcm512x.1-004c", ++ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBS_CFS, ++ .ops = &snd_rpi_iqaudio_dac_ops, ++ .init = snd_rpi_iqaudio_dac_init, ++}, ++}; ++ ++/* audio machine driver */ ++static struct snd_soc_card snd_rpi_iqaudio_dac = { ++ .name = "IQaudIODAC", ++ .dai_link = snd_rpi_iqaudio_dac_dai, ++ .num_links = ARRAY_SIZE(snd_rpi_iqaudio_dac_dai), ++}; ++ ++static int snd_rpi_iqaudio_dac_probe(struct platform_device *pdev) ++{ ++ int ret = 0; ++ ++ snd_rpi_iqaudio_dac.dev = &pdev->dev; ++ ++ if (pdev->dev.of_node) { ++ struct device_node *i2s_node; ++ struct snd_soc_dai_link *dai = &snd_rpi_iqaudio_dac_dai[0]; ++ i2s_node = of_parse_phandle(pdev->dev.of_node, ++ "i2s-controller", 0); ++ ++ if (i2s_node) { ++ dai->cpu_dai_name = NULL; ++ dai->cpu_of_node = i2s_node; ++ dai->platform_name = NULL; ++ dai->platform_of_node = i2s_node; ++ } ++ } ++ ++ ret = snd_soc_register_card(&snd_rpi_iqaudio_dac); ++ if (ret) ++ dev_err(&pdev->dev, ++ "snd_soc_register_card() failed: %d\n", ret); ++ ++ return ret; ++} ++ ++static int snd_rpi_iqaudio_dac_remove(struct platform_device *pdev) ++{ ++ return snd_soc_unregister_card(&snd_rpi_iqaudio_dac); ++} ++ ++static const struct of_device_id iqaudio_of_match[] = { ++ { .compatible = "iqaudio,iqaudio-dac", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, iqaudio_of_match); ++ ++static struct platform_driver snd_rpi_iqaudio_dac_driver = { ++ .driver = { ++ .name = "snd-rpi-iqaudio-dac", ++ .owner = THIS_MODULE, ++ .of_match_table = iqaudio_of_match, ++ }, ++ .probe = snd_rpi_iqaudio_dac_probe, ++ .remove = snd_rpi_iqaudio_dac_remove, ++}; ++ ++module_platform_driver(snd_rpi_iqaudio_dac_driver); ++ ++MODULE_AUTHOR("Florian Meier "); ++MODULE_DESCRIPTION("ASoC Driver for IQAudio DAC"); ++MODULE_LICENSE("GPL v2"); +diff -Nur linux-4.1.13.orig/sound/soc/bcm/Kconfig linux-rpi/sound/soc/bcm/Kconfig +--- linux-4.1.13.orig/sound/soc/bcm/Kconfig 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/sound/soc/bcm/Kconfig 2015-11-29 09:42:41.558989731 +0100 +@@ -7,3 +7,71 @@ + Say Y or M if you want to add support for codecs attached to + the BCM2835 I2S interface. You will also need + to select the audio interfaces to support below. ++ ++config SND_BCM2708_SOC_I2S ++ tristate "SoC Audio support for the Broadcom BCM2708 I2S module" ++ depends on MACH_BCM2708 || MACH_BCM2709 ++ select REGMAP_MMIO ++ select SND_SOC_DMAENGINE_PCM ++ select SND_SOC_GENERIC_DMAENGINE_PCM ++ help ++ Say Y or M if you want to add support for codecs attached to ++ the BCM2708 I2S interface. You will also need ++ to select the audio interfaces to support below. ++ ++config SND_BCM2708_SOC_HIFIBERRY_DAC ++ tristate "Support for HifiBerry DAC" ++ depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S ++ select SND_SOC_PCM5102A ++ help ++ Say Y or M if you want to add support for HifiBerry DAC. ++ ++config SND_BCM2708_SOC_HIFIBERRY_DACPLUS ++ tristate "Support for HifiBerry DAC+" ++ depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S ++ select SND_SOC_PCM512x ++ help ++ Say Y or M if you want to add support for HifiBerry DAC+. ++ ++config SND_BCM2708_SOC_HIFIBERRY_DIGI ++ tristate "Support for HifiBerry Digi" ++ depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S ++ select SND_SOC_WM8804 ++ help ++ Say Y or M if you want to add support for HifiBerry Digi S/PDIF output board. ++ ++config SND_BCM2708_SOC_HIFIBERRY_AMP ++ tristate "Support for the HifiBerry Amp" ++ depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S ++ select SND_SOC_TAS5713 ++ help ++ Say Y or M if you want to add support for the HifiBerry Amp amplifier board. ++ ++config SND_BCM2708_SOC_RPI_DAC ++ tristate "Support for RPi-DAC" ++ depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S ++ select SND_SOC_PCM1794A ++ help ++ Say Y or M if you want to add support for RPi-DAC. ++ ++config SND_BCM2708_SOC_RPI_PROTO ++ tristate "Support for Rpi-PROTO" ++ depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S ++ select SND_SOC_WM8731 ++ help ++ Say Y or M if you want to add support for Audio Codec Board PROTO (WM8731). ++ ++config SND_BCM2708_SOC_IQAUDIO_DAC ++ tristate "Support for IQaudIO-DAC" ++ depends on SND_BCM2708_SOC_I2S || SND_BCM2835_SOC_I2S ++ select SND_SOC_PCM512x_I2C ++ help ++ Say Y or M if you want to add support for IQaudIO-DAC. ++ ++config SND_BCM2708_SOC_RASPIDAC3 ++ tristate "Support for RaspiDAC Rev.3x" ++ depends on SND_BCM2708_SOC_I2S ++ select SND_SOC_PCM512x_I2C ++ select SND_SOC_TPA6130A2 ++ help ++ Say Y or M if you want to add support for RaspiDAC Rev.3x. +diff -Nur linux-4.1.13.orig/sound/soc/bcm/Makefile linux-rpi/sound/soc/bcm/Makefile +--- linux-4.1.13.orig/sound/soc/bcm/Makefile 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/sound/soc/bcm/Makefile 2015-11-29 09:42:41.558989731 +0100 +@@ -3,3 +3,26 @@ + + obj-$(CONFIG_SND_BCM2835_SOC_I2S) += snd-soc-bcm2835-i2s.o + ++# BCM2708 Platform Support ++snd-soc-bcm2708-i2s-objs := bcm2708-i2s.o ++ ++obj-$(CONFIG_SND_BCM2708_SOC_I2S) += snd-soc-bcm2708-i2s.o ++ ++# BCM2708 Machine Support ++snd-soc-hifiberry-dac-objs := hifiberry_dac.o ++snd-soc-hifiberry-dacplus-objs := hifiberry_dacplus.o ++snd-soc-hifiberry-digi-objs := hifiberry_digi.o ++snd-soc-hifiberry-amp-objs := hifiberry_amp.o ++snd-soc-rpi-dac-objs := rpi-dac.o ++snd-soc-rpi-proto-objs := rpi-proto.o ++snd-soc-iqaudio-dac-objs := iqaudio-dac.o ++snd-soc-raspidac3-objs := raspidac3.o ++ ++obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) += snd-soc-hifiberry-dac.o ++obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) += snd-soc-hifiberry-dacplus.o ++obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) += snd-soc-hifiberry-digi.o ++obj-$(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) += snd-soc-hifiberry-amp.o ++obj-$(CONFIG_SND_BCM2708_SOC_RPI_DAC) += snd-soc-rpi-dac.o ++obj-$(CONFIG_SND_BCM2708_SOC_RPI_PROTO) += snd-soc-rpi-proto.o ++obj-$(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) += snd-soc-iqaudio-dac.o ++obj-$(CONFIG_SND_BCM2708_SOC_RASPIDAC3) += snd-soc-raspidac3.o +diff -Nur linux-4.1.13.orig/sound/soc/bcm/raspidac3.c linux-rpi/sound/soc/bcm/raspidac3.c +--- linux-4.1.13.orig/sound/soc/bcm/raspidac3.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/sound/soc/bcm/raspidac3.c 2015-11-29 09:42:41.558989731 +0100 +@@ -0,0 +1,191 @@ ++/* ++ * ASoC Driver for RaspiDAC v3 ++ * ++ * Author: Jan Grulich ++ * Copyright 2015 ++ * based on code by Daniel Matuschek ++ * based on code by Florian Meier ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ */ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "../codecs/pcm512x.h" ++#include "../codecs/tpa6130a2.h" ++ ++/* sound card init */ ++static int snd_rpi_raspidac3_init(struct snd_soc_pcm_runtime *rtd) ++{ ++ int ret; ++ struct snd_soc_card *card = rtd->card; ++ struct snd_soc_codec *codec = rtd->codec; ++ snd_soc_update_bits(codec, PCM512x_GPIO_EN, 0x08, 0x08); ++ snd_soc_update_bits(codec, PCM512x_GPIO_OUTPUT_4, 0xf, 0x02); ++ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x00); ++ ++ ret = snd_soc_limit_volume(codec, "Digital Playback Volume", 207); ++ if (ret < 0) ++ dev_warn(card->dev, "Failed to set volume limit: %d\n", ret); ++ else { ++ struct snd_kcontrol *kctl; ++ ++ ret = tpa6130a2_add_controls(codec); ++ if (ret < 0) ++ dev_warn(card->dev, "Failed to add TPA6130A2 controls: %d\n", ++ ret); ++ ret = snd_soc_limit_volume(codec, ++ "TPA6130A2 Headphone Playback Volume", ++ 54); ++ if (ret < 0) ++ dev_warn(card->dev, "Failed to set TPA6130A2 volume limit: %d\n", ++ ret); ++ kctl = snd_soc_card_get_kcontrol(card, ++ "TPA6130A2 Headphone Playback Volume"); ++ if (kctl) { ++ strcpy(kctl->id.name, "Headphones Playback Volume"); ++ /* disable the volume dB scale so alsamixer works */ ++ kctl->vd[0].access = SNDRV_CTL_ELEM_ACCESS_READWRITE; ++ } ++ ++ kctl = snd_soc_card_get_kcontrol(card, ++ "TPA6130A2 Headphone Playback Switch"); ++ if (kctl) ++ strcpy(kctl->id.name, "Headphones Playback Switch"); ++ } ++ ++ return 0; ++} ++ ++/* set hw parameters */ ++static int snd_rpi_raspidac3_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai; ++ ++ unsigned int sample_bits = ++ snd_pcm_format_physical_width(params_format(params)); ++ ++ return snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2); ++} ++ ++/* startup */ ++static int snd_rpi_raspidac3_startup(struct snd_pcm_substream *substream) { ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_codec *codec = rtd->codec; ++ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x08); ++ tpa6130a2_stereo_enable(codec, 1); ++ return 0; ++} ++ ++/* shutdown */ ++static void snd_rpi_raspidac3_shutdown(struct snd_pcm_substream *substream) { ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_codec *codec = rtd->codec; ++ snd_soc_update_bits(codec, PCM512x_GPIO_CONTROL_1, 0x08,0x00); ++ tpa6130a2_stereo_enable(codec, 0); ++} ++ ++/* machine stream operations */ ++static struct snd_soc_ops snd_rpi_raspidac3_ops = { ++ .hw_params = snd_rpi_raspidac3_hw_params, ++ .startup = snd_rpi_raspidac3_startup, ++ .shutdown = snd_rpi_raspidac3_shutdown, ++}; ++ ++/* interface setup */ ++static struct snd_soc_dai_link snd_rpi_raspidac3_dai[] = { ++{ ++ .name = "RaspiDAC Rev.3x", ++ .stream_name = "RaspiDAC HiFi", ++ .cpu_dai_name = "bcm2708-i2s.0", ++ .codec_dai_name = "pcm512x-hifi", ++ .platform_name = "bcm2708-i2s.0", ++ .codec_name = "pcm512x.1-004c", ++ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBS_CFS, ++ .ops = &snd_rpi_raspidac3_ops, ++ .init = snd_rpi_raspidac3_init, ++}, ++}; ++ ++/* audio machine driver */ ++static struct snd_soc_card snd_rpi_raspidac3 = { ++ .name = "RaspiDAC Rev.3x HiFi Audio Card", ++ .dai_link = snd_rpi_raspidac3_dai, ++ .num_links = ARRAY_SIZE(snd_rpi_raspidac3_dai), ++}; ++ ++/* sound card test */ ++static int snd_rpi_raspidac3_probe(struct platform_device *pdev) ++{ ++ int ret = 0; ++ ++ snd_rpi_raspidac3.dev = &pdev->dev; ++ ++ if (pdev->dev.of_node) { ++ struct device_node *i2s_node; ++ struct snd_soc_dai_link *dai = &snd_rpi_raspidac3_dai[0]; ++ i2s_node = of_parse_phandle(pdev->dev.of_node, ++ "i2s-controller", 0); ++ ++ if (i2s_node) { ++ dai->cpu_dai_name = NULL; ++ dai->cpu_of_node = i2s_node; ++ dai->platform_name = NULL; ++ dai->platform_of_node = i2s_node; ++ } ++ } ++ ++ ret = snd_soc_register_card(&snd_rpi_raspidac3); ++ if (ret) ++ dev_err(&pdev->dev, ++ "snd_soc_register_card() failed: %d\n", ret); ++ ++ return ret; ++} ++ ++/* sound card disconnect */ ++static int snd_rpi_raspidac3_remove(struct platform_device *pdev) ++{ ++ return snd_soc_unregister_card(&snd_rpi_raspidac3); ++} ++ ++static const struct of_device_id raspidac3_of_match[] = { ++ { .compatible = "jg,raspidacv3", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, raspidac3_of_match); ++ ++/* sound card platform driver */ ++static struct platform_driver snd_rpi_raspidac3_driver = { ++ .driver = { ++ .name = "snd-rpi-raspidac3", ++ .owner = THIS_MODULE, ++ .of_match_table = raspidac3_of_match, ++ }, ++ .probe = snd_rpi_raspidac3_probe, ++ .remove = snd_rpi_raspidac3_remove, ++}; ++ ++module_platform_driver(snd_rpi_raspidac3_driver); ++ ++MODULE_AUTHOR("Jan Grulich "); ++MODULE_DESCRIPTION("ASoC Driver for RaspiDAC Rev.3x"); ++MODULE_LICENSE("GPL v2"); +diff -Nur linux-4.1.13.orig/sound/soc/bcm/rpi-dac.c linux-rpi/sound/soc/bcm/rpi-dac.c +--- linux-4.1.13.orig/sound/soc/bcm/rpi-dac.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/sound/soc/bcm/rpi-dac.c 2015-11-29 09:42:41.558989731 +0100 +@@ -0,0 +1,118 @@ ++/* ++ * ASoC Driver for RPi-DAC. ++ * ++ * Author: Florian Meier ++ * Copyright 2013 ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ */ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++static int snd_rpi_rpi_dac_init(struct snd_soc_pcm_runtime *rtd) ++{ ++ return 0; ++} ++ ++static int snd_rpi_rpi_dac_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai; ++ ++ return snd_soc_dai_set_bclk_ratio(cpu_dai, 32*2); ++} ++ ++/* machine stream operations */ ++static struct snd_soc_ops snd_rpi_rpi_dac_ops = { ++ .hw_params = snd_rpi_rpi_dac_hw_params, ++}; ++ ++static struct snd_soc_dai_link snd_rpi_rpi_dac_dai[] = { ++{ ++ .name = "RPi-DAC", ++ .stream_name = "RPi-DAC HiFi", ++ .cpu_dai_name = "bcm2708-i2s.0", ++ .codec_dai_name = "pcm1794a-hifi", ++ .platform_name = "bcm2708-i2s.0", ++ .codec_name = "pcm1794a-codec", ++ .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | ++ SND_SOC_DAIFMT_CBS_CFS, ++ .ops = &snd_rpi_rpi_dac_ops, ++ .init = snd_rpi_rpi_dac_init, ++}, ++}; ++ ++/* audio machine driver */ ++static struct snd_soc_card snd_rpi_rpi_dac = { ++ .name = "snd_rpi_rpi_dac", ++ .dai_link = snd_rpi_rpi_dac_dai, ++ .num_links = ARRAY_SIZE(snd_rpi_rpi_dac_dai), ++}; ++ ++static int snd_rpi_rpi_dac_probe(struct platform_device *pdev) ++{ ++ int ret = 0; ++ ++ snd_rpi_rpi_dac.dev = &pdev->dev; ++ ++ if (pdev->dev.of_node) { ++ struct device_node *i2s_node; ++ struct snd_soc_dai_link *dai = &snd_rpi_rpi_dac_dai[0]; ++ i2s_node = of_parse_phandle(pdev->dev.of_node, "i2s-controller", 0); ++ ++ if (i2s_node) { ++ dai->cpu_dai_name = NULL; ++ dai->cpu_of_node = i2s_node; ++ dai->platform_name = NULL; ++ dai->platform_of_node = i2s_node; ++ } ++ } ++ ++ ret = snd_soc_register_card(&snd_rpi_rpi_dac); ++ if (ret) ++ dev_err(&pdev->dev, "snd_soc_register_card() failed: %d\n", ret); ++ ++ return ret; ++} ++ ++static int snd_rpi_rpi_dac_remove(struct platform_device *pdev) ++{ ++ return snd_soc_unregister_card(&snd_rpi_rpi_dac); ++} ++ ++static const struct of_device_id snd_rpi_rpi_dac_of_match[] = { ++ { .compatible = "rpi,rpi-dac", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, snd_rpi_rpi_dac_of_match); ++ ++static struct platform_driver snd_rpi_rpi_dac_driver = { ++ .driver = { ++ .name = "snd-rpi-dac", ++ .owner = THIS_MODULE, ++ .of_match_table = snd_rpi_rpi_dac_of_match, ++ }, ++ .probe = snd_rpi_rpi_dac_probe, ++ .remove = snd_rpi_rpi_dac_remove, ++}; ++ ++module_platform_driver(snd_rpi_rpi_dac_driver); ++ ++MODULE_AUTHOR("Florian Meier "); ++MODULE_DESCRIPTION("ASoC Driver for RPi-DAC"); ++MODULE_LICENSE("GPL v2"); +diff -Nur linux-4.1.13.orig/sound/soc/bcm/rpi-proto.c linux-rpi/sound/soc/bcm/rpi-proto.c +--- linux-4.1.13.orig/sound/soc/bcm/rpi-proto.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/sound/soc/bcm/rpi-proto.c 2015-11-29 09:42:41.558989731 +0100 +@@ -0,0 +1,153 @@ ++/* ++ * ASoC driver for PROTO AudioCODEC (with a WM8731) ++ * connected to a Raspberry Pi ++ * ++ * Author: Florian Meier, ++ * Copyright 2013 ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "../codecs/wm8731.h" ++ ++static const unsigned int wm8731_rates_12288000[] = { ++ 8000, 32000, 48000, 96000, ++}; ++ ++static struct snd_pcm_hw_constraint_list wm8731_constraints_12288000 = { ++ .list = wm8731_rates_12288000, ++ .count = ARRAY_SIZE(wm8731_rates_12288000), ++}; ++ ++static int snd_rpi_proto_startup(struct snd_pcm_substream *substream) ++{ ++ /* Setup constraints, because there is a 12.288 MHz XTAL on the board */ ++ snd_pcm_hw_constraint_list(substream->runtime, 0, ++ SNDRV_PCM_HW_PARAM_RATE, ++ &wm8731_constraints_12288000); ++ return 0; ++} ++ ++static int snd_rpi_proto_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = substream->private_data; ++ struct snd_soc_codec *codec = rtd->codec; ++ struct snd_soc_dai *codec_dai = rtd->codec_dai; ++ struct snd_soc_dai *cpu_dai = rtd->cpu_dai; ++ int sysclk = 12288000; /* This is fixed on this board */ ++ ++ /* Set proto bclk */ ++ int ret = snd_soc_dai_set_bclk_ratio(cpu_dai,32*2); ++ if (ret < 0){ ++ dev_err(codec->dev, ++ "Failed to set BCLK ratio %d\n", ret); ++ return ret; ++ } ++ ++ /* Set proto sysclk */ ++ ret = snd_soc_dai_set_sysclk(codec_dai, WM8731_SYSCLK_XTAL, ++ sysclk, SND_SOC_CLOCK_IN); ++ if (ret < 0) { ++ dev_err(codec->dev, ++ "Failed to set WM8731 SYSCLK: %d\n", ret); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++/* machine stream operations */ ++static struct snd_soc_ops snd_rpi_proto_ops = { ++ .startup = snd_rpi_proto_startup, ++ .hw_params = snd_rpi_proto_hw_params, ++}; ++ ++static struct snd_soc_dai_link snd_rpi_proto_dai[] = { ++{ ++ .name = "WM8731", ++ .stream_name = "WM8731 HiFi", ++ .cpu_dai_name = "bcm2708-i2s.0", ++ .codec_dai_name = "wm8731-hifi", ++ .platform_name = "bcm2708-i2s.0", ++ .codec_name = "wm8731.1-001a", ++ .dai_fmt = SND_SOC_DAIFMT_I2S ++ | SND_SOC_DAIFMT_NB_NF ++ | SND_SOC_DAIFMT_CBM_CFM, ++ .ops = &snd_rpi_proto_ops, ++}, ++}; ++ ++/* audio machine driver */ ++static struct snd_soc_card snd_rpi_proto = { ++ .name = "snd_rpi_proto", ++ .dai_link = snd_rpi_proto_dai, ++ .num_links = ARRAY_SIZE(snd_rpi_proto_dai), ++}; ++ ++static int snd_rpi_proto_probe(struct platform_device *pdev) ++{ ++ int ret = 0; ++ ++ snd_rpi_proto.dev = &pdev->dev; ++ ++ if (pdev->dev.of_node) { ++ struct device_node *i2s_node; ++ struct snd_soc_dai_link *dai = &snd_rpi_proto_dai[0]; ++ i2s_node = of_parse_phandle(pdev->dev.of_node, ++ "i2s-controller", 0); ++ ++ if (i2s_node) { ++ dai->cpu_dai_name = NULL; ++ dai->cpu_of_node = i2s_node; ++ dai->platform_name = NULL; ++ dai->platform_of_node = i2s_node; ++ } ++ } ++ ++ ret = snd_soc_register_card(&snd_rpi_proto); ++ if (ret) { ++ dev_err(&pdev->dev, ++ "snd_soc_register_card() failed: %d\n", ret); ++ } ++ ++ return ret; ++} ++ ++ ++static int snd_rpi_proto_remove(struct platform_device *pdev) ++{ ++ return snd_soc_unregister_card(&snd_rpi_proto); ++} ++ ++static const struct of_device_id snd_rpi_proto_of_match[] = { ++ { .compatible = "rpi,rpi-proto", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, snd_rpi_proto_of_match); ++ ++static struct platform_driver snd_rpi_proto_driver = { ++ .driver = { ++ .name = "snd-rpi-proto", ++ .owner = THIS_MODULE, ++ .of_match_table = snd_rpi_proto_of_match, ++ }, ++ .probe = snd_rpi_proto_probe, ++ .remove = snd_rpi_proto_remove, ++}; ++ ++module_platform_driver(snd_rpi_proto_driver); ++ ++MODULE_AUTHOR("Florian Meier"); ++MODULE_DESCRIPTION("ASoC Driver for Raspberry Pi connected to PROTO board (WM8731)"); ++MODULE_LICENSE("GPL"); +diff -Nur linux-4.1.13.orig/sound/soc/codecs/Kconfig linux-rpi/sound/soc/codecs/Kconfig +--- linux-4.1.13.orig/sound/soc/codecs/Kconfig 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/sound/soc/codecs/Kconfig 2015-11-29 09:42:41.562989466 +0100 +@@ -83,6 +83,8 @@ + select SND_SOC_PCM512x_I2C if I2C + select SND_SOC_PCM512x_SPI if SPI_MASTER + select SND_SOC_RT286 if I2C ++ select SND_SOC_PCM5102A if I2C ++ select SND_SOC_PCM1794A if I2C + select SND_SOC_RT5631 if I2C + select SND_SOC_RT5640 if I2C + select SND_SOC_RT5645 if I2C +@@ -107,6 +109,7 @@ + select SND_SOC_TFA9879 if I2C + select SND_SOC_TLV320AIC23_I2C if I2C + select SND_SOC_TLV320AIC23_SPI if SPI_MASTER ++ select SND_SOC_TAS5713 if I2C + select SND_SOC_TLV320AIC26 if SPI_MASTER + select SND_SOC_TLV320AIC31XX if I2C + select SND_SOC_TLV320AIC32X4 if I2C +@@ -511,6 +514,12 @@ + tristate + depends on I2C + ++config SND_SOC_PCM1794A ++ tristate ++ ++config SND_SOC_PCM5102A ++ tristate ++ + config SND_SOC_RT5631 + tristate "Realtek ALC5631/RT5631 CODEC" + depends on I2C +@@ -615,6 +624,9 @@ + tristate "NXP Semiconductors TFA9879 amplifier" + depends on I2C + ++config SND_SOC_TAS5713 ++ tristate ++ + config SND_SOC_TLV320AIC23 + tristate + +diff -Nur linux-4.1.13.orig/sound/soc/codecs/Makefile linux-rpi/sound/soc/codecs/Makefile +--- linux-4.1.13.orig/sound/soc/codecs/Makefile 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/sound/soc/codecs/Makefile 2015-11-29 09:42:41.562989466 +0100 +@@ -78,6 +78,8 @@ + snd-soc-pcm512x-spi-objs := pcm512x-spi.o + snd-soc-rl6231-objs := rl6231.o + snd-soc-rt286-objs := rt286.o ++snd-soc-pcm1794a-objs := pcm1794a.o ++snd-soc-pcm5102a-objs := pcm5102a.o + snd-soc-rt5631-objs := rt5631.o + snd-soc-rt5640-objs := rt5640.o + snd-soc-rt5645-objs := rt5645.o +@@ -107,6 +109,7 @@ + snd-soc-stac9766-objs := stac9766.o + snd-soc-tas5086-objs := tas5086.o + snd-soc-tfa9879-objs := tfa9879.o ++snd-soc-tas5713-objs := tas5713.o + snd-soc-tlv320aic23-objs := tlv320aic23.o + snd-soc-tlv320aic23-i2c-objs := tlv320aic23-i2c.o + snd-soc-tlv320aic23-spi-objs := tlv320aic23-spi.o +@@ -263,6 +266,8 @@ + obj-$(CONFIG_SND_SOC_PCM512x_SPI) += snd-soc-pcm512x-spi.o + obj-$(CONFIG_SND_SOC_RL6231) += snd-soc-rl6231.o + obj-$(CONFIG_SND_SOC_RT286) += snd-soc-rt286.o ++obj-$(CONFIG_SND_SOC_PCM1794A) += snd-soc-pcm1794a.o ++obj-$(CONFIG_SND_SOC_PCM5102A) += snd-soc-pcm5102a.o + obj-$(CONFIG_SND_SOC_RT5631) += snd-soc-rt5631.o + obj-$(CONFIG_SND_SOC_RT5640) += snd-soc-rt5640.o + obj-$(CONFIG_SND_SOC_RT5645) += snd-soc-rt5645.o +@@ -289,6 +294,7 @@ + obj-$(CONFIG_SND_SOC_TAS2552) += snd-soc-tas2552.o + obj-$(CONFIG_SND_SOC_TAS5086) += snd-soc-tas5086.o + obj-$(CONFIG_SND_SOC_TFA9879) += snd-soc-tfa9879.o ++obj-$(CONFIG_SND_SOC_TAS5713) += snd-soc-tas5713.o + obj-$(CONFIG_SND_SOC_TLV320AIC23) += snd-soc-tlv320aic23.o + obj-$(CONFIG_SND_SOC_TLV320AIC23_I2C) += snd-soc-tlv320aic23-i2c.o + obj-$(CONFIG_SND_SOC_TLV320AIC23_SPI) += snd-soc-tlv320aic23-spi.o +diff -Nur linux-4.1.13.orig/sound/soc/codecs/pcm1794a.c linux-rpi/sound/soc/codecs/pcm1794a.c +--- linux-4.1.13.orig/sound/soc/codecs/pcm1794a.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/sound/soc/codecs/pcm1794a.c 2015-11-29 09:42:41.574988668 +0100 +@@ -0,0 +1,69 @@ ++/* ++ * Driver for the PCM1794A codec ++ * ++ * Author: Florian Meier ++ * Copyright 2013 ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ */ ++ ++ ++#include ++#include ++#include ++ ++#include ++ ++static struct snd_soc_dai_driver pcm1794a_dai = { ++ .name = "pcm1794a-hifi", ++ .playback = { ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = SNDRV_PCM_RATE_8000_192000, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE | ++ SNDRV_PCM_FMTBIT_S24_LE ++ }, ++}; ++ ++static struct snd_soc_codec_driver soc_codec_dev_pcm1794a; ++ ++static int pcm1794a_probe(struct platform_device *pdev) ++{ ++ return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_pcm1794a, ++ &pcm1794a_dai, 1); ++} ++ ++static int pcm1794a_remove(struct platform_device *pdev) ++{ ++ snd_soc_unregister_codec(&pdev->dev); ++ return 0; ++} ++ ++static const struct of_device_id pcm1794a_of_match[] = { ++ { .compatible = "ti,pcm1794a", }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, pcm1794a_of_match); ++ ++static struct platform_driver pcm1794a_codec_driver = { ++ .probe = pcm1794a_probe, ++ .remove = pcm1794a_remove, ++ .driver = { ++ .name = "pcm1794a-codec", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(pcm1794a_of_match), ++ }, ++}; ++ ++module_platform_driver(pcm1794a_codec_driver); ++ ++MODULE_DESCRIPTION("ASoC PCM1794A codec driver"); ++MODULE_AUTHOR("Florian Meier "); ++MODULE_LICENSE("GPL v2"); +diff -Nur linux-4.1.13.orig/sound/soc/codecs/pcm5102a.c linux-rpi/sound/soc/codecs/pcm5102a.c +--- linux-4.1.13.orig/sound/soc/codecs/pcm5102a.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/sound/soc/codecs/pcm5102a.c 2015-11-29 09:42:41.574988668 +0100 +@@ -0,0 +1,70 @@ ++/* ++ * Driver for the PCM5102A codec ++ * ++ * Author: Florian Meier ++ * Copyright 2013 ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ */ ++ ++ ++#include ++#include ++#include ++ ++#include ++ ++static struct snd_soc_dai_driver pcm5102a_dai = { ++ .name = "pcm5102a-hifi", ++ .playback = { ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = SNDRV_PCM_RATE_8000_192000, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE | ++ SNDRV_PCM_FMTBIT_S24_LE | ++ SNDRV_PCM_FMTBIT_S32_LE ++ }, ++}; ++ ++static struct snd_soc_codec_driver soc_codec_dev_pcm5102a; ++ ++static int pcm5102a_probe(struct platform_device *pdev) ++{ ++ return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_pcm5102a, ++ &pcm5102a_dai, 1); ++} ++ ++static int pcm5102a_remove(struct platform_device *pdev) ++{ ++ snd_soc_unregister_codec(&pdev->dev); ++ return 0; ++} ++ ++static const struct of_device_id pcm5102a_of_match[] = { ++ { .compatible = "ti,pcm5102a", }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, pcm5102a_of_match); ++ ++static struct platform_driver pcm5102a_codec_driver = { ++ .probe = pcm5102a_probe, ++ .remove = pcm5102a_remove, ++ .driver = { ++ .name = "pcm5102a-codec", ++ .owner = THIS_MODULE, ++ .of_match_table = pcm5102a_of_match, ++ }, ++}; ++ ++module_platform_driver(pcm5102a_codec_driver); ++ ++MODULE_DESCRIPTION("ASoC PCM5102A codec driver"); ++MODULE_AUTHOR("Florian Meier "); ++MODULE_LICENSE("GPL v2"); +diff -Nur linux-4.1.13.orig/sound/soc/codecs/pcm512x.c linux-rpi/sound/soc/codecs/pcm512x.c +--- linux-4.1.13.orig/sound/soc/codecs/pcm512x.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/sound/soc/codecs/pcm512x.c 2015-11-29 09:42:41.574988668 +0100 +@@ -856,7 +856,8 @@ + int fssp; + int gpio; + +- lrclk_div = snd_soc_params_to_frame_size(params); ++ lrclk_div = snd_pcm_format_physical_width(params_format(params)) ++ * params_channels(params); + if (lrclk_div == 0) { + dev_err(dev, "No LRCLK?\n"); + return -EINVAL; +diff -Nur linux-4.1.13.orig/sound/soc/codecs/tas5713.c linux-rpi/sound/soc/codecs/tas5713.c +--- linux-4.1.13.orig/sound/soc/codecs/tas5713.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/sound/soc/codecs/tas5713.c 2015-11-29 09:42:41.586987871 +0100 +@@ -0,0 +1,369 @@ ++/* ++ * ASoC Driver for TAS5713 ++ * ++ * Author: Sebastian Eickhoff ++ * Copyright 2014 ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "tas5713.h" ++ ++ ++static struct i2c_client *i2c; ++ ++struct tas5713_priv { ++ struct regmap *regmap; ++ int mclk_div; ++ struct snd_soc_codec *codec; ++}; ++ ++static struct tas5713_priv *priv_data; ++ ++ ++ ++ ++/* ++ * _ _ ___ _ ___ _ _ ++ * /_\ | | / __| /_\ / __|___ _ _| |_ _ _ ___| |___ ++ * / _ \| |__\__ \/ _ \ | (__/ _ \ ' \ _| '_/ _ \ (_-< ++ * /_/ \_\____|___/_/ \_\ \___\___/_||_\__|_| \___/_/__/ ++ * ++ */ ++ ++static const DECLARE_TLV_DB_SCALE(tas5713_vol_tlv, -10000, 50, 1); ++ ++ ++static const struct snd_kcontrol_new tas5713_snd_controls[] = { ++ SOC_SINGLE_TLV ("Master" , TAS5713_VOL_MASTER, 0, 248, 1, tas5713_vol_tlv), ++ SOC_DOUBLE_R_TLV("Channels" , TAS5713_VOL_CH1, TAS5713_VOL_CH2, 0, 248, 1, tas5713_vol_tlv) ++}; ++ ++ ++ ++ ++/* ++ * __ __ _ _ ___ _ ++ * | \/ |__ _ __| |_ (_)_ _ ___ | \ _ _(_)_ _____ _ _ ++ * | |\/| / _` / _| ' \| | ' \/ -_) | |) | '_| \ V / -_) '_| ++ * |_| |_\__,_\__|_||_|_|_||_\___| |___/|_| |_|\_/\___|_| ++ * ++ */ ++ ++static int tas5713_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params, ++ struct snd_soc_dai *dai) ++{ ++ u16 blen = 0x00; ++ ++ struct snd_soc_codec *codec; ++ codec = dai->codec; ++ priv_data->codec = dai->codec; ++ ++ switch (params_format(params)) { ++ case SNDRV_PCM_FORMAT_S16_LE: ++ blen = 0x03; ++ break; ++ case SNDRV_PCM_FORMAT_S20_3LE: ++ blen = 0x1; ++ break; ++ case SNDRV_PCM_FORMAT_S24_LE: ++ blen = 0x04; ++ break; ++ case SNDRV_PCM_FORMAT_S32_LE: ++ blen = 0x05; ++ break; ++ default: ++ dev_err(dai->dev, "Unsupported word length: %u\n", ++ params_format(params)); ++ return -EINVAL; ++ } ++ ++ // set word length ++ snd_soc_update_bits(codec, TAS5713_SERIAL_DATA_INTERFACE, 0x7, blen); ++ ++ return 0; ++} ++ ++ ++static int tas5713_mute_stream(struct snd_soc_dai *dai, int mute, int stream) ++{ ++ unsigned int val = 0; ++ ++ struct tas5713_priv *tas5713; ++ struct snd_soc_codec *codec = dai->codec; ++ tas5713 = snd_soc_codec_get_drvdata(codec); ++ ++ if (mute) { ++ val = TAS5713_SOFT_MUTE_ALL; ++ } ++ ++ return regmap_write(tas5713->regmap, TAS5713_SOFT_MUTE, val); ++} ++ ++ ++static const struct snd_soc_dai_ops tas5713_dai_ops = { ++ .hw_params = tas5713_hw_params, ++ .mute_stream = tas5713_mute_stream, ++}; ++ ++ ++static struct snd_soc_dai_driver tas5713_dai = { ++ .name = "tas5713-hifi", ++ .playback = { ++ .stream_name = "Playback", ++ .channels_min = 2, ++ .channels_max = 2, ++ .rates = SNDRV_PCM_RATE_8000_48000, ++ .formats = (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE ), ++ }, ++ .ops = &tas5713_dai_ops, ++}; ++ ++ ++ ++ ++/* ++ * ___ _ ___ _ ++ * / __|___ __| |___ __ | \ _ _(_)_ _____ _ _ ++ * | (__/ _ \/ _` / -_) _| | |) | '_| \ V / -_) '_| ++ * \___\___/\__,_\___\__| |___/|_| |_|\_/\___|_| ++ * ++ */ ++ ++static int tas5713_remove(struct snd_soc_codec *codec) ++{ ++ struct tas5713_priv *tas5713; ++ ++ tas5713 = snd_soc_codec_get_drvdata(codec); ++ ++ return 0; ++} ++ ++ ++static int tas5713_probe(struct snd_soc_codec *codec) ++{ ++ struct tas5713_priv *tas5713; ++ int i, ret; ++ ++ i2c = container_of(codec->dev, struct i2c_client, dev); ++ ++ tas5713 = snd_soc_codec_get_drvdata(codec); ++ ++ // Reset error ++ ret = snd_soc_write(codec, TAS5713_ERROR_STATUS, 0x00); ++ if (ret < 0) return ret; ++ ++ // Trim oscillator ++ ret = snd_soc_write(codec, TAS5713_OSC_TRIM, 0x00); ++ if (ret < 0) return ret; ++ msleep(1000); ++ ++ // Reset error ++ ret = snd_soc_write(codec, TAS5713_ERROR_STATUS, 0x00); ++ if (ret < 0) return ret; ++ ++ // Clock mode: 44/48kHz, MCLK=64xfs ++ ret = snd_soc_write(codec, TAS5713_CLOCK_CTRL, 0x60); ++ if (ret < 0) return ret; ++ ++ // I2S 24bit ++ ret = snd_soc_write(codec, TAS5713_SERIAL_DATA_INTERFACE, 0x05); ++ if (ret < 0) return ret; ++ ++ // Unmute ++ ret = snd_soc_write(codec, TAS5713_SYSTEM_CTRL2, 0x00); ++ if (ret < 0) return ret; ++ ret = snd_soc_write(codec, TAS5713_SOFT_MUTE, 0x00); ++ if (ret < 0) return ret; ++ ++ // Set volume to 0db ++ ret = snd_soc_write(codec, TAS5713_VOL_MASTER, 0x00); ++ if (ret < 0) return ret; ++ ++ // Now start programming the default initialization sequence ++ for (i = 0; i < ARRAY_SIZE(tas5713_init_sequence); ++i) { ++ ret = i2c_master_send(i2c, ++ tas5713_init_sequence[i].data, ++ tas5713_init_sequence[i].size); ++ if (ret < 0) { ++ printk(KERN_INFO "TAS5713 CODEC PROBE: InitSeq returns: %d\n", ret); ++ } ++ } ++ ++ // Unmute ++ ret = snd_soc_write(codec, TAS5713_SYSTEM_CTRL2, 0x00); ++ if (ret < 0) return ret; ++ ++ return 0; ++} ++ ++ ++static struct snd_soc_codec_driver soc_codec_dev_tas5713 = { ++ .probe = tas5713_probe, ++ .remove = tas5713_remove, ++ .controls = tas5713_snd_controls, ++ .num_controls = ARRAY_SIZE(tas5713_snd_controls), ++}; ++ ++ ++ ++ ++/* ++ * ___ ___ ___ ___ _ ++ * |_ _|_ ) __| | \ _ _(_)_ _____ _ _ ++ * | | / / (__ | |) | '_| \ V / -_) '_| ++ * |___/___\___| |___/|_| |_|\_/\___|_| ++ * ++ */ ++ ++static const struct reg_default tas5713_reg_defaults[] = { ++ { 0x07 ,0x80 }, // R7 - VOL_MASTER - -40dB ++ { 0x08 , 30 }, // R8 - VOL_CH1 - 0dB ++ { 0x09 , 30 }, // R9 - VOL_CH2 - 0dB ++ { 0x0A ,0x80 }, // R10 - VOL_HEADPHONE - -40dB ++}; ++ ++ ++static bool tas5713_reg_volatile(struct device *dev, unsigned int reg) ++{ ++ switch (reg) { ++ case TAS5713_DEVICE_ID: ++ case TAS5713_ERROR_STATUS: ++ return true; ++ default: ++ return false; ++ } ++} ++ ++ ++static const struct of_device_id tas5713_of_match[] = { ++ { .compatible = "ti,tas5713", }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, tas5713_of_match); ++ ++ ++static struct regmap_config tas5713_regmap_config = { ++ .reg_bits = 8, ++ .val_bits = 8, ++ ++ .max_register = TAS5713_MAX_REGISTER, ++ .volatile_reg = tas5713_reg_volatile, ++ ++ .cache_type = REGCACHE_RBTREE, ++ .reg_defaults = tas5713_reg_defaults, ++ .num_reg_defaults = ARRAY_SIZE(tas5713_reg_defaults), ++}; ++ ++ ++static int tas5713_i2c_probe(struct i2c_client *i2c, ++ const struct i2c_device_id *id) ++{ ++ int ret; ++ ++ priv_data = devm_kzalloc(&i2c->dev, sizeof *priv_data, GFP_KERNEL); ++ if (!priv_data) ++ return -ENOMEM; ++ ++ priv_data->regmap = devm_regmap_init_i2c(i2c, &tas5713_regmap_config); ++ if (IS_ERR(priv_data->regmap)) { ++ ret = PTR_ERR(priv_data->regmap); ++ return ret; ++ } ++ ++ i2c_set_clientdata(i2c, priv_data); ++ ++ ret = snd_soc_register_codec(&i2c->dev, ++ &soc_codec_dev_tas5713, &tas5713_dai, 1); ++ ++ return ret; ++} ++ ++ ++static int tas5713_i2c_remove(struct i2c_client *i2c) ++{ ++ snd_soc_unregister_codec(&i2c->dev); ++ i2c_set_clientdata(i2c, NULL); ++ ++ kfree(priv_data); ++ ++ return 0; ++} ++ ++ ++static const struct i2c_device_id tas5713_i2c_id[] = { ++ { "tas5713", 0 }, ++ { } ++}; ++ ++MODULE_DEVICE_TABLE(i2c, tas5713_i2c_id); ++ ++ ++static struct i2c_driver tas5713_i2c_driver = { ++ .driver = { ++ .name = "tas5713", ++ .owner = THIS_MODULE, ++ .of_match_table = tas5713_of_match, ++ }, ++ .probe = tas5713_i2c_probe, ++ .remove = tas5713_i2c_remove, ++ .id_table = tas5713_i2c_id ++}; ++ ++ ++static int __init tas5713_modinit(void) ++{ ++ int ret = 0; ++ ++ ret = i2c_add_driver(&tas5713_i2c_driver); ++ if (ret) { ++ printk(KERN_ERR "Failed to register tas5713 I2C driver: %d\n", ++ ret); ++ } ++ ++ return ret; ++} ++module_init(tas5713_modinit); ++ ++ ++static void __exit tas5713_exit(void) ++{ ++ i2c_del_driver(&tas5713_i2c_driver); ++} ++module_exit(tas5713_exit); ++ ++ ++MODULE_AUTHOR("Sebastian Eickhoff "); ++MODULE_DESCRIPTION("ASoC driver for TAS5713"); ++MODULE_LICENSE("GPL v2"); +diff -Nur linux-4.1.13.orig/sound/soc/codecs/tas5713.h linux-rpi/sound/soc/codecs/tas5713.h +--- linux-4.1.13.orig/sound/soc/codecs/tas5713.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-rpi/sound/soc/codecs/tas5713.h 2015-11-29 09:42:41.586987871 +0100 +@@ -0,0 +1,210 @@ ++/* ++ * ASoC Driver for TAS5713 ++ * ++ * Author: Sebastian Eickhoff ++ * Copyright 2014 ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * version 2 as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but ++ * WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * General Public License for more details. ++ */ ++ ++#ifndef _TAS5713_H ++#define _TAS5713_H ++ ++ ++// TAS5713 I2C-bus register addresses ++ ++#define TAS5713_CLOCK_CTRL 0x00 ++#define TAS5713_DEVICE_ID 0x01 ++#define TAS5713_ERROR_STATUS 0x02 ++#define TAS5713_SYSTEM_CTRL1 0x03 ++#define TAS5713_SERIAL_DATA_INTERFACE 0x04 ++#define TAS5713_SYSTEM_CTRL2 0x05 ++#define TAS5713_SOFT_MUTE 0x06 ++#define TAS5713_VOL_MASTER 0x07 ++#define TAS5713_VOL_CH1 0x08 ++#define TAS5713_VOL_CH2 0x09 ++#define TAS5713_VOL_HEADPHONE 0x0A ++#define TAS5713_VOL_CONFIG 0x0E ++#define TAS5713_MODULATION_LIMIT 0x10 ++#define TAS5713_IC_DLY_CH1 0x11 ++#define TAS5713_IC_DLY_CH2 0x12 ++#define TAS5713_IC_DLY_CH3 0x13 ++#define TAS5713_IC_DLY_CH4 0x14 ++ ++#define TAS5713_START_STOP_PERIOD 0x1A ++#define TAS5713_OSC_TRIM 0x1B ++#define TAS5713_BKND_ERR 0x1C ++ ++#define TAS5713_INPUT_MUX 0x20 ++#define TAS5713_SRC_SELECT_CH4 0x21 ++#define TAS5713_PWM_MUX 0x25 ++ ++#define TAS5713_CH1_BQ0 0x29 ++#define TAS5713_CH1_BQ1 0x2A ++#define TAS5713_CH1_BQ2 0x2B ++#define TAS5713_CH1_BQ3 0x2C ++#define TAS5713_CH1_BQ4 0x2D ++#define TAS5713_CH1_BQ5 0x2E ++#define TAS5713_CH1_BQ6 0x2F ++#define TAS5713_CH1_BQ7 0x58 ++#define TAS5713_CH1_BQ8 0x59 ++ ++#define TAS5713_CH2_BQ0 0x30 ++#define TAS5713_CH2_BQ1 0x31 ++#define TAS5713_CH2_BQ2 0x32 ++#define TAS5713_CH2_BQ3 0x33 ++#define TAS5713_CH2_BQ4 0x34 ++#define TAS5713_CH2_BQ5 0x35 ++#define TAS5713_CH2_BQ6 0x36 ++#define TAS5713_CH2_BQ7 0x5C ++#define TAS5713_CH2_BQ8 0x5D ++ ++#define TAS5713_CH4_BQ0 0x5A ++#define TAS5713_CH4_BQ1 0x5B ++#define TAS5713_CH3_BQ0 0x5E ++#define TAS5713_CH3_BQ1 0x5F ++ ++#define TAS5713_DRC1_SOFTENING_FILTER_ALPHA_OMEGA 0x3B ++#define TAS5713_DRC1_ATTACK_RELEASE_RATE 0x3C ++#define TAS5713_DRC2_SOFTENING_FILTER_ALPHA_OMEGA 0x3E ++#define TAS5713_DRC2_ATTACK_RELEASE_RATE 0x3F ++#define TAS5713_DRC1_ATTACK_RELEASE_THRES 0x40 ++#define TAS5713_DRC2_ATTACK_RELEASE_THRES 0x43 ++#define TAS5713_DRC_CTRL 0x46 ++ ++#define TAS5713_BANK_SW_CTRL 0x50 ++#define TAS5713_CH1_OUTPUT_MIXER 0x51 ++#define TAS5713_CH2_OUTPUT_MIXER 0x52 ++#define TAS5713_CH1_INPUT_MIXER 0x53 ++#define TAS5713_CH2_INPUT_MIXER 0x54 ++#define TAS5713_OUTPUT_POST_SCALE 0x56 ++#define TAS5713_OUTPUT_PRESCALE 0x57 ++ ++#define TAS5713_IDF_POST_SCALE 0x62 ++ ++#define TAS5713_CH1_INLINE_MIXER 0x70 ++#define TAS5713_CH1_INLINE_DRC_EN_MIXER 0x71 ++#define TAS5713_CH1_R_CHANNEL_MIXER 0x72 ++#define TAS5713_CH1_L_CHANNEL_MIXER 0x73 ++#define TAS5713_CH2_INLINE_MIXER 0x74 ++#define TAS5713_CH2_INLINE_DRC_EN_MIXER 0x75 ++#define TAS5713_CH2_L_CHANNEL_MIXER 0x76 ++#define TAS5713_CH2_R_CHANNEL_MIXER 0x77 ++ ++#define TAS5713_UPDATE_DEV_ADDR_KEY 0xF8 ++#define TAS5713_UPDATE_DEV_ADDR_REG 0xF9 ++ ++#define TAS5713_REGISTER_COUNT 0x46 ++#define TAS5713_MAX_REGISTER 0xF9 ++ ++ ++// Bitmasks for registers ++#define TAS5713_SOFT_MUTE_ALL 0x07 ++ ++ ++ ++struct tas5713_init_command { ++ const int size; ++ const char *const data; ++}; ++ ++static const struct tas5713_init_command tas5713_init_sequence[] = { ++ ++ // Trim oscillator ++ { .size = 2, .data = "\x1B\x00" }, ++ // System control register 1 (0x03): block DC ++ { .size = 2, .data = "\x03\x80" }, ++ // Mute everything ++ { .size = 2, .data = "\x05\x40" }, ++ // Modulation limit register (0x10): 97.7% ++ { .size = 2, .data = "\x10\x02" }, ++ // Interchannel delay registers ++ // (0x11, 0x12, 0x13, and 0x14): BD mode ++ { .size = 2, .data = "\x11\xB8" }, ++ { .size = 2, .data = "\x12\x60" }, ++ { .size = 2, .data = "\x13\xA0" }, ++ { .size = 2, .data = "\x14\x48" }, ++ // PWM shutdown group register (0x19): no shutdown ++ { .size = 2, .data = "\x19\x00" }, ++ // Input multiplexer register (0x20): BD mode ++ { .size = 2, .data = "\x20\x00\x89\x77\x72" }, ++ // PWM output mux register (0x25) ++ // Channel 1 --> OUTA, channel 1 neg --> OUTB ++ // Channel 2 --> OUTC, channel 2 neg --> OUTD ++ { .size = 5, .data = "\x25\x01\x02\x13\x45" }, ++ // DRC control (0x46): DRC off ++ { .size = 5, .data = "\x46\x00\x00\x00\x00" }, ++ // BKND_ERR register (0x1C): 299ms reset period ++ { .size = 2, .data = "\x1C\x07" }, ++ // Mute channel 3 ++ { .size = 2, .data = "\x0A\xFF" }, ++ // Volume configuration register (0x0E): volume slew 512 steps ++ { .size = 2, .data = "\x0E\x90" }, ++ // Clock control register (0x00): 44/48kHz, MCLK=64xfs ++ { .size = 2, .data = "\x00\x60" }, ++ // Bank switch and eq control (0x50): no bank switching ++ { .size = 5, .data = "\x50\x00\x00\x00\x00" }, ++ // Volume registers (0x07, 0x08, 0x09, 0x0A) ++ { .size = 2, .data = "\x07\x20" }, ++ { .size = 2, .data = "\x08\x30" }, ++ { .size = 2, .data = "\x09\x30" }, ++ { .size = 2, .data = "\x0A\xFF" }, ++ // 0x72, 0x73, 0x76, 0x77 input mixer: ++ // no intermix between channels ++ { .size = 5, .data = "\x72\x00\x00\x00\x00" }, ++ { .size = 5, .data = "\x73\x00\x80\x00\x00" }, ++ { .size = 5, .data = "\x76\x00\x00\x00\x00" }, ++ { .size = 5, .data = "\x77\x00\x80\x00\x00" }, ++ // 0x70, 0x71, 0x74, 0x75 inline DRC mixer: ++ // no inline DRC inmix ++ { .size = 5, .data = "\x70\x00\x80\x00\x00" }, ++ { .size = 5, .data = "\x71\x00\x00\x00\x00" }, ++ { .size = 5, .data = "\x74\x00\x80\x00\x00" }, ++ { .size = 5, .data = "\x75\x00\x00\x00\x00" }, ++ // 0x56, 0x57 Output scale ++ { .size = 5, .data = "\x56\x00\x80\x00\x00" }, ++ { .size = 5, .data = "\x57\x00\x02\x00\x00" }, ++ // 0x3B, 0x3c ++ { .size = 9, .data = "\x3B\x00\x08\x00\x00\x00\x78\x00\x00" }, ++ { .size = 9, .data = "\x3C\x00\x00\x01\x00\xFF\xFF\xFF\x00" }, ++ { .size = 9, .data = "\x3E\x00\x08\x00\x00\x00\x78\x00\x00" }, ++ { .size = 9, .data = "\x3F\x00\x00\x01\x00\xFF\xFF\xFF\x00" }, ++ { .size = 9, .data = "\x40\x00\x00\x01\x00\xFF\xFF\xFF\x00" }, ++ { .size = 9, .data = "\x43\x00\x00\x01\x00\xFF\xFF\xFF\x00" }, ++ // 0x51, 0x52: output mixer ++ { .size = 9, .data = "\x51\x00\x80\x00\x00\x00\x00\x00\x00" }, ++ { .size = 9, .data = "\x52\x00\x80\x00\x00\x00\x00\x00\x00" }, ++ // PEQ defaults ++ { .size = 21, .data = "\x29\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x2A\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x2B\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x2C\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x2D\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x2E\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x2F\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x30\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x31\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x32\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x33\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x34\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x35\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x36\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x58\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x59\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x5C\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x5D\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x5E\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x5F\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x5A\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++ { .size = 21, .data = "\x5B\x00\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" }, ++}; ++ ++ ++#endif /* _TAS5713_H */ +diff -Nur linux-4.1.13.orig/sound/soc/codecs/tpa6130a2.c linux-rpi/sound/soc/codecs/tpa6130a2.c +--- linux-4.1.13.orig/sound/soc/codecs/tpa6130a2.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/sound/soc/codecs/tpa6130a2.c 2015-11-29 09:42:41.586987871 +0100 +@@ -4,6 +4,7 @@ + * Copyright (C) Nokia Corporation + * + * Author: Peter Ujfalusi ++ * Modified: Jan Grulich + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License +@@ -52,6 +53,8 @@ + enum tpa_model id; + }; + ++static void tpa6130a2_channel_enable(u8 channel, int enable); ++ + static int tpa6130a2_i2c_read(int reg) + { + struct tpa6130a2_data *data; +@@ -189,7 +192,7 @@ + } + + static int tpa6130a2_get_volsw(struct snd_kcontrol *kcontrol, +- struct snd_ctl_elem_value *ucontrol) ++ struct snd_ctl_elem_value *ucontrol) + { + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; +@@ -218,7 +221,7 @@ + } + + static int tpa6130a2_put_volsw(struct snd_kcontrol *kcontrol, +- struct snd_ctl_elem_value *ucontrol) ++ struct snd_ctl_elem_value *ucontrol) + { + struct soc_mixer_control *mc = + (struct soc_mixer_control *)kcontrol->private_value; +@@ -255,8 +258,22 @@ + return 1; + } + ++static int tpa6130a2_put_hp_sw(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ int enable = ucontrol->value.integer.value[0]; ++ unsigned int state; ++ ++ state = (tpa6130a2_read(TPA6130A2_REG_VOL_MUTE) & 0x80) == 0; ++ if (state == enable) ++ return 0; /* No change */ ++ ++ tpa6130a2_channel_enable(TPA6130A2_HP_EN_R | TPA6130A2_HP_EN_L, enable); ++ return 1; /* Changed */ ++} ++ + /* +- * TPA6130 volume. From -59.5 to 4 dB with increasing step size when going ++ * TPA6130 volume. From -59.5 to +4.0 dB with increasing step size when going + * down in gain. + */ + static const unsigned int tpa6130_tlv[] = { +@@ -278,6 +295,9 @@ + TPA6130A2_REG_VOL_MUTE, 0, 0x3f, 0, + tpa6130a2_get_volsw, tpa6130a2_put_volsw, + tpa6130_tlv), ++ SOC_SINGLE_EXT("TPA6130A2 Headphone Playback Switch", ++ TPA6130A2_REG_VOL_MUTE, 7, 1, 1, ++ tpa6130a2_get_volsw, tpa6130a2_put_hp_sw), + }; + + static const unsigned int tpa6140_tlv[] = { +@@ -292,6 +312,9 @@ + TPA6130A2_REG_VOL_MUTE, 1, 0x1f, 0, + tpa6130a2_get_volsw, tpa6130a2_put_volsw, + tpa6140_tlv), ++ SOC_SINGLE_EXT("TPA6140A2 Headphone Playback Switch", ++ TPA6130A2_REG_VOL_MUTE, 7, 1, 1, ++ tpa6130a2_get_volsw, tpa6130a2_put_hp_sw), + }; + + /* +diff -Nur linux-4.1.13.orig/sound/soc/codecs/wm8804.c linux-rpi/sound/soc/codecs/wm8804.c +--- linux-4.1.13.orig/sound/soc/codecs/wm8804.c 2015-11-09 23:34:10.000000000 +0100 ++++ linux-rpi/sound/soc/codecs/wm8804.c 2015-11-29 09:42:41.598987074 +0100 +@@ -304,6 +304,7 @@ + blen = 0x1; + break; + case 24: ++ case 32: + blen = 0x2; + break; + default: +@@ -515,7 +516,7 @@ + }; + + #define WM8804_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ +- SNDRV_PCM_FMTBIT_S24_LE) ++ SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) + + #define WM8804_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \ + SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \ +@@ -543,7 +544,7 @@ + }; + + static const struct snd_soc_codec_driver soc_codec_dev_wm8804 = { +- .idle_bias_off = true, ++ .idle_bias_off = false, + + .dapm_widgets = wm8804_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(wm8804_dapm_widgets), diff --git a/target/arm/solidrun-imx6/patches/4.1.15/0001-xbian.patch b/target/arm/solidrun-imx6/patches/4.1.15/0001-xbian.patch deleted file mode 100644 index d3ce4744b..000000000 --- a/target/arm/solidrun-imx6/patches/4.1.15/0001-xbian.patch +++ /dev/null @@ -1,314813 +0,0 @@ -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/imx6dl-cm-fx6.dts linux-4.1.13/arch/arm/boot/dts/imx6dl-cm-fx6.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/imx6dl-cm-fx6.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/arch/arm/boot/dts/imx6dl-cm-fx6.dts 2015-11-30 17:56:13.480144383 +0100 -@@ -0,0 +1,21 @@ -+/* -+ * Copyright 2015 CompuLab Ltd. -+ * -+ * Author: Valentin Raevsky -+ * -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/dts-v1/; -+#include "imx6dl.dtsi" -+#include "imx6qdl-cm-fx6.dtsi" -+ -+/ { -+ model = "CompuLab CM-FX6"; -+ compatible = "compulab,cm-fx6", "fsl,imx6dl"; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/imx6dl.dtsi linux-4.1.13/arch/arm/boot/dts/imx6dl.dtsi ---- linux-4.1.13.orig/arch/arm/boot/dts/imx6dl.dtsi 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/boot/dts/imx6dl.dtsi 2015-11-30 17:56:13.480144383 +0100 -@@ -30,7 +30,7 @@ - /* kHz uV */ - 996000 1250000 - 792000 1175000 -- 396000 1075000 -+ 396000 1175000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ -@@ -43,9 +43,12 @@ - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, - <&clks IMX6QDL_CLK_STEP>, - <&clks IMX6QDL_CLK_PLL1_SW>, -- <&clks IMX6QDL_CLK_PLL1_SYS>; -+ <&clks IMX6QDL_CLK_PLL1_SYS>, -+ <&clks IMX6QDL_PLL1_BYPASS>, -+ <&clks IMX6QDL_CLK_PLL1>, -+ <&clks IMX6QDL_PLL1_BYPASS_SRC> ; - clock-names = "arm", "pll2_pfd2_396m", "step", -- "pll1_sw", "pll1_sys"; -+ "pll1_sw", "pll1_sys", "pll1_bypass", "pll1", "pll1_bypass_src"; - arm-supply = <®_arm>; - pu-supply = <®_pu>; - soc-supply = <®_soc>; -@@ -60,17 +63,82 @@ - }; - - soc { -- ocram: sram@00900000 { -+ busfreq { /* BUSFREQ */ -+ compatible = "fsl,imx6_busfreq"; -+ clocks = <&clks IMX6QDL_CLK_PLL2_BUS>, <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, -+ <&clks IMX6QDL_CLK_PLL2_198M>, <&clks IMX6QDL_CLK_ARM>, -+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>, <&clks IMX6QDL_CLK_PERIPH>, -+ <&clks IMX6QDL_CLK_PERIPH_PRE>, <&clks IMX6QDL_CLK_PERIPH_CLK2>, -+ <&clks IMX6QDL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6QDL_CLK_OSC>, -+ <&clks IMX6QDL_CLK_AXI_ALT_SEL>, <&clks IMX6QDL_CLK_AXI_SEL>, -+ <&clks IMX6QDL_CLK_PLL3_PFD1_540M>; -+ clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph", -+ "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "axi_alt_sel", "axi_sel", "pll3_pfd1_540m"; -+ interrupts = <0 107 0x04>, <0 112 0x4>; -+ interrupt-names = "irq_busfreq_0", "irq_busfreq_1"; -+ fsl,max_ddr_freq = <400000000>; -+ }; -+ -+ gpu@00130000 { -+ compatible = "fsl,imx6dl-gpu", "fsl,imx6q-gpu"; -+ reg = <0x00130000 0x4000>, <0x00134000 0x4000>, -+ <0x0 0x0>; -+ reg-names = "iobase_3d", "iobase_2d", -+ "phys_baseaddr"; -+ interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>, -+ <0 10 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-names = "irq_3d", "irq_2d"; -+ clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>, <&clks IMX6QDL_CLK_GPU3D_AXI>, -+ <&clks IMX6QDL_CLK_GPU2D_CORE>, <&clks IMX6QDL_CLK_GPU3D_CORE>, -+ <&clks IMX6QDL_CLK_DUMMY>; -+ clock-names = "gpu2d_axi_clk", "gpu3d_axi_clk", -+ "gpu2d_clk", "gpu3d_clk", -+ "gpu3d_shader_clk"; -+ resets = <&src 0>, <&src 3>; -+ reset-names = "gpu3d", "gpu2d"; -+ power-domains = <&gpc 1>; -+ }; -+ -+ hdmi_cec: hdmi_cec@00120000 { -+ compatible = "fsl,imx6q-hdmi-cec"; -+ interrupts = <0 115 0x04>; -+ status = "disabled"; -+ }; -+ -+ ocrams: sram@00900000 { -+ compatible = "fsl,lpm-sram"; -+ reg = <0x00900000 0x4000>; -+ clocks = <&clks IMX6QDL_CLK_OCRAM>; -+ }; -+ -+ ocrams_ddr: sram@00904000 { -+ compatible = "fsl,ddr-lpm-sram"; -+ reg = <0x00904000 0x1000>; -+ clocks = <&clks IMX6QDL_CLK_OCRAM>; -+ }; -+ -+ ocram: sram@00905000 { - compatible = "mmio-sram"; -- reg = <0x00900000 0x20000>; -+ reg = <0x00905000 0x1B000>; - clocks = <&clks IMX6QDL_CLK_OCRAM>; - }; - - aips1: aips-bus@02000000 { -+ vpu@02040000 { -+ iramsize = <0>; -+ status = "okay"; -+ }; -+ - iomuxc: iomuxc@020e0000 { - compatible = "fsl,imx6dl-iomuxc"; - }; - -+ dcic2: dcic@020e8000 { -+ clocks = <&clks IMX6QDL_CLK_DCIC1 >, -+ <&clks IMX6QDL_CLK_DCIC2>; /* DCIC2 depend on DCIC1 clock in imx6dl*/ -+ clock-names = "dcic", "disp-axi"; -+ }; -+ - pxp: pxp@020f0000 { - reg = <0x020f0000 0x4000>; - interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; -@@ -88,6 +156,16 @@ - }; - - aips2: aips-bus@02100000 { -+ mipi_dsi: mipi@021e0000 { -+ compatible = "fsl,imx6dl-mipi-dsi"; -+ reg = <0x021e0000 0x4000>; -+ interrupts = <0 102 0x04>; -+ gpr = <&gpr>; -+ clocks = <&clks IMX6QDL_CLK_HSI_TX>, <&clks IMX6QDL_CLK_VIDEO_27M>; -+ clock-names = "mipi_pllref_clk", "mipi_cfg_clk"; -+ status = "disabled"; -+ }; -+ - i2c4: i2c@021f8000 { - #address-cells = <1>; - #size-cells = <0>; -@@ -99,26 +177,13 @@ - }; - }; - }; -- -- display-subsystem { -- compatible = "fsl,imx-display-subsystem"; -- ports = <&ipu1_di0>, <&ipu1_di1>; -- }; --}; -- --&hdmi { -- compatible = "fsl,imx6dl-hdmi"; - }; - - &ldb { -- clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, -- <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, -- <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; -+ clocks = <&clks 33>, <&clks 34>, -+ <&clks 39>, <&clks 40>, -+ <&clks 135>, <&clks 136>; - clock-names = "di0_pll", "di1_pll", - "di0_sel", "di1_sel", - "di0", "di1"; - }; -- --&vpu { -- compatible = "fsl,imx6dl-vpu", "cnm,coda960"; --}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/imx6dl-hummingboard2.dts linux-4.1.13/arch/arm/boot/dts/imx6dl-hummingboard2.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/imx6dl-hummingboard2.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/arch/arm/boot/dts/imx6dl-hummingboard2.dts 2015-11-30 17:56:13.480144383 +0100 -@@ -0,0 +1,52 @@ -+/* -+ * Device Tree file for SolidRun HummingBoard2 -+ * Copyright (C) 2015 Rabeeh Khoury -+ * Based on work by Russell King -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPL or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This file is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License. -+ * -+ * This file is distributed in the hope that it will be useful -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+/dts-v1/; -+ -+#include "imx6dl.dtsi" -+#include "imx6qdl-hummingboard2.dtsi" -+ -+/ { -+ model = "SolidRun HummingBoard2 Solo/DualLite"; -+ compatible = "solidrun,hummingboard2/dl", "fsl,imx6dl"; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/imx6dl-sbc-fx6.dts linux-4.1.13/arch/arm/boot/dts/imx6dl-sbc-fx6.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/imx6dl-sbc-fx6.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/arch/arm/boot/dts/imx6dl-sbc-fx6.dts 2015-11-30 17:56:13.480144383 +0100 -@@ -0,0 +1,23 @@ -+/* -+* Copyright 2015 CompuLab Ltd. -+* -+* Author: Valentin Raevsky -+* -+* The code contained herein is licensed under the GNU General Public -+* License. You may obtain a copy of the GNU General Public License -+* Version 2 or later at the following locations: -+* -+* http://www.opensource.org/licenses/gpl-license.html -+* http://www.gnu.org/copyleft/gpl.html -+*/ -+ -+/dts-v1/; -+#include "imx6dl.dtsi" -+#include "imx6qdl-cm-fx6.dtsi" -+#include "imx6qdl-sb-fx6x.dtsi" -+#include "imx6qdl-sb-fx6.dtsi" -+ -+/ { -+ model = "CompuLab CM-FX6 on SBC-FX6"; -+ compatible = "compulab,cm-fx6", "compulab,sbc-fx6", "fsl,imx6dl"; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/imx6dl-sbc-fx6m.dts linux-4.1.13/arch/arm/boot/dts/imx6dl-sbc-fx6m.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/imx6dl-sbc-fx6m.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/arch/arm/boot/dts/imx6dl-sbc-fx6m.dts 2015-11-30 17:56:13.480144383 +0100 -@@ -0,0 +1,23 @@ -+/* -+* Copyright 2015 CompuLab Ltd. -+* -+* Author: Valentin Raevsky -+* -+* The code contained herein is licensed under the GNU General Public -+* License. You may obtain a copy of the GNU General Public License -+* Version 2 or later at the following locations: -+* -+* http://www.opensource.org/licenses/gpl-license.html -+* http://www.gnu.org/copyleft/gpl.html -+*/ -+ -+/dts-v1/; -+#include "imx6dl.dtsi" -+#include "imx6qdl-cm-fx6.dtsi" -+#include "imx6qdl-sb-fx6x.dtsi" -+#include "imx6qdl-sb-fx6m.dtsi" -+ -+/ { -+ model = "CompuLab CM-FX6 on SBC-FX6m"; -+ compatible = "compulab,cm-fx6", "compulab,sbc-fx6m", "fsl,imx6dl"; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/imx6dl-vero.dts linux-4.1.13/arch/arm/boot/dts/imx6dl-vero.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/imx6dl-vero.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/arch/arm/boot/dts/imx6dl-vero.dts 2015-11-30 17:56:13.480144383 +0100 -@@ -0,0 +1,51 @@ -+/* -+ * Copyright (C) 2014 Russell King -+ * Copyright (C) 2015 Sam Nazarko -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPL or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This file is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License. -+ * -+ * This file is distributed in the hope that it will be useful -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+/dts-v1/; -+ -+#include "imx6dl.dtsi" -+#include "imx6qdl-vero.dtsi" -+ -+/ { -+ model = "OSMC Vero Rev 1.0"; -+ compatible = "osmc,vero1", "fsl,imx6dl"; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/imx6q-cm-fx6.dts linux-4.1.13/arch/arm/boot/dts/imx6q-cm-fx6.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/imx6q-cm-fx6.dts 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/boot/dts/imx6q-cm-fx6.dts 2015-11-30 17:56:13.480144383 +0100 -@@ -1,5 +1,5 @@ - /* -- * Copyright 2013 CompuLab Ltd. -+ * Copyright 2014 CompuLab Ltd. - * - * Author: Valentin Raevsky - * -@@ -13,95 +13,9 @@ - - /dts-v1/; - #include "imx6q.dtsi" -+#include "imx6q-cm-fx6.dtsi" - - / { - model = "CompuLab CM-FX6"; - compatible = "compulab,cm-fx6", "fsl,imx6q"; -- -- memory { -- reg = <0x10000000 0x80000000>; -- }; -- -- leds { -- compatible = "gpio-leds"; -- -- heartbeat-led { -- label = "Heartbeat"; -- gpios = <&gpio2 31 0>; -- linux,default-trigger = "heartbeat"; -- }; -- }; --}; -- --&fec { -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_enet>; -- phy-mode = "rgmii"; -- status = "okay"; --}; -- --&gpmi { -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_gpmi_nand>; -- status = "okay"; --}; -- --&iomuxc { -- imx6q-cm-fx6 { -- pinctrl_enet: enetgrp { -- fsl,pins = < -- MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 -- MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 -- MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 -- MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 -- MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 -- MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 -- MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 -- MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 -- MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 -- MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 -- MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 -- MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 -- MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 -- MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 -- MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 -- MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 -- >; -- }; -- -- pinctrl_gpmi_nand: gpminandgrp { -- fsl,pins = < -- MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 -- MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 -- MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 -- MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 -- MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 -- MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 -- MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 -- MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 -- MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 -- MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 -- MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 -- MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 -- MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 -- MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 -- MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 -- MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 -- MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 -- >; -- }; -- -- pinctrl_uart4: uart4grp { -- fsl,pins = < -- MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 -- MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 -- >; -- }; -- }; --}; -- --&uart4 { -- pinctrl-names = "default"; -- pinctrl-0 = <&pinctrl_uart4>; -- status = "okay"; - }; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/imx6q-cm-fx6.dtsi linux-4.1.13/arch/arm/boot/dts/imx6q-cm-fx6.dtsi ---- linux-4.1.13.orig/arch/arm/boot/dts/imx6q-cm-fx6.dtsi 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/arch/arm/boot/dts/imx6q-cm-fx6.dtsi 2015-11-30 17:56:13.480144383 +0100 -@@ -0,0 +1,95 @@ -+/* -+ * Copyright 2014 CompuLab Ltd. -+ * -+ * Author: Valentin Raevsky -+ * -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+#include "imx6qdl-cm-fx6.dtsi" -+ -+/ { -+ regulators { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ reg_sata_ldo_en: sata_ldo_en { -+ compatible = "regulator-fixed"; -+ regulator-name = "cm_fx6_sata_ldo_en"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio2 16 0>; -+ startup-delay-us = <100>; -+ enable-active-high; -+ }; -+ -+ reg_sata_phy_slp: sata_phy_slp { -+ compatible = "regulator-fixed"; -+ regulator-name = "cm_fx6_sata_phy_slp"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio3 23 0>; -+ startup-delay-us = <100>; -+ enable-active-high; -+ vin-supply = <®_sata_ldo_en>; -+ }; -+ -+ reg_sata_nrstdly: sata_nrstdly { -+ compatible = "regulator-fixed"; -+ regulator-name = "cm_fx6_sata_nrstdly"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio6 6 0>; -+ startup-delay-us = <100>; -+ enable-active-high; -+ vin-supply = <®_sata_phy_slp>; -+ }; -+ -+ reg_sata_pwren: sata_pwren { -+ compatible = "regulator-fixed"; -+ regulator-name = "cm_fx6_sata_pwren"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio1 28 0>; -+ startup-delay-us = <100>; -+ enable-active-high; -+ vin-supply = <®_sata_nrstdly>; -+ }; -+ -+ reg_sata_nstandby1: sata_nstandby1 { -+ compatible = "regulator-fixed"; -+ regulator-name = "cm_fx6_sata_nstandby1"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio3 20 0>; -+ startup-delay-us = <100>; -+ enable-active-high; -+ vin-supply = <®_sata_pwren>; -+ }; -+ -+ reg_sata_nstandby2: sata_nstandby2 { -+ compatible = "regulator-fixed"; -+ regulator-name = "cm_fx6_sata_nstandby2"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio5 2 0>; -+ startup-delay-us = <100>; -+ enable-active-high; -+ regulator-boot-on; -+ vin-supply = <®_sata_nstandby1>; -+ }; -+ -+ }; -+ -+}; -+ -+/* sata */ -+&sata { -+ status = "okay"; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/imx6qdl-cm-fx6.dtsi linux-4.1.13/arch/arm/boot/dts/imx6qdl-cm-fx6.dtsi ---- linux-4.1.13.orig/arch/arm/boot/dts/imx6qdl-cm-fx6.dtsi 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/arch/arm/boot/dts/imx6qdl-cm-fx6.dtsi 2015-11-30 17:56:13.484144118 +0100 -@@ -0,0 +1,643 @@ -+/* -+ * Copyright 2014 CompuLab Ltd. -+ * -+ * Author: Valentin Raevsky -+ * -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+#define MX6QDL_GPR1 0x04 0x04 0x000 0x0 0x0 -+#define MX6QDL_GPR6 0x18 0x18 0x000 0x0 0x0 -+#define MX6QDL_GPR7 0x1c 0x1c 0x000 0x0 0x0 -+ -+/ { -+ memory { -+ reg = <0x10000000 0x20000000>; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ heartbeat-led { -+ label = "Heartbeat"; -+ gpios = <&gpio2 31 0>; -+ linux,default-trigger = "heartbeat"; -+ }; -+ }; -+ -+ regulators { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ reg_3p3v: 3p3v { -+ compatible = "regulator-fixed"; -+ regulator-name = "3P3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ /* regulator for usb otg */ -+ reg_usb_otg_vbus: usb_otg_vbus { -+ compatible = "regulator-fixed"; -+ regulator-name = "usb_otg_vbus"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ gpio = <&gpio3 22 0>; -+ enable-active-high; -+ }; -+ -+ /* regulator1 for pcie power-on-gpio */ -+ pcie_power_on_gpio: regulator-pcie-power-on-gpio { -+ compatible = "regulator-fixed"; -+ regulator-name = "regulator-pcie-power-on-gpio"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio2 24 0>; -+ enable-active-high; -+ }; -+ -+ /* regulator for usb hub1 */ -+ reg_usb_h1_vbus: usb_h1_vbus { -+ compatible = "regulator-fixed"; -+ regulator-name = "usb_h1_vbus"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ gpio = <&gpio7 8 0>; -+ enable-active-high; -+ }; -+ -+ /* regulator1 for wifi/bt */ -+ awnh387_npoweron: regulator-awnh387-npoweron { -+ compatible = "regulator-fixed"; -+ regulator-name = "regulator-awnh387-npoweron"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio7 12 0>; -+ enable-active-high; -+ }; -+ -+ /* regulator2 for wifi/bt */ -+ awnh387_wifi_nreset: regulator-awnh387-wifi-nreset { -+ compatible = "regulator-fixed"; -+ regulator-name = "regulator-awnh387-wifi-nreset"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ gpio = <&gpio6 16 0>; -+ startup-delay-us = <10000>; -+ }; -+ -+ tsc2046reg: tsc2046-reg { -+ compatible = "regulator-fixed"; -+ regulator-name = "tsc2046-reg"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ -+ }; -+ -+ aliases { -+ mxcfb0 = &mxcfb1; -+ mxcfb1 = &mxcfb2; -+ mxcfb2 = &mxcfb3; -+ mxcfb3 = &mxcfb4; -+ }; -+ -+ sound { -+ compatible = "fsl,imx-audio-wm8731"; -+ model = "wm8731-audio"; -+ ssi-controller = <&ssi2>; -+ src-port = <2>; -+ ext-port = <4>; -+ audio-codec = <&codec>; -+ audio-routing = "LOUT", "ROUT", "LLINEIN", "RLINEIN"; -+ }; -+ -+ sound-hdmi { -+ compatible = "fsl,imx-audio-hdmi"; -+ model = "imx-audio-hdmi"; -+ hdmi-controller = <&hdmi_audio>; -+ }; -+ -+ sound-spdif { -+ compatible = "fsl,imx-audio-spdif"; -+ model = "imx-spdif"; -+ spdif-controller = <&spdif>; -+ spdif-out; -+ spdif-in; -+ }; -+ -+ mxcfb1: fb@0 { -+ compatible = "fsl,mxc_sdc_fb"; -+ disp_dev = "hdmi"; -+ interface_pix_fmt = "RGB24"; -+ mode_str ="1920x1080M@60"; -+ default_bpp = <32>; -+ int_clk = <0>; -+ late_init = <0>; -+ status = "disabled"; -+ }; -+ -+ mxcfb2: fb@1 { -+ compatible = "fsl,mxc_sdc_fb"; -+ disp_dev = "lcd"; -+ interface_pix_fmt = "RGB24"; -+ mode_str ="1920x1080M@60"; -+ default_bpp = <32>; -+ int_clk = <0>; -+ late_init = <0>; -+ status = "disabled"; -+ }; -+ -+ mxcfb3: fb@2 { -+ compatible = "fsl,mxc_sdc_fb"; -+ disp_dev = "ldb"; -+ interface_pix_fmt = "RGB666"; -+ mode_str ="1366x768M-18@60"; -+ default_bpp = <16>; -+ int_clk = <0>; -+ late_init = <0>; -+ status = "disabled"; -+ }; -+ -+ mxcfb4: fb@3 { -+ compatible = "fsl,mxc_sdc_fb"; -+ disp_dev = "ldb"; -+ interface_pix_fmt = "RGB666"; -+ mode_str ="1280x800M-18@60"; -+ default_bpp = <16>; -+ int_clk = <0>; -+ late_init = <0>; -+ status = "disabled"; -+ }; -+ -+ lcd@0 { -+ compatible = "fsl,lcd"; -+ ipu_id = <0>; -+ disp_id = <0>; -+ default_ifmt = "RGB24"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_ipu1_lcd>; -+ status = "okay"; -+ }; -+ -+ v4l2_out { -+ compatible = "fsl,mxc_v4l2_output"; -+ status = "okay"; -+ }; -+ -+ restart_poweroff { -+ compatible = "fsl,snvs-poweroff"; -+ }; -+}; -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>; -+ -+ hog { -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ MX6QDL_GPR1 0x48400005 -+ /* ipu3 QoS */ -+ MX6QDL_GPR6 0x007f007f -+ MX6QDL_GPR7 0x007f007f -+ /* SATA PWR */ -+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 -+ MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x80000000 -+ MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x80000000 -+ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 -+ /* SATA CTRL */ -+ MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 -+ MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 -+ MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x80000000 -+ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 -+ /* POWER_BUTTON */ -+ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 -+ >; -+ }; -+ }; -+ -+ imx6q-cm-fx6 { -+ /* pins for eth0 */ -+ pinctrl_enet: enetgrp { -+ fsl,pins = < -+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 -+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 -+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 -+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 -+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 -+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 -+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 -+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 -+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 -+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 -+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 -+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 -+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 -+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 -+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 -+ >; -+ }; -+ -+ pinctrl_ipu1_lcd: ipu1grp-lcd { -+ fsl,pins = < -+ MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38 -+ MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38 -+ MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38 -+ MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38 -+ MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000028 -+ MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38 -+ MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38 -+ MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38 -+ MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38 -+ MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38 -+ MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38 -+ MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38 -+ MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38 -+ MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38 -+ MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38 -+ MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38 -+ MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38 -+ MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38 -+ MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38 -+ MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38 -+ MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38 -+ MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38 -+ MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38 -+ MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38 -+ MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38 -+ MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38 -+ MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38 -+ MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38 -+ MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38 -+ >; -+ }; -+ -+ /* pins for spi */ -+ pinctrl_ecspi1: ecspi1grp { -+ fsl,pins = < -+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 -+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 -+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 -+ MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1 -+ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1 -+ >; -+ }; -+ -+ /* pins for nand */ -+ pinctrl_gpmi_nand: gpminandgrp { -+ fsl,pins = < -+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 -+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 -+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 -+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 -+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 -+ MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 -+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 -+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 -+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 -+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 -+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 -+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 -+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 -+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 -+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 -+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 -+ MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 -+ >; -+ }; -+ -+ /* pins for i2c2 */ -+ pinctrl_i2c2: i2c2grp { -+ fsl,pins = < -+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 -+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 -+ >; -+ }; -+ -+ /* pins for i2c3 */ -+ pinctrl_i2c3: i2c3grp { -+ fsl,pins = < -+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 -+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 -+ >; -+ }; -+ -+ /* pins for console */ -+ pinctrl_uart4: uart4grp { -+ fsl,pins = < -+ MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 -+ MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 -+ >; -+ }; -+ -+ /* pins for usb hub1 */ -+ pinctrl_usbh1: usbh1grp { -+ fsl,pins = < -+ MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000 -+ >; -+ }; -+ -+ /* pins for usb otg */ -+ pinctrl_usbotg: usbotggrp { -+ fsl,pins = < -+ MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 -+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 -+ >; -+ }; -+ -+ /* pins for wifi/bt */ -+ pinctrl_usdhc1: usdhc1grp { -+ fsl,pins = < -+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 -+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 -+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 -+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 -+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 -+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 -+ >; -+ }; -+ -+ /* pins for wifi/bt */ -+ pinctrl_mrvl1: mrvl1grp { -+ fsl,pins = < -+ /* WIFI_PWR_RST */ -+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 -+ MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000 -+ >; -+ }; -+ -+ /* pins for tsc2046 pendown */ -+ pinctrl_tsc2046: tsc2046grp { -+ fsl,pins = < -+ /* tsc2046 PENDOWN */ -+ MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x80000000 -+ >; -+ }; -+ -+ /* pins for pcie */ -+ pinctrl_pcie: pciegrp { -+ fsl,pins = < -+ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 -+ MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000 -+ >; -+ }; -+ -+ /* pins for spdif */ -+ pinctrl_spdif: spdifgrp { -+ fsl,pins = < -+ MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 -+ MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x1b0b0 -+ >; -+ }; -+ -+ /* pins for audmux */ -+ pinctrl_audmux: audmuxgrp { -+ fsl,pins = < -+ MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x17059 -+ MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x17059 -+ MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x17059 -+ MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x17059 -+ MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x17059 -+ /* master mode pin */ -+ MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x17059 -+ >; -+ }; -+ -+ pinctrl_hdmi_hdcp: hdmihdcpgrp { -+ fsl,pins = < -+ MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 -+ MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 -+ >; -+ }; -+ -+ pinctrl_pwm3_1: pwm3grp-1 { -+ fsl,pins = < -+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_flexcan1_1: flexcan1grp-1 { -+ fsl,pins = < -+ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 -+ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 -+ >; -+ }; -+ }; -+}; -+ -+&cpu0 { -+ operating-points = < -+ /* kHz uV */ -+ 1248000 1300000 -+ 1200000 1275000 -+ 1128000 1275000 -+ 996000 1250000 -+ 852000 1250000 -+ 792000 1150000 -+ 396000 975000 -+ >; -+ fsl,soc-operating-points = < -+ /* ARM kHz SOC-PU uV */ -+ 1248000 1300000 -+ 1200000 1275000 -+ 1128000 1275000 -+ 996000 1250000 -+ 852000 1250000 -+ 792000 1175000 -+ 396000 1175000 -+ >; -+}; -+ -+/* spi */ -+&ecspi1 { -+ fsl,spi-num-chipselects = <2>; -+ cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_ecspi1>; -+ status = "okay"; -+ -+ flash: m25p80@0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "st,m25px16", "st,m25p"; -+ spi-max-frequency = <20000000>; -+ reg = <0>; -+ -+ partition@0 { -+ label = "uboot"; -+ reg = <0x0 0xc0000>; -+ }; -+ -+ partition@c0000 { -+ label = "uboot environment"; -+ reg = <0xc0000 0x40000>; -+ }; -+ -+ partition@100000 { -+ label = "reserved"; -+ reg = <0x100000 0x100000>; -+ }; -+ }; -+ -+ /* touch controller */ -+ touch: tsc2046@1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_tsc2046>; -+ -+ compatible = "ti,tsc2046"; -+ vcc-supply = <&tsc2046reg>; -+ -+ reg = <1>; /* CS1 */ -+ spi-max-frequency = <1500000>; -+ -+ interrupt-parent = <&gpio2>; -+ interrupts = <15 0>; -+ pendown-gpio = <&gpio2 15 0>; -+ -+ ti,x-min = /bits/ 16 <0x0>; -+ ti,x-max = /bits/ 16 <0x0fff>; -+ ti,y-min = /bits/ 16 <0x0>; -+ ti,y-max = /bits/ 16 <0x0fff>; -+ -+ ti,x-plate-ohms = /bits/ 16 <180>; -+ ti,pressure-max = /bits/ 16 <255>; -+ -+ ti,debounce-max = /bits/ 16 <30>; -+ ti,debounce-tol = /bits/ 16 <10>; -+ ti,debounce-rep = /bits/ 16 <1>; -+ -+ linux,wakeup; -+ }; -+}; -+ -+/* eth0 */ -+&fec { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_enet>; -+ phy-mode = "rgmii"; -+ status = "okay"; -+}; -+ -+/* nand */ -+&gpmi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gpmi_nand>; -+ status = "okay"; -+ -+ partition@0 { -+ label = "linux"; -+ reg = <0x0 0x800000>; -+ }; -+ -+ partition@800000 { -+ label = "rootfs"; -+ reg = < 0x800000 0x0>; -+ }; -+}; -+ -+/* i2c3 */ -+&i2c3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c3>; -+ status = "okay"; -+ -+ eeprom@50 { -+ compatible = "at24,24c02"; -+ reg = <0x50>; -+ pagesize = <16>; -+ }; -+ -+ codec: wm8731@1a { -+ compatible = "wlf,wm8731"; -+ reg = <0x1a>; -+ clocks = <&clks 173>, <&clks 158>, <&clks 201>, <&clks 200>; -+ clock-names = "pll4", "imx-ssi.1", "cko", "cko2"; -+ AVDD-supply = <®_3p3v>; -+ HPVDD-supply = <®_3p3v>; -+ DCVDD-supply = <®_3p3v>; -+ DBVDD-supply = <®_3p3v>; -+ }; -+}; -+ -+&pcie { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcie>; -+ reset-gpio = <&gpio1 26 0>; -+ vdd-supply = <&pcie_power_on_gpio>; -+ status = "okay"; -+}; -+ -+/* console */ -+&uart4 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart4>; -+ status = "okay"; -+}; -+ -+/* usb otg */ -+&usbotg { -+ vbus-supply = <®_usb_otg_vbus>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usbotg>; -+ dr_mode = "otg"; -+ status = "okay"; -+}; -+ -+/* usb hub1 */ -+&usbh1 { -+ vbus-supply = <®_usb_h1_vbus>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usbh1>; -+ status = "okay"; -+}; -+ -+/* wifi/bt */ -+&usdhc1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_mrvl1>; -+ non-removable; -+ vmmc-supply = <&awnh387_npoweron>; -+ vmmc_aux-supply = <&awnh387_wifi_nreset>; -+ status = "okay"; -+}; -+ -+&ssi2 { -+ fsl,mode = "i2s-master"; -+ status = "okay"; -+}; -+ -+&hdmi_core { -+ ipu_id = <0>; -+ disp_id = <1>; -+ status = "okay"; -+}; -+ -+&hdmi_video { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hdmi_hdcp>; -+ fsl,hdcp; -+ status = "okay"; -+}; -+ -+&hdmi_audio { -+ status = "okay"; -+}; -+ -+&spdif { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_spdif>; -+ status = "okay"; -+}; -+ -+&audmux { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_audmux>; -+ status = "okay"; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi linux-4.1.13/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi ---- linux-4.1.13.orig/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi 2015-11-30 17:56:13.484144118 +0100 -@@ -45,11 +45,22 @@ - #include - - / { -+ chosen { -+ bootargs = "quiet console=ttymxc0,115200 root=/dev/mmcblk0p2 rw"; -+ }; -+ -+ aliases { -+ mmc0 = &usdhc2; -+ mmc1 = &usdhc1; -+ mxcfb0 = &mxcfb1; -+ }; -+ - ir_recv: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio3 9 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_ir>; -+ linux,rc-map-name = "rc-rc6-mce"; - }; - - pwmleds { -@@ -78,6 +89,8 @@ - - reg_usbh1_vbus: usb-h1-vbus { - compatible = "regulator-fixed"; -+ regulator-boot-on; -+ regulator-always-on; - enable-active-high; - gpio = <&gpio1 0 0>; - pinctrl-names = "default"; -@@ -89,6 +102,8 @@ - - reg_usbotg_vbus: usb-otg-vbus { - compatible = "regulator-fixed"; -+ regulator-boot-on; -+ regulator-always-on; - enable-active-high; - gpio = <&gpio3 22 0>; - pinctrl-names = "default"; -@@ -101,8 +116,7 @@ - - sound-spdif { - compatible = "fsl,imx-audio-spdif"; -- model = "Integrated SPDIF"; -- /* IMX6 doesn't implement this yet */ -+ model = "imx-spdif"; - spdif-controller = <&spdif>; - spdif-out; - }; -@@ -118,12 +132,45 @@ - linux,code = ; - }; - }; -+ -+ sound-hdmi { -+ compatible = "fsl,imx6q-audio-hdmi", -+ "fsl,imx-audio-hdmi"; -+ model = "imx-audio-hdmi"; -+ hdmi-controller = <&hdmi_audio>; -+ }; -+ -+ mxcfb1: fb@0 { -+ compatible = "fsl,mxc_sdc_fb"; -+ disp_dev = "hdmi"; -+ interface_pix_fmt = "RGB24"; -+ mode_str ="1920x1080M@60"; -+ default_bpp = <32>; -+ int_clk = <0>; -+ late_init = <0>; -+ status = "okay"; -+ }; -+}; -+ -+&hdmi_core { -+ ipu_id = <0>; -+ disp_id = <0>; -+ status = "okay"; -+}; -+ -+&hdmi_video { -+ fsl,phy_reg_vlev = <0x0294>; -+ fsl,phy_reg_cksymtx = <0x800d>; -+ status = "okay"; -+}; -+ -+&hdmi_audio { -+ status = "okay"; - }; - --&hdmi { -+&hdmi_cec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_hdmi>; -- ddc-i2c-bus = <&i2c2>; - status = "okay"; - }; - -@@ -131,7 +178,13 @@ - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_cubox_i_i2c2>; -+ - status = "okay"; -+ -+ ddc: imx6_hdmi_i2c@50 { -+ compatible = "fsl,imx6-hdmi-i2c"; -+ reg = <0x50>; -+ }; - }; - - &i2c3 { -@@ -207,7 +260,7 @@ - - pinctrl_cubox_i_usdhc2_aux: cubox-i-usdhc2-aux { - fsl,pins = < -- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 -+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x13071 - MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b071 - >; - }; -@@ -228,6 +281,28 @@ - MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x17059 - >; - }; -+ -+ pinctrl_cubox_i_usdhc2_100mhz: cubox-i-usdhc2-100mhz { -+ fsl,pins = < -+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 -+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 -+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 -+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 -+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 -+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130b9 -+ >; -+ }; -+ -+ pinctrl_cubox_i_usdhc2_200mhz: cubox-i-usdhc2-200mhz { -+ fsl,pins = < -+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 -+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 -+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 -+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 -+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 -+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130f9 -+ >; -+ }; - }; - }; - -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/imx6qdl.dtsi linux-4.1.13/arch/arm/boot/dts/imx6qdl.dtsi ---- linux-4.1.13.orig/arch/arm/boot/dts/imx6qdl.dtsi 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/boot/dts/imx6qdl.dtsi 2015-11-30 17:56:13.488143852 +0100 -@@ -14,6 +14,7 @@ - #include - - #include "skeleton.dtsi" -+#include - - / { - aliases { -@@ -30,6 +31,7 @@ - i2c0 = &i2c1; - i2c1 = &i2c2; - i2c2 = &i2c3; -+ ipu0 = &ipu1; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; -@@ -79,6 +81,10 @@ - }; - }; - -+ pu_dummy: pudummy_reg { -+ compatible = "fsl,imx6-dummy-pureg"; /* only used in ldo-bypass */ -+ }; -+ - soc { - #address-cells = <1>; - #size-cells = <1>; -@@ -86,6 +92,11 @@ - interrupt-parent = <&gpc>; - ranges; - -+ caam_sm: caam-sm@00100000 { -+ compatible = "fsl,imx6q-caam-sm"; -+ reg = <0x00100000 0x3fff>; -+ }; -+ - dma_apbh: dma-apbh@00110000 { - compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; - reg = <0x00110000 0x2000>; -@@ -99,6 +110,12 @@ - clocks = <&clks IMX6QDL_CLK_APBH_DMA>; - }; - -+ irq_sec_vio: caam_secvio { -+ compatible = "fsl,imx6q-caam-secvio"; -+ interrupts = <0 20 0x04>; -+ secvio_src = <0x8000001d>; -+ }; -+ - gpmi: gpmi-nand@00112000 { - compatible = "fsl,imx6q-gpmi-nand"; - #address-cells = <1>; -@@ -169,6 +186,39 @@ - interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; - }; - -+ hdmi_core: hdmi_core@00120000 { -+ compatible = "fsl,imx6q-hdmi-core"; -+ reg = <0x00120000 0x9000>; -+ clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>, -+ <&clks IMX6QDL_CLK_HDMI_IAHB>, -+ <&clks IMX6QDL_CLK_HSI_TX>; -+ clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core"; -+ status = "disabled"; -+ }; -+ -+ hdmi_video: hdmi_video@020e0000 { -+ compatible = "fsl,imx6q-hdmi-video"; -+ reg = <0x020e0000 0x1000>; -+ reg-names = "hdmi_gpr"; -+ interrupts = <0 115 0x04>; -+ clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>, -+ <&clks IMX6QDL_CLK_HDMI_IAHB>, -+ <&clks IMX6QDL_CLK_HSI_TX>; -+ clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core"; -+ status = "disabled"; -+ }; -+ -+ hdmi_audio: hdmi_audio@00120000 { -+ compatible = "fsl,imx6q-hdmi-audio"; -+ clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>, -+ <&clks IMX6QDL_CLK_HDMI_IAHB>, -+ <&clks IMX6QDL_CLK_HSI_TX>; -+ clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core"; -+ dmas = <&sdma 2 23 0>; -+ dma-names = "tx"; -+ status = "disabled"; -+ }; -+ - aips-bus@02000000 { /* AIPS1 */ - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; -@@ -274,7 +324,12 @@ - esai: esai@02024000 { - reg = <0x02024000 0x4000>; - interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; -- }; -+ compatible = "fsl,imx6q-esai"; -+ clocks = <&clks 118>; -+ fsl,esai-dma-events = <24 23>; -+ fsl,flags = <1>; -+ status = "disabled"; -+ }; - - ssi1: ssi@02028000 { - #sound-dai-cells = <0>; -@@ -325,8 +380,30 @@ - }; - - asrc: asrc@02034000 { -+ compatible = "fsl,imx53-asrc"; - reg = <0x02034000 0x4000>; - interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clks IMX6QDL_CLK_ASRC_MEM>, -+ <&clks IMX6QDL_CLK_ASRC_IPG>, -+ <&clks IMX6QDL_CLK_SPDIF>, -+ <&clks IMX6QDL_CLK_SPBA>; -+ clock-names = "mem", "ipg", "asrck_0", "dma"; -+ dmas = <&sdma 17 20 1>, <&sdma 18 20 1>, <&sdma 19 20 1>, -+ <&sdma 20 20 1>, <&sdma 21 20 1>, <&sdma 22 20 1>; -+ dma-names = "rxa", "rxb", "rxc", -+ "txa", "txb", "txc"; -+ fsl,asrc-rate = <48000>; -+ fsl,asrc-width = <16>; -+ status = "okay"; -+ }; -+ -+ asrc_p2p: asrc_p2p { -+ compatible = "fsl,imx6q-asrc-p2p"; -+ fsl,output-rate = <48000>; -+ fsl,output-width = <16>; -+ fsl,asrc-dma-rx-events = <17 18 19>; -+ fsl,asrc-dma-tx-events = <20 21 22>; -+ status = "okay"; - }; - - spba@0203c000 { -@@ -335,16 +412,20 @@ - }; - - vpu: vpu@02040000 { -- compatible = "cnm,coda960"; -+ compatible = "cnm,coda960", "fsl,imx6-vpu"; - reg = <0x02040000 0x3c000>; -+ reg-names = "vpu_regs"; - interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>, - <0 3 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "bit", "jpeg"; - clocks = <&clks IMX6QDL_CLK_VPU_AXI>, -- <&clks IMX6QDL_CLK_MMDC_CH0_AXI>; -- clock-names = "per", "ahb"; -- resets = <&src 1>; -+ <&clks IMX6QDL_CLK_MMDC_CH0_AXI>, -+ <&clks IMX6QDL_CLK_OCRAM>; -+ clock-names = "per", "ahb", "ocram"; -+ iramsize = <0x21000>; - iram = <&ocram>; -+ resets = <&src 1>; -+ power-domains = <&gpc 1>; - }; - - aipstz@0207c000 { /* AIPSTZ1 */ -@@ -552,20 +633,21 @@ - anatop-min-bit-val = <4>; - anatop-min-voltage = <800000>; - anatop-max-voltage = <1375000>; -+ anatop-enable-bit = <0>; - }; - -- regulator-3p0@120 { -+ reg_3p0: regulator-3p0@120 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd3p0"; -- regulator-min-microvolt = <2800000>; -- regulator-max-microvolt = <3150000>; -- regulator-always-on; -+ regulator-min-microvolt = <2625000>; -+ regulator-max-microvolt = <3400000>; - anatop-reg-offset = <0x120>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <0>; - anatop-min-voltage = <2625000>; - anatop-max-voltage = <3400000>; -+ anatop-enable-bit = <0>; - }; - - regulator-2p5@130 { -@@ -580,6 +662,7 @@ - anatop-min-bit-val = <0>; - anatop-min-voltage = <2000000>; - anatop-max-voltage = <2750000>; -+ anatop-enable-bit = <0>; - }; - - reg_arm: regulator-vddcore@140 { -@@ -597,6 +680,8 @@ - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; -+ regulator-allow-bypass; -+ linux,phandle = <®_arm>; - }; - - reg_pu: regulator-vddpu@140 { -@@ -631,6 +716,8 @@ - anatop-min-bit-val = <1>; - anatop-min-voltage = <725000>; - anatop-max-voltage = <1450000>; -+ regulator-allow-bypass; -+ linux,phandle = <®_soc>; - }; - }; - -@@ -647,6 +734,7 @@ - reg = <0x020c9000 0x1000>; - interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_USBPHY1>; -+ phy-3p0-supply = <®_3p0>; - fsl,anatop = <&anatop>; - }; - -@@ -655,9 +743,15 @@ - reg = <0x020ca000 0x1000>; - interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_USBPHY2>; -+ phy-3p0-supply = <®_3p0>; - fsl,anatop = <&anatop>; - }; - -+ caam_snvs: caam-snvs@020cc000 { -+ compatible = "fsl,imx6q-caam-snvs"; -+ reg = <0x020cc000 0x4000>; -+ }; -+ - snvs@020cc000 { - compatible = "fsl,sec-v4.0-mon", "simple-bus"; - #address-cells = <1>; -@@ -704,14 +798,12 @@ - interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>, - <0 90 IRQ_TYPE_LEVEL_HIGH>; - interrupt-parent = <&intc>; -- pu-supply = <®_pu>; -- clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>, -- <&clks IMX6QDL_CLK_GPU3D_SHADER>, -- <&clks IMX6QDL_CLK_GPU2D_CORE>, -- <&clks IMX6QDL_CLK_GPU2D_AXI>, -- <&clks IMX6QDL_CLK_OPENVG_AXI>, -- <&clks IMX6QDL_CLK_VPU_AXI>; - #power-domain-cells = <1>; -+ clocks = <&clks 122>, <&clks 74>, <&clks 121>, -+ <&clks 26>, <&clks 143>, <&clks 168>; -+ clock-names = "gpu3d_core", "gpu3d_shader", "gpu2d_core", -+ "gpu2d_axi", "openvg_axi", "vpu_axi"; -+ pu-supply = <®_pu>; - }; - - gpr: iomuxc-gpr@020e0000 { -@@ -736,22 +828,6 @@ - #size-cells = <0>; - reg = <0>; - status = "disabled"; -- -- port@0 { -- reg = <0>; -- -- lvds0_mux_0: endpoint { -- remote-endpoint = <&ipu1_di0_lvds0>; -- }; -- }; -- -- port@1 { -- reg = <1>; -- -- lvds0_mux_1: endpoint { -- remote-endpoint = <&ipu1_di1_lvds0>; -- }; -- }; - }; - - lvds-channel@1 { -@@ -759,22 +835,6 @@ - #size-cells = <0>; - reg = <1>; - status = "disabled"; -- -- port@0 { -- reg = <0>; -- -- lvds1_mux_0: endpoint { -- remote-endpoint = <&ipu1_di0_lvds1>; -- }; -- }; -- -- port@1 { -- reg = <1>; -- -- lvds1_mux_1: endpoint { -- remote-endpoint = <&ipu1_di1_lvds1>; -- }; -- }; - }; - }; - -@@ -788,32 +848,26 @@ - <&clks IMX6QDL_CLK_HDMI_ISFR>; - clock-names = "iahb", "isfr"; - status = "disabled"; -- -- port@0 { -- reg = <0>; -- -- hdmi_mux_0: endpoint { -- remote-endpoint = <&ipu1_di0_hdmi>; -- }; -- }; -- -- port@1 { -- reg = <1>; -- -- hdmi_mux_1: endpoint { -- remote-endpoint = <&ipu1_di1_hdmi>; -- }; -- }; - }; - - dcic1: dcic@020e4000 { -+ compatible = "fsl,imx6q-dcic"; - reg = <0x020e4000 0x4000>; - interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clks IMX6QDL_CLK_DCIC1>, <&clks IMX6QDL_CLK_DCIC1>; -+ clock-names = "dcic", "disp-axi"; -+ gpr = <&gpr>; -+ status = "disabled"; - }; - - dcic2: dcic@020e8000 { -+ compatible = "fsl,imx6q-dcic"; - reg = <0x020e8000 0x4000>; - interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clks IMX6QDL_CLK_DCIC2>, <&clks IMX6QDL_CLK_DCIC2>; -+ clock-names = "dcic", "disp-axi"; -+ gpr = <&gpr>; -+ status = "disabled"; - }; - - sdma: sdma@020ec000 { -@@ -824,6 +878,7 @@ - <&clks IMX6QDL_CLK_SDMA>; - clock-names = "ipg", "ahb"; - #dma-cells = <3>; -+ iram = <&ocram>; - fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; - }; - }; -@@ -835,10 +890,30 @@ - reg = <0x02100000 0x100000>; - ranges; - -- caam@02100000 { -- reg = <0x02100000 0x40000>; -- interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>, -- <0 106 IRQ_TYPE_LEVEL_HIGH>; -+ crypto: caam@2100000 { -+ compatible = "fsl,sec-v4.0"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ reg = <0x2100000 0x40000>; -+ ranges = <0 0x2100000 0x40000>; -+ interrupt-parent = <&intc>; /* interrupts = <0 92 0x4>; */ -+ interrupts = <0 92 0x4>; -+ clocks = <&clks 213>, <&clks 214>, <&clks 215> ,<&clks 196>; -+ clock-names = "caam_mem", "caam_aclk", "caam_ipg", "caam_emi_slow"; -+ -+ sec_jr0: jr0@1000 { -+ compatible = "fsl,sec-v4.0-job-ring"; -+ reg = <0x1000 0x1000>; -+ interrupt-parent = <&intc>; -+ interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ sec_jr1: jr1@2000 { -+ compatible = "fsl,sec-v4.0-job-ring"; -+ reg = <0x2000 0x1000>; -+ interrupt-parent = <&intc>; -+ interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; -+ }; - }; - - aipstz@0217c000 { /* AIPSTZ2 */ -@@ -852,6 +927,7 @@ - clocks = <&clks IMX6QDL_CLK_USBOH3>; - fsl,usbphy = <&usbphy1>; - fsl,usbmisc = <&usbmisc 0>; -+ fsl,anatop = <&anatop>; - status = "disabled"; - }; - -@@ -903,14 +979,22 @@ - <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET_REF>; - clock-names = "ipg", "ahb", "ptp"; -- status = "disabled"; -+ phy-mode = "rgmii"; -+ fsl,magic-packet; -+ status = "okay"; -+ local-mac-address = [FF FF FF FF FF FF]; - }; - -- mlb@0218c000 { -+ mlb: mlb@0218c000 { - reg = <0x0218c000 0x4000>; - interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>, - <0 117 IRQ_TYPE_LEVEL_HIGH>, - <0 126 IRQ_TYPE_LEVEL_HIGH>; -+ compatible = "fsl,imx6q-mlb150"; -+ clocks = <&clks 139>, <&clks 175>; -+ clock-names = "mlb", "pll8_mlb"; -+ iram = <&ocram>; -+ status = "disabled"; - }; - - usdhc1: usdhc@02190000 { -@@ -995,6 +1079,11 @@ - reg = <0x021ac000 0x4000>; - }; - -+ mmdc0-1@021b0000 { -+ compatible = "fsl,imx6q-mmdc-combine"; -+ reg = <0x021b0000 0x8000>; -+ }; -+ - mmdc0: mmdc@021b0000 { /* MMDC0 */ - compatible = "fsl,imx6q-mmdc"; - reg = <0x021b0000 0x4000>; -@@ -1011,9 +1100,15 @@ - clocks = <&clks IMX6QDL_CLK_EIM_SLOW>; - }; - -- ocotp: ocotp@021bc000 { -- compatible = "fsl,imx6q-ocotp", "syscon"; -+ ocotp: ocotp-ctrl@021bc000 { -+ compatible = "syscon"; -+ reg = <0x021bc000 0x4000>; -+ }; -+ -+ ocotp-fuse@021bc000 { -+ compatible = "fsl,imx6q-ocotp"; - reg = <0x021bc000 0x4000>; -+ clocks = <&clks 128>; - }; - - tzasc@021d0000 { /* TZASC1 */ -@@ -1034,39 +1129,38 @@ - - mipi_csi: mipi@021dc000 { - reg = <0x021dc000 0x4000>; -+ compatible = "fsl,imx6q-mipi-csi2"; -+ interrupts = <0 100 0x04>, <0 101 0x04>; -+ clocks = <&clks IMX6QDL_CLK_HSI_TX>, -+ <&clks IMX6QDL_CLK_EIM_SEL>, -+ <&clks IMX6QDL_CLK_LVDS2_IN>; -+ /* Note: clks 138 is hsi_tx, however, the dphy_c -+ * hsi_tx and pll_refclk use the same clk gate. -+ * In current clk driver, open/close clk gate do -+ * use hsi_tx for a temporary debug purpose. -+ */ -+ clock-names = "dphy_clk", "pixel_clk", "cfg_clk"; -+ status = "disabled"; - }; - - mipi_dsi: mipi@021e0000 { -+ compatible = "fsl,imx6q-mipi-dsi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x021e0000 0x4000>; - status = "disabled"; -- -- ports { -- #address-cells = <1>; -- #size-cells = <0>; -- -- port@0 { -- reg = <0>; -- -- mipi_mux_0: endpoint { -- remote-endpoint = <&ipu1_di0_mipi>; -- }; -- }; -- -- port@1 { -- reg = <1>; -- -- mipi_mux_1: endpoint { -- remote-endpoint = <&ipu1_di1_mipi>; -- }; -- }; -- }; -+ interrupts = <0 102 0x04>; -+ gpr = <&gpr>; -+ clocks = <&clks IMX6QDL_CLK_HSI_TX>, <&clks IMX6QDL_CLK_VIDEO_27M>; -+ clock-names = "mipi_pllref_clk", "mipi_cfg_clk"; - }; - - vdoa@021e4000 { -+ compatible = "fsl,imx6q-vdoa"; - reg = <0x021e4000 0x4000>; - interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clks 202>; -+ iram = <&ocram>; - }; - - uart2: serial@021e8000 { -@@ -1127,67 +1221,14 @@ - <0 5 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_IPU1>, - <&clks IMX6QDL_CLK_IPU1_DI0>, -- <&clks IMX6QDL_CLK_IPU1_DI1>; -- clock-names = "bus", "di0", "di1"; -+ <&clks IMX6QDL_CLK_IPU1_DI1>, -+ <&clks 39>, <&clks 40>, -+ <&clks 135>, <&clks 136>; -+ clock-names = "bus", "di0", "di1", -+ "di0_sel", "di1_sel", -+ "ldb_di0", "ldb_di1"; - resets = <&src 2>; -- -- ipu1_csi0: port@0 { -- reg = <0>; -- }; -- -- ipu1_csi1: port@1 { -- reg = <1>; -- }; -- -- ipu1_di0: port@2 { -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <2>; -- -- ipu1_di0_disp0: endpoint@0 { -- }; -- -- ipu1_di0_hdmi: endpoint@1 { -- remote-endpoint = <&hdmi_mux_0>; -- }; -- -- ipu1_di0_mipi: endpoint@2 { -- remote-endpoint = <&mipi_mux_0>; -- }; -- -- ipu1_di0_lvds0: endpoint@3 { -- remote-endpoint = <&lvds0_mux_0>; -- }; -- -- ipu1_di0_lvds1: endpoint@4 { -- remote-endpoint = <&lvds1_mux_0>; -- }; -- }; -- -- ipu1_di1: port@3 { -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <3>; -- -- ipu1_di0_disp1: endpoint@0 { -- }; -- -- ipu1_di1_hdmi: endpoint@1 { -- remote-endpoint = <&hdmi_mux_1>; -- }; -- -- ipu1_di1_mipi: endpoint@2 { -- remote-endpoint = <&mipi_mux_1>; -- }; -- -- ipu1_di1_lvds0: endpoint@3 { -- remote-endpoint = <&lvds0_mux_1>; -- }; -- -- ipu1_di1_lvds1: endpoint@4 { -- remote-endpoint = <&lvds1_mux_1>; -- }; -- }; -+ bypass_reset = <0>; - }; - }; - }; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi linux-4.1.13/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi ---- linux-4.1.13.orig/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/arch/arm/boot/dts/imx6qdl-hummingboard2.dtsi 2015-11-30 17:56:13.488143852 +0100 -@@ -0,0 +1,686 @@ -+/* -+ * Device Tree file for SolidRun HummingBoard2 -+ * Copyright (C) 2015 Rabeeh Khoury -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPL or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This file is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License. -+ * -+ * This file is distributed in the hope that it will be useful -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+#include "imx6qdl-microsom.dtsi" -+#include "imx6qdl-microsom-ar8035.dtsi" -+ -+/ { -+ aliases { -+ mmc0 = &usdhc2; -+ mmc1 = &usdhc1; -+ mxcfb0 = &mxcfb1; -+ mxcfb2 = &mxcfb2; -+ }; -+ -+ chosen { -+ bootargs = "quiet console=ttymxc0,115200 root=/dev/mmcblk0p2 rw"; -+ stdout-path = &uart1; -+ }; -+ -+ ir_recv: ir-receiver { -+ compatible = "gpio-ir-receiver"; -+ gpios = <&gpio7 9 1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hummingboard2_gpio7_9>; -+ linux,rc-map-name = "rc-rc6-mce"; -+ }; -+ -+ mxcfb1: fb@0 { -+ compatible = "fsl,mxc_sdc_fb"; -+ disp_dev = "hdmi"; -+ interface_pix_fmt = "RGB24"; -+ mode_str ="1920x1080M@60"; -+ default_bpp = <32>; -+ int_clk = <0>; -+ late_init = <0>; -+ status = "okay"; -+ }; -+ -+ mxcfb2: fb@1 { -+ compatible = "fsl,mxc_sdc_fb"; -+ disp_dev = "ldb"; -+ interface_pix_fmt = "RGB666"; -+ default_bpp = <16>; -+ int_clk = <0>; -+ late_init = <0>; -+ status = "disabled"; -+ }; -+ -+ regulators { -+ compatible = "simple-bus"; -+ -+ reg_3p3v: 3p3v { -+ compatible = "regulator-fixed"; -+ regulator-name = "3P3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ reg_1p8v: 1p8v { -+ compatible = "regulator-fixed"; -+ regulator-name = "1P8V"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ }; -+ -+ reg_usbh1_vbus: usb-h1-vbus { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio1 0 0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hummingboard2_usbh1_vbus>; -+ regulator-name = "usb_h1_vbus"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ reg_usbotg_vbus: usb-otg-vbus { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio3 22 0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hummingboard2_usbotg_vbus>; -+ regulator-name = "usb_otg_vbus"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ reg_usbh2_vbus: usb-h2-vbus { -+ compatible = "regulator-gpio"; -+ enable-active-high; -+ enable-gpio = <&gpio2 13 0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hummingboard2_usbh2_vbus>; -+ regulator-name = "usb_h2_vbus"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-boot-on; -+ }; -+ -+ reg_usbh3_vbus: usb-h3-vbus { -+ compatible = "regulator-gpio"; -+ enable-active-high; -+ enable-gpio = <&gpio7 10 0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hummingboard2_usbh3_vbus>; -+ regulator-name = "usb_h3_vbus"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-boot-on; -+ }; -+ -+ reg_usdhc2_vbus: usdhc-2-vbus { -+ compatible = "regulator-fixed"; -+ regulator-name = "USDHC2-VBUS"; -+ gpio = <&gpio4 30 0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hummingboard2_usdhc2_pwr>; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ }; -+ -+ sound-sgtl5000 { -+ audio-codec = <&sgtl5000>; -+ audio-routing = -+ "MIC_IN", "Mic Jack", -+ "Mic Jack", "Mic Bias", -+ "Headphone Jack", "HP_OUT"; -+ compatible = "fsl,imx-audio-sgtl5000"; -+ model = "On-board Codec"; -+ mux-ext-port = <5>; -+ mux-int-port = <1>; -+ cpu-dai = <&ssi1>; -+ }; -+ -+ sound-hdmi { -+ compatible = "fsl,imx6q-audio-hdmi", -+ "fsl,imx-audio-hdmi"; -+ model = "imx-audio-hdmi"; -+ hdmi-controller = <&hdmi_audio>; -+ }; -+ -+ v4l2_cap_0 { -+ compatible = "fsl,imx6q-v4l2-capture"; -+ ipu_id = <0>; -+ csi_id = <1>; -+ mclk_source = <0>; -+ mipi_camera = <1>; -+ default_input = <0>; -+ status = "okay"; -+ }; -+ -+ v4l2_out { -+ compatible = "fsl,mxc_v4l2_output"; -+ status = "okay"; -+ }; -+}; -+ -+&audmux { -+ status = "okay"; -+}; -+ -+&ecspi2 { -+ fsl,spi-num-chipselects = <1>; -+ cs-gpios = <&gpio2 26 0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hummingboard2_ecspi2>; -+ status = "okay"; -+ -+ spidev0: spi@0 { -+ compatible = "spidev"; -+ reg = <0>; -+ spi-max-frequency = <20000000>; -+ }; -+}; -+ -+&gpc { -+ fsl,cpu_pupscr_sw2iso = <0xf>; -+ fsl,cpu_pupscr_sw = <0xf>; -+ fsl,cpu_pdnscr_iso2sw = <0x1>; -+ fsl,cpu_pdnscr_iso = <0x1>; -+}; -+ -+&hdmi_core { -+ ipu_id = <0>; -+ disp_id = <0>; -+ status = "okay"; -+}; -+ -+&hdmi_video { -+ fsl,phy_reg_vlev = <0x0294>; -+ fsl,phy_reg_cksymtx = <0x800d>; -+ status = "okay"; -+}; -+ -+&hdmi_audio { -+ status = "okay"; -+}; -+ -+&hdmi_cec { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hummingboard2_hdmi>; -+ status = "okay"; -+}; -+ -+&i2c1 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hummingboard2_i2c1>; -+ status = "okay"; -+ -+ ov5640_mipi: ov5640_mipi@3c { -+ compatible = "ovti,ov5640_mipi"; -+ reg = <0x3c>; -+ clocks = <&clks IMX6QDL_CLK_CKO2>; -+ clock-names = "csi_mclk"; -+/* -+ DOVDD-supply = <®_3p3v>; -+ AVDD-supply = <®_3p3v>; -+ DVDD-supply = <®_3p3v>; -+*/ -+ pwn-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; -+ rst-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; -+ ipu_id = <0>; -+ csi_id = <1>; -+ mclk = <24000000>; -+ mclk_source = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hummingboard2_mipi>; -+ extended-buffer; -+ }; -+ -+ rtc: pcf8523@68 { -+ compatible = "nxp,pcf8523"; -+ reg = <0x68>; -+ nxp,12p5_pf; -+ }; -+ -+ sgtl5000: sgtl5000@0a { -+ compatible = "fsl,sgtl5000"; -+ reg = <0x0a>; -+ clocks = <&clks IMX6QDL_CLK_CKO>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hummingboard2_sgtl5000>; -+ VDDA-supply = <®_3p3v>; -+ VDDIO-supply = <®_3p3v>; -+ }; -+}; -+ -+&i2c2 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hummingboard2_i2c2>; -+ status = "okay"; -+ -+ ddc: imx6_hdmi_i2c@50 { -+ compatible = "fsl,imx6-hdmi-i2c"; -+ reg = <0x50>; -+ }; -+}; -+ -+&i2c3 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hummingboard2_i2c3>; -+ status = "okay"; -+}; -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>; -+ hummingboard2 { -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ /* -+ * 36 pin headers GPIO description. The pins -+ * numbering as following - -+ * -+ * 3.2v 5v 74 75 -+ * 73 72 71 70 -+ * 69 68 67 66 -+ * -+ * 77 78 79 76 -+ * 65 64 61 60 -+ * 53 52 51 50 -+ * 49 48 166 132 -+ * 95 94 90 91 -+ * GND 54 24 204 -+ * -+ * The GPIO numbers can be extracted using -+ * signal name from below. -+ * Example - -+ * MX6QDL_PAD_EIM_DA10__GPIO3_IO10 is -+ * GPIO(3,10) which is (3-1)*32+10 = gpio 74 -+ * -+ * i.e. The mapping of GPIO(X,Y) to Linux gpio -+ * number is : gpio number = (X-1) * 32 + Y -+ */ -+ /* DI1_PIN15 */ -+ MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x400130b1 -+ /* DI1_PIN02 */ -+ MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x400130b1 -+ /* DISP1_DATA00 */ -+ MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x400130b1 -+ /* DISP1_DATA01 */ -+ MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x400130b1 -+ /* DISP1_DATA02 */ -+ MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x400130b1 -+ /* DISP1_DATA03 */ -+ MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x400130b1 -+ /* DISP1_DATA04 */ -+ MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x400130b1 -+ /* DISP1_DATA05 */ -+ MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x400130b1 -+ /* DISP1_DATA06 */ -+ MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x400130b1 -+ /* DISP1_DATA07 */ -+ MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x400130b1 -+ /* DI1_D0_CS */ -+ MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x400130b1 -+ /* DI1_D1_CS */ -+ MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x400130b1 -+ /* DI1_PIN01 */ -+ MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x400130b1 -+ /* DI1_PIN03 */ -+ MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x400130b1 -+ /* DISP1_DATA08 */ -+ MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x400130b1 -+ /* DISP1_DATA09 */ -+ MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x400130b1 -+ /* DISP1_DATA10 */ -+ MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x400130b1 -+ /* DISP1_DATA11 */ -+ MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x400130b1 -+ /* DISP1_DATA12 */ -+ MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x400130b1 -+ /* DISP1_DATA13 */ -+ MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x400130b1 -+ /* DISP1_DATA14 */ -+ MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x400130b1 -+ /* DISP1_DATA15 */ -+ MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x400130b1 -+ /* DISP1_DATA16 */ -+ MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x400130b1 -+ /* DISP1_DATA17 */ -+ MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x400130b1 -+ /* DISP1_DATA18 */ -+ MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x400130b1 -+ /* DISP1_DATA19 */ -+ MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x400130b1 -+ /* DISP1_DATA20 */ -+ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x400130b1 -+ /* DISP1_DATA21 */ -+ MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x400130b1 -+ /* DISP1_DATA22 */ -+ MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x400130b1 -+ /* DISP1_DATA23 */ -+ MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x400130b1 -+ /* DI1_DISP_CLK */ -+ MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x400130b1 -+ /* SPDIF_IN */ -+ MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x400130b1 -+ /* SPDIF_OUT */ -+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x400130b1 -+ -+ /* MikroBUS GPIO pin number 10 */ -+ MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x400130b1 -+ >; -+ }; -+ -+ pinctrl_hummingboard2_gpio7_9: hummingboard2-gpio7_9 { -+ fsl,pins = < -+ MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x80000000 -+ >; -+ }; -+ -+ pinctrl_hummingboard2_hdmi: hummingboard2-hdmi { -+ fsl,pins = < -+ MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 -+ >; -+ }; -+ -+ pinctrl_hummingboard2_i2c1: hummingboard2-i2c1 { -+ fsl,pins = < -+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 -+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 -+ >; -+ }; -+ -+ pinctrl_hummingboard2_i2c2: hummingboard2-i2c2 { -+ fsl,pins = < -+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 -+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 -+ >; -+ }; -+ -+ pinctrl_hummingboard2_i2c3: hummingboard2-i2c3 { -+ fsl,pins = < -+ MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 -+ MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 -+ >; -+ }; -+ -+ pinctrl_hummingboard2_mipi: hummingboard2_mipi { -+ fsl,pins = < -+ MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x4001b8b1 -+ MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x4001b8b1 -+ MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0 -+ >; -+ }; -+ -+ pinctrl_hummingboard2_pcie_reset: hummingboard2-pcie-reset { -+ fsl,pins = < -+ MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_hummingboard2_pwm1: pwm1grp { -+ fsl,pins = < -+ MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_hummingboard2_sgtl5000: hummingboard2-sgtl5000 { -+ fsl,pins = < -+ MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 -+ MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 -+ MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 -+ MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 -+ MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0 -+ >; -+ }; -+ -+ pinctrl_hummingboard2_usbh1_vbus: hummingboard2-usbh1-vbus { -+ fsl,pins = ; -+ }; -+ -+ pinctrl_hummingboard2_usbh2_vbus: hummingboard2-usbh2-vbus { -+ fsl,pins = ; -+ }; -+ -+ pinctrl_hummingboard2_usbh3_vbus: hummingboard2-usbh3-vbus { -+ fsl,pins = ; -+ }; -+ -+ pinctrl_hummingboard2_usbotg_id: hummingboard2-usbotg-id { -+ /* -+ * Similar to pinctrl_usbotg_2, but we want it -+ * pulled down for a fixed host connection. -+ */ -+ fsl,pins = ; -+ }; -+ -+ pinctrl_hummingboard2_usbotg_vbus: hummingboard2-usbotg-vbus { -+ fsl,pins = ; -+ }; -+ -+ pinctrl_hummingboard2_usdhc2_pwr: hummingboard2-usdhc2-pwr { -+ fsl,pins = ; -+ }; -+ -+ pinctrl_hummingboard2_usdhc2_aux: hummingboard2-usdhc2-aux { -+ fsl,pins = < -+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x13071 -+ MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b071 -+ >; -+ }; -+ -+ pinctrl_hummingboard2_usdhc2: hummingboard2-usdhc2 { -+ fsl,pins = < -+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 -+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 -+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 -+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 -+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 -+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 -+ >; -+ }; -+ -+ pinctrl_hummingboard2_usdhc2_100mhz: hummingboard2-usdhc2-100mhz { -+ fsl,pins = < -+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 -+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 -+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 -+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 -+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 -+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130b9 -+ >; -+ }; -+ -+ pinctrl_hummingboard2_usdhc2_200mhz: hummingboard2-usdhc2-200mhz { -+ fsl,pins = < -+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 -+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 -+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 -+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 -+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 -+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130f9 -+ >; -+ }; -+ -+ pinctrl_hummingboard2_usdhc3: hummingboard2-usdhc3 { -+ fsl,pins = < -+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 -+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 -+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 -+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 -+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 -+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 -+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 -+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 -+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 -+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 -+ MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 -+ >; -+ }; -+ pinctrl_hummingboard2_uart3: hummingboard2-uart3 { -+ fsl,pins = < -+ MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x1b0b1 -+ MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x40013000 -+ >; -+ }; -+ pinctrl_hummingboard2_ecspi2: hummingboard2-ecspi2grp { -+ fsl,pins = < -+ MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 -+ MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 -+ MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 -+ MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1 /* CS */ -+ >; -+ }; -+ }; -+}; -+ -+&ldb { -+ status = "disabled"; -+ -+ lvds-channel@0 { -+ fsl,data-mapping = "spwg"; -+ fsl,data-width = <18>; -+ crtc = "ipu2-di0"; -+ primary; -+ -+ display-timings { -+ native-mode = <&timing0>; -+ timing0: hsd100pxn1 { -+ clock-frequency = <65000000>; -+ hactive = <1024>; -+ vactive = <768>; -+ hback-porch = <220>; -+ hfront-porch = <40>; -+ vback-porch = <21>; -+ vfront-porch = <7>; -+ hsync-len = <60>; -+ vsync-len = <10>; -+ }; -+ }; -+ }; -+}; -+ -+&mipi_csi { -+ ipu_id = <0>; -+ csi_id = <1>; -+ v_channel = <0>; -+ lanes = <2>; -+ mipi_dphy_clk = <0x14>; -+ status = "okay"; -+}; -+ -+&pcie { -+ pinctrl-names = "default"; -+ pinctrl-0 = < -+ &pinctrl_hummingboard2_pcie_reset -+ >; -+ reset-gpio = <&gpio2 11 0>; -+ status = "okay"; -+ no-msi; -+}; -+ -+&pwm1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hummingboard2_pwm1>; -+ status = "okay"; -+}; -+ -+&pwm3 { -+ status = "disabled"; -+}; -+ -+&pwm4 { -+ status = "disabled"; -+}; -+ -+&ssi1 { -+ fsl,mode = "i2s-slave"; -+ status = "okay"; -+}; -+ -+&usbh1 { -+ disable-over-current; -+ vbus-supply = <®_usbh1_vbus>; -+ status = "okay"; -+}; -+ -+&usbotg { -+ disable-over-current; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hummingboard2_usbotg_id>; -+ vbus-supply = <®_usbotg_vbus>; -+ status = "okay"; -+}; -+ -+&usdhc2 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = < -+ &pinctrl_hummingboard2_usdhc2_aux -+ &pinctrl_hummingboard2_usdhc2 -+ >; -+ pinctrl-1 = < -+ &pinctrl_hummingboard2_usdhc2_aux -+ &pinctrl_hummingboard2_usdhc2_100mhz -+ >; -+ pinctrl-2 = < -+ &pinctrl_hummingboard2_usdhc2_aux -+ &pinctrl_hummingboard2_usdhc2_200mhz -+ >; -+ -+ vmmc-supply = <®_usdhc2_vbus>; -+ cd-gpios = <&gpio1 4 0>; -+ status = "okay"; -+}; -+ -+&usdhc3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = < -+ &pinctrl_hummingboard2_usdhc3 -+ >; -+ vmmc-supply = <®_3p3v>; -+ status = "okay"; -+}; -+ -+&uart3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hummingboard2_uart3>; -+ status = "okay"; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi linux-4.1.13/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi ---- linux-4.1.13.orig/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi 2015-11-30 17:56:13.492143584 +0100 -@@ -44,8 +44,11 @@ - #include - - / { -- chosen { -- stdout-path = &uart1; -+ aliases { -+ mmc0 = &usdhc2; -+ mmc1 = &usdhc1; -+ mxcfb0 = &mxcfb1; -+ mxcfb2 = &mxcfb2; - }; - - ir_recv: ir-receiver { -@@ -53,6 +56,17 @@ - gpios = <&gpio3 5 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_gpio3_5>; -+ linux,rc-map-name = "rc-rc6-mce"; -+ }; -+ -+ mxcfb2: fb@1 { -+ compatible = "fsl,mxc_sdc_fb"; -+ disp_dev = "ldb"; -+ interface_pix_fmt = "RGB666"; -+ default_bpp = <16>; -+ int_clk = <0>; -+ late_init = <0>; -+ status = "disabled"; - }; - - regulators { -@@ -87,6 +101,16 @@ - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -+ -+ reg_usdhc2_vbus: usdhc-2-vbus { -+ compatible = "regulator-fixed"; -+ regulator-name = "USDHC2-VBUS"; -+ gpio = <&gpio4 30 0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hummingboard_usdhc2_pwr>; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; - }; - - sound-sgtl5000 { -@@ -99,16 +123,50 @@ - model = "On-board Codec"; - mux-ext-port = <5>; - mux-int-port = <1>; -+ cpu-dai = <&ssi1>; - ssi-controller = <&ssi1>; -+ status = "disabled"; - }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif"; -- model = "On-board SPDIF"; -+ model = "imx-spdif"; - /* IMX6 doesn't implement this yet */ - spdif-controller = <&spdif>; - spdif-out; - }; -+ -+ sound-hdmi { -+ compatible = "fsl,imx6q-audio-hdmi", -+ "fsl,imx-audio-hdmi"; -+ model = "imx-audio-hdmi"; -+ hdmi-controller = <&hdmi_audio>; -+ }; -+ -+ mxcfb1: fb@0 { -+ compatible = "fsl,mxc_sdc_fb"; -+ disp_dev = "hdmi"; -+ interface_pix_fmt = "RGB24"; -+ mode_str ="1920x1080M@60"; -+ default_bpp = <32>; -+ int_clk = <0>; -+ late_init = <0>; -+ }; -+ -+ v4l2_cap_0 { -+ compatible = "fsl,imx6q-v4l2-capture"; -+ ipu_id = <0>; -+ csi_id = <1>; -+ mclk_source = <0>; -+ mipi_camera = <1>; -+ default_input = <1>; -+ status = "okay"; -+ }; -+ -+ v4l2_out { -+ compatible = "fsl,mxc_v4l2_output"; -+ status = "okay"; -+ }; - }; - - &audmux { -@@ -118,13 +176,32 @@ - &can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_flexcan1>; -+ status = "disabled"; -+}; -+ -+&hdmi_core { -+ ipu_id = <0>; -+ disp_id = <0>; - status = "okay"; - }; - --&hdmi { -+&hdmi_video { -+ fsl,phy_reg_vlev = <0x0294>; -+ fsl,phy_reg_cksymtx = <0x800d>; -+ status = "okay"; -+}; -+ -+&hdmi_audio { -+ status = "okay"; -+}; -+ -+&ocram { -+ status = "okay"; -+}; -+ -+&hdmi_cec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_hdmi>; -- ddc-i2c-bus = <&i2c2>; - status = "okay"; - }; - -@@ -133,21 +210,45 @@ - pinctrl-0 = <&pinctrl_hummingboard_i2c1>; - status = "okay"; - -+ /* Raspberry Pi camera rev 1.3 */ -+ ov5647_mipi: ov5647_mipi@36 { -+ compatible = "ovti,ov5647_mipi"; -+ reg = <0x36>; -+ /* Pi camera has its own 25MHz clock. */ -+ clocks = <&clks 0>; -+ clock-names = "csi_mclk"; -+ DOVDD-supply = <®_3p3v>; -+ AVDD-supply = <®_3p3v>; -+ DVDD-supply = <®_3p3v>; -+ pwn-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; -+ led-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; -+ ipu_id = <0>; -+ csi_id = <1>; -+ mclk = <25000000>; -+ mclk_source = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hummingboard_mipi>; -+ extended-buffer; -+ }; -+ - /* Pro baseboard model */ - rtc: pcf8523@68 { - compatible = "nxp,pcf8523"; - reg = <0x68>; -+ nxp,12p5_pf; -+ status = "disabled"; - }; - - /* Pro baseboard model */ - sgtl5000: sgtl5000@0a { -- clocks = <&clks IMX6QDL_CLK_CKO>; - compatible = "fsl,sgtl5000"; -+ reg = <0x0a>; -+ clocks = <&clks IMX6QDL_CLK_CKO>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_sgtl5000>; -- reg = <0x0a>; - VDDA-supply = <®_3p3v>; - VDDIO-supply = <®_3p3v>; -+ status = "disabled"; - }; - }; - -@@ -156,10 +257,47 @@ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_i2c2>; - status = "okay"; -+ -+ ddc: imx6_hdmi_i2c@50 { -+ compatible = "fsl,imx6-hdmi-i2c"; -+ reg = <0x50>; -+ }; - }; - - &iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>; - hummingboard { -+ pinctrl_hog: hoggrp { -+ fsl,pins = < -+ /* -+ * 26 pin header GPIO description. The pins -+ * numbering as following - -+ * GPIO number | GPIO (bank,num) | PIN number -+ * ------------+-----------------+------------ -+ * gpio1 | (1,1) | IO7 -+ * gpio73 | (3,9) | IO11 -+ * gpio72 | (3,8) | IO12 -+ * gpio71 | (3,7) | IO13 -+ * gpio70 | (3,6) | IO15 -+ * gpio194 | (7,2) | IO16 -+ * gpio195 | (7,3) | IO18 -+ * gpio67 | (3,3) | IO22 -+ * -+ * Notice the gpioX and GPIO (Y,Z) mapping forumla : -+ * X = (Y-1) * 32 + Z -+ */ -+ MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x400130b1 -+ MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x400130b1 -+ MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x400130b1 -+ MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x400130b1 -+ MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x400130b1 -+ MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x400130b1 -+ MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x400130b1 -+ MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x400130b1 -+ >; -+ }; -+ - pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 { - fsl,pins = < - MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000 -@@ -193,6 +331,19 @@ - >; - }; - -+ pinctrl_hummingboard_mipi: hummingboard_mipi { -+ fsl,pins = < -+ MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x17059 -+ MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x13059 -+ >; -+ }; -+ -+ pinctrl_hummingboard_pcie_reset: hummingboard-pcie-reset { -+ fsl,pins = < -+ MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b1 -+ >; -+ }; -+ - pinctrl_hummingboard_pwm1: pwm1grp { - fsl,pins = ; - }; -@@ -220,16 +371,21 @@ - * Similar to pinctrl_usbotg_2, but we want it - * pulled down for a fixed host connection. - */ -- fsl,pins = ; -+ fsl,pins = ; - }; - - pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus { - fsl,pins = ; - }; - -+ pinctrl_hummingboard_usdhc2_pwr: hummingboard-usdhc2-pwr { -+ fsl,pins = ; -+ }; -+ - pinctrl_hummingboard_usdhc2_aux: hummingboard-usdhc2-aux { - fsl,pins = < -- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 -+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x13071 -+ MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b071 - >; - }; - -@@ -243,9 +399,73 @@ - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 - >; - }; -+ -+ pinctrl_hummingboard_usdhc2_100mhz: hummingboard-usdhc2-100mhz { -+ fsl,pins = < -+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 -+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 -+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 -+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 -+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 -+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130b9 -+ >; -+ }; -+ -+ pinctrl_hummingboard_usdhc2_200mhz: hummingboard-usdhc2-200mhz { -+ fsl,pins = < -+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 -+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 -+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 -+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 -+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 -+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130f9 -+ >; -+ }; - }; - }; - -+&ldb { -+ status = "disabled"; -+ -+ lvds-channel@0 { -+ fsl,data-mapping = "spwg"; -+ fsl,data-width = <18>; -+ crtc = "ipu2-di0"; -+ primary; -+ -+ display-timings { -+ native-mode = <&timing0>; -+ timing0: hsd100pxn1 { -+ clock-frequency = <65000000>; -+ hactive = <1024>; -+ vactive = <768>; -+ hback-porch = <220>; -+ hfront-porch = <40>; -+ vback-porch = <21>; -+ vfront-porch = <7>; -+ hsync-len = <60>; -+ vsync-len = <10>; -+ }; -+ }; -+ }; -+}; -+ -+&mipi_csi { -+ ipu_id = <0>; -+ csi_id = <1>; -+ v_channel = <0>; -+ lanes = <2>; -+ mipi_dphy_clk = /bits/ 8 <0x28>; -+ status = "okay"; -+}; -+ -+&pcie { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hummingboard_pcie_reset>; -+ reset-gpio = <&gpio3 4 0>; -+ status = "okay"; -+}; -+ - &pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_pwm1>; -@@ -257,10 +477,28 @@ - status = "okay"; - }; - -+&pwm3 { -+ status = "disabled"; -+}; -+ -+&pwm4 { -+ status = "disabled"; -+}; -+ - &spdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_spdif>; - status = "okay"; -+ clocks = <&clks 197>, <&clks 0>, -+ <&clks 197>, <&clks 0>, -+ <&clks 0>, <&clks 0>, -+ <&clks 0>, <&clks 0>, -+ <&clks 0>; -+ clock-names = "core", "rxtx0", -+ "rxtx1", "rxtx2", -+ "rxtx3", "rxtx4", -+ "rxtx5", "rxtx6", -+ "rxtx7"; - }; - - &ssi1 { -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/imx6qdl-microsom.dtsi linux-4.1.13/arch/arm/boot/dts/imx6qdl-microsom.dtsi ---- linux-4.1.13.orig/arch/arm/boot/dts/imx6qdl-microsom.dtsi 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/boot/dts/imx6qdl-microsom.dtsi 2015-11-30 17:56:13.512142253 +0100 -@@ -39,15 +39,98 @@ - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -+#include -+/ { -+ clk_sdio: sdio-clock { -+ compatible = "gpio-gate-clock"; -+ #clock-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_microsom_brcm_osc>; -+ enable-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ regulators { -+ compatible = "simple-bus"; -+ -+ reg_brcm: brcm-reg { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio3 19 0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_microsom_brcm_reg>; -+ regulator-name = "brcm_reg"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <200000>; -+ }; -+ }; -+ -+ usdhc1_pwrseq: usdhc1_pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>, -+ <&gpio6 0 GPIO_ACTIVE_LOW>; -+ clocks = <&clk_sdio>; -+ clock-names = "ext_clock"; -+ }; -+}; - - &iomuxc { - microsom { -+ pinctrl_microsom_brcm_bt: microsom-brcm-bt { -+ fsl,pins = < -+ MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x40013070 -+ MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x40013070 -+ MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40013070 -+ >; -+ }; -+ -+ pinctrl_microsom_brcm_osc: microsom-brcm-osc { -+ fsl,pins = < -+ MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x40013070 -+ >; -+ }; -+ -+ pinctrl_microsom_brcm_reg: microsom-brcm-reg { -+ fsl,pins = < -+ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x40013070 -+ >; -+ }; -+ -+ pinctrl_microsom_brcm_wifi: microsom-brcm-wifi { -+ fsl,pins = < -+ MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x1b0b0 -+ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x40013070 -+ MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x40013070 -+ MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x40013070 -+ >; -+ }; -+ - pinctrl_microsom_uart1: microsom-uart1 { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - >; - }; -+ -+ pinctrl_microsom_uart4: microsom-uart4 { -+ fsl,pins = < -+ MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 -+ MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 -+ MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 -+ MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_microsom_usdhc1: microsom-usdhc1 { -+ fsl,pins = < -+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 -+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 -+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 -+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 -+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 -+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 -+ >; -+ }; - }; - }; - -@@ -56,3 +139,23 @@ - pinctrl-0 = <&pinctrl_microsom_uart1>; - status = "okay"; - }; -+ -+/* UART4 - Connected to optional BRCM Wifi/BT/FM */ -+&uart4 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_microsom_brcm_bt &pinctrl_microsom_uart4>; -+ fsl,uart-has-rtscts; -+ status = "okay"; -+}; -+ -+/* USDHC1 - Connected to optional BRCM Wifi/BT/FM */ -+&usdhc1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_microsom_brcm_wifi &pinctrl_microsom_usdhc1>; -+ bus-width = <4>; -+ mmc-pwrseq = <&usdhc1_pwrseq>; -+ keep-power-in-suspend; -+ non-removable; -+ vmmc-supply = <®_brcm>; -+ status = "okay"; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/imx6qdl-sabresd.dtsi linux-4.1.13/arch/arm/boot/dts/imx6qdl-sabresd.dtsi ---- linux-4.1.13.orig/arch/arm/boot/dts/imx6qdl-sabresd.dtsi 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/boot/dts/imx6qdl-sabresd.dtsi 2015-11-30 17:56:13.512142253 +0100 -@@ -57,6 +57,13 @@ - enable-active-high; - }; - -+ reg_mipi_dsi_pwr_on: mipi_dsi_pwr_on { -+ compatible = "regulator-fixed"; -+ regulator-name = "mipi_dsi_pwr_on"; -+ gpio = <&gpio6 14 0>; -+ enable-active-high; -+ }; -+ - reg_pcie: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; -@@ -133,6 +140,13 @@ - default-state = "on"; - }; - }; -+ -+ mipi_dsi_reset: mipi-dsi-reset { -+ compatible = "gpio-reset"; -+ reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; -+ reset-delay-us = <50>; -+ #reset-cells = <0>; -+ }; - }; - - &audmux { -@@ -332,10 +346,24 @@ - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 -- MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 -- MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 -- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 -- MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 -+ MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 -+ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 -+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 -+ MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 -+ MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000 -+ MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000 -+ MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 -+ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 -+ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 -+ MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 -+ MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x80000000 -+ MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x80000000 -+ MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000 -+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000 -+ MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 -+ MX6QDL_PAD_GPIO_1__WDOG2_B 0x80000000 -+ MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 -+ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 - >; - }; - -@@ -525,6 +553,15 @@ - status = "okay"; - }; - -+&mipi_dsi { -+ dev_id = <0>; -+ disp_id = <1>; -+ lcd_panel = "TRULY-WVGA"; -+ disp-power-on-supply = <®_mipi_dsi_pwr_on>; -+ resets = <&mipi_dsi_reset>; -+ status = "okay"; -+}; -+ - &pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/imx6qdl-sb-fx6.dtsi linux-4.1.13/arch/arm/boot/dts/imx6qdl-sb-fx6.dtsi ---- linux-4.1.13.orig/arch/arm/boot/dts/imx6qdl-sb-fx6.dtsi 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/arch/arm/boot/dts/imx6qdl-sb-fx6.dtsi 2015-11-30 17:56:13.512142253 +0100 -@@ -0,0 +1,116 @@ -+/* -+ * Copyright 2014 CompuLab Ltd. -+ * -+ * Author: Valentin Raevsky -+ * -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/ { -+ backlight { -+ compatible = "pwm-backlight"; -+ pwms = <&pwm3 0 5000000>; -+ brightness-levels = <0 4 8 16 32 64 128 255>; -+ default-brightness-level = <7>; -+ }; -+ -+ i2cmux { -+ compatible = "i2c-mux-gpio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ mux-gpios = <&gpio1 2 0>; -+ i2c-parent = <&i2c1>; -+ -+ i2c@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ pca9555@26 { -+ compatible = "nxp,pca9555"; -+ gpio-controller; -+ #gpio-cells = <2>; -+ reg = <0x26>; -+ }; -+ -+ hx8526@4a { -+ compatible = "himax,himax_ts"; -+ reg = <0x4a>; -+ gpio_intr = <&gpio1 4 0>; -+ }; -+ -+ eeprom@50 { -+ compatible = "at24,24c02"; -+ reg = <0x50>; -+ pagesize = <16>; -+ }; -+ -+ }; -+ -+ i2c@1 { -+ reg = <1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ dvi: edid@50 { -+ compatible = "fsl,imx6-hdmi-i2c"; -+ reg = <0x50>; -+ }; -+ }; -+ -+ }; -+}; -+ -+&i2c1 { -+ status = "okay"; -+}; -+ -+&usdhc3 { -+ wp-gpios = <&gpio7 0 0>; -+ cd-gpios = <&gpio7 1 0>; -+ status = "okay"; -+}; -+ -+&pwm3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm3_1>; -+ status = "okay"; -+}; -+ -+&mxcfb1 { -+ status = "okay"; -+}; -+ -+&mxcfb2 { -+ mode_str ="KD050C-WVGA"; -+ status = "okay"; -+}; -+ -+&mxcfb3 { -+ status = "okay"; -+}; -+ -+&mxcfb4 { -+ status = "okay"; -+}; -+ -+&ldb { -+ ipu_id = <1>; -+ disp_id = <0>; -+ ext_ref = <1>; -+ mode = "sep0"; -+ sec_ipu_id = <1>; -+ sec_disp_id = <1>; -+ status = "okay"; -+}; -+ -+&flexcan1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan1_1>; -+ status = "okay"; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/imx6qdl-sb-fx6m.dtsi linux-4.1.13/arch/arm/boot/dts/imx6qdl-sb-fx6m.dtsi ---- linux-4.1.13.orig/arch/arm/boot/dts/imx6qdl-sb-fx6m.dtsi 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/arch/arm/boot/dts/imx6qdl-sb-fx6m.dtsi 2015-11-30 17:56:13.512142253 +0100 -@@ -0,0 +1,114 @@ -+/* -+ * Copyright 2014 CompuLab Ltd. -+ * -+ * Author: Valentin Raevsky -+ * -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/ { -+ iomux_uart2: pinmux@20E0924 { -+ compatible = "pinctrl-single"; -+ reg = <0x20E0000 0x924>; /* Single register */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-single,register-width = <32>; -+ pinctrl-single,function-mask = <0x4>; -+ }; -+ -+ eth@pcie { -+ compatible = "intel,i211"; -+ local-mac-address = [FF FF FF FF FF FF]; -+ status = "okay"; -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ power { -+ label = "Power Button"; -+ gpios = <&gpio1 29 1>; -+ linux,code = <116>; /* KEY_POWER */ -+ gpio-key,wakeup; -+ }; -+ }; -+ -+ i2cmux { -+ compatible = "i2c-mux-gpio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ mux-gpios = <&gpio1 2 0>; -+ i2c-parent = <&i2c1>; -+ -+ i2c@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ eeprom@50 { -+ compatible = "at24,24c02"; -+ reg = <0x50>; -+ pagesize = <16>; -+ }; -+ -+ rtc@56 { -+ compatible = "emmicro,em3027"; -+ reg = <0x56>; -+ }; -+ }; -+ -+ i2c@1 { -+ reg = <1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ dvi: edid@50 { -+ compatible = "fsl,imx6-hdmi-i2c"; -+ reg = <0x50>; -+ }; -+ }; -+ }; -+}; -+ -+&iomuxc { -+ imx6q-sbc-fx6m { -+ /* pins for uart2 */ -+ pinctrl_uart2: uart2grp { -+ fsl,pins = < -+ MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b0b1 -+ MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b0b1 -+ MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 -+ MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 -+ >; -+ }; -+ }; -+}; -+ -+&i2c1 { -+ status = "okay"; -+}; -+ -+&usdhc3 { -+ non-removable; -+ status = "okay"; -+}; -+ -+/* rear serial console */ -+&uart2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart2>; -+ fsl,uart-has-rtscts; -+ status = "okay"; -+}; -+ -+&mxcfb1 { -+ status = "okay"; -+}; -+ -+&mxcfb2 { -+ status = "okay"; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/imx6qdl-sb-fx6x.dtsi linux-4.1.13/arch/arm/boot/dts/imx6qdl-sb-fx6x.dtsi ---- linux-4.1.13.orig/arch/arm/boot/dts/imx6qdl-sb-fx6x.dtsi 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/arch/arm/boot/dts/imx6qdl-sb-fx6x.dtsi 2015-11-30 17:56:13.512142253 +0100 -@@ -0,0 +1,110 @@ -+/* -+ * Copyright 2014 CompuLab Ltd. -+ * -+ * Author: Valentin Raevsky -+ * -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/ { -+ regulators { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ /* regulator for mmc */ -+ reg_3p3v: 3p3v { -+ compatible = "regulator-fixed"; -+ regulator-name = "3P3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ }; -+ -+}; -+ -+&iomuxc { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_hog>, <&pinctrl_dvi0>; -+ -+ imx6q-sb-fx6x { -+ /* pins for i2c1 */ -+ pinctrl_i2c1: i2c1grp { -+ fsl,pins = < -+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 -+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 -+ >; -+ }; -+ -+ /* pins for mmc */ -+ pinctrl_usdhc3: usdhc3grp { -+ fsl,pins = < -+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 -+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 -+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 -+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 -+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 -+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 -+ MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x80000000 -+ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 -+ >; -+ }; -+ -+ pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { /* 100Mhz */ -+ fsl,pins = < -+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B9 -+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B9 -+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B9 -+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B9 -+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B9 -+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B9 -+ >; -+ }; -+ -+ pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { /* 200Mhz */ -+ fsl,pins = < -+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9 -+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9 -+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9 -+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9 -+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9 -+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9 -+ >; -+ }; -+ -+ /* pins for dvi/ts */ -+ pinctrl_dvi0: dvi0grp { -+ fsl,pins = < -+ /* DVI_DDC_SEL */ -+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 -+ /* SB-FX6 Himax TS PENDOWN or SB-FX6m DVI HPD */ -+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 -+ >; -+ }; -+ }; -+}; -+ -+/* i2c1 */ -+&i2c1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c1>; -+ status = "disabled"; -+}; -+ -+/* mmc */ -+&usdhc3 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_usdhc3>; -+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>; -+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>; -+ no-1-8-v; -+ keep-power-in-suspend; -+ vmmc-supply = <®_3p3v>; -+ status = "disabled"; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/imx6qdl-vero.dtsi linux-4.1.13/arch/arm/boot/dts/imx6qdl-vero.dtsi ---- linux-4.1.13.orig/arch/arm/boot/dts/imx6qdl-vero.dtsi 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/arch/arm/boot/dts/imx6qdl-vero.dtsi 2015-11-30 17:56:13.516141986 +0100 -@@ -0,0 +1,355 @@ -+/* -+ * Copyright (C) 2014 Russell King -+ * Copyright (C) 2015 Sam Nazarko -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPL or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This file is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License. -+ * -+ * This file is distributed in the hope that it will be useful -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+#include "imx6qdl-verosom.dtsi" -+#include "imx6qdl-verosom-ar8035.dtsi" -+#include -+#include -+ -+/ { -+ chosen { -+ bootargs = "quiet console=ttymxc0,115200 rw root=/dev/mmcblk0p2"; -+ }; -+ -+ aliases { -+ mmc0 = &usdhc2; -+ mmc1 = &usdhc1; -+ mxcfb0 = &mxcfb1; -+ }; -+ -+ ir_recv: ir-receiver { -+ compatible = "gpio-ir-receiver"; -+ gpios = <&gpio3 9 1>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_vero_ir>; -+ linux,rc-map-name = "rc-rc6-mce"; -+ }; -+ -+ pwmleds { -+ compatible = "pwm-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_vero_pwm1>; -+ -+ front { -+ active-low; -+ label = "imx6:red:front"; -+ max-brightness = <248>; -+ pwms = <&pwm1 0 50000>; -+ }; -+ }; -+ -+ regulators { -+ compatible = "simple-bus"; -+ -+ reg_3p3v: 3p3v { -+ compatible = "regulator-fixed"; -+ regulator-name = "3P3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ reg_usbh1_vbus: usb-h1-vbus { -+ compatible = "regulator-fixed"; -+ regulator-boot-on; -+ regulator-always-on; -+ enable-active-high; -+ gpio = <&gpio1 0 0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_vero_usbh1_vbus>; -+ regulator-name = "usb_h1_vbus"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ reg_usbotg_vbus: usb-otg-vbus { -+ compatible = "regulator-fixed"; -+ regulator-boot-on; -+ regulator-always-on; -+ enable-active-high; -+ gpio = <&gpio3 22 0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_vero_usbotg_vbus>; -+ regulator-name = "usb_otg_vbus"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ }; -+ -+ sound-spdif { -+ compatible = "fsl,imx-audio-spdif"; -+ model = "imx-spdif"; -+ spdif-controller = <&spdif>; -+ spdif-out; -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ pinctrl-0 = <&pinctrl_gpio_key>; -+ pinctrl-names = "default"; -+ -+ button_0 { -+ label = "Button 0"; -+ gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; -+ linux,code = ; -+ }; -+ }; -+ -+ sound-hdmi { -+ compatible = "fsl,imx6q-audio-hdmi", -+ "fsl,imx-audio-hdmi"; -+ model = "imx-audio-hdmi"; -+ hdmi-controller = <&hdmi_audio>; -+ }; -+ -+ mxcfb1: fb@0 { -+ compatible = "fsl,mxc_sdc_fb"; -+ disp_dev = "hdmi"; -+ interface_pix_fmt = "RGB24"; -+ mode_str ="1920x1080M@60"; -+ default_bpp = <32>; -+ int_clk = <0>; -+ late_init = <0>; -+ status = "okay"; -+ }; -+}; -+ -+&hdmi_core { -+ ipu_id = <0>; -+ disp_id = <0>; -+ status = "okay"; -+}; -+ -+&hdmi_video { -+ fsl,phy_reg_vlev = <0x0294>; -+ fsl,phy_reg_cksymtx = <0x800d>; -+ status = "okay"; -+}; -+ -+&hdmi_audio { -+ status = "okay"; -+}; -+ -+&hdmi_cec { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_vero_hdmi>; -+ status = "okay"; -+}; -+ -+&i2c2 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_vero_i2c2>; -+ -+ status = "okay"; -+ -+ ddc: imx6_hdmi_i2c@50 { -+ compatible = "fsl,imx6-hdmi-i2c"; -+ reg = <0x50>; -+ }; -+}; -+ -+&i2c3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_vero_i2c3>; -+ -+ status = "okay"; -+ -+ rtc: pcf8523@68 { -+ compatible = "nxp,pcf8523"; -+ reg = <0x68>; -+ }; -+}; -+ -+&iomuxc { -+ vero { -+ pinctrl_vero_hdmi: vero-hdmi { -+ fsl,pins = < -+ MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 -+ >; -+ }; -+ -+ pinctrl_vero_i2c2: vero-i2c2 { -+ fsl,pins = < -+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 -+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 -+ >; -+ }; -+ -+ pinctrl_vero_i2c3: vero-i2c3 { -+ fsl,pins = < -+ MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 -+ MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 -+ >; -+ }; -+ -+ pinctrl_vero_ir: vero-ir { -+ fsl,pins = < -+ MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 -+ >; -+ }; -+ -+ pinctrl_vero_pwm1: vero-pwm1-front-led { -+ fsl,pins = ; -+ }; -+ -+ pinctrl_vero_spdif: vero-spdif { -+ fsl,pins = ; -+ }; -+ -+ pinctrl_vero_usbh1: vero-usbh1 { -+ fsl,pins = ; -+ }; -+ -+ pinctrl_vero_usbh1_vbus: vero-usbh1-vbus { -+ fsl,pins = ; -+ }; -+ -+ pinctrl_vero_usbotg: vero-usbotg { -+ /* -+ * The vero pulls ID low, but as it's pointless -+ * leaving it as a pull-up, even if it is just 10uA. -+ */ -+ fsl,pins = < -+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 -+ MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 -+ >; -+ }; -+ -+ pinctrl_vero_usbotg_vbus: vero-usbotg-vbus { -+ fsl,pins = ; -+ }; -+ -+ pinctrl_vero_usdhc2_aux: vero-usdhc2-aux { -+ fsl,pins = < -+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 -+ MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x1b071 -+ >; -+ }; -+ -+ pinctrl_vero_usdhc2: vero-usdhc2 { -+ fsl,pins = < -+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 -+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 -+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 -+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 -+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 -+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 -+ >; -+ }; -+ -+ pinctrl_gpio_key: gpio-key { -+ fsl,pins = < -+ MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x17059 -+ >; -+ }; -+ -+ pinctrl_vero_usdhc2_100mhz: vero-usdhc2-100mhz { -+ fsl,pins = < -+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9 -+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9 -+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9 -+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9 -+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9 -+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130b9 -+ >; -+ }; -+ -+ pinctrl_vero_usdhc2_200mhz: vero-usdhc2-200mhz { -+ fsl,pins = < -+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9 -+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9 -+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9 -+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9 -+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9 -+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130f9 -+ >; -+ }; -+ }; -+}; -+ -+&pwm1 { -+ status = "okay"; -+}; -+ -+&spdif { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_vero_spdif>; -+ status = "okay"; -+}; -+ -+&usbh1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_vero_usbh1>; -+ vbus-supply = <®_usbh1_vbus>; -+ status = "okay"; -+}; -+ -+&usbotg { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_vero_usbotg>; -+ vbus-supply = <®_usbotg_vbus>; -+ status = "okay"; -+}; -+ -+&usdhc2 { -+ pinctrl-names = "default", "state_100mhz", "state_200mhz"; -+ pinctrl-0 = <&pinctrl_vero_usdhc2_aux &pinctrl_vero_usdhc2>; -+ pinctrl-1 = <&pinctrl_vero_usdhc2_aux &pinctrl_vero_usdhc2_100mhz>; -+ pinctrl-2 = <&pinctrl_vero_usdhc2_aux &pinctrl_vero_usdhc2_200mhz>; -+ vmmc-supply = <®_3p3v>; -+ cd-gpios = <&gpio1 4 0>; -+ status = "okay"; -+ no-1-8-v; -+}; -+ -+&dcic1 { -+ dcic_id = <0>; -+ dcic_mux = "dcic-hdmi"; -+ status = "okay"; -+}; -+ -+&dcic2 { -+ dcic_id = <1>; -+ dcic_mux = "dcic-lvds1"; -+ status = "disabled"; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/imx6qdl-verosom-ar8035.dtsi linux-4.1.13/arch/arm/boot/dts/imx6qdl-verosom-ar8035.dtsi ---- linux-4.1.13.orig/arch/arm/boot/dts/imx6qdl-verosom-ar8035.dtsi 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/arch/arm/boot/dts/imx6qdl-verosom-ar8035.dtsi 2015-11-30 17:56:13.516141986 +0100 -@@ -0,0 +1,101 @@ -+/* -+ * Copyright (C) 2013,2014 Russell King -+ * Copyright (C) 2015 Sam Nazarko -+ * -+ * This describes the hookup for an AR8035 to the iMX6 on the Vero -+ * SOM. -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPL or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This file is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License. -+ * -+ * This file is distributed in the hope that it will be useful -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+&fec { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_verosom_enet_ar8035>; -+ phy-mode = "rgmii"; -+ phy-reset-duration = <2>; -+ phy-reset-gpios = <&gpio4 15 0>; -+ status = "okay"; -+}; -+ -+&iomuxc { -+ enet { -+ pinctrl_verosom_enet_ar8035: verosom-enet-ar8035 { -+ fsl,pins = < -+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b8b0 -+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 -+ /* AR8035 reset */ -+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0 -+ /* AR8035 interrupt */ -+ MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x80000000 -+ /* GPIO16 -> AR8035 25MHz */ -+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000 -+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000 -+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 -+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 -+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 -+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 -+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 -+ /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ -+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 -+ /* AR8035 pin strapping: IO voltage: pull up */ -+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 -+ /* AR8035 pin strapping: PHYADDR#0: pull down */ -+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 -+ /* AR8035 pin strapping: PHYADDR#1: pull down */ -+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 -+ /* AR8035 pin strapping: MODE#1: pull up */ -+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 -+ /* AR8035 pin strapping: MODE#3: pull up */ -+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 -+ /* AR8035 pin strapping: MODE#0: pull down */ -+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 -+ -+ /* -+ * As the RMII pins are also connected to RGMII -+ * so that an AR8030 can be placed, set these -+ * to high-z with the same pulls as above. -+ * Use the GPIO settings to avoid changing the -+ * input select registers. -+ */ -+ MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x03000 -+ MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x03000 -+ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x03000 -+ >; -+ }; -+ }; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/imx6qdl-verosom.dtsi linux-4.1.13/arch/arm/boot/dts/imx6qdl-verosom.dtsi ---- linux-4.1.13.orig/arch/arm/boot/dts/imx6qdl-verosom.dtsi 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/arch/arm/boot/dts/imx6qdl-verosom.dtsi 2015-11-30 17:56:13.516141986 +0100 -@@ -0,0 +1,162 @@ -+/* -+ * Copyright (C) 2013,2014 Russell King -+ * Copyright (C) 2015 Sam Nazarko -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPL or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This file is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License. -+ * -+ * This file is distributed in the hope that it will be useful -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+#include -+/ { -+ clk_sdio: sdio-clock { -+ compatible = "gpio-gate-clock"; -+ #clock-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_verosom_brcm_osc>; -+ enable-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ regulators { -+ compatible = "simple-bus"; -+ -+ reg_brcm: brcm-reg { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpio = <&gpio3 19 0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_verosom_brcm_reg>; -+ regulator-name = "brcm_reg"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <200000>; -+ }; -+ }; -+ -+ usdhc1_pwrseq: usdhc1_pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>, -+ <&gpio6 0 GPIO_ACTIVE_LOW>; -+ clocks = <&clk_sdio>; -+ clock-names = "ext_clock"; -+ }; -+}; -+ -+&iomuxc { -+ verosom { -+ pinctrl_verosom_brcm_bt: verosom-brcm-bt { -+ fsl,pins = < -+ MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x40013070 -+ MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x40013070 -+ MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40013070 -+ >; -+ }; -+ -+ pinctrl_verosom_brcm_osc: verosom-brcm-osc { -+ fsl,pins = < -+ MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x40013070 -+ >; -+ }; -+ -+ pinctrl_verosom_brcm_reg: verosom-brcm-reg { -+ fsl,pins = < -+ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x40013070 -+ >; -+ }; -+ -+ pinctrl_verosom_brcm_wifi: verosom-brcm-wifi { -+ fsl,pins = < -+ MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x1b0b0 -+ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x40013070 -+ MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x40013070 -+ MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x40013070 -+ >; -+ }; -+ -+ pinctrl_verosom_uart1: verosom-uart1 { -+ fsl,pins = < -+ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 -+ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_verosom_uart4: verosom-uart4 { -+ fsl,pins = < -+ MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 -+ MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 -+ MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 -+ MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_verosom_usdhc1: verosom-usdhc1 { -+ fsl,pins = < -+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 -+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 -+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 -+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 -+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 -+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 -+ >; -+ }; -+ }; -+}; -+ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_verosom_uart1>; -+ status = "okay"; -+}; -+ -+/* UART4 - Connected to optional BRCM Wifi/BT/FM */ -+&uart4 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_verosom_brcm_bt &pinctrl_verosom_uart4>; -+ fsl,uart-has-rtscts; -+ status = "okay"; -+}; -+ -+/* USDHC1 - Connected to optional BRCM Wifi/BT/FM */ -+&usdhc1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_verosom_brcm_wifi &pinctrl_verosom_usdhc1>; -+ bus-width = <4>; -+ mmc-pwrseq = <&usdhc1_pwrseq>; -+ keep-power-in-suspend; -+ non-removable; -+ vmmc-supply = <®_brcm>; -+ status = "okay"; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/imx6q.dtsi linux-4.1.13/arch/arm/boot/dts/imx6q.dtsi ---- linux-4.1.13.orig/arch/arm/boot/dts/imx6q.dtsi 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/boot/dts/imx6q.dtsi 2015-11-30 17:56:13.516141986 +0100 -@@ -14,6 +14,7 @@ - - / { - aliases { -+ ipu1 = &ipu2; - spi4 = &ecspi5; - }; - -@@ -32,7 +33,7 @@ - 996000 1250000 - 852000 1250000 - 792000 1175000 -- 396000 975000 -+ 396000 1175000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ -@@ -47,9 +48,12 @@ - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, - <&clks IMX6QDL_CLK_STEP>, - <&clks IMX6QDL_CLK_PLL1_SW>, -- <&clks IMX6QDL_CLK_PLL1_SYS>; -+ <&clks IMX6QDL_CLK_PLL1_SYS>, -+ <&clks IMX6QDL_PLL1_BYPASS>, -+ <&clks IMX6QDL_CLK_PLL1>, -+ <&clks IMX6QDL_PLL1_BYPASS_SRC> ; - clock-names = "arm", "pll2_pfd2_396m", "step", -- "pll1_sw", "pll1_sys"; -+ "pll1_sw", "pll1_sys", "pll1_bypass", "pll1", "pll1_bypass_src"; - arm-supply = <®_arm>; - pu-supply = <®_pu>; - soc-supply = <®_soc>; -@@ -78,9 +82,58 @@ - }; - - soc { -- ocram: sram@00900000 { -+ -+ busfreq { /* BUSFREQ */ -+ compatible = "fsl,imx6_busfreq"; -+ clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>, -+ <&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>; -+ clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph", -+ "periph_pre", "periph_clk2", "periph_clk2_sel", "osc"; -+ interrupts = <0 107 0x04>, <0 112 0x4>, <0 113 0x4>, <0 114 0x4>; -+ interrupt-names = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3"; -+ fsl,max_ddr_freq = <528000000>; -+ }; -+ -+ gpu@00130000 { -+ compatible = "fsl,imx6q-gpu"; -+ reg = <0x00130000 0x4000>, <0x00134000 0x4000>, -+ <0x02204000 0x4000>, <0x0 0x0>; -+ reg-names = "iobase_3d", "iobase_2d", -+ "iobase_vg", "phys_baseaddr"; -+ interrupts = <0 9 0x04>, <0 10 0x04>,<0 11 0x04>; -+ interrupt-names = "irq_3d", "irq_2d", "irq_vg"; -+ clocks = <&clks 26>, <&clks 143>, -+ <&clks 27>, <&clks 121>, -+ <&clks 122>, <&clks 74>; -+ clock-names = "gpu2d_axi_clk", "openvg_axi_clk", -+ "gpu3d_axi_clk", "gpu2d_clk", -+ "gpu3d_clk", "gpu3d_shader_clk"; -+ resets = <&src 0>, <&src 3>, <&src 3>; -+ reset-names = "gpu3d", "gpu2d", "gpuvg"; -+ power-domains = <&gpc 1>; -+ }; -+ -+ hdmi_cec: hdmi_cec@00120000 { -+ compatible = "fsl,imx6q-hdmi-cec"; -+ interrupts = <0 115 0x04>; -+ status = "disabled"; -+ }; -+ -+ ocrams: sram@00900000 { -+ compatible = "fsl,lpm-sram"; -+ reg = <0x00900000 0x4000>; -+ clocks = <&clks IMX6QDL_CLK_OCRAM>; -+ }; -+ -+ ocrams_ddr: sram@00904000 { -+ compatible = "fsl,ddr-lpm-sram"; -+ reg = <0x00904000 0x1000>; -+ clocks = <&clks IMX6QDL_CLK_OCRAM>; -+ }; -+ -+ ocram: sram@00905000 { - compatible = "mmio-sram"; -- reg = <0x00900000 0x40000>; -+ reg = <0x00905000 0x3B000>; - clocks = <&clks IMX6QDL_CLK_OCRAM>; - }; - -@@ -101,6 +154,10 @@ - }; - }; - -+ vpu@02040000 { -+ status = "okay"; -+ }; -+ - iomuxc: iomuxc@020e0000 { - compatible = "fsl,imx6q-iomuxc"; - -@@ -142,6 +199,18 @@ - }; - }; - -+ aips-bus@02100000 { /* AIPS2 */ -+ mipi_dsi: mipi@021e0000 { -+ compatible = "fsl,imx6q-mipi-dsi"; -+ reg = <0x021e0000 0x4000>; -+ interrupts = <0 102 0x04>; -+ gpr = <&gpr>; -+ clocks = <&clks IMX6QDL_CLK_HSI_TX>, <&clks IMX6QDL_CLK_VIDEO_27M>; -+ clock-names = "mipi_pllref_clk", "mipi_cfg_clk"; -+ status = "disabled"; -+ }; -+ }; -+ - sata: sata@02200000 { - compatible = "fsl,imx6q-ahci"; - reg = <0x02200000 0x4000>; -@@ -154,165 +223,33 @@ - }; - - ipu2: ipu@02800000 { -- #address-cells = <1>; -- #size-cells = <0>; - compatible = "fsl,imx6q-ipu"; - reg = <0x02800000 0x400000>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, - <0 7 IRQ_TYPE_LEVEL_HIGH>; -- clocks = <&clks IMX6QDL_CLK_IPU2>, -- <&clks IMX6QDL_CLK_IPU2_DI0>, -- <&clks IMX6QDL_CLK_IPU2_DI1>; -- clock-names = "bus", "di0", "di1"; -+ clocks = <&clks 133>, <&clks 134>, <&clks 137>, -+ <&clks 41>, <&clks 42>, -+ <&clks 135>, <&clks 136>; -+ clock-names = "bus", "di0", "di1", -+ "di0_sel", "di1_sel", -+ "ldb_di0", "ldb_di1"; - resets = <&src 4>; -- -- ipu2_csi0: port@0 { -- reg = <0>; -- }; -- -- ipu2_csi1: port@1 { -- reg = <1>; -- }; -- -- ipu2_di0: port@2 { -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <2>; -- -- ipu2_di0_disp0: endpoint@0 { -- }; -- -- ipu2_di0_hdmi: endpoint@1 { -- remote-endpoint = <&hdmi_mux_2>; -- }; -- -- ipu2_di0_mipi: endpoint@2 { -- }; -- -- ipu2_di0_lvds0: endpoint@3 { -- remote-endpoint = <&lvds0_mux_2>; -- }; -- -- ipu2_di0_lvds1: endpoint@4 { -- remote-endpoint = <&lvds1_mux_2>; -- }; -- }; -- -- ipu2_di1: port@3 { -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <3>; -- -- ipu2_di1_hdmi: endpoint@1 { -- remote-endpoint = <&hdmi_mux_3>; -- }; -- -- ipu2_di1_mipi: endpoint@2 { -- }; -- -- ipu2_di1_lvds0: endpoint@3 { -- remote-endpoint = <&lvds0_mux_3>; -- }; -- -- ipu2_di1_lvds1: endpoint@4 { -- remote-endpoint = <&lvds1_mux_3>; -- }; -- }; -- }; -- }; -- -- display-subsystem { -- compatible = "fsl,imx-display-subsystem"; -- ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>; -- }; --}; -- --&hdmi { -- compatible = "fsl,imx6q-hdmi"; -- -- port@2 { -- reg = <2>; -- -- hdmi_mux_2: endpoint { -- remote-endpoint = <&ipu2_di0_hdmi>; -- }; -- }; -- -- port@3 { -- reg = <3>; -- -- hdmi_mux_3: endpoint { -- remote-endpoint = <&ipu2_di1_hdmi>; -+ bypass_reset = <0>; - }; - }; - }; - - &ldb { -- clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, -+ clocks = <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>, - <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, - <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, -- <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; -- clock-names = "di0_pll", "di1_pll", -- "di0_sel", "di1_sel", "di2_sel", "di3_sel", -- "di0", "di1"; -- -- lvds-channel@0 { -- port@2 { -- reg = <2>; -- -- lvds0_mux_2: endpoint { -- remote-endpoint = <&ipu2_di0_lvds0>; -- }; -- }; -- -- port@3 { -- reg = <3>; -- -- lvds0_mux_3: endpoint { -- remote-endpoint = <&ipu2_di1_lvds0>; -- }; -- }; -- }; -- -- lvds-channel@1 { -- port@2 { -- reg = <2>; -- -- lvds1_mux_2: endpoint { -- remote-endpoint = <&ipu2_di0_lvds1>; -- }; -- }; -- -- port@3 { -- reg = <3>; -- -- lvds1_mux_3: endpoint { -- remote-endpoint = <&ipu2_di1_lvds1>; -- }; -- }; -- }; --}; -- --&mipi_dsi { -- ports { -- port@2 { -- reg = <2>; -- -- mipi_mux_2: endpoint { -- remote-endpoint = <&ipu2_di0_mipi>; -- }; -- }; -- -- port@3 { -- reg = <3>; -- -- mipi_mux_3: endpoint { -- remote-endpoint = <&ipu2_di1_mipi>; -- }; -- }; -- }; --}; -- --&vpu { -- compatible = "fsl,imx6q-vpu", "cnm,coda960"; -+ <&clks IMX6QDL_CLK_LDB_DI0_DIV_3_5>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_3_5>, -+ <&clks IMX6QDL_CLK_LDB_DI0_DIV_7>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_7>, -+ <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>; -+ clock-names = "ldb_di0", "ldb_di1", -+ "di0_sel", "di1_sel", -+ "di2_sel", "di3_sel", -+ "ldb_di0_div_3_5", "ldb_di1_div_3_5", -+ "ldb_di0_div_7", "ldb_di1_div_7", -+ "ldb_di0_div_sel", "ldb_di1_div_sel"; - }; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/imx6q-hummingboard2.dts linux-4.1.13/arch/arm/boot/dts/imx6q-hummingboard2.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/imx6q-hummingboard2.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/arch/arm/boot/dts/imx6q-hummingboard2.dts 2015-11-30 17:56:13.516141986 +0100 -@@ -0,0 +1,60 @@ -+/* -+ * Device Tree file for SolidRun HummingBoard2 -+ * Copyright (C) 2015 Rabeeh Khoury -+ * Based on work by Russell King -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPL or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This file is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License. -+ * -+ * This file is distributed in the hope that it will be useful -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+/dts-v1/; -+ -+#include "imx6q.dtsi" -+#include "imx6qdl-hummingboard2.dtsi" -+ -+/ { -+ model = "SolidRun HummingBoard2 Dual/Quad"; -+ compatible = "solidrun,hummingboard2/q", "fsl,imx6q"; -+}; -+ -+&sata { -+ status = "okay"; -+ fsl,transmit-level-mV = <1104>; -+ fsl,transmit-boost-mdB = <0>; -+ fsl,transmit-atten-16ths = <9>; -+ fsl,no-spread-spectrum; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/imx6q-hummingboard.dts linux-4.1.13/arch/arm/boot/dts/imx6q-hummingboard.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/imx6q-hummingboard.dts 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/boot/dts/imx6q-hummingboard.dts 2015-11-30 17:56:13.516141986 +0100 -@@ -48,6 +48,10 @@ - / { - model = "SolidRun HummingBoard Dual/Quad"; - compatible = "solidrun,hummingboard/q", "fsl,imx6q"; -+ -+ sound-sgtl5000 { -+ status = "okay"; -+ }; - }; - - &sata { -@@ -57,3 +61,11 @@ - fsl,transmit-atten-16ths = <9>; - fsl,receive-eq-mdB = <3000>; - }; -+ -+&sgtl5000 { -+ status = "okay"; -+}; -+ -+&rtc { -+ status = "okay"; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/imx6q-sbc-fx6.dts linux-4.1.13/arch/arm/boot/dts/imx6q-sbc-fx6.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/imx6q-sbc-fx6.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/arch/arm/boot/dts/imx6q-sbc-fx6.dts 2015-11-30 17:56:13.516141986 +0100 -@@ -0,0 +1,23 @@ -+/* -+* Copyright 2014 CompuLab Ltd. -+* -+* Author: Valentin Raevsky -+* -+* The code contained herein is licensed under the GNU General Public -+* License. You may obtain a copy of the GNU General Public License -+* Version 2 or later at the following locations: -+* -+* http://www.opensource.org/licenses/gpl-license.html -+* http://www.gnu.org/copyleft/gpl.html -+*/ -+ -+/dts-v1/; -+#include "imx6q.dtsi" -+#include "imx6q-cm-fx6.dtsi" -+#include "imx6qdl-sb-fx6x.dtsi" -+#include "imx6qdl-sb-fx6.dtsi" -+ -+/ { -+ model = "CompuLab CM-FX6 on SBC-FX6"; -+ compatible = "compulab,cm-fx6", "compulab,sbc-fx6", "fsl,imx6q"; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/imx6q-sbc-fx6m.dts linux-4.1.13/arch/arm/boot/dts/imx6q-sbc-fx6m.dts ---- linux-4.1.13.orig/arch/arm/boot/dts/imx6q-sbc-fx6m.dts 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/arch/arm/boot/dts/imx6q-sbc-fx6m.dts 2015-11-30 17:56:13.516141986 +0100 -@@ -0,0 +1,33 @@ -+/* -+* Copyright 2014 CompuLab Ltd. -+* -+* Author: Valentin Raevsky -+* -+* The code contained herein is licensed under the GNU General Public -+* License. You may obtain a copy of the GNU General Public License -+* Version 2 or later at the following locations: -+* -+* http://www.opensource.org/licenses/gpl-license.html -+* http://www.gnu.org/copyleft/gpl.html -+*/ -+ -+/dts-v1/; -+#include "imx6q.dtsi" -+#include "imx6q-cm-fx6.dtsi" -+#include "imx6qdl-sb-fx6x.dtsi" -+#include "imx6qdl-sb-fx6m.dtsi" -+ -+/ { -+ model = "CompuLab CM-FX6 on SBC-FX6m"; -+ compatible = "compulab,cm-fx6", "compulab,sbc-fx6m", "fsl,imx6q"; -+ -+ aliases { -+ mmc0 = &usdhc3; -+ }; -+}; -+ -+&hdmi_core { -+ ipu_id = <1>; -+ disp_id = <0>; -+ status = "okay"; -+}; -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/imx6sl.dtsi linux-4.1.13/arch/arm/boot/dts/imx6sl.dtsi ---- linux-4.1.13.orig/arch/arm/boot/dts/imx6sl.dtsi 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/boot/dts/imx6sl.dtsi 2015-11-30 17:56:13.520141720 +0100 -@@ -457,20 +457,21 @@ - anatop-min-bit-val = <4>; - anatop-min-voltage = <800000>; - anatop-max-voltage = <1375000>; -+ anatop-enable-bit = <0>; - }; - -- regulator-3p0@120 { -+ reg_3p0: regulator-3p0@120 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd3p0"; -- regulator-min-microvolt = <2800000>; -- regulator-max-microvolt = <3150000>; -- regulator-always-on; -+ regulator-min-microvolt = <2625000>; -+ regulator-max-microvolt = <3400000>; - anatop-reg-offset = <0x120>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <0>; - anatop-min-voltage = <2625000>; - anatop-max-voltage = <3400000>; -+ anatop-enable-bit = <0>; - }; - - regulator-2p5@130 { -@@ -485,6 +486,7 @@ - anatop-min-bit-val = <0>; - anatop-min-voltage = <2100000>; - anatop-max-voltage = <2850000>; -+ anatop-enable-bit = <0>; - }; - - reg_arm: regulator-vddcore@140 { -@@ -552,6 +554,7 @@ - reg = <0x020c9000 0x1000>; - interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USBPHY1>; -+ phy-3p0-supply = <®_3p0>; - fsl,anatop = <&anatop>; - }; - -@@ -560,6 +563,7 @@ - reg = <0x020ca000 0x1000>; - interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_USBPHY2>; -+ phy-3p0-supply = <®_3p0>; - fsl,anatop = <&anatop>; - }; - -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/imx6sx.dtsi linux-4.1.13/arch/arm/boot/dts/imx6sx.dtsi ---- linux-4.1.13.orig/arch/arm/boot/dts/imx6sx.dtsi 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/boot/dts/imx6sx.dtsi 2015-11-30 17:56:13.520141720 +0100 -@@ -556,20 +556,21 @@ - anatop-min-bit-val = <4>; - anatop-min-voltage = <800000>; - anatop-max-voltage = <1375000>; -+ anatop-enable-bit = <0>; - }; - -- regulator-3p0@120 { -+ reg_3p0: regulator-3p0@120 { - compatible = "fsl,anatop-regulator"; - regulator-name = "vdd3p0"; -- regulator-min-microvolt = <2800000>; -- regulator-max-microvolt = <3150000>; -- regulator-always-on; -+ regulator-min-microvolt = <2625000>; -+ regulator-max-microvolt = <3400000>; - anatop-reg-offset = <0x120>; - anatop-vol-bit-shift = <8>; - anatop-vol-bit-width = <5>; - anatop-min-bit-val = <0>; - anatop-min-voltage = <2625000>; - anatop-max-voltage = <3400000>; -+ anatop-enable-bit = <0>; - }; - - regulator-2p5@130 { -@@ -584,6 +585,7 @@ - anatop-min-bit-val = <0>; - anatop-min-voltage = <2100000>; - anatop-max-voltage = <2875000>; -+ anatop-enable-bit = <0>; - }; - - reg_arm: regulator-vddcore@140 { -@@ -650,6 +652,7 @@ - reg = <0x020c9000 0x1000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_USBPHY1>; -+ phy-3p0-supply = <®_3p0>; - fsl,anatop = <&anatop>; - }; - -@@ -658,6 +661,7 @@ - reg = <0x020ca000 0x1000>; - interrupts = ; - clocks = <&clks IMX6SX_CLK_USBPHY2>; -+ phy-3p0-supply = <®_3p0>; - fsl,anatop = <&anatop>; - }; - -diff -Nur linux-4.1.13.orig/arch/arm/boot/dts/Makefile linux-4.1.13/arch/arm/boot/dts/Makefile ---- linux-4.1.13.orig/arch/arm/boot/dts/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/boot/dts/Makefile 2015-11-30 17:56:13.520141720 +0100 -@@ -256,6 +256,7 @@ - dtb-$(CONFIG_SOC_IMX6Q) += \ - imx6dl-aristainetos_4.dtb \ - imx6dl-aristainetos_7.dtb \ -+ imx6dl-cm-fx6.dtb \ - imx6dl-cubox-i.dtb \ - imx6dl-dfi-fs700-m60.dtb \ - imx6dl-gw51xx.dtb \ -@@ -264,6 +265,7 @@ - imx6dl-gw54xx.dtb \ - imx6dl-gw552x.dtb \ - imx6dl-hummingboard.dtb \ -+ imx6dl-hummingboard2.dtb \ - imx6dl-nitrogen6x.dtb \ - imx6dl-phytec-pbab01.dtb \ - imx6dl-rex-basic.dtb \ -@@ -275,6 +277,8 @@ - imx6dl-tx6u-801x.dtb \ - imx6dl-tx6u-811x.dtb \ - imx6dl-udoo.dtb \ -+ imx6dl-sbc-fx6.dtb \ -+ imx6dl-sbc-fx6m.dtb \ - imx6dl-wandboard.dtb \ - imx6dl-wandboard-revb1.dtb \ - imx6q-arm2.dtb \ -@@ -290,12 +294,20 @@ - imx6q-gw54xx.dtb \ - imx6q-gw552x.dtb \ - imx6q-hummingboard.dtb \ -+ imx6q-hummingboard2.dtb \ - imx6q-nitrogen6x.dtb \ - imx6q-phytec-pbab01.dtb \ - imx6q-rex-pro.dtb \ - imx6q-sabreauto.dtb \ - imx6q-sabrelite.dtb \ - imx6q-sabresd.dtb \ -+ imx6q-sabresd-ldo.dtb \ -+ imx6q-sabresd-enetirq.dtb \ -+ imx6q-sabresd-uart.dtb \ -+ imx6q-sabresd-hdcp.dtb \ -+ imx6q-sabresd-ldo.dtb \ -+ imx6q-sbc-fx6.dtb \ -+ imx6q-sbc-fx6m.dtb \ - imx6q-sbc6x.dtb \ - imx6q-tbs2910.dtb \ - imx6q-tx6q-1010.dtb \ -@@ -305,7 +317,8 @@ - imx6q-tx6q-1110.dtb \ - imx6q-udoo.dtb \ - imx6q-wandboard.dtb \ -- imx6q-wandboard-revb1.dtb -+ imx6q-wandboard-revb1.dtb \ -+ imx6dl-vero.dtb - dtb-$(CONFIG_SOC_IMX6SL) += \ - imx6sl-evk.dtb \ - imx6sl-warp.dtb -diff -Nur linux-4.1.13.orig/arch/arm/configs/cm_fx6_defconfig linux-4.1.13/arch/arm/configs/cm_fx6_defconfig ---- linux-4.1.13.orig/arch/arm/configs/cm_fx6_defconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/arch/arm/configs/cm_fx6_defconfig 2015-11-30 17:56:13.520141720 +0100 -@@ -0,0 +1,443 @@ -+CONFIG_LOCALVERSION="-cm-fx6" -+CONFIG_KERNEL_LZO=y -+CONFIG_SYSVIPC=y -+CONFIG_NO_HZ=y -+CONFIG_HIGH_RES_TIMERS=y -+CONFIG_IKCONFIG=y -+CONFIG_IKCONFIG_PROC=y -+CONFIG_LOG_BUF_SHIFT=18 -+CONFIG_CGROUPS=y -+CONFIG_RELAY=y -+CONFIG_BLK_DEV_INITRD=y -+CONFIG_EXPERT=y -+CONFIG_PERF_EVENTS=y -+# CONFIG_SLUB_DEBUG is not set -+# CONFIG_COMPAT_BRK is not set -+CONFIG_MODULES=y -+CONFIG_MODULE_UNLOAD=y -+CONFIG_MODVERSIONS=y -+CONFIG_MODULE_SRCVERSION_ALL=y -+# CONFIG_BLK_DEV_BSG is not set -+CONFIG_GPIO_PCA953X=y -+CONFIG_ARCH_MXC=y -+CONFIG_MXC_DEBUG_BOARD=y -+CONFIG_MACH_IMX51_DT=y -+CONFIG_MACH_EUKREA_CPUIMX51SD=y -+CONFIG_SOC_IMX53=y -+CONFIG_SOC_IMX6Q=y -+CONFIG_SOC_IMX6SL=y -+CONFIG_SOC_IMX6SX=y -+CONFIG_SOC_VF610=y -+# CONFIG_SWP_EMULATE is not set -+CONFIG_PCI=y -+CONFIG_PCI_IMX6=y -+CONFIG_SMP=y -+CONFIG_VMSPLIT_2G=y -+CONFIG_PREEMPT=y -+CONFIG_AEABI=y -+CONFIG_HIGHMEM=y -+CONFIG_CMA=y -+CONFIG_CMDLINE="console=ttymxc3,115200 root=/dev/mmcblk0p1 rootwait" -+CONFIG_CPU_FREQ=y -+CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y -+CONFIG_CPU_FREQ_GOV_POWERSAVE=y -+CONFIG_CPU_FREQ_GOV_USERSPACE=y -+CONFIG_CPU_FREQ_GOV_ONDEMAND=y -+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -+CONFIG_ARM_IMX6Q_CPUFREQ=y -+CONFIG_CPU_IDLE=y -+CONFIG_VFP=y -+CONFIG_NEON=y -+CONFIG_BINFMT_MISC=m -+CONFIG_PM_RUNTIME=y -+CONFIG_PM_DEBUG=y -+CONFIG_PM_TEST_SUSPEND=y -+CONFIG_NET=y -+CONFIG_PACKET=y -+CONFIG_UNIX=y -+CONFIG_INET=y -+CONFIG_IP_PNP=y -+CONFIG_IP_PNP_DHCP=y -+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -+# CONFIG_INET_XFRM_MODE_TUNNEL is not set -+# CONFIG_INET_XFRM_MODE_BEET is not set -+# CONFIG_INET_LRO is not set -+CONFIG_IPV6=y -+CONFIG_NETFILTER=y -+CONFIG_NETFILTER_DEBUG=y -+CONFIG_NF_CONNTRACK=m -+CONFIG_NF_CONNTRACK_FTP=m -+CONFIG_NF_CONNTRACK_TFTP=m -+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m -+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m -+CONFIG_NETFILTER_XT_TARGET_DSCP=m -+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m -+CONFIG_NETFILTER_XT_TARGET_LED=m -+CONFIG_NETFILTER_XT_TARGET_MARK=m -+CONFIG_NETFILTER_XT_TARGET_NFLOG=m -+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m -+CONFIG_NETFILTER_XT_TARGET_TEE=m -+CONFIG_NETFILTER_XT_TARGET_TRACE=m -+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m -+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m -+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m -+CONFIG_NETFILTER_XT_MATCH_COMMENT=m -+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m -+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -+CONFIG_NETFILTER_XT_MATCH_CPU=m -+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m -+CONFIG_NETFILTER_XT_MATCH_DSCP=m -+CONFIG_NETFILTER_XT_MATCH_ESP=m -+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m -+CONFIG_NETFILTER_XT_MATCH_HELPER=m -+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m -+CONFIG_NETFILTER_XT_MATCH_LENGTH=m -+CONFIG_NETFILTER_XT_MATCH_LIMIT=m -+CONFIG_NETFILTER_XT_MATCH_MAC=m -+CONFIG_NETFILTER_XT_MATCH_MARK=m -+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -+CONFIG_NETFILTER_XT_MATCH_OSF=m -+CONFIG_NETFILTER_XT_MATCH_OWNER=m -+CONFIG_NETFILTER_XT_MATCH_POLICY=m -+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -+CONFIG_NETFILTER_XT_MATCH_QUOTA=m -+CONFIG_NETFILTER_XT_MATCH_RATEEST=m -+CONFIG_NETFILTER_XT_MATCH_REALM=m -+CONFIG_NETFILTER_XT_MATCH_RECENT=m -+CONFIG_NETFILTER_XT_MATCH_STATE=m -+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -+CONFIG_NETFILTER_XT_MATCH_STRING=m -+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -+CONFIG_NETFILTER_XT_MATCH_TIME=m -+CONFIG_NETFILTER_XT_MATCH_U32=m -+CONFIG_NF_CONNTRACK_IPV4=m -+CONFIG_IP_NF_IPTABLES=y -+CONFIG_IP_NF_MATCH_AH=m -+CONFIG_IP_NF_MATCH_ECN=m -+CONFIG_IP_NF_MATCH_RPFILTER=m -+CONFIG_IP_NF_MATCH_TTL=m -+CONFIG_IP_NF_FILTER=y -+CONFIG_IP_NF_TARGET_REJECT=y -+CONFIG_IP_NF_TARGET_ULOG=m -+CONFIG_NF_NAT_IPV4=m -+CONFIG_IP_NF_TARGET_MASQUERADE=m -+CONFIG_IP_NF_TARGET_NETMAP=m -+CONFIG_IP_NF_TARGET_REDIRECT=m -+CONFIG_IP_NF_MANGLE=m -+CONFIG_IP_NF_TARGET_ECN=m -+CONFIG_IP_NF_TARGET_TTL=m -+CONFIG_IP_NF_RAW=m -+CONFIG_IP_NF_ARPTABLES=m -+CONFIG_IP_NF_ARPFILTER=m -+CONFIG_IP_NF_ARP_MANGLE=m -+CONFIG_VLAN_8021Q=m -+CONFIG_VLAN_8021Q_GVRP=y -+CONFIG_CAN=y -+CONFIG_CAN_FLEXCAN=y -+CONFIG_BT=m -+CONFIG_BT_MRVL=m -+CONFIG_BT_MRVL_SDIO=m -+CONFIG_CFG80211=y -+CONFIG_CFG80211_WEXT=y -+CONFIG_MAC80211=y -+CONFIG_DEVTMPFS=y -+CONFIG_DEVTMPFS_MOUNT=y -+# CONFIG_STANDALONE is not set -+CONFIG_IMX_WEIM=y -+CONFIG_CONNECTOR=y -+CONFIG_MTD=y -+CONFIG_MTD_CMDLINE_PARTS=y -+CONFIG_MTD_BLOCK=y -+CONFIG_MTD_CFI=y -+CONFIG_MTD_JEDECPROBE=y -+CONFIG_MTD_CFI_INTELEXT=y -+CONFIG_MTD_CFI_AMDSTD=y -+CONFIG_MTD_CFI_STAA=y -+CONFIG_MTD_PHYSMAP_OF=y -+CONFIG_MTD_DATAFLASH=y -+CONFIG_MTD_SST25L=y -+CONFIG_MTD_NAND=y -+CONFIG_MTD_NAND_GPMI_NAND=y -+CONFIG_MTD_NAND_MXC=y -+CONFIG_MTD_UBI=y -+CONFIG_BLK_DEV_LOOP=y -+CONFIG_BLK_DEV_RAM=y -+CONFIG_BLK_DEV_RAM_SIZE=65536 -+CONFIG_EEPROM_AT24=y -+CONFIG_EEPROM_AT25=y -+# CONFIG_SCSI_PROC_FS is not set -+CONFIG_BLK_DEV_SD=y -+CONFIG_SCSI_MULTI_LUN=y -+CONFIG_SCSI_CONSTANTS=y -+CONFIG_SCSI_LOGGING=y -+CONFIG_SCSI_SCAN_ASYNC=y -+# CONFIG_SCSI_LOWLEVEL is not set -+CONFIG_ATA=y -+CONFIG_SATA_AHCI=y -+CONFIG_SATA_AHCI_PLATFORM=y -+CONFIG_AHCI_IMX=y -+CONFIG_PATA_IMX=y -+CONFIG_NETDEVICES=y -+CONFIG_TUN=m -+# CONFIG_NET_VENDOR_BROADCOM is not set -+CONFIG_CS89x0=y -+CONFIG_CS89x0_PLATFORM=y -+# CONFIG_NET_VENDOR_FARADAY is not set -+CONFIG_IGB=m -+# CONFIG_NET_VENDOR_MARVELL is not set -+# CONFIG_NET_VENDOR_MICREL is not set -+# CONFIG_NET_VENDOR_MICROCHIP is not set -+# CONFIG_NET_VENDOR_NATSEMI is not set -+# CONFIG_NET_VENDOR_SEEQ is not set -+CONFIG_SMC91X=y -+CONFIG_SMC911X=y -+CONFIG_SMSC911X=y -+# CONFIG_NET_VENDOR_STMICRO is not set -+CONFIG_ATH_CARDS=y -+CONFIG_ATH6KL=m -+CONFIG_ATH6KL_SDIO=m -+CONFIG_MWIFIEX=m -+CONFIG_MWIFIEX_SDIO=m -+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -+CONFIG_INPUT_EVDEV=y -+CONFIG_INPUT_EVBUG=m -+CONFIG_KEYBOARD_GPIO=y -+CONFIG_KEYBOARD_IMX=y -+CONFIG_MOUSE_PS2=m -+CONFIG_MOUSE_PS2_ELANTECH=y -+CONFIG_INPUT_TOUCHSCREEN=y -+CONFIG_TOUCHSCREEN_EGALAX=y -+CONFIG_TOUCHSCREEN_ELAN=y -+CONFIG_TOUCHSCREEN_MAX11801=y -+CONFIG_TOUCHSCREEN_MC13783=y -+CONFIG_INPUT_MISC=y -+CONFIG_INPUT_MMA8450=y -+CONFIG_INPUT_ISL29023=y -+CONFIG_SERIO_SERPORT=m -+# CONFIG_LEGACY_PTYS is not set -+# CONFIG_DEVKMEM is not set -+CONFIG_SERIAL_IMX=y -+CONFIG_SERIAL_IMX_CONSOLE=y -+CONFIG_SERIAL_FSL_LPUART=y -+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y -+CONFIG_FSL_OTP=y -+# CONFIG_I2C_COMPAT is not set -+CONFIG_I2C_CHARDEV=y -+CONFIG_I2C_MUX_GPIO=y -+CONFIG_I2C_MUX_PCA954x=y -+# CONFIG_I2C_HELPER_AUTO is not set -+CONFIG_I2C_ALGOPCF=m -+CONFIG_I2C_ALGOPCA=m -+CONFIG_I2C_IMX=y -+CONFIG_SPI=y -+CONFIG_SPI_IMX=y -+CONFIG_GPIO_SYSFS=y -+CONFIG_POWER_SUPPLY=y -+CONFIG_SABRESD_MAX8903=y -+CONFIG_IMX6_USB_CHARGER=y -+CONFIG_SENSORS_MAX17135=y -+CONFIG_SENSORS_MAG3110=y -+CONFIG_THERMAL=y -+CONFIG_CPU_THERMAL=y -+CONFIG_IMX_THERMAL=y -+CONFIG_DEVICE_THERMAL=y -+CONFIG_WATCHDOG=y -+CONFIG_IMX2_WDT=y -+CONFIG_MFD_DA9052_I2C=y -+CONFIG_MFD_MC13XXX_SPI=y -+CONFIG_MFD_MC13XXX_I2C=y -+CONFIG_MFD_MAX17135=y -+CONFIG_MFD_SI476X_CORE=y -+CONFIG_REGULATOR=y -+CONFIG_REGULATOR_FIXED_VOLTAGE=y -+CONFIG_REGULATOR_ANATOP=y -+CONFIG_REGULATOR_DA9052=y -+CONFIG_REGULATOR_MAX17135=y -+CONFIG_REGULATOR_MC13783=y -+CONFIG_REGULATOR_MC13892=y -+CONFIG_REGULATOR_PFUZE100=y -+CONFIG_MEDIA_SUPPORT=y -+CONFIG_MEDIA_CAMERA_SUPPORT=y -+CONFIG_MEDIA_RADIO_SUPPORT=y -+CONFIG_MEDIA_USB_SUPPORT=y -+CONFIG_USB_VIDEO_CLASS=m -+CONFIG_V4L_PLATFORM_DRIVERS=y -+CONFIG_VIDEO_MXC_OUTPUT=y -+CONFIG_VIDEO_MXC_CAPTURE=m -+CONFIG_MXC_CAMERA_OV5640=m -+CONFIG_MXC_CAMERA_OV5642=m -+CONFIG_MXC_CAMERA_OV5640_MIPI=m -+CONFIG_MXC_TVIN_ADV7180=m -+CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m -+CONFIG_VIDEO_MXC_IPU_OUTPUT=y -+CONFIG_VIDEO_MXC_PXP_V4L2=y -+CONFIG_VIDEO_MXC_CSI_CAMERA=m -+CONFIG_SOC_CAMERA=y -+CONFIG_VIDEO_MX3=y -+CONFIG_RADIO_SI476X=y -+CONFIG_SOC_CAMERA_OV2640=y -+CONFIG_DRM=y -+CONFIG_DRM_VIVANTE=y -+CONFIG_FB_MXS=y -+CONFIG_BACKLIGHT_LCD_SUPPORT=y -+CONFIG_LCD_CLASS_DEVICE=y -+CONFIG_LCD_L4F00242T03=y -+CONFIG_LCD_PLATFORM=y -+CONFIG_BACKLIGHT_CLASS_DEVICE=y -+CONFIG_BACKLIGHT_PWM=y -+CONFIG_FB_MXC_SYNC_PANEL=y -+CONFIG_FB_MXC_LDB=y -+CONFIG_FB_MXC_MIPI_DSI=y -+CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y -+CONFIG_FB_MXC_HDMI=y -+CONFIG_FB_MXC_EINK_PANEL=y -+CONFIG_FB_MXS_SII902X=y -+CONFIG_HANNSTAR_CABC=y -+CONFIG_FRAMEBUFFER_CONSOLE=y -+CONFIG_LOGO=y -+CONFIG_SOUND=y -+CONFIG_SND=y -+CONFIG_SND_USB_AUDIO=m -+CONFIG_SND_SOC=y -+CONFIG_SND_SOC_FSL_ASRC=y -+CONFIG_SND_SOC_FSL_SAI=y -+CONFIG_SND_SOC_FSL_SSI=y -+CONFIG_SND_SOC_FSL_ESAI=y -+CONFIG_SND_SOC_IMX_AUDMUX=y -+CONFIG_SND_IMX_SOC=y -+CONFIG_SND_SOC_IMX_SPDIF=y -+CONFIG_SND_SOC_IMX_HDMI=y -+CONFIG_SND_SOC_CS42XX8_I2C=y -+CONFIG_USB=y -+CONFIG_USB_OTG=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_MXC=y -+CONFIG_USB_EHCI_HCD_PLATFORM=y -+CONFIG_USB_STORAGE=y -+CONFIG_USB_CHIPIDEA=y -+CONFIG_USB_CHIPIDEA_UDC=y -+CONFIG_USB_CHIPIDEA_HOST=y -+CONFIG_NOP_USB_XCEIV=y -+CONFIG_USB_MXS_PHY=y -+CONFIG_USB_GADGET=y -+CONFIG_USB_FSL_USB2=y -+CONFIG_USB_ZERO=m -+CONFIG_USB_AUDIO=m -+CONFIG_USB_ETH=m -+CONFIG_USB_MASS_STORAGE=m -+CONFIG_USB_G_SERIAL=m -+CONFIG_MMC=y -+CONFIG_MMC_UNSAFE_RESUME=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_PLTFM=y -+CONFIG_MMC_SDHCI_ESDHC_IMX=y -+CONFIG_MXC_IPU=y -+CONFIG_MXC_GPU_VIV=y -+CONFIG_MXC_MIPI_CSI2=y -+CONFIG_MXC_MLB150=m -+CONFIG_NEW_LEDS=y -+CONFIG_LEDS_CLASS=y -+CONFIG_LEDS_GPIO=y -+CONFIG_LEDS_TRIGGERS=y -+CONFIG_LEDS_TRIGGER_GPIO=y -+CONFIG_RTC_CLASS=y -+CONFIG_RTC_INTF_DEV_UIE_EMUL=y -+CONFIG_RTC_DRV_EM3027=y -+CONFIG_RTC_DRV_MC13XXX=y -+CONFIG_RTC_DRV_MXC=y -+CONFIG_RTC_DRV_SNVS=y -+CONFIG_DMADEVICES=y -+CONFIG_MXC_PXP_V2=y -+CONFIG_IMX_SDMA=y -+CONFIG_MXS_DMA=y -+CONFIG_STAGING=y -+CONFIG_DRM_IMX=y -+CONFIG_DRM_IMX_FB_HELPER=y -+CONFIG_DRM_IMX_PARALLEL_DISPLAY=y -+CONFIG_DRM_IMX_LDB=y -+CONFIG_DRM_IMX_IPUV3_CORE=y -+CONFIG_DRM_IMX_IPUV3=y -+CONFIG_DRM_IMX_HDMI=y -+# CONFIG_IOMMU_SUPPORT is not set -+CONFIG_PWM=y -+CONFIG_PWM_IMX=y -+CONFIG_EXT2_FS=y -+CONFIG_EXT2_FS_XATTR=y -+CONFIG_EXT2_FS_POSIX_ACL=y -+CONFIG_EXT2_FS_SECURITY=y -+CONFIG_EXT3_FS=y -+CONFIG_EXT3_FS_POSIX_ACL=y -+CONFIG_EXT3_FS_SECURITY=y -+CONFIG_EXT4_FS=y -+CONFIG_EXT4_FS_POSIX_ACL=y -+CONFIG_EXT4_FS_SECURITY=y -+CONFIG_QUOTA=y -+CONFIG_QUOTA_NETLINK_INTERFACE=y -+# CONFIG_PRINT_QUOTA_WARNING is not set -+CONFIG_AUTOFS4_FS=y -+CONFIG_FUSE_FS=y -+CONFIG_ISO9660_FS=m -+CONFIG_JOLIET=y -+CONFIG_ZISOFS=y -+CONFIG_UDF_FS=m -+CONFIG_MSDOS_FS=m -+CONFIG_VFAT_FS=y -+CONFIG_TMPFS=y -+CONFIG_JFFS2_FS=y -+CONFIG_UBIFS_FS=y -+CONFIG_NFS_FS=y -+CONFIG_NFS_V3_ACL=y -+CONFIG_NFS_V4=y -+CONFIG_ROOT_NFS=y -+CONFIG_NLS_DEFAULT="cp437" -+CONFIG_NLS_CODEPAGE_437=y -+CONFIG_NLS_ASCII=y -+CONFIG_NLS_ISO8859_1=y -+CONFIG_NLS_ISO8859_15=m -+CONFIG_NLS_UTF8=y -+CONFIG_MAGIC_SYSRQ=y -+# CONFIG_SCHED_DEBUG is not set -+# CONFIG_DEBUG_BUGVERBOSE is not set -+# CONFIG_FTRACE is not set -+CONFIG_SECURITYFS=y -+CONFIG_CRYPTO_USER=y -+CONFIG_CRYPTO_TEST=m -+CONFIG_CRYPTO_GCM=y -+CONFIG_CRYPTO_CBC=y -+CONFIG_CRYPTO_CTS=y -+CONFIG_CRYPTO_ECB=y -+CONFIG_CRYPTO_LRW=y -+CONFIG_CRYPTO_XTS=y -+CONFIG_CRYPTO_MD4=y -+CONFIG_CRYPTO_MD5=y -+CONFIG_CRYPTO_MICHAEL_MIC=y -+CONFIG_CRYPTO_RMD128=y -+CONFIG_CRYPTO_RMD160=y -+CONFIG_CRYPTO_RMD256=y -+CONFIG_CRYPTO_RMD320=y -+CONFIG_CRYPTO_SHA1=y -+CONFIG_CRYPTO_SHA256=y -+CONFIG_CRYPTO_SHA512=y -+CONFIG_CRYPTO_TGR192=y -+CONFIG_CRYPTO_WP512=y -+CONFIG_CRYPTO_BLOWFISH=y -+CONFIG_CRYPTO_CAMELLIA=y -+CONFIG_CRYPTO_DES=y -+CONFIG_CRYPTO_TWOFISH=y -+# CONFIG_CRYPTO_ANSI_CPRNG is not set -+CONFIG_CRYPTO_DEV_FSL_CAAM=y -+CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y -+CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=y -+CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y -+CONFIG_CRC_CCITT=m -+CONFIG_CRC_T10DIF=y -+CONFIG_CRC7=m -+CONFIG_LIBCRC32C=m -+CONFIG_FONTS=y -+CONFIG_FONT_8x8=y -+CONFIG_FONT_8x16=y -diff -Nur linux-4.1.13.orig/arch/arm/configs/imx_v7_cbi_hb_base_defconfig linux-4.1.13/arch/arm/configs/imx_v7_cbi_hb_base_defconfig ---- linux-4.1.13.orig/arch/arm/configs/imx_v7_cbi_hb_base_defconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/arch/arm/configs/imx_v7_cbi_hb_base_defconfig 2015-11-30 17:56:13.524141455 +0100 -@@ -0,0 +1,367 @@ -+# CONFIG_LOCALVERSION_AUTO is not set -+CONFIG_KERNEL_LZO=y -+CONFIG_SYSVIPC=y -+CONFIG_FHANDLE=y -+CONFIG_NO_HZ=y -+CONFIG_HIGH_RES_TIMERS=y -+CONFIG_LOG_BUF_SHIFT=18 -+CONFIG_CGROUPS=y -+CONFIG_RELAY=y -+CONFIG_BLK_DEV_INITRD=y -+CONFIG_EXPERT=y -+CONFIG_PERF_EVENTS=y -+CONFIG_CLEANCACHE=y -+# CONFIG_SLUB_DEBUG is not set -+# CONFIG_COMPAT_BRK is not set -+CONFIG_MODULES=y -+CONFIG_MODULE_UNLOAD=y -+CONFIG_MODVERSIONS=y -+CONFIG_MODULE_SRCVERSION_ALL=y -+# CONFIG_BLK_DEV_BSG is not set -+CONFIG_GPIO_PCA953X=y -+CONFIG_ARCH_MXC=y -+CONFIG_MXC_DEBUG_BOARD=y -+CONFIG_SOC_IMX6Q=y -+# CONFIG_SOC_IMX6SL is not set -+# CONFIG_SOC_IMX6SX is not set -+# CONFIG_SWP_EMULATE is not set -+CONFIG_PCI=y -+CONFIG_PCIE_DW=y -+CONFIG_PCI_IMX6=y -+CONFIG_SMP=y -+CONFIG_VMSPLIT_3G=y -+CONFIG_PREEMPT_VOLUNTARY=y -+CONFIG_AEABI=y -+# CONFIG_OABI_COMPAT is not set -+CONFIG_HIGHMEM=y -+CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" -+CONFIG_CPU_FREQ=y -+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -+CONFIG_CPU_FREQ_GOV_POWERSAVE=y -+CONFIG_CPU_FREQ_GOV_USERSPACE=y -+CONFIG_CPU_FREQ_GOV_ONDEMAND=y -+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -+CONFIG_ARM_IMX6_CPUFREQ=y -+CONFIG_CPU_IDLE=y -+CONFIG_VFP=y -+CONFIG_VFPv3=y -+CONFIG_NEON=y -+CONFIG_KERNEL_MODE_NEON=y -+CONFIG_BINFMT_MISC=m -+CONFIG_PM=y -+CONFIG_SUSPEND=y -+# CONFIG_PM_DEBUG is not set -+# CONFIG_PM_TEST_SUSPEND is not set -+CONFIG_IOSCHED_BFQ=y -+CONFIG_CGROUP_BFQIO=y -+CONFIG_DEFAULT_BFQ=y -+CONFIG_DEFAULT_IOSCHED="bfq" -+CONFIG_NET=y -+CONFIG_PACKET=y -+CONFIG_UNIX=y -+CONFIG_INET=y -+CONFIG_IP_PNP=y -+CONFIG_IP_PNP_DHCP=y -+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -+# CONFIG_INET_XFRM_MODE_TUNNEL is not set -+# CONFIG_INET_XFRM_MODE_BEET is not set -+# CONFIG_INET_LRO is not set -+CONFIG_IPV6=y -+CONFIG_NETFILTER=y -+CONFIG_VLAN_8021Q=y -+CONFIG_WIRELESS=y -+CONFIG_WIRELESS_EXT=y -+CONFIG_WEXT_CORE=y -+CONFIG_WEXT_PROC=y -+CONFIG_WEXT_SPY=y -+CONFIG_WEXT_PRIV=y -+CONFIG_CFG80211=y -+CONFIG_ETHERNET=y -+# CONFIG_NET_VENDOR_BROADCOM is not set -+# CONFIG_NET_VENDOR_CIRRUS is not set -+# CONFIG_NET_VENDOR_FARADAY -+# CONFIG_NET_VENDOR_INTEL -+# CONFIG_NET_VENDOR_I825XX -+# CONFIG_NET_VENDOR_MARVELL -+# CONFIG_NET_VENDOR_MICROCHIP -+# CONFIG_NET_VENDOR_MICROCHIP=y -+# CONFIG_ENC28J60 is not set -+# CONFIG_NET_VENDOR_NATSEMI=y -+# CONFIG_NET_VENDOR_8390=y -+# CONFIG_AX88796 is not set -+# CONFIG_ETHOC is not set -+# CONFIG_SH_ETH is not set -+# CONFIG_NET_VENDOR_SEEQ=y -+# CONFIG_NET_VENDOR_SMSC=y -+# CONFIG_SMC91X is not set -+# CONFIG_SMC911X is not set -+# CONFIG_SMSC911X is not set -+# CONFIG_NET_VENDOR_STMICRO=y -+# CONFIG_STMMAC_ETH is not set -+# CONFIG_NET_VENDOR_VIA=y -+# CONFIG_VIA_VELOCITY is not set -+# CONFIG_NET_VENDOR_WIZNET=y -+CONFIG_NET_VENDOR_FREESCALE=y -+CONFIG_FEC=y -+CONFIG_PHYLIB=y -+CONFIG_AT803X_PHY=y -+CONFIG_WLAN=y -+CONFIG_BRCMUTIL=m -+CONFIG_BRCMFMAC=m -+CONFIG_BRCMFMAC_SDIO=y -+CONFIG_DEVTMPFS=y -+CONFIG_DEVTMPFS_MOUNT=y -+# CONFIG_STANDALONE is not set -+CONFIG_DMA_CMA=y -+CONFIG_CMA=y -+CONFIG_CMA_SIZE_MBYTES=256 -+CONFIG_CONNECTOR=y -+# CONFIG_MTD is not set -+CONFIG_BLK_DEV_LOOP=y -+CONFIG_BLK_DEV_RAM=y -+CONFIG_BLK_DEV_RAM_SIZE=65536 -+# CONFIG_SCSI_PROC_FS is not set -+CONFIG_BLK_DEV_SD=y -+CONFIG_SCSI_MULTI_LUN=y -+CONFIG_SCSI_CONSTANTS=y -+CONFIG_SCSI_LOGGING=y -+CONFIG_SCSI_SCAN_ASYNC=y -+# CONFIG_SCSI_LOWLEVEL is not set -+CONFIG_ATA=y -+CONFIG_SATA_AHCI_PLATFORM=y -+CONFIG_AHCI_IMX=y -+CONFIG_NETDEVICES=y -+CONFIG_INPUT_EVDEV=y -+# CONFIG_INPUT_EVBUG is not set -+CONFIG_KEYBOARD_GPIO=y -+CONFIG_KEYBOARD_IMX=y -+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -+# CONFIG_KEYBOARD_ATKBD is not set -+# CONFIG_MOUSE_PS2 is not set -+CONFIG_INPUT_MISC=y -+CONFIG_SERIO_SERPORT=m -+CONFIG_VT_HW_CONSOLE_BINDING=y -+# CONFIG_LEGACY_PTYS is not set -+# CONFIG_DEVKMEM is not set -+CONFIG_SERIAL_IMX=y -+CONFIG_SERIAL_IMX_CONSOLE=y -+CONFIG_SERIAL_FSL_LPUART=y -+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y -+CONFIG_FSL_OTP=y -+CONFIG_GPIO_MXC=y -+# CONFIG_I2C_COMPAT is not set -+CONFIG_I2C_CHARDEV=y -+# CONFIG_I2C_HELPER_AUTO is not set -+CONFIG_I2C_ALGOPCF=m -+CONFIG_I2C_ALGOPCA=m -+CONFIG_I2C_IMX=y -+CONFIG_SPI=y -+CONFIG_SPI_IMX=y -+CONFIG_GPIO_SYSFS=y -+CONFIG_POWER_SUPPLY=y -+CONFIG_THERMAL=y -+CONFIG_CPU_THERMAL=y -+CONFIG_IMX_THERMAL=y -+CONFIG_DEVICE_THERMAL=y -+CONFIG_WATCHDOG=y -+CONFIG_IMX2_WDT=y -+CONFIG_MFD_DA9052_I2C=y -+CONFIG_MFD_MC13XXX_SPI=y -+CONFIG_MFD_MC13XXX_I2C=y -+CONFIG_MFD_SI476X_CORE=y -+CONFIG_REGULATOR=y -+CONFIG_REGULATOR_FIXED_VOLTAGE=y -+CONFIG_REGULATOR_ANATOP=y -+CONFIG_REGULATOR_PFUZE100=y -+CONFIG_MEDIA_SUPPORT=y -+CONFIG_MEDIA_CAMERA_SUPPORT=y -+# CONFIG_MEDIA_RADIO_SUPPORT is not set -+CONFIG_VIDEO_V4L2_INT_DEVICE=y -+# CONFIG_MEDIA_USB_SUPPORT isnot set -+# CONFIG_USB_VIDEO_CLASS is not set -+# CONFIG_RADIO_ADAPTERS is not set -+CONFIG_V4L_PLATFORM_DRIVERS=y -+CONFIG_VIDEO_MXC_OUTPUT=y -+CONFIG_VIDEO_MXC_CAPTURE=m -+CONFIG_VIDEO_MXC_CSI_CAMERA=m -+CONFIG_MXC_CAMERA_OV5640=m -+CONFIG_MXC_CAMERA_OV5642=m -+CONFIG_MXC_CAMERA_OV5640_MIPI=m -+CONFIG_MXC_TVIN_ADV7180=m -+CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m -+CONFIG_VIDEO_MXC_IPU_OUTPUT=y -+CONFIG_VIDEO_MXC_PXP_V4L2=y -+CONFIG_SOC_CAMERA=y -+CONFIG_SOC_CAMERA_OV2640=y -+CONFIG_VIVANTE_GALCORE=y -+CONFIG_DRM=y -+CONFIG_DRM_VIVANTE=y -+CONFIG_FB=y -+# CONFIG_FB_MX3 is not set -+CONFIG_FB_MXC_SYNC_PANEL=y -+CONFIG_FB_MXC_LDB=y -+CONFIG_FB_MXC_HDMI=y -+CONFIG_FRAMEBUFFER_CONSOLE=y -+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -+CONFIG_FONTS=y -+CONFIG_FONT_8x8=y -+CONFIG_FONT_8x16=y -+CONFIG_LOGO=y -+CONFIG_SOUND=y -+CONFIG_SND=y -+CONFIG_SND_USB_AUDIO=m -+CONFIG_SND_SOC=y -+CONFIG_SND_IMX_SOC=y -+CONFIG_SND_SOC_IMX_SGTL5000=y -+CONFIG_SND_SOC_IMX_SPDIF=y -+CONFIG_SND_SOC_IMX_HDMI=y -+CONFIG_USB=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_STORAGE=y -+CONFIG_USB_CHIPIDEA=y -+CONFIG_USB_CHIPIDEA_UDC=y -+CONFIG_USB_CHIPIDEA_HOST=y -+CONFIG_USB_PHY=y -+CONFIG_NOP_USB_XCEIV=y -+CONFIG_USB_MXS_PHY=y -+CONFIG_USB_GADGET=y -+CONFIG_USB_ZERO=m -+CONFIG_USB_ETH=m -+CONFIG_USB_MASS_STORAGE=m -+CONFIG_USB_G_SERIAL=m -+CONFIG_MMC=y -+CONFIG_MMC_UNSAFE_RESUME=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_PLTFM=y -+CONFIG_MMC_SDHCI_ESDHC_IMX=y -+CONFIG_MXC_IPU=y -+# CONFIG_MXC_GPU_VIV is not set -+CONFIG_MXC_ASRC=y -+CONFIG_MXC_HDMI_CEC=y -+CONFIG_MXC_MIPI_CSI2=y -+CONFIG_MXC_MLB150=m -+CONFIG_NEW_LEDS=y -+CONFIG_LEDS_CLASS=y -+CONFIG_LEDS_GPIO=y -+CONFIG_LEDS_TRIGGERS=y -+CONFIG_LEDS_TRIGGER_GPIO=y -+CONFIG_RTC_CLASS=y -+CONFIG_RTC_DRV_MXC=y -+CONFIG_RTC_DRV_SNVS=y -+CONFIG_RTC_DRV_PCF8523=y -+CONFIG_DMADEVICES=y -+CONFIG_MXC_PXP_V2=y -+CONFIG_IMX_SDMA=y -+CONFIG_MXS_DMA=y -+CONFIG_SRAM=y -+CONFIG_STAGING=y -+CONFIG_COMMON_CLK_DEBUG=y -+# CONFIG_IOMMU_SUPPORT is not set -+CONFIG_PWM=y -+CONFIG_PWM_SYSFS=y -+CONFIG_PWM_IMX=y -+CONFIG_IRQCHIP=y -+CONFIG_ARM_GIC=y -+# CONFIG_IPACK_BUS is not set -+CONFIG_ARCH_HAS_RESET_CONTROLLER=y -+CONFIG_RESET_CONTROLLER=y -+CONFIG_RESET_GPIO=y -+CONFIG_EXT4_FS=y -+CONFIG_EXT4_USE_FOR_EXT23=y -+CONFIG_EXT4_FS_XATTR=y -+CONFIG_EXT4_FS_POSIX_ACL=y -+CONFIG_EXT4_FS_SECURITY=y -+CONFIG_QUOTA=y -+CONFIG_QUOTA_NETLINK_INTERFACE=y -+# CONFIG_PRINT_QUOTA_WARNING is not set -+CONFIG_AUTOFS4_FS=y -+CONFIG_FUSE_FS=y -+CONFIG_ISO9660_FS=m -+CONFIG_JOLIET=y -+CONFIG_ZISOFS=y -+CONFIG_UDF_FS=m -+CONFIG_MSDOS_FS=m -+CONFIG_VFAT_FS=y -+CONFIG_TMPFS=y -+CONFIG_JFFS2_FS=y -+CONFIG_UBIFS_FS=y -+CONFIG_NFS_FS=y -+CONFIG_NFS_V3_ACL=y -+CONFIG_NFS_V4=y -+CONFIG_ROOT_NFS=y -+CONFIG_NLS_DEFAULT="cp437" -+CONFIG_NLS_CODEPAGE_437=y -+CONFIG_NLS_ASCII=y -+CONFIG_NLS_ISO8859_1=y -+CONFIG_NLS_ISO8859_15=m -+CONFIG_NLS_UTF8=y -+CONFIG_MAGIC_SYSRQ=y -+# CONFIG_SCHED_DEBUG is not set -+# CONFIG_DEBUG_BUGVERBOSE is not set -+# CONFIG_FTRACE is not set -+CONFIG_SECURITYFS=y -+CONFIG_CRYPTO_USER=y -+CONFIG_CRYPTO_TEST=m -+CONFIG_CRYPTO_CCM=y -+CONFIG_CRYPTO_GCM=y -+CONFIG_CRYPTO_CBC=y -+CONFIG_CRYPTO_CTS=y -+CONFIG_CRYPTO_ECB=y -+CONFIG_CRYPTO_LRW=y -+CONFIG_CRYPTO_XTS=y -+CONFIG_CRYPTO_MD4=y -+CONFIG_CRYPTO_MD5=y -+CONFIG_CRYPTO_MICHAEL_MIC=y -+CONFIG_CRYPTO_RMD128=y -+CONFIG_CRYPTO_RMD160=y -+CONFIG_CRYPTO_RMD256=y -+CONFIG_CRYPTO_RMD320=y -+CONFIG_CRYPTO_SHA1=y -+CONFIG_CRYPTO_SHA256=y -+CONFIG_CRYPTO_SHA512=y -+CONFIG_CRYPTO_TGR192=y -+CONFIG_CRYPTO_WP512=y -+CONFIG_CRYPTO_BLOWFISH=y -+CONFIG_CRYPTO_CAMELLIA=y -+CONFIG_CRYPTO_DES=y -+CONFIG_CRYPTO_TWOFISH=y -+# CONFIG_CRYPTO_ANSI_CPRNG is not set -+CONFIG_CRYPTO_DEV_FSL_CAAM=y -+CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y -+# CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST is not set -+CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y -+CONFIG_CRYPTO_AES_ARM_BS=y -+CONFIG_CRC_CCITT=m -+CONFIG_CRC_T10DIF=y -+CONFIG_CRC7=m -+CONFIG_LIBCRC32C=m -+# CONFIG_MXC_MMA8451 is not set -+CONFIG_RC_CORE=m -+CONFIG_RC_DECODERS=y -+CONFIG_LIRC=m -+CONFIG_RC_LOOPBACK=m -+CONFIG_RC_MAP=m -+CONFIG_RC_DEVICES=y -+CONFIG_RC_ATI_REMOTE=m -+CONFIG_IR_NEC_DECODER=m -+CONFIG_IR_RC5_DECODER=m -+CONFIG_IR_RC6_DECODER=m -+CONFIG_IR_JVC_DECODER=m -+CONFIG_IR_SONY_DECODER=m -+CONFIG_IR_RC5_SZ_DECODER=m -+CONFIG_IR_SANYO_DECODER=m -+CONFIG_IR_MCE_KBD_DECODER=m -+CONFIG_IR_LIRC_CODEC=m -+CONFIG_IR_IMON=m -+CONFIG_IR_MCEUSB=m -+CONFIG_IR_ITE_CIR=m -+CONFIG_IR_NUVOTON=m -+CONFIG_IR_FINTEK=m -+CONFIG_IR_REDRAT3=m -+CONFIG_IR_ENE=m -+CONFIG_IR_STREAMZAP=m -+CONFIG_IR_WINBOND_CIR=m -+CONFIG_IR_IGUANA=m -+CONFIG_IR_TTUSBIR=m -+CONFIG_IR_GPIO_CIR=m -diff -Nur linux-4.1.13.orig/arch/arm/configs/imx_v7_cbi_hb_defconfig linux-4.1.13/arch/arm/configs/imx_v7_cbi_hb_defconfig ---- linux-4.1.13.orig/arch/arm/configs/imx_v7_cbi_hb_defconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/arch/arm/configs/imx_v7_cbi_hb_defconfig 2015-11-30 17:56:13.524141455 +0100 -@@ -0,0 +1,5139 @@ -+# -+# Automatically generated make config: don't edit -+# -+CONFIG_MMU=y -+CONFIG_HOTPLUG_CPU=y -+# CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set -+# CONFIG_DEBUG_HOTPLUG_CPU0 is not set -+CONFIG_LOCALVERSION="" -+CONFIG_CROSS_COMPILE="" -+CONFIG_DEFAULT_HOSTNAME="(none)" -+ -+# -+# Code maturity level options -+# -+CONFIG_EXPERIMENTAL=y -+CONFIG_HOTPLUG=y -+CONFIG_UEVENT_HELPER_PATH="" -+CONFIG_PREVENT_FIRMWARE_BUILD=y -+ -+CONFIG_BUILD_DOCSRC=y -+ -+# -+# General setup -+# -+CONFIG_KERNEL_LZO=y -+# CONFIG_KERNEL_BZIP2 is not set -+# CONFIG_KERNEL_LZMA is not set -+CONFIG_SWAP=y -+CONFIG_BSD_PROCESS_ACCT=y -+CONFIG_BSD_PROCESS_ACCT_V3=y -+# CONFIG_COMPILE_TEST is not set -+CONFIG_TASKSTATS=y -+CONFIG_TASK_DELAY_ACCT=y -+CONFIG_TASK_XACCT=y -+CONFIG_TASK_IO_ACCOUNTING=y -+CONFIG_SYSCTL=y -+# CONFIG_IKCONFIG is not set -+# CONFIG_EMBEDDED is not set -+CONFIG_KALLSYMS=y -+CONFIG_KALLSYMS_ALL=y -+CONFIG_FUTEX=y -+CONFIG_EPOLL=y -+CONFIG_IOSCHED_NOOP=y -+CONFIG_IOSCHED_DEADLINE=y -+CONFIG_IOSCHED_CFQ=y -+CONFIG_CFQ_GROUP_IOSCHED=y -+CONFIG_IOSCHED_BFQ=y -+CONFIG_CGROUP_BFQIO=y -+CONFIG_DEFAULT_BFQ=y -+CONFIG_DEFAULT_IOSCHED="bfq" -+# CONFIG_CHECKPOINT_RESTORE is not set -+CONFIG_NAMESPACES=y -+CONFIG_PID_NS=y -+CONFIG_UTS_NS=y -+CONFIG_IPC_NS=y -+CONFIG_NET_NS=y -+CONFIG_USER_NS=y -+# CONFIG_UIDGID_STRICT_TYPE_CHECKS is not set -+CONFIG_SYSVIPC=y -+CONFIG_FHANDLE=y -+CONFIG_NO_HZ=y -+CONFIG_HIGH_RES_TIMERS=y -+CONFIG_LOG_BUF_SHIFT=18 -+CONFIG_CGROUPS=y -+CONFIG_RELAY=y -+CONFIG_BLK_DEV_INITRD=y -+CONFIG_EXPERT=y -+CONFIG_PERF_EVENTS=y -+# CONFIG_SLUB_DEBUG is not set -+# CONFIG_COMPAT_BRK is not set -+CONFIG_MODULES=y -+CONFIG_MODULE_UNLOAD=y -+CONFIG_MODVERSIONS=y -+CONFIG_MODULE_SRCVERSION_ALL=y -+ -+CONFIG_POSIX_MQUEUE=y -+CONFIG_PREEMPT_VOLUNTARY=y -+ -+CONFIG_SLUB=y -+CONFIG_SLUB_CPU_PARTIAL=y -+# CONFIG_SLUB_STATS is not set -+# CONFIG_SLUB_DEBUG_ON is not set -+ -+# CONFIG_AD525X_DPOT is not set -+# CONFIG_ATMEL_PWM is not set -+# CONFIG_IWMC3200TOP is not set -+# CONFIG_BLK_DEV_BSG is not set -+ -+# MX6 specific kernel configuration -+CONFIG_GPIO_PCA953X=y -+CONFIG_ARCH_MXC=y -+CONFIG_MXC_DEBUG_BOARD=y -+CONFIG_SOC_IMX6Q=y -+# CONFIG_SOC_IMX6SL is not set -+# CONFIG_SOC_IMX6SX is not set -+# CONFIG_SWP_EMULATE is not set -+CONFIG_PCI=y -+CONFIG_PCIE_DW=y -+CONFIG_PCI_IMX6=y -+CONFIG_SMP=y -+CONFIG_VMSPLIT_3G=y -+CONFIG_AEABI=y -+# CONFIG_OABI_COMPAT is not set -+CONFIG_HIGHMEM=y -+CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" -+CONFIG_CPU_FREQ=y -+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -+CONFIG_CPU_FREQ_GOV_POWERSAVE=y -+CONFIG_CPU_FREQ_GOV_USERSPACE=y -+CONFIG_CPU_FREQ_GOV_ONDEMAND=y -+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -+CONFIG_ARM_IMX6_CPUFREQ=y -+CONFIG_CPU_IDLE=y -+CONFIG_VFP=y -+CONFIG_VFPv3=y -+CONFIG_NEON=y -+CONFIG_KERNEL_MODE_NEON=y -+CONFIG_BINFMT_MISC=m -+# CONFIG_PM_DEBUG is not set -+# CONFIG_PM_TEST_SUSPEND is not set -+CONFIG_NET=y -+CONFIG_PACKET=y -+CONFIG_UNIX=y -+CONFIG_INET=y -+CONFIG_IP_PNP=y -+CONFIG_IP_PNP_DHCP=y -+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -+# CONFIG_INET_XFRM_MODE_TUNNEL is not set -+# CONFIG_INET_XFRM_MODE_BEET is not set -+# CONFIG_INET_LRO is not set -+CONFIG_IPV6=y -+CONFIG_NETFILTER=y -+CONFIG_VLAN_8021Q=y -+CONFIG_WIRELESS=y -+CONFIG_WIRELESS_EXT=y -+CONFIG_WEXT_CORE=y -+CONFIG_WEXT_PROC=y -+CONFIG_WEXT_SPY=y -+CONFIG_WEXT_PRIV=y -+CONFIG_CFG80211=y -+CONFIG_ETHERNET=y -+# CONFIG_NET_VENDOR_BROADCOM is not set -+# CONFIG_NET_VENDOR_CIRRUS is not set -+# CONFIG_NET_VENDOR_FARADAY -+# CONFIG_NET_VENDOR_INTEL -+# CONFIG_NET_VENDOR_I825XX -+# CONFIG_NET_VENDOR_MARVELL -+# CONFIG_NET_VENDOR_MICROCHIP -+# CONFIG_NET_VENDOR_MICROCHIP=y -+# CONFIG_ENC28J60 is not set -+# CONFIG_NET_VENDOR_NATSEMI=y -+# CONFIG_NET_VENDOR_8390=y -+# CONFIG_AX88796 is not set -+# CONFIG_ETHOC is not set -+# CONFIG_SH_ETH is not set -+# CONFIG_NET_VENDOR_SEEQ=y -+# CONFIG_NET_VENDOR_SMSC=y -+# CONFIG_SMC91X is not set -+# CONFIG_SMC911X is not set -+# CONFIG_SMSC911X is not set -+# CONFIG_NET_VENDOR_STMICRO=y -+# CONFIG_STMMAC_ETH is not set -+# CONFIG_NET_VENDOR_VIA=y -+# CONFIG_VIA_VELOCITY is not set -+# CONFIG_NET_VENDOR_WIZNET=y -+CONFIG_NET_VENDOR_FREESCALE=y -+CONFIG_FEC=y -+CONFIG_PHYLIB=y -+CONFIG_AT803X_PHY=y -+CONFIG_WLAN=y -+CONFIG_BRCMUTIL=m -+CONFIG_BRCMFMAC=m -+CONFIG_BRCMFMAC_SDIO=y -+CONFIG_DEVTMPFS=y -+CONFIG_DEVTMPFS_MOUNT=y -+# CONFIG_STANDALONE is not set -+CONFIG_DMA_CMA=y -+CONFIG_CMA=y -+CONFIG_CMA_SIZE_MBYTES=256 -+CONFIG_CONNECTOR=y -+# CONFIG_MTD is not set -+CONFIG_BLK_DEV_LOOP=y -+CONFIG_BLK_DEV_RAM=y -+CONFIG_BLK_DEV_RAM_SIZE=65536 -+# CONFIG_SCSI_PROC_FS is not set -+CONFIG_BLK_DEV_SD=y -+CONFIG_SCSI_MULTI_LUN=y -+CONFIG_SCSI_CONSTANTS=y -+CONFIG_SCSI_LOGGING=y -+CONFIG_SCSI_SCAN_ASYNC=y -+# CONFIG_SCSI_LOWLEVEL is not set -+CONFIG_ATA=y -+CONFIG_SATA_AHCI_PLATFORM=y -+CONFIG_AHCI_IMX=y -+CONFIG_NETDEVICES=y -+CONFIG_INPUT_EVDEV=y -+# CONFIG_INPUT_EVBUG is not set -+CONFIG_KEYBOARD_GPIO=y -+CONFIG_KEYBOARD_IMX=y -+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -+# CONFIG_KEYBOARD_ATKBD is not set -+# CONFIG_MOUSE_PS2 is not set -+CONFIG_INPUT_MISC=y -+CONFIG_SERIO_SERPORT=m -+CONFIG_VT_HW_CONSOLE_BINDING=y -+# CONFIG_LEGACY_PTYS is not set -+# CONFIG_DEVKMEM is not set -+CONFIG_SERIAL_IMX=y -+CONFIG_SERIAL_IMX_CONSOLE=y -+CONFIG_SERIAL_FSL_LPUART=y -+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y -+CONFIG_FSL_OTP=y -+CONFIG_GPIO_MXC=y -+# CONFIG_I2C_COMPAT is not set -+CONFIG_I2C_CHARDEV=y -+# CONFIG_I2C_HELPER_AUTO is not set -+CONFIG_I2C_ALGOPCF=m -+CONFIG_I2C_ALGOPCA=m -+CONFIG_I2C_IMX=y -+CONFIG_SPI=y -+CONFIG_SPI_IMX=y -+CONFIG_GPIO_SYSFS=y -+CONFIG_POWER_SUPPLY=y -+CONFIG_THERMAL=y -+CONFIG_CPU_THERMAL=y -+CONFIG_IMX_THERMAL=y -+CONFIG_DEVICE_THERMAL=y -+CONFIG_WATCHDOG=y -+CONFIG_IMX2_WDT=y -+CONFIG_MFD_DA9052_I2C=y -+CONFIG_MFD_MC13XXX_SPI=y -+CONFIG_MFD_MC13XXX_I2C=y -+CONFIG_MFD_SI476X_CORE=y -+CONFIG_REGULATOR=y -+CONFIG_REGULATOR_FIXED_VOLTAGE=y -+CONFIG_REGULATOR_ANATOP=y -+CONFIG_REGULATOR_PFUZE100=y -+CONFIG_MEDIA_SUPPORT=y -+CONFIG_MEDIA_CAMERA_SUPPORT=y -+# CONFIG_MEDIA_RADIO_SUPPORT is not set -+CONFIG_VIDEO_V4L2_INT_DEVICE=y -+CONFIG_MEDIA_USB_SUPPORT=y -+CONFIG_USB_VIDEO_CLASS=m -+# CONFIG_RADIO_ADAPTERS is not set -+CONFIG_V4L_PLATFORM_DRIVERS=y -+CONFIG_VIDEO_MXC_OUTPUT=y -+CONFIG_VIDEO_MXC_CAPTURE=m -+CONFIG_VIDEO_MXC_CSI_CAMERA=m -+CONFIG_MXC_CAMERA_OV5640=m -+CONFIG_MXC_CAMERA_OV5642=m -+CONFIG_MXC_CAMERA_OV5640_MIPI=m -+CONFIG_MXC_TVIN_ADV7180=m -+CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m -+CONFIG_VIDEO_MXC_IPU_OUTPUT=y -+CONFIG_VIDEO_MXC_PXP_V4L2=y -+CONFIG_SOC_CAMERA=y -+CONFIG_SOC_CAMERA_OV2640=y -+CONFIG_VIVANTE_GALCORE=y -+CONFIG_DRM=y -+CONFIG_DRM_VIVANTE=y -+CONFIG_FB=y -+# CONFIG_FB_MX3 is not set -+CONFIG_FB_MXC_SYNC_PANEL=y -+CONFIG_FB_MXC_LDB=y -+CONFIG_FB_MXC_HDMI=y -+CONFIG_FRAMEBUFFER_CONSOLE=y -+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -+CONFIG_FONTS=y -+CONFIG_FONT_8x8=y -+CONFIG_FONT_8x16=y -+CONFIG_LOGO=y -+CONFIG_SOUND=y -+CONFIG_SND=y -+CONFIG_SND_USB_AUDIO=m -+CONFIG_SND_SOC=y -+CONFIG_SND_IMX_SOC=y -+CONFIG_SND_SOC_IMX_SGTL5000=y -+CONFIG_SND_SOC_IMX_SPDIF=y -+CONFIG_SND_SOC_IMX_HDMI=y -+CONFIG_USB=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_STORAGE=y -+CONFIG_USB_CHIPIDEA=y -+CONFIG_USB_CHIPIDEA_UDC=y -+CONFIG_USB_CHIPIDEA_HOST=y -+CONFIG_USB_PHY=y -+CONFIG_NOP_USB_XCEIV=y -+CONFIG_USB_MXS_PHY=y -+CONFIG_USB_GADGET=y -+CONFIG_USB_ZERO=m -+CONFIG_USB_ETH=m -+CONFIG_USB_MASS_STORAGE=m -+CONFIG_USB_G_SERIAL=m -+CONFIG_MMC=y -+CONFIG_MMC_UNSAFE_RESUME=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_PLTFM=y -+CONFIG_MMC_SDHCI_ESDHC_IMX=y -+CONFIG_MXC_IPU=y -+# CONFIG_MXC_GPU_VIV is not set -+CONFIG_MXC_ASRC=y -+CONFIG_MXC_HDMI_CEC=y -+CONFIG_MXC_MIPI_CSI2=y -+CONFIG_MXC_MLB150=m -+CONFIG_NEW_LEDS=y -+CONFIG_LEDS_CLASS=y -+CONFIG_LEDS_GPIO=y -+CONFIG_LEDS_TRIGGERS=y -+CONFIG_LEDS_TRIGGER_GPIO=y -+CONFIG_RTC_CLASS=y -+CONFIG_RTC_DRV_MXC=y -+CONFIG_RTC_DRV_SNVS=y -+CONFIG_RTC_DRV_PCF8523=y -+CONFIG_DMADEVICES=y -+CONFIG_MXC_PXP_V2=y -+CONFIG_IMX_SDMA=y -+CONFIG_MXS_DMA=y -+CONFIG_SRAM=y -+CONFIG_STAGING=y -+CONFIG_COMMON_CLK_DEBUG=y -+# CONFIG_IOMMU_SUPPORT is not set -+CONFIG_PWM=y -+CONFIG_PWM_SYSFS=y -+CONFIG_PWM_IMX=y -+CONFIG_IRQCHIP=y -+CONFIG_ARM_GIC=y -+CONFIG_ARCH_HAS_RESET_CONTROLLER=y -+CONFIG_RESET_CONTROLLER=y -+CONFIG_RESET_GPIO=y -+CONFIG_EXT4_FS=y -+CONFIG_EXT4_USE_FOR_EXT23=y -+CONFIG_EXT4_FS_XATTR=y -+CONFIG_EXT4_FS_POSIX_ACL=y -+CONFIG_EXT4_FS_SECURITY=y -+CONFIG_QUOTA=y -+CONFIG_QUOTA_NETLINK_INTERFACE=y -+# CONFIG_PRINT_QUOTA_WARNING is not set -+CONFIG_AUTOFS4_FS=y -+CONFIG_FUSE_FS=y -+CONFIG_ISO9660_FS=m -+CONFIG_JOLIET=y -+CONFIG_ZISOFS=y -+CONFIG_UDF_FS=m -+CONFIG_MSDOS_FS=m -+CONFIG_VFAT_FS=y -+CONFIG_TMPFS=y -+CONFIG_JFFS2_FS=y -+CONFIG_UBIFS_FS=y -+CONFIG_NFS_FS=y -+CONFIG_NFS_V3_ACL=y -+CONFIG_NFS_V4=y -+CONFIG_ROOT_NFS=y -+CONFIG_NLS_DEFAULT="cp437" -+CONFIG_NLS_CODEPAGE_437=y -+CONFIG_NLS_ASCII=y -+CONFIG_NLS_ISO8859_1=y -+CONFIG_NLS_ISO8859_15=m -+CONFIG_NLS_UTF8=y -+CONFIG_MAGIC_SYSRQ=y -+# CONFIG_SCHED_DEBUG is not set -+# CONFIG_DEBUG_BUGVERBOSE is not set -+# CONFIG_FTRACE is not set -+CONFIG_SECURITYFS=y -+CONFIG_CRYPTO_USER=y -+CONFIG_CRYPTO_TEST=m -+CONFIG_CRYPTO_CCM=y -+CONFIG_CRYPTO_GCM=y -+CONFIG_CRYPTO_CBC=y -+CONFIG_CRYPTO_CTS=y -+CONFIG_CRYPTO_ECB=y -+CONFIG_CRYPTO_LRW=y -+CONFIG_CRYPTO_XTS=y -+CONFIG_CRYPTO_MD4=y -+CONFIG_CRYPTO_MD5=y -+CONFIG_CRYPTO_MICHAEL_MIC=y -+CONFIG_CRYPTO_RMD128=y -+CONFIG_CRYPTO_RMD160=y -+CONFIG_CRYPTO_RMD256=y -+CONFIG_CRYPTO_RMD320=y -+CONFIG_CRYPTO_SHA1=y -+CONFIG_CRYPTO_SHA256=y -+CONFIG_CRYPTO_SHA512=y -+CONFIG_CRYPTO_TGR192=y -+CONFIG_CRYPTO_WP512=y -+CONFIG_CRYPTO_BLOWFISH=y -+CONFIG_CRYPTO_CAMELLIA=y -+CONFIG_CRYPTO_DES=y -+CONFIG_CRYPTO_TWOFISH=y -+# CONFIG_CRYPTO_ANSI_CPRNG is not set -+CONFIG_CRYPTO_DEV_FSL_CAAM=y -+CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y -+# CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST is not set -+CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y -+CONFIG_CRYPTO_AES_ARM_BS=y -+CONFIG_CRC_CCITT=m -+CONFIG_CRC_T10DIF=y -+CONFIG_CRC7=m -+CONFIG_LIBCRC32C=m -+# CONFIG_MXC_MMA8451 is not set -+ -+# -+# Loadable module support -+# -+# CONFIG_MODULE_FORCE_LOAD is not set -+# -- MODULE_FORCE_UNLOAD is controlled by config-debug/nodebug -+ -+# CONFIG_PCI_DEBUG is not set -+CONFIG_PCI_STUB=y -+CONFIG_PCI_IOV=y -+CONFIG_PCI_PRI=y -+CONFIG_PCI_PASID=y -+CONFIG_HT_IRQ=y -+CONFIG_PCI_MSI=y -+# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set -+CONFIG_PCIEPORTBUS=y -+CONFIG_PCIEAER=y -+CONFIG_PCIEASPM=y -+# CONFIG_PCIEASPM_DEBUG is not set -+CONFIG_PCIE_ECRC=y -+CONFIG_PCIEAER_INJECT=m -+CONFIG_HOTPLUG_PCI_PCIE=y -+CONFIG_HOTPLUG_PCI_FAKE=m -+ -+# CONFIG_SGI_IOC4 is not set -+ -+# CONFIG_ISA is not set -+# CONFIG_SCx200 is not set -+ -+# -+# PCMCIA/CardBus support -+# FIXME: Deprecate Cardbus ? -+# -+CONFIG_PCMCIA=y -+CONFIG_PCMCIA_LOAD_CIS=y -+# CONFIG_PCMCIA_DEBUG is not set -+CONFIG_YENTA=m -+CONFIG_CARDBUS=y -+CONFIG_I82092=m -+CONFIG_PD6729=m -+ -+CONFIG_PCCARD=y -+CONFIG_SDIO_UART=m -+# CONFIG_MMC_TEST is not set -+# CONFIG_MMC_DEBUG is not set -+# https://lists.fedoraproject.org/pipermail/kernel/2014-February/004889.html -+# CONFIG_MMC_CLKGATE is not set -+CONFIG_MMC_BLOCK=y -+CONFIG_MMC_BLOCK_MINORS=8 -+CONFIG_MMC_BLOCK_BOUNCE=y -+CONFIG_MMC_SDHCI_PCI=m -+CONFIG_MMC_SDHCI_ACPI=m -+CONFIG_MMC_SDRICOH_CS=m -+CONFIG_MMC_TIFM_SD=m -+CONFIG_MMC_WBSD=m -+CONFIG_MMC_VIA_SDMMC=m -+CONFIG_MMC_CB710=m -+CONFIG_MMC_RICOH_MMC=y -+CONFIG_MMC_USHC=m -+CONFIG_MMC_REALTEK_PCI=m -+CONFIG_MMC_VUB300=m -+# CONFIG_MMC_SDHCI_PXAV2 is not set -+# CONFIG_MMC_SDHCI_PXAV3 is not set -+# CONFIG_MMC_SDHCI_OF_ARASAN is not set -+ -+ -+CONFIG_CB710_CORE=m -+# CONFIG_CB710_DEBUG is not set -+ -+CONFIG_INFINIBAND=m -+CONFIG_INFINIBAND_MTHCA=m -+# CONFIG_INFINIBAND_MTHCA_DEBUG is not set -+CONFIG_INFINIBAND_IPOIB=m -+CONFIG_INFINIBAND_IPOIB_DEBUG=y -+CONFIG_INFINIBAND_IPOIB_DEBUG_DATA=y -+CONFIG_INFINIBAND_IPOIB_CM=y -+CONFIG_INFINIBAND_SRP=m -+CONFIG_INFINIBAND_SRPT=m -+CONFIG_INFINIBAND_USER_MAD=m -+CONFIG_INFINIBAND_USER_ACCESS=m -+# CONFIG_INFINIBAND_EXPERIMENTAL_UVERBS_FLOW_STEERING is not set #staging -+CONFIG_INFINIBAND_IPATH=m -+CONFIG_INFINIBAND_ISER=m -+CONFIG_INFINIBAND_ISERT=m -+CONFIG_INFINIBAND_AMSO1100=m -+# CONFIG_INFINIBAND_AMSO1100_DEBUG is not set -+CONFIG_INFINIBAND_CXGB3=m -+CONFIG_INFINIBAND_CXGB4=m -+CONFIG_SCSI_CXGB3_ISCSI=m -+CONFIG_SCSI_CXGB4_ISCSI=m -+# CONFIG_INFINIBAND_CXGB3_DEBUG is not set -+CONFIG_MLX4_INFINIBAND=m -+CONFIG_MLX5_INFINIBAND=m -+CONFIG_INFINIBAND_NES=m -+# CONFIG_INFINIBAND_NES_DEBUG is not set -+CONFIG_INFINIBAND_QIB=m -+CONFIG_INFINIBAND_QIB_DCA=y -+# CONFIG_INFINIBAND_OCRDMA is not set -+# CONFIG_INFINIBAND_USNIC is not set -+ -+# -+# Executable file formats -+# -+CONFIG_BINFMT_ELF=y -+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y -+# CONFIG_BINFMT_AOUT is not set -+CONFIG_BINFMT_SCRIPT=y -+ -+# -+# Device Drivers -+# -+ -+# CONFIG_COMMON_CLK_SI5351 is not set -+ -+# -+# Generic Driver Options -+# -+CONFIG_FW_LOADER=y -+# CONFIG_FIRMWARE_IN_KERNEL is not set -+CONFIG_EXTRA_FIRMWARE="" -+ -+# Give this a try in rawhide for now -+# CONFIG_FW_LOADER_USER_HELPER is not set -+ -+ -+ -+# -+# Memory Technology Devices (MTD) -+# -+# CONFIG_MTD_TESTS is not set -+# CONFIG_MTD_REDBOOT_PARTS is not set -+# CONFIG_MTD_AR7_PARTS is not set -+# CONFIG_MTD_CMDLINE_PARTS is not set -+ -+# -+# User Modules And Translation Layers -+# -+# CONFIG_MTD_CHAR is not set -+# CONFIG_MTD_BLKDEVS is not set -+# CONFIG_MTD_BLOCK is not set -+# CONFIG_MTD_BLOCK_RO is not set -+# CONFIG_FTL is not set -+# CONFIG_NFTL is not set -+# CONFIG_INFTL is not set -+# CONFIG_RFD_FTL is not set -+# CONFIG_SSFDC is not set -+# CONFIG_SM_FTL is not set -+# CONFIG_MTD_OOPS is not set -+# CONFIG_MTD_SWAP is not set -+ -+# -+# RAM/ROM/Flash chip drivers -+# -+# CONFIG_MTD_CFI is not set -+# CONFIG_MTD_JEDECPROBE is not set -+CONFIG_MTD_MAP_BANK_WIDTH_1=y -+CONFIG_MTD_MAP_BANK_WIDTH_2=y -+CONFIG_MTD_MAP_BANK_WIDTH_4=y -+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -+CONFIG_MTD_CFI_I1=y -+CONFIG_MTD_CFI_I2=y -+# CONFIG_MTD_CFI_I4 is not set -+# CONFIG_MTD_CFI_I8 is not set -+# CONFIG_MTD_RAM is not set -+# CONFIG_MTD_ROM is not set -+# CONFIG_MTD_ABSENT is not set -+ -+# -+# Mapping drivers for chip access -+# -+# CONFIG_MTD_COMPLEX_MAPPINGS is not set -+# CONFIG_MTD_TS5500 is not set -+# CONFIG_MTD_INTEL_VR_NOR is not set -+# CONFIG_MTD_PLATRAM is not set -+ -+# Self-contained MTD device drivers -+# CONFIG_MTD_PMC551 is not set -+# CONFIG_MTD_SLRAM is not set -+# CONFIG_MTD_PHRAM is not set -+# CONFIG_MTD_MTDRAM is not set -+# CONFIG_MTD_BLOCK2MTD is not set -+ -+# -+# Disk-On-Chip Device Drivers -+# -+# CONFIG_MTD_DOCG3 is not set -+# CONFIG_MTD_NAND is not set -+# CONFIG_MTD_ONENAND is not set -+# CONFIG_MTD_NAND_VERIFY_WRITE is not set -+# CONFIG_MTD_NAND_ECC_BCH is not set -+# CONFIG_MTD_NAND_MUSEUM_IDS is not set -+# CONFIG_MTD_NAND_DISKONCHIP is not set -+# CONFIG_MTD_LPDDR is not set -+CONFIG_MTD_UBI=m -+CONFIG_MTD_UBI_WL_THRESHOLD=4096 -+CONFIG_MTD_UBI_BEB_LIMIT=20 -+# CONFIG_MTD_UBI_FASTMAP is not set -+# CONFIG_MTD_UBI_GLUEBI is not set -+ -+# -+# Parallel port support -+# -+CONFIG_PARPORT=m -+CONFIG_PARPORT_PC=m -+CONFIG_PARPORT_SERIAL=m -+# CONFIG_PARPORT_PC_FIFO is not set -+# CONFIG_PARPORT_PC_SUPERIO is not set -+CONFIG_PARPORT_PC_PCMCIA=m -+CONFIG_PARPORT_1284=y -+# CONFIG_PARPORT_AX88796 is not set -+ -+CONFIG_ACPI_PCI_SLOT=y -+CONFIG_HOTPLUG_PCI_ACPI=y -+CONFIG_HOTPLUG_PCI_ACPI_IBM=m -+ -+# -+# Block devices -+# -+CONFIG_BLK_DEV=y -+CONFIG_BLK_DEV_NULL_BLK=m -+CONFIG_BLK_DEV_FD=m -+# CONFIG_PARIDE is not set -+CONFIG_ZRAM=m -+# CONFIG_ZRAM_DEBUG is not set -+CONFIG_ENHANCEIO=m -+ -+CONFIG_BLK_CPQ_DA=m -+CONFIG_BLK_CPQ_CISS_DA=m -+CONFIG_CISS_SCSI_TAPE=y -+CONFIG_BLK_DEV_DAC960=m -+# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set -+CONFIG_BLK_DEV_DRBD=m -+CONFIG_BLK_DEV_UMEM=m -+CONFIG_BLK_DEV_LOOP_MIN_COUNT=0 -+# Fedora 18 util-linux is the last release that supports cryptoloop devices -+# CONFIG_BLK_DEV_CRYPTOLOOP is not set -+CONFIG_BLK_DEV_NBD=m -+CONFIG_BLK_DEV_NVME=m -+CONFIG_BLK_DEV_SKD=m # 64-bit only but easier to put here -+CONFIG_BLK_DEV_OSD=m -+CONFIG_BLK_DEV_RAM_COUNT=16 -+CONFIG_BLK_DEV_IO_TRACE=y -+ -+CONFIG_BLK_DEV_BSGLIB=y -+CONFIG_BLK_DEV_INTEGRITY=y -+CONFIG_BLK_DEV_THROTTLING=y -+# CONFIG_BLK_CMDLINE_PARSER is not set -+ -+ -+# -+# ATA/ATAPI/MFM/RLL support -+# -+# CONFIG_IDE is not set -+ -+# CONFIG_BLK_DEV_HD is not set -+# CONFIG_BLK_DEV_RSXX is not set -+ -+CONFIG_SCSI_VIRTIO=m -+CONFIG_VIRTIO_BLK=m -+CONFIG_VIRTIO_PCI=m -+CONFIG_VIRTIO_BALLOON=m -+CONFIG_VIRTIO_MMIO=m -+# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set -+CONFIG_VIRTIO_NET=m -+CONFIG_HW_RANDOM_VIRTIO=m -+CONFIG_VIRTIO_CONSOLE=m -+CONFIG_VHOST_NET=m -+CONFIG_TCM_VHOST=m -+CONFIG_VHOST_SCSI=m -+ -+# -+# SCSI device support -+# -+CONFIG_SCSI=y -+ -+CONFIG_SCSI_ENCLOSURE=m -+CONFIG_SCSI_SRP=m -+CONFIG_SCSI_SRP_ATTRS=m -+CONFIG_SCSI_TGT=m -+CONFIG_SCSI_ISCI=m -+CONFIG_SCSI_CHELSIO_FCOE=m -+ -+CONFIG_SCSI_DH=y -+CONFIG_SCSI_DH_RDAC=m -+CONFIG_SCSI_DH_HP_SW=m -+CONFIG_SCSI_DH_EMC=m -+CONFIG_SCSI_DH_ALUA=m -+ -+# -+# SCSI support type (disk, tape, CD-ROM) -+# -+CONFIG_CHR_DEV_ST=m -+CONFIG_CHR_DEV_OSST=m -+CONFIG_BLK_DEV_SR=y -+CONFIG_BLK_DEV_SR_VENDOR=y -+CONFIG_CHR_DEV_SG=y -+CONFIG_CHR_DEV_SCH=m -+ -+# -+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -+# -+CONFIG_SCSI_SPI_ATTRS=m -+CONFIG_SCSI_FC_ATTRS=m -+CONFIG_SCSI_FC_TGT_ATTRS=y -+CONFIG_SCSI_ISCSI_ATTRS=m -+CONFIG_SCSI_SAS_ATTRS=m -+CONFIG_SCSI_SRP_TGT_ATTRS=y -+CONFIG_SCSI_SAS_LIBSAS=m -+CONFIG_SCSI_SAS_ATA=y -+CONFIG_SCSI_SAS_HOST_SMP=y -+CONFIG_RAID_ATTRS=m -+ -+CONFIG_ISCSI_TCP=m -+CONFIG_ISCSI_BOOT_SYSFS=m -+ -+# -+# SCSI low-level drivers -+# -+CONFIG_BLK_DEV_3W_XXXX_RAID=m -+CONFIG_SCSI_3W_9XXX=m -+CONFIG_SCSI_ACARD=m -+CONFIG_SCSI_AACRAID=m -+CONFIG_SCSI_AIC7XXX=m -+# http://lists.fedoraproject.org/pipermail/kernel/2013-February/004102.html -+# CONFIG_SCSI_AIC7XXX_OLD is not set -+CONFIG_AIC7XXX_CMDS_PER_DEVICE=4 -+CONFIG_AIC7XXX_RESET_DELAY_MS=15000 -+# CONFIG_AIC7XXX_BUILD_FIRMWARE is not set -+# CONFIG_AIC7XXX_DEBUG_ENABLE is not set -+CONFIG_AIC7XXX_DEBUG_MASK=0 -+# CONFIG_AIC7XXX_REG_PRETTY_PRINT is not set -+CONFIG_SCSI_AIC79XX=m -+CONFIG_AIC79XX_CMDS_PER_DEVICE=4 -+CONFIG_AIC79XX_RESET_DELAY_MS=15000 -+# CONFIG_AIC79XX_BUILD_FIRMWARE is not set -+# CONFIG_AIC79XX_DEBUG_ENABLE is not set -+CONFIG_AIC79XX_DEBUG_MASK=0 -+# CONFIG_AIC79XX_REG_PRETTY_PRINT is not set -+CONFIG_SCSI_AIC94XX=m -+# CONFIG_AIC94XX_DEBUG is not set -+# CONFIG_SCSI_ADVANSYS is not set -+CONFIG_SCSI_BFA_FC=m -+CONFIG_MEGARAID_NEWGEN=y -+CONFIG_MEGARAID_MM=m -+CONFIG_MEGARAID_MAILBOX=m -+CONFIG_MEGARAID_LEGACY=m -+CONFIG_MEGARAID_SAS=m -+CONFIG_SCSI_ESAS2R=m -+CONFIG_SCSI_MVSAS=m -+# CONFIG_SCSI_MVSAS_DEBUG is not set -+CONFIG_SCSI_MVSAS_TASKLET=y -+CONFIG_SCSI_MPT2SAS=m -+CONFIG_SCSI_MPT2SAS_MAX_SGE=128 -+CONFIG_SCSI_MPT2SAS_LOGGING=y -+CONFIG_SCSI_MPT3SAS=m -+CONFIG_SCSI_MPT3SAS_MAX_SGE=128 -+CONFIG_SCSI_MPT3SAS_LOGGING=y -+ -+CONFIG_SCSI_UFSHCD=m -+CONFIG_SCSI_UFSHCD_PCI=m -+# CONFIG_SCSI_UFSHCD_PLATFORM is not set -+ -+CONFIG_SCSI_MVUMI=m -+ -+CONFIG_SCSI_OSD_INITIATOR=m -+CONFIG_SCSI_OSD_ULD=m -+CONFIG_SCSI_OSD_DPRINT_SENSE=1 -+# CONFIG_SCSI_OSD_DEBUG is not set -+ -+CONFIG_SCSI_BNX2_ISCSI=m -+CONFIG_SCSI_BNX2X_FCOE=m -+CONFIG_BE2ISCSI=m -+CONFIG_SCSI_PMCRAID=m -+ -+CONFIG_SCSI_HPSA=m -+CONFIG_SCSI_3W_SAS=m -+CONFIG_SCSI_PM8001=m -+CONFIG_VMWARE_PVSCSI=m -+CONFIG_VMWARE_BALLOON=m -+ -+CONFIG_SCSI_ARCMSR=m -+CONFIG_SCSI_BUSLOGIC=m -+CONFIG_SCSI_INITIO=m -+CONFIG_SCSI_FLASHPOINT=y -+CONFIG_SCSI_DMX3191D=m -+# CONFIG_SCSI_EATA is not set -+# CONFIG_SCSI_EATA_PIO is not set -+# CONFIG_SCSI_FUTURE_DOMAIN is not set -+CONFIG_SCSI_GDTH=m -+CONFIG_SCSI_HPTIOP=m -+CONFIG_SCSI_IPS=m -+CONFIG_SCSI_INIA100=m -+# CONFIG_SCSI_PPA is not set -+# CONFIG_SCSI_IMM is not set -+# CONFIG_SCSI_IZIP_EPP16 is not set -+# CONFIG_SCSI_IZIP_SLOW_CTR is not set -+CONFIG_SCSI_STEX=m -+CONFIG_SCSI_SYM53C8XX_2=m -+CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1 -+CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 -+CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 -+CONFIG_SCSI_SYM53C8XX_MMIO=y -+CONFIG_SCSI_QLOGIC_1280=m -+CONFIG_SCSI_DC395x=m -+# CONFIG_SCSI_NSP32 is not set -+CONFIG_SCSI_DEBUG=m -+CONFIG_SCSI_DC390T=m -+CONFIG_SCSI_QLA_FC=m -+CONFIG_TCM_QLA2XXX=m -+CONFIG_SCSI_QLA_ISCSI=m -+CONFIG_SCSI_IPR=m -+CONFIG_SCSI_IPR_TRACE=y -+CONFIG_SCSI_IPR_DUMP=y -+# CONFIG_SCSI_DPT_I2O is not set -+CONFIG_SCSI_LPFC=m -+# CONFIG_SCSI_LPFC_DEBUG_FS is not set -+ -+# PCMCIA SCSI adapter support -+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set -+ -+CONFIG_ATA_BMDMA=y -+CONFIG_ATA_VERBOSE_ERROR=y -+CONFIG_ATA_SFF=y -+CONFIG_ATA_PIIX=y -+# CONFIG_SATA_HIGHBANK is not set -+CONFIG_ATA_ACPI=y -+CONFIG_BLK_DEV_SX8=m -+CONFIG_PDC_ADMA=m -+CONFIG_SATA_AHCI=y -+CONFIG_SATA_INIC162X=m -+CONFIG_SATA_MV=m -+CONFIG_SATA_NV=m -+CONFIG_SATA_PMP=y -+CONFIG_SATA_PROMISE=m -+CONFIG_SATA_QSTOR=m -+CONFIG_SATA_RCAR=m -+CONFIG_SATA_SIL=m -+CONFIG_SATA_SIL24=m -+CONFIG_SATA_SIS=m -+CONFIG_SATA_SVW=m -+CONFIG_SATA_SX4=m -+CONFIG_SATA_ULI=m -+CONFIG_SATA_VIA=m -+CONFIG_SATA_VITESSE=m -+# CONFIG_SATA_ZPODD is not set -+CONFIG_SATA_ACARD_AHCI=m -+ -+# CONFIG_PATA_LEGACY is not set -+CONFIG_PATA_ACPI=m -+CONFIG_PATA_ALI=m -+CONFIG_PATA_AMD=m -+CONFIG_PATA_ARASAN_CF=m -+CONFIG_PATA_ARTOP=m -+CONFIG_PATA_ATIIXP=m -+CONFIG_PATA_CMD640_PCI=m -+CONFIG_PATA_CMD64X=m -+CONFIG_PATA_CS5520=m -+CONFIG_PATA_CS5530=m -+CONFIG_PATA_CS5535=m -+CONFIG_PATA_CS5536=m -+CONFIG_PATA_CYPRESS=m -+CONFIG_PATA_EFAR=m -+CONFIG_ATA_GENERIC=m -+CONFIG_PATA_HPT366=m -+CONFIG_PATA_HPT37X=m -+CONFIG_PATA_HPT3X2N=m -+CONFIG_PATA_HPT3X3=m -+# CONFIG_PATA_HPT3X3_DMA is not set -+CONFIG_PATA_IT821X=m -+CONFIG_PATA_IT8213=m -+CONFIG_PATA_JMICRON=m -+CONFIG_PATA_NINJA32=m -+CONFIG_PATA_MARVELL=m -+CONFIG_PATA_MPIIX=m -+CONFIG_PATA_NETCELL=m -+CONFIG_PATA_NS87410=m -+CONFIG_PATA_NS87415=m -+CONFIG_PATA_OLDPIIX=m -+CONFIG_PATA_OPTI=m -+CONFIG_PATA_OPTIDMA=m -+CONFIG_PATA_PCMCIA=m -+CONFIG_PATA_PDC_OLD=m -+# CONFIG_PATA_RADISYS is not set -+CONFIG_PATA_RDC=m -+# CONFIG_PATA_RZ1000 is not set -+# CONFIG_PATA_SC1200 is not set -+CONFIG_PATA_SERVERWORKS=m -+CONFIG_PATA_PDC2027X=m -+CONFIG_PATA_SCH=m -+CONFIG_PATA_SIL680=m -+CONFIG_PATA_SIS=m -+CONFIG_PATA_TOSHIBA=m -+CONFIG_PATA_TRIFLEX=m -+CONFIG_PATA_VIA=m -+CONFIG_PATA_WINBOND=m -+CONFIG_PATA_ATP867X=m -+ -+ -+# -+# Multi-device support (RAID and LVM) -+# -+CONFIG_MD=y -+CONFIG_BLK_DEV_MD=y -+CONFIG_MD_AUTODETECT=y -+CONFIG_MD_FAULTY=m -+CONFIG_MD_LINEAR=m -+CONFIG_MD_MULTIPATH=m -+CONFIG_MD_RAID0=m -+CONFIG_MD_RAID1=m -+CONFIG_MD_RAID10=m -+CONFIG_MD_RAID456=m -+ -+CONFIG_BCACHE=m -+# CONFIG_BCACHE_DEBUG is not set -+# CONFIG_BCACHE_EDEBUG is not set -+# CONFIG_BCACHE_CLOSURES_DEBUG is not set -+ -+# CONFIG_MULTICORE_RAID456 is not set -+CONFIG_ASYNC_RAID6_TEST=m -+CONFIG_BLK_DEV_DM=y -+CONFIG_DM_CRYPT=m -+CONFIG_DM_DEBUG=y -+CONFIG_DM_DELAY=m -+CONFIG_DM_MIRROR=y -+CONFIG_DM_MULTIPATH=m -+CONFIG_DM_SNAPSHOT=y -+CONFIG_DM_THIN_PROVISIONING=m -+CONFIG_DM_CACHE=m -+CONFIG_DM_CACHE_MQ=m -+CONFIG_DM_CACHE_CLEANER=m -+# CONFIG_DM_DEBUG_BLOCK_STACK_TRACING is not set -+# CONFIG_DM_DEBUG_SPACE_MAPS is not set -+CONFIG_DM_UEVENT=y -+CONFIG_DM_ZERO=y -+CONFIG_DM_LOG_USERSPACE=m -+CONFIG_DM_MULTIPATH_QL=m -+CONFIG_DM_MULTIPATH_ST=m -+CONFIG_DM_RAID=m -+CONFIG_DM_FLAKEY=m -+CONFIG_DM_VERITY=m -+CONFIG_DM_SWITCH=m -+ -+# -+# Fusion MPT device support -+# -+CONFIG_FUSION=y -+CONFIG_FUSION_SPI=m -+CONFIG_FUSION_FC=m -+CONFIG_FUSION_MAX_SGE=40 -+CONFIG_FUSION_CTL=m -+CONFIG_FUSION_LAN=m -+CONFIG_FUSION_SAS=m -+CONFIG_FUSION_LOGGING=y -+ -+# -+# IEEE 1394 (FireWire) support (JUJU alternative stack) -+# -+CONFIG_FIREWIRE=m -+CONFIG_FIREWIRE_OHCI=m -+CONFIG_FIREWIRE_SBP2=m -+CONFIG_FIREWIRE_NET=m -+CONFIG_FIREWIRE_OHCI_DEBUG=y -+CONFIG_FIREWIRE_NOSY=m -+# CONFIG_FIREWIRE_SERIAL is not set -+# CONFIG_FIREWIRE_OHCI_REMOTE_DMA is not set -+ -+# -+# IEEE 1394 (FireWire) support -+# -+ -+# -+# I2O device support -+# -+# CONFIG_I2O is not set -+# CONFIG_I2O_LCT_NOTIFY_ON_CHANGES is not set -+ -+# -+# Virtualization support drivers -+# -+# CONFIG_VIRT_DRIVERS is not set -+ -+# Networking support -+# -+ -+CONFIG_NET_DMA=y -+ -+CONFIG_NETLINK_MMAP=y -+CONFIG_NETLINK_DIAG=m -+ -+CONFIG_TCP_CONG_ADVANCED=y -+CONFIG_TCP_CONG_BIC=m -+CONFIG_TCP_CONG_CUBIC=y -+CONFIG_TCP_CONG_HTCP=m -+CONFIG_TCP_CONG_HSTCP=m -+CONFIG_TCP_CONG_HYBLA=m -+CONFIG_TCP_CONG_ILLINOIS=m -+CONFIG_TCP_CONG_LP=m -+CONFIG_TCP_CONG_SCALABLE=m -+CONFIG_TCP_CONG_VEGAS=m -+CONFIG_TCP_CONG_VENO=m -+CONFIG_TCP_CONG_WESTWOOD=m -+CONFIG_TCP_CONG_YEAH=m -+ -+CONFIG_TCP_MD5SIG=y -+ -+# -+# Networking options -+# -+CONFIG_PACKET_DIAG=m -+CONFIG_UNIX_DIAG=m -+CONFIG_NET_KEY=m -+CONFIG_NET_KEY_MIGRATE=y -+CONFIG_INET_TUNNEL=m -+CONFIG_INET_DIAG=m -+CONFIG_INET_UDP_DIAG=m -+CONFIG_IP_MULTICAST=y -+CONFIG_IP_ADVANCED_ROUTER=y -+CONFIG_IP_FIB_TRIE_STATS=y -+CONFIG_IP_MULTIPLE_TABLES=y -+CONFIG_IP_ROUTE_MULTIPATH=y -+CONFIG_IP_ROUTE_VERBOSE=y -+CONFIG_IP_NF_SECURITY=m -+CONFIG_NET_IPIP=m -+CONFIG_NET_IPGRE_DEMUX=m -+CONFIG_NET_IPGRE=m -+CONFIG_NET_IPGRE_BROADCAST=y -+CONFIG_IP_MROUTE=y -+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y -+CONFIG_IP_PIMSM_V1=y -+CONFIG_IP_PIMSM_V2=y -+CONFIG_ARPD=y -+CONFIG_SYN_COOKIES=y -+CONFIG_NET_IPVTI=m -+CONFIG_INET_AH=m -+CONFIG_INET_ESP=m -+CONFIG_INET_IPCOMP=m -+CONFIG_NETCONSOLE=m -+CONFIG_NETCONSOLE_DYNAMIC=y -+CONFIG_NETPOLL_TRAP=y -+CONFIG_NET_POLL_CONTROLLER=y -+ -+# -+# IP: Virtual Server Configuration -+# -+CONFIG_IP_VS=m -+# CONFIG_IP_VS_DEBUG is not set -+CONFIG_IP_VS_TAB_BITS=12 -+CONFIG_IP_VS_PROTO_TCP=y -+CONFIG_IP_VS_PROTO_UDP=y -+CONFIG_IP_VS_PROTO_ESP=y -+CONFIG_IP_VS_PROTO_AH=y -+CONFIG_IP_VS_PROTO_SCTP=y -+CONFIG_IP_VS_IPV6=y -+CONFIG_IP_VS_RR=m -+CONFIG_IP_VS_WRR=m -+CONFIG_IP_VS_LC=m -+CONFIG_IP_VS_WLC=m -+CONFIG_IP_VS_LBLC=m -+CONFIG_IP_VS_LBLCR=m -+CONFIG_IP_VS_DH=m -+CONFIG_IP_VS_SH=m -+CONFIG_IP_VS_SED=m -+CONFIG_IP_VS_NQ=m -+ -+# -+# IPVS SH scheduler -+# -+CONFIG_IP_VS_SH_TAB_BITS=8 -+ -+CONFIG_IP_VS_FTP=m -+CONFIG_IP_VS_PE_SIP=m -+ -+CONFIG_IPV6_PRIVACY=y -+CONFIG_IPV6_ROUTER_PREF=y -+CONFIG_IPV6_ROUTE_INFO=y -+CONFIG_IPV6_OPTIMISTIC_DAD=y -+CONFIG_INET6_AH=m -+CONFIG_INET6_ESP=m -+CONFIG_INET6_IPCOMP=m -+CONFIG_IPV6_MIP6=y -+CONFIG_IPV6_VTI=m -+CONFIG_IPV6_SIT=m -+CONFIG_IPV6_SIT_6RD=y -+CONFIG_IPV6_TUNNEL=m -+# CONFIG_IPV6_GRE is not set -+CONFIG_IPV6_SUBTREES=y -+CONFIG_IPV6_MULTIPLE_TABLES=y -+CONFIG_IPV6_MROUTE=y -+CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y -+CONFIG_IPV6_PIMSM_V2=y -+ -+CONFIG_RDS=m -+# CONFIG_RDS_DEBUG is not set -+CONFIG_RDS_RDMA=m -+CONFIG_RDS_TCP=m -+ -+CONFIG_NET_9P=m -+CONFIG_NET_9P_VIRTIO=m -+# CONFIG_NET_9P_DEBUG is not set -+CONFIG_NET_9P_RDMA=m -+ -+# CONFIG_DECNET is not set -+CONFIG_BRIDGE=m -+CONFIG_BRIDGE_IGMP_SNOOPING=y -+CONFIG_BRIDGE_VLAN_FILTERING=y -+ -+# PHY timestamping adds overhead -+CONFIG_NETWORK_PHY_TIMESTAMPING=y -+ -+CONFIG_NETFILTER_ADVANCED=y -+CONFIG_NF_CONNTRACK=m -+CONFIG_NETFILTER_NETLINK=m -+CONFIG_NETFILTER_NETLINK_ACCT=m -+CONFIG_NETFILTER_NETLINK_QUEUE=m -+CONFIG_NETFILTER_NETLINK_QUEUE_CT=y -+CONFIG_NETFILTER_NETLINK_LOG=m -+CONFIG_NETFILTER_TPROXY=m -+CONFIG_NETFILTER_XTABLES=y -+CONFIG_NETFILTER_XT_SET=m -+CONFIG_NETFILTER_XT_MARK=m -+CONFIG_NETFILTER_XT_CONNMARK=m -+ -+CONFIG_NETFILTER_XT_TARGET_AUDIT=m -+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m -+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m -+CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m -+CONFIG_NETFILTER_XT_TARGET_CT=m -+CONFIG_NETFILTER_XT_TARGET_DSCP=m -+CONFIG_NETFILTER_XT_TARGET_HMARK=m -+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m -+CONFIG_NETFILTER_XT_TARGET_LED=m -+CONFIG_NETFILTER_XT_TARGET_LOG=m -+CONFIG_NETFILTER_XT_TARGET_MARK=m -+CONFIG_NETFILTER_XT_TARGET_NFLOG=m -+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m -+CONFIG_NETFILTER_XT_TARGET_RATEEST=m -+CONFIG_NETFILTER_XT_TARGET_SECMARK=m -+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m -+CONFIG_NETFILTER_XT_TARGET_TRACE=m -+CONFIG_NETFILTER_XT_TARGET_TEE=m -+CONFIG_NETFILTER_XT_TARGET_TPROXY=m -+ -+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m -+CONFIG_NETFILTER_XT_MATCH_BPF=m -+CONFIG_NETFILTER_XT_MATCH_CGROUP=m -+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m -+CONFIG_NETFILTER_XT_MATCH_COMMENT=m -+CONFIG_NETFILTER_XT_MATCH_CPU=m -+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m -+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m -+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y -+CONFIG_NETFILTER_XT_MATCH_DCCP=m -+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m -+CONFIG_NETFILTER_XT_MATCH_DSCP=m -+CONFIG_NETFILTER_XT_MATCH_ECN=m -+CONFIG_NETFILTER_XT_MATCH_ESP=m -+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m -+CONFIG_NETFILTER_XT_MATCH_HELPER=m -+CONFIG_NETFILTER_XT_MATCH_HL=m -+CONFIG_NETFILTER_XT_MATCH_IPCOMP=m -+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m -+CONFIG_NETFILTER_XT_MATCH_IPVS=m -+CONFIG_NETFILTER_XT_MATCH_L2TP=m -+CONFIG_NETFILTER_XT_MATCH_LENGTH=m -+CONFIG_NETFILTER_XT_MATCH_LIMIT=m -+CONFIG_NETFILTER_XT_MATCH_MAC=m -+CONFIG_NETFILTER_XT_MATCH_MARK=m -+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -+CONFIG_NETFILTER_XT_MATCH_NFACCT=m -+CONFIG_NETFILTER_XT_MATCH_OSF=m -+CONFIG_NETFILTER_XT_MATCH_OWNER=m -+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m -+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -+CONFIG_NETFILTER_XT_MATCH_POLICY=m -+CONFIG_NETFILTER_XT_MATCH_QUOTA=m -+CONFIG_NETFILTER_XT_MATCH_RATEEST=m -+CONFIG_NETFILTER_XT_MATCH_REALM=m -+CONFIG_NETFILTER_XT_MATCH_RECENT=m -+CONFIG_NETFILTER_XT_MATCH_SCTP=m -+CONFIG_NETFILTER_XT_MATCH_SOCKET=m -+CONFIG_NETFILTER_XT_MATCH_STATE=y -+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -+CONFIG_NETFILTER_XT_MATCH_STRING=m -+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -+CONFIG_NETFILTER_XT_MATCH_TIME=m -+CONFIG_NETFILTER_XT_MATCH_U32=m -+ -+# CONFIG_NETFILTER_DEBUG is not set -+CONFIG_BRIDGE_NETFILTER=y -+ -+# -+# IP: Netfilter Configuration -+# -+ -+CONFIG_NF_CONNTRACK_MARK=y -+CONFIG_NF_CONNTRACK_SECMARK=y -+CONFIG_NF_CONNTRACK_EVENTS=y -+CONFIG_NF_CONNTRACK_ZONES=y -+CONFIG_NF_CONNTRACK_PROCFS=y # check if contrack(8) in f17 supports netlink -+# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set -+CONFIG_NF_CONNTRACK_AMANDA=m -+CONFIG_NF_CONNTRACK_FTP=m -+CONFIG_NF_CONNTRACK_H323=m -+CONFIG_NF_CONNTRACK_IRC=m -+CONFIG_NF_CONNTRACK_NETBIOS_NS=m -+CONFIG_NF_CONNTRACK_PPTP=m -+CONFIG_NF_CONNTRACK_SANE=m -+CONFIG_NF_CONNTRACK_SIP=m -+CONFIG_NF_CONNTRACK_TFTP=m -+CONFIG_NF_CONNTRACK_IPV4=y -+CONFIG_NF_CONNTRACK_IPV6=y -+# CONFIG_NF_CONNTRACK_TIMEOUT is not set -+CONFIG_NF_CONNTRACK_TIMESTAMP=y -+CONFIG_NF_CONNTRACK_SNMP=m -+CONFIG_NF_NAT=m -+CONFIG_NF_NAT_SNMP_BASIC=m -+CONFIG_NF_CT_PROTO_DCCP=m -+CONFIG_NF_CT_PROTO_SCTP=m -+CONFIG_NF_CT_NETLINK=m -+# CONFIG_NF_CT_NETLINK_TIMEOUT is not set -+CONFIG_NF_CT_NETLINK_HELPER=m -+CONFIG_NF_CT_PROTO_UDPLITE=m -+ -+CONFIG_IP_NF_MATCH_AH=m -+CONFIG_IP_NF_MATCH_ECN=m -+CONFIG_IP_NF_MATCH_RPFILTER=m -+CONFIG_IP_NF_MATCH_TTL=m -+CONFIG_IP_NF_TARGET_CLUSTERIP=m -+CONFIG_IP_NF_TARGET_REDIRECT=m -+CONFIG_IP_NF_TARGET_NETMAP=m -+CONFIG_IP_NF_TARGET_ECN=m -+CONFIG_IP_NF_TARGET_LOG=m -+CONFIG_IP_NF_TARGET_ULOG=m -+CONFIG_IP_NF_TARGET_REJECT=y -+CONFIG_IP_NF_TARGET_SYNPROXY=m -+CONFIG_IP_NF_TARGET_TTL=m -+CONFIG_NF_NAT_IPV4=m -+CONFIG_IP_NF_TARGET_MASQUERADE=m -+CONFIG_IP_NF_MANGLE=m -+CONFIG_IP_NF_ARPTABLES=m -+CONFIG_IP_NF_ARPFILTER=m -+CONFIG_IP_NF_ARP_MANGLE=m -+CONFIG_IP_NF_QUEUE=m -+CONFIG_IP_NF_RAW=m -+ -+CONFIG_IP_NF_IPTABLES=y -+CONFIG_IP_NF_FILTER=y -+ -+# -+# IPv6: Netfilter Configuration -+# -+CONFIG_IP6_NF_FILTER=m -+CONFIG_IP6_NF_IPTABLES=m -+CONFIG_IP6_NF_MANGLE=m -+CONFIG_IP6_NF_MATCH_AH=m -+CONFIG_IP6_NF_MATCH_EUI64=m -+CONFIG_IP6_NF_MATCH_FRAG=m -+CONFIG_IP6_NF_MATCH_HL=m -+CONFIG_IP6_NF_MATCH_IPV6HEADER=m -+CONFIG_IP6_NF_MATCH_MH=m -+CONFIG_IP6_NF_MATCH_RPFILTER=m -+CONFIG_IP6_NF_MATCH_OPTS=m -+CONFIG_IP6_NF_MATCH_RT=m -+CONFIG_IP6_NF_QUEUE=m -+CONFIG_IP6_NF_RAW=m -+CONFIG_IP6_NF_SECURITY=m -+CONFIG_IP6_NF_TARGET_LOG=m -+CONFIG_IP6_NF_TARGET_REJECT=m -+CONFIG_IP6_NF_TARGET_SYNPROXY=m -+CONFIG_IP6_NF_TARGET_HL=m -+CONFIG_NF_NAT_IPV6=m -+CONFIG_IP6_NF_TARGET_MASQUERADE=m -+# CONFIG_IP6_NF_TARGET_NPT is not set -+ -+# nf_tables support -+CONFIG_NF_TABLES=m -+CONFIG_NF_TABLES_INET=m -+CONFIG_NFT_EXTHDR=m -+CONFIG_NFT_META=m -+CONFIG_NFT_CT=m -+CONFIG_NFT_RBTREE=m -+CONFIG_NFT_HASH=m -+CONFIG_NFT_COUNTER=m -+CONFIG_NFT_LOG=m -+CONFIG_NFT_LIMIT=m -+CONFIG_NFT_NAT=m -+CONFIG_NFT_QUEUE=m -+CONFIG_NFT_REJECT=m -+CONFIG_NFT_COMPAT=m -+ -+CONFIG_NF_TABLES_IPV4=m -+CONFIG_NFT_REJECT_IPV4=m -+CONFIG_NFT_CHAIN_ROUTE_IPV4=m -+CONFIG_NFT_CHAIN_NAT_IPV4=m -+CONFIG_NF_TABLES_ARP=m -+ -+CONFIG_NF_TABLES_IPV6=m -+CONFIG_NFT_CHAIN_ROUTE_IPV6=m -+CONFIG_NFT_CHAIN_NAT_IPV6=m -+ -+CONFIG_NF_TABLES_BRIDGE=m -+# -+# Bridge: Netfilter Configuration -+# -+CONFIG_BRIDGE_NF_EBTABLES=m -+CONFIG_BRIDGE_EBT_802_3=m -+CONFIG_BRIDGE_EBT_AMONG=m -+CONFIG_BRIDGE_EBT_ARP=m -+CONFIG_BRIDGE_EBT_ARPREPLY=m -+CONFIG_BRIDGE_EBT_BROUTE=m -+CONFIG_BRIDGE_EBT_DNAT=m -+CONFIG_BRIDGE_EBT_IP=m -+CONFIG_BRIDGE_EBT_IP6=m -+CONFIG_BRIDGE_EBT_LIMIT=m -+CONFIG_BRIDGE_EBT_LOG=m -+CONFIG_BRIDGE_EBT_MARK=m -+CONFIG_BRIDGE_EBT_MARK_T=m -+CONFIG_BRIDGE_EBT_NFLOG=m -+CONFIG_BRIDGE_EBT_PKTTYPE=m -+CONFIG_BRIDGE_EBT_REDIRECT=m -+CONFIG_BRIDGE_EBT_SNAT=m -+CONFIG_BRIDGE_EBT_STP=m -+CONFIG_BRIDGE_EBT_T_FILTER=m -+CONFIG_BRIDGE_EBT_T_NAT=m -+CONFIG_BRIDGE_EBT_ULOG=m -+CONFIG_BRIDGE_EBT_VLAN=m -+CONFIG_XFRM=y -+CONFIG_XFRM_MIGRATE=y -+CONFIG_XFRM_SUB_POLICY=y -+CONFIG_XFRM_STATISTICS=y -+CONFIG_XFRM_USER=y -+CONFIG_INET6_XFRM_MODE_TRANSPORT=m -+CONFIG_INET6_XFRM_MODE_TUNNEL=m -+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m -+CONFIG_INET6_XFRM_MODE_BEET=m -+ -+CONFIG_IP_SET=m -+CONFIG_IP_SET_MAX=256 -+CONFIG_IP_SET_BITMAP_IP=m -+CONFIG_IP_SET_BITMAP_IPMAC=m -+CONFIG_IP_SET_BITMAP_PORT=m -+CONFIG_IP_SET_HASH_IP=m -+CONFIG_IP_SET_HASH_IPPORT=m -+CONFIG_IP_SET_HASH_IPPORTIP=m -+CONFIG_IP_SET_HASH_IPPORTNET=m -+CONFIG_IP_SET_HASH_NETPORTNET=m -+CONFIG_IP_SET_HASH_NET=m -+CONFIG_IP_SET_HASH_NETNET=m -+CONFIG_IP_SET_HASH_NETPORT=m -+CONFIG_IP_SET_HASH_NETIFACE=m -+CONFIG_IP_SET_LIST_SET=m -+ -+# -+# SCTP Configuration (EXPERIMENTAL) -+# -+CONFIG_IP_SCTP=m -+CONFIG_NET_SCTPPROBE=m -+# CONFIG_SCTP_DBG_MSG is not set -+# CONFIG_SCTP_DBG_OBJCNT is not set -+CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1=y -+# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5 is not set -+# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set -+CONFIG_SCTP_COOKIE_HMAC_MD5=y -+CONFIG_SCTP_COOKIE_HMAC_SHA1=y -+CONFIG_ATM=m -+CONFIG_VLAN_8021Q_GVRP=y -+CONFIG_VLAN_8021Q_MVRP=y -+CONFIG_LLC=m -+# CONFIG_LLC2 is not set -+CONFIG_IPX=m -+# CONFIG_IPX_INTERN is not set -+CONFIG_ATALK=m -+CONFIG_DEV_APPLETALK=m -+CONFIG_IPDDP=m -+CONFIG_IPDDP_ENCAP=y -+CONFIG_IPDDP_DECAP=y -+# CONFIG_X25 is not set -+# CONFIG_LAPB is not set -+# CONFIG_ECONET is not set -+CONFIG_WAN_ROUTER=m -+CONFIG_IP_DCCP=m -+CONFIG_IP_DCCP_CCID2=m -+# CONFIG_IP_DCCP_CCID2_DEBUG is not set -+CONFIG_IP_DCCP_CCID3=y -+# CONFIG_IP_DCCP_CCID3_DEBUG is not set -+# CONFIG_IP_DCCP_DEBUG is not set -+# CONFIG_NET_DCCPPROBE is not set -+ -+# -+# TIPC Configuration (EXPERIMENTAL) -+# -+CONFIG_TIPC=m -+CONFIG_TIPC_PORTS=8192 -+# CONFIG_TIPC_MEDIA_IB is not set -+# CONFIG_TIPC_ADVANCED is not set -+# CONFIG_TIPC_DEBUG is not set -+ -+CONFIG_NETLABEL=y -+ -+# -+# QoS and/or fair queueing -+# -+CONFIG_NET_SCHED=y -+CONFIG_NET_SCH_CBQ=m -+CONFIG_NET_SCH_DSMARK=m -+CONFIG_NET_SCH_DRR=m -+CONFIG_NET_SCH_GRED=m -+CONFIG_NET_SCH_HFSC=m -+CONFIG_NET_SCH_HTB=m -+CONFIG_NET_SCH_INGRESS=m -+CONFIG_NET_SCH_NETEM=m -+CONFIG_NET_SCH_PRIO=m -+CONFIG_NET_SCH_RED=m -+CONFIG_NET_SCH_SFQ=m -+CONFIG_NET_SCH_TBF=m -+CONFIG_NET_SCH_TEQL=m -+CONFIG_NET_SCH_SFB=m -+CONFIG_NET_SCH_MQPRIO=m -+CONFIG_NET_SCH_MULTIQ=m -+CONFIG_NET_SCH_CHOKE=m -+CONFIG_NET_SCH_QFQ=m -+CONFIG_NET_SCH_CODEL=m -+CONFIG_NET_SCH_FQ_CODEL=m -+CONFIG_NET_SCH_FQ=m -+CONFIG_NET_SCH_HHF=m -+CONFIG_NET_SCH_PIE=m -+CONFIG_NET_SCH_PLUG=m -+CONFIG_NET_CLS=y -+CONFIG_NET_CLS_ACT=y -+CONFIG_NET_CLS_BASIC=m -+CONFIG_NET_CLS_CGROUP=y -+CONFIG_NET_CLS_BPF=m -+CONFIG_NET_CLS_FLOW=m -+CONFIG_NET_CLS_FW=m -+CONFIG_NET_CLS_IND=y -+CONFIG_NET_CLS_ROUTE4=m -+CONFIG_NET_CLS_ROUTE=y -+CONFIG_NET_CLS_RSVP=m -+CONFIG_NET_CLS_RSVP6=m -+CONFIG_NET_CLS_TCINDEX=m -+CONFIG_NET_CLS_U32=m -+CONFIG_CLS_U32_MARK=y -+CONFIG_CLS_U32_PERF=y -+CONFIG_NET_EMATCH=y -+CONFIG_NET_EMATCH_CMP=m -+CONFIG_NET_EMATCH_META=m -+CONFIG_NET_EMATCH_NBYTE=m -+CONFIG_NET_EMATCH_STACK=32 -+CONFIG_NET_EMATCH_TEXT=m -+CONFIG_NET_EMATCH_IPSET=m -+CONFIG_NET_EMATCH_U32=m -+ -+CONFIG_NET_ACT_CSUM=m -+CONFIG_NET_ACT_GACT=m -+CONFIG_GACT_PROB=y -+CONFIG_NET_ACT_IPT=m -+CONFIG_NET_ACT_MIRRED=m -+CONFIG_NET_ACT_NAT=m -+CONFIG_NET_ACT_PEDIT=m -+CONFIG_NET_ACT_POLICE=m -+CONFIG_NET_ACT_SIMP=m -+CONFIG_NET_ACT_SKBEDIT=m -+ -+CONFIG_DCB=y -+CONFIG_DNS_RESOLVER=m -+CONFIG_BATMAN_ADV=m -+CONFIG_BATMAN_ADV_BLA=y -+CONFIG_BATMAN_ADV_DAT=y -+CONFIG_BATMAN_ADV_NC=y -+ -+# CONFIG_BATMAN_ADV_DEBUG is not set -+CONFIG_OPENVSWITCH=m -+CONFIG_OPENVSWITCH_GRE=y -+CONFIG_OPENVSWITCH_VXLAN=y -+CONFIG_VSOCKETS=m -+ -+ -+# -+# Network testing -+# -+CONFIG_NET_PKTGEN=m -+# CONFIG_NET_TCPPROBE is not set -+CONFIG_NET_DROP_MONITOR=y -+ -+# disable later --kyle -+ -+# -+# ARCnet devices -+# -+# CONFIG_ARCNET is not set -+CONFIG_IFB=m -+CONFIG_NET_TEAM=m -+CONFIG_NET_TEAM_MODE_ROUNDROBIN=m -+CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m -+CONFIG_NET_TEAM_MODE_LOADBALANCE=m -+CONFIG_NET_TEAM_MODE_BROADCAST=m -+CONFIG_NET_TEAM_MODE_RANDOM=m -+CONFIG_DUMMY=m -+CONFIG_BONDING=m -+CONFIG_MACVLAN=m -+CONFIG_MACVTAP=m -+CONFIG_VXLAN=m -+CONFIG_EQUALIZER=m -+CONFIG_TUN=m -+CONFIG_VETH=m -+CONFIG_NLMON=m -+ -+# -+# ATM -+# -+CONFIG_ATM_DRIVERS=y -+# CONFIG_ATM_DUMMY is not set -+CONFIG_ATM_CLIP=m -+CONFIG_ATM_LANE=m -+CONFIG_ATM_BR2684=m -+CONFIG_NET_SCH_ATM=m -+CONFIG_ATM_TCP=m -+# CONFIG_ATM_LANAI is not set -+CONFIG_ATM_ENI=m -+CONFIG_ATM_FIRESTREAM=m -+# CONFIG_ATM_ZATM is not set -+# CONFIG_ATM_IDT77252 is not set -+# CONFIG_ATM_AMBASSADOR is not set -+# CONFIG_ATM_HORIZON is not set -+# CONFIG_ATM_FORE200E is not set -+# CONFIG_ATM_FORE200E_USE_TASKLET is not set -+CONFIG_ATM_FORE200E_TX_RETRY=16 -+CONFIG_ATM_FORE200E_DEBUG=0 -+ -+CONFIG_ATM_HE=m -+CONFIG_PPTP=m -+CONFIG_PPPOATM=m -+CONFIG_PPPOL2TP=m -+CONFIG_ATM_NICSTAR=m -+# CONFIG_ATM_IA is not set -+# CONFIG_ATM_CLIP_NO_ICMP is not set -+# CONFIG_ATM_MPOA is not set -+# CONFIG_ATM_BR2684_IPFILTER is not set -+# CONFIG_ATM_ENI_DEBUG is not set -+# CONFIG_ATM_ENI_TUNE_BURST is not set -+# CONFIG_ATM_ZATM_DEBUG is not set -+# CONFIG_ATM_IDT77252_DEBUG is not set -+# CONFIG_ATM_IDT77252_RCV_ALL is not set -+# CONFIG_ATM_AMBASSADOR_DEBUG is not set -+# CONFIG_ATM_HORIZON_DEBUG is not set -+# CONFIG_ATM_HE_USE_SUNI is not set -+# CONFIG_ATM_NICSTAR_USE_SUNI is not set -+# CONFIG_ATM_NICSTAR_USE_IDT77105 is not set -+# CONFIG_ATM_IA_DEBUG is not set -+CONFIG_ATM_SOLOS=m -+ -+CONFIG_L2TP=m -+CONFIG_L2TP_V3=y -+CONFIG_L2TP_IP=m -+CONFIG_L2TP_ETH=m -+ -+# CONFIG_CAIF is not set -+ -+CONFIG_RFKILL=m -+CONFIG_RFKILL_GPIO=m -+CONFIG_RFKILL_INPUT=y -+ -+ -+# -+# Ethernet (10 or 100Mbit) -+# -+ -+CONFIG_NET_VENDOR_ADAPTEC=y -+CONFIG_ADAPTEC_STARFIRE=m -+ -+CONFIG_NET_VENDOR_ALTEON=y -+CONFIG_ACENIC=m -+# CONFIG_ACENIC_OMIT_TIGON_I is not set -+ -+CONFIG_NET_VENDOR_AMD=y -+CONFIG_PCNET32=m -+CONFIG_AMD8111_ETH=m -+CONFIG_PCMCIA_NMCLAN=m -+ -+CONFIG_NET_VENDOR_ARC=y -+CONFIG_ARC_EMAC=m -+ -+CONFIG_NET_VENDOR_ATHEROS=y -+CONFIG_ALX=m -+CONFIG_ATL2=m -+CONFIG_ATL1=m -+CONFIG_ATL1C=m -+CONFIG_ATL1E=m -+CONFIG_NET_CADENCE=y -+CONFIG_ARM_AT91_ETHER=m -+CONFIG_MACB=m -+ -+CONFIG_NET_VENDOR_BROCADE=y -+CONFIG_BNA=m -+CONFIG_NET_CALXEDA_XGMAC=m -+ -+CONFIG_NET_VENDOR_CHELSIO=y -+CONFIG_CHELSIO_T1=m -+CONFIG_CHELSIO_T1_1G=y -+CONFIG_CHELSIO_T3=m -+CONFIG_CHELSIO_T4=m -+CONFIG_CHELSIO_T4VF=m -+ -+CONFIG_NET_VENDOR_CISCO=y -+CONFIG_ENIC=m -+ -+CONFIG_NET_VENDOR_DEC=y -+# -+# Tulip family network device support -+# -+CONFIG_NET_TULIP=y -+CONFIG_DE2104X=m -+CONFIG_DE2104X_DSL=0 -+CONFIG_TULIP=m -+# CONFIG_TULIP_NAPI is not set -+# CONFIG_TULIP_MWI is not set -+CONFIG_TULIP_MMIO=y -+# CONFIG_NI5010 is not set -+CONFIG_DE4X5=m -+CONFIG_WINBOND_840=m -+CONFIG_DM9102=m -+CONFIG_PCMCIA_XIRCOM=m -+CONFIG_ULI526X=m -+ -+CONFIG_NET_VENDOR_DLINK=y -+CONFIG_DE600=m -+CONFIG_DE620=m -+CONFIG_DL2K=m -+CONFIG_SUNDANCE=m -+# CONFIG_SUNDANCE_MMIO is not set -+ -+CONFIG_NET_VENDOR_EMULEX=y -+CONFIG_BE2NET=m -+ -+CONFIG_NET_VENDOR_EXAR=y -+CONFIG_S2IO=m -+CONFIG_VXGE=m -+# CONFIG_VXGE_DEBUG_TRACE_ALL is not set -+ -+# CONFIG_NET_VENDOR_FARADAY is not set -+# CONFIG_NET_VENDOR_FUJITSU is not set -+# CONFIG_NET_VENDOR_HP is not set -+CONFIG_NET_VENDOR_INTEL=y -+CONFIG_E100=m -+CONFIG_E1000=m -+CONFIG_E1000E=m -+CONFIG_IGB=m -+CONFIG_IGB_HWMON=y -+CONFIG_IGB_DCA=y -+CONFIG_IGB_PTP=y -+CONFIG_IGBVF=m -+CONFIG_IXGB=m -+CONFIG_IXGBEVF=m -+CONFIG_IXGBE=m -+CONFIG_IXGBE_DCA=y -+CONFIG_IXGBE_DCB=y -+CONFIG_IXGBE_HWMON=y -+CONFIG_IXGBE_PTP=y -+CONFIG_I40E=m -+# CONFIG_I40E_VXLAN is not set -+# CONFIG_I40E_DCB is not set -+# CONFIG_I40EVF is not set -+ -+ -+# CONFIG_NET_VENDOR_I825XX is not set -+CONFIG_NET_VENDOR_MARVELL=y -+CONFIG_MVMDIO=m -+CONFIG_SKGE=m -+# CONFIG_SKGE_DEBUG is not set -+CONFIG_SKGE_GENESIS=y -+CONFIG_SKY2=m -+# CONFIG_SKY2_DEBUG is not set -+ -+CONFIG_NET_VENDOR_MICREL=y -+CONFIG_KSZ884X_PCI=m -+# CONFIG_KS8842 is not set -+# CONFIG_KS8851_MLL is not set -+ -+CONFIG_NET_VENDOR_MYRI=y -+CONFIG_MYRI10GE=m -+CONFIG_MYRI10GE_DCA=y -+ -+CONFIG_NATSEMI=m -+CONFIG_NS83820=m -+ -+CONFIG_PCMCIA_AXNET=m -+CONFIG_NE2K_PCI=m -+CONFIG_NE3210=m -+CONFIG_PCMCIA_PCNET=m -+ -+CONFIG_NET_VENDOR_NVIDIA=y -+CONFIG_FORCEDETH=m -+ -+CONFIG_NET_VENDOR_OKI=y -+# CONFIG_PCH_GBE is not set -+# CONFIG_PCH_PTP is not set -+ -+CONFIG_NET_PACKET_ENGINE=y -+CONFIG_HAMACHI=m -+CONFIG_YELLOWFIN=m -+ -+CONFIG_NET_VENDOR_QLOGIC=y -+CONFIG_QLA3XXX=m -+CONFIG_QLCNIC=m -+CONFIG_QLCNIC_SRIOV=y -+CONFIG_QLCNIC_DCB=y -+CONFIG_QLGE=m -+CONFIG_NETXEN_NIC=m -+ -+CONFIG_NET_VENDOR_REALTEK=y -+CONFIG_ATP=m -+CONFIG_8139CP=m -+CONFIG_8139TOO=m -+# CONFIG_8139TOO_PIO is not set -+# CONFIG_8139TOO_TUNE_TWISTER is not set -+CONFIG_8139TOO_8129=y -+# CONFIG_8139_OLD_RX_RESET is not set -+CONFIG_R8169=m -+ -+ -+CONFIG_NET_VENDOR_RDC=y -+CONFIG_R6040=m -+ -+ -+CONFIG_NET_VENDOR_SILAN=y -+CONFIG_SC92031=m -+ -+CONFIG_NET_VENDOR_SIS=y -+CONFIG_SIS900=m -+CONFIG_SIS190=m -+ -+CONFIG_PCMCIA_SMC91C92=m -+CONFIG_EPIC100=m -+CONFIG_SMSC9420=m -+ -+# CONFIG_STMMAC_PLATFORM is not set -+# CONFIG_STMMAC_PCI is not set -+# CONFIG_STMMAC_DA is not set -+# CONFIG_STMMAC_DUAL_MAC is not set -+# CONFIG_STMMAC_TIMER is not set -+# CONFIG_STMMAC_DEBUG_FS is not set -+ -+CONFIG_NET_VENDOR_SUN=y -+CONFIG_HAPPYMEAL=m -+CONFIG_SUNGEM=m -+CONFIG_CASSINI=m -+CONFIG_NIU=m -+ -+CONFIG_NET_VENDOR_TEHUTI=y -+CONFIG_TEHUTI=m -+ -+CONFIG_NET_VENDOR_TI=y -+CONFIG_TLAN=m -+ -+CONFIG_VIA_RHINE=m -+CONFIG_VIA_RHINE_MMIO=y -+ -+CONFIG_WIZNET_W5100=m -+CONFIG_WIZNET_W5300=m -+CONFIG_NET_VENDOR_XIRCOM=y -+CONFIG_PCMCIA_XIRC2PS=m -+ -+CONFIG_AMD_PHY=m -+CONFIG_BROADCOM_PHY=m -+CONFIG_BCM87XX_PHY=m -+CONFIG_CICADA_PHY=m -+CONFIG_DAVICOM_PHY=m -+CONFIG_DP83640_PHY=m -+CONFIG_FIXED_PHY=y -+CONFIG_MDIO_BITBANG=m -+CONFIG_NATIONAL_PHY=m -+CONFIG_ICPLUS_PHY=m -+CONFIG_BCM63XX_PHY=m -+CONFIG_LSI_ET1011C_PHY=m -+CONFIG_LXT_PHY=m -+CONFIG_MARVELL_PHY=m -+CONFIG_QSEMI_PHY=m -+CONFIG_REALTEK_PHY=m -+CONFIG_SMSC_PHY=m -+CONFIG_STE10XP=m -+CONFIG_VITESSE_PHY=m -+CONFIG_MICREL_PHY=m -+ -+CONFIG_MII=m -+CONFIG_NET_CORE=y -+CONFIG_NET_VENDOR_3COM=y -+CONFIG_VORTEX=m -+CONFIG_TYPHOON=m -+CONFIG_DNET=m -+ -+ -+CONFIG_LNE390=m -+CONFIG_ES3210=m -+CONFIG_NET_PCI=y -+CONFIG_B44=m -+CONFIG_B44_PCI=y -+CONFIG_BNX2=m -+CONFIG_BNX2X=m -+CONFIG_BNX2X_SRIOV=y -+CONFIG_CNIC=m -+CONFIG_FEALNX=m -+CONFIG_NET_POCKET=y -+ -+# -+# Ethernet (1000 Mbit) -+# -+CONFIG_TIGON3=m -+CONFIG_JME=m -+ -+# -+# Ethernet (10000 Mbit) -+# -+# CONFIG_IP1000 is not set -+# CONFIG_MLX4_EN is not set -+# CONFIG_SFC is not set -+ -+# CONFIG_FDDI is not set -+# CONFIG_DEFXX is not set -+# CONFIG_SKFP is not set -+# CONFIG_HIPPI is not set -+# CONFIG_PLIP is not set -+CONFIG_PPP=m -+CONFIG_PPP_MULTILINK=y -+CONFIG_PPP_FILTER=y -+CONFIG_PPP_ASYNC=m -+CONFIG_PPP_SYNC_TTY=m -+CONFIG_PPP_DEFLATE=m -+CONFIG_IPPP_FILTER=y -+CONFIG_PPP_BSDCOMP=y -+CONFIG_PPPOE=m -+CONFIG_PPP_MPPE=m -+CONFIG_SLIP=m -+CONFIG_SLIP_COMPRESSED=y -+CONFIG_SLIP_SMART=y -+# CONFIG_SLIP_MODE_SLIP6 is not set -+ -+# -+# Wireless LAN -+# -+# -+# CONFIG_STRIP is not set -+# CONFIG_PCMCIA_RAYCS is not set -+ -+CONFIG_CFG80211_WEXT=y -+# CONFIG_CFG80211_REG_DEBUG is not set -+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set -+CONFIG_CFG80211_DEFAULT_PS=y -+CONFIG_NL80211=y -+# CONFIG_NL80211_TESTMODE is not set -+# CONFIG_WIRELESS_EXT_SYSFS is not set -+CONFIG_LIB80211=m -+CONFIG_LIB80211_CRYPT_WEP=m -+CONFIG_LIB80211_CRYPT_CCMP=m -+CONFIG_LIB80211_CRYPT_TKIP=m -+# CONFIG_LIB80211_DEBUG is not set -+ -+CONFIG_MAC80211=m -+CONFIG_MAC80211_RC_MINSTREL=y -+# CONFIG_MAC80211_RC_DEFAULT_PID is not set -+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y -+CONFIG_MAC80211_RC_DEFAULT="minstrel" -+CONFIG_MAC80211_MESH=y -+CONFIG_MAC80211_LEDS=y -+# CONFIG_MAC80211_DEBUG_MENU is not set -+ -+# CONFIG_WIMAX is not set -+ -+# CONFIG_ADM8211 is not set -+CONFIG_ATH_COMMON=m -+CONFIG_ATH_CARDS=m -+CONFIG_ATH5K=m -+CONFIG_ATH5K_DEBUG=y -+# CONFIG_ATH5K_TRACER is not set -+CONFIG_ATH6KL=m -+CONFIG_ATH6KL_DEBUG=y -+CONFIG_ATH6KL_SDIO=m -+CONFIG_ATH6KL_USB=m -+# CONFIG_ATH6KL_TRACING is not set -+CONFIG_AR5523=m -+CONFIG_ATH9K=m -+CONFIG_ATH9K_PCI=y -+CONFIG_ATH9K_AHB=y -+# CONFIG_ATH9K_DEBUG is not set -+# CONFIG_ATH9K_MAC_DEBUG is not set -+CONFIG_ATH9K_HTC=m -+CONFIG_ATH9K_BTCOEX_SUPPORT=y -+# CONFIG_ATH9K_LEGACY_RATE_CONTROL is not set -+# CONFIG_ATH9K_WOW is not set -+# -+CONFIG_ATH10K=m -+CONFIG_ATH10K_PCI=m -+# CONFIG_ATH10K_DEBUG is not set -+# CONFIG_ATH10K_TRACING is not set -+CONFIG_ATH10K_DEBUGFS=y -+CONFIG_WCN36XX=m -+# CONFIG_WCN36XX_DEBUGFS is not set -+CONFIG_WIL6210=m -+CONFIG_WIL6210_ISR_COR=y -+# CONFIG_WIL6210_TRACING is not set -+CONFIG_CARL9170=m -+CONFIG_CARL9170_LEDS=y -+# CONFIG_CARL9170_HWRNG is not set -+CONFIG_AT76C50X_USB=m -+# CONFIG_AIRO is not set -+# CONFIG_AIRO_CS is not set -+# CONFIG_ATMEL is not set -+CONFIG_B43=m -+CONFIG_B43_PCMCIA=y -+CONFIG_B43_SDIO=y -+CONFIG_B43_BCMA=y -+# CONFIG_B43_BCMA_EXTRA is not set -+CONFIG_B43_BCMA_PIO=y -+# CONFIG_B43_DEBUG is not set -+CONFIG_B43_PHY_LP=y -+CONFIG_B43_PHY_N=y -+CONFIG_B43_PHY_HT=y -+# CONFIG_B43_FORCE_PIO is not set -+CONFIG_B43LEGACY=m -+# CONFIG_B43LEGACY_DEBUG is not set -+CONFIG_B43LEGACY_DMA=y -+CONFIG_B43LEGACY_PIO=y -+CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y -+# CONFIG_B43LEGACY_DMA_MODE is not set -+# CONFIG_B43LEGACY_PIO_MODE is not set -+CONFIG_BRCMSMAC=m -+# CONFIG_BRCMFMAC_SDIO_OOB is not set -+CONFIG_BRCMFMAC_USB=y -+# CONFIG_BRCM_TRACING is not set -+# CONFIG_BRCMISCAN is not set -+# CONFIG_BRCMDBG is not set -+CONFIG_HERMES=m -+CONFIG_HERMES_CACHE_FW_ON_INIT=y -+# CONFIG_HERMES_PRISM is not set -+CONFIG_NORTEL_HERMES=m -+CONFIG_PCI_HERMES=m -+CONFIG_PLX_HERMES=m -+CONFIG_PCMCIA_HERMES=m -+CONFIG_ORINOCO_USB=m -+# CONFIG_TMD_HERMES is not set -+# CONFIG_PCMCIA_SPECTRUM is not set -+CONFIG_CW1200=m -+CONFIG_CW1200_WLAN_SDIO=m -+CONFIG_CW1200_WLAN_SPI=m -+# CONFIG_HOSTAP is not set -+# CONFIG_IPW2100 is not set -+# CONFIG_IPW2200 is not set -+# CONFIG_IPW2100_DEBUG is not set -+# CONFIG_IPW2200_DEBUG is not set -+# CONFIG_LIBIPW_DEBUG is not set -+CONFIG_LIBERTAS=m -+CONFIG_LIBERTAS_USB=m -+CONFIG_LIBERTAS_CS=m -+CONFIG_LIBERTAS_SDIO=m -+# CONFIG_LIBERTAS_DEBUG is not set -+# CONFIG_LIBERTAS_THINFIRM is not set -+CONFIG_LIBERTAS_MESH=y -+CONFIG_IWLWIFI=m -+CONFIG_IWLDVM=m -+CONFIG_IWLMVM=m -+CONFIG_IWLWIFI_DEBUG=y -+CONFIG_IWLWIFI_DEVICE_SVTOOL=y -+# CONFIG_IWLWIFI_EXPERIMENTAL_MFP is not set -+CONFIG_IWLWIFI_UCODE16=y -+# CONFIG_IWLWIFI_P2P is not set -+CONFIG_IWLEGACY=m -+CONFIG_IWLEGACY_DEBUG=y -+# CONFIG_IWLWIFI_LEGACY_DEVICE_TRACING is not set -+CONFIG_IWL4965=y -+CONFIG_IWL3945=m -+# CONFIG_IWM is not set -+# CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE is not set -+CONFIG_MAC80211_HWSIM=m -+CONFIG_P54_COMMON=m -+CONFIG_P54_USB=m -+CONFIG_P54_PCI=m -+CONFIG_MWL8K=m -+# CONFIG_PRISM54 is not set -+# CONFIG_PCMCIA_WL3501 is not set -+CONFIG_RT2X00=m -+# CONFIG_RT2X00_DEBUG is not set -+CONFIG_RT2400PCI=m -+CONFIG_RT2500PCI=m -+CONFIG_RT61PCI=m -+CONFIG_RT2500USB=m -+CONFIG_RT2800USB=m -+CONFIG_RT2800USB_RT33XX=y -+CONFIG_RT2800USB_RT35XX=y -+CONFIG_RT2800USB_RT3573=y -+CONFIG_RT2800USB_RT53XX=y -+CONFIG_RT2800USB_RT55XX=y -+CONFIG_RT2800USB_UNKNOWN=y -+CONFIG_RT2800PCI=m -+CONFIG_RT2800PCI_RT3290=y -+CONFIG_RT2800PCI_RT33XX=y -+CONFIG_RT2800PCI_RT35XX=y -+CONFIG_RT2800PCI_RT53XX=y -+CONFIG_RT73USB=m -+CONFIG_RTL8180=m -+CONFIG_RTL8187=m -+# CONFIG_USB_ZD1201 is not set -+# CONFIG_USB_NET_SR9800 is not set -+CONFIG_USB_NET_RNDIS_WLAN=m -+CONFIG_USB_NET_KALMIA=m -+CONFIG_USB_NET_QMI_WWAN=m -+CONFIG_USB_NET_SMSC75XX=m -+# CONFIG_WL_TI is not set -+CONFIG_ZD1211RW=m -+# CONFIG_ZD1211RW_DEBUG is not set -+ -+CONFIG_WL12XX=m -+CONFIG_WL12XX_SPI=m -+CONFIG_WL12XX_SDIO=m -+ -+CONFIG_WL1251=m -+CONFIG_WL1251_SPI=m -+CONFIG_WL1251_SDIO=m -+ -+CONFIG_RTL_CARDS=m -+CONFIG_RTLWIFI=m -+CONFIG_RTL8192CE=m -+CONFIG_RTL8192SE=m -+CONFIG_RTL8192CU=m -+CONFIG_RTL8192DE=m -+CONFIG_RTL8723AE=m -+CONFIG_RTL8188EE=m -+ -+CONFIG_MWIFIEX=m -+CONFIG_MWIFIEX_SDIO=m -+CONFIG_MWIFIEX_PCIE=m -+CONFIG_MWIFIEX_USB=m -+ -+# -+# Token Ring devices -+# -+# CONFIG_TR is not set -+ -+CONFIG_NET_FC=y -+ -+# -+# Wan interfaces -+# -+# CONFIG_WAN is not set -+ -+# -+# PCMCIA network device support -+# -+CONFIG_NET_PCMCIA=y -+CONFIG_PCMCIA_3C589=m -+CONFIG_PCMCIA_3C574=m -+CONFIG_PCMCIA_FMVJ18X=m -+ -+# -+# Amateur Radio support -+# -+CONFIG_HAMRADIO=y -+CONFIG_AX25=m -+CONFIG_AX25_DAMA_SLAVE=y -+ -+# CONFIG_CAN is not set -+ -+CONFIG_NETROM=m -+CONFIG_ROSE=m -+CONFIG_MKISS=m -+CONFIG_6PACK=m -+CONFIG_BPQETHER=m -+CONFIG_BAYCOM_SER_FDX=m -+CONFIG_BAYCOM_SER_HDX=m -+CONFIG_BAYCOM_PAR=m -+CONFIG_BAYCOM_EPP=m -+CONFIG_YAM=m -+ -+CONFIG_NFC=m -+CONFIG_NFC_DIGITAL=m -+CONFIG_NFC_NCI=m -+CONFIG_NFC_HCI=m -+CONFIG_NFC_SHDLC=y -+CONFIG_NFC_LLCP=y -+CONFIG_NFC_SIM=m -+CONFIG_NFC_MRVL=m -+CONFIG_NFC_MRVL_USB=m -+ -+# -+# Near Field Communication (NFC) devices -+# -+CONFIG_NFC_PORT100=m -+CONFIG_NFC_PN544=m -+CONFIG_NFC_PN544_I2C=m -+CONFIG_NFC_PN533=m -+CONFIG_NFC_MICROREAD=m -+CONFIG_NFC_MICROREAD_I2C=m -+ -+# -+# IrDA (infrared) support -+# -+CONFIG_IRDA=m -+# CONFIG_IRDA_DEBUG is not set -+CONFIG_IRLAN=m -+CONFIG_IRNET=m -+CONFIG_IRCOMM=m -+# CONFIG_IRDA_ULTRA is not set -+CONFIG_IRDA_CACHE_LAST_LSAP=y -+CONFIG_IRDA_FAST_RR=y -+CONFIG_IRTTY_SIR=m -+CONFIG_DONGLE=y -+CONFIG_ACTISYS_DONGLE=m -+CONFIG_ACT200L_DONGLE=m -+CONFIG_ESI_DONGLE=m -+CONFIG_GIRBIL_DONGLE=m -+CONFIG_KINGSUN_DONGLE=m -+CONFIG_KSDAZZLE_DONGLE=m -+CONFIG_KS959_DONGLE=m -+CONFIG_LITELINK_DONGLE=m -+CONFIG_MA600_DONGLE=m -+CONFIG_MCP2120_DONGLE=m -+CONFIG_OLD_BELKIN_DONGLE=m -+CONFIG_TEKRAM_DONGLE=m -+CONFIG_TOIM3232_DONGLE=m -+ -+CONFIG_ALI_FIR=m -+CONFIG_MCS_FIR=m -+CONFIG_NSC_FIR=m -+CONFIG_SIGMATEL_FIR=m -+CONFIG_SMC_IRCC_FIR=m -+# CONFIG_TOSHIBA_FIR is not set -+CONFIG_USB_IRDA=m -+CONFIG_VLSI_FIR=m -+CONFIG_VIA_FIR=m -+CONFIG_WINBOND_FIR=m -+ -+# -+# Bluetooth support -+# -+CONFIG_BT=m -+CONFIG_BT_L2CAP=y -+CONFIG_BT_SCO=y -+CONFIG_BT_CMTP=m -+CONFIG_BT_RFCOMM=m -+CONFIG_BT_RFCOMM_TTY=y -+CONFIG_BT_BNEP=m -+CONFIG_BT_BNEP_MC_FILTER=y -+CONFIG_BT_BNEP_PROTO_FILTER=y -+CONFIG_BT_HIDP=m -+ -+# -+# Bluetooth device drivers -+# -+CONFIG_BT_HCIBTUSB=m -+# Disable the BT_HCIUSB driver. -+# It sucks more power than BT_HCIBTUSB which has the same functionality. -+CONFIG_BT_HCIUART=m -+CONFIG_BT_HCIUART_H4=y -+CONFIG_BT_HCIUART_BCSP=y -+CONFIG_BT_HCIUART_ATH3K=y -+CONFIG_BT_HCIUART_3WIRE=y -+CONFIG_BT_HCIDTL1=m -+CONFIG_BT_HCIBT3C=m -+CONFIG_BT_HCIBLUECARD=m -+CONFIG_BT_HCIBTUART=m -+CONFIG_BT_HCIVHCI=m -+CONFIG_BT_HCIBCM203X=m -+CONFIG_BT_HCIBFUSB=m -+CONFIG_BT_HCIBPA10X=m -+CONFIG_BT_HCIBTSDIO=m -+CONFIG_BT_HCIUART_LL=y -+CONFIG_BT_MRVL=m -+CONFIG_BT_MRVL_SDIO=m -+CONFIG_BT_ATH3K=m -+CONFIG_BT_WILINK=m -+ -+# -+# ISDN subsystem -+# -+CONFIG_ISDN=y -+CONFIG_MISDN=m -+CONFIG_MISDN_DSP=m -+CONFIG_MISDN_L1OIP=m -+CONFIG_MISDN_AVMFRITZ=m -+CONFIG_MISDN_SPEEDFAX=m -+CONFIG_MISDN_INFINEON=m -+CONFIG_MISDN_W6692=m -+CONFIG_MISDN_NETJET=m -+ -+# -+# mISDN hardware drivers -+# -+CONFIG_MISDN_HFCPCI=m -+CONFIG_MISDN_HFCMULTI=m -+CONFIG_ISDN_I4L=m -+CONFIG_ISDN_DRV_AVMB1_B1PCI=m -+CONFIG_ISDN_DRV_AVMB1_B1PCMCIA=m -+CONFIG_ISDN_DRV_AVMB1_T1PCI=m -+CONFIG_ISDN_DRV_AVMB1_C4=m -+ -+CONFIG_MISDN_HFCUSB=m -+ -+CONFIG_ISDN_PPP=y -+CONFIG_ISDN_PPP_VJ=y -+CONFIG_ISDN_MPP=y -+# CONFIG_ISDN_PPP_BSDCOMP is not set -+CONFIG_ISDN_TTY_FAX=y -+CONFIG_DE_AOC=y -+ -+CONFIG_ISDN_AUDIO=y -+ -+CONFIG_ISDN_DRV_HISAX=m -+CONFIG_ISDN_DRV_AVMB1_B1PCIV4=y -+CONFIG_ISDN_DRV_AVMB1_AVM_CS=m -+ -+CONFIG_ISDN_CAPI_CAPIDRV=m -+CONFIG_ISDN_DIVERSION=m -+ -+CONFIG_HISAX_EURO=y -+CONFIG_HISAX_1TR6=y -+CONFIG_HISAX_NI1=y -+CONFIG_HISAX_MAX_CARDS=8 -+CONFIG_HISAX_16_3=y -+CONFIG_HISAX_TELESPCI=y -+CONFIG_HISAX_S0BOX=y -+CONFIG_HISAX_FRITZPCI=y -+CONFIG_HISAX_AVM_A1_PCMCIA=y -+CONFIG_HISAX_ELSA=y -+CONFIG_HISAX_DIEHLDIVA=y -+CONFIG_HISAX_SEDLBAUER=y -+CONFIG_HISAX_NETJET=y -+CONFIG_HISAX_NETJET_U=y -+CONFIG_HISAX_NICCY=y -+CONFIG_HISAX_BKM_A4T=y -+CONFIG_HISAX_SCT_QUADRO=y -+CONFIG_HISAX_GAZEL=y -+CONFIG_HISAX_HFC_PCI=y -+CONFIG_HISAX_W6692=y -+CONFIG_HISAX_HFC_SX=y -+CONFIG_HISAX_ENTERNOW_PCI=y -+# CONFIG_HISAX_DEBUG is not set -+CONFIG_HISAX_AVM_A1_CS=m -+CONFIG_HISAX_ST5481=m -+# CONFIG_HISAX_HFCUSB is not set -+CONFIG_HISAX_FRITZ_PCIPNP=m -+CONFIG_HISAX_NO_SENDCOMPLETE=y -+CONFIG_HISAX_NO_LLC=y -+CONFIG_HISAX_NO_KEYPAD=y -+CONFIG_HISAX_SEDLBAUER_CS=m -+CONFIG_HISAX_ELSA_CS=m -+CONFIG_HISAX_TELES_CS=m -+CONFIG_HISAX_HFC4S8S=m -+ -+CONFIG_ISDN_DRV_LOOP=m -+CONFIG_HYSDN=m -+CONFIG_HYSDN_CAPI=y -+ -+ -+# -+# CAPI subsystem -+# -+CONFIG_ISDN_CAPI=m -+# CONFIG_CAPI_TRACE is not set -+CONFIG_ISDN_DRV_AVMB1_VERBOSE_REASON=y -+CONFIG_ISDN_CAPI_MIDDLEWARE=y -+CONFIG_ISDN_CAPI_CAPI20=m -+ -+# -+# CAPI hardware drivers -+# -+ -+# -+# Active AVM cards -+# -+CONFIG_CAPI_AVM=y -+ -+# -+# Active Eicon DIVA Server cards -+# -+# CONFIG_CAPI_EICON is not set -+CONFIG_ISDN_DIVAS=m -+CONFIG_ISDN_DIVAS_BRIPCI=y -+CONFIG_ISDN_DIVAS_PRIPCI=y -+CONFIG_ISDN_DIVAS_DIVACAPI=m -+CONFIG_ISDN_DIVAS_USERIDI=m -+CONFIG_ISDN_DIVAS_MAINT=m -+ -+CONFIG_ISDN_DRV_GIGASET=m -+CONFIG_GIGASET_CAPI=y -+CONFIG_GIGASET_BASE=m -+CONFIG_GIGASET_M101=m -+CONFIG_GIGASET_M105=m -+# CONFIG_GIGASET_DEBUG is not set -+ -+# -+# Telephony Support -+# -+# CONFIG_PHONE is not set -+ -+# -+# Input device support -+# -+CONFIG_INPUT=y -+CONFIG_INPUT_FF_MEMLESS=m -+ -+# -+# Userland interfaces -+# -+CONFIG_INPUT_MOUSEDEV=y -+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -+CONFIG_INPUT_JOYDEV=m -+# CONFIG_INPUT_MATRIXKMAP is not set -+ -+CONFIG_INPUT_TABLET=y -+CONFIG_TABLET_USB_ACECAD=m -+CONFIG_TABLET_USB_AIPTEK=m -+CONFIG_TABLET_USB_GTCO=m -+CONFIG_TABLET_USB_HANWANG=m -+CONFIG_TABLET_USB_KBTAB=m -+CONFIG_TABLET_USB_WACOM=m -+ -+CONFIG_INPUT_POWERMATE=m -+CONFIG_INPUT_YEALINK=m -+CONFIG_INPUT_CM109=m -+CONFIG_INPUT_POLLDEV=m -+CONFIG_INPUT_SPARSEKMAP=m -+# CONFIG_INPUT_ADXL34X is not set -+# CONFIG_INPUT_BMA150 is not set -+# CONFIG_INPUT_IMS_PCU is not set -+CONFIG_INPUT_CMA3000=m -+CONFIG_INPUT_CMA3000_I2C=m -+CONFIG_INPUT_IDEAPAD_SLIDEBAR=m -+ -+# -+# Input I/O drivers -+# -+CONFIG_GAMEPORT=m -+CONFIG_GAMEPORT_NS558=m -+CONFIG_GAMEPORT_L4=m -+CONFIG_GAMEPORT_EMU10K1=m -+CONFIG_GAMEPORT_FM801=m -+CONFIG_SERIO=y -+CONFIG_SERIO_I8042=y -+CONFIG_SERIO_RAW=m -+CONFIG_SERIO_ALTERA_PS2=m -+# CONFIG_SERIO_PS2MULT is not set -+CONFIG_SERIO_ARC_PS2=m -+# CONFIG_SERIO_APBPS2 is not set -+ -+# CONFIG_SERIO_CT82C710 is not set -+# CONFIG_SERIO_OLPC_APSP is not set -+# CONFIG_SERIO_PARKBD is not set -+# CONFIG_SERIO_PCIPS2 is not set -+# CONFIG_SERIO_LIBPS2 is not set -+ -+# -+# Input Device Drivers -+# -+CONFIG_INPUT_KEYBOARD=y -+# CONFIG_KEYBOARD_SUNKBD is not set -+# CONFIG_KEYBOARD_SH_KEYSC is not set -+# CONFIG_KEYBOARD_XTKBD is not set -+# CONFIG_KEYBOARD_MATRIX is not set -+# CONFIG_KEYBOARD_NEWTON is not set -+# CONFIG_KEYBOARD_STOWAWAY is not set -+# CONFIG_KEYBOARD_LKKBD is not set -+# CONFIG_KEYBOARD_LM8323 is not set -+# CONFIG_KEYBOARD_LM8333 is not set -+# CONFIG_KEYBOARD_MAX7359 is not set -+# CONFIG_KEYBOARD_ADP5589 is not set -+# CONFIG_KEYBOARD_MPR121 is not set -+# CONFIG_KEYBOARD_QT1070 is not set -+# CONFIG_KEYBOARD_MCS is not set -+# CONFIG_KEYBOARD_OPENCORES is not set -+# CONFIG_KEYBOARD_SAMSUNG is not set -+# CONFIG_KEYBOARD_QT2160 is not set -+# CONFIG_KEYBOARD_TCA6416 is not set -+# CONFIG_KEYBOARD_TCA8418 is not set -+# CONFIG_KEYBOARD_OMAP4 is not set -+CONFIG_INPUT_MOUSE=y -+# CONFIG_MOUSE_PS2_TOUCHKIT is not set -+CONFIG_MOUSE_PS2_ELANTECH=y -+CONFIG_MOUSE_PS2_SENTELIC=y -+CONFIG_MOUSE_SERIAL=m -+CONFIG_MOUSE_VSXXXAA=m -+CONFIG_MOUSE_APPLETOUCH=m -+CONFIG_MOUSE_BCM5974=m -+CONFIG_MOUSE_SYNAPTICS_I2C=m -+CONFIG_MOUSE_SYNAPTICS_USB=m -+CONFIG_MOUSE_CYAPA=m -+CONFIG_INPUT_JOYSTICK=y -+CONFIG_JOYSTICK_ANALOG=m -+CONFIG_JOYSTICK_A3D=m -+CONFIG_JOYSTICK_ADI=m -+CONFIG_JOYSTICK_COBRA=m -+CONFIG_JOYSTICK_GF2K=m -+CONFIG_JOYSTICK_GRIP=m -+CONFIG_JOYSTICK_GRIP_MP=m -+CONFIG_JOYSTICK_GUILLEMOT=m -+CONFIG_JOYSTICK_INTERACT=m -+CONFIG_JOYSTICK_SIDEWINDER=m -+CONFIG_JOYSTICK_TMDC=m -+CONFIG_JOYSTICK_IFORCE=m -+CONFIG_JOYSTICK_IFORCE_USB=y -+CONFIG_JOYSTICK_IFORCE_232=y -+CONFIG_JOYSTICK_WARRIOR=m -+CONFIG_JOYSTICK_MAGELLAN=m -+CONFIG_JOYSTICK_SPACEORB=m -+CONFIG_JOYSTICK_SPACEBALL=m -+CONFIG_JOYSTICK_STINGER=m -+CONFIG_JOYSTICK_DB9=m -+CONFIG_JOYSTICK_GAMECON=m -+CONFIG_JOYSTICK_TURBOGRAFX=m -+CONFIG_JOYSTICK_JOYDUMP=m -+CONFIG_JOYSTICK_TWIDJOY=m -+CONFIG_JOYSTICK_WALKERA0701=m -+CONFIG_JOYSTICK_XPAD=m -+CONFIG_JOYSTICK_XPAD_FF=y -+CONFIG_JOYSTICK_XPAD_LEDS=y -+CONFIG_JOYSTICK_ZHENHUA=m -+# CONFIG_JOYSTICK_AS5011 is not set -+ -+CONFIG_INPUT_TOUCHSCREEN=y -+# CONFIG_TOUCHSCREEN_AD7879 is not set -+CONFIG_TOUCHSCREEN_AD7879_I2C=m -+# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set -+# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set -+# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set -+CONFIG_TOUCHSCREEN_DYNAPRO=m -+CONFIG_TOUCHSCREEN_EDT_FT5X06=m -+CONFIG_TOUCHSCREEN_EETI=m -+CONFIG_TOUCHSCREEN_EGALAX=m -+CONFIG_TOUCHSCREEN_ELO=m -+CONFIG_TOUCHSCREEN_FUJITSU=m -+CONFIG_TOUCHSCREEN_GUNZE=m -+# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set -+CONFIG_TOUCHSCREEN_INEXIO=m -+CONFIG_TOUCHSCREEN_ILI210X=m -+CONFIG_TOUCHSCREEN_MMS114=m -+CONFIG_TOUCHSCREEN_MTOUCH=m -+CONFIG_TOUCHSCREEN_MCS5000=m -+CONFIG_TOUCHSCREEN_MK712=m -+CONFIG_TOUCHSCREEN_PENMOUNT=m -+# CONFIG_TOUCHSCREEN_SUR40 is not set -+# CONFIG_TOUCHSCREEN_TPS6507X is not set -+CONFIG_TOUCHSCREEN_TSC_SERIO=m -+CONFIG_TOUCHSCREEN_TSC2007=m -+CONFIG_TOUCHSCREEN_TOUCHIT213=m -+CONFIG_TOUCHSCREEN_TOUCHRIGHT=m -+CONFIG_TOUCHSCREEN_TOUCHWIN=m -+CONFIG_TOUCHSCREEN_PIXCIR=m -+CONFIG_TOUCHSCREEN_UCB1400=m -+CONFIG_TOUCHSCREEN_WACOM_W8001=m -+CONFIG_TOUCHSCREEN_WACOM_I2C=m -+CONFIG_TOUCHSCREEN_USB_E2I=y -+CONFIG_TOUCHSCREEN_USB_COMPOSITE=m -+# CONFIG_TOUCHSCREEN_WM97XX is not set -+CONFIG_TOUCHSCREEN_W90X900=m -+# CONFIG_TOUCHSCREEN_BU21013 is not set -+CONFIG_TOUCHSCREEN_ST1232=m -+CONFIG_TOUCHSCREEN_ATMEL_MXT=m -+# CONFIG_TOUCHSCREEN_MAX11801 is not set -+CONFIG_TOUCHSCREEN_AUO_PIXCIR=m -+CONFIG_TOUCHSCREEN_TI_AM335X_TSC=m -+CONFIG_TOUCHSCREEN_ZFORCE=m -+ -+CONFIG_INPUT_PCSPKR=m -+CONFIG_INPUT_RETU_PWRBUTTON=m -+CONFIG_INPUT_UINPUT=m -+CONFIG_INPUT_WISTRON_BTNS=m -+CONFIG_INPUT_ATLAS_BTNS=m -+ -+CONFIG_INPUT_ATI_REMOTE2=m -+CONFIG_INPUT_KEYSPAN_REMOTE=m -+ -+CONFIG_MAC_EMUMOUSEBTN=y -+ -+CONFIG_INPUT_WM831X_ON=m -+ -+ -+# CONFIG_INPUT_AD714X is not set -+# CONFIG_INPUT_PCF8574 is not set -+CONFIG_INPUT_MMA8450=m -+CONFIG_INPUT_MPU3050=m -+CONFIG_INPUT_KXTJ9=m -+# CONFIG_INPUT_KXTJ9_POLLED_MODE is not set -+ -+# -+# Character devices -+# -+CONFIG_VT=y -+CONFIG_VT_CONSOLE=y -+CONFIG_HW_CONSOLE=y -+CONFIG_SERIAL_NONSTANDARD=y -+CONFIG_ROCKETPORT=m -+CONFIG_SYNCLINK=m -+CONFIG_SYNCLINKMP=m -+CONFIG_SYNCLINK_GT=m -+CONFIG_N_HDLC=m -+CONFIG_N_GSM=m -+# CONFIG_TRACE_SINK is not set -+# CONFIG_STALDRV is not set -+# CONFIG_DUMMY_IRQ is not set -+# CONFIG_IBM_ASM is not set -+CONFIG_TIFM_CORE=m -+CONFIG_TIFM_7XX1=m -+CONFIG_TCG_TPM=m -+CONFIG_TCG_TIS=m -+# CONFIG_TCG_TIS_I2C_INFINEON is not set -+# CONFIG_TCG_TIS_I2C_ATMEL is not set -+# CONFIG_TCG_TIS_I2C_NUVOTON is not set -+CONFIG_TCG_NSC=m -+CONFIG_TCG_ATMEL=m -+# CONFIG_TCG_INFINEON is not set -+# CONFIG_TCG_ST33_I2C is not set -+# CONFIG_TCG_XEN is not set -+CONFIG_TELCLOCK=m -+ -+# -+# Serial drivers -+# -+CONFIG_SERIAL_8250=y -+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set -+CONFIG_SERIAL_8250_CONSOLE=y -+CONFIG_SERIAL_8250_CS=m -+CONFIG_SERIAL_8250_NR_UARTS=32 -+CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -+CONFIG_SERIAL_8250_EXTENDED=y -+CONFIG_SERIAL_8250_MANY_PORTS=y -+CONFIG_SERIAL_8250_SHARE_IRQ=y -+# CONFIG_SERIAL_8250_DETECT_IRQ is not set -+CONFIG_SERIAL_8250_RSA=y -+# CONFIG_SERIAL_8250_DW is not set -+CONFIG_CYCLADES=m -+# CONFIG_CYZ_INTR is not set -+# CONFIG_MOXA_INTELLIO is not set -+# CONFIG_MOXA_SMARTIO is not set -+# CONFIG_ISI is not set -+# CONFIG_RIO is not set -+CONFIG_SERIAL_JSM=m -+# CONFIG_SERIAL_SCCNXP is not set -+# CONFIG_SERIAL_MFD_HSU is not set -+ -+# CONFIG_SERIAL_ALTERA_JTAGUART is not set -+# CONFIG_SERIAL_ALTERA_UART is not set -+ -+# -+# Non-8250 serial port support -+# -+CONFIG_SERIAL_CORE=y -+CONFIG_SERIAL_CORE_CONSOLE=y -+# CONFIG_SERIAL_XILINX_PS_UART is not set -+# CONFIG_SERIAL_TIMBERDALE is not set -+CONFIG_SERIAL_ARC=m -+CONFIG_SERIAL_ARC_NR_PORTS=1 -+# CONFIG_SERIAL_RP2 is not set -+# CONFIG_SERIAL_ST_ASC is not set -+# CONFIG_SERIAL_PCH_UART is not set -+ -+CONFIG_UNIX98_PTYS=y -+CONFIG_DEVPTS_MULTIPLE_INSTANCES=y -+CONFIG_PRINTER=m -+CONFIG_LP_CONSOLE=y -+CONFIG_PPDEV=m -+ -+# -+# I2C support -+# -+CONFIG_I2C=y -+# CONFIG_I2C_MUX is not set -+# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set -+# CONFIG_I2C_MUX_PCA954x is not set -+# CONFIG_I2C_MUX_GPIO is not set -+# CONFIG_I2C_MUX_PCA9541 is not set -+# CONFIG_I2C_MUX_PINCTRL is not set -+# -+ -+# -+# I2C Algorithms -+# -+# CONFIG_I2C_DEBUG_ALGO is not set -+CONFIG_I2C_ALGOBIT=m -+ -+# -+# I2C Hardware Bus support -+# -+ -+# CONFIG_I2C_ALI1535 is not set -+# CONFIG_I2C_ALI1563 is not set -+# CONFIG_I2C_ALI15X3 is not set -+# CONFIG_I2C_AMD756 is not set -+# CONFIG_I2C_AMD756_S4882 is not set -+# CONFIG_I2C_AMD8111 is not set -+# CONFIG_I2C_DEBUG_CORE is not set -+# CONFIG_I2C_DEBUG_BUS is not set -+# CONFIG_I2C_I801 is not set -+# CONFIG_I2C_ISCH is not set -+# CONFIG_I2C_NFORCE2_S4985 is not set -+# CONFIG_I2C_INTEL_MID is not set -+# CONFIG_I2C_EG20T is not set -+# CONFIG_I2C_CBUS_GPIO is not set -+CONFIG_I2C_VIPERBOARD=m -+ -+CONFIG_EEPROM_AT24=m -+CONFIG_EEPROM_LEGACY=m -+CONFIG_EEPROM_93CX6=m -+CONFIG_EEPROM_MAX6875=m -+ -+CONFIG_I2C_NFORCE2=m -+# CONFIG_I2C_OCORES is not set -+CONFIG_I2C_PARPORT=m -+CONFIG_I2C_PARPORT_LIGHT=m -+# CONFIG_I2C_ROBOTFUZZ_OSIF is not set -+CONFIG_I2C_PASEMI=m -+CONFIG_I2C_PCA_PLATFORM=m -+# CONFIG_I2C_PIIX4 is not set -+# CONFIG_SCx200_ACB is not set -+# CONFIG_I2C_SIS5595 is not set -+# CONFIG_I2C_SIS630 is not set -+# CONFIG_I2C_SIS96X is not set -+CONFIG_I2C_SIMTEC=m -+CONFIG_I2C_STUB=m -+CONFIG_I2C_TINY_USB=m -+# CONFIG_I2C_TAOS_EVM is not set -+# CONFIG_I2C_VIA is not set -+# CONFIG_I2C_VIAPRO is not set -+# CONFIG_I2C_DESIGNWARE is not set -+# CONFIG_I2C_XILINX is not set -+ -+CONFIG_I2C_DIOLAN_U2C=m -+ -+# -+# I2C Hardware Sensors Chip support -+# -+CONFIG_SENSORS_ATK0110=m -+CONFIG_SENSORS_ABITUGURU=m -+CONFIG_SENSORS_ABITUGURU3=m -+CONFIG_SENSORS_AD7414=m -+CONFIG_SENSORS_AD7418=m -+CONFIG_SENSORS_ADM1021=m -+CONFIG_SENSORS_ADM1025=m -+CONFIG_SENSORS_ADM1026=m -+CONFIG_SENSORS_ADM1029=m -+CONFIG_SENSORS_ADM1031=m -+CONFIG_SENSORS_ADM9240=m -+CONFIG_SENSORS_ADT7310=m -+CONFIG_SENSORS_ADT7410=m -+CONFIG_SENSORS_ADS7828=m -+CONFIG_SENSORS_ADT7462=m -+CONFIG_SENSORS_ADT7470=m -+CONFIG_SENSORS_ADT7475=m -+CONFIG_SENSORS_APPLESMC=m -+CONFIG_SENSORS_ASB100=m -+CONFIG_SENSORS_ATXP1=m -+CONFIG_SENSORS_CORETEMP=m -+CONFIG_SENSORS_DME1737=m -+CONFIG_SENSORS_DS1621=m -+# CONFIG_DS1682 is not set -+CONFIG_SENSORS_F71805F=m -+CONFIG_SENSORS_F71882FG=m -+CONFIG_SENSORS_F75375S=m -+CONFIG_SENSORS_FSCHMD=m -+CONFIG_SENSORS_G760A=m -+CONFIG_SENSORS_G762=m -+CONFIG_SENSORS_GL518SM=m -+CONFIG_SENSORS_GL520SM=m -+CONFIG_SENSORS_HDAPS=m -+# CONFIG_SENSORS_HIH6130 is not set -+# CONFIG_SENSORS_HTU21 is not set -+# CONFIG_SENSORS_I5K_AMB is not set -+# FIXME: IBMAEM x86 only? -+CONFIG_SENSORS_IBMAEM=m -+CONFIG_SENSORS_IBMPEX=m -+# CONFIG_SENSORS_IIO_HWMON is not set -+CONFIG_SENSORS_IT87=m -+CONFIG_SENSORS_K8TEMP=m -+CONFIG_SENSORS_K10TEMP=m -+CONFIG_SENSORS_LIS3LV02D=m -+CONFIG_SENSORS_LIS3_SPI=m -+CONFIG_SENSORS_LIS3_I2C=m -+CONFIG_SENSORS_LM63=m -+CONFIG_SENSORS_LM75=m -+CONFIG_SENSORS_LM77=m -+CONFIG_SENSORS_LM78=m -+CONFIG_SENSORS_LM80=m -+CONFIG_SENSORS_LM83=m -+CONFIG_SENSORS_LM85=m -+CONFIG_SENSORS_LM87=m -+CONFIG_SENSORS_LM90=m -+CONFIG_SENSORS_LM92=m -+CONFIG_SENSORS_LM93=m -+CONFIG_SENSORS_LM95234=m -+CONFIG_SENSORS_LTC4245=m -+CONFIG_SENSORS_MAX1619=m -+CONFIG_SENSORS_MAX6650=m -+CONFIG_SENSORS_MAX6697=m -+CONFIG_SENSORS_MCP3021=m -+CONFIG_SENSORS_NCT6775=m -+CONFIG_SENSORS_NTC_THERMISTOR=m -+CONFIG_SENSORS_PC87360=m -+CONFIG_SENSORS_PC87427=m -+CONFIG_SENSORS_PCF8591=m -+CONFIG_SENSORS_SHT15=m -+CONFIG_SENSORS_SIS5595=m -+CONFIG_CHARGER_SMB347=m -+CONFIG_SENSORS_SMSC47M1=m -+CONFIG_SENSORS_SMSC47M192=m -+CONFIG_SENSORS_SMSC47B397=m -+CONFIG_SENSORS_THMC50=m -+CONFIG_SENSORS_TMP401=m -+CONFIG_APDS9802ALS=m -+CONFIG_ISL29020=m -+CONFIG_ISL29003=m -+CONFIG_SENSORS_BH1770=m -+CONFIG_SENSORS_APDS990X=m -+CONFIG_SENSORS_TSL2550=m -+CONFIG_SENSORS_VIA686A=m -+CONFIG_SENSORS_VIA_CPUTEMP=m -+CONFIG_SENSORS_VT1211=m -+CONFIG_SENSORS_VT8231=m -+CONFIG_SENSORS_W83627HF=m -+CONFIG_SENSORS_W83781D=m -+CONFIG_SENSORS_W83L785TS=m -+CONFIG_SENSORS_W83L786NG=m -+CONFIG_SENSORS_W83627EHF=m -+CONFIG_SENSORS_W83791D=m -+CONFIG_SENSORS_W83792D=m -+CONFIG_SENSORS_W83793=m -+CONFIG_SENSORS_LTC4215=m -+CONFIG_SENSORS_LM95241=m -+CONFIG_SENSORS_LM95245=m -+CONFIG_SENSORS_TMP421=m -+CONFIG_SENSORS_WM8350=m -+CONFIG_SENSORS_WM831X=m -+CONFIG_SENSORS_LM73=m -+CONFIG_SENSORS_AMC6821=m -+CONFIG_SENSORS_INA2XX=m -+CONFIG_SENSORS_INA209=m -+CONFIG_SENSORS_ADT7411=m -+CONFIG_SENSORS_ASC7621=m -+CONFIG_SENSORS_EMC1403=m -+CONFIG_SENSORS_TMP102=m -+CONFIG_SENSORS_LTC4261=m -+# CONFIG_SENSORS_BH1780 is not set -+# CONFIG_SENSORS_JC42 is not set -+# CONFIG_SENSORS_SMM665 is not set -+# CONFIG_SENSORS_EMC2103 is not set -+# CONFIG_SENSORS_GPIO_FAN is not set -+CONFIG_SENSORS_W83795=m -+# CONFIG_SENSORS_W83795_FANCTRL is not set -+CONFIG_SENSORS_DS620=m -+CONFIG_SENSORS_SHT21=m -+CONFIG_SENSORS_LINEAGE=m -+CONFIG_SENSORS_LTC4151=m -+CONFIG_SENSORS_MAX6639=m -+CONFIG_SENSORS_SCH5627=m -+CONFIG_SENSORS_SCH5636=m -+CONFIG_SENSORS_ADS1015=m -+CONFIG_SENSORS_MAX16065=m -+CONFIG_SENSORS_MAX6642=m -+CONFIG_SENSORS_ADM1275=m -+CONFIG_SENSORS_UCD9000=m -+CONFIG_SENSORS_UCD9200=m -+CONFIG_SENSORS_ZL6100=m -+CONFIG_SENSORS_EMC6W201=m -+ -+CONFIG_PMBUS=m -+CONFIG_SENSORS_PMBUS=m -+CONFIG_SENSORS_MAX16064=m -+CONFIG_SENSORS_LM25066=m -+CONFIG_SENSORS_LTC2978=m -+CONFIG_SENSORS_MAX34440=m -+CONFIG_SENSORS_MAX8688=m -+CONFIG_SENSORS_MAX1668=m -+CONFIG_SENSORS_MAX197=m -+ -+# Industrial I/O subsystem configuration -+CONFIG_IIO=m -+CONFIG_IIO_BUFFER=y -+CONFIG_IIO_BUFFER_CB=y -+# CONFIG_IIO_KFIFO_BUF is not set -+CONFIG_IIO_TRIGGERED_BUFFER=m -+CONFIG_IIO_TRIGGER=y -+CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 -+CONFIG_IIO_INTERRUPT_TRIGGER=m -+CONFIG_HID_SENSOR_IIO_COMMON=m -+CONFIG_HID_SENSOR_IIO_TRIGGER=m -+CONFIG_HID_SENSOR_ENUM_BASE_QUIRKS=y -+# CONFIG_IIO_SYSFS_TRIGGER is not set -+# CONFIG_AD5446 is not set -+# CONFIG_AD5380 is not set -+# CONFIG_AD5064 is not set -+# CONFIG_BMA180 is not set -+# CONFIG_MAX1363 is not set -+# CONFIG_MAX517 is not set -+# CONFIG_MCP4725 is not set -+# CONFIG_ITG3200 is not set -+# CONFIG_APDS9300 is not set -+# CONFIG_CM32181 is not set -+# CONFIG_CM36651 is not set -+# CONFIG_GP2AP020A00F is not set -+# CONFIG_TSL2583 is not set -+# CONFIG_TSL2x7x is not set -+# CONFIG_TCS3472 is not set -+# CONFIG_TSL4531 is not set -+# CONFIG_NAU7802 is not set -+# CONFIG_TI_ADC081C is not set -+# CONFIG_EXYNOS_ADC is not set -+# CONFIG_VIPERBOARD_ADC is not set -+# CONFIG_INV_MPU6050_IIO is not set -+CONFIG_IIO_ST_GYRO_3AXIS=m -+CONFIG_IIO_ST_MAGN_3AXIS=m -+CONFIG_IIO_ST_ACCEL_3AXIS=m -+CONFIG_HID_SENSOR_INCLINOMETER_3D=m -+# CONFIG_ADJD_S311 is not set -+# CONFIG_SENSORS_TSL2563 is not set -+# CONFIG_VCNL4000 is not set -+# CONFIG_AK8975 is not set -+# CONFIG_MAG3110 is not set -+# CONFIG_TMP006 is not set -+# CONFIG_IIO_ST_PRESS is not set -+# CONFIG_KXSD9 is not set -+# CONFIG_AD7266 is not set -+# CONFIG_AD7298 is not set -+# CONFIG_AD7476 is not set -+# CONFIG_AD7791 is not set -+# CONFIG_AD7793 is not set -+# CONFIG_AD7887 is not set -+# CONFIG_AD7923 is not set -+# CONFIG_MCP320X is not set -+# CONFIG_MCP3422 is not set -+# CONFIG_AD8366 is not set -+# CONFIG_AD5360 is not set -+# CONFIG_AD5421 is not set -+# CONFIG_AD5449 is not set -+# CONFIG_AD5504 is not set -+# CONFIG_AD5624R_SPI is not set -+# CONFIG_AD5686 is not set -+# CONFIG_AD5755 is not set -+# CONFIG_AD5764 is not set -+# CONFIG_AD5791 is not set -+# CONFIG_AD7303 is not set -+# CONFIG_AD9523 is not set -+# CONFIG_ADF4350 is not set -+# CONFIG_ADIS16080 is not set -+# CONFIG_ADIS16130 is not set -+# CONFIG_ADIS16136 is not set -+# CONFIG_ADIS16260 is not set -+# CONFIG_ADXRS450 is not set -+# CONFIG_ADIS16400 is not set -+# CONFIG_ADIS16480 is not set -+# CONFIG_DHT11 is not set -+# CONFIG_MPL3115 is not set -+ -+# staging IIO drivers -+# CONFIG_AD7291 is not set -+# CONFIG_AD7606 is not set -+# CONFIG_AD799X is not set -+# CONFIG_ADT7316 is not set -+# CONFIG_AD7150 is not set -+# CONFIG_AD7152 is not set -+# CONFIG_AD7746 is not set -+# CONFIG_AD5933 is not set -+# CONFIG_ADE7854 is not set -+# CONFIG_SENSORS_ISL29018 is not set -+# CONFIG_SENSORS_ISL29028 is not set -+# CONFIG_SENSORS_HMC5843 is not set -+# CONFIG_IIO_PERIODIC_RTC_TRIGGER is not set -+# CONFIG_IIO_SIMPLE_DUMMY is not set -+# CONFIG_ADIS16201 is not set -+# CONFIG_ADIS16203 is not set -+# CONFIG_ADIS16204 is not set -+# CONFIG_ADIS16209 is not set -+# CONFIG_ADIS16220 is not set -+# CONFIG_ADIS16240 is not set -+# CONFIG_LIS3L02DQ is not set -+# CONFIG_SCA3000 is not set -+# CONFIG_AD7780 is not set -+# CONFIG_AD7816 is not set -+# CONFIG_AD7192 is not set -+# CONFIG_AD7280 is not set -+# CONFIG_AD5930 is not set -+# CONFIG_AD9832 is not set -+# CONFIG_AD9834 is not set -+# CONFIG_AD9850 is not set -+# CONFIG_AD9852 is not set -+# CONFIG_AD9910 is not set -+# CONFIG_AD9951 is not set -+# CONFIG_ADIS16060 is not set -+# CONFIG_ADE7753 is not set -+# CONFIG_ADE7754 is not set -+# CONFIG_ADE7758 is not set -+# CONFIG_ADE7759 is not set -+# CONFIG_AD2S90 is not set -+# CONFIG_AD2S1200 is not set -+# CONFIG_AD2S1210 is not set -+ -+ -+ -+# CONFIG_HMC6352 is not set -+# CONFIG_BMP085 is not set -+# CONFIG_BMP085_I2C is not set -+# CONFIG_PCH_PHUB is not set -+# CONFIG_USB_SWITCH_FSA9480 is not set -+ -+CONFIG_W1=m -+CONFIG_W1_CON=y -+# CONFIG_W1_MASTER_MATROX is not set -+CONFIG_W1_MASTER_DS2490=m -+CONFIG_W1_MASTER_DS2482=m -+CONFIG_W1_MASTER_DS1WM=m -+CONFIG_W1_MASTER_GPIO=m -+# CONFIG_HDQ_MASTER_OMAP is not set -+CONFIG_W1_SLAVE_THERM=m -+CONFIG_W1_SLAVE_SMEM=m -+CONFIG_W1_SLAVE_DS2408=m -+# CONFIG_W1_SLAVE_DS2408_READBACK is not set -+CONFIG_W1_SLAVE_DS2413=m -+CONFIG_W1_SLAVE_DS2423=m -+CONFIG_W1_SLAVE_DS2431=m -+CONFIG_W1_SLAVE_DS2433=m -+CONFIG_W1_SLAVE_DS2433_CRC=y -+CONFIG_W1_SLAVE_DS2760=m -+CONFIG_W1_SLAVE_DS2780=m -+CONFIG_W1_SLAVE_DS2781=m -+CONFIG_W1_SLAVE_DS28E04=m -+CONFIG_W1_SLAVE_BQ27000=m -+ -+# -+# Mice -+# -+ -+# -+# IPMI -+# -+CONFIG_IPMI_HANDLER=m -+# CONFIG_IPMI_PANIC_EVENT is not set -+CONFIG_IPMI_DEVICE_INTERFACE=m -+CONFIG_IPMI_WATCHDOG=m -+CONFIG_IPMI_SI=m -+CONFIG_IPMI_POWEROFF=m -+ -+# -+# Watchdog Cards -+# -+CONFIG_WATCHDOG_CORE=y -+# CONFIG_WATCHDOG_NOWAYOUT is not set -+CONFIG_SOFT_WATCHDOG=m -+CONFIG_WDTPCI=m -+# CONFIG_ACQUIRE_WDT is not set -+# CONFIG_ADVANTECH_WDT is not set -+# CONFIG_EUROTECH_WDT is not set -+CONFIG_IB700_WDT=m -+# CONFIG_SCx200_WDT is not set -+# CONFIG_60XX_WDT is not set -+CONFIG_W83877F_WDT=m -+CONFIG_W83627HF_WDT=m -+CONFIG_MACHZ_WDT=m -+# CONFIG_SC520_WDT is not set -+CONFIG_ALIM7101_WDT=m -+CONFIG_ALIM1535_WDT=m -+CONFIG_IT87_WDT=m -+CONFIG_ITCO_WDT=m -+CONFIG_ITCO_VENDOR_SUPPORT=y -+# CONFIG_SC1200_WDT is not set -+# CONFIG_PC87413_WDT is not set -+# CONFIG_WAFER_WDT is not set -+# CONFIG_CPU5_WDT is not set -+CONFIG_I6300ESB_WDT=m -+CONFIG_IT8712F_WDT=m -+# CONFIG_SBC8360_WDT is not set -+# CONFIG_SBC7240_WDT is not set -+CONFIG_SMSC_SCH311X_WDT=m -+CONFIG_W83977F_WDT=m -+CONFIG_PCIPCWATCHDOG=m -+CONFIG_USBPCWATCHDOG=m -+# CONFIG_SBC_EPX_C3_WATCHDOG is not set -+CONFIG_WM8350_WATCHDOG=m -+CONFIG_WM831X_WATCHDOG=m -+# CONFIG_MAX63XX_WATCHDOG is not set -+# CONFIG_DW_WATCHDOG is not set -+CONFIG_W83697UG_WDT=m -+# CONFIG_MEN_A21_WDT is not set -+# CONFIG_GPIO_WATCHDOG is not set -+ -+CONFIG_HW_RANDOM=y -+CONFIG_HW_RANDOM_TIMERIOMEM=m -+CONFIG_HW_RANDOM_TPM=m -+# CONFIG_HW_RANDOM_ATMEL is not set -+# CONFIG_HW_RANDOM_EXYNOS is not set -+# CONFIG_NVRAM is not set -+# CONFIG_RTC is not set -+# CONFIG_RTC_DEBUG is not set -+# CONFIG_GEN_RTC is not set -+CONFIG_RTC_HCTOSYS=y -+# CONFIG_RTC_SYSTOHC is not set -+CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -+CONFIG_RTC_INTF_SYSFS=y -+CONFIG_RTC_INTF_PROC=y -+CONFIG_RTC_INTF_DEV=y -+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -+CONFIG_RTC_DRV_CMOS=y -+CONFIG_RTC_DRV_DS1307=m -+CONFIG_RTC_DRV_DS1511=m -+CONFIG_RTC_DRV_DS1553=m -+CONFIG_RTC_DRV_DS1672=m -+CONFIG_RTC_DRV_DS1742=m -+CONFIG_RTC_DRV_DS1374=m -+# CONFIG_RTC_DRV_EP93XX is not set -+CONFIG_RTC_DRV_FM3130=m -+CONFIG_RTC_DRV_ISL1208=m -+CONFIG_RTC_DRV_M41T80=m -+CONFIG_RTC_DRV_M41T80_WDT=y -+CONFIG_RTC_DRV_M48T59=m -+CONFIG_RTC_DRV_MAX6900=m -+# CONFIG_RTC_DRV_M48T86 is not set -+CONFIG_RTC_DRV_PCF2127=m -+CONFIG_RTC_DRV_PCF8563=m -+CONFIG_RTC_DRV_PCF8583=m -+CONFIG_RTC_DRV_RS5C372=m -+# CONFIG_RTC_DRV_SA1100 is not set -+# CONFIG_RTC_DRV_TEST is not set -+CONFIG_RTC_DRV_X1205=m -+CONFIG_RTC_DRV_V3020=m -+CONFIG_RTC_DRV_DS2404=m -+CONFIG_RTC_DRV_STK17TA8=m -+# CONFIG_RTC_DRV_S35390A is not set -+CONFIG_RTC_DRV_RX8581=m -+CONFIG_RTC_DRV_RX8025=m -+CONFIG_RTC_DRV_DS1286=m -+CONFIG_RTC_DRV_M48T35=m -+CONFIG_RTC_DRV_BQ4802=m -+CONFIG_RTC_DRV_WM8350=m -+# CONFIG_RTC_DRV_AB3100 is not set -+CONFIG_RTC_DRV_WM831X=m -+CONFIG_RTC_DRV_BQ32K=m -+CONFIG_RTC_DRV_MSM6242=m -+CONFIG_RTC_DRV_RP5C01=m -+CONFIG_RTC_DRV_EM3027=m -+CONFIG_RTC_DRV_RV3029C2=m -+CONFIG_RTC_DRV_PCF50633=m -+CONFIG_RTC_DRV_DS3232=m -+CONFIG_RTC_DRV_ISL12022=m -+# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set -+# CONFIG_RTC_DRV_MOXART is not set -+# CONFIG_RTC_DRV_ISL12057 is not set -+ -+CONFIG_R3964=m -+# CONFIG_APPLICOM is not set -+# CONFIG_SONYPI is not set -+ -+# -+# Ftape, the floppy tape device driver -+# -+CONFIG_AGP=y -+CONFIG_AGP_ALI=y -+CONFIG_AGP_ATI=y -+CONFIG_AGP_AMD=y -+CONFIG_AGP_AMD64=y -+CONFIG_AGP_INTEL=y -+CONFIG_AGP_NVIDIA=y -+CONFIG_AGP_SIS=y -+CONFIG_AGP_SWORKS=y -+CONFIG_AGP_VIA=y -+CONFIG_AGP_EFFICEON=y -+ -+CONFIG_VGA_ARB=y -+CONFIG_VGA_ARB_MAX_GPUS=16 -+ -+# CONFIG_STUB_POULSBO is not set -+ -+# -+# PCMCIA character devices -+# -+# CONFIG_SYNCLINK_CS is not set -+ -+CONFIG_CARDMAN_4000=m -+CONFIG_CARDMAN_4040=m -+ -+CONFIG_MWAVE=m -+CONFIG_RAW_DRIVER=y -+CONFIG_MAX_RAW_DEVS=8192 -+CONFIG_HANGCHECK_TIMER=m -+ -+CONFIG_MEDIA_PCI_SUPPORT=y -+# -+# Multimedia devices -+# -+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y -+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y -+CONFIG_MEDIA_RC_SUPPORT=y -+CONFIG_MEDIA_CONTROLLER=y -+CONFIG_VIDEO_DEV=m -+# CONFIG_VIDEO_ADV_DEBUG is not set -+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y -+CONFIG_VIDEO_V4L2=y -+CONFIG_VIDEO_V4L2_SUBDEV_API=y -+# CONFIG_VIDEO_VIVI is not set -+# CONFIG_USB_SI4713 is not set -+# CONFIG_PLATFORM_SI4713 is not set -+# CONFIG_I2C_SI4713 is not set -+# CONFIG_USB_RAREMONO is not set -+ -+# -+# Video For Linux -+# -+ -+# -+# Video Adapters -+# -+CONFIG_V4L_USB_DRIVERS=y -+CONFIG_VIDEO_CAPTURE_DRIVERS=y -+CONFIG_V4L_PCI_DRIVERS=y -+CONFIG_VIDEO_AU0828=m -+CONFIG_VIDEO_AU0828_V4L2=y -+CONFIG_VIDEO_BT848=m -+CONFIG_VIDEO_BT848_DVB=y -+CONFIG_VIDEO_BWQCAM=m -+CONFIG_VIDEO_SR030PC30=m -+CONFIG_VIDEO_NOON010PC30=m -+CONFIG_VIDEO_CAFE_CCIC=m -+# CONFIG_VIDEO_CPIA is not set -+CONFIG_VIDEO_CPIA2=m -+CONFIG_VIDEO_CQCAM=m -+CONFIG_VIDEO_CX23885=m -+CONFIG_MEDIA_ALTERA_CI=m -+CONFIG_VIDEO_CX18=m -+CONFIG_VIDEO_CX18_ALSA=m -+CONFIG_VIDEO_CX88=m -+CONFIG_VIDEO_CX88_DVB=m -+CONFIG_VIDEO_CX88_ALSA=m -+CONFIG_VIDEO_CX88_BLACKBIRD=m -+CONFIG_VIDEO_CX88_ENABLE_VP3054=y -+CONFIG_VIDEO_CX88_VP3054=m -+CONFIG_VIDEO_EM28XX=m -+CONFIG_VIDEO_EM28XX_V4L2=m -+CONFIG_VIDEO_EM28XX_ALSA=m -+CONFIG_VIDEO_EM28XX_DVB=m -+CONFIG_VIDEO_EM28XX_RC=y -+CONFIG_VIDEO_CX231XX=m -+CONFIG_VIDEO_CX231XX_ALSA=m -+CONFIG_VIDEO_CX231XX_DVB=m -+CONFIG_VIDEO_CX231XX_RC=y -+CONFIG_VIDEO_HEXIUM_ORION=m -+CONFIG_VIDEO_HEXIUM_GEMINI=m -+CONFIG_VIDEO_IVTV=m -+# CONFIG_VIDEO_IVTV_ALSA is not set -+CONFIG_VIDEO_MEYE=m -+CONFIG_VIDEO_MXB=m -+CONFIG_VIDEO_PVRUSB2_DVB=y -+# CONFIG_VIDEO_PMS is not set -+CONFIG_VIDEO_HDPVR=m -+CONFIG_VIDEO_SAA6588=m -+CONFIG_VIDEO_SAA7134=m -+CONFIG_VIDEO_SAA7134_ALSA=m -+CONFIG_VIDEO_SAA7134_DVB=m -+CONFIG_VIDEO_SAA7134_RC=y -+CONFIG_VIDEO_USBVISION=m -+CONFIG_VIDEO_STK1160_COMMON=m -+CONFIG_VIDEO_STK1160=m -+CONFIG_VIDEO_STK1160_AC97=y -+CONFIG_VIDEO_W9966=m -+CONFIG_VIDEO_ZORAN=m -+CONFIG_VIDEO_ZORAN_AVS6EYES=m -+CONFIG_VIDEO_ZORAN_BUZ=m -+CONFIG_VIDEO_ZORAN_DC10=m -+CONFIG_VIDEO_ZORAN_DC30=m -+CONFIG_VIDEO_ZORAN_LML33=m -+CONFIG_VIDEO_ZORAN_LML33R10=m -+CONFIG_VIDEO_ZORAN_ZR36060=m -+# CONFIG_V4L_ISA_PARPORT_DRIVERS is not set -+CONFIG_VIDEO_FB_IVTV=m -+CONFIG_VIDEO_SAA7164=m -+CONFIG_VIDEO_TM6000=m -+CONFIG_VIDEO_TM6000_ALSA=m -+CONFIG_VIDEO_TM6000_DVB=m -+CONFIG_VIDEO_TLG2300=m -+CONFIG_VIDEO_USBTV=m -+ -+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y -+ -+# -+# Radio Adapters -+# -+CONFIG_RADIO_MAXIRADIO=m -+CONFIG_RADIO_SHARK=m -+CONFIG_RADIO_SHARK2=m -+CONFIG_RADIO_WL1273=m -+ -+CONFIG_MEDIA_ATTACH=y -+ -+# -+# V4L/DVB tuners -+# Selected automatically by not setting CONFIG_MEDIA_TUNER_CUSTOMISE -+# -+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set -+ -+# -+# Digital Video Broadcasting Devices -+# -+CONFIG_DVB_CAPTURE_DRIVERS=y -+CONFIG_DVB_CORE=m -+CONFIG_DVB_NET=y -+CONFIG_DVB_MAX_ADAPTERS=8 -+CONFIG_DVB_DYNAMIC_MINORS=y -+ -+# -+# DVB frontends -+# Selected automatically by not setting CONFIG_DVB_FE_CUSTOMISE -+# -+# CONFIG_DVB_FE_CUSTOMISE is not set -+ -+# -+# Supported DVB bridge Modules -+# -+CONFIG_DVB_BT8XX=m -+CONFIG_DVB_BUDGET_CORE=m -+CONFIG_DVB_PLUTO2=m -+CONFIG_SMS_SIANO_MDTV=m -+CONFIG_SMS_SIANO_RC=y -+# CONFIG_SMS_SIANO_DEBUGFS is not set -+CONFIG_MEDIA_SUBDRV_AUTOSELECT=y -+CONFIG_SMS_USB_DRV=m -+CONFIG_SMS_SDIO_DRV=m -+CONFIG_DVB_TTUSB_DEC=m -+CONFIG_DVB_USB_DTV5100=m -+CONFIG_DVB_USB_AF9015=m -+CONFIG_DVB_USB_ANYSEE=m -+CONFIG_DVB_USB_DW2102=m -+CONFIG_DVB_USB_FRIIO=m -+CONFIG_DVB_USB_EC168=m -+CONFIG_DVB_USB_PCTV452E=m -+CONFIG_DVB_USB_IT913X=m -+CONFIG_DVB_USB_MXL111SF=m -+CONFIG_DVB_DM1105=m -+CONFIG_DVB_FIREDTV=m -+CONFIG_DVB_NGENE=m -+CONFIG_DVB_DDBRIDGE=m -+CONFIG_DVB_USB_TECHNISAT_USB2=m -+CONFIG_DVB_USB_V2=m -+ -+CONFIG_DVB_AV7110=m -+CONFIG_DVB_AV7110_OSD=y -+CONFIG_DVB_BUDGET=m -+CONFIG_DVB_BUDGET_CI=m -+CONFIG_DVB_BUDGET_AV=m -+CONFIG_DVB_BUDGET_PATCH=m -+ -+CONFIG_DVB_TTUSB_BUDGET=m -+ -+CONFIG_DVB_USB_CINERGY_T2=m -+CONFIG_DVB_B2C2_FLEXCOP=m -+# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set -+ -+CONFIG_DVB_B2C2_FLEXCOP_PCI=m -+# CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set -+CONFIG_DVB_B2C2_FLEXCOP_USB=m -+# CONFIG_DVB_B2C2_FLEXCOP_DEBUG is not set -+CONFIG_DVB_USB=m -+# CONFIG_DVB_USB_DEBUG is not set -+CONFIG_DVB_USB_A800=m -+CONFIG_DVB_USB_AF9005=m -+CONFIG_DVB_USB_AF9005_REMOTE=m -+CONFIG_DVB_USB_AU6610=m -+CONFIG_DVB_USB_CXUSB=m -+CONFIG_DVB_USB_DIBUSB_MB=m -+# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set -+CONFIG_DVB_USB_DIBUSB_MC=m -+CONFIG_DVB_USB_DIB0700=m -+CONFIG_DVB_USB_DIGITV=m -+CONFIG_DVB_USB_DTT200U=m -+CONFIG_DVB_USB_GL861=m -+CONFIG_DVB_USB_GP8PSK=m -+CONFIG_DVB_USB_M920X=m -+CONFIG_DVB_USB_NOVA_T_USB2=m -+CONFIG_DVB_USB_CE6230=m -+CONFIG_DVB_USB_OPERA1=m -+CONFIG_DVB_USB_TTUSB2=m -+CONFIG_DVB_USB_UMT_010=m -+CONFIG_DVB_USB_VP702X=m -+CONFIG_DVB_USB_VP7045=m -+CONFIG_DVB_USB_AZ6027=m -+CONFIG_DVB_USB_AZ6007=m -+CONFIG_DVB_USB_LME2510=m -+CONFIG_DVB_USB_RTL28XXU=m -+CONFIG_DVB_USB_AF9035=m -+ -+CONFIG_DVB_PT1=m -+ -+CONFIG_MANTIS_CORE=m -+CONFIG_DVB_MANTIS=m -+CONFIG_DVB_HOPPER=m -+ -+CONFIG_VIDEO_SAA7146=m -+CONFIG_VIDEO_SAA7146_VV=m -+CONFIG_VIDEO_TVP5150=m -+CONFIG_VIDEO_TUNER=m -+CONFIG_VIDEO_BTCX=m -+CONFIG_VIDEO_PVRUSB2=m -+CONFIG_VIDEO_PVRUSB2_SYSFS=y -+# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set -+ -+CONFIG_RC_CORE=m -+CONFIG_RC_DECODERS=y -+CONFIG_LIRC=m -+CONFIG_RC_LOOPBACK=m -+CONFIG_RC_MAP=m -+CONFIG_RC_DEVICES=y -+CONFIG_RC_ATI_REMOTE=m -+CONFIG_IR_NEC_DECODER=m -+CONFIG_IR_RC5_DECODER=m -+CONFIG_IR_RC6_DECODER=m -+CONFIG_IR_JVC_DECODER=m -+CONFIG_IR_SONY_DECODER=m -+CONFIG_IR_RC5_SZ_DECODER=m -+CONFIG_IR_SANYO_DECODER=m -+CONFIG_IR_MCE_KBD_DECODER=m -+CONFIG_IR_LIRC_CODEC=m -+CONFIG_IR_IMON=m -+CONFIG_IR_MCEUSB=m -+CONFIG_IR_ITE_CIR=m -+CONFIG_IR_NUVOTON=m -+CONFIG_IR_FINTEK=m -+CONFIG_IR_REDRAT3=m -+CONFIG_IR_ENE=m -+CONFIG_IR_STREAMZAP=m -+CONFIG_IR_WINBOND_CIR=m -+CONFIG_IR_IGUANA=m -+CONFIG_IR_TTUSBIR=m -+CONFIG_IR_GPIO_CIR=m -+ -+CONFIG_V4L_MEM2MEM_DRIVERS=y -+# CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set -+# CONFIG_VIDEO_SH_VEU is not set -+# CONFIG_VIDEO_RENESAS_VSP1 is not set -+# CONFIG_V4L_TEST_DRIVERS is not set -+ -+# CONFIG_VIDEO_MEM2MEM_TESTDEV is not set -+ -+# -+# Broadcom Crystal HD video decoder driver -+# -+CONFIG_CRYSTALHD=m -+ -+# -+# Graphics support -+# -+ -+CONFIG_DISPLAY_SUPPORT=m -+CONFIG_VIDEO_OUTPUT_CONTROL=m -+ -+# -+# Console display driver support -+# -+CONFIG_VGA_CONSOLE=y -+CONFIG_VGACON_SOFT_SCROLLBACK=y -+CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64 -+CONFIG_DUMMY_CONSOLE=y -+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -+ -+# -+# Logo configuration -+# -+# CONFIG_LOGO_LINUX_MONO is not set -+# CONFIG_LOGO_LINUX_VGA16 is not set -+CONFIG_LOGO_LINUX_CLUT224=y -+ -+# -+# Sound -+# -+ -+# -+# Advanced Linux Sound Architecture -+# -+CONFIG_SOUND_OSS_CORE_PRECLAIM=y -+# CONFIG_SND_DEBUG_VERBOSE is not set -+CONFIG_SND_VERBOSE_PROCFS=y -+CONFIG_SND_SEQUENCER=y -+CONFIG_SND_HRTIMER=y -+CONFIG_SND_SEQ_HRTIMER_DEFAULT=y -+CONFIG_SND_SEQ_DUMMY=m -+CONFIG_SND_SEQUENCER_OSS=y -+CONFIG_SND_SEQ_RTCTIMER_DEFAULT=y -+CONFIG_SND_OSSEMUL=y -+CONFIG_SND_MIXER_OSS=y -+CONFIG_SND_PCM_OSS=y -+CONFIG_SND_PCM_OSS_PLUGINS=y -+CONFIG_SND_RTCTIMER=y -+CONFIG_SND_DYNAMIC_MINORS=y -+CONFIG_SND_MAX_CARDS=32 -+# CONFIG_SND_SUPPORT_OLD_API is not set -+ -+# -+# Generic devices -+# -+CONFIG_SND_DUMMY=m -+CONFIG_SND_ALOOP=m -+CONFIG_SND_VIRMIDI=m -+CONFIG_SND_MTPAV=m -+CONFIG_SND_MTS64=m -+CONFIG_SND_SERIAL_U16550=m -+CONFIG_SND_MPU401=m -+CONFIG_SND_PORTMAN2X4=m -+CONFIG_SND_AC97_POWER_SAVE=y -+CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0 -+ -+CONFIG_SND_DRIVERS=y -+ -+# -+# ISA devices -+# -+CONFIG_SND_AD1889=m -+ -+# -+# PCI devices -+# -+CONFIG_SND_PCI=y -+CONFIG_SND_ALI5451=m -+CONFIG_SND_ALS300=m -+CONFIG_SND_ALS4000=m -+CONFIG_SND_ATIIXP=m -+CONFIG_SND_ATIIXP_MODEM=m -+CONFIG_SND_AU8810=m -+CONFIG_SND_AU8820=m -+CONFIG_SND_AU8830=m -+# CONFIG_SND_AW2 is not set -+CONFIG_SND_AZT3328=m -+CONFIG_SND_BT87X=m -+# CONFIG_SND_BT87X_OVERCLOCK is not set -+CONFIG_SND_CA0106=m -+CONFIG_SND_CMIPCI=m -+CONFIG_SND_CS46XX=m -+CONFIG_SND_CS46XX_NEW_DSP=y -+CONFIG_SND_CS4281=m -+CONFIG_SND_CS5530=m -+CONFIG_SND_CS5535AUDIO=m -+CONFIG_SND_EMU10K1=m -+CONFIG_SND_EMU10K1X=m -+CONFIG_SND_ENS1370=m -+CONFIG_SND_ENS1371=m -+CONFIG_SND_ES1938=m -+CONFIG_SND_ES1968=m -+CONFIG_SND_ES1968_INPUT=y -+CONFIG_SND_ES1968_RADIO=y -+CONFIG_SND_FM801=m -+CONFIG_SND_FM801_TEA575X_BOOL=y -+CONFIG_SND_CTXFI=m -+CONFIG_SND_LX6464ES=m -+CONFIG_SND_HDA_INTEL=y -+CONFIG_SND_HDA_INPUT_BEEP=y -+CONFIG_SND_HDA_INPUT_BEEP_MODE=0 -+CONFIG_SND_HDA_INPUT_JACK=y -+CONFIG_SND_HDA_PATCH_LOADER=y -+CONFIG_SND_HDA_HWDEP=y -+CONFIG_SND_HDA_CODEC_REALTEK=y -+CONFIG_SND_HDA_ENABLE_REALTEK_QUIRKS=y -+CONFIG_SND_HDA_CODEC_CA0110=y -+CONFIG_SND_HDA_CODEC_ANALOG=y -+CONFIG_SND_HDA_CODEC_SIGMATEL=y -+CONFIG_SND_HDA_CODEC_VIA=y -+CONFIG_SND_HDA_CODEC_CIRRUS=y -+CONFIG_SND_HDA_CODEC_CONEXANT=y -+CONFIG_SND_HDA_CODEC_CMEDIA=y -+CONFIG_SND_HDA_CODEC_SI3054=y -+CONFIG_SND_HDA_CODEC_HDMI=y -+CONFIG_SND_HDA_I915=y -+CONFIG_SND_HDA_CODEC_CA0132=y -+CONFIG_SND_HDA_CODEC_CA0132_DSP=y -+CONFIG_SND_HDA_GENERIC=y -+CONFIG_SND_HDA_POWER_SAVE=y -+CONFIG_SND_HDA_POWER_SAVE_DEFAULT=0 -+CONFIG_SND_HDA_RECONFIG=y -+CONFIG_SND_HDA_PREALLOC_SIZE=4096 -+CONFIG_SND_HDSPM=m -+CONFIG_SND_ICE1712=m -+CONFIG_SND_ICE1724=m -+CONFIG_SND_INTEL8X0=y -+CONFIG_SND_INTEL8X0M=m -+CONFIG_SND_KORG1212=m -+CONFIG_SND_MAESTRO3=m -+CONFIG_SND_MAESTRO3_INPUT=y -+CONFIG_SND_MIXART=m -+CONFIG_SND_NM256=m -+CONFIG_SND_OXYGEN=m -+CONFIG_SND_RME32=m -+CONFIG_SND_PCSP=m -+CONFIG_SND_PCXHR=m -+CONFIG_SND_RIPTIDE=m -+CONFIG_SND_RME96=m -+CONFIG_SND_RME9652=m -+CONFIG_SND_SIS7019=m -+CONFIG_SND_SONICVIBES=m -+CONFIG_SND_HDSP=m -+CONFIG_SND_TRIDENT=m -+CONFIG_SND_VIA82XX=m -+CONFIG_SND_VIA82XX_MODEM=m -+CONFIG_SND_VIRTUOSO=m -+CONFIG_SND_VX222=m -+CONFIG_SND_YMFPCI=m -+CONFIG_SND_ASIHPI=m -+CONFIG_SND_LOLA=m -+ -+# -+# ALSA USB devices -+# -+CONFIG_SND_USB=y -+CONFIG_SND_USB_CAIAQ=m -+CONFIG_SND_USB_CAIAQ_INPUT=y -+CONFIG_SND_USB_USX2Y=m -+CONFIG_SND_USB_US122L=m -+CONFIG_SND_USB_UA101=m -+CONFIG_SND_USB_6FIRE=m -+CONFIG_SND_USB_HIFACE=m -+ -+# -+# PCMCIA devices -+# -+# CONFIG_SND_PCMCIA is not set -+ -+CONFIG_SND_FIREWIRE=y -+CONFIG_SND_FIREWIRE_SPEAKERS=m -+CONFIG_SND_ISIGHT=m -+CONFIG_SND_SCS1X=m -+CONFIG_SND_DICE=m -+ -+# -+# Open Sound System -+# -+# CONFIG_SOUND_PRIME is not set -+ -+# -+# USB support -+# -+CONFIG_USB_SUPPORT=y -+# CONFIG_USB_DEBUG is not set -+ -+# DEPRECATED: See bug 362221. Fix udev. -+# CONFIG_USB_DEVICE_CLASS is not set -+ -+ -+# -+# Miscellaneous USB options -+# -+ -+# Deprecated. -+# CONFIG_USB_DEVICEFS is not set -+ -+CONFIG_USB_DEFAULT_PERSIST=y -+# CONFIG_USB_DYNAMIC_MINORS is not set -+CONFIG_USB_SUSPEND=y -+ -+# -+# USB Host Controller Drivers -+# -+CONFIG_USB_EHCI_ROOT_HUB_TT=y -+CONFIG_USB_EHCI_TT_NEWSCHED=y -+# CONFIG_USB_EHCI_MV is not set -+# CONFIG_USB_EHCI_HCD_PLATFORM is not set -+# CONFIG_USB_ISP116X_HCD is not set -+# CONFIG_USB_ISP1760_HCD is not set -+CONFIG_USB_ISP1362_HCD=m -+CONFIG_USB_FUSBH200_HCD=m -+# CONFIG_USB_FOTG210_HCD is not set -+# CONFIG_USB_GR_UDC is not set -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_HCD_PCI=y -+# CONFIG_USB_OHCI_HCD_SSB is not set -+# CONFIG_USB_HCD_TEST_MODE is not set -+# CONFIG_USB_OHCI_HCD_PLATFORM is not set -+CONFIG_USB_UHCI_HCD=y -+CONFIG_USB_SL811_HCD=m -+CONFIG_USB_SL811_HCD_ISO=y -+# CONFIG_USB_SL811_CS is not set -+# CONFIG_USB_R8A66597_HCD is not set -+CONFIG_USB_XHCI_HCD=y -+# CONFIG_USB_XHCI_HCD_DEBUGGING is not set -+ -+# -+# USB Device Class drivers -+# -+ -+# -+# USB Bluetooth TTY can only be used with disabled Bluetooth subsystem -+# -+CONFIG_USB_ACM=m -+CONFIG_USB_PRINTER=m -+CONFIG_USB_WDM=m -+CONFIG_USB_TMC=m -+# CONFIG_BLK_DEV_UB is not set -+# CONFIG_USB_STORAGE_DEBUG is not set -+CONFIG_USB_STORAGE_CYPRESS_ATACB=m -+CONFIG_USB_STORAGE_DATAFAB=m -+CONFIG_USB_STORAGE_FREECOM=m -+CONFIG_USB_STORAGE_ISD200=m -+CONFIG_USB_STORAGE_SDDR09=m -+CONFIG_USB_STORAGE_SDDR55=m -+CONFIG_USB_STORAGE_JUMPSHOT=m -+CONFIG_USB_STORAGE_USBAT=y -+CONFIG_USB_STORAGE_ONETOUCH=m -+CONFIG_USB_STORAGE_ALAUDA=m -+CONFIG_USB_STORAGE_KARMA=m -+CONFIG_USB_STORAGE_REALTEK=m -+CONFIG_REALTEK_AUTOPM=y -+CONFIG_USB_STORAGE_ENE_UB6250=m -+# CONFIG_USB_LIBUSUAL is not set -+# CONFIG_USB_UAS is not set -+ -+ -+# -+# USB Human Interface Devices (HID) -+# -+CONFIG_USB_HID=y -+ -+CONFIG_HID_SUPPORT=y -+ -+CONFIG_HID=y -+CONFIG_I2C_HID=m -+CONFIG_HID_BATTERY_STRENGTH=y -+# debugging default is y upstream now -+CONFIG_HIDRAW=y -+CONFIG_UHID=m -+CONFIG_HID_PID=y -+CONFIG_LOGITECH_FF=y -+CONFIG_HID_LOGITECH_DJ=m -+CONFIG_LOGIWII_FF=y -+CONFIG_LOGIRUMBLEPAD2_FF=y -+CONFIG_PANTHERLORD_FF=y -+CONFIG_THRUSTMASTER_FF=y -+CONFIG_HID_WACOM=m -+CONFIG_HID_WACOM_POWER_SUPPLY=y -+CONFIG_ZEROPLUS_FF=y -+CONFIG_USB_HIDDEV=y -+CONFIG_USB_IDMOUSE=m -+CONFIG_DRAGONRISE_FF=y -+CONFIG_GREENASIA_FF=y -+CONFIG_SMARTJOYPLUS_FF=y -+CONFIG_LOGIG940_FF=y -+CONFIG_LOGIWHEELS_FF=y -+CONFIG_HID_MAGICMOUSE=y -+CONFIG_HID_MULTITOUCH=m -+CONFIG_HID_NTRIG=y -+CONFIG_HID_QUANTA=y -+CONFIG_HID_PRIMAX=m -+CONFIG_HID_PS3REMOTE=m -+CONFIG_HID_PRODIKEYS=m -+CONFIG_HID_DRAGONRISE=m -+CONFIG_HID_GYRATION=m -+CONFIG_HID_ICADE=m -+CONFIG_HID_TWINHAN=m -+CONFIG_HID_ORTEK=m -+CONFIG_HID_PANTHERLORD=m -+CONFIG_HID_PETALYNX=m -+CONFIG_HID_PICOLCD=m -+CONFIG_HID_RMI=m -+CONFIG_HID_ROCCAT=m -+CONFIG_HID_ROCCAT_KONE=m -+CONFIG_HID_SAMSUNG=m -+CONFIG_HID_SONY=m -+CONFIG_SONY_FF=y -+CONFIG_HID_SUNPLUS=m -+CONFIG_HID_STEELSERIES=m -+CONFIG_HID_GREENASIA=m -+CONFIG_HID_SMARTJOYPLUS=m -+CONFIG_HID_TOPSEED=m -+CONFIG_HID_THINGM=m -+CONFIG_HID_THRUSTMASTER=m -+CONFIG_HID_XINMO=m -+CONFIG_HID_ZEROPLUS=m -+CONFIG_HID_ZYDACRON=m -+CONFIG_HID_SENSOR_HUB=m -+CONFIG_HID_SENSOR_GYRO_3D=m -+CONFIG_HID_SENSOR_MAGNETOMETER_3D=m -+CONFIG_HID_SENSOR_ALS=m -+CONFIG_HID_SENSOR_ACCEL_3D=m -+CONFIG_HID_EMS_FF=m -+CONFIG_HID_ELECOM=m -+CONFIG_HID_ELO=m -+CONFIG_HID_UCLOGIC=m -+CONFIG_HID_WALTOP=m -+CONFIG_HID_ROCCAT_PYRA=m -+CONFIG_HID_ROCCAT_KONEPLUS=m -+CONFIG_HID_ACRUX=m -+CONFIG_HID_ACRUX_FF=y -+CONFIG_HID_KEYTOUCH=m -+CONFIG_HID_LCPOWER=m -+CONFIG_HID_LENOVO_TPKBD=m -+CONFIG_HID_ROCCAT_ARVO=m -+CONFIG_HID_ROCCAT_ISKU=m -+CONFIG_HID_ROCCAT_KOVAPLUS=m -+CONFIG_HID_HOLTEK=m -+CONFIG_HOLTEK_FF=y -+CONFIG_HID_HUION=m -+CONFIG_HID_SPEEDLINK=m -+CONFIG_HID_WIIMOTE=m -+CONFIG_HID_WIIMOTE_EXT=y -+CONFIG_HID_KYE=m -+CONFIG_HID_SAITEK=m -+CONFIG_HID_TIVO=m -+CONFIG_HID_GENERIC=y -+CONFIG_HID_AUREAL=m -+CONFIG_HID_APPLEIR=m -+ -+ -+# -+# USB Imaging devices -+# -+CONFIG_USB_MDC800=m -+CONFIG_USB_MICROTEK=m -+ -+# -+# USB Multimedia devices -+# -+ -+CONFIG_USB_DSBR=m -+# CONFIG_USB_ET61X251 is not set -+CONFIG_USB_M5602=m -+CONFIG_USB_STV06XX=m -+CONFIG_USB_GSPCA=m -+CONFIG_USB_GSPCA_MR97310A=m -+CONFIG_USB_GSPCA_BENQ=m -+CONFIG_USB_GSPCA_CONEX=m -+CONFIG_USB_GSPCA_CPIA1=m -+CONFIG_USB_GSPCA_ETOMS=m -+CONFIG_USB_GSPCA_FINEPIX=m -+CONFIG_USB_GSPCA_MARS=m -+CONFIG_USB_GSPCA_OV519=m -+CONFIG_USB_GSPCA_OV534=m -+CONFIG_USB_GSPCA_OV534_9=m -+CONFIG_USB_GSPCA_PAC207=m -+CONFIG_USB_GSPCA_PAC7311=m -+CONFIG_USB_GSPCA_SN9C2028=m -+CONFIG_USB_GSPCA_SN9C20X=m -+CONFIG_USB_GSPCA_SONIXB=m -+CONFIG_USB_GSPCA_SONIXJ=m -+CONFIG_USB_GSPCA_SPCA500=m -+CONFIG_USB_GSPCA_SPCA501=m -+CONFIG_USB_GSPCA_SPCA505=m -+CONFIG_USB_GSPCA_SPCA506=m -+CONFIG_USB_GSPCA_SPCA508=m -+CONFIG_USB_GSPCA_SPCA561=m -+CONFIG_USB_GSPCA_STK014=m -+CONFIG_USB_GSPCA_STK1135=m -+CONFIG_USB_GSPCA_SUNPLUS=m -+CONFIG_USB_GSPCA_T613=m -+CONFIG_USB_GSPCA_TOPRO=m -+CONFIG_USB_GSPCA_TV8532=m -+CONFIG_USB_GSPCA_VC032X=m -+CONFIG_USB_GSPCA_ZC3XX=m -+CONFIG_USB_GSPCA_SQ905=m -+CONFIG_USB_GSPCA_SQ905C=m -+CONFIG_USB_GSPCA_PAC7302=m -+CONFIG_USB_GSPCA_STV0680=m -+CONFIG_USB_GL860=m -+CONFIG_USB_GSPCA_JEILINJ=m -+CONFIG_USB_GSPCA_JL2005BCD=m -+CONFIG_USB_GSPCA_KONICA=m -+CONFIG_USB_GSPCA_XIRLINK_CIT=m -+CONFIG_USB_GSPCA_SPCA1528=m -+CONFIG_USB_GSPCA_SQ930X=m -+CONFIG_USB_GSPCA_NW80X=m -+CONFIG_USB_GSPCA_VICAM=m -+CONFIG_USB_GSPCA_KINECT=m -+CONFIG_USB_GSPCA_SE401=m -+ -+CONFIG_USB_S2255=m -+# CONFIG_VIDEO_SH_MOBILE_CEU is not set -+# CONFIG_VIDEO_SH_MOBILE_CSI2 is not set -+# CONFIG_USB_SN9C102 is not set -+CONFIG_USB_ZR364XX=m -+ -+# -+# USB Network adaptors -+# -+CONFIG_USB_CATC=m -+CONFIG_USB_HSO=m -+CONFIG_USB_KAWETH=m -+CONFIG_USB_PEGASUS=m -+CONFIG_USB_RTL8150=m -+CONFIG_USB_RTL8152=m -+CONFIG_USB_USBNET=m -+CONFIG_USB_SPEEDTOUCH=m -+CONFIG_USB_NET_AX8817X=m -+CONFIG_USB_NET_AX88179_178A=m -+CONFIG_USB_NET_DM9601=m -+CONFIG_USB_NET_SR9700=m -+CONFIG_USB_NET_SMSC95XX=m -+CONFIG_USB_NET_GL620A=m -+CONFIG_USB_NET_NET1080=m -+CONFIG_USB_NET_PLUSB=m -+CONFIG_USB_NET_MCS7830=m -+CONFIG_USB_NET_RNDIS_HOST=m -+CONFIG_USB_NET_CDC_SUBSET=m -+CONFIG_USB_NET_CDC_EEM=m -+CONFIG_USB_NET_CDC_NCM=m -+CONFIG_USB_NET_HUAWEI_CDC_NCM=m -+CONFIG_USB_NET_CDC_MBIM=m -+CONFIG_USB_NET_ZAURUS=m -+CONFIG_USB_NET_CX82310_ETH=m -+CONFIG_USB_NET_INT51X1=m -+CONFIG_USB_CDC_PHONET=m -+CONFIG_USB_IPHETH=m -+CONFIG_USB_SIERRA_NET=m -+CONFIG_USB_VL600=m -+ -+# -+# USB Host-to-Host Cables -+# -+CONFIG_USB_AN2720=y -+CONFIG_USB_BELKIN=y -+ -+# -+# Intelligent USB Devices/Gadgets -+# -+CONFIG_USB_ARMLINUX=y -+CONFIG_USB_EPSON2888=y -+CONFIG_USB_KC2190=y -+ -+# CONFIG_USB_MUSB_HDRC is not set -+ -+# -+# USB port drivers -+# -+CONFIG_USB_USS720=m -+ -+# -+# USB Serial Converter support -+# -+CONFIG_USB_SERIAL=y -+CONFIG_USB_SERIAL_GENERIC=y -+CONFIG_USB_SERIAL_SIMPLE=m -+CONFIG_USB_SERIAL_AIRCABLE=m -+CONFIG_USB_SERIAL_ARK3116=m -+CONFIG_USB_SERIAL_BELKIN=m -+CONFIG_USB_SERIAL_CH341=m -+CONFIG_USB_SERIAL_CYPRESS_M8=m -+CONFIG_USB_SERIAL_CYBERJACK=m -+CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m -+CONFIG_USB_SERIAL_CP210X=m -+CONFIG_USB_SERIAL_QUALCOMM=m -+CONFIG_USB_SERIAL_SYMBOL=m -+CONFIG_USB_SERIAL_EDGEPORT=m -+CONFIG_USB_SERIAL_EDGEPORT_TI=m -+CONFIG_USB_SERIAL_EMPEG=m -+# CONFIG_USB_SERIAL_F81232 is not set -+CONFIG_USB_SERIAL_FTDI_SIO=m -+CONFIG_USB_SERIAL_FUNSOFT=m -+CONFIG_USB_SERIAL_GARMIN=m -+CONFIG_USB_SERIAL_HP4X=m -+CONFIG_USB_SERIAL_IPAQ=m -+CONFIG_USB_SERIAL_IPW=m -+CONFIG_USB_SERIAL_IR=m -+CONFIG_USB_SERIAL_IUU=m -+CONFIG_USB_SERIAL_KEYSPAN_PDA=m -+CONFIG_USB_SERIAL_KEYSPAN=m -+CONFIG_USB_SERIAL_KEYSPAN_MPR=y -+CONFIG_USB_SERIAL_KEYSPAN_USA28=y -+CONFIG_USB_SERIAL_KEYSPAN_USA28X=y -+CONFIG_USB_SERIAL_KEYSPAN_USA28XA=y -+CONFIG_USB_SERIAL_KEYSPAN_USA28XB=y -+CONFIG_USB_SERIAL_KEYSPAN_USA19=y -+CONFIG_USB_SERIAL_KEYSPAN_USA18X=y -+CONFIG_USB_SERIAL_KEYSPAN_USA19W=y -+CONFIG_USB_SERIAL_KEYSPAN_USA19QW=y -+CONFIG_USB_SERIAL_KEYSPAN_USA19QI=y -+CONFIG_USB_SERIAL_KEYSPAN_USA49W=y -+CONFIG_USB_SERIAL_KEYSPAN_USA49WLC=y -+CONFIG_USB_SERIAL_KLSI=m -+CONFIG_USB_SERIAL_KOBIL_SCT=m -+CONFIG_USB_SERIAL_MCT_U232=m -+# CONFIG_USB_SERIAL_METRO is not set -+CONFIG_USB_SERIAL_MOS7720=m -+CONFIG_USB_SERIAL_MOS7715_PARPORT=y -+# CONFIG_USB_SERIAL_ZIO is not set -+# CONFIG_USB_SERIAL_WISHBONE is not set -+# CONFIG_USB_SERIAL_ZTE is not set -+CONFIG_USB_SERIAL_MOS7840=m -+CONFIG_USB_SERIAL_MOTOROLA=m -+# CONFIG_USB_SERIAL_MXUPORT is not set -+CONFIG_USB_SERIAL_NAVMAN=m -+CONFIG_USB_SERIAL_OPTION=m -+CONFIG_USB_SERIAL_OTI6858=m -+CONFIG_USB_SERIAL_OPTICON=m -+CONFIG_USB_SERIAL_OMNINET=m -+CONFIG_USB_SERIAL_PL2303=m -+# CONFIG_USB_SERIAL_QUATECH2 is not set -+CONFIG_USB_SERIAL_SAFE=m -+CONFIG_USB_SERIAL_SAFE_PADDED=y -+CONFIG_USB_SERIAL_SIERRAWIRELESS=m -+CONFIG_USB_SERIAL_SIEMENS_MPI=m -+CONFIG_USB_SERIAL_SPCP8X5=m -+CONFIG_USB_SERIAL_TI=m -+CONFIG_USB_SERIAL_VISOR=m -+CONFIG_USB_SERIAL_WHITEHEAT=m -+CONFIG_USB_SERIAL_XIRCOM=m -+CONFIG_USB_SERIAL_QCAUX=m -+CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m -+CONFIG_USB_SERIAL_XSENS_MT=m -+CONFIG_USB_SERIAL_DEBUG=m -+CONFIG_USB_SERIAL_SSU100=m -+CONFIG_USB_SERIAL_QT2=m -+CONFIG_USB_SERIAL_FLASHLOADER=m -+CONFIG_USB_SERIAL_SUUNTO=m -+CONFIG_USB_SERIAL_CONSOLE=y -+ -+CONFIG_USB_EZUSB=y -+CONFIG_USB_EMI62=m -+CONFIG_USB_LED=m -+# CONFIG_USB_CYPRESS_CY7C63 is not set -+ -+# -+# USB Miscellaneous drivers -+# -+ -+CONFIG_USB_ADUTUX=m -+CONFIG_USB_SEVSEG=m -+CONFIG_USB_ALI_M5632=y -+CONFIG_USB_APPLEDISPLAY=m -+ -+# Physical Layer USB driver -+# CONFIG_USB_OTG_FSM is not set -+ -+# CONFIG_GENERIC_PHY is not set -+# CONFIG_PHY_EXYNOS_MIPI_VIDEO is not set -+# CONFIG_PHY_EXYNOS_DP_VIDEO is not set -+# CONFIG_OMAP_USB2 is not set -+# CONFIG_OMAP_USB3 is not set -+# CONFIG_OMAP_CONTROL_USB is not set -+# CONFIG_AM335X_PHY_USB is not set -+# CONFIG_SAMSUNG_USBPHY is not set -+# CONFIG_SAMSUNG_USB2PHY is not set -+# CONFIG_SAMSUNG_USB3PHY is not set -+# CONFIG_BCM_KONA_USB2_PHY is not set -+CONFIG_USB_RCAR_PHY=m -+CONFIG_USB_ATM=m -+CONFIG_USB_CXACRU=m -+# CONFIG_USB_C67X00_HCD is not set -+# CONFIG_USB_CYTHERM is not set -+CONFIG_USB_EMI26=m -+CONFIG_USB_FTDI_ELAN=m -+CONFIG_USB_FILE_STORAGE=m -+# CONFIG_USB_FILE_STORAGE_TEST is not set -+# CONFIG_USB_DWC3 is not set -+# CONFIG_USB_GADGETFS is not set -+# CONFIG_USB_OXU210HP_HCD is not set -+CONFIG_USB_IOWARRIOR=m -+CONFIG_USB_ISIGHTFW=m -+CONFIG_USB_YUREX=m -+CONFIG_USB_EZUSB_FX2=m -+CONFIG_USB_HSIC_USB3503=m -+CONFIG_USB_LCD=m -+CONFIG_USB_LD=m -+CONFIG_USB_LEGOTOWER=m -+CONFIG_USB_MON=y -+CONFIG_USB_PWC=m -+CONFIG_USB_PWC_INPUT_EVDEV=y -+# CONFIG_USB_PWC_DEBUG is not set -+# CONFIG_USB_RIO500 is not set -+CONFIG_USB_SISUSBVGA=m -+CONFIG_USB_SISUSBVGA_CON=y -+CONFIG_RADIO_SI470X=y -+CONFIG_USB_KEENE=m -+CONFIG_USB_MA901=m -+CONFIG_USB_SI470X=m -+CONFIG_I2C_SI470X=m -+CONFIG_RADIO_SI4713=m -+# CONFIG_RADIO_TEF6862 is not set -+CONFIG_USB_MR800=m -+CONFIG_USB_STKWEBCAM=m -+# CONFIG_USB_TEST is not set -+# CONFIG_USB_EHSET_TEST_FIXTURE is not set -+CONFIG_USB_TRANCEVIBRATOR=m -+CONFIG_USB_U132_HCD=m -+CONFIG_USB_UEAGLEATM=m -+CONFIG_USB_XUSBATM=m -+ -+# CONFIG_USB_DWC2 is not set -+ -+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -+ -+# CONFIG_USB_ISP1301 is not set -+ -+# CONFIG_USB_OTG is not set -+ -+# -+# Sonics Silicon Backplane -+# -+CONFIG_SSB=m -+CONFIG_SSB_PCIHOST=y -+CONFIG_SSB_SDIOHOST=y -+CONFIG_SSB_PCMCIAHOST=y -+# CONFIG_SSB_SILENT is not set -+# CONFIG_SSB_DEBUG is not set -+CONFIG_SSB_DRIVER_PCICORE=y -+CONFIG_SSB_DRIVER_GPIO=y -+ -+# Multifunction USB devices -+# CONFIG_MFD_PCF50633 is not set -+CONFIG_PCF50633_ADC=m -+CONFIG_PCF50633_GPIO=m -+# CONFIG_AB3100_CORE is not set -+CONFIG_INPUT_PCF50633_PMU=m -+CONFIG_INPUT_GPIO_ROTARY_ENCODER=m -+ -+CONFIG_MFD_SUPPORT=y -+CONFIG_MFD_VX855=m -+CONFIG_MFD_SM501=m -+CONFIG_MFD_SM501_GPIO=y -+CONFIG_MFD_RTSX_PCI=m -+# CONFIG_MFD_TI_AM335X_TSCADC is not set -+CONFIG_MFD_VIPERBOARD=m -+# CONFIG_MFD_RETU is not set -+# CONFIG_MFD_TC6393XB is not set -+# CONFIG_MFD_WM8400 is not set -+# CONFIG_MFD_WM8350_I2C is not set -+# CONFIG_MFD_WM8350 is not set -+# CONFIG_MFD_WM831X is not set -+# CONFIG_AB3100_OTP is not set -+# CONFIG_MFD_TIMBERDALE is not set -+# CONFIG_MFD_WM8994 is not set -+# CONFIG_MFD_88PM860X is not set -+# CONFIG_LPC_SCH is not set -+# CONFIG_LPC_ICH is not set -+# CONFIG_HTC_I2CPLD is not set -+# CONFIG_MFD_MAX8925 is not set -+# CONFIG_MFD_ASIC3 is not set -+# CONFIG_MFD_AS3722 is not set -+# CONFIG_HTC_EGPIO is not set -+# CONFIG_TPS6507X is not set -+# CONFIG_ABX500_CORE is not set -+# CONFIG_MFD_RDC321X is not set -+# CONFIG_MFD_JANZ_CMODIO is not set -+# CONFIG_MFD_KEMPLD is not set -+# CONFIG_MFD_WM831X_I2C is not set -+# CONFIG_MFD_CS5535 is not set -+# CONFIG_MFD_STMPE is not set -+# CONFIG_MFD_MAX8998 is not set -+# CONFIG_MFD_TPS6586X is not set -+# CONFIG_MFD_TC3589X is not set -+# CONFIG_MFD_WL1273_CORE is not set -+# CONFIG_MFD_TPS65217 is not set -+# CONFIG_MFD_LM3533 is not set -+# CONFIG_MFD_ARIZONA is not set -+# CONFIG_MFD_ARIZONA_I2C is not set -+# CONFIG_MFD_CROS_EC is not set -+# CONFIG_MFD_TPS65912 is not set -+# CONFIG_MFD_SYSCON is not set -+# CONFIG_MFD_DA9063 is not set -+# CONFIG_MFD_LP3943 is not set -+ -+# -+# File systems -+# -+CONFIG_MISC_FILESYSTEMS=y -+ -+# ext4 is used for ext2 and ext3 filesystems -+CONFIG_JBD2=y -+CONFIG_FS_MBCACHE=y -+CONFIG_REISERFS_FS=m -+# CONFIG_REISERFS_CHECK is not set -+CONFIG_REISERFS_PROC_INFO=y -+CONFIG_REISERFS_FS_XATTR=y -+CONFIG_REISERFS_FS_POSIX_ACL=y -+CONFIG_REISERFS_FS_SECURITY=y -+CONFIG_JFS_FS=m -+# CONFIG_JFS_DEBUG is not set -+# CONFIG_JFS_STATISTICS is not set -+CONFIG_JFS_POSIX_ACL=y -+CONFIG_JFS_SECURITY=y -+CONFIG_XFS_FS=m -+# CONFIG_XFS_DEBUG is not set -+# CONFIG_XFS_RT is not set -+CONFIG_XFS_QUOTA=y -+CONFIG_XFS_POSIX_ACL=y -+CONFIG_MINIX_FS=m -+CONFIG_ROMFS_FS=m -+# CONFIG_QFMT_V1 is not set -+CONFIG_QFMT_V2=y -+CONFIG_QUOTACTL=y -+CONFIG_DNOTIFY=y -+# Autofsv3 is obsolete. -+# systemd is dependant upon AUTOFS, so build it in. -+# CONFIG_EXOFS_FS is not set -+# CONFIG_EXOFS_DEBUG is not set -+CONFIG_NILFS2_FS=m -+# CONFIG_LOGFS is not set -+CONFIG_CEPH_FS=m -+CONFIG_CEPH_FSCACHE=y -+CONFIG_BLK_DEV_RBD=m -+CONFIG_CEPH_LIB=m -+CONFIG_CEPH_FS_POSIX_ACL=y -+# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set -+ -+CONFIG_FSCACHE=m -+CONFIG_FSCACHE_STATS=y -+# CONFIG_FSCACHE_HISTOGRAM is not set -+# CONFIG_FSCACHE_DEBUG is not set -+CONFIG_FSCACHE_OBJECT_LIST=y -+ -+CONFIG_CACHEFILES=m -+# CONFIG_CACHEFILES_DEBUG is not set -+# CONFIG_CACHEFILES_HISTOGRAM is not set -+ -+# -+# CD-ROM/DVD Filesystems -+# -+ -+# -+# DOS/FAT/NT Filesystems -+# -+CONFIG_FAT_FS=m -+CONFIG_FAT_DEFAULT_CODEPAGE=437 -+CONFIG_FAT_DEFAULT_IOCHARSET="ascii" -+# CONFIG_NTFS_FS is not set -+ -+# -+# Pseudo filesystems -+# -+CONFIG_PROC_FS=y -+CONFIG_PROC_KCORE=y -+CONFIG_PROC_VMCORE=y -+CONFIG_TMPFS_POSIX_ACL=y -+CONFIG_TMPFS_XATTR=y -+CONFIG_HUGETLBFS=y -+CONFIG_HUGETLB_PAGE=y -+# CONFIG_DEBUG_FS is not set -+ -+# -+# Miscellaneous filesystems -+# -+# CONFIG_ADFS_FS is not set -+CONFIG_AFFS_FS=m -+CONFIG_ECRYPT_FS=m -+# CONFIG_ECRYPT_FS_MESSAGING is not set -+CONFIG_HFS_FS=m -+CONFIG_HFSPLUS_FS=m -+# CONFIG_HFSPLUS_FS_POSIX_ACL is not set -+CONFIG_BEFS_FS=m -+# CONFIG_BEFS_DEBUG is not set -+# CONFIG_BFS_FS is not set -+# CONFIG_EFS_FS is not set -+ -+CONFIG_CRAMFS=m -+CONFIG_SQUASHFS=m -+CONFIG_SQUASHFS_XATTR=y -+CONFIG_SQUASHFS_LZO=y -+CONFIG_SQUASHFS_XZ=y -+CONFIG_SQUASHFS_ZLIB=y -+# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set -+# CONFIG_SQUASHFS_EMBEDDED is not set -+# CONFIG_VXFS_FS is not set -+# CONFIG_HPFS_FS is not set -+# CONFIG_QNX4FS_FS is not set -+# CONFIG_QNX6FS_FS is not set -+CONFIG_SYSV_FS=m -+CONFIG_UFS_FS=m -+# CONFIG_UFS_FS_WRITE is not set -+# CONFIG_UFS_DEBUG is not set -+CONFIG_9P_FS=m -+CONFIG_9P_FSCACHE=y -+CONFIG_9P_FS_POSIX_ACL=y -+CONFIG_9P_FS_SECURITY=y -+# CONFIG_OMFS_FS is not set -+CONFIG_CUSE=m -+# CONFIG_F2FS_FS is not set -+ -+# -+# Network File Systems -+# -+CONFIG_NETWORK_FILESYSTEMS=y -+# CONFIG_NFS_V2 is not set -+CONFIG_NFS_V3=y -+CONFIG_NFS_SWAP=y -+CONFIG_NFS_V4_1=y -+CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" -+# CONFIG_NFS_V4_1_MIGRATION is not set -+CONFIG_NFS_V4_2=y -+CONFIG_NFSD=m -+CONFIG_NFSD_V3=y -+CONFIG_NFSD_V3_ACL=y -+CONFIG_NFSD_V4=y -+CONFIG_NFSD_V4_SECURITY_LABEL=y -+CONFIG_NFS_FSCACHE=y -+# CONFIG_NFS_USE_LEGACY_DNS is not set -+CONFIG_PNFS_OBJLAYOUT=m -+CONFIG_PNFS_BLOCK=m -+CONFIG_LOCKD=m -+CONFIG_LOCKD_V4=y -+CONFIG_EXPORTFS=y -+CONFIG_SUNRPC=m -+CONFIG_SUNRPC_GSS=m -+CONFIG_SUNRPC_XPRT_RDMA=m -+CONFIG_SUNRPC_DEBUG=y -+CONFIG_RPCSEC_GSS_KRB5=m -+CONFIG_CIFS=m -+CONFIG_CIFS_STATS=y -+# CONFIG_CIFS_STATS2 is not set -+CONFIG_CIFS_SMB2=y -+CONFIG_CIFS_UPCALL=y -+CONFIG_CIFS_XATTR=y -+CONFIG_CIFS_POSIX=y -+CONFIG_CIFS_FSCACHE=y -+CONFIG_CIFS_ACL=y -+CONFIG_CIFS_WEAK_PW_HASH=y -+CONFIG_CIFS_DEBUG=y -+# CONFIG_CIFS_DEBUG2 is not set -+CONFIG_CIFS_DFS_UPCALL=y -+CONFIG_CIFS_NFSD_EXPORT=y -+CONFIG_NCP_FS=m -+CONFIG_NCPFS_PACKET_SIGNING=y -+CONFIG_NCPFS_IOCTL_LOCKING=y -+CONFIG_NCPFS_STRONG=y -+CONFIG_NCPFS_NFS_NS=y -+CONFIG_NCPFS_OS2_NS=y -+CONFIG_NCPFS_SMALLDOS=y -+CONFIG_NCPFS_NLS=y -+CONFIG_NCPFS_EXTRAS=y -+CONFIG_CODA_FS=m -+# CONFIG_AFS_FS is not set -+# CONFIG_AF_RXRPC is not set -+ -+CONFIG_OCFS2_FS=m -+# CONFIG_OCFS2_DEBUG_FS is not set -+# CONFIG_OCFS2_DEBUG_MASKLOG is not set -+CONFIG_OCFS2_FS_O2CB=m -+CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m -+# CONFIG_OCFS2_FS_STATS is not set -+ -+CONFIG_BTRFS_FS=m -+CONFIG_BTRFS_FS_POSIX_ACL=y -+# Maybe see if we want this on for debug kernels? -+# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set -+# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set -+# CONFIG_BTRFS_DEBUG is not set -+# CONFIG_BTRFS_ASSERT is not set -+ -+CONFIG_CONFIGFS_FS=y -+ -+CONFIG_DLM=m -+CONFIG_DLM_DEBUG=y -+CONFIG_GFS2_FS=m -+CONFIG_GFS2_FS_LOCKING_DLM=y -+ -+ -+CONFIG_UBIFS_FS_XATTR=y -+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set -+# CONFIG_UBIFS_FS_DEBUG is not set -+ -+# -+# Partition Types -+# -+CONFIG_PARTITION_ADVANCED=y -+# CONFIG_ACORN_PARTITION is not set -+CONFIG_AIX_PARTITION=y -+CONFIG_AMIGA_PARTITION=y -+# CONFIG_ATARI_PARTITION is not set -+CONFIG_BSD_DISKLABEL=y -+CONFIG_EFI_PARTITION=y -+CONFIG_KARMA_PARTITION=y -+CONFIG_LDM_PARTITION=y -+# CONFIG_LDM_DEBUG is not set -+CONFIG_MAC_PARTITION=y -+CONFIG_MSDOS_PARTITION=y -+CONFIG_MINIX_SUBPARTITION=y -+CONFIG_OSF_PARTITION=y -+CONFIG_SGI_PARTITION=y -+CONFIG_SOLARIS_X86_PARTITION=y -+CONFIG_SUN_PARTITION=y -+# CONFIG_SYSV68_PARTITION is not set -+CONFIG_UNIXWARE_DISKLABEL=y -+# CONFIG_ULTRIX_PARTITION is not set -+# CONFIG_CMDLINE_PARTITION is not set -+ -+CONFIG_NLS=y -+ -+# -+# Native Language Support -+# -+CONFIG_NLS_CODEPAGE_737=m -+CONFIG_NLS_CODEPAGE_775=m -+CONFIG_NLS_CODEPAGE_850=m -+CONFIG_NLS_CODEPAGE_852=m -+CONFIG_NLS_CODEPAGE_855=m -+CONFIG_NLS_CODEPAGE_857=m -+CONFIG_NLS_CODEPAGE_860=m -+CONFIG_NLS_CODEPAGE_861=m -+CONFIG_NLS_CODEPAGE_862=m -+CONFIG_NLS_CODEPAGE_863=m -+CONFIG_NLS_CODEPAGE_864=m -+CONFIG_NLS_CODEPAGE_865=m -+CONFIG_NLS_CODEPAGE_866=m -+CONFIG_NLS_CODEPAGE_869=m -+CONFIG_NLS_CODEPAGE_936=m -+CONFIG_NLS_CODEPAGE_950=m -+CONFIG_NLS_CODEPAGE_932=m -+CONFIG_NLS_CODEPAGE_949=m -+CONFIG_NLS_CODEPAGE_874=m -+CONFIG_NLS_ISO8859_8=m -+CONFIG_NLS_CODEPAGE_1250=m -+CONFIG_NLS_CODEPAGE_1251=m -+CONFIG_NLS_ISO8859_2=m -+CONFIG_NLS_ISO8859_3=m -+CONFIG_NLS_ISO8859_4=m -+CONFIG_NLS_ISO8859_5=m -+CONFIG_NLS_ISO8859_6=m -+CONFIG_NLS_ISO8859_7=m -+CONFIG_NLS_ISO8859_9=m -+CONFIG_NLS_ISO8859_13=m -+CONFIG_NLS_ISO8859_14=m -+CONFIG_NLS_KOI8_R=m -+CONFIG_NLS_KOI8_U=m -+CONFIG_NLS_MAC_ROMAN=m -+CONFIG_NLS_MAC_CELTIC=m -+CONFIG_NLS_MAC_CENTEURO=m -+CONFIG_NLS_MAC_CROATIAN=m -+CONFIG_NLS_MAC_CYRILLIC=m -+CONFIG_NLS_MAC_GAELIC=m -+CONFIG_NLS_MAC_GREEK=m -+CONFIG_NLS_MAC_ICELAND=m -+CONFIG_NLS_MAC_INUIT=m -+CONFIG_NLS_MAC_ROMANIAN=m -+CONFIG_NLS_MAC_TURKISH=m -+ -+# -+# Profiling support -+# -+CONFIG_PROFILING=y -+CONFIG_OPROFILE=m -+CONFIG_OPROFILE_EVENT_MULTIPLEX=y -+ -+# -+# Kernel hacking -+# -+CONFIG_DEBUG_KERNEL=y -+CONFIG_FRAME_WARN=1024 -+CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x0 -+# CONFIG_DEBUG_INFO is not set -+CONFIG_FRAME_POINTER=y -+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -+# CONFIG_DEBUG_DRIVER is not set -+CONFIG_HEADERS_CHECK=y -+# CONFIG_LKDTM is not set -+# CONFIG_NOTIFIER_ERROR_INJECTION is not set -+# CONFIG_READABLE_ASM is not set -+ -+# CONFIG_RT_MUTEX_TESTER is not set -+# CONFIG_DEBUG_LOCKDEP is not set -+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -+ -+# DEBUG options that don't get enabled/disabled with 'make debug/release' -+ -+# This generates a huge amount of dmesg spew -+# CONFIG_DEBUG_KOBJECT is not set -+# -+# This breaks booting until the module patches are in-tree -+# CONFIG_DEBUG_KOBJECT_RELEASE is not set -+# -+# -+# These debug options are deliberatly left on (even in 'make release' kernels). -+# They aren't that much of a performance impact, and the value -+# from getting useful bug-reports makes it worth leaving them on. -+# CONFIG_DEBUG_HIGHMEM is not set -+# CONFIG_DEBUG_SHIRQ is not set -+CONFIG_BOOT_PRINTK_DELAY=y -+CONFIG_DEBUG_DEVRES=y -+CONFIG_DEBUG_RODATA_TEST=y -+CONFIG_DEBUG_NX_TEST=m -+CONFIG_DEBUG_SET_MODULE_RONX=y -+CONFIG_DEBUG_BOOT_PARAMS=y -+# CONFIG_DEBUG_VM is not set -+# CONFIG_DEBUG_STRICT_USER_COPY_CHECKS is not set -+CONFIG_LOCKUP_DETECTOR=y -+# CONFIG_DEBUG_INFO_REDUCED is not set -+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -+# CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set -+# CONFIG_PANIC_ON_OOPS is not set -+CONFIG_PANIC_TIMEOUT=0 -+CONFIG_ATOMIC64_SELFTEST=y -+CONFIG_MEMORY_FAILURE=y -+CONFIG_HWPOISON_INJECT=m -+CONFIG_CROSS_MEMORY_ATTACH=y -+# CONFIG_DEBUG_SECTION_MISMATCH is not set -+# CONFIG_BACKTRACE_SELF_TEST is not set -+CONFIG_RESOURCE_COUNTERS=y -+# CONFIG_DEBUG_VIRTUAL is not set -+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -+CONFIG_EARLY_PRINTK_DBGP=y -+# CONFIG_PAGE_POISONING is not set -+# CONFIG_CRASH_DUMP is not set -+# CONFIG_CRASH is not set -+# CONFIG_GCOV_KERNEL is not set -+# CONFIG_RAMOOPS is not set -+ -+ -+# -+# Security options -+# -+CONFIG_SECURITY=y -+# CONFIG_SECURITY_DMESG_RESTRICT is not set -+CONFIG_SECURITY_NETWORK=y -+CONFIG_SECURITY_NETWORK_XFRM=y -+# CONFIG_SECURITY_PATH is not set -+CONFIG_SECURITY_SELINUX=y -+CONFIG_SECURITY_SELINUX_BOOTPARAM=y -+CONFIG_SECURITY_SELINUX_DISABLE=y -+CONFIG_SECURITY_SELINUX_DEVELOP=y -+CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=1 -+CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 -+CONFIG_SECURITY_SELINUX_AVC_STATS=y -+# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set -+# CONFIG_SECURITY_SMACK is not set -+# CONFIG_SECURITY_TOMOYO is not set -+# CONFIG_SECURITY_APPARMOR is not set -+# CONFIG_SECURITY_YAMA is not set -+CONFIG_AUDIT=y -+CONFIG_AUDITSYSCALL=y -+# http://lists.fedoraproject.org/pipermail/kernel/2013-February/004125.html -+CONFIG_AUDIT_LOGINUID_IMMUTABLE=y -+ -+CONFIG_SECCOMP=y -+ -+# CONFIG_SSBI is not set -+ -+# -+# Cryptographic options -+# -+CONFIG_CRYPTO=y -+CONFIG_CRYPTO_FIPS=y -+CONFIG_CRYPTO_USER_API_HASH=y -+CONFIG_CRYPTO_USER_API_SKCIPHER=y -+CONFIG_CRYPTO_MANAGER=y -+# Note, CONFIG_CRYPTO_MANAGER_DISABLE_TESTS needs to be unset, or FIPS will be disabled. -+# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set -+CONFIG_CRYPTO_HW=y -+CONFIG_CRYPTO_BLKCIPHER=y -+# CONFIG_CRYPTO_CRYPTD is not set -+CONFIG_CRYPTO_AES=y -+CONFIG_CRYPTO_ARC4=m -+CONFIG_CRYPTO_ANUBIS=m -+CONFIG_CRYPTO_AUTHENC=m -+CONFIG_CRYPTO_CAST5=m -+CONFIG_CRYPTO_CAST6=m -+CONFIG_CRYPTO_CRC32C=y -+CONFIG_CRYPTO_CRC32=m -+CONFIG_CRYPTO_CTR=y -+CONFIG_CRYPTO_DEFLATE=m -+CONFIG_CRYPTO_FCRYPT=m -+CONFIG_CRYPTO_GF128MUL=m -+CONFIG_CRYPTO_CMAC=m -+CONFIG_CRYPTO_HMAC=y -+CONFIG_CRYPTO_KHAZAD=m -+CONFIG_CRYPTO_LZO=m -+CONFIG_CRYPTO_LZ4=m -+CONFIG_CRYPTO_LZ4HC=m -+CONFIG_CRYPTO_NULL=m -+CONFIG_CRYPTO_PCBC=m -+CONFIG_CRYPTO_SALSA20=m -+CONFIG_CRYPTO_SALSA20_586=m -+CONFIG_CRYPTO_SEED=m -+CONFIG_CRYPTO_SEQIV=m -+CONFIG_CRYPTO_SERPENT=m -+CONFIG_CRYPTO_TEA=m -+CONFIG_CRYPTO_XCBC=m -+CONFIG_CRYPTO_VMAC=m -+CONFIG_CRYPTO_CRC32C_INTEL=m -+CONFIG_CRYPTO_GHASH=m -+CONFIG_CRYPTO_DEV_HIFN_795X=m -+CONFIG_CRYPTO_DEV_HIFN_795X_RNG=y -+CONFIG_CRYPTO_PCRYPT=m -+ -+ -+ -+# Random number generation -+ -+# -+# Library routines -+# -+CONFIG_CRC16=y -+CONFIG_CRC32=m -+# CONFIG_CRC32_SELFTEST is not set -+CONFIG_CRC_ITU_T=m -+CONFIG_CRC8=m -+# CONFIG_RANDOM32_SELFTEST is not set -+CONFIG_CORDIC=m -+# CONFIG_DDR is not set -+ -+CONFIG_CRYPTO_ZLIB=m -+CONFIG_ZLIB_INFLATE=y -+CONFIG_ZLIB_DEFLATE=m -+ -+CONFIG_INITRAMFS_SOURCE="" -+CONFIG_KEYS=y -+CONFIG_PERSISTENT_KEYRINGS=y -+CONFIG_BIG_KEYS=y -+CONFIG_TRUSTED_KEYS=m -+CONFIG_ENCRYPTED_KEYS=m -+CONFIG_KEYS_DEBUG_PROC_KEYS=y -+CONFIG_CDROM_PKTCDVD=m -+CONFIG_CDROM_PKTCDVD_BUFFERS=8 -+# CONFIG_CDROM_PKTCDVD_WCACHE is not set -+ -+CONFIG_ATA_OVER_ETH=m -+CONFIG_BACKLIGHT_LCD_SUPPORT=y -+CONFIG_BACKLIGHT_CLASS_DEVICE=m -+# CONFIG_BACKLIGHT_GENERIC is not set -+CONFIG_BACKLIGHT_PROGEAR=m -+ -+CONFIG_LCD_CLASS_DEVICE=m -+CONFIG_LCD_PLATFORM=m -+ -+CONFIG_FAIR_GROUP_SCHED=y -+CONFIG_CFS_BANDWIDTH=y -+CONFIG_SCHED_OMIT_FRAME_POINTER=y -+CONFIG_RT_GROUP_SCHED=y -+CONFIG_SCHED_AUTOGROUP=y -+ -+CONFIG_CPUSETS=y -+CONFIG_PROC_PID_CPUSET=y -+ -+# CONFIG_CGROUP_DEBUG is not set -+CONFIG_CGROUP_CPUACCT=y -+CONFIG_CGROUP_DEVICE=y -+CONFIG_CGROUP_FREEZER=y -+CONFIG_CGROUP_SCHED=y -+CONFIG_MEMCG=y -+CONFIG_MEMCG_SWAP=y -+CONFIG_MEMCG_SWAP_ENABLED=y -+CONFIG_MEMCG_KMEM=y -+# CONFIG_CGROUP_HUGETLB is not set -+CONFIG_CGROUP_PERF=y -+CONFIG_CGROUP_NET_PRIO=m -+# CONFIG_CGROUP_NET_CLASSID is not set -+CONFIG_BLK_CGROUP=y -+ -+# CONFIG_SYSFS_DEPRECATED is not set -+# CONFIG_SYSFS_DEPRECATED_V2 is not set -+ -+CONFIG_PRINTK_TIME=y -+ -+CONFIG_ENABLE_MUST_CHECK=y -+# CONFIG_ENABLE_WARN_DEPRECATED is not set -+ -+CONFIG_KEXEC=y -+ -+CONFIG_HWMON=y -+# CONFIG_HWMON_DEBUG_CHIP is not set -+CONFIG_THERMAL_HWMON=y -+# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set -+# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set -+CONFIG_THERMAL_GOV_FAIR_SHARE=y -+# CONFIG_THERMAL_GOV_USER_SPACE is not set -+CONFIG_THERMAL_GOV_STEP_WISE=y -+# CONFIG_THERMAL_EMULATION is not set -+ -+CONFIG_INOTIFY=y -+CONFIG_INOTIFY_USER=y -+ -+# -+# Bus devices -+# -+# CONFIG_OMAP_OCP2SCP is not set -+CONFIG_PROC_EVENTS=y -+ -+CONFIG_IBMASR=m -+ -+CONFIG_PM_RUNTIME=y -+# CONFIG_PM_DEBUG is not set -+# CONFIG_PM_TEST_SUSPEND is not set -+CONFIG_PM=y -+CONFIG_PM_STD_PARTITION="" -+# CONFIG_DPM_WATCHDOG is not set # revisit this in debug -+CONFIG_PM_TRACE=y -+CONFIG_PM_TRACE_RTC=y -+# CONFIG_PM_OPP is not set -+# CONFIG_PM_AUTOSLEEP is not set -+# CONFIG_PM_WAKELOCKS is not set -+# CONFIG_HIBERNATION is not set -+# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set -+CONFIG_SUSPEND=y -+ -+CONFIG_CPU_FREQ_TABLE=y -+CONFIG_CPU_FREQ_STAT=m -+CONFIG_CPU_FREQ_STAT_DETAILS=y -+ -+ -+CONFIG_NET_VENDOR_SMC=y -+# CONFIG_IBMTR is not set -+# CONFIG_SKISA is not set -+# CONFIG_PROTEON is not set -+# CONFIG_SMCTR is not set -+ -+# CONFIG_MOUSE_ATIXL is not set -+ -+# CONFIG_MEDIA_PARPORT_SUPPORT is not set -+ -+CONFIG_RADIO_TEA5764=m -+CONFIG_RADIO_SAA7706H=m -+CONFIG_RADIO_CADET=m -+CONFIG_RADIO_RTRACK=m -+CONFIG_RADIO_RTRACK2=m -+CONFIG_RADIO_AZTECH=m -+CONFIG_RADIO_GEMTEK=m -+CONFIG_RADIO_SF16FMI=m -+CONFIG_RADIO_SF16FMR2=m -+CONFIG_RADIO_TERRATEC=m -+CONFIG_RADIO_TRUST=m -+CONFIG_RADIO_TYPHOON=m -+CONFIG_RADIO_ZOLTRIX=m -+ -+CONFIG_SND_DARLA20=m -+CONFIG_SND_GINA20=m -+CONFIG_SND_LAYLA20=m -+CONFIG_SND_DARLA24=m -+CONFIG_SND_GINA24=m -+CONFIG_SND_LAYLA24=m -+CONFIG_SND_MONA=m -+CONFIG_SND_MIA=m -+CONFIG_SND_ECHO3G=m -+CONFIG_SND_INDIGO=m -+CONFIG_SND_INDIGOIO=m -+CONFIG_SND_INDIGODJ=m -+CONFIG_SND_INDIGOIOX=m -+CONFIG_SND_INDIGODJX=m -+ -+CONFIG_BALLOON_COMPACTION=y -+CONFIG_COMPACTION=y -+CONFIG_MIGRATION=y -+CONFIG_BOUNCE=y -+# CONFIG_LEDS_AMS_DELTA is not set -+# CONFIG_LEDS_LOCOMO is not set -+# CONFIG_LEDS_NET48XX is not set -+# CONFIG_LEDS_NET5501 is not set -+# CONFIG_LEDS_PCA9532 is not set -+# CONFIG_LEDS_PCA955X is not set -+# CONFIG_LEDS_BD2802 is not set -+# CONFIG_LEDS_S3C24XX is not set -+# CONFIG_LEDS_PCA9633 is not set -+CONFIG_LEDS_DELL_NETBOOKS=m -+# CONFIG_LEDS_TCA6507 is not set -+# CONFIG_LEDS_LM355x is not set -+# CONFIG_LEDS_OT200 is not set -+# CONFIG_LEDS_PWM is not set -+# CONFIG_LEDS_LP8501 is not set -+# CONFIG_LEDS_PCA963X is not set -+# CONFIG_LEDS_PCA9685 is not set -+CONFIG_LEDS_TRIGGER_TIMER=m -+CONFIG_LEDS_TRIGGER_ONESHOT=m -+CONFIG_LEDS_TRIGGER_IDE_DISK=y -+CONFIG_LEDS_TRIGGER_HEARTBEAT=m -+CONFIG_LEDS_TRIGGER_BACKLIGHT=m -+# CONFIG_LEDS_TRIGGER_CPU is not set -+CONFIG_LEDS_TRIGGER_DEFAULT_ON=m -+CONFIG_LEDS_TRIGGER_TRANSIENT=m -+CONFIG_LEDS_TRIGGER_CAMERA=m -+CONFIG_LEDS_ALIX2=m -+CONFIG_LEDS_CLEVO_MAIL=m -+CONFIG_LEDS_INTEL_SS4200=m -+CONFIG_LEDS_LM3530=m -+# CONFIG_LEDS_LM3642 is not set -+CONFIG_LEDS_LM3556=m -+CONFIG_LEDS_BLINKM=m -+CONFIG_LEDS_LP3944=m -+CONFIG_LEDS_LP5521=m -+CONFIG_LEDS_LP5523=m -+CONFIG_LEDS_LP5562=m -+CONFIG_LEDS_LT3593=m -+CONFIG_LEDS_REGULATOR=m -+CONFIG_LEDS_WM8350=m -+CONFIG_LEDS_WM831X_STATUS=m -+ -+CONFIG_DMA_ENGINE=y -+CONFIG_DW_DMAC_CORE=m -+CONFIG_DW_DMAC=m -+CONFIG_DW_DMAC_PCI=m -+# CONFIG_DW_DMAC_BIG_ENDIAN_IO is not set -+# CONFIG_TIMB_DMA is not set -+# CONFIG_DMATEST is not set -+CONFIG_ASYNC_TX_DMA=y -+ -+CONFIG_UNUSED_SYMBOLS=y -+ -+CONFIG_UPROBE_EVENT=y -+ -+CONFIG_DYNAMIC_FTRACE=y -+# CONFIG_IRQSOFF_TRACER is not set -+CONFIG_SCHED_TRACER=y -+CONFIG_CONTEXT_SWITCH_TRACER=y -+CONFIG_TRACER_SNAPSHOT=y -+# CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP is not set -+CONFIG_FTRACE_SYSCALLS=y -+CONFIG_FTRACE_MCOUNT_RECORD=y -+# CONFIG_FTRACE_STARTUP_TEST is not set -+# CONFIG_TRACE_BRANCH_PROFILING is not set -+CONFIG_FUNCTION_PROFILER=y -+CONFIG_RING_BUFFER_BENCHMARK=m -+# CONFIG_RING_BUFFER_STARTUP_TEST is not set -+# CONFIG_RBTREE_TEST is not set -+# CONFIG_INTERVAL_TREE_TEST is not set -+CONFIG_FUNCTION_TRACER=y -+CONFIG_STACK_TRACER=y -+# CONFIG_FUNCTION_GRAPH_TRACER is not set -+ -+CONFIG_KPROBES=y -+CONFIG_KPROBE_EVENT=y -+# CONFIG_KPROBES_SANITY_TEST is not set -+# CONFIG_JUMP_LABEL is not set -+CONFIG_OPTPROBES=y -+ -+CONFIG_HZ_1000=y -+ -+CONFIG_TIMER_STATS=y -+CONFIG_PERF_COUNTERS=y -+ -+# Auxillary displays -+CONFIG_KS0108=m -+CONFIG_KS0108_PORT=0x378 -+CONFIG_KS0108_DELAY=2 -+CONFIG_CFAG12864B=y -+CONFIG_CFAG12864B_RATE=20 -+ -+# CONFIG_PHANTOM is not set -+ -+# CONFIG_POWER_SUPPLY_DEBUG is not set -+ -+# CONFIG_TEST_POWER is not set -+CONFIG_APM_POWER=m -+# CONFIG_GENERIC_ADC_BATTERY is not set -+# CONFIG_WM831X_POWER is not set -+ -+# CONFIG_BATTERY_DS2760 is not set -+# CONFIG_BATTERY_DS2781 is not set -+# CONFIG_BATTERY_DS2782 is not set -+# CONFIG_BATTERY_SBS is not set -+# CONFIG_BATTERY_BQ20Z75 is not set -+# CONFIG_BATTERY_DS2780 is not set -+# CONFIG_BATTERY_BQ27x00 is not set -+# CONFIG_BATTERY_MAX17040 is not set -+# CONFIG_BATTERY_MAX17042 is not set -+# CONFIG_BATTERY_GOLDFISH is not set -+ -+# CONFIG_CHARGER_ISP1704 is not set -+# CONFIG_CHARGER_MAX8903 is not set -+# CONFIG_CHARGER_LP8727 is not set -+# CONFIG_CHARGER_GPIO is not set -+# CONFIG_CHARGER_PCF50633 is not set -+# CONFIG_CHARGER_BQ2415X is not set -+# CONFIG_CHARGER_BQ24190 is not set -+# CONFIG_CHARGER_BQ24735 is not set -+CONFIG_POWER_RESET=y -+ -+# CONFIG_PDA_POWER is not set -+ -+CONFIG_AUXDISPLAY=y -+ -+CONFIG_UIO=m -+CONFIG_UIO_CIF=m -+# CONFIG_UIO_PDRV is not set -+# CONFIG_UIO_PDRV_GENIRQ is not set -+# CONFIG_UIO_DMEM_GENIRQ is not set -+CONFIG_UIO_AEC=m -+CONFIG_UIO_SERCOS3=m -+CONFIG_UIO_PCI_GENERIC=m -+# CONFIG_UIO_NETX is not set -+# CONFIG_UIO_MF624 is not set -+ -+CONFIG_VFIO=m -+CONFIG_VFIO_IOMMU_TYPE1=m -+CONFIG_VFIO_PCI=m -+ -+ -+# LIRC -+CONFIG_LIRC_STAGING=y -+CONFIG_LIRC_BT829=m -+CONFIG_LIRC_IGORPLUGUSB=m -+CONFIG_LIRC_IMON=m -+CONFIG_LIRC_ZILOG=m -+CONFIG_LIRC_PARALLEL=m -+CONFIG_LIRC_SERIAL=m -+CONFIG_LIRC_SERIAL_TRANSMITTER=y -+CONFIG_LIRC_SASEM=m -+CONFIG_LIRC_SIR=m -+CONFIG_LIRC_TTUSBIR=m -+ -+# CONFIG_SAMPLES is not set -+ -+ -+CONFIG_NOZOMI=m -+# CONFIG_TPS65010 is not set -+ -+CONFIG_INPUT_APANEL=m -+CONFIG_INPUT_GP2A=m -+# CONFIG_INPUT_GPIO_TILT_POLLED is not set -+# CONFIG_INPUT_GPIO_BEEPER is not set -+ -+# CONFIG_INTEL_MENLOW is not set -+CONFIG_ENCLOSURE_SERVICES=m -+CONFIG_IPWIRELESS=m -+ -+# CONFIG_BLK_DEV_XIP is not set -+CONFIG_MEMSTICK=m -+# CONFIG_MEMSTICK_DEBUG is not set -+# CONFIG_MEMSTICK_UNSAFE_RESUME is not set -+CONFIG_MSPRO_BLOCK=m -+# CONFIG_MS_BLOCK is not set -+CONFIG_MEMSTICK_TIFM_MS=m -+CONFIG_MEMSTICK_JMICRON_38X=m -+CONFIG_MEMSTICK_R592=m -+CONFIG_MEMSTICK_REALTEK_PCI=m -+ -+CONFIG_ACCESSIBILITY=y -+CONFIG_A11Y_BRAILLE_CONSOLE=y -+ -+# CONFIG_HTC_PASIC3 is not set -+ -+# MT9V022_PCA9536_SWITCH is not set -+ -+CONFIG_OPTIMIZE_INLINING=y -+ -+# FIXME: This should be x86/ia64 only -+# CONFIG_HP_ILO is not set -+ -+CONFIG_GPIOLIB=y -+# CONFIG_PINCTRL is not set -+# CONFIG_DEBUG_PINCTRL is not set -+# CONFIG_PINMUX is not set -+# CONFIG_PINCONF is not set -+ -+CONFIG_NET_DSA=m -+CONFIG_NET_DSA_MV88E6060=m -+CONFIG_NET_DSA_MV88E6131=m -+CONFIG_NET_DSA_MV88E6123_61_65=m -+ -+# Used by Maemo, we don't care. -+# CONFIG_PHONET is not set -+ -+# CONFIG_ICS932S401 is not set -+# CONFIG_ATMEL_SSC is not set -+ -+# CONFIG_C2PORT is not set -+ -+# CONFIG_REGULATOR_DEBUG is not set -+ -+CONFIG_WM8350_POWER=m -+ -+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set -+ -+CONFIG_USB_WUSB=m -+CONFIG_USB_WUSB_CBAF=m -+# CONFIG_USB_WUSB_CBAF_DEBUG is not set -+CONFIG_USB_WHCI_HCD=m -+CONFIG_USB_HWA_HCD=m -+# CONFIG_USB_HCD_BCMA is not set -+# CONFIG_USB_HCD_SSB is not set -+ -+CONFIG_UWB=m -+CONFIG_UWB_HWA=m -+CONFIG_UWB_WHCI=m -+CONFIG_UWB_I1480U=m -+ -+# CONFIG_ANDROID is not set -+CONFIG_STAGING_MEDIA=y -+# CONFIG_DVB_AS102 is not set -+# CONFIG_ET131X is not set -+# CONFIG_SLICOSS is not set -+# CONFIG_WLAGS49_H2 is not set -+# CONFIG_WLAGS49_H25 is not set -+# CONFIG_VIDEO_DT3155 is not set -+# CONFIG_TI_ST is not set -+# CONFIG_FB_XGI is not set -+# CONFIG_VIDEO_GO7007 is not set -+# CONFIG_I2C_BCM2048 is not set -+# CONFIG_VIDEO_TCM825X is not set -+# CONFIG_VIDEO_OMAP4 is not set -+# CONFIG_USB_MSI3101 is not set -+# CONFIG_DT3155 is not set -+# CONFIG_W35UND is not set -+# CONFIG_PRISM2_USB is not set -+# CONFIG_ECHO is not set -+CONFIG_USB_ATMEL=m -+# CONFIG_COMEDI is not set -+# CONFIG_ASUS_OLED is not set -+# CONFIG_PANEL is not set -+# CONFIG_TRANZPORT is not set -+# CONFIG_POHMELFS is not set -+# CONFIG_IDE_PHISON is not set -+# CONFIG_LINE6_USB is not set -+# CONFIG_VME_BUS is not set -+# CONFIG_RAR_REGISTER is not set -+# CONFIG_VT6656 is not set -+# CONFIG_USB_SERIAL_QUATECH_USB2 is not set -+# Larry Finger maintains these (rhbz 913753) -+CONFIG_RTLLIB=m -+CONFIG_RTLLIB_CRYPTO_CCMP=m -+CONFIG_RTLLIB_CRYPTO_TKIP=m -+CONFIG_RTLLIB_CRYPTO_WEP=m -+CONFIG_RTL8192E=m -+# CONFIG_INPUT_GPIO is not set -+# CONFIG_VIDEO_CX25821 is not set -+# CONFIG_R8187SE is not set -+# CONFIG_R8188EU is not set -+# CONFIG_R8821AE is not set -+# CONFIG_RTL8192U is not set -+# CONFIG_FB_SM7XX is not set -+# CONFIG_SPECTRA is not set -+# CONFIG_EASYCAP is not set -+# CONFIG_SOLO6X10 is not set -+# CONFIG_ACPI_QUICKSTART is not set -+# CONFIG_LTE_GDM724X is not set -+CONFIG_R8712U=m # Larry Finger maintains this (rhbz 699618) -+# CONFIG_R8712_AP is not set -+# CONFIG_ATH6K_LEGACY is not set -+# CONFIG_USB_ENESTORAGE is not set -+# CONFIG_BCM_WIMAX is not set -+# CONFIG_USB_BTMTK is not set -+# CONFIG_FT1000 is not set -+# CONFIG_SPEAKUP is not set -+# CONFIG_DX_SEP is not set -+# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set -+# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set -+# CONFIG_RTS_PSTOR is not set -+CONFIG_ALTERA_STAPL=m -+# CONFIG_DVB_CXD2099 is not set -+# CONFIG_USBIP_CORE is not set -+# CONFIG_INTEL_MEI is not set -+# CONFIG_ZCACHE is not set -+# CONFIG_RTS5139 is not set -+# CONFIG_NVEC_LEDS is not set -+# CONFIG_VT6655 is not set -+# CONFIG_RAMSTER is not set -+# CONFIG_USB_WPAN_HCD is not set -+# CONFIG_WIMAX_GDM72XX is not set -+# CONFIG_IPACK_BUS is not set -+# CONFIG_CSR_WIFI is not set -+# CONFIG_ZCACHE2 is not set -+# CONFIG_NET_VENDOR_SILICOM is not set -+# CONFIG_SBYPASS is not set -+# CONFIG_BPCTL is not set -+# CONFIG_CED1401 is not set -+# CONFIG_DGRP is not set -+# CONFIG_SB105X is not set -+# CONFIG_LUSTRE_FS is not set -+# CONFIG_XILLYBUS is not set -+# CONFIG_DGAP is not set -+# CONFIG_DGNC is not set -+# CONFIG_RTS5208 is not set -+# END OF STAGING -+ -+# -+# Remoteproc drivers (EXPERIMENTAL) -+# -+# CONFIG_STE_MODEM_RPROC is not set -+ -+CONFIG_LIBFC=m -+CONFIG_LIBFCOE=m -+CONFIG_FCOE=m -+CONFIG_FCOE_FNIC=m -+ -+ -+# CONFIG_IMA is not set -+CONFIG_IMA_MEASURE_PCR_IDX=10 -+CONFIG_IMA_AUDIT=y -+CONFIG_IMA_LSM_RULES=y -+ -+# CONFIG_EVM is not set -+# CONFIG_PWM_PCA9685 is not set -+ -+CONFIG_LSM_MMAP_MIN_ADDR=65536 -+ -+CONFIG_STRIP_ASM_SYMS=y -+ -+# CONFIG_RCU_FANOUT_EXACT is not set -+# FIXME: Revisit FAST_NO_HZ after it's fixed -+# CONFIG_RCU_FAST_NO_HZ is not set -+# CONFIG_RCU_NOCB_CPU is not set -+CONFIG_RCU_CPU_STALL_TIMEOUT=60 -+# CONFIG_RCU_TORTURE_TEST is not set -+# CONFIG_RCU_TRACE is not set -+# CONFIG_RCU_CPU_STALL_INFO is not set -+# CONFIG_RCU_USER_QS is not set -+ -+CONFIG_KSM=y -+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -+ -+CONFIG_FSNOTIFY=y -+CONFIG_FANOTIFY=y -+CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y -+ -+CONFIG_IEEE802154=m -+CONFIG_IEEE802154_6LOWPAN=m -+CONFIG_IEEE802154_DRIVERS=m -+CONFIG_IEEE802154_FAKEHARD=m -+CONFIG_IEEE802154_FAKELB=m -+ -+CONFIG_MAC802154=m -+CONFIG_NET_MPLS_GSO=m -+ -+# CONFIG_HSR is not set -+ -+# CONFIG_EXTCON is not set -+# CONFIG_EXTCON_ADC_JACK is not set -+# CONFIG_MEMORY is not set -+ -+CONFIG_PPS=m -+# CONFIG_PPS_CLIENT_KTIMER is not set -+CONFIG_PPS_CLIENT_LDISC=m -+# CONFIG_PPS_DEBUG is not set -+CONFIG_PPS_CLIENT_PARPORT=m -+CONFIG_PPS_GENERATOR_PARPORT=m -+CONFIG_PPS_CLIENT_GPIO=m -+CONFIG_NTP_PPS=y -+ -+CONFIG_PTP_1588_CLOCK=m -+CONFIG_PTP_1588_CLOCK_PCH=m -+ -+CONFIG_CLEANCACHE=y -+# CONFIG_PGTABLE_MAPPING is not set -+ -+# CONFIG_MDIO_GPIO is not set -+# CONFIG_KEYBOARD_GPIO_POLLED is not set -+# CONFIG_MOUSE_GPIO is not set -+# CONFIG_I2C_DESIGNWARE_PLATFORM is not set -+# CONFIG_I2C_DESIGNWARE_PCI is not set -+# CONFIG_I2C_GPIO is not set -+# CONFIG_DEBUG_GPIO is not set -+# CONFIG_GPIO_GENERIC_PLATFORM is not set -+# CONFIG_GPIO_CS5535 is not set -+# CONFIG_GPIO_IT8761E is not set -+# CONFIG SB105x is not set -+# CONFIG_GPIO_TS5500 is not set -+# CONFIG_GPIO_VIPERBOARD is not set -+# CONFIG_UCB1400_CORE is not set -+# CONFIG_TPS6105X is not set -+# CONFIG_RADIO_MIROPCM20 is not set -+# CONFIG_USB_GPIO_VBUS is not set -+# CONFIG_GPIO_SCH is not set -+# CONFIG_GPIO_LANGWELL is not set -+# CONFIG_GPIO_RDC321X is not set -+# CONFIG_GPIO_VX855 is not set -+# CONFIG_GPIO_PCH is not set -+# CONFIG_GPIO_ML_IOH is not set -+# CONFIG_GPIO_AMD8111 is not set -+# CONFIG_GPIO_BT8XX is not set -+# CONFIG_GPIO_GRGPIO is not set -+# CONFIG_GPIO_PL061 is not set -+# CONFIG_GPIO_BCM_KONA is not set -+# CONFIG_GPIO_SCH311X is not set -+CONFIG_GPIO_MAX730X=m -+CONFIG_GPIO_MAX7300=m -+CONFIG_GPIO_MAX732X=m -+CONFIG_GPIO_PCF857X=m -+CONFIG_GPIO_SX150X=y -+CONFIG_GPIO_ADP5588=m -+CONFIG_GPIO_ADNP=m -+CONFIG_GPIO_MAX7301=m -+CONFIG_GPIO_MCP23S08=m -+CONFIG_GPIO_MC33880=m -+CONFIG_GPIO_74X164=m -+ -+# FIXME: Why? -+CONFIG_EVENT_POWER_TRACING_DEPRECATED=y -+ -+CONFIG_TEST_KSTRTOX=y -+CONFIG_XZ_DEC=y -+CONFIG_XZ_DEC_X86=y -+CONFIG_XZ_DEC_POWERPC=y -+# CONFIG_XZ_DEC_IA64 is not set -+CONFIG_XZ_DEC_ARM=y -+# CONFIG_XZ_DEC_ARMTHUMB is not set -+# CONFIG_XZ_DEC_SPARC is not set -+# CONFIG_XZ_DEC_TEST is not set -+ -+# CONFIG_POWER_AVS is not set -+ -+CONFIG_TARGET_CORE=m -+CONFIG_ISCSI_TARGET=m -+CONFIG_LOOPBACK_TARGET=m -+CONFIG_SBP_TARGET=m -+CONFIG_TCM_IBLOCK=m -+CONFIG_TCM_FILEIO=m -+CONFIG_TCM_PSCSI=m -+CONFIG_TCM_FC=m -+ -+CONFIG_HWSPINLOCK=m -+ -+CONFIG_PSTORE=y -+CONFIG_PSTORE_RAM=m -+# CONFIG_PSTORE_CONSOLE is not set -+# CONFIG_PSTORE_FTRACE is not set -+ -+# CONFIG_TEST_MODULE is not set -+# CONFIG_TEST_USER_COPY is not set -+ -+# CONFIG_AVERAGE is not set -+# CONFIG_VMXNET3 is not set -+ -+# CONFIG_SIGMA is not set -+ -+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 -+ -+CONFIG_BCMA=m -+CONFIG_BCMA_BLOCKIO=y -+CONFIG_BCMA_HOST_PCI_POSSIBLE=y -+CONFIG_BCMA_HOST_PCI=y -+# CONFIG_BCMA_HOST_SOC is not set -+CONFIG_BCMA_DRIVER_GMAC_CMN=y -+CONFIG_BCMA_DRIVER_GPIO=y -+# CONFIG_BCMA_DEBUG is not set -+ -+# CONFIG_GOOGLE_FIRMWARE is not set -+# CONFIG_INTEL_MID_PTI is not set -+ -+# CONFIG_MAILBOX is not set -+ -+CONFIG_FMC=m -+CONFIG_FMC_FAKEDEV=m -+CONFIG_FMC_TRIVIAL=m -+CONFIG_FMC_WRITE_EEPROM=m -+CONFIG_FMC_CHARDEV=m -+ -+# CONFIG_GENWQE is not set -+ -+# CONFIG_POWERCAP is not set -+ -+# CONFIG_HSI is not set -+ -+ -+# CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set -+ -+# CONFIG_PM_DEVFREQ is not set -+# CONFIG_MODULE_SIG is not set -+# CONFIG_SYSTEM_TRUSTED_KEYRING is not set -+# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set -+# CONFIG_MODULE_VERIFY_ELF is not set -+# CONFIG_CRYPTO_KEY_TYPE is not set -+# CONFIG_PGP_LIBRARY is not set -+# CONFIG_PGP_PRELOAD is not set -+# CONFIG_LOCALVERSION_AUTO is not set -+CONFIG_PROC_DEVICETREE=y -+ -diff -Nur linux-4.1.13.orig/arch/arm/configs/imx_v7_cbi_hb_xbian_defconfig linux-4.1.13/arch/arm/configs/imx_v7_cbi_hb_xbian_defconfig ---- linux-4.1.13.orig/arch/arm/configs/imx_v7_cbi_hb_xbian_defconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/arch/arm/configs/imx_v7_cbi_hb_xbian_defconfig 2015-11-30 17:56:13.528141189 +0100 -@@ -0,0 +1,6246 @@ -+# -+# Automatically generated file; DO NOT EDIT. -+# Linux/arm 4.1.7 Kernel Configuration -+# -+CONFIG_ARM=y -+CONFIG_ARM_HAS_SG_CHAIN=y -+CONFIG_MIGHT_HAVE_PCI=y -+CONFIG_SYS_SUPPORTS_APM_EMULATION=y -+CONFIG_HAVE_PROC_CPU=y -+CONFIG_STACKTRACE_SUPPORT=y -+CONFIG_LOCKDEP_SUPPORT=y -+CONFIG_TRACE_IRQFLAGS_SUPPORT=y -+CONFIG_RWSEM_XCHGADD_ALGORITHM=y -+CONFIG_GENERIC_HWEIGHT=y -+CONFIG_GENERIC_CALIBRATE_DELAY=y -+CONFIG_ZONE_DMA=y -+CONFIG_NEED_DMA_MAP_STATE=y -+CONFIG_ARCH_SUPPORTS_UPROBES=y -+CONFIG_VECTORS_BASE=0xffff0000 -+CONFIG_ARM_PATCH_PHYS_VIRT=y -+CONFIG_GENERIC_BUG=y -+CONFIG_PGTABLE_LEVELS=2 -+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -+CONFIG_IRQ_WORK=y -+CONFIG_BUILDTIME_EXTABLE_SORT=y -+ -+# -+# General setup -+# -+CONFIG_INIT_ENV_ARG_LIMIT=32 -+CONFIG_CROSS_COMPILE="" -+# CONFIG_COMPILE_TEST is not set -+CONFIG_LOCALVERSION="" -+# CONFIG_LOCALVERSION_AUTO is not set -+CONFIG_HAVE_KERNEL_GZIP=y -+CONFIG_HAVE_KERNEL_LZMA=y -+CONFIG_HAVE_KERNEL_XZ=y -+CONFIG_HAVE_KERNEL_LZO=y -+CONFIG_HAVE_KERNEL_LZ4=y -+CONFIG_KERNEL_GZIP=y -+# CONFIG_KERNEL_LZMA is not set -+# CONFIG_KERNEL_XZ is not set -+# CONFIG_KERNEL_LZO is not set -+# CONFIG_KERNEL_LZ4 is not set -+CONFIG_DEFAULT_HOSTNAME="(none)" -+CONFIG_SWAP=y -+CONFIG_SYSVIPC=y -+CONFIG_SYSVIPC_SYSCTL=y -+CONFIG_POSIX_MQUEUE=y -+CONFIG_POSIX_MQUEUE_SYSCTL=y -+CONFIG_CROSS_MEMORY_ATTACH=y -+CONFIG_FHANDLE=y -+CONFIG_USELIB=y -+CONFIG_AUDIT=y -+CONFIG_HAVE_ARCH_AUDITSYSCALL=y -+CONFIG_AUDITSYSCALL=y -+CONFIG_AUDIT_WATCH=y -+CONFIG_AUDIT_TREE=y -+ -+# -+# IRQ subsystem -+# -+CONFIG_GENERIC_IRQ_PROBE=y -+CONFIG_GENERIC_IRQ_SHOW=y -+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -+CONFIG_HARDIRQS_SW_RESEND=y -+CONFIG_GENERIC_IRQ_CHIP=y -+CONFIG_IRQ_DOMAIN=y -+CONFIG_IRQ_DOMAIN_HIERARCHY=y -+CONFIG_HANDLE_DOMAIN_IRQ=y -+# CONFIG_IRQ_DOMAIN_DEBUG is not set -+CONFIG_IRQ_FORCED_THREADING=y -+CONFIG_SPARSE_IRQ=y -+CONFIG_GENERIC_TIME_VSYSCALL=y -+CONFIG_GENERIC_CLOCKEVENTS=y -+CONFIG_ARCH_HAS_TICK_BROADCAST=y -+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -+ -+# -+# Timers subsystem -+# -+CONFIG_TICK_ONESHOT=y -+CONFIG_NO_HZ_COMMON=y -+# CONFIG_HZ_PERIODIC is not set -+CONFIG_NO_HZ_IDLE=y -+# CONFIG_NO_HZ_FULL is not set -+# CONFIG_NO_HZ is not set -+CONFIG_HIGH_RES_TIMERS=y -+ -+# -+# CPU/Task time and stats accounting -+# -+# CONFIG_TICK_CPU_ACCOUNTING is not set -+# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set -+CONFIG_IRQ_TIME_ACCOUNTING=y -+CONFIG_BSD_PROCESS_ACCT=y -+CONFIG_BSD_PROCESS_ACCT_V3=y -+# CONFIG_TASKSTATS is not set -+ -+# -+# RCU Subsystem -+# -+CONFIG_TREE_RCU=y -+CONFIG_SRCU=y -+# CONFIG_TASKS_RCU is not set -+CONFIG_RCU_STALL_COMMON=y -+# CONFIG_RCU_USER_QS is not set -+CONFIG_RCU_FANOUT=32 -+CONFIG_RCU_FANOUT_LEAF=16 -+# CONFIG_RCU_FANOUT_EXACT is not set -+# CONFIG_RCU_FAST_NO_HZ is not set -+# CONFIG_TREE_RCU_TRACE is not set -+CONFIG_RCU_KTHREAD_PRIO=0 -+# CONFIG_RCU_NOCB_CPU is not set -+# CONFIG_RCU_EXPEDITE_BOOT is not set -+CONFIG_BUILD_BIN2C=y -+CONFIG_IKCONFIG=y -+CONFIG_IKCONFIG_PROC=y -+CONFIG_LOG_BUF_SHIFT=21 -+CONFIG_LOG_CPU_MAX_BUF_SHIFT=13 -+CONFIG_GENERIC_SCHED_CLOCK=y -+CONFIG_CGROUPS=y -+# CONFIG_CGROUP_DEBUG is not set -+# CONFIG_CGROUP_FREEZER is not set -+CONFIG_CGROUP_DEVICE=y -+# CONFIG_CPUSETS is not set -+# CONFIG_CGROUP_CPUACCT is not set -+CONFIG_PAGE_COUNTER=y -+CONFIG_MEMCG=y -+CONFIG_MEMCG_SWAP=y -+# CONFIG_MEMCG_SWAP_ENABLED is not set -+CONFIG_MEMCG_KMEM=y -+# CONFIG_CGROUP_PERF is not set -+# CONFIG_CGROUP_SCHED is not set -+# CONFIG_BLK_CGROUP is not set -+# CONFIG_CHECKPOINT_RESTORE is not set -+CONFIG_NAMESPACES=y -+CONFIG_UTS_NS=y -+CONFIG_IPC_NS=y -+CONFIG_USER_NS=y -+CONFIG_PID_NS=y -+CONFIG_NET_NS=y -+# CONFIG_SCHED_AUTOGROUP is not set -+# CONFIG_SYSFS_DEPRECATED is not set -+CONFIG_RELAY=y -+CONFIG_BLK_DEV_INITRD=y -+CONFIG_INITRAMFS_SOURCE="" -+CONFIG_RD_GZIP=y -+# CONFIG_RD_BZIP2 is not set -+# CONFIG_RD_LZMA is not set -+# CONFIG_RD_XZ is not set -+CONFIG_RD_LZO=y -+CONFIG_RD_LZ4=y -+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -+CONFIG_SYSCTL=y -+CONFIG_ANON_INODES=y -+CONFIG_HAVE_UID16=y -+CONFIG_BPF=y -+CONFIG_EXPERT=y -+# CONFIG_UID16 is not set -+CONFIG_MULTIUSER=y -+CONFIG_SGETMASK_SYSCALL=y -+CONFIG_SYSFS_SYSCALL=y -+CONFIG_SYSCTL_SYSCALL=y -+CONFIG_KALLSYMS=y -+CONFIG_KALLSYMS_ALL=y -+CONFIG_PRINTK=y -+CONFIG_BUG=y -+CONFIG_ELF_CORE=y -+CONFIG_BASE_FULL=y -+CONFIG_FUTEX=y -+CONFIG_EPOLL=y -+CONFIG_SIGNALFD=y -+CONFIG_TIMERFD=y -+CONFIG_EVENTFD=y -+# CONFIG_BPF_SYSCALL is not set -+CONFIG_SHMEM=y -+CONFIG_AIO=y -+CONFIG_ADVISE_SYSCALLS=y -+CONFIG_PCI_QUIRKS=y -+# CONFIG_EMBEDDED is not set -+CONFIG_HAVE_PERF_EVENTS=y -+CONFIG_PERF_USE_VMALLOC=y -+ -+# -+# Kernel Performance Events And Counters -+# -+CONFIG_PERF_EVENTS=y -+# CONFIG_DEBUG_PERF_USE_VMALLOC is not set -+CONFIG_VM_EVENT_COUNTERS=y -+# CONFIG_SLUB_DEBUG is not set -+# CONFIG_COMPAT_BRK is not set -+# CONFIG_SLAB is not set -+CONFIG_SLUB=y -+# CONFIG_SLOB is not set -+# CONFIG_SLUB_CPU_PARTIAL is not set -+# CONFIG_SYSTEM_TRUSTED_KEYRING is not set -+# CONFIG_PROFILING is not set -+CONFIG_HAVE_OPROFILE=y -+# CONFIG_KPROBES is not set -+# CONFIG_JUMP_LABEL is not set -+# CONFIG_UPROBES is not set -+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set -+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y -+CONFIG_ARCH_USE_BUILTIN_BSWAP=y -+CONFIG_HAVE_KPROBES=y -+CONFIG_HAVE_KRETPROBES=y -+CONFIG_HAVE_ARCH_TRACEHOOK=y -+CONFIG_HAVE_DMA_ATTRS=y -+CONFIG_HAVE_DMA_CONTIGUOUS=y -+CONFIG_GENERIC_SMP_IDLE_THREAD=y -+CONFIG_GENERIC_IDLE_POLL_SETUP=y -+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -+CONFIG_HAVE_CLK=y -+CONFIG_HAVE_DMA_API_DEBUG=y -+CONFIG_HAVE_HW_BREAKPOINT=y -+CONFIG_HAVE_PERF_REGS=y -+CONFIG_HAVE_PERF_USER_STACK_DUMP=y -+CONFIG_HAVE_ARCH_JUMP_LABEL=y -+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y -+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -+CONFIG_HAVE_CC_STACKPROTECTOR=y -+CONFIG_CC_STACKPROTECTOR=y -+# CONFIG_CC_STACKPROTECTOR_NONE is not set -+CONFIG_CC_STACKPROTECTOR_REGULAR=y -+# CONFIG_CC_STACKPROTECTOR_STRONG is not set -+CONFIG_HAVE_CONTEXT_TRACKING=y -+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y -+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -+CONFIG_MODULES_USE_ELF_REL=y -+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -+CONFIG_CLONE_BACKWARDS=y -+CONFIG_OLD_SIGSUSPEND3=y -+CONFIG_OLD_SIGACTION=y -+ -+# -+# GCOV-based kernel profiling -+# -+# CONFIG_GCOV_KERNEL is not set -+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y -+CONFIG_HAVE_GENERIC_DMA_COHERENT=y -+CONFIG_RT_MUTEXES=y -+CONFIG_BASE_SMALL=0 -+CONFIG_MODULES=y -+# CONFIG_MODULE_FORCE_LOAD is not set -+CONFIG_MODULE_UNLOAD=y -+# CONFIG_MODULE_FORCE_UNLOAD is not set -+CONFIG_MODVERSIONS=y -+CONFIG_MODULE_SRCVERSION_ALL=y -+# CONFIG_MODULE_SIG is not set -+# CONFIG_MODULE_COMPRESS is not set -+CONFIG_STOP_MACHINE=y -+CONFIG_BLOCK=y -+CONFIG_LBDAF=y -+CONFIG_BLK_DEV_BSG=y -+CONFIG_BLK_DEV_BSGLIB=y -+# CONFIG_BLK_DEV_INTEGRITY is not set -+# CONFIG_BLK_CMDLINE_PARSER is not set -+ -+# -+# Partition Types -+# -+CONFIG_PARTITION_ADVANCED=y -+# CONFIG_ACORN_PARTITION is not set -+# CONFIG_AIX_PARTITION is not set -+# CONFIG_OSF_PARTITION is not set -+# CONFIG_AMIGA_PARTITION is not set -+# CONFIG_ATARI_PARTITION is not set -+CONFIG_MAC_PARTITION=y -+CONFIG_MSDOS_PARTITION=y -+CONFIG_BSD_DISKLABEL=y -+CONFIG_MINIX_SUBPARTITION=y -+CONFIG_SOLARIS_X86_PARTITION=y -+CONFIG_UNIXWARE_DISKLABEL=y -+CONFIG_LDM_PARTITION=y -+# CONFIG_LDM_DEBUG is not set -+# CONFIG_SGI_PARTITION is not set -+# CONFIG_ULTRIX_PARTITION is not set -+CONFIG_SUN_PARTITION=y -+CONFIG_KARMA_PARTITION=y -+CONFIG_EFI_PARTITION=y -+# CONFIG_SYSV68_PARTITION is not set -+# CONFIG_CMDLINE_PARTITION is not set -+ -+# -+# IO Schedulers -+# -+CONFIG_IOSCHED_NOOP=y -+CONFIG_IOSCHED_DEADLINE=y -+CONFIG_IOSCHED_CFQ=y -+CONFIG_IOSCHED_BFQ=y -+# CONFIG_CGROUP_BFQIO is not set -+# CONFIG_DEFAULT_DEADLINE is not set -+# CONFIG_DEFAULT_CFQ is not set -+CONFIG_DEFAULT_BFQ=y -+# CONFIG_DEFAULT_NOOP is not set -+CONFIG_DEFAULT_IOSCHED="bfq" -+CONFIG_PADATA=y -+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y -+CONFIG_INLINE_READ_UNLOCK=y -+CONFIG_INLINE_READ_UNLOCK_IRQ=y -+CONFIG_INLINE_WRITE_UNLOCK=y -+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y -+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y -+CONFIG_MUTEX_SPIN_ON_OWNER=y -+CONFIG_RWSEM_SPIN_ON_OWNER=y -+CONFIG_LOCK_SPIN_ON_OWNER=y -+CONFIG_FREEZER=y -+ -+# -+# System Type -+# -+CONFIG_MMU=y -+CONFIG_ARCH_MULTIPLATFORM=y -+# CONFIG_ARCH_REALVIEW is not set -+# CONFIG_ARCH_VERSATILE is not set -+# CONFIG_ARCH_CLPS711X is not set -+# CONFIG_ARCH_GEMINI is not set -+# CONFIG_ARCH_EBSA110 is not set -+# CONFIG_ARCH_EP93XX is not set -+# CONFIG_ARCH_FOOTBRIDGE is not set -+# CONFIG_ARCH_NETX is not set -+# CONFIG_ARCH_IOP13XX is not set -+# CONFIG_ARCH_IOP32X is not set -+# CONFIG_ARCH_IOP33X is not set -+# CONFIG_ARCH_IXP4XX is not set -+# CONFIG_ARCH_DOVE is not set -+# CONFIG_ARCH_MV78XX0 is not set -+# CONFIG_ARCH_ORION5X is not set -+# CONFIG_ARCH_MMP is not set -+# CONFIG_ARCH_KS8695 is not set -+# CONFIG_ARCH_W90X900 is not set -+# CONFIG_ARCH_LPC32XX is not set -+# CONFIG_ARCH_PXA is not set -+# CONFIG_ARCH_SHMOBILE_LEGACY is not set -+# CONFIG_ARCH_RPC is not set -+# CONFIG_ARCH_SA1100 is not set -+# CONFIG_ARCH_S3C24XX is not set -+# CONFIG_ARCH_S3C64XX is not set -+# CONFIG_ARCH_DAVINCI is not set -+# CONFIG_ARCH_OMAP1 is not set -+ -+# -+# Multiple platform selection -+# -+ -+# -+# CPU Core family selection -+# -+# CONFIG_ARCH_MULTI_V6 is not set -+CONFIG_ARCH_MULTI_V7=y -+CONFIG_ARCH_MULTI_V6_V7=y -+# CONFIG_ARCH_MULTI_CPU_AUTO is not set -+# CONFIG_ARCH_VIRT is not set -+# CONFIG_ARCH_MVEBU is not set -+# CONFIG_ARCH_ALPINE is not set -+# CONFIG_ARCH_AT91 is not set -+# CONFIG_ARCH_BCM is not set -+# CONFIG_ARCH_BERLIN is not set -+# CONFIG_ARCH_DIGICOLOR is not set -+# CONFIG_ARCH_HIGHBANK is not set -+# CONFIG_ARCH_HISI is not set -+# CONFIG_ARCH_KEYSTONE is not set -+# CONFIG_ARCH_MESON is not set -+CONFIG_ARCH_MXC=y -+CONFIG_HAVE_IMX_ANATOP=y -+CONFIG_HAVE_IMX_GPC=y -+CONFIG_HAVE_IMX_MMDC=y -+CONFIG_HAVE_IMX_SRC=y -+ -+# -+# Device tree only -+# -+# CONFIG_SOC_IMX50 is not set -+# CONFIG_SOC_IMX51 is not set -+# CONFIG_SOC_IMX53 is not set -+CONFIG_SOC_IMX6=y -+CONFIG_SOC_IMX6Q=y -+CONFIG_SOC_IMX6SL=y -+# CONFIG_SOC_IMX6SX is not set -+# CONFIG_SOC_VF610 is not set -+# CONFIG_SOC_LS1021A is not set -+# CONFIG_ARCH_MEDIATEK is not set -+ -+# -+# TI OMAP/AM/DM/DRA Family -+# -+# CONFIG_ARCH_OMAP3 is not set -+# CONFIG_ARCH_OMAP4 is not set -+# CONFIG_SOC_OMAP5 is not set -+# CONFIG_SOC_AM33XX is not set -+# CONFIG_SOC_AM43XX is not set -+# CONFIG_SOC_DRA7XX is not set -+# CONFIG_ARCH_QCOM is not set -+# CONFIG_ARCH_ROCKCHIP is not set -+# CONFIG_ARCH_SOCFPGA is not set -+# CONFIG_PLAT_SPEAR is not set -+# CONFIG_ARCH_STI is not set -+# CONFIG_ARCH_S5PV210 is not set -+# CONFIG_ARCH_EXYNOS is not set -+# CONFIG_ARCH_SHMOBILE_MULTI is not set -+# CONFIG_ARCH_SUNXI is not set -+# CONFIG_ARCH_SIRF is not set -+# CONFIG_ARCH_TEGRA is not set -+# CONFIG_ARCH_U8500 is not set -+# CONFIG_ARCH_VEXPRESS is not set -+# CONFIG_ARCH_WM8850 is not set -+# CONFIG_ARCH_ZYNQ is not set -+ -+# -+# Processor Type -+# -+CONFIG_CPU_V7=y -+CONFIG_CPU_32v6K=y -+CONFIG_CPU_32v7=y -+CONFIG_CPU_ABRT_EV7=y -+CONFIG_CPU_PABRT_V7=y -+CONFIG_CPU_CACHE_V7=y -+CONFIG_CPU_CACHE_VIPT=y -+CONFIG_CPU_COPY_V6=y -+CONFIG_CPU_TLB_V7=y -+CONFIG_CPU_HAS_ASID=y -+CONFIG_CPU_CP15=y -+CONFIG_CPU_CP15_MMU=y -+ -+# -+# Processor Features -+# -+# CONFIG_ARM_LPAE is not set -+# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set -+CONFIG_ARM_THUMB=y -+CONFIG_ARM_THUMBEE=y -+CONFIG_ARM_VIRT_EXT=y -+CONFIG_SWP_EMULATE=y -+# CONFIG_CPU_ICACHE_DISABLE is not set -+# CONFIG_CPU_BPREDICT_DISABLE is not set -+CONFIG_KUSER_HELPERS=y -+CONFIG_VDSO=y -+CONFIG_OUTER_CACHE=y -+CONFIG_OUTER_CACHE_SYNC=y -+CONFIG_MIGHT_HAVE_CACHE_L2X0=y -+CONFIG_CACHE_L2X0=y -+# CONFIG_PL310_ERRATA_588369 is not set -+# CONFIG_PL310_ERRATA_727915 is not set -+# CONFIG_PL310_ERRATA_753970 is not set -+CONFIG_PL310_ERRATA_769419=y -+CONFIG_ARM_L1_CACHE_SHIFT_6=y -+CONFIG_ARM_L1_CACHE_SHIFT=6 -+CONFIG_ARM_DMA_MEM_BUFFERABLE=y -+# CONFIG_ARM_KERNMEM_PERMS is not set -+CONFIG_MULTI_IRQ_HANDLER=y -+# CONFIG_ARM_ERRATA_430973 is not set -+# CONFIG_ARM_ERRATA_643719 is not set -+# CONFIG_ARM_ERRATA_720789 is not set -+CONFIG_ARM_ERRATA_754322=y -+# CONFIG_ARM_ERRATA_754327 is not set -+CONFIG_ARM_ERRATA_764369=y -+CONFIG_ARM_ERRATA_775420=y -+# CONFIG_ARM_ERRATA_798181 is not set -+# CONFIG_ARM_ERRATA_773022 is not set -+ -+# -+# Bus support -+# -+CONFIG_PCI=y -+CONFIG_PCI_DOMAINS=y -+CONFIG_PCI_DOMAINS_GENERIC=y -+CONFIG_PCI_SYSCALL=y -+# CONFIG_PCI_MSI is not set -+# CONFIG_PCI_DEBUG is not set -+# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set -+# CONFIG_PCI_STUB is not set -+# CONFIG_PCI_IOV is not set -+# CONFIG_PCI_PRI is not set -+# CONFIG_PCI_PASID is not set -+ -+# -+# PCI host controller drivers -+# -+CONFIG_PCIE_DW=y -+CONFIG_PCI_IMX6=y -+# CONFIG_PCI_HOST_GENERIC is not set -+# CONFIG_PCI_LAYERSCAPE is not set -+# CONFIG_PCIE_IPROC is not set -+CONFIG_PCIEPORTBUS=y -+CONFIG_PCIEAER=y -+# CONFIG_PCIE_ECRC is not set -+# CONFIG_PCIEAER_INJECT is not set -+CONFIG_PCIEASPM=y -+# CONFIG_PCIEASPM_DEBUG is not set -+# CONFIG_PCIEASPM_DEFAULT is not set -+# CONFIG_PCIEASPM_POWERSAVE is not set -+CONFIG_PCIEASPM_PERFORMANCE=y -+CONFIG_PCIE_PME=y -+# CONFIG_PCCARD is not set -+ -+# -+# Kernel Features -+# -+CONFIG_HAVE_SMP=y -+CONFIG_SMP=y -+CONFIG_SMP_ON_UP=y -+CONFIG_ARM_CPU_TOPOLOGY=y -+# CONFIG_SCHED_MC is not set -+# CONFIG_SCHED_SMT is not set -+CONFIG_HAVE_ARM_SCU=y -+# CONFIG_HAVE_ARM_ARCH_TIMER is not set -+CONFIG_HAVE_ARM_TWD=y -+# CONFIG_MCPM is not set -+# CONFIG_BIG_LITTLE is not set -+# CONFIG_VMSPLIT_3G is not set -+CONFIG_VMSPLIT_2G=y -+# CONFIG_VMSPLIT_1G is not set -+CONFIG_PAGE_OFFSET=0x80000000 -+CONFIG_NR_CPUS=4 -+CONFIG_HOTPLUG_CPU=y -+# CONFIG_ARM_PSCI is not set -+CONFIG_ARCH_NR_GPIO=0 -+# CONFIG_PREEMPT_NONE is not set -+CONFIG_PREEMPT_VOLUNTARY=y -+# CONFIG_PREEMPT is not set -+CONFIG_HZ_FIXED=0 -+# CONFIG_HZ_100 is not set -+# CONFIG_HZ_200 is not set -+# CONFIG_HZ_250 is not set -+# CONFIG_HZ_300 is not set -+CONFIG_HZ_500=y -+# CONFIG_HZ_1000 is not set -+CONFIG_HZ=500 -+CONFIG_SCHED_HRTICK=y -+CONFIG_THUMB2_KERNEL=y -+CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y -+CONFIG_ARM_ASM_UNIFIED=y -+CONFIG_AEABI=y -+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set -+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set -+CONFIG_HAVE_ARCH_PFN_VALID=y -+CONFIG_HIGHMEM=y -+# CONFIG_HIGHPTE is not set -+CONFIG_HW_PERF_EVENTS=y -+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y -+CONFIG_FLATMEM=y -+CONFIG_FLAT_NODE_MEM_MAP=y -+CONFIG_HAVE_MEMBLOCK=y -+CONFIG_NO_BOOTMEM=y -+CONFIG_MEMORY_ISOLATION=y -+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set -+CONFIG_PAGEFLAGS_EXTENDED=y -+CONFIG_SPLIT_PTLOCK_CPUS=4 -+CONFIG_COMPACTION=y -+CONFIG_MIGRATION=y -+# CONFIG_PHYS_ADDR_T_64BIT is not set -+CONFIG_ZONE_DMA_FLAG=1 -+CONFIG_BOUNCE=y -+# CONFIG_KSM is not set -+CONFIG_DEFAULT_MMAP_MIN_ADDR=8192 -+CONFIG_CLEANCACHE=y -+CONFIG_FRONTSWAP=y -+CONFIG_CMA=y -+# CONFIG_CMA_DEBUG is not set -+# CONFIG_CMA_DEBUGFS is not set -+CONFIG_CMA_AREAS=7 -+CONFIG_ZSWAP=y -+CONFIG_ZPOOL=y -+CONFIG_ZBUD=y -+# CONFIG_ZSMALLOC is not set -+CONFIG_FORCE_MAX_ZONEORDER=14 -+CONFIG_ALIGNMENT_TRAP=y -+# CONFIG_UACCESS_WITH_MEMCPY is not set -+# CONFIG_SECCOMP is not set -+CONFIG_SWIOTLB=y -+CONFIG_IOMMU_HELPER=y -+# CONFIG_XEN is not set -+ -+# -+# Boot options -+# -+CONFIG_USE_OF=y -+CONFIG_ATAGS=y -+# CONFIG_DEPRECATED_PARAM_STRUCT is not set -+CONFIG_ZBOOT_ROM_TEXT=0 -+CONFIG_ZBOOT_ROM_BSS=0 -+# CONFIG_ARM_APPENDED_DTB is not set -+CONFIG_CMDLINE="console=ttymxc0,115200" -+# CONFIG_CMDLINE_FROM_BOOTLOADER is not set -+CONFIG_CMDLINE_EXTEND=y -+# CONFIG_CMDLINE_FORCE is not set -+CONFIG_KEXEC=y -+# CONFIG_ATAGS_PROC is not set -+# CONFIG_CRASH_DUMP is not set -+CONFIG_AUTO_ZRELADDR=y -+ -+# -+# CPU Power Management -+# -+ -+# -+# CPU Frequency scaling -+# -+CONFIG_CPU_FREQ=y -+CONFIG_CPU_FREQ_GOV_COMMON=y -+CONFIG_CPU_FREQ_STAT=y -+CONFIG_CPU_FREQ_STAT_DETAILS=y -+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set -+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set -+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set -+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set -+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -+CONFIG_CPU_FREQ_GOV_POWERSAVE=y -+CONFIG_CPU_FREQ_GOV_USERSPACE=y -+CONFIG_CPU_FREQ_GOV_ONDEMAND=y -+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -+ -+# -+# CPU frequency scaling drivers -+# -+# CONFIG_CPUFREQ_DT is not set -+CONFIG_ARM_IMX6Q_CPUFREQ=y -+# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set -+# CONFIG_QORIQ_CPUFREQ is not set -+ -+# -+# CPU Idle -+# -+CONFIG_CPU_IDLE=y -+CONFIG_CPU_IDLE_GOV_LADDER=y -+CONFIG_CPU_IDLE_GOV_MENU=y -+CONFIG_DT_IDLE_STATES=y -+ -+# -+# ARM CPU Idle Drivers -+# -+CONFIG_ARM_CPUIDLE=y -+# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set -+ -+# -+# Floating point emulation -+# -+ -+# -+# At least one emulation must be selected -+# -+CONFIG_VFP=y -+CONFIG_VFPv3=y -+CONFIG_NEON=y -+CONFIG_KERNEL_MODE_NEON=y -+ -+# -+# Userspace binary formats -+# -+CONFIG_BINFMT_ELF=y -+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y -+CONFIG_BINFMT_SCRIPT=y -+# CONFIG_HAVE_AOUT is not set -+CONFIG_BINFMT_MISC=m -+CONFIG_COREDUMP=y -+ -+# -+# Power management options -+# -+CONFIG_SUSPEND=y -+CONFIG_SUSPEND_FREEZER=y -+# CONFIG_HIBERNATION is not set -+CONFIG_PM_SLEEP=y -+CONFIG_PM_SLEEP_SMP=y -+# CONFIG_PM_AUTOSLEEP is not set -+CONFIG_PM_WAKELOCKS=y -+CONFIG_PM_WAKELOCKS_LIMIT=0 -+CONFIG_PM_WAKELOCKS_GC=y -+CONFIG_PM=y -+CONFIG_PM_DEBUG=y -+CONFIG_PM_ADVANCED_DEBUG=y -+# CONFIG_PM_TEST_SUSPEND is not set -+CONFIG_PM_SLEEP_DEBUG=y -+# CONFIG_APM_EMULATION is not set -+CONFIG_PM_OPP=y -+CONFIG_PM_CLK=y -+CONFIG_PM_GENERIC_DOMAINS=y -+# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set -+CONFIG_PM_GENERIC_DOMAINS_SLEEP=y -+CONFIG_PM_GENERIC_DOMAINS_OF=y -+CONFIG_CPU_PM=y -+CONFIG_ARCH_SUSPEND_POSSIBLE=y -+CONFIG_ARM_CPU_SUSPEND=y -+CONFIG_ARCH_HIBERNATION_POSSIBLE=y -+CONFIG_NET=y -+ -+# -+# Networking options -+# -+CONFIG_PACKET=y -+CONFIG_PACKET_DIAG=y -+CONFIG_UNIX=y -+CONFIG_UNIX_DIAG=y -+CONFIG_XFRM=y -+CONFIG_XFRM_ALGO=y -+CONFIG_XFRM_USER=y -+CONFIG_XFRM_SUB_POLICY=y -+CONFIG_XFRM_MIGRATE=y -+CONFIG_XFRM_STATISTICS=y -+CONFIG_XFRM_IPCOMP=m -+CONFIG_NET_KEY=y -+CONFIG_NET_KEY_MIGRATE=y -+CONFIG_INET=y -+CONFIG_IP_MULTICAST=y -+CONFIG_IP_ADVANCED_ROUTER=y -+# CONFIG_IP_FIB_TRIE_STATS is not set -+CONFIG_IP_MULTIPLE_TABLES=y -+CONFIG_IP_ROUTE_MULTIPATH=y -+CONFIG_IP_ROUTE_VERBOSE=y -+CONFIG_IP_ROUTE_CLASSID=y -+CONFIG_IP_PNP=y -+CONFIG_IP_PNP_DHCP=y -+CONFIG_IP_PNP_BOOTP=y -+# CONFIG_IP_PNP_RARP is not set -+CONFIG_NET_IPIP=m -+# CONFIG_NET_IPGRE_DEMUX is not set -+CONFIG_NET_IP_TUNNEL=m -+CONFIG_IP_MROUTE=y -+# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set -+# CONFIG_IP_PIMSM_V1 is not set -+# CONFIG_IP_PIMSM_V2 is not set -+CONFIG_SYN_COOKIES=y -+CONFIG_NET_IPVTI=m -+CONFIG_NET_UDP_TUNNEL=m -+# CONFIG_NET_FOU is not set -+# CONFIG_NET_FOU_IP_TUNNELS is not set -+# CONFIG_GENEVE is not set -+CONFIG_INET_AH=m -+CONFIG_INET_ESP=m -+CONFIG_INET_IPCOMP=m -+CONFIG_INET_XFRM_TUNNEL=m -+CONFIG_INET_TUNNEL=m -+CONFIG_INET_XFRM_MODE_TRANSPORT=m -+CONFIG_INET_XFRM_MODE_TUNNEL=m -+CONFIG_INET_XFRM_MODE_BEET=m -+CONFIG_INET_LRO=m -+CONFIG_INET_DIAG=y -+CONFIG_INET_TCP_DIAG=y -+CONFIG_INET_UDP_DIAG=m -+CONFIG_TCP_CONG_ADVANCED=y -+CONFIG_TCP_CONG_BIC=m -+CONFIG_TCP_CONG_CUBIC=m -+CONFIG_TCP_CONG_WESTWOOD=m -+CONFIG_TCP_CONG_HTCP=m -+CONFIG_TCP_CONG_HSTCP=m -+CONFIG_TCP_CONG_HYBLA=m -+CONFIG_TCP_CONG_VEGAS=y -+CONFIG_TCP_CONG_SCALABLE=m -+CONFIG_TCP_CONG_LP=m -+CONFIG_TCP_CONG_VENO=m -+CONFIG_TCP_CONG_YEAH=y -+CONFIG_TCP_CONG_ILLINOIS=m -+CONFIG_TCP_CONG_DCTCP=m -+CONFIG_DEFAULT_VEGAS=y -+# CONFIG_DEFAULT_RENO is not set -+CONFIG_DEFAULT_TCP_CONG="vegas" -+CONFIG_TCP_MD5SIG=y -+CONFIG_IPV6=m -+CONFIG_IPV6_ROUTER_PREF=y -+CONFIG_IPV6_ROUTE_INFO=y -+CONFIG_IPV6_OPTIMISTIC_DAD=y -+CONFIG_INET6_AH=m -+CONFIG_INET6_ESP=m -+CONFIG_INET6_IPCOMP=m -+CONFIG_IPV6_MIP6=m -+CONFIG_INET6_XFRM_TUNNEL=m -+CONFIG_INET6_TUNNEL=m -+CONFIG_INET6_XFRM_MODE_TRANSPORT=m -+CONFIG_INET6_XFRM_MODE_TUNNEL=m -+CONFIG_INET6_XFRM_MODE_BEET=m -+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m -+CONFIG_IPV6_VTI=m -+CONFIG_IPV6_SIT=m -+CONFIG_IPV6_SIT_6RD=y -+CONFIG_IPV6_NDISC_NODETYPE=y -+CONFIG_IPV6_TUNNEL=m -+CONFIG_IPV6_GRE=m -+CONFIG_IPV6_MULTIPLE_TABLES=y -+CONFIG_IPV6_SUBTREES=y -+CONFIG_IPV6_MROUTE=y -+CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y -+CONFIG_IPV6_PIMSM_V2=y -+CONFIG_NETWORK_SECMARK=y -+CONFIG_NET_PTP_CLASSIFY=y -+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set -+CONFIG_NETFILTER=y -+# CONFIG_NETFILTER_DEBUG is not set -+CONFIG_NETFILTER_ADVANCED=y -+CONFIG_BRIDGE_NETFILTER=m -+ -+# -+# Core Netfilter Configuration -+# -+CONFIG_NETFILTER_NETLINK=m -+CONFIG_NETFILTER_NETLINK_ACCT=m -+CONFIG_NETFILTER_NETLINK_QUEUE=m -+CONFIG_NETFILTER_NETLINK_LOG=m -+CONFIG_NF_CONNTRACK=m -+CONFIG_NF_LOG_COMMON=m -+CONFIG_NF_CONNTRACK_MARK=y -+CONFIG_NF_CONNTRACK_SECMARK=y -+CONFIG_NF_CONNTRACK_ZONES=y -+CONFIG_NF_CONNTRACK_PROCFS=y -+CONFIG_NF_CONNTRACK_EVENTS=y -+CONFIG_NF_CONNTRACK_TIMEOUT=y -+CONFIG_NF_CONNTRACK_TIMESTAMP=y -+CONFIG_NF_CONNTRACK_LABELS=y -+CONFIG_NF_CT_PROTO_DCCP=m -+CONFIG_NF_CT_PROTO_GRE=m -+CONFIG_NF_CT_PROTO_SCTP=m -+CONFIG_NF_CT_PROTO_UDPLITE=m -+CONFIG_NF_CONNTRACK_AMANDA=m -+CONFIG_NF_CONNTRACK_FTP=m -+CONFIG_NF_CONNTRACK_H323=m -+CONFIG_NF_CONNTRACK_IRC=m -+CONFIG_NF_CONNTRACK_BROADCAST=m -+CONFIG_NF_CONNTRACK_NETBIOS_NS=m -+CONFIG_NF_CONNTRACK_SNMP=m -+CONFIG_NF_CONNTRACK_PPTP=m -+CONFIG_NF_CONNTRACK_SANE=m -+CONFIG_NF_CONNTRACK_SIP=m -+CONFIG_NF_CONNTRACK_TFTP=m -+CONFIG_NF_CT_NETLINK=m -+CONFIG_NF_CT_NETLINK_TIMEOUT=m -+CONFIG_NF_CT_NETLINK_HELPER=m -+CONFIG_NETFILTER_NETLINK_QUEUE_CT=y -+CONFIG_NF_NAT=m -+CONFIG_NF_NAT_NEEDED=y -+CONFIG_NF_NAT_PROTO_DCCP=m -+CONFIG_NF_NAT_PROTO_UDPLITE=m -+CONFIG_NF_NAT_PROTO_SCTP=m -+CONFIG_NF_NAT_AMANDA=m -+CONFIG_NF_NAT_FTP=m -+CONFIG_NF_NAT_IRC=m -+CONFIG_NF_NAT_SIP=m -+CONFIG_NF_NAT_TFTP=m -+CONFIG_NF_NAT_REDIRECT=m -+CONFIG_NETFILTER_SYNPROXY=m -+CONFIG_NF_TABLES=m -+CONFIG_NF_TABLES_INET=m -+CONFIG_NFT_EXTHDR=m -+CONFIG_NFT_META=m -+CONFIG_NFT_CT=m -+CONFIG_NFT_RBTREE=m -+CONFIG_NFT_HASH=m -+CONFIG_NFT_COUNTER=m -+CONFIG_NFT_LOG=m -+CONFIG_NFT_LIMIT=m -+# CONFIG_NFT_MASQ is not set -+# CONFIG_NFT_REDIR is not set -+CONFIG_NFT_NAT=m -+CONFIG_NFT_QUEUE=m -+CONFIG_NFT_REJECT=m -+CONFIG_NFT_REJECT_INET=m -+CONFIG_NFT_COMPAT=m -+CONFIG_NETFILTER_XTABLES=m -+ -+# -+# Xtables combined modules -+# -+CONFIG_NETFILTER_XT_MARK=m -+CONFIG_NETFILTER_XT_CONNMARK=m -+CONFIG_NETFILTER_XT_SET=m -+ -+# -+# Xtables targets -+# -+# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set -+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m -+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m -+CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m -+CONFIG_NETFILTER_XT_TARGET_CT=m -+CONFIG_NETFILTER_XT_TARGET_DSCP=m -+CONFIG_NETFILTER_XT_TARGET_HL=m -+CONFIG_NETFILTER_XT_TARGET_HMARK=m -+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m -+CONFIG_NETFILTER_XT_TARGET_LED=m -+CONFIG_NETFILTER_XT_TARGET_LOG=m -+CONFIG_NETFILTER_XT_TARGET_MARK=m -+CONFIG_NETFILTER_XT_NAT=m -+CONFIG_NETFILTER_XT_TARGET_NETMAP=m -+CONFIG_NETFILTER_XT_TARGET_NFLOG=m -+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m -+CONFIG_NETFILTER_XT_TARGET_RATEEST=m -+CONFIG_NETFILTER_XT_TARGET_REDIRECT=m -+CONFIG_NETFILTER_XT_TARGET_TEE=m -+CONFIG_NETFILTER_XT_TARGET_TPROXY=m -+CONFIG_NETFILTER_XT_TARGET_TRACE=m -+CONFIG_NETFILTER_XT_TARGET_SECMARK=m -+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m -+ -+# -+# Xtables matches -+# -+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m -+CONFIG_NETFILTER_XT_MATCH_BPF=m -+CONFIG_NETFILTER_XT_MATCH_CGROUP=m -+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m -+CONFIG_NETFILTER_XT_MATCH_COMMENT=m -+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m -+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m -+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -+CONFIG_NETFILTER_XT_MATCH_CPU=m -+CONFIG_NETFILTER_XT_MATCH_DCCP=m -+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m -+CONFIG_NETFILTER_XT_MATCH_DSCP=m -+CONFIG_NETFILTER_XT_MATCH_ECN=m -+CONFIG_NETFILTER_XT_MATCH_ESP=m -+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m -+CONFIG_NETFILTER_XT_MATCH_HELPER=m -+CONFIG_NETFILTER_XT_MATCH_HL=m -+CONFIG_NETFILTER_XT_MATCH_IPCOMP=m -+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m -+CONFIG_NETFILTER_XT_MATCH_IPVS=m -+CONFIG_NETFILTER_XT_MATCH_L2TP=m -+CONFIG_NETFILTER_XT_MATCH_LENGTH=m -+CONFIG_NETFILTER_XT_MATCH_LIMIT=m -+CONFIG_NETFILTER_XT_MATCH_MAC=m -+CONFIG_NETFILTER_XT_MATCH_MARK=m -+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -+CONFIG_NETFILTER_XT_MATCH_NFACCT=m -+CONFIG_NETFILTER_XT_MATCH_OSF=m -+CONFIG_NETFILTER_XT_MATCH_OWNER=m -+CONFIG_NETFILTER_XT_MATCH_POLICY=m -+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m -+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -+CONFIG_NETFILTER_XT_MATCH_QUOTA=m -+CONFIG_NETFILTER_XT_MATCH_RATEEST=m -+CONFIG_NETFILTER_XT_MATCH_REALM=m -+CONFIG_NETFILTER_XT_MATCH_RECENT=m -+CONFIG_NETFILTER_XT_MATCH_SCTP=m -+CONFIG_NETFILTER_XT_MATCH_SOCKET=m -+CONFIG_NETFILTER_XT_MATCH_STATE=m -+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -+CONFIG_NETFILTER_XT_MATCH_STRING=m -+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -+CONFIG_NETFILTER_XT_MATCH_TIME=m -+CONFIG_NETFILTER_XT_MATCH_U32=m -+CONFIG_IP_SET=m -+CONFIG_IP_SET_MAX=256 -+CONFIG_IP_SET_BITMAP_IP=m -+CONFIG_IP_SET_BITMAP_IPMAC=m -+CONFIG_IP_SET_BITMAP_PORT=m -+CONFIG_IP_SET_HASH_IP=m -+# CONFIG_IP_SET_HASH_IPMARK is not set -+CONFIG_IP_SET_HASH_IPPORT=m -+CONFIG_IP_SET_HASH_IPPORTIP=m -+CONFIG_IP_SET_HASH_IPPORTNET=m -+# CONFIG_IP_SET_HASH_MAC is not set -+CONFIG_IP_SET_HASH_NETPORTNET=m -+CONFIG_IP_SET_HASH_NET=m -+CONFIG_IP_SET_HASH_NETNET=m -+CONFIG_IP_SET_HASH_NETPORT=m -+CONFIG_IP_SET_HASH_NETIFACE=m -+CONFIG_IP_SET_LIST_SET=m -+CONFIG_IP_VS=m -+CONFIG_IP_VS_IPV6=y -+# CONFIG_IP_VS_DEBUG is not set -+CONFIG_IP_VS_TAB_BITS=12 -+ -+# -+# IPVS transport protocol load balancing support -+# -+CONFIG_IP_VS_PROTO_TCP=y -+CONFIG_IP_VS_PROTO_UDP=y -+CONFIG_IP_VS_PROTO_AH_ESP=y -+CONFIG_IP_VS_PROTO_ESP=y -+CONFIG_IP_VS_PROTO_AH=y -+CONFIG_IP_VS_PROTO_SCTP=y -+ -+# -+# IPVS scheduler -+# -+CONFIG_IP_VS_RR=m -+CONFIG_IP_VS_WRR=m -+CONFIG_IP_VS_LC=m -+CONFIG_IP_VS_WLC=m -+# CONFIG_IP_VS_FO is not set -+CONFIG_IP_VS_LBLC=m -+CONFIG_IP_VS_LBLCR=m -+CONFIG_IP_VS_DH=m -+CONFIG_IP_VS_SH=m -+CONFIG_IP_VS_SED=m -+CONFIG_IP_VS_NQ=m -+ -+# -+# IPVS SH scheduler -+# -+CONFIG_IP_VS_SH_TAB_BITS=8 -+ -+# -+# IPVS application helper -+# -+# CONFIG_IP_VS_FTP is not set -+CONFIG_IP_VS_NFCT=y -+# CONFIG_IP_VS_PE_SIP is not set -+ -+# -+# IP: Netfilter Configuration -+# -+CONFIG_NF_DEFRAG_IPV4=m -+CONFIG_NF_CONNTRACK_IPV4=m -+CONFIG_NF_CONNTRACK_PROC_COMPAT=y -+CONFIG_NF_TABLES_IPV4=m -+CONFIG_NFT_CHAIN_ROUTE_IPV4=m -+CONFIG_NFT_REJECT_IPV4=m -+CONFIG_NF_TABLES_ARP=m -+# CONFIG_NF_LOG_ARP is not set -+CONFIG_NF_LOG_IPV4=m -+CONFIG_NF_REJECT_IPV4=m -+CONFIG_NF_NAT_IPV4=m -+CONFIG_NFT_CHAIN_NAT_IPV4=m -+CONFIG_NF_NAT_MASQUERADE_IPV4=m -+CONFIG_NF_NAT_SNMP_BASIC=m -+CONFIG_NF_NAT_PROTO_GRE=m -+CONFIG_NF_NAT_PPTP=m -+CONFIG_NF_NAT_H323=m -+CONFIG_IP_NF_IPTABLES=m -+CONFIG_IP_NF_MATCH_AH=m -+CONFIG_IP_NF_MATCH_ECN=m -+CONFIG_IP_NF_MATCH_RPFILTER=m -+CONFIG_IP_NF_MATCH_TTL=m -+CONFIG_IP_NF_FILTER=m -+CONFIG_IP_NF_TARGET_REJECT=m -+CONFIG_IP_NF_TARGET_SYNPROXY=m -+CONFIG_IP_NF_NAT=m -+CONFIG_IP_NF_TARGET_MASQUERADE=m -+CONFIG_IP_NF_TARGET_NETMAP=m -+CONFIG_IP_NF_TARGET_REDIRECT=m -+CONFIG_IP_NF_MANGLE=m -+CONFIG_IP_NF_TARGET_CLUSTERIP=m -+CONFIG_IP_NF_TARGET_ECN=m -+CONFIG_IP_NF_TARGET_TTL=m -+CONFIG_IP_NF_RAW=m -+CONFIG_IP_NF_ARPTABLES=m -+CONFIG_IP_NF_ARPFILTER=m -+CONFIG_IP_NF_ARP_MANGLE=m -+ -+# -+# IPv6: Netfilter Configuration -+# -+CONFIG_NF_DEFRAG_IPV6=m -+CONFIG_NF_CONNTRACK_IPV6=m -+CONFIG_NF_TABLES_IPV6=m -+CONFIG_NFT_CHAIN_ROUTE_IPV6=m -+CONFIG_NFT_REJECT_IPV6=m -+CONFIG_NF_REJECT_IPV6=m -+CONFIG_NF_LOG_IPV6=m -+CONFIG_NF_NAT_IPV6=m -+CONFIG_NFT_CHAIN_NAT_IPV6=m -+CONFIG_NF_NAT_MASQUERADE_IPV6=m -+CONFIG_IP6_NF_IPTABLES=m -+CONFIG_IP6_NF_MATCH_AH=m -+CONFIG_IP6_NF_MATCH_EUI64=m -+CONFIG_IP6_NF_MATCH_FRAG=m -+CONFIG_IP6_NF_MATCH_OPTS=m -+CONFIG_IP6_NF_MATCH_HL=m -+CONFIG_IP6_NF_MATCH_IPV6HEADER=m -+CONFIG_IP6_NF_MATCH_MH=m -+CONFIG_IP6_NF_MATCH_RPFILTER=m -+CONFIG_IP6_NF_MATCH_RT=m -+CONFIG_IP6_NF_TARGET_HL=m -+CONFIG_IP6_NF_FILTER=m -+CONFIG_IP6_NF_TARGET_REJECT=m -+CONFIG_IP6_NF_TARGET_SYNPROXY=m -+CONFIG_IP6_NF_MANGLE=m -+CONFIG_IP6_NF_RAW=m -+CONFIG_IP6_NF_NAT=m -+CONFIG_IP6_NF_TARGET_MASQUERADE=m -+CONFIG_IP6_NF_TARGET_NPT=m -+CONFIG_NF_TABLES_BRIDGE=m -+# CONFIG_NFT_BRIDGE_META is not set -+# CONFIG_NFT_BRIDGE_REJECT is not set -+# CONFIG_NF_LOG_BRIDGE is not set -+CONFIG_BRIDGE_NF_EBTABLES=m -+CONFIG_BRIDGE_EBT_BROUTE=m -+CONFIG_BRIDGE_EBT_T_FILTER=m -+CONFIG_BRIDGE_EBT_T_NAT=m -+CONFIG_BRIDGE_EBT_802_3=m -+CONFIG_BRIDGE_EBT_AMONG=m -+CONFIG_BRIDGE_EBT_ARP=m -+CONFIG_BRIDGE_EBT_IP=m -+CONFIG_BRIDGE_EBT_IP6=m -+CONFIG_BRIDGE_EBT_LIMIT=m -+CONFIG_BRIDGE_EBT_MARK=m -+CONFIG_BRIDGE_EBT_PKTTYPE=m -+CONFIG_BRIDGE_EBT_STP=m -+CONFIG_BRIDGE_EBT_VLAN=m -+CONFIG_BRIDGE_EBT_ARPREPLY=m -+CONFIG_BRIDGE_EBT_DNAT=m -+CONFIG_BRIDGE_EBT_MARK_T=m -+CONFIG_BRIDGE_EBT_REDIRECT=m -+CONFIG_BRIDGE_EBT_SNAT=m -+CONFIG_BRIDGE_EBT_LOG=m -+CONFIG_BRIDGE_EBT_NFLOG=m -+CONFIG_IP_DCCP=m -+CONFIG_INET_DCCP_DIAG=m -+ -+# -+# DCCP CCIDs Configuration -+# -+# CONFIG_IP_DCCP_CCID2_DEBUG is not set -+CONFIG_IP_DCCP_CCID3=y -+# CONFIG_IP_DCCP_CCID3_DEBUG is not set -+CONFIG_IP_DCCP_TFRC_LIB=y -+ -+# -+# DCCP Kernel Hacking -+# -+# CONFIG_IP_DCCP_DEBUG is not set -+CONFIG_IP_SCTP=m -+CONFIG_SCTP_DBG_OBJCNT=y -+CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y -+# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set -+# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set -+CONFIG_SCTP_COOKIE_HMAC_MD5=y -+CONFIG_SCTP_COOKIE_HMAC_SHA1=y -+CONFIG_RDS=m -+# CONFIG_RDS_TCP is not set -+# CONFIG_RDS_DEBUG is not set -+CONFIG_TIPC=m -+CONFIG_TIPC_MEDIA_UDP=y -+# CONFIG_ATM is not set -+CONFIG_L2TP=m -+# CONFIG_L2TP_DEBUGFS is not set -+# CONFIG_L2TP_V3 is not set -+CONFIG_STP=m -+CONFIG_BRIDGE=m -+CONFIG_BRIDGE_IGMP_SNOOPING=y -+CONFIG_BRIDGE_VLAN_FILTERING=y -+CONFIG_HAVE_NET_DSA=y -+CONFIG_VLAN_8021Q=m -+# CONFIG_VLAN_8021Q_GVRP is not set -+# CONFIG_VLAN_8021Q_MVRP is not set -+# CONFIG_DECNET is not set -+CONFIG_LLC=m -+CONFIG_LLC2=m -+# CONFIG_IPX is not set -+CONFIG_ATALK=m -+CONFIG_DEV_APPLETALK=m -+CONFIG_IPDDP=m -+CONFIG_IPDDP_ENCAP=y -+# CONFIG_X25 is not set -+# CONFIG_LAPB is not set -+# CONFIG_PHONET is not set -+# CONFIG_6LOWPAN is not set -+# CONFIG_IEEE802154 is not set -+CONFIG_NET_SCHED=y -+ -+# -+# Queueing/Scheduling -+# -+CONFIG_NET_SCH_CBQ=y -+CONFIG_NET_SCH_HTB=y -+CONFIG_NET_SCH_HFSC=m -+CONFIG_NET_SCH_PRIO=y -+CONFIG_NET_SCH_MULTIQ=m -+CONFIG_NET_SCH_RED=m -+CONFIG_NET_SCH_SFB=m -+CONFIG_NET_SCH_SFQ=y -+CONFIG_NET_SCH_TEQL=m -+CONFIG_NET_SCH_TBF=m -+CONFIG_NET_SCH_GRED=m -+CONFIG_NET_SCH_DSMARK=m -+CONFIG_NET_SCH_NETEM=m -+CONFIG_NET_SCH_DRR=m -+CONFIG_NET_SCH_MQPRIO=m -+CONFIG_NET_SCH_CHOKE=m -+CONFIG_NET_SCH_QFQ=y -+CONFIG_NET_SCH_CODEL=m -+CONFIG_NET_SCH_FQ_CODEL=m -+CONFIG_NET_SCH_FQ=m -+CONFIG_NET_SCH_HHF=m -+CONFIG_NET_SCH_PIE=m -+CONFIG_NET_SCH_INGRESS=m -+CONFIG_NET_SCH_PLUG=m -+ -+# -+# Classification -+# -+CONFIG_NET_CLS=y -+CONFIG_NET_CLS_BASIC=m -+CONFIG_NET_CLS_TCINDEX=m -+CONFIG_NET_CLS_ROUTE4=m -+CONFIG_NET_CLS_FW=m -+CONFIG_NET_CLS_U32=m -+CONFIG_CLS_U32_PERF=y -+CONFIG_CLS_U32_MARK=y -+CONFIG_NET_CLS_RSVP=m -+CONFIG_NET_CLS_RSVP6=m -+CONFIG_NET_CLS_FLOW=m -+CONFIG_NET_CLS_CGROUP=m -+CONFIG_NET_CLS_BPF=m -+CONFIG_NET_EMATCH=y -+CONFIG_NET_EMATCH_STACK=32 -+CONFIG_NET_EMATCH_CMP=m -+CONFIG_NET_EMATCH_NBYTE=m -+CONFIG_NET_EMATCH_U32=m -+CONFIG_NET_EMATCH_META=m -+CONFIG_NET_EMATCH_TEXT=m -+# CONFIG_NET_EMATCH_CANID is not set -+CONFIG_NET_EMATCH_IPSET=m -+CONFIG_NET_CLS_ACT=y -+CONFIG_NET_ACT_POLICE=m -+CONFIG_NET_ACT_GACT=m -+CONFIG_GACT_PROB=y -+CONFIG_NET_ACT_MIRRED=m -+CONFIG_NET_ACT_IPT=m -+CONFIG_NET_ACT_NAT=m -+CONFIG_NET_ACT_PEDIT=m -+CONFIG_NET_ACT_SIMP=m -+CONFIG_NET_ACT_SKBEDIT=m -+CONFIG_NET_ACT_CSUM=m -+# CONFIG_NET_ACT_VLAN is not set -+# CONFIG_NET_ACT_BPF is not set -+# CONFIG_NET_ACT_CONNMARK is not set -+CONFIG_NET_CLS_IND=y -+CONFIG_NET_SCH_FIFO=y -+# CONFIG_DCB is not set -+CONFIG_DNS_RESOLVER=y -+# CONFIG_BATMAN_ADV is not set -+CONFIG_OPENVSWITCH=m -+CONFIG_OPENVSWITCH_VXLAN=m -+# CONFIG_VSOCKETS is not set -+CONFIG_NETLINK_MMAP=y -+CONFIG_NETLINK_DIAG=m -+CONFIG_MPLS=y -+CONFIG_NET_MPLS_GSO=m -+# CONFIG_MPLS_ROUTING is not set -+# CONFIG_HSR is not set -+# CONFIG_NET_SWITCHDEV is not set -+CONFIG_RPS=y -+CONFIG_RFS_ACCEL=y -+CONFIG_XPS=y -+CONFIG_CGROUP_NET_PRIO=y -+CONFIG_CGROUP_NET_CLASSID=y -+CONFIG_NET_RX_BUSY_POLL=y -+CONFIG_BQL=y -+# CONFIG_BPF_JIT is not set -+CONFIG_NET_FLOW_LIMIT=y -+ -+# -+# Network testing -+# -+# CONFIG_NET_PKTGEN is not set -+# CONFIG_HAMRADIO is not set -+CONFIG_CAN=m -+CONFIG_CAN_RAW=m -+CONFIG_CAN_BCM=m -+CONFIG_CAN_GW=m -+ -+# -+# CAN Device Drivers -+# -+# CONFIG_CAN_VCAN is not set -+# CONFIG_CAN_SLCAN is not set -+CONFIG_CAN_DEV=m -+CONFIG_CAN_CALC_BITTIMING=y -+# CONFIG_CAN_LEDS is not set -+# CONFIG_CAN_TI_HECC is not set -+CONFIG_CAN_FLEXCAN=m -+# CONFIG_CAN_GRCAN is not set -+# CONFIG_CAN_RCAR is not set -+# CONFIG_CAN_SJA1000 is not set -+# CONFIG_CAN_C_CAN is not set -+# CONFIG_CAN_M_CAN is not set -+# CONFIG_CAN_CC770 is not set -+ -+# -+# CAN SPI interfaces -+# -+# CONFIG_CAN_MCP251X is not set -+ -+# -+# CAN USB interfaces -+# -+CONFIG_CAN_EMS_USB=m -+CONFIG_CAN_ESD_USB2=m -+CONFIG_CAN_GS_USB=m -+CONFIG_CAN_KVASER_USB=m -+CONFIG_CAN_PEAK_USB=m -+CONFIG_CAN_8DEV_USB=m -+# CONFIG_CAN_SOFTING is not set -+# CONFIG_CAN_DEBUG_DEVICES is not set -+CONFIG_IRDA=m -+ -+# -+# IrDA protocols -+# -+CONFIG_IRLAN=m -+CONFIG_IRNET=m -+CONFIG_IRCOMM=m -+CONFIG_IRDA_ULTRA=y -+ -+# -+# IrDA options -+# -+# CONFIG_IRDA_CACHE_LAST_LSAP is not set -+CONFIG_IRDA_FAST_RR=y -+# CONFIG_IRDA_DEBUG is not set -+ -+# -+# Infrared-port device drivers -+# -+ -+# -+# SIR device drivers -+# -+CONFIG_IRTTY_SIR=m -+ -+# -+# Dongle support -+# -+CONFIG_DONGLE=y -+CONFIG_ESI_DONGLE=m -+CONFIG_ACTISYS_DONGLE=m -+CONFIG_TEKRAM_DONGLE=m -+CONFIG_TOIM3232_DONGLE=m -+CONFIG_LITELINK_DONGLE=m -+CONFIG_MA600_DONGLE=m -+CONFIG_GIRBIL_DONGLE=m -+CONFIG_MCP2120_DONGLE=m -+CONFIG_OLD_BELKIN_DONGLE=m -+CONFIG_ACT200L_DONGLE=m -+CONFIG_KINGSUN_DONGLE=m -+CONFIG_KSDAZZLE_DONGLE=m -+CONFIG_KS959_DONGLE=m -+ -+# -+# FIR device drivers -+# -+CONFIG_USB_IRDA=m -+CONFIG_SIGMATEL_FIR=m -+CONFIG_VLSI_FIR=m -+CONFIG_MCS_FIR=m -+CONFIG_BT=y -+CONFIG_BT_BREDR=y -+CONFIG_BT_RFCOMM=y -+CONFIG_BT_RFCOMM_TTY=y -+CONFIG_BT_BNEP=y -+CONFIG_BT_BNEP_MC_FILTER=y -+CONFIG_BT_BNEP_PROTO_FILTER=y -+CONFIG_BT_CMTP=m -+CONFIG_BT_HIDP=m -+CONFIG_BT_LE=y -+# CONFIG_BT_SELFTEST is not set -+CONFIG_BT_DEBUGFS=y -+ -+# -+# Bluetooth device drivers -+# -+CONFIG_BT_INTEL=m -+CONFIG_BT_BCM=m -+CONFIG_BT_RTL=m -+CONFIG_BT_HCIBTUSB=m -+CONFIG_BT_HCIBTUSB_BCM=y -+CONFIG_BT_HCIBTUSB_RTL=y -+CONFIG_BT_HCIBTSDIO=y -+CONFIG_BT_HCIUART=y -+CONFIG_BT_HCIUART_H4=y -+CONFIG_BT_HCIUART_BCSP=y -+CONFIG_BT_HCIUART_ATH3K=y -+CONFIG_BT_HCIUART_LL=y -+CONFIG_BT_HCIUART_3WIRE=y -+# CONFIG_BT_HCIUART_INTEL is not set -+# CONFIG_BT_HCIUART_BCM is not set -+CONFIG_BT_HCIBCM203X=m -+CONFIG_BT_HCIBPA10X=m -+CONFIG_BT_HCIBFUSB=m -+CONFIG_BT_HCIVHCI=m -+CONFIG_BT_MRVL=m -+CONFIG_BT_MRVL_SDIO=m -+CONFIG_BT_ATH3K=m -+# CONFIG_BT_WILINK is not set -+CONFIG_AF_RXRPC=m -+# CONFIG_AF_RXRPC_DEBUG is not set -+# CONFIG_RXKAD is not set -+CONFIG_FIB_RULES=y -+CONFIG_WIRELESS=y -+CONFIG_WIRELESS_EXT=y -+CONFIG_WEXT_CORE=y -+CONFIG_WEXT_PROC=y -+CONFIG_WEXT_SPY=y -+CONFIG_WEXT_PRIV=y -+CONFIG_CFG80211=m -+# CONFIG_NL80211_TESTMODE is not set -+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set -+# CONFIG_CFG80211_REG_DEBUG is not set -+# CONFIG_CFG80211_CERTIFICATION_ONUS is not set -+# CONFIG_CFG80211_DEFAULT_PS is not set -+# CONFIG_CFG80211_DEBUGFS is not set -+# CONFIG_CFG80211_INTERNAL_REGDB is not set -+CONFIG_CFG80211_WEXT=y -+CONFIG_CFG80211_WEXT_EXPORT=y -+CONFIG_LIB80211=m -+CONFIG_LIB80211_CRYPT_WEP=m -+CONFIG_LIB80211_CRYPT_CCMP=m -+CONFIG_LIB80211_CRYPT_TKIP=m -+# CONFIG_LIB80211_DEBUG is not set -+CONFIG_MAC80211=m -+CONFIG_MAC80211_HAS_RC=y -+CONFIG_MAC80211_RC_MINSTREL=y -+CONFIG_MAC80211_RC_MINSTREL_HT=y -+CONFIG_MAC80211_RC_MINSTREL_VHT=y -+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y -+CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" -+CONFIG_MAC80211_MESH=y -+CONFIG_MAC80211_LEDS=y -+# CONFIG_MAC80211_DEBUGFS is not set -+# CONFIG_MAC80211_MESSAGE_TRACING is not set -+CONFIG_MAC80211_DEBUG_MENU=y -+# CONFIG_MAC80211_NOINLINE is not set -+# CONFIG_MAC80211_VERBOSE_DEBUG is not set -+# CONFIG_MAC80211_MLME_DEBUG is not set -+# CONFIG_MAC80211_STA_DEBUG is not set -+# CONFIG_MAC80211_HT_DEBUG is not set -+# CONFIG_MAC80211_OCB_DEBUG is not set -+# CONFIG_MAC80211_IBSS_DEBUG is not set -+# CONFIG_MAC80211_PS_DEBUG is not set -+# CONFIG_MAC80211_MPL_DEBUG is not set -+# CONFIG_MAC80211_MPATH_DEBUG is not set -+# CONFIG_MAC80211_MHWMP_DEBUG is not set -+# CONFIG_MAC80211_MESH_SYNC_DEBUG is not set -+# CONFIG_MAC80211_MESH_CSA_DEBUG is not set -+# CONFIG_MAC80211_MESH_PS_DEBUG is not set -+# CONFIG_MAC80211_TDLS_DEBUG is not set -+# CONFIG_WIMAX is not set -+CONFIG_RFKILL=y -+CONFIG_RFKILL_LEDS=y -+CONFIG_RFKILL_INPUT=y -+CONFIG_RFKILL_REGULATOR=y -+CONFIG_RFKILL_GPIO=y -+# CONFIG_NET_9P is not set -+CONFIG_CAIF=m -+# CONFIG_CAIF_DEBUG is not set -+CONFIG_CAIF_NETDEV=m -+CONFIG_CAIF_USB=m -+CONFIG_CEPH_LIB=m -+# CONFIG_CEPH_LIB_PRETTYDEBUG is not set -+CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y -+CONFIG_NFC=m -+# CONFIG_NFC_DIGITAL is not set -+# CONFIG_NFC_NCI is not set -+# CONFIG_NFC_HCI is not set -+ -+# -+# Near Field Communication (NFC) devices -+# -+# CONFIG_NFC_PN533 is not set -+# CONFIG_NFC_SIM is not set -+CONFIG_HAVE_BPF_JIT=y -+ -+# -+# Device Drivers -+# -+ -+# -+# Generic Driver Options -+# -+CONFIG_UEVENT_HELPER=y -+CONFIG_UEVENT_HELPER_PATH="" -+CONFIG_DEVTMPFS=y -+CONFIG_DEVTMPFS_MOUNT=y -+# CONFIG_STANDALONE is not set -+# CONFIG_PREVENT_FIRMWARE_BUILD is not set -+CONFIG_FW_LOADER=y -+CONFIG_FIRMWARE_IN_KERNEL=y -+CONFIG_EXTRA_FIRMWARE="" -+CONFIG_FW_LOADER_USER_HELPER=y -+CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y -+CONFIG_WANT_DEV_COREDUMP=y -+CONFIG_ALLOW_DEV_COREDUMP=y -+CONFIG_DEV_COREDUMP=y -+# CONFIG_DEBUG_DRIVER is not set -+# CONFIG_DEBUG_DEVRES is not set -+# CONFIG_SYS_HYPERVISOR is not set -+# CONFIG_GENERIC_CPU_DEVICES is not set -+CONFIG_SOC_BUS=y -+CONFIG_REGMAP=y -+CONFIG_REGMAP_I2C=y -+CONFIG_REGMAP_SPI=y -+CONFIG_REGMAP_MMIO=y -+CONFIG_REGMAP_IRQ=y -+CONFIG_DMA_SHARED_BUFFER=y -+# CONFIG_FENCE_TRACE is not set -+CONFIG_DMA_CMA=y -+ -+# -+# Default contiguous memory area size: -+# -+CONFIG_CMA_SIZE_MBYTES=288 -+CONFIG_CMA_SIZE_SEL_MBYTES=y -+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set -+# CONFIG_CMA_SIZE_SEL_MIN is not set -+# CONFIG_CMA_SIZE_SEL_MAX is not set -+CONFIG_CMA_ALIGNMENT=8 -+ -+# -+# Bus devices -+# -+CONFIG_ARM_CCI=y -+CONFIG_ARM_CCI400_COMMON=y -+CONFIG_ARM_CCI400_PMU=y -+CONFIG_ARM_CCN=y -+# CONFIG_BRCMSTB_GISB_ARB is not set -+CONFIG_IMX_WEIM=y -+# CONFIG_VEXPRESS_CONFIG is not set -+CONFIG_CONNECTOR=y -+CONFIG_PROC_EVENTS=y -+CONFIG_MTD=y -+# CONFIG_MTD_TESTS is not set -+# CONFIG_MTD_REDBOOT_PARTS is not set -+CONFIG_MTD_CMDLINE_PARTS=y -+# CONFIG_MTD_AFS_PARTS is not set -+CONFIG_MTD_OF_PARTS=y -+# CONFIG_MTD_AR7_PARTS is not set -+ -+# -+# User Modules And Translation Layers -+# -+CONFIG_MTD_BLKDEVS=y -+CONFIG_MTD_BLOCK=y -+# CONFIG_FTL is not set -+# CONFIG_NFTL is not set -+# CONFIG_INFTL is not set -+# CONFIG_RFD_FTL is not set -+# CONFIG_SSFDC is not set -+# CONFIG_SM_FTL is not set -+# CONFIG_MTD_OOPS is not set -+# CONFIG_MTD_SWAP is not set -+# CONFIG_MTD_PARTITIONED_MASTER is not set -+ -+# -+# RAM/ROM/Flash chip drivers -+# -+CONFIG_MTD_CFI=y -+CONFIG_MTD_JEDECPROBE=y -+CONFIG_MTD_GEN_PROBE=y -+# CONFIG_MTD_CFI_ADV_OPTIONS is not set -+CONFIG_MTD_MAP_BANK_WIDTH_1=y -+CONFIG_MTD_MAP_BANK_WIDTH_2=y -+CONFIG_MTD_MAP_BANK_WIDTH_4=y -+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -+CONFIG_MTD_CFI_I1=y -+CONFIG_MTD_CFI_I2=y -+# CONFIG_MTD_CFI_I4 is not set -+# CONFIG_MTD_CFI_I8 is not set -+CONFIG_MTD_CFI_INTELEXT=y -+CONFIG_MTD_CFI_AMDSTD=y -+CONFIG_MTD_CFI_STAA=y -+CONFIG_MTD_CFI_UTIL=y -+# CONFIG_MTD_RAM is not set -+# CONFIG_MTD_ROM is not set -+# CONFIG_MTD_ABSENT is not set -+ -+# -+# Mapping drivers for chip access -+# -+# CONFIG_MTD_COMPLEX_MAPPINGS is not set -+# CONFIG_MTD_PHYSMAP is not set -+CONFIG_MTD_PHYSMAP_OF=y -+# CONFIG_MTD_IMPA7 is not set -+# CONFIG_MTD_INTEL_VR_NOR is not set -+# CONFIG_MTD_PLATRAM is not set -+ -+# -+# Self-contained MTD device drivers -+# -+# CONFIG_MTD_PMC551 is not set -+CONFIG_MTD_DATAFLASH=y -+# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set -+# CONFIG_MTD_DATAFLASH_OTP is not set -+# CONFIG_MTD_M25P80 is not set -+CONFIG_MTD_SST25L=y -+# CONFIG_MTD_SLRAM is not set -+# CONFIG_MTD_PHRAM is not set -+# CONFIG_MTD_MTDRAM is not set -+# CONFIG_MTD_BLOCK2MTD is not set -+ -+# -+# Disk-On-Chip Device Drivers -+# -+# CONFIG_MTD_DOCG3 is not set -+CONFIG_MTD_NAND_ECC=y -+# CONFIG_MTD_NAND_ECC_SMC is not set -+CONFIG_MTD_NAND=y -+# CONFIG_MTD_NAND_ECC_BCH is not set -+# CONFIG_MTD_SM_COMMON is not set -+# CONFIG_MTD_NAND_DENALI is not set -+# CONFIG_MTD_NAND_GPIO is not set -+# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set -+CONFIG_MTD_NAND_IDS=y -+# CONFIG_MTD_NAND_RICOH is not set -+# CONFIG_MTD_NAND_DISKONCHIP is not set -+# CONFIG_MTD_NAND_DOCG4 is not set -+# CONFIG_MTD_NAND_CAFE is not set -+# CONFIG_MTD_NAND_NANDSIM is not set -+# CONFIG_MTD_NAND_GPMI_NAND is not set -+# CONFIG_MTD_NAND_PLATFORM is not set -+CONFIG_MTD_NAND_MXC=y -+# CONFIG_MTD_NAND_HISI504 is not set -+# CONFIG_MTD_ONENAND is not set -+ -+# -+# LPDDR & LPDDR2 PCM memory drivers -+# -+# CONFIG_MTD_LPDDR is not set -+# CONFIG_MTD_LPDDR2_NVM is not set -+CONFIG_MTD_SPI_NOR=m -+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y -+CONFIG_SPI_FSL_QUADSPI=m -+CONFIG_MTD_UBI=y -+CONFIG_MTD_UBI_WL_THRESHOLD=4096 -+CONFIG_MTD_UBI_BEB_LIMIT=20 -+# CONFIG_MTD_UBI_FASTMAP is not set -+# CONFIG_MTD_UBI_GLUEBI is not set -+# CONFIG_MTD_UBI_BLOCK is not set -+CONFIG_DTC=y -+CONFIG_OF=y -+ -+# -+# Device Tree and Open Firmware support -+# -+# CONFIG_OF_UNITTEST is not set -+CONFIG_OF_FLATTREE=y -+CONFIG_OF_EARLY_FLATTREE=y -+CONFIG_OF_ADDRESS=y -+CONFIG_OF_ADDRESS_PCI=y -+CONFIG_OF_IRQ=y -+CONFIG_OF_NET=y -+CONFIG_OF_MDIO=y -+CONFIG_OF_PCI=y -+CONFIG_OF_PCI_IRQ=y -+CONFIG_OF_MTD=y -+CONFIG_OF_RESERVED_MEM=y -+# CONFIG_OF_OVERLAY is not set -+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -+# CONFIG_PARPORT is not set -+CONFIG_BLK_DEV=y -+# CONFIG_BLK_DEV_NULL_BLK is not set -+# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set -+# CONFIG_BLK_CPQ_CISS_DA is not set -+# CONFIG_BLK_DEV_DAC960 is not set -+# CONFIG_BLK_DEV_UMEM is not set -+# CONFIG_BLK_DEV_COW_COMMON is not set -+CONFIG_BLK_DEV_LOOP=m -+CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 -+CONFIG_BLK_DEV_CRYPTOLOOP=m -+# CONFIG_BLK_DEV_DRBD is not set -+# CONFIG_BLK_DEV_NBD is not set -+# CONFIG_BLK_DEV_NVME is not set -+# CONFIG_BLK_DEV_SX8 is not set -+CONFIG_BLK_DEV_RAM=m -+CONFIG_BLK_DEV_RAM_COUNT=16 -+CONFIG_BLK_DEV_RAM_SIZE=65536 -+# CONFIG_BLK_DEV_PMEM is not set -+# CONFIG_CDROM_PKTCDVD is not set -+# CONFIG_ATA_OVER_ETH is not set -+CONFIG_MG_DISK=y -+CONFIG_MG_DISK_RES=0 -+# CONFIG_BLK_DEV_RBD is not set -+# CONFIG_BLK_DEV_RSXX is not set -+ -+# -+# Misc devices -+# -+# CONFIG_SENSORS_LIS3LV02D is not set -+# CONFIG_AD525X_DPOT is not set -+# CONFIG_DUMMY_IRQ is not set -+# CONFIG_PHANTOM is not set -+# CONFIG_SGI_IOC4 is not set -+CONFIG_TIFM_CORE=y -+CONFIG_TIFM_7XX1=y -+# CONFIG_ICS932S401 is not set -+CONFIG_ENCLOSURE_SERVICES=y -+# CONFIG_HP_ILO is not set -+# CONFIG_APDS9802ALS is not set -+# CONFIG_ISL29003 is not set -+# CONFIG_ISL29020 is not set -+# CONFIG_SENSORS_TSL2550 is not set -+# CONFIG_SENSORS_BH1780 is not set -+# CONFIG_SENSORS_BH1770 is not set -+# CONFIG_SENSORS_APDS990X is not set -+# CONFIG_HMC6352 is not set -+# CONFIG_DS1682 is not set -+# CONFIG_TI_DAC7512 is not set -+# CONFIG_BMP085_I2C is not set -+# CONFIG_BMP085_SPI is not set -+# CONFIG_USB_SWITCH_FSA9480 is not set -+# CONFIG_LATTICE_ECP3_CONFIG is not set -+CONFIG_SRAM=y -+# CONFIG_C2PORT is not set -+ -+# -+# EEPROM support -+# -+CONFIG_EEPROM_AT24=y -+CONFIG_EEPROM_AT25=y -+# CONFIG_EEPROM_LEGACY is not set -+CONFIG_EEPROM_MAX6875=y -+CONFIG_EEPROM_93CX6=m -+# CONFIG_EEPROM_93XX46 is not set -+CONFIG_CB710_CORE=y -+# CONFIG_CB710_DEBUG is not set -+CONFIG_CB710_DEBUG_ASSUMPTIONS=y -+ -+# -+# Texas Instruments shared transport line discipline -+# -+CONFIG_TI_ST=m -+# CONFIG_SENSORS_LIS3_SPI is not set -+# CONFIG_SENSORS_LIS3_I2C is not set -+ -+# -+# Altera FPGA firmware download module -+# -+CONFIG_ALTERA_STAPL=m -+ -+# -+# Intel MIC Bus Driver -+# -+ -+# -+# Intel MIC Host Driver -+# -+ -+# -+# Intel MIC Card Driver -+# -+CONFIG_ECHO=m -+# CONFIG_CXL_BASE is not set -+CONFIG_HAVE_IDE=y -+# CONFIG_IDE is not set -+ -+# -+# SCSI device support -+# -+CONFIG_SCSI_MOD=y -+# CONFIG_RAID_ATTRS is not set -+CONFIG_SCSI=y -+CONFIG_SCSI_DMA=y -+CONFIG_SCSI_NETLINK=y -+# CONFIG_SCSI_MQ_DEFAULT is not set -+# CONFIG_SCSI_PROC_FS is not set -+ -+# -+# SCSI support type (disk, tape, CD-ROM) -+# -+CONFIG_BLK_DEV_SD=y -+# CONFIG_CHR_DEV_ST is not set -+# CONFIG_CHR_DEV_OSST is not set -+CONFIG_BLK_DEV_SR=y -+CONFIG_BLK_DEV_SR_VENDOR=y -+CONFIG_CHR_DEV_SG=y -+CONFIG_CHR_DEV_SCH=y -+CONFIG_SCSI_ENCLOSURE=y -+# CONFIG_SCSI_CONSTANTS is not set -+CONFIG_SCSI_LOGGING=y -+CONFIG_SCSI_SCAN_ASYNC=y -+ -+# -+# SCSI Transports -+# -+# CONFIG_SCSI_SPI_ATTRS is not set -+CONFIG_SCSI_FC_ATTRS=m -+CONFIG_SCSI_ISCSI_ATTRS=m -+# CONFIG_SCSI_SAS_ATTRS is not set -+# CONFIG_SCSI_SAS_LIBSAS is not set -+# CONFIG_SCSI_SRP_ATTRS is not set -+CONFIG_SCSI_LOWLEVEL=y -+CONFIG_ISCSI_TCP=m -+CONFIG_ISCSI_BOOT_SYSFS=m -+# CONFIG_SCSI_CXGB3_ISCSI is not set -+# CONFIG_SCSI_CXGB4_ISCSI is not set -+# CONFIG_SCSI_BNX2_ISCSI is not set -+# CONFIG_SCSI_BNX2X_FCOE is not set -+# CONFIG_BE2ISCSI is not set -+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -+# CONFIG_SCSI_HPSA is not set -+# CONFIG_SCSI_3W_9XXX is not set -+# CONFIG_SCSI_3W_SAS is not set -+# CONFIG_SCSI_ACARD is not set -+# CONFIG_SCSI_AACRAID is not set -+# CONFIG_SCSI_AIC7XXX is not set -+# CONFIG_SCSI_AIC79XX is not set -+# CONFIG_SCSI_AIC94XX is not set -+# CONFIG_SCSI_MVSAS is not set -+# CONFIG_SCSI_MVUMI is not set -+# CONFIG_SCSI_ARCMSR is not set -+# CONFIG_SCSI_ESAS2R is not set -+# CONFIG_MEGARAID_NEWGEN is not set -+# CONFIG_MEGARAID_LEGACY is not set -+# CONFIG_MEGARAID_SAS is not set -+# CONFIG_SCSI_MPT2SAS is not set -+# CONFIG_SCSI_MPT3SAS is not set -+CONFIG_SCSI_UFSHCD=m -+# CONFIG_SCSI_UFSHCD_PCI is not set -+CONFIG_SCSI_UFSHCD_PLATFORM=m -+# CONFIG_SCSI_HPTIOP is not set -+CONFIG_LIBFC=m -+CONFIG_LIBFCOE=m -+# CONFIG_FCOE is not set -+# CONFIG_SCSI_DMX3191D is not set -+# CONFIG_SCSI_FUTURE_DOMAIN is not set -+# CONFIG_SCSI_IPS is not set -+# CONFIG_SCSI_INITIO is not set -+# CONFIG_SCSI_INIA100 is not set -+# CONFIG_SCSI_STEX is not set -+# CONFIG_SCSI_SYM53C8XX_2 is not set -+# CONFIG_SCSI_IPR is not set -+# CONFIG_SCSI_QLOGIC_1280 is not set -+# CONFIG_SCSI_QLA_FC is not set -+# CONFIG_SCSI_QLA_ISCSI is not set -+# CONFIG_SCSI_LPFC is not set -+# CONFIG_SCSI_DC395x is not set -+# CONFIG_SCSI_AM53C974 is not set -+# CONFIG_SCSI_NSP32 is not set -+# CONFIG_SCSI_WD719X is not set -+# CONFIG_SCSI_DEBUG is not set -+# CONFIG_SCSI_PMCRAID is not set -+# CONFIG_SCSI_PM8001 is not set -+# CONFIG_SCSI_BFA_FC is not set -+# CONFIG_SCSI_CHELSIO_FCOE is not set -+CONFIG_SCSI_DH=m -+CONFIG_SCSI_DH_RDAC=m -+CONFIG_SCSI_DH_HP_SW=m -+CONFIG_SCSI_DH_EMC=m -+CONFIG_SCSI_DH_ALUA=m -+CONFIG_SCSI_OSD_INITIATOR=m -+# CONFIG_SCSI_OSD_ULD is not set -+CONFIG_SCSI_OSD_DPRINT_SENSE=1 -+# CONFIG_SCSI_OSD_DEBUG is not set -+CONFIG_ATA=y -+# CONFIG_ATA_NONSTANDARD is not set -+# CONFIG_ATA_VERBOSE_ERROR is not set -+CONFIG_SATA_PMP=y -+ -+# -+# Controllers with non-SFF native interface -+# -+# CONFIG_SATA_AHCI is not set -+CONFIG_SATA_AHCI_PLATFORM=y -+CONFIG_AHCI_IMX=y -+# CONFIG_SATA_INIC162X is not set -+# CONFIG_SATA_ACARD_AHCI is not set -+# CONFIG_SATA_SIL24 is not set -+CONFIG_ATA_SFF=y -+ -+# -+# SFF controllers with custom DMA interface -+# -+# CONFIG_PDC_ADMA is not set -+# CONFIG_SATA_QSTOR is not set -+# CONFIG_SATA_SX4 is not set -+CONFIG_ATA_BMDMA=y -+ -+# -+# SATA SFF controllers with BMDMA -+# -+# CONFIG_ATA_PIIX is not set -+# CONFIG_SATA_MV is not set -+# CONFIG_SATA_NV is not set -+# CONFIG_SATA_PROMISE is not set -+# CONFIG_SATA_SIL is not set -+# CONFIG_SATA_SIS is not set -+# CONFIG_SATA_SVW is not set -+# CONFIG_SATA_ULI is not set -+# CONFIG_SATA_VIA is not set -+# CONFIG_SATA_VITESSE is not set -+ -+# -+# PATA SFF controllers with BMDMA -+# -+# CONFIG_PATA_ALI is not set -+# CONFIG_PATA_AMD is not set -+# CONFIG_PATA_ARTOP is not set -+# CONFIG_PATA_ATIIXP is not set -+# CONFIG_PATA_ATP867X is not set -+# CONFIG_PATA_CMD64X is not set -+# CONFIG_PATA_CYPRESS is not set -+# CONFIG_PATA_EFAR is not set -+# CONFIG_PATA_HPT366 is not set -+# CONFIG_PATA_HPT37X is not set -+# CONFIG_PATA_HPT3X2N is not set -+# CONFIG_PATA_HPT3X3 is not set -+CONFIG_PATA_IMX=y -+# CONFIG_PATA_IT8213 is not set -+# CONFIG_PATA_IT821X is not set -+# CONFIG_PATA_JMICRON is not set -+# CONFIG_PATA_MARVELL is not set -+# CONFIG_PATA_NETCELL is not set -+# CONFIG_PATA_NINJA32 is not set -+# CONFIG_PATA_NS87415 is not set -+# CONFIG_PATA_OLDPIIX is not set -+# CONFIG_PATA_OPTIDMA is not set -+# CONFIG_PATA_PDC2027X is not set -+# CONFIG_PATA_PDC_OLD is not set -+# CONFIG_PATA_RADISYS is not set -+# CONFIG_PATA_RDC is not set -+# CONFIG_PATA_SCH is not set -+# CONFIG_PATA_SERVERWORKS is not set -+# CONFIG_PATA_SIL680 is not set -+# CONFIG_PATA_SIS is not set -+# CONFIG_PATA_TOSHIBA is not set -+# CONFIG_PATA_TRIFLEX is not set -+# CONFIG_PATA_VIA is not set -+# CONFIG_PATA_WINBOND is not set -+ -+# -+# PIO-only SFF controllers -+# -+# CONFIG_PATA_CMD640_PCI is not set -+# CONFIG_PATA_MPIIX is not set -+# CONFIG_PATA_NS87410 is not set -+# CONFIG_PATA_OPTI is not set -+# CONFIG_PATA_PLATFORM is not set -+# CONFIG_PATA_RZ1000 is not set -+ -+# -+# Generic fallback / legacy drivers -+# -+# CONFIG_ATA_GENERIC is not set -+# CONFIG_PATA_LEGACY is not set -+CONFIG_MD=y -+CONFIG_BLK_DEV_MD=y -+CONFIG_MD_AUTODETECT=y -+CONFIG_MD_LINEAR=y -+CONFIG_MD_RAID0=y -+CONFIG_MD_RAID1=y -+CONFIG_MD_RAID10=y -+CONFIG_MD_RAID456=m -+CONFIG_MD_MULTIPATH=m -+CONFIG_MD_FAULTY=m -+CONFIG_BCACHE=m -+# CONFIG_BCACHE_DEBUG is not set -+# CONFIG_BCACHE_CLOSURES_DEBUG is not set -+CONFIG_BLK_DEV_DM_BUILTIN=y -+CONFIG_BLK_DEV_DM=m -+# CONFIG_DM_MQ_DEFAULT is not set -+# CONFIG_DM_DEBUG is not set -+CONFIG_DM_BUFIO=m -+CONFIG_DM_BIO_PRISON=m -+CONFIG_DM_PERSISTENT_DATA=m -+# CONFIG_DM_DEBUG_BLOCK_STACK_TRACING is not set -+CONFIG_DM_CRYPT=m -+CONFIG_DM_SNAPSHOT=m -+CONFIG_DM_THIN_PROVISIONING=m -+CONFIG_DM_CACHE=m -+CONFIG_DM_CACHE_MQ=m -+CONFIG_DM_CACHE_CLEANER=m -+# CONFIG_DM_ERA is not set -+CONFIG_DM_MIRROR=m -+CONFIG_DM_LOG_USERSPACE=m -+CONFIG_DM_RAID=m -+CONFIG_DM_ZERO=m -+CONFIG_DM_MULTIPATH=m -+CONFIG_DM_MULTIPATH_QL=m -+CONFIG_DM_MULTIPATH_ST=m -+CONFIG_DM_DELAY=m -+CONFIG_DM_UEVENT=y -+CONFIG_DM_FLAKEY=m -+CONFIG_DM_VERITY=m -+# CONFIG_DM_SWITCH is not set -+# CONFIG_DM_LOG_WRITES is not set -+# CONFIG_TARGET_CORE is not set -+# CONFIG_FUSION is not set -+ -+# -+# IEEE 1394 (FireWire) support -+# -+# CONFIG_FIREWIRE is not set -+# CONFIG_FIREWIRE_NOSY is not set -+CONFIG_NETDEVICES=y -+CONFIG_MII=y -+CONFIG_NET_CORE=y -+CONFIG_BONDING=m -+CONFIG_DUMMY=m -+# CONFIG_EQUALIZER is not set -+# CONFIG_NET_FC is not set -+# CONFIG_IFB is not set -+CONFIG_NET_TEAM=m -+CONFIG_NET_TEAM_MODE_BROADCAST=m -+CONFIG_NET_TEAM_MODE_ROUNDROBIN=m -+CONFIG_NET_TEAM_MODE_RANDOM=m -+CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m -+CONFIG_NET_TEAM_MODE_LOADBALANCE=m -+CONFIG_MACVLAN=m -+CONFIG_MACVTAP=m -+CONFIG_IPVLAN=m -+CONFIG_VXLAN=m -+CONFIG_NETCONSOLE=m -+CONFIG_NETCONSOLE_DYNAMIC=y -+CONFIG_NETPOLL=y -+CONFIG_NET_POLL_CONTROLLER=y -+CONFIG_TUN=m -+CONFIG_VETH=m -+CONFIG_NLMON=m -+# CONFIG_ARCNET is not set -+ -+# -+# CAIF transport drivers -+# -+# CONFIG_CAIF_TTY is not set -+# CONFIG_CAIF_SPI_SLAVE is not set -+# CONFIG_CAIF_HSI is not set -+# CONFIG_CAIF_VIRTIO is not set -+ -+# -+# Distributed Switch Architecture drivers -+# -+# CONFIG_NET_DSA_MV88E6XXX is not set -+# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set -+CONFIG_ETHERNET=y -+CONFIG_MDIO=y -+CONFIG_NET_VENDOR_3COM=y -+# CONFIG_VORTEX is not set -+# CONFIG_TYPHOON is not set -+CONFIG_NET_VENDOR_ADAPTEC=y -+# CONFIG_ADAPTEC_STARFIRE is not set -+CONFIG_NET_VENDOR_AGERE=y -+CONFIG_ET131X=m -+CONFIG_NET_VENDOR_ALTEON=y -+# CONFIG_ACENIC is not set -+# CONFIG_ALTERA_TSE is not set -+CONFIG_NET_VENDOR_AMD=y -+# CONFIG_AMD8111_ETH is not set -+# CONFIG_PCNET32 is not set -+CONFIG_NET_VENDOR_ARC=y -+# CONFIG_ARC_EMAC is not set -+# CONFIG_EMAC_ROCKCHIP is not set -+CONFIG_NET_VENDOR_ATHEROS=y -+CONFIG_ATL2=y -+CONFIG_ATL1=y -+CONFIG_ATL1E=y -+CONFIG_ATL1C=y -+CONFIG_ALX=y -+# CONFIG_NET_CADENCE is not set -+# CONFIG_NET_VENDOR_BROADCOM is not set -+CONFIG_NET_VENDOR_BROCADE=y -+# CONFIG_BNA is not set -+CONFIG_NET_VENDOR_CHELSIO=y -+# CONFIG_CHELSIO_T1 is not set -+# CONFIG_CHELSIO_T3 is not set -+# CONFIG_CHELSIO_T4 is not set -+# CONFIG_CHELSIO_T4VF is not set -+# CONFIG_NET_VENDOR_CIRRUS is not set -+CONFIG_NET_VENDOR_CISCO=y -+# CONFIG_ENIC is not set -+# CONFIG_DM9000 is not set -+# CONFIG_DNET is not set -+CONFIG_NET_VENDOR_DEC=y -+# CONFIG_NET_TULIP is not set -+CONFIG_NET_VENDOR_DLINK=y -+# CONFIG_DL2K is not set -+# CONFIG_SUNDANCE is not set -+CONFIG_NET_VENDOR_EMULEX=y -+# CONFIG_BE2NET is not set -+CONFIG_NET_VENDOR_EXAR=y -+# CONFIG_S2IO is not set -+# CONFIG_VXGE is not set -+# CONFIG_NET_VENDOR_FARADAY is not set -+CONFIG_NET_VENDOR_FREESCALE=y -+CONFIG_FEC=y -+# CONFIG_FSL_PQ_MDIO is not set -+# CONFIG_FSL_XGMAC_MDIO is not set -+CONFIG_NET_VENDOR_HISILICON=y -+# CONFIG_HIX5HD2_GMAC is not set -+# CONFIG_HIP04_ETH is not set -+CONFIG_NET_VENDOR_HP=y -+# CONFIG_HP100 is not set -+# CONFIG_NET_VENDOR_INTEL is not set -+# CONFIG_IP1000 is not set -+# CONFIG_JME is not set -+# CONFIG_NET_VENDOR_MARVELL is not set -+CONFIG_NET_VENDOR_MELLANOX=y -+# CONFIG_MLX4_EN is not set -+# CONFIG_MLX4_CORE is not set -+# CONFIG_MLX5_CORE is not set -+# CONFIG_NET_VENDOR_MICREL is not set -+# CONFIG_NET_VENDOR_MICROCHIP is not set -+CONFIG_NET_VENDOR_MYRI=y -+# CONFIG_MYRI10GE is not set -+# CONFIG_FEALNX is not set -+# CONFIG_NET_VENDOR_NATSEMI is not set -+CONFIG_NET_VENDOR_NVIDIA=y -+# CONFIG_FORCEDETH is not set -+CONFIG_NET_VENDOR_OKI=y -+# CONFIG_ETHOC is not set -+CONFIG_NET_PACKET_ENGINE=y -+# CONFIG_HAMACHI is not set -+# CONFIG_YELLOWFIN is not set -+CONFIG_NET_VENDOR_QLOGIC=y -+# CONFIG_QLA3XXX is not set -+# CONFIG_QLCNIC is not set -+# CONFIG_QLGE is not set -+# CONFIG_NETXEN_NIC is not set -+CONFIG_NET_VENDOR_QUALCOMM=y -+# CONFIG_QCA7000 is not set -+CONFIG_NET_VENDOR_REALTEK=y -+# CONFIG_8139CP is not set -+# CONFIG_8139TOO is not set -+# CONFIG_R8169 is not set -+CONFIG_NET_VENDOR_RDC=y -+# CONFIG_R6040 is not set -+CONFIG_NET_VENDOR_ROCKER=y -+CONFIG_NET_VENDOR_SAMSUNG=y -+# CONFIG_SXGBE_ETH is not set -+# CONFIG_NET_VENDOR_SEEQ is not set -+CONFIG_NET_VENDOR_SILAN=y -+# CONFIG_SC92031 is not set -+CONFIG_NET_VENDOR_SIS=y -+# CONFIG_SIS900 is not set -+# CONFIG_SIS190 is not set -+# CONFIG_SFC is not set -+# CONFIG_NET_VENDOR_SMSC is not set -+# CONFIG_NET_VENDOR_STMICRO is not set -+CONFIG_NET_VENDOR_SUN=y -+# CONFIG_HAPPYMEAL is not set -+# CONFIG_SUNGEM is not set -+# CONFIG_CASSINI is not set -+# CONFIG_NIU is not set -+CONFIG_NET_VENDOR_TEHUTI=y -+# CONFIG_TEHUTI is not set -+CONFIG_NET_VENDOR_TI=y -+# CONFIG_TI_CPSW_ALE is not set -+# CONFIG_TLAN is not set -+CONFIG_NET_VENDOR_VIA=y -+# CONFIG_VIA_RHINE is not set -+# CONFIG_VIA_VELOCITY is not set -+# CONFIG_NET_VENDOR_WIZNET is not set -+# CONFIG_FDDI is not set -+# CONFIG_HIPPI is not set -+CONFIG_PHYLIB=y -+ -+# -+# MII PHY device drivers -+# -+CONFIG_AT803X_PHY=y -+# CONFIG_AMD_PHY is not set -+# CONFIG_MARVELL_PHY is not set -+# CONFIG_DAVICOM_PHY is not set -+# CONFIG_QSEMI_PHY is not set -+# CONFIG_LXT_PHY is not set -+# CONFIG_CICADA_PHY is not set -+# CONFIG_VITESSE_PHY is not set -+# CONFIG_SMSC_PHY is not set -+CONFIG_BROADCOM_PHY=y -+CONFIG_BCM7XXX_PHY=m -+CONFIG_BCM87XX_PHY=y -+# CONFIG_ICPLUS_PHY is not set -+# CONFIG_REALTEK_PHY is not set -+# CONFIG_NATIONAL_PHY is not set -+# CONFIG_STE10XP is not set -+# CONFIG_LSI_ET1011C_PHY is not set -+CONFIG_MICREL_PHY=m -+CONFIG_FIXED_PHY=y -+CONFIG_MDIO_BITBANG=m -+CONFIG_MDIO_GPIO=m -+CONFIG_MDIO_BUS_MUX=m -+CONFIG_MDIO_BUS_MUX_GPIO=m -+CONFIG_MDIO_BUS_MUX_MMIOREG=m -+CONFIG_MDIO_BCM_UNIMAC=m -+# CONFIG_MICREL_KS8995MA is not set -+CONFIG_PPP=m -+CONFIG_PPP_BSDCOMP=m -+CONFIG_PPP_DEFLATE=m -+CONFIG_PPP_FILTER=y -+CONFIG_PPP_MPPE=m -+CONFIG_PPP_MULTILINK=y -+CONFIG_PPPOE=m -+CONFIG_PPPOL2TP=m -+CONFIG_PPP_ASYNC=m -+CONFIG_PPP_SYNC_TTY=m -+CONFIG_SLIP=m -+CONFIG_SLHC=m -+CONFIG_SLIP_COMPRESSED=y -+CONFIG_SLIP_SMART=y -+CONFIG_SLIP_MODE_SLIP6=y -+CONFIG_USB_NET_DRIVERS=y -+CONFIG_USB_CATC=m -+CONFIG_USB_KAWETH=m -+CONFIG_USB_PEGASUS=m -+CONFIG_USB_RTL8150=m -+CONFIG_USB_RTL8152=m -+CONFIG_USB_USBNET=m -+CONFIG_USB_NET_AX8817X=m -+CONFIG_USB_NET_AX88179_178A=m -+CONFIG_USB_NET_CDCETHER=m -+CONFIG_USB_NET_CDC_EEM=m -+CONFIG_USB_NET_CDC_NCM=m -+CONFIG_USB_NET_HUAWEI_CDC_NCM=m -+CONFIG_USB_NET_CDC_MBIM=m -+CONFIG_USB_NET_DM9601=m -+CONFIG_USB_NET_SR9700=m -+CONFIG_USB_NET_SR9800=m -+CONFIG_USB_NET_SMSC75XX=m -+CONFIG_USB_NET_SMSC95XX=m -+CONFIG_USB_NET_GL620A=m -+CONFIG_USB_NET_NET1080=m -+CONFIG_USB_NET_PLUSB=m -+CONFIG_USB_NET_MCS7830=m -+CONFIG_USB_NET_RNDIS_HOST=m -+CONFIG_USB_NET_CDC_SUBSET=m -+# CONFIG_USB_ALI_M5632 is not set -+# CONFIG_USB_AN2720 is not set -+CONFIG_USB_BELKIN=y -+CONFIG_USB_ARMLINUX=y -+# CONFIG_USB_EPSON2888 is not set -+# CONFIG_USB_KC2190 is not set -+CONFIG_USB_NET_ZAURUS=m -+CONFIG_USB_NET_CX82310_ETH=m -+CONFIG_USB_NET_KALMIA=m -+CONFIG_USB_NET_QMI_WWAN=m -+CONFIG_USB_HSO=m -+CONFIG_USB_NET_INT51X1=m -+CONFIG_USB_IPHETH=m -+CONFIG_USB_SIERRA_NET=m -+CONFIG_USB_VL600=m -+CONFIG_WLAN=y -+CONFIG_LIBERTAS_THINFIRM=m -+# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set -+CONFIG_LIBERTAS_THINFIRM_USB=m -+CONFIG_ATMEL=m -+CONFIG_PCI_ATMEL=m -+CONFIG_AT76C50X_USB=m -+CONFIG_PRISM54=m -+CONFIG_USB_ZD1201=m -+CONFIG_USB_NET_RNDIS_WLAN=m -+CONFIG_RTL8180=m -+CONFIG_RTL8187=m -+CONFIG_RTL8187_LEDS=y -+CONFIG_ADM8211=m -+# CONFIG_MAC80211_HWSIM is not set -+CONFIG_MWL8K=m -+CONFIG_ATH_COMMON=m -+CONFIG_ATH_CARDS=m -+# CONFIG_ATH_DEBUG is not set -+CONFIG_ATH5K=m -+# CONFIG_ATH5K_DEBUG is not set -+CONFIG_ATH5K_PCI=y -+CONFIG_ATH9K_HW=m -+CONFIG_ATH9K_COMMON=m -+CONFIG_ATH9K_BTCOEX_SUPPORT=y -+CONFIG_ATH9K=m -+CONFIG_ATH9K_PCI=y -+CONFIG_ATH9K_AHB=y -+# CONFIG_ATH9K_DEBUGFS is not set -+# CONFIG_ATH9K_DYNACK is not set -+CONFIG_ATH9K_WOW=y -+CONFIG_ATH9K_RFKILL=y -+CONFIG_ATH9K_CHANNEL_CONTEXT=y -+CONFIG_ATH9K_PCOEM=y -+CONFIG_ATH9K_HTC=m -+# CONFIG_ATH9K_HTC_DEBUGFS is not set -+CONFIG_CARL9170=m -+CONFIG_CARL9170_LEDS=y -+CONFIG_CARL9170_WPC=y -+CONFIG_CARL9170_HWRNG=y -+CONFIG_ATH6KL=m -+CONFIG_ATH6KL_SDIO=m -+CONFIG_ATH6KL_USB=m -+# CONFIG_ATH6KL_DEBUG is not set -+CONFIG_AR5523=m -+CONFIG_WIL6210=m -+CONFIG_WIL6210_ISR_COR=y -+CONFIG_ATH10K=m -+CONFIG_ATH10K_PCI=m -+# CONFIG_ATH10K_DEBUG is not set -+# CONFIG_ATH10K_DEBUGFS is not set -+CONFIG_WCN36XX=m -+# CONFIG_WCN36XX_DEBUGFS is not set -+CONFIG_B43=m -+CONFIG_B43_BCMA=y -+CONFIG_B43_SSB=y -+CONFIG_B43_BUSES_BCMA_AND_SSB=y -+# CONFIG_B43_BUSES_BCMA is not set -+# CONFIG_B43_BUSES_SSB is not set -+CONFIG_B43_PCI_AUTOSELECT=y -+CONFIG_B43_PCICORE_AUTOSELECT=y -+CONFIG_B43_SDIO=y -+CONFIG_B43_BCMA_PIO=y -+CONFIG_B43_PIO=y -+CONFIG_B43_PHY_G=y -+CONFIG_B43_PHY_N=y -+CONFIG_B43_PHY_LP=y -+CONFIG_B43_PHY_HT=y -+CONFIG_B43_LEDS=y -+CONFIG_B43_HWRNG=y -+# CONFIG_B43_DEBUG is not set -+CONFIG_B43LEGACY=m -+CONFIG_B43LEGACY_PCI_AUTOSELECT=y -+CONFIG_B43LEGACY_PCICORE_AUTOSELECT=y -+CONFIG_B43LEGACY_LEDS=y -+CONFIG_B43LEGACY_HWRNG=y -+# CONFIG_B43LEGACY_DEBUG is not set -+CONFIG_B43LEGACY_DMA=y -+CONFIG_B43LEGACY_PIO=y -+CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y -+# CONFIG_B43LEGACY_DMA_MODE is not set -+# CONFIG_B43LEGACY_PIO_MODE is not set -+CONFIG_BRCMUTIL=m -+CONFIG_BRCMSMAC=m -+CONFIG_BRCMFMAC=m -+CONFIG_BRCMFMAC_PROTO_BCDC=y -+CONFIG_BRCMFMAC_PROTO_MSGBUF=y -+CONFIG_BRCMFMAC_SDIO=y -+# CONFIG_BRCMFMAC_USB is not set -+CONFIG_BRCMFMAC_PCIE=y -+# CONFIG_BRCM_TRACING is not set -+# CONFIG_BRCMDBG is not set -+CONFIG_HOSTAP=m -+CONFIG_HOSTAP_FIRMWARE=y -+CONFIG_HOSTAP_FIRMWARE_NVRAM=y -+CONFIG_HOSTAP_PLX=m -+CONFIG_HOSTAP_PCI=m -+CONFIG_IPW2100=m -+CONFIG_IPW2100_MONITOR=y -+# CONFIG_IPW2100_DEBUG is not set -+CONFIG_IPW2200=m -+CONFIG_IPW2200_MONITOR=y -+CONFIG_IPW2200_RADIOTAP=y -+CONFIG_IPW2200_PROMISCUOUS=y -+CONFIG_IPW2200_QOS=y -+CONFIG_IPW2200_DEBUG=y -+CONFIG_LIBIPW=m -+# CONFIG_LIBIPW_DEBUG is not set -+CONFIG_IWLWIFI=m -+CONFIG_IWLWIFI_LEDS=y -+CONFIG_IWLDVM=m -+CONFIG_IWLMVM=m -+CONFIG_IWLWIFI_OPMODE_MODULAR=y -+CONFIG_IWLWIFI_BCAST_FILTERING=y -+CONFIG_IWLWIFI_UAPSD=y -+ -+# -+# Debugging Options -+# -+# CONFIG_IWLWIFI_DEBUG is not set -+CONFIG_IWLEGACY=m -+CONFIG_IWL4965=m -+CONFIG_IWL3945=m -+ -+# -+# iwl3945 / iwl4965 Debugging Options -+# -+# CONFIG_IWLEGACY_DEBUG is not set -+CONFIG_LIBERTAS=m -+CONFIG_LIBERTAS_USB=m -+CONFIG_LIBERTAS_SDIO=m -+CONFIG_LIBERTAS_SPI=m -+# CONFIG_LIBERTAS_DEBUG is not set -+CONFIG_LIBERTAS_MESH=y -+CONFIG_HERMES=m -+CONFIG_HERMES_PRISM=y -+CONFIG_HERMES_CACHE_FW_ON_INIT=y -+CONFIG_PLX_HERMES=m -+CONFIG_TMD_HERMES=m -+CONFIG_NORTEL_HERMES=m -+CONFIG_PCI_HERMES=m -+CONFIG_ORINOCO_USB=m -+CONFIG_P54_COMMON=m -+CONFIG_P54_USB=m -+CONFIG_P54_PCI=m -+CONFIG_P54_SPI=m -+CONFIG_P54_SPI_DEFAULT_EEPROM=y -+CONFIG_P54_LEDS=y -+CONFIG_RT2X00=m -+CONFIG_RT2400PCI=m -+CONFIG_RT2500PCI=m -+CONFIG_RT61PCI=m -+CONFIG_RT2800PCI=m -+CONFIG_RT2800PCI_RT33XX=y -+CONFIG_RT2800PCI_RT35XX=y -+CONFIG_RT2800PCI_RT53XX=y -+CONFIG_RT2800PCI_RT3290=y -+CONFIG_RT2500USB=m -+CONFIG_RT73USB=m -+CONFIG_RT2800USB=m -+CONFIG_RT2800USB_RT33XX=y -+CONFIG_RT2800USB_RT35XX=y -+CONFIG_RT2800USB_RT3573=y -+CONFIG_RT2800USB_RT53XX=y -+CONFIG_RT2800USB_RT55XX=y -+CONFIG_RT2800USB_UNKNOWN=y -+CONFIG_RT2800_LIB=m -+CONFIG_RT2800_LIB_MMIO=m -+CONFIG_RT2X00_LIB_MMIO=m -+CONFIG_RT2X00_LIB_PCI=m -+CONFIG_RT2X00_LIB_USB=m -+CONFIG_RT2X00_LIB=m -+CONFIG_RT2X00_LIB_FIRMWARE=y -+CONFIG_RT2X00_LIB_CRYPTO=y -+CONFIG_RT2X00_LIB_LEDS=y -+# CONFIG_RT2X00_DEBUG is not set -+CONFIG_RTL_CARDS=m -+CONFIG_RTL8192CE=m -+CONFIG_RTL8192SE=m -+CONFIG_RTL8192DE=m -+CONFIG_RTL8723AE=m -+CONFIG_RTL8723BE=m -+CONFIG_RTL8188EE=m -+CONFIG_RTL8192EE=m -+CONFIG_RTL8821AE=m -+CONFIG_RTL8192CU=m -+CONFIG_RTLWIFI=m -+CONFIG_RTLWIFI_PCI=m -+CONFIG_RTLWIFI_USB=m -+CONFIG_RTLWIFI_DEBUG=y -+CONFIG_RTL8192C_COMMON=m -+CONFIG_RTL8723_COMMON=m -+CONFIG_RTLBTCOEXIST=m -+CONFIG_WL_TI=y -+CONFIG_WL1251=m -+CONFIG_WL1251_SPI=m -+CONFIG_WL1251_SDIO=m -+CONFIG_WL12XX=m -+CONFIG_WL18XX=m -+CONFIG_WLCORE=m -+CONFIG_WLCORE_SPI=m -+CONFIG_WLCORE_SDIO=m -+CONFIG_WILINK_PLATFORM_DATA=y -+CONFIG_ZD1211RW=m -+# CONFIG_ZD1211RW_DEBUG is not set -+CONFIG_MWIFIEX=m -+CONFIG_MWIFIEX_SDIO=m -+CONFIG_MWIFIEX_PCIE=m -+CONFIG_MWIFIEX_USB=m -+CONFIG_CW1200=m -+CONFIG_CW1200_WLAN_SDIO=m -+CONFIG_CW1200_WLAN_SPI=m -+CONFIG_RSI_91X=m -+CONFIG_RSI_DEBUGFS=y -+CONFIG_RSI_SDIO=m -+CONFIG_RSI_USB=m -+ -+# -+# Enable WiMAX (Networking options) to see the WiMAX drivers -+# -+CONFIG_WAN=y -+CONFIG_HDLC=m -+CONFIG_HDLC_RAW=m -+CONFIG_HDLC_RAW_ETH=m -+CONFIG_HDLC_CISCO=m -+CONFIG_HDLC_FR=m -+CONFIG_HDLC_PPP=m -+ -+# -+# X.25/LAPB support is disabled -+# -+# CONFIG_PCI200SYN is not set -+CONFIG_WANXL=m -+# CONFIG_WANXL_BUILD_FIRMWARE is not set -+CONFIG_PC300TOO=m -+CONFIG_FARSYNC=m -+CONFIG_DSCC4=m -+# CONFIG_DSCC4_PCISYNC is not set -+# CONFIG_DSCC4_PCI_RST is not set -+# CONFIG_DLCI is not set -+# CONFIG_VMXNET3 is not set -+CONFIG_ISDN=y -+CONFIG_ISDN_I4L=m -+# CONFIG_ISDN_PPP is not set -+# CONFIG_ISDN_AUDIO is not set -+ -+# -+# ISDN feature submodules -+# -+# CONFIG_ISDN_DIVERSION is not set -+ -+# -+# ISDN4Linux hardware drivers -+# -+ -+# -+# Passive cards -+# -+# CONFIG_ISDN_DRV_HISAX is not set -+ -+# -+# Active cards -+# -+CONFIG_ISDN_CAPI=m -+CONFIG_CAPI_TRACE=y -+# CONFIG_ISDN_CAPI_CAPI20 is not set -+# CONFIG_ISDN_CAPI_CAPIDRV is not set -+ -+# -+# CAPI hardware drivers -+# -+# CONFIG_CAPI_AVM is not set -+# CONFIG_CAPI_EICON is not set -+CONFIG_ISDN_DRV_GIGASET=m -+CONFIG_GIGASET_CAPI=y -+# CONFIG_GIGASET_I4L is not set -+# CONFIG_GIGASET_DUMMYLL is not set -+# CONFIG_GIGASET_BASE is not set -+# CONFIG_GIGASET_M105 is not set -+# CONFIG_GIGASET_M101 is not set -+# CONFIG_GIGASET_DEBUG is not set -+CONFIG_HYSDN=m -+CONFIG_HYSDN_CAPI=y -+CONFIG_MISDN=m -+CONFIG_MISDN_DSP=m -+CONFIG_MISDN_L1OIP=m -+ -+# -+# mISDN hardware drivers -+# -+CONFIG_MISDN_HFCPCI=m -+CONFIG_MISDN_HFCMULTI=m -+CONFIG_MISDN_HFCUSB=m -+CONFIG_MISDN_AVMFRITZ=m -+CONFIG_MISDN_SPEEDFAX=m -+CONFIG_MISDN_INFINEON=m -+CONFIG_MISDN_W6692=m -+CONFIG_MISDN_NETJET=m -+CONFIG_MISDN_IPAC=m -+CONFIG_MISDN_ISAR=m -+CONFIG_ISDN_HDLC=m -+ -+# -+# Input device support -+# -+CONFIG_INPUT=y -+CONFIG_INPUT_FF_MEMLESS=y -+CONFIG_INPUT_POLLDEV=y -+CONFIG_INPUT_SPARSEKMAP=y -+CONFIG_INPUT_MATRIXKMAP=y -+ -+# -+# Userland interfaces -+# -+CONFIG_INPUT_MOUSEDEV=y -+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -+CONFIG_INPUT_JOYDEV=m -+CONFIG_INPUT_EVDEV=y -+CONFIG_INPUT_EVBUG=m -+ -+# -+# Input Device Drivers -+# -+CONFIG_INPUT_KEYBOARD=y -+# CONFIG_KEYBOARD_ADP5588 is not set -+# CONFIG_KEYBOARD_ADP5589 is not set -+CONFIG_KEYBOARD_ATKBD=y -+# CONFIG_KEYBOARD_QT1070 is not set -+# CONFIG_KEYBOARD_QT2160 is not set -+# CONFIG_KEYBOARD_LKKBD is not set -+CONFIG_KEYBOARD_GPIO=y -+CONFIG_KEYBOARD_GPIO_POLLED=y -+CONFIG_KEYBOARD_TCA6416=m -+CONFIG_KEYBOARD_TCA8418=m -+CONFIG_KEYBOARD_MATRIX=m -+# CONFIG_KEYBOARD_LM8323 is not set -+# CONFIG_KEYBOARD_LM8333 is not set -+# CONFIG_KEYBOARD_MAX7359 is not set -+# CONFIG_KEYBOARD_MCS is not set -+# CONFIG_KEYBOARD_MPR121 is not set -+CONFIG_KEYBOARD_IMX=y -+# CONFIG_KEYBOARD_NEWTON is not set -+# CONFIG_KEYBOARD_OPENCORES is not set -+# CONFIG_KEYBOARD_SAMSUNG is not set -+# CONFIG_KEYBOARD_STOWAWAY is not set -+# CONFIG_KEYBOARD_SUNKBD is not set -+# CONFIG_KEYBOARD_OMAP4 is not set -+CONFIG_KEYBOARD_XTKBD=m -+# CONFIG_KEYBOARD_CAP11XX is not set -+# CONFIG_KEYBOARD_BCM is not set -+CONFIG_INPUT_MOUSE=y -+CONFIG_MOUSE_PS2=m -+CONFIG_MOUSE_PS2_ALPS=y -+CONFIG_MOUSE_PS2_LOGIPS2PP=y -+CONFIG_MOUSE_PS2_SYNAPTICS=y -+CONFIG_MOUSE_PS2_CYPRESS=y -+CONFIG_MOUSE_PS2_TRACKPOINT=y -+CONFIG_MOUSE_PS2_ELANTECH=y -+# CONFIG_MOUSE_PS2_SENTELIC is not set -+# CONFIG_MOUSE_PS2_TOUCHKIT is not set -+CONFIG_MOUSE_PS2_FOCALTECH=y -+CONFIG_MOUSE_SERIAL=m -+CONFIG_MOUSE_APPLETOUCH=m -+CONFIG_MOUSE_BCM5974=m -+CONFIG_MOUSE_CYAPA=m -+CONFIG_MOUSE_ELAN_I2C=m -+CONFIG_MOUSE_ELAN_I2C_I2C=y -+# CONFIG_MOUSE_ELAN_I2C_SMBUS is not set -+CONFIG_MOUSE_VSXXXAA=m -+CONFIG_MOUSE_GPIO=m -+CONFIG_MOUSE_SYNAPTICS_I2C=m -+CONFIG_MOUSE_SYNAPTICS_USB=m -+CONFIG_INPUT_JOYSTICK=y -+CONFIG_JOYSTICK_ANALOG=m -+CONFIG_JOYSTICK_A3D=m -+CONFIG_JOYSTICK_ADI=m -+CONFIG_JOYSTICK_COBRA=m -+CONFIG_JOYSTICK_GF2K=m -+CONFIG_JOYSTICK_GRIP=m -+CONFIG_JOYSTICK_GRIP_MP=m -+CONFIG_JOYSTICK_GUILLEMOT=m -+CONFIG_JOYSTICK_INTERACT=m -+CONFIG_JOYSTICK_SIDEWINDER=m -+CONFIG_JOYSTICK_TMDC=m -+CONFIG_JOYSTICK_IFORCE=m -+CONFIG_JOYSTICK_IFORCE_USB=y -+CONFIG_JOYSTICK_IFORCE_232=y -+CONFIG_JOYSTICK_WARRIOR=m -+CONFIG_JOYSTICK_MAGELLAN=m -+CONFIG_JOYSTICK_SPACEORB=m -+CONFIG_JOYSTICK_SPACEBALL=m -+CONFIG_JOYSTICK_STINGER=m -+CONFIG_JOYSTICK_TWIDJOY=m -+CONFIG_JOYSTICK_ZHENHUA=m -+CONFIG_JOYSTICK_AS5011=m -+CONFIG_JOYSTICK_JOYDUMP=m -+CONFIG_JOYSTICK_XPAD=m -+CONFIG_JOYSTICK_XPAD_FF=y -+CONFIG_JOYSTICK_XPAD_LEDS=y -+# CONFIG_INPUT_TABLET is not set -+CONFIG_INPUT_TOUCHSCREEN=y -+CONFIG_OF_TOUCHSCREEN=y -+# CONFIG_TOUCHSCREEN_ADS7846 is not set -+# CONFIG_TOUCHSCREEN_AD7877 is not set -+# CONFIG_TOUCHSCREEN_AD7879 is not set -+# CONFIG_TOUCHSCREEN_AR1021_I2C is not set -+# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set -+# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set -+# CONFIG_TOUCHSCREEN_BU21013 is not set -+# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set -+# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set -+# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set -+# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set -+# CONFIG_TOUCHSCREEN_DA9052 is not set -+# CONFIG_TOUCHSCREEN_DYNAPRO is not set -+# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set -+CONFIG_TOUCHSCREEN_EETI=m -+CONFIG_TOUCHSCREEN_EGALAX=m -+CONFIG_TOUCHSCREEN_FUJITSU=m -+# CONFIG_TOUCHSCREEN_GOODIX is not set -+CONFIG_TOUCHSCREEN_ILI210X=m -+CONFIG_TOUCHSCREEN_GUNZE=m -+CONFIG_TOUCHSCREEN_ELAN=m -+CONFIG_TOUCHSCREEN_ELO=m -+CONFIG_TOUCHSCREEN_WACOM_W8001=m -+CONFIG_TOUCHSCREEN_WACOM_I2C=m -+CONFIG_TOUCHSCREEN_MAX11801=m -+CONFIG_TOUCHSCREEN_MCS5000=m -+CONFIG_TOUCHSCREEN_MMS114=m -+CONFIG_TOUCHSCREEN_MTOUCH=m -+CONFIG_TOUCHSCREEN_INEXIO=m -+CONFIG_TOUCHSCREEN_MK712=m -+CONFIG_TOUCHSCREEN_PENMOUNT=m -+CONFIG_TOUCHSCREEN_EDT_FT5X06=m -+CONFIG_TOUCHSCREEN_TOUCHRIGHT=m -+CONFIG_TOUCHSCREEN_TOUCHWIN=m -+CONFIG_TOUCHSCREEN_PIXCIR=m -+CONFIG_TOUCHSCREEN_WM97XX=m -+CONFIG_TOUCHSCREEN_WM9705=y -+CONFIG_TOUCHSCREEN_WM9712=y -+CONFIG_TOUCHSCREEN_WM9713=y -+CONFIG_TOUCHSCREEN_USB_COMPOSITE=m -+CONFIG_TOUCHSCREEN_MC13783=m -+CONFIG_TOUCHSCREEN_USB_EGALAX=y -+CONFIG_TOUCHSCREEN_USB_PANJIT=y -+CONFIG_TOUCHSCREEN_USB_3M=y -+CONFIG_TOUCHSCREEN_USB_ITM=y -+CONFIG_TOUCHSCREEN_USB_ETURBO=y -+CONFIG_TOUCHSCREEN_USB_GUNZE=y -+CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y -+CONFIG_TOUCHSCREEN_USB_IRTOUCH=y -+CONFIG_TOUCHSCREEN_USB_IDEALTEK=y -+CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y -+CONFIG_TOUCHSCREEN_USB_GOTOP=y -+CONFIG_TOUCHSCREEN_USB_JASTEC=y -+CONFIG_TOUCHSCREEN_USB_ELO=y -+CONFIG_TOUCHSCREEN_USB_E2I=y -+CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y -+CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y -+CONFIG_TOUCHSCREEN_USB_NEXIO=y -+CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y -+CONFIG_TOUCHSCREEN_TOUCHIT213=m -+CONFIG_TOUCHSCREEN_TSC_SERIO=m -+CONFIG_TOUCHSCREEN_TSC2005=m -+CONFIG_TOUCHSCREEN_TSC2007=m -+CONFIG_TOUCHSCREEN_ST1232=m -+CONFIG_TOUCHSCREEN_SUR40=m -+# CONFIG_TOUCHSCREEN_SX8654 is not set -+CONFIG_TOUCHSCREEN_TPS6507X=m -+CONFIG_TOUCHSCREEN_ZFORCE=m -+CONFIG_INPUT_MISC=y -+CONFIG_INPUT_AD714X=m -+CONFIG_INPUT_AD714X_I2C=m -+CONFIG_INPUT_AD714X_SPI=m -+CONFIG_INPUT_BMA150=m -+# CONFIG_INPUT_E3X0_BUTTON is not set -+CONFIG_INPUT_MC13783_PWRBUTTON=m -+CONFIG_INPUT_MMA8450=y -+CONFIG_INPUT_MPU3050=m -+CONFIG_INPUT_GP2A=m -+CONFIG_INPUT_GPIO_BEEPER=m -+CONFIG_INPUT_GPIO_TILT_POLLED=m -+CONFIG_INPUT_ATI_REMOTE2=m -+CONFIG_INPUT_KEYSPAN_REMOTE=m -+CONFIG_INPUT_KXTJ9=m -+CONFIG_INPUT_KXTJ9_POLLED_MODE=y -+CONFIG_INPUT_POWERMATE=m -+CONFIG_INPUT_YEALINK=m -+CONFIG_INPUT_CM109=m -+# CONFIG_INPUT_REGULATOR_HAPTIC is not set -+CONFIG_INPUT_UINPUT=m -+CONFIG_INPUT_PCF8574=m -+CONFIG_INPUT_PWM_BEEPER=m -+CONFIG_INPUT_GPIO_ROTARY_ENCODER=m -+CONFIG_INPUT_DA9052_ONKEY=m -+CONFIG_INPUT_ADXL34X=m -+CONFIG_INPUT_ADXL34X_I2C=m -+CONFIG_INPUT_ADXL34X_SPI=m -+CONFIG_INPUT_IMS_PCU=m -+CONFIG_INPUT_CMA3000=m -+CONFIG_INPUT_CMA3000_I2C=m -+CONFIG_INPUT_SOC_BUTTON_ARRAY=m -+CONFIG_INPUT_DRV260X_HAPTICS=m -+CONFIG_INPUT_DRV2667_HAPTICS=m -+ -+# -+# Hardware I/O ports -+# -+CONFIG_SERIO=y -+CONFIG_SERIO_SERPORT=m -+# CONFIG_SERIO_PCIPS2 is not set -+CONFIG_SERIO_LIBPS2=y -+CONFIG_SERIO_RAW=m -+# CONFIG_SERIO_ALTERA_PS2 is not set -+# CONFIG_SERIO_PS2MULT is not set -+# CONFIG_SERIO_ARC_PS2 is not set -+# CONFIG_SERIO_APBPS2 is not set -+CONFIG_GAMEPORT=m -+# CONFIG_GAMEPORT_NS558 is not set -+# CONFIG_GAMEPORT_L4 is not set -+# CONFIG_GAMEPORT_EMU10K1 is not set -+# CONFIG_GAMEPORT_FM801 is not set -+ -+# -+# Character devices -+# -+CONFIG_TTY=y -+CONFIG_VT=y -+CONFIG_CONSOLE_TRANSLATIONS=y -+CONFIG_VT_CONSOLE=y -+CONFIG_VT_CONSOLE_SLEEP=y -+CONFIG_HW_CONSOLE=y -+CONFIG_VT_HW_CONSOLE_BINDING=y -+CONFIG_UNIX98_PTYS=y -+CONFIG_DEVPTS_MULTIPLE_INSTANCES=y -+CONFIG_LEGACY_PTYS=y -+CONFIG_LEGACY_PTY_COUNT=256 -+# CONFIG_SERIAL_NONSTANDARD is not set -+# CONFIG_NOZOMI is not set -+# CONFIG_N_GSM is not set -+# CONFIG_TRACE_SINK is not set -+CONFIG_DEVMEM=y -+# CONFIG_DEVKMEM is not set -+ -+# -+# Serial drivers -+# -+CONFIG_SERIAL_EARLYCON=y -+CONFIG_SERIAL_8250=m -+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y -+CONFIG_SERIAL_8250_DMA=y -+CONFIG_SERIAL_8250_PCI=m -+CONFIG_SERIAL_8250_NR_UARTS=4 -+CONFIG_SERIAL_8250_RUNTIME_UARTS=4 -+# CONFIG_SERIAL_8250_EXTENDED is not set -+# CONFIG_SERIAL_8250_DW is not set -+# CONFIG_SERIAL_8250_EM is not set -+ -+# -+# Non-8250 serial port support -+# -+CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST=y -+# CONFIG_SERIAL_MAX3100 is not set -+# CONFIG_SERIAL_MAX310X is not set -+CONFIG_SERIAL_IMX=y -+CONFIG_SERIAL_IMX_CONSOLE=y -+CONFIG_SERIAL_CORE=y -+CONFIG_SERIAL_CORE_CONSOLE=y -+# CONFIG_SERIAL_JSM is not set -+# CONFIG_SERIAL_OF_PLATFORM is not set -+# CONFIG_SERIAL_SCCNXP is not set -+# CONFIG_SERIAL_SC16IS7XX is not set -+# CONFIG_SERIAL_BCM63XX is not set -+# CONFIG_SERIAL_ALTERA_JTAGUART is not set -+# CONFIG_SERIAL_ALTERA_UART is not set -+# CONFIG_SERIAL_IFX6X60 is not set -+# CONFIG_SERIAL_XILINX_PS_UART is not set -+# CONFIG_SERIAL_ARC is not set -+# CONFIG_SERIAL_RP2 is not set -+CONFIG_SERIAL_FSL_LPUART=m -+# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set -+# CONFIG_SERIAL_ST_ASC is not set -+CONFIG_TTY_PRINTK=m -+# CONFIG_HVC_DCC is not set -+# CONFIG_IPMI_HANDLER is not set -+CONFIG_HW_RANDOM=y -+CONFIG_HW_RANDOM_TIMERIOMEM=m -+# CONFIG_R3964 is not set -+# CONFIG_APPLICOM is not set -+CONFIG_RAW_DRIVER=m -+CONFIG_MAX_RAW_DEVS=256 -+# CONFIG_TCG_TPM is not set -+CONFIG_DEVPORT=y -+# CONFIG_XILLYBUS is not set -+ -+# -+# I2C support -+# -+CONFIG_I2C=y -+CONFIG_I2C_BOARDINFO=y -+CONFIG_I2C_COMPAT=y -+CONFIG_I2C_CHARDEV=y -+CONFIG_I2C_MUX=y -+ -+# -+# Multiplexer I2C Chip support -+# -+CONFIG_I2C_ARB_GPIO_CHALLENGE=y -+CONFIG_I2C_MUX_GPIO=y -+CONFIG_I2C_MUX_PCA9541=y -+CONFIG_I2C_MUX_PCA954x=y -+CONFIG_I2C_MUX_PINCTRL=y -+CONFIG_I2C_HELPER_AUTO=y -+CONFIG_I2C_ALGOBIT=y -+ -+# -+# I2C Hardware Bus support -+# -+ -+# -+# PC SMBus host controller drivers -+# -+# CONFIG_I2C_ALI1535 is not set -+# CONFIG_I2C_ALI1563 is not set -+# CONFIG_I2C_ALI15X3 is not set -+# CONFIG_I2C_AMD756 is not set -+# CONFIG_I2C_AMD8111 is not set -+# CONFIG_I2C_I801 is not set -+# CONFIG_I2C_ISCH is not set -+# CONFIG_I2C_PIIX4 is not set -+# CONFIG_I2C_NFORCE2 is not set -+# CONFIG_I2C_SIS5595 is not set -+# CONFIG_I2C_SIS630 is not set -+# CONFIG_I2C_SIS96X is not set -+# CONFIG_I2C_VIA is not set -+# CONFIG_I2C_VIAPRO is not set -+ -+# -+# I2C system bus drivers (mostly embedded / system-on-chip) -+# -+# CONFIG_I2C_CBUS_GPIO is not set -+CONFIG_I2C_DESIGNWARE_CORE=m -+CONFIG_I2C_DESIGNWARE_PLATFORM=m -+# CONFIG_I2C_DESIGNWARE_PCI is not set -+CONFIG_I2C_GPIO=y -+CONFIG_I2C_IMX=y -+CONFIG_I2C_OCORES=y -+# CONFIG_I2C_PCA_PLATFORM is not set -+# CONFIG_I2C_PXA_PCI is not set -+# CONFIG_I2C_RK3X is not set -+# CONFIG_I2C_SIMTEC is not set -+# CONFIG_I2C_XILINX is not set -+ -+# -+# External I2C/SMBus adapter drivers -+# -+# CONFIG_I2C_DIOLAN_U2C is not set -+# CONFIG_I2C_PARPORT_LIGHT is not set -+# CONFIG_I2C_ROBOTFUZZ_OSIF is not set -+# CONFIG_I2C_TAOS_EVM is not set -+# CONFIG_I2C_TINY_USB is not set -+ -+# -+# Other I2C/SMBus bus drivers -+# -+# CONFIG_I2C_STUB is not set -+CONFIG_I2C_SLAVE=y -+CONFIG_I2C_SLAVE_EEPROM=m -+# CONFIG_I2C_DEBUG_CORE is not set -+# CONFIG_I2C_DEBUG_ALGO is not set -+# CONFIG_I2C_DEBUG_BUS is not set -+CONFIG_SPI=y -+# CONFIG_SPI_DEBUG is not set -+CONFIG_SPI_MASTER=y -+ -+# -+# SPI Master Controller Drivers -+# -+# CONFIG_SPI_ALTERA is not set -+CONFIG_SPI_BITBANG=m -+# CONFIG_SPI_CADENCE is not set -+CONFIG_SPI_GPIO=m -+CONFIG_SPI_IMX=m -+# CONFIG_SPI_FSL_SPI is not set -+# CONFIG_SPI_OC_TINY is not set -+# CONFIG_SPI_PXA2XX is not set -+# CONFIG_SPI_PXA2XX_PCI is not set -+# CONFIG_SPI_ROCKCHIP is not set -+# CONFIG_SPI_SC18IS602 is not set -+# CONFIG_SPI_XCOMM is not set -+# CONFIG_SPI_XILINX is not set -+# CONFIG_SPI_DESIGNWARE is not set -+ -+# -+# SPI Protocol Masters -+# -+CONFIG_SPI_SPIDEV=y -+# CONFIG_SPI_TLE62X0 is not set -+# CONFIG_SPMI is not set -+# CONFIG_HSI is not set -+ -+# -+# PPS support -+# -+CONFIG_PPS=y -+# CONFIG_PPS_DEBUG is not set -+# CONFIG_NTP_PPS is not set -+ -+# -+# PPS clients support -+# -+# CONFIG_PPS_CLIENT_KTIMER is not set -+CONFIG_PPS_CLIENT_LDISC=y -+CONFIG_PPS_CLIENT_GPIO=y -+ -+# -+# PPS generators support -+# -+ -+# -+# PTP clock support -+# -+CONFIG_PTP_1588_CLOCK=y -+ -+# -+# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. -+# -+CONFIG_PINCTRL=y -+ -+# -+# Pin controllers -+# -+CONFIG_PINMUX=y -+CONFIG_PINCONF=y -+CONFIG_GENERIC_PINCONF=y -+# CONFIG_DEBUG_PINCTRL is not set -+# CONFIG_PINCTRL_AMD is not set -+CONFIG_PINCTRL_SINGLE=y -+CONFIG_PINCTRL_IMX=y -+CONFIG_PINCTRL_IMX6Q=y -+CONFIG_PINCTRL_IMX6SL=y -+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y -+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y -+CONFIG_ARCH_REQUIRE_GPIOLIB=y -+CONFIG_GPIOLIB=y -+CONFIG_GPIO_DEVRES=y -+CONFIG_OF_GPIO=y -+CONFIG_GPIOLIB_IRQCHIP=y -+# CONFIG_DEBUG_GPIO is not set -+CONFIG_GPIO_SYSFS=y -+CONFIG_GPIO_GENERIC=y -+ -+# -+# Memory mapped GPIO drivers -+# -+CONFIG_GPIO_74XX_MMIO=y -+# CONFIG_GPIO_ALTERA is not set -+# CONFIG_GPIO_DWAPB is not set -+# CONFIG_GPIO_EM is not set -+CONFIG_GPIO_GENERIC_PLATFORM=y -+# CONFIG_GPIO_GRGPIO is not set -+CONFIG_GPIO_MXC=y -+# CONFIG_GPIO_SCH311X is not set -+CONFIG_GPIO_SYSCON=y -+# CONFIG_GPIO_VX855 is not set -+# CONFIG_GPIO_ZEVIO is not set -+ -+# -+# I2C GPIO expanders -+# -+CONFIG_GPIO_ADP5588=m -+CONFIG_GPIO_ADNP=m -+# CONFIG_GPIO_MAX7300 is not set -+# CONFIG_GPIO_MAX732X is not set -+CONFIG_GPIO_PCA953X=y -+CONFIG_GPIO_PCA953X_IRQ=y -+CONFIG_GPIO_PCF857X=m -+CONFIG_GPIO_SX150X=y -+ -+# -+# MFD GPIO expanders -+# -+# CONFIG_GPIO_DA9052 is not set -+ -+# -+# PCI GPIO expanders -+# -+# CONFIG_GPIO_AMD8111 is not set -+# CONFIG_GPIO_BT8XX is not set -+# CONFIG_GPIO_ML_IOH is not set -+# CONFIG_GPIO_RDC321X is not set -+ -+# -+# SPI GPIO expanders -+# -+CONFIG_GPIO_74X164=y -+# CONFIG_GPIO_MAX7301 is not set -+CONFIG_GPIO_MCP23S08=y -+CONFIG_GPIO_MC33880=y -+ -+# -+# USB GPIO expanders -+# -+CONFIG_W1=y -+CONFIG_W1_CON=y -+ -+# -+# 1-wire Bus Masters -+# -+CONFIG_W1_MASTER_MATROX=m -+CONFIG_W1_MASTER_DS2490=m -+CONFIG_W1_MASTER_DS2482=m -+CONFIG_W1_MASTER_MXC=m -+CONFIG_W1_MASTER_DS1WM=m -+CONFIG_W1_MASTER_GPIO=m -+ -+# -+# 1-wire Slaves -+# -+CONFIG_W1_SLAVE_THERM=m -+CONFIG_W1_SLAVE_SMEM=m -+CONFIG_W1_SLAVE_DS2408=m -+CONFIG_W1_SLAVE_DS2408_READBACK=y -+CONFIG_W1_SLAVE_DS2413=m -+CONFIG_W1_SLAVE_DS2406=m -+CONFIG_W1_SLAVE_DS2423=m -+CONFIG_W1_SLAVE_DS2431=m -+CONFIG_W1_SLAVE_DS2433=m -+CONFIG_W1_SLAVE_DS2433_CRC=y -+CONFIG_W1_SLAVE_DS2760=m -+CONFIG_W1_SLAVE_DS2780=m -+CONFIG_W1_SLAVE_DS2781=m -+CONFIG_W1_SLAVE_DS28E04=m -+CONFIG_W1_SLAVE_BQ27000=m -+CONFIG_POWER_SUPPLY=y -+# CONFIG_POWER_SUPPLY_DEBUG is not set -+# CONFIG_PDA_POWER is not set -+# CONFIG_GENERIC_ADC_BATTERY is not set -+CONFIG_TEST_POWER=m -+# CONFIG_BATTERY_DS2760 is not set -+# CONFIG_BATTERY_DS2780 is not set -+# CONFIG_BATTERY_DS2781 is not set -+# CONFIG_BATTERY_DS2782 is not set -+# CONFIG_BATTERY_SBS is not set -+# CONFIG_BATTERY_BQ27x00 is not set -+# CONFIG_BATTERY_DA9052 is not set -+# CONFIG_BATTERY_MAX17040 is not set -+# CONFIG_BATTERY_MAX17042 is not set -+# CONFIG_CHARGER_ISP1704 is not set -+# CONFIG_CHARGER_MAX8903 is not set -+# CONFIG_CHARGER_LP8727 is not set -+CONFIG_CHARGER_GPIO=m -+# CONFIG_CHARGER_MANAGER is not set -+# CONFIG_CHARGER_BQ2415X is not set -+# CONFIG_CHARGER_BQ24190 is not set -+# CONFIG_CHARGER_BQ24735 is not set -+# CONFIG_CHARGER_SMB347 is not set -+# CONFIG_BATTERY_GAUGE_LTC2941 is not set -+CONFIG_POWER_RESET=y -+# CONFIG_POWER_RESET_BRCMSTB is not set -+CONFIG_POWER_RESET_GPIO=y -+CONFIG_POWER_RESET_GPIO_RESTART=y -+CONFIG_POWER_RESET_IMX=y -+CONFIG_POWER_RESET_LTC2952=y -+CONFIG_POWER_RESET_RESTART=y -+CONFIG_POWER_RESET_VERSATILE=y -+# CONFIG_POWER_RESET_SNVS is not set -+CONFIG_POWER_RESET_SYSCON=y -+# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set -+CONFIG_POWER_AVS=y -+CONFIG_HWMON=y -+# CONFIG_HWMON_VID is not set -+# CONFIG_HWMON_DEBUG_CHIP is not set -+ -+# -+# Native drivers -+# -+# CONFIG_SENSORS_AD7314 is not set -+# CONFIG_SENSORS_AD7414 is not set -+# CONFIG_SENSORS_AD7418 is not set -+# CONFIG_SENSORS_ADM1021 is not set -+# CONFIG_SENSORS_ADM1025 is not set -+# CONFIG_SENSORS_ADM1026 is not set -+# CONFIG_SENSORS_ADM1029 is not set -+# CONFIG_SENSORS_ADM1031 is not set -+# CONFIG_SENSORS_ADM9240 is not set -+# CONFIG_SENSORS_ADT7310 is not set -+# CONFIG_SENSORS_ADT7410 is not set -+# CONFIG_SENSORS_ADT7411 is not set -+# CONFIG_SENSORS_ADT7462 is not set -+# CONFIG_SENSORS_ADT7470 is not set -+# CONFIG_SENSORS_ADT7475 is not set -+# CONFIG_SENSORS_ASC7621 is not set -+# CONFIG_SENSORS_ATXP1 is not set -+# CONFIG_SENSORS_DS620 is not set -+# CONFIG_SENSORS_DS1621 is not set -+# CONFIG_SENSORS_DA9052_ADC is not set -+# CONFIG_SENSORS_I5K_AMB is not set -+# CONFIG_SENSORS_F71805F is not set -+# CONFIG_SENSORS_F71882FG is not set -+# CONFIG_SENSORS_F75375S is not set -+CONFIG_SENSORS_MC13783_ADC=y -+# CONFIG_SENSORS_GL518SM is not set -+# CONFIG_SENSORS_GL520SM is not set -+# CONFIG_SENSORS_G760A is not set -+# CONFIG_SENSORS_G762 is not set -+# CONFIG_SENSORS_GPIO_FAN is not set -+# CONFIG_SENSORS_HIH6130 is not set -+# CONFIG_SENSORS_IIO_HWMON is not set -+# CONFIG_SENSORS_IT87 is not set -+# CONFIG_SENSORS_JC42 is not set -+# CONFIG_SENSORS_POWR1220 is not set -+# CONFIG_SENSORS_LINEAGE is not set -+# CONFIG_SENSORS_LTC2945 is not set -+# CONFIG_SENSORS_LTC4151 is not set -+# CONFIG_SENSORS_LTC4215 is not set -+# CONFIG_SENSORS_LTC4222 is not set -+# CONFIG_SENSORS_LTC4245 is not set -+# CONFIG_SENSORS_LTC4260 is not set -+# CONFIG_SENSORS_LTC4261 is not set -+CONFIG_SENSORS_MAX1111=y -+CONFIG_SENSORS_MAX16065=y -+CONFIG_SENSORS_MAX1619=y -+CONFIG_SENSORS_MAX1668=y -+# CONFIG_SENSORS_MAX197 is not set -+# CONFIG_SENSORS_MAX6639 is not set -+# CONFIG_SENSORS_MAX6642 is not set -+# CONFIG_SENSORS_MAX6650 is not set -+# CONFIG_SENSORS_MAX6697 is not set -+# CONFIG_SENSORS_HTU21 is not set -+# CONFIG_SENSORS_MCP3021 is not set -+# CONFIG_SENSORS_ADCXX is not set -+# CONFIG_SENSORS_LM63 is not set -+# CONFIG_SENSORS_LM70 is not set -+# CONFIG_SENSORS_LM73 is not set -+# CONFIG_SENSORS_LM75 is not set -+# CONFIG_SENSORS_LM77 is not set -+# CONFIG_SENSORS_LM78 is not set -+# CONFIG_SENSORS_LM80 is not set -+# CONFIG_SENSORS_LM83 is not set -+# CONFIG_SENSORS_LM85 is not set -+# CONFIG_SENSORS_LM87 is not set -+# CONFIG_SENSORS_LM90 is not set -+# CONFIG_SENSORS_LM92 is not set -+# CONFIG_SENSORS_LM93 is not set -+# CONFIG_SENSORS_LM95234 is not set -+# CONFIG_SENSORS_LM95241 is not set -+# CONFIG_SENSORS_LM95245 is not set -+# CONFIG_SENSORS_PC87360 is not set -+# CONFIG_SENSORS_PC87427 is not set -+# CONFIG_SENSORS_NTC_THERMISTOR is not set -+# CONFIG_SENSORS_NCT6683 is not set -+# CONFIG_SENSORS_NCT6775 is not set -+# CONFIG_SENSORS_NCT7802 is not set -+# CONFIG_SENSORS_NCT7904 is not set -+# CONFIG_SENSORS_PCF8591 is not set -+# CONFIG_PMBUS is not set -+CONFIG_SENSORS_PWM_FAN=y -+# CONFIG_SENSORS_SHT15 is not set -+# CONFIG_SENSORS_SHT21 is not set -+# CONFIG_SENSORS_SHTC1 is not set -+# CONFIG_SENSORS_SIS5595 is not set -+# CONFIG_SENSORS_DME1737 is not set -+# CONFIG_SENSORS_EMC1403 is not set -+# CONFIG_SENSORS_EMC2103 is not set -+# CONFIG_SENSORS_EMC6W201 is not set -+# CONFIG_SENSORS_SMSC47M1 is not set -+# CONFIG_SENSORS_SMSC47M192 is not set -+# CONFIG_SENSORS_SMSC47B397 is not set -+# CONFIG_SENSORS_SCH56XX_COMMON is not set -+# CONFIG_SENSORS_SCH5627 is not set -+# CONFIG_SENSORS_SCH5636 is not set -+# CONFIG_SENSORS_SMM665 is not set -+# CONFIG_SENSORS_ADC128D818 is not set -+# CONFIG_SENSORS_ADS1015 is not set -+# CONFIG_SENSORS_ADS7828 is not set -+# CONFIG_SENSORS_ADS7871 is not set -+# CONFIG_SENSORS_AMC6821 is not set -+# CONFIG_SENSORS_INA209 is not set -+# CONFIG_SENSORS_INA2XX is not set -+# CONFIG_SENSORS_THMC50 is not set -+# CONFIG_SENSORS_TMP102 is not set -+# CONFIG_SENSORS_TMP103 is not set -+# CONFIG_SENSORS_TMP401 is not set -+# CONFIG_SENSORS_TMP421 is not set -+# CONFIG_SENSORS_VIA686A is not set -+# CONFIG_SENSORS_VT1211 is not set -+# CONFIG_SENSORS_VT8231 is not set -+# CONFIG_SENSORS_W83781D is not set -+# CONFIG_SENSORS_W83791D is not set -+# CONFIG_SENSORS_W83792D is not set -+# CONFIG_SENSORS_W83793 is not set -+# CONFIG_SENSORS_W83795 is not set -+# CONFIG_SENSORS_W83L785TS is not set -+# CONFIG_SENSORS_W83L786NG is not set -+# CONFIG_SENSORS_W83627HF is not set -+# CONFIG_SENSORS_W83627EHF is not set -+CONFIG_THERMAL=y -+CONFIG_THERMAL_HWMON=y -+CONFIG_THERMAL_OF=y -+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -+# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set -+# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set -+CONFIG_THERMAL_GOV_FAIR_SHARE=y -+CONFIG_THERMAL_GOV_STEP_WISE=y -+# CONFIG_THERMAL_GOV_BANG_BANG is not set -+CONFIG_THERMAL_GOV_USER_SPACE=y -+CONFIG_CPU_THERMAL=y -+CONFIG_CLOCK_THERMAL=y -+# CONFIG_THERMAL_EMULATION is not set -+CONFIG_IMX_THERMAL=y -+ -+# -+# Texas Instruments thermal drivers -+# -+CONFIG_WATCHDOG=y -+CONFIG_WATCHDOG_CORE=y -+# CONFIG_WATCHDOG_NOWAYOUT is not set -+ -+# -+# Watchdog Device Drivers -+# -+CONFIG_SOFT_WATCHDOG=m -+# CONFIG_DA9052_WATCHDOG is not set -+CONFIG_GPIO_WATCHDOG=m -+# CONFIG_XILINX_WATCHDOG is not set -+# CONFIG_CADENCE_WATCHDOG is not set -+# CONFIG_DW_WATCHDOG is not set -+# CONFIG_MAX63XX_WATCHDOG is not set -+CONFIG_IMX2_WDT=y -+# CONFIG_ALIM7101_WDT is not set -+# CONFIG_I6300ESB_WDT is not set -+# CONFIG_MEN_A21_WDT is not set -+ -+# -+# PCI-based Watchdog Cards -+# -+# CONFIG_PCIPCWATCHDOG is not set -+# CONFIG_WDTPCI is not set -+ -+# -+# USB-based Watchdog Cards -+# -+# CONFIG_USBPCWATCHDOG is not set -+CONFIG_SSB_POSSIBLE=y -+ -+# -+# Sonics Silicon Backplane -+# -+CONFIG_SSB=y -+CONFIG_SSB_SPROM=y -+CONFIG_SSB_BLOCKIO=y -+CONFIG_SSB_PCIHOST_POSSIBLE=y -+CONFIG_SSB_PCIHOST=y -+CONFIG_SSB_B43_PCI_BRIDGE=y -+CONFIG_SSB_SDIOHOST_POSSIBLE=y -+CONFIG_SSB_SDIOHOST=y -+# CONFIG_SSB_SILENT is not set -+# CONFIG_SSB_DEBUG is not set -+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y -+CONFIG_SSB_DRIVER_PCICORE=y -+# CONFIG_SSB_DRIVER_GPIO is not set -+CONFIG_BCMA_POSSIBLE=y -+ -+# -+# Broadcom specific AMBA -+# -+CONFIG_BCMA=m -+CONFIG_BCMA_BLOCKIO=y -+CONFIG_BCMA_HOST_PCI_POSSIBLE=y -+# CONFIG_BCMA_HOST_PCI is not set -+# CONFIG_BCMA_HOST_SOC is not set -+CONFIG_BCMA_DRIVER_PCI=y -+# CONFIG_BCMA_DRIVER_GMAC_CMN is not set -+# CONFIG_BCMA_DRIVER_GPIO is not set -+# CONFIG_BCMA_DEBUG is not set -+ -+# -+# Multifunction device drivers -+# -+CONFIG_MFD_CORE=y -+# CONFIG_MFD_AS3711 is not set -+# CONFIG_MFD_AS3722 is not set -+# CONFIG_PMIC_ADP5520 is not set -+# CONFIG_MFD_AAT2870_CORE is not set -+# CONFIG_MFD_ATMEL_HLCDC is not set -+# CONFIG_MFD_BCM590XX is not set -+# CONFIG_MFD_AXP20X is not set -+# CONFIG_MFD_CROS_EC is not set -+# CONFIG_MFD_ASIC3 is not set -+# CONFIG_PMIC_DA903X is not set -+CONFIG_PMIC_DA9052=y -+CONFIG_MFD_DA9052_SPI=y -+CONFIG_MFD_DA9052_I2C=y -+# CONFIG_MFD_DA9055 is not set -+# CONFIG_MFD_DA9063 is not set -+# CONFIG_MFD_DA9150 is not set -+CONFIG_MFD_MXC_HDMI=y -+# CONFIG_MFD_DLN2 is not set -+CONFIG_MFD_MC13XXX=y -+CONFIG_MFD_MC13XXX_SPI=y -+CONFIG_MFD_MC13XXX_I2C=y -+# CONFIG_MFD_HI6421_PMIC is not set -+# CONFIG_HTC_EGPIO is not set -+# CONFIG_HTC_PASIC3 is not set -+# CONFIG_HTC_I2CPLD is not set -+# CONFIG_LPC_ICH is not set -+# CONFIG_LPC_SCH is not set -+# CONFIG_INTEL_SOC_PMIC is not set -+# CONFIG_MFD_JANZ_CMODIO is not set -+# CONFIG_MFD_KEMPLD is not set -+# CONFIG_MFD_88PM800 is not set -+# CONFIG_MFD_88PM805 is not set -+# CONFIG_MFD_88PM860X is not set -+# CONFIG_MFD_MAX14577 is not set -+# CONFIG_MFD_MAX77686 is not set -+# CONFIG_MFD_MAX77693 is not set -+# CONFIG_MFD_MAX77843 is not set -+# CONFIG_MFD_MAX8907 is not set -+# CONFIG_MFD_MAX8925 is not set -+# CONFIG_MFD_MAX8997 is not set -+# CONFIG_MFD_MAX8998 is not set -+# CONFIG_MFD_MT6397 is not set -+# CONFIG_MFD_MENF21BMC is not set -+# CONFIG_EZX_PCAP is not set -+# CONFIG_MFD_VIPERBOARD is not set -+# CONFIG_MFD_RETU is not set -+# CONFIG_MFD_PCF50633 is not set -+# CONFIG_UCB1400_CORE is not set -+# CONFIG_MFD_PM8921_CORE is not set -+# CONFIG_MFD_RDC321X is not set -+# CONFIG_MFD_RTSX_PCI is not set -+# CONFIG_MFD_RT5033 is not set -+# CONFIG_MFD_RTSX_USB is not set -+# CONFIG_MFD_RC5T583 is not set -+# CONFIG_MFD_RK808 is not set -+# CONFIG_MFD_RN5T618 is not set -+# CONFIG_MFD_SEC_CORE is not set -+CONFIG_MFD_SI476X_CORE=y -+# CONFIG_MFD_SM501 is not set -+# CONFIG_MFD_SKY81452 is not set -+# CONFIG_MFD_SMSC is not set -+# CONFIG_ABX500_CORE is not set -+# CONFIG_MFD_STMPE is not set -+CONFIG_MFD_SYSCON=y -+# CONFIG_MFD_TI_AM335X_TSCADC is not set -+# CONFIG_MFD_LP3943 is not set -+# CONFIG_MFD_LP8788 is not set -+# CONFIG_MFD_PALMAS is not set -+# CONFIG_TPS6105X is not set -+# CONFIG_TPS65010 is not set -+# CONFIG_TPS6507X is not set -+# CONFIG_MFD_TPS65090 is not set -+# CONFIG_MFD_TPS65217 is not set -+# CONFIG_MFD_TPS65218 is not set -+# CONFIG_MFD_TPS6586X is not set -+# CONFIG_MFD_TPS65910 is not set -+# CONFIG_MFD_TPS65912 is not set -+# CONFIG_MFD_TPS65912_I2C is not set -+# CONFIG_MFD_TPS65912_SPI is not set -+# CONFIG_MFD_TPS80031 is not set -+# CONFIG_TWL4030_CORE is not set -+# CONFIG_TWL6040_CORE is not set -+CONFIG_MFD_WL1273_CORE=m -+# CONFIG_MFD_LM3533 is not set -+# CONFIG_MFD_TC3589X is not set -+# CONFIG_MFD_TMIO is not set -+# CONFIG_MFD_T7L66XB is not set -+# CONFIG_MFD_TC6387XB is not set -+# CONFIG_MFD_TC6393XB is not set -+# CONFIG_MFD_VX855 is not set -+# CONFIG_MFD_ARIZONA_I2C is not set -+# CONFIG_MFD_ARIZONA_SPI is not set -+# CONFIG_MFD_WM8400 is not set -+# CONFIG_MFD_WM831X_I2C is not set -+# CONFIG_MFD_WM831X_SPI is not set -+# CONFIG_MFD_WM8350_I2C is not set -+# CONFIG_MFD_WM8994 is not set -+CONFIG_REGULATOR=y -+# CONFIG_REGULATOR_DEBUG is not set -+CONFIG_REGULATOR_FIXED_VOLTAGE=y -+CONFIG_REGULATOR_VIRTUAL_CONSUMER=y -+CONFIG_REGULATOR_USERSPACE_CONSUMER=m -+# CONFIG_REGULATOR_ACT8865 is not set -+# CONFIG_REGULATOR_AD5398 is not set -+CONFIG_REGULATOR_ANATOP=y -+# CONFIG_REGULATOR_DA9052 is not set -+# CONFIG_REGULATOR_DA9210 is not set -+# CONFIG_REGULATOR_DA9211 is not set -+# CONFIG_REGULATOR_FAN53555 is not set -+CONFIG_REGULATOR_GPIO=y -+# CONFIG_REGULATOR_ISL9305 is not set -+# CONFIG_REGULATOR_ISL6271A is not set -+# CONFIG_REGULATOR_LP3971 is not set -+# CONFIG_REGULATOR_LP3972 is not set -+# CONFIG_REGULATOR_LP872X is not set -+# CONFIG_REGULATOR_LP8755 is not set -+# CONFIG_REGULATOR_LTC3589 is not set -+# CONFIG_REGULATOR_MAX1586 is not set -+# CONFIG_REGULATOR_MAX8649 is not set -+# CONFIG_REGULATOR_MAX8660 is not set -+# CONFIG_REGULATOR_MAX8952 is not set -+# CONFIG_REGULATOR_MAX8973 is not set -+CONFIG_REGULATOR_MC13XXX_CORE=y -+CONFIG_REGULATOR_MC13783=y -+CONFIG_REGULATOR_MC13892=y -+CONFIG_REGULATOR_PFUZE100=y -+CONFIG_REGULATOR_PWM=y -+# CONFIG_REGULATOR_TPS51632 is not set -+# CONFIG_REGULATOR_TPS62360 is not set -+# CONFIG_REGULATOR_TPS65023 is not set -+# CONFIG_REGULATOR_TPS6507X is not set -+# CONFIG_REGULATOR_TPS6524X is not set -+CONFIG_MEDIA_SUPPORT=m -+ -+# -+# Multimedia core support -+# -+CONFIG_MEDIA_CAMERA_SUPPORT=y -+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y -+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y -+CONFIG_MEDIA_RADIO_SUPPORT=y -+CONFIG_MEDIA_SDR_SUPPORT=y -+CONFIG_MEDIA_RC_SUPPORT=y -+CONFIG_MEDIA_CONTROLLER=y -+CONFIG_VIDEO_DEV=m -+CONFIG_VIDEO_V4L2_SUBDEV_API=y -+CONFIG_VIDEO_V4L2=m -+# CONFIG_VIDEO_ADV_DEBUG is not set -+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set -+CONFIG_VIDEO_TUNER=m -+CONFIG_V4L2_MEM2MEM_DEV=m -+CONFIG_VIDEOBUF_GEN=m -+CONFIG_VIDEOBUF_DMA_SG=m -+CONFIG_VIDEOBUF_VMALLOC=m -+CONFIG_VIDEOBUF_DVB=m -+CONFIG_VIDEOBUF2_CORE=m -+CONFIG_VIDEOBUF2_MEMOPS=m -+CONFIG_VIDEOBUF2_DMA_CONTIG=m -+CONFIG_VIDEOBUF2_VMALLOC=m -+CONFIG_VIDEOBUF2_DMA_SG=m -+CONFIG_VIDEOBUF2_DVB=m -+CONFIG_DVB_CORE=m -+CONFIG_DVB_NET=y -+CONFIG_TTPCI_EEPROM=m -+CONFIG_DVB_MAX_ADAPTERS=8 -+# CONFIG_DVB_DYNAMIC_MINORS is not set -+ -+# -+# Media drivers -+# -+CONFIG_RC_CORE=m -+CONFIG_RC_MAP=m -+CONFIG_RC_DECODERS=y -+CONFIG_LIRC=m -+CONFIG_IR_LIRC_CODEC=m -+CONFIG_IR_NEC_DECODER=m -+CONFIG_IR_RC5_DECODER=m -+CONFIG_IR_RC6_DECODER=m -+CONFIG_IR_JVC_DECODER=m -+CONFIG_IR_SONY_DECODER=m -+CONFIG_IR_SANYO_DECODER=m -+CONFIG_IR_SHARP_DECODER=m -+CONFIG_IR_MCE_KBD_DECODER=m -+CONFIG_IR_XMP_DECODER=m -+CONFIG_RC_DEVICES=y -+CONFIG_RC_ATI_REMOTE=m -+CONFIG_IR_HIX5HD2=m -+CONFIG_IR_IMON=m -+CONFIG_IR_MCEUSB=m -+CONFIG_IR_REDRAT3=m -+CONFIG_IR_STREAMZAP=m -+CONFIG_IR_IGORPLUGUSB=m -+CONFIG_IR_IGUANA=m -+CONFIG_IR_TTUSBIR=m -+CONFIG_RC_LOOPBACK=m -+CONFIG_IR_GPIO_CIR=m -+CONFIG_MEDIA_USB_SUPPORT=y -+ -+# -+# Webcam devices -+# -+CONFIG_USB_VIDEO_CLASS=m -+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y -+CONFIG_USB_GSPCA=m -+CONFIG_USB_M5602=m -+CONFIG_USB_STV06XX=m -+CONFIG_USB_GL860=m -+CONFIG_USB_GSPCA_BENQ=m -+CONFIG_USB_GSPCA_CONEX=m -+CONFIG_USB_GSPCA_CPIA1=m -+CONFIG_USB_GSPCA_DTCS033=m -+CONFIG_USB_GSPCA_ETOMS=m -+CONFIG_USB_GSPCA_FINEPIX=m -+CONFIG_USB_GSPCA_JEILINJ=m -+CONFIG_USB_GSPCA_JL2005BCD=m -+CONFIG_USB_GSPCA_KINECT=m -+CONFIG_USB_GSPCA_KONICA=m -+CONFIG_USB_GSPCA_MARS=m -+CONFIG_USB_GSPCA_MR97310A=m -+CONFIG_USB_GSPCA_NW80X=m -+CONFIG_USB_GSPCA_OV519=m -+CONFIG_USB_GSPCA_OV534=m -+CONFIG_USB_GSPCA_OV534_9=m -+CONFIG_USB_GSPCA_PAC207=m -+CONFIG_USB_GSPCA_PAC7302=m -+CONFIG_USB_GSPCA_PAC7311=m -+CONFIG_USB_GSPCA_SE401=m -+CONFIG_USB_GSPCA_SN9C2028=m -+CONFIG_USB_GSPCA_SN9C20X=m -+CONFIG_USB_GSPCA_SONIXB=m -+CONFIG_USB_GSPCA_SONIXJ=m -+CONFIG_USB_GSPCA_SPCA500=m -+CONFIG_USB_GSPCA_SPCA501=m -+CONFIG_USB_GSPCA_SPCA505=m -+CONFIG_USB_GSPCA_SPCA506=m -+CONFIG_USB_GSPCA_SPCA508=m -+CONFIG_USB_GSPCA_SPCA561=m -+CONFIG_USB_GSPCA_SPCA1528=m -+CONFIG_USB_GSPCA_SQ905=m -+CONFIG_USB_GSPCA_SQ905C=m -+CONFIG_USB_GSPCA_SQ930X=m -+CONFIG_USB_GSPCA_STK014=m -+CONFIG_USB_GSPCA_STK1135=m -+CONFIG_USB_GSPCA_STV0680=m -+CONFIG_USB_GSPCA_SUNPLUS=m -+CONFIG_USB_GSPCA_T613=m -+CONFIG_USB_GSPCA_TOPRO=m -+# CONFIG_USB_GSPCA_TOUPTEK is not set -+CONFIG_USB_GSPCA_TV8532=m -+CONFIG_USB_GSPCA_VC032X=m -+CONFIG_USB_GSPCA_VICAM=m -+CONFIG_USB_GSPCA_XIRLINK_CIT=m -+CONFIG_USB_GSPCA_ZC3XX=m -+CONFIG_USB_PWC=m -+# CONFIG_USB_PWC_DEBUG is not set -+CONFIG_USB_PWC_INPUT_EVDEV=y -+CONFIG_VIDEO_CPIA2=m -+CONFIG_USB_ZR364XX=m -+CONFIG_USB_STKWEBCAM=m -+CONFIG_USB_S2255=m -+CONFIG_VIDEO_USBTV=m -+ -+# -+# Analog TV USB devices -+# -+CONFIG_VIDEO_PVRUSB2=m -+CONFIG_VIDEO_PVRUSB2_SYSFS=y -+CONFIG_VIDEO_PVRUSB2_DVB=y -+# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set -+CONFIG_VIDEO_HDPVR=m -+CONFIG_VIDEO_USBVISION=m -+CONFIG_VIDEO_STK1160_COMMON=m -+CONFIG_VIDEO_STK1160_AC97=y -+CONFIG_VIDEO_STK1160=m -+CONFIG_VIDEO_GO7007=m -+CONFIG_VIDEO_GO7007_USB=m -+CONFIG_VIDEO_GO7007_LOADER=m -+CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m -+ -+# -+# Analog/digital TV USB devices -+# -+CONFIG_VIDEO_AU0828=m -+CONFIG_VIDEO_AU0828_V4L2=y -+CONFIG_VIDEO_AU0828_RC=y -+CONFIG_VIDEO_CX231XX=m -+CONFIG_VIDEO_CX231XX_RC=y -+CONFIG_VIDEO_CX231XX_ALSA=m -+CONFIG_VIDEO_CX231XX_DVB=m -+CONFIG_VIDEO_TM6000=m -+CONFIG_VIDEO_TM6000_ALSA=m -+CONFIG_VIDEO_TM6000_DVB=m -+ -+# -+# Digital TV USB devices -+# -+CONFIG_DVB_USB=m -+# CONFIG_DVB_USB_DEBUG is not set -+CONFIG_DVB_USB_A800=m -+CONFIG_DVB_USB_DIBUSB_MB=m -+CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y -+CONFIG_DVB_USB_DIBUSB_MC=m -+CONFIG_DVB_USB_DIB0700=m -+CONFIG_DVB_USB_UMT_010=m -+CONFIG_DVB_USB_CXUSB=m -+CONFIG_DVB_USB_M920X=m -+CONFIG_DVB_USB_DIGITV=m -+CONFIG_DVB_USB_VP7045=m -+CONFIG_DVB_USB_VP702X=m -+CONFIG_DVB_USB_GP8PSK=m -+CONFIG_DVB_USB_NOVA_T_USB2=m -+CONFIG_DVB_USB_TTUSB2=m -+CONFIG_DVB_USB_DTT200U=m -+CONFIG_DVB_USB_OPERA1=m -+CONFIG_DVB_USB_AF9005=m -+CONFIG_DVB_USB_AF9005_REMOTE=m -+CONFIG_DVB_USB_PCTV452E=m -+CONFIG_DVB_USB_DW2102=m -+CONFIG_DVB_USB_CINERGY_T2=m -+CONFIG_DVB_USB_DTV5100=m -+CONFIG_DVB_USB_FRIIO=m -+CONFIG_DVB_USB_AZ6027=m -+CONFIG_DVB_USB_TECHNISAT_USB2=m -+CONFIG_DVB_USB_V2=m -+CONFIG_DVB_USB_AF9015=m -+CONFIG_DVB_USB_AF9035=m -+CONFIG_DVB_USB_ANYSEE=m -+CONFIG_DVB_USB_AU6610=m -+CONFIG_DVB_USB_AZ6007=m -+CONFIG_DVB_USB_CE6230=m -+CONFIG_DVB_USB_EC168=m -+CONFIG_DVB_USB_GL861=m -+CONFIG_DVB_USB_LME2510=m -+CONFIG_DVB_USB_MXL111SF=m -+CONFIG_DVB_USB_RTL28XXU=m -+CONFIG_DVB_USB_DVBSKY=m -+CONFIG_DVB_TTUSB_BUDGET=m -+CONFIG_DVB_TTUSB_DEC=m -+CONFIG_SMS_USB_DRV=m -+CONFIG_DVB_B2C2_FLEXCOP_USB=m -+# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set -+CONFIG_DVB_AS102=m -+ -+# -+# Webcam, TV (analog/digital) USB devices -+# -+CONFIG_VIDEO_EM28XX=m -+CONFIG_VIDEO_EM28XX_V4L2=m -+CONFIG_VIDEO_EM28XX_ALSA=m -+CONFIG_VIDEO_EM28XX_DVB=m -+CONFIG_VIDEO_EM28XX_RC=m -+ -+# -+# Software defined radio USB devices -+# -+CONFIG_USB_AIRSPY=m -+CONFIG_USB_HACKRF=m -+CONFIG_USB_MSI2500=m -+CONFIG_MEDIA_PCI_SUPPORT=y -+ -+# -+# Media capture support -+# -+ -+# -+# Media capture/analog TV support -+# -+CONFIG_VIDEO_IVTV=m -+CONFIG_VIDEO_IVTV_ALSA=m -+CONFIG_VIDEO_FB_IVTV=m -+CONFIG_VIDEO_HEXIUM_GEMINI=m -+CONFIG_VIDEO_HEXIUM_ORION=m -+CONFIG_VIDEO_MXB=m -+CONFIG_VIDEO_SOLO6X10=m -+CONFIG_VIDEO_TW68=m -+ -+# -+# Media capture/analog/hybrid TV support -+# -+CONFIG_VIDEO_CX18=m -+CONFIG_VIDEO_CX18_ALSA=m -+CONFIG_VIDEO_CX23885=m -+CONFIG_MEDIA_ALTERA_CI=m -+CONFIG_VIDEO_CX25821=m -+CONFIG_VIDEO_CX25821_ALSA=m -+CONFIG_VIDEO_CX88=m -+CONFIG_VIDEO_CX88_ALSA=m -+CONFIG_VIDEO_CX88_BLACKBIRD=m -+CONFIG_VIDEO_CX88_DVB=m -+CONFIG_VIDEO_CX88_ENABLE_VP3054=y -+CONFIG_VIDEO_CX88_VP3054=m -+CONFIG_VIDEO_CX88_MPEG=m -+# CONFIG_VIDEO_BT848 is not set -+CONFIG_VIDEO_SAA7134=m -+CONFIG_VIDEO_SAA7134_ALSA=m -+CONFIG_VIDEO_SAA7134_RC=y -+CONFIG_VIDEO_SAA7134_DVB=m -+CONFIG_VIDEO_SAA7134_GO7007=m -+CONFIG_VIDEO_SAA7164=m -+ -+# -+# Media digital TV PCI Adapters -+# -+CONFIG_DVB_AV7110_IR=y -+CONFIG_DVB_AV7110=m -+CONFIG_DVB_AV7110_OSD=y -+CONFIG_DVB_BUDGET_CORE=m -+CONFIG_DVB_BUDGET=m -+CONFIG_DVB_BUDGET_CI=m -+CONFIG_DVB_BUDGET_AV=m -+CONFIG_DVB_BUDGET_PATCH=m -+CONFIG_DVB_B2C2_FLEXCOP_PCI=m -+# CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set -+CONFIG_DVB_PLUTO2=m -+CONFIG_DVB_DM1105=m -+CONFIG_DVB_PT1=m -+CONFIG_DVB_PT3=m -+CONFIG_MANTIS_CORE=m -+CONFIG_DVB_MANTIS=m -+CONFIG_DVB_HOPPER=m -+CONFIG_DVB_NGENE=m -+CONFIG_DVB_DDBRIDGE=m -+CONFIG_DVB_SMIPCIE=m -+CONFIG_V4L_PLATFORM_DRIVERS=y -+# CONFIG_VIDEO_CAFE_CCIC is not set -+# CONFIG_VIDEO_MXC_OUTPUT is not set -+# CONFIG_VIDEO_MXC_CAPTURE is not set -+CONFIG_SOC_CAMERA=m -+CONFIG_SOC_CAMERA_PLATFORM=m -+# CONFIG_VIDEO_XILINX is not set -+CONFIG_V4L_MEM2MEM_DRIVERS=y -+# CONFIG_VIDEO_CODA is not set -+CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m -+CONFIG_VIDEO_SH_VEU=m -+# CONFIG_V4L_TEST_DRIVERS is not set -+ -+# -+# Supported MMC/SDIO adapters -+# -+CONFIG_SMS_SDIO_DRV=m -+CONFIG_RADIO_ADAPTERS=y -+CONFIG_RADIO_TEA575X=m -+# CONFIG_RADIO_SI470X is not set -+CONFIG_RADIO_SI4713=m -+CONFIG_USB_SI4713=m -+CONFIG_PLATFORM_SI4713=m -+CONFIG_I2C_SI4713=m -+CONFIG_RADIO_SI476X=m -+CONFIG_USB_MR800=m -+CONFIG_USB_DSBR=m -+CONFIG_RADIO_MAXIRADIO=m -+CONFIG_RADIO_SHARK=m -+CONFIG_RADIO_SHARK2=m -+CONFIG_USB_KEENE=m -+CONFIG_USB_RAREMONO=m -+CONFIG_USB_MA901=m -+CONFIG_RADIO_TEA5764=m -+CONFIG_RADIO_SAA7706H=m -+CONFIG_RADIO_TEF6862=m -+CONFIG_RADIO_WL1273=m -+ -+# -+# Texas Instruments WL128x FM driver (ST based) -+# -+CONFIG_RADIO_WL128X=m -+CONFIG_MEDIA_COMMON_OPTIONS=y -+ -+# -+# common driver options -+# -+CONFIG_VIDEO_CX2341X=m -+CONFIG_VIDEO_TVEEPROM=m -+CONFIG_CYPRESS_FIRMWARE=m -+CONFIG_DVB_B2C2_FLEXCOP=m -+CONFIG_VIDEO_SAA7146=m -+CONFIG_VIDEO_SAA7146_VV=m -+CONFIG_SMS_SIANO_MDTV=m -+CONFIG_SMS_SIANO_RC=y -+# CONFIG_SMS_SIANO_DEBUGFS is not set -+ -+# -+# Media ancillary drivers (tuners, sensors, i2c, frontends) -+# -+# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set -+CONFIG_MEDIA_ATTACH=y -+CONFIG_VIDEO_IR_I2C=m -+ -+# -+# Encoders, decoders, sensors and other helper chips -+# -+ -+# -+# Audio decoders, processors and mixers -+# -+CONFIG_VIDEO_TVAUDIO=m -+CONFIG_VIDEO_TDA7432=m -+CONFIG_VIDEO_TDA9840=m -+CONFIG_VIDEO_TEA6415C=m -+CONFIG_VIDEO_TEA6420=m -+CONFIG_VIDEO_MSP3400=m -+CONFIG_VIDEO_CS5345=m -+CONFIG_VIDEO_CS53L32A=m -+CONFIG_VIDEO_TLV320AIC23B=m -+CONFIG_VIDEO_UDA1342=m -+CONFIG_VIDEO_WM8775=m -+CONFIG_VIDEO_WM8739=m -+CONFIG_VIDEO_VP27SMPX=m -+CONFIG_VIDEO_SONY_BTF_MPX=m -+ -+# -+# RDS decoders -+# -+CONFIG_VIDEO_SAA6588=m -+ -+# -+# Video decoders -+# -+CONFIG_VIDEO_ADV7180=m -+CONFIG_VIDEO_ADV7183=m -+CONFIG_VIDEO_ADV7604=m -+CONFIG_VIDEO_ADV7842=m -+CONFIG_VIDEO_BT819=m -+CONFIG_VIDEO_BT856=m -+CONFIG_VIDEO_BT866=m -+CONFIG_VIDEO_KS0127=m -+CONFIG_VIDEO_ML86V7667=m -+CONFIG_VIDEO_SAA7110=m -+CONFIG_VIDEO_SAA711X=m -+CONFIG_VIDEO_TVP514X=m -+CONFIG_VIDEO_TVP5150=m -+CONFIG_VIDEO_TVP7002=m -+CONFIG_VIDEO_TW2804=m -+CONFIG_VIDEO_TW9903=m -+CONFIG_VIDEO_TW9906=m -+CONFIG_VIDEO_VPX3220=m -+ -+# -+# Video and audio decoders -+# -+CONFIG_VIDEO_SAA717X=m -+CONFIG_VIDEO_CX25840=m -+ -+# -+# Video encoders -+# -+CONFIG_VIDEO_SAA7127=m -+CONFIG_VIDEO_SAA7185=m -+CONFIG_VIDEO_ADV7170=m -+CONFIG_VIDEO_ADV7175=m -+CONFIG_VIDEO_ADV7343=m -+CONFIG_VIDEO_ADV7393=m -+CONFIG_VIDEO_ADV7511=m -+CONFIG_VIDEO_AD9389B=m -+CONFIG_VIDEO_AK881X=m -+CONFIG_VIDEO_THS8200=m -+ -+# -+# Camera sensor devices -+# -+CONFIG_VIDEO_APTINA_PLL=m -+CONFIG_VIDEO_SMIAPP_PLL=m -+CONFIG_VIDEO_OV2659=m -+CONFIG_VIDEO_OV7640=m -+CONFIG_VIDEO_OV7670=m -+CONFIG_VIDEO_OV9650=m -+CONFIG_VIDEO_VS6624=m -+CONFIG_VIDEO_MT9M032=m -+CONFIG_VIDEO_MT9P031=m -+CONFIG_VIDEO_MT9T001=m -+CONFIG_VIDEO_MT9V011=m -+CONFIG_VIDEO_MT9V032=m -+CONFIG_VIDEO_SR030PC30=m -+CONFIG_VIDEO_NOON010PC30=m -+CONFIG_VIDEO_M5MOLS=m -+CONFIG_VIDEO_S5K6AA=m -+CONFIG_VIDEO_S5K6A3=m -+CONFIG_VIDEO_S5K4ECGX=m -+CONFIG_VIDEO_S5K5BAF=m -+CONFIG_VIDEO_SMIAPP=m -+CONFIG_VIDEO_S5C73M3=m -+ -+# -+# Flash devices -+# -+CONFIG_VIDEO_ADP1653=m -+CONFIG_VIDEO_AS3645A=m -+CONFIG_VIDEO_LM3560=m -+CONFIG_VIDEO_LM3646=m -+ -+# -+# Video improvement chips -+# -+CONFIG_VIDEO_UPD64031A=m -+CONFIG_VIDEO_UPD64083=m -+ -+# -+# Audio/Video compression chips -+# -+CONFIG_VIDEO_SAA6752HS=m -+ -+# -+# Miscellaneous helper chips -+# -+CONFIG_VIDEO_THS7303=m -+CONFIG_VIDEO_M52790=m -+ -+# -+# Sensors used on soc_camera driver -+# -+ -+# -+# soc_camera sensor drivers -+# -+CONFIG_SOC_CAMERA_IMX074=m -+CONFIG_SOC_CAMERA_MT9M001=m -+CONFIG_SOC_CAMERA_MT9M111=m -+CONFIG_SOC_CAMERA_MT9T031=m -+CONFIG_SOC_CAMERA_MT9T112=m -+CONFIG_SOC_CAMERA_MT9V022=m -+CONFIG_SOC_CAMERA_OV2640=m -+CONFIG_SOC_CAMERA_OV5642=m -+CONFIG_SOC_CAMERA_OV6650=m -+CONFIG_SOC_CAMERA_OV772X=m -+CONFIG_SOC_CAMERA_OV9640=m -+CONFIG_SOC_CAMERA_OV9740=m -+CONFIG_SOC_CAMERA_RJ54N1=m -+CONFIG_SOC_CAMERA_TW9910=m -+CONFIG_MEDIA_TUNER=m -+ -+# -+# Customize TV tuners -+# -+CONFIG_MEDIA_TUNER_SIMPLE=m -+CONFIG_MEDIA_TUNER_TDA8290=m -+CONFIG_MEDIA_TUNER_TDA827X=m -+CONFIG_MEDIA_TUNER_TDA18271=m -+CONFIG_MEDIA_TUNER_TDA9887=m -+CONFIG_MEDIA_TUNER_TEA5761=m -+CONFIG_MEDIA_TUNER_TEA5767=m -+CONFIG_MEDIA_TUNER_MSI001=m -+CONFIG_MEDIA_TUNER_MT20XX=m -+CONFIG_MEDIA_TUNER_MT2060=m -+CONFIG_MEDIA_TUNER_MT2063=m -+CONFIG_MEDIA_TUNER_MT2266=m -+CONFIG_MEDIA_TUNER_MT2131=m -+CONFIG_MEDIA_TUNER_QT1010=m -+CONFIG_MEDIA_TUNER_XC2028=m -+CONFIG_MEDIA_TUNER_XC5000=m -+CONFIG_MEDIA_TUNER_XC4000=m -+CONFIG_MEDIA_TUNER_MXL5005S=m -+CONFIG_MEDIA_TUNER_MXL5007T=m -+CONFIG_MEDIA_TUNER_MC44S803=m -+CONFIG_MEDIA_TUNER_MAX2165=m -+CONFIG_MEDIA_TUNER_TDA18218=m -+CONFIG_MEDIA_TUNER_FC0011=m -+CONFIG_MEDIA_TUNER_FC0012=m -+CONFIG_MEDIA_TUNER_FC0013=m -+CONFIG_MEDIA_TUNER_TDA18212=m -+CONFIG_MEDIA_TUNER_E4000=m -+CONFIG_MEDIA_TUNER_FC2580=m -+CONFIG_MEDIA_TUNER_M88RS6000T=m -+CONFIG_MEDIA_TUNER_TUA9001=m -+CONFIG_MEDIA_TUNER_SI2157=m -+CONFIG_MEDIA_TUNER_IT913X=m -+CONFIG_MEDIA_TUNER_R820T=m -+CONFIG_MEDIA_TUNER_MXL301RF=m -+CONFIG_MEDIA_TUNER_QM1D1C0042=m -+ -+# -+# Customise DVB Frontends -+# -+ -+# -+# Multistandard (satellite) frontends -+# -+CONFIG_DVB_STB0899=m -+CONFIG_DVB_STB6100=m -+CONFIG_DVB_STV090x=m -+CONFIG_DVB_STV6110x=m -+CONFIG_DVB_M88DS3103=m -+ -+# -+# Multistandard (cable + terrestrial) frontends -+# -+CONFIG_DVB_DRXK=m -+CONFIG_DVB_TDA18271C2DD=m -+CONFIG_DVB_SI2165=m -+ -+# -+# DVB-S (satellite) frontends -+# -+CONFIG_DVB_CX24110=m -+CONFIG_DVB_CX24123=m -+CONFIG_DVB_MT312=m -+CONFIG_DVB_ZL10036=m -+CONFIG_DVB_ZL10039=m -+CONFIG_DVB_S5H1420=m -+CONFIG_DVB_STV0288=m -+CONFIG_DVB_STB6000=m -+CONFIG_DVB_STV0299=m -+CONFIG_DVB_STV6110=m -+CONFIG_DVB_STV0900=m -+CONFIG_DVB_TDA8083=m -+CONFIG_DVB_TDA10086=m -+CONFIG_DVB_TDA8261=m -+CONFIG_DVB_VES1X93=m -+CONFIG_DVB_TUNER_ITD1000=m -+CONFIG_DVB_TUNER_CX24113=m -+CONFIG_DVB_TDA826X=m -+CONFIG_DVB_TUA6100=m -+CONFIG_DVB_CX24116=m -+CONFIG_DVB_CX24117=m -+CONFIG_DVB_SI21XX=m -+CONFIG_DVB_TS2020=m -+CONFIG_DVB_DS3000=m -+CONFIG_DVB_MB86A16=m -+CONFIG_DVB_TDA10071=m -+ -+# -+# DVB-T (terrestrial) frontends -+# -+CONFIG_DVB_SP8870=m -+CONFIG_DVB_SP887X=m -+CONFIG_DVB_CX22700=m -+CONFIG_DVB_CX22702=m -+CONFIG_DVB_S5H1432=m -+CONFIG_DVB_DRXD=m -+CONFIG_DVB_L64781=m -+CONFIG_DVB_TDA1004X=m -+CONFIG_DVB_NXT6000=m -+CONFIG_DVB_MT352=m -+CONFIG_DVB_ZL10353=m -+CONFIG_DVB_DIB3000MB=m -+CONFIG_DVB_DIB3000MC=m -+CONFIG_DVB_DIB7000M=m -+CONFIG_DVB_DIB7000P=m -+CONFIG_DVB_DIB9000=m -+CONFIG_DVB_TDA10048=m -+CONFIG_DVB_AF9013=m -+CONFIG_DVB_EC100=m -+CONFIG_DVB_HD29L2=m -+CONFIG_DVB_STV0367=m -+CONFIG_DVB_CXD2820R=m -+CONFIG_DVB_RTL2830=m -+CONFIG_DVB_RTL2832=m -+CONFIG_DVB_RTL2832_SDR=m -+CONFIG_DVB_SI2168=m -+CONFIG_DVB_AS102_FE=m -+ -+# -+# DVB-C (cable) frontends -+# -+CONFIG_DVB_VES1820=m -+CONFIG_DVB_TDA10021=m -+CONFIG_DVB_TDA10023=m -+CONFIG_DVB_STV0297=m -+ -+# -+# ATSC (North American/Korean Terrestrial/Cable DTV) frontends -+# -+CONFIG_DVB_NXT200X=m -+CONFIG_DVB_OR51211=m -+CONFIG_DVB_OR51132=m -+CONFIG_DVB_BCM3510=m -+CONFIG_DVB_LGDT330X=m -+CONFIG_DVB_LGDT3305=m -+CONFIG_DVB_LGDT3306A=m -+CONFIG_DVB_LG2160=m -+CONFIG_DVB_S5H1409=m -+CONFIG_DVB_AU8522=m -+CONFIG_DVB_AU8522_DTV=m -+CONFIG_DVB_AU8522_V4L=m -+CONFIG_DVB_S5H1411=m -+ -+# -+# ISDB-T (terrestrial) frontends -+# -+CONFIG_DVB_S921=m -+CONFIG_DVB_DIB8000=m -+CONFIG_DVB_MB86A20S=m -+ -+# -+# ISDB-S (satellite) & ISDB-T (terrestrial) frontends -+# -+CONFIG_DVB_TC90522=m -+ -+# -+# Digital terrestrial only tuners/PLL -+# -+CONFIG_DVB_PLL=m -+CONFIG_DVB_TUNER_DIB0070=m -+CONFIG_DVB_TUNER_DIB0090=m -+ -+# -+# SEC control devices for DVB-S -+# -+CONFIG_DVB_DRX39XYJ=m -+CONFIG_DVB_LNBP21=m -+CONFIG_DVB_LNBP22=m -+CONFIG_DVB_ISL6405=m -+CONFIG_DVB_ISL6421=m -+CONFIG_DVB_ISL6423=m -+CONFIG_DVB_A8293=m -+CONFIG_DVB_SP2=m -+CONFIG_DVB_LGS8GL5=m -+CONFIG_DVB_LGS8GXX=m -+CONFIG_DVB_ATBM8830=m -+CONFIG_DVB_TDA665x=m -+CONFIG_DVB_IX2505V=m -+CONFIG_DVB_M88RS2000=m -+CONFIG_DVB_AF9033=m -+ -+# -+# Tools to develop new frontends -+# -+CONFIG_DVB_DUMMY_FE=m -+ -+# -+# Graphics support -+# -+# CONFIG_VGA_ARB is not set -+# CONFIG_IMX_IPUV3_CORE is not set -+ -+# -+# Direct Rendering Manager -+# -+CONFIG_DRM=m -+# CONFIG_DRM_PTN3460 is not set -+# CONFIG_DRM_PS8622 is not set -+# CONFIG_DRM_TDFX is not set -+# CONFIG_DRM_R128 is not set -+# CONFIG_DRM_RADEON is not set -+# CONFIG_DRM_NOUVEAU is not set -+# CONFIG_DRM_MGA is not set -+# CONFIG_DRM_VIA is not set -+# CONFIG_DRM_SAVAGE is not set -+# CONFIG_DRM_VGEM is not set -+# CONFIG_DRM_EXYNOS is not set -+# CONFIG_DRM_VMWGFX is not set -+# CONFIG_DRM_UDL is not set -+# CONFIG_DRM_AST is not set -+# CONFIG_DRM_MGAG200 is not set -+# CONFIG_DRM_CIRRUS_QEMU is not set -+# CONFIG_DRM_ARMADA is not set -+# CONFIG_DRM_TILCDC is not set -+# CONFIG_DRM_QXL is not set -+# CONFIG_DRM_BOCHS is not set -+# CONFIG_DRM_STI is not set -+CONFIG_DRM_VIVANTE=m -+ -+# -+# Frame buffer Devices -+# -+CONFIG_FB=y -+CONFIG_FIRMWARE_EDID=y -+CONFIG_FB_CMDLINE=y -+# CONFIG_FB_DDC is not set -+# CONFIG_FB_BOOT_VESA_SUPPORT is not set -+CONFIG_FB_CFB_FILLRECT=y -+CONFIG_FB_CFB_COPYAREA=y -+CONFIG_FB_CFB_IMAGEBLIT=y -+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -+CONFIG_FB_SYS_FILLRECT=m -+CONFIG_FB_SYS_COPYAREA=m -+CONFIG_FB_SYS_IMAGEBLIT=m -+# CONFIG_FB_FOREIGN_ENDIAN is not set -+CONFIG_FB_SYS_FOPS=m -+CONFIG_FB_DEFERRED_IO=y -+# CONFIG_FB_SVGALIB is not set -+# CONFIG_FB_MACMODES is not set -+# CONFIG_FB_BACKLIGHT is not set -+CONFIG_FB_MODE_HELPERS=y -+CONFIG_FB_TILEBLITTING=y -+ -+# -+# Frame buffer hardware drivers -+# -+# CONFIG_FB_CIRRUS is not set -+# CONFIG_FB_PM2 is not set -+# CONFIG_FB_IMX is not set -+# CONFIG_FB_CYBER2000 is not set -+# CONFIG_FB_ASILIANT is not set -+# CONFIG_FB_IMSTT is not set -+# CONFIG_FB_UVESA is not set -+# CONFIG_FB_OPENCORES is not set -+# CONFIG_FB_S1D13XXX is not set -+# CONFIG_FB_NVIDIA is not set -+# CONFIG_FB_RIVA is not set -+# CONFIG_FB_I740 is not set -+# CONFIG_FB_MATROX is not set -+# CONFIG_FB_RADEON is not set -+# CONFIG_FB_ATY128 is not set -+# CONFIG_FB_ATY is not set -+# CONFIG_FB_S3 is not set -+# CONFIG_FB_SAVAGE is not set -+# CONFIG_FB_SIS is not set -+# CONFIG_FB_NEOMAGIC is not set -+# CONFIG_FB_KYRO is not set -+# CONFIG_FB_3DFX is not set -+# CONFIG_FB_VOODOO1 is not set -+# CONFIG_FB_VT8623 is not set -+# CONFIG_FB_TRIDENT is not set -+# CONFIG_FB_ARK is not set -+# CONFIG_FB_PM3 is not set -+# CONFIG_FB_CARMINE is not set -+# CONFIG_FB_SMSCUFX is not set -+CONFIG_FB_UDL=m -+# CONFIG_FB_VIRTUAL is not set -+# CONFIG_FB_METRONOME is not set -+# CONFIG_FB_MB862XX is not set -+# CONFIG_FB_BROADSHEET is not set -+# CONFIG_FB_AUO_K190X is not set -+# CONFIG_FB_MXS is not set -+# CONFIG_FB_SIMPLE is not set -+# CONFIG_FB_SSD1307 is not set -+CONFIG_FB_MXC=y -+CONFIG_FB_MXC_SYNC_PANEL=y -+CONFIG_FB_MXC_LDB=y -+CONFIG_FB_MXC_MIPI_DSI=y -+CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y -+CONFIG_FB_MXC_HDMI=y -+CONFIG_FB_MXC_DCIC=y -+CONFIG_FB_MXC_EDID=y -+CONFIG_BACKLIGHT_LCD_SUPPORT=y -+CONFIG_LCD_CLASS_DEVICE=y -+CONFIG_LCD_L4F00242T03=m -+CONFIG_LCD_LMS283GF05=m -+CONFIG_LCD_LTV350QV=m -+CONFIG_LCD_ILI922X=m -+CONFIG_LCD_ILI9320=m -+CONFIG_LCD_TDO24M=m -+CONFIG_LCD_VGG2432A4=m -+CONFIG_LCD_PLATFORM=y -+CONFIG_LCD_S6E63M0=m -+CONFIG_LCD_LD9040=m -+CONFIG_LCD_AMS369FG06=m -+CONFIG_LCD_LMS501KF03=m -+CONFIG_LCD_HX8357=m -+CONFIG_BACKLIGHT_CLASS_DEVICE=y -+CONFIG_BACKLIGHT_GENERIC=y -+CONFIG_BACKLIGHT_PWM=y -+CONFIG_BACKLIGHT_DA9052=m -+CONFIG_BACKLIGHT_ADP8860=m -+CONFIG_BACKLIGHT_ADP8870=m -+CONFIG_BACKLIGHT_LM3630A=m -+CONFIG_BACKLIGHT_LM3639=m -+CONFIG_BACKLIGHT_LP855X=m -+CONFIG_BACKLIGHT_GPIO=m -+CONFIG_BACKLIGHT_LV5207LP=m -+CONFIG_BACKLIGHT_BD6107=m -+# CONFIG_VGASTATE is not set -+CONFIG_VIDEOMODE_HELPERS=y -+CONFIG_HDMI=y -+ -+# -+# Console display driver support -+# -+CONFIG_DUMMY_CONSOLE=y -+CONFIG_FRAMEBUFFER_CONSOLE=y -+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set -+# CONFIG_LOGO is not set -+CONFIG_SOUND=y -+CONFIG_SOUND_OSS_CORE=y -+# CONFIG_SOUND_OSS_CORE_PRECLAIM is not set -+CONFIG_SND=y -+CONFIG_SND_TIMER=y -+CONFIG_SND_PCM=y -+CONFIG_SND_DMAENGINE_PCM=y -+CONFIG_SND_HWDEP=m -+CONFIG_SND_RAWMIDI=m -+CONFIG_SND_COMPRESS_OFFLOAD=y -+CONFIG_SND_JACK=y -+# CONFIG_SND_SEQUENCER is not set -+CONFIG_SND_OSSEMUL=y -+CONFIG_SND_MIXER_OSS=m -+# CONFIG_SND_PCM_OSS is not set -+CONFIG_SND_HRTIMER=y -+# CONFIG_SND_DYNAMIC_MINORS is not set -+# CONFIG_SND_SUPPORT_OLD_API is not set -+# CONFIG_SND_VERBOSE_PROCFS is not set -+# CONFIG_SND_VERBOSE_PRINTK is not set -+# CONFIG_SND_DEBUG is not set -+CONFIG_SND_VMASTER=y -+# CONFIG_SND_RAWMIDI_SEQ is not set -+# CONFIG_SND_OPL3_LIB_SEQ is not set -+# CONFIG_SND_OPL4_LIB_SEQ is not set -+# CONFIG_SND_SBAWE_SEQ is not set -+# CONFIG_SND_EMU10K1_SEQ is not set -+CONFIG_SND_MPU401_UART=m -+CONFIG_SND_AC97_CODEC=m -+CONFIG_SND_DRIVERS=y -+CONFIG_SND_DUMMY=m -+CONFIG_SND_ALOOP=m -+CONFIG_SND_MTPAV=m -+CONFIG_SND_SERIAL_U16550=m -+CONFIG_SND_MPU401=m -+# CONFIG_SND_AC97_POWER_SAVE is not set -+# CONFIG_SND_PCI is not set -+ -+# -+# HD-Audio -+# -+CONFIG_SND_ARM=y -+CONFIG_SND_SPI=y -+CONFIG_SND_USB=y -+CONFIG_SND_USB_AUDIO=m -+CONFIG_SND_USB_UA101=m -+CONFIG_SND_USB_CAIAQ=m -+CONFIG_SND_USB_CAIAQ_INPUT=y -+CONFIG_SND_USB_6FIRE=m -+CONFIG_SND_USB_HIFACE=m -+CONFIG_SND_BCD2000=m -+# CONFIG_SND_USB_POD is not set -+# CONFIG_SND_USB_PODHD is not set -+# CONFIG_SND_USB_TONEPORT is not set -+# CONFIG_SND_USB_VARIAX is not set -+CONFIG_SND_SOC=y -+CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y -+# CONFIG_SND_ATMEL_SOC is not set -+# CONFIG_SND_DESIGNWARE_I2S is not set -+ -+# -+# SoC Audio for Freescale CPUs -+# -+ -+# -+# Common SoC Audio options for Freescale CPUs: -+# -+# CONFIG_SND_SOC_FSL_ASRC is not set -+CONFIG_SND_SOC_FSL_SAI=y -+CONFIG_SND_SOC_FSL_SSI=y -+CONFIG_SND_SOC_FSL_SPDIF=y -+CONFIG_SND_SOC_FSL_ESAI=y -+CONFIG_SND_SOC_FSL_HDMI=y -+CONFIG_SND_SOC_FSL_UTILS=y -+CONFIG_SND_SOC_IMX_PCM_DMA=y -+CONFIG_SND_SOC_IMX_HDMI_DMA=y -+CONFIG_SND_SOC_IMX_AUDMUX=y -+CONFIG_SND_IMX_SOC=y -+ -+# -+# SoC Audio support for Freescale i.MX boards: -+# -+# CONFIG_SND_SOC_EUKREA_TLV320 is not set -+# CONFIG_SND_SOC_IMX_WM8962 is not set -+# CONFIG_SND_SOC_IMX_ES8328 is not set -+CONFIG_SND_SOC_IMX_SGTL5000=y -+CONFIG_SND_SOC_IMX_SPDIF=y -+# CONFIG_SND_SOC_IMX_MC13783 is not set -+CONFIG_SND_SOC_IMX_HDMI=y -+CONFIG_SND_SOC_FSL_ASOC_CARD=m -+# CONFIG_SND_SOC_QCOM is not set -+# CONFIG_SND_SOC_XTFPGA_I2S is not set -+CONFIG_SND_SOC_I2C_AND_SPI=y -+ -+# -+# CODEC drivers -+# -+# CONFIG_SND_SOC_ADAU1701 is not set -+# CONFIG_SND_SOC_AK4104 is not set -+# CONFIG_SND_SOC_AK4554 is not set -+# CONFIG_SND_SOC_AK4642 is not set -+# CONFIG_SND_SOC_AK5386 is not set -+# CONFIG_SND_SOC_ALC5623 is not set -+# CONFIG_SND_SOC_CS35L32 is not set -+# CONFIG_SND_SOC_CS42L51_I2C is not set -+# CONFIG_SND_SOC_CS42L52 is not set -+# CONFIG_SND_SOC_CS42L56 is not set -+# CONFIG_SND_SOC_CS42L73 is not set -+# CONFIG_SND_SOC_CS4265 is not set -+# CONFIG_SND_SOC_CS4270 is not set -+# CONFIG_SND_SOC_CS4271_I2C is not set -+# CONFIG_SND_SOC_CS4271_SPI is not set -+# CONFIG_SND_SOC_CS42XX8_I2C is not set -+CONFIG_SND_SOC_HDMI_CODEC=y -+# CONFIG_SND_SOC_ES8328 is not set -+# CONFIG_SND_SOC_PCM1681 is not set -+# CONFIG_SND_SOC_PCM1792A is not set -+# CONFIG_SND_SOC_PCM512x_I2C is not set -+# CONFIG_SND_SOC_PCM512x_SPI is not set -+# CONFIG_SND_SOC_RT5631 is not set -+# CONFIG_SND_SOC_RT5677_SPI is not set -+CONFIG_SND_SOC_SGTL5000=y -+CONFIG_SND_SOC_SI476X=m -+# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set -+CONFIG_SND_SOC_SPDIF=y -+# CONFIG_SND_SOC_SSM2602_SPI is not set -+# CONFIG_SND_SOC_SSM2602_I2C is not set -+# CONFIG_SND_SOC_SSM4567 is not set -+# CONFIG_SND_SOC_STA32X is not set -+# CONFIG_SND_SOC_STA350 is not set -+# CONFIG_SND_SOC_TAS2552 is not set -+# CONFIG_SND_SOC_TAS5086 is not set -+# CONFIG_SND_SOC_TFA9879 is not set -+# CONFIG_SND_SOC_TLV320AIC23_I2C is not set -+# CONFIG_SND_SOC_TLV320AIC23_SPI is not set -+# CONFIG_SND_SOC_TLV320AIC31XX is not set -+# CONFIG_SND_SOC_TLV320AIC3X is not set -+# CONFIG_SND_SOC_TS3A227E is not set -+# CONFIG_SND_SOC_WM8510 is not set -+# CONFIG_SND_SOC_WM8523 is not set -+# CONFIG_SND_SOC_WM8580 is not set -+# CONFIG_SND_SOC_WM8711 is not set -+# CONFIG_SND_SOC_WM8728 is not set -+# CONFIG_SND_SOC_WM8731 is not set -+# CONFIG_SND_SOC_WM8737 is not set -+# CONFIG_SND_SOC_WM8741 is not set -+# CONFIG_SND_SOC_WM8750 is not set -+# CONFIG_SND_SOC_WM8753 is not set -+# CONFIG_SND_SOC_WM8770 is not set -+# CONFIG_SND_SOC_WM8776 is not set -+# CONFIG_SND_SOC_WM8804_I2C is not set -+# CONFIG_SND_SOC_WM8804_SPI is not set -+# CONFIG_SND_SOC_WM8903 is not set -+# CONFIG_SND_SOC_WM8962 is not set -+# CONFIG_SND_SOC_WM8978 is not set -+# CONFIG_SND_SOC_TPA6130A2 is not set -+# CONFIG_SND_SIMPLE_CARD is not set -+# CONFIG_SOUND_PRIME is not set -+CONFIG_AC97_BUS=m -+ -+# -+# HID support -+# -+CONFIG_HID=y -+CONFIG_HID_BATTERY_STRENGTH=y -+CONFIG_HIDRAW=y -+CONFIG_UHID=m -+CONFIG_HID_GENERIC=y -+ -+# -+# Special HID drivers -+# -+CONFIG_HID_A4TECH=m -+CONFIG_HID_ACRUX=m -+CONFIG_HID_ACRUX_FF=y -+CONFIG_HID_APPLE=m -+CONFIG_HID_APPLEIR=m -+CONFIG_HID_AUREAL=m -+CONFIG_HID_BELKIN=m -+# CONFIG_HID_BETOP_FF is not set -+CONFIG_HID_CHERRY=m -+CONFIG_HID_CHICONY=m -+CONFIG_HID_PRODIKEYS=m -+CONFIG_HID_CP2112=m -+CONFIG_HID_CYPRESS=m -+CONFIG_HID_DRAGONRISE=m -+CONFIG_DRAGONRISE_FF=y -+CONFIG_HID_EMS_FF=m -+CONFIG_HID_ELECOM=m -+CONFIG_HID_ELO=m -+CONFIG_HID_EZKEY=m -+CONFIG_HID_HOLTEK=m -+CONFIG_HOLTEK_FF=y -+CONFIG_HID_GT683R=m -+CONFIG_HID_KEYTOUCH=m -+CONFIG_HID_KYE=m -+CONFIG_HID_UCLOGIC=m -+CONFIG_HID_WALTOP=m -+CONFIG_HID_GYRATION=m -+CONFIG_HID_ICADE=m -+CONFIG_HID_TWINHAN=m -+CONFIG_HID_KENSINGTON=m -+CONFIG_HID_LCPOWER=m -+CONFIG_HID_LENOVO=m -+CONFIG_HID_LOGITECH=m -+CONFIG_HID_LOGITECH_DJ=m -+CONFIG_HID_LOGITECH_HIDPP=m -+CONFIG_LOGITECH_FF=y -+CONFIG_LOGIRUMBLEPAD2_FF=y -+CONFIG_LOGIG940_FF=y -+CONFIG_LOGIWHEELS_FF=y -+CONFIG_HID_MAGICMOUSE=m -+CONFIG_HID_MICROSOFT=m -+CONFIG_HID_MONTEREY=m -+CONFIG_HID_MULTITOUCH=m -+CONFIG_HID_NTRIG=m -+CONFIG_HID_ORTEK=m -+CONFIG_HID_PANTHERLORD=m -+CONFIG_PANTHERLORD_FF=y -+CONFIG_HID_PENMOUNT=m -+CONFIG_HID_PETALYNX=m -+CONFIG_HID_PICOLCD=m -+CONFIG_HID_PICOLCD_FB=y -+CONFIG_HID_PICOLCD_BACKLIGHT=y -+CONFIG_HID_PICOLCD_LCD=y -+CONFIG_HID_PICOLCD_LEDS=y -+CONFIG_HID_PICOLCD_CIR=y -+CONFIG_HID_PLANTRONICS=m -+CONFIG_HID_PRIMAX=m -+CONFIG_HID_ROCCAT=m -+CONFIG_HID_SAITEK=m -+CONFIG_HID_SAMSUNG=m -+CONFIG_HID_SONY=m -+CONFIG_SONY_FF=y -+CONFIG_HID_SPEEDLINK=m -+CONFIG_HID_STEELSERIES=m -+CONFIG_HID_SUNPLUS=m -+CONFIG_HID_RMI=m -+CONFIG_HID_GREENASIA=m -+CONFIG_GREENASIA_FF=y -+CONFIG_HID_SMARTJOYPLUS=m -+CONFIG_SMARTJOYPLUS_FF=y -+CONFIG_HID_TIVO=m -+CONFIG_HID_TOPSEED=m -+CONFIG_HID_THINGM=m -+CONFIG_HID_THRUSTMASTER=m -+CONFIG_THRUSTMASTER_FF=y -+CONFIG_HID_WACOM=m -+CONFIG_HID_WIIMOTE=m -+CONFIG_HID_XINMO=m -+CONFIG_HID_ZEROPLUS=m -+CONFIG_ZEROPLUS_FF=y -+CONFIG_HID_ZYDACRON=m -+CONFIG_HID_SENSOR_HUB=m -+# CONFIG_HID_SENSOR_CUSTOM_SENSOR is not set -+ -+# -+# USB HID support -+# -+CONFIG_USB_HID=y -+CONFIG_HID_PID=y -+CONFIG_USB_HIDDEV=y -+ -+# -+# I2C HID support -+# -+CONFIG_I2C_HID=m -+CONFIG_USB_OHCI_LITTLE_ENDIAN=y -+CONFIG_USB_SUPPORT=y -+CONFIG_USB_COMMON=y -+CONFIG_USB_ARCH_HAS_HCD=y -+CONFIG_USB=y -+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set -+ -+# -+# Miscellaneous USB options -+# -+CONFIG_USB_DEFAULT_PERSIST=y -+# CONFIG_USB_DYNAMIC_MINORS is not set -+CONFIG_USB_OTG=y -+# CONFIG_USB_OTG_WHITELIST is not set -+# CONFIG_USB_OTG_BLACKLIST_HUB is not set -+CONFIG_USB_OTG_FSM=y -+# CONFIG_USB_MON is not set -+# CONFIG_USB_WUSB_CBAF is not set -+ -+# -+# USB Host Controller Drivers -+# -+# CONFIG_USB_C67X00_HCD is not set -+# CONFIG_USB_XHCI_HCD is not set -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_ROOT_HUB_TT=y -+CONFIG_USB_EHCI_TT_NEWSCHED=y -+CONFIG_USB_FSL_MPH_DR_OF=m -+CONFIG_USB_EHCI_PCI=y -+# CONFIG_USB_EHCI_MXC is not set -+CONFIG_USB_EHCI_HCD_PLATFORM=y -+# CONFIG_USB_OXU210HP_HCD is not set -+# CONFIG_USB_ISP116X_HCD is not set -+# CONFIG_USB_ISP1362_HCD is not set -+# CONFIG_USB_FUSBH200_HCD is not set -+# CONFIG_USB_FOTG210_HCD is not set -+# CONFIG_USB_MAX3421_HCD is not set -+# CONFIG_USB_OHCI_HCD is not set -+# CONFIG_USB_UHCI_HCD is not set -+# CONFIG_USB_SL811_HCD is not set -+# CONFIG_USB_R8A66597_HCD is not set -+# CONFIG_USB_IMX21_HCD is not set -+# CONFIG_USB_HCD_BCMA is not set -+# CONFIG_USB_HCD_SSB is not set -+# CONFIG_USB_HCD_TEST_MODE is not set -+ -+# -+# USB Device Class drivers -+# -+CONFIG_USB_ACM=m -+CONFIG_USB_PRINTER=m -+CONFIG_USB_WDM=m -+# CONFIG_USB_TMC is not set -+ -+# -+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -+# -+ -+# -+# also be needed; see USB_STORAGE Help for more info -+# -+CONFIG_USB_STORAGE=y -+# CONFIG_USB_STORAGE_DEBUG is not set -+CONFIG_USB_STORAGE_REALTEK=y -+CONFIG_REALTEK_AUTOPM=y -+CONFIG_USB_STORAGE_DATAFAB=y -+CONFIG_USB_STORAGE_FREECOM=y -+CONFIG_USB_STORAGE_ISD200=y -+CONFIG_USB_STORAGE_USBAT=y -+CONFIG_USB_STORAGE_SDDR09=y -+CONFIG_USB_STORAGE_SDDR55=y -+CONFIG_USB_STORAGE_JUMPSHOT=y -+CONFIG_USB_STORAGE_ALAUDA=y -+CONFIG_USB_STORAGE_ONETOUCH=y -+CONFIG_USB_STORAGE_KARMA=y -+CONFIG_USB_STORAGE_CYPRESS_ATACB=y -+CONFIG_USB_STORAGE_ENE_UB6250=y -+CONFIG_USB_UAS=y -+ -+# -+# USB Imaging devices -+# -+# CONFIG_USB_MDC800 is not set -+# CONFIG_USB_MICROTEK is not set -+CONFIG_USBIP_CORE=m -+CONFIG_USBIP_VHCI_HCD=m -+CONFIG_USBIP_HOST=m -+# CONFIG_USBIP_DEBUG is not set -+CONFIG_USB_MUSB_HDRC=m -+CONFIG_USB_MUSB_HOST=y -+# CONFIG_USB_MUSB_GADGET is not set -+# CONFIG_USB_MUSB_DUAL_ROLE is not set -+ -+# -+# Platform Glue Layer -+# -+CONFIG_MUSB_PIO_ONLY=y -+CONFIG_USB_DWC3=m -+CONFIG_USB_DWC3_HOST=y -+# CONFIG_USB_DWC3_GADGET is not set -+# CONFIG_USB_DWC3_DUAL_ROLE is not set -+ -+# -+# Platform Glue Driver Support -+# -+CONFIG_USB_DWC3_PCI=m -+ -+# -+# Debugging features -+# -+# CONFIG_USB_DWC3_DEBUG is not set -+CONFIG_USB_DWC2=m -+CONFIG_USB_DWC2_HOST=y -+ -+# -+# Gadget/Dual-role mode requires USB Gadget support to be enabled -+# -+# CONFIG_USB_DWC2_PERIPHERAL is not set -+# CONFIG_USB_DWC2_DUAL_ROLE is not set -+CONFIG_USB_DWC2_PLATFORM=m -+CONFIG_USB_DWC2_PCI=m -+# CONFIG_USB_DWC2_DEBUG is not set -+# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set -+CONFIG_USB_CHIPIDEA=y -+CONFIG_USB_CHIPIDEA_OF=y -+CONFIG_USB_CHIPIDEA_PCI=y -+# CONFIG_USB_CHIPIDEA_UDC is not set -+CONFIG_USB_CHIPIDEA_HOST=y -+# CONFIG_USB_CHIPIDEA_DEBUG is not set -+# CONFIG_USB_ISP1760 is not set -+ -+# -+# USB port drivers -+# -+CONFIG_USB_SERIAL=y -+# CONFIG_USB_SERIAL_CONSOLE is not set -+# CONFIG_USB_SERIAL_GENERIC is not set -+# CONFIG_USB_SERIAL_SIMPLE is not set -+# CONFIG_USB_SERIAL_AIRCABLE is not set -+# CONFIG_USB_SERIAL_ARK3116 is not set -+# CONFIG_USB_SERIAL_BELKIN is not set -+# CONFIG_USB_SERIAL_CH341 is not set -+# CONFIG_USB_SERIAL_WHITEHEAT is not set -+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set -+# CONFIG_USB_SERIAL_CP210X is not set -+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set -+# CONFIG_USB_SERIAL_EMPEG is not set -+# CONFIG_USB_SERIAL_FTDI_SIO is not set -+# CONFIG_USB_SERIAL_VISOR is not set -+# CONFIG_USB_SERIAL_IPAQ is not set -+# CONFIG_USB_SERIAL_IR is not set -+# CONFIG_USB_SERIAL_EDGEPORT is not set -+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set -+# CONFIG_USB_SERIAL_F81232 is not set -+# CONFIG_USB_SERIAL_GARMIN is not set -+# CONFIG_USB_SERIAL_IPW is not set -+# CONFIG_USB_SERIAL_IUU is not set -+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set -+# CONFIG_USB_SERIAL_KEYSPAN is not set -+# CONFIG_USB_SERIAL_KLSI is not set -+# CONFIG_USB_SERIAL_KOBIL_SCT is not set -+# CONFIG_USB_SERIAL_MCT_U232 is not set -+# CONFIG_USB_SERIAL_METRO is not set -+# CONFIG_USB_SERIAL_MOS7720 is not set -+# CONFIG_USB_SERIAL_MOS7840 is not set -+# CONFIG_USB_SERIAL_MXUPORT is not set -+# CONFIG_USB_SERIAL_NAVMAN is not set -+# CONFIG_USB_SERIAL_PL2303 is not set -+# CONFIG_USB_SERIAL_OTI6858 is not set -+# CONFIG_USB_SERIAL_QCAUX is not set -+# CONFIG_USB_SERIAL_QUALCOMM is not set -+# CONFIG_USB_SERIAL_SPCP8X5 is not set -+# CONFIG_USB_SERIAL_SAFE is not set -+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set -+# CONFIG_USB_SERIAL_SYMBOL is not set -+# CONFIG_USB_SERIAL_TI is not set -+# CONFIG_USB_SERIAL_CYBERJACK is not set -+# CONFIG_USB_SERIAL_XIRCOM is not set -+# CONFIG_USB_SERIAL_OPTION is not set -+# CONFIG_USB_SERIAL_OMNINET is not set -+# CONFIG_USB_SERIAL_OPTICON is not set -+# CONFIG_USB_SERIAL_XSENS_MT is not set -+# CONFIG_USB_SERIAL_WISHBONE is not set -+# CONFIG_USB_SERIAL_SSU100 is not set -+# CONFIG_USB_SERIAL_QT2 is not set -+# CONFIG_USB_SERIAL_DEBUG is not set -+ -+# -+# USB Miscellaneous drivers -+# -+CONFIG_USB_EMI62=m -+CONFIG_USB_EMI26=m -+# CONFIG_USB_ADUTUX is not set -+CONFIG_USB_SEVSEG=m -+CONFIG_USB_RIO500=m -+CONFIG_USB_LEGOTOWER=m -+CONFIG_USB_LCD=m -+CONFIG_USB_LED=m -+CONFIG_USB_CYPRESS_CY7C63=m -+CONFIG_USB_CYTHERM=m -+# CONFIG_USB_IDMOUSE is not set -+# CONFIG_USB_FTDI_ELAN is not set -+CONFIG_USB_APPLEDISPLAY=m -+CONFIG_USB_SISUSBVGA=m -+CONFIG_USB_SISUSBVGA_CON=y -+CONFIG_USB_LD=m -+CONFIG_USB_TRANCEVIBRATOR=m -+# CONFIG_USB_IOWARRIOR is not set -+# CONFIG_USB_TEST is not set -+# CONFIG_USB_EHSET_TEST_FIXTURE is not set -+CONFIG_USB_ISIGHTFW=m -+# CONFIG_USB_YUREX is not set -+# CONFIG_USB_EZUSB_FX2 is not set -+# CONFIG_USB_HSIC_USB3503 is not set -+# CONFIG_USB_LINK_LAYER_TEST is not set -+# CONFIG_USB_CHAOSKEY is not set -+ -+# -+# USB Physical Layer drivers -+# -+CONFIG_USB_PHY=y -+CONFIG_NOP_USB_XCEIV=y -+CONFIG_AM335X_CONTROL_USB=m -+CONFIG_AM335X_PHY_USB=m -+CONFIG_USB_GPIO_VBUS=m -+CONFIG_USB_ISP1301=m -+CONFIG_USB_MXS_PHY=y -+# CONFIG_USB_ULPI is not set -+CONFIG_USB_GADGET=y -+# CONFIG_USB_GADGET_DEBUG is not set -+# CONFIG_USB_GADGET_DEBUG_FILES is not set -+# CONFIG_USB_GADGET_DEBUG_FS is not set -+CONFIG_USB_GADGET_VBUS_DRAW=2 -+CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 -+ -+# -+# USB Peripheral Controller -+# -+CONFIG_USB_FSL_USB2=m -+# CONFIG_USB_FUSB300 is not set -+# CONFIG_USB_FOTG210_UDC is not set -+# CONFIG_USB_GR_UDC is not set -+# CONFIG_USB_R8A66597 is not set -+# CONFIG_USB_PXA27X is not set -+# CONFIG_USB_MV_UDC is not set -+# CONFIG_USB_MV_U3D is not set -+# CONFIG_USB_M66592 is not set -+# CONFIG_USB_BDC_UDC is not set -+# CONFIG_USB_AMD5536UDC is not set -+# CONFIG_USB_NET2272 is not set -+# CONFIG_USB_NET2280 is not set -+# CONFIG_USB_GOKU is not set -+# CONFIG_USB_EG20T is not set -+# CONFIG_USB_GADGET_XILINX is not set -+# CONFIG_USB_DUMMY_HCD is not set -+CONFIG_USB_LIBCOMPOSITE=m -+CONFIG_USB_F_ACM=m -+CONFIG_USB_F_SS_LB=m -+CONFIG_USB_U_SERIAL=m -+CONFIG_USB_U_ETHER=m -+CONFIG_USB_F_SERIAL=m -+CONFIG_USB_F_OBEX=m -+CONFIG_USB_F_NCM=m -+CONFIG_USB_F_ECM=m -+CONFIG_USB_F_EEM=m -+CONFIG_USB_F_SUBSET=m -+CONFIG_USB_F_RNDIS=m -+CONFIG_USB_F_MASS_STORAGE=m -+CONFIG_USB_F_FS=m -+CONFIG_USB_F_UAC1=m -+CONFIG_USB_F_UAC2=m -+CONFIG_USB_F_UVC=m -+CONFIG_USB_F_MIDI=m -+CONFIG_USB_F_HID=m -+CONFIG_USB_F_PRINTER=m -+CONFIG_USB_CONFIGFS=m -+CONFIG_USB_CONFIGFS_SERIAL=y -+CONFIG_USB_CONFIGFS_ACM=y -+CONFIG_USB_CONFIGFS_OBEX=y -+CONFIG_USB_CONFIGFS_NCM=y -+CONFIG_USB_CONFIGFS_ECM=y -+CONFIG_USB_CONFIGFS_ECM_SUBSET=y -+CONFIG_USB_CONFIGFS_RNDIS=y -+CONFIG_USB_CONFIGFS_EEM=y -+CONFIG_USB_CONFIGFS_MASS_STORAGE=y -+CONFIG_USB_CONFIGFS_F_LB_SS=y -+CONFIG_USB_CONFIGFS_F_FS=y -+CONFIG_USB_CONFIGFS_F_UAC1=y -+CONFIG_USB_CONFIGFS_F_UAC2=y -+CONFIG_USB_CONFIGFS_F_MIDI=y -+CONFIG_USB_CONFIGFS_F_HID=y -+# CONFIG_USB_CONFIGFS_F_UVC is not set -+# CONFIG_USB_CONFIGFS_F_PRINTER is not set -+CONFIG_USB_ZERO=m -+CONFIG_USB_ZERO_HNPTEST=y -+# CONFIG_USB_AUDIO is not set -+CONFIG_USB_ETH=m -+CONFIG_USB_ETH_RNDIS=y -+CONFIG_USB_ETH_EEM=y -+CONFIG_USB_G_NCM=m -+CONFIG_USB_GADGETFS=m -+CONFIG_USB_FUNCTIONFS=m -+CONFIG_USB_FUNCTIONFS_ETH=y -+CONFIG_USB_FUNCTIONFS_RNDIS=y -+CONFIG_USB_FUNCTIONFS_GENERIC=y -+CONFIG_USB_MASS_STORAGE=m -+CONFIG_USB_G_SERIAL=m -+CONFIG_USB_MIDI_GADGET=m -+CONFIG_USB_G_PRINTER=m -+CONFIG_USB_CDC_COMPOSITE=m -+CONFIG_USB_G_ACM_MS=m -+CONFIG_USB_G_MULTI=m -+CONFIG_USB_G_MULTI_RNDIS=y -+CONFIG_USB_G_MULTI_CDC=y -+# CONFIG_USB_G_HID is not set -+CONFIG_USB_G_DBGP=m -+# CONFIG_USB_G_DBGP_PRINTK is not set -+CONFIG_USB_G_DBGP_SERIAL=y -+CONFIG_USB_G_WEBCAM=m -+CONFIG_USB_LED_TRIG=y -+# CONFIG_UWB is not set -+CONFIG_MMC=y -+# CONFIG_MMC_DEBUG is not set -+# CONFIG_MMC_CLKGATE is not set -+ -+# -+# MMC/SD/SDIO Card Drivers -+# -+CONFIG_MMC_BLOCK=y -+CONFIG_MMC_BLOCK_MINORS=8 -+CONFIG_MMC_BLOCK_BOUNCE=y -+CONFIG_SDIO_UART=m -+# CONFIG_MMC_TEST is not set -+ -+# -+# MMC/SD/SDIO Host Controller Drivers -+# -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_IO_ACCESSORS=y -+# CONFIG_MMC_SDHCI_PCI is not set -+CONFIG_MMC_SDHCI_PLTFM=y -+CONFIG_MMC_SDHCI_OF_ARASAN=m -+CONFIG_MMC_SDHCI_ESDHC_IMX=y -+# CONFIG_MMC_SDHCI_F_SDH30 is not set -+CONFIG_MMC_MXC=y -+CONFIG_MMC_TIFM_SD=m -+CONFIG_MMC_CB710=m -+# CONFIG_MMC_VIA_SDMMC is not set -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_IDMAC=y -+CONFIG_MMC_DW_PLTFM=y -+CONFIG_MMC_DW_EXYNOS=y -+# CONFIG_MMC_DW_K3 is not set -+# CONFIG_MMC_DW_PCI is not set -+CONFIG_MMC_VUB300=m -+CONFIG_MMC_USHC=y -+CONFIG_MMC_USDHI6ROL0=m -+CONFIG_MMC_TOSHIBA_PCI=m -+# CONFIG_MEMSTICK is not set -+CONFIG_NEW_LEDS=y -+CONFIG_LEDS_CLASS=m -+# CONFIG_LEDS_CLASS_FLASH is not set -+ -+# -+# LED drivers -+# -+# CONFIG_LEDS_LM3530 is not set -+# CONFIG_LEDS_LM3642 is not set -+# CONFIG_LEDS_PCA9532 is not set -+CONFIG_LEDS_GPIO=m -+# CONFIG_LEDS_LP3944 is not set -+# CONFIG_LEDS_LP5521 is not set -+# CONFIG_LEDS_LP5523 is not set -+# CONFIG_LEDS_LP5562 is not set -+# CONFIG_LEDS_LP8501 is not set -+# CONFIG_LEDS_LP8860 is not set -+# CONFIG_LEDS_PCA955X is not set -+# CONFIG_LEDS_PCA963X is not set -+# CONFIG_LEDS_DA9052 is not set -+# CONFIG_LEDS_DAC124S085 is not set -+CONFIG_LEDS_PWM=m -+CONFIG_LEDS_REGULATOR=m -+# CONFIG_LEDS_BD2802 is not set -+# CONFIG_LEDS_LT3593 is not set -+# CONFIG_LEDS_MC13783 is not set -+# CONFIG_LEDS_TCA6507 is not set -+# CONFIG_LEDS_LM355x is not set -+ -+# -+# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) -+# -+# CONFIG_LEDS_BLINKM is not set -+# CONFIG_LEDS_PM8941_WLED is not set -+ -+# -+# LED Triggers -+# -+CONFIG_LEDS_TRIGGERS=y -+CONFIG_LEDS_TRIGGER_TIMER=m -+CONFIG_LEDS_TRIGGER_ONESHOT=m -+CONFIG_LEDS_TRIGGER_HEARTBEAT=y -+CONFIG_LEDS_TRIGGER_BACKLIGHT=m -+CONFIG_LEDS_TRIGGER_CPU=y -+CONFIG_LEDS_TRIGGER_GPIO=m -+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y -+ -+# -+# iptables trigger is under Netfilter config (LED target) -+# -+CONFIG_LEDS_TRIGGER_TRANSIENT=m -+CONFIG_LEDS_TRIGGER_CAMERA=m -+# CONFIG_ACCESSIBILITY is not set -+# CONFIG_INFINIBAND is not set -+# CONFIG_EDAC is not set -+CONFIG_RTC_LIB=y -+CONFIG_RTC_CLASS=y -+CONFIG_RTC_HCTOSYS=y -+# CONFIG_RTC_SYSTOHC is not set -+CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -+# CONFIG_RTC_DEBUG is not set -+ -+# -+# RTC interfaces -+# -+CONFIG_RTC_INTF_SYSFS=y -+CONFIG_RTC_INTF_PROC=y -+CONFIG_RTC_INTF_DEV=y -+CONFIG_RTC_INTF_DEV_UIE_EMUL=y -+# CONFIG_RTC_DRV_TEST is not set -+ -+# -+# I2C RTC drivers -+# -+# CONFIG_RTC_DRV_ABB5ZES3 is not set -+# CONFIG_RTC_DRV_ABX80X is not set -+# CONFIG_RTC_DRV_DS1307 is not set -+# CONFIG_RTC_DRV_DS1374 is not set -+# CONFIG_RTC_DRV_DS1672 is not set -+# CONFIG_RTC_DRV_DS3232 is not set -+# CONFIG_RTC_DRV_HYM8563 is not set -+# CONFIG_RTC_DRV_MAX6900 is not set -+# CONFIG_RTC_DRV_RS5C372 is not set -+# CONFIG_RTC_DRV_ISL1208 is not set -+# CONFIG_RTC_DRV_ISL12022 is not set -+# CONFIG_RTC_DRV_ISL12057 is not set -+# CONFIG_RTC_DRV_X1205 is not set -+# CONFIG_RTC_DRV_PCF2127 is not set -+CONFIG_RTC_DRV_PCF8523=y -+# CONFIG_RTC_DRV_PCF8563 is not set -+# CONFIG_RTC_DRV_PCF85063 is not set -+# CONFIG_RTC_DRV_PCF8583 is not set -+# CONFIG_RTC_DRV_M41T80 is not set -+# CONFIG_RTC_DRV_BQ32K is not set -+# CONFIG_RTC_DRV_S35390A is not set -+# CONFIG_RTC_DRV_FM3130 is not set -+# CONFIG_RTC_DRV_RX8581 is not set -+# CONFIG_RTC_DRV_RX8025 is not set -+# CONFIG_RTC_DRV_EM3027 is not set -+# CONFIG_RTC_DRV_RV3029C2 is not set -+ -+# -+# SPI RTC drivers -+# -+# CONFIG_RTC_DRV_M41T93 is not set -+# CONFIG_RTC_DRV_M41T94 is not set -+# CONFIG_RTC_DRV_DS1305 is not set -+# CONFIG_RTC_DRV_DS1343 is not set -+# CONFIG_RTC_DRV_DS1347 is not set -+# CONFIG_RTC_DRV_DS1390 is not set -+# CONFIG_RTC_DRV_MAX6902 is not set -+# CONFIG_RTC_DRV_R9701 is not set -+# CONFIG_RTC_DRV_RS5C348 is not set -+# CONFIG_RTC_DRV_DS3234 is not set -+# CONFIG_RTC_DRV_PCF2123 is not set -+# CONFIG_RTC_DRV_RX4581 is not set -+# CONFIG_RTC_DRV_MCP795 is not set -+ -+# -+# Platform RTC drivers -+# -+# CONFIG_RTC_DRV_CMOS is not set -+# CONFIG_RTC_DRV_DS1286 is not set -+# CONFIG_RTC_DRV_DS1511 is not set -+# CONFIG_RTC_DRV_DS1553 is not set -+# CONFIG_RTC_DRV_DS1685_FAMILY is not set -+# CONFIG_RTC_DRV_DS1742 is not set -+# CONFIG_RTC_DRV_DS2404 is not set -+# CONFIG_RTC_DRV_DA9052 is not set -+# CONFIG_RTC_DRV_STK17TA8 is not set -+# CONFIG_RTC_DRV_M48T86 is not set -+# CONFIG_RTC_DRV_M48T35 is not set -+# CONFIG_RTC_DRV_M48T59 is not set -+# CONFIG_RTC_DRV_MSM6242 is not set -+# CONFIG_RTC_DRV_BQ4802 is not set -+# CONFIG_RTC_DRV_RP5C01 is not set -+# CONFIG_RTC_DRV_V3020 is not set -+ -+# -+# on-CPU RTC drivers -+# -+CONFIG_RTC_DRV_IMXDI=y -+CONFIG_RTC_DRV_MC13XXX=y -+CONFIG_RTC_DRV_MXC=y -+CONFIG_RTC_DRV_SNVS=y -+# CONFIG_RTC_DRV_XGENE is not set -+ -+# -+# HID Sensor RTC drivers -+# -+# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set -+CONFIG_DMADEVICES=y -+# CONFIG_DMADEVICES_DEBUG is not set -+ -+# -+# DMA Devices -+# -+CONFIG_DW_DMAC_CORE=m -+CONFIG_DW_DMAC=m -+CONFIG_DW_DMAC_PCI=m -+# CONFIG_HSU_DMA_PCI is not set -+# CONFIG_MX3_IPU is not set -+CONFIG_IMX_SDMA=y -+# CONFIG_IMX_DMA is not set -+CONFIG_MXS_DMA=y -+CONFIG_FSL_EDMA=m -+# CONFIG_NBPFAXI_DMA is not set -+CONFIG_DMA_ENGINE=y -+CONFIG_DMA_VIRTUAL_CHANNELS=m -+CONFIG_DMA_OF=y -+ -+# -+# DMA Clients -+# -+CONFIG_ASYNC_TX_DMA=y -+# CONFIG_DMATEST is not set -+# CONFIG_AUXDISPLAY is not set -+# CONFIG_UIO is not set -+# CONFIG_VIRT_DRIVERS is not set -+ -+# -+# Virtio drivers -+# -+# CONFIG_VIRTIO_PCI is not set -+# CONFIG_VIRTIO_MMIO is not set -+ -+# -+# Microsoft Hyper-V guest support -+# -+CONFIG_STAGING=y -+CONFIG_PRISM2_USB=m -+CONFIG_COMEDI=m -+# CONFIG_COMEDI_DEBUG is not set -+CONFIG_COMEDI_DEFAULT_BUF_SIZE_KB=2048 -+CONFIG_COMEDI_DEFAULT_BUF_MAXSIZE_KB=20480 -+# CONFIG_COMEDI_MISC_DRIVERS is not set -+# CONFIG_COMEDI_ISA_DRIVERS is not set -+# CONFIG_COMEDI_PCI_DRIVERS is not set -+# CONFIG_COMEDI_USB_DRIVERS is not set -+# CONFIG_COMEDI_8255 is not set -+# CONFIG_COMEDI_KCOMEDILIB is not set -+CONFIG_RTL8192U=m -+CONFIG_RTLLIB=m -+CONFIG_RTLLIB_CRYPTO_CCMP=m -+CONFIG_RTLLIB_CRYPTO_TKIP=m -+CONFIG_RTLLIB_CRYPTO_WEP=m -+CONFIG_RTL8192E=m -+CONFIG_R8712U=m -+CONFIG_R8188EU=m -+CONFIG_88EU_AP_MODE=y -+CONFIG_R8723AU=m -+CONFIG_8723AU_AP_MODE=y -+CONFIG_8723AU_BT_COEXIST=y -+CONFIG_RTS5208=m -+# CONFIG_VT6655 is not set -+# CONFIG_VT6656 is not set -+ -+# -+# IIO staging drivers -+# -+ -+# -+# Accelerometers -+# -+# CONFIG_ADIS16201 is not set -+# CONFIG_ADIS16203 is not set -+# CONFIG_ADIS16204 is not set -+# CONFIG_ADIS16209 is not set -+# CONFIG_ADIS16220 is not set -+# CONFIG_ADIS16240 is not set -+# CONFIG_LIS3L02DQ is not set -+# CONFIG_SCA3000 is not set -+ -+# -+# Analog to digital converters -+# -+# CONFIG_AD7606 is not set -+# CONFIG_AD7780 is not set -+# CONFIG_AD7816 is not set -+# CONFIG_AD7192 is not set -+# CONFIG_AD7280 is not set -+ -+# -+# Analog digital bi-direction converters -+# -+# CONFIG_ADT7316 is not set -+ -+# -+# Capacitance to digital converters -+# -+# CONFIG_AD7150 is not set -+# CONFIG_AD7152 is not set -+# CONFIG_AD7746 is not set -+ -+# -+# Direct Digital Synthesis -+# -+# CONFIG_AD9832 is not set -+# CONFIG_AD9834 is not set -+ -+# -+# Digital gyroscope sensors -+# -+# CONFIG_ADIS16060 is not set -+ -+# -+# Network Analyzer, Impedance Converters -+# -+# CONFIG_AD5933 is not set -+ -+# -+# Light sensors -+# -+# CONFIG_SENSORS_ISL29018 is not set -+# CONFIG_SENSORS_ISL29028 is not set -+# CONFIG_TSL2583 is not set -+# CONFIG_TSL2x7x is not set -+ -+# -+# Magnetometer sensors -+# -+# CONFIG_SENSORS_HMC5843_I2C is not set -+# CONFIG_SENSORS_HMC5843_SPI is not set -+ -+# -+# Active energy metering IC -+# -+# CONFIG_ADE7753 is not set -+# CONFIG_ADE7754 is not set -+# CONFIG_ADE7758 is not set -+# CONFIG_ADE7759 is not set -+# CONFIG_ADE7854 is not set -+ -+# -+# Resolver to digital converters -+# -+# CONFIG_AD2S90 is not set -+# CONFIG_AD2S1200 is not set -+# CONFIG_AD2S1210 is not set -+ -+# -+# Triggers - standalone -+# -+CONFIG_IIO_PERIODIC_RTC_TRIGGER=m -+# CONFIG_IIO_SIMPLE_DUMMY is not set -+# CONFIG_FB_SM7XX is not set -+# CONFIG_FB_SM750 is not set -+# CONFIG_FB_XGI is not set -+CONFIG_FT1000=m -+CONFIG_FT1000_USB=m -+ -+# -+# Speakup console speech -+# -+CONFIG_SPEAKUP=m -+CONFIG_SPEAKUP_SYNTH_ACNTSA=m -+CONFIG_SPEAKUP_SYNTH_APOLLO=m -+CONFIG_SPEAKUP_SYNTH_AUDPTR=m -+CONFIG_SPEAKUP_SYNTH_BNS=m -+CONFIG_SPEAKUP_SYNTH_DECTLK=m -+CONFIG_SPEAKUP_SYNTH_DECEXT=m -+CONFIG_SPEAKUP_SYNTH_LTLK=m -+CONFIG_SPEAKUP_SYNTH_SOFT=m -+CONFIG_SPEAKUP_SYNTH_SPKOUT=m -+CONFIG_SPEAKUP_SYNTH_TXPRT=m -+CONFIG_SPEAKUP_SYNTH_DUMMY=m -+CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4=m -+CONFIG_STAGING_MEDIA=y -+CONFIG_I2C_BCM2048=m -+CONFIG_DVB_CXD2099=m -+CONFIG_VIDEO_DT3155=m -+CONFIG_DT3155_CCIR=y -+CONFIG_DT3155_STREAMING=y -+CONFIG_DVB_MN88472=m -+CONFIG_DVB_MN88473=m -+CONFIG_LIRC_STAGING=y -+CONFIG_LIRC_BT829=m -+CONFIG_LIRC_IMON=m -+CONFIG_LIRC_SASEM=m -+CONFIG_LIRC_SERIAL=m -+CONFIG_LIRC_SERIAL_TRANSMITTER=y -+CONFIG_LIRC_SIR=m -+CONFIG_LIRC_ZILOG=m -+ -+# -+# Android -+# -+CONFIG_USB_WPAN_HCD=m -+CONFIG_WIMAX_GDM72XX=m -+CONFIG_WIMAX_GDM72XX_QOS=y -+CONFIG_WIMAX_GDM72XX_K_MODE=y -+CONFIG_WIMAX_GDM72XX_WIMAX2=y -+CONFIG_WIMAX_GDM72XX_USB=y -+# CONFIG_WIMAX_GDM72XX_SDIO is not set -+CONFIG_WIMAX_GDM72XX_USB_PM=y -+CONFIG_LTE_GDM724X=m -+CONFIG_MTD_SPINAND_MT29F=m -+# CONFIG_MTD_SPINAND_ONDIEECC is not set -+# CONFIG_LUSTRE_FS is not set -+CONFIG_DGNC=m -+CONFIG_DGAP=m -+# CONFIG_GS_FPGABOOT is not set -+# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set -+# CONFIG_FB_TFT is not set -+# CONFIG_I2O is not set -+# CONFIG_CHROME_PLATFORMS is not set -+CONFIG_CLKDEV_LOOKUP=y -+CONFIG_HAVE_CLK_PREPARE=y -+CONFIG_COMMON_CLK=y -+ -+# -+# Common Clock Framework -+# -+# CONFIG_COMMON_CLK_SI5351 is not set -+# CONFIG_COMMON_CLK_SI570 is not set -+# CONFIG_CLK_QORIQ is not set -+# CONFIG_COMMON_CLK_PWM is not set -+# CONFIG_COMMON_CLK_PXA is not set -+# CONFIG_COMMON_CLK_CDCE706 is not set -+ -+# -+# Hardware Spinlock drivers -+# -+ -+# -+# Clock Source drivers -+# -+CONFIG_CLKSRC_OF=y -+CONFIG_CLKSRC_MMIO=y -+# CONFIG_ATMEL_PIT is not set -+# CONFIG_SH_TIMER_CMT is not set -+# CONFIG_SH_TIMER_MTU2 is not set -+# CONFIG_SH_TIMER_TMU is not set -+# CONFIG_EM_TIMER_STI is not set -+# CONFIG_MAILBOX is not set -+CONFIG_IOMMU_SUPPORT=y -+ -+# -+# Generic IOMMU Pagetable Support -+# -+# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set -+# CONFIG_ARM_SMMU is not set -+ -+# -+# Remoteproc drivers -+# -+# CONFIG_STE_MODEM_RPROC is not set -+ -+# -+# Rpmsg drivers -+# -+ -+# -+# SOC (System On Chip) specific Drivers -+# -+# CONFIG_SOC_TI is not set -+CONFIG_PM_DEVFREQ=y -+ -+# -+# DEVFREQ Governors -+# -+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=m -+CONFIG_DEVFREQ_GOV_PERFORMANCE=m -+CONFIG_DEVFREQ_GOV_POWERSAVE=m -+CONFIG_DEVFREQ_GOV_USERSPACE=m -+ -+# -+# DEVFREQ Drivers -+# -+# CONFIG_PM_DEVFREQ_EVENT is not set -+CONFIG_EXTCON=m -+ -+# -+# Extcon Device Drivers -+# -+CONFIG_EXTCON_ADC_JACK=m -+CONFIG_EXTCON_GPIO=m -+CONFIG_EXTCON_RT8973A=m -+CONFIG_EXTCON_SM5502=m -+# CONFIG_EXTCON_USB_GPIO is not set -+# CONFIG_MEMORY is not set -+CONFIG_IIO=m -+CONFIG_IIO_BUFFER=y -+# CONFIG_IIO_BUFFER_CB is not set -+CONFIG_IIO_KFIFO_BUF=m -+CONFIG_IIO_TRIGGERED_BUFFER=m -+CONFIG_IIO_TRIGGER=y -+CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 -+ -+# -+# Accelerometers -+# -+# CONFIG_BMA180 is not set -+# CONFIG_BMC150_ACCEL is not set -+# CONFIG_HID_SENSOR_ACCEL_3D is not set -+# CONFIG_IIO_ST_ACCEL_3AXIS is not set -+# CONFIG_KXSD9 is not set -+# CONFIG_MMA8452 is not set -+# CONFIG_KXCJK1013 is not set -+# CONFIG_MMA9551 is not set -+# CONFIG_MMA9553 is not set -+ -+# -+# Analog to digital converters -+# -+# CONFIG_AD7266 is not set -+# CONFIG_AD7291 is not set -+# CONFIG_AD7298 is not set -+# CONFIG_AD7476 is not set -+# CONFIG_AD7791 is not set -+# CONFIG_AD7793 is not set -+# CONFIG_AD7887 is not set -+# CONFIG_AD7923 is not set -+# CONFIG_AD799X is not set -+# CONFIG_CC10001_ADC is not set -+# CONFIG_MAX1027 is not set -+# CONFIG_MAX1363 is not set -+# CONFIG_MCP320X is not set -+# CONFIG_MCP3422 is not set -+# CONFIG_NAU7802 is not set -+# CONFIG_TI_ADC081C is not set -+# CONFIG_TI_ADC128S052 is not set -+# CONFIG_VF610_ADC is not set -+ -+# -+# Amplifiers -+# -+# CONFIG_AD8366 is not set -+ -+# -+# Hid Sensor IIO Common -+# -+CONFIG_HID_SENSOR_IIO_COMMON=m -+CONFIG_HID_SENSOR_IIO_TRIGGER=m -+ -+# -+# SSP Sensor Common -+# -+# CONFIG_IIO_SSP_SENSORHUB is not set -+ -+# -+# Digital to analog converters -+# -+# CONFIG_AD5064 is not set -+# CONFIG_AD5360 is not set -+# CONFIG_AD5380 is not set -+# CONFIG_AD5421 is not set -+# CONFIG_AD5446 is not set -+# CONFIG_AD5449 is not set -+# CONFIG_AD5504 is not set -+# CONFIG_AD5624R_SPI is not set -+# CONFIG_AD5686 is not set -+# CONFIG_AD5755 is not set -+# CONFIG_AD5764 is not set -+# CONFIG_AD5791 is not set -+# CONFIG_AD7303 is not set -+# CONFIG_MAX517 is not set -+# CONFIG_MAX5821 is not set -+# CONFIG_MCP4725 is not set -+# CONFIG_MCP4922 is not set -+ -+# -+# Frequency Synthesizers DDS/PLL -+# -+ -+# -+# Clock Generator/Distribution -+# -+# CONFIG_AD9523 is not set -+ -+# -+# Phase-Locked Loop (PLL) frequency synthesizers -+# -+# CONFIG_ADF4350 is not set -+ -+# -+# Digital gyroscope sensors -+# -+# CONFIG_ADIS16080 is not set -+# CONFIG_ADIS16130 is not set -+# CONFIG_ADIS16136 is not set -+# CONFIG_ADIS16260 is not set -+# CONFIG_ADXRS450 is not set -+# CONFIG_BMG160 is not set -+CONFIG_HID_SENSOR_GYRO_3D=m -+# CONFIG_IIO_ST_GYRO_3AXIS is not set -+# CONFIG_ITG3200 is not set -+ -+# -+# Humidity sensors -+# -+CONFIG_DHT11=m -+# CONFIG_SI7005 is not set -+# CONFIG_SI7020 is not set -+ -+# -+# Inertial measurement units -+# -+# CONFIG_ADIS16400 is not set -+# CONFIG_ADIS16480 is not set -+# CONFIG_KMX61 is not set -+# CONFIG_INV_MPU6050_IIO is not set -+ -+# -+# Light sensors -+# -+# CONFIG_ADJD_S311 is not set -+# CONFIG_AL3320A is not set -+# CONFIG_APDS9300 is not set -+# CONFIG_CM32181 is not set -+# CONFIG_CM3232 is not set -+# CONFIG_CM3323 is not set -+# CONFIG_CM36651 is not set -+# CONFIG_GP2AP020A00F is not set -+# CONFIG_ISL29125 is not set -+# CONFIG_HID_SENSOR_ALS is not set -+# CONFIG_HID_SENSOR_PROX is not set -+# CONFIG_JSA1212 is not set -+# CONFIG_LTR501 is not set -+# CONFIG_TCS3414 is not set -+# CONFIG_TCS3472 is not set -+# CONFIG_SENSORS_TSL2563 is not set -+# CONFIG_TSL4531 is not set -+# CONFIG_VCNL4000 is not set -+ -+# -+# Magnetometer sensors -+# -+# CONFIG_AK8975 is not set -+# CONFIG_AK09911 is not set -+# CONFIG_MAG3110 is not set -+# CONFIG_HID_SENSOR_MAGNETOMETER_3D is not set -+# CONFIG_IIO_ST_MAGN_3AXIS is not set -+ -+# -+# Inclinometer sensors -+# -+# CONFIG_HID_SENSOR_INCLINOMETER_3D is not set -+# CONFIG_HID_SENSOR_DEVICE_ROTATION is not set -+ -+# -+# Triggers - standalone -+# -+CONFIG_IIO_INTERRUPT_TRIGGER=m -+CONFIG_IIO_SYSFS_TRIGGER=m -+ -+# -+# Pressure sensors -+# -+# CONFIG_BMP280 is not set -+# CONFIG_HID_SENSOR_PRESS is not set -+# CONFIG_MPL115 is not set -+# CONFIG_MPL3115 is not set -+# CONFIG_MS5611 is not set -+# CONFIG_IIO_ST_PRESS is not set -+# CONFIG_T5403 is not set -+ -+# -+# Lightning sensors -+# -+# CONFIG_AS3935 is not set -+ -+# -+# Proximity sensors -+# -+# CONFIG_SX9500 is not set -+ -+# -+# Temperature sensors -+# -+# CONFIG_MLX90614 is not set -+# CONFIG_TMP006 is not set -+# CONFIG_VME_BUS is not set -+CONFIG_PWM=y -+CONFIG_PWM_SYSFS=y -+CONFIG_PWM_FSL_FTM=y -+CONFIG_PWM_IMX=y -+CONFIG_PWM_PCA9685=y -+CONFIG_IRQCHIP=y -+CONFIG_ARM_GIC=y -+# CONFIG_IPACK_BUS is not set -+CONFIG_ARCH_HAS_RESET_CONTROLLER=y -+CONFIG_RESET_CONTROLLER=y -+# CONFIG_FMC is not set -+ -+# -+# PHY Subsystem -+# -+CONFIG_GENERIC_PHY=y -+# CONFIG_BCM_KONA_USB2_PHY is not set -+# CONFIG_PHY_SAMSUNG_USB2 is not set -+CONFIG_POWERCAP=y -+# CONFIG_MCB is not set -+CONFIG_RAS=y -+# CONFIG_THUNDERBOLT is not set -+ -+# -+# Android -+# -+# CONFIG_ANDROID is not set -+ -+# -+# MXC support drivers -+# -+CONFIG_MXC_IPU=y -+ -+# -+# Vivante GPU support -+# -+CONFIG_MXC_GPU_VIV=y -+CONFIG_MXC_IPU_V3_FSL=y -+ -+# -+# MXC Asynchronous Sample Rate Converter support -+# -+# CONFIG_MXC_ASRC is not set -+ -+# -+# MXC VPU(Video Processing Unit) support -+# -+CONFIG_MXC_VPU=y -+# CONFIG_MXC_VPU_DEBUG is not set -+# CONFIG_MX6_VPU_352M is not set -+ -+# -+# MXC HDMI CEC (Consumer Electronics Control) support -+# -+CONFIG_MXC_HDMI_CEC=y -+ -+# -+# MXC MIPI Support -+# -+CONFIG_MXC_MIPI_CSI2=m -+ -+# -+# MXC Media Local Bus Driver -+# -+CONFIG_MXC_MLB=y -+CONFIG_MXC_MLB150=m -+ -+# -+# Firmware Drivers -+# -+# CONFIG_FIRMWARE_MEMMAP is not set -+ -+# -+# File systems -+# -+CONFIG_DCACHE_WORD_ACCESS=y -+# CONFIG_EXT2_FS is not set -+# CONFIG_EXT3_FS is not set -+CONFIG_EXT4_FS=y -+CONFIG_EXT4_USE_FOR_EXT23=y -+CONFIG_EXT4_FS_POSIX_ACL=y -+CONFIG_EXT4_FS_SECURITY=y -+# CONFIG_EXT4_ENCRYPTION is not set -+# CONFIG_EXT4_DEBUG is not set -+CONFIG_JBD2=y -+# CONFIG_JBD2_DEBUG is not set -+CONFIG_FS_MBCACHE=y -+CONFIG_REISERFS_FS=m -+# CONFIG_REISERFS_CHECK is not set -+# CONFIG_REISERFS_PROC_INFO is not set -+CONFIG_REISERFS_FS_XATTR=y -+CONFIG_REISERFS_FS_POSIX_ACL=y -+# CONFIG_REISERFS_FS_SECURITY is not set -+CONFIG_JFS_FS=m -+CONFIG_JFS_POSIX_ACL=y -+CONFIG_JFS_SECURITY=y -+# CONFIG_JFS_DEBUG is not set -+# CONFIG_JFS_STATISTICS is not set -+CONFIG_XFS_FS=m -+CONFIG_XFS_QUOTA=y -+CONFIG_XFS_POSIX_ACL=y -+# CONFIG_XFS_RT is not set -+# CONFIG_XFS_WARN is not set -+# CONFIG_XFS_DEBUG is not set -+# CONFIG_GFS2_FS is not set -+# CONFIG_OCFS2_FS is not set -+CONFIG_BTRFS_FS=y -+CONFIG_BTRFS_FS_POSIX_ACL=y -+# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set -+# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set -+# CONFIG_BTRFS_DEBUG is not set -+# CONFIG_BTRFS_ASSERT is not set -+# CONFIG_NILFS2_FS is not set -+CONFIG_F2FS_FS=m -+CONFIG_F2FS_STAT_FS=y -+CONFIG_F2FS_FS_XATTR=y -+CONFIG_F2FS_FS_POSIX_ACL=y -+# CONFIG_F2FS_FS_SECURITY is not set -+# CONFIG_F2FS_CHECK_FS is not set -+CONFIG_FS_POSIX_ACL=y -+CONFIG_EXPORTFS=y -+CONFIG_FILE_LOCKING=y -+CONFIG_FSNOTIFY=y -+CONFIG_DNOTIFY=y -+CONFIG_INOTIFY_USER=y -+CONFIG_FANOTIFY=y -+# CONFIG_QUOTA is not set -+# CONFIG_QUOTA_NETLINK_INTERFACE is not set -+CONFIG_QUOTACTL=y -+CONFIG_AUTOFS4_FS=y -+CONFIG_FUSE_FS=y -+CONFIG_CUSE=y -+CONFIG_OVERLAY_FS=y -+ -+# -+# Caches -+# -+CONFIG_FSCACHE=m -+# CONFIG_FSCACHE_STATS is not set -+# CONFIG_FSCACHE_HISTOGRAM is not set -+# CONFIG_FSCACHE_DEBUG is not set -+# CONFIG_FSCACHE_OBJECT_LIST is not set -+CONFIG_CACHEFILES=m -+# CONFIG_CACHEFILES_DEBUG is not set -+# CONFIG_CACHEFILES_HISTOGRAM is not set -+ -+# -+# CD-ROM/DVD Filesystems -+# -+CONFIG_ISO9660_FS=y -+CONFIG_JOLIET=y -+CONFIG_ZISOFS=y -+CONFIG_UDF_FS=y -+CONFIG_UDF_NLS=y -+ -+# -+# DOS/FAT/NT Filesystems -+# -+CONFIG_FAT_FS=y -+CONFIG_MSDOS_FS=y -+CONFIG_VFAT_FS=y -+CONFIG_FAT_DEFAULT_CODEPAGE=437 -+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -+CONFIG_NTFS_FS=m -+# CONFIG_NTFS_DEBUG is not set -+CONFIG_NTFS_RW=y -+ -+# -+# Pseudo filesystems -+# -+CONFIG_PROC_FS=y -+CONFIG_PROC_SYSCTL=y -+CONFIG_PROC_PAGE_MONITOR=y -+CONFIG_KERNFS=y -+CONFIG_SYSFS=y -+CONFIG_TMPFS=y -+CONFIG_TMPFS_POSIX_ACL=y -+CONFIG_TMPFS_XATTR=y -+# CONFIG_HUGETLB_PAGE is not set -+CONFIG_CONFIGFS_FS=y -+CONFIG_MISC_FILESYSTEMS=y -+# CONFIG_ADFS_FS is not set -+# CONFIG_AFFS_FS is not set -+# CONFIG_ECRYPT_FS is not set -+CONFIG_HFS_FS=m -+CONFIG_HFSPLUS_FS=m -+# CONFIG_HFSPLUS_FS_POSIX_ACL is not set -+# CONFIG_BEFS_FS is not set -+# CONFIG_BFS_FS is not set -+# CONFIG_EFS_FS is not set -+CONFIG_JFFS2_FS=m -+CONFIG_JFFS2_FS_DEBUG=0 -+CONFIG_JFFS2_FS_WRITEBUFFER=y -+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set -+# CONFIG_JFFS2_SUMMARY is not set -+# CONFIG_JFFS2_FS_XATTR is not set -+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set -+CONFIG_JFFS2_ZLIB=y -+# CONFIG_JFFS2_LZO is not set -+CONFIG_JFFS2_RTIME=y -+# CONFIG_JFFS2_RUBIN is not set -+CONFIG_UBIFS_FS=m -+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set -+CONFIG_UBIFS_FS_LZO=y -+CONFIG_UBIFS_FS_ZLIB=y -+CONFIG_LOGFS=m -+# CONFIG_CRAMFS is not set -+CONFIG_SQUASHFS=m -+CONFIG_SQUASHFS_FILE_CACHE=y -+# CONFIG_SQUASHFS_FILE_DIRECT is not set -+CONFIG_SQUASHFS_DECOMP_SINGLE=y -+# CONFIG_SQUASHFS_DECOMP_MULTI is not set -+# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set -+CONFIG_SQUASHFS_XATTR=y -+CONFIG_SQUASHFS_ZLIB=y -+# CONFIG_SQUASHFS_LZ4 is not set -+# CONFIG_SQUASHFS_LZO is not set -+# CONFIG_SQUASHFS_XZ is not set -+# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set -+# CONFIG_SQUASHFS_EMBEDDED is not set -+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 -+# CONFIG_VXFS_FS is not set -+# CONFIG_MINIX_FS is not set -+# CONFIG_OMFS_FS is not set -+# CONFIG_HPFS_FS is not set -+# CONFIG_QNX4FS_FS is not set -+# CONFIG_QNX6FS_FS is not set -+# CONFIG_ROMFS_FS is not set -+# CONFIG_PSTORE is not set -+CONFIG_SYSV_FS=m -+# CONFIG_UFS_FS is not set -+CONFIG_NETWORK_FILESYSTEMS=y -+CONFIG_NFS_FS=y -+CONFIG_NFS_V2=y -+CONFIG_NFS_V3=y -+CONFIG_NFS_V3_ACL=y -+CONFIG_NFS_V4=y -+# CONFIG_NFS_SWAP is not set -+CONFIG_NFS_V4_1=y -+CONFIG_NFS_V4_2=y -+CONFIG_PNFS_FILE_LAYOUT=y -+CONFIG_PNFS_BLOCK=m -+CONFIG_PNFS_FLEXFILE_LAYOUT=m -+CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" -+CONFIG_NFS_V4_1_MIGRATION=y -+CONFIG_ROOT_NFS=y -+# CONFIG_NFS_USE_LEGACY_DNS is not set -+CONFIG_NFS_USE_KERNEL_DNS=y -+CONFIG_NFS_DEBUG=y -+CONFIG_NFSD=m -+CONFIG_NFSD_V2_ACL=y -+CONFIG_NFSD_V3=y -+CONFIG_NFSD_V3_ACL=y -+CONFIG_NFSD_V4=y -+# CONFIG_NFSD_PNFS is not set -+# CONFIG_NFSD_FAULT_INJECTION is not set -+CONFIG_GRACE_PERIOD=y -+CONFIG_LOCKD=y -+CONFIG_LOCKD_V4=y -+CONFIG_NFS_ACL_SUPPORT=y -+CONFIG_NFS_COMMON=y -+CONFIG_SUNRPC=y -+CONFIG_SUNRPC_GSS=y -+CONFIG_SUNRPC_BACKCHANNEL=y -+CONFIG_RPCSEC_GSS_KRB5=m -+CONFIG_SUNRPC_DEBUG=y -+# CONFIG_CEPH_FS is not set -+CONFIG_CIFS=m -+# CONFIG_CIFS_STATS is not set -+CONFIG_CIFS_WEAK_PW_HASH=y -+# CONFIG_CIFS_UPCALL is not set -+CONFIG_CIFS_XATTR=y -+CONFIG_CIFS_POSIX=y -+CONFIG_CIFS_ACL=y -+# CONFIG_CIFS_DEBUG is not set -+CONFIG_CIFS_DFS_UPCALL=y -+CONFIG_CIFS_SMB2=y -+CONFIG_CIFS_FSCACHE=y -+CONFIG_NCP_FS=m -+# CONFIG_NCPFS_PACKET_SIGNING is not set -+# CONFIG_NCPFS_IOCTL_LOCKING is not set -+# CONFIG_NCPFS_STRONG is not set -+# CONFIG_NCPFS_NFS_NS is not set -+# CONFIG_NCPFS_OS2_NS is not set -+# CONFIG_NCPFS_SMALLDOS is not set -+# CONFIG_NCPFS_NLS is not set -+# CONFIG_NCPFS_EXTRAS is not set -+# CONFIG_CODA_FS is not set -+# CONFIG_AFS_FS is not set -+CONFIG_NLS=y -+CONFIG_NLS_DEFAULT="utf8" -+CONFIG_NLS_CODEPAGE_437=y -+CONFIG_NLS_CODEPAGE_737=m -+CONFIG_NLS_CODEPAGE_775=m -+CONFIG_NLS_CODEPAGE_850=y -+CONFIG_NLS_CODEPAGE_852=y -+CONFIG_NLS_CODEPAGE_855=m -+CONFIG_NLS_CODEPAGE_857=m -+CONFIG_NLS_CODEPAGE_860=m -+CONFIG_NLS_CODEPAGE_861=m -+CONFIG_NLS_CODEPAGE_862=m -+CONFIG_NLS_CODEPAGE_863=m -+CONFIG_NLS_CODEPAGE_864=m -+CONFIG_NLS_CODEPAGE_865=m -+CONFIG_NLS_CODEPAGE_866=m -+CONFIG_NLS_CODEPAGE_869=m -+CONFIG_NLS_CODEPAGE_936=m -+CONFIG_NLS_CODEPAGE_950=m -+CONFIG_NLS_CODEPAGE_932=m -+CONFIG_NLS_CODEPAGE_949=m -+CONFIG_NLS_CODEPAGE_874=m -+CONFIG_NLS_ISO8859_8=m -+CONFIG_NLS_CODEPAGE_1250=m -+CONFIG_NLS_CODEPAGE_1251=m -+CONFIG_NLS_ASCII=y -+CONFIG_NLS_ISO8859_1=y -+CONFIG_NLS_ISO8859_2=y -+CONFIG_NLS_ISO8859_3=m -+CONFIG_NLS_ISO8859_4=m -+CONFIG_NLS_ISO8859_5=m -+CONFIG_NLS_ISO8859_6=m -+CONFIG_NLS_ISO8859_7=m -+CONFIG_NLS_ISO8859_9=m -+CONFIG_NLS_ISO8859_13=m -+CONFIG_NLS_ISO8859_14=m -+CONFIG_NLS_ISO8859_15=y -+CONFIG_NLS_KOI8_R=m -+CONFIG_NLS_KOI8_U=m -+CONFIG_NLS_MAC_ROMAN=m -+CONFIG_NLS_MAC_CELTIC=m -+CONFIG_NLS_MAC_CENTEURO=m -+CONFIG_NLS_MAC_CROATIAN=m -+CONFIG_NLS_MAC_CYRILLIC=m -+CONFIG_NLS_MAC_GAELIC=m -+CONFIG_NLS_MAC_GREEK=m -+CONFIG_NLS_MAC_ICELAND=m -+CONFIG_NLS_MAC_INUIT=m -+CONFIG_NLS_MAC_ROMANIAN=m -+CONFIG_NLS_MAC_TURKISH=m -+CONFIG_NLS_UTF8=y -+# CONFIG_DLM is not set -+ -+# -+# Kernel hacking -+# -+ -+# -+# printk and dmesg options -+# -+CONFIG_PRINTK_TIME=y -+CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 -+# CONFIG_BOOT_PRINTK_DELAY is not set -+CONFIG_DYNAMIC_DEBUG=y -+ -+# -+# Compile-time checks and compiler options -+# -+# CONFIG_DEBUG_INFO is not set -+CONFIG_ENABLE_WARN_DEPRECATED=y -+# CONFIG_ENABLE_MUST_CHECK is not set -+CONFIG_FRAME_WARN=1024 -+CONFIG_STRIP_ASM_SYMS=y -+# CONFIG_READABLE_ASM is not set -+# CONFIG_UNUSED_SYMBOLS is not set -+# CONFIG_PAGE_OWNER is not set -+CONFIG_DEBUG_FS=y -+# CONFIG_HEADERS_CHECK is not set -+# CONFIG_DEBUG_SECTION_MISMATCH is not set -+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -+CONFIG_MAGIC_SYSRQ=y -+CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 -+CONFIG_DEBUG_KERNEL=y -+ -+# -+# Memory Debugging -+# -+# CONFIG_PAGE_EXTENSION is not set -+# CONFIG_DEBUG_PAGEALLOC is not set -+# CONFIG_DEBUG_OBJECTS is not set -+# CONFIG_SLUB_STATS is not set -+CONFIG_HAVE_DEBUG_KMEMLEAK=y -+# CONFIG_DEBUG_KMEMLEAK is not set -+# CONFIG_DEBUG_STACK_USAGE is not set -+# CONFIG_DEBUG_VM is not set -+# CONFIG_DEBUG_MEMORY_INIT is not set -+# CONFIG_DEBUG_PER_CPU_MAPS is not set -+# CONFIG_DEBUG_HIGHMEM is not set -+# CONFIG_DEBUG_SHIRQ is not set -+ -+# -+# Debug Lockups and Hangs -+# -+# CONFIG_LOCKUP_DETECTOR is not set -+# CONFIG_DETECT_HUNG_TASK is not set -+CONFIG_PANIC_ON_OOPS=y -+CONFIG_PANIC_ON_OOPS_VALUE=1 -+CONFIG_PANIC_TIMEOUT=60 -+# CONFIG_SCHED_DEBUG is not set -+# CONFIG_SCHEDSTATS is not set -+# CONFIG_SCHED_STACK_END_CHECK is not set -+# CONFIG_DEBUG_TIMEKEEPING is not set -+# CONFIG_TIMER_STATS is not set -+ -+# -+# Lock Debugging (spinlocks, mutexes, etc...) -+# -+# CONFIG_DEBUG_RT_MUTEXES is not set -+# CONFIG_DEBUG_SPINLOCK is not set -+# CONFIG_DEBUG_MUTEXES is not set -+# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set -+# CONFIG_DEBUG_LOCK_ALLOC is not set -+# CONFIG_PROVE_LOCKING is not set -+# CONFIG_LOCK_STAT is not set -+# CONFIG_DEBUG_ATOMIC_SLEEP is not set -+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -+# CONFIG_LOCK_TORTURE_TEST is not set -+# CONFIG_STACKTRACE is not set -+# CONFIG_DEBUG_KOBJECT is not set -+# CONFIG_DEBUG_BUGVERBOSE is not set -+# CONFIG_DEBUG_LIST is not set -+# CONFIG_DEBUG_PI_LIST is not set -+# CONFIG_DEBUG_SG is not set -+# CONFIG_DEBUG_NOTIFIERS is not set -+# CONFIG_DEBUG_CREDENTIALS is not set -+ -+# -+# RCU Debugging -+# -+# CONFIG_PROVE_RCU is not set -+# CONFIG_SPARSE_RCU_POINTER is not set -+# CONFIG_TORTURE_TEST is not set -+# CONFIG_RCU_TORTURE_TEST is not set -+CONFIG_RCU_CPU_STALL_TIMEOUT=21 -+# CONFIG_RCU_CPU_STALL_INFO is not set -+# CONFIG_RCU_TRACE is not set -+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -+# CONFIG_NOTIFIER_ERROR_INJECTION is not set -+# CONFIG_FAULT_INJECTION is not set -+CONFIG_HAVE_FUNCTION_TRACER=y -+CONFIG_HAVE_DYNAMIC_FTRACE=y -+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -+CONFIG_HAVE_C_RECORDMCOUNT=y -+CONFIG_TRACING_SUPPORT=y -+# CONFIG_FTRACE is not set -+ -+# -+# Runtime Testing -+# -+# CONFIG_LKDTM is not set -+# CONFIG_TEST_LIST_SORT is not set -+# CONFIG_BACKTRACE_SELF_TEST is not set -+# CONFIG_RBTREE_TEST is not set -+# CONFIG_INTERVAL_TREE_TEST is not set -+# CONFIG_PERCPU_TEST is not set -+# CONFIG_ATOMIC64_SELFTEST is not set -+# CONFIG_ASYNC_RAID6_TEST is not set -+# CONFIG_TEST_HEXDUMP is not set -+# CONFIG_TEST_STRING_HELPERS is not set -+# CONFIG_TEST_KSTRTOX is not set -+# CONFIG_TEST_RHASHTABLE is not set -+# CONFIG_DMA_API_DEBUG is not set -+# CONFIG_TEST_LKM is not set -+# CONFIG_TEST_USER_COPY is not set -+# CONFIG_TEST_BPF is not set -+# CONFIG_TEST_FIRMWARE is not set -+# CONFIG_TEST_UDELAY is not set -+# CONFIG_MEMTEST is not set -+# CONFIG_SAMPLES is not set -+CONFIG_HAVE_ARCH_KGDB=y -+# CONFIG_KGDB is not set -+# CONFIG_ARM_PTDUMP is not set -+# CONFIG_STRICT_DEVMEM is not set -+CONFIG_ARM_UNWIND=y -+# CONFIG_DEBUG_USER is not set -+# CONFIG_DEBUG_LL is not set -+CONFIG_DEBUG_IMX_UART_PORT=1 -+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -+# CONFIG_DEBUG_UART_8250 is not set -+# CONFIG_DEBUG_UART_BCM63XX is not set -+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -+# CONFIG_PID_IN_CONTEXTIDR is not set -+# CONFIG_DEBUG_SET_MODULE_RONX is not set -+# CONFIG_CORESIGHT is not set -+ -+# -+# Security options -+# -+CONFIG_KEYS=y -+# CONFIG_PERSISTENT_KEYRINGS is not set -+# CONFIG_BIG_KEYS is not set -+# CONFIG_ENCRYPTED_KEYS is not set -+# CONFIG_SECURITY_DMESG_RESTRICT is not set -+# CONFIG_SECURITY is not set -+# CONFIG_SECURITYFS is not set -+CONFIG_DEFAULT_SECURITY_DAC=y -+CONFIG_DEFAULT_SECURITY="" -+CONFIG_XOR_BLOCKS=y -+CONFIG_ASYNC_CORE=m -+CONFIG_ASYNC_MEMCPY=m -+CONFIG_ASYNC_XOR=m -+CONFIG_ASYNC_PQ=m -+CONFIG_ASYNC_RAID6_RECOV=m -+CONFIG_CRYPTO=y -+ -+# -+# Crypto core or helper -+# -+CONFIG_CRYPTO_ALGAPI=y -+CONFIG_CRYPTO_ALGAPI2=y -+CONFIG_CRYPTO_AEAD=y -+CONFIG_CRYPTO_AEAD2=y -+CONFIG_CRYPTO_BLKCIPHER=y -+CONFIG_CRYPTO_BLKCIPHER2=y -+CONFIG_CRYPTO_HASH=y -+CONFIG_CRYPTO_HASH2=y -+CONFIG_CRYPTO_RNG=y -+CONFIG_CRYPTO_RNG2=y -+CONFIG_CRYPTO_PCOMP=y -+CONFIG_CRYPTO_PCOMP2=y -+CONFIG_CRYPTO_MANAGER=y -+CONFIG_CRYPTO_MANAGER2=y -+CONFIG_CRYPTO_USER=y -+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y -+CONFIG_CRYPTO_GF128MUL=y -+CONFIG_CRYPTO_NULL=y -+CONFIG_CRYPTO_PCRYPT=y -+CONFIG_CRYPTO_WORKQUEUE=y -+CONFIG_CRYPTO_CRYPTD=y -+# CONFIG_CRYPTO_MCRYPTD is not set -+CONFIG_CRYPTO_AUTHENC=y -+# CONFIG_CRYPTO_TEST is not set -+ -+# -+# Authenticated Encryption with Associated Data -+# -+CONFIG_CRYPTO_CCM=y -+CONFIG_CRYPTO_GCM=y -+CONFIG_CRYPTO_SEQIV=y -+ -+# -+# Block modes -+# -+CONFIG_CRYPTO_CBC=y -+CONFIG_CRYPTO_CTR=y -+CONFIG_CRYPTO_CTS=y -+CONFIG_CRYPTO_ECB=y -+CONFIG_CRYPTO_LRW=y -+CONFIG_CRYPTO_PCBC=y -+CONFIG_CRYPTO_XTS=y -+ -+# -+# Hash modes -+# -+CONFIG_CRYPTO_CMAC=y -+CONFIG_CRYPTO_HMAC=y -+CONFIG_CRYPTO_XCBC=y -+CONFIG_CRYPTO_VMAC=y -+ -+# -+# Digest -+# -+CONFIG_CRYPTO_CRC32C=y -+CONFIG_CRYPTO_CRC32=y -+CONFIG_CRYPTO_CRCT10DIF=y -+CONFIG_CRYPTO_GHASH=y -+CONFIG_CRYPTO_MD4=y -+CONFIG_CRYPTO_MD5=y -+CONFIG_CRYPTO_MICHAEL_MIC=y -+CONFIG_CRYPTO_RMD128=m -+CONFIG_CRYPTO_RMD160=m -+CONFIG_CRYPTO_RMD256=m -+CONFIG_CRYPTO_RMD320=m -+CONFIG_CRYPTO_SHA1=y -+CONFIG_CRYPTO_SHA256=y -+CONFIG_CRYPTO_SHA512=y -+CONFIG_CRYPTO_TGR192=m -+CONFIG_CRYPTO_WP512=m -+ -+# -+# Ciphers -+# -+CONFIG_CRYPTO_AES=y -+CONFIG_CRYPTO_ANUBIS=m -+CONFIG_CRYPTO_ARC4=y -+CONFIG_CRYPTO_BLOWFISH=m -+CONFIG_CRYPTO_BLOWFISH_COMMON=m -+CONFIG_CRYPTO_CAMELLIA=m -+CONFIG_CRYPTO_CAST_COMMON=m -+CONFIG_CRYPTO_CAST5=m -+CONFIG_CRYPTO_CAST6=m -+CONFIG_CRYPTO_DES=y -+CONFIG_CRYPTO_FCRYPT=m -+CONFIG_CRYPTO_KHAZAD=m -+CONFIG_CRYPTO_SALSA20=m -+CONFIG_CRYPTO_SEED=m -+CONFIG_CRYPTO_SERPENT=m -+CONFIG_CRYPTO_TEA=y -+CONFIG_CRYPTO_TWOFISH=y -+CONFIG_CRYPTO_TWOFISH_COMMON=y -+ -+# -+# Compression -+# -+CONFIG_CRYPTO_DEFLATE=y -+CONFIG_CRYPTO_ZLIB=y -+CONFIG_CRYPTO_LZO=y -+CONFIG_CRYPTO_LZ4=y -+CONFIG_CRYPTO_LZ4HC=y -+ -+# -+# Random Number Generation -+# -+CONFIG_CRYPTO_ANSI_CPRNG=y -+# CONFIG_CRYPTO_DRBG_MENU is not set -+CONFIG_CRYPTO_USER_API=m -+CONFIG_CRYPTO_USER_API_HASH=m -+CONFIG_CRYPTO_USER_API_SKCIPHER=m -+# CONFIG_CRYPTO_USER_API_RNG is not set -+CONFIG_CRYPTO_HW=y -+# CONFIG_CRYPTO_DEV_HIFN_795X is not set -+CONFIG_CRYPTO_DEV_FSL_CAAM=y -+CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9 -+# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set -+CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=m -+CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=m -+CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y -+# CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST is not set -+CONFIG_CRYPTO_DEV_FSL_CAAM_SM=m -+CONFIG_CRYPTO_DEV_FSL_CAAM_SM_SLOTSIZE=7 -+# CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST is not set -+# CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO is not set -+# CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set -+# CONFIG_CRYPTO_DEV_SAHARA is not set -+# CONFIG_ASYMMETRIC_KEY_TYPE is not set -+# CONFIG_ARM_CRYPTO is not set -+# CONFIG_BINARY_PRINTF is not set -+ -+# -+# Library routines -+# -+CONFIG_RAID6_PQ=y -+CONFIG_BITREVERSE=y -+CONFIG_HAVE_ARCH_BITREVERSE=y -+CONFIG_RATIONAL=y -+CONFIG_GENERIC_STRNCPY_FROM_USER=y -+CONFIG_GENERIC_STRNLEN_USER=y -+CONFIG_GENERIC_NET_UTILS=y -+CONFIG_GENERIC_PCI_IOMAP=y -+CONFIG_GENERIC_IO=y -+CONFIG_STMP_DEVICE=y -+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y -+CONFIG_CRC_CCITT=y -+CONFIG_CRC16=y -+CONFIG_CRC_T10DIF=y -+CONFIG_CRC_ITU_T=y -+CONFIG_CRC32=y -+# CONFIG_CRC32_SELFTEST is not set -+CONFIG_CRC32_SLICEBY8=y -+# CONFIG_CRC32_SLICEBY4 is not set -+# CONFIG_CRC32_SARWATE is not set -+# CONFIG_CRC32_BIT is not set -+CONFIG_CRC7=m -+CONFIG_LIBCRC32C=y -+CONFIG_CRC8=y -+CONFIG_AUDIT_GENERIC=y -+# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set -+# CONFIG_RANDOM32_SELFTEST is not set -+CONFIG_ZLIB_INFLATE=y -+CONFIG_ZLIB_DEFLATE=y -+CONFIG_LZO_COMPRESS=y -+CONFIG_LZO_DECOMPRESS=y -+CONFIG_LZ4_COMPRESS=y -+CONFIG_LZ4HC_COMPRESS=y -+CONFIG_LZ4_DECOMPRESS=y -+CONFIG_XZ_DEC=y -+# CONFIG_XZ_DEC_X86 is not set -+# CONFIG_XZ_DEC_POWERPC is not set -+# CONFIG_XZ_DEC_IA64 is not set -+CONFIG_XZ_DEC_ARM=y -+CONFIG_XZ_DEC_ARMTHUMB=y -+# CONFIG_XZ_DEC_SPARC is not set -+CONFIG_XZ_DEC_BCJ=y -+# CONFIG_XZ_DEC_TEST is not set -+CONFIG_DECOMPRESS_GZIP=y -+CONFIG_DECOMPRESS_LZO=y -+CONFIG_DECOMPRESS_LZ4=y -+CONFIG_GENERIC_ALLOCATOR=y -+CONFIG_TEXTSEARCH=y -+CONFIG_TEXTSEARCH_KMP=m -+CONFIG_TEXTSEARCH_BM=m -+CONFIG_TEXTSEARCH_FSM=m -+CONFIG_BTREE=y -+CONFIG_ASSOCIATIVE_ARRAY=y -+CONFIG_HAS_IOMEM=y -+CONFIG_HAS_IOPORT_MAP=y -+CONFIG_HAS_DMA=y -+CONFIG_CPU_RMAP=y -+CONFIG_DQL=y -+CONFIG_GLOB=y -+# CONFIG_GLOB_SELFTEST is not set -+CONFIG_NLATTR=y -+CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y -+CONFIG_AVERAGE=y -+CONFIG_CORDIC=m -+# CONFIG_DDR is not set -+CONFIG_LIBFDT=y -+CONFIG_OID_REGISTRY=y -+CONFIG_FONT_SUPPORT=y -+# CONFIG_FONTS is not set -+CONFIG_FONT_8x8=y -+CONFIG_FONT_8x16=y -+CONFIG_ARCH_HAS_SG_CHAIN=y -+# CONFIG_VIRTUALIZATION is not set -diff -Nur linux-4.1.13.orig/arch/arm/configs/imx_v7_defconfig linux-4.1.13/arch/arm/configs/imx_v7_defconfig ---- linux-4.1.13.orig/arch/arm/configs/imx_v7_defconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/arch/arm/configs/imx_v7_defconfig 2015-11-30 17:56:13.528141189 +0100 -@@ -0,0 +1,414 @@ -+CONFIG_KERNEL_LZO=y -+CONFIG_SYSVIPC=y -+CONFIG_NO_HZ=y -+CONFIG_HIGH_RES_TIMERS=y -+CONFIG_LOG_BUF_SHIFT=18 -+CONFIG_CGROUPS=y -+CONFIG_RELAY=y -+CONFIG_BLK_DEV_INITRD=y -+CONFIG_EXPERT=y -+CONFIG_KALLSYMS_ALL=y -+CONFIG_PERF_EVENTS=y -+# CONFIG_SLUB_DEBUG is not set -+# CONFIG_COMPAT_BRK is not set -+CONFIG_MODULES=y -+CONFIG_MODULE_UNLOAD=y -+CONFIG_MODVERSIONS=y -+CONFIG_MODULE_SRCVERSION_ALL=y -+# CONFIG_BLK_DEV_BSG is not set -+CONFIG_GPIO_PCA953X=y -+CONFIG_ARCH_MXC=y -+CONFIG_MACH_IMX51_DT=y -+CONFIG_MACH_EUKREA_CPUIMX51SD=y -+CONFIG_SOC_IMX50=y -+CONFIG_SOC_IMX53=y -+CONFIG_SOC_IMX6Q=y -+CONFIG_SOC_IMX6SL=y -+CONFIG_SOC_IMX6SX=y -+CONFIG_SOC_VF610=y -+# CONFIG_SWP_EMULATE is not set -+CONFIG_SMP=y -+CONFIG_VMSPLIT_2G=y -+CONFIG_PREEMPT=y -+CONFIG_AEABI=y -+CONFIG_HIGHMEM=y -+CONFIG_CMA=y -+CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" -+CONFIG_KEXEC=y -+CONFIG_CPU_FREQ=y -+CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y -+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -+CONFIG_CPU_FREQ_GOV_POWERSAVE=y -+CONFIG_CPU_FREQ_GOV_USERSPACE=y -+CONFIG_CPU_FREQ_GOV_ONDEMAND=y -+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -+CONFIG_ARM_IMX6Q_CPUFREQ=y -+CONFIG_CPU_IDLE=y -+CONFIG_VFP=y -+CONFIG_NEON=y -+CONFIG_BINFMT_MISC=m -+CONFIG_PM_RUNTIME=y -+CONFIG_PM_DEBUG=y -+CONFIG_PM_TEST_SUSPEND=y -+CONFIG_NET=y -+CONFIG_PACKET=y -+CONFIG_UNIX=y -+CONFIG_INET=y -+CONFIG_IP_PNP=y -+CONFIG_IP_PNP_DHCP=y -+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -+# CONFIG_INET_XFRM_MODE_TUNNEL is not set -+# CONFIG_INET_XFRM_MODE_BEET is not set -+# CONFIG_INET_LRO is not set -+CONFIG_IPV6=y -+CONFIG_NETFILTER=y -+CONFIG_VLAN_8021Q=y -+CONFIG_LLC2=y -+CONFIG_CAN=y -+CONFIG_CAN_FLEXCAN=y -+CONFIG_CAN_M_CAN=y -+CONFIG_BT=y -+CONFIG_BT_RFCOMM=y -+CONFIG_BT_RFCOMM_TTY=y -+CONFIG_BT_BNEP=y -+CONFIG_BT_BNEP_MC_FILTER=y -+CONFIG_BT_BNEP_PROTO_FILTER=y -+CONFIG_BT_HIDP=y -+CONFIG_BT_HCIBTUSB=y -+CONFIG_BT_HCIBTSDIO=y -+CONFIG_BT_HCIUART=y -+CONFIG_BT_HCIUART_H4=y -+CONFIG_BT_HCIUART_BCSP=y -+CONFIG_BT_HCIUART_ATH3K=y -+CONFIG_BT_HCIBCM203X=y -+CONFIG_BT_ATH3K=y -+CONFIG_CFG80211=y -+CONFIG_MAC80211=y -+CONFIG_DEVTMPFS=y -+CONFIG_DEVTMPFS_MOUNT=y -+# CONFIG_STANDALONE is not set -+CONFIG_DMA_CMA=y -+CONFIG_CMA_SIZE_MBYTES=320 -+CONFIG_IMX_WEIM=y -+CONFIG_CONNECTOR=y -+CONFIG_MTD=y -+CONFIG_MTD_CMDLINE_PARTS=y -+CONFIG_MTD_BLOCK=y -+CONFIG_MTD_CFI=y -+CONFIG_MTD_JEDECPROBE=y -+CONFIG_MTD_CFI_INTELEXT=y -+CONFIG_MTD_CFI_AMDSTD=y -+CONFIG_MTD_CFI_STAA=y -+CONFIG_MTD_PHYSMAP_OF=y -+CONFIG_MTD_DATAFLASH=y -+CONFIG_MTD_M25P80=y -+CONFIG_MTD_SST25L=y -+CONFIG_MTD_NAND=y -+CONFIG_MTD_NAND_GPMI_NAND=y -+CONFIG_MTD_NAND_MXC=y -+CONFIG_MTD_SPI_NOR=y -+CONFIG_SPI_FSL_QUADSPI=y -+CONFIG_MTD_UBI=y -+CONFIG_BLK_DEV_LOOP=y -+CONFIG_BLK_DEV_RAM=y -+CONFIG_BLK_DEV_RAM_SIZE=65536 -+CONFIG_EEPROM_AT24=y -+CONFIG_EEPROM_AT25=y -+# CONFIG_SCSI_PROC_FS is not set -+CONFIG_BLK_DEV_SD=y -+CONFIG_SCSI_MULTI_LUN=y -+CONFIG_SCSI_CONSTANTS=y -+CONFIG_SCSI_LOGGING=y -+CONFIG_SCSI_SCAN_ASYNC=y -+# CONFIG_SCSI_LOWLEVEL is not set -+CONFIG_ATA=y -+CONFIG_SATA_AHCI_PLATFORM=y -+CONFIG_AHCI_IMX=y -+CONFIG_PATA_IMX=y -+CONFIG_NETDEVICES=y -+# CONFIG_NET_VENDOR_BROADCOM is not set -+CONFIG_CS89x0=y -+CONFIG_CS89x0_PLATFORM=y -+# CONFIG_NET_VENDOR_FARADAY is not set -+# CONFIG_NET_VENDOR_INTEL is not set -+# CONFIG_NET_VENDOR_MARVELL is not set -+# CONFIG_NET_VENDOR_MICREL is not set -+# CONFIG_NET_VENDOR_MICROCHIP is not set -+# CONFIG_NET_VENDOR_NATSEMI is not set -+# CONFIG_NET_VENDOR_SEEQ is not set -+CONFIG_SMC91X=y -+CONFIG_SMC911X=y -+CONFIG_SMSC911X=y -+# CONFIG_NET_VENDOR_STMICRO is not set -+CONFIG_USB_PEGASUS=m -+CONFIG_USB_RTL8150=m -+CONFIG_USB_RTL8152=m -+CONFIG_USB_USBNET=m -+CONFIG_USB_NET_CDC_EEM=m -+CONFIG_ATH_CARDS=y -+CONFIG_ATH6KL=m -+CONFIG_ATH6KL_SDIO=m -+CONFIG_BRCMFMAC=m -+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -+CONFIG_INPUT_EVDEV=y -+CONFIG_INPUT_EVBUG=m -+CONFIG_KEYBOARD_GPIO=y -+CONFIG_KEYBOARD_SNVS_PWRKEY=y -+CONFIG_KEYBOARD_IMX=y -+CONFIG_MOUSE_PS2=m -+CONFIG_MOUSE_PS2_ELANTECH=y -+CONFIG_INPUT_TOUCHSCREEN=y -+CONFIG_TOUCHSCREEN_EGALAX=y -+CONFIG_TOUCHSCREEN_ELAN=y -+CONFIG_TOUCHSCREEN_MAX11801=y -+CONFIG_TOUCHSCREEN_MC13783=y -+CONFIG_TOUCHSCREEN_TSC2007=y -+CONFIG_TOUCHSCREEN_STMPE=y -+CONFIG_INPUT_MISC=y -+CONFIG_INPUT_MMA8450=y -+CONFIG_INPUT_ISL29023=y -+CONFIG_SERIO_SERPORT=m -+# CONFIG_LEGACY_PTYS is not set -+# CONFIG_DEVKMEM is not set -+CONFIG_SERIAL_IMX=y -+CONFIG_SERIAL_IMX_CONSOLE=y -+CONFIG_SERIAL_FSL_LPUART=y -+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y -+CONFIG_FSL_OTP=y -+# CONFIG_I2C_COMPAT is not set -+CONFIG_I2C_CHARDEV=y -+# CONFIG_I2C_HELPER_AUTO is not set -+CONFIG_I2C_ALGOPCF=m -+CONFIG_I2C_ALGOPCA=m -+CONFIG_I2C_IMX=y -+CONFIG_SPI=y -+CONFIG_SPI_IMX=y -+CONFIG_GPIO_SYSFS=y -+CONFIG_POWER_SUPPLY=y -+CONFIG_SABRESD_MAX8903=y -+CONFIG_SENSORS_MAX17135=y -+CONFIG_SENSORS_MAG3110=y -+CONFIG_THERMAL=y -+CONFIG_CPU_THERMAL=y -+CONFIG_IMX_THERMAL=y -+CONFIG_DEVICE_THERMAL=y -+CONFIG_WATCHDOG=y -+CONFIG_IMX2_WDT=y -+CONFIG_MFD_DA9052_I2C=y -+CONFIG_MFD_MC13XXX_SPI=y -+CONFIG_MFD_MC13XXX_I2C=y -+CONFIG_MFD_MAX17135=y -+CONFIG_MFD_SI476X_CORE=y -+CONFIG_MFD_STMPE=y -+CONFIG_REGULATOR=y -+CONFIG_REGULATOR_FIXED_VOLTAGE=y -+CONFIG_REGULATOR_ANATOP=y -+CONFIG_REGULATOR_DA9052=y -+CONFIG_REGULATOR_MAX17135=y -+CONFIG_REGULATOR_MC13783=y -+CONFIG_REGULATOR_MC13892=y -+CONFIG_REGULATOR_PFUZE100=y -+CONFIG_MEDIA_SUPPORT=y -+CONFIG_MEDIA_CAMERA_SUPPORT=y -+CONFIG_MEDIA_RADIO_SUPPORT=y -+CONFIG_MEDIA_RC_SUPPORT=y -+CONFIG_RC_DEVICES=y -+CONFIG_IR_GPIO_CIR=y -+CONFIG_MEDIA_USB_SUPPORT=y -+CONFIG_USB_VIDEO_CLASS=m -+CONFIG_V4L_PLATFORM_DRIVERS=y -+CONFIG_VIDEO_MXC_OUTPUT=y -+CONFIG_VIDEO_MXC_CAPTURE=m -+CONFIG_MXC_CAMERA_OV5640=m -+CONFIG_MXC_CAMERA_OV5642=m -+CONFIG_MXC_CAMERA_OV5640_MIPI=m -+CONFIG_MXC_TVIN_ADV7180=m -+CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m -+CONFIG_VIDEO_MXC_IPU_OUTPUT=y -+CONFIG_VIDEO_MXC_PXP_V4L2=y -+CONFIG_VIDEO_MXC_CSI_CAMERA=m -+CONFIG_MXC_VADC=m -+CONFIG_SOC_CAMERA=y -+CONFIG_VIDEO_MX3=y -+CONFIG_V4L_MEM2MEM_DRIVERS=y -+CONFIG_VIDEO_CODA=y -+CONFIG_RADIO_SI476X=y -+CONFIG_SOC_CAMERA_OV2640=y -+CONFIG_DRM=y -+CONFIG_DRM_VIVANTE=y -+CONFIG_FB=y -+CONFIG_FB_MXS=y -+CONFIG_BACKLIGHT_LCD_SUPPORT=y -+CONFIG_LCD_CLASS_DEVICE=y -+CONFIG_LCD_L4F00242T03=y -+CONFIG_LCD_PLATFORM=y -+CONFIG_BACKLIGHT_CLASS_DEVICE=y -+CONFIG_BACKLIGHT_PWM=y -+CONFIG_FB_MXC_SYNC_PANEL=y -+CONFIG_FB_MXC_LDB=y -+CONFIG_FB_MXC_MIPI_DSI=y -+CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y -+CONFIG_FB_MXC_HDMI=y -+CONFIG_FB_MXC_EINK_PANEL=y -+CONFIG_FB_MXS_SII902X=y -+CONFIG_FB_MXC_DCIC=m -+CONFIG_HANNSTAR_CABC=y -+CONFIG_FRAMEBUFFER_CONSOLE=y -+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -+CONFIG_LOGO=y -+CONFIG_SOUND=y -+CONFIG_SND=y -+CONFIG_SND_USB_AUDIO=m -+CONFIG_SND_SOC=y -+CONFIG_SND_IMX_SOC=y -+CONFIG_SND_SOC_EUKREA_TLV320=y -+CONFIG_SND_SOC_IMX_CS42888=y -+CONFIG_SND_SOC_IMX_WM8962=y -+CONFIG_SND_SOC_IMX_SGTL5000=y -+CONFIG_SND_SOC_IMX_MQS=y -+CONFIG_SND_SOC_IMX_SPDIF=y -+CONFIG_SND_SOC_IMX_MC13783=y -+CONFIG_SND_SOC_IMX_HDMI=y -+CONFIG_SND_SOC_IMX_SI476X=y -+CONFIG_USB=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_MXC=y -+CONFIG_USB_ACM=m -+CONFIG_USB_STORAGE=y -+CONFIG_USB_CHIPIDEA=y -+CONFIG_USB_CHIPIDEA_UDC=y -+CONFIG_USB_CHIPIDEA_HOST=y -+CONFIG_USB_SERIAL=m -+CONFIG_USB_SERIAL_GENERIC=y -+CONFIG_USB_SERIAL_FTDI_SIO=m -+CONFIG_USB_SERIAL_OPTION=m -+CONFIG_USB_EHSET_TEST_FIXTURE=m -+CONFIG_NOP_USB_XCEIV=y -+CONFIG_USB_MXS_PHY=y -+CONFIG_USB_GADGET=y -+CONFIG_USB_CONFIGFS=m -+CONFIG_USB_CONFIGFS_SERIAL=y -+CONFIG_USB_CONFIGFS_ACM=y -+CONFIG_USB_CONFIGFS_OBEX=y -+CONFIG_USB_CONFIGFS_NCM=y -+CONFIG_USB_CONFIGFS_ECM=y -+CONFIG_USB_CONFIGFS_ECM_SUBSET=y -+CONFIG_USB_CONFIGFS_RNDIS=y -+CONFIG_USB_CONFIGFS_EEM=y -+CONFIG_USB_CONFIGFS_MASS_STORAGE=y -+CONFIG_USB_CONFIGFS_F_LB_SS=y -+CONFIG_USB_CONFIGFS_F_FS=y -+CONFIG_USB_ZERO=m -+CONFIG_USB_ETH=m -+CONFIG_USB_G_NCM=m -+CONFIG_USB_GADGETFS=m -+CONFIG_USB_MASS_STORAGE=m -+CONFIG_USB_G_SERIAL=m -+CONFIG_MMC=y -+CONFIG_MMC_UNSAFE_RESUME=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_PLTFM=y -+CONFIG_MMC_SDHCI_ESDHC_IMX=y -+CONFIG_MXC_IPU=y -+CONFIG_MXC_GPU_VIV=y -+CONFIG_MXC_MIPI_CSI2=y -+CONFIG_MXC_MLB150=m -+CONFIG_NEW_LEDS=y -+CONFIG_LEDS_CLASS=y -+CONFIG_LEDS_GPIO=y -+CONFIG_LEDS_TRIGGERS=y -+CONFIG_LEDS_TRIGGER_TIMER=y -+CONFIG_LEDS_TRIGGER_ONESHOT=y -+CONFIG_LEDS_TRIGGER_HEARTBEAT=y -+CONFIG_LEDS_TRIGGER_BACKLIGHT=y -+CONFIG_LEDS_TRIGGER_GPIO=y -+CONFIG_RTC_CLASS=y -+CONFIG_RTC_INTF_DEV_UIE_EMUL=y -+CONFIG_RTC_DRV_MC13XXX=y -+CONFIG_RTC_DRV_MXC=y -+CONFIG_RTC_DRV_SNVS=y -+CONFIG_DMADEVICES=y -+CONFIG_MXC_PXP_V2=y -+CONFIG_IMX_SDMA=y -+CONFIG_MXS_DMA=y -+CONFIG_STAGING=y -+CONFIG_STAGING_MEDIA=y -+# CONFIG_IOMMU_SUPPORT is not set -+CONFIG_IIO=y -+CONFIG_VF610_ADC=y -+CONFIG_PWM=y -+CONFIG_PWM_IMX=y -+CONFIG_EXT2_FS=y -+CONFIG_EXT2_FS_XATTR=y -+CONFIG_EXT2_FS_POSIX_ACL=y -+CONFIG_EXT2_FS_SECURITY=y -+CONFIG_EXT3_FS=y -+CONFIG_EXT3_FS_POSIX_ACL=y -+CONFIG_EXT3_FS_SECURITY=y -+CONFIG_EXT4_FS=y -+CONFIG_EXT4_FS_POSIX_ACL=y -+CONFIG_EXT4_FS_SECURITY=y -+CONFIG_QUOTA=y -+CONFIG_QUOTA_NETLINK_INTERFACE=y -+# CONFIG_PRINT_QUOTA_WARNING is not set -+CONFIG_AUTOFS4_FS=y -+CONFIG_FUSE_FS=y -+CONFIG_ISO9660_FS=m -+CONFIG_JOLIET=y -+CONFIG_ZISOFS=y -+CONFIG_UDF_FS=m -+CONFIG_MSDOS_FS=m -+CONFIG_VFAT_FS=y -+CONFIG_TMPFS=y -+CONFIG_JFFS2_FS=y -+CONFIG_UBIFS_FS=y -+CONFIG_NFS_FS=y -+CONFIG_NFS_V3_ACL=y -+CONFIG_NFS_V4=y -+CONFIG_ROOT_NFS=y -+CONFIG_NLS_DEFAULT="cp437" -+CONFIG_NLS_CODEPAGE_437=y -+CONFIG_NLS_ASCII=y -+CONFIG_NLS_ISO8859_1=y -+CONFIG_NLS_ISO8859_15=m -+CONFIG_NLS_UTF8=y -+CONFIG_DEBUG_FS=y -+CONFIG_MAGIC_SYSRQ=y -+# CONFIG_SCHED_DEBUG is not set -+# CONFIG_DEBUG_BUGVERBOSE is not set -+# CONFIG_FTRACE is not set -+CONFIG_SECURITYFS=y -+CONFIG_CRYPTO_USER=y -+CONFIG_CRYPTO_TEST=m -+CONFIG_CRYPTO_GCM=y -+CONFIG_CRYPTO_CBC=y -+CONFIG_CRYPTO_CTS=y -+CONFIG_CRYPTO_LRW=y -+CONFIG_CRYPTO_XTS=y -+CONFIG_CRYPTO_MD4=y -+CONFIG_CRYPTO_MD5=y -+CONFIG_CRYPTO_MICHAEL_MIC=y -+CONFIG_CRYPTO_RMD128=y -+CONFIG_CRYPTO_RMD160=y -+CONFIG_CRYPTO_RMD256=y -+CONFIG_CRYPTO_RMD320=y -+CONFIG_CRYPTO_SHA1=y -+CONFIG_CRYPTO_SHA512=y -+CONFIG_CRYPTO_TGR192=y -+CONFIG_CRYPTO_WP512=y -+CONFIG_CRYPTO_BLOWFISH=y -+CONFIG_CRYPTO_CAMELLIA=y -+CONFIG_CRYPTO_DES=y -+CONFIG_CRYPTO_TWOFISH=y -+# CONFIG_CRYPTO_ANSI_CPRNG is not set -+CONFIG_CRYPTO_DEV_FSL_CAAM=y -+CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y -+CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=y -+CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y -+CONFIG_CRC_CCITT=m -+CONFIG_CRC_T10DIF=y -+CONFIG_CRC7=m -+CONFIG_LIBCRC32C=m -+CONFIG_FONTS=y -+CONFIG_FONT_8x8=y -+CONFIG_FONT_8x16=y -diff -Nur linux-4.1.13.orig/arch/arm/configs/imx_v7_mfg_defconfig linux-4.1.13/arch/arm/configs/imx_v7_mfg_defconfig ---- linux-4.1.13.orig/arch/arm/configs/imx_v7_mfg_defconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/arch/arm/configs/imx_v7_mfg_defconfig 2015-11-30 17:56:13.528141189 +0100 -@@ -0,0 +1,332 @@ -+# CONFIG_LOCALVERSION_AUTO is not set -+CONFIG_KERNEL_LZO=y -+CONFIG_SYSVIPC=y -+CONFIG_NO_HZ=y -+CONFIG_HIGH_RES_TIMERS=y -+CONFIG_LOG_BUF_SHIFT=18 -+CONFIG_CGROUPS=y -+CONFIG_RELAY=y -+CONFIG_BLK_DEV_INITRD=y -+CONFIG_EXPERT=y -+CONFIG_KALLSYMS_ALL=y -+CONFIG_PERF_EVENTS=y -+# CONFIG_SLUB_DEBUG is not set -+# CONFIG_COMPAT_BRK is not set -+CONFIG_MODULES=y -+CONFIG_MODULE_UNLOAD=y -+CONFIG_MODVERSIONS=y -+CONFIG_MODULE_SRCVERSION_ALL=y -+# CONFIG_BLK_DEV_BSG is not set -+CONFIG_ARCH_MULTI_V6=y -+CONFIG_GPIO_PCA953X=y -+CONFIG_ARCH_MXC=y -+# CONFIG_MACH_MX31ADS is not set -+# CONFIG_MACH_BUG is not set -+CONFIG_MACH_IMX51_DT=y -+CONFIG_MACH_EUKREA_CPUIMX51SD=y -+CONFIG_SOC_IMX50=y -+CONFIG_SOC_IMX53=y -+CONFIG_SOC_IMX6Q=y -+CONFIG_SOC_IMX6SL=y -+CONFIG_SOC_IMX6SX=y -+CONFIG_SOC_VF610=y -+CONFIG_SMP=y -+CONFIG_VMSPLIT_2G=y -+CONFIG_PREEMPT=y -+CONFIG_AEABI=y -+CONFIG_HIGHMEM=y -+CONFIG_CMA=y -+CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" -+CONFIG_CPU_FREQ=y -+CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y -+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -+CONFIG_CPU_FREQ_GOV_POWERSAVE=y -+CONFIG_CPU_FREQ_GOV_USERSPACE=y -+CONFIG_CPU_FREQ_GOV_ONDEMAND=y -+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -+CONFIG_ARM_IMX6Q_CPUFREQ=y -+CONFIG_CPU_IDLE=y -+CONFIG_VFP=y -+CONFIG_NEON=y -+CONFIG_BINFMT_MISC=m -+CONFIG_PM_RUNTIME=y -+CONFIG_PM_DEBUG=y -+CONFIG_PM_TEST_SUSPEND=y -+CONFIG_NET=y -+CONFIG_PACKET=y -+CONFIG_UNIX=y -+CONFIG_INET=y -+CONFIG_IP_PNP=y -+CONFIG_IP_PNP_DHCP=y -+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -+# CONFIG_INET_XFRM_MODE_TUNNEL is not set -+# CONFIG_INET_XFRM_MODE_BEET is not set -+# CONFIG_INET_LRO is not set -+CONFIG_IPV6=y -+CONFIG_NETFILTER=y -+CONFIG_CFG80211=y -+CONFIG_MAC80211=y -+CONFIG_RFKILL=y -+CONFIG_RFKILL_INPUT=y -+CONFIG_DEVTMPFS=y -+CONFIG_DEVTMPFS_MOUNT=y -+# CONFIG_STANDALONE is not set -+CONFIG_DMA_CMA=y -+CONFIG_CMA_SIZE_MBYTES=320 -+CONFIG_IMX_WEIM=y -+CONFIG_CONNECTOR=y -+CONFIG_MTD=y -+CONFIG_MTD_CMDLINE_PARTS=y -+CONFIG_MTD_BLOCK=y -+CONFIG_MTD_CFI=y -+CONFIG_MTD_JEDECPROBE=y -+CONFIG_MTD_CFI_INTELEXT=y -+CONFIG_MTD_CFI_AMDSTD=y -+CONFIG_MTD_CFI_STAA=y -+CONFIG_MTD_PHYSMAP_OF=y -+CONFIG_MTD_DATAFLASH=y -+CONFIG_MTD_M25P80=y -+CONFIG_MTD_SST25L=y -+CONFIG_MTD_NAND=y -+CONFIG_MTD_NAND_GPMI_NAND=y -+CONFIG_MTD_NAND_MXC=y -+CONFIG_MTD_SPI_NOR=y -+CONFIG_SPI_FSL_QUADSPI=y -+CONFIG_MTD_UBI=y -+CONFIG_BLK_DEV_LOOP=y -+CONFIG_BLK_DEV_RAM=y -+CONFIG_BLK_DEV_RAM_SIZE=65536 -+CONFIG_EEPROM_AT24=y -+CONFIG_EEPROM_AT25=y -+# CONFIG_SCSI_PROC_FS is not set -+CONFIG_BLK_DEV_SD=y -+CONFIG_SCSI_MULTI_LUN=y -+CONFIG_SCSI_CONSTANTS=y -+CONFIG_SCSI_LOGGING=y -+CONFIG_SCSI_SCAN_ASYNC=y -+# CONFIG_SCSI_LOWLEVEL is not set -+CONFIG_ATA=y -+CONFIG_SATA_AHCI_PLATFORM=y -+CONFIG_AHCI_IMX=y -+CONFIG_PATA_IMX=y -+CONFIG_NETDEVICES=y -+# CONFIG_NET_VENDOR_BROADCOM is not set -+CONFIG_CS89x0=y -+CONFIG_CS89x0_PLATFORM=y -+# CONFIG_NET_VENDOR_FARADAY is not set -+# CONFIG_NET_VENDOR_INTEL is not set -+# CONFIG_NET_VENDOR_MARVELL is not set -+# CONFIG_NET_VENDOR_MICREL is not set -+# CONFIG_NET_VENDOR_MICROCHIP is not set -+# CONFIG_NET_VENDOR_NATSEMI is not set -+# CONFIG_NET_VENDOR_SEEQ is not set -+CONFIG_SMC91X=y -+CONFIG_SMC911X=y -+CONFIG_SMSC911X=y -+# CONFIG_NET_VENDOR_STMICRO is not set -+CONFIG_AT803X_PHY=y -+CONFIG_BRCMFMAC=m -+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -+CONFIG_INPUT_EVDEV=y -+CONFIG_INPUT_EVBUG=m -+CONFIG_KEYBOARD_GPIO=y -+CONFIG_KEYBOARD_IMX=y -+CONFIG_MOUSE_PS2=m -+CONFIG_MOUSE_PS2_ELANTECH=y -+CONFIG_INPUT_TOUCHSCREEN=y -+CONFIG_TOUCHSCREEN_EGALAX=y -+CONFIG_TOUCHSCREEN_MC13783=y -+CONFIG_TOUCHSCREEN_TSC2007=y -+CONFIG_TOUCHSCREEN_STMPE=y -+CONFIG_INPUT_MISC=y -+CONFIG_INPUT_MMA8450=y -+CONFIG_SERIO_SERPORT=m -+# CONFIG_LEGACY_PTYS is not set -+# CONFIG_DEVKMEM is not set -+CONFIG_SERIAL_IMX=y -+CONFIG_SERIAL_IMX_CONSOLE=y -+CONFIG_SERIAL_FSL_LPUART=y -+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y -+CONFIG_HW_RANDOM=y -+CONFIG_IMX_SEMA4=y -+# CONFIG_I2C_COMPAT is not set -+CONFIG_I2C_CHARDEV=y -+# CONFIG_I2C_HELPER_AUTO is not set -+CONFIG_I2C_ALGOPCF=m -+CONFIG_I2C_ALGOPCA=m -+CONFIG_I2C_IMX=y -+CONFIG_SPI=y -+CONFIG_SPI_IMX=y -+CONFIG_GPIO_SYSFS=y -+# CONFIG_HWMON is not set -+CONFIG_THERMAL=y -+CONFIG_CPU_THERMAL=y -+CONFIG_IMX_THERMAL=y -+CONFIG_DEVICE_THERMAL=y -+CONFIG_WATCHDOG=y -+CONFIG_IMX2_WDT=y -+CONFIG_MFD_DA9052_I2C=y -+CONFIG_MFD_MC13XXX_SPI=y -+CONFIG_MFD_MC13XXX_I2C=y -+CONFIG_MFD_STMPE=y -+CONFIG_REGULATOR=y -+CONFIG_REGULATOR_FIXED_VOLTAGE=y -+CONFIG_REGULATOR_ANATOP=y -+CONFIG_REGULATOR_DA9052=y -+CONFIG_REGULATOR_MC13783=y -+CONFIG_REGULATOR_MC13892=y -+CONFIG_REGULATOR_PFUZE100=y -+CONFIG_MEDIA_SUPPORT=y -+CONFIG_MEDIA_CAMERA_SUPPORT=y -+CONFIG_MEDIA_RC_SUPPORT=y -+CONFIG_RC_DEVICES=y -+CONFIG_IR_GPIO_CIR=y -+CONFIG_V4L_PLATFORM_DRIVERS=y -+CONFIG_VIDEO_MXC_OUTPUT=y -+CONFIG_VIDEO_MXC_IPU_OUTPUT=y -+CONFIG_VIDEO_MXC_PXP_V4L2=y -+CONFIG_SOC_CAMERA=y -+CONFIG_VIDEO_MX3=y -+CONFIG_V4L_MEM2MEM_DRIVERS=y -+CONFIG_VIDEO_CODA=y -+CONFIG_SOC_CAMERA_OV2640=y -+CONFIG_DRM=y -+CONFIG_DRM_VIVANTE=y -+CONFIG_FB=y -+CONFIG_FB_MXS=y -+CONFIG_BACKLIGHT_LCD_SUPPORT=y -+CONFIG_LCD_CLASS_DEVICE=y -+CONFIG_LCD_L4F00242T03=y -+CONFIG_LCD_PLATFORM=y -+CONFIG_BACKLIGHT_CLASS_DEVICE=y -+CONFIG_BACKLIGHT_PWM=y -+CONFIG_FB_MXC_SYNC_PANEL=y -+CONFIG_FB_MXC_LDB=y -+CONFIG_FB_MXC_MIPI_DSI=y -+CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y -+CONFIG_FB_MXC_HDMI=y -+CONFIG_FB_MXC_EINK_PANEL=y -+CONFIG_FB_MXC_EINK_AUTO_UPDATE_MODE=y -+CONFIG_FB_MXS_SII902X=y -+CONFIG_HANNSTAR_CABC=y -+CONFIG_FRAMEBUFFER_CONSOLE=y -+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -+CONFIG_LOGO=y -+CONFIG_SOUND=y -+CONFIG_SND=y -+CONFIG_SND_SOC=y -+CONFIG_SND_IMX_SOC=y -+CONFIG_SND_SOC_EUKREA_TLV320=y -+CONFIG_SND_SOC_IMX_WM8962=y -+CONFIG_SND_SOC_IMX_SGTL5000=y -+CONFIG_SND_SOC_IMX_SPDIF=y -+CONFIG_SND_SOC_IMX_MC13783=y -+CONFIG_USB=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_MXC=y -+CONFIG_USB_STORAGE=y -+CONFIG_USB_CHIPIDEA=y -+CONFIG_USB_CHIPIDEA_UDC=y -+CONFIG_USB_CHIPIDEA_HOST=y -+CONFIG_NOP_USB_XCEIV=y -+CONFIG_USB_MXS_PHY=y -+CONFIG_USB_GADGET=y -+CONFIG_USB_ETH=m -+CONFIG_USB_PHY=y -+# CONFIG_USB_ZERO is not set -+# CONFIG_USB_AUDIO is not set -+# CONFIG_USB_ETH is not set -+# CONFIG_USB_G_NCM is not set -+# CONFIG_USB_GADGETFS is not set -+# CONFIG_USB_FUNCTIONFS is not set -+CONFIG_USB_MASS_STORAGE=y -+CONFIG_FSL_UTP=y -+# CONFIG_USB_G_SERIAL is not set -+# CONFIG_USB_MIDI_GADGET is not set -+# CONFIG_USB_G_PRINTER is not set -+# CONFIG_USB_CDC_COMPOSITE is not set -+# CONFIG_USB_G_ACM_MS is not set -+# CONFIG_USB_G_MULTI is not set -+# CONFIG_USB_G_HID is not set -+# CONFIG_USB_G_DBGP is not set -+# CONFIG_USB_G_WEBCAM is not set -+CONFIG_MMC=y -+CONFIG_MMC_UNSAFE_RESUME=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_PLTFM=y -+CONFIG_MMC_SDHCI_ESDHC_IMX=y -+CONFIG_MXC_IPU=y -+CONFIG_MXC_GPU_VIV=y -+CONFIG_MXC_MIPI_CSI2=y -+CONFIG_MXC_MLB150=y -+CONFIG_NEW_LEDS=y -+CONFIG_LEDS_CLASS=y -+CONFIG_LEDS_GPIO=y -+CONFIG_LEDS_TRIGGERS=y -+CONFIG_LEDS_TRIGGER_TIMER=y -+CONFIG_LEDS_TRIGGER_ONESHOT=y -+CONFIG_LEDS_TRIGGER_HEARTBEAT=y -+CONFIG_LEDS_TRIGGER_BACKLIGHT=y -+CONFIG_LEDS_TRIGGER_GPIO=y -+CONFIG_RTC_CLASS=y -+CONFIG_RTC_INTF_DEV_UIE_EMUL=y -+CONFIG_RTC_DRV_MC13XXX=y -+CONFIG_RTC_DRV_MXC=y -+CONFIG_RTC_DRV_SNVS=y -+CONFIG_DMADEVICES=y -+CONFIG_MXC_PXP_V2=y -+CONFIG_IMX_SDMA=y -+CONFIG_MXS_DMA=y -+CONFIG_STAGING=y -+CONFIG_STAGING_MEDIA=y -+# CONFIG_IOMMU_SUPPORT is not set -+CONFIG_PWM=y -+CONFIG_PWM_IMX=y -+CONFIG_EXT2_FS=y -+CONFIG_EXT2_FS_XATTR=y -+CONFIG_EXT2_FS_POSIX_ACL=y -+CONFIG_EXT2_FS_SECURITY=y -+CONFIG_EXT3_FS=y -+CONFIG_EXT3_FS_POSIX_ACL=y -+CONFIG_EXT3_FS_SECURITY=y -+CONFIG_EXT4_FS=y -+CONFIG_EXT4_FS_POSIX_ACL=y -+CONFIG_EXT4_FS_SECURITY=y -+CONFIG_QUOTA=y -+CONFIG_QUOTA_NETLINK_INTERFACE=y -+# CONFIG_PRINT_QUOTA_WARNING is not set -+CONFIG_AUTOFS4_FS=y -+CONFIG_FUSE_FS=y -+CONFIG_ISO9660_FS=m -+CONFIG_JOLIET=y -+CONFIG_ZISOFS=y -+CONFIG_UDF_FS=m -+CONFIG_MSDOS_FS=m -+CONFIG_VFAT_FS=y -+CONFIG_TMPFS=y -+CONFIG_JFFS2_FS=y -+CONFIG_UBIFS_FS=y -+CONFIG_NFS_FS=y -+CONFIG_NFS_V3_ACL=y -+CONFIG_NFS_V4=y -+CONFIG_ROOT_NFS=y -+CONFIG_NLS_DEFAULT="cp437" -+CONFIG_NLS_CODEPAGE_437=y -+CONFIG_NLS_ASCII=y -+CONFIG_NLS_ISO8859_1=y -+CONFIG_NLS_ISO8859_15=m -+CONFIG_NLS_UTF8=y -+CONFIG_MAGIC_SYSRQ=y -+# CONFIG_SCHED_DEBUG is not set -+# CONFIG_DEBUG_BUGVERBOSE is not set -+# CONFIG_FTRACE is not set -+CONFIG_SECURITYFS=y -+# CONFIG_CRYPTO_ANSI_CPRNG is not set -+# CONFIG_CRYPTO_HW is not set -+CONFIG_CRC_CCITT=m -+CONFIG_CRC_T10DIF=y -+CONFIG_CRC7=m -+CONFIG_LIBCRC32C=m -+CONFIG_FONTS=y -+CONFIG_FONT_8x8=y -+CONFIG_FONT_8x16=y -diff -Nur linux-4.1.13.orig/arch/arm/include/asm/glue-cache.h linux-4.1.13/arch/arm/include/asm/glue-cache.h ---- linux-4.1.13.orig/arch/arm/include/asm/glue-cache.h 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/include/asm/glue-cache.h 2015-11-30 17:56:13.528141189 +0100 -@@ -102,19 +102,19 @@ - #endif - - #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) --# ifdef _CACHE -+//# ifdef _CACHE - # define MULTI_CACHE 1 --# else --# define _CACHE v6 --# endif -+//# else -+//# define _CACHE v6 -+//# endif - #endif - - #if defined(CONFIG_CPU_V7) --# ifdef _CACHE -+//# ifdef _CACHE - # define MULTI_CACHE 1 --# else --# define _CACHE v7 --# endif -+//# else -+//# define _CACHE v7 -+//# endif - #endif - - #if defined(CONFIG_CPU_V7M) -diff -Nur linux-4.1.13.orig/arch/arm/Kconfig linux-4.1.13/arch/arm/Kconfig ---- linux-4.1.13.orig/arch/arm/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/Kconfig 2015-11-30 17:56:13.528141189 +0100 -@@ -1689,6 +1689,7 @@ - range 11 64 if ARCH_SHMOBILE_LEGACY - default "12" if SOC_AM33XX - default "9" if SA1111 || ARCH_EFM32 -+ default "14" if ARCH_MXC - default "11" - help - The kernel memory allocator divides physically contiguous memory -diff -Nur linux-4.1.13.orig/arch/arm/mach-imx/busfreq_ddr3.c linux-4.1.13/arch/arm/mach-imx/busfreq_ddr3.c ---- linux-4.1.13.orig/arch/arm/mach-imx/busfreq_ddr3.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/arch/arm/mach-imx/busfreq_ddr3.c 2015-11-30 17:56:13.528141189 +0100 -@@ -0,0 +1,519 @@ -+/* -+ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved. -+ */ -+ -+/* -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/*! -+ * @file busfreq_ddr3.c -+ * -+ * @brief iMX6 DDR3 frequency change specific file. -+ * -+ * @ingroup PM -+ */ -+#define DEBUG -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "hardware.h" -+ -+/* DDR settings */ -+static unsigned long (*iram_ddr_settings)[2]; -+static unsigned long (*normal_mmdc_settings)[2]; -+static unsigned long (*iram_iomux_settings)[2]; -+ -+static void __iomem *mmdc_base; -+static void __iomem *iomux_base; -+static void __iomem *ccm_base; -+static void __iomem *l2_base; -+static void __iomem *gic_dist_base; -+static u32 *irqs_used; -+ -+static void *ddr_freq_change_iram_base; -+static int ddr_settings_size; -+static int iomux_settings_size; -+static volatile unsigned int cpus_in_wfe; -+static volatile bool wait_for_ddr_freq_update; -+static int curr_ddr_rate; -+ -+void (*mx6_change_ddr_freq)(u32 freq, void *ddr_settings, -+ bool dll_mode, void *iomux_offsets) = NULL; -+ -+extern unsigned int ddr_med_rate; -+extern unsigned int ddr_normal_rate; -+extern int low_bus_freq_mode; -+extern int audio_bus_freq_mode; -+extern void mx6_ddr3_freq_change(u32 freq, void *ddr_settings, -+ bool dll_mode, void *iomux_offsets); -+extern unsigned long save_ttbr1(void); -+extern void restore_ttbr1(unsigned long ttbr1); -+ -+#ifdef CONFIG_SMP -+extern void __iomem *imx_scu_base; -+static unsigned int online_cpus; -+#endif -+ -+#define MIN_DLL_ON_FREQ 333000000 -+#define MAX_DLL_OFF_FREQ 125000000 -+#define DDR_FREQ_CHANGE_SIZE 0x2000 -+ -+unsigned long ddr3_dll_mx6q[][2] = { -+ {0x0c, 0x0}, -+ {0x10, 0x0}, -+ {0x1C, 0x04088032}, -+ {0x1C, 0x0408803a}, -+ {0x1C, 0x08408030}, -+ {0x1C, 0x08408038}, -+ {0x818, 0x0}, -+}; -+ -+unsigned long ddr3_calibration[][2] = { -+ {0x83c, 0x0}, -+ {0x840, 0x0}, -+ {0x483c, 0x0}, -+ {0x4840, 0x0}, -+ {0x848, 0x0}, -+ {0x4848, 0x0}, -+ {0x850, 0x0}, -+ {0x4850, 0x0}, -+}; -+ -+unsigned long ddr3_dll_mx6dl[][2] = { -+ {0x0c, 0x0}, -+ {0x10, 0x0}, -+ {0x1C, 0x04008032}, -+ {0x1C, 0x0400803a}, -+ {0x1C, 0x07208030}, -+ {0x1C, 0x07208038}, -+ {0x818, 0x0}, -+}; -+ -+unsigned long iomux_offsets_mx6q[][2] = { -+ {0x5A8, 0x0}, -+ {0x5B0, 0x0}, -+ {0x524, 0x0}, -+ {0x51C, 0x0}, -+ {0x518, 0x0}, -+ {0x50C, 0x0}, -+ {0x5B8, 0x0}, -+ {0x5C0, 0x0}, -+}; -+ -+unsigned long iomux_offsets_mx6dl[][2] = { -+ {0x4BC, 0x0}, -+ {0x4C0, 0x0}, -+ {0x4C4, 0x0}, -+ {0x4C8, 0x0}, -+ {0x4CC, 0x0}, -+ {0x4D0, 0x0}, -+ {0x4D4, 0x0}, -+ {0x4D8, 0x0}, -+}; -+ -+unsigned long ddr3_400[][2] = { -+ {0x83c, 0x42490249}, -+ {0x840, 0x02470247}, -+ {0x483c, 0x42570257}, -+ {0x4840, 0x02400240}, -+ {0x848, 0x4039363C}, -+ {0x4848, 0x3A39333F}, -+ {0x850, 0x38414441}, -+ {0x4850, 0x472D4833} -+}; -+ -+int can_change_ddr_freq(void) -+{ -+ return 0; -+} -+ -+/* -+ * each active core apart from the one changing -+ * the DDR frequency will execute this function. -+ * the rest of the cores have to remain in WFE -+ * state until the frequency is changed. -+ */ -+irqreturn_t wait_in_wfe_irq(int irq, void *dev_id) -+{ -+ u32 me = smp_processor_id(); -+ -+ *((char *)(&cpus_in_wfe) + (u8)me) = 0xff; -+ -+ while (wait_for_ddr_freq_update) -+ wfe(); -+ -+ *((char *)(&cpus_in_wfe) + (u8)me) = 0; -+ -+ return IRQ_HANDLED; -+} -+ -+/* change the DDR frequency. */ -+int update_ddr_freq(int ddr_rate) -+{ -+ int i, j; -+ bool dll_off = false; -+ int me = 0; -+ unsigned long ttbr1; -+#ifdef CONFIG_SMP -+ unsigned int reg; -+ int cpu = 0; -+#endif -+ -+ if (!can_change_ddr_freq()) -+ return -1; -+ -+ if (ddr_rate == curr_ddr_rate) -+ return 0; -+ -+ pr_debug("Bus freq set to %d start...\n", ddr_rate); -+ -+ if (low_bus_freq_mode || audio_bus_freq_mode) -+ dll_off = true; -+ -+ iram_ddr_settings[0][0] = ddr_settings_size; -+ iram_iomux_settings[0][0] = iomux_settings_size; -+ if (ddr_rate == ddr_med_rate && cpu_is_imx6q() && -+ ddr_med_rate != ddr_normal_rate) { -+ for (i = 0; i < ARRAY_SIZE(ddr3_dll_mx6q); i++) { -+ iram_ddr_settings[i + 1][0] = -+ normal_mmdc_settings[i][0]; -+ iram_ddr_settings[i + 1][1] = -+ normal_mmdc_settings[i][1]; -+ } -+ for (j = 0, i = ARRAY_SIZE(ddr3_dll_mx6q); -+ i < iram_ddr_settings[0][0]; j++, i++) { -+ iram_ddr_settings[i + 1][0] = -+ ddr3_400[j][0]; -+ iram_ddr_settings[i + 1][1] = -+ ddr3_400[j][1]; -+ } -+ } else if (ddr_rate == ddr_normal_rate) { -+ for (i = 0; i < iram_ddr_settings[0][0]; i++) { -+ iram_ddr_settings[i + 1][0] = -+ normal_mmdc_settings[i][0]; -+ iram_ddr_settings[i + 1][1] = -+ normal_mmdc_settings[i][1]; -+ } -+ } -+ -+ /* ensure that all Cores are in WFE. */ -+ local_irq_disable(); -+ -+#ifdef CONFIG_SMP -+ me = smp_processor_id(); -+ -+ /* Make sure all the online cores are active */ -+ while (1) { -+ bool not_exited_busfreq = false; -+ for_each_online_cpu(cpu) { -+ u32 reg = __raw_readl(imx_scu_base + 0x08); -+ if (reg & (0x02 << (cpu * 8))) -+ not_exited_busfreq = true; -+ } -+ if (!not_exited_busfreq) -+ break; -+ } -+ -+ wmb(); -+ wait_for_ddr_freq_update = 1; -+ dsb(); -+ -+ online_cpus = readl_relaxed(imx_scu_base + 0x08); -+ for_each_online_cpu(cpu) { -+ *((char *)(&online_cpus) + (u8)cpu) = 0x02; -+ if (cpu != me) { -+ /* set the interrupt to be pending in the GIC. */ -+ reg = 1 << (irqs_used[cpu] % 32); -+ writel_relaxed(reg, gic_dist_base + GIC_DIST_PENDING_SET -+ + (irqs_used[cpu] / 32) * 4); -+ } -+ } -+ /* Wait for the other active CPUs to idle */ -+ while (1) { -+ u32 reg = readl_relaxed(imx_scu_base + 0x08); -+ reg |= (0x02 << (me * 8)); -+ if (reg == online_cpus) -+ break; -+ } -+#endif -+ -+ /* Ensure iram_tlb_phys_addr is flushed to DDR. */ -+ /*__cpuc_flush_dcache_area(&iram_tlb_phys_addr, sizeof(iram_tlb_phys_addr)); -+ outer_clean_range(virt_to_phys(&iram_tlb_phys_addr), virt_to_phys(&iram_tlb_phys_addr + 1));*/ -+ -+ /* -+ * Flush the TLB, to ensure no TLB maintenance occurs -+ * when DDR is in self-refresh. -+ */ -+ local_flush_tlb_all(); -+ -+ ttbr1 = save_ttbr1(); -+ /* Now we can change the DDR frequency. */ -+ mx6_change_ddr_freq(ddr_rate, iram_ddr_settings, -+ dll_off, iram_iomux_settings); -+ restore_ttbr1(ttbr1); -+ curr_ddr_rate = ddr_rate; -+ -+#ifdef CONFIG_SMP -+ wmb(); -+ /* DDR frequency change is done . */ -+ wait_for_ddr_freq_update = 0; -+ dsb(); -+ -+ /* wake up all the cores. */ -+ sev(); -+#endif -+ -+ local_irq_enable(); -+ -+ pr_debug("Bus freq set to %d done! cpu=%d\n", ddr_rate, me); -+ -+ return 0; -+} -+ -+int init_mmdc_ddr3_settings(struct platform_device *busfreq_pdev) -+{ -+ struct device *dev = &busfreq_pdev->dev; -+ struct platform_device *ocram_dev; -+ unsigned int iram_paddr; -+ int i, err; -+ u32 cpu; -+ struct device_node *node; -+ struct gen_pool *iram_pool; -+ void *iram_addr; -+ -+ node = of_find_compatible_node(NULL, NULL, "fsl,imx6q-mmdc-combine"); -+ if (!node) { -+ pr_err("failed to find imx6q-mmdc device tree data!\n"); -+ return -EINVAL; -+ } -+ mmdc_base = of_iomap(node, 0); -+ WARN(!mmdc_base, "unable to map mmdc registers\n"); -+ -+ node = NULL; -+ if (cpu_is_imx6q()) -+ node = of_find_compatible_node(NULL, NULL, "fsl,imx6q-iomuxc"); -+ if (cpu_is_imx6dl()) -+ node = of_find_compatible_node(NULL, NULL, -+ "fsl,imx6dl-iomuxc"); -+ if (!node) { -+ pr_err("failed to find imx6q-iomux device tree data!\n"); -+ return -EINVAL; -+ } -+ iomux_base = of_iomap(node, 0); -+ WARN(!iomux_base, "unable to map iomux registers\n"); -+ -+ node = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ccm"); -+ if (!node) { -+ pr_err("failed to find imx6q-ccm device tree data!\n"); -+ return -EINVAL; -+ } -+ ccm_base = of_iomap(node, 0); -+ WARN(!ccm_base, "unable to map mmdc registers\n"); -+ -+ node = of_find_compatible_node(NULL, NULL, "arm,pl310-cache"); -+ if (!node) { -+ pr_err("failed to find imx6q-pl310-cache device tree data!\n"); -+ return -EINVAL; -+ } -+ l2_base = of_iomap(node, 0); -+ WARN(!ccm_base, "unable to map mmdc registers\n"); -+ -+ node = NULL; -+ node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic"); -+ if (!node) { -+ pr_err("failed to find imx6q-a9-gic device tree data!\n"); -+ return -EINVAL; -+ } -+ gic_dist_base = of_iomap(node, 0); -+ WARN(!gic_dist_base, "unable to map gic dist registers\n"); -+ -+ if (cpu_is_imx6q()) -+ ddr_settings_size = ARRAY_SIZE(ddr3_dll_mx6q) + -+ ARRAY_SIZE(ddr3_calibration); -+ if (cpu_is_imx6dl()) -+ ddr_settings_size = ARRAY_SIZE(ddr3_dll_mx6dl) + -+ ARRAY_SIZE(ddr3_calibration); -+ -+ normal_mmdc_settings = kmalloc((ddr_settings_size * 8), GFP_KERNEL); -+ if (cpu_is_imx6q()) { -+ memcpy(normal_mmdc_settings, ddr3_dll_mx6q, -+ sizeof(ddr3_dll_mx6q)); -+ memcpy(((char *)normal_mmdc_settings + sizeof(ddr3_dll_mx6q)), -+ ddr3_calibration, sizeof(ddr3_calibration)); -+ } -+ if (cpu_is_imx6dl()) { -+ memcpy(normal_mmdc_settings, ddr3_dll_mx6dl, -+ sizeof(ddr3_dll_mx6dl)); -+ memcpy(((char *)normal_mmdc_settings + sizeof(ddr3_dll_mx6dl)), -+ ddr3_calibration, sizeof(ddr3_calibration)); -+ } -+ /* store the original DDR settings at boot. */ -+ for (i = 0; i < ddr_settings_size; i++) { -+ /* -+ * writes via command mode register cannot be read back. -+ * hence hardcode them in the initial static array. -+ * this may require modification on a per customer basis. -+ */ -+ if (normal_mmdc_settings[i][0] != 0x1C) -+ normal_mmdc_settings[i][1] = -+ readl_relaxed(mmdc_base -+ + normal_mmdc_settings[i][0]); -+ } -+ -+ irqs_used = devm_kzalloc(dev, sizeof(u32) * num_present_cpus(), -+ GFP_KERNEL); -+ -+ for_each_online_cpu(cpu) { -+ int irq; -+ -+ /* -+ * set up a reserved interrupt to get all -+ * the active cores into a WFE state -+ * before changing the DDR frequency. -+ */ -+ irq = platform_get_irq(busfreq_pdev, cpu); -+ err = request_irq(irq, wait_in_wfe_irq, -+ IRQF_PERCPU, "mmdc_1", NULL); -+ if (err) { -+ dev_err(dev, -+ "Busfreq:request_irq failed %d, err = %d\n", -+ irq, err); -+ return err; -+ } -+ err = irq_set_affinity(irq, cpumask_of(cpu)); -+ if (err) { -+ dev_err(dev, -+ "Busfreq: Cannot set irq affinity irq=%d,\n", -+ irq); -+ return err; -+ } -+ irqs_used[cpu] = irq; -+ } -+ -+ node = NULL; -+ node = of_find_compatible_node(NULL, NULL, "mmio-sram"); -+ if (!node) { -+ dev_err(dev, "%s: failed to find ocram node\n", -+ __func__); -+ return -EINVAL; -+ } -+ -+ ocram_dev = of_find_device_by_node(node); -+ if (!ocram_dev) { -+ dev_err(dev, "failed to find ocram device!\n"); -+ return -EINVAL; -+ } -+ -+ iram_pool = dev_get_gen_pool(&ocram_dev->dev); -+ if (!iram_pool) { -+ dev_err(dev, "iram pool unavailable!\n"); -+ return -EINVAL; -+ } -+ -+ iomux_settings_size = ARRAY_SIZE(iomux_offsets_mx6q); -+ iram_addr = (void *)gen_pool_alloc(iram_pool, -+ (iomux_settings_size * 8) + 8); -+ iram_iomux_settings = iram_addr; -+ if (!iram_iomux_settings) { -+ dev_err(dev, "unable to alloc iram for IOMUX settings!\n"); -+ return -ENOMEM; -+ } -+ -+ /* -+ * Allocate extra space to store the number of entries in the -+ * ddr_settings plus 4 extra regsiter information that needs -+ * to be passed to the frequency change code. -+ * sizeof(iram_ddr_settings) = sizeof(ddr_settings) + -+ * entries in ddr_settings + 16. -+ * The last 4 enties store the addresses of the registers: -+ * CCM_BASE_ADDR -+ * MMDC_BASE_ADDR -+ * IOMUX_BASE_ADDR -+ * L2X0_BASE_ADDR -+ */ -+ iram_addr = (void *)gen_pool_alloc(iram_pool, -+ (ddr_settings_size * 8) + 8 + 32); -+ iram_ddr_settings = iram_addr; -+ if (!iram_ddr_settings) { -+ dev_err(dev, "unable to alloc iram for ddr settings!\n"); -+ return -ENOMEM; -+ } -+ -+ i = ddr_settings_size + 1; -+ iram_ddr_settings[i][0] = (unsigned long)mmdc_base; -+ iram_ddr_settings[i+1][0] = (unsigned long)ccm_base; -+ iram_ddr_settings[i+2][0] = (unsigned long)iomux_base; -+ iram_ddr_settings[i+3][0] = (unsigned long)l2_base; -+ -+ if (cpu_is_imx6q()) { -+ /* store the IOMUX settings at boot. */ -+ for (i = 0; i < iomux_settings_size; i++) { -+ iomux_offsets_mx6q[i][1] = -+ readl_relaxed(iomux_base + -+ iomux_offsets_mx6q[i][0]); -+ iram_iomux_settings[i+1][0] = iomux_offsets_mx6q[i][0]; -+ iram_iomux_settings[i+1][1] = iomux_offsets_mx6q[i][1]; -+ } -+ } -+ -+ if (cpu_is_imx6dl()) { -+ for (i = 0; i < iomux_settings_size; i++) { -+ iomux_offsets_mx6dl[i][1] = -+ readl_relaxed(iomux_base + -+ iomux_offsets_mx6dl[i][0]); -+ iram_iomux_settings[i+1][0] = iomux_offsets_mx6dl[i][0]; -+ iram_iomux_settings[i+1][1] = iomux_offsets_mx6dl[i][1]; -+ } -+ } -+ -+ ddr_freq_change_iram_base = (void *)gen_pool_alloc(iram_pool, -+ DDR_FREQ_CHANGE_SIZE); -+ if (!ddr_freq_change_iram_base) { -+ dev_err(dev, "Cannot alloc iram for ddr freq change code!\n"); -+ return -ENOMEM; -+ } -+ -+ iram_paddr = gen_pool_virt_to_phys(iram_pool, -+ (unsigned long)ddr_freq_change_iram_base); -+ /* -+ * Need to remap the area here since we want -+ * the memory region to be executable. -+ */ -+ ddr_freq_change_iram_base = __arm_ioremap(iram_paddr, -+ DDR_FREQ_CHANGE_SIZE, -+ MT_MEMORY_RWX_NONCACHED); -+ mx6_change_ddr_freq = (void *)fncpy(ddr_freq_change_iram_base, -+ &mx6_ddr3_freq_change, DDR_FREQ_CHANGE_SIZE); -+ -+ curr_ddr_rate = ddr_normal_rate; -+ -+ return 0; -+} -diff -Nur linux-4.1.13.orig/arch/arm/mach-imx/busfreq-imx6.c linux-4.1.13/arch/arm/mach-imx/busfreq-imx6.c ---- linux-4.1.13.orig/arch/arm/mach-imx/busfreq-imx6.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/arch/arm/mach-imx/busfreq-imx6.c 2015-11-30 17:56:13.528141189 +0100 -@@ -0,0 +1,994 @@ -+/* -+ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -+ */ -+ -+/*! -+ * @file busfreq-imx6.c -+ * -+ * @brief A common API for the Freescale Semiconductor iMX6 Busfreq API -+ * -+ * The APIs are for setting bus frequency to different values based on the -+ * highest freqeuncy requested. -+ * -+ * @ingroup PM -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "hardware.h" -+ -+#define LPAPM_CLK 24000000 -+#define DDR3_AUDIO_CLK 50000000 -+#define LPDDR2_AUDIO_CLK 100000000 -+ -+int vpu352 = 0; -+ -+int high_bus_freq_mode; -+int med_bus_freq_mode; -+int audio_bus_freq_mode; -+int low_bus_freq_mode; -+int ultra_low_bus_freq_mode; -+unsigned int ddr_med_rate; -+unsigned int ddr_normal_rate; -+ -+#ifdef CONFIG_ARM_IMX6Q_CPUFREQ -+static int bus_freq_scaling_initialized; -+static struct device *busfreq_dev; -+static int busfreq_suspended; -+static u32 org_arm_rate; -+static int bus_freq_scaling_is_active; -+static int high_bus_count, med_bus_count, audio_bus_count, low_bus_count; -+static unsigned int ddr_low_rate; -+ -+extern int init_mmdc_lpddr2_settings(struct platform_device *dev); -+extern int init_mmdc_ddr3_settings(struct platform_device *dev); -+extern int update_ddr_freq(int ddr_rate); -+extern int update_lpddr2_freq(int ddr_rate); -+ -+DEFINE_MUTEX(bus_freq_mutex); -+static DEFINE_SPINLOCK(freq_lock); -+ -+static struct clk *pll2_400; -+static struct clk *periph_clk; -+static struct clk *periph_pre_clk; -+static struct clk *periph_clk2_sel; -+static struct clk *periph_clk2; -+static struct clk *osc_clk; -+static struct clk *cpu_clk; -+static struct clk *pll3; -+static struct clk *pll2; -+static struct clk *pll2_200; -+static struct clk *pll1_sys; -+static struct clk *periph2_clk; -+static struct clk *ocram_clk; -+static struct clk *ahb_clk; -+static struct clk *pll1_sw_clk; -+static struct clk *periph2_pre_clk; -+static struct clk *periph2_clk2_sel; -+static struct clk *periph2_clk2; -+static struct clk *step_clk; -+static struct clk *axi_sel_clk; -+static struct clk *pll3_pfd1_540m; -+ -+static u32 pll2_org_rate; -+static struct delayed_work low_bus_freq_handler; -+static struct delayed_work bus_freq_daemon; -+ -+static void enter_lpm_imx6sl(void) -+{ -+ unsigned long flags; -+ -+ if (high_bus_freq_mode) { -+ pll2_org_rate = clk_get_rate(pll2); -+ /* Set periph_clk to be sourced from OSC_CLK */ -+ clk_set_parent(periph_clk2_sel, osc_clk); -+ clk_set_parent(periph_clk, periph_clk2); -+ /* Ensure AHB/AXI clks are at 24MHz. */ -+ clk_set_rate(ahb_clk, LPAPM_CLK); -+ clk_set_rate(ocram_clk, LPAPM_CLK); -+ } -+ if (audio_bus_count) { -+ /* Set AHB to 8MHz to lower pwer.*/ -+ clk_set_rate(ahb_clk, LPAPM_CLK / 3); -+ -+ /* Set up DDR to 100MHz. */ -+ spin_lock_irqsave(&freq_lock, flags); -+ update_lpddr2_freq(LPDDR2_AUDIO_CLK); -+ spin_unlock_irqrestore(&freq_lock, flags); -+ -+ /* Fix the clock tree in kernel */ -+ clk_set_rate(pll2, pll2_org_rate); -+ clk_set_parent(periph2_pre_clk, pll2_200); -+ clk_set_parent(periph2_clk, periph2_pre_clk); -+ -+ if (low_bus_freq_mode || ultra_low_bus_freq_mode) { -+ /* -+ * Swtich ARM to run off PLL2_PFD2_400MHz -+ * since DDR is anyway at 100MHz. -+ */ -+ clk_set_parent(step_clk, pll2_400); -+ clk_set_parent(pll1_sw_clk, step_clk); -+ /* -+ * Ensure that the clock will be -+ * at original speed. -+ */ -+ clk_set_rate(cpu_clk, org_arm_rate); -+ } -+ low_bus_freq_mode = 0; -+ ultra_low_bus_freq_mode = 0; -+ audio_bus_freq_mode = 1; -+ } else { -+ u32 arm_div, pll1_rate; -+ org_arm_rate = clk_get_rate(cpu_clk); -+ if (low_bus_freq_mode && low_bus_count == 0) { -+ /* -+ * We are already in DDR @ 24MHz state, but -+ * no one but ARM needs the DDR. In this case, -+ * we can lower the DDR freq to 1MHz when ARM -+ * enters WFI in this state. Keep track of this state. -+ */ -+ ultra_low_bus_freq_mode = 1; -+ low_bus_freq_mode = 0; -+ audio_bus_freq_mode = 0; -+ } else { -+ if (!ultra_low_bus_freq_mode && !low_bus_freq_mode) { -+ /* -+ * Anyway, make sure the AHB is running at 24MHz -+ * in low_bus_freq_mode. -+ */ -+ if (audio_bus_freq_mode) -+ clk_set_rate(ahb_clk, LPAPM_CLK); -+ /* -+ * Set DDR to 24MHz. -+ * Since we are going to bypass PLL2, -+ * we need to move ARM clk off PLL2_PFD2 -+ * to PLL1. Make sure the PLL1 is running -+ * at the lowest possible freq. -+ */ -+ clk_set_rate(pll1_sys, -+ clk_round_rate(pll1_sys, org_arm_rate)); -+ pll1_rate = clk_get_rate(pll1_sys); -+ arm_div = pll1_rate / org_arm_rate + 1; -+ /* -+ * Ensure ARM CLK is lower before -+ * changing the parent. -+ */ -+ clk_set_rate(cpu_clk, org_arm_rate / arm_div); -+ /* Now set the ARM clk parent to PLL1_SYS. */ -+ clk_set_parent(pll1_sw_clk, pll1_sys); -+ -+ /* -+ * Set STEP_CLK back to OSC to save power and -+ * also to maintain the parent.The WFI iram code -+ * will switch step_clk to osc, but the clock API -+ * is not aware of the change and when a new request -+ * to change the step_clk parent to pll2_pfd2_400M -+ * is requested sometime later, the change is ignored. -+ */ -+ clk_set_parent(step_clk, osc_clk); -+ /* Now set DDR to 24MHz. */ -+ spin_lock_irqsave(&freq_lock, flags); -+ update_lpddr2_freq(LPAPM_CLK); -+ spin_unlock_irqrestore(&freq_lock, flags); -+ -+ /* -+ * Fix the clock tree in kernel. -+ * Make sure PLL2 rate is updated as it gets -+ * bypassed in the DDR freq change code. -+ */ -+ clk_set_rate(pll2, LPAPM_CLK); -+ clk_set_parent(periph2_clk2_sel, pll2); -+ clk_set_parent(periph2_clk, periph2_clk2_sel); -+ -+ } -+ if (low_bus_count == 0) { -+ ultra_low_bus_freq_mode = 1; -+ low_bus_freq_mode = 0; -+ } else { -+ ultra_low_bus_freq_mode = 0; -+ low_bus_freq_mode = 1; -+ } -+ audio_bus_freq_mode = 0; -+ } -+ } -+} -+ -+static void exit_lpm_imx6sl(void) -+{ -+ unsigned long flags; -+ -+ spin_lock_irqsave(&freq_lock, flags); -+ /* Change DDR freq in IRAM. */ -+ update_lpddr2_freq(ddr_normal_rate); -+ spin_unlock_irqrestore(&freq_lock, flags); -+ -+ /* -+ * Fix the clock tree in kernel. -+ * Make sure PLL2 rate is updated as it gets -+ * un-bypassed in the DDR freq change code. -+ */ -+ clk_set_rate(pll2, pll2_org_rate); -+ clk_set_parent(periph2_pre_clk, pll2_400); -+ clk_set_parent(periph2_clk, periph2_pre_clk); -+ -+ /* Ensure that periph_clk is sourced from PLL2_400. */ -+ clk_set_parent(periph_pre_clk, pll2_400); -+ /* -+ * Before switching the perhiph_clk, ensure that the -+ * AHB/AXI will not be too fast. -+ */ -+ clk_set_rate(ahb_clk, LPAPM_CLK / 3); -+ clk_set_rate(ocram_clk, LPAPM_CLK / 2); -+ clk_set_parent(periph_clk, periph_pre_clk); -+ -+ if (low_bus_freq_mode || ultra_low_bus_freq_mode) { -+ /* Move ARM from PLL1_SW_CLK to PLL2_400. */ -+ clk_set_parent(step_clk, pll2_400); -+ clk_set_parent(pll1_sw_clk, step_clk); -+ clk_set_rate(cpu_clk, org_arm_rate); -+ ultra_low_bus_freq_mode = 0; -+ } -+} -+ -+int reduce_bus_freq(void) -+{ -+ int ret = 0; -+ clk_prepare_enable(pll3); -+ if (cpu_is_imx6sl()) -+ enter_lpm_imx6sl(); -+ else { -+ if (cpu_is_imx6dl() && (clk_get_parent(axi_sel_clk) -+ != periph_clk)) -+ /* Set axi to periph_clk */ -+ clk_set_parent(axi_sel_clk, periph_clk); -+ -+ if (audio_bus_count) { -+ /* Need to ensure that PLL2_PFD_400M is kept ON. */ -+ clk_prepare_enable(pll2_400); -+ update_ddr_freq(DDR3_AUDIO_CLK); -+ /* Make sure periph clk's parent also got updated */ -+ ret = clk_set_parent(periph_clk2_sel, pll3); -+ if (ret) -+ dev_WARN(busfreq_dev, -+ "%s: %d: clk set parent fail!\n", -+ __func__, __LINE__); -+ ret = clk_set_parent(periph_pre_clk, pll2_200); -+ if (ret) -+ dev_WARN(busfreq_dev, -+ "%s: %d: clk set parent fail!\n", -+ __func__, __LINE__); -+ ret = clk_set_parent(periph_clk, periph_pre_clk); -+ if (ret) -+ dev_WARN(busfreq_dev, -+ "%s: %d: clk set parent fail!\n", -+ __func__, __LINE__); -+ audio_bus_freq_mode = 1; -+ low_bus_freq_mode = 0; -+ } else { -+ update_ddr_freq(LPAPM_CLK); -+ /* Make sure periph clk's parent also got updated */ -+ ret = clk_set_parent(periph_clk2_sel, osc_clk); -+ if (ret) -+ dev_WARN(busfreq_dev, -+ "%s: %d: clk set parent fail!\n", -+ __func__, __LINE__); -+ /* Set periph_clk parent to OSC via periph_clk2_sel */ -+ ret = clk_set_parent(periph_clk, periph_clk2); -+ if (ret) -+ dev_WARN(busfreq_dev, -+ "%s: %d: clk set parent fail!\n", -+ __func__, __LINE__); -+ if (audio_bus_freq_mode) -+ clk_disable_unprepare(pll2_400); -+ low_bus_freq_mode = 1; -+ audio_bus_freq_mode = 0; -+ } -+ } -+ clk_disable_unprepare(pll3); -+ -+ med_bus_freq_mode = 0; -+ high_bus_freq_mode = 0; -+ -+ if (audio_bus_freq_mode) -+ dev_dbg(busfreq_dev, "Bus freq set to audio mode. Count:\ -+ high %d, med %d, audio %d\n", -+ high_bus_count, med_bus_count, audio_bus_count); -+ if (low_bus_freq_mode) -+ dev_dbg(busfreq_dev, "Bus freq set to low mode. Count:\ -+ high %d, med %d, audio %d\n", -+ high_bus_count, med_bus_count, audio_bus_count); -+ -+ return ret; -+} -+ -+static void reduce_bus_freq_handler(struct work_struct *work) -+{ -+ mutex_lock(&bus_freq_mutex); -+ -+ reduce_bus_freq(); -+ -+ mutex_unlock(&bus_freq_mutex); -+} -+ -+/* -+ * Set the DDR, AHB to 24MHz. -+ * This mode will be activated only when none of the modules that -+ * need a higher DDR or AHB frequency are active. -+ */ -+int set_low_bus_freq(void) -+{ -+ if (busfreq_suspended) -+ return 0; -+ -+ if (!bus_freq_scaling_initialized || !bus_freq_scaling_is_active) -+ return 0; -+ -+ /* -+ * Check to see if we need to got from -+ * low bus freq mode to audio bus freq mode. -+ * If so, the change needs to be done immediately. -+ */ -+ if (audio_bus_count && (low_bus_freq_mode || ultra_low_bus_freq_mode)) -+ reduce_bus_freq(); -+ else -+ /* -+ * Don't lower the frequency immediately. Instead -+ * scheduled a delayed work and drop the freq if -+ * the conditions still remain the same. -+ */ -+ schedule_delayed_work(&low_bus_freq_handler, -+ usecs_to_jiffies(3000000)); -+ return 0; -+} -+ -+/* -+ * Set the DDR to either 528MHz or 400MHz for iMX6qd -+ * or 400MHz for iMX6dl. -+ */ -+int set_high_bus_freq(int high_bus_freq) -+{ -+ int ret = 0; -+ struct clk *periph_clk_parent; -+ -+ if (bus_freq_scaling_initialized && bus_freq_scaling_is_active) -+ cancel_delayed_work_sync(&low_bus_freq_handler); -+ -+ if (busfreq_suspended) -+ return 0; -+ -+ if (cpu_is_imx6q()) -+ periph_clk_parent = pll2; -+ else -+ periph_clk_parent = pll2_400; -+ -+ if (!bus_freq_scaling_initialized || !bus_freq_scaling_is_active) -+ return 0; -+ -+ if (high_bus_freq_mode) -+ return 0; -+ -+ /* medium bus freq is only supported for MX6DQ */ -+ if (med_bus_freq_mode && !high_bus_freq) -+ return 0; -+ -+ clk_prepare_enable(pll3); -+ if (cpu_is_imx6sl()) -+ exit_lpm_imx6sl(); -+ else { -+ if (high_bus_freq) { -+ update_ddr_freq(ddr_normal_rate); -+ /* Make sure periph clk's parent also got updated */ -+ ret = clk_set_parent(periph_clk2_sel, pll3); -+ if (ret) -+ dev_WARN(busfreq_dev, -+ "%s: %d: clk set parent fail!\n", -+ __func__, __LINE__); -+ ret = clk_set_parent(periph_pre_clk, periph_clk_parent); -+ if (ret) -+ dev_WARN(busfreq_dev, -+ "%s: %d: clk set parent fail!\n", -+ __func__, __LINE__); -+ ret = clk_set_parent(periph_clk, periph_pre_clk); -+ if (ret) -+ dev_WARN(busfreq_dev, -+ "%s: %d: clk set parent fail!\n", -+ __func__, __LINE__); -+ if (cpu_is_imx6dl() && (clk_get_parent(axi_sel_clk) -+ != pll3_pfd1_540m)) -+ /* Set axi to pll3_pfd1_540m */ -+ clk_set_parent(axi_sel_clk, pll3_pfd1_540m); -+ } else { -+ update_ddr_freq(ddr_med_rate); -+ /* Make sure periph clk's parent also got updated */ -+ ret = clk_set_parent(periph_clk2_sel, pll3); -+ if (ret) -+ dev_WARN(busfreq_dev, -+ "%s: %d: clk set parent fail!\n", -+ __func__, __LINE__); -+ ret = clk_set_parent(periph_pre_clk, pll2_400); -+ if (ret) -+ dev_WARN(busfreq_dev, -+ "%s: %d: clk set parent fail!\n", -+ __func__, __LINE__); -+ ret = clk_set_parent(periph_clk, periph_pre_clk); -+ if (ret) -+ dev_WARN(busfreq_dev, -+ "%s: %d: clk set parent fail!\n", -+ __func__, __LINE__); -+ } -+ if (audio_bus_freq_mode) -+ clk_disable_unprepare(pll2_400); -+ } -+ -+ high_bus_freq_mode = 1; -+ med_bus_freq_mode = 0; -+ low_bus_freq_mode = 0; -+ audio_bus_freq_mode = 0; -+ -+ clk_disable_unprepare(pll3); -+ -+ if (high_bus_freq_mode) -+ dev_dbg(busfreq_dev, "Bus freq set to high mode. Count:\ -+ high %d, med %d, audio %d\n", -+ high_bus_count, med_bus_count, audio_bus_count); -+ if (med_bus_freq_mode) -+ dev_dbg(busfreq_dev, "Bus freq set to med mode. Count:\ -+ high %d, med %d, audio %d\n", -+ high_bus_count, med_bus_count, audio_bus_count); -+ -+ return 0; -+} -+#endif -+ -+void request_bus_freq(enum bus_freq_mode mode) -+{ -+ if (vpu352) -+ return; -+#ifdef CONFIG_ARM_IMX6Q_CPUFREQ -+ mutex_lock(&bus_freq_mutex); -+ -+ if (mode == BUS_FREQ_HIGH) -+ high_bus_count++; -+ else if (mode == BUS_FREQ_MED) -+ med_bus_count++; -+ else if (mode == BUS_FREQ_AUDIO) -+ audio_bus_count++; -+ else if (mode == BUS_FREQ_LOW) -+ low_bus_count++; -+ -+ if (busfreq_suspended || !bus_freq_scaling_initialized || -+ !bus_freq_scaling_is_active) { -+ mutex_unlock(&bus_freq_mutex); -+ return; -+ } -+ cancel_delayed_work_sync(&low_bus_freq_handler); -+ -+ if (cpu_is_imx6dl()) { -+ /* No support for medium setpoint on MX6DL. */ -+ if (mode == BUS_FREQ_MED) { -+ high_bus_count++; -+ mode = BUS_FREQ_HIGH; -+ } -+ } -+ -+ if ((mode == BUS_FREQ_HIGH) && (!high_bus_freq_mode)) { -+ set_high_bus_freq(1); -+ mutex_unlock(&bus_freq_mutex); -+ return; -+ } -+ -+ if ((mode == BUS_FREQ_MED) && (!high_bus_freq_mode) && -+ (!med_bus_freq_mode)) { -+ set_high_bus_freq(0); -+ mutex_unlock(&bus_freq_mutex); -+ return; -+ } -+ if ((mode == BUS_FREQ_AUDIO) && (!high_bus_freq_mode) && -+ (!med_bus_freq_mode) && (!audio_bus_freq_mode)) { -+ set_low_bus_freq(); -+ mutex_unlock(&bus_freq_mutex); -+ return; -+ } -+ mutex_unlock(&bus_freq_mutex); -+#endif -+ return; -+} -+EXPORT_SYMBOL(request_bus_freq); -+ -+void release_bus_freq(enum bus_freq_mode mode) -+{ -+ if (vpu352) -+ return; -+#ifdef CONFIG_ARM_IMX6Q_CPUFREQ -+ mutex_lock(&bus_freq_mutex); -+ -+ if (mode == BUS_FREQ_HIGH) { -+ if (high_bus_count == 0) { -+ dev_err(busfreq_dev, "high bus count mismatch!\n"); -+ dump_stack(); -+ mutex_unlock(&bus_freq_mutex); -+ return; -+ } -+ high_bus_count--; -+ } else if (mode == BUS_FREQ_MED) { -+ if (med_bus_count == 0) { -+ dev_err(busfreq_dev, "med bus count mismatch!\n"); -+ dump_stack(); -+ mutex_unlock(&bus_freq_mutex); -+ return; -+ } -+ med_bus_count--; -+ } else if (mode == BUS_FREQ_AUDIO) { -+ if (audio_bus_count == 0) { -+ dev_err(busfreq_dev, "audio bus count mismatch!\n"); -+ dump_stack(); -+ mutex_unlock(&bus_freq_mutex); -+ return; -+ } -+ audio_bus_count--; -+ } else if (mode == BUS_FREQ_LOW) { -+ if (low_bus_count == 0) { -+ dev_err(busfreq_dev, "low bus count mismatch!\n"); -+ dump_stack(); -+ mutex_unlock(&bus_freq_mutex); -+ return; -+ } -+ low_bus_count--; -+ } -+ -+ if (busfreq_suspended || !bus_freq_scaling_initialized || -+ !bus_freq_scaling_is_active) { -+ mutex_unlock(&bus_freq_mutex); -+ return; -+ } -+ -+ if (cpu_is_imx6dl()) { -+ /* No support for medium setpoint on MX6DL. */ -+ if (mode == BUS_FREQ_MED) { -+ high_bus_count--; -+ mode = BUS_FREQ_HIGH; -+ } -+ } -+ -+ if ((!audio_bus_freq_mode) && (high_bus_count == 0) && -+ (med_bus_count == 0) && (audio_bus_count != 0)) { -+ set_low_bus_freq(); -+ mutex_unlock(&bus_freq_mutex); -+ return; -+ } -+ if ((!low_bus_freq_mode) && (high_bus_count == 0) && -+ (med_bus_count == 0) && (audio_bus_count == 0) && -+ (low_bus_count != 0)) { -+ set_low_bus_freq(); -+ mutex_unlock(&bus_freq_mutex); -+ return; -+ } -+ if ((!ultra_low_bus_freq_mode) && (high_bus_count == 0) && -+ (med_bus_count == 0) && (audio_bus_count == 0) && -+ (low_bus_count == 0)) { -+ set_low_bus_freq(); -+ mutex_unlock(&bus_freq_mutex); -+ return; -+ } -+ -+ mutex_unlock(&bus_freq_mutex); -+#endif -+ return; -+} -+EXPORT_SYMBOL(release_bus_freq); -+ -+#ifdef CONFIG_ARM_IMX6Q_CPUFREQ -+static void bus_freq_daemon_handler(struct work_struct *work) -+{ -+ mutex_lock(&bus_freq_mutex); -+ if ((!low_bus_freq_mode) && (!ultra_low_bus_freq_mode) && (high_bus_count == 0) && -+ (med_bus_count == 0) && (audio_bus_count == 0)) -+ set_low_bus_freq(); -+ mutex_unlock(&bus_freq_mutex); -+} -+ -+static ssize_t bus_freq_scaling_enable_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ if (bus_freq_scaling_is_active) -+ return sprintf(buf, "Bus frequency scaling is enabled\n"); -+ else -+ return sprintf(buf, "Bus frequency scaling is disabled\n"); -+} -+ -+static ssize_t vpu352_enable_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ if (vpu352) -+ return sprintf(buf, "VPU352M is enabled\n"); -+ else -+ return sprintf(buf, "VPU352M is disabled\n"); -+} -+ -+static int vpu352_setup(char *options) -+{ -+ return kstrtol(options, 0, (long int *)&vpu352); -+} -+ -+static ssize_t bus_freq_scaling_enable_store(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t size) -+{ -+ if (strncmp(buf, "1", 1) == 0) { -+ bus_freq_scaling_is_active = 1; -+ set_high_bus_freq(1); -+ /* -+ * We set bus freq to highest at the beginning, -+ * so we use this daemon thread to make sure system -+ * can enter low bus mode if -+ * there is no high bus request pending -+ */ -+ schedule_delayed_work(&bus_freq_daemon, -+ usecs_to_jiffies(5000000)); -+ } else if (strncmp(buf, "0", 1) == 0) { -+ if (bus_freq_scaling_is_active) -+ set_high_bus_freq(1); -+ bus_freq_scaling_is_active = 0; -+ } -+ return size; -+} -+ -+static int bus_freq_pm_notify(struct notifier_block *nb, unsigned long event, -+ void *dummy) -+{ -+ mutex_lock(&bus_freq_mutex); -+ -+ if (event == PM_SUSPEND_PREPARE) { -+ high_bus_count++; -+ set_high_bus_freq(1); -+ busfreq_suspended = 1; -+ } else if (event == PM_POST_SUSPEND) { -+ busfreq_suspended = 0; -+ high_bus_count--; -+ schedule_delayed_work(&bus_freq_daemon, -+ usecs_to_jiffies(5000000)); -+ } -+ -+ mutex_unlock(&bus_freq_mutex); -+ -+ return NOTIFY_OK; -+} -+ -+static int busfreq_reboot_notifier_event(struct notifier_block *this, -+ unsigned long event, void *ptr) -+{ -+ /* System is rebooting. Set the system into high_bus_freq_mode. */ -+ request_bus_freq(BUS_FREQ_HIGH); -+ -+ return 0; -+} -+ -+static struct notifier_block imx_bus_freq_pm_notifier = { -+ .notifier_call = bus_freq_pm_notify, -+}; -+ -+static struct notifier_block imx_busfreq_reboot_notifier = { -+ .notifier_call = busfreq_reboot_notifier_event, -+}; -+ -+ -+static DEVICE_ATTR(enable, 0644, bus_freq_scaling_enable_show, -+ bus_freq_scaling_enable_store); -+static DEVICE_ATTR(vpu352, 0444, vpu352_enable_show, -+ NULL); -+#endif -+ -+/*! -+ * This is the probe routine for the bus frequency driver. -+ * -+ * @param pdev The platform device structure -+ * -+ * @return The function returns 0 on success -+ * -+ */ -+ -+static int busfreq_probe(struct platform_device *pdev) -+{ -+#ifdef CONFIG_ARM_IMX6Q_CPUFREQ -+ u32 err; -+ -+ busfreq_dev = &pdev->dev; -+ -+ pll2_400 = devm_clk_get(&pdev->dev, "pll2_pfd2_396m"); -+ if (IS_ERR(pll2_400)) { -+ dev_err(busfreq_dev, "%s: failed to get pll2_pfd2_396m\n", -+ __func__); -+ return PTR_ERR(pll2_400); -+ } -+ -+ pll2_200 = devm_clk_get(&pdev->dev, "pll2_198m"); -+ if (IS_ERR(pll2_200)) { -+ dev_err(busfreq_dev, "%s: failed to get pll2_198m\n", -+ __func__); -+ return PTR_ERR(pll2_200); -+ } -+ -+ pll2 = devm_clk_get(&pdev->dev, "pll2_bus"); -+ if (IS_ERR(pll2)) { -+ dev_err(busfreq_dev, "%s: failed to get pll2_bus\n", -+ __func__); -+ return PTR_ERR(pll2); -+ } -+ -+ cpu_clk = devm_clk_get(&pdev->dev, "arm"); -+ if (IS_ERR(cpu_clk)) { -+ dev_err(busfreq_dev, "%s: failed to get cpu_clk\n", -+ __func__); -+ return PTR_ERR(cpu_clk); -+ } -+ -+ pll3 = devm_clk_get(&pdev->dev, "pll3_usb_otg"); -+ if (IS_ERR(pll3)) { -+ dev_err(busfreq_dev, "%s: failed to get pll3_usb_otg\n", -+ __func__); -+ return PTR_ERR(pll3); -+ } -+ -+ periph_clk = devm_clk_get(&pdev->dev, "periph"); -+ if (IS_ERR(periph_clk)) { -+ dev_err(busfreq_dev, "%s: failed to get periph\n", -+ __func__); -+ return PTR_ERR(periph_clk); -+ } -+ -+ periph_pre_clk = devm_clk_get(&pdev->dev, "periph_pre"); -+ if (IS_ERR(periph_pre_clk)) { -+ dev_err(busfreq_dev, "%s: failed to get periph_pre\n", -+ __func__); -+ return PTR_ERR(periph_pre_clk); -+ } -+ -+ periph_clk2 = devm_clk_get(&pdev->dev, "periph_clk2"); -+ if (IS_ERR(periph_clk2)) { -+ dev_err(busfreq_dev, "%s: failed to get periph_clk2\n", -+ __func__); -+ return PTR_ERR(periph_clk2); -+ } -+ -+ periph_clk2_sel = devm_clk_get(&pdev->dev, "periph_clk2_sel"); -+ if (IS_ERR(periph_clk2_sel)) { -+ dev_err(busfreq_dev, "%s: failed to get periph_clk2_sel\n", -+ __func__); -+ return PTR_ERR(periph_clk2_sel); -+ } -+ -+ osc_clk = devm_clk_get(&pdev->dev, "osc"); -+ if (IS_ERR(osc_clk)) { -+ dev_err(busfreq_dev, "%s: failed to get osc_clk\n", -+ __func__); -+ return PTR_ERR(osc_clk); -+ } -+ -+ if (cpu_is_imx6dl()) { -+ axi_sel_clk = devm_clk_get(&pdev->dev, "axi_sel"); -+ if (IS_ERR(axi_sel_clk)) { -+ dev_err(busfreq_dev, "%s: failed to get axi_sel_clk\n", -+ __func__); -+ return PTR_ERR(axi_sel_clk); -+ } -+ -+ pll3_pfd1_540m = devm_clk_get(&pdev->dev, "pll3_pfd1_540m"); -+ if (IS_ERR(pll3_pfd1_540m)) { -+ dev_err(busfreq_dev, -+ "%s: failed to get pll3_pfd1_540m\n", __func__); -+ return PTR_ERR(pll3_pfd1_540m); -+ } -+ } -+ -+ if (cpu_is_imx6sl()) { -+ pll1_sys = devm_clk_get(&pdev->dev, "pll1_sys"); -+ if (IS_ERR(pll1_sys)) { -+ dev_err(busfreq_dev, "%s: failed to get pll1_sys\n", -+ __func__); -+ return PTR_ERR(pll1_sys); -+ } -+ -+ ahb_clk = devm_clk_get(&pdev->dev, "ahb"); -+ if (IS_ERR(ahb_clk)) { -+ dev_err(busfreq_dev, "%s: failed to get ahb_clk\n", -+ __func__); -+ return PTR_ERR(ahb_clk); -+ } -+ -+ ocram_clk = devm_clk_get(&pdev->dev, "ocram"); -+ if (IS_ERR(ocram_clk)) { -+ dev_err(busfreq_dev, "%s: failed to get ocram_clk\n", -+ __func__); -+ return PTR_ERR(ocram_clk); -+ } -+ -+ pll1_sw_clk = devm_clk_get(&pdev->dev, "pll1_sw"); -+ if (IS_ERR(pll1_sw_clk)) { -+ dev_err(busfreq_dev, "%s: failed to get pll1_sw_clk\n", -+ __func__); -+ return PTR_ERR(pll1_sw_clk); -+ } -+ -+ periph2_clk = devm_clk_get(&pdev->dev, "periph2"); -+ if (IS_ERR(periph2_clk)) { -+ dev_err(busfreq_dev, "%s: failed to get periph2\n", -+ __func__); -+ return PTR_ERR(periph2_clk); -+ } -+ -+ periph2_pre_clk = devm_clk_get(&pdev->dev, "periph2_pre"); -+ if (IS_ERR(periph2_pre_clk)) { -+ dev_err(busfreq_dev, -+ "%s: failed to get periph2_pre_clk\n", -+ __func__); -+ return PTR_ERR(periph2_pre_clk); -+ } -+ -+ periph2_clk2 = devm_clk_get(&pdev->dev, "periph2_clk2"); -+ if (IS_ERR(periph2_clk2)) { -+ dev_err(busfreq_dev, -+ "%s: failed to get periph2_clk2\n", -+ __func__); -+ return PTR_ERR(periph2_clk2); -+ } -+ -+ periph2_clk2_sel = devm_clk_get(&pdev->dev, "periph2_clk2_sel"); -+ if (IS_ERR(periph2_clk2_sel)) { -+ dev_err(busfreq_dev, -+ "%s: failed to get periph2_clk2_sel\n", -+ __func__); -+ return PTR_ERR(periph2_clk2_sel); -+ } -+ -+ step_clk = devm_clk_get(&pdev->dev, "step"); -+ if (IS_ERR(step_clk)) { -+ dev_err(busfreq_dev, -+ "%s: failed to get step_clk\n", -+ __func__); -+ return PTR_ERR(periph2_clk2_sel); -+ } -+ -+ } -+ -+ err = sysfs_create_file(&busfreq_dev->kobj, &dev_attr_enable.attr); -+ if (err) { -+ dev_err(busfreq_dev, -+ "Unable to register sysdev entry for BUSFREQ"); -+ return err; -+ } -+ err = sysfs_create_file(&busfreq_dev->kobj, &dev_attr_vpu352.attr); -+ if (err) { -+ dev_err(busfreq_dev, -+ "Unable to register sysdev entry for BUSFREQ"); -+ return err; -+ } -+ -+ if (of_property_read_u32(pdev->dev.of_node, "fsl,max_ddr_freq", -+ &ddr_normal_rate)) { -+ dev_err(busfreq_dev, "max_ddr_freq entry missing\n"); -+ return -EINVAL; -+ } -+#endif -+ -+ high_bus_freq_mode = 1; -+ med_bus_freq_mode = 0; -+ low_bus_freq_mode = 0; -+ audio_bus_freq_mode = 0; -+ ultra_low_bus_freq_mode = 0; -+ -+#ifdef CONFIG_ARM_IMX6Q_CPUFREQ -+ bus_freq_scaling_is_active = 1; -+ bus_freq_scaling_initialized = 1; -+ -+ ddr_low_rate = LPAPM_CLK; -+ if (cpu_is_imx6q()) { -+ if (of_property_read_u32(pdev->dev.of_node, "fsl,med_ddr_freq", -+ &ddr_med_rate)) { -+ dev_info(busfreq_dev, -+ "DDR medium rate not supported.\n"); -+ ddr_med_rate = ddr_normal_rate; -+ } -+ } -+ -+ INIT_DELAYED_WORK(&low_bus_freq_handler, reduce_bus_freq_handler); -+ INIT_DELAYED_WORK(&bus_freq_daemon, bus_freq_daemon_handler); -+ register_pm_notifier(&imx_bus_freq_pm_notifier); -+ register_reboot_notifier(&imx_busfreq_reboot_notifier); -+ -+ if (cpu_is_imx6sl()) -+ err = init_mmdc_lpddr2_settings(pdev); -+ else -+ err = init_mmdc_ddr3_settings(pdev); -+ if (err) { -+ dev_err(busfreq_dev, "Busfreq init of MMDC failed\n"); -+ return err; -+ } -+#endif -+ return 0; -+} -+ -+static const struct of_device_id imx6_busfreq_ids[] = { -+ { .compatible = "fsl,imx6_busfreq", }, -+ { /* sentinel */ } -+}; -+ -+static struct platform_driver busfreq_driver = { -+ .driver = { -+ .name = "imx6_busfreq", -+ .owner = THIS_MODULE, -+ .of_match_table = imx6_busfreq_ids, -+ }, -+ .probe = busfreq_probe, -+}; -+ -+/*! -+ * Initialise the busfreq_driver. -+ * -+ * @return The function always returns 0. -+ */ -+ -+static int __init busfreq_init(void) -+{ -+ if (vpu352) { -+ printk(KERN_INFO "VPU@352Mhz activated. Bus freq driver module inactive\n"); -+ return 0; -+ } -+ -+ if (platform_driver_register(&busfreq_driver) != 0) -+ return -ENODEV; -+ -+ printk(KERN_INFO "Bus freq driver module loaded\n"); -+ -+ return 0; -+} -+ -+static void __exit busfreq_cleanup(void) -+{ -+#ifdef CONFIG_ARM_IMX6Q_CPUFREQ -+ sysfs_remove_file(&busfreq_dev->kobj, &dev_attr_enable.attr); -+ -+ bus_freq_scaling_initialized = 0; -+#endif -+ /* Unregister the device structure */ -+ platform_driver_unregister(&busfreq_driver); -+} -+ -+__setup("vpu352=", vpu352_setup); -+module_init(busfreq_init); -+module_exit(busfreq_cleanup); -+ -+MODULE_AUTHOR("Freescale Semiconductor, Inc."); -+MODULE_DESCRIPTION("BusFreq driver"); -+MODULE_LICENSE("GPL"); -diff -Nur linux-4.1.13.orig/arch/arm/mach-imx/busfreq_lpddr2.c linux-4.1.13/arch/arm/mach-imx/busfreq_lpddr2.c ---- linux-4.1.13.orig/arch/arm/mach-imx/busfreq_lpddr2.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/arch/arm/mach-imx/busfreq_lpddr2.c 2015-11-30 17:56:13.528141189 +0100 -@@ -0,0 +1,183 @@ -+/* -+ * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. All Rights Reserved. -+ */ -+ -+/* -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/*! -+ * @file busfreq_lpddr2.c -+ * -+ * @brief iMX6 LPDDR2 frequency change specific file. -+ * -+ * @ingroup PM -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "hardware.h" -+ -+/* DDR settings */ -+static void __iomem *mmdc_base; -+static void __iomem *anatop_base; -+static void __iomem *ccm_base; -+static void __iomem *l2_base; -+static struct device *busfreq_dev; -+static void *ddr_freq_change_iram_base; -+static int curr_ddr_rate; -+ -+unsigned long reg_addrs[4]; -+ -+void (*mx6_change_lpddr2_freq)(u32 ddr_freq, int bus_freq_mode, -+ void *iram_addr) = NULL; -+ -+extern unsigned int ddr_normal_rate; -+extern int low_bus_freq_mode; -+extern int ultra_low_bus_freq_mode; -+extern void mx6_lpddr2_freq_change(u32 freq, int bus_freq_mode, -+ void *iram_addr); -+ -+ -+#define LPDDR2_FREQ_CHANGE_SIZE 0x1000 -+ -+ -+/* change the DDR frequency. */ -+int update_lpddr2_freq(int ddr_rate) -+{ -+ if (ddr_rate == curr_ddr_rate) -+ return 0; -+ -+ pr_debug("Bus freq set to %d start...\n", ddr_rate); -+ -+ /* -+ * Flush the TLB, to ensure no TLB maintenance occurs -+ * when DDR is in self-refresh. -+ */ -+ local_flush_tlb_all(); -+ /* Now change DDR frequency. */ -+ mx6_change_lpddr2_freq(ddr_rate, -+ (low_bus_freq_mode | ultra_low_bus_freq_mode), -+ reg_addrs); -+ -+ curr_ddr_rate = ddr_rate; -+ -+ pr_debug("Bus freq set to %d done...\n", ddr_rate); -+ -+ return 0; -+} -+ -+int init_mmdc_lpddr2_settings(struct platform_device *busfreq_pdev) -+{ -+ struct platform_device *ocram_dev; -+ unsigned int iram_paddr; -+ struct device_node *node; -+ struct gen_pool *iram_pool; -+ -+ busfreq_dev = &busfreq_pdev->dev; -+ node = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-mmdc"); -+ if (!node) { -+ printk(KERN_ERR "failed to find imx6sl-mmdc device tree data!\n"); -+ return -EINVAL; -+ } -+ mmdc_base = of_iomap(node, 0); -+ WARN(!mmdc_base, "unable to map mmdc registers\n"); -+ -+ node = NULL; -+ node = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-ccm"); -+ if (!node) { -+ printk(KERN_ERR "failed to find imx6sl-ccm device tree data!\n"); -+ return -EINVAL; -+ } -+ ccm_base = of_iomap(node, 0); -+ WARN(!ccm_base, "unable to map ccm registers\n"); -+ -+ node = of_find_compatible_node(NULL, NULL, "arm,pl310-cache"); -+ if (!node) { -+ printk(KERN_ERR "failed to find imx6sl-pl310-cache device tree data!\n"); -+ return -EINVAL; -+ } -+ l2_base = of_iomap(node, 0); -+ WARN(!l2_base, "unable to map PL310 registers\n"); -+ -+ node = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop"); -+ if (!node) { -+ printk(KERN_ERR "failed to find imx6sl-pl310-cache device tree data!\n"); -+ return -EINVAL; -+ } -+ anatop_base = of_iomap(node, 0); -+ WARN(!anatop_base, "unable to map anatop registers\n"); -+ -+ node = NULL; -+ node = of_find_compatible_node(NULL, NULL, "mmio-sram"); -+ if (!node) { -+ dev_err(busfreq_dev, "%s: failed to find ocram node\n", -+ __func__); -+ return -EINVAL; -+ } -+ -+ ocram_dev = of_find_device_by_node(node); -+ if (!ocram_dev) { -+ dev_err(busfreq_dev, "failed to find ocram device!\n"); -+ return -EINVAL; -+ } -+ -+ iram_pool = dev_get_gen_pool(&ocram_dev->dev); -+ if (!iram_pool) { -+ dev_err(busfreq_dev, "iram pool unavailable!\n"); -+ return -EINVAL; -+ } -+ -+ reg_addrs[0] = (unsigned long)anatop_base; -+ reg_addrs[1] = (unsigned long)ccm_base; -+ reg_addrs[2] = (unsigned long)mmdc_base; -+ reg_addrs[3] = (unsigned long)l2_base; -+ -+ ddr_freq_change_iram_base = (void *)gen_pool_alloc(iram_pool, -+ LPDDR2_FREQ_CHANGE_SIZE); -+ if (!ddr_freq_change_iram_base) { -+ dev_err(busfreq_dev, -+ "Cannot alloc iram for ddr freq change code!\n"); -+ return -ENOMEM; -+ } -+ -+ iram_paddr = gen_pool_virt_to_phys(iram_pool, -+ (unsigned long)ddr_freq_change_iram_base); -+ /* -+ * Need to remap the area here since we want -+ * the memory region to be executable. -+ */ -+ ddr_freq_change_iram_base = __arm_ioremap(iram_paddr, -+ LPDDR2_FREQ_CHANGE_SIZE, -+ MT_MEMORY_RWX_NONCACHED); -+ mx6_change_lpddr2_freq = (void *)fncpy(ddr_freq_change_iram_base, -+ &mx6_lpddr2_freq_change, LPDDR2_FREQ_CHANGE_SIZE); -+ -+ curr_ddr_rate = ddr_normal_rate; -+ -+ return 0; -+} -diff -Nur linux-4.1.13.orig/arch/arm/mach-imx/clk.h linux-4.1.13/arch/arm/mach-imx/clk.h ---- linux-4.1.13.orig/arch/arm/mach-imx/clk.h 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/mach-imx/clk.h 2015-11-30 17:56:13.528141189 +0100 -@@ -55,6 +55,34 @@ - shift, 0, &imx_ccm_lock, share_count); - } - -+static inline void imx_clk_prepare_enable(struct clk *clk) -+{ -+ int ret = clk_prepare_enable(clk); -+ -+ if (ret) -+ pr_err("failed to prepare and enable clk %s: %d\n", -+ __clk_get_name(clk), ret); -+} -+ -+static inline int imx_clk_set_parent(struct clk *clk, struct clk *parent) -+{ -+ int ret = clk_set_parent(clk, parent); -+ -+ if (ret) -+ pr_err("failed to set parent of clk %s to %s: %d\n", -+ __clk_get_name(clk), __clk_get_name(parent), ret); -+ return ret; -+} -+ -+static inline void imx_clk_set_rate(struct clk *clk, unsigned long rate) -+{ -+ int ret = clk_set_rate(clk, rate); -+ -+ if (ret) -+ pr_err("failed to set rate of clk %s to %ld: %d\n", -+ __clk_get_name(clk), rate, ret); -+} -+ - struct clk *imx_clk_pfd(const char *name, const char *parent_name, - void __iomem *reg, u8 idx); - -@@ -125,6 +153,15 @@ - &imx_ccm_lock); - } - -+static inline struct clk *imx_clk_mux_glitchless(const char *name, -+ void __iomem *reg, u8 shift, u8 width, const char **parents, -+ int num_parents) -+{ -+ return clk_register_mux(NULL, name, parents, num_parents, -+ CLK_SET_RATE_NO_REPARENT, reg, shift, -+ width, 0, &imx_ccm_lock); -+} -+ - static inline struct clk *imx_clk_fixed_factor(const char *name, - const char *parent, unsigned int mult, unsigned int div) - { -diff -Nur linux-4.1.13.orig/arch/arm/mach-imx/clk-imx1.c linux-4.1.13/arch/arm/mach-imx/clk-imx1.c ---- linux-4.1.13.orig/arch/arm/mach-imx/clk-imx1.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/mach-imx/clk-imx1.c 2015-11-30 17:56:13.528141189 +0100 -@@ -75,7 +75,8 @@ - - int __init mx1_clocks_init(unsigned long fref) - { -- ccm = MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR); -+ ccm = ioremap(MX1_CCM_BASE_ADDR, SZ_4K); -+ BUG_ON(!ccm); - - _mx1_clocks_init(fref); - -@@ -98,7 +99,7 @@ - clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-fb.0"); - clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ahb", "imx1-fb.0"); - -- mxc_timer_init(MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR), MX1_TIM1_INT); -+ mxc_timer_init(MX1_TIM1_BASE_ADDR, MX1_TIM1_INT); - - return 0; - } -diff -Nur linux-4.1.13.orig/arch/arm/mach-imx/clk-imx21.c linux-4.1.13/arch/arm/mach-imx/clk-imx21.c ---- linux-4.1.13.orig/arch/arm/mach-imx/clk-imx21.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/mach-imx/clk-imx21.c 2015-11-30 17:56:13.528141189 +0100 -@@ -153,7 +153,7 @@ - clk_register_clkdev(clk[IMX21_CLK_I2C_GATE], NULL, "imx21-i2c.0"); - clk_register_clkdev(clk[IMX21_CLK_OWIRE_GATE], NULL, "mxc_w1.0"); - -- mxc_timer_init(MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR), MX21_INT_GPT1); -+ mxc_timer_init(MX21_GPT1_BASE_ADDR, MX21_INT_GPT1); - - return 0; - } -diff -Nur linux-4.1.13.orig/arch/arm/mach-imx/clk-imx27.c linux-4.1.13/arch/arm/mach-imx/clk-imx27.c ---- linux-4.1.13.orig/arch/arm/mach-imx/clk-imx27.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/mach-imx/clk-imx27.c 2015-11-30 17:56:13.528141189 +0100 -@@ -229,7 +229,7 @@ - clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "ahb", "m2m-emmaprp.0"); - clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "ipg", "m2m-emmaprp.0"); - -- mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1); -+ mxc_timer_init(MX27_GPT1_BASE_ADDR, MX27_INT_GPT1); - - return 0; - } -diff -Nur linux-4.1.13.orig/arch/arm/mach-imx/clk-imx31.c linux-4.1.13/arch/arm/mach-imx/clk-imx31.c ---- linux-4.1.13.orig/arch/arm/mach-imx/clk-imx31.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/mach-imx/clk-imx31.c 2015-11-30 17:56:13.528141189 +0100 -@@ -50,9 +50,12 @@ - - int __init mx31_clocks_init(unsigned long fref) - { -- void __iomem *base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR); -+ void __iomem *base; - struct device_node *np; - -+ base = ioremap(MX31_CCM_BASE_ADDR, SZ_4K); -+ BUG_ON(!base); -+ - clk[dummy] = imx_clk_fixed("dummy", 0); - clk[ckih] = imx_clk_fixed("ckih", fref); - clk[ckil] = imx_clk_fixed("ckil", 32768); -@@ -182,7 +185,7 @@ - mx31_revision(); - clk_disable_unprepare(clk[iim_gate]); - -- mxc_timer_init(MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR), MX31_INT_GPT); -+ mxc_timer_init(MX31_GPT1_BASE_ADDR, MX31_INT_GPT); - - return 0; - } -diff -Nur linux-4.1.13.orig/arch/arm/mach-imx/clk-imx35.c linux-4.1.13/arch/arm/mach-imx/clk-imx35.c ---- linux-4.1.13.orig/arch/arm/mach-imx/clk-imx35.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/mach-imx/clk-imx35.c 2015-11-30 17:56:13.528141189 +0100 -@@ -71,11 +71,14 @@ - - int __init mx35_clocks_init(void) - { -- void __iomem *base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR); -+ void __iomem *base; - u32 pdr0, consumer_sel, hsp_sel; - struct arm_ahb_div *aad; - unsigned char *hsp_div; - -+ base = ioremap(MX35_CCM_BASE_ADDR, SZ_4K); -+ BUG_ON(!base); -+ - pdr0 = __raw_readl(base + MXC_CCM_PDR0); - consumer_sel = (pdr0 >> 16) & 0xf; - aad = &clk_consumer[consumer_sel]; -@@ -279,7 +282,7 @@ - #ifdef CONFIG_MXC_USE_EPIT - epit_timer_init(MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1); - #else -- mxc_timer_init(MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT); -+ mxc_timer_init(MX35_GPT1_BASE_ADDR, MX35_INT_GPT); - #endif - - return 0; -diff -Nur linux-4.1.13.orig/arch/arm/mach-imx/clk-imx6q.c linux-4.1.13/arch/arm/mach-imx/clk-imx6q.c ---- linux-4.1.13.orig/arch/arm/mach-imx/clk-imx6q.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/mach-imx/clk-imx6q.c 2015-11-30 17:56:13.532140921 +0100 -@@ -24,7 +24,6 @@ - #include "clk.h" - #include "common.h" - #include "hardware.h" -- - static const char *step_sels[] = { "osc", "pll2_pfd2_396m", }; - static const char *pll1_sw_sels[] = { "pll1_sys", "step", }; - static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", }; -@@ -32,7 +31,8 @@ - static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; - static const char *periph_sels[] = { "periph_pre", "periph_clk2", }; - static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", }; --static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", }; -+static const char *axi_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_540m", }; -+static const char *axi_sels[] = { "periph", "axi_alt_sel", }; - static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", }; - static const char *gpu_axi_sels[] = { "axi", "ahb", }; - static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", }; -@@ -40,6 +40,8 @@ - static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m", }; - static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", }; - static const char *ldb_di_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", }; -+static const char *ldb_di0_div_sels[] = { "ldb_di0_div_3_5", "ldb_di0_div_7", }; -+static const char *ldb_di1_div_sels[] = { "ldb_di1_div_3_5", "ldb_di1_div_7", }; - static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", }; - static const char *ipu1_di0_sels[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; - static const char *ipu1_di1_sels[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; -@@ -121,6 +123,18 @@ - static unsigned int share_count_ssi3; - static unsigned int share_count_mipi_core_cfg; - -+static void __iomem *ccm_base; -+ -+static inline int clk_on_imx6q(void) -+{ -+ return of_machine_is_compatible("fsl,imx6q"); -+} -+ -+static inline int clk_on_imx6dl(void) -+{ -+ return of_machine_is_compatible("fsl,imx6dl"); -+} -+ - static void __init imx6q_clocks_init(struct device_node *ccm_node) - { - struct device_node *np; -@@ -141,7 +155,7 @@ - WARN_ON(!base); - - /* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */ -- if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) { -+ if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) { - post_div_table[1].div = 1; - post_div_table[2].div = 1; - video_div_table[1].div = 1; -@@ -174,13 +188,13 @@ - clk[IMX6QDL_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); - - /* Do not bypass PLLs initially */ -- clk_set_parent(clk[IMX6QDL_PLL1_BYPASS], clk[IMX6QDL_CLK_PLL1]); -- clk_set_parent(clk[IMX6QDL_PLL2_BYPASS], clk[IMX6QDL_CLK_PLL2]); -- clk_set_parent(clk[IMX6QDL_PLL3_BYPASS], clk[IMX6QDL_CLK_PLL3]); -- clk_set_parent(clk[IMX6QDL_PLL4_BYPASS], clk[IMX6QDL_CLK_PLL4]); -- clk_set_parent(clk[IMX6QDL_PLL5_BYPASS], clk[IMX6QDL_CLK_PLL5]); -- clk_set_parent(clk[IMX6QDL_PLL6_BYPASS], clk[IMX6QDL_CLK_PLL6]); -- clk_set_parent(clk[IMX6QDL_PLL7_BYPASS], clk[IMX6QDL_CLK_PLL7]); -+ imx_clk_set_parent(clk[IMX6QDL_PLL1_BYPASS], clk[IMX6QDL_CLK_PLL1]); -+ imx_clk_set_parent(clk[IMX6QDL_PLL2_BYPASS], clk[IMX6QDL_CLK_PLL2]); -+ imx_clk_set_parent(clk[IMX6QDL_PLL3_BYPASS], clk[IMX6QDL_CLK_PLL3]); -+ imx_clk_set_parent(clk[IMX6QDL_PLL4_BYPASS], clk[IMX6QDL_CLK_PLL4]); -+ imx_clk_set_parent(clk[IMX6QDL_PLL5_BYPASS], clk[IMX6QDL_CLK_PLL5]); -+ imx_clk_set_parent(clk[IMX6QDL_PLL6_BYPASS], clk[IMX6QDL_CLK_PLL6]); -+ imx_clk_set_parent(clk[IMX6QDL_PLL7_BYPASS], clk[IMX6QDL_CLK_PLL7]); - - clk[IMX6QDL_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", base + 0x00, 13); - clk[IMX6QDL_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13); -@@ -248,7 +262,7 @@ - clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2); - clk[IMX6QDL_CLK_GPT_3M] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8); - clk[IMX6QDL_CLK_VIDEO_27M] = imx_clk_fixed_factor("video_27m", "pll3_pfd1_540m", 1, 20); -- if (cpu_is_imx6dl()) { -+ if (clk_on_imx6dl()) { - clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1); - clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1); - } -@@ -259,11 +273,9 @@ - clk[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); - - np = ccm_node; -- base = of_iomap(np, 0); -+ ccm_base = base = of_iomap(np, 0); - WARN_ON(!base); - -- imx6q_pm_set_ccm_base(base); -- - /* name reg shift width parent_names num_parents */ - clk[IMX6QDL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); - clk[IMX6QDL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); -@@ -271,11 +283,12 @@ - clk[IMX6QDL_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); - clk[IMX6QDL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); - clk[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); -- clk[IMX6QDL_CLK_AXI_SEL] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels)); -+ clk[IMX6QDL_CLK_AXI_ALT_SEL] = imx_clk_mux("axi_alt_sel", base + 0x14, 7, 1, axi_alt_sels, ARRAY_SIZE(axi_alt_sels)); -+ clk[IMX6QDL_CLK_AXI_SEL] = imx_clk_mux_glitchless("axi_sel", base + 0x14, 6, 1, axi_sels, ARRAY_SIZE(axi_sels)); - clk[IMX6QDL_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); - clk[IMX6QDL_CLK_ASRC_SEL] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); - clk[IMX6QDL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); -- if (cpu_is_imx6q()) { -+ if (clk_on_imx6q()) { - clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); - clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); - } -@@ -286,6 +299,8 @@ - clk[IMX6QDL_CLK_IPU2_SEL] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); - clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); - clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); -+ clk[IMX6QDL_CLK_LDB_DI0_DIV_SEL] = imx_clk_mux_flags("ldb_di0_div_sel", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels), CLK_SET_RATE_PARENT); -+ clk[IMX6QDL_CLK_LDB_DI1_DIV_SEL] = imx_clk_mux_flags("ldb_di1_div_sel", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels), CLK_SET_RATE_PARENT); - clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); - clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); - clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); -@@ -335,9 +350,9 @@ - clk[IMX6QDL_CLK_IPU1_PODF] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3); - clk[IMX6QDL_CLK_IPU2_PODF] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3); - clk[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); -- clk[IMX6QDL_CLK_LDB_DI0_PODF] = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0); -+ clk[IMX6QDL_CLK_LDB_DI0_DIV_7] = imx_clk_fixed_factor("ldb_di0_div_7", "ldb_di0_sel", 1, 7); - clk[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); -- clk[IMX6QDL_CLK_LDB_DI1_PODF] = imx_clk_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0); -+ clk[IMX6QDL_CLK_LDB_DI1_DIV_7] = imx_clk_fixed_factor("ldb_di1_div_7", "ldb_di1_sel", 1, 7); - clk[IMX6QDL_CLK_IPU1_DI0_PRE] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3); - clk[IMX6QDL_CLK_IPU1_DI1_PRE] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3); - clk[IMX6QDL_CLK_IPU2_DI0_PRE] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3); -@@ -378,11 +393,13 @@ - clk[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16); - clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18); - clk[IMX6QDL_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20); -+ clk[IMX6QDL_CLK_DCIC1] = imx_clk_gate2("dcic1", "ipu1_podf", base + 0x68, 24); -+ clk[IMX6QDL_CLK_DCIC2] = imx_clk_gate2("dcic2", "ipu2_podf", base + 0x68, 26); - clk[IMX6QDL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0); - clk[IMX6QDL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2); - clk[IMX6QDL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4); - clk[IMX6QDL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6); -- if (cpu_is_imx6dl()) -+ if (clk_on_imx6dl()) - clk[IMX6DL_CLK_I2C4] = imx_clk_gate2("i2c4", "ipg_per", base + 0x6c, 8); - else - clk[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8); -@@ -392,7 +409,7 @@ - clk[IMX6QDL_CLK_ESAI_MEM] = imx_clk_gate2_shared("esai_mem", "ahb", base + 0x6c, 16, &share_count_esai); - clk[IMX6QDL_CLK_GPT_IPG] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20); - clk[IMX6QDL_CLK_GPT_IPG_PER] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22); -- if (cpu_is_imx6dl()) -+ if (clk_on_imx6dl()) - /* - * The multiplexer and divider of imx6q clock gpu3d_shader get - * redefined/reused as gpu2d_core_sel and gpu2d_core_podf on imx6dl. -@@ -414,13 +431,13 @@ - clk[IMX6QDL_CLK_IPU1_DI1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4); - clk[IMX6QDL_CLK_IPU2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6); - clk[IMX6QDL_CLK_IPU2_DI0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8); -- clk[IMX6QDL_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12); -- clk[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14); - clk[IMX6QDL_CLK_IPU2_DI1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10); -+ clk[IMX6QDL_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_div_sel", base + 0x74, 12); -+ clk[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2("ldb_di1", "ldb_di1_div_sel", base + 0x74, 14); - clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2_shared("hsi_tx", "hsi_tx_podf", base + 0x74, 16, &share_count_mipi_core_cfg); - clk[IMX6QDL_CLK_MIPI_CORE_CFG] = imx_clk_gate2_shared("mipi_core_cfg", "video_27m", base + 0x74, 16, &share_count_mipi_core_cfg); - clk[IMX6QDL_CLK_MIPI_IPG] = imx_clk_gate2_shared("mipi_ipg", "ipg", base + 0x74, 16, &share_count_mipi_core_cfg); -- if (cpu_is_imx6dl()) -+ if (clk_on_imx6dl()) - /* - * The multiplexer and divider of the imx6q clock gpu2d get - * redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl. -@@ -470,7 +487,7 @@ - * The gpt_3m clock is not available on i.MX6Q TO1.0. Let's point it - * to clock gpt_ipg_per to ease the gpt driver code. - */ -- if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) -+ if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) - clk[IMX6QDL_CLK_GPT_3M] = clk[IMX6QDL_CLK_GPT_IPG_PER]; - - imx_check_clocks(clk, ARRAY_SIZE(clk)); -@@ -479,56 +496,114 @@ - clk_data.clk_num = ARRAY_SIZE(clk); - of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); - -+ clk_register_clkdev(clk[IMX6QDL_CLK_GPT_3M], "gpt_3m", "imx-gpt.0"); - clk_register_clkdev(clk[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL); - - if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) || -- cpu_is_imx6dl()) { -- clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); -- clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); -+ clk_on_imx6dl()) { -+ imx_clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); -+ imx_clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); - } - -- clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); -- clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); -- clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); -- clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); -- clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_SEL], clk[IMX6QDL_CLK_IPU1_DI0_PRE]); -- clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_SEL], clk[IMX6QDL_CLK_IPU1_DI1_PRE]); -- clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_SEL], clk[IMX6QDL_CLK_IPU2_DI0_PRE]); -- clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_SEL], clk[IMX6QDL_CLK_IPU2_DI1_PRE]); -+ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); -+ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); -+ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); -+ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); -+ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_SEL], clk[IMX6QDL_CLK_IPU1_DI0_PRE]); -+ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_SEL], clk[IMX6QDL_CLK_IPU1_DI1_PRE]); -+ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_SEL], clk[IMX6QDL_CLK_IPU2_DI0_PRE]); -+ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_SEL], clk[IMX6QDL_CLK_IPU2_DI1_PRE]); -+ imx_clk_set_rate(clk[IMX6QDL_CLK_PLL3_PFD1_540M], 540000000); -+ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_SEL], clk[IMX6QDL_CLK_PLL3_PFD1_540M]); -+ imx_clk_set_parent(clk[IMX6QDL_CLK_AXI_ALT_SEL], clk[IMX6QDL_CLK_PLL3_PFD1_540M]); -+ imx_clk_set_parent(clk[IMX6QDL_CLK_AXI_SEL], clk[IMX6QDL_CLK_AXI_ALT_SEL]); -+ /* set epdc/pxp axi clock to 200Mhz */ -+ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU2_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]); -+ imx_clk_set_rate(clk[IMX6QDL_CLK_IPU2], 200000000); -+ if (cpu_is_imx6q()) { -+ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU1_SEL], clk[IMX6QDL_CLK_MMDC_CH0_AXI]); -+ imx_clk_set_parent(clk[IMX6QDL_CLK_IPU2_SEL], clk[IMX6QDL_CLK_MMDC_CH0_AXI]); -+ } - - /* - * The gpmi needs 100MHz frequency in the EDO/Sync mode, - * We can not get the 100MHz from the pll2_pfd0_352m. - * So choose pll2_pfd2_396m as enfc_sel's parent. - */ -- clk_set_parent(clk[IMX6QDL_CLK_ENFC_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]); -- -- for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) -- clk_prepare_enable(clk[clks_init_on[i]]); -+ imx_clk_set_parent(clk[IMX6QDL_CLK_ENFC_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]); - -+ /* gpu clock initilazation */ -+ /* -+ * On mx6dl, 2d core clock sources(sel, podf) is from 3d -+ * shader core clock, but 3d shader clock multiplexer of -+ * mx6dl is different. For instance the equivalent of -+ * pll2_pfd_594M on mx6q is pll2_pfd_528M on mx6dl. -+ * Make a note here. -+ */ -+#if 1 -+ imx_clk_set_parent(clk[IMX6QDL_CLK_GPU3D_SHADER_SEL], clk[IMX6QDL_CLK_PLL2_PFD1_594M]); -+ if (cpu_is_imx6dl()) { -+ imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_SHADER], 528000000); -+ /* for mx6dl, change gpu3d_core parent to 594_PFD*/ -+ imx_clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL], clk[IMX6QDL_CLK_PLL2_PFD1_594M]); -+ imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_CORE], 528000000); -+ imx_clk_set_parent(clk[IMX6QDL_CLK_GPU2D_CORE_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]); -+ } else if (cpu_is_imx6q()) { -+ imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_SHADER], 594000000); -+ imx_clk_set_parent(clk[IMX6QDL_CLK_GPU3D_CORE_SEL], clk[IMX6QDL_CLK_MMDC_CH0_AXI]); -+ imx_clk_set_rate(clk[IMX6QDL_CLK_GPU3D_CORE], 528000000); -+ imx_clk_set_parent(clk[IMX6QDL_CLK_GPU2D_CORE_SEL], clk[IMX6QDL_CLK_PLL3_USB_OTG]); -+ imx_clk_set_rate(clk[IMX6QDL_CLK_GPU2D_CORE], 480000000); -+ } -+#endif - if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { -- clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]); -- clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]); -+ imx_clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]); -+ imx_clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]); - } - - /* - * Let's initially set up CLKO with OSC24M, since this configuration - * is widely used by imx6q board designs to clock audio codec. - */ -- ret = clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_OSC]); -+ ret = imx_clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_OSC]); - if (!ret) -- ret = clk_set_parent(clk[IMX6QDL_CLK_CKO], clk[IMX6QDL_CLK_CKO2]); -+ ret = imx_clk_set_parent(clk[IMX6QDL_CLK_CKO], clk[IMX6QDL_CLK_CKO2]); - if (ret) - pr_warn("failed to set up CLKO: %d\n", ret); - - /* Audio-related clocks configuration */ -- clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL], clk[IMX6QDL_CLK_PLL3_PFD3_454M]); -+ imx_clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL], clk[IMX6QDL_CLK_PLL3_PFD3_454M]); - - /* All existing boards with PCIe use LVDS1 */ - if (IS_ENABLED(CONFIG_PCI_IMX6)) -- clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]); -+ imx_clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]); -+ -+ /* -+ * Enable clocks only after both parent and rate are all initialized -+ * as needed -+ */ -+ for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) -+ imx_clk_prepare_enable(clk[clks_init_on[i]]); -+ -+ imx_clk_set_parent(clk[IMX6QDL_CLK_VPU_AXI_SEL], clk[IMX6QDL_CLK_PLL2_PFD0_352M]); -+ -+ if (cpu_is_imx6dl()) -+ imx_clk_set_rate(clk[IMX6QDL_CLK_PLL2_PFD0_352M], 306000000); -+ else -+ imx_clk_set_rate(clk[IMX6QDL_CLK_PLL2_PFD0_352M], 327000000); - -- /* Set initial power mode */ -- imx6q_set_lpm(WAIT_CLOCKED); -+ /* -+ * If VPU 352M is enabled, then PLL2_PDF2 need to be -+ * set to 352M, cpufreq will be disabled as VDDSOC/PU -+ * need to be at highest voltage, scaling cpu freq is -+ * not saving any power, and busfreq will be also disabled -+ * as the PLL2_PFD2 is not at default freq, in a word, -+ * all modules that sourceing clk from PLL2_PFD2 will -+ * be impacted. -+ */ -+ if (vpu352) { -+ imx_clk_set_rate(clk[IMX6QDL_CLK_PLL2_PFD0_352M], 352000000); -+ pr_info("VPU 352M is enabled!\n"); -+ } - } - CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init); -diff -Nur linux-4.1.13.orig/arch/arm/mach-imx/clk-imx6sl.c linux-4.1.13/arch/arm/mach-imx/clk-imx6sl.c ---- linux-4.1.13.orig/arch/arm/mach-imx/clk-imx6sl.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/mach-imx/clk-imx6sl.c 2015-11-30 17:56:13.532140921 +0100 -@@ -288,9 +288,6 @@ - WARN_ON(!base); - ccm_base = base; - -- /* Reuse imx6q pm code */ -- imx6q_pm_set_ccm_base(base); -- - /* name reg shift width parent_names num_parents */ - clks[IMX6SL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); - clks[IMX6SL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); -@@ -443,8 +440,5 @@ - - clk_set_parent(clks[IMX6SL_CLK_LCDIF_AXI_SEL], - clks[IMX6SL_CLK_PLL2_PFD2]); -- -- /* Set initial power mode */ -- imx6q_set_lpm(WAIT_CLOCKED); - } - CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init); -diff -Nur linux-4.1.13.orig/arch/arm/mach-imx/clk-imx6sx.c linux-4.1.13/arch/arm/mach-imx/clk-imx6sx.c ---- linux-4.1.13.orig/arch/arm/mach-imx/clk-imx6sx.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/mach-imx/clk-imx6sx.c 2015-11-30 17:56:13.532140921 +0100 -@@ -268,8 +268,6 @@ - base = of_iomap(np, 0); - WARN_ON(!base); - -- imx6q_pm_set_ccm_base(base); -- - /* name reg shift width parent_names num_parents */ - clks[IMX6SX_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); - clks[IMX6SX_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); -@@ -560,8 +558,5 @@ - - clk_set_parent(clks[IMX6SX_CLK_QSPI1_SEL], clks[IMX6SX_CLK_PLL2_BUS]); - clk_set_parent(clks[IMX6SX_CLK_QSPI2_SEL], clks[IMX6SX_CLK_PLL2_BUS]); -- -- /* Set initial power mode */ -- imx6q_set_lpm(WAIT_CLOCKED); - } - CLK_OF_DECLARE(imx6sx, "fsl,imx6sx-ccm", imx6sx_clocks_init); -diff -Nur linux-4.1.13.orig/arch/arm/mach-imx/clk-pllv3.c linux-4.1.13/arch/arm/mach-imx/clk-pllv3.c ---- linux-4.1.13.orig/arch/arm/mach-imx/clk-pllv3.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/mach-imx/clk-pllv3.c 2015-11-30 17:56:13.532140921 +0100 -@@ -23,6 +23,7 @@ - #define PLL_DENOM_OFFSET 0x20 - - #define BM_PLL_POWER (0x1 << 12) -+#define BM_PLL_BYPASS (0x1 << 16) - #define BM_PLL_LOCK (0x1 << 31) - - /** -@@ -237,9 +238,10 @@ - struct clk_pllv3 *pll = to_clk_pllv3(hw); - unsigned long min_rate = parent_rate * 27; - unsigned long max_rate = parent_rate * 54; -- u32 val, div; -+ u32 val, newval, div; - u32 mfn, mfd = 1000000; - s64 temp64; -+ int ret; - - if (rate < min_rate || rate > max_rate) - return -EINVAL; -@@ -251,13 +253,27 @@ - mfn = temp64; - - val = readl_relaxed(pll->base); -- val &= ~pll->div_mask; -- val |= div; -- writel_relaxed(val, pll->base); -+ -+ /* set the PLL into bypass mode */ -+ newval = val | BM_PLL_BYPASS; -+ writel_relaxed(newval, pll->base); -+ -+ /* configure the new frequency */ -+ newval &= ~pll->div_mask; -+ newval |= div; -+ writel_relaxed(newval, pll->base); - writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET); - writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET); - -- return clk_pllv3_wait_lock(pll); -+ ret = clk_pllv3_wait_lock(pll); -+ if (ret == 0 && val & BM_PLL_POWER) { -+ /* only if it locked can we switch back to the PLL */ -+ newval &= ~BM_PLL_BYPASS; -+ newval |= val & BM_PLL_BYPASS; -+ writel_relaxed(newval, pll->base); -+ } -+ -+ return ret; - } - - static const struct clk_ops clk_pllv3_av_ops = { -diff -Nur linux-4.1.13.orig/arch/arm/mach-imx/common.h linux-4.1.13/arch/arm/mach-imx/common.h ---- linux-4.1.13.orig/arch/arm/mach-imx/common.h 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/mach-imx/common.h 2015-11-30 17:56:13.532140921 +0100 -@@ -44,7 +44,7 @@ - void imx31_soc_init(void); - void imx35_soc_init(void); - void epit_timer_init(void __iomem *base, int irq); --void mxc_timer_init(void __iomem *, int); -+void mxc_timer_init(unsigned long, int); - int mx1_clocks_init(unsigned long fref); - int mx21_clocks_init(unsigned long lref, unsigned long fref); - int mx27_clocks_init(unsigned long fref); -@@ -56,6 +56,7 @@ - void mxc_set_cpu_type(unsigned int type); - void mxc_restart(enum reboot_mode, const char *); - void mxc_arch_reset_init(void __iomem *); -+void mxc_arch_reset_init_dt(void); - int mx51_revision(void); - int mx53_revision(void); - void imx_set_aips(void __iomem *); -@@ -86,6 +87,8 @@ - MX3_SLEEP, - }; - -+extern int vpu352; -+ - void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode); - void imx_print_silicon_rev(const char *cpu, int srev); - -@@ -102,6 +105,7 @@ - static inline void imx_smp_prepare(void) {} - #endif - void imx_src_init(void); -+ - void imx_gpc_pre_suspend(bool arm_power_off); - void imx_gpc_post_resume(void); - void imx_gpc_mask_all(void); -@@ -111,10 +115,11 @@ - void imx_anatop_init(void); - void imx_anatop_pre_suspend(void); - void imx_anatop_post_resume(void); --int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); -+int imx6_set_lpm(enum mxc_cpu_pwr_mode mode); - void imx6q_set_int_mem_clk_lpm(bool enable); - void imx6sl_set_wait_clk(bool enter); - int imx_mmdc_get_ddr_type(void); -+void imx6_enet_mac_init(const char *compatible); - - void imx_cpu_die(unsigned int cpu); - int imx_cpu_kill(unsigned int cpu); -@@ -127,11 +132,11 @@ - static inline void imx6_suspend(void __iomem *ocram_vbase) {} - #endif - -+void imx6_pm_ccm_init(const char *ccm_compat); - void imx6q_pm_init(void); - void imx6dl_pm_init(void); - void imx6sl_pm_init(void); - void imx6sx_pm_init(void); --void imx6q_pm_set_ccm_base(void __iomem *base); - - #ifdef CONFIG_PM - void imx51_pm_init(void); -diff -Nur linux-4.1.13.orig/arch/arm/mach-imx/common-imx6.c linux-4.1.13/arch/arm/mach-imx/common-imx6.c ---- linux-4.1.13.orig/arch/arm/mach-imx/common-imx6.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/arch/arm/mach-imx/common-imx6.c 2015-11-30 17:56:13.532140921 +0100 -@@ -0,0 +1,96 @@ -+/* -+ * Copyright 2011-2015 Freescale Semiconductor, Inc. -+ * Copyright 2011 Linaro Ltd. -+ * -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+#include -+#include -+#include -+#include -+ -+#include "common.h" -+#define OCOTP_MACn(n) (0x00000620 + (n) * 0x10) -+ -+void __init imx6_enet_mac_init(const char *compatible) -+{ -+ struct device_node *ocotp_np, *enet_np, *from = NULL; -+ void __iomem *base; -+ struct property *newmac; -+ u32 macaddr_low; -+ u32 macaddr_high = 0; -+ u32 macaddr1_high = 0; -+ u8 *macaddr; -+ int i; -+ -+ for (i = 0; i < 2; i++) { -+ enet_np = of_find_compatible_node(from, NULL, compatible); -+ if (!enet_np) -+ return; -+ -+ from = enet_np; -+ -+ if (of_get_mac_address(enet_np)) -+ goto put_enet_node; -+ -+ ocotp_np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp"); -+ if (!ocotp_np) { -+ pr_warn("failed to find ocotp node\n"); -+ goto put_enet_node; -+ } -+ -+ base = of_iomap(ocotp_np, 0); -+ if (!base) { -+ pr_warn("failed to map ocotp\n"); -+ goto put_ocotp_node; -+ } -+ -+ macaddr_low = readl_relaxed(base + OCOTP_MACn(1)); -+ if (i) -+ macaddr1_high = readl_relaxed(base + OCOTP_MACn(2)); -+ else -+ macaddr_high = readl_relaxed(base + OCOTP_MACn(0)); -+ -+ newmac = kzalloc(sizeof(*newmac) + 6, GFP_KERNEL); -+ if (!newmac) -+ goto put_ocotp_node; -+ -+ newmac->value = newmac + 1; -+ newmac->length = 6; -+ newmac->name = kstrdup("local-mac-address", GFP_KERNEL); -+ if (!newmac->name) { -+ kfree(newmac); -+ goto put_ocotp_node; -+ } -+ -+ macaddr = newmac->value; -+ if (i) { -+ macaddr[5] = (macaddr_low >> 16) & 0xff; -+ macaddr[4] = (macaddr_low >> 24) & 0xff; -+ macaddr[3] = macaddr1_high & 0xff; -+ macaddr[2] = (macaddr1_high >> 8) & 0xff; -+ macaddr[1] = (macaddr1_high >> 16) & 0xff; -+ macaddr[0] = (macaddr1_high >> 24) & 0xff; -+ } else { -+ macaddr[5] = macaddr_high & 0xff; -+ macaddr[4] = (macaddr_high >> 8) & 0xff; -+ macaddr[3] = (macaddr_high >> 16) & 0xff; -+ macaddr[2] = (macaddr_high >> 24) & 0xff; -+ macaddr[1] = macaddr_low & 0xff; -+ macaddr[0] = (macaddr_low >> 8) & 0xff; -+ } -+ -+ of_update_property(enet_np, newmac); -+ -+put_ocotp_node: -+ of_node_put(ocotp_np); -+put_enet_node: -+ of_node_put(enet_np); -+ } -+} -+ -diff -Nur linux-4.1.13.orig/arch/arm/mach-imx/cpuidle-imx6q.c linux-4.1.13/arch/arm/mach-imx/cpuidle-imx6q.c ---- linux-4.1.13.orig/arch/arm/mach-imx/cpuidle-imx6q.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/mach-imx/cpuidle-imx6q.c 2015-11-30 17:56:13.532140921 +0100 -@@ -27,9 +27,9 @@ - */ - if (!spin_trylock(&master_lock)) - goto idle; -- imx6q_set_lpm(WAIT_UNCLOCKED); -+ imx6_set_lpm(WAIT_UNCLOCKED); - cpu_do_idle(); -- imx6q_set_lpm(WAIT_CLOCKED); -+ imx6_set_lpm(WAIT_CLOCKED); - spin_unlock(&master_lock); - goto done; - } -diff -Nur linux-4.1.13.orig/arch/arm/mach-imx/cpuidle-imx6sl.c linux-4.1.13/arch/arm/mach-imx/cpuidle-imx6sl.c ---- linux-4.1.13.orig/arch/arm/mach-imx/cpuidle-imx6sl.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/mach-imx/cpuidle-imx6sl.c 2015-11-30 17:56:13.532140921 +0100 -@@ -16,7 +16,7 @@ - static int imx6sl_enter_wait(struct cpuidle_device *dev, - struct cpuidle_driver *drv, int index) - { -- imx6q_set_lpm(WAIT_UNCLOCKED); -+ imx6_set_lpm(WAIT_UNCLOCKED); - /* - * Software workaround for ERR005311, see function - * description for details. -@@ -24,7 +24,7 @@ - imx6sl_set_wait_clk(true); - cpu_do_idle(); - imx6sl_set_wait_clk(false); -- imx6q_set_lpm(WAIT_CLOCKED); -+ imx6_set_lpm(WAIT_CLOCKED); - - return index; - } -diff -Nur linux-4.1.13.orig/arch/arm/mach-imx/cpuidle-imx6sx.c linux-4.1.13/arch/arm/mach-imx/cpuidle-imx6sx.c ---- linux-4.1.13.orig/arch/arm/mach-imx/cpuidle-imx6sx.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/mach-imx/cpuidle-imx6sx.c 2015-11-30 17:56:13.532140921 +0100 -@@ -25,7 +25,7 @@ - static int imx6sx_enter_wait(struct cpuidle_device *dev, - struct cpuidle_driver *drv, int index) - { -- imx6q_set_lpm(WAIT_UNCLOCKED); -+ imx6_set_lpm(WAIT_UNCLOCKED); - - switch (index) { - case 1: -@@ -50,7 +50,7 @@ - break; - } - -- imx6q_set_lpm(WAIT_CLOCKED); -+ imx6_set_lpm(WAIT_CLOCKED); - - return index; - } -diff -Nur linux-4.1.13.orig/arch/arm/mach-imx/ddr3_freq_imx6.S linux-4.1.13/arch/arm/mach-imx/ddr3_freq_imx6.S ---- linux-4.1.13.orig/arch/arm/mach-imx/ddr3_freq_imx6.S 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/arch/arm/mach-imx/ddr3_freq_imx6.S 2015-11-30 17:56:13.532140921 +0100 -@@ -0,0 +1,893 @@ -+/* -+ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -+ */ -+ -+#include -+ -+#define MMDC0_MDPDC 0x4 -+#define MMDC0_MDCF0 0x0c -+#define MMDC0_MDCF1 0x10 -+#define MMDC0_MDMISC 0x18 -+#define MMDC0_MDSCR 0x1c -+#define MMDC0_MAPSR 0x404 -+#define MMDC0_MADPCR0 0x410 -+#define MMDC0_MPZQHWCTRL 0x800 -+#define MMDC1_MPZQHWCTRL 0x4800 -+#define MMDC0_MPODTCTRL 0x818 -+#define MMDC1_MPODTCTRL 0x4818 -+#define MMDC0_MPDGCTRL0 0x83c -+#define MMDC1_MPDGCTRL0 0x483c -+#define MMDC0_MPMUR0 0x8b8 -+#define MMDC1_MPMUR0 0x48b8 -+ -+#define CCM_CBCDR 0x14 -+#define CCM_CBCMR 0x18 -+#define CCM_CSCMR1 0x1c -+#define CCM_CDHIPR 0x48 -+ -+#define L2_CACHE_SYNC 0x730 -+ -+ .align 3 -+ -+ .macro switch_to_528MHz -+ -+ /* check if periph_clk_sel is already set */ -+ ldr r0, [r6, #CCM_CBCDR] -+ and r0, r0, #(1 << 25) -+ cmp r0, #(1 << 25) -+ beq set_ahb_podf_before_switch -+ -+ /* change periph_clk to be sourced from pll3_clk. */ -+ ldr r0, [r6, #CCM_CBCMR] -+ bic r0, r0, #(3 << 12) -+ str r0, [r6, #CCM_CBCMR] -+ -+ ldr r0, [r6, #CCM_CBCDR] -+ bic r0, r0, #(0x38 << 20) -+ str r0, [r6, #CCM_CBCDR] -+ -+ /* -+ * set the AHB dividers before the switch, -+ * don't change AXI clock divider, -+ * set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=4, -+ */ -+ ldr r0, [r6, #CCM_CBCDR] -+ ldr r2, =0x3f1f00 -+ bic r0, r0, r2 -+ orr r0, r0, #0xd00 -+ orr r0, r0, #(1 << 16) -+ str r0, [r6, #CCM_CBCDR] -+ -+wait_div_update528: -+ ldr r0, [r6, #CCM_CDHIPR] -+ cmp r0, #0 -+ bne wait_div_update528 -+ -+ /* now switch periph_clk to pll3_main_clk. */ -+ ldr r0, [r6, #CCM_CBCDR] -+ orr r0, r0, #(1 << 25) -+ str r0, [r6, #CCM_CBCDR] -+ -+periph_clk_switch3: -+ ldr r0, [r6, #CCM_CDHIPR] -+ cmp r0, #0 -+ bne periph_clk_switch3 -+ -+ b switch_pre_periph_clk_528 -+ -+set_ahb_podf_before_switch: -+ /* -+ * set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=4, -+ */ -+ ldr r0, [r6, #CCM_CBCDR] -+ ldr r2, =0x3f1f00 -+ bic r0, r0, r2 -+ orr r0, r0, #0xd00 -+ orr r0, r0, #(1 << 16) -+ str r0, [r6, #CCM_CBCDR] -+ -+wait_div_update528_1: -+ ldr r0, [r6, #CCM_CDHIPR] -+ cmp r0, #0 -+ bne wait_div_update528_1 -+ -+switch_pre_periph_clk_528: -+ -+ /* now switch pre_periph_clk to PLL2_528MHz. */ -+ ldr r0, [r6, #CCM_CBCMR] -+ bic r0, r0, #(0xc << 16) -+ str r0, [r6, #CCM_CBCMR] -+ -+ /* now switch periph_clk back. */ -+ ldr r0, [r6, #CCM_CBCDR] -+ bic r0, r0, #(1 << 25) -+ str r0, [r6, #CCM_CBCDR] -+ -+periph_clk_switch4: -+ ldr r0, [r6, #CCM_CDHIPR] -+ cmp r0, #0 -+ bne periph_clk_switch4 -+ -+ .endm -+ -+ .macro switch_to_400MHz -+ -+ /* check if periph_clk_sel is already set. */ -+ ldr r0, [r6, #CCM_CBCDR] -+ and r0, r0, #(1 << 25) -+ cmp r0, #(1 << 25) -+ beq set_ahb_podf_before_switch1 -+ -+ /* change periph_clk to be sourced from pll3_clk. */ -+ ldr r0, [r6, #CCM_CBCMR] -+ bic r0, r0, #(3 << 12) -+ str r0, [r6, #CCM_CBCMR] -+ -+ ldr r0, [r6, #CCM_CBCDR] -+ bic r0, r0, #(0x38 << 24) -+ str r0, [r6, #CCM_CBCDR] -+ -+ /* now switch periph_clk to pll3_main_clk. */ -+ ldr r0, [r6, #CCM_CBCDR] -+ orr r0, r0, #(1 << 25) -+ str r0, [r6, #CCM_CBCDR] -+ -+periph_clk_switch5: -+ ldr r0, [r6, #CCM_CDHIPR] -+ cmp r0, #0 -+ bne periph_clk_switch5 -+ -+ b switch_pre_periph_clk_400 -+ -+set_ahb_podf_before_switch1: -+ /* -+ * set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=4, -+ */ -+ ldr r0, [r6, #CCM_CBCDR] -+ ldr r2, =0x3f1f00 -+ bic r0, r0, r2 -+ orr r0, r0, #(0x9 << 8) -+ orr r0, r0, #(1 << 16) -+ str r0, [r6, #CCM_CBCDR] -+ -+wait_div_update400_1: -+ ldr r0, [r6, #CCM_CDHIPR] -+ cmp r0, #0 -+ bne wait_div_update400_1 -+ -+switch_pre_periph_clk_400: -+ -+ /* now switch pre_periph_clk to PFD_400MHz. */ -+ ldr r0, [r6, #CCM_CBCMR] -+ bic r0, r0, #(0xc << 16) -+ orr r0, r0, #(0x4 << 16) -+ str r0, [r6, #CCM_CBCMR] -+ -+ /* now switch periph_clk back. */ -+ ldr r0, [r6, #CCM_CBCDR] -+ bic r0, r0, #(1 << 25) -+ str r0, [r6, #CCM_CBCDR] -+ -+periph_clk_switch6: -+ ldr r0, [r6, #CCM_CDHIPR] -+ cmp r0, #0 -+ bne periph_clk_switch6 -+ -+ /* -+ * change AHB divider so that we are at 400/3=133MHz. -+ * don't change AXI clock divider. -+ * set the MMDC_DIV=1, AXI_DIV=2, AHB_DIV=3, -+ */ -+ ldr r0, [r6, #CCM_CBCDR] -+ ldr r2, =0x3f1f00 -+ bic r0, r0, r2 -+ orr r0, r0, #(0x9 << 8) -+ orr r0, r0, #(1 << 16) -+ str r0, [r6, #CCM_CBCDR] -+ -+wait_div_update400_2: -+ ldr r0, [r6, #CCM_CDHIPR] -+ cmp r0, #0 -+ bne wait_div_update400_2 -+ -+ .endm -+ -+ .macro switch_to_50MHz -+ -+ /* check if periph_clk_sel is already set. */ -+ ldr r0, [r6, #CCM_CBCDR] -+ and r0, r0, #(1 << 25) -+ cmp r0, #(1 << 25) -+ beq switch_pre_periph_clk_50 -+ -+ /* -+ * set the periph_clk to be sourced from PLL2_PFD_200M -+ * change periph_clk to be sourced from pll3_clk. -+ * ensure PLL3 is the source and set the divider to 1. -+ */ -+ ldr r0, [r6, #CCM_CBCMR] -+ bic r0, r0, #(0x3 << 12) -+ str r0, [r6, #CCM_CBCMR] -+ -+ ldr r0, [r6, #CCM_CBCDR] -+ bic r0, r0, #(0x38 << 24) -+ str r0, [r6, #CCM_CBCDR] -+ -+ /* now switch periph_clk to pll3_main_clk. */ -+ ldr r0, [r6, #CCM_CBCDR] -+ orr r0, r0, #(1 << 25) -+ str r0, [r6, #CCM_CBCDR] -+ -+periph_clk_switch_50: -+ ldr r0, [r6, #CCM_CDHIPR] -+ cmp r0, #0 -+ bne periph_clk_switch_50 -+ -+switch_pre_periph_clk_50: -+ -+ /* now switch pre_periph_clk to PFD_200MHz. */ -+ ldr r0, [r6, #CCM_CBCMR] -+ orr r0, r0, #(0xc << 16) -+ str r0, [r6, #CCM_CBCMR] -+ -+ /* -+ * set the MMDC_DIV=4, AXI_DIV = 4, AHB_DIV=8, -+ */ -+ ldr r0, [r6, #CCM_CBCDR] -+ ldr r2, =0x3f1f00 -+ bic r0, r0, r2 -+ orr r0, r0, #(0x18 << 16) -+ orr r0, r0, #(0x3 << 16) -+ -+ /* -+ * if changing AHB divider remember to change -+ * the IPGPER divider too below. -+ */ -+ orr r0, r0, #0x1d00 -+ str r0, [r6, #CCM_CBCDR] -+ -+wait_div_update_50: -+ ldr r0, [r6, #CCM_CDHIPR] -+ cmp r0, #0 -+ bne wait_div_update_50 -+ -+ /* now switch periph_clk back. */ -+ ldr r0, [r6, #CCM_CBCDR] -+ bic r0, r0, #(1 << 25) -+ str r0, [r6, #CCM_CBCDR] -+ -+periph_clk_switch2: -+ ldr r0, [r6, #CCM_CDHIPR] -+ cmp r0, #0 -+ bne periph_clk_switch2 -+ -+ .endm -+ -+ .macro switch_to_24MHz -+ /* -+ * change the freq now try setting DDR to 24MHz. -+ * source it from the periph_clk2 ensure the -+ * periph_clk2 is sourced from 24MHz and the -+ * divider is 1. -+ */ -+ -+ ldr r0, [r6, #CCM_CBCMR] -+ bic r0, r0, #(0x3 << 12) -+ orr r0, r0, #(1 << 12) -+ str r0, [r6, #CCM_CBCMR] -+ -+ ldr r0, [r6, #CCM_CBCDR] -+ bic r0, r0, #(0x38 << 24) -+ str r0, [r6, #CCM_CBCDR] -+ -+ /* now switch periph_clk to 24MHz. */ -+ ldr r0, [r6, #CCM_CBCDR] -+ orr r0, r0, #(1 << 25) -+ str r0, [r6, #CCM_CBCDR] -+ -+periph_clk_switch1: -+ ldr r0, [r6, #CCM_CDHIPR] -+ cmp r0, #0 -+ bne periph_clk_switch1 -+ -+ /* change all the dividers to 1. */ -+ ldr r0, [r6, #CCM_CBCDR] -+ ldr r2, =0x3f1f00 -+ bic r0, r0, r2 -+ orr r0, r0, #(1 << 8) -+ str r0, [r6, #CCM_CBCDR] -+ -+ /* Wait for the divider to change. */ -+wait_div_update: -+ ldr r0, [r6, #CCM_CDHIPR] -+ cmp r0, #0 -+ bne wait_div_update -+ -+ .endm -+ -+/* -+ * mx6_ddr3_freq_change -+ * -+ * idle the processor (eg, wait for interrupt). -+ * make sure DDR is in self-refresh. -+ * IRQs are already disabled. -+ */ -+ENTRY(mx6_ddr3_freq_change) -+ -+ stmfd sp!, {r4-r12} -+ -+ /* -+ * r5 -> mmdc_base -+ * r6 -> ccm_base -+ * r7 -> iomux_base -+ * r12 -> l2_base -+ */ -+ mov r4, r0 -+ mov r8, r1 -+ mov r9, r2 -+ mov r11, r3 -+ -+ /* -+ * Get the addresses of the registers. -+ * They are last few entries in the -+ * ddr_settings parameter. -+ * The first entry contains the count, -+ * and each entry is 2 words. -+ */ -+ ldr r0, [r1] -+ add r0, r0, #1 -+ lsl r0, r0, #3 -+ add r1, r0, r1 -+ /* mmdc_base. */ -+ ldr r5, [r1] -+ add r1, #8 -+ /* ccm_base */ -+ ldr r6, [r1] -+ add r1, #8 -+ /*iomux_base */ -+ ldr r7, [r1] -+ add r1, #8 -+ /*l2_base */ -+ ldr r12, [r1] -+ -+ddr_freq_change: -+ /* -+ * make sure no TLB miss will occur when -+ * the DDR is in self refresh. invalidate -+ * TLB single entry to ensure that the -+ * address is not already in the TLB. -+ */ -+ -+ adr r10, ddr_freq_change -+ -+ ldr r2, [r6] -+ ldr r2, [r5] -+ ldr r2, [r7] -+ ldr r2, [r8] -+ ldr r2, [r10] -+ ldr r2, [r11] -+ ldr r2, [r12] -+ -+#ifdef CONFIG_CACHE_L2X0 -+ /* -+ * Make sure the L2 buffers are drained. -+ * Sync operation on L2 drains the buffers. -+ */ -+ mov r1, #0x0 -+ str r1, [r12, #L2_CACHE_SYNC] -+#endif -+ -+ /* disable automatic power saving. */ -+ ldr r0, [r5, #MMDC0_MAPSR] -+ orr r0, r0, #0x01 -+ str r0, [r5, #MMDC0_MAPSR] -+ -+ /* disable MMDC power down timer. */ -+ ldr r0, [r5, #MMDC0_MDPDC] -+ bic r0, r0, #(0xff << 8) -+ str r0, [r5, #MMDC0_MDPDC] -+ -+ /* delay for a while */ -+ ldr r1, =4 -+delay1: -+ ldr r2, =0 -+cont1: -+ ldr r0, [r5, r2] -+ add r2, r2, #4 -+ cmp r2, #16 -+ bne cont1 -+ sub r1, r1, #1 -+ cmp r1, #0 -+ bgt delay1 -+ -+ /* set CON_REG */ -+ ldr r0, =0x8000 -+ str r0, [r5, #MMDC0_MDSCR] -+poll_conreq_set_1: -+ ldr r0, [r5, #MMDC0_MDSCR] -+ and r0, r0, #(0x4 << 12) -+ cmp r0, #(0x4 << 12) -+ bne poll_conreq_set_1 -+ -+ ldr r0, =0x00008050 -+ str r0, [r5, #MMDC0_MDSCR] -+ ldr r0, =0x00008058 -+ str r0, [r5, #MMDC0_MDSCR] -+ -+ /* -+ * if requested frequency is greater than -+ * 300MHz go to DLL on mode. -+ */ -+ ldr r1, =300000000 -+ cmp r4, r1 -+ bge dll_on_mode -+ -+dll_off_mode: -+ -+ /* if DLL is currently on, turn it off. */ -+ cmp r9, #1 -+ beq continue_dll_off_1 -+ -+ ldr r0, =0x00018031 -+ str r0, [r5, #MMDC0_MDSCR] -+ -+ ldr r0, =0x00018039 -+ str r0, [r5, #MMDC0_MDSCR] -+ -+ ldr r1, =10 -+delay1a: -+ ldr r2, =0 -+cont1a: -+ ldr r0, [r5, r2] -+ add r2, r2, #4 -+ cmp r2, #16 -+ bne cont1a -+ sub r1, r1, #1 -+ cmp r1, #0 -+ bgt delay1a -+ -+continue_dll_off_1: -+ /* set DVFS - enter self refresh mode */ -+ ldr r0, [r5, #MMDC0_MAPSR] -+ orr r0, r0, #(1 << 21) -+ str r0, [r5, #MMDC0_MAPSR] -+ -+ /* de-assert con_req */ -+ mov r0, #0x0 -+ str r0, [r5, #MMDC0_MDSCR] -+ -+poll_dvfs_set_1: -+ ldr r0, [r5, #MMDC0_MAPSR] -+ and r0, r0, #(1 << 25) -+ cmp r0, #(1 << 25) -+ bne poll_dvfs_set_1 -+ -+ ldr r1, =24000000 -+ cmp r4, r1 -+ beq switch_freq_24 -+ -+ switch_to_50MHz -+ b continue_dll_off_2 -+ -+switch_freq_24: -+ switch_to_24MHz -+ -+continue_dll_off_2: -+ -+ /* set SBS - block ddr accesses */ -+ ldr r0, [r5, #MMDC0_MADPCR0] -+ orr r0, r0, #(1 << 8) -+ str r0, [r5, #MMDC0_MADPCR0] -+ -+ /* clear DVFS - exit from self refresh mode */ -+ ldr r0, [r5, #MMDC0_MAPSR] -+ bic r0, r0, #(1 << 21) -+ str r0, [r5, #MMDC0_MAPSR] -+ -+poll_dvfs_clear_1: -+ ldr r0, [r5, #MMDC0_MAPSR] -+ and r0, r0, #(1 << 25) -+ cmp r0, #(1 << 25) -+ beq poll_dvfs_clear_1 -+ -+ /* if DLL was previously on, continue DLL off routine. */ -+ cmp r9, #1 -+ beq continue_dll_off_3 -+ -+ ldr r0, =0x00018031 -+ str r0, [r5, #MMDC0_MDSCR] -+ -+ ldr r0, =0x00018039 -+ str r0, [r5, #MMDC0_MDSCR] -+ -+ ldr r0, =0x08208030 -+ str r0, [r5, #MMDC0_MDSCR] -+ -+ ldr r0, =0x08208038 -+ str r0, [r5, #MMDC0_MDSCR] -+ -+ ldr r0, =0x00088032 -+ str r0, [r5, #MMDC0_MDSCR] -+ -+ ldr r0, =0x0008803A -+ str r0, [r5, #MMDC0_MDSCR] -+ -+ /* delay for a while. */ -+ ldr r1, =4 -+delay_1: -+ ldr r2, =0 -+cont_1: -+ ldr r0, [r5, r2] -+ add r2, r2, #4 -+ cmp r2, #16 -+ bne cont_1 -+ sub r1, r1, #1 -+ cmp r1, #0 -+ bgt delay_1 -+ -+ ldr r0, [r5, #MMDC0_MDCF0] -+ bic r0, r0, #0xf -+ orr r0, r0, #0x3 -+ str r0, [r5, #MMDC0_MDCF0] -+ -+ ldr r0, [r5, #MMDC0_MDCF1] -+ bic r0, r0, #0x7 -+ orr r0, r0, #0x4 -+ str r0, [r5, #MMDC0_MDCF1] -+ -+ ldr r0, =0x00011680 -+ str r0, [r5, #MMDC0_MDMISC] -+ -+ /* enable dqs pull down in the IOMUX. */ -+ ldr r1, [r11] -+ add r11, r11, #8 -+ ldr r2, =0x3028 -+update_iomux: -+ ldr r0, [r11, #0x0] -+ ldr r3, [r7, r0] -+ bic r3, r3, r2 -+ orr r3, r3, #(0x3 << 12) -+ orr r3, r3, #0x28 -+ str r3, [r7, r0] -+ add r11, r11, #8 -+ sub r1, r1, #1 -+ cmp r1, #0 -+ bgt update_iomux -+ -+ /* ODT disabled. */ -+ ldr r0, =0x0 -+ ldr r2, =MMDC0_MPODTCTRL -+ str r0, [r5, r2] -+ ldr r2, =MMDC1_MPODTCTRL -+ str r0, [r5, r2] -+ -+ /* DQS gating disabled. */ -+ ldr r2, =MMDC0_MPDGCTRL0 -+ ldr r0, [r5, r2] -+ orr r0, r0, #(1 << 29) -+ str r0, [r5, r2] -+ -+ ldr r2, =MMDC1_MPDGCTRL0 -+ ldr r0, [r5, r2] -+ orr r0, r0, #(0x1 << 29) -+ str r0, [r5, r2] -+ -+ /* MMDC0_MAPSR adopt power down enable. */ -+ ldr r0, [r5, #MMDC0_MAPSR] -+ bic r0, r0, #0x01 -+ str r0, [r5, #MMDC0_MAPSR] -+ -+ /* frc_msr + mu bypass */ -+ ldr r0, =0x00000060 -+ str r0, [r5, #MMDC0_MPMUR0] -+ ldr r2, =MMDC1_MPMUR0 -+ str r0, [r5, r2] -+ ldr r0, =0x00000460 -+ str r0, [r5, #MMDC0_MPMUR0] -+ ldr r2, =MMDC1_MPMUR0 -+ str r0, [r5, r2] -+ ldr r0, =0x00000c60 -+ str r0, [r5, #MMDC0_MPMUR0] -+ ldr r2, =MMDC1_MPMUR0 -+ str r0, [r5, r2] -+ -+continue_dll_off_3: -+ /* clear SBS - unblock accesses to DDR. */ -+ ldr r0, [r5, #MMDC0_MADPCR0] -+ bic r0, r0, #(0x1 << 8) -+ str r0, [r5, #MMDC0_MADPCR0] -+ -+ mov r0, #0x0 -+ str r0, [r5, #MMDC0_MDSCR] -+poll_conreq_clear_1: -+ ldr r0, [r5, #MMDC0_MDSCR] -+ and r0, r0, #(0x4 << 12) -+ cmp r0, #(0x4 << 12) -+ beq poll_conreq_clear_1 -+ -+ b done -+ -+dll_on_mode: -+ /* assert DVFS - enter self refresh mode. */ -+ ldr r0, [r5, #MMDC0_MAPSR] -+ orr r0, r0, #(1 << 21) -+ str r0, [r5, #MMDC0_MAPSR] -+ -+ /* de-assert CON_REQ. */ -+ mov r0, #0x0 -+ str r0, [r5, #MMDC0_MDSCR] -+ -+ /* poll DVFS ack. */ -+poll_dvfs_set_2: -+ ldr r0, [r5, #MMDC0_MAPSR] -+ and r0, r0, #(1 << 25) -+ cmp r0, #(1 << 25) -+ bne poll_dvfs_set_2 -+ -+ ldr r1, =528000000 -+ cmp r4, r1 -+ beq switch_freq_528 -+ -+ switch_to_400MHz -+ -+ b continue_dll_on -+ -+switch_freq_528: -+ switch_to_528MHz -+ -+continue_dll_on: -+ -+ /* set SBS step-by-step mode. */ -+ ldr r0, [r5, #MMDC0_MADPCR0] -+ orr r0, r0, #( 1 << 8) -+ str r0, [r5, #MMDC0_MADPCR0] -+ -+ /* clear DVFS - exit self refresh mode. */ -+ ldr r0, [r5, #MMDC0_MAPSR] -+ bic r0, r0, #(1 << 21) -+ str r0, [r5, #MMDC0_MAPSR] -+ -+poll_dvfs_clear_2: -+ ldr r0, [r5, #MMDC0_MAPSR] -+ and r0, r0, #(1 << 25) -+ cmp r0, #(1 << 25) -+ beq poll_dvfs_clear_2 -+ -+ /* if DLL is currently off, turn it back on. */ -+ cmp r9, #0 -+ beq update_calibration_only -+ -+ ldr r0, =0xa5390003 -+ str r0, [r5, #MMDC0_MPZQHWCTRL] -+ ldr r2, =MMDC1_MPZQHWCTRL -+ str r0, [r5, r2] -+ -+ /* enable DQS gating. */ -+ ldr r2, =MMDC0_MPDGCTRL0 -+ ldr r0, [r5, r2] -+ bic r0, r0, #(1 << 29) -+ str r0, [r5, r2] -+ -+ ldr r2, =MMDC1_MPDGCTRL0 -+ ldr r0, [r5, r2] -+ bic r0, r0, #(1 << 29) -+ str r0, [r5, r2] -+ -+ /* force measure. */ -+ ldr r0, =0x00000800 -+ str r0, [r5, #MMDC0_MPMUR0] -+ ldr r2, =MMDC1_MPMUR0 -+ str r0, [r5, r2] -+ -+ /* delay for while. */ -+ ldr r1, =4 -+delay5: -+ ldr r2, =0 -+cont5: -+ ldr r0, [r5, r2] -+ add r2, r2, #4 -+ cmp r2, #16 -+ bne cont5 -+ sub r1, r1, #1 -+ cmp r1, #0 -+ bgt delay5 -+ -+ /* disable dqs pull down in the IOMUX. */ -+ ldr r1, [r11] -+ add r11, r11, #8 -+update_iomux1: -+ ldr r0, [r11, #0x0] -+ ldr r3, [r11, #0x4] -+ str r3, [r7, r0] -+ add r11, r11, #8 -+ sub r1, r1, #1 -+ cmp r1, #0 -+ bgt update_iomux1 -+ -+ /* config MMDC timings to 528MHz. */ -+ ldr r9, [r8] -+ add r8, r8, #8 -+ ldr r0, [r8, #0x0] -+ ldr r3, [r8, #0x4] -+ str r3, [r5, r0] -+ add r8, r8, #8 -+ -+ ldr r0, [r8, #0x0] -+ ldr r3, [r8, #0x4] -+ str r3, [r5, r0] -+ add r8, r8, #8 -+ -+ /* update MISC register: WALAT, RALAT */ -+ ldr r0, =0x00001740 -+ str r0, [r5, #MMDC0_MDMISC] -+ -+ /* configure ddr devices to dll on, odt. */ -+ ldr r0, =0x00048031 -+ str r0, [r5, #MMDC0_MDSCR] -+ -+ ldr r0, =0x00048039 -+ str r0, [r5, #MMDC0_MDSCR] -+ -+ /* delay for while. */ -+ ldr r1, =4 -+delay7: -+ ldr r2, =0 -+cont7: -+ ldr r0, [r5, r2] -+ add r2, r2, #4 -+ cmp r2, #16 -+ bne cont7 -+ sub r1, r1, #1 -+ cmp r1, #0 -+ bgt delay7 -+ -+ /* reset dll. */ -+ ldr r0, =0x09408030 -+ str r0, [r5, #MMDC0_MDSCR] -+ -+ ldr r0, =0x09408038 -+ str r0, [r5, #MMDC0_MDSCR] -+ -+ /* delay for while. */ -+ ldr r1, =100 -+delay8: -+ ldr r2, =0 -+cont8: -+ ldr r0, [r5, r2] -+ add r2, r2, #4 -+ cmp r2, #16 -+ bne cont8 -+ sub r1, r1, #1 -+ cmp r1, #0 -+ bgt delay8 -+ -+ ldr r0, [r8, #0x0] -+ ldr r3, [r8, #0x4] -+ str r3, [r5, r0] -+ add r8, r8, #8 -+ -+ ldr r0, [r8, #0x0] -+ ldr r3, [r8, #0x4] -+ str r3, [r5, r0] -+ add r8, r8, #8 -+ -+ ldr r0, =0x00428031 -+ str r0, [r5, #MMDC0_MDSCR] -+ -+ ldr r0, =0x00428039 -+ str r0, [r5, #MMDC0_MDSCR] -+ -+ ldr r0, [r8, #0x0] -+ ldr r3, [r8, #0x4] -+ str r3, [r5, r0] -+ add r8, r8, #8 -+ -+ ldr r0, [r8, #0x0] -+ ldr r3, [r8, #0x4] -+ str r3, [r5, r0] -+ add r8, r8, #8 -+ -+ /* issue a zq command. */ -+ ldr r0, =0x04008040 -+ str r0, [r5, #MMDC0_MDSCR] -+ -+ ldr r0, =0x04008048 -+ str r0, [r5, #MMDC0_MDSCR] -+ -+ /* MMDC ODT enable. */ -+ ldr r0, [r8, #0x0] -+ ldr r3, [r8, #0x4] -+ str r3, [r5, r0] -+ add r8, r8, #8 -+ -+ ldr r2, =0x4818 -+ str r3, [r5, r2] -+ -+ /* delay for while. */ -+ ldr r1, =40 -+delay15: -+ ldr r2, =0 -+cont15: -+ ldr r0, [r5, r2] -+ add r2, r2, #4 -+ cmp r2, #16 -+ bne cont15 -+ sub r1, r1, #1 -+ cmp r1, #0 -+ bgt delay15 -+ -+ /* MMDC0_MAPSR adopt power down enable. */ -+ ldr r0, [r5, #MMDC0_MAPSR] -+ bic r0, r0, #0x01 -+ str r0, [r5, #MMDC0_MAPSR] -+ -+ /* enable MMDC power down timer. */ -+ ldr r0, [r5, #MMDC0_MDPDC] -+ orr r0, r0, #(0x55 << 8) -+ str r0, [r5, #MMDC0_MDPDC] -+ -+ b update_calibration -+ -+update_calibration_only: -+ ldr r1, [r8] -+ sub r1, r1, #7 -+ add r8, r8, #64 -+ b update_calib -+ -+update_calibration: -+ /* write the new calibration values. */ -+ mov r1, r9 -+ sub r1, r1, #7 -+ -+update_calib: -+ ldr r0, [r8, #0x0] -+ ldr r3, [r8, #0x4] -+ str r3, [r5, r0] -+ add r8, r8, #8 -+ sub r1, r1, #1 -+ cmp r1, #0 -+ bgt update_calib -+ -+ /* perform a force measurement. */ -+ ldr r0, =0x800 -+ str r0, [r5, #MMDC0_MPMUR0] -+ ldr r2, =MMDC1_MPMUR0 -+ str r0, [r5, r2] -+ -+ /* clear SBS - unblock DDR accesses. */ -+ ldr r0, [r5, #MMDC0_MADPCR0] -+ bic r0, r0, #(1 << 8) -+ str r0, [r5, #MMDC0_MADPCR0] -+ -+ mov r0, #0x0 -+ str r0, [r5, #MMDC0_MDSCR] -+poll_conreq_clear_2: -+ ldr r0, [r5, #MMDC0_MDSCR] -+ and r0, r0, #(0x4 << 12) -+ cmp r0, #(0x4 << 12) -+ beq poll_conreq_clear_2 -+ -+done: -+ /* restore registers */ -+ -+ ldmfd sp!, {r4-r12} -+ mov pc, lr -+ -+ .type mx6_do_ddr3_freq_change, #object -+ENTRY(mx6_do_ddr_freq_change) -+ .word mx6_ddr3_freq_change -+ .size mx6_ddr3_freq_change, . - mx6_ddr3_freq_change -diff -Nur linux-4.1.13.orig/arch/arm/mach-imx/Kconfig linux-4.1.13/arch/arm/mach-imx/Kconfig ---- linux-4.1.13.orig/arch/arm/mach-imx/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/mach-imx/Kconfig 2015-11-30 17:56:13.532140921 +0100 -@@ -8,6 +8,7 @@ - select PM_OPP if PM - select SOC_BUS - select SRAM -+ select ZONE_DMA - help - Support for Freescale MXC/iMX-based family of processors - -diff -Nur linux-4.1.13.orig/arch/arm/mach-imx/lpddr2_freq_imx6.S linux-4.1.13/arch/arm/mach-imx/lpddr2_freq_imx6.S ---- linux-4.1.13.orig/arch/arm/mach-imx/lpddr2_freq_imx6.S 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/arch/arm/mach-imx/lpddr2_freq_imx6.S 2015-11-30 17:56:13.532140921 +0100 -@@ -0,0 +1,484 @@ -+/* -+ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -+ */ -+ -+#include -+ -+ .macro mx6sl_switch_to_24MHz -+ -+ /* -+ * Set MMDC clock to be sourced from PLL3. -+ * Ensure first periph2_clk2 is sourced from PLL3. -+ * Set the PERIPH2_CLK2_PODF to divide by 2. -+ */ -+ ldr r6, [r2, #0x14] -+ bic r6, r6, #0x7 -+ orr r6, r6, #0x1 -+ str r6, [r2, #0x14] -+ -+ /* Select PLL3 to source MMDC. */ -+ ldr r6, [r2, #0x18] -+ bic r6, r6, #0x100000 -+ str r6, [r2, #0x18] -+ -+ /* Swtich periph2_clk_sel to run from PLL3. */ -+ ldr r6, [r2, #0x14] -+ orr r6, r6, #0x4000000 -+ str r6, [r2, #0x14] -+ -+periph2_clk_switch1: -+ ldr r6, [r2, #0x48] -+ cmp r6, #0 -+ bne periph2_clk_switch1 -+ -+ /* -+ * Need to clock gate the 528 PFDs before -+ * powering down PLL2. -+ * Only the PLL2_PFD2_400M should be ON -+ * at this time, so only clock gate that one. -+ */ -+ ldr r6, [r3, #0x100] -+ orr r6, r6, #0x800000 -+ str r6, [r3, #0x100] -+ -+ /* -+ * Set PLL2 to bypass state. We should be here -+ * only if MMDC is not sourced from PLL2. -+ */ -+ ldr r6, [r3, #0x30] -+ orr r6, r6, #0x10000 -+ str r6, [r3, #0x30] -+ -+ ldr r6, [r3, #0x30] -+ orr r6, r6, #0x1000 -+ str r6, [r3, #0x30] -+ -+ /* Ensure pre_periph2_clk_mux is set to pll2 */ -+ ldr r6, [r2, #0x18] -+ bic r6, r6, #0x600000 -+ str r6, [r2, #0x18] -+ -+ /* Set MMDC clock to be sourced from the bypassed PLL2. */ -+ ldr r6, [r2, #0x14] -+ bic r6, r6, #0x4000000 -+ str r6, [r2, #0x14] -+ -+periph2_clk_switch2: -+ ldr r6, [r2, #0x48] -+ cmp r6, #0 -+ bne periph2_clk_switch2 -+ -+ /* -+ * Now move MMDC back to periph2_clk2 source. -+ * after selecting PLL2 as the option. -+ * Select PLL2 as the source. -+ */ -+ ldr r6, [r2, #0x18] -+ orr r6, r6, #0x100000 -+ str r6, [r2, #0x18] -+ -+ /* set periph2_clk2_podf to divide by 1. */ -+ ldr r6, [r2, #0x14] -+ bic r6, r6, #0x7 -+ str r6, [r2, #0x14] -+ -+ /* Now move periph2_clk to periph2_clk2 source */ -+ ldr r6, [r2, #0x14] -+ orr r6, r6, #0x4000000 -+ str r6, [r2, #0x14] -+ -+periph2_clk_switch3: -+ ldr r6, [r2, #0x48] -+ cmp r6, #0 -+ bne periph2_clk_switch3 -+ -+ /* Now set the MMDC PODF back to 1.*/ -+ ldr r6, [r2, #0x14] -+ bic r6, r6, #0x38 -+ str r6, [r2, #0x14] -+ -+mmdc_podf0: -+ ldr r6, [r2, #0x48] -+ cmp r6, #0 -+ bne mmdc_podf0 -+ -+ .endm -+ -+ .macro ddr_switch_400MHz -+ -+ /* Set MMDC divider first, in case PLL3 is at 480MHz. */ -+ ldr r6, [r3, #0x10] -+ and r6, r6, #0x10000 -+ cmp r6, #0x10000 -+ beq pll3_in_bypass -+ -+ /* Set MMDC divder to divide by 2. */ -+ ldr r6, [r2, #0x14] -+ bic r6, r6, #0x38 -+ orr r6, r6, #0x8 -+ str r6, [r2, #0x14] -+ -+mmdc_podf: -+ ldr r6, [r2, #0x48] -+ cmp r6, #0 -+ bne mmdc_podf -+ -+pll3_in_bypass: -+ /* -+ * Check if we are switching between -+ * 400Mhz <-> 100MHz.If so, we should -+ * try to source MMDC from PLL2_200M. -+ */ -+ cmp r1, #0 -+ beq not_low_bus_freq -+ -+ /* Ensure that MMDC is sourced from PLL2 mux first. */ -+ ldr r6, [r2, #0x14] -+ bic r6, r6, #0x4000000 -+ str r6, [r2, #0x14] -+ -+periph2_clk_switch4: -+ ldr r6, [r2, #0x48] -+ cmp r6, #0 -+ bne periph2_clk_switch4 -+ -+not_low_bus_freq: -+ /* Now ensure periph2_clk2_sel mux is set to PLL3 */ -+ ldr r6, [r2, #0x18] -+ bic r6, r6, #0x100000 -+ str r6, [r2, #0x18] -+ -+ /* Now switch MMDC to PLL3. */ -+ ldr r6, [r2, #0x14] -+ orr r6, r6, #0x4000000 -+ str r6, [r2, #0x14] -+ -+periph2_clk_switch5: -+ ldr r6, [r2, #0x48] -+ cmp r6, #0 -+ bne periph2_clk_switch5 -+ -+ /* -+ * Check if PLL2 is already unlocked. -+ * If so do nothing with PLL2. -+ */ -+ cmp r1, #0 -+ beq pll2_already_on -+ -+ /* Now power up PLL2 and unbypass it. */ -+ ldr r6, [r3, #0x30] -+ bic r6, r6, #0x1000 -+ str r6, [r3, #0x30] -+ -+ /* Make sure PLL2 has locked.*/ -+wait_for_pll_lock: -+ ldr r6, [r3, #0x30] -+ and r6, r6, #0x80000000 -+ cmp r6, #0x80000000 -+ bne wait_for_pll_lock -+ -+ ldr r6, [r3, #0x30] -+ bic r6, r6, #0x10000 -+ str r6, [r3, #0x30] -+ -+ /* -+ * Need to enable the 528 PFDs after -+ * powering up PLL2. -+ * Only the PLL2_PFD2_400M should be ON -+ * as it feeds the MMDC. Rest should have -+ * been managed by clock code. -+ */ -+ ldr r6, [r3, #0x100] -+ bic r6, r6, #0x800000 -+ str r6, [r3, #0x100] -+ -+pll2_already_on: -+ /* -+ * Now switch MMDC clk back to pll2_mux option. -+ * Ensure pre_periph2_clk2 is set to pll2_pfd_400M. -+ * If switching to audio DDR freq, set the -+ * pre_periph2_clk2 to PLL2_PFD_200M -+ */ -+ ldr r6, =400000000 -+ cmp r6, r0 -+ bne use_pll2_pfd_200M -+ -+ ldr r6, [r2, #0x18] -+ bic r6, r6, #0x600000 -+ orr r6, r6, #0x200000 -+ str r6, [r2, #0x18] -+ ldr r6, =400000000 -+ b cont2 -+ -+use_pll2_pfd_200M: -+ ldr r6, [r2, #0x18] -+ orr r6, r6, #0x600000 -+ str r6, [r2, #0x18] -+ ldr r6, =200000000 -+ -+cont2: -+ ldr r4, [r2, #0x14] -+ bic r4, r4, #0x4000000 -+ str r4, [r2, #0x14] -+ -+periph2_clk_switch6: -+ ldr r4, [r2, #0x48] -+ cmp r4, #0 -+ bne periph2_clk_switch6 -+ -+change_divider_only: -+ /* -+ * Calculate the MMDC divider -+ * based on the requested freq. -+ */ -+ ldr r4, =0 -+Loop2: -+ sub r6, r6, r0 -+ cmp r6, r0 -+ blt Div_Found -+ add r4, r4, #1 -+ bgt Loop2 -+ -+ /* Shift divider into correct offset. */ -+ lsl r4, r4, #3 -+Div_Found: -+ /* Set the MMDC PODF. */ -+ ldr r6, [r2, #0x14] -+ bic r6, r6, #0x38 -+ orr r6, r6, r4 -+ str r6, [r2, #0x14] -+ -+mmdc_podf1: -+ ldr r6, [r2, #0x48] -+ cmp r6, #0 -+ bne mmdc_podf1 -+ -+ .endm -+ -+ .macro mmdc_clk_lower_100MHz -+ -+ /* -+ * Prior to reducing the DDR frequency (at 528/400 MHz), -+ * read the Measure unit count bits (MU_UNIT_DEL_NUM) -+ */ -+ ldr r5, =0x8B8 -+ ldr r6, [r8, r5] -+ /* Original MU unit count */ -+ mov r6, r6, LSR #16 -+ ldr r4, =0x3FF -+ and r6, r6, r4 -+ /* Original MU unit count * 2 */ -+ mov r7, r6, LSL #1 -+ /* -+ * Bypass the automatic measure unit when below 100 MHz -+ * by setting the Measure unit bypass enable bit (MU_BYP_EN) -+ */ -+ ldr r6, [r8, r5] -+ orr r6, r6, #0x400 -+ str r6, [r8, r5] -+ /* -+ * Double the measure count value read in step 1 and program it in the -+ * measurement bypass bits (MU_BYP_VAL) of the MMDC PHY Measure Unit -+ * Register for the reduced frequency operation below 100 MHz -+ */ -+ ldr r6, [r8, r5] -+ ldr r4, =0x3FF -+ bic r6, r6, r4 -+ orr r6, r6, r7 -+ str r6, [r8, r5] -+ /* Now perform a Force Measurement. */ -+ ldr r6, [r8, r5] -+ orr r6, r6, #0x800 -+ str r6, [r8, r5] -+ /* Wait for FRC_MSR to clear. */ -+force_measure: -+ ldr r6, [r8, r5] -+ and r6, r6, #0x800 -+ cmp r6, #0x0 -+ bne force_measure -+ -+ .endm -+ -+ .macro mmdc_clk_above_100MHz -+ -+ /* Make sure that the PHY measurement unit is NOT in bypass mode */ -+ ldr r5, =0x8B8 -+ ldr r6, [r8, r5] -+ bic r6, r6, #0x400 -+ str r6, [r8, r5] -+ /* Now perform a Force Measurement. */ -+ ldr r6, [r8, r5] -+ orr r6, r6, #0x800 -+ str r6, [r8, r5] -+ /* Wait for FRC_MSR to clear. */ -+force_measure1: -+ ldr r6, [r8, r5] -+ and r6, r6, #0x800 -+ cmp r6, #0x0 -+ bne force_measure1 -+ .endm -+ -+/* -+ * mx6_lpddr2_freq_change -+ * -+ * Make sure DDR is in self-refresh. -+ * IRQs are already disabled. -+ * r0 : DDR freq. -+ * r1: low_bus_freq_mode flag -+ * r2: Pointer to array containing addresses of registers. -+ */ -+ .align 3 -+ENTRY(mx6_lpddr2_freq_change) -+ -+ push {r4-r10} -+ -+ mov r4, r2 -+ ldr r3, [r4] @ANATOP_BASE_ADDR -+ ldr r2, [r4, #0x4] @CCM_BASE_ADDR -+ ldr r8, [r4, #0x8] @MMDC_P0_BASE_ADDR -+ ldr r7, [r4, #0xC] @L2_BASE_ADDR -+ -+lpddr2_freq_change: -+ adr r9, lpddr2_freq_change -+ -+ /* Prime all TLB entries. */ -+ ldr r6, [r9] -+ ldr r6, [r8] -+ ldr r6, [r3] -+ ldr r6, [r2] -+ -+ /* Drain all the L1 buffers. */ -+ dsb -+ -+#ifdef CONFIG_CACHE_L2X0 -+ /* -+ * Need to make sure the buffers in L2 are drained. -+ * Performing a sync operation does this. -+ */ -+ mov r6, #0x0 -+ str r6, [r7, #0x730] -+#endif -+ -+ /* -+ * The second dsb might be needed to keep cache sync (device write) -+ * ordering with the memory accesses before it. -+ */ -+ dsb -+ isb -+ -+ /* Disable Automatic power savings. */ -+ ldr r6, [r8, #0x404] -+ orr r6, r6, #0x01 -+ str r6, [r8, #0x404] -+ -+ /* MMDC0_MDPDC disable power down timer */ -+ ldr r6, [r8, #0x4] -+ bic r6, r6, #0xff00 -+ str r6, [r8, #0x4] -+ -+ /* Delay for a while */ -+ ldr r10, =10 -+delay1: -+ ldr r7, =0 -+cont1: -+ ldr r6, [r8, r7] -+ add r7, r7, #4 -+ cmp r7, #16 -+ bne cont1 -+ sub r10, r10, #1 -+ cmp r10, #0 -+ bgt delay1 -+ -+ /* Make the DDR explicitly enter self-refresh. */ -+ ldr r6, [r8, #0x404] -+ orr r6, r6, #0x200000 -+ str r6, [r8, #0x404] -+ -+poll_dvfs_set_1: -+ ldr r6, [r8, #0x404] -+ and r6, r6, #0x2000000 -+ cmp r6, #0x2000000 -+ bne poll_dvfs_set_1 -+ -+ /* set SBS step-by-step mode */ -+ ldr r6, [r8, #0x410] -+ orr r6, r6, #0x100 -+ str r6, [r8, #0x410] -+ -+ ldr r10, =100000000 -+ cmp r0, r10 -+ bgt set_ddr_mu_above_100 -+ mmdc_clk_lower_100MHz -+ -+set_ddr_mu_above_100: -+ ldr r10, =24000000 -+ cmp r0, r10 -+ beq set_to_24MHz -+ -+ ddr_switch_400MHz -+ -+ ldr r10,=100000000 -+ cmp r0, r10 -+ blt done -+ mmdc_clk_above_100MHz -+ -+ b done -+ -+set_to_24MHz: -+ mx6sl_switch_to_24MHz -+ -+done: -+ /* clear DVFS - exit from self refresh mode */ -+ ldr r6, [r8, #0x404] -+ bic r6, r6, #0x200000 -+ str r6, [r8, #0x404] -+ -+poll_dvfs_clear_1: -+ ldr r6, [r8, #0x404] -+ and r6, r6, #0x2000000 -+ cmp r6, #0x2000000 -+ beq poll_dvfs_clear_1 -+ -+ /* Enable Automatic power savings. */ -+ ldr r6, [r8, #0x404] -+ bic r6, r6, #0x01 -+ str r6, [r8, #0x404] -+ -+ ldr r10, =24000000 -+ cmp r0, r10 -+ beq skip_power_down -+ -+ /* Enable MMDC power down timer. */ -+ ldr r6, [r8, #0x4] -+ orr r6, r6, #0x5500 -+ str r6, [r8, #0x4] -+ -+skip_power_down: -+ /* clear SBS - unblock DDR accesses */ -+ ldr r6, [r8, #0x410] -+ bic r6, r6, #0x100 -+ str r6, [r8, #0x410] -+ -+ pop {r4-r10} -+ -+ /* Restore registers */ -+ mov pc, lr -+ -+ .type mx6_lpddr2_do_iram, #object -+ENTRY(mx6_lpddr2_do_iram) -+ .word mx6_lpddr2_freq_change -+ .size mx6_lpddr2_freq_change, . - mx6_lpddr2_freq_change -diff -Nur linux-4.1.13.orig/arch/arm/mach-imx/mach-imx6q.c linux-4.1.13/arch/arm/mach-imx/mach-imx6q.c ---- linux-4.1.13.orig/arch/arm/mach-imx/mach-imx6q.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/mach-imx/mach-imx6q.c 2015-11-30 17:56:13.532140921 +0100 -@@ -31,6 +31,9 @@ - #include - #include - #include -+#include -+#include -+#include - #include - #include - #include -@@ -39,6 +42,45 @@ - #include "cpuidle.h" - #include "hardware.h" - -+static struct fec_platform_data fec_pdata; -+ -+static int ar803x_smarteee = 0; -+ -+static int __init ar803x_smarteee_setup(char *__unused) -+{ -+ ar803x_smarteee = 1; -+ return 1; -+} -+ -+__setup("ar803x_smarteee", ar803x_smarteee_setup); -+ -+ -+static void imx6q_fec_sleep_enable(int enabled) -+{ -+ struct regmap *gpr; -+ -+ gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); -+ if (!IS_ERR(gpr)) { -+ if (enabled) -+ regmap_update_bits(gpr, IOMUXC_GPR13, -+ IMX6Q_GPR13_ENET_STOP_REQ, -+ IMX6Q_GPR13_ENET_STOP_REQ); -+ else -+ regmap_update_bits(gpr, IOMUXC_GPR13, -+ IMX6Q_GPR13_ENET_STOP_REQ, 0); -+ } else -+ pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n"); -+} -+ -+static void __init imx6q_enet_plt_init(void) -+{ -+ struct device_node *np; -+ -+ np = of_find_node_by_path("/soc/aips-bus@02100000/ethernet@02188000"); -+ if (np && of_get_property(np, "fsl,magic-packet", NULL)) -+ fec_pdata.sleep_mode_enable = imx6q_fec_sleep_enable; -+} -+ - /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */ - static int ksz9021rn_phy_fixup(struct phy_device *phydev) - { -@@ -112,6 +154,14 @@ - { - u16 val; - -+ /* disable phy AR8031 SmartEEE function. */ -+ phy_write(dev, 0xd, 0x3); -+ phy_write(dev, 0xe, 0x805d); -+ phy_write(dev, 0xd, 0x4003); -+ val = phy_read(dev, 0xe); -+ val &= ~(0x1 << 8); -+ phy_write(dev, 0xe, val); -+ - /* To enable AR8031 output a 125MHz clk from CLK_25M */ - phy_write(dev, 0xd, 0x7); - phy_write(dev, 0xe, 0x8016); -@@ -137,20 +187,11 @@ - { - u16 val; - -- /* Ar803x phy SmartEEE feature cause link status generates glitch, -- * which cause ethernet link down/up issue, so disable SmartEEE -- */ -- phy_write(dev, 0xd, 0x3); -- phy_write(dev, 0xe, 0x805d); -- phy_write(dev, 0xd, 0x4003); -- -- val = phy_read(dev, 0xe); -- phy_write(dev, 0xe, val & ~(1 << 8)); -- - /* -- * Enable 125MHz clock from CLK_25M on the AR8031. This -- * is fed in to the IMX6 on the ENET_REF_CLK (V22) pad. -- * Also, introduce a tx clock delay. -+ * Disable SmartEEE and Enable 125MHz clock from -+ * CLK_25M on the AR8031. This is fed in to the -+ * IMX6 on the ENET_REF_CLK (V22) pad. Also, -+ * introduce a tx clock delay. - * - * This is the same as is the AR8031 fixup. - */ -@@ -161,6 +202,31 @@ - if (val & BMCR_PDOWN) - phy_write(dev, 0x0, val & ~BMCR_PDOWN); - -+ if (!ar803x_smarteee) -+ return 0; -+ -+ /* Ar803x phy SmartEEE feature cause link status generates glitch, -+ * which cause ethernet link down/up issue, so disable SmartEEE -+ */ -+ phy_write(dev, 0xd, 0x3); -+ phy_write(dev, 0xe, 0x805d); -+ phy_write(dev, 0xd, 0x4003); -+ val = phy_read(dev, 0xe); -+ val |= (0x1 << 8); -+ phy_write(dev, 0xe, val); -+ -+ /* Increase 1000BT tw time for SmartEEE. It seems that we need -+ * a bit more time than standard to git up and running. Bumping -+ * up the Tw time allows us to enable SmartEEE without generating -+ * ethernet disconnects occasionally -+ */ -+ phy_write(dev, 0xd, 0x3); -+ phy_write(dev, 0xe, 0x805b); -+ phy_write(dev, 0xd, 0x4003); -+ val = phy_read(dev, 0xe); -+ val = 0x1517; -+ phy_write(dev, 0xe, val); -+ - return 0; - } - -@@ -262,9 +328,24 @@ - } - } - -+static inline void imx6q_enet_init(void) -+{ -+ imx6_enet_mac_init("fsl,imx6q-fec"); -+ imx6q_enet_phy_init(); -+ imx6q_1588_init(); -+ imx6q_enet_plt_init(); -+} -+ -+/* Add auxdata to pass platform data */ -+static const struct of_dev_auxdata imx6q_auxdata_lookup[] __initconst = { -+ OF_DEV_AUXDATA("fsl,imx6q-fec", 0x02188000, NULL, &fec_pdata), -+ { /* sentinel */ } -+}; -+ - static void __init imx6q_init_machine(void) - { - struct device *parent; -+ void __iomem *p; - - imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", - imx_get_soc_revision()); -@@ -273,14 +354,19 @@ - if (parent == NULL) - pr_warn("failed to initialize soc device\n"); - -- imx6q_enet_phy_init(); -- - of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); - -+ imx6q_enet_init(); - imx_anatop_init(); - cpu_is_imx6q() ? imx6q_pm_init() : imx6dl_pm_init(); - imx6q_1588_init(); - imx6q_axi_init(); -+ -+ p = ioremap(0x21b0000, SZ_4K); -+ if (p) { -+ writel(0x7f, p + 0x40); -+ iounmap(p); -+ } - } - - #define OCOTP_CFG3 0x440 -@@ -330,6 +416,12 @@ - if (dev_pm_opp_disable(cpu_dev, 852000000)) - pr_warn("failed to disable 852 MHz OPP\n"); - } -+ if (vpu352) { -+ if (dev_pm_opp_disable(cpu_dev, 396000000)) -+ pr_warn("VPU352: failed to disable 396MHz OPP\n"); -+ pr_info("VPU352: remove 396MHz OPP for VPU running at 352MHz!\n"); -+ } -+ - iounmap(base); - put_node: - of_node_put(np); -@@ -393,6 +485,7 @@ - imx_init_l2cache(); - imx_src_init(); - irqchip_init(); -+ imx6_pm_ccm_init("fsl,imx6q-ccm"); - } - - static const char * const imx6q_dt_compat[] __initconst = { -diff -Nur linux-4.1.13.orig/arch/arm/mach-imx/mach-imx6sl.c linux-4.1.13/arch/arm/mach-imx/mach-imx6sl.c ---- linux-4.1.13.orig/arch/arm/mach-imx/mach-imx6sl.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/mach-imx/mach-imx6sl.c 2015-11-30 17:56:13.532140921 +0100 -@@ -48,6 +48,8 @@ - { - struct device *parent; - -+ mxc_arch_reset_init_dt(); -+ - parent = imx_soc_device_init(); - if (parent == NULL) - pr_warn("failed to initialize soc device\n"); -@@ -66,6 +68,7 @@ - imx_init_l2cache(); - imx_src_init(); - irqchip_init(); -+ imx6_pm_ccm_init("fsl,imx6sl-ccm"); - } - - static const char * const imx6sl_dt_compat[] __initconst = { -@@ -78,4 +81,5 @@ - .init_machine = imx6sl_init_machine, - .init_late = imx6sl_init_late, - .dt_compat = imx6sl_dt_compat, -+ .restart = mxc_restart, - MACHINE_END -diff -Nur linux-4.1.13.orig/arch/arm/mach-imx/mach-imx6sx.c linux-4.1.13/arch/arm/mach-imx/mach-imx6sx.c ---- linux-4.1.13.orig/arch/arm/mach-imx/mach-imx6sx.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/mach-imx/mach-imx6sx.c 2015-11-30 17:56:13.532140921 +0100 -@@ -12,12 +12,135 @@ - #include - #include - #include -+#include -+#include -+#include - #include - #include - - #include "common.h" - #include "cpuidle.h" - -+static struct fec_platform_data fec_pdata[2]; -+static struct flexcan_platform_data flexcan_pdata[2]; -+static int flexcan_en_gpio; -+static int flexcan_stby_gpio; -+static int flexcan0_en; -+static int flexcan1_en; -+ -+static void imx6sx_fec1_sleep_enable(int enabled) -+{ -+ struct regmap *gpr; -+ -+ gpr = syscon_regmap_lookup_by_compatible("fsl,imx6sx-iomuxc-gpr"); -+ if (!IS_ERR(gpr)) { -+ if (enabled) -+ regmap_update_bits(gpr, IOMUXC_GPR4, -+ IMX6SX_GPR4_FEC_ENET1_STOP_REQ, -+ IMX6SX_GPR4_FEC_ENET1_STOP_REQ); -+ else -+ regmap_update_bits(gpr, IOMUXC_GPR4, -+ IMX6SX_GPR4_FEC_ENET1_STOP_REQ, 0); -+ } else -+ pr_err("failed to find fsl,imx6sx-iomux-gpr regmap\n"); -+} -+ -+static void imx6sx_fec2_sleep_enable(int enabled) -+{ -+ struct regmap *gpr; -+ -+ gpr = syscon_regmap_lookup_by_compatible("fsl,imx6sx-iomuxc-gpr"); -+ if (!IS_ERR(gpr)) { -+ if (enabled) -+ regmap_update_bits(gpr, IOMUXC_GPR4, -+ IMX6SX_GPR4_FEC_ENET2_STOP_REQ, -+ IMX6SX_GPR4_FEC_ENET2_STOP_REQ); -+ else -+ regmap_update_bits(gpr, IOMUXC_GPR4, -+ IMX6SX_GPR4_FEC_ENET2_STOP_REQ, 0); -+ } else -+ pr_err("failed to find fsl,imx6sx-iomux-gpr regmap\n"); -+} -+ -+static void __init imx6sx_enet_plt_init(void) -+{ -+ struct device_node *np; -+ -+ np = of_find_node_by_path("/soc/aips-bus@02100000/ethernet@02188000"); -+ if (np && of_get_property(np, "fsl,magic-packet", NULL)) -+ fec_pdata[0].sleep_mode_enable = imx6sx_fec1_sleep_enable; -+ np = of_find_node_by_path("/soc/aips-bus@02100000/ethernet@021b4000"); -+ if (np && of_get_property(np, "fsl,magic-packet", NULL)) -+ fec_pdata[1].sleep_mode_enable = imx6sx_fec2_sleep_enable; -+} -+ -+static void mx6sx_flexcan_switch(void) -+{ -+ if (flexcan0_en || flexcan1_en) { -+ gpio_set_value_cansleep(flexcan_en_gpio, 0); -+ gpio_set_value_cansleep(flexcan_stby_gpio, 0); -+ gpio_set_value_cansleep(flexcan_en_gpio, 1); -+ gpio_set_value_cansleep(flexcan_stby_gpio, 1); -+ } else { -+ /* -+ * avoid to disable CAN xcvr if any of the CAN interfaces -+ * are down. XCRV will be disabled only if both CAN2 -+ * interfaces are DOWN. -+ */ -+ gpio_set_value_cansleep(flexcan_en_gpio, 0); -+ gpio_set_value_cansleep(flexcan_stby_gpio, 0); -+ } -+} -+ -+static void imx6sx_arm2_flexcan0_switch(int enable) -+{ -+ flexcan0_en = enable; -+ mx6sx_flexcan_switch(); -+} -+ -+static void imx6sx_arm2_flexcan1_switch(int enable) -+{ -+ flexcan1_en = enable; -+ mx6sx_flexcan_switch(); -+} -+ -+static int __init imx6sx_arm2_flexcan_fixup(void) -+{ -+ struct device_node *np; -+ bool canfd_en = false; -+ -+ np = of_find_node_by_path("/soc/aips-bus@02000000/can@02090000"); -+ if (!np) -+ return -ENODEV; -+ -+ flexcan_en_gpio = of_get_named_gpio(np, "trx-en-gpio", 0); -+ flexcan_stby_gpio = of_get_named_gpio(np, "trx-stby-gpio", 0); -+ if (gpio_is_valid(flexcan_en_gpio) && gpio_is_valid(flexcan_stby_gpio) && -+ !gpio_request_one(flexcan_en_gpio, GPIOF_DIR_OUT, "flexcan-trx-en") && -+ !gpio_request_one(flexcan_stby_gpio, GPIOF_DIR_OUT, "flexcan-trx-stby")) { -+ /* flexcan 0 & 1 are using the same GPIOs for transceiver */ -+ flexcan_pdata[0].transceiver_switch = imx6sx_arm2_flexcan0_switch; -+ flexcan_pdata[1].transceiver_switch = imx6sx_arm2_flexcan1_switch; -+ } -+ -+ /* -+ * Switch on the transceiver by default for board with canfd enabled -+ * since canfd driver does not handle it. -+ * Two CAN instances share the same switch. -+ */ -+ for_each_node_by_name(np, "canfd") { -+ if (of_device_is_available(np)) { -+ canfd_en = true; -+ break; -+ } -+ } -+ -+ if (of_machine_is_compatible("fsl,imx6sx-sdb") && canfd_en) -+ imx6sx_arm2_flexcan0_switch(1); -+ -+ return 0; -+} -+ - static int ar8031_phy_fixup(struct phy_device *dev) - { - u16 val; -@@ -62,8 +185,18 @@ - { - imx6sx_enet_phy_init(); - imx6sx_enet_clk_sel(); -+ imx6sx_enet_plt_init(); - } - -+/* Add auxdata to pass platform data */ -+static const struct of_dev_auxdata imx6sx_auxdata_lookup[] __initconst = { -+ OF_DEV_AUXDATA("fsl,imx6q-flexcan", 0x02090000, NULL, &flexcan_pdata[0]), -+ OF_DEV_AUXDATA("fsl,imx6q-flexcan", 0x02094000, NULL, &flexcan_pdata[1]), -+ OF_DEV_AUXDATA("fsl,imx6sx-fec", 0x02188000, NULL, &fec_pdata[0]), -+ OF_DEV_AUXDATA("fsl,imx6sx-fec", 0x021b4000, NULL, &fec_pdata[1]), -+ { /* sentinel */ } -+}; -+ - static void __init imx6sx_init_machine(void) - { - struct device *parent; -@@ -86,6 +219,7 @@ - imx_init_l2cache(); - imx_src_init(); - irqchip_init(); -+ imx6_pm_ccm_init("fsl,imx6sx-ccm"); - } - - static void __init imx6sx_init_late(void) -diff -Nur linux-4.1.13.orig/arch/arm/mach-imx/Makefile linux-4.1.13/arch/arm/mach-imx/Makefile ---- linux-4.1.13.orig/arch/arm/mach-imx/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/mach-imx/Makefile 2015-11-30 17:56:13.532140921 +0100 -@@ -28,6 +28,14 @@ - obj-$(CONFIG_MXC_USE_EPIT) += epit.o - obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o - -+obj-y += busfreq-imx6.o -+ifdef CONFIG_ARM_IMX6Q_CPUFREQ -+obj-$(CONFIG_SOC_IMX6Q) += ddr3_freq_imx6.o busfreq_ddr3.o -+obj-$(CONFIG_SOC_IMX6SL) += lpddr2_freq_imx6.o busfreq_lpddr2.o -+AFLAGS_ddr3_freq_imx6.o :=-Wa,-march=armv7-a -+AFLAGS_lpddr2_freq_imx6.o :=-Wa,-march=armv7-a -+endif -+ - ifeq ($(CONFIG_CPU_IDLE),y) - obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o - obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o -@@ -87,9 +95,9 @@ - obj-$(CONFIG_SMP) += headsmp.o platsmp.o - obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o - endif --obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o --obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o --obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o mach-imx6sx.o -+obj-$(CONFIG_SOC_IMX6Q) += common-imx6.o clk-imx6q.o mach-imx6q.o -+obj-$(CONFIG_SOC_IMX6SL) += common-imx6.o clk-imx6sl.o mach-imx6sl.o -+obj-$(CONFIG_SOC_IMX6SX) += common-imx6.o clk-imx6sx.o mach-imx6sx.o - - ifeq ($(CONFIG_SUSPEND),y) - AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a -diff -Nur linux-4.1.13.orig/arch/arm/mach-imx/pm-imx6.c linux-4.1.13/arch/arm/mach-imx/pm-imx6.c ---- linux-4.1.13.orig/arch/arm/mach-imx/pm-imx6.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/mach-imx/pm-imx6.c 2015-11-30 17:56:13.532140921 +0100 -@@ -89,6 +89,7 @@ - - struct imx6_pm_socdata { - u32 ddr_type; -+ const char *ccm_compat; - const char *mmdc_compat; - const char *src_compat; - const char *iomuxc_compat; -@@ -138,6 +139,7 @@ - }; - - static const struct imx6_pm_socdata imx6q_pm_data __initconst = { -+ .ccm_compat = "fsl,imx6q-ccm", - .mmdc_compat = "fsl,imx6q-mmdc", - .src_compat = "fsl,imx6q-src", - .iomuxc_compat = "fsl,imx6q-iomuxc", -@@ -147,6 +149,7 @@ - }; - - static const struct imx6_pm_socdata imx6dl_pm_data __initconst = { -+ .ccm_compat = "fsl,imx6q-ccm", - .mmdc_compat = "fsl,imx6q-mmdc", - .src_compat = "fsl,imx6q-src", - .iomuxc_compat = "fsl,imx6dl-iomuxc", -@@ -156,6 +159,7 @@ - }; - - static const struct imx6_pm_socdata imx6sl_pm_data __initconst = { -+ .ccm_compat = "fsl,imx6sl-ccm", - .mmdc_compat = "fsl,imx6sl-mmdc", - .src_compat = "fsl,imx6sl-src", - .iomuxc_compat = "fsl,imx6sl-iomuxc", -@@ -165,6 +169,7 @@ - }; - - static const struct imx6_pm_socdata imx6sx_pm_data __initconst = { -+ .ccm_compat = "fsl,imx6sx-ccm", - .mmdc_compat = "fsl,imx6sx-mmdc", - .src_compat = "fsl,imx6sx-src", - .iomuxc_compat = "fsl,imx6sx-iomuxc", -@@ -255,7 +260,7 @@ - writel_relaxed(val, ccm_base + CCR); - } - --int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) -+int imx6_set_lpm(enum mxc_cpu_pwr_mode mode) - { - u32 val = readl_relaxed(ccm_base + CLPCR); - -@@ -340,7 +345,7 @@ - { - switch (state) { - case PM_SUSPEND_STANDBY: -- imx6q_set_lpm(STOP_POWER_ON); -+ imx6_set_lpm(STOP_POWER_ON); - imx6q_set_int_mem_clk_lpm(true); - imx_gpc_pre_suspend(false); - if (cpu_is_imx6sl()) -@@ -350,10 +355,10 @@ - if (cpu_is_imx6sl()) - imx6sl_set_wait_clk(false); - imx_gpc_post_resume(); -- imx6q_set_lpm(WAIT_CLOCKED); -+ imx6_set_lpm(WAIT_CLOCKED); - break; - case PM_SUSPEND_MEM: -- imx6q_set_lpm(STOP_POWER_OFF); -+ imx6_set_lpm(STOP_POWER_OFF); - imx6q_set_int_mem_clk_lpm(false); - imx6q_enable_wb(true); - /* -@@ -373,7 +378,7 @@ - imx6_enable_rbc(false); - imx6q_enable_wb(false); - imx6q_set_int_mem_clk_lpm(true); -- imx6q_set_lpm(WAIT_CLOCKED); -+ imx6_set_lpm(WAIT_CLOCKED); - break; - default: - return -EINVAL; -@@ -392,11 +397,6 @@ - .valid = imx6q_pm_valid, - }; - --void __init imx6q_pm_set_ccm_base(void __iomem *base) --{ -- ccm_base = base; --} -- - static int __init imx6_pm_get_base(struct imx6_pm_base *base, - const char *compat) - { -@@ -482,8 +482,7 @@ - - /* - * ccm physical address is not used by asm code currently, -- * so get ccm virtual address directly, as we already have -- * it from ccm driver. -+ * so get ccm virtual address directly. - */ - pm_info->ccm_base.vbase = ccm_base; - -@@ -554,11 +553,16 @@ - static void __init imx6_pm_common_init(const struct imx6_pm_socdata - *socdata) - { -+ struct device_node *np; - struct regmap *gpr; - int ret; - -+ np = of_find_compatible_node(NULL, NULL, socdata->ccm_compat); -+ ccm_base = of_iomap(np, 0); - WARN_ON(!ccm_base); - -+ imx6_set_lpm(WAIT_CLOCKED); -+ - if (IS_ENABLED(CONFIG_SUSPEND)) { - ret = imx6q_suspend_init(socdata); - if (ret) -@@ -568,7 +572,7 @@ - - /* - * This is for SW workaround step #1 of ERR007265, see comments -- * in imx6q_set_lpm for details of this errata. -+ * in imx6_set_lpm for details of this errata. - * Force IOMUXC irq pending, so that the interrupt to GPC can be - * used to deassert dsm_request signal when the signal gets - * asserted unexpectedly. -@@ -579,6 +583,24 @@ - IMX6Q_GPR1_GINT); - } - -+void __init imx6_pm_ccm_init(const char *ccm_compat) -+{ -+ struct device_node *np; -+ u32 val; -+ -+ np = of_find_compatible_node(NULL, NULL, ccm_compat); -+ ccm_base = of_iomap(np, 0); -+ BUG_ON(!ccm_base); -+ -+ /* -+ * Initialize CCM_CLPCR_LPM into RUN mode to avoid ARM core -+ * clock being shut down unexpectedly by WAIT mode. -+ */ -+ val = readl_relaxed(ccm_base + CLPCR); -+ val &= ~BM_CLPCR_LPM; -+ writel_relaxed(val, ccm_base + CLPCR); -+} -+ - void __init imx6q_pm_init(void) - { - imx6_pm_common_init(&imx6q_pm_data); -diff -Nur linux-4.1.13.orig/arch/arm/mach-imx/src.c linux-4.1.13/arch/arm/mach-imx/src.c ---- linux-4.1.13.orig/arch/arm/mach-imx/src.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/mach-imx/src.c 2015-11-30 17:56:13.532140921 +0100 -@@ -1,5 +1,5 @@ - /* -- * Copyright 2011 Freescale Semiconductor, Inc. -+ * Copyright 2011-2014 Freescale Semiconductor, Inc. - * Copyright 2011 Linaro Ltd. - * - * The code contained herein is licensed under the GNU General Public -@@ -18,6 +18,7 @@ - #include - #include - #include "common.h" -+#include "hardware.h" - - #define SRC_SCR 0x000 - #define SRC_GPR1 0x020 -@@ -32,6 +33,7 @@ - - static void __iomem *src_base; - static DEFINE_SPINLOCK(scr_lock); -+static bool m4_is_enabled; - - static const int sw_reset_bits[5] = { - BP_SRC_SCR_SW_GPU_RST, -@@ -41,6 +43,11 @@ - BP_SRC_SCR_SW_IPU2_RST - }; - -+bool imx_src_is_m4_enabled(void) -+{ -+ return m4_is_enabled; -+} -+ - static int imx_src_reset_module(struct reset_controller_dev *rcdev, - unsigned long sw_reset_idx) - { -@@ -136,6 +143,14 @@ - */ - spin_lock(&scr_lock); - val = readl_relaxed(src_base + SRC_SCR); -+ -+ /* bit 4 is m4c_non_sclr_rst on i.MX6SX */ -+ if (cpu_is_imx6sx() && ((val & -+ (1 << BP_SRC_SCR_SW_OPEN_VG_RST)) == 0)) -+ m4_is_enabled = true; -+ else -+ m4_is_enabled = false; -+ - val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE); - writel_relaxed(val, src_base + SRC_SCR); - spin_unlock(&scr_lock); -diff -Nur linux-4.1.13.orig/arch/arm/mach-imx/system.c linux-4.1.13/arch/arm/mach-imx/system.c ---- linux-4.1.13.orig/arch/arm/mach-imx/system.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/mach-imx/system.c 2015-11-30 17:56:13.532140921 +0100 -@@ -34,6 +34,7 @@ - - static void __iomem *wdog_base; - static struct clk *wdog_clk; -+static u32 wdog_source = 1; /* use WDOG1 default */ - - /* - * Reset the system. It is called by machine_restart(). -@@ -50,6 +51,17 @@ - - if (cpu_is_mx1()) - wcr_enable = (1 << 0); -+ /* -+ * Some i.MX6 boards use WDOG2 to reset external pmic in bypass mode, -+ * so do WDOG2 reset here. Do not set SRS, since we will -+ * trigger external POR later. Use WDOG1 to reset in ldo-enable -+ * mode. You can set it by "fsl,wdog-reset" in dts. -+ * For i.MX6SX we have to trigger wdog-reset to reset QSPI-NOR flash to -+ * workaround qspi-nor reboot issue whatever ldo-bypass or not. -+ */ -+ else if ((wdog_source == 2 && (cpu_is_imx6q() || cpu_is_imx6dl() || -+ cpu_is_imx6sl())) || cpu_is_imx6sx()) -+ wcr_enable = 0x14; - else - wcr_enable = (1 << 2); - -@@ -89,6 +101,41 @@ - clk_prepare(wdog_clk); - } - -+void __init mxc_arch_reset_init_dt(void) -+{ -+ struct device_node *np = NULL; -+ -+ if (cpu_is_imx6q() || cpu_is_imx6dl()) -+ np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpc"); -+ else if (cpu_is_imx6sl()) -+ np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpc"); -+ -+ if (np) -+ of_property_read_u32(np, "fsl,wdog-reset", &wdog_source); -+ pr_info("Use WDOG%d as reset source\n", wdog_source); -+ -+ np = of_find_compatible_node(NULL, NULL, "fsl,imx21-wdt"); -+ wdog_base = of_iomap(np, 0); -+ WARN_ON(!wdog_base); -+ -+ /* Some i.MX6 boards use WDOG2 to reset board in ldo-bypass mode */ -+ if (wdog_source == 2 && (cpu_is_imx6q() || cpu_is_imx6dl() || -+ cpu_is_imx6sl())) { -+ np = of_find_compatible_node(np, NULL, "fsl,imx21-wdt"); -+ wdog_base = of_iomap(np, 0); -+ WARN_ON(!wdog_base); -+ } -+ -+ wdog_clk = of_clk_get(np, 0); -+ if (IS_ERR(wdog_clk)) { -+ pr_warn("%s: failed to get wdog clock\n", __func__); -+ wdog_clk = NULL; -+ return; -+ } -+ -+ clk_prepare(wdog_clk); -+} -+ - #ifdef CONFIG_CACHE_L2X0 - void __init imx_init_l2cache(void) - { -diff -Nur linux-4.1.13.orig/arch/arm/mach-imx/time.c linux-4.1.13/arch/arm/mach-imx/time.c ---- linux-4.1.13.orig/arch/arm/mach-imx/time.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/mach-imx/time.c 2015-11-30 17:56:13.532140921 +0100 -@@ -28,6 +28,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -38,9 +39,11 @@ - #include "hardware.h" - - /* -- * There are 2 versions of the timer hardware on Freescale MXC hardware. -- * Version 1: MX1/MXL, MX21, MX27. -- * Version 2: MX25, MX31, MX35, MX37, MX51 -+ * There are 4 versions of the timer hardware on Freescale MXC hardware. -+ * - MX1/MXL -+ * - MX21, MX27. -+ * - MX25, MX31, MX35, MX37, MX51, MX6Q(rev1.0) -+ * - MX6DL, MX6SX, MX6Q(rev1.1+) - */ - - /* defines common for all i.MX */ -@@ -82,6 +85,13 @@ - static struct clock_event_device clockevent_mxc; - static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; - -+struct imx_timer { -+ void __iomem *base; -+ int irq; -+ struct clk *clk_per; -+ struct clk *clk_ipg; -+}; -+ - static void __iomem *timer_base; - - static inline void gpt_irq_disable(void) -@@ -89,19 +99,19 @@ - unsigned int tmp; - - if (timer_is_v2()) -- __raw_writel(0, timer_base + V2_IR); -+ writel_relaxed(0, timer_base + V2_IR); - else { -- tmp = __raw_readl(timer_base + MXC_TCTL); -- __raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL); -+ tmp = readl_relaxed(timer_base + MXC_TCTL); -+ writel_relaxed(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL); - } - } - - static inline void gpt_irq_enable(void) - { - if (timer_is_v2()) -- __raw_writel(1<<0, timer_base + V2_IR); -+ writel_relaxed(1<<0, timer_base + V2_IR); - else { -- __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN, -+ writel_relaxed(readl_relaxed(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN, - timer_base + MXC_TCTL); - } - } -@@ -110,32 +120,32 @@ - { - if (timer_is_v1()) { - if (cpu_is_mx1()) -- __raw_writel(0, timer_base + MX1_2_TSTAT); -+ writel_relaxed(0, timer_base + MX1_2_TSTAT); - else -- __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, -+ writel_relaxed(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, - timer_base + MX1_2_TSTAT); - } else if (timer_is_v2()) -- __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT); -+ writel_relaxed(V2_TSTAT_OF1, timer_base + V2_TSTAT); - } - - static void __iomem *sched_clock_reg; - - static u64 notrace mxc_read_sched_clock(void) - { -- return sched_clock_reg ? __raw_readl(sched_clock_reg) : 0; -+ return sched_clock_reg ? readl_relaxed(sched_clock_reg) : 0; - } - - static struct delay_timer imx_delay_timer; - - static unsigned long imx_read_current_timer(void) - { -- return __raw_readl(sched_clock_reg); -+ return readl_relaxed(sched_clock_reg); - } - --static int __init mxc_clocksource_init(struct clk *timer_clk) -+static int __init mxc_clocksource_init(struct imx_timer *imxtm) - { -- unsigned int c = clk_get_rate(timer_clk); -- void __iomem *reg = timer_base + (timer_is_v2() ? V2_TCN : MX1_2_TCN); -+ unsigned int c = clk_get_rate(imxtm->clk_per); -+ void __iomem *reg = imxtm->base + (timer_is_v2() ? V2_TCN : MX1_2_TCN); - - imx_delay_timer.read_current_timer = &imx_read_current_timer; - imx_delay_timer.freq = c; -@@ -155,11 +165,11 @@ - { - unsigned long tcmp; - -- tcmp = __raw_readl(timer_base + MX1_2_TCN) + evt; -+ tcmp = readl_relaxed(timer_base + MX1_2_TCN) + evt; - -- __raw_writel(tcmp, timer_base + MX1_2_TCMP); -+ writel_relaxed(tcmp, timer_base + MX1_2_TCMP); - -- return (int)(tcmp - __raw_readl(timer_base + MX1_2_TCN)) < 0 ? -+ return (int)(tcmp - readl_relaxed(timer_base + MX1_2_TCN)) < 0 ? - -ETIME : 0; - } - -@@ -168,12 +178,12 @@ - { - unsigned long tcmp; - -- tcmp = __raw_readl(timer_base + V2_TCN) + evt; -+ tcmp = readl_relaxed(timer_base + V2_TCN) + evt; - -- __raw_writel(tcmp, timer_base + V2_TCMP); -+ writel_relaxed(tcmp, timer_base + V2_TCMP); - - return evt < 0x7fffffff && -- (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ? -+ (int)(tcmp - readl_relaxed(timer_base + V2_TCN)) < 0 ? - -ETIME : 0; - } - -@@ -204,10 +214,10 @@ - if (mode != clockevent_mode) { - /* Set event time into far-far future */ - if (timer_is_v2()) -- __raw_writel(__raw_readl(timer_base + V2_TCN) - 3, -+ writel_relaxed(readl_relaxed(timer_base + V2_TCN) - 3, - timer_base + V2_TCMP); - else -- __raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3, -+ writel_relaxed(readl_relaxed(timer_base + MX1_2_TCN) - 3, - timer_base + MX1_2_TCMP); - - /* Clear pending interrupt */ -@@ -257,9 +267,9 @@ - uint32_t tstat; - - if (timer_is_v2()) -- tstat = __raw_readl(timer_base + V2_TSTAT); -+ tstat = readl_relaxed(timer_base + V2_TSTAT); - else -- tstat = __raw_readl(timer_base + MX1_2_TSTAT); -+ tstat = readl_relaxed(timer_base + MX1_2_TSTAT); - - gpt_irq_acknowledge(); - -@@ -282,49 +292,51 @@ - .rating = 200, - }; - --static int __init mxc_clockevent_init(struct clk *timer_clk) -+static int __init mxc_clockevent_init(struct imx_timer *imxtm) - { - if (timer_is_v2()) - clockevent_mxc.set_next_event = v2_set_next_event; - - clockevent_mxc.cpumask = cpumask_of(0); - clockevents_config_and_register(&clockevent_mxc, -- clk_get_rate(timer_clk), -+ clk_get_rate(imxtm->clk_per), - 0xff, 0xfffffffe); - - return 0; - } - --static void __init _mxc_timer_init(int irq, -- struct clk *clk_per, struct clk *clk_ipg) -+static void __init _mxc_timer_init(struct imx_timer *imxtm) - { - uint32_t tctl_val; - -- if (IS_ERR(clk_per)) { -+ /* Temporary */ -+ timer_base = imxtm->base; -+ -+ if (IS_ERR(imxtm->clk_per)) { - pr_err("i.MX timer: unable to get clk\n"); - return; - } - -- if (!IS_ERR(clk_ipg)) -- clk_prepare_enable(clk_ipg); -+ if (!IS_ERR(imxtm->clk_ipg)) -+ clk_prepare_enable(imxtm->clk_ipg); - -- clk_prepare_enable(clk_per); -+ clk_prepare_enable(imxtm->clk_per); - - /* - * Initialise to a known state (all timers off, and timing reset) - */ - -- __raw_writel(0, timer_base + MXC_TCTL); -- __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ -+ writel_relaxed(0, imxtm->base + MXC_TCTL); -+ writel_relaxed(0, imxtm->base + MXC_TPRER); /* see datasheet note */ - - if (timer_is_v2()) { - tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; -- if (clk_get_rate(clk_per) == V2_TIMER_RATE_OSC_DIV8) { -+ if (clk_get_rate(imxtm->clk_per) == V2_TIMER_RATE_OSC_DIV8) { - tctl_val |= V2_TCTL_CLK_OSC_DIV8; - if (cpu_is_imx6dl() || cpu_is_imx6sx()) { - /* 24 / 8 = 3 MHz */ -- __raw_writel(7 << V2_TPRER_PRE24M, -- timer_base + MXC_TPRER); -+ writel_relaxed(7 << V2_TPRER_PRE24M, -+ imxtm->base + MXC_TPRER); - tctl_val |= V2_TCTL_24MEN; - } - } else { -@@ -334,46 +346,58 @@ - tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; - } - -- __raw_writel(tctl_val, timer_base + MXC_TCTL); -+ writel_relaxed(tctl_val, imxtm->base + MXC_TCTL); - - /* init and register the timer to the framework */ -- mxc_clocksource_init(clk_per); -- mxc_clockevent_init(clk_per); -+ mxc_clocksource_init(imxtm); -+ mxc_clockevent_init(imxtm); - - /* Make irqs happen */ -- setup_irq(irq, &mxc_timer_irq); -+ setup_irq(imxtm->irq, &mxc_timer_irq); - } - --void __init mxc_timer_init(void __iomem *base, int irq) -+void __init mxc_timer_init(unsigned long pbase, int irq) - { -- struct clk *clk_per = clk_get_sys("imx-gpt.0", "per"); -- struct clk *clk_ipg = clk_get_sys("imx-gpt.0", "ipg"); -+ struct imx_timer *imxtm; -+ -+ imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL); -+ BUG_ON(!imxtm); - -- timer_base = base; -+ imxtm->clk_per = clk_get_sys("imx-gpt.0", "per"); -+ imxtm->clk_ipg = clk_get_sys("imx-gpt.0", "ipg"); - -- _mxc_timer_init(irq, clk_per, clk_ipg); -+ imxtm->base = ioremap(pbase, SZ_4K); -+ BUG_ON(!imxtm->base); -+ -+ _mxc_timer_init(imxtm); - } - - static void __init mxc_timer_init_dt(struct device_node *np) - { -- struct clk *clk_per, *clk_ipg; -- int irq; -+ struct imx_timer *imxtm; -+ static int initialized; - -- if (timer_base) -+ /* Support one instance only */ -+ if (initialized) - return; - -- timer_base = of_iomap(np, 0); -- WARN_ON(!timer_base); -- irq = irq_of_parse_and_map(np, 0); -+ imxtm = kzalloc(sizeof(*imxtm), GFP_KERNEL); -+ BUG_ON(!imxtm); - -- clk_ipg = of_clk_get_by_name(np, "ipg"); -+ imxtm->base = of_iomap(np, 0); -+ WARN_ON(!imxtm->base); -+ imxtm->irq = irq_of_parse_and_map(np, 0); -+ -+ imxtm->clk_ipg = of_clk_get_by_name(np, "ipg"); - - /* Try osc_per first, and fall back to per otherwise */ -- clk_per = of_clk_get_by_name(np, "osc_per"); -- if (IS_ERR(clk_per)) -- clk_per = of_clk_get_by_name(np, "per"); -+ imxtm->clk_per = of_clk_get_by_name(np, "osc_per"); -+ if (IS_ERR(imxtm->clk_per)) -+ imxtm->clk_per = of_clk_get_by_name(np, "per"); -+ -+ _mxc_timer_init(imxtm); - -- _mxc_timer_init(irq, clk_per, clk_ipg); -+ initialized = 1; - } - CLOCKSOURCE_OF_DECLARE(mx1_timer, "fsl,imx1-gpt", mxc_timer_init_dt); - CLOCKSOURCE_OF_DECLARE(mx25_timer, "fsl,imx25-gpt", mxc_timer_init_dt); -diff -Nur linux-4.1.13.orig/arch/arm/mm/cache-v7.S linux-4.1.13/arch/arm/mm/cache-v7.S ---- linux-4.1.13.orig/arch/arm/mm/cache-v7.S 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/arch/arm/mm/cache-v7.S 2015-11-30 17:56:13.532140921 +0100 -@@ -446,3 +446,5 @@ - - @ define struct cpu_cache_fns (see and proc-macros.S) - define_cache_functions v7 -+ -+ .long v7_dma_flush_range -diff -Nur linux-4.1.13.orig/block/bfq-cgroup.c linux-4.1.13/block/bfq-cgroup.c ---- linux-4.1.13.orig/block/bfq-cgroup.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/block/bfq-cgroup.c 2015-11-30 17:56:13.536140654 +0100 -@@ -0,0 +1,936 @@ -+/* -+ * BFQ: CGROUPS support. -+ * -+ * Based on ideas and code from CFQ: -+ * Copyright (C) 2003 Jens Axboe -+ * -+ * Copyright (C) 2008 Fabio Checconi -+ * Paolo Valente -+ * -+ * Copyright (C) 2010 Paolo Valente -+ * -+ * Licensed under the GPL-2 as detailed in the accompanying COPYING.BFQ -+ * file. -+ */ -+ -+#ifdef CONFIG_CGROUP_BFQIO -+ -+static DEFINE_MUTEX(bfqio_mutex); -+ -+static bool bfqio_is_removed(struct bfqio_cgroup *bgrp) -+{ -+ return bgrp ? !bgrp->online : false; -+} -+ -+static struct bfqio_cgroup bfqio_root_cgroup = { -+ .weight = BFQ_DEFAULT_GRP_WEIGHT, -+ .ioprio = BFQ_DEFAULT_GRP_IOPRIO, -+ .ioprio_class = BFQ_DEFAULT_GRP_CLASS, -+}; -+ -+static inline void bfq_init_entity(struct bfq_entity *entity, -+ struct bfq_group *bfqg) -+{ -+ entity->weight = entity->new_weight; -+ entity->orig_weight = entity->new_weight; -+ entity->ioprio = entity->new_ioprio; -+ entity->ioprio_class = entity->new_ioprio_class; -+ entity->parent = bfqg->my_entity; -+ entity->sched_data = &bfqg->sched_data; -+} -+ -+static struct bfqio_cgroup *css_to_bfqio(struct cgroup_subsys_state *css) -+{ -+ return css ? container_of(css, struct bfqio_cgroup, css) : NULL; -+} -+ -+/* -+ * Search the bfq_group for bfqd into the hash table (by now only a list) -+ * of bgrp. Must be called under rcu_read_lock(). -+ */ -+static struct bfq_group *bfqio_lookup_group(struct bfqio_cgroup *bgrp, -+ struct bfq_data *bfqd) -+{ -+ struct bfq_group *bfqg; -+ void *key; -+ -+ hlist_for_each_entry_rcu(bfqg, &bgrp->group_data, group_node) { -+ key = rcu_dereference(bfqg->bfqd); -+ if (key == bfqd) -+ return bfqg; -+ } -+ -+ return NULL; -+} -+ -+static inline void bfq_group_init_entity(struct bfqio_cgroup *bgrp, -+ struct bfq_group *bfqg) -+{ -+ struct bfq_entity *entity = &bfqg->entity; -+ -+ /* -+ * If the weight of the entity has never been set via the sysfs -+ * interface, then bgrp->weight == 0. In this case we initialize -+ * the weight from the current ioprio value. Otherwise, the group -+ * weight, if set, has priority over the ioprio value. -+ */ -+ if (bgrp->weight == 0) { -+ entity->new_weight = bfq_ioprio_to_weight(bgrp->ioprio); -+ entity->new_ioprio = bgrp->ioprio; -+ } else { -+ if (bgrp->weight < BFQ_MIN_WEIGHT || -+ bgrp->weight > BFQ_MAX_WEIGHT) { -+ printk(KERN_CRIT "bfq_group_init_entity: " -+ "bgrp->weight %d\n", bgrp->weight); -+ BUG(); -+ } -+ entity->new_weight = bgrp->weight; -+ entity->new_ioprio = bfq_weight_to_ioprio(bgrp->weight); -+ } -+ entity->orig_weight = entity->weight = entity->new_weight; -+ entity->ioprio = entity->new_ioprio; -+ entity->ioprio_class = entity->new_ioprio_class = bgrp->ioprio_class; -+ entity->my_sched_data = &bfqg->sched_data; -+ bfqg->active_entities = 0; -+} -+ -+static inline void bfq_group_set_parent(struct bfq_group *bfqg, -+ struct bfq_group *parent) -+{ -+ struct bfq_entity *entity; -+ -+ BUG_ON(parent == NULL); -+ BUG_ON(bfqg == NULL); -+ -+ entity = &bfqg->entity; -+ entity->parent = parent->my_entity; -+ entity->sched_data = &parent->sched_data; -+} -+ -+/** -+ * bfq_group_chain_alloc - allocate a chain of groups. -+ * @bfqd: queue descriptor. -+ * @css: the leaf cgroup_subsys_state this chain starts from. -+ * -+ * Allocate a chain of groups starting from the one belonging to -+ * @cgroup up to the root cgroup. Stop if a cgroup on the chain -+ * to the root has already an allocated group on @bfqd. -+ */ -+static struct bfq_group *bfq_group_chain_alloc(struct bfq_data *bfqd, -+ struct cgroup_subsys_state *css) -+{ -+ struct bfqio_cgroup *bgrp; -+ struct bfq_group *bfqg, *prev = NULL, *leaf = NULL; -+ -+ for (; css != NULL; css = css->parent) { -+ bgrp = css_to_bfqio(css); -+ -+ bfqg = bfqio_lookup_group(bgrp, bfqd); -+ if (bfqg != NULL) { -+ /* -+ * All the cgroups in the path from there to the -+ * root must have a bfq_group for bfqd, so we don't -+ * need any more allocations. -+ */ -+ break; -+ } -+ -+ bfqg = kzalloc(sizeof(*bfqg), GFP_ATOMIC); -+ if (bfqg == NULL) -+ goto cleanup; -+ -+ bfq_group_init_entity(bgrp, bfqg); -+ bfqg->my_entity = &bfqg->entity; -+ -+ if (leaf == NULL) { -+ leaf = bfqg; -+ prev = leaf; -+ } else { -+ bfq_group_set_parent(prev, bfqg); -+ /* -+ * Build a list of allocated nodes using the bfqd -+ * filed, that is still unused and will be -+ * initialized only after the node will be -+ * connected. -+ */ -+ prev->bfqd = bfqg; -+ prev = bfqg; -+ } -+ } -+ -+ return leaf; -+ -+cleanup: -+ while (leaf != NULL) { -+ prev = leaf; -+ leaf = leaf->bfqd; -+ kfree(prev); -+ } -+ -+ return NULL; -+} -+ -+/** -+ * bfq_group_chain_link - link an allocated group chain to a cgroup -+ * hierarchy. -+ * @bfqd: the queue descriptor. -+ * @css: the leaf cgroup_subsys_state to start from. -+ * @leaf: the leaf group (to be associated to @cgroup). -+ * -+ * Try to link a chain of groups to a cgroup hierarchy, connecting the -+ * nodes bottom-up, so we can be sure that when we find a cgroup in the -+ * hierarchy that already as a group associated to @bfqd all the nodes -+ * in the path to the root cgroup have one too. -+ * -+ * On locking: the queue lock protects the hierarchy (there is a hierarchy -+ * per device) while the bfqio_cgroup lock protects the list of groups -+ * belonging to the same cgroup. -+ */ -+static void bfq_group_chain_link(struct bfq_data *bfqd, -+ struct cgroup_subsys_state *css, -+ struct bfq_group *leaf) -+{ -+ struct bfqio_cgroup *bgrp; -+ struct bfq_group *bfqg, *next, *prev = NULL; -+ unsigned long flags; -+ -+ assert_spin_locked(bfqd->queue->queue_lock); -+ -+ for (; css != NULL && leaf != NULL; css = css->parent) { -+ bgrp = css_to_bfqio(css); -+ next = leaf->bfqd; -+ -+ bfqg = bfqio_lookup_group(bgrp, bfqd); -+ BUG_ON(bfqg != NULL); -+ -+ spin_lock_irqsave(&bgrp->lock, flags); -+ -+ rcu_assign_pointer(leaf->bfqd, bfqd); -+ hlist_add_head_rcu(&leaf->group_node, &bgrp->group_data); -+ hlist_add_head(&leaf->bfqd_node, &bfqd->group_list); -+ -+ spin_unlock_irqrestore(&bgrp->lock, flags); -+ -+ prev = leaf; -+ leaf = next; -+ } -+ -+ BUG_ON(css == NULL && leaf != NULL); -+ if (css != NULL && prev != NULL) { -+ bgrp = css_to_bfqio(css); -+ bfqg = bfqio_lookup_group(bgrp, bfqd); -+ bfq_group_set_parent(prev, bfqg); -+ } -+} -+ -+/** -+ * bfq_find_alloc_group - return the group associated to @bfqd in @cgroup. -+ * @bfqd: queue descriptor. -+ * @cgroup: cgroup being searched for. -+ * -+ * Return a group associated to @bfqd in @cgroup, allocating one if -+ * necessary. When a group is returned all the cgroups in the path -+ * to the root have a group associated to @bfqd. -+ * -+ * If the allocation fails, return the root group: this breaks guarantees -+ * but is a safe fallback. If this loss becomes a problem it can be -+ * mitigated using the equivalent weight (given by the product of the -+ * weights of the groups in the path from @group to the root) in the -+ * root scheduler. -+ * -+ * We allocate all the missing nodes in the path from the leaf cgroup -+ * to the root and we connect the nodes only after all the allocations -+ * have been successful. -+ */ -+static struct bfq_group *bfq_find_alloc_group(struct bfq_data *bfqd, -+ struct cgroup_subsys_state *css) -+{ -+ struct bfqio_cgroup *bgrp = css_to_bfqio(css); -+ struct bfq_group *bfqg; -+ -+ bfqg = bfqio_lookup_group(bgrp, bfqd); -+ if (bfqg != NULL) -+ return bfqg; -+ -+ bfqg = bfq_group_chain_alloc(bfqd, css); -+ if (bfqg != NULL) -+ bfq_group_chain_link(bfqd, css, bfqg); -+ else -+ bfqg = bfqd->root_group; -+ -+ return bfqg; -+} -+ -+/** -+ * bfq_bfqq_move - migrate @bfqq to @bfqg. -+ * @bfqd: queue descriptor. -+ * @bfqq: the queue to move. -+ * @entity: @bfqq's entity. -+ * @bfqg: the group to move to. -+ * -+ * Move @bfqq to @bfqg, deactivating it from its old group and reactivating -+ * it on the new one. Avoid putting the entity on the old group idle tree. -+ * -+ * Must be called under the queue lock; the cgroup owning @bfqg must -+ * not disappear (by now this just means that we are called under -+ * rcu_read_lock()). -+ */ -+static void bfq_bfqq_move(struct bfq_data *bfqd, struct bfq_queue *bfqq, -+ struct bfq_entity *entity, struct bfq_group *bfqg) -+{ -+ int busy, resume; -+ -+ busy = bfq_bfqq_busy(bfqq); -+ resume = !RB_EMPTY_ROOT(&bfqq->sort_list); -+ -+ BUG_ON(resume && !entity->on_st); -+ BUG_ON(busy && !resume && entity->on_st && -+ bfqq != bfqd->in_service_queue); -+ -+ if (busy) { -+ BUG_ON(atomic_read(&bfqq->ref) < 2); -+ -+ if (!resume) -+ bfq_del_bfqq_busy(bfqd, bfqq, 0); -+ else -+ bfq_deactivate_bfqq(bfqd, bfqq, 0); -+ } else if (entity->on_st) -+ bfq_put_idle_entity(bfq_entity_service_tree(entity), entity); -+ -+ /* -+ * Here we use a reference to bfqg. We don't need a refcounter -+ * as the cgroup reference will not be dropped, so that its -+ * destroy() callback will not be invoked. -+ */ -+ entity->parent = bfqg->my_entity; -+ entity->sched_data = &bfqg->sched_data; -+ -+ if (busy && resume) -+ bfq_activate_bfqq(bfqd, bfqq); -+ -+ if (bfqd->in_service_queue == NULL && !bfqd->rq_in_driver) -+ bfq_schedule_dispatch(bfqd); -+} -+ -+/** -+ * __bfq_bic_change_cgroup - move @bic to @cgroup. -+ * @bfqd: the queue descriptor. -+ * @bic: the bic to move. -+ * @cgroup: the cgroup to move to. -+ * -+ * Move bic to cgroup, assuming that bfqd->queue is locked; the caller -+ * has to make sure that the reference to cgroup is valid across the call. -+ * -+ * NOTE: an alternative approach might have been to store the current -+ * cgroup in bfqq and getting a reference to it, reducing the lookup -+ * time here, at the price of slightly more complex code. -+ */ -+static struct bfq_group *__bfq_bic_change_cgroup(struct bfq_data *bfqd, -+ struct bfq_io_cq *bic, -+ struct cgroup_subsys_state *css) -+{ -+ struct bfq_queue *async_bfqq = bic_to_bfqq(bic, 0); -+ struct bfq_queue *sync_bfqq = bic_to_bfqq(bic, 1); -+ struct bfq_entity *entity; -+ struct bfq_group *bfqg; -+ struct bfqio_cgroup *bgrp; -+ -+ bgrp = css_to_bfqio(css); -+ -+ bfqg = bfq_find_alloc_group(bfqd, css); -+ if (async_bfqq != NULL) { -+ entity = &async_bfqq->entity; -+ -+ if (entity->sched_data != &bfqg->sched_data) { -+ bic_set_bfqq(bic, NULL, 0); -+ bfq_log_bfqq(bfqd, async_bfqq, -+ "bic_change_group: %p %d", -+ async_bfqq, atomic_read(&async_bfqq->ref)); -+ bfq_put_queue(async_bfqq); -+ } -+ } -+ -+ if (sync_bfqq != NULL) { -+ entity = &sync_bfqq->entity; -+ if (entity->sched_data != &bfqg->sched_data) -+ bfq_bfqq_move(bfqd, sync_bfqq, entity, bfqg); -+ } -+ -+ return bfqg; -+} -+ -+/** -+ * bfq_bic_change_cgroup - move @bic to @cgroup. -+ * @bic: the bic being migrated. -+ * @cgroup: the destination cgroup. -+ * -+ * When the task owning @bic is moved to @cgroup, @bic is immediately -+ * moved into its new parent group. -+ */ -+static void bfq_bic_change_cgroup(struct bfq_io_cq *bic, -+ struct cgroup_subsys_state *css) -+{ -+ struct bfq_data *bfqd; -+ unsigned long uninitialized_var(flags); -+ -+ bfqd = bfq_get_bfqd_locked(&(bic->icq.q->elevator->elevator_data), -+ &flags); -+ if (bfqd != NULL) { -+ __bfq_bic_change_cgroup(bfqd, bic, css); -+ bfq_put_bfqd_unlock(bfqd, &flags); -+ } -+} -+ -+/** -+ * bfq_bic_update_cgroup - update the cgroup of @bic. -+ * @bic: the @bic to update. -+ * -+ * Make sure that @bic is enqueued in the cgroup of the current task. -+ * We need this in addition to moving bics during the cgroup attach -+ * phase because the task owning @bic could be at its first disk -+ * access or we may end up in the root cgroup as the result of a -+ * memory allocation failure and here we try to move to the right -+ * group. -+ * -+ * Must be called under the queue lock. It is safe to use the returned -+ * value even after the rcu_read_unlock() as the migration/destruction -+ * paths act under the queue lock too. IOW it is impossible to race with -+ * group migration/destruction and end up with an invalid group as: -+ * a) here cgroup has not yet been destroyed, nor its destroy callback -+ * has started execution, as current holds a reference to it, -+ * b) if it is destroyed after rcu_read_unlock() [after current is -+ * migrated to a different cgroup] its attach() callback will have -+ * taken care of remove all the references to the old cgroup data. -+ */ -+static struct bfq_group *bfq_bic_update_cgroup(struct bfq_io_cq *bic) -+{ -+ struct bfq_data *bfqd = bic_to_bfqd(bic); -+ struct bfq_group *bfqg; -+ struct cgroup_subsys_state *css; -+ -+ BUG_ON(bfqd == NULL); -+ -+ rcu_read_lock(); -+ css = task_css(current, bfqio_cgrp_id); -+ bfqg = __bfq_bic_change_cgroup(bfqd, bic, css); -+ rcu_read_unlock(); -+ -+ return bfqg; -+} -+ -+/** -+ * bfq_flush_idle_tree - deactivate any entity on the idle tree of @st. -+ * @st: the service tree being flushed. -+ */ -+static inline void bfq_flush_idle_tree(struct bfq_service_tree *st) -+{ -+ struct bfq_entity *entity = st->first_idle; -+ -+ for (; entity != NULL; entity = st->first_idle) -+ __bfq_deactivate_entity(entity, 0); -+} -+ -+/** -+ * bfq_reparent_leaf_entity - move leaf entity to the root_group. -+ * @bfqd: the device data structure with the root group. -+ * @entity: the entity to move. -+ */ -+static inline void bfq_reparent_leaf_entity(struct bfq_data *bfqd, -+ struct bfq_entity *entity) -+{ -+ struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity); -+ -+ BUG_ON(bfqq == NULL); -+ bfq_bfqq_move(bfqd, bfqq, entity, bfqd->root_group); -+ return; -+} -+ -+/** -+ * bfq_reparent_active_entities - move to the root group all active -+ * entities. -+ * @bfqd: the device data structure with the root group. -+ * @bfqg: the group to move from. -+ * @st: the service tree with the entities. -+ * -+ * Needs queue_lock to be taken and reference to be valid over the call. -+ */ -+static inline void bfq_reparent_active_entities(struct bfq_data *bfqd, -+ struct bfq_group *bfqg, -+ struct bfq_service_tree *st) -+{ -+ struct rb_root *active = &st->active; -+ struct bfq_entity *entity = NULL; -+ -+ if (!RB_EMPTY_ROOT(&st->active)) -+ entity = bfq_entity_of(rb_first(active)); -+ -+ for (; entity != NULL; entity = bfq_entity_of(rb_first(active))) -+ bfq_reparent_leaf_entity(bfqd, entity); -+ -+ if (bfqg->sched_data.in_service_entity != NULL) -+ bfq_reparent_leaf_entity(bfqd, -+ bfqg->sched_data.in_service_entity); -+ -+ return; -+} -+ -+/** -+ * bfq_destroy_group - destroy @bfqg. -+ * @bgrp: the bfqio_cgroup containing @bfqg. -+ * @bfqg: the group being destroyed. -+ * -+ * Destroy @bfqg, making sure that it is not referenced from its parent. -+ */ -+static void bfq_destroy_group(struct bfqio_cgroup *bgrp, struct bfq_group *bfqg) -+{ -+ struct bfq_data *bfqd; -+ struct bfq_service_tree *st; -+ struct bfq_entity *entity = bfqg->my_entity; -+ unsigned long uninitialized_var(flags); -+ int i; -+ -+ hlist_del(&bfqg->group_node); -+ -+ /* -+ * Empty all service_trees belonging to this group before -+ * deactivating the group itself. -+ */ -+ for (i = 0; i < BFQ_IOPRIO_CLASSES; i++) { -+ st = bfqg->sched_data.service_tree + i; -+ -+ /* -+ * The idle tree may still contain bfq_queues belonging -+ * to exited task because they never migrated to a different -+ * cgroup from the one being destroyed now. No one else -+ * can access them so it's safe to act without any lock. -+ */ -+ bfq_flush_idle_tree(st); -+ -+ /* -+ * It may happen that some queues are still active -+ * (busy) upon group destruction (if the corresponding -+ * processes have been forced to terminate). We move -+ * all the leaf entities corresponding to these queues -+ * to the root_group. -+ * Also, it may happen that the group has an entity -+ * in service, which is disconnected from the active -+ * tree: it must be moved, too. -+ * There is no need to put the sync queues, as the -+ * scheduler has taken no reference. -+ */ -+ bfqd = bfq_get_bfqd_locked(&bfqg->bfqd, &flags); -+ if (bfqd != NULL) { -+ bfq_reparent_active_entities(bfqd, bfqg, st); -+ bfq_put_bfqd_unlock(bfqd, &flags); -+ } -+ BUG_ON(!RB_EMPTY_ROOT(&st->active)); -+ BUG_ON(!RB_EMPTY_ROOT(&st->idle)); -+ } -+ BUG_ON(bfqg->sched_data.next_in_service != NULL); -+ BUG_ON(bfqg->sched_data.in_service_entity != NULL); -+ -+ /* -+ * We may race with device destruction, take extra care when -+ * dereferencing bfqg->bfqd. -+ */ -+ bfqd = bfq_get_bfqd_locked(&bfqg->bfqd, &flags); -+ if (bfqd != NULL) { -+ hlist_del(&bfqg->bfqd_node); -+ __bfq_deactivate_entity(entity, 0); -+ bfq_put_async_queues(bfqd, bfqg); -+ bfq_put_bfqd_unlock(bfqd, &flags); -+ } -+ BUG_ON(entity->tree != NULL); -+ -+ /* -+ * No need to defer the kfree() to the end of the RCU grace -+ * period: we are called from the destroy() callback of our -+ * cgroup, so we can be sure that no one is a) still using -+ * this cgroup or b) doing lookups in it. -+ */ -+ kfree(bfqg); -+} -+ -+static void bfq_end_wr_async(struct bfq_data *bfqd) -+{ -+ struct hlist_node *tmp; -+ struct bfq_group *bfqg; -+ -+ hlist_for_each_entry_safe(bfqg, tmp, &bfqd->group_list, bfqd_node) -+ bfq_end_wr_async_queues(bfqd, bfqg); -+ bfq_end_wr_async_queues(bfqd, bfqd->root_group); -+} -+ -+/** -+ * bfq_disconnect_groups - disconnect @bfqd from all its groups. -+ * @bfqd: the device descriptor being exited. -+ * -+ * When the device exits we just make sure that no lookup can return -+ * the now unused group structures. They will be deallocated on cgroup -+ * destruction. -+ */ -+static void bfq_disconnect_groups(struct bfq_data *bfqd) -+{ -+ struct hlist_node *tmp; -+ struct bfq_group *bfqg; -+ -+ bfq_log(bfqd, "disconnect_groups beginning"); -+ hlist_for_each_entry_safe(bfqg, tmp, &bfqd->group_list, bfqd_node) { -+ hlist_del(&bfqg->bfqd_node); -+ -+ __bfq_deactivate_entity(bfqg->my_entity, 0); -+ -+ /* -+ * Don't remove from the group hash, just set an -+ * invalid key. No lookups can race with the -+ * assignment as bfqd is being destroyed; this -+ * implies also that new elements cannot be added -+ * to the list. -+ */ -+ rcu_assign_pointer(bfqg->bfqd, NULL); -+ -+ bfq_log(bfqd, "disconnect_groups: put async for group %p", -+ bfqg); -+ bfq_put_async_queues(bfqd, bfqg); -+ } -+} -+ -+static inline void bfq_free_root_group(struct bfq_data *bfqd) -+{ -+ struct bfqio_cgroup *bgrp = &bfqio_root_cgroup; -+ struct bfq_group *bfqg = bfqd->root_group; -+ -+ bfq_put_async_queues(bfqd, bfqg); -+ -+ spin_lock_irq(&bgrp->lock); -+ hlist_del_rcu(&bfqg->group_node); -+ spin_unlock_irq(&bgrp->lock); -+ -+ /* -+ * No need to synchronize_rcu() here: since the device is gone -+ * there cannot be any read-side access to its root_group. -+ */ -+ kfree(bfqg); -+} -+ -+static struct bfq_group *bfq_alloc_root_group(struct bfq_data *bfqd, int node) -+{ -+ struct bfq_group *bfqg; -+ struct bfqio_cgroup *bgrp; -+ int i; -+ -+ bfqg = kzalloc_node(sizeof(*bfqg), GFP_KERNEL, node); -+ if (bfqg == NULL) -+ return NULL; -+ -+ bfqg->entity.parent = NULL; -+ for (i = 0; i < BFQ_IOPRIO_CLASSES; i++) -+ bfqg->sched_data.service_tree[i] = BFQ_SERVICE_TREE_INIT; -+ -+ bgrp = &bfqio_root_cgroup; -+ spin_lock_irq(&bgrp->lock); -+ rcu_assign_pointer(bfqg->bfqd, bfqd); -+ hlist_add_head_rcu(&bfqg->group_node, &bgrp->group_data); -+ spin_unlock_irq(&bgrp->lock); -+ -+ return bfqg; -+} -+ -+#define SHOW_FUNCTION(__VAR) \ -+static u64 bfqio_cgroup_##__VAR##_read(struct cgroup_subsys_state *css, \ -+ struct cftype *cftype) \ -+{ \ -+ struct bfqio_cgroup *bgrp = css_to_bfqio(css); \ -+ u64 ret = -ENODEV; \ -+ \ -+ mutex_lock(&bfqio_mutex); \ -+ if (bfqio_is_removed(bgrp)) \ -+ goto out_unlock; \ -+ \ -+ spin_lock_irq(&bgrp->lock); \ -+ ret = bgrp->__VAR; \ -+ spin_unlock_irq(&bgrp->lock); \ -+ \ -+out_unlock: \ -+ mutex_unlock(&bfqio_mutex); \ -+ return ret; \ -+} -+ -+SHOW_FUNCTION(weight); -+SHOW_FUNCTION(ioprio); -+SHOW_FUNCTION(ioprio_class); -+#undef SHOW_FUNCTION -+ -+#define STORE_FUNCTION(__VAR, __MIN, __MAX) \ -+static int bfqio_cgroup_##__VAR##_write(struct cgroup_subsys_state *css,\ -+ struct cftype *cftype, \ -+ u64 val) \ -+{ \ -+ struct bfqio_cgroup *bgrp = css_to_bfqio(css); \ -+ struct bfq_group *bfqg; \ -+ int ret = -EINVAL; \ -+ \ -+ if (val < (__MIN) || val > (__MAX)) \ -+ return ret; \ -+ \ -+ ret = -ENODEV; \ -+ mutex_lock(&bfqio_mutex); \ -+ if (bfqio_is_removed(bgrp)) \ -+ goto out_unlock; \ -+ ret = 0; \ -+ \ -+ spin_lock_irq(&bgrp->lock); \ -+ bgrp->__VAR = (unsigned short)val; \ -+ hlist_for_each_entry(bfqg, &bgrp->group_data, group_node) { \ -+ /* \ -+ * Setting the ioprio_changed flag of the entity \ -+ * to 1 with new_##__VAR == ##__VAR would re-set \ -+ * the value of the weight to its ioprio mapping. \ -+ * Set the flag only if necessary. \ -+ */ \ -+ if ((unsigned short)val != bfqg->entity.new_##__VAR) { \ -+ bfqg->entity.new_##__VAR = (unsigned short)val; \ -+ /* \ -+ * Make sure that the above new value has been \ -+ * stored in bfqg->entity.new_##__VAR before \ -+ * setting the ioprio_changed flag. In fact, \ -+ * this flag may be read asynchronously (in \ -+ * critical sections protected by a different \ -+ * lock than that held here), and finding this \ -+ * flag set may cause the execution of the code \ -+ * for updating parameters whose value may \ -+ * depend also on bfqg->entity.new_##__VAR (in \ -+ * __bfq_entity_update_weight_prio). \ -+ * This barrier makes sure that the new value \ -+ * of bfqg->entity.new_##__VAR is correctly \ -+ * seen in that code. \ -+ */ \ -+ smp_wmb(); \ -+ bfqg->entity.ioprio_changed = 1; \ -+ } \ -+ } \ -+ spin_unlock_irq(&bgrp->lock); \ -+ \ -+out_unlock: \ -+ mutex_unlock(&bfqio_mutex); \ -+ return ret; \ -+} -+ -+STORE_FUNCTION(weight, BFQ_MIN_WEIGHT, BFQ_MAX_WEIGHT); -+STORE_FUNCTION(ioprio, 0, IOPRIO_BE_NR - 1); -+STORE_FUNCTION(ioprio_class, IOPRIO_CLASS_RT, IOPRIO_CLASS_IDLE); -+#undef STORE_FUNCTION -+ -+static struct cftype bfqio_files[] = { -+ { -+ .name = "weight", -+ .read_u64 = bfqio_cgroup_weight_read, -+ .write_u64 = bfqio_cgroup_weight_write, -+ }, -+ { -+ .name = "ioprio", -+ .read_u64 = bfqio_cgroup_ioprio_read, -+ .write_u64 = bfqio_cgroup_ioprio_write, -+ }, -+ { -+ .name = "ioprio_class", -+ .read_u64 = bfqio_cgroup_ioprio_class_read, -+ .write_u64 = bfqio_cgroup_ioprio_class_write, -+ }, -+ { }, /* terminate */ -+}; -+ -+static struct cgroup_subsys_state *bfqio_create(struct cgroup_subsys_state -+ *parent_css) -+{ -+ struct bfqio_cgroup *bgrp; -+ -+ if (parent_css != NULL) { -+ bgrp = kzalloc(sizeof(*bgrp), GFP_KERNEL); -+ if (bgrp == NULL) -+ return ERR_PTR(-ENOMEM); -+ } else -+ bgrp = &bfqio_root_cgroup; -+ -+ spin_lock_init(&bgrp->lock); -+ INIT_HLIST_HEAD(&bgrp->group_data); -+ bgrp->ioprio = BFQ_DEFAULT_GRP_IOPRIO; -+ bgrp->ioprio_class = BFQ_DEFAULT_GRP_CLASS; -+ -+ return &bgrp->css; -+} -+ -+/* -+ * We cannot support shared io contexts, as we have no means to support -+ * two tasks with the same ioc in two different groups without major rework -+ * of the main bic/bfqq data structures. By now we allow a task to change -+ * its cgroup only if it's the only owner of its ioc; the drawback of this -+ * behavior is that a group containing a task that forked using CLONE_IO -+ * will not be destroyed until the tasks sharing the ioc die. -+ */ -+static int bfqio_can_attach(struct cgroup_subsys_state *css, -+ struct cgroup_taskset *tset) -+{ -+ struct task_struct *task; -+ struct io_context *ioc; -+ int ret = 0; -+ -+ cgroup_taskset_for_each(task, tset) { -+ /* -+ * task_lock() is needed to avoid races with -+ * exit_io_context() -+ */ -+ task_lock(task); -+ ioc = task->io_context; -+ if (ioc != NULL && atomic_read(&ioc->nr_tasks) > 1) -+ /* -+ * ioc == NULL means that the task is either too -+ * young or exiting: if it has still no ioc the -+ * ioc can't be shared, if the task is exiting the -+ * attach will fail anyway, no matter what we -+ * return here. -+ */ -+ ret = -EINVAL; -+ task_unlock(task); -+ if (ret) -+ break; -+ } -+ -+ return ret; -+} -+ -+static void bfqio_attach(struct cgroup_subsys_state *css, -+ struct cgroup_taskset *tset) -+{ -+ struct task_struct *task; -+ struct io_context *ioc; -+ struct io_cq *icq; -+ -+ /* -+ * IMPORTANT NOTE: The move of more than one process at a time to a -+ * new group has not yet been tested. -+ */ -+ cgroup_taskset_for_each(task, tset) { -+ ioc = get_task_io_context(task, GFP_ATOMIC, NUMA_NO_NODE); -+ if (ioc) { -+ /* -+ * Handle cgroup change here. -+ */ -+ rcu_read_lock(); -+ hlist_for_each_entry_rcu(icq, &ioc->icq_list, ioc_node) -+ if (!strncmp( -+ icq->q->elevator->type->elevator_name, -+ "bfq", ELV_NAME_MAX)) -+ bfq_bic_change_cgroup(icq_to_bic(icq), -+ css); -+ rcu_read_unlock(); -+ put_io_context(ioc); -+ } -+ } -+} -+ -+static void bfqio_destroy(struct cgroup_subsys_state *css) -+{ -+ struct bfqio_cgroup *bgrp = css_to_bfqio(css); -+ struct hlist_node *tmp; -+ struct bfq_group *bfqg; -+ -+ /* -+ * Since we are destroying the cgroup, there are no more tasks -+ * referencing it, and all the RCU grace periods that may have -+ * referenced it are ended (as the destruction of the parent -+ * cgroup is RCU-safe); bgrp->group_data will not be accessed by -+ * anything else and we don't need any synchronization. -+ */ -+ hlist_for_each_entry_safe(bfqg, tmp, &bgrp->group_data, group_node) -+ bfq_destroy_group(bgrp, bfqg); -+ -+ BUG_ON(!hlist_empty(&bgrp->group_data)); -+ -+ kfree(bgrp); -+} -+ -+static int bfqio_css_online(struct cgroup_subsys_state *css) -+{ -+ struct bfqio_cgroup *bgrp = css_to_bfqio(css); -+ -+ mutex_lock(&bfqio_mutex); -+ bgrp->online = true; -+ mutex_unlock(&bfqio_mutex); -+ -+ return 0; -+} -+ -+static void bfqio_css_offline(struct cgroup_subsys_state *css) -+{ -+ struct bfqio_cgroup *bgrp = css_to_bfqio(css); -+ -+ mutex_lock(&bfqio_mutex); -+ bgrp->online = false; -+ mutex_unlock(&bfqio_mutex); -+} -+ -+struct cgroup_subsys bfqio_cgrp_subsys = { -+ .css_alloc = bfqio_create, -+ .css_online = bfqio_css_online, -+ .css_offline = bfqio_css_offline, -+ .can_attach = bfqio_can_attach, -+ .attach = bfqio_attach, -+ .css_free = bfqio_destroy, -+ .legacy_cftypes = bfqio_files, -+}; -+#else -+static inline void bfq_init_entity(struct bfq_entity *entity, -+ struct bfq_group *bfqg) -+{ -+ entity->weight = entity->new_weight; -+ entity->orig_weight = entity->new_weight; -+ entity->ioprio = entity->new_ioprio; -+ entity->ioprio_class = entity->new_ioprio_class; -+ entity->sched_data = &bfqg->sched_data; -+} -+ -+static inline struct bfq_group * -+bfq_bic_update_cgroup(struct bfq_io_cq *bic) -+{ -+ struct bfq_data *bfqd = bic_to_bfqd(bic); -+ return bfqd->root_group; -+} -+ -+static inline void bfq_bfqq_move(struct bfq_data *bfqd, -+ struct bfq_queue *bfqq, -+ struct bfq_entity *entity, -+ struct bfq_group *bfqg) -+{ -+} -+ -+static void bfq_end_wr_async(struct bfq_data *bfqd) -+{ -+ bfq_end_wr_async_queues(bfqd, bfqd->root_group); -+} -+ -+static inline void bfq_disconnect_groups(struct bfq_data *bfqd) -+{ -+ bfq_put_async_queues(bfqd, bfqd->root_group); -+} -+ -+static inline void bfq_free_root_group(struct bfq_data *bfqd) -+{ -+ kfree(bfqd->root_group); -+} -+ -+static struct bfq_group *bfq_alloc_root_group(struct bfq_data *bfqd, int node) -+{ -+ struct bfq_group *bfqg; -+ int i; -+ -+ bfqg = kmalloc_node(sizeof(*bfqg), GFP_KERNEL | __GFP_ZERO, node); -+ if (bfqg == NULL) -+ return NULL; -+ -+ for (i = 0; i < BFQ_IOPRIO_CLASSES; i++) -+ bfqg->sched_data.service_tree[i] = BFQ_SERVICE_TREE_INIT; -+ -+ return bfqg; -+} -+#endif -diff -Nur linux-4.1.13.orig/block/bfq.h linux-4.1.13/block/bfq.h ---- linux-4.1.13.orig/block/bfq.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/block/bfq.h 2015-11-30 17:56:13.536140654 +0100 -@@ -0,0 +1,811 @@ -+/* -+ * BFQ-v7r7 for 4.0.0: data structures and common functions prototypes. -+ * -+ * Based on ideas and code from CFQ: -+ * Copyright (C) 2003 Jens Axboe -+ * -+ * Copyright (C) 2008 Fabio Checconi -+ * Paolo Valente -+ * -+ * Copyright (C) 2010 Paolo Valente -+ */ -+ -+#ifndef _BFQ_H -+#define _BFQ_H -+ -+#include -+#include -+#include -+#include -+ -+#define BFQ_IOPRIO_CLASSES 3 -+#define BFQ_CL_IDLE_TIMEOUT (HZ/5) -+ -+#define BFQ_MIN_WEIGHT 1 -+#define BFQ_MAX_WEIGHT 1000 -+ -+#define BFQ_DEFAULT_QUEUE_IOPRIO 4 -+ -+#define BFQ_DEFAULT_GRP_WEIGHT 10 -+#define BFQ_DEFAULT_GRP_IOPRIO 0 -+#define BFQ_DEFAULT_GRP_CLASS IOPRIO_CLASS_BE -+ -+struct bfq_entity; -+ -+/** -+ * struct bfq_service_tree - per ioprio_class service tree. -+ * @active: tree for active entities (i.e., those backlogged). -+ * @idle: tree for idle entities (i.e., those not backlogged, with V <= F_i). -+ * @first_idle: idle entity with minimum F_i. -+ * @last_idle: idle entity with maximum F_i. -+ * @vtime: scheduler virtual time. -+ * @wsum: scheduler weight sum; active and idle entities contribute to it. -+ * -+ * Each service tree represents a B-WF2Q+ scheduler on its own. Each -+ * ioprio_class has its own independent scheduler, and so its own -+ * bfq_service_tree. All the fields are protected by the queue lock -+ * of the containing bfqd. -+ */ -+struct bfq_service_tree { -+ struct rb_root active; -+ struct rb_root idle; -+ -+ struct bfq_entity *first_idle; -+ struct bfq_entity *last_idle; -+ -+ u64 vtime; -+ unsigned long wsum; -+}; -+ -+/** -+ * struct bfq_sched_data - multi-class scheduler. -+ * @in_service_entity: entity in service. -+ * @next_in_service: head-of-the-line entity in the scheduler. -+ * @service_tree: array of service trees, one per ioprio_class. -+ * -+ * bfq_sched_data is the basic scheduler queue. It supports three -+ * ioprio_classes, and can be used either as a toplevel queue or as -+ * an intermediate queue on a hierarchical setup. -+ * @next_in_service points to the active entity of the sched_data -+ * service trees that will be scheduled next. -+ * -+ * The supported ioprio_classes are the same as in CFQ, in descending -+ * priority order, IOPRIO_CLASS_RT, IOPRIO_CLASS_BE, IOPRIO_CLASS_IDLE. -+ * Requests from higher priority queues are served before all the -+ * requests from lower priority queues; among requests of the same -+ * queue requests are served according to B-WF2Q+. -+ * All the fields are protected by the queue lock of the containing bfqd. -+ */ -+struct bfq_sched_data { -+ struct bfq_entity *in_service_entity; -+ struct bfq_entity *next_in_service; -+ struct bfq_service_tree service_tree[BFQ_IOPRIO_CLASSES]; -+}; -+ -+/** -+ * struct bfq_weight_counter - counter of the number of all active entities -+ * with a given weight. -+ * @weight: weight of the entities that this counter refers to. -+ * @num_active: number of active entities with this weight. -+ * @weights_node: weights tree member (see bfq_data's @queue_weights_tree -+ * and @group_weights_tree). -+ */ -+struct bfq_weight_counter { -+ short int weight; -+ unsigned int num_active; -+ struct rb_node weights_node; -+}; -+ -+/** -+ * struct bfq_entity - schedulable entity. -+ * @rb_node: service_tree member. -+ * @weight_counter: pointer to the weight counter associated with this entity. -+ * @on_st: flag, true if the entity is on a tree (either the active or -+ * the idle one of its service_tree). -+ * @finish: B-WF2Q+ finish timestamp (aka F_i). -+ * @start: B-WF2Q+ start timestamp (aka S_i). -+ * @tree: tree the entity is enqueued into; %NULL if not on a tree. -+ * @min_start: minimum start time of the (active) subtree rooted at -+ * this entity; used for O(log N) lookups into active trees. -+ * @service: service received during the last round of service. -+ * @budget: budget used to calculate F_i; F_i = S_i + @budget / @weight. -+ * @weight: weight of the queue -+ * @parent: parent entity, for hierarchical scheduling. -+ * @my_sched_data: for non-leaf nodes in the cgroup hierarchy, the -+ * associated scheduler queue, %NULL on leaf nodes. -+ * @sched_data: the scheduler queue this entity belongs to. -+ * @ioprio: the ioprio in use. -+ * @new_weight: when a weight change is requested, the new weight value. -+ * @orig_weight: original weight, used to implement weight boosting -+ * @new_ioprio: when an ioprio change is requested, the new ioprio value. -+ * @ioprio_class: the ioprio_class in use. -+ * @new_ioprio_class: when an ioprio_class change is requested, the new -+ * ioprio_class value. -+ * @ioprio_changed: flag, true when the user requested a weight, ioprio or -+ * ioprio_class change. -+ * -+ * A bfq_entity is used to represent either a bfq_queue (leaf node in the -+ * cgroup hierarchy) or a bfq_group into the upper level scheduler. Each -+ * entity belongs to the sched_data of the parent group in the cgroup -+ * hierarchy. Non-leaf entities have also their own sched_data, stored -+ * in @my_sched_data. -+ * -+ * Each entity stores independently its priority values; this would -+ * allow different weights on different devices, but this -+ * functionality is not exported to userspace by now. Priorities and -+ * weights are updated lazily, first storing the new values into the -+ * new_* fields, then setting the @ioprio_changed flag. As soon as -+ * there is a transition in the entity state that allows the priority -+ * update to take place the effective and the requested priority -+ * values are synchronized. -+ * -+ * Unless cgroups are used, the weight value is calculated from the -+ * ioprio to export the same interface as CFQ. When dealing with -+ * ``well-behaved'' queues (i.e., queues that do not spend too much -+ * time to consume their budget and have true sequential behavior, and -+ * when there are no external factors breaking anticipation) the -+ * relative weights at each level of the cgroups hierarchy should be -+ * guaranteed. All the fields are protected by the queue lock of the -+ * containing bfqd. -+ */ -+struct bfq_entity { -+ struct rb_node rb_node; -+ struct bfq_weight_counter *weight_counter; -+ -+ int on_st; -+ -+ u64 finish; -+ u64 start; -+ -+ struct rb_root *tree; -+ -+ u64 min_start; -+ -+ unsigned long service, budget; -+ unsigned short weight, new_weight; -+ unsigned short orig_weight; -+ -+ struct bfq_entity *parent; -+ -+ struct bfq_sched_data *my_sched_data; -+ struct bfq_sched_data *sched_data; -+ -+ unsigned short ioprio, new_ioprio; -+ unsigned short ioprio_class, new_ioprio_class; -+ -+ int ioprio_changed; -+}; -+ -+struct bfq_group; -+ -+/** -+ * struct bfq_queue - leaf schedulable entity. -+ * @ref: reference counter. -+ * @bfqd: parent bfq_data. -+ * @new_bfqq: shared bfq_queue if queue is cooperating with -+ * one or more other queues. -+ * @pos_node: request-position tree member (see bfq_data's @rq_pos_tree). -+ * @pos_root: request-position tree root (see bfq_data's @rq_pos_tree). -+ * @sort_list: sorted list of pending requests. -+ * @next_rq: if fifo isn't expired, next request to serve. -+ * @queued: nr of requests queued in @sort_list. -+ * @allocated: currently allocated requests. -+ * @meta_pending: pending metadata requests. -+ * @fifo: fifo list of requests in sort_list. -+ * @entity: entity representing this queue in the scheduler. -+ * @max_budget: maximum budget allowed from the feedback mechanism. -+ * @budget_timeout: budget expiration (in jiffies). -+ * @dispatched: number of requests on the dispatch list or inside driver. -+ * @flags: status flags. -+ * @bfqq_list: node for active/idle bfqq list inside our bfqd. -+ * @burst_list_node: node for the device's burst list. -+ * @seek_samples: number of seeks sampled -+ * @seek_total: sum of the distances of the seeks sampled -+ * @seek_mean: mean seek distance -+ * @last_request_pos: position of the last request enqueued -+ * @requests_within_timer: number of consecutive pairs of request completion -+ * and arrival, such that the queue becomes idle -+ * after the completion, but the next request arrives -+ * within an idle time slice; used only if the queue's -+ * IO_bound has been cleared. -+ * @pid: pid of the process owning the queue, used for logging purposes. -+ * @last_wr_start_finish: start time of the current weight-raising period if -+ * the @bfq-queue is being weight-raised, otherwise -+ * finish time of the last weight-raising period -+ * @wr_cur_max_time: current max raising time for this queue -+ * @soft_rt_next_start: minimum time instant such that, only if a new -+ * request is enqueued after this time instant in an -+ * idle @bfq_queue with no outstanding requests, then -+ * the task associated with the queue it is deemed as -+ * soft real-time (see the comments to the function -+ * bfq_bfqq_softrt_next_start()) -+ * @last_idle_bklogged: time of the last transition of the @bfq_queue from -+ * idle to backlogged -+ * @service_from_backlogged: cumulative service received from the @bfq_queue -+ * since the last transition from idle to -+ * backlogged -+ * @bic: pointer to the bfq_io_cq owning the bfq_queue, set to %NULL if the -+ * queue is shared -+ * -+ * A bfq_queue is a leaf request queue; it can be associated with an -+ * io_context or more, if it is async or shared between cooperating -+ * processes. @cgroup holds a reference to the cgroup, to be sure that it -+ * does not disappear while a bfqq still references it (mostly to avoid -+ * races between request issuing and task migration followed by cgroup -+ * destruction). -+ * All the fields are protected by the queue lock of the containing bfqd. -+ */ -+struct bfq_queue { -+ atomic_t ref; -+ struct bfq_data *bfqd; -+ -+ /* fields for cooperating queues handling */ -+ struct bfq_queue *new_bfqq; -+ struct rb_node pos_node; -+ struct rb_root *pos_root; -+ -+ struct rb_root sort_list; -+ struct request *next_rq; -+ int queued[2]; -+ int allocated[2]; -+ int meta_pending; -+ struct list_head fifo; -+ -+ struct bfq_entity entity; -+ -+ unsigned long max_budget; -+ unsigned long budget_timeout; -+ -+ int dispatched; -+ -+ unsigned int flags; -+ -+ struct list_head bfqq_list; -+ -+ struct hlist_node burst_list_node; -+ -+ unsigned int seek_samples; -+ u64 seek_total; -+ sector_t seek_mean; -+ sector_t last_request_pos; -+ -+ unsigned int requests_within_timer; -+ -+ pid_t pid; -+ struct bfq_io_cq *bic; -+ -+ /* weight-raising fields */ -+ unsigned long wr_cur_max_time; -+ unsigned long soft_rt_next_start; -+ unsigned long last_wr_start_finish; -+ unsigned int wr_coeff; -+ unsigned long last_idle_bklogged; -+ unsigned long service_from_backlogged; -+}; -+ -+/** -+ * struct bfq_ttime - per process thinktime stats. -+ * @ttime_total: total process thinktime -+ * @ttime_samples: number of thinktime samples -+ * @ttime_mean: average process thinktime -+ */ -+struct bfq_ttime { -+ unsigned long last_end_request; -+ -+ unsigned long ttime_total; -+ unsigned long ttime_samples; -+ unsigned long ttime_mean; -+}; -+ -+/** -+ * struct bfq_io_cq - per (request_queue, io_context) structure. -+ * @icq: associated io_cq structure -+ * @bfqq: array of two process queues, the sync and the async -+ * @ttime: associated @bfq_ttime struct -+ * @wr_time_left: snapshot of the time left before weight raising ends -+ * for the sync queue associated to this process; this -+ * snapshot is taken to remember this value while the weight -+ * raising is suspended because the queue is merged with a -+ * shared queue, and is used to set @raising_cur_max_time -+ * when the queue is split from the shared queue and its -+ * weight is raised again -+ * @saved_idle_window: same purpose as the previous field for the idle -+ * window -+ * @saved_IO_bound: same purpose as the previous two fields for the I/O -+ * bound classification of a queue -+ * @saved_in_large_burst: same purpose as the previous fields for the -+ * value of the field keeping the queue's belonging -+ * to a large burst -+ * @was_in_burst_list: true if the queue belonged to a burst list -+ * before its merge with another cooperating queue -+ * @cooperations: counter of consecutive successful queue merges underwent -+ * by any of the process' @bfq_queues -+ * @failed_cooperations: counter of consecutive failed queue merges of any -+ * of the process' @bfq_queues -+ */ -+struct bfq_io_cq { -+ struct io_cq icq; /* must be the first member */ -+ struct bfq_queue *bfqq[2]; -+ struct bfq_ttime ttime; -+ int ioprio; -+ -+ unsigned int wr_time_left; -+ bool saved_idle_window; -+ bool saved_IO_bound; -+ -+ bool saved_in_large_burst; -+ bool was_in_burst_list; -+ -+ unsigned int cooperations; -+ unsigned int failed_cooperations; -+}; -+ -+enum bfq_device_speed { -+ BFQ_BFQD_FAST, -+ BFQ_BFQD_SLOW, -+}; -+ -+/** -+ * struct bfq_data - per device data structure. -+ * @queue: request queue for the managed device. -+ * @root_group: root bfq_group for the device. -+ * @rq_pos_tree: rbtree sorted by next_request position, used when -+ * determining if two or more queues have interleaving -+ * requests (see bfq_close_cooperator()). -+ * @active_numerous_groups: number of bfq_groups containing more than one -+ * active @bfq_entity. -+ * @queue_weights_tree: rbtree of weight counters of @bfq_queues, sorted by -+ * weight. Used to keep track of whether all @bfq_queues -+ * have the same weight. The tree contains one counter -+ * for each distinct weight associated to some active -+ * and not weight-raised @bfq_queue (see the comments to -+ * the functions bfq_weights_tree_[add|remove] for -+ * further details). -+ * @group_weights_tree: rbtree of non-queue @bfq_entity weight counters, sorted -+ * by weight. Used to keep track of whether all -+ * @bfq_groups have the same weight. The tree contains -+ * one counter for each distinct weight associated to -+ * some active @bfq_group (see the comments to the -+ * functions bfq_weights_tree_[add|remove] for further -+ * details). -+ * @busy_queues: number of bfq_queues containing requests (including the -+ * queue in service, even if it is idling). -+ * @busy_in_flight_queues: number of @bfq_queues containing pending or -+ * in-flight requests, plus the @bfq_queue in -+ * service, even if idle but waiting for the -+ * possible arrival of its next sync request. This -+ * field is updated only if the device is rotational, -+ * but used only if the device is also NCQ-capable. -+ * The reason why the field is updated also for non- -+ * NCQ-capable rotational devices is related to the -+ * fact that the value of @hw_tag may be set also -+ * later than when busy_in_flight_queues may need to -+ * be incremented for the first time(s). Taking also -+ * this possibility into account, to avoid unbalanced -+ * increments/decrements, would imply more overhead -+ * than just updating busy_in_flight_queues -+ * regardless of the value of @hw_tag. -+ * @const_seeky_busy_in_flight_queues: number of constantly-seeky @bfq_queues -+ * (that is, seeky queues that expired -+ * for budget timeout at least once) -+ * containing pending or in-flight -+ * requests, including the in-service -+ * @bfq_queue if constantly seeky. This -+ * field is updated only if the device -+ * is rotational, but used only if the -+ * device is also NCQ-capable (see the -+ * comments to @busy_in_flight_queues). -+ * @wr_busy_queues: number of weight-raised busy @bfq_queues. -+ * @queued: number of queued requests. -+ * @rq_in_driver: number of requests dispatched and waiting for completion. -+ * @sync_flight: number of sync requests in the driver. -+ * @max_rq_in_driver: max number of reqs in driver in the last -+ * @hw_tag_samples completed requests. -+ * @hw_tag_samples: nr of samples used to calculate hw_tag. -+ * @hw_tag: flag set to one if the driver is showing a queueing behavior. -+ * @budgets_assigned: number of budgets assigned. -+ * @idle_slice_timer: timer set when idling for the next sequential request -+ * from the queue in service. -+ * @unplug_work: delayed work to restart dispatching on the request queue. -+ * @in_service_queue: bfq_queue in service. -+ * @in_service_bic: bfq_io_cq (bic) associated with the @in_service_queue. -+ * @last_position: on-disk position of the last served request. -+ * @last_budget_start: beginning of the last budget. -+ * @last_idling_start: beginning of the last idle slice. -+ * @peak_rate: peak transfer rate observed for a budget. -+ * @peak_rate_samples: number of samples used to calculate @peak_rate. -+ * @bfq_max_budget: maximum budget allotted to a bfq_queue before -+ * rescheduling. -+ * @group_list: list of all the bfq_groups active on the device. -+ * @active_list: list of all the bfq_queues active on the device. -+ * @idle_list: list of all the bfq_queues idle on the device. -+ * @bfq_quantum: max number of requests dispatched per dispatch round. -+ * @bfq_fifo_expire: timeout for async/sync requests; when it expires -+ * requests are served in fifo order. -+ * @bfq_back_penalty: weight of backward seeks wrt forward ones. -+ * @bfq_back_max: maximum allowed backward seek. -+ * @bfq_slice_idle: maximum idling time. -+ * @bfq_user_max_budget: user-configured max budget value -+ * (0 for auto-tuning). -+ * @bfq_max_budget_async_rq: maximum budget (in nr of requests) allotted to -+ * async queues. -+ * @bfq_timeout: timeout for bfq_queues to consume their budget; used to -+ * to prevent seeky queues to impose long latencies to well -+ * behaved ones (this also implies that seeky queues cannot -+ * receive guarantees in the service domain; after a timeout -+ * they are charged for the whole allocated budget, to try -+ * to preserve a behavior reasonably fair among them, but -+ * without service-domain guarantees). -+ * @bfq_coop_thresh: number of queue merges after which a @bfq_queue is -+ * no more granted any weight-raising. -+ * @bfq_failed_cooperations: number of consecutive failed cooperation -+ * chances after which weight-raising is restored -+ * to a queue subject to more than bfq_coop_thresh -+ * queue merges. -+ * @bfq_requests_within_timer: number of consecutive requests that must be -+ * issued within the idle time slice to set -+ * again idling to a queue which was marked as -+ * non-I/O-bound (see the definition of the -+ * IO_bound flag for further details). -+ * @last_ins_in_burst: last time at which a queue entered the current -+ * burst of queues being activated shortly after -+ * each other; for more details about this and the -+ * following parameters related to a burst of -+ * activations, see the comments to the function -+ * @bfq_handle_burst. -+ * @bfq_burst_interval: reference time interval used to decide whether a -+ * queue has been activated shortly after -+ * @last_ins_in_burst. -+ * @burst_size: number of queues in the current burst of queue activations. -+ * @bfq_large_burst_thresh: maximum burst size above which the current -+ * queue-activation burst is deemed as 'large'. -+ * @large_burst: true if a large queue-activation burst is in progress. -+ * @burst_list: head of the burst list (as for the above fields, more details -+ * in the comments to the function bfq_handle_burst). -+ * @low_latency: if set to true, low-latency heuristics are enabled. -+ * @bfq_wr_coeff: maximum factor by which the weight of a weight-raised -+ * queue is multiplied. -+ * @bfq_wr_max_time: maximum duration of a weight-raising period (jiffies). -+ * @bfq_wr_rt_max_time: maximum duration for soft real-time processes. -+ * @bfq_wr_min_idle_time: minimum idle period after which weight-raising -+ * may be reactivated for a queue (in jiffies). -+ * @bfq_wr_min_inter_arr_async: minimum period between request arrivals -+ * after which weight-raising may be -+ * reactivated for an already busy queue -+ * (in jiffies). -+ * @bfq_wr_max_softrt_rate: max service-rate for a soft real-time queue, -+ * sectors per seconds. -+ * @RT_prod: cached value of the product R*T used for computing the maximum -+ * duration of the weight raising automatically. -+ * @device_speed: device-speed class for the low-latency heuristic. -+ * @oom_bfqq: fallback dummy bfqq for extreme OOM conditions. -+ * -+ * All the fields are protected by the @queue lock. -+ */ -+struct bfq_data { -+ struct request_queue *queue; -+ -+ struct bfq_group *root_group; -+ struct rb_root rq_pos_tree; -+ -+#ifdef CONFIG_CGROUP_BFQIO -+ int active_numerous_groups; -+#endif -+ -+ struct rb_root queue_weights_tree; -+ struct rb_root group_weights_tree; -+ -+ int busy_queues; -+ int busy_in_flight_queues; -+ int const_seeky_busy_in_flight_queues; -+ int wr_busy_queues; -+ int queued; -+ int rq_in_driver; -+ int sync_flight; -+ -+ int max_rq_in_driver; -+ int hw_tag_samples; -+ int hw_tag; -+ -+ int budgets_assigned; -+ -+ struct timer_list idle_slice_timer; -+ struct work_struct unplug_work; -+ -+ struct bfq_queue *in_service_queue; -+ struct bfq_io_cq *in_service_bic; -+ -+ sector_t last_position; -+ -+ ktime_t last_budget_start; -+ ktime_t last_idling_start; -+ int peak_rate_samples; -+ u64 peak_rate; -+ unsigned long bfq_max_budget; -+ -+ struct hlist_head group_list; -+ struct list_head active_list; -+ struct list_head idle_list; -+ -+ unsigned int bfq_quantum; -+ unsigned int bfq_fifo_expire[2]; -+ unsigned int bfq_back_penalty; -+ unsigned int bfq_back_max; -+ unsigned int bfq_slice_idle; -+ u64 bfq_class_idle_last_service; -+ -+ unsigned int bfq_user_max_budget; -+ unsigned int bfq_max_budget_async_rq; -+ unsigned int bfq_timeout[2]; -+ -+ unsigned int bfq_coop_thresh; -+ unsigned int bfq_failed_cooperations; -+ unsigned int bfq_requests_within_timer; -+ -+ unsigned long last_ins_in_burst; -+ unsigned long bfq_burst_interval; -+ int burst_size; -+ unsigned long bfq_large_burst_thresh; -+ bool large_burst; -+ struct hlist_head burst_list; -+ -+ bool low_latency; -+ -+ /* parameters of the low_latency heuristics */ -+ unsigned int bfq_wr_coeff; -+ unsigned int bfq_wr_max_time; -+ unsigned int bfq_wr_rt_max_time; -+ unsigned int bfq_wr_min_idle_time; -+ unsigned long bfq_wr_min_inter_arr_async; -+ unsigned int bfq_wr_max_softrt_rate; -+ u64 RT_prod; -+ enum bfq_device_speed device_speed; -+ -+ struct bfq_queue oom_bfqq; -+}; -+ -+enum bfqq_state_flags { -+ BFQ_BFQQ_FLAG_busy = 0, /* has requests or is in service */ -+ BFQ_BFQQ_FLAG_wait_request, /* waiting for a request */ -+ BFQ_BFQQ_FLAG_must_alloc, /* must be allowed rq alloc */ -+ BFQ_BFQQ_FLAG_fifo_expire, /* FIFO checked in this slice */ -+ BFQ_BFQQ_FLAG_idle_window, /* slice idling enabled */ -+ BFQ_BFQQ_FLAG_prio_changed, /* task priority has changed */ -+ BFQ_BFQQ_FLAG_sync, /* synchronous queue */ -+ BFQ_BFQQ_FLAG_budget_new, /* no completion with this budget */ -+ BFQ_BFQQ_FLAG_IO_bound, /* -+ * bfqq has timed-out at least once -+ * having consumed at most 2/10 of -+ * its budget -+ */ -+ BFQ_BFQQ_FLAG_in_large_burst, /* -+ * bfqq activated in a large burst, -+ * see comments to bfq_handle_burst. -+ */ -+ BFQ_BFQQ_FLAG_constantly_seeky, /* -+ * bfqq has proved to be slow and -+ * seeky until budget timeout -+ */ -+ BFQ_BFQQ_FLAG_softrt_update, /* -+ * may need softrt-next-start -+ * update -+ */ -+ BFQ_BFQQ_FLAG_coop, /* bfqq is shared */ -+ BFQ_BFQQ_FLAG_split_coop, /* shared bfqq will be split */ -+ BFQ_BFQQ_FLAG_just_split, /* queue has just been split */ -+}; -+ -+#define BFQ_BFQQ_FNS(name) \ -+static inline void bfq_mark_bfqq_##name(struct bfq_queue *bfqq) \ -+{ \ -+ (bfqq)->flags |= (1 << BFQ_BFQQ_FLAG_##name); \ -+} \ -+static inline void bfq_clear_bfqq_##name(struct bfq_queue *bfqq) \ -+{ \ -+ (bfqq)->flags &= ~(1 << BFQ_BFQQ_FLAG_##name); \ -+} \ -+static inline int bfq_bfqq_##name(const struct bfq_queue *bfqq) \ -+{ \ -+ return ((bfqq)->flags & (1 << BFQ_BFQQ_FLAG_##name)) != 0; \ -+} -+ -+BFQ_BFQQ_FNS(busy); -+BFQ_BFQQ_FNS(wait_request); -+BFQ_BFQQ_FNS(must_alloc); -+BFQ_BFQQ_FNS(fifo_expire); -+BFQ_BFQQ_FNS(idle_window); -+BFQ_BFQQ_FNS(prio_changed); -+BFQ_BFQQ_FNS(sync); -+BFQ_BFQQ_FNS(budget_new); -+BFQ_BFQQ_FNS(IO_bound); -+BFQ_BFQQ_FNS(in_large_burst); -+BFQ_BFQQ_FNS(constantly_seeky); -+BFQ_BFQQ_FNS(coop); -+BFQ_BFQQ_FNS(split_coop); -+BFQ_BFQQ_FNS(just_split); -+BFQ_BFQQ_FNS(softrt_update); -+#undef BFQ_BFQQ_FNS -+ -+/* Logging facilities. */ -+#define bfq_log_bfqq(bfqd, bfqq, fmt, args...) \ -+ blk_add_trace_msg((bfqd)->queue, "bfq%d " fmt, (bfqq)->pid, ##args) -+ -+#define bfq_log(bfqd, fmt, args...) \ -+ blk_add_trace_msg((bfqd)->queue, "bfq " fmt, ##args) -+ -+/* Expiration reasons. */ -+enum bfqq_expiration { -+ BFQ_BFQQ_TOO_IDLE = 0, /* -+ * queue has been idling for -+ * too long -+ */ -+ BFQ_BFQQ_BUDGET_TIMEOUT, /* budget took too long to be used */ -+ BFQ_BFQQ_BUDGET_EXHAUSTED, /* budget consumed */ -+ BFQ_BFQQ_NO_MORE_REQUESTS, /* the queue has no more requests */ -+}; -+ -+#ifdef CONFIG_CGROUP_BFQIO -+/** -+ * struct bfq_group - per (device, cgroup) data structure. -+ * @entity: schedulable entity to insert into the parent group sched_data. -+ * @sched_data: own sched_data, to contain child entities (they may be -+ * both bfq_queues and bfq_groups). -+ * @group_node: node to be inserted into the bfqio_cgroup->group_data -+ * list of the containing cgroup's bfqio_cgroup. -+ * @bfqd_node: node to be inserted into the @bfqd->group_list list -+ * of the groups active on the same device; used for cleanup. -+ * @bfqd: the bfq_data for the device this group acts upon. -+ * @async_bfqq: array of async queues for all the tasks belonging to -+ * the group, one queue per ioprio value per ioprio_class, -+ * except for the idle class that has only one queue. -+ * @async_idle_bfqq: async queue for the idle class (ioprio is ignored). -+ * @my_entity: pointer to @entity, %NULL for the toplevel group; used -+ * to avoid too many special cases during group creation/ -+ * migration. -+ * @active_entities: number of active entities belonging to the group; -+ * unused for the root group. Used to know whether there -+ * are groups with more than one active @bfq_entity -+ * (see the comments to the function -+ * bfq_bfqq_must_not_expire()). -+ * -+ * Each (device, cgroup) pair has its own bfq_group, i.e., for each cgroup -+ * there is a set of bfq_groups, each one collecting the lower-level -+ * entities belonging to the group that are acting on the same device. -+ * -+ * Locking works as follows: -+ * o @group_node is protected by the bfqio_cgroup lock, and is accessed -+ * via RCU from its readers. -+ * o @bfqd is protected by the queue lock, RCU is used to access it -+ * from the readers. -+ * o All the other fields are protected by the @bfqd queue lock. -+ */ -+struct bfq_group { -+ struct bfq_entity entity; -+ struct bfq_sched_data sched_data; -+ -+ struct hlist_node group_node; -+ struct hlist_node bfqd_node; -+ -+ void *bfqd; -+ -+ struct bfq_queue *async_bfqq[2][IOPRIO_BE_NR]; -+ struct bfq_queue *async_idle_bfqq; -+ -+ struct bfq_entity *my_entity; -+ -+ int active_entities; -+}; -+ -+/** -+ * struct bfqio_cgroup - bfq cgroup data structure. -+ * @css: subsystem state for bfq in the containing cgroup. -+ * @online: flag marked when the subsystem is inserted. -+ * @weight: cgroup weight. -+ * @ioprio: cgroup ioprio. -+ * @ioprio_class: cgroup ioprio_class. -+ * @lock: spinlock that protects @ioprio, @ioprio_class and @group_data. -+ * @group_data: list containing the bfq_group belonging to this cgroup. -+ * -+ * @group_data is accessed using RCU, with @lock protecting the updates, -+ * @ioprio and @ioprio_class are protected by @lock. -+ */ -+struct bfqio_cgroup { -+ struct cgroup_subsys_state css; -+ bool online; -+ -+ unsigned short weight, ioprio, ioprio_class; -+ -+ spinlock_t lock; -+ struct hlist_head group_data; -+}; -+#else -+struct bfq_group { -+ struct bfq_sched_data sched_data; -+ -+ struct bfq_queue *async_bfqq[2][IOPRIO_BE_NR]; -+ struct bfq_queue *async_idle_bfqq; -+}; -+#endif -+ -+static inline struct bfq_service_tree * -+bfq_entity_service_tree(struct bfq_entity *entity) -+{ -+ struct bfq_sched_data *sched_data = entity->sched_data; -+ unsigned int idx = entity->ioprio_class - 1; -+ -+ BUG_ON(idx >= BFQ_IOPRIO_CLASSES); -+ BUG_ON(sched_data == NULL); -+ -+ return sched_data->service_tree + idx; -+} -+ -+static inline struct bfq_queue *bic_to_bfqq(struct bfq_io_cq *bic, -+ bool is_sync) -+{ -+ return bic->bfqq[is_sync]; -+} -+ -+static inline void bic_set_bfqq(struct bfq_io_cq *bic, -+ struct bfq_queue *bfqq, bool is_sync) -+{ -+ bic->bfqq[is_sync] = bfqq; -+} -+ -+static inline struct bfq_data *bic_to_bfqd(struct bfq_io_cq *bic) -+{ -+ return bic->icq.q->elevator->elevator_data; -+} -+ -+/** -+ * bfq_get_bfqd_locked - get a lock to a bfqd using a RCU protected pointer. -+ * @ptr: a pointer to a bfqd. -+ * @flags: storage for the flags to be saved. -+ * -+ * This function allows bfqg->bfqd to be protected by the -+ * queue lock of the bfqd they reference; the pointer is dereferenced -+ * under RCU, so the storage for bfqd is assured to be safe as long -+ * as the RCU read side critical section does not end. After the -+ * bfqd->queue->queue_lock is taken the pointer is rechecked, to be -+ * sure that no other writer accessed it. If we raced with a writer, -+ * the function returns NULL, with the queue unlocked, otherwise it -+ * returns the dereferenced pointer, with the queue locked. -+ */ -+static inline struct bfq_data *bfq_get_bfqd_locked(void **ptr, -+ unsigned long *flags) -+{ -+ struct bfq_data *bfqd; -+ -+ rcu_read_lock(); -+ bfqd = rcu_dereference(*(struct bfq_data **)ptr); -+ -+ if (bfqd != NULL) { -+ spin_lock_irqsave(bfqd->queue->queue_lock, *flags); -+ if (*ptr == bfqd) -+ goto out; -+ spin_unlock_irqrestore(bfqd->queue->queue_lock, *flags); -+ } -+ -+ bfqd = NULL; -+out: -+ rcu_read_unlock(); -+ return bfqd; -+} -+ -+static inline void bfq_put_bfqd_unlock(struct bfq_data *bfqd, -+ unsigned long *flags) -+{ -+ spin_unlock_irqrestore(bfqd->queue->queue_lock, *flags); -+} -+ -+static void bfq_changed_ioprio(struct bfq_io_cq *bic); -+static void bfq_put_queue(struct bfq_queue *bfqq); -+static void bfq_dispatch_insert(struct request_queue *q, struct request *rq); -+static struct bfq_queue *bfq_get_queue(struct bfq_data *bfqd, -+ struct bfq_group *bfqg, int is_sync, -+ struct bfq_io_cq *bic, gfp_t gfp_mask); -+static void bfq_end_wr_async_queues(struct bfq_data *bfqd, -+ struct bfq_group *bfqg); -+static void bfq_put_async_queues(struct bfq_data *bfqd, struct bfq_group *bfqg); -+static void bfq_exit_bfqq(struct bfq_data *bfqd, struct bfq_queue *bfqq); -+ -+#endif /* _BFQ_H */ -diff -Nur linux-4.1.13.orig/block/bfq-ioc.c linux-4.1.13/block/bfq-ioc.c ---- linux-4.1.13.orig/block/bfq-ioc.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/block/bfq-ioc.c 2015-11-30 17:56:13.536140654 +0100 -@@ -0,0 +1,36 @@ -+/* -+ * BFQ: I/O context handling. -+ * -+ * Based on ideas and code from CFQ: -+ * Copyright (C) 2003 Jens Axboe -+ * -+ * Copyright (C) 2008 Fabio Checconi -+ * Paolo Valente -+ * -+ * Copyright (C) 2010 Paolo Valente -+ */ -+ -+/** -+ * icq_to_bic - convert iocontext queue structure to bfq_io_cq. -+ * @icq: the iocontext queue. -+ */ -+static inline struct bfq_io_cq *icq_to_bic(struct io_cq *icq) -+{ -+ /* bic->icq is the first member, %NULL will convert to %NULL */ -+ return container_of(icq, struct bfq_io_cq, icq); -+} -+ -+/** -+ * bfq_bic_lookup - search into @ioc a bic associated to @bfqd. -+ * @bfqd: the lookup key. -+ * @ioc: the io_context of the process doing I/O. -+ * -+ * Queue lock must be held. -+ */ -+static inline struct bfq_io_cq *bfq_bic_lookup(struct bfq_data *bfqd, -+ struct io_context *ioc) -+{ -+ if (ioc) -+ return icq_to_bic(ioc_lookup_icq(ioc, bfqd->queue)); -+ return NULL; -+} -diff -Nur linux-4.1.13.orig/block/bfq-iosched.c linux-4.1.13/block/bfq-iosched.c ---- linux-4.1.13.orig/block/bfq-iosched.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/block/bfq-iosched.c 2015-11-30 17:56:13.536140654 +0100 -@@ -0,0 +1,4223 @@ -+/* -+ * Budget Fair Queueing (BFQ) disk scheduler. -+ * -+ * Based on ideas and code from CFQ: -+ * Copyright (C) 2003 Jens Axboe -+ * -+ * Copyright (C) 2008 Fabio Checconi -+ * Paolo Valente -+ * -+ * Copyright (C) 2010 Paolo Valente -+ * -+ * Licensed under the GPL-2 as detailed in the accompanying COPYING.BFQ -+ * file. -+ * -+ * BFQ is a proportional-share storage-I/O scheduling algorithm based on -+ * the slice-by-slice service scheme of CFQ. But BFQ assigns budgets, -+ * measured in number of sectors, to processes instead of time slices. The -+ * device is not granted to the in-service process for a given time slice, -+ * but until it has exhausted its assigned budget. This change from the time -+ * to the service domain allows BFQ to distribute the device throughput -+ * among processes as desired, without any distortion due to ZBR, workload -+ * fluctuations or other factors. BFQ uses an ad hoc internal scheduler, -+ * called B-WF2Q+, to schedule processes according to their budgets. More -+ * precisely, BFQ schedules queues associated to processes. Thanks to the -+ * accurate policy of B-WF2Q+, BFQ can afford to assign high budgets to -+ * I/O-bound processes issuing sequential requests (to boost the -+ * throughput), and yet guarantee a low latency to interactive and soft -+ * real-time applications. -+ * -+ * BFQ is described in [1], where also a reference to the initial, more -+ * theoretical paper on BFQ can be found. The interested reader can find -+ * in the latter paper full details on the main algorithm, as well as -+ * formulas of the guarantees and formal proofs of all the properties. -+ * With respect to the version of BFQ presented in these papers, this -+ * implementation adds a few more heuristics, such as the one that -+ * guarantees a low latency to soft real-time applications, and a -+ * hierarchical extension based on H-WF2Q+. -+ * -+ * B-WF2Q+ is based on WF2Q+, that is described in [2], together with -+ * H-WF2Q+, while the augmented tree used to implement B-WF2Q+ with O(log N) -+ * complexity derives from the one introduced with EEVDF in [3]. -+ * -+ * [1] P. Valente and M. Andreolini, ``Improving Application Responsiveness -+ * with the BFQ Disk I/O Scheduler'', -+ * Proceedings of the 5th Annual International Systems and Storage -+ * Conference (SYSTOR '12), June 2012. -+ * -+ * http://algogroup.unimo.it/people/paolo/disk_sched/bf1-v1-suite-results.pdf -+ * -+ * [2] Jon C.R. Bennett and H. Zhang, ``Hierarchical Packet Fair Queueing -+ * Algorithms,'' IEEE/ACM Transactions on Networking, 5(5):675-689, -+ * Oct 1997. -+ * -+ * http://www.cs.cmu.edu/~hzhang/papers/TON-97-Oct.ps.gz -+ * -+ * [3] I. Stoica and H. Abdel-Wahab, ``Earliest Eligible Virtual Deadline -+ * First: A Flexible and Accurate Mechanism for Proportional Share -+ * Resource Allocation,'' technical report. -+ * -+ * http://www.cs.berkeley.edu/~istoica/papers/eevdf-tr-95.pdf -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "bfq.h" -+#include "blk.h" -+ -+/* Max number of dispatches in one round of service. */ -+static const int bfq_quantum = 4; -+ -+/* Expiration time of sync (0) and async (1) requests, in jiffies. */ -+static const int bfq_fifo_expire[2] = { HZ / 4, HZ / 8 }; -+ -+/* Maximum backwards seek, in KiB. */ -+static const int bfq_back_max = 16 * 1024; -+ -+/* Penalty of a backwards seek, in number of sectors. */ -+static const int bfq_back_penalty = 2; -+ -+/* Idling period duration, in jiffies. */ -+static int bfq_slice_idle = HZ / 125; -+ -+/* Default maximum budget values, in sectors and number of requests. */ -+static const int bfq_default_max_budget = 16 * 1024; -+static const int bfq_max_budget_async_rq = 4; -+ -+/* -+ * Async to sync throughput distribution is controlled as follows: -+ * when an async request is served, the entity is charged the number -+ * of sectors of the request, multiplied by the factor below -+ */ -+static const int bfq_async_charge_factor = 10; -+ -+/* Default timeout values, in jiffies, approximating CFQ defaults. */ -+static const int bfq_timeout_sync = HZ / 8; -+static int bfq_timeout_async = HZ / 25; -+ -+struct kmem_cache *bfq_pool; -+ -+/* Below this threshold (in ms), we consider thinktime immediate. */ -+#define BFQ_MIN_TT 2 -+ -+/* hw_tag detection: parallel requests threshold and min samples needed. */ -+#define BFQ_HW_QUEUE_THRESHOLD 4 -+#define BFQ_HW_QUEUE_SAMPLES 32 -+ -+#define BFQQ_SEEK_THR (sector_t)(8 * 1024) -+#define BFQQ_SEEKY(bfqq) ((bfqq)->seek_mean > BFQQ_SEEK_THR) -+ -+/* Min samples used for peak rate estimation (for autotuning). */ -+#define BFQ_PEAK_RATE_SAMPLES 32 -+ -+/* Shift used for peak rate fixed precision calculations. */ -+#define BFQ_RATE_SHIFT 16 -+ -+/* -+ * By default, BFQ computes the duration of the weight raising for -+ * interactive applications automatically, using the following formula: -+ * duration = (R / r) * T, where r is the peak rate of the device, and -+ * R and T are two reference parameters. -+ * In particular, R is the peak rate of the reference device (see below), -+ * and T is a reference time: given the systems that are likely to be -+ * installed on the reference device according to its speed class, T is -+ * about the maximum time needed, under BFQ and while reading two files in -+ * parallel, to load typical large applications on these systems. -+ * In practice, the slower/faster the device at hand is, the more/less it -+ * takes to load applications with respect to the reference device. -+ * Accordingly, the longer/shorter BFQ grants weight raising to interactive -+ * applications. -+ * -+ * BFQ uses four different reference pairs (R, T), depending on: -+ * . whether the device is rotational or non-rotational; -+ * . whether the device is slow, such as old or portable HDDs, as well as -+ * SD cards, or fast, such as newer HDDs and SSDs. -+ * -+ * The device's speed class is dynamically (re)detected in -+ * bfq_update_peak_rate() every time the estimated peak rate is updated. -+ * -+ * In the following definitions, R_slow[0]/R_fast[0] and T_slow[0]/T_fast[0] -+ * are the reference values for a slow/fast rotational device, whereas -+ * R_slow[1]/R_fast[1] and T_slow[1]/T_fast[1] are the reference values for -+ * a slow/fast non-rotational device. Finally, device_speed_thresh are the -+ * thresholds used to switch between speed classes. -+ * Both the reference peak rates and the thresholds are measured in -+ * sectors/usec, left-shifted by BFQ_RATE_SHIFT. -+ */ -+static int R_slow[2] = {1536, 10752}; -+static int R_fast[2] = {17415, 34791}; -+/* -+ * To improve readability, a conversion function is used to initialize the -+ * following arrays, which entails that they can be initialized only in a -+ * function. -+ */ -+static int T_slow[2]; -+static int T_fast[2]; -+static int device_speed_thresh[2]; -+ -+#define BFQ_SERVICE_TREE_INIT ((struct bfq_service_tree) \ -+ { RB_ROOT, RB_ROOT, NULL, NULL, 0, 0 }) -+ -+#define RQ_BIC(rq) ((struct bfq_io_cq *) (rq)->elv.priv[0]) -+#define RQ_BFQQ(rq) ((rq)->elv.priv[1]) -+ -+static inline void bfq_schedule_dispatch(struct bfq_data *bfqd); -+ -+#include "bfq-ioc.c" -+#include "bfq-sched.c" -+#include "bfq-cgroup.c" -+ -+#define bfq_class_idle(bfqq) ((bfqq)->entity.ioprio_class ==\ -+ IOPRIO_CLASS_IDLE) -+#define bfq_class_rt(bfqq) ((bfqq)->entity.ioprio_class ==\ -+ IOPRIO_CLASS_RT) -+ -+#define bfq_sample_valid(samples) ((samples) > 80) -+ -+/* -+ * We regard a request as SYNC, if either it's a read or has the SYNC bit -+ * set (in which case it could also be a direct WRITE). -+ */ -+static inline int bfq_bio_sync(struct bio *bio) -+{ -+ if (bio_data_dir(bio) == READ || (bio->bi_rw & REQ_SYNC)) -+ return 1; -+ -+ return 0; -+} -+ -+/* -+ * Scheduler run of queue, if there are requests pending and no one in the -+ * driver that will restart queueing. -+ */ -+static inline void bfq_schedule_dispatch(struct bfq_data *bfqd) -+{ -+ if (bfqd->queued != 0) { -+ bfq_log(bfqd, "schedule dispatch"); -+ kblockd_schedule_work(&bfqd->unplug_work); -+ } -+} -+ -+/* -+ * Lifted from AS - choose which of rq1 and rq2 that is best served now. -+ * We choose the request that is closesr to the head right now. Distance -+ * behind the head is penalized and only allowed to a certain extent. -+ */ -+static struct request *bfq_choose_req(struct bfq_data *bfqd, -+ struct request *rq1, -+ struct request *rq2, -+ sector_t last) -+{ -+ sector_t s1, s2, d1 = 0, d2 = 0; -+ unsigned long back_max; -+#define BFQ_RQ1_WRAP 0x01 /* request 1 wraps */ -+#define BFQ_RQ2_WRAP 0x02 /* request 2 wraps */ -+ unsigned wrap = 0; /* bit mask: requests behind the disk head? */ -+ -+ if (rq1 == NULL || rq1 == rq2) -+ return rq2; -+ if (rq2 == NULL) -+ return rq1; -+ -+ if (rq_is_sync(rq1) && !rq_is_sync(rq2)) -+ return rq1; -+ else if (rq_is_sync(rq2) && !rq_is_sync(rq1)) -+ return rq2; -+ if ((rq1->cmd_flags & REQ_META) && !(rq2->cmd_flags & REQ_META)) -+ return rq1; -+ else if ((rq2->cmd_flags & REQ_META) && !(rq1->cmd_flags & REQ_META)) -+ return rq2; -+ -+ s1 = blk_rq_pos(rq1); -+ s2 = blk_rq_pos(rq2); -+ -+ /* -+ * By definition, 1KiB is 2 sectors. -+ */ -+ back_max = bfqd->bfq_back_max * 2; -+ -+ /* -+ * Strict one way elevator _except_ in the case where we allow -+ * short backward seeks which are biased as twice the cost of a -+ * similar forward seek. -+ */ -+ if (s1 >= last) -+ d1 = s1 - last; -+ else if (s1 + back_max >= last) -+ d1 = (last - s1) * bfqd->bfq_back_penalty; -+ else -+ wrap |= BFQ_RQ1_WRAP; -+ -+ if (s2 >= last) -+ d2 = s2 - last; -+ else if (s2 + back_max >= last) -+ d2 = (last - s2) * bfqd->bfq_back_penalty; -+ else -+ wrap |= BFQ_RQ2_WRAP; -+ -+ /* Found required data */ -+ -+ /* -+ * By doing switch() on the bit mask "wrap" we avoid having to -+ * check two variables for all permutations: --> faster! -+ */ -+ switch (wrap) { -+ case 0: /* common case for CFQ: rq1 and rq2 not wrapped */ -+ if (d1 < d2) -+ return rq1; -+ else if (d2 < d1) -+ return rq2; -+ else { -+ if (s1 >= s2) -+ return rq1; -+ else -+ return rq2; -+ } -+ -+ case BFQ_RQ2_WRAP: -+ return rq1; -+ case BFQ_RQ1_WRAP: -+ return rq2; -+ case (BFQ_RQ1_WRAP|BFQ_RQ2_WRAP): /* both rqs wrapped */ -+ default: -+ /* -+ * Since both rqs are wrapped, -+ * start with the one that's further behind head -+ * (--> only *one* back seek required), -+ * since back seek takes more time than forward. -+ */ -+ if (s1 <= s2) -+ return rq1; -+ else -+ return rq2; -+ } -+} -+ -+static struct bfq_queue * -+bfq_rq_pos_tree_lookup(struct bfq_data *bfqd, struct rb_root *root, -+ sector_t sector, struct rb_node **ret_parent, -+ struct rb_node ***rb_link) -+{ -+ struct rb_node **p, *parent; -+ struct bfq_queue *bfqq = NULL; -+ -+ parent = NULL; -+ p = &root->rb_node; -+ while (*p) { -+ struct rb_node **n; -+ -+ parent = *p; -+ bfqq = rb_entry(parent, struct bfq_queue, pos_node); -+ -+ /* -+ * Sort strictly based on sector. Smallest to the left, -+ * largest to the right. -+ */ -+ if (sector > blk_rq_pos(bfqq->next_rq)) -+ n = &(*p)->rb_right; -+ else if (sector < blk_rq_pos(bfqq->next_rq)) -+ n = &(*p)->rb_left; -+ else -+ break; -+ p = n; -+ bfqq = NULL; -+ } -+ -+ *ret_parent = parent; -+ if (rb_link) -+ *rb_link = p; -+ -+ bfq_log(bfqd, "rq_pos_tree_lookup %llu: returning %d", -+ (long long unsigned)sector, -+ bfqq != NULL ? bfqq->pid : 0); -+ -+ return bfqq; -+} -+ -+static void bfq_rq_pos_tree_add(struct bfq_data *bfqd, struct bfq_queue *bfqq) -+{ -+ struct rb_node **p, *parent; -+ struct bfq_queue *__bfqq; -+ -+ if (bfqq->pos_root != NULL) { -+ rb_erase(&bfqq->pos_node, bfqq->pos_root); -+ bfqq->pos_root = NULL; -+ } -+ -+ if (bfq_class_idle(bfqq)) -+ return; -+ if (!bfqq->next_rq) -+ return; -+ -+ bfqq->pos_root = &bfqd->rq_pos_tree; -+ __bfqq = bfq_rq_pos_tree_lookup(bfqd, bfqq->pos_root, -+ blk_rq_pos(bfqq->next_rq), &parent, &p); -+ if (__bfqq == NULL) { -+ rb_link_node(&bfqq->pos_node, parent, p); -+ rb_insert_color(&bfqq->pos_node, bfqq->pos_root); -+ } else -+ bfqq->pos_root = NULL; -+} -+ -+/* -+ * Tell whether there are active queues or groups with differentiated weights. -+ */ -+static inline bool bfq_differentiated_weights(struct bfq_data *bfqd) -+{ -+ BUG_ON(!bfqd->hw_tag); -+ /* -+ * For weights to differ, at least one of the trees must contain -+ * at least two nodes. -+ */ -+ return (!RB_EMPTY_ROOT(&bfqd->queue_weights_tree) && -+ (bfqd->queue_weights_tree.rb_node->rb_left || -+ bfqd->queue_weights_tree.rb_node->rb_right) -+#ifdef CONFIG_CGROUP_BFQIO -+ ) || -+ (!RB_EMPTY_ROOT(&bfqd->group_weights_tree) && -+ (bfqd->group_weights_tree.rb_node->rb_left || -+ bfqd->group_weights_tree.rb_node->rb_right) -+#endif -+ ); -+} -+ -+/* -+ * If the weight-counter tree passed as input contains no counter for -+ * the weight of the input entity, then add that counter; otherwise just -+ * increment the existing counter. -+ * -+ * Note that weight-counter trees contain few nodes in mostly symmetric -+ * scenarios. For example, if all queues have the same weight, then the -+ * weight-counter tree for the queues may contain at most one node. -+ * This holds even if low_latency is on, because weight-raised queues -+ * are not inserted in the tree. -+ * In most scenarios, the rate at which nodes are created/destroyed -+ * should be low too. -+ */ -+static void bfq_weights_tree_add(struct bfq_data *bfqd, -+ struct bfq_entity *entity, -+ struct rb_root *root) -+{ -+ struct rb_node **new = &(root->rb_node), *parent = NULL; -+ -+ /* -+ * Do not insert if: -+ * - the device does not support queueing; -+ * - the entity is already associated with a counter, which happens if: -+ * 1) the entity is associated with a queue, 2) a request arrival -+ * has caused the queue to become both non-weight-raised, and hence -+ * change its weight, and backlogged; in this respect, each -+ * of the two events causes an invocation of this function, -+ * 3) this is the invocation of this function caused by the second -+ * event. This second invocation is actually useless, and we handle -+ * this fact by exiting immediately. More efficient or clearer -+ * solutions might possibly be adopted. -+ */ -+ if (!bfqd->hw_tag || entity->weight_counter) -+ return; -+ -+ while (*new) { -+ struct bfq_weight_counter *__counter = container_of(*new, -+ struct bfq_weight_counter, -+ weights_node); -+ parent = *new; -+ -+ if (entity->weight == __counter->weight) { -+ entity->weight_counter = __counter; -+ goto inc_counter; -+ } -+ if (entity->weight < __counter->weight) -+ new = &((*new)->rb_left); -+ else -+ new = &((*new)->rb_right); -+ } -+ -+ entity->weight_counter = kzalloc(sizeof(struct bfq_weight_counter), -+ GFP_ATOMIC); -+ entity->weight_counter->weight = entity->weight; -+ rb_link_node(&entity->weight_counter->weights_node, parent, new); -+ rb_insert_color(&entity->weight_counter->weights_node, root); -+ -+inc_counter: -+ entity->weight_counter->num_active++; -+} -+ -+/* -+ * Decrement the weight counter associated with the entity, and, if the -+ * counter reaches 0, remove the counter from the tree. -+ * See the comments to the function bfq_weights_tree_add() for considerations -+ * about overhead. -+ */ -+static void bfq_weights_tree_remove(struct bfq_data *bfqd, -+ struct bfq_entity *entity, -+ struct rb_root *root) -+{ -+ /* -+ * Check whether the entity is actually associated with a counter. -+ * In fact, the device may not be considered NCQ-capable for a while, -+ * which implies that no insertion in the weight trees is performed, -+ * after which the device may start to be deemed NCQ-capable, and hence -+ * this function may start to be invoked. This may cause the function -+ * to be invoked for entities that are not associated with any counter. -+ */ -+ if (!entity->weight_counter) -+ return; -+ -+ BUG_ON(RB_EMPTY_ROOT(root)); -+ BUG_ON(entity->weight_counter->weight != entity->weight); -+ -+ BUG_ON(!entity->weight_counter->num_active); -+ entity->weight_counter->num_active--; -+ if (entity->weight_counter->num_active > 0) -+ goto reset_entity_pointer; -+ -+ rb_erase(&entity->weight_counter->weights_node, root); -+ kfree(entity->weight_counter); -+ -+reset_entity_pointer: -+ entity->weight_counter = NULL; -+} -+ -+static struct request *bfq_find_next_rq(struct bfq_data *bfqd, -+ struct bfq_queue *bfqq, -+ struct request *last) -+{ -+ struct rb_node *rbnext = rb_next(&last->rb_node); -+ struct rb_node *rbprev = rb_prev(&last->rb_node); -+ struct request *next = NULL, *prev = NULL; -+ -+ BUG_ON(RB_EMPTY_NODE(&last->rb_node)); -+ -+ if (rbprev != NULL) -+ prev = rb_entry_rq(rbprev); -+ -+ if (rbnext != NULL) -+ next = rb_entry_rq(rbnext); -+ else { -+ rbnext = rb_first(&bfqq->sort_list); -+ if (rbnext && rbnext != &last->rb_node) -+ next = rb_entry_rq(rbnext); -+ } -+ -+ return bfq_choose_req(bfqd, next, prev, blk_rq_pos(last)); -+} -+ -+/* see the definition of bfq_async_charge_factor for details */ -+static inline unsigned long bfq_serv_to_charge(struct request *rq, -+ struct bfq_queue *bfqq) -+{ -+ return blk_rq_sectors(rq) * -+ (1 + ((!bfq_bfqq_sync(bfqq)) * (bfqq->wr_coeff == 1) * -+ bfq_async_charge_factor)); -+} -+ -+/** -+ * bfq_updated_next_req - update the queue after a new next_rq selection. -+ * @bfqd: the device data the queue belongs to. -+ * @bfqq: the queue to update. -+ * -+ * If the first request of a queue changes we make sure that the queue -+ * has enough budget to serve at least its first request (if the -+ * request has grown). We do this because if the queue has not enough -+ * budget for its first request, it has to go through two dispatch -+ * rounds to actually get it dispatched. -+ */ -+static void bfq_updated_next_req(struct bfq_data *bfqd, -+ struct bfq_queue *bfqq) -+{ -+ struct bfq_entity *entity = &bfqq->entity; -+ struct bfq_service_tree *st = bfq_entity_service_tree(entity); -+ struct request *next_rq = bfqq->next_rq; -+ unsigned long new_budget; -+ -+ if (next_rq == NULL) -+ return; -+ -+ if (bfqq == bfqd->in_service_queue) -+ /* -+ * In order not to break guarantees, budgets cannot be -+ * changed after an entity has been selected. -+ */ -+ return; -+ -+ BUG_ON(entity->tree != &st->active); -+ BUG_ON(entity == entity->sched_data->in_service_entity); -+ -+ new_budget = max_t(unsigned long, bfqq->max_budget, -+ bfq_serv_to_charge(next_rq, bfqq)); -+ if (entity->budget != new_budget) { -+ entity->budget = new_budget; -+ bfq_log_bfqq(bfqd, bfqq, "updated next rq: new budget %lu", -+ new_budget); -+ bfq_activate_bfqq(bfqd, bfqq); -+ } -+} -+ -+static inline unsigned int bfq_wr_duration(struct bfq_data *bfqd) -+{ -+ u64 dur; -+ -+ if (bfqd->bfq_wr_max_time > 0) -+ return bfqd->bfq_wr_max_time; -+ -+ dur = bfqd->RT_prod; -+ do_div(dur, bfqd->peak_rate); -+ -+ return dur; -+} -+ -+static inline unsigned -+bfq_bfqq_cooperations(struct bfq_queue *bfqq) -+{ -+ return bfqq->bic ? bfqq->bic->cooperations : 0; -+} -+ -+static inline void -+bfq_bfqq_resume_state(struct bfq_queue *bfqq, struct bfq_io_cq *bic) -+{ -+ if (bic->saved_idle_window) -+ bfq_mark_bfqq_idle_window(bfqq); -+ else -+ bfq_clear_bfqq_idle_window(bfqq); -+ if (bic->saved_IO_bound) -+ bfq_mark_bfqq_IO_bound(bfqq); -+ else -+ bfq_clear_bfqq_IO_bound(bfqq); -+ /* Assuming that the flag in_large_burst is already correctly set */ -+ if (bic->wr_time_left && bfqq->bfqd->low_latency && -+ !bfq_bfqq_in_large_burst(bfqq) && -+ bic->cooperations < bfqq->bfqd->bfq_coop_thresh) { -+ /* -+ * Start a weight raising period with the duration given by -+ * the raising_time_left snapshot. -+ */ -+ if (bfq_bfqq_busy(bfqq)) -+ bfqq->bfqd->wr_busy_queues++; -+ bfqq->wr_coeff = bfqq->bfqd->bfq_wr_coeff; -+ bfqq->wr_cur_max_time = bic->wr_time_left; -+ bfqq->last_wr_start_finish = jiffies; -+ bfqq->entity.ioprio_changed = 1; -+ } -+ /* -+ * Clear wr_time_left to prevent bfq_bfqq_save_state() from -+ * getting confused about the queue's need of a weight-raising -+ * period. -+ */ -+ bic->wr_time_left = 0; -+} -+ -+/* Must be called with the queue_lock held. */ -+static int bfqq_process_refs(struct bfq_queue *bfqq) -+{ -+ int process_refs, io_refs; -+ -+ io_refs = bfqq->allocated[READ] + bfqq->allocated[WRITE]; -+ process_refs = atomic_read(&bfqq->ref) - io_refs - bfqq->entity.on_st; -+ BUG_ON(process_refs < 0); -+ return process_refs; -+} -+ -+/* Empty burst list and add just bfqq (see comments to bfq_handle_burst) */ -+static inline void bfq_reset_burst_list(struct bfq_data *bfqd, -+ struct bfq_queue *bfqq) -+{ -+ struct bfq_queue *item; -+ struct hlist_node *n; -+ -+ hlist_for_each_entry_safe(item, n, &bfqd->burst_list, burst_list_node) -+ hlist_del_init(&item->burst_list_node); -+ hlist_add_head(&bfqq->burst_list_node, &bfqd->burst_list); -+ bfqd->burst_size = 1; -+} -+ -+/* Add bfqq to the list of queues in current burst (see bfq_handle_burst) */ -+static void bfq_add_to_burst(struct bfq_data *bfqd, struct bfq_queue *bfqq) -+{ -+ /* Increment burst size to take into account also bfqq */ -+ bfqd->burst_size++; -+ -+ if (bfqd->burst_size == bfqd->bfq_large_burst_thresh) { -+ struct bfq_queue *pos, *bfqq_item; -+ struct hlist_node *n; -+ -+ /* -+ * Enough queues have been activated shortly after each -+ * other to consider this burst as large. -+ */ -+ bfqd->large_burst = true; -+ -+ /* -+ * We can now mark all queues in the burst list as -+ * belonging to a large burst. -+ */ -+ hlist_for_each_entry(bfqq_item, &bfqd->burst_list, -+ burst_list_node) -+ bfq_mark_bfqq_in_large_burst(bfqq_item); -+ bfq_mark_bfqq_in_large_burst(bfqq); -+ -+ /* -+ * From now on, and until the current burst finishes, any -+ * new queue being activated shortly after the last queue -+ * was inserted in the burst can be immediately marked as -+ * belonging to a large burst. So the burst list is not -+ * needed any more. Remove it. -+ */ -+ hlist_for_each_entry_safe(pos, n, &bfqd->burst_list, -+ burst_list_node) -+ hlist_del_init(&pos->burst_list_node); -+ } else /* burst not yet large: add bfqq to the burst list */ -+ hlist_add_head(&bfqq->burst_list_node, &bfqd->burst_list); -+} -+ -+/* -+ * If many queues happen to become active shortly after each other, then, -+ * to help the processes associated to these queues get their job done as -+ * soon as possible, it is usually better to not grant either weight-raising -+ * or device idling to these queues. In this comment we describe, firstly, -+ * the reasons why this fact holds, and, secondly, the next function, which -+ * implements the main steps needed to properly mark these queues so that -+ * they can then be treated in a different way. -+ * -+ * As for the terminology, we say that a queue becomes active, i.e., -+ * switches from idle to backlogged, either when it is created (as a -+ * consequence of the arrival of an I/O request), or, if already existing, -+ * when a new request for the queue arrives while the queue is idle. -+ * Bursts of activations, i.e., activations of different queues occurring -+ * shortly after each other, are typically caused by services or applications -+ * that spawn or reactivate many parallel threads/processes. Examples are -+ * systemd during boot or git grep. -+ * -+ * These services or applications benefit mostly from a high throughput: -+ * the quicker the requests of the activated queues are cumulatively served, -+ * the sooner the target job of these queues gets completed. As a consequence, -+ * weight-raising any of these queues, which also implies idling the device -+ * for it, is almost always counterproductive: in most cases it just lowers -+ * throughput. -+ * -+ * On the other hand, a burst of activations may be also caused by the start -+ * of an application that does not consist in a lot of parallel I/O-bound -+ * threads. In fact, with a complex application, the burst may be just a -+ * consequence of the fact that several processes need to be executed to -+ * start-up the application. To start an application as quickly as possible, -+ * the best thing to do is to privilege the I/O related to the application -+ * with respect to all other I/O. Therefore, the best strategy to start as -+ * quickly as possible an application that causes a burst of activations is -+ * to weight-raise all the queues activated during the burst. This is the -+ * exact opposite of the best strategy for the other type of bursts. -+ * -+ * In the end, to take the best action for each of the two cases, the two -+ * types of bursts need to be distinguished. Fortunately, this seems -+ * relatively easy to do, by looking at the sizes of the bursts. In -+ * particular, we found a threshold such that bursts with a larger size -+ * than that threshold are apparently caused only by services or commands -+ * such as systemd or git grep. For brevity, hereafter we call just 'large' -+ * these bursts. BFQ *does not* weight-raise queues whose activations occur -+ * in a large burst. In addition, for each of these queues BFQ performs or -+ * does not perform idling depending on which choice boosts the throughput -+ * most. The exact choice depends on the device and request pattern at -+ * hand. -+ * -+ * Turning back to the next function, it implements all the steps needed -+ * to detect the occurrence of a large burst and to properly mark all the -+ * queues belonging to it (so that they can then be treated in a different -+ * way). This goal is achieved by maintaining a special "burst list" that -+ * holds, temporarily, the queues that belong to the burst in progress. The -+ * list is then used to mark these queues as belonging to a large burst if -+ * the burst does become large. The main steps are the following. -+ * -+ * . when the very first queue is activated, the queue is inserted into the -+ * list (as it could be the first queue in a possible burst) -+ * -+ * . if the current burst has not yet become large, and a queue Q that does -+ * not yet belong to the burst is activated shortly after the last time -+ * at which a new queue entered the burst list, then the function appends -+ * Q to the burst list -+ * -+ * . if, as a consequence of the previous step, the burst size reaches -+ * the large-burst threshold, then -+ * -+ * . all the queues in the burst list are marked as belonging to a -+ * large burst -+ * -+ * . the burst list is deleted; in fact, the burst list already served -+ * its purpose (keeping temporarily track of the queues in a burst, -+ * so as to be able to mark them as belonging to a large burst in the -+ * previous sub-step), and now is not needed any more -+ * -+ * . the device enters a large-burst mode -+ * -+ * . if a queue Q that does not belong to the burst is activated while -+ * the device is in large-burst mode and shortly after the last time -+ * at which a queue either entered the burst list or was marked as -+ * belonging to the current large burst, then Q is immediately marked -+ * as belonging to a large burst. -+ * -+ * . if a queue Q that does not belong to the burst is activated a while -+ * later, i.e., not shortly after, than the last time at which a queue -+ * either entered the burst list or was marked as belonging to the -+ * current large burst, then the current burst is deemed as finished and: -+ * -+ * . the large-burst mode is reset if set -+ * -+ * . the burst list is emptied -+ * -+ * . Q is inserted in the burst list, as Q may be the first queue -+ * in a possible new burst (then the burst list contains just Q -+ * after this step). -+ */ -+static void bfq_handle_burst(struct bfq_data *bfqd, struct bfq_queue *bfqq, -+ bool idle_for_long_time) -+{ -+ /* -+ * If bfqq happened to be activated in a burst, but has been idle -+ * for at least as long as an interactive queue, then we assume -+ * that, in the overall I/O initiated in the burst, the I/O -+ * associated to bfqq is finished. So bfqq does not need to be -+ * treated as a queue belonging to a burst anymore. Accordingly, -+ * we reset bfqq's in_large_burst flag if set, and remove bfqq -+ * from the burst list if it's there. We do not decrement instead -+ * burst_size, because the fact that bfqq does not need to belong -+ * to the burst list any more does not invalidate the fact that -+ * bfqq may have been activated during the current burst. -+ */ -+ if (idle_for_long_time) { -+ hlist_del_init(&bfqq->burst_list_node); -+ bfq_clear_bfqq_in_large_burst(bfqq); -+ } -+ -+ /* -+ * If bfqq is already in the burst list or is part of a large -+ * burst, then there is nothing else to do. -+ */ -+ if (!hlist_unhashed(&bfqq->burst_list_node) || -+ bfq_bfqq_in_large_burst(bfqq)) -+ return; -+ -+ /* -+ * If bfqq's activation happens late enough, then the current -+ * burst is finished, and related data structures must be reset. -+ * -+ * In this respect, consider the special case where bfqq is the very -+ * first queue being activated. In this case, last_ins_in_burst is -+ * not yet significant when we get here. But it is easy to verify -+ * that, whether or not the following condition is true, bfqq will -+ * end up being inserted into the burst list. In particular the -+ * list will happen to contain only bfqq. And this is exactly what -+ * has to happen, as bfqq may be the first queue in a possible -+ * burst. -+ */ -+ if (time_is_before_jiffies(bfqd->last_ins_in_burst + -+ bfqd->bfq_burst_interval)) { -+ bfqd->large_burst = false; -+ bfq_reset_burst_list(bfqd, bfqq); -+ return; -+ } -+ -+ /* -+ * If we get here, then bfqq is being activated shortly after the -+ * last queue. So, if the current burst is also large, we can mark -+ * bfqq as belonging to this large burst immediately. -+ */ -+ if (bfqd->large_burst) { -+ bfq_mark_bfqq_in_large_burst(bfqq); -+ return; -+ } -+ -+ /* -+ * If we get here, then a large-burst state has not yet been -+ * reached, but bfqq is being activated shortly after the last -+ * queue. Then we add bfqq to the burst. -+ */ -+ bfq_add_to_burst(bfqd, bfqq); -+} -+ -+static void bfq_add_request(struct request *rq) -+{ -+ struct bfq_queue *bfqq = RQ_BFQQ(rq); -+ struct bfq_entity *entity = &bfqq->entity; -+ struct bfq_data *bfqd = bfqq->bfqd; -+ struct request *next_rq, *prev; -+ unsigned long old_wr_coeff = bfqq->wr_coeff; -+ bool interactive = false; -+ -+ bfq_log_bfqq(bfqd, bfqq, "add_request %d", rq_is_sync(rq)); -+ bfqq->queued[rq_is_sync(rq)]++; -+ bfqd->queued++; -+ -+ elv_rb_add(&bfqq->sort_list, rq); -+ -+ /* -+ * Check if this request is a better next-serve candidate. -+ */ -+ prev = bfqq->next_rq; -+ next_rq = bfq_choose_req(bfqd, bfqq->next_rq, rq, bfqd->last_position); -+ BUG_ON(next_rq == NULL); -+ bfqq->next_rq = next_rq; -+ -+ /* -+ * Adjust priority tree position, if next_rq changes. -+ */ -+ if (prev != bfqq->next_rq) -+ bfq_rq_pos_tree_add(bfqd, bfqq); -+ -+ if (!bfq_bfqq_busy(bfqq)) { -+ bool soft_rt, coop_or_in_burst, -+ idle_for_long_time = time_is_before_jiffies( -+ bfqq->budget_timeout + -+ bfqd->bfq_wr_min_idle_time); -+ -+ if (bfq_bfqq_sync(bfqq)) { -+ bool already_in_burst = -+ !hlist_unhashed(&bfqq->burst_list_node) || -+ bfq_bfqq_in_large_burst(bfqq); -+ bfq_handle_burst(bfqd, bfqq, idle_for_long_time); -+ /* -+ * If bfqq was not already in the current burst, -+ * then, at this point, bfqq either has been -+ * added to the current burst or has caused the -+ * current burst to terminate. In particular, in -+ * the second case, bfqq has become the first -+ * queue in a possible new burst. -+ * In both cases last_ins_in_burst needs to be -+ * moved forward. -+ */ -+ if (!already_in_burst) -+ bfqd->last_ins_in_burst = jiffies; -+ } -+ -+ coop_or_in_burst = bfq_bfqq_in_large_burst(bfqq) || -+ bfq_bfqq_cooperations(bfqq) >= bfqd->bfq_coop_thresh; -+ soft_rt = bfqd->bfq_wr_max_softrt_rate > 0 && -+ !coop_or_in_burst && -+ time_is_before_jiffies(bfqq->soft_rt_next_start); -+ interactive = !coop_or_in_burst && idle_for_long_time; -+ entity->budget = max_t(unsigned long, bfqq->max_budget, -+ bfq_serv_to_charge(next_rq, bfqq)); -+ -+ if (!bfq_bfqq_IO_bound(bfqq)) { -+ if (time_before(jiffies, -+ RQ_BIC(rq)->ttime.last_end_request + -+ bfqd->bfq_slice_idle)) { -+ bfqq->requests_within_timer++; -+ if (bfqq->requests_within_timer >= -+ bfqd->bfq_requests_within_timer) -+ bfq_mark_bfqq_IO_bound(bfqq); -+ } else -+ bfqq->requests_within_timer = 0; -+ } -+ -+ if (!bfqd->low_latency) -+ goto add_bfqq_busy; -+ -+ if (bfq_bfqq_just_split(bfqq)) -+ goto set_ioprio_changed; -+ -+ /* -+ * If the queue: -+ * - is not being boosted, -+ * - has been idle for enough time, -+ * - is not a sync queue or is linked to a bfq_io_cq (it is -+ * shared "for its nature" or it is not shared and its -+ * requests have not been redirected to a shared queue) -+ * start a weight-raising period. -+ */ -+ if (old_wr_coeff == 1 && (interactive || soft_rt) && -+ (!bfq_bfqq_sync(bfqq) || bfqq->bic != NULL)) { -+ bfqq->wr_coeff = bfqd->bfq_wr_coeff; -+ if (interactive) -+ bfqq->wr_cur_max_time = bfq_wr_duration(bfqd); -+ else -+ bfqq->wr_cur_max_time = -+ bfqd->bfq_wr_rt_max_time; -+ bfq_log_bfqq(bfqd, bfqq, -+ "wrais starting at %lu, rais_max_time %u", -+ jiffies, -+ jiffies_to_msecs(bfqq->wr_cur_max_time)); -+ } else if (old_wr_coeff > 1) { -+ if (interactive) -+ bfqq->wr_cur_max_time = bfq_wr_duration(bfqd); -+ else if (coop_or_in_burst || -+ (bfqq->wr_cur_max_time == -+ bfqd->bfq_wr_rt_max_time && -+ !soft_rt)) { -+ bfqq->wr_coeff = 1; -+ bfq_log_bfqq(bfqd, bfqq, -+ "wrais ending at %lu, rais_max_time %u", -+ jiffies, -+ jiffies_to_msecs(bfqq-> -+ wr_cur_max_time)); -+ } else if (time_before( -+ bfqq->last_wr_start_finish + -+ bfqq->wr_cur_max_time, -+ jiffies + -+ bfqd->bfq_wr_rt_max_time) && -+ soft_rt) { -+ /* -+ * -+ * The remaining weight-raising time is lower -+ * than bfqd->bfq_wr_rt_max_time, which means -+ * that the application is enjoying weight -+ * raising either because deemed soft-rt in -+ * the near past, or because deemed interactive -+ * a long ago. -+ * In both cases, resetting now the current -+ * remaining weight-raising time for the -+ * application to the weight-raising duration -+ * for soft rt applications would not cause any -+ * latency increase for the application (as the -+ * new duration would be higher than the -+ * remaining time). -+ * -+ * In addition, the application is now meeting -+ * the requirements for being deemed soft rt. -+ * In the end we can correctly and safely -+ * (re)charge the weight-raising duration for -+ * the application with the weight-raising -+ * duration for soft rt applications. -+ * -+ * In particular, doing this recharge now, i.e., -+ * before the weight-raising period for the -+ * application finishes, reduces the probability -+ * of the following negative scenario: -+ * 1) the weight of a soft rt application is -+ * raised at startup (as for any newly -+ * created application), -+ * 2) since the application is not interactive, -+ * at a certain time weight-raising is -+ * stopped for the application, -+ * 3) at that time the application happens to -+ * still have pending requests, and hence -+ * is destined to not have a chance to be -+ * deemed soft rt before these requests are -+ * completed (see the comments to the -+ * function bfq_bfqq_softrt_next_start() -+ * for details on soft rt detection), -+ * 4) these pending requests experience a high -+ * latency because the application is not -+ * weight-raised while they are pending. -+ */ -+ bfqq->last_wr_start_finish = jiffies; -+ bfqq->wr_cur_max_time = -+ bfqd->bfq_wr_rt_max_time; -+ } -+ } -+set_ioprio_changed: -+ if (old_wr_coeff != bfqq->wr_coeff) -+ entity->ioprio_changed = 1; -+add_bfqq_busy: -+ bfqq->last_idle_bklogged = jiffies; -+ bfqq->service_from_backlogged = 0; -+ bfq_clear_bfqq_softrt_update(bfqq); -+ bfq_add_bfqq_busy(bfqd, bfqq); -+ } else { -+ if (bfqd->low_latency && old_wr_coeff == 1 && !rq_is_sync(rq) && -+ time_is_before_jiffies( -+ bfqq->last_wr_start_finish + -+ bfqd->bfq_wr_min_inter_arr_async)) { -+ bfqq->wr_coeff = bfqd->bfq_wr_coeff; -+ bfqq->wr_cur_max_time = bfq_wr_duration(bfqd); -+ -+ bfqd->wr_busy_queues++; -+ entity->ioprio_changed = 1; -+ bfq_log_bfqq(bfqd, bfqq, -+ "non-idle wrais starting at %lu, rais_max_time %u", -+ jiffies, -+ jiffies_to_msecs(bfqq->wr_cur_max_time)); -+ } -+ if (prev != bfqq->next_rq) -+ bfq_updated_next_req(bfqd, bfqq); -+ } -+ -+ if (bfqd->low_latency && -+ (old_wr_coeff == 1 || bfqq->wr_coeff == 1 || interactive)) -+ bfqq->last_wr_start_finish = jiffies; -+} -+ -+static struct request *bfq_find_rq_fmerge(struct bfq_data *bfqd, -+ struct bio *bio) -+{ -+ struct task_struct *tsk = current; -+ struct bfq_io_cq *bic; -+ struct bfq_queue *bfqq; -+ -+ bic = bfq_bic_lookup(bfqd, tsk->io_context); -+ if (bic == NULL) -+ return NULL; -+ -+ bfqq = bic_to_bfqq(bic, bfq_bio_sync(bio)); -+ if (bfqq != NULL) -+ return elv_rb_find(&bfqq->sort_list, bio_end_sector(bio)); -+ -+ return NULL; -+} -+ -+static void bfq_activate_request(struct request_queue *q, struct request *rq) -+{ -+ struct bfq_data *bfqd = q->elevator->elevator_data; -+ -+ bfqd->rq_in_driver++; -+ bfqd->last_position = blk_rq_pos(rq) + blk_rq_sectors(rq); -+ bfq_log(bfqd, "activate_request: new bfqd->last_position %llu", -+ (long long unsigned)bfqd->last_position); -+} -+ -+static inline void bfq_deactivate_request(struct request_queue *q, -+ struct request *rq) -+{ -+ struct bfq_data *bfqd = q->elevator->elevator_data; -+ -+ BUG_ON(bfqd->rq_in_driver == 0); -+ bfqd->rq_in_driver--; -+} -+ -+static void bfq_remove_request(struct request *rq) -+{ -+ struct bfq_queue *bfqq = RQ_BFQQ(rq); -+ struct bfq_data *bfqd = bfqq->bfqd; -+ const int sync = rq_is_sync(rq); -+ -+ if (bfqq->next_rq == rq) { -+ bfqq->next_rq = bfq_find_next_rq(bfqd, bfqq, rq); -+ bfq_updated_next_req(bfqd, bfqq); -+ } -+ -+ list_del_init(&rq->queuelist); -+ BUG_ON(bfqq->queued[sync] == 0); -+ bfqq->queued[sync]--; -+ bfqd->queued--; -+ elv_rb_del(&bfqq->sort_list, rq); -+ -+ if (RB_EMPTY_ROOT(&bfqq->sort_list)) { -+ if (bfq_bfqq_busy(bfqq) && bfqq != bfqd->in_service_queue) -+ bfq_del_bfqq_busy(bfqd, bfqq, 1); -+ /* -+ * Remove queue from request-position tree as it is empty. -+ */ -+ if (bfqq->pos_root != NULL) { -+ rb_erase(&bfqq->pos_node, bfqq->pos_root); -+ bfqq->pos_root = NULL; -+ } -+ } -+ -+ if (rq->cmd_flags & REQ_META) { -+ BUG_ON(bfqq->meta_pending == 0); -+ bfqq->meta_pending--; -+ } -+} -+ -+static int bfq_merge(struct request_queue *q, struct request **req, -+ struct bio *bio) -+{ -+ struct bfq_data *bfqd = q->elevator->elevator_data; -+ struct request *__rq; -+ -+ __rq = bfq_find_rq_fmerge(bfqd, bio); -+ if (__rq != NULL && elv_rq_merge_ok(__rq, bio)) { -+ *req = __rq; -+ return ELEVATOR_FRONT_MERGE; -+ } -+ -+ return ELEVATOR_NO_MERGE; -+} -+ -+static void bfq_merged_request(struct request_queue *q, struct request *req, -+ int type) -+{ -+ if (type == ELEVATOR_FRONT_MERGE && -+ rb_prev(&req->rb_node) && -+ blk_rq_pos(req) < -+ blk_rq_pos(container_of(rb_prev(&req->rb_node), -+ struct request, rb_node))) { -+ struct bfq_queue *bfqq = RQ_BFQQ(req); -+ struct bfq_data *bfqd = bfqq->bfqd; -+ struct request *prev, *next_rq; -+ -+ /* Reposition request in its sort_list */ -+ elv_rb_del(&bfqq->sort_list, req); -+ elv_rb_add(&bfqq->sort_list, req); -+ /* Choose next request to be served for bfqq */ -+ prev = bfqq->next_rq; -+ next_rq = bfq_choose_req(bfqd, bfqq->next_rq, req, -+ bfqd->last_position); -+ BUG_ON(next_rq == NULL); -+ bfqq->next_rq = next_rq; -+ /* -+ * If next_rq changes, update both the queue's budget to -+ * fit the new request and the queue's position in its -+ * rq_pos_tree. -+ */ -+ if (prev != bfqq->next_rq) { -+ bfq_updated_next_req(bfqd, bfqq); -+ bfq_rq_pos_tree_add(bfqd, bfqq); -+ } -+ } -+} -+ -+static void bfq_merged_requests(struct request_queue *q, struct request *rq, -+ struct request *next) -+{ -+ struct bfq_queue *bfqq = RQ_BFQQ(rq); -+ -+ /* -+ * Reposition in fifo if next is older than rq. -+ */ -+ if (!list_empty(&rq->queuelist) && !list_empty(&next->queuelist) && -+ time_before(next->fifo_time, rq->fifo_time)) { -+ list_move(&rq->queuelist, &next->queuelist); -+ rq->fifo_time = next->fifo_time; -+ } -+ -+ if (bfqq->next_rq == next) -+ bfqq->next_rq = rq; -+ -+ bfq_remove_request(next); -+} -+ -+/* Must be called with bfqq != NULL */ -+static inline void bfq_bfqq_end_wr(struct bfq_queue *bfqq) -+{ -+ BUG_ON(bfqq == NULL); -+ if (bfq_bfqq_busy(bfqq)) -+ bfqq->bfqd->wr_busy_queues--; -+ bfqq->wr_coeff = 1; -+ bfqq->wr_cur_max_time = 0; -+ /* Trigger a weight change on the next activation of the queue */ -+ bfqq->entity.ioprio_changed = 1; -+} -+ -+static void bfq_end_wr_async_queues(struct bfq_data *bfqd, -+ struct bfq_group *bfqg) -+{ -+ int i, j; -+ -+ for (i = 0; i < 2; i++) -+ for (j = 0; j < IOPRIO_BE_NR; j++) -+ if (bfqg->async_bfqq[i][j] != NULL) -+ bfq_bfqq_end_wr(bfqg->async_bfqq[i][j]); -+ if (bfqg->async_idle_bfqq != NULL) -+ bfq_bfqq_end_wr(bfqg->async_idle_bfqq); -+} -+ -+static void bfq_end_wr(struct bfq_data *bfqd) -+{ -+ struct bfq_queue *bfqq; -+ -+ spin_lock_irq(bfqd->queue->queue_lock); -+ -+ list_for_each_entry(bfqq, &bfqd->active_list, bfqq_list) -+ bfq_bfqq_end_wr(bfqq); -+ list_for_each_entry(bfqq, &bfqd->idle_list, bfqq_list) -+ bfq_bfqq_end_wr(bfqq); -+ bfq_end_wr_async(bfqd); -+ -+ spin_unlock_irq(bfqd->queue->queue_lock); -+} -+ -+static inline sector_t bfq_io_struct_pos(void *io_struct, bool request) -+{ -+ if (request) -+ return blk_rq_pos(io_struct); -+ else -+ return ((struct bio *)io_struct)->bi_iter.bi_sector; -+} -+ -+static inline sector_t bfq_dist_from(sector_t pos1, -+ sector_t pos2) -+{ -+ if (pos1 >= pos2) -+ return pos1 - pos2; -+ else -+ return pos2 - pos1; -+} -+ -+static inline int bfq_rq_close_to_sector(void *io_struct, bool request, -+ sector_t sector) -+{ -+ return bfq_dist_from(bfq_io_struct_pos(io_struct, request), sector) <= -+ BFQQ_SEEK_THR; -+} -+ -+static struct bfq_queue *bfqq_close(struct bfq_data *bfqd, sector_t sector) -+{ -+ struct rb_root *root = &bfqd->rq_pos_tree; -+ struct rb_node *parent, *node; -+ struct bfq_queue *__bfqq; -+ -+ if (RB_EMPTY_ROOT(root)) -+ return NULL; -+ -+ /* -+ * First, if we find a request starting at the end of the last -+ * request, choose it. -+ */ -+ __bfqq = bfq_rq_pos_tree_lookup(bfqd, root, sector, &parent, NULL); -+ if (__bfqq != NULL) -+ return __bfqq; -+ -+ /* -+ * If the exact sector wasn't found, the parent of the NULL leaf -+ * will contain the closest sector (rq_pos_tree sorted by -+ * next_request position). -+ */ -+ __bfqq = rb_entry(parent, struct bfq_queue, pos_node); -+ if (bfq_rq_close_to_sector(__bfqq->next_rq, true, sector)) -+ return __bfqq; -+ -+ if (blk_rq_pos(__bfqq->next_rq) < sector) -+ node = rb_next(&__bfqq->pos_node); -+ else -+ node = rb_prev(&__bfqq->pos_node); -+ if (node == NULL) -+ return NULL; -+ -+ __bfqq = rb_entry(node, struct bfq_queue, pos_node); -+ if (bfq_rq_close_to_sector(__bfqq->next_rq, true, sector)) -+ return __bfqq; -+ -+ return NULL; -+} -+ -+/* -+ * bfqd - obvious -+ * cur_bfqq - passed in so that we don't decide that the current queue -+ * is closely cooperating with itself -+ * sector - used as a reference point to search for a close queue -+ */ -+static struct bfq_queue *bfq_close_cooperator(struct bfq_data *bfqd, -+ struct bfq_queue *cur_bfqq, -+ sector_t sector) -+{ -+ struct bfq_queue *bfqq; -+ -+ if (bfq_class_idle(cur_bfqq)) -+ return NULL; -+ if (!bfq_bfqq_sync(cur_bfqq)) -+ return NULL; -+ if (BFQQ_SEEKY(cur_bfqq)) -+ return NULL; -+ -+ /* If device has only one backlogged bfq_queue, don't search. */ -+ if (bfqd->busy_queues == 1) -+ return NULL; -+ -+ /* -+ * We should notice if some of the queues are cooperating, e.g. -+ * working closely on the same area of the disk. In that case, -+ * we can group them together and don't waste time idling. -+ */ -+ bfqq = bfqq_close(bfqd, sector); -+ if (bfqq == NULL || bfqq == cur_bfqq) -+ return NULL; -+ -+ /* -+ * Do not merge queues from different bfq_groups. -+ */ -+ if (bfqq->entity.parent != cur_bfqq->entity.parent) -+ return NULL; -+ -+ /* -+ * It only makes sense to merge sync queues. -+ */ -+ if (!bfq_bfqq_sync(bfqq)) -+ return NULL; -+ if (BFQQ_SEEKY(bfqq)) -+ return NULL; -+ -+ /* -+ * Do not merge queues of different priority classes. -+ */ -+ if (bfq_class_rt(bfqq) != bfq_class_rt(cur_bfqq)) -+ return NULL; -+ -+ return bfqq; -+} -+ -+static struct bfq_queue * -+bfq_setup_merge(struct bfq_queue *bfqq, struct bfq_queue *new_bfqq) -+{ -+ int process_refs, new_process_refs; -+ struct bfq_queue *__bfqq; -+ -+ /* -+ * If there are no process references on the new_bfqq, then it is -+ * unsafe to follow the ->new_bfqq chain as other bfqq's in the chain -+ * may have dropped their last reference (not just their last process -+ * reference). -+ */ -+ if (!bfqq_process_refs(new_bfqq)) -+ return NULL; -+ -+ /* Avoid a circular list and skip interim queue merges. */ -+ while ((__bfqq = new_bfqq->new_bfqq)) { -+ if (__bfqq == bfqq) -+ return NULL; -+ new_bfqq = __bfqq; -+ } -+ -+ process_refs = bfqq_process_refs(bfqq); -+ new_process_refs = bfqq_process_refs(new_bfqq); -+ /* -+ * If the process for the bfqq has gone away, there is no -+ * sense in merging the queues. -+ */ -+ if (process_refs == 0 || new_process_refs == 0) -+ return NULL; -+ -+ bfq_log_bfqq(bfqq->bfqd, bfqq, "scheduling merge with queue %d", -+ new_bfqq->pid); -+ -+ /* -+ * Merging is just a redirection: the requests of the process -+ * owning one of the two queues are redirected to the other queue. -+ * The latter queue, in its turn, is set as shared if this is the -+ * first time that the requests of some process are redirected to -+ * it. -+ * -+ * We redirect bfqq to new_bfqq and not the opposite, because we -+ * are in the context of the process owning bfqq, hence we have -+ * the io_cq of this process. So we can immediately configure this -+ * io_cq to redirect the requests of the process to new_bfqq. -+ * -+ * NOTE, even if new_bfqq coincides with the in-service queue, the -+ * io_cq of new_bfqq is not available, because, if the in-service -+ * queue is shared, bfqd->in_service_bic may not point to the -+ * io_cq of the in-service queue. -+ * Redirecting the requests of the process owning bfqq to the -+ * currently in-service queue is in any case the best option, as -+ * we feed the in-service queue with new requests close to the -+ * last request served and, by doing so, hopefully increase the -+ * throughput. -+ */ -+ bfqq->new_bfqq = new_bfqq; -+ atomic_add(process_refs, &new_bfqq->ref); -+ return new_bfqq; -+} -+ -+/* -+ * Attempt to schedule a merge of bfqq with the currently in-service queue -+ * or with a close queue among the scheduled queues. -+ * Return NULL if no merge was scheduled, a pointer to the shared bfq_queue -+ * structure otherwise. -+ * -+ * The OOM queue is not allowed to participate to cooperation: in fact, since -+ * the requests temporarily redirected to the OOM queue could be redirected -+ * again to dedicated queues at any time, the state needed to correctly -+ * handle merging with the OOM queue would be quite complex and expensive -+ * to maintain. Besides, in such a critical condition as an out of memory, -+ * the benefits of queue merging may be little relevant, or even negligible. -+ */ -+static struct bfq_queue * -+bfq_setup_cooperator(struct bfq_data *bfqd, struct bfq_queue *bfqq, -+ void *io_struct, bool request) -+{ -+ struct bfq_queue *in_service_bfqq, *new_bfqq; -+ -+ if (bfqq->new_bfqq) -+ return bfqq->new_bfqq; -+ -+ if (!io_struct || unlikely(bfqq == &bfqd->oom_bfqq)) -+ return NULL; -+ -+ in_service_bfqq = bfqd->in_service_queue; -+ -+ if (in_service_bfqq == NULL || in_service_bfqq == bfqq || -+ !bfqd->in_service_bic || -+ unlikely(in_service_bfqq == &bfqd->oom_bfqq)) -+ goto check_scheduled; -+ -+ if (bfq_class_idle(in_service_bfqq) || bfq_class_idle(bfqq)) -+ goto check_scheduled; -+ -+ if (bfq_class_rt(in_service_bfqq) != bfq_class_rt(bfqq)) -+ goto check_scheduled; -+ -+ if (in_service_bfqq->entity.parent != bfqq->entity.parent) -+ goto check_scheduled; -+ -+ if (bfq_rq_close_to_sector(io_struct, request, bfqd->last_position) && -+ bfq_bfqq_sync(in_service_bfqq) && bfq_bfqq_sync(bfqq)) { -+ new_bfqq = bfq_setup_merge(bfqq, in_service_bfqq); -+ if (new_bfqq != NULL) -+ return new_bfqq; /* Merge with in-service queue */ -+ } -+ -+ /* -+ * Check whether there is a cooperator among currently scheduled -+ * queues. The only thing we need is that the bio/request is not -+ * NULL, as we need it to establish whether a cooperator exists. -+ */ -+check_scheduled: -+ new_bfqq = bfq_close_cooperator(bfqd, bfqq, -+ bfq_io_struct_pos(io_struct, request)); -+ if (new_bfqq && likely(new_bfqq != &bfqd->oom_bfqq)) -+ return bfq_setup_merge(bfqq, new_bfqq); -+ -+ return NULL; -+} -+ -+static inline void -+bfq_bfqq_save_state(struct bfq_queue *bfqq) -+{ -+ /* -+ * If bfqq->bic == NULL, the queue is already shared or its requests -+ * have already been redirected to a shared queue; both idle window -+ * and weight raising state have already been saved. Do nothing. -+ */ -+ if (bfqq->bic == NULL) -+ return; -+ if (bfqq->bic->wr_time_left) -+ /* -+ * This is the queue of a just-started process, and would -+ * deserve weight raising: we set wr_time_left to the full -+ * weight-raising duration to trigger weight-raising when -+ * and if the queue is split and the first request of the -+ * queue is enqueued. -+ */ -+ bfqq->bic->wr_time_left = bfq_wr_duration(bfqq->bfqd); -+ else if (bfqq->wr_coeff > 1) { -+ unsigned long wr_duration = -+ jiffies - bfqq->last_wr_start_finish; -+ /* -+ * It may happen that a queue's weight raising period lasts -+ * longer than its wr_cur_max_time, as weight raising is -+ * handled only when a request is enqueued or dispatched (it -+ * does not use any timer). If the weight raising period is -+ * about to end, don't save it. -+ */ -+ if (bfqq->wr_cur_max_time <= wr_duration) -+ bfqq->bic->wr_time_left = 0; -+ else -+ bfqq->bic->wr_time_left = -+ bfqq->wr_cur_max_time - wr_duration; -+ /* -+ * The bfq_queue is becoming shared or the requests of the -+ * process owning the queue are being redirected to a shared -+ * queue. Stop the weight raising period of the queue, as in -+ * both cases it should not be owned by an interactive or -+ * soft real-time application. -+ */ -+ bfq_bfqq_end_wr(bfqq); -+ } else -+ bfqq->bic->wr_time_left = 0; -+ bfqq->bic->saved_idle_window = bfq_bfqq_idle_window(bfqq); -+ bfqq->bic->saved_IO_bound = bfq_bfqq_IO_bound(bfqq); -+ bfqq->bic->saved_in_large_burst = bfq_bfqq_in_large_burst(bfqq); -+ bfqq->bic->was_in_burst_list = !hlist_unhashed(&bfqq->burst_list_node); -+ bfqq->bic->cooperations++; -+ bfqq->bic->failed_cooperations = 0; -+} -+ -+static inline void -+bfq_get_bic_reference(struct bfq_queue *bfqq) -+{ -+ /* -+ * If bfqq->bic has a non-NULL value, the bic to which it belongs -+ * is about to begin using a shared bfq_queue. -+ */ -+ if (bfqq->bic) -+ atomic_long_inc(&bfqq->bic->icq.ioc->refcount); -+} -+ -+static void -+bfq_merge_bfqqs(struct bfq_data *bfqd, struct bfq_io_cq *bic, -+ struct bfq_queue *bfqq, struct bfq_queue *new_bfqq) -+{ -+ bfq_log_bfqq(bfqd, bfqq, "merging with queue %lu", -+ (long unsigned)new_bfqq->pid); -+ /* Save weight raising and idle window of the merged queues */ -+ bfq_bfqq_save_state(bfqq); -+ bfq_bfqq_save_state(new_bfqq); -+ if (bfq_bfqq_IO_bound(bfqq)) -+ bfq_mark_bfqq_IO_bound(new_bfqq); -+ bfq_clear_bfqq_IO_bound(bfqq); -+ /* -+ * Grab a reference to the bic, to prevent it from being destroyed -+ * before being possibly touched by a bfq_split_bfqq(). -+ */ -+ bfq_get_bic_reference(bfqq); -+ bfq_get_bic_reference(new_bfqq); -+ /* -+ * Merge queues (that is, let bic redirect its requests to new_bfqq) -+ */ -+ bic_set_bfqq(bic, new_bfqq, 1); -+ bfq_mark_bfqq_coop(new_bfqq); -+ /* -+ * new_bfqq now belongs to at least two bics (it is a shared queue): -+ * set new_bfqq->bic to NULL. bfqq either: -+ * - does not belong to any bic any more, and hence bfqq->bic must -+ * be set to NULL, or -+ * - is a queue whose owning bics have already been redirected to a -+ * different queue, hence the queue is destined to not belong to -+ * any bic soon and bfqq->bic is already NULL (therefore the next -+ * assignment causes no harm). -+ */ -+ new_bfqq->bic = NULL; -+ bfqq->bic = NULL; -+ bfq_put_queue(bfqq); -+} -+ -+static inline void bfq_bfqq_increase_failed_cooperations(struct bfq_queue *bfqq) -+{ -+ struct bfq_io_cq *bic = bfqq->bic; -+ struct bfq_data *bfqd = bfqq->bfqd; -+ -+ if (bic && bfq_bfqq_cooperations(bfqq) >= bfqd->bfq_coop_thresh) { -+ bic->failed_cooperations++; -+ if (bic->failed_cooperations >= bfqd->bfq_failed_cooperations) -+ bic->cooperations = 0; -+ } -+} -+ -+static int bfq_allow_merge(struct request_queue *q, struct request *rq, -+ struct bio *bio) -+{ -+ struct bfq_data *bfqd = q->elevator->elevator_data; -+ struct bfq_io_cq *bic; -+ struct bfq_queue *bfqq, *new_bfqq; -+ -+ /* -+ * Disallow merge of a sync bio into an async request. -+ */ -+ if (bfq_bio_sync(bio) && !rq_is_sync(rq)) -+ return 0; -+ -+ /* -+ * Lookup the bfqq that this bio will be queued with. Allow -+ * merge only if rq is queued there. -+ * Queue lock is held here. -+ */ -+ bic = bfq_bic_lookup(bfqd, current->io_context); -+ if (bic == NULL) -+ return 0; -+ -+ bfqq = bic_to_bfqq(bic, bfq_bio_sync(bio)); -+ /* -+ * We take advantage of this function to perform an early merge -+ * of the queues of possible cooperating processes. -+ */ -+ if (bfqq != NULL) { -+ new_bfqq = bfq_setup_cooperator(bfqd, bfqq, bio, false); -+ if (new_bfqq != NULL) { -+ bfq_merge_bfqqs(bfqd, bic, bfqq, new_bfqq); -+ /* -+ * If we get here, the bio will be queued in the -+ * shared queue, i.e., new_bfqq, so use new_bfqq -+ * to decide whether bio and rq can be merged. -+ */ -+ bfqq = new_bfqq; -+ } else -+ bfq_bfqq_increase_failed_cooperations(bfqq); -+ } -+ -+ return bfqq == RQ_BFQQ(rq); -+} -+ -+static void __bfq_set_in_service_queue(struct bfq_data *bfqd, -+ struct bfq_queue *bfqq) -+{ -+ if (bfqq != NULL) { -+ bfq_mark_bfqq_must_alloc(bfqq); -+ bfq_mark_bfqq_budget_new(bfqq); -+ bfq_clear_bfqq_fifo_expire(bfqq); -+ -+ bfqd->budgets_assigned = (bfqd->budgets_assigned*7 + 256) / 8; -+ -+ bfq_log_bfqq(bfqd, bfqq, -+ "set_in_service_queue, cur-budget = %lu", -+ bfqq->entity.budget); -+ } -+ -+ bfqd->in_service_queue = bfqq; -+} -+ -+/* -+ * Get and set a new queue for service. -+ */ -+static struct bfq_queue *bfq_set_in_service_queue(struct bfq_data *bfqd) -+{ -+ struct bfq_queue *bfqq = bfq_get_next_queue(bfqd); -+ -+ __bfq_set_in_service_queue(bfqd, bfqq); -+ return bfqq; -+} -+ -+/* -+ * If enough samples have been computed, return the current max budget -+ * stored in bfqd, which is dynamically updated according to the -+ * estimated disk peak rate; otherwise return the default max budget -+ */ -+static inline unsigned long bfq_max_budget(struct bfq_data *bfqd) -+{ -+ if (bfqd->budgets_assigned < 194) -+ return bfq_default_max_budget; -+ else -+ return bfqd->bfq_max_budget; -+} -+ -+/* -+ * Return min budget, which is a fraction of the current or default -+ * max budget (trying with 1/32) -+ */ -+static inline unsigned long bfq_min_budget(struct bfq_data *bfqd) -+{ -+ if (bfqd->budgets_assigned < 194) -+ return bfq_default_max_budget / 32; -+ else -+ return bfqd->bfq_max_budget / 32; -+} -+ -+static void bfq_arm_slice_timer(struct bfq_data *bfqd) -+{ -+ struct bfq_queue *bfqq = bfqd->in_service_queue; -+ struct bfq_io_cq *bic; -+ unsigned long sl; -+ -+ BUG_ON(!RB_EMPTY_ROOT(&bfqq->sort_list)); -+ -+ /* Processes have exited, don't wait. */ -+ bic = bfqd->in_service_bic; -+ if (bic == NULL || atomic_read(&bic->icq.ioc->active_ref) == 0) -+ return; -+ -+ bfq_mark_bfqq_wait_request(bfqq); -+ -+ /* -+ * We don't want to idle for seeks, but we do want to allow -+ * fair distribution of slice time for a process doing back-to-back -+ * seeks. So allow a little bit of time for him to submit a new rq. -+ * -+ * To prevent processes with (partly) seeky workloads from -+ * being too ill-treated, grant them a small fraction of the -+ * assigned budget before reducing the waiting time to -+ * BFQ_MIN_TT. This happened to help reduce latency. -+ */ -+ sl = bfqd->bfq_slice_idle; -+ /* -+ * Unless the queue is being weight-raised, grant only minimum idle -+ * time if the queue either has been seeky for long enough or has -+ * already proved to be constantly seeky. -+ */ -+ if (bfq_sample_valid(bfqq->seek_samples) && -+ ((BFQQ_SEEKY(bfqq) && bfqq->entity.service > -+ bfq_max_budget(bfqq->bfqd) / 8) || -+ bfq_bfqq_constantly_seeky(bfqq)) && bfqq->wr_coeff == 1) -+ sl = min(sl, msecs_to_jiffies(BFQ_MIN_TT)); -+ else if (bfqq->wr_coeff > 1) -+ sl = sl * 3; -+ bfqd->last_idling_start = ktime_get(); -+ mod_timer(&bfqd->idle_slice_timer, jiffies + sl); -+ bfq_log(bfqd, "arm idle: %u/%u ms", -+ jiffies_to_msecs(sl), jiffies_to_msecs(bfqd->bfq_slice_idle)); -+} -+ -+/* -+ * Set the maximum time for the in-service queue to consume its -+ * budget. This prevents seeky processes from lowering the disk -+ * throughput (always guaranteed with a time slice scheme as in CFQ). -+ */ -+static void bfq_set_budget_timeout(struct bfq_data *bfqd) -+{ -+ struct bfq_queue *bfqq = bfqd->in_service_queue; -+ unsigned int timeout_coeff; -+ if (bfqq->wr_cur_max_time == bfqd->bfq_wr_rt_max_time) -+ timeout_coeff = 1; -+ else -+ timeout_coeff = bfqq->entity.weight / bfqq->entity.orig_weight; -+ -+ bfqd->last_budget_start = ktime_get(); -+ -+ bfq_clear_bfqq_budget_new(bfqq); -+ bfqq->budget_timeout = jiffies + -+ bfqd->bfq_timeout[bfq_bfqq_sync(bfqq)] * timeout_coeff; -+ -+ bfq_log_bfqq(bfqd, bfqq, "set budget_timeout %u", -+ jiffies_to_msecs(bfqd->bfq_timeout[bfq_bfqq_sync(bfqq)] * -+ timeout_coeff)); -+} -+ -+/* -+ * Move request from internal lists to the request queue dispatch list. -+ */ -+static void bfq_dispatch_insert(struct request_queue *q, struct request *rq) -+{ -+ struct bfq_data *bfqd = q->elevator->elevator_data; -+ struct bfq_queue *bfqq = RQ_BFQQ(rq); -+ -+ /* -+ * For consistency, the next instruction should have been executed -+ * after removing the request from the queue and dispatching it. -+ * We execute instead this instruction before bfq_remove_request() -+ * (and hence introduce a temporary inconsistency), for efficiency. -+ * In fact, in a forced_dispatch, this prevents two counters related -+ * to bfqq->dispatched to risk to be uselessly decremented if bfqq -+ * is not in service, and then to be incremented again after -+ * incrementing bfqq->dispatched. -+ */ -+ bfqq->dispatched++; -+ bfq_remove_request(rq); -+ elv_dispatch_sort(q, rq); -+ -+ if (bfq_bfqq_sync(bfqq)) -+ bfqd->sync_flight++; -+} -+ -+/* -+ * Return expired entry, or NULL to just start from scratch in rbtree. -+ */ -+static struct request *bfq_check_fifo(struct bfq_queue *bfqq) -+{ -+ struct request *rq = NULL; -+ -+ if (bfq_bfqq_fifo_expire(bfqq)) -+ return NULL; -+ -+ bfq_mark_bfqq_fifo_expire(bfqq); -+ -+ if (list_empty(&bfqq->fifo)) -+ return NULL; -+ -+ rq = rq_entry_fifo(bfqq->fifo.next); -+ -+ if (time_before(jiffies, rq->fifo_time)) -+ return NULL; -+ -+ return rq; -+} -+ -+static inline unsigned long bfq_bfqq_budget_left(struct bfq_queue *bfqq) -+{ -+ struct bfq_entity *entity = &bfqq->entity; -+ return entity->budget - entity->service; -+} -+ -+static void __bfq_bfqq_expire(struct bfq_data *bfqd, struct bfq_queue *bfqq) -+{ -+ BUG_ON(bfqq != bfqd->in_service_queue); -+ -+ __bfq_bfqd_reset_in_service(bfqd); -+ -+ /* -+ * If this bfqq is shared between multiple processes, check -+ * to make sure that those processes are still issuing I/Os -+ * within the mean seek distance. If not, it may be time to -+ * break the queues apart again. -+ */ -+ if (bfq_bfqq_coop(bfqq) && BFQQ_SEEKY(bfqq)) -+ bfq_mark_bfqq_split_coop(bfqq); -+ -+ if (RB_EMPTY_ROOT(&bfqq->sort_list)) { -+ /* -+ * Overloading budget_timeout field to store the time -+ * at which the queue remains with no backlog; used by -+ * the weight-raising mechanism. -+ */ -+ bfqq->budget_timeout = jiffies; -+ bfq_del_bfqq_busy(bfqd, bfqq, 1); -+ } else { -+ bfq_activate_bfqq(bfqd, bfqq); -+ /* -+ * Resort priority tree of potential close cooperators. -+ */ -+ bfq_rq_pos_tree_add(bfqd, bfqq); -+ } -+} -+ -+/** -+ * __bfq_bfqq_recalc_budget - try to adapt the budget to the @bfqq behavior. -+ * @bfqd: device data. -+ * @bfqq: queue to update. -+ * @reason: reason for expiration. -+ * -+ * Handle the feedback on @bfqq budget. See the body for detailed -+ * comments. -+ */ -+static void __bfq_bfqq_recalc_budget(struct bfq_data *bfqd, -+ struct bfq_queue *bfqq, -+ enum bfqq_expiration reason) -+{ -+ struct request *next_rq; -+ unsigned long budget, min_budget; -+ -+ budget = bfqq->max_budget; -+ min_budget = bfq_min_budget(bfqd); -+ -+ BUG_ON(bfqq != bfqd->in_service_queue); -+ -+ bfq_log_bfqq(bfqd, bfqq, "recalc_budg: last budg %lu, budg left %lu", -+ bfqq->entity.budget, bfq_bfqq_budget_left(bfqq)); -+ bfq_log_bfqq(bfqd, bfqq, "recalc_budg: last max_budg %lu, min budg %lu", -+ budget, bfq_min_budget(bfqd)); -+ bfq_log_bfqq(bfqd, bfqq, "recalc_budg: sync %d, seeky %d", -+ bfq_bfqq_sync(bfqq), BFQQ_SEEKY(bfqd->in_service_queue)); -+ -+ if (bfq_bfqq_sync(bfqq)) { -+ switch (reason) { -+ /* -+ * Caveat: in all the following cases we trade latency -+ * for throughput. -+ */ -+ case BFQ_BFQQ_TOO_IDLE: -+ /* -+ * This is the only case where we may reduce -+ * the budget: if there is no request of the -+ * process still waiting for completion, then -+ * we assume (tentatively) that the timer has -+ * expired because the batch of requests of -+ * the process could have been served with a -+ * smaller budget. Hence, betting that -+ * process will behave in the same way when it -+ * becomes backlogged again, we reduce its -+ * next budget. As long as we guess right, -+ * this budget cut reduces the latency -+ * experienced by the process. -+ * -+ * However, if there are still outstanding -+ * requests, then the process may have not yet -+ * issued its next request just because it is -+ * still waiting for the completion of some of -+ * the still outstanding ones. So in this -+ * subcase we do not reduce its budget, on the -+ * contrary we increase it to possibly boost -+ * the throughput, as discussed in the -+ * comments to the BUDGET_TIMEOUT case. -+ */ -+ if (bfqq->dispatched > 0) /* still outstanding reqs */ -+ budget = min(budget * 2, bfqd->bfq_max_budget); -+ else { -+ if (budget > 5 * min_budget) -+ budget -= 4 * min_budget; -+ else -+ budget = min_budget; -+ } -+ break; -+ case BFQ_BFQQ_BUDGET_TIMEOUT: -+ /* -+ * We double the budget here because: 1) it -+ * gives the chance to boost the throughput if -+ * this is not a seeky process (which may have -+ * bumped into this timeout because of, e.g., -+ * ZBR), 2) together with charge_full_budget -+ * it helps give seeky processes higher -+ * timestamps, and hence be served less -+ * frequently. -+ */ -+ budget = min(budget * 2, bfqd->bfq_max_budget); -+ break; -+ case BFQ_BFQQ_BUDGET_EXHAUSTED: -+ /* -+ * The process still has backlog, and did not -+ * let either the budget timeout or the disk -+ * idling timeout expire. Hence it is not -+ * seeky, has a short thinktime and may be -+ * happy with a higher budget too. So -+ * definitely increase the budget of this good -+ * candidate to boost the disk throughput. -+ */ -+ budget = min(budget * 4, bfqd->bfq_max_budget); -+ break; -+ case BFQ_BFQQ_NO_MORE_REQUESTS: -+ /* -+ * Leave the budget unchanged. -+ */ -+ default: -+ return; -+ } -+ } else /* async queue */ -+ /* async queues get always the maximum possible budget -+ * (their ability to dispatch is limited by -+ * @bfqd->bfq_max_budget_async_rq). -+ */ -+ budget = bfqd->bfq_max_budget; -+ -+ bfqq->max_budget = budget; -+ -+ if (bfqd->budgets_assigned >= 194 && bfqd->bfq_user_max_budget == 0 && -+ bfqq->max_budget > bfqd->bfq_max_budget) -+ bfqq->max_budget = bfqd->bfq_max_budget; -+ -+ /* -+ * Make sure that we have enough budget for the next request. -+ * Since the finish time of the bfqq must be kept in sync with -+ * the budget, be sure to call __bfq_bfqq_expire() after the -+ * update. -+ */ -+ next_rq = bfqq->next_rq; -+ if (next_rq != NULL) -+ bfqq->entity.budget = max_t(unsigned long, bfqq->max_budget, -+ bfq_serv_to_charge(next_rq, bfqq)); -+ else -+ bfqq->entity.budget = bfqq->max_budget; -+ -+ bfq_log_bfqq(bfqd, bfqq, "head sect: %u, new budget %lu", -+ next_rq != NULL ? blk_rq_sectors(next_rq) : 0, -+ bfqq->entity.budget); -+} -+ -+static unsigned long bfq_calc_max_budget(u64 peak_rate, u64 timeout) -+{ -+ unsigned long max_budget; -+ -+ /* -+ * The max_budget calculated when autotuning is equal to the -+ * amount of sectors transfered in timeout_sync at the -+ * estimated peak rate. -+ */ -+ max_budget = (unsigned long)(peak_rate * 1000 * -+ timeout >> BFQ_RATE_SHIFT); -+ -+ return max_budget; -+} -+ -+/* -+ * In addition to updating the peak rate, checks whether the process -+ * is "slow", and returns 1 if so. This slow flag is used, in addition -+ * to the budget timeout, to reduce the amount of service provided to -+ * seeky processes, and hence reduce their chances to lower the -+ * throughput. See the code for more details. -+ */ -+static int bfq_update_peak_rate(struct bfq_data *bfqd, struct bfq_queue *bfqq, -+ int compensate, enum bfqq_expiration reason) -+{ -+ u64 bw, usecs, expected, timeout; -+ ktime_t delta; -+ int update = 0; -+ -+ if (!bfq_bfqq_sync(bfqq) || bfq_bfqq_budget_new(bfqq)) -+ return 0; -+ -+ if (compensate) -+ delta = bfqd->last_idling_start; -+ else -+ delta = ktime_get(); -+ delta = ktime_sub(delta, bfqd->last_budget_start); -+ usecs = ktime_to_us(delta); -+ -+ /* Don't trust short/unrealistic values. */ -+ if (usecs < 100 || usecs >= LONG_MAX) -+ return 0; -+ -+ /* -+ * Calculate the bandwidth for the last slice. We use a 64 bit -+ * value to store the peak rate, in sectors per usec in fixed -+ * point math. We do so to have enough precision in the estimate -+ * and to avoid overflows. -+ */ -+ bw = (u64)bfqq->entity.service << BFQ_RATE_SHIFT; -+ do_div(bw, (unsigned long)usecs); -+ -+ timeout = jiffies_to_msecs(bfqd->bfq_timeout[BLK_RW_SYNC]); -+ -+ /* -+ * Use only long (> 20ms) intervals to filter out spikes for -+ * the peak rate estimation. -+ */ -+ if (usecs > 20000) { -+ if (bw > bfqd->peak_rate || -+ (!BFQQ_SEEKY(bfqq) && -+ reason == BFQ_BFQQ_BUDGET_TIMEOUT)) { -+ bfq_log(bfqd, "measured bw =%llu", bw); -+ /* -+ * To smooth oscillations use a low-pass filter with -+ * alpha=7/8, i.e., -+ * new_rate = (7/8) * old_rate + (1/8) * bw -+ */ -+ do_div(bw, 8); -+ if (bw == 0) -+ return 0; -+ bfqd->peak_rate *= 7; -+ do_div(bfqd->peak_rate, 8); -+ bfqd->peak_rate += bw; -+ update = 1; -+ bfq_log(bfqd, "new peak_rate=%llu", bfqd->peak_rate); -+ } -+ -+ update |= bfqd->peak_rate_samples == BFQ_PEAK_RATE_SAMPLES - 1; -+ -+ if (bfqd->peak_rate_samples < BFQ_PEAK_RATE_SAMPLES) -+ bfqd->peak_rate_samples++; -+ -+ if (bfqd->peak_rate_samples == BFQ_PEAK_RATE_SAMPLES && -+ update) { -+ int dev_type = blk_queue_nonrot(bfqd->queue); -+ if (bfqd->bfq_user_max_budget == 0) { -+ bfqd->bfq_max_budget = -+ bfq_calc_max_budget(bfqd->peak_rate, -+ timeout); -+ bfq_log(bfqd, "new max_budget=%lu", -+ bfqd->bfq_max_budget); -+ } -+ if (bfqd->device_speed == BFQ_BFQD_FAST && -+ bfqd->peak_rate < device_speed_thresh[dev_type]) { -+ bfqd->device_speed = BFQ_BFQD_SLOW; -+ bfqd->RT_prod = R_slow[dev_type] * -+ T_slow[dev_type]; -+ } else if (bfqd->device_speed == BFQ_BFQD_SLOW && -+ bfqd->peak_rate > device_speed_thresh[dev_type]) { -+ bfqd->device_speed = BFQ_BFQD_FAST; -+ bfqd->RT_prod = R_fast[dev_type] * -+ T_fast[dev_type]; -+ } -+ } -+ } -+ -+ /* -+ * If the process has been served for a too short time -+ * interval to let its possible sequential accesses prevail on -+ * the initial seek time needed to move the disk head on the -+ * first sector it requested, then give the process a chance -+ * and for the moment return false. -+ */ -+ if (bfqq->entity.budget <= bfq_max_budget(bfqd) / 8) -+ return 0; -+ -+ /* -+ * A process is considered ``slow'' (i.e., seeky, so that we -+ * cannot treat it fairly in the service domain, as it would -+ * slow down too much the other processes) if, when a slice -+ * ends for whatever reason, it has received service at a -+ * rate that would not be high enough to complete the budget -+ * before the budget timeout expiration. -+ */ -+ expected = bw * 1000 * timeout >> BFQ_RATE_SHIFT; -+ -+ /* -+ * Caveat: processes doing IO in the slower disk zones will -+ * tend to be slow(er) even if not seeky. And the estimated -+ * peak rate will actually be an average over the disk -+ * surface. Hence, to not be too harsh with unlucky processes, -+ * we keep a budget/3 margin of safety before declaring a -+ * process slow. -+ */ -+ return expected > (4 * bfqq->entity.budget) / 3; -+} -+ -+/* -+ * To be deemed as soft real-time, an application must meet two -+ * requirements. First, the application must not require an average -+ * bandwidth higher than the approximate bandwidth required to playback or -+ * record a compressed high-definition video. -+ * The next function is invoked on the completion of the last request of a -+ * batch, to compute the next-start time instant, soft_rt_next_start, such -+ * that, if the next request of the application does not arrive before -+ * soft_rt_next_start, then the above requirement on the bandwidth is met. -+ * -+ * The second requirement is that the request pattern of the application is -+ * isochronous, i.e., that, after issuing a request or a batch of requests, -+ * the application stops issuing new requests until all its pending requests -+ * have been completed. After that, the application may issue a new batch, -+ * and so on. -+ * For this reason the next function is invoked to compute -+ * soft_rt_next_start only for applications that meet this requirement, -+ * whereas soft_rt_next_start is set to infinity for applications that do -+ * not. -+ * -+ * Unfortunately, even a greedy application may happen to behave in an -+ * isochronous way if the CPU load is high. In fact, the application may -+ * stop issuing requests while the CPUs are busy serving other processes, -+ * then restart, then stop again for a while, and so on. In addition, if -+ * the disk achieves a low enough throughput with the request pattern -+ * issued by the application (e.g., because the request pattern is random -+ * and/or the device is slow), then the application may meet the above -+ * bandwidth requirement too. To prevent such a greedy application to be -+ * deemed as soft real-time, a further rule is used in the computation of -+ * soft_rt_next_start: soft_rt_next_start must be higher than the current -+ * time plus the maximum time for which the arrival of a request is waited -+ * for when a sync queue becomes idle, namely bfqd->bfq_slice_idle. -+ * This filters out greedy applications, as the latter issue instead their -+ * next request as soon as possible after the last one has been completed -+ * (in contrast, when a batch of requests is completed, a soft real-time -+ * application spends some time processing data). -+ * -+ * Unfortunately, the last filter may easily generate false positives if -+ * only bfqd->bfq_slice_idle is used as a reference time interval and one -+ * or both the following cases occur: -+ * 1) HZ is so low that the duration of a jiffy is comparable to or higher -+ * than bfqd->bfq_slice_idle. This happens, e.g., on slow devices with -+ * HZ=100. -+ * 2) jiffies, instead of increasing at a constant rate, may stop increasing -+ * for a while, then suddenly 'jump' by several units to recover the lost -+ * increments. This seems to happen, e.g., inside virtual machines. -+ * To address this issue, we do not use as a reference time interval just -+ * bfqd->bfq_slice_idle, but bfqd->bfq_slice_idle plus a few jiffies. In -+ * particular we add the minimum number of jiffies for which the filter -+ * seems to be quite precise also in embedded systems and KVM/QEMU virtual -+ * machines. -+ */ -+static inline unsigned long bfq_bfqq_softrt_next_start(struct bfq_data *bfqd, -+ struct bfq_queue *bfqq) -+{ -+ return max(bfqq->last_idle_bklogged + -+ HZ * bfqq->service_from_backlogged / -+ bfqd->bfq_wr_max_softrt_rate, -+ jiffies + bfqq->bfqd->bfq_slice_idle + 4); -+} -+ -+/* -+ * Return the largest-possible time instant such that, for as long as possible, -+ * the current time will be lower than this time instant according to the macro -+ * time_is_before_jiffies(). -+ */ -+static inline unsigned long bfq_infinity_from_now(unsigned long now) -+{ -+ return now + ULONG_MAX / 2; -+} -+ -+/** -+ * bfq_bfqq_expire - expire a queue. -+ * @bfqd: device owning the queue. -+ * @bfqq: the queue to expire. -+ * @compensate: if true, compensate for the time spent idling. -+ * @reason: the reason causing the expiration. -+ * -+ * -+ * If the process associated to the queue is slow (i.e., seeky), or in -+ * case of budget timeout, or, finally, if it is async, we -+ * artificially charge it an entire budget (independently of the -+ * actual service it received). As a consequence, the queue will get -+ * higher timestamps than the correct ones upon reactivation, and -+ * hence it will be rescheduled as if it had received more service -+ * than what it actually received. In the end, this class of processes -+ * will receive less service in proportion to how slowly they consume -+ * their budgets (and hence how seriously they tend to lower the -+ * throughput). -+ * -+ * In contrast, when a queue expires because it has been idling for -+ * too much or because it exhausted its budget, we do not touch the -+ * amount of service it has received. Hence when the queue will be -+ * reactivated and its timestamps updated, the latter will be in sync -+ * with the actual service received by the queue until expiration. -+ * -+ * Charging a full budget to the first type of queues and the exact -+ * service to the others has the effect of using the WF2Q+ policy to -+ * schedule the former on a timeslice basis, without violating the -+ * service domain guarantees of the latter. -+ */ -+static void bfq_bfqq_expire(struct bfq_data *bfqd, -+ struct bfq_queue *bfqq, -+ int compensate, -+ enum bfqq_expiration reason) -+{ -+ int slow; -+ BUG_ON(bfqq != bfqd->in_service_queue); -+ -+ /* Update disk peak rate for autotuning and check whether the -+ * process is slow (see bfq_update_peak_rate). -+ */ -+ slow = bfq_update_peak_rate(bfqd, bfqq, compensate, reason); -+ -+ /* -+ * As above explained, 'punish' slow (i.e., seeky), timed-out -+ * and async queues, to favor sequential sync workloads. -+ * -+ * Processes doing I/O in the slower disk zones will tend to be -+ * slow(er) even if not seeky. Hence, since the estimated peak -+ * rate is actually an average over the disk surface, these -+ * processes may timeout just for bad luck. To avoid punishing -+ * them we do not charge a full budget to a process that -+ * succeeded in consuming at least 2/3 of its budget. -+ */ -+ if (slow || (reason == BFQ_BFQQ_BUDGET_TIMEOUT && -+ bfq_bfqq_budget_left(bfqq) >= bfqq->entity.budget / 3)) -+ bfq_bfqq_charge_full_budget(bfqq); -+ -+ bfqq->service_from_backlogged += bfqq->entity.service; -+ -+ if (BFQQ_SEEKY(bfqq) && reason == BFQ_BFQQ_BUDGET_TIMEOUT && -+ !bfq_bfqq_constantly_seeky(bfqq)) { -+ bfq_mark_bfqq_constantly_seeky(bfqq); -+ if (!blk_queue_nonrot(bfqd->queue)) -+ bfqd->const_seeky_busy_in_flight_queues++; -+ } -+ -+ if (reason == BFQ_BFQQ_TOO_IDLE && -+ bfqq->entity.service <= 2 * bfqq->entity.budget / 10 ) -+ bfq_clear_bfqq_IO_bound(bfqq); -+ -+ if (bfqd->low_latency && bfqq->wr_coeff == 1) -+ bfqq->last_wr_start_finish = jiffies; -+ -+ if (bfqd->low_latency && bfqd->bfq_wr_max_softrt_rate > 0 && -+ RB_EMPTY_ROOT(&bfqq->sort_list)) { -+ /* -+ * If we get here, and there are no outstanding requests, -+ * then the request pattern is isochronous (see the comments -+ * to the function bfq_bfqq_softrt_next_start()). Hence we -+ * can compute soft_rt_next_start. If, instead, the queue -+ * still has outstanding requests, then we have to wait -+ * for the completion of all the outstanding requests to -+ * discover whether the request pattern is actually -+ * isochronous. -+ */ -+ if (bfqq->dispatched == 0) -+ bfqq->soft_rt_next_start = -+ bfq_bfqq_softrt_next_start(bfqd, bfqq); -+ else { -+ /* -+ * The application is still waiting for the -+ * completion of one or more requests: -+ * prevent it from possibly being incorrectly -+ * deemed as soft real-time by setting its -+ * soft_rt_next_start to infinity. In fact, -+ * without this assignment, the application -+ * would be incorrectly deemed as soft -+ * real-time if: -+ * 1) it issued a new request before the -+ * completion of all its in-flight -+ * requests, and -+ * 2) at that time, its soft_rt_next_start -+ * happened to be in the past. -+ */ -+ bfqq->soft_rt_next_start = -+ bfq_infinity_from_now(jiffies); -+ /* -+ * Schedule an update of soft_rt_next_start to when -+ * the task may be discovered to be isochronous. -+ */ -+ bfq_mark_bfqq_softrt_update(bfqq); -+ } -+ } -+ -+ bfq_log_bfqq(bfqd, bfqq, -+ "expire (%d, slow %d, num_disp %d, idle_win %d)", reason, -+ slow, bfqq->dispatched, bfq_bfqq_idle_window(bfqq)); -+ -+ /* -+ * Increase, decrease or leave budget unchanged according to -+ * reason. -+ */ -+ __bfq_bfqq_recalc_budget(bfqd, bfqq, reason); -+ __bfq_bfqq_expire(bfqd, bfqq); -+} -+ -+/* -+ * Budget timeout is not implemented through a dedicated timer, but -+ * just checked on request arrivals and completions, as well as on -+ * idle timer expirations. -+ */ -+static int bfq_bfqq_budget_timeout(struct bfq_queue *bfqq) -+{ -+ if (bfq_bfqq_budget_new(bfqq) || -+ time_before(jiffies, bfqq->budget_timeout)) -+ return 0; -+ return 1; -+} -+ -+/* -+ * If we expire a queue that is waiting for the arrival of a new -+ * request, we may prevent the fictitious timestamp back-shifting that -+ * allows the guarantees of the queue to be preserved (see [1] for -+ * this tricky aspect). Hence we return true only if this condition -+ * does not hold, or if the queue is slow enough to deserve only to be -+ * kicked off for preserving a high throughput. -+*/ -+static inline int bfq_may_expire_for_budg_timeout(struct bfq_queue *bfqq) -+{ -+ bfq_log_bfqq(bfqq->bfqd, bfqq, -+ "may_budget_timeout: wait_request %d left %d timeout %d", -+ bfq_bfqq_wait_request(bfqq), -+ bfq_bfqq_budget_left(bfqq) >= bfqq->entity.budget / 3, -+ bfq_bfqq_budget_timeout(bfqq)); -+ -+ return (!bfq_bfqq_wait_request(bfqq) || -+ bfq_bfqq_budget_left(bfqq) >= bfqq->entity.budget / 3) -+ && -+ bfq_bfqq_budget_timeout(bfqq); -+} -+ -+/* -+ * Device idling is allowed only for the queues for which this function -+ * returns true. For this reason, the return value of this function plays a -+ * critical role for both throughput boosting and service guarantees. The -+ * return value is computed through a logical expression. In this rather -+ * long comment, we try to briefly describe all the details and motivations -+ * behind the components of this logical expression. -+ * -+ * First, the expression is false if bfqq is not sync, or if: bfqq happened -+ * to become active during a large burst of queue activations, and the -+ * pattern of requests bfqq contains boosts the throughput if bfqq is -+ * expired. In fact, queues that became active during a large burst benefit -+ * only from throughput, as discussed in the comments to bfq_handle_burst. -+ * In this respect, expiring bfqq certainly boosts the throughput on NCQ- -+ * capable flash-based devices, whereas, on rotational devices, it boosts -+ * the throughput only if bfqq contains random requests. -+ * -+ * On the opposite end, if (a) bfqq is sync, (b) the above burst-related -+ * condition does not hold, and (c) bfqq is being weight-raised, then the -+ * expression always evaluates to true, as device idling is instrumental -+ * for preserving low-latency guarantees (see [1]). If, instead, conditions -+ * (a) and (b) do hold, but (c) does not, then the expression evaluates to -+ * true only if: (1) bfqq is I/O-bound and has a non-null idle window, and -+ * (2) at least one of the following two conditions holds. -+ * The first condition is that the device is not performing NCQ, because -+ * idling the device most certainly boosts the throughput if this condition -+ * holds and bfqq is I/O-bound and has been granted a non-null idle window. -+ * The second compound condition is made of the logical AND of two components. -+ * -+ * The first component is true only if there is no weight-raised busy -+ * queue. This guarantees that the device is not idled for a sync non- -+ * weight-raised queue when there are busy weight-raised queues. The former -+ * is then expired immediately if empty. Combined with the timestamping -+ * rules of BFQ (see [1] for details), this causes sync non-weight-raised -+ * queues to get a lower number of requests served, and hence to ask for a -+ * lower number of requests from the request pool, before the busy weight- -+ * raised queues get served again. -+ * -+ * This is beneficial for the processes associated with weight-raised -+ * queues, when the request pool is saturated (e.g., in the presence of -+ * write hogs). In fact, if the processes associated with the other queues -+ * ask for requests at a lower rate, then weight-raised processes have a -+ * higher probability to get a request from the pool immediately (or at -+ * least soon) when they need one. Hence they have a higher probability to -+ * actually get a fraction of the disk throughput proportional to their -+ * high weight. This is especially true with NCQ-capable drives, which -+ * enqueue several requests in advance and further reorder internally- -+ * queued requests. -+ * -+ * In the end, mistreating non-weight-raised queues when there are busy -+ * weight-raised queues seems to mitigate starvation problems in the -+ * presence of heavy write workloads and NCQ, and hence to guarantee a -+ * higher application and system responsiveness in these hostile scenarios. -+ * -+ * If the first component of the compound condition is instead true, i.e., -+ * there is no weight-raised busy queue, then the second component of the -+ * compound condition takes into account service-guarantee and throughput -+ * issues related to NCQ (recall that the compound condition is evaluated -+ * only if the device is detected as supporting NCQ). -+ * -+ * As for service guarantees, allowing the drive to enqueue more than one -+ * request at a time, and hence delegating de facto final scheduling -+ * decisions to the drive's internal scheduler, causes loss of control on -+ * the actual request service order. In this respect, when the drive is -+ * allowed to enqueue more than one request at a time, the service -+ * distribution enforced by the drive's internal scheduler is likely to -+ * coincide with the desired device-throughput distribution only in the -+ * following, perfectly symmetric, scenario: -+ * 1) all active queues have the same weight, -+ * 2) all active groups at the same level in the groups tree have the same -+ * weight, -+ * 3) all active groups at the same level in the groups tree have the same -+ * number of children. -+ * -+ * Even in such a scenario, sequential I/O may still receive a preferential -+ * treatment, but this is not likely to be a big issue with flash-based -+ * devices, because of their non-dramatic loss of throughput with random -+ * I/O. Things do differ with HDDs, for which additional care is taken, as -+ * explained after completing the discussion for flash-based devices. -+ * -+ * Unfortunately, keeping the necessary state for evaluating exactly the -+ * above symmetry conditions would be quite complex and time-consuming. -+ * Therefore BFQ evaluates instead the following stronger sub-conditions, -+ * for which it is much easier to maintain the needed state: -+ * 1) all active queues have the same weight, -+ * 2) all active groups have the same weight, -+ * 3) all active groups have at most one active child each. -+ * In particular, the last two conditions are always true if hierarchical -+ * support and the cgroups interface are not enabled, hence no state needs -+ * to be maintained in this case. -+ * -+ * According to the above considerations, the second component of the -+ * compound condition evaluates to true if any of the above symmetry -+ * sub-condition does not hold, or the device is not flash-based. Therefore, -+ * if also the first component is true, then idling is allowed for a sync -+ * queue. These are the only sub-conditions considered if the device is -+ * flash-based, as, for such a device, it is sensible to force idling only -+ * for service-guarantee issues. In fact, as for throughput, idling -+ * NCQ-capable flash-based devices would not boost the throughput even -+ * with sequential I/O; rather it would lower the throughput in proportion -+ * to how fast the device is. In the end, (only) if all the three -+ * sub-conditions hold and the device is flash-based, the compound -+ * condition evaluates to false and therefore no idling is performed. -+ * -+ * As already said, things change with a rotational device, where idling -+ * boosts the throughput with sequential I/O (even with NCQ). Hence, for -+ * such a device the second component of the compound condition evaluates -+ * to true also if the following additional sub-condition does not hold: -+ * the queue is constantly seeky. Unfortunately, this different behavior -+ * with respect to flash-based devices causes an additional asymmetry: if -+ * some sync queues enjoy idling and some other sync queues do not, then -+ * the latter get a low share of the device throughput, simply because the -+ * former get many requests served after being set as in service, whereas -+ * the latter do not. As a consequence, to guarantee the desired throughput -+ * distribution, on HDDs the compound expression evaluates to true (and -+ * hence device idling is performed) also if the following last symmetry -+ * condition does not hold: no other queue is benefiting from idling. Also -+ * this last condition is actually replaced with a simpler-to-maintain and -+ * stronger condition: there is no busy queue which is not constantly seeky -+ * (and hence may also benefit from idling). -+ * -+ * To sum up, when all the required symmetry and throughput-boosting -+ * sub-conditions hold, the second component of the compound condition -+ * evaluates to false, and hence no idling is performed. This helps to -+ * keep the drives' internal queues full on NCQ-capable devices, and hence -+ * to boost the throughput, without causing 'almost' any loss of service -+ * guarantees. The 'almost' follows from the fact that, if the internal -+ * queue of one such device is filled while all the sub-conditions hold, -+ * but at some point in time some sub-condition stops to hold, then it may -+ * become impossible to let requests be served in the new desired order -+ * until all the requests already queued in the device have been served. -+ */ -+static inline bool bfq_bfqq_must_not_expire(struct bfq_queue *bfqq) -+{ -+ struct bfq_data *bfqd = bfqq->bfqd; -+#ifdef CONFIG_CGROUP_BFQIO -+#define symmetric_scenario (!bfqd->active_numerous_groups && \ -+ !bfq_differentiated_weights(bfqd)) -+#else -+#define symmetric_scenario (!bfq_differentiated_weights(bfqd)) -+#endif -+#define cond_for_seeky_on_ncq_hdd (bfq_bfqq_constantly_seeky(bfqq) && \ -+ bfqd->busy_in_flight_queues == \ -+ bfqd->const_seeky_busy_in_flight_queues) -+ -+#define cond_for_expiring_in_burst (bfq_bfqq_in_large_burst(bfqq) && \ -+ bfqd->hw_tag && \ -+ (blk_queue_nonrot(bfqd->queue) || \ -+ bfq_bfqq_constantly_seeky(bfqq))) -+ -+/* -+ * Condition for expiring a non-weight-raised queue (and hence not idling -+ * the device). -+ */ -+#define cond_for_expiring_non_wr (bfqd->hw_tag && \ -+ (bfqd->wr_busy_queues > 0 || \ -+ (symmetric_scenario && \ -+ (blk_queue_nonrot(bfqd->queue) || \ -+ cond_for_seeky_on_ncq_hdd)))) -+ -+ return bfq_bfqq_sync(bfqq) && -+ !cond_for_expiring_in_burst && -+ (bfqq->wr_coeff > 1 || -+ (bfq_bfqq_IO_bound(bfqq) && bfq_bfqq_idle_window(bfqq) && -+ !cond_for_expiring_non_wr) -+ ); -+} -+ -+/* -+ * If the in-service queue is empty but sync, and the function -+ * bfq_bfqq_must_not_expire returns true, then: -+ * 1) the queue must remain in service and cannot be expired, and -+ * 2) the disk must be idled to wait for the possible arrival of a new -+ * request for the queue. -+ * See the comments to the function bfq_bfqq_must_not_expire for the reasons -+ * why performing device idling is the best choice to boost the throughput -+ * and preserve service guarantees when bfq_bfqq_must_not_expire itself -+ * returns true. -+ */ -+static inline bool bfq_bfqq_must_idle(struct bfq_queue *bfqq) -+{ -+ struct bfq_data *bfqd = bfqq->bfqd; -+ -+ return RB_EMPTY_ROOT(&bfqq->sort_list) && bfqd->bfq_slice_idle != 0 && -+ bfq_bfqq_must_not_expire(bfqq); -+} -+ -+/* -+ * Select a queue for service. If we have a current queue in service, -+ * check whether to continue servicing it, or retrieve and set a new one. -+ */ -+static struct bfq_queue *bfq_select_queue(struct bfq_data *bfqd) -+{ -+ struct bfq_queue *bfqq; -+ struct request *next_rq; -+ enum bfqq_expiration reason = BFQ_BFQQ_BUDGET_TIMEOUT; -+ -+ bfqq = bfqd->in_service_queue; -+ if (bfqq == NULL) -+ goto new_queue; -+ -+ bfq_log_bfqq(bfqd, bfqq, "select_queue: already in-service queue"); -+ -+ if (bfq_may_expire_for_budg_timeout(bfqq) && -+ !timer_pending(&bfqd->idle_slice_timer) && -+ !bfq_bfqq_must_idle(bfqq)) -+ goto expire; -+ -+ next_rq = bfqq->next_rq; -+ /* -+ * If bfqq has requests queued and it has enough budget left to -+ * serve them, keep the queue, otherwise expire it. -+ */ -+ if (next_rq != NULL) { -+ if (bfq_serv_to_charge(next_rq, bfqq) > -+ bfq_bfqq_budget_left(bfqq)) { -+ reason = BFQ_BFQQ_BUDGET_EXHAUSTED; -+ goto expire; -+ } else { -+ /* -+ * The idle timer may be pending because we may -+ * not disable disk idling even when a new request -+ * arrives. -+ */ -+ if (timer_pending(&bfqd->idle_slice_timer)) { -+ /* -+ * If we get here: 1) at least a new request -+ * has arrived but we have not disabled the -+ * timer because the request was too small, -+ * 2) then the block layer has unplugged -+ * the device, causing the dispatch to be -+ * invoked. -+ * -+ * Since the device is unplugged, now the -+ * requests are probably large enough to -+ * provide a reasonable throughput. -+ * So we disable idling. -+ */ -+ bfq_clear_bfqq_wait_request(bfqq); -+ del_timer(&bfqd->idle_slice_timer); -+ } -+ goto keep_queue; -+ } -+ } -+ -+ /* -+ * No requests pending. If the in-service queue still has requests -+ * in flight (possibly waiting for a completion) or is idling for a -+ * new request, then keep it. -+ */ -+ if (timer_pending(&bfqd->idle_slice_timer) || -+ (bfqq->dispatched != 0 && bfq_bfqq_must_not_expire(bfqq))) { -+ bfqq = NULL; -+ goto keep_queue; -+ } -+ -+ reason = BFQ_BFQQ_NO_MORE_REQUESTS; -+expire: -+ bfq_bfqq_expire(bfqd, bfqq, 0, reason); -+new_queue: -+ bfqq = bfq_set_in_service_queue(bfqd); -+ bfq_log(bfqd, "select_queue: new queue %d returned", -+ bfqq != NULL ? bfqq->pid : 0); -+keep_queue: -+ return bfqq; -+} -+ -+static void bfq_update_wr_data(struct bfq_data *bfqd, struct bfq_queue *bfqq) -+{ -+ struct bfq_entity *entity = &bfqq->entity; -+ if (bfqq->wr_coeff > 1) { /* queue is being weight-raised */ -+ bfq_log_bfqq(bfqd, bfqq, -+ "raising period dur %u/%u msec, old coeff %u, w %d(%d)", -+ jiffies_to_msecs(jiffies - bfqq->last_wr_start_finish), -+ jiffies_to_msecs(bfqq->wr_cur_max_time), -+ bfqq->wr_coeff, -+ bfqq->entity.weight, bfqq->entity.orig_weight); -+ -+ BUG_ON(bfqq != bfqd->in_service_queue && entity->weight != -+ entity->orig_weight * bfqq->wr_coeff); -+ if (entity->ioprio_changed) -+ bfq_log_bfqq(bfqd, bfqq, "WARN: pending prio change"); -+ -+ /* -+ * If the queue was activated in a burst, or -+ * too much time has elapsed from the beginning -+ * of this weight-raising period, or the queue has -+ * exceeded the acceptable number of cooperations, -+ * then end weight raising. -+ */ -+ if (bfq_bfqq_in_large_burst(bfqq) || -+ bfq_bfqq_cooperations(bfqq) >= bfqd->bfq_coop_thresh || -+ time_is_before_jiffies(bfqq->last_wr_start_finish + -+ bfqq->wr_cur_max_time)) { -+ bfqq->last_wr_start_finish = jiffies; -+ bfq_log_bfqq(bfqd, bfqq, -+ "wrais ending at %lu, rais_max_time %u", -+ bfqq->last_wr_start_finish, -+ jiffies_to_msecs(bfqq->wr_cur_max_time)); -+ bfq_bfqq_end_wr(bfqq); -+ } -+ } -+ /* Update weight both if it must be raised and if it must be lowered */ -+ if ((entity->weight > entity->orig_weight) != (bfqq->wr_coeff > 1)) -+ __bfq_entity_update_weight_prio( -+ bfq_entity_service_tree(entity), -+ entity); -+} -+ -+/* -+ * Dispatch one request from bfqq, moving it to the request queue -+ * dispatch list. -+ */ -+static int bfq_dispatch_request(struct bfq_data *bfqd, -+ struct bfq_queue *bfqq) -+{ -+ int dispatched = 0; -+ struct request *rq; -+ unsigned long service_to_charge; -+ -+ BUG_ON(RB_EMPTY_ROOT(&bfqq->sort_list)); -+ -+ /* Follow expired path, else get first next available. */ -+ rq = bfq_check_fifo(bfqq); -+ if (rq == NULL) -+ rq = bfqq->next_rq; -+ service_to_charge = bfq_serv_to_charge(rq, bfqq); -+ -+ if (service_to_charge > bfq_bfqq_budget_left(bfqq)) { -+ /* -+ * This may happen if the next rq is chosen in fifo order -+ * instead of sector order. The budget is properly -+ * dimensioned to be always sufficient to serve the next -+ * request only if it is chosen in sector order. The reason -+ * is that it would be quite inefficient and little useful -+ * to always make sure that the budget is large enough to -+ * serve even the possible next rq in fifo order. -+ * In fact, requests are seldom served in fifo order. -+ * -+ * Expire the queue for budget exhaustion, and make sure -+ * that the next act_budget is enough to serve the next -+ * request, even if it comes from the fifo expired path. -+ */ -+ bfqq->next_rq = rq; -+ /* -+ * Since this dispatch is failed, make sure that -+ * a new one will be performed -+ */ -+ if (!bfqd->rq_in_driver) -+ bfq_schedule_dispatch(bfqd); -+ goto expire; -+ } -+ -+ /* Finally, insert request into driver dispatch list. */ -+ bfq_bfqq_served(bfqq, service_to_charge); -+ bfq_dispatch_insert(bfqd->queue, rq); -+ -+ bfq_update_wr_data(bfqd, bfqq); -+ -+ bfq_log_bfqq(bfqd, bfqq, -+ "dispatched %u sec req (%llu), budg left %lu", -+ blk_rq_sectors(rq), -+ (long long unsigned)blk_rq_pos(rq), -+ bfq_bfqq_budget_left(bfqq)); -+ -+ dispatched++; -+ -+ if (bfqd->in_service_bic == NULL) { -+ atomic_long_inc(&RQ_BIC(rq)->icq.ioc->refcount); -+ bfqd->in_service_bic = RQ_BIC(rq); -+ } -+ -+ if (bfqd->busy_queues > 1 && ((!bfq_bfqq_sync(bfqq) && -+ dispatched >= bfqd->bfq_max_budget_async_rq) || -+ bfq_class_idle(bfqq))) -+ goto expire; -+ -+ return dispatched; -+ -+expire: -+ bfq_bfqq_expire(bfqd, bfqq, 0, BFQ_BFQQ_BUDGET_EXHAUSTED); -+ return dispatched; -+} -+ -+static int __bfq_forced_dispatch_bfqq(struct bfq_queue *bfqq) -+{ -+ int dispatched = 0; -+ -+ while (bfqq->next_rq != NULL) { -+ bfq_dispatch_insert(bfqq->bfqd->queue, bfqq->next_rq); -+ dispatched++; -+ } -+ -+ BUG_ON(!list_empty(&bfqq->fifo)); -+ return dispatched; -+} -+ -+/* -+ * Drain our current requests. -+ * Used for barriers and when switching io schedulers on-the-fly. -+ */ -+static int bfq_forced_dispatch(struct bfq_data *bfqd) -+{ -+ struct bfq_queue *bfqq, *n; -+ struct bfq_service_tree *st; -+ int dispatched = 0; -+ -+ bfqq = bfqd->in_service_queue; -+ if (bfqq != NULL) -+ __bfq_bfqq_expire(bfqd, bfqq); -+ -+ /* -+ * Loop through classes, and be careful to leave the scheduler -+ * in a consistent state, as feedback mechanisms and vtime -+ * updates cannot be disabled during the process. -+ */ -+ list_for_each_entry_safe(bfqq, n, &bfqd->active_list, bfqq_list) { -+ st = bfq_entity_service_tree(&bfqq->entity); -+ -+ dispatched += __bfq_forced_dispatch_bfqq(bfqq); -+ bfqq->max_budget = bfq_max_budget(bfqd); -+ -+ bfq_forget_idle(st); -+ } -+ -+ BUG_ON(bfqd->busy_queues != 0); -+ -+ return dispatched; -+} -+ -+static int bfq_dispatch_requests(struct request_queue *q, int force) -+{ -+ struct bfq_data *bfqd = q->elevator->elevator_data; -+ struct bfq_queue *bfqq; -+ int max_dispatch; -+ -+ bfq_log(bfqd, "dispatch requests: %d busy queues", bfqd->busy_queues); -+ if (bfqd->busy_queues == 0) -+ return 0; -+ -+ if (unlikely(force)) -+ return bfq_forced_dispatch(bfqd); -+ -+ bfqq = bfq_select_queue(bfqd); -+ if (bfqq == NULL) -+ return 0; -+ -+ max_dispatch = bfqd->bfq_quantum; -+ if (bfq_class_idle(bfqq)) -+ max_dispatch = 1; -+ -+ if (!bfq_bfqq_sync(bfqq)) -+ max_dispatch = bfqd->bfq_max_budget_async_rq; -+ -+ if (bfqq->dispatched >= max_dispatch) { -+ if (bfqd->busy_queues > 1) -+ return 0; -+ if (bfqq->dispatched >= 4 * max_dispatch) -+ return 0; -+ } -+ -+ if (bfqd->sync_flight != 0 && !bfq_bfqq_sync(bfqq)) -+ return 0; -+ -+ bfq_clear_bfqq_wait_request(bfqq); -+ BUG_ON(timer_pending(&bfqd->idle_slice_timer)); -+ -+ if (!bfq_dispatch_request(bfqd, bfqq)) -+ return 0; -+ -+ bfq_log_bfqq(bfqd, bfqq, "dispatched one request of %d (max_disp %d)", -+ bfqq->pid, max_dispatch); -+ -+ return 1; -+} -+ -+/* -+ * Task holds one reference to the queue, dropped when task exits. Each rq -+ * in-flight on this queue also holds a reference, dropped when rq is freed. -+ * -+ * Queue lock must be held here. -+ */ -+static void bfq_put_queue(struct bfq_queue *bfqq) -+{ -+ struct bfq_data *bfqd = bfqq->bfqd; -+ -+ BUG_ON(atomic_read(&bfqq->ref) <= 0); -+ -+ bfq_log_bfqq(bfqd, bfqq, "put_queue: %p %d", bfqq, -+ atomic_read(&bfqq->ref)); -+ if (!atomic_dec_and_test(&bfqq->ref)) -+ return; -+ -+ BUG_ON(rb_first(&bfqq->sort_list) != NULL); -+ BUG_ON(bfqq->allocated[READ] + bfqq->allocated[WRITE] != 0); -+ BUG_ON(bfqq->entity.tree != NULL); -+ BUG_ON(bfq_bfqq_busy(bfqq)); -+ BUG_ON(bfqd->in_service_queue == bfqq); -+ -+ if (bfq_bfqq_sync(bfqq)) -+ /* -+ * The fact that this queue is being destroyed does not -+ * invalidate the fact that this queue may have been -+ * activated during the current burst. As a consequence, -+ * although the queue does not exist anymore, and hence -+ * needs to be removed from the burst list if there, -+ * the burst size has not to be decremented. -+ */ -+ hlist_del_init(&bfqq->burst_list_node); -+ -+ bfq_log_bfqq(bfqd, bfqq, "put_queue: %p freed", bfqq); -+ -+ kmem_cache_free(bfq_pool, bfqq); -+} -+ -+static void bfq_put_cooperator(struct bfq_queue *bfqq) -+{ -+ struct bfq_queue *__bfqq, *next; -+ -+ /* -+ * If this queue was scheduled to merge with another queue, be -+ * sure to drop the reference taken on that queue (and others in -+ * the merge chain). See bfq_setup_merge and bfq_merge_bfqqs. -+ */ -+ __bfqq = bfqq->new_bfqq; -+ while (__bfqq) { -+ if (__bfqq == bfqq) -+ break; -+ next = __bfqq->new_bfqq; -+ bfq_put_queue(__bfqq); -+ __bfqq = next; -+ } -+} -+ -+static void bfq_exit_bfqq(struct bfq_data *bfqd, struct bfq_queue *bfqq) -+{ -+ if (bfqq == bfqd->in_service_queue) { -+ __bfq_bfqq_expire(bfqd, bfqq); -+ bfq_schedule_dispatch(bfqd); -+ } -+ -+ bfq_log_bfqq(bfqd, bfqq, "exit_bfqq: %p, %d", bfqq, -+ atomic_read(&bfqq->ref)); -+ -+ bfq_put_cooperator(bfqq); -+ -+ bfq_put_queue(bfqq); -+} -+ -+static inline void bfq_init_icq(struct io_cq *icq) -+{ -+ struct bfq_io_cq *bic = icq_to_bic(icq); -+ -+ bic->ttime.last_end_request = jiffies; -+ /* -+ * A newly created bic indicates that the process has just -+ * started doing I/O, and is probably mapping into memory its -+ * executable and libraries: it definitely needs weight raising. -+ * There is however the possibility that the process performs, -+ * for a while, I/O close to some other process. EQM intercepts -+ * this behavior and may merge the queue corresponding to the -+ * process with some other queue, BEFORE the weight of the queue -+ * is raised. Merged queues are not weight-raised (they are assumed -+ * to belong to processes that benefit only from high throughput). -+ * If the merge is basically the consequence of an accident, then -+ * the queue will be split soon and will get back its old weight. -+ * It is then important to write down somewhere that this queue -+ * does need weight raising, even if it did not make it to get its -+ * weight raised before being merged. To this purpose, we overload -+ * the field raising_time_left and assign 1 to it, to mark the queue -+ * as needing weight raising. -+ */ -+ bic->wr_time_left = 1; -+} -+ -+static void bfq_exit_icq(struct io_cq *icq) -+{ -+ struct bfq_io_cq *bic = icq_to_bic(icq); -+ struct bfq_data *bfqd = bic_to_bfqd(bic); -+ -+ if (bic->bfqq[BLK_RW_ASYNC]) { -+ bfq_exit_bfqq(bfqd, bic->bfqq[BLK_RW_ASYNC]); -+ bic->bfqq[BLK_RW_ASYNC] = NULL; -+ } -+ -+ if (bic->bfqq[BLK_RW_SYNC]) { -+ /* -+ * If the bic is using a shared queue, put the reference -+ * taken on the io_context when the bic started using a -+ * shared bfq_queue. -+ */ -+ if (bfq_bfqq_coop(bic->bfqq[BLK_RW_SYNC])) -+ put_io_context(icq->ioc); -+ bfq_exit_bfqq(bfqd, bic->bfqq[BLK_RW_SYNC]); -+ bic->bfqq[BLK_RW_SYNC] = NULL; -+ } -+} -+ -+/* -+ * Update the entity prio values; note that the new values will not -+ * be used until the next (re)activation. -+ */ -+static void bfq_init_prio_data(struct bfq_queue *bfqq, struct bfq_io_cq *bic) -+{ -+ struct task_struct *tsk = current; -+ int ioprio_class; -+ -+ if (!bfq_bfqq_prio_changed(bfqq)) -+ return; -+ -+ ioprio_class = IOPRIO_PRIO_CLASS(bic->ioprio); -+ switch (ioprio_class) { -+ default: -+ dev_err(bfqq->bfqd->queue->backing_dev_info.dev, -+ "bfq: bad prio class %d\n", ioprio_class); -+ case IOPRIO_CLASS_NONE: -+ /* -+ * No prio set, inherit CPU scheduling settings. -+ */ -+ bfqq->entity.new_ioprio = task_nice_ioprio(tsk); -+ bfqq->entity.new_ioprio_class = task_nice_ioclass(tsk); -+ break; -+ case IOPRIO_CLASS_RT: -+ bfqq->entity.new_ioprio = IOPRIO_PRIO_DATA(bic->ioprio); -+ bfqq->entity.new_ioprio_class = IOPRIO_CLASS_RT; -+ break; -+ case IOPRIO_CLASS_BE: -+ bfqq->entity.new_ioprio = IOPRIO_PRIO_DATA(bic->ioprio); -+ bfqq->entity.new_ioprio_class = IOPRIO_CLASS_BE; -+ break; -+ case IOPRIO_CLASS_IDLE: -+ bfqq->entity.new_ioprio_class = IOPRIO_CLASS_IDLE; -+ bfqq->entity.new_ioprio = 7; -+ bfq_clear_bfqq_idle_window(bfqq); -+ break; -+ } -+ -+ if (bfqq->entity.new_ioprio < 0 || -+ bfqq->entity.new_ioprio >= IOPRIO_BE_NR) { -+ printk(KERN_CRIT "bfq_init_prio_data: new_ioprio %d\n", -+ bfqq->entity.new_ioprio); -+ BUG(); -+ } -+ -+ bfqq->entity.ioprio_changed = 1; -+ -+ bfq_clear_bfqq_prio_changed(bfqq); -+} -+ -+static void bfq_changed_ioprio(struct bfq_io_cq *bic) -+{ -+ struct bfq_data *bfqd; -+ struct bfq_queue *bfqq, *new_bfqq; -+ struct bfq_group *bfqg; -+ unsigned long uninitialized_var(flags); -+ int ioprio = bic->icq.ioc->ioprio; -+ -+ bfqd = bfq_get_bfqd_locked(&(bic->icq.q->elevator->elevator_data), -+ &flags); -+ /* -+ * This condition may trigger on a newly created bic, be sure to -+ * drop the lock before returning. -+ */ -+ if (unlikely(bfqd == NULL) || likely(bic->ioprio == ioprio)) -+ goto out; -+ -+ bfqq = bic->bfqq[BLK_RW_ASYNC]; -+ if (bfqq != NULL) { -+ bfqg = container_of(bfqq->entity.sched_data, struct bfq_group, -+ sched_data); -+ new_bfqq = bfq_get_queue(bfqd, bfqg, BLK_RW_ASYNC, bic, -+ GFP_ATOMIC); -+ if (new_bfqq != NULL) { -+ bic->bfqq[BLK_RW_ASYNC] = new_bfqq; -+ bfq_log_bfqq(bfqd, bfqq, -+ "changed_ioprio: bfqq %p %d", -+ bfqq, atomic_read(&bfqq->ref)); -+ bfq_put_queue(bfqq); -+ } -+ } -+ -+ bfqq = bic->bfqq[BLK_RW_SYNC]; -+ if (bfqq != NULL) -+ bfq_mark_bfqq_prio_changed(bfqq); -+ -+ bic->ioprio = ioprio; -+ -+out: -+ bfq_put_bfqd_unlock(bfqd, &flags); -+} -+ -+static void bfq_init_bfqq(struct bfq_data *bfqd, struct bfq_queue *bfqq, -+ pid_t pid, int is_sync) -+{ -+ RB_CLEAR_NODE(&bfqq->entity.rb_node); -+ INIT_LIST_HEAD(&bfqq->fifo); -+ INIT_HLIST_NODE(&bfqq->burst_list_node); -+ -+ atomic_set(&bfqq->ref, 0); -+ bfqq->bfqd = bfqd; -+ -+ bfq_mark_bfqq_prio_changed(bfqq); -+ -+ if (is_sync) { -+ if (!bfq_class_idle(bfqq)) -+ bfq_mark_bfqq_idle_window(bfqq); -+ bfq_mark_bfqq_sync(bfqq); -+ } -+ bfq_mark_bfqq_IO_bound(bfqq); -+ -+ /* Tentative initial value to trade off between thr and lat */ -+ bfqq->max_budget = (2 * bfq_max_budget(bfqd)) / 3; -+ bfqq->pid = pid; -+ -+ bfqq->wr_coeff = 1; -+ bfqq->last_wr_start_finish = 0; -+ /* -+ * Set to the value for which bfqq will not be deemed as -+ * soft rt when it becomes backlogged. -+ */ -+ bfqq->soft_rt_next_start = bfq_infinity_from_now(jiffies); -+} -+ -+static struct bfq_queue *bfq_find_alloc_queue(struct bfq_data *bfqd, -+ struct bfq_group *bfqg, -+ int is_sync, -+ struct bfq_io_cq *bic, -+ gfp_t gfp_mask) -+{ -+ struct bfq_queue *bfqq, *new_bfqq = NULL; -+ -+retry: -+ /* bic always exists here */ -+ bfqq = bic_to_bfqq(bic, is_sync); -+ -+ /* -+ * Always try a new alloc if we fall back to the OOM bfqq -+ * originally, since it should just be a temporary situation. -+ */ -+ if (bfqq == NULL || bfqq == &bfqd->oom_bfqq) { -+ bfqq = NULL; -+ if (new_bfqq != NULL) { -+ bfqq = new_bfqq; -+ new_bfqq = NULL; -+ } else if (gfp_mask & __GFP_WAIT) { -+ spin_unlock_irq(bfqd->queue->queue_lock); -+ new_bfqq = kmem_cache_alloc_node(bfq_pool, -+ gfp_mask | __GFP_ZERO, -+ bfqd->queue->node); -+ spin_lock_irq(bfqd->queue->queue_lock); -+ if (new_bfqq != NULL) -+ goto retry; -+ } else { -+ bfqq = kmem_cache_alloc_node(bfq_pool, -+ gfp_mask | __GFP_ZERO, -+ bfqd->queue->node); -+ } -+ -+ if (bfqq != NULL) { -+ bfq_init_bfqq(bfqd, bfqq, current->pid, is_sync); -+ bfq_init_prio_data(bfqq, bic); -+ bfq_init_entity(&bfqq->entity, bfqg); -+ bfq_log_bfqq(bfqd, bfqq, "allocated"); -+ } else { -+ bfqq = &bfqd->oom_bfqq; -+ bfq_log_bfqq(bfqd, bfqq, "using oom bfqq"); -+ } -+ } -+ -+ if (new_bfqq != NULL) -+ kmem_cache_free(bfq_pool, new_bfqq); -+ -+ return bfqq; -+} -+ -+static struct bfq_queue **bfq_async_queue_prio(struct bfq_data *bfqd, -+ struct bfq_group *bfqg, -+ int ioprio_class, int ioprio) -+{ -+ switch (ioprio_class) { -+ case IOPRIO_CLASS_RT: -+ return &bfqg->async_bfqq[0][ioprio]; -+ case IOPRIO_CLASS_NONE: -+ ioprio = IOPRIO_NORM; -+ /* fall through */ -+ case IOPRIO_CLASS_BE: -+ return &bfqg->async_bfqq[1][ioprio]; -+ case IOPRIO_CLASS_IDLE: -+ return &bfqg->async_idle_bfqq; -+ default: -+ BUG(); -+ } -+} -+ -+static struct bfq_queue *bfq_get_queue(struct bfq_data *bfqd, -+ struct bfq_group *bfqg, int is_sync, -+ struct bfq_io_cq *bic, gfp_t gfp_mask) -+{ -+ const int ioprio = IOPRIO_PRIO_DATA(bic->ioprio); -+ const int ioprio_class = IOPRIO_PRIO_CLASS(bic->ioprio); -+ struct bfq_queue **async_bfqq = NULL; -+ struct bfq_queue *bfqq = NULL; -+ -+ if (!is_sync) { -+ async_bfqq = bfq_async_queue_prio(bfqd, bfqg, ioprio_class, -+ ioprio); -+ bfqq = *async_bfqq; -+ } -+ -+ if (bfqq == NULL) -+ bfqq = bfq_find_alloc_queue(bfqd, bfqg, is_sync, bic, gfp_mask); -+ -+ /* -+ * Pin the queue now that it's allocated, scheduler exit will -+ * prune it. -+ */ -+ if (!is_sync && *async_bfqq == NULL) { -+ atomic_inc(&bfqq->ref); -+ bfq_log_bfqq(bfqd, bfqq, "get_queue, bfqq not in async: %p, %d", -+ bfqq, atomic_read(&bfqq->ref)); -+ *async_bfqq = bfqq; -+ } -+ -+ atomic_inc(&bfqq->ref); -+ bfq_log_bfqq(bfqd, bfqq, "get_queue, at end: %p, %d", bfqq, -+ atomic_read(&bfqq->ref)); -+ return bfqq; -+} -+ -+static void bfq_update_io_thinktime(struct bfq_data *bfqd, -+ struct bfq_io_cq *bic) -+{ -+ unsigned long elapsed = jiffies - bic->ttime.last_end_request; -+ unsigned long ttime = min(elapsed, 2UL * bfqd->bfq_slice_idle); -+ -+ bic->ttime.ttime_samples = (7*bic->ttime.ttime_samples + 256) / 8; -+ bic->ttime.ttime_total = (7*bic->ttime.ttime_total + 256*ttime) / 8; -+ bic->ttime.ttime_mean = (bic->ttime.ttime_total + 128) / -+ bic->ttime.ttime_samples; -+} -+ -+static void bfq_update_io_seektime(struct bfq_data *bfqd, -+ struct bfq_queue *bfqq, -+ struct request *rq) -+{ -+ sector_t sdist; -+ u64 total; -+ -+ if (bfqq->last_request_pos < blk_rq_pos(rq)) -+ sdist = blk_rq_pos(rq) - bfqq->last_request_pos; -+ else -+ sdist = bfqq->last_request_pos - blk_rq_pos(rq); -+ -+ /* -+ * Don't allow the seek distance to get too large from the -+ * odd fragment, pagein, etc. -+ */ -+ if (bfqq->seek_samples == 0) /* first request, not really a seek */ -+ sdist = 0; -+ else if (bfqq->seek_samples <= 60) /* second & third seek */ -+ sdist = min(sdist, (bfqq->seek_mean * 4) + 2*1024*1024); -+ else -+ sdist = min(sdist, (bfqq->seek_mean * 4) + 2*1024*64); -+ -+ bfqq->seek_samples = (7*bfqq->seek_samples + 256) / 8; -+ bfqq->seek_total = (7*bfqq->seek_total + (u64)256*sdist) / 8; -+ total = bfqq->seek_total + (bfqq->seek_samples/2); -+ do_div(total, bfqq->seek_samples); -+ bfqq->seek_mean = (sector_t)total; -+ -+ bfq_log_bfqq(bfqd, bfqq, "dist=%llu mean=%llu", (u64)sdist, -+ (u64)bfqq->seek_mean); -+} -+ -+/* -+ * Disable idle window if the process thinks too long or seeks so much that -+ * it doesn't matter. -+ */ -+static void bfq_update_idle_window(struct bfq_data *bfqd, -+ struct bfq_queue *bfqq, -+ struct bfq_io_cq *bic) -+{ -+ int enable_idle; -+ -+ /* Don't idle for async or idle io prio class. */ -+ if (!bfq_bfqq_sync(bfqq) || bfq_class_idle(bfqq)) -+ return; -+ -+ /* Idle window just restored, statistics are meaningless. */ -+ if (bfq_bfqq_just_split(bfqq)) -+ return; -+ -+ enable_idle = bfq_bfqq_idle_window(bfqq); -+ -+ if (atomic_read(&bic->icq.ioc->active_ref) == 0 || -+ bfqd->bfq_slice_idle == 0 || -+ (bfqd->hw_tag && BFQQ_SEEKY(bfqq) && -+ bfqq->wr_coeff == 1)) -+ enable_idle = 0; -+ else if (bfq_sample_valid(bic->ttime.ttime_samples)) { -+ if (bic->ttime.ttime_mean > bfqd->bfq_slice_idle && -+ bfqq->wr_coeff == 1) -+ enable_idle = 0; -+ else -+ enable_idle = 1; -+ } -+ bfq_log_bfqq(bfqd, bfqq, "update_idle_window: enable_idle %d", -+ enable_idle); -+ -+ if (enable_idle) -+ bfq_mark_bfqq_idle_window(bfqq); -+ else -+ bfq_clear_bfqq_idle_window(bfqq); -+} -+ -+/* -+ * Called when a new fs request (rq) is added to bfqq. Check if there's -+ * something we should do about it. -+ */ -+static void bfq_rq_enqueued(struct bfq_data *bfqd, struct bfq_queue *bfqq, -+ struct request *rq) -+{ -+ struct bfq_io_cq *bic = RQ_BIC(rq); -+ -+ if (rq->cmd_flags & REQ_META) -+ bfqq->meta_pending++; -+ -+ bfq_update_io_thinktime(bfqd, bic); -+ bfq_update_io_seektime(bfqd, bfqq, rq); -+ if (!BFQQ_SEEKY(bfqq) && bfq_bfqq_constantly_seeky(bfqq)) { -+ bfq_clear_bfqq_constantly_seeky(bfqq); -+ if (!blk_queue_nonrot(bfqd->queue)) { -+ BUG_ON(!bfqd->const_seeky_busy_in_flight_queues); -+ bfqd->const_seeky_busy_in_flight_queues--; -+ } -+ } -+ if (bfqq->entity.service > bfq_max_budget(bfqd) / 8 || -+ !BFQQ_SEEKY(bfqq)) -+ bfq_update_idle_window(bfqd, bfqq, bic); -+ bfq_clear_bfqq_just_split(bfqq); -+ -+ bfq_log_bfqq(bfqd, bfqq, -+ "rq_enqueued: idle_window=%d (seeky %d, mean %llu)", -+ bfq_bfqq_idle_window(bfqq), BFQQ_SEEKY(bfqq), -+ (long long unsigned)bfqq->seek_mean); -+ -+ bfqq->last_request_pos = blk_rq_pos(rq) + blk_rq_sectors(rq); -+ -+ if (bfqq == bfqd->in_service_queue && bfq_bfqq_wait_request(bfqq)) { -+ int small_req = bfqq->queued[rq_is_sync(rq)] == 1 && -+ blk_rq_sectors(rq) < 32; -+ int budget_timeout = bfq_bfqq_budget_timeout(bfqq); -+ -+ /* -+ * There is just this request queued: if the request -+ * is small and the queue is not to be expired, then -+ * just exit. -+ * -+ * In this way, if the disk is being idled to wait for -+ * a new request from the in-service queue, we avoid -+ * unplugging the device and committing the disk to serve -+ * just a small request. On the contrary, we wait for -+ * the block layer to decide when to unplug the device: -+ * hopefully, new requests will be merged to this one -+ * quickly, then the device will be unplugged and -+ * larger requests will be dispatched. -+ */ -+ if (small_req && !budget_timeout) -+ return; -+ -+ /* -+ * A large enough request arrived, or the queue is to -+ * be expired: in both cases disk idling is to be -+ * stopped, so clear wait_request flag and reset -+ * timer. -+ */ -+ bfq_clear_bfqq_wait_request(bfqq); -+ del_timer(&bfqd->idle_slice_timer); -+ -+ /* -+ * The queue is not empty, because a new request just -+ * arrived. Hence we can safely expire the queue, in -+ * case of budget timeout, without risking that the -+ * timestamps of the queue are not updated correctly. -+ * See [1] for more details. -+ */ -+ if (budget_timeout) -+ bfq_bfqq_expire(bfqd, bfqq, 0, BFQ_BFQQ_BUDGET_TIMEOUT); -+ -+ /* -+ * Let the request rip immediately, or let a new queue be -+ * selected if bfqq has just been expired. -+ */ -+ __blk_run_queue(bfqd->queue); -+ } -+} -+ -+static void bfq_insert_request(struct request_queue *q, struct request *rq) -+{ -+ struct bfq_data *bfqd = q->elevator->elevator_data; -+ struct bfq_queue *bfqq = RQ_BFQQ(rq), *new_bfqq; -+ -+ assert_spin_locked(bfqd->queue->queue_lock); -+ -+ /* -+ * An unplug may trigger a requeue of a request from the device -+ * driver: make sure we are in process context while trying to -+ * merge two bfq_queues. -+ */ -+ if (!in_interrupt()) { -+ new_bfqq = bfq_setup_cooperator(bfqd, bfqq, rq, true); -+ if (new_bfqq != NULL) { -+ if (bic_to_bfqq(RQ_BIC(rq), 1) != bfqq) -+ new_bfqq = bic_to_bfqq(RQ_BIC(rq), 1); -+ /* -+ * Release the request's reference to the old bfqq -+ * and make sure one is taken to the shared queue. -+ */ -+ new_bfqq->allocated[rq_data_dir(rq)]++; -+ bfqq->allocated[rq_data_dir(rq)]--; -+ atomic_inc(&new_bfqq->ref); -+ bfq_put_queue(bfqq); -+ if (bic_to_bfqq(RQ_BIC(rq), 1) == bfqq) -+ bfq_merge_bfqqs(bfqd, RQ_BIC(rq), -+ bfqq, new_bfqq); -+ rq->elv.priv[1] = new_bfqq; -+ bfqq = new_bfqq; -+ } else -+ bfq_bfqq_increase_failed_cooperations(bfqq); -+ } -+ -+ bfq_init_prio_data(bfqq, RQ_BIC(rq)); -+ -+ bfq_add_request(rq); -+ -+ /* -+ * Here a newly-created bfq_queue has already started a weight-raising -+ * period: clear raising_time_left to prevent bfq_bfqq_save_state() -+ * from assigning it a full weight-raising period. See the detailed -+ * comments about this field in bfq_init_icq(). -+ */ -+ if (bfqq->bic != NULL) -+ bfqq->bic->wr_time_left = 0; -+ rq->fifo_time = jiffies + bfqd->bfq_fifo_expire[rq_is_sync(rq)]; -+ list_add_tail(&rq->queuelist, &bfqq->fifo); -+ -+ bfq_rq_enqueued(bfqd, bfqq, rq); -+} -+ -+static void bfq_update_hw_tag(struct bfq_data *bfqd) -+{ -+ bfqd->max_rq_in_driver = max(bfqd->max_rq_in_driver, -+ bfqd->rq_in_driver); -+ -+ if (bfqd->hw_tag == 1) -+ return; -+ -+ /* -+ * This sample is valid if the number of outstanding requests -+ * is large enough to allow a queueing behavior. Note that the -+ * sum is not exact, as it's not taking into account deactivated -+ * requests. -+ */ -+ if (bfqd->rq_in_driver + bfqd->queued < BFQ_HW_QUEUE_THRESHOLD) -+ return; -+ -+ if (bfqd->hw_tag_samples++ < BFQ_HW_QUEUE_SAMPLES) -+ return; -+ -+ bfqd->hw_tag = bfqd->max_rq_in_driver > BFQ_HW_QUEUE_THRESHOLD; -+ bfqd->max_rq_in_driver = 0; -+ bfqd->hw_tag_samples = 0; -+} -+ -+static void bfq_completed_request(struct request_queue *q, struct request *rq) -+{ -+ struct bfq_queue *bfqq = RQ_BFQQ(rq); -+ struct bfq_data *bfqd = bfqq->bfqd; -+ bool sync = bfq_bfqq_sync(bfqq); -+ -+ bfq_log_bfqq(bfqd, bfqq, "completed one req with %u sects left (%d)", -+ blk_rq_sectors(rq), sync); -+ -+ bfq_update_hw_tag(bfqd); -+ -+ BUG_ON(!bfqd->rq_in_driver); -+ BUG_ON(!bfqq->dispatched); -+ bfqd->rq_in_driver--; -+ bfqq->dispatched--; -+ -+ if (!bfqq->dispatched && !bfq_bfqq_busy(bfqq)) { -+ bfq_weights_tree_remove(bfqd, &bfqq->entity, -+ &bfqd->queue_weights_tree); -+ if (!blk_queue_nonrot(bfqd->queue)) { -+ BUG_ON(!bfqd->busy_in_flight_queues); -+ bfqd->busy_in_flight_queues--; -+ if (bfq_bfqq_constantly_seeky(bfqq)) { -+ BUG_ON(!bfqd-> -+ const_seeky_busy_in_flight_queues); -+ bfqd->const_seeky_busy_in_flight_queues--; -+ } -+ } -+ } -+ -+ if (sync) { -+ bfqd->sync_flight--; -+ RQ_BIC(rq)->ttime.last_end_request = jiffies; -+ } -+ -+ /* -+ * If we are waiting to discover whether the request pattern of the -+ * task associated with the queue is actually isochronous, and -+ * both requisites for this condition to hold are satisfied, then -+ * compute soft_rt_next_start (see the comments to the function -+ * bfq_bfqq_softrt_next_start()). -+ */ -+ if (bfq_bfqq_softrt_update(bfqq) && bfqq->dispatched == 0 && -+ RB_EMPTY_ROOT(&bfqq->sort_list)) -+ bfqq->soft_rt_next_start = -+ bfq_bfqq_softrt_next_start(bfqd, bfqq); -+ -+ /* -+ * If this is the in-service queue, check if it needs to be expired, -+ * or if we want to idle in case it has no pending requests. -+ */ -+ if (bfqd->in_service_queue == bfqq) { -+ if (bfq_bfqq_budget_new(bfqq)) -+ bfq_set_budget_timeout(bfqd); -+ -+ if (bfq_bfqq_must_idle(bfqq)) { -+ bfq_arm_slice_timer(bfqd); -+ goto out; -+ } else if (bfq_may_expire_for_budg_timeout(bfqq)) -+ bfq_bfqq_expire(bfqd, bfqq, 0, BFQ_BFQQ_BUDGET_TIMEOUT); -+ else if (RB_EMPTY_ROOT(&bfqq->sort_list) && -+ (bfqq->dispatched == 0 || -+ !bfq_bfqq_must_not_expire(bfqq))) -+ bfq_bfqq_expire(bfqd, bfqq, 0, -+ BFQ_BFQQ_NO_MORE_REQUESTS); -+ } -+ -+ if (!bfqd->rq_in_driver) -+ bfq_schedule_dispatch(bfqd); -+ -+out: -+ return; -+} -+ -+static inline int __bfq_may_queue(struct bfq_queue *bfqq) -+{ -+ if (bfq_bfqq_wait_request(bfqq) && bfq_bfqq_must_alloc(bfqq)) { -+ bfq_clear_bfqq_must_alloc(bfqq); -+ return ELV_MQUEUE_MUST; -+ } -+ -+ return ELV_MQUEUE_MAY; -+} -+ -+static int bfq_may_queue(struct request_queue *q, int rw) -+{ -+ struct bfq_data *bfqd = q->elevator->elevator_data; -+ struct task_struct *tsk = current; -+ struct bfq_io_cq *bic; -+ struct bfq_queue *bfqq; -+ -+ /* -+ * Don't force setup of a queue from here, as a call to may_queue -+ * does not necessarily imply that a request actually will be -+ * queued. So just lookup a possibly existing queue, or return -+ * 'may queue' if that fails. -+ */ -+ bic = bfq_bic_lookup(bfqd, tsk->io_context); -+ if (bic == NULL) -+ return ELV_MQUEUE_MAY; -+ -+ bfqq = bic_to_bfqq(bic, rw_is_sync(rw)); -+ if (bfqq != NULL) { -+ bfq_init_prio_data(bfqq, bic); -+ -+ return __bfq_may_queue(bfqq); -+ } -+ -+ return ELV_MQUEUE_MAY; -+} -+ -+/* -+ * Queue lock held here. -+ */ -+static void bfq_put_request(struct request *rq) -+{ -+ struct bfq_queue *bfqq = RQ_BFQQ(rq); -+ -+ if (bfqq != NULL) { -+ const int rw = rq_data_dir(rq); -+ -+ BUG_ON(!bfqq->allocated[rw]); -+ bfqq->allocated[rw]--; -+ -+ rq->elv.priv[0] = NULL; -+ rq->elv.priv[1] = NULL; -+ -+ bfq_log_bfqq(bfqq->bfqd, bfqq, "put_request %p, %d", -+ bfqq, atomic_read(&bfqq->ref)); -+ bfq_put_queue(bfqq); -+ } -+} -+ -+/* -+ * Returns NULL if a new bfqq should be allocated, or the old bfqq if this -+ * was the last process referring to said bfqq. -+ */ -+static struct bfq_queue * -+bfq_split_bfqq(struct bfq_io_cq *bic, struct bfq_queue *bfqq) -+{ -+ bfq_log_bfqq(bfqq->bfqd, bfqq, "splitting queue"); -+ -+ put_io_context(bic->icq.ioc); -+ -+ if (bfqq_process_refs(bfqq) == 1) { -+ bfqq->pid = current->pid; -+ bfq_clear_bfqq_coop(bfqq); -+ bfq_clear_bfqq_split_coop(bfqq); -+ return bfqq; -+ } -+ -+ bic_set_bfqq(bic, NULL, 1); -+ -+ bfq_put_cooperator(bfqq); -+ -+ bfq_put_queue(bfqq); -+ return NULL; -+} -+ -+/* -+ * Allocate bfq data structures associated with this request. -+ */ -+static int bfq_set_request(struct request_queue *q, struct request *rq, -+ struct bio *bio, gfp_t gfp_mask) -+{ -+ struct bfq_data *bfqd = q->elevator->elevator_data; -+ struct bfq_io_cq *bic = icq_to_bic(rq->elv.icq); -+ const int rw = rq_data_dir(rq); -+ const int is_sync = rq_is_sync(rq); -+ struct bfq_queue *bfqq; -+ struct bfq_group *bfqg; -+ unsigned long flags; -+ bool split = false; -+ -+ might_sleep_if(gfp_mask & __GFP_WAIT); -+ -+ bfq_changed_ioprio(bic); -+ -+ spin_lock_irqsave(q->queue_lock, flags); -+ -+ if (bic == NULL) -+ goto queue_fail; -+ -+ bfqg = bfq_bic_update_cgroup(bic); -+ -+new_queue: -+ bfqq = bic_to_bfqq(bic, is_sync); -+ if (bfqq == NULL || bfqq == &bfqd->oom_bfqq) { -+ bfqq = bfq_get_queue(bfqd, bfqg, is_sync, bic, gfp_mask); -+ bic_set_bfqq(bic, bfqq, is_sync); -+ if (split && is_sync) { -+ if ((bic->was_in_burst_list && bfqd->large_burst) || -+ bic->saved_in_large_burst) -+ bfq_mark_bfqq_in_large_burst(bfqq); -+ else { -+ bfq_clear_bfqq_in_large_burst(bfqq); -+ if (bic->was_in_burst_list) -+ hlist_add_head(&bfqq->burst_list_node, -+ &bfqd->burst_list); -+ } -+ } -+ } else { -+ /* If the queue was seeky for too long, break it apart. */ -+ if (bfq_bfqq_coop(bfqq) && bfq_bfqq_split_coop(bfqq)) { -+ bfq_log_bfqq(bfqd, bfqq, "breaking apart bfqq"); -+ bfqq = bfq_split_bfqq(bic, bfqq); -+ split = true; -+ if (!bfqq) -+ goto new_queue; -+ } -+ } -+ -+ bfqq->allocated[rw]++; -+ atomic_inc(&bfqq->ref); -+ bfq_log_bfqq(bfqd, bfqq, "set_request: bfqq %p, %d", bfqq, -+ atomic_read(&bfqq->ref)); -+ -+ rq->elv.priv[0] = bic; -+ rq->elv.priv[1] = bfqq; -+ -+ /* -+ * If a bfq_queue has only one process reference, it is owned -+ * by only one bfq_io_cq: we can set the bic field of the -+ * bfq_queue to the address of that structure. Also, if the -+ * queue has just been split, mark a flag so that the -+ * information is available to the other scheduler hooks. -+ */ -+ if (likely(bfqq != &bfqd->oom_bfqq) && bfqq_process_refs(bfqq) == 1) { -+ bfqq->bic = bic; -+ if (split) { -+ bfq_mark_bfqq_just_split(bfqq); -+ /* -+ * If the queue has just been split from a shared -+ * queue, restore the idle window and the possible -+ * weight raising period. -+ */ -+ bfq_bfqq_resume_state(bfqq, bic); -+ } -+ } -+ -+ spin_unlock_irqrestore(q->queue_lock, flags); -+ -+ return 0; -+ -+queue_fail: -+ bfq_schedule_dispatch(bfqd); -+ spin_unlock_irqrestore(q->queue_lock, flags); -+ -+ return 1; -+} -+ -+static void bfq_kick_queue(struct work_struct *work) -+{ -+ struct bfq_data *bfqd = -+ container_of(work, struct bfq_data, unplug_work); -+ struct request_queue *q = bfqd->queue; -+ -+ spin_lock_irq(q->queue_lock); -+ __blk_run_queue(q); -+ spin_unlock_irq(q->queue_lock); -+} -+ -+/* -+ * Handler of the expiration of the timer running if the in-service queue -+ * is idling inside its time slice. -+ */ -+static void bfq_idle_slice_timer(unsigned long data) -+{ -+ struct bfq_data *bfqd = (struct bfq_data *)data; -+ struct bfq_queue *bfqq; -+ unsigned long flags; -+ enum bfqq_expiration reason; -+ -+ spin_lock_irqsave(bfqd->queue->queue_lock, flags); -+ -+ bfqq = bfqd->in_service_queue; -+ /* -+ * Theoretical race here: the in-service queue can be NULL or -+ * different from the queue that was idling if the timer handler -+ * spins on the queue_lock and a new request arrives for the -+ * current queue and there is a full dispatch cycle that changes -+ * the in-service queue. This can hardly happen, but in the worst -+ * case we just expire a queue too early. -+ */ -+ if (bfqq != NULL) { -+ bfq_log_bfqq(bfqd, bfqq, "slice_timer expired"); -+ if (bfq_bfqq_budget_timeout(bfqq)) -+ /* -+ * Also here the queue can be safely expired -+ * for budget timeout without wasting -+ * guarantees -+ */ -+ reason = BFQ_BFQQ_BUDGET_TIMEOUT; -+ else if (bfqq->queued[0] == 0 && bfqq->queued[1] == 0) -+ /* -+ * The queue may not be empty upon timer expiration, -+ * because we may not disable the timer when the -+ * first request of the in-service queue arrives -+ * during disk idling. -+ */ -+ reason = BFQ_BFQQ_TOO_IDLE; -+ else -+ goto schedule_dispatch; -+ -+ bfq_bfqq_expire(bfqd, bfqq, 1, reason); -+ } -+ -+schedule_dispatch: -+ bfq_schedule_dispatch(bfqd); -+ -+ spin_unlock_irqrestore(bfqd->queue->queue_lock, flags); -+} -+ -+static void bfq_shutdown_timer_wq(struct bfq_data *bfqd) -+{ -+ del_timer_sync(&bfqd->idle_slice_timer); -+ cancel_work_sync(&bfqd->unplug_work); -+} -+ -+static inline void __bfq_put_async_bfqq(struct bfq_data *bfqd, -+ struct bfq_queue **bfqq_ptr) -+{ -+ struct bfq_group *root_group = bfqd->root_group; -+ struct bfq_queue *bfqq = *bfqq_ptr; -+ -+ bfq_log(bfqd, "put_async_bfqq: %p", bfqq); -+ if (bfqq != NULL) { -+ bfq_bfqq_move(bfqd, bfqq, &bfqq->entity, root_group); -+ bfq_log_bfqq(bfqd, bfqq, "put_async_bfqq: putting %p, %d", -+ bfqq, atomic_read(&bfqq->ref)); -+ bfq_put_queue(bfqq); -+ *bfqq_ptr = NULL; -+ } -+} -+ -+/* -+ * Release all the bfqg references to its async queues. If we are -+ * deallocating the group these queues may still contain requests, so -+ * we reparent them to the root cgroup (i.e., the only one that will -+ * exist for sure until all the requests on a device are gone). -+ */ -+static void bfq_put_async_queues(struct bfq_data *bfqd, struct bfq_group *bfqg) -+{ -+ int i, j; -+ -+ for (i = 0; i < 2; i++) -+ for (j = 0; j < IOPRIO_BE_NR; j++) -+ __bfq_put_async_bfqq(bfqd, &bfqg->async_bfqq[i][j]); -+ -+ __bfq_put_async_bfqq(bfqd, &bfqg->async_idle_bfqq); -+} -+ -+static void bfq_exit_queue(struct elevator_queue *e) -+{ -+ struct bfq_data *bfqd = e->elevator_data; -+ struct request_queue *q = bfqd->queue; -+ struct bfq_queue *bfqq, *n; -+ -+ bfq_shutdown_timer_wq(bfqd); -+ -+ spin_lock_irq(q->queue_lock); -+ -+ BUG_ON(bfqd->in_service_queue != NULL); -+ list_for_each_entry_safe(bfqq, n, &bfqd->idle_list, bfqq_list) -+ bfq_deactivate_bfqq(bfqd, bfqq, 0); -+ -+ bfq_disconnect_groups(bfqd); -+ spin_unlock_irq(q->queue_lock); -+ -+ bfq_shutdown_timer_wq(bfqd); -+ -+ synchronize_rcu(); -+ -+ BUG_ON(timer_pending(&bfqd->idle_slice_timer)); -+ -+ bfq_free_root_group(bfqd); -+ kfree(bfqd); -+} -+ -+static int bfq_init_queue(struct request_queue *q, struct elevator_type *e) -+{ -+ struct bfq_group *bfqg; -+ struct bfq_data *bfqd; -+ struct elevator_queue *eq; -+ -+ eq = elevator_alloc(q, e); -+ if (eq == NULL) -+ return -ENOMEM; -+ -+ bfqd = kzalloc_node(sizeof(*bfqd), GFP_KERNEL, q->node); -+ if (bfqd == NULL) { -+ kobject_put(&eq->kobj); -+ return -ENOMEM; -+ } -+ eq->elevator_data = bfqd; -+ -+ /* -+ * Our fallback bfqq if bfq_find_alloc_queue() runs into OOM issues. -+ * Grab a permanent reference to it, so that the normal code flow -+ * will not attempt to free it. -+ */ -+ bfq_init_bfqq(bfqd, &bfqd->oom_bfqq, 1, 0); -+ atomic_inc(&bfqd->oom_bfqq.ref); -+ bfqd->oom_bfqq.entity.new_ioprio = BFQ_DEFAULT_QUEUE_IOPRIO; -+ bfqd->oom_bfqq.entity.new_ioprio_class = IOPRIO_CLASS_BE; -+ /* -+ * Trigger weight initialization, according to ioprio, at the -+ * oom_bfqq's first activation. The oom_bfqq's ioprio and ioprio -+ * class won't be changed any more. -+ */ -+ bfqd->oom_bfqq.entity.ioprio_changed = 1; -+ -+ bfqd->queue = q; -+ -+ spin_lock_irq(q->queue_lock); -+ q->elevator = eq; -+ spin_unlock_irq(q->queue_lock); -+ -+ bfqg = bfq_alloc_root_group(bfqd, q->node); -+ if (bfqg == NULL) { -+ kfree(bfqd); -+ kobject_put(&eq->kobj); -+ return -ENOMEM; -+ } -+ -+ bfqd->root_group = bfqg; -+ bfq_init_entity(&bfqd->oom_bfqq.entity, bfqd->root_group); -+#ifdef CONFIG_CGROUP_BFQIO -+ bfqd->active_numerous_groups = 0; -+#endif -+ -+ init_timer(&bfqd->idle_slice_timer); -+ bfqd->idle_slice_timer.function = bfq_idle_slice_timer; -+ bfqd->idle_slice_timer.data = (unsigned long)bfqd; -+ -+ bfqd->rq_pos_tree = RB_ROOT; -+ bfqd->queue_weights_tree = RB_ROOT; -+ bfqd->group_weights_tree = RB_ROOT; -+ -+ INIT_WORK(&bfqd->unplug_work, bfq_kick_queue); -+ -+ INIT_LIST_HEAD(&bfqd->active_list); -+ INIT_LIST_HEAD(&bfqd->idle_list); -+ INIT_HLIST_HEAD(&bfqd->burst_list); -+ -+ bfqd->hw_tag = -1; -+ -+ bfqd->bfq_max_budget = bfq_default_max_budget; -+ -+ bfqd->bfq_quantum = bfq_quantum; -+ bfqd->bfq_fifo_expire[0] = bfq_fifo_expire[0]; -+ bfqd->bfq_fifo_expire[1] = bfq_fifo_expire[1]; -+ bfqd->bfq_back_max = bfq_back_max; -+ bfqd->bfq_back_penalty = bfq_back_penalty; -+ bfqd->bfq_slice_idle = bfq_slice_idle; -+ bfqd->bfq_class_idle_last_service = 0; -+ bfqd->bfq_max_budget_async_rq = bfq_max_budget_async_rq; -+ bfqd->bfq_timeout[BLK_RW_ASYNC] = bfq_timeout_async; -+ bfqd->bfq_timeout[BLK_RW_SYNC] = bfq_timeout_sync; -+ -+ bfqd->bfq_coop_thresh = 2; -+ bfqd->bfq_failed_cooperations = 7000; -+ bfqd->bfq_requests_within_timer = 120; -+ -+ bfqd->bfq_large_burst_thresh = 11; -+ bfqd->bfq_burst_interval = msecs_to_jiffies(500); -+ -+ bfqd->low_latency = true; -+ -+ bfqd->bfq_wr_coeff = 20; -+ bfqd->bfq_wr_rt_max_time = msecs_to_jiffies(300); -+ bfqd->bfq_wr_max_time = 0; -+ bfqd->bfq_wr_min_idle_time = msecs_to_jiffies(2000); -+ bfqd->bfq_wr_min_inter_arr_async = msecs_to_jiffies(500); -+ bfqd->bfq_wr_max_softrt_rate = 7000; /* -+ * Approximate rate required -+ * to playback or record a -+ * high-definition compressed -+ * video. -+ */ -+ bfqd->wr_busy_queues = 0; -+ bfqd->busy_in_flight_queues = 0; -+ bfqd->const_seeky_busy_in_flight_queues = 0; -+ -+ /* -+ * Begin by assuming, optimistically, that the device peak rate is -+ * equal to the highest reference rate. -+ */ -+ bfqd->RT_prod = R_fast[blk_queue_nonrot(bfqd->queue)] * -+ T_fast[blk_queue_nonrot(bfqd->queue)]; -+ bfqd->peak_rate = R_fast[blk_queue_nonrot(bfqd->queue)]; -+ bfqd->device_speed = BFQ_BFQD_FAST; -+ -+ return 0; -+} -+ -+static void bfq_slab_kill(void) -+{ -+ if (bfq_pool != NULL) -+ kmem_cache_destroy(bfq_pool); -+} -+ -+static int __init bfq_slab_setup(void) -+{ -+ bfq_pool = KMEM_CACHE(bfq_queue, 0); -+ if (bfq_pool == NULL) -+ return -ENOMEM; -+ return 0; -+} -+ -+static ssize_t bfq_var_show(unsigned int var, char *page) -+{ -+ return sprintf(page, "%d\n", var); -+} -+ -+static ssize_t bfq_var_store(unsigned long *var, const char *page, -+ size_t count) -+{ -+ unsigned long new_val; -+ int ret = kstrtoul(page, 10, &new_val); -+ -+ if (ret == 0) -+ *var = new_val; -+ -+ return count; -+} -+ -+static ssize_t bfq_wr_max_time_show(struct elevator_queue *e, char *page) -+{ -+ struct bfq_data *bfqd = e->elevator_data; -+ return sprintf(page, "%d\n", bfqd->bfq_wr_max_time > 0 ? -+ jiffies_to_msecs(bfqd->bfq_wr_max_time) : -+ jiffies_to_msecs(bfq_wr_duration(bfqd))); -+} -+ -+static ssize_t bfq_weights_show(struct elevator_queue *e, char *page) -+{ -+ struct bfq_queue *bfqq; -+ struct bfq_data *bfqd = e->elevator_data; -+ ssize_t num_char = 0; -+ -+ num_char += sprintf(page + num_char, "Tot reqs queued %d\n\n", -+ bfqd->queued); -+ -+ spin_lock_irq(bfqd->queue->queue_lock); -+ -+ num_char += sprintf(page + num_char, "Active:\n"); -+ list_for_each_entry(bfqq, &bfqd->active_list, bfqq_list) { -+ num_char += sprintf(page + num_char, -+ "pid%d: weight %hu, nr_queued %d %d, dur %d/%u\n", -+ bfqq->pid, -+ bfqq->entity.weight, -+ bfqq->queued[0], -+ bfqq->queued[1], -+ jiffies_to_msecs(jiffies - bfqq->last_wr_start_finish), -+ jiffies_to_msecs(bfqq->wr_cur_max_time)); -+ } -+ -+ num_char += sprintf(page + num_char, "Idle:\n"); -+ list_for_each_entry(bfqq, &bfqd->idle_list, bfqq_list) { -+ num_char += sprintf(page + num_char, -+ "pid%d: weight %hu, dur %d/%u\n", -+ bfqq->pid, -+ bfqq->entity.weight, -+ jiffies_to_msecs(jiffies - -+ bfqq->last_wr_start_finish), -+ jiffies_to_msecs(bfqq->wr_cur_max_time)); -+ } -+ -+ spin_unlock_irq(bfqd->queue->queue_lock); -+ -+ return num_char; -+} -+ -+#define SHOW_FUNCTION(__FUNC, __VAR, __CONV) \ -+static ssize_t __FUNC(struct elevator_queue *e, char *page) \ -+{ \ -+ struct bfq_data *bfqd = e->elevator_data; \ -+ unsigned int __data = __VAR; \ -+ if (__CONV) \ -+ __data = jiffies_to_msecs(__data); \ -+ return bfq_var_show(__data, (page)); \ -+} -+SHOW_FUNCTION(bfq_quantum_show, bfqd->bfq_quantum, 0); -+SHOW_FUNCTION(bfq_fifo_expire_sync_show, bfqd->bfq_fifo_expire[1], 1); -+SHOW_FUNCTION(bfq_fifo_expire_async_show, bfqd->bfq_fifo_expire[0], 1); -+SHOW_FUNCTION(bfq_back_seek_max_show, bfqd->bfq_back_max, 0); -+SHOW_FUNCTION(bfq_back_seek_penalty_show, bfqd->bfq_back_penalty, 0); -+SHOW_FUNCTION(bfq_slice_idle_show, bfqd->bfq_slice_idle, 1); -+SHOW_FUNCTION(bfq_max_budget_show, bfqd->bfq_user_max_budget, 0); -+SHOW_FUNCTION(bfq_max_budget_async_rq_show, -+ bfqd->bfq_max_budget_async_rq, 0); -+SHOW_FUNCTION(bfq_timeout_sync_show, bfqd->bfq_timeout[BLK_RW_SYNC], 1); -+SHOW_FUNCTION(bfq_timeout_async_show, bfqd->bfq_timeout[BLK_RW_ASYNC], 1); -+SHOW_FUNCTION(bfq_low_latency_show, bfqd->low_latency, 0); -+SHOW_FUNCTION(bfq_wr_coeff_show, bfqd->bfq_wr_coeff, 0); -+SHOW_FUNCTION(bfq_wr_rt_max_time_show, bfqd->bfq_wr_rt_max_time, 1); -+SHOW_FUNCTION(bfq_wr_min_idle_time_show, bfqd->bfq_wr_min_idle_time, 1); -+SHOW_FUNCTION(bfq_wr_min_inter_arr_async_show, bfqd->bfq_wr_min_inter_arr_async, -+ 1); -+SHOW_FUNCTION(bfq_wr_max_softrt_rate_show, bfqd->bfq_wr_max_softrt_rate, 0); -+#undef SHOW_FUNCTION -+ -+#define STORE_FUNCTION(__FUNC, __PTR, MIN, MAX, __CONV) \ -+static ssize_t \ -+__FUNC(struct elevator_queue *e, const char *page, size_t count) \ -+{ \ -+ struct bfq_data *bfqd = e->elevator_data; \ -+ unsigned long uninitialized_var(__data); \ -+ int ret = bfq_var_store(&__data, (page), count); \ -+ if (__data < (MIN)) \ -+ __data = (MIN); \ -+ else if (__data > (MAX)) \ -+ __data = (MAX); \ -+ if (__CONV) \ -+ *(__PTR) = msecs_to_jiffies(__data); \ -+ else \ -+ *(__PTR) = __data; \ -+ return ret; \ -+} -+STORE_FUNCTION(bfq_quantum_store, &bfqd->bfq_quantum, 1, INT_MAX, 0); -+STORE_FUNCTION(bfq_fifo_expire_sync_store, &bfqd->bfq_fifo_expire[1], 1, -+ INT_MAX, 1); -+STORE_FUNCTION(bfq_fifo_expire_async_store, &bfqd->bfq_fifo_expire[0], 1, -+ INT_MAX, 1); -+STORE_FUNCTION(bfq_back_seek_max_store, &bfqd->bfq_back_max, 0, INT_MAX, 0); -+STORE_FUNCTION(bfq_back_seek_penalty_store, &bfqd->bfq_back_penalty, 1, -+ INT_MAX, 0); -+STORE_FUNCTION(bfq_slice_idle_store, &bfqd->bfq_slice_idle, 0, INT_MAX, 1); -+STORE_FUNCTION(bfq_max_budget_async_rq_store, &bfqd->bfq_max_budget_async_rq, -+ 1, INT_MAX, 0); -+STORE_FUNCTION(bfq_timeout_async_store, &bfqd->bfq_timeout[BLK_RW_ASYNC], 0, -+ INT_MAX, 1); -+STORE_FUNCTION(bfq_wr_coeff_store, &bfqd->bfq_wr_coeff, 1, INT_MAX, 0); -+STORE_FUNCTION(bfq_wr_max_time_store, &bfqd->bfq_wr_max_time, 0, INT_MAX, 1); -+STORE_FUNCTION(bfq_wr_rt_max_time_store, &bfqd->bfq_wr_rt_max_time, 0, INT_MAX, -+ 1); -+STORE_FUNCTION(bfq_wr_min_idle_time_store, &bfqd->bfq_wr_min_idle_time, 0, -+ INT_MAX, 1); -+STORE_FUNCTION(bfq_wr_min_inter_arr_async_store, -+ &bfqd->bfq_wr_min_inter_arr_async, 0, INT_MAX, 1); -+STORE_FUNCTION(bfq_wr_max_softrt_rate_store, &bfqd->bfq_wr_max_softrt_rate, 0, -+ INT_MAX, 0); -+#undef STORE_FUNCTION -+ -+/* do nothing for the moment */ -+static ssize_t bfq_weights_store(struct elevator_queue *e, -+ const char *page, size_t count) -+{ -+ return count; -+} -+ -+static inline unsigned long bfq_estimated_max_budget(struct bfq_data *bfqd) -+{ -+ u64 timeout = jiffies_to_msecs(bfqd->bfq_timeout[BLK_RW_SYNC]); -+ -+ if (bfqd->peak_rate_samples >= BFQ_PEAK_RATE_SAMPLES) -+ return bfq_calc_max_budget(bfqd->peak_rate, timeout); -+ else -+ return bfq_default_max_budget; -+} -+ -+static ssize_t bfq_max_budget_store(struct elevator_queue *e, -+ const char *page, size_t count) -+{ -+ struct bfq_data *bfqd = e->elevator_data; -+ unsigned long uninitialized_var(__data); -+ int ret = bfq_var_store(&__data, (page), count); -+ -+ if (__data == 0) -+ bfqd->bfq_max_budget = bfq_estimated_max_budget(bfqd); -+ else { -+ if (__data > INT_MAX) -+ __data = INT_MAX; -+ bfqd->bfq_max_budget = __data; -+ } -+ -+ bfqd->bfq_user_max_budget = __data; -+ -+ return ret; -+} -+ -+static ssize_t bfq_timeout_sync_store(struct elevator_queue *e, -+ const char *page, size_t count) -+{ -+ struct bfq_data *bfqd = e->elevator_data; -+ unsigned long uninitialized_var(__data); -+ int ret = bfq_var_store(&__data, (page), count); -+ -+ if (__data < 1) -+ __data = 1; -+ else if (__data > INT_MAX) -+ __data = INT_MAX; -+ -+ bfqd->bfq_timeout[BLK_RW_SYNC] = msecs_to_jiffies(__data); -+ if (bfqd->bfq_user_max_budget == 0) -+ bfqd->bfq_max_budget = bfq_estimated_max_budget(bfqd); -+ -+ return ret; -+} -+ -+static ssize_t bfq_low_latency_store(struct elevator_queue *e, -+ const char *page, size_t count) -+{ -+ struct bfq_data *bfqd = e->elevator_data; -+ unsigned long uninitialized_var(__data); -+ int ret = bfq_var_store(&__data, (page), count); -+ -+ if (__data > 1) -+ __data = 1; -+ if (__data == 0 && bfqd->low_latency != 0) -+ bfq_end_wr(bfqd); -+ bfqd->low_latency = __data; -+ -+ return ret; -+} -+ -+#define BFQ_ATTR(name) \ -+ __ATTR(name, S_IRUGO|S_IWUSR, bfq_##name##_show, bfq_##name##_store) -+ -+static struct elv_fs_entry bfq_attrs[] = { -+ BFQ_ATTR(quantum), -+ BFQ_ATTR(fifo_expire_sync), -+ BFQ_ATTR(fifo_expire_async), -+ BFQ_ATTR(back_seek_max), -+ BFQ_ATTR(back_seek_penalty), -+ BFQ_ATTR(slice_idle), -+ BFQ_ATTR(max_budget), -+ BFQ_ATTR(max_budget_async_rq), -+ BFQ_ATTR(timeout_sync), -+ BFQ_ATTR(timeout_async), -+ BFQ_ATTR(low_latency), -+ BFQ_ATTR(wr_coeff), -+ BFQ_ATTR(wr_max_time), -+ BFQ_ATTR(wr_rt_max_time), -+ BFQ_ATTR(wr_min_idle_time), -+ BFQ_ATTR(wr_min_inter_arr_async), -+ BFQ_ATTR(wr_max_softrt_rate), -+ BFQ_ATTR(weights), -+ __ATTR_NULL -+}; -+ -+static struct elevator_type iosched_bfq = { -+ .ops = { -+ .elevator_merge_fn = bfq_merge, -+ .elevator_merged_fn = bfq_merged_request, -+ .elevator_merge_req_fn = bfq_merged_requests, -+ .elevator_allow_merge_fn = bfq_allow_merge, -+ .elevator_dispatch_fn = bfq_dispatch_requests, -+ .elevator_add_req_fn = bfq_insert_request, -+ .elevator_activate_req_fn = bfq_activate_request, -+ .elevator_deactivate_req_fn = bfq_deactivate_request, -+ .elevator_completed_req_fn = bfq_completed_request, -+ .elevator_former_req_fn = elv_rb_former_request, -+ .elevator_latter_req_fn = elv_rb_latter_request, -+ .elevator_init_icq_fn = bfq_init_icq, -+ .elevator_exit_icq_fn = bfq_exit_icq, -+ .elevator_set_req_fn = bfq_set_request, -+ .elevator_put_req_fn = bfq_put_request, -+ .elevator_may_queue_fn = bfq_may_queue, -+ .elevator_init_fn = bfq_init_queue, -+ .elevator_exit_fn = bfq_exit_queue, -+ }, -+ .icq_size = sizeof(struct bfq_io_cq), -+ .icq_align = __alignof__(struct bfq_io_cq), -+ .elevator_attrs = bfq_attrs, -+ .elevator_name = "bfq", -+ .elevator_owner = THIS_MODULE, -+}; -+ -+static int __init bfq_init(void) -+{ -+ /* -+ * Can be 0 on HZ < 1000 setups. -+ */ -+ if (bfq_slice_idle == 0) -+ bfq_slice_idle = 1; -+ -+ if (bfq_timeout_async == 0) -+ bfq_timeout_async = 1; -+ -+ if (bfq_slab_setup()) -+ return -ENOMEM; -+ -+ /* -+ * Times to load large popular applications for the typical systems -+ * installed on the reference devices (see the comments before the -+ * definitions of the two arrays). -+ */ -+ T_slow[0] = msecs_to_jiffies(2600); -+ T_slow[1] = msecs_to_jiffies(1000); -+ T_fast[0] = msecs_to_jiffies(5500); -+ T_fast[1] = msecs_to_jiffies(2000); -+ -+ /* -+ * Thresholds that determine the switch between speed classes (see -+ * the comments before the definition of the array). -+ */ -+ device_speed_thresh[0] = (R_fast[0] + R_slow[0]) / 2; -+ device_speed_thresh[1] = (R_fast[1] + R_slow[1]) / 2; -+ -+ elv_register(&iosched_bfq); -+ pr_info("BFQ I/O-scheduler version: v7r7"); -+ -+ return 0; -+} -+ -+static void __exit bfq_exit(void) -+{ -+ elv_unregister(&iosched_bfq); -+ bfq_slab_kill(); -+} -+ -+module_init(bfq_init); -+module_exit(bfq_exit); -+ -+MODULE_AUTHOR("Fabio Checconi, Paolo Valente"); -+MODULE_LICENSE("GPL"); -diff -Nur linux-4.1.13.orig/block/bfq-sched.c linux-4.1.13/block/bfq-sched.c ---- linux-4.1.13.orig/block/bfq-sched.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/block/bfq-sched.c 2015-11-30 17:56:13.536140654 +0100 -@@ -0,0 +1,1186 @@ -+/* -+ * BFQ: Hierarchical B-WF2Q+ scheduler. -+ * -+ * Based on ideas and code from CFQ: -+ * Copyright (C) 2003 Jens Axboe -+ * -+ * Copyright (C) 2008 Fabio Checconi -+ * Paolo Valente -+ * -+ * Copyright (C) 2010 Paolo Valente -+ */ -+ -+#ifdef CONFIG_CGROUP_BFQIO -+#define for_each_entity(entity) \ -+ for (; entity != NULL; entity = entity->parent) -+ -+#define for_each_entity_safe(entity, parent) \ -+ for (; entity && ({ parent = entity->parent; 1; }); entity = parent) -+ -+static struct bfq_entity *bfq_lookup_next_entity(struct bfq_sched_data *sd, -+ int extract, -+ struct bfq_data *bfqd); -+ -+static inline void bfq_update_budget(struct bfq_entity *next_in_service) -+{ -+ struct bfq_entity *bfqg_entity; -+ struct bfq_group *bfqg; -+ struct bfq_sched_data *group_sd; -+ -+ BUG_ON(next_in_service == NULL); -+ -+ group_sd = next_in_service->sched_data; -+ -+ bfqg = container_of(group_sd, struct bfq_group, sched_data); -+ /* -+ * bfq_group's my_entity field is not NULL only if the group -+ * is not the root group. We must not touch the root entity -+ * as it must never become an in-service entity. -+ */ -+ bfqg_entity = bfqg->my_entity; -+ if (bfqg_entity != NULL) -+ bfqg_entity->budget = next_in_service->budget; -+} -+ -+static int bfq_update_next_in_service(struct bfq_sched_data *sd) -+{ -+ struct bfq_entity *next_in_service; -+ -+ if (sd->in_service_entity != NULL) -+ /* will update/requeue at the end of service */ -+ return 0; -+ -+ /* -+ * NOTE: this can be improved in many ways, such as returning -+ * 1 (and thus propagating upwards the update) only when the -+ * budget changes, or caching the bfqq that will be scheduled -+ * next from this subtree. By now we worry more about -+ * correctness than about performance... -+ */ -+ next_in_service = bfq_lookup_next_entity(sd, 0, NULL); -+ sd->next_in_service = next_in_service; -+ -+ if (next_in_service != NULL) -+ bfq_update_budget(next_in_service); -+ -+ return 1; -+} -+ -+static inline void bfq_check_next_in_service(struct bfq_sched_data *sd, -+ struct bfq_entity *entity) -+{ -+ BUG_ON(sd->next_in_service != entity); -+} -+#else -+#define for_each_entity(entity) \ -+ for (; entity != NULL; entity = NULL) -+ -+#define for_each_entity_safe(entity, parent) \ -+ for (parent = NULL; entity != NULL; entity = parent) -+ -+static inline int bfq_update_next_in_service(struct bfq_sched_data *sd) -+{ -+ return 0; -+} -+ -+static inline void bfq_check_next_in_service(struct bfq_sched_data *sd, -+ struct bfq_entity *entity) -+{ -+} -+ -+static inline void bfq_update_budget(struct bfq_entity *next_in_service) -+{ -+} -+#endif -+ -+/* -+ * Shift for timestamp calculations. This actually limits the maximum -+ * service allowed in one timestamp delta (small shift values increase it), -+ * the maximum total weight that can be used for the queues in the system -+ * (big shift values increase it), and the period of virtual time -+ * wraparounds. -+ */ -+#define WFQ_SERVICE_SHIFT 22 -+ -+/** -+ * bfq_gt - compare two timestamps. -+ * @a: first ts. -+ * @b: second ts. -+ * -+ * Return @a > @b, dealing with wrapping correctly. -+ */ -+static inline int bfq_gt(u64 a, u64 b) -+{ -+ return (s64)(a - b) > 0; -+} -+ -+static inline struct bfq_queue *bfq_entity_to_bfqq(struct bfq_entity *entity) -+{ -+ struct bfq_queue *bfqq = NULL; -+ -+ BUG_ON(entity == NULL); -+ -+ if (entity->my_sched_data == NULL) -+ bfqq = container_of(entity, struct bfq_queue, entity); -+ -+ return bfqq; -+} -+ -+ -+/** -+ * bfq_delta - map service into the virtual time domain. -+ * @service: amount of service. -+ * @weight: scale factor (weight of an entity or weight sum). -+ */ -+static inline u64 bfq_delta(unsigned long service, -+ unsigned long weight) -+{ -+ u64 d = (u64)service << WFQ_SERVICE_SHIFT; -+ -+ do_div(d, weight); -+ return d; -+} -+ -+/** -+ * bfq_calc_finish - assign the finish time to an entity. -+ * @entity: the entity to act upon. -+ * @service: the service to be charged to the entity. -+ */ -+static inline void bfq_calc_finish(struct bfq_entity *entity, -+ unsigned long service) -+{ -+ struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity); -+ -+ BUG_ON(entity->weight == 0); -+ -+ entity->finish = entity->start + -+ bfq_delta(service, entity->weight); -+ -+ if (bfqq != NULL) { -+ bfq_log_bfqq(bfqq->bfqd, bfqq, -+ "calc_finish: serv %lu, w %d", -+ service, entity->weight); -+ bfq_log_bfqq(bfqq->bfqd, bfqq, -+ "calc_finish: start %llu, finish %llu, delta %llu", -+ entity->start, entity->finish, -+ bfq_delta(service, entity->weight)); -+ } -+} -+ -+/** -+ * bfq_entity_of - get an entity from a node. -+ * @node: the node field of the entity. -+ * -+ * Convert a node pointer to the relative entity. This is used only -+ * to simplify the logic of some functions and not as the generic -+ * conversion mechanism because, e.g., in the tree walking functions, -+ * the check for a %NULL value would be redundant. -+ */ -+static inline struct bfq_entity *bfq_entity_of(struct rb_node *node) -+{ -+ struct bfq_entity *entity = NULL; -+ -+ if (node != NULL) -+ entity = rb_entry(node, struct bfq_entity, rb_node); -+ -+ return entity; -+} -+ -+/** -+ * bfq_extract - remove an entity from a tree. -+ * @root: the tree root. -+ * @entity: the entity to remove. -+ */ -+static inline void bfq_extract(struct rb_root *root, -+ struct bfq_entity *entity) -+{ -+ BUG_ON(entity->tree != root); -+ -+ entity->tree = NULL; -+ rb_erase(&entity->rb_node, root); -+} -+ -+/** -+ * bfq_idle_extract - extract an entity from the idle tree. -+ * @st: the service tree of the owning @entity. -+ * @entity: the entity being removed. -+ */ -+static void bfq_idle_extract(struct bfq_service_tree *st, -+ struct bfq_entity *entity) -+{ -+ struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity); -+ struct rb_node *next; -+ -+ BUG_ON(entity->tree != &st->idle); -+ -+ if (entity == st->first_idle) { -+ next = rb_next(&entity->rb_node); -+ st->first_idle = bfq_entity_of(next); -+ } -+ -+ if (entity == st->last_idle) { -+ next = rb_prev(&entity->rb_node); -+ st->last_idle = bfq_entity_of(next); -+ } -+ -+ bfq_extract(&st->idle, entity); -+ -+ if (bfqq != NULL) -+ list_del(&bfqq->bfqq_list); -+} -+ -+/** -+ * bfq_insert - generic tree insertion. -+ * @root: tree root. -+ * @entity: entity to insert. -+ * -+ * This is used for the idle and the active tree, since they are both -+ * ordered by finish time. -+ */ -+static void bfq_insert(struct rb_root *root, struct bfq_entity *entity) -+{ -+ struct bfq_entity *entry; -+ struct rb_node **node = &root->rb_node; -+ struct rb_node *parent = NULL; -+ -+ BUG_ON(entity->tree != NULL); -+ -+ while (*node != NULL) { -+ parent = *node; -+ entry = rb_entry(parent, struct bfq_entity, rb_node); -+ -+ if (bfq_gt(entry->finish, entity->finish)) -+ node = &parent->rb_left; -+ else -+ node = &parent->rb_right; -+ } -+ -+ rb_link_node(&entity->rb_node, parent, node); -+ rb_insert_color(&entity->rb_node, root); -+ -+ entity->tree = root; -+} -+ -+/** -+ * bfq_update_min - update the min_start field of a entity. -+ * @entity: the entity to update. -+ * @node: one of its children. -+ * -+ * This function is called when @entity may store an invalid value for -+ * min_start due to updates to the active tree. The function assumes -+ * that the subtree rooted at @node (which may be its left or its right -+ * child) has a valid min_start value. -+ */ -+static inline void bfq_update_min(struct bfq_entity *entity, -+ struct rb_node *node) -+{ -+ struct bfq_entity *child; -+ -+ if (node != NULL) { -+ child = rb_entry(node, struct bfq_entity, rb_node); -+ if (bfq_gt(entity->min_start, child->min_start)) -+ entity->min_start = child->min_start; -+ } -+} -+ -+/** -+ * bfq_update_active_node - recalculate min_start. -+ * @node: the node to update. -+ * -+ * @node may have changed position or one of its children may have moved, -+ * this function updates its min_start value. The left and right subtrees -+ * are assumed to hold a correct min_start value. -+ */ -+static inline void bfq_update_active_node(struct rb_node *node) -+{ -+ struct bfq_entity *entity = rb_entry(node, struct bfq_entity, rb_node); -+ -+ entity->min_start = entity->start; -+ bfq_update_min(entity, node->rb_right); -+ bfq_update_min(entity, node->rb_left); -+} -+ -+/** -+ * bfq_update_active_tree - update min_start for the whole active tree. -+ * @node: the starting node. -+ * -+ * @node must be the deepest modified node after an update. This function -+ * updates its min_start using the values held by its children, assuming -+ * that they did not change, and then updates all the nodes that may have -+ * changed in the path to the root. The only nodes that may have changed -+ * are the ones in the path or their siblings. -+ */ -+static void bfq_update_active_tree(struct rb_node *node) -+{ -+ struct rb_node *parent; -+ -+up: -+ bfq_update_active_node(node); -+ -+ parent = rb_parent(node); -+ if (parent == NULL) -+ return; -+ -+ if (node == parent->rb_left && parent->rb_right != NULL) -+ bfq_update_active_node(parent->rb_right); -+ else if (parent->rb_left != NULL) -+ bfq_update_active_node(parent->rb_left); -+ -+ node = parent; -+ goto up; -+} -+ -+static void bfq_weights_tree_add(struct bfq_data *bfqd, -+ struct bfq_entity *entity, -+ struct rb_root *root); -+ -+static void bfq_weights_tree_remove(struct bfq_data *bfqd, -+ struct bfq_entity *entity, -+ struct rb_root *root); -+ -+ -+/** -+ * bfq_active_insert - insert an entity in the active tree of its -+ * group/device. -+ * @st: the service tree of the entity. -+ * @entity: the entity being inserted. -+ * -+ * The active tree is ordered by finish time, but an extra key is kept -+ * per each node, containing the minimum value for the start times of -+ * its children (and the node itself), so it's possible to search for -+ * the eligible node with the lowest finish time in logarithmic time. -+ */ -+static void bfq_active_insert(struct bfq_service_tree *st, -+ struct bfq_entity *entity) -+{ -+ struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity); -+ struct rb_node *node = &entity->rb_node; -+#ifdef CONFIG_CGROUP_BFQIO -+ struct bfq_sched_data *sd = NULL; -+ struct bfq_group *bfqg = NULL; -+ struct bfq_data *bfqd = NULL; -+#endif -+ -+ bfq_insert(&st->active, entity); -+ -+ if (node->rb_left != NULL) -+ node = node->rb_left; -+ else if (node->rb_right != NULL) -+ node = node->rb_right; -+ -+ bfq_update_active_tree(node); -+ -+#ifdef CONFIG_CGROUP_BFQIO -+ sd = entity->sched_data; -+ bfqg = container_of(sd, struct bfq_group, sched_data); -+ BUG_ON(!bfqg); -+ bfqd = (struct bfq_data *)bfqg->bfqd; -+#endif -+ if (bfqq != NULL) -+ list_add(&bfqq->bfqq_list, &bfqq->bfqd->active_list); -+#ifdef CONFIG_CGROUP_BFQIO -+ else { /* bfq_group */ -+ BUG_ON(!bfqd); -+ bfq_weights_tree_add(bfqd, entity, &bfqd->group_weights_tree); -+ } -+ if (bfqg != bfqd->root_group) { -+ BUG_ON(!bfqg); -+ BUG_ON(!bfqd); -+ bfqg->active_entities++; -+ if (bfqg->active_entities == 2) -+ bfqd->active_numerous_groups++; -+ } -+#endif -+} -+ -+/** -+ * bfq_ioprio_to_weight - calc a weight from an ioprio. -+ * @ioprio: the ioprio value to convert. -+ */ -+static inline unsigned short bfq_ioprio_to_weight(int ioprio) -+{ -+ BUG_ON(ioprio < 0 || ioprio >= IOPRIO_BE_NR); -+ return IOPRIO_BE_NR - ioprio; -+} -+ -+/** -+ * bfq_weight_to_ioprio - calc an ioprio from a weight. -+ * @weight: the weight value to convert. -+ * -+ * To preserve as mush as possible the old only-ioprio user interface, -+ * 0 is used as an escape ioprio value for weights (numerically) equal or -+ * larger than IOPRIO_BE_NR -+ */ -+static inline unsigned short bfq_weight_to_ioprio(int weight) -+{ -+ BUG_ON(weight < BFQ_MIN_WEIGHT || weight > BFQ_MAX_WEIGHT); -+ return IOPRIO_BE_NR - weight < 0 ? 0 : IOPRIO_BE_NR - weight; -+} -+ -+static inline void bfq_get_entity(struct bfq_entity *entity) -+{ -+ struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity); -+ -+ if (bfqq != NULL) { -+ atomic_inc(&bfqq->ref); -+ bfq_log_bfqq(bfqq->bfqd, bfqq, "get_entity: %p %d", -+ bfqq, atomic_read(&bfqq->ref)); -+ } -+} -+ -+/** -+ * bfq_find_deepest - find the deepest node that an extraction can modify. -+ * @node: the node being removed. -+ * -+ * Do the first step of an extraction in an rb tree, looking for the -+ * node that will replace @node, and returning the deepest node that -+ * the following modifications to the tree can touch. If @node is the -+ * last node in the tree return %NULL. -+ */ -+static struct rb_node *bfq_find_deepest(struct rb_node *node) -+{ -+ struct rb_node *deepest; -+ -+ if (node->rb_right == NULL && node->rb_left == NULL) -+ deepest = rb_parent(node); -+ else if (node->rb_right == NULL) -+ deepest = node->rb_left; -+ else if (node->rb_left == NULL) -+ deepest = node->rb_right; -+ else { -+ deepest = rb_next(node); -+ if (deepest->rb_right != NULL) -+ deepest = deepest->rb_right; -+ else if (rb_parent(deepest) != node) -+ deepest = rb_parent(deepest); -+ } -+ -+ return deepest; -+} -+ -+/** -+ * bfq_active_extract - remove an entity from the active tree. -+ * @st: the service_tree containing the tree. -+ * @entity: the entity being removed. -+ */ -+static void bfq_active_extract(struct bfq_service_tree *st, -+ struct bfq_entity *entity) -+{ -+ struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity); -+ struct rb_node *node; -+#ifdef CONFIG_CGROUP_BFQIO -+ struct bfq_sched_data *sd = NULL; -+ struct bfq_group *bfqg = NULL; -+ struct bfq_data *bfqd = NULL; -+#endif -+ -+ node = bfq_find_deepest(&entity->rb_node); -+ bfq_extract(&st->active, entity); -+ -+ if (node != NULL) -+ bfq_update_active_tree(node); -+ -+#ifdef CONFIG_CGROUP_BFQIO -+ sd = entity->sched_data; -+ bfqg = container_of(sd, struct bfq_group, sched_data); -+ BUG_ON(!bfqg); -+ bfqd = (struct bfq_data *)bfqg->bfqd; -+#endif -+ if (bfqq != NULL) -+ list_del(&bfqq->bfqq_list); -+#ifdef CONFIG_CGROUP_BFQIO -+ else { /* bfq_group */ -+ BUG_ON(!bfqd); -+ bfq_weights_tree_remove(bfqd, entity, -+ &bfqd->group_weights_tree); -+ } -+ if (bfqg != bfqd->root_group) { -+ BUG_ON(!bfqg); -+ BUG_ON(!bfqd); -+ BUG_ON(!bfqg->active_entities); -+ bfqg->active_entities--; -+ if (bfqg->active_entities == 1) { -+ BUG_ON(!bfqd->active_numerous_groups); -+ bfqd->active_numerous_groups--; -+ } -+ } -+#endif -+} -+ -+/** -+ * bfq_idle_insert - insert an entity into the idle tree. -+ * @st: the service tree containing the tree. -+ * @entity: the entity to insert. -+ */ -+static void bfq_idle_insert(struct bfq_service_tree *st, -+ struct bfq_entity *entity) -+{ -+ struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity); -+ struct bfq_entity *first_idle = st->first_idle; -+ struct bfq_entity *last_idle = st->last_idle; -+ -+ if (first_idle == NULL || bfq_gt(first_idle->finish, entity->finish)) -+ st->first_idle = entity; -+ if (last_idle == NULL || bfq_gt(entity->finish, last_idle->finish)) -+ st->last_idle = entity; -+ -+ bfq_insert(&st->idle, entity); -+ -+ if (bfqq != NULL) -+ list_add(&bfqq->bfqq_list, &bfqq->bfqd->idle_list); -+} -+ -+/** -+ * bfq_forget_entity - remove an entity from the wfq trees. -+ * @st: the service tree. -+ * @entity: the entity being removed. -+ * -+ * Update the device status and forget everything about @entity, putting -+ * the device reference to it, if it is a queue. Entities belonging to -+ * groups are not refcounted. -+ */ -+static void bfq_forget_entity(struct bfq_service_tree *st, -+ struct bfq_entity *entity) -+{ -+ struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity); -+ struct bfq_sched_data *sd; -+ -+ BUG_ON(!entity->on_st); -+ -+ entity->on_st = 0; -+ st->wsum -= entity->weight; -+ if (bfqq != NULL) { -+ sd = entity->sched_data; -+ bfq_log_bfqq(bfqq->bfqd, bfqq, "forget_entity: %p %d", -+ bfqq, atomic_read(&bfqq->ref)); -+ bfq_put_queue(bfqq); -+ } -+} -+ -+/** -+ * bfq_put_idle_entity - release the idle tree ref of an entity. -+ * @st: service tree for the entity. -+ * @entity: the entity being released. -+ */ -+static void bfq_put_idle_entity(struct bfq_service_tree *st, -+ struct bfq_entity *entity) -+{ -+ bfq_idle_extract(st, entity); -+ bfq_forget_entity(st, entity); -+} -+ -+/** -+ * bfq_forget_idle - update the idle tree if necessary. -+ * @st: the service tree to act upon. -+ * -+ * To preserve the global O(log N) complexity we only remove one entry here; -+ * as the idle tree will not grow indefinitely this can be done safely. -+ */ -+static void bfq_forget_idle(struct bfq_service_tree *st) -+{ -+ struct bfq_entity *first_idle = st->first_idle; -+ struct bfq_entity *last_idle = st->last_idle; -+ -+ if (RB_EMPTY_ROOT(&st->active) && last_idle != NULL && -+ !bfq_gt(last_idle->finish, st->vtime)) { -+ /* -+ * Forget the whole idle tree, increasing the vtime past -+ * the last finish time of idle entities. -+ */ -+ st->vtime = last_idle->finish; -+ } -+ -+ if (first_idle != NULL && !bfq_gt(first_idle->finish, st->vtime)) -+ bfq_put_idle_entity(st, first_idle); -+} -+ -+static struct bfq_service_tree * -+__bfq_entity_update_weight_prio(struct bfq_service_tree *old_st, -+ struct bfq_entity *entity) -+{ -+ struct bfq_service_tree *new_st = old_st; -+ -+ if (entity->ioprio_changed) { -+ struct bfq_queue *bfqq = bfq_entity_to_bfqq(entity); -+ unsigned short prev_weight, new_weight; -+ struct bfq_data *bfqd = NULL; -+ struct rb_root *root; -+#ifdef CONFIG_CGROUP_BFQIO -+ struct bfq_sched_data *sd; -+ struct bfq_group *bfqg; -+#endif -+ -+ if (bfqq != NULL) -+ bfqd = bfqq->bfqd; -+#ifdef CONFIG_CGROUP_BFQIO -+ else { -+ sd = entity->my_sched_data; -+ bfqg = container_of(sd, struct bfq_group, sched_data); -+ BUG_ON(!bfqg); -+ bfqd = (struct bfq_data *)bfqg->bfqd; -+ BUG_ON(!bfqd); -+ } -+#endif -+ -+ BUG_ON(old_st->wsum < entity->weight); -+ old_st->wsum -= entity->weight; -+ -+ if (entity->new_weight != entity->orig_weight) { -+ if (entity->new_weight < BFQ_MIN_WEIGHT || -+ entity->new_weight > BFQ_MAX_WEIGHT) { -+ printk(KERN_CRIT "update_weight_prio: " -+ "new_weight %d\n", -+ entity->new_weight); -+ BUG(); -+ } -+ entity->orig_weight = entity->new_weight; -+ entity->ioprio = -+ bfq_weight_to_ioprio(entity->orig_weight); -+ } else if (entity->new_ioprio != entity->ioprio) { -+ entity->ioprio = entity->new_ioprio; -+ entity->orig_weight = -+ bfq_ioprio_to_weight(entity->ioprio); -+ } else -+ entity->new_weight = entity->orig_weight = -+ bfq_ioprio_to_weight(entity->ioprio); -+ -+ entity->ioprio_class = entity->new_ioprio_class; -+ entity->ioprio_changed = 0; -+ -+ /* -+ * NOTE: here we may be changing the weight too early, -+ * this will cause unfairness. The correct approach -+ * would have required additional complexity to defer -+ * weight changes to the proper time instants (i.e., -+ * when entity->finish <= old_st->vtime). -+ */ -+ new_st = bfq_entity_service_tree(entity); -+ -+ prev_weight = entity->weight; -+ new_weight = entity->orig_weight * -+ (bfqq != NULL ? bfqq->wr_coeff : 1); -+ /* -+ * If the weight of the entity changes, remove the entity -+ * from its old weight counter (if there is a counter -+ * associated with the entity), and add it to the counter -+ * associated with its new weight. -+ */ -+ if (prev_weight != new_weight) { -+ root = bfqq ? &bfqd->queue_weights_tree : -+ &bfqd->group_weights_tree; -+ bfq_weights_tree_remove(bfqd, entity, root); -+ } -+ entity->weight = new_weight; -+ /* -+ * Add the entity to its weights tree only if it is -+ * not associated with a weight-raised queue. -+ */ -+ if (prev_weight != new_weight && -+ (bfqq ? bfqq->wr_coeff == 1 : 1)) -+ /* If we get here, root has been initialized. */ -+ bfq_weights_tree_add(bfqd, entity, root); -+ -+ new_st->wsum += entity->weight; -+ -+ if (new_st != old_st) -+ entity->start = new_st->vtime; -+ } -+ -+ return new_st; -+} -+ -+/** -+ * bfq_bfqq_served - update the scheduler status after selection for -+ * service. -+ * @bfqq: the queue being served. -+ * @served: bytes to transfer. -+ * -+ * NOTE: this can be optimized, as the timestamps of upper level entities -+ * are synchronized every time a new bfqq is selected for service. By now, -+ * we keep it to better check consistency. -+ */ -+static void bfq_bfqq_served(struct bfq_queue *bfqq, unsigned long served) -+{ -+ struct bfq_entity *entity = &bfqq->entity; -+ struct bfq_service_tree *st; -+ -+ for_each_entity(entity) { -+ st = bfq_entity_service_tree(entity); -+ -+ entity->service += served; -+ BUG_ON(entity->service > entity->budget); -+ BUG_ON(st->wsum == 0); -+ -+ st->vtime += bfq_delta(served, st->wsum); -+ bfq_forget_idle(st); -+ } -+ bfq_log_bfqq(bfqq->bfqd, bfqq, "bfqq_served %lu secs", served); -+} -+ -+/** -+ * bfq_bfqq_charge_full_budget - set the service to the entity budget. -+ * @bfqq: the queue that needs a service update. -+ * -+ * When it's not possible to be fair in the service domain, because -+ * a queue is not consuming its budget fast enough (the meaning of -+ * fast depends on the timeout parameter), we charge it a full -+ * budget. In this way we should obtain a sort of time-domain -+ * fairness among all the seeky/slow queues. -+ */ -+static inline void bfq_bfqq_charge_full_budget(struct bfq_queue *bfqq) -+{ -+ struct bfq_entity *entity = &bfqq->entity; -+ -+ bfq_log_bfqq(bfqq->bfqd, bfqq, "charge_full_budget"); -+ -+ bfq_bfqq_served(bfqq, entity->budget - entity->service); -+} -+ -+/** -+ * __bfq_activate_entity - activate an entity. -+ * @entity: the entity being activated. -+ * -+ * Called whenever an entity is activated, i.e., it is not active and one -+ * of its children receives a new request, or has to be reactivated due to -+ * budget exhaustion. It uses the current budget of the entity (and the -+ * service received if @entity is active) of the queue to calculate its -+ * timestamps. -+ */ -+static void __bfq_activate_entity(struct bfq_entity *entity) -+{ -+ struct bfq_sched_data *sd = entity->sched_data; -+ struct bfq_service_tree *st = bfq_entity_service_tree(entity); -+ -+ if (entity == sd->in_service_entity) { -+ BUG_ON(entity->tree != NULL); -+ /* -+ * If we are requeueing the current entity we have -+ * to take care of not charging to it service it has -+ * not received. -+ */ -+ bfq_calc_finish(entity, entity->service); -+ entity->start = entity->finish; -+ sd->in_service_entity = NULL; -+ } else if (entity->tree == &st->active) { -+ /* -+ * Requeueing an entity due to a change of some -+ * next_in_service entity below it. We reuse the -+ * old start time. -+ */ -+ bfq_active_extract(st, entity); -+ } else if (entity->tree == &st->idle) { -+ /* -+ * Must be on the idle tree, bfq_idle_extract() will -+ * check for that. -+ */ -+ bfq_idle_extract(st, entity); -+ entity->start = bfq_gt(st->vtime, entity->finish) ? -+ st->vtime : entity->finish; -+ } else { -+ /* -+ * The finish time of the entity may be invalid, and -+ * it is in the past for sure, otherwise the queue -+ * would have been on the idle tree. -+ */ -+ entity->start = st->vtime; -+ st->wsum += entity->weight; -+ bfq_get_entity(entity); -+ -+ BUG_ON(entity->on_st); -+ entity->on_st = 1; -+ } -+ -+ st = __bfq_entity_update_weight_prio(st, entity); -+ bfq_calc_finish(entity, entity->budget); -+ bfq_active_insert(st, entity); -+} -+ -+/** -+ * bfq_activate_entity - activate an entity and its ancestors if necessary. -+ * @entity: the entity to activate. -+ * -+ * Activate @entity and all the entities on the path from it to the root. -+ */ -+static void bfq_activate_entity(struct bfq_entity *entity) -+{ -+ struct bfq_sched_data *sd; -+ -+ for_each_entity(entity) { -+ __bfq_activate_entity(entity); -+ -+ sd = entity->sched_data; -+ if (!bfq_update_next_in_service(sd)) -+ /* -+ * No need to propagate the activation to the -+ * upper entities, as they will be updated when -+ * the in-service entity is rescheduled. -+ */ -+ break; -+ } -+} -+ -+/** -+ * __bfq_deactivate_entity - deactivate an entity from its service tree. -+ * @entity: the entity to deactivate. -+ * @requeue: if false, the entity will not be put into the idle tree. -+ * -+ * Deactivate an entity, independently from its previous state. If the -+ * entity was not on a service tree just return, otherwise if it is on -+ * any scheduler tree, extract it from that tree, and if necessary -+ * and if the caller did not specify @requeue, put it on the idle tree. -+ * -+ * Return %1 if the caller should update the entity hierarchy, i.e., -+ * if the entity was in service or if it was the next_in_service for -+ * its sched_data; return %0 otherwise. -+ */ -+static int __bfq_deactivate_entity(struct bfq_entity *entity, int requeue) -+{ -+ struct bfq_sched_data *sd = entity->sched_data; -+ struct bfq_service_tree *st = bfq_entity_service_tree(entity); -+ int was_in_service = entity == sd->in_service_entity; -+ int ret = 0; -+ -+ if (!entity->on_st) -+ return 0; -+ -+ BUG_ON(was_in_service && entity->tree != NULL); -+ -+ if (was_in_service) { -+ bfq_calc_finish(entity, entity->service); -+ sd->in_service_entity = NULL; -+ } else if (entity->tree == &st->active) -+ bfq_active_extract(st, entity); -+ else if (entity->tree == &st->idle) -+ bfq_idle_extract(st, entity); -+ else if (entity->tree != NULL) -+ BUG(); -+ -+ if (was_in_service || sd->next_in_service == entity) -+ ret = bfq_update_next_in_service(sd); -+ -+ if (!requeue || !bfq_gt(entity->finish, st->vtime)) -+ bfq_forget_entity(st, entity); -+ else -+ bfq_idle_insert(st, entity); -+ -+ BUG_ON(sd->in_service_entity == entity); -+ BUG_ON(sd->next_in_service == entity); -+ -+ return ret; -+} -+ -+/** -+ * bfq_deactivate_entity - deactivate an entity. -+ * @entity: the entity to deactivate. -+ * @requeue: true if the entity can be put on the idle tree -+ */ -+static void bfq_deactivate_entity(struct bfq_entity *entity, int requeue) -+{ -+ struct bfq_sched_data *sd; -+ struct bfq_entity *parent; -+ -+ for_each_entity_safe(entity, parent) { -+ sd = entity->sched_data; -+ -+ if (!__bfq_deactivate_entity(entity, requeue)) -+ /* -+ * The parent entity is still backlogged, and -+ * we don't need to update it as it is still -+ * in service. -+ */ -+ break; -+ -+ if (sd->next_in_service != NULL) -+ /* -+ * The parent entity is still backlogged and -+ * the budgets on the path towards the root -+ * need to be updated. -+ */ -+ goto update; -+ -+ /* -+ * If we reach there the parent is no more backlogged and -+ * we want to propagate the dequeue upwards. -+ */ -+ requeue = 1; -+ } -+ -+ return; -+ -+update: -+ entity = parent; -+ for_each_entity(entity) { -+ __bfq_activate_entity(entity); -+ -+ sd = entity->sched_data; -+ if (!bfq_update_next_in_service(sd)) -+ break; -+ } -+} -+ -+/** -+ * bfq_update_vtime - update vtime if necessary. -+ * @st: the service tree to act upon. -+ * -+ * If necessary update the service tree vtime to have at least one -+ * eligible entity, skipping to its start time. Assumes that the -+ * active tree of the device is not empty. -+ * -+ * NOTE: this hierarchical implementation updates vtimes quite often, -+ * we may end up with reactivated processes getting timestamps after a -+ * vtime skip done because we needed a ->first_active entity on some -+ * intermediate node. -+ */ -+static void bfq_update_vtime(struct bfq_service_tree *st) -+{ -+ struct bfq_entity *entry; -+ struct rb_node *node = st->active.rb_node; -+ -+ entry = rb_entry(node, struct bfq_entity, rb_node); -+ if (bfq_gt(entry->min_start, st->vtime)) { -+ st->vtime = entry->min_start; -+ bfq_forget_idle(st); -+ } -+} -+ -+/** -+ * bfq_first_active_entity - find the eligible entity with -+ * the smallest finish time -+ * @st: the service tree to select from. -+ * -+ * This function searches the first schedulable entity, starting from the -+ * root of the tree and going on the left every time on this side there is -+ * a subtree with at least one eligible (start >= vtime) entity. The path on -+ * the right is followed only if a) the left subtree contains no eligible -+ * entities and b) no eligible entity has been found yet. -+ */ -+static struct bfq_entity *bfq_first_active_entity(struct bfq_service_tree *st) -+{ -+ struct bfq_entity *entry, *first = NULL; -+ struct rb_node *node = st->active.rb_node; -+ -+ while (node != NULL) { -+ entry = rb_entry(node, struct bfq_entity, rb_node); -+left: -+ if (!bfq_gt(entry->start, st->vtime)) -+ first = entry; -+ -+ BUG_ON(bfq_gt(entry->min_start, st->vtime)); -+ -+ if (node->rb_left != NULL) { -+ entry = rb_entry(node->rb_left, -+ struct bfq_entity, rb_node); -+ if (!bfq_gt(entry->min_start, st->vtime)) { -+ node = node->rb_left; -+ goto left; -+ } -+ } -+ if (first != NULL) -+ break; -+ node = node->rb_right; -+ } -+ -+ BUG_ON(first == NULL && !RB_EMPTY_ROOT(&st->active)); -+ return first; -+} -+ -+/** -+ * __bfq_lookup_next_entity - return the first eligible entity in @st. -+ * @st: the service tree. -+ * -+ * Update the virtual time in @st and return the first eligible entity -+ * it contains. -+ */ -+static struct bfq_entity *__bfq_lookup_next_entity(struct bfq_service_tree *st, -+ bool force) -+{ -+ struct bfq_entity *entity, *new_next_in_service = NULL; -+ -+ if (RB_EMPTY_ROOT(&st->active)) -+ return NULL; -+ -+ bfq_update_vtime(st); -+ entity = bfq_first_active_entity(st); -+ BUG_ON(bfq_gt(entity->start, st->vtime)); -+ -+ /* -+ * If the chosen entity does not match with the sched_data's -+ * next_in_service and we are forcedly serving the IDLE priority -+ * class tree, bubble up budget update. -+ */ -+ if (unlikely(force && entity != entity->sched_data->next_in_service)) { -+ new_next_in_service = entity; -+ for_each_entity(new_next_in_service) -+ bfq_update_budget(new_next_in_service); -+ } -+ -+ return entity; -+} -+ -+/** -+ * bfq_lookup_next_entity - return the first eligible entity in @sd. -+ * @sd: the sched_data. -+ * @extract: if true the returned entity will be also extracted from @sd. -+ * -+ * NOTE: since we cache the next_in_service entity at each level of the -+ * hierarchy, the complexity of the lookup can be decreased with -+ * absolutely no effort just returning the cached next_in_service value; -+ * we prefer to do full lookups to test the consistency of * the data -+ * structures. -+ */ -+static struct bfq_entity *bfq_lookup_next_entity(struct bfq_sched_data *sd, -+ int extract, -+ struct bfq_data *bfqd) -+{ -+ struct bfq_service_tree *st = sd->service_tree; -+ struct bfq_entity *entity; -+ int i = 0; -+ -+ BUG_ON(sd->in_service_entity != NULL); -+ -+ if (bfqd != NULL && -+ jiffies - bfqd->bfq_class_idle_last_service > BFQ_CL_IDLE_TIMEOUT) { -+ entity = __bfq_lookup_next_entity(st + BFQ_IOPRIO_CLASSES - 1, -+ true); -+ if (entity != NULL) { -+ i = BFQ_IOPRIO_CLASSES - 1; -+ bfqd->bfq_class_idle_last_service = jiffies; -+ sd->next_in_service = entity; -+ } -+ } -+ for (; i < BFQ_IOPRIO_CLASSES; i++) { -+ entity = __bfq_lookup_next_entity(st + i, false); -+ if (entity != NULL) { -+ if (extract) { -+ bfq_check_next_in_service(sd, entity); -+ bfq_active_extract(st + i, entity); -+ sd->in_service_entity = entity; -+ sd->next_in_service = NULL; -+ } -+ break; -+ } -+ } -+ -+ return entity; -+} -+ -+/* -+ * Get next queue for service. -+ */ -+static struct bfq_queue *bfq_get_next_queue(struct bfq_data *bfqd) -+{ -+ struct bfq_entity *entity = NULL; -+ struct bfq_sched_data *sd; -+ struct bfq_queue *bfqq; -+ -+ BUG_ON(bfqd->in_service_queue != NULL); -+ -+ if (bfqd->busy_queues == 0) -+ return NULL; -+ -+ sd = &bfqd->root_group->sched_data; -+ for (; sd != NULL; sd = entity->my_sched_data) { -+ entity = bfq_lookup_next_entity(sd, 1, bfqd); -+ BUG_ON(entity == NULL); -+ entity->service = 0; -+ } -+ -+ bfqq = bfq_entity_to_bfqq(entity); -+ BUG_ON(bfqq == NULL); -+ -+ return bfqq; -+} -+ -+static void __bfq_bfqd_reset_in_service(struct bfq_data *bfqd) -+{ -+ if (bfqd->in_service_bic != NULL) { -+ put_io_context(bfqd->in_service_bic->icq.ioc); -+ bfqd->in_service_bic = NULL; -+ } -+ -+ bfqd->in_service_queue = NULL; -+ del_timer(&bfqd->idle_slice_timer); -+} -+ -+static void bfq_deactivate_bfqq(struct bfq_data *bfqd, struct bfq_queue *bfqq, -+ int requeue) -+{ -+ struct bfq_entity *entity = &bfqq->entity; -+ -+ if (bfqq == bfqd->in_service_queue) -+ __bfq_bfqd_reset_in_service(bfqd); -+ -+ bfq_deactivate_entity(entity, requeue); -+} -+ -+static void bfq_activate_bfqq(struct bfq_data *bfqd, struct bfq_queue *bfqq) -+{ -+ struct bfq_entity *entity = &bfqq->entity; -+ -+ bfq_activate_entity(entity); -+} -+ -+/* -+ * Called when the bfqq no longer has requests pending, remove it from -+ * the service tree. -+ */ -+static void bfq_del_bfqq_busy(struct bfq_data *bfqd, struct bfq_queue *bfqq, -+ int requeue) -+{ -+ BUG_ON(!bfq_bfqq_busy(bfqq)); -+ BUG_ON(!RB_EMPTY_ROOT(&bfqq->sort_list)); -+ -+ bfq_log_bfqq(bfqd, bfqq, "del from busy"); -+ -+ bfq_clear_bfqq_busy(bfqq); -+ -+ BUG_ON(bfqd->busy_queues == 0); -+ bfqd->busy_queues--; -+ -+ if (!bfqq->dispatched) { -+ bfq_weights_tree_remove(bfqd, &bfqq->entity, -+ &bfqd->queue_weights_tree); -+ if (!blk_queue_nonrot(bfqd->queue)) { -+ BUG_ON(!bfqd->busy_in_flight_queues); -+ bfqd->busy_in_flight_queues--; -+ if (bfq_bfqq_constantly_seeky(bfqq)) { -+ BUG_ON(!bfqd-> -+ const_seeky_busy_in_flight_queues); -+ bfqd->const_seeky_busy_in_flight_queues--; -+ } -+ } -+ } -+ if (bfqq->wr_coeff > 1) -+ bfqd->wr_busy_queues--; -+ -+ bfq_deactivate_bfqq(bfqd, bfqq, requeue); -+} -+ -+/* -+ * Called when an inactive queue receives a new request. -+ */ -+static void bfq_add_bfqq_busy(struct bfq_data *bfqd, struct bfq_queue *bfqq) -+{ -+ BUG_ON(bfq_bfqq_busy(bfqq)); -+ BUG_ON(bfqq == bfqd->in_service_queue); -+ -+ bfq_log_bfqq(bfqd, bfqq, "add to busy"); -+ -+ bfq_activate_bfqq(bfqd, bfqq); -+ -+ bfq_mark_bfqq_busy(bfqq); -+ bfqd->busy_queues++; -+ -+ if (!bfqq->dispatched) { -+ if (bfqq->wr_coeff == 1) -+ bfq_weights_tree_add(bfqd, &bfqq->entity, -+ &bfqd->queue_weights_tree); -+ if (!blk_queue_nonrot(bfqd->queue)) { -+ bfqd->busy_in_flight_queues++; -+ if (bfq_bfqq_constantly_seeky(bfqq)) -+ bfqd->const_seeky_busy_in_flight_queues++; -+ } -+ } -+ if (bfqq->wr_coeff > 1) -+ bfqd->wr_busy_queues++; -+} -diff -Nur linux-4.1.13.orig/block/Kconfig.iosched linux-4.1.13/block/Kconfig.iosched ---- linux-4.1.13.orig/block/Kconfig.iosched 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/block/Kconfig.iosched 2015-11-30 17:56:13.536140654 +0100 -@@ -39,6 +39,27 @@ - ---help--- - Enable group IO scheduling in CFQ. - -+config IOSCHED_BFQ -+ tristate "BFQ I/O scheduler" -+ default n -+ ---help--- -+ The BFQ I/O scheduler tries to distribute bandwidth among -+ all processes according to their weights. -+ It aims at distributing the bandwidth as desired, independently of -+ the disk parameters and with any workload. It also tries to -+ guarantee low latency to interactive and soft real-time -+ applications. If compiled built-in (saying Y here), BFQ can -+ be configured to support hierarchical scheduling. -+ -+config CGROUP_BFQIO -+ bool "BFQ hierarchical scheduling support" -+ depends on CGROUPS && IOSCHED_BFQ=y -+ default n -+ ---help--- -+ Enable hierarchical scheduling in BFQ, using the cgroups -+ filesystem interface. The name of the subsystem will be -+ bfqio. -+ - choice - prompt "Default I/O scheduler" - default DEFAULT_CFQ -@@ -52,6 +73,16 @@ - config DEFAULT_CFQ - bool "CFQ" if IOSCHED_CFQ=y - -+ config DEFAULT_BFQ -+ bool "BFQ" if IOSCHED_BFQ=y -+ help -+ Selects BFQ as the default I/O scheduler which will be -+ used by default for all block devices. -+ The BFQ I/O scheduler aims at distributing the bandwidth -+ as desired, independently of the disk parameters and with -+ any workload. It also tries to guarantee low latency to -+ interactive and soft real-time applications. -+ - config DEFAULT_NOOP - bool "No-op" - -@@ -61,6 +92,7 @@ - string - default "deadline" if DEFAULT_DEADLINE - default "cfq" if DEFAULT_CFQ -+ default "bfq" if DEFAULT_BFQ - default "noop" if DEFAULT_NOOP - - endmenu -diff -Nur linux-4.1.13.orig/block/Makefile linux-4.1.13/block/Makefile ---- linux-4.1.13.orig/block/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/block/Makefile 2015-11-30 17:56:13.536140654 +0100 -@@ -18,6 +18,7 @@ - obj-$(CONFIG_IOSCHED_NOOP) += noop-iosched.o - obj-$(CONFIG_IOSCHED_DEADLINE) += deadline-iosched.o - obj-$(CONFIG_IOSCHED_CFQ) += cfq-iosched.o -+obj-$(CONFIG_IOSCHED_BFQ) += bfq-iosched.o - - obj-$(CONFIG_BLOCK_COMPAT) += compat_ioctl.o - obj-$(CONFIG_BLK_CMDLINE_PARSER) += cmdline-parser.o -diff -Nur linux-4.1.13.orig/Documentation/devicetree/bindings/fb/fsl_ipuv3_fb.txt linux-4.1.13/Documentation/devicetree/bindings/fb/fsl_ipuv3_fb.txt ---- linux-4.1.13.orig/Documentation/devicetree/bindings/fb/fsl_ipuv3_fb.txt 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/Documentation/devicetree/bindings/fb/fsl_ipuv3_fb.txt 2015-11-30 17:56:13.540140388 +0100 -@@ -0,0 +1,118 @@ -+* FSL IPUv3 Display/FB -+ -+The FSL IPUv3 is Image Processing Unit version 3, a part of video and graphics -+subsystem in an application processor. The goal of the IPU is to provide -+comprehensive support for the flow of data from an image sensor or/and to a -+display device. -+ -+Two IPU units are on the imx6q SOC while only one IPU unit on the imx6dl SOC. -+Each IPU unit has two display interfaces. -+ -+Required properties for IPU: -+- bypass_reset :Bypass reset to avoid display channel being. -+ stopped by probe since it may start to work in bootloader: 0 or 1. -+- compatible : should be "fsl,imx6q-ipu". -+- reg : the register address range. -+- interrupts : the error and sync interrupts request. -+- clocks : the clock sources that it depends on. -+- clock-names: the related clock names. -+- resets : IPU reset specifier. See reset.txt and fsl,imx-src.txt in -+ Documentation/devicetree/bindings/reset/ for details. -+ -+Required properties for fb: -+- compatible : should be "fsl,mxc_sdc_fb". -+- disp_dev : display device: "ldb", "lcd", "hdmi", "mipi_dsi", "adv739x". -+- mode_str : video mode string: "LDB-XGA" or "LDB-1080P60" for ldb, -+ "CLAA-WVGA" for lcd, "TRULY-WVGA" for TRULY mipi_dsi lcd panel, -+ "1920x1080M@60" for hdmi, "BT656-NTSC" or "BT656-PAL" for adv739x. -+- default_bpp : default bits per pixel: 8/16/24/32 -+- int_clk : use internal clock as pixel clock: 0 or 1 -+- late_init : to avoid display channel being re-initialized -+ as we've probably setup the channel in bootloader: 0 or 1 -+- interface_pix_fmt : display interface pixel format as below: -+ RGB666 IPU_PIX_FMT_RGB666 -+ RGB565 IPU_PIX_FMT_RGB565 -+ RGB24 IPU_PIX_FMT_RGB24 -+ BGR24 IPU_PIX_FMT_BGR24 -+ GBR24 IPU_PIX_FMT_GBR24 -+ YUV444 IPU_PIX_FMT_YUV444 -+ YUYV IPU_PIX_FMT_YUYV -+ UYVY IPU_PIX_FMT_UYVY -+ YVYV IPU_PIX_FMT_YVYU -+ VYUY IPU_PIX_FMT_VYUY -+ -+Required properties for display: -+- compatible : should be "fsl,lcd" for lcd panel -+- reg : the register address range if necessary to have. -+- interrupts : the error and sync interrupts if necessary to have. -+- clocks : the clock sources that it depends on if necessary to have. -+- clock-names: the related clock names if necessary to have. -+- ipu_id : ipu id for the first display device: 0 or 1 -+- disp_id : display interface id for the first display interface: 0 or 1 -+- default_ifmt : save as above display interface pixel format for lcd -+- pinctrl-names : should be "default" -+- pinctrl-0 : should be pinctrl_ipu1_1 or pinctrl_ipu2_1, which depends on the -+ IPU connected. -+- gpr : the mux controller for the display engine's display interfaces and the display encoder -+ (only valid for mipi dsi now). -+- disp-power-on-supply : the regulator to control display panel's power. -+ (only valid for mipi dsi now). -+- resets : the gpio pin to reset the display device(only valid for mipi display panel now). -+- lcd_panel : the video mode name for the display device(only valid for mipi display panel now). -+- dev_id : the display engine's identity within the system, which intends to replace ipu_id -+ (only valid for mipi dsi now). -+ -+Example for IPU: -+ ipu1: ipu@02400000 { -+ compatible = "fsl,imx6q-ipu"; -+ reg = <0x02400000 0x400000>; -+ interrupts = <0 6 0x4 0 5 0x4>; -+ clocks = <&clks 130>, <&clks 131>, <&clks 132>, -+ <&clks 39>, <&clks 40>, -+ <&clks 135>, <&clks 136>; -+ clock-names = "bus", "di0", "di1", -+ "di0_sel", "di1_sel", -+ "ldb_di0", "ldb_di1"; -+ resets = <&src 2>; -+ bypass_reset = <0>; -+ }; -+ -+Example for fb: -+ fb0 { -+ compatible = "fsl,mxc_sdc_fb"; -+ disp_dev = "ldb"; -+ interface_pix_fmt = "RGB666"; -+ mode_str ="LDB-XGA"; -+ default_bpp = <16>; -+ int_clk = <0>; -+ late_init = <0>; -+ status = "okay"; -+ }; -+ -+Example for mipi dsi display: -+ mipi_dsi: mipi@021e0000 { -+ compatible = "fsl,imx6q-mipi-dsi"; -+ reg = <0x021e0000 0x4000>; -+ interrupts = <0 102 0x04>; -+ gpr = <&gpr>; -+ clocks = <&clks 138>, <&clks 204>; -+ clock-names = "mipi_pllref_clk", "mipi_cfg_clk"; -+ dev_id = <0>; -+ disp_id = <0>; -+ lcd_panel = "TRULY-WVGA"; -+ disp-power-on-supply = <®_mipi_dsi_pwr_on> -+ resets = <&mipi_dsi_reset>; -+ status = "okay"; -+ }; -+ -+Example for adv739x CVBS output: -+ fb0 { -+ compatible = "fsl,mxc_sdc_fb"; -+ disp_dev = "adv739x"; -+ interface_pix_fmt = "BT656"; -+ mode_str ="BT656-NTSC"; -+ default_bpp = <16>; -+ int_clk = <0>; -+ late_init = <0>; -+ status = "okay"; -+ }; -diff -Nur linux-4.1.13.orig/Documentation/devicetree/bindings/regulator/ltc3676.txt linux-4.1.13/Documentation/devicetree/bindings/regulator/ltc3676.txt ---- linux-4.1.13.orig/Documentation/devicetree/bindings/regulator/ltc3676.txt 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/Documentation/devicetree/bindings/regulator/ltc3676.txt 2015-11-30 17:56:13.540140388 +0100 -@@ -0,0 +1,103 @@ -+Linear Technology LTC3676 8-output regulators -+ -+Required properties: -+- compatible: "lltc,ltc3676" -+- reg: I2C slave address -+ -+Required child node: -+- regulators: Contains eight regulator child nodes sw1, sw2, sw3, sw4, -+ ldo1, ldo2, ldo3, and ldo4, specifying the initialization data as -+ documented in Documentation/devicetree/bindings/regulator/regulator.txt. -+ -+Each regulator is defined using the standard binding for regulators. The -+nodes for sw1, sw2, sw3, sw4, ldo1, ldo2 and ldo4 additionally need to specify -+the resistor values of their external feedback voltage dividers: -+ -+Required properties (not on ldo3): -+- lltc,fb-voltage-divider: An array of two integers containing the resistor -+ values R1 and R2 of the feedback voltage divider in ohms. -+ -+Regulators sw1, sw2, sw3, sw4 can regulate the feedback reference from: -+412.5mV to 800mV in 12.5 mV steps. The output voltage thus ranges between -+0.4125 * (1 + R1/R2) V and 0.8 * (1 + R1/R2) V. -+ -+Regulators ldo1, ldo2, and ldo4 have a fixed 0.725 V reference and thus output -+0.725 * (1 + R1/R2) V. The ldo3 regulator is fixed to 1.8 V. The ldo1 standby -+regulator can not be disabled and thus should have the regulator-always-on -+property set. -+ -+Example: -+ -+ ltc3676: pmic@3c { -+ compatible = "lltc,ltc3676"; -+ reg = <0x3c>; -+ -+ regulators { -+ sw1_reg: sw1 { -+ regulator-min-microvolt = <674400>; -+ regulator-max-microvolt = <1308000>; -+ lltc,fb-voltage-divider = <127000 200000>; -+ regulator-ramp-delay = <7000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ sw2_reg: sw2 { -+ regulator-min-microvolt = <1033310>; -+ regulator-max-microvolt = <200400>; -+ lltc,fb-voltage-divider = <301000 200000>; -+ regulator-ramp-delay = <7000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ sw3_reg: sw3 { -+ regulator-min-microvolt = <674400>; -+ regulator-max-microvolt = <130800>; -+ lltc,fb-voltage-divider = <127000 200000>; -+ regulator-ramp-delay = <7000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ sw4_reg: sw4 { -+ regulator-min-microvolt = <868310>; -+ regulator-max-microvolt = <168400>; -+ lltc,fb-voltage-divider = <221000 200000>; -+ regulator-ramp-delay = <7000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ /* unused */ -+ ldo1_reg: ldo1 { -+ regulator-min-microvolt = <0>; -+ regulator-max-microvolt = <0>; -+ lltc,fb-voltage-divider = <0 0>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo2_reg: ldo2 { -+ regulator-min-microvolt = <2490375>; -+ regulator-max-microvolt = <2490375>; -+ lltc,fb-voltage-divider = <487000 200000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo3_reg: ldo3 { -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ }; -+ -+ ldo4_reg: ldo4 { -+ regulator-min-microvolt = <3023250>; -+ regulator-max-microvolt = <3023250>; -+ lltc,fb-voltage-divider = <634000 200000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ }; -+ }; -diff -Nur linux-4.1.13.orig/Documentation/devicetree/bindings/vendor-prefixes.txt linux-4.1.13/Documentation/devicetree/bindings/vendor-prefixes.txt ---- linux-4.1.13.orig/Documentation/devicetree/bindings/vendor-prefixes.txt 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/Documentation/devicetree/bindings/vendor-prefixes.txt 2015-11-30 17:56:13.540140388 +0100 -@@ -201,6 +201,7 @@ - variscite Variscite Ltd. - via VIA Technologies, Inc. - virtio Virtual I/O Device Specification, developed by the OASIS consortium -+vivante Vivante Corporation - voipac Voipac Technologies s.r.o. - winbond Winbond Electronics corp. - wlf Wolfson Microelectronics -diff -Nur linux-4.1.13.orig/Documentation/tda1997x linux-4.1.13/Documentation/tda1997x ---- linux-4.1.13.orig/Documentation/tda1997x 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/Documentation/tda1997x 2015-11-30 17:56:13.540140388 +0100 -@@ -0,0 +1,31 @@ -+The NXP TDA19971/19972 are HDMI receiver devices that decode HDMI -+input signals and present a configurable parallel video output bus and -+audio output bus. The internal video bus is 36bits while the output bus -+differs per device. These devices offer High Definition (HD) video resolutions -+up to 1080p50/60 or WUXGA and HD audio formats up to 8 channels such as DTS HD -+and Dolby True HD. The chips optionally include an HDCP 1.4 engine with -+pre-programmed keys stored into an internal NV memory. Additionally the chips -+also supports several HDMI 1.4b options such as 3D formats up to 1080p50/60, -+Deep Colors up to 36bpp and extended colorimetry. -+ -+The TDA19971 has one HDMI input (HDMI-A) and 24bit output bus and the TDA19972 -+has two HDMI inputs (HDMI-A/B) and a 36bit video output bus. -+ -+Driver Details: -+--------------- -+ -+The chips respond to two i2c slave addresses, the first allows access to -+HDMI input, audio, and video status and configuration and the second allows -+access to CEC. -+ -+The tda1997x-core driver attaches to the i2c slave that controls the device. -+It also manages the 2nd i2c slave for CEC. The platform data structure -+provides details about the desired video output bus configuration and the -+desired audio output bus configuration. An ASoC codec driver is also provided -+however this is merely a skeleton driver as the audio output format cannot -+be changed and is dependent upon the HDMI input signal. A separate platform -+specific device video driver can interact with the core to obtain information -+about the video data format which is dependent upon the HDMI input signal. A -+separate platform specific ASoC SoC DAI driver can interact with the core -+to obtain information about the audio data format which is dependent upon -+the HDMI input signal. -diff -Nur linux-4.1.13.orig/drivers/bluetooth/bt3c_cs.c linux-4.1.13/drivers/bluetooth/bt3c_cs.c ---- linux-4.1.13.orig/drivers/bluetooth/bt3c_cs.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/bluetooth/bt3c_cs.c 2015-11-30 17:56:13.540140388 +0100 -@@ -202,9 +202,8 @@ - /* Send frame */ - len = bt3c_write(iobase, 256, skb->data, skb->len); - -- if (len != skb->len) { -+ if (len != skb->len) - BT_ERR("Very strange"); -- } - - kfree_skb(skb); - -diff -Nur linux-4.1.13.orig/drivers/bluetooth/btbcm.c linux-4.1.13/drivers/bluetooth/btbcm.c ---- linux-4.1.13.orig/drivers/bluetooth/btbcm.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/bluetooth/btbcm.c 2015-11-30 17:56:13.540140388 +0100 -@@ -33,6 +33,7 @@ - #define VERSION "0.1" - - #define BDADDR_BCM20702A0 (&(bdaddr_t) {{0x00, 0xa0, 0x02, 0x70, 0x20, 0x00}}) -+#define BDADDR_BCM4324B3 (&(bdaddr_t) {{0x00, 0x00, 0x00, 0xb3, 0x24, 0x43}}) - - int btbcm_check_bdaddr(struct hci_dev *hdev) - { -@@ -55,17 +56,19 @@ - } - - bda = (struct hci_rp_read_bd_addr *)skb->data; -- if (bda->status) { -- BT_ERR("%s: BCM: Device address result failed (%02x)", -- hdev->name, bda->status); -- kfree_skb(skb); -- return -bt_to_errno(bda->status); -- } - -- /* The address 00:20:70:02:A0:00 indicates a BCM20702A0 controller -+ /* Check if the address indicates a controller with either an -+ * invalid or default address. In both cases the device needs -+ * to be marked as not having a valid address. -+ * -+ * The address 00:20:70:02:A0:00 indicates a BCM20702A0 controller - * with no configured address. -+ * -+ * The address 43:24:B3:00:00:00 indicates a BCM4324B3 controller -+ * with waiting for configuration state. - */ -- if (!bacmp(&bda->bdaddr, BDADDR_BCM20702A0)) { -+ if (!bacmp(&bda->bdaddr, BDADDR_BCM20702A0) || -+ !bacmp(&bda->bdaddr, BDADDR_BCM4324B3)) { - BT_INFO("%s: BCM: Using default device address (%pMR)", - hdev->name, &bda->bdaddr); - set_bit(HCI_QUIRK_INVALID_BDADDR, &hdev->quirks); -@@ -95,21 +98,14 @@ - } - EXPORT_SYMBOL_GPL(btbcm_set_bdaddr); - --int btbcm_patchram(struct hci_dev *hdev, const char *firmware) -+int btbcm_patchram(struct hci_dev *hdev, const struct firmware *fw) - { - const struct hci_command_hdr *cmd; -- const struct firmware *fw; - const u8 *fw_ptr; - size_t fw_size; - struct sk_buff *skb; - u16 opcode; -- int err; -- -- err = request_firmware(&fw, firmware, &hdev->dev); -- if (err < 0) { -- BT_INFO("%s: BCM: Patch %s not found", hdev->name, firmware); -- return err; -- } -+ int err = 0; - - /* Start Download */ - skb = __hci_cmd_sync(hdev, 0xfc2e, 0, NULL, HCI_INIT_TIMEOUT); -@@ -135,8 +131,7 @@ - fw_size -= sizeof(*cmd); - - if (fw_size < cmd->plen) { -- BT_ERR("%s: BCM: Patch %s is corrupted", hdev->name, -- firmware); -+ BT_ERR("%s: BCM: Patch is corrupted", hdev->name); - err = -EINVAL; - goto done; - } -@@ -162,7 +157,6 @@ - msleep(250); - - done: -- release_firmware(fw); - return err; - } - EXPORT_SYMBOL(btbcm_patchram); -@@ -248,9 +242,101 @@ - const char *name; - } bcm_uart_subver_table[] = { - { 0x410e, "BCM43341B0" }, /* 002.001.014 */ -+ { 0x4406, "BCM4324B3" }, /* 002.004.006 */ -+ { 0x610c, "BCM4354" }, /* 003.001.012 */ - { } - }; - -+int btbcm_initialize(struct hci_dev *hdev, char *fw_name, size_t len) -+{ -+ u16 subver, rev; -+ const char *hw_name = NULL; -+ struct sk_buff *skb; -+ struct hci_rp_read_local_version *ver; -+ int i, err; -+ -+ /* Reset */ -+ err = btbcm_reset(hdev); -+ if (err) -+ return err; -+ -+ /* Read Local Version Info */ -+ skb = btbcm_read_local_version(hdev); -+ if (IS_ERR(skb)) -+ return PTR_ERR(skb); -+ -+ ver = (struct hci_rp_read_local_version *)skb->data; -+ rev = le16_to_cpu(ver->hci_rev); -+ subver = le16_to_cpu(ver->lmp_subver); -+ kfree_skb(skb); -+ -+ /* Read Verbose Config Version Info */ -+ skb = btbcm_read_verbose_config(hdev); -+ if (IS_ERR(skb)) -+ return PTR_ERR(skb); -+ -+ BT_INFO("%s: BCM: chip id %u", hdev->name, skb->data[1]); -+ kfree_skb(skb); -+ -+ switch ((rev & 0xf000) >> 12) { -+ case 0: -+ case 1: -+ case 3: -+ for (i = 0; bcm_uart_subver_table[i].name; i++) { -+ if (subver == bcm_uart_subver_table[i].subver) { -+ hw_name = bcm_uart_subver_table[i].name; -+ break; -+ } -+ } -+ -+ snprintf(fw_name, len, "brcm/%s.hcd", hw_name ? : "BCM"); -+ break; -+ default: -+ return 0; -+ } -+ -+ BT_INFO("%s: %s (%3.3u.%3.3u.%3.3u) build %4.4u", hdev->name, -+ hw_name ? : "BCM", (subver & 0x7000) >> 13, -+ (subver & 0x1f00) >> 8, (subver & 0x00ff), rev & 0x0fff); -+ -+ return 0; -+} -+EXPORT_SYMBOL_GPL(btbcm_initialize); -+ -+int btbcm_finalize(struct hci_dev *hdev) -+{ -+ struct sk_buff *skb; -+ struct hci_rp_read_local_version *ver; -+ u16 subver, rev; -+ int err; -+ -+ /* Reset */ -+ err = btbcm_reset(hdev); -+ if (err) -+ return err; -+ -+ /* Read Local Version Info */ -+ skb = btbcm_read_local_version(hdev); -+ if (IS_ERR(skb)) -+ return PTR_ERR(skb); -+ -+ ver = (struct hci_rp_read_local_version *)skb->data; -+ rev = le16_to_cpu(ver->hci_rev); -+ subver = le16_to_cpu(ver->lmp_subver); -+ kfree_skb(skb); -+ -+ BT_INFO("%s: BCM (%3.3u.%3.3u.%3.3u) build %4.4u", hdev->name, -+ (subver & 0x7000) >> 13, (subver & 0x1f00) >> 8, -+ (subver & 0x00ff), rev & 0x0fff); -+ -+ btbcm_check_bdaddr(hdev); -+ -+ set_bit(HCI_QUIRK_STRICT_DUPLICATE_FILTER, &hdev->quirks); -+ -+ return 0; -+} -+EXPORT_SYMBOL_GPL(btbcm_finalize); -+ - static const struct { - u16 subver; - const char *name; -@@ -271,6 +357,7 @@ - int btbcm_setup_patchram(struct hci_dev *hdev) - { - char fw_name[64]; -+ const struct firmware *fw; - u16 subver, rev, pid, vid; - const char *hw_name = NULL; - struct sk_buff *skb; -@@ -302,6 +389,7 @@ - - switch ((rev & 0xf000) >> 12) { - case 0: -+ case 3: - for (i = 0; bcm_uart_subver_table[i].name; i++) { - if (subver == bcm_uart_subver_table[i].subver) { - hw_name = bcm_uart_subver_table[i].name; -@@ -341,9 +429,15 @@ - hw_name ? : "BCM", (subver & 0x7000) >> 13, - (subver & 0x1f00) >> 8, (subver & 0x00ff), rev & 0x0fff); - -- err = btbcm_patchram(hdev, fw_name); -- if (err == -ENOENT) -+ err = request_firmware(&fw, fw_name, &hdev->dev); -+ if (err < 0) { -+ BT_INFO("%s: BCM: Patch %s not found", hdev->name, fw_name); - return 0; -+ } -+ -+ btbcm_patchram(hdev, fw); -+ -+ release_firmware(fw); - - /* Reset */ - err = btbcm_reset(hdev); -diff -Nur linux-4.1.13.orig/drivers/bluetooth/btbcm.h linux-4.1.13/drivers/bluetooth/btbcm.h ---- linux-4.1.13.orig/drivers/bluetooth/btbcm.h 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/bluetooth/btbcm.h 2015-11-30 17:56:13.540140388 +0100 -@@ -21,15 +21,61 @@ - * - */ - -+#define BCM_UART_CLOCK_48MHZ 0x01 -+#define BCM_UART_CLOCK_24MHZ 0x02 -+ -+struct bcm_update_uart_baud_rate { -+ __le16 zero; -+ __le32 baud_rate; -+} __packed; -+ -+struct bcm_write_uart_clock_setting { -+ __u8 type; -+} __packed; -+ -+struct bcm_set_sleep_mode { -+ __u8 sleep_mode; -+ __u8 idle_host; -+ __u8 idle_dev; -+ __u8 bt_wake_active; -+ __u8 host_wake_active; -+ __u8 allow_host_sleep; -+ __u8 combine_modes; -+ __u8 tristate_control; -+ __u8 usb_auto_sleep; -+ __u8 usb_resume_timeout; -+ __u8 pulsed_host_wake; -+ __u8 break_to_host; -+} __packed; -+ -+struct bcm_set_pcm_int_params { -+ __u8 routing; -+ __u8 rate; -+ __u8 frame_sync; -+ __u8 sync_mode; -+ __u8 clock_mode; -+} __packed; -+ -+struct bcm_set_pcm_format_params { -+ __u8 lsb_first; -+ __u8 fill_value; -+ __u8 fill_method; -+ __u8 fill_num; -+ __u8 right_justify; -+} __packed; -+ - #if IS_ENABLED(CONFIG_BT_BCM) - - int btbcm_check_bdaddr(struct hci_dev *hdev); - int btbcm_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr); --int btbcm_patchram(struct hci_dev *hdev, const char *firmware); -+int btbcm_patchram(struct hci_dev *hdev, const struct firmware *fw); - - int btbcm_setup_patchram(struct hci_dev *hdev); - int btbcm_setup_apple(struct hci_dev *hdev); - -+int btbcm_initialize(struct hci_dev *hdev, char *fw_name, size_t len); -+int btbcm_finalize(struct hci_dev *hdev); -+ - #else - - static inline int btbcm_check_bdaddr(struct hci_dev *hdev) -@@ -42,7 +88,7 @@ - return -EOPNOTSUPP; - } - --static inline int btbcm_patchram(struct hci_dev *hdev, const char *firmware) -+static inline int btbcm_patchram(struct hci_dev *hdev, const struct firmware *fw) - { - return -EOPNOTSUPP; - } -@@ -56,5 +102,16 @@ - { - return 0; - } -+ -+static inline int btbcm_initialize(struct hci_dev *hdev, char *fw_name, -+ size_t len) -+{ -+ return 0; -+} -+ -+static inline int btbcm_finalize(struct hci_dev *hdev) -+{ -+ return 0; -+} - - #endif -diff -Nur linux-4.1.13.orig/drivers/bluetooth/btintel.c linux-4.1.13/drivers/bluetooth/btintel.c ---- linux-4.1.13.orig/drivers/bluetooth/btintel.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/bluetooth/btintel.c 2015-11-30 17:56:13.540140388 +0100 -@@ -53,12 +53,6 @@ - } - - bda = (struct hci_rp_read_bd_addr *)skb->data; -- if (bda->status) { -- BT_ERR("%s: Intel device address result failed (%02x)", -- hdev->name, bda->status); -- kfree_skb(skb); -- return -bt_to_errno(bda->status); -- } - - /* For some Intel based controllers, the default Bluetooth device - * address 00:03:19:9E:8B:00 can be found. These controllers are -diff -Nur linux-4.1.13.orig/drivers/bluetooth/btmrvl_sdio.c linux-4.1.13/drivers/bluetooth/btmrvl_sdio.c ---- linux-4.1.13.orig/drivers/bluetooth/btmrvl_sdio.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/bluetooth/btmrvl_sdio.c 2015-11-30 17:56:13.540140388 +0100 -@@ -1217,7 +1217,7 @@ - unsigned int reg, reg_start, reg_end; - enum rdwr_status stat; - u8 *dbg_ptr, *end_ptr, *fw_dump_data, *fw_dump_ptr; -- u8 dump_num, idx, i, read_reg, doneflag = 0; -+ u8 dump_num = 0, idx, i, read_reg, doneflag = 0; - u32 memory_size, fw_dump_len = 0; - - /* dump sdio register first */ -diff -Nur linux-4.1.13.orig/drivers/bluetooth/btrtl.c linux-4.1.13/drivers/bluetooth/btrtl.c ---- linux-4.1.13.orig/drivers/bluetooth/btrtl.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/bluetooth/btrtl.c 2015-11-30 17:56:13.540140388 +0100 -@@ -0,0 +1,390 @@ -+/* -+ * Bluetooth support for Realtek devices -+ * -+ * Copyright (C) 2015 Endless Mobile, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include "btrtl.h" -+ -+#define VERSION "0.1" -+ -+#define RTL_EPATCH_SIGNATURE "Realtech" -+#define RTL_ROM_LMP_3499 0x3499 -+#define RTL_ROM_LMP_8723A 0x1200 -+#define RTL_ROM_LMP_8723B 0x8723 -+#define RTL_ROM_LMP_8821A 0x8821 -+#define RTL_ROM_LMP_8761A 0x8761 -+ -+static int rtl_read_rom_version(struct hci_dev *hdev, u8 *version) -+{ -+ struct rtl_rom_version_evt *rom_version; -+ struct sk_buff *skb; -+ -+ /* Read RTL ROM version command */ -+ skb = __hci_cmd_sync(hdev, 0xfc6d, 0, NULL, HCI_INIT_TIMEOUT); -+ if (IS_ERR(skb)) { -+ BT_ERR("%s: Read ROM version failed (%ld)", -+ hdev->name, PTR_ERR(skb)); -+ return PTR_ERR(skb); -+ } -+ -+ if (skb->len != sizeof(*rom_version)) { -+ BT_ERR("%s: RTL version event length mismatch", hdev->name); -+ kfree_skb(skb); -+ return -EIO; -+ } -+ -+ rom_version = (struct rtl_rom_version_evt *)skb->data; -+ BT_INFO("%s: rom_version status=%x version=%x", -+ hdev->name, rom_version->status, rom_version->version); -+ -+ *version = rom_version->version; -+ -+ kfree_skb(skb); -+ return 0; -+} -+ -+static int rtl8723b_parse_firmware(struct hci_dev *hdev, u16 lmp_subver, -+ const struct firmware *fw, -+ unsigned char **_buf) -+{ -+ const u8 extension_sig[] = { 0x51, 0x04, 0xfd, 0x77 }; -+ struct rtl_epatch_header *epatch_info; -+ unsigned char *buf; -+ int i, ret, len; -+ size_t min_size; -+ u8 opcode, length, data, rom_version = 0; -+ int project_id = -1; -+ const unsigned char *fwptr, *chip_id_base; -+ const unsigned char *patch_length_base, *patch_offset_base; -+ u32 patch_offset = 0; -+ u16 patch_length, num_patches; -+ const u16 project_id_to_lmp_subver[] = { -+ RTL_ROM_LMP_8723A, -+ RTL_ROM_LMP_8723B, -+ RTL_ROM_LMP_8821A, -+ RTL_ROM_LMP_8761A -+ }; -+ -+ ret = rtl_read_rom_version(hdev, &rom_version); -+ if (ret) -+ return ret; -+ -+ min_size = sizeof(struct rtl_epatch_header) + sizeof(extension_sig) + 3; -+ if (fw->size < min_size) -+ return -EINVAL; -+ -+ fwptr = fw->data + fw->size - sizeof(extension_sig); -+ if (memcmp(fwptr, extension_sig, sizeof(extension_sig)) != 0) { -+ BT_ERR("%s: extension section signature mismatch", hdev->name); -+ return -EINVAL; -+ } -+ -+ /* Loop from the end of the firmware parsing instructions, until -+ * we find an instruction that identifies the "project ID" for the -+ * hardware supported by this firwmare file. -+ * Once we have that, we double-check that that project_id is suitable -+ * for the hardware we are working with. -+ */ -+ while (fwptr >= fw->data + (sizeof(struct rtl_epatch_header) + 3)) { -+ opcode = *--fwptr; -+ length = *--fwptr; -+ data = *--fwptr; -+ -+ BT_DBG("check op=%x len=%x data=%x", opcode, length, data); -+ -+ if (opcode == 0xff) /* EOF */ -+ break; -+ -+ if (length == 0) { -+ BT_ERR("%s: found instruction with length 0", -+ hdev->name); -+ return -EINVAL; -+ } -+ -+ if (opcode == 0 && length == 1) { -+ project_id = data; -+ break; -+ } -+ -+ fwptr -= length; -+ } -+ -+ if (project_id < 0) { -+ BT_ERR("%s: failed to find version instruction", hdev->name); -+ return -EINVAL; -+ } -+ -+ if (project_id >= ARRAY_SIZE(project_id_to_lmp_subver)) { -+ BT_ERR("%s: unknown project id %d", hdev->name, project_id); -+ return -EINVAL; -+ } -+ -+ if (lmp_subver != project_id_to_lmp_subver[project_id]) { -+ BT_ERR("%s: firmware is for %x but this is a %x", hdev->name, -+ project_id_to_lmp_subver[project_id], lmp_subver); -+ return -EINVAL; -+ } -+ -+ epatch_info = (struct rtl_epatch_header *)fw->data; -+ if (memcmp(epatch_info->signature, RTL_EPATCH_SIGNATURE, 8) != 0) { -+ BT_ERR("%s: bad EPATCH signature", hdev->name); -+ return -EINVAL; -+ } -+ -+ num_patches = le16_to_cpu(epatch_info->num_patches); -+ BT_DBG("fw_version=%x, num_patches=%d", -+ le32_to_cpu(epatch_info->fw_version), num_patches); -+ -+ /* After the rtl_epatch_header there is a funky patch metadata section. -+ * Assuming 2 patches, the layout is: -+ * ChipID1 ChipID2 PatchLength1 PatchLength2 PatchOffset1 PatchOffset2 -+ * -+ * Find the right patch for this chip. -+ */ -+ min_size += 8 * num_patches; -+ if (fw->size < min_size) -+ return -EINVAL; -+ -+ chip_id_base = fw->data + sizeof(struct rtl_epatch_header); -+ patch_length_base = chip_id_base + (sizeof(u16) * num_patches); -+ patch_offset_base = patch_length_base + (sizeof(u16) * num_patches); -+ for (i = 0; i < num_patches; i++) { -+ u16 chip_id = get_unaligned_le16(chip_id_base + -+ (i * sizeof(u16))); -+ if (chip_id == rom_version + 1) { -+ patch_length = get_unaligned_le16(patch_length_base + -+ (i * sizeof(u16))); -+ patch_offset = get_unaligned_le32(patch_offset_base + -+ (i * sizeof(u32))); -+ break; -+ } -+ } -+ -+ if (!patch_offset) { -+ BT_ERR("%s: didn't find patch for chip id %d", -+ hdev->name, rom_version); -+ return -EINVAL; -+ } -+ -+ BT_DBG("length=%x offset=%x index %d", patch_length, patch_offset, i); -+ min_size = patch_offset + patch_length; -+ if (fw->size < min_size) -+ return -EINVAL; -+ -+ /* Copy the firmware into a new buffer and write the version at -+ * the end. -+ */ -+ len = patch_length; -+ buf = kmemdup(fw->data + patch_offset, patch_length, GFP_KERNEL); -+ if (!buf) -+ return -ENOMEM; -+ -+ memcpy(buf + patch_length - 4, &epatch_info->fw_version, 4); -+ -+ *_buf = buf; -+ return len; -+} -+ -+static int rtl_download_firmware(struct hci_dev *hdev, -+ const unsigned char *data, int fw_len) -+{ -+ struct rtl_download_cmd *dl_cmd; -+ int frag_num = fw_len / RTL_FRAG_LEN + 1; -+ int frag_len = RTL_FRAG_LEN; -+ int ret = 0; -+ int i; -+ -+ dl_cmd = kmalloc(sizeof(struct rtl_download_cmd), GFP_KERNEL); -+ if (!dl_cmd) -+ return -ENOMEM; -+ -+ for (i = 0; i < frag_num; i++) { -+ struct sk_buff *skb; -+ -+ BT_DBG("download fw (%d/%d)", i, frag_num); -+ -+ dl_cmd->index = i; -+ if (i == (frag_num - 1)) { -+ dl_cmd->index |= 0x80; /* data end */ -+ frag_len = fw_len % RTL_FRAG_LEN; -+ } -+ memcpy(dl_cmd->data, data, frag_len); -+ -+ /* Send download command */ -+ skb = __hci_cmd_sync(hdev, 0xfc20, frag_len + 1, dl_cmd, -+ HCI_INIT_TIMEOUT); -+ if (IS_ERR(skb)) { -+ BT_ERR("%s: download fw command failed (%ld)", -+ hdev->name, PTR_ERR(skb)); -+ ret = -PTR_ERR(skb); -+ goto out; -+ } -+ -+ if (skb->len != sizeof(struct rtl_download_response)) { -+ BT_ERR("%s: download fw event length mismatch", -+ hdev->name); -+ kfree_skb(skb); -+ ret = -EIO; -+ goto out; -+ } -+ -+ kfree_skb(skb); -+ data += RTL_FRAG_LEN; -+ } -+ -+out: -+ kfree(dl_cmd); -+ return ret; -+} -+ -+static int btrtl_setup_rtl8723a(struct hci_dev *hdev) -+{ -+ const struct firmware *fw; -+ int ret; -+ -+ BT_INFO("%s: rtl: loading rtl_bt/rtl8723a_fw.bin", hdev->name); -+ ret = request_firmware(&fw, "rtl_bt/rtl8723a_fw.bin", &hdev->dev); -+ if (ret < 0) { -+ BT_ERR("%s: Failed to load rtl_bt/rtl8723a_fw.bin", hdev->name); -+ return ret; -+ } -+ -+ if (fw->size < 8) { -+ ret = -EINVAL; -+ goto out; -+ } -+ -+ /* Check that the firmware doesn't have the epatch signature -+ * (which is only for RTL8723B and newer). -+ */ -+ if (!memcmp(fw->data, RTL_EPATCH_SIGNATURE, 8)) { -+ BT_ERR("%s: unexpected EPATCH signature!", hdev->name); -+ ret = -EINVAL; -+ goto out; -+ } -+ -+ ret = rtl_download_firmware(hdev, fw->data, fw->size); -+ -+out: -+ release_firmware(fw); -+ return ret; -+} -+ -+static int btrtl_setup_rtl8723b(struct hci_dev *hdev, u16 lmp_subver, -+ const char *fw_name) -+{ -+ unsigned char *fw_data = NULL; -+ const struct firmware *fw; -+ int ret; -+ -+ BT_INFO("%s: rtl: loading %s", hdev->name, fw_name); -+ ret = request_firmware(&fw, fw_name, &hdev->dev); -+ if (ret < 0) { -+ BT_ERR("%s: Failed to load %s", hdev->name, fw_name); -+ return ret; -+ } -+ -+ ret = rtl8723b_parse_firmware(hdev, lmp_subver, fw, &fw_data); -+ if (ret < 0) -+ goto out; -+ -+ ret = rtl_download_firmware(hdev, fw_data, ret); -+ kfree(fw_data); -+ if (ret < 0) -+ goto out; -+ -+out: -+ release_firmware(fw); -+ return ret; -+} -+ -+static struct sk_buff *btrtl_read_local_version(struct hci_dev *hdev) -+{ -+ struct sk_buff *skb; -+ -+ skb = __hci_cmd_sync(hdev, HCI_OP_READ_LOCAL_VERSION, 0, NULL, -+ HCI_INIT_TIMEOUT); -+ if (IS_ERR(skb)) { -+ BT_ERR("%s: HCI_OP_READ_LOCAL_VERSION failed (%ld)", -+ hdev->name, PTR_ERR(skb)); -+ return skb; -+ } -+ -+ if (skb->len != sizeof(struct hci_rp_read_local_version)) { -+ BT_ERR("%s: HCI_OP_READ_LOCAL_VERSION event length mismatch", -+ hdev->name); -+ kfree_skb(skb); -+ return ERR_PTR(-EIO); -+ } -+ -+ return skb; -+} -+ -+int btrtl_setup_realtek(struct hci_dev *hdev) -+{ -+ struct sk_buff *skb; -+ struct hci_rp_read_local_version *resp; -+ u16 lmp_subver; -+ -+ skb = btrtl_read_local_version(hdev); -+ if (IS_ERR(skb)) -+ return -PTR_ERR(skb); -+ -+ resp = (struct hci_rp_read_local_version *)skb->data; -+ BT_INFO("%s: rtl: examining hci_ver=%02x hci_rev=%04x lmp_ver=%02x " -+ "lmp_subver=%04x", hdev->name, resp->hci_ver, resp->hci_rev, -+ resp->lmp_ver, resp->lmp_subver); -+ -+ lmp_subver = le16_to_cpu(resp->lmp_subver); -+ kfree_skb(skb); -+ -+ /* Match a set of subver values that correspond to stock firmware, -+ * which is not compatible with standard btusb. -+ * If matched, upload an alternative firmware that does conform to -+ * standard btusb. Once that firmware is uploaded, the subver changes -+ * to a different value. -+ */ -+ switch (lmp_subver) { -+ case RTL_ROM_LMP_8723A: -+ case RTL_ROM_LMP_3499: -+ return btrtl_setup_rtl8723a(hdev); -+ case RTL_ROM_LMP_8723B: -+ return btrtl_setup_rtl8723b(hdev, lmp_subver, -+ "rtl_bt/rtl8723b_fw.bin"); -+ case RTL_ROM_LMP_8821A: -+ return btrtl_setup_rtl8723b(hdev, lmp_subver, -+ "rtl_bt/rtl8821a_fw.bin"); -+ case RTL_ROM_LMP_8761A: -+ return btrtl_setup_rtl8723b(hdev, lmp_subver, -+ "rtl_bt/rtl8761a_fw.bin"); -+ default: -+ BT_INFO("rtl: assuming no firmware upload needed."); -+ return 0; -+ } -+} -+EXPORT_SYMBOL_GPL(btrtl_setup_realtek); -+ -+MODULE_AUTHOR("Daniel Drake "); -+MODULE_DESCRIPTION("Bluetooth support for Realtek devices ver " VERSION); -+MODULE_VERSION(VERSION); -+MODULE_LICENSE("GPL"); -diff -Nur linux-4.1.13.orig/drivers/bluetooth/btrtl.h linux-4.1.13/drivers/bluetooth/btrtl.h ---- linux-4.1.13.orig/drivers/bluetooth/btrtl.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/bluetooth/btrtl.h 2015-11-30 17:56:13.540140388 +0100 -@@ -0,0 +1,52 @@ -+/* -+ * Bluetooth support for Realtek devices -+ * -+ * Copyright (C) 2015 Endless Mobile, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ */ -+ -+#define RTL_FRAG_LEN 252 -+ -+struct rtl_download_cmd { -+ __u8 index; -+ __u8 data[RTL_FRAG_LEN]; -+} __packed; -+ -+struct rtl_download_response { -+ __u8 status; -+ __u8 index; -+} __packed; -+ -+struct rtl_rom_version_evt { -+ __u8 status; -+ __u8 version; -+} __packed; -+ -+struct rtl_epatch_header { -+ __u8 signature[8]; -+ __le32 fw_version; -+ __le16 num_patches; -+} __packed; -+ -+#if IS_ENABLED(CONFIG_BT_RTL) -+ -+int btrtl_setup_realtek(struct hci_dev *hdev); -+ -+#else -+ -+static inline int btrtl_setup_realtek(struct hci_dev *hdev) -+{ -+ return -EOPNOTSUPP; -+} -+ -+#endif -diff -Nur linux-4.1.13.orig/drivers/bluetooth/btusb.c linux-4.1.13/drivers/bluetooth/btusb.c ---- linux-4.1.13.orig/drivers/bluetooth/btusb.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/bluetooth/btusb.c 2015-11-30 17:56:13.540140388 +0100 -@@ -31,13 +31,14 @@ - - #include "btintel.h" - #include "btbcm.h" -+#include "btrtl.h" - - #define VERSION "0.8" - - static bool disable_scofix; - static bool force_scofix; - --static bool reset = 1; -+static bool reset = true; - - static struct usb_driver btusb_driver; - -@@ -333,6 +334,7 @@ - #define BTUSB_FIRMWARE_LOADED 7 - #define BTUSB_FIRMWARE_FAILED 8 - #define BTUSB_BOOTING 9 -+#define BTUSB_RESET_RESUME 10 - - struct btusb_data { - struct hci_dev *hdev; -@@ -1301,28 +1303,6 @@ - usb_autopm_put_interface(data->intf); - } - --static struct sk_buff *btusb_read_local_version(struct hci_dev *hdev) --{ -- struct sk_buff *skb; -- -- skb = __hci_cmd_sync(hdev, HCI_OP_READ_LOCAL_VERSION, 0, NULL, -- HCI_INIT_TIMEOUT); -- if (IS_ERR(skb)) { -- BT_ERR("%s: HCI_OP_READ_LOCAL_VERSION failed (%ld)", -- hdev->name, PTR_ERR(skb)); -- return skb; -- } -- -- if (skb->len != sizeof(struct hci_rp_read_local_version)) { -- BT_ERR("%s: HCI_OP_READ_LOCAL_VERSION event length mismatch", -- hdev->name); -- kfree_skb(skb); -- return ERR_PTR(-EIO); -- } -- -- return skb; --} -- - static int btusb_setup_bcm92035(struct hci_dev *hdev) - { - struct sk_buff *skb; -@@ -1343,408 +1323,40 @@ - { - struct hci_rp_read_local_version *rp; - struct sk_buff *skb; -- int ret; - - BT_DBG("%s", hdev->name); - -- skb = btusb_read_local_version(hdev); -- if (IS_ERR(skb)) -- return -PTR_ERR(skb); -- -- rp = (struct hci_rp_read_local_version *)skb->data; -- -- if (!rp->status) { -- if (le16_to_cpu(rp->manufacturer) != 10) { -- /* Clear the reset quirk since this is not an actual -- * early Bluetooth 1.1 device from CSR. -- */ -- clear_bit(HCI_QUIRK_RESET_ON_CLOSE, &hdev->quirks); -- -- /* These fake CSR controllers have all a broken -- * stored link key handling and so just disable it. -- */ -- set_bit(HCI_QUIRK_BROKEN_STORED_LINK_KEY, -- &hdev->quirks); -- } -- } -- -- ret = -bt_to_errno(rp->status); -- -- kfree_skb(skb); -- -- return ret; --} -- --#define RTL_FRAG_LEN 252 -- --struct rtl_download_cmd { -- __u8 index; -- __u8 data[RTL_FRAG_LEN]; --} __packed; -- --struct rtl_download_response { -- __u8 status; -- __u8 index; --} __packed; -- --struct rtl_rom_version_evt { -- __u8 status; -- __u8 version; --} __packed; -- --struct rtl_epatch_header { -- __u8 signature[8]; -- __le32 fw_version; -- __le16 num_patches; --} __packed; -- --#define RTL_EPATCH_SIGNATURE "Realtech" --#define RTL_ROM_LMP_3499 0x3499 --#define RTL_ROM_LMP_8723A 0x1200 --#define RTL_ROM_LMP_8723B 0x8723 --#define RTL_ROM_LMP_8821A 0x8821 --#define RTL_ROM_LMP_8761A 0x8761 -- --static int rtl_read_rom_version(struct hci_dev *hdev, u8 *version) --{ -- struct rtl_rom_version_evt *rom_version; -- struct sk_buff *skb; -- int ret; -- -- /* Read RTL ROM version command */ -- skb = __hci_cmd_sync(hdev, 0xfc6d, 0, NULL, HCI_INIT_TIMEOUT); -+ skb = __hci_cmd_sync(hdev, HCI_OP_READ_LOCAL_VERSION, 0, NULL, -+ HCI_INIT_TIMEOUT); - if (IS_ERR(skb)) { -- BT_ERR("%s: Read ROM version failed (%ld)", -- hdev->name, PTR_ERR(skb)); -- return PTR_ERR(skb); -+ int err = PTR_ERR(skb); -+ BT_ERR("%s: CSR: Local version failed (%d)", hdev->name, err); -+ return err; - } - -- if (skb->len != sizeof(*rom_version)) { -- BT_ERR("%s: RTL version event length mismatch", hdev->name); -+ if (skb->len != sizeof(struct hci_rp_read_local_version)) { -+ BT_ERR("%s: CSR: Local version length mismatch", hdev->name); - kfree_skb(skb); - return -EIO; - } - -- rom_version = (struct rtl_rom_version_evt *)skb->data; -- BT_INFO("%s: rom_version status=%x version=%x", -- hdev->name, rom_version->status, rom_version->version); -- -- ret = rom_version->status; -- if (ret == 0) -- *version = rom_version->version; -- -- kfree_skb(skb); -- return ret; --} -- --static int rtl8723b_parse_firmware(struct hci_dev *hdev, u16 lmp_subver, -- const struct firmware *fw, -- unsigned char **_buf) --{ -- const u8 extension_sig[] = { 0x51, 0x04, 0xfd, 0x77 }; -- struct rtl_epatch_header *epatch_info; -- unsigned char *buf; -- int i, ret, len; -- size_t min_size; -- u8 opcode, length, data, rom_version = 0; -- int project_id = -1; -- const unsigned char *fwptr, *chip_id_base; -- const unsigned char *patch_length_base, *patch_offset_base; -- u32 patch_offset = 0; -- u16 patch_length, num_patches; -- const u16 project_id_to_lmp_subver[] = { -- RTL_ROM_LMP_8723A, -- RTL_ROM_LMP_8723B, -- RTL_ROM_LMP_8821A, -- RTL_ROM_LMP_8761A -- }; -- -- ret = rtl_read_rom_version(hdev, &rom_version); -- if (ret) -- return -bt_to_errno(ret); -- -- min_size = sizeof(struct rtl_epatch_header) + sizeof(extension_sig) + 3; -- if (fw->size < min_size) -- return -EINVAL; -- -- fwptr = fw->data + fw->size - sizeof(extension_sig); -- if (memcmp(fwptr, extension_sig, sizeof(extension_sig)) != 0) { -- BT_ERR("%s: extension section signature mismatch", hdev->name); -- return -EINVAL; -- } -- -- /* Loop from the end of the firmware parsing instructions, until -- * we find an instruction that identifies the "project ID" for the -- * hardware supported by this firwmare file. -- * Once we have that, we double-check that that project_id is suitable -- * for the hardware we are working with. -- */ -- while (fwptr >= fw->data + (sizeof(struct rtl_epatch_header) + 3)) { -- opcode = *--fwptr; -- length = *--fwptr; -- data = *--fwptr; -- -- BT_DBG("check op=%x len=%x data=%x", opcode, length, data); -- -- if (opcode == 0xff) /* EOF */ -- break; -- -- if (length == 0) { -- BT_ERR("%s: found instruction with length 0", -- hdev->name); -- return -EINVAL; -- } -- -- if (opcode == 0 && length == 1) { -- project_id = data; -- break; -- } -- -- fwptr -= length; -- } -- -- if (project_id < 0) { -- BT_ERR("%s: failed to find version instruction", hdev->name); -- return -EINVAL; -- } -- -- if (project_id >= ARRAY_SIZE(project_id_to_lmp_subver)) { -- BT_ERR("%s: unknown project id %d", hdev->name, project_id); -- return -EINVAL; -- } -- -- if (lmp_subver != project_id_to_lmp_subver[project_id]) { -- BT_ERR("%s: firmware is for %x but this is a %x", hdev->name, -- project_id_to_lmp_subver[project_id], lmp_subver); -- return -EINVAL; -- } -- -- epatch_info = (struct rtl_epatch_header *)fw->data; -- if (memcmp(epatch_info->signature, RTL_EPATCH_SIGNATURE, 8) != 0) { -- BT_ERR("%s: bad EPATCH signature", hdev->name); -- return -EINVAL; -- } -- -- num_patches = le16_to_cpu(epatch_info->num_patches); -- BT_DBG("fw_version=%x, num_patches=%d", -- le32_to_cpu(epatch_info->fw_version), num_patches); -- -- /* After the rtl_epatch_header there is a funky patch metadata section. -- * Assuming 2 patches, the layout is: -- * ChipID1 ChipID2 PatchLength1 PatchLength2 PatchOffset1 PatchOffset2 -- * -- * Find the right patch for this chip. -- */ -- min_size += 8 * num_patches; -- if (fw->size < min_size) -- return -EINVAL; -- -- chip_id_base = fw->data + sizeof(struct rtl_epatch_header); -- patch_length_base = chip_id_base + (sizeof(u16) * num_patches); -- patch_offset_base = patch_length_base + (sizeof(u16) * num_patches); -- for (i = 0; i < num_patches; i++) { -- u16 chip_id = get_unaligned_le16(chip_id_base + -- (i * sizeof(u16))); -- if (chip_id == rom_version + 1) { -- patch_length = get_unaligned_le16(patch_length_base + -- (i * sizeof(u16))); -- patch_offset = get_unaligned_le32(patch_offset_base + -- (i * sizeof(u32))); -- break; -- } -- } -- -- if (!patch_offset) { -- BT_ERR("%s: didn't find patch for chip id %d", -- hdev->name, rom_version); -- return -EINVAL; -- } -- -- BT_DBG("length=%x offset=%x index %d", patch_length, patch_offset, i); -- min_size = patch_offset + patch_length; -- if (fw->size < min_size) -- return -EINVAL; -- -- /* Copy the firmware into a new buffer and write the version at -- * the end. -- */ -- len = patch_length; -- buf = kmemdup(fw->data + patch_offset, patch_length, GFP_KERNEL); -- if (!buf) -- return -ENOMEM; -- -- memcpy(buf + patch_length - 4, &epatch_info->fw_version, 4); -- -- *_buf = buf; -- return len; --} -- --static int rtl_download_firmware(struct hci_dev *hdev, -- const unsigned char *data, int fw_len) --{ -- struct rtl_download_cmd *dl_cmd; -- int frag_num = fw_len / RTL_FRAG_LEN + 1; -- int frag_len = RTL_FRAG_LEN; -- int ret = 0; -- int i; -- -- dl_cmd = kmalloc(sizeof(struct rtl_download_cmd), GFP_KERNEL); -- if (!dl_cmd) -- return -ENOMEM; -- -- for (i = 0; i < frag_num; i++) { -- struct rtl_download_response *dl_resp; -- struct sk_buff *skb; -- -- BT_DBG("download fw (%d/%d)", i, frag_num); -- -- dl_cmd->index = i; -- if (i == (frag_num - 1)) { -- dl_cmd->index |= 0x80; /* data end */ -- frag_len = fw_len % RTL_FRAG_LEN; -- } -- memcpy(dl_cmd->data, data, frag_len); -- -- /* Send download command */ -- skb = __hci_cmd_sync(hdev, 0xfc20, frag_len + 1, dl_cmd, -- HCI_INIT_TIMEOUT); -- if (IS_ERR(skb)) { -- BT_ERR("%s: download fw command failed (%ld)", -- hdev->name, PTR_ERR(skb)); -- ret = -PTR_ERR(skb); -- goto out; -- } -- -- if (skb->len != sizeof(*dl_resp)) { -- BT_ERR("%s: download fw event length mismatch", -- hdev->name); -- kfree_skb(skb); -- ret = -EIO; -- goto out; -- } -- -- dl_resp = (struct rtl_download_response *)skb->data; -- if (dl_resp->status != 0) { -- kfree_skb(skb); -- ret = bt_to_errno(dl_resp->status); -- goto out; -- } -- -- kfree_skb(skb); -- data += RTL_FRAG_LEN; -- } -- --out: -- kfree(dl_cmd); -- return ret; --} -- --static int btusb_setup_rtl8723a(struct hci_dev *hdev) --{ -- struct btusb_data *data = dev_get_drvdata(&hdev->dev); -- struct usb_device *udev = interface_to_usbdev(data->intf); -- const struct firmware *fw; -- int ret; -- -- BT_INFO("%s: rtl: loading rtl_bt/rtl8723a_fw.bin", hdev->name); -- ret = request_firmware(&fw, "rtl_bt/rtl8723a_fw.bin", &udev->dev); -- if (ret < 0) { -- BT_ERR("%s: Failed to load rtl_bt/rtl8723a_fw.bin", hdev->name); -- return ret; -- } -- -- if (fw->size < 8) { -- ret = -EINVAL; -- goto out; -- } -- -- /* Check that the firmware doesn't have the epatch signature -- * (which is only for RTL8723B and newer). -- */ -- if (!memcmp(fw->data, RTL_EPATCH_SIGNATURE, 8)) { -- BT_ERR("%s: unexpected EPATCH signature!", hdev->name); -- ret = -EINVAL; -- goto out; -- } -- -- ret = rtl_download_firmware(hdev, fw->data, fw->size); -- --out: -- release_firmware(fw); -- return ret; --} -+ rp = (struct hci_rp_read_local_version *)skb->data; - --static int btusb_setup_rtl8723b(struct hci_dev *hdev, u16 lmp_subver, -- const char *fw_name) --{ -- struct btusb_data *data = dev_get_drvdata(&hdev->dev); -- struct usb_device *udev = interface_to_usbdev(data->intf); -- unsigned char *fw_data = NULL; -- const struct firmware *fw; -- int ret; -+ if (le16_to_cpu(rp->manufacturer) != 10) { -+ /* Clear the reset quirk since this is not an actual -+ * early Bluetooth 1.1 device from CSR. -+ */ -+ clear_bit(HCI_QUIRK_RESET_ON_CLOSE, &hdev->quirks); - -- BT_INFO("%s: rtl: loading %s", hdev->name, fw_name); -- ret = request_firmware(&fw, fw_name, &udev->dev); -- if (ret < 0) { -- BT_ERR("%s: Failed to load %s", hdev->name, fw_name); -- return ret; -+ /* These fake CSR controllers have all a broken -+ * stored link key handling and so just disable it. -+ */ -+ set_bit(HCI_QUIRK_BROKEN_STORED_LINK_KEY, &hdev->quirks); - } - -- ret = rtl8723b_parse_firmware(hdev, lmp_subver, fw, &fw_data); -- if (ret < 0) -- goto out; -- -- ret = rtl_download_firmware(hdev, fw_data, ret); -- kfree(fw_data); -- if (ret < 0) -- goto out; -- --out: -- release_firmware(fw); -- return ret; --} -- --static int btusb_setup_realtek(struct hci_dev *hdev) --{ -- struct sk_buff *skb; -- struct hci_rp_read_local_version *resp; -- u16 lmp_subver; -- -- skb = btusb_read_local_version(hdev); -- if (IS_ERR(skb)) -- return -PTR_ERR(skb); -- -- resp = (struct hci_rp_read_local_version *)skb->data; -- BT_INFO("%s: rtl: examining hci_ver=%02x hci_rev=%04x lmp_ver=%02x " -- "lmp_subver=%04x", hdev->name, resp->hci_ver, resp->hci_rev, -- resp->lmp_ver, resp->lmp_subver); -- -- lmp_subver = le16_to_cpu(resp->lmp_subver); - kfree_skb(skb); - -- /* Match a set of subver values that correspond to stock firmware, -- * which is not compatible with standard btusb. -- * If matched, upload an alternative firmware that does conform to -- * standard btusb. Once that firmware is uploaded, the subver changes -- * to a different value. -- */ -- switch (lmp_subver) { -- case RTL_ROM_LMP_8723A: -- case RTL_ROM_LMP_3499: -- return btusb_setup_rtl8723a(hdev); -- case RTL_ROM_LMP_8723B: -- return btusb_setup_rtl8723b(hdev, lmp_subver, -- "rtl_bt/rtl8723b_fw.bin"); -- case RTL_ROM_LMP_8821A: -- return btusb_setup_rtl8723b(hdev, lmp_subver, -- "rtl_bt/rtl8821a_fw.bin"); -- case RTL_ROM_LMP_8761A: -- return btusb_setup_rtl8723b(hdev, lmp_subver, -- "rtl_bt/rtl8761a_fw.bin"); -- default: -- BT_INFO("rtl: assuming no firmware upload needed."); -- return 0; -- } -+ return 0; - } - - static const struct firmware *btusb_setup_intel_get_fw(struct hci_dev *hdev, -@@ -1954,12 +1566,6 @@ - } - - ver = (struct intel_version *)skb->data; -- if (ver->status) { -- BT_ERR("%s Intel fw version event failed (%02x)", hdev->name, -- ver->status); -- kfree_skb(skb); -- return -bt_to_errno(ver->status); -- } - - BT_INFO("%s: read Intel version: %02x%02x%02x%02x%02x%02x%02x%02x%02x", - hdev->name, ver->hw_platform, ver->hw_variant, -@@ -2009,15 +1615,6 @@ - return PTR_ERR(skb); - } - -- if (skb->data[0]) { -- u8 evt_status = skb->data[0]; -- -- BT_ERR("%s enable Intel manufacturer mode event failed (%02x)", -- hdev->name, evt_status); -- kfree_skb(skb); -- release_firmware(fw); -- return -bt_to_errno(evt_status); -- } - kfree_skb(skb); - - disable_patch = 1; -@@ -2364,13 +1961,6 @@ - } - - ver = (struct intel_version *)skb->data; -- if (ver->status) { -- BT_ERR("%s: Intel version command failure (%02x)", -- hdev->name, ver->status); -- err = -bt_to_errno(ver->status); -- kfree_skb(skb); -- return err; -- } - - /* The hardware platform number has a fixed value of 0x37 and - * for now only accept this single value. -@@ -2445,13 +2035,6 @@ - } - - params = (struct intel_boot_params *)skb->data; -- if (params->status) { -- BT_ERR("%s: Intel boot parameters command failure (%02x)", -- hdev->name, params->status); -- err = -bt_to_errno(params->status); -- kfree_skb(skb); -- return err; -- } - - BT_INFO("%s: Device revision is %u", hdev->name, - le16_to_cpu(params->dev_revid)); -@@ -2501,6 +2084,12 @@ - - BT_INFO("%s: Found device firmware: %s", hdev->name, fwname); - -+ /* Save the DDC file name for later use to apply once the firmware -+ * downloading is done. -+ */ -+ snprintf(fwname, sizeof(fwname), "intel/ibt-11-%u.ddc", -+ le16_to_cpu(params->dev_revid)); -+ - kfree_skb(skb); - - if (fw->size < 644) { -@@ -2662,6 +2251,43 @@ - - clear_bit(BTUSB_BOOTLOADER, &data->flags); - -+ /* Once the device is running in operational mode, it needs to apply -+ * the device configuration (DDC) parameters. -+ * -+ * The device can work without DDC parameters, so even if it fails -+ * to load the file, no need to fail the setup. -+ */ -+ err = request_firmware_direct(&fw, fwname, &hdev->dev); -+ if (err < 0) -+ return 0; -+ -+ BT_INFO("%s: Found Intel DDC parameters: %s", hdev->name, fwname); -+ -+ fw_ptr = fw->data; -+ -+ /* DDC file contains one or more DDC structure which has -+ * Length (1 byte), DDC ID (2 bytes), and DDC value (Length - 2). -+ */ -+ while (fw->size > fw_ptr - fw->data) { -+ u8 cmd_plen = fw_ptr[0] + sizeof(u8); -+ -+ skb = __hci_cmd_sync(hdev, 0xfc8b, cmd_plen, fw_ptr, -+ HCI_INIT_TIMEOUT); -+ if (IS_ERR(skb)) { -+ BT_ERR("%s: Failed to send Intel_Write_DDC (%ld)", -+ hdev->name, PTR_ERR(skb)); -+ release_firmware(fw); -+ return PTR_ERR(skb); -+ } -+ -+ fw_ptr += cmd_plen; -+ kfree_skb(skb); -+ } -+ -+ release_firmware(fw); -+ -+ BT_INFO("%s: Applying Intel DDC parameters completed", hdev->name); -+ - return 0; - } - -@@ -2693,13 +2319,6 @@ - return; - } - -- if (skb->data[0] != 0x00) { -- BT_ERR("%s: Exception info command failure (%02x)", -- hdev->name, skb->data[0]); -- kfree_skb(skb); -- return; -- } -- - BT_ERR("%s: Exception info %s", hdev->name, (char *)(skb->data + 1)); - - kfree_skb(skb); -@@ -2807,6 +2426,7 @@ - static const struct qca_device_info qca_devices_table[] = { - { 0x00000100, 20, 4, 10 }, /* Rome 1.0 */ - { 0x00000101, 20, 4, 10 }, /* Rome 1.1 */ -+ { 0x00000200, 28, 4, 18 }, /* Rome 2.0 */ - { 0x00000201, 28, 4, 18 }, /* Rome 2.1 */ - { 0x00000300, 28, 4, 18 }, /* Rome 3.0 */ - { 0x00000302, 28, 4, 18 }, /* Rome 3.2 */ -@@ -3190,8 +2810,17 @@ - hdev->set_bdaddr = btusb_set_bdaddr_ath3012; - } - -- if (id->driver_info & BTUSB_REALTEK) -- hdev->setup = btusb_setup_realtek; -+#ifdef CONFIG_BT_HCIBTUSB_RTL -+ if (id->driver_info & BTUSB_REALTEK) { -+ hdev->setup = btrtl_setup_realtek; -+ -+ /* Realtek devices lose their updated firmware over suspend, -+ * but the USB hub doesn't notice any status change. -+ * Explicitly request a device reset on resume. -+ */ -+ set_bit(BTUSB_RESET_RESUME, &data->flags); -+ } -+#endif - - if (id->driver_info & BTUSB_AMP) { - /* AMP controllers do not support SCO packets */ -@@ -3323,6 +2952,14 @@ - btusb_stop_traffic(data); - usb_kill_anchored_urbs(&data->tx_anchor); - -+ /* Optionally request a device reset on resume, but only when -+ * wakeups are disabled. If wakeups are enabled we assume the -+ * device will stay powered up throughout suspend. -+ */ -+ if (test_bit(BTUSB_RESET_RESUME, &data->flags) && -+ !device_may_wakeup(&data->udev->dev)) -+ data->udev->reset_resume = 1; -+ - return 0; - } - -diff -Nur linux-4.1.13.orig/drivers/bluetooth/btwilink.c linux-4.1.13/drivers/bluetooth/btwilink.c ---- linux-4.1.13.orig/drivers/bluetooth/btwilink.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/bluetooth/btwilink.c 2015-11-30 17:56:13.540140388 +0100 -@@ -22,7 +22,7 @@ - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ --#define DEBUG -+ - #include - #include - #include -diff -Nur linux-4.1.13.orig/drivers/bluetooth/hci_ath.c linux-4.1.13/drivers/bluetooth/hci_ath.c ---- linux-4.1.13.orig/drivers/bluetooth/hci_ath.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/bluetooth/hci_ath.c 2015-11-30 17:56:13.540140388 +0100 -@@ -192,6 +192,7 @@ - if (IS_ERR(ath->rx_skb)) { - int err = PTR_ERR(ath->rx_skb); - BT_ERR("%s: Frame reassembly failed (%d)", hu->hdev->name, err); -+ ath->rx_skb = NULL; - return err; - } - -diff -Nur linux-4.1.13.orig/drivers/bluetooth/hci_bcm.c linux-4.1.13/drivers/bluetooth/hci_bcm.c ---- linux-4.1.13.orig/drivers/bluetooth/hci_bcm.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/bluetooth/hci_bcm.c 2015-11-30 17:56:13.540140388 +0100 -@@ -24,6 +24,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -36,6 +37,55 @@ - struct sk_buff_head txq; - }; - -+static int bcm_set_baudrate(struct hci_uart *hu, unsigned int speed) -+{ -+ struct hci_dev *hdev = hu->hdev; -+ struct sk_buff *skb; -+ struct bcm_update_uart_baud_rate param; -+ -+ if (speed > 3000000) { -+ struct bcm_write_uart_clock_setting clock; -+ -+ clock.type = BCM_UART_CLOCK_48MHZ; -+ -+ BT_DBG("%s: Set Controller clock (%d)", hdev->name, clock.type); -+ -+ /* This Broadcom specific command changes the UART's controller -+ * clock for baud rate > 3000000. -+ */ -+ skb = __hci_cmd_sync(hdev, 0xfc45, 1, &clock, HCI_INIT_TIMEOUT); -+ if (IS_ERR(skb)) { -+ int err = PTR_ERR(skb); -+ BT_ERR("%s: BCM: failed to write clock command (%d)", -+ hdev->name, err); -+ return err; -+ } -+ -+ kfree_skb(skb); -+ } -+ -+ BT_DBG("%s: Set Controller UART speed to %d bit/s", hdev->name, speed); -+ -+ param.zero = cpu_to_le16(0); -+ param.baud_rate = cpu_to_le32(speed); -+ -+ /* This Broadcom specific command changes the UART's controller baud -+ * rate. -+ */ -+ skb = __hci_cmd_sync(hdev, 0xfc18, sizeof(param), ¶m, -+ HCI_INIT_TIMEOUT); -+ if (IS_ERR(skb)) { -+ int err = PTR_ERR(skb); -+ BT_ERR("%s: BCM: failed to write update baudrate command (%d)", -+ hdev->name, err); -+ return err; -+ } -+ -+ kfree_skb(skb); -+ -+ return 0; -+} -+ - static int bcm_open(struct hci_uart *hu) - { - struct bcm_data *bcm; -@@ -79,11 +129,62 @@ - - static int bcm_setup(struct hci_uart *hu) - { -+ char fw_name[64]; -+ const struct firmware *fw; -+ unsigned int speed; -+ int err; -+ - BT_DBG("hu %p", hu); - - hu->hdev->set_bdaddr = btbcm_set_bdaddr; - -- return btbcm_setup_patchram(hu->hdev); -+ err = btbcm_initialize(hu->hdev, fw_name, sizeof(fw_name)); -+ if (err) -+ return err; -+ -+ err = request_firmware(&fw, fw_name, &hu->hdev->dev); -+ if (err < 0) { -+ BT_INFO("%s: BCM: Patch %s not found", hu->hdev->name, fw_name); -+ return 0; -+ } -+ -+ err = btbcm_patchram(hu->hdev, fw); -+ if (err) { -+ BT_INFO("%s: BCM: Patch failed (%d)", hu->hdev->name, err); -+ goto finalize; -+ } -+ -+ /* Init speed if any */ -+ if (hu->init_speed) -+ speed = hu->init_speed; -+ else if (hu->proto->init_speed) -+ speed = hu->proto->init_speed; -+ else -+ speed = 0; -+ -+ if (speed) -+ hci_uart_set_baudrate(hu, speed); -+ -+ /* Operational speed if any */ -+ if (hu->oper_speed) -+ speed = hu->oper_speed; -+ else if (hu->proto->oper_speed) -+ speed = hu->proto->oper_speed; -+ else -+ speed = 0; -+ -+ if (speed) { -+ err = bcm_set_baudrate(hu, speed); -+ if (!err) -+ hci_uart_set_baudrate(hu, speed); -+ } -+ -+finalize: -+ release_firmware(fw); -+ -+ err = btbcm_finalize(hu->hdev); -+ -+ return err; - } - - static const struct h4_recv_pkt bcm_recv_pkts[] = { -@@ -104,6 +205,7 @@ - if (IS_ERR(bcm->rx_skb)) { - int err = PTR_ERR(bcm->rx_skb); - BT_ERR("%s: Frame reassembly failed (%d)", hu->hdev->name, err); -+ bcm->rx_skb = NULL; - return err; - } - -@@ -133,10 +235,13 @@ - static const struct hci_uart_proto bcm_proto = { - .id = HCI_UART_BCM, - .name = "BCM", -+ .init_speed = 115200, -+ .oper_speed = 4000000, - .open = bcm_open, - .close = bcm_close, - .flush = bcm_flush, - .setup = bcm_setup, -+ .set_baudrate = bcm_set_baudrate, - .recv = bcm_recv, - .enqueue = bcm_enqueue, - .dequeue = bcm_dequeue, -diff -Nur linux-4.1.13.orig/drivers/bluetooth/hci_bcsp.c linux-4.1.13/drivers/bluetooth/hci_bcsp.c ---- linux-4.1.13.orig/drivers/bluetooth/hci_bcsp.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/bluetooth/hci_bcsp.c 2015-11-30 17:56:13.540140388 +0100 -@@ -47,8 +47,8 @@ - - #include "hci_uart.h" - --static bool txcrc = 1; --static bool hciextn = 1; -+static bool txcrc = true; -+static bool hciextn = true; - - #define BCSP_TXWINSIZE 4 - -@@ -436,7 +436,7 @@ - break; - default: - memcpy(skb_put(bcsp->rx_skb, 1), &byte, 1); -- if ((bcsp->rx_skb-> data[0] & 0x40) != 0 && -+ if ((bcsp->rx_skb->data[0] & 0x40) != 0 && - bcsp->rx_state != BCSP_W4_CRC) - bcsp_crc_update(&bcsp->message_crc, byte); - bcsp->rx_count--; -@@ -447,24 +447,24 @@ - switch (byte) { - case 0xdc: - memcpy(skb_put(bcsp->rx_skb, 1), &c0, 1); -- if ((bcsp->rx_skb-> data[0] & 0x40) != 0 && -+ if ((bcsp->rx_skb->data[0] & 0x40) != 0 && - bcsp->rx_state != BCSP_W4_CRC) -- bcsp_crc_update(&bcsp-> message_crc, 0xc0); -+ bcsp_crc_update(&bcsp->message_crc, 0xc0); - bcsp->rx_esc_state = BCSP_ESCSTATE_NOESC; - bcsp->rx_count--; - break; - - case 0xdd: - memcpy(skb_put(bcsp->rx_skb, 1), &db, 1); -- if ((bcsp->rx_skb-> data[0] & 0x40) != 0 && -+ if ((bcsp->rx_skb->data[0] & 0x40) != 0 && - bcsp->rx_state != BCSP_W4_CRC) -- bcsp_crc_update(&bcsp-> message_crc, 0xdb); -+ bcsp_crc_update(&bcsp->message_crc, 0xdb); - bcsp->rx_esc_state = BCSP_ESCSTATE_NOESC; - bcsp->rx_count--; - break; - - default: -- BT_ERR ("Invalid byte %02x after esc byte", byte); -+ BT_ERR("Invalid byte %02x after esc byte", byte); - kfree_skb(bcsp->rx_skb); - bcsp->rx_skb = NULL; - bcsp->rx_state = BCSP_W4_PKT_DELIMITER; -@@ -527,7 +527,7 @@ - - hci_recv_frame(hu->hdev, bcsp->rx_skb); - } else { -- BT_ERR ("Packet for unknown channel (%u %s)", -+ BT_ERR("Packet for unknown channel (%u %s)", - bcsp->rx_skb->data[1] & 0x0f, - bcsp->rx_skb->data[0] & 0x80 ? - "reliable" : "unreliable"); -@@ -587,7 +587,7 @@ - } - if (bcsp->rx_skb->data[0] & 0x80 /* reliable pkt */ - && (bcsp->rx_skb->data[0] & 0x07) != bcsp->rxseq_txack) { -- BT_ERR ("Out-of-order packet arrived, got %u expected %u", -+ BT_ERR("Out-of-order packet arrived, got %u expected %u", - bcsp->rx_skb->data[0] & 0x07, bcsp->rxseq_txack); - - kfree_skb(bcsp->rx_skb); -diff -Nur linux-4.1.13.orig/drivers/bluetooth/hci_h4.c linux-4.1.13/drivers/bluetooth/hci_h4.c ---- linux-4.1.13.orig/drivers/bluetooth/hci_h4.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/bluetooth/hci_h4.c 2015-11-30 17:56:13.540140388 +0100 -@@ -133,6 +133,7 @@ - if (IS_ERR(h4->rx_skb)) { - int err = PTR_ERR(h4->rx_skb); - BT_ERR("%s: Frame reassembly failed (%d)", hu->hdev->name, err); -+ h4->rx_skb = NULL; - return err; - } - -diff -Nur linux-4.1.13.orig/drivers/bluetooth/hci_ldisc.c linux-4.1.13/drivers/bluetooth/hci_ldisc.c ---- linux-4.1.13.orig/drivers/bluetooth/hci_ldisc.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/bluetooth/hci_ldisc.c 2015-11-30 17:56:13.540140388 +0100 -@@ -40,6 +40,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -265,11 +266,133 @@ - return 0; - } - -+/* Flow control or un-flow control the device */ -+void hci_uart_set_flow_control(struct hci_uart *hu, bool enable) -+{ -+ struct tty_struct *tty = hu->tty; -+ struct ktermios ktermios; -+ int status; -+ unsigned int set = 0; -+ unsigned int clear = 0; -+ -+ if (enable) { -+ /* Disable hardware flow control */ -+ ktermios = tty->termios; -+ ktermios.c_cflag &= ~CRTSCTS; -+ status = tty_set_termios(tty, &ktermios); -+ BT_DBG("Disabling hardware flow control: %s", -+ status ? "failed" : "success"); -+ -+ /* Clear RTS to prevent the device from sending */ -+ /* Most UARTs need OUT2 to enable interrupts */ -+ status = tty->driver->ops->tiocmget(tty); -+ BT_DBG("Current tiocm 0x%x", status); -+ -+ set &= ~(TIOCM_OUT2 | TIOCM_RTS); -+ clear = ~set; -+ set &= TIOCM_DTR | TIOCM_RTS | TIOCM_OUT1 | -+ TIOCM_OUT2 | TIOCM_LOOP; -+ clear &= TIOCM_DTR | TIOCM_RTS | TIOCM_OUT1 | -+ TIOCM_OUT2 | TIOCM_LOOP; -+ status = tty->driver->ops->tiocmset(tty, set, clear); -+ BT_DBG("Clearing RTS: %s", status ? "failed" : "success"); -+ } else { -+ /* Set RTS to allow the device to send again */ -+ status = tty->driver->ops->tiocmget(tty); -+ BT_DBG("Current tiocm 0x%x", status); -+ -+ set |= (TIOCM_OUT2 | TIOCM_RTS); -+ clear = ~set; -+ set &= TIOCM_DTR | TIOCM_RTS | TIOCM_OUT1 | -+ TIOCM_OUT2 | TIOCM_LOOP; -+ clear &= TIOCM_DTR | TIOCM_RTS | TIOCM_OUT1 | -+ TIOCM_OUT2 | TIOCM_LOOP; -+ status = tty->driver->ops->tiocmset(tty, set, clear); -+ BT_DBG("Setting RTS: %s", status ? "failed" : "success"); -+ -+ /* Re-enable hardware flow control */ -+ ktermios = tty->termios; -+ ktermios.c_cflag |= CRTSCTS; -+ status = tty_set_termios(tty, &ktermios); -+ BT_DBG("Enabling hardware flow control: %s", -+ status ? "failed" : "success"); -+ } -+} -+ -+void hci_uart_set_speeds(struct hci_uart *hu, unsigned int init_speed, -+ unsigned int oper_speed) -+{ -+ hu->init_speed = init_speed; -+ hu->oper_speed = oper_speed; -+} -+ -+void hci_uart_init_tty(struct hci_uart *hu) -+{ -+ struct tty_struct *tty = hu->tty; -+ struct ktermios ktermios; -+ -+ /* Bring the UART into a known 8 bits no parity hw fc state */ -+ ktermios = tty->termios; -+ ktermios.c_iflag &= ~(IGNBRK | BRKINT | PARMRK | ISTRIP | -+ INLCR | IGNCR | ICRNL | IXON); -+ ktermios.c_oflag &= ~OPOST; -+ ktermios.c_lflag &= ~(ECHO | ECHONL | ICANON | ISIG | IEXTEN); -+ ktermios.c_cflag &= ~(CSIZE | PARENB); -+ ktermios.c_cflag |= CS8; -+ ktermios.c_cflag |= CRTSCTS; -+ -+ /* tty_set_termios() return not checked as it is always 0 */ -+ tty_set_termios(tty, &ktermios); -+} -+ -+void hci_uart_set_baudrate(struct hci_uart *hu, unsigned int speed) -+{ -+ struct tty_struct *tty = hu->tty; -+ struct ktermios ktermios; -+ -+ ktermios = tty->termios; -+ ktermios.c_cflag &= ~CBAUD; -+ tty_termios_encode_baud_rate(&ktermios, speed, speed); -+ -+ /* tty_set_termios() return not checked as it is always 0 */ -+ tty_set_termios(tty, &ktermios); -+ -+ BT_DBG("%s: New tty speeds: %d/%d", hu->hdev->name, -+ tty->termios.c_ispeed, tty->termios.c_ospeed); -+} -+ - static int hci_uart_setup(struct hci_dev *hdev) - { - struct hci_uart *hu = hci_get_drvdata(hdev); - struct hci_rp_read_local_version *ver; - struct sk_buff *skb; -+ unsigned int speed; -+ int err; -+ -+ /* Init speed if any */ -+ if (hu->init_speed) -+ speed = hu->init_speed; -+ else if (hu->proto->init_speed) -+ speed = hu->proto->init_speed; -+ else -+ speed = 0; -+ -+ if (speed) -+ hci_uart_set_baudrate(hu, speed); -+ -+ /* Operational speed if any */ -+ if (hu->oper_speed) -+ speed = hu->oper_speed; -+ else if (hu->proto->oper_speed) -+ speed = hu->proto->oper_speed; -+ else -+ speed = 0; -+ -+ if (hu->proto->set_baudrate && speed) { -+ err = hu->proto->set_baudrate(hu, speed); -+ if (!err) -+ hci_uart_set_baudrate(hu, speed); -+ } - - if (hu->proto->setup) - return hu->proto->setup(hu); -diff -Nur linux-4.1.13.orig/drivers/bluetooth/hci_uart.h linux-4.1.13/drivers/bluetooth/hci_uart.h ---- linux-4.1.13.orig/drivers/bluetooth/hci_uart.h 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/bluetooth/hci_uart.h 2015-11-30 17:56:13.540140388 +0100 -@@ -58,10 +58,13 @@ - struct hci_uart_proto { - unsigned int id; - const char *name; -+ unsigned int init_speed; -+ unsigned int oper_speed; - int (*open)(struct hci_uart *hu); - int (*close)(struct hci_uart *hu); - int (*flush)(struct hci_uart *hu); - int (*setup)(struct hci_uart *hu); -+ int (*set_baudrate)(struct hci_uart *hu, unsigned int speed); - int (*recv)(struct hci_uart *hu, const void *data, int len); - int (*enqueue)(struct hci_uart *hu, struct sk_buff *skb); - struct sk_buff *(*dequeue)(struct hci_uart *hu); -@@ -82,6 +85,9 @@ - struct sk_buff *tx_skb; - unsigned long tx_state; - spinlock_t rx_lock; -+ -+ unsigned int init_speed; -+ unsigned int oper_speed; - }; - - /* HCI_UART proto flag bits */ -@@ -96,6 +102,11 @@ - int hci_uart_unregister_proto(const struct hci_uart_proto *p); - int hci_uart_tx_wakeup(struct hci_uart *hu); - int hci_uart_init_ready(struct hci_uart *hu); -+void hci_uart_init_tty(struct hci_uart *hu); -+void hci_uart_set_baudrate(struct hci_uart *hu, unsigned int speed); -+void hci_uart_set_flow_control(struct hci_uart *hu, bool enable); -+void hci_uart_set_speeds(struct hci_uart *hu, unsigned int init_speed, -+ unsigned int oper_speed); - - #ifdef CONFIG_BT_HCIUART_H4 - int h4_init(void); -diff -Nur linux-4.1.13.orig/drivers/bluetooth/hci_vhci.c linux-4.1.13/drivers/bluetooth/hci_vhci.c ---- linux-4.1.13.orig/drivers/bluetooth/hci_vhci.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/bluetooth/hci_vhci.c 2015-11-30 17:56:13.540140388 +0100 -@@ -366,7 +366,7 @@ - .llseek = no_llseek, - }; - --static struct miscdevice vhci_miscdev= { -+static struct miscdevice vhci_miscdev = { - .name = "vhci", - .fops = &vhci_fops, - .minor = VHCI_MINOR, -diff -Nur linux-4.1.13.orig/drivers/bluetooth/Kconfig linux-4.1.13/drivers/bluetooth/Kconfig ---- linux-4.1.13.orig/drivers/bluetooth/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/bluetooth/Kconfig 2015-11-30 17:56:13.544140122 +0100 -@@ -9,6 +9,10 @@ - tristate - select FW_LOADER - -+config BT_RTL -+ tristate -+ select FW_LOADER -+ - config BT_HCIBTUSB - tristate "HCI USB driver" - depends on USB -@@ -32,6 +36,17 @@ - - Say Y here to compile support for Broadcom protocol. - -+config BT_HCIBTUSB_RTL -+ bool "Realtek protocol support" -+ depends on BT_HCIBTUSB -+ select BT_RTL -+ default y -+ help -+ The Realtek protocol support enables firmware and configuration -+ download support for Realtek Bluetooth controllers. -+ -+ Say Y here to compile support for Realtek protocol. -+ - config BT_HCIBTSDIO - tristate "HCI SDIO driver" - depends on MMC -diff -Nur linux-4.1.13.orig/drivers/bluetooth/Makefile linux-4.1.13/drivers/bluetooth/Makefile ---- linux-4.1.13.orig/drivers/bluetooth/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/bluetooth/Makefile 2015-11-30 17:56:13.544140122 +0100 -@@ -21,6 +21,7 @@ - obj-$(CONFIG_BT_MRVL_SDIO) += btmrvl_sdio.o - obj-$(CONFIG_BT_WILINK) += btwilink.o - obj-$(CONFIG_BT_BCM) += btbcm.o -+obj-$(CONFIG_BT_RTL) += btrtl.o - - btmrvl-y := btmrvl_main.o - btmrvl-$(CONFIG_DEBUG_FS) += btmrvl_debugfs.o -diff -Nur linux-4.1.13.orig/drivers/char/frandom.c linux-4.1.13/drivers/char/frandom.c ---- linux-4.1.13.orig/drivers/char/frandom.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/char/frandom.c 2015-11-30 17:56:13.544140122 +0100 -@@ -0,0 +1,415 @@ -+/* -+** frandom.c -+** Fast pseudo-random generator -+** -+** (c) Copyright 2003-2011 Eli Billauer -+** http://www.billauer.co.il -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** -+*/ -+ -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+ -+#define INTERNAL_SEED 0 -+#define EXTERNAL_SEED 1 -+ -+#define FRANDOM_MAJOR 235 -+#define FRANDOM_MINOR 11 -+#define ERANDOM_MINOR 12 -+ -+static struct file_operations frandom_fops; /* Values assigned below */ -+ -+static int erandom_seeded = 0; /* Internal flag */ -+ -+static int frandom_major = FRANDOM_MAJOR; -+static int frandom_minor = FRANDOM_MINOR; -+static int erandom_minor = ERANDOM_MINOR; -+static int frandom_bufsize = 256; -+static int frandom_chunklimit = 0; /* =0 means unlimited */ -+ -+static struct cdev frandom_cdev; -+static struct cdev erandom_cdev; -+static struct class *frandom_class; -+struct device *frandom_device; -+struct device *erandom_device; -+ -+MODULE_DESCRIPTION("Fast pseudo-random number generator"); -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Eli Billauer"); -+module_param(frandom_major, int, 0); -+module_param(frandom_minor, int, 0); -+module_param(erandom_minor, int, 0); -+module_param(frandom_bufsize, int, 0); -+module_param(frandom_chunklimit, int, 0); -+ -+MODULE_PARM_DESC(frandom_major,"Major number of /dev/frandom and /dev/erandom"); -+MODULE_PARM_DESC(frandom_minor,"Minor number of /dev/frandom"); -+MODULE_PARM_DESC(erandom_minor,"Minor number of /dev/erandom"); -+MODULE_PARM_DESC(frandom_bufsize,"Internal buffer size in bytes. Default is 256. Must be >= 256"); -+MODULE_PARM_DESC(frandom_chunklimit,"Limit for read() blocks size. 0 (default) is unlimited, otherwise must be >= 256"); -+ -+struct frandom_state -+{ -+ struct semaphore sem; /* Semaphore on the state structure */ -+ -+ u8 S[256]; /* The state array */ -+ u8 i; -+ u8 j; -+ -+ char *buf; -+}; -+ -+static struct frandom_state *erandom_state; -+ -+static inline void swap_byte(u8 *a, u8 *b) -+{ -+ u8 swapByte; -+ -+ swapByte = *a; -+ *a = *b; -+ *b = swapByte; -+} -+ -+static void init_rand_state(struct frandom_state *state, int seedflag); -+ -+void erandom_get_random_bytes(char *buf, size_t count) -+{ -+ struct frandom_state *state = erandom_state; -+ int k; -+ -+ unsigned int i; -+ unsigned int j; -+ u8 *S; -+ -+ /* If we fail to get the semaphore, we revert to external random data. -+ Since semaphore blocking is expected to be very rare, and interrupts -+ during these rare and very short periods of time even less frequent, -+ we take the better-safe-than-sorry approach, and fill the buffer -+ some expensive random data, in case the caller wasn't aware of this -+ possibility, and expects random data anyhow. -+ */ -+ -+ if (down_interruptible(&state->sem)) { -+ get_random_bytes(buf, count); -+ return; -+ } -+ -+ /* We seed erandom as late as possible, hoping that the kernel's main -+ RNG is already restored in the boot sequence (not critical, but -+ better. -+ */ -+ -+ if (!erandom_seeded) { -+ erandom_seeded = 1; -+ init_rand_state(state, EXTERNAL_SEED); -+ printk(KERN_INFO "frandom: Seeded global generator now (used by erandom)\n"); -+ } -+ -+ i = state->i; -+ j = state->j; -+ S = state->S; -+ -+ for (k=0; ki = i; -+ state->j = j; -+ -+ up(&state->sem); -+} -+ -+static void init_rand_state(struct frandom_state *state, int seedflag) -+{ -+ unsigned int i, j, k; -+ u8 *S; -+ u8 *seed = state->buf; -+ -+ if (seedflag == INTERNAL_SEED) -+ erandom_get_random_bytes(seed, 256); -+ else -+ get_random_bytes(seed, 256); -+ -+ S = state->S; -+ for (i=0; i<256; i++) -+ *S++=i; -+ -+ j=0; -+ S = state->S; -+ -+ for (i=0; i<256; i++) { -+ j = (j + S[i] + *seed++) & 0xff; -+ swap_byte(&S[i], &S[j]); -+ } -+ -+ /* It's considered good practice to discard the first 256 bytes -+ generated. So we do it: -+ */ -+ -+ i=0; j=0; -+ for (k=0; k<256; k++) { -+ i = (i + 1) & 0xff; -+ j = (j + S[i]) & 0xff; -+ swap_byte(&S[i], &S[j]); -+ } -+ -+ state->i = i; /* Save state */ -+ state->j = j; -+} -+ -+static int frandom_open(struct inode *inode, struct file *filp) -+{ -+ -+ struct frandom_state *state; -+ -+ int num = iminor(inode); -+ -+ /* This should never happen, now when the minors are regsitered -+ * explicitly -+ */ -+ if ((num != frandom_minor) && (num != erandom_minor)) return -ENODEV; -+ -+ state = kmalloc(sizeof(struct frandom_state), GFP_KERNEL); -+ if (!state) -+ return -ENOMEM; -+ -+ state->buf = kmalloc(frandom_bufsize, GFP_KERNEL); -+ if (!state->buf) { -+ kfree(state); -+ return -ENOMEM; -+ } -+ -+ sema_init(&state->sem, 1); /* Init semaphore as a mutex */ -+ -+ if (num == frandom_minor) -+ init_rand_state(state, EXTERNAL_SEED); -+ else -+ init_rand_state(state, INTERNAL_SEED); -+ -+ filp->private_data = state; -+ -+ return 0; /* Success */ -+} -+ -+static int frandom_release(struct inode *inode, struct file *filp) -+{ -+ -+ struct frandom_state *state = filp->private_data; -+ -+ kfree(state->buf); -+ kfree(state); -+ -+ return 0; -+} -+ -+static ssize_t frandom_read(struct file *filp, char *buf, size_t count, -+ loff_t *f_pos) -+{ -+ struct frandom_state *state = filp->private_data; -+ ssize_t ret; -+ int dobytes, k; -+ char *localbuf; -+ -+ unsigned int i; -+ unsigned int j; -+ u8 *S; -+ -+ if (down_interruptible(&state->sem)) -+ return -ERESTARTSYS; -+ -+ if ((frandom_chunklimit > 0) && (count > frandom_chunklimit)) -+ count = frandom_chunklimit; -+ -+ ret = count; /* It's either everything or an error... */ -+ -+ i = state->i; -+ j = state->j; -+ S = state->S; -+ -+ while (count) { -+ if (count > frandom_bufsize) -+ dobytes = frandom_bufsize; -+ else -+ dobytes = count; -+ -+ localbuf = state->buf; -+ -+ for (k=0; kbuf, dobytes)) { -+ ret = -EFAULT; -+ goto out; -+ } -+ -+ buf += dobytes; -+ count -= dobytes; -+ } -+ -+ out: -+ state->i = i; -+ state->j = j; -+ -+ up(&state->sem); -+ return ret; -+} -+ -+static struct file_operations frandom_fops = { -+ read: frandom_read, -+ open: frandom_open, -+ release: frandom_release, -+}; -+ -+static void frandom_cleanup_module(void) { -+ unregister_chrdev_region(MKDEV(frandom_major, erandom_minor), 1); -+ cdev_del(&erandom_cdev); -+ device_destroy(frandom_class, MKDEV(frandom_major, erandom_minor)); -+ -+ unregister_chrdev_region(MKDEV(frandom_major, frandom_minor), 1); -+ cdev_del(&frandom_cdev); -+ device_destroy(frandom_class, MKDEV(frandom_major, frandom_minor)); -+ class_destroy(frandom_class); -+ -+ kfree(erandom_state->buf); -+ kfree(erandom_state); -+} -+ -+ -+static int frandom_init_module(void) -+{ -+ int result; -+ -+ /* The buffer size MUST be at least 256 bytes, because we assume that -+ minimal length in init_rand_state(). -+ */ -+ if (frandom_bufsize < 256) { -+ printk(KERN_ERR "frandom: Refused to load because frandom_bufsize=%d < 256\n",frandom_bufsize); -+ return -EINVAL; -+ } -+ if ((frandom_chunklimit != 0) && (frandom_chunklimit < 256)) { -+ printk(KERN_ERR "frandom: Refused to load because frandom_chunklimit=%d < 256 and != 0\n",frandom_chunklimit); -+ return -EINVAL; -+ } -+ -+ erandom_state = kmalloc(sizeof(struct frandom_state), GFP_KERNEL); -+ if (!erandom_state) -+ return -ENOMEM; -+ -+ /* This specific buffer is only used for seeding, so we need -+ 256 bytes exactly */ -+ erandom_state->buf = kmalloc(256, GFP_KERNEL); -+ if (!erandom_state->buf) { -+ kfree(erandom_state); -+ return -ENOMEM; -+ } -+ -+ sema_init(&erandom_state->sem, 1); /* Init semaphore as a mutex */ -+ -+ erandom_seeded = 0; -+ -+ frandom_class = class_create(THIS_MODULE, "fastrng"); -+ if (IS_ERR(frandom_class)) { -+ result = PTR_ERR(frandom_class); -+ printk(KERN_WARNING "frandom: Failed to register class fastrng\n"); -+ goto error0; -+ } -+ -+ /* -+ * Register your major, and accept a dynamic number. This is the -+ * first thing to do, in order to avoid releasing other module's -+ * fops in frandom_cleanup_module() -+ */ -+ -+ cdev_init(&frandom_cdev, &frandom_fops); -+ frandom_cdev.owner = THIS_MODULE; -+ result = cdev_add(&frandom_cdev, MKDEV(frandom_major, frandom_minor), 1); -+ if (result) { -+ printk(KERN_WARNING "frandom: Failed to add cdev for /dev/frandom\n"); -+ goto error1; -+ } -+ -+ result = register_chrdev_region(MKDEV(frandom_major, frandom_minor), 1, "/dev/frandom"); -+ if (result < 0) { -+ printk(KERN_WARNING "frandom: can't get major/minor %d/%d\n", frandom_major, frandom_minor); -+ goto error2; -+ } -+ -+ frandom_device = device_create(frandom_class, NULL, MKDEV(frandom_major, frandom_minor), NULL, "frandom"); -+ -+ if (IS_ERR(frandom_device)) { -+ printk(KERN_WARNING "frandom: Failed to create frandom device\n"); -+ goto error3; -+ } -+ -+ cdev_init(&erandom_cdev, &frandom_fops); -+ erandom_cdev.owner = THIS_MODULE; -+ result = cdev_add(&erandom_cdev, MKDEV(frandom_major, erandom_minor), 1); -+ if (result) { -+ printk(KERN_WARNING "frandom: Failed to add cdev for /dev/erandom\n"); -+ goto error4; -+ } -+ -+ result = register_chrdev_region(MKDEV(frandom_major, erandom_minor), 1, "/dev/erandom"); -+ if (result < 0) { -+ printk(KERN_WARNING "frandom: can't get major/minor %d/%d\n", frandom_major, erandom_minor); -+ goto error5; -+ } -+ -+ erandom_device = device_create(frandom_class, NULL, MKDEV(frandom_major, erandom_minor), NULL, "erandom"); -+ -+ if (IS_ERR(erandom_device)) { -+ printk(KERN_WARNING "frandom: Failed to create erandom device\n"); -+ goto error6; -+ } -+ return 0; /* succeed */ -+ -+ error6: -+ unregister_chrdev_region(MKDEV(frandom_major, erandom_minor), 1); -+ error5: -+ cdev_del(&erandom_cdev); -+ error4: -+ device_destroy(frandom_class, MKDEV(frandom_major, frandom_minor)); -+ error3: -+ unregister_chrdev_region(MKDEV(frandom_major, frandom_minor), 1); -+ error2: -+ cdev_del(&frandom_cdev); -+ error1: -+ class_destroy(frandom_class); -+ error0: -+ kfree(erandom_state->buf); -+ kfree(erandom_state); -+ -+ return result; -+} -+ -+module_init(frandom_init_module); -+module_exit(frandom_cleanup_module); -+ -+EXPORT_SYMBOL(erandom_get_random_bytes); -diff -Nur linux-4.1.13.orig/drivers/char/Makefile linux-4.1.13/drivers/char/Makefile ---- linux-4.1.13.orig/drivers/char/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/char/Makefile 2015-11-30 17:56:13.544140122 +0100 -@@ -2,6 +2,7 @@ - # Makefile for the kernel character device drivers. - # - -+obj-m += frandom.o - obj-y += mem.o random.o - obj-$(CONFIG_TTY_PRINTK) += ttyprintk.o - obj-y += misc.o -diff -Nur linux-4.1.13.orig/drivers/cpufreq/imx6q-cpufreq.c linux-4.1.13/drivers/cpufreq/imx6q-cpufreq.c ---- linux-4.1.13.orig/drivers/cpufreq/imx6q-cpufreq.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/cpufreq/imx6q-cpufreq.c 2015-11-30 17:56:13.544140122 +0100 -@@ -20,6 +20,8 @@ - #define PU_SOC_VOLTAGE_HIGH 1275000 - #define FREQ_1P2_GHZ 1200000000 - -+extern int vpu352; -+ - static struct regulator *arm_reg; - static struct regulator *pu_reg; - static struct regulator *soc_reg; -@@ -44,6 +46,7 @@ - unsigned long freq_hz, volt, volt_old; - unsigned int old_freq, new_freq; - int ret; -+ int tol = 25000; /* 25mv tollerance */ - - new_freq = freq_table[index].frequency; - freq_hz = new_freq * 1000; -@@ -61,25 +64,25 @@ - rcu_read_unlock(); - volt_old = regulator_get_voltage(arm_reg); - -- dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n", -+ dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld/%d mV\n", - old_freq / 1000, volt_old / 1000, -- new_freq / 1000, volt / 1000); -+ new_freq / 1000, volt / 1000, imx6_soc_volt[index] / 1000); - - /* scaling up? scale voltage before frequency */ - if (new_freq > old_freq) { - if (!IS_ERR(pu_reg)) { -- ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0); -+ ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], tol); - if (ret) { - dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret); - return ret; - } - } -- ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0); -+ ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], tol); - if (ret) { - dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret); - return ret; - } -- ret = regulator_set_voltage_tol(arm_reg, volt, 0); -+ ret = regulator_set_voltage_tol(arm_reg, volt, tol); - if (ret) { - dev_err(cpu_dev, - "failed to scale vddarm up: %d\n", ret); -@@ -107,25 +110,25 @@ - ret = clk_set_rate(arm_clk, new_freq * 1000); - if (ret) { - dev_err(cpu_dev, "failed to set clock rate: %d\n", ret); -- regulator_set_voltage_tol(arm_reg, volt_old, 0); -+ regulator_set_voltage_tol(arm_reg, volt_old, tol); - return ret; - } - - /* scaling down? scale voltage after frequency */ - if (new_freq < old_freq) { -- ret = regulator_set_voltage_tol(arm_reg, volt, 0); -+ ret = regulator_set_voltage_tol(arm_reg, volt, tol); - if (ret) { - dev_warn(cpu_dev, - "failed to scale vddarm down: %d\n", ret); - ret = 0; - } -- ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0); -+ ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], tol); - if (ret) { - dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret); - ret = 0; - } - if (!IS_ERR(pu_reg)) { -- ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0); -+ ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], tol); - if (ret) { - dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret); - ret = 0; -@@ -251,6 +254,10 @@ - unsigned long volt = be32_to_cpup(val++); - if (freq_table[j].frequency == freq) { - imx6_soc_volt[soc_opp_count++] = volt; -+ if (vpu352 && freq == 792000) { -+ pr_info("VPU352: increase SOC/PU voltage for VPU352MHz\n"); -+ imx6_soc_volt[soc_opp_count-1] = 1250000; -+ } - break; - } - } -diff -Nur linux-4.1.13.orig/drivers/crypto/caam/caamalg.c linux-4.1.13/drivers/crypto/caam/caamalg.c ---- linux-4.1.13.orig/drivers/crypto/caam/caamalg.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/crypto/caam/caamalg.c 2015-11-30 17:56:13.544140122 +0100 -@@ -1,7 +1,7 @@ - /* - * caam - Freescale FSL CAAM support for crypto API - * -- * Copyright 2008-2011 Freescale Semiconductor, Inc. -+ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc. - * - * Based on talitos crypto API driver. - * -@@ -53,6 +53,7 @@ - #include "error.h" - #include "sg_sw_sec4.h" - #include "key_gen.h" -+#include - - /* - * crypto alg -@@ -60,68 +61,42 @@ - #define CAAM_CRA_PRIORITY 3000 - /* max key is sum of AES_MAX_KEY_SIZE, max split key size */ - #define CAAM_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + \ -- CTR_RFC3686_NONCE_SIZE + \ - SHA512_DIGEST_SIZE * 2) - /* max IV is max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */ - #define CAAM_MAX_IV_LENGTH 16 - - /* length of descriptors text */ -+#define DESC_JOB_IO_LEN (CAAM_CMD_SZ * 5 + CAAM_PTR_SZ * 3) -+ - #define DESC_AEAD_BASE (4 * CAAM_CMD_SZ) --#define DESC_AEAD_ENC_LEN (DESC_AEAD_BASE + 15 * CAAM_CMD_SZ) --#define DESC_AEAD_DEC_LEN (DESC_AEAD_BASE + 18 * CAAM_CMD_SZ) -+#define DESC_AEAD_ENC_LEN (DESC_AEAD_BASE + 16 * CAAM_CMD_SZ) -+#define DESC_AEAD_DEC_LEN (DESC_AEAD_BASE + 21 * CAAM_CMD_SZ) - #define DESC_AEAD_GIVENC_LEN (DESC_AEAD_ENC_LEN + 7 * CAAM_CMD_SZ) - --/* Note: Nonce is counted in enckeylen */ --#define DESC_AEAD_CTR_RFC3686_LEN (6 * CAAM_CMD_SZ) -- --#define DESC_AEAD_NULL_BASE (3 * CAAM_CMD_SZ) --#define DESC_AEAD_NULL_ENC_LEN (DESC_AEAD_NULL_BASE + 14 * CAAM_CMD_SZ) --#define DESC_AEAD_NULL_DEC_LEN (DESC_AEAD_NULL_BASE + 17 * CAAM_CMD_SZ) -- --#define DESC_GCM_BASE (3 * CAAM_CMD_SZ) --#define DESC_GCM_ENC_LEN (DESC_GCM_BASE + 23 * CAAM_CMD_SZ) --#define DESC_GCM_DEC_LEN (DESC_GCM_BASE + 19 * CAAM_CMD_SZ) -- --#define DESC_RFC4106_BASE (3 * CAAM_CMD_SZ) --#define DESC_RFC4106_ENC_LEN (DESC_RFC4106_BASE + 15 * CAAM_CMD_SZ) --#define DESC_RFC4106_DEC_LEN (DESC_RFC4106_BASE + 14 * CAAM_CMD_SZ) --#define DESC_RFC4106_GIVENC_LEN (DESC_RFC4106_BASE + 21 * CAAM_CMD_SZ) -- --#define DESC_RFC4543_BASE (3 * CAAM_CMD_SZ) --#define DESC_RFC4543_ENC_LEN (DESC_RFC4543_BASE + 25 * CAAM_CMD_SZ) --#define DESC_RFC4543_DEC_LEN (DESC_RFC4543_BASE + 27 * CAAM_CMD_SZ) --#define DESC_RFC4543_GIVENC_LEN (DESC_RFC4543_BASE + 30 * CAAM_CMD_SZ) -- - #define DESC_ABLKCIPHER_BASE (3 * CAAM_CMD_SZ) - #define DESC_ABLKCIPHER_ENC_LEN (DESC_ABLKCIPHER_BASE + \ - 20 * CAAM_CMD_SZ) - #define DESC_ABLKCIPHER_DEC_LEN (DESC_ABLKCIPHER_BASE + \ - 15 * CAAM_CMD_SZ) - --#define DESC_MAX_USED_BYTES (DESC_RFC4543_GIVENC_LEN + \ -+#define DESC_MAX_USED_BYTES (DESC_AEAD_GIVENC_LEN + \ - CAAM_MAX_KEY_SIZE) - #define DESC_MAX_USED_LEN (DESC_MAX_USED_BYTES / CAAM_CMD_SZ) - - #ifdef DEBUG - /* for print_hex_dumps with line references */ -+#define xstr(s) str(s) -+#define str(s) #s - #define debug(format, arg...) printk(format, arg) - #else - #define debug(format, arg...) - #endif --static struct list_head alg_list; - - /* Set DK bit in class 1 operation if shared */ - static inline void append_dec_op1(u32 *desc, u32 type) - { - u32 *jump_cmd, *uncond_jump_cmd; - -- /* DK bit is valid only for AES */ -- if ((type & OP_ALG_ALGSEL_MASK) != OP_ALG_ALGSEL_AES) { -- append_operation(desc, type | OP_ALG_AS_INITFINAL | -- OP_ALG_DECRYPT); -- return; -- } -- - jump_cmd = append_jump(desc, JUMP_TEST_ALL | JUMP_COND_SHRD); - append_operation(desc, type | OP_ALG_AS_INITFINAL | - OP_ALG_DECRYPT); -@@ -133,26 +108,37 @@ - } - - /* -+ * Wait for completion of class 1 key loading before allowing -+ * error propagation -+ */ -+static inline void append_dec_shr_done(u32 *desc) -+{ -+ u32 *jump_cmd; -+ -+ jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TEST_ALL); -+ set_jump_tgt_here(desc, jump_cmd); -+ append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD); -+} -+ -+/* - * For aead functions, read payload and write payload, - * both of which are specified in req->src and req->dst - */ - static inline void aead_append_src_dst(u32 *desc, u32 msg_type) - { -- append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | KEY_VLF); - append_seq_fifo_load(desc, 0, FIFOLD_CLASS_BOTH | - KEY_VLF | msg_type | FIFOLD_TYPE_LASTBOTH); -+ append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | KEY_VLF); - } - - /* - * For aead encrypt and decrypt, read iv for both classes - */ --static inline void aead_append_ld_iv(u32 *desc, int ivsize, int ivoffset) -+static inline void aead_append_ld_iv(u32 *desc, int ivsize) - { -- append_seq_load(desc, ivsize, LDST_CLASS_1_CCB | -- LDST_SRCDST_BYTE_CONTEXT | -- (ivoffset << LDST_OFFSET_SHIFT)); -- append_move(desc, MOVE_SRC_CLASS1CTX | MOVE_DEST_CLASS2INFIFO | -- (ivoffset << MOVE_OFFSET_SHIFT) | ivsize); -+ append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT | -+ LDST_CLASS_1_CCB | ivsize); -+ append_move(desc, MOVE_SRC_CLASS1CTX | MOVE_DEST_CLASS2INFIFO | ivsize); - } - - /* -@@ -198,309 +184,68 @@ - }; - - static void append_key_aead(u32 *desc, struct caam_ctx *ctx, -- int keys_fit_inline, bool is_rfc3686) -+ int keys_fit_inline) - { -- u32 *nonce; -- unsigned int enckeylen = ctx->enckeylen; -- -- /* -- * RFC3686 specific: -- * | ctx->key = {AUTH_KEY, ENC_KEY, NONCE} -- * | enckeylen = encryption key size + nonce size -- */ -- if (is_rfc3686) -- enckeylen -= CTR_RFC3686_NONCE_SIZE; -- - if (keys_fit_inline) { - append_key_as_imm(desc, ctx->key, ctx->split_key_pad_len, - ctx->split_key_len, CLASS_2 | - KEY_DEST_MDHA_SPLIT | KEY_ENC); - append_key_as_imm(desc, (void *)ctx->key + -- ctx->split_key_pad_len, enckeylen, -- enckeylen, CLASS_1 | KEY_DEST_CLASS_REG); -+ ctx->split_key_pad_len, ctx->enckeylen, -+ ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG); - } else { - append_key(desc, ctx->key_dma, ctx->split_key_len, CLASS_2 | - KEY_DEST_MDHA_SPLIT | KEY_ENC); - append_key(desc, ctx->key_dma + ctx->split_key_pad_len, -- enckeylen, CLASS_1 | KEY_DEST_CLASS_REG); -- } -- -- /* Load Counter into CONTEXT1 reg */ -- if (is_rfc3686) { -- nonce = (u32 *)((void *)ctx->key + ctx->split_key_pad_len + -- enckeylen); -- append_load_imm_u32(desc, *nonce, LDST_CLASS_IND_CCB | -- LDST_SRCDST_BYTE_OUTFIFO | LDST_IMM); -- append_move(desc, -- MOVE_SRC_OUTFIFO | -- MOVE_DEST_CLASS1CTX | -- (16 << MOVE_OFFSET_SHIFT) | -- (CTR_RFC3686_NONCE_SIZE << MOVE_LEN_SHIFT)); -+ ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG); - } - } - - static void init_sh_desc_key_aead(u32 *desc, struct caam_ctx *ctx, -- int keys_fit_inline, bool is_rfc3686) -+ int keys_fit_inline) - { - u32 *key_jump_cmd; - -- /* Note: Context registers are saved. */ -- init_sh_desc(desc, HDR_SHARE_SERIAL | HDR_SAVECTX); -- -- /* Skip if already shared */ -- key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | -- JUMP_COND_SHRD); -- -- append_key_aead(desc, ctx, keys_fit_inline, is_rfc3686); -- -- set_jump_tgt_here(desc, key_jump_cmd); --} -- --static int aead_null_set_sh_desc(struct crypto_aead *aead) --{ -- struct aead_tfm *tfm = &aead->base.crt_aead; -- struct caam_ctx *ctx = crypto_aead_ctx(aead); -- struct device *jrdev = ctx->jrdev; -- bool keys_fit_inline = false; -- u32 *key_jump_cmd, *jump_cmd, *read_move_cmd, *write_move_cmd; -- u32 *desc; -- -- /* -- * Job Descriptor and Shared Descriptors -- * must all fit into the 64-word Descriptor h/w Buffer -- */ -- if (DESC_AEAD_NULL_ENC_LEN + DESC_JOB_IO_LEN + -- ctx->split_key_pad_len <= CAAM_DESC_BYTES_MAX) -- keys_fit_inline = true; -- -- /* aead_encrypt shared descriptor */ -- desc = ctx->sh_desc_enc; -- - init_sh_desc(desc, HDR_SHARE_SERIAL); - - /* Skip if already shared */ - key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | - JUMP_COND_SHRD); -- if (keys_fit_inline) -- append_key_as_imm(desc, ctx->key, ctx->split_key_pad_len, -- ctx->split_key_len, CLASS_2 | -- KEY_DEST_MDHA_SPLIT | KEY_ENC); -- else -- append_key(desc, ctx->key_dma, ctx->split_key_len, CLASS_2 | -- KEY_DEST_MDHA_SPLIT | KEY_ENC); -- set_jump_tgt_here(desc, key_jump_cmd); -- -- /* cryptlen = seqoutlen - authsize */ -- append_math_sub_imm_u32(desc, REG3, SEQOUTLEN, IMM, ctx->authsize); -- -- /* -- * NULL encryption; IV is zero -- * assoclen = (assoclen + cryptlen) - cryptlen -- */ -- append_math_sub(desc, VARSEQINLEN, SEQINLEN, REG3, CAAM_CMD_SZ); -- -- /* read assoc before reading payload */ -- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG | -- KEY_VLF); -- -- /* Prepare to read and write cryptlen bytes */ -- append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ); -- append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ); -- -- /* -- * MOVE_LEN opcode is not available in all SEC HW revisions, -- * thus need to do some magic, i.e. self-patch the descriptor -- * buffer. -- */ -- read_move_cmd = append_move(desc, MOVE_SRC_DESCBUF | -- MOVE_DEST_MATH3 | -- (0x6 << MOVE_LEN_SHIFT)); -- write_move_cmd = append_move(desc, MOVE_SRC_MATH3 | -- MOVE_DEST_DESCBUF | -- MOVE_WAITCOMP | -- (0x8 << MOVE_LEN_SHIFT)); -- -- /* Class 2 operation */ -- append_operation(desc, ctx->class2_alg_type | -- OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT); -- -- /* Read and write cryptlen bytes */ -- aead_append_src_dst(desc, FIFOLD_TYPE_MSG | FIFOLD_TYPE_FLUSH1); -- -- set_move_tgt_here(desc, read_move_cmd); -- set_move_tgt_here(desc, write_move_cmd); -- append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO); -- append_move(desc, MOVE_SRC_INFIFO_CL | MOVE_DEST_OUTFIFO | -- MOVE_AUX_LS); -- -- /* Write ICV */ -- append_seq_store(desc, ctx->authsize, LDST_CLASS_2_CCB | -- LDST_SRCDST_BYTE_CONTEXT); -- -- ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc, -- desc_bytes(desc), -- DMA_TO_DEVICE); -- if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) { -- dev_err(jrdev, "unable to map shared descriptor\n"); -- return -ENOMEM; -- } --#ifdef DEBUG -- print_hex_dump(KERN_ERR, -- "aead null enc shdesc@"__stringify(__LINE__)": ", -- DUMP_PREFIX_ADDRESS, 16, 4, desc, -- desc_bytes(desc), 1); --#endif -- -- /* -- * Job Descriptor and Shared Descriptors -- * must all fit into the 64-word Descriptor h/w Buffer -- */ -- keys_fit_inline = false; -- if (DESC_AEAD_NULL_DEC_LEN + DESC_JOB_IO_LEN + -- ctx->split_key_pad_len <= CAAM_DESC_BYTES_MAX) -- keys_fit_inline = true; -- -- desc = ctx->sh_desc_dec; - -- /* aead_decrypt shared descriptor */ -- init_sh_desc(desc, HDR_SHARE_SERIAL); -+ append_key_aead(desc, ctx, keys_fit_inline); - -- /* Skip if already shared */ -- key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | -- JUMP_COND_SHRD); -- if (keys_fit_inline) -- append_key_as_imm(desc, ctx->key, ctx->split_key_pad_len, -- ctx->split_key_len, CLASS_2 | -- KEY_DEST_MDHA_SPLIT | KEY_ENC); -- else -- append_key(desc, ctx->key_dma, ctx->split_key_len, CLASS_2 | -- KEY_DEST_MDHA_SPLIT | KEY_ENC); - set_jump_tgt_here(desc, key_jump_cmd); - -- /* Class 2 operation */ -- append_operation(desc, ctx->class2_alg_type | -- OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT | OP_ALG_ICV_ON); -- -- /* assoclen + cryptlen = seqinlen - ivsize - authsize */ -- append_math_sub_imm_u32(desc, REG3, SEQINLEN, IMM, -- ctx->authsize + tfm->ivsize); -- /* assoclen = (assoclen + cryptlen) - cryptlen */ -- append_math_sub(desc, REG2, SEQOUTLEN, REG0, CAAM_CMD_SZ); -- append_math_sub(desc, VARSEQINLEN, REG3, REG2, CAAM_CMD_SZ); -- -- /* read assoc before reading payload */ -- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG | -- KEY_VLF); -- -- /* Prepare to read and write cryptlen bytes */ -- append_math_add(desc, VARSEQINLEN, ZERO, REG2, CAAM_CMD_SZ); -- append_math_add(desc, VARSEQOUTLEN, ZERO, REG2, CAAM_CMD_SZ); -- -- /* -- * MOVE_LEN opcode is not available in all SEC HW revisions, -- * thus need to do some magic, i.e. self-patch the descriptor -- * buffer. -- */ -- read_move_cmd = append_move(desc, MOVE_SRC_DESCBUF | -- MOVE_DEST_MATH2 | -- (0x6 << MOVE_LEN_SHIFT)); -- write_move_cmd = append_move(desc, MOVE_SRC_MATH2 | -- MOVE_DEST_DESCBUF | -- MOVE_WAITCOMP | -- (0x8 << MOVE_LEN_SHIFT)); -- -- /* Read and write cryptlen bytes */ -- aead_append_src_dst(desc, FIFOLD_TYPE_MSG | FIFOLD_TYPE_FLUSH1); -- -- /* -- * Insert a NOP here, since we need at least 4 instructions between -- * code patching the descriptor buffer and the location being patched. -- */ -- jump_cmd = append_jump(desc, JUMP_TEST_ALL); -- set_jump_tgt_here(desc, jump_cmd); -- -- set_move_tgt_here(desc, read_move_cmd); -- set_move_tgt_here(desc, write_move_cmd); -- append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO); -- append_move(desc, MOVE_SRC_INFIFO_CL | MOVE_DEST_OUTFIFO | -- MOVE_AUX_LS); -- append_cmd(desc, CMD_LOAD | ENABLE_AUTO_INFO_FIFO); -- -- /* Load ICV */ -- append_seq_fifo_load(desc, ctx->authsize, FIFOLD_CLASS_CLASS2 | -- FIFOLD_TYPE_LAST2 | FIFOLD_TYPE_ICV); -- -- ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc, -- desc_bytes(desc), -- DMA_TO_DEVICE); -- if (dma_mapping_error(jrdev, ctx->sh_desc_dec_dma)) { -- dev_err(jrdev, "unable to map shared descriptor\n"); -- return -ENOMEM; -- } --#ifdef DEBUG -- print_hex_dump(KERN_ERR, -- "aead null dec shdesc@"__stringify(__LINE__)": ", -- DUMP_PREFIX_ADDRESS, 16, 4, desc, -- desc_bytes(desc), 1); --#endif -- -- return 0; -+ /* Propagate errors from shared to job descriptor */ -+ append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD); - } - - static int aead_set_sh_desc(struct crypto_aead *aead) - { - struct aead_tfm *tfm = &aead->base.crt_aead; - struct caam_ctx *ctx = crypto_aead_ctx(aead); -- struct crypto_tfm *ctfm = crypto_aead_tfm(aead); -- const char *alg_name = crypto_tfm_alg_name(ctfm); - struct device *jrdev = ctx->jrdev; -- bool keys_fit_inline; -+ bool keys_fit_inline = false; -+ u32 *key_jump_cmd, *jump_cmd; - u32 geniv, moveiv; -- u32 ctx1_iv_off = 0; - u32 *desc; -- const bool ctr_mode = ((ctx->class1_alg_type & OP_ALG_AAI_MASK) == -- OP_ALG_AAI_CTR_MOD128); -- const bool is_rfc3686 = (ctr_mode && -- (strstr(alg_name, "rfc3686") != NULL)); - -- if (!ctx->authsize) -+ if (!ctx->enckeylen || !ctx->authsize) - return 0; - -- /* NULL encryption / decryption */ -- if (!ctx->enckeylen) -- return aead_null_set_sh_desc(aead); -- -- /* -- * AES-CTR needs to load IV in CONTEXT1 reg -- * at an offset of 128bits (16bytes) -- * CONTEXT1[255:128] = IV -- */ -- if (ctr_mode) -- ctx1_iv_off = 16; -- -- /* -- * RFC3686 specific: -- * CONTEXT1[255:128] = {NONCE, IV, COUNTER} -- */ -- if (is_rfc3686) -- ctx1_iv_off = 16 + CTR_RFC3686_NONCE_SIZE; -- - /* - * Job Descriptor and Shared Descriptors - * must all fit into the 64-word Descriptor h/w Buffer - */ -- keys_fit_inline = false; - if (DESC_AEAD_ENC_LEN + DESC_JOB_IO_LEN + -- ctx->split_key_pad_len + ctx->enckeylen + -- (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0) <= -+ ctx->split_key_pad_len + ctx->enckeylen <= - CAAM_DESC_BYTES_MAX) - keys_fit_inline = true; - - /* aead_encrypt shared descriptor */ - desc = ctx->sh_desc_enc; - -- /* Note: Context registers are saved. */ -- init_sh_desc_key_aead(desc, ctx, keys_fit_inline, is_rfc3686); -+ init_sh_desc_key_aead(desc, ctx, keys_fit_inline); - - /* Class 2 operation */ - append_operation(desc, ctx->class2_alg_type | -@@ -512,21 +257,13 @@ - /* assoclen + cryptlen = seqinlen - ivsize */ - append_math_sub_imm_u32(desc, REG2, SEQINLEN, IMM, tfm->ivsize); - -- /* assoclen = (assoclen + cryptlen) - cryptlen */ -+ /* assoclen + cryptlen = (assoclen + cryptlen) - cryptlen */ - append_math_sub(desc, VARSEQINLEN, REG2, REG3, CAAM_CMD_SZ); - - /* read assoc before reading payload */ - append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG | - KEY_VLF); -- aead_append_ld_iv(desc, tfm->ivsize, ctx1_iv_off); -- -- /* Load Counter into CONTEXT1 reg */ -- if (is_rfc3686) -- append_load_imm_u32(desc, be32_to_cpu(1), LDST_IMM | -- LDST_CLASS_1_CCB | -- LDST_SRCDST_BYTE_CONTEXT | -- ((ctx1_iv_off + CTR_RFC3686_IV_SIZE) << -- LDST_OFFSET_SHIFT)); -+ aead_append_ld_iv(desc, tfm->ivsize); - - /* Class 1 operation */ - append_operation(desc, ctx->class1_alg_type | -@@ -549,35 +286,46 @@ - return -ENOMEM; - } - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "aead enc shdesc@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "aead enc shdesc@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, desc, - desc_bytes(desc), 1); - #endif - -+ dma_sync_single_for_cpu(jrdev, ctx->sh_desc_enc_dma, desc_bytes(desc), -+ DMA_TO_DEVICE); - /* - * Job Descriptor and Shared Descriptors - * must all fit into the 64-word Descriptor h/w Buffer - */ -- keys_fit_inline = false; - if (DESC_AEAD_DEC_LEN + DESC_JOB_IO_LEN + -- ctx->split_key_pad_len + ctx->enckeylen + -- (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0) <= -+ ctx->split_key_pad_len + ctx->enckeylen <= - CAAM_DESC_BYTES_MAX) - keys_fit_inline = true; - -- /* aead_decrypt shared descriptor */ - desc = ctx->sh_desc_dec; - -- /* Note: Context registers are saved. */ -- init_sh_desc_key_aead(desc, ctx, keys_fit_inline, is_rfc3686); -+ /* aead_decrypt shared descriptor */ -+ init_sh_desc(desc, HDR_SHARE_SERIAL); -+ -+ /* Skip if already shared */ -+ key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | -+ JUMP_COND_SHRD); -+ -+ append_key_aead(desc, ctx, keys_fit_inline); -+ -+ /* Only propagate error immediately if shared */ -+ jump_cmd = append_jump(desc, JUMP_TEST_ALL); -+ set_jump_tgt_here(desc, key_jump_cmd); -+ append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD); -+ set_jump_tgt_here(desc, jump_cmd); - - /* Class 2 operation */ - append_operation(desc, ctx->class2_alg_type | - OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT | OP_ALG_ICV_ON); - -- /* assoclen + cryptlen = seqinlen - ivsize - authsize */ -+ /* assoclen + cryptlen = seqinlen - ivsize */ - append_math_sub_imm_u32(desc, REG3, SEQINLEN, IMM, -- ctx->authsize + tfm->ivsize); -+ ctx->authsize + tfm->ivsize) - /* assoclen = (assoclen + cryptlen) - cryptlen */ - append_math_sub(desc, REG2, SEQOUTLEN, REG0, CAAM_CMD_SZ); - append_math_sub(desc, VARSEQINLEN, REG3, REG2, CAAM_CMD_SZ); -@@ -586,22 +334,9 @@ - append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG | - KEY_VLF); - -- aead_append_ld_iv(desc, tfm->ivsize, ctx1_iv_off); -+ aead_append_ld_iv(desc, tfm->ivsize); - -- /* Load Counter into CONTEXT1 reg */ -- if (is_rfc3686) -- append_load_imm_u32(desc, be32_to_cpu(1), LDST_IMM | -- LDST_CLASS_1_CCB | -- LDST_SRCDST_BYTE_CONTEXT | -- ((ctx1_iv_off + CTR_RFC3686_IV_SIZE) << -- LDST_OFFSET_SHIFT)); -- -- /* Choose operation */ -- if (ctr_mode) -- append_operation(desc, ctx->class1_alg_type | -- OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT); -- else -- append_dec_op1(desc, ctx->class1_alg_type); -+ append_dec_op1(desc, ctx->class1_alg_type); - - /* Read and write cryptlen bytes */ - append_math_add(desc, VARSEQINLEN, ZERO, REG2, CAAM_CMD_SZ); -@@ -611,6 +346,7 @@ - /* Load ICV */ - append_seq_fifo_load(desc, ctx->authsize, FIFOLD_CLASS_CLASS2 | - FIFOLD_TYPE_LAST2 | FIFOLD_TYPE_ICV); -+ append_dec_shr_done(desc); - - ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc, - desc_bytes(desc), -@@ -620,27 +356,26 @@ - return -ENOMEM; - } - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "aead dec shdesc@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "aead dec shdesc@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, desc, - desc_bytes(desc), 1); - #endif -+ dma_sync_single_for_cpu(jrdev, ctx->sh_desc_dec_dma, desc_bytes(desc), -+ DMA_TO_DEVICE); - - /* - * Job Descriptor and Shared Descriptors - * must all fit into the 64-word Descriptor h/w Buffer - */ -- keys_fit_inline = false; - if (DESC_AEAD_GIVENC_LEN + DESC_JOB_IO_LEN + -- ctx->split_key_pad_len + ctx->enckeylen + -- (is_rfc3686 ? DESC_AEAD_CTR_RFC3686_LEN : 0) <= -+ ctx->split_key_pad_len + ctx->enckeylen <= - CAAM_DESC_BYTES_MAX) - keys_fit_inline = true; - - /* aead_givencrypt shared descriptor */ - desc = ctx->sh_desc_givenc; - -- /* Note: Context registers are saved. */ -- init_sh_desc_key_aead(desc, ctx, keys_fit_inline, is_rfc3686); -+ init_sh_desc_key_aead(desc, ctx, keys_fit_inline); - - /* Generate IV */ - geniv = NFIFOENTRY_STYPE_PAD | NFIFOENTRY_DEST_DECO | -@@ -649,16 +384,13 @@ - append_load_imm_u32(desc, geniv, LDST_CLASS_IND_CCB | - LDST_SRCDST_WORD_INFO_FIFO | LDST_IMM); - append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO); -- append_move(desc, MOVE_WAITCOMP | -- MOVE_SRC_INFIFO | MOVE_DEST_CLASS1CTX | -- (ctx1_iv_off << MOVE_OFFSET_SHIFT) | -- (tfm->ivsize << MOVE_LEN_SHIFT)); -+ append_move(desc, MOVE_SRC_INFIFO | -+ MOVE_DEST_CLASS1CTX | (tfm->ivsize << MOVE_LEN_SHIFT)); - append_cmd(desc, CMD_LOAD | ENABLE_AUTO_INFO_FIFO); - - /* Copy IV to class 1 context */ -- append_move(desc, MOVE_SRC_CLASS1CTX | MOVE_DEST_OUTFIFO | -- (ctx1_iv_off << MOVE_OFFSET_SHIFT) | -- (tfm->ivsize << MOVE_LEN_SHIFT)); -+ append_move(desc, MOVE_SRC_CLASS1CTX | -+ MOVE_DEST_OUTFIFO | (tfm->ivsize << MOVE_LEN_SHIFT)); - - /* Return to encryption */ - append_operation(desc, ctx->class2_alg_type | -@@ -674,7 +406,7 @@ - append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG | - KEY_VLF); - -- /* Copy iv from outfifo to class 2 fifo */ -+ /* Copy iv from class 1 ctx to class 2 fifo*/ - moveiv = NFIFOENTRY_STYPE_OFIFO | NFIFOENTRY_DEST_CLASS2 | - NFIFOENTRY_DTYPE_MSG | (tfm->ivsize << NFIFOENTRY_DLEN_SHIFT); - append_load_imm_u32(desc, moveiv, LDST_CLASS_IND_CCB | -@@ -682,14 +414,6 @@ - append_load_imm_u32(desc, tfm->ivsize, LDST_CLASS_2_CCB | - LDST_SRCDST_WORD_DATASZ_REG | LDST_IMM); - -- /* Load Counter into CONTEXT1 reg */ -- if (is_rfc3686) -- append_load_imm_u32(desc, be32_to_cpu(1), LDST_IMM | -- LDST_CLASS_1_CCB | -- LDST_SRCDST_BYTE_CONTEXT | -- ((ctx1_iv_off + CTR_RFC3686_IV_SIZE) << -- LDST_OFFSET_SHIFT)); -- - /* Class 1 operation */ - append_operation(desc, ctx->class1_alg_type | - OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT); -@@ -717,10 +441,12 @@ - return -ENOMEM; - } - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "aead givenc shdesc@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "aead givenc shdesc@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, desc, - desc_bytes(desc), 1); - #endif -+ dma_sync_single_for_cpu(jrdev, ctx->sh_desc_givenc_dma, -+ desc_bytes(desc), DMA_TO_DEVICE); - - return 0; - } -@@ -736,977 +462,84 @@ - return 0; - } - --static int gcm_set_sh_desc(struct crypto_aead *aead) -+static u32 gen_split_aead_key(struct caam_ctx *ctx, const u8 *key_in, -+ u32 authkeylen) - { -- struct aead_tfm *tfm = &aead->base.crt_aead; -+ return gen_split_key(ctx->jrdev, ctx->key, ctx->split_key_len, -+ ctx->split_key_pad_len, key_in, authkeylen, -+ ctx->alg_op); -+} -+ -+static int aead_setkey(struct crypto_aead *aead, -+ const u8 *key, unsigned int keylen) -+{ -+ /* Sizes for MDHA pads (*not* keys): MD5, SHA1, 224, 256, 384, 512 */ -+ static const u8 mdpadlen[] = { 16, 20, 32, 32, 64, 64 }; - struct caam_ctx *ctx = crypto_aead_ctx(aead); - struct device *jrdev = ctx->jrdev; -- bool keys_fit_inline = false; -- u32 *key_jump_cmd, *zero_payload_jump_cmd, -- *zero_assoc_jump_cmd1, *zero_assoc_jump_cmd2; -- u32 *desc; -- -- if (!ctx->enckeylen || !ctx->authsize) -- return 0; -- -- /* -- * AES GCM encrypt shared descriptor -- * Job Descriptor and Shared Descriptor -- * must fit into the 64-word Descriptor h/w Buffer -- */ -- if (DESC_GCM_ENC_LEN + DESC_JOB_IO_LEN + -- ctx->enckeylen <= CAAM_DESC_BYTES_MAX) -- keys_fit_inline = true; -+ struct rtattr *rta = (void *)key; -+ struct crypto_authenc_key_param *param; -+ unsigned int authkeylen; -+ unsigned int enckeylen; -+ int ret = 0; - -- desc = ctx->sh_desc_enc; -+ param = RTA_DATA(rta); -+ enckeylen = be32_to_cpu(param->enckeylen); - -- init_sh_desc(desc, HDR_SHARE_SERIAL); -+ key += RTA_ALIGN(rta->rta_len); -+ keylen -= RTA_ALIGN(rta->rta_len); - -- /* skip key loading if they are loaded due to sharing */ -- key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | -- JUMP_COND_SHRD | JUMP_COND_SELF); -- if (keys_fit_inline) -- append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen, -- ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG); -- else -- append_key(desc, ctx->key_dma, ctx->enckeylen, -- CLASS_1 | KEY_DEST_CLASS_REG); -- set_jump_tgt_here(desc, key_jump_cmd); -+ if (keylen < enckeylen) -+ goto badkey; - -- /* class 1 operation */ -- append_operation(desc, ctx->class1_alg_type | -- OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT); -+ authkeylen = keylen - enckeylen; - -- /* cryptlen = seqoutlen - authsize */ -- append_math_sub_imm_u32(desc, REG3, SEQOUTLEN, IMM, ctx->authsize); -+ if (keylen > CAAM_MAX_KEY_SIZE) -+ goto badkey; - -- /* assoclen + cryptlen = seqinlen - ivsize */ -- append_math_sub_imm_u32(desc, REG2, SEQINLEN, IMM, tfm->ivsize); -+ /* Pick class 2 key length from algorithm submask */ -+ ctx->split_key_len = mdpadlen[(ctx->alg_op & OP_ALG_ALGSEL_SUBMASK) >> -+ OP_ALG_ALGSEL_SHIFT] * 2; -+ ctx->split_key_pad_len = ALIGN(ctx->split_key_len, 16); - -- /* assoclen = (assoclen + cryptlen) - cryptlen */ -- append_math_sub(desc, REG1, REG2, REG3, CAAM_CMD_SZ); -+#ifdef DEBUG -+ printk(KERN_ERR "keylen %d enckeylen %d authkeylen %d\n", -+ keylen, enckeylen, authkeylen); -+ printk(KERN_ERR "split_key_len %d split_key_pad_len %d\n", -+ ctx->split_key_len, ctx->split_key_pad_len); -+ print_hex_dump(KERN_ERR, "key in @"xstr(__LINE__)": ", -+ DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1); -+#endif - -- /* if cryptlen is ZERO jump to zero-payload commands */ -- append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ); -- zero_payload_jump_cmd = append_jump(desc, JUMP_TEST_ALL | -- JUMP_COND_MATH_Z); -- /* read IV */ -- append_seq_fifo_load(desc, tfm->ivsize, FIFOLD_CLASS_CLASS1 | -- FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1); -- -- /* if assoclen is ZERO, skip reading the assoc data */ -- append_math_add(desc, VARSEQINLEN, ZERO, REG1, CAAM_CMD_SZ); -- zero_assoc_jump_cmd1 = append_jump(desc, JUMP_TEST_ALL | -- JUMP_COND_MATH_Z); -- -- /* read assoc data */ -- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF | -- FIFOLD_TYPE_AAD | FIFOLD_TYPE_FLUSH1); -- set_jump_tgt_here(desc, zero_assoc_jump_cmd1); -+ ret = gen_split_aead_key(ctx, key, authkeylen); -+ if (ret) { -+ goto badkey; -+ } - -- append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ); -+ /* postpend encryption key to auth split key */ -+ memcpy(ctx->key + ctx->split_key_pad_len, key + authkeylen, enckeylen); - -- /* write encrypted data */ -- append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | FIFOLDST_VLF); -+ ctx->key_dma = dma_map_single(jrdev, ctx->key, ctx->split_key_pad_len + -+ enckeylen, DMA_TO_DEVICE); -+ if (dma_mapping_error(jrdev, ctx->key_dma)) { -+ dev_err(jrdev, "unable to map key i/o memory\n"); -+ return -ENOMEM; -+ } -+#ifdef DEBUG -+ print_hex_dump(KERN_ERR, "ctx.key@"xstr(__LINE__)": ", -+ DUMP_PREFIX_ADDRESS, 16, 4, ctx->key, -+ ctx->split_key_pad_len + enckeylen, 1); -+#endif -+ dma_sync_single_for_device(jrdev, ctx->key_dma, -+ ctx->split_key_pad_len + enckeylen, -+ DMA_TO_DEVICE); - -- /* read payload data */ -- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF | -- FIFOLD_TYPE_MSG | FIFOLD_TYPE_LAST1); -- -- /* jump the zero-payload commands */ -- append_jump(desc, JUMP_TEST_ALL | 7); -- -- /* zero-payload commands */ -- set_jump_tgt_here(desc, zero_payload_jump_cmd); -- -- /* if assoclen is ZERO, jump to IV reading - is the only input data */ -- append_math_add(desc, VARSEQINLEN, ZERO, REG1, CAAM_CMD_SZ); -- zero_assoc_jump_cmd2 = append_jump(desc, JUMP_TEST_ALL | -- JUMP_COND_MATH_Z); -- /* read IV */ -- append_seq_fifo_load(desc, tfm->ivsize, FIFOLD_CLASS_CLASS1 | -- FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1); -- -- /* read assoc data */ -- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF | -- FIFOLD_TYPE_AAD | FIFOLD_TYPE_LAST1); -- -- /* jump to ICV writing */ -- append_jump(desc, JUMP_TEST_ALL | 2); -- -- /* read IV - is the only input data */ -- set_jump_tgt_here(desc, zero_assoc_jump_cmd2); -- append_seq_fifo_load(desc, tfm->ivsize, FIFOLD_CLASS_CLASS1 | -- FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1 | -- FIFOLD_TYPE_LAST1); -- -- /* write ICV */ -- append_seq_store(desc, ctx->authsize, LDST_CLASS_1_CCB | -- LDST_SRCDST_BYTE_CONTEXT); -- -- ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc, -- desc_bytes(desc), -- DMA_TO_DEVICE); -- if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) { -- dev_err(jrdev, "unable to map shared descriptor\n"); -- return -ENOMEM; -- } --#ifdef DEBUG -- print_hex_dump(KERN_ERR, "gcm enc shdesc@"__stringify(__LINE__)": ", -- DUMP_PREFIX_ADDRESS, 16, 4, desc, -- desc_bytes(desc), 1); --#endif -- -- /* -- * Job Descriptor and Shared Descriptors -- * must all fit into the 64-word Descriptor h/w Buffer -- */ -- keys_fit_inline = false; -- if (DESC_GCM_DEC_LEN + DESC_JOB_IO_LEN + -- ctx->enckeylen <= CAAM_DESC_BYTES_MAX) -- keys_fit_inline = true; -- -- desc = ctx->sh_desc_dec; -- -- init_sh_desc(desc, HDR_SHARE_SERIAL); -- -- /* skip key loading if they are loaded due to sharing */ -- key_jump_cmd = append_jump(desc, JUMP_JSL | -- JUMP_TEST_ALL | JUMP_COND_SHRD | -- JUMP_COND_SELF); -- if (keys_fit_inline) -- append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen, -- ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG); -- else -- append_key(desc, ctx->key_dma, ctx->enckeylen, -- CLASS_1 | KEY_DEST_CLASS_REG); -- set_jump_tgt_here(desc, key_jump_cmd); -- -- /* class 1 operation */ -- append_operation(desc, ctx->class1_alg_type | -- OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT | OP_ALG_ICV_ON); -- -- /* assoclen + cryptlen = seqinlen - ivsize - icvsize */ -- append_math_sub_imm_u32(desc, REG3, SEQINLEN, IMM, -- ctx->authsize + tfm->ivsize); -- -- /* assoclen = (assoclen + cryptlen) - cryptlen */ -- append_math_sub(desc, REG2, SEQOUTLEN, REG0, CAAM_CMD_SZ); -- append_math_sub(desc, REG1, REG3, REG2, CAAM_CMD_SZ); -- -- /* read IV */ -- append_seq_fifo_load(desc, tfm->ivsize, FIFOLD_CLASS_CLASS1 | -- FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1); -- -- /* jump to zero-payload command if cryptlen is zero */ -- append_math_add(desc, VARSEQOUTLEN, ZERO, REG2, CAAM_CMD_SZ); -- zero_payload_jump_cmd = append_jump(desc, JUMP_TEST_ALL | -- JUMP_COND_MATH_Z); -- -- append_math_add(desc, VARSEQINLEN, ZERO, REG1, CAAM_CMD_SZ); -- /* if asoclen is ZERO, skip reading assoc data */ -- zero_assoc_jump_cmd1 = append_jump(desc, JUMP_TEST_ALL | -- JUMP_COND_MATH_Z); -- /* read assoc data */ -- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF | -- FIFOLD_TYPE_AAD | FIFOLD_TYPE_FLUSH1); -- set_jump_tgt_here(desc, zero_assoc_jump_cmd1); -- -- append_math_add(desc, VARSEQINLEN, ZERO, REG2, CAAM_CMD_SZ); -- -- /* store encrypted data */ -- append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | FIFOLDST_VLF); -- -- /* read payload data */ -- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF | -- FIFOLD_TYPE_MSG | FIFOLD_TYPE_FLUSH1); -- -- /* jump the zero-payload commands */ -- append_jump(desc, JUMP_TEST_ALL | 4); -- -- /* zero-payload command */ -- set_jump_tgt_here(desc, zero_payload_jump_cmd); -- -- /* if assoclen is ZERO, jump to ICV reading */ -- append_math_add(desc, VARSEQINLEN, ZERO, REG1, CAAM_CMD_SZ); -- zero_assoc_jump_cmd2 = append_jump(desc, JUMP_TEST_ALL | -- JUMP_COND_MATH_Z); -- /* read assoc data */ -- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF | -- FIFOLD_TYPE_AAD | FIFOLD_TYPE_FLUSH1); -- set_jump_tgt_here(desc, zero_assoc_jump_cmd2); -- -- /* read ICV */ -- append_seq_fifo_load(desc, ctx->authsize, FIFOLD_CLASS_CLASS1 | -- FIFOLD_TYPE_ICV | FIFOLD_TYPE_LAST1); -- -- ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc, -- desc_bytes(desc), -- DMA_TO_DEVICE); -- if (dma_mapping_error(jrdev, ctx->sh_desc_dec_dma)) { -- dev_err(jrdev, "unable to map shared descriptor\n"); -- return -ENOMEM; -- } --#ifdef DEBUG -- print_hex_dump(KERN_ERR, "gcm dec shdesc@"__stringify(__LINE__)": ", -- DUMP_PREFIX_ADDRESS, 16, 4, desc, -- desc_bytes(desc), 1); --#endif -- -- return 0; --} -- --static int gcm_setauthsize(struct crypto_aead *authenc, unsigned int authsize) --{ -- struct caam_ctx *ctx = crypto_aead_ctx(authenc); -- -- ctx->authsize = authsize; -- gcm_set_sh_desc(authenc); -- -- return 0; --} -- --static int rfc4106_set_sh_desc(struct crypto_aead *aead) --{ -- struct aead_tfm *tfm = &aead->base.crt_aead; -- struct caam_ctx *ctx = crypto_aead_ctx(aead); -- struct device *jrdev = ctx->jrdev; -- bool keys_fit_inline = false; -- u32 *key_jump_cmd, *move_cmd, *write_iv_cmd; -- u32 *desc; -- u32 geniv; -- -- if (!ctx->enckeylen || !ctx->authsize) -- return 0; -- -- /* -- * RFC4106 encrypt shared descriptor -- * Job Descriptor and Shared Descriptor -- * must fit into the 64-word Descriptor h/w Buffer -- */ -- if (DESC_RFC4106_ENC_LEN + DESC_JOB_IO_LEN + -- ctx->enckeylen <= CAAM_DESC_BYTES_MAX) -- keys_fit_inline = true; -- -- desc = ctx->sh_desc_enc; -- -- init_sh_desc(desc, HDR_SHARE_SERIAL); -- -- /* Skip key loading if it is loaded due to sharing */ -- key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | -- JUMP_COND_SHRD); -- if (keys_fit_inline) -- append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen, -- ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG); -- else -- append_key(desc, ctx->key_dma, ctx->enckeylen, -- CLASS_1 | KEY_DEST_CLASS_REG); -- set_jump_tgt_here(desc, key_jump_cmd); -- -- /* Class 1 operation */ -- append_operation(desc, ctx->class1_alg_type | -- OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT); -- -- /* cryptlen = seqoutlen - authsize */ -- append_math_sub_imm_u32(desc, REG3, SEQOUTLEN, IMM, ctx->authsize); -- append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ); -- -- /* assoclen + cryptlen = seqinlen - ivsize */ -- append_math_sub_imm_u32(desc, REG2, SEQINLEN, IMM, tfm->ivsize); -- -- /* assoclen = (assoclen + cryptlen) - cryptlen */ -- append_math_sub(desc, VARSEQINLEN, REG2, REG3, CAAM_CMD_SZ); -- -- /* Read Salt */ -- append_fifo_load_as_imm(desc, (void *)(ctx->key + ctx->enckeylen), -- 4, FIFOLD_CLASS_CLASS1 | FIFOLD_TYPE_IV); -- /* Read AES-GCM-ESP IV */ -- append_seq_fifo_load(desc, tfm->ivsize, FIFOLD_CLASS_CLASS1 | -- FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1); -- -- /* Read assoc data */ -- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF | -- FIFOLD_TYPE_AAD | FIFOLD_TYPE_FLUSH1); -- -- /* Will read cryptlen bytes */ -- append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ); -- -- /* Write encrypted data */ -- append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | FIFOLDST_VLF); -- -- /* Read payload data */ -- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF | -- FIFOLD_TYPE_MSG | FIFOLD_TYPE_LAST1); -- -- /* Write ICV */ -- append_seq_store(desc, ctx->authsize, LDST_CLASS_1_CCB | -- LDST_SRCDST_BYTE_CONTEXT); -- -- ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc, -- desc_bytes(desc), -- DMA_TO_DEVICE); -- if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) { -- dev_err(jrdev, "unable to map shared descriptor\n"); -- return -ENOMEM; -- } --#ifdef DEBUG -- print_hex_dump(KERN_ERR, "rfc4106 enc shdesc@"__stringify(__LINE__)": ", -- DUMP_PREFIX_ADDRESS, 16, 4, desc, -- desc_bytes(desc), 1); --#endif -- -- /* -- * Job Descriptor and Shared Descriptors -- * must all fit into the 64-word Descriptor h/w Buffer -- */ -- keys_fit_inline = false; -- if (DESC_RFC4106_DEC_LEN + DESC_JOB_IO_LEN + -- ctx->enckeylen <= CAAM_DESC_BYTES_MAX) -- keys_fit_inline = true; -- -- desc = ctx->sh_desc_dec; -- -- init_sh_desc(desc, HDR_SHARE_SERIAL); -- -- /* Skip key loading if it is loaded due to sharing */ -- key_jump_cmd = append_jump(desc, JUMP_JSL | -- JUMP_TEST_ALL | JUMP_COND_SHRD); -- if (keys_fit_inline) -- append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen, -- ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG); -- else -- append_key(desc, ctx->key_dma, ctx->enckeylen, -- CLASS_1 | KEY_DEST_CLASS_REG); -- set_jump_tgt_here(desc, key_jump_cmd); -- -- /* Class 1 operation */ -- append_operation(desc, ctx->class1_alg_type | -- OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT | OP_ALG_ICV_ON); -- -- /* assoclen + cryptlen = seqinlen - ivsize - icvsize */ -- append_math_sub_imm_u32(desc, REG3, SEQINLEN, IMM, -- ctx->authsize + tfm->ivsize); -- -- /* assoclen = (assoclen + cryptlen) - cryptlen */ -- append_math_sub(desc, REG2, SEQOUTLEN, REG0, CAAM_CMD_SZ); -- append_math_sub(desc, VARSEQINLEN, REG3, REG2, CAAM_CMD_SZ); -- -- /* Will write cryptlen bytes */ -- append_math_sub(desc, VARSEQOUTLEN, SEQOUTLEN, REG0, CAAM_CMD_SZ); -- -- /* Read Salt */ -- append_fifo_load_as_imm(desc, (void *)(ctx->key + ctx->enckeylen), -- 4, FIFOLD_CLASS_CLASS1 | FIFOLD_TYPE_IV); -- /* Read AES-GCM-ESP IV */ -- append_seq_fifo_load(desc, tfm->ivsize, FIFOLD_CLASS_CLASS1 | -- FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1); -- -- /* Read assoc data */ -- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF | -- FIFOLD_TYPE_AAD | FIFOLD_TYPE_FLUSH1); -- -- /* Will read cryptlen bytes */ -- append_math_add(desc, VARSEQINLEN, ZERO, REG2, CAAM_CMD_SZ); -- -- /* Store payload data */ -- append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | FIFOLDST_VLF); -- -- /* Read encrypted data */ -- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF | -- FIFOLD_TYPE_MSG | FIFOLD_TYPE_FLUSH1); -- -- /* Read ICV */ -- append_seq_fifo_load(desc, ctx->authsize, FIFOLD_CLASS_CLASS1 | -- FIFOLD_TYPE_ICV | FIFOLD_TYPE_LAST1); -- -- ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc, -- desc_bytes(desc), -- DMA_TO_DEVICE); -- if (dma_mapping_error(jrdev, ctx->sh_desc_dec_dma)) { -- dev_err(jrdev, "unable to map shared descriptor\n"); -- return -ENOMEM; -- } --#ifdef DEBUG -- print_hex_dump(KERN_ERR, "rfc4106 dec shdesc@"__stringify(__LINE__)": ", -- DUMP_PREFIX_ADDRESS, 16, 4, desc, -- desc_bytes(desc), 1); --#endif -- -- /* -- * Job Descriptor and Shared Descriptors -- * must all fit into the 64-word Descriptor h/w Buffer -- */ -- keys_fit_inline = false; -- if (DESC_RFC4106_GIVENC_LEN + DESC_JOB_IO_LEN + -- ctx->split_key_pad_len + ctx->enckeylen <= -- CAAM_DESC_BYTES_MAX) -- keys_fit_inline = true; -- -- /* rfc4106_givencrypt shared descriptor */ -- desc = ctx->sh_desc_givenc; -- -- init_sh_desc(desc, HDR_SHARE_SERIAL); -- -- /* Skip key loading if it is loaded due to sharing */ -- key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | -- JUMP_COND_SHRD); -- if (keys_fit_inline) -- append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen, -- ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG); -- else -- append_key(desc, ctx->key_dma, ctx->enckeylen, -- CLASS_1 | KEY_DEST_CLASS_REG); -- set_jump_tgt_here(desc, key_jump_cmd); -- -- /* Generate IV */ -- geniv = NFIFOENTRY_STYPE_PAD | NFIFOENTRY_DEST_DECO | -- NFIFOENTRY_DTYPE_MSG | NFIFOENTRY_LC1 | -- NFIFOENTRY_PTYPE_RND | (tfm->ivsize << NFIFOENTRY_DLEN_SHIFT); -- append_load_imm_u32(desc, geniv, LDST_CLASS_IND_CCB | -- LDST_SRCDST_WORD_INFO_FIFO | LDST_IMM); -- append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO); -- move_cmd = append_move(desc, MOVE_SRC_INFIFO | MOVE_DEST_DESCBUF | -- (tfm->ivsize << MOVE_LEN_SHIFT)); -- append_cmd(desc, CMD_LOAD | ENABLE_AUTO_INFO_FIFO); -- -- /* Copy generated IV to OFIFO */ -- write_iv_cmd = append_move(desc, MOVE_SRC_DESCBUF | MOVE_DEST_OUTFIFO | -- (tfm->ivsize << MOVE_LEN_SHIFT)); -- -- /* Class 1 operation */ -- append_operation(desc, ctx->class1_alg_type | -- OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT); -- -- /* ivsize + cryptlen = seqoutlen - authsize */ -- append_math_sub_imm_u32(desc, REG3, SEQOUTLEN, IMM, ctx->authsize); -- -- /* assoclen = seqinlen - (ivsize + cryptlen) */ -- append_math_sub(desc, VARSEQINLEN, SEQINLEN, REG3, CAAM_CMD_SZ); -- -- /* Will write ivsize + cryptlen */ -- append_math_add(desc, VARSEQOUTLEN, REG3, REG0, CAAM_CMD_SZ); -- -- /* Read Salt and generated IV */ -- append_cmd(desc, CMD_FIFO_LOAD | FIFOLD_CLASS_CLASS1 | FIFOLD_TYPE_IV | -- FIFOLD_TYPE_FLUSH1 | IMMEDIATE | 12); -- /* Append Salt */ -- append_data(desc, (void *)(ctx->key + ctx->enckeylen), 4); -- set_move_tgt_here(desc, move_cmd); -- set_move_tgt_here(desc, write_iv_cmd); -- /* Blank commands. Will be overwritten by generated IV. */ -- append_cmd(desc, 0x00000000); -- append_cmd(desc, 0x00000000); -- /* End of blank commands */ -- -- /* No need to reload iv */ -- append_seq_fifo_load(desc, tfm->ivsize, FIFOLD_CLASS_SKIP); -- -- /* Read assoc data */ -- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF | -- FIFOLD_TYPE_AAD | FIFOLD_TYPE_FLUSH1); -- -- /* Will read cryptlen */ -- append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ); -- -- /* Store generated IV and encrypted data */ -- append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | FIFOLDST_VLF); -- -- /* Read payload data */ -- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF | -- FIFOLD_TYPE_MSG | FIFOLD_TYPE_LAST1); -- -- /* Write ICV */ -- append_seq_store(desc, ctx->authsize, LDST_CLASS_1_CCB | -- LDST_SRCDST_BYTE_CONTEXT); -- -- ctx->sh_desc_givenc_dma = dma_map_single(jrdev, desc, -- desc_bytes(desc), -- DMA_TO_DEVICE); -- if (dma_mapping_error(jrdev, ctx->sh_desc_givenc_dma)) { -- dev_err(jrdev, "unable to map shared descriptor\n"); -- return -ENOMEM; -- } --#ifdef DEBUG -- print_hex_dump(KERN_ERR, -- "rfc4106 givenc shdesc@"__stringify(__LINE__)": ", -- DUMP_PREFIX_ADDRESS, 16, 4, desc, -- desc_bytes(desc), 1); --#endif -- -- return 0; --} -- --static int rfc4106_setauthsize(struct crypto_aead *authenc, -- unsigned int authsize) --{ -- struct caam_ctx *ctx = crypto_aead_ctx(authenc); -- -- ctx->authsize = authsize; -- rfc4106_set_sh_desc(authenc); -- -- return 0; --} -- --static int rfc4543_set_sh_desc(struct crypto_aead *aead) --{ -- struct aead_tfm *tfm = &aead->base.crt_aead; -- struct caam_ctx *ctx = crypto_aead_ctx(aead); -- struct device *jrdev = ctx->jrdev; -- bool keys_fit_inline = false; -- u32 *key_jump_cmd, *write_iv_cmd, *write_aad_cmd; -- u32 *read_move_cmd, *write_move_cmd; -- u32 *desc; -- u32 geniv; -- -- if (!ctx->enckeylen || !ctx->authsize) -- return 0; -- -- /* -- * RFC4543 encrypt shared descriptor -- * Job Descriptor and Shared Descriptor -- * must fit into the 64-word Descriptor h/w Buffer -- */ -- if (DESC_RFC4543_ENC_LEN + DESC_JOB_IO_LEN + -- ctx->enckeylen <= CAAM_DESC_BYTES_MAX) -- keys_fit_inline = true; -- -- desc = ctx->sh_desc_enc; -- -- init_sh_desc(desc, HDR_SHARE_SERIAL); -- -- /* Skip key loading if it is loaded due to sharing */ -- key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | -- JUMP_COND_SHRD); -- if (keys_fit_inline) -- append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen, -- ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG); -- else -- append_key(desc, ctx->key_dma, ctx->enckeylen, -- CLASS_1 | KEY_DEST_CLASS_REG); -- set_jump_tgt_here(desc, key_jump_cmd); -- -- /* Class 1 operation */ -- append_operation(desc, ctx->class1_alg_type | -- OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT); -- -- /* Load AES-GMAC ESP IV into Math1 register */ -- append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_WORD_DECO_MATH1 | -- LDST_CLASS_DECO | tfm->ivsize); -- -- /* Wait the DMA transaction to finish */ -- append_jump(desc, JUMP_TEST_ALL | JUMP_COND_CALM | -- (1 << JUMP_OFFSET_SHIFT)); -- -- /* Overwrite blank immediate AES-GMAC ESP IV data */ -- write_iv_cmd = append_move(desc, MOVE_SRC_MATH1 | MOVE_DEST_DESCBUF | -- (tfm->ivsize << MOVE_LEN_SHIFT)); -- -- /* Overwrite blank immediate AAD data */ -- write_aad_cmd = append_move(desc, MOVE_SRC_MATH1 | MOVE_DEST_DESCBUF | -- (tfm->ivsize << MOVE_LEN_SHIFT)); -- -- /* cryptlen = seqoutlen - authsize */ -- append_math_sub_imm_u32(desc, REG3, SEQOUTLEN, IMM, ctx->authsize); -- -- /* assoclen = (seqinlen - ivsize) - cryptlen */ -- append_math_sub(desc, VARSEQINLEN, SEQINLEN, REG3, CAAM_CMD_SZ); -- -- /* Read Salt and AES-GMAC ESP IV */ -- append_cmd(desc, CMD_FIFO_LOAD | FIFOLD_CLASS_CLASS1 | IMMEDIATE | -- FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1 | (4 + tfm->ivsize)); -- /* Append Salt */ -- append_data(desc, (void *)(ctx->key + ctx->enckeylen), 4); -- set_move_tgt_here(desc, write_iv_cmd); -- /* Blank commands. Will be overwritten by AES-GMAC ESP IV. */ -- append_cmd(desc, 0x00000000); -- append_cmd(desc, 0x00000000); -- /* End of blank commands */ -- -- /* Read assoc data */ -- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF | -- FIFOLD_TYPE_AAD); -- -- /* Will read cryptlen bytes */ -- append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ); -- -- /* Will write cryptlen bytes */ -- append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ); -- -- /* -- * MOVE_LEN opcode is not available in all SEC HW revisions, -- * thus need to do some magic, i.e. self-patch the descriptor -- * buffer. -- */ -- read_move_cmd = append_move(desc, MOVE_SRC_DESCBUF | MOVE_DEST_MATH3 | -- (0x6 << MOVE_LEN_SHIFT)); -- write_move_cmd = append_move(desc, MOVE_SRC_MATH3 | MOVE_DEST_DESCBUF | -- (0x8 << MOVE_LEN_SHIFT)); -- -- /* Authenticate AES-GMAC ESP IV */ -- append_cmd(desc, CMD_FIFO_LOAD | FIFOLD_CLASS_CLASS1 | IMMEDIATE | -- FIFOLD_TYPE_AAD | tfm->ivsize); -- set_move_tgt_here(desc, write_aad_cmd); -- /* Blank commands. Will be overwritten by AES-GMAC ESP IV. */ -- append_cmd(desc, 0x00000000); -- append_cmd(desc, 0x00000000); -- /* End of blank commands */ -- -- /* Read and write cryptlen bytes */ -- aead_append_src_dst(desc, FIFOLD_TYPE_AAD); -- -- set_move_tgt_here(desc, read_move_cmd); -- set_move_tgt_here(desc, write_move_cmd); -- append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO); -- /* Move payload data to OFIFO */ -- append_move(desc, MOVE_SRC_INFIFO_CL | MOVE_DEST_OUTFIFO); -- -- /* Write ICV */ -- append_seq_store(desc, ctx->authsize, LDST_CLASS_1_CCB | -- LDST_SRCDST_BYTE_CONTEXT); -- -- ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc, -- desc_bytes(desc), -- DMA_TO_DEVICE); -- if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) { -- dev_err(jrdev, "unable to map shared descriptor\n"); -- return -ENOMEM; -- } --#ifdef DEBUG -- print_hex_dump(KERN_ERR, "rfc4543 enc shdesc@"__stringify(__LINE__)": ", -- DUMP_PREFIX_ADDRESS, 16, 4, desc, -- desc_bytes(desc), 1); --#endif -- -- /* -- * Job Descriptor and Shared Descriptors -- * must all fit into the 64-word Descriptor h/w Buffer -- */ -- keys_fit_inline = false; -- if (DESC_RFC4543_DEC_LEN + DESC_JOB_IO_LEN + -- ctx->enckeylen <= CAAM_DESC_BYTES_MAX) -- keys_fit_inline = true; -- -- desc = ctx->sh_desc_dec; -- -- init_sh_desc(desc, HDR_SHARE_SERIAL); -- -- /* Skip key loading if it is loaded due to sharing */ -- key_jump_cmd = append_jump(desc, JUMP_JSL | -- JUMP_TEST_ALL | JUMP_COND_SHRD); -- if (keys_fit_inline) -- append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen, -- ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG); -- else -- append_key(desc, ctx->key_dma, ctx->enckeylen, -- CLASS_1 | KEY_DEST_CLASS_REG); -- set_jump_tgt_here(desc, key_jump_cmd); -- -- /* Class 1 operation */ -- append_operation(desc, ctx->class1_alg_type | -- OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT | OP_ALG_ICV_ON); -- -- /* Load AES-GMAC ESP IV into Math1 register */ -- append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_WORD_DECO_MATH1 | -- LDST_CLASS_DECO | tfm->ivsize); -- -- /* Wait the DMA transaction to finish */ -- append_jump(desc, JUMP_TEST_ALL | JUMP_COND_CALM | -- (1 << JUMP_OFFSET_SHIFT)); -- -- /* assoclen + cryptlen = (seqinlen - ivsize) - icvsize */ -- append_math_sub_imm_u32(desc, REG3, SEQINLEN, IMM, ctx->authsize); -- -- /* Overwrite blank immediate AES-GMAC ESP IV data */ -- write_iv_cmd = append_move(desc, MOVE_SRC_MATH1 | MOVE_DEST_DESCBUF | -- (tfm->ivsize << MOVE_LEN_SHIFT)); -- -- /* Overwrite blank immediate AAD data */ -- write_aad_cmd = append_move(desc, MOVE_SRC_MATH1 | MOVE_DEST_DESCBUF | -- (tfm->ivsize << MOVE_LEN_SHIFT)); -- -- /* assoclen = (assoclen + cryptlen) - cryptlen */ -- append_math_sub(desc, REG2, SEQOUTLEN, REG0, CAAM_CMD_SZ); -- append_math_sub(desc, VARSEQINLEN, REG3, REG2, CAAM_CMD_SZ); -- -- /* -- * MOVE_LEN opcode is not available in all SEC HW revisions, -- * thus need to do some magic, i.e. self-patch the descriptor -- * buffer. -- */ -- read_move_cmd = append_move(desc, MOVE_SRC_DESCBUF | MOVE_DEST_MATH3 | -- (0x6 << MOVE_LEN_SHIFT)); -- write_move_cmd = append_move(desc, MOVE_SRC_MATH3 | MOVE_DEST_DESCBUF | -- (0x8 << MOVE_LEN_SHIFT)); -- -- /* Read Salt and AES-GMAC ESP IV */ -- append_cmd(desc, CMD_FIFO_LOAD | FIFOLD_CLASS_CLASS1 | IMMEDIATE | -- FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1 | (4 + tfm->ivsize)); -- /* Append Salt */ -- append_data(desc, (void *)(ctx->key + ctx->enckeylen), 4); -- set_move_tgt_here(desc, write_iv_cmd); -- /* Blank commands. Will be overwritten by AES-GMAC ESP IV. */ -- append_cmd(desc, 0x00000000); -- append_cmd(desc, 0x00000000); -- /* End of blank commands */ -- -- /* Read assoc data */ -- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF | -- FIFOLD_TYPE_AAD); -- -- /* Will read cryptlen bytes */ -- append_math_add(desc, VARSEQINLEN, ZERO, REG2, CAAM_CMD_SZ); -- -- /* Will write cryptlen bytes */ -- append_math_add(desc, VARSEQOUTLEN, ZERO, REG2, CAAM_CMD_SZ); -- -- /* Authenticate AES-GMAC ESP IV */ -- append_cmd(desc, CMD_FIFO_LOAD | FIFOLD_CLASS_CLASS1 | IMMEDIATE | -- FIFOLD_TYPE_AAD | tfm->ivsize); -- set_move_tgt_here(desc, write_aad_cmd); -- /* Blank commands. Will be overwritten by AES-GMAC ESP IV. */ -- append_cmd(desc, 0x00000000); -- append_cmd(desc, 0x00000000); -- /* End of blank commands */ -- -- /* Store payload data */ -- append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | FIFOLDST_VLF); -- -- /* In-snoop cryptlen data */ -- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_BOTH | FIFOLDST_VLF | -- FIFOLD_TYPE_AAD | FIFOLD_TYPE_LAST2FLUSH1); -- -- set_move_tgt_here(desc, read_move_cmd); -- set_move_tgt_here(desc, write_move_cmd); -- append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO); -- /* Move payload data to OFIFO */ -- append_move(desc, MOVE_SRC_INFIFO_CL | MOVE_DEST_OUTFIFO); -- append_cmd(desc, CMD_LOAD | ENABLE_AUTO_INFO_FIFO); -- -- /* Read ICV */ -- append_seq_fifo_load(desc, ctx->authsize, FIFOLD_CLASS_CLASS1 | -- FIFOLD_TYPE_ICV | FIFOLD_TYPE_LAST1); -- -- ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc, -- desc_bytes(desc), -- DMA_TO_DEVICE); -- if (dma_mapping_error(jrdev, ctx->sh_desc_dec_dma)) { -- dev_err(jrdev, "unable to map shared descriptor\n"); -- return -ENOMEM; -- } --#ifdef DEBUG -- print_hex_dump(KERN_ERR, "rfc4543 dec shdesc@"__stringify(__LINE__)": ", -- DUMP_PREFIX_ADDRESS, 16, 4, desc, -- desc_bytes(desc), 1); --#endif -- -- /* -- * Job Descriptor and Shared Descriptors -- * must all fit into the 64-word Descriptor h/w Buffer -- */ -- keys_fit_inline = false; -- if (DESC_RFC4543_GIVENC_LEN + DESC_JOB_IO_LEN + -- ctx->enckeylen <= CAAM_DESC_BYTES_MAX) -- keys_fit_inline = true; -- -- /* rfc4543_givencrypt shared descriptor */ -- desc = ctx->sh_desc_givenc; -- -- init_sh_desc(desc, HDR_SHARE_SERIAL); -- -- /* Skip key loading if it is loaded due to sharing */ -- key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | -- JUMP_COND_SHRD); -- if (keys_fit_inline) -- append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen, -- ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG); -- else -- append_key(desc, ctx->key_dma, ctx->enckeylen, -- CLASS_1 | KEY_DEST_CLASS_REG); -- set_jump_tgt_here(desc, key_jump_cmd); -- -- /* Generate IV */ -- geniv = NFIFOENTRY_STYPE_PAD | NFIFOENTRY_DEST_DECO | -- NFIFOENTRY_DTYPE_MSG | NFIFOENTRY_LC1 | -- NFIFOENTRY_PTYPE_RND | (tfm->ivsize << NFIFOENTRY_DLEN_SHIFT); -- append_load_imm_u32(desc, geniv, LDST_CLASS_IND_CCB | -- LDST_SRCDST_WORD_INFO_FIFO | LDST_IMM); -- append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO); -- /* Move generated IV to Math1 register */ -- append_move(desc, MOVE_SRC_INFIFO | MOVE_DEST_MATH1 | -- (tfm->ivsize << MOVE_LEN_SHIFT)); -- append_cmd(desc, CMD_LOAD | ENABLE_AUTO_INFO_FIFO); -- -- /* Overwrite blank immediate AES-GMAC IV data */ -- write_iv_cmd = append_move(desc, MOVE_SRC_MATH1 | MOVE_DEST_DESCBUF | -- (tfm->ivsize << MOVE_LEN_SHIFT)); -- -- /* Overwrite blank immediate AAD data */ -- write_aad_cmd = append_move(desc, MOVE_SRC_MATH1 | MOVE_DEST_DESCBUF | -- (tfm->ivsize << MOVE_LEN_SHIFT)); -- -- /* Copy generated IV to OFIFO */ -- append_move(desc, MOVE_SRC_MATH1 | MOVE_DEST_OUTFIFO | -- (tfm->ivsize << MOVE_LEN_SHIFT)); -- -- /* Class 1 operation */ -- append_operation(desc, ctx->class1_alg_type | -- OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT); -- -- /* ivsize + cryptlen = seqoutlen - authsize */ -- append_math_sub_imm_u32(desc, REG3, SEQOUTLEN, IMM, ctx->authsize); -- -- /* assoclen = seqinlen - (ivsize + cryptlen) */ -- append_math_sub(desc, VARSEQINLEN, SEQINLEN, REG3, CAAM_CMD_SZ); -- -- /* Will write ivsize + cryptlen */ -- append_math_add(desc, VARSEQOUTLEN, REG3, REG0, CAAM_CMD_SZ); -- -- /* -- * MOVE_LEN opcode is not available in all SEC HW revisions, -- * thus need to do some magic, i.e. self-patch the descriptor -- * buffer. -- */ -- read_move_cmd = append_move(desc, MOVE_SRC_DESCBUF | MOVE_DEST_MATH3 | -- (0x6 << MOVE_LEN_SHIFT)); -- write_move_cmd = append_move(desc, MOVE_SRC_MATH3 | MOVE_DEST_DESCBUF | -- (0x8 << MOVE_LEN_SHIFT)); -- -- /* Read Salt and AES-GMAC generated IV */ -- append_cmd(desc, CMD_FIFO_LOAD | FIFOLD_CLASS_CLASS1 | IMMEDIATE | -- FIFOLD_TYPE_IV | FIFOLD_TYPE_FLUSH1 | (4 + tfm->ivsize)); -- /* Append Salt */ -- append_data(desc, (void *)(ctx->key + ctx->enckeylen), 4); -- set_move_tgt_here(desc, write_iv_cmd); -- /* Blank commands. Will be overwritten by AES-GMAC generated IV. */ -- append_cmd(desc, 0x00000000); -- append_cmd(desc, 0x00000000); -- /* End of blank commands */ -- -- /* No need to reload iv */ -- append_seq_fifo_load(desc, tfm->ivsize, FIFOLD_CLASS_SKIP); -- -- /* Read assoc data */ -- append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLDST_VLF | -- FIFOLD_TYPE_AAD); -- -- /* Will read cryptlen */ -- append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ); -- -- /* Authenticate AES-GMAC IV */ -- append_cmd(desc, CMD_FIFO_LOAD | FIFOLD_CLASS_CLASS1 | IMMEDIATE | -- FIFOLD_TYPE_AAD | tfm->ivsize); -- set_move_tgt_here(desc, write_aad_cmd); -- /* Blank commands. Will be overwritten by AES-GMAC IV. */ -- append_cmd(desc, 0x00000000); -- append_cmd(desc, 0x00000000); -- /* End of blank commands */ -- -- /* Read and write cryptlen bytes */ -- aead_append_src_dst(desc, FIFOLD_TYPE_AAD); -- -- set_move_tgt_here(desc, read_move_cmd); -- set_move_tgt_here(desc, write_move_cmd); -- append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO); -- /* Move payload data to OFIFO */ -- append_move(desc, MOVE_SRC_INFIFO_CL | MOVE_DEST_OUTFIFO); -- -- /* Write ICV */ -- append_seq_store(desc, ctx->authsize, LDST_CLASS_1_CCB | -- LDST_SRCDST_BYTE_CONTEXT); -- -- ctx->sh_desc_givenc_dma = dma_map_single(jrdev, desc, -- desc_bytes(desc), -- DMA_TO_DEVICE); -- if (dma_mapping_error(jrdev, ctx->sh_desc_givenc_dma)) { -- dev_err(jrdev, "unable to map shared descriptor\n"); -- return -ENOMEM; -- } --#ifdef DEBUG -- print_hex_dump(KERN_ERR, -- "rfc4543 givenc shdesc@"__stringify(__LINE__)": ", -- DUMP_PREFIX_ADDRESS, 16, 4, desc, -- desc_bytes(desc), 1); --#endif -- -- return 0; --} -- --static int rfc4543_setauthsize(struct crypto_aead *authenc, -- unsigned int authsize) --{ -- struct caam_ctx *ctx = crypto_aead_ctx(authenc); -- -- ctx->authsize = authsize; -- rfc4543_set_sh_desc(authenc); -- -- return 0; --} -- --static u32 gen_split_aead_key(struct caam_ctx *ctx, const u8 *key_in, -- u32 authkeylen) --{ -- return gen_split_key(ctx->jrdev, ctx->key, ctx->split_key_len, -- ctx->split_key_pad_len, key_in, authkeylen, -- ctx->alg_op); --} -- --static int aead_setkey(struct crypto_aead *aead, -- const u8 *key, unsigned int keylen) --{ -- /* Sizes for MDHA pads (*not* keys): MD5, SHA1, 224, 256, 384, 512 */ -- static const u8 mdpadlen[] = { 16, 20, 32, 32, 64, 64 }; -- struct caam_ctx *ctx = crypto_aead_ctx(aead); -- struct device *jrdev = ctx->jrdev; -- struct crypto_authenc_keys keys; -- int ret = 0; -- -- if (crypto_authenc_extractkeys(&keys, key, keylen) != 0) -- goto badkey; -- -- /* Pick class 2 key length from algorithm submask */ -- ctx->split_key_len = mdpadlen[(ctx->alg_op & OP_ALG_ALGSEL_SUBMASK) >> -- OP_ALG_ALGSEL_SHIFT] * 2; -- ctx->split_key_pad_len = ALIGN(ctx->split_key_len, 16); -- -- if (ctx->split_key_pad_len + keys.enckeylen > CAAM_MAX_KEY_SIZE) -- goto badkey; -- --#ifdef DEBUG -- printk(KERN_ERR "keylen %d enckeylen %d authkeylen %d\n", -- keys.authkeylen + keys.enckeylen, keys.enckeylen, -- keys.authkeylen); -- printk(KERN_ERR "split_key_len %d split_key_pad_len %d\n", -- ctx->split_key_len, ctx->split_key_pad_len); -- print_hex_dump(KERN_ERR, "key in @"__stringify(__LINE__)": ", -- DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1); --#endif -- -- ret = gen_split_aead_key(ctx, keys.authkey, keys.authkeylen); -- if (ret) { -- goto badkey; -- } -- -- /* postpend encryption key to auth split key */ -- memcpy(ctx->key + ctx->split_key_pad_len, keys.enckey, keys.enckeylen); -- -- ctx->key_dma = dma_map_single(jrdev, ctx->key, ctx->split_key_pad_len + -- keys.enckeylen, DMA_TO_DEVICE); -- if (dma_mapping_error(jrdev, ctx->key_dma)) { -- dev_err(jrdev, "unable to map key i/o memory\n"); -- return -ENOMEM; -- } --#ifdef DEBUG -- print_hex_dump(KERN_ERR, "ctx.key@"__stringify(__LINE__)": ", -- DUMP_PREFIX_ADDRESS, 16, 4, ctx->key, -- ctx->split_key_pad_len + keys.enckeylen, 1); --#endif -- -- ctx->enckeylen = keys.enckeylen; -+ ctx->enckeylen = enckeylen; - - ret = aead_set_sh_desc(aead); - if (ret) { - dma_unmap_single(jrdev, ctx->key_dma, ctx->split_key_pad_len + -- keys.enckeylen, DMA_TO_DEVICE); -+ enckeylen, DMA_TO_DEVICE); - } - - return ret; -@@ -1715,154 +548,20 @@ - return -EINVAL; - } - --static int gcm_setkey(struct crypto_aead *aead, -- const u8 *key, unsigned int keylen) --{ -- struct caam_ctx *ctx = crypto_aead_ctx(aead); -- struct device *jrdev = ctx->jrdev; -- int ret = 0; -- --#ifdef DEBUG -- print_hex_dump(KERN_ERR, "key in @"__stringify(__LINE__)": ", -- DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1); --#endif -- -- memcpy(ctx->key, key, keylen); -- ctx->key_dma = dma_map_single(jrdev, ctx->key, keylen, -- DMA_TO_DEVICE); -- if (dma_mapping_error(jrdev, ctx->key_dma)) { -- dev_err(jrdev, "unable to map key i/o memory\n"); -- return -ENOMEM; -- } -- ctx->enckeylen = keylen; -- -- ret = gcm_set_sh_desc(aead); -- if (ret) { -- dma_unmap_single(jrdev, ctx->key_dma, ctx->enckeylen, -- DMA_TO_DEVICE); -- } -- -- return ret; --} -- --static int rfc4106_setkey(struct crypto_aead *aead, -- const u8 *key, unsigned int keylen) --{ -- struct caam_ctx *ctx = crypto_aead_ctx(aead); -- struct device *jrdev = ctx->jrdev; -- int ret = 0; -- -- if (keylen < 4) -- return -EINVAL; -- --#ifdef DEBUG -- print_hex_dump(KERN_ERR, "key in @"__stringify(__LINE__)": ", -- DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1); --#endif -- -- memcpy(ctx->key, key, keylen); -- -- /* -- * The last four bytes of the key material are used as the salt value -- * in the nonce. Update the AES key length. -- */ -- ctx->enckeylen = keylen - 4; -- -- ctx->key_dma = dma_map_single(jrdev, ctx->key, ctx->enckeylen, -- DMA_TO_DEVICE); -- if (dma_mapping_error(jrdev, ctx->key_dma)) { -- dev_err(jrdev, "unable to map key i/o memory\n"); -- return -ENOMEM; -- } -- -- ret = rfc4106_set_sh_desc(aead); -- if (ret) { -- dma_unmap_single(jrdev, ctx->key_dma, ctx->enckeylen, -- DMA_TO_DEVICE); -- } -- -- return ret; --} -- --static int rfc4543_setkey(struct crypto_aead *aead, -- const u8 *key, unsigned int keylen) --{ -- struct caam_ctx *ctx = crypto_aead_ctx(aead); -- struct device *jrdev = ctx->jrdev; -- int ret = 0; -- -- if (keylen < 4) -- return -EINVAL; -- --#ifdef DEBUG -- print_hex_dump(KERN_ERR, "key in @"__stringify(__LINE__)": ", -- DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1); --#endif -- -- memcpy(ctx->key, key, keylen); -- -- /* -- * The last four bytes of the key material are used as the salt value -- * in the nonce. Update the AES key length. -- */ -- ctx->enckeylen = keylen - 4; -- -- ctx->key_dma = dma_map_single(jrdev, ctx->key, ctx->enckeylen, -- DMA_TO_DEVICE); -- if (dma_mapping_error(jrdev, ctx->key_dma)) { -- dev_err(jrdev, "unable to map key i/o memory\n"); -- return -ENOMEM; -- } -- -- ret = rfc4543_set_sh_desc(aead); -- if (ret) { -- dma_unmap_single(jrdev, ctx->key_dma, ctx->enckeylen, -- DMA_TO_DEVICE); -- } -- -- return ret; --} -- - static int ablkcipher_setkey(struct crypto_ablkcipher *ablkcipher, - const u8 *key, unsigned int keylen) - { - struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher); -- struct ablkcipher_tfm *crt = &ablkcipher->base.crt_ablkcipher; -- struct crypto_tfm *tfm = crypto_ablkcipher_tfm(ablkcipher); -- const char *alg_name = crypto_tfm_alg_name(tfm); -+ struct ablkcipher_tfm *tfm = &ablkcipher->base.crt_ablkcipher; - struct device *jrdev = ctx->jrdev; - int ret = 0; -- u32 *key_jump_cmd; -+ u32 *key_jump_cmd, *jump_cmd; - u32 *desc; -- u32 *nonce; -- u32 geniv; -- u32 ctx1_iv_off = 0; -- const bool ctr_mode = ((ctx->class1_alg_type & OP_ALG_AAI_MASK) == -- OP_ALG_AAI_CTR_MOD128); -- const bool is_rfc3686 = (ctr_mode && -- (strstr(alg_name, "rfc3686") != NULL)); - - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "key in @"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "key in @"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1); - #endif -- /* -- * AES-CTR needs to load IV in CONTEXT1 reg -- * at an offset of 128bits (16bytes) -- * CONTEXT1[255:128] = IV -- */ -- if (ctr_mode) -- ctx1_iv_off = 16; -- -- /* -- * RFC3686 specific: -- * | CONTEXT1[255:128] = {NONCE, IV, COUNTER} -- * | *key = {KEY, NONCE} -- */ -- if (is_rfc3686) { -- ctx1_iv_off = 16 + CTR_RFC3686_NONCE_SIZE; -- keylen -= CTR_RFC3686_NONCE_SIZE; -- } - - memcpy(ctx->key, key, keylen); - ctx->key_dma = dma_map_single(jrdev, ctx->key, keylen, -@@ -1872,10 +571,11 @@ - return -ENOMEM; - } - ctx->enckeylen = keylen; -+ dma_sync_single_for_device(jrdev, ctx->key_dma, keylen, DMA_TO_DEVICE); - - /* ablkcipher_encrypt shared descriptor */ - desc = ctx->sh_desc_enc; -- init_sh_desc(desc, HDR_SHARE_SERIAL | HDR_SAVECTX); -+ init_sh_desc(desc, HDR_SHARE_SERIAL); - /* Skip if already shared */ - key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | - JUMP_COND_SHRD); -@@ -1885,32 +585,20 @@ - ctx->enckeylen, CLASS_1 | - KEY_DEST_CLASS_REG); - -- /* Load nonce into CONTEXT1 reg */ -- if (is_rfc3686) { -- nonce = (u32 *)(key + keylen); -- append_load_imm_u32(desc, *nonce, LDST_CLASS_IND_CCB | -- LDST_SRCDST_BYTE_OUTFIFO | LDST_IMM); -- append_move(desc, MOVE_WAITCOMP | -- MOVE_SRC_OUTFIFO | -- MOVE_DEST_CLASS1CTX | -- (16 << MOVE_OFFSET_SHIFT) | -- (CTR_RFC3686_NONCE_SIZE << MOVE_LEN_SHIFT)); -- } -- - set_jump_tgt_here(desc, key_jump_cmd); - -- /* Load iv */ -- append_seq_load(desc, crt->ivsize, LDST_SRCDST_BYTE_CONTEXT | -- LDST_CLASS_1_CCB | (ctx1_iv_off << LDST_OFFSET_SHIFT)); -- -- /* Load counter into CONTEXT1 reg */ -- if (is_rfc3686) -- append_load_imm_u32(desc, be32_to_cpu(1), LDST_IMM | -- LDST_CLASS_1_CCB | -- LDST_SRCDST_BYTE_CONTEXT | -- ((ctx1_iv_off + CTR_RFC3686_IV_SIZE) << -- LDST_OFFSET_SHIFT)); -+ /* Propagate errors from shared to job descriptor */ -+ append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD); - -+ /* load IV */ -+ if (strncmp(ablkcipher->base.__crt_alg->cra_name, "ctr(aes)", 8) == 0) { -+ append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT | -+ LDST_CLASS_1_CCB | tfm->ivsize | -+ (16 << LDST_OFFSET_SHIFT)); -+ } else { -+ append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT | -+ LDST_CLASS_1_CCB | tfm->ivsize); -+ } - /* Load operation */ - append_operation(desc, ctx->class1_alg_type | - OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT); -@@ -1926,15 +614,17 @@ - return -ENOMEM; - } - #ifdef DEBUG -- print_hex_dump(KERN_ERR, -- "ablkcipher enc shdesc@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "ablkcipher enc shdesc@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, desc, - desc_bytes(desc), 1); - #endif -+ dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma, -+ desc_bytes(desc), DMA_TO_DEVICE); -+ - /* ablkcipher_decrypt shared descriptor */ - desc = ctx->sh_desc_dec; - -- init_sh_desc(desc, HDR_SHARE_SERIAL | HDR_SAVECTX); -+ init_sh_desc(desc, HDR_SHARE_SERIAL); - /* Skip if already shared */ - key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | - JUMP_COND_SHRD); -@@ -1944,133 +634,49 @@ - ctx->enckeylen, CLASS_1 | - KEY_DEST_CLASS_REG); - -- /* Load nonce into CONTEXT1 reg */ -- if (is_rfc3686) { -- nonce = (u32 *)(key + keylen); -- append_load_imm_u32(desc, *nonce, LDST_CLASS_IND_CCB | -- LDST_SRCDST_BYTE_OUTFIFO | LDST_IMM); -- append_move(desc, MOVE_WAITCOMP | -- MOVE_SRC_OUTFIFO | -- MOVE_DEST_CLASS1CTX | -- (16 << MOVE_OFFSET_SHIFT) | -- (CTR_RFC3686_NONCE_SIZE << MOVE_LEN_SHIFT)); -- } -- -+ /* For aead, only propagate error immediately if shared */ -+ jump_cmd = append_jump(desc, JUMP_TEST_ALL); - set_jump_tgt_here(desc, key_jump_cmd); -+ append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD); -+ set_jump_tgt_here(desc, jump_cmd); - - /* load IV */ -- append_seq_load(desc, crt->ivsize, LDST_SRCDST_BYTE_CONTEXT | -- LDST_CLASS_1_CCB | (ctx1_iv_off << LDST_OFFSET_SHIFT)); -- -- /* Load counter into CONTEXT1 reg */ -- if (is_rfc3686) -- append_load_imm_u32(desc, be32_to_cpu(1), LDST_IMM | -- LDST_CLASS_1_CCB | -- LDST_SRCDST_BYTE_CONTEXT | -- ((ctx1_iv_off + CTR_RFC3686_IV_SIZE) << -- LDST_OFFSET_SHIFT)); -+ if (strncmp(ablkcipher->base.__crt_alg->cra_name, "ctr(aes)", 8) == 0) { -+ append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT | -+ LDST_CLASS_1_CCB | tfm->ivsize | -+ (16 << LDST_OFFSET_SHIFT)); - -- /* Choose operation */ -- if (ctr_mode) - append_operation(desc, ctx->class1_alg_type | -- OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT); -- else -+ OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT); -+ } else { -+ append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT | -+ LDST_CLASS_1_CCB | tfm->ivsize); -+ -+ /* Choose operation */ - append_dec_op1(desc, ctx->class1_alg_type); -+ } - - /* Perform operation */ - ablkcipher_append_src_dst(desc); - -+ /* Wait for key to load before allowing propagating error */ -+ append_dec_shr_done(desc); -+ - ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc, - desc_bytes(desc), - DMA_TO_DEVICE); -- if (dma_mapping_error(jrdev, ctx->sh_desc_dec_dma)) { -+ if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) { - dev_err(jrdev, "unable to map shared descriptor\n"); - return -ENOMEM; - } - - #ifdef DEBUG -- print_hex_dump(KERN_ERR, -- "ablkcipher dec shdesc@"__stringify(__LINE__)": ", -- DUMP_PREFIX_ADDRESS, 16, 4, desc, -- desc_bytes(desc), 1); --#endif -- /* ablkcipher_givencrypt shared descriptor */ -- desc = ctx->sh_desc_givenc; -- -- init_sh_desc(desc, HDR_SHARE_SERIAL | HDR_SAVECTX); -- /* Skip if already shared */ -- key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | -- JUMP_COND_SHRD); -- -- /* Load class1 key only */ -- append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen, -- ctx->enckeylen, CLASS_1 | -- KEY_DEST_CLASS_REG); -- -- /* Load Nonce into CONTEXT1 reg */ -- if (is_rfc3686) { -- nonce = (u32 *)(key + keylen); -- append_load_imm_u32(desc, *nonce, LDST_CLASS_IND_CCB | -- LDST_SRCDST_BYTE_OUTFIFO | LDST_IMM); -- append_move(desc, MOVE_WAITCOMP | -- MOVE_SRC_OUTFIFO | -- MOVE_DEST_CLASS1CTX | -- (16 << MOVE_OFFSET_SHIFT) | -- (CTR_RFC3686_NONCE_SIZE << MOVE_LEN_SHIFT)); -- } -- set_jump_tgt_here(desc, key_jump_cmd); -- -- /* Generate IV */ -- geniv = NFIFOENTRY_STYPE_PAD | NFIFOENTRY_DEST_DECO | -- NFIFOENTRY_DTYPE_MSG | NFIFOENTRY_LC1 | -- NFIFOENTRY_PTYPE_RND | (crt->ivsize << NFIFOENTRY_DLEN_SHIFT); -- append_load_imm_u32(desc, geniv, LDST_CLASS_IND_CCB | -- LDST_SRCDST_WORD_INFO_FIFO | LDST_IMM); -- append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO); -- append_move(desc, MOVE_WAITCOMP | -- MOVE_SRC_INFIFO | -- MOVE_DEST_CLASS1CTX | -- (crt->ivsize << MOVE_LEN_SHIFT) | -- (ctx1_iv_off << MOVE_OFFSET_SHIFT)); -- append_cmd(desc, CMD_LOAD | ENABLE_AUTO_INFO_FIFO); -- -- /* Copy generated IV to memory */ -- append_seq_store(desc, crt->ivsize, -- LDST_SRCDST_BYTE_CONTEXT | LDST_CLASS_1_CCB | -- (ctx1_iv_off << LDST_OFFSET_SHIFT)); -- -- /* Load Counter into CONTEXT1 reg */ -- if (is_rfc3686) -- append_load_imm_u32(desc, (u32)1, LDST_IMM | -- LDST_CLASS_1_CCB | -- LDST_SRCDST_BYTE_CONTEXT | -- ((ctx1_iv_off + CTR_RFC3686_IV_SIZE) << -- LDST_OFFSET_SHIFT)); -- -- if (ctx1_iv_off) -- append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | JUMP_COND_NCP | -- (1 << JUMP_OFFSET_SHIFT)); -- -- /* Load operation */ -- append_operation(desc, ctx->class1_alg_type | -- OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT); -- -- /* Perform operation */ -- ablkcipher_append_src_dst(desc); -- -- ctx->sh_desc_givenc_dma = dma_map_single(jrdev, desc, -- desc_bytes(desc), -- DMA_TO_DEVICE); -- if (dma_mapping_error(jrdev, ctx->sh_desc_givenc_dma)) { -- dev_err(jrdev, "unable to map shared descriptor\n"); -- return -ENOMEM; -- } --#ifdef DEBUG -- print_hex_dump(KERN_ERR, -- "ablkcipher givenc shdesc@" __stringify(__LINE__) ": ", -+ print_hex_dump(KERN_ERR, "ablkcipher dec shdesc@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, desc, - desc_bytes(desc), 1); - #endif -+ dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma, -+ desc_bytes(desc), DMA_TO_DEVICE); - - return ret; - } -@@ -2195,19 +801,22 @@ - edesc = (struct aead_edesc *)((char *)desc - - offsetof(struct aead_edesc, hw_desc)); - -- if (err) -- caam_jr_strstatus(jrdev, err); -+ if (err) { -+ char tmp[CAAM_ERROR_STR_MAX]; -+ -+ dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err)); -+ } - - aead_unmap(jrdev, edesc, req); - - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "assoc @"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "assoc @"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->assoc), - req->assoclen , 1); -- print_hex_dump(KERN_ERR, "dstiv @"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "dstiv @"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src) - ivsize, - edesc->src_nents ? 100 : ivsize, 1); -- print_hex_dump(KERN_ERR, "dst @"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "dst @"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src), - edesc->src_nents ? 100 : req->cryptlen + - ctx->authsize + 4, 1); -@@ -2235,16 +844,19 @@ - offsetof(struct aead_edesc, hw_desc)); - - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "dstiv @"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "dstiv @"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, req->iv, - ivsize, 1); -- print_hex_dump(KERN_ERR, "dst @"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "dst @"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->dst), -- req->cryptlen - ctx->authsize, 1); -+ req->cryptlen, 1); - #endif - -- if (err) -- caam_jr_strstatus(jrdev, err); -+ if (err) { -+ char tmp[CAAM_ERROR_STR_MAX]; -+ -+ dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err)); -+ } - - aead_unmap(jrdev, edesc, req); - -@@ -2255,7 +867,7 @@ - err = -EBADMSG; - - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "iphdrout@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "iphdrout@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, - ((char *)sg_virt(req->assoc) - sizeof(struct iphdr)), - sizeof(struct iphdr) + req->assoclen + -@@ -2263,7 +875,7 @@ - ctx->authsize + 36, 1); - if (!err && edesc->sec4_sg_bytes) { - struct scatterlist *sg = sg_last(req->src, edesc->src_nents); -- print_hex_dump(KERN_ERR, "sglastout@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "sglastout@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(sg), - sg->length + ctx->authsize + 16, 1); - } -@@ -2289,14 +901,17 @@ - edesc = (struct ablkcipher_edesc *)((char *)desc - - offsetof(struct ablkcipher_edesc, hw_desc)); - -- if (err) -- caam_jr_strstatus(jrdev, err); -+ if (err) { -+ char tmp[CAAM_ERROR_STR_MAX]; -+ -+ dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err)); -+ } - - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "dstiv @"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "dstiv @"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, req->info, - edesc->src_nents > 1 ? 100 : ivsize, 1); -- print_hex_dump(KERN_ERR, "dst @"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "dst @"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src), - edesc->dst_nents > 1 ? 100 : req->nbytes, 1); - #endif -@@ -2321,14 +936,17 @@ - - edesc = (struct ablkcipher_edesc *)((char *)desc - - offsetof(struct ablkcipher_edesc, hw_desc)); -- if (err) -- caam_jr_strstatus(jrdev, err); -+ if (err) { -+ char tmp[CAAM_ERROR_STR_MAX]; -+ -+ dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err)); -+ } - - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "dstiv @"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "dstiv @"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, req->info, - ivsize, 1); -- print_hex_dump(KERN_ERR, "dst @"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "dst @"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src), - edesc->dst_nents > 1 ? 100 : req->nbytes, 1); - #endif -@@ -2355,38 +973,29 @@ - u32 out_options = 0, in_options; - dma_addr_t dst_dma, src_dma; - int len, sec4_sg_index = 0; -- bool is_gcm = false; - - #ifdef DEBUG - debug("assoclen %d cryptlen %d authsize %d\n", - req->assoclen, req->cryptlen, authsize); -- print_hex_dump(KERN_ERR, "assoc @"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "assoc @"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->assoc), - req->assoclen , 1); -- print_hex_dump(KERN_ERR, "presciv@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "presciv@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, req->iv, - edesc->src_nents ? 100 : ivsize, 1); -- print_hex_dump(KERN_ERR, "src @"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "src @"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src), - edesc->src_nents ? 100 : req->cryptlen, 1); -- print_hex_dump(KERN_ERR, "shrdesc@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "shrdesc@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, sh_desc, - desc_bytes(sh_desc), 1); - #endif - -- if (((ctx->class1_alg_type & OP_ALG_ALGSEL_MASK) == -- OP_ALG_ALGSEL_AES) && -- ((ctx->class1_alg_type & OP_ALG_AAI_MASK) == OP_ALG_AAI_GCM)) -- is_gcm = true; -- - len = desc_len(sh_desc); - init_job_desc_shared(desc, ptr, len, HDR_SHARE_DEFER | HDR_REVERSE); - - if (all_contig) { -- if (is_gcm) -- src_dma = edesc->iv_dma; -- else -- src_dma = sg_dma_address(req->assoc); -+ src_dma = sg_dma_address(req->assoc); - in_options = 0; - } else { - src_dma = edesc->sec4_sg_dma; -@@ -2394,9 +1003,12 @@ - (edesc->src_nents ? : 1); - in_options = LDST_SGF; - } -- -- append_seq_in_ptr(desc, src_dma, req->assoclen + ivsize + req->cryptlen, -- in_options); -+ if (encrypt) -+ append_seq_in_ptr(desc, src_dma, req->assoclen + ivsize + -+ req->cryptlen - authsize, in_options); -+ else -+ append_seq_in_ptr(desc, src_dma, req->assoclen + ivsize + -+ req->cryptlen, in_options); - - if (likely(req->src == req->dst)) { - if (all_contig) { -@@ -2417,8 +1029,7 @@ - } - } - if (encrypt) -- append_seq_out_ptr(desc, dst_dma, req->cryptlen + authsize, -- out_options); -+ append_seq_out_ptr(desc, dst_dma, req->cryptlen, out_options); - else - append_seq_out_ptr(desc, dst_dma, req->cryptlen - authsize, - out_options); -@@ -2440,53 +1051,43 @@ - u32 out_options = 0, in_options; - dma_addr_t dst_dma, src_dma; - int len, sec4_sg_index = 0; -- bool is_gcm = false; - - #ifdef DEBUG - debug("assoclen %d cryptlen %d authsize %d\n", - req->assoclen, req->cryptlen, authsize); -- print_hex_dump(KERN_ERR, "assoc @"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "assoc @"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->assoc), - req->assoclen , 1); -- print_hex_dump(KERN_ERR, "presciv@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "presciv@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, req->iv, ivsize, 1); -- print_hex_dump(KERN_ERR, "src @"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "src @"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src), - edesc->src_nents > 1 ? 100 : req->cryptlen, 1); -- print_hex_dump(KERN_ERR, "shrdesc@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "shrdesc@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, sh_desc, - desc_bytes(sh_desc), 1); - #endif - -- if (((ctx->class1_alg_type & OP_ALG_ALGSEL_MASK) == -- OP_ALG_ALGSEL_AES) && -- ((ctx->class1_alg_type & OP_ALG_AAI_MASK) == OP_ALG_AAI_GCM)) -- is_gcm = true; -- - len = desc_len(sh_desc); - init_job_desc_shared(desc, ptr, len, HDR_SHARE_DEFER | HDR_REVERSE); - - if (contig & GIV_SRC_CONTIG) { -- if (is_gcm) -- src_dma = edesc->iv_dma; -- else -- src_dma = sg_dma_address(req->assoc); -+ src_dma = sg_dma_address(req->assoc); - in_options = 0; - } else { - src_dma = edesc->sec4_sg_dma; - sec4_sg_index += edesc->assoc_nents + 1 + edesc->src_nents; - in_options = LDST_SGF; - } -- append_seq_in_ptr(desc, src_dma, req->assoclen + ivsize + req->cryptlen, -- in_options); -+ append_seq_in_ptr(desc, src_dma, req->assoclen + ivsize + -+ req->cryptlen - authsize, in_options); - - if (contig & GIV_DST_CONTIG) { - dst_dma = edesc->iv_dma; - } else { - if (likely(req->src == req->dst)) { - dst_dma = src_dma + sizeof(struct sec4_sg_entry) * -- (edesc->assoc_nents + -- (is_gcm ? 1 + edesc->src_nents : 0)); -+ edesc->assoc_nents; - out_options = LDST_SGF; - } else { - dst_dma = edesc->sec4_sg_dma + -@@ -2496,8 +1097,7 @@ - } - } - -- append_seq_out_ptr(desc, dst_dma, ivsize + req->cryptlen + authsize, -- out_options); -+ append_seq_out_ptr(desc, dst_dma, ivsize + req->cryptlen, out_options); - } - - /* -@@ -2516,10 +1116,10 @@ - int len, sec4_sg_index = 0; - - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "presciv@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "presciv@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, req->info, - ivsize, 1); -- print_hex_dump(KERN_ERR, "src @"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "src @"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src), - edesc->src_nents ? 100 : req->nbytes, 1); - #endif -@@ -2532,7 +1132,7 @@ - in_options = 0; - } else { - src_dma = edesc->sec4_sg_dma; -- sec4_sg_index += edesc->src_nents + 1; -+ sec4_sg_index += (iv_contig ? 0 : 1) + edesc->src_nents; - in_options = LDST_SGF; - } - append_seq_in_ptr(desc, src_dma, req->nbytes + ivsize, in_options); -@@ -2558,59 +1158,10 @@ - } - - /* -- * Fill in ablkcipher givencrypt job descriptor -- */ --static void init_ablkcipher_giv_job(u32 *sh_desc, dma_addr_t ptr, -- struct ablkcipher_edesc *edesc, -- struct ablkcipher_request *req, -- bool iv_contig) --{ -- struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req); -- int ivsize = crypto_ablkcipher_ivsize(ablkcipher); -- u32 *desc = edesc->hw_desc; -- u32 out_options, in_options; -- dma_addr_t dst_dma, src_dma; -- int len, sec4_sg_index = 0; -- --#ifdef DEBUG -- print_hex_dump(KERN_ERR, "presciv@" __stringify(__LINE__) ": ", -- DUMP_PREFIX_ADDRESS, 16, 4, req->info, -- ivsize, 1); -- print_hex_dump(KERN_ERR, "src @" __stringify(__LINE__) ": ", -- DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src), -- edesc->src_nents ? 100 : req->nbytes, 1); --#endif -- -- len = desc_len(sh_desc); -- init_job_desc_shared(desc, ptr, len, HDR_SHARE_DEFER | HDR_REVERSE); -- -- if (!edesc->src_nents) { -- src_dma = sg_dma_address(req->src); -- in_options = 0; -- } else { -- src_dma = edesc->sec4_sg_dma; -- sec4_sg_index += edesc->src_nents; -- in_options = LDST_SGF; -- } -- append_seq_in_ptr(desc, src_dma, req->nbytes, in_options); -- -- if (iv_contig) { -- dst_dma = edesc->iv_dma; -- out_options = 0; -- } else { -- dst_dma = edesc->sec4_sg_dma + -- sec4_sg_index * sizeof(struct sec4_sg_entry); -- out_options = LDST_SGF; -- } -- append_seq_out_ptr(desc, dst_dma, req->nbytes + ivsize, out_options); --} -- --/* - * allocate and map the aead extended descriptor - */ - static struct aead_edesc *aead_edesc_alloc(struct aead_request *req, -- int desc_bytes, bool *all_contig_ptr, -- bool encrypt) -+ int desc_bytes, bool *all_contig_ptr) - { - struct crypto_aead *aead = crypto_aead_reqtfm(req); - struct caam_ctx *ctx = crypto_aead_ctx(aead); -@@ -2625,26 +1176,15 @@ - bool assoc_chained = false, src_chained = false, dst_chained = false; - int ivsize = crypto_aead_ivsize(aead); - int sec4_sg_index, sec4_sg_len = 0, sec4_sg_bytes; -- unsigned int authsize = ctx->authsize; -- bool is_gcm = false; - - assoc_nents = sg_count(req->assoc, req->assoclen, &assoc_chained); -+ src_nents = sg_count(req->src, req->cryptlen, &src_chained); - -- if (unlikely(req->dst != req->src)) { -- src_nents = sg_count(req->src, req->cryptlen, &src_chained); -- dst_nents = sg_count(req->dst, -- req->cryptlen + -- (encrypt ? authsize : (-authsize)), -- &dst_chained); -- } else { -- src_nents = sg_count(req->src, -- req->cryptlen + -- (encrypt ? authsize : 0), -- &src_chained); -- } -+ if (unlikely(req->dst != req->src)) -+ dst_nents = sg_count(req->dst, req->cryptlen, &dst_chained); - - sgc = dma_map_sg_chained(jrdev, req->assoc, assoc_nents ? : 1, -- DMA_TO_DEVICE, assoc_chained); -+ DMA_BIDIRECTIONAL, assoc_chained); - if (likely(req->src == req->dst)) { - sgc = dma_map_sg_chained(jrdev, req->src, src_nents ? : 1, - DMA_BIDIRECTIONAL, src_chained); -@@ -2655,43 +1195,23 @@ - DMA_FROM_DEVICE, dst_chained); - } - -+ /* Check if data are contiguous */ - iv_dma = dma_map_single(jrdev, req->iv, ivsize, DMA_TO_DEVICE); -- if (dma_mapping_error(jrdev, iv_dma)) { -- dev_err(jrdev, "unable to map IV\n"); -- return ERR_PTR(-ENOMEM); -- } -- -- if (((ctx->class1_alg_type & OP_ALG_ALGSEL_MASK) == -- OP_ALG_ALGSEL_AES) && -- ((ctx->class1_alg_type & OP_ALG_AAI_MASK) == OP_ALG_AAI_GCM)) -- is_gcm = true; -- -- /* -- * Check if data are contiguous. -- * GCM expected input sequence: IV, AAD, text -- * All other - expected input sequence: AAD, IV, text -- */ -- if (is_gcm) -- all_contig = (!assoc_nents && -- iv_dma + ivsize == sg_dma_address(req->assoc) && -- !src_nents && sg_dma_address(req->assoc) + -- req->assoclen == sg_dma_address(req->src)); -- else -- all_contig = (!assoc_nents && sg_dma_address(req->assoc) + -- req->assoclen == iv_dma && !src_nents && -- iv_dma + ivsize == sg_dma_address(req->src)); -- if (!all_contig) { -+ if (assoc_nents || sg_dma_address(req->assoc) + req->assoclen != -+ iv_dma || src_nents || iv_dma + ivsize != -+ sg_dma_address(req->src)) { -+ all_contig = false; - assoc_nents = assoc_nents ? : 1; - src_nents = src_nents ? : 1; - sec4_sg_len = assoc_nents + 1 + src_nents; - } -- - sec4_sg_len += dst_nents; - - sec4_sg_bytes = sec4_sg_len * sizeof(struct sec4_sg_entry); -+ dma_sync_single_for_device(jrdev, iv_dma, ivsize, DMA_TO_DEVICE); - - /* allocate space for base edesc and hw desc commands, link tables */ -- edesc = kmalloc(sizeof(struct aead_edesc) + desc_bytes + -+ edesc = kzalloc(sizeof(struct aead_edesc) + desc_bytes + - sec4_sg_bytes, GFP_DMA | flags); - if (!edesc) { - dev_err(jrdev, "could not allocate extended descriptor\n"); -@@ -2708,46 +1228,32 @@ - edesc->sec4_sg_bytes = sec4_sg_bytes; - edesc->sec4_sg = (void *)edesc + sizeof(struct aead_edesc) + - desc_bytes; -+ edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg, -+ sec4_sg_bytes, DMA_TO_DEVICE); - *all_contig_ptr = all_contig; - - sec4_sg_index = 0; - if (!all_contig) { -- if (!is_gcm) { -- sg_to_sec4_sg(req->assoc, -- assoc_nents, -- edesc->sec4_sg + -- sec4_sg_index, 0); -- sec4_sg_index += assoc_nents; -- } -- -+ sg_to_sec4_sg(req->assoc, -+ (assoc_nents ? : 1), -+ edesc->sec4_sg + -+ sec4_sg_index, 0); -+ sec4_sg_index += assoc_nents ? : 1; - dma_to_sec4_sg_one(edesc->sec4_sg + sec4_sg_index, - iv_dma, ivsize, 0); - sec4_sg_index += 1; -- -- if (is_gcm) { -- sg_to_sec4_sg(req->assoc, -- assoc_nents, -- edesc->sec4_sg + -- sec4_sg_index, 0); -- sec4_sg_index += assoc_nents; -- } -- - sg_to_sec4_sg_last(req->src, -- src_nents, -+ (src_nents ? : 1), - edesc->sec4_sg + - sec4_sg_index, 0); -- sec4_sg_index += src_nents; -+ sec4_sg_index += src_nents ? : 1; - } - if (dst_nents) { - sg_to_sec4_sg_last(req->dst, dst_nents, - edesc->sec4_sg + sec4_sg_index, 0); - } -- edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg, -- sec4_sg_bytes, DMA_TO_DEVICE); -- if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) { -- dev_err(jrdev, "unable to map S/G table\n"); -- return ERR_PTR(-ENOMEM); -- } -+ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma, sec4_sg_bytes, -+ DMA_TO_DEVICE); - - return edesc; - } -@@ -2762,9 +1268,11 @@ - u32 *desc; - int ret = 0; - -+ req->cryptlen += ctx->authsize; -+ - /* allocate extended descriptor */ - edesc = aead_edesc_alloc(req, DESC_JOB_IO_LEN * -- CAAM_CMD_SZ, &all_contig, true); -+ CAAM_CMD_SZ, &all_contig); - if (IS_ERR(edesc)) - return PTR_ERR(edesc); - -@@ -2772,7 +1280,7 @@ - init_aead_job(ctx->sh_desc_enc, ctx->sh_desc_enc_dma, edesc, req, - all_contig, true); - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "aead jobdesc@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "aead jobdesc@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc, - desc_bytes(edesc->hw_desc), 1); - #endif -@@ -2801,12 +1309,12 @@ - - /* allocate extended descriptor */ - edesc = aead_edesc_alloc(req, DESC_JOB_IO_LEN * -- CAAM_CMD_SZ, &all_contig, false); -+ CAAM_CMD_SZ, &all_contig); - if (IS_ERR(edesc)) - return PTR_ERR(edesc); - - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "dec src@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "dec src@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src), - req->cryptlen, 1); - #endif -@@ -2815,7 +1323,7 @@ - init_aead_job(ctx->sh_desc_dec, - ctx->sh_desc_dec_dma, edesc, req, all_contig, false); - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "aead jobdesc@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "aead jobdesc@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc, - desc_bytes(edesc->hw_desc), 1); - #endif -@@ -2853,17 +1361,15 @@ - int ivsize = crypto_aead_ivsize(aead); - bool assoc_chained = false, src_chained = false, dst_chained = false; - int sec4_sg_index, sec4_sg_len = 0, sec4_sg_bytes; -- bool is_gcm = false; - - assoc_nents = sg_count(req->assoc, req->assoclen, &assoc_chained); - src_nents = sg_count(req->src, req->cryptlen, &src_chained); - - if (unlikely(req->dst != req->src)) -- dst_nents = sg_count(req->dst, req->cryptlen + ctx->authsize, -- &dst_chained); -+ dst_nents = sg_count(req->dst, req->cryptlen, &dst_chained); - - sgc = dma_map_sg_chained(jrdev, req->assoc, assoc_nents ? : 1, -- DMA_TO_DEVICE, assoc_chained); -+ DMA_BIDIRECTIONAL, assoc_chained); - if (likely(req->src == req->dst)) { - sgc = dma_map_sg_chained(jrdev, req->src, src_nents ? : 1, - DMA_BIDIRECTIONAL, src_chained); -@@ -2874,64 +1380,32 @@ - DMA_FROM_DEVICE, dst_chained); - } - -+ /* Check if data are contiguous */ - iv_dma = dma_map_single(jrdev, greq->giv, ivsize, DMA_TO_DEVICE); -- if (dma_mapping_error(jrdev, iv_dma)) { -- dev_err(jrdev, "unable to map IV\n"); -- return ERR_PTR(-ENOMEM); -- } -- -- if (((ctx->class1_alg_type & OP_ALG_ALGSEL_MASK) == -- OP_ALG_ALGSEL_AES) && -- ((ctx->class1_alg_type & OP_ALG_AAI_MASK) == OP_ALG_AAI_GCM)) -- is_gcm = true; -- -- /* -- * Check if data are contiguous. -- * GCM expected input sequence: IV, AAD, text -- * All other - expected input sequence: AAD, IV, text -- */ -- -- if (is_gcm) { -- if (assoc_nents || iv_dma + ivsize != -- sg_dma_address(req->assoc) || src_nents || -- sg_dma_address(req->assoc) + req->assoclen != -- sg_dma_address(req->src)) -- contig &= ~GIV_SRC_CONTIG; -- } else { -- if (assoc_nents || -- sg_dma_address(req->assoc) + req->assoclen != iv_dma || -- src_nents || iv_dma + ivsize != sg_dma_address(req->src)) -- contig &= ~GIV_SRC_CONTIG; -- } -- -+ if (assoc_nents || sg_dma_address(req->assoc) + req->assoclen != -+ iv_dma || src_nents || iv_dma + ivsize != sg_dma_address(req->src)) -+ contig &= ~GIV_SRC_CONTIG; - if (dst_nents || iv_dma + ivsize != sg_dma_address(req->dst)) - contig &= ~GIV_DST_CONTIG; -- -+ if (unlikely(req->src != req->dst)) { -+ dst_nents = dst_nents ? : 1; -+ sec4_sg_len += 1; -+ } - if (!(contig & GIV_SRC_CONTIG)) { - assoc_nents = assoc_nents ? : 1; - src_nents = src_nents ? : 1; - sec4_sg_len += assoc_nents + 1 + src_nents; -- if (req->src == req->dst && -- (src_nents || iv_dma + ivsize != sg_dma_address(req->src))) -- contig &= ~GIV_DST_CONTIG; -- } -- -- /* -- * Add new sg entries for GCM output sequence. -- * Expected output sequence: IV, encrypted text. -- */ -- if (is_gcm && req->src == req->dst && !(contig & GIV_DST_CONTIG)) -- sec4_sg_len += 1 + src_nents; -- -- if (unlikely(req->src != req->dst)) { -- dst_nents = dst_nents ? : 1; -- sec4_sg_len += 1 + dst_nents; -+ if (likely(req->src == req->dst)) -+ contig &= ~GIV_DST_CONTIG; - } -+ sec4_sg_len += dst_nents; - - sec4_sg_bytes = sec4_sg_len * sizeof(struct sec4_sg_entry); - -+ dma_sync_single_for_device(jrdev, iv_dma, ivsize, DMA_TO_DEVICE); -+ - /* allocate space for base edesc and hw desc commands, link tables */ -- edesc = kmalloc(sizeof(struct aead_edesc) + desc_bytes + -+ edesc = kzalloc(sizeof(struct aead_edesc) + desc_bytes + - sec4_sg_bytes, GFP_DMA | flags); - if (!edesc) { - dev_err(jrdev, "could not allocate extended descriptor\n"); -@@ -2948,40 +1422,24 @@ - edesc->sec4_sg_bytes = sec4_sg_bytes; - edesc->sec4_sg = (void *)edesc + sizeof(struct aead_edesc) + - desc_bytes; -+ edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg, -+ sec4_sg_bytes, DMA_TO_DEVICE); - *contig_ptr = contig; - - sec4_sg_index = 0; - if (!(contig & GIV_SRC_CONTIG)) { -- if (!is_gcm) { -- sg_to_sec4_sg(req->assoc, assoc_nents, -- edesc->sec4_sg + sec4_sg_index, 0); -- sec4_sg_index += assoc_nents; -- } -- -+ sg_to_sec4_sg(req->assoc, assoc_nents, -+ edesc->sec4_sg + -+ sec4_sg_index, 0); -+ sec4_sg_index += assoc_nents; - dma_to_sec4_sg_one(edesc->sec4_sg + sec4_sg_index, - iv_dma, ivsize, 0); - sec4_sg_index += 1; -- -- if (is_gcm) { -- sg_to_sec4_sg(req->assoc, assoc_nents, -- edesc->sec4_sg + sec4_sg_index, 0); -- sec4_sg_index += assoc_nents; -- } -- - sg_to_sec4_sg_last(req->src, src_nents, - edesc->sec4_sg + - sec4_sg_index, 0); - sec4_sg_index += src_nents; - } -- -- if (is_gcm && req->src == req->dst && !(contig & GIV_DST_CONTIG)) { -- dma_to_sec4_sg_one(edesc->sec4_sg + sec4_sg_index, -- iv_dma, ivsize, 0); -- sec4_sg_index += 1; -- sg_to_sec4_sg_last(req->src, src_nents, -- edesc->sec4_sg + sec4_sg_index, 0); -- } -- - if (unlikely(req->src != req->dst && !(contig & GIV_DST_CONTIG))) { - dma_to_sec4_sg_one(edesc->sec4_sg + sec4_sg_index, - iv_dma, ivsize, 0); -@@ -2989,12 +1447,8 @@ - sg_to_sec4_sg_last(req->dst, dst_nents, - edesc->sec4_sg + sec4_sg_index, 0); - } -- edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg, -- sec4_sg_bytes, DMA_TO_DEVICE); -- if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) { -- dev_err(jrdev, "unable to map S/G table\n"); -- return ERR_PTR(-ENOMEM); -- } -+ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma, sec4_sg_bytes, -+ DMA_TO_DEVICE); - - return edesc; - } -@@ -3010,6 +1464,8 @@ - u32 *desc; - int ret = 0; - -+ req->cryptlen += ctx->authsize; -+ - /* allocate extended descriptor */ - edesc = aead_giv_edesc_alloc(areq, DESC_JOB_IO_LEN * - CAAM_CMD_SZ, &contig); -@@ -3018,7 +1474,7 @@ - return PTR_ERR(edesc); - - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "giv src@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "giv src@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src), - req->cryptlen, 1); - #endif -@@ -3027,7 +1483,7 @@ - init_aead_giv_job(ctx->sh_desc_givenc, - ctx->sh_desc_givenc_dma, edesc, req, contig); - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "aead jobdesc@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "aead jobdesc@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc, - desc_bytes(edesc->hw_desc), 1); - #endif -@@ -3044,11 +1500,6 @@ - return ret; - } - --static int aead_null_givencrypt(struct aead_givcrypt_request *areq) --{ -- return aead_encrypt(&areq->areq); --} -- - /* - * allocate and map the ablkcipher extended descriptor for ablkcipher - */ -@@ -3086,16 +1537,12 @@ - DMA_FROM_DEVICE, dst_chained); - } - -- iv_dma = dma_map_single(jrdev, req->info, ivsize, DMA_TO_DEVICE); -- if (dma_mapping_error(jrdev, iv_dma)) { -- dev_err(jrdev, "unable to map IV\n"); -- return ERR_PTR(-ENOMEM); -- } -- - /* - * Check if iv can be contiguous with source and destination. - * If so, include it. If not, create scatterlist. - */ -+ iv_dma = dma_map_single(jrdev, req->info, ivsize, DMA_TO_DEVICE); -+ dma_sync_single_for_device(jrdev, iv_dma, ivsize, DMA_TO_DEVICE); - if (!src_nents && iv_dma + ivsize == sg_dma_address(req->src)) - iv_contig = true; - else -@@ -3104,7 +1551,7 @@ - sizeof(struct sec4_sg_entry); - - /* allocate space for base edesc and hw desc commands, link tables */ -- edesc = kmalloc(sizeof(struct ablkcipher_edesc) + desc_bytes + -+ edesc = kzalloc(sizeof(struct ablkcipher_edesc) + desc_bytes + - sec4_sg_bytes, GFP_DMA | flags); - if (!edesc) { - dev_err(jrdev, "could not allocate extended descriptor\n"); -@@ -3134,15 +1581,13 @@ - - edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg, - sec4_sg_bytes, DMA_TO_DEVICE); -- if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) { -- dev_err(jrdev, "unable to map S/G table\n"); -- return ERR_PTR(-ENOMEM); -- } -- - edesc->iv_dma = iv_dma; - -+ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma, sec4_sg_bytes, -+ DMA_TO_DEVICE); -+ - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "ablkcipher sec4_sg@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "ablkcipher sec4_sg@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, edesc->sec4_sg, - sec4_sg_bytes, 1); - #endif -@@ -3171,7 +1616,7 @@ - init_ablkcipher_job(ctx->sh_desc_enc, - ctx->sh_desc_enc_dma, edesc, req, iv_contig); - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "ablkcipher jobdesc@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "ablkcipher jobdesc@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc, - desc_bytes(edesc->hw_desc), 1); - #endif -@@ -3209,7 +1654,7 @@ - ctx->sh_desc_dec_dma, edesc, req, iv_contig); - desc = edesc->hw_desc; - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "ablkcipher jobdesc@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "ablkcipher jobdesc@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc, - desc_bytes(edesc->hw_desc), 1); - #endif -@@ -3225,291 +1670,28 @@ - return ret; - } - --/* -- * allocate and map the ablkcipher extended descriptor -- * for ablkcipher givencrypt -- */ --static struct ablkcipher_edesc *ablkcipher_giv_edesc_alloc( -- struct skcipher_givcrypt_request *greq, -- int desc_bytes, -- bool *iv_contig_out) --{ -- struct ablkcipher_request *req = &greq->creq; -- struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req); -- struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher); -- struct device *jrdev = ctx->jrdev; -- gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG | -- CRYPTO_TFM_REQ_MAY_SLEEP)) ? -- GFP_KERNEL : GFP_ATOMIC; -- int src_nents, dst_nents = 0, sec4_sg_bytes; -- struct ablkcipher_edesc *edesc; -- dma_addr_t iv_dma = 0; -- bool iv_contig = false; -- int sgc; -- int ivsize = crypto_ablkcipher_ivsize(ablkcipher); -- bool src_chained = false, dst_chained = false; -- int sec4_sg_index; -- -- src_nents = sg_count(req->src, req->nbytes, &src_chained); -- -- if (unlikely(req->dst != req->src)) -- dst_nents = sg_count(req->dst, req->nbytes, &dst_chained); -- -- if (likely(req->src == req->dst)) { -- sgc = dma_map_sg_chained(jrdev, req->src, src_nents ? : 1, -- DMA_BIDIRECTIONAL, src_chained); -- } else { -- sgc = dma_map_sg_chained(jrdev, req->src, src_nents ? : 1, -- DMA_TO_DEVICE, src_chained); -- sgc = dma_map_sg_chained(jrdev, req->dst, dst_nents ? : 1, -- DMA_FROM_DEVICE, dst_chained); -- } -- -- /* -- * Check if iv can be contiguous with source and destination. -- * If so, include it. If not, create scatterlist. -- */ -- iv_dma = dma_map_single(jrdev, greq->giv, ivsize, DMA_TO_DEVICE); -- if (dma_mapping_error(jrdev, iv_dma)) { -- dev_err(jrdev, "unable to map IV\n"); -- return ERR_PTR(-ENOMEM); -- } -- -- if (!dst_nents && iv_dma + ivsize == sg_dma_address(req->dst)) -- iv_contig = true; -- else -- dst_nents = dst_nents ? : 1; -- sec4_sg_bytes = ((iv_contig ? 0 : 1) + src_nents + dst_nents) * -- sizeof(struct sec4_sg_entry); -- -- /* allocate space for base edesc and hw desc commands, link tables */ -- edesc = kmalloc(sizeof(*edesc) + desc_bytes + -- sec4_sg_bytes, GFP_DMA | flags); -- if (!edesc) { -- dev_err(jrdev, "could not allocate extended descriptor\n"); -- return ERR_PTR(-ENOMEM); -- } -- -- edesc->src_nents = src_nents; -- edesc->src_chained = src_chained; -- edesc->dst_nents = dst_nents; -- edesc->dst_chained = dst_chained; -- edesc->sec4_sg_bytes = sec4_sg_bytes; -- edesc->sec4_sg = (void *)edesc + sizeof(struct ablkcipher_edesc) + -- desc_bytes; -- -- sec4_sg_index = 0; -- if (src_nents) { -- sg_to_sec4_sg_last(req->src, src_nents, edesc->sec4_sg, 0); -- sec4_sg_index += src_nents; -- } -- -- if (!iv_contig) { -- dma_to_sec4_sg_one(edesc->sec4_sg + sec4_sg_index, -- iv_dma, ivsize, 0); -- sec4_sg_index += 1; -- sg_to_sec4_sg_last(req->dst, dst_nents, -- edesc->sec4_sg + sec4_sg_index, 0); -- } -- -- edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg, -- sec4_sg_bytes, DMA_TO_DEVICE); -- if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) { -- dev_err(jrdev, "unable to map S/G table\n"); -- return ERR_PTR(-ENOMEM); -- } -- edesc->iv_dma = iv_dma; -- --#ifdef DEBUG -- print_hex_dump(KERN_ERR, -- "ablkcipher sec4_sg@" __stringify(__LINE__) ": ", -- DUMP_PREFIX_ADDRESS, 16, 4, edesc->sec4_sg, -- sec4_sg_bytes, 1); --#endif -- -- *iv_contig_out = iv_contig; -- return edesc; --} -- --static int ablkcipher_givencrypt(struct skcipher_givcrypt_request *creq) --{ -- struct ablkcipher_request *req = &creq->creq; -- struct ablkcipher_edesc *edesc; -- struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req); -- struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher); -- struct device *jrdev = ctx->jrdev; -- bool iv_contig; -- u32 *desc; -- int ret = 0; -- -- /* allocate extended descriptor */ -- edesc = ablkcipher_giv_edesc_alloc(creq, DESC_JOB_IO_LEN * -- CAAM_CMD_SZ, &iv_contig); -- if (IS_ERR(edesc)) -- return PTR_ERR(edesc); -- -- /* Create and submit job descriptor*/ -- init_ablkcipher_giv_job(ctx->sh_desc_givenc, ctx->sh_desc_givenc_dma, -- edesc, req, iv_contig); --#ifdef DEBUG -- print_hex_dump(KERN_ERR, -- "ablkcipher jobdesc@" __stringify(__LINE__) ": ", -- DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc, -- desc_bytes(edesc->hw_desc), 1); --#endif -- desc = edesc->hw_desc; -- ret = caam_jr_enqueue(jrdev, desc, ablkcipher_encrypt_done, req); -- -- if (!ret) { -- ret = -EINPROGRESS; -- } else { -- ablkcipher_unmap(jrdev, edesc, req); -- kfree(edesc); -- } -- -- return ret; --} -- - #define template_aead template_u.aead - #define template_ablkcipher template_u.ablkcipher - struct caam_alg_template { - char name[CRYPTO_MAX_ALG_NAME]; -- char driver_name[CRYPTO_MAX_ALG_NAME]; -- unsigned int blocksize; -- u32 type; -- union { -- struct ablkcipher_alg ablkcipher; -- struct aead_alg aead; -- struct blkcipher_alg blkcipher; -- struct cipher_alg cipher; -- struct compress_alg compress; -- struct rng_alg rng; -- } template_u; -- u32 class1_alg_type; -- u32 class2_alg_type; -- u32 alg_op; --}; -- --static struct caam_alg_template driver_algs[] = { -- /* single-pass ipsec_esp descriptor */ -- { -- .name = "authenc(hmac(md5),ecb(cipher_null))", -- .driver_name = "authenc-hmac-md5-ecb-cipher_null-caam", -- .blocksize = NULL_BLOCK_SIZE, -- .type = CRYPTO_ALG_TYPE_AEAD, -- .template_aead = { -- .setkey = aead_setkey, -- .setauthsize = aead_setauthsize, -- .encrypt = aead_encrypt, -- .decrypt = aead_decrypt, -- .givencrypt = aead_null_givencrypt, -- .geniv = "", -- .ivsize = NULL_IV_SIZE, -- .maxauthsize = MD5_DIGEST_SIZE, -- }, -- .class1_alg_type = 0, -- .class2_alg_type = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC_PRECOMP, -- .alg_op = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC, -- }, -- { -- .name = "authenc(hmac(sha1),ecb(cipher_null))", -- .driver_name = "authenc-hmac-sha1-ecb-cipher_null-caam", -- .blocksize = NULL_BLOCK_SIZE, -- .type = CRYPTO_ALG_TYPE_AEAD, -- .template_aead = { -- .setkey = aead_setkey, -- .setauthsize = aead_setauthsize, -- .encrypt = aead_encrypt, -- .decrypt = aead_decrypt, -- .givencrypt = aead_null_givencrypt, -- .geniv = "", -- .ivsize = NULL_IV_SIZE, -- .maxauthsize = SHA1_DIGEST_SIZE, -- }, -- .class1_alg_type = 0, -- .class2_alg_type = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC_PRECOMP, -- .alg_op = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC, -- }, -- { -- .name = "authenc(hmac(sha224),ecb(cipher_null))", -- .driver_name = "authenc-hmac-sha224-ecb-cipher_null-caam", -- .blocksize = NULL_BLOCK_SIZE, -- .type = CRYPTO_ALG_TYPE_AEAD, -- .template_aead = { -- .setkey = aead_setkey, -- .setauthsize = aead_setauthsize, -- .encrypt = aead_encrypt, -- .decrypt = aead_decrypt, -- .givencrypt = aead_null_givencrypt, -- .geniv = "", -- .ivsize = NULL_IV_SIZE, -- .maxauthsize = SHA224_DIGEST_SIZE, -- }, -- .class1_alg_type = 0, -- .class2_alg_type = OP_ALG_ALGSEL_SHA224 | -- OP_ALG_AAI_HMAC_PRECOMP, -- .alg_op = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC, -- }, -- { -- .name = "authenc(hmac(sha256),ecb(cipher_null))", -- .driver_name = "authenc-hmac-sha256-ecb-cipher_null-caam", -- .blocksize = NULL_BLOCK_SIZE, -- .type = CRYPTO_ALG_TYPE_AEAD, -- .template_aead = { -- .setkey = aead_setkey, -- .setauthsize = aead_setauthsize, -- .encrypt = aead_encrypt, -- .decrypt = aead_decrypt, -- .givencrypt = aead_null_givencrypt, -- .geniv = "", -- .ivsize = NULL_IV_SIZE, -- .maxauthsize = SHA256_DIGEST_SIZE, -- }, -- .class1_alg_type = 0, -- .class2_alg_type = OP_ALG_ALGSEL_SHA256 | -- OP_ALG_AAI_HMAC_PRECOMP, -- .alg_op = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC, -- }, -- { -- .name = "authenc(hmac(sha384),ecb(cipher_null))", -- .driver_name = "authenc-hmac-sha384-ecb-cipher_null-caam", -- .blocksize = NULL_BLOCK_SIZE, -- .type = CRYPTO_ALG_TYPE_AEAD, -- .template_aead = { -- .setkey = aead_setkey, -- .setauthsize = aead_setauthsize, -- .encrypt = aead_encrypt, -- .decrypt = aead_decrypt, -- .givencrypt = aead_null_givencrypt, -- .geniv = "", -- .ivsize = NULL_IV_SIZE, -- .maxauthsize = SHA384_DIGEST_SIZE, -- }, -- .class1_alg_type = 0, -- .class2_alg_type = OP_ALG_ALGSEL_SHA384 | -- OP_ALG_AAI_HMAC_PRECOMP, -- .alg_op = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC, -- }, -- { -- .name = "authenc(hmac(sha512),ecb(cipher_null))", -- .driver_name = "authenc-hmac-sha512-ecb-cipher_null-caam", -- .blocksize = NULL_BLOCK_SIZE, -- .type = CRYPTO_ALG_TYPE_AEAD, -- .template_aead = { -- .setkey = aead_setkey, -- .setauthsize = aead_setauthsize, -- .encrypt = aead_encrypt, -- .decrypt = aead_decrypt, -- .givencrypt = aead_null_givencrypt, -- .geniv = "", -- .ivsize = NULL_IV_SIZE, -- .maxauthsize = SHA512_DIGEST_SIZE, -- }, -- .class1_alg_type = 0, -- .class2_alg_type = OP_ALG_ALGSEL_SHA512 | -- OP_ALG_AAI_HMAC_PRECOMP, -- .alg_op = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC, -- }, -+ char driver_name[CRYPTO_MAX_ALG_NAME]; -+ unsigned int blocksize; -+ u32 type; -+ union { -+ struct ablkcipher_alg ablkcipher; -+ struct aead_alg aead; -+ struct blkcipher_alg blkcipher; -+ struct cipher_alg cipher; -+ struct compress_alg compress; -+ struct rng_alg rng; -+ } template_u; -+ u32 class1_alg_type; -+ u32 class2_alg_type; -+ u32 alg_op; -+}; -+ -+static struct caam_alg_template driver_algs[] = { -+ /* single-pass ipsec_esp descriptor */ - { - .name = "authenc(hmac(md5),cbc(aes))", - .driver_name = "authenc-hmac-md5-cbc-aes-caam", -@@ -3865,188 +2047,81 @@ - OP_ALG_AAI_HMAC_PRECOMP, - .alg_op = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC, - }, -+ /* ablkcipher descriptor */ - { -- .name = "authenc(hmac(md5),rfc3686(ctr(aes)))", -- .driver_name = "authenc-hmac-md5-rfc3686-ctr-aes-caam", -- .blocksize = 1, -- .type = CRYPTO_ALG_TYPE_AEAD, -- .template_aead = { -- .setkey = aead_setkey, -- .setauthsize = aead_setauthsize, -- .encrypt = aead_encrypt, -- .decrypt = aead_decrypt, -- .givencrypt = aead_givencrypt, -- .geniv = "", -- .ivsize = CTR_RFC3686_IV_SIZE, -- .maxauthsize = MD5_DIGEST_SIZE, -- }, -- .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CTR_MOD128, -- .class2_alg_type = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC_PRECOMP, -- .alg_op = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC, -- }, -- { -- .name = "authenc(hmac(sha1),rfc3686(ctr(aes)))", -- .driver_name = "authenc-hmac-sha1-rfc3686-ctr-aes-caam", -- .blocksize = 1, -- .type = CRYPTO_ALG_TYPE_AEAD, -- .template_aead = { -- .setkey = aead_setkey, -- .setauthsize = aead_setauthsize, -- .encrypt = aead_encrypt, -- .decrypt = aead_decrypt, -- .givencrypt = aead_givencrypt, -- .geniv = "", -- .ivsize = CTR_RFC3686_IV_SIZE, -- .maxauthsize = SHA1_DIGEST_SIZE, -- }, -- .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CTR_MOD128, -- .class2_alg_type = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC_PRECOMP, -- .alg_op = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC, -- }, -- { -- .name = "authenc(hmac(sha224),rfc3686(ctr(aes)))", -- .driver_name = "authenc-hmac-sha224-rfc3686-ctr-aes-caam", -- .blocksize = 1, -- .type = CRYPTO_ALG_TYPE_AEAD, -- .template_aead = { -- .setkey = aead_setkey, -- .setauthsize = aead_setauthsize, -- .encrypt = aead_encrypt, -- .decrypt = aead_decrypt, -- .givencrypt = aead_givencrypt, -- .geniv = "", -- .ivsize = CTR_RFC3686_IV_SIZE, -- .maxauthsize = SHA224_DIGEST_SIZE, -+ .name = "ecb(des)", -+ .driver_name = "ecb-des-caam", -+ .blocksize = DES_BLOCK_SIZE, -+ .type = CRYPTO_ALG_TYPE_ABLKCIPHER, -+ .template_ablkcipher = { -+ .setkey = ablkcipher_setkey, -+ .encrypt = ablkcipher_encrypt, -+ .decrypt = ablkcipher_decrypt, -+ .geniv = "eseqiv", -+ .min_keysize = DES_KEY_SIZE, -+ .max_keysize = DES_KEY_SIZE, -+ .ivsize = DES_BLOCK_SIZE, - }, -- .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CTR_MOD128, -- .class2_alg_type = OP_ALG_ALGSEL_SHA224 | -- OP_ALG_AAI_HMAC_PRECOMP, -- .alg_op = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC, -+ .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_ECB, - }, - { -- .name = "authenc(hmac(sha256),rfc3686(ctr(aes)))", -- .driver_name = "authenc-hmac-sha256-rfc3686-ctr-aes-caam", -- .blocksize = 1, -- .type = CRYPTO_ALG_TYPE_AEAD, -- .template_aead = { -- .setkey = aead_setkey, -- .setauthsize = aead_setauthsize, -- .encrypt = aead_encrypt, -- .decrypt = aead_decrypt, -- .givencrypt = aead_givencrypt, -- .geniv = "", -- .ivsize = CTR_RFC3686_IV_SIZE, -- .maxauthsize = SHA256_DIGEST_SIZE, -- }, -- .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CTR_MOD128, -- .class2_alg_type = OP_ALG_ALGSEL_SHA256 | -- OP_ALG_AAI_HMAC_PRECOMP, -- .alg_op = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC, -+ .name = "ecb(arc4)", -+ .driver_name = "ecb-arc4-caam", -+ .blocksize = ARC4_BLOCK_SIZE, -+ .type = CRYPTO_ALG_TYPE_ABLKCIPHER, -+ .template_ablkcipher = { -+ .setkey = ablkcipher_setkey, -+ .encrypt = ablkcipher_encrypt, -+ .decrypt = ablkcipher_decrypt, -+ .geniv = "eseqiv", -+ .min_keysize = ARC4_MIN_KEY_SIZE, -+ .max_keysize = ARC4_MAX_KEY_SIZE, -+ .ivsize = ARC4_BLOCK_SIZE, -+ }, -+ .class1_alg_type = OP_ALG_ALGSEL_ARC4 | OP_ALG_AAI_ECB - }, - { -- .name = "authenc(hmac(sha384),rfc3686(ctr(aes)))", -- .driver_name = "authenc-hmac-sha384-rfc3686-ctr-aes-caam", -- .blocksize = 1, -- .type = CRYPTO_ALG_TYPE_AEAD, -- .template_aead = { -- .setkey = aead_setkey, -- .setauthsize = aead_setauthsize, -- .encrypt = aead_encrypt, -- .decrypt = aead_decrypt, -- .givencrypt = aead_givencrypt, -- .geniv = "", -- .ivsize = CTR_RFC3686_IV_SIZE, -- .maxauthsize = SHA384_DIGEST_SIZE, -+ .name = "ecb(aes)", -+ .driver_name = "ecb-aes-caam", -+ .blocksize = AES_BLOCK_SIZE, -+ .type = CRYPTO_ALG_TYPE_ABLKCIPHER, -+ .template_ablkcipher = { -+ .setkey = ablkcipher_setkey, -+ .encrypt = ablkcipher_encrypt, -+ .decrypt = ablkcipher_decrypt, -+ .geniv = "eseqiv", -+ .min_keysize = AES_MIN_KEY_SIZE, -+ .max_keysize = AES_MAX_KEY_SIZE, -+ .ivsize = AES_BLOCK_SIZE, - }, -- .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CTR_MOD128, -- .class2_alg_type = OP_ALG_ALGSEL_SHA384 | -- OP_ALG_AAI_HMAC_PRECOMP, -- .alg_op = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC, -+ .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_ECB, - }, - { -- .name = "authenc(hmac(sha512),rfc3686(ctr(aes)))", -- .driver_name = "authenc-hmac-sha512-rfc3686-ctr-aes-caam", -- .blocksize = 1, -- .type = CRYPTO_ALG_TYPE_AEAD, -- .template_aead = { -- .setkey = aead_setkey, -- .setauthsize = aead_setauthsize, -- .encrypt = aead_encrypt, -- .decrypt = aead_decrypt, -- .givencrypt = aead_givencrypt, -- .geniv = "", -- .ivsize = CTR_RFC3686_IV_SIZE, -- .maxauthsize = SHA512_DIGEST_SIZE, -+ .name = "ctr(aes)", -+ .driver_name = "ctr-aes-caam", -+ .blocksize = AES_BLOCK_SIZE, -+ .type = CRYPTO_ALG_TYPE_ABLKCIPHER, -+ .template_ablkcipher = { -+ .setkey = ablkcipher_setkey, -+ .encrypt = ablkcipher_encrypt, -+ .decrypt = ablkcipher_decrypt, -+ .geniv = "eseqiv", -+ .min_keysize = AES_MIN_KEY_SIZE, -+ .max_keysize = AES_MAX_KEY_SIZE, -+ .ivsize = AES_BLOCK_SIZE, - }, - .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CTR_MOD128, -- .class2_alg_type = OP_ALG_ALGSEL_SHA512 | -- OP_ALG_AAI_HMAC_PRECOMP, -- .alg_op = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC, -- }, -- { -- .name = "rfc4106(gcm(aes))", -- .driver_name = "rfc4106-gcm-aes-caam", -- .blocksize = 1, -- .type = CRYPTO_ALG_TYPE_AEAD, -- .template_aead = { -- .setkey = rfc4106_setkey, -- .setauthsize = rfc4106_setauthsize, -- .encrypt = aead_encrypt, -- .decrypt = aead_decrypt, -- .givencrypt = aead_givencrypt, -- .geniv = "", -- .ivsize = 8, -- .maxauthsize = AES_BLOCK_SIZE, -- }, -- .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM, -- }, -- { -- .name = "rfc4543(gcm(aes))", -- .driver_name = "rfc4543-gcm-aes-caam", -- .blocksize = 1, -- .type = CRYPTO_ALG_TYPE_AEAD, -- .template_aead = { -- .setkey = rfc4543_setkey, -- .setauthsize = rfc4543_setauthsize, -- .encrypt = aead_encrypt, -- .decrypt = aead_decrypt, -- .givencrypt = aead_givencrypt, -- .geniv = "", -- .ivsize = 8, -- .maxauthsize = AES_BLOCK_SIZE, -- }, -- .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM, -- }, -- /* Galois Counter Mode */ -- { -- .name = "gcm(aes)", -- .driver_name = "gcm-aes-caam", -- .blocksize = 1, -- .type = CRYPTO_ALG_TYPE_AEAD, -- .template_aead = { -- .setkey = gcm_setkey, -- .setauthsize = gcm_setauthsize, -- .encrypt = aead_encrypt, -- .decrypt = aead_decrypt, -- .givencrypt = NULL, -- .geniv = "", -- .ivsize = 12, -- .maxauthsize = AES_BLOCK_SIZE, -- }, -- .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_GCM, - }, -- /* ablkcipher descriptor */ - { - .name = "cbc(aes)", - .driver_name = "cbc-aes-caam", - .blocksize = AES_BLOCK_SIZE, -- .type = CRYPTO_ALG_TYPE_GIVCIPHER, -+ .type = CRYPTO_ALG_TYPE_ABLKCIPHER, - .template_ablkcipher = { - .setkey = ablkcipher_setkey, - .encrypt = ablkcipher_encrypt, - .decrypt = ablkcipher_decrypt, -- .givencrypt = ablkcipher_givencrypt, -- .geniv = "", -+ .geniv = "eseqiv", - .min_keysize = AES_MIN_KEY_SIZE, - .max_keysize = AES_MAX_KEY_SIZE, - .ivsize = AES_BLOCK_SIZE, -@@ -4054,16 +2129,31 @@ - .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC, - }, - { -+ .name = "ecb(des3_ede)", -+ .driver_name = "ecb-des3-caam", -+ .blocksize = DES3_EDE_BLOCK_SIZE, -+ .type = CRYPTO_ALG_TYPE_ABLKCIPHER, -+ .template_ablkcipher = { -+ .setkey = ablkcipher_setkey, -+ .encrypt = ablkcipher_encrypt, -+ .decrypt = ablkcipher_decrypt, -+ .geniv = "eseqiv", -+ .min_keysize = DES3_EDE_KEY_SIZE, -+ .max_keysize = DES3_EDE_KEY_SIZE, -+ .ivsize = DES3_EDE_BLOCK_SIZE, -+ }, -+ .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_ECB, -+ }, -+ { - .name = "cbc(des3_ede)", - .driver_name = "cbc-3des-caam", - .blocksize = DES3_EDE_BLOCK_SIZE, -- .type = CRYPTO_ALG_TYPE_GIVCIPHER, -+ .type = CRYPTO_ALG_TYPE_ABLKCIPHER, - .template_ablkcipher = { - .setkey = ablkcipher_setkey, - .encrypt = ablkcipher_encrypt, - .decrypt = ablkcipher_decrypt, -- .givencrypt = ablkcipher_givencrypt, -- .geniv = "", -+ .geniv = "eseqiv", - .min_keysize = DES3_EDE_KEY_SIZE, - .max_keysize = DES3_EDE_KEY_SIZE, - .ivsize = DES3_EDE_BLOCK_SIZE, -@@ -4074,58 +2164,23 @@ - .name = "cbc(des)", - .driver_name = "cbc-des-caam", - .blocksize = DES_BLOCK_SIZE, -- .type = CRYPTO_ALG_TYPE_GIVCIPHER, -+ .type = CRYPTO_ALG_TYPE_ABLKCIPHER, - .template_ablkcipher = { - .setkey = ablkcipher_setkey, - .encrypt = ablkcipher_encrypt, - .decrypt = ablkcipher_decrypt, -- .givencrypt = ablkcipher_givencrypt, -- .geniv = "", -+ .geniv = "eseqiv", - .min_keysize = DES_KEY_SIZE, - .max_keysize = DES_KEY_SIZE, - .ivsize = DES_BLOCK_SIZE, - }, - .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC, -- }, -- { -- .name = "ctr(aes)", -- .driver_name = "ctr-aes-caam", -- .blocksize = 1, -- .type = CRYPTO_ALG_TYPE_ABLKCIPHER, -- .template_ablkcipher = { -- .setkey = ablkcipher_setkey, -- .encrypt = ablkcipher_encrypt, -- .decrypt = ablkcipher_decrypt, -- .geniv = "chainiv", -- .min_keysize = AES_MIN_KEY_SIZE, -- .max_keysize = AES_MAX_KEY_SIZE, -- .ivsize = AES_BLOCK_SIZE, -- }, -- .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CTR_MOD128, -- }, -- { -- .name = "rfc3686(ctr(aes))", -- .driver_name = "rfc3686-ctr-aes-caam", -- .blocksize = 1, -- .type = CRYPTO_ALG_TYPE_GIVCIPHER, -- .template_ablkcipher = { -- .setkey = ablkcipher_setkey, -- .encrypt = ablkcipher_encrypt, -- .decrypt = ablkcipher_decrypt, -- .givencrypt = ablkcipher_givencrypt, -- .geniv = "", -- .min_keysize = AES_MIN_KEY_SIZE + -- CTR_RFC3686_NONCE_SIZE, -- .max_keysize = AES_MAX_KEY_SIZE + -- CTR_RFC3686_NONCE_SIZE, -- .ivsize = CTR_RFC3686_IV_SIZE, -- }, -- .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CTR_MOD128, - } - }; - - struct caam_crypto_alg { - struct list_head entry; -+ struct device *ctrldev; - int class1_alg_type; - int class2_alg_type; - int alg_op; -@@ -4138,12 +2193,14 @@ - struct caam_crypto_alg *caam_alg = - container_of(alg, struct caam_crypto_alg, crypto_alg); - struct caam_ctx *ctx = crypto_tfm_ctx(tfm); -+ struct caam_drv_private *priv = dev_get_drvdata(caam_alg->ctrldev); -+ int tgt_jr = atomic_inc_return(&priv->tfm_count); - -- ctx->jrdev = caam_jr_alloc(); -- if (IS_ERR(ctx->jrdev)) { -- pr_err("Job Ring Device allocation for transform failed\n"); -- return PTR_ERR(ctx->jrdev); -- } -+ /* -+ * distribute tfms across job rings to ensure in-order -+ * crypto request processing per tfm -+ */ -+ ctx->jrdev = priv->algapi_jr[(tgt_jr / 2) % priv->num_jrs_for_algapi]; - - /* copy descriptor header template value */ - ctx->class1_alg_type = OP_TYPE_CLASS1_ALG | caam_alg->class1_alg_type; -@@ -4170,31 +2227,57 @@ - dma_unmap_single(ctx->jrdev, ctx->sh_desc_givenc_dma, - desc_bytes(ctx->sh_desc_givenc), - DMA_TO_DEVICE); -- if (ctx->key_dma && -- !dma_mapping_error(ctx->jrdev, ctx->key_dma)) -- dma_unmap_single(ctx->jrdev, ctx->key_dma, -- ctx->enckeylen + ctx->split_key_pad_len, -- DMA_TO_DEVICE); -- -- caam_jr_free(ctx->jrdev); - } - - static void __exit caam_algapi_exit(void) - { - -+ struct device_node *dev_node; -+ struct platform_device *pdev; -+ struct device *ctrldev; -+ struct caam_drv_private *priv; - struct caam_crypto_alg *t_alg, *n; -+ int i, err; -+ -+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); -+ if (!dev_node) { -+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0"); -+ if (!dev_node) -+ return; -+ } -+ -+ pdev = of_find_device_by_node(dev_node); -+ if (!pdev) { -+ of_node_put(dev_node); -+ return; -+ } - -- if (!alg_list.next) -+ ctrldev = &pdev->dev; -+ priv = dev_get_drvdata(ctrldev); -+ -+ if (!priv->alg_list.next) { -+ of_node_put(dev_node); - return; -+ } - -- list_for_each_entry_safe(t_alg, n, &alg_list, entry) { -+ list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) { - crypto_unregister_alg(&t_alg->crypto_alg); - list_del(&t_alg->entry); - kfree(t_alg); - } -+ -+ for (i = 0; i < priv->total_jobrs; i++) { -+ err = caam_jr_deregister(priv->algapi_jr[i]); -+ if (err < 0) -+ break; -+ } -+ kfree(priv->algapi_jr); -+ -+ of_node_put(dev_node); - } - --static struct caam_crypto_alg *caam_alg_alloc(struct caam_alg_template -+static struct caam_crypto_alg *caam_alg_alloc(struct device *ctrldev, -+ struct caam_alg_template - *template) - { - struct caam_crypto_alg *t_alg; -@@ -4202,7 +2285,7 @@ - - t_alg = kzalloc(sizeof(struct caam_crypto_alg), GFP_KERNEL); - if (!t_alg) { -- pr_err("failed to allocate t_alg\n"); -+ dev_err(ctrldev, "failed to allocate t_alg\n"); - return ERR_PTR(-ENOMEM); - } - -@@ -4218,13 +2301,13 @@ - alg->cra_blocksize = template->blocksize; - alg->cra_alignmask = 0; - alg->cra_ctxsize = sizeof(struct caam_ctx); -- alg->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY | -- template->type; -+ alg->cra_flags = CRYPTO_ALG_ASYNC | template->type; -+ -+#ifdef CRYPTO_ALG_KERN_DRIVER_ONLY -+ alg->cra_flags |= CRYPTO_ALG_KERN_DRIVER_ONLY; -+#endif -+ - switch (template->type) { -- case CRYPTO_ALG_TYPE_GIVCIPHER: -- alg->cra_type = &crypto_givcipher_type; -- alg->cra_ablkcipher = template->template_ablkcipher; -- break; - case CRYPTO_ALG_TYPE_ABLKCIPHER: - alg->cra_type = &crypto_ablkcipher_type; - alg->cra_ablkcipher = template->template_ablkcipher; -@@ -4238,6 +2321,7 @@ - t_alg->class1_alg_type = template->class1_alg_type; - t_alg->class2_alg_type = template->class2_alg_type; - t_alg->alg_op = template->alg_op; -+ t_alg->ctrldev = ctrldev; - - return t_alg; - } -@@ -4246,9 +2330,11 @@ - { - struct device_node *dev_node; - struct platform_device *pdev; -- struct device *ctrldev; -- void *priv; -- int i = 0, err = 0; -+ struct device *ctrldev, **jrdev; -+ struct caam_drv_private *priv; -+ int i = 0, err = 0, md_limit = 0; -+ int des_inst, aes_inst, md_inst; -+ u64 cha_inst; - - dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); - if (!dev_node) { -@@ -4265,42 +2351,117 @@ - - ctrldev = &pdev->dev; - priv = dev_get_drvdata(ctrldev); -- of_node_put(dev_node); - -- /* -- * If priv is NULL, it's probably because the caam driver wasn't -- * properly initialized (e.g. RNG4 init failed). Thus, bail out here. -- */ -- if (!priv) -- return -ENODEV; -+ INIT_LIST_HEAD(&priv->alg_list); -+ -+ jrdev = kmalloc(sizeof(*jrdev) * priv->total_jobrs, GFP_ATOMIC); -+ if (!jrdev) { -+ of_node_put(dev_node); -+ return -ENOMEM; -+ } - -+ for (i = 0; i < priv->total_jobrs; i++) { -+ err = caam_jr_register(ctrldev, &jrdev[i]); -+ if (err < 0) -+ break; -+ } -+ if (err < 0 && i == 0) { -+ dev_err(ctrldev, "algapi error in job ring registration: %d\n", -+ err); -+ of_node_put(dev_node); -+ kfree(jrdev); -+ return err; -+ } - -- INIT_LIST_HEAD(&alg_list); -+ priv->num_jrs_for_algapi = i; -+ priv->algapi_jr = jrdev; -+ atomic_set(&priv->tfm_count, -1); -+ -+ /* -+ * register crypto algorithms the device supports -+ * first, detect presence of DES, AES, and MD blocks. If MD present, -+ * determine limit of supported digest size -+ */ -+ cha_inst = rd_reg64(&priv->ctrl->perfmon.cha_num); -+ des_inst = (cha_inst & CHA_ID_DES_MASK) >> CHA_ID_DES_SHIFT; -+ aes_inst = (cha_inst & CHA_ID_AES_MASK) >> CHA_ID_AES_SHIFT; -+ md_inst = (cha_inst & CHA_ID_MD_MASK) >> CHA_ID_MD_SHIFT; -+ if (md_inst) { -+ md_limit = SHA512_DIGEST_SIZE; -+ if ((rd_reg64(&priv->ctrl->perfmon.cha_id) & CHA_ID_MD_MASK) -+ == CHA_ID_MD_LP256) /* LP256 limits digest size */ -+ md_limit = SHA256_DIGEST_SIZE; -+ } - -- /* register crypto algorithms the device supports */ - for (i = 0; i < ARRAY_SIZE(driver_algs); i++) { -- /* TODO: check if h/w supports alg */ - struct caam_crypto_alg *t_alg; -+ bool done = false; -+ -+authencesn: -+ /* -+ * All registrable algs in this module require a blockcipher -+ * All aead algs require message digests, so check them for -+ * instantiation and size. -+ */ -+ if (driver_algs[i].type == CRYPTO_ALG_TYPE_AEAD) { -+ /* If no MD instantiated, or MD too small, skip */ -+ if ((!md_inst) || -+ (driver_algs[i].template_aead.maxauthsize > -+ md_limit)) -+ continue; -+ } -+ /* If DES alg, and CHA not instantiated, skip */ -+ if ((driver_algs[i].class1_alg_type & OP_ALG_ALGSEL_3DES) || -+ (driver_algs[i].class1_alg_type & OP_ALG_ALGSEL_DES)) -+ if (!des_inst) -+ continue; -+ /* If AES alg, and CHA not instantiated, skip */ -+ if (driver_algs[i].class1_alg_type & OP_ALG_ALGSEL_AES) -+ if (!aes_inst) -+ continue; - -- t_alg = caam_alg_alloc(&driver_algs[i]); -+ t_alg = caam_alg_alloc(ctrldev, &driver_algs[i]); - if (IS_ERR(t_alg)) { - err = PTR_ERR(t_alg); -- pr_warn("%s alg allocation failed\n", -- driver_algs[i].driver_name); -+ dev_warn(ctrldev, "%s alg allocation failed\n", -+ driver_algs[i].driver_name); - continue; - } - - err = crypto_register_alg(&t_alg->crypto_alg); - if (err) { -- pr_warn("%s alg registration failed\n", -+ dev_warn(ctrldev, "%s alg registration failed\n", - t_alg->crypto_alg.cra_driver_name); - kfree(t_alg); -- } else -- list_add_tail(&t_alg->entry, &alg_list); -+ } else { -+ list_add_tail(&t_alg->entry, &priv->alg_list); -+ dev_info(ctrldev, "%s\n", -+ t_alg->crypto_alg.cra_driver_name); -+ -+ if (driver_algs[i].type == CRYPTO_ALG_TYPE_AEAD && -+ !memcmp(driver_algs[i].name, "authenc", 7) && -+ !done) { -+ char *name; -+ -+ name = driver_algs[i].name; -+ memmove(name + 10, name + 7, strlen(name) - 7); -+ memcpy(name + 7, "esn", 3); -+ -+ name = driver_algs[i].driver_name; -+ memmove(name + 10, name + 7, strlen(name) - 7); -+ memcpy(name + 7, "esn", 3); -+ -+ done = true; -+ goto authencesn; -+ } -+ } - } -- if (!list_empty(&alg_list)) -- pr_info("caam algorithms registered in /proc/crypto\n"); - -+ if (!list_empty(&priv->alg_list)) -+ dev_info(ctrldev, "%s algorithms registered in /proc/crypto\n", -+ (char *)of_get_property(dev_node, "compatible", NULL)); -+ -+ of_node_put(dev_node); - return err; - } - -diff -Nur linux-4.1.13.orig/drivers/crypto/caam/caamhash.c linux-4.1.13/drivers/crypto/caam/caamhash.c ---- linux-4.1.13.orig/drivers/crypto/caam/caamhash.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/crypto/caam/caamhash.c 2015-11-30 17:56:13.548139857 +0100 -@@ -1,7 +1,7 @@ - /* - * caam - Freescale FSL CAAM support for ahash functions of crypto API - * -- * Copyright 2011 Freescale Semiconductor, Inc. -+ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. - * - * Based on caamalg.c crypto API driver. - * -@@ -62,6 +62,7 @@ - #include "error.h" - #include "sg_sw_sec4.h" - #include "key_gen.h" -+#include - - #define CAAM_CRA_PRIORITY 3000 - -@@ -72,6 +73,8 @@ - #define CAAM_MAX_HASH_DIGEST_SIZE SHA512_DIGEST_SIZE - - /* length of descriptors text */ -+#define DESC_JOB_IO_LEN (CAAM_CMD_SZ * 5 + CAAM_PTR_SZ * 3) -+ - #define DESC_AHASH_BASE (4 * CAAM_CMD_SZ) - #define DESC_AHASH_UPDATE_LEN (6 * CAAM_CMD_SZ) - #define DESC_AHASH_UPDATE_FIRST_LEN (DESC_AHASH_BASE + 4 * CAAM_CMD_SZ) -@@ -89,14 +92,13 @@ - - #ifdef DEBUG - /* for print_hex_dumps with line references */ -+#define xstr(s) str(s) -+#define str(s) #s - #define debug(format, arg...) printk(format, arg) - #else - #define debug(format, arg...) - #endif - -- --static struct list_head hash_list; -- - /* ahash per-session context */ - struct caam_hash_ctx { - struct device *jrdev; -@@ -115,6 +117,7 @@ - u8 key[CAAM_MAX_HASH_KEY_SIZE]; - dma_addr_t key_dma; - int ctx_len; -+ unsigned int key_len; - unsigned int split_key_len; - unsigned int split_key_pad_len; - }; -@@ -137,20 +140,13 @@ - /* Common job descriptor seq in/out ptr routines */ - - /* Map state->caam_ctx, and append seq_out_ptr command that points to it */ --static inline int map_seq_out_ptr_ctx(u32 *desc, struct device *jrdev, -- struct caam_hash_state *state, -- int ctx_len) -+static inline void map_seq_out_ptr_ctx(u32 *desc, struct device *jrdev, -+ struct caam_hash_state *state, -+ int ctx_len) - { - state->ctx_dma = dma_map_single(jrdev, state->caam_ctx, - ctx_len, DMA_FROM_DEVICE); -- if (dma_mapping_error(jrdev, state->ctx_dma)) { -- dev_err(jrdev, "unable to map ctx\n"); -- return -ENOMEM; -- } -- - append_seq_out_ptr(desc, state->ctx_dma, ctx_len, 0); -- -- return 0; - } - - /* Map req->result, and append seq_out_ptr command that points to it */ -@@ -173,6 +169,7 @@ - dma_addr_t buf_dma; - - buf_dma = dma_map_single(jrdev, buf, buflen, DMA_TO_DEVICE); -+ dma_sync_single_for_device(jrdev, buf_dma, buflen, DMA_TO_DEVICE); - dma_to_sec4_sg_one(sec4_sg, buf_dma, buflen, 0); - - return buf_dma; -@@ -208,19 +205,17 @@ - } - - /* Map state->caam_ctx, and add it to link table */ --static inline int ctx_map_to_sec4_sg(u32 *desc, struct device *jrdev, -- struct caam_hash_state *state, int ctx_len, -- struct sec4_sg_entry *sec4_sg, u32 flag) -+static inline void ctx_map_to_sec4_sg(u32 *desc, struct device *jrdev, -+ struct caam_hash_state *state, -+ int ctx_len, -+ struct sec4_sg_entry *sec4_sg, -+ u32 flag) - { - state->ctx_dma = dma_map_single(jrdev, state->caam_ctx, ctx_len, flag); -- if (dma_mapping_error(jrdev, state->ctx_dma)) { -- dev_err(jrdev, "unable to map ctx\n"); -- return -ENOMEM; -- } -- -+ if ((flag == DMA_TO_DEVICE) || (flag == DMA_BIDIRECTIONAL)) -+ dma_sync_single_for_device(jrdev, state->ctx_dma, ctx_len, -+ flag); - dma_to_sec4_sg_one(sec4_sg, state->ctx_dma, ctx_len, 0); -- -- return 0; - } - - /* Common shared descriptor commands */ -@@ -231,6 +226,13 @@ - KEY_DEST_MDHA_SPLIT | KEY_ENC); - } - -+static inline void append_key_axcbc(u32 *desc, struct caam_hash_ctx *ctx) -+{ -+ append_key_as_imm(desc, ctx->key, ctx->key_len, -+ ctx->key_len, CLASS_1 | -+ KEY_DEST_CLASS_REG); -+} -+ - /* Append key if it has been set */ - static inline void init_sh_desc_key_ahash(u32 *desc, struct caam_hash_ctx *ctx) - { -@@ -252,6 +254,25 @@ - append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD); - } - -+static inline void init_sh_desc_key_axcbc(u32 *desc, struct caam_hash_ctx *ctx) -+{ -+ u32 *key_jump_cmd; -+ -+ init_sh_desc(desc, HDR_SHARE_SERIAL); -+ -+ if (ctx->key_len) { -+ key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL | -+ JUMP_COND_SHRD); -+ -+ append_key_axcbc(desc, ctx); -+ -+ set_jump_tgt_here(desc, key_jump_cmd); -+ } -+ -+ /* Propagate errors from shared to job descriptor */ -+ append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD); -+ -+} - /* - * For ahash read data from seqin following state->caam_ctx, - * and write resulting class2 context to seqout, which may be state->caam_ctx -@@ -271,6 +292,20 @@ - LDST_SRCDST_BYTE_CONTEXT); - } - -+static inline void axcbc_append_load_str(u32 *desc, int digestsize) -+{ -+ /* Calculate remaining bytes to read */ -+ append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ); -+ -+ /* Read remaining bytes */ -+ append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 | FIFOLD_TYPE_LAST1 | -+ FIFOLD_TYPE_MSG | KEY_VLF); -+ -+ /* Store class1 context bytes */ -+ append_seq_store(desc, digestsize, LDST_CLASS_1_CCB | -+ LDST_SRCDST_BYTE_CONTEXT); -+} -+ - /* - * For ahash update, final and finup, import context, read and write to seqout - */ -@@ -293,6 +328,27 @@ - ahash_append_load_str(desc, digestsize); - } - -+/* -+ * For ahash update, final and finup, import context, read and write to seqout -+ */ -+static inline void axcbc_ctx_data_to_out(u32 *desc, u32 op, u32 state, -+ int digestsize, -+ struct caam_hash_ctx *ctx) -+{ -+ init_sh_desc_key_axcbc(desc, ctx); -+ -+ /* Import context from software */ -+ append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT | -+ LDST_CLASS_1_CCB | ctx->ctx_len); -+ -+ /* Class 1 operation */ -+ append_operation(desc, op | state | OP_ALG_ENCRYPT); -+ -+ /* -+ * Load from buf and/or src and write to req->result or state->context -+ */ -+ axcbc_append_load_str(desc, digestsize); -+} - /* For ahash firsts and digest, read and write to seqout */ - static inline void ahash_data_to_out(u32 *desc, u32 op, u32 state, - int digestsize, struct caam_hash_ctx *ctx) -@@ -308,6 +364,21 @@ - ahash_append_load_str(desc, digestsize); - } - -+/* For ahash firsts and digest, read and write to seqout */ -+static inline void axcbc_data_to_out(u32 *desc, u32 op, u32 state, -+ int digestsize, struct caam_hash_ctx *ctx) -+{ -+ init_sh_desc_key_axcbc(desc, ctx); -+ -+ /* Class 1 operation */ -+ append_operation(desc, op | state | OP_ALG_ENCRYPT); -+ -+ /* -+ * Load from buf and/or src and write to req->result or state->context -+ */ -+ axcbc_append_load_str(desc, digestsize); -+} -+ - static int ahash_set_sh_desc(struct crypto_ahash *ahash) - { - struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); -@@ -342,8 +413,7 @@ - return -ENOMEM; - } - #ifdef DEBUG -- print_hex_dump(KERN_ERR, -- "ahash update shdesc@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "ahash update shdesc@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1); - #endif - -@@ -361,10 +431,11 @@ - return -ENOMEM; - } - #ifdef DEBUG -- print_hex_dump(KERN_ERR, -- "ahash update first shdesc@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "ahash update first shdesc@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1); - #endif -+ dma_sync_single_for_device(jrdev, ctx->sh_desc_update_first_dma, -+ desc_bytes(desc), DMA_TO_DEVICE); - - /* ahash_final shared descriptor */ - desc = ctx->sh_desc_fin; -@@ -379,10 +450,12 @@ - return -ENOMEM; - } - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "ahash final shdesc@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "ahash final shdesc@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, desc, - desc_bytes(desc), 1); - #endif -+ dma_sync_single_for_device(jrdev, ctx->sh_desc_fin_dma, -+ desc_bytes(desc), DMA_TO_DEVICE); - - /* ahash_finup shared descriptor */ - desc = ctx->sh_desc_finup; -@@ -397,10 +470,12 @@ - return -ENOMEM; - } - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "ahash finup shdesc@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "ahash finup shdesc@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, desc, - desc_bytes(desc), 1); - #endif -+ dma_sync_single_for_device(jrdev, ctx->sh_desc_finup_dma, -+ desc_bytes(desc), DMA_TO_DEVICE); - - /* ahash_digest shared descriptor */ - desc = ctx->sh_desc_digest; -@@ -416,15 +491,134 @@ - return -ENOMEM; - } - #ifdef DEBUG -- print_hex_dump(KERN_ERR, -- "ahash digest shdesc@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "ahash digest shdesc@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, desc, - desc_bytes(desc), 1); - #endif -+ dma_sync_single_for_device(jrdev, ctx->sh_desc_digest_dma, -+ desc_bytes(desc), DMA_TO_DEVICE); - - return 0; - } - -+static int axcbc_set_sh_desc(struct crypto_ahash *ahash) -+{ -+ struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); -+ int digestsize = crypto_ahash_digestsize(ahash); -+ struct device *jrdev = ctx->jrdev; -+ u32 have_key = 0; -+ u32 *desc; -+ -+ /* ahash_update shared descriptor */ -+ desc = ctx->sh_desc_update; -+ -+ init_sh_desc(desc, HDR_SHARE_SERIAL); -+ -+ /* Import context from software */ -+ append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT | -+ LDST_CLASS_1_CCB | ctx->ctx_len); -+ -+ /* Class 1 operation */ -+ append_operation(desc, ctx->alg_type | OP_ALG_AS_UPDATE | -+ OP_ALG_ENCRYPT); -+ -+ /* Load data and write to result or context */ -+ axcbc_append_load_str(desc, ctx->ctx_len); -+ -+ ctx->sh_desc_update_dma = dma_map_single(jrdev, desc, desc_bytes(desc), -+ DMA_TO_DEVICE); -+ if (dma_mapping_error(jrdev, ctx->sh_desc_update_dma)) { -+ dev_err(jrdev, "unable to map shared descriptor\n"); -+ return -ENOMEM; -+ } -+#ifdef DEBUG -+ print_hex_dump(KERN_ERR, "ahash update shdesc@"xstr(__LINE__)": ", -+ DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1); -+#endif -+ -+ /* ahash_update_first shared descriptor */ -+ desc = ctx->sh_desc_update_first; -+ -+ axcbc_data_to_out(desc, have_key | ctx->alg_type, OP_ALG_AS_INIT, -+ ctx->ctx_len, ctx); -+ -+ ctx->sh_desc_update_first_dma = dma_map_single(jrdev, desc, -+ desc_bytes(desc), -+ DMA_TO_DEVICE); -+ if (dma_mapping_error(jrdev, ctx->sh_desc_update_first_dma)) { -+ dev_err(jrdev, "unable to map shared descriptor\n"); -+ return -ENOMEM; -+ } -+#ifdef DEBUG -+ print_hex_dump(KERN_ERR, "ahash update first shdesc@"xstr(__LINE__)": ", -+ DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1); -+#endif -+ dma_sync_single_for_device(jrdev, ctx->sh_desc_update_first_dma, -+ desc_bytes(desc), DMA_TO_DEVICE); -+ -+ /* ahash_final shared descriptor */ -+ desc = ctx->sh_desc_fin; -+ -+ axcbc_ctx_data_to_out(desc, have_key | ctx->alg_type, -+ OP_ALG_AS_FINALIZE, digestsize, ctx); -+ -+ ctx->sh_desc_fin_dma = dma_map_single(jrdev, desc, desc_bytes(desc), -+ DMA_TO_DEVICE); -+ if (dma_mapping_error(jrdev, ctx->sh_desc_fin_dma)) { -+ dev_err(jrdev, "unable to map shared descriptor\n"); -+ return -ENOMEM; -+ } -+#ifdef DEBUG -+ print_hex_dump(KERN_ERR, "ahash final shdesc@"xstr(__LINE__)": ", -+ DUMP_PREFIX_ADDRESS, 16, 4, desc, -+ desc_bytes(desc), 1); -+#endif -+ dma_sync_single_for_device(jrdev, ctx->sh_desc_fin_dma, -+ desc_bytes(desc), DMA_TO_DEVICE); -+ -+ /* ahash_finup shared descriptor */ -+ desc = ctx->sh_desc_finup; -+ -+ axcbc_ctx_data_to_out(desc, have_key | ctx->alg_type, -+ OP_ALG_AS_FINALIZE, digestsize, ctx); -+ -+ ctx->sh_desc_finup_dma = dma_map_single(jrdev, desc, desc_bytes(desc), -+ DMA_TO_DEVICE); -+ if (dma_mapping_error(jrdev, ctx->sh_desc_finup_dma)) { -+ dev_err(jrdev, "unable to map shared descriptor\n"); -+ return -ENOMEM; -+ } -+#ifdef DEBUG -+ print_hex_dump(KERN_ERR, "ahash finup shdesc@"xstr(__LINE__)": ", -+ DUMP_PREFIX_ADDRESS, 16, 4, desc, -+ desc_bytes(desc), 1); -+#endif -+ dma_sync_single_for_device(jrdev, ctx->sh_desc_finup_dma, -+ desc_bytes(desc), DMA_TO_DEVICE); -+ -+ /* ahash_digest shared descriptor */ -+ desc = ctx->sh_desc_digest; -+ -+ axcbc_data_to_out(desc, have_key | ctx->alg_type, OP_ALG_AS_INITFINAL, -+ digestsize, ctx); -+ -+ ctx->sh_desc_digest_dma = dma_map_single(jrdev, desc, -+ desc_bytes(desc), -+ DMA_TO_DEVICE); -+ if (dma_mapping_error(jrdev, ctx->sh_desc_digest_dma)) { -+ dev_err(jrdev, "unable to map shared descriptor\n"); -+ return -ENOMEM; -+ } -+#ifdef DEBUG -+ print_hex_dump(KERN_ERR, "ahash digest shdesc@"xstr(__LINE__)": ", -+ DUMP_PREFIX_ADDRESS, 16, 4, desc, -+ desc_bytes(desc), 1); -+#endif -+ dma_sync_single_for_device(jrdev, ctx->sh_desc_digest_dma, -+ desc_bytes(desc), DMA_TO_DEVICE); -+ -+ return 0; -+} - static int gen_split_hash_key(struct caam_hash_ctx *ctx, const u8 *key_in, - u32 keylen) - { -@@ -458,6 +652,8 @@ - kfree(desc); - return -ENOMEM; - } -+ dma_sync_single_for_device(jrdev, src_dma, *keylen, DMA_TO_DEVICE); -+ - dst_dma = dma_map_single(jrdev, (void *)key_out, digestsize, - DMA_FROM_DEVICE); - if (dma_mapping_error(jrdev, dst_dma)) { -@@ -478,9 +674,9 @@ - LDST_SRCDST_BYTE_CONTEXT); - - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "key_in@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "key_in@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, key_in, *keylen, 1); -- print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "jobdesc@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1); - #endif - -@@ -493,17 +689,17 @@ - wait_for_completion_interruptible(&result.completion); - ret = result.err; - #ifdef DEBUG -- print_hex_dump(KERN_ERR, -- "digested key@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "digested key@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, key_in, - digestsize, 1); - #endif - } -+ *keylen = digestsize; -+ - dma_unmap_single(jrdev, src_dma, *keylen, DMA_TO_DEVICE); -+ dma_sync_single_for_cpu(jrdev, dst_dma, digestsize, DMA_FROM_DEVICE); - dma_unmap_single(jrdev, dst_dma, digestsize, DMA_FROM_DEVICE); - -- *keylen = digestsize; -- - kfree(desc); - - return ret; -@@ -545,7 +741,7 @@ - #ifdef DEBUG - printk(KERN_ERR "split_key_len %d split_key_pad_len %d\n", - ctx->split_key_len, ctx->split_key_pad_len); -- print_hex_dump(KERN_ERR, "key in @"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "key in @"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1); - #endif - -@@ -557,11 +753,14 @@ - DMA_TO_DEVICE); - if (dma_mapping_error(jrdev, ctx->key_dma)) { - dev_err(jrdev, "unable to map key i/o memory\n"); -- ret = -ENOMEM; -- goto map_err; -+ return -ENOMEM; - } -+ -+ dma_sync_single_for_device(jrdev, ctx->key_dma, ctx->split_key_pad_len, -+ DMA_TO_DEVICE); -+ - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "ctx.key@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "ctx.key@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, ctx->key, - ctx->split_key_pad_len, 1); - #endif -@@ -572,7 +771,6 @@ - DMA_TO_DEVICE); - } - --map_err: - kfree(hashed_key); - return ret; - badkey: -@@ -581,6 +779,25 @@ - return -EINVAL; - } - -+static int axcbc_setkey(struct crypto_ahash *ahash, -+ const u8 *key, unsigned int keylen) -+{ -+ struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); -+ int ret = 0; -+ -+ ctx->key_len = keylen; -+ memcpy(ctx->key, key, keylen); -+ -+#ifdef DEBUG -+ print_hex_dump(KERN_ERR, "ctx.key@"xstr(__LINE__)": ", -+ DUMP_PREFIX_ADDRESS, 16, 4, ctx->key, -+ ctx->key_len, 1); -+#endif -+ -+ ret = axcbc_set_sh_desc(ahash); -+ -+ return ret; -+} - /* - * ahash_edesc - s/w-extended ahash descriptor - * @dst_dma: physical mapped address of req->result -@@ -608,8 +825,11 @@ - if (edesc->src_nents) - dma_unmap_sg_chained(dev, req->src, edesc->src_nents, - DMA_TO_DEVICE, edesc->chained); -- if (edesc->dst_dma) -+ if (edesc->dst_dma) { -+ dma_sync_single_for_cpu(dev, edesc->dst_dma, dst_len, -+ DMA_FROM_DEVICE); - dma_unmap_single(dev, edesc->dst_dma, dst_len, DMA_FROM_DEVICE); -+ } - - if (edesc->sec4_sg_bytes) - dma_unmap_single(dev, edesc->sec4_sg_dma, -@@ -624,8 +844,12 @@ - struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); - struct caam_hash_state *state = ahash_request_ctx(req); - -- if (state->ctx_dma) -+ if (state->ctx_dma) { -+ if ((flag == DMA_FROM_DEVICE) || (flag == DMA_BIDIRECTIONAL)) -+ dma_sync_single_for_cpu(dev, state->ctx_dma, -+ ctx->ctx_len, flag); - dma_unmap_single(dev, state->ctx_dma, ctx->ctx_len, flag); -+ } - ahash_unmap(dev, edesc, req, dst_len); - } - -@@ -645,18 +869,21 @@ - - edesc = (struct ahash_edesc *)((char *)desc - - offsetof(struct ahash_edesc, hw_desc)); -- if (err) -- caam_jr_strstatus(jrdev, err); -+ if (err) { -+ char tmp[CAAM_ERROR_STR_MAX]; -+ -+ dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err)); -+ } - - ahash_unmap(jrdev, edesc, req, digestsize); - kfree(edesc); - - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "ctx@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "ctx@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx, - ctx->ctx_len, 1); - if (req->result) -- print_hex_dump(KERN_ERR, "result@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "result@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, req->result, - digestsize, 1); - #endif -@@ -680,18 +907,21 @@ - - edesc = (struct ahash_edesc *)((char *)desc - - offsetof(struct ahash_edesc, hw_desc)); -- if (err) -- caam_jr_strstatus(jrdev, err); -+ if (err) { -+ char tmp[CAAM_ERROR_STR_MAX]; -+ -+ dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err)); -+ } - - ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len, DMA_BIDIRECTIONAL); - kfree(edesc); - - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "ctx@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "ctx@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx, - ctx->ctx_len, 1); - if (req->result) -- print_hex_dump(KERN_ERR, "result@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "result@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, req->result, - digestsize, 1); - #endif -@@ -715,18 +945,21 @@ - - edesc = (struct ahash_edesc *)((char *)desc - - offsetof(struct ahash_edesc, hw_desc)); -- if (err) -- caam_jr_strstatus(jrdev, err); -+ if (err) { -+ char tmp[CAAM_ERROR_STR_MAX]; - -- ahash_unmap_ctx(jrdev, edesc, req, digestsize, DMA_TO_DEVICE); -+ dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err)); -+ } -+ -+ ahash_unmap_ctx(jrdev, edesc, req, digestsize, DMA_FROM_DEVICE); - kfree(edesc); - - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "ctx@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "ctx@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx, - ctx->ctx_len, 1); - if (req->result) -- print_hex_dump(KERN_ERR, "result@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "result@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, req->result, - digestsize, 1); - #endif -@@ -750,18 +983,21 @@ - - edesc = (struct ahash_edesc *)((char *)desc - - offsetof(struct ahash_edesc, hw_desc)); -- if (err) -- caam_jr_strstatus(jrdev, err); -+ if (err) { -+ char tmp[CAAM_ERROR_STR_MAX]; -+ -+ dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err)); -+ } - -- ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len, DMA_FROM_DEVICE); -+ ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len, DMA_TO_DEVICE); - kfree(edesc); - - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "ctx@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "ctx@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, state->caam_ctx, - ctx->ctx_len, 1); - if (req->result) -- print_hex_dump(KERN_ERR, "result@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "result@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, req->result, - digestsize, 1); - #endif -@@ -807,7 +1043,7 @@ - * allocate space for base edesc and hw desc commands, - * link tables - */ -- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN + -+ edesc = kzalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN + - sec4_sg_bytes, GFP_DMA | flags); - if (!edesc) { - dev_err(jrdev, -@@ -820,11 +1056,12 @@ - edesc->sec4_sg_bytes = sec4_sg_bytes; - edesc->sec4_sg = (void *)edesc + sizeof(struct ahash_edesc) + - DESC_JOB_IO_LEN; -+ edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg, -+ sec4_sg_bytes, -+ DMA_TO_DEVICE); - -- ret = ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len, -- edesc->sec4_sg, DMA_BIDIRECTIONAL); -- if (ret) -- return ret; -+ ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len, -+ edesc->sec4_sg, DMA_BIDIRECTIONAL); - - state->buf_dma = try_buf_map_to_sec4_sg(jrdev, - edesc->sec4_sg + 1, -@@ -851,21 +1088,16 @@ - init_job_desc_shared(desc, ptr, sh_len, HDR_SHARE_DEFER | - HDR_REVERSE); - -- edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg, -- sec4_sg_bytes, -- DMA_TO_DEVICE); -- if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) { -- dev_err(jrdev, "unable to map S/G table\n"); -- return -ENOMEM; -- } -- - append_seq_in_ptr(desc, edesc->sec4_sg_dma, ctx->ctx_len + - to_hash, LDST_SGF); - - append_seq_out_ptr(desc, state->ctx_dma, ctx->ctx_len, 0); - -+ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma, -+ sec4_sg_bytes, DMA_TO_DEVICE); -+ - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "jobdesc@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, desc, - desc_bytes(desc), 1); - #endif -@@ -885,9 +1117,9 @@ - *next_buflen = last_buflen; - } - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "buf@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "buf@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, buf, *buflen, 1); -- print_hex_dump(KERN_ERR, "next buf@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "next buf@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, next_buf, - *next_buflen, 1); - #endif -@@ -919,7 +1151,7 @@ - sec4_sg_bytes = sec4_sg_src_index * sizeof(struct sec4_sg_entry); - - /* allocate space for base edesc and hw desc commands, link tables */ -- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN + -+ edesc = kzalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN + - sec4_sg_bytes, GFP_DMA | flags); - if (!edesc) { - dev_err(jrdev, "could not allocate extended descriptor\n"); -@@ -933,37 +1165,29 @@ - edesc->sec4_sg_bytes = sec4_sg_bytes; - edesc->sec4_sg = (void *)edesc + sizeof(struct ahash_edesc) + - DESC_JOB_IO_LEN; -+ edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg, -+ sec4_sg_bytes, DMA_TO_DEVICE); - edesc->src_nents = 0; - -- ret = ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len, -- edesc->sec4_sg, DMA_TO_DEVICE); -- if (ret) -- return ret; -+ ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len, edesc->sec4_sg, -+ DMA_TO_DEVICE); - - state->buf_dma = try_buf_map_to_sec4_sg(jrdev, edesc->sec4_sg + 1, - buf, state->buf_dma, buflen, - last_buflen); - (edesc->sec4_sg + sec4_sg_src_index - 1)->len |= SEC4_SG_LEN_FIN; - -- edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg, -- sec4_sg_bytes, DMA_TO_DEVICE); -- if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) { -- dev_err(jrdev, "unable to map S/G table\n"); -- return -ENOMEM; -- } -- - append_seq_in_ptr(desc, edesc->sec4_sg_dma, ctx->ctx_len + buflen, - LDST_SGF); - - edesc->dst_dma = map_seq_out_ptr_result(desc, jrdev, req->result, - digestsize); -- if (dma_mapping_error(jrdev, edesc->dst_dma)) { -- dev_err(jrdev, "unable to map dst\n"); -- return -ENOMEM; -- } -+ -+ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma, sec4_sg_bytes, -+ DMA_TO_DEVICE); - - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "jobdesc@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1); - #endif - -@@ -1006,7 +1230,7 @@ - sizeof(struct sec4_sg_entry); - - /* allocate space for base edesc and hw desc commands, link tables */ -- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN + -+ edesc = kzalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN + - sec4_sg_bytes, GFP_DMA | flags); - if (!edesc) { - dev_err(jrdev, "could not allocate extended descriptor\n"); -@@ -1022,11 +1246,11 @@ - edesc->sec4_sg_bytes = sec4_sg_bytes; - edesc->sec4_sg = (void *)edesc + sizeof(struct ahash_edesc) + - DESC_JOB_IO_LEN; -+ edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg, -+ sec4_sg_bytes, DMA_TO_DEVICE); - -- ret = ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len, -- edesc->sec4_sg, DMA_TO_DEVICE); -- if (ret) -- return ret; -+ ctx_map_to_sec4_sg(desc, jrdev, state, ctx->ctx_len, edesc->sec4_sg, -+ DMA_TO_DEVICE); - - state->buf_dma = try_buf_map_to_sec4_sg(jrdev, edesc->sec4_sg + 1, - buf, state->buf_dma, buflen, -@@ -1035,25 +1259,17 @@ - src_map_to_sec4_sg(jrdev, req->src, src_nents, edesc->sec4_sg + - sec4_sg_src_index, chained); - -- edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg, -- sec4_sg_bytes, DMA_TO_DEVICE); -- if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) { -- dev_err(jrdev, "unable to map S/G table\n"); -- return -ENOMEM; -- } -- - append_seq_in_ptr(desc, edesc->sec4_sg_dma, ctx->ctx_len + - buflen + req->nbytes, LDST_SGF); - - edesc->dst_dma = map_seq_out_ptr_result(desc, jrdev, req->result, - digestsize); -- if (dma_mapping_error(jrdev, edesc->dst_dma)) { -- dev_err(jrdev, "unable to map dst\n"); -- return -ENOMEM; -- } -+ -+ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma, sec4_sg_bytes, -+ DMA_TO_DEVICE); - - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "jobdesc@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1); - #endif - -@@ -1092,7 +1308,7 @@ - sec4_sg_bytes = src_nents * sizeof(struct sec4_sg_entry); - - /* allocate space for base edesc and hw desc commands, link tables */ -- edesc = kmalloc(sizeof(struct ahash_edesc) + sec4_sg_bytes + -+ edesc = kzalloc(sizeof(struct ahash_edesc) + sec4_sg_bytes + - DESC_JOB_IO_LEN, GFP_DMA | flags); - if (!edesc) { - dev_err(jrdev, "could not allocate extended descriptor\n"); -@@ -1100,6 +1316,8 @@ - } - edesc->sec4_sg = (void *)edesc + sizeof(struct ahash_edesc) + - DESC_JOB_IO_LEN; -+ edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg, -+ sec4_sg_bytes, DMA_TO_DEVICE); - edesc->sec4_sg_bytes = sec4_sg_bytes; - edesc->src_nents = src_nents; - edesc->chained = chained; -@@ -1110,12 +1328,6 @@ - - if (src_nents) { - sg_to_sec4_sg_last(req->src, src_nents, edesc->sec4_sg, 0); -- edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg, -- sec4_sg_bytes, DMA_TO_DEVICE); -- if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) { -- dev_err(jrdev, "unable to map S/G table\n"); -- return -ENOMEM; -- } - src_dma = edesc->sec4_sg_dma; - options = LDST_SGF; - } else { -@@ -1124,15 +1336,14 @@ - } - append_seq_in_ptr(desc, src_dma, req->nbytes, options); - -+ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma, -+ edesc->sec4_sg_bytes, DMA_TO_DEVICE); -+ - edesc->dst_dma = map_seq_out_ptr_result(desc, jrdev, req->result, - digestsize); -- if (dma_mapping_error(jrdev, edesc->dst_dma)) { -- dev_err(jrdev, "unable to map dst\n"); -- return -ENOMEM; -- } - - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "jobdesc@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1); - #endif - -@@ -1166,7 +1377,7 @@ - int sh_len; - - /* allocate space for base edesc and hw desc commands, link tables */ -- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN, -+ edesc = kzalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN, - GFP_DMA | flags); - if (!edesc) { - dev_err(jrdev, "could not allocate extended descriptor\n"); -@@ -1179,23 +1390,17 @@ - init_job_desc_shared(desc, ptr, sh_len, HDR_SHARE_DEFER | HDR_REVERSE); - - state->buf_dma = dma_map_single(jrdev, buf, buflen, DMA_TO_DEVICE); -- if (dma_mapping_error(jrdev, state->buf_dma)) { -- dev_err(jrdev, "unable to map src\n"); -- return -ENOMEM; -- } - - append_seq_in_ptr(desc, state->buf_dma, buflen, 0); - - edesc->dst_dma = map_seq_out_ptr_result(desc, jrdev, req->result, - digestsize); -- if (dma_mapping_error(jrdev, edesc->dst_dma)) { -- dev_err(jrdev, "unable to map dst\n"); -- return -ENOMEM; -- } - edesc->src_nents = 0; - -+ dma_sync_single_for_device(jrdev, state->buf_dma, buflen, -+ DMA_TO_DEVICE); - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "jobdesc@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1); - #endif - -@@ -1246,7 +1451,7 @@ - * allocate space for base edesc and hw desc commands, - * link tables - */ -- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN + -+ edesc = kzalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN + - sec4_sg_bytes, GFP_DMA | flags); - if (!edesc) { - dev_err(jrdev, -@@ -1259,7 +1464,9 @@ - edesc->sec4_sg_bytes = sec4_sg_bytes; - edesc->sec4_sg = (void *)edesc + sizeof(struct ahash_edesc) + - DESC_JOB_IO_LEN; -- edesc->dst_dma = 0; -+ edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg, -+ sec4_sg_bytes, -+ DMA_TO_DEVICE); - - state->buf_dma = buf_map_to_sec4_sg(jrdev, edesc->sec4_sg, - buf, *buflen); -@@ -1277,22 +1484,14 @@ - init_job_desc_shared(desc, ptr, sh_len, HDR_SHARE_DEFER | - HDR_REVERSE); - -- edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg, -- sec4_sg_bytes, -- DMA_TO_DEVICE); -- if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) { -- dev_err(jrdev, "unable to map S/G table\n"); -- return -ENOMEM; -- } -- - append_seq_in_ptr(desc, edesc->sec4_sg_dma, to_hash, LDST_SGF); - -- ret = map_seq_out_ptr_ctx(desc, jrdev, state, ctx->ctx_len); -- if (ret) -- return ret; -+ map_seq_out_ptr_ctx(desc, jrdev, state, ctx->ctx_len); - -+ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma, -+ sec4_sg_bytes, DMA_TO_DEVICE); - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "jobdesc@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, desc, - desc_bytes(desc), 1); - #endif -@@ -1315,9 +1514,9 @@ - *next_buflen = 0; - } - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "buf@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "buf@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, buf, *buflen, 1); -- print_hex_dump(KERN_ERR, "next buf@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "next buf@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, next_buf, - *next_buflen, 1); - #endif -@@ -1353,7 +1552,7 @@ - sizeof(struct sec4_sg_entry); - - /* allocate space for base edesc and hw desc commands, link tables */ -- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN + -+ edesc = kzalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN + - sec4_sg_bytes, GFP_DMA | flags); - if (!edesc) { - dev_err(jrdev, "could not allocate extended descriptor\n"); -@@ -1369,6 +1568,8 @@ - edesc->sec4_sg_bytes = sec4_sg_bytes; - edesc->sec4_sg = (void *)edesc + sizeof(struct ahash_edesc) + - DESC_JOB_IO_LEN; -+ edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg, -+ sec4_sg_bytes, DMA_TO_DEVICE); - - state->buf_dma = try_buf_map_to_sec4_sg(jrdev, edesc->sec4_sg, buf, - state->buf_dma, buflen, -@@ -1377,25 +1578,17 @@ - src_map_to_sec4_sg(jrdev, req->src, src_nents, edesc->sec4_sg + 1, - chained); - -- edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg, -- sec4_sg_bytes, DMA_TO_DEVICE); -- if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) { -- dev_err(jrdev, "unable to map S/G table\n"); -- return -ENOMEM; -- } -- - append_seq_in_ptr(desc, edesc->sec4_sg_dma, buflen + - req->nbytes, LDST_SGF); - - edesc->dst_dma = map_seq_out_ptr_result(desc, jrdev, req->result, - digestsize); -- if (dma_mapping_error(jrdev, edesc->dst_dma)) { -- dev_err(jrdev, "unable to map dst\n"); -- return -ENOMEM; -- } -+ -+ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma, sec4_sg_bytes, -+ DMA_TO_DEVICE); - - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "jobdesc@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1); - #endif - -@@ -1448,7 +1641,7 @@ - * allocate space for base edesc and hw desc commands, - * link tables - */ -- edesc = kmalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN + -+ edesc = kzalloc(sizeof(struct ahash_edesc) + DESC_JOB_IO_LEN + - sec4_sg_bytes, GFP_DMA | flags); - if (!edesc) { - dev_err(jrdev, -@@ -1461,19 +1654,13 @@ - edesc->sec4_sg_bytes = sec4_sg_bytes; - edesc->sec4_sg = (void *)edesc + sizeof(struct ahash_edesc) + - DESC_JOB_IO_LEN; -- edesc->dst_dma = 0; -+ edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg, -+ sec4_sg_bytes, -+ DMA_TO_DEVICE); - - if (src_nents) { - sg_to_sec4_sg_last(req->src, src_nents, - edesc->sec4_sg, 0); -- edesc->sec4_sg_dma = dma_map_single(jrdev, -- edesc->sec4_sg, -- sec4_sg_bytes, -- DMA_TO_DEVICE); -- if (dma_mapping_error(jrdev, edesc->sec4_sg_dma)) { -- dev_err(jrdev, "unable to map S/G table\n"); -- return -ENOMEM; -- } - src_dma = edesc->sec4_sg_dma; - options = LDST_SGF; - } else { -@@ -1492,12 +1679,12 @@ - - append_seq_in_ptr(desc, src_dma, to_hash, options); - -- ret = map_seq_out_ptr_ctx(desc, jrdev, state, ctx->ctx_len); -- if (ret) -- return ret; -+ map_seq_out_ptr_ctx(desc, jrdev, state, ctx->ctx_len); - -+ dma_sync_single_for_device(jrdev, edesc->sec4_sg_dma, -+ sec4_sg_bytes, DMA_TO_DEVICE); - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "jobdesc@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, desc, - desc_bytes(desc), 1); - #endif -@@ -1522,7 +1709,7 @@ - req->nbytes, 0); - } - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "next buf@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "next buf@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, next_buf, - *next_buflen, 1); - #endif -@@ -1736,10 +1923,33 @@ - .alg_type = OP_ALG_ALGSEL_MD5, - .alg_op = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC, - }, -+ { -+ .name = "xcbc(aes)", -+ .driver_name = "xcbc-aes-caam", -+ .hmac_name = "xcbc(aes)", -+ .hmac_driver_name = "xcbc-aes-caam", -+ .blocksize = XCBC_MAC_BLOCK_WORDS * 4, -+ .template_ahash = { -+ .init = ahash_init, -+ .update = ahash_update, -+ .final = ahash_final, -+ .finup = ahash_finup, -+ .digest = ahash_digest, -+ .export = ahash_export, -+ .import = ahash_import, -+ .setkey = axcbc_setkey, -+ .halg = { -+ .digestsize = XCBC_MAC_DIGEST_SIZE, -+ }, -+ }, -+ .alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_XCBC_MAC, -+ .alg_op = OP_ALG_ALGSEL_AES, -+ }, - }; - - struct caam_hash_alg { - struct list_head entry; -+ struct device *ctrldev; - int alg_type; - int alg_op; - struct ahash_alg ahash_alg; -@@ -1756,6 +1966,7 @@ - struct caam_hash_alg *caam_hash = - container_of(alg, struct caam_hash_alg, ahash_alg); - struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm); -+ struct caam_drv_private *priv = dev_get_drvdata(caam_hash->ctrldev); - /* Sizes for MDHA running digests: MD5, SHA1, 224, 256, 384, 512 */ - static const u8 runninglen[] = { HASH_MSG_LEN + MD5_DIGEST_SIZE, - HASH_MSG_LEN + SHA1_DIGEST_SIZE, -@@ -1763,17 +1974,15 @@ - HASH_MSG_LEN + SHA256_DIGEST_SIZE, - HASH_MSG_LEN + 64, - HASH_MSG_LEN + SHA512_DIGEST_SIZE }; -+ int tgt_jr = atomic_inc_return(&priv->tfm_count); - int ret = 0; - - /* -- * Get a Job ring from Job Ring driver to ensure in-order -+ * distribute tfms across job rings to ensure in-order - * crypto request processing per tfm - */ -- ctx->jrdev = caam_jr_alloc(); -- if (IS_ERR(ctx->jrdev)) { -- pr_err("Job Ring Device allocation for transform failed\n"); -- return PTR_ERR(ctx->jrdev); -- } -+ ctx->jrdev = priv->jrdev[tgt_jr % priv->total_jobrs]; -+ - /* copy descriptor header template value */ - ctx->alg_type = OP_TYPE_CLASS2_ALG | caam_hash->alg_type; - ctx->alg_op = OP_TYPE_CLASS2_ALG | caam_hash->alg_op; -@@ -1789,6 +1998,39 @@ - return ret; - } - -+static int caam_axcbc_cra_init(struct crypto_tfm *tfm) -+{ -+ struct crypto_ahash *ahash = __crypto_ahash_cast(tfm); -+ struct crypto_alg *base = tfm->__crt_alg; -+ struct hash_alg_common *halg = -+ container_of(base, struct hash_alg_common, base); -+ struct ahash_alg *alg = -+ container_of(halg, struct ahash_alg, halg); -+ struct caam_hash_alg *caam_hash = -+ container_of(alg, struct caam_hash_alg, ahash_alg); -+ struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm); -+ struct caam_drv_private *priv = dev_get_drvdata(caam_hash->ctrldev); -+ int tgt_jr = atomic_inc_return(&priv->tfm_count); -+ int ret = 0; -+ -+ /* -+ * distribute tfms across job rings to ensure in-order -+ * crypto request processing per tfm -+ */ -+ ctx->jrdev = priv->jrdev[tgt_jr % priv->total_jobrs]; -+ -+ /* copy descriptor header template value */ -+ ctx->alg_type = OP_TYPE_CLASS1_ALG | caam_hash->alg_type; -+ ctx->alg_op = OP_TYPE_CLASS1_ALG | caam_hash->alg_op; -+ -+ crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm), -+ sizeof(struct caam_hash_state)); -+ -+ ret = axcbc_set_sh_desc(ahash); -+ -+ return ret; -+} -+ - static void caam_hash_cra_exit(struct crypto_tfm *tfm) - { - struct caam_hash_ctx *ctx = crypto_tfm_ctx(tfm); -@@ -1816,35 +2058,57 @@ - !dma_mapping_error(ctx->jrdev, ctx->sh_desc_finup_dma)) - dma_unmap_single(ctx->jrdev, ctx->sh_desc_finup_dma, - desc_bytes(ctx->sh_desc_finup), DMA_TO_DEVICE); -- -- caam_jr_free(ctx->jrdev); - } - - static void __exit caam_algapi_hash_exit(void) - { -+ struct device_node *dev_node; -+ struct platform_device *pdev; -+ struct device *ctrldev; -+ struct caam_drv_private *priv; - struct caam_hash_alg *t_alg, *n; - -- if (!hash_list.next) -+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); -+ if (!dev_node) { -+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0"); -+ if (!dev_node) -+ return; -+ } -+ -+ pdev = of_find_device_by_node(dev_node); -+ if (!pdev) { -+ of_node_put(dev_node); - return; -+ } - -- list_for_each_entry_safe(t_alg, n, &hash_list, entry) { -+ ctrldev = &pdev->dev; -+ priv = dev_get_drvdata(ctrldev); -+ -+ if (!priv->hash_list.next) { -+ of_node_put(dev_node); -+ return; -+ } -+ -+ list_for_each_entry_safe(t_alg, n, &priv->hash_list, entry) { - crypto_unregister_ahash(&t_alg->ahash_alg); - list_del(&t_alg->entry); - kfree(t_alg); - } -+ -+ of_node_put(dev_node); - } - - static struct caam_hash_alg * --caam_hash_alloc(struct caam_hash_template *template, -+caam_hash_alloc(struct device *ctrldev, struct caam_hash_template *template, - bool keyed) - { - struct caam_hash_alg *t_alg; - struct ahash_alg *halg; - struct crypto_alg *alg; - -- t_alg = kzalloc(sizeof(struct caam_hash_alg), GFP_KERNEL); -+ t_alg = kzalloc(sizeof(struct caam_hash_alg), GFP_ATOMIC); - if (!t_alg) { -- pr_err("failed to allocate t_alg\n"); -+ dev_err(ctrldev, "failed to allocate t_alg\n"); - return ERR_PTR(-ENOMEM); - } - -@@ -1864,7 +2128,11 @@ - template->driver_name); - } - alg->cra_module = THIS_MODULE; -- alg->cra_init = caam_hash_cra_init; -+ -+ if (strstr(alg->cra_name, "xcbc") > 0) -+ alg->cra_init = caam_axcbc_cra_init; -+ else -+ alg->cra_init = caam_hash_cra_init; - alg->cra_exit = caam_hash_cra_exit; - alg->cra_ctxsize = sizeof(struct caam_hash_ctx); - alg->cra_priority = CAAM_CRA_PRIORITY; -@@ -1875,6 +2143,7 @@ - - t_alg->alg_type = template->alg_type; - t_alg->alg_op = template->alg_op; -+ t_alg->ctrldev = ctrldev; - - return t_alg; - } -@@ -1884,8 +2153,9 @@ - struct device_node *dev_node; - struct platform_device *pdev; - struct device *ctrldev; -- void *priv; -- int i = 0, err = 0; -+ struct caam_drv_private *priv; -+ int i = 0, err = 0, md_limit = 0, md_inst; -+ u64 cha_inst; - - dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); - if (!dev_node) { -@@ -1899,60 +2169,68 @@ - of_node_put(dev_node); - return -ENODEV; - } -- - ctrldev = &pdev->dev; - priv = dev_get_drvdata(ctrldev); -- of_node_put(dev_node); - -- /* -- * If priv is NULL, it's probably because the caam driver wasn't -- * properly initialized (e.g. RNG4 init failed). Thus, bail out here. -- */ -- if (!priv) -- return -ENODEV; -+ INIT_LIST_HEAD(&priv->hash_list); - -- INIT_LIST_HEAD(&hash_list); -+ atomic_set(&priv->tfm_count, -1); -+ -+ /* register algorithms the device supports */ -+ cha_inst = rd_reg64(&priv->ctrl->perfmon.cha_num); -+ md_inst = (cha_inst & CHA_ID_MD_MASK) >> CHA_ID_MD_SHIFT; -+ if (md_inst) { -+ md_limit = SHA512_DIGEST_SIZE; -+ if ((rd_reg64(&priv->ctrl->perfmon.cha_id) & CHA_ID_MD_MASK) -+ == CHA_ID_MD_LP256) /* LP256 limits digest size */ -+ md_limit = SHA256_DIGEST_SIZE; -+ } - -- /* register crypto algorithms the device supports */ - for (i = 0; i < ARRAY_SIZE(driver_hash); i++) { -- /* TODO: check if h/w supports alg */ - struct caam_hash_alg *t_alg; - -+ /* If no MD instantiated, or MD too small, skip */ -+ if ((!md_inst) || -+ (driver_hash[i].template_ahash.halg.digestsize > -+ md_limit)) -+ continue; -+ - /* register hmac version */ -- t_alg = caam_hash_alloc(&driver_hash[i], true); -+ t_alg = caam_hash_alloc(ctrldev, &driver_hash[i], true); - if (IS_ERR(t_alg)) { - err = PTR_ERR(t_alg); -- pr_warn("%s alg allocation failed\n", -- driver_hash[i].driver_name); -+ dev_warn(ctrldev, "%s alg allocation failed\n", -+ driver_hash[i].driver_name); - continue; - } - - err = crypto_register_ahash(&t_alg->ahash_alg); - if (err) { -- pr_warn("%s alg registration failed\n", -+ dev_warn(ctrldev, "%s alg registration failed\n", - t_alg->ahash_alg.halg.base.cra_driver_name); - kfree(t_alg); - } else -- list_add_tail(&t_alg->entry, &hash_list); -+ list_add_tail(&t_alg->entry, &priv->hash_list); - - /* register unkeyed version */ -- t_alg = caam_hash_alloc(&driver_hash[i], false); -+ t_alg = caam_hash_alloc(ctrldev, &driver_hash[i], false); - if (IS_ERR(t_alg)) { - err = PTR_ERR(t_alg); -- pr_warn("%s alg allocation failed\n", -- driver_hash[i].driver_name); -+ dev_warn(ctrldev, "%s alg allocation failed\n", -+ driver_hash[i].driver_name); - continue; - } - - err = crypto_register_ahash(&t_alg->ahash_alg); - if (err) { -- pr_warn("%s alg registration failed\n", -+ dev_warn(ctrldev, "%s alg registration failed\n", - t_alg->ahash_alg.halg.base.cra_driver_name); - kfree(t_alg); - } else -- list_add_tail(&t_alg->entry, &hash_list); -+ list_add_tail(&t_alg->entry, &priv->hash_list); - } - -+ of_node_put(dev_node); - return err; - } - -diff -Nur linux-4.1.13.orig/drivers/crypto/caam/caam_keyblob.c linux-4.1.13/drivers/crypto/caam/caam_keyblob.c ---- linux-4.1.13.orig/drivers/crypto/caam/caam_keyblob.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/crypto/caam/caam_keyblob.c 2015-11-30 17:56:13.548139857 +0100 -@@ -0,0 +1,687 @@ -+/* -+ * Key blob driver based on CAAM hardware -+ * -+ * Copyright (C) 2015 Freescale Semiconductor, Inc. -+ */ -+ -+#include -+#include -+ -+#include "compat.h" -+#include "regs.h" -+#include "jr.h" -+#include "desc.h" -+#include "intern.h" -+#include "sm.h" -+#include "caam_keyblob.h" -+ -+#define INITIAL_DESCSZ 16 /* size of tmp buffer for descriptor const. */ -+ -+/** -+ * struct kb_device - the metadata of the caam key blob device node -+ * @dev: the actual misc device -+ */ -+struct kb_device { -+ struct miscdevice misc_dev; -+ struct device *jr_dev; -+}; -+ -+/* -+ * Pseudo-synchronous ring access functions for carrying out key -+ * encapsulation and decapsulation -+ */ -+ -+struct sm_key_job_result { -+ int error; -+ struct completion completion; -+}; -+ -+ -+static struct kb_device *kb_dev; -+ -+static struct kb_device *kb_device_create(void); -+static int kb_device_destroy(struct kb_device *kb_dev); -+static int kb_open(struct inode *inode, struct file *file); -+static int kb_release(struct inode *inode, struct file *file); -+static void sm_key_job_done(struct device *dev, u32 *desc, -+ u32 err, void *context); -+static int gen_mem_encap(struct device *jr_dev, void __user *secretbuf, -+ int keylen, void __user *kmodbuf, void __user *outbuf); -+static int gen_mem_decap(struct device *jr_dev, void __user *keyblobbuf, -+ int bloblen, void __user *kmodbuf, void __user *outbuf); -+static long kb_ioctl(struct file *file, unsigned int cmd, unsigned long arg); -+static int caam_keyblob_probe(struct platform_device *pdev); -+static int caam_keyblob_remove(struct platform_device *pdev); -+ -+static int kb_open(struct inode *inode, struct file *file) -+{ -+ struct miscdevice *miscdev = file->private_data; -+ struct kb_device *dev = container_of(miscdev, struct kb_device, misc_dev); -+ struct device *jr_dev; -+ -+ if (!dev->jr_dev) { -+ jr_dev = caam_jr_alloc(); -+ if (IS_ERR(jr_dev)) { -+ pr_err("Job Ring Device allocation for transform failed\n"); -+ return -ENOMEM; -+ } -+ pr_info("Allocate a job ring device\n"); -+ dev->jr_dev = jr_dev; -+ } -+ else { -+ pr_err("Already created a job ring device"); -+ return -EPERM; -+ } -+ -+ return 0; -+} -+ -+static int kb_release(struct inode *inode, struct file *file) -+{ -+ struct miscdevice *miscdev = file->private_data; -+ struct kb_device *dev = container_of(miscdev, struct kb_device, misc_dev); -+ -+ if (dev && dev->jr_dev) { -+ caam_jr_free(dev->jr_dev); -+ pr_info("Free a job ring device\n"); -+ dev->jr_dev = NULL; -+ } -+ return 0; -+} -+ -+static void sm_key_job_done(struct device *dev, u32 *desc, -+ u32 err, void *context) -+{ -+ struct sm_key_job_result *res = context; -+ -+ res->error = err; /* save off the error for postprocessing */ -+ complete(&res->completion); /* mark us complete */ -+} -+ -+/* -+ * Construct a blob encapsulation job descriptor -+ * -+ * This function dynamically constructs a blob encapsulation job descriptor -+ * from the following arguments: -+ * -+ * - desc pointer to a pointer to the descriptor generated by this -+ * function. Caller will be responsible to kfree() this -+ * descriptor after execution. -+ * - keymod Physical pointer to a key modifier, which must reside in a -+ * contiguous piece of memory. Modifier will be assumed to be -+ * 8 bytes long for a blob of type SM_SECMEM, or 16 bytes long -+ * for a blob of type SM_GENMEM (see blobtype argument). -+ * - secretbuf Physical pointer to a secret, normally a black or red key, -+ * possibly residing within an accessible secure memory page, -+ * of the secret to be encapsulated to an output blob. -+ * - outbuf Physical pointer to the destination buffer to receive the -+ * encapsulated output. This buffer will need to be 48 bytes -+ * larger than the input because of the added encapsulation data. -+ * The generated descriptor will account for the increase in size, -+ * but the caller must also account for this increase in the -+ * buffer allocator. -+ * - secretsz Size of input secret, in bytes. This is limited to 65536 -+ * less the size of blob overhead, since the length embeds into -+ * DECO pointer in/out instructions. -+ * - keycolor Determines if the source data is covered (black key) or -+ * plaintext (red key). RED_KEY or BLACK_KEY are defined in -+ * for this purpose. -+ * - blobtype Determine if encapsulated blob should be a secure memory -+ * blob (SM_SECMEM), with partition data embedded with key -+ * material, or a general memory blob (SM_GENMEM). -+ * - auth If BLACK_KEY source is covered via AES-CCM, specify -+ * KEY_COVER_CCM, else uses AES-ECB (KEY_COVER_ECB). -+ * -+ * Upon completion, desc points to a buffer containing a CAAM job -+ * descriptor which encapsulates data into an externally-storable blob -+ * suitable for use across power cycles. -+ * -+ * This is an example of a black key encapsulation job into a general memory -+ * blob. Notice the 16-byte key modifier in the LOAD instruction. Also note -+ * the output 48 bytes longer than the input: -+ * -+ * [00] B0800008 jobhdr: stidx=0 len=8 -+ * [01] 14400010 ld: ccb2-key len=16 offs=0 -+ * [02] 08144891 ptr->@0x08144891 -+ * [03] F800003A seqoutptr: len=58 -+ * [04] 01000000 out_ptr->@0x01000000 -+ * [05] F000000A seqinptr: len=10 -+ * [06] 09745090 in_ptr->@0x09745090 -+ * [07] 870D0004 operation: encap blob reg=memory, black, format=normal -+ * -+ * This is an example of a red key encapsulation job for storing a red key -+ * into a secure memory blob. Note the 8 byte modifier on the 12 byte offset -+ * in the LOAD instruction; this accounts for blob permission storage: -+ * -+ * [00] B0800008 jobhdr: stidx=0 len=8 -+ * [01] 14400C08 ld: ccb2-key len=8 offs=12 -+ * [02] 087D0784 ptr->@0x087d0784 -+ * [03] F8000050 seqoutptr: len=80 -+ * [04] 09251BB2 out_ptr->@0x09251bb2 -+ * [05] F0000020 seqinptr: len=32 -+ * [06] 40000F31 in_ptr->@0x40000f31 -+ * [07] 870D0008 operation: encap blob reg=memory, red, sec_mem, -+ * format=normal -+ * -+ * Note: this function only generates 32-bit pointers at present, and should -+ * be refactored using a scheme that allows both 32 and 64 bit addressing -+ */ -+ -+static int blob_encap_jobdesc(u32 **desc, dma_addr_t keymod, -+ void *secretbuf, dma_addr_t outbuf, -+ u16 secretsz, u8 keycolor, u8 blobtype, u8 auth) -+{ -+ u32 *tdesc, tmpdesc[INITIAL_DESCSZ]; -+ u16 dsize, idx; -+ -+ memset(tmpdesc, 0, INITIAL_DESCSZ * sizeof(u32)); -+ idx = 1; -+ -+ /* -+ * Key modifier works differently for secure/general memory blobs -+ * This accounts for the permission/protection data encapsulated -+ * within the blob if a secure memory blob is requested -+ */ -+ if (blobtype == SM_SECMEM) -+ tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB | -+ LDST_SRCDST_BYTE_KEY | -+ ((12 << LDST_OFFSET_SHIFT) & LDST_OFFSET_MASK) -+ | (8 & LDST_LEN_MASK); -+ else /* is general memory blob */ -+ tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB | -+ LDST_SRCDST_BYTE_KEY | (16 & LDST_LEN_MASK); -+ -+ tmpdesc[idx++] = (u32)keymod; -+ -+ /* -+ * Encapsulation output must include space for blob key encryption -+ * key and MAC tag -+ */ -+ tmpdesc[idx++] = CMD_SEQ_OUT_PTR | (secretsz + BLOB_OVERHEAD); -+ tmpdesc[idx++] = (u32)outbuf; -+ -+ /* Input data, should be somewhere in secure memory */ -+ tmpdesc[idx++] = CMD_SEQ_IN_PTR | secretsz; -+ tmpdesc[idx++] = (u32)secretbuf; -+ -+ /* Set blob encap, then color */ -+ tmpdesc[idx] = CMD_OPERATION | OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB; -+ -+ if (blobtype == SM_SECMEM) -+ tmpdesc[idx] |= OP_PCL_BLOB_PTXT_SECMEM; -+ -+ if (auth == KEY_COVER_CCM) -+ tmpdesc[idx] |= OP_PCL_BLOB_EKT; -+ -+ if (keycolor == BLACK_KEY) -+ tmpdesc[idx] |= OP_PCL_BLOB_BLACK; -+ -+ idx++; -+ tmpdesc[0] = CMD_DESC_HDR | HDR_ONE | (idx & HDR_DESCLEN_MASK); -+ dsize = idx * sizeof(u32); -+ -+ tdesc = kmalloc(dsize, GFP_KERNEL | GFP_DMA); -+ if (tdesc == NULL) -+ return 0; -+ -+ memcpy(tdesc, tmpdesc, dsize); -+ *desc = tdesc; -+ return dsize; -+} -+ -+/* -+ * Construct a blob decapsulation job descriptor -+ * -+ * This function dynamically constructs a blob decapsulation job descriptor -+ * from the following arguments: -+ * -+ * - desc pointer to a pointer to the descriptor generated by this -+ * function. Caller will be responsible to kfree() this -+ * descriptor after execution. -+ * - keymod Physical pointer to a key modifier, which must reside in a -+ * contiguous piece of memory. Modifier will be assumed to be -+ * 8 bytes long for a blob of type SM_SECMEM, or 16 bytes long -+ * for a blob of type SM_GENMEM (see blobtype argument). -+ * - blobbuf Physical pointer (into external memory) of the blob to -+ * be decapsulated. Blob must reside in a contiguous memory -+ * segment. -+ * - outbuf Physical pointer of the decapsulated output, possibly into -+ * a location within a secure memory page. Must be contiguous. -+ * - secretsz Size of encapsulated secret in bytes (not the size of the -+ * input blob). -+ * - keycolor Determines if decapsulated content is encrypted (BLACK_KEY) -+ * or left as plaintext (RED_KEY). -+ * - blobtype Determine if encapsulated blob should be a secure memory -+ * blob (SM_SECMEM), with partition data embedded with key -+ * material, or a general memory blob (SM_GENMEM). -+ * - auth If decapsulation path is specified by BLACK_KEY, then if -+ * AES-CCM is requested for key covering use KEY_COVER_CCM, else -+ * use AES-ECB (KEY_COVER_ECB). -+ * -+ * Upon completion, desc points to a buffer containing a CAAM job descriptor -+ * that decapsulates a key blob from external memory into a black (encrypted) -+ * key or red (plaintext) content. -+ * -+ * This is an example of a black key decapsulation job from a general memory -+ * blob. Notice the 16-byte key modifier in the LOAD instruction. -+ * -+ * [00] B0800008 jobhdr: stidx=0 len=8 -+ * [01] 14400010 ld: ccb2-key len=16 offs=0 -+ * [02] 08A63B7F ptr->@0x08a63b7f -+ * [03] F8000010 seqoutptr: len=16 -+ * [04] 01000000 out_ptr->@0x01000000 -+ * [05] F000003A seqinptr: len=58 -+ * [06] 01000010 in_ptr->@0x01000010 -+ * [07] 860D0004 operation: decap blob reg=memory, black, format=normal -+ * -+ * This is an example of a red key decapsulation job for restoring a red key -+ * from a secure memory blob. Note the 8 byte modifier on the 12 byte offset -+ * in the LOAD instruction: -+ * -+ * [00] B0800008 jobhdr: stidx=0 len=8 -+ * [01] 14400C08 ld: ccb2-key len=8 offs=12 -+ * [02] 01000000 ptr->@0x01000000 -+ * [03] F8000020 seqoutptr: len=32 -+ * [04] 400000E6 out_ptr->@0x400000e6 -+ * [05] F0000050 seqinptr: len=80 -+ * [06] 08F0C0EA in_ptr->@0x08f0c0ea -+ * [07] 860D0008 operation: decap blob reg=memory, red, sec_mem, -+ * format=normal -+ * -+ * Note: this function only generates 32-bit pointers at present, and should -+ * be refactored using a scheme that allows both 32 and 64 bit addressing -+ */ -+ -+static int blob_decap_jobdesc(u32 **desc, dma_addr_t keymod, dma_addr_t blobbuf, -+ u8 *outbuf, u16 secretsz, u8 keycolor, -+ u8 blobtype, u8 auth) -+{ -+ u32 *tdesc, tmpdesc[INITIAL_DESCSZ]; -+ u16 dsize, idx; -+ -+ memset(tmpdesc, 0, INITIAL_DESCSZ * sizeof(u32)); -+ idx = 1; -+ -+ /* Load key modifier */ -+ if (blobtype == SM_SECMEM) -+ tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB | -+ LDST_SRCDST_BYTE_KEY | -+ ((12 << LDST_OFFSET_SHIFT) & LDST_OFFSET_MASK) -+ | (8 & LDST_LEN_MASK); -+ else /* is general memory blob */ -+ tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB | -+ LDST_SRCDST_BYTE_KEY | (16 & LDST_LEN_MASK); -+ -+ tmpdesc[idx++] = (u32)keymod; -+ -+ /* Compensate BKEK + MAC tag over size of encapsulated secret */ -+ tmpdesc[idx++] = CMD_SEQ_IN_PTR | (secretsz + BLOB_OVERHEAD); -+ tmpdesc[idx++] = (u32)blobbuf; -+ tmpdesc[idx++] = CMD_SEQ_OUT_PTR | secretsz; -+ tmpdesc[idx++] = (u32)outbuf; -+ -+ /* Decapsulate from secure memory partition to black blob */ -+ tmpdesc[idx] = CMD_OPERATION | OP_TYPE_DECAP_PROTOCOL | OP_PCLID_BLOB; -+ -+ if (blobtype == SM_SECMEM) -+ tmpdesc[idx] |= OP_PCL_BLOB_PTXT_SECMEM; -+ -+ if (auth == KEY_COVER_CCM) -+ tmpdesc[idx] |= OP_PCL_BLOB_EKT; -+ -+ if (keycolor == BLACK_KEY) -+ tmpdesc[idx] |= OP_PCL_BLOB_BLACK; -+ -+ idx++; -+ tmpdesc[0] = CMD_DESC_HDR | HDR_ONE | (idx & HDR_DESCLEN_MASK); -+ dsize = idx * sizeof(u32); -+ -+ tdesc = kmalloc(dsize, GFP_KERNEL | GFP_DMA); -+ if (tdesc == NULL) -+ return 0; -+ -+ memcpy(tdesc, tmpdesc, dsize); -+ *desc = tdesc; -+ return dsize; -+} -+ -+ -+ -+static int gen_mem_encap(struct device *jr_dev, void __user *secretbuf, -+ int keylen, void __user *kmodbuf, void __user *outbuf) -+{ -+ int retval = 0; -+ u32 dsize; -+ u32 __iomem *encapdesc = NULL; -+ dma_addr_t secret_dma = 0, keymod_dma = 0, outbuf_dma = 0; -+ u8 __iomem *lsecret = NULL, *lkeymod = NULL, *loutbuf = NULL; -+ struct sm_key_job_result testres; -+ -+ /* Build/map/flush the scret */ -+ lsecret = kmalloc(keylen, GFP_KERNEL | GFP_DMA); -+ if (!lsecret) { -+ dev_err(jr_dev, "%s: can't alloc for key\n", __func__); -+ retval = -ENOMEM; -+ goto out; -+ } -+ if (copy_from_user(lsecret, secretbuf, keylen)) { -+ dev_err(jr_dev, "%s: can't Copy for key\n", __func__); -+ retval = -EFAULT; -+ goto out; -+ } -+ secret_dma = dma_map_single(jr_dev, lsecret, keylen, -+ DMA_TO_DEVICE); -+ -+ /* Build/map/flush the key modifier */ -+ lkeymod = kmalloc(GENMEM_KEYMOD_LEN, GFP_KERNEL | GFP_DMA); -+ if (!lkeymod) { -+ dev_err(jr_dev, "%s: can't alloc for keymod\n", __func__); -+ retval = -ENOMEM; -+ goto out; -+ } -+ if (copy_from_user(lkeymod, kmodbuf, GENMEM_KEYMOD_LEN)) { -+ dev_err(jr_dev, "%s: can't Copy for keymod\n", __func__); -+ retval = -EFAULT; -+ goto out; -+ } -+ keymod_dma = dma_map_single(jr_dev, lkeymod, GENMEM_KEYMOD_LEN, -+ DMA_TO_DEVICE); -+ -+ loutbuf = kmalloc(keylen + BLOB_OVERHEAD, GFP_KERNEL | GFP_DMA); -+ if (!lkeymod) { -+ dev_err(jr_dev, "%s: can't alloc for output\n", __func__); -+ retval = -ENOMEM; -+ goto out; -+ } -+ outbuf_dma = dma_map_single(jr_dev, loutbuf, keylen + BLOB_OVERHEAD, -+ DMA_FROM_DEVICE); -+ dsize = blob_encap_jobdesc(&encapdesc, keymod_dma, (void *)secret_dma, outbuf_dma, -+ keylen, RED_KEY, SM_GENMEM, KEY_COVER_ECB); -+ if (!dsize) { -+ dev_err(jr_dev, "can't alloc an encapsulation descriptor\n"); -+ retval = -ENOMEM; -+ goto out; -+ } -+ init_completion(&testres.completion); -+ -+ retval = caam_jr_enqueue(jr_dev, encapdesc, sm_key_job_done, -+ &testres); -+ if (!retval) { -+ wait_for_completion_interruptible(&testres.completion); -+ dev_info(jr_dev, "job ring return %d\n", testres.error); -+ if (!testres.error) { -+ dma_sync_single_for_cpu(jr_dev, outbuf_dma, keylen + BLOB_OVERHEAD, -+ DMA_FROM_DEVICE); -+ -+ if (copy_to_user(outbuf, loutbuf, keylen + BLOB_OVERHEAD)) { -+ retval = -EFAULT; -+ dev_err(jr_dev, "can't copy for output\n"); -+ goto out; -+ } -+ } -+ retval = testres.error; -+ } -+ -+out: -+ if (outbuf_dma) -+ dma_unmap_single(jr_dev, outbuf_dma, keylen + BLOB_OVERHEAD, -+ DMA_FROM_DEVICE); -+ if (keymod_dma) -+ dma_unmap_single(jr_dev, keymod_dma, GENMEM_KEYMOD_LEN, DMA_TO_DEVICE); -+ if (secret_dma) -+ dma_unmap_single(jr_dev, secret_dma, keylen, DMA_TO_DEVICE); -+ kfree(encapdesc); -+ kfree(lkeymod); -+ kfree(lsecret); -+ kfree(loutbuf); -+ -+ return retval; -+} -+ -+static int gen_mem_decap(struct device *jr_dev, void __user *keyblobbuf, -+ int bloblen, void __user *kmodbuf, void __user *outbuf) -+{ -+ int retval = 0; -+ int keylen = bloblen - BLOB_OVERHEAD; -+ u32 dsize; -+ dma_addr_t keyblob_dma = 0, keymod_dma = 0, outbuf_dma = 0; -+ u8 __iomem *lkeyblob = NULL, *lkeymod = NULL, *loutbuf = NULL; -+ struct sm_key_job_result testres; -+ u32 __iomem *decapdesc = NULL; -+ -+ /* Build/map/flush the scret */ -+ lkeyblob = kmalloc(bloblen, GFP_KERNEL | GFP_DMA); -+ if (!lkeyblob) { -+ dev_err(jr_dev, "%s: can't alloc for keylob\n", __func__); -+ retval = -ENOMEM; -+ goto out; -+ } -+ if (copy_from_user(lkeyblob, keyblobbuf, bloblen)) { -+ dev_err(jr_dev, "%s: can't Copy for keyblob\n", __func__); -+ retval = -EFAULT; -+ goto out; -+ } -+ keyblob_dma = dma_map_single(jr_dev, lkeyblob, bloblen, -+ DMA_TO_DEVICE); -+ -+ /* Build/map/flush the key modifier */ -+ lkeymod = kmalloc(GENMEM_KEYMOD_LEN, GFP_KERNEL | GFP_DMA); -+ if (!lkeymod) { -+ dev_err(jr_dev, "%s: can't alloc for keymod\n", __func__); -+ retval = -ENOMEM; -+ goto out; -+ } -+ if (copy_from_user(lkeymod, kmodbuf, GENMEM_KEYMOD_LEN)) { -+ dev_err(jr_dev, "%s: can't Copy for keymod\n", __func__); -+ retval = -EFAULT; -+ goto out; -+ } -+ keymod_dma = dma_map_single(jr_dev, lkeymod, GENMEM_KEYMOD_LEN, -+ DMA_TO_DEVICE); -+ -+ loutbuf = kmalloc(keylen, GFP_KERNEL | GFP_DMA); -+ if (!loutbuf) { -+ dev_err(jr_dev, "%s: can't alloc for outbuf\n", __func__); -+ retval = -ENOMEM; -+ goto out; -+ } -+ outbuf_dma = dma_map_single(jr_dev, loutbuf, keylen, -+ DMA_FROM_DEVICE); -+ -+ /* Build the encapsulation job descriptor */ -+ dsize = blob_decap_jobdesc(&decapdesc, keymod_dma, keyblob_dma, (u8 *)outbuf_dma, -+ keylen, RED_KEY, SM_GENMEM, KEY_COVER_ECB); -+ if (!dsize) { -+ dev_err(jr_dev, "can't alloc a decapsulation descriptor\n"); -+ retval = -ENOMEM; -+ goto out; -+ } -+ -+ init_completion(&testres.completion); -+ -+ retval = caam_jr_enqueue(jr_dev, decapdesc, sm_key_job_done, -+ &testres); -+ if (!retval) { -+ wait_for_completion_interruptible(&testres.completion); -+ dev_info(jr_dev, "job ring return %d\n", testres.error); -+ if (!testres.error) { -+ dma_sync_single_for_cpu(jr_dev, outbuf_dma, keylen, -+ DMA_FROM_DEVICE); -+ -+ if (copy_to_user(outbuf, loutbuf, keylen)) { -+ retval = -EFAULT; -+ goto out; -+ } -+ } -+ retval = testres.error; -+ } -+ -+out: -+ if (outbuf_dma) -+ dma_unmap_single(jr_dev, outbuf_dma, keylen, -+ DMA_FROM_DEVICE); -+ if (keymod_dma) -+ dma_unmap_single(jr_dev, keymod_dma, GENMEM_KEYMOD_LEN, -+ DMA_TO_DEVICE); -+ if (keyblob_dma) -+ dma_unmap_single(jr_dev, keyblob_dma, bloblen, -+ DMA_TO_DEVICE); -+ kfree(decapdesc); -+ kfree(lkeymod); -+ kfree(lkeyblob); -+ kfree(loutbuf); -+ -+ return retval; -+} -+ -+ -+static long kb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) -+{ -+ int retval = 0; -+ struct caam_kb_data kb_data; -+ struct miscdevice *miscdev = file->private_data; -+ struct kb_device *dev = container_of(miscdev, struct kb_device, misc_dev); -+ -+ if (copy_from_user(&kb_data, (void *)arg, sizeof(kb_data))) { -+ retval = -EFAULT; -+ goto err; -+ } -+ -+ if (!kb_data.rawkey || !kb_data.keyblob || -+ (kb_data.rawkey_len + BLOB_OVERHEAD != kb_data.keyblob_len) || -+ (kb_data.keymod_len != GENMEM_KEYMOD_LEN)) { -+ retval = -EINVAL; -+ goto err; -+ } -+ -+ printk(KERN_INFO"%s:rawkey_len %d, keyblob_len %d\n", -+ __func__, kb_data.rawkey_len, kb_data.keyblob_len); -+ -+ switch (cmd) { -+ case CAAM_KB_ENCRYPT: -+ { -+ retval = gen_mem_encap(dev->jr_dev, kb_data.rawkey, kb_data.rawkey_len, -+ kb_data.keymod, kb_data.keyblob); -+ break; -+ } -+ case CAAM_KB_DECRYPT: -+ { -+ retval = gen_mem_decap(dev->jr_dev, kb_data.keyblob, kb_data.keyblob_len, -+ kb_data.keymod, kb_data.rawkey); -+ break; -+ } -+ default: -+ return -ENOTTY; -+ } -+ -+err: -+ return retval; -+} -+ -+static const struct file_operations kb_fops = { -+ .owner = THIS_MODULE, -+ .open = kb_open, -+ .release = kb_release, -+ .unlocked_ioctl = kb_ioctl, -+}; -+ -+static struct kb_device *kb_device_create(void) -+{ -+ struct kb_device *idev; -+ int ret; -+ -+ idev = kzalloc(sizeof(struct kb_device), GFP_KERNEL); -+ if (!idev) -+ return ERR_PTR(-ENOMEM); -+ -+ idev->misc_dev.minor = MISC_DYNAMIC_MINOR; -+ idev->misc_dev.name = "caam_kb"; -+ idev->misc_dev.fops = &kb_fops; -+ idev->misc_dev.parent = NULL; -+ ret = misc_register(&idev->misc_dev); -+ if (ret) { -+ pr_err("ion: failed to register misc device.\n"); -+ return ERR_PTR(ret); -+ } -+ -+ return idev; -+} -+ -+static int kb_device_destroy(struct kb_device *kb_dev) -+{ -+ if ((kb_dev) && (kb_dev->jr_dev)) { -+ caam_jr_free(kb_dev->jr_dev); -+ kb_dev->jr_dev = NULL; -+ } -+ -+ if (kb_dev) -+ misc_deregister(&kb_dev->misc_dev); -+ -+ return 0; -+} -+/* -+ * Probe key blob device -+ */ -+static int caam_keyblob_probe(struct platform_device *pdev) -+{ -+ int err; -+ -+ dev_dbg(&pdev->dev, "%s enter\n", __func__); -+ kb_dev = kb_device_create(); -+ if (IS_ERR_OR_NULL(kb_dev)) { -+ err = PTR_ERR(kb_dev); -+ goto err; -+ } -+ return 0; -+err: -+ return err; -+} -+ -+/* -+ * Remove key blob device -+ */ -+static int caam_keyblob_remove(struct platform_device *pdev) -+{ -+ kb_device_destroy(kb_dev); -+ return 0; -+} -+ -+static struct of_device_id caam_keyblob_match[] = { -+ { -+ .compatible = "fsl,sec-v4.0-keyblob", -+ }, -+ { -+ .compatible = "fsl,sec4.0-keyblob", -+ }, -+ {}, -+}; -+ -+MODULE_DEVICE_TABLE(of, caam_keyblob_match); -+ -+static struct platform_driver caam_keyblob_driver = { -+ .driver = { -+ .name = "caam_keyblob", -+ .owner = THIS_MODULE, -+ .of_match_table = caam_keyblob_match, -+ }, -+ .probe = caam_keyblob_probe, -+ .remove = caam_keyblob_remove, -+}; -+ -+static int __init keyblob_driver_init(void) -+{ -+ return platform_driver_register(&caam_keyblob_driver); -+} -+ -+static void __exit keyblob_driver_exit(void) -+{ -+ platform_driver_unregister(&caam_keyblob_driver); -+} -+ -+module_init(keyblob_driver_init); -+module_exit(keyblob_driver_exit); -+ -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_DESCRIPTION("FSL CAAM Secure Memory / Keystore"); -+MODULE_AUTHOR("Freescale Semiconductor - NMSG/MAD"); -diff -Nur linux-4.1.13.orig/drivers/crypto/caam/caam_keyblob.h linux-4.1.13/drivers/crypto/caam/caam_keyblob.h ---- linux-4.1.13.orig/drivers/crypto/caam/caam_keyblob.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/crypto/caam/caam_keyblob.h 2015-11-30 17:56:13.548139857 +0100 -@@ -0,0 +1,45 @@ -+/* -+ * CAAM public-level include definitions for the key blob -+ * -+ * Copyright (C) 2015 Freescale Semiconductor, Inc. -+ */ -+ -+#ifndef CAAM_KEYBLOB_H -+#define CAAM_KEYBLOB_H -+ -+ -+#include -+#include -+ -+struct caam_kb_data { -+ char *rawkey; -+ size_t rawkey_len; -+ char *keyblob; -+ size_t keyblob_len; -+ char *keymod; -+ size_t keymod_len; -+}; -+ -+ -+#define CAAM_KB_MAGIC 'I' -+ -+/** -+ * DOC: CAAM_KB_ENCRYPT - generate a key blob from raw key -+ * -+ * Takes an caam_kb_data struct and returns it with the key blob -+ */ -+#define CAAM_KB_ENCRYPT _IOWR(CAAM_KB_MAGIC, 0, \ -+ struct caam_kb_data) -+ -+/** -+ * DOC: CAAM_KB_DECRYPT - get keys from a key blob -+ * -+ * Takes an caam_kb_data struct and returns it with the raw key. -+ */ -+#define CAAM_KB_DECRYPT _IOWR(CAAM_KB_MAGIC, 1, struct caam_kb_data) -+ -+#ifndef GENMEM_KEYMOD_LEN -+#define GENMEM_KEYMOD_LEN 16 -+#endif -+ -+#endif /* CAAM_KEYBLOB_H */ -diff -Nur linux-4.1.13.orig/drivers/crypto/caam/caamrng.c linux-4.1.13/drivers/crypto/caam/caamrng.c ---- linux-4.1.13.orig/drivers/crypto/caam/caamrng.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/crypto/caam/caamrng.c 2015-11-30 17:56:13.548139857 +0100 -@@ -1,7 +1,7 @@ - /* - * caam - Freescale FSL CAAM support for hw_random - * -- * Copyright 2011 Freescale Semiconductor, Inc. -+ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. - * - * Based on caamalg.c crypto API driver. - * -@@ -80,9 +80,12 @@ - - static inline void rng_unmap_buf(struct device *jrdev, struct buf_data *bd) - { -- if (bd->addr) -+ if (bd->addr) { -+ dma_sync_single_for_cpu(jrdev, bd->addr, RN_BUF_SIZE, -+ DMA_FROM_DEVICE); - dma_unmap_single(jrdev, bd->addr, RN_BUF_SIZE, - DMA_FROM_DEVICE); -+ } - } - - static inline void rng_unmap_ctx(struct caam_rng_ctx *ctx) -@@ -103,11 +106,18 @@ - bd = (struct buf_data *)((char *)desc - - offsetof(struct buf_data, hw_desc)); - -- if (err) -- caam_jr_strstatus(jrdev, err); -+ if (err) { -+ char tmp[CAAM_ERROR_STR_MAX]; -+ -+ dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err)); -+ } - - atomic_set(&bd->empty, BUF_NOT_EMPTY); - complete(&bd->filled); -+ -+ /* Buffer refilled, invalidate cache */ -+ dma_sync_single_for_cpu(jrdev, bd->addr, RN_BUF_SIZE, DMA_FROM_DEVICE); -+ - #ifdef DEBUG - print_hex_dump(KERN_ERR, "rng refreshed buf@: ", - DUMP_PREFIX_ADDRESS, 16, 4, bd->buf, RN_BUF_SIZE, 1); -@@ -185,7 +195,7 @@ - max - copied_idx, false); - } - --static inline int rng_create_sh_desc(struct caam_rng_ctx *ctx) -+static inline void rng_create_sh_desc(struct caam_rng_ctx *ctx) - { - struct device *jrdev = ctx->jrdev; - u32 *desc = ctx->sh_desc; -@@ -203,18 +213,16 @@ - - ctx->sh_desc_dma = dma_map_single(jrdev, desc, desc_bytes(desc), - DMA_TO_DEVICE); -- if (dma_mapping_error(jrdev, ctx->sh_desc_dma)) { -- dev_err(jrdev, "unable to map shared descriptor\n"); -- return -ENOMEM; -- } -+ dma_sync_single_for_device(jrdev, ctx->sh_desc_dma, desc_bytes(desc), -+ DMA_TO_DEVICE); -+ - #ifdef DEBUG - print_hex_dump(KERN_ERR, "rng shdesc@: ", DUMP_PREFIX_ADDRESS, 16, 4, - desc, desc_bytes(desc), 1); - #endif -- return 0; - } - --static inline int rng_create_job_desc(struct caam_rng_ctx *ctx, int buf_id) -+static inline void rng_create_job_desc(struct caam_rng_ctx *ctx, int buf_id) - { - struct device *jrdev = ctx->jrdev; - struct buf_data *bd = &ctx->bufs[buf_id]; -@@ -225,17 +233,12 @@ - HDR_REVERSE); - - bd->addr = dma_map_single(jrdev, bd->buf, RN_BUF_SIZE, DMA_FROM_DEVICE); -- if (dma_mapping_error(jrdev, bd->addr)) { -- dev_err(jrdev, "unable to map dst\n"); -- return -ENOMEM; -- } - - append_seq_out_ptr_intlen(desc, bd->addr, RN_BUF_SIZE, 0); - #ifdef DEBUG - print_hex_dump(KERN_ERR, "rng job desc@: ", DUMP_PREFIX_ADDRESS, 16, 4, - desc, desc_bytes(desc), 1); - #endif -- return 0; - } - - static void caam_cleanup(struct hwrng *rng) -@@ -252,44 +255,67 @@ - rng_unmap_ctx(rng_ctx); - } - --static int caam_init_buf(struct caam_rng_ctx *ctx, int buf_id) -+#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST -+static inline void test_len(struct hwrng *rng, size_t len, bool wait) - { -- struct buf_data *bd = &ctx->bufs[buf_id]; -- int err; -+ u8 *buf; -+ int real_len; - -- err = rng_create_job_desc(ctx, buf_id); -- if (err) -- return err; -+ buf = kzalloc(sizeof(u8) * len, GFP_KERNEL); -+ real_len = rng->read(rng, buf, len, wait); -+ if (real_len == 0 && wait) -+ pr_err("WAITING FAILED\n"); -+ pr_info("wanted %d bytes, got %d\n", len, real_len); -+ print_hex_dump(KERN_INFO, "random bytes@: ", DUMP_PREFIX_ADDRESS, -+ 16, 4, buf, real_len, 1); -+ kfree(buf); -+} - -- atomic_set(&bd->empty, BUF_EMPTY); -- submit_job(ctx, buf_id == ctx->current_buf); -- wait_for_completion(&bd->filled); -+static inline void test_mode_once(struct hwrng *rng, bool wait) -+{ -+#define TEST_CHUNK (RN_BUF_SIZE / 4) - -- return 0; -+ test_len(rng, TEST_CHUNK, wait); -+ test_len(rng, RN_BUF_SIZE * 2, wait); -+ test_len(rng, RN_BUF_SIZE * 2 - TEST_CHUNK, wait); - } - --static int caam_init_rng(struct caam_rng_ctx *ctx, struct device *jrdev) -+static inline void test_mode(struct hwrng *rng, bool wait) - { -- int err; -- -- ctx->jrdev = jrdev; -+#define TEST_PASS 1 -+ int i; - -- err = rng_create_sh_desc(ctx); -- if (err) -- return err; -+ for (i = 0; i < TEST_PASS; i++) -+ test_mode_once(rng, wait); -+} - -- ctx->current_buf = 0; -- ctx->cur_buf_idx = 0; -+static void self_test(struct hwrng *rng) -+{ -+ pr_info("testing without waiting\n"); -+ test_mode(rng, false); -+ pr_info("testing with waiting\n"); -+ test_mode(rng, true); -+} -+#endif - -- err = caam_init_buf(ctx, 0); -- if (err) -- return err; -+static void caam_init_buf(struct caam_rng_ctx *ctx, int buf_id) -+{ -+ struct buf_data *bd = &ctx->bufs[buf_id]; - -- err = caam_init_buf(ctx, 1); -- if (err) -- return err; -+ rng_create_job_desc(ctx, buf_id); -+ atomic_set(&bd->empty, BUF_EMPTY); -+ submit_job(ctx, buf_id == ctx->current_buf); -+ wait_for_completion(&bd->filled); -+} - -- return 0; -+static void caam_init_rng(struct caam_rng_ctx *ctx, struct device *jrdev) -+{ -+ ctx->jrdev = jrdev; -+ rng_create_sh_desc(ctx); -+ ctx->current_buf = 0; -+ ctx->cur_buf_idx = 0; -+ caam_init_buf(ctx, 0); -+ caam_init_buf(ctx, 1); - } - - static struct hwrng caam_rng = { -@@ -300,19 +326,15 @@ - - static void __exit caam_rng_exit(void) - { -- caam_jr_free(rng_ctx->jrdev); - hwrng_unregister(&caam_rng); -- kfree(rng_ctx); - } - - static int __init caam_rng_init(void) - { -- struct device *dev; - struct device_node *dev_node; - struct platform_device *pdev; - struct device *ctrldev; -- void *priv; -- int err; -+ struct caam_drv_private *priv; - - dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); - if (!dev_node) { -@@ -322,35 +344,26 @@ - } - - pdev = of_find_device_by_node(dev_node); -- if (!pdev) { -- of_node_put(dev_node); -+ if (!pdev) - return -ENODEV; -- } - - ctrldev = &pdev->dev; - priv = dev_get_drvdata(ctrldev); - of_node_put(dev_node); - -- /* -- * If priv is NULL, it's probably because the caam driver wasn't -- * properly initialized (e.g. RNG4 init failed). Thus, bail out here. -- */ -- if (!priv) -+ /* Check RNG present in hardware before registration */ -+ if (!(rd_reg64(&priv->ctrl->perfmon.cha_num) & CHA_ID_RNG_MASK)) - return -ENODEV; - -- dev = caam_jr_alloc(); -- if (IS_ERR(dev)) { -- pr_err("Job Ring Device allocation for transform failed\n"); -- return PTR_ERR(dev); -- } -- rng_ctx = kmalloc(sizeof(struct caam_rng_ctx), GFP_DMA); -- if (!rng_ctx) -- return -ENOMEM; -- err = caam_init_rng(rng_ctx, dev); -- if (err) -- return err; -+ rng_ctx = kmalloc(sizeof(struct caam_rng_ctx), GFP_KERNEL | GFP_DMA); -+ -+ caam_init_rng(rng_ctx, priv->jrdev[0]); -+ -+#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST -+ self_test(&caam_rng); -+#endif - -- dev_info(dev, "registering rng-caam\n"); -+ dev_info(priv->jrdev[0], "registering rng-caam\n"); - return hwrng_register(&caam_rng); - } - -diff -Nur linux-4.1.13.orig/drivers/crypto/caam/compat.h linux-4.1.13/drivers/crypto/caam/compat.h ---- linux-4.1.13.orig/drivers/crypto/caam/compat.h 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/crypto/caam/compat.h 2015-11-30 17:56:13.548139857 +0100 -@@ -14,6 +14,8 @@ - #include - #include - #include -+#include -+#include - #include - #include - #include -@@ -23,12 +25,15 @@ - #include - #include - #include -+#include -+ -+#ifdef CONFIG_ARM /* needs the clock control subsystem */ -+#include -+#endif - #include - - #include --#include - #include --#include - #include - #include - #include -diff -Nur linux-4.1.13.orig/drivers/crypto/caam/ctrl.c linux-4.1.13/drivers/crypto/caam/ctrl.c ---- linux-4.1.13.orig/drivers/crypto/caam/ctrl.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/crypto/caam/ctrl.c 2015-11-30 17:56:13.548139857 +0100 -@@ -1,405 +1,260 @@ --/* * CAAM control-plane driver backend -+/* -+ * CAAM control-plane driver backend - * Controller-level driver, kernel property detection, initialization - * -- * Copyright 2008-2012 Freescale Semiconductor, Inc. -+ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc. - */ - --#include --#include --#include -- - #include "compat.h" - #include "regs.h" - #include "intern.h" - #include "jr.h" - #include "desc_constr.h" - #include "error.h" -+#include "ctrl.h" -+#include "sm.h" -+#include - --/* -- * Descriptor to instantiate RNG State Handle 0 in normal mode and -- * load the JDKEK, TDKEK and TDSK registers -- */ --static void build_instantiation_desc(u32 *desc, int handle, int do_sk) --{ -- u32 *jump_cmd, op_flags; -- -- init_job_desc(desc, 0); -- -- op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | -- (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT; -- -- /* INIT RNG in non-test mode */ -- append_operation(desc, op_flags); -- -- if (!handle && do_sk) { -- /* -- * For SH0, Secure Keys must be generated as well -- */ -+/* Used to capture the array of job rings */ -+struct device **caam_jr_dev; - -- /* wait for done */ -- jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1); -- set_jump_tgt_here(desc, jump_cmd); -+static int caam_remove(struct platform_device *pdev) -+{ -+ struct device *ctrldev; -+ struct caam_drv_private *ctrlpriv; -+ struct caam_drv_private_jr *jrpriv; -+ struct caam_full __iomem *topregs; -+ int ring, ret = 0; - -- /* -- * load 1 to clear written reg: -- * resets the done interrrupt and returns the RNG to idle. -- */ -- append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW); -+ ctrldev = &pdev->dev; -+ ctrlpriv = dev_get_drvdata(ctrldev); -+ topregs = (struct caam_full __iomem *)ctrlpriv->ctrl; - -- /* Initialize State Handle */ -- append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | -- OP_ALG_AAI_RNG4_SK); -+ /* shut down JobRs */ -+ for (ring = 0; ring < ctrlpriv->total_jobrs; ring++) { -+ ret |= caam_jr_shutdown(ctrlpriv->jrdev[ring]); -+ jrpriv = dev_get_drvdata(ctrlpriv->jrdev[ring]); -+ irq_dispose_mapping(jrpriv->irq); - } - -- append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT); --} -+ /* Shut down debug views */ -+#ifdef CONFIG_DEBUG_FS -+ debugfs_remove_recursive(ctrlpriv->dfs_root); -+#endif - --/* Descriptor for deinstantiation of State Handle 0 of the RNG block. */ --static void build_deinstantiation_desc(u32 *desc, int handle) --{ -- init_job_desc(desc, 0); -+ /* Unmap controller region */ -+ iounmap(&topregs->ctrl); - -- /* Uninstantiate State Handle 0 */ -- append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | -- (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL); -+#ifdef CONFIG_ARM -+ /* shut clocks off before finalizing shutdown */ -+ clk_disable(ctrlpriv->caam_ipg); -+ clk_disable(ctrlpriv->caam_mem); -+ clk_disable(ctrlpriv->caam_aclk); -+#endif -+ -+ kfree(ctrlpriv->jrdev); -+ kfree(ctrlpriv); - -- append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT); -+ return ret; - } - - /* -- * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of -- * the software (no JR/QI used). -- * @ctrldev - pointer to device -- * @status - descriptor status, after being run -- * -- * Return: - 0 if no error occurred -- * - -ENODEV if the DECO couldn't be acquired -- * - -EAGAIN if an error occurred while executing the descriptor -+ * Descriptor to instantiate RNG State Handle 0 in normal mode and -+ * load the JDKEK, TDKEK and TDSK registers - */ --static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc, -- u32 *status) -+static void build_instantiation_desc(u32 *desc) - { -- struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); -- struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl; -- struct caam_deco __iomem *deco = ctrlpriv->deco; -- unsigned int timeout = 100000; -- u32 deco_dbg_reg, flags; -- int i; -- -+ u32 *jump_cmd; - -- if (ctrlpriv->virt_en == 1) { -- setbits32(&ctrl->deco_rsr, DECORSR_JR0); -- -- while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) && -- --timeout) -- cpu_relax(); -- -- timeout = 100000; -- } -- -- setbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE); -- -- while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) && -- --timeout) -- cpu_relax(); -+ init_job_desc(desc, 0); - -- if (!timeout) { -- dev_err(ctrldev, "failed to acquire DECO 0\n"); -- clrbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE); -- return -ENODEV; -- } -+ /* INIT RNG in non-test mode */ -+ append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | -+ OP_ALG_AS_INIT); - -- for (i = 0; i < desc_len(desc); i++) -- wr_reg32(&deco->descbuf[i], *(desc + i)); -+ /* wait for done */ -+ jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1); -+ set_jump_tgt_here(desc, jump_cmd); - -- flags = DECO_JQCR_WHL; - /* -- * If the descriptor length is longer than 4 words, then the -- * FOUR bit in JRCTRL register must be set. -+ * load 1 to clear written reg: -+ * resets the done interrupt and returns the RNG to idle. - */ -- if (desc_len(desc) >= 4) -- flags |= DECO_JQCR_FOUR; -+ append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW); - -- /* Instruct the DECO to execute it */ -- wr_reg32(&deco->jr_ctl_hi, flags); -- -- timeout = 10000000; -- do { -- deco_dbg_reg = rd_reg32(&deco->desc_dbg); -- /* -- * If an error occured in the descriptor, then -- * the DECO status field will be set to 0x0D -- */ -- if ((deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) == -- DESC_DBG_DECO_STAT_HOST_ERR) -- break; -- cpu_relax(); -- } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout); -- -- *status = rd_reg32(&deco->op_status_hi) & -- DECO_OP_STATUS_HI_ERR_MASK; -- -- if (ctrlpriv->virt_en == 1) -- clrbits32(&ctrl->deco_rsr, DECORSR_JR0); -- -- /* Mark the DECO as free */ -- clrbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE); -- -- if (!timeout) -- return -EAGAIN; -- -- return 0; - } - --/* -- * instantiate_rng - builds and executes a descriptor on DECO0, -- * which initializes the RNG block. -- * @ctrldev - pointer to device -- * @state_handle_mask - bitmask containing the instantiation status -- * for the RNG4 state handles which exist in -- * the RNG4 block: 1 if it's been instantiated -- * by an external entry, 0 otherwise. -- * @gen_sk - generate data to be loaded into the JDKEK, TDKEK and TDSK; -- * Caution: this can be done only once; if the keys need to be -- * regenerated, a POR is required -- * -- * Return: - 0 if no error occurred -- * - -ENOMEM if there isn't enough memory to allocate the descriptor -- * - -ENODEV if DECO0 couldn't be acquired -- * - -EAGAIN if an error occurred when executing the descriptor -- * f.i. there was a RNG hardware error due to not "good enough" -- * entropy being aquired. -- */ --static int instantiate_rng(struct device *ctrldev, int state_handle_mask, -- int gen_sk) -+static void generate_secure_keys_desc(u32 *desc) - { -- struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); -- struct caam_ctrl __iomem *ctrl; -- u32 *desc, status, rdsta_val; -- int ret = 0, sh_idx; -- -- ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; -- desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL); -- if (!desc) -- return -ENOMEM; -+ /* generate secure keys (non-test) */ -+ append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | -+ OP_ALG_RNG4_SK); -+} - -- for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) { -- /* -- * If the corresponding bit is set, this state handle -- * was initialized by somebody else, so it's left alone. -- */ -- if ((1 << sh_idx) & state_handle_mask) -- continue; -+struct instantiate_result { -+ struct completion completion; -+ int err; -+}; - -- /* Create the descriptor for instantiating RNG State Handle */ -- build_instantiation_desc(desc, sh_idx, gen_sk); -+static void rng4_init_done(struct device *dev, u32 *desc, u32 err, -+ void *context) -+{ -+ struct instantiate_result *instantiation = context; - -- /* Try to run it through DECO0 */ -- ret = run_descriptor_deco0(ctrldev, desc, &status); -+ if (err) { -+ char tmp[CAAM_ERROR_STR_MAX]; - -- /* -- * If ret is not 0, or descriptor status is not 0, then -- * something went wrong. No need to try the next state -- * handle (if available), bail out here. -- * Also, if for some reason, the State Handle didn't get -- * instantiated although the descriptor has finished -- * without any error (HW optimizations for later -- * CAAM eras), then try again. -- */ -- rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK; -- if (status || !(rdsta_val & (1 << sh_idx))) -- ret = -EAGAIN; -- if (ret) -- break; -- dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx); -- /* Clear the contents before recreating the descriptor */ -- memset(desc, 0x00, CAAM_CMD_SZ * 7); -+ dev_err(dev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err)); - } - -- kfree(desc); -- -- return ret; -+ instantiation->err = err; -+ complete(&instantiation->completion); - } - --/* -- * deinstantiate_rng - builds and executes a descriptor on DECO0, -- * which deinitializes the RNG block. -- * @ctrldev - pointer to device -- * @state_handle_mask - bitmask containing the instantiation status -- * for the RNG4 state handles which exist in -- * the RNG4 block: 1 if it's been instantiated -- * -- * Return: - 0 if no error occurred -- * - -ENOMEM if there isn't enough memory to allocate the descriptor -- * - -ENODEV if DECO0 couldn't be acquired -- * - -EAGAIN if an error occurred when executing the descriptor -- */ --static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask) -+static int instantiate_rng(struct device *jrdev, u32 keys_generated) - { -- u32 *desc, status; -- int sh_idx, ret = 0; -+ struct instantiate_result instantiation; - -- desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL); -- if (!desc) -+ dma_addr_t desc_dma; -+ u32 *desc; -+ int ret; -+ -+ desc = kmalloc(CAAM_CMD_SZ * 6, GFP_KERNEL | GFP_DMA); -+ if (!desc) { -+ dev_err(jrdev, "cannot allocate RNG init descriptor memory\n"); - return -ENOMEM; -- -- for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) { -- /* -- * If the corresponding bit is set, then it means the state -- * handle was initialized by us, and thus it needs to be -- * deintialized as well -- */ -- if ((1 << sh_idx) & state_handle_mask) { -- /* -- * Create the descriptor for deinstantating this state -- * handle -- */ -- build_deinstantiation_desc(desc, sh_idx); -- -- /* Try to run it through DECO0 */ -- ret = run_descriptor_deco0(ctrldev, desc, &status); -- -- if (ret || status) { -- dev_err(ctrldev, -- "Failed to deinstantiate RNG4 SH%d\n", -- sh_idx); -- break; -- } -- dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx); -- } - } - -- kfree(desc); -- -- return ret; --} -+ build_instantiation_desc(desc); - --static int caam_remove(struct platform_device *pdev) --{ -- struct device *ctrldev; -- struct caam_drv_private *ctrlpriv; -- struct caam_ctrl __iomem *ctrl; -- int ring, ret = 0; -- -- ctrldev = &pdev->dev; -- ctrlpriv = dev_get_drvdata(ctrldev); -- ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; -- -- /* Remove platform devices for JobRs */ -- for (ring = 0; ring < ctrlpriv->total_jobrs; ring++) { -- if (ctrlpriv->jrpdev[ring]) -- of_device_unregister(ctrlpriv->jrpdev[ring]); -+ /* If keys have not been generated, add op code to generate key. */ -+ if (!keys_generated) -+ generate_secure_keys_desc(desc); -+ -+ desc_dma = dma_map_single(jrdev, desc, desc_bytes(desc), DMA_TO_DEVICE); -+ dma_sync_single_for_device(jrdev, desc_dma, desc_bytes(desc), -+ DMA_TO_DEVICE); -+ init_completion(&instantiation.completion); -+ ret = caam_jr_enqueue(jrdev, desc, rng4_init_done, &instantiation); -+ if (!ret) { -+ wait_for_completion_interruptible(&instantiation.completion); -+ ret = instantiation.err; -+ if (ret) -+ dev_err(jrdev, "unable to instantiate RNG\n"); - } - -- /* De-initialize RNG state handles initialized by this driver. */ -- if (ctrlpriv->rng4_sh_init) -- deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init); -- -- /* Shut down debug views */ --#ifdef CONFIG_DEBUG_FS -- debugfs_remove_recursive(ctrlpriv->dfs_root); --#endif -+ dma_unmap_single(jrdev, desc_dma, desc_bytes(desc), DMA_TO_DEVICE); - -- /* Unmap controller region */ -- iounmap(&ctrl); -+ kfree(desc); - - return ret; - } - - /* -- * kick_trng - sets the various parameters for enabling the initialization -- * of the RNG4 block in CAAM -- * @pdev - pointer to the platform device -- * @ent_delay - Defines the length (in system clocks) of each entropy sample. -+ * By default, the TRNG runs for 200 clocks per sample; -+ * 1600 clocks per sample generates better entropy. - */ --static void kick_trng(struct platform_device *pdev, int ent_delay) -+static void kick_trng(struct platform_device *pdev) - { - struct device *ctrldev = &pdev->dev; - struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); -- struct caam_ctrl __iomem *ctrl; -+ struct caam_full __iomem *topregs; - struct rng4tst __iomem *r4tst; - u32 val; - -- ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; -- r4tst = &ctrl->r4tst[0]; -+ topregs = (struct caam_full __iomem *)ctrlpriv->ctrl; -+ r4tst = &topregs->ctrl.r4tst[0]; - -+ val = rd_reg32(&r4tst->rtmctl); - /* put RNG4 into program mode */ - setbits32(&r4tst->rtmctl, RTMCTL_PRGM); -- -- /* -- * Performance-wise, it does not make sense to -- * set the delay to a value that is lower -- * than the last one that worked (i.e. the state handles -- * were instantiated properly. Thus, instead of wasting -- * time trying to set the values controlling the sample -- * frequency, the function simply returns. -- */ -- val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK) -- >> RTSDCTL_ENT_DLY_SHIFT; -- if (ent_delay <= val) { -- /* put RNG4 into run mode */ -- clrbits32(&r4tst->rtmctl, RTMCTL_PRGM); -- return; -- } -- -+ /* Set clocks per sample to the default, and divider to zero */ - val = rd_reg32(&r4tst->rtsdctl); - val = (val & ~RTSDCTL_ENT_DLY_MASK) | -- (ent_delay << RTSDCTL_ENT_DLY_SHIFT); -+ (RNG4_ENT_CLOCKS_SAMPLE << RTSDCTL_ENT_DLY_SHIFT); - wr_reg32(&r4tst->rtsdctl, val); -- /* min. freq. count, equal to 1/4 of the entropy sample length */ -- wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2); -- /* disable maximum frequency count */ -- wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE); -- /* read the control register */ -- val = rd_reg32(&r4tst->rtmctl); -- /* -- * select raw sampling in both entropy shifter -- * and statistical checker -- */ -- setbits32(&val, RTMCTL_SAMP_MODE_RAW_ES_SC); -+ /* min. freq. count */ -+ wr_reg32(&r4tst->rtfrqmin, RNG4_ENT_CLOCKS_SAMPLE / 4); -+ /* max. freq. count */ -+ wr_reg32(&r4tst->rtfrqmax, RNG4_ENT_CLOCKS_SAMPLE * 8); - /* put RNG4 into run mode */ -- clrbits32(&val, RTMCTL_PRGM); -- /* write back the control register */ -- wr_reg32(&r4tst->rtmctl, val); -+ clrbits32(&r4tst->rtmctl, RTMCTL_PRGM); - } - - /** - * caam_get_era() - Return the ERA of the SEC on SoC, based -- * on "sec-era" propery in the DTS. This property is updated by u-boot. -+ * on the SEC_VID register. -+ * Returns the ERA number (1..4) or -ENOTSUPP if the ERA is unknown. -+ * @caam_id - the value of the SEC_VID register - **/ --int caam_get_era(void) -+int caam_get_era(u64 caam_id) - { -- struct device_node *caam_node; -- for_each_compatible_node(caam_node, NULL, "fsl,sec-v4.0") { -- const uint32_t *prop = (uint32_t *)of_get_property(caam_node, -- "fsl,sec-era", -- NULL); -- return prop ? *prop : -ENOTSUPP; -- } -+ struct sec_vid *sec_vid = (struct sec_vid *)&caam_id; -+ static const struct { -+ u16 ip_id; -+ u8 maj_rev; -+ u8 era; -+ } caam_eras[] = { -+ {0x0A10, 1, 1}, -+ {0x0A10, 2, 2}, -+ {0x0A12, 1, 3}, -+ {0x0A14, 1, 3}, -+ {0x0A14, 2, 4}, -+ {0x0A16, 1, 4}, -+ {0x0A11, 1, 4}, -+ {0x0A10, 3, 4}, -+ {0x0A18, 1, 4}, -+ {0x0A11, 2, 5}, -+ {0x0A12, 2, 5}, -+ {0x0A13, 1, 5}, -+ {0x0A1C, 1, 5}, -+ {0x0A12, 4, 6}, -+ {0x0A13, 2, 6}, -+ {0x0A16, 2, 6}, -+ {0x0A18, 2, 6}, -+ {0x0A1A, 1, 6}, -+ {0x0A1C, 2, 6}, -+ {0x0A17, 1, 6} -+ }; -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(caam_eras); i++) -+ if (caam_eras[i].ip_id == sec_vid->ip_id && -+ caam_eras[i].maj_rev == sec_vid->maj_rev) -+ return caam_eras[i].era; - - return -ENOTSUPP; - } - EXPORT_SYMBOL(caam_get_era); - -+/* -+ * Return a job ring device. This is available so outside -+ * entities can gain direct access to the job ring. For now, -+ * this function returns the first job ring (at index 0). -+ */ -+struct device *caam_get_jrdev(void) -+{ -+ return caam_jr_dev[0]; -+} -+EXPORT_SYMBOL(caam_get_jrdev); -+ -+ - /* Probe routine for CAAM top (controller) level */ - static int caam_probe(struct platform_device *pdev) - { -- int ret, ring, rspec, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN; -+ int ret, ring, rspec; - u64 caam_id; - struct device *dev; - struct device_node *nprop, *np; - struct caam_ctrl __iomem *ctrl; -+ struct caam_full __iomem *topregs; -+ struct snvs_full __iomem *snvsregs; - struct caam_drv_private *ctrlpriv; - #ifdef CONFIG_DEBUG_FS - struct caam_perfmon *perfmon; - #endif -- u32 scfgr, comp_params; -- u32 cha_vid_ls; -- int pg_size; -- int BLOCK_OFFSET = 0; - -- ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(struct caam_drv_private), -- GFP_KERNEL); -+ ctrlpriv = kzalloc(sizeof(struct caam_drv_private), GFP_KERNEL); - if (!ctrlpriv) - return -ENOMEM; - -@@ -415,71 +270,128 @@ - dev_err(dev, "caam: of_iomap() failed\n"); - return -ENOMEM; - } -- /* Finding the page size for using the CTPR_MS register */ -- comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms); -- pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT; -- -- /* Allocating the BLOCK_OFFSET based on the supported page size on -- * the platform -- */ -- if (pg_size == 0) -- BLOCK_OFFSET = PG_SIZE_4K; -- else -- BLOCK_OFFSET = PG_SIZE_64K; -- - ctrlpriv->ctrl = (struct caam_ctrl __force *)ctrl; -- ctrlpriv->assure = (struct caam_assurance __force *) -- ((uint8_t *)ctrl + -- BLOCK_OFFSET * ASSURE_BLOCK_NUMBER -- ); -- ctrlpriv->deco = (struct caam_deco __force *) -- ((uint8_t *)ctrl + -- BLOCK_OFFSET * DECO_BLOCK_NUMBER -- ); -+ -+ /* topregs used to derive pointers to CAAM sub-blocks only */ -+ topregs = (struct caam_full __iomem *)ctrl; - - /* Get the IRQ of the controller (for security violations only) */ -- ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0); -+ ctrlpriv->secvio_irq = of_irq_to_resource(nprop, 0, NULL); -+ -+ /* Get SNVS register Page */ -+ np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-caam-snvs"); -+ -+ if (!np) -+ return -ENODEV; -+ -+ snvsregs = of_iomap(np, 0); -+ ctrlpriv->snvs = snvsregs; -+ /* Get CAAM-SM node and of_iomap() and save */ -+ np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-caam-sm"); -+ -+ if (!np) -+ return -ENODEV; -+ -+ ctrlpriv->sm_base = of_iomap(np, 0); -+ ctrlpriv->sm_size = 0x3fff; -+ -+/* -+ * ARM targets tend to have clock control subsystems that can -+ * enable/disable clocking to our device. Turn clocking on to proceed -+ */ -+#ifdef CONFIG_ARM -+ ctrlpriv->caam_ipg = devm_clk_get(&ctrlpriv->pdev->dev, "caam_ipg"); -+ if (IS_ERR(ctrlpriv->caam_ipg)) { -+ ret = PTR_ERR(ctrlpriv->caam_ipg); -+ dev_err(&ctrlpriv->pdev->dev, -+ "can't identify CAAM ipg clk: %d\n", ret); -+ return -ENODEV; -+ } -+ ctrlpriv->caam_mem = devm_clk_get(&ctrlpriv->pdev->dev, "caam_mem"); -+ if (IS_ERR(ctrlpriv->caam_mem)) { -+ ret = PTR_ERR(ctrlpriv->caam_mem); -+ dev_err(&ctrlpriv->pdev->dev, -+ "can't identify CAAM secure mem clk: %d\n", ret); -+ return -ENODEV; -+ } -+ ctrlpriv->caam_aclk = devm_clk_get(&ctrlpriv->pdev->dev, "caam_aclk"); -+ if (IS_ERR(ctrlpriv->caam_aclk)) { -+ ret = PTR_ERR(ctrlpriv->caam_aclk); -+ dev_err(&ctrlpriv->pdev->dev, -+ "can't identify CAAM aclk clk: %d\n", ret); -+ return -ENODEV; -+ } -+ -+ ret = clk_prepare(ctrlpriv->caam_ipg); -+ if (ret < 0) { -+ dev_err(&pdev->dev, "can't prepare CAAM ipg clock: %d\n", ret); -+ return -ENODEV; -+ } -+ ret = clk_prepare(ctrlpriv->caam_mem); -+ if (ret < 0) { -+ dev_err(&pdev->dev, "can't prepare CAAM secure mem clock: %d\n", ret); -+ return -ENODEV; -+ } -+ ret = clk_prepare(ctrlpriv->caam_aclk); -+ if (ret < 0) { -+ dev_err(&pdev->dev, "can't prepare CAAM aclk clock: %d\n", ret); -+ return -ENODEV; -+ } -+ -+ ret = clk_enable(ctrlpriv->caam_ipg); -+ if (ret < 0) { -+ dev_err(&pdev->dev, "can't enable CAAM ipg clock: %d\n", ret); -+ return -ENODEV; -+ } -+ ret = clk_enable(ctrlpriv->caam_mem); -+ if (ret < 0) { -+ dev_err(&pdev->dev, "can't enable CAAM secure mem clock: %d\n", ret); -+ return -ENODEV; -+ } -+ ret = clk_enable(ctrlpriv->caam_aclk); -+ if (ret < 0) { -+ dev_err(&pdev->dev, "can't enable CAAM aclk clock: %d\n", ret); -+ return -ENODEV; -+ } -+ -+ pr_debug("%s caam_ipg clock:%d\n", __func__, -+ (int)clk_get_rate(ctrlpriv->caam_ipg)); -+ pr_debug("%s caam_mem clock:%d\n", __func__, -+ (int)clk_get_rate(ctrlpriv->caam_mem)); -+ pr_debug("%s caam_aclk clock:%d\n", __func__, -+ (int)clk_get_rate(ctrlpriv->caam_aclk)); -+#endif - - /* - * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel, - * long pointers in master configuration register - */ -- setbits32(&ctrl->mcr, MCFGR_WDENABLE | -+ setbits32(&topregs->ctrl.mcr, MCFGR_WDENABLE | - (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0)); - -+#ifdef CONFIG_ARCH_MX6 - /* -- * Read the Compile Time paramters and SCFGR to determine -- * if Virtualization is enabled for this platform -+ * ERRATA: mx6 devices have an issue wherein AXI bus transactions -+ * may not occur in the correct order. This isn't a problem running -+ * single descriptors, but can be if running multiple concurrent -+ * descriptors. Reworking the driver to throttle to single requests -+ * is impractical, thus the workaround is to limit the AXI pipeline -+ * to a depth of 1 (from it's default of 4) to preclude this situation -+ * from occurring. - */ -- scfgr = rd_reg32(&ctrl->scfgr); -- -- ctrlpriv->virt_en = 0; -- if (comp_params & CTPR_MS_VIRT_EN_INCL) { -- /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or -- * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SCFGR_VIRT_EN = 1 -- */ -- if ((comp_params & CTPR_MS_VIRT_EN_POR) || -- (!(comp_params & CTPR_MS_VIRT_EN_POR) && -- (scfgr & SCFGR_VIRT_EN))) -- ctrlpriv->virt_en = 1; -- } else { -- /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */ -- if (comp_params & CTPR_MS_VIRT_EN_POR) -- ctrlpriv->virt_en = 1; -- } -- -- if (ctrlpriv->virt_en == 1) -- setbits32(&ctrl->jrstart, JRSTART_JR0_START | -- JRSTART_JR1_START | JRSTART_JR2_START | -- JRSTART_JR3_START); -+ wr_reg32(&topregs->ctrl.mcr, -+ (rd_reg32(&topregs->ctrl.mcr) & ~(MCFGR_AXIPIPE_MASK)) | -+ ((1 << MCFGR_AXIPIPE_SHIFT) & MCFGR_AXIPIPE_MASK)); -+#endif - -+ /* Set DMA masks according to platform ranging */ - if (sizeof(dma_addr_t) == sizeof(u64)) -- if (of_device_is_compatible(nprop, "fsl,sec-v5.0")) -- dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); -+ if (of_device_is_compatible(nprop, "fsl,sec-v4.0")) -+ dma_set_mask(dev, DMA_BIT_MASK(40)); - else -- dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36)); -+ dma_set_mask(dev, DMA_BIT_MASK(36)); - else -- dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); -+ dma_set_mask(dev, DMA_BIT_MASK(32)); - - /* - * Detect and enable JobRs -@@ -487,51 +399,65 @@ - * for all, then go probe each one. - */ - rspec = 0; -- for_each_available_child_of_node(nprop, np) -- if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") || -- of_device_is_compatible(np, "fsl,sec4.0-job-ring")) -+ for_each_compatible_node(np, NULL, "fsl,sec-v4.0-job-ring") -+ rspec++; -+ if (!rspec) { -+ /* for backward compatible with device trees */ -+ for_each_compatible_node(np, NULL, "fsl,sec4.0-job-ring") - rspec++; -+ } - -- ctrlpriv->jrpdev = devm_kzalloc(&pdev->dev, -- sizeof(struct platform_device *) * rspec, -- GFP_KERNEL); -- if (ctrlpriv->jrpdev == NULL) { -- iounmap(&ctrl); -+ ctrlpriv->jrdev = kzalloc(sizeof(struct device *) * rspec, GFP_KERNEL); -+ if (ctrlpriv->jrdev == NULL) { -+ iounmap(&topregs->ctrl); - return -ENOMEM; - } - - ring = 0; - ctrlpriv->total_jobrs = 0; -- for_each_available_child_of_node(nprop, np) -- if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") || -- of_device_is_compatible(np, "fsl,sec4.0-job-ring")) { -- ctrlpriv->jrpdev[ring] = -- of_platform_device_create(np, NULL, dev); -- if (!ctrlpriv->jrpdev[ring]) { -- pr_warn("JR%d Platform device creation error\n", -- ring); -- continue; -+ for_each_compatible_node(np, NULL, "fsl,sec-v4.0-job-ring") { -+ ret = caam_jr_probe(pdev, np, ring); -+ if (ret < 0) { -+ /* -+ * Job ring not found, error out. At some -+ * point, we should enhance job ring handling -+ * to allow for non-consecutive job rings to -+ * be found. -+ */ -+ pr_err("fsl,sec-v4.0-job-ring not found "); -+ pr_err("(ring %d)\n", ring); -+ return ret; -+ } -+ ctrlpriv->total_jobrs++; -+ ring++; -+ } -+ -+ if (!ring) { -+ for_each_compatible_node(np, NULL, "fsl,sec4.0-job-ring") { -+ ret = caam_jr_probe(pdev, np, ring); -+ if (ret < 0) { -+ /* -+ * Job ring not found, error out. At some -+ * point, we should enhance job ring handling -+ * to allow for non-consecutive job rings to -+ * be found. -+ */ -+ pr_err("fsl,sec4.0-job-ring not found "); -+ pr_err("(ring %d)\n", ring); -+ return ret; - } -- ctrlpriv->jr[ring] = (struct caam_job_ring __force *) -- ((uint8_t *)ctrl + -- (ring + JR_BLOCK_NUMBER) * -- BLOCK_OFFSET -- ); - ctrlpriv->total_jobrs++; - ring++; -+ } - } - - /* Check to see if QI present. If so, enable */ -- ctrlpriv->qi_present = -- !!(rd_reg32(&ctrl->perfmon.comp_parms_ms) & -- CTPR_MS_QI_MASK); -+ ctrlpriv->qi_present = !!(rd_reg64(&topregs->ctrl.perfmon.comp_parms) & -+ CTPR_QI_MASK); - if (ctrlpriv->qi_present) { -- ctrlpriv->qi = (struct caam_queue_if __force *) -- ((uint8_t *)ctrl + -- BLOCK_OFFSET * QI_BLOCK_NUMBER -- ); -+ ctrlpriv->qi = (struct caam_queue_if __force *)&topregs->qi; - /* This is all that's required to physically enable QI */ -- wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN); -+ wr_reg32(&topregs->qi.qi_control_lo, QICTL_DQEN); - } - - /* If no QI and no rings specified, quit and go home */ -@@ -541,81 +467,53 @@ - return -ENOMEM; - } - -- cha_vid_ls = rd_reg32(&ctrl->perfmon.cha_id_ls); -- - /* -- * If SEC has RNG version >= 4 and RNG state handle has not been -- * already instantiated, do RNG instantiation -+ * RNG4 based SECs (v5+ | >= i.MX6) need special initialization prior -+ * to executing any descriptors. If there's a problem with init, -+ * remove other subsystems and return; internal padding functions -+ * cannot run without an RNG. This procedure assumes a single RNG4 -+ * instance. - */ -- if ((cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) { -- ctrlpriv->rng4_sh_init = -- rd_reg32(&ctrl->r4tst[0].rdsta); -+ if ((rd_reg64(&topregs->ctrl.perfmon.cha_id) & CHA_ID_RNG_MASK) -+ == CHA_ID_RNG_4) { -+ struct rng4tst __iomem *r4tst; -+ u32 rdsta, rng_if, rng_skvn; -+ - /* -- * If the secure keys (TDKEK, JDKEK, TDSK), were already -- * generated, signal this to the function that is instantiating -- * the state handles. An error would occur if RNG4 attempts -- * to regenerate these keys before the next POR. -+ * Check to see if the RNG has already been instantiated. -+ * If either the state 0 or 1 instantiated flags are set, -+ * then don't continue on and try to instantiate the RNG -+ * again. - */ -- gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1; -- ctrlpriv->rng4_sh_init &= RDSTA_IFMASK; -- do { -- int inst_handles = -- rd_reg32(&ctrl->r4tst[0].rdsta) & -- RDSTA_IFMASK; -- /* -- * If either SH were instantiated by somebody else -- * (e.g. u-boot) then it is assumed that the entropy -- * parameters are properly set and thus the function -- * setting these (kick_trng(...)) is skipped. -- * Also, if a handle was instantiated, do not change -- * the TRNG parameters. -- */ -- if (!(ctrlpriv->rng4_sh_init || inst_handles)) { -- dev_info(dev, -- "Entropy delay = %u\n", -- ent_delay); -- kick_trng(pdev, ent_delay); -- ent_delay += 400; -+ r4tst = &topregs->ctrl.r4tst[0]; -+ rdsta = rd_reg32(&r4tst->rdsta); /* Read RDSTA register */ -+ -+ /* Check IF bit for non-deterministic instantiation */ -+ rng_if = rdsta & RDSTA_IF; -+ -+ /* Check SKVN bit for non-deterministic key generation */ -+ rng_skvn = rdsta & RDSTA_SKVN; -+ if (!rng_if) { -+ kick_trng(pdev); -+ ret = instantiate_rng(ctrlpriv->jrdev[0], rng_skvn); -+ if (ret) { -+ caam_remove(pdev); -+ return -ENODEV; - } -- /* -- * if instantiate_rng(...) fails, the loop will rerun -- * and the kick_trng(...) function will modfiy the -- * upper and lower limits of the entropy sampling -- * interval, leading to a sucessful initialization of -- * the RNG. -- */ -- ret = instantiate_rng(dev, inst_handles, -- gen_sk); -- if (ret == -EAGAIN) -- /* -- * if here, the loop will rerun, -- * so don't hog the CPU -- */ -- cpu_relax(); -- } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX)); -- if (ret) { -- dev_err(dev, "failed to instantiate RNG"); -- caam_remove(pdev); -- return ret; -+ ctrlpriv->rng_inst++; - } -- /* -- * Set handles init'ed by this module as the complement of the -- * already initialized ones -- */ -- ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK; -- -- /* Enable RDB bit so that RNG works faster */ -- setbits32(&ctrl->scfgr, SCFGR_RDBENABLE); - } - - /* NOTE: RTIC detection ought to go here, around Si time */ - -- caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 | -- (u64)rd_reg32(&ctrl->perfmon.caam_id_ls); -+ /* Initialize queue allocator lock */ -+ spin_lock_init(&ctrlpriv->jr_alloc_lock); -+ -+ caam_id = rd_reg64(&topregs->ctrl.perfmon.caam_id); - - /* Report "alive" for developer to see */ - dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id, -- caam_get_era()); -+ caam_get_era(caam_id)); - dev_info(dev, "job rings = %d, qi = %d\n", - ctrlpriv->total_jobrs, ctrlpriv->qi_present); - -@@ -627,7 +525,7 @@ - */ - perfmon = (struct caam_perfmon __force *)&ctrl->perfmon; - -- ctrlpriv->dfs_root = debugfs_create_dir(dev_name(dev), NULL); -+ ctrlpriv->dfs_root = debugfs_create_dir("caam", NULL); - ctrlpriv->ctl = debugfs_create_dir("ctl", ctrlpriv->dfs_root); - - /* Controller-level - performance monitor counters */ -@@ -716,6 +614,7 @@ - static struct platform_driver caam_driver = { - .driver = { - .name = "caam", -+ .owner = THIS_MODULE, - .of_match_table = caam_match, - }, - .probe = caam_probe, -diff -Nur linux-4.1.13.orig/drivers/crypto/caam/ctrl.h linux-4.1.13/drivers/crypto/caam/ctrl.h ---- linux-4.1.13.orig/drivers/crypto/caam/ctrl.h 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/crypto/caam/ctrl.h 2015-11-30 17:56:13.548139857 +0100 -@@ -8,6 +8,6 @@ - #define CTRL_H - - /* Prototypes for backend-level services exposed to APIs */ --int caam_get_era(void); -+int caam_get_era(u64 caam_id); - - #endif /* CTRL_H */ -diff -Nur linux-4.1.13.orig/drivers/crypto/caam/desc_constr.h linux-4.1.13/drivers/crypto/caam/desc_constr.h ---- linux-4.1.13.orig/drivers/crypto/caam/desc_constr.h 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/crypto/caam/desc_constr.h 2015-11-30 17:56:13.548139857 +0100 -@@ -10,7 +10,6 @@ - #define CAAM_CMD_SZ sizeof(u32) - #define CAAM_PTR_SZ sizeof(dma_addr_t) - #define CAAM_DESC_BYTES_MAX (CAAM_CMD_SZ * MAX_CAAM_DESCSIZE) --#define DESC_JOB_IO_LEN (CAAM_CMD_SZ * 5 + CAAM_PTR_SZ * 3) - - #ifdef DEBUG - #define PRINT_POS do { printk(KERN_DEBUG "%02d: %s\n", desc_len(desc),\ -@@ -111,26 +110,6 @@ - (*desc)++; - } - --#define append_u32 append_cmd -- --static inline void append_u64(u32 *desc, u64 data) --{ -- u32 *offset = desc_end(desc); -- -- *offset = upper_32_bits(data); -- *(++offset) = lower_32_bits(data); -- -- (*desc) += 2; --} -- --/* Write command without affecting header, and return pointer to next word */ --static inline u32 *write_cmd(u32 *desc, u32 command) --{ -- *desc = command; -- -- return desc + 1; --} -- - static inline void append_cmd_ptr(u32 *desc, dma_addr_t ptr, int len, - u32 command) - { -@@ -143,8 +122,7 @@ - unsigned int len, u32 command) - { - append_cmd(desc, command); -- if (!(command & (SQIN_RTO | SQIN_PRE))) -- append_ptr(desc, ptr); -+ append_ptr(desc, ptr); - append_cmd(desc, len); - } - -@@ -155,29 +133,21 @@ - append_data(desc, data, len); - } - --#define APPEND_CMD_RET(cmd, op) \ --static inline u32 *append_##cmd(u32 *desc, u32 options) \ --{ \ -- u32 *cmd = desc_end(desc); \ -- PRINT_POS; \ -- append_cmd(desc, CMD_##op | options); \ -- return cmd; \ -+static inline u32 *append_jump(u32 *desc, u32 options) -+{ -+ u32 *cmd = desc_end(desc); -+ -+ PRINT_POS; -+ append_cmd(desc, CMD_JUMP | options); -+ -+ return cmd; - } --APPEND_CMD_RET(jump, JUMP) --APPEND_CMD_RET(move, MOVE) - - static inline void set_jump_tgt_here(u32 *desc, u32 *jump_cmd) - { - *jump_cmd = *jump_cmd | (desc_len(desc) - (jump_cmd - desc)); - } - --static inline void set_move_tgt_here(u32 *desc, u32 *move_cmd) --{ -- *move_cmd &= ~MOVE_OFFSET_MASK; -- *move_cmd = *move_cmd | ((desc_len(desc) << (MOVE_OFFSET_SHIFT + 2)) & -- MOVE_OFFSET_MASK); --} -- - #define APPEND_CMD(cmd, op) \ - static inline void append_##cmd(u32 *desc, u32 options) \ - { \ -@@ -185,6 +155,7 @@ - append_cmd(desc, CMD_##op | options); \ - } - APPEND_CMD(operation, OPERATION) -+APPEND_CMD(move, MOVE) - - #define APPEND_CMD_LEN(cmd, op) \ - static inline void append_##cmd(u32 *desc, unsigned int len, u32 options) \ -@@ -192,8 +163,6 @@ - PRINT_POS; \ - append_cmd(desc, CMD_##op | len | options); \ - } -- --APPEND_CMD_LEN(seq_load, SEQ_LOAD) - APPEND_CMD_LEN(seq_store, SEQ_STORE) - APPEND_CMD_LEN(seq_fifo_load, SEQ_FIFO_LOAD) - APPEND_CMD_LEN(seq_fifo_store, SEQ_FIFO_STORE) -@@ -207,36 +176,17 @@ - } - APPEND_CMD_PTR(key, KEY) - APPEND_CMD_PTR(load, LOAD) -+APPEND_CMD_PTR(store, STORE) - APPEND_CMD_PTR(fifo_load, FIFO_LOAD) - APPEND_CMD_PTR(fifo_store, FIFO_STORE) - --static inline void append_store(u32 *desc, dma_addr_t ptr, unsigned int len, -- u32 options) --{ -- u32 cmd_src; -- -- cmd_src = options & LDST_SRCDST_MASK; -- -- append_cmd(desc, CMD_STORE | options | len); -- -- /* The following options do not require pointer */ -- if (!(cmd_src == LDST_SRCDST_WORD_DESCBUF_SHARED || -- cmd_src == LDST_SRCDST_WORD_DESCBUF_JOB || -- cmd_src == LDST_SRCDST_WORD_DESCBUF_JOB_WE || -- cmd_src == LDST_SRCDST_WORD_DESCBUF_SHARED_WE)) -- append_ptr(desc, ptr); --} -- - #define APPEND_SEQ_PTR_INTLEN(cmd, op) \ - static inline void append_seq_##cmd##_ptr_intlen(u32 *desc, dma_addr_t ptr, \ - unsigned int len, \ - u32 options) \ - { \ - PRINT_POS; \ -- if (options & (SQIN_RTO | SQIN_PRE)) \ -- append_cmd(desc, CMD_SEQ_##op##_PTR | len | options); \ -- else \ -- append_cmd_ptr(desc, ptr, len, CMD_SEQ_##op##_PTR | options); \ -+ append_cmd_ptr(desc, ptr, len, CMD_SEQ_##op##_PTR | options); \ - } - APPEND_SEQ_PTR_INTLEN(in, IN) - APPEND_SEQ_PTR_INTLEN(out, OUT) -@@ -309,7 +259,7 @@ - */ - #define APPEND_MATH(op, desc, dest, src_0, src_1, len) \ - append_cmd(desc, CMD_MATH | MATH_FUN_##op | MATH_DEST_##dest | \ -- MATH_SRC0_##src_0 | MATH_SRC1_##src_1 | (u32)len); -+ MATH_SRC0_##src_0 | MATH_SRC1_##src_1 | (u32) (len & MATH_LEN_MASK)); - - #define append_math_add(desc, dest, src0, src1, len) \ - APPEND_MATH(ADD, desc, dest, src0, src1, len) -@@ -329,15 +279,13 @@ - APPEND_MATH(LSHIFT, desc, dest, src0, src1, len) - #define append_math_rshift(desc, dest, src0, src1, len) \ - APPEND_MATH(RSHIFT, desc, dest, src0, src1, len) --#define append_math_ldshift(desc, dest, src0, src1, len) \ -- APPEND_MATH(SHLD, desc, dest, src0, src1, len) - - /* Exactly one source is IMM. Data is passed in as u32 value */ - #define APPEND_MATH_IMM_u32(op, desc, dest, src_0, src_1, data) \ - do { \ - APPEND_MATH(op, desc, dest, src_0, src_1, CAAM_CMD_SZ); \ - append_cmd(desc, data); \ --} while (0) -+} while (0); - - #define append_math_add_imm_u32(desc, dest, src0, src1, data) \ - APPEND_MATH_IMM_u32(ADD, desc, dest, src0, src1, data) -@@ -357,34 +305,3 @@ - APPEND_MATH_IMM_u32(LSHIFT, desc, dest, src0, src1, data) - #define append_math_rshift_imm_u32(desc, dest, src0, src1, data) \ - APPEND_MATH_IMM_u32(RSHIFT, desc, dest, src0, src1, data) -- --/* Exactly one source is IMM. Data is passed in as u64 value */ --#define APPEND_MATH_IMM_u64(op, desc, dest, src_0, src_1, data) \ --do { \ -- u32 upper = (data >> 16) >> 16; \ -- APPEND_MATH(op, desc, dest, src_0, src_1, CAAM_CMD_SZ * 2 | \ -- (upper ? 0 : MATH_IFB)); \ -- if (upper) \ -- append_u64(desc, data); \ -- else \ -- append_u32(desc, data); \ --} while (0) -- --#define append_math_add_imm_u64(desc, dest, src0, src1, data) \ -- APPEND_MATH_IMM_u64(ADD, desc, dest, src0, src1, data) --#define append_math_sub_imm_u64(desc, dest, src0, src1, data) \ -- APPEND_MATH_IMM_u64(SUB, desc, dest, src0, src1, data) --#define append_math_add_c_imm_u64(desc, dest, src0, src1, data) \ -- APPEND_MATH_IMM_u64(ADDC, desc, dest, src0, src1, data) --#define append_math_sub_b_imm_u64(desc, dest, src0, src1, data) \ -- APPEND_MATH_IMM_u64(SUBB, desc, dest, src0, src1, data) --#define append_math_and_imm_u64(desc, dest, src0, src1, data) \ -- APPEND_MATH_IMM_u64(AND, desc, dest, src0, src1, data) --#define append_math_or_imm_u64(desc, dest, src0, src1, data) \ -- APPEND_MATH_IMM_u64(OR, desc, dest, src0, src1, data) --#define append_math_xor_imm_u64(desc, dest, src0, src1, data) \ -- APPEND_MATH_IMM_u64(XOR, desc, dest, src0, src1, data) --#define append_math_lshift_imm_u64(desc, dest, src0, src1, data) \ -- APPEND_MATH_IMM_u64(LSHIFT, desc, dest, src0, src1, data) --#define append_math_rshift_imm_u64(desc, dest, src0, src1, data) \ -- APPEND_MATH_IMM_u64(RSHIFT, desc, dest, src0, src1, data) -diff -Nur linux-4.1.13.orig/drivers/crypto/caam/desc.h linux-4.1.13/drivers/crypto/caam/desc.h ---- linux-4.1.13.orig/drivers/crypto/caam/desc.h 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/crypto/caam/desc.h 2015-11-30 17:56:13.548139857 +0100 -@@ -2,19 +2,35 @@ - * CAAM descriptor composition header - * Definitions to support CAAM descriptor instruction generation - * -- * Copyright 2008-2011 Freescale Semiconductor, Inc. -+ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc. - */ - - #ifndef DESC_H - #define DESC_H - -+/* -+ * 16-byte hardware scatter/gather table -+ * An 8-byte table exists in the hardware spec, but has never been -+ * implemented to date. The 8/16 option is selected at RTL-compile-time. -+ * and this selection is visible in the Compile Time Parameters Register -+ */ -+ -+#define SEC4_SG_LEN_EXT 0x80000000 /* Entry points to table */ -+#define SEC4_SG_LEN_FIN 0x40000000 /* Last ent in table */ -+#define SEC4_SG_BPID_MASK 0x000000ff -+#define SEC4_SG_BPID_SHIFT 16 -+#define SEC4_SG_LEN_MASK 0x3fffffff /* Excludes EXT and FINAL */ -+#define SEC4_SG_OFFS_MASK 0x00001fff -+ - struct sec4_sg_entry { -+#ifdef CONFIG_64BIT - u64 ptr; --#define SEC4_SG_LEN_FIN 0x40000000 --#define SEC4_SG_LEN_EXT 0x80000000 -+#else -+ u32 reserved; -+ u32 ptr; -+#endif - u32 len; -- u8 reserved; -- u8 buf_pool_id; -+ u16 buf_pool_id; - u16 offset; - }; - -@@ -231,12 +247,7 @@ - #define LDST_SRCDST_WORD_PKHA_B_SZ (0x11 << LDST_SRCDST_SHIFT) - #define LDST_SRCDST_WORD_PKHA_N_SZ (0x12 << LDST_SRCDST_SHIFT) - #define LDST_SRCDST_WORD_PKHA_E_SZ (0x13 << LDST_SRCDST_SHIFT) --#define LDST_SRCDST_WORD_CLASS_CTX (0x20 << LDST_SRCDST_SHIFT) - #define LDST_SRCDST_WORD_DESCBUF (0x40 << LDST_SRCDST_SHIFT) --#define LDST_SRCDST_WORD_DESCBUF_JOB (0x41 << LDST_SRCDST_SHIFT) --#define LDST_SRCDST_WORD_DESCBUF_SHARED (0x42 << LDST_SRCDST_SHIFT) --#define LDST_SRCDST_WORD_DESCBUF_JOB_WE (0x45 << LDST_SRCDST_SHIFT) --#define LDST_SRCDST_WORD_DESCBUF_SHARED_WE (0x46 << LDST_SRCDST_SHIFT) - #define LDST_SRCDST_WORD_INFO_FIFO (0x7a << LDST_SRCDST_SHIFT) - - /* Offset in source/destination */ -@@ -321,6 +332,7 @@ - /* Continue - Not the last FIFO store to come */ - #define FIFOST_CONT_SHIFT 23 - #define FIFOST_CONT_MASK (1 << FIFOST_CONT_SHIFT) -+#define FIFOST_CONT_MASK (1 << FIFOST_CONT_SHIFT) - - /* - * Extended Length - use 32-bit extended length that -@@ -370,7 +382,6 @@ - #define FIFOLD_TYPE_LAST2FLUSH1 (0x05 << FIFOLD_TYPE_SHIFT) - #define FIFOLD_TYPE_LASTBOTH (0x06 << FIFOLD_TYPE_SHIFT) - #define FIFOLD_TYPE_LASTBOTHFL (0x07 << FIFOLD_TYPE_SHIFT) --#define FIFOLD_TYPE_NOINFOFIFO (0x0F << FIFOLD_TYPE_SHIFT) - - #define FIFOLDST_LEN_MASK 0xffff - #define FIFOLDST_EXT_LEN_MASK 0xffffffff -@@ -1092,6 +1103,23 @@ - #define OP_PCL_PKPROT_ECC 0x0002 - #define OP_PCL_PKPROT_F2M 0x0001 - -+/* Blob protocol protinfo bits */ -+#define OP_PCL_BLOB_TK 0x0200 -+#define OP_PCL_BLOB_EKT 0x0100 -+ -+#define OP_PCL_BLOB_K2KR_MEM 0x0000 -+#define OP_PCL_BLOB_K2KR_C1KR 0x0010 -+#define OP_PCL_BLOB_K2KR_C2KR 0x0030 -+#define OP_PCL_BLOB_K2KR_AFHAS 0x0050 -+#define OP_PCL_BLOB_K2KR_C2KR_SPLIT 0x0070 -+ -+#define OP_PCL_BLOB_PTXT_SECMEM 0x0008 -+#define OP_PCL_BLOB_BLACK 0x0004 -+ -+#define OP_PCL_BLOB_FMT_NORMAL 0x0000 -+#define OP_PCL_BLOB_FMT_MSTR 0x0002 -+#define OP_PCL_BLOB_FMT_TEST 0x0003 -+ - /* For non-protocol/alg-only op commands */ - #define OP_ALG_TYPE_SHIFT 24 - #define OP_ALG_TYPE_MASK (0x7 << OP_ALG_TYPE_SHIFT) -@@ -1154,15 +1182,8 @@ - - /* randomizer AAI set */ - #define OP_ALG_AAI_RNG (0x00 << OP_ALG_AAI_SHIFT) --#define OP_ALG_AAI_RNG_NZB (0x10 << OP_ALG_AAI_SHIFT) --#define OP_ALG_AAI_RNG_OBP (0x20 << OP_ALG_AAI_SHIFT) -- --/* RNG4 AAI set */ --#define OP_ALG_AAI_RNG4_SH_0 (0x00 << OP_ALG_AAI_SHIFT) --#define OP_ALG_AAI_RNG4_SH_1 (0x01 << OP_ALG_AAI_SHIFT) --#define OP_ALG_AAI_RNG4_PS (0x40 << OP_ALG_AAI_SHIFT) --#define OP_ALG_AAI_RNG4_AI (0x80 << OP_ALG_AAI_SHIFT) --#define OP_ALG_AAI_RNG4_SK (0x100 << OP_ALG_AAI_SHIFT) -+#define OP_ALG_AAI_RNG_NOZERO (0x10 << OP_ALG_AAI_SHIFT) -+#define OP_ALG_AAI_RNG_ODD (0x20 << OP_ALG_AAI_SHIFT) - - /* hmac/smac AAI set */ - #define OP_ALG_AAI_HASH (0x00 << OP_ALG_AAI_SHIFT) -@@ -1184,6 +1205,12 @@ - #define OP_ALG_AAI_GSM (0x10 << OP_ALG_AAI_SHIFT) - #define OP_ALG_AAI_EDGE (0x20 << OP_ALG_AAI_SHIFT) - -+/* RNG4 set */ -+#define OP_ALG_RNG4_SHIFT 4 -+#define OP_ALG_RNG4_MASK (0x1f3 << OP_ALG_RNG4_SHIFT) -+ -+#define OP_ALG_RNG4_SK (0x100 << OP_ALG_RNG4_SHIFT) -+ - #define OP_ALG_AS_SHIFT 2 - #define OP_ALG_AS_MASK (0x3 << OP_ALG_AS_SHIFT) - #define OP_ALG_AS_UPDATE (0 << OP_ALG_AS_SHIFT) -@@ -1300,10 +1327,10 @@ - #define SQOUT_SGF 0x01000000 - - /* Appends to a previous pointer */ --#define SQOUT_PRE SQIN_PRE -+#define SQOUT_PRE 0x00800000 - - /* Restore sequence with pointer/length */ --#define SQOUT_RTO SQIN_RTO -+#define SQOUT_RTO 0x00200000 - - /* Use extended length following pointer */ - #define SQOUT_EXT 0x00400000 -@@ -1365,7 +1392,6 @@ - #define MOVE_DEST_MATH3 (0x07 << MOVE_DEST_SHIFT) - #define MOVE_DEST_CLASS1INFIFO (0x08 << MOVE_DEST_SHIFT) - #define MOVE_DEST_CLASS2INFIFO (0x09 << MOVE_DEST_SHIFT) --#define MOVE_DEST_INFIFO_NOINFO (0x0a << MOVE_DEST_SHIFT) - #define MOVE_DEST_PK_A (0x0c << MOVE_DEST_SHIFT) - #define MOVE_DEST_CLASS1KEY (0x0d << MOVE_DEST_SHIFT) - #define MOVE_DEST_CLASS2KEY (0x0e << MOVE_DEST_SHIFT) -@@ -1418,7 +1444,6 @@ - #define MATH_SRC0_REG2 (0x02 << MATH_SRC0_SHIFT) - #define MATH_SRC0_REG3 (0x03 << MATH_SRC0_SHIFT) - #define MATH_SRC0_IMM (0x04 << MATH_SRC0_SHIFT) --#define MATH_SRC0_DPOVRD (0x07 << MATH_SRC0_SHIFT) - #define MATH_SRC0_SEQINLEN (0x08 << MATH_SRC0_SHIFT) - #define MATH_SRC0_SEQOUTLEN (0x09 << MATH_SRC0_SHIFT) - #define MATH_SRC0_VARSEQINLEN (0x0a << MATH_SRC0_SHIFT) -@@ -1433,7 +1458,6 @@ - #define MATH_SRC1_REG2 (0x02 << MATH_SRC1_SHIFT) - #define MATH_SRC1_REG3 (0x03 << MATH_SRC1_SHIFT) - #define MATH_SRC1_IMM (0x04 << MATH_SRC1_SHIFT) --#define MATH_SRC1_DPOVRD (0x07 << MATH_SRC0_SHIFT) - #define MATH_SRC1_INFIFO (0x0a << MATH_SRC1_SHIFT) - #define MATH_SRC1_OUTFIFO (0x0b << MATH_SRC1_SHIFT) - #define MATH_SRC1_ONE (0x0c << MATH_SRC1_SHIFT) -@@ -1609,13 +1633,28 @@ - #define NFIFOENTRY_PLEN_SHIFT 0 - #define NFIFOENTRY_PLEN_MASK (0xFF << NFIFOENTRY_PLEN_SHIFT) - --/* Append Load Immediate Command */ --#define FD_CMD_APPEND_LOAD_IMMEDIATE 0x80000000 -+/* -+ * PDB internal definitions -+ */ -+ -+/* IPSec ESP CBC Encap/Decap Options */ -+#define PDBOPTS_ESPCBC_ARSNONE 0x00 /* no antireplay window */ -+#define PDBOPTS_ESPCBC_ARS32 0x40 /* 32-entry antireplay window */ -+#define PDBOPTS_ESPCBC_ARS64 0xc0 /* 64-entry antireplay window */ -+#define PDBOPTS_ESPCBC_IVSRC 0x20 /* IV comes from internal random gen */ -+#define PDBOPTS_ESPCBC_ESN 0x10 /* extended sequence included */ -+#define PDBOPTS_ESPCBC_OUTFMT 0x08 /* output only decapsulation (decap) */ -+#define PDBOPTS_ESPCBC_IPHDRSRC 0x08 /* IP header comes from PDB (encap) */ -+#define PDBOPTS_ESPCBC_INCIPHDR 0x04 /* Prepend IP header to output frame */ -+#define PDBOPTS_ESPCBC_IPVSN 0x02 /* process IPv6 header */ -+#define PDBOPTS_ESPCBC_TUNNEL 0x01 /* tunnel mode next-header byte */ -+ -+#define ARC4_BLOCK_SIZE 1 -+#define ARC4_MAX_KEY_SIZE 256 -+#define ARC4_MIN_KEY_SIZE 1 - --/* Set SEQ LIODN equal to the Non-SEQ LIODN for the job */ --#define FD_CMD_SET_SEQ_LIODN_EQUAL_NONSEQ_LIODN 0x40000000 -+#define XCBC_MAC_DIGEST_SIZE 16 -+#define XCBC_MAC_BLOCK_WORDS 16 - --/* Frame Descriptor Command for Replacement Job Descriptor */ --#define FD_CMD_REPLACE_JOB_DESC 0x20000000 - - #endif /* DESC_H */ -diff -Nur linux-4.1.13.orig/drivers/crypto/caam/error.c linux-4.1.13/drivers/crypto/caam/error.c ---- linux-4.1.13.orig/drivers/crypto/caam/error.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/crypto/caam/error.c 2015-11-30 17:56:13.548139857 +0100 -@@ -11,243 +11,264 @@ - #include "jr.h" - #include "error.h" - --static const struct { -- u8 value; -- const char *error_text; --} desc_error_list[] = { -- { 0x00, "No error." }, -- { 0x01, "SGT Length Error. The descriptor is trying to read more data than is contained in the SGT table." }, -- { 0x02, "SGT Null Entry Error." }, -- { 0x03, "Job Ring Control Error. There is a bad value in the Job Ring Control register." }, -- { 0x04, "Invalid Descriptor Command. The Descriptor Command field is invalid." }, -- { 0x05, "Reserved." }, -- { 0x06, "Invalid KEY Command" }, -- { 0x07, "Invalid LOAD Command" }, -- { 0x08, "Invalid STORE Command" }, -- { 0x09, "Invalid OPERATION Command" }, -- { 0x0A, "Invalid FIFO LOAD Command" }, -- { 0x0B, "Invalid FIFO STORE Command" }, -- { 0x0C, "Invalid MOVE/MOVE_LEN Command" }, -- { 0x0D, "Invalid JUMP Command. A nonlocal JUMP Command is invalid because the target is not a Job Header Command, or the jump is from a Trusted Descriptor to a Job Descriptor, or because the target Descriptor contains a Shared Descriptor." }, -- { 0x0E, "Invalid MATH Command" }, -- { 0x0F, "Invalid SIGNATURE Command" }, -- { 0x10, "Invalid Sequence Command. A SEQ IN PTR OR SEQ OUT PTR Command is invalid or a SEQ KEY, SEQ LOAD, SEQ FIFO LOAD, or SEQ FIFO STORE decremented the input or output sequence length below 0. This error may result if a built-in PROTOCOL Command has encountered a malformed PDU." }, -- { 0x11, "Skip data type invalid. The type must be 0xE or 0xF."}, -- { 0x12, "Shared Descriptor Header Error" }, -- { 0x13, "Header Error. Invalid length or parity, or certain other problems." }, -- { 0x14, "Burster Error. Burster has gotten to an illegal state" }, -- { 0x15, "Context Register Length Error. The descriptor is trying to read or write past the end of the Context Register. A SEQ LOAD or SEQ STORE with the VLF bit set was executed with too large a length in the variable length register (VSOL for SEQ STORE or VSIL for SEQ LOAD)." }, -- { 0x16, "DMA Error" }, -- { 0x17, "Reserved." }, -- { 0x1A, "Job failed due to JR reset" }, -- { 0x1B, "Job failed due to Fail Mode" }, -- { 0x1C, "DECO Watchdog timer timeout error" }, -- { 0x1D, "DECO tried to copy a key from another DECO but the other DECO's Key Registers were locked" }, -- { 0x1E, "DECO attempted to copy data from a DECO that had an unmasked Descriptor error" }, -- { 0x1F, "LIODN error. DECO was trying to share from itself or from another DECO but the two Non-SEQ LIODN values didn't match or the 'shared from' DECO's Descriptor required that the SEQ LIODNs be the same and they aren't." }, -- { 0x20, "DECO has completed a reset initiated via the DRR register" }, -- { 0x21, "Nonce error. When using EKT (CCM) key encryption option in the FIFO STORE Command, the Nonce counter reached its maximum value and this encryption mode can no longer be used." }, -- { 0x22, "Meta data is too large (> 511 bytes) for TLS decap (input frame; block ciphers) and IPsec decap (output frame, when doing the next header byte update) and DCRC (output frame)." }, -- { 0x23, "Read Input Frame error" }, -- { 0x24, "JDKEK, TDKEK or TDSK not loaded error" }, -- { 0x80, "DNR (do not run) error" }, -- { 0x81, "undefined protocol command" }, -- { 0x82, "invalid setting in PDB" }, -- { 0x83, "Anti-replay LATE error" }, -- { 0x84, "Anti-replay REPLAY error" }, -- { 0x85, "Sequence number overflow" }, -- { 0x86, "Sigver invalid signature" }, -- { 0x87, "DSA Sign Illegal test descriptor" }, -- { 0x88, "Protocol Format Error - A protocol has seen an error in the format of data received. When running RSA, this means that formatting with random padding was used, and did not follow the form: 0x00, 0x02, 8-to-N bytes of non-zero pad, 0x00, F data." }, -- { 0x89, "Protocol Size Error - A protocol has seen an error in size. When running RSA, pdb size N < (size of F) when no formatting is used; or pdb size N < (F + 11) when formatting is used." }, -- { 0xC1, "Blob Command error: Undefined mode" }, -- { 0xC2, "Blob Command error: Secure Memory Blob mode error" }, -- { 0xC4, "Blob Command error: Black Blob key or input size error" }, -- { 0xC5, "Blob Command error: Invalid key destination" }, -- { 0xC8, "Blob Command error: Trusted/Secure mode error" }, -- { 0xF0, "IPsec TTL or hop limit field either came in as 0, or was decremented to 0" }, -- { 0xF1, "3GPP HFN matches or exceeds the Threshold" }, --}; -- --static const char * const cha_id_list[] = { -- "", -- "AES", -- "DES", -- "ARC4", -- "MDHA", -- "RNG", -- "SNOW f8", -- "Kasumi f8/9", -- "PKHA", -- "CRCA", -- "SNOW f9", -- "ZUCE", -- "ZUCA", --}; -- --static const char * const err_id_list[] = { -- "No error.", -- "Mode error.", -- "Data size error.", -- "Key size error.", -- "PKHA A memory size error.", -- "PKHA B memory size error.", -- "Data arrived out of sequence error.", -- "PKHA divide-by-zero error.", -- "PKHA modulus even error.", -- "DES key parity error.", -- "ICV check failed.", -- "Hardware error.", -- "Unsupported CCM AAD size.", -- "Class 1 CHA is not reset", -- "Invalid CHA combination was selected", -- "Invalid CHA selected.", --}; -- --static const char * const rng_err_id_list[] = { -- "", -- "", -- "", -- "Instantiate", -- "Not instantiated", -- "Test instantiate", -- "Prediction resistance", -- "Prediction resistance and test request", -- "Uninstantiate", -- "Secure key generation", --}; -+#define SPRINTFCAT(str, format, param, max_alloc) \ -+{ \ -+ char *tmp; \ -+ \ -+ tmp = kmalloc(sizeof(format) + max_alloc, GFP_ATOMIC); \ -+ if (likely(tmp)) { \ -+ sprintf(tmp, format, param); \ -+ strcat(str, tmp); \ -+ kfree(tmp); \ -+ } else { \ -+ strcat(str, "kmalloc failure in SPRINTFCAT"); \ -+ } \ -+} - --static void report_ccb_status(struct device *jrdev, const u32 status, -- const char *error) -+static void report_jump_idx(u32 status, char *outstr) - { -- u8 cha_id = (status & JRSTA_CCBERR_CHAID_MASK) >> -- JRSTA_CCBERR_CHAID_SHIFT; -- u8 err_id = status & JRSTA_CCBERR_ERRID_MASK; - u8 idx = (status & JRSTA_DECOERR_INDEX_MASK) >> - JRSTA_DECOERR_INDEX_SHIFT; -- char *idx_str; -- const char *cha_str = "unidentified cha_id value 0x"; -- char cha_err_code[3] = { 0 }; -- const char *err_str = "unidentified err_id value 0x"; -- char err_err_code[3] = { 0 }; - - if (status & JRSTA_DECOERR_JUMP) -- idx_str = "jump tgt desc idx"; -+ strcat(outstr, "jump tgt desc idx "); - else -- idx_str = "desc idx"; -+ strcat(outstr, "desc idx "); - -- if (cha_id < ARRAY_SIZE(cha_id_list)) -- cha_str = cha_id_list[cha_id]; -- else -- snprintf(cha_err_code, sizeof(cha_err_code), "%02x", cha_id); -+ SPRINTFCAT(outstr, "%d: ", idx, sizeof("255")); -+} -+ -+static void report_ccb_status(u32 status, char *outstr) -+{ -+ static const char * const cha_id_list[] = { -+ "", -+ "AES", -+ "DES", -+ "ARC4", -+ "MDHA", -+ "RNG", -+ "SNOW f8", -+ "Kasumi f8/9", -+ "PKHA", -+ "CRCA", -+ "SNOW f9", -+ "ZUCE", -+ "ZUCA", -+ }; -+ static const char * const err_id_list[] = { -+ "No error.", -+ "Mode error.", -+ "Data size error.", -+ "Key size error.", -+ "PKHA A memory size error.", -+ "PKHA B memory size error.", -+ "Data arrived out of sequence error.", -+ "PKHA divide-by-zero error.", -+ "PKHA modulus even error.", -+ "DES key parity error.", -+ "ICV check failed.", -+ "Hardware error.", -+ "Unsupported CCM AAD size.", -+ "Class 1 CHA is not reset", -+ "Invalid CHA combination was selected", -+ "Invalid CHA selected.", -+ }; -+ static const char * const rng_err_id_list[] = { -+ "", -+ "", -+ "", -+ "Instantiate", -+ "Not instantiated", -+ "Test instantiate", -+ "Prediction resistance", -+ "Prediction resistance and test request", -+ "Uninstantiate", -+ "Secure key generation", -+ }; -+ u8 cha_id = (status & JRSTA_CCBERR_CHAID_MASK) >> -+ JRSTA_CCBERR_CHAID_SHIFT; -+ u8 err_id = status & JRSTA_CCBERR_ERRID_MASK; -+ -+ report_jump_idx(status, outstr); -+ -+ if (cha_id < ARRAY_SIZE(cha_id_list)) { -+ SPRINTFCAT(outstr, "%s: ", cha_id_list[cha_id], -+ strlen(cha_id_list[cha_id])); -+ } else { -+ SPRINTFCAT(outstr, "unidentified cha_id value 0x%02x: ", -+ cha_id, sizeof("ff")); -+ } - - if ((cha_id << JRSTA_CCBERR_CHAID_SHIFT) == JRSTA_CCBERR_CHAID_RNG && - err_id < ARRAY_SIZE(rng_err_id_list) && - strlen(rng_err_id_list[err_id])) { - /* RNG-only error */ -- err_str = rng_err_id_list[err_id]; -- } else if (err_id < ARRAY_SIZE(err_id_list)) -- err_str = err_id_list[err_id]; -- else -- snprintf(err_err_code, sizeof(err_err_code), "%02x", err_id); -- -- /* -- * CCB ICV check failures are part of normal operation life; -- * we leave the upper layers to do what they want with them. -- */ -- if (err_id != JRSTA_CCBERR_ERRID_ICVCHK) -- dev_err(jrdev, "%08x: %s: %s %d: %s%s: %s%s\n", -- status, error, idx_str, idx, -- cha_str, cha_err_code, -- err_str, err_err_code); -+ SPRINTFCAT(outstr, "%s", rng_err_id_list[err_id], -+ strlen(rng_err_id_list[err_id])); -+ } else if (err_id < ARRAY_SIZE(err_id_list)) { -+ SPRINTFCAT(outstr, "%s", err_id_list[err_id], -+ strlen(err_id_list[err_id])); -+ } else { -+ SPRINTFCAT(outstr, "unidentified err_id value 0x%02x", -+ err_id, sizeof("ff")); -+ } - } - --static void report_jump_status(struct device *jrdev, const u32 status, -- const char *error) -+static void report_jump_status(u32 status, char *outstr) - { -- dev_err(jrdev, "%08x: %s: %s() not implemented\n", -- status, error, __func__); -+ SPRINTFCAT(outstr, "%s() not implemented", __func__, sizeof(__func__)); - } - --static void report_deco_status(struct device *jrdev, const u32 status, -- const char *error) -+static void report_deco_status(u32 status, char *outstr) - { -- u8 err_id = status & JRSTA_DECOERR_ERROR_MASK; -- u8 idx = (status & JRSTA_DECOERR_INDEX_MASK) >> -- JRSTA_DECOERR_INDEX_SHIFT; -- char *idx_str; -- const char *err_str = "unidentified error value 0x"; -- char err_err_code[3] = { 0 }; -+ static const struct { -+ u8 value; -+ char *error_text; -+ } desc_error_list[] = { -+ { 0x00, "No error." }, -+ { 0x01, "SGT Length Error. The descriptor is trying to read " -+ "more data than is contained in the SGT table." }, -+ { 0x02, "SGT Null Entry Error." }, -+ { 0x03, "Job Ring Control Error. There is a bad value in the " -+ "Job Ring Control register." }, -+ { 0x04, "Invalid Descriptor Command. The Descriptor Command " -+ "field is invalid." }, -+ { 0x05, "Reserved." }, -+ { 0x06, "Invalid KEY Command" }, -+ { 0x07, "Invalid LOAD Command" }, -+ { 0x08, "Invalid STORE Command" }, -+ { 0x09, "Invalid OPERATION Command" }, -+ { 0x0A, "Invalid FIFO LOAD Command" }, -+ { 0x0B, "Invalid FIFO STORE Command" }, -+ { 0x0C, "Invalid MOVE/MOVE_LEN Command" }, -+ { 0x0D, "Invalid JUMP Command. A nonlocal JUMP Command is " -+ "invalid because the target is not a Job Header " -+ "Command, or the jump is from a Trusted Descriptor to " -+ "a Job Descriptor, or because the target Descriptor " -+ "contains a Shared Descriptor." }, -+ { 0x0E, "Invalid MATH Command" }, -+ { 0x0F, "Invalid SIGNATURE Command" }, -+ { 0x10, "Invalid Sequence Command. A SEQ IN PTR OR SEQ OUT PTR " -+ "Command is invalid or a SEQ KEY, SEQ LOAD, SEQ FIFO " -+ "LOAD, or SEQ FIFO STORE decremented the input or " -+ "output sequence length below 0. This error may result " -+ "if a built-in PROTOCOL Command has encountered a " -+ "malformed PDU." }, -+ { 0x11, "Skip data type invalid. The type must be 0xE or 0xF."}, -+ { 0x12, "Shared Descriptor Header Error" }, -+ { 0x13, "Header Error. Invalid length or parity, or certain " -+ "other problems." }, -+ { 0x14, "Burster Error. Burster has gotten to an illegal " -+ "state" }, -+ { 0x15, "Context Register Length Error. The descriptor is " -+ "trying to read or write past the end of the Context " -+ "Register. A SEQ LOAD or SEQ STORE with the VLF bit " -+ "set was executed with too large a length in the " -+ "variable length register (VSOL for SEQ STORE or VSIL " -+ "for SEQ LOAD)." }, -+ { 0x16, "DMA Error" }, -+ { 0x17, "Reserved." }, -+ { 0x1A, "Job failed due to JR reset" }, -+ { 0x1B, "Job failed due to Fail Mode" }, -+ { 0x1C, "DECO Watchdog timer timeout error" }, -+ { 0x1D, "DECO tried to copy a key from another DECO but the " -+ "other DECO's Key Registers were locked" }, -+ { 0x1E, "DECO attempted to copy data from a DECO that had an " -+ "unmasked Descriptor error" }, -+ { 0x1F, "LIODN error. DECO was trying to share from itself or " -+ "from another DECO but the two Non-SEQ LIODN values " -+ "didn't match or the 'shared from' DECO's Descriptor " -+ "required that the SEQ LIODNs be the same and they " -+ "aren't." }, -+ { 0x20, "DECO has completed a reset initiated via the DRR " -+ "register" }, -+ { 0x21, "Nonce error. When using EKT (CCM) key encryption " -+ "option in the FIFO STORE Command, the Nonce counter " -+ "reached its maximum value and this encryption mode " -+ "can no longer be used." }, -+ { 0x22, "Meta data is too large (> 511 bytes) for TLS decap " -+ "(input frame; block ciphers) and IPsec decap (output " -+ "frame, when doing the next header byte update) and " -+ "DCRC (output frame)." }, -+ { 0x23, "Read Input Frame error" }, -+ { 0x24, "JDKEK, TDKEK or TDSK not loaded error" }, -+ { 0x80, "DNR (do not run) error" }, -+ { 0x81, "undefined protocol command" }, -+ { 0x82, "invalid setting in PDB" }, -+ { 0x83, "Anti-replay LATE error" }, -+ { 0x84, "Anti-replay REPLAY error" }, -+ { 0x85, "Sequence number overflow" }, -+ { 0x86, "Sigver invalid signature" }, -+ { 0x87, "DSA Sign Illegal test descriptor" }, -+ { 0x88, "Protocol Format Error - A protocol has seen an error " -+ "in the format of data received. When running RSA, " -+ "this means that formatting with random padding was " -+ "used, and did not follow the form: 0x00, 0x02, 8-to-N " -+ "bytes of non-zero pad, 0x00, F data." }, -+ { 0x89, "Protocol Size Error - A protocol has seen an error in " -+ "size. When running RSA, pdb size N < (size of F) when " -+ "no formatting is used; or pdb size N < (F + 11) when " -+ "formatting is used." }, -+ { 0xC1, "Blob Command error: Undefined mode" }, -+ { 0xC2, "Blob Command error: Secure Memory Blob mode error" }, -+ { 0xC4, "Blob Command error: Black Blob key or input size " -+ "error" }, -+ { 0xC5, "Blob Command error: Invalid key destination" }, -+ { 0xC8, "Blob Command error: Trusted/Secure mode error" }, -+ { 0xF0, "IPsec TTL or hop limit field either came in as 0, " -+ "or was decremented to 0" }, -+ { 0xF1, "3GPP HFN matches or exceeds the Threshold" }, -+ }; -+ u8 desc_error = status & JRSTA_DECOERR_ERROR_MASK; - int i; - -- if (status & JRSTA_DECOERR_JUMP) -- idx_str = "jump tgt desc idx"; -- else -- idx_str = "desc idx"; -+ report_jump_idx(status, outstr); - - for (i = 0; i < ARRAY_SIZE(desc_error_list); i++) -- if (desc_error_list[i].value == err_id) -+ if (desc_error_list[i].value == desc_error) - break; - -- if (i != ARRAY_SIZE(desc_error_list) && desc_error_list[i].error_text) -- err_str = desc_error_list[i].error_text; -- else -- snprintf(err_err_code, sizeof(err_err_code), "%02x", err_id); -- -- dev_err(jrdev, "%08x: %s: %s %d: %s%s\n", -- status, error, idx_str, idx, err_str, err_err_code); -+ if (i != ARRAY_SIZE(desc_error_list) && desc_error_list[i].error_text) { -+ SPRINTFCAT(outstr, "%s", desc_error_list[i].error_text, -+ strlen(desc_error_list[i].error_text)); -+ } else { -+ SPRINTFCAT(outstr, "unidentified error value 0x%02x", -+ desc_error, sizeof("ff")); -+ } - } - --static void report_jr_status(struct device *jrdev, const u32 status, -- const char *error) -+static void report_jr_status(u32 status, char *outstr) - { -- dev_err(jrdev, "%08x: %s: %s() not implemented\n", -- status, error, __func__); -+ SPRINTFCAT(outstr, "%s() not implemented", __func__, sizeof(__func__)); - } - --static void report_cond_code_status(struct device *jrdev, const u32 status, -- const char *error) -+static void report_cond_code_status(u32 status, char *outstr) - { -- dev_err(jrdev, "%08x: %s: %s() not implemented\n", -- status, error, __func__); -+ SPRINTFCAT(outstr, "%s() not implemented", __func__, sizeof(__func__)); - } - --void caam_jr_strstatus(struct device *jrdev, u32 status) -+char *caam_jr_strstatus(char *outstr, u32 status) - { - static const struct stat_src { -- void (*report_ssed)(struct device *jrdev, const u32 status, -- const char *error); -- const char *error; -- } status_src[16] = { -+ void (*report_ssed)(u32 status, char *outstr); -+ char *error; -+ } status_src[] = { - { NULL, "No error" }, - { NULL, NULL }, - { report_ccb_status, "CCB" }, - { report_jump_status, "Jump" }, - { report_deco_status, "DECO" }, -- { NULL, "Queue Manager Interface" }, -+ { NULL, NULL }, - { report_jr_status, "Job Ring" }, - { report_cond_code_status, "Condition Code" }, -- { NULL, NULL }, -- { NULL, NULL }, -- { NULL, NULL }, -- { NULL, NULL }, -- { NULL, NULL }, -- { NULL, NULL }, -- { NULL, NULL }, -- { NULL, NULL }, - }; - u32 ssrc = status >> JRSTA_SSRC_SHIFT; -- const char *error = status_src[ssrc].error; - -- /* -- * If there is an error handling function, call it to report the error. -- * Otherwise print the error source name. -- */ -+ sprintf(outstr, "%s: ", status_src[ssrc].error); -+ - if (status_src[ssrc].report_ssed) -- status_src[ssrc].report_ssed(jrdev, status, error); -- else if (error) -- dev_err(jrdev, "%d: %s\n", ssrc, error); -- else -- dev_err(jrdev, "%d: unknown error source\n", ssrc); -+ status_src[ssrc].report_ssed(status, outstr); -+ -+ return outstr; - } - EXPORT_SYMBOL(caam_jr_strstatus); -diff -Nur linux-4.1.13.orig/drivers/crypto/caam/error.h linux-4.1.13/drivers/crypto/caam/error.h ---- linux-4.1.13.orig/drivers/crypto/caam/error.h 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/crypto/caam/error.h 2015-11-30 17:56:13.548139857 +0100 -@@ -7,5 +7,5 @@ - #ifndef CAAM_ERROR_H - #define CAAM_ERROR_H - #define CAAM_ERROR_STR_MAX 302 --void caam_jr_strstatus(struct device *jrdev, u32 status); -+extern char *caam_jr_strstatus(char *outstr, u32 status); - #endif /* CAAM_ERROR_H */ -diff -Nur linux-4.1.13.orig/drivers/crypto/caam/intern.h linux-4.1.13/drivers/crypto/caam/intern.h ---- linux-4.1.13.orig/drivers/crypto/caam/intern.h 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/crypto/caam/intern.h 2015-11-30 17:56:13.548139857 +0100 -@@ -2,13 +2,19 @@ - * CAAM/SEC 4.x driver backend - * Private/internal definitions between modules - * -- * Copyright 2008-2011 Freescale Semiconductor, Inc. -+ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc. - * - */ - - #ifndef INTERN_H - #define INTERN_H - -+#define JOBR_UNASSIGNED 0 -+#define JOBR_ASSIGNED 1 -+ -+/* Default clock/sample settings for an RNG4 entropy source */ -+#define RNG4_ENT_CLOCKS_SAMPLE 1600 -+ - /* Currently comes from Kconfig param as a ^2 (driver-required) */ - #define JOBR_DEPTH (1 << CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE) - -@@ -37,15 +43,13 @@ - - /* Private sub-storage for a single JobR */ - struct caam_drv_private_jr { -- struct list_head list_node; /* Job Ring device list */ -- struct device *dev; -+ struct device *parentdev; /* points back to controller dev */ -+ struct platform_device *jr_pdev;/* points to platform device for JR */ - int ridx; - struct caam_job_ring __iomem *rregs; /* JobR's register space */ - struct tasklet_struct irqtask; - int irq; /* One per queue */ -- -- /* Number of scatterlist crypt transforms active on the JobR */ -- atomic_t tfm_count ____cacheline_aligned; -+ int assign; /* busy/free */ - - /* Job ring info */ - int ringsize; /* Size of rings (assume input = output) */ -@@ -66,15 +70,20 @@ - struct caam_drv_private { - - struct device *dev; -- struct platform_device **jrpdev; /* Alloc'ed array per sub-device */ -+ struct device *smdev; -+ struct device *secviodev; -+ struct device **jrdev; /* Alloc'ed array per sub-device */ -+ spinlock_t jr_alloc_lock; - struct platform_device *pdev; - - /* Physical-presence section */ -- struct caam_ctrl __iomem *ctrl; /* controller region */ -- struct caam_deco __iomem *deco; /* DECO/CCB views */ -- struct caam_assurance __iomem *assure; -- struct caam_queue_if __iomem *qi; /* QI control region */ -- struct caam_job_ring __iomem *jr[4]; /* JobR's register space */ -+ struct caam_ctrl *ctrl; /* controller region */ -+ struct caam_deco **deco; /* DECO/CCB views */ -+ struct caam_assurance *ac; -+ struct caam_queue_if *qi; /* QI control region */ -+ struct snvs_full __iomem *snvs; /* SNVS HP+LP register space */ -+ dma_addr_t __iomem *sm_base; /* Secure memory storage base */ -+ u32 sm_size; - - /* - * Detected geometry block. Filled in from device tree if powerpc, -@@ -83,14 +92,22 @@ - u8 total_jobrs; /* Total Job Rings in device */ - u8 qi_present; /* Nonzero if QI present in device */ - int secvio_irq; /* Security violation interrupt number */ -- int virt_en; /* Virtualization enabled in CAAM */ -- --#define RNG4_MAX_HANDLES 2 -- /* RNG4 block */ -- u32 rng4_sh_init; /* This bitmap shows which of the State -- Handles of the RNG4 block are initialized -- by this driver */ -+ int rng_inst; /* Total instantiated RNGs */ - -+ /* which jr allocated to scatterlist crypto */ -+ atomic_t tfm_count ____cacheline_aligned; -+ int num_jrs_for_algapi; -+ struct device **algapi_jr; -+ /* list of registered crypto algorithms (mk generic context handle?) */ -+ struct list_head alg_list; -+ /* list of registered hash algorithms (mk generic context handle?) */ -+ struct list_head hash_list; -+ -+#ifdef CONFIG_ARM -+ struct clk *caam_ipg; -+ struct clk *caam_mem; -+ struct clk *caam_aclk; -+#endif - /* - * debugfs entries for developer view into driver/device - * variables at runtime. -diff -Nur linux-4.1.13.orig/drivers/crypto/caam/jr.c linux-4.1.13/drivers/crypto/caam/jr.c ---- linux-4.1.13.orig/drivers/crypto/caam/jr.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/crypto/caam/jr.c 2015-11-30 17:56:13.548139857 +0100 -@@ -2,125 +2,15 @@ - * CAAM/SEC 4.x transport/backend driver - * JobR backend functionality - * -- * Copyright 2008-2012 Freescale Semiconductor, Inc. -+ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc. - */ - --#include --#include -- - #include "compat.h" - #include "regs.h" - #include "jr.h" - #include "desc.h" - #include "intern.h" - --struct jr_driver_data { -- /* List of Physical JobR's with the Driver */ -- struct list_head jr_list; -- spinlock_t jr_alloc_lock; /* jr_list lock */ --} ____cacheline_aligned; -- --static struct jr_driver_data driver_data; -- --static int caam_reset_hw_jr(struct device *dev) --{ -- struct caam_drv_private_jr *jrp = dev_get_drvdata(dev); -- unsigned int timeout = 100000; -- -- /* -- * mask interrupts since we are going to poll -- * for reset completion status -- */ -- setbits32(&jrp->rregs->rconfig_lo, JRCFG_IMSK); -- -- /* initiate flush (required prior to reset) */ -- wr_reg32(&jrp->rregs->jrcommand, JRCR_RESET); -- while (((rd_reg32(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_MASK) == -- JRINT_ERR_HALT_INPROGRESS) && --timeout) -- cpu_relax(); -- -- if ((rd_reg32(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_MASK) != -- JRINT_ERR_HALT_COMPLETE || timeout == 0) { -- dev_err(dev, "failed to flush job ring %d\n", jrp->ridx); -- return -EIO; -- } -- -- /* initiate reset */ -- timeout = 100000; -- wr_reg32(&jrp->rregs->jrcommand, JRCR_RESET); -- while ((rd_reg32(&jrp->rregs->jrcommand) & JRCR_RESET) && --timeout) -- cpu_relax(); -- -- if (timeout == 0) { -- dev_err(dev, "failed to reset job ring %d\n", jrp->ridx); -- return -EIO; -- } -- -- /* unmask interrupts */ -- clrbits32(&jrp->rregs->rconfig_lo, JRCFG_IMSK); -- -- return 0; --} -- --/* -- * Shutdown JobR independent of platform property code -- */ --int caam_jr_shutdown(struct device *dev) --{ -- struct caam_drv_private_jr *jrp = dev_get_drvdata(dev); -- dma_addr_t inpbusaddr, outbusaddr; -- int ret; -- -- ret = caam_reset_hw_jr(dev); -- -- tasklet_kill(&jrp->irqtask); -- -- /* Release interrupt */ -- free_irq(jrp->irq, dev); -- -- /* Free rings */ -- inpbusaddr = rd_reg64(&jrp->rregs->inpring_base); -- outbusaddr = rd_reg64(&jrp->rregs->outring_base); -- dma_free_coherent(dev, sizeof(dma_addr_t) * JOBR_DEPTH, -- jrp->inpring, inpbusaddr); -- dma_free_coherent(dev, sizeof(struct jr_outentry) * JOBR_DEPTH, -- jrp->outring, outbusaddr); -- kfree(jrp->entinfo); -- -- return ret; --} -- --static int caam_jr_remove(struct platform_device *pdev) --{ -- int ret; -- struct device *jrdev; -- struct caam_drv_private_jr *jrpriv; -- -- jrdev = &pdev->dev; -- jrpriv = dev_get_drvdata(jrdev); -- -- /* -- * Return EBUSY if job ring already allocated. -- */ -- if (atomic_read(&jrpriv->tfm_count)) { -- dev_err(jrdev, "Device is busy\n"); -- return -EBUSY; -- } -- -- /* Remove the node from Physical JobR list maintained by driver */ -- spin_lock(&driver_data.jr_alloc_lock); -- list_del(&jrpriv->list_node); -- spin_unlock(&driver_data.jr_alloc_lock); -- -- /* Release ring */ -- ret = caam_jr_shutdown(jrdev); -- if (ret) -- dev_err(jrdev, "Failed to shut down job ring\n"); -- irq_dispose_mapping(jrpriv->irq); -- -- return ret; --} -- - /* Main per-ring interrupt handler */ - static irqreturn_t caam_jr_interrupt(int irq, void *st_dev) - { -@@ -168,6 +58,9 @@ - void (*usercall)(struct device *dev, u32 *desc, u32 status, void *arg); - u32 *userdesc, userstatus; - void *userarg; -+ dma_addr_t outbusaddr; -+ -+ outbusaddr = rd_reg64(&jrp->rregs->outring_base); - - while (rd_reg32(&jrp->rregs->outring_used)) { - -@@ -177,10 +70,15 @@ - - sw_idx = tail = jrp->tail; - hw_idx = jrp->out_ring_read_index; -+ dma_sync_single_for_cpu(dev, outbusaddr, -+ sizeof(struct jr_outentry) * JOBR_DEPTH, -+ DMA_FROM_DEVICE); - - for (i = 0; CIRC_CNT(head, tail + i, JOBR_DEPTH) >= 1; i++) { - sw_idx = (tail + i) & (JOBR_DEPTH - 1); - -+ smp_read_barrier_depends(); -+ - if (jrp->outring[hw_idx].desc == - jrp->entinfo[sw_idx].desc_addr_dma) - break; /* found */ -@@ -202,6 +100,8 @@ - userdesc = jrp->entinfo[sw_idx].desc_addr_virt; - userstatus = jrp->outring[hw_idx].jrstatus; - -+ smp_mb(); -+ - /* set done */ - wr_reg32(&jrp->rregs->outring_rmvd, 1); - -@@ -216,6 +116,7 @@ - if (sw_idx == tail) { - do { - tail = (tail + 1) & (JOBR_DEPTH - 1); -+ smp_read_barrier_depends(); - } while (CIRC_CNT(head, tail, JOBR_DEPTH) >= 1 && - jrp->entinfo[tail].desc_addr_dma == 0); - -@@ -233,57 +134,70 @@ - } - - /** -- * caam_jr_alloc() - Alloc a job ring for someone to use as needed. -- * -- * returns : pointer to the newly allocated physical -- * JobR dev can be written to if successful. -+ * caam_jr_register() - Alloc a ring for someone to use as needed. Returns -+ * an ordinal of the rings allocated, else returns -ENODEV if no rings -+ * are available. -+ * @ctrldev: points to the controller level dev (parent) that -+ * owns rings available for use. -+ * @dev: points to where a pointer to the newly allocated queue's -+ * dev can be written to if successful. - **/ --struct device *caam_jr_alloc(void) -+int caam_jr_register(struct device *ctrldev, struct device **rdev) - { -- struct caam_drv_private_jr *jrpriv, *min_jrpriv = NULL; -- struct device *dev = NULL; -- int min_tfm_cnt = INT_MAX; -- int tfm_cnt; -- -- spin_lock(&driver_data.jr_alloc_lock); -- -- if (list_empty(&driver_data.jr_list)) { -- spin_unlock(&driver_data.jr_alloc_lock); -- return ERR_PTR(-ENODEV); -- } -- -- list_for_each_entry(jrpriv, &driver_data.jr_list, list_node) { -- tfm_cnt = atomic_read(&jrpriv->tfm_count); -- if (tfm_cnt < min_tfm_cnt) { -- min_tfm_cnt = tfm_cnt; -- min_jrpriv = jrpriv; -+ struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev); -+ struct caam_drv_private_jr *jrpriv = NULL; -+ int ring; -+ -+ /* Lock, if free ring - assign, unlock */ -+ spin_lock(&ctrlpriv->jr_alloc_lock); -+ for (ring = 0; ring < ctrlpriv->total_jobrs; ring++) { -+ jrpriv = dev_get_drvdata(ctrlpriv->jrdev[ring]); -+ if (jrpriv->assign == JOBR_UNASSIGNED) { -+ jrpriv->assign = JOBR_ASSIGNED; -+ *rdev = ctrlpriv->jrdev[ring]; -+ spin_unlock(&ctrlpriv->jr_alloc_lock); -+ return ring; - } -- if (!min_tfm_cnt) -- break; - } - -- if (min_jrpriv) { -- atomic_inc(&min_jrpriv->tfm_count); -- dev = min_jrpriv->dev; -- } -- spin_unlock(&driver_data.jr_alloc_lock); -+ /* If assigned, write dev where caller needs it */ -+ spin_unlock(&ctrlpriv->jr_alloc_lock); -+ *rdev = NULL; - -- return dev; -+ return -ENODEV; - } --EXPORT_SYMBOL(caam_jr_alloc); -+EXPORT_SYMBOL(caam_jr_register); - - /** -- * caam_jr_free() - Free the Job Ring -- * @rdev - points to the dev that identifies the Job ring to -- * be released. -+ * caam_jr_deregister() - Deregister an API and release the queue. -+ * Returns 0 if OK, -EBUSY if queue still contains pending entries -+ * or unprocessed results at the time of the call -+ * @dev - points to the dev that identifies the queue to -+ * be released. - **/ --void caam_jr_free(struct device *rdev) -+int caam_jr_deregister(struct device *rdev) - { - struct caam_drv_private_jr *jrpriv = dev_get_drvdata(rdev); -+ struct caam_drv_private *ctrlpriv; -+ -+ /* Get the owning controller's private space */ -+ ctrlpriv = dev_get_drvdata(jrpriv->parentdev); -+ -+ /* -+ * Make sure ring empty before release -+ */ -+ if (rd_reg32(&jrpriv->rregs->outring_used) || -+ (rd_reg32(&jrpriv->rregs->inpring_avail) != JOBR_DEPTH)) -+ return -EBUSY; - -- atomic_dec(&jrpriv->tfm_count); -+ /* Release ring */ -+ spin_lock(&ctrlpriv->jr_alloc_lock); -+ jrpriv->assign = JOBR_UNASSIGNED; -+ spin_unlock(&ctrlpriv->jr_alloc_lock); -+ -+ return 0; - } --EXPORT_SYMBOL(caam_jr_free); -+EXPORT_SYMBOL(caam_jr_deregister); - - /** - * caam_jr_enqueue() - Enqueue a job descriptor head. Returns 0 if OK, -@@ -321,7 +235,7 @@ - struct caam_drv_private_jr *jrp = dev_get_drvdata(dev); - struct caam_jrentry_info *head_entry; - int head, tail, desc_size; -- dma_addr_t desc_dma; -+ dma_addr_t desc_dma, inpbusaddr; - - desc_size = (*desc & HDR_JD_LENGTH_MASK) * sizeof(u32); - desc_dma = dma_map_single(dev, desc, desc_size, DMA_TO_DEVICE); -@@ -330,6 +244,13 @@ - return -EIO; - } - -+ dma_sync_single_for_device(dev, desc_dma, desc_size, DMA_TO_DEVICE); -+ -+ inpbusaddr = rd_reg64(&jrp->rregs->inpring_base); -+ dma_sync_single_for_device(dev, inpbusaddr, -+ sizeof(dma_addr_t) * JOBR_DEPTH, -+ DMA_TO_DEVICE); -+ - spin_lock_bh(&jrp->inplock); - - head = jrp->head; -@@ -351,12 +272,18 @@ - - jrp->inpring[jrp->inp_ring_write_index] = desc_dma; - -+ dma_sync_single_for_device(dev, inpbusaddr, -+ sizeof(dma_addr_t) * JOBR_DEPTH, -+ DMA_TO_DEVICE); -+ - smp_wmb(); - - jrp->inp_ring_write_index = (jrp->inp_ring_write_index + 1) & - (JOBR_DEPTH - 1); - jrp->head = (head + 1) & (JOBR_DEPTH - 1); - -+ wmb(); -+ - wr_reg32(&jrp->rregs->inpring_jobadd, 1); - - spin_unlock_bh(&jrp->inplock); -@@ -365,6 +292,46 @@ - } - EXPORT_SYMBOL(caam_jr_enqueue); - -+static int caam_reset_hw_jr(struct device *dev) -+{ -+ struct caam_drv_private_jr *jrp = dev_get_drvdata(dev); -+ unsigned int timeout = 100000; -+ -+ /* -+ * mask interrupts since we are going to poll -+ * for reset completion status -+ */ -+ setbits32(&jrp->rregs->rconfig_lo, JRCFG_IMSK); -+ -+ /* initiate flush (required prior to reset) */ -+ wr_reg32(&jrp->rregs->jrcommand, JRCR_RESET); -+ while (((rd_reg32(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_MASK) == -+ JRINT_ERR_HALT_INPROGRESS) && --timeout) -+ cpu_relax(); -+ -+ if ((rd_reg32(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_MASK) != -+ JRINT_ERR_HALT_COMPLETE || timeout == 0) { -+ dev_err(dev, "failed to flush job ring %d\n", jrp->ridx); -+ return -EIO; -+ } -+ -+ /* initiate reset */ -+ timeout = 100000; -+ wr_reg32(&jrp->rregs->jrcommand, JRCR_RESET); -+ while ((rd_reg32(&jrp->rregs->jrcommand) & JRCR_RESET) && --timeout) -+ cpu_relax(); -+ -+ if (timeout == 0) { -+ dev_err(dev, "failed to reset job ring %d\n", jrp->ridx); -+ return -EIO; -+ } -+ -+ /* unmask interrupts */ -+ clrbits32(&jrp->rregs->rconfig_lo, JRCFG_IMSK); -+ -+ return 0; -+} -+ - /* - * Init JobR independent of platform property detection - */ -@@ -380,32 +347,34 @@ - - /* Connect job ring interrupt handler. */ - error = request_irq(jrp->irq, caam_jr_interrupt, IRQF_SHARED, -- dev_name(dev), dev); -+ "caam-jobr", dev); - if (error) { - dev_err(dev, "can't connect JobR %d interrupt (%d)\n", - jrp->ridx, jrp->irq); -- goto out_kill_deq; -+ irq_dispose_mapping(jrp->irq); -+ jrp->irq = 0; -+ return -EINVAL; - } - - error = caam_reset_hw_jr(dev); - if (error) -- goto out_free_irq; -+ return error; - -- error = -ENOMEM; - jrp->inpring = dma_alloc_coherent(dev, sizeof(dma_addr_t) * JOBR_DEPTH, - &inpbusaddr, GFP_KERNEL); -- if (!jrp->inpring) -- goto out_free_irq; - - jrp->outring = dma_alloc_coherent(dev, sizeof(struct jr_outentry) * - JOBR_DEPTH, &outbusaddr, GFP_KERNEL); -- if (!jrp->outring) -- goto out_free_inpring; - - jrp->entinfo = kzalloc(sizeof(struct caam_jrentry_info) * JOBR_DEPTH, - GFP_KERNEL); -- if (!jrp->entinfo) -- goto out_free_outring; -+ -+ if ((jrp->inpring == NULL) || (jrp->outring == NULL) || -+ (jrp->entinfo == NULL)) { -+ dev_err(dev, "can't allocate job rings for %d\n", -+ jrp->ridx); -+ return -ENOMEM; -+ } - - for (i = 0; i < JOBR_DEPTH; i++) - jrp->entinfo[i].desc_addr_dma = !0; -@@ -431,120 +400,123 @@ - (JOBR_INTC_COUNT_THLD << JRCFG_ICDCT_SHIFT) | - (JOBR_INTC_TIME_THLD << JRCFG_ICTT_SHIFT)); - -+ jrp->assign = JOBR_UNASSIGNED; - return 0; -+} - --out_free_outring: -- dma_free_coherent(dev, sizeof(struct jr_outentry) * JOBR_DEPTH, -- jrp->outring, outbusaddr); --out_free_inpring: -+/* -+ * Shutdown JobR independent of platform property code -+ */ -+int caam_jr_shutdown(struct device *dev) -+{ -+ struct caam_drv_private_jr *jrp = dev_get_drvdata(dev); -+ dma_addr_t inpbusaddr, outbusaddr; -+ int ret; -+ -+ ret = caam_reset_hw_jr(dev); -+ -+ tasklet_kill(&jrp->irqtask); -+ -+ /* Release interrupt */ -+ free_irq(jrp->irq, dev); -+ -+ /* Free rings */ -+ inpbusaddr = rd_reg64(&jrp->rregs->inpring_base); -+ outbusaddr = rd_reg64(&jrp->rregs->outring_base); - dma_free_coherent(dev, sizeof(dma_addr_t) * JOBR_DEPTH, - jrp->inpring, inpbusaddr); -- dev_err(dev, "can't allocate job rings for %d\n", jrp->ridx); --out_free_irq: -- free_irq(jrp->irq, dev); --out_kill_deq: -- tasklet_kill(&jrp->irqtask); -- return error; --} -+ dma_free_coherent(dev, sizeof(struct jr_outentry) * JOBR_DEPTH, -+ jrp->outring, outbusaddr); -+ kfree(jrp->entinfo); -+ of_device_unregister(jrp->jr_pdev); - -+ return ret; -+} - - /* -- * Probe routine for each detected JobR subsystem. -+ * Probe routine for each detected JobR subsystem. It assumes that -+ * property detection was picked up externally. - */ --static int caam_jr_probe(struct platform_device *pdev) -+int caam_jr_probe(struct platform_device *pdev, struct device_node *np, -+ int ring) - { -- struct device *jrdev; -- struct device_node *nprop; -- struct caam_job_ring __iomem *ctrl; -+ struct device *ctrldev, *jrdev; -+ struct platform_device *jr_pdev; -+ struct caam_drv_private *ctrlpriv; - struct caam_drv_private_jr *jrpriv; -- static int total_jobrs; -+ const __be32 *jroffset_addr; -+ u32 jroffset; - int error; - -- jrdev = &pdev->dev; -- jrpriv = devm_kmalloc(jrdev, sizeof(struct caam_drv_private_jr), -- GFP_KERNEL); -- if (!jrpriv) -+ ctrldev = &pdev->dev; -+ ctrlpriv = dev_get_drvdata(ctrldev); -+ -+ jrpriv = kmalloc(sizeof(struct caam_drv_private_jr), -+ GFP_KERNEL); -+ if (jrpriv == NULL) { -+ dev_err(ctrldev, "can't alloc private mem for job ring %d\n", -+ ring); - return -ENOMEM; -+ } -+ jrpriv->parentdev = ctrldev; /* point back to parent */ -+ jrpriv->ridx = ring; /* save ring identity relative to detection */ - -- dev_set_drvdata(jrdev, jrpriv); -+ /* -+ * Derive a pointer to the detected JobRs regs -+ * Driver has already iomapped the entire space, we just -+ * need to add in the offset to this JobR. Don't know if I -+ * like this long-term, but it'll run -+ */ -+ jroffset_addr = of_get_property(np, "reg", NULL); - -- /* save ring identity relative to detection */ -- jrpriv->ridx = total_jobrs++; -+ if (jroffset_addr == NULL) { -+ kfree(jrpriv); -+ return -EINVAL; -+ } - -- nprop = pdev->dev.of_node; -- /* Get configuration properties from device tree */ -- /* First, get register page */ -- ctrl = of_iomap(nprop, 0); -- if (!ctrl) { -- dev_err(jrdev, "of_iomap() failed\n"); -- return -ENOMEM; -+ /* -+ * Fix the endianness of this value read from the device -+ * tree if running on ARM. -+ */ -+ jroffset = be32_to_cpup(jroffset_addr); -+ -+ jrpriv->rregs = (struct caam_job_ring __iomem *)((void *)ctrlpriv->ctrl -+ + jroffset); -+ -+ /* Build a local dev for each detected queue */ -+ jr_pdev = of_platform_device_create(np, NULL, ctrldev); -+ if (jr_pdev == NULL) { -+ kfree(jrpriv); -+ return -EINVAL; - } - -- jrpriv->rregs = (struct caam_job_ring __force *)ctrl; -+ jrpriv->jr_pdev = jr_pdev; -+ jrdev = &jr_pdev->dev; -+ dev_set_drvdata(jrdev, jrpriv); -+ ctrlpriv->jrdev[ring] = jrdev; - - if (sizeof(dma_addr_t) == sizeof(u64)) -- if (of_device_is_compatible(nprop, "fsl,sec-v5.0-job-ring")) -- dma_set_mask_and_coherent(jrdev, DMA_BIT_MASK(40)); -+ if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring")) -+ dma_set_mask(jrdev, DMA_BIT_MASK(40)); - else -- dma_set_mask_and_coherent(jrdev, DMA_BIT_MASK(36)); -+ dma_set_mask(jrdev, DMA_BIT_MASK(36)); - else -- dma_set_mask_and_coherent(jrdev, DMA_BIT_MASK(32)); -+ dma_set_mask(jrdev, DMA_BIT_MASK(32)); - - /* Identify the interrupt */ -- jrpriv->irq = irq_of_parse_and_map(nprop, 0); -+ jrpriv->irq = of_irq_to_resource(np, 0, NULL); -+ if (jrpriv->irq <= 0) { -+ kfree(jrpriv); -+ return -EINVAL; -+ } - - /* Now do the platform independent part */ - error = caam_jr_init(jrdev); /* now turn on hardware */ - if (error) { -- irq_dispose_mapping(jrpriv->irq); -+ of_device_unregister(jr_pdev); -+ kfree(jrpriv); - return error; - } - -- jrpriv->dev = jrdev; -- spin_lock(&driver_data.jr_alloc_lock); -- list_add_tail(&jrpriv->list_node, &driver_data.jr_list); -- spin_unlock(&driver_data.jr_alloc_lock); -- -- atomic_set(&jrpriv->tfm_count, 0); -- -- return 0; --} -- --static struct of_device_id caam_jr_match[] = { -- { -- .compatible = "fsl,sec-v4.0-job-ring", -- }, -- { -- .compatible = "fsl,sec4.0-job-ring", -- }, -- {}, --}; --MODULE_DEVICE_TABLE(of, caam_jr_match); -- --static struct platform_driver caam_jr_driver = { -- .driver = { -- .name = "caam_jr", -- .of_match_table = caam_jr_match, -- }, -- .probe = caam_jr_probe, -- .remove = caam_jr_remove, --}; -- --static int __init jr_driver_init(void) --{ -- spin_lock_init(&driver_data.jr_alloc_lock); -- INIT_LIST_HEAD(&driver_data.jr_list); -- return platform_driver_register(&caam_jr_driver); --} -- --static void __exit jr_driver_exit(void) --{ -- platform_driver_unregister(&caam_jr_driver); -+ return error; - } -- --module_init(jr_driver_init); --module_exit(jr_driver_exit); -- --MODULE_LICENSE("GPL"); --MODULE_DESCRIPTION("FSL CAAM JR request backend"); --MODULE_AUTHOR("Freescale Semiconductor - NMG/STC"); -diff -Nur linux-4.1.13.orig/drivers/crypto/caam/jr.h linux-4.1.13/drivers/crypto/caam/jr.h ---- linux-4.1.13.orig/drivers/crypto/caam/jr.h 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/crypto/caam/jr.h 2015-11-30 17:56:13.548139857 +0100 -@@ -1,18 +1,22 @@ - /* - * CAAM public-level include definitions for the JobR backend - * -- * Copyright 2008-2011 Freescale Semiconductor, Inc. -+ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc. - */ - - #ifndef JR_H - #define JR_H - - /* Prototypes for backend-level services exposed to APIs */ --struct device *caam_jr_alloc(void); --void caam_jr_free(struct device *rdev); -+int caam_jr_register(struct device *ctrldev, struct device **rdev); -+int caam_jr_deregister(struct device *rdev); - int caam_jr_enqueue(struct device *dev, u32 *desc, - void (*cbk)(struct device *dev, u32 *desc, u32 status, - void *areq), - void *areq); - -+extern int caam_jr_probe(struct platform_device *pdev, struct device_node *np, -+ int ring); -+extern int caam_jr_shutdown(struct device *dev); -+extern struct device *caam_get_jrdev(void); - #endif /* JR_H */ -diff -Nur linux-4.1.13.orig/drivers/crypto/caam/Kconfig linux-4.1.13/drivers/crypto/caam/Kconfig ---- linux-4.1.13.orig/drivers/crypto/caam/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/crypto/caam/Kconfig 2015-11-30 17:56:13.548139857 +0100 -@@ -1,32 +1,19 @@ - config CRYPTO_DEV_FSL_CAAM - tristate "Freescale CAAM-Multicore driver backend" -- depends on FSL_SOC -+ depends on FSL_SOC || ARCH_MXC - help - Enables the driver module for Freescale's Cryptographic Accelerator - and Assurance Module (CAAM), also known as the SEC version 4 (SEC4). -- This module creates job ring devices, and configures h/w -+ This module adds a job ring operation interface, and configures h/w - to operate as a DPAA component automatically, depending - on h/w feature availability. - - To compile this driver as a module, choose M here: the module - will be called caam. - --config CRYPTO_DEV_FSL_CAAM_JR -- tristate "Freescale CAAM Job Ring driver backend" -- depends on CRYPTO_DEV_FSL_CAAM -- default y -- help -- Enables the driver module for Job Rings which are part of -- Freescale's Cryptographic Accelerator -- and Assurance Module (CAAM). This module adds a job ring operation -- interface. -- -- To compile this driver as a module, choose M here: the module -- will be called caam_jr. -- - config CRYPTO_DEV_FSL_CAAM_RINGSIZE - int "Job Ring size" -- depends on CRYPTO_DEV_FSL_CAAM_JR -+ depends on CRYPTO_DEV_FSL_CAAM - range 2 9 - default "9" - help -@@ -44,7 +31,7 @@ - - config CRYPTO_DEV_FSL_CAAM_INTC - bool "Job Ring interrupt coalescing" -- depends on CRYPTO_DEV_FSL_CAAM_JR -+ depends on CRYPTO_DEV_FSL_CAAM - default n - help - Enable the Job Ring's interrupt coalescing feature. -@@ -75,7 +62,7 @@ - - config CRYPTO_DEV_FSL_CAAM_CRYPTO_API - tristate "Register algorithm implementations with the Crypto API" -- depends on CRYPTO_DEV_FSL_CAAM && CRYPTO_DEV_FSL_CAAM_JR -+ depends on CRYPTO_DEV_FSL_CAAM - default y - select CRYPTO_ALGAPI - select CRYPTO_AUTHENC -@@ -89,7 +76,7 @@ - - config CRYPTO_DEV_FSL_CAAM_AHASH_API - tristate "Register hash algorithm implementations with Crypto API" -- depends on CRYPTO_DEV_FSL_CAAM && CRYPTO_DEV_FSL_CAAM_JR -+ depends on CRYPTO_DEV_FSL_CAAM - default y - select CRYPTO_HASH - help -@@ -101,7 +88,7 @@ - - config CRYPTO_DEV_FSL_CAAM_RNG_API - tristate "Register caam device for hwrng API" -- depends on CRYPTO_DEV_FSL_CAAM && CRYPTO_DEV_FSL_CAAM_JR -+ depends on CRYPTO_DEV_FSL_CAAM - default y - select CRYPTO_RNG - select HW_RANDOM -@@ -112,6 +99,54 @@ - To compile this as a module, choose M here: the module - will be called caamrng. - -+config CRYPTO_DEV_FSL_CAAM_RNG_TEST -+ boolean "Test caam rng" -+ depends on CRYPTO_DEV_FSL_CAAM_RNG_API -+ default n -+ help -+ Selecting this will enable self-test for caam rng. -+ -+config CRYPTO_DEV_FSL_CAAM_SM -+ tristate "CAAM Secure Memory / Keystore API (EXPERIMENTAL)" -+ default n -+ help -+ Enables use of a prototype kernel-level Keystore API with CAAM -+ Secure Memory for insertion/extraction of bus-protected secrets. -+ -+config CRYPTO_DEV_FSL_CAAM_SM_SLOTSIZE -+ int "Size of each keystore slot in Secure Memory" -+ depends on CRYPTO_DEV_FSL_CAAM_SM -+ range 5 9 -+ default 7 -+ help -+ Select size of allocation units to divide Secure Memory pages into -+ (the size of a "slot" as referenced inside the API code). -+ Established as powers of two. -+ Examples: -+ 5 => 32 bytes -+ 6 => 64 bytes -+ 7 => 128 bytes -+ 8 => 256 bytes -+ 9 => 512 bytes -+ -+config CRYPTO_DEV_FSL_CAAM_SM_TEST -+ tristate "CAAM Secure Memory - Keystore Test/Example (EXPERIMENTAL)" -+ depends on CRYPTO_DEV_FSL_CAAM_SM -+ default n -+ help -+ Example thread to exercise the Keystore API and to verify that -+ stored and recovered secrets can be used for general purpose -+ encryption/decryption. -+ -+config CRYPTO_DEV_FSL_CAAM_SECVIO -+ tristate "CAAM/SNVS Security Violation Handler (EXPERIMENTAL)" -+ depends on CRYPTO_DEV_FSL_CAAM -+ default n -+ help -+ Enables installation of an interrupt handler with registrable -+ handler functions which can be specified to act on the consequences -+ of a security violation. -+ - config CRYPTO_DEV_FSL_CAAM_DEBUG - bool "Enable debug output in CAAM driver" - depends on CRYPTO_DEV_FSL_CAAM -@@ -119,3 +154,19 @@ - help - Selecting this will enable printing of various debug - information in the CAAM driver. -+ -+config CRYPTO_DEV_FSL_CAAM_KEYBLOB -+ tristate "Freescale CAAM memory keyblob driver backend" -+ depends on CRYPTO_DEV_FSL_CAAM -+ depends on CRYPTO_DEV_FSL_CAAM_JR -+ default y -+ help -+ Enables the driver module for Key Blob which are part of -+ Freescale's Cryptographic Accelerator -+ and Assurance Module (CAAM). This module adds a key blob operation -+ interface. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called caam_keyblob. -+ -+ -diff -Nur linux-4.1.13.orig/drivers/crypto/caam/key_gen.c linux-4.1.13/drivers/crypto/caam/key_gen.c ---- linux-4.1.13.orig/drivers/crypto/caam/key_gen.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/crypto/caam/key_gen.c 2015-11-30 17:56:13.552139590 +0100 -@@ -1,7 +1,7 @@ - /* - * CAAM/SEC 4.x functions for handling key-generation jobs - * -- * Copyright 2008-2011 Freescale Semiconductor, Inc. -+ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc. - * - */ - #include "compat.h" -@@ -19,8 +19,11 @@ - dev_err(dev, "%s %d: err 0x%x\n", __func__, __LINE__, err); - #endif - -- if (err) -- caam_jr_strstatus(dev, err); -+ if (err) { -+ char tmp[CAAM_ERROR_STR_MAX]; -+ -+ dev_err(dev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err)); -+ } - - res->err = err; - -@@ -48,29 +51,24 @@ - u32 *desc; - struct split_key_result result; - dma_addr_t dma_addr_in, dma_addr_out; -- int ret = -ENOMEM; -+ int ret = 0; - - desc = kmalloc(CAAM_CMD_SZ * 6 + CAAM_PTR_SZ * 2, GFP_KERNEL | GFP_DMA); - if (!desc) { - dev_err(jrdev, "unable to allocate key input memory\n"); -- return ret; -+ return -ENOMEM; - } - -+ init_job_desc(desc, 0); -+ - dma_addr_in = dma_map_single(jrdev, (void *)key_in, keylen, - DMA_TO_DEVICE); - if (dma_mapping_error(jrdev, dma_addr_in)) { - dev_err(jrdev, "unable to map key input memory\n"); -- goto out_free; -+ kfree(desc); -+ return -ENOMEM; - } -- -- dma_addr_out = dma_map_single(jrdev, key_out, split_key_pad_len, -- DMA_FROM_DEVICE); -- if (dma_mapping_error(jrdev, dma_addr_out)) { -- dev_err(jrdev, "unable to map key output memory\n"); -- goto out_unmap_in; -- } -- -- init_job_desc(desc, 0); -+ dma_sync_single_for_device(jrdev, dma_addr_in, keylen, DMA_TO_DEVICE); - append_key(desc, dma_addr_in, keylen, CLASS_2 | KEY_DEST_CLASS_REG); - - /* Sets MDHA up into an HMAC-INIT */ -@@ -91,9 +89,9 @@ - LDST_CLASS_2_CCB | FIFOST_TYPE_SPLIT_KEK); - - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "ctx.key@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "ctx.key@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, key_in, keylen, 1); -- print_hex_dump(KERN_ERR, "jobdesc@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "jobdesc@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, desc, desc_bytes(desc), 1); - #endif - -@@ -106,12 +104,13 @@ - wait_for_completion_interruptible(&result.completion); - ret = result.err; - #ifdef DEBUG -- print_hex_dump(KERN_ERR, "ctx.key@"__stringify(__LINE__)": ", -+ print_hex_dump(KERN_ERR, "ctx.key@"xstr(__LINE__)": ", - DUMP_PREFIX_ADDRESS, 16, 4, key_out, - split_key_pad_len, 1); - #endif - } -- -+ dma_sync_single_for_cpu(jrdev, dma_addr_out, split_key_pad_len, -+ DMA_FROM_DEVICE); - dma_unmap_single(jrdev, dma_addr_out, split_key_pad_len, - DMA_FROM_DEVICE); - out_unmap_in: -diff -Nur linux-4.1.13.orig/drivers/crypto/caam/Makefile linux-4.1.13/drivers/crypto/caam/Makefile ---- linux-4.1.13.orig/drivers/crypto/caam/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/crypto/caam/Makefile 2015-11-30 17:56:13.552139590 +0100 -@@ -1,15 +1,14 @@ - # - # Makefile for the CAAM backend and dependent components - # --ifeq ($(CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG), y) -- EXTRA_CFLAGS := -DDEBUG --endif - - obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM) += caam.o --obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_JR) += caam_jr.o - obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API) += caamalg.o - obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API) += caamhash.o - obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API) += caamrng.o -+obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_SM) += sm_store.o -+obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST) += sm_test.o -+obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO) += secvio.o -+obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_KEYBLOB) += caam_keyblob.o - --caam-objs := ctrl.o --caam_jr-objs := jr.o key_gen.o error.o -+caam-objs := ctrl.o jr.o error.o key_gen.o -diff -Nur linux-4.1.13.orig/drivers/crypto/caam/pdb.h linux-4.1.13/drivers/crypto/caam/pdb.h ---- linux-4.1.13.orig/drivers/crypto/caam/pdb.h 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/crypto/caam/pdb.h 2015-11-30 17:56:13.552139590 +0100 -@@ -44,7 +44,6 @@ - #define PDBOPTS_ESP_IPHDRSRC 0x08 /* IP header comes from PDB (encap) */ - #define PDBOPTS_ESP_INCIPHDR 0x04 /* Prepend IP header to output frame */ - #define PDBOPTS_ESP_IPVSN 0x02 /* process IPv6 header */ --#define PDBOPTS_ESP_AOFL 0x04 /* adjust out frame len (decap, SEC>=5.3)*/ - #define PDBOPTS_ESP_TUNNEL 0x01 /* tunnel mode next-header byte */ - #define PDBOPTS_ESP_IPV6 0x02 /* ip header version is V6 */ - #define PDBOPTS_ESP_DIFFSERV 0x40 /* copy TOS/TC from inner iphdr */ -diff -Nur linux-4.1.13.orig/drivers/crypto/caam/regs.h linux-4.1.13/drivers/crypto/caam/regs.h ---- linux-4.1.13.orig/drivers/crypto/caam/regs.h 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/crypto/caam/regs.h 2015-11-30 17:56:13.552139590 +0100 -@@ -1,7 +1,7 @@ - /* - * CAAM hardware register-level view - * -- * Copyright 2008-2011 Freescale Semiconductor, Inc. -+ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc. - */ - - #ifndef REGS_H -@@ -74,17 +74,22 @@ - #endif - #else - #ifdef __LITTLE_ENDIAN --#define wr_reg32(reg, data) __raw_writel(data, reg) --#define rd_reg32(reg) __raw_readl(reg) -+#define wr_reg32(reg, data) writel(data, reg) -+#define rd_reg32(reg) readl(reg) - #ifdef CONFIG_64BIT --#define wr_reg64(reg, data) __raw_writeq(data, reg) --#define rd_reg64(reg) __raw_readq(reg) -+#define wr_reg64(reg, data) writeq(data, reg) -+#define rd_reg64(reg) readq(reg) - #endif - #endif - #endif - -+#ifdef CONFIG_ARM -+/* These are common macros for Power, put here for ARMs */ -+#define setbits32(_addr, _v) writel((readl(_addr) | (_v)), (_addr)) -+#define clrbits32(_addr, _v) writel((readl(_addr) & ~(_v)), (_addr)) -+#endif -+ - #ifndef CONFIG_64BIT --#ifdef __BIG_ENDIAN - static inline void wr_reg64(u64 __iomem *reg, u64 data) - { - wr_reg32((u32 __iomem *)reg, (data & 0xffffffff00000000ull) >> 32); -@@ -96,21 +101,6 @@ - return (((u64)rd_reg32((u32 __iomem *)reg)) << 32) | - ((u64)rd_reg32((u32 __iomem *)reg + 1)); - } --#else --#ifdef __LITTLE_ENDIAN --static inline void wr_reg64(u64 __iomem *reg, u64 data) --{ -- wr_reg32((u32 __iomem *)reg + 1, (data & 0xffffffff00000000ull) >> 32); -- wr_reg32((u32 __iomem *)reg, data & 0x00000000ffffffffull); --} -- --static inline u64 rd_reg64(u64 __iomem *reg) --{ -- return (((u64)rd_reg32((u32 __iomem *)reg + 1)) << 32) | -- ((u64)rd_reg32((u32 __iomem *)reg)); --} --#endif --#endif - #endif - - /* -@@ -123,6 +113,98 @@ - } __packed; - - /* -+ * CHA version ID / instantiation bitfields -+ * Defined for use within cha_id in perfmon -+ * Note that the same shift/mask selectors can be used to pull out number -+ * of instantiated blocks within cha_num in perfmon, the locations are -+ * the same. -+ */ -+ -+/* Job Ring */ -+#define CHA_ID_JR_SHIFT 60 -+#define CHA_ID_JR_MASK (0xfull << CHA_ID_JR_SHIFT) -+ -+/* DEscriptor COntroller */ -+#define CHA_ID_DECO_SHIFT 56 -+#define CHA_ID_DECO_MASK (0xfull << CHA_ID_DECO_SHIFT) -+#define CHA_NUM_DECONUM_SHIFT 56 /* legacy definition */ -+#define CHA_NUM_DECONUM_MASK (0xfull << CHA_NUM_DECONUM_SHIFT) -+ -+/* ZUC-Authentication */ -+#define CHA_ID_ZA_SHIFT 44 -+#define CHA_ID_ZA_MASK (0xfull << CHA_ID_ZA_SHIFT) -+ -+/* ZUC-Encryption */ -+#define CHA_ID_ZE_SHIFT 40 -+#define CHA_ID_ZE_MASK (0xfull << CHA_ID_ZE_SHIFT) -+ -+/* SNOW f9 */ -+#define CHA_ID_SNW9_SHIFT 36 -+#define CHA_ID_SNW9_MASK (0xfull << CHA_ID_SNW9_SHIFT) -+ -+/* CRC */ -+#define CHA_ID_CRC_SHIFT 32 -+#define CHA_ID_CRC_MASK (0xfull << CHA_ID_CRC_SHIFT) -+ -+/* Public Key */ -+#define CHA_ID_PK_SHIFT 28 -+#define CHA_ID_PK_MASK (0xfull << CHA_ID_PK_SHIFT) -+ -+/* Kasumi */ -+#define CHA_ID_KAS_SHIFT 24 -+#define CHA_ID_KAS_MASK (0xfull << CHA_ID_KAS_SHIFT) -+ -+/* SNOW f8 */ -+#define CHA_ID_SNW8_SHIFT 20 -+#define CHA_ID_SNW8_MASK (0xfull << CHA_ID_SNW8_SHIFT) -+ -+/* -+ * Random Generator -+ * RNG4 = FIPS-verification-compliant, requires init kickstart for use -+ */ -+#define CHA_ID_RNG_SHIFT 16 -+#define CHA_ID_RNG_MASK (0xfull << CHA_ID_RNG_SHIFT) -+#define CHA_ID_RNG_A (0x1ull << CHA_ID_RNG_SHIFT) -+#define CHA_ID_RNG_B (0x2ull << CHA_ID_RNG_SHIFT) -+#define CHA_ID_RNG_C (0x3ull << CHA_ID_RNG_SHIFT) -+#define CHA_ID_RNG_4 (0x4ull << CHA_ID_RNG_SHIFT) -+ -+/* -+ * Message Digest -+ * LP256 = Low Power (MD5/SHA1/SHA224/SHA256 + HMAC) -+ * LP512 = Low Power (LP256 + SHA384/SHA512) -+ * HP = High Power (LP512 + SMAC) -+ */ -+#define CHA_ID_MD_SHIFT 12 -+#define CHA_ID_MD_MASK (0xfull << CHA_ID_MD_SHIFT) -+#define CHA_ID_MD_LP256 (0x0ull << CHA_ID_MD_SHIFT) -+#define CHA_ID_MD_LP512 (0x1ull << CHA_ID_MD_SHIFT) -+#define CHA_ID_MD_HP (0x2ull << CHA_ID_MD_SHIFT) -+ -+/* ARC4 Streamcipher */ -+#define CHA_ID_ARC4_SHIFT 8 -+#define CHA_ID_ARC4_MASK (0xfull << CHA_ID_ARC4_SHIFT) -+#define CHA_ID_ARC4_LP (0x0ull << CHA_ID_ARC4_SHIFT) -+#define CHA_ID_ARC4_HP (0x1ull << CHA_ID_ARC4_SHIFT) -+ -+/* DES Blockcipher Accelerator */ -+#define CHA_ID_DES_SHIFT 4 -+#define CHA_ID_DES_MASK (0xfull << CHA_ID_DES_SHIFT) -+ -+/* -+ * AES Blockcipher + Combo Mode Accelerator -+ * LP = Low Power (includes ECB/CBC/CFB128/OFB/CTR/CCM/CMAC/XCBC-MAC) -+ * HP = High Power (LP + CBCXCBC/CTRXCBC/XTS/GCM) -+ * DIFFPWR = ORed in if differential-power-analysis resistance implemented -+ */ -+#define CHA_ID_AES_SHIFT 0 -+#define CHA_ID_AES_MASK (0xfull << CHA_ID_AES_SHIFT) -+#define CHA_ID_AES_LP (0x3ull << CHA_ID_AES_SHIFT) -+#define CHA_ID_AES_HP (0x4ull << CHA_ID_AES_SHIFT) -+#define CHA_ID_AES_DIFFPWR (0x1ull << CHA_ID_AES_SHIFT) -+ -+ -+/* - * caam_perfmon - Performance Monitor/Secure Memory Status/ - * CAAM Global Status/Component Version IDs - * -@@ -130,45 +212,8 @@ - */ - - /* Number of DECOs */ --#define CHA_NUM_MS_DECONUM_SHIFT 24 --#define CHA_NUM_MS_DECONUM_MASK (0xfull << CHA_NUM_MS_DECONUM_SHIFT) -- --/* CHA Version IDs */ --#define CHA_ID_LS_AES_SHIFT 0 --#define CHA_ID_LS_AES_MASK (0xfull << CHA_ID_LS_AES_SHIFT) -- --#define CHA_ID_LS_DES_SHIFT 4 --#define CHA_ID_LS_DES_MASK (0xfull << CHA_ID_LS_DES_SHIFT) -- --#define CHA_ID_LS_ARC4_SHIFT 8 --#define CHA_ID_LS_ARC4_MASK (0xfull << CHA_ID_LS_ARC4_SHIFT) -- --#define CHA_ID_LS_MD_SHIFT 12 --#define CHA_ID_LS_MD_MASK (0xfull << CHA_ID_LS_MD_SHIFT) -- --#define CHA_ID_LS_RNG_SHIFT 16 --#define CHA_ID_LS_RNG_MASK (0xfull << CHA_ID_LS_RNG_SHIFT) -- --#define CHA_ID_LS_SNW8_SHIFT 20 --#define CHA_ID_LS_SNW8_MASK (0xfull << CHA_ID_LS_SNW8_SHIFT) -- --#define CHA_ID_LS_KAS_SHIFT 24 --#define CHA_ID_LS_KAS_MASK (0xfull << CHA_ID_LS_KAS_SHIFT) -- --#define CHA_ID_LS_PK_SHIFT 28 --#define CHA_ID_LS_PK_MASK (0xfull << CHA_ID_LS_PK_SHIFT) -- --#define CHA_ID_MS_CRC_SHIFT 0 --#define CHA_ID_MS_CRC_MASK (0xfull << CHA_ID_MS_CRC_SHIFT) -- --#define CHA_ID_MS_SNW9_SHIFT 4 --#define CHA_ID_MS_SNW9_MASK (0xfull << CHA_ID_MS_SNW9_SHIFT) -- --#define CHA_ID_MS_DECO_SHIFT 24 --#define CHA_ID_MS_DECO_MASK (0xfull << CHA_ID_MS_DECO_SHIFT) -- --#define CHA_ID_MS_JR_SHIFT 28 --#define CHA_ID_MS_JR_MASK (0xfull << CHA_ID_MS_JR_SHIFT) -+#define CHA_NUM_DECONUM_SHIFT 56 -+#define CHA_NUM_DECONUM_MASK (0xfull << CHA_NUM_DECONUM_SHIFT) - - struct sec_vid { - u16 ip_id; -@@ -176,6 +221,10 @@ - u8 min_rev; - }; - -+#define SEC_VID_IPID_SHIFT 16 -+#define SEC_VID_MAJ_SHIFT 8 -+#define SEC_VID_MAJ_MASK 0xFF00 -+ - struct caam_perfmon { - /* Performance Monitor Registers f00-f9f */ - u64 req_dequeued; /* PC_REQ_DEQ - Dequeued Requests */ -@@ -188,36 +237,89 @@ - u64 rsvd[13]; - - /* CAAM Hardware Instantiation Parameters fa0-fbf */ -- u32 cha_rev_ms; /* CRNR - CHA Rev No. Most significant half*/ -- u32 cha_rev_ls; /* CRNR - CHA Rev No. Least significant half*/ --#define CTPR_MS_QI_SHIFT 25 --#define CTPR_MS_QI_MASK (0x1ull << CTPR_MS_QI_SHIFT) --#define CTPR_MS_VIRT_EN_INCL 0x00000001 --#define CTPR_MS_VIRT_EN_POR 0x00000002 --#define CTPR_MS_PG_SZ_MASK 0x10 --#define CTPR_MS_PG_SZ_SHIFT 4 -- u32 comp_parms_ms; /* CTPR - Compile Parameters Register */ -- u32 comp_parms_ls; /* CTPR - Compile Parameters Register */ -- u64 rsvd1[2]; -+ u64 cha_rev; /* CRNR - CHA Revision Number */ -+#define CTPR_QI_SHIFT 57 -+#define CTPR_QI_MASK (0x1ull << CTPR_QI_SHIFT) -+ u64 comp_parms; /* CTPR - Compile Parameters Register */ -+ -+ /* Secure Memory State Visibility */ -+ u32 rsvd1; -+ u32 smstatus; /* Secure memory status */ -+ u32 rsvd2; -+ u32 smpartown; /* Secure memory partition owner */ - - /* CAAM Global Status fc0-fdf */ - u64 faultaddr; /* FAR - Fault Address */ - u32 faultliodn; /* FALR - Fault Address LIODN */ - u32 faultdetail; /* FADR - Fault Addr Detail */ -- u32 rsvd2; -+ u32 rsvd3; - u32 status; /* CSTA - CAAM Status */ -- u64 rsvd3; -+ u32 smpart; /* Secure Memory Partition Parameters */ -+ u32 smvid; /* Secure Memory Version ID */ - - /* Component Instantiation Parameters fe0-fff */ - u32 rtic_id; /* RVID - RTIC Version ID */ - u32 ccb_id; /* CCBVID - CCB Version ID */ -- u32 cha_id_ms; /* CHAVID - CHA Version ID Most Significant*/ -- u32 cha_id_ls; /* CHAVID - CHA Version ID Least Significant*/ -- u32 cha_num_ms; /* CHANUM - CHA Number Most Significant */ -- u32 cha_num_ls; /* CHANUM - CHA Number Least Significant*/ -- u32 caam_id_ms; /* CAAMVID - CAAM Version ID MS */ -- u32 caam_id_ls; /* CAAMVID - CAAM Version ID LS */ --}; -+ u64 cha_id; /* CHAVID - CHA Version ID */ -+ u64 cha_num; /* CHANUM - CHA Number */ -+ u64 caam_id; /* CAAMVID - CAAM Version ID */ -+}; -+ -+#define SMSTATUS_PART_SHIFT 28 -+#define SMSTATUS_PART_MASK (0xf << SMSTATUS_PART_SHIFT) -+#define SMSTATUS_PAGE_SHIFT 16 -+#define SMSTATUS_PAGE_MASK (0x7ff << SMSTATUS_PAGE_SHIFT) -+#define SMSTATUS_MID_SHIFT 8 -+#define SMSTATUS_MID_MASK (0x3f << SMSTATUS_MID_SHIFT) -+#define SMSTATUS_ACCERR_SHIFT 4 -+#define SMSTATUS_ACCERR_MASK (0xf << SMSTATUS_ACCERR_SHIFT) -+#define SMSTATUS_ACCERR_NONE 0 -+#define SMSTATUS_ACCERR_ALLOC 1 /* Page not allocated */ -+#define SMSTATUS_ACCESS_ID 2 /* Not granted by ID */ -+#define SMSTATUS_ACCESS_WRITE 3 /* Writes not allowed */ -+#define SMSTATUS_ACCESS_READ 4 /* Reads not allowed */ -+#define SMSTATUS_ACCESS_NONKEY 6 /* Non-key reads not allowed */ -+#define SMSTATUS_ACCESS_BLOB 9 /* Blob access not allowed */ -+#define SMSTATUS_ACCESS_DESCB 10 /* Descriptor Blob access spans pages */ -+#define SMSTATUS_ACCESS_NON_SM 11 /* Outside Secure Memory range */ -+#define SMSTATUS_ACCESS_XPAGE 12 /* Access crosses pages */ -+#define SMSTATUS_ACCESS_INITPG 13 /* Page still initializing */ -+#define SMSTATUS_STATE_SHIFT 0 -+#define SMSTATUS_STATE_MASK (0xf << SMSTATUS_STATE_SHIFT) -+#define SMSTATUS_STATE_RESET 0 -+#define SMSTATUS_STATE_INIT 1 -+#define SMSTATUS_STATE_NORMAL 2 -+#define SMSTATUS_STATE_FAIL 3 -+ -+/* up to 15 rings, 2 bits shifted by ring number */ -+#define SMPARTOWN_RING_SHIFT 2 -+#define SMPARTOWN_RING_MASK 3 -+#define SMPARTOWN_AVAILABLE 0 -+#define SMPARTOWN_NOEXIST 1 -+#define SMPARTOWN_UNAVAILABLE 2 -+#define SMPARTOWN_OURS 3 -+ -+/* Maximum number of pages possible */ -+#define SMPART_MAX_NUMPG_SHIFT 16 -+#define SMPART_MAX_NUMPG_MASK (0x3f << SMPART_MAX_NUMPG_SHIFT) -+ -+/* Maximum partition number */ -+#define SMPART_MAX_PNUM_SHIFT 12 -+#define SMPART_MAX_PNUM_MASK (0xf << SMPART_MAX_PNUM_SHIFT) -+ -+/* Highest possible page number */ -+#define SMPART_MAX_PG_SHIFT 0 -+#define SMPART_MAX_PG_MASK (0x3f << SMPART_MAX_PG_SHIFT) -+ -+/* Max size of a page */ -+#define SMVID_PG_SIZE_SHIFT 16 -+#define SMVID_PG_SIZE_MASK (0x7 << SMVID_PG_SIZE_SHIFT) -+ -+/* Major/Minor Version ID */ -+#define SMVID_MAJ_VERS_SHIFT 8 -+#define SMVID_MAJ_VERS (0xf << SMVID_MAJ_VERS_SHIFT) -+#define SMVID_MIN_VERS_SHIFT 0 -+#define SMVID_MIN_VERS (0xf << SMVID_MIN_VERS_SHIFT) - - /* LIODN programming for DMA configuration */ - #define MSTRID_LOCK_LIODN 0x80000000 -@@ -270,17 +372,7 @@ - - /* RNG4 TRNG test registers */ - struct rng4tst { --#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */ --#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in -- both entropy shifter and -- statistical checker */ --#define RTMCTL_SAMP_MODE_RAW_ES_SC 1 /* use raw data in both -- entropy shifter and -- statistical checker */ --#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2 /* use von Neumann data in -- entropy shifter, raw data -- in statistical checker */ --#define RTMCTL_SAMP_MODE_INVALID 3 /* invalid combination */ -+#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */ - u32 rtmctl; /* misc. control register */ - u32 rtscmisc; /* statistical check misc. register */ - u32 rtpkrrng; /* poker range register */ -@@ -290,26 +382,22 @@ - }; - #define RTSDCTL_ENT_DLY_SHIFT 16 - #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT) --#define RTSDCTL_ENT_DLY_MIN 3200 --#define RTSDCTL_ENT_DLY_MAX 12800 - u32 rtsdctl; /* seed control register */ - union { - u32 rtsblim; /* PRGM=1: sparse bit limit register */ - u32 rttotsam; /* PRGM=0: total samples register */ - }; - u32 rtfrqmin; /* frequency count min. limit register */ --#define RTFRQMAX_DISABLE (1 << 20) - union { - u32 rtfrqmax; /* PRGM=1: freq. count max. limit register */ - u32 rtfrqcnt; /* PRGM=0: freq. count register */ - }; - u32 rsvd1[40]; --#define RDSTA_SKVT 0x80000000 --#define RDSTA_SKVN 0x40000000 --#define RDSTA_IF0 0x00000001 --#define RDSTA_IF1 0x00000002 --#define RDSTA_IFMASK (RDSTA_IF1 | RDSTA_IF0) -- u32 rdsta; -+#define RDSTA_IF 0x00000003 /* state handle instantiated flags 0 and 1 */ -+#define RDSTA_SKVN 0x40000000 /* Secure Key Valid Non-Test mode */ -+#define RDSTA_SKVT 0x80000000 /* Secure Key Valid Test. non-test mode */ -+#define RDSTA_TF 0x00000300 /* State handle instantiated Test-mode */ -+ u32 rdsta; /* DRNG status register */ - u32 rsvd2[15]; - }; - -@@ -340,12 +428,9 @@ - /* Bus Access Configuration Section 010-11f */ - /* Read/Writable */ - struct masterid jr_mid[4]; /* JRxLIODNR - JobR LIODN setup */ -- u32 rsvd3[11]; -- u32 jrstart; /* JRSTART - Job Ring Start Register */ -+ u32 rsvd3[12]; - struct masterid rtic_mid[4]; /* RTICxLIODNR - RTIC LIODN setup */ -- u32 rsvd4[5]; -- u32 deco_rsr; /* DECORSR - Deco Request Source */ -- u32 rsvd11; -+ u32 rsvd4[7]; - u32 deco_rq; /* DECORR - DECO Request */ - struct partid deco_mid[5]; /* DECOxLIODNR - 1 per DECO */ - u32 rsvd5[22]; -@@ -386,11 +471,6 @@ - #define MCFGR_DMA_RESET 0x10000000 - #define MCFGR_LONG_PTR 0x00010000 /* Use >32-bit desc addressing */ - #define SCFGR_RDBENABLE 0x00000400 --#define SCFGR_VIRT_EN 0x00008000 --#define DECORR_RQD0ENABLE 0x00000001 /* Enable DECO0 for direct access */ --#define DECORSR_JR0 0x00000001 /* JR to supply TZ, SDID, ICID */ --#define DECORSR_VALID 0x80000000 --#define DECORR_DEN0 0x00010000 /* DECO0 available for access*/ - - /* AXI read cache control */ - #define MCFGR_ARCACHE_SHIFT 12 -@@ -407,12 +487,6 @@ - #define MCFGR_AXIPRI 0x00000008 /* Assert AXI priority sideband */ - #define MCFGR_BURST_64 0x00000001 /* Max burst size */ - --/* JRSTART register offsets */ --#define JRSTART_JR0_START 0x00000001 /* Start Job ring 0 */ --#define JRSTART_JR1_START 0x00000002 /* Start Job ring 1 */ --#define JRSTART_JR2_START 0x00000004 /* Start Job ring 2 */ --#define JRSTART_JR3_START 0x00000008 /* Start Job ring 3 */ -- - /* - * caam_job_ring - direct job ring setup - * 1-4 possible per instantiation, base + 1000/2000/3000/4000 -@@ -455,7 +529,18 @@ - u32 rsvd11; - u32 jrcommand; /* JRCRx - JobR command */ - -- u32 rsvd12[932]; -+ u32 rsvd12[33]; -+ -+ /* Secure Memory Configuration - if you have it */ -+ u32 sm_cmd; /* SMCJRx - Secure memory command */ -+ u32 rsvd13; -+ u32 sm_status; /* SMCSJRx - Secure memory status */ -+ u32 rsvd14; -+ u32 sm_perm; /* SMAPJRx - Secure memory access perms */ -+ u32 sm_group2; /* SMAP2JRx - Secure memory access group 2 */ -+ u32 sm_group1; /* SMAP1JRx - Secure memory access group 1 */ -+ -+ u32 rsvd15[891]; - - /* Performance Monitor f00-fff */ - struct caam_perfmon perfmon; -@@ -578,6 +663,62 @@ - - #define JRCR_RESET 0x01 - -+/* secure memory command */ -+#define SMC_PAGE_SHIFT 16 -+#define SMC_PAGE_MASK (0xffff << SMC_PAGE_SHIFT) -+#define SMC_PART_SHIFT 8 -+#define SMC_PART_MASK (0x0f << SMC_PART_SHIFT) -+#define SMC_CMD_SHIFT 0 -+#define SMC_CMD_MASK (0x0f << SMC_CMD_SHIFT) -+ -+#define SMC_CMD_ALLOC_PAGE 0x01 /* allocate page to this partition */ -+#define SMC_CMD_DEALLOC_PAGE 0x02 /* deallocate page from partition */ -+#define SMC_CMD_DEALLOC_PART 0x03 /* deallocate partition */ -+#define SMC_CMD_PAGE_INQUIRY 0x05 /* find partition associate with page */ -+ -+/* secure memory (command) status */ -+#define SMCS_PAGE_SHIFT 16 -+#define SMCS_PAGE_MASK (0x0fff << SMCS_PAGE_SHIFT) -+#define SMCS_CMDERR_SHIFT 14 -+#define SMCS_CMDERR_MASK (3 << SMCS_CMDERR_SHIFT) -+#define SMCS_ALCERR_SHIFT 12 -+#define SMCS_ALCERR_MASK (3 << SMCS_ALCERR_SHIFT) -+#define SMCS_PGOWN_SHIFT 6 -+#define SMCS_PGWON_MASK (3 << SMCS_PGOWN_SHIFT) -+#define SMCS_PART_SHIFT 0 -+#define SMCS_PART_MASK (0xf << SMCS_PART_SHIFT) -+ -+#define SMCS_CMDERR_NONE 0 -+#define SMCS_CMDERR_INCOMP 1 /* Command not yet complete */ -+#define SMCS_CMDERR_SECFAIL 2 /* Security failure occurred */ -+#define SMCS_CMDERR_OVERFLOW 3 /* Command overflow */ -+ -+#define SMCS_ALCERR_NONE 0 -+#define SMCS_ALCERR_PSPERR 1 /* Partion marked PSP (dealloc only) */ -+#define SMCS_ALCERR_PAGEAVAIL 2 /* Page not available */ -+#define SMCS_ALCERR_PARTOWN 3 /* Partition ownership error */ -+ -+#define SMCS_PGOWN_AVAIL 0 /* Page is available */ -+#define SMCS_PGOWN_NOEXIST 1 /* Page initializing or nonexistent */ -+#define SMCS_PGOWN_NOOWN 2 /* Page owned by another processor */ -+#define SMCS_PGOWN_OWNED 3 /* Page belongs to this processor */ -+ -+/* secure memory access permissions */ -+#define SMCS_PERM_KEYMOD_SHIFT 16 -+#define SMCA_PERM_KEYMOD_MASK (0xff << SMCS_PERM_KEYMOD_SHIFT) -+#define SMCA_PERM_CSP_ZERO 0x8000 /* Zero when deallocated or released */ -+#define SMCA_PERM_PSP_LOCK 0x4000 /* Part./pages can't be deallocated */ -+#define SMCA_PERM_PERM_LOCK 0x2000 /* Lock permissions */ -+#define SMCA_PERM_GRP_LOCK 0x1000 /* Lock access groups */ -+#define SMCA_PERM_RINGID_SHIFT 10 -+#define SMCA_PERM_RINGID_MASK (3 << SMCA_PERM_RINGID_SHIFT) -+#define SMCA_PERM_G2_BLOB 0x0080 /* Group 2 blob import/export */ -+#define SMCA_PERM_G2_WRITE 0x0020 /* Group 2 write */ -+#define SMCA_PERM_G2_READ 0x0010 /* Group 2 read */ -+#define SMCA_PERM_G1_BLOB 0x0008 /* Group 1... */ -+#define SMCA_PERM_G1_WRITE 0x0002 -+#define SMCA_PERM_G1_READ 0x0001 -+ - /* - * caam_assurance - Assurance Controller View - * base + 0x6000 padded out to 0x1000 -@@ -746,7 +887,6 @@ - u32 jr_ctl_hi; /* CxJRR - JobR Control Register @800 */ - u32 jr_ctl_lo; - u64 jr_descaddr; /* CxDADR - JobR Descriptor Address */ --#define DECO_OP_STATUS_HI_ERR_MASK 0xF00000FF - u32 op_status_hi; /* DxOPSTA - DECO Operation Status */ - u32 op_status_lo; - u32 rsvd24[2]; -@@ -760,21 +900,36 @@ - struct deco_sg_table sctr_tbl[4]; /* DxSTR - Scatter Tables */ - u32 rsvd29[48]; - u32 descbuf[64]; /* DxDESB - Descriptor buffer */ -- u32 rscvd30[193]; --#define DESC_DBG_DECO_STAT_HOST_ERR 0x00D00000 --#define DESC_DBG_DECO_STAT_VALID 0x80000000 --#define DESC_DBG_DECO_STAT_MASK 0x00F00000 -- u32 desc_dbg; /* DxDDR - DECO Debug Register */ -- u32 rsvd31[126]; --}; -- --#define DECO_JQCR_WHL 0x20000000 --#define DECO_JQCR_FOUR 0x10000000 -- --#define JR_BLOCK_NUMBER 1 --#define ASSURE_BLOCK_NUMBER 6 --#define QI_BLOCK_NUMBER 7 --#define DECO_BLOCK_NUMBER 8 --#define PG_SIZE_4K 0x1000 --#define PG_SIZE_64K 0x10000 -+ u32 rsvd30[320]; -+}; -+ -+/* -+ * Current top-level view of memory map is: -+ * -+ * 0x0000 - 0x0fff - CAAM Top-Level Control -+ * 0x1000 - 0x1fff - Job Ring 0 -+ * 0x2000 - 0x2fff - Job Ring 1 -+ * 0x3000 - 0x3fff - Job Ring 2 -+ * 0x4000 - 0x4fff - Job Ring 3 -+ * 0x5000 - 0x5fff - (unused) -+ * 0x6000 - 0x6fff - Assurance Controller -+ * 0x7000 - 0x7fff - Queue Interface -+ * 0x8000 - 0x8fff - DECO-CCB 0 -+ * 0x9000 - 0x9fff - DECO-CCB 1 -+ * 0xa000 - 0xafff - DECO-CCB 2 -+ * 0xb000 - 0xbfff - DECO-CCB 3 -+ * 0xc000 - 0xcfff - DECO-CCB 4 -+ * -+ * caam_full describes the full register view of CAAM if useful, -+ * although many configurations may choose to implement parts of -+ * the register map separately, in differing privilege regions -+ */ -+struct caam_full { -+ struct caam_ctrl __iomem ctrl; -+ struct caam_job_ring jr[4]; -+ u64 rsvd[512]; -+ struct caam_assurance assure; -+ struct caam_queue_if qi; -+}; -+ - #endif /* REGS_H */ -diff -Nur linux-4.1.13.orig/drivers/crypto/caam/secvio.c linux-4.1.13/drivers/crypto/caam/secvio.c ---- linux-4.1.13.orig/drivers/crypto/caam/secvio.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/crypto/caam/secvio.c 2015-11-30 17:56:13.552139590 +0100 -@@ -0,0 +1,290 @@ -+ -+/* -+ * SNVS Security Violation Handler -+ * Copyright (C) 2012-2015 Freescale Semiconductor, Inc., All Rights Reserved -+ */ -+ -+#include "compat.h" -+#include "intern.h" -+#include "secvio.h" -+#include "regs.h" -+ -+/* -+ * These names are associated with each violation handler. -+ * The source names were taken from MX6, and are based on recommendations -+ * for most common SoCs. -+ */ -+static const u8 *violation_src_name[] = { -+ "CAAM Internal Security Violation", -+ "JTAG Alarm", -+ "Watchdog", -+ "(reserved)", -+ "External Boot", -+ "External Tamper Detect", -+}; -+ -+/* These names help describe security monitor state for the console */ -+static const u8 *snvs_ssm_state_name[] = { -+ "init", -+ "hard fail", -+ "(undef:2)", -+ "soft fail", -+ "(undef:4)", -+ "(undef:5)", -+ "(undef:6)", -+ "(undef:7)", -+ "transition", -+ "check", -+ "(undef:10)", -+ "non-secure", -+ "(undef:12)", -+ "trusted", -+ "(undef:14)", -+ "secure", -+}; -+ -+/* Top-level security violation interrupt */ -+static irqreturn_t snvs_secvio_interrupt(int irq, void *snvsdev) -+{ -+ struct device *dev = snvsdev; -+ struct snvs_secvio_drv_private *svpriv = dev_get_drvdata(dev); -+ -+ /* Check the HP secvio status register */ -+ svpriv->irqcause = rd_reg32(&svpriv->svregs->hp.secvio_status) & -+ HP_SECVIOST_SECVIOMASK; -+ -+ if (!svpriv->irqcause) -+ return IRQ_NONE; -+ -+ /* Now ACK cause */ -+ setbits32(&svpriv->svregs->hp.secvio_status, svpriv->irqcause); -+ -+ /* And run deferred service */ -+ preempt_disable(); -+ tasklet_schedule(&svpriv->irqtask[smp_processor_id()]); -+ preempt_enable(); -+ -+ return IRQ_HANDLED; -+} -+ -+/* Deferred service handler. Tasklet arg is simply the SNVS dev */ -+static void snvs_secvio_dispatch(unsigned long indev) -+{ -+ struct device *dev = (struct device *)indev; -+ struct snvs_secvio_drv_private *svpriv = dev_get_drvdata(dev); -+ unsigned long flags; -+ int i; -+ -+ -+ /* Look through stored causes, call each handler if exists */ -+ for (i = 0; i < MAX_SECVIO_SOURCES; i++) -+ if (svpriv->irqcause & (1 << i)) { -+ spin_lock_irqsave(&svpriv->svlock, flags); -+ svpriv->intsrc[i].handler(dev, i, -+ svpriv->intsrc[i].ext); -+ spin_unlock_irqrestore(&svpriv->svlock, flags); -+ }; -+ -+ /* Re-enable now-serviced interrupts */ -+ setbits32(&svpriv->svregs->hp.secvio_intcfg, svpriv->irqcause); -+} -+ -+/* -+ * Default cause handler, used in lieu of an application-defined handler. -+ * All it does at this time is print a console message. It could force a halt. -+ */ -+static void snvs_secvio_default(struct device *dev, u32 cause, void *ext) -+{ -+ struct snvs_secvio_drv_private *svpriv = dev_get_drvdata(dev); -+ -+ dev_err(dev, "Unhandled Security Violation Interrupt %d = %s\n", -+ cause, svpriv->intsrc[cause].intname); -+} -+ -+/* -+ * Install an application-defined handler for a specified cause -+ * Arguments: -+ * - dev points to SNVS-owning device -+ * - cause interrupt source cause -+ * - handler application-defined handler, gets called with dev -+ * source cause, and locally-defined handler argument -+ * - cause_description points to a string to override the default cause -+ * name, this can be used as an alternate for error -+ * messages and such. If left NULL, the default -+ * description string is used. -+ * - ext pointer to any extra data needed by the handler. -+ */ -+int snvs_secvio_install_handler(struct device *dev, enum secvio_cause cause, -+ void (*handler)(struct device *dev, u32 cause, -+ void *ext), -+ u8 *cause_description, void *ext) -+{ -+ unsigned long flags; -+ struct snvs_secvio_drv_private *svpriv; -+ -+ svpriv = dev_get_drvdata(dev); -+ -+ if ((handler == NULL) || (cause > SECVIO_CAUSE_SOURCE_5)) -+ return -EINVAL; -+ -+ spin_lock_irqsave(&svpriv->svlock, flags); -+ svpriv->intsrc[cause].handler = handler; -+ if (cause_description != NULL) -+ svpriv->intsrc[cause].intname = cause_description; -+ if (ext != NULL) -+ svpriv->intsrc[cause].ext = ext; -+ spin_unlock_irqrestore(&svpriv->svlock, flags); -+ -+ return 0; -+} -+EXPORT_SYMBOL(snvs_secvio_install_handler); -+ -+/* -+ * Remove an application-defined handler for a specified cause (and, by -+ * implication, restore the "default". -+ * Arguments: -+ * - dev points to SNVS-owning device -+ * - cause interrupt source cause -+ */ -+int snvs_secvio_remove_handler(struct device *dev, enum secvio_cause cause) -+{ -+ unsigned long flags; -+ struct snvs_secvio_drv_private *svpriv; -+ -+ svpriv = dev_get_drvdata(dev); -+ -+ if (cause > SECVIO_CAUSE_SOURCE_5) -+ return -EINVAL; -+ -+ spin_lock_irqsave(&svpriv->svlock, flags); -+ svpriv->intsrc[cause].intname = violation_src_name[cause]; -+ svpriv->intsrc[cause].handler = snvs_secvio_default; -+ svpriv->intsrc[cause].ext = NULL; -+ spin_unlock_irqrestore(&svpriv->svlock, flags); -+ return 0; -+} -+EXPORT_SYMBOL(snvs_secvio_remove_handler); -+ -+static int snvs_secvio_remove(struct platform_device *pdev) -+{ -+ struct device *svdev; -+ struct snvs_secvio_drv_private *svpriv; -+ int i; -+ -+ svdev = &pdev->dev; -+ svpriv = dev_get_drvdata(svdev); -+ -+ /* Set all sources to nonfatal */ -+ wr_reg32(&svpriv->svregs->hp.secvio_intcfg, 0); -+ -+ /* Remove tasklets and release interrupt */ -+ for_each_possible_cpu(i) -+ tasklet_kill(&svpriv->irqtask[i]); -+ -+ free_irq(svpriv->irq, svdev); -+ iounmap(svpriv->svregs); -+ kfree(svpriv); -+ -+ return 0; -+} -+ -+static int snvs_secvio_probe(struct platform_device *pdev) -+{ -+ struct device *svdev; -+ struct snvs_secvio_drv_private *svpriv; -+ struct device_node *np, *npirq; -+ struct snvs_full __iomem *snvsregs; -+ int i, error; -+ u32 hpstate; -+ -+ svpriv = kzalloc(sizeof(struct snvs_secvio_drv_private), GFP_KERNEL); -+ if (!svpriv) -+ return -ENOMEM; -+ -+ svdev = &pdev->dev; -+ dev_set_drvdata(svdev, svpriv); -+ svpriv->pdev = pdev; -+ np = pdev->dev.of_node; -+ -+ npirq = of_find_compatible_node(NULL, NULL, "fsl,imx6q-caam-secvio"); -+ if (!npirq) { -+ dev_err(svdev, "can't identify secvio interrupt\n"); -+ kfree(svpriv); -+ return -EINVAL; -+ } -+ svpriv->irq = irq_of_parse_and_map(npirq, 0); -+ if (svpriv->irq <= 0) { -+ kfree(svpriv); -+ return -EINVAL; -+ } -+ -+ snvsregs = of_iomap(np, 0); -+ if (!snvsregs) { -+ dev_err(svdev, "register mapping failed\n"); -+ return -ENOMEM; -+ } -+ svpriv->svregs = (struct snvs_full __force *)snvsregs; -+ -+ /* Device data set up. Now init interrupt source descriptions */ -+ for (i = 0; i < MAX_SECVIO_SOURCES; i++) { -+ svpriv->intsrc[i].intname = violation_src_name[i]; -+ svpriv->intsrc[i].handler = snvs_secvio_default; -+ } -+ /* Connect main handler */ -+ for_each_possible_cpu(i) -+ tasklet_init(&svpriv->irqtask[i], snvs_secvio_dispatch, -+ (unsigned long)svdev); -+ -+ error = request_irq(svpriv->irq, snvs_secvio_interrupt, -+ IRQF_SHARED, "snvs-secvio", svdev); -+ if (error) { -+ dev_err(svdev, "can't connect secvio interrupt\n"); -+ irq_dispose_mapping(svpriv->irq); -+ svpriv->irq = 0; -+ iounmap(svpriv->svregs); -+ kfree(svpriv); -+ return -EINVAL; -+ } -+ -+ /* -+ * Configure all sources as fatal violations except LP section, -+ * source #5 (typically used as an external tamper detect), and -+ * source #3 (typically unused). Whenever the transition to -+ * secure mode has occurred, these will now be "fatal" violations -+ */ -+ wr_reg32(&svpriv->svregs->hp.secvio_intcfg, -+ HP_SECVIO_INTEN_SRC4 | HP_SECVIO_INTEN_SRC2 | -+ HP_SECVIO_INTEN_SRC1 | HP_SECVIO_INTEN_SRC0); -+ -+ hpstate = (rd_reg32(&svpriv->svregs->hp.status) & -+ HP_STATUS_SSM_ST_MASK) >> HP_STATUS_SSM_ST_SHIFT; -+ dev_info(svdev, "violation handlers armed - %s state\n", -+ snvs_ssm_state_name[hpstate]); -+ -+ return 0; -+} -+ -+static struct of_device_id snvs_secvio_match[] = { -+ { -+ .compatible = "fsl,imx6q-caam-snvs", -+ }, -+ {}, -+}; -+MODULE_DEVICE_TABLE(of, snvs_secvio_match); -+ -+static struct platform_driver snvs_secvio_driver = { -+ .driver = { -+ .name = "snvs-secvio", -+ .owner = THIS_MODULE, -+ .of_match_table = snvs_secvio_match, -+ }, -+ .probe = snvs_secvio_probe, -+ .remove = snvs_secvio_remove, -+}; -+ -+module_platform_driver(snvs_secvio_driver); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_DESCRIPTION("FSL SNVS Security Violation Handler"); -+MODULE_AUTHOR("Freescale Semiconductor - MCU"); -+ -diff -Nur linux-4.1.13.orig/drivers/crypto/caam/secvio.h linux-4.1.13/drivers/crypto/caam/secvio.h ---- linux-4.1.13.orig/drivers/crypto/caam/secvio.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/crypto/caam/secvio.h 2015-11-30 17:56:13.552139590 +0100 -@@ -0,0 +1,66 @@ -+ -+/* -+ * CAAM Security Violation Handler -+ * Copyright (C) 2012-2014 Freescale Semiconductor, Inc., All Rights Reserved -+ */ -+ -+#ifndef SECVIO_H -+#define SECVIO_H -+ -+#include "snvsregs.h" -+ -+ -+/* -+ * Defines the published interfaces to install/remove application-specified -+ * handlers for catching violations -+ */ -+ -+#define MAX_SECVIO_SOURCES 6 -+ -+/* these are the untranslated causes */ -+enum secvio_cause { -+ SECVIO_CAUSE_SOURCE_0, -+ SECVIO_CAUSE_SOURCE_1, -+ SECVIO_CAUSE_SOURCE_2, -+ SECVIO_CAUSE_SOURCE_3, -+ SECVIO_CAUSE_SOURCE_4, -+ SECVIO_CAUSE_SOURCE_5 -+}; -+ -+/* These are common "recommended" cause definitions for most devices */ -+#define SECVIO_CAUSE_CAAM_VIOLATION SECVIO_CAUSE_SOURCE_0 -+#define SECVIO_CAUSE_JTAG_ALARM SECVIO_CAUSE_SOURCE_1 -+#define SECVIO_CAUSE_WATCHDOG SECVIO_CAUSE_SOURCE_2 -+#define SECVIO_CAUSE_EXTERNAL_BOOT SECVIO_CAUSE_SOURCE_4 -+#define SECVIO_CAUSE_TAMPER_DETECT SECVIO_CAUSE_SOURCE_5 -+ -+int snvs_secvio_install_handler(struct device *dev, enum secvio_cause cause, -+ void (*handler)(struct device *dev, u32 cause, -+ void *ext), -+ u8 *cause_description, void *ext); -+int snvs_secvio_remove_handler(struct device *dev, enum secvio_cause cause); -+ -+/* -+ * Private data definitions for the secvio "driver" -+ */ -+ -+struct secvio_int_src { -+ const u8 *intname; /* Points to a descriptive name for source */ -+ void *ext; /* Extended data to pass to the handler */ -+ void (*handler)(struct device *dev, u32 cause, void *ext); -+}; -+ -+struct snvs_secvio_drv_private { -+ struct platform_device *pdev; -+ spinlock_t svlock ____cacheline_aligned; -+ struct tasklet_struct irqtask[NR_CPUS]; -+ struct snvs_full __iomem *svregs; /* both HP and LP domains */ -+ int irq; -+ u32 irqcause; /* stashed cause of violation interrupt */ -+ -+ /* Registered handlers for each violation */ -+ struct secvio_int_src intsrc[MAX_SECVIO_SOURCES]; -+ -+}; -+ -+#endif /* SECVIO_H */ -diff -Nur linux-4.1.13.orig/drivers/crypto/caam/sg_sw_sec4.h linux-4.1.13/drivers/crypto/caam/sg_sw_sec4.h ---- linux-4.1.13.orig/drivers/crypto/caam/sg_sw_sec4.h 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/crypto/caam/sg_sw_sec4.h 2015-11-30 17:56:13.552139590 +0100 -@@ -1,7 +1,7 @@ - /* - * CAAM/SEC 4.x functions for using scatterlists in caam driver - * -- * Copyright 2008-2011 Freescale Semiconductor, Inc. -+ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc. - * - */ - -@@ -91,13 +91,22 @@ - { - if (unlikely(chained)) { - int i; -+ struct scatterlist *tsg = sg; -+ -+ /* We use a local copy of the sg pointer to avoid moving the -+ * head of the list pointed to by sg as we wall the list. -+ */ - for (i = 0; i < nents; i++) { -- dma_map_sg(dev, sg, 1, dir); -- sg = sg_next(sg); -+ dma_map_sg(dev, tsg, 1, dir); -+ tsg = sg_next(tsg); - } - } else { - dma_map_sg(dev, sg, nents, dir); - } -+ -+ if ((dir == DMA_TO_DEVICE) || (dir == DMA_BIDIRECTIONAL)) -+ dma_sync_sg_for_device(dev, sg, nents, dir); -+ - return nents; - } - -@@ -105,6 +114,9 @@ - unsigned int nents, enum dma_data_direction dir, - bool chained) - { -+ if ((dir == DMA_FROM_DEVICE) || (dir == DMA_BIDIRECTIONAL)) -+ dma_sync_sg_for_cpu(dev, sg, nents, dir); -+ - if (unlikely(chained)) { - int i; - for (i = 0; i < nents; i++) { -@@ -116,3 +128,41 @@ - } - return nents; - } -+ -+/* Copy from len bytes of sg to dest, starting from beginning */ -+static inline void sg_copy(u8 *dest, struct scatterlist *sg, unsigned int len) -+{ -+ struct scatterlist *current_sg = sg; -+ int cpy_index = 0, next_cpy_index = current_sg->length; -+ -+ while (next_cpy_index < len) { -+ memcpy(dest + cpy_index, (u8 *) sg_virt(current_sg), -+ current_sg->length); -+ current_sg = sg_next(current_sg); -+ cpy_index = next_cpy_index; -+ next_cpy_index += current_sg->length; -+ } -+ if (cpy_index < len) -+ memcpy(dest + cpy_index, (u8 *) sg_virt(current_sg), -+ len - cpy_index); -+} -+ -+/* Copy sg data, from to_skip to end, to dest */ -+static inline void sg_copy_part(u8 *dest, struct scatterlist *sg, -+ int to_skip, unsigned int end) -+{ -+ struct scatterlist *current_sg = sg; -+ int sg_index, cpy_index; -+ -+ sg_index = current_sg->length; -+ while (sg_index <= to_skip) { -+ current_sg = sg_next(current_sg); -+ sg_index += current_sg->length; -+ } -+ cpy_index = sg_index - to_skip; -+ memcpy(dest, (u8 *) sg_virt(current_sg) + -+ current_sg->length - cpy_index, cpy_index); -+ current_sg = sg_next(current_sg); -+ if (end - sg_index) -+ sg_copy(dest + cpy_index, current_sg, end - sg_index); -+} -diff -Nur linux-4.1.13.orig/drivers/crypto/caam/sm.h linux-4.1.13/drivers/crypto/caam/sm.h ---- linux-4.1.13.orig/drivers/crypto/caam/sm.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/crypto/caam/sm.h 2015-11-30 17:56:13.552139590 +0100 -@@ -0,0 +1,88 @@ -+ -+/* -+ * CAAM Secure Memory/Keywrap API Definitions -+ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc. -+ */ -+ -+#ifndef SM_H -+#define SM_H -+ -+ -+/* Storage access permissions */ -+#define SM_PERM_READ 0x01 -+#define SM_PERM_WRITE 0x02 -+#define SM_PERM_BLOB 0x03 -+ -+ -+/* Keystore maintenance functions */ -+void sm_init_keystore(struct device *dev); -+u32 sm_detect_keystore_units(struct device *dev); -+int sm_establish_keystore(struct device *dev, u32 unit); -+void sm_release_keystore(struct device *dev, u32 unit); -+void caam_sm_shutdown(struct platform_device *pdev); -+int caam_sm_example_init(struct platform_device *pdev); -+ -+/* Keystore accessor functions */ -+extern int sm_keystore_slot_alloc(struct device *dev, u32 unit, u32 size, -+ u32 *slot); -+extern int sm_keystore_slot_dealloc(struct device *dev, u32 unit, u32 slot); -+extern int sm_keystore_slot_load(struct device *dev, u32 unit, u32 slot, -+ const u8 *key_data, u32 key_length); -+extern int sm_keystore_slot_read(struct device *dev, u32 unit, u32 slot, -+ u32 key_length, u8 *key_data); -+extern int sm_keystore_slot_encapsulate(struct device *dev, u32 unit, -+ u32 inslot, u32 outslot, u16 secretlen, -+ u8 *keymod, u16 keymodlen); -+extern int sm_keystore_slot_decapsulate(struct device *dev, u32 unit, -+ u32 inslot, u32 outslot, u16 secretlen, -+ u8 *keymod, u16 keymodlen); -+ -+/* Data structure to hold per-slot information */ -+struct keystore_data_slot_info { -+ u8 allocated; /* Track slot assignments */ -+ u32 key_length; /* Size of the key */ -+}; -+ -+/* Data structure to hold keystore information */ -+struct keystore_data { -+ void *base_address; /* Base of the Secure Partition */ -+ u32 slot_count; /* Number of slots in the keystore */ -+ struct keystore_data_slot_info *slot; /* Per-slot information */ -+}; -+ -+/* store the detected attributes of a secure memory page */ -+struct sm_page_descriptor { -+ u16 phys_pagenum; /* may be discontiguous */ -+ u16 own_part; /* Owning partition */ -+ void *pg_base; /* Calculated virtual address */ -+ struct keystore_data *ksdata; -+}; -+ -+struct caam_drv_private_sm { -+ struct device *parentdev; /* this ends up as the controller */ -+ struct device *smringdev; /* ring that owns this instance */ -+ spinlock_t kslock ____cacheline_aligned; -+ -+ /* Default parameters for geometry */ -+ u32 max_pages; /* maximum pages this instance can support */ -+ u32 top_partition; /* highest partition number in this instance */ -+ u32 top_page; /* highest page number in this instance */ -+ u32 page_size; /* page size */ -+ u32 slot_size; /* selected size of each storage block */ -+ -+ /* Partition/Page Allocation Map */ -+ u32 localpages; /* Number of pages we can access */ -+ struct sm_page_descriptor *pagedesc; /* Allocated per-page */ -+ -+ /* Installed handlers for keystore access */ -+ int (*data_init)(struct device *dev, u32 unit); -+ void (*data_cleanup)(struct device *dev, u32 unit); -+ int (*slot_alloc)(struct device *dev, u32 unit, u32 size, u32 *slot); -+ int (*slot_dealloc)(struct device *dev, u32 unit, u32 slot); -+ void *(*slot_get_address)(struct device *dev, u32 unit, u32 handle); -+ u32 (*slot_get_base)(struct device *dev, u32 unit, u32 handle); -+ u32 (*slot_get_offset)(struct device *dev, u32 unit, u32 handle); -+ u32 (*slot_get_slot_size)(struct device *dev, u32 unit, u32 handle); -+}; -+ -+#endif /* SM_H */ -diff -Nur linux-4.1.13.orig/drivers/crypto/caam/sm_store.c linux-4.1.13/drivers/crypto/caam/sm_store.c ---- linux-4.1.13.orig/drivers/crypto/caam/sm_store.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/crypto/caam/sm_store.c 2015-11-30 17:56:13.552139590 +0100 -@@ -0,0 +1,896 @@ -+ -+/* -+ * CAAM Secure Memory Storage Interface -+ * Copyright (C) 2008-2013 Freescale Semiconductor, Inc. -+ * -+ * Loosely based on the SHW Keystore API for SCC/SCC2 -+ * Experimental implementation and NOT intended for upstream use. Expect -+ * this interface to be amended significantly in the future once it becomes -+ * integrated into live applications. -+ * -+ * Known issues: -+ * -+ * - Executes one instance of an secure memory "driver". This is tied to the -+ * fact that job rings can't run as standalone instances in the present -+ * configuration. -+ * -+ * - It does not expose a userspace interface. The value of a userspace -+ * interface for access to secrets is a point for further architectural -+ * discussion. -+ * -+ * - Partition/permission management is not part of this interface. It -+ * depends on some level of "knowledge" agreed upon between bootloader, -+ * provisioning applications, and OS-hosted software (which uses this -+ * driver). -+ * -+ * - No means of identifying the location or purpose of secrets managed by -+ * this interface exists; "slot location" and format of a given secret -+ * needs to be agreed upon between bootloader, provisioner, and OS-hosted -+ * application. -+ */ -+ -+#include "compat.h" -+#include "regs.h" -+#include "jr.h" -+#include "desc.h" -+#include "intern.h" -+#include "error.h" -+#include "sm.h" -+ -+#ifdef SM_DEBUG_CONT -+void sm_show_page(struct device *dev, struct sm_page_descriptor *pgdesc) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ u32 i, *smdata; -+ -+ dev_info(dev, "physical page %d content at 0x%08x\n", -+ pgdesc->phys_pagenum, pgdesc->pg_base); -+ smdata = pgdesc->pg_base; -+ for (i = 0; i < (smpriv->page_size / sizeof(u32)); i += 4) -+ dev_info(dev, "[0x%08x] 0x%08x 0x%08x 0x%08x 0x%08x\n", -+ (u32)&smdata[i], smdata[i], smdata[i+1], smdata[i+2], -+ smdata[i+3]); -+} -+#endif -+ -+/* -+ * Construct a secure memory blob encapsulation job descriptor -+ * -+ * - desc pointer to hold new (to be allocated) pointer to the generated -+ * descriptor for later use. Calling thread can kfree the -+ * descriptor after execution. -+ * - keymod Physical pointer to key modifier (contiguous piece). -+ * - keymodsz Size of key modifier in bytes (should normally be 8). -+ * - secretbuf Physical pointer (within an accessible secure memory page) -+ * of the secret to be encapsulated. -+ * - outbuf Physical pointer (within an accessible secure memory page) -+ * of the encapsulated output. This will be larger than the -+ * input secret because of the added encapsulation data. -+ * - secretsz Size of input secret, in bytes. -+ * - auth If nonzero, use AES-CCM for encapsulation, else use ECB -+ * -+ * Note: this uses 32-bit pointers at present -+ */ -+#define INITIAL_DESCSZ 16 /* size of tmp buffer for descriptor const. */ -+static int blob_encap_desc(u32 **desc, dma_addr_t keymod, u16 keymodsz, -+ dma_addr_t secretbuf, dma_addr_t outbuf, -+ u16 secretsz, bool auth) -+{ -+ u32 *tdesc, tmpdesc[INITIAL_DESCSZ]; -+ u16 dsize, idx; -+ -+ memset(tmpdesc, 0, INITIAL_DESCSZ * sizeof(u32)); -+ idx = 1; -+ -+ /* Load key modifier */ -+ tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_KEY | -+ ((12 << LDST_OFFSET_SHIFT) & LDST_OFFSET_MASK) | -+ (keymodsz & LDST_LEN_MASK); -+ -+ tmpdesc[idx++] = (u32)keymod; -+ -+ /* Encapsulate to secure memory */ -+ tmpdesc[idx++] = CMD_SEQ_IN_PTR | secretsz; -+ tmpdesc[idx++] = (u32)secretbuf; -+ -+ /* Add space for BKEK and MAC tag */ -+ tmpdesc[idx++] = CMD_SEQ_IN_PTR | (secretsz + (32 + 16)); -+ -+ tmpdesc[idx++] = (u32)outbuf; -+ tmpdesc[idx] = CMD_OPERATION | OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB | -+ OP_PCL_BLOB_PTXT_SECMEM; -+ if (auth) -+ tmpdesc[idx] |= OP_PCL_BLOB_EKT; -+ -+ idx++; -+ tmpdesc[0] = CMD_DESC_HDR | HDR_ONE | (idx & HDR_DESCLEN_MASK); -+ dsize = idx * sizeof(u32); -+ -+ tdesc = kmalloc(dsize, GFP_KERNEL | GFP_DMA); -+ if (tdesc == NULL) -+ return 0; -+ -+ memcpy(tdesc, tmpdesc, dsize); -+ *desc = tdesc; -+ return dsize; -+} -+ -+/* -+ * Construct a secure memory blob decapsulation job descriptor -+ * -+ * - desc pointer to hold new (to be allocated) pointer to the generated -+ * descriptor for later use. Calling thread can kfree the -+ * descriptor after execution. -+ * - keymod Physical pointer to key modifier (contiguous piece). -+ * - keymodsz Size of key modifier in bytes (should normally be 16). -+ * - blobbuf Physical pointer (within an accessible secure memory page) -+ * of the blob to be decapsulated. -+ * - outbuf Physical pointer (within an accessible secure memory page) -+ * of the decapsulated output. -+ * - secretsz Size of input blob, in bytes. -+ * - auth If nonzero, assume AES-CCM for decapsulation, else use ECB -+ * -+ * Note: this uses 32-bit pointers at present -+ */ -+static int blob_decap_desc(u32 **desc, dma_addr_t keymod, u16 keymodsz, -+ dma_addr_t blobbuf, dma_addr_t outbuf, -+ u16 blobsz, bool auth) -+{ -+ u32 *tdesc, tmpdesc[INITIAL_DESCSZ]; -+ u16 dsize, idx; -+ -+ memset(tmpdesc, 0, INITIAL_DESCSZ * sizeof(u32)); -+ idx = 1; -+ -+ /* Load key modifier */ -+ tmpdesc[idx++] = CMD_LOAD | LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_KEY | -+ ((12 << LDST_OFFSET_SHIFT) & LDST_OFFSET_MASK) | -+ (keymodsz & LDST_LEN_MASK); -+ -+ tmpdesc[idx++] = (u32)keymod; -+ -+ /* Compensate BKEK + MAC tag */ -+ tmpdesc[idx++] = CMD_SEQ_IN_PTR | (blobsz + 32 + 16); -+ -+ tmpdesc[idx++] = (u32)blobbuf; -+ tmpdesc[idx++] = CMD_SEQ_OUT_PTR | blobsz; -+ tmpdesc[idx++] = (u32)outbuf; -+ -+ /* Decapsulate from secure memory partition to black blob */ -+ tmpdesc[idx] = CMD_OPERATION | OP_TYPE_DECAP_PROTOCOL | OP_PCLID_BLOB | -+ OP_PCL_BLOB_PTXT_SECMEM | OP_PCL_BLOB_BLACK; -+ if (auth) -+ tmpdesc[idx] |= OP_PCL_BLOB_EKT; -+ -+ idx++; -+ tmpdesc[0] = CMD_DESC_HDR | HDR_ONE | (idx & HDR_DESCLEN_MASK); -+ dsize = idx * sizeof(u32); -+ -+ tdesc = kmalloc(dsize, GFP_KERNEL | GFP_DMA); -+ if (tdesc == NULL) -+ return 0; -+ -+ memcpy(tdesc, tmpdesc, dsize); -+ *desc = tdesc; -+ return dsize; -+} -+ -+/* -+ * Pseudo-synchronous ring access functions for carrying out key -+ * encapsulation and decapsulation -+ */ -+ -+struct sm_key_job_result { -+ int error; -+ struct completion completion; -+}; -+ -+void sm_key_job_done(struct device *dev, u32 *desc, u32 err, void *context) -+{ -+ struct sm_key_job_result *res = context; -+ -+ res->error = err; /* save off the error for postprocessing */ -+ complete(&res->completion); /* mark us complete */ -+} -+ -+static int sm_key_job(struct device *ksdev, u32 *jobdesc) -+{ -+ struct sm_key_job_result testres; -+ struct caam_drv_private_sm *kspriv; -+ int rtn = 0; -+ -+ kspriv = dev_get_drvdata(ksdev); -+ -+ init_completion(&testres.completion); -+ -+ rtn = caam_jr_enqueue(kspriv->smringdev, jobdesc, sm_key_job_done, -+ &testres); -+ if (!rtn) { -+ wait_for_completion_interruptible(&testres.completion); -+ rtn = testres.error; -+ } -+ return rtn; -+} -+ -+/* -+ * Following section establishes the default methods for keystore access -+ * They are NOT intended for use external to this module -+ * -+ * In the present version, these are the only means for the higher-level -+ * interface to deal with the mechanics of accessing the phyiscal keystore -+ */ -+ -+ -+int slot_alloc(struct device *dev, u32 unit, u32 size, u32 *slot) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata; -+ u32 i; -+#ifdef SM_DEBUG -+ dev_info(dev, "slot_alloc(): requesting slot for %d bytes\n", size); -+#endif -+ -+ if (size > smpriv->slot_size) -+ return -EKEYREJECTED; -+ -+ for (i = 0; i < ksdata->slot_count; i++) { -+ if (ksdata->slot[i].allocated == 0) { -+ ksdata->slot[i].allocated = 1; -+ (*slot) = i; -+#ifdef SM_DEBUG -+ dev_info(dev, "slot_alloc(): new slot %d allocated\n", -+ *slot); -+#endif -+ return 0; -+ } -+ } -+ -+ return -ENOSPC; -+} -+EXPORT_SYMBOL(slot_alloc); -+ -+int slot_dealloc(struct device *dev, u32 unit, u32 slot) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata; -+ u8 __iomem *slotdata; -+ -+#ifdef SM_DEBUG -+ dev_info(dev, "slot_dealloc(): releasing slot %d\n", slot); -+#endif -+ if (slot >= ksdata->slot_count) -+ return -EINVAL; -+ slotdata = ksdata->base_address + slot * smpriv->slot_size; -+ -+ if (ksdata->slot[slot].allocated == 1) { -+ /* Forcibly overwrite the data from the keystore */ -+ memset(ksdata->base_address + slot * smpriv->slot_size, 0, -+ smpriv->slot_size); -+ -+ ksdata->slot[slot].allocated = 0; -+#ifdef SM_DEBUG -+ dev_info(dev, "slot_dealloc(): slot %d released\n", slot); -+#endif -+ return 0; -+ } -+ -+ return -EINVAL; -+} -+EXPORT_SYMBOL(slot_dealloc); -+ -+void *slot_get_address(struct device *dev, u32 unit, u32 slot) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata; -+ -+ if (slot >= ksdata->slot_count) -+ return NULL; -+ -+#ifdef SM_DEBUG -+ dev_info(dev, "slot_get_address(): slot %d is 0x%08x\n", slot, -+ (u32)ksdata->base_address + slot * smpriv->slot_size); -+#endif -+ -+ return ksdata->base_address + slot * smpriv->slot_size; -+} -+ -+u32 slot_get_base(struct device *dev, u32 unit, u32 slot) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata; -+ -+ /* -+ * There could potentially be more than one secure partition object -+ * associated with this keystore. For now, there is just one. -+ */ -+ -+ (void)slot; -+ -+#ifdef SM_DEBUG -+ dev_info(dev, "slot_get_base(): slot %d = 0x%08x\n", -+ slot, (u32)ksdata->base_address); -+#endif -+ -+ return (u32)(ksdata->base_address); -+} -+ -+u32 slot_get_offset(struct device *dev, u32 unit, u32 slot) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ struct keystore_data *ksdata = smpriv->pagedesc[unit].ksdata; -+ -+ if (slot >= ksdata->slot_count) -+ return -EINVAL; -+ -+#ifdef SM_DEBUG -+ dev_info(dev, "slot_get_offset(): slot %d = %d\n", slot, -+ slot * smpriv->slot_size); -+#endif -+ -+ return slot * smpriv->slot_size; -+} -+ -+u32 slot_get_slot_size(struct device *dev, u32 unit, u32 slot) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ -+ -+#ifdef SM_DEBUG -+ dev_info(dev, "slot_get_slot_size(): slot %d = %d\n", slot, -+ smpriv->slot_size); -+#endif -+ /* All slots are the same size in the default implementation */ -+ return smpriv->slot_size; -+} -+ -+ -+ -+int kso_init_data(struct device *dev, u32 unit) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ int retval = -EINVAL; -+ struct keystore_data *keystore_data = NULL; -+ u32 slot_count; -+ u32 keystore_data_size; -+ -+ /* -+ * Calculate the required size of the keystore data structure, based -+ * on the number of keys that can fit in the partition. -+ */ -+ slot_count = smpriv->page_size / smpriv->slot_size; -+#ifdef SM_DEBUG -+ dev_info(dev, "kso_init_data: %d slots initializing\n", slot_count); -+#endif -+ -+ keystore_data_size = sizeof(struct keystore_data) + -+ slot_count * -+ sizeof(struct keystore_data_slot_info); -+ -+ keystore_data = kzalloc(keystore_data_size, GFP_KERNEL); -+ -+ if (keystore_data == NULL) { -+ retval = -ENOSPC; -+ goto out; -+ } -+ -+#ifdef SM_DEBUG -+ dev_info(dev, "kso_init_data: keystore data size = %d\n", -+ keystore_data_size); -+#endif -+ -+ /* -+ * Place the slot information structure directly after the keystore data -+ * structure. -+ */ -+ keystore_data->slot = (struct keystore_data_slot_info *) -+ (keystore_data + 1); -+ keystore_data->slot_count = slot_count; -+ -+ smpriv->pagedesc[unit].ksdata = keystore_data; -+ smpriv->pagedesc[unit].ksdata->base_address = -+ smpriv->pagedesc[unit].pg_base; -+ -+ retval = 0; -+ -+out: -+ if (retval != 0) -+ if (keystore_data != NULL) -+ kfree(keystore_data); -+ -+ -+ return retval; -+} -+ -+void kso_cleanup_data(struct device *dev, u32 unit) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ struct keystore_data *keystore_data = NULL; -+ -+ if (smpriv->pagedesc[unit].ksdata != NULL) -+ keystore_data = smpriv->pagedesc[unit].ksdata; -+ -+ /* Release the allocated keystore management data */ -+ kfree(smpriv->pagedesc[unit].ksdata); -+ -+ return; -+} -+ -+ -+ -+/* -+ * Keystore management section -+ */ -+ -+void sm_init_keystore(struct device *dev) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ -+ smpriv->data_init = kso_init_data; -+ smpriv->data_cleanup = kso_cleanup_data; -+ smpriv->slot_alloc = slot_alloc; -+ smpriv->slot_dealloc = slot_dealloc; -+ smpriv->slot_get_address = slot_get_address; -+ smpriv->slot_get_base = slot_get_base; -+ smpriv->slot_get_offset = slot_get_offset; -+ smpriv->slot_get_slot_size = slot_get_slot_size; -+#ifdef SM_DEBUG -+ dev_info(dev, "sm_init_keystore(): handlers installed\n"); -+#endif -+} -+EXPORT_SYMBOL(sm_init_keystore); -+ -+/* Return available pages/units */ -+u32 sm_detect_keystore_units(struct device *dev) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ -+ return smpriv->localpages; -+} -+EXPORT_SYMBOL(sm_detect_keystore_units); -+ -+/* -+ * Do any keystore specific initializations -+ */ -+int sm_establish_keystore(struct device *dev, u32 unit) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ -+#ifdef SM_DEBUG -+ dev_info(dev, "sm_establish_keystore(): unit %d initializing\n", unit); -+#endif -+ -+ if (smpriv->data_init == NULL) -+ return -EINVAL; -+ -+ /* Call the data_init function for any user setup */ -+ return smpriv->data_init(dev, unit); -+} -+EXPORT_SYMBOL(sm_establish_keystore); -+ -+void sm_release_keystore(struct device *dev, u32 unit) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ -+#ifdef SM_DEBUG -+ dev_info(dev, "sm_establish_keystore(): unit %d releasing\n", unit); -+#endif -+ if ((smpriv != NULL) && (smpriv->data_cleanup != NULL)) -+ smpriv->data_cleanup(dev, unit); -+ -+ return; -+} -+EXPORT_SYMBOL(sm_release_keystore); -+ -+/* -+ * Subsequent interfacce (sm_keystore_*) forms the accessor interfacce to -+ * the keystore -+ */ -+int sm_keystore_slot_alloc(struct device *dev, u32 unit, u32 size, u32 *slot) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ int retval = -EINVAL; -+ -+ spin_lock(&smpriv->kslock); -+ -+ if ((smpriv->slot_alloc == NULL) || -+ (smpriv->pagedesc[unit].ksdata == NULL)) -+ goto out; -+ -+ retval = smpriv->slot_alloc(dev, unit, size, slot); -+ -+out: -+ spin_unlock(&smpriv->kslock); -+ return retval; -+} -+EXPORT_SYMBOL(sm_keystore_slot_alloc); -+ -+int sm_keystore_slot_dealloc(struct device *dev, u32 unit, u32 slot) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ int retval = -EINVAL; -+ -+ spin_lock(&smpriv->kslock); -+ -+ if ((smpriv->slot_alloc == NULL) || -+ (smpriv->pagedesc[unit].ksdata == NULL)) -+ goto out; -+ -+ retval = smpriv->slot_dealloc(dev, unit, slot); -+out: -+ spin_unlock(&smpriv->kslock); -+ return retval; -+} -+EXPORT_SYMBOL(sm_keystore_slot_dealloc); -+ -+int sm_keystore_slot_load(struct device *dev, u32 unit, u32 slot, -+ const u8 *key_data, u32 key_length) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ int retval = -EINVAL; -+ u32 slot_size; -+ u32 i; -+ u8 __iomem *slot_location; -+ -+ spin_lock(&smpriv->kslock); -+ -+ slot_size = smpriv->slot_get_slot_size(dev, unit, slot); -+ -+ if (key_length > slot_size) { -+ retval = -EFBIG; -+ goto out; -+ } -+ -+ slot_location = smpriv->slot_get_address(dev, unit, slot); -+ -+ for (i = 0; i < key_length; i++) -+ slot_location[i] = key_data[i]; -+ -+ retval = 0; -+ -+out: -+ spin_unlock(&smpriv->kslock); -+ return retval; -+} -+EXPORT_SYMBOL(sm_keystore_slot_load); -+ -+int sm_keystore_slot_read(struct device *dev, u32 unit, u32 slot, -+ u32 key_length, u8 *key_data) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ int retval = -EINVAL; -+ u8 __iomem *slot_addr; -+ u32 slot_size; -+ -+ spin_lock(&smpriv->kslock); -+ -+ slot_addr = smpriv->slot_get_address(dev, unit, slot); -+ slot_size = smpriv->slot_get_slot_size(dev, unit, slot); -+ -+ if (key_length > slot_size) { -+ retval = -EKEYREJECTED; -+ goto out; -+ } -+ -+ memcpy(key_data, slot_addr, key_length); -+ retval = 0; -+ -+out: -+ spin_unlock(&smpriv->kslock); -+ return retval; -+} -+EXPORT_SYMBOL(sm_keystore_slot_read); -+ -+int sm_keystore_slot_encapsulate(struct device *dev, u32 unit, u32 inslot, -+ u32 outslot, u16 secretlen, u8 *keymod, -+ u16 keymodlen) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ int retval = 0; -+ u32 slot_length, dsize, jstat; -+ u32 __iomem *encapdesc = NULL; -+ u8 __iomem *lkeymod, *inpslotaddr, *outslotaddr; -+ dma_addr_t keymod_dma; -+ -+ /* Ensure that the full blob will fit in the key slot */ -+ slot_length = smpriv->slot_get_slot_size(dev, unit, outslot); -+ if ((secretlen + 48) > slot_length) -+ goto out; -+ -+ /* Get the base addresses of both keystore slots */ -+ inpslotaddr = (u8 *)smpriv->slot_get_address(dev, unit, inslot); -+ outslotaddr = (u8 *)smpriv->slot_get_address(dev, unit, outslot); -+ -+ /* Build the key modifier */ -+ lkeymod = kmalloc(keymodlen, GFP_KERNEL | GFP_DMA); -+ memcpy(lkeymod, keymod, keymodlen); -+ keymod_dma = dma_map_single(dev, lkeymod, keymodlen, DMA_TO_DEVICE); -+ dma_sync_single_for_device(dev, keymod_dma, keymodlen, DMA_TO_DEVICE); -+ -+ /* Build the encapsulation job descriptor */ -+ dsize = blob_encap_desc(&encapdesc, keymod_dma, keymodlen, -+ __pa(inpslotaddr), __pa(outslotaddr), -+ secretlen, 0); -+ if (!dsize) { -+ dev_err(dev, "can't alloc an encap descriptor\n"); -+ retval = -ENOMEM; -+ goto out; -+ } -+ jstat = sm_key_job(dev, encapdesc); -+ -+ dma_unmap_single(dev, keymod_dma, keymodlen, DMA_TO_DEVICE); -+ kfree(encapdesc); -+ -+out: -+ return retval; -+ -+} -+EXPORT_SYMBOL(sm_keystore_slot_encapsulate); -+ -+int sm_keystore_slot_decapsulate(struct device *dev, u32 unit, u32 inslot, -+ u32 outslot, u16 secretlen, u8 *keymod, -+ u16 keymodlen) -+{ -+ struct caam_drv_private_sm *smpriv = dev_get_drvdata(dev); -+ int retval = 0; -+ u32 slot_length, dsize, jstat; -+ u32 __iomem *decapdesc = NULL; -+ u8 __iomem *lkeymod, *inpslotaddr, *outslotaddr; -+ dma_addr_t keymod_dma; -+ -+ /* Ensure that the decap data will fit in the key slot */ -+ slot_length = smpriv->slot_get_slot_size(dev, unit, outslot); -+ if (secretlen > slot_length) -+ goto out; -+ -+ /* Get the base addresses of both keystore slots */ -+ inpslotaddr = (u8 *)smpriv->slot_get_address(dev, unit, inslot); -+ outslotaddr = (u8 *)smpriv->slot_get_address(dev, unit, outslot); -+ -+ /* Build the key modifier */ -+ lkeymod = kmalloc(keymodlen, GFP_KERNEL | GFP_DMA); -+ memcpy(lkeymod, keymod, keymodlen); -+ keymod_dma = dma_map_single(dev, lkeymod, keymodlen, DMA_TO_DEVICE); -+ dma_sync_single_for_device(dev, keymod_dma, keymodlen, DMA_TO_DEVICE); -+ -+ /* Build the decapsulation job descriptor */ -+ dsize = blob_decap_desc(&decapdesc, keymod_dma, keymodlen, -+ __pa(inpslotaddr), __pa(outslotaddr), -+ secretlen, 0); -+ if (!dsize) { -+ dev_err(dev, "can't alloc a decap descriptor\n"); -+ retval = -ENOMEM; -+ goto out; -+ } -+ jstat = sm_key_job(dev, decapdesc); -+ -+ dma_unmap_single(dev, keymod_dma, keymodlen, DMA_TO_DEVICE); -+ kfree(decapdesc); -+ -+out: -+ return retval; -+ -+} -+EXPORT_SYMBOL(sm_keystore_slot_decapsulate); -+ -+ -+/* -+ * Initialization/shutdown subsystem -+ * Assumes statically-invoked startup/shutdown from the controller driver -+ * for the present time, to be reworked when a device tree becomes -+ * available. This code will not modularize in present form. -+ * -+ * Also, simply uses ring 0 for execution at the present -+ */ -+ -+int caam_sm_startup(struct platform_device *pdev) -+{ -+ struct device *ctrldev, *smdev; -+ struct caam_drv_private *ctrlpriv; -+ struct caam_drv_private_sm *smpriv; -+ struct caam_drv_private_jr *jrpriv; /* need this for reg page */ -+ struct platform_device *sm_pdev; -+ struct sm_page_descriptor *lpagedesc; -+ u32 page, pgstat, lpagect, detectedpage; -+ -+ struct device_node *np; -+ ctrldev = &pdev->dev; -+ ctrlpriv = dev_get_drvdata(ctrldev); -+ -+ /* -+ * Set up the private block for secure memory -+ * Only one instance is possible -+ */ -+ smpriv = kzalloc(sizeof(struct caam_drv_private_sm), GFP_KERNEL); -+ if (smpriv == NULL) { -+ dev_err(ctrldev, "can't alloc private mem for secure memory\n"); -+ return -ENOMEM; -+ } -+ smpriv->parentdev = ctrldev; /* copy of parent dev is handy */ -+ -+ /* Create the dev */ -+#ifdef CONFIG_OF -+ np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-caam-sm"); -+ sm_pdev = of_platform_device_create(np, "caam_sm", ctrldev); -+#else -+ sm_pdev = platform_device_register_data(ctrldev, "caam_sm", 0, -+ smpriv, -+ sizeof(struct caam_drv_private_sm)); -+#endif -+ if (sm_pdev == NULL) { -+ kfree(smpriv); -+ return -EINVAL; -+ } -+ smdev = &sm_pdev->dev; -+ dev_set_drvdata(smdev, smpriv); -+ ctrlpriv->smdev = smdev; -+ -+ /* -+ * Collect configuration limit data for reference -+ * This batch comes from the partition data/vid registers in perfmon -+ */ -+ smpriv->max_pages = ((rd_reg32(&ctrlpriv->ctrl->perfmon.smpart) -+ & SMPART_MAX_NUMPG_MASK) >> -+ SMPART_MAX_NUMPG_SHIFT) + 1; -+ smpriv->top_partition = ((rd_reg32(&ctrlpriv->ctrl->perfmon.smpart) -+ & SMPART_MAX_PNUM_MASK) >> -+ SMPART_MAX_PNUM_SHIFT) + 1; -+ smpriv->top_page = ((rd_reg32(&ctrlpriv->ctrl->perfmon.smpart) -+ & SMPART_MAX_PG_MASK) >> SMPART_MAX_PG_SHIFT) + 1; -+ smpriv->page_size = 1024 << ((rd_reg32(&ctrlpriv->ctrl->perfmon.smvid) -+ & SMVID_PG_SIZE_MASK) >> SMVID_PG_SIZE_SHIFT); -+ smpriv->slot_size = 1 << CONFIG_CRYPTO_DEV_FSL_CAAM_SM_SLOTSIZE; -+ -+#ifdef SM_DEBUG -+ dev_info(smdev, "max pages = %d, top partition = %d\n", -+ smpriv->max_pages, smpriv->top_partition); -+ dev_info(smdev, "top page = %d, page size = %d (total = %d)\n", -+ smpriv->top_page, smpriv->page_size, -+ smpriv->top_page * smpriv->page_size); -+ dev_info(smdev, "selected slot size = %d\n", smpriv->slot_size); -+#endif -+ -+ /* -+ * Now probe for partitions/pages to which we have access. Note that -+ * these have likely been set up by a bootloader or platform -+ * provisioning application, so we have to assume that we "inherit" -+ * a configuration and work within the constraints of what it might be. -+ * -+ * Assume use of the zeroth ring in the present iteration (until -+ * we can divorce the controller and ring drivers, and then assign -+ * an SM instance to any ring instance). -+ */ -+ smpriv->smringdev = ctrlpriv->jrdev[0]; -+ jrpriv = dev_get_drvdata(smpriv->smringdev); -+ lpagect = 0; -+ lpagedesc = kzalloc(sizeof(struct sm_page_descriptor) -+ * smpriv->max_pages, GFP_KERNEL); -+ if (lpagedesc == NULL) { -+ kfree(smpriv); -+ return -ENOMEM; -+ } -+ -+ for (page = 0; page < smpriv->max_pages; page++) { -+ wr_reg32(&jrpriv->rregs->sm_cmd, -+ ((page << SMC_PAGE_SHIFT) & SMC_PAGE_MASK) | -+ (SMC_CMD_PAGE_INQUIRY & SMC_CMD_MASK)); -+ pgstat = rd_reg32(&jrpriv->rregs->sm_status); -+ if (((pgstat & SMCS_PGWON_MASK) >> SMCS_PGOWN_SHIFT) -+ == SMCS_PGOWN_OWNED) { /* our page? */ -+ lpagedesc[page].phys_pagenum = -+ (pgstat & SMCS_PAGE_MASK) >> SMCS_PAGE_SHIFT; -+ lpagedesc[page].own_part = -+ (pgstat & SMCS_PART_SHIFT) >> SMCS_PART_MASK; -+ lpagedesc[page].pg_base = ctrlpriv->sm_base + -+ ((smpriv->page_size * page) / sizeof(u32)); -+ lpagect++; -+#ifdef SM_DEBUG -+ dev_info(smdev, -+ "physical page %d, owning partition = %d\n", -+ lpagedesc[page].phys_pagenum, -+ lpagedesc[page].own_part); -+#endif -+ } -+ } -+ -+ smpriv->pagedesc = kzalloc(sizeof(struct sm_page_descriptor) * lpagect, -+ GFP_KERNEL); -+ if (smpriv->pagedesc == NULL) { -+ kfree(lpagedesc); -+ kfree(smpriv); -+ return -ENOMEM; -+ } -+ smpriv->localpages = lpagect; -+ -+ detectedpage = 0; -+ for (page = 0; page < smpriv->max_pages; page++) { -+ if (lpagedesc[page].pg_base != NULL) { /* e.g. live entry */ -+ memcpy(&smpriv->pagedesc[detectedpage], -+ &lpagedesc[page], -+ sizeof(struct sm_page_descriptor)); -+#ifdef SM_DEBUG_CONT -+ sm_show_page(smdev, &smpriv->pagedesc[detectedpage]); -+#endif -+ detectedpage++; -+ } -+ } -+ -+ kfree(lpagedesc); -+ -+ sm_init_keystore(smdev); -+ -+ return 0; -+} -+ -+void caam_sm_shutdown(struct platform_device *pdev) -+{ -+ struct device *ctrldev, *smdev; -+ struct caam_drv_private *priv; -+ struct caam_drv_private_sm *smpriv; -+ -+ ctrldev = &pdev->dev; -+ priv = dev_get_drvdata(ctrldev); -+ smdev = priv->smdev; -+ smpriv = dev_get_drvdata(smdev); -+ -+ kfree(smpriv->pagedesc); -+ kfree(smpriv); -+} -+EXPORT_SYMBOL(caam_sm_shutdown); -+#ifdef CONFIG_OF -+static void __exit caam_sm_exit(void) -+{ -+ struct device_node *dev_node; -+ struct platform_device *pdev; -+ -+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); -+ if (!dev_node) { -+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0"); -+ if (!dev_node) -+ return; -+ } -+ -+ pdev = of_find_device_by_node(dev_node); -+ if (!pdev) -+ return; -+ -+ of_node_put(dev_node); -+ -+ caam_sm_shutdown(pdev); -+ -+ return; -+} -+ -+static int __init caam_sm_init(void) -+{ -+ struct device_node *dev_node; -+ struct platform_device *pdev; -+ -+ /* -+ * Do of_find_compatible_node() then of_find_device_by_node() -+ * once a functional device tree is available -+ */ -+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); -+ if (!dev_node) { -+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0"); -+ if (!dev_node) -+ return -ENODEV; -+ } -+ -+ pdev = of_find_device_by_node(dev_node); -+ if (!pdev) -+ return -ENODEV; -+ -+ of_node_get(dev_node); -+ -+ caam_sm_startup(pdev); -+ -+ return 0; -+} -+ -+module_init(caam_sm_init); -+module_exit(caam_sm_exit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_DESCRIPTION("FSL CAAM Secure Memory / Keystore"); -+MODULE_AUTHOR("Freescale Semiconductor - NMSG/MAD"); -+#endif -diff -Nur linux-4.1.13.orig/drivers/crypto/caam/sm_test.c linux-4.1.13/drivers/crypto/caam/sm_test.c ---- linux-4.1.13.orig/drivers/crypto/caam/sm_test.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/crypto/caam/sm_test.c 2015-11-30 17:56:13.552139590 +0100 -@@ -0,0 +1,844 @@ -+/* -+ * Secure Memory / Keystore Exemplification Module -+ * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved -+ * -+ * Serves as a functional example, and as a self-contained unit test for -+ * the functionality contained in sm_store.c. -+ * -+ * The example function, caam_sm_example_init(), runs a thread that: -+ * -+ * - initializes a set of fixed keys -+ * - stores one copy in clear buffers -+ * - stores them again in secure memory -+ * - extracts stored keys back out for use -+ * - intializes 3 data buffers for a test: -+ * (1) containing cleartext -+ * (2) to hold ciphertext encrypted with an extracted black key -+ * (3) to hold extracted cleartext decrypted with an equivalent clear key -+ * -+ * The function then builds simple job descriptors that reference the key -+ * material and buffers as initialized, and executes an encryption job -+ * with a black key, and a decryption job using a the same key held in the -+ * clear. The output of the decryption job is compared to the original -+ * cleartext; if they don't compare correctly, one can assume a key problem -+ * exists, where the function will exit with an error. -+ * -+ * This module can use a substantial amount of refactoring, which may occur -+ * after the API gets some mileage. Furthermore, expect this module to -+ * eventually disappear once the API is integrated into "real" software. -+ */ -+ -+#include "compat.h" -+#include "intern.h" -+#include "desc.h" -+#include "error.h" -+#include "jr.h" -+#include "sm.h" -+ -+static u8 skeymod[] = { -+ 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, -+ 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00 -+}; -+static u8 symkey[] = { -+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, -+ 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, -+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, -+ 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f -+}; -+ -+static u8 symdata[] = { -+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x0f, 0x06, 0x07, -+ 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, -+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, -+ 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, -+ 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, -+ 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, -+ 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, -+ 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, -+ 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, -+ 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, -+ 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, -+ 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, -+ 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, -+ 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, -+ 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, -+ 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, -+ 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, -+ 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, -+ 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, -+ 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, -+ 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, -+ 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, -+ 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, -+ 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, -+ 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, -+ 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, -+ 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, -+ 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, -+ 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, -+ 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, -+ 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, -+ 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff -+}; -+ -+static int mk_job_desc(u32 *desc, dma_addr_t key, u16 keysz, dma_addr_t indata, -+ dma_addr_t outdata, u16 sz, u32 cipherdir, u32 keymode) -+{ -+ desc[1] = CMD_KEY | CLASS_1 | (keysz & KEY_LENGTH_MASK) | keymode; -+ desc[2] = (u32)key; -+ desc[3] = CMD_OPERATION | OP_TYPE_CLASS1_ALG | OP_ALG_AAI_ECB | -+ cipherdir; -+ desc[4] = CMD_FIFO_LOAD | FIFOLD_CLASS_CLASS1 | -+ FIFOLD_TYPE_MSG | FIFOLD_TYPE_LAST1 | sz; -+ desc[5] = (u32)indata; -+ desc[6] = CMD_FIFO_STORE | FIFOST_TYPE_MESSAGE_DATA | sz; -+ desc[7] = (u32)outdata; -+ -+ desc[0] = CMD_DESC_HDR | HDR_ONE | (8 & HDR_DESCLEN_MASK); -+ return 8 * sizeof(u32); -+} -+ -+struct exec_test_result { -+ int error; -+ struct completion completion; -+}; -+ -+void exec_test_done(struct device *dev, u32 *desc, u32 err, void *context) -+{ -+ struct exec_test_result *res = context; -+ -+ if (err) { -+ char tmp[CAAM_ERROR_STR_MAX]; -+ dev_err(dev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err)); -+ } -+ -+ res->error = err; -+ complete(&res->completion); -+} -+ -+static int exec_test_job(struct device *ksdev, u32 *jobdesc) -+{ -+ struct exec_test_result testres; -+ struct caam_drv_private_sm *kspriv; -+ int rtn = 0; -+ -+ kspriv = dev_get_drvdata(ksdev); -+ -+ init_completion(&testres.completion); -+ -+ rtn = caam_jr_enqueue(kspriv->smringdev, jobdesc, exec_test_done, -+ &testres); -+ if (!rtn) { -+ wait_for_completion_interruptible(&testres.completion); -+ rtn = testres.error; -+ } -+ return rtn; -+} -+ -+ -+int caam_sm_example_init(struct platform_device *pdev) -+{ -+ struct device *ctrldev, *ksdev; -+ struct caam_drv_private *ctrlpriv; -+ struct caam_drv_private_sm *kspriv; -+ u32 unit, units, jdescsz; -+ int stat, jstat, rtnval = 0; -+ u8 __iomem *syminp, *symint, *symout = NULL; -+ dma_addr_t syminp_dma, symint_dma, symout_dma; -+ u8 __iomem *black_key_des, *black_key_aes128; -+ u8 __iomem *black_key_aes256; -+ dma_addr_t black_key_des_dma, black_key_aes128_dma; -+ dma_addr_t black_key_aes256_dma; -+ u8 __iomem *clear_key_des, *clear_key_aes128, *clear_key_aes256; -+ dma_addr_t clear_key_des_dma, clear_key_aes128_dma; -+ dma_addr_t clear_key_aes256_dma; -+ u32 __iomem *jdesc; -+ u32 keyslot_des, keyslot_aes128, keyslot_aes256 = 0; -+ -+ jdesc = NULL; -+ black_key_des = black_key_aes128 = black_key_aes256 = NULL; -+ clear_key_des = clear_key_aes128 = clear_key_aes256 = NULL; -+ -+ /* We can lose this cruft once we can get a pdev by name */ -+ ctrldev = &pdev->dev; -+ ctrlpriv = dev_get_drvdata(ctrldev); -+ ksdev = ctrlpriv->smdev; -+ kspriv = dev_get_drvdata(ksdev); -+ if (kspriv == NULL) -+ return -ENODEV; -+ -+ /* Now that we have the dev for the single SM instance, connect */ -+#ifdef SM_TEST_DETAIL -+ dev_info(ksdev, "caam_sm_test_init() running\n"); -+#endif -+ /* Probe to see what keystores are available to us */ -+ units = sm_detect_keystore_units(ksdev); -+ if (!units) -+ dev_err(ksdev, "caam_sm_test: no keystore units available\n"); -+ -+ /* -+ * MX6 bootloader stores some stuff in unit 0, so let's -+ * use 1 or above -+ */ -+ if (units < 2) { -+ dev_err(ksdev, "caam_sm_test: insufficient keystore units\n"); -+ return -ENODEV; -+ } -+ unit = 1; -+ -+#ifdef SM_TEST_DETAIL -+ dev_info(ksdev, "caam_sm_test: %d keystore units available\n", units); -+#endif -+ -+ /* Initialize/Establish Keystore */ -+ sm_establish_keystore(ksdev, unit); /* Initalize store in #1 */ -+ -+ /* -+ * Top of main test thread -+ */ -+ -+ /* Allocate test data blocks (input, intermediate, output) */ -+ syminp = kmalloc(256, GFP_KERNEL | GFP_DMA); -+ symint = kmalloc(256, GFP_KERNEL | GFP_DMA); -+ symout = kmalloc(256, GFP_KERNEL | GFP_DMA); -+ if ((syminp == NULL) || (symint == NULL) || (symout == NULL)) { -+ rtnval = -ENOMEM; -+ dev_err(ksdev, "caam_sm_test: can't get test data buffers\n"); -+ goto freemem; -+ } -+ -+ /* Allocate storage for 3 black keys: encapsulated 8, 16, 32 */ -+ black_key_des = kmalloc(16, GFP_KERNEL | GFP_DMA); /* padded to 16... */ -+ black_key_aes128 = kmalloc(16, GFP_KERNEL | GFP_DMA); -+ black_key_aes256 = kmalloc(16, GFP_KERNEL | GFP_DMA); -+ if ((black_key_des == NULL) || (black_key_aes128 == NULL) || -+ (black_key_aes256 == NULL)) { -+ rtnval = -ENOMEM; -+ dev_err(ksdev, "caam_sm_test: can't black key buffers\n"); -+ goto freemem; -+ } -+ -+ clear_key_des = kmalloc(8, GFP_KERNEL | GFP_DMA); -+ clear_key_aes128 = kmalloc(16, GFP_KERNEL | GFP_DMA); -+ clear_key_aes256 = kmalloc(32, GFP_KERNEL | GFP_DMA); -+ if ((clear_key_des == NULL) || (clear_key_aes128 == NULL) || -+ (clear_key_aes256 == NULL)) { -+ rtnval = -ENOMEM; -+ dev_err(ksdev, "caam_sm_test: can't get clear key buffers\n"); -+ goto freemem; -+ } -+ -+ /* Allocate storage for job descriptor */ -+ jdesc = kmalloc(8 * sizeof(u32), GFP_KERNEL | GFP_DMA); -+ if (jdesc == NULL) { -+ rtnval = -ENOMEM; -+ dev_err(ksdev, "caam_sm_test: can't get descriptor buffers\n"); -+ goto freemem; -+ } -+ -+#ifdef SM_TEST_DETAIL -+ dev_info(ksdev, "caam_sm_test: all buffers allocated\n"); -+#endif -+ -+ /* Load up input data block, clear outputs */ -+ memcpy(syminp, symdata, 256); -+ memset(symint, 0, 256); -+ memset(symout, 0, 256); -+#ifdef SM_TEST_DETAIL -+ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \ -+ "0x%02x 0x%02x 0x%02x 0x%02x\n", -+ syminp[0], syminp[1], syminp[2], syminp[3], -+ syminp[4], syminp[5], syminp[6], syminp[7]); -+ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \ -+ "0x%02x 0x%02x 0x%02x 0x%02x\n", -+ symint[0], symint[1], symint[2], symint[3], -+ symint[4], symint[5], symint[6], symint[7]); -+ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \ -+ "0x%02x 0x%02x 0x%02x 0x%02x\n", -+ symout[0], symout[1], symout[2], symout[3], -+ symout[4], symout[5], symout[6], symout[7]); -+ -+ dev_info(ksdev, "caam_sm_test: data buffers initialized\n"); -+#endif -+ -+ /* Load up clear keys */ -+ memcpy(clear_key_des, symkey, 8); -+ memcpy(clear_key_aes128, symkey, 16); -+ memcpy(clear_key_aes256, symkey, 32); -+ -+#ifdef SM_TEST_DETAIL -+ dev_info(ksdev, "caam_sm_test: all clear keys loaded\n"); -+#endif -+ -+ /* -+ * Place clear keys in keystore. -+ * All the interesting stuff happens here. -+ */ -+ /* 8 bit DES key */ -+ stat = sm_keystore_slot_alloc(ksdev, unit, 8, &keyslot_des); -+ if (stat) -+ goto freemem; -+#ifdef SM_TEST_DETAIL -+ dev_info(ksdev, "caam_sm_test: 8 byte key slot in %d\n", keyslot_des); -+#endif -+ stat = sm_keystore_slot_load(ksdev, unit, keyslot_des, clear_key_des, -+ 8); -+ if (stat) { -+#ifdef SM_TEST_DETAIL -+ dev_info(ksdev, "caam_sm_test: can't load 8 byte key in %d\n", -+ keyslot_des); -+#endif -+ sm_keystore_slot_dealloc(ksdev, unit, keyslot_des); -+ goto freemem; -+ } -+ -+ /* 16 bit AES key */ -+ stat = sm_keystore_slot_alloc(ksdev, unit, 16, &keyslot_aes128); -+ if (stat) { -+ sm_keystore_slot_dealloc(ksdev, unit, keyslot_des); -+ goto freemem; -+ } -+#ifdef SM_TEST_DETAIL -+ dev_info(ksdev, "caam_sm_test: 16 byte key slot in %d\n", -+ keyslot_aes128); -+#endif -+ stat = sm_keystore_slot_load(ksdev, unit, keyslot_aes128, -+ clear_key_aes128, 16); -+ if (stat) { -+#ifdef SM_TEST_DETAIL -+ dev_info(ksdev, "caam_sm_test: can't load 16 byte key in %d\n", -+ keyslot_aes128); -+#endif -+ sm_keystore_slot_dealloc(ksdev, unit, keyslot_aes128); -+ sm_keystore_slot_dealloc(ksdev, unit, keyslot_des); -+ goto freemem; -+ } -+ -+ /* 32 bit AES key */ -+ stat = sm_keystore_slot_alloc(ksdev, unit, 32, &keyslot_aes256); -+ if (stat) { -+ sm_keystore_slot_dealloc(ksdev, unit, keyslot_aes128); -+ sm_keystore_slot_dealloc(ksdev, unit, keyslot_des); -+ goto freemem; -+ } -+#ifdef SM_TEST_DETAIL -+ dev_info(ksdev, "caam_sm_test: 32 byte key slot in %d\n", -+ keyslot_aes256); -+#endif -+ stat = sm_keystore_slot_load(ksdev, unit, keyslot_aes256, -+ clear_key_aes256, 32); -+ if (stat) { -+#ifdef SM_TEST_DETAIL -+ dev_info(ksdev, "caam_sm_test: can't load 32 byte key in %d\n", -+ keyslot_aes128); -+#endif -+ sm_keystore_slot_dealloc(ksdev, unit, keyslot_aes256); -+ sm_keystore_slot_dealloc(ksdev, unit, keyslot_aes128); -+ sm_keystore_slot_dealloc(ksdev, unit, keyslot_des); -+ goto freemem; -+ } -+ -+ /* Encapsulate all keys as SM blobs */ -+ stat = sm_keystore_slot_encapsulate(ksdev, unit, keyslot_des, -+ keyslot_des, 8, skeymod, 8); -+ if (stat) { -+ dev_info(ksdev, "caam_sm_test: can't encapsulate DES key\n"); -+ goto freekeys; -+ } -+ -+ stat = sm_keystore_slot_encapsulate(ksdev, unit, keyslot_aes128, -+ keyslot_aes128, 16, skeymod, 8); -+ if (stat) { -+ dev_info(ksdev, "caam_sm_test: can't encapsulate AES128 key\n"); -+ goto freekeys; -+ } -+ -+ stat = sm_keystore_slot_encapsulate(ksdev, unit, keyslot_aes256, -+ keyslot_aes256, 32, skeymod, 8); -+ if (stat) { -+ dev_info(ksdev, "caam_sm_test: can't encapsulate AES256 key\n"); -+ goto freekeys; -+ } -+ -+ /* Now decapsulate as black key blobs */ -+ stat = sm_keystore_slot_decapsulate(ksdev, unit, keyslot_des, -+ keyslot_des, 8, skeymod, 8); -+ if (stat) { -+ dev_info(ksdev, "caam_sm_test: can't decapsulate DES key\n"); -+ goto freekeys; -+ } -+ -+ stat = sm_keystore_slot_decapsulate(ksdev, unit, keyslot_aes128, -+ keyslot_aes128, 16, skeymod, 8); -+ if (stat) { -+ dev_info(ksdev, "caam_sm_test: can't decapsulate AES128 key\n"); -+ goto freekeys; -+ } -+ -+ stat = sm_keystore_slot_decapsulate(ksdev, unit, keyslot_aes256, -+ keyslot_aes256, 32, skeymod, 8); -+ if (stat) { -+ dev_info(ksdev, "caam_sm_test: can't decapsulate AES128 key\n"); -+ goto freekeys; -+ } -+ -+ /* Extract 8/16/32 byte black keys */ -+ sm_keystore_slot_read(ksdev, unit, keyslot_des, 8, black_key_des); -+ sm_keystore_slot_read(ksdev, unit, keyslot_aes128, 16, -+ black_key_aes128); -+ sm_keystore_slot_read(ksdev, unit, keyslot_aes256, 32, -+ black_key_aes256); -+ -+#ifdef SM_TEST_DETAIL -+ dev_info(ksdev, "caam_sm_test: all black keys extracted\n"); -+#endif -+ -+ /* DES encrypt using 8 byte black key */ -+ black_key_des_dma = dma_map_single(ksdev, black_key_des, 8, -+ DMA_TO_DEVICE); -+ dma_sync_single_for_device(ksdev, black_key_des_dma, 8, DMA_TO_DEVICE); -+ syminp_dma = dma_map_single(ksdev, syminp, 256, DMA_TO_DEVICE); -+ dma_sync_single_for_device(ksdev, syminp_dma, 256, DMA_TO_DEVICE); -+ symint_dma = dma_map_single(ksdev, symint, 256, DMA_FROM_DEVICE); -+ -+ jdescsz = mk_job_desc(jdesc, black_key_des_dma, 8, syminp_dma, -+ symint_dma, 256, -+ OP_ALG_ENCRYPT | OP_ALG_ALGSEL_DES, 0); -+ -+#ifdef SM_TEST_DETAIL -+ dev_info(ksdev, "jobdesc:\n"); -+ dev_info(ksdev, "0x%08x\n", jdesc[0]); -+ dev_info(ksdev, "0x%08x\n", jdesc[1]); -+ dev_info(ksdev, "0x%08x\n", jdesc[2]); -+ dev_info(ksdev, "0x%08x\n", jdesc[3]); -+ dev_info(ksdev, "0x%08x\n", jdesc[4]); -+ dev_info(ksdev, "0x%08x\n", jdesc[5]); -+ dev_info(ksdev, "0x%08x\n", jdesc[6]); -+ dev_info(ksdev, "0x%08x\n", jdesc[7]); -+#endif -+ -+ jstat = exec_test_job(ksdev, jdesc); -+ -+ dma_sync_single_for_cpu(ksdev, symint_dma, 256, DMA_FROM_DEVICE); -+ dma_unmap_single(ksdev, symint_dma, 256, DMA_FROM_DEVICE); -+ dma_unmap_single(ksdev, syminp_dma, 256, DMA_TO_DEVICE); -+ dma_unmap_single(ksdev, black_key_des_dma, 8, DMA_TO_DEVICE); -+ -+#ifdef SM_TEST_DETAIL -+ dev_info(ksdev, "input block:\n"); -+ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \ -+ "0x%02x 0x%02x 0x%02x 0x%02x\n", -+ syminp[0], syminp[1], syminp[2], syminp[3], -+ syminp[4], syminp[5], syminp[6], syminp[7]); -+ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \ -+ "0x%02x 0x%02x 0x%02x 0x%02x\n", -+ syminp[8], syminp[9], syminp[10], syminp[11], -+ syminp[12], syminp[13], syminp[14], syminp[15]); -+ dev_info(ksdev, "intermediate block:\n"); -+ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \ -+ "0x%02x 0x%02x 0x%02x 0x%02x\n", -+ symint[0], symint[1], symint[2], symint[3], -+ symint[4], symint[5], symint[6], symint[7]); -+ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \ -+ "0x%02x 0x%02x 0x%02x 0x%02x\n", -+ symint[8], symint[9], symint[10], symint[11], -+ symint[12], symint[13], symint[14], symint[15]); -+ dev_info(ksdev, "caam_sm_test: encrypt cycle with 8 byte key\n"); -+#endif -+ -+ /* DES decrypt using 8 byte clear key */ -+ clear_key_des_dma = dma_map_single(ksdev, clear_key_des, 8, -+ DMA_TO_DEVICE); -+ dma_sync_single_for_device(ksdev, clear_key_des_dma, 8, DMA_TO_DEVICE); -+ symint_dma = dma_map_single(ksdev, symint, 256, DMA_TO_DEVICE); -+ dma_sync_single_for_device(ksdev, symint_dma, 256, DMA_TO_DEVICE); -+ symout_dma = dma_map_single(ksdev, symout, 256, DMA_FROM_DEVICE); -+ -+ jdescsz = mk_job_desc(jdesc, clear_key_des_dma, 8, symint_dma, -+ symout_dma, 256, -+ OP_ALG_DECRYPT | OP_ALG_ALGSEL_DES, 0); -+ -+#ifdef SM_TEST_DETAIL -+ dev_info(ksdev, "jobdesc:\n"); -+ dev_info(ksdev, "0x%08x\n", jdesc[0]); -+ dev_info(ksdev, "0x%08x\n", jdesc[1]); -+ dev_info(ksdev, "0x%08x\n", jdesc[2]); -+ dev_info(ksdev, "0x%08x\n", jdesc[3]); -+ dev_info(ksdev, "0x%08x\n", jdesc[4]); -+ dev_info(ksdev, "0x%08x\n", jdesc[5]); -+ dev_info(ksdev, "0x%08x\n", jdesc[6]); -+ dev_info(ksdev, "0x%08x\n", jdesc[7]); -+#endif -+ -+ jstat = exec_test_job(ksdev, jdesc); -+ -+ dma_sync_single_for_cpu(ksdev, symout_dma, 256, DMA_FROM_DEVICE); -+ dma_unmap_single(ksdev, symout_dma, 256, DMA_FROM_DEVICE); -+ dma_unmap_single(ksdev, symint_dma, 256, DMA_TO_DEVICE); -+ dma_unmap_single(ksdev, clear_key_des_dma, 8, DMA_TO_DEVICE); -+ -+#ifdef SM_TEST_DETAIL -+ dev_info(ksdev, "intermediate block:\n"); -+ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \ -+ "0x%02x 0x%02x 0x%02x 0x%02x\n", -+ symint[0], symint[1], symint[2], symint[3], -+ symint[4], symint[5], symint[6], symint[7]); -+ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \ -+ "0x%02x 0x%02x 0x%02x 0x%02x\n", -+ symint[8], symint[9], symint[10], symint[11], -+ symint[12], symint[13], symint[14], symint[15]); -+ dev_info(ksdev, "decrypted block:\n"); -+ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \ -+ "0x%02x 0x%02x 0x%02x 0x%02x\n", -+ symout[0], symout[1], symout[2], symout[3], -+ symout[4], symout[5], symout[6], symout[7]); -+ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \ -+ "0x%02x 0x%02x 0x%02x 0x%02x\n", -+ symout[8], symout[9], symout[10], symout[11], -+ symout[12], symout[13], symout[14], symout[15]); -+ dev_info(ksdev, "caam_sm_test: decrypt cycle with 8 byte key\n"); -+#endif -+ -+ /* Check result */ -+ if (memcmp(symout, syminp, 256)) { -+ dev_info(ksdev, "caam_sm_test: 8-byte key test mismatch\n"); -+ rtnval = -1; -+ goto freekeys; -+ } else -+ dev_info(ksdev, "caam_sm_test: 8-byte key test match OK\n"); -+ -+ /* AES-128 encrypt using 16 byte black key */ -+ black_key_aes128_dma = dma_map_single(ksdev, black_key_aes128, 16, -+ DMA_TO_DEVICE); -+ dma_sync_single_for_device(ksdev, black_key_aes128_dma, 16, -+ DMA_TO_DEVICE); -+ syminp_dma = dma_map_single(ksdev, syminp, 256, DMA_TO_DEVICE); -+ dma_sync_single_for_device(ksdev, syminp_dma, 256, DMA_TO_DEVICE); -+ symint_dma = dma_map_single(ksdev, symint, 256, DMA_FROM_DEVICE); -+ -+ jdescsz = mk_job_desc(jdesc, black_key_aes128_dma, 16, syminp_dma, -+ symint_dma, 256, -+ OP_ALG_ENCRYPT | OP_ALG_ALGSEL_AES, 0); -+ -+#ifdef SM_TEST_DETAIL -+ dev_info(ksdev, "jobdesc:\n"); -+ dev_info(ksdev, "0x%08x\n", jdesc[0]); -+ dev_info(ksdev, "0x%08x\n", jdesc[1]); -+ dev_info(ksdev, "0x%08x\n", jdesc[2]); -+ dev_info(ksdev, "0x%08x\n", jdesc[3]); -+ dev_info(ksdev, "0x%08x\n", jdesc[4]); -+ dev_info(ksdev, "0x%08x\n", jdesc[5]); -+ dev_info(ksdev, "0x%08x\n", jdesc[6]); -+ dev_info(ksdev, "0x%08x\n", jdesc[7]); -+#endif -+ -+ jstat = exec_test_job(ksdev, jdesc); -+ -+ dma_sync_single_for_cpu(ksdev, symint_dma, 256, DMA_FROM_DEVICE); -+ dma_unmap_single(ksdev, symint_dma, 256, DMA_FROM_DEVICE); -+ dma_unmap_single(ksdev, syminp_dma, 256, DMA_TO_DEVICE); -+ dma_unmap_single(ksdev, black_key_aes128_dma, 16, DMA_TO_DEVICE); -+ -+#ifdef SM_TEST_DETAIL -+ dev_info(ksdev, "input block:\n"); -+ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \ -+ "0x%02x 0x%02x 0x%02x 0x%02x\n", -+ syminp[0], syminp[1], syminp[2], syminp[3], -+ syminp[4], syminp[5], syminp[6], syminp[7]); -+ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \ -+ "0x%02x 0x%02x 0x%02x 0x%02x\n", -+ syminp[8], syminp[9], syminp[10], syminp[11], -+ syminp[12], syminp[13], syminp[14], syminp[15]); -+ dev_info(ksdev, "intermediate block:\n"); -+ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \ -+ "0x%02x 0x%02x 0x%02x 0x%02x\n", -+ symint[0], symint[1], symint[2], symint[3], -+ symint[4], symint[5], symint[6], symint[7]); -+ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \ -+ "0x%02x 0x%02x 0x%02x 0x%02x\n", -+ symint[8], symint[9], symint[10], symint[11], -+ symint[12], symint[13], symint[14], symint[15]); -+ dev_info(ksdev, "caam_sm_test: encrypt cycle with 16 byte key\n"); -+#endif -+ -+ /* AES-128 decrypt using 16 byte clear key */ -+ clear_key_aes128_dma = dma_map_single(ksdev, clear_key_aes128, 16, -+ DMA_TO_DEVICE); -+ dma_sync_single_for_device(ksdev, clear_key_aes128_dma, 16, -+ DMA_TO_DEVICE); -+ symint_dma = dma_map_single(ksdev, symint, 256, DMA_TO_DEVICE); -+ dma_sync_single_for_device(ksdev, symint_dma, 256, DMA_TO_DEVICE); -+ symout_dma = dma_map_single(ksdev, symout, 256, DMA_FROM_DEVICE); -+ -+ jdescsz = mk_job_desc(jdesc, clear_key_aes128_dma, 16, symint_dma, -+ symout_dma, 256, -+ OP_ALG_DECRYPT | OP_ALG_ALGSEL_AES, 0); -+ -+#ifdef SM_TEST_DETAIL -+ dev_info(ksdev, "jobdesc:\n"); -+ dev_info(ksdev, "0x%08x\n", jdesc[0]); -+ dev_info(ksdev, "0x%08x\n", jdesc[1]); -+ dev_info(ksdev, "0x%08x\n", jdesc[2]); -+ dev_info(ksdev, "0x%08x\n", jdesc[3]); -+ dev_info(ksdev, "0x%08x\n", jdesc[4]); -+ dev_info(ksdev, "0x%08x\n", jdesc[5]); -+ dev_info(ksdev, "0x%08x\n", jdesc[6]); -+ dev_info(ksdev, "0x%08x\n", jdesc[7]); -+#endif -+ jstat = exec_test_job(ksdev, jdesc); -+ -+ dma_sync_single_for_cpu(ksdev, symout_dma, 256, DMA_FROM_DEVICE); -+ dma_unmap_single(ksdev, symout_dma, 256, DMA_FROM_DEVICE); -+ dma_unmap_single(ksdev, symint_dma, 256, DMA_TO_DEVICE); -+ dma_unmap_single(ksdev, clear_key_aes128_dma, 16, DMA_TO_DEVICE); -+ -+#ifdef SM_TEST_DETAIL -+ dev_info(ksdev, "intermediate block:\n"); -+ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \ -+ "0x%02x 0x%02x 0x%02x 0x%02x\n", -+ symint[0], symint[1], symint[2], symint[3], -+ symint[4], symint[5], symint[6], symint[7]); -+ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \ -+ "0x%02x 0x%02x 0x%02x 0x%02x\n", -+ symint[8], symint[9], symint[10], symint[11], -+ symint[12], symint[13], symint[14], symint[15]); -+ dev_info(ksdev, "decrypted block:\n"); -+ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \ -+ "0x%02x 0x%02x 0x%02x 0x%02x\n", -+ symout[0], symout[1], symout[2], symout[3], -+ symout[4], symout[5], symout[6], symout[7]); -+ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \ -+ "0x%02x 0x%02x 0x%02x 0x%02x\n", -+ symout[8], symout[9], symout[10], symout[11], -+ symout[12], symout[13], symout[14], symout[15]); -+ dev_info(ksdev, "caam_sm_test: decrypt cycle with 16 byte key\n"); -+#endif -+ -+ /* Check result */ -+ if (memcmp(symout, syminp, 256)) { -+ dev_info(ksdev, "caam_sm_test: 16-byte key test mismatch\n"); -+ rtnval = -1; -+ goto freekeys; -+ } else -+ dev_info(ksdev, "caam_sm_test: 16-byte key test match OK\n"); -+ -+ /* AES-256 encrypt using 32 byte black key */ -+ black_key_aes256_dma = dma_map_single(ksdev, black_key_aes256, 32, -+ DMA_TO_DEVICE); -+ dma_sync_single_for_device(ksdev, black_key_aes256_dma, 32, -+ DMA_TO_DEVICE); -+ syminp_dma = dma_map_single(ksdev, syminp, 256, DMA_TO_DEVICE); -+ dma_sync_single_for_device(ksdev, syminp_dma, 256, DMA_TO_DEVICE); -+ symint_dma = dma_map_single(ksdev, symint, 256, DMA_FROM_DEVICE); -+ -+ jdescsz = mk_job_desc(jdesc, black_key_aes256_dma, 32, syminp_dma, -+ symint_dma, 256, -+ OP_ALG_ENCRYPT | OP_ALG_ALGSEL_AES, 0); -+ -+#ifdef SM_TEST_DETAIL -+ dev_info(ksdev, "jobdesc:\n"); -+ dev_info(ksdev, "0x%08x\n", jdesc[0]); -+ dev_info(ksdev, "0x%08x\n", jdesc[1]); -+ dev_info(ksdev, "0x%08x\n", jdesc[2]); -+ dev_info(ksdev, "0x%08x\n", jdesc[3]); -+ dev_info(ksdev, "0x%08x\n", jdesc[4]); -+ dev_info(ksdev, "0x%08x\n", jdesc[5]); -+ dev_info(ksdev, "0x%08x\n", jdesc[6]); -+ dev_info(ksdev, "0x%08x\n", jdesc[7]); -+#endif -+ -+ jstat = exec_test_job(ksdev, jdesc); -+ -+ dma_sync_single_for_cpu(ksdev, symint_dma, 256, DMA_FROM_DEVICE); -+ dma_unmap_single(ksdev, symint_dma, 256, DMA_FROM_DEVICE); -+ dma_unmap_single(ksdev, syminp_dma, 256, DMA_TO_DEVICE); -+ dma_unmap_single(ksdev, black_key_aes256_dma, 32, DMA_TO_DEVICE); -+ -+#ifdef SM_TEST_DETAIL -+ dev_info(ksdev, "input block:\n"); -+ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \ -+ "0x%02x 0x%02x 0x%02x 0x%02x\n", -+ syminp[0], syminp[1], syminp[2], syminp[3], -+ syminp[4], syminp[5], syminp[6], syminp[7]); -+ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \ -+ "0x%02x 0x%02x 0x%02x 0x%02x\n", -+ syminp[8], syminp[9], syminp[10], syminp[11], -+ syminp[12], syminp[13], syminp[14], syminp[15]); -+ dev_info(ksdev, "intermediate block:\n"); -+ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \ -+ "0x%02x 0x%02x 0x%02x 0x%02x\n", -+ symint[0], symint[1], symint[2], symint[3], -+ symint[4], symint[5], symint[6], symint[7]); -+ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \ -+ "0x%02x 0x%02x 0x%02x 0x%02x\n", -+ symint[8], symint[9], symint[10], symint[11], -+ symint[12], symint[13], symint[14], symint[15]); -+ dev_info(ksdev, "caam_sm_test: encrypt cycle with 32 byte key\n"); -+#endif -+ -+ /* AES-256 decrypt using 32-byte black key */ -+ clear_key_aes256_dma = dma_map_single(ksdev, clear_key_aes256, 32, -+ DMA_TO_DEVICE); -+ dma_sync_single_for_device(ksdev, clear_key_aes256_dma, 32, -+ DMA_TO_DEVICE); -+ symint_dma = dma_map_single(ksdev, symint, 256, DMA_TO_DEVICE); -+ dma_sync_single_for_device(ksdev, symint_dma, 256, DMA_TO_DEVICE); -+ symout_dma = dma_map_single(ksdev, symout, 256, DMA_FROM_DEVICE); -+ -+ jdescsz = mk_job_desc(jdesc, clear_key_aes256_dma, 32, symint_dma, -+ symout_dma, 256, -+ OP_ALG_DECRYPT | OP_ALG_ALGSEL_AES, 0); -+ -+#ifdef SM_TEST_DETAIL -+ dev_info(ksdev, "jobdesc:\n"); -+ dev_info(ksdev, "0x%08x\n", jdesc[0]); -+ dev_info(ksdev, "0x%08x\n", jdesc[1]); -+ dev_info(ksdev, "0x%08x\n", jdesc[2]); -+ dev_info(ksdev, "0x%08x\n", jdesc[3]); -+ dev_info(ksdev, "0x%08x\n", jdesc[4]); -+ dev_info(ksdev, "0x%08x\n", jdesc[5]); -+ dev_info(ksdev, "0x%08x\n", jdesc[6]); -+ dev_info(ksdev, "0x%08x\n", jdesc[7]); -+#endif -+ -+ jstat = exec_test_job(ksdev, jdesc); -+ -+ dma_sync_single_for_cpu(ksdev, symout_dma, 256, DMA_FROM_DEVICE); -+ dma_unmap_single(ksdev, symout_dma, 256, DMA_FROM_DEVICE); -+ dma_unmap_single(ksdev, symint_dma, 256, DMA_TO_DEVICE); -+ dma_unmap_single(ksdev, clear_key_aes256_dma, 32, DMA_TO_DEVICE); -+ -+#ifdef SM_TEST_DETAIL -+ dev_info(ksdev, "intermediate block:\n"); -+ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \ -+ "0x%02x 0x%02x 0x%02x 0x%02x\n", -+ symint[0], symint[1], symint[2], symint[3], -+ symint[4], symint[5], symint[6], symint[7]); -+ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \ -+ "0x%02x 0x%02x 0x%02x 0x%02x\n", -+ symint[8], symint[9], symint[10], symint[11], -+ symint[12], symint[13], symint[14], symint[15]); -+ dev_info(ksdev, "decrypted block:\n"); -+ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \ -+ "0x%02x 0x%02x 0x%02x 0x%02x\n", -+ symout[0], symout[1], symout[2], symout[3], -+ symout[4], symout[5], symout[6], symout[7]); -+ dev_info(ksdev, "0x%02x 0x%02x 0x%02x 0x%02x " \ -+ "0x%02x 0x%02x 0x%02x 0x%02x\n", -+ symout[8], symout[9], symout[10], symout[11], -+ symout[12], symout[13], symout[14], symout[15]); -+ dev_info(ksdev, "caam_sm_test: decrypt cycle with 32 byte key\n"); -+#endif -+ -+ /* Check result */ -+ if (memcmp(symout, syminp, 256)) { -+ dev_info(ksdev, "caam_sm_test: 32-byte key test mismatch\n"); -+ rtnval = -1; -+ goto freekeys; -+ } else -+ dev_info(ksdev, "caam_sm_test: 32-byte key test match OK\n"); -+ -+ -+ /* Remove 8/16/32 byte keys from keystore */ -+freekeys: -+ stat = sm_keystore_slot_dealloc(ksdev, unit, keyslot_des); -+ if (stat) -+ dev_info(ksdev, "caam_sm_test: can't release slot %d\n", -+ keyslot_des); -+ -+ stat = sm_keystore_slot_dealloc(ksdev, unit, keyslot_aes128); -+ if (stat) -+ dev_info(ksdev, "caam_sm_test: can't release slot %d\n", -+ keyslot_aes128); -+ -+ stat = sm_keystore_slot_dealloc(ksdev, unit, keyslot_aes256); -+ if (stat) -+ dev_info(ksdev, "caam_sm_test: can't release slot %d\n", -+ keyslot_aes256); -+ -+ -+ /* Free resources */ -+freemem: -+#ifdef SM_TEST_DETAIL -+ dev_info(ksdev, "caam_sm_test: cleaning up\n"); -+#endif -+ kfree(syminp); -+ kfree(symint); -+ kfree(symout); -+ kfree(clear_key_des); -+ kfree(clear_key_aes128); -+ kfree(clear_key_aes256); -+ kfree(black_key_des); -+ kfree(black_key_aes128); -+ kfree(black_key_aes256); -+ kfree(jdesc); -+ -+ /* Disconnect from keystore and leave */ -+ sm_release_keystore(ksdev, unit); -+ -+ return rtnval; -+} -+EXPORT_SYMBOL(caam_sm_example_init); -+ -+void caam_sm_example_shutdown(void) -+{ -+ /* unused in present version */ -+ struct device_node *dev_node; -+ struct platform_device *pdev; -+ -+ /* -+ * Do of_find_compatible_node() then of_find_device_by_node() -+ * once a functional device tree is available -+ */ -+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); -+ if (!dev_node) { -+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0"); -+ if (!dev_node) -+ return; -+ } -+ -+ pdev = of_find_device_by_node(dev_node); -+ if (!pdev) -+ return; -+ -+ of_node_get(dev_node); -+ -+} -+ -+static int __init caam_sm_test_init(void) -+{ -+ struct device_node *dev_node; -+ struct platform_device *pdev; -+ -+ /* -+ * Do of_find_compatible_node() then of_find_device_by_node() -+ * once a functional device tree is available -+ */ -+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0"); -+ if (!dev_node) { -+ dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec4.0"); -+ if (!dev_node) -+ return -ENODEV; -+ } -+ -+ pdev = of_find_device_by_node(dev_node); -+ if (!pdev) -+ return -ENODEV; -+ -+ of_node_put(dev_node); -+ -+ caam_sm_example_init(pdev); -+ -+ return 0; -+} -+ -+ -+/* Module-based initialization needs to wait for dev tree */ -+#ifdef CONFIG_OF -+module_init(caam_sm_test_init); -+module_exit(caam_sm_example_shutdown); -+ -+MODULE_LICENSE("Dual BSD/GPL"); -+MODULE_DESCRIPTION("FSL CAAM Keystore Usage Example"); -+MODULE_AUTHOR("Freescale Semiconductor - NMSG/MAD"); -+#endif -diff -Nur linux-4.1.13.orig/drivers/crypto/caam/snvsregs.h linux-4.1.13/drivers/crypto/caam/snvsregs.h ---- linux-4.1.13.orig/drivers/crypto/caam/snvsregs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/crypto/caam/snvsregs.h 2015-11-30 17:56:13.552139590 +0100 -@@ -0,0 +1,237 @@ -+/* -+ * SNVS hardware register-level view -+ * -+ * Copyright (C) 2012-2014 Freescale Semiconductor, Inc., All Rights Reserved -+ */ -+ -+#ifndef SNVSREGS_H -+#define SNVSREGS_H -+ -+#include -+#include -+ -+/* -+ * SNVS High Power Domain -+ * Includes security violations, HA counter, RTC, alarm -+ */ -+struct snvs_hp { -+ u32 lock; /* HPLR - HP Lock */ -+ u32 cmd; /* HPCOMR - HP Command */ -+ u32 ctl; /* HPCR - HP Control */ -+ u32 secvio_intcfg; /* HPSICR - Security Violation Int Config */ -+ u32 secvio_ctl; /* HPSVCR - Security Violation Control */ -+ u32 status; /* HPSR - HP Status */ -+ u32 secvio_status; /* HPSVSR - Security Violation Status */ -+ u32 ha_counteriv; /* High Assurance Counter IV */ -+ u32 ha_counter; /* High Assurance Counter */ -+ u32 rtc_msb; /* Real Time Clock/Counter MSB */ -+ u32 rtc_lsb; /* Real Time Counter LSB */ -+ u32 time_alarm_msb; /* Time Alarm MSB */ -+ u32 time_alarm_lsb; /* Time Alarm LSB */ -+}; -+ -+#define HP_LOCK_HAC_LCK 0x00040000 -+#define HP_LOCK_HPSICR_LCK 0x00020000 -+#define HP_LOCK_HPSVCR_LCK 0x00010000 -+#define HP_LOCK_MKEYSEL_LCK 0x00000200 -+#define HP_LOCK_TAMPCFG_LCK 0x00000100 -+#define HP_LOCK_TAMPFLT_LCK 0x00000080 -+#define HP_LOCK_SECVIO_LCK 0x00000040 -+#define HP_LOCK_GENP_LCK 0x00000020 -+#define HP_LOCK_MONOCTR_LCK 0x00000010 -+#define HP_LOCK_CALIB_LCK 0x00000008 -+#define HP_LOCK_SRTC_LCK 0x00000004 -+#define HP_LOCK_ZMK_RD_LCK 0x00000002 -+#define HP_LOCK_ZMK_WT_LCK 0x00000001 -+ -+#define HP_CMD_NONPRIV_AXS 0x80000000 -+#define HP_CMD_HAC_STOP 0x00080000 -+#define HP_CMD_HAC_CLEAR 0x00040000 -+#define HP_CMD_HAC_LOAD 0x00020000 -+#define HP_CMD_HAC_CFG_EN 0x00010000 -+#define HP_CMD_SNVS_MSTR_KEY 0x00002000 -+#define HP_CMD_PROG_ZMK 0x00001000 -+#define HP_CMD_SW_LPSV 0x00000400 -+#define HP_CMD_SW_FSV 0x00000200 -+#define HP_CMD_SW_SV 0x00000100 -+#define HP_CMD_LP_SWR_DIS 0x00000020 -+#define HP_CMD_LP_SWR 0x00000010 -+#define HP_CMD_SSM_SFNS_DIS 0x00000004 -+#define HP_CMD_SSM_ST_DIS 0x00000002 -+#define HP_CMD_SMM_ST 0x00000001 -+ -+#define HP_CTL_TIME_SYNC 0x00010000 -+#define HP_CTL_CAL_VAL_SHIFT 10 -+#define HP_CTL_CAL_VAL_MASK (0x1f << HP_CTL_CALIB_SHIFT) -+#define HP_CTL_CALIB_EN 0x00000100 -+#define HP_CTL_PI_FREQ_SHIFT 4 -+#define HP_CTL_PI_FREQ_MASK (0xf << HP_CTL_PI_FREQ_SHIFT) -+#define HP_CTL_PI_EN 0x00000008 -+#define HP_CTL_TIMEALARM_EN 0x00000002 -+#define HP_CTL_RTC_EN 0x00000001 -+ -+#define HP_SECVIO_INTEN_EN 0x10000000 -+#define HP_SECVIO_INTEN_SRC5 0x00000020 -+#define HP_SECVIO_INTEN_SRC4 0x00000010 -+#define HP_SECVIO_INTEN_SRC3 0x00000008 -+#define HP_SECVIO_INTEN_SRC2 0x00000004 -+#define HP_SECVIO_INTEN_SRC1 0x00000002 -+#define HP_SECVIO_INTEN_SRC0 0x00000001 -+#define HP_SECVIO_INTEN_ALL 0x8000003f -+ -+#define HP_SECVIO_ICTL_CFG_SHIFT 30 -+#define HP_SECVIO_ICTL_CFG_MASK (0x3 << HP_SECVIO_ICTL_CFG_SHIFT) -+#define HP_SECVIO_ICTL_CFG5_SHIFT 5 -+#define HP_SECVIO_ICTL_CFG5_MASK (0x3 << HP_SECVIO_ICTL_CFG5_SHIFT) -+#define HP_SECVIO_ICTL_CFG_DISABLE 0 -+#define HP_SECVIO_ICTL_CFG_NONFATAL 1 -+#define HP_SECVIO_ICTL_CFG_FATAL 2 -+#define HP_SECVIO_ICTL_CFG4_FATAL 0x00000010 -+#define HP_SECVIO_ICTL_CFG3_FATAL 0x00000008 -+#define HP_SECVIO_ICTL_CFG2_FATAL 0x00000004 -+#define HP_SECVIO_ICTL_CFG1_FATAL 0x00000002 -+#define HP_SECVIO_ICTL_CFG0_FATAL 0x00000001 -+ -+#define HP_STATUS_ZMK_ZERO 0x80000000 -+#define HP_STATUS_OTPMK_ZERO 0x08000000 -+#define HP_STATUS_OTPMK_SYN_SHIFT 16 -+#define HP_STATUS_OTPMK_SYN_MASK (0x1ff << HP_STATUS_OTPMK_SYN_SHIFT) -+#define HP_STATUS_SSM_ST_SHIFT 8 -+#define HP_STATUS_SSM_ST_MASK (0xf << HP_STATUS_SSM_ST_SHIFT) -+#define HP_STATUS_SSM_ST_INIT 0 -+#define HP_STATUS_SSM_ST_HARDFAIL 1 -+#define HP_STATUS_SSM_ST_SOFTFAIL 3 -+#define HP_STATUS_SSM_ST_INITINT 8 -+#define HP_STATUS_SSM_ST_CHECK 9 -+#define HP_STATUS_SSM_ST_NONSECURE 11 -+#define HP_STATUS_SSM_ST_TRUSTED 13 -+#define HP_STATUS_SSM_ST_SECURE 15 -+ -+#define HP_SECVIOST_ZMK_ECC_FAIL 0x08000000 /* write to clear */ -+#define HP_SECVIOST_ZMK_SYN_SHIFT 16 -+#define HP_SECVIOST_ZMK_SYN_MASK (0x1ff << HP_SECVIOST_ZMK_SYN_SHIFT) -+#define HP_SECVIOST_SECVIO5 0x00000020 -+#define HP_SECVIOST_SECVIO4 0x00000010 -+#define HP_SECVIOST_SECVIO3 0x00000008 -+#define HP_SECVIOST_SECVIO2 0x00000004 -+#define HP_SECVIOST_SECVIO1 0x00000002 -+#define HP_SECVIOST_SECVIO0 0x00000001 -+#define HP_SECVIOST_SECVIOMASK 0x0000003f -+ -+/* -+ * SNVS Low Power Domain -+ * Includes glitch detector, SRTC, alarm, monotonic counter, ZMK -+ */ -+struct snvs_lp { -+ u32 lock; -+ u32 ctl; -+ u32 mstr_key_ctl; /* Master Key Control */ -+ u32 secvio_ctl; /* Security Violation Control */ -+ u32 tamper_filt_cfg; /* Tamper Glitch Filters Configuration */ -+ u32 tamper_det_cfg; /* Tamper Detectors Configuration */ -+ u32 status; -+ u32 srtc_msb; /* Secure Real Time Clock/Counter MSB */ -+ u32 srtc_lsb; /* Secure Real Time Clock/Counter LSB */ -+ u32 time_alarm; /* Time Alarm */ -+ u32 smc_msb; /* Secure Monotonic Counter MSB */ -+ u32 smc_lsb; /* Secure Monotonic Counter LSB */ -+ u32 pwr_glitch_det; /* Power Glitch Detector */ -+ u32 gen_purpose; -+ u32 zmk[8]; /* Zeroizable Master Key */ -+}; -+ -+#define LP_LOCK_MKEYSEL_LCK 0x00000200 -+#define LP_LOCK_TAMPDET_LCK 0x00000100 -+#define LP_LOCK_TAMPFLT_LCK 0x00000080 -+#define LP_LOCK_SECVIO_LCK 0x00000040 -+#define LP_LOCK_GENP_LCK 0x00000020 -+#define LP_LOCK_MONOCTR_LCK 0x00000010 -+#define LP_LOCK_CALIB_LCK 0x00000008 -+#define LP_LOCK_SRTC_LCK 0x00000004 -+#define LP_LOCK_ZMK_RD_LCK 0x00000002 -+#define LP_LOCK_ZMK_WT_LCK 0x00000001 -+ -+#define LP_CTL_CAL_VAL_SHIFT 10 -+#define LP_CTL_CAL_VAL_MASK (0x1f << LP_CTL_CAL_VAL_SHIFT) -+#define LP_CTL_CALIB_EN 0x00000100 -+#define LP_CTL_SRTC_INVAL_EN 0x00000010 -+#define LP_CTL_WAKE_INT_EN 0x00000008 -+#define LP_CTL_MONOCTR_EN 0x00000004 -+#define LP_CTL_TIMEALARM_EN 0x00000002 -+#define LP_CTL_SRTC_EN 0x00000001 -+ -+#define LP_MKEYCTL_ZMKECC_SHIFT 8 -+#define LP_MKEYCTL_ZMKECC_MASK (0xff << LP_MKEYCTL_ZMKECC_SHIFT) -+#define LP_MKEYCTL_ZMKECC_EN 0x00000010 -+#define LP_MKEYCTL_ZMKECC_VAL 0x00000008 -+#define LP_MKEYCTL_ZMKECC_PROG 0x00000004 -+#define LP_MKEYCTL_MKSEL_SHIFT 0 -+#define LP_MKEYCTL_MKSEL_MASK (3 << LP_MKEYCTL_MKSEL_SHIFT) -+#define LP_MKEYCTL_MK_OTP 0 -+#define LP_MKEYCTL_MK_ZMK 2 -+#define LP_MKEYCTL_MK_COMB 3 -+ -+#define LP_SECVIO_CTL_SRC5 0x20 -+#define LP_SECVIO_CTL_SRC4 0x10 -+#define LP_SECVIO_CTL_SRC3 0x08 -+#define LP_SECVIO_CTL_SRC2 0x04 -+#define LP_SECVIO_CTL_SRC1 0x02 -+#define LP_SECVIO_CTL_SRC0 0x01 -+ -+#define LP_TAMPFILT_EXT2_EN 0x80000000 -+#define LP_TAMPFILT_EXT2_SHIFT 24 -+#define LP_TAMPFILT_EXT2_MASK (0x1f << LP_TAMPFILT_EXT2_SHIFT) -+#define LP_TAMPFILT_EXT1_EN 0x00800000 -+#define LP_TAMPFILT_EXT1_SHIFT 16 -+#define LP_TAMPFILT_EXT1_MASK (0x1f << LP_TAMPFILT_EXT1_SHIFT) -+#define LP_TAMPFILT_WM_EN 0x00000080 -+#define LP_TAMPFILT_WM_SHIFT 0 -+#define LP_TAMPFILT_WM_MASK (0x1f << LP_TAMPFILT_WM_SHIFT) -+ -+#define LP_TAMPDET_OSC_BPS 0x10000000 -+#define LP_TAMPDET_VRC_SHIFT 24 -+#define LP_TAMPDET_VRC_MASK (3 << LP_TAMPFILT_VRC_SHIFT) -+#define LP_TAMPDET_HTDC_SHIFT 20 -+#define LP_TAMPDET_HTDC_MASK (3 << LP_TAMPFILT_HTDC_SHIFT) -+#define LP_TAMPDET_LTDC_SHIFT 16 -+#define LP_TAMPDET_LTDC_MASK (3 << LP_TAMPFILT_LTDC_SHIFT) -+#define LP_TAMPDET_POR_OBS 0x00008000 -+#define LP_TAMPDET_PFD_OBS 0x00004000 -+#define LP_TAMPDET_ET2_EN 0x00000400 -+#define LP_TAMPDET_ET1_EN 0x00000200 -+#define LP_TAMPDET_WMT2_EN 0x00000100 -+#define LP_TAMPDET_WMT1_EN 0x00000080 -+#define LP_TAMPDET_VT_EN 0x00000040 -+#define LP_TAMPDET_TT_EN 0x00000020 -+#define LP_TAMPDET_CT_EN 0x00000010 -+#define LP_TAMPDET_MCR_EN 0x00000004 -+#define LP_TAMPDET_SRTCR_EN 0x00000002 -+ -+#define LP_STATUS_SECURE -+#define LP_STATUS_NONSECURE -+#define LP_STATUS_SCANEXIT 0x00100000 /* all write 1 clear here on */ -+#define LP_STATUS_EXT_SECVIO 0x00010000 -+#define LP_STATUS_ET2 0x00000400 -+#define LP_STATUS_ET1 0x00000200 -+#define LP_STATUS_WMT2 0x00000100 -+#define LP_STATUS_WMT1 0x00000080 -+#define LP_STATUS_VTD 0x00000040 -+#define LP_STATUS_TTD 0x00000020 -+#define LP_STATUS_CTD 0x00000010 -+#define LP_STATUS_PGD 0x00000008 -+#define LP_STATUS_MCR 0x00000004 -+#define LP_STATUS_SRTCR 0x00000002 -+#define LP_STATUS_LPTA 0x00000001 -+ -+/* Full SNVS register page, including version/options */ -+struct snvs_full { -+ struct snvs_hp hp; -+ struct snvs_lp lp; -+ u32 rsvd[731]; /* deadspace 0x08c-0xbf7 */ -+ -+ /* Version / Revision / Option ID space - end of register page */ -+ u32 vid; /* 0xbf8 HP Version ID (VID 1) */ -+ u32 opt_rev; /* 0xbfc HP Options / Revision (VID 2) */ -+}; -+ -+#endif /* SNVSREGS_H */ -diff -Nur linux-4.1.13.orig/drivers/dma/imx-sdma.c linux-4.1.13/drivers/dma/imx-sdma.c ---- linux-4.1.13.orig/drivers/dma/imx-sdma.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/dma/imx-sdma.c 2015-11-30 17:56:13.552139590 +0100 -@@ -29,6 +29,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -232,6 +233,14 @@ - - struct sdma_engine; - -+enum sdma_mode { -+ SDMA_MODE_INVALID = 0, -+ SDMA_MODE_LOOP, -+ SDMA_MODE_NORMAL, -+ SDMA_MODE_P2P, -+ SDMA_MODE_NO_BD, -+}; -+ - /** - * struct sdma_channel - housekeeping for a SDMA channel - * -@@ -244,6 +253,7 @@ - * @word_size peripheral access size - * @buf_tail ID of the buffer that was processed - * @num_bd max NUM_BD. number of descriptors currently handling -+ * @bd_iram flag indicating the memory location of buffer descriptor - */ - struct sdma_channel { - struct sdma_engine *sdma; -@@ -258,12 +268,16 @@ - unsigned int period_len; - struct sdma_buffer_descriptor *bd; - dma_addr_t bd_phys; -+ bool bd_iram; - unsigned int pc_from_device, pc_to_device; -- unsigned long flags; -- dma_addr_t per_address; -+ unsigned int device_to_device; -+ unsigned int other_script; -+ enum sdma_mode mode; -+ dma_addr_t per_address, per_address2; - unsigned long event_mask[2]; - unsigned long watermark_level; - u32 shp_addr, per_addr; -+ u32 data_addr1, data_addr2; - struct dma_chan chan; - spinlock_t lock; - struct dma_async_tx_descriptor desc; -@@ -271,11 +285,8 @@ - unsigned int chn_count; - unsigned int chn_real_count; - struct tasklet_struct tasklet; -- struct imx_dma_data data; - }; - --#define IMX_DMA_SG_LOOP BIT(0) -- - #define MAX_DMA_CHANNELS 32 - #define MXC_SDMA_DEFAULT_PRIORITY 1 - #define MXC_SDMA_MIN_PRIORITY 1 -@@ -327,6 +338,7 @@ - spinlock_t channel_0_lock; - u32 script_number; - struct sdma_script_start_addrs *script_addrs; -+ struct gen_pool *iram_pool; - const struct sdma_driver_data *drvdata; - }; - -@@ -546,12 +558,14 @@ - dma_addr_t buf_phys; - int ret; - unsigned long flags; -+ bool use_iram = true; - -- buf_virt = dma_alloc_coherent(NULL, -- size, -- &buf_phys, GFP_KERNEL); -+ buf_virt = gen_pool_dma_alloc(sdma->iram_pool, size, &buf_phys); - if (!buf_virt) { -- return -ENOMEM; -+ use_iram = false; -+ buf_virt = dma_alloc_coherent(NULL, size, &buf_phys, GFP_KERNEL); -+ if (!buf_virt) -+ return -ENOMEM; - } - - spin_lock_irqsave(&sdma->channel_0_lock, flags); -@@ -568,7 +582,10 @@ - - spin_unlock_irqrestore(&sdma->channel_0_lock, flags); - -- dma_free_coherent(NULL, size, buf_virt, buf_phys); -+ if (use_iram) -+ gen_pool_free(sdma->iram_pool, (unsigned long)buf_virt, size); -+ else -+ dma_free_coherent(NULL, size, buf_virt, buf_phys); - - return ret; - } -@@ -654,14 +671,31 @@ - sdmac->desc.callback(sdmac->desc.callback_param); - } - -+static void sdma_handle_other_intr(struct sdma_channel *sdmac) -+{ -+ if (sdmac->desc.callback) -+ sdmac->desc.callback(sdmac->desc.callback_param); -+} -+ - static void sdma_tasklet(unsigned long data) - { - struct sdma_channel *sdmac = (struct sdma_channel *) data; -+ struct sdma_engine *sdma = sdmac->sdma; - -- if (sdmac->flags & IMX_DMA_SG_LOOP) -+ switch (sdmac->mode) { -+ case SDMA_MODE_LOOP: - sdma_handle_channel_loop(sdmac); -- else -+ break; -+ case SDMA_MODE_NORMAL: - mxc_sdma_handle_channel_normal(sdmac); -+ break; -+ case SDMA_MODE_NO_BD: -+ sdma_handle_other_intr(sdmac); -+ break; -+ default: -+ dev_err(sdma->dev, "invalid SDMA MODE!\n"); -+ break; -+ } - } - - static irqreturn_t sdma_int_handler(int irq, void *dev_id) -@@ -678,7 +712,7 @@ - int channel = fls(stat) - 1; - struct sdma_channel *sdmac = &sdma->channel[channel]; - -- if (sdmac->flags & IMX_DMA_SG_LOOP) -+ if (sdmac->mode & SDMA_MODE_LOOP) - sdma_update_channel_loop(sdmac); - - tasklet_schedule(&sdmac->tasklet); -@@ -702,9 +736,12 @@ - * two peripherals or memory-to-memory transfers - */ - int per_2_per = 0, emi_2_emi = 0; -+ int other = 0; - - sdmac->pc_from_device = 0; - sdmac->pc_to_device = 0; -+ sdmac->device_to_device = 0; -+ sdmac->other_script = 0; - - switch (peripheral_type) { - case IMX_DMATYPE_MEMORY: -@@ -733,7 +770,6 @@ - case IMX_DMATYPE_CSPI: - case IMX_DMATYPE_EXT: - case IMX_DMATYPE_SSI: -- case IMX_DMATYPE_SAI: - per_2_emi = sdma->script_addrs->app_2_mcu_addr; - emi_2_per = sdma->script_addrs->mcu_2_app_addr; - break; -@@ -751,11 +787,6 @@ - emi_2_per = sdma->script_addrs->mcu_2_shp_addr; - break; - case IMX_DMATYPE_ASRC: -- per_2_emi = sdma->script_addrs->asrc_2_mcu_addr; -- emi_2_per = sdma->script_addrs->asrc_2_mcu_addr; -- per_2_per = sdma->script_addrs->per_2_per_addr; -- break; -- case IMX_DMATYPE_ASRC_SP: - per_2_emi = sdma->script_addrs->shp_2_mcu_addr; - emi_2_per = sdma->script_addrs->mcu_2_shp_addr; - per_2_per = sdma->script_addrs->per_2_per_addr; -@@ -774,12 +805,17 @@ - case IMX_DMATYPE_IPU_MEMORY: - emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr; - break; -+ case IMX_DMATYPE_HDMI: -+ other = sdma->script_addrs->hdmi_dma_addr; -+ break; - default: - break; - } - - sdmac->pc_from_device = per_2_emi; - sdmac->pc_to_device = emi_2_per; -+ sdmac->device_to_device = per_2_per; -+ sdmac->other_script = other; - } - - static int sdma_load_context(struct sdma_channel *sdmac) -@@ -792,11 +828,14 @@ - int ret; - unsigned long flags; - -- if (sdmac->direction == DMA_DEV_TO_MEM) { -+ if (sdmac->direction == DMA_DEV_TO_MEM) - load_address = sdmac->pc_from_device; -- } else { -+ else if (sdmac->direction == DMA_DEV_TO_DEV) -+ load_address = sdmac->device_to_device; -+ else if (sdmac->direction == DMA_MEM_TO_DEV) - load_address = sdmac->pc_to_device; -- } -+ else -+ load_address = sdmac->other_script; - - if (load_address < 0) - return load_address; -@@ -816,11 +855,16 @@ - /* Send by context the event mask,base address for peripheral - * and watermark level - */ -- context->gReg[0] = sdmac->event_mask[1]; -- context->gReg[1] = sdmac->event_mask[0]; -- context->gReg[2] = sdmac->per_addr; -- context->gReg[6] = sdmac->shp_addr; -- context->gReg[7] = sdmac->watermark_level; -+ if (sdmac->peripheral_type == IMX_DMATYPE_HDMI) { -+ context->gReg[4] = sdmac->data_addr1; -+ context->gReg[6] = sdmac->data_addr2; -+ } else { -+ context->gReg[0] = sdmac->event_mask[1]; -+ context->gReg[1] = sdmac->event_mask[0]; -+ context->gReg[2] = sdmac->per_addr; -+ context->gReg[6] = sdmac->shp_addr; -+ context->gReg[7] = sdmac->watermark_level; -+ } - - bd0->mode.command = C0_SETDM; - bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; -@@ -854,6 +898,7 @@ - static int sdma_config_channel(struct dma_chan *chan) - { - struct sdma_channel *sdmac = to_sdma_chan(chan); -+ struct imx_dma_data *data = sdmac->chan.private; - int ret; - - sdma_disable_channel(chan); -@@ -862,12 +907,19 @@ - sdmac->event_mask[1] = 0; - sdmac->shp_addr = 0; - sdmac->per_addr = 0; -+ sdmac->data_addr1 = 0; -+ sdmac->data_addr2 = 0; - -- if (sdmac->event_id0) { -+ if (sdmac->event_id0 >= 0) { - if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events) - return -EINVAL; - sdma_event_enable(sdmac, sdmac->event_id0); - } -+ if (sdmac->event_id1) { -+ if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events) -+ return -EINVAL; -+ sdma_event_enable(sdmac, sdmac->event_id1); -+ } - - switch (sdmac->peripheral_type) { - case IMX_DMATYPE_DSP: -@@ -887,19 +939,75 @@ - (sdmac->peripheral_type != IMX_DMATYPE_DSP)) { - /* Handle multiple event channels differently */ - if (sdmac->event_id1) { -- sdmac->event_mask[1] = BIT(sdmac->event_id1 % 32); -- if (sdmac->event_id1 > 31) -- __set_bit(31, &sdmac->watermark_level); -- sdmac->event_mask[0] = BIT(sdmac->event_id0 % 32); -- if (sdmac->event_id0 > 31) -- __set_bit(30, &sdmac->watermark_level); -+ if (sdmac->event_id0 > 31) { -+ sdmac->event_mask[0] |= 0; -+ __set_bit(28, &sdmac->watermark_level); -+ sdmac->event_mask[1] |= -+ BIT(sdmac->event_id0 % 32); -+ } else { -+ sdmac->event_mask[1] |= 0; -+ sdmac->event_mask[0] |= -+ BIT(sdmac->event_id0 % 32); -+ } -+ if (sdmac->event_id1 > 31) { -+ sdmac->event_mask[0] |= 0; -+ __set_bit(29, &sdmac->watermark_level); -+ sdmac->event_mask[1] |= -+ BIT(sdmac->event_id1 % 32); -+ } else { -+ sdmac->event_mask[1] |= 0; -+ sdmac->event_mask[0] |= -+ BIT(sdmac->event_id1 % 32); -+ } -+ /* BIT 11: -+ * 1 : Source on SPBA -+ * 0 : Source on AIPS -+ */ -+ __set_bit(11, &sdmac->watermark_level); -+ /* BIT 12: -+ * 1 : Destination on SPBA -+ * 0 : Destination on AIPS -+ */ -+ __set_bit(12, &sdmac->watermark_level); -+ __set_bit(31, &sdmac->watermark_level); -+ /* BIT 31: -+ * 1 : Amount of samples to be transferred is -+ * unknown and script will keep on transferring -+ * samples as long as both events are detected -+ * and script must be manually stopped by the -+ * application. -+ * 0 : The amount of samples to be is equal to -+ * the count field of mode word -+ * */ -+ __set_bit(25, &sdmac->watermark_level); -+ __clear_bit(24, &sdmac->watermark_level); - } else { -- __set_bit(sdmac->event_id0, sdmac->event_mask); -+ if (sdmac->event_id0 > 31) { -+ sdmac->event_mask[0] = 0; -+ sdmac->event_mask[1] |= -+ BIT(sdmac->event_id0 % 32); -+ } else { -+ sdmac->event_mask[0] |= -+ BIT(sdmac->event_id0 % 32); -+ sdmac->event_mask[1] = 0; -+ } - } - /* Watermark Level */ - sdmac->watermark_level |= sdmac->watermark_level; - /* Address */ -- sdmac->shp_addr = sdmac->per_address; -+ if (sdmac->direction == DMA_DEV_TO_DEV) { -+ sdmac->shp_addr = sdmac->per_address2; -+ sdmac->per_addr = sdmac->per_address; -+ } else if (sdmac->direction == DMA_TRANS_NONE) { -+ if (sdmac->peripheral_type != IMX_DMATYPE_HDMI || -+ !data->data_addr1 || !data->data_addr2) -+ return -EINVAL; -+ sdmac->data_addr1 = *(u32 *)data->data_addr1; -+ sdmac->data_addr2 = *(u32 *)data->data_addr2; -+ sdmac->watermark_level = 0; -+ } else { -+ sdmac->shp_addr = sdmac->per_address; -+ } - } else { - sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */ - } -@@ -931,13 +1039,19 @@ - int channel = sdmac->channel; - int ret = -EBUSY; - -- sdmac->bd = dma_zalloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, -- GFP_KERNEL); -+ sdmac->bd_iram = true; -+ sdmac->bd = gen_pool_dma_alloc(sdma->iram_pool, PAGE_SIZE, &sdmac->bd_phys); - if (!sdmac->bd) { -- ret = -ENOMEM; -- goto out; -+ sdmac->bd_iram = false; -+ sdmac->bd = dma_alloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys, GFP_KERNEL); -+ if (!sdmac->bd) { -+ ret = -ENOMEM; -+ goto out; -+ } - } - -+ memset(sdmac->bd, 0, PAGE_SIZE); -+ - sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys; - sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys; - -@@ -987,6 +1101,7 @@ - - sdmac->peripheral_type = data->peripheral_type; - sdmac->event_id0 = data->dma_request; -+ sdmac->event_id1 = data->dma_request2; - - clk_enable(sdmac->sdma->clk_ipg); - clk_enable(sdmac->sdma->clk_ahb); -@@ -1004,6 +1119,9 @@ - /* txd.flags will be overwritten in prep funcs */ - sdmac->desc.flags = DMA_CTRL_ACK; - -+ /* Set SDMA channel mode to unvalid to avoid misconfig */ -+ sdmac->mode = SDMA_MODE_INVALID; -+ - return 0; - } - -@@ -1014,7 +1132,7 @@ - - sdma_disable_channel(chan); - -- if (sdmac->event_id0) -+ if (sdmac->event_id0 >= 0) - sdma_event_disable(sdmac, sdmac->event_id0); - if (sdmac->event_id1) - sdma_event_disable(sdmac, sdmac->event_id1); -@@ -1024,7 +1142,10 @@ - - sdma_set_channel_priority(sdmac, 0); - -- dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys); -+ if (sdmac->bd_iram) -+ gen_pool_free(sdma->iram_pool, (unsigned long)sdmac->bd, PAGE_SIZE); -+ else -+ dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys); - - clk_disable(sdma->clk_ipg); - clk_disable(sdma->clk_ahb); -@@ -1045,7 +1166,7 @@ - return NULL; - sdmac->status = DMA_IN_PROGRESS; - -- sdmac->flags = 0; -+ sdmac->mode = SDMA_MODE_NORMAL; - - sdmac->buf_tail = 0; - -@@ -1134,13 +1255,13 @@ - static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic( - struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, - size_t period_len, enum dma_transfer_direction direction, -- unsigned long flags) -+ unsigned long flags, void *context) - { - struct sdma_channel *sdmac = to_sdma_chan(chan); - struct sdma_engine *sdma = sdmac->sdma; -- int num_periods = buf_len / period_len; - int channel = sdmac->channel; - int ret, i = 0, buf = 0; -+ int num_periods; - - dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel); - -@@ -1152,12 +1273,33 @@ - sdmac->buf_tail = 0; - sdmac->period_len = period_len; - -- sdmac->flags |= IMX_DMA_SG_LOOP; - sdmac->direction = direction; -+ -+ switch (sdmac->direction) { -+ case DMA_DEV_TO_DEV: -+ sdmac->mode = SDMA_MODE_P2P; -+ break; -+ case DMA_TRANS_NONE: -+ sdmac->mode = SDMA_MODE_NO_BD; -+ break; -+ case DMA_MEM_TO_DEV: -+ case DMA_DEV_TO_MEM: -+ sdmac->mode = SDMA_MODE_LOOP; -+ break; -+ default: -+ dev_err(sdma->dev, "invalid SDMA direction %d\n", direction); -+ return NULL; -+ } -+ - ret = sdma_load_context(sdmac); - if (ret) - goto err_out; - -+ if (period_len) -+ num_periods = buf_len / period_len; -+ else -+ return &sdmac->desc; -+ - if (num_periods > NUM_BD) { - dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n", - channel, num_periods, NUM_BD); -@@ -1216,7 +1358,16 @@ - { - struct sdma_channel *sdmac = to_sdma_chan(chan); - -- if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) { -+ if (dmaengine_cfg->direction == DMA_DEV_TO_DEV) { -+ sdmac->per_address = dmaengine_cfg->src_addr; -+ sdmac->per_address2 = dmaengine_cfg->dst_addr; -+ sdmac->watermark_level = 0; -+ sdmac->watermark_level |= -+ dmaengine_cfg->src_maxburst; -+ sdmac->watermark_level |= -+ dmaengine_cfg->dst_maxburst << 16; -+ sdmac->word_size = dmaengine_cfg->dst_addr_width; -+ } else if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) { - sdmac->per_address = dmaengine_cfg->src_addr; - sdmac->watermark_level = dmaengine_cfg->src_maxburst * - dmaengine_cfg->src_addr_width; -@@ -1238,7 +1389,7 @@ - struct sdma_channel *sdmac = to_sdma_chan(chan); - u32 residue; - -- if (sdmac->flags & IMX_DMA_SG_LOOP) -+ if (sdmac->mode & SDMA_MODE_LOOP) - residue = (sdmac->num_bd - sdmac->buf_tail) * sdmac->period_len; - else - residue = sdmac->chn_count - sdmac->chn_real_count; -@@ -1286,8 +1437,7 @@ - unsigned short *ram_code; - - if (!fw) { -- dev_info(sdma->dev, "external firmware not found, using ROM firmware\n"); -- /* In this case we just use the ROM firmware. */ -+ dev_err(sdma->dev, "firmware not found\n"); - return; - } - -@@ -1302,7 +1452,10 @@ - goto err_firmware; - switch (header->version_major) { - case 1: -- sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; -+ if (header->version_minor > 0) -+ sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2; -+ else -+ sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; - break; - case 2: - sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2; -@@ -1337,7 +1490,7 @@ - release_firmware(fw); - } - --static int sdma_get_firmware(struct sdma_engine *sdma, -+static int __init sdma_get_firmware(struct sdma_engine *sdma, - const char *fw_name) - { - int ret; -@@ -1349,9 +1502,9 @@ - return ret; - } - --static int sdma_init(struct sdma_engine *sdma) -+static int __init sdma_init(struct sdma_engine *sdma) - { -- int i, ret; -+ int i, ret, ccbsize; - dma_addr_t ccb_phys; - - clk_enable(sdma->clk_ipg); -@@ -1360,14 +1513,17 @@ - /* Be sure SDMA has not started yet */ - writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); - -- sdma->channel_control = dma_alloc_coherent(NULL, -- MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) + -- sizeof(struct sdma_context_data), -- &ccb_phys, GFP_KERNEL); -+ ccbsize = MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) -+ + sizeof(struct sdma_context_data); - -+ sdma->channel_control = gen_pool_dma_alloc(sdma->iram_pool, ccbsize, &ccb_phys); - if (!sdma->channel_control) { -- ret = -ENOMEM; -- goto err_dma_alloc; -+ sdma->channel_control = dma_alloc_coherent(NULL, ccbsize, -+ &ccb_phys, GFP_KERNEL); -+ if (!sdma->channel_control) { -+ ret = -ENOMEM; -+ goto err_dma_alloc; -+ } - } - - sdma->context = (void *)sdma->channel_control + -@@ -1419,14 +1575,12 @@ - - static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param) - { -- struct sdma_channel *sdmac = to_sdma_chan(chan); - struct imx_dma_data *data = fn_param; - - if (!imx_dma_is_general_purpose(chan)) - return false; - -- sdmac->data = *data; -- chan->private = &sdmac->data; -+ chan->private = data; - - return true; - } -@@ -1444,11 +1598,12 @@ - data.dma_request = dma_spec->args[0]; - data.peripheral_type = dma_spec->args[1]; - data.priority = dma_spec->args[2]; -+ data.dma_request2 = 0; - - return dma_request_channel(mask, sdma_filter_fn, &data); - } - --static int sdma_probe(struct platform_device *pdev) -+static int __init sdma_probe(struct platform_device *pdev) - { - const struct of_device_id *of_id = - of_match_device(sdma_dt_ids, &pdev->dev); -@@ -1547,6 +1702,11 @@ - &sdma->dma_device.channels); - } - -+ if (np) -+ sdma->iram_pool = of_get_named_gen_pool(np, "iram", 0); -+ if (!sdma->iram_pool) -+ dev_warn(&pdev->dev, "no iram assigned, using external mem\n"); -+ - ret = sdma_init(sdma); - if (ret) - goto err_init; -@@ -1583,7 +1743,7 @@ - sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources; - sdma->dma_device.device_tx_status = sdma_tx_status; - sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg; -- sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic; -+ sdma->dma_device.device_prep_dma_cyclic = (void*)sdma_prep_dma_cyclic; - sdma->dma_device.device_config = sdma_config; - sdma->dma_device.device_terminate_all = sdma_disable_channel; - sdma->dma_device.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); -@@ -1594,8 +1754,6 @@ - sdma->dma_device.dev->dma_parms = &sdma->dma_parms; - dma_set_max_seg_size(sdma->dma_device.dev, 65535); - -- platform_set_drvdata(pdev, sdma); -- - ret = dma_async_device_register(&sdma->dma_device); - if (ret) { - dev_err(&pdev->dev, "unable to register\n"); -@@ -1647,10 +1805,13 @@ - }, - .id_table = sdma_devtypes, - .remove = sdma_remove, -- .probe = sdma_probe, - }; - --module_platform_driver(sdma_driver); -+static int __init sdma_module_init(void) -+{ -+ return platform_driver_probe(&sdma_driver, sdma_probe); -+} -+module_init(sdma_module_init); - - MODULE_AUTHOR("Sascha Hauer, Pengutronix "); - MODULE_DESCRIPTION("i.MX SDMA driver"); -diff -Nur linux-4.1.13.orig/drivers/gpu/drm/Kconfig linux-4.1.13/drivers/gpu/drm/Kconfig ---- linux-4.1.13.orig/drivers/gpu/drm/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/drm/Kconfig 2015-11-30 17:56:13.552139590 +0100 -@@ -217,3 +217,5 @@ - source "drivers/gpu/drm/amd/amdkfd/Kconfig" - - source "drivers/gpu/drm/imx/Kconfig" -+ -+source "drivers/gpu/drm/vivante/Kconfig" -diff -Nur linux-4.1.13.orig/drivers/gpu/drm/Makefile linux-4.1.13/drivers/gpu/drm/Makefile ---- linux-4.1.13.orig/drivers/gpu/drm/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/drm/Makefile 2015-11-30 17:56:13.552139590 +0100 -@@ -67,6 +67,7 @@ - obj-$(CONFIG_DRM_TEGRA) += tegra/ - obj-$(CONFIG_DRM_STI) += sti/ - obj-$(CONFIG_DRM_IMX) += imx/ -+obj-$(CONFIG_DRM_VIVANTE) += vivante/ - obj-y += i2c/ - obj-y += panel/ - obj-y += bridge/ -diff -Nur linux-4.1.13.orig/drivers/gpu/drm/vivante/Kconfig linux-4.1.13/drivers/gpu/drm/vivante/Kconfig ---- linux-4.1.13.orig/drivers/gpu/drm/vivante/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/drm/vivante/Kconfig 2015-11-30 17:56:13.552139590 +0100 -@@ -0,0 +1,6 @@ -+config DRM_VIVANTE -+ tristate "Vivante GCCore" -+ depends on DRM -+ help -+ Choose this option if you have a Vivante graphics card. -+ If M is selected, the module will be called vivante. -diff -Nur linux-4.1.13.orig/drivers/gpu/drm/vivante/Makefile linux-4.1.13/drivers/gpu/drm/vivante/Makefile ---- linux-4.1.13.orig/drivers/gpu/drm/vivante/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/drm/vivante/Makefile 2015-11-30 17:56:13.552139590 +0100 -@@ -0,0 +1,29 @@ -+############################################################################## -+# -+# Copyright (C) 2005 - 2013 by Vivante Corp. -+# -+# This program is free software; you can redistribute it and/or modify -+# it under the terms of the GNU General Public License as published by -+# the Free Software Foundation; either version 2 of the license, or -+# (at your option) any later version. -+# -+# This program is distributed in the hope that it will be useful, -+# but WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+# GNU General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with this program; if not write to the Free Software -+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+# -+############################################################################## -+ -+ -+# -+# Makefile for the drm device driver. This driver provides support for the -+# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. -+ -+ccflags-y := -Iinclude/drm -+vivante-y := vivante_drv.o -+ -+obj-$(CONFIG_DRM_VIVANTE) += vivante.o -diff -Nur linux-4.1.13.orig/drivers/gpu/drm/vivante/vivante_drv.c linux-4.1.13/drivers/gpu/drm/vivante/vivante_drv.c ---- linux-4.1.13.orig/drivers/gpu/drm/vivante/vivante_drv.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/drm/vivante/vivante_drv.c 2015-11-30 17:56:13.552139590 +0100 -@@ -0,0 +1,112 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2013 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+/* vivante_drv.c -- vivante driver -*- linux-c -*- -+ * -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a -+ * copy of this software and associated documentation files (the "Software"), -+ * to deal in the Software without restriction, including without limitation -+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, -+ * and/or sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice (including the next -+ * paragraph) shall be included in all copies or substantial portions of the -+ * Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -+ * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR -+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER -+ * DEALINGS IN THE SOFTWARE. -+ * -+ * Authors: -+ * Rickard E. (Rik) Faith -+ * Daryll Strauss -+ * Gareth Hughes -+ */ -+ -+#include -+#include -+ -+#include "drmP.h" -+#include "vivante_drv.h" -+ -+#include "drm_pciids.h" -+ -+static char platformdevicename[] = "Vivante GCCore"; -+static struct platform_device *pplatformdev; -+ -+static const struct file_operations viv_driver_fops = { -+ .owner = THIS_MODULE, -+ .open = drm_open, -+ .release = drm_release, -+ .unlocked_ioctl = drm_ioctl, -+ .mmap = drm_legacy_mmap, -+ .poll = drm_poll, -+ .llseek = noop_llseek, -+}; -+ -+static struct drm_driver driver = { -+// .driver_features = DRIVER_RENDER, -+ .fops = &viv_driver_fops, -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0) -+ .set_busid = drm_platform_set_busid, -+#endif -+ .name = DRIVER_NAME, -+ .desc = DRIVER_DESC, -+ .date = DRIVER_DATE, -+ .major = DRIVER_MAJOR, -+ .minor = DRIVER_MINOR, -+ .patchlevel = DRIVER_PATCHLEVEL, -+}; -+ -+static int __init vivante_init(void) -+{ -+ int retcode; -+ -+ pplatformdev = platform_device_register_simple(platformdevicename, -+ -1, NULL, 0); -+ if (pplatformdev == NULL) -+ printk(KERN_ERR"Platform device is null\n"); -+ -+ retcode = drm_platform_init(&driver, pplatformdev); -+ -+ return retcode; -+} -+ -+static void __exit vivante_exit(void) -+{ -+ if (pplatformdev) { -+ platform_device_unregister(pplatformdev); -+ pplatformdev = NULL; -+ } -+} -+ -+module_init(vivante_init); -+module_exit(vivante_exit); -+ -+MODULE_AUTHOR(DRIVER_AUTHOR); -+MODULE_DESCRIPTION(DRIVER_DESC); -+MODULE_LICENSE("GPL and additional rights"); -diff -Nur linux-4.1.13.orig/drivers/gpu/drm/vivante/vivante_drv.h linux-4.1.13/drivers/gpu/drm/vivante/vivante_drv.h ---- linux-4.1.13.orig/drivers/gpu/drm/vivante/vivante_drv.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/drm/vivante/vivante_drv.h 2015-11-30 17:56:13.552139590 +0100 -@@ -0,0 +1,69 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2013 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+/* vivante_drv.h -- Vivante DRM template customization -*- linux-c -*- -+ * Created: Wed Feb 14 12:32:32 2012 by John Zhao -+ */ -+/* -+ * -+ * Permission is hereby granted, free of charge, to any person obtaining a -+ * copy of this software and associated documentation files (the "Software"), -+ * to deal in the Software without restriction, including without limitation -+ * the rights to use, copy, modify, merge, publish, distribute, sublicense, -+ * and/or sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following conditions: -+ * -+ * The above copyright notice and this permission notice (including the next -+ * paragraph) shall be included in all copies or substantial portions of the -+ * Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL -+ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR -+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ * -+ * Authors: -+ * Gareth Hughes -+ */ -+ -+#ifndef __VIVANTE_DRV_H__ -+#define __VIVANTE_DRV_H__ -+ -+/* General customization: -+ */ -+ -+#include -+#include -+ -+#define DRIVER_AUTHOR "Vivante Inc." -+ -+#define DRIVER_NAME "vivante" -+#define DRIVER_DESC "Vivante GCCore" -+#define DRIVER_DATE "20120216" -+ -+#define DRIVER_MAJOR 1 -+#define DRIVER_MINOR 0 -+#define DRIVER_PATCHLEVEL 0 -+ -+#endif -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/allocator/default/gc_hal_kernel_allocator_array.h linux-4.1.13/drivers/gpu/galcore/allocator/default/gc_hal_kernel_allocator_array.h ---- linux-4.1.13.orig/drivers/gpu/galcore/allocator/default/gc_hal_kernel_allocator_array.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/allocator/default/gc_hal_kernel_allocator_array.h 2015-11-30 17:56:13.556139323 +0100 -@@ -0,0 +1,34 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+extern gceSTATUS -+_DefaultAlloctorInit( -+ IN gckOS Os, -+ OUT gckALLOCATOR * Allocator -+ ); -+ -+gcsALLOCATOR_DESC allocatorArray[] = -+{ -+ /* Default allocator. */ -+ gcmkDEFINE_ALLOCATOR_DESC("default", _DefaultAlloctorInit), -+}; -+ -+ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/allocator/freescale/gc_hal_kernel_allocator_array.h linux-4.1.13/drivers/gpu/galcore/allocator/freescale/gc_hal_kernel_allocator_array.h ---- linux-4.1.13.orig/drivers/gpu/galcore/allocator/freescale/gc_hal_kernel_allocator_array.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/allocator/freescale/gc_hal_kernel_allocator_array.h 2015-11-30 17:56:13.556139323 +0100 -@@ -0,0 +1,45 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+extern gceSTATUS -+_DefaultAlloctorInit( -+ IN gckOS Os, -+ OUT gckALLOCATOR * Allocator -+ ); -+ -+#if LINUX_CMA_FSL -+gceSTATUS -+_CMAFSLAlloctorInit( -+ IN gckOS Os, -+ OUT gckALLOCATOR * Allocator -+ ); -+#endif -+ -+gcsALLOCATOR_DESC allocatorArray[] = -+{ -+#if LINUX_CMA_FSL -+ gcmkDEFINE_ALLOCATOR_DESC("cmafsl", _CMAFSLAlloctorInit), -+#endif -+ /* Default allocator. */ -+ gcmkDEFINE_ALLOCATOR_DESC("default", _DefaultAlloctorInit), -+}; -+ -+ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/allocator/freescale/gc_hal_kernel_allocator_cma.c linux-4.1.13/drivers/gpu/galcore/allocator/freescale/gc_hal_kernel_allocator_cma.c ---- linux-4.1.13.orig/drivers/gpu/galcore/allocator/freescale/gc_hal_kernel_allocator_cma.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/allocator/freescale/gc_hal_kernel_allocator_cma.c 2015-11-30 17:56:13.556139323 +0100 -@@ -0,0 +1,386 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#include "gc_hal_kernel_linux.h" -+#include "gc_hal_kernel_allocator.h" -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define _GC_OBJ_ZONE gcvZONE_OS -+ -+typedef struct _gcsCMA_PRIV * gcsCMA_PRIV_PTR; -+typedef struct _gcsCMA_PRIV { -+ gctUINT32 cmasize; -+} -+gcsCMA_PRIV; -+ -+struct mdl_cma_priv { -+ gctPOINTER kvaddr; -+ dma_addr_t physical; -+}; -+ -+int gc_cma_usage_show(struct seq_file* m, void* data) -+{ -+ gcsINFO_NODE *node = m->private; -+ gckALLOCATOR Allocator = node->device; -+ gcsCMA_PRIV_PTR priv = Allocator->privateData; -+ -+ seq_printf(m, "cma: %u bytes\n", priv->cmasize); -+ -+ return 0; -+} -+ -+static gcsINFO InfoList[] = -+{ -+ {"cmausage", gc_cma_usage_show}, -+}; -+ -+static void -+_DefaultAllocatorDebugfsInit( -+ IN gckALLOCATOR Allocator, -+ IN gckDEBUGFS_DIR Root -+ ) -+{ -+ gcmkVERIFY_OK( -+ gckDEBUGFS_DIR_Init(&Allocator->debugfsDir, Root->root, "cma")); -+ -+ gcmkVERIFY_OK(gckDEBUGFS_DIR_CreateFiles( -+ &Allocator->debugfsDir, -+ InfoList, -+ gcmCOUNTOF(InfoList), -+ Allocator -+ )); -+} -+ -+static void -+_DefaultAllocatorDebugfsCleanup( -+ IN gckALLOCATOR Allocator -+ ) -+{ -+ gcmkVERIFY_OK(gckDEBUGFS_DIR_RemoveFiles( -+ &Allocator->debugfsDir, -+ InfoList, -+ gcmCOUNTOF(InfoList) -+ )); -+ -+ gckDEBUGFS_DIR_Deinit(&Allocator->debugfsDir); -+} -+ -+static gceSTATUS -+_CMAFSLAlloc( -+ IN gckALLOCATOR Allocator, -+ INOUT PLINUX_MDL Mdl, -+ IN gctSIZE_T NumPages, -+ IN gctUINT32 Flags -+ ) -+{ -+ gceSTATUS status; -+ gcsCMA_PRIV_PTR priv = (gcsCMA_PRIV_PTR)Allocator->privateData; -+ -+ struct mdl_cma_priv *mdl_priv=gcvNULL; -+ gckOS os = Allocator->os; -+ -+ gcmkHEADER_ARG("Mdl=%p NumPages=%d", Mdl, NumPages); -+ -+ gcmkONERROR(gckOS_Allocate(os, sizeof(struct mdl_cma_priv), (gctPOINTER *)&mdl_priv)); -+ mdl_priv->kvaddr = gcvNULL; -+ -+ mdl_priv->kvaddr = dma_alloc_writecombine(gcvNULL, -+ NumPages * PAGE_SIZE, -+ &mdl_priv->physical, -+ GFP_KERNEL | gcdNOWARN); -+ -+ if (mdl_priv->kvaddr == gcvNULL) -+ { -+ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); -+ } -+ -+ Mdl->priv = mdl_priv; -+ priv->cmasize += NumPages * PAGE_SIZE; -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if(mdl_priv) -+ gckOS_Free(os, mdl_priv); -+ gcmkFOOTER(); -+ return status; -+} -+ -+static void -+_CMAFSLFree( -+ IN gckALLOCATOR Allocator, -+ IN OUT PLINUX_MDL Mdl -+ ) -+{ -+ gckOS os = Allocator->os; -+ struct mdl_cma_priv *mdl_priv=(struct mdl_cma_priv *)Mdl->priv; -+ gcsCMA_PRIV_PTR priv = (gcsCMA_PRIV_PTR)Allocator->privateData; -+ dma_free_writecombine(gcvNULL, -+ Mdl->numPages * PAGE_SIZE, -+ mdl_priv->kvaddr, -+ mdl_priv->physical); -+ gckOS_Free(os, mdl_priv); -+ priv->cmasize -= Mdl->numPages * PAGE_SIZE; -+} -+ -+gctINT -+_CMAFSLMapUser( -+ gckALLOCATOR Allocator, -+ PLINUX_MDL Mdl, -+ PLINUX_MDL_MAP MdlMap, -+ gctBOOL Cacheable -+ ) -+{ -+ -+ PLINUX_MDL mdl = Mdl; -+ PLINUX_MDL_MAP mdlMap = MdlMap; -+ struct mdl_cma_priv *mdl_priv=(struct mdl_cma_priv *)Mdl->priv; -+ -+ gcmkHEADER_ARG("Allocator=%p Mdl=%p MdlMap=%p gctBOOL=%d", Allocator, Mdl, MdlMap, Cacheable); -+ -+ mdlMap->vmaAddr = (gctSTRING)vm_mmap(gcvNULL, -+ 0L, -+ mdl->numPages * PAGE_SIZE, -+ PROT_READ | PROT_WRITE, -+ MAP_SHARED, -+ 0); -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, gcvZONE_OS, -+ "%s(%d): vmaAddr->0x%X for phys_addr->0x%X", -+ __FUNCTION__, __LINE__, -+ (gctUINT32)(gctUINTPTR_T)mdlMap->vmaAddr, -+ (gctUINT32)(gctUINTPTR_T)mdl -+ ); -+ -+ if (IS_ERR(mdlMap->vmaAddr)) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, gcvZONE_OS, -+ "%s(%d): do_mmap_pgoff error", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ mdlMap->vmaAddr = gcvNULL; -+ -+ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY); -+ return gcvSTATUS_OUT_OF_MEMORY; -+ } -+ -+ down_write(¤t->mm->mmap_sem); -+ -+ mdlMap->vma = find_vma(current->mm, (unsigned long)mdlMap->vmaAddr); -+ -+ if (mdlMap->vma == gcvNULL) -+ { -+ up_write(¤t->mm->mmap_sem); -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, gcvZONE_OS, -+ "%s(%d): find_vma error", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ mdlMap->vmaAddr = gcvNULL; -+ -+ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_RESOURCES); -+ return gcvSTATUS_OUT_OF_RESOURCES; -+ } -+ -+ /* Now map all the vmalloc pages to this user address. */ -+ if (mdl->contiguous) -+ { -+ /* map kernel memory to user space.. */ -+ if (dma_mmap_writecombine(gcvNULL, -+ mdlMap->vma, -+ mdl_priv->kvaddr, -+ mdl_priv->physical, -+ mdl->numPages * PAGE_SIZE) < 0) -+ { -+ up_write(¤t->mm->mmap_sem); -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_WARNING, gcvZONE_OS, -+ "%s(%d): dma_mmap_attrs error", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ mdlMap->vmaAddr = gcvNULL; -+ -+ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY); -+ return gcvSTATUS_OUT_OF_MEMORY; -+ } -+ } -+ else -+ { -+ gckOS_Print("incorrect mdl:conti%d\n",mdl->contiguous); -+ } -+ -+ up_write(¤t->mm->mmap_sem); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+void -+_CMAUnmapUser( -+ IN gckALLOCATOR Allocator, -+ IN gctPOINTER Logical, -+ IN gctUINT32 Size -+ ) -+{ -+ if (unlikely(current->mm == gcvNULL)) -+ { -+ /* Do nothing if process is exiting. */ -+ return; -+ } -+ -+ if (vm_munmap((unsigned long)Logical, Size) < 0) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_WARNING, gcvZONE_OS, -+ "%s(%d): vm_munmap failed", -+ __FUNCTION__, __LINE__ -+ ); -+ } -+} -+ -+gceSTATUS -+_CMAMapKernel( -+ IN gckALLOCATOR Allocator, -+ IN PLINUX_MDL Mdl, -+ OUT gctPOINTER *Logical -+ ) -+{ -+ struct mdl_cma_priv *mdl_priv=(struct mdl_cma_priv *)Mdl->priv; -+ *Logical =mdl_priv->kvaddr; -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+_CMAUnmapKernel( -+ IN gckALLOCATOR Allocator, -+ IN PLINUX_MDL Mdl, -+ IN gctPOINTER Logical -+ ) -+{ -+ return gcvSTATUS_OK; -+} -+ -+extern gceSTATUS -+_DefaultLogicalToPhysical( -+ IN gckALLOCATOR Allocator, -+ IN PLINUX_MDL Mdl, -+ IN gctPOINTER Logical, -+ IN gctUINT32 ProcessID, -+ OUT gctUINT32_PTR Physical -+ ); -+ -+extern gceSTATUS -+_DefaultCache( -+ IN gckALLOCATOR Allocator, -+ IN PLINUX_MDL Mdl, -+ IN gctPOINTER Logical, -+ IN gctUINT32 Physical, -+ IN gctUINT32 Bytes, -+ IN gceCACHEOPERATION Operation -+ ); -+ -+gceSTATUS -+_CMAPhysical( -+ IN gckALLOCATOR Allocator, -+ IN PLINUX_MDL Mdl, -+ IN gctUINT32 Offset, -+ OUT gctUINT32_PTR Physical -+ ) -+{ -+ struct mdl_cma_priv *mdl_priv=(struct mdl_cma_priv *)Mdl->priv; -+ gcmkASSERT(!Offset); -+ *Physical = mdl_priv->physical; -+ -+ return gcvSTATUS_OK; -+} -+ -+ -+extern void -+_DefaultAllocatorDestructor( -+ IN void* PrivateData -+ ); -+ -+/* Default allocator operations. */ -+gcsALLOCATOR_OPERATIONS CMAFSLAllocatorOperations = { -+ .Alloc = _CMAFSLAlloc, -+ .Free = _CMAFSLFree, -+ .MapUser = _CMAFSLMapUser, -+ .UnmapUser = _CMAUnmapUser, -+ .MapKernel = _CMAMapKernel, -+ .UnmapKernel = _CMAUnmapKernel, -+ .LogicalToPhysical = _DefaultLogicalToPhysical, -+ .Cache = _DefaultCache, -+ .Physical = _CMAPhysical, -+}; -+ -+/* Default allocator entry. */ -+gceSTATUS -+_CMAFSLAlloctorInit( -+ IN gckOS Os, -+ OUT gckALLOCATOR * Allocator -+ ) -+{ -+ gceSTATUS status; -+ gckALLOCATOR allocator; -+ gcsCMA_PRIV_PTR priv = gcvNULL; -+ -+ gcmkONERROR( -+ gckALLOCATOR_Construct(Os, &CMAFSLAllocatorOperations, &allocator)); -+ -+ priv = kzalloc(gcmSIZEOF(gcsCMA_PRIV), GFP_KERNEL | gcdNOWARN); -+ -+ if (!priv) -+ { -+ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); -+ } -+ -+ /* Register private data. */ -+ allocator->privateData = priv; -+ allocator->privateDataDestructor = _DefaultAllocatorDestructor; -+ -+ allocator->debugfsInit = _DefaultAllocatorDebugfsInit; -+ allocator->debugfsCleanup = _DefaultAllocatorDebugfsCleanup; -+ -+ allocator->capability = gcvALLOC_FLAG_CONTIGUOUS; -+ -+ *Allocator = allocator; -+ -+ return gcvSTATUS_OK; -+ -+OnError: -+ return status; -+} -+ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/arch/gc_hal_kernel_context.c linux-4.1.13/drivers/gpu/galcore/arch/gc_hal_kernel_context.c ---- linux-4.1.13.orig/drivers/gpu/galcore/arch/gc_hal_kernel_context.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/arch/gc_hal_kernel_context.c 2015-11-30 17:56:13.556139323 +0100 -@@ -0,0 +1,2252 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#include "gc_hal.h" -+#include "gc_hal_kernel.h" -+#include "gc_hal_kernel_context.h" -+#include "gc_hal_kernel_buffer.h" -+ -+/******************************************************************************\ -+******************************** Debugging Macro ******************************* -+\******************************************************************************/ -+ -+/* Zone used for header/footer. */ -+#define _GC_OBJ_ZONE gcvZONE_HARDWARE -+ -+ -+/******************************************************************************\ -+************************** Context State Buffer Helpers ************************ -+\******************************************************************************/ -+ -+#define _STATE(reg) \ -+ _State(\ -+ Context, index, \ -+ reg ## _Address >> 2, \ -+ reg ## _ResetValue, \ -+ reg ## _Count, \ -+ gcvFALSE, gcvFALSE \ -+ ) -+ -+#define _STATE_COUNT(reg, count) \ -+ _State(\ -+ Context, index, \ -+ reg ## _Address >> 2, \ -+ reg ## _ResetValue, \ -+ count, \ -+ gcvFALSE, gcvFALSE \ -+ ) -+ -+#define _STATE_COUNT_OFFSET(reg, offset, count) \ -+ _State(\ -+ Context, index, \ -+ (reg ## _Address >> 2) + offset, \ -+ reg ## _ResetValue, \ -+ count, \ -+ gcvFALSE, gcvFALSE \ -+ ) -+ -+#define _STATE_MIRROR_COUNT(reg, mirror, count) \ -+ _StateMirror(\ -+ Context, \ -+ reg ## _Address >> 2, \ -+ count, \ -+ mirror ## _Address >> 2 \ -+ ) -+ -+#define _STATE_HINT(reg) \ -+ _State(\ -+ Context, index, \ -+ reg ## _Address >> 2, \ -+ reg ## _ResetValue, \ -+ reg ## _Count, \ -+ gcvFALSE, gcvTRUE \ -+ ) -+ -+#define _STATE_HINT_BLOCK(reg, block, count) \ -+ _State(\ -+ Context, index, \ -+ (reg ## _Address >> 2) + (block << reg ## _BLK), \ -+ reg ## _ResetValue, \ -+ count, \ -+ gcvFALSE, gcvTRUE \ -+ ) -+ -+#define _STATE_COUNT_OFFSET_HINT(reg, offset, count) \ -+ _State(\ -+ Context, index, \ -+ (reg ## _Address >> 2) + offset, \ -+ reg ## _ResetValue, \ -+ count, \ -+ gcvFALSE, gcvTRUE \ -+ ) -+ -+#define _STATE_X(reg) \ -+ _State(\ -+ Context, index, \ -+ reg ## _Address >> 2, \ -+ reg ## _ResetValue, \ -+ reg ## _Count, \ -+ gcvTRUE, gcvFALSE \ -+ ) -+ -+#define _STATE_INIT_VALUE(reg, value) \ -+ _State(\ -+ Context, index, \ -+ reg ## _Address >> 2, \ -+ value, \ -+ reg ## _Count, \ -+ gcvFALSE, gcvFALSE \ -+ ) -+ -+#define _CLOSE_RANGE() \ -+ _TerminateStateBlock(Context, index) -+ -+#define _ENABLE(reg, field) \ -+ do \ -+ { \ -+ if (gcmVERIFYFIELDVALUE(data, reg, MASK_ ## field, ENABLED)) \ -+ { \ -+ enable |= gcmFIELDMASK(reg, field); \ -+ } \ -+ } \ -+ while (gcvFALSE) -+ -+#define _BLOCK_COUNT(reg) \ -+ ((reg ## _Count) >> (reg ## _BLK)) -+ -+ -+/******************************************************************************\ -+*********************** Support Functions and Definitions ********************** -+\******************************************************************************/ -+ -+#define gcdSTATE_MASK \ -+ (((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x03 | 0xC0FFEE & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27)))) -+ -+#if gcdENABLE_3D -+static gctUINT32 -+_TerminateStateBlock( -+ IN gckCONTEXT Context, -+ IN gctUINT32 Index -+ ) -+{ -+ gctUINT32_PTR buffer; -+ gctUINT32 align; -+ -+ /* Determine if we need alignment. */ -+ align = (Index & 1) ? 1 : 0; -+ -+ /* Address correct index. */ -+ buffer = (Context->buffer == gcvNULL) -+ ? gcvNULL -+ : Context->buffer->logical; -+ -+ /* Flush the current state block; make sure no pairing with the states -+ to follow happens. */ -+ if (align && (buffer != gcvNULL)) -+ { -+ buffer[Index] = 0xDEADDEAD; -+ } -+ -+ /* Reset last address. */ -+ Context->lastAddress = ~0U; -+ -+ /* Return alignment requirement. */ -+ return align; -+} -+#endif -+ -+ -+#if (gcdENABLE_3D || gcdENABLE_2D) -+static gctUINT32 -+_FlushPipe( -+ IN gckCONTEXT Context, -+ IN gctUINT32 Index, -+ IN gcePIPE_SELECT Pipe -+ ) -+{ -+ gctBOOL fcFlushStall; -+ gctUINT32 flushSlots; -+ gctBOOL iCacheInvalidate; -+ -+ fcFlushStall -+ = gckHARDWARE_IsFeatureAvailable(Context->hardware, gcvFEATURE_FC_FLUSH_STALL); -+ -+ iCacheInvalidate -+ = ((((gctUINT32) (Context->hardware->identity.chipMinorFeatures3)) >> (0 ? 3:3) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))); -+ -+ flushSlots = 6; -+ -+ if (fcFlushStall) -+ { -+ /* Flush tile status cache. */ -+ flushSlots += 6; -+ } -+ -+ if (iCacheInvalidate) -+ { -+ flushSlots += 12; -+ } -+ -+ if (Context->buffer != gcvNULL) -+ { -+ gctUINT32_PTR buffer; -+ -+ /* Address correct index. */ -+ buffer = Context->buffer->logical + Index; -+ -+ /* Flush the current pipe. */ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E03) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); -+ -+ *buffer++ -+ = (Pipe == gcvPIPE_2D) -+ ? ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) -+ : ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))); -+ -+ /* Semaphore from FE to PE. */ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); -+ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); -+ -+ /* Stall from FE to PE. */ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))); -+ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); -+ -+ if (fcFlushStall) -+ { -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0594) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))); -+ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))); -+ -+ /* Semaphore from FE to PE. */ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); -+ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); -+ -+ /* Stall from FE to PE. */ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))); -+ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); -+ } -+ -+ if (iCacheInvalidate) -+ { -+ /* Invalidate I$ after pipe is stalled */ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0218) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); -+ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))); -+ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x021A) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); -+ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))); -+ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0218) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); -+ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))); -+ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x021A) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); -+ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))); -+ -+ /* Semaphore from FE to PE. */ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); -+ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); -+ -+ /* Stall from FE to PE. */ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))); -+ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); -+ } -+ } -+ -+ /* Number of slots taken by flushing pipe. */ -+ return flushSlots; -+} -+#endif -+ -+#if gcdENABLE_3D -+static gctUINT32 -+_SemaphoreStall( -+ IN gckCONTEXT Context, -+ IN gctUINT32 Index -+ ) -+{ -+ if (Context->buffer != gcvNULL) -+ { -+ gctUINT32_PTR buffer; -+ -+ /* Address correct index. */ -+ buffer = Context->buffer->logical + Index; -+ -+ /* Semaphore from FE to PE. */ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); -+ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); -+ -+ /* Stall from FE to PE. */ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))); -+ -+ *buffer -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); -+ } -+ -+ /* Semaphore/stall takes 4 slots. */ -+ return 4; -+} -+#endif -+ -+#if (gcdENABLE_3D || gcdENABLE_2D) -+static gctUINT32 -+_SwitchPipe( -+ IN gckCONTEXT Context, -+ IN gctUINT32 Index, -+ IN gcePIPE_SELECT Pipe -+ ) -+{ -+ gctUINT32 slots = 6; -+ -+ if (Context->buffer != gcvNULL) -+ { -+ gctUINT32_PTR buffer; -+ -+ /* Address correct index. */ -+ buffer = Context->buffer->logical + Index; -+ -+ /* LoadState(AQPipeSelect, 1), pipe. */ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E00) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))); -+ -+ *buffer++ -+ = (Pipe == gcvPIPE_2D) -+ ? 0x1 -+ : 0x0; -+ -+ /* Semaphore from FE to PE. */ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); -+ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); -+ -+ /* Stall from FE to PE. */ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))); -+ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); -+ } -+ -+ Context->pipeSelectBytes = slots * gcmSIZEOF(gctUINT32); -+ -+ return slots; -+} -+#endif -+ -+#if gcdENABLE_3D -+static gctUINT32 -+_State( -+ IN gckCONTEXT Context, -+ IN gctUINT32 Index, -+ IN gctUINT32 Address, -+ IN gctUINT32 Value, -+ IN gctUINT32 Size, -+ IN gctBOOL FixedPoint, -+ IN gctBOOL Hinted -+ ) -+{ -+ gctUINT32_PTR buffer; -+ gctUINT32 align; -+ gctUINT32 i; -+ -+ /* Determine if we need alignment. */ -+ align = (Index & 1) ? 1 : 0; -+ -+ /* Address correct index. */ -+ buffer = (Context->buffer == gcvNULL) -+ ? gcvNULL -+ : Context->buffer->logical; -+ -+ if ((buffer == gcvNULL) && (Address + Size > Context->stateCount)) -+ { -+ /* Determine maximum state. */ -+ Context->stateCount = Address + Size; -+ } -+ -+ /* Do we need a new entry? */ -+ if ((Address != Context->lastAddress) || (FixedPoint != Context->lastFixed)) -+ { -+ if (buffer != gcvNULL) -+ { -+ if (align) -+ { -+ /* Add filler. */ -+ buffer[Index++] = 0xDEADDEAD; -+ } -+ -+ /* LoadState(Address, Count). */ -+ gcmkASSERT((Index & 1) == 0); -+ -+ if (FixedPoint) -+ { -+ buffer[Index] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1))))))) << (0 ? 26:26))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1))))))) << (0 ? 26:26))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (Size) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (Address) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); -+ } -+ else -+ { -+ buffer[Index] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1))))))) << (0 ? 26:26))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1))))))) << (0 ? 26:26))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (Size) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (Address) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); -+ } -+ -+ /* Walk all the states. */ -+ for (i = 0; i < (gctUINT32)Size; i += 1) -+ { -+ /* Set state to uninitialized value. */ -+ buffer[Index + 1 + i] = Value; -+ -+ /* Set index in state mapping table. */ -+ Context->map[Address + i].index = (gctUINT)Index + 1 + i; -+ } -+ } -+ -+ /* Save information for this LoadState. */ -+ Context->lastIndex = (gctUINT)Index; -+ Context->lastAddress = Address + (gctUINT32)Size; -+ Context->lastSize = Size; -+ Context->lastFixed = FixedPoint; -+ -+ /* Return size for load state. */ -+ return align + 1 + Size; -+ } -+ -+ /* Append this state to the previous one. */ -+ if (buffer != gcvNULL) -+ { -+ /* Update last load state. */ -+ buffer[Context->lastIndex] = -+ ((((gctUINT32) (buffer[Context->lastIndex])) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (Context->lastSize + Size) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))); -+ -+ /* Walk all the states. */ -+ for (i = 0; i < (gctUINT32)Size; i += 1) -+ { -+ /* Set state to uninitialized value. */ -+ buffer[Index + i] = Value; -+ -+ /* Set index in state mapping table. */ -+ Context->map[Address + i].index = (gctUINT)Index + i; -+ } -+ } -+ -+ /* Update last address and size. */ -+ Context->lastAddress += (gctUINT32)Size; -+ Context->lastSize += Size; -+ -+ /* Return number of slots required. */ -+ return Size; -+} -+ -+static gctUINT32 -+_StateMirror( -+ IN gckCONTEXT Context, -+ IN gctUINT32 Address, -+ IN gctUINT32 Size, -+ IN gctUINT32 AddressMirror -+ ) -+{ -+ gctUINT32 i; -+ -+ /* Process when buffer is set. */ -+ if (Context->buffer != gcvNULL) -+ { -+ /* Walk all states. */ -+ for (i = 0; i < Size; i++) -+ { -+ /* Copy the mapping address. */ -+ Context->map[Address + i].index = -+ Context->map[AddressMirror + i].index; -+ } -+ } -+ -+ /* Return the number of required maps. */ -+ return Size; -+} -+#endif -+ -+#if (gcdENABLE_3D || gcdENABLE_2D) -+static gceSTATUS -+_InitializeContextBuffer( -+ IN gckCONTEXT Context -+ ) -+{ -+ gctUINT32_PTR buffer; -+ gctUINT32 index; -+ -+#if gcdENABLE_3D -+ gctBOOL halti0, halti1, halti2, halti3; -+ gctUINT i; -+ gctUINT vertexUniforms, fragmentUniforms, vsConstBase, psConstBase, constMax; -+ gctBOOL unifiedUniform; -+ gctUINT fe2vsCount; -+#endif -+ -+ /* Reset the buffer index. */ -+ index = 0; -+ -+ /* Reset the last state address. */ -+ Context->lastAddress = ~0U; -+ -+ /* Get the buffer pointer. */ -+ buffer = (Context->buffer == gcvNULL) -+ ? gcvNULL -+ : Context->buffer->logical; -+ -+ -+ /**************************************************************************/ -+ /* Build 2D states. *******************************************************/ -+ -+ -+#if gcdENABLE_3D -+ /**************************************************************************/ -+ /* Build 3D states. *******************************************************/ -+ -+ halti0 = (((((gctUINT32) (Context->hardware->identity.chipMinorFeatures1)) >> (0 ? 23:23)) & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1)))))) ); -+ halti1 = (((((gctUINT32) (Context->hardware->identity.chipMinorFeatures2)) >> (0 ? 11:11)) & ((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1)))))) ); -+ halti2 = (((((gctUINT32) (Context->hardware->identity.chipMinorFeatures4)) >> (0 ? 16:16)) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) ); -+ halti3 = (((((gctUINT32) (Context->hardware->identity.chipMinorFeatures5)) >> (0 ? 9:9)) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) ); -+ -+ /* Query how many uniforms can support for non-unified uniform mode. */ -+ {if (Context->hardware->identity.numConstants > 256){ unifiedUniform = gcvTRUE; vsConstBase = 0xC000; psConstBase = 0xC000; constMax = Context->hardware->identity.numConstants; vertexUniforms = 256; fragmentUniforms = constMax - vertexUniforms;}else if (Context->hardware->identity.numConstants == 256){ if (Context->hardware->identity.chipModel == gcv2000 && Context->hardware->identity.chipRevision == 0x5118) { unifiedUniform = gcvFALSE; vsConstBase = 0x1400; psConstBase = 0x1C00; vertexUniforms = 256; fragmentUniforms = 64; constMax = 320; } else { unifiedUniform = gcvFALSE; vsConstBase = 0x1400; psConstBase = 0x1C00; vertexUniforms = 256; fragmentUniforms = 256; constMax = 512; }}else{ unifiedUniform = gcvFALSE; vsConstBase = 0x1400; psConstBase = 0x1C00; vertexUniforms = 168; fragmentUniforms = 64; constMax = 232;}}; -+ -+#if !gcdENABLE_UNIFIED_CONSTANT -+ if (Context->hardware->identity.numConstants > 256) -+ { -+ unifiedUniform = gcvTRUE; -+ } -+ else -+ { -+ unifiedUniform = gcvFALSE; -+ } -+#endif -+ -+ /* Store the 3D entry index. */ -+ Context->entryOffset3D = (gctUINT)index * gcmSIZEOF(gctUINT32); -+ -+ /* Switch to 3D pipe. */ -+ index += _SwitchPipe(Context, index, gcvPIPE_3D); -+ -+ /* Current context pointer. */ -+#if DEBUG -+ index += _State(Context, index, 0x03850 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+#endif -+ -+ index += _FlushPipe(Context, index, gcvPIPE_3D); -+ -+ /* Global states. */ -+ index += _State(Context, index, 0x03814 >> 2, 0x00000001, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x03818 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x0381C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x03820 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x03828 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x0382C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x03834 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x03838 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x03854 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x0384C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ -+ /* Front End states. */ -+ fe2vsCount = 12; -+ if (halti0) -+ { -+ fe2vsCount = 16; -+ } -+ index += _State(Context, index, 0x00600 >> 2, 0x00000000, fe2vsCount, gcvFALSE, gcvFALSE); -+ index += _CLOSE_RANGE(); -+ -+ index += _State(Context, index, 0x00644 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, 0x00648 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x0064C >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, 0x00650 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00680 >> 2, 0x00000000, 8, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, 0x006A0 >> 2, 0x00000000, 8, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00674 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00670 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00678 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x0067C >> 2, 0xFFFFFFFF, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x006C0 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00700 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00740 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00780 >> 2, 0x3F800000, 16, gcvFALSE, gcvFALSE); -+ -+ if (halti2) -+ { -+ index += _State(Context, index, 0x14600 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x14640 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x14680 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE); -+ } -+ -+ /* This register is programed by all chips, which program all DECODE_SELECT as VS -+ ** except SAMPLER_DECODE_SELECT. -+ */ -+ index += _State(Context, index, 0x00860 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ -+ if (((((gctUINT32) (Context->hardware->identity.chipMinorFeatures3)) >> (0 ? 3:3) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))))) -+ { -+ /* I-Cache states. */ -+ index += _State(Context, index, 0x00868 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x0086C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x0304C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x01028 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _CLOSE_RANGE(); -+ -+ if (halti3) -+ { -+ index += _State(Context, index, 0x00890 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, 0x0104C >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE); -+ index += _CLOSE_RANGE(); -+ } -+ } -+ -+ /* Vertex Shader states. */ -+ index += _State(Context, index, 0x00804 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00808 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x0080C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00810 >> 2, 0x00000000, 4, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00820 >> 2, 0x00000000, 4, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00830 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ -+ index += _CLOSE_RANGE(); -+ -+ /* Primitive Assembly states. */ -+ index += _State(Context, index, 0x00A00 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE); -+ index += _State(Context, index, 0x00A04 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE); -+ index += _State(Context, index, 0x00A08 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00A0C >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE); -+ index += _State(Context, index, 0x00A10 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE); -+ index += _State(Context, index, 0x00A14 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00A18 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00A1C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00A28 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00A2C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00A30 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00A40 >> 2, 0x00000000, Context->hardware->identity.varyingsCount, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00A34 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00A38 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00A3C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00A80 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00A84 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE); -+ index += _State(Context, index, 0x00A8C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00A88 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ -+ /* Setup states. */ -+ index += _State(Context, index, 0x00C00 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE); -+ index += _State(Context, index, 0x00C04 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE); -+ index += _State(Context, index, 0x00C08 >> 2, 0x45000000, 1, gcvTRUE, gcvFALSE); -+ index += _State(Context, index, 0x00C0C >> 2, 0x45000000, 1, gcvTRUE, gcvFALSE); -+ index += _State(Context, index, 0x00C10 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00C14 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00C18 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00C1C >> 2, 0x42000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00C20 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE); -+ index += _State(Context, index, 0x00C24 >> 2, 0x00000000, 1, gcvTRUE, gcvFALSE); -+ -+ /* Raster states. */ -+ index += _State(Context, index, 0x00E00 >> 2, 0x00000001, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00E10 >> 2, 0x00000000, 4, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00E04 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00E40 >> 2, 0x00000000, 16, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00E08 >> 2, 0x00000031, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00E24 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00E20 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ -+ if (halti2) -+ { -+ index += _State(Context, index, 0x00E0C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ } -+ -+ /* Pixel Shader states. */ -+ index += _State(Context, index, 0x01004 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x01008 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x0100C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x01010 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x01030 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ -+ index += _CLOSE_RANGE(); -+ -+ /* Texture states. */ -+ index += _State(Context, index, 0x02000 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x02040 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x02080 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x020C0 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x02100 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x02140 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x02180 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x021C0 >> 2, 0x00321000, 12, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x02200 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x02240 >> 2, 0x00000000, 12, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, (0x02400 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, (0x02440 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, (0x02480 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, (0x024C0 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, (0x02500 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, (0x02540 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, (0x02580 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, (0x025C0 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, (0x02600 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, (0x02640 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, (0x02680 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, (0x026C0 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, (0x02700 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, (0x02740 >> 2) + (0 << 4), 0x00000000, 12, gcvFALSE, gcvTRUE); -+ index += _CLOSE_RANGE(); -+ -+ if ((((((gctUINT32) (Context->hardware->identity.chipMinorFeatures1)) >> (0 ? 22:22)) & ((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1)))))) )) -+ { -+ /* -+ * Linear stride LODn will overwrite LOD0 on GC880,GC2000. -+ * And only LOD0 is valid for this register. -+ */ -+ gctUINT count = halti1 ? 14 : 1; -+ -+ for (i = 0; i < 12; i += 1) -+ { -+ index += _State(Context, index, (0x02C00 >> 2) + i * 16, 0x00000000, count, gcvFALSE, gcvFALSE); -+ } -+ } -+ -+ if (halti1) -+ { -+ gctUINT texBlockCount; -+ gctUINT gcregTXLogSizeResetValue; -+ -+ /* Enable the integer filter pipe for all texture samplers -+ so that the floating point filter clock will shut off until -+ we start using the floating point filter. -+ */ -+ gcregTXLogSizeResetValue = ((((gctUINT32) (0x00000000)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 29:29) - (0 ? 29:29) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 29:29) - (0 ? 29:29) + 1))))))) << (0 ? 29:29))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 29:29) - (0 ? 29:29) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 29:29) - (0 ? 29:29) + 1))))))) << (0 ? 29:29))); -+ -+ /* New texture block. */ -+ index += _State(Context, index, 0x10000 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x10080 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x10100 >> 2, gcregTXLogSizeResetValue, 32, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x10180 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x10200 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x10280 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x10300 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x10380 >> 2, 0x00321000, 32, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x10400 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x10480 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE); -+ -+ if ((((((gctUINT32) (Context->hardware->identity.chipMinorFeatures2)) >> (0 ? 15:15)) & ((gctUINT32) ((((1 ? 15:15) - (0 ? 15:15) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:15) - (0 ? 15:15) + 1)))))) )) -+ { -+ index += _State(Context, index, 0x12000 >> 2, 0x00000000, 256, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x12400 >> 2, 0x00000000, 256, gcvFALSE, gcvFALSE); -+ } -+ -+ texBlockCount = ((512) >> (4)); -+ -+ for (i = 0; i < texBlockCount; i += 1) -+ { -+ index += _State(Context, index, (0x10800 >> 2) + (i << 4), 0x00000000, 14, gcvFALSE, gcvTRUE); -+ } -+ } -+ -+ if (halti2) -+ { -+ index += _State(Context, index, 0x10700 >> 2, 0x00000F00, 32, gcvFALSE, gcvFALSE); -+ } -+ -+ if (halti3) -+ { -+ index += _State(Context, index, 0x10780 >> 2, 0x00030000, 32, gcvFALSE, gcvFALSE); -+ } -+ -+ /* ASTC */ -+ if ((((((gctUINT32) (Context->hardware->identity.chipMinorFeatures4)) >> (0 ? 13:13)) & ((gctUINT32) ((((1 ? 13:13) - (0 ? 13:13) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:13) - (0 ? 13:13) + 1)))))) )) -+ { -+ index += _State(Context, index, 0x10500 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x10580 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x10600 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x10680 >> 2, 0x00000000, 32, gcvFALSE, gcvFALSE); -+ } -+ -+ /* YUV. */ -+ index += _State(Context, index, 0x01678 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x0167C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x01680 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, 0x01684 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x01688 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, 0x0168C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x01690 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, 0x01694 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x01698 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, 0x0169C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _CLOSE_RANGE(); -+ -+ /* Thread walker states. */ -+ index += _State(Context, index, 0x00900 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00904 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00908 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x0090C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00910 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00914 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00918 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x0091C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00924 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ -+ if (((((gctUINT32) (Context->hardware->identity.chipMinorFeatures3)) >> (0 ? 21:21) & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1)))))))) -+ { -+ index += _State(Context, index, 0x00940 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00944 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00948 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x0094C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00950 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00954 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ } -+ -+ index += _CLOSE_RANGE(); -+ -+ if (!halti3) -+ { -+ if (Context->hardware->identity.instructionCount > 1024) -+ { -+ /* New Shader instruction PC registers. */ -+ index += _State(Context, index, 0x0085C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x0101C >> 2, 0x00000100, 1, gcvFALSE, gcvFALSE); -+ index += _CLOSE_RANGE(); -+ -+ for (i = 0; -+ i < Context->hardware->identity.instructionCount << 2; -+ i += 256 << 2 -+ ) -+ { -+ index += _State(Context, index, (0x20000 >> 2) + i, 0x00000000, 256 << 2, gcvFALSE, gcvFALSE); -+ index += _CLOSE_RANGE(); -+ } -+ } -+ else if (Context->hardware->identity.instructionCount > 256) -+ { -+ /* New Shader instruction PC registers. */ -+ index += _State(Context, index, 0x0085C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x0101C >> 2, 0x00000100, 1, gcvFALSE, gcvFALSE); -+ index += _CLOSE_RANGE(); -+ -+ /* VX instruction memory. */ -+ for (i = 0; -+ i < Context->hardware->identity.instructionCount << 2; -+ i += 256 << 2 -+ ) -+ { -+ index += _State(Context, index, (0x0C000 >> 2) + i, 0x00000000, 256 << 2, gcvFALSE, gcvFALSE); -+ index += _CLOSE_RANGE(); -+ } -+ -+ _StateMirror(Context, 0x08000 >> 2, Context->hardware->identity.instructionCount << 2 , 0x0C000 >> 2); -+ } -+ else /* if (Context->hardware->identity.instructionCount <= 256) */ -+ { -+ /* old shader instruction PC registers */ -+ index += _State(Context, index, 0x00800 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00838 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _CLOSE_RANGE(); -+ -+ index += _State(Context, index, 0x01000 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x01018 >> 2, 0x01000000, 1, gcvFALSE, gcvFALSE); -+ index += _CLOSE_RANGE(); -+ -+ index += _State(Context, index, 0x04000 >> 2, 0x00000000, 1024, gcvFALSE, gcvFALSE); -+ index += _CLOSE_RANGE(); -+ index += _State(Context, index, 0x06000 >> 2, 0x00000000, 1024, gcvFALSE, gcvFALSE); -+ index += _CLOSE_RANGE(); -+ } -+ } -+ /* I cache use the new instruction PC registers */ -+ else -+ { -+ /* New Shader instruction PC registers. */ -+ index += _State(Context, index, 0x0085C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x0101C >> 2, 0x00000100, 1, gcvFALSE, gcvFALSE); -+ index += _CLOSE_RANGE(); -+ } -+ -+ if (unifiedUniform) -+ { -+ gctINT numConstants = Context->hardware->identity.numConstants; -+ -+ index += _State(Context, index, 0x01024 >> 2, 0x00000100, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x00864 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _CLOSE_RANGE(); -+ -+ for (i = 0; -+ numConstants > 0; -+ i += 256 << 2, -+ numConstants -= 256 -+ ) -+ { -+ if (numConstants >= 256) -+ { -+ index += _State(Context, index, (0x30000 >> 2) + i, 0x00000000, 256 << 2, gcvFALSE, gcvFALSE); -+ } -+ else -+ { -+ index += _State(Context, index, (0x30000 >> 2) + i, 0x00000000, numConstants << 2, gcvFALSE, gcvFALSE); -+ } -+ index += _CLOSE_RANGE(); -+ } -+ } -+#if gcdENABLE_UNIFIED_CONSTANT -+ else -+#endif -+ { -+ index += _State(Context, index, 0x05000 >> 2, 0x00000000, vertexUniforms * 4, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x07000 >> 2, 0x00000000, fragmentUniforms * 4, gcvFALSE, gcvFALSE); -+ } -+ -+ /* Store the index of the "XD" entry. */ -+ Context->entryOffsetXDFrom3D = (gctUINT)index * gcmSIZEOF(gctUINT32); -+ -+ -+ /* Pixel Engine states. */ -+ index += _State(Context, index, 0x01400 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x01404 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x01408 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x0140C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x01414 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x01418 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x0141C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x01420 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x01424 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x01428 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x0142C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x01434 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x01454 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x01458 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, 0x0145C >> 2, 0x00000010, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x014A0 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x014A8 >> 2, 0xFFFFFFFF, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x014AC >> 2, 0xFFFFFFFF, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x014B0 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x014B4 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x014A4 >> 2, 0x000E400C, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x01580 >> 2, 0x00000000, 3, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x014B8 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ -+ /* Composition states. */ -+ index += _State(Context, index, 0x03008 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ -+ if (Context->hardware->identity.pixelPipes == 1) -+ { -+ index += _State(Context, index, 0x01460 >> 2, 0x00000000, 8, gcvFALSE, gcvTRUE); -+ -+ index += _State(Context, index, 0x01430 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, 0x01410 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE); -+ } -+ else -+ { -+ index += _State(Context, index, (0x01460 >> 2) + (0 << 3), 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvTRUE); -+ } -+ -+ if (Context->hardware->identity.pixelPipes > 1 || halti0) -+ { -+ index += _State(Context, index, (0x01480 >> 2) + (0 << 3), 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvTRUE); -+ } -+ -+ for (i = 0; i < 3; i++) -+ { -+ index += _State(Context, index, (0x01500 >> 2) + (i << 3), 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvTRUE); -+ } -+ -+ if (halti2) -+ { -+ for (i = 0; i < 7; i++) -+ { -+ index += _State(Context, index, (0x14800 >> 2) + (i << 3), 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvTRUE); -+ } -+ index += _State(Context, index, 0x14900 >> 2, 0x00000000, 7, gcvFALSE, gcvFALSE); -+ } -+ -+ -+ if (halti3) -+ { -+ index += _State(Context, index, 0x014BC >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ } -+ -+ /* Resolve states. */ -+ index += _State(Context, index, 0x01604 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x01608 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, 0x0160C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x01610 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, 0x01614 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x01620 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x01630 >> 2, 0x00000000, 2, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x01640 >> 2, 0x00000000, 4, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x0163C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x016A0 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x016B4 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _CLOSE_RANGE(); -+ -+ if ((Context->hardware->identity.pixelPipes > 1) || halti1) -+ { -+ index += _State(Context, index, (0x016C0 >> 2) + (0 << 3), 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvTRUE); -+ -+ index += _State(Context, index, (0x016E0 >> 2) + (0 << 3), 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvTRUE); -+ -+ index += _State(Context, index, 0x01700 >> 2, 0x00000000, Context->hardware->identity.pixelPipes, gcvFALSE, gcvFALSE); -+ } -+ -+#if gcd3DBLIT -+ index += _State(Context, index, (0x14000 >> 2) + (0 << 1), 0x00000000, 2, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, 0x14008 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x1400C >> 2, 0x0001C800, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x14010 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, 0x14014 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, (0x14018 >> 2) + (0 << 1), 0x00000000, 2, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, 0x14020 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, 0x14024 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x14028 >> 2, 0x0001C800, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x1402C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x14030 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x14034 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x14038 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x1403C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x14040 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x14044 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x14048 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x1404C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x14050 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x14058 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x1405C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x14054 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x14100 >> 2, 0x00000000, 64, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x14200 >> 2, 0x00000000, 64, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x14064 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x14068 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ -+ index += _State(Context, index, 0x1406C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x14070 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x14074 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x14078 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x1407C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x14080 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x14084 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x14088 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x1408C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x14090 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ -+ index += _State(Context, index, 0x14094 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x14098 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+#endif -+ -+ /* Tile status. */ -+ index += _State(Context, index, 0x01654 >> 2, 0x00200000, 1, gcvFALSE, gcvFALSE); -+ -+ index += _CLOSE_RANGE(); -+ index += _State(Context, index, 0x01658 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, 0x0165C >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, 0x01660 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x01664 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, 0x01668 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, 0x0166C >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x01670 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x01674 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x016A4 >> 2, 0x00000000, 1, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, 0x016AC >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x016A8 >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x01720 >> 2, 0x00000000, 8, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x01740 >> 2, 0x00000000, 8, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, 0x01760 >> 2, 0x00000000, 8, gcvFALSE, gcvFALSE); -+ -+ -+ if (halti2) -+ { -+ index += _State(Context, index, 0x01780 >> 2, 0x00000000, 8, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, 0x016BC >> 2, 0x00000000, 1, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, (0x017A0 >> 2) + 1, 0x00000000, 7, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, (0x017C0 >> 2) + 1, 0x00000000, 7, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, (0x017E0 >> 2) + 1, 0x00000000, 7, gcvFALSE, gcvTRUE); -+ index += _State(Context, index, (0x01A00 >> 2) + 1, 0x00000000, 7, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, (0x01A20 >> 2) + 1, 0x00000000, 7, gcvFALSE, gcvFALSE); -+ index += _State(Context, index, (0x01A40 >> 2) + 1, 0x00000000, 7, gcvFALSE, gcvFALSE); -+ } -+ -+ index += _CLOSE_RANGE(); -+ -+ if(((((gctUINT32) (Context->hardware->identity.chipMinorFeatures4)) >> (0 ? 25:25) & ((gctUINT32) ((((1 ? 25:25) - (0 ? 25:25) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:25) - (0 ? 25:25) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 25:25) - (0 ? 25:25) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:25) - (0 ? 25:25) + 1)))))))) -+ { -+ index += _State(Context, index, 0x03860 >> 2, 0x6, 1, gcvFALSE, gcvFALSE); -+ index += _CLOSE_RANGE(); -+ } -+ -+ if (halti3) -+ { -+ index += _State(Context, index, 0x01A80 >> 2, 0x00000000, 8, gcvFALSE, gcvTRUE); -+ index += _CLOSE_RANGE(); -+ } -+ -+ /* Semaphore/stall. */ -+ index += _SemaphoreStall(Context, index); -+#endif -+ -+ /**************************************************************************/ -+ /* Link to another address. ***********************************************/ -+ -+ Context->linkIndex3D = (gctUINT)index; -+ -+ if (buffer != gcvNULL) -+ { -+ buffer[index + 0] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); -+ -+ buffer[index + 1] -+ = 0; -+ } -+ -+ index += 2; -+ -+ /* Store the end of the context buffer. */ -+ Context->bufferSize = index * gcmSIZEOF(gctUINT32); -+ -+ -+ /**************************************************************************/ -+ /* Pipe switch for the case where neither 2D nor 3D are used. *************/ -+ -+ /* Store the 3D entry index. */ -+ Context->entryOffsetXDFrom2D = (gctUINT)index * gcmSIZEOF(gctUINT32); -+ -+ /* Flush 2D pipe. */ -+ index += _FlushPipe(Context, index, gcvPIPE_2D); -+ -+ /* Switch to 3D pipe. */ -+ index += _SwitchPipe(Context, index, gcvPIPE_3D); -+ -+ /* Store the location of the link. */ -+ Context->linkIndexXD = (gctUINT)index; -+ -+ if (buffer != gcvNULL) -+ { -+ buffer[index + 0] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); -+ -+ buffer[index + 1] -+ = 0; -+ } -+ -+ index += 2; -+ -+ -+ /**************************************************************************/ -+ /* Save size for buffer. **************************************************/ -+ -+ Context->totalSize = index * gcmSIZEOF(gctUINT32); -+ -+ -+ /* Success. */ -+ return gcvSTATUS_OK; -+} -+#endif -+ -+static gceSTATUS -+_DestroyContext( -+ IN gckCONTEXT Context -+ ) -+{ -+ gceSTATUS status = gcvSTATUS_OK; -+ -+ if (Context != gcvNULL) -+ { -+ gcsCONTEXT_PTR bufferHead; -+ -+ /* Free context buffers. */ -+ for (bufferHead = Context->buffer; Context->buffer != gcvNULL;) -+ { -+ /* Get a shortcut to the current buffer. */ -+ gcsCONTEXT_PTR buffer = Context->buffer; -+ -+ /* Get the next buffer. */ -+ gcsCONTEXT_PTR next = buffer->next; -+ -+ /* Last item? */ -+ if (next == bufferHead) -+ { -+ next = gcvNULL; -+ } -+ -+ /* Destroy the signal. */ -+ if (buffer->signal != gcvNULL) -+ { -+ gcmkONERROR(gckOS_DestroySignal( -+ Context->os, buffer->signal -+ )); -+ -+ buffer->signal = gcvNULL; -+ } -+ -+ /* Free state delta map. */ -+ if (buffer->logical != gcvNULL) -+ { -+ if (Context->hardware->kernel->virtualCommandBuffer) -+ { -+ gcmkONERROR(gckEVENT_DestroyVirtualCommandBuffer( -+ Context->hardware->kernel->eventObj, -+ Context->totalSize, -+ buffer->physical, -+ buffer->logical, -+ gcvKERNEL_PIXEL -+ )); -+ } -+ else -+ { -+ gcmkONERROR(gckEVENT_FreeContiguousMemory( -+ Context->hardware->kernel->eventObj, -+ Context->totalSize, -+ buffer->physical, -+ buffer->logical, -+ gcvKERNEL_PIXEL -+ )); -+ } -+ -+ buffer->logical = gcvNULL; -+ } -+ -+ /* Free context buffer. */ -+ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, buffer)); -+ -+ /* Remove from the list. */ -+ Context->buffer = next; -+ } -+ -+ /* Free record array copy. */ -+#if REMOVE_DUPLICATED_COPY_FROM_USER -+ if (Context->recordArrayMap != gcvNULL) -+ { -+ gcsRECORD_ARRAY_MAP_PTR map = Context->recordArrayMap; -+ -+ do -+ { -+ /* Free record array. */ -+ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, map->kData)); -+ map = map->next; -+ } -+ while (map != Context->recordArrayMap); -+ -+ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, Context->recordArrayMap)); -+ } -+#else -+ if (Context->recordArray != gcvNULL) -+ { -+ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, Context->recordArray)); -+ } -+#endif -+ -+ /* Free the state mapping. */ -+ if (Context->map != gcvNULL) -+ { -+ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, Context->map)); -+ } -+ -+ /* Mark the gckCONTEXT object as unknown. */ -+ Context->object.type = gcvOBJ_UNKNOWN; -+ -+ /* Free the gckCONTEXT object. */ -+ gcmkONERROR(gcmkOS_SAFE_FREE(Context->os, Context)); -+ } -+ -+OnError: -+ return status; -+} -+ -+ -+/******************************************************************************\ -+**************************** Context Management API **************************** -+\******************************************************************************/ -+ -+/******************************************************************************\ -+** -+** gckCONTEXT_Construct -+** -+** Construct a new gckCONTEXT object. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to gckOS object. -+** -+** gctUINT32 ProcessID -+** Current process ID. -+** -+** gckHARDWARE Hardware -+** Pointer to gckHARDWARE object. -+** -+** OUTPUT: -+** -+** gckCONTEXT * Context -+** Pointer to a variable thet will receive the gckCONTEXT object -+** pointer. -+*/ -+#if (gcdENABLE_3D || gcdENABLE_2D) -+gceSTATUS -+gckCONTEXT_Construct( -+ IN gckOS Os, -+ IN gckHARDWARE Hardware, -+ IN gctUINT32 ProcessID, -+ OUT gckCONTEXT * Context -+ ) -+{ -+ gceSTATUS status; -+ gckCONTEXT context = gcvNULL; -+ gctUINT32 allocationSize; -+ gctUINT i; -+ gctPOINTER pointer = gcvNULL; -+ gctUINT32 address; -+ -+ gcmkHEADER_ARG("Os=0x%08X Hardware=0x%08X", Os, Hardware); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Context != gcvNULL); -+ -+ -+ /**************************************************************************/ -+ /* Allocate and initialize basic fields of gckCONTEXT. ********************/ -+ -+ /* The context object size. */ -+ allocationSize = gcmSIZEOF(struct _gckCONTEXT); -+ -+ /* Allocate the object. */ -+ gcmkONERROR(gckOS_Allocate( -+ Os, allocationSize, &pointer -+ )); -+ -+ context = pointer; -+ -+ /* Reset the entire object. */ -+ gcmkONERROR(gckOS_ZeroMemory(context, allocationSize)); -+ -+ /* Initialize the gckCONTEXT object. */ -+ context->object.type = gcvOBJ_CONTEXT; -+ context->os = Os; -+ context->hardware = Hardware; -+ -+ -+#if !gcdENABLE_3D -+ context->entryPipe = gcvPIPE_2D; -+ context->exitPipe = gcvPIPE_2D; -+#elif gcdCMD_NO_2D_CONTEXT -+ context->entryPipe = gcvPIPE_3D; -+ context->exitPipe = gcvPIPE_3D; -+#else -+ context->entryPipe -+ = (((((gctUINT32) (context->hardware->identity.chipFeatures)) >> (0 ? 9:9)) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) ) -+ ? gcvPIPE_2D -+ : gcvPIPE_3D; -+ context->exitPipe = gcvPIPE_3D; -+#endif -+ -+ /* Get the command buffer requirements. */ -+ gcmkONERROR(gckHARDWARE_QueryCommandBuffer( -+ Hardware, -+ &context->alignment, -+ &context->reservedHead, -+ &context->reservedTail -+ )); -+ -+ /* Mark the context as dirty to force loading of the entire state table -+ the first time. */ -+ context->dirty = gcvTRUE; -+ -+ -+ /**************************************************************************/ -+ /* Get the size of the context buffer. ************************************/ -+ -+ gcmkONERROR(_InitializeContextBuffer(context)); -+ -+ -+ /**************************************************************************/ -+ /* Compute the size of the record array. **********************************/ -+ -+ context->recordArraySize -+ = gcmSIZEOF(gcsSTATE_DELTA_RECORD) * (gctUINT)context->stateCount; -+ -+ -+ if (context->stateCount > 0) -+ { -+ /**************************************************************************/ -+ /* Allocate and reset the state mapping table. ****************************/ -+ -+ /* Allocate the state mapping table. */ -+ gcmkONERROR(gckOS_Allocate( -+ Os, -+ gcmSIZEOF(gcsSTATE_MAP) * context->stateCount, -+ &pointer -+ )); -+ -+ context->map = pointer; -+ -+ /* Zero the state mapping table. */ -+ gcmkONERROR(gckOS_ZeroMemory( -+ context->map, gcmSIZEOF(gcsSTATE_MAP) * context->stateCount -+ )); -+ } -+ -+ /**************************************************************************/ -+ /* Allocate the context and state delta buffers. **************************/ -+ -+ for (i = 0; i < gcdCONTEXT_BUFFER_COUNT; i += 1) -+ { -+ /* Allocate a context buffer. */ -+ gcsCONTEXT_PTR buffer; -+ -+ gctSIZE_T totalSize = context->totalSize; -+ -+ /* Allocate the context buffer structure. */ -+ gcmkONERROR(gckOS_Allocate( -+ Os, -+ gcmSIZEOF(gcsCONTEXT), -+ &pointer -+ )); -+ -+ buffer = pointer; -+ -+ /* Reset the context buffer structure. */ -+ gcmkVERIFY_OK(gckOS_ZeroMemory( -+ buffer, gcmSIZEOF(gcsCONTEXT) -+ )); -+ -+ /* Append to the list. */ -+ if (context->buffer == gcvNULL) -+ { -+ buffer->next = buffer; -+ context->buffer = buffer; -+ } -+ else -+ { -+ buffer->next = context->buffer->next; -+ context->buffer->next = buffer; -+ } -+ -+ /* Set the number of delta in the order of creation. */ -+#if gcmIS_DEBUG(gcdDEBUG_CODE) -+ buffer->num = i; -+#endif -+ -+ /* Create the busy signal. */ -+ gcmkONERROR(gckOS_CreateSignal( -+ Os, gcvFALSE, &buffer->signal -+ )); -+ -+ /* Set the signal, buffer is currently not busy. */ -+ gcmkONERROR(gckOS_Signal( -+ Os, buffer->signal, gcvTRUE -+ )); -+ -+ /* Create a new physical context buffer. */ -+ if (context->hardware->kernel->virtualCommandBuffer) -+ { -+ gcmkONERROR(gckKERNEL_AllocateVirtualCommandBuffer( -+ context->hardware->kernel, -+ gcvFALSE, -+ &totalSize, -+ &buffer->physical, -+ &pointer -+ )); -+ -+ gcmkONERROR(gckKERNEL_GetGPUAddress( -+ context->hardware->kernel, -+ pointer, -+ gcvFALSE, -+ &address -+ )); -+ } -+ else -+ { -+ gcmkONERROR(gckOS_AllocateContiguous( -+ Os, -+ gcvFALSE, -+ &totalSize, -+ &buffer->physical, -+ &pointer -+ )); -+ -+ gcmkONERROR(gckHARDWARE_ConvertLogical( -+ context->hardware, -+ pointer, -+ gcvFALSE, -+ &address -+ )); -+ } -+ -+ buffer->logical = pointer; -+ buffer->address = address; -+ -+ /* Set gckEVENT object pointer. */ -+ buffer->eventObj = Hardware->kernel->eventObj; -+ -+ /* Set the pointers to the LINK commands. */ -+ if (context->linkIndex2D != 0) -+ { -+ buffer->link2D = &buffer->logical[context->linkIndex2D]; -+ } -+ -+ if (context->linkIndex3D != 0) -+ { -+ buffer->link3D = &buffer->logical[context->linkIndex3D]; -+ } -+ -+ if (context->linkIndexXD != 0) -+ { -+ gctPOINTER xdLink; -+ gctUINT32 xdEntryAddress; -+ gctUINT32 xdEntrySize; -+ gctUINT32 linkBytes; -+ -+ /* Determine LINK parameters. */ -+ xdLink -+ = &buffer->logical[context->linkIndexXD]; -+ -+ xdEntryAddress -+ = buffer->address -+ + context->entryOffsetXDFrom3D; -+ -+ xdEntrySize -+ = context->bufferSize -+ - context->entryOffsetXDFrom3D; -+ -+ /* Query LINK size. */ -+ gcmkONERROR(gckHARDWARE_Link( -+ Hardware, gcvNULL, 0, 0, &linkBytes -+ )); -+ -+ /* Generate a LINK. */ -+ gcmkONERROR(gckHARDWARE_Link( -+ Hardware, -+ xdLink, -+ xdEntryAddress, -+ xdEntrySize, -+ &linkBytes -+ )); -+ } -+ } -+ -+ -+ /**************************************************************************/ -+ /* Initialize the context buffers. ****************************************/ -+ -+ /* Initialize the current context buffer. */ -+ gcmkONERROR(_InitializeContextBuffer(context)); -+ -+ /* Make all created contexts equal. */ -+ { -+ gcsCONTEXT_PTR currContext, tempContext; -+ -+ /* Set the current context buffer. */ -+ currContext = context->buffer; -+ -+ /* Get the next context buffer. */ -+ tempContext = currContext->next; -+ -+ /* Loop through all buffers. */ -+ while (tempContext != currContext) -+ { -+ if (tempContext == gcvNULL) -+ { -+ gcmkONERROR(gcvSTATUS_NOT_FOUND); -+ } -+ -+ /* Copy the current context. */ -+ gckOS_MemCopy( -+ tempContext->logical, -+ currContext->logical, -+ context->totalSize -+ ); -+ -+ /* Get the next context buffer. */ -+ tempContext = tempContext->next; -+ } -+ } -+ -+ /* Return pointer to the gckCONTEXT object. */ -+ *Context = context; -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Context=0x%08X", *Context); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Roll back on error. */ -+ gcmkVERIFY_OK(_DestroyContext(context)); -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+#endif -+ -+/******************************************************************************\ -+** -+** gckCONTEXT_Destroy -+** -+** Destroy a gckCONTEXT object. -+** -+** INPUT: -+** -+** gckCONTEXT Context -+** Pointer to an gckCONTEXT object. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckCONTEXT_Destroy( -+ IN gckCONTEXT Context -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Context=0x%08X", Context); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Context, gcvOBJ_CONTEXT); -+ -+ /* Destroy the context and all related objects. */ -+ status = _DestroyContext(Context); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return status; -+} -+ -+/******************************************************************************\ -+** -+** gckCONTEXT_Update -+** -+** Merge all pending state delta buffers into the current context buffer. -+** -+** INPUT: -+** -+** gckCONTEXT Context -+** Pointer to an gckCONTEXT object. -+** -+** gctUINT32 ProcessID -+** Current process ID. -+** -+** gcsSTATE_DELTA_PTR StateDelta -+** Pointer to the state delta. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckCONTEXT_Update( -+ IN gckCONTEXT Context, -+ IN gctUINT32 ProcessID, -+ IN gcsSTATE_DELTA_PTR StateDelta -+ ) -+{ -+#if gcdENABLE_3D -+ gceSTATUS status = gcvSTATUS_OK; -+ gcsSTATE_DELTA _stateDelta; -+ gckKERNEL kernel; -+ gcsCONTEXT_PTR buffer; -+ gcsSTATE_MAP_PTR map; -+ gctBOOL needCopy = gcvFALSE; -+ gcsSTATE_DELTA_PTR nDelta; -+ gcsSTATE_DELTA_PTR uDelta = gcvNULL; -+ gcsSTATE_DELTA_PTR kDelta = gcvNULL; -+ gcsSTATE_DELTA_RECORD_PTR record; -+ gcsSTATE_DELTA_RECORD_PTR recordArray = gcvNULL; -+#if REMOVE_DUPLICATED_COPY_FROM_USER -+ gcsRECORD_ARRAY_MAP_PTR recordArrayMap = gcvNULL; -+#endif -+ gctUINT elementCount; -+ gctUINT address; -+ gctUINT32 mask; -+ gctUINT32 data; -+ gctUINT index; -+ gctUINT i, j; -+ -+ gcmkHEADER_ARG( -+ "Context=0x%08X ProcessID=%d StateDelta=0x%08X", -+ Context, ProcessID, StateDelta -+ ); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Context, gcvOBJ_CONTEXT); -+ -+ /* Get a shortcut to the kernel object. */ -+ kernel = Context->hardware->kernel; -+ -+ /* Check wehther we need to copy the structures or not. */ -+ gcmkONERROR(gckOS_QueryNeedCopy(Context->os, ProcessID, &needCopy)); -+ -+ /* Allocate the copy buffer for the user record array. */ -+#if REMOVE_DUPLICATED_COPY_FROM_USER -+ if (needCopy && (Context->recordArrayMap == gcvNULL)) -+ { -+ /* Allocate enough maps. */ -+ gcmkONERROR(gckOS_Allocate( -+ Context->os, -+ gcmSIZEOF(gcsRECORD_ARRAY_MAP_PTR) * gcdCONTEXT_BUFFER_COUNT, -+ (gctPOINTER *) &Context->recordArrayMap -+ )); -+ -+ for (i = 0; i < gcdCONTEXT_BUFFER_COUNT; i++) -+ { -+ /* Next mapping id. */ -+ gctUINT n = (i + 1) % gcdCONTEXT_BUFFER_COUNT; -+ -+ recordArrayMap = &Context->recordArrayMap[i]; -+ -+ /* Allocate the buffer. */ -+ gcmkONERROR(gckOS_Allocate( -+ Context->os, -+ Context->recordArraySize, -+ (gctPOINTER *) &recordArrayMap->kData -+ )); -+ -+ /* Initialize fields. */ -+ recordArrayMap->key = 0; -+ recordArrayMap->next = &Context->recordArrayMap[n]; -+ } -+ } -+#else -+ if (needCopy && (Context->recordArray == gcvNULL)) -+ { -+ /* Allocate the buffer. */ -+ gcmkONERROR(gckOS_Allocate( -+ Context->os, -+ Context->recordArraySize, -+ (gctPOINTER *) &Context->recordArray -+ )); -+ } -+#endif -+ -+ /* Get the current context buffer. */ -+ buffer = Context->buffer; -+ -+ /* Wait until the context buffer becomes available; this will -+ also reset the signal and mark the buffer as busy. */ -+ gcmkONERROR(gckOS_WaitSignal( -+ Context->os, buffer->signal, gcvINFINITE -+ )); -+ -+#if gcmIS_DEBUG(gcdDEBUG_CODE) && 1 && gcdENABLE_3D -+ /* Update current context token. */ -+ buffer->logical[Context->map[0x0E14].index] -+ = (gctUINT32)gcmPTR2INT32(Context); -+#endif -+ -+ /* Are there any pending deltas? */ -+ if (buffer->deltaCount != 0) -+ { -+ /* Get the state map. */ -+ map = Context->map; -+ -+ /* Get the first delta item. */ -+ uDelta = buffer->delta; -+ -+ /* Reset the vertex stream count. */ -+ elementCount = 0; -+ -+ /* Merge all pending deltas. */ -+ for (i = 0; i < buffer->deltaCount; i += 1) -+ { -+ /* Get access to the state delta. */ -+ gcmkONERROR(gckKERNEL_OpenUserData( -+ kernel, needCopy, -+ &_stateDelta, -+ uDelta, gcmSIZEOF(gcsSTATE_DELTA), -+ (gctPOINTER *) &kDelta -+ )); -+ -+#if REMOVE_DUPLICATED_COPY_FROM_USER -+ if (needCopy) -+ { -+ recordArray = gcvNULL; -+ recordArrayMap = Context->recordArrayMap; -+ -+ do -+ { -+ /* Check if recordArray is alreay opened. */ -+ if (recordArrayMap->key == kDelta->recordArray) -+ { -+ /* Found. */ -+ recordArray = recordArrayMap->kData; -+ break; -+ } -+ -+ recordArrayMap = recordArrayMap->next; -+ } -+ while (recordArrayMap != Context->recordArrayMap); -+ -+ if (recordArray == gcvNULL) -+ { -+ while (recordArrayMap->key != 0) -+ { -+ /* Found an empty slot. */ -+ recordArrayMap = recordArrayMap->next; -+ } -+ -+ /* Get access to the state records. */ -+ gcmkONERROR(gckOS_CopyFromUserData( -+ kernel->os, -+ recordArrayMap->kData, -+ gcmUINT64_TO_PTR(kDelta->recordArray), -+ Context->recordArraySize -+ )); -+ -+ /* Save user pointer as key. */ -+ recordArrayMap->key = kDelta->recordArray; -+ recordArray = recordArrayMap->kData; -+ } -+ } -+ else -+ { -+ /* Get access to the state records. */ -+ gcmkONERROR(gckOS_MapUserPointer( -+ kernel->os, -+ gcmUINT64_TO_PTR(kDelta->recordArray), -+ Context->recordArraySize, -+ (gctPOINTER *) &recordArray -+ )); -+ } -+#else -+ /* Get access to the state records. */ -+ gcmkONERROR(gckKERNEL_OpenUserData( -+ kernel, needCopy, -+ Context->recordArray, -+ gcmUINT64_TO_PTR(kDelta->recordArray), Context->recordArraySize, -+ (gctPOINTER *) &recordArray -+ )); -+#endif -+ -+ /* Merge all pending states. */ -+ for (j = 0; j < kDelta->recordCount; j += 1) -+ { -+ if (j >= Context->stateCount) -+ { -+ break; -+ } -+ -+ /* Get the current state record. */ -+ record = &recordArray[j]; -+ -+ /* Get the state address. */ -+ address = record->address; -+ -+ /* Make sure the state is a part of the mapping table. */ -+ if (address >= Context->stateCount) -+ { -+ gcmkTRACE( -+ gcvLEVEL_ERROR, -+ "%s(%d): State 0x%04X is not mapped.\n", -+ __FUNCTION__, __LINE__, -+ address -+ ); -+ -+ continue; -+ } -+ -+ /* Get the state index. */ -+ index = map[address].index; -+ -+ /* Skip the state if not mapped. */ -+ if (index == 0) -+ { -+ continue; -+ } -+ -+ /* Get the data mask. */ -+ mask = record->mask; -+ -+ /* Masked states that are being completly reset or regular states. */ -+ if ((mask == 0) || (mask == ~0U)) -+ { -+ /* Get the new data value. */ -+ data = record->data; -+ -+ /* Process special states. */ -+ if (address == 0x0595) -+ { -+ /* Force auto-disable to be disabled. */ -+ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))); -+ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))); -+ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 13:13) - (0 ? 13:13) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:13) - (0 ? 13:13) + 1))))))) << (0 ? 13:13))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 13:13) - (0 ? 13:13) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:13) - (0 ? 13:13) + 1))))))) << (0 ? 13:13))); -+ } -+ -+ /* Set new data. */ -+ buffer->logical[index] = data; -+ } -+ -+ /* Masked states that are being set partially. */ -+ else -+ { -+ buffer->logical[index] -+ = (~mask & buffer->logical[index]) -+ | (mask & record->data); -+ } -+ } -+ -+ /* Get the element count. */ -+ if (kDelta->elementCount != 0) -+ { -+ elementCount = kDelta->elementCount; -+ } -+ -+ /* Dereference delta. */ -+ kDelta->refCount -= 1; -+ gcmkASSERT(kDelta->refCount >= 0); -+ -+ /* Get the next state delta. */ -+ nDelta = gcmUINT64_TO_PTR(kDelta->next); -+ -+#if REMOVE_DUPLICATED_COPY_FROM_USER -+ if (needCopy) -+ { -+ if (kDelta->refCount == 0) -+ { -+ /* No other reference, reset the mapping. */ -+ recordArrayMap->key = 0; -+ } -+ } -+ else -+ { -+ /* Close access to the state records. */ -+ gcmkONERROR(gckOS_UnmapUserPointer( -+ kernel->os, -+ gcmUINT64_TO_PTR(kDelta->recordArray), -+ Context->recordArraySize, -+ (gctPOINTER *) recordArray -+ )); -+ -+ recordArray = gcvNULL; -+ } -+#else -+ /* Get access to the state records. */ -+ gcmkONERROR(gckKERNEL_CloseUserData( -+ kernel, needCopy, -+ gcvFALSE, -+ gcmUINT64_TO_PTR(kDelta->recordArray), Context->recordArraySize, -+ (gctPOINTER *) &recordArray -+ )); -+#endif -+ -+ /* Close access to the current state delta. */ -+ gcmkONERROR(gckKERNEL_CloseUserData( -+ kernel, needCopy, -+ gcvTRUE, -+ uDelta, gcmSIZEOF(gcsSTATE_DELTA), -+ (gctPOINTER *) &kDelta -+ )); -+ -+ /* Update the user delta pointer. */ -+ uDelta = nDelta; -+ } -+ -+ /* Hardware disables all input streams when the stream 0 is programmed, -+ it then reenables those streams that were explicitely programmed by -+ the software. Because of this we cannot program the entire array of -+ values, otherwise we'll get all streams reenabled, but rather program -+ only those that are actully needed by the software. */ -+ if (elementCount != 0) -+ { -+ gctUINT base; -+ gctUINT nopCount; -+ gctUINT32_PTR nop; -+ gctUINT fe2vsCount = 12; -+ -+ if ((((((gctUINT32) (Context->hardware->identity.chipMinorFeatures1)) >> (0 ? 23:23)) & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1)))))) )) -+ { -+ fe2vsCount = 16; -+ } -+ -+ /* Determine the base index of the vertex stream array. */ -+ base = map[0x0180].index; -+ -+ /* Set the proper state count. */ -+ buffer->logical[base - 1] -+ = ((((gctUINT32) (buffer->logical[base - 1])) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (elementCount ) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))); -+ -+ /* Determine the number of NOP commands. */ -+ nopCount -+ = (fe2vsCount / 2) -+ - (elementCount / 2); -+ -+ /* Determine the location of the first NOP. */ -+ nop = &buffer->logical[base + (elementCount | 1)]; -+ -+ if ((nop + (nopCount * 2)) >= buffer->logical + Context->totalSize) -+ nopCount = (buffer->logical + Context->totalSize - nop) / 2; -+ -+ /* Fill the unused space with NOPs. */ -+ for (i = 0; i < nopCount; i += 1) -+ { -+ /* Generate a NOP command. */ -+ *nop = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x03 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))); -+ -+ /* Advance. */ -+ nop += 2; -+ } -+ } -+ -+ /* Reset pending deltas. */ -+ buffer->deltaCount = 0; -+ buffer->delta = gcvNULL; -+ } -+ -+ /* Set state delta user pointer. */ -+ uDelta = StateDelta; -+ -+ /* Get access to the state delta. */ -+ gcmkONERROR(gckKERNEL_OpenUserData( -+ kernel, needCopy, -+ &_stateDelta, -+ uDelta, gcmSIZEOF(gcsSTATE_DELTA), -+ (gctPOINTER *) &kDelta -+ )); -+ -+ /* State delta cannot be attached to anything yet. */ -+ if (kDelta->refCount != 0) -+ { -+ gcmkTRACE( -+ gcvLEVEL_ERROR, -+ "%s(%d): kDelta->refCount = %d (has to be 0).\n", -+ __FUNCTION__, __LINE__, -+ kDelta->refCount -+ ); -+ } -+ -+ /* Attach to all contexts. */ -+ buffer = Context->buffer; -+ -+ do -+ { -+ /* Attach to the context if nothing is attached yet. If a delta -+ is allready attached, all we need to do is to increment -+ the number of deltas in the context. */ -+ if (buffer->delta == gcvNULL) -+ { -+ buffer->delta = uDelta; -+ } -+ -+ /* Update reference count. */ -+ kDelta->refCount += 1; -+ -+ /* Update counters. */ -+ buffer->deltaCount += 1; -+ -+ /* Get the next context buffer. */ -+ buffer = buffer->next; -+ -+ if (buffer == gcvNULL) -+ { -+ gcmkONERROR(gcvSTATUS_NOT_FOUND); -+ } -+ } -+ while (Context->buffer != buffer); -+ -+ /* Close access to the current state delta. */ -+ gcmkONERROR(gckKERNEL_CloseUserData( -+ kernel, needCopy, -+ gcvTRUE, -+ uDelta, gcmSIZEOF(gcsSTATE_DELTA), -+ (gctPOINTER *) &kDelta -+ )); -+ -+ /* Schedule an event to mark the context buffer as available. */ -+ gcmkONERROR(gckEVENT_Signal( -+ buffer->eventObj, buffer->signal, gcvKERNEL_PIXEL -+ )); -+ -+ /* Advance to the next context buffer. */ -+ Context->buffer = buffer->next; -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Get access to the state records. */ -+ if (kDelta != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckKERNEL_CloseUserData( -+ kernel, needCopy, -+ gcvFALSE, -+ gcmUINT64_TO_PTR(kDelta->recordArray), Context->recordArraySize, -+ (gctPOINTER *) &recordArray -+ )); -+ } -+ -+ /* Close access to the current state delta. */ -+ gcmkVERIFY_OK(gckKERNEL_CloseUserData( -+ kernel, needCopy, -+ gcvTRUE, -+ uDelta, gcmSIZEOF(gcsSTATE_DELTA), -+ (gctPOINTER *) &kDelta -+ )); -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+#else -+ return gcvSTATUS_OK; -+#endif -+} -+ -+gceSTATUS -+gckCONTEXT_MapBuffer( -+ IN gckCONTEXT Context, -+ OUT gctUINT32 *Physicals, -+ OUT gctUINT64 *Logicals, -+ OUT gctUINT32 *Bytes -+ ) -+{ -+ gceSTATUS status; -+ int i = 0; -+ gctSIZE_T pageCount; -+ gckVIRTUAL_COMMAND_BUFFER_PTR commandBuffer; -+ gckKERNEL kernel = Context->hardware->kernel; -+ gctPOINTER logical; -+ gctPHYS_ADDR physical; -+ -+ gcsCONTEXT_PTR buffer; -+ -+ gcmkHEADER(); -+ -+ gcmkVERIFY_OBJECT(Context, gcvOBJ_CONTEXT); -+ -+ buffer = Context->buffer; -+ -+ for (i = 0; i < gcdCONTEXT_BUFFER_COUNT; i++) -+ { -+ if (kernel->virtualCommandBuffer) -+ { -+ commandBuffer = (gckVIRTUAL_COMMAND_BUFFER_PTR)buffer->physical; -+ physical = commandBuffer->physical; -+ -+ gcmkONERROR(gckOS_CreateUserVirtualMapping( -+ kernel->os, -+ physical, -+ Context->totalSize, -+ &logical, -+ &pageCount)); -+ } -+ else -+ { -+ physical = buffer->physical; -+ -+ gcmkONERROR(gckOS_MapMemory( -+ kernel->os, -+ physical, -+ Context->totalSize, -+ &logical)); -+ } -+ -+ Physicals[i] = gcmPTR_TO_NAME(physical); -+ -+ Logicals[i] = gcmPTR_TO_UINT64(logical); -+ -+ buffer = buffer->next; -+ } -+ -+ *Bytes = (gctUINT)Context->totalSize; -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ gcmkFOOTER(); -+ return status; -+} -+ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/arch/gc_hal_kernel_context.h linux-4.1.13/drivers/gpu/galcore/arch/gc_hal_kernel_context.h ---- linux-4.1.13.orig/drivers/gpu/galcore/arch/gc_hal_kernel_context.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/arch/gc_hal_kernel_context.h 2015-11-30 17:56:13.556139323 +0100 -@@ -0,0 +1,178 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#ifndef __gc_hal_kernel_context_h_ -+#define __gc_hal_kernel_context_h_ -+ -+#include "gc_hal_kernel_buffer.h" -+ -+/* Exprimental optimization. */ -+#define REMOVE_DUPLICATED_COPY_FROM_USER 1 -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+/* Maps state locations within the context buffer. */ -+typedef struct _gcsSTATE_MAP * gcsSTATE_MAP_PTR; -+typedef struct _gcsSTATE_MAP -+{ -+ /* Index of the state in the context buffer. */ -+ gctUINT index; -+ -+ /* State mask. */ -+ gctUINT32 mask; -+} -+gcsSTATE_MAP; -+ -+/* Context buffer. */ -+typedef struct _gcsCONTEXT * gcsCONTEXT_PTR; -+typedef struct _gcsCONTEXT -+{ -+ /* For debugging: the number of context buffer in the order of creation. */ -+#if gcmIS_DEBUG(gcdDEBUG_CODE) -+ gctUINT num; -+#endif -+ -+ /* Pointer to gckEVENT object. */ -+ gckEVENT eventObj; -+ -+ /* Context busy signal. */ -+ gctSIGNAL signal; -+ -+ /* Physical address of the context buffer. */ -+ gctPHYS_ADDR physical; -+ -+ /* Logical address of the context buffer. */ -+ gctUINT32_PTR logical; -+ -+ /* Hardware address of the context buffer. */ -+ gctUINT32 address; -+ -+ /* Pointer to the LINK commands. */ -+ gctPOINTER link2D; -+ gctPOINTER link3D; -+ -+ /* The number of pending state deltas. */ -+ gctUINT deltaCount; -+ -+ /* Pointer to the first delta to be applied. */ -+ gcsSTATE_DELTA_PTR delta; -+ -+ /* Next context buffer. */ -+ gcsCONTEXT_PTR next; -+} -+gcsCONTEXT; -+ -+typedef struct _gcsRECORD_ARRAY_MAP * gcsRECORD_ARRAY_MAP_PTR; -+struct _gcsRECORD_ARRAY_MAP -+{ -+ /* User pointer key. */ -+ gctUINT64 key; -+ -+ /* Kernel memory buffer. */ -+ gcsSTATE_DELTA_RECORD_PTR kData; -+ -+ /* Next map. */ -+ gcsRECORD_ARRAY_MAP_PTR next; -+ -+}; -+ -+/* gckCONTEXT structure that hold the current context. */ -+struct _gckCONTEXT -+{ -+ /* Object. */ -+ gcsOBJECT object; -+ -+ /* Pointer to gckOS object. */ -+ gckOS os; -+ -+ /* Pointer to gckHARDWARE object. */ -+ gckHARDWARE hardware; -+ -+ /* Command buffer alignment. */ -+ gctUINT32 alignment; -+ gctUINT32 reservedHead; -+ gctUINT32 reservedTail; -+ -+ /* Context buffer metrics. */ -+ gctSIZE_T stateCount; -+ gctUINT32 totalSize; -+ gctUINT32 bufferSize; -+ gctUINT32 linkIndex2D; -+ gctUINT32 linkIndex3D; -+ gctUINT32 linkIndexXD; -+ gctUINT32 entryOffset3D; -+ gctUINT32 entryOffsetXDFrom2D; -+ gctUINT32 entryOffsetXDFrom3D; -+ -+ /* Dirty flags. */ -+ gctBOOL dirty; -+ gctBOOL dirty2D; -+ gctBOOL dirty3D; -+ gcsCONTEXT_PTR dirtyBuffer; -+ -+ /* State mapping. */ -+ gcsSTATE_MAP_PTR map; -+ -+ /* List of context buffers. */ -+ gcsCONTEXT_PTR buffer; -+ -+ /* A copy of the user record array. */ -+ gctUINT recordArraySize; -+#if REMOVE_DUPLICATED_COPY_FROM_USER -+ gcsRECORD_ARRAY_MAP_PTR recordArrayMap; -+#else -+ gcsSTATE_DELTA_RECORD_PTR recordArray; -+#endif -+ -+ /* Requested pipe select for context. */ -+ gcePIPE_SELECT entryPipe; -+ gcePIPE_SELECT exitPipe; -+ -+ /* Variables used for building state buffer. */ -+ gctUINT32 lastAddress; -+ gctSIZE_T lastSize; -+ gctUINT32 lastIndex; -+ gctBOOL lastFixed; -+ -+ gctUINT32 pipeSelectBytes; -+ -+#if VIVANTE_PROFILER_CONTEXT -+ gcsPROFILER_COUNTERS latestProfiler; -+ gcsPROFILER_COUNTERS histroyProfiler; -+ gctUINT32 prevVSInstCount; -+ gctUINT32 prevVSBranchInstCount; -+ gctUINT32 prevVSTexInstCount; -+ gctUINT32 prevVSVertexCount; -+ gctUINT32 prevPSInstCount; -+ gctUINT32 prevPSBranchInstCount; -+ gctUINT32 prevPSTexInstCount; -+ gctUINT32 prevPSPixelCount; -+#endif -+}; -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* __gc_hal_kernel_context_h_ */ -+ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/arch/gc_hal_kernel_hardware.c linux-4.1.13/drivers/gpu/galcore/arch/gc_hal_kernel_hardware.c ---- linux-4.1.13.orig/drivers/gpu/galcore/arch/gc_hal_kernel_hardware.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/arch/gc_hal_kernel_hardware.c 2015-11-30 17:56:13.560139057 +0100 -@@ -0,0 +1,7719 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#include "gc_hal.h" -+#include "gc_hal_kernel.h" -+#if VIVANTE_PROFILER_CONTEXT -+#include "gc_hal_kernel_context.h" -+#endif -+ -+#define gcdDISABLE_FE_L2 1 -+ -+#define _GC_OBJ_ZONE gcvZONE_HARDWARE -+ -+#define gcmSEMAPHORESTALL(buffer) \ -+ do \ -+ { \ -+ /* Arm the PE-FE Semaphore. */ \ -+ *buffer++ \ -+ = gcmSETFIELDVALUE(0, AQ_COMMAND_LOAD_STATE_COMMAND, OPCODE, LOAD_STATE) \ -+ | gcmSETFIELD (0, AQ_COMMAND_LOAD_STATE_COMMAND, COUNT, 1) \ -+ | gcmSETFIELD (0, AQ_COMMAND_LOAD_STATE_COMMAND, ADDRESS, 0x0E02); \ -+ \ -+ *buffer++ \ -+ = gcmSETFIELDVALUE(0, AQ_SEMAPHORE, SOURCE, FRONT_END) \ -+ | gcmSETFIELDVALUE(0, AQ_SEMAPHORE, DESTINATION, PIXEL_ENGINE);\ -+ \ -+ /* STALL FE until PE is done flushing. */ \ -+ *buffer++ \ -+ = gcmSETFIELDVALUE(0, STALL_COMMAND, OPCODE, STALL); \ -+ \ -+ *buffer++ \ -+ = gcmSETFIELDVALUE(0, STALL_STALL, SOURCE, FRONT_END) \ -+ | gcmSETFIELDVALUE(0, STALL_STALL, DESTINATION, PIXEL_ENGINE); \ -+ } while(0) -+ -+typedef struct _gcsiDEBUG_REGISTERS * gcsiDEBUG_REGISTERS_PTR; -+typedef struct _gcsiDEBUG_REGISTERS -+{ -+ gctSTRING module; -+ gctUINT index; -+ gctUINT shift; -+ gctUINT data; -+ gctUINT count; -+ gctUINT32 signature; -+} -+gcsiDEBUG_REGISTERS; -+ -+/******************************************************************************\ -+********************************* Support Code ********************************* -+\******************************************************************************/ -+static gctBOOL -+_IsHardwareMatch( -+ IN gckHARDWARE Hardware, -+ IN gctINT32 ChipModel, -+ IN gctUINT32 ChipRevision -+ ) -+{ -+ return ((Hardware->identity.chipModel == ChipModel) && -+ (Hardware->identity.chipRevision == ChipRevision)); -+} -+ -+static gceSTATUS -+_ResetGPU( -+ IN gckHARDWARE Hardware, -+ IN gckOS Os, -+ IN gceCORE Core -+ ); -+ -+static gceSTATUS -+_IdentifyHardware( -+ IN gckOS Os, -+ IN gceCORE Core, -+ OUT gcsHAL_QUERY_CHIP_IDENTITY_PTR Identity -+ ) -+{ -+ gceSTATUS status; -+ -+ gctUINT32 chipIdentity; -+ -+ gctUINT32 streamCount = 0; -+ gctUINT32 registerMax = 0; -+ gctUINT32 threadCount = 0; -+ gctUINT32 shaderCoreCount = 0; -+ gctUINT32 vertexCacheSize = 0; -+ gctUINT32 vertexOutputBufferSize = 0; -+ gctUINT32 pixelPipes = 0; -+ gctUINT32 instructionCount = 0; -+ gctUINT32 numConstants = 0; -+ gctUINT32 bufferSize = 0; -+ gctUINT32 varyingsCount = 0; -+ -+ gcmkHEADER_ARG("Os=0x%x", Os); -+ -+ /*************************************************************************** -+ ** Get chip ID and revision. -+ */ -+ -+ /* Read chip identity register. */ -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Os, Core, -+ 0x00018, -+ &chipIdentity)); -+ -+ /* Special case for older graphic cores. */ -+ if (((((gctUINT32) (chipIdentity)) >> (0 ? 31:24) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1)))))) == (0x01 & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1)))))))) -+ { -+ Identity->chipModel = gcv500; -+ Identity->chipRevision = (((((gctUINT32) (chipIdentity)) >> (0 ? 15:12)) & ((gctUINT32) ((((1 ? 15:12) - (0 ? 15:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:12) - (0 ? 15:12) + 1)))))) ); -+ } -+ -+ else -+ { -+ /* Read chip identity register. */ -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Os, Core, -+ 0x00020, -+ (gctUINT32_PTR) &Identity->chipModel)); -+ -+ if (((Identity->chipModel & 0xFF00) == 0x0400) -+ && (Identity->chipModel != 0x0420) -+ && (Identity->chipModel != 0x0428)) -+ { -+ Identity->chipModel = (gceCHIPMODEL) (Identity->chipModel & 0x0400); -+ } -+ -+ /* Read CHIP_REV register. */ -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Os, Core, -+ 0x00024, -+ &Identity->chipRevision)); -+ -+ if ((Identity->chipModel == gcv300) -+ && (Identity->chipRevision == 0x2201) -+ ) -+ { -+ gctUINT32 chipDate; -+ gctUINT32 chipTime; -+ -+ /* Read date and time registers. */ -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Os, Core, -+ 0x00028, -+ &chipDate)); -+ -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Os, Core, -+ 0x0002C, -+ &chipTime)); -+ -+ if ((chipDate == 0x20080814) && (chipTime == 0x12051100)) -+ { -+ /* This IP has an ECO; put the correct revision in it. */ -+ Identity->chipRevision = 0x1051; -+ } -+ } -+ -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Os, Core, -+ 0x000A8, -+ &Identity->productID)); -+ } -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "Identity: chipModel=%X", -+ Identity->chipModel); -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "Identity: chipRevision=%X", -+ Identity->chipRevision); -+ -+ -+ /*************************************************************************** -+ ** Get chip features. -+ */ -+ -+ /* Read chip feature register. */ -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Os, Core, -+ 0x0001C, -+ &Identity->chipFeatures)); -+ -+#if gcdENABLE_3D -+ /* Disable fast clear on GC700. */ -+ if (Identity->chipModel == gcv700) -+ { -+ Identity->chipFeatures -+ = ((((gctUINT32) (Identity->chipFeatures)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))); -+ } -+#endif -+ -+ if (((Identity->chipModel == gcv500) && (Identity->chipRevision < 2)) -+ || ((Identity->chipModel == gcv300) && (Identity->chipRevision < 0x2000)) -+ ) -+ { -+ /* GC500 rev 1.x and GC300 rev < 2.0 doesn't have these registers. */ -+ Identity->chipMinorFeatures = 0; -+ Identity->chipMinorFeatures1 = 0; -+ Identity->chipMinorFeatures2 = 0; -+ Identity->chipMinorFeatures3 = 0; -+ Identity->chipMinorFeatures4 = 0; -+ Identity->chipMinorFeatures5 = 0; -+ } -+ else -+ { -+ /* Read chip minor feature register #0. */ -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Os, Core, -+ 0x00034, -+ &Identity->chipMinorFeatures)); -+ -+ if (((((gctUINT32) (Identity->chipMinorFeatures)) >> (0 ? 21:21) & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1))))))) -+ ) -+ { -+ /* Read chip minor featuress register #1. */ -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Os, Core, -+ 0x00074, -+ &Identity->chipMinorFeatures1)); -+ -+ /* Read chip minor featuress register #2. */ -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Os, Core, -+ 0x00084, -+ &Identity->chipMinorFeatures2)); -+ -+ /*Identity->chipMinorFeatures2 &= ~(0x1 << 3);*/ -+ -+ /* Read chip minor featuress register #1. */ -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Os, Core, -+ 0x00088, -+ &Identity->chipMinorFeatures3)); -+ -+ -+ /* Read chip minor featuress register #4. */ -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Os, Core, -+ 0x00094, -+ &Identity->chipMinorFeatures4)); -+ -+ /* Read chip minor featuress register #5. */ -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Os, Core, -+ 0x000A0, -+ &Identity->chipMinorFeatures5)); -+ } -+ else -+ { -+ /* Chip doesn't has minor features register #1 or 2 or 3 or 4. */ -+ Identity->chipMinorFeatures1 = 0; -+ Identity->chipMinorFeatures2 = 0; -+ Identity->chipMinorFeatures3 = 0; -+ Identity->chipMinorFeatures4 = 0; -+ Identity->chipMinorFeatures5 = 0; -+ } -+ } -+ -+ /* Get the Supertile layout in the hardware. */ -+ if (((((gctUINT32) (Identity->chipMinorFeatures3)) >> (0 ? 26:26) & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1))))))) -+ || ((((gctUINT32) (Identity->chipMinorFeatures3)) >> (0 ? 8:8) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1)))))))) -+ { -+ Identity->superTileMode = 2; -+ } -+ else if (((((gctUINT32) (Identity->chipMinorFeatures)) >> (0 ? 27:27) & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1)))))))) -+ { -+ Identity->superTileMode = 1; -+ } -+ else -+ { -+ Identity->superTileMode = 0; -+ } -+ -+ /* Exception for GC1000, revision 5035 & GC800, revision 4612 */ -+ if (((Identity->chipModel == gcv1000) && ((Identity->chipRevision == 0x5035) -+ || (Identity->chipRevision == 0x5036) -+ || (Identity->chipRevision == 0x5037) -+ || (Identity->chipRevision == 0x5039) -+ || (Identity->chipRevision >= 0x5040))) -+ || ((Identity->chipModel == gcv800) && (Identity->chipRevision == 0x4612)) -+ || ((Identity->chipModel == gcv600) && (Identity->chipRevision >= 0x4650)) -+ || ((Identity->chipModel == gcv860) && (Identity->chipRevision == 0x4647)) -+ || ((Identity->chipModel == gcv400) && (Identity->chipRevision >= 0x4633))) -+ { -+ Identity->superTileMode = 1; -+ } -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "Identity: chipFeatures=0x%08X", -+ Identity->chipFeatures); -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "Identity: chipMinorFeatures=0x%08X", -+ Identity->chipMinorFeatures); -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "Identity: chipMinorFeatures1=0x%08X", -+ Identity->chipMinorFeatures1); -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "Identity: chipMinorFeatures2=0x%08X", -+ Identity->chipMinorFeatures2); -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "Identity: chipMinorFeatures3=0x%08X", -+ Identity->chipMinorFeatures3); -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "Identity: chipMinorFeatures4=0x%08X", -+ Identity->chipMinorFeatures4); -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "Identity: chipMinorFeatures5=0x%08X", -+ Identity->chipMinorFeatures5); -+ -+ /*************************************************************************** -+ ** Get chip specs. -+ */ -+ -+ if (((((gctUINT32) (Identity->chipMinorFeatures)) >> (0 ? 21:21) & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1)))))))) -+ { -+ gctUINT32 specs, specs2, specs3, specs4; -+ -+ /* Read gcChipSpecs register. */ -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Os, Core, -+ 0x00048, -+ &specs)); -+ -+ /* Extract the fields. */ -+ registerMax = (((((gctUINT32) (specs)) >> (0 ? 7:4)) & ((gctUINT32) ((((1 ? 7:4) - (0 ? 7:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:4) - (0 ? 7:4) + 1)))))) ); -+ threadCount = (((((gctUINT32) (specs)) >> (0 ? 11:8)) & ((gctUINT32) ((((1 ? 11:8) - (0 ? 11:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:8) - (0 ? 11:8) + 1)))))) ); -+ shaderCoreCount = (((((gctUINT32) (specs)) >> (0 ? 24:20)) & ((gctUINT32) ((((1 ? 24:20) - (0 ? 24:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:20) - (0 ? 24:20) + 1)))))) ); -+ vertexCacheSize = (((((gctUINT32) (specs)) >> (0 ? 16:12)) & ((gctUINT32) ((((1 ? 16:12) - (0 ? 16:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:12) - (0 ? 16:12) + 1)))))) ); -+ vertexOutputBufferSize = (((((gctUINT32) (specs)) >> (0 ? 31:28)) & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1)))))) ); -+ pixelPipes = (((((gctUINT32) (specs)) >> (0 ? 27:25)) & ((gctUINT32) ((((1 ? 27:25) - (0 ? 27:25) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:25) - (0 ? 27:25) + 1)))))) ); -+ -+ /* Read gcChipSpecs2 register. */ -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Os, Core, -+ 0x00080, -+ &specs2)); -+ -+ instructionCount = (((((gctUINT32) (specs2)) >> (0 ? 15:8)) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1)))))) ); -+ numConstants = (((((gctUINT32) (specs2)) >> (0 ? 31:16)) & ((gctUINT32) ((((1 ? 31:16) - (0 ? 31:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:16) - (0 ? 31:16) + 1)))))) ); -+ bufferSize = (((((gctUINT32) (specs2)) >> (0 ? 7:0)) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1)))))) ); -+ -+ /* Read gcChipSpecs3 register. */ -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Os, Core, -+ 0x0008C, -+ &specs3)); -+ -+ varyingsCount = (((((gctUINT32) (specs3)) >> (0 ? 8:4)) & ((gctUINT32) ((((1 ? 8:4) - (0 ? 8:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:4) - (0 ? 8:4) + 1)))))) ); -+ -+ /* Read gcChipSpecs4 register. */ -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Os, Core, -+ 0x0009C, -+ &specs4)); -+ -+ -+ streamCount = (((((gctUINT32) (specs4)) >> (0 ? 16:12)) & ((gctUINT32) ((((1 ? 16:12) - (0 ? 16:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:12) - (0 ? 16:12) + 1)))))) ); -+ if (streamCount == 0) -+ { -+ /* Extract stream count from older register. */ -+ streamCount = (((((gctUINT32) (specs)) >> (0 ? 3:0)) & ((gctUINT32) ((((1 ? 3:0) - (0 ? 3:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:0) - (0 ? 3:0) + 1)))))) ); -+ } -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "Identity: chipSpecs1=0x%08X", -+ specs); -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "Identity: chipSpecs2=0x%08X", -+ specs2); -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "Identity: chipSpecs3=0x%08X", -+ specs3); -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "Identity: chipSpecs4=0x%08X", -+ specs4); -+ } -+ -+ /* Get the number of pixel pipes. */ -+ Identity->pixelPipes = gcmMAX(pixelPipes, 1); -+ -+ /* Get the stream count. */ -+ Identity->streamCount = (streamCount != 0) -+ ? streamCount -+ : (Identity->chipModel >= gcv1000) ? 4 : 1; -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "Specs: streamCount=%u%s", -+ Identity->streamCount, -+ (streamCount == 0) ? " (default)" : ""); -+ -+ /* Get the vertex output buffer size. */ -+ Identity->vertexOutputBufferSize = (vertexOutputBufferSize != 0) -+ ? 1 << vertexOutputBufferSize -+ : (Identity->chipModel == gcv400) -+ ? (Identity->chipRevision < 0x4000) ? 512 -+ : (Identity->chipRevision < 0x4200) ? 256 -+ : 128 -+ : (Identity->chipModel == gcv530) -+ ? (Identity->chipRevision < 0x4200) ? 512 -+ : 128 -+ : 512; -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "Specs: vertexOutputBufferSize=%u%s", -+ Identity->vertexOutputBufferSize, -+ (vertexOutputBufferSize == 0) ? " (default)" : ""); -+ -+ /* Get the maximum number of threads. */ -+ Identity->threadCount = (threadCount != 0) -+ ? 1 << threadCount -+ : (Identity->chipModel == gcv400) ? 64 -+ : (Identity->chipModel == gcv500) ? 128 -+ : (Identity->chipModel == gcv530) ? 128 -+ : 256; -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "Specs: threadCount=%u%s", -+ Identity->threadCount, -+ (threadCount == 0) ? " (default)" : ""); -+ -+ /* Get the number of shader cores. */ -+ Identity->shaderCoreCount = (shaderCoreCount != 0) -+ ? shaderCoreCount -+ : (Identity->chipModel >= gcv1000) ? 2 -+ : 1; -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "Specs: shaderCoreCount=%u%s", -+ Identity->shaderCoreCount, -+ (shaderCoreCount == 0) ? " (default)" : ""); -+ -+ /* Get the vertex cache size. */ -+ Identity->vertexCacheSize = (vertexCacheSize != 0) -+ ? vertexCacheSize -+ : 8; -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "Specs: vertexCacheSize=%u%s", -+ Identity->vertexCacheSize, -+ (vertexCacheSize == 0) ? " (default)" : ""); -+ -+ /* Get the maximum number of temporary registers. */ -+ Identity->registerMax = (registerMax != 0) -+ /* Maximum of registerMax/4 registers are accessible to 1 shader */ -+ ? 1 << registerMax -+ : (Identity->chipModel == gcv400) ? 32 -+ : 64; -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "Specs: registerMax=%u%s", -+ Identity->registerMax, -+ (registerMax == 0) ? " (default)" : ""); -+ -+ /* Get the instruction count. */ -+ Identity->instructionCount = (instructionCount == 0) ? 256 -+ : (instructionCount == 1) ? 1024 -+ : (instructionCount == 2) ? 2048 -+ : (instructionCount == 0xFF) ? 512 -+ : 256; -+ -+ if (Identity->instructionCount == 256) -+ { -+ if ((Identity->chipModel == gcv2000 && Identity->chipRevision == 0x5108) -+ || Identity->chipModel == gcv880) -+ { -+ Identity->instructionCount = 512; -+ } -+ else if (((((gctUINT32) (Identity->chipMinorFeatures3)) >> (0 ? 3:3) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))))) -+ { -+ Identity->instructionCount = 512; -+ } -+ } -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "Specs: instructionCount=%u%s", -+ Identity->instructionCount, -+ (instructionCount == 0) ? " (default)" : ""); -+ -+ /* Get the number of constants. */ -+ Identity->numConstants = (numConstants == 0) ? 168 : numConstants; -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "Specs: numConstants=%u%s", -+ Identity->numConstants, -+ (numConstants == 0) ? " (default)" : ""); -+ -+ /* Get the buffer size. */ -+ Identity->bufferSize = bufferSize; -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "Specs: bufferSize=%u%s", -+ Identity->bufferSize, -+ (bufferSize == 0) ? " (default)" : ""); -+ -+ -+ if (varyingsCount != 0) -+ { -+ Identity->varyingsCount = varyingsCount; -+ } -+ else if (((((gctUINT32) (Identity->chipMinorFeatures1)) >> (0 ? 23:23) & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1)))))))) -+ { -+ Identity->varyingsCount = 12; -+ } -+ else -+ { -+ Identity->varyingsCount = 8; -+ } -+ -+ /* For some cores, it consumes two varying for position, so the max varying vectors should minus one. */ -+ if ((Identity->chipModel == gcv5000 && Identity->chipRevision == 0x5434) || -+ (Identity->chipModel == gcv4000 && Identity->chipRevision == 0x5222) || -+ (Identity->chipModel == gcv4000 && Identity->chipRevision == 0x5208) || -+ (Identity->chipModel == gcv4000 && Identity->chipRevision == 0x5245) || -+ (Identity->chipModel == gcv3000 && Identity->chipRevision == 0x5435) || -+ (Identity->chipModel == gcv2200 && Identity->chipRevision == 0x5244) || -+ (Identity->chipModel == gcv1500 && Identity->chipRevision == 0x5246) || -+ ((Identity->chipModel == gcv2100 || Identity->chipModel == gcv2000) && Identity->chipRevision == 0x5108) || -+ (Identity->chipModel == gcv880 && (Identity->chipRevision == 0x5107 || Identity->chipRevision == 0x5106))) -+ { -+ Identity->varyingsCount -= 1; -+ } -+ -+ Identity->chip2DControl = 0; -+ if (Identity->chipModel == gcv320) -+ { -+ gctUINT32 data; -+ -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Os, -+ Core, -+ 0x0002C, -+ &data)); -+ -+ if ((data != 33956864) && -+ ((Identity->chipRevision == 0x5007) || -+ (Identity->chipRevision == 0x5220))) -+ { -+ Identity->chip2DControl |= 0xFF & -+ (Identity->chipRevision == 0x5220 ? 8 : -+ (Identity->chipRevision == 0x5007 ? 12 : 0)); -+ } -+ -+ if (Identity->chipRevision == 0x5007) -+ { -+ /* Disable splitting rectangle. */ -+ Identity->chip2DControl |= 0x100; -+ -+ /* Enable 2D Flush. */ -+ Identity->chip2DControl |= 0x200; -+ } -+ } -+ -+ /* Success. */ -+ gcmkFOOTER(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+#define gcdDEBUG_MODULE_CLOCK_GATING 0 -+#define gcdDISABLE_MODULE_CLOCK_GATING 0 -+#define gcdDISABLE_FE_CLOCK_GATING 0 -+#define gcdDISABLE_PE_CLOCK_GATING 0 -+#define gcdDISABLE_SH_CLOCK_GATING 0 -+#define gcdDISABLE_PA_CLOCK_GATING 0 -+#define gcdDISABLE_SE_CLOCK_GATING 0 -+#define gcdDISABLE_RA_CLOCK_GATING 0 -+#define gcdDISABLE_RA_EZ_CLOCK_GATING 0 -+#define gcdDISABLE_RA_HZ_CLOCK_GATING 0 -+#define gcdDISABLE_TX_CLOCK_GATING 0 -+ -+#if gcdDEBUG_MODULE_CLOCK_GATING -+gceSTATUS -+_ConfigureModuleLevelClockGating( -+ gckHARDWARE Hardware -+ ) -+{ -+ gctUINT32 data; -+ -+ gcmkVERIFY_OK( -+ gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ Hardware->powerBaseAddress -+ + 0x00104, -+ &data)); -+ -+#if gcdDISABLE_FE_CLOCK_GATING -+ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))); -+#endif -+ -+#if gcdDISABLE_PE_CLOCK_GATING -+ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))); -+#endif -+ -+#if gcdDISABLE_SH_CLOCK_GATING -+ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))); -+#endif -+ -+#if gcdDISABLE_PA_CLOCK_GATING -+ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))); -+#endif -+ -+#if gcdDISABLE_SE_CLOCK_GATING -+ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))); -+#endif -+ -+#if gcdDISABLE_RA_CLOCK_GATING -+ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))); -+#endif -+ -+#if gcdDISABLE_TX_CLOCK_GATING -+ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))); -+#endif -+ -+#if gcdDISABLE_RA_EZ_CLOCK_GATING -+ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))); -+#endif -+ -+#if gcdDISABLE_RA_HZ_CLOCK_GATING -+ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17))); -+#endif -+ -+ gcmkVERIFY_OK( -+ gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ Hardware->powerBaseAddress -+ + 0x00104, -+ data)); -+ -+#if gcdDISABLE_MODULE_CLOCK_GATING -+ gcmkVERIFY_OK( -+ gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ Hardware->powerBaseAddress + -+ 0x00100, -+ &data)); -+ -+ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))); -+ -+ -+ gcmkVERIFY_OK( -+ gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ Hardware->powerBaseAddress -+ + 0x00100, -+ data)); -+#endif -+ -+ return gcvSTATUS_OK; -+} -+#endif -+ -+#if gcdPOWEROFF_TIMEOUT -+void -+_PowerTimerFunction( -+ gctPOINTER Data -+ ) -+{ -+ gckHARDWARE hardware = (gckHARDWARE)Data; -+ gcmkVERIFY_OK( -+ gckHARDWARE_SetPowerManagementState(hardware, gcvPOWER_OFF_TIMEOUT)); -+} -+#endif -+ -+static gceSTATUS -+_VerifyDMA( -+ IN gckOS Os, -+ IN gceCORE Core, -+ gctUINT32_PTR Address1, -+ gctUINT32_PTR Address2, -+ gctUINT32_PTR State1, -+ gctUINT32_PTR State2 -+ ) -+{ -+ gceSTATUS status; -+ gctUINT32 i; -+ -+ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, 0x660, State1)); -+ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, 0x664, Address1)); -+ -+ for (i = 0; i < 500; i += 1) -+ { -+ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, 0x660, State2)); -+ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, 0x664, Address2)); -+ -+ if (*Address1 != *Address2) -+ { -+ break; -+ } -+ -+ if (*State1 != *State2) -+ { -+ break; -+ } -+ } -+ -+OnError: -+ return status; -+} -+ -+static gceSTATUS -+_DumpDebugRegisters( -+ IN gckOS Os, -+ IN gceCORE Core, -+ IN gcsiDEBUG_REGISTERS_PTR Descriptor -+ ) -+{ -+ gceSTATUS status = gcvSTATUS_OK; -+ gctUINT32 select; -+ gctUINT32 data = 0; -+ gctUINT i; -+ -+ gcmkHEADER_ARG("Os=0x%X Descriptor=0x%X", Os, Descriptor); -+ -+ gcmkPRINT_N(4, " %s debug registers:\n", Descriptor->module); -+ -+ for (i = 0; i < Descriptor->count; i += 1) -+ { -+ select = i << Descriptor->shift; -+ -+ gcmkONERROR(gckOS_WriteRegisterEx(Os, Core, Descriptor->index, select)); -+#if gcdFPGA_BUILD -+ gcmkONERROR(gckOS_Delay(Os, 1000)); -+#endif -+ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, Descriptor->data, &data)); -+ -+ gcmkPRINT_N(12, " [0x%02X] 0x%08X\n", i, data); -+ } -+ -+ select = 0xF << Descriptor->shift; -+ -+ for (i = 0; i < 500; i += 1) -+ { -+ gcmkONERROR(gckOS_WriteRegisterEx(Os, Core, Descriptor->index, select)); -+#if gcdFPGA_BUILD -+ gcmkONERROR(gckOS_Delay(Os, 1000)); -+#endif -+ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, Descriptor->data, &data)); -+ -+ if (data == Descriptor->signature) -+ { -+ break; -+ } -+ } -+ -+ if (i == 500) -+ { -+ gcmkPRINT_N(4, " failed to obtain the signature (read 0x%08X).\n", data); -+ } -+ else -+ { -+ gcmkPRINT_N(8, " signature = 0x%08X (%d read attempt(s))\n", data, i + 1); -+ } -+ -+OnError: -+ /* Return the error. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+static gceSTATUS -+_IsGPUPresent( -+ IN gckHARDWARE Hardware -+ ) -+{ -+ gceSTATUS status; -+ gctUINT32 control; -+ -+ gcmkHEADER_ARG("Hardware=0x%x", Hardware); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00000, -+ &control)); -+ -+ control = ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))); -+ control = ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))); -+ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00000, -+ control)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the error. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+_FlushCache( -+ gckHARDWARE Hardware, -+ gckCOMMAND Command -+ ) -+{ -+ gceSTATUS status; -+ gctUINT32 bytes, requested; -+ gctPOINTER buffer; -+ -+ /* Get the size of the flush command. */ -+ gcmkONERROR(gckHARDWARE_Flush(Hardware, -+ gcvFLUSH_ALL, -+ gcvNULL, -+ &requested)); -+ -+ /* Reserve space in the command queue. */ -+ gcmkONERROR(gckCOMMAND_Reserve(Command, -+ requested, -+ &buffer, -+ &bytes)); -+ -+ /* Append a flush. */ -+ gcmkONERROR(gckHARDWARE_Flush( -+ Hardware, gcvFLUSH_ALL, buffer, &bytes -+ )); -+ -+ /* Execute the command queue. */ -+ gcmkONERROR(gckCOMMAND_Execute(Command, requested)); -+ -+ return gcvSTATUS_OK; -+ -+OnError: -+ return status; -+} -+ -+gctBOOL -+_IsGPUIdle( -+ IN gctUINT32 Idle -+ ) -+{ -+ return (((((gctUINT32) (Idle)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ) -+ && (((((gctUINT32) (Idle)) >> (0 ? 1:1)) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1)))))) ) -+ && (((((gctUINT32) (Idle)) >> (0 ? 3:3)) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))) ) -+ && (((((gctUINT32) (Idle)) >> (0 ? 4:4)) & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1)))))) ) -+ && (((((gctUINT32) (Idle)) >> (0 ? 5:5)) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1)))))) ) -+ && (((((gctUINT32) (Idle)) >> (0 ? 6:6)) & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1)))))) ) -+ && (((((gctUINT32) (Idle)) >> (0 ? 7:7)) & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1)))))) ) -+ && (((((gctUINT32) (Idle)) >> (0 ? 2:2)) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))) ) -+ ; -+} -+ -+/******************************************************************************\ -+****************************** gckHARDWARE API code ***************************** -+\******************************************************************************/ -+ -+/******************************************************************************* -+** -+** gckHARDWARE_Construct -+** -+** Construct a new gckHARDWARE object. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an initialized gckOS object. -+** -+** gceCORE Core -+** Specified core. -+** -+** OUTPUT: -+** -+** gckHARDWARE * Hardware -+** Pointer to a variable that will hold the pointer to the gckHARDWARE -+** object. -+*/ -+gceSTATUS -+gckHARDWARE_Construct( -+ IN gckOS Os, -+ IN gceCORE Core, -+ OUT gckHARDWARE * Hardware -+ ) -+{ -+ gceSTATUS status; -+ gckHARDWARE hardware = gcvNULL; -+ gctUINT16 data = 0xff00; -+ gctPOINTER pointer = gcvNULL; -+ -+ gcmkHEADER_ARG("Os=0x%x", Os); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Hardware != gcvNULL); -+ -+ /* Enable the GPU. */ -+ gcmkONERROR(gckOS_SetGPUPower(Os, Core, gcvTRUE, gcvTRUE)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Os, -+ Core, -+ 0x00000, -+ 0x00000900)); -+ -+ /* Allocate the gckHARDWARE object. */ -+ gcmkONERROR(gckOS_Allocate(Os, -+ gcmSIZEOF(struct _gckHARDWARE), -+ &pointer)); -+ -+ hardware = (gckHARDWARE) pointer; -+ -+ /* Initialize the gckHARDWARE object. */ -+ hardware->object.type = gcvOBJ_HARDWARE; -+ hardware->os = Os; -+ hardware->core = Core; -+ -+ /* Identify the hardware. */ -+ gcmkONERROR(_IdentifyHardware(Os, Core, &hardware->identity)); -+ -+ /* Determine the hardware type */ -+ switch (hardware->identity.chipModel) -+ { -+ case gcv350: -+ case gcv355: -+ hardware->type = gcvHARDWARE_VG; -+ break; -+ -+ case gcv200: -+ case gcv300: -+ case gcv320: -+ case gcv328: -+ case gcv420: -+ case gcv428: -+ hardware->type = gcvHARDWARE_2D; -+ break; -+ -+ default: -+ hardware->type = gcvHARDWARE_3D; -+ -+ if(hardware->identity.chipModel == gcv880 && hardware->identity.chipRevision == 0x5107) -+ { -+ /*set outstanding limit*/ -+ gctUINT32 axi_ot; -+ gcmkONERROR(gckOS_ReadRegisterEx(Os, Core, 0x00414, &axi_ot)); -+ axi_ot = (axi_ot & (~0xFF)) | 0x00010; -+ gcmkONERROR(gckOS_WriteRegisterEx(Os, Core, 0x00414, axi_ot)); -+ } -+ -+ -+ if ((((((gctUINT32) (hardware->identity.chipFeatures)) >> (0 ? 9:9)) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) )) -+ { -+ hardware->type = (gceHARDWARE_TYPE) (hardware->type | gcvHARDWARE_2D); -+ } -+ } -+ -+ hardware->powerBaseAddress -+ = ((hardware->identity.chipModel == gcv300) -+ && (hardware->identity.chipRevision < 0x2000)) -+ ? 0x0100 -+ : 0x0000; -+ -+ /* _ResetGPU need powerBaseAddress. */ -+ status = _ResetGPU(hardware, Os, Core); -+ -+ if (status != gcvSTATUS_OK) -+ { -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "_ResetGPU failed: status=%d\n", status); -+ } -+ -+ hardware->powerMutex = gcvNULL; -+ -+ hardware->mmuVersion -+ = (((((gctUINT32) (hardware->identity.chipMinorFeatures1)) >> (0 ? 28:28)) & ((gctUINT32) ((((1 ? 28:28) - (0 ? 28:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 28:28) - (0 ? 28:28) + 1)))))) ); -+ -+ /* Determine whether bug fixes #1 are present. */ -+ hardware->extraEventStates = ((((gctUINT32) (hardware->identity.chipMinorFeatures1)) >> (0 ? 3:3) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))) == (0x0 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))); -+ -+ /* Check if big endian */ -+ hardware->bigEndian = (*(gctUINT8 *)&data == 0xff); -+ -+ /* Initialize the fast clear. */ -+ gcmkONERROR(gckHARDWARE_SetFastClear(hardware, -1, -1)); -+ -+#if !gcdENABLE_128B_MERGE -+ -+ if (((((gctUINT32) (hardware->identity.chipMinorFeatures2)) >> (0 ? 21:21) & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1)))))))) -+ { -+ /* 128B merge is turned on by default. Disable it. */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Os, Core, 0x00558, 0)); -+ } -+ -+#endif -+ -+ /* Set power state to ON. */ -+ hardware->chipPowerState = gcvPOWER_ON; -+ hardware->clockState = gcvTRUE; -+ hardware->powerState = gcvTRUE; -+ hardware->lastWaitLink = ~0U; -+ hardware->lastEnd = ~0U; -+ hardware->globalSemaphore = gcvNULL; -+#if gcdENABLE_FSCALE_VAL_ADJUST -+ hardware->powerOnFscaleVal = 64; -+#endif -+ -+ gcmkONERROR(gckOS_CreateMutex(Os, &hardware->powerMutex)); -+ gcmkONERROR(gckOS_CreateSemaphore(Os, &hardware->globalSemaphore)); -+ hardware->startIsr = gcvNULL; -+ hardware->stopIsr = gcvNULL; -+ -+#if gcdPOWEROFF_TIMEOUT -+ hardware->powerOffTimeout = gcdPOWEROFF_TIMEOUT; -+ -+ gcmkVERIFY_OK(gckOS_CreateTimer(Os, -+ _PowerTimerFunction, -+ (gctPOINTER)hardware, -+ &hardware->powerOffTimer)); -+#endif -+ -+ gcmkONERROR(gckOS_AtomConstruct(Os, &hardware->pageTableDirty)); -+ gcmkONERROR(gckOS_AtomConstruct(Os, &hardware->pendingEvent)); -+ -+#if gcdLINK_QUEUE_SIZE -+ hardware->linkQueue.front = 0; -+ hardware->linkQueue.rear = 0; -+ hardware->linkQueue.count = 0; -+#endif -+ -+ /* Enable power management by default. */ -+ hardware->powerManagement = gcvTRUE; -+ -+ /* Disable profiler by default */ -+ hardware->gpuProfiler = gcvFALSE; -+ -+ if (hardware->mmuVersion) -+ { -+ hardware->endAfterFlushMmuCache = gcvTRUE; -+ } -+ else -+ { -+ hardware->endAfterFlushMmuCache = gcvFALSE; -+ } -+ -+ gcmkONERROR(gckOS_QueryOption(Os, "mmu", (gctUINT32_PTR)&hardware->enableMMU)); -+ -+ hardware->minFscaleValue = 1; -+ -+ /* Return pointer to the gckHARDWARE object. */ -+ *Hardware = hardware; -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Hardware=0x%x", *Hardware); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Roll back. */ -+ if (hardware != gcvNULL) -+ { -+ /* Turn off the power. */ -+ gcmkVERIFY_OK(gckOS_SetGPUPower(Os, Core, gcvFALSE, gcvFALSE)); -+ -+ if (hardware->globalSemaphore != gcvNULL) -+ { -+ /* Destroy the global semaphore. */ -+ gcmkVERIFY_OK(gckOS_DestroySemaphore(Os, -+ hardware->globalSemaphore)); -+ } -+ -+ if (hardware->powerMutex != gcvNULL) -+ { -+ /* Destroy the power mutex. */ -+ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, hardware->powerMutex)); -+ } -+ -+#if gcdPOWEROFF_TIMEOUT -+ if (hardware->powerOffTimer != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckOS_StopTimer(Os, hardware->powerOffTimer)); -+ gcmkVERIFY_OK(gckOS_DestroyTimer(Os, hardware->powerOffTimer)); -+ } -+#endif -+ -+ if (hardware->pageTableDirty != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckOS_AtomDestroy(Os, hardware->pageTableDirty)); -+ } -+ -+ if (hardware->pendingEvent != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckOS_AtomDestroy(Os, hardware->pendingEvent)); -+ } -+ -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Os, hardware)); -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckHARDWARE_Destroy -+** -+** Destroy an gckHARDWARE object. -+** -+** INPUT: -+** -+** gckHARDWARE Hardware -+** Pointer to the gckHARDWARE object that needs to be destroyed. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckHARDWARE_Destroy( -+ IN gckHARDWARE Hardware -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Hardware=0x%x", Hardware); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ /* Destroy the power semaphore. */ -+ gcmkVERIFY_OK(gckOS_DestroySemaphore(Hardware->os, -+ Hardware->globalSemaphore)); -+ -+ /* Destroy the power mutex. */ -+ gcmkVERIFY_OK(gckOS_DeleteMutex(Hardware->os, Hardware->powerMutex)); -+ -+#if gcdPOWEROFF_TIMEOUT -+ gcmkVERIFY_OK(gckOS_StopTimer(Hardware->os, Hardware->powerOffTimer)); -+ gcmkVERIFY_OK(gckOS_DestroyTimer(Hardware->os, Hardware->powerOffTimer)); -+#endif -+ -+ gcmkVERIFY_OK(gckOS_AtomDestroy(Hardware->os, Hardware->pageTableDirty)); -+ -+ gcmkVERIFY_OK(gckOS_AtomDestroy(Hardware->os, Hardware->pendingEvent)); -+ -+ gcmkVERIFY_OK(gckOS_FreeNonPagedMemory( -+ Hardware->os, -+ Hardware->functionBytes, -+ Hardware->functionPhysical, -+ Hardware->functionLogical -+ )); -+ -+ /* Mark the object as unknown. */ -+ Hardware->object.type = gcvOBJ_UNKNOWN; -+ -+ /* Free the object. */ -+ gcmkONERROR(gcmkOS_SAFE_FREE(Hardware->os, Hardware)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckHARDWARE_GetType -+** -+** Get the hardware type. -+** -+** INPUT: -+** -+** gckHARDWARE Harwdare -+** Pointer to an gckHARDWARE object. -+** -+** OUTPUT: -+** -+** gceHARDWARE_TYPE * Type -+** Pointer to a variable that receives the type of hardware object. -+*/ -+gceSTATUS -+gckHARDWARE_GetType( -+ IN gckHARDWARE Hardware, -+ OUT gceHARDWARE_TYPE * Type -+ ) -+{ -+ gcmkHEADER_ARG("Hardware=0x%x", Hardware); -+ gcmkVERIFY_ARGUMENT(Type != gcvNULL); -+ -+ *Type = Hardware->type; -+ -+ gcmkFOOTER_ARG("*Type=%d", *Type); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckHARDWARE_InitializeHardware -+** -+** Initialize the hardware. -+** -+** INPUT: -+** -+** gckHARDWARE Hardware -+** Pointer to the gckHARDWARE object. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckHARDWARE_InitializeHardware( -+ IN gckHARDWARE Hardware -+ ) -+{ -+ gceSTATUS status; -+ gctUINT32 baseAddress; -+ gctUINT32 chipRev; -+ gctUINT32 control; -+ gctUINT32 data; -+ gctUINT32 regPMC = 0; -+ -+ gcmkHEADER_ARG("Hardware=0x%x", Hardware); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ /* Read the chip revision register. */ -+ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00024, -+ &chipRev)); -+ -+ if (chipRev != Hardware->identity.chipRevision) -+ { -+ /* Chip is not there! */ -+ gcmkONERROR(gcvSTATUS_CONTEXT_LOSSED); -+ } -+ -+ /* Disable isolate GPU bit. */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00000, -+ ((((gctUINT32) (0x00000900)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))))); -+ -+ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00000, -+ &control)); -+ -+ /* Enable debug register. */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00000, -+ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1))))))) << (0 ? 11:11))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1))))))) << (0 ? 11:11))))); -+ -+ /* Reset memory counters. */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x0003C, -+ ~0U)); -+ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x0003C, -+ 0)); -+ -+ /* Get the system's physical base address. */ -+ gcmkONERROR(gckOS_GetBaseAddress(Hardware->os, &baseAddress)); -+ -+ /* Program the base addesses. */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x0041C, -+ baseAddress)); -+ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00418, -+ baseAddress)); -+ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00428, -+ baseAddress)); -+ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00420, -+ baseAddress)); -+ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00424, -+ baseAddress)); -+ -+ { -+ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ Hardware->powerBaseAddress + -+ 0x00100, -+ &data)); -+ -+ /* Enable clock gating. */ -+ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))); -+ -+ if ((Hardware->identity.chipRevision == 0x4301) -+ || (Hardware->identity.chipRevision == 0x4302) -+ ) -+ { -+ /* Disable stall module level clock gating for 4.3.0.1 and 4.3.0.2 -+ ** revisions. */ -+ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))); -+ } -+ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ Hardware->powerBaseAddress -+ + 0x00100, -+ data)); -+ -+#if gcdENABLE_3D -+ /* Disable PE clock gating on revs < 5.0 when HZ is present without a -+ ** bug fix. */ -+ if ((Hardware->identity.chipRevision < 0x5000) -+ && gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_HZ) -+ && ((((gctUINT32) (Hardware->identity.chipMinorFeatures1)) >> (0 ? 9:9) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) == (0x0 & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) -+ ) -+ { -+ if (regPMC == 0) -+ { -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ Hardware->powerBaseAddress -+ + 0x00104, -+ ®PMC)); -+ } -+ -+ /* Disable PE clock gating. */ -+ regPMC = ((((gctUINT32) (regPMC)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))); -+ } -+ -+#endif -+ } -+ -+ if (Hardware->identity.chipModel == gcv4000 && -+ ((Hardware->identity.chipRevision == 0x5208) || (Hardware->identity.chipRevision == 0x5222))) -+ { -+ gcmkONERROR( -+ gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x0010C, -+ ((((gctUINT32) (0x01590880)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1))))))) << (0 ? 23:23))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1))))))) << (0 ? 23:23))))); -+ } -+ -+ if (Hardware->identity.chipModel == gcv1000 && -+ (Hardware->identity.chipRevision == 0x5039 || -+ Hardware->identity.chipRevision == 0x5040)) -+ { -+ gctUINT32 pulseEater; -+ -+ pulseEater = ((((gctUINT32) (0x01590880)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))); -+ -+ gcmkONERROR( -+ gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x0010C, -+ ((((gctUINT32) (pulseEater)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17))))); -+ } -+ -+ if ((gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_HALTI2) == gcvSTATUS_FALSE) -+ || (Hardware->identity.chipRevision < 0x5422) -+ ) -+ { -+ if (regPMC == 0) -+ { -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ Hardware->powerBaseAddress -+ + 0x00104, -+ ®PMC)); -+ } -+ -+ regPMC = ((((gctUINT32) (regPMC)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:15) - (0 ? 15:15) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:15) - (0 ? 15:15) + 1))))))) << (0 ? 15:15))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 15:15) - (0 ? 15:15) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:15) - (0 ? 15:15) + 1))))))) << (0 ? 15:15))); -+ } -+ -+ if (_IsHardwareMatch(Hardware, gcv2000, 0x5108)) -+ { -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00480, -+ &data)); -+ -+ /* Set FE bus to one, TX bus to zero */ -+ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))); -+ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))); -+ -+ gcmkONERROR( -+ gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00480, -+ data)); -+ } -+ -+ gcmkONERROR( -+ gckHARDWARE_SetMMU(Hardware, -+ Hardware->kernel->mmu->pageTableLogical)); -+ -+ if (Hardware->identity.chipModel >= gcv400 -+ && Hardware->identity.chipModel != gcv420) -+ { -+ if (regPMC == 0) -+ { -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ Hardware->powerBaseAddress -+ + 0x00104, -+ ®PMC)); -+ } -+ -+ /* Disable PA clock gating. */ -+ regPMC = ((((gctUINT32) (regPMC)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))); -+ } -+ -+ /* Limit 2D outstanding request. */ -+ if (_IsHardwareMatch(Hardware, gcv880, 0x5107)) -+ { -+ gctUINT32 axi_ot; -+ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00414, &axi_ot)); -+ axi_ot = (axi_ot & (~0xFF)) | 0x00010; -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00414, axi_ot)); -+ } -+ -+ if (Hardware->identity.chip2DControl & 0xFF) -+ { -+ gctUINT32 data; -+ -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00414, -+ &data)); -+ -+ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (Hardware->identity.chip2DControl & 0xFF) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))); -+ -+ gcmkONERROR( -+ gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00414, -+ data)); -+ } -+ -+ if (_IsHardwareMatch(Hardware, gcv1000, 0x5035)) -+ { -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00414, -+ &data)); -+ -+ /* Disable HZ-L2. */ -+ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))); -+ -+ gcmkONERROR( -+ gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00414, -+ data)); -+ } -+ -+ if (_IsHardwareMatch(Hardware, gcv4000, 0x5222)) -+ { -+ if (regPMC == 0) -+ { -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ Hardware->powerBaseAddress -+ + 0x00104, -+ ®PMC)); -+ } -+ -+ /* Disable TX clock gating. */ -+ regPMC = ((((gctUINT32) (regPMC)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))); -+ } -+ -+ if (_IsHardwareMatch(Hardware, gcv880, 0x5106)) -+ { -+ Hardware->kernel->timeOut = 140 * 1000; -+ } -+ -+ if (regPMC == 0) -+ { -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ Hardware->powerBaseAddress -+ + 0x00104, -+ ®PMC)); -+ } -+ -+ /* Disable RA HZ clock gating. */ -+ regPMC = ((((gctUINT32) (regPMC)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17))); -+ -+ /* Disable RA EZ clock gating. */ -+ regPMC = ((((gctUINT32) (regPMC)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))); -+ -+ if (regPMC != 0) -+ { -+ gcmkONERROR( -+ gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ Hardware->powerBaseAddress -+ + 0x00104, -+ regPMC)); -+ } -+ -+ if (_IsHardwareMatch(Hardware, gcv2000, 0x5108) -+ || _IsHardwareMatch(Hardware, gcv320, 0x5007) -+ || _IsHardwareMatch(Hardware, gcv880, 0x5106) -+ || _IsHardwareMatch(Hardware, gcv400, 0x4645) -+ ) -+ { -+ /* Update GPU AXI cache atttribute. */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00008, -+ 0x00002200)); -+ } -+ -+ -+ if ((Hardware->identity.chipRevision > 0x5420) -+ && gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_PIPE_3D)) -+ { -+ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x0010C, -+ &data)); -+ -+ /* Disable internal DFS. */ -+ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1))))))) << (0 ? 18:18))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1))))))) << (0 ? 18:18))); -+ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x0010C, -+ data)); -+ } -+ -+#if gcdDEBUG_MODULE_CLOCK_GATING -+ _ConfigureModuleLevelClockGating(Hardware); -+#endif -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the error. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckHARDWARE_QueryMemory -+** -+** Query the amount of memory available on the hardware. -+** -+** INPUT: -+** -+** gckHARDWARE Hardware -+** Pointer to the gckHARDWARE object. -+** -+** OUTPUT: -+** -+** gctSIZE_T * InternalSize -+** Pointer to a variable that will hold the size of the internal video -+** memory in bytes. If 'InternalSize' is gcvNULL, no information of the -+** internal memory will be returned. -+** -+** gctUINT32 * InternalBaseAddress -+** Pointer to a variable that will hold the hardware's base address for -+** the internal video memory. This pointer cannot be gcvNULL if -+** 'InternalSize' is also non-gcvNULL. -+** -+** gctUINT32 * InternalAlignment -+** Pointer to a variable that will hold the hardware's base address for -+** the internal video memory. This pointer cannot be gcvNULL if -+** 'InternalSize' is also non-gcvNULL. -+** -+** gctSIZE_T * ExternalSize -+** Pointer to a variable that will hold the size of the external video -+** memory in bytes. If 'ExternalSize' is gcvNULL, no information of the -+** external memory will be returned. -+** -+** gctUINT32 * ExternalBaseAddress -+** Pointer to a variable that will hold the hardware's base address for -+** the external video memory. This pointer cannot be gcvNULL if -+** 'ExternalSize' is also non-gcvNULL. -+** -+** gctUINT32 * ExternalAlignment -+** Pointer to a variable that will hold the hardware's base address for -+** the external video memory. This pointer cannot be gcvNULL if -+** 'ExternalSize' is also non-gcvNULL. -+** -+** gctUINT32 * HorizontalTileSize -+** Number of horizontal pixels per tile. If 'HorizontalTileSize' is -+** gcvNULL, no horizontal pixel per tile will be returned. -+** -+** gctUINT32 * VerticalTileSize -+** Number of vertical pixels per tile. If 'VerticalTileSize' is -+** gcvNULL, no vertical pixel per tile will be returned. -+*/ -+gceSTATUS -+gckHARDWARE_QueryMemory( -+ IN gckHARDWARE Hardware, -+ OUT gctSIZE_T * InternalSize, -+ OUT gctUINT32 * InternalBaseAddress, -+ OUT gctUINT32 * InternalAlignment, -+ OUT gctSIZE_T * ExternalSize, -+ OUT gctUINT32 * ExternalBaseAddress, -+ OUT gctUINT32 * ExternalAlignment, -+ OUT gctUINT32 * HorizontalTileSize, -+ OUT gctUINT32 * VerticalTileSize -+ ) -+{ -+ gcmkHEADER_ARG("Hardware=0x%x", Hardware); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ if (InternalSize != gcvNULL) -+ { -+ /* No internal memory. */ -+ *InternalSize = 0; -+ } -+ -+ if (ExternalSize != gcvNULL) -+ { -+ /* No external memory. */ -+ *ExternalSize = 0; -+ } -+ -+ if (HorizontalTileSize != gcvNULL) -+ { -+ /* 4x4 tiles. */ -+ *HorizontalTileSize = 4; -+ } -+ -+ if (VerticalTileSize != gcvNULL) -+ { -+ /* 4x4 tiles. */ -+ *VerticalTileSize = 4; -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*InternalSize=%lu *InternalBaseAddress=0x%08x " -+ "*InternalAlignment=0x%08x *ExternalSize=%lu " -+ "*ExternalBaseAddress=0x%08x *ExtenalAlignment=0x%08x " -+ "*HorizontalTileSize=%u *VerticalTileSize=%u", -+ gcmOPT_VALUE(InternalSize), -+ gcmOPT_VALUE(InternalBaseAddress), -+ gcmOPT_VALUE(InternalAlignment), -+ gcmOPT_VALUE(ExternalSize), -+ gcmOPT_VALUE(ExternalBaseAddress), -+ gcmOPT_VALUE(ExternalAlignment), -+ gcmOPT_VALUE(HorizontalTileSize), -+ gcmOPT_VALUE(VerticalTileSize)); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckHARDWARE_QueryChipIdentity -+** -+** Query the identity of the hardware. -+** -+** INPUT: -+** -+** gckHARDWARE Hardware -+** Pointer to the gckHARDWARE object. -+** -+** OUTPUT: -+** -+** gcsHAL_QUERY_CHIP_IDENTITY_PTR Identity -+** Pointer to the identity structure. -+** -+*/ -+gceSTATUS -+gckHARDWARE_QueryChipIdentity( -+ IN gckHARDWARE Hardware, -+ OUT gcsHAL_QUERY_CHIP_IDENTITY_PTR Identity -+ ) -+{ -+ gctUINT32 features; -+ -+ gcmkHEADER_ARG("Hardware=0x%x", Hardware); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ gcmkVERIFY_ARGUMENT(Identity != gcvNULL); -+ -+ /* Return chip model and revision. */ -+ Identity->chipModel = Hardware->identity.chipModel; -+ Identity->chipRevision = Hardware->identity.chipRevision; -+ -+ /* Return feature set. */ -+ features = Hardware->identity.chipFeatures; -+ -+ if ((((((gctUINT32) (features)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) )) -+ { -+ /* Override fast clear by command line. */ -+ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (Hardware->allowFastClear) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))); -+ } -+ -+ if ((((((gctUINT32) (features)) >> (0 ? 5:5)) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1)))))) )) -+ { -+ /* Override compression by command line. */ -+ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) ((gctUINT32) (Hardware->allowCompression) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))); -+ } -+ -+ /* Mark 2D pipe as available for GC500.0 through GC500.2 and GC300, -+ ** since they did not have this bit. */ -+ if (((Hardware->identity.chipModel == gcv500) && (Hardware->identity.chipRevision <= 2)) -+ || (Hardware->identity.chipModel == gcv300) -+ ) -+ { -+ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))); -+ } -+ -+ Identity->chipFeatures = features; -+ -+ /* Return minor features. */ -+ Identity->chipMinorFeatures = Hardware->identity.chipMinorFeatures; -+ Identity->chipMinorFeatures1 = Hardware->identity.chipMinorFeatures1; -+ Identity->chipMinorFeatures2 = Hardware->identity.chipMinorFeatures2; -+ Identity->chipMinorFeatures3 = Hardware->identity.chipMinorFeatures3; -+ Identity->chipMinorFeatures4 = Hardware->identity.chipMinorFeatures4; -+ Identity->chipMinorFeatures5 = Hardware->identity.chipMinorFeatures5; -+ -+ /* Return chip specs. */ -+ Identity->streamCount = Hardware->identity.streamCount; -+ Identity->registerMax = Hardware->identity.registerMax; -+ Identity->threadCount = Hardware->identity.threadCount; -+ Identity->shaderCoreCount = Hardware->identity.shaderCoreCount; -+ Identity->vertexCacheSize = Hardware->identity.vertexCacheSize; -+ Identity->vertexOutputBufferSize = Hardware->identity.vertexOutputBufferSize; -+ Identity->pixelPipes = Hardware->identity.pixelPipes; -+ Identity->instructionCount = Hardware->identity.instructionCount; -+ Identity->numConstants = Hardware->identity.numConstants; -+ Identity->bufferSize = Hardware->identity.bufferSize; -+ Identity->varyingsCount = Hardware->identity.varyingsCount; -+ Identity->superTileMode = Hardware->identity.superTileMode; -+ Identity->chip2DControl = Hardware->identity.chip2DControl; -+ -+ Identity->productID = Hardware->identity.productID; -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckHARDWARE_SplitMemory -+** -+** Split a hardware specific memory address into a pool and offset. -+** -+** INPUT: -+** -+** gckHARDWARE Hardware -+** Pointer to the gckHARDWARE object. -+** -+** gctUINT32 Address -+** Address in hardware specific format. -+** -+** OUTPUT: -+** -+** gcePOOL * Pool -+** Pointer to a variable that will hold the pool type for the address. -+** -+** gctUINT32 * Offset -+** Pointer to a variable that will hold the offset for the address. -+*/ -+gceSTATUS -+gckHARDWARE_SplitMemory( -+ IN gckHARDWARE Hardware, -+ IN gctUINT32 Address, -+ OUT gcePOOL * Pool, -+ OUT gctUINT32 * Offset -+ ) -+{ -+ gcmkHEADER_ARG("Hardware=0x%x Addres=0x%08x", Hardware, Address); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ gcmkVERIFY_ARGUMENT(Pool != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Offset != gcvNULL); -+ -+ if (Hardware->mmuVersion == 0) -+ { -+ /* Dispatch on memory type. */ -+ switch ((((((gctUINT32) (Address)) >> (0 ? 31:31)) & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1)))))) )) -+ { -+ case 0x0: -+ /* System memory. */ -+ *Pool = gcvPOOL_SYSTEM; -+ break; -+ -+ case 0x1: -+ /* Virtual memory. */ -+ *Pool = gcvPOOL_VIRTUAL; -+ break; -+ -+ default: -+ /* Invalid memory type. */ -+ gcmkFOOTER_ARG("status=%d", gcvSTATUS_INVALID_ARGUMENT); -+ return gcvSTATUS_INVALID_ARGUMENT; -+ } -+ -+ /* Return offset of address. */ -+ *Offset = (((((gctUINT32) (Address)) >> (0 ? 30:0)) & ((gctUINT32) ((((1 ? 30:0) - (0 ? 30:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 30:0) - (0 ? 30:0) + 1)))))) ); -+ } -+ else -+ { -+ *Pool = gcvPOOL_SYSTEM; -+ *Offset = Address; -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Pool=%d *Offset=0x%08x", *Pool, *Offset); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckHARDWARE_Execute -+** -+** Kickstart the hardware's command processor with an initialized command -+** buffer. -+** -+** INPUT: -+** -+** gckHARDWARE Hardware -+** Pointer to the gckHARDWARE object. -+** -+** gctUINT32 Address -+** Hardware address of command buffer. -+** -+** gctSIZE_T Bytes -+** Number of bytes for the prefetch unit (until after the first LINK). -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckHARDWARE_Execute( -+ IN gckHARDWARE Hardware, -+ IN gctUINT32 Address, -+ IN gctSIZE_T Bytes -+ ) -+{ -+ gceSTATUS status; -+ gctUINT32 control; -+ -+ gcmkHEADER_ARG("Hardware=0x%x Address=0x%x Bytes=%lu", -+ Hardware, Address, Bytes); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ /* Enable all events. */ -+ gcmkONERROR( -+ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00014, ~0U)); -+ -+ /* Write address register. */ -+ gcmkONERROR( -+ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00654, Address)); -+ -+ /* Build control register. */ -+ control = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) ((Bytes + 7) >> 3) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); -+ -+ /* Set big endian */ -+ if (Hardware->bigEndian) -+ { -+ control |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 21:20) - (0 ? 21:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:20) - (0 ? 21:20) + 1))))))) << (0 ? 21:20))) | (((gctUINT32) (0x2 & ((gctUINT32) ((((1 ? 21:20) - (0 ? 21:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:20) - (0 ? 21:20) + 1))))))) << (0 ? 21:20))); -+ } -+ -+ /* Write control register. */ -+ gcmkONERROR( -+ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00658, control)); -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "Started command buffer @ 0x%08x", -+ Address); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckHARDWARE_WaitLink -+** -+** Append a WAIT/LINK command sequence at the specified location in the command -+** queue. -+** -+** INPUT: -+** -+** gckHARDWARE Hardware -+** Pointer to an gckHARDWARE object. -+** -+** gctPOINTER Logical -+** Pointer to the current location inside the command queue to append -+** WAIT/LINK command sequence at or gcvNULL just to query the size of the -+** WAIT/LINK command sequence. -+** -+** gctUINT32 Offset -+** Offset into command buffer required for alignment. -+** -+** gctSIZE_T * Bytes -+** Pointer to the number of bytes available for the WAIT/LINK command -+** sequence. If 'Logical' is gcvNULL, this argument will be ignored. -+** -+** OUTPUT: -+** -+** gctSIZE_T * Bytes -+** Pointer to a variable that will receive the number of bytes required -+** by the WAIT/LINK command sequence. If 'Bytes' is gcvNULL, nothing will -+** be returned. -+** -+** gctUINT32 * WaitOffset -+** Pointer to a variable that will receive the offset of the WAIT command -+** from the specified logcial pointer. -+** If 'WaitOffset' is gcvNULL nothing will be returned. -+** -+** gctSIZE_T * WaitSize -+** Pointer to a variable that will receive the number of bytes used by -+** the WAIT command. If 'LinkSize' is gcvNULL nothing will be returned. -+*/ -+gceSTATUS -+gckHARDWARE_WaitLink( -+ IN gckHARDWARE Hardware, -+ IN gctPOINTER Logical, -+ IN gctUINT32 Offset, -+ IN OUT gctUINT32 * Bytes, -+ OUT gctUINT32 * WaitOffset, -+ OUT gctUINT32 * WaitSize -+ ) -+{ -+ static const gctUINT waitCount = 200; -+ -+ gceSTATUS status; -+ gctUINT32 address; -+ gctUINT32_PTR logical; -+ gctUINT32 bytes; -+ -+ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x Offset=0x%08x *Bytes=%lu", -+ Hardware, Logical, Offset, gcmOPT_VALUE(Bytes)); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ gcmkVERIFY_ARGUMENT((Logical != gcvNULL) || (Bytes != gcvNULL)); -+ -+ /* Compute number of bytes required. */ -+ bytes = gcmALIGN(Offset + 16, 8) - Offset; -+ /* Cast the input pointer. */ -+ logical = (gctUINT32_PTR) Logical; -+ -+ if (logical != gcvNULL) -+ { -+ /* Not enough space? */ -+ if (*Bytes < bytes) -+ { -+ /* Command queue too small. */ -+ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL); -+ } -+ -+ /* Convert logical into hardware specific address. */ -+ gcmkONERROR(gckHARDWARE_ConvertLogical(Hardware, logical, gcvFALSE, &address)); -+ -+ /* Store the WAIT/LINK address. */ -+ Hardware->lastWaitLink = address; -+ -+ /* Append WAIT(count). */ -+ logical[0] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (waitCount) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); -+ -+ /* Append LINK(2, address). */ -+ logical[2] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (bytes >> 3) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); -+ -+ logical[3] = address; -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "0x%08x: WAIT %u", address, waitCount -+ ); -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "0x%08x: LINK 0x%08x, #%lu", -+ address + 8, address, bytes -+ ); -+ if (WaitOffset != gcvNULL) -+ { -+ /* Return the offset pointer to WAIT command. */ -+ *WaitOffset = 0; -+ } -+ -+ if (WaitSize != gcvNULL) -+ { -+ /* Return number of bytes used by the WAIT command. */ -+ *WaitSize = 8; -+ } -+ } -+ -+ if (Bytes != gcvNULL) -+ { -+ /* Return number of bytes required by the WAIT/LINK command -+ ** sequence. */ -+ *Bytes = bytes; -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Bytes=%lu *WaitOffset=0x%x *WaitSize=%lu", -+ gcmOPT_VALUE(Bytes), gcmOPT_VALUE(WaitOffset), -+ gcmOPT_VALUE(WaitSize)); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckHARDWARE_End -+** -+** Append an END command at the specified location in the command queue. -+** -+** INPUT: -+** -+** gckHARDWARE Hardware -+** Pointer to an gckHARDWARE object. -+** -+** gctPOINTER Logical -+** Pointer to the current location inside the command queue to append -+** END command at or gcvNULL just to query the size of the END command. -+** -+** gctSIZE_T * Bytes -+** Pointer to the number of bytes available for the END command. If -+** 'Logical' is gcvNULL, this argument will be ignored. -+** -+** OUTPUT: -+** -+** gctSIZE_T * Bytes -+** Pointer to a variable that will receive the number of bytes required -+** for the END command. If 'Bytes' is gcvNULL, nothing will be returned. -+*/ -+gceSTATUS -+gckHARDWARE_End( -+ IN gckHARDWARE Hardware, -+ IN gctPOINTER Logical, -+ IN OUT gctUINT32 * Bytes -+ ) -+{ -+ gctUINT32_PTR logical = (gctUINT32_PTR) Logical; -+ gctUINT32 address; -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x *Bytes=%lu", -+ Hardware, Logical, gcmOPT_VALUE(Bytes)); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ gcmkVERIFY_ARGUMENT((Logical == gcvNULL) || (Bytes != gcvNULL)); -+ -+ if (Logical != gcvNULL) -+ { -+ if (*Bytes < 8) -+ { -+ /* Command queue too small. */ -+ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL); -+ } -+ -+ /* Append END. */ -+ logical[0] = -+ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x02 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))); -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, "0x%x: END", Logical); -+ -+ /* Make sure the CPU writes out the data to memory. */ -+ gcmkONERROR( -+ gckOS_MemoryBarrier(Hardware->os, Logical)); -+ -+ gcmkONERROR(gckHARDWARE_ConvertLogical(Hardware, logical, gcvFALSE, &address)); -+ -+ Hardware->lastEnd = address; -+ } -+ -+ if (Bytes != gcvNULL) -+ { -+ /* Return number of bytes required by the END command. */ -+ *Bytes = 8; -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes)); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckHARDWARE_Nop -+** -+** Append a NOP command at the specified location in the command queue. -+** -+** INPUT: -+** -+** gckHARDWARE Hardware -+** Pointer to an gckHARDWARE object. -+** -+** gctPOINTER Logical -+** Pointer to the current location inside the command queue to append -+** NOP command at or gcvNULL just to query the size of the NOP command. -+** -+** gctSIZE_T * Bytes -+** Pointer to the number of bytes available for the NOP command. If -+** 'Logical' is gcvNULL, this argument will be ignored. -+** -+** OUTPUT: -+** -+** gctSIZE_T * Bytes -+** Pointer to a variable that will receive the number of bytes required -+** for the NOP command. If 'Bytes' is gcvNULL, nothing will be returned. -+*/ -+gceSTATUS -+gckHARDWARE_Nop( -+ IN gckHARDWARE Hardware, -+ IN gctPOINTER Logical, -+ IN OUT gctSIZE_T * Bytes -+ ) -+{ -+ gctUINT32_PTR logical = (gctUINT32_PTR) Logical; -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x *Bytes=%lu", -+ Hardware, Logical, gcmOPT_VALUE(Bytes)); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ gcmkVERIFY_ARGUMENT((Logical == gcvNULL) || (Bytes != gcvNULL)); -+ -+ if (Logical != gcvNULL) -+ { -+ if (*Bytes < 8) -+ { -+ /* Command queue too small. */ -+ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL); -+ } -+ -+ /* Append NOP. */ -+ logical[0] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x03 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))); -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, "0x%x: NOP", Logical); -+ } -+ -+ if (Bytes != gcvNULL) -+ { -+ /* Return number of bytes required by the NOP command. */ -+ *Bytes = 8; -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes)); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckHARDWARE_Event -+** -+** Append an EVENT command at the specified location in the command queue. -+** -+** INPUT: -+** -+** gckHARDWARE Hardware -+** Pointer to an gckHARDWARE object. -+** -+** gctPOINTER Logical -+** Pointer to the current location inside the command queue to append -+** the EVENT command at or gcvNULL just to query the size of the EVENT -+** command. -+** -+** gctUINT8 Event -+** Event ID to program. -+** -+** gceKERNEL_WHERE FromWhere -+** Location of the pipe to send the event. -+** -+** gctSIZE_T * Bytes -+** Pointer to the number of bytes available for the EVENT command. If -+** 'Logical' is gcvNULL, this argument will be ignored. -+** -+** OUTPUT: -+** -+** gctSIZE_T * Bytes -+** Pointer to a variable that will receive the number of bytes required -+** for the EVENT command. If 'Bytes' is gcvNULL, nothing will be -+** returned. -+*/ -+gceSTATUS -+gckHARDWARE_Event( -+ IN gckHARDWARE Hardware, -+ IN gctPOINTER Logical, -+ IN gctUINT8 Event, -+ IN gceKERNEL_WHERE FromWhere, -+ IN OUT gctUINT32 * Bytes -+ ) -+{ -+ gctUINT size; -+ gctUINT32 destination = 0; -+ gctUINT32_PTR logical = (gctUINT32_PTR) Logical; -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x Event=%u FromWhere=%d *Bytes=%lu", -+ Hardware, Logical, Event, FromWhere, gcmOPT_VALUE(Bytes)); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ gcmkVERIFY_ARGUMENT((Logical == gcvNULL) || (Bytes != gcvNULL)); -+ gcmkVERIFY_ARGUMENT(Event < 32); -+ -+ /* Determine the size of the command. */ -+ -+ size = (Hardware->extraEventStates && (FromWhere == gcvKERNEL_PIXEL)) -+ ? gcmALIGN(8 + (1 + 5) * 4, 8) /* EVENT + 5 STATES */ -+ : 8; -+ -+ if (Logical != gcvNULL) -+ { -+ if (*Bytes < size) -+ { -+ /* Command queue too small. */ -+ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL); -+ } -+ -+ switch (FromWhere) -+ { -+ case gcvKERNEL_COMMAND: -+ /* From command processor. */ -+ destination = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))); -+ break; -+ -+ case gcvKERNEL_PIXEL: -+ /* From pixel engine. */ -+ destination = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))); -+ break; -+ -+ default: -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ } -+ -+ /* Append EVENT(Event, destiantion). */ -+ logical[0] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E01) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))); -+ -+ logical[1] = ((((gctUINT32) (destination)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (Event) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))); -+ -+ /* Make sure the event ID gets written out before GPU can access it. */ -+ gcmkONERROR( -+ gckOS_MemoryBarrier(Hardware->os, logical + 1)); -+ -+#if gcmIS_DEBUG(gcdDEBUG_TRACE) -+ { -+ gctUINT32 phys; -+ gckOS_GetPhysicalAddress(Hardware->os, Logical, &phys); -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "0x%08x: EVENT %d", phys, Event); -+ } -+#endif -+ -+ /* Append the extra states. These are needed for the chips that do not -+ ** support back-to-back events due to the async interface. The extra -+ ** states add the necessary delay to ensure that event IDs do not -+ ** collide. */ -+ if (size > 8) -+ { -+ logical[2] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0100) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))); -+ logical[3] = 0; -+ logical[4] = 0; -+ logical[5] = 0; -+ logical[6] = 0; -+ logical[7] = 0; -+ } -+ -+#if gcdINTERRUPT_STATISTIC -+ if (Event < gcmCOUNTOF(Hardware->kernel->eventObj->queues)) -+ { -+ gckOS_AtomSetMask(Hardware->pendingEvent, 1 << Event); -+ } -+#endif -+ } -+ -+ if (Bytes != gcvNULL) -+ { -+ /* Return number of bytes required by the EVENT command. */ -+ *Bytes = size; -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes)); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckHARDWARE_PipeSelect -+** -+** Append a PIPESELECT command at the specified location in the command queue. -+** -+** INPUT: -+** -+** gckHARDWARE Hardware -+** Pointer to an gckHARDWARE object. -+** -+** gctPOINTER Logical -+** Pointer to the current location inside the command queue to append -+** the PIPESELECT command at or gcvNULL just to query the size of the -+** PIPESELECT command. -+** -+** gcePIPE_SELECT Pipe -+** Pipe value to select. -+** -+** gctSIZE_T * Bytes -+** Pointer to the number of bytes available for the PIPESELECT command. -+** If 'Logical' is gcvNULL, this argument will be ignored. -+** -+** OUTPUT: -+** -+** gctSIZE_T * Bytes -+** Pointer to a variable that will receive the number of bytes required -+** for the PIPESELECT command. If 'Bytes' is gcvNULL, nothing will be -+** returned. -+*/ -+gceSTATUS -+gckHARDWARE_PipeSelect( -+ IN gckHARDWARE Hardware, -+ IN gctPOINTER Logical, -+ IN gcePIPE_SELECT Pipe, -+ IN OUT gctUINT32 * Bytes -+ ) -+{ -+ gctUINT32_PTR logical = (gctUINT32_PTR) Logical; -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x Pipe=%d *Bytes=%lu", -+ Hardware, Logical, Pipe, gcmOPT_VALUE(Bytes)); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ gcmkVERIFY_ARGUMENT((Logical == gcvNULL) || (Bytes != gcvNULL)); -+ -+ /* Append a PipeSelect. */ -+ if (Logical != gcvNULL) -+ { -+ gctUINT32 flush, stall; -+ -+ if (*Bytes < 32) -+ { -+ /* Command queue too small. */ -+ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL); -+ } -+ -+ flush = (Pipe == gcvPIPE_2D) -+ ? ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) -+ : ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))); -+ -+ stall = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); -+ -+ /* LoadState(AQFlush, 1), flush. */ -+ logical[0] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E03) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))); -+ -+ logical[1] -+ = flush; -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "0x%x: FLUSH 0x%x", logical, flush); -+ -+ /* LoadState(AQSempahore, 1), stall. */ -+ logical[2] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); -+ -+ logical[3] -+ = stall; -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "0x%x: SEMAPHORE 0x%x", logical + 2, stall); -+ -+ /* Stall, stall. */ -+ logical[4] = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))); -+ logical[5] = stall; -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "0x%x: STALL 0x%x", logical + 4, stall); -+ -+ /* LoadState(AQPipeSelect, 1), pipe. */ -+ logical[6] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E00) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))); -+ -+ logical[7] = (Pipe == gcvPIPE_2D) -+ ? 0x1 -+ : 0x0; -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "0x%x: PIPE %d", logical + 6, Pipe); -+ } -+ -+ if (Bytes != gcvNULL) -+ { -+ /* Return number of bytes required by the PIPESELECT command. */ -+ *Bytes = 32; -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes)); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckHARDWARE_Link -+** -+** Append a LINK command at the specified location in the command queue. -+** -+** INPUT: -+** -+** gckHARDWARE Hardware -+** Pointer to an gckHARDWARE object. -+** -+** gctPOINTER Logical -+** Pointer to the current location inside the command queue to append -+** the LINK command at or gcvNULL just to query the size of the LINK -+** command. -+** -+** gctUINT32 FetchAddress -+** Hardware address of destination of LINK. -+** -+** gctSIZE_T FetchSize -+** Number of bytes in destination of LINK. -+** -+** gctSIZE_T * Bytes -+** Pointer to the number of bytes available for the LINK command. If -+** 'Logical' is gcvNULL, this argument will be ignored. -+** -+** OUTPUT: -+** -+** gctSIZE_T * Bytes -+** Pointer to a variable that will receive the number of bytes required -+** for the LINK command. If 'Bytes' is gcvNULL, nothing will be returned. -+*/ -+gceSTATUS -+gckHARDWARE_Link( -+ IN gckHARDWARE Hardware, -+ IN gctPOINTER Logical, -+ IN gctUINT32 FetchAddress, -+ IN gctUINT32 FetchSize, -+ IN OUT gctUINT32 * Bytes -+ ) -+{ -+ gceSTATUS status; -+ gctSIZE_T bytes; -+ gctUINT32 link; -+ gctUINT32_PTR logical = (gctUINT32_PTR) Logical; -+ -+ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x FetchAddress=0x%x FetchSize=%lu " -+ "*Bytes=%lu", -+ Hardware, Logical, FetchAddress, FetchSize, -+ gcmOPT_VALUE(Bytes)); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ gcmkVERIFY_ARGUMENT((Logical == gcvNULL) || (Bytes != gcvNULL)); -+ -+ if (Logical != gcvNULL) -+ { -+ if (*Bytes < 8) -+ { -+ /* Command queue too small. */ -+ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL); -+ } -+ -+ gcmkONERROR( -+ gckOS_WriteMemory(Hardware->os, logical + 1, FetchAddress)); -+ -+ /* Make sure the address got written before the LINK command. */ -+ gcmkONERROR( -+ gckOS_MemoryBarrier(Hardware->os, logical + 1)); -+ -+ /* Compute number of 64-byte aligned bytes to fetch. */ -+ bytes = gcmALIGN(FetchAddress + FetchSize, 8) - FetchAddress; -+ -+ /* Append LINK(bytes / 8), FetchAddress. */ -+ link = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (bytes >> 3) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); -+ -+ gcmkONERROR( -+ gckOS_WriteMemory(Hardware->os, logical, link)); -+ -+ /* Memory barrier. */ -+ gcmkONERROR( -+ gckOS_MemoryBarrier(Hardware->os, logical)); -+ -+#if gcdLINK_QUEUE_SIZE && !gcdPROCESS_ADDRESS_SPACE -+ if ((Hardware->kernel->virtualCommandBuffer) -+ && (Hardware->kernel->stuckDump > 2) -+ ) -+ { -+ gctBOOL in; -+ -+ gcmkVERIFY_OK(gckCOMMAND_AddressInKernelCommandBuffer( -+ Hardware->kernel->command, FetchAddress, &in)); -+ -+ if (in == gcvFALSE) -+ { -+ /* Record user command buffer and context buffer link -+ ** information for stuck dump. -+ **/ -+ gckLINKQUEUE_Enqueue( -+ &Hardware->linkQueue, FetchAddress, FetchAddress + (gctUINT)bytes); -+ } -+ } -+#endif -+ } -+ -+ if (Bytes != gcvNULL) -+ { -+ /* Return number of bytes required by the LINK command. */ -+ *Bytes = 8; -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes)); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckHARDWARE_UpdateQueueTail -+** -+** Update the tail of the command queue. -+** -+** INPUT: -+** -+** gckHARDWARE Hardware -+** Pointer to an gckHARDWARE object. -+** -+** gctPOINTER Logical -+** Logical address of the start of the command queue. -+** -+** gctUINT32 Offset -+** Offset into the command queue of the tail (last command). -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckHARDWARE_UpdateQueueTail( -+ IN gckHARDWARE Hardware, -+ IN gctPOINTER Logical, -+ IN gctUINT32 Offset -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x Offset=0x%08x", -+ Hardware, Logical, Offset); -+ -+ /* Verify the hardware. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ /* Force a barrier. */ -+ gcmkONERROR( -+ gckOS_MemoryBarrier(Hardware->os, Logical)); -+ -+ /* Notify gckKERNEL object of change. */ -+ gcmkONERROR( -+ gckKERNEL_Notify(Hardware->kernel, -+ gcvNOTIFY_COMMAND_QUEUE, -+ gcvFALSE)); -+ -+ if (status == gcvSTATUS_CHIP_NOT_READY) -+ { -+ gcmkONERROR(gcvSTATUS_DEVICE); -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckHARDWARE_ConvertLogical -+** -+** Convert a logical system address into a hardware specific address. -+** -+** INPUT: -+** -+** gckHARDWARE Hardware -+** Pointer to an gckHARDWARE object. -+** -+** gctPOINTER Logical -+** Logical address to convert. -+** -+** gctBOOL InUserSpace -+** gcvTRUE if the memory in user space. -+** -+** gctUINT32* Address -+** Return hardware specific address. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckHARDWARE_ConvertLogical( -+ IN gckHARDWARE Hardware, -+ IN gctPOINTER Logical, -+ IN gctBOOL InUserSpace, -+ OUT gctUINT32 * Address -+ ) -+{ -+ gctUINT32 address; -+ gceSTATUS status; -+ gctUINT32 baseAddress; -+ -+ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x InUserSpace=%d", -+ Hardware, Logical, InUserSpace); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ gcmkVERIFY_ARGUMENT(Logical != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Address != gcvNULL); -+ -+ /* Convert logical address into a physical address. */ -+ if (InUserSpace) -+ { -+ gcmkONERROR(gckOS_UserLogicalToPhysical(Hardware->os, Logical, &address)); -+ } -+ else -+ { -+ gcmkONERROR(gckOS_GetPhysicalAddress(Hardware->os, Logical, &address)); -+ } -+ -+ /* For old MMU, get GPU address according to baseAddress. */ -+ if (Hardware->mmuVersion == 0) -+ { -+ gcmkONERROR(gckOS_GetBaseAddress(Hardware->os, &baseAddress)); -+ -+ /* Subtract base address to get a GPU address. */ -+ gcmkASSERT(address >= baseAddress); -+ address -= baseAddress; -+ } -+ -+ /* Return hardware specific address. */ -+ *Address = (Hardware->mmuVersion == 0) -+ ? ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 30:0) - (0 ? 30:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 30:0) - (0 ? 30:0) + 1))))))) << (0 ? 30:0))) | (((gctUINT32) ((gctUINT32) (address) & ((gctUINT32) ((((1 ? 30:0) - (0 ? 30:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 30:0) - (0 ? 30:0) + 1))))))) << (0 ? 30:0))) -+ : address; -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Address=0x%08x", *Address); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckHARDWARE_Interrupt -+** -+** Process an interrupt. -+** -+** INPUT: -+** -+** gckHARDWARE Hardware -+** Pointer to an gckHARDWARE object. -+** -+** gctBOOL InterruptValid -+** If gcvTRUE, this function will read the interrupt acknowledge -+** register, stores the data, and return whether or not the interrupt -+** is ours or not. If gcvFALSE, this functions will read the interrupt -+** acknowledge register and combine it with any stored value to handle -+** the event notifications. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckHARDWARE_Interrupt( -+ IN gckHARDWARE Hardware, -+ IN gctBOOL InterruptValid -+ ) -+{ -+ gckEVENT eventObj; -+ gctUINT32 data = 0; -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Hardware=0x%x InterruptValid=%d", Hardware, InterruptValid); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ /* Extract gckEVENT object. */ -+ eventObj = Hardware->kernel->eventObj; -+ gcmkVERIFY_OBJECT(eventObj, gcvOBJ_EVENT); -+ -+ if (InterruptValid) -+ { -+ /* Read AQIntrAcknowledge register. */ -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00010, -+ &data)); -+ -+ if (data == 0) -+ { -+ /* Not our interrupt. */ -+ status = gcvSTATUS_NOT_OUR_INTERRUPT; -+ } -+ else -+ { -+ -+#if gcdINTERRUPT_STATISTIC -+ gckOS_AtomClearMask(Hardware->pendingEvent, data); -+#endif -+ -+ /* Inform gckEVENT of the interrupt. */ -+ status = gckEVENT_Interrupt(eventObj, -+ data); -+ } -+ } -+ else -+ { -+ /* Handle events. */ -+ status = gckEVENT_Notify(eventObj, 0); -+ } -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckHARDWARE_QueryCommandBuffer -+** -+** Query the command buffer alignment and number of reserved bytes. -+** -+** INPUT: -+** -+** gckHARDWARE Harwdare -+** Pointer to an gckHARDWARE object. -+** -+** OUTPUT: -+** -+** gctSIZE_T * Alignment -+** Pointer to a variable receiving the alignment for each command. -+** -+** gctSIZE_T * ReservedHead -+** Pointer to a variable receiving the number of reserved bytes at the -+** head of each command buffer. -+** -+** gctSIZE_T * ReservedTail -+** Pointer to a variable receiving the number of bytes reserved at the -+** tail of each command buffer. -+*/ -+gceSTATUS -+gckHARDWARE_QueryCommandBuffer( -+ IN gckHARDWARE Hardware, -+ OUT gctUINT32 * Alignment, -+ OUT gctUINT32 * ReservedHead, -+ OUT gctUINT32 * ReservedTail -+ ) -+{ -+ gcmkHEADER_ARG("Hardware=0x%x", Hardware); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ if (Alignment != gcvNULL) -+ { -+ /* Align every 8 bytes. */ -+ *Alignment = 8; -+ } -+ -+ if (ReservedHead != gcvNULL) -+ { -+ /* Reserve space for SelectPipe(). */ -+ *ReservedHead = 32; -+ } -+ -+ if (ReservedTail != gcvNULL) -+ { -+ /* Reserve space for Link(). */ -+ *ReservedTail = 8; -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Alignment=%lu *ReservedHead=%lu *ReservedTail=%lu", -+ gcmOPT_VALUE(Alignment), gcmOPT_VALUE(ReservedHead), -+ gcmOPT_VALUE(ReservedTail)); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckHARDWARE_QuerySystemMemory -+** -+** Query the command buffer alignment and number of reserved bytes. -+** -+** INPUT: -+** -+** gckHARDWARE Harwdare -+** Pointer to an gckHARDWARE object. -+** -+** OUTPUT: -+** -+** gctSIZE_T * SystemSize -+** Pointer to a variable that receives the maximum size of the system -+** memory. -+** -+** gctUINT32 * SystemBaseAddress -+** Poinetr to a variable that receives the base address for system -+** memory. -+*/ -+gceSTATUS -+gckHARDWARE_QuerySystemMemory( -+ IN gckHARDWARE Hardware, -+ OUT gctSIZE_T * SystemSize, -+ OUT gctUINT32 * SystemBaseAddress -+ ) -+{ -+ gcmkHEADER_ARG("Hardware=0x%x", Hardware); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ if (SystemSize != gcvNULL) -+ { -+ /* Maximum system memory can be 2GB. */ -+ *SystemSize = 1U << 31; -+ } -+ -+ if (SystemBaseAddress != gcvNULL) -+ { -+ /* Set system memory base address. */ -+ *SystemBaseAddress = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31))); -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*SystemSize=%lu *SystemBaseAddress=%lu", -+ gcmOPT_VALUE(SystemSize), gcmOPT_VALUE(SystemBaseAddress)); -+ return gcvSTATUS_OK; -+} -+ -+#if gcdENABLE_3D -+/******************************************************************************* -+** -+** gckHARDWARE_QueryShaderCaps -+** -+** Query the shader capabilities. -+** -+** INPUT: -+** -+** Nothing. -+** -+** OUTPUT: -+** -+** gctUINT * VertexUniforms -+** Pointer to a variable receiving the number of uniforms in the vertex -+** shader. -+** -+** gctUINT * FragmentUniforms -+** Pointer to a variable receiving the number of uniforms in the -+** fragment shader. -+** -+** gctBOOL * UnifiedUnforms -+** Pointer to a variable receiving whether the uniformas are unified. -+*/ -+gceSTATUS -+gckHARDWARE_QueryShaderCaps( -+ IN gckHARDWARE Hardware, -+ OUT gctUINT * VertexUniforms, -+ OUT gctUINT * FragmentUniforms, -+ OUT gctBOOL * UnifiedUnforms -+ ) -+{ -+ gctBOOL unifiedConst; -+ gctUINT32 vsConstMax; -+ gctUINT32 psConstMax; -+ gctUINT32 vsConstBase; -+ gctUINT32 psConstBase; -+ gctUINT32 ConstMax; -+ -+ gcmkHEADER_ARG("Hardware=0x%x VertexUniforms=0x%x " -+ "FragmentUniforms=0x%x UnifiedUnforms=0x%x", -+ Hardware, VertexUniforms, -+ FragmentUniforms, UnifiedUnforms); -+ -+ {if (Hardware->identity.numConstants > 256){ unifiedConst = gcvTRUE; vsConstBase = 0xC000; psConstBase = 0xC000; ConstMax = Hardware->identity.numConstants; vsConstMax = 256; psConstMax = ConstMax - vsConstMax;}else if (Hardware->identity.numConstants == 256){ if (Hardware->identity.chipModel == gcv2000 && Hardware->identity.chipRevision == 0x5118) { unifiedConst = gcvFALSE; vsConstBase = 0x1400; psConstBase = 0x1C00; vsConstMax = 256; psConstMax = 64; ConstMax = 320; } else { unifiedConst = gcvFALSE; vsConstBase = 0x1400; psConstBase = 0x1C00; vsConstMax = 256; psConstMax = 256; ConstMax = 512; }}else{ unifiedConst = gcvFALSE; vsConstBase = 0x1400; psConstBase = 0x1C00; vsConstMax = 168; psConstMax = 64; ConstMax = 232;}}; -+ -+ if (VertexUniforms != gcvNULL) -+ { -+ /* Return the vs shader const count. */ -+ *VertexUniforms = vsConstMax; -+ } -+ -+ if (FragmentUniforms != gcvNULL) -+ { -+ /* Return the ps shader const count. */ -+ *FragmentUniforms = psConstMax; -+ } -+ -+ if (UnifiedUnforms != gcvNULL) -+ { -+ /* Return whether the uniformas are unified. */ -+ *UnifiedUnforms = unifiedConst; -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+#endif -+ -+/******************************************************************************* -+** -+** gckHARDWARE_SetMMU -+** -+** Set the page table base address. -+** -+** INPUT: -+** -+** gckHARDWARE Harwdare -+** Pointer to an gckHARDWARE object. -+** -+** gctPOINTER Logical -+** Logical address of the page table. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckHARDWARE_SetMMU( -+ IN gckHARDWARE Hardware, -+ IN gctPOINTER Logical -+ ) -+{ -+ gceSTATUS status; -+ gctUINT32 address = 0; -+ gctUINT32 idle; -+ gctUINT32 timer = 0, delay = 1; -+ -+ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x", Hardware, Logical); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ if (Hardware->mmuVersion == 0) -+ { -+ gcmkVERIFY_ARGUMENT(Logical != gcvNULL); -+ -+ /* Convert the logical address into physical address. */ -+ gcmkONERROR(gckOS_GetPhysicalAddress(Hardware->os, Logical, &address)); -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "Setting page table to 0x%08X", -+ address); -+ -+ /* Write the AQMemoryFePageTable register. */ -+ gcmkONERROR( -+ gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00400, -+ address)); -+ -+ /* Write the AQMemoryRaPageTable register. */ -+ gcmkONERROR( -+ gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00410, -+ address)); -+ -+ /* Write the AQMemoryTxPageTable register. */ -+ gcmkONERROR( -+ gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00404, -+ address)); -+ -+ -+ /* Write the AQMemoryPePageTable register. */ -+ gcmkONERROR( -+ gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00408, -+ address)); -+ -+ /* Write the AQMemoryPezPageTable register. */ -+ gcmkONERROR( -+ gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x0040C, -+ address)); -+ } -+ else if (Hardware->enableMMU == gcvTRUE) -+ { -+ /* Execute prepared command sequence. */ -+ gcmkONERROR(gckHARDWARE_Execute( -+ Hardware, -+ Hardware->functions[gcvHARDWARE_FUNCTION_MMU].address, -+ Hardware->functions[gcvHARDWARE_FUNCTION_MMU].bytes -+ )); -+ -+ /* Wait until MMU configure finishes. */ -+ do -+ { -+ gckOS_Delay(Hardware->os, delay); -+ -+ gcmkONERROR(gckOS_ReadRegisterEx( -+ Hardware->os, -+ Hardware->core, -+ 0x00004, -+ &idle)); -+ -+ timer += delay; -+ delay *= 2; -+ -+#if gcdGPU_TIMEOUT -+ if (timer >= Hardware->kernel->timeOut) -+ { -+ /* Even if hardware is not reset correctly, let software -+ ** continue to avoid software stuck. Software will timeout again -+ ** and try to recover GPU in next timeout. -+ */ -+ gcmkONERROR(gcvSTATUS_DEVICE); -+ } -+#endif -+ } -+ while (!(((((gctUINT32) (idle)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) )); -+ -+ /* Enable MMU. */ -+ gcmkONERROR(gckOS_WriteRegisterEx( -+ Hardware->os, -+ Hardware->core, -+ 0x0018C, -+ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (gcvTRUE) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) -+ )); -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckHARDWARE_FlushMMU -+** -+** Flush the page table. -+** -+** INPUT: -+** -+** gckHARDWARE Harwdare -+** Pointer to an gckHARDWARE object. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckHARDWARE_FlushMMU( -+ IN gckHARDWARE Hardware -+ ) -+{ -+ gceSTATUS status; -+ gckCOMMAND command; -+ gctUINT32_PTR buffer; -+ gctUINT32 bufferSize; -+ gctPOINTER pointer = gcvNULL; -+ gctUINT32 flushSize; -+ gctUINT32 count; -+ gctUINT32 physical; -+ -+ gcmkHEADER_ARG("Hardware=0x%x", Hardware); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ /* Verify the gckCOMMAND object pointer. */ -+ command = Hardware->kernel->command; -+ -+ /* Flush the memory controller. */ -+ if (Hardware->mmuVersion == 0) -+ { -+ gcmkONERROR(gckCOMMAND_Reserve( -+ command, 8, &pointer, &bufferSize -+ )); -+ -+ buffer = (gctUINT32_PTR) pointer; -+ -+ buffer[0] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E04) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))); -+ -+ buffer[1] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))); -+ -+ gcmkONERROR(gckCOMMAND_Execute(command, 8)); -+ } -+ else -+ { -+ flushSize = 16 * 4; -+ -+ gcmkONERROR(gckCOMMAND_Reserve( -+ command, flushSize, &pointer, &bufferSize -+ )); -+ -+ buffer = (gctUINT32_PTR) pointer; -+ -+ count = ((gctUINT)bufferSize - flushSize + 7) >> 3; -+ -+ gcmkONERROR(gckOS_GetPhysicalAddress(command->os, buffer, &physical)); -+ -+ /* Flush cache. */ -+ buffer[0] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E03) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); -+ -+ buffer[1] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))); -+ -+ /* Arm the PE-FE Semaphore. */ -+ buffer[2] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); -+ -+ buffer[3] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); -+ -+ /* STALL FE until PE is done flushing. */ -+ buffer[4] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))); -+ -+ buffer[5] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); -+ -+ /* LINK to next slot to flush FE FIFO. */ -+ buffer[6] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (4) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); -+ -+ buffer[7] -+ = physical + 8 * gcmSIZEOF(gctUINT32); -+ -+ /* Flush MMU cache. */ -+ buffer[8] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0061) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))); -+ -+ buffer[9] -+ = (((((gctUINT32) (~0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) & ((((gctUINT32) (~0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7)))); -+ -+ /* Arm the PE-FE Semaphore. */ -+ buffer[10] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); -+ -+ buffer[11] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); -+ -+ /* STALL FE until PE is done flushing. */ -+ buffer[12] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))); -+ -+ buffer[13] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); -+ -+ /* LINK to next slot to flush FE FIFO. */ -+ buffer[14] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (count) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); -+ -+ buffer[15] -+ = physical + flushSize; -+ -+ gcmkONERROR(gckCOMMAND_Execute(command, flushSize)); -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckHARDWARE_SetMMUStates( -+ IN gckHARDWARE Hardware, -+ IN gctPOINTER MtlbAddress, -+ IN gceMMU_MODE Mode, -+ IN gctPOINTER SafeAddress, -+ IN gctPOINTER Logical, -+ IN OUT gctUINT32 * Bytes -+ ) -+{ -+ gceSTATUS status; -+ gctUINT32 config, address; -+ gctUINT32_PTR buffer; -+ gctBOOL ace; -+ gctUINT32 reserveBytes = 16 + 4 * 4; -+ -+ gctBOOL config2D; -+ -+ gcmkHEADER_ARG("Hardware=0x%x", Hardware); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ gcmkVERIFY_ARGUMENT(Hardware->mmuVersion != 0); -+ -+ ace = gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_ACE); -+ -+ if (ace) -+ { -+ reserveBytes += 8; -+ } -+ -+ config2D = gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_PIPE_3D) -+ && gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_PIPE_2D); -+ -+ if (config2D) -+ { -+ reserveBytes += -+ /* Pipe Select. */ -+ 4 * 4 -+ /* Configure MMU States. */ -+ + 4 * 4 -+ /* Semaphore stall */ -+ + 4 * 8; -+ } -+ -+ /* Convert logical address into physical address. */ -+ gcmkONERROR( -+ gckOS_GetPhysicalAddress(Hardware->os, MtlbAddress, &config)); -+ -+ gcmkONERROR( -+ gckOS_GetPhysicalAddress(Hardware->os, SafeAddress, &address)); -+ -+ if (address & 0x3F) -+ { -+ gcmkONERROR(gcvSTATUS_NOT_ALIGNED); -+ } -+ -+ switch (Mode) -+ { -+ case gcvMMU_MODE_1K: -+ if (config & 0x3FF) -+ { -+ gcmkONERROR(gcvSTATUS_NOT_ALIGNED); -+ } -+ -+ config |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))); -+ -+ break; -+ -+ case gcvMMU_MODE_4K: -+ if (config & 0xFFF) -+ { -+ gcmkONERROR(gcvSTATUS_NOT_ALIGNED); -+ } -+ -+ config |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))); -+ -+ break; -+ -+ default: -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ } -+ -+ if (Logical != gcvNULL) -+ { -+ buffer = Logical; -+ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0061) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))); -+ -+ *buffer++ = config; -+ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0060) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))); -+ -+ *buffer++ = address; -+ -+ if (ace) -+ { -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0068) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))); -+ -+ *buffer++ = 0; -+ } -+ -+ do{*buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));} while(0);; -+ -+ if (config2D) -+ { -+ /* LoadState(AQPipeSelect, 1), pipe. */ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E00) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))); -+ -+ *buffer++ = 0x1; -+ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0061) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))); -+ -+ *buffer++ = config; -+ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0060) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))); -+ -+ *buffer++ = address; -+ -+ do{*buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));} while(0);; -+ -+ /* LoadState(AQPipeSelect, 1), pipe. */ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E00) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))); -+ -+ *buffer++ = 0x0; -+ -+ do{*buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))); *buffer++ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8)));} while(0);; -+ } -+ -+ } -+ -+ if (Bytes != gcvNULL) -+ { -+ *Bytes = reserveBytes; -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER_NO(); -+ return status; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+#if gcdPROCESS_ADDRESS_SPACE -+/******************************************************************************* -+** -+** gckHARDWARE_ConfigMMU -+** -+** Append a MMU Configuration command sequence at the specified location in the command -+** queue. That command sequence consists of mmu configuration, LINK and WAIT/LINK. -+** LINK is fetched and paresed with new mmu configuration. -+** -+** If MMU Configuration is not changed between commit, change last WAIT/LINK to -+** link to ENTRY. -+** -+** -+-----------+-----------+----------------------------------------- -+** | WAIT/LINK | WAIT/LINK | -+** -+-----------+-----------+----------------------------------------- -+** | /|\ -+** \|/ | -+** +--------------------+ -+** | ENTRY | ... | LINK | -+** +--------------------+ -+** -+** If MMU Configuration is changed between commit, change last WAIT/LINK to -+** link to MMU CONFIGURATION command sequence, and there are an EVNET and -+** an END at the end of this command sequence, when interrupt handler -+** receives this event, it will start FE at ENTRY to continue the command -+** buffer execution. -+** -+** -+-----------+-------------------+---------+---------+-----------+-- -+** | WAIT/LINK | MMU CONFIGURATION | EVENT | END | WAIT/LINK | -+** -+-----------+-------------------+---------+---------+-----------+-- -+** | /|\ /|\ -+** +-------------+ | -+** +--------------------+ -+** | ENTRY | ... | LINK | -+** +--------------------+ -+** INPUT: -+** -+** gckHARDWARE Hardware -+** Pointer to an gckHARDWARE object. -+** -+** gctPOINTER Logical -+** Pointer to the current location inside the command queue to append -+** command sequence at or gcvNULL just to query the size of the -+** command sequence. -+** -+** gctPOINTER MtlbLogical -+** Pointer to the current Master TLB. -+** -+** gctUINT32 Offset -+** Offset into command buffer required for alignment. -+** -+** gctSIZE_T * Bytes -+** Pointer to the number of bytes available for the command -+** sequence. If 'Logical' is gcvNULL, this argument will be ignored. -+** -+** OUTPUT: -+** -+** gctSIZE_T * Bytes -+** Pointer to a variable that will receive the number of bytes required -+** by the command sequence. If 'Bytes' is gcvNULL, nothing will -+** be returned. -+** -+** gctUINT32 * WaitLinkOffset -+** Pointer to a variable that will receive the offset of the WAIT/LINK command -+** from the specified logcial pointer. -+** If 'WaitLinkOffset' is gcvNULL nothing will be returned. -+** -+** gctSIZE_T * WaitLinkBytes -+** Pointer to a variable that will receive the number of bytes used by -+** the WAIT command. -+** If 'WaitLinkBytes' is gcvNULL nothing will be returned. -+*/ -+gceSTATUS -+gckHARDWARE_ConfigMMU( -+ IN gckHARDWARE Hardware, -+ IN gctPOINTER Logical, -+ IN gctPOINTER MtlbLogical, -+ IN gctUINT32 Offset, -+ IN OUT gctSIZE_T * Bytes, -+ OUT gctSIZE_T * WaitLinkOffset, -+ OUT gctSIZE_T * WaitLinkBytes -+ ) -+{ -+ gceSTATUS status; -+ gctSIZE_T bytes, bytesAligned; -+ gctUINT32 config; -+ gctUINT32_PTR buffer = (gctUINT32_PTR) Logical; -+ gctUINT32 physical; -+ gctUINT32 event; -+ -+ gcmkHEADER_ARG("Hardware=0x%08X Logical=0x%08x MtlbLogical=0x%08X", -+ Hardware, Logical, MtlbLogical); -+ -+ bytes -+ /* Flush cache states. */ -+ = 18 * 4 -+ /* MMU configuration states. */ -+ + 6 * 4 -+ /* EVENT. */ -+ + 2 * 4 -+ /* END. */ -+ + 2 * 4 -+ /* WAIT/LINK. */ -+ + 4 * 4; -+ -+ /* Compute number of bytes required. */ -+ bytesAligned = gcmALIGN(Offset + bytes, 8) - Offset; -+ -+ if (buffer != gcvNULL) -+ { -+ if (MtlbLogical == gcvNULL) -+ { -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ } -+ -+ /* Get physical address of this command buffer segment. */ -+ gcmkONERROR(gckOS_GetPhysicalAddress(Hardware->os, buffer, &physical)); -+ -+ /* Get physical address of Master TLB. */ -+ gcmkONERROR(gckOS_GetPhysicalAddress(Hardware->os, MtlbLogical, &config)); -+ -+ config |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))); -+ -+ /* Flush cache. */ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E03) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); -+ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))); -+ -+ /* Flush tile status cache. */ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0594) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); -+ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))); -+ -+ /* Arm the PE-FE Semaphore. */ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); -+ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); -+ -+ /* STALL FE until PE is done flushing. */ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))); -+ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); -+ -+ /* LINK to next slot to flush FE FIFO. */ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (4) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); -+ -+ *buffer++ -+ = physical + 10 * gcmSIZEOF(gctUINT32); -+ -+ /* Configure MMU. */ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0061) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))); -+ -+ *buffer++ -+ = (((((gctUINT32) (~0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) & ((((gctUINT32) (~0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7)))); -+ -+ /* Arm the PE-FE Semaphore. */ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); -+ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); -+ -+ /* STALL FE until PE is done flushing. */ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))); -+ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); -+ -+ /* LINK to next slot to flush FE FIFO. */ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); -+ -+ *buffer++ -+ = physical + 18 * 4; -+ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0061) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))); -+ -+ *buffer++ -+ = config; -+ -+ /* Arm the PE-FE Semaphore. */ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); -+ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); -+ -+ /* STALL FE until PE is done flushing. */ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))); -+ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); -+ -+ /* Event 29. */ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E01) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))); -+ -+ event = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))); -+ event = ((((gctUINT32) (event)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (29) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))); -+ -+ *buffer++ -+ = event; -+ -+ /* Append END. */ -+ *buffer++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x02 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))); -+ } -+ -+ if (Bytes != gcvNULL) -+ { -+ *Bytes = bytesAligned; -+ } -+ -+ if (WaitLinkOffset != gcvNULL) -+ { -+ *WaitLinkOffset = bytes - 4 * 4; -+ } -+ -+ if (WaitLinkBytes != gcvNULL) -+ { -+ *WaitLinkBytes = 4 * 4; -+ } -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ gcmkFOOTER(); -+ return status; -+} -+#endif -+ -+/******************************************************************************* -+** -+** gckHARDWARE_BuildVirtualAddress -+** -+** Build a virtual address. -+** -+** INPUT: -+** -+** gckHARDWARE Harwdare -+** Pointer to an gckHARDWARE object. -+** -+** gctUINT32 Index -+** Index into page table. -+** -+** gctUINT32 Offset -+** Offset into page. -+** -+** OUTPUT: -+** -+** gctUINT32 * Address -+** Pointer to a variable receiving te hardware address. -+*/ -+gceSTATUS -+gckHARDWARE_BuildVirtualAddress( -+ IN gckHARDWARE Hardware, -+ IN gctUINT32 Index, -+ IN gctUINT32 Offset, -+ OUT gctUINT32 * Address -+ ) -+{ -+ gcmkHEADER_ARG("Hardware=0x%x Index=%u Offset=%u", Hardware, Index, Offset); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ gcmkVERIFY_ARGUMENT(Address != gcvNULL); -+ -+ /* Build virtual address. */ -+ *Address = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))) << (0 ? 31:31))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 30:0) - (0 ? 30:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 30:0) - (0 ? 30:0) + 1))))))) << (0 ? 30:0))) | (((gctUINT32) ((gctUINT32) (Offset | (Index << 12)) & ((gctUINT32) ((((1 ? 30:0) - (0 ? 30:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 30:0) - (0 ? 30:0) + 1))))))) << (0 ? 30:0))); -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Address=0x%08x", *Address); -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckHARDWARE_GetIdle( -+ IN gckHARDWARE Hardware, -+ IN gctBOOL Wait, -+ OUT gctUINT32 * Data -+ ) -+{ -+ gceSTATUS status; -+ gctUINT32 idle = 0; -+ gctINT retry, poll, pollCount; -+ gctUINT32 address; -+ -+ gcmkHEADER_ARG("Hardware=0x%x Wait=%d", Hardware, Wait); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ gcmkVERIFY_ARGUMENT(Data != gcvNULL); -+ -+ -+ /* If we have to wait, try 100 polls per millisecond. */ -+ pollCount = Wait ? 100 : 1; -+ -+ /* At most, try for 1 second. */ -+ for (retry = 0; retry < 1000; ++retry) -+ { -+ /* If we have to wait, try 100 polls per millisecond. */ -+ for (poll = pollCount; poll > 0; --poll) -+ { -+ /* Read register. */ -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00004, &idle)); -+ -+ /* Read the current FE address. */ -+ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00664, -+ &address)); -+ -+ -+ /* See if we have to wait for FE idle. */ -+ if (_IsGPUIdle(idle) -+ && (address == Hardware->lastEnd + 8) -+ ) -+ { -+ /* FE is idle. */ -+ break; -+ } -+ } -+ -+ /* Check if we need to wait for FE and FE is busy. */ -+ if (Wait && !_IsGPUIdle(idle)) -+ { -+ /* Wait a little. */ -+ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_HARDWARE, -+ "%s: Waiting for idle: 0x%08X", -+ __FUNCTION__, idle); -+ -+ gcmkVERIFY_OK(gckOS_Delay(Hardware->os, 1)); -+ } -+ else -+ { -+ break; -+ } -+ } -+ -+ /* Return idle to caller. */ -+ *Data = idle; -+ -+#if defined(EMULATOR) -+ /* Wait a little while until CModel FE gets END. -+ * END is supposed to be appended by caller. -+ */ -+ gckOS_Delay(gcvNULL, 100); -+#endif -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Data=0x%08x", *Data); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/* Flush the caches. */ -+gceSTATUS -+gckHARDWARE_Flush( -+ IN gckHARDWARE Hardware, -+ IN gceKERNEL_FLUSH Flush, -+ IN gctPOINTER Logical, -+ IN OUT gctUINT32 * Bytes -+ ) -+{ -+ gctUINT32 pipe; -+ gctUINT32 flush = 0; -+ gctBOOL flushTileStatus; -+ gctUINT32_PTR logical = (gctUINT32_PTR) Logical; -+ gceSTATUS status; -+ gctUINT32 reserveBytes -+ /* Semaphore/Stall */ -+ = 4 * gcmSIZEOF(gctUINT32); -+ -+ gcmkHEADER_ARG("Hardware=0x%x Flush=0x%x Logical=0x%x *Bytes=%lu", -+ Hardware, Flush, Logical, gcmOPT_VALUE(Bytes)); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ /* Get current pipe. */ -+ pipe = Hardware->kernel->command->pipeSelect; -+ -+ /* Flush tile status cache. */ -+ flushTileStatus = Flush & gcvFLUSH_TILE_STATUS; -+ -+ /* Flush 3D color cache. */ -+ if ((Flush & gcvFLUSH_COLOR) && (pipe == 0x0)) -+ { -+ flush |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))); -+ } -+ -+ /* Flush 3D depth cache. */ -+ if ((Flush & gcvFLUSH_DEPTH) && (pipe == 0x0)) -+ { -+ flush |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))); -+ } -+ -+ /* Flush 3D texture cache. */ -+ if ((Flush & gcvFLUSH_TEXTURE) && (pipe == 0x0)) -+ { -+ flush |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))); -+ } -+ -+ /* Flush 2D cache. */ -+ if ((Flush & gcvFLUSH_2D) && (pipe == 0x1)) -+ { -+ flush |= ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))); -+ } -+ -+ /* Determine reserve bytes. */ -+ if (flush) -+ { -+ reserveBytes += 2 * gcmSIZEOF(gctUINT32); -+ } -+ -+ if (flushTileStatus) -+ { -+ reserveBytes += 2 * gcmSIZEOF(gctUINT32); -+ } -+ -+ /* See if there is a valid flush. */ -+ if ((flush == 0) && (flushTileStatus == gcvFALSE)) -+ { -+ if (Bytes != gcvNULL) -+ { -+ /* No bytes required. */ -+ *Bytes = 0; -+ } -+ } -+ -+ else -+ { -+ /* Copy to command queue. */ -+ if (Logical != gcvNULL) -+ { -+ if (*Bytes < reserveBytes) -+ { -+ /* Command queue too small. */ -+ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL); -+ } -+ -+ if (flush) -+ { -+ /* Append LOAD_STATE to AQFlush. */ -+ *logical++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E03) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))); -+ -+ *logical++ -+ = flush; -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "0x%x: FLUSH 0x%x", logical - 1, flush); -+ } -+ -+ if (flushTileStatus) -+ { -+ *logical++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0594) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))); -+ -+ *logical++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))); -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "0x%x: FLUSH TILE STATUS 0x%x", logical - 1, logical[-1]); -+ } -+ -+ /* Semaphore. */ -+ *logical++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E02) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); -+ -+ *logical++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); -+ -+ /* Stall. */ -+ *logical++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x09 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))); -+ -+ *logical++ -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) (0x05 & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) (0x07 & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); -+ } -+ -+ if (Bytes != gcvNULL) -+ { -+ /* bytes required. */ -+ *Bytes = reserveBytes; -+ } -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes)); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckHARDWARE_SetFastClear( -+ IN gckHARDWARE Hardware, -+ IN gctINT Enable, -+ IN gctINT Compression -+ ) -+{ -+#if gcdENABLE_3D -+ gctUINT32 debug; -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Hardware=0x%x Enable=%d Compression=%d", -+ Hardware, Enable, Compression); -+ -+ /* Only process if fast clear is available. */ -+ if ((((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) )) -+ { -+ if (Enable == -1) -+ { -+ /* Determine automatic value for fast clear. */ -+ Enable = ((Hardware->identity.chipModel != gcv500) -+ || (Hardware->identity.chipRevision >= 3) -+ ) ? 1 : 0; -+ } -+ -+ if (Compression == -1) -+ { -+ /* Determine automatic value for compression. */ -+ Compression = Enable -+ & (((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 5:5)) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1)))))) ); -+ } -+ -+ /* Read AQMemoryDebug register. */ -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00414, &debug)); -+ -+ /* Set fast clear bypass. */ -+ debug = ((((gctUINT32) (debug)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20))) | (((gctUINT32) ((gctUINT32) (Enable == 0) & ((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20))); -+ -+ if ( -+ ((((gctUINT32) (Hardware->identity.chipMinorFeatures2)) >> (0 ? 27:27) & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1))))))) || -+ (Hardware->identity.chipModel >= gcv4000)) -+ { -+ /* Set compression bypass. */ -+ debug = ((((gctUINT32) (debug)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1))))))) << (0 ? 21:21))) | (((gctUINT32) ((gctUINT32) (Compression == 0) & ((gctUINT32) ((((1 ? 21:21) - (0 ? 21:21) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 21:21) - (0 ? 21:21) + 1))))))) << (0 ? 21:21))); -+ } -+ -+ /* Write back AQMemoryDebug register. */ -+ gcmkONERROR( -+ gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00414, -+ debug)); -+ -+ /* Store fast clear and comprersison flags. */ -+ Hardware->allowFastClear = Enable; -+ Hardware->allowCompression = Compression; -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "FastClear=%d Compression=%d", Enable, Compression); -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+#else -+ return gcvSTATUS_OK; -+#endif -+} -+ -+typedef enum -+{ -+ gcvPOWER_FLAG_INITIALIZE = 1 << 0, -+ gcvPOWER_FLAG_STALL = 1 << 1, -+ gcvPOWER_FLAG_STOP = 1 << 2, -+ gcvPOWER_FLAG_START = 1 << 3, -+ gcvPOWER_FLAG_RELEASE = 1 << 4, -+ gcvPOWER_FLAG_DELAY = 1 << 5, -+ gcvPOWER_FLAG_SAVE = 1 << 6, -+ gcvPOWER_FLAG_ACQUIRE = 1 << 7, -+ gcvPOWER_FLAG_POWER_OFF = 1 << 8, -+ gcvPOWER_FLAG_CLOCK_OFF = 1 << 9, -+ gcvPOWER_FLAG_CLOCK_ON = 1 << 10, -+} -+gcePOWER_FLAGS; -+ -+#if gcmIS_DEBUG(gcdDEBUG_TRACE) -+static gctCONST_STRING -+_PowerEnum(gceCHIPPOWERSTATE State) -+{ -+ const gctCONST_STRING states[] = -+ { -+ gcmSTRING(gcvPOWER_ON), -+ gcmSTRING(gcvPOWER_OFF), -+ gcmSTRING(gcvPOWER_IDLE), -+ gcmSTRING(gcvPOWER_SUSPEND), -+ gcmSTRING(gcvPOWER_SUSPEND_ATPOWERON), -+ gcmSTRING(gcvPOWER_OFF_ATPOWERON), -+ gcmSTRING(gcvPOWER_IDLE_BROADCAST), -+ gcmSTRING(gcvPOWER_SUSPEND_BROADCAST), -+ gcmSTRING(gcvPOWER_OFF_BROADCAST), -+ gcmSTRING(gcvPOWER_OFF_RECOVERY), -+ gcmSTRING(gcvPOWER_OFF_TIMEOUT), -+ gcmSTRING(gcvPOWER_ON_AUTO) -+ }; -+ -+ if ((State >= gcvPOWER_ON) && (State <= gcvPOWER_ON_AUTO)) -+ { -+ return states[State - gcvPOWER_ON]; -+ } -+ -+ return "unknown"; -+} -+#endif -+ -+/******************************************************************************* -+** -+** gckHARDWARE_SetPowerManagementState -+** -+** Set GPU to a specified power state. -+** -+** INPUT: -+** -+** gckHARDWARE Harwdare -+** Pointer to an gckHARDWARE object. -+** -+** gceCHIPPOWERSTATE State -+** Power State. -+** -+*/ -+gceSTATUS -+gckHARDWARE_SetPowerManagementState( -+ IN gckHARDWARE Hardware, -+ IN gceCHIPPOWERSTATE State -+ ) -+{ -+ gceSTATUS status; -+ gckCOMMAND command = gcvNULL; -+ gckOS os; -+ gctUINT flag, clock; -+ gctPOINTER buffer; -+ gctUINT32 bytes, requested; -+ gctBOOL acquired = gcvFALSE; -+ gctBOOL mutexAcquired = gcvFALSE; -+ gctBOOL stall = gcvTRUE; -+ gctBOOL broadcast = gcvFALSE; -+#if gcdPOWEROFF_TIMEOUT -+ gctBOOL timeout = gcvFALSE; -+ gctBOOL isAfter = gcvFALSE; -+ gctUINT32 currentTime; -+#endif -+ gctUINT32 process, thread; -+ gctBOOL commitEntered = gcvFALSE; -+ gctBOOL commandStarted = gcvFALSE; -+ gctBOOL isrStarted = gcvFALSE; -+ -+#if gcdENABLE_PROFILING -+ gctUINT64 time, freq, mutexTime, onTime, stallTime, stopTime, delayTime, -+ initTime, offTime, startTime, totalTime; -+#endif -+ gctBOOL global = gcvFALSE; -+ gctBOOL globalAcquired = gcvFALSE; -+ gctBOOL configMmu = gcvFALSE; -+ -+ /* State transition flags. */ -+ static const gctUINT flags[4][4] = -+ { -+ /* gcvPOWER_ON */ -+ { /* ON */ 0, -+ /* OFF */ gcvPOWER_FLAG_ACQUIRE | -+ gcvPOWER_FLAG_STALL | -+ gcvPOWER_FLAG_STOP | -+ gcvPOWER_FLAG_POWER_OFF | -+ gcvPOWER_FLAG_CLOCK_OFF, -+ /* IDLE */ gcvPOWER_FLAG_ACQUIRE | -+ gcvPOWER_FLAG_STALL, -+ /* SUSPEND */ gcvPOWER_FLAG_ACQUIRE | -+ gcvPOWER_FLAG_STALL | -+ gcvPOWER_FLAG_STOP | -+ gcvPOWER_FLAG_CLOCK_OFF, -+ }, -+ -+ /* gcvPOWER_OFF */ -+ { /* ON */ gcvPOWER_FLAG_INITIALIZE | -+ gcvPOWER_FLAG_START | -+ gcvPOWER_FLAG_RELEASE | -+ gcvPOWER_FLAG_DELAY, -+ /* OFF */ 0, -+ /* IDLE */ gcvPOWER_FLAG_INITIALIZE | -+ gcvPOWER_FLAG_START | -+ gcvPOWER_FLAG_DELAY, -+ /* SUSPEND */ gcvPOWER_FLAG_INITIALIZE | -+ gcvPOWER_FLAG_CLOCK_OFF, -+ }, -+ -+ /* gcvPOWER_IDLE */ -+ { /* ON */ gcvPOWER_FLAG_RELEASE, -+ /* OFF */ gcvPOWER_FLAG_STOP | -+ gcvPOWER_FLAG_POWER_OFF | -+ gcvPOWER_FLAG_CLOCK_OFF, -+ /* IDLE */ 0, -+ /* SUSPEND */ gcvPOWER_FLAG_STOP | -+ gcvPOWER_FLAG_CLOCK_OFF, -+ }, -+ -+ /* gcvPOWER_SUSPEND */ -+ { /* ON */ gcvPOWER_FLAG_START | -+ gcvPOWER_FLAG_RELEASE | -+ gcvPOWER_FLAG_DELAY | -+ gcvPOWER_FLAG_CLOCK_ON, -+ /* OFF */ gcvPOWER_FLAG_SAVE | -+ gcvPOWER_FLAG_POWER_OFF | -+ gcvPOWER_FLAG_CLOCK_OFF, -+ /* IDLE */ gcvPOWER_FLAG_START | -+ gcvPOWER_FLAG_DELAY | -+ gcvPOWER_FLAG_CLOCK_ON, -+ /* SUSPEND */ 0, -+ }, -+ }; -+ -+ /* Clocks. */ -+ static const gctUINT clocks[4] = -+ { -+ /* gcvPOWER_ON */ -+ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | -+ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | -+ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (64) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | -+ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))), -+ -+ /* gcvPOWER_OFF */ -+ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | -+ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | -+ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | -+ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))), -+ -+ /* gcvPOWER_IDLE */ -+ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | -+ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | -+ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | -+ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))), -+ -+ /* gcvPOWER_SUSPEND */ -+ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | -+ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | -+ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | -+ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))), -+ }; -+ -+ gcmkHEADER_ARG("Hardware=0x%x State=%d", Hardware, State); -+#if gcmIS_DEBUG(gcdDEBUG_TRACE) -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "Switching to power state %d(%s)", -+ State, _PowerEnum(State)); -+#endif -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ /* Get the gckOS object pointer. */ -+ os = Hardware->os; -+ gcmkVERIFY_OBJECT(os, gcvOBJ_OS); -+ -+ /* Get the gckCOMMAND object pointer. */ -+ gcmkVERIFY_OBJECT(Hardware->kernel, gcvOBJ_KERNEL); -+ command = Hardware->kernel->command; -+ gcmkVERIFY_OBJECT(command, gcvOBJ_COMMAND); -+ -+ /* Start profiler. */ -+ gcmkPROFILE_INIT(freq, time); -+ -+ /* Convert the broadcast power state. */ -+ switch (State) -+ { -+ case gcvPOWER_SUSPEND_ATPOWERON: -+ /* Convert to SUSPEND and don't wait for STALL. */ -+ State = gcvPOWER_SUSPEND; -+ stall = gcvFALSE; -+ break; -+ -+ case gcvPOWER_OFF_ATPOWERON: -+ /* Convert to OFF and don't wait for STALL. */ -+ State = gcvPOWER_OFF; -+ stall = gcvFALSE; -+ break; -+ -+ case gcvPOWER_IDLE_BROADCAST: -+ /* Convert to IDLE and note we are inside broadcast. */ -+ State = gcvPOWER_IDLE; -+ broadcast = gcvTRUE; -+ break; -+ -+ case gcvPOWER_SUSPEND_BROADCAST: -+ /* Convert to SUSPEND and note we are inside broadcast. */ -+ State = gcvPOWER_SUSPEND; -+ broadcast = gcvTRUE; -+ break; -+ -+ case gcvPOWER_OFF_BROADCAST: -+ /* Convert to OFF and note we are inside broadcast. */ -+ State = gcvPOWER_OFF; -+ broadcast = gcvTRUE; -+ break; -+ -+ case gcvPOWER_OFF_RECOVERY: -+ /* Convert to OFF and note we are inside recovery. */ -+ State = gcvPOWER_OFF; -+ stall = gcvFALSE; -+ broadcast = gcvTRUE; -+ break; -+ -+ case gcvPOWER_ON_AUTO: -+ /* Convert to ON and note we are inside recovery. */ -+ State = gcvPOWER_ON; -+ break; -+ -+ case gcvPOWER_ON: -+ case gcvPOWER_IDLE: -+ case gcvPOWER_SUSPEND: -+ case gcvPOWER_OFF: -+ /* Mark as global power management. */ -+ global = gcvTRUE; -+ break; -+ -+#if gcdPOWEROFF_TIMEOUT -+ case gcvPOWER_OFF_TIMEOUT: -+ /* Convert to OFF and note we are inside broadcast. */ -+ State = gcvPOWER_OFF; -+ broadcast = gcvTRUE; -+ /* Check time out */ -+ timeout = gcvTRUE; -+ break; -+#endif -+ -+ default: -+ break; -+ } -+ -+ if (Hardware->powerManagement == gcvFALSE -+ && State != gcvPOWER_ON -+ ) -+ { -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ } -+ -+ /* Get current process and thread IDs. */ -+ gcmkONERROR(gckOS_GetProcessID(&process)); -+ gcmkONERROR(gckOS_GetThreadID(&thread)); -+ -+ if (broadcast) -+ { -+ /* Try to acquire the power mutex. */ -+ status = gckOS_AcquireMutex(os, Hardware->powerMutex, 3); -+ -+ if (status == gcvSTATUS_TIMEOUT) -+ { -+ /* Check if we already own this mutex. */ -+ if ((Hardware->powerProcess == process) -+ && (Hardware->powerThread == thread) -+ ) -+ { -+ /* Bail out on recursive power management. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ } -+ else if (State != gcvPOWER_ON) -+ { -+ /* Called from IST, -+ ** so waiting here will cause deadlock, -+ ** if lock holder call gckCOMMAND_Stall() */ -+ gcmkONWARNING(gcvSTATUS_INVALID_REQUEST); -+ } -+ else -+ { -+ /* Acquire the power mutex. */ -+ gcmkONERROR(gckOS_AcquireMutex(os, -+ Hardware->powerMutex, -+ gcvINFINITE)); -+ } -+ } -+ } -+ else -+ { -+ /* Acquire the power mutex. */ -+ gcmkONERROR(gckOS_AcquireMutex(os, Hardware->powerMutex, gcvINFINITE)); -+ } -+ -+ /* Before we grab locks see if this is actually a needed change */ -+ if (State == Hardware->chipPowerState) -+ { -+ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex)); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ } -+ -+ /* Get time until mutex acquired. */ -+ gcmkPROFILE_QUERY(time, mutexTime); -+ -+ Hardware->powerProcess = process; -+ Hardware->powerThread = thread; -+ mutexAcquired = gcvTRUE; -+ -+ /* Grab control flags and clock. */ -+ flag = flags[Hardware->chipPowerState][State]; -+ clock = clocks[State]; -+ -+#if gcdENABLE_FSCALE_VAL_ADJUST -+ if (State == gcvPOWER_ON) -+ { -+ clock = ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (Hardware->powerOnFscaleVal) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))); -+ } -+#endif -+ -+ if (State == gcvPOWER_SUSPEND && Hardware->chipPowerState == gcvPOWER_OFF && broadcast) -+ { -+#if gcdPOWER_SUSPEND_WHEN_IDLE -+ /* Do nothing */ -+ -+ /* Release the power mutex. */ -+ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex)); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+#else -+ /* Clock should be on when switch power from off to suspend */ -+ clock = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | -+ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | -+ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | -+ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) ; -+#endif -+ } -+ -+#if gcdPOWEROFF_TIMEOUT -+ if (timeout) -+ { -+ gcmkONERROR(gckOS_GetTicks(¤tTime)); -+ -+ gcmkONERROR( -+ gckOS_TicksAfter(Hardware->powerOffTime, currentTime, &isAfter)); -+ -+ /* powerOffTime is pushed forward, give up.*/ -+ if (isAfter -+ /* Expect a transition start from IDLE or SUSPEND. */ -+ || (Hardware->chipPowerState == gcvPOWER_ON) -+ || (Hardware->chipPowerState == gcvPOWER_OFF) -+ ) -+ { -+ /* Release the power mutex. */ -+ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex)); -+ -+ /* No need to do anything. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ } -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "Power Off GPU[%d] at %u [supposed to be at %u]", -+ Hardware->core, currentTime, Hardware->powerOffTime); -+ } -+ -+ if (State == gcvPOWER_ON || State == gcvPOWER_OFF) -+ { -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, "Cancel powerOfftimer"); -+ -+ /* Cancel running timer when GPU enters ON or OFF. */ -+ gcmkVERIFY_OK(gckOS_StopTimer(os, Hardware->powerOffTimer)); -+ } -+#endif -+ -+ if (flag == 0) -+ { -+ /* Release the power mutex. */ -+ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex)); -+ -+ /* No need to do anything. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ } -+ -+ /* If this is an internal power management, we have to check if we can grab -+ ** the global power semaphore. If we cannot, we have to wait until the -+ ** external world changes power management. */ -+ if (!global) -+ { -+ /* Try to acquire the global semaphore. */ -+ status = gckOS_TryAcquireSemaphore(os, Hardware->globalSemaphore); -+ if (status == gcvSTATUS_TIMEOUT) -+ { -+ if (State == gcvPOWER_IDLE || State == gcvPOWER_SUSPEND) -+ { -+ /* Called from thread routine which should NEVER sleep.*/ -+ gcmkONWARNING(gcvSTATUS_INVALID_REQUEST); -+ } -+ -+ /* Release the power mutex. */ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "Releasing the power mutex."); -+ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex)); -+ mutexAcquired = gcvFALSE; -+ -+ /* Wait for the semaphore. */ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "Waiting for global semaphore."); -+ gcmkONERROR(gckOS_AcquireSemaphore(os, Hardware->globalSemaphore)); -+ globalAcquired = gcvTRUE; -+ -+ /* Acquire the power mutex. */ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "Reacquiring the power mutex."); -+ gcmkONERROR(gckOS_AcquireMutex(os, -+ Hardware->powerMutex, -+ gcvINFINITE)); -+ mutexAcquired = gcvTRUE; -+ -+ /* chipPowerState may be changed by external world during the time -+ ** we give up powerMutex, so updating flag now is necessary. */ -+ flag = flags[Hardware->chipPowerState][State]; -+ -+ if (flag == 0) -+ { -+ gcmkONERROR(gckOS_ReleaseSemaphore(os, Hardware->globalSemaphore)); -+ globalAcquired = gcvFALSE; -+ -+ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex)); -+ mutexAcquired = gcvFALSE; -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ } -+ } -+ else -+ { -+ /* Error. */ -+ gcmkONERROR(status); -+ } -+ -+ /* Release the global semaphore again. */ -+ gcmkONERROR(gckOS_ReleaseSemaphore(os, Hardware->globalSemaphore)); -+ globalAcquired = gcvFALSE; -+ } -+ else -+ { -+ if (State == gcvPOWER_OFF || State == gcvPOWER_SUSPEND || State == gcvPOWER_IDLE) -+ { -+ gctBOOL idle; -+ /* Check for idle. */ -+ gcmkONERROR(gckHARDWARE_QueryIdle(Hardware, &idle)); -+ -+ if (!idle) -+ { -+ gcmkONWARNING(gcvSTATUS_CHIP_NOT_READY); -+ } -+ -+ /* Acquire the global semaphore if it has not been acquired. */ -+ status = gckOS_TryAcquireSemaphore(os, Hardware->globalSemaphore); -+ if (status == gcvSTATUS_OK) -+ { -+ globalAcquired = gcvTRUE; -+ } -+ else if (status != gcvSTATUS_TIMEOUT) -+ { -+ /* Other errors. */ -+ gcmkONERROR(status); -+ } -+ /* Ignore gcvSTATUS_TIMEOUT and leave globalAcquired as gcvFALSE. -+ ** gcvSTATUS_TIMEOUT means global semaphore has already -+ ** been acquired before this operation, so even if we fail, -+ ** we should not release it in our error handling. It should be -+ ** released by the next successful global gcvPOWER_ON. */ -+ } -+ -+ /* Global power management can't be aborted, so sync with -+ ** proceeding last commit. */ -+ if (flag & gcvPOWER_FLAG_ACQUIRE) -+ { -+ /* Acquire the power management semaphore. */ -+ gcmkONERROR(gckOS_AcquireSemaphore(os, command->powerSemaphore)); -+ acquired = gcvTRUE; -+ -+ /* avoid acquiring again. */ -+ flag &= ~gcvPOWER_FLAG_ACQUIRE; -+ } -+ } -+ -+ if (flag & (gcvPOWER_FLAG_INITIALIZE | gcvPOWER_FLAG_CLOCK_ON)) -+ { -+ /* Turn on the power. */ -+ gcmkONERROR(gckOS_SetGPUPower(os, Hardware->core, gcvTRUE, gcvTRUE)); -+ -+ /* Mark clock and power as enabled. */ -+ Hardware->clockState = gcvTRUE; -+ Hardware->powerState = gcvTRUE; -+ -+ for (;;) -+ { -+ /* Check if GPU is present and awake. */ -+ status = _IsGPUPresent(Hardware); -+ -+ /* Check if the GPU is not responding. */ -+ if (status == gcvSTATUS_GPU_NOT_RESPONDING) -+ { -+ /* Turn off the power and clock. */ -+ gcmkONERROR(gckOS_SetGPUPower(os, Hardware->core, gcvFALSE, gcvFALSE)); -+ -+ Hardware->clockState = gcvFALSE; -+ Hardware->powerState = gcvFALSE; -+ -+ /* Wait a little. */ -+ gckOS_Delay(os, 1); -+ -+ /* Turn on the power and clock. */ -+ gcmkONERROR(gckOS_SetGPUPower(os, Hardware->core, gcvTRUE, gcvTRUE)); -+ -+ Hardware->clockState = gcvTRUE; -+ Hardware->powerState = gcvTRUE; -+ -+ /* We need to initialize the hardware and start the command -+ * processor. */ -+ flag |= gcvPOWER_FLAG_INITIALIZE | gcvPOWER_FLAG_START; -+ } -+ else -+ { -+ /* Test for error. */ -+ gcmkONERROR(status); -+ -+ /* Break out of loop. */ -+ break; -+ } -+ } -+ } -+ -+ /* Get time until powered on. */ -+ gcmkPROFILE_QUERY(time, onTime); -+ -+ if ((flag & gcvPOWER_FLAG_STALL) && stall) -+ { -+ gctBOOL idle; -+ gctINT32 atomValue; -+ -+ /* For global operation, all pending commits have already been -+ ** blocked by globalSemaphore or powerSemaphore.*/ -+ if (!global) -+ { -+ /* Check commit atom. */ -+ gcmkONERROR(gckOS_AtomGet(os, command->atomCommit, &atomValue)); -+ -+ if (atomValue > 0) -+ { -+ /* Commits are pending - abort power management. */ -+ status = broadcast ? gcvSTATUS_CHIP_NOT_READY -+ : gcvSTATUS_MORE_DATA; -+ goto OnError; -+ } -+ } -+ -+ if (broadcast) -+ { -+ /* Check for idle. */ -+ gcmkONERROR(gckHARDWARE_QueryIdle(Hardware, &idle)); -+ -+ if (!idle) -+ { -+ status = gcvSTATUS_CHIP_NOT_READY; -+ goto OnError; -+ } -+ } -+ -+ else -+ { -+ /* Acquire the command queue. */ -+ gcmkONERROR(gckCOMMAND_EnterCommit(command, gcvTRUE)); -+ commitEntered = gcvTRUE; -+ -+ /* Get the size of the flush command. */ -+ gcmkONERROR(gckHARDWARE_Flush(Hardware, -+ gcvFLUSH_ALL, -+ gcvNULL, -+ &requested)); -+ -+ /* Reserve space in the command queue. */ -+ gcmkONERROR(gckCOMMAND_Reserve(command, -+ requested, -+ &buffer, -+ &bytes)); -+ -+ /* Append a flush. */ -+ gcmkONERROR(gckHARDWARE_Flush( -+ Hardware, gcvFLUSH_ALL, buffer, &bytes -+ )); -+ -+ /* Execute the command queue. */ -+ gcmkONERROR(gckCOMMAND_Execute(command, requested)); -+ -+ /* Release the command queue. */ -+ gcmkONERROR(gckCOMMAND_ExitCommit(command, gcvTRUE)); -+ commitEntered = gcvFALSE; -+ -+ /* Wait to finish all commands. */ -+ gcmkONERROR(gckCOMMAND_Stall(command, gcvTRUE)); -+ } -+ } -+ -+ /* Get time until stalled. */ -+ gcmkPROFILE_QUERY(time, stallTime); -+ -+ if (flag & gcvPOWER_FLAG_ACQUIRE) -+ { -+ /* Acquire the power management semaphore. */ -+ gcmkONERROR(gckOS_AcquireSemaphore(os, command->powerSemaphore)); -+ acquired = gcvTRUE; -+ } -+ -+ if (flag & gcvPOWER_FLAG_STOP) -+ { -+ /* Stop the command parser. */ -+ gcmkONERROR(gckCOMMAND_Stop(command, gcvFALSE)); -+ -+ /* Stop the Isr. */ -+ if (Hardware->stopIsr) -+ { -+ gcmkONERROR(Hardware->stopIsr(Hardware->isrContext, Hardware->core)); -+ } -+ } -+ -+ /* Flush Cache before Power Off. */ -+ if (flag & gcvPOWER_FLAG_POWER_OFF) -+ { -+ if (Hardware->clockState == gcvFALSE) -+ { -+ /* Turn off the GPU power. */ -+ gcmkONERROR( -+ gckOS_SetGPUPower(os, -+ Hardware->core, -+ gcvTRUE, -+ gcvTRUE)); -+ -+ Hardware->clockState = gcvTRUE; -+ -+ if (gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_DYNAMIC_FREQUENCY_SCALING) != gcvTRUE) -+ { -+ /* Write the clock control register. */ -+ gcmkONERROR(gckOS_WriteRegisterEx(os, -+ Hardware->core, -+ 0x00000, -+ clocks[0])); -+ -+ /* Done loading the frequency scaler. */ -+ gcmkONERROR(gckOS_WriteRegisterEx(os, -+ Hardware->core, -+ 0x00000, -+ ((((gctUINT32) (clocks[0])) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))))); -+ } -+ } -+ -+ gcmkONERROR(gckCOMMAND_Start(command)); -+ -+ gcmkONERROR(_FlushCache(Hardware, command)); -+ -+ gckOS_Delay(gcvNULL, 1); -+ -+ /* Stop the command parser. */ -+ gcmkONERROR(gckCOMMAND_Stop(command, gcvFALSE)); -+ -+ flag |= gcvPOWER_FLAG_CLOCK_OFF; -+ } -+ -+ /* Get time until stopped. */ -+ gcmkPROFILE_QUERY(time, stopTime); -+ -+ /* Only process this when hardware is enabled. */ -+ if (Hardware->clockState && Hardware->powerState -+ /* Don't touch clock control if dynamic frequency scaling is available. */ -+ && gckHARDWARE_IsFeatureAvailable(Hardware, gcvFEATURE_DYNAMIC_FREQUENCY_SCALING) != gcvTRUE -+ ) -+ { -+ if (flag & (gcvPOWER_FLAG_POWER_OFF | gcvPOWER_FLAG_CLOCK_OFF)) -+ { -+ if (Hardware->identity.chipModel == gcv4000 -+ && ((Hardware->identity.chipRevision == 0x5208) || (Hardware->identity.chipRevision == 0x5222))) -+ { -+ clock &= ~2U; -+ } -+ } -+ -+ /* Write the clock control register. */ -+ gcmkONERROR(gckOS_WriteRegisterEx(os, -+ Hardware->core, -+ 0x00000, -+ clock)); -+ -+ /* Done loading the frequency scaler. */ -+ gcmkONERROR(gckOS_WriteRegisterEx(os, -+ Hardware->core, -+ 0x00000, -+ ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))))); -+ } -+ -+ if (flag & gcvPOWER_FLAG_DELAY) -+ { -+ /* Wait for the specified amount of time to settle coming back from -+ ** power-off or suspend state. */ -+ gcmkONERROR(gckOS_Delay(os, gcdPOWER_CONTROL_DELAY)); -+ } -+ -+ /* Get time until delayed. */ -+ gcmkPROFILE_QUERY(time, delayTime); -+ -+ if (flag & gcvPOWER_FLAG_INITIALIZE) -+ { -+ /* Initialize hardware. */ -+ gcmkONERROR(gckHARDWARE_InitializeHardware(Hardware)); -+ -+ gcmkONERROR(gckHARDWARE_SetFastClear(Hardware, -+ Hardware->allowFastClear, -+ Hardware->allowCompression)); -+ -+ /* Force the command queue to reload the next context. */ -+ command->currContext = gcvNULL; -+ -+ /* Need to config mmu after command start. */ -+ configMmu = gcvTRUE; -+ } -+ -+ /* Get time until initialized. */ -+ gcmkPROFILE_QUERY(time, initTime); -+ -+ if (flag & (gcvPOWER_FLAG_POWER_OFF | gcvPOWER_FLAG_CLOCK_OFF)) -+ { -+ /* Turn off the GPU power. */ -+ gcmkONERROR( -+ gckOS_SetGPUPower(os, -+ Hardware->core, -+ (flag & gcvPOWER_FLAG_CLOCK_OFF) ? gcvFALSE -+ : gcvTRUE, -+ (flag & gcvPOWER_FLAG_POWER_OFF) ? gcvFALSE -+ : gcvTRUE)); -+ -+ /* Save current hardware power and clock states. */ -+ Hardware->clockState = (flag & gcvPOWER_FLAG_CLOCK_OFF) ? gcvFALSE -+ : gcvTRUE; -+ Hardware->powerState = (flag & gcvPOWER_FLAG_POWER_OFF) ? gcvFALSE -+ : gcvTRUE; -+ } -+ -+ /* Get time until off. */ -+ gcmkPROFILE_QUERY(time, offTime); -+ -+ if (flag & gcvPOWER_FLAG_START) -+ { -+ /* Start the command processor. */ -+ gcmkONERROR(gckCOMMAND_Start(command)); -+ commandStarted = gcvTRUE; -+ -+ if (Hardware->startIsr) -+ { -+ /* Start the Isr. */ -+ gcmkONERROR(Hardware->startIsr(Hardware->isrContext, Hardware->core)); -+ isrStarted = gcvTRUE; -+ } -+ } -+ -+ /* Get time until started. */ -+ gcmkPROFILE_QUERY(time, startTime); -+ -+ if (flag & gcvPOWER_FLAG_RELEASE) -+ { -+ /* Release the power management semaphore. */ -+ gcmkONERROR(gckOS_ReleaseSemaphore(os, command->powerSemaphore)); -+ acquired = gcvFALSE; -+ -+ if (global) -+ { -+ /* Verify global semaphore has been acquired already before -+ ** we release it. -+ ** If it was acquired, gckOS_TryAcquireSemaphore will return -+ ** gcvSTATUS_TIMEOUT and we release it. Otherwise, global -+ ** semaphore will be acquried now, but it still is released -+ ** immediately. */ -+ status = gckOS_TryAcquireSemaphore(os, Hardware->globalSemaphore); -+ if (status != gcvSTATUS_TIMEOUT) -+ { -+ gcmkONERROR(status); -+ } -+ -+ /* Release the global semaphore. */ -+ gcmkONERROR(gckOS_ReleaseSemaphore(os, Hardware->globalSemaphore)); -+ globalAcquired = gcvFALSE; -+ } -+ } -+ -+ /* Save the new power state. */ -+ Hardware->chipPowerState = State; -+ -+#if gcdDVFS -+ if (State == gcvPOWER_ON && Hardware->kernel->dvfs) -+ { -+ gckDVFS_Start(Hardware->kernel->dvfs); -+ } -+#endif -+ -+#if gcdPOWEROFF_TIMEOUT -+ if (State == gcvPOWER_IDLE || State == gcvPOWER_SUSPEND) -+ { -+ gcmkONERROR(gckOS_GetTicks(¤tTime)); -+ -+ Hardware->powerOffTime = currentTime + Hardware->powerOffTimeout; -+ /* Start a timer to power off GPU when GPU enters IDLE or SUSPEND. */ -+ gcmkVERIFY_OK(gckOS_StartTimer(os, -+ Hardware->powerOffTimer, -+ Hardware->powerOffTimeout)); -+ } -+#endif -+ -+ /* Release the power mutex. */ -+ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex)); -+ -+ /* Get total time. */ -+ gcmkPROFILE_QUERY(time, totalTime); -+#if gcdENABLE_PROFILING -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "PROF(%llu): mutex:%llu on:%llu stall:%llu stop:%llu", -+ freq, mutexTime, onTime, stallTime, stopTime); -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ " delay:%llu init:%llu off:%llu start:%llu total:%llu", -+ delayTime, initTime, offTime, startTime, totalTime); -+#endif -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (commandStarted) -+ { -+ gcmkVERIFY_OK(gckCOMMAND_Stop(command, gcvFALSE)); -+ } -+ -+ if (isrStarted) -+ { -+ gcmkVERIFY_OK(Hardware->stopIsr(Hardware->isrContext, Hardware->core)); -+ } -+ -+ if (commitEntered) -+ { -+ /* Release the command queue mutex. */ -+ gcmkVERIFY_OK(gckCOMMAND_ExitCommit(command, gcvTRUE)); -+ } -+ -+ if (acquired) -+ { -+ /* Release semaphore. */ -+ gcmkVERIFY_OK(gckOS_ReleaseSemaphore(Hardware->os, -+ command->powerSemaphore)); -+ } -+ -+ if (globalAcquired) -+ { -+ gcmkVERIFY_OK(gckOS_ReleaseSemaphore(Hardware->os, -+ Hardware->globalSemaphore)); -+ } -+ -+ if (mutexAcquired) -+ { -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex)); -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckHARDWARE_QueryPowerManagementState -+** -+** Get GPU power state. -+** -+** INPUT: -+** -+** gckHARDWARE Harwdare -+** Pointer to an gckHARDWARE object. -+** -+** gceCHIPPOWERSTATE* State -+** Power State. -+** -+*/ -+gceSTATUS -+gckHARDWARE_QueryPowerManagementState( -+ IN gckHARDWARE Hardware, -+ OUT gceCHIPPOWERSTATE* State -+ ) -+{ -+ gcmkHEADER_ARG("Hardware=0x%x", Hardware); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ gcmkVERIFY_ARGUMENT(State != gcvNULL); -+ -+ /* Return the statue. */ -+ *State = Hardware->chipPowerState; -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*State=%d", *State); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckHARDWARE_SetPowerManagement -+** -+** Configure GPU power management function. -+** -+** INPUT: -+** -+** gckHARDWARE Harwdare -+** Pointer to an gckHARDWARE object. -+** -+** gctBOOL PowerManagement -+** Power Mangement State. -+** -+*/ -+gceSTATUS -+gckHARDWARE_SetPowerManagement( -+ IN gckHARDWARE Hardware, -+ IN gctBOOL PowerManagement -+ ) -+{ -+ gcmkHEADER_ARG("Hardware=0x%x", Hardware); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ if(!Hardware->powerManagementLock) -+ { -+ gcmkVERIFY_OK( -+ gckOS_AcquireMutex(Hardware->os, Hardware->powerMutex, gcvINFINITE)); -+ -+ Hardware->powerManagement = PowerManagement; -+ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex)); -+ } -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckHARDWARE_SetPowerManagementLock -+** -+** Disable dynamic GPU power management switch. -+** Only used in driver initialization stage. -+** -+** INPUT: -+** -+** gckHARDWARE Harwdare -+** Pointer to an gckHARDWARE object. -+** -+** gctBOOL Lock -+** Power Mangement Lock State. -+** -+*/ -+gceSTATUS -+gckHARDWARE_SetPowerManagementLock( -+ IN gckHARDWARE Hardware, -+ IN gctBOOL Lock -+ ) -+{ -+ gcmkHEADER_ARG("Hardware=0x%x", Hardware); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ Hardware->powerManagementLock = Lock; -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+/******************************************************************************* -+** -+** gckHARDWARE_SetGpuProfiler -+** -+** Configure GPU profiler function. -+** Only used in driver initialization stage. -+** -+** INPUT: -+** -+** gckHARDWARE Harwdare -+** Pointer to an gckHARDWARE object. -+** -+** gctBOOL GpuProfiler -+** GOU Profiler State. -+** -+*/ -+gceSTATUS -+gckHARDWARE_SetGpuProfiler( -+ IN gckHARDWARE Hardware, -+ IN gctBOOL GpuProfiler -+ ) -+{ -+ gcmkHEADER_ARG("Hardware=0x%x", Hardware); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ if (GpuProfiler == gcvTRUE) -+ { -+ gctUINT32 data = 0; -+ -+ /* Need to disable clock gating when doing profiling. */ -+ gcmkVERIFY_OK( -+ gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ Hardware->powerBaseAddress + -+ 0x00100, -+ &data)); -+ -+ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))); -+ -+ -+ gcmkVERIFY_OK( -+ gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ Hardware->powerBaseAddress -+ + 0x00100, -+ data)); -+ } -+ -+ Hardware->gpuProfiler = GpuProfiler; -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+#if gcdENABLE_FSCALE_VAL_ADJUST -+gceSTATUS -+gckHARDWARE_SetFscaleValue( -+ IN gckHARDWARE Hardware, -+ IN gctUINT32 FscaleValue -+ ) -+{ -+ gceSTATUS status; -+ gctUINT32 clock; -+ gctBOOL acquired = gcvFALSE; -+ -+ gcmkHEADER_ARG("Hardware=0x%x FscaleValue=%d", Hardware, FscaleValue); -+ -+ gcmkVERIFY_ARGUMENT(FscaleValue > 0 && FscaleValue <= 64); -+ -+ gcmkONERROR( -+ gckOS_AcquireMutex(Hardware->os, Hardware->powerMutex, gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ Hardware->powerOnFscaleVal = FscaleValue; -+ -+ if (Hardware->chipPowerState == gcvPOWER_ON) -+ { -+ gctUINT32 data; -+ -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ Hardware->powerBaseAddress -+ + 0x00104, -+ &data)); -+ -+ /* Disable all clock gating. */ -+ gcmkONERROR( -+ gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ Hardware->powerBaseAddress -+ + 0x00104, -+ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1))))))) << (0 ? 7:7))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1))))))) << (0 ? 8:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1))))))) << (0 ? 8:8))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1))))))) << (0 ? 11:11))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1))))))) << (0 ? 11:11))))); -+ -+ clock = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) | (((gctUINT32) ((gctUINT32) (FscaleValue) & ((gctUINT32) ((((1 ? 8:2) - (0 ? 8:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:2) - (0 ? 8:2) + 1))))))) << (0 ? 8:2))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))); -+ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00000, -+ clock)); -+ -+ /* Done loading the frequency scaler. */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00000, -+ ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))))); -+ -+ /* Restore all clock gating. */ -+ gcmkONERROR( -+ gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ Hardware->powerBaseAddress -+ + 0x00104, -+ data)); -+ } -+ -+ gcmkVERIFY(gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex)); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (acquired) -+ { -+ gcmkVERIFY(gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex)); -+ } -+ -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckHARDWARE_GetFscaleValue( -+ IN gckHARDWARE Hardware, -+ IN gctUINT * FscaleValue, -+ IN gctUINT * MinFscaleValue, -+ IN gctUINT * MaxFscaleValue -+ ) -+{ -+ *FscaleValue = Hardware->powerOnFscaleVal; -+ *MinFscaleValue = Hardware->minFscaleValue; -+ *MaxFscaleValue = 64; -+ -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckHARDWARE_SetMinFscaleValue( -+ IN gckHARDWARE Hardware, -+ IN gctUINT MinFscaleValue -+ ) -+{ -+ if (MinFscaleValue >= 1 && MinFscaleValue <= 64) -+ { -+ Hardware->minFscaleValue = MinFscaleValue; -+ } -+ -+ return gcvSTATUS_OK; -+} -+#endif -+ -+#if gcdPOWEROFF_TIMEOUT -+gceSTATUS -+gckHARDWARE_SetPowerOffTimeout( -+ IN gckHARDWARE Hardware, -+ IN gctUINT32 Timeout -+) -+{ -+ gcmkHEADER_ARG("Hardware=0x%x Timeout=%d", Hardware, Timeout); -+ -+ Hardware->powerOffTimeout = Timeout; -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+ -+gceSTATUS -+gckHARDWARE_QueryPowerOffTimeout( -+ IN gckHARDWARE Hardware, -+ OUT gctUINT32* Timeout -+) -+{ -+ gcmkHEADER_ARG("Hardware=0x%x", Hardware); -+ -+ *Timeout = Hardware->powerOffTimeout; -+ -+ gcmkFOOTER_ARG("*Timeout=%d", *Timeout); -+ return gcvSTATUS_OK; -+} -+#endif -+ -+gceSTATUS -+gckHARDWARE_QueryIdle( -+ IN gckHARDWARE Hardware, -+ OUT gctBOOL_PTR IsIdle -+ ) -+{ -+ gceSTATUS status; -+ gctUINT32 idle, address; -+ gctBOOL isIdle; -+ -+#if gcdINTERRUPT_STATISTIC -+ gctINT32 pendingInterrupt; -+#endif -+ -+ gcmkHEADER_ARG("Hardware=0x%x", Hardware); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ gcmkVERIFY_ARGUMENT(IsIdle != gcvNULL); -+ -+ /* We are idle when the power is not ON. */ -+ if (Hardware->chipPowerState != gcvPOWER_ON) -+ { -+ isIdle = gcvTRUE; -+ } -+ -+ else -+ { -+ /* Read idle register. */ -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00004, &idle)); -+ -+ /* Pipe must be idle. */ -+ if (((((((gctUINT32) (idle)) >> (0 ? 1:1)) & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1)))))) ) != 1) -+ || ((((((gctUINT32) (idle)) >> (0 ? 3:3)) & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1)))))) ) != 1) -+ || ((((((gctUINT32) (idle)) >> (0 ? 4:4)) & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1)))))) ) != 1) -+ || ((((((gctUINT32) (idle)) >> (0 ? 5:5)) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1)))))) ) != 1) -+ || ((((((gctUINT32) (idle)) >> (0 ? 6:6)) & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1)))))) ) != 1) -+ || ((((((gctUINT32) (idle)) >> (0 ? 7:7)) & ((gctUINT32) ((((1 ? 7:7) - (0 ? 7:7) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:7) - (0 ? 7:7) + 1)))))) ) != 1) -+ || ((((((gctUINT32) (idle)) >> (0 ? 2:2)) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))) ) != 1) -+ ) -+ { -+ /* Something is busy. */ -+ isIdle = gcvFALSE; -+ } -+ -+ else -+ { -+ /* Read the current FE address. */ -+ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00664, -+ &address)); -+ -+ /* Test if address is inside the last WAIT/LINK sequence. */ -+ if ((address >= Hardware->lastWaitLink) -+ && (address <= Hardware->lastWaitLink + 16) -+ ) -+ { -+ /* FE is in last WAIT/LINK and the pipe is idle. */ -+ isIdle = gcvTRUE; -+ } -+ else -+ { -+ /* FE is not in WAIT/LINK yet. */ -+ isIdle = gcvFALSE; -+ } -+ } -+ } -+ -+#if gcdINTERRUPT_STATISTIC -+ gcmkONERROR(gckOS_AtomGet( -+ Hardware->os, -+ Hardware->kernel->eventObj->interruptCount, -+ &pendingInterrupt -+ )); -+ -+ if (pendingInterrupt) -+ { -+ isIdle = gcvFALSE; -+ } -+#endif -+ -+ *IsIdle = isIdle; -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** Handy macros that will help in reading those debug registers. -+*/ -+ -+#define gcmkREAD_DEBUG_REGISTER(control, block, index, data) \ -+ gcmkONERROR(\ -+ gckOS_WriteRegisterEx(Hardware->os, \ -+ Hardware->core, \ -+ GC_DEBUG_CONTROL##control##_Address, \ -+ gcmSETFIELD(0, \ -+ GC_DEBUG_CONTROL##control, \ -+ block, \ -+ index))); \ -+ gcmkONERROR(\ -+ gckOS_ReadRegisterEx(Hardware->os, \ -+ Hardware->core, \ -+ GC_DEBUG_SIGNALS_##block##_Address, \ -+ &profiler->data)) -+ -+#define gcmkREAD_DEBUG_REGISTER_N(control, block, index, data) \ -+ gcmkONERROR(\ -+ gckOS_WriteRegisterEx(Hardware->os, \ -+ Hardware->core, \ -+ GC_DEBUG_CONTROL##control##_Address, \ -+ gcmSETFIELD(0, \ -+ GC_DEBUG_CONTROL##control, \ -+ block, \ -+ index))); \ -+ gcmkONERROR(\ -+ gckOS_ReadRegisterEx(Hardware->os, \ -+ Hardware->core, \ -+ GC_DEBUG_SIGNALS_##block##_Address, \ -+ &data)) -+ -+#define gcmkRESET_DEBUG_REGISTER(control, block) \ -+ gcmkONERROR(\ -+ gckOS_WriteRegisterEx(Hardware->os, \ -+ Hardware->core, \ -+ GC_DEBUG_CONTROL##control##_Address, \ -+ gcmSETFIELD(0, \ -+ GC_DEBUG_CONTROL##control, \ -+ block, \ -+ 15))); \ -+ gcmkONERROR(\ -+ gckOS_WriteRegisterEx(Hardware->os, \ -+ Hardware->core, \ -+ GC_DEBUG_CONTROL##control##_Address, \ -+ gcmSETFIELD(0, \ -+ GC_DEBUG_CONTROL##control, \ -+ block, \ -+ 0))) -+ -+/******************************************************************************* -+** -+** gckHARDWARE_ProfileEngine2D -+** -+** Read the profile registers available in the 2D engine and sets them in the -+** profile. The function will also reset the pixelsRendered counter every time. -+** -+** INPUT: -+** -+** gckHARDWARE Hardware -+** Pointer to an gckHARDWARE object. -+** -+** OPTIONAL gcs2D_PROFILE_PTR Profile -+** Pointer to a gcs2D_Profile structure. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckHARDWARE_ProfileEngine2D( -+ IN gckHARDWARE Hardware, -+ OPTIONAL gcs2D_PROFILE_PTR Profile -+ ) -+{ -+ gceSTATUS status; -+ gcs2D_PROFILE_PTR profiler = Profile; -+ -+ gcmkHEADER_ARG("Hardware=0x%x", Hardware); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ if (Profile != gcvNULL) -+ { -+ /* Read the cycle count. */ -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00438, -+ &Profile->cycleCount)); -+ -+ /* Read pixels rendered by 2D engine. */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (11) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &profiler->pixelsRendered)); -+ -+ /* Reset counter. */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) )); -+gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) -+)); -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+#if VIVANTE_PROFILER -+gceSTATUS -+gckHARDWARE_QueryProfileRegisters( -+ IN gckHARDWARE Hardware, -+ IN gctBOOL Reset, -+ OUT gcsPROFILER_COUNTERS * Counters -+ ) -+{ -+ gceSTATUS status; -+ gcsPROFILER_COUNTERS * profiler = Counters; -+ gctUINT i, clock; -+ gctUINT32 colorKilled, colorDrawn, depthKilled, depthDrawn; -+ gctUINT32 totalRead, totalWrite; -+ -+ gcmkHEADER_ARG("Hardware=0x%x Counters=0x%x", Hardware, Counters); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ /* Read the counters. */ -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00438, -+ &profiler->gpuCyclesCounter)); -+ -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00078, -+ &profiler->gpuTotalCyclesCounter)); -+ -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x0007C, -+ &profiler->gpuIdleCyclesCounter)); -+ -+ -+ /* Read clock control register. */ -+ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00000, -+ &clock)); -+ -+ profiler->gpuTotalRead64BytesPerFrame = 0; -+ profiler->gpuTotalWrite64BytesPerFrame = 0; -+ profiler->pe_pixel_count_killed_by_color_pipe = 0; -+ profiler->pe_pixel_count_killed_by_depth_pipe = 0; -+ profiler->pe_pixel_count_drawn_by_color_pipe = 0; -+ profiler->pe_pixel_count_drawn_by_depth_pipe = 0; -+ -+ /* Walk through all avaiable pixel pipes. */ -+ for (i = 0; i < Hardware->identity.pixelPipes; ++i) -+ { -+ /* Select proper pipe. */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00000, -+ ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20))) | (((gctUINT32) ((gctUINT32) (i) & ((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20))))); -+ -+ /* BW */ -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00040, -+ &totalRead)); -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00044, -+ &totalWrite)); -+ -+ profiler->gpuTotalRead64BytesPerFrame += totalRead; -+ profiler->gpuTotalWrite64BytesPerFrame += totalWrite; -+ -+ /* PE */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &colorKilled)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &depthKilled)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &colorDrawn)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &depthDrawn)); -+ -+ profiler->pe_pixel_count_killed_by_color_pipe += colorKilled; -+ profiler->pe_pixel_count_killed_by_depth_pipe += depthKilled; -+ profiler->pe_pixel_count_drawn_by_color_pipe += colorDrawn; -+ profiler->pe_pixel_count_drawn_by_depth_pipe += depthDrawn; -+ } -+ -+ /* Reset clock control register. */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00000, -+ clock)); -+ -+ /* Reset counters. */ -+ gcmkONERROR( -+ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x0003C, 1)); -+ gcmkONERROR( -+ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x0003C, 0)); -+ gcmkONERROR( -+ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00438, 0)); -+ gcmkONERROR( -+ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00078, 0)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) )); -+gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) -+)); -+ -+ /* SH */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->ps_inst_counter)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->rendered_pixel_counter)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vs_inst_counter)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (10) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->rendered_vertice_counter)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (11) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vtx_branch_inst_counter)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (12) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vtx_texld_inst_counter)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (13) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->pxl_branch_inst_counter)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (14) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->pxl_texld_inst_counter)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) -+)); -+ -+ /* PA */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_input_vtx_counter)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (4) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_input_prim_counter)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_output_prim_counter)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (6) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_depth_clipped_counter)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_trivial_rejected_counter)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_culled_counter)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) )); -+gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) -+)); -+ -+ /* SE */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00464, &profiler->se_culled_triangle_count)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00464, &profiler->se_culled_lines_count)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) )); -+gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) -+)); -+ -+ /* RA */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_valid_pixel_count)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_total_quad_count)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_valid_quad_count_after_early_z)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_total_primitive_count)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_pipe_cache_miss_counter)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (10) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_prefetch_cache_miss_counter)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) )); -+gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) -+)); -+ -+ /* TX */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_bilinear_requests)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_trilinear_requests)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_discarded_texture_requests)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_texture_requests)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_mem_read_count)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (6) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_mem_read_in_8B_count)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_miss_count)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_hit_texel_count)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_miss_texel_count)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) -+)); -+ -+ /* MC */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_read_req_8B_from_pipeline)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_read_req_8B_from_IP)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_write_req_8B_from_pipeline)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) )); -+gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) -+)); -+ -+ /* HI */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_read_request_stalled)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_write_request_stalled)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_write_data_stalled)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) )); -+gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) -+)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+#endif -+ -+ -+#if VIVANTE_PROFILER_CONTEXT -+#define gcmkUPDATE_PROFILE_DATA(data) \ -+ profilerHistroy->data += profiler->data -+ -+gceSTATUS -+gckHARDWARE_QueryContextProfile( -+ IN gckHARDWARE Hardware, -+ IN gctBOOL Reset, -+ IN gckCONTEXT Context, -+ OUT gcsPROFILER_COUNTERS * Counters -+ ) -+{ -+ gceSTATUS status; -+ gckCOMMAND command = Hardware->kernel->command; -+ gcsPROFILER_COUNTERS * profiler = Counters; -+ -+ gcmkHEADER_ARG("Hardware=0x%x Counters=0x%x", Hardware, Counters); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ /* Acquire the context sequnence mutex. */ -+ gcmkONERROR(gckOS_AcquireMutex( -+ command->os, command->mutexContextSeq, gcvINFINITE -+ )); -+ -+ /* Read the counters. */ -+ gcmkVERIFY_OK(gckOS_MemCopy( -+ profiler, &Context->histroyProfiler, gcmSIZEOF(gcsPROFILER_COUNTERS) -+ )); -+ -+ /* Reset counters. */ -+ gcmkVERIFY_OK(gckOS_ZeroMemory( -+ &Context->histroyProfiler, gcmSIZEOF(gcsPROFILER_COUNTERS) -+ )); -+ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex( -+ command->os, command->mutexContextSeq -+ )); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+static gctUINT32 -+CalcDelta( -+ IN gctUINT32 new, -+ IN gctUINT32 old -+ ) -+{ -+ if (new >= old) -+ { -+ return new - old; -+ } -+ else -+ { -+ return (gctUINT32)((gctUINT64)new + 0x100000000ll - old); -+ } -+} -+ -+gceSTATUS -+gckHARDWARE_UpdateContextProfile( -+ IN gckHARDWARE Hardware, -+ IN gckCONTEXT Context -+ ) -+{ -+ gceSTATUS status; -+ gcsPROFILER_COUNTERS * profiler = &Context->latestProfiler; -+ gcsPROFILER_COUNTERS * profilerHistroy = &Context->histroyProfiler; -+ gctUINT i, clock; -+ gctUINT32 colorKilled = 0, colorDrawn = 0, depthKilled = 0, depthDrawn = 0; -+ gctUINT32 totalRead, totalWrite; -+ gceCHIPMODEL chipModel; -+ gctUINT32 chipRevision; -+ gctUINT32 temp; -+ gctBOOL needResetShader = gcvFALSE; -+ -+ gcmkHEADER_ARG("Hardware=0x%x Context=0x%x", Hardware, Context); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ gcmkVERIFY_OBJECT(Context, gcvOBJ_CONTEXT); -+ -+ chipModel = Hardware->identity.chipModel; -+ chipRevision = Hardware->identity.chipRevision; -+ if (chipModel == gcv2000 || (chipModel == gcv2100 && chipRevision == 0x5118)) -+ { -+ needResetShader = gcvTRUE; -+ } -+ -+ /* Read the counters. */ -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00438, -+ &profiler->gpuCyclesCounter)); -+ gcmkUPDATE_PROFILE_DATA(gpuCyclesCounter); -+ -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00078, -+ &profiler->gpuTotalCyclesCounter)); -+ gcmkUPDATE_PROFILE_DATA(gpuTotalCyclesCounter); -+ -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x0007C, -+ &profiler->gpuIdleCyclesCounter)); -+ gcmkUPDATE_PROFILE_DATA(gpuIdleCyclesCounter); -+ -+ /* Read clock control register. */ -+ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00000, -+ &clock)); -+ -+ profiler->gpuTotalRead64BytesPerFrame = 0; -+ profiler->gpuTotalWrite64BytesPerFrame = 0; -+ profiler->pe_pixel_count_killed_by_color_pipe = 0; -+ profiler->pe_pixel_count_killed_by_depth_pipe = 0; -+ profiler->pe_pixel_count_drawn_by_color_pipe = 0; -+ profiler->pe_pixel_count_drawn_by_depth_pipe = 0; -+ -+ /* Walk through all avaiable pixel pipes. */ -+ for (i = 0; i < Hardware->identity.pixelPipes; ++i) -+ { -+ /* Select proper pipe. */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00000, -+ ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20))) | (((gctUINT32) ((gctUINT32) (i) & ((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20))))); -+ -+ /* BW */ -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00040, -+ &totalRead)); -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00044, -+ &totalWrite)); -+ -+ profiler->gpuTotalRead64BytesPerFrame += totalRead; -+ profiler->gpuTotalWrite64BytesPerFrame += totalWrite; -+ gcmkUPDATE_PROFILE_DATA(gpuTotalRead64BytesPerFrame); -+ gcmkUPDATE_PROFILE_DATA(gpuTotalWrite64BytesPerFrame); -+ -+ /* PE */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &colorKilled)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &depthKilled)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &colorDrawn)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16)))));gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00454, &depthDrawn)); -+ -+ profiler->pe_pixel_count_killed_by_color_pipe += colorKilled; -+ profiler->pe_pixel_count_killed_by_depth_pipe += depthKilled; -+ profiler->pe_pixel_count_drawn_by_color_pipe += colorDrawn; -+ profiler->pe_pixel_count_drawn_by_depth_pipe += depthDrawn; -+ gcmkUPDATE_PROFILE_DATA(pe_pixel_count_killed_by_color_pipe); -+ gcmkUPDATE_PROFILE_DATA(pe_pixel_count_killed_by_depth_pipe); -+ gcmkUPDATE_PROFILE_DATA(pe_pixel_count_drawn_by_color_pipe); -+ gcmkUPDATE_PROFILE_DATA(pe_pixel_count_drawn_by_depth_pipe); -+ } -+ -+ /* Reset clock control register. */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00000, -+ clock)); -+ -+ -+ /* Reset counters. */ -+ gcmkONERROR( -+ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x0003C, 1)); -+ gcmkONERROR( -+ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x0003C, 0)); -+ gcmkONERROR( -+ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00438, 0)); -+ gcmkONERROR( -+ gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00078, 0)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) )); -+gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) -+)); -+ -+ /* SH */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->ps_inst_counter)); -+ if (needResetShader) -+ { -+ temp = profiler->ps_inst_counter; -+ profiler->ps_inst_counter = CalcDelta(temp, Context->prevPSInstCount); -+ Context->prevPSInstCount = temp; -+ } -+ gcmkUPDATE_PROFILE_DATA(ps_inst_counter); -+ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->rendered_pixel_counter)); -+ if (needResetShader) -+ { -+ temp = profiler->rendered_pixel_counter; -+ profiler->rendered_pixel_counter = CalcDelta(temp, Context->prevPSPixelCount); -+ Context->prevPSPixelCount = temp; -+ } -+ gcmkUPDATE_PROFILE_DATA(rendered_pixel_counter); -+ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vs_inst_counter)); -+ if (needResetShader) -+ { -+ temp = profiler->vs_inst_counter; -+ profiler->vs_inst_counter = CalcDelta(temp, Context->prevVSInstCount); -+ Context->prevVSInstCount = temp; -+ } -+ gcmkUPDATE_PROFILE_DATA(vs_inst_counter); -+ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (10) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->rendered_vertice_counter)); -+ if (needResetShader) -+ { -+ temp = profiler->rendered_vertice_counter; -+ profiler->rendered_vertice_counter = CalcDelta(temp, Context->prevVSVertexCount); -+ Context->prevVSVertexCount = temp; -+ } -+ gcmkUPDATE_PROFILE_DATA(rendered_vertice_counter); -+ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (11) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vtx_branch_inst_counter)); -+ if (needResetShader) -+ { -+ temp = profiler->vtx_branch_inst_counter; -+ profiler->vtx_branch_inst_counter = CalcDelta(temp, Context->prevVSBranchInstCount); -+ Context->prevVSBranchInstCount = temp; -+ } -+ gcmkUPDATE_PROFILE_DATA(vtx_branch_inst_counter); -+ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (12) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->vtx_texld_inst_counter)); -+ if (needResetShader) -+ { -+ temp = profiler->vtx_texld_inst_counter; -+ profiler->vtx_texld_inst_counter = CalcDelta(temp, Context->prevVSTexInstCount); -+ Context->prevVSTexInstCount = temp; -+ } -+ gcmkUPDATE_PROFILE_DATA(vtx_texld_inst_counter); -+ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (13) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->pxl_branch_inst_counter)); -+ if (needResetShader) -+ { -+ temp = profiler->pxl_branch_inst_counter; -+ profiler->pxl_branch_inst_counter = CalcDelta(temp, Context->prevPSBranchInstCount); -+ Context->prevPSBranchInstCount = temp; -+ } -+ gcmkUPDATE_PROFILE_DATA(pxl_branch_inst_counter); -+ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (14) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0045C, &profiler->pxl_texld_inst_counter)); -+ if (needResetShader) -+ { -+ temp = profiler->pxl_texld_inst_counter; -+ profiler->pxl_texld_inst_counter = CalcDelta(temp, Context->prevPSTexInstCount); -+ Context->prevPSTexInstCount = temp; -+ } -+ gcmkUPDATE_PROFILE_DATA(pxl_texld_inst_counter); -+ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00470, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) -+)); -+ -+ /* PA */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_input_vtx_counter)); -+ gcmkUPDATE_PROFILE_DATA(pa_input_vtx_counter); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (4) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_input_prim_counter)); -+ gcmkUPDATE_PROFILE_DATA(pa_input_prim_counter); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_output_prim_counter)); -+ gcmkUPDATE_PROFILE_DATA(pa_output_prim_counter); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (6) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_depth_clipped_counter)); -+ gcmkUPDATE_PROFILE_DATA(pa_depth_clipped_counter); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_trivial_rejected_counter)); -+ gcmkUPDATE_PROFILE_DATA(pa_trivial_rejected_counter); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00460, &profiler->pa_culled_counter)); -+ gcmkUPDATE_PROFILE_DATA(pa_culled_counter); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) )); -+gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) -+)); -+ -+ /* SE */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00464, &profiler->se_culled_triangle_count)); -+ gcmkUPDATE_PROFILE_DATA(se_culled_triangle_count); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00464, &profiler->se_culled_lines_count)); -+ gcmkUPDATE_PROFILE_DATA(se_culled_lines_count); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) )); -+gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) -+)); -+ -+ /* RA */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_valid_pixel_count)); -+ gcmkUPDATE_PROFILE_DATA(ra_valid_pixel_count); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_total_quad_count)); -+ gcmkUPDATE_PROFILE_DATA(ra_total_quad_count); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_valid_quad_count_after_early_z)); -+ gcmkUPDATE_PROFILE_DATA(ra_valid_quad_count_after_early_z); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_total_primitive_count)); -+ gcmkUPDATE_PROFILE_DATA(ra_total_primitive_count); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_pipe_cache_miss_counter)); -+ gcmkUPDATE_PROFILE_DATA(ra_pipe_cache_miss_counter); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (10) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00448, &profiler->ra_prefetch_cache_miss_counter)); -+ gcmkUPDATE_PROFILE_DATA(ra_prefetch_cache_miss_counter); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) )); -+gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 23:16) - (0 ? 23:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:16) - (0 ? 23:16) + 1))))))) << (0 ? 23:16))) -+)); -+ -+ /* TX */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_bilinear_requests)); -+ gcmkUPDATE_PROFILE_DATA(tx_total_bilinear_requests); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_trilinear_requests)); -+ gcmkUPDATE_PROFILE_DATA(tx_total_trilinear_requests); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_discarded_texture_requests)); -+ gcmkUPDATE_PROFILE_DATA(tx_total_discarded_texture_requests); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_total_texture_requests)); -+ gcmkUPDATE_PROFILE_DATA(tx_total_texture_requests); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (5) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_mem_read_count)); -+ gcmkUPDATE_PROFILE_DATA(tx_mem_read_count); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (6) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_mem_read_in_8B_count)); -+ gcmkUPDATE_PROFILE_DATA(tx_mem_read_in_8B_count); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (7) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_miss_count)); -+ gcmkUPDATE_PROFILE_DATA(tx_cache_miss_count); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (8) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_hit_texel_count)); -+ gcmkUPDATE_PROFILE_DATA(tx_cache_hit_texel_count); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (9) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0044C, &profiler->tx_cache_miss_texel_count)); -+ gcmkUPDATE_PROFILE_DATA(tx_cache_miss_texel_count); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) )); -+gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00474, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1))))))) << (0 ? 31:24))) -+)); -+ -+ /* MC */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_read_req_8B_from_pipeline)); -+ gcmkUPDATE_PROFILE_DATA(mc_total_read_req_8B_from_pipeline); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_read_req_8B_from_IP)); -+ gcmkUPDATE_PROFILE_DATA(mc_total_read_req_8B_from_IP); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (3) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x00468, &profiler->mc_total_write_req_8B_from_pipeline)); -+ gcmkUPDATE_PROFILE_DATA(mc_total_write_req_8B_from_pipeline); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) )); -+gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 7:0) - (0 ? 7:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 7:0) - (0 ? 7:0) + 1))))))) << (0 ? 7:0))) -+)); -+ -+ /* HI */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_read_request_stalled)); -+ gcmkUPDATE_PROFILE_DATA(hi_axi_cycles_read_request_stalled); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_write_request_stalled)); -+ gcmkUPDATE_PROFILE_DATA(hi_axi_cycles_write_request_stalled); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (2) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) )); -+gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, Hardware->core, 0x0046C, &profiler->hi_axi_cycles_write_data_stalled)); -+ gcmkUPDATE_PROFILE_DATA(hi_axi_cycles_write_data_stalled); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (15) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) )); -+gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, 0x00478, ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) -+)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+#endif -+ -+ -+#if VIVANTE_PROFILER_NEW -+gceSTATUS -+gckHARDWARE_InitProfiler( -+ IN gckHARDWARE Hardware -+ ) -+{ -+ gceSTATUS status; -+ gctUINT32 control; -+ -+ gcmkHEADER_ARG("Hardware=0x%x", Hardware); -+ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00000, -+ &control)); -+ /* Enable debug register. */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00000, -+ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1))))))) << (0 ? 11:11))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1))))))) << (0 ? 11:11))))); -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+#endif -+ -+static gceSTATUS -+_ResetGPU( -+ IN gckHARDWARE Hardware, -+ IN gckOS Os, -+ IN gceCORE Core -+ ) -+{ -+ gctUINT32 control, idle; -+ gceSTATUS status; -+ -+ for (;;) -+ { -+ /* Disable clock gating. */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Os, -+ Core, -+ Hardware->powerBaseAddress + -+ 0x00104, -+ 0x00000000)); -+ -+ control = ((((gctUINT32) (0x01590880)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1))))))) << (0 ? 17:17))); -+ -+ /* Disable pulse-eater. */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Os, -+ Core, -+ 0x0010C, -+ control)); -+ -+ gcmkONERROR(gckOS_WriteRegisterEx(Os, -+ Core, -+ 0x0010C, -+ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))))); -+ -+ gcmkONERROR(gckOS_WriteRegisterEx(Os, -+ Core, -+ 0x0010C, -+ control)); -+ -+ gcmkONERROR(gckOS_WriteRegisterEx(Os, -+ Core, -+ 0x00000, -+ ((((gctUINT32) (0x00000900)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))))); -+ -+ gcmkONERROR(gckOS_WriteRegisterEx(Os, -+ Core, -+ 0x00000, -+ 0x00000900)); -+ -+ /* Wait for clock being stable. */ -+ gcmkONERROR(gckOS_Delay(Os, 1)); -+ -+ /* Isolate the GPU. */ -+ control = ((((gctUINT32) (0x00000900)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))); -+ -+ gcmkONERROR(gckOS_WriteRegisterEx(Os, -+ Core, -+ 0x00000, -+ control)); -+ -+ /* Set soft reset. */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Os, -+ Core, -+ 0x00000, -+ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))))); -+ -+ /* Wait for reset. */ -+ gcmkONERROR(gckOS_Delay(Os, 1)); -+ -+ /* Reset soft reset bit. */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Os, -+ Core, -+ 0x00000, -+ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))))); -+ -+ /* Reset GPU isolation. */ -+ control = ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))); -+ -+ gcmkONERROR(gckOS_WriteRegisterEx(Os, -+ Core, -+ 0x00000, -+ control)); -+ -+ /* Read idle register. */ -+ gcmkONERROR(gckOS_ReadRegisterEx(Os, -+ Core, -+ 0x00004, -+ &idle)); -+ -+ if ((((((gctUINT32) (idle)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ) == 0) -+ { -+ continue; -+ } -+ -+ /* Read reset register. */ -+ gcmkONERROR(gckOS_ReadRegisterEx(Os, -+ Core, -+ 0x00000, -+ &control)); -+ -+ if (((((((gctUINT32) (control)) >> (0 ? 16:16)) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) ) == 0) -+ || ((((((gctUINT32) (control)) >> (0 ? 17:17)) & ((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1)))))) ) == 0) -+ ) -+ { -+ continue; -+ } -+ -+ /* GPU is idle. */ -+ break; -+ } -+ -+ /* Success. */ -+ return gcvSTATUS_OK; -+ -+OnError: -+ -+ /* Return the error. */ -+ return status; -+} -+ -+gceSTATUS -+gckHARDWARE_Reset( -+ IN gckHARDWARE Hardware -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Hardware=0x%x", Hardware); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ gcmkVERIFY_OBJECT(Hardware->kernel, gcvOBJ_KERNEL); -+ -+ /* Hardware reset. */ -+ status = gckOS_ResetGPU(Hardware->os, Hardware->core); -+ -+ if (gcmIS_ERROR(status)) -+ { -+ if (Hardware->identity.chipRevision < 0x4600) -+ { -+ /* Not supported - we need the isolation bit. */ -+ gcmkONERROR(gcvSTATUS_NOT_SUPPORTED); -+ } -+ -+ /* Soft reset. */ -+ gcmkONERROR(_ResetGPU(Hardware, Hardware->os, Hardware->core)); -+ } -+ -+ /* Initialize hardware. */ -+ gcmkONERROR(gckHARDWARE_InitializeHardware(Hardware)); -+ -+ /* Jump to address into which GPU should run if it doesn't stuck. */ -+ gcmkONERROR(gckHARDWARE_Execute(Hardware, Hardware->kernel->restoreAddress, 16)); -+ -+ gcmkPRINT("[galcore]: recovery done"); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ gcmkPRINT("[galcore]: Hardware not reset successfully, give up"); -+ -+ /* Return the error. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckHARDWARE_GetBaseAddress( -+ IN gckHARDWARE Hardware, -+ OUT gctUINT32_PTR BaseAddress -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Hardware=0x%x", Hardware); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ gcmkVERIFY_ARGUMENT(BaseAddress != gcvNULL); -+ -+ /* Test if we have a new Memory Controller. */ -+ if (((((gctUINT32) (Hardware->identity.chipMinorFeatures)) >> (0 ? 22:22) & ((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1)))))))) -+ { -+ /* No base address required. */ -+ *BaseAddress = 0; -+ } -+ else -+ { -+ /* Get the base address from the OS. */ -+ gcmkONERROR(gckOS_GetBaseAddress(Hardware->os, BaseAddress)); -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*BaseAddress=0x%08x", *BaseAddress); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckHARDWARE_NeedBaseAddress( -+ IN gckHARDWARE Hardware, -+ IN gctUINT32 State, -+ OUT gctBOOL_PTR NeedBase -+ ) -+{ -+ gctBOOL need = gcvFALSE; -+ -+ gcmkHEADER_ARG("Hardware=0x%x State=0x%08x", Hardware, State); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ gcmkVERIFY_ARGUMENT(NeedBase != gcvNULL); -+ -+ /* Make sure this is a load state. */ -+ if (((((gctUINT32) (State)) >> (0 ? 31:27) & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1)))))) == (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1)))))))) -+ { -+#if gcdENABLE_3D -+ /* Get the state address. */ -+ switch ((((((gctUINT32) (State)) >> (0 ? 15:0)) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1)))))) )) -+ { -+ case 0x0596: -+ case 0x0597: -+ case 0x0599: -+ case 0x059A: -+ case 0x05A9: -+ /* These states need a TRUE physical address. */ -+ need = gcvTRUE; -+ break; -+ } -+#else -+ /* 2D addresses don't need a base address. */ -+#endif -+ } -+ -+ /* Return the flag. */ -+ *NeedBase = need; -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*NeedBase=%d", *NeedBase); -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckHARDWARE_SetIsrManager( -+ IN gckHARDWARE Hardware, -+ IN gctISRMANAGERFUNC StartIsr, -+ IN gctISRMANAGERFUNC StopIsr, -+ IN gctPOINTER Context -+ ) -+{ -+ gceSTATUS status = gcvSTATUS_OK; -+ -+ gcmkHEADER_ARG("Hardware=0x%x, StartIsr=0x%x, StopIsr=0x%x, Context=0x%x", -+ Hardware, StartIsr, StopIsr, Context); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ if (StartIsr == gcvNULL || -+ StopIsr == gcvNULL || -+ Context == gcvNULL) -+ { -+ status = gcvSTATUS_INVALID_ARGUMENT; -+ -+ gcmkFOOTER(); -+ return status; -+ } -+ -+ Hardware->startIsr = StartIsr; -+ Hardware->stopIsr = StopIsr; -+ Hardware->isrContext = Context; -+ -+ /* Success. */ -+ gcmkFOOTER(); -+ -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckHARDWARE_Compose -+** -+** Start a composition. -+** -+** INPUT: -+** -+** gckHARDWARE Hardware -+** Pointer to the gckHARDWARE object. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckHARDWARE_Compose( -+ IN gckHARDWARE Hardware, -+ IN gctUINT32 ProcessID, -+ IN gctPHYS_ADDR Physical, -+ IN gctPOINTER Logical, -+ IN gctSIZE_T Offset, -+ IN gctSIZE_T Size, -+ IN gctUINT8 EventID -+ ) -+{ -+#if gcdENABLE_3D -+ gceSTATUS status; -+ gctUINT32_PTR triggerState; -+ -+ gcmkHEADER_ARG("Hardware=0x%x Physical=0x%x Logical=0x%x" -+ " Offset=%d Size=%d EventID=%d", -+ Hardware, Physical, Logical, Offset, Size, EventID); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ gcmkVERIFY_ARGUMENT(((Size + 8) & 63) == 0); -+ gcmkVERIFY_ARGUMENT(Logical != gcvNULL); -+ -+ /* Program the trigger state. */ -+ triggerState = (gctUINT32_PTR) ((gctUINT8_PTR) Logical + Offset + Size); -+ triggerState[0] = 0x0C03; -+ triggerState[1] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:4) - (0 ? 5:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:4) - (0 ? 5:4) + 1))))))) << (0 ? 5:4))) | (((gctUINT32) (0x3 & ((gctUINT32) ((((1 ? 5:4) - (0 ? 5:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:4) - (0 ? 5:4) + 1))))))) << (0 ? 5:4))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1))))))) << (0 ? 8:8))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1))))))) << (0 ? 8:8))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:16) - (0 ? 20:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:16) - (0 ? 20:16) + 1))))))) << (0 ? 20:16))) | (((gctUINT32) ((gctUINT32) (EventID) & ((gctUINT32) ((((1 ? 20:16) - (0 ? 20:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:16) - (0 ? 20:16) + 1))))))) << (0 ? 20:16))) -+ ; -+ -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ /* Flush the cache for the wait/link. */ -+ gcmkONERROR(gckOS_CacheClean( -+ Hardware->os, ProcessID, gcvNULL, -+ (gctUINT32)Physical, Logical, Offset + Size -+ )); -+#endif -+ -+ /* Start composition. */ -+ gcmkONERROR(gckOS_WriteRegisterEx( -+ Hardware->os, Hardware->core, 0x00554, -+ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) (0x3 & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) -+ )); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+#else -+ /* Return the status. */ -+ return gcvSTATUS_NOT_SUPPORTED; -+#endif -+} -+ -+/******************************************************************************* -+** -+** gckHARDWARE_IsFeatureAvailable -+** -+** Verifies whether the specified feature is available in hardware. -+** -+** INPUT: -+** -+** gckHARDWARE Hardware -+** Pointer to an gckHARDWARE object. -+** -+** gceFEATURE Feature -+** Feature to be verified. -+*/ -+gceSTATUS -+gckHARDWARE_IsFeatureAvailable( -+ IN gckHARDWARE Hardware, -+ IN gceFEATURE Feature -+ ) -+{ -+ gctBOOL available; -+ -+ gcmkHEADER_ARG("Hardware=0x%x Feature=%d", Hardware, Feature); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ /* Only features needed by common kernel logic added here. */ -+ switch (Feature) -+ { -+ case gcvFEATURE_END_EVENT: -+ /*available = gcmVERIFYFIELDVALUE(Hardware->identity.chipMinorFeatures2, -+ GC_MINOR_FEATURES2, END_EVENT, AVAILABLE -+ );*/ -+ available = gcvFALSE; -+ break; -+ -+ case gcvFEATURE_MC20: -+ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures)) >> (0 ? 22:22) & ((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1))))))); -+ break; -+ -+ case gcvFEATURE_EARLY_Z: -+ available = ((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 16:16) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) == (0x0 & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))); -+ break; -+ -+ case gcvFEATURE_HZ: -+ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures)) >> (0 ? 27:27) & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 27:27) - (0 ? 27:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:27) - (0 ? 27:27) + 1))))))); -+ break; -+ -+ case gcvFEATURE_NEW_HZ: -+ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures3)) >> (0 ? 26:26) & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 26:26) - (0 ? 26:26) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:26) - (0 ? 26:26) + 1))))))); -+ break; -+ -+ case gcvFEATURE_FAST_MSAA: -+ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures3)) >> (0 ? 8:8) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1))))))); -+ break; -+ -+ case gcvFEATURE_SMALL_MSAA: -+ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures4)) >> (0 ? 18:18) & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1))))))); -+ break; -+ -+ case gcvFEATURE_DYNAMIC_FREQUENCY_SCALING: -+ /* This feature doesn't apply for 2D cores. */ -+ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures2)) >> (0 ? 14:14) & ((gctUINT32) ((((1 ? 14:14) - (0 ? 14:14) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 14:14) - (0 ? 14:14) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 14:14) - (0 ? 14:14) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 14:14) - (0 ? 14:14) + 1))))))) -+ && ((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 2:2) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))); -+ -+ if (Hardware->identity.chipModel == gcv1000 && -+ (Hardware->identity.chipRevision == 0x5039 || -+ Hardware->identity.chipRevision == 0x5040)) -+ { -+ available = gcvFALSE; -+ } -+ break; -+ -+ case gcvFEATURE_ACE: -+ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures3)) >> (0 ? 18:18) & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1))))))); -+ break; -+ -+ case gcvFEATURE_HALTI2: -+ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures4)) >> (0 ? 16:16) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))); -+ break; -+ -+ case gcvFEATURE_PIPE_2D: -+ available = ((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 9:9) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))); -+ break; -+ -+ case gcvFEATURE_PIPE_3D: -+#if gcdENABLE_3D -+ available = ((((gctUINT32) (Hardware->identity.chipFeatures)) >> (0 ? 2:2) & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))); -+#else -+ available = gcvFALSE; -+#endif -+ break; -+ -+ case gcvFEATURE_FC_FLUSH_STALL: -+ available = ((((gctUINT32) (Hardware->identity.chipMinorFeatures1)) >> (0 ? 31:31) & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 31:31) - (0 ? 31:31) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:31) - (0 ? 31:31) + 1))))))); -+ break; -+ -+ default: -+ gcmkFATAL("Invalid feature has been requested."); -+ available = gcvFALSE; -+ } -+ -+ /* Return result. */ -+ gcmkFOOTER_ARG("%d", available ? gcvSTATUS_TRUE : gcvSTATUS_FALSE); -+ return available ? gcvSTATUS_TRUE : gcvSTATUS_FALSE; -+} -+ -+/******************************************************************************* -+** -+** gckHARDWARE_DumpMMUException -+** -+** Dump the MMU debug info on an MMU exception. -+** -+** INPUT: -+** -+** gckHARDWARE Harwdare -+** Pointer to an gckHARDWARE object. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckHARDWARE_DumpMMUException( -+ IN gckHARDWARE Hardware -+ ) -+{ -+ gctUINT32 mmu = 0; -+ gctUINT32 mmuStatus = 0; -+ gctUINT32 address = 0; -+ gctUINT32 i = 0; -+ gctUINT32 mtlb = 0; -+ gctUINT32 stlb = 0; -+ gctUINT32 offset = 0; -+#if gcdPROCESS_ADDRESS_SPACE -+ gcsDATABASE_PTR database; -+#endif -+ -+ gcmkHEADER_ARG("Hardware=0x%x", Hardware); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ gcmkPRINT("GPU[%d](ChipModel=0x%x ChipRevision=0x%x):\n", -+ Hardware->core, -+ Hardware->identity.chipModel, -+ Hardware->identity.chipRevision); -+ -+ gcmkPRINT("**************************\n"); -+ gcmkPRINT("*** MMU ERROR DUMP ***\n"); -+ gcmkPRINT("**************************\n"); -+ -+ gcmkVERIFY_OK( -+ gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00188, -+ &mmuStatus)); -+ -+ gcmkPRINT(" MMU status = 0x%08X\n", mmuStatus); -+ -+ for (i = 0; i < 4; i += 1) -+ { -+ mmu = mmuStatus & 0xF; -+ mmuStatus >>= 4; -+ -+ if (mmu == 0) -+ { -+ continue; -+ } -+ -+ switch (mmu) -+ { -+ case 1: -+ gcmkPRINT(" MMU%d: slave not present\n", i); -+ break; -+ -+ case 2: -+ gcmkPRINT(" MMU%d: page not present\n", i); -+ break; -+ -+ case 3: -+ gcmkPRINT(" MMU%d: write violation\n", i); -+ break; -+ -+ default: -+ gcmkPRINT(" MMU%d: unknown state\n", i); -+ } -+ -+ gcmkVERIFY_OK( -+ gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00190 + i * 4, -+ &address)); -+ -+ mtlb = (address & gcdMMU_MTLB_MASK) >> gcdMMU_MTLB_SHIFT; -+ stlb = (address & gcdMMU_STLB_4K_MASK) >> gcdMMU_STLB_4K_SHIFT; -+ offset = address & gcdMMU_OFFSET_4K_MASK; -+ -+ gcmkPRINT(" MMU%d: exception address = 0x%08X\n", i, address); -+ -+ gcmkPRINT(" MTLB entry = %d\n", mtlb); -+ -+ gcmkPRINT(" STLB entry = %d\n", stlb); -+ -+ gcmkPRINT(" Offset = 0x%08X (%d)\n", offset, offset); -+ -+ gckMMU_DumpPageTableEntry(Hardware->kernel->mmu, address); -+ -+#if gcdPROCESS_ADDRESS_SPACE -+ for (i = 0; i < gcmCOUNTOF(Hardware->kernel->db->db); ++i) -+ { -+ for (database = Hardware->kernel->db->db[i]; -+ database != gcvNULL; -+ database = database->next) -+ { -+ gcmkPRINT(" database [%d] :", database->processID); -+ gckMMU_DumpPageTableEntry(database->mmu, address); -+ } -+ } -+#endif -+ } -+ -+ gckHARDWARE_DumpGPUState(Hardware); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckHARDWARE_DumpGPUState -+** -+** Dump the GPU debug registers. -+** -+** INPUT: -+** -+** gckHARDWARE Harwdare -+** Pointer to an gckHARDWARE object. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckHARDWARE_DumpGPUState( -+ IN gckHARDWARE Hardware -+ ) -+{ -+ static gctCONST_STRING _cmdState[] = -+ { -+ "PAR_IDLE_ST", "PAR_DEC_ST", "PAR_ADR0_ST", "PAR_LOAD0_ST", -+ "PAR_ADR1_ST", "PAR_LOAD1_ST", "PAR_3DADR_ST", "PAR_3DCMD_ST", -+ "PAR_3DCNTL_ST", "PAR_3DIDXCNTL_ST", "PAR_INITREQDMA_ST", -+ "PAR_DRAWIDX_ST", "PAR_DRAW_ST", "PAR_2DRECT0_ST", "PAR_2DRECT1_ST", -+ "PAR_2DDATA0_ST", "PAR_2DDATA1_ST", "PAR_WAITFIFO_ST", "PAR_WAIT_ST", -+ "PAR_LINK_ST", "PAR_END_ST", "PAR_STALL_ST" -+ }; -+ -+ static gctCONST_STRING _cmdDmaState[] = -+ { -+ "CMD_IDLE_ST", "CMD_START_ST", "CMD_REQ_ST", "CMD_END_ST" -+ }; -+ -+ static gctCONST_STRING _cmdFetState[] = -+ { -+ "FET_IDLE_ST", "FET_RAMVALID_ST", "FET_VALID_ST" -+ }; -+ -+ static gctCONST_STRING _reqDmaState[] = -+ { -+ "REQ_IDLE_ST", "REQ_WAITIDX_ST", "REQ_CAL_ST" -+ }; -+ -+ static gctCONST_STRING _calState[] = -+ { -+ "CAL_IDLE_ST", "CAL_LDADR_ST", "CAL_IDXCALC_ST" -+ }; -+ -+ static gctCONST_STRING _veReqState[] = -+ { -+ "VER_IDLE_ST", "VER_CKCACHE_ST", "VER_MISS_ST" -+ }; -+ -+ static gcsiDEBUG_REGISTERS _dbgRegs[] = -+ { -+ { "RA", 0x474, 16, 0x448, 16, 0x12344321 }, -+ { "TX", 0x474, 24, 0x44C, 16, 0x12211221 }, -+ { "FE", 0x470, 0, 0x450, 16, 0xBABEF00D }, -+ { "PE", 0x470, 16, 0x454, 16, 0xBABEF00D }, -+ { "DE", 0x470, 8, 0x458, 16, 0xBABEF00D }, -+ { "SH", 0x470, 24, 0x45C, 16, 0xDEADBEEF }, -+ { "PA", 0x474, 0, 0x460, 16, 0x0000AAAA }, -+ { "SE", 0x474, 8, 0x464, 16, 0x5E5E5E5E }, -+ { "MC", 0x478, 0, 0x468, 16, 0x12345678 }, -+ { "HI", 0x478, 8, 0x46C, 16, 0xAAAAAAAA } -+ }; -+ -+ static gctUINT32 _otherRegs[] = -+ { -+ 0x040, 0x044, 0x04C, 0x050, 0x054, 0x058, 0x05C, 0x060, -+ 0x43c, 0x440, 0x444, 0x414, -+ }; -+ -+ gceSTATUS status; -+ gckKERNEL kernel = gcvNULL; -+ gctUINT32 idle = 0, axi = 0; -+ gctUINT32 dmaAddress1 = 0, dmaAddress2 = 0; -+ gctUINT32 dmaState1 = 0, dmaState2 = 0; -+ gctUINT32 dmaLow = 0, dmaHigh = 0; -+ gctUINT32 cmdState = 0, cmdDmaState = 0, cmdFetState = 0; -+ gctUINT32 dmaReqState = 0, calState = 0, veReqState = 0; -+ gctUINT i; -+ gctUINT pipe = 0, pixelPipes = 0; -+ gctUINT32 control = 0, oldControl = 0; -+ gckOS os = Hardware->os; -+ gceCORE core = Hardware->core; -+ -+ gcmkHEADER_ARG("Hardware=0x%X", Hardware); -+ -+ kernel = Hardware->kernel; -+ -+ gcmkPRINT_N(12, "GPU[%d](ChipModel=0x%x ChipRevision=0x%x):\n", -+ core, -+ Hardware->identity.chipModel, -+ Hardware->identity.chipRevision); -+ -+ pixelPipes = Hardware->identity.pixelPipes -+ ? Hardware->identity.pixelPipes -+ : 1; -+ -+ /* Reset register values. */ -+ idle = axi = -+ dmaState1 = dmaState2 = -+ dmaAddress1 = dmaAddress2 = -+ dmaLow = dmaHigh = 0; -+ -+ /* Verify whether DMA is running. */ -+ gcmkONERROR(_VerifyDMA( -+ os, core, &dmaAddress1, &dmaAddress2, &dmaState1, &dmaState2 -+ )); -+ -+ cmdState = dmaState2 & 0x1F; -+ cmdDmaState = (dmaState2 >> 8) & 0x03; -+ cmdFetState = (dmaState2 >> 10) & 0x03; -+ dmaReqState = (dmaState2 >> 12) & 0x03; -+ calState = (dmaState2 >> 14) & 0x03; -+ veReqState = (dmaState2 >> 16) & 0x03; -+ -+ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x004, &idle)); -+ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x00C, &axi)); -+ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x668, &dmaLow)); -+ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x66C, &dmaHigh)); -+ -+ gcmkPRINT_N(0, "**************************\n"); -+ gcmkPRINT_N(0, "*** GPU STATE DUMP ***\n"); -+ gcmkPRINT_N(0, "**************************\n"); -+ -+ gcmkPRINT_N(4, " axi = 0x%08X\n", axi); -+ -+ gcmkPRINT_N(4, " idle = 0x%08X\n", idle); -+ if ((idle & 0x00000001) == 0) gcmkPRINT_N(0, " FE not idle\n"); -+ if ((idle & 0x00000002) == 0) gcmkPRINT_N(0, " DE not idle\n"); -+ if ((idle & 0x00000004) == 0) gcmkPRINT_N(0, " PE not idle\n"); -+ if ((idle & 0x00000008) == 0) gcmkPRINT_N(0, " SH not idle\n"); -+ if ((idle & 0x00000010) == 0) gcmkPRINT_N(0, " PA not idle\n"); -+ if ((idle & 0x00000020) == 0) gcmkPRINT_N(0, " SE not idle\n"); -+ if ((idle & 0x00000040) == 0) gcmkPRINT_N(0, " RA not idle\n"); -+ if ((idle & 0x00000080) == 0) gcmkPRINT_N(0, " TX not idle\n"); -+ if ((idle & 0x00000100) == 0) gcmkPRINT_N(0, " VG not idle\n"); -+ if ((idle & 0x00000200) == 0) gcmkPRINT_N(0, " IM not idle\n"); -+ if ((idle & 0x00000400) == 0) gcmkPRINT_N(0, " FP not idle\n"); -+ if ((idle & 0x00000800) == 0) gcmkPRINT_N(0, " TS not idle\n"); -+ if ((idle & 0x80000000) != 0) gcmkPRINT_N(0, " AXI low power mode\n"); -+ -+ if ( -+ (dmaAddress1 == dmaAddress2) -+ && (dmaState1 == dmaState2) -+ ) -+ { -+ gcmkPRINT_N(0, " DMA appears to be stuck at this address:\n"); -+ gcmkPRINT_N(4, " 0x%08X\n", dmaAddress1); -+ } -+ else -+ { -+ if (dmaAddress1 == dmaAddress2) -+ { -+ gcmkPRINT_N(0, " DMA address is constant, but state is changing:\n"); -+ gcmkPRINT_N(4, " 0x%08X\n", dmaState1); -+ gcmkPRINT_N(4, " 0x%08X\n", dmaState2); -+ } -+ else -+ { -+ gcmkPRINT_N(0, " DMA is running; known addresses are:\n"); -+ gcmkPRINT_N(4, " 0x%08X\n", dmaAddress1); -+ gcmkPRINT_N(4, " 0x%08X\n", dmaAddress2); -+ } -+ } -+ -+ gcmkPRINT_N(4, " dmaLow = 0x%08X\n", dmaLow); -+ gcmkPRINT_N(4, " dmaHigh = 0x%08X\n", dmaHigh); -+ gcmkPRINT_N(4, " dmaState = 0x%08X\n", dmaState2); -+ gcmkPRINT_N(8, " command state = %d (%s)\n", cmdState, _cmdState [cmdState]); -+ gcmkPRINT_N(8, " command DMA state = %d (%s)\n", cmdDmaState, _cmdDmaState[cmdDmaState]); -+ gcmkPRINT_N(8, " command fetch state = %d (%s)\n", cmdFetState, _cmdFetState[cmdFetState]); -+ gcmkPRINT_N(8, " DMA request state = %d (%s)\n", dmaReqState, _reqDmaState[dmaReqState]); -+ gcmkPRINT_N(8, " cal state = %d (%s)\n", calState, _calState [calState]); -+ gcmkPRINT_N(8, " VE request state = %d (%s)\n", veReqState, _veReqState [veReqState]); -+ -+ /* Record control. */ -+ gckOS_ReadRegisterEx(os, core, 0x0, &oldControl); -+ -+ for (pipe = 0; pipe < pixelPipes; pipe++) -+ { -+ gcmkPRINT_N(4, " Debug registers of pipe[%d]:\n", pipe); -+ -+ /* Switch pipe. */ -+ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x0, &control)); -+ control &= ~(0xF << 20); -+ control |= (pipe << 20); -+ gcmkONERROR(gckOS_WriteRegisterEx(os, core, 0x0, control)); -+ -+ for (i = 0; i < gcmCOUNTOF(_dbgRegs); i += 1) -+ { -+ gcmkONERROR(_DumpDebugRegisters(os, core, &_dbgRegs[i])); -+ } -+ -+ gcmkPRINT_N(0, " Other Registers:\n"); -+ for (i = 0; i < gcmCOUNTOF(_otherRegs); i += 1) -+ { -+ gctUINT32 read; -+ gcmkONERROR(gckOS_ReadRegisterEx(os, core, _otherRegs[i], &read)); -+ gcmkPRINT_N(12, " [0x%04X] 0x%08X\n", _otherRegs[i], read); -+ } -+ } -+ -+ if (kernel->hardware->identity.chipFeatures & (1 << 4)) -+ { -+ gctUINT32 read0, read1, write; -+ -+ read0 = read1 = write = 0; -+ -+ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x43C, &read0)); -+ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x440, &read1)); -+ gcmkONERROR(gckOS_ReadRegisterEx(os, core, 0x444, &write)); -+ -+ gcmkPRINT_N(4, " read0 = 0x%08X\n", read0); -+ gcmkPRINT_N(4, " read1 = 0x%08X\n", read1); -+ gcmkPRINT_N(4, " write = 0x%08X\n", write); -+ } -+ -+ /* Restore control. */ -+ gcmkONERROR(gckOS_WriteRegisterEx(os, core, 0x0, oldControl)); -+ -+ /* dump stack. */ -+ gckOS_DumpCallStack(os); -+ -+OnError: -+ -+ /* Return the error. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+static gceSTATUS -+gckHARDWARE_ReadPerformanceRegister( -+ IN gckHARDWARE Hardware, -+ IN gctUINT PerformanceAddress, -+ IN gctUINT IndexAddress, -+ IN gctUINT IndexShift, -+ IN gctUINT Index, -+ OUT gctUINT32_PTR Value -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Hardware=0x%x PerformanceAddress=0x%x IndexAddress=0x%x " -+ "IndexShift=%u Index=%u", -+ Hardware, PerformanceAddress, IndexAddress, IndexShift, -+ Index); -+ -+ /* Write the index. */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ IndexAddress, -+ Index << IndexShift)); -+ -+ /* Read the register. */ -+ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ PerformanceAddress, -+ Value)); -+ -+ /* Test for reset. */ -+ if (Index == 15) -+ { -+ /* Index another register to get out of reset. */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, Hardware->core, IndexAddress, 0)); -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Value=0x%x", *Value); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckHARDWARE_GetFrameInfo( -+ IN gckHARDWARE Hardware, -+ OUT gcsHAL_FRAME_INFO * FrameInfo -+ ) -+{ -+ gceSTATUS status; -+ gctUINT i, clock; -+ gcsHAL_FRAME_INFO info; -+#if gcdFRAME_DB_RESET -+ gctUINT reset; -+#endif -+ -+ gcmkHEADER_ARG("Hardware=0x%x", Hardware); -+ -+ /* Get profile tick. */ -+ gcmkONERROR(gckOS_GetProfileTick(&info.ticks)); -+ -+ /* Read SH counters and reset them. */ -+ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister( -+ Hardware, -+ 0x0045C, -+ 0x00470, -+ 24, -+ 4, -+ &info.shaderCycles)); -+ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister( -+ Hardware, -+ 0x0045C, -+ 0x00470, -+ 24, -+ 9, -+ &info.vsInstructionCount)); -+ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister( -+ Hardware, -+ 0x0045C, -+ 0x00470, -+ 24, -+ 12, -+ &info.vsTextureCount)); -+ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister( -+ Hardware, -+ 0x0045C, -+ 0x00470, -+ 24, -+ 7, -+ &info.psInstructionCount)); -+ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister( -+ Hardware, -+ 0x0045C, -+ 0x00470, -+ 24, -+ 14, -+ &info.psTextureCount)); -+#if gcdFRAME_DB_RESET -+ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister( -+ Hardware, -+ 0x0045C, -+ 0x00470, -+ 24, -+ 15, -+ &reset)); -+#endif -+ -+ /* Read PA counters and reset them. */ -+ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister( -+ Hardware, -+ 0x00460, -+ 0x00474, -+ 0, -+ 3, -+ &info.vertexCount)); -+ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister( -+ Hardware, -+ 0x00460, -+ 0x00474, -+ 0, -+ 4, -+ &info.primitiveCount)); -+ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister( -+ Hardware, -+ 0x00460, -+ 0x00474, -+ 0, -+ 7, -+ &info.rejectedPrimitives)); -+ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister( -+ Hardware, -+ 0x00460, -+ 0x00474, -+ 0, -+ 8, -+ &info.culledPrimitives)); -+ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister( -+ Hardware, -+ 0x00460, -+ 0x00474, -+ 0, -+ 6, -+ &info.clippedPrimitives)); -+ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister( -+ Hardware, -+ 0x00460, -+ 0x00474, -+ 0, -+ 5, -+ &info.outPrimitives)); -+#if gcdFRAME_DB_RESET -+ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister( -+ Hardware, -+ 0x00460, -+ 0x00474, -+ 0, -+ 15, -+ &reset)); -+#endif -+ -+ /* Read RA counters and reset them. */ -+ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister( -+ Hardware, -+ 0x00448, -+ 0x00474, -+ 16, -+ 3, -+ &info.inPrimitives)); -+ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister( -+ Hardware, -+ 0x00448, -+ 0x00474, -+ 16, -+ 11, -+ &info.culledQuadCount)); -+ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister( -+ Hardware, -+ 0x00448, -+ 0x00474, -+ 16, -+ 1, -+ &info.totalQuadCount)); -+ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister( -+ Hardware, -+ 0x00448, -+ 0x00474, -+ 16, -+ 2, -+ &info.quadCount)); -+ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister( -+ Hardware, -+ 0x00448, -+ 0x00474, -+ 16, -+ 0, -+ &info.totalPixelCount)); -+#if gcdFRAME_DB_RESET -+ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister( -+ Hardware, -+ 0x00448, -+ 0x00474, -+ 16, -+ 15, -+ &reset)); -+#endif -+ -+ /* Read TX counters and reset them. */ -+ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister( -+ Hardware, -+ 0x0044C, -+ 0x00474, -+ 24, -+ 0, -+ &info.bilinearRequests)); -+ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister( -+ Hardware, -+ 0x0044C, -+ 0x00474, -+ 24, -+ 1, -+ &info.trilinearRequests)); -+ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister( -+ Hardware, -+ 0x0044C, -+ 0x00474, -+ 24, -+ 8, -+ &info.txHitCount)); -+ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister( -+ Hardware, -+ 0x0044C, -+ 0x00474, -+ 24, -+ 9, -+ &info.txMissCount)); -+ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister( -+ Hardware, -+ 0x0044C, -+ 0x00474, -+ 24, -+ 6, -+ &info.txBytes8)); -+#if gcdFRAME_DB_RESET -+ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister( -+ Hardware, -+ 0x0044C, -+ 0x00474, -+ 24, -+ 15, -+ &reset)); -+#endif -+ -+ /* Read clock control register. */ -+ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00000, -+ &clock)); -+ -+ /* Walk through all avaiable pixel pipes. */ -+ for (i = 0; i < Hardware->identity.pixelPipes; ++i) -+ { -+ /* Select proper pipe. */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00000, -+ ((((gctUINT32) (clock)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20))) | (((gctUINT32) ((gctUINT32) (i) & ((gctUINT32) ((((1 ? 23:20) - (0 ? 23:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:20) - (0 ? 23:20) + 1))))))) << (0 ? 23:20))))); -+ -+ /* Read cycle registers. */ -+ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00078, -+ &info.cycles[i])); -+ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x0007C, -+ &info.idleCycles[i])); -+ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00438, -+ &info.mcCycles[i])); -+ -+ /* Read bandwidth registers. */ -+ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x0005C, -+ &info.readRequests[i])); -+ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00040, -+ &info.readBytes8[i])); -+ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00050, -+ &info.writeRequests[i])); -+ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00044, -+ &info.writeBytes8[i])); -+ -+ /* Read PE counters. */ -+ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister( -+ Hardware, -+ 0x00454, -+ 0x00470, -+ 16, -+ 0, -+ &info.colorKilled[i])); -+ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister( -+ Hardware, -+ 0x00454, -+ 0x00470, -+ 16, -+ 2, -+ &info.colorDrawn[i])); -+ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister( -+ Hardware, -+ 0x00454, -+ 0x00470, -+ 16, -+ 1, -+ &info.depthKilled[i])); -+ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister( -+ Hardware, -+ 0x00454, -+ 0x00470, -+ 16, -+ 3, -+ &info.depthDrawn[i])); -+ } -+ -+ /* Zero out remaning reserved counters. */ -+ for (; i < 8; ++i) -+ { -+ info.readBytes8[i] = 0; -+ info.writeBytes8[i] = 0; -+ info.cycles[i] = 0; -+ info.idleCycles[i] = 0; -+ info.mcCycles[i] = 0; -+ info.readRequests[i] = 0; -+ info.writeRequests[i] = 0; -+ info.colorKilled[i] = 0; -+ info.colorDrawn[i] = 0; -+ info.depthKilled[i] = 0; -+ info.depthDrawn[i] = 0; -+ } -+ -+ /* Reset clock control register. */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00000, -+ clock)); -+ -+ /* Reset cycle and bandwidth counters. */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x0003C, -+ 1)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x0003C, -+ 0)); -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00078, -+ 0)); -+ -+#if gcdFRAME_DB_RESET -+ /* Reset PE counters. */ -+ gcmkONERROR(gckHARDWARE_ReadPerformanceRegister( -+ Hardware, -+ 0x00454, -+ 0x00470, -+ 16, -+ 15, -+ &reset)); -+#endif -+ -+ /* Copy to user. */ -+ gcmkONERROR(gckOS_CopyToUserData(Hardware->os, -+ &info, -+ FrameInfo, -+ gcmSIZEOF(info))); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+#if gcdDVFS -+#define READ_FROM_EATER1 0 -+ -+gceSTATUS -+gckHARDWARE_QueryLoad( -+ IN gckHARDWARE Hardware, -+ OUT gctUINT32 * Load -+ ) -+{ -+ gctUINT32 debug1; -+ gceSTATUS status; -+ gcmkHEADER_ARG("Hardware=0x%X", Hardware); -+ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ gcmkVERIFY_ARGUMENT(Load != gcvNULL); -+ -+ gckOS_AcquireMutex(Hardware->os, Hardware->powerMutex, gcvINFINITE); -+ -+ if (Hardware->chipPowerState == gcvPOWER_ON) -+ { -+ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00110, -+ Load)); -+#if READ_FROM_EATER1 -+ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00134, -+ Load)); -+#endif -+ -+ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00114, -+ &debug1)); -+ -+ /* Patch result of 0x110 with result of 0x114. */ -+ if ((debug1 & 0xFF) == 1) -+ { -+ *Load &= ~0xFF; -+ *Load |= 1; -+ } -+ -+ if (((debug1 & 0xFF00) >> 8) == 1) -+ { -+ *Load &= ~(0xFF << 8); -+ *Load |= 1 << 8; -+ } -+ -+ if (((debug1 & 0xFF0000) >> 16) == 1) -+ { -+ *Load &= ~(0xFF << 16); -+ *Load |= 1 << 16; -+ } -+ -+ if (((debug1 & 0xFF000000) >> 24) == 1) -+ { -+ *Load &= ~(0xFF << 24); -+ *Load |= 1 << 24; -+ } -+ } -+ else -+ { -+ status = gcvSTATUS_INVALID_REQUEST; -+ } -+ -+OnError: -+ -+ gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex); -+ -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckHARDWARE_SetDVFSPeroid( -+ IN gckHARDWARE Hardware, -+ OUT gctUINT32 Frequency -+ ) -+{ -+ gceSTATUS status; -+ gctUINT32 period; -+ gctUINT32 eater; -+ -+#if READ_FROM_EATER1 -+ gctUINT32 period1; -+ gctUINT32 eater1; -+#endif -+ -+ gcmkHEADER_ARG("Hardware=0x%X Frequency=%d", Hardware, Frequency); -+ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ period = 0; -+ -+ while((64 << period) < (gcdDVFS_ANAYLSE_WINDOW * Frequency * 1000) ) -+ { -+ period++; -+ } -+ -+#if READ_FROM_EATER1 -+ /* -+ * Peroid = F * 1000 * 1000 / (60 * 16 * 1024); -+ */ -+ period1 = Frequency * 6250 / 6114; -+#endif -+ -+ gckOS_AcquireMutex(Hardware->os, Hardware->powerMutex, gcvINFINITE); -+ -+ if (Hardware->chipPowerState == gcvPOWER_ON) -+ { -+ /* Get current configure. */ -+ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x0010C, -+ &eater)); -+ -+ /* Change peroid. */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x0010C, -+ ((((gctUINT32) (eater)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))) | (((gctUINT32) ((gctUINT32) (period) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1))))))) << (0 ? 15:8))))); -+ -+#if READ_FROM_EATER1 -+ /* Config eater1. */ -+ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00130, -+ &eater1)); -+ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x00130, -+ ((((gctUINT32) (eater1)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:16) - (0 ? 31:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:16) - (0 ? 31:16) + 1))))))) << (0 ? 31:16))) | (((gctUINT32) ((gctUINT32) (period1) & ((gctUINT32) ((((1 ? 31:16) - (0 ? 31:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:16) - (0 ? 31:16) + 1))))))) << (0 ? 31:16))))); -+#endif -+ } -+ else -+ { -+ status = gcvSTATUS_INVALID_REQUEST; -+ } -+ -+OnError: -+ gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex); -+ -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckHARDWARE_InitDVFS( -+ IN gckHARDWARE Hardware -+ ) -+{ -+ gceSTATUS status; -+ gctUINT32 data; -+ -+ gcmkHEADER_ARG("Hardware=0x%X", Hardware); -+ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ gcmkONERROR(gckOS_ReadRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x0010C, -+ &data)); -+ -+ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))); -+ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1))))))) << (0 ? 18:18))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1))))))) << (0 ? 18:18))); -+ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))); -+ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20))); -+ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1))))))) << (0 ? 23:23))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 23:23) - (0 ? 23:23) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 23:23) - (0 ? 23:23) + 1))))))) << (0 ? 23:23))); -+ data = ((((gctUINT32) (data)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1))))))) << (0 ? 22:22))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 22:22) - (0 ? 22:22) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 22:22) - (0 ? 22:22) + 1))))))) << (0 ? 22:22))); -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "DVFS Configure=0x%X", -+ data); -+ -+ gcmkONERROR(gckOS_WriteRegisterEx(Hardware->os, -+ Hardware->core, -+ 0x0010C, -+ data)); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ gcmkFOOTER(); -+ return status; -+} -+#endif -+ -+/******************************************************************************* -+** -+** gckHARDWARE_PrepareFunctions -+** -+** Generate command buffer snippets which will be used by gckHARDWARE, by which -+** gckHARDWARE can manipulate GPU by FE command without using gckCOMMAND to avoid -+** race condition and deadlock. -+** -+** Notice: -+** 1. Each snippet can only be executed when GPU is idle. -+** 2. Execution is triggered by AHB (0x658) -+** 3. Each snippet followed by END so software can sync with GPU by checking GPU -+** idle -+** 4. It is transparent to gckCOMMAND command buffer. -+** -+** Existing Snippets: -+** 1. MMU Configure -+** For new MMU, after GPU is reset, FE execute this command sequence to enble MMU. -+*/ -+gceSTATUS -+gckHARDWARE_PrepareFunctions( -+ gckHARDWARE Hardware -+ ) -+{ -+ gceSTATUS status; -+ gckOS os; -+ gctUINT32 offset = 0; -+ gctUINT32 mmuBytes; -+ gctUINT32 endBytes; -+ gctUINT8_PTR logical; -+ -+ gcmkHEADER_ARG("%x", Hardware); -+ -+ os = Hardware->os; -+ -+ gcmkVERIFY_OK(gckOS_GetPageSize(os, &Hardware->functionBytes)); -+ -+ /* Allocate a command buffer. */ -+ gcmkONERROR(gckOS_AllocateNonPagedMemory( -+ os, -+ gcvFALSE, -+ &Hardware->functionBytes, -+ &Hardware->functionPhysical, -+ &Hardware->functionLogical -+ )); -+ -+ gcmkONERROR(gckOS_GetPhysicalAddress( -+ os, -+ Hardware->functionLogical, -+ &Hardware->functionAddress -+ )); -+ -+ if (Hardware->mmuVersion > 0) -+ { -+ /* MMU configure command sequence. */ -+ logical = (gctUINT8_PTR)Hardware->functionLogical + offset; -+ -+ Hardware->functions[gcvHARDWARE_FUNCTION_MMU].address -+ = Hardware->functionAddress + offset; -+ -+ gcmkONERROR(gckHARDWARE_SetMMUStates( -+ Hardware, -+ Hardware->kernel->mmu->mtlbLogical, -+ gcvMMU_MODE_4K, -+ (gctUINT8_PTR)Hardware->kernel->mmu->mtlbLogical + gcdMMU_MTLB_SIZE, -+ logical, -+ &mmuBytes -+ )); -+ -+ offset += mmuBytes; -+ -+ logical = (gctUINT8_PTR)Hardware->functionLogical + offset; -+ -+ gcmkONERROR(gckHARDWARE_End( -+ Hardware, -+ gcvNULL, -+ &endBytes -+ )); -+ -+ gcmkONERROR(gckHARDWARE_End( -+ Hardware, -+ logical, -+ &endBytes -+ )); -+ -+ offset += endBytes; -+ -+ Hardware->functions[gcvHARDWARE_FUNCTION_MMU].bytes = mmuBytes + endBytes; -+ } -+ -+ gcmkASSERT(offset < Hardware->functionBytes); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ gcmkFOOTER(); -+ return status; -+} -+ -+ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/arch/gc_hal_kernel_hardware.h linux-4.1.13/drivers/gpu/galcore/arch/gc_hal_kernel_hardware.h ---- linux-4.1.13.orig/drivers/gpu/galcore/arch/gc_hal_kernel_hardware.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/arch/gc_hal_kernel_hardware.h 2015-11-30 17:56:13.560139057 +0100 -@@ -0,0 +1,160 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#ifndef __gc_hal_kernel_hardware_h_ -+#define __gc_hal_kernel_hardware_h_ -+ -+#if gcdENABLE_VG -+#include "gc_hal_kernel_hardware_vg.h" -+#endif -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+typedef enum { -+ gcvHARDWARE_FUNCTION_MMU, -+ gcvHARDWARE_FUNCTION_FLUSH, -+ -+ gcvHARDWARE_FUNCTION_NUM, -+} -+gceHARDWARE_FUNCTION; -+ -+ -+typedef struct _gcsHARWARE_FUNCTION -+{ -+ /* Entry of the function. */ -+ gctUINT32 address; -+ -+ /* Bytes of the function. */ -+ gctUINT32 bytes; -+} -+gcsHARDWARE_FUNCTION; -+ -+/* gckHARDWARE object. */ -+struct _gckHARDWARE -+{ -+ /* Object. */ -+ gcsOBJECT object; -+ -+ /* Pointer to gctKERNEL object. */ -+ gckKERNEL kernel; -+ -+ /* Pointer to gctOS object. */ -+ gckOS os; -+ -+ /* Core */ -+ gceCORE core; -+ -+ /* Chip characteristics. */ -+ gcsHAL_QUERY_CHIP_IDENTITY identity; -+ gctBOOL allowFastClear; -+ gctBOOL allowCompression; -+ gctUINT32 powerBaseAddress; -+ gctBOOL extraEventStates; -+ -+ /* Big endian */ -+ gctBOOL bigEndian; -+ -+ /* Chip status */ -+ gctPOINTER powerMutex; -+ gctUINT32 powerProcess; -+ gctUINT32 powerThread; -+ gceCHIPPOWERSTATE chipPowerState; -+ gctUINT32 lastWaitLink; -+ gctUINT32 lastEnd; -+ gctBOOL clockState; -+ gctBOOL powerState; -+ gctPOINTER globalSemaphore; -+ -+ gctISRMANAGERFUNC startIsr; -+ gctISRMANAGERFUNC stopIsr; -+ gctPOINTER isrContext; -+ -+ gctUINT32 mmuVersion; -+ -+ /* Whether use new MMU. It is meaningless -+ ** for old MMU since old MMU is always enabled. -+ */ -+ gctBOOL enableMMU; -+ -+ /* Type */ -+ gceHARDWARE_TYPE type; -+ -+#if gcdPOWEROFF_TIMEOUT -+ gctUINT32 powerOffTime; -+ gctUINT32 powerOffTimeout; -+ gctPOINTER powerOffTimer; -+#endif -+ -+#if gcdENABLE_FSCALE_VAL_ADJUST -+ gctUINT32 powerOnFscaleVal; -+#endif -+ gctPOINTER pageTableDirty; -+ -+#if gcdLINK_QUEUE_SIZE -+ struct _gckLINKQUEUE linkQueue; -+#endif -+ -+ gctBOOL powerManagement; -+ gctBOOL powerManagementLock; -+ gctBOOL gpuProfiler; -+ -+ gctBOOL endAfterFlushMmuCache; -+ -+ gctUINT32 minFscaleValue; -+ -+ gctPOINTER pendingEvent; -+ -+ /* Function used by gckHARDWARE. */ -+ gctPHYS_ADDR functionPhysical; -+ gctPOINTER functionLogical; -+ gctUINT32 functionAddress; -+ gctSIZE_T functionBytes; -+ -+ gcsHARDWARE_FUNCTION functions[gcvHARDWARE_FUNCTION_NUM]; -+}; -+ -+gceSTATUS -+gckHARDWARE_GetBaseAddress( -+ IN gckHARDWARE Hardware, -+ OUT gctUINT32_PTR BaseAddress -+ ); -+ -+gceSTATUS -+gckHARDWARE_NeedBaseAddress( -+ IN gckHARDWARE Hardware, -+ IN gctUINT32 State, -+ OUT gctBOOL_PTR NeedBase -+ ); -+ -+gceSTATUS -+gckHARDWARE_GetFrameInfo( -+ IN gckHARDWARE Hardware, -+ OUT gcsHAL_FRAME_INFO * FrameInfo -+ ); -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* __gc_hal_kernel_hardware_h_ */ -+ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/arch/gc_hal_kernel_recorder.c linux-4.1.13/drivers/gpu/galcore/arch/gc_hal_kernel_recorder.c ---- linux-4.1.13.orig/drivers/gpu/galcore/arch/gc_hal_kernel_recorder.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/arch/gc_hal_kernel_recorder.c 2015-11-30 17:56:13.564138792 +0100 -@@ -0,0 +1,679 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#include "gc_hal.h" -+#include "gc_hal_kernel.h" -+#include "gc_hal_kernel_context.h" -+ -+/* -+ * ----------------------- -+ * HARDWARE STATE RECORDER -+ * ----------------------- -+ * -+ * State mirror buffer is used to 'mirror' hardware states since hardware -+ * states can't be dumpped. It is a context buffer which stores 'global' -+ * context. -+ * -+ * For each commit, state recorder -+ * 1) Records context buffer (if there is) and command buffers in this commit. -+ * 2) Parse those buffers to estimate the state changed. -+ * 3) Stores result to a mirror buffer. -+ * -+ * == Commit 0 ==================================================================== -+ * -+ * Context Buffer 0 -+ * -+ * Command Buffer 0 -+ * -+ * Mirror Buffer 0 <- Context Buffer 0 + Command Buffer 0 -+ * -+ * == Commit 1 ==================================================================== -+ * -+ * Command Buffer 1 -+ * -+ * Mirror Buffer 1 <- Command buffer 1 + Mirror Buffer 0 -+ * -+ * == Commit 2 ==================================================================== -+ * -+ * Context Buffer 2 (optional) -+ * -+ * Command Buffer 2 -+ * -+ * Mirror Buffer 2 <- Command buffer 2 + Context Buffer 2 + Mirror Buffer 1 -+ * -+ * == Commit N ==================================================================== -+ * -+ * For Commit N, these buffers are needed to reproduce hardware's behavior in -+ * this commit. -+ * -+ * Mirror Buffer [N - 1] : State Mirror accumlated by past commits, -+ * which is used to restore hardware state. -+ * Context Buffer [N] : -+ * Command Buffer [N] : Command buffer executed by hardware in this commit. -+ * -+ * If sequence of states programming matters, hardware's behavior can't be reproduced, -+ * but the state values stored in mirror buffer are assuring. -+ */ -+ -+/* Queue size. */ -+#define gcdNUM_RECORDS 6 -+ -+typedef struct _gcsPARSER_HANDLER * gckPARSER_HANDLER; -+ -+typedef void -+(*HandlerFunction)( -+ IN gckPARSER_HANDLER Handler, -+ IN gctUINT32 Addr, -+ IN gctUINT32 Data -+ ); -+ -+typedef struct _gcsPARSER_HANDLER -+{ -+ gctUINT32 type; -+ gctUINT32 cmd; -+ gctPOINTER private; -+ HandlerFunction function; -+} -+gcsPARSER_HANDLER; -+ -+typedef struct _gcsPARSER * gckPARSER; -+typedef struct _gcsPARSER -+{ -+ gctUINT8_PTR currentCmdBufferAddr; -+ -+ /* Current command. */ -+ gctUINT32 lo; -+ gctUINT32 hi; -+ -+ gctUINT8 cmdOpcode; -+ gctUINT16 cmdAddr; -+ gctUINT32 cmdSize; -+ gctUINT32 cmdRectCount; -+ gctUINT8 skip; -+ gctUINT32 skipCount; -+ -+ gctBOOL allow; -+ -+ /* Callback used by parser to handle a command. */ -+ gckPARSER_HANDLER commandHandler; -+} -+gcsPARSER; -+ -+typedef struct _gcsMIRROR -+{ -+ gctUINT32_PTR logical[gcdNUM_RECORDS]; -+ gctUINT32 bytes; -+ gcsSTATE_MAP_PTR map; -+ gctUINT32 stateCount; -+} -+gcsMIRROR; -+ -+typedef struct _gcsDELTA -+{ -+ gctUINT64 commitStamp; -+ gctUINT32_PTR command; -+ gctUINT32 commandBytes; -+ gctUINT32_PTR context; -+ gctUINT32 contextBytes; -+} -+gcsDELTA; -+ -+typedef struct _gcsRECORDER -+{ -+ gckOS os; -+ gcsMIRROR mirror; -+ gcsDELTA deltas[gcdNUM_RECORDS]; -+ -+ /* Index of current record. */ -+ gctUINT index; -+ -+ /* Number of records. */ -+ gctUINT num; -+ -+ /* Plugin used by gckPARSER. */ -+ gcsPARSER_HANDLER recorderHandler; -+ gckPARSER parser; -+} -+gcsRECORDER; -+ -+ -+/******************************************************************************\ -+***************************** Command Buffer Parser **************************** -+\******************************************************************************/ -+ -+/* -+** Command buffer parser checks command buffer in FE's view to make sure there -+** is no format error. -+** -+** Parser provide a callback mechnisam, so plug-in can be added to implement -+** other functions. -+*/ -+ -+static void -+_HandleLoadState( -+ IN OUT gckPARSER Parser -+ ) -+{ -+ gctUINT i; -+ gctUINT32_PTR data = (gctUINT32_PTR)Parser->currentCmdBufferAddr; -+ gctUINT32 cmdAddr = Parser->cmdAddr; -+ -+ if (Parser->commandHandler == gcvNULL -+ || Parser->commandHandler->cmd != 0x01 -+ ) -+ { -+ /* No handler for this command. */ -+ return; -+ } -+ -+ for (i = 0; i < Parser->cmdSize; i++) -+ { -+ Parser->commandHandler->function(Parser->commandHandler, cmdAddr, *data); -+ -+ /* Advance to next state. */ -+ cmdAddr++; -+ data++; -+ } -+} -+ -+static void -+_GetCommand( -+ IN OUT gckPARSER Parser -+ ) -+{ -+ gctUINT32 * buffer = (gctUINT32 *)Parser->currentCmdBufferAddr; -+ -+ gctUINT16 cmdRectCount; -+ gctUINT16 cmdDataCount; -+ -+ Parser->hi = buffer[0]; -+ Parser->lo = buffer[1]; -+ -+ Parser->cmdOpcode = (((((gctUINT32) (Parser->hi)) >> (0 ? 31:27)) & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1)))))) ); -+ Parser->cmdRectCount = 1; -+ -+ switch (Parser->cmdOpcode) -+ { -+ case 0x01: -+ /* Extract count. */ -+ Parser->cmdSize = (((((gctUINT32) (Parser->hi)) >> (0 ? 25:16)) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1)))))) ); -+ if (Parser->cmdSize == 0) -+ { -+ /* 0 means 1024. */ -+ Parser->cmdSize = 1024; -+ } -+ Parser->skip = (Parser->cmdSize & 0x1) ? 0 : 1; -+ -+ /* Extract address. */ -+ Parser->cmdAddr = (((((gctUINT32) (Parser->hi)) >> (0 ? 15:0)) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1)))))) ); -+ -+ Parser->currentCmdBufferAddr = Parser->currentCmdBufferAddr + 4; -+ Parser->skipCount = Parser->cmdSize + Parser->skip; -+ break; -+ -+ case 0x05: -+ Parser->cmdSize = 4; -+ Parser->skipCount = gcmALIGN(Parser->cmdSize, 2); -+ break; -+ -+ case 0x06: -+ Parser->cmdSize = 5; -+ Parser->skipCount = gcmALIGN(Parser->cmdSize, 2); -+ break; -+ -+ case 0x0C: -+ Parser->cmdSize = 3; -+ Parser->skipCount = gcmALIGN(Parser->cmdSize, 2); -+ break; -+ -+ case 0x09: -+ Parser->cmdSize = 2; -+ Parser->cmdAddr = 0x0F16; -+ Parser->skipCount = gcmALIGN(Parser->cmdSize, 2); -+ break; -+ -+ case 0x04: -+ Parser->cmdSize = 1; -+ Parser->cmdAddr = 0x0F06; -+ -+ cmdRectCount = (((((gctUINT32) (Parser->hi)) >> (0 ? 15:8)) & ((gctUINT32) ((((1 ? 15:8) - (0 ? 15:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:8) - (0 ? 15:8) + 1)))))) ); -+ cmdDataCount = (((((gctUINT32) (Parser->hi)) >> (0 ? 26:16)) & ((gctUINT32) ((((1 ? 26:16) - (0 ? 26:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 26:16) - (0 ? 26:16) + 1)))))) ); -+ -+ Parser->skipCount = gcmALIGN(Parser->cmdSize, 2) -+ + cmdRectCount * 2 -+ + gcmALIGN(cmdDataCount, 2); -+ -+ Parser->cmdRectCount = cmdRectCount; -+ break; -+ -+ case 0x03: -+ Parser->currentCmdBufferAddr = Parser->currentCmdBufferAddr + 8; -+ Parser->skipCount = 0; -+ break; -+ -+ case 0x02: -+ Parser->currentCmdBufferAddr = Parser->currentCmdBufferAddr + 8; -+ Parser->skipCount = 0; -+ break; -+ -+ default: -+ /* Unknown command is a risk. */ -+ Parser->allow = gcvFALSE; -+ break; -+ } -+} -+ -+static void -+_ParseCommand( -+ IN OUT gckPARSER Parser -+ ) -+{ -+ switch(Parser->cmdOpcode) -+ { -+ case 0x01: -+ _HandleLoadState(Parser); -+ break; -+ case 0x05: -+ case 0x06: -+ case 0x0C: -+ break; -+ case 0x04: -+ break; -+ default: -+ break; -+ } -+ -+ /* Advance to next command. */ -+ Parser->currentCmdBufferAddr = Parser->currentCmdBufferAddr -+ + (Parser->skipCount << 2); -+} -+ -+gceSTATUS -+gckPARSER_Parse( -+ IN gckPARSER Parser, -+ IN gctUINT8_PTR Buffer, -+ IN gctUINT32 Bytes -+ ) -+{ -+ gckPARSER parser = Parser; -+ gctUINT8_PTR end = (gctUINT8_PTR)Buffer + Bytes; -+ -+ /* Initialize parser. */ -+ parser->currentCmdBufferAddr = (gctUINT8_PTR)Buffer; -+ parser->skip = 0; -+ parser->allow = gcvTRUE; -+ -+ /* Go through command buffer until reaching the end -+ ** or meeting an error. */ -+ do -+ { -+ _GetCommand(parser); -+ -+ _ParseCommand(parser); -+ } -+ while ((parser->currentCmdBufferAddr < end) && (parser->allow == gcvTRUE)); -+ -+ if (parser->allow == gcvFALSE) -+ { -+ /* Error detected. */ -+ return gcvSTATUS_NOT_SUPPORTED; -+ } -+ -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckPARSER_RegisterCommandHandler -+** -+** Register a command handler which will be called when parser get a command. -+** -+*/ -+gceSTATUS -+gckPARSER_RegisterCommandHandler( -+ IN gckPARSER Parser, -+ IN gckPARSER_HANDLER Handler -+ ) -+{ -+ Parser->commandHandler = Handler; -+ -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckPARSER_Construct( -+ IN gckOS Os, -+ IN gckPARSER_HANDLER Handler, -+ OUT gckPARSER * Parser -+ ) -+{ -+ gceSTATUS status; -+ gckPARSER pointer; -+ -+ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(gcsPARSER), (gctPOINTER *)&pointer)); -+ -+ /* Put it here temp, should have a more general plug-in mechnisam. */ -+ pointer->commandHandler = Handler; -+ -+ *Parser = pointer; -+ -+ return gcvSTATUS_OK; -+ -+OnError: -+ return status; -+} -+ -+void -+gckPARSER_Destroy( -+ IN gckOS Os, -+ IN gckPARSER Parser -+ ) -+{ -+ gcmkOS_SAFE_FREE(Os, Parser); -+} -+ -+/******************************************************************************\ -+**************************** Hardware States Recorder ************************** -+\******************************************************************************/ -+ -+static void -+_RecodeState( -+ IN gckPARSER_HANDLER Handler, -+ IN gctUINT32 Addr, -+ IN gctUINT32 Data -+ ) -+{ -+ gcmkVERIFY_OK(gckRECORDER_UpdateMirror(Handler->private, Addr, Data)); -+} -+ -+static gctUINT -+_Previous( -+ IN gctUINT Index -+ ) -+{ -+ if (Index == 0) -+ { -+ return gcdNUM_RECORDS - 1; -+ } -+ -+ return Index - 1; -+} -+ -+static gctUINT -+_Next( -+ IN gctUINT Index -+ ) -+{ -+ return (Index + 1) % gcdNUM_RECORDS; -+} -+ -+gceSTATUS -+gckRECORDER_Construct( -+ IN gckOS Os, -+ IN gckHARDWARE Hardware, -+ OUT gckRECORDER * Recorder -+ ) -+{ -+ gceSTATUS status; -+ gckCONTEXT context = gcvNULL; -+ gckRECORDER recorder = gcvNULL; -+ gctUINT32 mapSize; -+ gctUINT i; -+ gctBOOL virtualCommandBuffer = Hardware->kernel->virtualCommandBuffer; -+ -+ /* TODO: We only need context buffer and state map, it should be able to get without construct a -+ ** new context. -+ ** Now it is leaked, since we can't free it when command buffer is gone. -+ */ -+ -+ /* MMU is not ready now. */ -+ Hardware->kernel->virtualCommandBuffer = gcvFALSE; -+ -+ gcmkONERROR(gckCONTEXT_Construct(Os, Hardware, 0, &context)); -+ -+ /* Restore. */ -+ Hardware->kernel->virtualCommandBuffer = virtualCommandBuffer; -+ -+ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(gcsRECORDER), (gctPOINTER *)&recorder)); -+ -+ gckOS_ZeroMemory(recorder, gcmSIZEOF(gcsRECORDER)); -+ -+ /* Copy state map. */ -+ recorder->mirror.stateCount = context->stateCount; -+ -+ mapSize = context->stateCount * gcmSIZEOF(gcsSTATE_MAP); -+ -+ gcmkONERROR(gckOS_Allocate(Os, mapSize, (gctPOINTER *)&recorder->mirror.map)); -+ -+ gckOS_MemCopy(recorder->mirror.map, context->map, mapSize); -+ -+ /* Copy context buffer. */ -+ recorder->mirror.bytes = context->totalSize; -+ -+ for (i = 0; i < gcdNUM_RECORDS; i++) -+ { -+ gcmkONERROR(gckOS_Allocate(Os, context->totalSize, (gctPOINTER *)&recorder->mirror.logical[i])); -+ gckOS_MemCopy(recorder->mirror.logical[i], context->buffer->logical, context->totalSize); -+ } -+ -+ for (i = 0; i < gcdNUM_RECORDS; i++) -+ { -+ /* TODO : Optimize size. */ -+ gcmkONERROR(gckOS_Allocate(Os, gcdCMD_BUFFER_SIZE, (gctPOINTER *)&recorder->deltas[i].command)); -+ gcmkONERROR(gckOS_Allocate(Os, context->totalSize, (gctPOINTER *)&recorder->deltas[i].context)); -+ } -+ -+ recorder->index = 0; -+ recorder->num = 0; -+ -+ /* Initialize Parser plugin. */ -+ recorder->recorderHandler.cmd = 0x01; -+ recorder->recorderHandler.private = recorder; -+ recorder->recorderHandler.function = _RecodeState; -+ -+ gcmkONERROR(gckPARSER_Construct(Os, &recorder->recorderHandler, &recorder->parser)); -+ -+ recorder->os = Os; -+ -+ *Recorder = recorder; -+ -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (recorder) -+ { -+ gckRECORDER_Destory(Os, recorder); -+ } -+ -+ return status; -+} -+ -+gceSTATUS -+gckRECORDER_Destory( -+ IN gckOS Os, -+ IN gckRECORDER Recorder -+ ) -+{ -+ gctUINT i; -+ -+ if (Recorder->mirror.map) -+ { -+ gcmkOS_SAFE_FREE(Os, Recorder->mirror.map); -+ } -+ -+ for (i = 0; i < gcdNUM_RECORDS; i++) -+ { -+ if (Recorder->mirror.logical[i]) -+ { -+ gcmkOS_SAFE_FREE(Os, Recorder->mirror.logical[i]); -+ } -+ } -+ -+ for (i = 0; i < gcdNUM_RECORDS; i++) -+ { -+ if (Recorder->deltas[i].command) -+ { -+ gcmkOS_SAFE_FREE(Os, Recorder->deltas[i].command); -+ } -+ -+ if (Recorder->deltas[i].context) -+ { -+ gcmkOS_SAFE_FREE(Os, Recorder->deltas[i].context); -+ } -+ } -+ -+ if (Recorder->parser) -+ { -+ gckPARSER_Destroy(Os, Recorder->parser); -+ } -+ -+ gcmkOS_SAFE_FREE(Os, Recorder); -+ -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckRECORDER_UpdateMirror( -+ IN gckRECORDER Recorder, -+ IN gctUINT32 State, -+ IN gctUINT32 Data -+ ) -+{ -+ gctUINT32 index; -+ gcsSTATE_MAP_PTR map = Recorder->mirror.map; -+ gctUINT32_PTR buffer = Recorder->mirror.logical[Recorder->index]; -+ -+ if (State >= Recorder->mirror.stateCount) -+ { -+ /* Ignore them just like HW does. */ -+ return gcvSTATUS_OK; -+ } -+ -+ index = map[State].index; -+ -+ if (index) -+ { -+ buffer[index] = Data; -+ } -+ -+ return gcvSTATUS_OK; -+} -+ -+void -+gckRECORDER_AdvanceIndex( -+ IN gckRECORDER Recorder, -+ IN gctUINT64 CommitStamp -+ ) -+{ -+ /* Get next record. */ -+ gctUINT next = (Recorder->index + 1) % gcdNUM_RECORDS; -+ -+ /* Record stamp of this commit. */ -+ Recorder->deltas[Recorder->index].commitStamp = CommitStamp; -+ -+ /* Mirror of next record is mirror of this record and delta in next record. */ -+ gckOS_MemCopy(Recorder->mirror.logical[next], -+ Recorder->mirror.logical[Recorder->index], Recorder->mirror.bytes); -+ -+ /* Advance to next record. */ -+ Recorder->index = next; -+ -+ Recorder->num = gcmMIN(Recorder->num + 1, gcdNUM_RECORDS - 1); -+ -+ -+ /* Reset delta. */ -+ Recorder->deltas[Recorder->index].commandBytes = 0; -+ Recorder->deltas[Recorder->index].contextBytes = 0; -+} -+ -+void -+gckRECORDER_Record( -+ IN gckRECORDER Recorder, -+ IN gctUINT8_PTR CommandBuffer, -+ IN gctUINT32 CommandBytes, -+ IN gctUINT8_PTR ContextBuffer, -+ IN gctUINT32 ContextBytes -+ ) -+{ -+ gcsDELTA * delta = &Recorder->deltas[Recorder->index]; -+ -+ if (CommandBytes != 0xFFFFFFFF) -+ { -+ gckPARSER_Parse(Recorder->parser, CommandBuffer, CommandBytes); -+ gckOS_MemCopy(delta->command, CommandBuffer, CommandBytes); -+ delta->commandBytes = CommandBytes; -+ } -+ -+ if (ContextBytes != 0xFFFFFFFF) -+ { -+ gckPARSER_Parse(Recorder->parser, ContextBuffer, ContextBytes); -+ gckOS_MemCopy(delta->context, ContextBuffer, ContextBytes); -+ delta->contextBytes = ContextBytes; -+ } -+} -+ -+void -+gckRECORDER_Dump( -+ IN gckRECORDER Recorder -+ ) -+{ -+ gctUINT last = Recorder->index; -+ gctUINT previous; -+ gctUINT i; -+ gcsMIRROR *mirror = &Recorder->mirror; -+ gcsDELTA *delta; -+ gckOS os = Recorder->os; -+ -+ for (i = 0; i < Recorder->num; i++) -+ { -+ last = _Previous(last); -+ } -+ -+ for (i = 0; i < Recorder->num; i++) -+ { -+ delta = &Recorder->deltas[last]; -+ -+ /* Dump record */ -+ gcmkPRINT("#[commit %llu]", delta->commitStamp); -+ -+ if (delta->commitStamp) -+ { -+ previous = _Previous(last); -+ -+ gcmkPRINT("#[mirror]"); -+ gckOS_DumpBuffer(os, mirror->logical[previous], mirror->bytes, gceDUMP_BUFFER_CONTEXT, gcvTRUE); -+ gcmkPRINT("@[kernel.execute]"); -+ } -+ -+ if (delta->contextBytes) -+ { -+ gckOS_DumpBuffer(os, delta->context, delta->contextBytes, gceDUMP_BUFFER_CONTEXT, gcvTRUE); -+ gcmkPRINT("@[kernel.execute]"); -+ } -+ -+ gckOS_DumpBuffer(os, delta->command, delta->commandBytes, gceDUMP_BUFFER_USER, gcvTRUE); -+ gcmkPRINT("@[kernel.execute]"); -+ -+ last = _Next(last); -+ } -+} -+ -+ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/archvg/gc_hal_kernel_hardware_command_vg.c linux-4.1.13/drivers/gpu/galcore/archvg/gc_hal_kernel_hardware_command_vg.c ---- linux-4.1.13.orig/drivers/gpu/galcore/archvg/gc_hal_kernel_hardware_command_vg.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/archvg/gc_hal_kernel_hardware_command_vg.c 2015-11-30 17:56:13.564138792 +0100 -@@ -0,0 +1,932 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#include "gc_hal.h" -+#include "gc_hal_kernel.h" -+ -+#if gcdENABLE_VG -+ -+#include "gc_hal_kernel_hardware_command_vg.h" -+ -+#define _GC_OBJ_ZONE gcvZONE_COMMAND -+ -+/******************************************************************************\ -+****************************** gckVGCOMMAND API code ***************************** -+\******************************************************************************/ -+ -+/******************************************************************************* -+** -+** gckVGCOMMAND_InitializeInfo -+** -+** Initialize architecture dependent command buffer information. -+** -+** INPUT: -+** -+** gckVGCOMMAND Command -+** Pointer to the Command object. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckVGCOMMAND_InitializeInfo( -+ IN gckVGCOMMAND Command -+ ) -+{ -+ gceSTATUS status; -+ gcmkHEADER_ARG("Command=0x%x", Command); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND); -+ -+ do -+ { -+ /* Reset interrupts. */ -+ Command->info.feBufferInt = -1; -+ Command->info.tsOverflowInt = -1; -+ -+ /* Set command buffer attributes. */ -+ Command->info.addressAlignment = 64; -+ Command->info.commandAlignment = 8; -+ -+ /* Determine command alignment address mask. */ -+ Command->info.addressMask = ((((gctUINT32) (Command->info.addressAlignment - 1)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) ((gctUINT32) (0 ) & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))); -+ -+ /* Query the number of bytes needed by the STATE command. */ -+ gcmkERR_BREAK(gckVGCOMMAND_StateCommand( -+ Command, 0x0, gcvNULL, (gctUINT32)~0, 0, -+ &Command->info.stateCommandSize -+ )); -+ -+ /* Query the number of bytes needed by the RESTART command. */ -+ gcmkERR_BREAK(gckVGCOMMAND_RestartCommand( -+ Command, gcvNULL, (gctUINT32)~0, 0, -+ &Command->info.restartCommandSize -+ )); -+ -+ /* Query the number of bytes needed by the FETCH command. */ -+ gcmkERR_BREAK(gckVGCOMMAND_FetchCommand( -+ Command, gcvNULL, (gctUINT32)~0, 0, -+ &Command->info.fetchCommandSize -+ )); -+ -+ /* Query the number of bytes needed by the CALL command. */ -+ gcmkERR_BREAK(gckVGCOMMAND_CallCommand( -+ Command, gcvNULL, (gctUINT32)~0, 0, -+ &Command->info.callCommandSize -+ )); -+ -+ /* Query the number of bytes needed by the RETURN command. */ -+ gcmkERR_BREAK(gckVGCOMMAND_ReturnCommand( -+ Command, gcvNULL, -+ &Command->info.returnCommandSize -+ )); -+ -+ /* Query the number of bytes needed by the EVENT command. */ -+ gcmkERR_BREAK(gckVGCOMMAND_EventCommand( -+ Command, gcvNULL, gcvBLOCK_PIXEL, -1, -+ &Command->info.eventCommandSize -+ )); -+ -+ /* Query the number of bytes needed by the END command. */ -+ gcmkERR_BREAK(gckVGCOMMAND_EndCommand( -+ Command, gcvNULL, -1, -+ &Command->info.endCommandSize -+ )); -+ -+ /* Determine the tail reserve size. */ -+ Command->info.staticTailSize = gcmMAX( -+ Command->info.fetchCommandSize, -+ gcmMAX( -+ Command->info.returnCommandSize, -+ Command->info.endCommandSize -+ ) -+ ); -+ -+ /* Determine the maximum tail size. */ -+ Command->info.dynamicTailSize -+ = Command->info.staticTailSize -+ + Command->info.eventCommandSize * gcvBLOCK_COUNT; -+ } -+ while (gcvFALSE); -+ -+ gcmkFOOTER(); -+ /* Return status. */ -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckVGCOMMAND_StateCommand -+** -+** Append a STATE command at the specified location in the command buffer. -+** -+** INPUT: -+** -+** gckVGCOMMAND Command -+** Pointer to an gckVGCOMMAND object. -+** -+** gctUINT32 Pipe -+** Harwdare destination pipe. -+** -+** gctPOINTER Logical -+** Pointer to the current location inside the command buffer to append -+** STATE command at or gcvNULL to query the size of the command. -+** -+** gctUINT32 Address -+** Starting register address of the state buffer. -+** If 'Logical' is gcvNULL, this argument is ignored. -+** -+** gctUINT32 Count -+** Number of states in state buffer. -+** If 'Logical' is gcvNULL, this argument is ignored. -+** -+** gctSIZE_T * Bytes -+** Pointer to the number of bytes available for the STATE command. -+** If 'Logical' is gcvNULL, the value from this argument is ignored. -+** -+** OUTPUT: -+** -+** gctSIZE_T * Bytes -+** Pointer to a variable that will receive the number of bytes required -+** for the STATE command. If 'Bytes' is gcvNULL, nothing is returned. -+*/ -+gceSTATUS -+gckVGCOMMAND_StateCommand( -+ IN gckVGCOMMAND Command, -+ IN gctUINT32 Pipe, -+ IN gctPOINTER Logical, -+ IN gctUINT32 Address, -+ IN gctUINT32 Count, -+ IN OUT gctUINT32 * Bytes -+ ) -+{ -+ gcmkHEADER_ARG("Command=0x%x Pipe=0x%x Logical=0x%x Address=0x%x Count=0x%x Bytes = 0x%x", -+ Command, Pipe, Logical, Address, Count, Bytes); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND); -+ -+ if (Command->fe20) -+ { -+ if (Logical != gcvNULL) -+ { -+ gctUINT32_PTR buffer; -+ -+ /* Cast the buffer pointer. */ -+ buffer = (gctUINT32_PTR) Logical; -+ -+ /* Append STATE. */ -+ buffer[0] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x3 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 11:0) - (0 ? 11:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:0) - (0 ? 11:0) + 1))))))) << (0 ? 11:0))) | (((gctUINT32) ((gctUINT32) (Address) & ((gctUINT32) ((((1 ? 11:0) - (0 ? 11:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:0) - (0 ? 11:0) + 1))))))) << (0 ? 11:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 27:16) - (0 ? 27:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:16) - (0 ? 27:16) + 1))))))) << (0 ? 27:16))) | (((gctUINT32) ((gctUINT32) (Count) & ((gctUINT32) ((((1 ? 27:16) - (0 ? 27:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:16) - (0 ? 27:16) + 1))))))) << (0 ? 27:16))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 13:12) - (0 ? 13:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:12) - (0 ? 13:12) + 1))))))) << (0 ? 13:12))) | (((gctUINT32) ((gctUINT32) (Pipe) & ((gctUINT32) ((((1 ? 13:12) - (0 ? 13:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:12) - (0 ? 13:12) + 1))))))) << (0 ? 13:12))); -+ } -+ -+ if (Bytes != gcvNULL) -+ { -+ /* Return number of bytes required by the STATE command. */ -+ *Bytes = 4 * (Count + 1); -+ } -+ } -+ else -+ { -+ if (Logical != gcvNULL) -+ { -+ gctUINT32_PTR buffer; -+ -+ /* Cast the buffer pointer. */ -+ buffer = (gctUINT32_PTR) Logical; -+ -+ /* Append LOAD_STATE. */ -+ buffer[0] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (Count) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (Address) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); -+ } -+ -+ if (Bytes != gcvNULL) -+ { -+ /* Return number of bytes required by the STATE command. */ -+ *Bytes = 4 * (Count + 1); -+ } -+ } -+ -+ gcmkFOOTER_NO(); -+ /* Success. */ -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckVGCOMMAND_RestartCommand -+** -+** Form a RESTART command at the specified location in the command buffer. -+** -+** INPUT: -+** -+** gckVGCOMMAND Command -+** Pointer to an gckVGCOMMAND object. -+** -+** gctPOINTER Logical -+** Pointer to the current location inside the command buffer to append -+** RESTART command at or gcvNULL to query the size of the command. -+** -+** gctUINT32 FetchAddress -+** The address of another command buffer to be executed by this RESTART -+** command. If 'Logical' is gcvNULL, this argument is ignored. -+** -+** gctUINT FetchCount -+** The number of 64-bit data quantities in another command buffer to -+** be executed by this RESTART command. If 'Logical' is gcvNULL, this -+** argument is ignored. -+** -+** gctSIZE_T * Bytes -+** Pointer to the number of bytes available for the RESTART command. -+** If 'Logical' is gcvNULL, the value from this argument is ignored. -+** -+** OUTPUT: -+** -+** gctSIZE_T * Bytes -+** Pointer to a variable that will receive the number of bytes required -+** for the RESTART command. If 'Bytes' is gcvNULL, nothing is returned. -+*/ -+gceSTATUS -+gckVGCOMMAND_RestartCommand( -+ IN gckVGCOMMAND Command, -+ IN gctPOINTER Logical, -+ IN gctUINT32 FetchAddress, -+ IN gctUINT FetchCount, -+ IN OUT gctUINT32 * Bytes -+ ) -+{ -+ gcmkHEADER_ARG("Command=0x%x Logical=0x%x FetchAddress=0x%x FetchCount=0x%x Bytes = 0x%x", -+ Command, Logical, FetchAddress, FetchCount, Bytes); -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND); -+ -+ if (Command->fe20) -+ { -+ if (Logical != gcvNULL) -+ { -+ gctUINT32_PTR buffer; -+ gctUINT32 beginEndMark; -+ -+ /* Cast the buffer pointer. */ -+ buffer = (gctUINT32_PTR) Logical; -+ -+ /* Determine Begin/End flag. */ -+ beginEndMark = (FetchCount > 0) -+ ? ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24))) -+ : ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 24:24) - (0 ? 24:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 24:24) - (0 ? 24:24) + 1))))))) << (0 ? 24:24))); -+ -+ /* Append RESTART. */ -+ buffer[0] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x9 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0))) | (((gctUINT32) ((gctUINT32) (FetchCount) & ((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0))) -+ | beginEndMark; -+ -+ buffer[1] -+ = FetchAddress; -+ } -+ -+ if (Bytes != gcvNULL) -+ { -+ /* Return number of bytes required by the RESTART command. */ -+ *Bytes = 8; -+ } -+ } -+ else -+ { -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_NOT_SUPPORTED; -+ } -+ -+ -+ gcmkFOOTER_NO(); -+ /* Success. */ -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckVGCOMMAND_FetchCommand -+** -+** Form a FETCH command at the specified location in the command buffer. -+** -+** INPUT: -+** -+** gckVGCOMMAND Command -+** Pointer to an gckVGCOMMAND object. -+** -+** gctPOINTER Logical -+** Pointer to the current location inside the command buffer to append -+** FETCH command at or gcvNULL to query the size of the command. -+** -+** gctUINT32 FetchAddress -+** The address of another command buffer to be executed by this FETCH -+** command. If 'Logical' is gcvNULL, this argument is ignored. -+** -+** gctUINT FetchCount -+** The number of 64-bit data quantities in another command buffer to -+** be executed by this FETCH command. If 'Logical' is gcvNULL, this -+** argument is ignored. -+** -+** gctSIZE_T * Bytes -+** Pointer to the number of bytes available for the FETCH command. -+** If 'Logical' is gcvNULL, the value from this argument is ignored. -+** -+** OUTPUT: -+** -+** gctSIZE_T * Bytes -+** Pointer to a variable that will receive the number of bytes required -+** for the FETCH command. If 'Bytes' is gcvNULL, nothing is returned. -+*/ -+gceSTATUS -+gckVGCOMMAND_FetchCommand( -+ IN gckVGCOMMAND Command, -+ IN gctPOINTER Logical, -+ IN gctUINT32 FetchAddress, -+ IN gctUINT FetchCount, -+ IN OUT gctUINT32 * Bytes -+ ) -+{ -+ gcmkHEADER_ARG("Command=0x%x Logical=0x%x FetchAddress=0x%x FetchCount=0x%x Bytes = 0x%x", -+ Command, Logical, FetchAddress, FetchCount, Bytes); -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND); -+ -+ if (Command->fe20) -+ { -+ if (Logical != gcvNULL) -+ { -+ gctUINT32_PTR buffer; -+ -+ /* Cast the buffer pointer. */ -+ buffer = (gctUINT32_PTR) Logical; -+ -+ /* Append FETCH. */ -+ buffer[0] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x5 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0))) | (((gctUINT32) ((gctUINT32) (FetchCount) & ((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0))); -+ -+ buffer[1] -+ = gcmkFIXADDRESS(FetchAddress); -+ } -+ -+ if (Bytes != gcvNULL) -+ { -+ /* Return number of bytes required by the FETCH command. */ -+ *Bytes = 8; -+ } -+ } -+ else -+ { -+ if (Logical != gcvNULL) -+ { -+ gctUINT32_PTR buffer; -+ -+ /* Cast the buffer pointer. */ -+ buffer = (gctUINT32_PTR) Logical; -+ -+ /* Append LINK. */ -+ buffer[0] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x08 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (FetchCount) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))); -+ -+ buffer[1] -+ = gcmkFIXADDRESS(FetchAddress); -+ } -+ -+ if (Bytes != gcvNULL) -+ { -+ /* Return number of bytes required by the LINK command. */ -+ *Bytes = 8; -+ } -+ } -+ -+ gcmkFOOTER_NO(); -+ /* Success. */ -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckVGCOMMAND_CallCommand -+** -+** Append a CALL command at the specified location in the command buffer. -+** -+** INPUT: -+** -+** gckVGCOMMAND Command -+** Pointer to an gckVGCOMMAND object. -+** -+** gctPOINTER Logical -+** Pointer to the current location inside the command buffer to append -+** CALL command at or gcvNULL to query the size of the command. -+** -+** gctUINT32 FetchAddress -+** The address of another command buffer to be executed by this CALL -+** command. If 'Logical' is gcvNULL, this argument is ignored. -+** -+** gctUINT FetchCount -+** The number of 64-bit data quantities in another command buffer to -+** be executed by this CALL command. If 'Logical' is gcvNULL, this -+** argument is ignored. -+** -+** gctSIZE_T * Bytes -+** Pointer to the number of bytes available for the CALL command. -+** If 'Logical' is gcvNULL, the value from this argument is ignored. -+** -+** OUTPUT: -+** -+** gctSIZE_T * Bytes -+** Pointer to a variable that will receive the number of bytes required -+** for the CALL command. If 'Bytes' is gcvNULL, nothing is returned. -+*/ -+gceSTATUS -+gckVGCOMMAND_CallCommand( -+ IN gckVGCOMMAND Command, -+ IN gctPOINTER Logical, -+ IN gctUINT32 FetchAddress, -+ IN gctUINT FetchCount, -+ IN OUT gctUINT32 * Bytes -+ ) -+{ -+ gcmkHEADER_ARG("Command=0x%x Logical=0x%x FetchAddress=0x%x FetchCount=0x%x Bytes = 0x%x", -+ Command, Logical, FetchAddress, FetchCount, Bytes); -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND); -+ -+ if (Command->fe20) -+ { -+ if (Logical != gcvNULL) -+ { -+ gctUINT32_PTR buffer; -+ -+ /* Cast the buffer pointer. */ -+ buffer = (gctUINT32_PTR) Logical; -+ -+ /* Append CALL. */ -+ buffer[0] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x6 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0))) | (((gctUINT32) ((gctUINT32) (FetchCount) & ((gctUINT32) ((((1 ? 20:0) - (0 ? 20:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:0) - (0 ? 20:0) + 1))))))) << (0 ? 20:0))); -+ -+ buffer[1] -+ = gcmkFIXADDRESS(FetchAddress); -+ } -+ -+ if (Bytes != gcvNULL) -+ { -+ /* Return number of bytes required by the CALL command. */ -+ *Bytes = 8; -+ } -+ } -+ else -+ { -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_NOT_SUPPORTED; -+ } -+ -+ gcmkFOOTER_NO(); -+ /* Success. */ -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckVGCOMMAND_ReturnCommand -+** -+** Append a RETURN command at the specified location in the command buffer. -+** -+** INPUT: -+** -+** gckVGCOMMAND Command -+** Pointer to an gckVGCOMMAND object. -+** -+** gctPOINTER Logical -+** Pointer to the current location inside the command buffer to append -+** RETURN command at or gcvNULL to query the size of the command. -+** -+** gctSIZE_T * Bytes -+** Pointer to the number of bytes available for the RETURN command. -+** If 'Logical' is gcvNULL, the value from this argument is ignored. -+** -+** OUTPUT: -+** -+** gctSIZE_T * Bytes -+** Pointer to a variable that will receive the number of bytes required -+** for the RETURN command. If 'Bytes' is gcvNULL, nothing is returned. -+*/ -+gceSTATUS -+gckVGCOMMAND_ReturnCommand( -+ IN gckVGCOMMAND Command, -+ IN gctPOINTER Logical, -+ IN OUT gctUINT32 * Bytes -+ ) -+{ -+ gcmkHEADER_ARG("Command=0x%x Logical=0x%x Bytes = 0x%x", -+ Command, Logical, Bytes); -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND); -+ -+ if (Command->fe20) -+ { -+ if (Logical != gcvNULL) -+ { -+ gctUINT32_PTR buffer; -+ -+ /* Cast the buffer pointer. */ -+ buffer = (gctUINT32_PTR) Logical; -+ -+ /* Append RETURN. */ -+ buffer[0] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x7 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))); -+ } -+ -+ if (Bytes != gcvNULL) -+ { -+ /* Return number of bytes required by the RETURN command. */ -+ *Bytes = 8; -+ } -+ } -+ else -+ { -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_NOT_SUPPORTED; -+ } -+ -+ gcmkFOOTER_NO(); -+ /* Success. */ -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckVGCOMMAND_EventCommand -+** -+** Form an EVENT command at the specified location in the command buffer. -+** -+** INPUT: -+** -+** gckVGCOMMAND Command -+** Pointer to the Command object. -+** -+** gctPOINTER Logical -+** Pointer to the current location inside the command buffer to append -+** EVENT command at or gcvNULL to query the size of the command. -+** -+** gctINT32 InterruptId -+** The ID of the interrupt to generate. -+** If 'Logical' is gcvNULL, this argument is ignored. -+** -+** gceBLOCK Block -+** Block that will generate the interrupt. -+** -+** gctSIZE_T * Bytes -+** Pointer to the number of bytes available for the EVENT command. -+** If 'Logical' is gcvNULL, the value from this argument is ignored. -+** -+** OUTPUT: -+** -+** gctSIZE_T * Bytes -+** Pointer to a variable that will receive the number of bytes required -+** for the END command. If 'Bytes' is gcvNULL, nothing is returned. -+*/ -+gceSTATUS -+gckVGCOMMAND_EventCommand( -+ IN gckVGCOMMAND Command, -+ IN gctPOINTER Logical, -+ IN gceBLOCK Block, -+ IN gctINT32 InterruptId, -+ IN OUT gctUINT32 * Bytes -+ ) -+{ -+ gcmkHEADER_ARG("Command=0x%x Logical=0x%x Block=0x%x InterruptId=0x%x Bytes = 0x%x", -+ Command, Logical, Block, InterruptId, Bytes); -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND); -+ -+ if (Command->fe20) -+ { -+ typedef struct _gcsEVENTSTATES -+ { -+ /* Chips before VG21 use these values. */ -+ gctUINT eventFromFE; -+ gctUINT eventFromPE; -+ -+ /* VG21 chips and later use SOURCE field. */ -+ gctUINT eventSource; -+ } -+ gcsEVENTSTATES; -+ -+ static gcsEVENTSTATES states[] = -+ { -+ /* gcvBLOCK_COMMAND */ -+ { -+ (gctUINT)~0, -+ (gctUINT)~0, -+ (gctUINT)~0 -+ }, -+ -+ /* gcvBLOCK_TESSELLATOR */ -+ { -+ 0x0, -+ 0x1, -+ 0x10 -+ }, -+ -+ /* gcvBLOCK_TESSELLATOR2 */ -+ { -+ 0x0, -+ 0x1, -+ 0x12 -+ }, -+ -+ /* gcvBLOCK_TESSELLATOR3 */ -+ { -+ 0x0, -+ 0x1, -+ 0x14 -+ }, -+ -+ /* gcvBLOCK_RASTER */ -+ { -+ 0x0, -+ 0x1, -+ 0x07, -+ }, -+ -+ /* gcvBLOCK_VG */ -+ { -+ 0x0, -+ 0x1, -+ 0x0F -+ }, -+ -+ /* gcvBLOCK_VG2 */ -+ { -+ 0x0, -+ 0x1, -+ 0x11 -+ }, -+ -+ /* gcvBLOCK_VG3 */ -+ { -+ 0x0, -+ 0x1, -+ 0x13 -+ }, -+ -+ /* gcvBLOCK_PIXEL */ -+ { -+ 0x0, -+ 0x1, -+ 0x07 -+ }, -+ }; -+ -+ /* Verify block ID. */ -+ gcmkVERIFY_ARGUMENT(gcmIS_VALID_INDEX(Block, states)); -+ -+ if (Logical != gcvNULL) -+ { -+ gctUINT32_PTR buffer; -+ -+ /* Verify the event ID. */ -+ gcmkVERIFY_ARGUMENT(InterruptId >= 0); -+ gcmkVERIFY_ARGUMENT(InterruptId <= ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1)))))); -+ -+ /* Cast the buffer pointer. */ -+ buffer = (gctUINT32_PTR) Logical; -+ -+ /* Append EVENT. */ -+ buffer[0] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x3 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 11:0) - (0 ? 11:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:0) - (0 ? 11:0) + 1))))))) << (0 ? 11:0))) | (((gctUINT32) ((gctUINT32) (0x0E01) & ((gctUINT32) ((((1 ? 11:0) - (0 ? 11:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:0) - (0 ? 11:0) + 1))))))) << (0 ? 11:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 27:16) - (0 ? 27:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:16) - (0 ? 27:16) + 1))))))) << (0 ? 27:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 27:16) - (0 ? 27:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 27:16) - (0 ? 27:16) + 1))))))) << (0 ? 27:16))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 13:12) - (0 ? 13:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:12) - (0 ? 13:12) + 1))))))) << (0 ? 13:12))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 13:12) - (0 ? 13:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:12) - (0 ? 13:12) + 1))))))) << (0 ? 13:12))); -+ -+ /* Determine chip version. */ -+ if (Command->vg21) -+ { -+ /* Get the event source for the block. */ -+ gctUINT eventSource = states[Block].eventSource; -+ -+ /* Supported? */ -+ if (eventSource == ~0) -+ { -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_NOT_SUPPORTED; -+ } -+ -+ buffer[1] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))) | (((gctUINT32) ((gctUINT32) (eventSource) & ((gctUINT32) ((((1 ? 12:8) - (0 ? 12:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:8) - (0 ? 12:8) + 1))))))) << (0 ? 12:8))); -+ } -+ else -+ { -+ /* Get the event source for the block. */ -+ gctUINT eventFromFE = states[Block].eventFromFE; -+ gctUINT eventFromPE = states[Block].eventFromPE; -+ -+ /* Supported? */ -+ if (eventFromFE == ~0) -+ { -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_NOT_SUPPORTED; -+ } -+ -+ buffer[1] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) ((gctUINT32) (eventFromFE) & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) ((gctUINT32) (eventFromPE) & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))); -+ } -+ } -+ -+ if (Bytes != gcvNULL) -+ { -+ /* Make sure the events are directly supported for the block. */ -+ if (states[Block].eventSource == ~0) -+ { -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_NOT_SUPPORTED; -+ } -+ -+ /* Return number of bytes required by the END command. */ -+ *Bytes = 8; -+ } -+ } -+ else -+ { -+ if (Logical != gcvNULL) -+ { -+ gctUINT32_PTR buffer; -+ -+ /* Verify the event ID. */ -+ gcmkVERIFY_ARGUMENT(InterruptId >= 0); -+ gcmkVERIFY_ARGUMENT(InterruptId <= ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1)))))); -+ -+ /* Cast the buffer pointer. */ -+ buffer = (gctUINT32_PTR) Logical; -+ -+ /* Append EVENT. */ -+ buffer[0] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E01) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))); -+ -+ /* Determine event source. */ -+ if (Block == gcvBLOCK_COMMAND) -+ { -+ buffer[1] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 5:5) - (0 ? 5:5) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 5:5) - (0 ? 5:5) + 1))))))) << (0 ? 5:5))); -+ } -+ else -+ { -+ buffer[1] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))); -+ } -+ } -+ -+ if (Bytes != gcvNULL) -+ { -+ /* Return number of bytes required by the EVENT and END commands. */ -+ *Bytes = 8; -+ } -+ } -+ -+ gcmkFOOTER_NO(); -+ /* Success. */ -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckVGCOMMAND_EndCommand -+** -+** Form an END command at the specified location in the command buffer. -+** -+** INPUT: -+** -+** gckVGCOMMAND Command -+** Pointer to the Command object. -+** -+** gctPOINTER Logical -+** Pointer to the current location inside the command buffer to append -+** END command at or gcvNULL to query the size of the command. -+** -+** gctINT32 InterruptId -+** The ID of the interrupt to generate. -+** If 'Logical' is gcvNULL, this argument will be ignored. -+** -+** gctSIZE_T * Bytes -+** Pointer to the number of bytes available for the END command. -+** If 'Logical' is gcvNULL, the value from this argument is ignored. -+** -+** OUTPUT: -+** -+** gctSIZE_T * Bytes -+** Pointer to a variable that will receive the number of bytes required -+** for the END command. If 'Bytes' is gcvNULL, nothing is returned. -+*/ -+gceSTATUS -+gckVGCOMMAND_EndCommand( -+ IN gckVGCOMMAND Command, -+ IN gctPOINTER Logical, -+ IN gctINT32 InterruptId, -+ IN OUT gctUINT32 * Bytes -+ ) -+{ -+ gcmkHEADER_ARG("Command=0x%x Logical=0x%x InterruptId=0x%x Bytes = 0x%x", -+ Command, Logical, InterruptId, Bytes); -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND); -+ -+ if (Command->fe20) -+ { -+ if (Logical != gcvNULL) -+ { -+ gctUINT32_PTR buffer; -+ -+ /* Verify the event ID. */ -+ gcmkVERIFY_ARGUMENT(InterruptId >= 0); -+ -+ /* Cast the buffer pointer. */ -+ buffer = (gctUINT32_PTR) Logical; -+ -+ /* Append END. */ -+ buffer[0] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 31:28) - (0 ? 31:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:28) - (0 ? 31:28) + 1))))))) << (0 ? 31:28))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))); -+ } -+ -+ if (Bytes != gcvNULL) -+ { -+ /* Return number of bytes required by the END command. */ -+ *Bytes = 8; -+ } -+ } -+ else -+ { -+ if (Logical != gcvNULL) -+ { -+ gctUINT32_PTR memory; -+ -+ /* Verify the event ID. */ -+ gcmkVERIFY_ARGUMENT(InterruptId >= 0); -+ -+ /* Cast the buffer pointer. */ -+ memory = (gctUINT32_PTR) Logical; -+ -+ /* Append EVENT. */ -+ memory[0] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E01) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))); -+ -+ memory[1] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) | (((gctUINT32) ((gctUINT32) (InterruptId) & ((gctUINT32) ((((1 ? 4:0) - (0 ? 4:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:0) - (0 ? 4:0) + 1))))))) << (0 ? 4:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 6:6) - (0 ? 6:6) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 6:6) - (0 ? 6:6) + 1))))))) << (0 ? 6:6))); -+ -+ /* Append END. */ -+ memory[2] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x02 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))); -+ } -+ -+ if (Bytes != gcvNULL) -+ { -+ /* Return number of bytes required by the EVENT and END commands. */ -+ *Bytes = 16; -+ } -+ } -+ -+ gcmkFOOTER_NO(); -+ /* Success. */ -+ return gcvSTATUS_OK; -+} -+ -+#endif /* gcdENABLE_VG */ -+ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/archvg/gc_hal_kernel_hardware_command_vg.h linux-4.1.13/drivers/gpu/galcore/archvg/gc_hal_kernel_hardware_command_vg.h ---- linux-4.1.13.orig/drivers/gpu/galcore/archvg/gc_hal_kernel_hardware_command_vg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/archvg/gc_hal_kernel_hardware_command_vg.h 2015-11-30 17:56:13.564138792 +0100 -@@ -0,0 +1,319 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#ifndef __gc_hal_kernel_hardware_command_vg_h_ -+#define __gc_hal_kernel_hardware_command_vg_h_ -+ -+/******************************************************************************\ -+******************* Task and Interrupt Management Structures. ****************** -+\******************************************************************************/ -+ -+/* Task storage header. */ -+typedef struct _gcsTASK_STORAGE * gcsTASK_STORAGE_PTR; -+typedef struct _gcsTASK_STORAGE -+{ -+ /* Next allocated storage buffer. */ -+ gcsTASK_STORAGE_PTR next; -+} -+gcsTASK_STORAGE; -+ -+/* Task container header. */ -+typedef struct _gcsTASK_CONTAINER * gcsTASK_CONTAINER_PTR; -+typedef struct _gcsTASK_CONTAINER -+{ -+ /* The number of tasks left to be processed in the container. */ -+ gctINT referenceCount; -+ -+ /* Size of the buffer. */ -+ gctUINT size; -+ -+ /* Link to the previous and the next allocated containers. */ -+ gcsTASK_CONTAINER_PTR allocPrev; -+ gcsTASK_CONTAINER_PTR allocNext; -+ -+ /* Link to the previous and the next containers in the free list. */ -+ gcsTASK_CONTAINER_PTR freePrev; -+ gcsTASK_CONTAINER_PTR freeNext; -+} -+gcsTASK_CONTAINER; -+ -+/* Kernel space task master table entry. */ -+typedef struct _gcsBLOCK_TASK_ENTRY * gcsBLOCK_TASK_ENTRY_PTR; -+typedef struct _gcsBLOCK_TASK_ENTRY -+{ -+ /* Pointer to the current task container for the block. */ -+ gcsTASK_CONTAINER_PTR container; -+ -+ /* Pointer to the current task data within the container. */ -+ gcsTASK_HEADER_PTR task; -+ -+ /* Pointer to the last link task within the container. */ -+ gcsTASK_LINK_PTR link; -+ -+ /* Number of interrupts allocated for this block. */ -+ gctUINT interruptCount; -+ -+ /* The index of the current interrupt. */ -+ gctUINT interruptIndex; -+ -+ /* Interrupt semaphore. */ -+ gctSEMAPHORE interruptSemaphore; -+ -+ /* Interrupt value array. */ -+ gctINT32 interruptArray[32]; -+} -+gcsBLOCK_TASK_ENTRY; -+ -+ -+/******************************************************************************\ -+********************* Command Queue Management Structures. ********************* -+\******************************************************************************/ -+ -+/* Command queue kernel element pointer. */ -+typedef struct _gcsKERNEL_CMDQUEUE * gcsKERNEL_CMDQUEUE_PTR; -+ -+/* Command queue object handler function type. */ -+typedef gceSTATUS (* gctOBJECT_HANDLER) ( -+ gckVGKERNEL Kernel, -+ gcsKERNEL_CMDQUEUE_PTR Entry -+ ); -+ -+/* Command queue kernel element. */ -+typedef struct _gcsKERNEL_CMDQUEUE -+{ -+ /* The number of buffers in the queue. */ -+ gcsCMDBUFFER_PTR commandBuffer; -+ -+ /* Pointer to the object handler function. */ -+ gctOBJECT_HANDLER handler; -+} -+gcsKERNEL_CMDQUEUE; -+ -+/* Command queue header. */ -+typedef struct _gcsKERNEL_QUEUE_HEADER * gcsKERNEL_QUEUE_HEADER_PTR; -+typedef struct _gcsKERNEL_QUEUE_HEADER -+{ -+ /* The size of the buffer in bytes. */ -+ gctUINT size; -+ -+ /* The number of pending entries to be processed. */ -+ volatile gctUINT pending; -+ -+ /* The current command queue entry. */ -+ gcsKERNEL_CMDQUEUE_PTR currentEntry; -+ -+ /* Next buffer. */ -+ gcsKERNEL_QUEUE_HEADER_PTR next; -+} -+gcsKERNEL_QUEUE_HEADER; -+ -+ -+/******************************************************************************\ -+******************************* gckVGCOMMAND Object ******************************* -+\******************************************************************************/ -+ -+/* gckVGCOMMAND object. */ -+struct _gckVGCOMMAND -+{ -+ /*************************************************************************** -+ ** Object data and pointers. -+ */ -+ -+ gcsOBJECT object; -+ gckVGKERNEL kernel; -+ gckOS os; -+ gckVGHARDWARE hardware; -+ -+ /* Features. */ -+ gctBOOL fe20; -+ gctBOOL vg20; -+ gctBOOL vg21; -+ -+ -+ /*************************************************************************** -+ ** Enable command queue dumping. -+ */ -+ -+ gctBOOL enableDumping; -+ -+ -+ /*************************************************************************** -+ ** Bus Error interrupt. -+ */ -+ -+ gctINT32 busErrorInt; -+ -+ -+ /*************************************************************************** -+ ** Command buffer information. -+ */ -+ -+ gcsCOMMAND_BUFFER_INFO info; -+ -+ -+ /*************************************************************************** -+ ** Synchronization objects. -+ */ -+ -+ gctPOINTER queueMutex; -+ gctPOINTER taskMutex; -+ gctPOINTER commitMutex; -+ -+ -+ /*************************************************************************** -+ ** Task management. -+ */ -+ -+ /* The head of the storage buffer linked list. */ -+ gcsTASK_STORAGE_PTR taskStorage; -+ -+ /* Allocation size. */ -+ gctUINT taskStorageGranularity; -+ gctUINT taskStorageUsable; -+ -+ /* The free container list. */ -+ gcsTASK_CONTAINER_PTR taskFreeHead; -+ gcsTASK_CONTAINER_PTR taskFreeTail; -+ -+ /* Task table */ -+ gcsBLOCK_TASK_ENTRY taskTable[gcvBLOCK_COUNT]; -+ -+ -+ /*************************************************************************** -+ ** Command queue. -+ */ -+ -+ /* Pointer to the allocated queue memory. */ -+ gcsKERNEL_QUEUE_HEADER_PTR queue; -+ -+ /* Pointer to the current available queue from which new queue entries -+ will be allocated. */ -+ gcsKERNEL_QUEUE_HEADER_PTR queueHead; -+ -+ /* If different from queueHead, points to the command queue which is -+ currently being executed by the hardware. */ -+ gcsKERNEL_QUEUE_HEADER_PTR queueTail; -+ -+ /* Points to the queue to merge the tail with when the tail is processed. */ -+ gcsKERNEL_QUEUE_HEADER_PTR mergeQueue; -+ -+ /* Queue overflow counter. */ -+ gctUINT queueOverflow; -+ -+ -+ /*************************************************************************** -+ ** Context. -+ */ -+ -+ /* Context counter used for unique ID. */ -+ gctUINT64 contextCounter; -+ -+ /* Current context ID. */ -+ gctUINT64 currentContext; -+ -+ /* Command queue power semaphore. */ -+ gctPOINTER powerSemaphore; -+ gctINT32 powerStallInt; -+ gcsCMDBUFFER_PTR powerStallBuffer; -+ gctSIGNAL powerStallSignal; -+ -+}; -+ -+/******************************************************************************\ -+************************ gckVGCOMMAND Object Internal API. *********************** -+\******************************************************************************/ -+ -+/* Initialize architecture dependent command buffer information. */ -+gceSTATUS -+gckVGCOMMAND_InitializeInfo( -+ IN gckVGCOMMAND Command -+ ); -+ -+/* Form a STATE command at the specified location in the command buffer. */ -+gceSTATUS -+gckVGCOMMAND_StateCommand( -+ IN gckVGCOMMAND Command, -+ IN gctUINT32 Pipe, -+ IN gctPOINTER Logical, -+ IN gctUINT32 Address, -+ IN gctUINT32 Count, -+ IN OUT gctUINT32 * Bytes -+ ); -+ -+/* Form a RESTART command at the specified location in the command buffer. */ -+gceSTATUS -+gckVGCOMMAND_RestartCommand( -+ IN gckVGCOMMAND Command, -+ IN gctPOINTER Logical, -+ IN gctUINT32 FetchAddress, -+ IN gctUINT FetchCount, -+ IN OUT gctUINT32 * Bytes -+ ); -+ -+/* Form a FETCH command at the specified location in the command buffer. */ -+gceSTATUS -+gckVGCOMMAND_FetchCommand( -+ IN gckVGCOMMAND Command, -+ IN gctPOINTER Logical, -+ IN gctUINT32 FetchAddress, -+ IN gctUINT FetchCount, -+ IN OUT gctUINT32 * Bytes -+ ); -+ -+/* Form a CALL command at the specified location in the command buffer. */ -+gceSTATUS -+gckVGCOMMAND_CallCommand( -+ IN gckVGCOMMAND Command, -+ IN gctPOINTER Logical, -+ IN gctUINT32 FetchAddress, -+ IN gctUINT FetchCount, -+ IN OUT gctUINT32 * Bytes -+ ); -+ -+/* Form a RETURN command at the specified location in the command buffer. */ -+gceSTATUS -+gckVGCOMMAND_ReturnCommand( -+ IN gckVGCOMMAND Command, -+ IN gctPOINTER Logical, -+ IN OUT gctUINT32 * Bytes -+ ); -+ -+/* Form an EVENT command at the specified location in the command buffer. */ -+gceSTATUS -+gckVGCOMMAND_EventCommand( -+ IN gckVGCOMMAND Command, -+ IN gctPOINTER Logical, -+ IN gceBLOCK Block, -+ IN gctINT32 InterruptId, -+ IN OUT gctUINT32 * Bytes -+ ); -+ -+/* Form an END command at the specified location in the command buffer. */ -+gceSTATUS -+gckVGCOMMAND_EndCommand( -+ IN gckVGCOMMAND Command, -+ IN gctPOINTER Logical, -+ IN gctINT32 InterruptId, -+ IN OUT gctUINT32 * Bytes -+ ); -+ -+#endif /* __gc_hal_kernel_hardware_command_h_ */ -+ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/archvg/gc_hal_kernel_hardware_vg.c linux-4.1.13/drivers/gpu/galcore/archvg/gc_hal_kernel_hardware_vg.c ---- linux-4.1.13.orig/drivers/gpu/galcore/archvg/gc_hal_kernel_hardware_vg.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/archvg/gc_hal_kernel_hardware_vg.c 2015-11-30 17:56:13.564138792 +0100 -@@ -0,0 +1,2119 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#include "gc_hal.h" -+#include "gc_hal_kernel.h" -+#include "gc_hal_kernel_hardware_command_vg.h" -+ -+#if gcdENABLE_VG -+ -+#define _GC_OBJ_ZONE gcvZONE_HARDWARE -+ -+typedef enum -+{ -+ gcvPOWER_FLAG_INITIALIZE = 1 << 0, -+ gcvPOWER_FLAG_STALL = 1 << 1, -+ gcvPOWER_FLAG_STOP = 1 << 2, -+ gcvPOWER_FLAG_START = 1 << 3, -+ gcvPOWER_FLAG_RELEASE = 1 << 4, -+ gcvPOWER_FLAG_DELAY = 1 << 5, -+ gcvPOWER_FLAG_SAVE = 1 << 6, -+ gcvPOWER_FLAG_ACQUIRE = 1 << 7, -+ gcvPOWER_FLAG_POWER_OFF = 1 << 8, -+ gcvPOWER_FLAG_CLOCK_OFF = 1 << 9, -+ gcvPOWER_FLAG_CLOCK_ON = 1 << 10, -+ gcvPOWER_FLAG_NOP = 1 << 11, -+} -+gcePOWER_FLAGS; -+ -+/******************************************************************************\ -+********************************* Support Code ********************************* -+\******************************************************************************/ -+static gceSTATUS -+_ResetGPU( -+ IN gckOS Os -+ ) -+{ -+ gctUINT32 control, idle; -+ gceSTATUS status; -+ -+ /* Read register. */ -+ gcmkONERROR(gckOS_ReadRegisterEx(Os, -+ gcvCORE_VG, -+ 0x00000, -+ &control)); -+ -+ for (;;) -+ { -+ /* Disable clock gating. */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Os, -+ gcvCORE_VG, -+ 0x00104, -+ 0x00000000)); -+ -+ /* Wait for clock being stable. */ -+ gcmkONERROR(gckOS_Delay(Os, 1)); -+ -+ /* Isolate the GPU. */ -+ control = ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))); -+ -+ gcmkONERROR(gckOS_WriteRegisterEx(Os, -+ gcvCORE_VG, -+ 0x00000, -+ control)); -+ -+ /* Set soft reset. */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Os, -+ gcvCORE_VG, -+ 0x00000, -+ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))))); -+ -+ /* Wait for reset. */ -+ gcmkONERROR(gckOS_Delay(Os, 1)); -+ -+ /* Reset soft reset bit. */ -+ gcmkONERROR(gckOS_WriteRegisterEx(Os, -+ gcvCORE_VG, -+ 0x00000, -+ ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 12:12) - (0 ? 12:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 12:12) - (0 ? 12:12) + 1))))))) << (0 ? 12:12))))); -+ -+ /* Reset GPU isolation. */ -+ control = ((((gctUINT32) (control)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 19:19) - (0 ? 19:19) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 19:19) - (0 ? 19:19) + 1))))))) << (0 ? 19:19))); -+ -+ gcmkONERROR(gckOS_WriteRegisterEx(Os, -+ gcvCORE_VG, -+ 0x00000, -+ control)); -+ -+ /* Read idle register. */ -+ gcmkONERROR(gckOS_ReadRegisterEx(Os, -+ gcvCORE_VG, -+ 0x00004, -+ &idle)); -+ -+ if ((((((gctUINT32) (idle)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ) == 0) -+ { -+ continue; -+ } -+ -+ /* Read reset register. */ -+ gcmkONERROR(gckOS_ReadRegisterEx(Os, -+ gcvCORE_VG, -+ 0x00000, -+ &control)); -+ -+ if (((((((gctUINT32) (control)) >> (0 ? 16:16)) & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1)))))) ) == 0) -+ || ((((((gctUINT32) (control)) >> (0 ? 17:17)) & ((gctUINT32) ((((1 ? 17:17) - (0 ? 17:17) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 17:17) - (0 ? 17:17) + 1)))))) ) == 0) -+ ) -+ { -+ continue; -+ } -+ -+ /* GPU is idle. */ -+ break; -+ } -+ -+ /* Success. */ -+ return gcvSTATUS_OK; -+ -+OnError: -+ -+ /* Return the error. */ -+ return status; -+} -+ -+ -+static gceSTATUS -+_IdentifyHardware( -+ IN gckOS Os, -+ OUT gceCHIPMODEL * ChipModel, -+ OUT gctUINT32 * ChipRevision, -+ OUT gctUINT32 * ChipFeatures, -+ OUT gctUINT32 * ChipMinorFeatures, -+ OUT gctUINT32 * ChipMinorFeatures2 -+ ) -+{ -+ gceSTATUS status; -+ gctUINT32 chipIdentity; -+ -+ do -+ { -+ /* Read chip identity register. */ -+ gcmkERR_BREAK(gckOS_ReadRegisterEx(Os, gcvCORE_VG, 0x00018, &chipIdentity)); -+ -+ /* Special case for older graphic cores. */ -+ if (((((gctUINT32) (chipIdentity)) >> (0 ? 31:24) & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1)))))) == (0x01 & ((gctUINT32) ((((1 ? 31:24) - (0 ? 31:24) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:24) - (0 ? 31:24) + 1)))))))) -+ { -+ *ChipModel = gcv500; -+ *ChipRevision = (((((gctUINT32) (chipIdentity)) >> (0 ? 15:12)) & ((gctUINT32) ((((1 ? 15:12) - (0 ? 15:12) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:12) - (0 ? 15:12) + 1)))))) ); -+ } -+ -+ else -+ { -+ /* Read chip identity register. */ -+ gcmkERR_BREAK(gckOS_ReadRegisterEx(Os, gcvCORE_VG, -+ 0x00020, -+ (gctUINT32 *) ChipModel)); -+ -+ /* Read CHIP_REV register. */ -+ gcmkERR_BREAK(gckOS_ReadRegisterEx(Os, gcvCORE_VG, -+ 0x00024, -+ ChipRevision)); -+ } -+ -+ /* Read chip feature register. */ -+ gcmkERR_BREAK(gckOS_ReadRegisterEx( -+ Os, gcvCORE_VG, 0x0001C, ChipFeatures -+ )); -+ -+ /* Read chip minor feature register. */ -+ gcmkERR_BREAK(gckOS_ReadRegisterEx( -+ Os, gcvCORE_VG, 0x00034, ChipMinorFeatures -+ )); -+ -+ /* Read chip minor feature register #2. */ -+ gcmkERR_BREAK(gckOS_ReadRegisterEx( -+ Os, gcvCORE_VG, 0x00074, ChipMinorFeatures2 -+ )); -+ -+ gcmkTRACE( -+ gcvLEVEL_VERBOSE, -+ "ChipModel=0x%08X\n" -+ "ChipRevision=0x%08X\n" -+ "ChipFeatures=0x%08X\n" -+ "ChipMinorFeatures=0x%08X\n" -+ "ChipMinorFeatures2=0x%08X\n", -+ *ChipModel, -+ *ChipRevision, -+ *ChipFeatures, -+ *ChipMinorFeatures, -+ *ChipMinorFeatures2 -+ ); -+ -+ /* Success. */ -+ return gcvSTATUS_OK; -+ } -+ while (gcvFALSE); -+ -+ /* Return the status. */ -+ return status; -+} -+ -+#if gcdPOWEROFF_TIMEOUT -+void -+_VGPowerTimerFunction( -+ gctPOINTER Data -+ ) -+{ -+ gckVGHARDWARE hardware = (gckVGHARDWARE)Data; -+ gcmkVERIFY_OK( -+ gckVGHARDWARE_SetPowerManagementState(hardware, gcvPOWER_OFF_TIMEOUT)); -+} -+#endif -+ -+/******************************************************************************\ -+****************************** gckVGHARDWARE API code ***************************** -+\******************************************************************************/ -+ -+/******************************************************************************* -+** -+** gckVGHARDWARE_Construct -+** -+** Construct a new gckVGHARDWARE object. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an initialized gckOS object. -+** -+** OUTPUT: -+** -+** gckVGHARDWARE * Hardware -+** Pointer to a variable that will hold the pointer to the gckVGHARDWARE -+** object. -+*/ -+gceSTATUS -+gckVGHARDWARE_Construct( -+ IN gckOS Os, -+ OUT gckVGHARDWARE * Hardware -+ ) -+{ -+ gckVGHARDWARE hardware = gcvNULL; -+ gceSTATUS status; -+ gceCHIPMODEL chipModel; -+ gctUINT32 chipRevision; -+ gctUINT32 chipFeatures; -+ gctUINT32 chipMinorFeatures; -+ gctUINT32 chipMinorFeatures2; -+ -+ gcmkHEADER_ARG("Os=0x%x Hardware=0x%x ", Os, Hardware); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Hardware != gcvNULL); -+ -+ do -+ { -+ gcmkERR_BREAK(gckOS_SetGPUPower(Os, gcvCORE_VG, gcvTRUE, gcvTRUE)); -+ -+ status = _ResetGPU(Os); -+ -+ if (status != gcvSTATUS_OK) -+ { -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "_ResetGPU failed: status=%d\n", status); -+ } -+ -+ /* Identify the hardware. */ -+ gcmkERR_BREAK(_IdentifyHardware(Os, -+ &chipModel, &chipRevision, -+ &chipFeatures, &chipMinorFeatures, &chipMinorFeatures2 -+ )); -+ -+ /* Allocate the gckVGHARDWARE object. */ -+ gcmkERR_BREAK(gckOS_Allocate(Os, -+ gcmSIZEOF(struct _gckVGHARDWARE), (gctPOINTER *) &hardware -+ )); -+ -+ /* Initialize the gckVGHARDWARE object. */ -+ hardware->object.type = gcvOBJ_HARDWARE; -+ hardware->os = Os; -+ -+ /* Set chip identity. */ -+ hardware->chipModel = chipModel; -+ hardware->chipRevision = chipRevision; -+ hardware->chipFeatures = chipFeatures; -+ hardware->chipMinorFeatures = chipMinorFeatures; -+ hardware->chipMinorFeatures2 = chipMinorFeatures2; -+ -+ hardware->powerMutex = gcvNULL; -+ hardware->chipPowerState = gcvPOWER_ON; -+ hardware->chipPowerStateGlobal = gcvPOWER_ON; -+ hardware->clockState = gcvTRUE; -+ hardware->powerState = gcvTRUE; -+ -+#if gcdPOWEROFF_TIMEOUT -+ hardware->powerOffTime = 0; -+ hardware->powerOffTimeout = gcdPOWEROFF_TIMEOUT; -+ -+ gcmkVERIFY_OK(gckOS_CreateTimer(Os, -+ _VGPowerTimerFunction, -+ (gctPOINTER)hardware, -+ &hardware->powerOffTimer)); -+#endif -+ -+ /* Determine whether FE 2.0 is present. */ -+ hardware->fe20 = ((((gctUINT32) (hardware->chipFeatures)) >> (0 ? 28:28) & ((gctUINT32) ((((1 ? 28:28) - (0 ? 28:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 28:28) - (0 ? 28:28) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 28:28) - (0 ? 28:28) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 28:28) - (0 ? 28:28) + 1))))))); -+ -+ /* Determine whether VG 2.0 is present. */ -+ hardware->vg20 = ((((gctUINT32) (hardware->chipMinorFeatures)) >> (0 ? 13:13) & ((gctUINT32) ((((1 ? 13:13) - (0 ? 13:13) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:13) - (0 ? 13:13) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 13:13) - (0 ? 13:13) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 13:13) - (0 ? 13:13) + 1))))))); -+ -+ /* Determine whether VG 2.1 is present. */ -+ hardware->vg21 = ((((gctUINT32) (hardware->chipMinorFeatures)) >> (0 ? 18:18) & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1)))))) == (0x1 & ((gctUINT32) ((((1 ? 18:18) - (0 ? 18:18) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 18:18) - (0 ? 18:18) + 1))))))); -+ -+ /* Set default event mask. */ -+ hardware->eventMask = 0xFFFFFFFF; -+ -+ gcmkERR_BREAK(gckOS_AtomConstruct(Os, &hardware->pageTableDirty)); -+ -+ /* Set fast clear to auto. */ -+ gcmkVERIFY_OK(gckVGHARDWARE_SetFastClear(hardware, -1)); -+ -+ gcmkERR_BREAK(gckOS_CreateMutex(Os, &hardware->powerMutex)); -+ -+ /* Enable power management by default. */ -+ hardware->powerManagement = gcvTRUE; -+ -+ /* Return pointer to the gckVGHARDWARE object. */ -+ *Hardware = hardware; -+ -+ gcmkFOOTER_NO(); -+ /* Success. */ -+ return gcvSTATUS_OK; -+ } -+ while (gcvFALSE); -+ -+#if gcdPOWEROFF_TIMEOUT -+ if (hardware->powerOffTimer != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckOS_StopTimer(Os, hardware->powerOffTimer)); -+ gcmkVERIFY_OK(gckOS_DestroyTimer(Os, hardware->powerOffTimer)); -+ } -+#endif -+ -+ gcmkVERIFY_OK(gckOS_SetGPUPower(Os, gcvCORE_VG, gcvFALSE, gcvFALSE)); -+ -+ if (hardware != gcvNULL && hardware->pageTableDirty != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckOS_AtomDestroy(Os, hardware->pageTableDirty)); -+ } -+ -+ if (hardware != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckOS_Free(Os, hardware)); -+ } -+ -+ gcmkFOOTER(); -+ /* Return the status. */ -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckVGHARDWARE_Destroy -+** -+** Destroy an gckVGHARDWARE object. -+** -+** INPUT: -+** -+** gckVGHARDWARE Hardware -+** Pointer to the gckVGHARDWARE object that needs to be destroyed. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckVGHARDWARE_Destroy( -+ IN gckVGHARDWARE Hardware -+ ) -+{ -+ gceSTATUS status; -+ gcmkHEADER_ARG("Hardware=0x%x ", Hardware); -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ /* Mark the object as unknown. */ -+ Hardware->object.type = gcvOBJ_UNKNOWN; -+ -+ if (Hardware->powerMutex != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckOS_DeleteMutex( -+ Hardware->os, Hardware->powerMutex)); -+ } -+ -+#if gcdPOWEROFF_TIMEOUT -+ gcmkVERIFY_OK(gckOS_StopTimer(Hardware->os, Hardware->powerOffTimer)); -+ gcmkVERIFY_OK(gckOS_DestroyTimer(Hardware->os, Hardware->powerOffTimer)); -+#endif -+ -+ if (Hardware->pageTableDirty != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckOS_AtomDestroy(Hardware->os, Hardware->pageTableDirty)); -+ } -+ -+ /* Free the object. */ -+ status = gckOS_Free(Hardware->os, Hardware); -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckVGHARDWARE_QueryMemory -+** -+** Query the amount of memory available on the hardware. -+** -+** INPUT: -+** -+** gckVGHARDWARE Hardware -+** Pointer to the gckVGHARDWARE object. -+** -+** OUTPUT: -+** -+** gctSIZE_T * InternalSize -+** Pointer to a variable that will hold the size of the internal video -+** memory in bytes. If 'InternalSize' is gcvNULL, no information of the -+** internal memory will be returned. -+** -+** gctUINT32 * InternalBaseAddress -+** Pointer to a variable that will hold the hardware's base address for -+** the internal video memory. This pointer cannot be gcvNULL if -+** 'InternalSize' is also non-gcvNULL. -+** -+** gctUINT32 * InternalAlignment -+** Pointer to a variable that will hold the hardware's base address for -+** the internal video memory. This pointer cannot be gcvNULL if -+** 'InternalSize' is also non-gcvNULL. -+** -+** gctSIZE_T * ExternalSize -+** Pointer to a variable that will hold the size of the external video -+** memory in bytes. If 'ExternalSize' is gcvNULL, no information of the -+** external memory will be returned. -+** -+** gctUINT32 * ExternalBaseAddress -+** Pointer to a variable that will hold the hardware's base address for -+** the external video memory. This pointer cannot be gcvNULL if -+** 'ExternalSize' is also non-gcvNULL. -+** -+** gctUINT32 * ExternalAlignment -+** Pointer to a variable that will hold the hardware's base address for -+** the external video memory. This pointer cannot be gcvNULL if -+** 'ExternalSize' is also non-gcvNULL. -+** -+** gctUINT32 * HorizontalTileSize -+** Number of horizontal pixels per tile. If 'HorizontalTileSize' is -+** gcvNULL, no horizontal pixel per tile will be returned. -+** -+** gctUINT32 * VerticalTileSize -+** Number of vertical pixels per tile. If 'VerticalTileSize' is -+** gcvNULL, no vertical pixel per tile will be returned. -+*/ -+gceSTATUS -+gckVGHARDWARE_QueryMemory( -+ IN gckVGHARDWARE Hardware, -+ OUT gctSIZE_T * InternalSize, -+ OUT gctUINT32 * InternalBaseAddress, -+ OUT gctUINT32 * InternalAlignment, -+ OUT gctSIZE_T * ExternalSize, -+ OUT gctUINT32 * ExternalBaseAddress, -+ OUT gctUINT32 * ExternalAlignment, -+ OUT gctUINT32 * HorizontalTileSize, -+ OUT gctUINT32 * VerticalTileSize -+ ) -+{ -+ gcmkHEADER_ARG("Hardware=0x%x InternalSize=0x%x InternalBaseAddress=0x%x InternalAlignment=0x%x" -+ "ExternalSize=0x%x ExternalBaseAddress=0x%x ExternalAlignment=0x%x HorizontalTileSize=0x%x VerticalTileSize=0x%x", -+ Hardware, InternalSize, InternalBaseAddress, InternalAlignment, -+ ExternalSize, ExternalBaseAddress, ExternalAlignment, HorizontalTileSize, VerticalTileSize); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ if (InternalSize != gcvNULL) -+ { -+ /* No internal memory. */ -+ *InternalSize = 0; -+ } -+ -+ if (ExternalSize != gcvNULL) -+ { -+ /* No external memory. */ -+ *ExternalSize = 0; -+ } -+ -+ if (HorizontalTileSize != gcvNULL) -+ { -+ /* 4x4 tiles. */ -+ *HorizontalTileSize = 4; -+ } -+ -+ if (VerticalTileSize != gcvNULL) -+ { -+ /* 4x4 tiles. */ -+ *VerticalTileSize = 4; -+ } -+ -+ gcmkFOOTER_NO(); -+ /* Success. */ -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckVGHARDWARE_QueryChipIdentity -+** -+** Query the identity of the hardware. -+** -+** INPUT: -+** -+** gckVGHARDWARE Hardware -+** Pointer to the gckVGHARDWARE object. -+** -+** OUTPUT: -+** -+** gceCHIPMODEL * ChipModel -+** If 'ChipModel' is not gcvNULL, the variable it points to will -+** receive the model of the chip. -+** -+** gctUINT32 * ChipRevision -+** If 'ChipRevision' is not gcvNULL, the variable it points to will -+** receive the revision of the chip. -+** -+** gctUINT32 * ChipFeatures -+** If 'ChipFeatures' is not gcvNULL, the variable it points to will -+** receive the feature set of the chip. -+** -+** gctUINT32 * ChipMinorFeatures -+** If 'ChipMinorFeatures' is not gcvNULL, the variable it points to -+** will receive the minor feature set of the chip. -+** -+** gctUINT32 * ChipMinorFeatures2 -+** If 'ChipMinorFeatures2' is not gcvNULL, the variable it points to -+** will receive the minor feature set of the chip. -+** -+*/ -+gceSTATUS -+gckVGHARDWARE_QueryChipIdentity( -+ IN gckVGHARDWARE Hardware, -+ OUT gceCHIPMODEL * ChipModel, -+ OUT gctUINT32 * ChipRevision, -+ OUT gctUINT32* ChipFeatures, -+ OUT gctUINT32* ChipMinorFeatures, -+ OUT gctUINT32* ChipMinorFeatures2 -+ ) -+{ -+ gcmkHEADER_ARG("Hardware=0x%x ChipModel=0x%x ChipRevision=0x%x ChipFeatures = 0x%x ChipMinorFeatures = 0x%x ChipMinorFeatures2 = 0x%x", -+ Hardware, ChipModel, ChipRevision, ChipFeatures, ChipMinorFeatures, ChipMinorFeatures2); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ /* Return chip model. */ -+ if (ChipModel != gcvNULL) -+ { -+ *ChipModel = Hardware->chipModel; -+ } -+ -+ /* Return revision number. */ -+ if (ChipRevision != gcvNULL) -+ { -+ *ChipRevision = Hardware->chipRevision; -+ } -+ -+ /* Return feature set. */ -+ if (ChipFeatures != gcvNULL) -+ { -+ gctUINT32 features = Hardware->chipFeatures; -+ -+ if ((((((gctUINT32) (features)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) )) -+ { -+ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) ((gctUINT32) (Hardware->allowFastClear) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))); -+ } -+ -+ /* Mark 2D pipe as available for GC500.0 since it did not have this *\ -+ \* bit. */ -+ if ((Hardware->chipModel == gcv500) -+ && (Hardware->chipRevision == 0) -+ ) -+ { -+ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))); -+ } -+ -+ /* Mark 2D pipe as available for GC300 since it did not have this *\ -+ \* bit. */ -+ if (Hardware->chipModel == gcv300) -+ { -+ features = ((((gctUINT32) (features)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1))))))) << (0 ? 9:9))); -+ } -+ -+ *ChipFeatures = features; -+ } -+ -+ /* Return minor feature set. */ -+ if (ChipMinorFeatures != gcvNULL) -+ { -+ *ChipMinorFeatures = Hardware->chipMinorFeatures; -+ } -+ -+ /* Return minor feature set #2. */ -+ if (ChipMinorFeatures2 != gcvNULL) -+ { -+ *ChipMinorFeatures2 = Hardware->chipMinorFeatures2; -+ } -+ -+ gcmkFOOTER_NO(); -+ /* Success. */ -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckVGHARDWARE_ConvertFormat -+** -+** Convert an API format to hardware parameters. -+** -+** INPUT: -+** -+** gckVGHARDWARE Hardware -+** Pointer to the gckVGHARDWARE object. -+** -+** gceSURF_FORMAT Format -+** API format to convert. -+** -+** OUTPUT: -+** -+** gctUINT32 * BitsPerPixel -+** Pointer to a variable that will hold the number of bits per pixel. -+** -+** gctUINT32 * BytesPerTile -+** Pointer to a variable that will hold the number of bytes per tile. -+*/ -+gceSTATUS -+gckVGHARDWARE_ConvertFormat( -+ IN gckVGHARDWARE Hardware, -+ IN gceSURF_FORMAT Format, -+ OUT gctUINT32 * BitsPerPixel, -+ OUT gctUINT32 * BytesPerTile -+ ) -+{ -+ gctUINT32 bitsPerPixel; -+ gctUINT32 bytesPerTile; -+ -+ gcmkHEADER_ARG("Hardware=0x%x Format=0x%x BitsPerPixel=0x%x BytesPerTile = 0x%x", -+ Hardware, Format, BitsPerPixel, BytesPerTile); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ /* Dispatch on format. */ -+ switch (Format) -+ { -+ case gcvSURF_A1: -+ case gcvSURF_L1: -+ /* 1-bpp format. */ -+ bitsPerPixel = 1; -+ bytesPerTile = (1 * 4 * 4) / 8; -+ break; -+ -+ case gcvSURF_A4: -+ /* 4-bpp format. */ -+ bitsPerPixel = 4; -+ bytesPerTile = (4 * 4 * 4) / 8; -+ break; -+ -+ case gcvSURF_INDEX8: -+ case gcvSURF_A8: -+ case gcvSURF_L8: -+ /* 8-bpp format. */ -+ bitsPerPixel = 8; -+ bytesPerTile = (8 * 4 * 4) / 8; -+ break; -+ -+ case gcvSURF_YV12: -+ /* 12-bpp planar YUV formats. */ -+ bitsPerPixel = 12; -+ bytesPerTile = (12 * 4 * 4) / 8; -+ break; -+ -+ case gcvSURF_NV12: -+ /* 12-bpp planar YUV formats. */ -+ bitsPerPixel = 12; -+ bytesPerTile = (12 * 4 * 4) / 8; -+ break; -+ -+ /* 4444 variations. */ -+ case gcvSURF_X4R4G4B4: -+ case gcvSURF_A4R4G4B4: -+ case gcvSURF_R4G4B4X4: -+ case gcvSURF_R4G4B4A4: -+ case gcvSURF_B4G4R4X4: -+ case gcvSURF_B4G4R4A4: -+ case gcvSURF_X4B4G4R4: -+ case gcvSURF_A4B4G4R4: -+ -+ /* 1555 variations. */ -+ case gcvSURF_X1R5G5B5: -+ case gcvSURF_A1R5G5B5: -+ case gcvSURF_R5G5B5X1: -+ case gcvSURF_R5G5B5A1: -+ case gcvSURF_X1B5G5R5: -+ case gcvSURF_A1B5G5R5: -+ case gcvSURF_B5G5R5X1: -+ case gcvSURF_B5G5R5A1: -+ -+ /* 565 variations. */ -+ case gcvSURF_R5G6B5: -+ case gcvSURF_B5G6R5: -+ -+ case gcvSURF_A8L8: -+ case gcvSURF_YUY2: -+ case gcvSURF_UYVY: -+ case gcvSURF_D16: -+ /* 16-bpp format. */ -+ bitsPerPixel = 16; -+ bytesPerTile = (16 * 4 * 4) / 8; -+ break; -+ -+ case gcvSURF_X8R8G8B8: -+ case gcvSURF_A8R8G8B8: -+ case gcvSURF_X8B8G8R8: -+ case gcvSURF_A8B8G8R8: -+ case gcvSURF_R8G8B8X8: -+ case gcvSURF_R8G8B8A8: -+ case gcvSURF_B8G8R8X8: -+ case gcvSURF_B8G8R8A8: -+ case gcvSURF_D32: -+ /* 32-bpp format. */ -+ bitsPerPixel = 32; -+ bytesPerTile = (32 * 4 * 4) / 8; -+ break; -+ -+ case gcvSURF_D24S8: -+ /* 24-bpp format. */ -+ bitsPerPixel = 32; -+ bytesPerTile = (32 * 4 * 4) / 8; -+ break; -+ -+ case gcvSURF_DXT1: -+ case gcvSURF_ETC1: -+ bitsPerPixel = 4; -+ bytesPerTile = (4 * 4 * 4) / 8; -+ break; -+ -+ case gcvSURF_DXT2: -+ case gcvSURF_DXT3: -+ case gcvSURF_DXT4: -+ case gcvSURF_DXT5: -+ bitsPerPixel = 8; -+ bytesPerTile = (8 * 4 * 4) / 8; -+ break; -+ -+ default: -+ /* Invalid format. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_INVALID_ARGUMENT; -+ } -+ -+ /* Set the result. */ -+ if (BitsPerPixel != gcvNULL) -+ { -+ * BitsPerPixel = bitsPerPixel; -+ } -+ -+ if (BytesPerTile != gcvNULL) -+ { -+ * BytesPerTile = bytesPerTile; -+ } -+ -+ gcmkFOOTER_NO(); -+ /* Success. */ -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckVGHARDWARE_SplitMemory -+** -+** Split a hardware specific memory address into a pool and offset. -+** -+** INPUT: -+** -+** gckVGHARDWARE Hardware -+** Pointer to the gckVGHARDWARE object. -+** -+** gctUINT32 Address -+** Address in hardware specific format. -+** -+** OUTPUT: -+** -+** gcePOOL * Pool -+** Pointer to a variable that will hold the pool type for the address. -+** -+** gctUINT32 * Offset -+** Pointer to a variable that will hold the offset for the address. -+*/ -+gceSTATUS -+gckVGHARDWARE_SplitMemory( -+ IN gckVGHARDWARE Hardware, -+ IN gctUINT32 Address, -+ OUT gcePOOL * Pool, -+ OUT gctUINT32 * Offset -+ ) -+{ -+ gcmkHEADER_ARG("Hardware=0x%x Address=0x%x Pool=0x%x Offset = 0x%x", -+ Hardware, Address, Pool, Offset); -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ gcmkVERIFY_ARGUMENT(Pool != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Offset != gcvNULL); -+ -+ /* Dispatch on memory type. */ -+ switch ((((((gctUINT32) (Address)) >> (0 ? 1:0)) & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1)))))) )) -+ { -+ case 0x0: -+ /* System memory. */ -+ *Pool = gcvPOOL_SYSTEM; -+ break; -+ -+ case 0x2: -+ /* Virtual memory. */ -+ *Pool = gcvPOOL_VIRTUAL; -+ break; -+ -+ default: -+ /* Invalid memory type. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_INVALID_ARGUMENT; -+ } -+ -+ /* Return offset of address. */ -+ *Offset = ((((gctUINT32) (Address)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) ((gctUINT32) (0) & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))); -+ -+ gcmkFOOTER_NO(); -+ /* Success. */ -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckVGHARDWARE_Execute -+** -+** Kickstart the hardware's command processor with an initialized command -+** buffer. -+** -+** INPUT: -+** -+** gckVGHARDWARE Hardware -+** Pointer to the gckVGHARDWARE object. -+** -+** gctUINT32 Address -+** Address of the command buffer. -+** -+** gctSIZE_T Count -+** Number of command-sized data units to be executed. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckVGHARDWARE_Execute( -+ IN gckVGHARDWARE Hardware, -+ IN gctUINT32 Address, -+ IN gctUINT32 Count -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Hardware=0x%x Address=0x%x Count=0x%x", -+ Hardware, Address, Count); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ do -+ { -+ /* Enable all events. */ -+ gcmkERR_BREAK(gckOS_WriteRegisterEx( -+ Hardware->os, -+ gcvCORE_VG, -+ 0x00014, -+ Hardware->eventMask -+ )); -+ -+ if (Hardware->fe20) -+ { -+ /* Write address register. */ -+ gcmkERR_BREAK(gckOS_WriteRegisterEx( -+ Hardware->os, -+ gcvCORE_VG, -+ 0x00500, -+ gcmkFIXADDRESS(Address) -+ )); -+ -+ /* Write control register. */ -+ gcmkERR_BREAK(gckOS_WriteRegisterEx( -+ Hardware->os, -+ gcvCORE_VG, -+ 0x00504, -+ Count -+ )); -+ } -+ else -+ { -+ /* Write address register. */ -+ gcmkERR_BREAK(gckOS_WriteRegisterEx( -+ Hardware->os, -+ gcvCORE_VG, -+ 0x00654, -+ gcmkFIXADDRESS(Address) -+ )); -+ -+ /* Write control register. */ -+ gcmkERR_BREAK(gckOS_WriteRegisterEx( -+ Hardware->os, -+ gcvCORE_VG, -+ 0x00658, -+ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 16:16) - (0 ? 16:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 16:16) - (0 ? 16:16) + 1))))))) << (0 ? 16:16))) | -+ ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (Count) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) -+ )); -+ } -+ -+ /* Success. */ -+ gcmkFOOTER(); -+ return gcvSTATUS_OK; -+ } -+ while (gcvFALSE); -+ -+ -+ gcmkFOOTER(); -+ /* Return the status. */ -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckVGHARDWARE_AlignToTile -+** -+** Align the specified width and height to tile boundaries. -+** -+** INPUT: -+** -+** gckVGHARDWARE Hardware -+** Pointer to an gckVGHARDWARE object. -+** -+** gceSURF_TYPE Type -+** Type of alignment. -+** -+** gctUINT32 * Width -+** Pointer to the width to be aligned. If 'Width' is gcvNULL, no width -+** will be aligned. -+** -+** gctUINT32 * Height -+** Pointer to the height to be aligned. If 'Height' is gcvNULL, no height -+** will be aligned. -+** -+** OUTPUT: -+** -+** gctUINT32 * Width -+** Pointer to a variable that will receive the aligned width. -+** -+** gctUINT32 * Height -+** Pointer to a variable that will receive the aligned height. -+*/ -+gceSTATUS -+gckVGHARDWARE_AlignToTile( -+ IN gckVGHARDWARE Hardware, -+ IN gceSURF_TYPE Type, -+ IN OUT gctUINT32 * Width, -+ IN OUT gctUINT32 * Height -+ ) -+{ -+ gcmkHEADER_ARG("Hardware=0x%x Type=0x%x Width=0x%x Height=0x%x", -+ Hardware, Type, Width, Height); -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ if (Width != gcvNULL) -+ { -+ /* Align the width. */ -+ *Width = gcmALIGN(*Width, (Type == gcvSURF_TEXTURE) ? 4 : 16); -+ } -+ -+ if (Height != gcvNULL) -+ { -+ /* Special case for VG images. */ -+ if ((*Height == 0) && (Type == gcvSURF_IMAGE)) -+ { -+ *Height = 4; -+ } -+ else -+ { -+ /* Align the height. */ -+ *Height = gcmALIGN(*Height, 4); -+ } -+ } -+ -+ gcmkFOOTER_NO(); -+ /* Success. */ -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckVGHARDWARE_ConvertLogical -+** -+** Convert a logical system address into a hardware specific address. -+** -+** INPUT: -+** -+** gckVGHARDWARE Hardware -+** Pointer to an gckVGHARDWARE object. -+** -+** gctPOINTER Logical -+** Logical address to convert. -+** -+** gctBOOL InUserSpace -+** gcvTRUE if the memory in user space. -+** -+** gctUINT32* Address -+** Return hardware specific address. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckVGHARDWARE_ConvertLogical( -+ IN gckVGHARDWARE Hardware, -+ IN gctPOINTER Logical, -+ IN gctBOOL InUserSpace, -+ OUT gctUINT32 * Address -+ ) -+{ -+ gctUINT32 address; -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x InUserSpace=%d Address=0x%x", -+ Hardware, Logical, InUserSpace, Address); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ gcmkVERIFY_ARGUMENT(Logical != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Address != gcvNULL); -+ -+ do -+ { -+ /* Convert logical address into a physical address. */ -+ if (InUserSpace) -+ { -+ gcmkERR_BREAK(gckOS_UserLogicalToPhysical( -+ Hardware->os, Logical, &address -+ )); -+ } -+ else -+ { -+ gcmkERR_BREAK(gckOS_GetPhysicalAddress( -+ Hardware->os, Logical, &address -+ )); -+ } -+ -+ /* Return hardware specific address. */ -+ *Address = ((((gctUINT32) (address)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))); -+ -+ /* Success. */ -+ gcmkFOOTER(); -+ return gcvSTATUS_OK; -+ } -+ while (gcvFALSE); -+ -+ gcmkFOOTER(); -+ /* Return the status. */ -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckVGHARDWARE_QuerySystemMemory -+** -+** Query the command buffer alignment and number of reserved bytes. -+** -+** INPUT: -+** -+** gckVGHARDWARE Harwdare -+** Pointer to an gckVGHARDWARE object. -+** -+** OUTPUT: -+** -+** gctSIZE_T * SystemSize -+** Pointer to a variable that receives the maximum size of the system -+** memory. -+** -+** gctUINT32 * SystemBaseAddress -+** Poinetr to a variable that receives the base address for system -+** memory. -+*/ -+gceSTATUS gckVGHARDWARE_QuerySystemMemory( -+ IN gckVGHARDWARE Hardware, -+ OUT gctSIZE_T * SystemSize, -+ OUT gctUINT32 * SystemBaseAddress -+ ) -+{ -+ gcmkHEADER_ARG("Hardware=0x%x SystemSize=0x%x SystemBaseAddress=0x%x", -+ Hardware, SystemSize, SystemBaseAddress); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ if (SystemSize != gcvNULL) -+ { -+ /* Maximum system memory can be 2GB. */ -+ *SystemSize = (gctSIZE_T)(1 << 31); -+ } -+ -+ if (SystemBaseAddress != gcvNULL) -+ { -+ /* Set system memory base address. */ -+ *SystemBaseAddress = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) (0x0 & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))); -+ } -+ -+ gcmkFOOTER_NO(); -+ /* Success. */ -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckVGHARDWARE_SetMMU -+** -+** Set the page table base address. -+** -+** INPUT: -+** -+** gckVGHARDWARE Harwdare -+** Pointer to an gckVGHARDWARE object. -+** -+** gctPOINTER Logical -+** Logical address of the page table. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS gckVGHARDWARE_SetMMU( -+ IN gckVGHARDWARE Hardware, -+ IN gctPOINTER Logical -+ ) -+{ -+ gceSTATUS status; -+ gctUINT32 address = 0; -+ -+ gcmkHEADER_ARG("Hardware=0x%x Logical=0x%x", -+ Hardware, Logical); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ gcmkVERIFY_ARGUMENT(Logical != gcvNULL); -+ -+ do -+ { -+ /* Convert the logical address into an hardware address. */ -+ gcmkERR_BREAK(gckVGHARDWARE_ConvertLogical(Hardware, Logical, -+ gcvFALSE, &address)); -+ -+ /* Write the AQMemoryFePageTable register. */ -+ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG, -+ 0x00400, -+ gcmkFIXADDRESS(address))); -+ -+ /* Write the AQMemoryTxPageTable register. */ -+ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG, -+ 0x00404, -+ gcmkFIXADDRESS(address))); -+ -+ /* Write the AQMemoryPePageTable register. */ -+ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG, -+ 0x00408, -+ gcmkFIXADDRESS(address))); -+ -+ /* Write the AQMemoryPezPageTable register. */ -+ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG, -+ 0x0040C, -+ gcmkFIXADDRESS(address))); -+ -+ /* Write the AQMemoryRaPageTable register. */ -+ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG, -+ 0x00410, -+ gcmkFIXADDRESS(address))); -+ } -+ while (gcvFALSE); -+ -+ gcmkFOOTER(); -+ /* Return the status. */ -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckVGHARDWARE_FlushMMU -+** -+** Flush the page table. -+** -+** INPUT: -+** -+** gckVGHARDWARE Harwdare -+** Pointer to an gckVGHARDWARE object. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS gckVGHARDWARE_FlushMMU( -+ IN gckVGHARDWARE Hardware -+ ) -+{ -+ gceSTATUS status; -+ gckVGCOMMAND command; -+ -+ gcmkHEADER_ARG("Hardware=0x%x ", Hardware); -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ do -+ { -+ gcsCMDBUFFER_PTR commandBuffer; -+ gctUINT32_PTR buffer; -+ -+ /* Create a shortcut to the command buffer object. */ -+ command = Hardware->kernel->command; -+ -+ /* Allocate command buffer space. */ -+ gcmkERR_BREAK(gckVGCOMMAND_Allocate( -+ command, 8, &commandBuffer, (gctPOINTER *) &buffer -+ )); -+ -+ buffer[0] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) | (((gctUINT32) (0x01 & ((gctUINT32) ((((1 ? 31:27) - (0 ? 31:27) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 31:27) - (0 ? 31:27) + 1))))))) << (0 ? 31:27))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) | (((gctUINT32) ((gctUINT32) (0x0E04) & ((gctUINT32) ((((1 ? 15:0) - (0 ? 15:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 15:0) - (0 ? 15:0) + 1))))))) << (0 ? 15:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))) | (((gctUINT32) ((gctUINT32) (1) & ((gctUINT32) ((((1 ? 25:16) - (0 ? 25:16) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 25:16) - (0 ? 25:16) + 1))))))) << (0 ? 25:16))); -+ -+ buffer[1] -+ = ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1))))))) << (0 ? 0:0))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 1:1) - (0 ? 1:1) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:1) - (0 ? 1:1) + 1))))))) << (0 ? 1:1))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 2:2) - (0 ? 2:2) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 2:2) - (0 ? 2:2) + 1))))))) << (0 ? 2:2))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 3:3) - (0 ? 3:3) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 3:3) - (0 ? 3:3) + 1))))))) << (0 ? 3:3))) -+ | ((((gctUINT32) (0)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))) | (((gctUINT32) (0x1 & ((gctUINT32) ((((1 ? 4:4) - (0 ? 4:4) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 4:4) - (0 ? 4:4) + 1))))))) << (0 ? 4:4))); -+ } -+ while(gcvFALSE); -+ -+ gcmkFOOTER(); -+ /* Return the status. */ -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckVGHARDWARE_BuildVirtualAddress -+** -+** Build a virtual address. -+** -+** INPUT: -+** -+** gckVGHARDWARE Harwdare -+** Pointer to an gckVGHARDWARE object. -+** -+** gctUINT32 Index -+** Index into page table. -+** -+** gctUINT32 Offset -+** Offset into page. -+** -+** OUTPUT: -+** -+** gctUINT32 * Address -+** Pointer to a variable receiving te hardware address. -+*/ -+gceSTATUS gckVGHARDWARE_BuildVirtualAddress( -+ IN gckVGHARDWARE Hardware, -+ IN gctUINT32 Index, -+ IN gctUINT32 Offset, -+ OUT gctUINT32 * Address -+ ) -+{ -+ gctUINT32 address; -+ -+ gcmkHEADER_ARG("Hardware=0x%x Index=0x%x Offset=0x%x Address=0x%x", -+ Hardware, Index, Offset, Address); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ gcmkVERIFY_ARGUMENT(Address != gcvNULL); -+ -+ /* Build virtual address. */ -+ address = (Index << 12) | Offset; -+ -+ /* Set virtual type. */ -+ address = ((((gctUINT32) (address)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))) | (((gctUINT32) (0x2 & ((gctUINT32) ((((1 ? 1:0) - (0 ? 1:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 1:0) - (0 ? 1:0) + 1))))))) << (0 ? 1:0))); -+ -+ /* Set the result. */ -+ *Address = address; -+ -+ gcmkFOOTER_NO(); -+ /* Success. */ -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckVGHARDWARE_GetIdle( -+ IN gckVGHARDWARE Hardware, -+ OUT gctUINT32 * Data -+ ) -+{ -+ gceSTATUS status; -+ gcmkHEADER_ARG("Hardware=0x%x Data=0x%x", Hardware, Data); -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ gcmkVERIFY_ARGUMENT(Data != gcvNULL); -+ -+ /* Read register and return. */ -+ status = gckOS_ReadRegisterEx(Hardware->os, gcvCORE_VG, 0x00004, Data); -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckVGHARDWARE_SetFastClear( -+ IN gckVGHARDWARE Hardware, -+ IN gctINT Enable -+ ) -+{ -+ gctUINT32 debug; -+ gceSTATUS status; -+ -+ if (!(((((gctUINT32) (Hardware->chipFeatures)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) )) -+ { -+ return gcvSTATUS_OK; -+ } -+ -+ do -+ { -+ if (Enable == -1) -+ { -+ Enable = (Hardware->chipModel > gcv500) || -+ ((Hardware->chipModel == gcv500) && (Hardware->chipRevision >= 3)); -+ } -+ -+ gcmkERR_BREAK(gckOS_ReadRegisterEx(Hardware->os, gcvCORE_VG, -+ 0x00414, -+ &debug)); -+ -+ debug = ((((gctUINT32) (debug)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20))) | (((gctUINT32) ((gctUINT32) (Enable == 0) & ((gctUINT32) ((((1 ? 20:20) - (0 ? 20:20) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 20:20) - (0 ? 20:20) + 1))))))) << (0 ? 20:20))); -+ -+#ifdef AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION -+ debug = ((((gctUINT32) (debug)) & ~(((gctUINT32) (((gctUINT32) ((((1 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) - (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) + 1) == 32) ? ~0 : (~(~0 << ((1 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) - (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) + 1))))))) << (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION))) | (((gctUINT32) ((gctUINT32) (Enable == 0) & ((gctUINT32) ((((1 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) - (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) + 1) == 32) ? ~0 : (~(~0 << ((1 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) - (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION) + 1))))))) << (0 ? AQ_MEMORY_DEBUG_DISABLE_Z_COMPRESSION))); -+#endif -+ -+ gcmkERR_BREAK(gckOS_WriteRegisterEx(Hardware->os, gcvCORE_VG, -+ 0x00414, -+ debug)); -+ -+ Hardware->allowFastClear = Enable; -+ -+ status = gcvFALSE; -+ } -+ while (gcvFALSE); -+ -+ return status; -+} -+ -+gceSTATUS -+gckVGHARDWARE_ReadInterrupt( -+ IN gckVGHARDWARE Hardware, -+ OUT gctUINT32_PTR IDs -+ ) -+{ -+ gceSTATUS status; -+ gcmkHEADER_ARG("Hardware=0x%x IDs=0x%x", Hardware, IDs); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ gcmkVERIFY_ARGUMENT(IDs != gcvNULL); -+ -+ /* Read AQIntrAcknowledge register. */ -+ status = gckOS_ReadRegisterEx(Hardware->os, gcvCORE_VG, -+ 0x00010, -+ IDs); -+ gcmkFOOTER(); -+ return status; -+} -+ -+static gceSTATUS _CommandStall( -+ gckVGHARDWARE Hardware) -+{ -+ gceSTATUS status; -+ gckVGCOMMAND command; -+ -+ gcmkHEADER_ARG("Hardware=0x%x", Hardware); -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ do -+ { -+ gctUINT32_PTR buffer; -+ command = Hardware->kernel->command; -+ -+ /* Allocate command buffer space. */ -+ gcmkERR_BREAK(gckVGCOMMAND_Allocate( -+ command, 8, &command->powerStallBuffer, -+ (gctPOINTER *) &buffer -+ )); -+ -+ gcmkERR_BREAK(gckVGCOMMAND_EventCommand( -+ command, buffer, gcvBLOCK_PIXEL, -+ command->powerStallInt, gcvNULL)); -+ -+ gcmkERR_BREAK(gckVGCOMMAND_Execute( -+ command, -+ command->powerStallBuffer -+ )); -+ -+ /* Wait the signal. */ -+ gcmkERR_BREAK(gckOS_WaitSignal( -+ command->os, -+ command->powerStallSignal, -+ command->kernel->kernel->timeOut)); -+ -+ -+ } -+ while(gcvFALSE); -+ -+ gcmkFOOTER(); -+ /* Return the status. */ -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckHARDWARE_SetPowerManagementState -+** -+** Set GPU to a specified power state. -+** -+** INPUT: -+** -+** gckHARDWARE Harwdare -+** Pointer to an gckHARDWARE object. -+** -+** gceCHIPPOWERSTATE State -+** Power State. -+** -+*/ -+gceSTATUS -+gckVGHARDWARE_SetPowerManagementState( -+ IN gckVGHARDWARE Hardware, -+ IN gceCHIPPOWERSTATE State -+ ) -+{ -+ gceSTATUS status; -+ gckVGCOMMAND command = gcvNULL; -+ gckOS os; -+ gctUINT flag/*, clock*/; -+ -+ gctBOOL acquired = gcvFALSE; -+ gctBOOL stall = gcvTRUE; -+ gctBOOL commitMutex = gcvFALSE; -+ gctBOOL mutexAcquired = gcvFALSE; -+ -+#if gcdPOWEROFF_TIMEOUT -+ gctBOOL timeout = gcvFALSE; -+ gctBOOL isAfter = gcvFALSE; -+ gctUINT32 currentTime; -+#endif -+ -+ gctBOOL broadcast = gcvFALSE; -+ gctUINT32 process, thread; -+ gctBOOL global = gcvFALSE; -+ -+#if gcdENABLE_PROFILING -+ gctUINT64 time, freq, mutexTime, onTime, stallTime, stopTime, delayTime, -+ initTime, offTime, startTime, totalTime; -+#endif -+ -+ /* State transition flags. */ -+ static const gctUINT flags[4][4] = -+ { -+ /* gcvPOWER_ON */ -+ { /* ON */ 0, -+ /* OFF */ gcvPOWER_FLAG_ACQUIRE | -+ gcvPOWER_FLAG_STALL | -+ gcvPOWER_FLAG_STOP | -+ gcvPOWER_FLAG_POWER_OFF | -+ gcvPOWER_FLAG_CLOCK_OFF, -+ /* IDLE */ gcvPOWER_FLAG_NOP, -+ /* SUSPEND */ gcvPOWER_FLAG_ACQUIRE | -+ gcvPOWER_FLAG_STALL | -+ gcvPOWER_FLAG_STOP | -+ gcvPOWER_FLAG_CLOCK_OFF, -+ }, -+ -+ /* gcvPOWER_OFF */ -+ { /* ON */ gcvPOWER_FLAG_INITIALIZE | -+ gcvPOWER_FLAG_START | -+ gcvPOWER_FLAG_RELEASE | -+ gcvPOWER_FLAG_DELAY, -+ /* OFF */ 0, -+ /* IDLE */ gcvPOWER_FLAG_INITIALIZE | -+ gcvPOWER_FLAG_START | -+ gcvPOWER_FLAG_RELEASE | -+ gcvPOWER_FLAG_DELAY, -+ /* SUSPEND */ gcvPOWER_FLAG_INITIALIZE | -+ gcvPOWER_FLAG_CLOCK_OFF, -+ }, -+ -+ /* gcvPOWER_IDLE */ -+ { /* ON */ gcvPOWER_FLAG_NOP, -+ /* OFF */ gcvPOWER_FLAG_ACQUIRE | -+ gcvPOWER_FLAG_STOP | -+ gcvPOWER_FLAG_POWER_OFF | -+ gcvPOWER_FLAG_CLOCK_OFF, -+ /* IDLE */ 0, -+ /* SUSPEND */ gcvPOWER_FLAG_ACQUIRE | -+ gcvPOWER_FLAG_STOP | -+ gcvPOWER_FLAG_CLOCK_OFF, -+ }, -+ -+ /* gcvPOWER_SUSPEND */ -+ { /* ON */ gcvPOWER_FLAG_START | -+ gcvPOWER_FLAG_RELEASE | -+ gcvPOWER_FLAG_DELAY | -+ gcvPOWER_FLAG_CLOCK_ON, -+ /* OFF */ gcvPOWER_FLAG_SAVE | -+ gcvPOWER_FLAG_POWER_OFF | -+ gcvPOWER_FLAG_CLOCK_OFF, -+ /* IDLE */ gcvPOWER_FLAG_START | -+ gcvPOWER_FLAG_DELAY | -+ gcvPOWER_FLAG_RELEASE | -+ gcvPOWER_FLAG_CLOCK_ON, -+ /* SUSPEND */ 0, -+ }, -+ }; -+ -+ gcmkHEADER_ARG("Hardware=0x%x State=%d", Hardware, State); -+#if gcmIS_DEBUG(gcdDEBUG_TRACE) -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "Switching to power state %d", -+ State); -+#endif -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ /* Get the gckOS object pointer. */ -+ os = Hardware->os; -+ gcmkVERIFY_OBJECT(os, gcvOBJ_OS); -+ -+ /* Get the gckCOMMAND object pointer. */ -+ gcmkVERIFY_OBJECT(Hardware->kernel, gcvOBJ_KERNEL); -+ command = Hardware->kernel->command; -+ gcmkVERIFY_OBJECT(command, gcvOBJ_COMMAND); -+ -+ if (Hardware->powerManagement == gcvFALSE) -+ { -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ } -+ -+ /* Start profiler. */ -+ gcmkPROFILE_INIT(freq, time); -+ -+ /* Convert the broadcast power state. */ -+ switch (State) -+ { -+ case gcvPOWER_SUSPEND_ATPOWERON: -+ /* Convert to SUSPEND and don't wait for STALL. */ -+ State = gcvPOWER_SUSPEND; -+ stall = gcvFALSE; -+ break; -+ -+ case gcvPOWER_OFF_ATPOWERON: -+ /* Convert to OFF and don't wait for STALL. */ -+ State = gcvPOWER_OFF; -+ stall = gcvFALSE; -+ break; -+ -+ case gcvPOWER_IDLE_BROADCAST: -+ /* Convert to IDLE and note we are inside broadcast. */ -+ State = gcvPOWER_IDLE; -+ broadcast = gcvTRUE; -+ break; -+ -+ case gcvPOWER_SUSPEND_BROADCAST: -+ /* Convert to SUSPEND and note we are inside broadcast. */ -+ State = gcvPOWER_SUSPEND; -+ broadcast = gcvTRUE; -+ break; -+ -+ case gcvPOWER_OFF_BROADCAST: -+ /* Convert to OFF and note we are inside broadcast. */ -+ State = gcvPOWER_OFF; -+ broadcast = gcvTRUE; -+ break; -+ -+ case gcvPOWER_OFF_RECOVERY: -+ /* Convert to OFF and note we are inside recovery. */ -+ State = gcvPOWER_OFF; -+ stall = gcvFALSE; -+ broadcast = gcvTRUE; -+ break; -+ -+ case gcvPOWER_ON_AUTO: -+ /* Convert to ON and note we are inside recovery. */ -+ State = gcvPOWER_ON; -+ break; -+ -+ case gcvPOWER_ON: -+ case gcvPOWER_IDLE: -+ case gcvPOWER_SUSPEND: -+ case gcvPOWER_OFF: -+ /* Mark as global power management. */ -+ global = gcvTRUE; -+ break; -+ -+#if gcdPOWEROFF_TIMEOUT -+ case gcvPOWER_OFF_TIMEOUT: -+ /* Convert to OFF and note we are inside broadcast. */ -+ State = gcvPOWER_OFF; -+ broadcast = gcvTRUE; -+ /* Check time out */ -+ timeout = gcvTRUE; -+ break; -+#endif -+ -+ default: -+ break; -+ } -+ -+ /* Get current process and thread IDs. */ -+ gcmkONERROR(gckOS_GetProcessID(&process)); -+ gcmkONERROR(gckOS_GetThreadID(&thread)); -+ -+ /* Acquire the power mutex. */ -+ if (broadcast) -+ { -+ /* Try to acquire the power mutex. */ -+ status = gckOS_AcquireMutex(os, Hardware->powerMutex, 1); -+ -+ if (status == gcvSTATUS_TIMEOUT) -+ { -+ /* Check if we already own this mutex. */ -+ if ((Hardware->powerProcess == process) -+ && (Hardware->powerThread == thread) -+ ) -+ { -+ /* Bail out on recursive power management. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ } -+ else if (State == gcvPOWER_IDLE) -+ { -+ /* gcvPOWER_IDLE_BROADCAST is from IST, -+ ** so waiting here will cause deadlock, -+ ** if lock holder call gckCOMMAND_Stall() */ -+ gcmkONERROR(gcvSTATUS_INVALID_REQUEST); -+ } -+ else -+ { -+ /* Acquire the power mutex. */ -+ gcmkONERROR(gckOS_AcquireMutex(os, -+ Hardware->powerMutex, -+ gcvINFINITE)); -+ } -+ } -+ } -+ else -+ { -+ /* Acquire the power mutex. */ -+ gcmkONERROR(gckOS_AcquireMutex(os, Hardware->powerMutex, gcvINFINITE)); -+ } -+ -+ /* Get time until mtuex acquired. */ -+ gcmkPROFILE_QUERY(time, mutexTime); -+ -+ Hardware->powerProcess = process; -+ Hardware->powerThread = thread; -+ mutexAcquired = gcvTRUE; -+ -+ /* Grab control flags and clock. */ -+ flag = flags[Hardware->chipPowerState][State]; -+ /*clock = clocks[State];*/ -+ -+#if gcdPOWEROFF_TIMEOUT -+ if (timeout) -+ { -+ gcmkONERROR(gckOS_GetTicks(¤tTime)); -+ -+ gcmkONERROR( -+ gckOS_TicksAfter(Hardware->powerOffTime, currentTime, &isAfter)); -+ -+ /* powerOffTime is pushed forward, give up.*/ -+ if (isAfter -+ /* Expect a transition start from IDLE. */ -+ || (Hardware->chipPowerState == gcvPOWER_ON) -+ || (Hardware->chipPowerState == gcvPOWER_OFF) -+ ) -+ { -+ /* Release the power mutex. */ -+ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex)); -+ -+ /* No need to do anything. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ } -+ } -+#endif -+ -+ if (flag == 0) -+ { -+ /* Release the power mutex. */ -+ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex)); -+ -+ /* No need to do anything. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ } -+ -+ /* internal power control */ -+ if (!global) -+ { -+ if (Hardware->chipPowerStateGlobal == gcvPOWER_OFF) -+ { -+ /* Release the power mutex. */ -+ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex)); -+ -+ /* No need to do anything. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ } -+ } -+ else -+ { -+ if (flag & gcvPOWER_FLAG_ACQUIRE) -+ { -+ /* Acquire the power management semaphore. */ -+ gcmkONERROR(gckOS_AcquireSemaphore(os, command->powerSemaphore)); -+ acquired = gcvTRUE; -+ -+ /* avoid acquiring again. */ -+ flag &= ~gcvPOWER_FLAG_ACQUIRE; -+ } -+ } -+ -+ if (flag & (gcvPOWER_FLAG_INITIALIZE | gcvPOWER_FLAG_CLOCK_ON)) -+ { -+ /* Turn on the power. */ -+ gcmkONERROR(gckOS_SetGPUPower(os, gcvCORE_VG, gcvTRUE, gcvTRUE)); -+ -+ /* Mark clock and power as enabled. */ -+ Hardware->clockState = gcvTRUE; -+ Hardware->powerState = gcvTRUE; -+ } -+ -+ /* Get time until powered on. */ -+ gcmkPROFILE_QUERY(time, onTime); -+ -+ if ((flag & gcvPOWER_FLAG_STALL) && stall) -+ { -+ /* Acquire the mutex. */ -+ gcmkONERROR(gckOS_AcquireMutex( -+ command->os, -+ command->commitMutex, -+ gcvINFINITE -+ )); -+ -+ commitMutex = gcvTRUE; -+ -+ gcmkONERROR(_CommandStall(Hardware)); -+ } -+ -+ /* Get time until stalled. */ -+ gcmkPROFILE_QUERY(time, stallTime); -+ -+ if (flag & gcvPOWER_FLAG_ACQUIRE) -+ { -+ /* Acquire the power management semaphore. */ -+ gcmkONERROR(gckOS_AcquireSemaphore(os, command->powerSemaphore)); -+ -+ acquired = gcvTRUE; -+ } -+ -+ -+ /* Get time until stopped. */ -+ gcmkPROFILE_QUERY(time, stopTime); -+ -+ -+ if (flag & gcvPOWER_FLAG_DELAY) -+ { -+ /* Wait for the specified amount of time to settle coming back from -+ ** power-off or suspend state. */ -+ gcmkONERROR(gckOS_Delay(os, gcdPOWER_CONTROL_DELAY)); -+ } -+ -+ /* Get time until delayed. */ -+ gcmkPROFILE_QUERY(time, delayTime); -+ -+ if (flag & gcvPOWER_FLAG_INITIALIZE) -+ { -+ -+ /* Initialize GPU here, replaced by InitializeHardware later */ -+ gcmkONERROR(gckVGHARDWARE_SetMMU(Hardware, Hardware->kernel->mmu->pageTableLogical)); -+ gcmkVERIFY_OK(gckVGHARDWARE_SetFastClear(Hardware, -1)); -+ -+ /* Force the command queue to reload the next context. */ -+ command->currentContext = 0; -+ } -+ -+ /* Get time until initialized. */ -+ gcmkPROFILE_QUERY(time, initTime); -+ -+ if (flag & (gcvPOWER_FLAG_POWER_OFF | gcvPOWER_FLAG_CLOCK_OFF)) -+ { -+ /* Turn off the GPU power. */ -+ gcmkONERROR( -+ gckOS_SetGPUPower(os, -+ gcvCORE_VG, -+ (flag & gcvPOWER_FLAG_CLOCK_OFF) ? gcvFALSE -+ : gcvTRUE, -+ (flag & gcvPOWER_FLAG_POWER_OFF) ? gcvFALSE -+ : gcvTRUE)); -+ -+ /* Save current hardware power and clock states. */ -+ Hardware->clockState = (flag & gcvPOWER_FLAG_CLOCK_OFF) ? gcvFALSE -+ : gcvTRUE; -+ Hardware->powerState = (flag & gcvPOWER_FLAG_POWER_OFF) ? gcvFALSE -+ : gcvTRUE; -+ } -+ -+ /* Get time until off. */ -+ gcmkPROFILE_QUERY(time, offTime); -+ -+ -+ /* Get time until started. */ -+ gcmkPROFILE_QUERY(time, startTime); -+ -+ if (flag & gcvPOWER_FLAG_RELEASE) -+ { -+ /* Release the power management semaphore. */ -+ gcmkONERROR(gckOS_ReleaseSemaphore(os, command->powerSemaphore)); -+ acquired = gcvFALSE; -+ } -+ -+ /* Save the new power state. */ -+ Hardware->chipPowerState = State; -+ -+ if (global) -+ { -+ /* Save the new power state. */ -+ Hardware->chipPowerStateGlobal = State; -+ } -+ -+ if (commitMutex) -+ { -+ /* Acquire the mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex( -+ command->os, -+ command->commitMutex -+ )); -+ } -+ -+#if gcdPOWEROFF_TIMEOUT -+ /* Reset power off time */ -+ gcmkONERROR(gckOS_GetTicks(¤tTime)); -+ -+ Hardware->powerOffTime = currentTime + Hardware->powerOffTimeout; -+ -+ if (State == gcvPOWER_IDLE) -+ { -+ /* Start a timer to power off GPU when GPU enters IDLE or SUSPEND. */ -+ gcmkVERIFY_OK(gckOS_StartTimer(os, -+ Hardware->powerOffTimer, -+ Hardware->powerOffTimeout)); -+ } -+ else -+ { -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, "Cancel powerOfftimer"); -+ -+ /* Cancel running timer when GPU enters ON or OFF. */ -+ gcmkVERIFY_OK(gckOS_StopTimer(os, Hardware->powerOffTimer)); -+ } -+#endif -+ -+ /* Release the power mutex. */ -+ gcmkONERROR(gckOS_ReleaseMutex(os, Hardware->powerMutex)); -+ -+ /* Get total time. */ -+ gcmkPROFILE_QUERY(time, totalTime); -+#if gcdENABLE_PROFILING -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ "PROF(%llu): mutex:%llu on:%llu stall:%llu stop:%llu", -+ freq, mutexTime, onTime, stallTime, stopTime); -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_HARDWARE, -+ " delay:%llu init:%llu off:%llu start:%llu total:%llu", -+ delayTime, initTime, offTime, startTime, totalTime); -+#endif -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ -+ if (acquired) -+ { -+ /* Release semaphore. */ -+ gcmkVERIFY_OK(gckOS_ReleaseSemaphore(Hardware->os, -+ command->powerSemaphore)); -+ } -+ -+ if (mutexAcquired) -+ { -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Hardware->os, Hardware->powerMutex)); -+ } -+ -+ if (commitMutex) -+ { -+ /* Acquire the mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex( -+ command->os, -+ command->commitMutex -+ )); -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckHARDWARE_QueryPowerManagementState -+** -+** Get GPU power state. -+** -+** INPUT: -+** -+** gckHARDWARE Harwdare -+** Pointer to an gckHARDWARE object. -+** -+** gceCHIPPOWERSTATE* State -+** Power State. -+** -+*/ -+gceSTATUS -+gckVGHARDWARE_QueryPowerManagementState( -+ IN gckVGHARDWARE Hardware, -+ OUT gceCHIPPOWERSTATE* State -+ ) -+{ -+ gcmkHEADER_ARG("Hardware=0x%x", Hardware); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ gcmkVERIFY_ARGUMENT(State != gcvNULL); -+ -+ /* Return the statue. */ -+ *State = Hardware->chipPowerState; -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*State=%d", *State); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckVGHARDWARE_SetPowerManagement -+** -+** Configure GPU power management function. -+** Only used in driver initialization stage. -+** -+** INPUT: -+** -+** gckVGHARDWARE Harwdare -+** Pointer to an gckHARDWARE object. -+** -+** gctBOOL PowerManagement -+** Power Mangement State. -+** -+*/ -+gceSTATUS -+gckVGHARDWARE_SetPowerManagement( -+ IN gckVGHARDWARE Hardware, -+ IN gctBOOL PowerManagement -+ ) -+{ -+ gcmkHEADER_ARG("Hardware=0x%x", Hardware); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ Hardware->powerManagement = PowerManagement; -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+#if gcdPOWEROFF_TIMEOUT -+gceSTATUS -+gckVGHARDWARE_SetPowerOffTimeout( -+ IN gckVGHARDWARE Hardware, -+ IN gctUINT32 Timeout -+ ) -+{ -+ gcmkHEADER_ARG("Hardware=0x%x Timeout=%d", Hardware, Timeout); -+ -+ Hardware->powerOffTimeout = Timeout; -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+ -+gceSTATUS -+gckVGHARDWARE_QueryPowerOffTimeout( -+ IN gckVGHARDWARE Hardware, -+ OUT gctUINT32* Timeout -+ ) -+{ -+ gcmkHEADER_ARG("Hardware=0x%x", Hardware); -+ -+ *Timeout = Hardware->powerOffTimeout; -+ -+ gcmkFOOTER_ARG("*Timeout=%d", *Timeout); -+ return gcvSTATUS_OK; -+} -+#endif -+ -+gceSTATUS -+gckVGHARDWARE_QueryIdle( -+ IN gckVGHARDWARE Hardware, -+ OUT gctBOOL_PTR IsIdle -+ ) -+{ -+ gceSTATUS status; -+ gctUINT32 idle; -+ -+ gcmkHEADER_ARG("Hardware=0x%x", Hardware); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ gcmkVERIFY_ARGUMENT(IsIdle != gcvNULL); -+ -+ /* We are idle when the power is not ON. */ -+ if (Hardware->chipPowerState != gcvPOWER_ON) -+ { -+ *IsIdle = gcvTRUE; -+ } -+ -+ else -+ { -+ /* Read idle register. */ -+ gcmkONERROR( -+ gckOS_ReadRegisterEx(Hardware->os, gcvCORE_VG, 0x00004, &idle)); -+ -+ /* Pipe must be idle. */ -+ if (((((((gctUINT32) (idle)) >> (0 ? 0:0)) & ((gctUINT32) ((((1 ? 0:0) - (0 ? 0:0) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 0:0) - (0 ? 0:0) + 1)))))) ) != 1) -+ || ((((((gctUINT32) (idle)) >> (0 ? 8:8)) & ((gctUINT32) ((((1 ? 8:8) - (0 ? 8:8) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 8:8) - (0 ? 8:8) + 1)))))) ) != 1) -+ || ((((((gctUINT32) (idle)) >> (0 ? 9:9)) & ((gctUINT32) ((((1 ? 9:9) - (0 ? 9:9) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 9:9) - (0 ? 9:9) + 1)))))) ) != 1) -+ || ((((((gctUINT32) (idle)) >> (0 ? 10:10)) & ((gctUINT32) ((((1 ? 10:10) - (0 ? 10:10) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 10:10) - (0 ? 10:10) + 1)))))) ) != 1) -+ || ((((((gctUINT32) (idle)) >> (0 ? 11:11)) & ((gctUINT32) ((((1 ? 11:11) - (0 ? 11:11) + 1) == 32) ? ~0 : (~(~0 << ((1 ? 11:11) - (0 ? 11:11) + 1)))))) ) != 1) -+ ) -+ { -+ /* Something is busy. */ -+ *IsIdle = gcvFALSE; -+ } -+ -+ else -+ { -+ *IsIdle = gcvTRUE; -+ } -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+#endif /* gcdENABLE_VG */ -+ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/archvg/gc_hal_kernel_hardware_vg.h linux-4.1.13/drivers/gpu/galcore/archvg/gc_hal_kernel_hardware_vg.h ---- linux-4.1.13.orig/drivers/gpu/galcore/archvg/gc_hal_kernel_hardware_vg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/archvg/gc_hal_kernel_hardware_vg.h 2015-11-30 17:56:13.564138792 +0100 -@@ -0,0 +1,74 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#ifndef __gc_hal_kernel_hardware_vg_h_ -+#define __gc_hal_kernel_hardware_vg_h_ -+ -+/* gckHARDWARE object. */ -+struct _gckVGHARDWARE -+{ -+ /* Object. */ -+ gcsOBJECT object; -+ -+ /* Pointer to gckKERNEL object. */ -+ gckVGKERNEL kernel; -+ -+ /* Pointer to gckOS object. */ -+ gckOS os; -+ -+ /* Chip characteristics. */ -+ gceCHIPMODEL chipModel; -+ gctUINT32 chipRevision; -+ gctUINT32 chipFeatures; -+ gctUINT32 chipMinorFeatures; -+ gctUINT32 chipMinorFeatures2; -+ gctBOOL allowFastClear; -+ -+ /* Features. */ -+ gctBOOL fe20; -+ gctBOOL vg20; -+ gctBOOL vg21; -+ -+ /* Event mask. */ -+ gctUINT32 eventMask; -+ -+ gctBOOL clockState; -+ gctBOOL powerState; -+ gctPOINTER powerMutex; -+ gctUINT32 powerProcess; -+ gctUINT32 powerThread; -+ gceCHIPPOWERSTATE chipPowerState; -+ gceCHIPPOWERSTATE chipPowerStateGlobal; -+ gctISRMANAGERFUNC startIsr; -+ gctISRMANAGERFUNC stopIsr; -+ gctPOINTER isrContext; -+ gctPOINTER pageTableDirty; -+#if gcdPOWEROFF_TIMEOUT -+ gctUINT32 powerOffTime; -+ gctUINT32 powerOffTimeout; -+ gctPOINTER powerOffTimer; -+#endif -+ -+ gctBOOL powerManagement; -+}; -+ -+#endif /* __gc_hal_kernel_hardware_h_ */ -+ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/config linux-4.1.13/drivers/gpu/galcore/config ---- linux-4.1.13.orig/drivers/gpu/galcore/config 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/config 2015-11-30 17:56:13.564138792 +0100 -@@ -0,0 +1,35 @@ -+############################################################################## -+# -+# Copyright (C) 2005 - 2014 by Vivante Corp. -+# -+# This program is free software; you can redistribute it and/or modify -+# it under the terms of the GNU General Public License as published by -+# the Free Software Foundation; either version 2 of the license, or -+# (at your option) any later version. -+# -+# This program is distributed in the hope that it will be useful, -+# but WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+# GNU General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with this program; if not write to the Free Software -+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+# -+############################################################################## -+ -+ -+ARCH_TYPE ?= arm -+SDK_DIR ?= $(AQROOT)/build/sdk -+VIVANTE_ENABLE_3D ?= 1 -+VIVANTE_ENABLE_2D ?= 1 -+VIVANTE_ENABLE_VG ?= 1 -+FORCE_ALL_VIDEO_MEMORY_CACHED ?= 0 -+NONPAGED_MEMORY_CACHEABLE ?= 0 -+NONPAGED_MEMORY_BUFFERABLE ?= 1 -+USE_BANK_ALIGNMENT ?= 1 -+BANK_BIT_START ?= 13 -+BANK_BIT_END ?= 15 -+BANK_CHANNEL_BIT ?= 12 -+PLATFORM ?= freescale/gc_hal_kernel_platform_imx6q14 -+DEBUG ?= 0 -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_allocator.c linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_allocator.c ---- linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_allocator.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_allocator.c 2015-11-30 17:56:13.564138792 +0100 -@@ -0,0 +1,884 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#include "gc_hal_kernel_linux.h" -+#include "gc_hal_kernel_allocator.h" -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "gc_hal_kernel_allocator_array.h" -+#include "gc_hal_kernel_platform.h" -+ -+#define _GC_OBJ_ZONE gcvZONE_OS -+ -+typedef struct _gcsDEFAULT_PRIV * gcsDEFAULT_PRIV_PTR; -+typedef struct _gcsDEFAULT_PRIV { -+ gctUINT32 low; -+ gctUINT32 high; -+} -+gcsDEFAULT_PRIV; -+ -+/******************************************************************************\ -+************************** Default Allocator Debugfs *************************** -+\******************************************************************************/ -+ -+int gc_usage_show(struct seq_file* m, void* data) -+{ -+ gcsINFO_NODE *node = m->private; -+ gckALLOCATOR Allocator = node->device; -+ gcsDEFAULT_PRIV_PTR priv = Allocator->privateData; -+ -+ seq_printf(m, "low: %u bytes\n", priv->low); -+ seq_printf(m, "high: %u bytes\n", priv->high); -+ -+ return 0; -+} -+ -+static gcsINFO InfoList[] = -+{ -+ {"lowHighUsage", gc_usage_show}, -+}; -+ -+static void -+_DefaultAllocatorDebugfsInit( -+ IN gckALLOCATOR Allocator, -+ IN gckDEBUGFS_DIR Root -+ ) -+{ -+ gcmkVERIFY_OK( -+ gckDEBUGFS_DIR_Init(&Allocator->debugfsDir, Root->root, "default")); -+ -+ gcmkVERIFY_OK(gckDEBUGFS_DIR_CreateFiles( -+ &Allocator->debugfsDir, -+ InfoList, -+ gcmCOUNTOF(InfoList), -+ Allocator -+ )); -+} -+ -+static void -+_DefaultAllocatorDebugfsCleanup( -+ IN gckALLOCATOR Allocator -+ ) -+{ -+ gcmkVERIFY_OK(gckDEBUGFS_DIR_RemoveFiles( -+ &Allocator->debugfsDir, -+ InfoList, -+ gcmCOUNTOF(InfoList) -+ )); -+ -+ gckDEBUGFS_DIR_Deinit(&Allocator->debugfsDir); -+} -+ -+ -+static void -+_NonContiguousFree( -+ IN struct page ** Pages, -+ IN gctUINT32 NumPages -+ ) -+{ -+ gctINT i; -+ -+ gcmkHEADER_ARG("Pages=0x%X, NumPages=%d", Pages, NumPages); -+ -+ gcmkASSERT(Pages != gcvNULL); -+ -+ for (i = 0; i < NumPages; i++) -+ { -+ __free_page(Pages[i]); -+ } -+ -+ if (is_vmalloc_addr(Pages)) -+ { -+ vfree(Pages); -+ } -+ else -+ { -+ kfree(Pages); -+ } -+ -+ gcmkFOOTER_NO(); -+} -+ -+static struct page ** -+_NonContiguousAlloc( -+ IN gctUINT32 NumPages -+ ) -+{ -+ struct page ** pages; -+ struct page *p; -+ gctINT i, size; -+ -+ gcmkHEADER_ARG("NumPages=%lu", NumPages); -+ -+ if (NumPages > totalram_pages) -+ { -+ gcmkFOOTER_NO(); -+ return gcvNULL; -+ } -+ -+ size = NumPages * sizeof(struct page *); -+ -+ pages = kmalloc(size, GFP_KERNEL | gcdNOWARN); -+ -+ if (!pages) -+ { -+ pages = vmalloc(size); -+ -+ if (!pages) -+ { -+ gcmkFOOTER_NO(); -+ return gcvNULL; -+ } -+ } -+ -+ for (i = 0; i < NumPages; i++) -+ { -+ p = alloc_page(GFP_KERNEL | __GFP_HIGHMEM | gcdNOWARN); -+ -+ if (!p) -+ { -+ _NonContiguousFree(pages, i); -+ gcmkFOOTER_NO(); -+ return gcvNULL; -+ } -+ -+ pages[i] = p; -+ } -+ -+ gcmkFOOTER_ARG("pages=0x%X", pages); -+ return pages; -+} -+ -+gctSTRING -+_CreateKernelVirtualMapping( -+ IN PLINUX_MDL Mdl -+ ) -+{ -+ gctSTRING addr = 0; -+ gctINT numPages = Mdl->numPages; -+ -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ if (Mdl->contiguous) -+ { -+ addr = page_address(Mdl->u.contiguousPages); -+ } -+ else -+ { -+ addr = vmap(Mdl->u.nonContiguousPages, -+ numPages, -+ 0, -+ PAGE_KERNEL); -+ -+ /* Trigger a page fault. */ -+ memset(addr, 0, numPages * PAGE_SIZE); -+ } -+#else -+ struct page ** pages; -+ gctBOOL free = gcvFALSE; -+ gctINT i; -+ -+ if (Mdl->contiguous) -+ { -+ pages = kmalloc(sizeof(struct page *) * numPages, GFP_KERNEL | gcdNOWARN); -+ -+ if (!pages) -+ { -+ return gcvNULL; -+ } -+ -+ for (i = 0; i < numPages; i++) -+ { -+ pages[i] = nth_page(Mdl->u.contiguousPages, i); -+ } -+ -+ free = gcvTRUE; -+ } -+ else -+ { -+ pages = Mdl->u.nonContiguousPages; -+ } -+ -+ /* ioremap() can't work on system memory since 2.6.38. */ -+ addr = vmap(pages, numPages, 0, gcmkNONPAGED_MEMROY_PROT(PAGE_KERNEL)); -+ -+ if (free) -+ { -+ kfree(pages); -+ } -+ -+#endif -+ -+ return addr; -+} -+ -+void -+_DestoryKernelVirtualMapping( -+ IN gctSTRING Addr -+ ) -+{ -+#if !gcdNONPAGED_MEMORY_CACHEABLE -+ vunmap(Addr); -+#endif -+} -+ -+void -+_UnmapUserLogical( -+ IN gctPOINTER Logical, -+ IN gctUINT32 Size -+) -+{ -+ if (unlikely(current->mm == gcvNULL)) -+ { -+ /* Do nothing if process is exiting. */ -+ return; -+ } -+ -+ if (vm_munmap((unsigned long)Logical, Size) < 0) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_WARNING, gcvZONE_OS, -+ "%s(%d): vm_munmap failed", -+ __FUNCTION__, __LINE__ -+ ); -+ } -+} -+ -+/***************************************************************************\ -+************************ Default Allocator ********************************** -+\***************************************************************************/ -+#define C_MAX_PAGENUM (50*1024) -+static gceSTATUS -+_DefaultAlloc( -+ IN gckALLOCATOR Allocator, -+ INOUT PLINUX_MDL Mdl, -+ IN gctSIZE_T NumPages, -+ IN gctUINT32 Flags -+ ) -+{ -+ gceSTATUS status; -+ gctUINT32 order; -+ gctSIZE_T bytes; -+ gctPOINTER addr = gcvNULL; -+ gctUINT32 numPages; -+ gctUINT i = 0; -+ gctBOOL contiguous = Flags & gcvALLOC_FLAG_CONTIGUOUS; -+ struct sysinfo temsysinfo; -+ gcsDEFAULT_PRIV_PTR priv = (gcsDEFAULT_PRIV_PTR)Allocator->privateData; -+ -+ gcmkHEADER_ARG("Mdl=%p NumPages=%d", Mdl, NumPages); -+ -+ numPages = NumPages; -+ bytes = NumPages * PAGE_SIZE; -+ order = get_order(bytes); -+ -+ si_meminfo(&temsysinfo); -+ -+ if (Flags & gcvALLOC_FLAG_MEMLIMIT) -+ { -+ if ( (temsysinfo.freeram < NumPages) || ((temsysinfo.freeram-NumPages) < C_MAX_PAGENUM) ) -+ { -+ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); -+ } -+ } -+ -+ if (contiguous) -+ { -+ if (order >= MAX_ORDER) -+ { -+ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); -+ } -+ -+ addr = -+ alloc_pages_exact(bytes, GFP_KERNEL | gcdNOWARN | __GFP_NORETRY); -+ -+ Mdl->u.contiguousPages = addr -+ ? virt_to_page(addr) -+ : gcvNULL; -+ -+ Mdl->exact = gcvTRUE; -+ -+ if (Mdl->u.contiguousPages == gcvNULL) -+ { -+ Mdl->u.contiguousPages = -+ alloc_pages(GFP_KERNEL | __GFP_HIGHMEM | gcdNOWARN, order); -+ -+ Mdl->exact = gcvFALSE; -+ } -+ } -+ else -+ { -+ Mdl->u.nonContiguousPages = _NonContiguousAlloc(numPages); -+ } -+ -+ if (Mdl->u.contiguousPages == gcvNULL && Mdl->u.nonContiguousPages == gcvNULL) -+ { -+ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); -+ } -+ -+ for (i = 0; i < numPages; i++) -+ { -+ struct page *page; -+ -+ if (contiguous) -+ { -+ page = nth_page(Mdl->u.contiguousPages, i); -+ } -+ else -+ { -+ page = _NonContiguousToPage(Mdl->u.nonContiguousPages, i); -+ } -+ -+ SetPageReserved(page); -+ -+ if (!PageHighMem(page) && page_to_phys(page)) -+ { -+ gcmkVERIFY_OK( -+ gckOS_CacheFlush(Allocator->os, _GetProcessID(), gcvNULL, -+ page_to_phys(page), -+ page_address(page), -+ PAGE_SIZE)); -+ -+ priv->low += PAGE_SIZE; -+ } -+ else -+ { -+ flush_dcache_page(page); -+ -+ priv->high += PAGE_SIZE; -+ } -+ } -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ gcmkFOOTER(); -+ return status; -+} -+ -+static void -+_DefaultFree( -+ IN gckALLOCATOR Allocator, -+ IN OUT PLINUX_MDL Mdl -+ ) -+{ -+ gctINT i; -+ struct page * page; -+ gcsDEFAULT_PRIV_PTR priv = (gcsDEFAULT_PRIV_PTR)Allocator->privateData; -+ -+ for (i = 0; i < Mdl->numPages; i++) -+ { -+ if (Mdl->contiguous) -+ { -+ page = nth_page(Mdl->u.contiguousPages, i); -+ } -+ else -+ { -+ page = _NonContiguousToPage(Mdl->u.nonContiguousPages, i); -+ } -+ -+ ClearPageReserved(page); -+ -+ if (PageHighMem(page)) -+ { -+ priv->high -= PAGE_SIZE; -+ } -+ else -+ { -+ priv->low -= PAGE_SIZE; -+ } -+ } -+ -+ if (Mdl->contiguous) -+ { -+ if (Mdl->exact == gcvTRUE) -+ { -+ free_pages_exact(page_address(Mdl->u.contiguousPages), Mdl->numPages * PAGE_SIZE); -+ } -+ else -+ { -+ __free_pages(Mdl->u.contiguousPages, get_order(Mdl->numPages * PAGE_SIZE)); -+ } -+ } -+ else -+ { -+ _NonContiguousFree(Mdl->u.nonContiguousPages, Mdl->numPages); -+ } -+} -+ -+gctINT -+_DefaultMapUser( -+ gckALLOCATOR Allocator, -+ PLINUX_MDL Mdl, -+ PLINUX_MDL_MAP MdlMap, -+ gctBOOL Cacheable -+ ) -+{ -+ -+ gctSTRING addr; -+ unsigned long start; -+ unsigned long pfn; -+ gctINT i; -+ gckOS os = Allocator->os; -+ gcsPLATFORM * platform = os->device->platform; -+ -+ PLINUX_MDL mdl = Mdl; -+ PLINUX_MDL_MAP mdlMap = MdlMap; -+ -+ gcmkHEADER_ARG("Allocator=%p Mdl=%p MdlMap=%p gctBOOL=%d", Allocator, Mdl, MdlMap, Cacheable); -+ -+ mdlMap->vmaAddr = (gctSTRING)vm_mmap(gcvNULL, -+ 0L, -+ mdl->numPages * PAGE_SIZE, -+ PROT_READ | PROT_WRITE, -+ MAP_SHARED, -+ 0); -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, gcvZONE_OS, -+ "%s(%d): vmaAddr->0x%X for phys_addr->0x%X", -+ __FUNCTION__, __LINE__, -+ (gctUINT32)(gctUINTPTR_T)mdlMap->vmaAddr, -+ (gctUINT32)(gctUINTPTR_T)mdl -+ ); -+ -+ if (IS_ERR(mdlMap->vmaAddr)) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, gcvZONE_OS, -+ "%s(%d): do_mmap_pgoff error", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ mdlMap->vmaAddr = gcvNULL; -+ -+ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY); -+ return gcvSTATUS_OUT_OF_MEMORY; -+ } -+ -+ down_write(¤t->mm->mmap_sem); -+ -+ mdlMap->vma = find_vma(current->mm, (unsigned long)mdlMap->vmaAddr); -+ -+ if (mdlMap->vma == gcvNULL) -+ { -+ up_write(¤t->mm->mmap_sem); -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, gcvZONE_OS, -+ "%s(%d): find_vma error", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ mdlMap->vmaAddr = gcvNULL; -+ -+ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_RESOURCES); -+ return gcvSTATUS_OUT_OF_RESOURCES; -+ } -+ -+ mdlMap->vma->vm_flags |= gcdVM_FLAGS; -+ -+ if (Cacheable == gcvFALSE) -+ { -+ /* Make this mapping non-cached. */ -+ mdlMap->vma->vm_page_prot = gcmkPAGED_MEMROY_PROT(mdlMap->vma->vm_page_prot); -+ } -+ -+ if (platform && platform->ops->adjustProt) -+ { -+ platform->ops->adjustProt(mdlMap->vma); -+ } -+ -+ addr = mdl->addr; -+ -+ /* Now map all the vmalloc pages to this user address. */ -+ if (mdl->contiguous) -+ { -+ /* map kernel memory to user space.. */ -+ if (remap_pfn_range(mdlMap->vma, -+ mdlMap->vma->vm_start, -+ page_to_pfn(mdl->u.contiguousPages), -+ mdlMap->vma->vm_end - mdlMap->vma->vm_start, -+ mdlMap->vma->vm_page_prot) < 0) -+ { -+ up_write(¤t->mm->mmap_sem); -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, gcvZONE_OS, -+ "%s(%d): unable to mmap ret", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ mdlMap->vmaAddr = gcvNULL; -+ -+ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY); -+ return gcvSTATUS_OUT_OF_MEMORY; -+ } -+ } -+ else -+ { -+ start = mdlMap->vma->vm_start; -+ -+ for (i = 0; i < mdl->numPages; i++) -+ { -+ pfn = _NonContiguousToPfn(mdl->u.nonContiguousPages, i); -+ -+ if (remap_pfn_range(mdlMap->vma, -+ start, -+ pfn, -+ PAGE_SIZE, -+ mdlMap->vma->vm_page_prot) < 0) -+ { -+ up_write(¤t->mm->mmap_sem); -+ -+ mdlMap->vmaAddr = gcvNULL; -+ -+ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY); -+ return gcvSTATUS_OUT_OF_MEMORY; -+ } -+ -+ start += PAGE_SIZE; -+ addr += PAGE_SIZE; -+ } -+ } -+ -+ up_write(¤t->mm->mmap_sem); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+void -+_DefaultUnmapUser( -+ IN gckALLOCATOR Allocator, -+ IN gctPOINTER Logical, -+ IN gctUINT32 Size -+ ) -+{ -+ _UnmapUserLogical(Logical, Size); -+} -+ -+gceSTATUS -+_DefaultMapKernel( -+ IN gckALLOCATOR Allocator, -+ IN PLINUX_MDL Mdl, -+ OUT gctPOINTER *Logical -+ ) -+{ -+ *Logical = _CreateKernelVirtualMapping(Mdl); -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+_DefaultUnmapKernel( -+ IN gckALLOCATOR Allocator, -+ IN PLINUX_MDL Mdl, -+ IN gctPOINTER Logical -+ ) -+{ -+ _DestoryKernelVirtualMapping(Logical); -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+_DefaultLogicalToPhysical( -+ IN gckALLOCATOR Allocator, -+ IN PLINUX_MDL Mdl, -+ IN gctPOINTER Logical, -+ IN gctUINT32 ProcessID, -+ OUT gctUINT32_PTR Physical -+ ) -+{ -+ return _ConvertLogical2Physical( -+ Allocator->os, Logical, ProcessID, Mdl, Physical); -+} -+ -+gceSTATUS -+_DefaultCache( -+ IN gckALLOCATOR Allocator, -+ IN PLINUX_MDL Mdl, -+ IN gctPOINTER Logical, -+ IN gctUINT32 Physical, -+ IN gctUINT32 Bytes, -+ IN gceCACHEOPERATION Operation -+ ) -+{ -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+_DefaultPhysical( -+ IN gckALLOCATOR Allocator, -+ IN PLINUX_MDL Mdl, -+ IN gctUINT32 Offset, -+ OUT gctUINT32_PTR Physical -+ ) -+{ -+ gcmkASSERT(Mdl->pagedMem && !Mdl->contiguous); -+ *Physical = _NonContiguousToPhys(Mdl->u.nonContiguousPages, Offset); -+ -+ return gcvSTATUS_OK; -+} -+ -+void -+_DefaultAllocatorDestructor( -+ IN void* PrivateData -+ ) -+{ -+ kfree(PrivateData); -+} -+ -+/* Default allocator operations. */ -+gcsALLOCATOR_OPERATIONS DefaultAllocatorOperations = { -+ .Alloc = _DefaultAlloc, -+ .Free = _DefaultFree, -+ .MapUser = _DefaultMapUser, -+ .UnmapUser = _DefaultUnmapUser, -+ .MapKernel = _DefaultMapKernel, -+ .UnmapKernel = _DefaultUnmapKernel, -+ .LogicalToPhysical = _DefaultLogicalToPhysical, -+ .Cache = _DefaultCache, -+ .Physical = _DefaultPhysical, -+}; -+ -+/* Default allocator entry. */ -+gceSTATUS -+_DefaultAlloctorInit( -+ IN gckOS Os, -+ OUT gckALLOCATOR * Allocator -+ ) -+{ -+ gceSTATUS status; -+ gckALLOCATOR allocator; -+ gcsDEFAULT_PRIV_PTR priv = gcvNULL; -+ -+ gcmkONERROR( -+ gckALLOCATOR_Construct(Os, &DefaultAllocatorOperations, &allocator)); -+ -+ priv = kzalloc(gcmSIZEOF(gcsDEFAULT_PRIV), GFP_KERNEL | gcdNOWARN); -+ -+ if (!priv) -+ { -+ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); -+ } -+ -+ /* Register private data. */ -+ allocator->privateData = priv; -+ allocator->privateDataDestructor = _DefaultAllocatorDestructor; -+ -+ allocator->debugfsInit = _DefaultAllocatorDebugfsInit; -+ allocator->debugfsCleanup = _DefaultAllocatorDebugfsCleanup; -+ -+ *Allocator = allocator; -+ -+ return gcvSTATUS_OK; -+ -+OnError: -+ return status; -+} -+ -+/***************************************************************************\ -+************************ Allocator helper *********************************** -+\***************************************************************************/ -+ -+gceSTATUS -+gckALLOCATOR_Construct( -+ IN gckOS Os, -+ IN gcsALLOCATOR_OPERATIONS * Operations, -+ OUT gckALLOCATOR * Allocator -+ ) -+{ -+ gceSTATUS status; -+ gckALLOCATOR allocator; -+ -+ gcmkHEADER_ARG("Os=%p, Operations=%p, Allocator=%p", -+ Os, Operations, Allocator); -+ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Allocator != gcvNULL); -+ gcmkVERIFY_ARGUMENT -+ ( Operations -+ && Operations->Alloc -+ && Operations->Free -+ && Operations->MapUser -+ && Operations->UnmapUser -+ && Operations->MapKernel -+ && Operations->UnmapKernel -+ && Operations->LogicalToPhysical -+ && Operations->Cache -+ && Operations->Physical -+ ); -+ -+ gcmkONERROR( -+ gckOS_Allocate(Os, gcmSIZEOF(gcsALLOCATOR), (gctPOINTER *)&allocator)); -+ -+ gckOS_ZeroMemory(allocator, gcmSIZEOF(gcsALLOCATOR)); -+ -+ /* Record os. */ -+ allocator->os = Os; -+ -+ /* Set operations. */ -+ allocator->ops = Operations; -+ -+ allocator->capability = gcvALLOC_FLAG_CONTIGUOUS -+ | gcvALLOC_FLAG_NON_CONTIGUOUS -+ | gcvALLOC_FLAG_CACHEABLE -+ | gcvALLOC_FLAG_MEMLIMIT; -+ ; -+ -+ *Allocator = allocator; -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************\ -+******************************** Debugfs Support ******************************* -+\******************************************************************************/ -+ -+static gceSTATUS -+_AllocatorDebugfsInit( -+ IN gckOS Os -+ ) -+{ -+ gceSTATUS status; -+ gckGALDEVICE device = Os->device; -+ -+ gckDEBUGFS_DIR dir = &Os->allocatorDebugfsDir; -+ -+ gcmkONERROR(gckDEBUGFS_DIR_Init(dir, device->debugfsDir.root, "allocators")); -+ -+ return gcvSTATUS_OK; -+ -+OnError: -+ return status; -+} -+ -+static void -+_AllocatorDebugfsCleanup( -+ IN gckOS Os -+ ) -+{ -+ gckDEBUGFS_DIR dir = &Os->allocatorDebugfsDir; -+ -+ gckDEBUGFS_DIR_Deinit(dir); -+} -+ -+/***************************************************************************\ -+************************ Allocator management ******************************* -+\***************************************************************************/ -+ -+gceSTATUS -+gckOS_ImportAllocators( -+ gckOS Os -+ ) -+{ -+ gceSTATUS status; -+ gctUINT i; -+ gckALLOCATOR allocator; -+ -+ _AllocatorDebugfsInit(Os); -+ -+ INIT_LIST_HEAD(&Os->allocatorList); -+ -+ for (i = 0; i < gcmCOUNTOF(allocatorArray); i++) -+ { -+ if (allocatorArray[i].construct) -+ { -+ /* Construct allocator. */ -+ status = allocatorArray[i].construct(Os, &allocator); -+ -+ if (gcmIS_ERROR(status)) -+ { -+ gcmkPRINT("["DEVICE_NAME"]: Can't construct allocator(%s)", -+ allocatorArray[i].name); -+ -+ continue; -+ } -+ -+ allocator->name = allocatorArray[i].name; -+ -+ if (allocator->debugfsInit) -+ { -+ /* Init allocator's debugfs. */ -+ allocator->debugfsInit(allocator, &Os->allocatorDebugfsDir); -+ } -+ -+ list_add_tail(&allocator->head, &Os->allocatorList); -+ } -+ } -+ -+#if DEBUG -+ list_for_each_entry(allocator, &Os->allocatorList, head) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_WARNING, gcvZONE_OS, -+ "%s(%d) Allocator: %s", -+ __FUNCTION__, __LINE__, -+ allocator->name -+ ); -+ } -+#endif -+ -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckOS_FreeAllocators( -+ gckOS Os -+ ) -+{ -+ gckALLOCATOR allocator; -+ gckALLOCATOR temp; -+ -+ list_for_each_entry_safe(allocator, temp, &Os->allocatorList, head) -+ { -+ list_del(&allocator->head); -+ -+ if (allocator->debugfsCleanup) -+ { -+ /* Clean up allocator's debugfs. */ -+ allocator->debugfsCleanup(allocator); -+ } -+ -+ /* Free private data. */ -+ if (allocator->privateDataDestructor && allocator->privateData) -+ { -+ allocator->privateDataDestructor(allocator->privateData); -+ } -+ -+ gckOS_Free(Os, allocator); -+ } -+ -+ _AllocatorDebugfsCleanup(Os); -+ -+ return gcvSTATUS_OK; -+} -+ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_allocator.h linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_allocator.h ---- linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_allocator.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_allocator.h 2015-11-30 17:56:13.564138792 +0100 -@@ -0,0 +1,400 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#ifndef __gc_hal_kernel_allocator_h_ -+#define __gc_hal_kernel_allocator_h_ -+ -+#include "gc_hal_kernel_linux.h" -+ -+typedef struct _gcsALLOCATOR * gckALLOCATOR; -+ -+typedef struct _gcsALLOCATOR_OPERATIONS -+{ -+ /************************************************************************** -+ ** -+ ** Alloc -+ ** -+ ** Allocte memory, request size is page aligned. -+ ** -+ ** INPUT: -+ ** -+ ** gckALLOCATOR Allocator -+ ** Pointer to an gckALLOCATOER object. -+ ** -+ ** PLINUX_Mdl -+ ** Pointer to Mdl whichs stores information -+ ** about allocated memory. -+ ** -+ ** gctSIZE_T NumPages -+ ** Number of pages need to allocate. -+ ** -+ ** gctUINT32 Flag -+ ** Allocation option. -+ ** -+ ** OUTPUT: -+ ** -+ ** Nothing. -+ ** -+ */ -+ gceSTATUS -+ (*Alloc)( -+ IN gckALLOCATOR Allocator, -+ IN PLINUX_MDL Mdl, -+ IN gctSIZE_T NumPages, -+ IN gctUINT32 Flag -+ ); -+ -+ /************************************************************************** -+ ** -+ ** Free -+ ** -+ ** Free memory. -+ ** -+ ** INPUT: -+ ** -+ ** gckALLOCATOR Allocator -+ ** Pointer to an gckALLOCATOER object. -+ ** -+ ** PLINUX_MDL Mdl -+ ** Mdl which stores information. -+ ** -+ ** OUTPUT: -+ ** -+ ** Nothing. -+ ** -+ */ -+ void -+ (*Free)( -+ IN gckALLOCATOR Allocator, -+ IN PLINUX_MDL Mdl -+ ); -+ -+ /************************************************************************** -+ ** -+ ** MapUser -+ ** -+ ** Map memory to user space. -+ ** -+ ** INPUT: -+ ** gckALLOCATOR Allocator -+ ** Pointer to an gckALLOCATOER object. -+ ** -+ ** PLINUX_MDL Mdl -+ ** Pointer to a Mdl. -+ ** -+ ** PLINUX_MDL_MAP MdlMap -+ ** Pointer to a MdlMap, mapped address is stored -+ ** in MdlMap->vmaAddr -+ ** -+ ** gctBOOL Cacheable -+ ** Whether this mapping is cacheable. -+ ** -+ ** OUTPUT: -+ ** -+ ** Nothing. -+ ** -+ */ -+ gctINT -+ (*MapUser)( -+ IN gckALLOCATOR Allocator, -+ IN PLINUX_MDL Mdl, -+ IN PLINUX_MDL_MAP MdlMap, -+ IN gctBOOL Cacheable -+ ); -+ -+ /************************************************************************** -+ ** -+ ** UnmapUser -+ ** -+ ** Unmap address from user address space. -+ ** -+ ** INPUT: -+ ** gckALLOCATOR Allocator -+ ** Pointer to an gckALLOCATOER object. -+ ** -+ ** gctPOINTER Logical -+ ** Address to be unmap -+ ** -+ ** gctUINT32 Size -+ ** Size of address space -+ ** -+ ** OUTPUT: -+ ** -+ ** Nothing. -+ ** -+ */ -+ void -+ (*UnmapUser)( -+ IN gckALLOCATOR Allocator, -+ IN gctPOINTER Logical, -+ IN gctUINT32 Size -+ ); -+ -+ /************************************************************************** -+ ** -+ ** MapKernel -+ ** -+ ** Map memory to kernel space. -+ ** -+ ** INPUT: -+ ** gckALLOCATOR Allocator -+ ** Pointer to an gckALLOCATOER object. -+ ** -+ ** PLINUX_MDL Mdl -+ ** Pointer to a Mdl object. -+ ** -+ ** OUTPUT: -+ ** gctPOINTER * Logical -+ ** Mapped kernel address. -+ */ -+ gceSTATUS -+ (*MapKernel)( -+ IN gckALLOCATOR Allocator, -+ IN PLINUX_MDL Mdl, -+ OUT gctPOINTER *Logical -+ ); -+ -+ /************************************************************************** -+ ** -+ ** UnmapKernel -+ ** -+ ** Unmap memory from kernel space. -+ ** -+ ** INPUT: -+ ** gckALLOCATOR Allocator -+ ** Pointer to an gckALLOCATOER object. -+ ** -+ ** PLINUX_MDL Mdl -+ ** Pointer to a Mdl object. -+ ** -+ ** gctPOINTER Logical -+ ** Mapped kernel address. -+ ** -+ ** OUTPUT: -+ ** -+ ** Nothing. -+ ** -+ */ -+ gceSTATUS -+ (*UnmapKernel)( -+ IN gckALLOCATOR Allocator, -+ IN PLINUX_MDL Mdl, -+ IN gctPOINTER Logical -+ ); -+ -+ /************************************************************************** -+ ** -+ ** LogicalToPhysical -+ ** -+ ** Get physical address from logical address, logical -+ ** address could be user virtual address or kernel -+ ** virtual address. -+ ** -+ ** INPUT: -+ ** gckALLOCATOR Allocator -+ ** Pointer to an gckALLOCATOER object. -+ ** -+ ** PLINUX_MDL Mdl -+ ** Pointer to a Mdl object. -+ ** -+ ** gctPOINTER Logical -+ ** Mapped kernel address. -+ ** -+ ** gctUINT32 ProcessID -+ ** pid of current process. -+ ** OUTPUT: -+ ** -+ ** gctUINT32_PTR Physical -+ ** Physical address. -+ ** -+ */ -+ gceSTATUS -+ (*LogicalToPhysical)( -+ IN gckALLOCATOR Allocator, -+ IN PLINUX_MDL Mdl, -+ IN gctPOINTER Logical, -+ IN gctUINT32 ProcessID, -+ OUT gctUINT32_PTR Physical -+ ); -+ -+ /************************************************************************** -+ ** -+ ** Cache -+ ** -+ ** Maintain cache coherency. -+ ** -+ ** INPUT: -+ ** gckALLOCATOR Allocator -+ ** Pointer to an gckALLOCATOER object. -+ ** -+ ** PLINUX_MDL Mdl -+ ** Pointer to a Mdl object. -+ ** -+ ** gctPOINTER Logical -+ ** Logical address, could be user address or kernel address -+ ** -+ ** gctUINT32_PTR Physical -+ ** Physical address. -+ ** -+ ** gctUINT32 Bytes -+ ** Size of memory region. -+ ** -+ ** gceCACHEOPERATION Opertaion -+ ** Cache operation. -+ ** -+ ** OUTPUT: -+ ** -+ ** Nothing. -+ ** -+ */ -+ gceSTATUS (*Cache)( -+ IN gckALLOCATOR Allocator, -+ IN PLINUX_MDL Mdl, -+ IN gctPOINTER Logical, -+ IN gctUINT32 Physical, -+ IN gctUINT32 Bytes, -+ IN gceCACHEOPERATION Operation -+ ); -+ -+ /************************************************************************** -+ ** -+ ** Physical -+ ** -+ ** Get physical address from a offset in memory region. -+ ** -+ ** INPUT: -+ ** gckALLOCATOR Allocator -+ ** Pointer to an gckALLOCATOER object. -+ ** -+ ** PLINUX_MDL Mdl -+ ** Pointer to a Mdl object. -+ ** -+ ** gctUINT32 Offset -+ ** Offset in this memory region. -+ ** -+ ** OUTPUT: -+ ** gctUINT32_PTR Physical -+ ** Physical address. -+ ** -+ */ -+ gceSTATUS (*Physical)( -+ IN gckALLOCATOR Allocator, -+ IN PLINUX_MDL Mdl, -+ IN gctUINT32 Offset, -+ OUT gctUINT32_PTR Physical -+ ); -+} -+gcsALLOCATOR_OPERATIONS; -+ -+typedef struct _gcsALLOCATOR -+{ -+ /* Pointer to gckOS Object. */ -+ gckOS os; -+ -+ /* Name. */ -+ gctSTRING name; -+ -+ /* Operations. */ -+ gcsALLOCATOR_OPERATIONS* ops; -+ -+ /* Capability of this allocator. */ -+ gctUINT32 capability; -+ -+ struct list_head head; -+ -+ /* Debugfs entry of this allocator. */ -+ gcsDEBUGFS_DIR debugfsDir; -+ -+ /* Init allocator debugfs. */ -+ void (*debugfsInit)(gckALLOCATOR, gckDEBUGFS_DIR); -+ -+ /* Cleanup allocator debugfs. */ -+ void (*debugfsCleanup)(gckALLOCATOR); -+ -+ /* Private data used by customer allocator. */ -+ void * privateData; -+ -+ /* Private data destructor. */ -+ void (*privateDataDestructor)(void *); -+} -+gcsALLOCATOR; -+ -+typedef struct _gcsALLOCATOR_DESC -+{ -+ /* Name of a allocator. */ -+ char * name; -+ -+ /* Entry function to construct a allocator. */ -+ gceSTATUS (*construct)(gckOS, gckALLOCATOR *); -+} -+gcsALLOCATOR_DESC; -+ -+/* -+* Helpers -+*/ -+ -+/* Fill a gcsALLOCATOR_DESC structure. */ -+#define gcmkDEFINE_ALLOCATOR_DESC(Name, Construct) \ -+ { \ -+ .name = Name, \ -+ .construct = Construct, \ -+ } -+ -+/* Construct a allocator. */ -+gceSTATUS -+gckALLOCATOR_Construct( -+ IN gckOS Os, -+ IN gcsALLOCATOR_OPERATIONS * Operations, -+ OUT gckALLOCATOR * Allocator -+ ); -+ -+/* -+ How to implement customer allocator -+ -+ Build in customer alloctor -+ -+ It is recommanded that customer allocator is implmented in independent -+ source file(s) which is specified by CUSOMTER_ALLOCATOR_OBJS in Kbuld. -+ -+ Register gcsALLOCATOR -+ -+ For each customer specified allocator, a desciption entry must be added -+ to allocatorArray defined in gc_hal_kernel_allocator_array.h. -+ -+ An entry in allocatorArray is a gcsALLOCATOR_DESC structure which describes -+ name and constructor of a gckALLOCATOR object. -+ -+ -+ Implement gcsALLOCATOR_DESC.init() -+ -+ In gcsALLOCATOR_DESC.init(), gckALLOCATOR_Construct should be called -+ to create a gckALLOCATOR object, customer specified private data can -+ be put in gcsALLOCATOR.privateData. -+ -+ -+ Implement gcsALLOCATOR_OPERATIONS -+ -+ When call gckALLOCATOR_Construct to create a gckALLOCATOR object, a -+ gcsALLOCATOR_OPERATIONS structure must be provided whose all members -+ implemented. -+ -+*/ -+#endif -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel.c linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel.c ---- linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel.c 2015-11-30 17:56:13.568138526 +0100 -@@ -0,0 +1,4244 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#include -+#include "gc_hal_kernel_precomp.h" -+ -+#define _GC_OBJ_ZONE gcvZONE_KERNEL -+ -+/******************************************************************************* -+***** Version Signature *******************************************************/ -+ -+#define _gcmTXT2STR(t) #t -+#define gcmTXT2STR(t) _gcmTXT2STR(t) -+const char * _VERSION = "\n\0$VERSION$" -+ gcmTXT2STR(gcvVERSION_MAJOR) "." -+ gcmTXT2STR(gcvVERSION_MINOR) "." -+ gcmTXT2STR(gcvVERSION_PATCH) ":" -+ gcmTXT2STR(gcvVERSION_BUILD) "$\n"; -+ -+/******************************************************************************\ -+******************************* gckKERNEL API Code ****************************** -+\******************************************************************************/ -+ -+#if gcmIS_DEBUG(gcdDEBUG_TRACE) -+#define gcmDEFINE2TEXT(d) #d -+gctCONST_STRING _DispatchText[] = -+{ -+ gcmDEFINE2TEXT(gcvHAL_QUERY_VIDEO_MEMORY), -+ gcmDEFINE2TEXT(gcvHAL_QUERY_CHIP_IDENTITY), -+ gcmDEFINE2TEXT(gcvHAL_ALLOCATE_NON_PAGED_MEMORY), -+ gcmDEFINE2TEXT(gcvHAL_FREE_NON_PAGED_MEMORY), -+ gcmDEFINE2TEXT(gcvHAL_ALLOCATE_CONTIGUOUS_MEMORY), -+ gcmDEFINE2TEXT(gcvHAL_FREE_CONTIGUOUS_MEMORY), -+ gcmDEFINE2TEXT(gcvHAL_ALLOCATE_VIDEO_MEMORY), -+ gcmDEFINE2TEXT(gcvHAL_ALLOCATE_LINEAR_VIDEO_MEMORY), -+ gcmDEFINE2TEXT(gcvHAL_RELEASE_VIDEO_MEMORY), -+ gcmDEFINE2TEXT(gcvHAL_MAP_MEMORY), -+ gcmDEFINE2TEXT(gcvHAL_UNMAP_MEMORY), -+ gcmDEFINE2TEXT(gcvHAL_MAP_USER_MEMORY), -+ gcmDEFINE2TEXT(gcvHAL_UNMAP_USER_MEMORY), -+ gcmDEFINE2TEXT(gcvHAL_LOCK_VIDEO_MEMORY), -+ gcmDEFINE2TEXT(gcvHAL_UNLOCK_VIDEO_MEMORY), -+ gcmDEFINE2TEXT(gcvHAL_EVENT_COMMIT), -+ gcmDEFINE2TEXT(gcvHAL_USER_SIGNAL), -+ gcmDEFINE2TEXT(gcvHAL_SIGNAL), -+ gcmDEFINE2TEXT(gcvHAL_WRITE_DATA), -+ gcmDEFINE2TEXT(gcvHAL_COMMIT), -+ gcmDEFINE2TEXT(gcvHAL_STALL), -+ gcmDEFINE2TEXT(gcvHAL_READ_REGISTER), -+ gcmDEFINE2TEXT(gcvHAL_WRITE_REGISTER), -+ gcmDEFINE2TEXT(gcvHAL_GET_PROFILE_SETTING), -+ gcmDEFINE2TEXT(gcvHAL_SET_PROFILE_SETTING), -+ gcmDEFINE2TEXT(gcvHAL_READ_ALL_PROFILE_REGISTERS), -+ gcmDEFINE2TEXT(gcvHAL_PROFILE_REGISTERS_2D), -+#if VIVANTE_PROFILER_PERDRAW -+ gcvHAL_READ_PROFILER_REGISTER_SETTING, -+#endif -+ gcmDEFINE2TEXT(gcvHAL_SET_POWER_MANAGEMENT_STATE), -+ gcmDEFINE2TEXT(gcvHAL_QUERY_POWER_MANAGEMENT_STATE), -+ gcmDEFINE2TEXT(gcvHAL_GET_BASE_ADDRESS), -+ gcmDEFINE2TEXT(gcvHAL_SET_IDLE), -+ gcmDEFINE2TEXT(gcvHAL_QUERY_KERNEL_SETTINGS), -+ gcmDEFINE2TEXT(gcvHAL_RESET), -+ gcmDEFINE2TEXT(gcvHAL_MAP_PHYSICAL), -+ gcmDEFINE2TEXT(gcvHAL_DEBUG), -+ gcmDEFINE2TEXT(gcvHAL_CACHE), -+ gcmDEFINE2TEXT(gcvHAL_TIMESTAMP), -+ gcmDEFINE2TEXT(gcvHAL_DATABASE), -+ gcmDEFINE2TEXT(gcvHAL_VERSION), -+ gcmDEFINE2TEXT(gcvHAL_CHIP_INFO), -+ gcmDEFINE2TEXT(gcvHAL_ATTACH), -+ gcmDEFINE2TEXT(gcvHAL_DETACH), -+ gcmDEFINE2TEXT(gcvHAL_COMPOSE), -+ gcmDEFINE2TEXT(gcvHAL_SET_TIMEOUT), -+ gcmDEFINE2TEXT(gcvHAL_GET_FRAME_INFO), -+ gcmDEFINE2TEXT(gcvHAL_QUERY_COMMAND_BUFFER), -+ gcmDEFINE2TEXT(gcvHAL_COMMIT_DONE), -+ gcmDEFINE2TEXT(gcvHAL_DUMP_GPU_STATE), -+ gcmDEFINE2TEXT(gcvHAL_DUMP_EVENT), -+ gcmDEFINE2TEXT(gcvHAL_ALLOCATE_VIRTUAL_COMMAND_BUFFER), -+ gcmDEFINE2TEXT(gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER), -+ gcmDEFINE2TEXT(gcvHAL_SET_FSCALE_VALUE), -+ gcmDEFINE2TEXT(gcvHAL_GET_FSCALE_VALUE), -+ gcmDEFINE2TEXT(gcvHAL_NAME_VIDEO_MEMORY), -+ gcmDEFINE2TEXT(gcvHAL_IMPORT_VIDEO_MEMORY), -+ gcmDEFINE2TEXT(gcvHAL_QUERY_RESET_TIME_STAMP), -+ gcmDEFINE2TEXT(gcvHAL_READ_REGISTER_EX), -+ gcmDEFINE2TEXT(gcvHAL_WRITE_REGISTER_EX), -+ gcmDEFINE2TEXT(gcvHAL_SYNC_POINT), -+ gcmDEFINE2TEXT(gcvHAL_CREATE_NATIVE_FENCE), -+ gcmDEFINE2TEXT(gcvHAL_DESTROY_MMU), -+ gcmDEFINE2TEXT(gcvHAL_SHBUF), -+}; -+#endif -+ -+#if gcdGPU_TIMEOUT && gcdINTERRUPT_STATISTIC -+void -+_MonitorTimerFunction( -+ gctPOINTER Data -+ ) -+{ -+ gckKERNEL kernel = (gckKERNEL)Data; -+ gctUINT32 pendingInterrupt; -+ gctBOOL reset = gcvFALSE; -+ gctUINT32 mask; -+ gctUINT32 advance = kernel->timeOut/2; -+ -+#if gcdENABLE_VG -+ if (kernel->core == gcvCORE_VG) -+ { -+ return; -+ } -+#endif -+ -+ if (kernel->monitorTimerStop) -+ { -+ /* Stop. */ -+ return; -+ } -+ -+ gckOS_AtomGet(kernel->os, kernel->eventObj->interruptCount, &pendingInterrupt); -+ -+ if (kernel->monitoring == gcvFALSE) -+ { -+ if (pendingInterrupt) -+ { -+ /* Begin to mointor GPU state. */ -+ kernel->monitoring = gcvTRUE; -+ -+ /* Record current state. */ -+ kernel->lastCommitStamp = kernel->eventObj->lastCommitStamp; -+ kernel->restoreAddress = kernel->hardware->lastWaitLink; -+ gcmkVERIFY_OK(gckOS_AtomGet( -+ kernel->os, -+ kernel->hardware->pendingEvent, -+ &kernel->restoreMask -+ )); -+ -+ /* Clear timeout. */ -+ kernel->timer = 0; -+ } -+ } -+ else -+ { -+ if (pendingInterrupt) -+ { -+ gcmkVERIFY_OK(gckOS_AtomGet( -+ kernel->os, -+ kernel->hardware->pendingEvent, -+ &mask -+ )); -+ -+ if (kernel->eventObj->lastCommitStamp == kernel->lastCommitStamp -+ && kernel->hardware->lastWaitLink == kernel->restoreAddress -+ && mask == kernel->restoreMask -+ ) -+ { -+ /* GPU state is not changed, accumlate timeout. */ -+ kernel->timer += advance; -+ -+ if (kernel->timer >= kernel->timeOut) -+ { -+ /* GPU stuck, trigger reset. */ -+ reset = gcvTRUE; -+ } -+ } -+ else -+ { -+ /* GPU state changed, cancel current timeout.*/ -+ kernel->monitoring = gcvFALSE; -+ } -+ } -+ else -+ { -+ /* GPU finish all jobs, cancel current timeout*/ -+ kernel->monitoring = gcvFALSE; -+ } -+ } -+ -+ if (reset) -+ { -+ gckKERNEL_Recovery(kernel); -+ -+ /* Work in this timeout is done. */ -+ kernel->monitoring = gcvFALSE; -+ } -+ -+ gcmkVERIFY_OK(gckOS_StartTimer(kernel->os, kernel->monitorTimer, advance)); -+} -+#endif -+ -+#if gcdPROCESS_ADDRESS_SPACE -+gceSTATUS -+_MapCommandBuffer( -+ IN gckKERNEL Kernel -+ ) -+{ -+ gceSTATUS status; -+ gctUINT32 i; -+ gctUINT32 physical; -+ gckMMU mmu; -+ -+ gcmkONERROR(gckKERNEL_GetProcessMMU(Kernel, &mmu)); -+ -+ for (i = 0; i < gcdCOMMAND_QUEUES; i++) -+ { -+ gcmkONERROR(gckOS_GetPhysicalAddress( -+ Kernel->os, -+ Kernel->command->queues[i].logical, -+ &physical -+ )); -+ -+ gcmkONERROR(gckMMU_FlatMapping(mmu, physical)); -+ } -+ -+ return gcvSTATUS_OK; -+ -+OnError: -+ return status; -+} -+#endif -+ -+void -+_DumpDriverConfigure( -+ IN gckKERNEL Kernel -+ ) -+{ -+ gcmkPRINT_N(0, "**************************\n"); -+ gcmkPRINT_N(0, "*** GPU DRV CONFIG ***\n"); -+ gcmkPRINT_N(0, "**************************\n"); -+ -+ gcmkPRINT("Galcore version %d.%d.%d.%d\n", -+ gcvVERSION_MAJOR, gcvVERSION_MINOR, gcvVERSION_PATCH, gcvVERSION_BUILD); -+ -+ gckOS_DumpParam(); -+} -+ -+void -+_DumpState( -+ IN gckKERNEL Kernel -+ ) -+{ -+ /* Dump GPU Debug registers. */ -+ gcmkVERIFY_OK(gckHARDWARE_DumpGPUState(Kernel->hardware)); -+ -+ if (Kernel->virtualCommandBuffer) -+ { -+ gcmkVERIFY_OK(gckCOMMAND_DumpExecutingBuffer(Kernel->command)); -+ } -+ -+ /* Dump Pending event. */ -+ gcmkVERIFY_OK(gckEVENT_Dump(Kernel->eventObj)); -+ -+ /* Dump Process DB. */ -+ gcmkVERIFY_OK(gckKERNEL_DumpProcessDB(Kernel)); -+ -+#if gcdRECORD_COMMAND -+ /* Dump record. */ -+ gckRECORDER_Dump(Kernel->command->recorder); -+#endif -+} -+ -+/******************************************************************************* -+** -+** gckKERNEL_Construct -+** -+** Construct a new gckKERNEL object. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gceCORE Core -+** Specified core. -+** -+** IN gctPOINTER Context -+** Pointer to a driver defined context. -+** -+** IN gckDB SharedDB, -+** Pointer to a shared DB. -+** -+** OUTPUT: -+** -+** gckKERNEL * Kernel -+** Pointer to a variable that will hold the pointer to the gckKERNEL -+** object. -+*/ -+ -+gceSTATUS -+gckKERNEL_Construct( -+ IN gckOS Os, -+ IN gceCORE Core, -+ IN gctPOINTER Context, -+ IN gckDB SharedDB, -+ OUT gckKERNEL * Kernel -+ ) -+{ -+ gckKERNEL kernel = gcvNULL; -+ gceSTATUS status; -+ gctSIZE_T i; -+ gctPOINTER pointer = gcvNULL; -+ -+ gcmkHEADER_ARG("Os=0x%x Context=0x%x", Os, Context); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Kernel != gcvNULL); -+ -+ /* Allocate the gckKERNEL object. */ -+ gcmkONERROR(gckOS_Allocate(Os, -+ gcmSIZEOF(struct _gckKERNEL), -+ &pointer)); -+ -+ kernel = pointer; -+ -+ /* Zero the object pointers. */ -+ kernel->hardware = gcvNULL; -+ kernel->command = gcvNULL; -+ kernel->eventObj = gcvNULL; -+ kernel->mmu = gcvNULL; -+#if gcdDVFS -+ kernel->dvfs = gcvNULL; -+#endif -+ kernel->monitorTimer = gcvNULL; -+ -+ /* Initialize the gckKERNEL object. */ -+ kernel->object.type = gcvOBJ_KERNEL; -+ kernel->os = Os; -+ kernel->core = Core; -+ -+ if (SharedDB == gcvNULL) -+ { -+ gcmkONERROR(gckOS_Allocate(Os, -+ gcmSIZEOF(struct _gckDB), -+ &pointer)); -+ -+ kernel->db = pointer; -+ kernel->dbCreated = gcvTRUE; -+ kernel->db->freeDatabase = gcvNULL; -+ kernel->db->freeRecord = gcvNULL; -+ kernel->db->dbMutex = gcvNULL; -+ kernel->db->lastDatabase = gcvNULL; -+ kernel->db->idleTime = 0; -+ kernel->db->lastIdle = 0; -+ kernel->db->lastSlowdown = 0; -+ -+ for (i = 0; i < gcmCOUNTOF(kernel->db->db); ++i) -+ { -+ kernel->db->db[i] = gcvNULL; -+ } -+ -+ /* Construct a database mutex. */ -+ gcmkONERROR(gckOS_CreateMutex(Os, &kernel->db->dbMutex)); -+ -+ /* Construct a video memory name database. */ -+ gcmkONERROR(gckKERNEL_CreateIntegerDatabase(kernel, &kernel->db->nameDatabase)); -+ -+ /* Construct a video memory name database mutex. */ -+ gcmkONERROR(gckOS_CreateMutex(Os, &kernel->db->nameDatabaseMutex)); -+ -+ /* Construct a pointer name database. */ -+ gcmkONERROR(gckKERNEL_CreateIntegerDatabase(kernel, &kernel->db->pointerDatabase)); -+ -+ /* Construct a pointer name database mutex. */ -+ gcmkONERROR(gckOS_CreateMutex(Os, &kernel->db->pointerDatabaseMutex)); -+ } -+ else -+ { -+ kernel->db = SharedDB; -+ kernel->dbCreated = gcvFALSE; -+ } -+ -+ for (i = 0; i < gcmCOUNTOF(kernel->timers); ++i) -+ { -+ kernel->timers[i].startTime = 0; -+ kernel->timers[i].stopTime = 0; -+ } -+ -+ /* Save context. */ -+ kernel->context = Context; -+ -+ /* Construct atom holding number of clients. */ -+ kernel->atomClients = gcvNULL; -+ gcmkONERROR(gckOS_AtomConstruct(Os, &kernel->atomClients)); -+ -+#if gcdENABLE_VG -+ kernel->vg = gcvNULL; -+ -+ if (Core == gcvCORE_VG) -+ { -+ /* Construct the gckMMU object. */ -+ gcmkONERROR( -+ gckVGKERNEL_Construct(Os, Context, kernel, &kernel->vg)); -+ -+ kernel->timeOut = gcdGPU_TIMEOUT; -+ } -+ else -+#endif -+ { -+ /* Construct the gckHARDWARE object. */ -+ gcmkONERROR( -+ gckHARDWARE_Construct(Os, kernel->core, &kernel->hardware)); -+ -+ /* Set pointer to gckKERNEL object in gckHARDWARE object. */ -+ kernel->hardware->kernel = kernel; -+ -+ kernel->timeOut = kernel->hardware->type == gcvHARDWARE_2D -+ ? gcdGPU_2D_TIMEOUT -+ : gcdGPU_TIMEOUT -+ ; -+ -+ /* Initialize virtual command buffer. */ -+ kernel->virtualCommandBuffer = gcvTRUE; -+ -+ /* Construct the gckCOMMAND object. */ -+ gcmkONERROR( -+ gckCOMMAND_Construct(kernel, &kernel->command)); -+ -+ /* Construct the gckEVENT object. */ -+ gcmkONERROR( -+ gckEVENT_Construct(kernel, &kernel->eventObj)); -+ -+ /* Construct the gckMMU object. */ -+ gcmkONERROR( -+ gckMMU_Construct(kernel, gcdMMU_SIZE, &kernel->mmu)); -+ -+ gcmkVERIFY_OK(gckOS_GetTime(&kernel->resetTimeStamp)); -+ -+ gcmkONERROR(gckHARDWARE_PrepareFunctions(kernel->hardware)); -+ -+ /* Initialize the hardware. */ -+ gcmkONERROR( -+ gckHARDWARE_InitializeHardware(kernel->hardware)); -+ -+#if gcdDVFS -+ if (gckHARDWARE_IsFeatureAvailable(kernel->hardware, -+ gcvFEATURE_DYNAMIC_FREQUENCY_SCALING)) -+ { -+ gcmkONERROR(gckDVFS_Construct(kernel->hardware, &kernel->dvfs)); -+ gcmkONERROR(gckDVFS_Start(kernel->dvfs)); -+ } -+#endif -+ } -+ -+ spin_lock_init(&kernel->irq_lock); -+ -+#if VIVANTE_PROFILER -+ /* Initialize profile setting */ -+ kernel->profileEnable = gcvFALSE; -+ kernel->profileCleanRegister = gcvTRUE; -+#endif -+ -+#if gcdANDROID_NATIVE_FENCE_SYNC -+ gcmkONERROR(gckOS_CreateSyncTimeline(Os, &kernel->timeline)); -+#endif -+ -+ kernel->recovery = gcvTRUE; -+ kernel->stuckDump = 1; -+ -+ kernel->virtualBufferHead = -+ kernel->virtualBufferTail = gcvNULL; -+ -+ gcmkONERROR( -+ gckOS_CreateMutex(Os, (gctPOINTER)&kernel->virtualBufferLock)); -+ -+#if gcdGPU_TIMEOUT && gcdINTERRUPT_STATISTIC -+ if (kernel->timeOut) -+ { -+ gcmkVERIFY_OK(gckOS_CreateTimer( -+ Os, -+ (gctTIMERFUNCTION)_MonitorTimerFunction, -+ (gctPOINTER)kernel, -+ &kernel->monitorTimer -+ )); -+ -+ kernel->monitoring = gcvFALSE; -+ -+ kernel->monitorTimerStop = gcvFALSE; -+ -+ gcmkVERIFY_OK(gckOS_StartTimer( -+ Os, -+ kernel->monitorTimer, -+ 100 -+ )); -+ } -+#endif -+ -+ /* Return pointer to the gckKERNEL object. */ -+ *Kernel = kernel; -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Kernel=0x%x", *Kernel); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (kernel != gcvNULL) -+ { -+#if gcdENABLE_VG -+ if (Core != gcvCORE_VG) -+#endif -+ { -+ if (kernel->eventObj != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckEVENT_Destroy(kernel->eventObj)); -+ } -+ -+ if (kernel->command != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckCOMMAND_Destroy(kernel->command)); -+ } -+ -+ if (kernel->hardware != gcvNULL) -+ { -+ /* Turn off the power. */ -+ gcmkVERIFY_OK(gckOS_SetGPUPower(kernel->hardware->os, -+ kernel->hardware->core, -+ gcvFALSE, -+ gcvFALSE)); -+ gcmkVERIFY_OK(gckHARDWARE_Destroy(kernel->hardware)); -+ } -+ } -+ -+ if (kernel->atomClients != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckOS_AtomDestroy(Os, kernel->atomClients)); -+ } -+ -+ if (kernel->dbCreated && kernel->db != gcvNULL) -+ { -+ if (kernel->db->dbMutex != gcvNULL) -+ { -+ /* Destroy the database mutex. */ -+ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, kernel->db->dbMutex)); -+ } -+ -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Os, kernel->db)); -+ } -+ -+ if (kernel->virtualBufferLock != gcvNULL) -+ { -+ /* Destroy the virtual command buffer mutex. */ -+ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, kernel->virtualBufferLock)); -+ } -+ -+#if gcdDVFS -+ if (kernel->dvfs) -+ { -+ gcmkVERIFY_OK(gckDVFS_Stop(kernel->dvfs)); -+ gcmkVERIFY_OK(gckDVFS_Destroy(kernel->dvfs)); -+ } -+#endif -+ -+#if gcdANDROID_NATIVE_FENCE_SYNC -+ if (kernel->timeline) -+ { -+ gcmkVERIFY_OK(gckOS_DestroySyncTimeline(Os, kernel->timeline)); -+ } -+#endif -+ -+ if (kernel->monitorTimer) -+ { -+ gcmkVERIFY_OK(gckOS_StopTimer(Os, kernel->monitorTimer)); -+ gcmkVERIFY_OK(gckOS_DestroyTimer(Os, kernel->monitorTimer)); -+ } -+ -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Os, kernel)); -+ } -+ -+ /* Return the error. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckKERNEL_Destroy -+** -+** Destroy an gckKERNEL object. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object to destroy. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckKERNEL_Destroy( -+ IN gckKERNEL Kernel -+ ) -+{ -+ gctSIZE_T i; -+ gcsDATABASE_PTR database, databaseNext; -+ gcsDATABASE_RECORD_PTR record, recordNext; -+ -+ gcmkHEADER_ARG("Kernel=0x%x", Kernel); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ -+ /* Destroy the database. */ -+ if (Kernel->dbCreated) -+ { -+ for (i = 0; i < gcmCOUNTOF(Kernel->db->db); ++i) -+ { -+ if (Kernel->db->db[i] != gcvNULL) -+ { -+ gcmkVERIFY_OK( -+ gckKERNEL_DestroyProcessDB(Kernel, Kernel->db->db[i]->processID)); -+ } -+ } -+ -+ /* Free all databases. */ -+ for (database = Kernel->db->freeDatabase; -+ database != gcvNULL; -+ database = databaseNext) -+ { -+ databaseNext = database->next; -+ -+ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, database->counterMutex)); -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, database)); -+ } -+ -+ if (Kernel->db->lastDatabase != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, Kernel->db->lastDatabase->counterMutex)); -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, Kernel->db->lastDatabase)); -+ } -+ -+ /* Free all database records. */ -+ for (record = Kernel->db->freeRecord; record != gcvNULL; record = recordNext) -+ { -+ recordNext = record->next; -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, record)); -+ } -+ -+ /* Destroy the database mutex. */ -+ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, Kernel->db->dbMutex)); -+ -+ /* Destroy video memory name database. */ -+ gcmkVERIFY_OK(gckKERNEL_DestroyIntegerDatabase(Kernel, Kernel->db->nameDatabase)); -+ -+ /* Destroy video memory name database mutex. */ -+ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, Kernel->db->nameDatabaseMutex)); -+ -+ -+ /* Destroy id-pointer database. */ -+ gcmkVERIFY_OK(gckKERNEL_DestroyIntegerDatabase(Kernel, Kernel->db->pointerDatabase)); -+ -+ /* Destroy id-pointer database mutex. */ -+ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, Kernel->db->pointerDatabaseMutex)); -+ -+ /* Destroy the database. */ -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, Kernel->db)); -+ -+ /* Notify stuck timer to quit. */ -+ Kernel->monitorTimerStop = gcvTRUE; -+ } -+ -+#if gcdENABLE_VG -+ if (Kernel->vg) -+ { -+ gcmkVERIFY_OK(gckVGKERNEL_Destroy(Kernel->vg)); -+ } -+ else -+#endif -+ { -+ /* Destroy the gckMMU object. */ -+ gcmkVERIFY_OK(gckMMU_Destroy(Kernel->mmu)); -+ -+ /* Destroy the gckCOMMNAND object. */ -+ gcmkVERIFY_OK(gckCOMMAND_Destroy(Kernel->command)); -+ -+ /* Destroy the gckEVENT object. */ -+ gcmkVERIFY_OK(gckEVENT_Destroy(Kernel->eventObj)); -+ -+ /* Destroy the gckHARDWARE object. */ -+ gcmkVERIFY_OK(gckHARDWARE_Destroy(Kernel->hardware)); -+ } -+ -+ /* Detsroy the client atom. */ -+ gcmkVERIFY_OK(gckOS_AtomDestroy(Kernel->os, Kernel->atomClients)); -+ -+ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, Kernel->virtualBufferLock)); -+ -+#if gcdDVFS -+ if (Kernel->dvfs) -+ { -+ gcmkVERIFY_OK(gckDVFS_Stop(Kernel->dvfs)); -+ gcmkVERIFY_OK(gckDVFS_Destroy(Kernel->dvfs)); -+ } -+#endif -+ -+#if gcdANDROID_NATIVE_FENCE_SYNC -+ gcmkVERIFY_OK(gckOS_DestroySyncTimeline(Kernel->os, Kernel->timeline)); -+#endif -+ -+ if (Kernel->monitorTimer) -+ { -+ gcmkVERIFY_OK(gckOS_StopTimer(Kernel->os, Kernel->monitorTimer)); -+ gcmkVERIFY_OK(gckOS_DestroyTimer(Kernel->os, Kernel->monitorTimer)); -+ } -+ -+ /* Mark the gckKERNEL object as unknown. */ -+ Kernel->object.type = gcvOBJ_UNKNOWN; -+ -+ /* Free the gckKERNEL object. */ -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, Kernel)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** _AllocateMemory -+** -+** Private function to walk all required memory pools to allocate the requested -+** amount of video memory. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** gcsHAL_INTERFACE * Interface -+** Pointer to a gcsHAL_INTERFACE structure that defines the command to -+** be dispatched. -+** -+** OUTPUT: -+** -+** gcsHAL_INTERFACE * Interface -+** Pointer to a gcsHAL_INTERFACE structure that receives any data to be -+** returned. -+*/ -+gceSTATUS -+gckKERNEL_AllocateLinearMemory( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 ProcessID, -+ IN OUT gcePOOL * Pool, -+ IN gctSIZE_T Bytes, -+ IN gctUINT32 Alignment, -+ IN gceSURF_TYPE Type, -+ IN gctUINT32 Flag, -+ OUT gctUINT32 * Node -+ ) -+{ -+ gcePOOL pool; -+ gceSTATUS status; -+ gckVIDMEM videoMemory; -+ gctINT loopCount; -+ gcuVIDMEM_NODE_PTR node = gcvNULL; -+ gctBOOL tileStatusInVirtual; -+ gctBOOL contiguous = gcvFALSE; -+ gctBOOL cacheable = gcvFALSE; -+ gctSIZE_T bytes = Bytes; -+ gctUINT32 handle = 0; -+ gceDATABASE_TYPE type; -+ -+ gcmkHEADER_ARG("Kernel=0x%x *Pool=%d Bytes=%lu Alignment=%lu Type=%d", -+ Kernel, *Pool, Bytes, Alignment, Type); -+ -+ gcmkVERIFY_ARGUMENT(Pool != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Bytes != 0); -+ -+ /* Get basic type. */ -+ Type &= 0xFF; -+ -+ /* Check flags. */ -+ contiguous = Flag & gcvALLOC_FLAG_CONTIGUOUS; -+ cacheable = Flag & gcvALLOC_FLAG_CACHEABLE; -+ -+AllocateMemory: -+ -+ /* Get initial pool. */ -+ switch (pool = *Pool) -+ { -+ case gcvPOOL_DEFAULT: -+ case gcvPOOL_LOCAL: -+ pool = gcvPOOL_LOCAL_INTERNAL; -+ loopCount = (gctINT) gcvPOOL_NUMBER_OF_POOLS; -+ break; -+ -+ case gcvPOOL_UNIFIED: -+ pool = gcvPOOL_SYSTEM; -+ loopCount = (gctINT) gcvPOOL_NUMBER_OF_POOLS; -+ break; -+ -+ case gcvPOOL_CONTIGUOUS: -+ loopCount = (gctINT) gcvPOOL_NUMBER_OF_POOLS; -+ break; -+ -+ default: -+ loopCount = 1; -+ break; -+ } -+ -+ while (loopCount-- > 0) -+ { -+ if (pool == gcvPOOL_VIRTUAL) -+ { -+ /* Create a gcuVIDMEM_NODE for virtual memory. */ -+ gcmkONERROR( -+ gckVIDMEM_ConstructVirtual(Kernel, Flag | gcvALLOC_FLAG_NON_CONTIGUOUS, Bytes, &node)); -+ -+ bytes = node->Virtual.bytes; -+ node->Virtual.type = Type; -+ -+ /* Success. */ -+ break; -+ } -+ -+ else -+ if (pool == gcvPOOL_CONTIGUOUS) -+ { -+#if gcdCONTIGUOUS_SIZE_LIMIT -+ if (Bytes > gcdCONTIGUOUS_SIZE_LIMIT && contiguous == gcvFALSE) -+ { -+ status = gcvSTATUS_OUT_OF_MEMORY; -+ } -+ else -+#endif -+ { -+ /* Create a gcuVIDMEM_NODE from contiguous memory. */ -+ status = gckVIDMEM_ConstructVirtual( -+ Kernel, -+ Flag | gcvALLOC_FLAG_CONTIGUOUS, -+ Bytes, -+ &node); -+ } -+ -+ if (gcmIS_SUCCESS(status)) -+ { -+ bytes = node->Virtual.bytes; -+ node->Virtual.type = Type; -+ -+ /* Memory allocated. */ -+ break; -+ } -+ } -+ -+ else -+ /* gcvPOOL_SYSTEM can't be cacheable. */ -+ if (cacheable == gcvFALSE) -+ { -+ /* Get pointer to gckVIDMEM object for pool. */ -+ status = gckKERNEL_GetVideoMemoryPool(Kernel, pool, &videoMemory); -+ -+ if (gcmIS_SUCCESS(status)) -+ { -+ /* Allocate memory. */ -+#if defined(gcdLINEAR_SIZE_LIMIT) -+ /* 512 KB */ -+ if (Bytes > gcdLINEAR_SIZE_LIMIT) -+ { -+ status = gcvSTATUS_OUT_OF_MEMORY; -+ } -+ else -+#endif -+ { -+ status = gckVIDMEM_AllocateLinear(Kernel, -+ videoMemory, -+ Bytes, -+ Alignment, -+ Type, -+ (*Pool == gcvPOOL_SYSTEM), -+ &node); -+ } -+ -+ if (gcmIS_SUCCESS(status)) -+ { -+ /* Memory allocated. */ -+ node->VidMem.pool = pool; -+ bytes = node->VidMem.bytes; -+ break; -+ } -+ } -+ } -+ -+ if (pool == gcvPOOL_LOCAL_INTERNAL) -+ { -+ /* Advance to external memory. */ -+ pool = gcvPOOL_LOCAL_EXTERNAL; -+ } -+ -+ else -+ if (pool == gcvPOOL_LOCAL_EXTERNAL) -+ { -+ /* Advance to contiguous system memory. */ -+ pool = gcvPOOL_SYSTEM; -+ } -+ -+ else -+ if (pool == gcvPOOL_SYSTEM) -+ { -+ /* Advance to contiguous memory. */ -+ pool = gcvPOOL_CONTIGUOUS; -+ } -+ -+ else -+ if (pool == gcvPOOL_CONTIGUOUS) -+ { -+#if gcdENABLE_VG -+ if (Kernel->vg) -+ { -+ tileStatusInVirtual = gcvFALSE; -+ } -+ else -+#endif -+ { -+ tileStatusInVirtual = -+ gckHARDWARE_IsFeatureAvailable(Kernel->hardware, -+ gcvFEATURE_MC20); -+ } -+ -+ if (Type == gcvSURF_TILE_STATUS && tileStatusInVirtual != gcvTRUE) -+ { -+ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); -+ } -+ -+ if (contiguous) -+ { -+ break; -+ } -+ -+ /* Advance to virtual memory. */ -+ pool = gcvPOOL_VIRTUAL; -+ } -+ -+ else -+ { -+ /* Out of pools. */ -+ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); -+ } -+ } -+ -+ if (node == gcvNULL) -+ { -+ if (contiguous) -+ { -+ /* Broadcast OOM message. */ -+ status = gckOS_Broadcast(Kernel->os, Kernel->hardware, gcvBROADCAST_OUT_OF_MEMORY); -+ -+ if (gcmIS_SUCCESS(status)) -+ { -+ /* Get some memory. */ -+ gckOS_Delay(gcvNULL, 1); -+ goto AllocateMemory; -+ } -+ } -+ -+ /* Nothing allocated. */ -+ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); -+ } -+ -+ /* Allocate handle for this video memory. */ -+ gcmkONERROR( -+ gckVIDMEM_NODE_Allocate(Kernel, node, Type, pool, &handle)); -+ -+ /* Return node and pool used for allocation. */ -+ *Node = handle; -+ *Pool = pool; -+ -+ /* Encode surface type and pool to database type. */ -+ type = gcvDB_VIDEO_MEMORY -+ | (Type << gcdDB_VIDEO_MEMORY_TYPE_SHIFT) -+ | (pool << gcdDB_VIDEO_MEMORY_POOL_SHIFT); -+ -+ /* Record in process db. */ -+ gcmkONERROR( -+ gckKERNEL_AddProcessDB(Kernel, -+ ProcessID, -+ type, -+ gcmINT2PTR(handle), -+ gcvNULL, -+ bytes)); -+ -+ /* Return status. */ -+ gcmkFOOTER_ARG("*Pool=%d *Node=0x%x", *Pool, *Node); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (handle) -+ { -+ /* Destroy handle allocated. */ -+ gcmkVERIFY_OK(gckVIDMEM_HANDLE_Dereference(Kernel, ProcessID, handle)); -+ } -+ -+ if (node) -+ { -+ /* Free video memory allocated. */ -+ gcmkVERIFY_OK(gckVIDMEM_Free(Kernel, node)); -+ } -+ -+ /* For some case like chrome with webgl test, it needs too much memory so that it invokes oom_killer -+ * And the case is killed by oom_killer, the user wants not to see the crash and hope the case iteself handles the condition -+ * So the patch reports the out_of_memory to the case */ -+ if ( status == gcvSTATUS_OUT_OF_MEMORY && (Flag & gcvALLOC_FLAG_MEMLIMIT) ) -+ gcmkPRINT("The running case is out_of_memory"); -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckKERNEL_ReleaseVideoMemory -+** -+** Release handle of a video memory. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** gctUINT32 ProcessID -+** ProcessID of current process. -+** -+** gctUINT32 Handle -+** Handle of video memory. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckKERNEL_ReleaseVideoMemory( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 ProcessID, -+ IN gctUINT32 Handle -+ ) -+{ -+ gceSTATUS status; -+ gckVIDMEM_NODE nodeObject; -+ gceDATABASE_TYPE type; -+ -+ gcmkHEADER_ARG("Kernel=0x%08X ProcessID=%d Handle=%d", -+ Kernel, ProcessID, Handle); -+ -+ gcmkONERROR( -+ gckVIDMEM_HANDLE_Lookup(Kernel, ProcessID, Handle, &nodeObject)); -+ -+ type = gcvDB_VIDEO_MEMORY -+ | (nodeObject->type << gcdDB_VIDEO_MEMORY_TYPE_SHIFT) -+ | (nodeObject->pool << gcdDB_VIDEO_MEMORY_POOL_SHIFT); -+ -+ gcmkONERROR( -+ gckKERNEL_RemoveProcessDB(Kernel, -+ ProcessID, -+ type, -+ gcmINT2PTR(Handle))); -+ -+ gckVIDMEM_HANDLE_Dereference(Kernel, ProcessID, Handle); -+ -+ gckVIDMEM_NODE_Dereference(Kernel, nodeObject); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckKERNEL_LockVideoMemory -+** -+** Lock a video memory node. It will generate a cpu virtual address used -+** by software and a GPU address used by GPU. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** gceCORE Core -+** GPU to which video memory is locked. -+** -+** gcsHAL_INTERFACE * Interface -+** Pointer to a gcsHAL_INTERFACE structure that defines the command to -+** be dispatched. -+** -+** OUTPUT: -+** -+** gcsHAL_INTERFACE * Interface -+** Pointer to a gcsHAL_INTERFACE structure that receives any data to be -+** returned. -+*/ -+gceSTATUS -+gckKERNEL_LockVideoMemory( -+ IN gckKERNEL Kernel, -+ IN gceCORE Core, -+ IN gctUINT32 ProcessID, -+ IN gctBOOL FromUser, -+ IN OUT gcsHAL_INTERFACE * Interface -+ ) -+{ -+ gceSTATUS status; -+ gckVIDMEM_NODE nodeObject = gcvNULL; -+ gcuVIDMEM_NODE_PTR node = gcvNULL; -+ gctBOOL locked = gcvFALSE; -+ gctBOOL asynchronous = gcvFALSE; -+ gctPOINTER pointer = gcvNULL; -+ -+ gcmkHEADER_ARG("Kernel=0x%08X ProcessID=%d", -+ Kernel, ProcessID); -+ -+ gcmkONERROR( -+ gckVIDMEM_HANDLE_LookupAndReference(Kernel, -+ Interface->u.LockVideoMemory.node, -+ &nodeObject)); -+ -+ node = nodeObject->node; -+ -+ Interface->u.LockVideoMemory.gid = 0; -+ -+ /* Lock video memory. */ -+ gcmkONERROR( -+ gckVIDMEM_Lock(Kernel, -+ nodeObject, -+ Interface->u.LockVideoMemory.cacheable, -+ &Interface->u.LockVideoMemory.address, -+ &Interface->u.LockVideoMemory.gid, -+ &Interface->u.LockVideoMemory.physicalAddress)); -+ -+ locked = gcvTRUE; -+ -+ if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM) -+ { -+ /* Map video memory address into user space. */ -+ gcmkONERROR( -+ gckKERNEL_MapVideoMemoryEx(Kernel, -+ Core, -+ FromUser, -+ Interface->u.LockVideoMemory.address, -+ &pointer)); -+ -+ Interface->u.LockVideoMemory.memory = gcmPTR_TO_UINT64(pointer); -+ } -+ else -+ { -+ Interface->u.LockVideoMemory.memory = gcmPTR_TO_UINT64(node->Virtual.logical); -+ -+ /* Success. */ -+ status = gcvSTATUS_OK; -+ } -+ -+#if gcdPROCESS_ADDRESS_SPACE -+ gcmkONERROR(gckVIDMEM_Node_Lock( -+ Kernel, -+ nodeObject, -+ &Interface->u.LockVideoMemory.address -+ )); -+#endif -+ -+ -+ gcmkONERROR( -+ gckKERNEL_AddProcessDB(Kernel, -+ ProcessID, gcvDB_VIDEO_MEMORY_LOCKED, -+ gcmINT2PTR(Interface->u.LockVideoMemory.node), -+ gcvNULL, -+ 0)); -+ -+ gckVIDMEM_HANDLE_Reference( -+ Kernel, ProcessID, (gctUINT32)Interface->u.LockVideoMemory.node); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (locked) -+ { -+ /* Roll back the lock. */ -+ gcmkVERIFY_OK(gckVIDMEM_Unlock(Kernel, -+ nodeObject, -+ gcvSURF_TYPE_UNKNOWN, -+ &asynchronous)); -+ -+ if (gcvTRUE == asynchronous) -+ { -+ /* Bottom Half */ -+ gcmkVERIFY_OK(gckVIDMEM_Unlock(Kernel, -+ nodeObject, -+ gcvSURF_TYPE_UNKNOWN, -+ gcvNULL)); -+ } -+ } -+ -+ if (nodeObject != gcvNULL) -+ { -+ gckVIDMEM_NODE_Dereference(Kernel, nodeObject); -+ } -+ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckKERNEL_UnlockVideoMemory -+** -+** Unlock a video memory node. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** gctUINT32 ProcessID -+** ProcessID of current process. -+** -+** gcsHAL_INTERFACE * Interface -+** Pointer to a gcsHAL_INTERFACE structure that defines the command to -+** be dispatched. -+** -+** OUTPUT: -+** -+** gcsHAL_INTERFACE * Interface -+** Pointer to a gcsHAL_INTERFACE structure that receives any data to be -+** returned. -+*/ -+gceSTATUS -+gckKERNEL_UnlockVideoMemory( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 ProcessID, -+ IN OUT gcsHAL_INTERFACE * Interface -+ ) -+{ -+ gceSTATUS status; -+ gckVIDMEM_NODE nodeObject; -+ gcuVIDMEM_NODE_PTR node; -+ -+ gcmkHEADER_ARG("Kernel=0x%08X ProcessID=%d", -+ Kernel, ProcessID); -+ -+ gcmkONERROR(gckVIDMEM_HANDLE_Lookup( -+ Kernel, -+ ProcessID, -+ (gctUINT32)Interface->u.UnlockVideoMemory.node, -+ &nodeObject)); -+ -+ node = nodeObject->node; -+ -+ /* Unlock video memory. */ -+ gcmkONERROR(gckVIDMEM_Unlock( -+ Kernel, -+ nodeObject, -+ Interface->u.UnlockVideoMemory.type, -+ &Interface->u.UnlockVideoMemory.asynchroneous)); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckKERNEL_QueryDatabase( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 ProcessID, -+ IN OUT gcsHAL_INTERFACE * Interface -+ ) -+{ -+ gceSTATUS status; -+ gctINT i; -+ gcuDATABASE_INFO tmp; -+ -+ gceDATABASE_TYPE type[3] = { -+ gcvDB_VIDEO_MEMORY | (gcvPOOL_SYSTEM << gcdDB_VIDEO_MEMORY_POOL_SHIFT), -+ gcvDB_VIDEO_MEMORY | (gcvPOOL_CONTIGUOUS << gcdDB_VIDEO_MEMORY_POOL_SHIFT), -+ gcvDB_VIDEO_MEMORY | (gcvPOOL_VIRTUAL << gcdDB_VIDEO_MEMORY_POOL_SHIFT), -+ }; -+ -+ gcmkHEADER(); -+ -+ /* Query video memory. */ -+ gcmkONERROR( -+ gckKERNEL_QueryProcessDB(Kernel, -+ Interface->u.Database.processID, -+ !Interface->u.Database.validProcessID, -+ gcvDB_VIDEO_MEMORY, -+ &Interface->u.Database.vidMem)); -+ -+ /* Query non-paged memory. */ -+ gcmkONERROR( -+ gckKERNEL_QueryProcessDB(Kernel, -+ Interface->u.Database.processID, -+ !Interface->u.Database.validProcessID, -+ gcvDB_NON_PAGED, -+ &Interface->u.Database.nonPaged)); -+ -+ /* Query contiguous memory. */ -+ gcmkONERROR( -+ gckKERNEL_QueryProcessDB(Kernel, -+ Interface->u.Database.processID, -+ !Interface->u.Database.validProcessID, -+ gcvDB_CONTIGUOUS, -+ &Interface->u.Database.contiguous)); -+ -+ /* Query GPU idle time. */ -+ gcmkONERROR( -+ gckKERNEL_QueryProcessDB(Kernel, -+ Interface->u.Database.processID, -+ !Interface->u.Database.validProcessID, -+ gcvDB_IDLE, -+ &Interface->u.Database.gpuIdle)); -+ for (i = 0; i < 3; i++) -+ { -+ /* Query each video memory pool. */ -+ gcmkONERROR( -+ gckKERNEL_QueryProcessDB(Kernel, -+ Interface->u.Database.processID, -+ !Interface->u.Database.validProcessID, -+ type[i], -+ &Interface->u.Database.vidMemPool[i])); -+ } -+ -+ /* Query virtual command buffer pool. */ -+ gcmkONERROR( -+ gckKERNEL_QueryProcessDB(Kernel, -+ Interface->u.Database.processID, -+ !Interface->u.Database.validProcessID, -+ gcvDB_COMMAND_BUFFER, -+ &tmp)); -+ -+ Interface->u.Database.vidMemPool[2].counters.bytes += tmp.counters.bytes; -+ Interface->u.Database.vidMemPool[2].counters.maxBytes += tmp.counters.maxBytes; -+ Interface->u.Database.vidMemPool[2].counters.totalBytes += tmp.counters.totalBytes; -+ -+ Interface->u.Database.vidMem.counters.bytes += tmp.counters.bytes; -+ Interface->u.Database.vidMem.counters.maxBytes += tmp.counters.maxBytes; -+ Interface->u.Database.vidMem.counters.totalBytes += tmp.counters.totalBytes; -+ -+#if gcmIS_DEBUG(gcdDEBUG_TRACE) -+ gckKERNEL_DumpVidMemUsage(Kernel, Interface->u.Database.processID); -+#endif -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckKERNEL_ConfigPowerManagement( -+ IN gckKERNEL Kernel, -+ IN OUT gcsHAL_INTERFACE * Interface -+) -+{ -+ gceSTATUS status; -+ gctBOOL enable = Interface->u.ConfigPowerManagement.enable; -+ -+ gcmkHEADER(); -+ -+ gcmkONERROR(gckHARDWARE_SetPowerManagement(Kernel->hardware, enable)); -+ -+ if (enable == gcvTRUE) -+ { -+ gcmkONERROR( -+ gckHARDWARE_SetPowerManagementState(Kernel->hardware, gcvPOWER_ON)); -+ } -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckKERNEL_Dispatch -+** -+** Dispatch a command received from the user HAL layer. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** gctBOOL FromUser -+** whether the call is from the user space. -+** -+** gcsHAL_INTERFACE * Interface -+** Pointer to a gcsHAL_INTERFACE structure that defines the command to -+** be dispatched. -+** -+** OUTPUT: -+** -+** gcsHAL_INTERFACE * Interface -+** Pointer to a gcsHAL_INTERFACE structure that receives any data to be -+** returned. -+*/ -+gceSTATUS -+gckKERNEL_Dispatch( -+ IN gckKERNEL Kernel, -+ IN gctBOOL FromUser, -+ IN OUT gcsHAL_INTERFACE * Interface -+ ) -+{ -+ gceSTATUS status = gcvSTATUS_OK; -+ gctPHYS_ADDR physical = gcvNULL; -+ gctSIZE_T bytes; -+ gctPOINTER logical = gcvNULL; -+ gctPOINTER info = gcvNULL; -+#if (gcdENABLE_3D || gcdENABLE_2D) -+ gckCONTEXT context = gcvNULL; -+#endif -+ gckKERNEL kernel = Kernel; -+ gctUINT32 address; -+ gctUINT32 processID; -+ gctUINT32 paddr = gcvINVALID_ADDRESS; -+ gctSIGNAL signal; -+ gckVIRTUAL_COMMAND_BUFFER_PTR buffer; -+ -+ gckVIDMEM_NODE nodeObject; -+ gctBOOL powerMutexAcquired = gcvFALSE; -+ -+ gcmkHEADER_ARG("Kernel=0x%x FromUser=%d Interface=0x%x", -+ Kernel, FromUser, Interface); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ gcmkVERIFY_ARGUMENT(Interface != gcvNULL); -+ -+#if gcmIS_DEBUG(gcdDEBUG_TRACE) -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_KERNEL, -+ "Dispatching command %d (%s)", -+ Interface->command, _DispatchText[Interface->command]); -+#endif -+ -+ /* Get the current process ID. */ -+ gcmkONERROR(gckOS_GetProcessID(&processID)); -+ -+ /* Dispatch on command. */ -+ switch (Interface->command) -+ { -+ case gcvHAL_GET_BASE_ADDRESS: -+ /* Get base address. */ -+ gcmkONERROR( -+ gckOS_GetBaseAddress(Kernel->os, -+ &Interface->u.GetBaseAddress.baseAddress)); -+ break; -+ -+ case gcvHAL_QUERY_VIDEO_MEMORY: -+ /* Query video memory size. */ -+ gcmkONERROR(gckKERNEL_QueryVideoMemory(Kernel, Interface)); -+ break; -+ -+ case gcvHAL_QUERY_CHIP_IDENTITY: -+ /* Query chip identity. */ -+ gcmkONERROR( -+ gckHARDWARE_QueryChipIdentity( -+ Kernel->hardware, -+ &Interface->u.QueryChipIdentity)); -+ break; -+ -+ case gcvHAL_MAP_MEMORY: -+ physical = gcmINT2PTR(Interface->u.MapMemory.physical); -+ -+ /* Map memory. */ -+ gcmkONERROR( -+ gckKERNEL_MapMemory(Kernel, -+ physical, -+ (gctSIZE_T) Interface->u.MapMemory.bytes, -+ &logical)); -+ -+ Interface->u.MapMemory.logical = gcmPTR_TO_UINT64(logical); -+ -+ gcmkVERIFY_OK( -+ gckKERNEL_AddProcessDB(Kernel, -+ processID, gcvDB_MAP_MEMORY, -+ logical, -+ physical, -+ (gctSIZE_T) Interface->u.MapMemory.bytes)); -+ break; -+ -+ case gcvHAL_UNMAP_MEMORY: -+ physical = gcmINT2PTR(Interface->u.UnmapMemory.physical); -+ -+ gcmkVERIFY_OK( -+ gckKERNEL_RemoveProcessDB(Kernel, -+ processID, gcvDB_MAP_MEMORY, -+ gcmUINT64_TO_PTR(Interface->u.UnmapMemory.logical))); -+ -+ /* Unmap memory. */ -+ gcmkONERROR( -+ gckKERNEL_UnmapMemory(Kernel, -+ physical, -+ (gctSIZE_T) Interface->u.UnmapMemory.bytes, -+ gcmUINT64_TO_PTR(Interface->u.UnmapMemory.logical))); -+ break; -+ -+ case gcvHAL_ALLOCATE_NON_PAGED_MEMORY: -+ bytes = (gctSIZE_T) Interface->u.AllocateNonPagedMemory.bytes; -+ -+ /* Allocate non-paged memory. */ -+ gcmkONERROR( -+ gckOS_AllocateNonPagedMemory( -+ Kernel->os, -+ FromUser, -+ &bytes, -+ &physical, -+ &logical)); -+ -+ Interface->u.AllocateNonPagedMemory.bytes = bytes; -+ Interface->u.AllocateNonPagedMemory.logical = gcmPTR_TO_UINT64(logical); -+ Interface->u.AllocateNonPagedMemory.physical = gcmPTR_TO_NAME(physical); -+ -+ gcmkVERIFY_OK( -+ gckKERNEL_AddProcessDB(Kernel, -+ processID, gcvDB_NON_PAGED, -+ logical, -+ gcmINT2PTR(Interface->u.AllocateNonPagedMemory.physical), -+ bytes)); -+ break; -+ -+ case gcvHAL_ALLOCATE_VIRTUAL_COMMAND_BUFFER: -+ bytes = (gctSIZE_T) Interface->u.AllocateVirtualCommandBuffer.bytes; -+ -+ gcmkONERROR( -+ gckKERNEL_AllocateVirtualCommandBuffer( -+ Kernel, -+ FromUser, -+ &bytes, -+ &physical, -+ &logical)); -+ -+ Interface->u.AllocateVirtualCommandBuffer.bytes = bytes; -+ Interface->u.AllocateVirtualCommandBuffer.logical = gcmPTR_TO_UINT64(logical); -+ Interface->u.AllocateVirtualCommandBuffer.physical = gcmPTR_TO_NAME(physical); -+ -+ gcmkVERIFY_OK( -+ gckKERNEL_AddProcessDB(Kernel, -+ processID, gcvDB_COMMAND_BUFFER, -+ logical, -+ gcmINT2PTR(Interface->u.AllocateVirtualCommandBuffer.physical), -+ bytes)); -+ break; -+ -+ case gcvHAL_FREE_NON_PAGED_MEMORY: -+ physical = gcmNAME_TO_PTR(Interface->u.FreeNonPagedMemory.physical); -+ -+ gcmkVERIFY_OK( -+ gckKERNEL_RemoveProcessDB(Kernel, -+ processID, gcvDB_NON_PAGED, -+ gcmUINT64_TO_PTR(Interface->u.FreeNonPagedMemory.logical))); -+ -+ /* Unmap user logical out of physical memory first. */ -+ gcmkONERROR(gckOS_UnmapUserLogical(Kernel->os, -+ physical, -+ (gctSIZE_T) Interface->u.FreeNonPagedMemory.bytes, -+ gcmUINT64_TO_PTR(Interface->u.FreeNonPagedMemory.logical))); -+ -+ /* Free non-paged memory. */ -+ gcmkONERROR( -+ gckOS_FreeNonPagedMemory(Kernel->os, -+ (gctSIZE_T) Interface->u.FreeNonPagedMemory.bytes, -+ physical, -+ gcmUINT64_TO_PTR(Interface->u.FreeNonPagedMemory.logical))); -+ -+ gcmRELEASE_NAME(Interface->u.FreeNonPagedMemory.physical); -+ break; -+ -+ case gcvHAL_ALLOCATE_CONTIGUOUS_MEMORY: -+ bytes = (gctSIZE_T) Interface->u.AllocateContiguousMemory.bytes; -+ -+ /* Allocate contiguous memory. */ -+ gcmkONERROR(gckOS_AllocateContiguous( -+ Kernel->os, -+ FromUser, -+ &bytes, -+ &physical, -+ &logical)); -+ -+ Interface->u.AllocateContiguousMemory.bytes = bytes; -+ Interface->u.AllocateContiguousMemory.logical = gcmPTR_TO_UINT64(logical); -+ Interface->u.AllocateContiguousMemory.physical = gcmPTR_TO_NAME(physical); -+ -+ gcmkONERROR(gckHARDWARE_ConvertLogical( -+ Kernel->hardware, -+ logical, -+ gcvTRUE, -+ &Interface->u.AllocateContiguousMemory.address)); -+ -+ gcmkVERIFY_OK(gckKERNEL_AddProcessDB( -+ Kernel, -+ processID, gcvDB_CONTIGUOUS, -+ logical, -+ gcmINT2PTR(Interface->u.AllocateContiguousMemory.physical), -+ bytes)); -+ break; -+ -+ case gcvHAL_FREE_CONTIGUOUS_MEMORY: -+ physical = gcmNAME_TO_PTR(Interface->u.FreeContiguousMemory.physical); -+ -+ gcmkVERIFY_OK( -+ gckKERNEL_RemoveProcessDB(Kernel, -+ processID, gcvDB_CONTIGUOUS, -+ gcmUINT64_TO_PTR(Interface->u.FreeNonPagedMemory.logical))); -+ -+ /* Unmap user logical out of physical memory first. */ -+ gcmkONERROR(gckOS_UnmapUserLogical(Kernel->os, -+ physical, -+ (gctSIZE_T) Interface->u.FreeContiguousMemory.bytes, -+ gcmUINT64_TO_PTR(Interface->u.FreeContiguousMemory.logical))); -+ -+ /* Free contiguous memory. */ -+ gcmkONERROR( -+ gckOS_FreeContiguous(Kernel->os, -+ physical, -+ gcmUINT64_TO_PTR(Interface->u.FreeContiguousMemory.logical), -+ (gctSIZE_T) Interface->u.FreeContiguousMemory.bytes)); -+ -+ gcmRELEASE_NAME(Interface->u.FreeContiguousMemory.physical); -+ break; -+ -+ case gcvHAL_ALLOCATE_VIDEO_MEMORY: -+ -+ gcmkONERROR(gcvSTATUS_NOT_SUPPORTED); -+ -+ break; -+ -+ case gcvHAL_ALLOCATE_LINEAR_VIDEO_MEMORY: -+ /* Allocate memory. */ -+ gcmkONERROR( -+ gckKERNEL_AllocateLinearMemory(Kernel, processID, -+ &Interface->u.AllocateLinearVideoMemory.pool, -+ Interface->u.AllocateLinearVideoMemory.bytes, -+ Interface->u.AllocateLinearVideoMemory.alignment, -+ Interface->u.AllocateLinearVideoMemory.type, -+ Interface->u.AllocateLinearVideoMemory.flag, -+ &Interface->u.AllocateLinearVideoMemory.node)); -+ break; -+ -+ case gcvHAL_RELEASE_VIDEO_MEMORY: -+ /* Release video memory. */ -+ gcmkONERROR(gckKERNEL_ReleaseVideoMemory( -+ Kernel, processID, -+ (gctUINT32)Interface->u.ReleaseVideoMemory.node -+ )); -+ break; -+ -+ case gcvHAL_LOCK_VIDEO_MEMORY: -+ /* Lock video memory. */ -+ gcmkONERROR(gckKERNEL_LockVideoMemory(Kernel, Kernel->core, processID, FromUser, Interface)); -+ break; -+ -+ case gcvHAL_UNLOCK_VIDEO_MEMORY: -+ /* Unlock video memory. */ -+ gcmkONERROR(gckKERNEL_UnlockVideoMemory(Kernel, processID, Interface)); -+ break; -+ -+ case gcvHAL_EVENT_COMMIT: -+ /* Commit an event queue. */ -+ gcmkONERROR( -+ gckEVENT_Commit(Kernel->eventObj, -+ gcmUINT64_TO_PTR(Interface->u.Event.queue))); -+ break; -+ -+ case gcvHAL_COMMIT: -+ /* Commit a command and context buffer. */ -+ gcmkONERROR( -+ gckCOMMAND_Commit(Kernel->command, -+ Interface->u.Commit.context ? -+ gcmNAME_TO_PTR(Interface->u.Commit.context) : gcvNULL, -+ gcmUINT64_TO_PTR(Interface->u.Commit.commandBuffer), -+ gcmUINT64_TO_PTR(Interface->u.Commit.delta), -+ gcmUINT64_TO_PTR(Interface->u.Commit.queue), -+ processID)); -+ -+ break; -+ -+ case gcvHAL_STALL: -+ /* Stall the command queue. */ -+ gcmkONERROR(gckCOMMAND_Stall(Kernel->command, gcvFALSE)); -+ break; -+ -+ case gcvHAL_MAP_USER_MEMORY: -+ /* Map user memory to DMA. */ -+ gcmkONERROR( -+ gckOS_MapUserMemory(Kernel->os, -+ Kernel->core, -+ gcmUINT64_TO_PTR(Interface->u.MapUserMemory.memory), -+ Interface->u.MapUserMemory.physical, -+ (gctSIZE_T) Interface->u.MapUserMemory.size, -+ &info, -+ &Interface->u.MapUserMemory.address)); -+ -+ Interface->u.MapUserMemory.info = gcmPTR_TO_NAME(info); -+ -+ gcmkVERIFY_OK( -+ gckKERNEL_AddProcessDB(Kernel, -+ processID, gcvDB_MAP_USER_MEMORY, -+ gcmINT2PTR(Interface->u.MapUserMemory.info), -+ gcmUINT64_TO_PTR(Interface->u.MapUserMemory.memory), -+ (gctSIZE_T) Interface->u.MapUserMemory.size)); -+ break; -+ -+ case gcvHAL_UNMAP_USER_MEMORY: -+ address = Interface->u.UnmapUserMemory.address; -+ info = gcmNAME_TO_PTR(Interface->u.UnmapUserMemory.info); -+ -+ gcmkVERIFY_OK( -+ gckKERNEL_RemoveProcessDB(Kernel, -+ processID, gcvDB_MAP_USER_MEMORY, -+ gcmINT2PTR(Interface->u.UnmapUserMemory.info))); -+ /* Unmap user memory. */ -+ gcmkONERROR( -+ gckOS_UnmapUserMemory(Kernel->os, -+ Kernel->core, -+ gcmUINT64_TO_PTR(Interface->u.UnmapUserMemory.memory), -+ (gctSIZE_T) Interface->u.UnmapUserMemory.size, -+ info, -+ address)); -+ -+ gcmRELEASE_NAME(Interface->u.UnmapUserMemory.info); -+ break; -+ -+ case gcvHAL_USER_SIGNAL: -+ /* Dispatch depends on the user signal subcommands. */ -+ switch(Interface->u.UserSignal.command) -+ { -+ case gcvUSER_SIGNAL_CREATE: -+ /* Create a signal used in the user space. */ -+ gcmkONERROR( -+ gckOS_CreateUserSignal(Kernel->os, -+ Interface->u.UserSignal.manualReset, -+ &Interface->u.UserSignal.id)); -+ -+ gcmkVERIFY_OK( -+ gckKERNEL_AddProcessDB(Kernel, -+ processID, gcvDB_SIGNAL, -+ gcmINT2PTR(Interface->u.UserSignal.id), -+ gcvNULL, -+ 0)); -+ break; -+ -+ case gcvUSER_SIGNAL_DESTROY: -+ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB( -+ Kernel, -+ processID, gcvDB_SIGNAL, -+ gcmINT2PTR(Interface->u.UserSignal.id))); -+ -+ /* Destroy the signal. */ -+ gcmkONERROR( -+ gckOS_DestroyUserSignal(Kernel->os, -+ Interface->u.UserSignal.id)); -+ break; -+ -+ case gcvUSER_SIGNAL_SIGNAL: -+ /* Signal the signal. */ -+ gcmkONERROR( -+ gckOS_SignalUserSignal(Kernel->os, -+ Interface->u.UserSignal.id, -+ Interface->u.UserSignal.state)); -+ break; -+ -+ case gcvUSER_SIGNAL_WAIT: -+ /* Wait on the signal. */ -+ status = gckOS_WaitUserSignal(Kernel->os, -+ Interface->u.UserSignal.id, -+ Interface->u.UserSignal.wait); -+ -+ break; -+ -+ case gcvUSER_SIGNAL_MAP: -+ gcmkONERROR( -+ gckOS_MapSignal(Kernel->os, -+ (gctSIGNAL)(gctUINTPTR_T)Interface->u.UserSignal.id, -+ (gctHANDLE)(gctUINTPTR_T)processID, -+ &signal)); -+ -+ gcmkVERIFY_OK( -+ gckKERNEL_AddProcessDB(Kernel, -+ processID, gcvDB_SIGNAL, -+ gcmINT2PTR(Interface->u.UserSignal.id), -+ gcvNULL, -+ 0)); -+ break; -+ -+ case gcvUSER_SIGNAL_UNMAP: -+ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB( -+ Kernel, -+ processID, gcvDB_SIGNAL, -+ gcmINT2PTR(Interface->u.UserSignal.id))); -+ -+ /* Destroy the signal. */ -+ gcmkONERROR( -+ gckOS_DestroyUserSignal(Kernel->os, -+ Interface->u.UserSignal.id)); -+ break; -+ -+ default: -+ /* Invalid user signal command. */ -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ } -+ break; -+ -+ case gcvHAL_SET_POWER_MANAGEMENT_STATE: -+ /* Set the power management state. */ -+ gcmkONERROR( -+ gckHARDWARE_SetPowerManagementState( -+ Kernel->hardware, -+ Interface->u.SetPowerManagement.state)); -+ break; -+ -+ case gcvHAL_QUERY_POWER_MANAGEMENT_STATE: -+ /* Chip is not idle. */ -+ Interface->u.QueryPowerManagement.isIdle = gcvFALSE; -+ -+ /* Query the power management state. */ -+ gcmkONERROR(gckHARDWARE_QueryPowerManagementState( -+ Kernel->hardware, -+ &Interface->u.QueryPowerManagement.state)); -+ -+ /* Query the idle state. */ -+ gcmkONERROR( -+ gckHARDWARE_QueryIdle(Kernel->hardware, -+ &Interface->u.QueryPowerManagement.isIdle)); -+ break; -+ -+ case gcvHAL_READ_REGISTER: -+#if gcdREGISTER_ACCESS_FROM_USER -+ { -+ gceCHIPPOWERSTATE power; -+ -+ gcmkONERROR(gckOS_AcquireMutex(Kernel->os, Kernel->hardware->powerMutex, gcvINFINITE)); -+ powerMutexAcquired = gcvTRUE; -+ gcmkONERROR(gckHARDWARE_QueryPowerManagementState(Kernel->hardware, -+ &power)); -+ if (power == gcvPOWER_ON) -+ { -+ /* Read a register. */ -+ gcmkONERROR(gckOS_ReadRegisterEx( -+ Kernel->os, -+ Kernel->core, -+ Interface->u.ReadRegisterData.address, -+ &Interface->u.ReadRegisterData.data)); -+ } -+ else -+ { -+ /* Chip is in power-state. */ -+ Interface->u.ReadRegisterData.data = 0; -+ status = gcvSTATUS_CHIP_NOT_READY; -+ } -+ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->hardware->powerMutex)); -+ powerMutexAcquired = gcvFALSE; -+ } -+#else -+ /* No access from user land to read registers. */ -+ Interface->u.ReadRegisterData.data = 0; -+ status = gcvSTATUS_NOT_SUPPORTED; -+#endif -+ break; -+ -+ case gcvHAL_WRITE_REGISTER: -+#if gcdREGISTER_ACCESS_FROM_USER -+ { -+ gceCHIPPOWERSTATE power; -+ -+ gcmkONERROR(gckOS_AcquireMutex(Kernel->os, Kernel->hardware->powerMutex, gcvINFINITE)); -+ powerMutexAcquired = gcvTRUE; -+ gcmkONERROR(gckHARDWARE_QueryPowerManagementState(Kernel->hardware, -+ &power)); -+ if (power == gcvPOWER_ON) -+ { -+ /* Write a register. */ -+ gcmkONERROR( -+ gckOS_WriteRegisterEx(Kernel->os, -+ Kernel->core, -+ Interface->u.WriteRegisterData.address, -+ Interface->u.WriteRegisterData.data)); -+ } -+ else -+ { -+ /* Chip is in power-state. */ -+ Interface->u.WriteRegisterData.data = 0; -+ status = gcvSTATUS_CHIP_NOT_READY; -+ } -+ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->hardware->powerMutex)); -+ powerMutexAcquired = gcvFALSE; -+ } -+#else -+ /* No access from user land to write registers. */ -+ status = gcvSTATUS_NOT_SUPPORTED; -+#endif -+ break; -+ -+ case gcvHAL_READ_ALL_PROFILE_REGISTERS: -+#if VIVANTE_PROFILER && VIVANTE_PROFILER_CONTEXT -+ /* Read profile data according to the context. */ -+ gcmkONERROR( -+ gckHARDWARE_QueryContextProfile( -+ Kernel->hardware, -+ Kernel->profileCleanRegister, -+ gcmNAME_TO_PTR(Interface->u.RegisterProfileData.context), -+ &Interface->u.RegisterProfileData.counters)); -+#elif VIVANTE_PROFILER -+ /* Read all 3D profile registers. */ -+ gcmkONERROR( -+ gckHARDWARE_QueryProfileRegisters( -+ Kernel->hardware, -+ Kernel->profileCleanRegister, -+ &Interface->u.RegisterProfileData.counters)); -+#else -+ status = gcvSTATUS_OK; -+#endif -+ break; -+ -+ case gcvHAL_PROFILE_REGISTERS_2D: -+#if VIVANTE_PROFILER -+ /* Read all 2D profile registers. */ -+ gcmkONERROR( -+ gckHARDWARE_ProfileEngine2D( -+ Kernel->hardware, -+ gcmUINT64_TO_PTR(Interface->u.RegisterProfileData2D.hwProfile2D))); -+#else -+ status = gcvSTATUS_OK; -+#endif -+ break; -+ -+ case gcvHAL_GET_PROFILE_SETTING: -+#if VIVANTE_PROFILER -+ /* Get profile setting */ -+ Interface->u.GetProfileSetting.enable = Kernel->profileEnable; -+#endif -+ -+ status = gcvSTATUS_OK; -+ break; -+ -+ case gcvHAL_SET_PROFILE_SETTING: -+#if VIVANTE_PROFILER -+ /* Set profile setting */ -+ if(Kernel->hardware->gpuProfiler) -+ { -+ Kernel->profileEnable = Interface->u.SetProfileSetting.enable; -+#if VIVANTE_PROFILER_NEW -+ if (Kernel->profileEnable) -+ gckHARDWARE_InitProfiler(Kernel->hardware); -+#endif -+ } -+ else -+ { -+ status = gcvSTATUS_NOT_SUPPORTED; -+ break; -+ } -+#endif -+ -+ status = gcvSTATUS_OK; -+ break; -+ -+#if VIVANTE_PROFILER_PERDRAW -+ case gcvHAL_READ_PROFILER_REGISTER_SETTING: -+ #if VIVANTE_PROFILER -+ Kernel->profileCleanRegister = Interface->u.SetProfilerRegisterClear.bclear; -+ #endif -+ status = gcvSTATUS_OK; -+ break; -+#endif -+ -+ case gcvHAL_QUERY_KERNEL_SETTINGS: -+ /* Get kernel settings. */ -+ gcmkONERROR( -+ gckKERNEL_QuerySettings(Kernel, -+ &Interface->u.QueryKernelSettings.settings)); -+ break; -+ -+ case gcvHAL_RESET: -+ /* Reset the hardware. */ -+ gcmkONERROR( -+ gckHARDWARE_Reset(Kernel->hardware)); -+ break; -+ -+ case gcvHAL_DEBUG: -+ /* Set debug level and zones. */ -+ if (Interface->u.Debug.set) -+ { -+ gckOS_SetDebugLevel(Interface->u.Debug.level); -+ gckOS_SetDebugZones(Interface->u.Debug.zones, -+ Interface->u.Debug.enable); -+ } -+ -+ if (Interface->u.Debug.message[0] != '\0') -+ { -+ /* Print a message to the debugger. */ -+ if (Interface->u.Debug.type == gcvMESSAGE_TEXT) -+ { -+ gckOS_CopyPrint(Interface->u.Debug.message); -+ } -+ else -+ { -+ gckOS_DumpBuffer(Kernel->os, -+ Interface->u.Debug.message, -+ Interface->u.Debug.messageSize, -+ gceDUMP_BUFFER_FROM_USER, -+ gcvTRUE); -+ } -+ } -+ status = gcvSTATUS_OK; -+ break; -+ -+ case gcvHAL_DUMP_GPU_STATE: -+ { -+ gceCHIPPOWERSTATE power; -+ -+ _DumpDriverConfigure(Kernel); -+ -+ gcmkONERROR(gckHARDWARE_QueryPowerManagementState( -+ Kernel->hardware, -+ &power -+ )); -+ -+ if (power == gcvPOWER_ON) -+ { -+ Interface->u.ReadRegisterData.data = 1; -+ -+ _DumpState(Kernel); -+ } -+ else -+ { -+ Interface->u.ReadRegisterData.data = 0; -+ status = gcvSTATUS_CHIP_NOT_READY; -+ -+ gcmkPRINT("[galcore]: Can't dump state if GPU isn't POWER ON."); -+ } -+ } -+ break; -+ -+ case gcvHAL_DUMP_EVENT: -+ break; -+ -+ case gcvHAL_CACHE: -+ -+ logical = gcmUINT64_TO_PTR(Interface->u.Cache.logical); -+ -+ if (Interface->u.Cache.node) -+ { -+ gcmkONERROR(gckVIDMEM_HANDLE_Lookup( -+ Kernel, -+ processID, -+ Interface->u.Cache.node, -+ &nodeObject)); -+ -+ if (nodeObject->node->VidMem.memory->object.type == gcvOBJ_VIDMEM -+ || nodeObject->node->Virtual.contiguous -+ ) -+ { -+ /* If memory is contiguous, get physical address. */ -+ gcmkONERROR(gckOS_GetPhysicalAddress( -+ Kernel->os, logical, (gctUINT32*)&paddr)); -+ } -+ } -+ -+ bytes = (gctSIZE_T) Interface->u.Cache.bytes; -+ switch(Interface->u.Cache.operation) -+ { -+ case gcvCACHE_FLUSH: -+ /* Clean and invalidate the cache. */ -+ status = gckOS_CacheFlush(Kernel->os, -+ processID, -+ physical, -+ paddr, -+ logical, -+ bytes); -+ break; -+ case gcvCACHE_CLEAN: -+ /* Clean the cache. */ -+ status = gckOS_CacheClean(Kernel->os, -+ processID, -+ physical, -+ paddr, -+ logical, -+ bytes); -+ break; -+ case gcvCACHE_INVALIDATE: -+ /* Invalidate the cache. */ -+ status = gckOS_CacheInvalidate(Kernel->os, -+ processID, -+ physical, -+ paddr, -+ logical, -+ bytes); -+ break; -+ -+ case gcvCACHE_MEMORY_BARRIER: -+ status = gckOS_MemoryBarrier(Kernel->os, -+ logical); -+ break; -+ default: -+ status = gcvSTATUS_INVALID_ARGUMENT; -+ break; -+ } -+ break; -+ -+ case gcvHAL_TIMESTAMP: -+ /* Check for invalid timer. */ -+ if ((Interface->u.TimeStamp.timer >= gcmCOUNTOF(Kernel->timers)) -+ || (Interface->u.TimeStamp.request != 2)) -+ { -+ Interface->u.TimeStamp.timeDelta = 0; -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ } -+ -+ /* Return timer results and reset timer. */ -+ { -+ gcsTIMER_PTR timer = &(Kernel->timers[Interface->u.TimeStamp.timer]); -+ gctUINT64 timeDelta = 0; -+ -+ if (timer->stopTime < timer->startTime ) -+ { -+ Interface->u.TimeStamp.timeDelta = 0; -+ gcmkONERROR(gcvSTATUS_TIMER_OVERFLOW); -+ } -+ -+ timeDelta = timer->stopTime - timer->startTime; -+ -+ /* Check truncation overflow. */ -+ Interface->u.TimeStamp.timeDelta = (gctINT32) timeDelta; -+ /*bit0~bit30 is available*/ -+ if (timeDelta>>31) -+ { -+ Interface->u.TimeStamp.timeDelta = 0; -+ gcmkONERROR(gcvSTATUS_TIMER_OVERFLOW); -+ } -+ -+ status = gcvSTATUS_OK; -+ } -+ break; -+ -+ case gcvHAL_DATABASE: -+ gcmkONERROR(gckKERNEL_QueryDatabase(Kernel, processID, Interface)); -+ break; -+ -+ case gcvHAL_VERSION: -+ Interface->u.Version.major = gcvVERSION_MAJOR; -+ Interface->u.Version.minor = gcvVERSION_MINOR; -+ Interface->u.Version.patch = gcvVERSION_PATCH; -+ Interface->u.Version.build = gcvVERSION_BUILD; -+#if gcmIS_DEBUG(gcdDEBUG_TRACE) -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_KERNEL, -+ "KERNEL version %d.%d.%d build %u %s", -+ gcvVERSION_MAJOR, gcvVERSION_MINOR, gcvVERSION_PATCH, -+ gcvVERSION_BUILD, utsname()->version); -+#endif -+ break; -+ -+ case gcvHAL_CHIP_INFO: -+ /* Only if not support multi-core */ -+ Interface->u.ChipInfo.count = 1; -+ Interface->u.ChipInfo.types[0] = Kernel->hardware->type; -+ break; -+ -+#if (gcdENABLE_3D || gcdENABLE_2D) -+ case gcvHAL_ATTACH: -+ /* Attach user process. */ -+ gcmkONERROR( -+ gckCOMMAND_Attach(Kernel->command, -+ &context, -+ &bytes, -+ processID)); -+ -+ Interface->u.Attach.stateCount = bytes; -+ Interface->u.Attach.context = gcmPTR_TO_NAME(context); -+ -+ if (Interface->u.Attach.map == gcvTRUE) -+ { -+ gcmkVERIFY_OK( -+ gckCONTEXT_MapBuffer(context, -+ Interface->u.Attach.physicals, -+ Interface->u.Attach.logicals, -+ &Interface->u.Attach.bytes)); -+ } -+ -+ gcmkVERIFY_OK( -+ gckKERNEL_AddProcessDB(Kernel, -+ processID, gcvDB_CONTEXT, -+ gcmINT2PTR(Interface->u.Attach.context), -+ gcvNULL, -+ 0)); -+ break; -+#endif -+ -+ case gcvHAL_DETACH: -+ gcmkVERIFY_OK( -+ gckKERNEL_RemoveProcessDB(Kernel, -+ processID, gcvDB_CONTEXT, -+ gcmINT2PTR(Interface->u.Detach.context))); -+ -+ /* Detach user process. */ -+ gcmkONERROR( -+ gckCOMMAND_Detach(Kernel->command, -+ gcmNAME_TO_PTR(Interface->u.Detach.context))); -+ -+ gcmRELEASE_NAME(Interface->u.Detach.context); -+ break; -+ -+ case gcvHAL_COMPOSE: -+ Interface->u.Compose.physical = gcmPTR_TO_UINT64(gcmNAME_TO_PTR(Interface->u.Compose.physical)); -+ /* Start composition. */ -+ gcmkONERROR( -+ gckEVENT_Compose(Kernel->eventObj, -+ &Interface->u.Compose)); -+ break; -+ -+ case gcvHAL_SET_TIMEOUT: -+ /* set timeOut value from user */ -+ gckKERNEL_SetTimeOut(Kernel, Interface->u.SetTimeOut.timeOut); -+ break; -+ -+ case gcvHAL_GET_FRAME_INFO: -+ gcmkONERROR(gckHARDWARE_GetFrameInfo( -+ Kernel->hardware, -+ gcmUINT64_TO_PTR(Interface->u.GetFrameInfo.frameInfo))); -+ break; -+ -+ case gcvHAL_SET_FSCALE_VALUE: -+#if gcdENABLE_FSCALE_VAL_ADJUST -+ status = gckHARDWARE_SetFscaleValue(Kernel->hardware, -+ Interface->u.SetFscaleValue.value); -+#else -+ status = gcvSTATUS_NOT_SUPPORTED; -+#endif -+ break; -+ case gcvHAL_GET_FSCALE_VALUE: -+#if gcdENABLE_FSCALE_VAL_ADJUST -+ status = gckHARDWARE_GetFscaleValue(Kernel->hardware, -+ &Interface->u.GetFscaleValue.value, -+ &Interface->u.GetFscaleValue.minValue, -+ &Interface->u.GetFscaleValue.maxValue); -+#else -+ status = gcvSTATUS_NOT_SUPPORTED; -+#endif -+ break; -+ -+ case gcvHAL_NAME_VIDEO_MEMORY: -+ gcmkONERROR(gckVIDMEM_NODE_Name(Kernel, -+ Interface->u.NameVideoMemory.handle, -+ &Interface->u.NameVideoMemory.name)); -+ break; -+ -+ case gcvHAL_IMPORT_VIDEO_MEMORY: -+ gcmkONERROR(gckVIDMEM_NODE_Import(Kernel, -+ Interface->u.ImportVideoMemory.name, -+ &Interface->u.ImportVideoMemory.handle)); -+ -+ gcmkONERROR( -+ gckKERNEL_AddProcessDB(Kernel, -+ processID, gcvDB_VIDEO_MEMORY, -+ gcmINT2PTR(Interface->u.ImportVideoMemory.handle), -+ gcvNULL, -+ 0)); -+ break; -+ -+ case gcvHAL_GET_VIDEO_MEMORY_FD: -+ gcmkONERROR(gckVIDMEM_NODE_GetFd( -+ Kernel, -+ Interface->u.GetVideoMemoryFd.handle, -+ &Interface->u.GetVideoMemoryFd.fd -+ )); -+ -+ /* No need to add it to processDB because OS will release all fds when -+ ** process quits. -+ */ -+ break; -+ -+ case gcvHAL_QUERY_RESET_TIME_STAMP: -+ Interface->u.QueryResetTimeStamp.timeStamp = Kernel->resetTimeStamp; -+ break; -+ -+ case gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER: -+ buffer = (gckVIRTUAL_COMMAND_BUFFER_PTR)gcmNAME_TO_PTR(Interface->u.FreeVirtualCommandBuffer.physical); -+ -+ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB( -+ Kernel, -+ processID, -+ gcvDB_COMMAND_BUFFER, -+ gcmUINT64_TO_PTR(Interface->u.FreeVirtualCommandBuffer.logical))); -+ -+ gcmkONERROR(gckOS_DestroyUserVirtualMapping( -+ Kernel->os, -+ buffer->physical, -+ (gctSIZE_T)Interface->u.FreeVirtualCommandBuffer.bytes, -+ gcmUINT64_TO_PTR(Interface->u.FreeVirtualCommandBuffer.logical))); -+ -+ gcmkONERROR(gckKERNEL_DestroyVirtualCommandBuffer( -+ Kernel, -+ (gctSIZE_T)Interface->u.FreeVirtualCommandBuffer.bytes, -+ (gctPHYS_ADDR)buffer, -+ gcmUINT64_TO_PTR(Interface->u.FreeVirtualCommandBuffer.logical))); -+ -+ gcmRELEASE_NAME(Interface->u.FreeVirtualCommandBuffer.physical); -+ break; -+ -+#if gcdANDROID_NATIVE_FENCE_SYNC -+ case gcvHAL_SYNC_POINT: -+ { -+ gctSYNC_POINT syncPoint; -+ -+ switch (Interface->u.SyncPoint.command) -+ { -+ case gcvSYNC_POINT_CREATE: -+ gcmkONERROR(gckOS_CreateSyncPoint(Kernel->os, &syncPoint)); -+ -+ Interface->u.SyncPoint.syncPoint = gcmPTR_TO_UINT64(syncPoint); -+ -+ gcmkVERIFY_OK( -+ gckKERNEL_AddProcessDB(Kernel, -+ processID, gcvDB_SYNC_POINT, -+ syncPoint, -+ gcvNULL, -+ 0)); -+ break; -+ -+ case gcvSYNC_POINT_DESTROY: -+ syncPoint = gcmUINT64_TO_PTR(Interface->u.SyncPoint.syncPoint); -+ -+ gcmkVERIFY_OK( -+ gckKERNEL_RemoveProcessDB(Kernel, -+ processID, gcvDB_SYNC_POINT, -+ syncPoint)); -+ -+ gcmkONERROR(gckOS_DestroySyncPoint(Kernel->os, syncPoint)); -+ break; -+ -+ default: -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ break; -+ } -+ } -+ break; -+ -+ case gcvHAL_CREATE_NATIVE_FENCE: -+ { -+ gctINT fenceFD; -+ gctSYNC_POINT syncPoint = -+ gcmUINT64_TO_PTR(Interface->u.CreateNativeFence.syncPoint); -+ -+ gcmkONERROR( -+ gckOS_CreateNativeFence(Kernel->os, -+ Kernel->timeline, -+ syncPoint, -+ &fenceFD)); -+ -+ Interface->u.CreateNativeFence.fenceFD = fenceFD; -+ } -+ break; -+#endif -+ -+ case gcvHAL_SHBUF: -+ { -+ gctSHBUF shBuf; -+ gctPOINTER uData; -+ gctUINT32 bytes; -+ -+ switch (Interface->u.ShBuf.command) -+ { -+ case gcvSHBUF_CREATE: -+ bytes = Interface->u.ShBuf.bytes; -+ -+ /* Create. */ -+ gcmkONERROR(gckKERNEL_CreateShBuffer(Kernel, bytes, &shBuf)); -+ -+ Interface->u.ShBuf.id = gcmPTR_TO_UINT64(shBuf); -+ -+ gcmkVERIFY_OK( -+ gckKERNEL_AddProcessDB(Kernel, -+ processID, -+ gcvDB_SHBUF, -+ shBuf, -+ gcvNULL, -+ 0)); -+ break; -+ -+ case gcvSHBUF_DESTROY: -+ shBuf = gcmUINT64_TO_PTR(Interface->u.ShBuf.id); -+ -+ /* Check db first to avoid illegal destroy in the process. */ -+ gcmkONERROR( -+ gckKERNEL_RemoveProcessDB(Kernel, -+ processID, -+ gcvDB_SHBUF, -+ shBuf)); -+ -+ gcmkONERROR(gckKERNEL_DestroyShBuffer(Kernel, shBuf)); -+ break; -+ -+ case gcvSHBUF_MAP: -+ shBuf = gcmUINT64_TO_PTR(Interface->u.ShBuf.id); -+ -+ /* Map for current process access. */ -+ gcmkONERROR(gckKERNEL_MapShBuffer(Kernel, shBuf)); -+ -+ gcmkVERIFY_OK( -+ gckKERNEL_AddProcessDB(Kernel, -+ processID, -+ gcvDB_SHBUF, -+ shBuf, -+ gcvNULL, -+ 0)); -+ break; -+ -+ case gcvSHBUF_WRITE: -+ shBuf = gcmUINT64_TO_PTR(Interface->u.ShBuf.id); -+ uData = gcmUINT64_TO_PTR(Interface->u.ShBuf.data); -+ bytes = Interface->u.ShBuf.bytes; -+ -+ /* Write. */ -+ gcmkONERROR( -+ gckKERNEL_WriteShBuffer(Kernel, shBuf, uData, bytes)); -+ break; -+ -+ case gcvSHBUF_READ: -+ shBuf = gcmUINT64_TO_PTR(Interface->u.ShBuf.id); -+ uData = gcmUINT64_TO_PTR(Interface->u.ShBuf.data); -+ bytes = Interface->u.ShBuf.bytes; -+ -+ /* Read. */ -+ gcmkONERROR( -+ gckKERNEL_ReadShBuffer(Kernel, -+ shBuf, -+ uData, -+ bytes, -+ &bytes)); -+ -+ /* Return copied size. */ -+ Interface->u.ShBuf.bytes = bytes; -+ break; -+ -+ default: -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ break; -+ } -+ } -+ break; -+ -+ case gcvHAL_CONFIG_POWER_MANAGEMENT: -+ gcmkONERROR(gckKERNEL_ConfigPowerManagement(Kernel, Interface)); -+ break; -+ -+ default: -+ /* Invalid command. */ -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ } -+ -+OnError: -+ /* Save status. */ -+ Interface->status = status; -+ -+ if (powerMutexAcquired == gcvTRUE) -+ { -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->hardware->powerMutex)); -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** gckKERNEL_AttachProcess -+** -+** Attach or detach a process. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** gctBOOL Attach -+** gcvTRUE if a new process gets attached or gcFALSE when a process -+** gets detatched. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckKERNEL_AttachProcess( -+ IN gckKERNEL Kernel, -+ IN gctBOOL Attach -+ ) -+{ -+ gceSTATUS status; -+ gctUINT32 processID; -+ -+ gcmkHEADER_ARG("Kernel=0x%x Attach=%d", Kernel, Attach); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ -+ /* Get current process ID. */ -+ gcmkONERROR(gckOS_GetProcessID(&processID)); -+ -+ gcmkONERROR(gckKERNEL_AttachProcessEx(Kernel, Attach, processID)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** gckKERNEL_AttachProcessEx -+** -+** Attach or detach a process with the given PID. Can be paired with gckKERNEL_AttachProcess -+** provided the programmer is aware of the consequences. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** gctBOOL Attach -+** gcvTRUE if a new process gets attached or gcFALSE when a process -+** gets detatched. -+** -+** gctUINT32 PID -+** PID of the process to attach or detach. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckKERNEL_AttachProcessEx( -+ IN gckKERNEL Kernel, -+ IN gctBOOL Attach, -+ IN gctUINT32 PID -+ ) -+{ -+ gceSTATUS status; -+ gctINT32 old; -+ -+ gcmkHEADER_ARG("Kernel=0x%x Attach=%d PID=%d", Kernel, Attach, PID); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ -+ if (Attach) -+ { -+ /* Increment the number of clients attached. */ -+ gcmkONERROR( -+ gckOS_AtomIncrement(Kernel->os, Kernel->atomClients, &old)); -+ -+ if (old == 0) -+ { -+#if gcdENABLE_VG -+ if (Kernel->vg == gcvNULL) -+#endif -+ { -+ gcmkONERROR(gckOS_Broadcast(Kernel->os, -+ Kernel->hardware, -+ gcvBROADCAST_FIRST_PROCESS)); -+ } -+ } -+ -+ if (Kernel->dbCreated) -+ { -+ /* Create the process database. */ -+ gcmkONERROR(gckKERNEL_CreateProcessDB(Kernel, PID)); -+ } -+ -+#if gcdPROCESS_ADDRESS_SPACE -+ /* Map kernel command buffer in the process's own MMU. */ -+ gcmkONERROR(_MapCommandBuffer(Kernel)); -+#endif -+ } -+ else -+ { -+ if (Kernel->dbCreated) -+ { -+ /* Clean up the process database. */ -+ gcmkONERROR(gckKERNEL_DestroyProcessDB(Kernel, PID)); -+ -+ /* Save the last know process ID. */ -+ Kernel->db->lastProcessID = PID; -+ } -+ -+#if gcdENABLE_VG -+ if (Kernel->vg == gcvNULL) -+#endif -+ { -+ status = gckEVENT_Submit(Kernel->eventObj, gcvTRUE, gcvFALSE, gcvFALSE); -+ -+ if (status == gcvSTATUS_INTERRUPTED && Kernel->eventObj->submitTimer) -+ { -+ gcmkONERROR(gckOS_StartTimer(Kernel->os, -+ Kernel->eventObj->submitTimer, -+ 1)); -+ } -+ else -+ { -+ gcmkONERROR(status); -+ } -+ } -+ -+ /* Decrement the number of clients attached. */ -+ gcmkONERROR( -+ gckOS_AtomDecrement(Kernel->os, Kernel->atomClients, &old)); -+ -+ if (old == 1) -+ { -+#if gcdENABLE_VG -+ if (Kernel->vg == gcvNULL) -+#endif -+ { -+ /* Last client detached, switch to SUSPEND power state. */ -+ gcmkONERROR(gckOS_Broadcast(Kernel->os, -+ Kernel->hardware, -+ gcvBROADCAST_LAST_PROCESS)); -+ } -+ -+ /* Flush the debug cache. */ -+ gcmkDEBUGFLUSH(~0U); -+ } -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckKERNEL_Recovery -+** -+** Try to recover the GPU from a fatal error. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckKERNEL_Recovery( -+ IN gckKERNEL Kernel -+ ) -+{ -+ gceSTATUS status; -+ gckEVENT eventObj; -+ gckHARDWARE hardware; -+ gctUINT32 mask = 0; -+ gckCOMMAND command; -+ gckENTRYDATA data; -+ gctUINT32 i = 0, count = 0; -+#if gcdINTERRUPT_STATISTIC -+ gctINT32 oldValue; -+#endif -+ -+ gcmkHEADER_ARG("Kernel=0x%x", Kernel); -+ -+ /* Validate the arguemnts. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ -+ /* Grab gckEVENT object. */ -+ eventObj = Kernel->eventObj; -+ gcmkVERIFY_OBJECT(eventObj, gcvOBJ_EVENT); -+ -+ /* Grab gckHARDWARE object. */ -+ hardware = Kernel->hardware; -+ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE); -+ -+ /* Grab gckCOMMAND object. */ -+ command = Kernel->command; -+ gcmkVERIFY_OBJECT(command, gcvOBJ_COMMAND); -+ -+ if (Kernel->stuckDump == gcdSTUCK_DUMP_MINIMAL) -+ { -+ gcmkPRINT("[galcore]: GPU[%d] hang, automatic recovery.", Kernel->core); -+ } -+ else -+ { -+ _DumpDriverConfigure(Kernel); -+ _DumpState(Kernel); -+ } -+ -+ if (Kernel->recovery == gcvFALSE) -+ { -+ gcmkPRINT("[galcore]: Stop driver to keep scene."); -+ -+ for (;;) -+ { -+ gckOS_Delay(Kernel->os, 10000); -+ } -+ } -+ -+ /* Clear queue. */ -+ do -+ { -+ status = gckENTRYQUEUE_Dequeue(&command->queue, &data); -+ } -+ while (status == gcvSTATUS_OK); -+ -+ /* Issuing a soft reset for the GPU. */ -+ gcmkONERROR(gckHARDWARE_Reset(hardware)); -+ -+ mask = Kernel->restoreMask; -+ -+ for (i = 0; i < 32; i++) -+ { -+ if (mask & (1 << i)) -+ { -+ count++; -+ } -+ } -+ -+ /* Handle all outstanding events now. */ -+#if gcdSMP -+ gcmkONERROR(gckOS_AtomSet(Kernel->os, eventObj->pending, mask)); -+#else -+ eventObj->pending = mask; -+#endif -+ -+#if gcdINTERRUPT_STATISTIC -+ while (count--) -+ { -+ gcmkONERROR(gckOS_AtomDecrement( -+ Kernel->os, -+ eventObj->interruptCount, -+ &oldValue -+ )); -+ } -+ -+ gckOS_AtomClearMask(Kernel->hardware->pendingEvent, mask); -+#endif -+ -+ gcmkONERROR(gckEVENT_Notify(eventObj, 1)); -+ -+ gcmkVERIFY_OK(gckOS_GetTime(&Kernel->resetTimeStamp)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckKERNEL_OpenUserData -+** -+** Get access to the user data. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** gctBOOL NeedCopy -+** The flag indicating whether or not the data should be copied. -+** -+** gctPOINTER StaticStorage -+** Pointer to the kernel storage where the data is to be copied if -+** NeedCopy is gcvTRUE. -+** -+** gctPOINTER UserPointer -+** User pointer to the data. -+** -+** gctSIZE_T Size -+** Size of the data. -+** -+** OUTPUT: -+** -+** gctPOINTER * KernelPointer -+** Pointer to the kernel pointer that will be pointing to the data. -+*/ -+gceSTATUS -+gckKERNEL_OpenUserData( -+ IN gckKERNEL Kernel, -+ IN gctBOOL NeedCopy, -+ IN gctPOINTER StaticStorage, -+ IN gctPOINTER UserPointer, -+ IN gctSIZE_T Size, -+ OUT gctPOINTER * KernelPointer -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG( -+ "Kernel=0x%08X NeedCopy=%d StaticStorage=0x%08X " -+ "UserPointer=0x%08X Size=%lu KernelPointer=0x%08X", -+ Kernel, NeedCopy, StaticStorage, UserPointer, Size, KernelPointer -+ ); -+ -+ /* Validate the arguemnts. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ gcmkVERIFY_ARGUMENT(!NeedCopy || (StaticStorage != gcvNULL)); -+ gcmkVERIFY_ARGUMENT(UserPointer != gcvNULL); -+ gcmkVERIFY_ARGUMENT(KernelPointer != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Size > 0); -+ -+ if (NeedCopy) -+ { -+ /* Copy the user data to the static storage. */ -+ gcmkONERROR(gckOS_CopyFromUserData( -+ Kernel->os, StaticStorage, UserPointer, Size -+ )); -+ -+ /* Set the kernel pointer. */ -+ * KernelPointer = StaticStorage; -+ } -+ else -+ { -+ gctPOINTER pointer = gcvNULL; -+ -+ /* Map the user pointer. */ -+ gcmkONERROR(gckOS_MapUserPointer( -+ Kernel->os, UserPointer, Size, &pointer -+ )); -+ -+ /* Set the kernel pointer. */ -+ * KernelPointer = pointer; -+ } -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckKERNEL_CloseUserData -+** -+** Release resources associated with the user data connection opened by -+** gckKERNEL_OpenUserData. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** gctBOOL NeedCopy -+** The flag indicating whether or not the data should be copied. -+** -+** gctBOOL FlushData -+** If gcvTRUE, the data is written back to the user. -+** -+** gctPOINTER UserPointer -+** User pointer to the data. -+** -+** gctSIZE_T Size -+** Size of the data. -+** -+** OUTPUT: -+** -+** gctPOINTER * KernelPointer -+** Kernel pointer to the data. -+*/ -+gceSTATUS -+gckKERNEL_CloseUserData( -+ IN gckKERNEL Kernel, -+ IN gctBOOL NeedCopy, -+ IN gctBOOL FlushData, -+ IN gctPOINTER UserPointer, -+ IN gctSIZE_T Size, -+ OUT gctPOINTER * KernelPointer -+ ) -+{ -+ gceSTATUS status = gcvSTATUS_OK; -+ gctPOINTER pointer; -+ -+ gcmkHEADER_ARG( -+ "Kernel=0x%08X NeedCopy=%d FlushData=%d " -+ "UserPointer=0x%08X Size=%lu KernelPointer=0x%08X", -+ Kernel, NeedCopy, FlushData, UserPointer, Size, KernelPointer -+ ); -+ -+ /* Validate the arguemnts. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ gcmkVERIFY_ARGUMENT(UserPointer != gcvNULL); -+ gcmkVERIFY_ARGUMENT(KernelPointer != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Size > 0); -+ -+ /* Get a shortcut to the kernel pointer. */ -+ pointer = * KernelPointer; -+ -+ if (pointer != gcvNULL) -+ { -+ if (NeedCopy) -+ { -+ if (FlushData) -+ { -+ gcmkONERROR(gckOS_CopyToUserData( -+ Kernel->os, * KernelPointer, UserPointer, Size -+ )); -+ } -+ } -+ else -+ { -+ /* Unmap record from kernel memory. */ -+ gcmkONERROR(gckOS_UnmapUserPointer( -+ Kernel->os, -+ UserPointer, -+ Size, -+ * KernelPointer -+ )); -+ } -+ -+ /* Reset the kernel pointer. */ -+ * KernelPointer = gcvNULL; -+ } -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+void -+gckKERNEL_SetTimeOut( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 timeOut -+ ) -+{ -+ gcmkHEADER_ARG("Kernel=0x%x timeOut=%d", Kernel, timeOut); -+#if gcdGPU_TIMEOUT -+ Kernel->timeOut = timeOut; -+#endif -+ gcmkFOOTER_NO(); -+} -+ -+gceSTATUS -+gckKERNEL_AllocateVirtualCommandBuffer( -+ IN gckKERNEL Kernel, -+ IN gctBOOL InUserSpace, -+ IN OUT gctSIZE_T * Bytes, -+ OUT gctPHYS_ADDR * Physical, -+ OUT gctPOINTER * Logical -+ ) -+{ -+ gckOS os = Kernel->os; -+ gceSTATUS status; -+ gctPOINTER logical = gcvNULL; -+ gctSIZE_T pageCount; -+ gctSIZE_T bytes = *Bytes; -+ gckVIRTUAL_COMMAND_BUFFER_PTR buffer = gcvNULL; -+ gckMMU mmu; -+ gctUINT32 flag = gcvALLOC_FLAG_NON_CONTIGUOUS; -+ -+ gcmkHEADER_ARG("Os=0x%X InUserSpace=%d *Bytes=%lu", -+ os, InUserSpace, gcmOPT_VALUE(Bytes)); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Bytes != gcvNULL); -+ gcmkVERIFY_ARGUMENT(*Bytes > 0); -+ gcmkVERIFY_ARGUMENT(Physical != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Logical != gcvNULL); -+ -+ gcmkONERROR(gckOS_Allocate(os, -+ sizeof(gckVIRTUAL_COMMAND_BUFFER), -+ (gctPOINTER)&buffer)); -+ -+ gcmkONERROR(gckOS_ZeroMemory(buffer, sizeof(gckVIRTUAL_COMMAND_BUFFER))); -+ -+ buffer->bytes = bytes; -+ -+ gcmkONERROR(gckOS_AllocatePagedMemoryEx(os, -+ flag, -+ bytes, -+ gcvNULL, -+ &buffer->physical)); -+ -+ if (InUserSpace) -+ { -+ gcmkONERROR(gckOS_CreateUserVirtualMapping(os, -+ buffer->physical, -+ bytes, -+ &logical, -+ &pageCount)); -+ -+ *Logical = -+ buffer->userLogical = logical; -+ } -+ else -+ { -+ gcmkONERROR(gckOS_CreateKernelVirtualMapping(os, -+ buffer->physical, -+ bytes, -+ &logical, -+ &pageCount)); -+ -+ *Logical = -+ buffer->kernelLogical = logical; -+ } -+ -+ buffer->pageCount = pageCount; -+ buffer->kernel = Kernel; -+ -+ gcmkONERROR(gckOS_GetProcessID(&buffer->pid)); -+ -+#if gcdPROCESS_ADDRESS_SPACE -+ gcmkONERROR(gckKERNEL_GetProcessMMU(Kernel, &mmu)); -+ buffer->mmu = mmu; -+#else -+ mmu = Kernel->mmu; -+#endif -+ -+ gcmkONERROR(gckMMU_AllocatePages(mmu, -+ pageCount, -+ &buffer->pageTable, -+ &buffer->gpuAddress)); -+ -+ -+ gcmkONERROR(gckOS_MapPagesEx(os, -+ Kernel->core, -+ buffer->physical, -+ pageCount, -+ buffer->gpuAddress, -+ buffer->pageTable)); -+ -+ gcmkONERROR(gckMMU_Flush(mmu, gcvSURF_INDEX)); -+ -+ *Physical = buffer; -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_KERNEL, -+ "gpuAddress = %x pageCount = %d kernelLogical = %x userLogical=%x", -+ buffer->gpuAddress, buffer->pageCount, -+ buffer->kernelLogical, buffer->userLogical); -+ -+ gcmkVERIFY_OK(gckOS_AcquireMutex(os, Kernel->virtualBufferLock, gcvINFINITE)); -+ -+ if (Kernel->virtualBufferHead == gcvNULL) -+ { -+ Kernel->virtualBufferHead = -+ Kernel->virtualBufferTail = buffer; -+ } -+ else -+ { -+ buffer->prev = Kernel->virtualBufferTail; -+ Kernel->virtualBufferTail->next = buffer; -+ Kernel->virtualBufferTail = buffer; -+ } -+ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, Kernel->virtualBufferLock)); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (buffer->gpuAddress) -+ { -+#if gcdPROCESS_ADDRESS_SPACE -+ gcmkVERIFY_OK( -+ gckMMU_FreePages(mmu, buffer->pageTable, buffer->pageCount)); -+#else -+ gcmkVERIFY_OK( -+ gckMMU_FreePages(Kernel->mmu, buffer->pageTable, buffer->pageCount)); -+#endif -+ } -+ -+ if (buffer->userLogical) -+ { -+ gcmkVERIFY_OK( -+ gckOS_DestroyUserVirtualMapping(os, -+ buffer->physical, -+ bytes, -+ buffer->userLogical)); -+ } -+ -+ if (buffer->kernelLogical) -+ { -+ gcmkVERIFY_OK( -+ gckOS_DestroyKernelVirtualMapping(os, -+ buffer->physical, -+ bytes, -+ buffer->kernelLogical)); -+ } -+ -+ if (buffer->physical) -+ { -+ gcmkVERIFY_OK(gckOS_FreePagedMemory(os, buffer->physical, bytes)); -+ } -+ -+ gcmkVERIFY_OK(gckOS_Free(os, buffer)); -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckKERNEL_DestroyVirtualCommandBuffer( -+ IN gckKERNEL Kernel, -+ IN gctSIZE_T Bytes, -+ IN gctPHYS_ADDR Physical, -+ IN gctPOINTER Logical -+ ) -+{ -+ gckOS os; -+ gckKERNEL kernel; -+ gckVIRTUAL_COMMAND_BUFFER_PTR buffer = (gckVIRTUAL_COMMAND_BUFFER_PTR)Physical; -+ -+ gcmkHEADER(); -+ gcmkVERIFY_ARGUMENT(buffer != gcvNULL); -+ -+ kernel = buffer->kernel; -+ os = kernel->os; -+ -+ if (!buffer->userLogical) -+ { -+ gcmkVERIFY_OK(gckOS_DestroyKernelVirtualMapping(os, -+ buffer->physical, -+ Bytes, -+ Logical)); -+ } -+ -+#if !gcdPROCESS_ADDRESS_SPACE -+ gcmkVERIFY_OK( -+ gckMMU_FreePages(kernel->mmu, buffer->pageTable, buffer->pageCount)); -+#endif -+ -+ gcmkVERIFY_OK(gckOS_UnmapPages(os, buffer->pageCount, buffer->gpuAddress)); -+ -+ gcmkVERIFY_OK(gckOS_FreePagedMemory(os, buffer->physical, Bytes)); -+ -+ gcmkVERIFY_OK(gckOS_AcquireMutex(os, kernel->virtualBufferLock, gcvINFINITE)); -+ -+ if (buffer == kernel->virtualBufferHead) -+ { -+ if ((kernel->virtualBufferHead = buffer->next) == gcvNULL) -+ { -+ kernel->virtualBufferTail = gcvNULL; -+ } -+ } -+ else -+ { -+ buffer->prev->next = buffer->next; -+ -+ if (buffer == kernel->virtualBufferTail) -+ { -+ kernel->virtualBufferTail = buffer->prev; -+ } -+ else -+ { -+ buffer->next->prev = buffer->prev; -+ } -+ } -+ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, kernel->virtualBufferLock)); -+ -+ gcmkVERIFY_OK(gckOS_Free(os, buffer)); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckKERNEL_GetGPUAddress( -+ IN gckKERNEL Kernel, -+ IN gctPOINTER Logical, -+ IN gctBOOL InUserSpace, -+ OUT gctUINT32 * Address -+ ) -+{ -+ gceSTATUS status; -+ gckVIRTUAL_COMMAND_BUFFER_PTR buffer; -+ gctPOINTER start; -+ gctUINT32 pid; -+ -+ gcmkHEADER_ARG("Logical = %x InUserSpace=%d.", Logical, InUserSpace); -+ -+ gcmkVERIFY_OK(gckOS_GetProcessID(&pid)); -+ -+ status = gcvSTATUS_INVALID_ADDRESS; -+ -+ gcmkVERIFY_OK(gckOS_AcquireMutex(Kernel->os, Kernel->virtualBufferLock, gcvINFINITE)); -+ -+ /* Walk all command buffer. */ -+ for (buffer = Kernel->virtualBufferHead; buffer != gcvNULL; buffer = buffer->next) -+ { -+ if (InUserSpace) -+ { -+ start = buffer->userLogical; -+ } -+ else -+ { -+ start = buffer->kernelLogical; -+ } -+ -+ if (start == gcvNULL) -+ { -+ continue; -+ } -+ -+ if (Logical >= start -+ && (Logical < (gctPOINTER)((gctUINT8_PTR)start + buffer->pageCount * 4096)) -+ && pid == buffer->pid -+ ) -+ { -+ * Address = buffer->gpuAddress + (gctUINT32)((gctUINT8_PTR)Logical - (gctUINT8_PTR)start); -+ status = gcvSTATUS_OK; -+ break; -+ } -+ } -+ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->virtualBufferLock)); -+ -+ gcmkFOOTER_NO(); -+ return status; -+} -+ -+gceSTATUS -+gckKERNEL_QueryGPUAddress( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 GpuAddress, -+ OUT gckVIRTUAL_COMMAND_BUFFER_PTR * Buffer -+ ) -+{ -+ gckVIRTUAL_COMMAND_BUFFER_PTR buffer; -+ gctUINT32 start; -+ gceSTATUS status = gcvSTATUS_NOT_SUPPORTED; -+ -+ gcmkVERIFY_OK(gckOS_AcquireMutex(Kernel->os, Kernel->virtualBufferLock, gcvINFINITE)); -+ -+ /* Walk all command buffers. */ -+ for (buffer = Kernel->virtualBufferHead; buffer != gcvNULL; buffer = buffer->next) -+ { -+ start = (gctUINT32)buffer->gpuAddress; -+ -+ if (GpuAddress >= start && GpuAddress < (start + buffer->pageCount * 4096)) -+ { -+ /* Find a range matched. */ -+ *Buffer = buffer; -+ status = gcvSTATUS_OK; -+ break; -+ } -+ } -+ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->virtualBufferLock)); -+ -+ return status; -+} -+ -+#if gcdLINK_QUEUE_SIZE -+static void -+gckLINKQUEUE_Dequeue( -+ IN gckLINKQUEUE LinkQueue -+ ) -+{ -+ gcmkASSERT(LinkQueue->count == gcdLINK_QUEUE_SIZE); -+ -+ LinkQueue->count--; -+ LinkQueue->front = (LinkQueue->front + 1) % gcdLINK_QUEUE_SIZE; -+} -+ -+void -+gckLINKQUEUE_Enqueue( -+ IN gckLINKQUEUE LinkQueue, -+ IN gctUINT32 start, -+ IN gctUINT32 end -+ ) -+{ -+ if (LinkQueue->count == gcdLINK_QUEUE_SIZE) -+ { -+ gckLINKQUEUE_Dequeue(LinkQueue); -+ } -+ -+ gcmkASSERT(LinkQueue->count < gcdLINK_QUEUE_SIZE); -+ -+ LinkQueue->count++; -+ -+ LinkQueue->data[LinkQueue->rear].start = start; -+ LinkQueue->data[LinkQueue->rear].end = end; -+ -+ gcmkVERIFY_OK( -+ gckOS_GetProcessID(&LinkQueue->data[LinkQueue->rear].pid)); -+ -+ LinkQueue->rear = (LinkQueue->rear + 1) % gcdLINK_QUEUE_SIZE; -+} -+ -+void -+gckLINKQUEUE_GetData( -+ IN gckLINKQUEUE LinkQueue, -+ IN gctUINT32 Index, -+ OUT gckLINKDATA * Data -+ ) -+{ -+ gcmkASSERT(Index >= 0 && Index < gcdLINK_QUEUE_SIZE); -+ -+ *Data = &LinkQueue->data[(Index + LinkQueue->front) % gcdLINK_QUEUE_SIZE]; -+} -+#endif -+ -+/* -+* gckENTRYQUEUE_Enqueue is called with Command->mutexQueue acquired. -+*/ -+gceSTATUS -+gckENTRYQUEUE_Enqueue( -+ IN gckKERNEL Kernel, -+ IN gckENTRYQUEUE Queue, -+ IN gctUINT32 physical, -+ IN gctUINT32 bytes -+ ) -+{ -+ gctUINT32 next = (Queue->rear + 1) % gcdENTRY_QUEUE_SIZE; -+ -+ if (next == Queue->front) -+ { -+ /* Queue is full. */ -+ return gcvSTATUS_INVALID_REQUEST; -+ } -+ -+ /* Copy data. */ -+ Queue->data[Queue->rear].physical = physical; -+ Queue->data[Queue->rear].bytes = bytes; -+ -+ gcmkVERIFY_OK(gckOS_MemoryBarrier(Kernel->os, &Queue->rear)); -+ -+ /* Update rear. */ -+ Queue->rear = next; -+ -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckENTRYQUEUE_Dequeue( -+ IN gckENTRYQUEUE Queue, -+ OUT gckENTRYDATA * Data -+ ) -+{ -+ if (Queue->front == Queue->rear) -+ { -+ /* Queue is empty. */ -+ return gcvSTATUS_INVALID_REQUEST; -+ } -+ -+ /* Copy data. */ -+ *Data = &Queue->data[Queue->front]; -+ -+ /* Update front. */ -+ Queue->front = (Queue->front + 1) % gcdENTRY_QUEUE_SIZE; -+ -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************\ -+*************************** Pointer - ID translation *************************** -+\******************************************************************************/ -+#define gcdID_TABLE_LENGTH 1024 -+typedef struct _gcsINTEGERDB * gckINTEGERDB; -+typedef struct _gcsINTEGERDB -+{ -+ gckOS os; -+ gctPOINTER* table; -+ gctPOINTER mutex; -+ gctUINT32 tableLen; -+ gctUINT32 currentID; -+ gctUINT32 unused; -+} -+gcsINTEGERDB; -+ -+gceSTATUS -+gckKERNEL_CreateIntegerDatabase( -+ IN gckKERNEL Kernel, -+ OUT gctPOINTER * Database -+ ) -+{ -+ gceSTATUS status; -+ gckINTEGERDB database = gcvNULL; -+ -+ gcmkHEADER_ARG("Kernel=0x%08X Datbase=0x%08X", Kernel, Database); -+ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ gcmkVERIFY_ARGUMENT(Database != gcvNULL); -+ -+ /* Allocate a database. */ -+ gcmkONERROR(gckOS_Allocate( -+ Kernel->os, gcmSIZEOF(gcsINTEGERDB), (gctPOINTER *)&database)); -+ -+ gcmkONERROR(gckOS_ZeroMemory(database, gcmSIZEOF(gcsINTEGERDB))); -+ -+ /* Allocate a pointer table. */ -+ gcmkONERROR(gckOS_Allocate( -+ Kernel->os, gcmSIZEOF(gctPOINTER) * gcdID_TABLE_LENGTH, (gctPOINTER *)&database->table)); -+ -+ gcmkONERROR(gckOS_ZeroMemory(database->table, gcmSIZEOF(gctPOINTER) * gcdID_TABLE_LENGTH)); -+ -+ /* Allocate a database mutex. */ -+ gcmkONERROR(gckOS_CreateMutex(Kernel->os, &database->mutex)); -+ -+ /* Initialize. */ -+ database->currentID = 0; -+ database->unused = gcdID_TABLE_LENGTH; -+ database->os = Kernel->os; -+ database->tableLen = gcdID_TABLE_LENGTH; -+ -+ *Database = database; -+ -+ gcmkFOOTER_ARG("*Database=0x%08X", *Database); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Rollback. */ -+ if (database) -+ { -+ if (database->table) -+ { -+ gcmkOS_SAFE_FREE(Kernel->os, database->table); -+ } -+ -+ gcmkOS_SAFE_FREE(Kernel->os, database); -+ } -+ -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckKERNEL_DestroyIntegerDatabase( -+ IN gckKERNEL Kernel, -+ IN gctPOINTER Database -+ ) -+{ -+ gckINTEGERDB database = Database; -+ -+ gcmkHEADER_ARG("Kernel=0x%08X Datbase=0x%08X", Kernel, Database); -+ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ gcmkVERIFY_ARGUMENT(Database != gcvNULL); -+ -+ /* Destroy pointer table. */ -+ gcmkOS_SAFE_FREE(Kernel->os, database->table); -+ -+ /* Destroy database mutex. */ -+ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, database->mutex)); -+ -+ /* Destroy database. */ -+ gcmkOS_SAFE_FREE(Kernel->os, database); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckKERNEL_AllocateIntegerId( -+ IN gctPOINTER Database, -+ IN gctPOINTER Pointer, -+ OUT gctUINT32 * Id -+ ) -+{ -+ gceSTATUS status; -+ gckINTEGERDB database = Database; -+ gctUINT32 i, unused, currentID, tableLen; -+ gctPOINTER * table; -+ gckOS os = database->os; -+ gctBOOL acquired = gcvFALSE; -+ -+ gcmkHEADER_ARG("Database=0x%08X Pointer=0x%08X", Database, Pointer); -+ -+ gcmkVERIFY_ARGUMENT(Id != gcvNULL); -+ -+ gcmkVERIFY_OK(gckOS_AcquireMutex(os, database->mutex, gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ if (database->unused < 1) -+ { -+ /* Extend table. */ -+ gcmkONERROR( -+ gckOS_Allocate(os, -+ gcmSIZEOF(gctPOINTER) * (database->tableLen + gcdID_TABLE_LENGTH), -+ (gctPOINTER *)&table)); -+ -+ gcmkONERROR(gckOS_ZeroMemory(table + database->tableLen, -+ gcmSIZEOF(gctPOINTER) * gcdID_TABLE_LENGTH)); -+ -+ /* Copy data from old table. */ -+ gckOS_MemCopy(table, -+ database->table, -+ database->tableLen * gcmSIZEOF(gctPOINTER)); -+ -+ gcmkOS_SAFE_FREE(os, database->table); -+ -+ /* Update databse with new allocated table. */ -+ database->table = table; -+ database->currentID = database->tableLen; -+ database->tableLen += gcdID_TABLE_LENGTH; -+ database->unused += gcdID_TABLE_LENGTH; -+ } -+ -+ table = database->table; -+ currentID = database->currentID; -+ tableLen = database->tableLen; -+ unused = database->unused; -+ -+ /* Connect id with pointer. */ -+ table[currentID] = Pointer; -+ -+ *Id = currentID + 1; -+ -+ /* Update the currentID. */ -+ if (--unused > 0) -+ { -+ for (i = 0; i < tableLen; i++) -+ { -+ if (++currentID >= tableLen) -+ { -+ /* Wrap to the begin. */ -+ currentID = 0; -+ } -+ -+ if (table[currentID] == gcvNULL) -+ { -+ break; -+ } -+ } -+ } -+ -+ database->table = table; -+ database->currentID = currentID; -+ database->tableLen = tableLen; -+ database->unused = unused; -+ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, database->mutex)); -+ acquired = gcvFALSE; -+ -+ gcmkFOOTER_ARG("*Id=%d", *Id); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (acquired) -+ { -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, database->mutex)); -+ } -+ -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckKERNEL_FreeIntegerId( -+ IN gctPOINTER Database, -+ IN gctUINT32 Id -+ ) -+{ -+ gceSTATUS status; -+ gckINTEGERDB database = Database; -+ gckOS os = database->os; -+ gctBOOL acquired = gcvFALSE; -+ -+ gcmkHEADER_ARG("Database=0x%08X Id=%d", Database, Id); -+ -+ gcmkVERIFY_OK(gckOS_AcquireMutex(os, database->mutex, gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ if (!(Id > 0 && Id <= database->tableLen)) -+ { -+ gcmkONERROR(gcvSTATUS_NOT_FOUND); -+ } -+ -+ Id -= 1; -+ -+ database->table[Id] = gcvNULL; -+ -+ if (database->unused++ == 0) -+ { -+ database->currentID = Id; -+ } -+ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, database->mutex)); -+ acquired = gcvFALSE; -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (acquired) -+ { -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, database->mutex)); -+ } -+ -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckKERNEL_QueryIntegerId( -+ IN gctPOINTER Database, -+ IN gctUINT32 Id, -+ OUT gctPOINTER * Pointer -+ ) -+{ -+ gceSTATUS status; -+ gckINTEGERDB database = Database; -+ gctPOINTER pointer; -+ gckOS os = database->os; -+ gctBOOL acquired = gcvFALSE; -+ -+ gcmkHEADER_ARG("Database=0x%08X Id=%d", Database, Id); -+ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL); -+ -+ gcmkVERIFY_OK(gckOS_AcquireMutex(os, database->mutex, gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ if (!(Id > 0 && Id <= database->tableLen)) -+ { -+ gcmkONERROR(gcvSTATUS_NOT_FOUND); -+ } -+ -+ Id -= 1; -+ -+ pointer = database->table[Id]; -+ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, database->mutex)); -+ acquired = gcvFALSE; -+ -+ if (pointer) -+ { -+ *Pointer = pointer; -+ } -+ else -+ { -+ gcmkONERROR(gcvSTATUS_NOT_FOUND); -+ } -+ -+ gcmkFOOTER_ARG("*Pointer=0x%08X", *Pointer); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (acquired) -+ { -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, database->mutex)); -+ } -+ -+ gcmkFOOTER(); -+ return status; -+} -+ -+ -+gctUINT32 -+gckKERNEL_AllocateNameFromPointer( -+ IN gckKERNEL Kernel, -+ IN gctPOINTER Pointer -+ ) -+{ -+ gceSTATUS status; -+ gctUINT32 name; -+ gctPOINTER database = Kernel->db->pointerDatabase; -+ -+ gcmkHEADER_ARG("Kernel=0x%X Pointer=0x%X", Kernel, Pointer); -+ -+ gcmkONERROR( -+ gckKERNEL_AllocateIntegerId(database, Pointer, &name)); -+ -+ gcmkFOOTER_ARG("name=%d", name); -+ return name; -+ -+OnError: -+ gcmkFOOTER(); -+ return 0; -+} -+ -+gctPOINTER -+gckKERNEL_QueryPointerFromName( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 Name -+ ) -+{ -+ gceSTATUS status; -+ gctPOINTER pointer = gcvNULL; -+ gctPOINTER database = Kernel->db->pointerDatabase; -+ -+ gcmkHEADER_ARG("Kernel=0x%X Name=%d", Kernel, Name); -+ -+ /* Lookup in database to get pointer. */ -+ gcmkONERROR(gckKERNEL_QueryIntegerId(database, Name, &pointer)); -+ -+ gcmkFOOTER_ARG("pointer=0x%X", pointer); -+ return pointer; -+ -+OnError: -+ gcmkFOOTER(); -+ return gcvNULL; -+} -+ -+gceSTATUS -+gckKERNEL_DeleteName( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 Name -+ ) -+{ -+ gctPOINTER database = Kernel->db->pointerDatabase; -+ -+ gcmkHEADER_ARG("Kernel=0x%X Name=0x%X", Kernel, Name); -+ -+ /* Free name if exists. */ -+ gcmkVERIFY_OK(gckKERNEL_FreeIntegerId(database, Name)); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckKERNEL_SetRecovery( -+ IN gckKERNEL Kernel, -+ IN gctBOOL Recovery, -+ IN gctUINT32 StuckDump -+ ) -+{ -+ Kernel->recovery = Recovery; -+ -+ if (Recovery == gcvFALSE) -+ { -+ /* Dump stuck information if Recovery is disabled. */ -+ Kernel->stuckDump = gcmMAX(StuckDump, gcdSTUCK_DUMP_MIDDLE); -+ } -+ -+ return gcvSTATUS_OK; -+} -+ -+ -+/******************************************************************************* -+***** Shared Buffer ************************************************************ -+*******************************************************************************/ -+ -+/******************************************************************************* -+** -+** gckKERNEL_CreateShBuffer -+** -+** Create shared buffer. -+** The shared buffer can be used across processes. Other process needs call -+** gckKERNEL_MapShBuffer before use it. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** gctUINT32 Size -+** Specify the shared buffer size. -+** -+** OUTPUT: -+** -+** gctSHBUF * ShBuf -+** Pointer to hold return shared buffer handle. -+*/ -+gceSTATUS -+gckKERNEL_CreateShBuffer( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 Size, -+ OUT gctSHBUF * ShBuf -+ ) -+{ -+ gceSTATUS status; -+ gcsSHBUF_PTR shBuf = gcvNULL; -+ -+ gcmkHEADER_ARG("Kernel=0x%X, Size=%u", Kernel, Size); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ -+ if (Size == 0) -+ { -+ /* Invalid size. */ -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ } -+ else if (Size > 1024) -+ { -+ /* Limite shared buffer size. */ -+ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES); -+ } -+ -+ /* Create a shared buffer structure. */ -+ gcmkONERROR( -+ gckOS_Allocate(Kernel->os, -+ sizeof (gcsSHBUF), -+ (gctPOINTER *)&shBuf)); -+ -+ /* Initialize shared buffer. */ -+ shBuf->id = 0; -+ shBuf->reference = gcvNULL; -+ shBuf->size = Size; -+ shBuf->data = gcvNULL; -+ -+ /* Allocate integer id for this shared buffer. */ -+ gcmkONERROR( -+ gckKERNEL_AllocateIntegerId(Kernel->db->pointerDatabase, -+ shBuf, -+ &shBuf->id)); -+ -+ /* Allocate atom. */ -+ gcmkONERROR(gckOS_AtomConstruct(Kernel->os, &shBuf->reference)); -+ -+ /* Set default reference count to 1. */ -+ gcmkVERIFY_OK(gckOS_AtomSet(Kernel->os, shBuf->reference, 1)); -+ -+ /* Return integer id. */ -+ *ShBuf = (gctSHBUF)(gctUINTPTR_T)shBuf->id; -+ -+ gcmkFOOTER_ARG("*ShBuf=%u", shBuf->id); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Error roll back. */ -+ if (shBuf != gcvNULL) -+ { -+ if (shBuf->id != 0) -+ { -+ gcmkVERIFY_OK( -+ gckKERNEL_FreeIntegerId(Kernel->db->pointerDatabase, -+ shBuf->id)); -+ } -+ -+ gcmkOS_SAFE_FREE(Kernel->os, shBuf); -+ } -+ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckKERNEL_DestroyShBuffer -+** -+** Destroy shared buffer. -+** This will decrease reference of specified shared buffer and do actual -+** destroy when no reference on it. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** gctSHBUF ShBuf -+** Specify the shared buffer to be destroyed. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckKERNEL_DestroyShBuffer( -+ IN gckKERNEL Kernel, -+ IN gctSHBUF ShBuf -+ ) -+{ -+ gceSTATUS status; -+ gcsSHBUF_PTR shBuf; -+ gctINT32 oldValue = 0; -+ gctBOOL acquired = gcvFALSE; -+ -+ gcmkHEADER_ARG("Kernel=0x%X ShBuf=%u", -+ Kernel, (gctUINT32)(gctUINTPTR_T) ShBuf); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ gcmkVERIFY_ARGUMENT(ShBuf != gcvNULL); -+ -+ /* Acquire mutex. */ -+ gcmkONERROR( -+ gckOS_AcquireMutex(Kernel->os, -+ Kernel->db->pointerDatabaseMutex, -+ gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ /* Find shared buffer structure. */ -+ gcmkONERROR( -+ gckKERNEL_QueryIntegerId(Kernel->db->pointerDatabase, -+ (gctUINT32)(gctUINTPTR_T)ShBuf, -+ (gctPOINTER)&shBuf)); -+ -+ gcmkASSERT(shBuf->id == (gctUINT32)(gctUINTPTR_T)ShBuf); -+ -+ /* Decrease the reference count. */ -+ gckOS_AtomDecrement(Kernel->os, shBuf->reference, &oldValue); -+ -+ if (oldValue == 1) -+ { -+ /* Free integer id. */ -+ gcmkVERIFY_OK( -+ gckKERNEL_FreeIntegerId(Kernel->db->pointerDatabase, -+ shBuf->id)); -+ -+ /* Free atom. */ -+ gcmkVERIFY_OK(gckOS_AtomDestroy(Kernel->os, shBuf->reference)); -+ -+ if (shBuf->data) -+ { -+ gcmkOS_SAFE_FREE(Kernel->os, shBuf->data); -+ shBuf->data = gcvNULL; -+ } -+ -+ /* Free the shared buffer. */ -+ gcmkOS_SAFE_FREE(Kernel->os, shBuf); -+ } -+ -+ /* Release the mutex. */ -+ gcmkVERIFY_OK( -+ gckOS_ReleaseMutex(Kernel->os, Kernel->db->pointerDatabaseMutex)); -+ acquired = gcvFALSE; -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (acquired) -+ { -+ /* Release the mutex. */ -+ gcmkVERIFY_OK( -+ gckOS_ReleaseMutex(Kernel->os, Kernel->db->pointerDatabaseMutex)); -+ } -+ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckKERNEL_MapShBuffer -+** -+** Map shared buffer into this process so that it can be used in this process. -+** This will increase reference count on the specified shared buffer. -+** Call gckKERNEL_DestroyShBuffer to dereference. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** gctSHBUF ShBuf -+** Specify the shared buffer to be mapped. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckKERNEL_MapShBuffer( -+ IN gckKERNEL Kernel, -+ IN gctSHBUF ShBuf -+ ) -+{ -+ gceSTATUS status; -+ gcsSHBUF_PTR shBuf; -+ gctINT32 oldValue = 0; -+ gctBOOL acquired = gcvFALSE; -+ -+ gcmkHEADER_ARG("Kernel=0x%X ShBuf=%u", -+ Kernel, (gctUINT32)(gctUINTPTR_T) ShBuf); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ gcmkVERIFY_ARGUMENT(ShBuf != gcvNULL); -+ -+ /* Acquire mutex. */ -+ gcmkONERROR( -+ gckOS_AcquireMutex(Kernel->os, -+ Kernel->db->pointerDatabaseMutex, -+ gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ /* Find shared buffer structure. */ -+ gcmkONERROR( -+ gckKERNEL_QueryIntegerId(Kernel->db->pointerDatabase, -+ (gctUINT32)(gctUINTPTR_T)ShBuf, -+ (gctPOINTER)&shBuf)); -+ -+ gcmkASSERT(shBuf->id == (gctUINT32)(gctUINTPTR_T)ShBuf); -+ -+ /* Increase the reference count. */ -+ gckOS_AtomIncrement(Kernel->os, shBuf->reference, &oldValue); -+ -+ /* Release the mutex. */ -+ gcmkVERIFY_OK( -+ gckOS_ReleaseMutex(Kernel->os, Kernel->db->pointerDatabaseMutex)); -+ acquired = gcvFALSE; -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (acquired) -+ { -+ /* Release the mutex. */ -+ gcmkVERIFY_OK( -+ gckOS_ReleaseMutex(Kernel->os, Kernel->db->pointerDatabaseMutex)); -+ } -+ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckKERNEL_WriteShBuffer -+** -+** Write user data into shared buffer. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** gctSHBUF ShBuf -+** Specify the shared buffer to be written to. -+** -+** gctPOINTER UserData -+** User mode pointer to hold the source data. -+** -+** gctUINT32 ByteCount -+** Specify number of bytes to write. If this is larger than -+** shared buffer size, gcvSTATUS_INVALID_ARGUMENT is returned. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckKERNEL_WriteShBuffer( -+ IN gckKERNEL Kernel, -+ IN gctSHBUF ShBuf, -+ IN gctPOINTER UserData, -+ IN gctUINT32 ByteCount -+ ) -+{ -+ gceSTATUS status; -+ gcsSHBUF_PTR shBuf; -+ gctBOOL acquired = gcvFALSE; -+ -+ gcmkHEADER_ARG("Kernel=0x%X ShBuf=%u UserData=0x%X ByteCount=%u", -+ Kernel, (gctUINT32)(gctUINTPTR_T) ShBuf, UserData, ByteCount); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ gcmkVERIFY_ARGUMENT(ShBuf != gcvNULL); -+ -+ /* Acquire mutex. */ -+ gcmkONERROR( -+ gckOS_AcquireMutex(Kernel->os, -+ Kernel->db->pointerDatabaseMutex, -+ gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ /* Find shared buffer structure. */ -+ gcmkONERROR( -+ gckKERNEL_QueryIntegerId(Kernel->db->pointerDatabase, -+ (gctUINT32)(gctUINTPTR_T)ShBuf, -+ (gctPOINTER)&shBuf)); -+ -+ gcmkASSERT(shBuf->id == (gctUINT32)(gctUINTPTR_T)ShBuf); -+ -+ if ((ByteCount > shBuf->size) || -+ (ByteCount == 0) || -+ (UserData == gcvNULL)) -+ { -+ /* Exceeds buffer max size or invalid. */ -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ } -+ -+ if (shBuf->data == gcvNULL) -+ { -+ /* Allocate buffer data when first time write. */ -+ gcmkONERROR(gckOS_Allocate(Kernel->os, ByteCount, &shBuf->data)); -+ } -+ -+ /* Copy data from user. */ -+ gcmkONERROR( -+ gckOS_CopyFromUserData(Kernel->os, -+ shBuf->data, -+ UserData, -+ ByteCount)); -+ -+ /* Release the mutex. */ -+ gcmkVERIFY_OK( -+ gckOS_ReleaseMutex(Kernel->os, Kernel->db->pointerDatabaseMutex)); -+ acquired = gcvFALSE; -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (acquired) -+ { -+ /* Release the mutex. */ -+ gcmkVERIFY_OK( -+ gckOS_ReleaseMutex(Kernel->os, Kernel->db->pointerDatabaseMutex)); -+ } -+ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckKERNEL_ReadShBuffer -+** -+** Read data from shared buffer and copy to user pointer. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** gctSHBUF ShBuf -+** Specify the shared buffer to be read from. -+** -+** gctPOINTER UserData -+** User mode pointer to save output data. -+** -+** gctUINT32 ByteCount -+** Specify number of bytes to read. -+** If this is larger than shared buffer size, only avaiable bytes are -+** copied. If smaller, copy requested size. -+** -+** OUTPUT: -+** -+** gctUINT32 * BytesRead -+** Pointer to hold how many bytes actually read from shared buffer. -+*/ -+gceSTATUS -+gckKERNEL_ReadShBuffer( -+ IN gckKERNEL Kernel, -+ IN gctSHBUF ShBuf, -+ IN gctPOINTER UserData, -+ IN gctUINT32 ByteCount, -+ OUT gctUINT32 * BytesRead -+ ) -+{ -+ gceSTATUS status; -+ gcsSHBUF_PTR shBuf; -+ gctUINT32 bytes; -+ gctBOOL acquired = gcvFALSE; -+ -+ gcmkHEADER_ARG("Kernel=0x%X ShBuf=%u UserData=0x%X ByteCount=%u", -+ Kernel, (gctUINT32)(gctUINTPTR_T) ShBuf, UserData, ByteCount); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ gcmkVERIFY_ARGUMENT(ShBuf != gcvNULL); -+ -+ /* Acquire mutex. */ -+ gcmkONERROR( -+ gckOS_AcquireMutex(Kernel->os, -+ Kernel->db->pointerDatabaseMutex, -+ gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ /* Find shared buffer structure. */ -+ gcmkONERROR( -+ gckKERNEL_QueryIntegerId(Kernel->db->pointerDatabase, -+ (gctUINT32)(gctUINTPTR_T)ShBuf, -+ (gctPOINTER)&shBuf)); -+ -+ gcmkASSERT(shBuf->id == (gctUINT32)(gctUINTPTR_T)ShBuf); -+ -+ if (shBuf->data == gcvNULL) -+ { -+ *BytesRead = 0; -+ -+ /* No data in shared buffer, skip copy. */ -+ status = gcvSTATUS_SKIP; -+ goto OnError; -+ } -+ else if (ByteCount == 0) -+ { -+ /* Invalid size to read. */ -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ } -+ -+ /* Determine bytes to copy. */ -+ bytes = (ByteCount < shBuf->size) ? ByteCount : shBuf->size; -+ -+ /* Copy data to user. */ -+ gcmkONERROR( -+ gckOS_CopyToUserData(Kernel->os, -+ shBuf->data, -+ UserData, -+ bytes)); -+ -+ /* Return copied size. */ -+ *BytesRead = bytes; -+ -+ /* Release the mutex. */ -+ gcmkVERIFY_OK( -+ gckOS_ReleaseMutex(Kernel->os, Kernel->db->pointerDatabaseMutex)); -+ acquired = gcvFALSE; -+ -+ gcmkFOOTER_ARG("*BytesRead=%u", bytes); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (acquired) -+ { -+ /* Release the mutex. */ -+ gcmkVERIFY_OK( -+ gckOS_ReleaseMutex(Kernel->os, Kernel->db->pointerDatabaseMutex)); -+ } -+ -+ gcmkFOOTER(); -+ return status; -+} -+ -+ -+/******************************************************************************* -+***** Test Code **************************************************************** -+*******************************************************************************/ -+ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_command.c linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_command.c ---- linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_command.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_command.c 2015-11-30 17:56:13.568138526 +0100 -@@ -0,0 +1,3075 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#include "gc_hal_kernel_precomp.h" -+#include "gc_hal_kernel_context.h" -+ -+#define _GC_OBJ_ZONE gcvZONE_COMMAND -+ -+/******************************************************************************\ -+********************************* Support Code ********************************* -+\******************************************************************************/ -+ -+/******************************************************************************* -+** -+** _NewQueue -+** -+** Allocate a new command queue. -+** -+** INPUT: -+** -+** gckCOMMAND Command -+** Pointer to an gckCOMMAND object. -+** -+** OUTPUT: -+** -+** gckCOMMAND Command -+** gckCOMMAND object has been updated with a new command queue. -+*/ -+static gceSTATUS -+_NewQueue( -+ IN OUT gckCOMMAND Command -+ ) -+{ -+ gceSTATUS status; -+ gctINT currentIndex, newIndex; -+ -+ gcmkHEADER_ARG("Command=0x%x", Command); -+ -+ /* Switch to the next command buffer. */ -+ currentIndex = Command->index; -+ newIndex = (currentIndex + 1) % gcdCOMMAND_QUEUES; -+ -+ /* Wait for availability. */ -+#if gcdDUMP_COMMAND -+ gcmkPRINT("@[kernel.waitsignal]"); -+#endif -+ -+ gcmkONERROR(gckOS_WaitSignal( -+ Command->os, -+ Command->queues[newIndex].signal, -+ gcvINFINITE -+ )); -+ -+#if gcmIS_DEBUG(gcdDEBUG_TRACE) -+ if (newIndex < currentIndex) -+ { -+ Command->wrapCount += 1; -+ -+ gcmkTRACE_ZONE_N( -+ gcvLEVEL_INFO, gcvZONE_COMMAND, -+ 2 * 4, -+ "%s(%d): queue array wrapped around.\n", -+ __FUNCTION__, __LINE__ -+ ); -+ } -+ -+ gcmkTRACE_ZONE_N( -+ gcvLEVEL_INFO, gcvZONE_COMMAND, -+ 3 * 4, -+ "%s(%d): total queue wrap arounds %d.\n", -+ __FUNCTION__, __LINE__, Command->wrapCount -+ ); -+ -+ gcmkTRACE_ZONE_N( -+ gcvLEVEL_INFO, gcvZONE_COMMAND, -+ 3 * 4, -+ "%s(%d): switched to queue %d.\n", -+ __FUNCTION__, __LINE__, newIndex -+ ); -+#endif -+ -+ /* Update gckCOMMAND object with new command queue. */ -+ Command->index = newIndex; -+ Command->newQueue = gcvTRUE; -+ Command->logical = Command->queues[newIndex].logical; -+ Command->address = Command->queues[newIndex].address; -+ Command->offset = 0; -+ -+ gcmkONERROR(gckOS_GetPhysicalAddress( -+ Command->os, -+ Command->logical, -+ (gctUINT32 *) &Command->physical -+ )); -+ -+ if (currentIndex != -1) -+ { -+ /* Mark the command queue as available. */ -+ gcmkONERROR(gckEVENT_Signal( -+ Command->kernel->eventObj, -+ Command->queues[currentIndex].signal, -+ gcvKERNEL_COMMAND -+ )); -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("Command->index=%d", Command->index); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+static gceSTATUS -+_IncrementCommitAtom( -+ IN gckCOMMAND Command, -+ IN gctBOOL Increment -+ ) -+{ -+ gceSTATUS status; -+ gckHARDWARE hardware; -+ gctINT32 atomValue; -+ gctBOOL powerAcquired = gcvFALSE; -+ -+ gcmkHEADER_ARG("Command=0x%x", Command); -+ -+ /* Extract the gckHARDWARE and gckEVENT objects. */ -+ hardware = Command->kernel->hardware; -+ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE); -+ -+ /* Increment the commit atom. */ -+ if (Increment) -+ { -+ /* Grab the power mutex. */ -+ gcmkONERROR(gckOS_AcquireMutex( -+ Command->os, hardware->powerMutex, gcvINFINITE -+ )); -+ powerAcquired = gcvTRUE; -+ -+ gcmkONERROR(gckOS_AtomIncrement( -+ Command->os, Command->atomCommit, &atomValue -+ )); -+ -+ /* Release the power mutex. */ -+ gcmkONERROR(gckOS_ReleaseMutex( -+ Command->os, hardware->powerMutex -+ )); -+ powerAcquired = gcvFALSE; -+ } -+ else -+ { -+ gcmkONERROR(gckOS_AtomDecrement( -+ Command->os, Command->atomCommit, &atomValue -+ )); -+ } -+ -+ /* Success. */ -+ gcmkFOOTER(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (powerAcquired) -+ { -+ /* Release the power mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex( -+ Command->os, hardware->powerMutex -+ )); -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+static gceSTATUS -+_FlushMMU( -+ IN gckCOMMAND Command -+ ) -+{ -+ gceSTATUS status; -+ gctUINT32 oldValue; -+ gckHARDWARE hardware = Command->kernel->hardware; -+ gctBOOL pause = gcvFALSE; -+ -+ gctUINT8_PTR pointer; -+ gctUINT32 eventBytes; -+ gctUINT32 endBytes; -+ gctUINT32 bufferSize; -+ gctUINT32 executeBytes; -+ gctUINT32 waitLinkBytes; -+ -+ gcmkONERROR(gckOS_AtomicExchange(Command->os, -+ hardware->pageTableDirty, -+ 0, -+ &oldValue)); -+ -+ if (oldValue) -+ { -+ /* Page Table is upated, flush mmu before commit. */ -+ gcmkONERROR(gckHARDWARE_FlushMMU(hardware)); -+ -+ if ((oldValue & gcvPAGE_TABLE_DIRTY_BIT_FE) -+ && (hardware->endAfterFlushMmuCache) -+ ) -+ { -+ pause = gcvTRUE; -+ } -+ } -+ -+ if (pause) -+ { -+ /* Query size. */ -+ gcmkONERROR(gckHARDWARE_Event(hardware, gcvNULL, 0, gcvKERNEL_PIXEL, &eventBytes)); -+ gcmkONERROR(gckHARDWARE_End(hardware, gcvNULL, &endBytes)); -+ -+ executeBytes = eventBytes + endBytes; -+ -+ gcmkONERROR(gckHARDWARE_WaitLink( -+ hardware, -+ gcvNULL, -+ Command->offset + executeBytes, -+ &waitLinkBytes, -+ gcvNULL, -+ gcvNULL -+ )); -+ -+ /* Reserve space. */ -+ gcmkONERROR(gckCOMMAND_Reserve( -+ Command, -+ executeBytes, -+ (gctPOINTER *)&pointer, -+ &bufferSize -+ )); -+ -+ /* Append EVENT(29). */ -+ gcmkONERROR(gckHARDWARE_Event( -+ hardware, -+ pointer, -+ 29, -+ gcvKERNEL_PIXEL, -+ &eventBytes -+ )); -+ -+ /* Append END. */ -+ pointer += eventBytes; -+ gcmkONERROR(gckHARDWARE_End(hardware, pointer, &endBytes)); -+ -+ /* Store address to queue. */ -+ gcmkONERROR(gckENTRYQUEUE_Enqueue( -+ Command->kernel, -+ &Command->queue, -+ Command->address + Command->offset + executeBytes, -+ waitLinkBytes -+ )); -+ -+ gcmkONERROR(gckCOMMAND_Execute(Command, executeBytes)); -+ } -+ -+ return gcvSTATUS_OK; -+OnError: -+ return status; -+} -+ -+static void -+_DumpBuffer( -+ IN gctPOINTER Buffer, -+ IN gctUINT32 GpuAddress, -+ IN gctSIZE_T Size -+ ) -+{ -+ gctSIZE_T i, line, left; -+ gctUINT32_PTR data = Buffer; -+ -+ line = Size / 32; -+ left = Size % 32; -+ -+ for (i = 0; i < line; i++) -+ { -+ gcmkPRINT("%X : %08X %08X %08X %08X %08X %08X %08X %08X ", -+ GpuAddress, data[0], data[1], data[2], data[3], data[4], data[5], data[6], data[7]); -+ data += 8; -+ GpuAddress += 8 * 4; -+ } -+ -+ switch(left) -+ { -+ case 28: -+ gcmkPRINT("%X : %08X %08X %08X %08X %08X %08X %08X ", -+ GpuAddress, data[0], data[1], data[2], data[3], data[4], data[5], data[6]); -+ break; -+ case 24: -+ gcmkPRINT("%X : %08X %08X %08X %08X %08X %08X ", -+ GpuAddress, data[0], data[1], data[2], data[3], data[4], data[5]); -+ break; -+ case 20: -+ gcmkPRINT("%X : %08X %08X %08X %08X %08X ", -+ GpuAddress, data[0], data[1], data[2], data[3], data[4]); -+ break; -+ case 16: -+ gcmkPRINT("%X : %08X %08X %08X %08X ", -+ GpuAddress, data[0], data[1], data[2], data[3]); -+ break; -+ case 12: -+ gcmkPRINT("%X : %08X %08X %08X ", -+ GpuAddress, data[0], data[1], data[2]); -+ break; -+ case 8: -+ gcmkPRINT("%X : %08X %08X ", -+ GpuAddress, data[0], data[1]); -+ break; -+ case 4: -+ gcmkPRINT("%X : %08X ", -+ GpuAddress, data[0]); -+ break; -+ default: -+ break; -+ } -+} -+ -+static void -+_DumpKernelCommandBuffer( -+ IN gckCOMMAND Command -+ ) -+{ -+ gctINT i; -+ gctUINT32 physical = 0; -+ gctPOINTER entry = gcvNULL; -+ -+ for (i = 0; i < gcdCOMMAND_QUEUES; i++) -+ { -+ entry = Command->queues[i].logical; -+ -+ gckOS_GetPhysicalAddress(Command->os, entry, &physical); -+ -+ gcmkPRINT("Kernel command buffer %d\n", i); -+ -+ _DumpBuffer(entry, physical, Command->pageSize); -+ } -+} -+ -+/******************************************************************************\ -+****************************** gckCOMMAND API Code ****************************** -+\******************************************************************************/ -+ -+/******************************************************************************* -+** -+** gckCOMMAND_Construct -+** -+** Construct a new gckCOMMAND object. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** OUTPUT: -+** -+** gckCOMMAND * Command -+** Pointer to a variable that will hold the pointer to the gckCOMMAND -+** object. -+*/ -+gceSTATUS -+gckCOMMAND_Construct( -+ IN gckKERNEL Kernel, -+ OUT gckCOMMAND * Command -+ ) -+{ -+ gckOS os; -+ gckCOMMAND command = gcvNULL; -+ gceSTATUS status; -+ gctINT i; -+ gctPOINTER pointer = gcvNULL; -+ gctSIZE_T pageSize; -+ -+ gcmkHEADER_ARG("Kernel=0x%x", Kernel); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ gcmkVERIFY_ARGUMENT(Command != gcvNULL); -+ -+ /* Extract the gckOS object. */ -+ os = Kernel->os; -+ -+ /* Allocate the gckCOMMAND structure. */ -+ gcmkONERROR(gckOS_Allocate(os, gcmSIZEOF(struct _gckCOMMAND), &pointer)); -+ command = pointer; -+ -+ /* Reset the entire object. */ -+ gcmkONERROR(gckOS_ZeroMemory(command, gcmSIZEOF(struct _gckCOMMAND))); -+ -+ /* Initialize the gckCOMMAND object.*/ -+ command->object.type = gcvOBJ_COMMAND; -+ command->kernel = Kernel; -+ command->os = os; -+ -+ /* Get the command buffer requirements. */ -+ gcmkONERROR(gckHARDWARE_QueryCommandBuffer( -+ Kernel->hardware, -+ &command->alignment, -+ &command->reservedHead, -+ &command->reservedTail -+ )); -+ -+ /* Create the command queue mutex. */ -+ gcmkONERROR(gckOS_CreateMutex(os, &command->mutexQueue)); -+ -+ /* Create the context switching mutex. */ -+ gcmkONERROR(gckOS_CreateMutex(os, &command->mutexContext)); -+ -+#if VIVANTE_PROFILER_CONTEXT -+ /* Create the context switching mutex. */ -+ gcmkONERROR(gckOS_CreateMutex(os, &command->mutexContextSeq)); -+#endif -+ -+ /* Create the power management semaphore. */ -+ gcmkONERROR(gckOS_CreateSemaphore(os, &command->powerSemaphore)); -+ -+ /* Create the commit atom. */ -+ gcmkONERROR(gckOS_AtomConstruct(os, &command->atomCommit)); -+ -+ /* Get the page size from teh OS. */ -+ gcmkONERROR(gckOS_GetPageSize(os, &pageSize)); -+ -+ gcmkSAFECASTSIZET(command->pageSize, pageSize); -+ -+ /* Get process ID. */ -+ gcmkONERROR(gckOS_GetProcessID(&command->kernelProcessID)); -+ -+ /* Set hardware to pipe 0. */ -+ command->pipeSelect = gcvPIPE_INVALID; -+ -+ /* Pre-allocate the command queues. */ -+ for (i = 0; i < gcdCOMMAND_QUEUES; ++i) -+ { -+ gcmkONERROR(gckOS_AllocateNonPagedMemory( -+ os, -+ gcvFALSE, -+ &pageSize, -+ &command->queues[i].physical, -+ &command->queues[i].logical -+ )); -+ -+ gcmkONERROR(gckHARDWARE_ConvertLogical( -+ Kernel->hardware, -+ command->queues[i].logical, -+ gcvFALSE, -+ &command->queues[i].address -+ )); -+ -+ gcmkONERROR(gckOS_CreateSignal( -+ os, gcvFALSE, &command->queues[i].signal -+ )); -+ -+ gcmkONERROR(gckOS_Signal( -+ os, command->queues[i].signal, gcvTRUE -+ )); -+ } -+ -+#if gcdRECORD_COMMAND -+ gcmkONERROR(gckRECORDER_Construct(os, Kernel->hardware, &command->recorder)); -+#endif -+ -+ /* No command queue in use yet. */ -+ command->index = -1; -+ command->logical = gcvNULL; -+ command->newQueue = gcvFALSE; -+ -+ /* Command is not yet running. */ -+ command->running = gcvFALSE; -+ -+ /* Command queue is idle. */ -+ command->idle = gcvTRUE; -+ -+ /* Commit stamp is zero. */ -+ command->commitStamp = 0; -+ -+ /* END event signal not created. */ -+ command->endEventSignal = gcvNULL; -+ -+ command->queue.front = 0; -+ command->queue.rear = 0; -+ command->queue.count = 0; -+ -+ /* Return pointer to the gckCOMMAND object. */ -+ *Command = command; -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Command=0x%x", *Command); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Roll back. */ -+ if (command != gcvNULL) -+ { -+ if (command->atomCommit != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckOS_AtomDestroy(os, command->atomCommit)); -+ } -+ -+ if (command->powerSemaphore != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckOS_DestroySemaphore(os, command->powerSemaphore)); -+ } -+ -+ if (command->mutexContext != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckOS_DeleteMutex(os, command->mutexContext)); -+ } -+ -+#if VIVANTE_PROFILER_CONTEXT -+ if (command->mutexContextSeq != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckOS_DeleteMutex(os, command->mutexContextSeq)); -+ } -+#endif -+ -+ if (command->mutexQueue != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckOS_DeleteMutex(os, command->mutexQueue)); -+ } -+ -+ for (i = 0; i < gcdCOMMAND_QUEUES; ++i) -+ { -+ if (command->queues[i].signal != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckOS_DestroySignal( -+ os, command->queues[i].signal -+ )); -+ } -+ -+ if (command->queues[i].logical != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckOS_FreeNonPagedMemory( -+ os, -+ command->pageSize, -+ command->queues[i].physical, -+ command->queues[i].logical -+ )); -+ } -+ } -+ -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, command)); -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckCOMMAND_Destroy -+** -+** Destroy an gckCOMMAND object. -+** -+** INPUT: -+** -+** gckCOMMAND Command -+** Pointer to an gckCOMMAND object to destroy. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckCOMMAND_Destroy( -+ IN gckCOMMAND Command -+ ) -+{ -+ gctINT i; -+ -+ gcmkHEADER_ARG("Command=0x%x", Command); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND); -+ -+ /* Stop the command queue. */ -+ gcmkVERIFY_OK(gckCOMMAND_Stop(Command, gcvFALSE)); -+ -+ for (i = 0; i < gcdCOMMAND_QUEUES; ++i) -+ { -+ gcmkASSERT(Command->queues[i].signal != gcvNULL); -+ gcmkVERIFY_OK(gckOS_DestroySignal( -+ Command->os, Command->queues[i].signal -+ )); -+ -+ gcmkASSERT(Command->queues[i].logical != gcvNULL); -+ gcmkVERIFY_OK(gckOS_FreeNonPagedMemory( -+ Command->os, -+ Command->pageSize, -+ Command->queues[i].physical, -+ Command->queues[i].logical -+ )); -+ } -+ -+ /* END event signal. */ -+ if (Command->endEventSignal != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckOS_DestroySignal( -+ Command->os, Command->endEventSignal -+ )); -+ } -+ -+ /* Delete the context switching mutex. */ -+ gcmkVERIFY_OK(gckOS_DeleteMutex(Command->os, Command->mutexContext)); -+ -+#if VIVANTE_PROFILER_CONTEXT -+ if (Command->mutexContextSeq != gcvNULL) -+ gcmkVERIFY_OK(gckOS_DeleteMutex(Command->os, Command->mutexContextSeq)); -+#endif -+ -+ /* Delete the command queue mutex. */ -+ gcmkVERIFY_OK(gckOS_DeleteMutex(Command->os, Command->mutexQueue)); -+ -+ /* Destroy the power management semaphore. */ -+ gcmkVERIFY_OK(gckOS_DestroySemaphore(Command->os, Command->powerSemaphore)); -+ -+ /* Destroy the commit atom. */ -+ gcmkVERIFY_OK(gckOS_AtomDestroy(Command->os, Command->atomCommit)); -+ -+#if gcdRECORD_COMMAND -+ gckRECORDER_Destory(Command->os, Command->recorder); -+#endif -+ -+ /* Mark object as unknown. */ -+ Command->object.type = gcvOBJ_UNKNOWN; -+ -+ /* Free the gckCOMMAND object. */ -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Command->os, Command)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckCOMMAND_EnterCommit -+** -+** Acquire command queue synchronization objects. -+** -+** INPUT: -+** -+** gckCOMMAND Command -+** Pointer to an gckCOMMAND object to destroy. -+** -+** gctBOOL FromPower -+** Determines whether the call originates from inside the power -+** management or not. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckCOMMAND_EnterCommit( -+ IN gckCOMMAND Command, -+ IN gctBOOL FromPower -+ ) -+{ -+ gceSTATUS status; -+ gckHARDWARE hardware; -+ gctBOOL atomIncremented = gcvFALSE; -+ gctBOOL semaAcquired = gcvFALSE; -+ -+ gcmkHEADER_ARG("Command=0x%x", Command); -+ -+ /* Extract the gckHARDWARE and gckEVENT objects. */ -+ hardware = Command->kernel->hardware; -+ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE); -+ -+ if (!FromPower) -+ { -+ /* Increment COMMIT atom to let power management know that a commit is -+ ** in progress. */ -+ gcmkONERROR(_IncrementCommitAtom(Command, gcvTRUE)); -+ atomIncremented = gcvTRUE; -+ -+ /* Notify the system the GPU has a commit. */ -+ gcmkONERROR(gckOS_Broadcast(Command->os, -+ hardware, -+ gcvBROADCAST_GPU_COMMIT)); -+ -+ /* Acquire the power management semaphore. */ -+ gcmkONERROR(gckOS_AcquireSemaphore(Command->os, -+ Command->powerSemaphore)); -+ semaAcquired = gcvTRUE; -+ } -+ -+ /* Grab the conmmand queue mutex. */ -+ gcmkONERROR(gckOS_AcquireMutex(Command->os, -+ Command->mutexQueue, -+ gcvINFINITE)); -+ -+ /* Success. */ -+ gcmkFOOTER(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (semaAcquired) -+ { -+ /* Release the power management semaphore. */ -+ gcmkVERIFY_OK(gckOS_ReleaseSemaphore( -+ Command->os, Command->powerSemaphore -+ )); -+ } -+ -+ if (atomIncremented) -+ { -+ /* Decrement the commit atom. */ -+ gcmkVERIFY_OK(_IncrementCommitAtom( -+ Command, gcvFALSE -+ )); -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckCOMMAND_ExitCommit -+** -+** Release command queue synchronization objects. -+** -+** INPUT: -+** -+** gckCOMMAND Command -+** Pointer to an gckCOMMAND object to destroy. -+** -+** gctBOOL FromPower -+** Determines whether the call originates from inside the power -+** management or not. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckCOMMAND_ExitCommit( -+ IN gckCOMMAND Command, -+ IN gctBOOL FromPower -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Command=0x%x", Command); -+ -+ /* Release the power mutex. */ -+ gcmkONERROR(gckOS_ReleaseMutex(Command->os, Command->mutexQueue)); -+ -+ if (!FromPower) -+ { -+ /* Release the power management semaphore. */ -+ gcmkONERROR(gckOS_ReleaseSemaphore(Command->os, -+ Command->powerSemaphore)); -+ -+ /* Decrement the commit atom. */ -+ gcmkONERROR(_IncrementCommitAtom(Command, gcvFALSE)); -+ } -+ -+ /* Success. */ -+ gcmkFOOTER(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckCOMMAND_Start -+** -+** Start up the command queue. -+** -+** INPUT: -+** -+** gckCOMMAND Command -+** Pointer to an gckCOMMAND object to start. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckCOMMAND_Start( -+ IN gckCOMMAND Command -+ ) -+{ -+ gceSTATUS status; -+ gckHARDWARE hardware; -+ gctUINT32 waitOffset = 0; -+ gctUINT32 waitLinkBytes; -+ -+ gcmkHEADER_ARG("Command=0x%x", Command); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND); -+ -+ if (Command->running) -+ { -+ /* Command queue already running. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ } -+ -+ /* Extract the gckHARDWARE object. */ -+ hardware = Command->kernel->hardware; -+ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE); -+ -+ if (Command->logical == gcvNULL) -+ { -+ /* Start at beginning of a new queue. */ -+ gcmkONERROR(_NewQueue(Command)); -+ } -+ -+ /* Start at beginning of page. */ -+ Command->offset = 0; -+ -+ /* Set abvailable number of bytes for WAIT/LINK command sequence. */ -+ waitLinkBytes = Command->pageSize; -+ -+ /* Append WAIT/LINK. */ -+ gcmkONERROR(gckHARDWARE_WaitLink( -+ hardware, -+ Command->logical, -+ 0, -+ &waitLinkBytes, -+ &waitOffset, -+ &Command->waitSize -+ )); -+ -+ Command->waitLogical = (gctUINT8_PTR) Command->logical + waitOffset; -+ Command->waitPhysical = (gctUINT8_PTR) Command->physical + waitOffset; -+ -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ /* Flush the cache for the wait/link. */ -+ gcmkONERROR(gckOS_CacheClean( -+ Command->os, -+ Command->kernelProcessID, -+ gcvNULL, -+ (gctUINT32)Command->physical, -+ Command->logical, -+ waitLinkBytes -+ )); -+#endif -+ -+ /* Adjust offset. */ -+ Command->offset = waitLinkBytes; -+ Command->newQueue = gcvFALSE; -+ -+ /* Enable command processor. */ -+ gcmkONERROR(gckHARDWARE_Execute( -+ hardware, -+ Command->address, -+ waitLinkBytes -+ )); -+ -+ /* Command queue is running. */ -+ Command->running = gcvTRUE; -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckCOMMAND_Stop -+** -+** Stop the command queue. -+** -+** INPUT: -+** -+** gckCOMMAND Command -+** Pointer to an gckCOMMAND object to stop. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckCOMMAND_Stop( -+ IN gckCOMMAND Command, -+ IN gctBOOL FromRecovery -+ ) -+{ -+ gckHARDWARE hardware; -+ gceSTATUS status; -+ gctUINT32 idle; -+ -+ gcmkHEADER_ARG("Command=0x%x", Command); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND); -+ -+ if (!Command->running) -+ { -+ /* Command queue is not running. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ } -+ -+ /* Extract the gckHARDWARE object. */ -+ hardware = Command->kernel->hardware; -+ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE); -+ -+ if (gckHARDWARE_IsFeatureAvailable(hardware, -+ gcvFEATURE_END_EVENT) == gcvSTATUS_TRUE) -+ { -+ /* Allocate the signal. */ -+ if (Command->endEventSignal == gcvNULL) -+ { -+ gcmkONERROR(gckOS_CreateSignal(Command->os, -+ gcvTRUE, -+ &Command->endEventSignal)); -+ } -+ -+ /* Append the END EVENT command to trigger the signal. */ -+ gcmkONERROR(gckEVENT_Stop(Command->kernel->eventObj, -+ Command->kernelProcessID, -+ Command->waitPhysical, -+ Command->waitLogical, -+ Command->endEventSignal, -+ &Command->waitSize)); -+ } -+ else -+ { -+ /* Replace last WAIT with END. */ -+ gcmkONERROR(gckHARDWARE_End( -+ hardware, Command->waitLogical, &Command->waitSize -+ )); -+ -+ /* Update queue tail pointer. */ -+ gcmkONERROR(gckHARDWARE_UpdateQueueTail(Command->kernel->hardware, -+ Command->logical, -+ Command->offset)); -+ -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ /* Flush the cache for the END. */ -+ gcmkONERROR(gckOS_CacheClean( -+ Command->os, -+ Command->kernelProcessID, -+ gcvNULL, -+ (gctUINT32)Command->waitPhysical, -+ Command->waitLogical, -+ Command->waitSize -+ )); -+#endif -+ -+ /* Wait for idle. */ -+ gcmkONERROR(gckHARDWARE_GetIdle(hardware, !FromRecovery, &idle)); -+ } -+ -+ /* Command queue is no longer running. */ -+ Command->running = gcvFALSE; -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckCOMMAND_Commit -+** -+** Commit a command buffer to the command queue. -+** -+** INPUT: -+** -+** gckCOMMAND Command -+** Pointer to a gckCOMMAND object. -+** -+** gckCONTEXT Context -+** Pointer to a gckCONTEXT object. -+** -+** gcoCMDBUF CommandBuffer -+** Pointer to a gcoCMDBUF object. -+** -+** gcsSTATE_DELTA_PTR StateDelta -+** Pointer to the state delta. -+** -+** gctUINT32 ProcessID -+** Current process ID. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckCOMMAND_Commit( -+ IN gckCOMMAND Command, -+ IN gckCONTEXT Context, -+ IN gcoCMDBUF CommandBuffer, -+ IN gcsSTATE_DELTA_PTR StateDelta, -+ IN gcsQUEUE_PTR EventQueue, -+ IN gctUINT32 ProcessID -+ ) -+{ -+ gceSTATUS status; -+ gctBOOL commitEntered = gcvFALSE; -+ gctBOOL contextAcquired = gcvFALSE; -+ gckHARDWARE hardware; -+ gctBOOL needCopy = gcvFALSE; -+ gcsQUEUE_PTR eventRecord = gcvNULL; -+ gcsQUEUE _eventRecord; -+ gcsQUEUE_PTR nextEventRecord; -+ gctBOOL commandBufferMapped = gcvFALSE; -+ gcoCMDBUF commandBufferObject = gcvNULL; -+ -+#if !gcdNULL_DRIVER -+ gcsCONTEXT_PTR contextBuffer; -+ struct _gcoCMDBUF _commandBufferObject; -+ gctPHYS_ADDR commandBufferPhysical; -+ gctUINT8_PTR commandBufferLogical = gcvNULL; -+ gctUINT32 commandBufferAddress = 0; -+ gctUINT8_PTR commandBufferLink = gcvNULL; -+ gctUINT commandBufferSize; -+ gctSIZE_T nopBytes; -+ gctUINT32 pipeBytes; -+ gctUINT32 linkBytes; -+ gctSIZE_T bytes; -+ gctUINT32 offset; -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ gctPHYS_ADDR entryPhysical; -+#endif -+ gctPOINTER entryLogical; -+ gctUINT32 entryAddress; -+ gctUINT32 entryBytes; -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ gctPHYS_ADDR exitPhysical; -+#endif -+ gctPOINTER exitLogical; -+ gctUINT32 exitAddress; -+ gctUINT32 exitBytes; -+ gctPHYS_ADDR waitLinkPhysical; -+ gctPOINTER waitLinkLogical; -+ gctUINT32 waitLinkAddress; -+ gctUINT32 waitLinkBytes; -+ gctPHYS_ADDR waitPhysical; -+ gctPOINTER waitLogical; -+ gctUINT32 waitOffset; -+ gctUINT32 waitSize; -+ -+#if gcdPROCESS_ADDRESS_SPACE -+ gctSIZE_T mmuConfigureBytes; -+ gctPOINTER mmuConfigureLogical = gcvNULL; -+ gctUINT32 mmuConfigureAddress; -+ gctPOINTER mmuConfigurePhysical = 0; -+ gctSIZE_T mmuConfigureWaitLinkOffset; -+ gckMMU mmu; -+ gctSIZE_T reservedBytes; -+ gctUINT32 oldValue; -+#endif -+ -+#if gcdDUMP_COMMAND -+ gctPOINTER contextDumpLogical = gcvNULL; -+ gctSIZE_T contextDumpBytes = 0; -+ gctPOINTER bufferDumpLogical = gcvNULL; -+ gctSIZE_T bufferDumpBytes = 0; -+# endif -+#endif -+ -+#if VIVANTE_PROFILER_CONTEXT -+ gctBOOL sequenceAcquired = gcvFALSE; -+#endif -+ -+ gctPOINTER pointer = gcvNULL; -+ -+ gcmkHEADER_ARG( -+ "Command=0x%x CommandBuffer=0x%x ProcessID=%d", -+ Command, CommandBuffer, ProcessID -+ ); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND); -+ -+ if (Command->kernel->hardware->type== gcvHARDWARE_2D) -+ { -+ /* There is no context for 2D. */ -+ Context = gcvNULL; -+ } -+ -+#if gcdPROCESS_ADDRESS_SPACE -+ gcmkONERROR(gckKERNEL_GetProcessMMU(Command->kernel, &mmu)); -+ -+ gcmkONERROR(gckOS_AtomicExchange(Command->os, -+ mmu->pageTableDirty[Command->kernel->core], -+ 0, -+ &oldValue)); -+#else -+#endif -+ -+#if VIVANTE_PROFILER_CONTEXT -+ if((Command->kernel->hardware->gpuProfiler) && (Command->kernel->profileEnable)) -+ { -+ /* Acquire the context sequnence mutex. */ -+ gcmkONERROR(gckOS_AcquireMutex( -+ Command->os, Command->mutexContextSeq, gcvINFINITE -+ )); -+ sequenceAcquired = gcvTRUE; -+ } -+#endif -+ -+ /* Acquire the command queue. */ -+ gcmkONERROR(gckCOMMAND_EnterCommit(Command, gcvFALSE)); -+ commitEntered = gcvTRUE; -+ -+ /* Acquire the context switching mutex. */ -+ gcmkONERROR(gckOS_AcquireMutex( -+ Command->os, Command->mutexContext, gcvINFINITE -+ )); -+ contextAcquired = gcvTRUE; -+ -+ /* Extract the gckHARDWARE and gckEVENT objects. */ -+ hardware = Command->kernel->hardware; -+ -+ /* Check wehther we need to copy the structures or not. */ -+ gcmkONERROR(gckOS_QueryNeedCopy(Command->os, ProcessID, &needCopy)); -+ -+#if gcdNULL_DRIVER -+ /* Context switch required? */ -+ if ((Context != gcvNULL) && (Command->currContext != Context)) -+ { -+ /* Yes, merge in the deltas. */ -+ gckCONTEXT_Update(Context, ProcessID, StateDelta); -+ -+ /* Update the current context. */ -+ Command->currContext = Context; -+ } -+#else -+ if (needCopy) -+ { -+ commandBufferObject = &_commandBufferObject; -+ -+ gcmkONERROR(gckOS_CopyFromUserData( -+ Command->os, -+ commandBufferObject, -+ CommandBuffer, -+ gcmSIZEOF(struct _gcoCMDBUF) -+ )); -+ -+ gcmkVERIFY_OBJECT(commandBufferObject, gcvOBJ_COMMANDBUFFER); -+ } -+ else -+ { -+ gcmkONERROR(gckOS_MapUserPointer( -+ Command->os, -+ CommandBuffer, -+ gcmSIZEOF(struct _gcoCMDBUF), -+ &pointer -+ )); -+ -+ commandBufferObject = pointer; -+ -+ gcmkVERIFY_OBJECT(commandBufferObject, gcvOBJ_COMMANDBUFFER); -+ commandBufferMapped = gcvTRUE; -+ } -+ -+ /* Query the size of NOP command. */ -+ gcmkONERROR(gckHARDWARE_Nop( -+ hardware, gcvNULL, &nopBytes -+ )); -+ -+ /* Query the size of pipe select command sequence. */ -+ gcmkONERROR(gckHARDWARE_PipeSelect( -+ hardware, gcvNULL, gcvPIPE_3D, &pipeBytes -+ )); -+ -+ /* Query the size of LINK command. */ -+ gcmkONERROR(gckHARDWARE_Link( -+ hardware, gcvNULL, 0, 0, &linkBytes -+ )); -+ -+ /* Compute the command buffer entry and the size. */ -+ commandBufferLogical -+ = (gctUINT8_PTR) gcmUINT64_TO_PTR(commandBufferObject->logical) -+ + commandBufferObject->startOffset; -+ -+ /* Get the hardware address. */ -+ if (Command->kernel->virtualCommandBuffer) -+ { -+ gcmkONERROR(gckKERNEL_GetGPUAddress( -+ Command->kernel, -+ commandBufferLogical, -+ gcvTRUE, -+ &commandBufferAddress -+ )); -+ } -+ else -+ { -+ gcmkONERROR(gckHARDWARE_ConvertLogical( -+ hardware, -+ commandBufferLogical, -+ gcvTRUE, -+ &commandBufferAddress -+ )); -+ } -+ -+ /* Get the physical address. */ -+ gcmkONERROR(gckOS_UserLogicalToPhysical( -+ Command->os, -+ commandBufferLogical, -+ (gctUINT32_PTR)&commandBufferPhysical -+ )); -+ -+ commandBufferSize -+ = commandBufferObject->offset -+ + Command->reservedTail -+ - commandBufferObject->startOffset; -+ -+ gcmkONERROR(_FlushMMU(Command)); -+ -+ /* Get the current offset. */ -+ offset = Command->offset; -+ -+ /* Compute number of bytes left in current kernel command queue. */ -+ bytes = Command->pageSize - offset; -+ -+ /* Query the size of WAIT/LINK command sequence. */ -+ gcmkONERROR(gckHARDWARE_WaitLink( -+ hardware, -+ gcvNULL, -+ offset, -+ &waitLinkBytes, -+ gcvNULL, -+ gcvNULL -+ )); -+ -+ /* Is there enough space in the current command queue? */ -+ if (bytes < waitLinkBytes) -+ { -+ /* No, create a new one. */ -+ gcmkONERROR(_NewQueue(Command)); -+ -+ /* Get the new current offset. */ -+ offset = Command->offset; -+ -+ /* Recompute the number of bytes in the new kernel command queue. */ -+ bytes = Command->pageSize - offset; -+ gcmkASSERT(bytes >= waitLinkBytes); -+ } -+ -+ /* Compute the location if WAIT/LINK command sequence. */ -+ waitLinkPhysical = (gctUINT8_PTR) Command->physical + offset; -+ waitLinkLogical = (gctUINT8_PTR) Command->logical + offset; -+ waitLinkAddress = Command->address + offset; -+ -+ /* Context switch required? */ -+ if (Context == gcvNULL) -+ { -+ /* See if we have to switch pipes for the command buffer. */ -+ if (commandBufferObject->entryPipe == Command->pipeSelect) -+ { -+ /* Skip pipe switching sequence. */ -+ offset = pipeBytes; -+ } -+ else -+ { -+ /* The current hardware and the entry command buffer pipes -+ ** are different, switch to the correct pipe. */ -+ gcmkONERROR(gckHARDWARE_PipeSelect( -+ Command->kernel->hardware, -+ commandBufferLogical, -+ commandBufferObject->entryPipe, -+ &pipeBytes -+ )); -+ -+ /* Do not skip pipe switching sequence. */ -+ offset = 0; -+ } -+ -+ /* Compute the entry. */ -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ entryPhysical = (gctUINT8_PTR) commandBufferPhysical + offset; -+#endif -+ entryLogical = commandBufferLogical + offset; -+ entryAddress = commandBufferAddress + offset; -+ entryBytes = commandBufferSize - offset; -+ -+ Command->currContext = gcvNULL; -+ } -+ else if (Command->currContext != Context) -+ { -+ /* Temporary disable context length oprimization. */ -+ Context->dirty = gcvTRUE; -+ -+ /* Get the current context buffer. */ -+ contextBuffer = Context->buffer; -+ -+ /* Yes, merge in the deltas. */ -+ gcmkONERROR(gckCONTEXT_Update(Context, ProcessID, StateDelta)); -+ -+ /* Determine context entry and exit points. */ -+ if (0) -+ { -+ /* Reset 2D dirty flag. */ -+ Context->dirty2D = gcvFALSE; -+ -+ if (Context->dirty || commandBufferObject->using3D) -+ { -+ /*************************************************************** -+ ** SWITCHING CONTEXT: 2D and 3D are used. -+ */ -+ -+ /* Reset 3D dirty flag. */ -+ Context->dirty3D = gcvFALSE; -+ -+ /* Compute the entry. */ -+ if (Command->pipeSelect == gcvPIPE_2D) -+ { -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ entryPhysical = (gctUINT8_PTR) contextBuffer->physical + pipeBytes; -+#endif -+ entryLogical = (gctUINT8_PTR) contextBuffer->logical + pipeBytes; -+ entryAddress = contextBuffer->address + pipeBytes; -+ entryBytes = Context->bufferSize - pipeBytes; -+ } -+ else -+ { -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ entryPhysical = (gctUINT8_PTR) contextBuffer->physical; -+#endif -+ entryLogical = (gctUINT8_PTR) contextBuffer->logical; -+ entryAddress = contextBuffer->address; -+ entryBytes = Context->bufferSize; -+ } -+ -+ /* See if we have to switch pipes between the context -+ and command buffers. */ -+ if (commandBufferObject->entryPipe == gcvPIPE_3D) -+ { -+ /* Skip pipe switching sequence. */ -+ offset = pipeBytes; -+ } -+ else -+ { -+ /* The current hardware and the initial context pipes are -+ different, switch to the correct pipe. */ -+ gcmkONERROR(gckHARDWARE_PipeSelect( -+ Command->kernel->hardware, -+ commandBufferLogical, -+ commandBufferObject->entryPipe, -+ &pipeBytes -+ )); -+ -+ /* Do not skip pipe switching sequence. */ -+ offset = 0; -+ } -+ -+ /* Ensure the NOP between 2D and 3D is in place so that the -+ execution falls through from 2D to 3D. */ -+ gcmkONERROR(gckHARDWARE_Nop( -+ hardware, -+ contextBuffer->link2D, -+ &nopBytes -+ )); -+ -+ /* Generate a LINK from the context buffer to -+ the command buffer. */ -+ gcmkONERROR(gckHARDWARE_Link( -+ hardware, -+ contextBuffer->link3D, -+ commandBufferAddress + offset, -+ commandBufferSize - offset, -+ &linkBytes -+ )); -+ -+ /* Mark context as not dirty. */ -+ Context->dirty = gcvFALSE; -+ } -+ else -+ { -+ /*************************************************************** -+ ** SWITCHING CONTEXT: 2D only command buffer. -+ */ -+ -+ /* Mark 3D as dirty. */ -+ Context->dirty3D = gcvTRUE; -+ -+ /* Compute the entry. */ -+ if (Command->pipeSelect == gcvPIPE_2D) -+ { -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ entryPhysical = (gctUINT8_PTR) contextBuffer->physical + pipeBytes; -+#endif -+ entryLogical = (gctUINT8_PTR) contextBuffer->logical + pipeBytes; -+ entryAddress = contextBuffer->address + pipeBytes; -+ entryBytes = Context->entryOffset3D - pipeBytes; -+ } -+ else -+ { -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ entryPhysical = (gctUINT8_PTR) contextBuffer->physical; -+#endif -+ entryLogical = (gctUINT8_PTR) contextBuffer->logical; -+ entryAddress = contextBuffer->address; -+ entryBytes = Context->entryOffset3D; -+ } -+ -+ /* Store the current context buffer. */ -+ Context->dirtyBuffer = contextBuffer; -+ -+ /* See if we have to switch pipes between the context -+ and command buffers. */ -+ if (commandBufferObject->entryPipe == gcvPIPE_2D) -+ { -+ /* Skip pipe switching sequence. */ -+ offset = pipeBytes; -+ } -+ else -+ { -+ /* The current hardware and the initial context pipes are -+ different, switch to the correct pipe. */ -+ gcmkONERROR(gckHARDWARE_PipeSelect( -+ Command->kernel->hardware, -+ commandBufferLogical, -+ commandBufferObject->entryPipe, -+ &pipeBytes -+ )); -+ -+ /* Do not skip pipe switching sequence. */ -+ offset = 0; -+ } -+ -+ /* 3D is not used, generate a LINK from the end of 2D part of -+ the context buffer to the command buffer. */ -+ gcmkONERROR(gckHARDWARE_Link( -+ hardware, -+ contextBuffer->link2D, -+ commandBufferAddress + offset, -+ commandBufferSize - offset, -+ &linkBytes -+ )); -+ } -+ } -+ -+ /* Not using 2D. */ -+ else -+ { -+ -+ /* Store the current context buffer. */ -+ Context->dirtyBuffer = contextBuffer; -+ -+ if (Context->dirty || commandBufferObject->using3D) -+ { -+ /*************************************************************** -+ ** SWITCHING CONTEXT: 3D only command buffer. -+ */ -+ -+ /* Reset 3D dirty flag. */ -+ Context->dirty3D = gcvFALSE; -+ -+ /* Determine context buffer entry offset. */ -+ offset = (Command->pipeSelect == gcvPIPE_3D) -+ -+ /* Skip pipe switching sequence. */ -+ ? Context->entryOffset3D + Context->pipeSelectBytes -+ -+ /* Do not skip pipe switching sequence. */ -+ : Context->entryOffset3D; -+ -+ /* Compute the entry. */ -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ entryPhysical = (gctUINT8_PTR) contextBuffer->physical + offset; -+#endif -+ entryLogical = (gctUINT8_PTR) contextBuffer->logical + offset; -+ entryAddress = contextBuffer->address + offset; -+ entryBytes = Context->bufferSize - offset; -+ -+ /* See if we have to switch pipes between the context -+ and command buffers. */ -+ if (commandBufferObject->entryPipe == gcvPIPE_3D) -+ { -+ /* Skip pipe switching sequence. */ -+ offset = pipeBytes; -+ } -+ else -+ { -+ /* The current hardware and the initial context pipes are -+ different, switch to the correct pipe. */ -+ gcmkONERROR(gckHARDWARE_PipeSelect( -+ Command->kernel->hardware, -+ commandBufferLogical, -+ commandBufferObject->entryPipe, -+ &pipeBytes -+ )); -+ -+ /* Do not skip pipe switching sequence. */ -+ offset = 0; -+ } -+ -+ /* Generate a LINK from the context buffer to -+ the command buffer. */ -+ gcmkONERROR(gckHARDWARE_Link( -+ hardware, -+ contextBuffer->link3D, -+ commandBufferAddress + offset, -+ commandBufferSize - offset, -+ &linkBytes -+ )); -+ } -+ else -+ { -+ /*************************************************************** -+ ** SWITCHING CONTEXT: "XD" command buffer - neither 2D nor 3D. -+ */ -+ -+ /* Mark 3D as dirty. */ -+ Context->dirty3D = gcvTRUE; -+ -+ /* Compute the entry. */ -+ if (Command->pipeSelect == gcvPIPE_3D) -+ { -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ entryPhysical -+ = (gctUINT8_PTR) contextBuffer->physical -+ + Context->entryOffsetXDFrom3D; -+#endif -+ entryLogical -+ = (gctUINT8_PTR) contextBuffer->logical -+ + Context->entryOffsetXDFrom3D; -+ -+ entryAddress -+ = contextBuffer->address -+ + Context->entryOffsetXDFrom3D; -+ -+ entryBytes -+ = Context->bufferSize -+ - Context->entryOffsetXDFrom3D; -+ } -+ else -+ { -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ entryPhysical -+ = (gctUINT8_PTR) contextBuffer->physical -+ + Context->entryOffsetXDFrom2D; -+#endif -+ entryLogical -+ = (gctUINT8_PTR) contextBuffer->logical -+ + Context->entryOffsetXDFrom2D; -+ -+ entryAddress -+ = contextBuffer->address -+ + Context->entryOffsetXDFrom2D; -+ -+ entryBytes -+ = Context->totalSize -+ - Context->entryOffsetXDFrom2D; -+ } -+ -+ /* See if we have to switch pipes between the context -+ and command buffers. */ -+ if (commandBufferObject->entryPipe == gcvPIPE_3D) -+ { -+ /* Skip pipe switching sequence. */ -+ offset = pipeBytes; -+ } -+ else -+ { -+ /* The current hardware and the initial context pipes are -+ different, switch to the correct pipe. */ -+ gcmkONERROR(gckHARDWARE_PipeSelect( -+ Command->kernel->hardware, -+ commandBufferLogical, -+ commandBufferObject->entryPipe, -+ &pipeBytes -+ )); -+ -+ /* Do not skip pipe switching sequence. */ -+ offset = 0; -+ } -+ -+ /* Generate a LINK from the context buffer to -+ the command buffer. */ -+ gcmkONERROR(gckHARDWARE_Link( -+ hardware, -+ contextBuffer->link3D, -+ commandBufferAddress + offset, -+ commandBufferSize - offset, -+ &linkBytes -+ )); -+ } -+ } -+ -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ /* Flush the context buffer cache. */ -+ gcmkONERROR(gckOS_CacheClean( -+ Command->os, -+ Command->kernelProcessID, -+ gcvNULL, -+ (gctUINT32)entryPhysical, -+ entryLogical, -+ entryBytes -+ )); -+#endif -+ -+ /* Update the current context. */ -+ Command->currContext = Context; -+ -+#if gcdDUMP_COMMAND -+ contextDumpLogical = entryLogical; -+ contextDumpBytes = entryBytes; -+#endif -+ -+#if gcdRECORD_COMMAND -+ gckRECORDER_Record( -+ Command->recorder, -+ gcvNULL, -+ 0xFFFFFFFF, -+ entryLogical, -+ entryBytes - 8 -+ ); -+#endif -+ } -+ -+ /* Same context. */ -+ else -+ { -+ /* Determine context entry and exit points. */ -+ if (commandBufferObject->using2D && Context->dirty2D) -+ { -+ /* Reset 2D dirty flag. */ -+ Context->dirty2D = gcvFALSE; -+ -+ /* Get the "dirty" context buffer. */ -+ contextBuffer = Context->dirtyBuffer; -+ -+ if (commandBufferObject->using3D && Context->dirty3D) -+ { -+ /* Reset 3D dirty flag. */ -+ Context->dirty3D = gcvFALSE; -+ -+ /* Compute the entry. */ -+ if (Command->pipeSelect == gcvPIPE_2D) -+ { -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ entryPhysical = (gctUINT8_PTR) contextBuffer->physical + pipeBytes; -+#endif -+ entryLogical = (gctUINT8_PTR) contextBuffer->logical + pipeBytes; -+ entryAddress = contextBuffer->address + pipeBytes; -+ entryBytes = Context->bufferSize - pipeBytes; -+ } -+ else -+ { -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ entryPhysical = (gctUINT8_PTR) contextBuffer->physical; -+#endif -+ entryLogical = (gctUINT8_PTR) contextBuffer->logical; -+ entryAddress = contextBuffer->address; -+ entryBytes = Context->bufferSize; -+ } -+ -+ /* See if we have to switch pipes between the context -+ and command buffers. */ -+ if (commandBufferObject->entryPipe == gcvPIPE_3D) -+ { -+ /* Skip pipe switching sequence. */ -+ offset = pipeBytes; -+ } -+ else -+ { -+ /* The current hardware and the initial context pipes are -+ different, switch to the correct pipe. */ -+ gcmkONERROR(gckHARDWARE_PipeSelect( -+ Command->kernel->hardware, -+ commandBufferLogical, -+ commandBufferObject->entryPipe, -+ &pipeBytes -+ )); -+ -+ /* Do not skip pipe switching sequence. */ -+ offset = 0; -+ } -+ -+ /* Ensure the NOP between 2D and 3D is in place so that the -+ execution falls through from 2D to 3D. */ -+ gcmkONERROR(gckHARDWARE_Nop( -+ hardware, -+ contextBuffer->link2D, -+ &nopBytes -+ )); -+ -+ /* Generate a LINK from the context buffer to -+ the command buffer. */ -+ gcmkONERROR(gckHARDWARE_Link( -+ hardware, -+ contextBuffer->link3D, -+ commandBufferAddress + offset, -+ commandBufferSize - offset, -+ &linkBytes -+ )); -+ } -+ else -+ { -+ /* Compute the entry. */ -+ if (Command->pipeSelect == gcvPIPE_2D) -+ { -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ entryPhysical = (gctUINT8_PTR) contextBuffer->physical + pipeBytes; -+#endif -+ entryLogical = (gctUINT8_PTR) contextBuffer->logical + pipeBytes; -+ entryAddress = contextBuffer->address + pipeBytes; -+ entryBytes = Context->entryOffset3D - pipeBytes; -+ } -+ else -+ { -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ entryPhysical = (gctUINT8_PTR) contextBuffer->physical; -+#endif -+ entryLogical = (gctUINT8_PTR) contextBuffer->logical; -+ entryAddress = contextBuffer->address; -+ entryBytes = Context->entryOffset3D; -+ } -+ -+ /* See if we have to switch pipes between the context -+ and command buffers. */ -+ if (commandBufferObject->entryPipe == gcvPIPE_2D) -+ { -+ /* Skip pipe switching sequence. */ -+ offset = pipeBytes; -+ } -+ else -+ { -+ /* The current hardware and the initial context pipes are -+ different, switch to the correct pipe. */ -+ gcmkONERROR(gckHARDWARE_PipeSelect( -+ Command->kernel->hardware, -+ commandBufferLogical, -+ commandBufferObject->entryPipe, -+ &pipeBytes -+ )); -+ -+ /* Do not skip pipe switching sequence. */ -+ offset = 0; -+ } -+ -+ /* 3D is not used, generate a LINK from the end of 2D part of -+ the context buffer to the command buffer. */ -+ gcmkONERROR(gckHARDWARE_Link( -+ hardware, -+ contextBuffer->link2D, -+ commandBufferAddress + offset, -+ commandBufferSize - offset, -+ &linkBytes -+ )); -+ } -+ } -+ else -+ { -+ if (commandBufferObject->using3D && Context->dirty3D) -+ { -+ /* Reset 3D dirty flag. */ -+ Context->dirty3D = gcvFALSE; -+ -+ /* Get the "dirty" context buffer. */ -+ contextBuffer = Context->dirtyBuffer; -+ -+ /* Determine context buffer entry offset. */ -+ offset = (Command->pipeSelect == gcvPIPE_3D) -+ -+ /* Skip pipe switching sequence. */ -+ ? Context->entryOffset3D + pipeBytes -+ -+ /* Do not skip pipe switching sequence. */ -+ : Context->entryOffset3D; -+ -+ /* Compute the entry. */ -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ entryPhysical = (gctUINT8_PTR) contextBuffer->physical + offset; -+#endif -+ entryLogical = (gctUINT8_PTR) contextBuffer->logical + offset; -+ entryAddress = contextBuffer->address + offset; -+ entryBytes = Context->bufferSize - offset; -+ -+ /* See if we have to switch pipes between the context -+ and command buffers. */ -+ if (commandBufferObject->entryPipe == gcvPIPE_3D) -+ { -+ /* Skip pipe switching sequence. */ -+ offset = pipeBytes; -+ } -+ else -+ { -+ /* The current hardware and the initial context pipes are -+ different, switch to the correct pipe. */ -+ gcmkONERROR(gckHARDWARE_PipeSelect( -+ Command->kernel->hardware, -+ commandBufferLogical, -+ commandBufferObject->entryPipe, -+ &pipeBytes -+ )); -+ -+ /* Do not skip pipe switching sequence. */ -+ offset = 0; -+ } -+ -+ /* Generate a LINK from the context buffer to -+ the command buffer. */ -+ gcmkONERROR(gckHARDWARE_Link( -+ hardware, -+ contextBuffer->link3D, -+ commandBufferAddress + offset, -+ commandBufferSize - offset, -+ &linkBytes -+ )); -+ } -+ else -+ { -+ /* See if we have to switch pipes for the command buffer. */ -+ if (commandBufferObject->entryPipe == Command->pipeSelect) -+ { -+ /* Skip pipe switching sequence. */ -+ offset = pipeBytes; -+ } -+ else -+ { -+ /* The current hardware and the entry command buffer pipes -+ ** are different, switch to the correct pipe. */ -+ gcmkONERROR(gckHARDWARE_PipeSelect( -+ Command->kernel->hardware, -+ commandBufferLogical, -+ commandBufferObject->entryPipe, -+ &pipeBytes -+ )); -+ -+ /* Do not skip pipe switching sequence. */ -+ offset = 0; -+ } -+ -+ /* Compute the entry. */ -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ entryPhysical = (gctUINT8_PTR) commandBufferPhysical + offset; -+#endif -+ entryLogical = commandBufferLogical + offset; -+ entryAddress = commandBufferAddress + offset; -+ entryBytes = commandBufferSize - offset; -+ } -+ } -+ } -+ -+#if gcdDUMP_COMMAND -+ bufferDumpLogical = commandBufferLogical + offset; -+ bufferDumpBytes = commandBufferSize - offset; -+#endif -+ -+ /* Determine the location to jump to for the command buffer being -+ ** scheduled. */ -+ if (Command->newQueue) -+ { -+ /* New command queue, jump to the beginning of it. */ -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ exitPhysical = Command->physical; -+#endif -+ -+ exitLogical = Command->logical; -+ exitAddress = Command->address; -+ exitBytes = Command->offset + waitLinkBytes; -+ } -+ else -+ { -+ /* Still within the preexisting command queue, jump to the new -+ WAIT/LINK command sequence. */ -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ exitPhysical = waitLinkPhysical; -+#endif -+ exitLogical = waitLinkLogical; -+ exitAddress = waitLinkAddress; -+ exitBytes = waitLinkBytes; -+ } -+ -+ /* Add a new WAIT/LINK command sequence. When the command buffer which is -+ currently being scheduled is fully executed by the GPU, the FE will -+ jump to this WAIT/LINK sequence. */ -+ gcmkONERROR(gckHARDWARE_WaitLink( -+ hardware, -+ waitLinkLogical, -+ offset, -+ &waitLinkBytes, -+ &waitOffset, -+ &waitSize -+ )); -+ -+ /* Compute the location if WAIT command. */ -+ waitPhysical = (gctUINT8_PTR) waitLinkPhysical + waitOffset; -+ waitLogical = (gctUINT8_PTR) waitLinkLogical + waitOffset; -+ -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ /* Flush the command queue cache. */ -+ gcmkONERROR(gckOS_CacheClean( -+ Command->os, -+ Command->kernelProcessID, -+ gcvNULL, -+ (gctUINT32)exitPhysical, -+ exitLogical, -+ exitBytes -+ )); -+#endif -+ -+ /* Determine the location of the LINK command in the command buffer. */ -+ commandBufferLink -+ = (gctUINT8_PTR) gcmUINT64_TO_PTR(commandBufferObject->logical) -+ + commandBufferObject->offset; -+ -+ /* Generate a LINK from the end of the command buffer being scheduled -+ back to the kernel command queue. */ -+ gcmkONERROR(gckHARDWARE_Link( -+ hardware, -+ commandBufferLink, -+ exitAddress, -+ exitBytes, -+ &linkBytes -+ )); -+ -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ /* Flush the command buffer cache. */ -+ gcmkONERROR(gckOS_CacheClean( -+ Command->os, -+ ProcessID, -+ gcvNULL, -+ (gctUINT32)commandBufferPhysical, -+ commandBufferLogical, -+ commandBufferSize -+ )); -+#endif -+ -+#if gcdRECORD_COMMAND -+ gckRECORDER_Record( -+ Command->recorder, -+ commandBufferLogical + offset, -+ commandBufferSize - offset - 8, -+ gcvNULL, -+ 0xFFFFFFFF -+ ); -+ -+ gckRECORDER_AdvanceIndex(Command->recorder, Command->commitStamp); -+ -+ Command->commitStamp++; -+#endif -+ -+ /* Generate a LINK from the previous WAIT/LINK command sequence to the -+ entry determined above (either the context or the command buffer). -+ This LINK replaces the WAIT instruction from the previous WAIT/LINK -+ pair, therefore we use WAIT metrics for generation of this LINK. -+ This action will execute the entire sequence. */ -+ gcmkONERROR(gckHARDWARE_Link( -+ hardware, -+ Command->waitLogical, -+ entryAddress, -+ entryBytes, -+ &Command->waitSize -+ )); -+ -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ /* Flush the cache for the link. */ -+ gcmkONERROR(gckOS_CacheClean( -+ Command->os, -+ Command->kernelProcessID, -+ gcvNULL, -+ (gctUINT32)Command->waitPhysical, -+ Command->waitLogical, -+ Command->waitSize -+ )); -+#endif -+ -+ gcmkDUMPCOMMAND( -+ Command->os, -+ Command->waitLogical, -+ Command->waitSize, -+ gceDUMP_BUFFER_LINK, -+ gcvFALSE -+ ); -+ -+ gcmkDUMPCOMMAND( -+ Command->os, -+ contextDumpLogical, -+ contextDumpBytes, -+ gceDUMP_BUFFER_CONTEXT, -+ gcvFALSE -+ ); -+ -+ gcmkDUMPCOMMAND( -+ Command->os, -+ bufferDumpLogical, -+ bufferDumpBytes, -+ gceDUMP_BUFFER_USER, -+ gcvFALSE -+ ); -+ -+ gcmkDUMPCOMMAND( -+ Command->os, -+ waitLinkLogical, -+ waitLinkBytes, -+ gceDUMP_BUFFER_WAITLINK, -+ gcvFALSE -+ ); -+ -+ /* Update the current pipe. */ -+ Command->pipeSelect = commandBufferObject->exitPipe; -+ -+ /* Update command queue offset. */ -+ Command->offset += waitLinkBytes; -+ Command->newQueue = gcvFALSE; -+ -+ /* Update address of last WAIT. */ -+ Command->waitPhysical = waitPhysical; -+ Command->waitLogical = waitLogical; -+ Command->waitSize = waitSize; -+ -+ /* Update queue tail pointer. */ -+ gcmkONERROR(gckHARDWARE_UpdateQueueTail( -+ hardware, Command->logical, Command->offset -+ )); -+ -+#if gcdDUMP_COMMAND -+ gcmkPRINT("@[kernel.commit]"); -+#endif -+#endif /* gcdNULL_DRIVER */ -+ -+ /* Release the context switching mutex. */ -+ gcmkONERROR(gckOS_ReleaseMutex(Command->os, Command->mutexContext)); -+ contextAcquired = gcvFALSE; -+ -+ /* Release the command queue. */ -+ gcmkONERROR(gckCOMMAND_ExitCommit(Command, gcvFALSE)); -+ commitEntered = gcvFALSE; -+ -+#if VIVANTE_PROFILER_CONTEXT -+ if(sequenceAcquired) -+ { -+ gcmkONERROR(gckCOMMAND_Stall(Command, gcvTRUE)); -+ if (Command->currContext) -+ { -+ gcmkONERROR(gckHARDWARE_UpdateContextProfile( -+ hardware, -+ Command->currContext)); -+ } -+ -+ /* Release the context switching mutex. */ -+ gcmkONERROR(gckOS_ReleaseMutex(Command->os, Command->mutexContextSeq)); -+ sequenceAcquired = gcvFALSE; -+ } -+#endif -+ -+ /* Loop while there are records in the queue. */ -+ while (EventQueue != gcvNULL) -+ { -+ if (needCopy) -+ { -+ /* Point to stack record. */ -+ eventRecord = &_eventRecord; -+ -+ /* Copy the data from the client. */ -+ gcmkONERROR(gckOS_CopyFromUserData( -+ Command->os, eventRecord, EventQueue, gcmSIZEOF(gcsQUEUE) -+ )); -+ } -+ else -+ { -+ /* Map record into kernel memory. */ -+ gcmkONERROR(gckOS_MapUserPointer(Command->os, -+ EventQueue, -+ gcmSIZEOF(gcsQUEUE), -+ &pointer)); -+ -+ eventRecord = pointer; -+ } -+ -+ /* Append event record to event queue. */ -+ gcmkONERROR(gckEVENT_AddList( -+ Command->kernel->eventObj, &eventRecord->iface, gcvKERNEL_PIXEL, gcvTRUE, gcvFALSE -+ )); -+ -+ /* Next record in the queue. */ -+ nextEventRecord = gcmUINT64_TO_PTR(eventRecord->next); -+ -+ if (!needCopy) -+ { -+ /* Unmap record from kernel memory. */ -+ gcmkONERROR(gckOS_UnmapUserPointer( -+ Command->os, EventQueue, gcmSIZEOF(gcsQUEUE), (gctPOINTER *) eventRecord -+ )); -+ -+ eventRecord = gcvNULL; -+ } -+ -+ EventQueue = nextEventRecord; -+ } -+ -+ if (Command->kernel->eventObj->queueHead == gcvNULL -+ && Command->kernel->hardware->powerManagement == gcvTRUE -+ ) -+ { -+ /* Commit done event by which work thread knows all jobs done. */ -+ gcmkVERIFY_OK( -+ gckEVENT_CommitDone(Command->kernel->eventObj, gcvKERNEL_PIXEL)); -+ } -+ -+ /* Submit events. */ -+ status = gckEVENT_Submit(Command->kernel->eventObj, gcvTRUE, gcvFALSE, gcvTRUE); -+ if (status == gcvSTATUS_INTERRUPTED) -+ { -+ gcmkTRACE( -+ gcvLEVEL_INFO, -+ "%s(%d): Intterupted in gckEVENT_Submit", -+ __FUNCTION__, __LINE__ -+ ); -+ status = gcvSTATUS_OK; -+ } -+ else -+ { -+ gcmkONERROR(status); -+ } -+ -+ /* Unmap the command buffer pointer. */ -+ if (commandBufferMapped) -+ { -+ gcmkONERROR(gckOS_UnmapUserPointer( -+ Command->os, -+ CommandBuffer, -+ gcmSIZEOF(struct _gcoCMDBUF), -+ commandBufferObject -+ )); -+ -+ commandBufferMapped = gcvFALSE; -+ } -+ -+ /* Return status. */ -+ gcmkFOOTER(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if ((eventRecord != gcvNULL) && !needCopy) -+ { -+ /* Roll back. */ -+ gcmkVERIFY_OK(gckOS_UnmapUserPointer( -+ Command->os, -+ EventQueue, -+ gcmSIZEOF(gcsQUEUE), -+ (gctPOINTER *) eventRecord -+ )); -+ } -+ -+ if (contextAcquired) -+ { -+ /* Release the context switching mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Command->os, Command->mutexContext)); -+ } -+ -+ if (commitEntered) -+ { -+ /* Release the command queue mutex. */ -+ gcmkVERIFY_OK(gckCOMMAND_ExitCommit(Command, gcvFALSE)); -+ } -+ -+#if VIVANTE_PROFILER_CONTEXT -+ if (sequenceAcquired) -+ { -+ /* Release the context sequence mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Command->os, Command->mutexContextSeq)); -+ } -+#endif -+ -+ /* Unmap the command buffer pointer. */ -+ if (commandBufferMapped) -+ { -+ gcmkVERIFY_OK(gckOS_UnmapUserPointer( -+ Command->os, -+ CommandBuffer, -+ gcmSIZEOF(struct _gcoCMDBUF), -+ commandBufferObject -+ )); -+ } -+ -+ /* Return status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckCOMMAND_Reserve -+** -+** Reserve space in the command queue. Also acquire the command queue mutex. -+** -+** INPUT: -+** -+** gckCOMMAND Command -+** Pointer to an gckCOMMAND object. -+** -+** gctSIZE_T RequestedBytes -+** Number of bytes previously reserved. -+** -+** OUTPUT: -+** -+** gctPOINTER * Buffer -+** Pointer to a variable that will receive the address of the reserved -+** space. -+** -+** gctSIZE_T * BufferSize -+** Pointer to a variable that will receive the number of bytes -+** available in the command queue. -+*/ -+gceSTATUS -+gckCOMMAND_Reserve( -+ IN gckCOMMAND Command, -+ IN gctUINT32 RequestedBytes, -+ OUT gctPOINTER * Buffer, -+ OUT gctUINT32 * BufferSize -+ ) -+{ -+ gceSTATUS status; -+ gctUINT32 bytes; -+ gctUINT32 requiredBytes; -+ gctUINT32 requestedAligned; -+ -+ gcmkHEADER_ARG("Command=0x%x RequestedBytes=%lu", Command, RequestedBytes); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND); -+ -+ /* Compute aligned number of reuested bytes. */ -+ requestedAligned = gcmALIGN(RequestedBytes, Command->alignment); -+ -+ /* Another WAIT/LINK command sequence will have to be appended after -+ the requested area being reserved. Compute the number of bytes -+ required for WAIT/LINK at the location after the reserved area. */ -+ gcmkONERROR(gckHARDWARE_WaitLink( -+ Command->kernel->hardware, -+ gcvNULL, -+ Command->offset + requestedAligned, -+ &requiredBytes, -+ gcvNULL, -+ gcvNULL -+ )); -+ -+ /* Compute total number of bytes required. */ -+ requiredBytes += requestedAligned; -+ -+ /* Compute number of bytes available in command queue. */ -+ bytes = Command->pageSize - Command->offset; -+ -+ /* Is there enough space in the current command queue? */ -+ if (bytes < requiredBytes) -+ { -+ /* Create a new command queue. */ -+ gcmkONERROR(_NewQueue(Command)); -+ -+ /* Recompute the number of bytes in the new kernel command queue. */ -+ bytes = Command->pageSize - Command->offset; -+ -+ /* Still not enough space? */ -+ if (bytes < requiredBytes) -+ { -+ /* Rare case, not enough room in command queue. */ -+ gcmkONERROR(gcvSTATUS_BUFFER_TOO_SMALL); -+ } -+ } -+ -+ /* Return pointer to empty slot command queue. */ -+ *Buffer = (gctUINT8 *) Command->logical + Command->offset; -+ -+ /* Return number of bytes left in command queue. */ -+ *BufferSize = bytes; -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Buffer=0x%x *BufferSize=%lu", *Buffer, *BufferSize); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckCOMMAND_Execute -+** -+** Execute a previously reserved command queue by appending a WAIT/LINK command -+** sequence after it and modifying the last WAIT into a LINK command. The -+** command FIFO mutex will be released whether this function succeeds or not. -+** -+** INPUT: -+** -+** gckCOMMAND Command -+** Pointer to an gckCOMMAND object. -+** -+** gctSIZE_T RequestedBytes -+** Number of bytes previously reserved. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckCOMMAND_Execute( -+ IN gckCOMMAND Command, -+ IN gctUINT32 RequestedBytes -+ ) -+{ -+ gceSTATUS status; -+ -+ gctPHYS_ADDR waitLinkPhysical; -+ gctUINT8_PTR waitLinkLogical; -+ gctUINT32 waitLinkOffset; -+ gctUINT32 waitLinkBytes; -+ -+ gctPHYS_ADDR waitPhysical; -+ gctPOINTER waitLogical; -+ gctUINT32 waitOffset; -+ gctUINT32 waitBytes; -+ -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ gctPHYS_ADDR execPhysical; -+#endif -+ gctPOINTER execLogical; -+ gctUINT32 execAddress; -+ gctUINT32 execBytes; -+ -+ gcmkHEADER_ARG("Command=0x%x RequestedBytes=%lu", Command, RequestedBytes); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND); -+ -+ /* Compute offset for WAIT/LINK. */ -+ waitLinkOffset = Command->offset + RequestedBytes; -+ -+ /* Compute number of bytes left in command queue. */ -+ waitLinkBytes = Command->pageSize - waitLinkOffset; -+ -+ /* Compute the location if WAIT/LINK command sequence. */ -+ waitLinkPhysical = (gctUINT8_PTR) Command->physical + waitLinkOffset; -+ waitLinkLogical = (gctUINT8_PTR) Command->logical + waitLinkOffset; -+ -+ /* Append WAIT/LINK in command queue. */ -+ gcmkONERROR(gckHARDWARE_WaitLink( -+ Command->kernel->hardware, -+ waitLinkLogical, -+ waitLinkOffset, -+ &waitLinkBytes, -+ &waitOffset, -+ &waitBytes -+ )); -+ -+ /* Compute the location if WAIT command. */ -+ waitPhysical = (gctUINT8_PTR) waitLinkPhysical + waitOffset; -+ waitLogical = waitLinkLogical + waitOffset; -+ -+ /* Determine the location to jump to for the command buffer being -+ ** scheduled. */ -+ if (Command->newQueue) -+ { -+ /* New command queue, jump to the beginning of it. */ -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ execPhysical = Command->physical; -+#endif -+ execLogical = Command->logical; -+ execAddress = Command->address; -+ execBytes = waitLinkOffset + waitLinkBytes; -+ } -+ else -+ { -+ /* Still within the preexisting command queue, jump directly to the -+ reserved area. */ -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ execPhysical = (gctUINT8 *) Command->physical + Command->offset; -+#endif -+ execLogical = (gctUINT8 *) Command->logical + Command->offset; -+ execAddress = Command->address + Command->offset; -+ execBytes = RequestedBytes + waitLinkBytes; -+ } -+ -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ /* Flush the cache. */ -+ gcmkONERROR(gckOS_CacheClean( -+ Command->os, -+ Command->kernelProcessID, -+ gcvNULL, -+ (gctUINT32)execPhysical, -+ execLogical, -+ execBytes -+ )); -+#endif -+ -+ /* Convert the last WAIT into a LINK. */ -+ gcmkONERROR(gckHARDWARE_Link( -+ Command->kernel->hardware, -+ Command->waitLogical, -+ execAddress, -+ execBytes, -+ &Command->waitSize -+ )); -+ -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ /* Flush the cache. */ -+ gcmkONERROR(gckOS_CacheClean( -+ Command->os, -+ Command->kernelProcessID, -+ gcvNULL, -+ (gctUINT32)Command->waitPhysical, -+ Command->waitLogical, -+ Command->waitSize -+ )); -+#endif -+ -+ gcmkDUMPCOMMAND( -+ Command->os, -+ Command->waitLogical, -+ Command->waitSize, -+ gceDUMP_BUFFER_LINK, -+ gcvFALSE -+ ); -+ -+ gcmkDUMPCOMMAND( -+ Command->os, -+ execLogical, -+ execBytes, -+ gceDUMP_BUFFER_KERNEL, -+ gcvFALSE -+ ); -+ -+ /* Update the pointer to the last WAIT. */ -+ Command->waitPhysical = waitPhysical; -+ Command->waitLogical = waitLogical; -+ Command->waitSize = waitBytes; -+ -+ /* Update the command queue. */ -+ Command->offset += RequestedBytes + waitLinkBytes; -+ Command->newQueue = gcvFALSE; -+ -+ /* Update queue tail pointer. */ -+ gcmkONERROR(gckHARDWARE_UpdateQueueTail( -+ Command->kernel->hardware, Command->logical, Command->offset -+ )); -+ -+#if gcdDUMP_COMMAND -+ gcmkPRINT("@[kernel.execute]"); -+#endif -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckCOMMAND_Stall -+** -+** The calling thread will be suspended until the command queue has been -+** completed. -+** -+** INPUT: -+** -+** gckCOMMAND Command -+** Pointer to an gckCOMMAND object. -+** -+** gctBOOL FromPower -+** Determines whether the call originates from inside the power -+** management or not. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckCOMMAND_Stall( -+ IN gckCOMMAND Command, -+ IN gctBOOL FromPower -+ ) -+{ -+#if gcdNULL_DRIVER -+ /* Do nothing with infinite hardware. */ -+ return gcvSTATUS_OK; -+#else -+ gckOS os; -+ gckHARDWARE hardware; -+ gckEVENT eventObject; -+ gceSTATUS status; -+ gctSIGNAL signal = gcvNULL; -+ gctUINT timer = 0; -+ -+ gcmkHEADER_ARG("Command=0x%x", Command); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND); -+ -+ /* Extract the gckOS object pointer. */ -+ os = Command->os; -+ gcmkVERIFY_OBJECT(os, gcvOBJ_OS); -+ -+ /* Extract the gckHARDWARE object pointer. */ -+ hardware = Command->kernel->hardware; -+ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE); -+ -+ /* Extract the gckEVENT object pointer. */ -+ eventObject = Command->kernel->eventObj; -+ gcmkVERIFY_OBJECT(eventObject, gcvOBJ_EVENT); -+ -+ /* Allocate the signal. */ -+ gcmkONERROR(gckOS_CreateSignal(os, gcvTRUE, &signal)); -+ -+ /* Append the EVENT command to trigger the signal. */ -+ gcmkONERROR(gckEVENT_Signal(eventObject, signal, gcvKERNEL_PIXEL)); -+ -+ /* Submit the event queue. */ -+ gcmkONERROR(gckEVENT_Submit(eventObject, gcvTRUE, FromPower, gcvFALSE)); -+ -+#if gcdDUMP_COMMAND -+ gcmkPRINT("@[kernel.stall]"); -+#endif -+ -+ if (status == gcvSTATUS_CHIP_NOT_READY) -+ { -+ /* Error. */ -+ goto OnError; -+ } -+ -+ do -+ { -+ /* Wait for the signal. */ -+ status = gckOS_WaitSignal(os, signal, gcdGPU_ADVANCETIMER); -+ -+ if (status == gcvSTATUS_TIMEOUT) -+ { -+#if gcmIS_DEBUG(gcdDEBUG_CODE) -+ gctUINT32 idle; -+ -+ /* Read idle register. */ -+ gcmkVERIFY_OK(gckHARDWARE_GetIdle( -+ hardware, gcvFALSE, &idle -+ )); -+ -+ gcmkTRACE( -+ gcvLEVEL_ERROR, -+ "%s(%d): idle=%08x", -+ __FUNCTION__, __LINE__, idle -+ ); -+ -+ gcmkVERIFY_OK(gckOS_MemoryBarrier(os, gcvNULL)); -+#endif -+ -+ /* Advance timer. */ -+ timer += gcdGPU_ADVANCETIMER; -+ } -+ else if (status == gcvSTATUS_INTERRUPTED) -+ { -+ gcmkONERROR(gcvSTATUS_INTERRUPTED); -+ } -+ -+ } -+ while (gcmIS_ERROR(status)); -+ -+ /* Bail out on timeout. */ -+ if (gcmIS_ERROR(status)) -+ { -+ /* Broadcast the stuck GPU. */ -+ gcmkONERROR(gckOS_Broadcast( -+ os, hardware, gcvBROADCAST_GPU_STUCK -+ )); -+ } -+ -+ /* Delete the signal. */ -+ gcmkVERIFY_OK(gckOS_DestroySignal(os, signal)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (signal != gcvNULL) -+ { -+ /* Free the signal. */ -+ gcmkVERIFY_OK(gckOS_DestroySignal(os, signal)); -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+#endif -+} -+ -+/******************************************************************************* -+** -+** gckCOMMAND_Attach -+** -+** Attach user process. -+** -+** INPUT: -+** -+** gckCOMMAND Command -+** Pointer to a gckCOMMAND object. -+** -+** gctUINT32 ProcessID -+** Current process ID. -+** -+** OUTPUT: -+** -+** gckCONTEXT * Context -+** Pointer to a variable that will receive a pointer to a new -+** gckCONTEXT object. -+** -+** gctSIZE_T * StateCount -+** Pointer to a variable that will receive the number of states -+** in the context buffer. -+*/ -+#if (gcdENABLE_3D || gcdENABLE_2D) -+gceSTATUS -+gckCOMMAND_Attach( -+ IN gckCOMMAND Command, -+ OUT gckCONTEXT * Context, -+ OUT gctSIZE_T * StateCount, -+ IN gctUINT32 ProcessID -+ ) -+{ -+ gceSTATUS status; -+ gctBOOL acquired = gcvFALSE; -+ -+ gcmkHEADER_ARG("Command=0x%x", Command); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND); -+ -+ /* Acquire the context switching mutex. */ -+ gcmkONERROR(gckOS_AcquireMutex( -+ Command->os, Command->mutexContext, gcvINFINITE -+ )); -+ acquired = gcvTRUE; -+ -+ /* Construct a gckCONTEXT object. */ -+ gcmkONERROR(gckCONTEXT_Construct( -+ Command->os, -+ Command->kernel->hardware, -+ ProcessID, -+ Context -+ )); -+ -+ /* Return the number of states in the context. */ -+ * StateCount = (* Context)->stateCount; -+ -+ /* Release the context switching mutex. */ -+ gcmkONERROR(gckOS_ReleaseMutex(Command->os, Command->mutexContext)); -+ acquired = gcvFALSE; -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Context=0x%x", *Context); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Release mutex. */ -+ if (acquired) -+ { -+ /* Release the context switching mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Command->os, Command->mutexContext)); -+ acquired = gcvFALSE; -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+#endif -+ -+/******************************************************************************* -+** -+** gckCOMMAND_Detach -+** -+** Detach user process. -+** -+** INPUT: -+** -+** gckCOMMAND Command -+** Pointer to a gckCOMMAND object. -+** -+** gckCONTEXT Context -+** Pointer to a gckCONTEXT object to be destroyed. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckCOMMAND_Detach( -+ IN gckCOMMAND Command, -+ IN gckCONTEXT Context -+ ) -+{ -+ gceSTATUS status; -+ gctBOOL acquired = gcvFALSE; -+ -+ gcmkHEADER_ARG("Command=0x%x Context=0x%x", Command, Context); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND); -+ -+ /* Acquire the context switching mutex. */ -+ gcmkONERROR(gckOS_AcquireMutex( -+ Command->os, Command->mutexContext, gcvINFINITE -+ )); -+ acquired = gcvTRUE; -+ -+ /* Construct a gckCONTEXT object. */ -+ gcmkONERROR(gckCONTEXT_Destroy(Context)); -+ -+ if (Command->currContext == Context) -+ { -+ /* Detach from gckCOMMAND object if the destoryed context is current context. */ -+ Command->currContext = gcvNULL; -+ } -+ -+ /* Release the context switching mutex. */ -+ gcmkONERROR(gckOS_ReleaseMutex(Command->os, Command->mutexContext)); -+ acquired = gcvFALSE; -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Release mutex. */ -+ if (acquired) -+ { -+ /* Release the context switching mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Command->os, Command->mutexContext)); -+ acquired = gcvFALSE; -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckCOMMAND_DumpExecutingBuffer -+** -+** Dump the command buffer which GPU is executing. -+** -+** INPUT: -+** -+** gckCOMMAND Command -+** Pointer to a gckCOMMAND object. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckCOMMAND_DumpExecutingBuffer( -+ IN gckCOMMAND Command -+ ) -+{ -+ gceSTATUS status; -+ gckVIRTUAL_COMMAND_BUFFER_PTR buffer; -+ gctUINT32 gpuAddress; -+ gctSIZE_T pageCount; -+ gctPOINTER entry; -+ gckOS os = Command->os; -+ gckKERNEL kernel = Command->kernel; -+ gctINT pid; -+ gctUINT32 i, rear; -+ gctUINT32 start, end; -+ gctUINT32 dumpFront, dumpRear; -+ gckLINKQUEUE queue = &kernel->hardware->linkQueue; -+ gckLINKQUEUE queueMirror; -+ gctUINT32 bytes; -+ gckLINKDATA linkData; -+ -+ gcmkPRINT("**************************\n"); -+ gcmkPRINT("**** COMMAND BUF DUMP ****\n"); -+ gcmkPRINT("**************************\n"); -+ -+ gcmkVERIFY_OK(gckOS_ReadRegisterEx(os, kernel->core, 0x664, &gpuAddress)); -+ -+ gcmkPRINT("DMA Address 0x%08X", gpuAddress); -+ -+ if (Command->kernel->stuckDump > gcdSTUCK_DUMP_MIDDLE) -+ { -+ gcmkPRINT("Dump Level is %d", Command->kernel->stuckDump); -+ -+ /* Duplicate queue because it will be changed.*/ -+ gcmkONERROR(gckOS_AllocateMemory(os, -+ sizeof(struct _gckLINKQUEUE), -+ (gctPOINTER *)&queueMirror)); -+ -+ gckOS_MemCopy(queueMirror, -+ queue, -+ sizeof(struct _gckLINKQUEUE)); -+ -+ /* If kernel command buffer link to a context buffer, then link to a user command -+ ** buffer, the second link will be in queue first, so we must fix this. -+ ** In Queue: C1 U1 U2 C2 U3 U4 U5 C3 -+ ** Real: C1 X1 U1 C2 U2 U3 U4 C3 U5 -+ ** Command buffer X1 which is after C1 is out of queue, so C1 is meaningless. -+ */ -+ for (i = 0; i < gcdLINK_QUEUE_SIZE; i++) -+ { -+ gckLINKQUEUE_GetData(queueMirror, i, &linkData); -+ -+ status = gckKERNEL_QueryGPUAddress(kernel, linkData->start, &buffer); -+ -+ if (gcmIS_ERROR(status)) -+ { -+ /* Can't find it in virtual command buffer list, ignore it. */ -+ continue; -+ } -+ -+ if (buffer->kernelLogical) -+ { -+ /* It is a context buffer. */ -+ if (i == 0) -+ { -+ /* The real command buffer is out, so clear this slot. */ -+ linkData->start = 0; -+ linkData->end = 0; -+ linkData->pid = 0; -+ } -+ else -+ { -+ /* switch context buffer and command buffer. */ -+ struct _gckLINKDATA tmp = *linkData; -+ gckLINKDATA linkDataPrevious; -+ -+ gckLINKQUEUE_GetData(queueMirror, i - 1, &linkDataPrevious); -+ *linkData = *linkDataPrevious; -+ *linkDataPrevious = tmp; -+ } -+ } -+ } -+ -+ /* Clear search result. */ -+ dumpFront = dumpRear = gcvINFINITE; -+ -+ gcmkPRINT("Link Stack:"); -+ -+ /* Search stuck address in link queue from rear. */ -+ rear = gcdLINK_QUEUE_SIZE - 1; -+ for (i = 0; i < gcdLINK_QUEUE_SIZE; i++) -+ { -+ gckLINKQUEUE_GetData(queueMirror, rear, &linkData); -+ -+ start = linkData->start; -+ end = linkData->end; -+ pid = linkData->pid; -+ -+ if (gpuAddress >= start && gpuAddress < end) -+ { -+ /* Find latest matched command buffer. */ -+ gcmkPRINT(" %d, [%08X - %08X]", pid, start, end); -+ -+ /* Initiliaze dump information. */ -+ dumpFront = dumpRear = rear; -+ } -+ -+ /* Advance to previous one. */ -+ rear--; -+ -+ if (dumpFront != gcvINFINITE) -+ { -+ break; -+ } -+ } -+ -+ if (dumpFront == gcvINFINITE) -+ { -+ /* Can't find matched record in link queue, dump kernel command buffer. */ -+ _DumpKernelCommandBuffer(Command); -+ -+ /* Free local copy. */ -+ gcmkOS_SAFE_FREE(os, queueMirror); -+ return gcvSTATUS_OK; -+ } -+ -+ /* Search the last context buffer linked. */ -+ while (rear > 0) -+ { -+ gckLINKQUEUE_GetData(queueMirror, rear, &linkData); -+ -+ gcmkPRINT(" %d, [%08X - %08X]", -+ linkData->pid, -+ linkData->start, -+ linkData->end); -+ -+ status = gckKERNEL_QueryGPUAddress(kernel, linkData->start, &buffer); -+ -+ if (gcmIS_SUCCESS(status) && buffer->kernelLogical) -+ { -+ /* Find a context buffer. */ -+ dumpFront = rear; -+ break; -+ } -+ -+ rear--; -+ } -+ -+ if (dumpFront == dumpRear) -+ { -+ /* No context buffer is found, dump all we got.*/ -+ dumpFront = 0; -+ } -+ -+ /* Dump from last context buffer to last command buffer where hang happens. */ -+ for (i = dumpFront; i <= dumpRear; i++) -+ { -+ gckLINKQUEUE_GetData(queueMirror, i, &linkData); -+ -+ /* Get gpu address of this command buffer. */ -+ gpuAddress = linkData->start; -+ bytes = linkData->end - gpuAddress; -+ -+ /* Get the whole buffer. */ -+ status = gckKERNEL_QueryGPUAddress(kernel, gpuAddress, &buffer); -+ -+ if (gcmIS_ERROR(status)) -+ { -+ gcmkPRINT("Buffer [%08X - %08X] is lost or not belong to current process", -+ linkData->start, -+ linkData->end); -+ continue; -+ } -+ -+ /* Get kernel logical for dump. */ -+ if (buffer->kernelLogical) -+ { -+ /* Get kernel logical directly if it is a context buffer. */ -+ entry = buffer->kernelLogical; -+ gcmkPRINT("Context Buffer:"); -+ } -+ else -+ { -+ /* Make it accessiable by kernel if it is a user command buffer. */ -+ gcmkVERIFY_OK( -+ gckOS_CreateKernelVirtualMapping(os, -+ buffer->physical, -+ buffer->bytes, -+ &entry, -+ &pageCount)); -+ gcmkPRINT("User Command Buffer:"); -+ } -+ -+ /* Dump from the entry. */ -+ _DumpBuffer((gctUINT8_PTR)entry + (gpuAddress - buffer->gpuAddress), gpuAddress, bytes); -+ -+ /* Release kernel logical address if neccessary. */ -+ if (!buffer->kernelLogical) -+ { -+ gcmkVERIFY_OK( -+ gckOS_DestroyKernelVirtualMapping(os, -+ buffer->physical, -+ buffer->bytes, -+ entry)); -+ } -+ } -+ -+ /* Free local copy. */ -+ gcmkOS_SAFE_FREE(os, queueMirror); -+ return gcvSTATUS_OK; -+ OnError: -+ return status; -+ } -+ else -+ { -+ gcmkPRINT("Dump Level is %d, dump memory near the stuck address", -+ Command->kernel->stuckDump); -+ -+ /* Without link queue information, we don't know the entry of last command -+ ** buffer, just dump the page where GPU stuck. */ -+ status = gckKERNEL_QueryGPUAddress(kernel, gpuAddress, &buffer); -+ -+ if (gcmIS_SUCCESS(status)) -+ { -+ gcmkVERIFY_OK( -+ gckOS_CreateKernelVirtualMapping(os, -+ buffer->physical, -+ buffer->bytes, -+ &entry, -+ &pageCount)); -+ -+ if (entry) -+ { -+ gctUINT32 offset = gpuAddress - buffer->gpuAddress; -+ gctPOINTER entryDump = entry; -+ -+ /* Dump one pages. */ -+ gctUINT32 bytes = 4096; -+ -+ /* Align to page. */ -+ offset &= 0xfffff000; -+ -+ /* Kernel address of page where stall point stay. */ -+ entryDump = (gctUINT8_PTR)entryDump + offset; -+ -+ /* Align to page. */ -+ gpuAddress &= 0xfffff000; -+ -+ gcmkPRINT("User Command Buffer:\n"); -+ _DumpBuffer(entryDump, gpuAddress, bytes); -+ } -+ -+ gcmkVERIFY_OK( -+ gckOS_DestroyKernelVirtualMapping(os, -+ buffer->physical, -+ buffer->bytes, -+ entry)); -+ } -+ else -+ { -+ _DumpKernelCommandBuffer(Command); -+ } -+ -+ return gcvSTATUS_OK; -+ } -+} -+ -+gceSTATUS -+gckCOMMAND_AddressInKernelCommandBuffer( -+ IN gckCOMMAND Command, -+ IN gctUINT32 Address, -+ OUT gctBOOL *In -+ ) -+{ -+ gctBOOL in = gcvFALSE; -+ gctINT i; -+ -+ for (i = 0; i < gcdCOMMAND_QUEUES; i++) -+ { -+ if ((Address >= Command->queues[i].address) -+ && (Address < (Command->queues[i].address + Command->pageSize)) -+ ) -+ { -+ in = gcvTRUE; -+ break; -+ } -+ } -+ -+ *In = in; -+ return gcvSTATUS_OK; -+} -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_command_vg.c linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_command_vg.c ---- linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_command_vg.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_command_vg.c 2015-11-30 17:56:13.572138258 +0100 -@@ -0,0 +1,3678 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#include "gc_hal_kernel_precomp.h" -+ -+#if gcdENABLE_VG -+ -+#include "gc_hal_kernel_hardware_command_vg.h" -+ -+#define _GC_OBJ_ZONE gcvZONE_COMMAND -+ -+/******************************************************************************\ -+*********************************** Debugging ********************************** -+\******************************************************************************/ -+ -+#define gcvDISABLE_TIMEOUT 1 -+#define gcvDUMP_COMMAND_BUFFER 0 -+#define gcvDUMP_COMMAND_LINES 0 -+ -+ -+#if gcvDEBUG || defined(EMULATOR) || gcvDISABLE_TIMEOUT -+# define gcvQUEUE_TIMEOUT ~0 -+#else -+# define gcvQUEUE_TIMEOUT 10 -+#endif -+ -+ -+/******************************************************************************\ -+********************************** Definitions ********************************* -+\******************************************************************************/ -+ -+/* Minimum buffer size. */ -+#define gcvMINUMUM_BUFFER \ -+ gcmSIZEOF(gcsKERNEL_QUEUE_HEADER) + \ -+ gcmSIZEOF(gcsKERNEL_CMDQUEUE) * 2 -+ -+#define gcmDECLARE_INTERRUPT_HANDLER(Block, Number) \ -+ static gceSTATUS \ -+ _EventHandler_##Block##_##Number( \ -+ IN gckVGKERNEL Kernel \ -+ ) -+ -+#define gcmDEFINE_INTERRUPT_HANDLER(Block, Number) \ -+ gcmDECLARE_INTERRUPT_HANDLER(Block, Number) \ -+ { \ -+ return _EventHandler_Block( \ -+ Kernel, \ -+ &Kernel->command->taskTable[gcvBLOCK_##Block], \ -+ gcvFALSE \ -+ ); \ -+ } -+ -+#define gcmDEFINE_INTERRUPT_HANDLER_ENTRY(Block, Number) \ -+ { gcvBLOCK_##Block, _EventHandler_##Block##_##Number } -+ -+/* Block interrupt handling table entry. */ -+typedef struct _gcsBLOCK_INTERRUPT_HANDLER * gcsBLOCK_INTERRUPT_HANDLER_PTR; -+typedef struct _gcsBLOCK_INTERRUPT_HANDLER -+{ -+ gceBLOCK block; -+ gctINTERRUPT_HANDLER handler; -+} -+gcsBLOCK_INTERRUPT_HANDLER; -+ -+/* Queue control functions. */ -+typedef struct _gcsQUEUE_UPDATE_CONTROL * gcsQUEUE_UPDATE_CONTROL_PTR; -+typedef struct _gcsQUEUE_UPDATE_CONTROL -+{ -+ gctOBJECT_HANDLER execute; -+ gctOBJECT_HANDLER update; -+ gctOBJECT_HANDLER lastExecute; -+ gctOBJECT_HANDLER lastUpdate; -+} -+gcsQUEUE_UPDATE_CONTROL; -+ -+ -+/******************************************************************************\ -+********************************* Support Code ********************************* -+\******************************************************************************/ -+static gceSTATUS -+_FlushMMU( -+ IN gckVGCOMMAND Command -+ ) -+{ -+ gceSTATUS status; -+ gctUINT32 oldValue; -+ gckVGHARDWARE hardware = Command->hardware; -+ -+ gcmkONERROR(gckOS_AtomicExchange(Command->os, -+ hardware->pageTableDirty, -+ 0, -+ &oldValue)); -+ -+ if (oldValue) -+ { -+ /* Page Table is upated, flush mmu before commit. */ -+ gcmkONERROR(gckVGHARDWARE_FlushMMU(hardware)); -+ } -+ -+ return gcvSTATUS_OK; -+OnError: -+ return status; -+} -+ -+static gceSTATUS -+_WaitForIdle( -+ IN gckVGCOMMAND Command, -+ IN gcsKERNEL_QUEUE_HEADER_PTR Queue -+ ) -+{ -+ gceSTATUS status = gcvSTATUS_OK; -+ gctUINT32 idle; -+ gctUINT timeout = 0; -+ -+ /* Loop while not idle. */ -+ while (Queue->pending) -+ { -+ /* Did we reach the timeout limit? */ -+ if (timeout == gcvQUEUE_TIMEOUT) -+ { -+ /* Hardware is probably dead... */ -+ return gcvSTATUS_TIMEOUT; -+ } -+ -+ /* Sleep for 100ms. */ -+ gcmkERR_BREAK(gckOS_Delay(Command->os, 100)); -+ -+ /* Not the first loop? */ -+ if (timeout > 0) -+ { -+ /* Read IDLE register. */ -+ gcmkVERIFY_OK(gckVGHARDWARE_GetIdle(Command->hardware, &idle)); -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_COMMAND, -+ "%s: timeout, IDLE=%08X\n", -+ __FUNCTION__, idle -+ ); -+ } -+ -+ /* Increment the timeout counter. */ -+ timeout += 1; -+ } -+ -+ /* Return status. */ -+ return status; -+} -+ -+static gctINT32 -+_GetNextInterrupt( -+ IN gckVGCOMMAND Command, -+ IN gceBLOCK Block -+ ) -+{ -+ gctUINT index; -+ gcsBLOCK_TASK_ENTRY_PTR entry; -+ gctINT32 interrupt; -+ -+ /* Get the block entry. */ -+ entry = &Command->taskTable[Block]; -+ -+ /* Make sure we have initialized interrupts. */ -+ gcmkASSERT(entry->interruptCount > 0); -+ -+ /* Decrement the interrupt usage semaphore. */ -+ gcmkVERIFY_OK(gckOS_DecrementSemaphore( -+ Command->os, entry->interruptSemaphore -+ )); -+ -+ /* Get the value index. */ -+ index = entry->interruptIndex; -+ -+ /* Get the interrupt value. */ -+ interrupt = entry->interruptArray[index]; -+ -+ /* Must be a valid value. */ -+ gcmkASSERT((interrupt >= 0) && (interrupt <= 31)); -+ -+ /* Advance the index to the next value. */ -+ index += 1; -+ -+ /* Set the new index. */ -+ entry->interruptIndex = (index == entry->interruptCount) -+ ? 0 -+ : index; -+ -+ /* Return interrupt value. */ -+ return interrupt; -+} -+ -+ -+/******************************************************************************\ -+***************************** Task Storage Management ************************** -+\******************************************************************************/ -+ -+/* Minimum task buffer size. */ -+#define gcvMIN_TASK_BUFFER \ -+( \ -+ gcmSIZEOF(gcsTASK_CONTAINER) + 128 \ -+) -+ -+/* Free list terminator. */ -+#define gcvFREE_TASK_TERMINATOR \ -+( \ -+ (gcsTASK_CONTAINER_PTR) gcmINT2PTR(~0) \ -+) -+ -+ -+/*----------------------------------------------------------------------------*/ -+/*------------------- Allocated Task Buffer List Management ------------------*/ -+ -+static void -+_InsertTaskBuffer( -+ IN gcsTASK_CONTAINER_PTR AddAfter, -+ IN gcsTASK_CONTAINER_PTR Buffer -+ ) -+{ -+ gcsTASK_CONTAINER_PTR addBefore; -+ -+ /* Cannot add before the first buffer. */ -+ gcmkASSERT(AddAfter != gcvNULL); -+ -+ /* Create a shortcut to the next buffer. */ -+ addBefore = AddAfter->allocNext; -+ -+ /* Initialize the links. */ -+ Buffer->allocPrev = AddAfter; -+ Buffer->allocNext = addBefore; -+ -+ /* Link to the previous buffer. */ -+ AddAfter->allocNext = Buffer; -+ -+ /* Link to the next buffer. */ -+ if (addBefore != gcvNULL) -+ { -+ addBefore->allocPrev = Buffer; -+ } -+} -+ -+static void -+_RemoveTaskBuffer( -+ IN gcsTASK_CONTAINER_PTR Buffer -+ ) -+{ -+ gcsTASK_CONTAINER_PTR prev; -+ gcsTASK_CONTAINER_PTR next; -+ -+ /* Cannot remove the first buffer. */ -+ gcmkASSERT(Buffer->allocPrev != gcvNULL); -+ -+ /* Create shortcuts to the previous and next buffers. */ -+ prev = Buffer->allocPrev; -+ next = Buffer->allocNext; -+ -+ /* Tail buffer? */ -+ if (next == gcvNULL) -+ { -+ /* Remove from the list. */ -+ prev->allocNext = gcvNULL; -+ } -+ -+ /* Buffer from the middle. */ -+ else -+ { -+ prev->allocNext = next; -+ next->allocPrev = prev; -+ } -+} -+ -+ -+/*----------------------------------------------------------------------------*/ -+/*--------------------- Free Task Buffer List Management ---------------------*/ -+ -+static void -+_AppendToFreeList( -+ IN gckVGCOMMAND Command, -+ IN gcsTASK_CONTAINER_PTR Buffer -+ ) -+{ -+ /* Cannot be a part of the free list already. */ -+ gcmkASSERT(Buffer->freePrev == gcvNULL); -+ gcmkASSERT(Buffer->freeNext == gcvNULL); -+ -+ /* First buffer to add? */ -+ if (Command->taskFreeHead == gcvNULL) -+ { -+ /* Terminate the links. */ -+ Buffer->freePrev = gcvFREE_TASK_TERMINATOR; -+ Buffer->freeNext = gcvFREE_TASK_TERMINATOR; -+ -+ /* Initialize the list pointer. */ -+ Command->taskFreeHead = Command->taskFreeTail = Buffer; -+ } -+ -+ /* Not the first, add after the tail. */ -+ else -+ { -+ /* Initialize the new tail buffer. */ -+ Buffer->freePrev = Command->taskFreeTail; -+ Buffer->freeNext = gcvFREE_TASK_TERMINATOR; -+ -+ /* Add after the tail. */ -+ Command->taskFreeTail->freeNext = Buffer; -+ Command->taskFreeTail = Buffer; -+ } -+} -+ -+static void -+_RemoveFromFreeList( -+ IN gckVGCOMMAND Command, -+ IN gcsTASK_CONTAINER_PTR Buffer -+ ) -+{ -+ /* Has to be a part of the free list. */ -+ gcmkASSERT(Buffer->freePrev != gcvNULL); -+ gcmkASSERT(Buffer->freeNext != gcvNULL); -+ -+ /* Head buffer? */ -+ if (Buffer->freePrev == gcvFREE_TASK_TERMINATOR) -+ { -+ /* Tail buffer as well? */ -+ if (Buffer->freeNext == gcvFREE_TASK_TERMINATOR) -+ { -+ /* Reset the list pointer. */ -+ Command->taskFreeHead = Command->taskFreeTail = gcvNULL; -+ } -+ -+ /* No, just the head. */ -+ else -+ { -+ /* Update the head. */ -+ Command->taskFreeHead = Buffer->freeNext; -+ -+ /* Terminate the next buffer. */ -+ Command->taskFreeHead->freePrev = gcvFREE_TASK_TERMINATOR; -+ } -+ } -+ -+ /* Not the head. */ -+ else -+ { -+ /* Tail buffer? */ -+ if (Buffer->freeNext == gcvFREE_TASK_TERMINATOR) -+ { -+ /* Update the tail. */ -+ Command->taskFreeTail = Buffer->freePrev; -+ -+ /* Terminate the previous buffer. */ -+ Command->taskFreeTail->freeNext = gcvFREE_TASK_TERMINATOR; -+ } -+ -+ /* A buffer in the middle. */ -+ else -+ { -+ /* Remove the buffer from the list. */ -+ Buffer->freePrev->freeNext = Buffer->freeNext; -+ Buffer->freeNext->freePrev = Buffer->freePrev; -+ } -+ } -+ -+ /* Reset free list pointers. */ -+ Buffer->freePrev = gcvNULL; -+ Buffer->freeNext = gcvNULL; -+} -+ -+ -+/*----------------------------------------------------------------------------*/ -+/*-------------------------- Task Buffer Allocation --------------------------*/ -+ -+static void -+_SplitTaskBuffer( -+ IN gckVGCOMMAND Command, -+ IN gcsTASK_CONTAINER_PTR Buffer, -+ IN gctUINT Size -+ ) -+{ -+ /* Determine the size of the new buffer. */ -+ gctINT splitBufferSize = Buffer->size - Size; -+ gcmkASSERT(splitBufferSize >= 0); -+ -+ /* Is the split buffer big enough to become a separate buffer? */ -+ if (splitBufferSize >= gcvMIN_TASK_BUFFER) -+ { -+ /* Place the new path data. */ -+ gcsTASK_CONTAINER_PTR splitBuffer = (gcsTASK_CONTAINER_PTR) -+ ( -+ (gctUINT8_PTR) Buffer + Size -+ ); -+ -+ /* Set the trimmed buffer size. */ -+ Buffer->size = Size; -+ -+ /* Initialize the split buffer. */ -+ splitBuffer->referenceCount = 0; -+ splitBuffer->size = splitBufferSize; -+ splitBuffer->freePrev = gcvNULL; -+ splitBuffer->freeNext = gcvNULL; -+ -+ /* Link in. */ -+ _InsertTaskBuffer(Buffer, splitBuffer); -+ _AppendToFreeList(Command, splitBuffer); -+ } -+} -+ -+static gceSTATUS -+_AllocateTaskContainer( -+ IN gckVGCOMMAND Command, -+ IN gctUINT Size, -+ OUT gcsTASK_CONTAINER_PTR * Buffer -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Command=0x%x Size=0x%x, Buffer ==0x%x", Command, Size, Buffer); -+ -+ /* Verify arguments. */ -+ gcmkVERIFY_ARGUMENT(Buffer != gcvNULL); -+ -+ do -+ { -+ gcsTASK_STORAGE_PTR storage; -+ gcsTASK_CONTAINER_PTR buffer; -+ -+ /* Adjust the size. */ -+ Size += gcmSIZEOF(gcsTASK_CONTAINER); -+ -+ /* Adjust the allocation size if not big enough. */ -+ if (Size > Command->taskStorageUsable) -+ { -+ Command->taskStorageGranularity -+ = gcmALIGN(Size + gcmSIZEOF(gcsTASK_STORAGE), 1024); -+ -+ Command->taskStorageUsable -+ = Command->taskStorageGranularity - gcmSIZEOF(gcsTASK_STORAGE); -+ } -+ -+ /* Is there a free buffer available? */ -+ else if (Command->taskFreeHead != gcvNULL) -+ { -+ /* Set the initial free buffer. */ -+ gcsTASK_CONTAINER_PTR buffer = Command->taskFreeHead; -+ -+ do -+ { -+ /* Is the buffer big enough? */ -+ if (buffer->size >= Size) -+ { -+ /* Remove the buffer from the free list. */ -+ _RemoveFromFreeList(Command, buffer); -+ -+ /* Split the buffer. */ -+ _SplitTaskBuffer(Command, buffer, Size); -+ -+ /* Set the result. */ -+ * Buffer = buffer; -+ -+ gcmkFOOTER_ARG("*Buffer=0x%x",*Buffer); -+ /* Success. */ -+ return gcvSTATUS_OK; -+ } -+ -+ /* Get the next free buffer. */ -+ buffer = buffer->freeNext; -+ } -+ while (buffer != gcvFREE_TASK_TERMINATOR); -+ } -+ -+ /* Allocate a container. */ -+ gcmkERR_BREAK(gckOS_Allocate( -+ Command->os, -+ Command->taskStorageGranularity, -+ (gctPOINTER *) &storage -+ )); -+ -+ /* Link in the storage buffer. */ -+ storage->next = Command->taskStorage; -+ Command->taskStorage = storage; -+ -+ /* Place the task buffer. */ -+ buffer = (gcsTASK_CONTAINER_PTR) (storage + 1); -+ -+ /* Determine the size of the buffer. */ -+ buffer->size -+ = Command->taskStorageGranularity -+ - gcmSIZEOF(gcsTASK_STORAGE); -+ -+ /* Initialize the task buffer. */ -+ buffer->referenceCount = 0; -+ buffer->allocPrev = gcvNULL; -+ buffer->allocNext = gcvNULL; -+ buffer->freePrev = gcvNULL; -+ buffer->freeNext = gcvNULL; -+ -+ /* Split the buffer. */ -+ _SplitTaskBuffer(Command, buffer, Size); -+ -+ /* Set the result. */ -+ * Buffer = buffer; -+ -+ gcmkFOOTER_ARG("*Buffer=0x%x",*Buffer); -+ /* Success. */ -+ return gcvSTATUS_OK; -+ } -+ while (gcvFALSE); -+ -+ gcmkFOOTER(); -+ /* Return status. */ -+ return status; -+} -+ -+static void -+_FreeTaskContainer( -+ IN gckVGCOMMAND Command, -+ IN gcsTASK_CONTAINER_PTR Buffer -+ ) -+{ -+ gcsTASK_CONTAINER_PTR prev; -+ gcsTASK_CONTAINER_PTR next; -+ gcsTASK_CONTAINER_PTR merged; -+ -+ gctUINT32 mergedSize; -+ -+ /* Verify arguments. */ -+ gcmkASSERT(Buffer != gcvNULL); -+ gcmkASSERT(Buffer->freePrev == gcvNULL); -+ gcmkASSERT(Buffer->freeNext == gcvNULL); -+ -+ /* Get shortcuts to the previous and next path data buffers. */ -+ prev = Buffer->allocPrev; -+ next = Buffer->allocNext; -+ -+ /* Is the previous path data buffer already free? */ -+ if (prev && prev->freeNext) -+ { -+ /* The previous path data buffer is the one that remains. */ -+ merged = prev; -+ -+ /* Is the next path data buffer already free? */ -+ if (next && next->freeNext) -+ { -+ /* Merge all three path data buffers into the previous. */ -+ mergedSize = prev->size + Buffer->size + next->size; -+ -+ /* Remove the next path data buffer. */ -+ _RemoveFromFreeList(Command, next); -+ _RemoveTaskBuffer(next); -+ } -+ else -+ { -+ /* Merge the current path data buffer into the previous. */ -+ mergedSize = prev->size + Buffer->size; -+ } -+ -+ /* Delete the current path data buffer. */ -+ _RemoveTaskBuffer(Buffer); -+ -+ /* Set new size. */ -+ merged->size = mergedSize; -+ } -+ else -+ { -+ /* The current path data buffer is the one that remains. */ -+ merged = Buffer; -+ -+ /* Is the next buffer already free? */ -+ if (next && next->freeNext) -+ { -+ /* Merge the next into the current. */ -+ mergedSize = Buffer->size + next->size; -+ -+ /* Remove the next buffer. */ -+ _RemoveFromFreeList(Command, next); -+ _RemoveTaskBuffer(next); -+ -+ /* Set new size. */ -+ merged->size = mergedSize; -+ } -+ -+ /* Add the current buffer into the free list. */ -+ _AppendToFreeList(Command, merged); -+ } -+} -+ -+gceSTATUS -+_RemoveRecordFromProcesDB( -+ IN gckVGCOMMAND Command, -+ IN gcsTASK_HEADER_PTR Task -+ ) -+{ -+ gceSTATUS status; -+ gcsTASK_PTR task = (gcsTASK_PTR)((gctUINT8_PTR)Task - sizeof(gcsTASK)); -+ gcsTASK_FREE_VIDEO_MEMORY_PTR freeVideoMemory; -+ gcsTASK_UNLOCK_VIDEO_MEMORY_PTR unlockVideoMemory; -+ gctINT pid; -+ gctUINT32 size; -+ gctUINT32 handle; -+ gckKERNEL kernel = Command->kernel->kernel; -+ gckVIDMEM_NODE unlockNode = gcvNULL; -+ gckVIDMEM_NODE nodeObject = gcvNULL; -+ gceDATABASE_TYPE type; -+ -+ /* Get the total size of all tasks. */ -+ size = task->size; -+ -+ gcmkVERIFY_OK(gckOS_GetProcessID((gctUINT32_PTR)&pid)); -+ -+ do -+ { -+ switch (Task->id) -+ { -+ case gcvTASK_FREE_VIDEO_MEMORY: -+ freeVideoMemory = (gcsTASK_FREE_VIDEO_MEMORY_PTR)Task; -+ -+ handle = (gctUINT32)freeVideoMemory->node; -+ -+ status = gckVIDMEM_HANDLE_Lookup( -+ Command->kernel->kernel, -+ pid, -+ handle, -+ &nodeObject); -+ -+ if (gcmIS_ERROR(status)) -+ { -+ return status; -+ } -+ -+ gckVIDMEM_HANDLE_Dereference(kernel, pid, handle); -+ freeVideoMemory->node = gcmALL_TO_UINT32(nodeObject); -+ -+ type = gcvDB_VIDEO_MEMORY -+ | (nodeObject->type << gcdDB_VIDEO_MEMORY_TYPE_SHIFT) -+ | (nodeObject->pool << gcdDB_VIDEO_MEMORY_POOL_SHIFT); -+ -+ /* Remove record from process db. */ -+ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB( -+ Command->kernel->kernel, -+ pid, -+ type, -+ gcmINT2PTR(handle))); -+ -+ /* Advance to next task. */ -+ size -= sizeof(gcsTASK_FREE_VIDEO_MEMORY); -+ Task = (gcsTASK_HEADER_PTR)(freeVideoMemory + 1); -+ -+ break; -+ case gcvTASK_UNLOCK_VIDEO_MEMORY: -+ unlockVideoMemory = (gcsTASK_UNLOCK_VIDEO_MEMORY_PTR)Task; -+ -+ /* Remove record from process db. */ -+ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB( -+ Command->kernel->kernel, -+ pid, -+ gcvDB_VIDEO_MEMORY_LOCKED, -+ gcmUINT64_TO_PTR(unlockVideoMemory->node))); -+ -+ handle = (gctUINT32)unlockVideoMemory->node; -+ -+ status = gckVIDMEM_HANDLE_Lookup( -+ Command->kernel->kernel, -+ pid, -+ handle, -+ &unlockNode); -+ -+ if (gcmIS_ERROR(status)) -+ { -+ return status; -+ } -+ -+ gckVIDMEM_HANDLE_Dereference(kernel, pid, handle); -+ unlockVideoMemory->node = gcmPTR_TO_UINT64(unlockNode); -+ -+ /* Advance to next task. */ -+ size -= sizeof(gcsTASK_UNLOCK_VIDEO_MEMORY); -+ Task = (gcsTASK_HEADER_PTR)(unlockVideoMemory + 1); -+ -+ break; -+ default: -+ /* Skip the whole task. */ -+ size = 0; -+ break; -+ } -+ } -+ while(size); -+ -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************\ -+********************************* Task Scheduling ****************************** -+\******************************************************************************/ -+ -+static gceSTATUS -+_ScheduleTasks( -+ IN gckVGCOMMAND Command, -+ IN gcsTASK_MASTER_TABLE_PTR TaskTable, -+ IN gctUINT8_PTR PreviousEnd -+ ) -+{ -+ gceSTATUS status; -+ -+ do -+ { -+ gctINT block; -+ gcsTASK_CONTAINER_PTR container; -+ gcsTASK_MASTER_ENTRY_PTR userTaskEntry; -+ gcsBLOCK_TASK_ENTRY_PTR kernelTaskEntry; -+ gcsTASK_PTR userTask; -+ gctUINT8_PTR kernelTask; -+ gctINT32 interrupt; -+ gctUINT8_PTR eventCommand; -+ -+ /* Nothing to schedule? */ -+ if (TaskTable->size == 0) -+ { -+ status = gcvSTATUS_OK; -+ break; -+ } -+ -+ /* Acquire the mutex. */ -+ gcmkERR_BREAK(gckOS_AcquireMutex( -+ Command->os, -+ Command->taskMutex, -+ gcvINFINITE -+ )); -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_VERBOSE, gcvZONE_COMMAND, -+ "%s(%d)\n", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ do -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_VERBOSE, gcvZONE_COMMAND, -+ " number of tasks scheduled = %d\n" -+ " size of event data in bytes = %d\n", -+ TaskTable->count, -+ TaskTable->size -+ ); -+ -+ /* Allocate task buffer. */ -+ gcmkERR_BREAK(_AllocateTaskContainer( -+ Command, -+ TaskTable->size, -+ &container -+ )); -+ -+ /* Determine the task data pointer. */ -+ kernelTask = (gctUINT8_PTR) (container + 1); -+ -+ /* Initialize the reference count. */ -+ container->referenceCount = TaskTable->count; -+ -+ /* Process tasks. */ -+ for (block = gcvBLOCK_COUNT - 1; block >= 0; block -= 1) -+ { -+ /* Get the current user table entry. */ -+ userTaskEntry = &TaskTable->table[block]; -+ -+ /* Are there tasks scheduled? */ -+ if (userTaskEntry->head == gcvNULL) -+ { -+ /* No, skip to the next block. */ -+ continue; -+ } -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_VERBOSE, gcvZONE_COMMAND, -+ " processing tasks for block %d\n", -+ block -+ ); -+ -+ /* Get the current kernel table entry. */ -+ kernelTaskEntry = &Command->taskTable[block]; -+ -+ /* Are there tasks for the current block scheduled? */ -+ if (kernelTaskEntry->container == gcvNULL) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_VERBOSE, gcvZONE_COMMAND, -+ " first task container for the block added\n", -+ block -+ ); -+ -+ /* Nothing yet, set the container buffer pointer. */ -+ kernelTaskEntry->container = container; -+ kernelTaskEntry->task = (gcsTASK_HEADER_PTR) kernelTask; -+ } -+ -+ /* Yes, append to the end. */ -+ else -+ { -+ kernelTaskEntry->link->cotainer = container; -+ kernelTaskEntry->link->task = (gcsTASK_HEADER_PTR) kernelTask; -+ } -+ -+ /* Set initial task. */ -+ userTask = userTaskEntry->head; -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_VERBOSE, gcvZONE_COMMAND, -+ " copying user tasks over to the kernel\n" -+ ); -+ -+ /* Copy tasks. */ -+ do -+ { -+ gcsTASK_HEADER_PTR taskHeader; -+ -+ taskHeader = (gcsTASK_HEADER_PTR) (userTask + 1); -+ -+ gcmkVERIFY_OK(_RemoveRecordFromProcesDB(Command, taskHeader)); -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_VERBOSE, gcvZONE_COMMAND, -+ " task ID = %d, size = %d\n", -+ ((gcsTASK_HEADER_PTR) (userTask + 1))->id, -+ userTask->size -+ ); -+ -+ /* Copy the task data. */ -+ gcmkVERIFY_OK(gckOS_MemCopy( -+ kernelTask, taskHeader, userTask->size -+ )); -+ -+ /* Advance to the next task. */ -+ kernelTask += userTask->size; -+ userTask = userTask->next; -+ } -+ while (userTask != gcvNULL); -+ -+ /* Update link pointer in the header. */ -+ kernelTaskEntry->link = (gcsTASK_LINK_PTR) kernelTask; -+ -+ /* Initialize link task. */ -+ kernelTaskEntry->link->id = gcvTASK_LINK; -+ kernelTaskEntry->link->cotainer = gcvNULL; -+ kernelTaskEntry->link->task = gcvNULL; -+ -+ /* Advance the task data pointer. */ -+ kernelTask += gcmSIZEOF(gcsTASK_LINK); -+ } -+ } -+ while (gcvFALSE); -+ -+ /* Release the mutex. */ -+ gcmkERR_BREAK(gckOS_ReleaseMutex( -+ Command->os, -+ Command->taskMutex -+ )); -+ -+ /* Assign interrupts to the blocks. */ -+ eventCommand = PreviousEnd; -+ -+ for (block = gcvBLOCK_COUNT - 1; block >= 0; block -= 1) -+ { -+ /* Get the current user table entry. */ -+ userTaskEntry = &TaskTable->table[block]; -+ -+ /* Are there tasks scheduled? */ -+ if (userTaskEntry->head == gcvNULL) -+ { -+ /* No, skip to the next block. */ -+ continue; -+ } -+ -+ /* Get the interrupt number. */ -+ interrupt = _GetNextInterrupt(Command, block); -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_VERBOSE, gcvZONE_COMMAND, -+ "%s(%d): block = %d interrupt = %d\n", -+ __FUNCTION__, __LINE__, -+ block, interrupt -+ ); -+ -+ /* Determine the command position. */ -+ eventCommand -= Command->info.eventCommandSize; -+ -+ /* Append an EVENT command. */ -+ gcmkERR_BREAK(gckVGCOMMAND_EventCommand( -+ Command, eventCommand, block, interrupt, gcvNULL -+ )); -+ } -+ } -+ while (gcvFALSE); -+ -+ /* Return status. */ -+ return status; -+} -+ -+ -+/******************************************************************************\ -+******************************** Memory Management ***************************** -+\******************************************************************************/ -+ -+static gceSTATUS -+_HardwareToKernel( -+ IN gckOS Os, -+ IN gcuVIDMEM_NODE_PTR Node, -+ IN gctUINT32 Address, -+ OUT gctPOINTER * KernelPointer -+ ) -+{ -+ gceSTATUS status; -+ gckVIDMEM memory; -+ gctUINT32 offset; -+ gctUINT32 nodePhysical; -+ gctPOINTER *logical; -+ gctSIZE_T bytes; -+ status = gcvSTATUS_OK; -+ -+ memory = Node->VidMem.memory; -+ -+ if (memory->object.type == gcvOBJ_VIDMEM) -+ { -+ nodePhysical = memory->baseAddress -+ + (gctUINT32)Node->VidMem.offset -+ + Node->VidMem.alignment; -+ bytes = Node->VidMem.bytes; -+ logical = &Node->VidMem.kernelVirtual; -+ } -+ else -+ { -+ nodePhysical = Node->Virtual.physicalAddress; -+ bytes = Node->Virtual.bytes; -+ logical = &Node->Virtual.kernelVirtual; -+ } -+ -+ if (*logical == gcvNULL) -+ { -+ status = gckOS_MapPhysical(Os, nodePhysical, bytes, logical); -+ -+ if (gcmkIS_ERROR(status)) -+ { -+ return status; -+ } -+ } -+ -+ offset = Address - nodePhysical; -+ *KernelPointer = (gctPOINTER)((gctUINT8_PTR)(*logical) + offset); -+ -+ /* Return status. */ -+ return status; -+} -+ -+static gceSTATUS -+_ConvertUserCommandBufferPointer( -+ IN gckVGCOMMAND Command, -+ IN gcsCMDBUFFER_PTR UserCommandBuffer, -+ OUT gcsCMDBUFFER_PTR * KernelCommandBuffer -+ ) -+{ -+ gceSTATUS status, last; -+ gcsCMDBUFFER_PTR mappedUserCommandBuffer = gcvNULL; -+ gckKERNEL kernel = Command->kernel->kernel; -+ gctUINT32 pid; -+ gckVIDMEM_NODE node; -+ -+ gckOS_GetProcessID(&pid); -+ -+ do -+ { -+ gctUINT32 headerAddress; -+ -+ /* Map the command buffer structure into the kernel space. */ -+ gcmkERR_BREAK(gckOS_MapUserPointer( -+ Command->os, -+ UserCommandBuffer, -+ gcmSIZEOF(gcsCMDBUFFER), -+ (gctPOINTER *) &mappedUserCommandBuffer -+ )); -+ -+ /* Determine the address of the header. */ -+ headerAddress -+ = mappedUserCommandBuffer->address -+ - mappedUserCommandBuffer->bufferOffset; -+ -+ gcmkERR_BREAK(gckVIDMEM_HANDLE_Lookup( -+ kernel, -+ pid, -+ gcmPTR2INT32(mappedUserCommandBuffer->node), -+ &node)); -+ -+ /* Translate the logical address to the kernel space. */ -+ gcmkERR_BREAK(_HardwareToKernel( -+ Command->os, -+ node->node, -+ headerAddress, -+ (gctPOINTER *) KernelCommandBuffer -+ )); -+ } -+ while (gcvFALSE); -+ -+ /* Unmap the user command buffer. */ -+ if (mappedUserCommandBuffer != gcvNULL) -+ { -+ gcmkCHECK_STATUS(gckOS_UnmapUserPointer( -+ Command->os, -+ UserCommandBuffer, -+ gcmSIZEOF(gcsCMDBUFFER), -+ mappedUserCommandBuffer -+ )); -+ } -+ -+ /* Return status. */ -+ return status; -+} -+ -+static gceSTATUS -+_AllocateLinear( -+ IN gckVGCOMMAND Command, -+ IN gctUINT Size, -+ IN gctUINT Alignment, -+ OUT gcuVIDMEM_NODE_PTR * Node, -+ OUT gctUINT32 * Address, -+ OUT gctPOINTER * Logical -+ ) -+{ -+ gceSTATUS status, last; -+ gctPOINTER logical; -+ gctPHYS_ADDR physical; -+ gctUINT32 address; -+ gctSIZE_T size = Size; -+ -+ do -+ { -+ gcmkERR_BREAK(gckOS_AllocateContiguous( -+ Command->os, -+ gcvFALSE, -+ &size, -+ &physical, -+ &logical -+ )); -+ -+ gcmkERR_BREAK(gckOS_GetPhysicalAddress(Command->os, logical, &address)); -+ -+ /* Set return values. */ -+ * Node = physical; -+ * Address = address; -+ * Logical = logical; -+ -+ /* Success. */ -+ return gcvSTATUS_OK; -+ } -+ while (gcvFALSE); -+ -+ /* Roll back. */ -+ if (physical != gcvNULL) -+ { -+ /* Free the command buffer. */ -+ gcmkCHECK_STATUS(gckOS_FreeContiguous(Command->os, physical, logical, size)); -+ } -+ -+ /* Return status. */ -+ return status; -+} -+ -+static gceSTATUS -+_FreeLinear( -+ IN gckVGKERNEL Kernel, -+ IN gcuVIDMEM_NODE_PTR Node, -+ IN gctPOINTER Logical -+ ) -+{ -+ gceSTATUS status = gcvSTATUS_OK; -+ -+ do -+ { -+ gcmkERR_BREAK(gckOS_FreeContiguous(Kernel->os, Node, Logical, 1)); -+ } -+ while (gcvFALSE); -+ -+ /* Return status. */ -+ return status; -+} -+ -+gceSTATUS -+_AllocateCommandBuffer( -+ IN gckVGCOMMAND Command, -+ IN gctSIZE_T Size, -+ OUT gcsCMDBUFFER_PTR * CommandBuffer -+ ) -+{ -+ gceSTATUS status, last; -+ gcuVIDMEM_NODE_PTR node = gcvNULL; -+ gcsCMDBUFFER_PTR commandBuffer = gcvNULL; -+ -+ do -+ { -+ gctUINT alignedHeaderSize; -+ gctUINT requestedSize; -+ gctUINT allocationSize; -+ gctUINT32 address = 0; -+ gctUINT8_PTR endCommand; -+ -+ /* Determine the aligned header size. */ -+ alignedHeaderSize -+ = (gctUINT32)gcmALIGN(gcmSIZEOF(gcsCMDBUFFER), Command->info.addressAlignment); -+ -+ /* Align the requested size. */ -+ requestedSize -+ = (gctUINT32)gcmALIGN(Size, Command->info.commandAlignment); -+ -+ /* Determine the size of the buffer to allocate. */ -+ allocationSize -+ = alignedHeaderSize -+ + requestedSize -+ + (gctUINT32)Command->info.staticTailSize; -+ -+ /* Allocate the command buffer. */ -+ gcmkERR_BREAK(_AllocateLinear( -+ Command, -+ allocationSize, -+ Command->info.addressAlignment, -+ &node, -+ &address, -+ (gctPOINTER *) &commandBuffer -+ )); -+ -+ /* Initialize the structure. */ -+ commandBuffer->completion = gcvVACANT_BUFFER; -+ commandBuffer->node = node; -+ commandBuffer->address = address + alignedHeaderSize; -+ commandBuffer->bufferOffset = alignedHeaderSize; -+ commandBuffer->size = requestedSize; -+ commandBuffer->offset = requestedSize; -+ commandBuffer->nextAllocated = gcvNULL; -+ commandBuffer->nextSubBuffer = gcvNULL; -+ -+ /* Determine the data count. */ -+ commandBuffer->dataCount -+ = (requestedSize + Command->info.staticTailSize) -+ / Command->info.commandAlignment; -+ -+ /* Determine the location of the END command. */ -+ endCommand -+ = (gctUINT8_PTR) commandBuffer -+ + alignedHeaderSize -+ + requestedSize; -+ -+ /* Append an END command. */ -+ gcmkERR_BREAK(gckVGCOMMAND_EndCommand( -+ Command, -+ endCommand, -+ Command->info.feBufferInt, -+ gcvNULL -+ )); -+ -+ /* Set the return pointer. */ -+ * CommandBuffer = commandBuffer; -+ -+ /* Success. */ -+ return gcvSTATUS_OK; -+ } -+ while (gcvFALSE); -+ -+ /* Roll back. */ -+ if (node != gcvNULL) -+ { -+ /* Free the command buffer. */ -+ gcmkCHECK_STATUS(_FreeLinear(Command->kernel, node, commandBuffer)); -+ } -+ -+ /* Return status. */ -+ return status; -+} -+ -+static gceSTATUS -+_FreeCommandBuffer( -+ IN gckVGKERNEL Kernel, -+ IN gcsCMDBUFFER_PTR CommandBuffer -+ ) -+{ -+ gceSTATUS status; -+ -+ /* Free the buffer. */ -+ status = _FreeLinear(Kernel, CommandBuffer->node, CommandBuffer); -+ -+ /* Return status. */ -+ return status; -+} -+ -+ -+/******************************************************************************\ -+****************************** TS Overflow Handler ***************************** -+\******************************************************************************/ -+ -+static gceSTATUS -+_EventHandler_TSOverflow( -+ IN gckVGKERNEL Kernel -+ ) -+{ -+ gcmkTRACE( -+ gcvLEVEL_ERROR, -+ "%s(%d): **** TS OVERFLOW ENCOUNTERED ****\n", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ return gcvSTATUS_OK; -+} -+ -+ -+/******************************************************************************\ -+****************************** Bus Error Handler ******************************* -+\******************************************************************************/ -+ -+static gceSTATUS -+_EventHandler_BusError( -+ IN gckVGKERNEL Kernel -+ ) -+{ -+ gcmkTRACE( -+ gcvLEVEL_ERROR, -+ "%s(%d): **** BUS ERROR ENCOUNTERED ****\n", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************\ -+****************************** Power Stall Handler ******************************* -+\******************************************************************************/ -+ -+static gceSTATUS -+_EventHandler_PowerStall( -+ IN gckVGKERNEL Kernel -+ ) -+{ -+ /* Signal. */ -+ return gckOS_Signal( -+ Kernel->os, -+ Kernel->command->powerStallSignal, -+ gcvTRUE); -+} -+ -+/******************************************************************************\ -+******************************** Task Routines ********************************* -+\******************************************************************************/ -+ -+typedef gceSTATUS (* gctTASKROUTINE) ( -+ gckVGCOMMAND Command, -+ gcsBLOCK_TASK_ENTRY_PTR TaskHeader -+ ); -+ -+static gceSTATUS -+_TaskLink( -+ gckVGCOMMAND Command, -+ gcsBLOCK_TASK_ENTRY_PTR TaskHeader -+ ); -+ -+static gceSTATUS -+_TaskCluster( -+ gckVGCOMMAND Command, -+ gcsBLOCK_TASK_ENTRY_PTR TaskHeader -+ ); -+ -+static gceSTATUS -+_TaskIncrement( -+ gckVGCOMMAND Command, -+ gcsBLOCK_TASK_ENTRY_PTR TaskHeader -+ ); -+ -+static gceSTATUS -+_TaskDecrement( -+ gckVGCOMMAND Command, -+ gcsBLOCK_TASK_ENTRY_PTR TaskHeader -+ ); -+ -+static gceSTATUS -+_TaskSignal( -+ gckVGCOMMAND Command, -+ gcsBLOCK_TASK_ENTRY_PTR TaskHeader -+ ); -+ -+static gceSTATUS -+_TaskLockdown( -+ gckVGCOMMAND Command, -+ gcsBLOCK_TASK_ENTRY_PTR TaskHeader -+ ); -+ -+static gceSTATUS -+_TaskUnlockVideoMemory( -+ gckVGCOMMAND Command, -+ gcsBLOCK_TASK_ENTRY_PTR TaskHeader -+ ); -+ -+static gceSTATUS -+_TaskFreeVideoMemory( -+ gckVGCOMMAND Command, -+ gcsBLOCK_TASK_ENTRY_PTR TaskHeader -+ ); -+ -+static gceSTATUS -+_TaskFreeContiguousMemory( -+ gckVGCOMMAND Command, -+ gcsBLOCK_TASK_ENTRY_PTR TaskHeader -+ ); -+ -+static gceSTATUS -+_TaskUnmapUserMemory( -+ gckVGCOMMAND Command, -+ gcsBLOCK_TASK_ENTRY_PTR TaskHeader -+ ); -+ -+static gctTASKROUTINE _taskRoutine[] = -+{ -+ _TaskLink, /* gcvTASK_LINK */ -+ _TaskCluster, /* gcvTASK_CLUSTER */ -+ _TaskIncrement, /* gcvTASK_INCREMENT */ -+ _TaskDecrement, /* gcvTASK_DECREMENT */ -+ _TaskSignal, /* gcvTASK_SIGNAL */ -+ _TaskLockdown, /* gcvTASK_LOCKDOWN */ -+ _TaskUnlockVideoMemory, /* gcvTASK_UNLOCK_VIDEO_MEMORY */ -+ _TaskFreeVideoMemory, /* gcvTASK_FREE_VIDEO_MEMORY */ -+ _TaskFreeContiguousMemory, /* gcvTASK_FREE_CONTIGUOUS_MEMORY */ -+ _TaskUnmapUserMemory, /* gcvTASK_UNMAP_USER_MEMORY */ -+}; -+ -+static gceSTATUS -+_TaskLink( -+ gckVGCOMMAND Command, -+ gcsBLOCK_TASK_ENTRY_PTR TaskHeader -+ ) -+{ -+ /* Cast the task pointer. */ -+ gcsTASK_LINK_PTR task = (gcsTASK_LINK_PTR) TaskHeader->task; -+ -+ /* Save the pointer to the container. */ -+ gcsTASK_CONTAINER_PTR container = TaskHeader->container; -+ -+ /* No more tasks in the list? */ -+ if (task->task == gcvNULL) -+ { -+ /* Reset the entry. */ -+ TaskHeader->container = gcvNULL; -+ TaskHeader->task = gcvNULL; -+ TaskHeader->link = gcvNULL; -+ } -+ else -+ { -+ /* Update the entry. */ -+ TaskHeader->container = task->cotainer; -+ TaskHeader->task = task->task; -+ } -+ -+ /* Decrement the task buffer reference. */ -+ gcmkASSERT(container->referenceCount >= 0); -+ if (container->referenceCount == 0) -+ { -+ /* Free the container. */ -+ _FreeTaskContainer(Command, container); -+ } -+ -+ /* Success. */ -+ return gcvSTATUS_OK; -+} -+ -+static gceSTATUS -+_TaskCluster( -+ gckVGCOMMAND Command, -+ gcsBLOCK_TASK_ENTRY_PTR TaskHeader -+ ) -+{ -+ gceSTATUS status = gcvSTATUS_OK; -+ -+ /* Cast the task pointer. */ -+ gcsTASK_CLUSTER_PTR cluster = (gcsTASK_CLUSTER_PTR) TaskHeader->task; -+ -+ /* Get the number of tasks. */ -+ gctUINT taskCount = cluster->taskCount; -+ -+ /* Advance to the next task. */ -+ TaskHeader->task = (gcsTASK_HEADER_PTR) (cluster + 1); -+ -+ /* Perform all tasks in the cluster. */ -+ while (taskCount) -+ { -+ /* Perform the current task. */ -+ gcmkERR_BREAK(_taskRoutine[TaskHeader->task->id]( -+ Command, -+ TaskHeader -+ )); -+ -+ /* Update the task count. */ -+ taskCount -= 1; -+ } -+ -+ /* Return status. */ -+ return status; -+} -+ -+static gceSTATUS -+_TaskIncrement( -+ gckVGCOMMAND Command, -+ gcsBLOCK_TASK_ENTRY_PTR TaskHeader -+ ) -+{ -+ gceSTATUS status; -+ -+ do -+ { -+ /* Cast the task pointer. */ -+ gcsTASK_INCREMENT_PTR task = (gcsTASK_INCREMENT_PTR) TaskHeader->task; -+ -+ /* Convert physical into logical address. */ -+ gctUINT32_PTR logical; -+ gcmkERR_BREAK(gckOS_MapPhysical( -+ Command->os, -+ task->address, -+ gcmSIZEOF(gctUINT32), -+ (gctPOINTER *) &logical -+ )); -+ -+ /* Increment data. */ -+ (* logical) += 1; -+ -+ /* Unmap the physical memory. */ -+ gcmkERR_BREAK(gckOS_UnmapPhysical( -+ Command->os, -+ logical, -+ gcmSIZEOF(gctUINT32) -+ )); -+ -+ /* Update the reference counter. */ -+ TaskHeader->container->referenceCount -= 1; -+ -+ /* Update the task pointer. */ -+ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1); -+ } -+ while (gcvFALSE); -+ -+ /* Return status. */ -+ return status; -+} -+ -+static gceSTATUS -+_TaskDecrement( -+ gckVGCOMMAND Command, -+ gcsBLOCK_TASK_ENTRY_PTR TaskHeader -+ ) -+{ -+ gceSTATUS status; -+ -+ do -+ { -+ /* Cast the task pointer. */ -+ gcsTASK_DECREMENT_PTR task = (gcsTASK_DECREMENT_PTR) TaskHeader->task; -+ -+ /* Convert physical into logical address. */ -+ gctUINT32_PTR logical; -+ gcmkERR_BREAK(gckOS_MapPhysical( -+ Command->os, -+ task->address, -+ gcmSIZEOF(gctUINT32), -+ (gctPOINTER *) &logical -+ )); -+ -+ /* Decrement data. */ -+ (* logical) -= 1; -+ -+ /* Unmap the physical memory. */ -+ gcmkERR_BREAK(gckOS_UnmapPhysical( -+ Command->os, -+ logical, -+ gcmSIZEOF(gctUINT32) -+ )); -+ -+ /* Update the reference counter. */ -+ TaskHeader->container->referenceCount -= 1; -+ -+ /* Update the task pointer. */ -+ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1); -+ } -+ while (gcvFALSE); -+ -+ /* Return status. */ -+ return status; -+} -+ -+static gceSTATUS -+_TaskSignal( -+ gckVGCOMMAND Command, -+ gcsBLOCK_TASK_ENTRY_PTR TaskHeader -+ ) -+{ -+ gceSTATUS status; -+ -+ do -+ { -+ /* Cast the task pointer. */ -+ gcsTASK_SIGNAL_PTR task = (gcsTASK_SIGNAL_PTR) TaskHeader->task; -+ -+ -+ /* Map the signal into kernel space. */ -+ gcmkERR_BREAK(gckOS_UserSignal( -+ Command->os, task->signal, task->process -+ )); -+ -+ /* Update the reference counter. */ -+ TaskHeader->container->referenceCount -= 1; -+ -+ /* Update the task pointer. */ -+ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1); -+ } -+ while (gcvFALSE); -+ -+ /* Return status. */ -+ return status; -+} -+ -+static gceSTATUS -+_TaskLockdown( -+ gckVGCOMMAND Command, -+ gcsBLOCK_TASK_ENTRY_PTR TaskHeader -+ ) -+{ -+ gceSTATUS status; -+ gctUINT32_PTR userCounter = gcvNULL; -+ gctUINT32_PTR kernelCounter = gcvNULL; -+ gctSIGNAL signal = gcvNULL; -+ -+ do -+ { -+ /* Cast the task pointer. */ -+ gcsTASK_LOCKDOWN_PTR task = (gcsTASK_LOCKDOWN_PTR) TaskHeader->task; -+ -+ /* Convert physical addresses into logical. */ -+ gcmkERR_BREAK(gckOS_MapPhysical( -+ Command->os, -+ task->userCounter, -+ gcmSIZEOF(gctUINT32), -+ (gctPOINTER *) &userCounter -+ )); -+ -+ gcmkERR_BREAK(gckOS_MapPhysical( -+ Command->os, -+ task->kernelCounter, -+ gcmSIZEOF(gctUINT32), -+ (gctPOINTER *) &kernelCounter -+ )); -+ -+ /* Update the kernel counter. */ -+ (* kernelCounter) += 1; -+ -+ /* Are the counters equal? */ -+ if ((* userCounter) == (* kernelCounter)) -+ { -+ /* Map the signal into kernel space. */ -+ gcmkERR_BREAK(gckOS_MapSignal( -+ Command->os, task->signal, task->process, &signal -+ )); -+ -+ if (signal == gcvNULL) -+ { -+ /* Signal. */ -+ gcmkERR_BREAK(gckOS_Signal( -+ Command->os, task->signal, gcvTRUE -+ )); -+ } -+ else -+ { -+ /* Signal. */ -+ gcmkERR_BREAK(gckOS_Signal( -+ Command->os, signal, gcvTRUE -+ )); -+ } -+ } -+ -+ /* Update the reference counter. */ -+ TaskHeader->container->referenceCount -= 1; -+ -+ /* Update the task pointer. */ -+ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1); -+ } -+ while (gcvFALSE); -+ -+ /* Destroy the mapped signal. */ -+ if (signal != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckOS_DestroySignal( -+ Command->os, signal -+ )); -+ } -+ -+ /* Unmap the physical memory. */ -+ if (kernelCounter != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckOS_UnmapPhysical( -+ Command->os, -+ kernelCounter, -+ gcmSIZEOF(gctUINT32) -+ )); -+ } -+ -+ if (userCounter != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckOS_UnmapPhysical( -+ Command->os, -+ userCounter, -+ gcmSIZEOF(gctUINT32) -+ )); -+ } -+ -+ /* Return status. */ -+ return status; -+} -+ -+static gceSTATUS -+_TaskUnlockVideoMemory( -+ gckVGCOMMAND Command, -+ gcsBLOCK_TASK_ENTRY_PTR TaskHeader -+ ) -+{ -+ gceSTATUS status; -+ -+ do -+ { -+ /* Cast the task pointer. */ -+ gcsTASK_UNLOCK_VIDEO_MEMORY_PTR task -+ = (gcsTASK_UNLOCK_VIDEO_MEMORY_PTR) TaskHeader->task; -+ -+ /* Unlock video memory. */ -+ gcmkERR_BREAK(gckVIDMEM_Unlock( -+ Command->kernel->kernel, -+ (gckVIDMEM_NODE)gcmUINT64_TO_PTR(task->node), -+ gcvSURF_TYPE_UNKNOWN, -+ gcvNULL)); -+ -+ gcmkERR_BREAK(gckVIDMEM_NODE_Dereference( -+ Command->kernel->kernel, -+ gcmUINT64_TO_PTR(task->node))); -+ -+ /* Update the reference counter. */ -+ TaskHeader->container->referenceCount -= 1; -+ -+ /* Update the task pointer. */ -+ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1); -+ } -+ while (gcvFALSE); -+ -+ /* Return status. */ -+ return status; -+} -+ -+static gceSTATUS -+_TaskFreeVideoMemory( -+ gckVGCOMMAND Command, -+ gcsBLOCK_TASK_ENTRY_PTR TaskHeader -+ ) -+{ -+ gceSTATUS status; -+ -+ do -+ { -+ /* Cast the task pointer. */ -+ gcsTASK_FREE_VIDEO_MEMORY_PTR task -+ = (gcsTASK_FREE_VIDEO_MEMORY_PTR) TaskHeader->task; -+ -+ /* Free video memory. */ -+ gcmkERR_BREAK(gckVIDMEM_NODE_Dereference( -+ Command->kernel->kernel, -+ gcmINT2PTR(task->node))); -+ -+ /* Update the reference counter. */ -+ TaskHeader->container->referenceCount -= 1; -+ -+ /* Update the task pointer. */ -+ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1); -+ } -+ while (gcvFALSE); -+ -+ /* Return status. */ -+ return status; -+} -+ -+static gceSTATUS -+_TaskFreeContiguousMemory( -+ gckVGCOMMAND Command, -+ gcsBLOCK_TASK_ENTRY_PTR TaskHeader -+ ) -+{ -+ gceSTATUS status; -+ -+ do -+ { -+ /* Cast the task pointer. */ -+ gcsTASK_FREE_CONTIGUOUS_MEMORY_PTR task -+ = (gcsTASK_FREE_CONTIGUOUS_MEMORY_PTR) TaskHeader->task; -+ -+ /* Free contiguous memory. */ -+ gcmkERR_BREAK(gckOS_FreeContiguous( -+ Command->os, task->physical, task->logical, task->bytes -+ )); -+ -+ /* Update the reference counter. */ -+ TaskHeader->container->referenceCount -= 1; -+ -+ /* Update the task pointer. */ -+ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1); -+ } -+ while (gcvFALSE); -+ -+ /* Return status. */ -+ return status; -+} -+ -+static gceSTATUS -+_TaskUnmapUserMemory( -+ gckVGCOMMAND Command, -+ gcsBLOCK_TASK_ENTRY_PTR TaskHeader -+ ) -+{ -+ gceSTATUS status; -+ gctPOINTER info; -+ -+ do -+ { -+ /* Cast the task pointer. */ -+ gcsTASK_UNMAP_USER_MEMORY_PTR task -+ = (gcsTASK_UNMAP_USER_MEMORY_PTR) TaskHeader->task; -+ -+ info = gckKERNEL_QueryPointerFromName( -+ Command->kernel->kernel, gcmALL_TO_UINT32(task->info)); -+ -+ /* Unmap the user memory. */ -+ gcmkERR_BREAK(gckOS_UnmapUserMemory( -+ Command->os, gcvCORE_VG, task->memory, task->size, info, task->address -+ )); -+ -+ /* Update the reference counter. */ -+ TaskHeader->container->referenceCount -= 1; -+ -+ /* Update the task pointer. */ -+ TaskHeader->task = (gcsTASK_HEADER_PTR) (task + 1); -+ } -+ while (gcvFALSE); -+ -+ /* Return status. */ -+ return status; -+} -+ -+/******************************************************************************\ -+************ Hardware Block Interrupt Handlers For Scheduled Events ************ -+\******************************************************************************/ -+ -+static gceSTATUS -+_EventHandler_Block( -+ IN gckVGKERNEL Kernel, -+ IN gcsBLOCK_TASK_ENTRY_PTR TaskHeader, -+ IN gctBOOL ProcessAll -+ ) -+{ -+ gceSTATUS status = gcvSTATUS_OK, last; -+ -+ gcmkHEADER_ARG("Kernel=0x%x TaskHeader=0x%x ProcessAll=0x%x", Kernel, TaskHeader, ProcessAll); -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ -+ if (TaskHeader->task == gcvNULL) -+ { -+ gcmkFOOTER(); -+ return gcvSTATUS_OK; -+ } -+ -+ do -+ { -+ gckVGCOMMAND command; -+ -+ /* Get the command buffer object. */ -+ command = Kernel->command; -+ -+ /* Increment the interrupt usage semaphore. */ -+ gcmkERR_BREAK(gckOS_IncrementSemaphore( -+ command->os, TaskHeader->interruptSemaphore -+ )); -+ -+ /* Acquire the mutex. */ -+ gcmkERR_BREAK(gckOS_AcquireMutex( -+ command->os, -+ command->taskMutex, -+ gcvINFINITE -+ )); -+ -+ /* Verify inputs. */ -+ gcmkASSERT(TaskHeader != gcvNULL); -+ gcmkASSERT(TaskHeader->container != gcvNULL); -+ gcmkASSERT(TaskHeader->task != gcvNULL); -+ gcmkASSERT(TaskHeader->link != gcvNULL); -+ -+ /* Process tasks. */ -+ do -+ { -+ /* Process the current task. */ -+ gcmkERR_BREAK(_taskRoutine[TaskHeader->task->id]( -+ command, -+ TaskHeader -+ )); -+ -+ /* Is the next task is LINK? */ -+ if (TaskHeader->task->id == gcvTASK_LINK) -+ { -+ gcmkERR_BREAK(_taskRoutine[TaskHeader->task->id]( -+ command, -+ TaskHeader -+ )); -+ -+ /* Done. */ -+ break; -+ } -+ } -+ while (ProcessAll); -+ -+ /* Release the mutex. */ -+ gcmkCHECK_STATUS(gckOS_ReleaseMutex( -+ command->os, -+ command->taskMutex -+ )); -+ } -+ while (gcvFALSE); -+ -+ gcmkFOOTER(); -+ /* Return status. */ -+ return status; -+} -+ -+gcmDECLARE_INTERRUPT_HANDLER(COMMAND, 0) -+{ -+ gceSTATUS status, last; -+ -+ gcmkHEADER_ARG("Kernel=0x%x ", Kernel); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ -+ -+ do -+ { -+ gckVGCOMMAND command; -+ gcsKERNEL_QUEUE_HEADER_PTR mergeQueue; -+ gcsKERNEL_QUEUE_HEADER_PTR queueTail; -+ gcsKERNEL_CMDQUEUE_PTR entry; -+ gctUINT entryCount; -+ -+ /* Get the command buffer object. */ -+ command = Kernel->command; -+ -+ /* Acquire the mutex. */ -+ gcmkERR_BREAK(gckOS_AcquireMutex( -+ command->os, -+ command->queueMutex, -+ gcvINFINITE -+ )); -+ -+ /* Get the current queue. */ -+ queueTail = command->queueTail; -+ -+ /* Get the current queue entry. */ -+ entry = queueTail->currentEntry; -+ -+ /* Get the number of entries in the queue. */ -+ entryCount = queueTail->pending; -+ -+ /* Process all entries. */ -+ while (gcvTRUE) -+ { -+ /* Call post-execution function. */ -+ status = entry->handler(Kernel, entry); -+ -+ /* Failed? */ -+ if (gcmkIS_ERROR(status)) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, -+ gcvZONE_COMMAND, -+ "[%s] line %d: post action failed.\n", -+ __FUNCTION__, __LINE__ -+ ); -+ } -+ -+ /* Executed the next buffer? */ -+ if (status == gcvSTATUS_EXECUTED) -+ { -+ /* Update the queue. */ -+ queueTail->pending = entryCount; -+ queueTail->currentEntry = entry; -+ -+ /* Success. */ -+ status = gcvSTATUS_OK; -+ -+ /* Break out of the loop. */ -+ break; -+ } -+ -+ /* Advance to the next entry. */ -+ entry += 1; -+ entryCount -= 1; -+ -+ /* Last entry? */ -+ if (entryCount == 0) -+ { -+ /* Reset the queue to idle. */ -+ queueTail->pending = 0; -+ -+ /* Get a shortcut to the queue to merge with. */ -+ mergeQueue = command->mergeQueue; -+ -+ /* Merge the queues if necessary. */ -+ if (mergeQueue != queueTail) -+ { -+ gcmkASSERT(mergeQueue < queueTail); -+ gcmkASSERT(mergeQueue->next == queueTail); -+ -+ mergeQueue->size -+ += gcmSIZEOF(gcsKERNEL_QUEUE_HEADER) -+ + queueTail->size; -+ -+ mergeQueue->next = queueTail->next; -+ } -+ -+ /* Advance to the next queue. */ -+ queueTail = queueTail->next; -+ -+ /* Did it wrap around? */ -+ if (command->queue == queueTail) -+ { -+ /* Reset merge queue. */ -+ command->mergeQueue = queueTail; -+ } -+ -+ /* Set new queue. */ -+ command->queueTail = queueTail; -+ -+ /* Is the next queue scheduled? */ -+ if (queueTail->pending > 0) -+ { -+ gcsCMDBUFFER_PTR commandBuffer; -+ -+ /* The first entry must be a command buffer. */ -+ commandBuffer = queueTail->currentEntry->commandBuffer; -+ -+ /* Start the command processor. */ -+ status = gckVGHARDWARE_Execute( -+ command->hardware, -+ commandBuffer->address, -+ commandBuffer->dataCount -+ ); -+ -+ /* Failed? */ -+ if (gcmkIS_ERROR(status)) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, -+ gcvZONE_COMMAND, -+ "[%s] line %d: failed to start the next queue.\n", -+ __FUNCTION__, __LINE__ -+ ); -+ } -+ } -+ else -+ { -+ status = gckVGHARDWARE_SetPowerManagementState( -+ Kernel->command->hardware, gcvPOWER_IDLE_BROADCAST -+ ); -+ } -+ -+ /* Break out of the loop. */ -+ break; -+ } -+ } -+ -+ /* Release the mutex. */ -+ gcmkCHECK_STATUS(gckOS_ReleaseMutex( -+ command->os, -+ command->queueMutex -+ )); -+ } -+ while (gcvFALSE); -+ -+ -+ gcmkFOOTER(); -+ /* Return status. */ -+ return status; -+} -+ -+/* Define standard block interrupt handlers. */ -+gcmDEFINE_INTERRUPT_HANDLER(TESSELLATOR, 0) -+gcmDEFINE_INTERRUPT_HANDLER(VG, 0) -+gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 0) -+gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 1) -+gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 2) -+gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 3) -+gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 4) -+gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 5) -+gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 6) -+gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 7) -+gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 8) -+gcmDEFINE_INTERRUPT_HANDLER(PIXEL, 9) -+ -+/* The entries in the array are arranged by event priority. */ -+static gcsBLOCK_INTERRUPT_HANDLER _blockHandlers[] = -+{ -+ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(TESSELLATOR, 0), -+ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(VG, 0), -+ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 0), -+ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 1), -+ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 2), -+ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 3), -+ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 4), -+ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 5), -+ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 6), -+ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 7), -+ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 8), -+ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(PIXEL, 9), -+ gcmDEFINE_INTERRUPT_HANDLER_ENTRY(COMMAND, 0), -+}; -+ -+ -+/******************************************************************************\ -+************************* Static Command Buffer Handlers *********************** -+\******************************************************************************/ -+ -+static gceSTATUS -+_UpdateStaticCommandBuffer( -+ IN gckVGKERNEL Kernel, -+ IN gcsKERNEL_CMDQUEUE_PTR Entry -+ ) -+{ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_VERBOSE, gcvZONE_COMMAND, -+ "%s(%d)\n", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ /* Success. */ -+ return gcvSTATUS_OK; -+} -+ -+static gceSTATUS -+_ExecuteStaticCommandBuffer( -+ IN gckVGKERNEL Kernel, -+ IN gcsKERNEL_CMDQUEUE_PTR Entry -+ ) -+{ -+ gceSTATUS status; -+ -+ do -+ { -+ gcsCMDBUFFER_PTR commandBuffer; -+ -+ /* Cast the command buffer header. */ -+ commandBuffer = Entry->commandBuffer; -+ -+ /* Set to update the command buffer next time. */ -+ Entry->handler = _UpdateStaticCommandBuffer; -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_VERBOSE, gcvZONE_COMMAND, -+ "%s(%d): executing next buffer @ 0x%08X, data count = %d\n", -+ __FUNCTION__, __LINE__, -+ commandBuffer->address, -+ commandBuffer->dataCount -+ ); -+ -+ /* Start the command processor. */ -+ gcmkERR_BREAK(gckVGHARDWARE_Execute( -+ Kernel->hardware, -+ commandBuffer->address, -+ commandBuffer->dataCount -+ )); -+ -+ /* Success. */ -+ return gcvSTATUS_EXECUTED; -+ } -+ while (gcvFALSE); -+ -+ /* Return status. */ -+ return status; -+} -+ -+static gceSTATUS -+_UpdateLastStaticCommandBuffer( -+ IN gckVGKERNEL Kernel, -+ IN gcsKERNEL_CMDQUEUE_PTR Entry -+ ) -+{ -+#if gcvDEBUG || gcdFORCE_MESSAGES -+ /* Get the command buffer header. */ -+ gcsCMDBUFFER_PTR commandBuffer = Entry->commandBuffer; -+ -+ /* Validate the command buffer. */ -+ gcmkASSERT(commandBuffer->completion != gcvNULL); -+ gcmkASSERT(commandBuffer->completion != gcvVACANT_BUFFER); -+ -+#endif -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_VERBOSE, gcvZONE_COMMAND, -+ "%s(%d): processing all tasks scheduled for FE.\n", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ /* Perform scheduled tasks. */ -+ return _EventHandler_Block( -+ Kernel, -+ &Kernel->command->taskTable[gcvBLOCK_COMMAND], -+ gcvTRUE -+ ); -+} -+ -+static gceSTATUS -+_ExecuteLastStaticCommandBuffer( -+ IN gckVGKERNEL Kernel, -+ IN gcsKERNEL_CMDQUEUE_PTR Entry -+ ) -+{ -+ gceSTATUS status; -+ -+ do -+ { -+ /* Cast the command buffer header. */ -+ gcsCMDBUFFER_PTR commandBuffer = Entry->commandBuffer; -+ -+ /* Set to update the command buffer next time. */ -+ Entry->handler = _UpdateLastStaticCommandBuffer; -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_VERBOSE, gcvZONE_COMMAND, -+ "%s(%d): executing next buffer @ 0x%08X, data count = %d\n", -+ __FUNCTION__, __LINE__, -+ commandBuffer->address, -+ commandBuffer->dataCount -+ ); -+ -+ /* Start the command processor. */ -+ gcmkERR_BREAK(gckVGHARDWARE_Execute( -+ Kernel->hardware, -+ commandBuffer->address, -+ commandBuffer->dataCount -+ )); -+ -+ /* Success. */ -+ return gcvSTATUS_EXECUTED; -+ } -+ while (gcvFALSE); -+ -+ /* Return status. */ -+ return status; -+} -+ -+ -+/******************************************************************************\ -+************************* Dynamic Command Buffer Handlers ********************** -+\******************************************************************************/ -+ -+static gceSTATUS -+_UpdateDynamicCommandBuffer( -+ IN gckVGKERNEL Kernel, -+ IN gcsKERNEL_CMDQUEUE_PTR Entry -+ ) -+{ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_VERBOSE, gcvZONE_COMMAND, -+ "%s(%d)\n", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ /* Success. */ -+ return gcvSTATUS_OK; -+} -+ -+static gceSTATUS -+_ExecuteDynamicCommandBuffer( -+ IN gckVGKERNEL Kernel, -+ IN gcsKERNEL_CMDQUEUE_PTR Entry -+ ) -+{ -+ gceSTATUS status; -+ -+ do -+ { -+ /* Cast the command buffer header. */ -+ gcsCMDBUFFER_PTR commandBuffer = Entry->commandBuffer; -+ -+ /* Set to update the command buffer next time. */ -+ Entry->handler = _UpdateDynamicCommandBuffer; -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_VERBOSE, gcvZONE_COMMAND, -+ "%s(%d): executing next buffer @ 0x%08X, data count = %d\n", -+ __FUNCTION__, __LINE__, -+ commandBuffer->address, -+ commandBuffer->dataCount -+ ); -+ -+ /* Start the command processor. */ -+ gcmkERR_BREAK(gckVGHARDWARE_Execute( -+ Kernel->hardware, -+ commandBuffer->address, -+ commandBuffer->dataCount -+ )); -+ -+ /* Success. */ -+ return gcvSTATUS_EXECUTED; -+ } -+ while (gcvFALSE); -+ -+ /* Return status. */ -+ return status; -+} -+ -+static gceSTATUS -+_UpdateLastDynamicCommandBuffer( -+ IN gckVGKERNEL Kernel, -+ IN gcsKERNEL_CMDQUEUE_PTR Entry -+ ) -+{ -+#if gcvDEBUG || gcdFORCE_MESSAGES -+ /* Get the command buffer header. */ -+ gcsCMDBUFFER_PTR commandBuffer = Entry->commandBuffer; -+ -+ /* Validate the command buffer. */ -+ gcmkASSERT(commandBuffer->completion != gcvNULL); -+ gcmkASSERT(commandBuffer->completion != gcvVACANT_BUFFER); -+ -+#endif -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_VERBOSE, gcvZONE_COMMAND, -+ "%s(%d): processing all tasks scheduled for FE.\n", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ /* Perform scheduled tasks. */ -+ return _EventHandler_Block( -+ Kernel, -+ &Kernel->command->taskTable[gcvBLOCK_COMMAND], -+ gcvTRUE -+ ); -+} -+ -+static gceSTATUS -+_ExecuteLastDynamicCommandBuffer( -+ IN gckVGKERNEL Kernel, -+ IN gcsKERNEL_CMDQUEUE_PTR Entry -+ ) -+{ -+ gceSTATUS status; -+ -+ do -+ { -+ /* Cast the command buffer header. */ -+ gcsCMDBUFFER_PTR commandBuffer = Entry->commandBuffer; -+ -+ /* Set to update the command buffer next time. */ -+ Entry->handler = _UpdateLastDynamicCommandBuffer; -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_VERBOSE, gcvZONE_COMMAND, -+ "%s(%d): executing next buffer @ 0x%08X, data count = %d\n", -+ __FUNCTION__, __LINE__, -+ commandBuffer->address, -+ commandBuffer->dataCount -+ ); -+ -+ /* Start the command processor. */ -+ gcmkERR_BREAK(gckVGHARDWARE_Execute( -+ Kernel->hardware, -+ commandBuffer->address, -+ commandBuffer->dataCount -+ )); -+ -+ /* Success. */ -+ return gcvSTATUS_EXECUTED; -+ } -+ while (gcvFALSE); -+ -+ /* Return status. */ -+ return status; -+} -+ -+ -+/******************************************************************************\ -+********************************* Other Handlers ******************************* -+\******************************************************************************/ -+ -+static gceSTATUS -+_FreeKernelCommandBuffer( -+ IN gckVGKERNEL Kernel, -+ IN gcsKERNEL_CMDQUEUE_PTR Entry -+ ) -+{ -+ gceSTATUS status; -+ -+ /* Free the command buffer. */ -+ status = _FreeCommandBuffer(Kernel, Entry->commandBuffer); -+ -+ /* Return status. */ -+ return status; -+} -+ -+ -+/******************************************************************************\ -+******************************* Queue Management ******************************* -+\******************************************************************************/ -+ -+#if gcvDUMP_COMMAND_BUFFER -+static void -+_DumpCommandQueue( -+ IN gckVGCOMMAND Command, -+ IN gcsKERNEL_QUEUE_HEADER_PTR QueueHeader, -+ IN gctUINT EntryCount -+ ) -+{ -+ gcsKERNEL_CMDQUEUE_PTR entry; -+ gctUINT queueIndex; -+ -+#if defined(gcvCOMMAND_BUFFER_NAME) -+ static gctUINT arrayCount = 0; -+#endif -+ -+ /* Is dumpinng enabled? */ -+ if (!Commad->enableDumping) -+ { -+ return; -+ } -+ -+#if !defined(gcvCOMMAND_BUFFER_NAME) -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, gcvZONE_COMMAND, -+ "COMMAND QUEUE DUMP: %d entries\n", EntryCount -+ ); -+#endif -+ -+ /* Get the pointer to the first entry. */ -+ entry = QueueHeader->currentEntry; -+ -+ /* Iterate through the queue. */ -+ for (queueIndex = 0; queueIndex < EntryCount; queueIndex += 1) -+ { -+ gcsCMDBUFFER_PTR buffer; -+ gctUINT bufferCount; -+ gctUINT bufferIndex; -+ gctUINT i, count; -+ gctUINT size; -+ gctUINT32_PTR data; -+ -+#if gcvDUMP_COMMAND_LINES -+ gctUINT lineNumber; -+#endif -+ -+#if !defined(gcvCOMMAND_BUFFER_NAME) -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, gcvZONE_COMMAND, -+ "ENTRY %d\n", queueIndex -+ ); -+#endif -+ -+ /* Reset the count. */ -+ bufferCount = 0; -+ -+ /* Set the initial buffer. */ -+ buffer = entry->commandBuffer; -+ -+ /* Loop through all subbuffers. */ -+ while (buffer) -+ { -+ /* Update the count. */ -+ bufferCount += 1; -+ -+ /* Advance to the next subbuffer. */ -+ buffer = buffer->nextSubBuffer; -+ } -+ -+#if !defined(gcvCOMMAND_BUFFER_NAME) -+ if (bufferCount > 1) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, -+ gcvZONE_COMMAND, -+ " COMMAND BUFFER SET: %d buffers.\n", -+ bufferCount -+ ); -+ } -+#endif -+ -+ /* Reset the buffer index. */ -+ bufferIndex = 0; -+ -+ /* Set the initial buffer. */ -+ buffer = entry->commandBuffer; -+ -+ /* Loop through all subbuffers. */ -+ while (buffer) -+ { -+ /* Determine the size of the buffer. */ -+ size = buffer->dataCount * Command->info.commandAlignment; -+ -+#if !defined(gcvCOMMAND_BUFFER_NAME) -+ /* A single buffer? */ -+ if (bufferCount == 1) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, -+ gcvZONE_COMMAND, -+ " COMMAND BUFFER: count=%d (0x%X), size=%d bytes @ %08X.\n", -+ buffer->dataCount, -+ buffer->dataCount, -+ size, -+ buffer->address -+ ); -+ } -+ else -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, -+ gcvZONE_COMMAND, -+ " COMMAND BUFFER %d: count=%d (0x%X), size=%d bytes @ %08X\n", -+ bufferIndex, -+ buffer->dataCount, -+ buffer->dataCount, -+ size, -+ buffer->address -+ ); -+ } -+#endif -+ -+ /* Determine the number of double words to print. */ -+ count = size / 4; -+ -+ /* Determine the buffer location. */ -+ data = (gctUINT32_PTR) -+ ( -+ (gctUINT8_PTR) buffer + buffer->bufferOffset -+ ); -+ -+#if defined(gcvCOMMAND_BUFFER_NAME) -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, -+ gcvZONE_COMMAND, -+ "unsigned int _" gcvCOMMAND_BUFFER_NAME "_%d[] =\n", -+ arrayCount -+ ); -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, -+ gcvZONE_COMMAND, -+ "{\n" -+ ); -+ -+ arrayCount += 1; -+#endif -+ -+#if gcvDUMP_COMMAND_LINES -+ /* Reset the line number. */ -+ lineNumber = 0; -+#endif -+ -+#if defined(gcvCOMMAND_BUFFER_NAME) -+ count -= 2; -+#endif -+ -+ for (i = 0; i < count; i += 1) -+ { -+ if ((i % 8) == 0) -+ { -+#if defined(gcvCOMMAND_BUFFER_NAME) -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, "\t"); -+#else -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, " "); -+#endif -+ } -+ -+#if gcvDUMP_COMMAND_LINES -+ if (lineNumber == gcvDUMP_COMMAND_LINES) -+ { -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, " . . . . . . . . .\n"); -+ break; -+ } -+#endif -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, "0x%08X", data[i]); -+ -+ if (i + 1 == count) -+ { -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, "\n"); -+ -+#if gcvDUMP_COMMAND_LINES -+ lineNumber += 1; -+#endif -+ } -+ else -+ { -+ if (((i + 1) % 8) == 0) -+ { -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, ",\n"); -+ -+#if gcvDUMP_COMMAND_LINES -+ lineNumber += 1; -+#endif -+ } -+ else -+ { -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_COMMAND, ", "); -+ } -+ } -+ } -+ -+#if defined(gcvCOMMAND_BUFFER_NAME) -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, -+ gcvZONE_COMMAND, -+ "};\n\n" -+ ); -+#endif -+ -+ /* Advance to the next subbuffer. */ -+ buffer = buffer->nextSubBuffer; -+ bufferIndex += 1; -+ } -+ -+ /* Advance to the next entry. */ -+ entry += 1; -+ } -+} -+#endif -+ -+static gceSTATUS -+_LockCurrentQueue( -+ IN gckVGCOMMAND Command, -+ OUT gcsKERNEL_CMDQUEUE_PTR * Entries, -+ OUT gctUINT_PTR EntryCount -+ ) -+{ -+ gceSTATUS status; -+ -+ do -+ { -+ gcsKERNEL_QUEUE_HEADER_PTR queueHead; -+ -+ /* Get a shortcut to the head of the queue. */ -+ queueHead = Command->queueHead; -+ -+ /* Is the head buffer still being worked on? */ -+ if (queueHead->pending) -+ { -+ /* Increment overflow count. */ -+ Command->queueOverflow += 1; -+ -+ /* Wait until the head becomes idle. */ -+ gcmkERR_BREAK(_WaitForIdle(Command, queueHead)); -+ } -+ -+ /* Acquire the mutex. */ -+ gcmkERR_BREAK(gckOS_AcquireMutex( -+ Command->os, -+ Command->queueMutex, -+ gcvINFINITE -+ )); -+ -+ /* Determine the first queue entry. */ -+ queueHead->currentEntry = (gcsKERNEL_CMDQUEUE_PTR) -+ ( -+ (gctUINT8_PTR) queueHead + gcmSIZEOF(gcsKERNEL_QUEUE_HEADER) -+ ); -+ -+ /* Set the pointer to the first entry. */ -+ * Entries = queueHead->currentEntry; -+ -+ /* Determine the number of available entries. */ -+ * EntryCount = queueHead->size / gcmSIZEOF(gcsKERNEL_CMDQUEUE); -+ -+ /* Success. */ -+ return gcvSTATUS_OK; -+ } -+ while (gcvFALSE); -+ -+ /* Return status. */ -+ return status; -+} -+ -+static gceSTATUS -+_UnlockCurrentQueue( -+ IN gckVGCOMMAND Command, -+ IN gctUINT EntryCount -+ ) -+{ -+ gceSTATUS status; -+ -+ do -+ { -+#if !gcdENABLE_INFINITE_SPEED_HW -+ gcsKERNEL_QUEUE_HEADER_PTR queueTail; -+ gcsKERNEL_QUEUE_HEADER_PTR queueHead; -+ gcsKERNEL_QUEUE_HEADER_PTR queueNext; -+ gctUINT queueSize; -+ gctUINT newSize; -+ gctUINT unusedSize; -+ -+ /* Get shortcut to the head and to the tail of the queue. */ -+ queueTail = Command->queueTail; -+ queueHead = Command->queueHead; -+ -+ /* Dump the command buffer. */ -+#if gcvDUMP_COMMAND_BUFFER -+ _DumpCommandQueue(Command, queueHead, EntryCount); -+#endif -+ -+ /* Get a shortcut to the current queue size. */ -+ queueSize = queueHead->size; -+ -+ /* Determine the new queue size. */ -+ newSize = EntryCount * gcmSIZEOF(gcsKERNEL_CMDQUEUE); -+ gcmkASSERT(newSize <= queueSize); -+ -+ /* Determine the size of the unused area. */ -+ unusedSize = queueSize - newSize; -+ -+ /* Is the unused area big enough to become a buffer? */ -+ if (unusedSize >= gcvMINUMUM_BUFFER) -+ { -+ gcsKERNEL_QUEUE_HEADER_PTR nextHead; -+ -+ /* Place the new header. */ -+ nextHead = (gcsKERNEL_QUEUE_HEADER_PTR) -+ ( -+ (gctUINT8_PTR) queueHead -+ + gcmSIZEOF(gcsKERNEL_QUEUE_HEADER) -+ + newSize -+ ); -+ -+ /* Initialize the buffer. */ -+ nextHead->size = unusedSize - gcmSIZEOF(gcsKERNEL_QUEUE_HEADER); -+ nextHead->pending = 0; -+ -+ /* Link the buffer in. */ -+ nextHead->next = queueHead->next; -+ queueHead->next = nextHead; -+ queueNext = nextHead; -+ -+ /* Update the size of the current buffer. */ -+ queueHead->size = newSize; -+ } -+ -+ /* Not big enough. */ -+ else -+ { -+ /* Determine the next queue. */ -+ queueNext = queueHead->next; -+ } -+ -+ /* Mark the buffer as busy. */ -+ queueHead->pending = EntryCount; -+ -+ /* Advance to the next buffer. */ -+ Command->queueHead = queueNext; -+ -+ /* Start the command processor if the queue was empty. */ -+ if (queueTail == queueHead) -+ { -+ gcsCMDBUFFER_PTR commandBuffer; -+ -+ /* The first entry must be a command buffer. */ -+ commandBuffer = queueTail->currentEntry->commandBuffer; -+ -+ /* Start the command processor. */ -+ gcmkERR_BREAK(gckVGHARDWARE_Execute( -+ Command->hardware, -+ commandBuffer->address, -+ commandBuffer->dataCount -+ )); -+ } -+ -+ /* The queue was not empty. */ -+ else -+ { -+ /* Advance the merge buffer if needed. */ -+ if (queueHead == Command->mergeQueue) -+ { -+ Command->mergeQueue = queueNext; -+ } -+ } -+#endif -+ -+ /* Release the mutex. */ -+ gcmkERR_BREAK(gckOS_ReleaseMutex( -+ Command->os, -+ Command->queueMutex -+ )); -+ -+ /* Success. */ -+ return gcvSTATUS_OK; -+ } -+ while (gcvFALSE); -+ -+ /* Return status. */ -+ return status; -+} -+ -+ -+ -+/******************************************************************************\ -+****************************** gckVGCOMMAND API Code ***************************** -+\******************************************************************************/ -+gceSTATUS -+gckVGCOMMAND_Construct( -+ IN gckVGKERNEL Kernel, -+ IN gctUINT TaskGranularity, -+ IN gctUINT QueueSize, -+ OUT gckVGCOMMAND * Command -+ ) -+{ -+ gceSTATUS status, last; -+ gckVGCOMMAND command = gcvNULL; -+ gcsKERNEL_QUEUE_HEADER_PTR queue; -+ gctUINT i, j; -+ -+ gcmkHEADER_ARG("Kernel=0x%x TaskGranularity=0x%x QueueSize=0x%x Command=0x%x", -+ Kernel, TaskGranularity, QueueSize, Command); -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ gcmkVERIFY_ARGUMENT(QueueSize >= gcvMINUMUM_BUFFER); -+ gcmkVERIFY_ARGUMENT(Command != gcvNULL); -+ -+ do -+ { -+ /*********************************************************************** -+ ** Generic object initialization. -+ */ -+ -+ /* Allocate the gckVGCOMMAND structure. */ -+ gcmkERR_BREAK(gckOS_Allocate( -+ Kernel->os, -+ gcmSIZEOF(struct _gckVGCOMMAND), -+ (gctPOINTER *) &command -+ )); -+ -+ /* Initialize the object. */ -+ command->object.type = gcvOBJ_COMMAND; -+ -+ /* Set the object pointers. */ -+ command->kernel = Kernel; -+ command->os = Kernel->os; -+ command->hardware = Kernel->hardware; -+ -+ /* Reset pointers. */ -+ command->queue = gcvNULL; -+ command->queueMutex = gcvNULL; -+ command->taskMutex = gcvNULL; -+ command->commitMutex = gcvNULL; -+ -+ command->powerStallBuffer = gcvNULL; -+ command->powerStallSignal = gcvNULL; -+ command->powerSemaphore = gcvNULL; -+ -+ /* Reset context states. */ -+ command->contextCounter = 0; -+ command->currentContext = 0; -+ -+ /* Enable command buffer dumping. */ -+ command->enableDumping = gcvTRUE; -+ -+ /* Set features. */ -+ command->fe20 = Kernel->hardware->fe20; -+ command->vg20 = Kernel->hardware->vg20; -+ command->vg21 = Kernel->hardware->vg21; -+ -+ /* Reset task table .*/ -+ gcmkVERIFY_OK(gckOS_ZeroMemory( -+ command->taskTable, gcmSIZEOF(command->taskTable) -+ )); -+ -+ /* Query command buffer attributes. */ -+ gcmkERR_BREAK(gckVGCOMMAND_InitializeInfo(command)); -+ -+ /* Create the control mutexes. */ -+ gcmkERR_BREAK(gckOS_CreateMutex(Kernel->os, &command->queueMutex)); -+ gcmkERR_BREAK(gckOS_CreateMutex(Kernel->os, &command->taskMutex)); -+ gcmkERR_BREAK(gckOS_CreateMutex(Kernel->os, &command->commitMutex)); -+ -+ /* Create the power management semaphore. */ -+ gcmkERR_BREAK(gckOS_CreateSemaphore(Kernel->os, -+ &command->powerSemaphore)); -+ -+ gcmkERR_BREAK(gckOS_CreateSignal(Kernel->os, -+ gcvFALSE, &command->powerStallSignal)); -+ -+ /*********************************************************************** -+ ** Command queue initialization. -+ */ -+ -+ /* Allocate the command queue. */ -+ gcmkERR_BREAK(gckOS_Allocate( -+ Kernel->os, -+ QueueSize, -+ (gctPOINTER *) &command->queue -+ )); -+ -+ /* Initialize the command queue. */ -+ queue = command->queue; -+ -+ queue->size = QueueSize - gcmSIZEOF(gcsKERNEL_QUEUE_HEADER); -+ queue->pending = 0; -+ queue->next = queue; -+ -+ command->queueHead = -+ command->queueTail = -+ command->mergeQueue = command->queue; -+ -+ command->queueOverflow = 0; -+ -+ -+ /*********************************************************************** -+ ** Enable TS overflow interrupt. -+ */ -+ -+ command->info.tsOverflowInt = 0; -+ gcmkERR_BREAK(gckVGINTERRUPT_Enable( -+ Kernel->interrupt, -+ &command->info.tsOverflowInt, -+ _EventHandler_TSOverflow -+ )); -+ -+ /* Mask out the interrupt. */ -+ Kernel->hardware->eventMask &= ~(1 << command->info.tsOverflowInt); -+ -+ -+ /*********************************************************************** -+ ** Enable Bus Error interrupt. -+ */ -+ -+ /* Hardwired to bit 31. */ -+ command->busErrorInt = 31; -+ -+ /* Enable the interrupt. */ -+ gcmkERR_BREAK(gckVGINTERRUPT_Enable( -+ Kernel->interrupt, -+ &command->busErrorInt, -+ _EventHandler_BusError -+ )); -+ -+ -+ command->powerStallInt = 30; -+ /* Enable the interrupt. */ -+ gcmkERR_BREAK(gckVGINTERRUPT_Enable( -+ Kernel->interrupt, -+ &command->powerStallInt, -+ _EventHandler_PowerStall -+ )); -+ -+ /*********************************************************************** -+ ** Task management initialization. -+ */ -+ -+ command->taskStorage = gcvNULL; -+ command->taskStorageGranularity = TaskGranularity; -+ command->taskStorageUsable = TaskGranularity - gcmSIZEOF(gcsTASK_STORAGE); -+ -+ command->taskFreeHead = gcvNULL; -+ command->taskFreeTail = gcvNULL; -+ -+ /* Enable block handlers. */ -+ for (i = 0; i < gcmCOUNTOF(_blockHandlers); i += 1) -+ { -+ /* Get the target hardware block. */ -+ gceBLOCK block = _blockHandlers[i].block; -+ -+ /* Get the interrupt array entry. */ -+ gcsBLOCK_TASK_ENTRY_PTR entry = &command->taskTable[block]; -+ -+ /* Determine the interrupt value index. */ -+ gctUINT index = entry->interruptCount; -+ -+ /* Create the block semaphore. */ -+ if (entry->interruptSemaphore == gcvNULL) -+ { -+ gcmkERR_BREAK(gckOS_CreateSemaphoreVG( -+ command->os, &entry->interruptSemaphore -+ )); -+ } -+ -+ /* Enable auto-detection. */ -+ entry->interruptArray[index] = -1; -+ -+ /* Enable interrupt for the block. */ -+ gcmkERR_BREAK(gckVGINTERRUPT_Enable( -+ Kernel->interrupt, -+ &entry->interruptArray[index], -+ _blockHandlers[i].handler -+ )); -+ -+ /* Update the number of registered interrupts. */ -+ entry->interruptCount += 1; -+ -+ /* Inrement the semaphore to allow the usage of the registered -+ interrupt. */ -+ gcmkERR_BREAK(gckOS_IncrementSemaphore( -+ command->os, entry->interruptSemaphore -+ )); -+ -+ } -+ -+ /* Error? */ -+ if (gcmkIS_ERROR(status)) -+ { -+ break; -+ } -+ -+ /* Get the FE interrupt. */ -+ command->info.feBufferInt -+ = command->taskTable[gcvBLOCK_COMMAND].interruptArray[0]; -+ -+ /* Return gckVGCOMMAND object pointer. */ -+ *Command = command; -+ -+ gcmkFOOTER_ARG("*Command=0x%x",*Command); -+ /* Success. */ -+ return gcvSTATUS_OK; -+ } -+ while (gcvFALSE); -+ -+ /* Roll back. */ -+ if (command != gcvNULL) -+ { -+ /* Disable block handlers. */ -+ for (i = 0; i < gcvBLOCK_COUNT; i += 1) -+ { -+ /* Get the task table entry. */ -+ gcsBLOCK_TASK_ENTRY_PTR entry = &command->taskTable[i]; -+ -+ /* Destroy the semaphore. */ -+ if (entry->interruptSemaphore != gcvNULL) -+ { -+ gcmkCHECK_STATUS(gckOS_DestroySemaphore( -+ command->os, entry->interruptSemaphore -+ )); -+ } -+ -+ /* Disable all enabled interrupts. */ -+ for (j = 0; j < entry->interruptCount; j += 1) -+ { -+ /* Must be a valid value. */ -+ gcmkASSERT(entry->interruptArray[j] >= 0); -+ gcmkASSERT(entry->interruptArray[j] <= 31); -+ -+ /* Disable the interrupt. */ -+ gcmkCHECK_STATUS(gckVGINTERRUPT_Disable( -+ Kernel->interrupt, -+ entry->interruptArray[j] -+ )); -+ } -+ } -+ -+ /* Disable the bus error interrupt. */ -+ gcmkCHECK_STATUS(gckVGINTERRUPT_Disable( -+ Kernel->interrupt, -+ command->busErrorInt -+ )); -+ -+ /* Disable TS overflow interrupt. */ -+ if (command->info.tsOverflowInt != -1) -+ { -+ gcmkCHECK_STATUS(gckVGINTERRUPT_Disable( -+ Kernel->interrupt, -+ command->info.tsOverflowInt -+ )); -+ } -+ -+ /* Delete the commit mutex. */ -+ if (command->commitMutex != gcvNULL) -+ { -+ gcmkCHECK_STATUS(gckOS_DeleteMutex( -+ Kernel->os, command->commitMutex -+ )); -+ } -+ -+ /* Delete the command queue mutex. */ -+ if (command->taskMutex != gcvNULL) -+ { -+ gcmkCHECK_STATUS(gckOS_DeleteMutex( -+ Kernel->os, command->taskMutex -+ )); -+ } -+ -+ /* Delete the command queue mutex. */ -+ if (command->queueMutex != gcvNULL) -+ { -+ gcmkCHECK_STATUS(gckOS_DeleteMutex( -+ Kernel->os, command->queueMutex -+ )); -+ } -+ -+ /* Delete the command queue. */ -+ if (command->queue != gcvNULL) -+ { -+ gcmkCHECK_STATUS(gckOS_Free( -+ Kernel->os, command->queue -+ )); -+ } -+ -+ if (command->powerSemaphore != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckOS_DestroySemaphore( -+ Kernel->os, command->powerSemaphore)); -+ } -+ -+ if (command->powerStallSignal != gcvNULL) -+ { -+ /* Create the power management semaphore. */ -+ gcmkVERIFY_OK(gckOS_DestroySignal( -+ Kernel->os, -+ command->powerStallSignal)); -+ } -+ -+ /* Free the gckVGCOMMAND structure. */ -+ gcmkCHECK_STATUS(gckOS_Free( -+ Kernel->os, command -+ )); -+ } -+ -+ gcmkFOOTER(); -+ /* Return the error. */ -+ return status; -+} -+ -+gceSTATUS -+gckVGCOMMAND_Destroy( -+ OUT gckVGCOMMAND Command -+ ) -+{ -+ gceSTATUS status = gcvSTATUS_OK; -+ -+ gcmkHEADER_ARG("Command=0x%x", Command); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND); -+ -+ do -+ { -+ gctUINT i; -+ gcsTASK_STORAGE_PTR nextStorage; -+ -+ if (Command->queueHead != gcvNULL) -+ { -+ /* Wait until the head becomes idle. */ -+ gcmkERR_BREAK(_WaitForIdle(Command, Command->queueHead)); -+ } -+ -+ /* Disable block handlers. */ -+ for (i = 0; i < gcvBLOCK_COUNT; i += 1) -+ { -+ /* Get the interrupt array entry. */ -+ gcsBLOCK_TASK_ENTRY_PTR entry = &Command->taskTable[i]; -+ -+ /* Determine the index of the last interrupt in the array. */ -+ gctINT index = entry->interruptCount - 1; -+ -+ /* Destroy the semaphore. */ -+ if (entry->interruptSemaphore != gcvNULL) -+ { -+ gcmkERR_BREAK(gckOS_DestroySemaphore( -+ Command->os, entry->interruptSemaphore -+ )); -+ } -+ -+ /* Disable all enabled interrupts. */ -+ while (index >= 0) -+ { -+ /* Must be a valid value. */ -+ gcmkASSERT(entry->interruptArray[index] >= 0); -+ gcmkASSERT(entry->interruptArray[index] <= 31); -+ -+ /* Disable the interrupt. */ -+ gcmkERR_BREAK(gckVGINTERRUPT_Disable( -+ Command->kernel->interrupt, -+ entry->interruptArray[index] -+ )); -+ -+ /* Update to the next interrupt. */ -+ index -= 1; -+ entry->interruptCount -= 1; -+ } -+ -+ /* Error? */ -+ if (gcmkIS_ERROR(status)) -+ { -+ break; -+ } -+ } -+ -+ /* Error? */ -+ if (gcmkIS_ERROR(status)) -+ { -+ break; -+ } -+ -+ /* Disable the bus error interrupt. */ -+ gcmkERR_BREAK(gckVGINTERRUPT_Disable( -+ Command->kernel->interrupt, -+ Command->busErrorInt -+ )); -+ -+ /* Disable TS overflow interrupt. */ -+ if (Command->info.tsOverflowInt != -1) -+ { -+ gcmkERR_BREAK(gckVGINTERRUPT_Disable( -+ Command->kernel->interrupt, -+ Command->info.tsOverflowInt -+ )); -+ -+ Command->info.tsOverflowInt = -1; -+ } -+ -+ /* Delete the commit mutex. */ -+ if (Command->commitMutex != gcvNULL) -+ { -+ gcmkERR_BREAK(gckOS_DeleteMutex( -+ Command->os, Command->commitMutex -+ )); -+ -+ Command->commitMutex = gcvNULL; -+ } -+ -+ /* Delete the command queue mutex. */ -+ if (Command->taskMutex != gcvNULL) -+ { -+ gcmkERR_BREAK(gckOS_DeleteMutex( -+ Command->os, Command->taskMutex -+ )); -+ -+ Command->taskMutex = gcvNULL; -+ } -+ -+ /* Delete the command queue mutex. */ -+ if (Command->queueMutex != gcvNULL) -+ { -+ gcmkERR_BREAK(gckOS_DeleteMutex( -+ Command->os, Command->queueMutex -+ )); -+ -+ Command->queueMutex = gcvNULL; -+ } -+ -+ if (Command->powerSemaphore != gcvNULL) -+ { -+ /* Destroy the power management semaphore. */ -+ gcmkERR_BREAK(gckOS_DestroySemaphore( -+ Command->os, Command->powerSemaphore)); -+ } -+ -+ if (Command->powerStallSignal != gcvNULL) -+ { -+ /* Create the power management semaphore. */ -+ gcmkERR_BREAK(gckOS_DestroySignal( -+ Command->os, -+ Command->powerStallSignal)); -+ } -+ -+ if (Command->queue != gcvNULL) -+ { -+ /* Delete the command queue. */ -+ gcmkERR_BREAK(gckOS_Free( -+ Command->os, Command->queue -+ )); -+ } -+ -+ /* Destroy all allocated buffers. */ -+ while (Command->taskStorage) -+ { -+ /* Copy the buffer pointer. */ -+ nextStorage = Command->taskStorage->next; -+ -+ /* Free the current container. */ -+ gcmkERR_BREAK(gckOS_Free( -+ Command->os, Command->taskStorage -+ )); -+ -+ /* Advance to the next one. */ -+ Command->taskStorage = nextStorage; -+ } -+ -+ /* Error? */ -+ if (gcmkIS_ERROR(status)) -+ { -+ break; -+ } -+ -+ /* Mark the object as unknown. */ -+ Command->object.type = gcvOBJ_UNKNOWN; -+ -+ /* Free the gckVGCOMMAND structure. */ -+ gcmkERR_BREAK(gckOS_Free(Command->os, Command)); -+ -+ gcmkFOOTER_NO(); -+ /* Success. */ -+ return gcvSTATUS_OK; -+ } -+ while (gcvFALSE); -+ -+ /* Restore the object type if failed. */ -+ Command->object.type = gcvOBJ_COMMAND; -+ -+ gcmkFOOTER(); -+ /* Return the error. */ -+ return status; -+} -+ -+gceSTATUS -+gckVGCOMMAND_QueryCommandBuffer( -+ IN gckVGCOMMAND Command, -+ OUT gcsCOMMAND_BUFFER_INFO_PTR Information -+ ) -+{ -+ gcmkHEADER_ARG("Command=0x%x Information=0x%x", Command, Information); -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND); -+ gcmkVERIFY_ARGUMENT(Information != gcvNULL); -+ -+ /* Copy the information. */ -+ gcmkVERIFY_OK(gckOS_MemCopy( -+ Information, &Command->info, sizeof(gcsCOMMAND_BUFFER_INFO) -+ )); -+ -+ gcmkFOOTER_NO(); -+ /* Success. */ -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckVGCOMMAND_Allocate( -+ IN gckVGCOMMAND Command, -+ IN gctSIZE_T Size, -+ OUT gcsCMDBUFFER_PTR * CommandBuffer, -+ OUT gctPOINTER * Data -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Command=0x%x Size=0x%x CommandBuffer=0x%x Data=0x%x", -+ Command, Size, CommandBuffer, Data); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND); -+ gcmkVERIFY_ARGUMENT(Data != gcvNULL); -+ -+ do -+ { -+ /* Allocate the buffer. */ -+ gcmkERR_BREAK(_AllocateCommandBuffer(Command, Size, CommandBuffer)); -+ -+ /* Determine the data pointer. */ -+ * Data = (gctUINT8_PTR) (*CommandBuffer) + (* CommandBuffer)->bufferOffset; -+ } -+ while (gcvFALSE); -+ -+ gcmkFOOTER(); -+ /* Return status. */ -+ return status; -+} -+ -+gceSTATUS -+gckVGCOMMAND_Free( -+ IN gckVGCOMMAND Command, -+ IN gcsCMDBUFFER_PTR CommandBuffer -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Command=0x%x CommandBuffer=0x%x", -+ Command, CommandBuffer); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND); -+ gcmkVERIFY_ARGUMENT(CommandBuffer != gcvNULL); -+ -+ /* Free command buffer. */ -+ status = _FreeCommandBuffer(Command->kernel, CommandBuffer); -+ -+ gcmkFOOTER(); -+ /* Return status. */ -+ return status; -+} -+ -+gceSTATUS -+gckVGCOMMAND_Execute( -+ IN gckVGCOMMAND Command, -+ IN gcsCMDBUFFER_PTR CommandBuffer -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Command=0x%x CommandBuffer=0x%x", -+ Command, CommandBuffer); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND); -+ gcmkVERIFY_ARGUMENT(CommandBuffer != gcvNULL); -+ -+ do -+ { -+ gctUINT queueLength; -+ gcsKERNEL_CMDQUEUE_PTR kernelEntry; -+ -+ /* Lock the current queue. */ -+ gcmkERR_BREAK(_LockCurrentQueue( -+ Command, &kernelEntry, &queueLength -+ )); -+ -+ /* Set the buffer. */ -+ kernelEntry->commandBuffer = CommandBuffer; -+ kernelEntry->handler = _FreeKernelCommandBuffer; -+ -+ /* Lock the current queue. */ -+ gcmkERR_BREAK(_UnlockCurrentQueue( -+ Command, 1 -+ )); -+ } -+ while (gcvFALSE); -+ -+ gcmkFOOTER(); -+ /* Return status. */ -+ return status; -+} -+ -+gceSTATUS -+gckVGCOMMAND_Commit( -+ IN gckVGCOMMAND Command, -+ IN gcsVGCONTEXT_PTR Context, -+ IN gcsVGCMDQUEUE_PTR Queue, -+ IN gctUINT EntryCount, -+ IN gcsTASK_MASTER_TABLE_PTR TaskTable -+ ) -+{ -+ /* -+ The first buffer is executed through a direct gckVGHARDWARE_Execute call, -+ therefore only an update is needed after the execution is over. All -+ consequent buffers need to be executed upon the first update call from -+ the FE interrupt handler. -+ */ -+ -+ static gcsQUEUE_UPDATE_CONTROL _dynamicBuffer[] = -+ { -+ { -+ _UpdateDynamicCommandBuffer, -+ _UpdateDynamicCommandBuffer, -+ _UpdateLastDynamicCommandBuffer, -+ _UpdateLastDynamicCommandBuffer -+ }, -+ { -+ _ExecuteDynamicCommandBuffer, -+ _UpdateDynamicCommandBuffer, -+ _ExecuteLastDynamicCommandBuffer, -+ _UpdateLastDynamicCommandBuffer -+ } -+ }; -+ -+ static gcsQUEUE_UPDATE_CONTROL _staticBuffer[] = -+ { -+ { -+ _UpdateStaticCommandBuffer, -+ _UpdateStaticCommandBuffer, -+ _UpdateLastStaticCommandBuffer, -+ _UpdateLastStaticCommandBuffer -+ }, -+ { -+ _ExecuteStaticCommandBuffer, -+ _UpdateStaticCommandBuffer, -+ _ExecuteLastStaticCommandBuffer, -+ _UpdateLastStaticCommandBuffer -+ } -+ }; -+ -+ gceSTATUS status, last; -+ -+ gcmkHEADER_ARG("Command=0x%x Context=0x%x Queue=0x%x EntryCount=0x%x TaskTable=0x%x", -+ Command, Context, Queue, EntryCount, TaskTable); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Command, gcvOBJ_COMMAND); -+ gcmkVERIFY_ARGUMENT(Context != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Queue != gcvNULL); -+ gcmkVERIFY_ARGUMENT(EntryCount > 1); -+ -+ do -+ { -+ gctBOOL haveFETasks; -+ gctUINT queueSize; -+ gcsVGCMDQUEUE_PTR mappedQueue; -+ gcsVGCMDQUEUE_PTR userEntry; -+ gcsKERNEL_CMDQUEUE_PTR kernelEntry; -+ gcsQUEUE_UPDATE_CONTROL_PTR queueControl; -+ gctUINT currentLength; -+ gctUINT queueLength; -+ gctUINT entriesQueued; -+ gctUINT8_PTR previousEnd; -+ gctBOOL previousDynamic; -+ gctBOOL previousExecuted; -+ gctUINT controlIndex; -+ -+ gcmkERR_BREAK(gckVGHARDWARE_SetPowerManagementState( -+ Command->hardware, gcvPOWER_ON_AUTO -+ )); -+ -+ /* Acquire the power semaphore. */ -+ gcmkERR_BREAK(gckOS_AcquireSemaphore( -+ Command->os, Command->powerSemaphore -+ )); -+ -+ /* Acquire the mutex. */ -+ status = gckOS_AcquireMutex( -+ Command->os, -+ Command->commitMutex, -+ gcvINFINITE -+ ); -+ -+ if (gcmIS_ERROR(status)) -+ { -+ gcmkVERIFY_OK(gckOS_ReleaseSemaphore( -+ Command->os, Command->powerSemaphore)); -+ break; -+ } -+ -+ do -+ { -+ gcmkERR_BREAK(_FlushMMU(Command)); -+ -+ /* Assign a context ID if not yet assigned. */ -+ if (Context->id == 0) -+ { -+ /* Assign the next context number. */ -+ Context->id = ++ Command->contextCounter; -+ -+ /* See if we overflowed. */ -+ if (Command->contextCounter == 0) -+ { -+ /* We actually did overflow, wow... */ -+ status = gcvSTATUS_OUT_OF_RESOURCES; -+ break; -+ } -+ } -+ -+ /* The first entry in the queue is always the context buffer. -+ Verify whether the user context is the same as the current -+ context and if that's the case, skip the first entry. */ -+ if (Context->id == Command->currentContext) -+ { -+ /* Same context as before, skip the first entry. */ -+ EntryCount -= 1; -+ Queue += 1; -+ -+ /* Set the signal to avoid user waiting. */ -+ gcmkERR_BREAK(gckOS_UserSignal( -+ Command->os, Context->signal, Context->process -+ )); -+ } -+ else -+ { -+ /* Different user context - keep the first entry. -+ Set the user context as the current one. */ -+ Command->currentContext = Context->id; -+ } -+ -+ /* Reset pointers. */ -+ queueControl = gcvNULL; -+ previousEnd = gcvNULL; -+ -+ /* Determine whether there are FE tasks to be performed. */ -+ haveFETasks = (TaskTable->table[gcvBLOCK_COMMAND].head != gcvNULL); -+ -+ /* Determine the size of the queue. */ -+ queueSize = EntryCount * gcmSIZEOF(gcsVGCMDQUEUE); -+ -+ /* Map the command queue into the kernel space. */ -+ gcmkERR_BREAK(gckOS_MapUserPointer( -+ Command->os, -+ Queue, -+ queueSize, -+ (gctPOINTER *) &mappedQueue -+ )); -+ -+ /* Set the first entry. */ -+ userEntry = mappedQueue; -+ -+ /* Process the command queue. */ -+ while (EntryCount) -+ { -+ /* Lock the current queue. */ -+ gcmkERR_BREAK(_LockCurrentQueue( -+ Command, &kernelEntry, &queueLength -+ )); -+ -+ /* Determine the number of entries to process. */ -+ currentLength = (queueLength < EntryCount) -+ ? queueLength -+ : EntryCount; -+ -+ /* Update the number of the entries left to process. */ -+ EntryCount -= currentLength; -+ -+ /* Reset previous flags. */ -+ previousDynamic = gcvFALSE; -+ previousExecuted = gcvFALSE; -+ -+ /* Set the initial control index. */ -+ controlIndex = 0; -+ -+ /* Process entries. */ -+ for (entriesQueued = 0; entriesQueued < currentLength; entriesQueued += 1) -+ { -+ /* Get the kernel pointer to the command buffer header. */ -+ gcsCMDBUFFER_PTR commandBuffer = gcvNULL; -+ gcmkERR_BREAK(_ConvertUserCommandBufferPointer( -+ Command, -+ userEntry->commandBuffer, -+ &commandBuffer -+ )); -+ -+ /* Is it a dynamic command buffer? */ -+ if (userEntry->dynamic) -+ { -+ /* Select dynamic buffer control functions. */ -+ queueControl = &_dynamicBuffer[controlIndex]; -+ } -+ -+ /* No, a static command buffer. */ -+ else -+ { -+ /* Select static buffer control functions. */ -+ queueControl = &_staticBuffer[controlIndex]; -+ } -+ -+ /* Set the command buffer pointer to the entry. */ -+ kernelEntry->commandBuffer = commandBuffer; -+ -+ /* If the previous entry was a dynamic command buffer, -+ link it to the current. */ -+ if (previousDynamic) -+ { -+ gcmkERR_BREAK(gckVGCOMMAND_FetchCommand( -+ Command, -+ previousEnd, -+ commandBuffer->address, -+ commandBuffer->dataCount, -+ gcvNULL -+ )); -+ -+ /* The buffer will be auto-executed, only need to -+ update it after it has been executed. */ -+ kernelEntry->handler = queueControl->update; -+ -+ /* The buffer is only being updated. */ -+ previousExecuted = gcvFALSE; -+ } -+ else -+ { -+ /* Set the buffer up for execution. */ -+ kernelEntry->handler = queueControl->execute; -+ -+ /* The buffer is being updated. */ -+ previousExecuted = gcvTRUE; -+ } -+ -+ /* The current buffer's END command becomes the last END. */ -+ previousEnd -+ = ((gctUINT8_PTR) commandBuffer) -+ + commandBuffer->bufferOffset -+ + commandBuffer->dataCount * Command->info.commandAlignment -+ - Command->info.staticTailSize; -+ -+ /* Update the last entry info. */ -+ previousDynamic = userEntry->dynamic; -+ -+ /* Advance entries. */ -+ userEntry += 1; -+ kernelEntry += 1; -+ -+ /* Update the control index. */ -+ controlIndex = 1; -+ } -+ -+ /* If the previous entry was a dynamic command buffer, -+ terminate it with an END. */ -+ if (previousDynamic) -+ { -+ gcmkERR_BREAK(gckVGCOMMAND_EndCommand( -+ Command, -+ previousEnd, -+ Command->info.feBufferInt, -+ gcvNULL -+ )); -+ } -+ -+ /* Last buffer? */ -+ if (EntryCount == 0) -+ { -+ /* Modify the last command buffer's routines to handle -+ tasks if any.*/ -+ if (haveFETasks) -+ { -+ if (previousExecuted) -+ { -+ kernelEntry[-1].handler = queueControl->lastExecute; -+ } -+ else -+ { -+ kernelEntry[-1].handler = queueControl->lastUpdate; -+ } -+ } -+ -+ /* Release the mutex. */ -+ gcmkERR_BREAK(gckOS_ReleaseMutex( -+ Command->os, -+ Command->queueMutex -+ )); -+ /* Schedule tasks. */ -+ gcmkERR_BREAK(_ScheduleTasks(Command, TaskTable, previousEnd)); -+ -+ /* Acquire the mutex. */ -+ gcmkERR_BREAK(gckOS_AcquireMutex( -+ Command->os, -+ Command->queueMutex, -+ gcvINFINITE -+ )); -+ } -+ -+ /* Unkock and schedule the current queue for execution. */ -+ gcmkERR_BREAK(_UnlockCurrentQueue( -+ Command, currentLength -+ )); -+ } -+ -+ -+ /* Unmap the user command buffer. */ -+ gcmkERR_BREAK(gckOS_UnmapUserPointer( -+ Command->os, -+ Queue, -+ queueSize, -+ mappedQueue -+ )); -+ } -+ while (gcvFALSE); -+ -+ /* Release the mutex. */ -+ gcmkCHECK_STATUS(gckOS_ReleaseMutex( -+ Command->os, -+ Command->commitMutex -+ )); -+ -+ gcmkVERIFY_OK(gckOS_ReleaseSemaphore( -+ Command->os, Command->powerSemaphore)); -+ } -+ while (gcvFALSE); -+ -+ gcmkFOOTER(); -+ /* Return status. */ -+ return status; -+} -+ -+#endif /* gcdENABLE_VG */ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_db.c linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_db.c ---- linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_db.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_db.c 2015-11-30 17:56:13.572138258 +0100 -@@ -0,0 +1,1758 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#include "gc_hal_kernel_precomp.h" -+ -+#define _GC_OBJ_ZONE gcvZONE_DATABASE -+ -+/******************************************************************************* -+***** Private fuctions ********************************************************/ -+ -+#define _GetSlot(database, x) \ -+ (gctUINT32)(gcmPTR_TO_UINT64(x) % gcmCOUNTOF(database->list)) -+ -+/******************************************************************************* -+** gckKERNEL_NewDatabase -+** -+** Create a new database structure and insert it to the head of the hash list. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to a gckKERNEL object. -+** -+** gctUINT32 ProcessID -+** ProcessID that identifies the database. -+** -+** OUTPUT: -+** -+** gcsDATABASE_PTR * Database -+** Pointer to a variable receiving the database structure pointer on -+** success. -+*/ -+static gceSTATUS -+gckKERNEL_NewDatabase( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 ProcessID, -+ OUT gcsDATABASE_PTR * Database -+ ) -+{ -+ gceSTATUS status; -+ gcsDATABASE_PTR database; -+ gctBOOL acquired = gcvFALSE; -+ gctSIZE_T slot; -+ gcsDATABASE_PTR existingDatabase; -+ -+ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d", Kernel, ProcessID); -+ -+ /* Acquire the database mutex. */ -+ gcmkONERROR(gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ /* Compute the hash for the database. */ -+ slot = ProcessID % gcmCOUNTOF(Kernel->db->db); -+ -+ /* Walk the hash list. */ -+ for (existingDatabase = Kernel->db->db[slot]; -+ existingDatabase != gcvNULL; -+ existingDatabase = existingDatabase->next) -+ { -+ if (existingDatabase->processID == ProcessID) -+ { -+ /* One process can't be added twice. */ -+ gcmkONERROR(gcvSTATUS_NOT_SUPPORTED); -+ } -+ } -+ -+ if (Kernel->db->freeDatabase != gcvNULL) -+ { -+ /* Allocate a database from the free list. */ -+ database = Kernel->db->freeDatabase; -+ Kernel->db->freeDatabase = database->next; -+ } -+ else -+ { -+ gctPOINTER pointer = gcvNULL; -+ -+ /* Allocate a new database from the heap. */ -+ gcmkONERROR(gckOS_Allocate(Kernel->os, -+ gcmSIZEOF(gcsDATABASE), -+ &pointer)); -+ -+ gckOS_ZeroMemory(pointer, gcmSIZEOF(gcsDATABASE)); -+ -+ database = pointer; -+ -+ gcmkONERROR(gckOS_CreateMutex(Kernel->os, &database->counterMutex)); -+ } -+ -+ /* Insert the database into the hash. */ -+ database->next = Kernel->db->db[slot]; -+ Kernel->db->db[slot] = database; -+ -+ /* Save the hash slot. */ -+ database->slot = slot; -+ -+ /* Release the database mutex. */ -+ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex)); -+ -+ /* Return the database. */ -+ *Database = database; -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Database=0x%x", *Database); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (acquired) -+ { -+ /* Release the database mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex)); -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** gckKERNEL_FindDatabase -+** -+** Find a database identified by a process ID and move it to the head of the -+** hash list. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to a gckKERNEL object. -+** -+** gctUINT32 ProcessID -+** ProcessID that identifies the database. -+** -+** gctBOOL LastProcessID -+** gcvTRUE if searching for the last known process ID. gcvFALSE if -+** we need to search for the process ID specified by the ProcessID -+** argument. -+** -+** OUTPUT: -+** -+** gcsDATABASE_PTR * Database -+** Pointer to a variable receiving the database structure pointer on -+** success. -+*/ -+gceSTATUS -+gckKERNEL_FindDatabase( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 ProcessID, -+ IN gctBOOL LastProcessID, -+ OUT gcsDATABASE_PTR * Database -+ ) -+{ -+ gceSTATUS status; -+ gcsDATABASE_PTR database, previous; -+ gctSIZE_T slot; -+ gctBOOL acquired = gcvFALSE; -+ -+ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d LastProcessID=%d", -+ Kernel, ProcessID, LastProcessID); -+ -+ /* Compute the hash for the database. */ -+ slot = ProcessID % gcmCOUNTOF(Kernel->db->db); -+ -+ /* Acquire the database mutex. */ -+ gcmkONERROR( -+ gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ /* Check whether we are getting the last known database. */ -+ if (LastProcessID) -+ { -+ /* Use last database. */ -+ database = Kernel->db->lastDatabase; -+ -+ if (database == gcvNULL) -+ { -+ /* Database not found. */ -+ gcmkONERROR(gcvSTATUS_INVALID_DATA); -+ } -+ } -+ else -+ { -+ /* Walk the hash list. */ -+ for (previous = gcvNULL, database = Kernel->db->db[slot]; -+ database != gcvNULL; -+ database = database->next) -+ { -+ if (database->processID == ProcessID) -+ { -+ /* Found it! */ -+ break; -+ } -+ -+ previous = database; -+ } -+ -+ if (database == gcvNULL) -+ { -+ /* Database not found. */ -+ gcmkONERROR(gcvSTATUS_INVALID_DATA); -+ } -+ -+ if (previous != gcvNULL) -+ { -+ /* Move database to the head of the hash list. */ -+ previous->next = database->next; -+ database->next = Kernel->db->db[slot]; -+ Kernel->db->db[slot] = database; -+ } -+ } -+ -+ /* Release the database mutex. */ -+ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex)); -+ -+ /* Return the database. */ -+ *Database = database; -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Database=0x%x", *Database); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (acquired) -+ { -+ /* Release the database mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex)); -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** gckKERNEL_DeleteDatabase -+** -+** Remove a database from the hash list and delete its structure. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to a gckKERNEL object. -+** -+** gcsDATABASE_PTR Database -+** Pointer to the database structure to remove. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+static gceSTATUS -+gckKERNEL_DeleteDatabase( -+ IN gckKERNEL Kernel, -+ IN gcsDATABASE_PTR Database -+ ) -+{ -+ gceSTATUS status; -+ gctBOOL acquired = gcvFALSE; -+ gcsDATABASE_PTR database; -+ -+ gcmkHEADER_ARG("Kernel=0x%x Database=0x%x", Kernel, Database); -+ -+ /* Acquire the database mutex. */ -+ gcmkONERROR( -+ gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ /* Check slot value. */ -+ gcmkVERIFY_ARGUMENT(Database->slot < gcmCOUNTOF(Kernel->db->db)); -+ -+ if (Database->slot < gcmCOUNTOF(Kernel->db->db)) -+ { -+ /* Check if database if the head of the hash list. */ -+ if (Kernel->db->db[Database->slot] == Database) -+ { -+ /* Remove the database from the hash list. */ -+ Kernel->db->db[Database->slot] = Database->next; -+ } -+ else -+ { -+ /* Walk the has list to find the database. */ -+ for (database = Kernel->db->db[Database->slot]; -+ database != gcvNULL; -+ database = database->next -+ ) -+ { -+ /* Check if the next list entry is this database. */ -+ if (database->next == Database) -+ { -+ /* Remove the database from the hash list. */ -+ database->next = Database->next; -+ break; -+ } -+ } -+ -+ if (database == gcvNULL) -+ { -+ /* Ouch! Something got corrupted. */ -+ gcmkONERROR(gcvSTATUS_INVALID_DATA); -+ } -+ } -+ } -+ -+ if (Kernel->db->lastDatabase != gcvNULL) -+ { -+ /* Insert database to the free list. */ -+ Kernel->db->lastDatabase->next = Kernel->db->freeDatabase; -+ Kernel->db->freeDatabase = Kernel->db->lastDatabase; -+ } -+ -+ /* Keep database as the last database. */ -+ Kernel->db->lastDatabase = Database; -+ -+ /* Destory handle db. */ -+ gcmkVERIFY_OK(gckKERNEL_DestroyIntegerDatabase(Kernel, Database->handleDatabase)); -+ Database->handleDatabase = gcvNULL; -+ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, Database->handleDatabaseMutex)); -+ Database->handleDatabaseMutex = gcvNULL; -+ -+#if gcdPROCESS_ADDRESS_SPACE -+ /* Destory process MMU. */ -+ gcmkVERIFY_OK(gckEVENT_DestroyMmu(Kernel->eventObj, Database->mmu, gcvKERNEL_PIXEL)); -+ Database->mmu = gcvNULL; -+#endif -+ -+ /* Release the database mutex. */ -+ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (acquired) -+ { -+ /* Release the database mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex)); -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** gckKERNEL_NewRecord -+** -+** Create a new database record structure and insert it to the head of the -+** database. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to a gckKERNEL object. -+** -+** gcsDATABASE_PTR Database -+** Pointer to a database structure. -+** -+** OUTPUT: -+** -+** gcsDATABASE_RECORD_PTR * Record -+** Pointer to a variable receiving the database record structure -+** pointer on success. -+*/ -+static gceSTATUS -+gckKERNEL_NewRecord( -+ IN gckKERNEL Kernel, -+ IN gcsDATABASE_PTR Database, -+ IN gctUINT32 Slot, -+ OUT gcsDATABASE_RECORD_PTR * Record -+ ) -+{ -+ gceSTATUS status; -+ gctBOOL acquired = gcvFALSE; -+ gcsDATABASE_RECORD_PTR record = gcvNULL; -+ -+ gcmkHEADER_ARG("Kernel=0x%x Database=0x%x", Kernel, Database); -+ -+ /* Acquire the database mutex. */ -+ gcmkONERROR( -+ gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ if (Kernel->db->freeRecord != gcvNULL) -+ { -+ /* Allocate the record from the free list. */ -+ record = Kernel->db->freeRecord; -+ Kernel->db->freeRecord = record->next; -+ } -+ else -+ { -+ gctPOINTER pointer = gcvNULL; -+ -+ /* Allocate the record from the heap. */ -+ gcmkONERROR(gckOS_Allocate(Kernel->os, -+ gcmSIZEOF(gcsDATABASE_RECORD), -+ &pointer)); -+ -+ record = pointer; -+ } -+ -+ /* Insert the record in the database. */ -+ record->next = Database->list[Slot]; -+ Database->list[Slot] = record; -+ -+ /* Release the database mutex. */ -+ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex)); -+ -+ /* Return the record. */ -+ *Record = record; -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Record=0x%x", *Record); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (acquired) -+ { -+ /* Release the database mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex)); -+ } -+ if (record != gcvNULL) -+ { -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, record)); -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** gckKERNEL_DeleteRecord -+** -+** Remove a database record from the database and delete its structure. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to a gckKERNEL object. -+** -+** gcsDATABASE_PTR Database -+** Pointer to a database structure. -+** -+** gceDATABASE_TYPE Type -+** Type of the record to remove. -+** -+** gctPOINTER Data -+** Data of the record to remove. -+** -+** OUTPUT: -+** -+** gctSIZE_T_PTR Bytes -+** Pointer to a variable that receives the size of the record deleted. -+** Can be gcvNULL if the size is not required. -+*/ -+static gceSTATUS -+gckKERNEL_DeleteRecord( -+ IN gckKERNEL Kernel, -+ IN gcsDATABASE_PTR Database, -+ IN gceDATABASE_TYPE Type, -+ IN gctPOINTER Data, -+ OUT gctSIZE_T_PTR Bytes OPTIONAL -+ ) -+{ -+ gceSTATUS status; -+ gctBOOL acquired = gcvFALSE; -+ gcsDATABASE_RECORD_PTR record, previous; -+ gctUINT32 slot = _GetSlot(Database, Data); -+ -+ gcmkHEADER_ARG("Kernel=0x%x Database=0x%x Type=%d Data=0x%x", -+ Kernel, Database, Type, Data); -+ -+ /* Acquire the database mutex. */ -+ gcmkONERROR( -+ gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ /* Scan the database for this record. */ -+ for (record = Database->list[slot], previous = gcvNULL; -+ record != gcvNULL; -+ record = record->next -+ ) -+ { -+ if ((record->type == Type) -+ && (record->data == Data) -+ ) -+ { -+ /* Found it! */ -+ break; -+ } -+ -+ previous = record; -+ } -+ -+ if (record == gcvNULL) -+ { -+ /* Ouch! This record is not found? */ -+ gcmkONERROR(gcvSTATUS_INVALID_DATA); -+ } -+ -+ if (Bytes != gcvNULL) -+ { -+ /* Return size of record. */ -+ *Bytes = record->bytes; -+ } -+ -+ /* Remove record from database. */ -+ if (previous == gcvNULL) -+ { -+ Database->list[slot] = record->next; -+ } -+ else -+ { -+ previous->next = record->next; -+ } -+ -+ /* Insert record in free list. */ -+ record->next = Kernel->db->freeRecord; -+ Kernel->db->freeRecord = record; -+ -+ /* Release the database mutex. */ -+ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex)); -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Bytes=%lu", gcmOPT_VALUE(Bytes)); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (acquired) -+ { -+ /* Release the database mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex)); -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** gckKERNEL_FindRecord -+** -+** Find a database record from the database. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to a gckKERNEL object. -+** -+** gcsDATABASE_PTR Database -+** Pointer to a database structure. -+** -+** gceDATABASE_TYPE Type -+** Type of the record to remove. -+** -+** gctPOINTER Data -+** Data of the record to remove. -+** -+** OUTPUT: -+** -+** gctSIZE_T_PTR Bytes -+** Pointer to a variable that receives the size of the record deleted. -+** Can be gcvNULL if the size is not required. -+*/ -+static gceSTATUS -+gckKERNEL_FindRecord( -+ IN gckKERNEL Kernel, -+ IN gcsDATABASE_PTR Database, -+ IN gceDATABASE_TYPE Type, -+ IN gctPOINTER Data, -+ OUT gcsDATABASE_RECORD_PTR Record -+ ) -+{ -+ gceSTATUS status; -+ gctBOOL acquired = gcvFALSE; -+ gcsDATABASE_RECORD_PTR record; -+ gctUINT32 slot = _GetSlot(Database, Data); -+ -+ gcmkHEADER_ARG("Kernel=0x%x Database=0x%x Type=%d Data=0x%x", -+ Kernel, Database, Type, Data); -+ -+ /* Acquire the database mutex. */ -+ gcmkONERROR( -+ gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ /* Scan the database for this record. */ -+ for (record = Database->list[slot]; -+ record != gcvNULL; -+ record = record->next -+ ) -+ { -+ if ((record->type == Type) -+ && (record->data == Data) -+ ) -+ { -+ /* Found it! */ -+ break; -+ } -+ } -+ -+ if (record == gcvNULL) -+ { -+ /* Ouch! This record is not found? */ -+ gcmkONERROR(gcvSTATUS_INVALID_DATA); -+ } -+ -+ if (Record != gcvNULL) -+ { -+ /* Return information of record. */ -+ gcmkONERROR( -+ gckOS_MemCopy(Record, record, sizeof(gcsDATABASE_RECORD))); -+ } -+ -+ /* Release the database mutex. */ -+ gcmkONERROR(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex)); -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("Record=0x%x", Record); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (acquired) -+ { -+ /* Release the database mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex)); -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+***** Public API **************************************************************/ -+ -+/******************************************************************************* -+** gckKERNEL_CreateProcessDB -+** -+** Create a new process database. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to a gckKERNEL object. -+** -+** gctUINT32 ProcessID -+** Process ID used to identify the database. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckKERNEL_CreateProcessDB( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 ProcessID -+ ) -+{ -+ gceSTATUS status; -+ gcsDATABASE_PTR database = gcvNULL; -+ gctUINT32 i; -+ -+ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d", Kernel, ProcessID); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ -+ /* Create a new database. */ -+ gcmkONERROR(gckKERNEL_NewDatabase(Kernel, ProcessID, &database)); -+ -+ /* Initialize the database. */ -+ database->processID = ProcessID; -+ database->vidMem.bytes = 0; -+ database->vidMem.maxBytes = 0; -+ database->vidMem.totalBytes = 0; -+ database->nonPaged.bytes = 0; -+ database->nonPaged.maxBytes = 0; -+ database->nonPaged.totalBytes = 0; -+ database->contiguous.bytes = 0; -+ database->contiguous.maxBytes = 0; -+ database->contiguous.totalBytes = 0; -+ database->mapMemory.bytes = 0; -+ database->mapMemory.maxBytes = 0; -+ database->mapMemory.totalBytes = 0; -+ database->mapUserMemory.bytes = 0; -+ database->mapUserMemory.maxBytes = 0; -+ database->mapUserMemory.totalBytes = 0; -+ database->virtualCommandBuffer.bytes = 0; -+ database->virtualCommandBuffer.maxBytes = 0; -+ database->virtualCommandBuffer.totalBytes = 0; -+ -+ for (i = 0; i < gcmCOUNTOF(database->list); i++) -+ { -+ database->list[i] = gcvNULL; -+ } -+ -+ for (i = 0; i < gcvSURF_NUM_TYPES; i++) -+ { -+ database->vidMemType[i].bytes = 0; -+ database->vidMemType[i].maxBytes = 0; -+ database->vidMemType[i].totalBytes = 0; -+ } -+ -+ for (i = 0; i < gcvPOOL_NUMBER_OF_POOLS; i++) -+ { -+ database->vidMemPool[i].bytes = 0; -+ database->vidMemPool[i].maxBytes = 0; -+ database->vidMemPool[i].totalBytes = 0; -+ } -+ -+ gcmkASSERT(database->handleDatabase == gcvNULL); -+ gcmkONERROR( -+ gckKERNEL_CreateIntegerDatabase(Kernel, &database->handleDatabase)); -+ -+ gcmkASSERT(database->handleDatabaseMutex == gcvNULL); -+ gcmkONERROR( -+ gckOS_CreateMutex(Kernel->os, &database->handleDatabaseMutex)); -+ -+#if gcdPROCESS_ADDRESS_SPACE -+ gcmkASSERT(database->mmu == gcvNULL); -+ gcmkONERROR( -+ gckMMU_Construct(Kernel, gcdMMU_SIZE, &database->mmu)); -+#endif -+ -+ /* Reset idle timer. */ -+ Kernel->db->lastIdle = 0; -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** gckKERNEL_AddProcessDB -+** -+** Add a record to a process database. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to a gckKERNEL object. -+** -+** gctUINT32 ProcessID -+** Process ID used to identify the database. -+** -+** gceDATABASE_TYPE TYPE -+** Type of the record to add. -+** -+** gctPOINTER Pointer -+** Data of the record to add. -+** -+** gctPHYS_ADDR Physical -+** Physical address of the record to add. -+** -+** gctSIZE_T Size -+** Size of the record to add. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckKERNEL_AddProcessDB( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 ProcessID, -+ IN gceDATABASE_TYPE Type, -+ IN gctPOINTER Pointer, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T Size -+ ) -+{ -+ gceSTATUS status; -+ gcsDATABASE_PTR database; -+ gcsDATABASE_RECORD_PTR record = gcvNULL; -+ gcsDATABASE_COUNTERS * count; -+ gctUINT32 vidMemType; -+ gcePOOL vidMemPool; -+ -+ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d Type=%d Pointer=0x%x " -+ "Physical=0x%x Size=%lu", -+ Kernel, ProcessID, Type, Pointer, Physical, Size); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ -+ /* Decode type. */ -+ vidMemType = (Type & gcdDB_VIDEO_MEMORY_TYPE_MASK) >> gcdDB_VIDEO_MEMORY_TYPE_SHIFT; -+ vidMemPool = (Type & gcdDB_VIDEO_MEMORY_POOL_MASK) >> gcdDB_VIDEO_MEMORY_POOL_SHIFT; -+ -+ Type &= gcdDATABASE_TYPE_MASK; -+ -+ /* Special case the idle record. */ -+ if (Type == gcvDB_IDLE) -+ { -+ gctUINT64 time; -+ -+ /* Get the current profile time. */ -+ gcmkONERROR(gckOS_GetProfileTick(&time)); -+ -+ if ((ProcessID == 0) && (Kernel->db->lastIdle != 0)) -+ { -+ /* Out of idle, adjust time it was idle. */ -+ Kernel->db->idleTime += time - Kernel->db->lastIdle; -+ Kernel->db->lastIdle = 0; -+ } -+ else if (ProcessID == 1) -+ { -+ /* Save current idle time. */ -+ Kernel->db->lastIdle = time; -+ } -+ -+#if gcdDYNAMIC_SPEED -+ { -+ /* Test for first call. */ -+ if (Kernel->db->lastSlowdown == 0) -+ { -+ /* Save milliseconds. */ -+ Kernel->db->lastSlowdown = time; -+ Kernel->db->lastSlowdownIdle = Kernel->db->idleTime; -+ } -+ else -+ { -+ /* Compute ellapsed time in milliseconds. */ -+ gctUINT delta = gckOS_ProfileToMS(time - Kernel->db->lastSlowdown); -+ -+ /* Test for end of period. */ -+ if (delta >= gcdDYNAMIC_SPEED) -+ { -+ /* Compute number of idle milliseconds. */ -+ gctUINT idle = gckOS_ProfileToMS( -+ Kernel->db->idleTime - Kernel->db->lastSlowdownIdle); -+ -+ /* Broadcast to slow down the GPU. */ -+ gcmkONERROR(gckOS_BroadcastCalibrateSpeed(Kernel->os, -+ Kernel->hardware, -+ idle, -+ delta)); -+ -+ /* Save current time. */ -+ Kernel->db->lastSlowdown = time; -+ Kernel->db->lastSlowdownIdle = Kernel->db->idleTime; -+ } -+ } -+ } -+#endif -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ } -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL); -+ -+ /* Find the database. */ -+ gcmkONERROR(gckKERNEL_FindDatabase(Kernel, ProcessID, gcvFALSE, &database)); -+ -+ /* Create a new record in the database. */ -+ gcmkONERROR(gckKERNEL_NewRecord(Kernel, database, _GetSlot(database, Pointer), &record)); -+ -+ /* Initialize the record. */ -+ record->kernel = Kernel; -+ record->type = Type; -+ record->data = Pointer; -+ record->physical = Physical; -+ record->bytes = Size; -+ -+ /* Get pointer to counters. */ -+ switch (Type) -+ { -+ case gcvDB_VIDEO_MEMORY: -+ count = &database->vidMem; -+ break; -+ -+ case gcvDB_NON_PAGED: -+ count = &database->nonPaged; -+ break; -+ -+ case gcvDB_CONTIGUOUS: -+ count = &database->contiguous; -+ break; -+ -+ case gcvDB_MAP_MEMORY: -+ count = &database->mapMemory; -+ break; -+ -+ case gcvDB_MAP_USER_MEMORY: -+ count = &database->mapUserMemory; -+ break; -+ -+ case gcvDB_COMMAND_BUFFER: -+ count = &database->virtualCommandBuffer; -+ break; -+ -+ default: -+ count = gcvNULL; -+ break; -+ } -+ -+ gcmkVERIFY_OK(gckOS_AcquireMutex(Kernel->os, database->counterMutex, gcvINFINITE)); -+ -+ if (count != gcvNULL) -+ { -+ /* Adjust counters. */ -+ count->totalBytes += Size; -+ count->bytes += Size; -+ -+ if (count->bytes > count->maxBytes) -+ { -+ count->maxBytes = count->bytes; -+ } -+ } -+ -+ if (Type == gcvDB_VIDEO_MEMORY) -+ { -+ count = &database->vidMemType[vidMemType]; -+ -+ /* Adjust counters. */ -+ count->totalBytes += Size; -+ count->bytes += Size; -+ -+ if (count->bytes > count->maxBytes) -+ { -+ count->maxBytes = count->bytes; -+ } -+ -+ count = &database->vidMemPool[vidMemPool]; -+ -+ /* Adjust counters. */ -+ count->totalBytes += Size; -+ count->bytes += Size; -+ -+ if (count->bytes > count->maxBytes) -+ { -+ count->maxBytes = count->bytes; -+ } -+ } -+ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, database->counterMutex)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** gckKERNEL_RemoveProcessDB -+** -+** Remove a record from a process database. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to a gckKERNEL object. -+** -+** gctUINT32 ProcessID -+** Process ID used to identify the database. -+** -+** gceDATABASE_TYPE TYPE -+** Type of the record to remove. -+** -+** gctPOINTER Pointer -+** Data of the record to remove. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckKERNEL_RemoveProcessDB( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 ProcessID, -+ IN gceDATABASE_TYPE Type, -+ IN gctPOINTER Pointer -+ ) -+{ -+ gceSTATUS status; -+ gcsDATABASE_PTR database; -+ gctSIZE_T bytes = 0; -+ gctUINT32 vidMemType; -+ gcePOOL vidMempool; -+ -+ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d Type=%d Pointer=0x%x", -+ Kernel, ProcessID, Type, Pointer); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL); -+ -+ /* Decode type. */ -+ vidMemType = (Type & gcdDB_VIDEO_MEMORY_TYPE_MASK) >> gcdDB_VIDEO_MEMORY_TYPE_SHIFT; -+ vidMempool = (Type & gcdDB_VIDEO_MEMORY_POOL_MASK) >> gcdDB_VIDEO_MEMORY_POOL_SHIFT; -+ -+ Type &= gcdDATABASE_TYPE_MASK; -+ -+ /* Find the database. */ -+ gcmkONERROR(gckKERNEL_FindDatabase(Kernel, ProcessID, gcvFALSE, &database)); -+ -+ /* Delete the record. */ -+ gcmkONERROR( -+ gckKERNEL_DeleteRecord(Kernel, database, Type, Pointer, &bytes)); -+ -+ gcmkVERIFY_OK(gckOS_AcquireMutex(Kernel->os, database->counterMutex, gcvINFINITE)); -+ -+ /* Update counters. */ -+ switch (Type) -+ { -+ case gcvDB_VIDEO_MEMORY: -+ database->vidMem.bytes -= bytes; -+ database->vidMemType[vidMemType].bytes -= bytes; -+ database->vidMemPool[vidMempool].bytes -= bytes; -+ break; -+ -+ case gcvDB_NON_PAGED: -+ database->nonPaged.bytes -= bytes; -+ break; -+ -+ case gcvDB_CONTIGUOUS: -+ database->contiguous.bytes -= bytes; -+ break; -+ -+ case gcvDB_MAP_MEMORY: -+ database->mapMemory.bytes -= bytes; -+ break; -+ -+ case gcvDB_MAP_USER_MEMORY: -+ database->mapUserMemory.bytes -= bytes; -+ break; -+ -+ case gcvDB_COMMAND_BUFFER: -+ database->virtualCommandBuffer.bytes -= bytes; -+ break; -+ -+ default: -+ break; -+ } -+ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, database->counterMutex)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** gckKERNEL_FindProcessDB -+** -+** Find a record from a process database. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to a gckKERNEL object. -+** -+** gctUINT32 ProcessID -+** Process ID used to identify the database. -+** -+** gceDATABASE_TYPE TYPE -+** Type of the record to remove. -+** -+** gctPOINTER Pointer -+** Data of the record to remove. -+** -+** OUTPUT: -+** -+** gcsDATABASE_RECORD_PTR Record -+** Copy of record. -+*/ -+gceSTATUS -+gckKERNEL_FindProcessDB( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 ProcessID, -+ IN gctUINT32 ThreadID, -+ IN gceDATABASE_TYPE Type, -+ IN gctPOINTER Pointer, -+ OUT gcsDATABASE_RECORD_PTR Record -+ ) -+{ -+ gceSTATUS status; -+ gcsDATABASE_PTR database; -+ -+ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d Type=%d Pointer=0x%x", -+ Kernel, ProcessID, ThreadID, Type, Pointer); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL); -+ -+ /* Find the database. */ -+ gcmkONERROR(gckKERNEL_FindDatabase(Kernel, ProcessID, gcvFALSE, &database)); -+ -+ /* Find the record. */ -+ gcmkONERROR( -+ gckKERNEL_FindRecord(Kernel, database, Type, Pointer, Record)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** gckKERNEL_DestroyProcessDB -+** -+** Destroy a process database. If the database contains any records, the data -+** inside those records will be deleted as well. This aids in the cleanup if -+** a process has died unexpectedly or has memory leaks. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to a gckKERNEL object. -+** -+** gctUINT32 ProcessID -+** Process ID used to identify the database. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckKERNEL_DestroyProcessDB( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 ProcessID -+ ) -+{ -+ gceSTATUS status; -+ gcsDATABASE_PTR database; -+ gcsDATABASE_RECORD_PTR record, next; -+ gctBOOL asynchronous = gcvTRUE; -+ gckVIDMEM_NODE nodeObject; -+ gctPHYS_ADDR physical; -+ gckKERNEL kernel = Kernel; -+ gctUINT32 handle; -+ gctUINT32 i; -+ -+ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d", Kernel, ProcessID); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ -+ /* Find the database. */ -+ gcmkONERROR(gckKERNEL_FindDatabase(Kernel, ProcessID, gcvFALSE, &database)); -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DATABASE, -+ "DB(%d): VidMem: total=%lu max=%lu", -+ ProcessID, database->vidMem.totalBytes, -+ database->vidMem.maxBytes); -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DATABASE, -+ "DB(%d): NonPaged: total=%lu max=%lu", -+ ProcessID, database->nonPaged.totalBytes, -+ database->nonPaged.maxBytes); -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DATABASE, -+ "DB(%d): Contiguous: total=%lu max=%lu", -+ ProcessID, database->contiguous.totalBytes, -+ database->contiguous.maxBytes); -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DATABASE, -+ "DB(%d): Idle time=%llu", -+ ProcessID, Kernel->db->idleTime); -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DATABASE, -+ "DB(%d): Map: total=%lu max=%lu", -+ ProcessID, database->mapMemory.totalBytes, -+ database->mapMemory.maxBytes); -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DATABASE, -+ "DB(%d): Map: total=%lu max=%lu", -+ ProcessID, database->mapUserMemory.totalBytes, -+ database->mapUserMemory.maxBytes); -+ -+ if (database->list != gcvNULL) -+ { -+ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE, -+ "Process %d has entries in its database:", -+ ProcessID); -+ } -+ -+ for(i = 0; i < gcmCOUNTOF(database->list); i++) -+ { -+ -+ /* Walk all records. */ -+ for (record = database->list[i]; record != gcvNULL; record = next) -+ { -+ /* Next next record. */ -+ next = record->next; -+ -+ /* Dispatch on record type. */ -+ switch (record->type) -+ { -+ case gcvDB_VIDEO_MEMORY: -+ gcmkERR_BREAK(gckVIDMEM_HANDLE_Lookup(record->kernel, -+ ProcessID, -+ gcmPTR2INT32(record->data), -+ &nodeObject)); -+ -+ /* Free the video memory. */ -+ gcmkVERIFY_OK(gckVIDMEM_HANDLE_Dereference(record->kernel, -+ ProcessID, -+ gcmPTR2INT32(record->data))); -+ -+ gcmkVERIFY_OK(gckVIDMEM_NODE_Dereference(record->kernel, -+ nodeObject)); -+ -+ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE, -+ "DB: VIDEO_MEMORY 0x%x (status=%d)", -+ record->data, status); -+ break; -+ -+ case gcvDB_NON_PAGED: -+ physical = gcmNAME_TO_PTR(record->physical); -+ /* Unmap user logical memory first. */ -+ status = gckOS_UnmapUserLogical(Kernel->os, -+ physical, -+ record->bytes, -+ record->data); -+ -+ /* Free the non paged memory. */ -+ status = gckEVENT_FreeNonPagedMemory(Kernel->eventObj, -+ record->bytes, -+ physical, -+ record->data, -+ gcvKERNEL_PIXEL); -+ gcmRELEASE_NAME(record->physical); -+ -+ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE, -+ "DB: NON_PAGED 0x%x, bytes=%lu (status=%d)", -+ record->data, record->bytes, status); -+ break; -+ -+ case gcvDB_COMMAND_BUFFER: -+ /* Free the command buffer. */ -+ status = gckEVENT_DestroyVirtualCommandBuffer(record->kernel->eventObj, -+ record->bytes, -+ gcmNAME_TO_PTR(record->physical), -+ record->data, -+ gcvKERNEL_PIXEL); -+ gcmRELEASE_NAME(record->physical); -+ -+ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE, -+ "DB: COMMAND_BUFFER 0x%x, bytes=%lu (status=%d)", -+ record->data, record->bytes, status); -+ break; -+ -+ case gcvDB_CONTIGUOUS: -+ physical = gcmNAME_TO_PTR(record->physical); -+ /* Unmap user logical memory first. */ -+ status = gckOS_UnmapUserLogical(Kernel->os, -+ physical, -+ record->bytes, -+ record->data); -+ -+ /* Free the contiguous memory. */ -+ status = gckEVENT_FreeContiguousMemory(Kernel->eventObj, -+ record->bytes, -+ physical, -+ record->data, -+ gcvKERNEL_PIXEL); -+ gcmRELEASE_NAME(record->physical); -+ -+ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE, -+ "DB: CONTIGUOUS 0x%x bytes=%lu (status=%d)", -+ record->data, record->bytes, status); -+ break; -+ -+ case gcvDB_SIGNAL: -+ /* Free the user signal. */ -+ status = gckOS_DestroyUserSignal(Kernel->os, -+ gcmPTR2INT32(record->data)); -+ -+ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE, -+ "DB: SIGNAL %d (status=%d)", -+ (gctINT)(gctUINTPTR_T)record->data, status); -+ break; -+ -+ case gcvDB_VIDEO_MEMORY_LOCKED: -+ handle = gcmPTR2INT32(record->data); -+ -+ gcmkERR_BREAK(gckVIDMEM_HANDLE_Lookup(record->kernel, -+ ProcessID, -+ handle, -+ &nodeObject)); -+ -+ /* Unlock what we still locked */ -+ status = gckVIDMEM_Unlock(record->kernel, -+ nodeObject, -+ nodeObject->type, -+ &asynchronous); -+ -+#if gcdENABLE_VG -+ if (record->kernel->core == gcvCORE_VG) -+ { -+ if (gcmIS_SUCCESS(status) && (gcvTRUE == asynchronous)) -+ { -+ /* TODO: we maybe need to schedule a event here */ -+ status = gckVIDMEM_Unlock(record->kernel, -+ nodeObject, -+ nodeObject->type, -+ gcvNULL); -+ } -+ -+ gcmkVERIFY_OK(gckVIDMEM_HANDLE_Dereference(record->kernel, -+ ProcessID, -+ handle)); -+ -+ gcmkVERIFY_OK(gckVIDMEM_NODE_Dereference(record->kernel, -+ nodeObject)); -+ } -+ else -+#endif -+ { -+ gcmkVERIFY_OK(gckVIDMEM_HANDLE_Dereference(record->kernel, -+ ProcessID, -+ handle)); -+ -+ if (gcmIS_SUCCESS(status) && (gcvTRUE == asynchronous)) -+ { -+ status = gckEVENT_Unlock(record->kernel->eventObj, -+ gcvKERNEL_PIXEL, -+ nodeObject, -+ nodeObject->type); -+ } -+ else -+ { -+ gcmkVERIFY_OK(gckVIDMEM_NODE_Dereference(record->kernel, -+ nodeObject)); -+ } -+ } -+ -+ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE, -+ "DB: VIDEO_MEMORY_LOCKED 0x%x (status=%d)", -+ record->data, status); -+ break; -+ -+ case gcvDB_CONTEXT: -+ /* TODO: Free the context */ -+ status = gckCOMMAND_Detach(Kernel->command, gcmNAME_TO_PTR(record->data)); -+ gcmRELEASE_NAME(record->data); -+ -+ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE, -+ "DB: CONTEXT 0x%x (status=%d)", -+ record->data, status); -+ break; -+ -+ case gcvDB_MAP_MEMORY: -+ /* Unmap memory. */ -+ status = gckKERNEL_UnmapMemory(Kernel, -+ record->physical, -+ record->bytes, -+ record->data); -+ -+ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE, -+ "DB: MAP MEMORY %d (status=%d)", -+ gcmPTR2INT32(record->data), status); -+ break; -+ -+ case gcvDB_MAP_USER_MEMORY: -+ /* TODO: Unmap user memory. */ -+ status = gckOS_UnmapUserMemory(Kernel->os, -+ Kernel->core, -+ record->physical, -+ record->bytes, -+ gcmNAME_TO_PTR(record->data), -+ 0); -+ gcmRELEASE_NAME(record->data); -+ -+ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE, -+ "DB: MAP USER MEMORY %d (status=%d)", -+ gcmPTR2INT32(record->data), status); -+ break; -+ -+#if gcdANDROID_NATIVE_FENCE_SYNC -+ case gcvDB_SYNC_POINT: -+ /* Free the user signal. */ -+ status = gckOS_DestroySyncPoint(Kernel->os, -+ (gctSYNC_POINT) record->data); -+ -+ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE, -+ "DB: SYNC POINT %d (status=%d)", -+ (gctINT)(gctUINTPTR_T)record->data, status); -+ break; -+#endif -+ -+ case gcvDB_SHBUF: -+ /* Free shared buffer. */ -+ status = gckKERNEL_DestroyShBuffer(Kernel, -+ (gctSHBUF) record->data); -+ -+ gcmkTRACE_ZONE(gcvLEVEL_WARNING, gcvZONE_DATABASE, -+ "DB: SHBUF %u (status=%d)", -+ (gctUINT32)(gctUINTPTR_T) record->data, status); -+ break; -+ -+ default: -+ gcmkTRACE_ZONE(gcvLEVEL_ERROR, gcvZONE_DATABASE, -+ "DB: Correcupted record=0x%08x type=%d", -+ record, record->type); -+ break; -+ } -+ -+ /* Delete the record. */ -+ gcmkONERROR(gckKERNEL_DeleteRecord(Kernel, -+ database, -+ record->type, -+ record->data, -+ gcvNULL)); -+ } -+ -+ } -+ -+ /* Delete the database. */ -+ gcmkONERROR(gckKERNEL_DeleteDatabase(Kernel, database)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** gckKERNEL_QueryProcessDB -+** -+** Query a process database for the current usage of a particular record type. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to a gckKERNEL object. -+** -+** gctUINT32 ProcessID -+** Process ID used to identify the database. -+** -+** gctBOOL LastProcessID -+** gcvTRUE if searching for the last known process ID. gcvFALSE if -+** we need to search for the process ID specified by the ProcessID -+** argument. -+** -+** gceDATABASE_TYPE Type -+** Type of the record to query. -+** -+** OUTPUT: -+** -+** gcuDATABASE_INFO * Info -+** Pointer to a variable that receives the requested information. -+*/ -+gceSTATUS -+gckKERNEL_QueryProcessDB( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 ProcessID, -+ IN gctBOOL LastProcessID, -+ IN gceDATABASE_TYPE Type, -+ OUT gcuDATABASE_INFO * Info -+ ) -+{ -+ gceSTATUS status; -+ gcsDATABASE_PTR database; -+ gcePOOL vidMemPool; -+ -+ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d Type=%d Info=0x%x", -+ Kernel, ProcessID, Type, Info); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ gcmkVERIFY_ARGUMENT(Info != gcvNULL); -+ -+ /* Deocde pool. */ -+ vidMemPool = (Type & gcdDB_VIDEO_MEMORY_POOL_MASK) >> gcdDB_VIDEO_MEMORY_POOL_SHIFT; -+ -+ Type &= gcdDATABASE_TYPE_MASK; -+ -+ /* Find the database. */ -+ if(Type != gcvDB_IDLE) -+ { -+ gcmkONERROR( -+ gckKERNEL_FindDatabase(Kernel, ProcessID, LastProcessID, &database)); -+ -+ gcmkVERIFY_OK(gckOS_AcquireMutex(Kernel->os, database->counterMutex, gcvINFINITE)); -+ -+ /* Get pointer to counters. */ -+ switch (Type) -+ { -+ case gcvDB_VIDEO_MEMORY: -+ if (vidMemPool != gcvPOOL_UNKNOWN) -+ { -+ gckOS_MemCopy(&Info->counters, -+ &database->vidMemPool[vidMemPool], -+ gcmSIZEOF(database->vidMemPool[vidMemPool])); -+ } -+ else -+ { -+ gckOS_MemCopy(&Info->counters, -+ &database->vidMem, -+ gcmSIZEOF(database->vidMem)); -+ } -+ break; -+ -+ case gcvDB_NON_PAGED: -+ gckOS_MemCopy(&Info->counters, -+ &database->nonPaged, -+ gcmSIZEOF(database->vidMem)); -+ break; -+ -+ case gcvDB_CONTIGUOUS: -+ gckOS_MemCopy(&Info->counters, -+ &database->contiguous, -+ gcmSIZEOF(database->vidMem)); -+ break; -+ -+ case gcvDB_MAP_MEMORY: -+ gckOS_MemCopy(&Info->counters, -+ &database->mapMemory, -+ gcmSIZEOF(database->mapMemory)); -+ break; -+ -+ case gcvDB_MAP_USER_MEMORY: -+ gckOS_MemCopy(&Info->counters, -+ &database->mapUserMemory, -+ gcmSIZEOF(database->mapUserMemory)); -+ break; -+ -+ case gcvDB_COMMAND_BUFFER: -+ gckOS_MemCopy(&Info->counters, -+ &database->virtualCommandBuffer, -+ gcmSIZEOF(database->virtualCommandBuffer)); -+ break; -+ -+ default: -+ break; -+ } -+ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, database->counterMutex)); -+ } -+ else -+ { -+ Info->time = Kernel->db->idleTime; -+ Kernel->db->idleTime = 0; -+ } -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckKERNEL_FindHandleDatbase( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 ProcessID, -+ OUT gctPOINTER * HandleDatabase, -+ OUT gctPOINTER * HandleDatabaseMutex -+ ) -+{ -+ gceSTATUS status; -+ gcsDATABASE_PTR database; -+ -+ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d", -+ Kernel, ProcessID); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ -+ /* Find the database. */ -+ gcmkONERROR(gckKERNEL_FindDatabase(Kernel, ProcessID, gcvFALSE, &database)); -+ -+ *HandleDatabase = database->handleDatabase; -+ *HandleDatabaseMutex = database->handleDatabaseMutex; -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+#if gcdPROCESS_ADDRESS_SPACE -+gceSTATUS -+gckKERNEL_GetProcessMMU( -+ IN gckKERNEL Kernel, -+ OUT gckMMU * Mmu -+ ) -+{ -+ gceSTATUS status; -+ gcsDATABASE_PTR database; -+ gctUINT32 processID; -+ -+ gcmkONERROR(gckOS_GetProcessID(&processID)); -+ -+ gcmkONERROR(gckKERNEL_FindDatabase(Kernel, processID, gcvFALSE, &database)); -+ -+ *Mmu = database->mmu; -+ -+ return gcvSTATUS_OK; -+ -+OnError: -+ return status; -+} -+#endif -+ -+gceSTATUS -+gckKERNEL_DumpProcessDB( -+ IN gckKERNEL Kernel -+ ) -+{ -+ gcsDATABASE_PTR database; -+ gctINT i, pid; -+ gctUINT8 name[24]; -+ -+ gcmkHEADER_ARG("Kernel=0x%x", Kernel); -+ -+ /* Acquire the database mutex. */ -+ gcmkVERIFY_OK( -+ gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE)); -+ -+ gcmkPRINT("**************************\n"); -+ gcmkPRINT("*** PROCESS DB DUMP ***\n"); -+ gcmkPRINT("**************************\n"); -+ -+ gcmkPRINT_N(8, "%-8s%s\n", "PID", "NAME"); -+ /* Walk the databases. */ -+ for (i = 0; i < gcmCOUNTOF(Kernel->db->db); ++i) -+ { -+ for (database = Kernel->db->db[i]; -+ database != gcvNULL; -+ database = database->next) -+ { -+ pid = database->processID; -+ -+ gcmkVERIFY_OK(gckOS_ZeroMemory(name, gcmSIZEOF(name))); -+ -+ gcmkVERIFY_OK(gckOS_GetProcessNameByPid(pid, gcmSIZEOF(name), name)); -+ -+ gcmkPRINT_N(8, "%-8d%s\n", pid, name); -+ } -+ } -+ -+ /* Release the database mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+void -+_DumpCounter( -+ IN gcsDATABASE_COUNTERS * Counter, -+ IN gctCONST_STRING Name -+ ) -+{ -+ gcmkPRINT("%s:", Name); -+ gcmkPRINT(" Currently allocated : %10lld", Counter->bytes); -+ gcmkPRINT(" Maximum allocated : %10lld", Counter->maxBytes); -+ gcmkPRINT(" Total allocated : %10lld", Counter->totalBytes); -+} -+ -+gceSTATUS -+gckKERNEL_DumpVidMemUsage( -+ IN gckKERNEL Kernel, -+ IN gctINT32 ProcessID -+ ) -+{ -+ gceSTATUS status; -+ gcsDATABASE_PTR database; -+ gcsDATABASE_COUNTERS * counter; -+ gctUINT32 i = 0; -+ -+ static gctCONST_STRING surfaceTypes[] = { -+ "UNKNOWN", -+ "INDEX", -+ "VERTEX", -+ "TEXTURE", -+ "RENDER_TARGET", -+ "DEPTH", -+ "BITMAP", -+ "TILE_STATUS", -+ "IMAGE", -+ "MASK", -+ "SCISSOR", -+ "HIERARCHICAL_DEPTH", -+ }; -+ -+ gcmkHEADER_ARG("Kernel=0x%x ProcessID=%d", -+ Kernel, ProcessID); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ -+ /* Find the database. */ -+ gcmkONERROR( -+ gckKERNEL_FindDatabase(Kernel, ProcessID, gcvFALSE, &database)); -+ -+ gcmkPRINT("VidMem Usage (Process %d):", ProcessID); -+ -+ /* Get pointer to counters. */ -+ counter = &database->vidMem; -+ -+ _DumpCounter(counter, "Total Video Memory"); -+ -+ for (i = 0; i < gcvSURF_NUM_TYPES; i++) -+ { -+ counter = &database->vidMemType[i]; -+ -+ _DumpCounter(counter, surfaceTypes[i]); -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_debug.c linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_debug.c ---- linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_debug.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_debug.c 2015-11-30 17:56:13.572138258 +0100 -@@ -0,0 +1,2766 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#include "gc_hal_kernel_precomp.h" -+#include -+ -+/******************************************************************************\ -+******************************** Debug Variables ******************************* -+\******************************************************************************/ -+ -+static gceSTATUS _lastError = gcvSTATUS_OK; -+static gctUINT32 _debugLevel = gcvLEVEL_ERROR; -+/* -+_debugZones config value -+Please Reference define in gc_hal_base.h -+*/ -+static gctUINT32 _debugZones = gcvZONE_ALL; -+ -+/******************************************************************************\ -+********************************* Debug Switches ******************************* -+\******************************************************************************/ -+ -+/* -+ gcdBUFFERED_OUTPUT -+ -+ When set to non-zero, all output is collected into a buffer with the -+ specified size. Once the buffer gets full, the debug buffer will be -+ printed to the console. gcdBUFFERED_SIZE determines the size of the buffer. -+*/ -+#define gcdBUFFERED_OUTPUT 0 -+ -+/* -+ gcdBUFFERED_SIZE -+ -+ When set to non-zero, all output is collected into a buffer with the -+ specified size. Once the buffer gets full, the debug buffer will be -+ printed to the console. -+*/ -+#define gcdBUFFERED_SIZE (1024 * 1024 * 2) -+ -+/* -+ gcdDMA_BUFFER_COUNT -+ -+ If greater then zero, the debugger will attempt to find the command buffer -+ where DMA is currently executing and then print this buffer and -+ (gcdDMA_BUFFER_COUNT - 1) buffers before the current one. If set to zero -+ or the current buffer is not found, all buffers are printed. -+*/ -+#define gcdDMA_BUFFER_COUNT 0 -+ -+/* -+ gcdTHREAD_BUFFERS -+ -+ When greater then one, will accumulate messages from the specified number -+ of threads in separate output buffers. -+*/ -+#define gcdTHREAD_BUFFERS 1 -+ -+/* -+ gcdENABLE_OVERFLOW -+ -+ When set to non-zero, and the output buffer gets full, instead of being -+ printed, it will be allowed to overflow removing the oldest messages. -+*/ -+#define gcdENABLE_OVERFLOW 1 -+ -+/* -+ gcdSHOW_LINE_NUMBER -+ -+ When enabledm each print statement will be preceeded with the current -+ line number. -+*/ -+#define gcdSHOW_LINE_NUMBER 0 -+ -+/* -+ gcdSHOW_PROCESS_ID -+ -+ When enabledm each print statement will be preceeded with the current -+ process ID. -+*/ -+#define gcdSHOW_PROCESS_ID 0 -+ -+/* -+ gcdSHOW_THREAD_ID -+ -+ When enabledm each print statement will be preceeded with the current -+ thread ID. -+*/ -+#define gcdSHOW_THREAD_ID 0 -+ -+/* -+ gcdSHOW_TIME -+ -+ When enabled each print statement will be preceeded with the current -+ high-resolution time. -+*/ -+#define gcdSHOW_TIME 0 -+ -+ -+/******************************************************************************\ -+****************************** Miscellaneous Macros **************************** -+\******************************************************************************/ -+ -+#if gcmIS_DEBUG(gcdDEBUG_TRACE) -+# define gcmDBGASSERT(Expression, Format, Value) \ -+ if (!(Expression)) \ -+ { \ -+ _DirectPrint( \ -+ "*** gcmDBGASSERT ***************************\n" \ -+ " function : %s\n" \ -+ " line : %d\n" \ -+ " expression : " #Expression "\n" \ -+ " actual value : " Format "\n", \ -+ __FUNCTION__, __LINE__, Value \ -+ ); \ -+ } -+#else -+# define gcmDBGASSERT(Expression, Format, Value) -+#endif -+ -+#define gcmPTRALIGNMENT(Pointer, Alignemnt) \ -+( \ -+ gcmALIGN(gcmPTR2INT32(Pointer), Alignemnt) - gcmPTR2INT32(Pointer) \ -+) -+ -+#if gcdALIGNBYSIZE -+# define gcmISALIGNED(Offset, Alignment) \ -+ (((Offset) & ((Alignment) - 1)) == 0) -+ -+# define gcmkALIGNPTR(Type, Pointer, Alignment) \ -+ Pointer = (Type) gcmINT2PTR(gcmALIGN(gcmPTR2INT32(Pointer), Alignment)) -+#else -+# define gcmISALIGNED(Offset, Alignment) \ -+ gcvTRUE -+ -+# define gcmkALIGNPTR(Type, Pointer, Alignment) -+#endif -+ -+#define gcmALIGNSIZE(Offset, Size) \ -+ ((Size - Offset) + Size) -+ -+#define gcdHAVEPREFIX \ -+( \ -+ gcdSHOW_TIME \ -+ || gcdSHOW_LINE_NUMBER \ -+ || gcdSHOW_PROCESS_ID \ -+ || gcdSHOW_THREAD_ID \ -+) -+ -+#if gcdHAVEPREFIX -+ -+# define gcdOFFSET 0 -+ -+#if gcdSHOW_TIME -+#if gcmISALIGNED(gcdOFFSET, 8) -+# define gcdTIMESIZE gcmSIZEOF(gctUINT64) -+# elif gcdOFFSET == 4 -+# define gcdTIMESIZE gcmALIGNSIZE(4, gcmSIZEOF(gctUINT64)) -+# else -+# error "Unexpected offset value." -+# endif -+# undef gcdOFFSET -+# define gcdOFFSET 8 -+#if !defined(gcdPREFIX_LEADER) -+# define gcdPREFIX_LEADER gcmSIZEOF(gctUINT64) -+# define gcdTIMEFORMAT "0x%016llX" -+# else -+# define gcdTIMEFORMAT ", 0x%016llX" -+# endif -+# else -+# define gcdTIMESIZE 0 -+# define gcdTIMEFORMAT -+# endif -+ -+#if gcdSHOW_LINE_NUMBER -+#if gcmISALIGNED(gcdOFFSET, 8) -+# define gcdNUMSIZE gcmSIZEOF(gctUINT64) -+# elif gcdOFFSET == 4 -+# define gcdNUMSIZE gcmALIGNSIZE(4, gcmSIZEOF(gctUINT64)) -+# else -+# error "Unexpected offset value." -+# endif -+# undef gcdOFFSET -+# define gcdOFFSET 8 -+#if !defined(gcdPREFIX_LEADER) -+# define gcdPREFIX_LEADER gcmSIZEOF(gctUINT64) -+# define gcdNUMFORMAT "%8llu" -+# else -+# define gcdNUMFORMAT ", %8llu" -+# endif -+# else -+# define gcdNUMSIZE 0 -+# define gcdNUMFORMAT -+# endif -+ -+#if gcdSHOW_PROCESS_ID -+#if gcmISALIGNED(gcdOFFSET, 4) -+# define gcdPIDSIZE gcmSIZEOF(gctUINT32) -+# else -+# error "Unexpected offset value." -+# endif -+# undef gcdOFFSET -+# define gcdOFFSET 4 -+#if !defined(gcdPREFIX_LEADER) -+# define gcdPREFIX_LEADER gcmSIZEOF(gctUINT32) -+# define gcdPIDFORMAT "pid=%5d" -+# else -+# define gcdPIDFORMAT ", pid=%5d" -+# endif -+# else -+# define gcdPIDSIZE 0 -+# define gcdPIDFORMAT -+# endif -+ -+#if gcdSHOW_THREAD_ID -+#if gcmISALIGNED(gcdOFFSET, 4) -+# define gcdTIDSIZE gcmSIZEOF(gctUINT32) -+# else -+# error "Unexpected offset value." -+# endif -+# undef gcdOFFSET -+# define gcdOFFSET 4 -+#if !defined(gcdPREFIX_LEADER) -+# define gcdPREFIX_LEADER gcmSIZEOF(gctUINT32) -+# define gcdTIDFORMAT "tid=%5d" -+# else -+# define gcdTIDFORMAT ", tid=%5d" -+# endif -+# else -+# define gcdTIDSIZE 0 -+# define gcdTIDFORMAT -+# endif -+ -+# define gcdPREFIX_SIZE \ -+ ( \ -+ gcdTIMESIZE \ -+ + gcdNUMSIZE \ -+ + gcdPIDSIZE \ -+ + gcdTIDSIZE \ -+ ) -+ -+ static const char * _prefixFormat = -+ "[" -+ gcdTIMEFORMAT -+ gcdNUMFORMAT -+ gcdPIDFORMAT -+ gcdTIDFORMAT -+ "] "; -+ -+#else -+ -+# define gcdPREFIX_LEADER gcmSIZEOF(gctUINT32) -+# define gcdPREFIX_SIZE 0 -+ -+#endif -+ -+/* Assumed largest variable argument leader size. */ -+#define gcdVARARG_LEADER gcmSIZEOF(gctUINT64) -+ -+/* Alignnments. */ -+#if gcdALIGNBYSIZE -+# define gcdPREFIX_ALIGNMENT gcdPREFIX_LEADER -+# define gcdVARARG_ALIGNMENT gcdVARARG_LEADER -+#else -+# define gcdPREFIX_ALIGNMENT 0 -+# define gcdVARARG_ALIGNMENT 0 -+#endif -+ -+#if gcdBUFFERED_OUTPUT -+# define gcdOUTPUTPREFIX _AppendPrefix -+# define gcdOUTPUTSTRING _AppendString -+# define gcdOUTPUTCOPY _AppendCopy -+# define gcdOUTPUTBUFFER _AppendBuffer -+#else -+# define gcdOUTPUTPREFIX _PrintPrefix -+# define gcdOUTPUTSTRING _PrintString -+# define gcdOUTPUTCOPY _PrintString -+# define gcdOUTPUTBUFFER _PrintBuffer -+#endif -+ -+/******************************************************************************\ -+****************************** Private Structures ****************************** -+\******************************************************************************/ -+ -+typedef enum _gceBUFITEM -+{ -+ gceBUFITEM_NONE, -+ gcvBUFITEM_PREFIX, -+ gcvBUFITEM_STRING, -+ gcvBUFITEM_COPY, -+ gcvBUFITEM_BUFFER -+} -+gceBUFITEM; -+ -+/* Common item head/buffer terminator. */ -+typedef struct _gcsBUFITEM_HEAD * gcsBUFITEM_HEAD_PTR; -+typedef struct _gcsBUFITEM_HEAD -+{ -+ gceBUFITEM type; -+} -+gcsBUFITEM_HEAD; -+ -+/* String prefix (for ex. [ 1,tid=0x019A]) */ -+typedef struct _gcsBUFITEM_PREFIX * gcsBUFITEM_PREFIX_PTR; -+typedef struct _gcsBUFITEM_PREFIX -+{ -+ gceBUFITEM type; -+#if gcdHAVEPREFIX -+ gctPOINTER prefixData; -+#endif -+} -+gcsBUFITEM_PREFIX; -+ -+/* Buffered string. */ -+typedef struct _gcsBUFITEM_STRING * gcsBUFITEM_STRING_PTR; -+typedef struct _gcsBUFITEM_STRING -+{ -+ gceBUFITEM type; -+ gctINT indent; -+ gctCONST_STRING message; -+ gctPOINTER messageData; -+ gctUINT messageDataSize; -+} -+gcsBUFITEM_STRING; -+ -+/* Buffered string (copy of the string is included with the record). */ -+typedef struct _gcsBUFITEM_COPY * gcsBUFITEM_COPY_PTR; -+typedef struct _gcsBUFITEM_COPY -+{ -+ gceBUFITEM type; -+ gctINT indent; -+ gctPOINTER messageData; -+ gctUINT messageDataSize; -+} -+gcsBUFITEM_COPY; -+ -+/* Memory buffer. */ -+typedef struct _gcsBUFITEM_BUFFER * gcsBUFITEM_BUFFER_PTR; -+typedef struct _gcsBUFITEM_BUFFER -+{ -+ gceBUFITEM type; -+ gctINT indent; -+ gceDUMP_BUFFER bufferType; -+ -+#if gcdDMA_BUFFER_COUNT && (gcdTHREAD_BUFFERS == 1) -+ gctUINT32 dmaAddress; -+#endif -+ -+ gctUINT dataSize; -+ gctUINT32 address; -+#if gcdHAVEPREFIX -+ gctPOINTER prefixData; -+#endif -+} -+gcsBUFITEM_BUFFER; -+ -+typedef struct _gcsBUFFERED_OUTPUT * gcsBUFFERED_OUTPUT_PTR; -+typedef struct _gcsBUFFERED_OUTPUT -+{ -+#if gcdTHREAD_BUFFERS > 1 -+ gctUINT32 threadID; -+#endif -+ -+#if gcdSHOW_LINE_NUMBER -+ gctUINT64 lineNumber; -+#endif -+ -+ gctINT indent; -+ -+#if gcdBUFFERED_OUTPUT -+ gctINT start; -+ gctINT index; -+ gctINT count; -+ gctUINT8 buffer[gcdBUFFERED_SIZE]; -+#endif -+ -+ gcsBUFFERED_OUTPUT_PTR prev; -+ gcsBUFFERED_OUTPUT_PTR next; -+} -+gcsBUFFERED_OUTPUT; -+ -+typedef gctUINT (* gcfPRINTSTRING) ( -+ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer, -+ IN gcsBUFITEM_HEAD_PTR Item -+ ); -+ -+typedef gctINT (* gcfGETITEMSIZE) ( -+ IN gcsBUFITEM_HEAD_PTR Item -+ ); -+ -+/******************************************************************************\ -+******************************* Private Variables ****************************** -+\******************************************************************************/ -+ -+static gcsBUFFERED_OUTPUT _outputBuffer[gcdTHREAD_BUFFERS]; -+static gcsBUFFERED_OUTPUT_PTR _outputBufferHead = gcvNULL; -+static gcsBUFFERED_OUTPUT_PTR _outputBufferTail = gcvNULL; -+ -+/******************************************************************************\ -+****************************** Item Size Functions ***************************** -+\******************************************************************************/ -+ -+#if gcdBUFFERED_OUTPUT -+static gctINT -+_GetTerminatorItemSize( -+ IN gcsBUFITEM_HEAD_PTR Item -+ ) -+{ -+ return gcmSIZEOF(gcsBUFITEM_HEAD); -+} -+ -+static gctINT -+_GetPrefixItemSize( -+ IN gcsBUFITEM_HEAD_PTR Item -+ ) -+{ -+#if gcdHAVEPREFIX -+ gcsBUFITEM_PREFIX_PTR item = (gcsBUFITEM_PREFIX_PTR) Item; -+ gctUINT vlen = ((gctUINT8_PTR) item->prefixData) - ((gctUINT8_PTR) item); -+ return vlen + gcdPREFIX_SIZE; -+#else -+ return gcmSIZEOF(gcsBUFITEM_PREFIX); -+#endif -+} -+ -+static gctINT -+_GetStringItemSize( -+ IN gcsBUFITEM_HEAD_PTR Item -+ ) -+{ -+ gcsBUFITEM_STRING_PTR item = (gcsBUFITEM_STRING_PTR) Item; -+ gctUINT vlen = ((gctUINT8_PTR) item->messageData) - ((gctUINT8_PTR) item); -+ return vlen + item->messageDataSize; -+} -+ -+static gctINT -+_GetCopyItemSize( -+ IN gcsBUFITEM_HEAD_PTR Item -+ ) -+{ -+ gcsBUFITEM_COPY_PTR item = (gcsBUFITEM_COPY_PTR) Item; -+ gctUINT vlen = ((gctUINT8_PTR) item->messageData) - ((gctUINT8_PTR) item); -+ return vlen + item->messageDataSize; -+} -+ -+static gctINT -+_GetBufferItemSize( -+ IN gcsBUFITEM_HEAD_PTR Item -+ ) -+{ -+#if gcdHAVEPREFIX -+ gcsBUFITEM_BUFFER_PTR item = (gcsBUFITEM_BUFFER_PTR) Item; -+ gctUINT vlen = ((gctUINT8_PTR) item->prefixData) - ((gctUINT8_PTR) item); -+ return vlen + gcdPREFIX_SIZE + item->dataSize; -+#else -+ gcsBUFITEM_BUFFER_PTR item = (gcsBUFITEM_BUFFER_PTR) Item; -+ return gcmSIZEOF(gcsBUFITEM_BUFFER) + item->dataSize; -+#endif -+} -+ -+static gcfGETITEMSIZE _itemSize[] = -+{ -+ _GetTerminatorItemSize, -+ _GetPrefixItemSize, -+ _GetStringItemSize, -+ _GetCopyItemSize, -+ _GetBufferItemSize -+}; -+#endif -+ -+/******************************************************************************\ -+******************************* Printing Functions ***************************** -+\******************************************************************************/ -+ -+#if gcdDEBUG || gcdBUFFERED_OUTPUT -+static void -+_DirectPrint( -+ gctCONST_STRING Message, -+ ... -+ ) -+{ -+ gctINT len; -+ char buffer[768]; -+ gctARGUMENTS arguments; -+ -+ gcmkARGUMENTS_START(arguments, Message); -+ len = gcmkVSPRINTF(buffer, gcmSIZEOF(buffer), Message, &arguments); -+ gcmkARGUMENTS_END(arguments); -+ -+ buffer[len] = '\0'; -+ gcmkOUTPUT_STRING(buffer); -+} -+#endif -+ -+static int -+_AppendIndent( -+ IN gctINT Indent, -+ IN char * Buffer, -+ IN int BufferSize -+ ) -+{ -+ gctINT i; -+ -+ gctINT len = 0; -+ gctINT indent = Indent % 40; -+ -+ for (i = 0; i < indent; i += 1) -+ { -+ Buffer[len++] = ' '; -+ } -+ -+ if (indent != Indent) -+ { -+ len += gcmkSPRINTF( -+ Buffer + len, BufferSize - len, " <%d> ", Indent -+ ); -+ -+ Buffer[len] = '\0'; -+ } -+ -+ return len; -+} -+ -+#if gcdHAVEPREFIX -+static void -+_PrintPrefix( -+ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer, -+ IN gctPOINTER Data -+ ) -+{ -+ char buffer[768]; -+ gctINT len; -+ -+ /* Format the string. */ -+ len = gcmkVSPRINTF(buffer, gcmSIZEOF(buffer), _prefixFormat, Data); -+ buffer[len] = '\0'; -+ -+ /* Print the string. */ -+ gcmkOUTPUT_STRING(buffer); -+} -+#endif -+ -+static void -+_PrintString( -+ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer, -+ IN gctINT Indent, -+ IN gctCONST_STRING Message, -+ IN gctUINT ArgumentSize, -+ IN gctPOINTER Data -+ ) -+{ -+ char buffer[768]; -+ gctINT len; -+ -+ /* Append the indent string. */ -+ len = _AppendIndent(Indent, buffer, gcmSIZEOF(buffer)); -+ -+ /* Format the string. */ -+ len += gcmkVSPRINTF(buffer + len, gcmSIZEOF(buffer) - len, Message, Data); -+ buffer[len] = '\0'; -+ -+ /* Add end-of-line if missing. */ -+ if (buffer[len - 1] != '\n') -+ { -+ buffer[len++] = '\n'; -+ buffer[len] = '\0'; -+ } -+ -+ /* Print the string. */ -+ gcmkOUTPUT_STRING(buffer); -+} -+ -+static void -+_PrintBuffer( -+ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer, -+ IN gctINT Indent, -+ IN gctPOINTER PrefixData, -+ IN gctPOINTER Data, -+ IN gctUINT Address, -+ IN gctUINT DataSize, -+ IN gceDUMP_BUFFER Type, -+ IN gctUINT32 DmaAddress -+ ) -+{ -+ static gctCONST_STRING _titleString[] = -+ { -+ "CONTEXT BUFFER", -+ "USER COMMAND BUFFER", -+ "KERNEL COMMAND BUFFER", -+ "LINK BUFFER", -+ "WAIT LINK BUFFER", -+ "" -+ }; -+ -+ static const gctINT COLUMN_COUNT = 8; -+ -+ gctUINT i, count, column, address; -+ gctUINT32_PTR data; -+ gctCHAR buffer[768]; -+ gctUINT indent, len; -+ gctBOOL command; -+ -+ /* Append space for the prefix. */ -+#if gcdHAVEPREFIX -+ indent = gcmkVSPRINTF(buffer, gcmSIZEOF(buffer), _prefixFormat, PrefixData); -+ buffer[indent] = '\0'; -+#else -+ indent = 0; -+#endif -+ -+ /* Append the indent string. */ -+ indent += _AppendIndent( -+ Indent, buffer + indent, gcmSIZEOF(buffer) - indent -+ ); -+ -+ switch (Type) -+ { -+ case gceDUMP_BUFFER_CONTEXT: -+ case gceDUMP_BUFFER_USER: -+ case gceDUMP_BUFFER_KERNEL: -+ case gceDUMP_BUFFER_LINK: -+ case gceDUMP_BUFFER_WAITLINK: -+ /* Form and print the title string. */ -+ gcmkSPRINTF2( -+ buffer + indent, gcmSIZEOF(buffer) - indent, -+ "%s%s\n", _titleString[Type], -+ ((DmaAddress >= Address) && (DmaAddress < Address + DataSize)) -+ ? " (CURRENT)" : "" -+ ); -+ -+ gcmkOUTPUT_STRING(buffer); -+ -+ /* Terminate the string. */ -+ buffer[indent] = '\0'; -+ -+ /* This is a command buffer. */ -+ command = gcvTRUE; -+ break; -+ -+ case gceDUMP_BUFFER_FROM_USER: -+ /* This is not a command buffer. */ -+ command = gcvFALSE; -+ -+ /* No title. */ -+ break; -+ -+ default: -+ gcmDBGASSERT(gcvFALSE, "%s", "invalid buffer type"); -+ -+ /* This is not a command buffer. */ -+ command = gcvFALSE; -+ } -+ -+ /* Overwrite the prefix with spaces. */ -+ for (i = 0; i < indent; i += 1) -+ { -+ buffer[i] = ' '; -+ } -+ -+ /* Form and print the opening string. */ -+ if (command) -+ { -+ gcmkSPRINTF2( -+ buffer + indent, gcmSIZEOF(buffer) - indent, -+ "@[kernel.command %08X %08X\n", Address, DataSize -+ ); -+ -+ gcmkOUTPUT_STRING(buffer); -+ -+ /* Terminate the string. */ -+ buffer[indent] = '\0'; -+ } -+ -+ /* Get initial address. */ -+ address = Address; -+ -+ /* Cast the data pointer. */ -+ data = (gctUINT32_PTR) Data; -+ -+ /* Compute the number of double words. */ -+ count = DataSize / gcmSIZEOF(gctUINT32); -+ -+ /* Print the buffer. */ -+ for (i = 0, len = indent, column = 0; i < count; i += 1) -+ { -+ /* Append the address. */ -+ if (column == 0) -+ { -+ len += gcmkSPRINTF( -+ buffer + len, gcmSIZEOF(buffer) - len, "0x%08X:", address -+ ); -+ } -+ -+ /* Append the data value. */ -+ len += gcmkSPRINTF2( -+ buffer + len, gcmSIZEOF(buffer) - len, "%c%08X", -+ (address == DmaAddress)? '>' : ' ', data[i] -+ ); -+ -+ buffer[len] = '\0'; -+ -+ /* Update the address. */ -+ address += gcmSIZEOF(gctUINT32); -+ -+ /* Advance column count. */ -+ column += 1; -+ -+ /* End of line? */ -+ if ((column % COLUMN_COUNT) == 0) -+ { -+ /* Append EOL. */ -+ gcmkSTRCAT(buffer + len, gcmSIZEOF(buffer) - len, "\n"); -+ -+ /* Print the string. */ -+ gcmkOUTPUT_STRING(buffer); -+ -+ /* Reset. */ -+ len = indent; -+ column = 0; -+ } -+ } -+ -+ /* Print the last partial string. */ -+ if (column != 0) -+ { -+ /* Append EOL. */ -+ gcmkSTRCAT(buffer + len, gcmSIZEOF(buffer) - len, "\n"); -+ -+ /* Print the string. */ -+ gcmkOUTPUT_STRING(buffer); -+ } -+ -+ /* Form and print the opening string. */ -+ if (command) -+ { -+ buffer[indent] = '\0'; -+ gcmkSTRCAT(buffer, gcmSIZEOF(buffer), "] -- command\n"); -+ gcmkOUTPUT_STRING(buffer); -+ } -+} -+ -+#if gcdBUFFERED_OUTPUT -+static gctUINT -+_PrintNone( -+ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer, -+ IN gcsBUFITEM_HEAD_PTR Item -+ ) -+{ -+ /* Return the size of the node. */ -+ return gcmSIZEOF(gcsBUFITEM_HEAD); -+} -+ -+static gctUINT -+_PrintPrefixWrapper( -+ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer, -+ IN gcsBUFITEM_HEAD_PTR Item -+ ) -+{ -+#if gcdHAVEPREFIX -+ gcsBUFITEM_PREFIX_PTR item; -+ gctUINT vlen; -+ -+ /* Get access to the data. */ -+ item = (gcsBUFITEM_PREFIX_PTR) Item; -+ -+ /* Print the message. */ -+ _PrintPrefix(OutputBuffer, item->prefixData); -+ -+ /* Compute the size of the variable portion of the structure. */ -+ vlen = ((gctUINT8_PTR) item->prefixData) - ((gctUINT8_PTR) item); -+ -+ /* Return the size of the node. */ -+ return vlen + gcdPREFIX_SIZE; -+#else -+ return gcmSIZEOF(gcsBUFITEM_PREFIX); -+#endif -+} -+ -+static gctUINT -+_PrintStringWrapper( -+ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer, -+ IN gcsBUFITEM_HEAD_PTR Item -+ ) -+{ -+ gcsBUFITEM_STRING_PTR item; -+ gctUINT vlen; -+ -+ /* Get access to the data. */ -+ item = (gcsBUFITEM_STRING_PTR) Item; -+ -+ /* Print the message. */ -+ _PrintString( -+ OutputBuffer, -+ item->indent, item->message, item->messageDataSize, item->messageData -+ ); -+ -+ /* Compute the size of the variable portion of the structure. */ -+ vlen = ((gctUINT8_PTR) item->messageData) - ((gctUINT8_PTR) item); -+ -+ /* Return the size of the node. */ -+ return vlen + item->messageDataSize; -+} -+ -+static gctUINT -+_PrintCopyWrapper( -+ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer, -+ IN gcsBUFITEM_HEAD_PTR Item -+ ) -+{ -+ gcsBUFITEM_COPY_PTR item; -+ gctCONST_STRING message; -+ gctUINT vlen; -+ -+ /* Get access to the data. */ -+ item = (gcsBUFITEM_COPY_PTR) Item; -+ -+ /* Determine the string pointer. */ -+ message = (gctCONST_STRING) (item + 1); -+ -+ /* Print the message. */ -+ _PrintString( -+ OutputBuffer, -+ item->indent, message, item->messageDataSize, item->messageData -+ ); -+ -+ /* Compute the size of the variable portion of the structure. */ -+ vlen = ((gctUINT8_PTR) item->messageData) - ((gctUINT8_PTR) item); -+ -+ /* Return the size of the node. */ -+ return vlen + item->messageDataSize; -+} -+ -+static gctUINT -+_PrintBufferWrapper( -+ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer, -+ IN gcsBUFITEM_HEAD_PTR Item -+ ) -+{ -+#if gcdHAVEPREFIX -+ gctUINT32 dmaAddress; -+ gcsBUFITEM_BUFFER_PTR item; -+ gctPOINTER data; -+ gctUINT vlen; -+ -+ /* Get access to the data. */ -+ item = (gcsBUFITEM_BUFFER_PTR) Item; -+ -+#if gcdDMA_BUFFER_COUNT && (gcdTHREAD_BUFFERS == 1) -+ dmaAddress = item->dmaAddress; -+#else -+ dmaAddress = 0xFFFFFFFF; -+#endif -+ -+ if (dmaAddress != 0) -+ { -+ /* Compute the data address. */ -+ data = ((gctUINT8_PTR) item->prefixData) + gcdPREFIX_SIZE; -+ -+ /* Print buffer. */ -+ _PrintBuffer( -+ OutputBuffer, -+ item->indent, item->prefixData, -+ data, item->address, item->dataSize, -+ item->bufferType, dmaAddress -+ ); -+ } -+ -+ /* Compute the size of the variable portion of the structure. */ -+ vlen = ((gctUINT8_PTR) item->prefixData) - ((gctUINT8_PTR) item); -+ -+ /* Return the size of the node. */ -+ return vlen + gcdPREFIX_SIZE + item->dataSize; -+#else -+ gctUINT32 dmaAddress; -+ gcsBUFITEM_BUFFER_PTR item; -+ -+ /* Get access to the data. */ -+ item = (gcsBUFITEM_BUFFER_PTR) Item; -+ -+#if gcdDMA_BUFFER_COUNT && (gcdTHREAD_BUFFERS == 1) -+ dmaAddress = item->dmaAddress; -+#else -+ dmaAddress = 0xFFFFFFFF; -+#endif -+ -+ if (dmaAddress != 0) -+ { -+ /* Print buffer. */ -+ _PrintBuffer( -+ OutputBuffer, -+ item->indent, gcvNULL, -+ item + 1, item->address, item->dataSize, -+ item->bufferType, dmaAddress -+ ); -+ } -+ -+ /* Return the size of the node. */ -+ return gcmSIZEOF(gcsBUFITEM_BUFFER) + item->dataSize; -+#endif -+} -+ -+static gcfPRINTSTRING _printArray[] = -+{ -+ _PrintNone, -+ _PrintPrefixWrapper, -+ _PrintStringWrapper, -+ _PrintCopyWrapper, -+ _PrintBufferWrapper -+}; -+#endif -+ -+/******************************************************************************\ -+******************************* Private Functions ****************************** -+\******************************************************************************/ -+ -+#if gcdBUFFERED_OUTPUT -+ -+#if gcdDMA_BUFFER_COUNT && (gcdTHREAD_BUFFERS == 1) -+static gcsBUFITEM_BUFFER_PTR -+_FindCurrentDMABuffer( -+ gctUINT32 DmaAddress -+ ) -+{ -+ gctINT i, skip; -+ gcsBUFITEM_HEAD_PTR item; -+ gcsBUFITEM_BUFFER_PTR dmaCurrent; -+ -+ /* Reset the current buffer. */ -+ dmaCurrent = gcvNULL; -+ -+ /* Get the first stored item. */ -+ item = (gcsBUFITEM_HEAD_PTR) &_outputBufferHead->buffer[_outputBufferHead->start]; -+ -+ /* Run through all items. */ -+ for (i = 0; i < _outputBufferHead->count; i += 1) -+ { -+ /* Buffer item? */ -+ if (item->type == gcvBUFITEM_BUFFER) -+ { -+ gcsBUFITEM_BUFFER_PTR buffer = (gcsBUFITEM_BUFFER_PTR) item; -+ -+ if ((DmaAddress >= buffer->address) && -+ (DmaAddress < buffer->address + buffer->dataSize)) -+ { -+ dmaCurrent = buffer; -+ } -+ } -+ -+ /* Get the item size and skip it. */ -+ skip = (* _itemSize[item->type]) (item); -+ item = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + skip); -+ -+ /* End of the buffer? Wrap around. */ -+ if (item->type == gceBUFITEM_NONE) -+ { -+ item = (gcsBUFITEM_HEAD_PTR) _outputBufferHead->buffer; -+ } -+ } -+ -+ /* Return result. */ -+ return dmaCurrent; -+} -+ -+static void -+_EnableAllDMABuffers( -+ void -+ ) -+{ -+ gctINT i, skip; -+ gcsBUFITEM_HEAD_PTR item; -+ -+ /* Get the first stored item. */ -+ item = (gcsBUFITEM_HEAD_PTR) &_outputBufferHead->buffer[_outputBufferHead->start]; -+ -+ /* Run through all items. */ -+ for (i = 0; i < _outputBufferHead->count; i += 1) -+ { -+ /* Buffer item? */ -+ if (item->type == gcvBUFITEM_BUFFER) -+ { -+ gcsBUFITEM_BUFFER_PTR buffer = (gcsBUFITEM_BUFFER_PTR) item; -+ -+ /* Enable the buffer. */ -+ buffer->dmaAddress = ~0U; -+ } -+ -+ /* Get the item size and skip it. */ -+ skip = (* _itemSize[item->type]) (item); -+ item = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + skip); -+ -+ /* End of the buffer? Wrap around. */ -+ if (item->type == gceBUFITEM_NONE) -+ { -+ item = (gcsBUFITEM_HEAD_PTR) _outputBufferHead->buffer; -+ } -+ } -+} -+ -+static void -+_EnableDMABuffers( -+ gctUINT32 DmaAddress, -+ gcsBUFITEM_BUFFER_PTR CurrentDMABuffer -+ ) -+{ -+ gctINT i, skip, index; -+ gcsBUFITEM_HEAD_PTR item; -+ gcsBUFITEM_BUFFER_PTR buffers[gcdDMA_BUFFER_COUNT]; -+ -+ /* Reset buffer pointers. */ -+ gckOS_ZeroMemory(buffers, gcmSIZEOF(buffers)); -+ -+ /* Set the current buffer index. */ -+ index = -1; -+ -+ /* Get the first stored item. */ -+ item = (gcsBUFITEM_HEAD_PTR) &_outputBufferHead->buffer[_outputBufferHead->start]; -+ -+ /* Run through all items until the current DMA buffer is found. */ -+ for (i = 0; i < _outputBufferHead->count; i += 1) -+ { -+ /* Buffer item? */ -+ if (item->type == gcvBUFITEM_BUFFER) -+ { -+ /* Advance the index. */ -+ index = (index + 1) % gcdDMA_BUFFER_COUNT; -+ -+ /* Add to the buffer array. */ -+ buffers[index] = (gcsBUFITEM_BUFFER_PTR) item; -+ -+ /* Stop if this is the current DMA buffer. */ -+ if ((gcsBUFITEM_BUFFER_PTR) item == CurrentDMABuffer) -+ { -+ break; -+ } -+ } -+ -+ /* Get the item size and skip it. */ -+ skip = (* _itemSize[item->type]) (item); -+ item = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + skip); -+ -+ /* End of the buffer? Wrap around. */ -+ if (item->type == gceBUFITEM_NONE) -+ { -+ item = (gcsBUFITEM_HEAD_PTR) _outputBufferHead->buffer; -+ } -+ } -+ -+ /* Enable the found buffers. */ -+ gcmDBGASSERT(index != -1, "%d", index); -+ -+ for (i = 0; i < gcdDMA_BUFFER_COUNT; i += 1) -+ { -+ if (buffers[index] == gcvNULL) -+ { -+ break; -+ } -+ -+ buffers[index]->dmaAddress = DmaAddress; -+ -+ index -= 1; -+ -+ if (index == -1) -+ { -+ index = gcdDMA_BUFFER_COUNT - 1; -+ } -+ } -+} -+#endif -+ -+static void -+_Flush( -+ gctUINT32 DmaAddress -+ ) -+{ -+ gctINT i, skip; -+ gcsBUFITEM_HEAD_PTR item; -+ -+ gcsBUFFERED_OUTPUT_PTR outputBuffer = _outputBufferHead; -+ -+#if gcdDMA_BUFFER_COUNT && (gcdTHREAD_BUFFERS == 1) -+ if ((outputBuffer != gcvNULL) && (outputBuffer->count != 0)) -+ { -+ /* Find the current DMA buffer. */ -+ gcsBUFITEM_BUFFER_PTR dmaCurrent = _FindCurrentDMABuffer(DmaAddress); -+ -+ /* Was the current buffer found? */ -+ if (dmaCurrent == gcvNULL) -+ { -+ /* No, print all buffers. */ -+ _EnableAllDMABuffers(); -+ } -+ else -+ { -+ /* Yes, enable only specified number of buffers. */ -+ _EnableDMABuffers(DmaAddress, dmaCurrent); -+ } -+ } -+#endif -+ -+ while (outputBuffer != gcvNULL) -+ { -+ if (outputBuffer->count != 0) -+ { -+ _DirectPrint("********************************************************************************\n"); -+ _DirectPrint("FLUSHING DEBUG OUTPUT BUFFER (%d elements).\n", outputBuffer->count); -+ _DirectPrint("********************************************************************************\n"); -+ -+ item = (gcsBUFITEM_HEAD_PTR) &outputBuffer->buffer[outputBuffer->start]; -+ -+ for (i = 0; i < outputBuffer->count; i += 1) -+ { -+ skip = (* _printArray[item->type]) (outputBuffer, item); -+ -+ item = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + skip); -+ -+ if (item->type == gceBUFITEM_NONE) -+ { -+ item = (gcsBUFITEM_HEAD_PTR) outputBuffer->buffer; -+ } -+ } -+ -+ outputBuffer->start = 0; -+ outputBuffer->index = 0; -+ outputBuffer->count = 0; -+ } -+ -+ outputBuffer = outputBuffer->next; -+ } -+} -+ -+static gcsBUFITEM_HEAD_PTR -+_AllocateItem( -+ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer, -+ IN gctINT Size -+ ) -+{ -+ gctINT skip; -+ gcsBUFITEM_HEAD_PTR item, next; -+ -+#if gcdENABLE_OVERFLOW -+ if ( -+ (OutputBuffer->index + Size >= gcdBUFFERED_SIZE - gcmSIZEOF(gcsBUFITEM_HEAD)) -+ || -+ ( -+ (OutputBuffer->index < OutputBuffer->start) && -+ (OutputBuffer->index + Size >= OutputBuffer->start) -+ ) -+ ) -+ { -+ if (OutputBuffer->index + Size >= gcdBUFFERED_SIZE - gcmSIZEOF(gcsBUFITEM_HEAD)) -+ { -+ if (OutputBuffer->index < OutputBuffer->start) -+ { -+ item = (gcsBUFITEM_HEAD_PTR) &OutputBuffer->buffer[OutputBuffer->start]; -+ -+ while (item->type != gceBUFITEM_NONE) -+ { -+ skip = (* _itemSize[item->type]) (item); -+ -+ OutputBuffer->start += skip; -+ OutputBuffer->count -= 1; -+ -+ item->type = gceBUFITEM_NONE; -+ item = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + skip); -+ } -+ -+ OutputBuffer->start = 0; -+ } -+ -+ OutputBuffer->index = 0; -+ } -+ -+ item = (gcsBUFITEM_HEAD_PTR) &OutputBuffer->buffer[OutputBuffer->start]; -+ -+ while (OutputBuffer->start - OutputBuffer->index <= Size) -+ { -+ skip = (* _itemSize[item->type]) (item); -+ -+ OutputBuffer->start += skip; -+ OutputBuffer->count -= 1; -+ -+ item->type = gceBUFITEM_NONE; -+ item = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + skip); -+ -+ if (item->type == gceBUFITEM_NONE) -+ { -+ OutputBuffer->start = 0; -+ break; -+ } -+ } -+ } -+#else -+ if (OutputBuffer->index + Size > gcdBUFFERED_SIZE - gcmSIZEOF(gcsBUFITEM_HEAD)) -+ { -+ _DirectPrint("\nMessage buffer full; forcing message flush.\n\n"); -+ _Flush(~0U); -+ } -+#endif -+ -+ item = (gcsBUFITEM_HEAD_PTR) &OutputBuffer->buffer[OutputBuffer->index]; -+ -+ OutputBuffer->index += Size; -+ OutputBuffer->count += 1; -+ -+ next = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) item + Size); -+ next->type = gceBUFITEM_NONE; -+ -+ return item; -+} -+ -+#if gcdALIGNBYSIZE -+static void -+_FreeExtraSpace( -+ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer, -+ IN gctPOINTER Item, -+ IN gctINT ItemSize, -+ IN gctINT FreeSize -+ ) -+{ -+ gcsBUFITEM_HEAD_PTR next; -+ -+ OutputBuffer->index -= FreeSize; -+ -+ next = (gcsBUFITEM_HEAD_PTR) ((gctUINT8_PTR) Item + ItemSize); -+ next->type = gceBUFITEM_NONE; -+} -+#endif -+ -+#if gcdHAVEPREFIX -+static void -+_AppendPrefix( -+ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer, -+ IN gctPOINTER Data -+ ) -+{ -+ gctUINT8_PTR prefixData; -+ gcsBUFITEM_PREFIX_PTR item; -+ gctINT allocSize; -+ -+#if gcdALIGNBYSIZE -+ gctUINT alignment; -+ gctINT size, freeSize; -+#endif -+ -+ gcmDBGASSERT(Data != gcvNULL, "%p", Data); -+ -+ /* Determine the maximum item size. */ -+ allocSize -+ = gcmSIZEOF(gcsBUFITEM_PREFIX) -+ + gcdPREFIX_SIZE -+ + gcdPREFIX_ALIGNMENT; -+ -+ /* Allocate prefix item. */ -+ item = (gcsBUFITEM_PREFIX_PTR) _AllocateItem(OutputBuffer, allocSize); -+ -+ /* Compute the initial prefix data pointer. */ -+ prefixData = (gctUINT8_PTR) (item + 1); -+ -+ /* Align the data pointer as necessary. */ -+#if gcdALIGNBYSIZE -+ alignment = gcmPTRALIGNMENT(prefixData, gcdPREFIX_ALIGNMENT); -+ prefixData += alignment; -+#endif -+ -+ /* Set item data. */ -+ item->type = gcvBUFITEM_PREFIX; -+ item->prefixData = prefixData; -+ -+ /* Copy argument value. */ -+ memcpy(prefixData, Data, gcdPREFIX_SIZE); -+ -+#if gcdALIGNBYSIZE -+ /* Compute the actual node size. */ -+ size = gcmSIZEOF(gcsBUFITEM_PREFIX) + gcdPREFIX_SIZE + alignment; -+ -+ /* Free extra memory if any. */ -+ freeSize = allocSize - size; -+ if (freeSize != 0) -+ { -+ _FreeExtraSpace(OutputBuffer, item, size, freeSize); -+ } -+#endif -+} -+#endif -+ -+static void -+_AppendString( -+ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer, -+ IN gctINT Indent, -+ IN gctCONST_STRING Message, -+ IN gctUINT ArgumentSize, -+ IN gctPOINTER Data -+ ) -+{ -+ gctUINT8_PTR messageData; -+ gcsBUFITEM_STRING_PTR item; -+ gctINT allocSize; -+ -+#if gcdALIGNBYSIZE -+ gctUINT alignment; -+ gctINT size, freeSize; -+#endif -+ -+ /* Determine the maximum item size. */ -+ allocSize -+ = gcmSIZEOF(gcsBUFITEM_STRING) -+ + ArgumentSize -+ + gcdVARARG_ALIGNMENT; -+ -+ /* Allocate prefix item. */ -+ item = (gcsBUFITEM_STRING_PTR) _AllocateItem(OutputBuffer, allocSize); -+ -+ /* Compute the initial message data pointer. */ -+ messageData = (gctUINT8_PTR) (item + 1); -+ -+ /* Align the data pointer as necessary. */ -+#if gcdALIGNBYSIZE -+ alignment = gcmPTRALIGNMENT(messageData, gcdVARARG_ALIGNMENT); -+ messageData += alignment; -+#endif -+ -+ /* Set item data. */ -+ item->type = gcvBUFITEM_STRING; -+ item->indent = Indent; -+ item->message = Message; -+ item->messageData = messageData; -+ item->messageDataSize = ArgumentSize; -+ -+ /* Copy argument value. */ -+ if (ArgumentSize != 0) -+ { -+ memcpy(messageData, Data, ArgumentSize); -+ } -+ -+#if gcdALIGNBYSIZE -+ /* Compute the actual node size. */ -+ size = gcmSIZEOF(gcsBUFITEM_STRING) + ArgumentSize + alignment; -+ -+ /* Free extra memory if any. */ -+ freeSize = allocSize - size; -+ if (freeSize != 0) -+ { -+ _FreeExtraSpace(OutputBuffer, item, size, freeSize); -+ } -+#endif -+} -+ -+static void -+_AppendCopy( -+ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer, -+ IN gctINT Indent, -+ IN gctCONST_STRING Message, -+ IN gctUINT ArgumentSize, -+ IN gctPOINTER Data -+ ) -+{ -+ gctUINT8_PTR messageData; -+ gcsBUFITEM_COPY_PTR item; -+ gctINT allocSize; -+ gctINT messageLength; -+ gctCONST_STRING message; -+ -+#if gcdALIGNBYSIZE -+ gctUINT alignment; -+ gctINT size, freeSize; -+#endif -+ -+ /* Get the length of the string. */ -+ messageLength = strlen(Message) + 1; -+ -+ /* Determine the maximum item size. */ -+ allocSize -+ = gcmSIZEOF(gcsBUFITEM_COPY) -+ + messageLength -+ + ArgumentSize -+ + gcdVARARG_ALIGNMENT; -+ -+ /* Allocate prefix item. */ -+ item = (gcsBUFITEM_COPY_PTR) _AllocateItem(OutputBuffer, allocSize); -+ -+ /* Determine the message placement. */ -+ message = (gctCONST_STRING) (item + 1); -+ -+ /* Compute the initial message data pointer. */ -+ messageData = (gctUINT8_PTR) message + messageLength; -+ -+ /* Align the data pointer as necessary. */ -+#if gcdALIGNBYSIZE -+ if (ArgumentSize == 0) -+ { -+ alignment = 0; -+ } -+ else -+ { -+ alignment = gcmPTRALIGNMENT(messageData, gcdVARARG_ALIGNMENT); -+ messageData += alignment; -+ } -+#endif -+ -+ /* Set item data. */ -+ item->type = gcvBUFITEM_COPY; -+ item->indent = Indent; -+ item->messageData = messageData; -+ item->messageDataSize = ArgumentSize; -+ -+ /* Copy the message. */ -+ memcpy((gctPOINTER) message, Message, messageLength); -+ -+ /* Copy argument value. */ -+ if (ArgumentSize != 0) -+ { -+ memcpy(messageData, Data, ArgumentSize); -+ } -+ -+#if gcdALIGNBYSIZE -+ /* Compute the actual node size. */ -+ size -+ = gcmSIZEOF(gcsBUFITEM_COPY) -+ + messageLength -+ + ArgumentSize -+ + alignment; -+ -+ /* Free extra memory if any. */ -+ freeSize = allocSize - size; -+ if (freeSize != 0) -+ { -+ _FreeExtraSpace(OutputBuffer, item, size, freeSize); -+ } -+#endif -+} -+ -+static void -+_AppendBuffer( -+ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer, -+ IN gctINT Indent, -+ IN gctPOINTER PrefixData, -+ IN gctPOINTER Data, -+ IN gctUINT Address, -+ IN gctUINT DataSize, -+ IN gceDUMP_BUFFER Type, -+ IN gctUINT32 DmaAddress -+ ) -+{ -+#if gcdHAVEPREFIX -+ gctUINT8_PTR prefixData; -+ gcsBUFITEM_BUFFER_PTR item; -+ gctINT allocSize; -+ gctPOINTER data; -+ -+#if gcdALIGNBYSIZE -+ gctUINT alignment; -+ gctINT size, freeSize; -+#endif -+ -+ gcmDBGASSERT(DataSize != 0, "%d", DataSize); -+ gcmDBGASSERT(Data != gcvNULL, "%p", Data); -+ -+ /* Determine the maximum item size. */ -+ allocSize -+ = gcmSIZEOF(gcsBUFITEM_BUFFER) -+ + gcdPREFIX_SIZE -+ + gcdPREFIX_ALIGNMENT -+ + DataSize; -+ -+ /* Allocate prefix item. */ -+ item = (gcsBUFITEM_BUFFER_PTR) _AllocateItem(OutputBuffer, allocSize); -+ -+ /* Compute the initial prefix data pointer. */ -+ prefixData = (gctUINT8_PTR) (item + 1); -+ -+#if gcdALIGNBYSIZE -+ /* Align the data pointer as necessary. */ -+ alignment = gcmPTRALIGNMENT(prefixData, gcdPREFIX_ALIGNMENT); -+ prefixData += alignment; -+#endif -+ -+ /* Set item data. */ -+ item->type = gcvBUFITEM_BUFFER; -+ item->indent = Indent; -+ item->bufferType = Type; -+ item->dataSize = DataSize; -+ item->address = Address; -+ item->prefixData = prefixData; -+ -+#if gcdDMA_BUFFER_COUNT && (gcdTHREAD_BUFFERS == 1) -+ item->dmaAddress = DmaAddress; -+#endif -+ -+ /* Copy prefix data. */ -+ memcpy(prefixData, PrefixData, gcdPREFIX_SIZE); -+ -+ /* Compute the data pointer. */ -+ data = prefixData + gcdPREFIX_SIZE; -+ -+ /* Copy argument value. */ -+ memcpy(data, Data, DataSize); -+ -+#if gcdALIGNBYSIZE -+ /* Compute the actual node size. */ -+ size -+ = gcmSIZEOF(gcsBUFITEM_BUFFER) -+ + gcdPREFIX_SIZE -+ + alignment -+ + DataSize; -+ -+ /* Free extra memory if any. */ -+ freeSize = allocSize - size; -+ if (freeSize != 0) -+ { -+ _FreeExtraSpace(OutputBuffer, item, size, freeSize); -+ } -+#endif -+#else -+ gcsBUFITEM_BUFFER_PTR item; -+ gctINT size; -+ -+ gcmDBGASSERT(DataSize != 0, "%d", DataSize); -+ gcmDBGASSERT(Data != gcvNULL, "%p", Data); -+ -+ /* Determine the maximum item size. */ -+ size = gcmSIZEOF(gcsBUFITEM_BUFFER) + DataSize; -+ -+ /* Allocate prefix item. */ -+ item = (gcsBUFITEM_BUFFER_PTR) _AllocateItem(OutputBuffer, size); -+ -+ /* Set item data. */ -+ item->type = gcvBUFITEM_BUFFER; -+ item->indent = Indent; -+ item->dataSize = DataSize; -+ item->address = Address; -+ -+ /* Copy argument value. */ -+ memcpy(item + 1, Data, DataSize); -+#endif -+} -+#endif -+ -+static gcmINLINE void -+_InitBuffers( -+ void -+ ) -+{ -+ int i; -+ -+ if (_outputBufferHead == gcvNULL) -+ { -+ for (i = 0; i < gcdTHREAD_BUFFERS; i += 1) -+ { -+ if (_outputBufferTail == gcvNULL) -+ { -+ _outputBufferHead = &_outputBuffer[i]; -+ } -+ else -+ { -+ _outputBufferTail->next = &_outputBuffer[i]; -+ } -+ -+#if gcdTHREAD_BUFFERS > 1 -+ _outputBuffer[i].threadID = ~0U; -+#endif -+ -+ _outputBuffer[i].prev = _outputBufferTail; -+ _outputBuffer[i].next = gcvNULL; -+ -+ _outputBufferTail = &_outputBuffer[i]; -+ } -+ } -+} -+ -+static gcmINLINE gcsBUFFERED_OUTPUT_PTR -+_GetOutputBuffer( -+ void -+ ) -+{ -+ gcsBUFFERED_OUTPUT_PTR outputBuffer; -+ -+#if gcdTHREAD_BUFFERS > 1 -+ /* Get the current thread ID. */ -+ gctUINT32 ThreadID = gcmkGETTHREADID(); -+ -+ /* Locate the output buffer for the thread. */ -+ outputBuffer = _outputBufferHead; -+ -+ while (outputBuffer != gcvNULL) -+ { -+ if (outputBuffer->threadID == ThreadID) -+ { -+ break; -+ } -+ -+ outputBuffer = outputBuffer->next; -+ } -+ -+ /* No matching buffer found? */ -+ if (outputBuffer == gcvNULL) -+ { -+ /* Get the tail for the buffer. */ -+ outputBuffer = _outputBufferTail; -+ -+ /* Move it to the head. */ -+ _outputBufferTail = _outputBufferTail->prev; -+ _outputBufferTail->next = gcvNULL; -+ -+ outputBuffer->prev = gcvNULL; -+ outputBuffer->next = _outputBufferHead; -+ -+ _outputBufferHead->prev = outputBuffer; -+ _outputBufferHead = outputBuffer; -+ -+ /* Reset the buffer. */ -+ outputBuffer->threadID = ThreadID; -+#if gcdBUFFERED_OUTPUT -+ outputBuffer->start = 0; -+ outputBuffer->index = 0; -+ outputBuffer->count = 0; -+#endif -+#if gcdSHOW_LINE_NUMBER -+ outputBuffer->lineNumber = 0; -+#endif -+ } -+#else -+ outputBuffer = _outputBufferHead; -+#endif -+ -+ return outputBuffer; -+} -+ -+static gcmINLINE int _GetArgumentSize( -+ IN gctCONST_STRING Message -+ ) -+{ -+ int i, count; -+ -+ gcmDBGASSERT(Message != gcvNULL, "%p", Message); -+ -+ for (i = 0, count = 0; Message[i]; i += 1) -+ { -+ if (Message[i] == '%') -+ { -+ count += 1; -+ } -+ } -+ -+ return count * gcmSIZEOF(gctUINT32); -+} -+ -+#if gcdHAVEPREFIX -+static void -+_InitPrefixData( -+ IN gcsBUFFERED_OUTPUT_PTR OutputBuffer, -+ IN gctPOINTER Data -+ ) -+{ -+ gctUINT8_PTR data = (gctUINT8_PTR) Data; -+ -+#if gcdSHOW_TIME -+ { -+ gctUINT64 time; -+ gckOS_GetProfileTick(&time); -+ gcmkALIGNPTR(gctUINT8_PTR, data, gcmSIZEOF(gctUINT64)); -+ * ((gctUINT64_PTR) data) = time; -+ data += gcmSIZEOF(gctUINT64); -+ } -+#endif -+ -+#if gcdSHOW_LINE_NUMBER -+ { -+ gcmkALIGNPTR(gctUINT8_PTR, data, gcmSIZEOF(gctUINT64)); -+ * ((gctUINT64_PTR) data) = OutputBuffer->lineNumber; -+ data += gcmSIZEOF(gctUINT64); -+ } -+#endif -+ -+#if gcdSHOW_PROCESS_ID -+ { -+ gcmkALIGNPTR(gctUINT8_PTR, data, gcmSIZEOF(gctUINT32)); -+ * ((gctUINT32_PTR) data) = gcmkGETPROCESSID(); -+ data += gcmSIZEOF(gctUINT32); -+ } -+#endif -+ -+#if gcdSHOW_THREAD_ID -+ { -+ gcmkALIGNPTR(gctUINT8_PTR, data, gcmSIZEOF(gctUINT32)); -+ * ((gctUINT32_PTR) data) = gcmkGETTHREADID(); -+ } -+#endif -+} -+#endif -+ -+static void -+_Print( -+ IN gctUINT ArgumentSize, -+ IN gctBOOL CopyMessage, -+ IN gctCONST_STRING Message, -+ IN gctARGUMENTS * Arguments -+ ) -+{ -+ gcsBUFFERED_OUTPUT_PTR outputBuffer; -+ gcmkDECLARE_LOCK(lockHandle); -+ -+ gcmkLOCKSECTION(lockHandle); -+ -+ /* Initialize output buffer list. */ -+ _InitBuffers(); -+ -+ /* Locate the proper output buffer. */ -+ outputBuffer = _GetOutputBuffer(); -+ -+ /* Update the line number. */ -+#if gcdSHOW_LINE_NUMBER -+ outputBuffer->lineNumber += 1; -+#endif -+ -+ /* Print prefix. */ -+#if gcdHAVEPREFIX -+ { -+ gctUINT8_PTR alignedPrefixData; -+ gctUINT8 prefixData[gcdPREFIX_SIZE + gcdPREFIX_ALIGNMENT]; -+ -+ /* Compute aligned pointer. */ -+ alignedPrefixData = prefixData; -+ gcmkALIGNPTR(gctUINT8_PTR, alignedPrefixData, gcdPREFIX_ALIGNMENT); -+ -+ /* Initialize the prefix data. */ -+ _InitPrefixData(outputBuffer, alignedPrefixData); -+ -+ /* Print the prefix. */ -+ gcdOUTPUTPREFIX(outputBuffer, alignedPrefixData); -+ } -+#endif -+ -+ /* Form the indent string. */ -+ if (strncmp(Message, "--", 2) == 0) -+ { -+ outputBuffer->indent -= 2; -+ } -+ -+ /* Print the message. */ -+ if (CopyMessage) -+ { -+ gcdOUTPUTCOPY( -+ outputBuffer, outputBuffer->indent, -+ Message, ArgumentSize, (gctPOINTER) Arguments -+ ); -+ } -+ else -+ { -+ gcdOUTPUTSTRING( -+ outputBuffer, outputBuffer->indent, -+ Message, ArgumentSize, ((gctPOINTER) Arguments) -+ ); -+ } -+ -+ /* Check increasing indent. */ -+ if (strncmp(Message, "++", 2) == 0) -+ { -+ outputBuffer->indent += 2; -+ } -+ -+ gcmkUNLOCKSECTION(lockHandle); -+} -+ -+ -+/******************************************************************************\ -+********************************* Debug Macros ********************************* -+\******************************************************************************/ -+ -+#define gcmDEBUGPRINT(ArgumentSize, CopyMessage, Message) \ -+{ \ -+ gctARGUMENTS __arguments__; \ -+ gcmkARGUMENTS_START(__arguments__, Message); \ -+ _Print(ArgumentSize, CopyMessage, Message, &__arguments__); \ -+ gcmkARGUMENTS_END(__arguments__); \ -+} -+ -+ -+/******************************************************************************\ -+********************************** Debug Code ********************************** -+\******************************************************************************/ -+ -+/******************************************************************************* -+** -+** gckOS_Print -+** -+** Send a message to the debugger. -+** -+** INPUT: -+** -+** gctCONST_STRING Message -+** Pointer to message. -+** -+** ... -+** Optional arguments. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+ -+void -+gckOS_Print( -+ IN gctCONST_STRING Message, -+ ... -+ ) -+{ -+ gcmDEBUGPRINT(_GetArgumentSize(Message), gcvFALSE, Message); -+} -+ -+/******************************************************************************* -+** -+** gckOS_PrintN -+** -+** Send a message to the debugger. -+** -+** INPUT: -+** -+** gctUINT ArgumentSize -+** The size of the optional arguments in bytes. -+** -+** gctCONST_STRING Message -+** Pointer to message. -+** -+** ... -+** Optional arguments. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+ -+void -+gckOS_PrintN( -+ IN gctUINT ArgumentSize, -+ IN gctCONST_STRING Message, -+ ... -+ ) -+{ -+ gcmDEBUGPRINT(ArgumentSize, gcvFALSE, Message); -+} -+ -+/******************************************************************************* -+** -+** gckOS_CopyPrint -+** -+** Send a message to the debugger. If in buffered output mode, the entire -+** message will be copied into the buffer instead of using the pointer to -+** the string. -+** -+** INPUT: -+** -+** gctCONST_STRING Message -+** Pointer to message. -+** -+** ... -+** Optional arguments. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+ -+void -+gckOS_CopyPrint( -+ IN gctCONST_STRING Message, -+ ... -+ ) -+{ -+ gcmDEBUGPRINT(_GetArgumentSize(Message), gcvTRUE, Message); -+} -+ -+/******************************************************************************* -+** -+** gckOS_DumpBuffer -+** -+** Print the contents of the specified buffer. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to gckOS object. -+** -+** gctPOINTER Buffer -+** Pointer to the buffer to print. -+** -+** gctUINT Size -+** Size of the buffer. -+** -+** gceDUMP_BUFFER Type -+** Buffer type. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+ -+void -+gckOS_DumpBuffer( -+ IN gckOS Os, -+ IN gctPOINTER Buffer, -+ IN gctUINT Size, -+ IN gceDUMP_BUFFER Type, -+ IN gctBOOL CopyMessage -+ ) -+{ -+ gctUINT32 address = 0; -+ gcsBUFFERED_OUTPUT_PTR outputBuffer = gcvNULL; -+ static gctBOOL userLocked; -+ gctCHAR *buffer = (gctCHAR*)Buffer; -+ -+ gcmkDECLARE_LOCK(lockHandle); -+ -+ /* Request lock when not coming from user, -+ or coming from user and not yet locked -+ and message is starting with @[. */ -+ if (Type == gceDUMP_BUFFER_FROM_USER) -+ { -+ if ((Size > 2) -+ && (buffer[0] == '@') -+ && (buffer[1] == '[')) -+ { -+ /* Beginning of a user dump. */ -+ gcmkLOCKSECTION(lockHandle); -+ userLocked = gcvTRUE; -+ } -+ /* Else, let it pass through. */ -+ } -+ else -+ { -+ gcmkLOCKSECTION(lockHandle); -+ userLocked = gcvFALSE; -+ } -+ -+ if (Buffer != gcvNULL) -+ { -+ /* Initialize output buffer list. */ -+ _InitBuffers(); -+ -+ /* Locate the proper output buffer. */ -+ outputBuffer = _GetOutputBuffer(); -+ -+ /* Update the line number. */ -+#if gcdSHOW_LINE_NUMBER -+ outputBuffer->lineNumber += 1; -+#endif -+ -+ /* Get the physical address of the buffer. */ -+ if (Type != gceDUMP_BUFFER_FROM_USER) -+ { -+ gcmkVERIFY_OK(gckOS_GetPhysicalAddress(Os, Buffer, &address)); -+ } -+ else -+ { -+ address = 0; -+ } -+ -+#if gcdHAVEPREFIX -+ { -+ gctUINT8_PTR alignedPrefixData; -+ gctUINT8 prefixData[gcdPREFIX_SIZE + gcdPREFIX_ALIGNMENT]; -+ -+ /* Compute aligned pointer. */ -+ alignedPrefixData = prefixData; -+ gcmkALIGNPTR(gctUINT8_PTR, alignedPrefixData, gcdPREFIX_ALIGNMENT); -+ -+ /* Initialize the prefix data. */ -+ _InitPrefixData(outputBuffer, alignedPrefixData); -+ -+ /* Print/schedule the buffer. */ -+ gcdOUTPUTBUFFER( -+ outputBuffer, outputBuffer->indent, -+ alignedPrefixData, Buffer, address, Size, Type, 0 -+ ); -+ } -+#else -+ /* Print/schedule the buffer. */ -+ if (Type == gceDUMP_BUFFER_FROM_USER) -+ { -+ gcdOUTPUTSTRING( -+ outputBuffer, outputBuffer->indent, -+ Buffer, 0, gcvNULL -+ ); -+ } -+ else -+ { -+ gcdOUTPUTBUFFER( -+ outputBuffer, outputBuffer->indent, -+ gcvNULL, Buffer, address, Size, Type, 0 -+ ); -+ } -+#endif -+ } -+ -+ /* Unlock when not coming from user, -+ or coming from user and not yet locked. */ -+ if (userLocked) -+ { -+ if ((Size > 4) -+ && (buffer[0] == ']') -+ && (buffer[1] == ' ') -+ && (buffer[2] == '-') -+ && (buffer[3] == '-')) -+ { -+ /* End of a user dump. */ -+ gcmkUNLOCKSECTION(lockHandle); -+ userLocked = gcvFALSE; -+ } -+ /* Else, let it pass through, don't unlock. */ -+ } -+ else -+ { -+ gcmkUNLOCKSECTION(lockHandle); -+ } -+} -+ -+/******************************************************************************* -+** -+** gckOS_DebugTrace -+** -+** Send a leveled message to the debugger. -+** -+** INPUT: -+** -+** gctUINT32 Level -+** Debug level of message. -+** -+** gctCONST_STRING Message -+** Pointer to message. -+** -+** ... -+** Optional arguments. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+ -+void -+gckOS_DebugTrace( -+ IN gctUINT32 Level, -+ IN gctCONST_STRING Message, -+ ... -+ ) -+{ -+ if (Level > _debugLevel) -+ { -+ return; -+ } -+ -+ gcmDEBUGPRINT(_GetArgumentSize(Message), gcvFALSE, Message); -+} -+ -+/******************************************************************************* -+** -+** gckOS_DebugTraceN -+** -+** Send a leveled message to the debugger. -+** -+** INPUT: -+** -+** gctUINT32 Level -+** Debug level of message. -+** -+** gctUINT ArgumentSize -+** The size of the optional arguments in bytes. -+** -+** gctCONST_STRING Message -+** Pointer to message. -+** -+** ... -+** Optional arguments. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+ -+void -+gckOS_DebugTraceN( -+ IN gctUINT32 Level, -+ IN gctUINT ArgumentSize, -+ IN gctCONST_STRING Message, -+ ... -+ ) -+{ -+ if (Level > _debugLevel) -+ { -+ return; -+ } -+ -+ gcmDEBUGPRINT(ArgumentSize, gcvFALSE, Message); -+} -+ -+/******************************************************************************* -+** -+** gckOS_DebugTraceZone -+** -+** Send a leveled and zoned message to the debugger. -+** -+** INPUT: -+** -+** gctUINT32 Level -+** Debug level for message. -+** -+** gctUINT32 Zone -+** Debug zone for message. -+** -+** gctCONST_STRING Message -+** Pointer to message. -+** -+** ... -+** Optional arguments. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+ -+void -+gckOS_DebugTraceZone( -+ IN gctUINT32 Level, -+ IN gctUINT32 Zone, -+ IN gctCONST_STRING Message, -+ ... -+ ) -+{ -+ if ((Level > _debugLevel) || !(Zone & _debugZones)) -+ { -+ return; -+ } -+ -+ gcmDEBUGPRINT(_GetArgumentSize(Message), gcvFALSE, Message); -+} -+ -+/******************************************************************************* -+** -+** gckOS_DebugTraceZoneN -+** -+** Send a leveled and zoned message to the debugger. -+** -+** INPUT: -+** -+** gctUINT32 Level -+** Debug level for message. -+** -+** gctUINT32 Zone -+** Debug zone for message. -+** -+** gctUINT ArgumentSize -+** The size of the optional arguments in bytes. -+** -+** gctCONST_STRING Message -+** Pointer to message. -+** -+** ... -+** Optional arguments. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+ -+void -+gckOS_DebugTraceZoneN( -+ IN gctUINT32 Level, -+ IN gctUINT32 Zone, -+ IN gctUINT ArgumentSize, -+ IN gctCONST_STRING Message, -+ ... -+ ) -+{ -+ if ((Level > _debugLevel) || !(Zone & _debugZones)) -+ { -+ return; -+ } -+ -+ gcmDEBUGPRINT(ArgumentSize, gcvFALSE, Message); -+} -+ -+/******************************************************************************* -+** -+** gckOS_DebugBreak -+** -+** Break into the debugger. -+** -+** INPUT: -+** -+** Nothing. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+void -+gckOS_DebugBreak( -+ void -+ ) -+{ -+ gckOS_DebugTrace(gcvLEVEL_ERROR, "%s(%d)", __FUNCTION__, __LINE__); -+} -+ -+/******************************************************************************* -+** -+** gckOS_DebugFatal -+** -+** Send a message to the debugger and break into the debugger. -+** -+** INPUT: -+** -+** gctCONST_STRING Message -+** Pointer to message. -+** -+** ... -+** Optional arguments. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+void -+gckOS_DebugFatal( -+ IN gctCONST_STRING Message, -+ ... -+ ) -+{ -+ gcmkPRINT_VERSION(); -+ gcmDEBUGPRINT(_GetArgumentSize(Message), gcvFALSE, Message); -+ -+ /* Break into the debugger. */ -+ gckOS_DebugBreak(); -+} -+ -+/******************************************************************************* -+** -+** gckOS_SetDebugLevel -+** -+** Set the debug level. -+** -+** INPUT: -+** -+** gctUINT32 Level -+** New debug level. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+ -+void -+gckOS_SetDebugLevel( -+ IN gctUINT32 Level -+ ) -+{ -+ _debugLevel = Level; -+} -+ -+/******************************************************************************* -+** -+** gckOS_SetDebugZone -+** -+** Set the debug zone. -+** -+** INPUT: -+** -+** gctUINT32 Zone -+** New debug zone. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+void -+gckOS_SetDebugZone( -+ IN gctUINT32 Zone -+ ) -+{ -+ _debugZones = Zone; -+} -+ -+/******************************************************************************* -+** -+** gckOS_SetDebugLevelZone -+** -+** Set the debug level and zone. -+** -+** INPUT: -+** -+** gctUINT32 Level -+** New debug level. -+** -+** gctUINT32 Zone -+** New debug zone. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+ -+void -+gckOS_SetDebugLevelZone( -+ IN gctUINT32 Level, -+ IN gctUINT32 Zone -+ ) -+{ -+ _debugLevel = Level; -+ _debugZones = Zone; -+} -+ -+/******************************************************************************* -+** -+** gckOS_SetDebugZones -+** -+** Enable or disable debug zones. -+** -+** INPUT: -+** -+** gctUINT32 Zones -+** Debug zones to enable or disable. -+** -+** gctBOOL Enable -+** Set to gcvTRUE to enable the zones (or the Zones with the current -+** zones) or gcvFALSE to disable the specified Zones. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+ -+void -+gckOS_SetDebugZones( -+ IN gctUINT32 Zones, -+ IN gctBOOL Enable -+ ) -+{ -+ if (Enable) -+ { -+ /* Enable the zones. */ -+ _debugZones |= Zones; -+ } -+ else -+ { -+ /* Disable the zones. */ -+ _debugZones &= ~Zones; -+ } -+} -+ -+/******************************************************************************* -+** -+** gckOS_Verify -+** -+** Called to verify the result of a function call. -+** -+** INPUT: -+** -+** gceSTATUS Status -+** Function call result. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+ -+void -+gckOS_Verify( -+ IN gceSTATUS status -+ ) -+{ -+ _lastError = status; -+} -+ -+/******************************************************************************* -+** -+** gckOS_DebugFlush -+** -+** Force messages to be flushed out. -+** -+** INPUT: -+** -+** gctCONST_STRING CallerName -+** Name of the caller function. -+** -+** gctUINT LineNumber -+** Line number of the caller. -+** -+** gctUINT32 DmaAddress -+** The current DMA address or ~0U to ignore. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+ -+void -+gckOS_DebugFlush( -+ gctCONST_STRING CallerName, -+ gctUINT LineNumber, -+ gctUINT32 DmaAddress -+ ) -+{ -+#if gcdBUFFERED_OUTPUT -+ _DirectPrint("\nFlush requested by %s(%d).\n\n", CallerName, LineNumber); -+ _Flush(DmaAddress); -+#endif -+} -+gctCONST_STRING -+gckOS_DebugStatus2Name( -+ gceSTATUS status -+ ) -+{ -+ switch (status) -+ { -+ case gcvSTATUS_OK: -+ return "gcvSTATUS_OK"; -+ case gcvSTATUS_TRUE: -+ return "gcvSTATUS_TRUE"; -+ case gcvSTATUS_NO_MORE_DATA: -+ return "gcvSTATUS_NO_MORE_DATA"; -+ case gcvSTATUS_CACHED: -+ return "gcvSTATUS_CACHED"; -+ case gcvSTATUS_MIPMAP_TOO_LARGE: -+ return "gcvSTATUS_MIPMAP_TOO_LARGE"; -+ case gcvSTATUS_NAME_NOT_FOUND: -+ return "gcvSTATUS_NAME_NOT_FOUND"; -+ case gcvSTATUS_NOT_OUR_INTERRUPT: -+ return "gcvSTATUS_NOT_OUR_INTERRUPT"; -+ case gcvSTATUS_MISMATCH: -+ return "gcvSTATUS_MISMATCH"; -+ case gcvSTATUS_MIPMAP_TOO_SMALL: -+ return "gcvSTATUS_MIPMAP_TOO_SMALL"; -+ case gcvSTATUS_LARGER: -+ return "gcvSTATUS_LARGER"; -+ case gcvSTATUS_SMALLER: -+ return "gcvSTATUS_SMALLER"; -+ case gcvSTATUS_CHIP_NOT_READY: -+ return "gcvSTATUS_CHIP_NOT_READY"; -+ case gcvSTATUS_NEED_CONVERSION: -+ return "gcvSTATUS_NEED_CONVERSION"; -+ case gcvSTATUS_SKIP: -+ return "gcvSTATUS_SKIP"; -+ case gcvSTATUS_DATA_TOO_LARGE: -+ return "gcvSTATUS_DATA_TOO_LARGE"; -+ case gcvSTATUS_INVALID_CONFIG: -+ return "gcvSTATUS_INVALID_CONFIG"; -+ case gcvSTATUS_CHANGED: -+ return "gcvSTATUS_CHANGED"; -+ case gcvSTATUS_NOT_SUPPORT_DITHER: -+ return "gcvSTATUS_NOT_SUPPORT_DITHER"; -+ -+ case gcvSTATUS_INVALID_ARGUMENT: -+ return "gcvSTATUS_INVALID_ARGUMENT"; -+ case gcvSTATUS_INVALID_OBJECT: -+ return "gcvSTATUS_INVALID_OBJECT"; -+ case gcvSTATUS_OUT_OF_MEMORY: -+ return "gcvSTATUS_OUT_OF_MEMORY"; -+ case gcvSTATUS_MEMORY_LOCKED: -+ return "gcvSTATUS_MEMORY_LOCKED"; -+ case gcvSTATUS_MEMORY_UNLOCKED: -+ return "gcvSTATUS_MEMORY_UNLOCKED"; -+ case gcvSTATUS_HEAP_CORRUPTED: -+ return "gcvSTATUS_HEAP_CORRUPTED"; -+ case gcvSTATUS_GENERIC_IO: -+ return "gcvSTATUS_GENERIC_IO"; -+ case gcvSTATUS_INVALID_ADDRESS: -+ return "gcvSTATUS_INVALID_ADDRESS"; -+ case gcvSTATUS_CONTEXT_LOSSED: -+ return "gcvSTATUS_CONTEXT_LOSSED"; -+ case gcvSTATUS_TOO_COMPLEX: -+ return "gcvSTATUS_TOO_COMPLEX"; -+ case gcvSTATUS_BUFFER_TOO_SMALL: -+ return "gcvSTATUS_BUFFER_TOO_SMALL"; -+ case gcvSTATUS_INTERFACE_ERROR: -+ return "gcvSTATUS_INTERFACE_ERROR"; -+ case gcvSTATUS_NOT_SUPPORTED: -+ return "gcvSTATUS_NOT_SUPPORTED"; -+ case gcvSTATUS_MORE_DATA: -+ return "gcvSTATUS_MORE_DATA"; -+ case gcvSTATUS_TIMEOUT: -+ return "gcvSTATUS_TIMEOUT"; -+ case gcvSTATUS_OUT_OF_RESOURCES: -+ return "gcvSTATUS_OUT_OF_RESOURCES"; -+ case gcvSTATUS_INVALID_DATA: -+ return "gcvSTATUS_INVALID_DATA"; -+ case gcvSTATUS_INVALID_MIPMAP: -+ return "gcvSTATUS_INVALID_MIPMAP"; -+ case gcvSTATUS_NOT_FOUND: -+ return "gcvSTATUS_NOT_FOUND"; -+ case gcvSTATUS_NOT_ALIGNED: -+ return "gcvSTATUS_NOT_ALIGNED"; -+ case gcvSTATUS_INVALID_REQUEST: -+ return "gcvSTATUS_INVALID_REQUEST"; -+ case gcvSTATUS_GPU_NOT_RESPONDING: -+ return "gcvSTATUS_GPU_NOT_RESPONDING"; -+ case gcvSTATUS_TIMER_OVERFLOW: -+ return "gcvSTATUS_TIMER_OVERFLOW"; -+ case gcvSTATUS_VERSION_MISMATCH: -+ return "gcvSTATUS_VERSION_MISMATCH"; -+ case gcvSTATUS_LOCKED: -+ return "gcvSTATUS_LOCKED"; -+ case gcvSTATUS_INTERRUPTED: -+ return "gcvSTATUS_INTERRUPTED"; -+ case gcvSTATUS_DEVICE: -+ return "gcvSTATUS_DEVICE"; -+ case gcvSTATUS_NOT_MULTI_PIPE_ALIGNED: -+ return "gcvSTATUS_NOT_MULTI_PIPE_ALIGNED"; -+ -+ /* Linker errors. */ -+ case gcvSTATUS_GLOBAL_TYPE_MISMATCH: -+ return "gcvSTATUS_GLOBAL_TYPE_MISMATCH"; -+ case gcvSTATUS_TOO_MANY_ATTRIBUTES: -+ return "gcvSTATUS_TOO_MANY_ATTRIBUTES"; -+ case gcvSTATUS_TOO_MANY_UNIFORMS: -+ return "gcvSTATUS_TOO_MANY_UNIFORMS"; -+ case gcvSTATUS_TOO_MANY_SAMPLER: -+ return "gcvSTATUS_TOO_MANY_SAMPLER"; -+ case gcvSTATUS_TOO_MANY_VARYINGS: -+ return "gcvSTATUS_TOO_MANY_VARYINGS"; -+ case gcvSTATUS_UNDECLARED_VARYING: -+ return "gcvSTATUS_UNDECLARED_VARYING"; -+ case gcvSTATUS_VARYING_TYPE_MISMATCH: -+ return "gcvSTATUS_VARYING_TYPE_MISMATCH"; -+ case gcvSTATUS_MISSING_MAIN: -+ return "gcvSTATUS_MISSING_MAIN"; -+ case gcvSTATUS_NAME_MISMATCH: -+ return "gcvSTATUS_NAME_MISMATCH"; -+ case gcvSTATUS_INVALID_INDEX: -+ return "gcvSTATUS_INVALID_INDEX"; -+ case gcvSTATUS_UNIFORM_MISMATCH: -+ return "gcvSTATUS_UNIFORM_MISMATCH"; -+ case gcvSTATUS_UNSAT_LIB_SYMBOL: -+ return "gcvSTATUS_UNSAT_LIB_SYMBOL"; -+ case gcvSTATUS_TOO_MANY_SHADERS: -+ return "gcvSTATUS_TOO_MANY_SHADERS"; -+ case gcvSTATUS_LINK_INVALID_SHADERS: -+ return "gcvSTATUS_LINK_INVALID_SHADERS"; -+ case gcvSTATUS_CS_NO_WORKGROUP_SIZE: -+ return "gcvSTATUS_CS_NO_WORKGROUP_SIZE"; -+ case gcvSTATUS_LINK_LIB_ERROR: -+ return "gcvSTATUS_LINK_LIB_ERROR"; -+ case gcvSTATUS_SHADER_VERSION_MISMATCH: -+ return "gcvSTATUS_SHADER_VERSION_MISMATCH"; -+ case gcvSTATUS_TOO_MANY_INSTRUCTION: -+ return "gcvSTATUS_TOO_MANY_INSTRUCTION"; -+ case gcvSTATUS_SSBO_MISMATCH: -+ return "gcvSTATUS_SSBO_MISMATCH"; -+ case gcvSTATUS_TOO_MANY_OUTPUT: -+ return "gcvSTATUS_TOO_MANY_OUTPUT"; -+ case gcvSTATUS_TOO_MANY_INPUT: -+ return "gcvSTATUS_TOO_MANY_INPUT"; -+ case gcvSTATUS_NOT_SUPPORT_CL: -+ return "gcvSTATUS_NOT_SUPPORT_CL"; -+ case gcvSTATUS_NOT_SUPPORT_INTEGER: -+ return "gcvSTATUS_NOT_SUPPORT_INTEGER"; -+ -+ /* Compiler errors. */ -+ case gcvSTATUS_COMPILER_FE_PREPROCESSOR_ERROR: -+ return "gcvSTATUS_COMPILER_FE_PREPROCESSOR_ERROR"; -+ case gcvSTATUS_COMPILER_FE_PARSER_ERROR: -+ return "gcvSTATUS_COMPILER_FE_PARSER_ERROR"; -+ -+ default: -+ return "nil"; -+ } -+} -+ -+/******************************************************************************* -+***** Binary Trace ************************************************************* -+*******************************************************************************/ -+ -+/******************************************************************************* -+** _VerifyMessage -+** -+** Verify a binary trace message, decode it to human readable string and print -+** it. -+** -+** ARGUMENTS: -+** -+** gctCONST_STRING Buffer -+** Pointer to buffer to store. -+** -+** gctSIZE_T Bytes -+** Buffer length. -+*/ -+void -+_VerifyMessage( -+ IN gctCONST_STRING Buffer, -+ IN gctSIZE_T Bytes -+ ) -+{ -+ char arguments[150] = {0}; -+ char format[100] = {0}; -+ -+ gctSTRING function; -+ gctPOINTER args; -+ gctUINT32 numArguments; -+ int i = 0; -+ gctUINT32 functionBytes; -+ -+ gcsBINARY_TRACE_MESSAGE_PTR message = (gcsBINARY_TRACE_MESSAGE_PTR)Buffer; -+ -+ /* Check signature. */ -+ if (message->signature != 0x7FFFFFFF) -+ { -+ gcmkPRINT("Signature error"); -+ return; -+ } -+ -+ /* Get function name. */ -+ function = (gctSTRING)&message->payload; -+ functionBytes = (gctUINT32)strlen(function) + 1; -+ -+ /* Get arguments number. */ -+ numArguments = message->numArguments; -+ -+ /* Get arguments . */ -+ args = function + functionBytes; -+ -+ /* Prepare format string. */ -+ while (numArguments--) -+ { -+ format[i++] = '%'; -+ format[i++] = 'x'; -+ format[i++] = ' '; -+ } -+ -+ format[i] = '\0'; -+ -+ if (numArguments) -+ { -+ gcmkVSPRINTF(arguments, 150, format, (gctARGUMENTS *) &args); -+ } -+ -+ gcmkPRINT("[%d](%d): %s(%d) %s", -+ message->pid, -+ message->tid, -+ function, -+ message->line, -+ arguments); -+} -+ -+ -+/******************************************************************************* -+** gckOS_WriteToRingBuffer -+** -+** Store a buffer to ring buffer. -+** -+** ARGUMENTS: -+** -+** gctCONST_STRING Buffer -+** Pointer to buffer to store. -+** -+** gctSIZE_T Bytes -+** Buffer length. -+*/ -+void -+gckOS_WriteToRingBuffer( -+ IN gctCONST_STRING Buffer, -+ IN gctSIZE_T Bytes -+ ) -+{ -+ -+} -+ -+/******************************************************************************* -+** gckOS_BinaryTrace -+** -+** Output a binary trace message. -+** -+** ARGUMENTS: -+** -+** gctCONST_STRING Function -+** Pointer to function name. -+** -+** gctINT Line -+** Line number. -+** -+** gctCONST_STRING Text OPTIONAL -+** Optional pointer to a descriptive text. -+** -+** ... -+** Optional arguments to the descriptive text. -+*/ -+void -+gckOS_BinaryTrace( -+ IN gctCONST_STRING Function, -+ IN gctINT Line, -+ IN gctCONST_STRING Text OPTIONAL, -+ ... -+ ) -+{ -+ static gctUINT32 messageSignature = 0x7FFFFFFF; -+ char buffer[gcdBINARY_TRACE_MESSAGE_SIZE]; -+ gctUINT32 numArguments = 0; -+ gctUINT32 functionBytes; -+ gctUINT32 i = 0; -+ gctSTRING payload; -+ gcsBINARY_TRACE_MESSAGE_PTR message = (gcsBINARY_TRACE_MESSAGE_PTR)buffer; -+ -+ /* Calculate arguments number. */ -+ if (Text) -+ { -+ while (Text[i] != '\0') -+ { -+ if (Text[i] == '%') -+ { -+ numArguments++; -+ } -+ i++; -+ } -+ } -+ -+ message->signature = messageSignature; -+ message->pid = gcmkGETPROCESSID(); -+ message->tid = gcmkGETTHREADID(); -+ message->line = Line; -+ message->numArguments = numArguments; -+ -+ payload = (gctSTRING)&message->payload; -+ -+ /* Function name. */ -+ functionBytes = (gctUINT32)gcmkSTRLEN(Function) + 1; -+ gcmkMEMCPY(payload, Function, functionBytes); -+ -+ /* Advance to next payload. */ -+ payload += functionBytes; -+ -+ /* Arguments value. */ -+ if (numArguments) -+ { -+ gctARGUMENTS p; -+ gcmkARGUMENTS_START(p, Text); -+ -+ for (i = 0; i < numArguments; ++i) -+ { -+ gctPOINTER value = gcmkARGUMENTS_ARG(p, gctPOINTER); -+ gcmkMEMCPY(payload, &value, gcmSIZEOF(gctPOINTER)); -+ payload += gcmSIZEOF(gctPOINTER); -+ } -+ -+ gcmkARGUMENTS_END(p); -+ } -+ -+ gcmkASSERT(payload - buffer <= gcdBINARY_TRACE_MESSAGE_SIZE); -+ -+ -+ /* Send buffer to ring buffer. */ -+ gckOS_WriteToRingBuffer(buffer, (gctUINT32)(payload - buffer)); -+} -+ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_debugfs.c linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_debugfs.c ---- linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_debugfs.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_debugfs.c 2015-11-30 17:56:13.572138258 +0100 -@@ -0,0 +1,1137 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#ifdef MODULE -+#include -+#endif -+#include -+#include -+#include -+#ifdef MODVERSIONS -+#include -+#endif -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "gc_hal_kernel_linux.h" -+#include "gc_hal_kernel.h" -+ -+/* -+ Prequsite: -+ -+ 1) Debugfs feature must be enabled in the kernel. -+ 1.a) You can enable this, in the compilation of the uImage, all you have to do is, In the "make menuconfig" part, -+ you have to enable the debugfs in the kernel hacking part of the menu. -+ -+ HOW TO USE: -+ 1) insert the driver with the following option logFileSize, Ex: insmod galcore.ko ...... logFileSize=10240 -+ This gives a circular buffer of 10 MB -+ -+ 2)Usually after inserting the driver, the debug file system is mounted under /sys/kernel/debug/ -+ -+ 2.a)If the debugfs is not mounted, you must do "mount -t debugfs none /sys/kernel/debug" -+ -+ 3) To read what is being printed in the debugfs file system: -+ Ex : cat /sys/kernel/debug/gc/galcore_trace -+ -+ 4)To write into the debug file system from user side : -+ Ex: echo "hello" > cat /sys/kernel/debug/gc/galcore_trace -+ -+ 5)To write into debugfs from kernel side, Use the function called gckDEBUGFS_Print -+ -+ How to Get Video Memory Usage: -+ 1) Select a process whose video memory usage can be dump, no need to reset it until is needed to be change. -+ echo > /sys/kernel/debug/gc/vidmem -+ -+ 2) Get video memory usage. -+ cat /sys/kernel/debug/gc/vidmem -+ -+ USECASE Kernel Dump: -+ -+ 1) Go to /hal/inc/gc_hal_options.h, and enable the following flags: -+ - # define gcdDUMP 1 -+ - # define gcdDUMP_IN_KERNEL 1 -+ - # define gcdDUMP_COMMAND 1 -+ -+ 2) Go to /hal/kernel/gc_hal_kernel_command.c and disable the following flag -+ -#define gcdSIMPLE_COMMAND_DUMP 0 -+ -+ 3) Compile the driver -+ 4) insmod it with the logFileSize option -+ 5) Run an application -+ 6) You can get the dump by cat /sys/kernel/debug/gpu/galcore_trace -+ -+ */ -+ -+/**/ -+typedef va_list gctDBGARGS ; -+#define gcmkARGS_START(argument, pointer) va_start(argument, pointer) -+#define gcmkARGS_END(argument) va_end(argument) -+ -+#define gcmkDEBUGFS_PRINT(ArgumentSize, Message) \ -+ { \ -+ gctDBGARGS __arguments__; \ -+ gcmkARGS_START(__arguments__, Message); \ -+ _debugfs_res = _DebugFSPrint(ArgumentSize, Message, &__arguments__);\ -+ gcmkARGS_END(__arguments__); \ -+ } -+ -+/* Debug File System Node Struct. */ -+struct _gcsDEBUGFS_Node -+{ -+ /*wait queues for read and write operations*/ -+#if defined(DECLARE_WAIT_QUEUE_HEAD) -+ wait_queue_head_t read_q , write_q ; -+#else -+ struct wait_queue *read_q , *write_q ; -+#endif -+ struct dentry *parent ; /*parent directory*/ -+ struct dentry *filen ; /*filename*/ -+ struct dentry *vidmem; -+ struct semaphore sem ; /* mutual exclusion semaphore */ -+ char *data ; /* The circular buffer data */ -+ int size ; /* Size of the buffer pointed to by 'data' */ -+ int refcount ; /* Files that have this buffer open */ -+ int read_point ; /* Offset in circ. buffer of oldest data */ -+ int write_point ; /* Offset in circ. buffer of newest data */ -+ int offset ; /* Byte number of read_point in the stream */ -+ struct _gcsDEBUGFS_Node *next ; -+}; -+ -+/* amount of data in the queue */ -+#define gcmkNODE_QLEN(node) ( (node)->write_point >= (node)->read_point ? \ -+ (node)->write_point - (node)->read_point : \ -+ (node)->size - (node)->read_point + (node)->write_point) -+ -+/* byte number of the last byte in the queue */ -+#define gcmkNODE_FIRST_EMPTY_BYTE(node) ((node)->offset + gcmkNODE_QLEN(node)) -+ -+/*Synchronization primitives*/ -+#define gcmkNODE_READQ(node) (&((node)->read_q)) -+#define gcmkNODE_WRITEQ(node) (&((node)->write_q)) -+ -+/*Utilities*/ -+#define gcmkMIN(x, y) ((x) < (y) ? (x) : y) -+ -+/*Debug File System Struct*/ -+typedef struct _gcsDEBUGFS_ -+{ -+ gcsDEBUGFS_Node* linkedlist ; -+ gcsDEBUGFS_Node* currentNode ; -+ int isInited ; -+} gcsDEBUGFS_ ; -+ -+/*debug file system*/ -+static gcsDEBUGFS_ gc_dbgfs ; -+ -+static int gc_debugfs_open(struct inode *inode, struct file *file) -+{ -+ gcsINFO_NODE *node = inode->i_private; -+ -+ return single_open(file, node->info->show, node); -+} -+ -+static const struct file_operations gc_debugfs_operations = { -+ .owner = THIS_MODULE, -+ .open = gc_debugfs_open, -+ .read = seq_read, -+ .llseek = seq_lseek, -+ .release = single_release, -+}; -+ -+gceSTATUS -+gckDEBUGFS_DIR_Init( -+ IN gckDEBUGFS_DIR Dir, -+ IN struct dentry *root, -+ IN gctCONST_STRING Name -+ ) -+{ -+ Dir->root = debugfs_create_dir(Name, root); -+ -+ if (!Dir->root) -+ { -+ return gcvSTATUS_NOT_SUPPORTED; -+ } -+ -+ INIT_LIST_HEAD(&Dir->nodeList); -+ -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckDEBUGFS_DIR_CreateFiles( -+ IN gckDEBUGFS_DIR Dir, -+ IN gcsINFO * List, -+ IN int count, -+ IN gctPOINTER Data -+ ) -+{ -+ int i; -+ gcsINFO_NODE * node; -+ gceSTATUS status; -+ -+ for (i = 0; i < count; i++) -+ { -+ /* Create a node. */ -+ node = (gcsINFO_NODE *)kzalloc(sizeof(gcsINFO_NODE), GFP_KERNEL); -+ -+ node->info = &List[i]; -+ node->device = Data; -+ -+ /* Bind to a file. TODO: clean up when fail. */ -+ node->entry = debugfs_create_file( -+ List[i].name, S_IRUGO|S_IWUSR, Dir->root, node, &gc_debugfs_operations); -+ -+ if (!node->entry) -+ { -+ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); -+ } -+ -+ list_add(&(node->head), &(Dir->nodeList)); -+ } -+ -+ return gcvSTATUS_OK; -+ -+OnError: -+ gcmkVERIFY_OK(gckDEBUGFS_DIR_RemoveFiles(Dir, List, count)); -+ return status; -+} -+ -+gceSTATUS -+gckDEBUGFS_DIR_RemoveFiles( -+ IN gckDEBUGFS_DIR Dir, -+ IN gcsINFO * List, -+ IN int count -+ ) -+{ -+ int i; -+ gcsINFO_NODE * node; -+ gcsINFO_NODE * temp; -+ -+ for (i = 0; i < count; i++) -+ { -+ list_for_each_entry_safe(node, temp, &Dir->nodeList, head) -+ { -+ if (node->info == &List[i]) -+ { -+ debugfs_remove(node->entry); -+ list_del(&node->head); -+ kfree(node); -+ } -+ } -+ } -+ -+ return gcvSTATUS_OK; -+} -+ -+void -+gckDEBUGFS_DIR_Deinit( -+ IN gckDEBUGFS_DIR Dir -+ ) -+{ -+ if (Dir->root != NULL) -+ { -+ debugfs_remove(Dir->root); -+ Dir->root = NULL; -+ } -+} -+ -+/******************************************************************************* -+ ** -+ ** READ & WRITE FUNCTIONS (START) -+ ** -+ *******************************************************************************/ -+ -+/******************************************************************************* -+ ** -+ ** _ReadFromNode -+ ** -+ ** 1) reading bytes out of a circular buffer with wraparound. -+ ** 2)returns caddr_t, pointer to data read, which the caller must free. -+ ** 3) length is (a pointer to) the number of bytes to be read, which will be set by this function to -+ ** be the number of bytes actually returned -+ ** -+ *******************************************************************************/ -+static caddr_t -+_ReadFromNode ( -+ gcsDEBUGFS_Node* Node , -+ size_t *Length , -+ loff_t *Offset -+ ) -+{ -+ caddr_t retval ; -+ int bytes_copied = 0 , n , start_point , remaining ; -+ -+ /* is the user trying to read data that has already scrolled off? */ -+ if ( *Offset < Node->offset ) -+ { -+ *Offset = Node->offset ; -+ } -+ -+ /* is the user trying to read past EOF? */ -+ if ( *Offset >= gcmkNODE_FIRST_EMPTY_BYTE ( Node ) ) -+ { -+ return NULL ; -+ } -+ -+ /* find the smaller of the total bytes we have available and what -+ * the user is asking for */ -+ -+ *Length = gcmkMIN ( *Length , gcmkNODE_FIRST_EMPTY_BYTE ( Node ) - *Offset ) ; -+ -+ remaining = * Length ; -+ -+ /* figure out where to start based on user's Offset */ -+ start_point = Node->read_point + ( *Offset - Node->offset ) ; -+ -+ start_point = start_point % Node->size ; -+ -+ /* allocate memory to return */ -+ if ( ( retval = kmalloc ( sizeof (char ) * remaining , GFP_KERNEL ) ) == NULL ) -+ return NULL ; -+ -+ /* copy the (possibly noncontiguous) data to our buffer */ -+ while ( remaining ) -+ { -+ n = gcmkMIN ( remaining , Node->size - start_point ) ; -+ memcpy ( retval + bytes_copied , Node->data + start_point , n ) ; -+ bytes_copied += n ; -+ remaining -= n ; -+ start_point = ( start_point + n ) % Node->size ; -+ } -+ -+ /* advance user's file pointer */ -+ *Offset += * Length ; -+ -+ return retval ; -+} -+ -+/******************************************************************************* -+ ** -+ ** _WriteToNode -+ ** -+ ** 1) writes to a circular buffer with wraparound. -+ ** 2)in case of an overflow, it overwrites the oldest unread data. -+ ** -+ *********************************************************************************/ -+static void -+_WriteToNode ( -+ gcsDEBUGFS_Node* Node , -+ caddr_t Buf , -+ int Length -+ ) -+{ -+ int bytes_copied = 0 ; -+ int overflow = 0 ; -+ int n ; -+ -+ if ( Length + gcmkNODE_QLEN ( Node ) >= ( Node->size - 1 ) ) -+ { -+ overflow = 1 ; -+ -+ /* in case of overflow, figure out where the new buffer will -+ * begin. we start by figuring out where the current buffer ENDS: -+ * node->parent->offset + gcmkNODE_QLEN. we then advance the end-offset -+ * by the Length of the current write, and work backwards to -+ * figure out what the oldest unoverwritten data will be (i.e., -+ * size of the buffer). */ -+ Node->offset = Node->offset + gcmkNODE_QLEN ( Node ) + Length -+ - Node->size + 1 ; -+ } -+ -+ while ( Length ) -+ { -+ /* how many contiguous bytes are available from the write point to -+ * the end of the circular buffer? */ -+ n = gcmkMIN ( Length , Node->size - Node->write_point ) ; -+ memcpy ( Node->data + Node->write_point , Buf + bytes_copied , n ) ; -+ bytes_copied += n ; -+ Length -= n ; -+ Node->write_point = ( Node->write_point + n ) % Node->size ; -+ } -+ -+ /* if there is an overflow, reset the read point to read whatever is -+ * the oldest data that we have, that has not yet been -+ * overwritten. */ -+ if ( overflow ) -+ { -+ Node->read_point = ( Node->write_point + 1 ) % Node->size ; -+ } -+} -+ -+/******************************************************************************* -+ ** -+ ** PRINTING UTILITY (START) -+ ** -+ *******************************************************************************/ -+ -+/******************************************************************************* -+ ** -+ ** _GetArgumentSize -+ ** -+ ** -+ *******************************************************************************/ -+static gctINT -+_GetArgumentSize ( -+ IN gctCONST_STRING Message -+ ) -+{ -+ gctINT i , count ; -+ -+ for ( i = 0 , count = 0 ; Message[i] ; i += 1 ) -+ { -+ if ( Message[i] == '%' ) -+ { -+ count += 1 ; -+ } -+ } -+ return count * sizeof (unsigned int ) ; -+} -+ -+/******************************************************************************* -+ ** -+ ** _AppendString -+ ** -+ ** -+ *******************************************************************************/ -+static ssize_t -+_AppendString ( -+ IN gcsDEBUGFS_Node* Node , -+ IN gctCONST_STRING String , -+ IN int Length -+ ) -+{ -+ caddr_t message = NULL ; -+ int n ; -+ -+ /* if the message is longer than the buffer, just take the beginning -+ * of it, in hopes that the reader (if any) will have time to read -+ * before we wrap around and obliterate it */ -+ n = gcmkMIN ( Length , Node->size - 1 ) ; -+ -+ /* make sure we have the memory for it */ -+ if ( ( message = kmalloc ( n , GFP_ATOMIC ) ) == NULL ) -+ return - ENOMEM ; -+ -+ /* copy into our temp buffer */ -+ memcpy ( message , String , n ) ; -+ -+ /* now copy it into the circular buffer and free our temp copy */ -+ _WriteToNode ( Node , message , n ) ; -+ kfree ( message ) ; -+ return n ; -+} -+ -+/******************************************************************************* -+ ** -+ ** _DebugFSPrint -+ ** -+ ** -+ *******************************************************************************/ -+static ssize_t -+_DebugFSPrint ( -+ IN unsigned int ArgumentSize , -+ IN const char* Message , -+ IN gctDBGARGS * Arguments -+ -+ ) -+{ -+ char buffer[MAX_LINE_SIZE] ; -+ int len ; -+ ssize_t res=0; -+ -+ if(in_interrupt()) -+ { -+ return - ERESTARTSYS ; -+ } -+ -+ len = vsnprintf ( buffer , sizeof (buffer ) , Message , *( va_list * ) Arguments ) ; -+ buffer[len] = '\0' ; -+ -+ /* Add end-of-line if missing. */ -+ if ( buffer[len - 1] != '\n' ) -+ { -+ buffer[len ++] = '\n' ; -+ buffer[len] = '\0' ; -+ } -+ res = _AppendString ( gc_dbgfs.currentNode , buffer , len ) ; -+ wake_up ( gcmkNODE_READQ ( gc_dbgfs.currentNode ) ) ; /* blocked in read*/ -+ return res; -+} -+ -+/******************************************************************************* -+ ** -+ ** LINUX SYSTEM FUNCTIONS (START) -+ ** -+ *******************************************************************************/ -+ -+/******************************************************************************* -+ ** -+ ** find the vivlog structure associated with an inode. -+ ** returns a pointer to the structure if found, NULL if not found -+ ** -+ *******************************************************************************/ -+static gcsDEBUGFS_Node* -+_GetNodeInfo ( -+ IN struct inode *Inode -+ ) -+{ -+ gcsDEBUGFS_Node* node ; -+ -+ if ( Inode == NULL ) -+ return NULL ; -+ -+ for ( node = gc_dbgfs.linkedlist ; node != NULL ; node = node->next ) -+ if ( node->filen->d_inode->i_ino == Inode->i_ino ) -+ return node ; -+ -+ return NULL ; -+} -+ -+/******************************************************************************* -+ ** -+ ** _DebugFSRead -+ ** -+ *******************************************************************************/ -+static ssize_t -+_DebugFSRead ( -+ struct file *file , -+ char __user * buffer , -+ size_t length , -+ loff_t * offset -+ ) -+{ -+ int retval ; -+ caddr_t data_to_return ; -+ gcsDEBUGFS_Node* node ; -+ /* get the metadata about this emlog */ -+ if ( ( node = _GetNodeInfo ( file->f_path.dentry->d_inode ) ) == NULL ) -+ { -+ printk ( "debugfs_read: record not found\n" ) ; -+ return - EIO ; -+ } -+ -+ /* wait until there's data available (unless we do nonblocking reads) */ -+ while ( *offset >= gcmkNODE_FIRST_EMPTY_BYTE ( node ) ) -+ { -+ if ( file->f_flags & O_NONBLOCK ) -+ { -+ return - EAGAIN ; -+ } -+ if ( wait_event_interruptible ( ( *( gcmkNODE_READQ ( node ) ) ) , ( *offset < gcmkNODE_FIRST_EMPTY_BYTE ( node ) ) ) ) -+ { -+ return - ERESTARTSYS ; /* signal: tell the fs layer to handle it */ -+ } -+ } -+ data_to_return = _ReadFromNode ( node , &length , offset ) ; -+ if ( data_to_return == NULL ) -+ { -+ retval = 0 ; -+ goto unlock ; -+ } -+ if ( copy_to_user ( buffer , data_to_return , length ) > 0 ) -+ { -+ retval = - EFAULT ; -+ } -+ else -+ { -+ retval = length ; -+ } -+ kfree ( data_to_return ) ; -+unlock: -+ wake_up_interruptible ( gcmkNODE_WRITEQ ( node ) ) ; -+ return retval ; -+} -+ -+/******************************************************************************* -+ ** -+ **_DebugFSWrite -+ ** -+ *******************************************************************************/ -+static ssize_t -+_DebugFSWrite ( -+ struct file *file , -+ const char __user * buffer , -+ size_t length , -+ loff_t * offset -+ ) -+{ -+ caddr_t message = NULL ; -+ int n ; -+ gcsDEBUGFS_Node*node ; -+ -+ /* get the metadata about this log */ -+ if ( ( node = _GetNodeInfo ( file->f_path.dentry->d_inode ) ) == NULL ) -+ { -+ return - EIO ; -+ } -+ -+ /* if the message is longer than the buffer, just take the beginning -+ * of it, in hopes that the reader (if any) will have time to read -+ * before we wrap around and obliterate it */ -+ n = gcmkMIN ( length , node->size - 1 ) ; -+ -+ /* make sure we have the memory for it */ -+ if ( ( message = kmalloc ( n , GFP_KERNEL ) ) == NULL ) -+ { -+ return - ENOMEM ; -+ } -+ -+ -+ /* copy into our temp buffer */ -+ if ( copy_from_user ( message , buffer , n ) > 0 ) -+ { -+ kfree ( message ) ; -+ return - EFAULT ; -+ } -+ -+ /* now copy it into the circular buffer and free our temp copy */ -+ _WriteToNode ( node , message , n ) ; -+ -+ kfree ( message ) ; -+ -+ /* wake up any readers that might be waiting for the data. we call -+ * schedule in the vague hope that a reader will run before the -+ * writer's next write, to avoid losing data. */ -+ wake_up_interruptible ( gcmkNODE_READQ ( node ) ) ; -+ -+ return n ; -+} -+ -+int dumpProcess = 0; -+ -+void -+_PrintCounter( -+ struct seq_file *file, -+ gcsDATABASE_COUNTERS * counter, -+ gctCONST_STRING Name -+ ) -+{ -+ seq_printf(file,"Counter: %s\n", Name); -+ -+ seq_printf(file,"%-9s%10s","", "All"); -+ -+ seq_printf(file, "\n"); -+ -+ seq_printf(file,"%-9s","Current"); -+ -+ seq_printf(file,"%10lld", counter->bytes); -+ -+ seq_printf(file, "\n"); -+ -+ seq_printf(file,"%-9s","Maximum"); -+ -+ seq_printf(file,"%10lld", counter->maxBytes); -+ -+ seq_printf(file, "\n"); -+ -+ seq_printf(file,"%-9s","Total"); -+ -+ seq_printf(file,"%10lld", counter->totalBytes); -+ -+ seq_printf(file, "\n"); -+} -+ -+void -+_ShowCounters( -+ struct seq_file *file, -+ gcsDATABASE_PTR database -+ ) -+{ -+ gctUINT i = 0; -+ gcsDATABASE_COUNTERS * counter; -+ gcsDATABASE_COUNTERS * nonPaged; -+ -+ static gctCONST_STRING surfaceTypes[] = { -+ "UNKNOWN", -+ "Index", -+ "Vertex", -+ "Texture", -+ "RT", -+ "Depth", -+ "Bitmap", -+ "TS", -+ "Image", -+ "Mask", -+ "Scissor", -+ "HZDepth", -+ }; -+ -+ /* Get pointer to counters. */ -+ counter = &database->vidMem; -+ -+ nonPaged = &database->nonPaged; -+ -+ seq_printf(file,"Counter: vidMem (for each surface type)\n"); -+ -+ seq_printf(file,"%-9s%10s","", "All"); -+ -+ for (i = 1; i < gcvSURF_NUM_TYPES; i++) -+ { -+ counter = &database->vidMemType[i]; -+ -+ seq_printf(file, "%10s",surfaceTypes[i]); -+ } -+ -+ seq_printf(file, "\n"); -+ -+ seq_printf(file,"%-9s","Current"); -+ -+ seq_printf(file,"%10lld", database->vidMem.bytes); -+ -+ for (i = 1; i < gcvSURF_NUM_TYPES; i++) -+ { -+ counter = &database->vidMemType[i]; -+ -+ seq_printf(file,"%10lld", counter->bytes); -+ } -+ -+ seq_printf(file, "\n"); -+ -+ seq_printf(file,"%-9s","Maximum"); -+ -+ seq_printf(file,"%10lld", database->vidMem.maxBytes); -+ -+ for (i = 1; i < gcvSURF_NUM_TYPES; i++) -+ { -+ counter = &database->vidMemType[i]; -+ -+ seq_printf(file,"%10lld", counter->maxBytes); -+ } -+ -+ seq_printf(file, "\n"); -+ -+ seq_printf(file,"%-9s","Total"); -+ -+ seq_printf(file,"%10lld", database->vidMem.totalBytes); -+ -+ for (i = 1; i < gcvSURF_NUM_TYPES; i++) -+ { -+ counter = &database->vidMemType[i]; -+ -+ seq_printf(file,"%10lld", counter->totalBytes); -+ } -+ -+ seq_printf(file, "\n"); -+ -+ seq_printf(file,"Counter: vidMem (for each pool)\n"); -+ -+ seq_printf(file,"%-9s%10s","", "All"); -+ -+ for (i = 1; i < gcvPOOL_NUMBER_OF_POOLS; i++) -+ { -+ seq_printf(file, "%10d", i); -+ } -+ -+ seq_printf(file, "\n"); -+ -+ seq_printf(file,"%-9s","Current"); -+ -+ seq_printf(file,"%10lld", database->vidMem.bytes); -+ -+ for (i = 1; i < gcvPOOL_NUMBER_OF_POOLS; i++) -+ { -+ counter = &database->vidMemPool[i]; -+ -+ seq_printf(file,"%10lld", counter->bytes); -+ } -+ -+ seq_printf(file, "\n"); -+ -+ seq_printf(file,"%-9s","Maximum"); -+ -+ seq_printf(file,"%10lld", database->vidMem.maxBytes); -+ -+ for (i = 1; i < gcvPOOL_NUMBER_OF_POOLS; i++) -+ { -+ counter = &database->vidMemPool[i]; -+ -+ seq_printf(file,"%10lld", counter->maxBytes); -+ } -+ -+ seq_printf(file, "\n"); -+ -+ seq_printf(file,"%-9s","Total"); -+ -+ seq_printf(file,"%10lld", database->vidMem.totalBytes); -+ -+ for (i = 1; i < gcvPOOL_NUMBER_OF_POOLS; i++) -+ { -+ counter = &database->vidMemPool[i]; -+ -+ seq_printf(file,"%10lld", counter->totalBytes); -+ } -+ -+ seq_printf(file, "\n"); -+ -+ /* Print nonPaged. */ -+ _PrintCounter(file, &database->nonPaged, "nonPaged"); -+ _PrintCounter(file, &database->contiguous, "contiguous"); -+ _PrintCounter(file, &database->mapUserMemory, "mapUserMemory"); -+ _PrintCounter(file, &database->mapMemory, "mapMemory"); -+} -+ -+gckKERNEL -+_GetValidKernel( -+ gckGALDEVICE Device -+); -+static int vidmem_show(struct seq_file *file, void *unused) -+{ -+ gceSTATUS status; -+ gcsDATABASE_PTR database; -+ gckGALDEVICE device = file->private; -+ -+ gckKERNEL kernel = _GetValidKernel(device); -+ if(kernel == gcvNULL) -+ { -+ return 0; -+ } -+ -+ /* Find the database. */ -+ gcmkONERROR( -+ gckKERNEL_FindDatabase(kernel, dumpProcess, gcvFALSE, &database)); -+ -+ seq_printf(file, "VidMem Usage (Process %d):\n", dumpProcess); -+ -+ _ShowCounters(file, database); -+ -+ return 0; -+ -+OnError: -+ return 0; -+} -+ -+static int -+vidmem_open( -+ struct inode *inode, -+ struct file *file -+ ) -+{ -+ return single_open(file, vidmem_show, inode->i_private); -+} -+ -+static ssize_t -+vidmem_write( -+ struct file *file, -+ const char __user *buf, -+ size_t count, -+ loff_t *pos -+ ) -+{ -+ dumpProcess = simple_strtol(buf, NULL, 0); -+ return count; -+} -+ -+/******************************************************************************* -+ ** -+ ** File Operations Table -+ ** -+ *******************************************************************************/ -+static const struct file_operations debugfs_operations = { -+ .owner = THIS_MODULE , -+ .read = _DebugFSRead , -+ .write = _DebugFSWrite , -+} ; -+ -+static const struct file_operations vidmem_operations = { -+ .owner = THIS_MODULE , -+ .open = vidmem_open, -+ .read = seq_read, -+ .write = vidmem_write, -+ .llseek = seq_lseek, -+} ; -+ -+/******************************************************************************* -+ ** -+ ** INTERFACE FUNCTIONS (START) -+ ** -+ *******************************************************************************/ -+ -+/******************************************************************************* -+ ** -+ ** gckDEBUGFS_IsEnabled -+ ** -+ ** -+ ** INPUT: -+ ** -+ ** OUTPUT: -+ ** -+ *******************************************************************************/ -+ -+ -+gctINT -+gckDEBUGFS_IsEnabled ( void ) -+{ -+ return gc_dbgfs.isInited ; -+} -+/******************************************************************************* -+ ** -+ ** gckDEBUGFS_Initialize -+ ** -+ ** -+ ** INPUT: -+ ** -+ ** OUTPUT: -+ ** -+ *******************************************************************************/ -+ -+gctINT -+gckDEBUGFS_Initialize ( void ) -+{ -+ if ( ! gc_dbgfs.isInited ) -+ { -+ gc_dbgfs.linkedlist = gcvNULL ; -+ gc_dbgfs.currentNode = gcvNULL ; -+ gc_dbgfs.isInited = 1 ; -+ } -+ return gc_dbgfs.isInited ; -+} -+/******************************************************************************* -+ ** -+ ** gckDEBUGFS_Terminate -+ ** -+ ** -+ ** INPUT: -+ ** -+ ** OUTPUT: -+ ** -+ *******************************************************************************/ -+ -+gctINT -+gckDEBUGFS_Terminate ( void ) -+{ -+ gcsDEBUGFS_Node * next = gcvNULL ; -+ gcsDEBUGFS_Node * temp = gcvNULL ; -+ if ( gc_dbgfs.isInited ) -+ { -+ temp = gc_dbgfs.linkedlist ; -+ while ( temp != gcvNULL ) -+ { -+ next = temp->next ; -+ gckDEBUGFS_FreeNode ( temp ) ; -+ kfree ( temp ) ; -+ temp = next ; -+ } -+ gc_dbgfs.isInited = 0 ; -+ } -+ return 0 ; -+} -+ -+ -+/******************************************************************************* -+ ** -+ ** gckDEBUGFS_CreateNode -+ ** -+ ** -+ ** INPUT: -+ ** -+ ** OUTPUT: -+ ** -+ ** gckDEBUGFS_FreeNode * Device -+ ** Pointer to a variable receiving the gcsDEBUGFS_Node object pointer on -+ ** success. -+ *********************************************************************************/ -+ -+gctINT -+gckDEBUGFS_CreateNode ( -+ IN gctPOINTER Device, -+ IN gctINT SizeInKB , -+ IN struct dentry * Root , -+ IN gctCONST_STRING NodeName , -+ OUT gcsDEBUGFS_Node **Node -+ ) -+{ -+ gcsDEBUGFS_Node*node ; -+ /* allocate space for our metadata and initialize it */ -+ if ( ( node = kmalloc ( sizeof (gcsDEBUGFS_Node ) , GFP_KERNEL ) ) == NULL ) -+ goto struct_malloc_failed ; -+ -+ /*Zero it out*/ -+ memset ( node , 0 , sizeof (gcsDEBUGFS_Node ) ) ; -+ -+ /*Init the sync primitives*/ -+#if defined(DECLARE_WAIT_QUEUE_HEAD) -+ init_waitqueue_head ( gcmkNODE_READQ ( node ) ) ; -+#else -+ init_waitqueue ( gcmkNODE_READQ ( node ) ) ; -+#endif -+ -+#if defined(DECLARE_WAIT_QUEUE_HEAD) -+ init_waitqueue_head ( gcmkNODE_WRITEQ ( node ) ) ; -+#else -+ init_waitqueue ( gcmkNODE_WRITEQ ( node ) ) ; -+#endif -+ /*End the sync primitives*/ -+ -+ /*creating the debug file system*/ -+ node->parent = Root; -+ -+ if (SizeInKB) -+ { -+ /* figure out how much of a buffer this should be and allocate the buffer */ -+ node->size = 1024 * SizeInKB ; -+ if ( ( node->data = ( char * ) vmalloc ( sizeof (char ) * node->size ) ) == NULL ) -+ goto data_malloc_failed ; -+ -+ /*creating the file*/ -+ node->filen = debugfs_create_file(NodeName, S_IRUGO|S_IWUSR, node->parent, NULL, -+ &debugfs_operations); -+ } -+ -+ node->vidmem -+ = debugfs_create_file("vidmem", S_IRUGO|S_IWUSR, node->parent, Device, &vidmem_operations); -+ -+ /* add it to our linked list */ -+ node->next = gc_dbgfs.linkedlist ; -+ gc_dbgfs.linkedlist = node ; -+ -+ -+ /* pass the struct back */ -+ *Node = node ; -+ return 0 ; -+ -+ -+data_malloc_failed: -+ kfree ( node ) ; -+struct_malloc_failed: -+ return - ENOMEM ; -+} -+ -+/******************************************************************************* -+ ** -+ ** gckDEBUGFS_FreeNode -+ ** -+ ** -+ ** INPUT: -+ ** -+ ** OUTPUT: -+ ** -+ *******************************************************************************/ -+void -+gckDEBUGFS_FreeNode ( -+ IN gcsDEBUGFS_Node * Node -+ ) -+{ -+ -+ gcsDEBUGFS_Node **ptr ; -+ -+ if ( Node == NULL ) -+ { -+ printk ( "null passed to free_vinfo\n" ) ; -+ return ; -+ } -+ -+ /*free data*/ -+ vfree ( Node->data ) ; -+ -+ /*Close Debug fs*/ -+ if (Node->vidmem) -+ { -+ debugfs_remove(Node->vidmem); -+ } -+ -+ if ( Node->filen ) -+ { -+ debugfs_remove ( Node->filen ) ; -+ } -+ -+ /* now delete the node from the linked list */ -+ ptr = & ( gc_dbgfs.linkedlist ) ; -+ while ( *ptr != Node ) -+ { -+ if ( ! *ptr ) -+ { -+ printk ( "corrupt info list!\n" ) ; -+ break ; -+ } -+ else -+ ptr = & ( ( **ptr ).next ) ; -+ } -+ *ptr = Node->next ; -+} -+ -+/******************************************************************************* -+ ** -+ ** gckDEBUGFS_SetCurrentNode -+ ** -+ ** -+ ** INPUT: -+ ** -+ ** OUTPUT: -+ ** -+ *******************************************************************************/ -+void -+gckDEBUGFS_SetCurrentNode ( -+ IN gcsDEBUGFS_Node * Node -+ ) -+{ -+ gc_dbgfs.currentNode = Node ; -+} -+ -+/******************************************************************************* -+ ** -+ ** gckDEBUGFS_GetCurrentNode -+ ** -+ ** -+ ** INPUT: -+ ** -+ ** OUTPUT: -+ ** -+ *******************************************************************************/ -+void -+gckDEBUGFS_GetCurrentNode ( -+ OUT gcsDEBUGFS_Node ** Node -+ ) -+{ -+ *Node = gc_dbgfs.currentNode ; -+} -+ -+/******************************************************************************* -+ ** -+ ** gckDEBUGFS_Print -+ ** -+ ** -+ ** INPUT: -+ ** -+ ** OUTPUT: -+ ** -+ *******************************************************************************/ -+ssize_t -+gckDEBUGFS_Print ( -+ IN gctCONST_STRING Message , -+ ... -+ ) -+{ -+ ssize_t _debugfs_res; -+ gcmkDEBUGFS_PRINT ( _GetArgumentSize ( Message ) , Message ) ; -+ return _debugfs_res; -+} -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_debugfs.h linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_debugfs.h ---- linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_debugfs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_debugfs.h 2015-11-30 17:56:13.572138258 +0100 -@@ -0,0 +1,135 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#include -+ -+#ifndef __gc_hal_kernel_debugfs_h_ -+#define __gc_hal_kernel_debugfs_h_ -+ -+ #define MAX_LINE_SIZE 768 /* Max bytes for a line of debug info */ -+ -+ -+ typedef struct _gcsDEBUGFS_Node gcsDEBUGFS_Node; -+ -+typedef struct _gcsDEBUGFS_DIR *gckDEBUGFS_DIR; -+typedef struct _gcsDEBUGFS_DIR -+{ -+ struct dentry * root; -+ struct list_head nodeList; -+} -+gcsDEBUGFS_DIR; -+ -+typedef struct _gcsINFO -+{ -+ const char * name; -+ int (*show)(struct seq_file*, void*); -+} -+gcsINFO; -+ -+typedef struct _gcsINFO_NODE -+{ -+ gcsINFO * info; -+ gctPOINTER device; -+ struct dentry * entry; -+ struct list_head head; -+} -+gcsINFO_NODE; -+ -+gceSTATUS -+gckDEBUGFS_DIR_Init( -+ IN gckDEBUGFS_DIR Dir, -+ IN struct dentry *root, -+ IN gctCONST_STRING Name -+ ); -+ -+gceSTATUS -+gckDEBUGFS_DIR_CreateFiles( -+ IN gckDEBUGFS_DIR Dir, -+ IN gcsINFO * List, -+ IN int count, -+ IN gctPOINTER Data -+ ); -+ -+gceSTATUS -+gckDEBUGFS_DIR_RemoveFiles( -+ IN gckDEBUGFS_DIR Dir, -+ IN gcsINFO * List, -+ IN int count -+ ); -+ -+void -+gckDEBUGFS_DIR_Deinit( -+ IN gckDEBUGFS_DIR Dir -+ ); -+ -+/******************************************************************************* -+ ** -+ ** System Related -+ ** -+ *******************************************************************************/ -+ -+gctINT gckDEBUGFS_IsEnabled(void); -+ -+gctINT gckDEBUGFS_Initialize(void); -+ -+gctINT gckDEBUGFS_Terminate(void); -+ -+ -+/******************************************************************************* -+ ** -+ ** Node Related -+ ** -+ *******************************************************************************/ -+ -+gctINT -+gckDEBUGFS_CreateNode( -+ IN gctPOINTER Device, -+ IN gctINT SizeInKB, -+ IN struct dentry * Root, -+ IN gctCONST_STRING NodeName, -+ OUT gcsDEBUGFS_Node **Node -+ ); -+ -+void gckDEBUGFS_FreeNode( -+ IN gcsDEBUGFS_Node * Node -+ ); -+ -+ -+ -+void gckDEBUGFS_SetCurrentNode( -+ IN gcsDEBUGFS_Node * Node -+ ); -+ -+ -+ -+void gckDEBUGFS_GetCurrentNode( -+ OUT gcsDEBUGFS_Node ** Node -+ ); -+ -+ -+ssize_t gckDEBUGFS_Print( -+ IN gctCONST_STRING Message, -+ ... -+ ); -+ -+#endif -+ -+ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_debug.h linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_debug.h ---- linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_debug.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_debug.h 2015-11-30 17:56:13.572138258 +0100 -@@ -0,0 +1,103 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#ifndef __gc_hal_kernel_debug_h_ -+#define __gc_hal_kernel_debug_h_ -+ -+#include -+#include -+#include -+#include -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+/******************************************************************************\ -+****************************** OS-dependent Macros ***************************** -+\******************************************************************************/ -+ -+typedef va_list gctARGUMENTS; -+ -+#define gcmkARGUMENTS_START(Arguments, Pointer) \ -+ va_start(Arguments, Pointer) -+ -+#define gcmkARGUMENTS_END(Arguments) \ -+ va_end(Arguments) -+ -+#define gcmkARGUMENTS_ARG(Arguments, Type) \ -+ va_arg(Arguments, Type) -+ -+#define gcmkDECLARE_LOCK(__spinLock__) \ -+ static DEFINE_SPINLOCK(__spinLock__); \ -+ unsigned long __spinLock__##flags = 0; -+ -+#define gcmkLOCKSECTION(__spinLock__) \ -+ spin_lock_irqsave(&__spinLock__, __spinLock__##flags) -+ -+#define gcmkUNLOCKSECTION(__spinLock__) \ -+ spin_unlock_irqrestore(&__spinLock__, __spinLock__##flags) -+ -+# define gcmkGETPROCESSID() \ -+ task_tgid_vnr(current) -+ -+# define gcmkGETTHREADID() \ -+ task_pid_vnr(current) -+ -+#define gcmkOUTPUT_STRING(String) \ -+ if(gckDEBUGFS_IsEnabled()) {\ -+ while(-ERESTARTSYS == gckDEBUGFS_Print(String));\ -+ }else{\ -+ printk(String); \ -+ }\ -+ touch_softlockup_watchdog() -+ -+ -+#define gcmkSPRINTF(Destination, Size, Message, Value) \ -+ snprintf(Destination, Size, Message, Value) -+ -+#define gcmkSPRINTF2(Destination, Size, Message, Value1, Value2) \ -+ snprintf(Destination, Size, Message, Value1, Value2) -+ -+#define gcmkSPRINTF3(Destination, Size, Message, Value1, Value2, Value3) \ -+ snprintf(Destination, Size, Message, Value1, Value2, Value3) -+ -+#define gcmkVSPRINTF(Destination, Size, Message, Arguments) \ -+ vsnprintf(Destination, Size, Message, *((va_list*)Arguments)) -+ -+#define gcmkSTRCAT(Destination, Size, String) \ -+ strncat(Destination, String, Size) -+ -+#define gcmkMEMCPY(Destination, Source, Size) \ -+ memcpy(Destination, Source, Size) -+ -+#define gcmkSTRLEN(String) \ -+ strlen(String) -+ -+/* If not zero, forces data alignment in the variable argument list -+ by its individual size. */ -+#define gcdALIGNBYSIZE 1 -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* __gc_hal_kernel_debug_h_ */ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_device.c linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_device.c ---- linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_device.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_device.c 2015-11-30 17:56:13.576137991 +0100 -@@ -0,0 +1,1938 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#include "gc_hal_kernel_linux.h" -+#include -+#include -+#include -+#include -+ -+#define _GC_OBJ_ZONE gcvZONE_DEVICE -+ -+#define DEBUG_FILE "galcore_trace" -+#define PARENT_FILE "gpu" -+ -+gckKERNEL -+_GetValidKernel( -+ gckGALDEVICE Device -+ ) -+{ -+ if (Device->kernels[gcvCORE_MAJOR]) -+ { -+ return Device->kernels[gcvCORE_MAJOR]; -+ } -+ else -+ if (Device->kernels[gcvCORE_2D]) -+ { -+ return Device->kernels[gcvCORE_2D]; -+ } -+ else -+ if (Device->kernels[gcvCORE_VG]) -+ { -+ return Device->kernels[gcvCORE_VG]; -+ } -+ else -+ { -+ return gcvNULL; -+ } -+} -+ -+/******************************************************************************\ -+******************************** Debugfs Support ******************************* -+\******************************************************************************/ -+ -+/******************************************************************************\ -+***************************** DEBUG SHOW FUNCTIONS ***************************** -+\******************************************************************************/ -+ -+int gc_info_show(struct seq_file* m, void* data) -+{ -+ gcsINFO_NODE *node = m->private; -+ gckGALDEVICE device = node->device; -+ int i = 0; -+ gceCHIPMODEL chipModel; -+ gctUINT32 chipRevision; -+ -+ for (i = 0; i < gcdMAX_GPU_COUNT; i++) -+ { -+ if (device->irqLines[i] != -1) -+ { -+#if gcdENABLE_VG -+ if (i == gcvCORE_VG) -+ { -+ chipModel = device->kernels[i]->vg->hardware->chipModel; -+ chipRevision = device->kernels[i]->vg->hardware->chipRevision; -+ } -+ else -+#endif -+ { -+ chipModel = device->kernels[i]->hardware->identity.chipModel; -+ chipRevision = device->kernels[i]->hardware->identity.chipRevision; -+ } -+ -+ seq_printf(m, "gpu : %d\n", i); -+ seq_printf(m, "model : %4x\n", chipModel); -+ seq_printf(m, "revision : %4x\n", chipRevision); -+ seq_printf(m, "\n"); -+ } -+ } -+ -+ return 0; -+} -+ -+int gc_clients_show(struct seq_file* m, void* data) -+{ -+ gcsINFO_NODE *node = m->private; -+ gckGALDEVICE device = node->device; -+ -+ gckKERNEL kernel = _GetValidKernel(device); -+ -+ gcsDATABASE_PTR database; -+ gctINT i, pid; -+ gctUINT8 name[24]; -+ -+ seq_printf(m, "%-8s%s\n", "PID", "NAME"); -+ seq_printf(m, "------------------------\n"); -+ -+ /* Acquire the database mutex. */ -+ gcmkVERIFY_OK( -+ gckOS_AcquireMutex(kernel->os, kernel->db->dbMutex, gcvINFINITE)); -+ -+ /* Walk the databases. */ -+ for (i = 0; i < gcmCOUNTOF(kernel->db->db); ++i) -+ { -+ for (database = kernel->db->db[i]; -+ database != gcvNULL; -+ database = database->next) -+ { -+ pid = database->processID; -+ -+ gcmkVERIFY_OK(gckOS_ZeroMemory(name, gcmSIZEOF(name))); -+ -+ gcmkVERIFY_OK(gckOS_GetProcessNameByPid(pid, gcmSIZEOF(name), name)); -+ -+ seq_printf(m, "%-8d%s\n", pid, name); -+ } -+ } -+ -+ /* Release the database mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(kernel->os, kernel->db->dbMutex)); -+ -+ /* Success. */ -+ return 0; -+} -+ -+static void -+_CounterAdd( -+ gcsDATABASE_COUNTERS * Dest, -+ gcsDATABASE_COUNTERS * Src -+ ) -+{ -+ Dest->bytes += Src->bytes; -+ Dest->maxBytes += Src->maxBytes; -+ Dest->totalBytes += Src->totalBytes; -+} -+ -+static void -+_CounterPrint( -+ gcsDATABASE_COUNTERS * Counter, -+ gctCONST_STRING Name, -+ struct seq_file* m -+ ) -+{ -+ seq_printf(m, " %s:\n", Name); -+ seq_printf(m, " Used : %10llu B\n", Counter->bytes); -+} -+ -+int gc_meminfo_show(struct seq_file* m, void* data) -+{ -+ gcsINFO_NODE *node = m->private; -+ gckGALDEVICE device = node->device; -+ gckKERNEL kernel = _GetValidKernel(device); -+ gckVIDMEM memory; -+ gceSTATUS status; -+ gcsDATABASE_PTR database; -+ gctUINT32 i; -+ -+ gctUINT32 free = 0, used = 0, total = 0; -+ -+ gcsDATABASE_COUNTERS contiguousCounter = {0, 0, 0}; -+ gcsDATABASE_COUNTERS virtualCounter = {0, 0, 0}; -+ gcsDATABASE_COUNTERS nonPagedCounter = {0, 0, 0}; -+ -+ status = gckKERNEL_GetVideoMemoryPool(kernel, gcvPOOL_SYSTEM, &memory); -+ -+ if (gcmIS_SUCCESS(status)) -+ { -+ gcmkVERIFY_OK( -+ gckOS_AcquireMutex(memory->os, memory->mutex, gcvINFINITE)); -+ -+ free = memory->freeBytes; -+ used = memory->bytes - memory->freeBytes; -+ total = memory->bytes; -+ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(memory->os, memory->mutex)); -+ } -+ -+ seq_printf(m, "VIDEO MEMORY:\n"); -+ seq_printf(m, " gcvPOOL_SYSTEM:\n"); -+ seq_printf(m, " Free : %10u B\n", free); -+ seq_printf(m, " Used : %10u B\n", used); -+ seq_printf(m, " Total : %10u B\n", total); -+ -+ /* Acquire the database mutex. */ -+ gcmkVERIFY_OK( -+ gckOS_AcquireMutex(kernel->os, kernel->db->dbMutex, gcvINFINITE)); -+ -+ /* Walk the databases. */ -+ for (i = 0; i < gcmCOUNTOF(kernel->db->db); ++i) -+ { -+ for (database = kernel->db->db[i]; -+ database != gcvNULL; -+ database = database->next) -+ { -+ gcsDATABASE_COUNTERS * counter = &database->vidMemPool[gcvPOOL_CONTIGUOUS]; -+ _CounterAdd(&contiguousCounter, counter); -+ -+ counter = &database->vidMemPool[gcvPOOL_VIRTUAL]; -+ _CounterAdd(&virtualCounter, counter); -+ -+ -+ counter = &database->nonPaged; -+ _CounterAdd(&nonPagedCounter, counter); -+ } -+ } -+ -+ /* Release the database mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(kernel->os, kernel->db->dbMutex)); -+ -+ _CounterPrint(&contiguousCounter, "gcvPOOL_CONTIGUOUS", m); -+ _CounterPrint(&virtualCounter, "gcvPOOL_VIRTUAL", m); -+ -+ seq_printf(m, "\n"); -+ -+ seq_printf(m, "NON PAGED MEMORY:\n"); -+ seq_printf(m, " Used : %10llu B\n", nonPagedCounter.bytes); -+ -+ return 0; -+} -+ -+static int -+_ShowRecord( -+ IN struct seq_file *file, -+ IN gcsDATABASE_RECORD_PTR record -+ ) -+{ -+ seq_printf(file, "%4d%8d%16p%16p%16zu\n", -+ record->type, -+ record->kernel->core, -+ record->data, -+ record->physical, -+ record->bytes -+ ); -+ -+ return 0; -+} -+ -+static int -+_ShowRecords( -+ IN struct seq_file *File, -+ IN gcsDATABASE_PTR Database -+ ) -+{ -+ gctUINT i; -+ -+ seq_printf(File, "Records:\n"); -+ -+ seq_printf(File, "%s%8s%16s%16s%16s\n", -+ "Type", "GPU", "Data", "Physical", "Bytes"); -+ -+ for (i = 0; i < gcmCOUNTOF(Database->list); i++) -+ { -+ gcsDATABASE_RECORD_PTR record = Database->list[i]; -+ -+ while (record != NULL) -+ { -+ _ShowRecord(File, record); -+ record = record->next; -+ } -+ } -+ -+ return 0; -+} -+ -+void -+_ShowCounters( -+ struct seq_file *File, -+ gcsDATABASE_PTR Database -+ ); -+ -+static void -+_ShowProcess( -+ IN struct seq_file *File, -+ IN gcsDATABASE_PTR Database -+ ) -+{ -+ gctINT pid; -+ gctUINT8 name[24]; -+ -+ /* Process ID and name */ -+ pid = Database->processID; -+ gcmkVERIFY_OK(gckOS_ZeroMemory(name, gcmSIZEOF(name))); -+ gcmkVERIFY_OK(gckOS_GetProcessNameByPid(pid, gcmSIZEOF(name), name)); -+ -+ seq_printf(File, "--------------------------------------------------------------------------------\n"); -+ seq_printf(File, "Process: %-8d %s\n", pid, name); -+ -+ /* Detailed records */ -+ _ShowRecords(File, Database); -+ -+ seq_printf(File, "Counters:\n"); -+ -+ _ShowCounters(File, Database); -+} -+ -+static void -+_ShowProcesses( -+ IN struct seq_file * file, -+ IN gckKERNEL Kernel -+ ) -+{ -+ gcsDATABASE_PTR database; -+ gctINT i; -+ -+ /* Acquire the database mutex. */ -+ gcmkVERIFY_OK( -+ gckOS_AcquireMutex(Kernel->os, Kernel->db->dbMutex, gcvINFINITE)); -+ -+ /* Idle time since last call */ -+ seq_printf(file, "GPU Idle: %llu ns\n", Kernel->db->idleTime); -+ Kernel->db->idleTime = 0; -+ -+ /* Walk the databases. */ -+ for (i = 0; i < gcmCOUNTOF(Kernel->db->db); ++i) -+ { -+ for (database = Kernel->db->db[i]; -+ database != gcvNULL; -+ database = database->next) -+ { -+ _ShowProcess(file, database); -+ } -+ } -+ -+ /* Release the database mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Kernel->db->dbMutex)); -+} -+ -+static int -+gc_db_show(struct seq_file *m, void *data) -+{ -+ gcsINFO_NODE *node = m->private; -+ gckGALDEVICE device = node->device; -+ gckKERNEL kernel = _GetValidKernel(device); -+ _ShowProcesses(m, kernel); -+ return 0 ; -+} -+ -+static int -+gc_version_show(struct seq_file *m, void *data) -+{ -+ seq_printf(m, "%s\n", gcvVERSION_STRING); -+ -+ return 0 ; -+} -+ -+int gc_idle_show(struct seq_file* m, void* data) -+{ -+ gcsINFO_NODE *node = m->private; -+ gckGALDEVICE device = node->device; -+ gckKERNEL kernel = _GetValidKernel(device); -+ gcuDATABASE_INFO info; -+ -+ gckKERNEL_QueryProcessDB(kernel, 0, gcvFALSE, gcvDB_IDLE, &info); -+ -+ seq_printf(m, "GPU idle time since last query: %llu ns\n", info.time); -+ -+ return 0; -+} -+ -+static gcsINFO InfoList[] = -+{ -+ {"info", gc_info_show}, -+ {"clients", gc_clients_show}, -+ {"meminfo", gc_meminfo_show}, -+ {"idle", gc_idle_show}, -+ {"database", gc_db_show}, -+ {"version", gc_version_show}, -+}; -+ -+static gceSTATUS -+_DebugfsInit( -+ IN gckGALDEVICE Device -+ ) -+{ -+ gceSTATUS status; -+ -+ gckDEBUGFS_DIR dir = &Device->debugfsDir; -+ -+ gcmkONERROR(gckDEBUGFS_DIR_Init(dir, gcvNULL, "gc")); -+ -+ gcmkONERROR(gckDEBUGFS_DIR_CreateFiles(dir, InfoList, gcmCOUNTOF(InfoList), Device)); -+ -+ return gcvSTATUS_OK; -+ -+OnError: -+ return status; -+} -+ -+static void -+_DebugfsCleanup( -+ IN gckGALDEVICE Device -+ ) -+{ -+ gckDEBUGFS_DIR dir = &Device->debugfsDir; -+ -+ if (Device->debugfsDir.root) -+ { -+ gcmkVERIFY_OK(gckDEBUGFS_DIR_RemoveFiles(dir, InfoList, gcmCOUNTOF(InfoList))); -+ -+ gckDEBUGFS_DIR_Deinit(dir); -+ } -+} -+ -+ -+/******************************************************************************\ -+*************************** Memory Allocation Wrappers ************************* -+\******************************************************************************/ -+ -+static gceSTATUS -+_AllocateMemory( -+ IN gckGALDEVICE Device, -+ IN gctSIZE_T Bytes, -+ OUT gctPOINTER *Logical, -+ OUT gctPHYS_ADDR *Physical, -+ OUT gctUINT32 *PhysAddr -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Device=0x%x Bytes=%lu", Device, Bytes); -+ -+ gcmkVERIFY_ARGUMENT(Device != NULL); -+ gcmkVERIFY_ARGUMENT(Logical != NULL); -+ gcmkVERIFY_ARGUMENT(Physical != NULL); -+ gcmkVERIFY_ARGUMENT(PhysAddr != NULL); -+ -+ gcmkONERROR(gckOS_AllocateContiguous( -+ Device->os, gcvFALSE, &Bytes, Physical, Logical -+ )); -+ -+ *PhysAddr = ((PLINUX_MDL)*Physical)->dmaHandle; -+ -+ /* Success. */ -+ gcmkFOOTER_ARG( -+ "*Logical=0x%x *Physical=0x%x *PhysAddr=0x%08x", -+ *Logical, *Physical, *PhysAddr -+ ); -+ -+ return gcvSTATUS_OK; -+ -+OnError: -+ gcmkFOOTER(); -+ return status; -+} -+ -+static gceSTATUS -+_FreeMemory( -+ IN gckGALDEVICE Device, -+ IN gctPOINTER Logical, -+ IN gctPHYS_ADDR Physical) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Device=0x%x Logical=0x%x Physical=0x%x", -+ Device, Logical, Physical); -+ -+ gcmkVERIFY_ARGUMENT(Device != NULL); -+ -+ status = gckOS_FreeContiguous( -+ Device->os, Physical, Logical, -+ ((PLINUX_MDL) Physical)->numPages * PAGE_SIZE -+ ); -+ -+ gcmkFOOTER(); -+ return status; -+} -+ -+ -+ -+/******************************************************************************\ -+******************************* Interrupt Handler ****************************** -+\******************************************************************************/ -+static irqreturn_t isrRoutine(int irq, void *ctxt) -+{ -+ gceSTATUS status; -+ gckGALDEVICE device; -+ -+ device = (gckGALDEVICE) ctxt; -+ -+ /* Call kernel interrupt notification. */ -+ status = gckKERNEL_Notify(device->kernels[gcvCORE_MAJOR], gcvNOTIFY_INTERRUPT, gcvTRUE); -+ -+ if (gcmIS_SUCCESS(status)) -+ { -+ up(&device->semas[gcvCORE_MAJOR]); -+ -+ return IRQ_HANDLED; -+ } -+ -+ return IRQ_NONE; -+} -+ -+static int threadRoutine(void *ctxt) -+{ -+ gckGALDEVICE device = (gckGALDEVICE) ctxt; -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER, -+ "Starting isr Thread with extension=%p", -+ device); -+ -+ for (;;) -+ { -+ static int down; -+ -+ down = down_interruptible(&device->semas[gcvCORE_MAJOR]); -+ if (down); /*To make gcc 4.6 happye*/ -+ -+ if (device->killThread == gcvTRUE) -+ { -+ /* The daemon exits. */ -+ while (!kthread_should_stop()) -+ { -+ gckOS_Delay(device->os, 1); -+ } -+ -+ return 0; -+ } -+ -+ gckKERNEL_Notify(device->kernels[gcvCORE_MAJOR], -+ gcvNOTIFY_INTERRUPT, -+ gcvFALSE); -+ } -+} -+ -+static irqreturn_t isrRoutine2D(int irq, void *ctxt) -+{ -+ gceSTATUS status; -+ gckGALDEVICE device; -+ -+ device = (gckGALDEVICE) ctxt; -+ -+ /* Call kernel interrupt notification. */ -+ status = gckKERNEL_Notify(device->kernels[gcvCORE_2D], -+ gcvNOTIFY_INTERRUPT, -+ gcvTRUE); -+ if (gcmIS_SUCCESS(status)) -+ { -+ up(&device->semas[gcvCORE_2D]); -+ -+ return IRQ_HANDLED; -+ } -+ -+ return IRQ_NONE; -+} -+ -+static int threadRoutine2D(void *ctxt) -+{ -+ gckGALDEVICE device = (gckGALDEVICE) ctxt; -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER, -+ "Starting isr Thread with extension=%p", -+ device); -+ -+ for (;;) -+ { -+ static int down; -+ -+ down = down_interruptible(&device->semas[gcvCORE_2D]); -+ if (down); /*To make gcc 4.6 happye*/ -+ -+ if (device->killThread == gcvTRUE) -+ { -+ /* The daemon exits. */ -+ while (!kthread_should_stop()) -+ { -+ gckOS_Delay(device->os, 1); -+ } -+ -+ return 0; -+ } -+ gckKERNEL_Notify(device->kernels[gcvCORE_2D], -+ gcvNOTIFY_INTERRUPT, -+ gcvFALSE); -+ } -+} -+ -+static irqreturn_t isrRoutineVG(int irq, void *ctxt) -+{ -+#if gcdENABLE_VG -+ gceSTATUS status; -+ gckGALDEVICE device; -+ -+ device = (gckGALDEVICE) ctxt; -+ -+ /* Serve the interrupt. */ -+ status = gckVGINTERRUPT_Enque(device->kernels[gcvCORE_VG]->vg->interrupt); -+ -+ /* Determine the return value. */ -+ return (status == gcvSTATUS_NOT_OUR_INTERRUPT) -+ ? IRQ_RETVAL(0) -+ : IRQ_RETVAL(1); -+#else -+ return IRQ_NONE; -+#endif -+} -+ -+static int threadRoutineVG(void *ctxt) -+{ -+ gckGALDEVICE device = (gckGALDEVICE) ctxt; -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_DRIVER, -+ "Starting isr Thread with extension=%p", -+ device); -+ -+ for (;;) -+ { -+ static int down; -+ -+ down = down_interruptible(&device->semas[gcvCORE_VG]); -+ if (down); /*To make gcc 4.6 happye*/ -+ -+ if (device->killThread == gcvTRUE) -+ { -+ /* The daemon exits. */ -+ while (!kthread_should_stop()) -+ { -+ gckOS_Delay(device->os, 1); -+ } -+ -+ return 0; -+ } -+ gckKERNEL_Notify(device->kernels[gcvCORE_VG], -+ gcvNOTIFY_INTERRUPT, -+ gcvFALSE); -+ } -+} -+ -+/******************************************************************************\ -+******************************* gckGALDEVICE Code ****************************** -+\******************************************************************************/ -+ -+/******************************************************************************* -+** -+** gckGALDEVICE_Construct -+** -+** Constructor. -+** -+** INPUT: -+** -+** OUTPUT: -+** -+** gckGALDEVICE * Device -+** Pointer to a variable receiving the gckGALDEVICE object pointer on -+** success. -+*/ -+gceSTATUS -+gckGALDEVICE_Construct( -+ IN gctINT IrqLine, -+ IN gctUINT32 RegisterMemBase, -+ IN gctSIZE_T RegisterMemSize, -+ IN gctINT IrqLine2D, -+ IN gctUINT32 RegisterMemBase2D, -+ IN gctSIZE_T RegisterMemSize2D, -+ IN gctINT IrqLineVG, -+ IN gctUINT32 RegisterMemBaseVG, -+ IN gctSIZE_T RegisterMemSizeVG, -+ IN gctUINT32 ContiguousBase, -+ IN gctSIZE_T ContiguousSize, -+ IN gctSIZE_T BankSize, -+ IN gctINT FastClear, -+ IN gctINT Compression, -+ IN gctUINT32 PhysBaseAddr, -+ IN gctUINT32 PhysSize, -+ IN gctINT Signal, -+ IN gctUINT LogFileSize, -+ IN gctINT PowerManagement, -+ IN gctINT GpuProfiler, -+ IN gcsDEVICE_CONSTRUCT_ARGS * Args, -+ OUT gckGALDEVICE *Device -+ ) -+{ -+ gctUINT32 internalBaseAddress = 0, internalAlignment = 0; -+ gctUINT32 externalBaseAddress = 0, externalAlignment = 0; -+ gctUINT32 horizontalTileSize, verticalTileSize; -+ struct resource* mem_region; -+ gctUINT32 physAddr; -+ gctUINT32 physical; -+ gckGALDEVICE device; -+ gceSTATUS status; -+ gctINT32 i; -+ gceHARDWARE_TYPE type; -+ gckDB sharedDB = gcvNULL; -+ gckKERNEL kernel = gcvNULL; -+ -+ gcmkHEADER_ARG("IrqLine=%d RegisterMemBase=0x%08x RegisterMemSize=%u " -+ "IrqLine2D=%d RegisterMemBase2D=0x%08x RegisterMemSize2D=%u " -+ "IrqLineVG=%d RegisterMemBaseVG=0x%08x RegisterMemSizeVG=%u " -+ "ContiguousBase=0x%08x ContiguousSize=%lu BankSize=%lu " -+ "FastClear=%d Compression=%d PhysBaseAddr=0x%x PhysSize=%d Signal=%d", -+ IrqLine, RegisterMemBase, RegisterMemSize, -+ IrqLine2D, RegisterMemBase2D, RegisterMemSize2D, -+ IrqLineVG, RegisterMemBaseVG, RegisterMemSizeVG, -+ ContiguousBase, ContiguousSize, BankSize, FastClear, Compression, -+ PhysBaseAddr, PhysSize, Signal); -+ -+#if gcdDISABLE_CORES_2D3D -+ IrqLine = -1; -+ IrqLine2D = -1; -+#endif -+ -+ /* Allocate device structure. */ -+ device = kmalloc(sizeof(struct _gckGALDEVICE), GFP_KERNEL | __GFP_NOWARN); -+ -+ if (!device) -+ { -+ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); -+ } -+ -+ memset(device, 0, sizeof(struct _gckGALDEVICE)); -+ -+ device->dbgNode = gcvNULL; -+ -+ device->platform = Args->platform; -+ -+ gcmkONERROR(_DebugfsInit(device)); -+ -+ if (gckDEBUGFS_CreateNode( -+ device, LogFileSize, device->debugfsDir.root ,DEBUG_FILE, &(device->dbgNode))) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_DRIVER, -+ "%s(%d): Failed to create the debug file system %s/%s \n", -+ __FUNCTION__, __LINE__, -+ PARENT_FILE, DEBUG_FILE -+ ); -+ } -+ else if (LogFileSize) -+ { -+ gckDEBUGFS_SetCurrentNode(device->dbgNode); -+ } -+ -+ if (IrqLine != -1) -+ { -+ device->requestedRegisterMemBases[gcvCORE_MAJOR] = RegisterMemBase; -+ device->requestedRegisterMemSizes[gcvCORE_MAJOR] = RegisterMemSize; -+ } -+ -+ if (IrqLine2D != -1) -+ { -+ device->requestedRegisterMemBases[gcvCORE_2D] = RegisterMemBase2D; -+ device->requestedRegisterMemSizes[gcvCORE_2D] = RegisterMemSize2D; -+ } -+ -+ if (IrqLineVG != -1) -+ { -+ device->requestedRegisterMemBases[gcvCORE_VG] = RegisterMemBaseVG; -+ device->requestedRegisterMemSizes[gcvCORE_VG] = RegisterMemSizeVG; -+ } -+ -+ device->requestedContiguousBase = 0; -+ device->requestedContiguousSize = 0; -+ -+ for (i = 0; i < gcdMAX_GPU_COUNT; i++) -+ { -+ physical = device->requestedRegisterMemBases[i]; -+ -+ /* Set up register memory region. */ -+ if (physical != 0) -+ { -+ mem_region = request_mem_region(physical, -+ device->requestedRegisterMemSizes[i], -+ "galcore register region"); -+ -+ if (mem_region == gcvNULL) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_DRIVER, -+ "%s(%d): Failed to claim %lu bytes @ 0x%08X\n", -+ __FUNCTION__, __LINE__, -+ physical, device->requestedRegisterMemSizes[i] -+ ); -+ -+ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES); -+ } -+ -+ device->registerBases[i] = (gctPOINTER) ioremap_nocache( -+ physical, device->requestedRegisterMemSizes[i]); -+ -+ if (device->registerBases[i] == gcvNULL) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_DRIVER, -+ "%s(%d): Unable to map %ld bytes @ 0x%08X\n", -+ __FUNCTION__, __LINE__, -+ physical, device->requestedRegisterMemSizes[i] -+ ); -+ -+ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES); -+ } -+ -+ physical += device->requestedRegisterMemSizes[i]; -+ } -+ } -+ -+ /* Set the base address */ -+ device->baseAddress = device->physBase = PhysBaseAddr; -+ device->physSize = PhysSize; -+ device->mmu = Args->mmu; -+ -+ /* Construct the gckOS object. */ -+ gcmkONERROR(gckOS_Construct(device, &device->os)); -+ -+ if (IrqLine != -1) -+ { -+ /* Construct the gckKERNEL object. */ -+ gcmkONERROR(gckKERNEL_Construct( -+ device->os, gcvCORE_MAJOR, device, -+ gcvNULL, &device->kernels[gcvCORE_MAJOR])); -+ -+ sharedDB = device->kernels[gcvCORE_MAJOR]->db; -+ -+ /* Initialize core mapping */ -+ for (i = 0; i < 8; i++) -+ { -+ device->coreMapping[i] = gcvCORE_MAJOR; -+ } -+ -+ /* Setup the ISR manager. */ -+ gcmkONERROR(gckHARDWARE_SetIsrManager( -+ device->kernels[gcvCORE_MAJOR]->hardware, -+ (gctISRMANAGERFUNC) gckGALDEVICE_Enable_ISR, -+ (gctISRMANAGERFUNC) gckGALDEVICE_Disable_ISR, -+ device -+ )); -+ -+ gcmkONERROR(gckHARDWARE_SetFastClear( -+ device->kernels[gcvCORE_MAJOR]->hardware, FastClear, Compression -+ )); -+ -+ if(PowerManagement != -1) -+ { -+ gcmkONERROR(gckHARDWARE_SetPowerManagementLock( -+ device->kernels[gcvCORE_MAJOR]->hardware, gcvFALSE -+ )); -+ gcmkONERROR(gckHARDWARE_SetPowerManagement( -+ device->kernels[gcvCORE_MAJOR]->hardware, PowerManagement -+ )); -+ gcmkONERROR(gckHARDWARE_SetPowerManagementLock( -+ device->kernels[gcvCORE_MAJOR]->hardware, gcvTRUE -+ )); -+ } -+ else -+ { -+ gcmkONERROR(gckHARDWARE_SetPowerManagementLock( -+ device->kernels[gcvCORE_MAJOR]->hardware, gcvFALSE -+ )); -+ gcmkONERROR(gckHARDWARE_SetPowerManagement( -+ device->kernels[gcvCORE_MAJOR]->hardware, gcvTRUE -+ )); -+ } -+ -+#if gcdENABLE_FSCALE_VAL_ADJUST -+ gcmkONERROR(gckHARDWARE_SetMinFscaleValue( -+ device->kernels[gcvCORE_MAJOR]->hardware, Args->gpu3DMinClock -+ )); -+#endif -+ -+ gcmkONERROR(gckHARDWARE_SetGpuProfiler( -+ device->kernels[gcvCORE_MAJOR]->hardware, GpuProfiler -+ )); -+ -+ gcmkVERIFY_OK(gckKERNEL_SetRecovery( -+ device->kernels[gcvCORE_MAJOR], Args->recovery, Args->stuckDump -+ )); -+ -+ /* Start the command queue. */ -+ gcmkONERROR(gckCOMMAND_Start(device->kernels[gcvCORE_MAJOR]->command)); -+ } -+ else -+ { -+ device->kernels[gcvCORE_MAJOR] = gcvNULL; -+ } -+ -+ if (IrqLine2D != -1) -+ { -+ gcmkONERROR(gckKERNEL_Construct( -+ device->os, gcvCORE_2D, device, -+ sharedDB, &device->kernels[gcvCORE_2D])); -+ -+ if (sharedDB == gcvNULL) sharedDB = device->kernels[gcvCORE_2D]->db; -+ -+ /* Verify the hardware type */ -+ gcmkONERROR(gckHARDWARE_GetType(device->kernels[gcvCORE_2D]->hardware, &type)); -+ -+ if (type != gcvHARDWARE_2D) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_DRIVER, -+ "%s(%d): Unexpected hardware type: %d\n", -+ __FUNCTION__, __LINE__, -+ type -+ ); -+ -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ } -+ -+ /* Initialize core mapping */ -+ if (device->kernels[gcvCORE_MAJOR] == gcvNULL) -+ { -+ for (i = 0; i < 8; i++) -+ { -+ device->coreMapping[i] = gcvCORE_2D; -+ } -+ } -+ else -+ { -+ device->coreMapping[gcvHARDWARE_2D] = gcvCORE_2D; -+ } -+ -+ /* Setup the ISR manager. */ -+ gcmkONERROR(gckHARDWARE_SetIsrManager( -+ device->kernels[gcvCORE_2D]->hardware, -+ (gctISRMANAGERFUNC) gckGALDEVICE_Enable_ISR, -+ (gctISRMANAGERFUNC) gckGALDEVICE_Disable_ISR, -+ device -+ )); -+ -+ if(PowerManagement != -1) -+ { -+ gcmkONERROR(gckHARDWARE_SetPowerManagementLock( -+ device->kernels[gcvCORE_2D]->hardware, gcvFALSE -+ )); -+ gcmkONERROR(gckHARDWARE_SetPowerManagement( -+ device->kernels[gcvCORE_2D]->hardware, PowerManagement -+ )); -+ gcmkONERROR(gckHARDWARE_SetPowerManagementLock( -+ device->kernels[gcvCORE_2D]->hardware, gcvTRUE -+ )); -+ } -+ else -+ { -+ gcmkONERROR(gckHARDWARE_SetPowerManagementLock( -+ device->kernels[gcvCORE_2D]->hardware, gcvFALSE -+ )); -+ gcmkONERROR(gckHARDWARE_SetPowerManagement( -+ device->kernels[gcvCORE_2D]->hardware, gcvTRUE -+ )); -+ } -+ -+#if gcdENABLE_FSCALE_VAL_ADJUST -+ gcmkONERROR(gckHARDWARE_SetMinFscaleValue( -+ device->kernels[gcvCORE_2D]->hardware, 1 -+ )); -+#endif -+ -+ gcmkVERIFY_OK(gckKERNEL_SetRecovery( -+ device->kernels[gcvCORE_2D], Args->recovery, Args->stuckDump -+ )); -+ -+ /* Start the command queue. */ -+ gcmkONERROR(gckCOMMAND_Start(device->kernels[gcvCORE_2D]->command)); -+ } -+ else -+ { -+ device->kernels[gcvCORE_2D] = gcvNULL; -+ } -+ -+ if (IrqLineVG != -1) -+ { -+#if gcdENABLE_VG -+ gcmkONERROR(gckKERNEL_Construct( -+ device->os, gcvCORE_VG, device, -+ sharedDB, &device->kernels[gcvCORE_VG])); -+ /* Initialize core mapping */ -+ if (device->kernels[gcvCORE_MAJOR] == gcvNULL -+ && device->kernels[gcvCORE_2D] == gcvNULL -+ ) -+ { -+ for (i = 0; i < 8; i++) -+ { -+ device->coreMapping[i] = gcvCORE_VG; -+ } -+ } -+ else -+ { -+ device->coreMapping[gcvHARDWARE_VG] = gcvCORE_VG; -+ } -+ -+ if(PowerManagement != -1) -+ { -+ gcmkONERROR(gckVGHARDWARE_SetPowerManagement( -+ device->kernels[gcvCORE_VG]->vg->hardware, -+ PowerManagement -+ )); -+ } -+ else -+ { -+ gcmkONERROR(gckVGHARDWARE_SetPowerManagement( -+ device->kernels[gcvCORE_VG]->vg->hardware, -+ gcvTRUE -+ )); -+ } -+#endif -+ } -+ else -+ { -+ device->kernels[gcvCORE_VG] = gcvNULL; -+ } -+ -+ /* Initialize the ISR. */ -+ device->irqLines[gcvCORE_MAJOR] = IrqLine; -+ device->irqLines[gcvCORE_2D] = IrqLine2D; -+ device->irqLines[gcvCORE_VG] = IrqLineVG; -+ -+ /* Initialize the kernel thread semaphores. */ -+ for (i = 0; i < gcdMAX_GPU_COUNT; i++) -+ { -+ if (device->irqLines[i] != -1) sema_init(&device->semas[i], 0); -+ } -+ -+ device->signal = Signal; -+ -+ for (i = 0; i < gcdMAX_GPU_COUNT; i++) -+ { -+ if (device->kernels[i] != gcvNULL) break; -+ } -+ -+ if (i == gcdMAX_GPU_COUNT) -+ { -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ } -+ -+#if gcdENABLE_VG -+ if (i == gcvCORE_VG) -+ { -+ /* Query the ceiling of the system memory. */ -+ gcmkONERROR(gckVGHARDWARE_QuerySystemMemory( -+ device->kernels[i]->vg->hardware, -+ &device->systemMemorySize, -+ &device->systemMemoryBaseAddress -+ )); -+ /* query the amount of video memory */ -+ gcmkONERROR(gckVGHARDWARE_QueryMemory( -+ device->kernels[i]->vg->hardware, -+ &device->internalSize, &internalBaseAddress, &internalAlignment, -+ &device->externalSize, &externalBaseAddress, &externalAlignment, -+ &horizontalTileSize, &verticalTileSize -+ )); -+ } -+ else -+#endif -+ { -+ /* Query the ceiling of the system memory. */ -+ gcmkONERROR(gckHARDWARE_QuerySystemMemory( -+ device->kernels[i]->hardware, -+ &device->systemMemorySize, -+ &device->systemMemoryBaseAddress -+ )); -+ -+ /* query the amount of video memory */ -+ gcmkONERROR(gckHARDWARE_QueryMemory( -+ device->kernels[i]->hardware, -+ &device->internalSize, &internalBaseAddress, &internalAlignment, -+ &device->externalSize, &externalBaseAddress, &externalAlignment, -+ &horizontalTileSize, &verticalTileSize -+ )); -+ } -+ -+ -+ /* Grab the first availiable kernel */ -+ for (i = 0; i < gcdMAX_GPU_COUNT; i++) -+ { -+ if (device->irqLines[i] != -1) -+ { -+ kernel = device->kernels[i]; -+ break; -+ } -+ } -+ -+ /* Set up the internal memory region. */ -+ if (device->internalSize > 0) -+ { -+ status = gckVIDMEM_Construct( -+ device->os, -+ internalBaseAddress, device->internalSize, internalAlignment, -+ 0, &device->internalVidMem -+ ); -+ -+ if (gcmIS_ERROR(status)) -+ { -+ /* Error, disable internal heap. */ -+ device->internalSize = 0; -+ } -+ else -+ { -+ /* Map internal memory. */ -+ device->internalLogical -+ = (gctPOINTER) ioremap_nocache(physical, device->internalSize); -+ -+ if (device->internalLogical == gcvNULL) -+ { -+ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES); -+ } -+ -+ device->internalPhysical = (gctPHYS_ADDR)(gctUINTPTR_T) physical; -+ device->internalPhysicalName = gcmPTR_TO_NAME(device->internalPhysical); -+ physical += device->internalSize; -+ } -+ } -+ -+ if (device->externalSize > 0) -+ { -+ /* create the external memory heap */ -+ status = gckVIDMEM_Construct( -+ device->os, -+ externalBaseAddress, device->externalSize, externalAlignment, -+ 0, &device->externalVidMem -+ ); -+ -+ if (gcmIS_ERROR(status)) -+ { -+ /* Error, disable internal heap. */ -+ device->externalSize = 0; -+ } -+ else -+ { -+ /* Map external memory. */ -+ device->externalLogical -+ = (gctPOINTER) ioremap_nocache(physical, device->externalSize); -+ -+ if (device->externalLogical == gcvNULL) -+ { -+ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES); -+ } -+ -+ device->externalPhysical = (gctPHYS_ADDR)(gctUINTPTR_T) physical; -+ device->externalPhysicalName = gcmPTR_TO_NAME(device->externalPhysical); -+ physical += device->externalSize; -+ } -+ } -+ -+ /* set up the contiguous memory */ -+ device->contiguousSize = ContiguousSize; -+ -+ if (ContiguousSize > 0) -+ { -+ if (ContiguousBase == 0) -+ { -+ while (device->contiguousSize > 0) -+ { -+ /* Allocate contiguous memory. */ -+ status = _AllocateMemory( -+ device, -+ device->contiguousSize, -+ &device->contiguousBase, -+ &device->contiguousPhysical, -+ &physAddr -+ ); -+ -+ if (gcmIS_SUCCESS(status)) -+ { -+ device->contiguousPhysicalName = gcmPTR_TO_NAME(device->contiguousPhysical); -+ status = gckVIDMEM_Construct( -+ device->os, -+ physAddr | device->systemMemoryBaseAddress, -+ device->contiguousSize, -+ 64, -+ BankSize, -+ &device->contiguousVidMem -+ ); -+ -+ if (gcmIS_SUCCESS(status)) -+ { -+ break; -+ } -+ -+ gcmkONERROR(_FreeMemory( -+ device, -+ device->contiguousBase, -+ device->contiguousPhysical -+ )); -+ -+ gcmRELEASE_NAME(device->contiguousPhysicalName); -+ device->contiguousBase = gcvNULL; -+ device->contiguousPhysical = gcvNULL; -+ } -+ -+ if (device->contiguousSize <= (4 << 20)) -+ { -+ device->contiguousSize = 0; -+ } -+ else -+ { -+ device->contiguousSize -= (4 << 20); -+ } -+ } -+ } -+ else -+ { -+ /* Create the contiguous memory heap. */ -+ status = gckVIDMEM_Construct( -+ device->os, -+ ContiguousBase | device->systemMemoryBaseAddress, -+ ContiguousSize, -+ 64, BankSize, -+ &device->contiguousVidMem -+ ); -+ -+ if (gcmIS_ERROR(status)) -+ { -+ /* Error, disable contiguous memory pool. */ -+ device->contiguousVidMem = gcvNULL; -+ device->contiguousSize = 0; -+ } -+ else -+ { -+ if (Args->contiguousRequested == gcvFALSE) -+ { -+ mem_region = request_mem_region( -+ ContiguousBase, ContiguousSize, "galcore managed memory" -+ ); -+ -+ if (mem_region == gcvNULL) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_DRIVER, -+ "%s(%d): Failed to claim %ld bytes @ 0x%08X\n", -+ __FUNCTION__, __LINE__, -+ ContiguousSize, ContiguousBase -+ ); -+ -+ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES); -+ } -+ } -+ -+ device->requestedContiguousBase = ContiguousBase; -+ device->requestedContiguousSize = ContiguousSize; -+ device->contiguousRequested = Args->contiguousRequested; -+ -+ device->contiguousPhysical = gcvNULL; -+ device->contiguousPhysicalName = 0; -+ device->contiguousSize = ContiguousSize; -+ device->contiguousMapped = gcvTRUE; -+ } -+ } -+ } -+ -+ /* Return pointer to the device. */ -+ *Device = device; -+ -+ gcmkFOOTER_ARG("*Device=0x%x", * Device); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Roll back. */ -+ gcmkVERIFY_OK(gckGALDEVICE_Destroy(device)); -+ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckGALDEVICE_Destroy -+** -+** Class destructor. -+** -+** INPUT: -+** -+** Nothing. -+** -+** OUTPUT: -+** -+** Nothing. -+** -+** RETURNS: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckGALDEVICE_Destroy( -+ gckGALDEVICE Device) -+{ -+ gctINT i; -+ gckKERNEL kernel = gcvNULL; -+ -+ gcmkHEADER_ARG("Device=0x%x", Device); -+ -+ if (Device != gcvNULL) -+ { -+ /* Grab the first availiable kernel */ -+ for (i = 0; i < gcdMAX_GPU_COUNT; i++) -+ { -+ if (Device->irqLines[i] != -1) -+ { -+ kernel = Device->kernels[i]; -+ break; -+ } -+ } -+ -+ if (Device->internalPhysicalName != 0) -+ { -+ gcmRELEASE_NAME(Device->internalPhysicalName); -+ Device->internalPhysicalName = 0; -+ } -+ if (Device->externalPhysicalName != 0) -+ { -+ gcmRELEASE_NAME(Device->externalPhysicalName); -+ Device->externalPhysicalName = 0; -+ } -+ if (Device->contiguousPhysicalName != 0) -+ { -+ gcmRELEASE_NAME(Device->contiguousPhysicalName); -+ Device->contiguousPhysicalName = 0; -+ } -+ -+ -+ for (i = 0; i < gcdMAX_GPU_COUNT; i++) -+ { -+ if (Device->kernels[i] != gcvNULL) -+ { -+ /* Destroy the gckKERNEL object. */ -+ gcmkVERIFY_OK(gckKERNEL_Destroy(Device->kernels[i])); -+ Device->kernels[i] = gcvNULL; -+ } -+ } -+ -+ if (Device->internalLogical != gcvNULL) -+ { -+ /* Unmap the internal memory. */ -+ iounmap(Device->internalLogical); -+ Device->internalLogical = gcvNULL; -+ } -+ -+ if (Device->internalVidMem != gcvNULL) -+ { -+ /* Destroy the internal heap. */ -+ gcmkVERIFY_OK(gckVIDMEM_Destroy(Device->internalVidMem)); -+ Device->internalVidMem = gcvNULL; -+ } -+ -+ if (Device->externalLogical != gcvNULL) -+ { -+ /* Unmap the external memory. */ -+ iounmap(Device->externalLogical); -+ Device->externalLogical = gcvNULL; -+ } -+ -+ if (Device->externalVidMem != gcvNULL) -+ { -+ /* destroy the external heap */ -+ gcmkVERIFY_OK(gckVIDMEM_Destroy(Device->externalVidMem)); -+ Device->externalVidMem = gcvNULL; -+ } -+ -+ if (Device->contiguousBase != gcvNULL) -+ { -+ if (Device->contiguousMapped == gcvFALSE) -+ { -+ gcmkVERIFY_OK(_FreeMemory( -+ Device, -+ Device->contiguousBase, -+ Device->contiguousPhysical -+ )); -+ } -+ -+ Device->contiguousBase = gcvNULL; -+ Device->contiguousPhysical = gcvNULL; -+ } -+ -+ if (Device->requestedContiguousBase != 0 -+ && Device->contiguousRequested == gcvFALSE -+ ) -+ { -+ release_mem_region(Device->requestedContiguousBase, Device->requestedContiguousSize); -+ Device->requestedContiguousBase = 0; -+ Device->requestedContiguousSize = 0; -+ } -+ -+ if (Device->contiguousVidMem != gcvNULL) -+ { -+ /* Destroy the contiguous heap. */ -+ gcmkVERIFY_OK(gckVIDMEM_Destroy(Device->contiguousVidMem)); -+ Device->contiguousVidMem = gcvNULL; -+ } -+ -+ if (Device->dbgNode) -+ { -+ gckDEBUGFS_FreeNode(Device->dbgNode); -+ -+ if(Device->dbgNode != gcvNULL) -+ { -+ kfree(Device->dbgNode); -+ Device->dbgNode = gcvNULL; -+ } -+ } -+ -+ for (i = 0; i < gcdMAX_GPU_COUNT; i++) -+ { -+ if (Device->registerBases[i] != gcvNULL) -+ { -+ /* Unmap register memory. */ -+ iounmap(Device->registerBases[i]); -+ if (Device->requestedRegisterMemBases[i] != 0) -+ { -+ release_mem_region(Device->requestedRegisterMemBases[i], -+ Device->requestedRegisterMemSizes[i]); -+ } -+ -+ Device->registerBases[i] = gcvNULL; -+ Device->requestedRegisterMemBases[i] = 0; -+ Device->requestedRegisterMemSizes[i] = 0; -+ } -+ } -+ -+ /* Destroy the gckOS object. */ -+ if (Device->os != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckOS_Destroy(Device->os)); -+ Device->os = gcvNULL; -+ } -+ -+ _DebugfsCleanup(Device); -+ -+ /* Free the device. */ -+ kfree(Device); -+ } -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckGALDEVICE_Setup_ISR -+** -+** Start the ISR routine. -+** -+** INPUT: -+** -+** gckGALDEVICE Device -+** Pointer to an gckGALDEVICE object. -+** -+** OUTPUT: -+** -+** Nothing. -+** -+** RETURNS: -+** -+** gcvSTATUS_OK -+** Setup successfully. -+** gcvSTATUS_GENERIC_IO -+** Setup failed. -+*/ -+gceSTATUS -+gckGALDEVICE_Setup_ISR( -+ IN gckGALDEVICE Device, -+ IN gceCORE Core -+ ) -+{ -+ gceSTATUS status; -+ gctINT ret = 0; -+ -+ gcmkHEADER_ARG("Device=0x%x Core=%d", Device, Core); -+ -+ gcmkVERIFY_ARGUMENT(Device != NULL); -+ -+ if (Device->irqLines[Core] < 0) -+ { -+ gcmkONERROR(gcvSTATUS_GENERIC_IO); -+ } -+ -+ /* Hook up the isr based on the irq line. */ -+ switch (Core) { -+ case gcvCORE_MAJOR: -+ ret = request_irq( -+ Device->irqLines[Core], isrRoutine, 0, -+ "galcore interrupt service", Device -+ ); -+ break; -+ case gcvCORE_2D: -+ ret = request_irq( -+ Device->irqLines[Core], isrRoutine2D, 0, -+ "galcore 2D interrupt service", Device -+ ); -+ break; -+ case gcvCORE_VG: -+ ret = request_irq( -+ Device->irqLines[Core], isrRoutineVG, 0, -+ "galcore VG interrupt service", Device -+ ); -+ break; -+ default: -+ break; -+ } -+ -+ if (ret != 0) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_DRIVER, -+ "%s(%d): Could not register irq line %d (error=%d)\n", -+ __FUNCTION__, __LINE__, -+ Device->irqLines[gcvCORE_MAJOR], ret -+ ); -+ -+ gcmkONERROR(gcvSTATUS_GENERIC_IO); -+ } -+ -+ Device->isrEnabled[Core] = 1; -+ -+ /* Mark ISR as initialized. */ -+ Device->isrInitializeds[Core] = gcvTRUE; -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckGALDEVICE_Enable_ISR( -+ IN gckGALDEVICE Device, -+ IN gceCORE Core -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Device=0x%x Core=%d", Device, Core); -+ -+ gcmkVERIFY_ARGUMENT(Device != NULL); -+ -+ if (Device->irqLines[Core] < 0) -+ { -+ gcmkONERROR(gcvSTATUS_GENERIC_IO); -+ } -+ -+ spin_lock(&Device->kernels[Core]->irq_lock); -+ if (Device->isrEnabled[Core] == 0) -+ { -+ enable_irq(Device->irqLines[Core]); -+ /* Mark ISR as initialized. */ -+ Device->isrEnabled[Core] = gcvTRUE; -+ } -+ Device->isrEnabled[Core]++; -+ spin_unlock(&Device->kernels[Core]->irq_lock); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckGALDEVICE_Release_ISR -+** -+** Release the irq line. -+** -+** INPUT: -+** -+** gckGALDEVICE Device -+** Pointer to an gckGALDEVICE object. -+** -+** OUTPUT: -+** -+** Nothing. -+** -+** RETURNS: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckGALDEVICE_Release_ISR( -+ IN gckGALDEVICE Device, -+ IN gceCORE Core -+ ) -+{ -+ gcmkHEADER_ARG("Device=0x%x Core=%d", Device, Core); -+ -+ gcmkVERIFY_ARGUMENT(Device != NULL); -+ -+ /* release the irq */ -+ if (Device->isrInitializeds[Core]) -+ { -+ free_irq(Device->irqLines[Core], Device); -+ Device->isrInitializeds[Core] = gcvFALSE; -+ } -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckGALDEVICE_Disable_ISR( -+ IN gckGALDEVICE Device, -+ IN gceCORE Core -+ ) -+{ -+ gcmkHEADER_ARG("Device=0x%x Core=%d", Device, Core); -+ -+ gcmkVERIFY_ARGUMENT(Device != NULL); -+ -+ /* disable the irq */ -+ spin_lock(&Device->kernels[Core]->irq_lock); -+ if (Device->isrEnabled[Core] > 0) -+ { -+ Device->isrEnabled[Core]--; -+ if (Device->isrEnabled[Core] == 0) -+ disable_irq(Device->irqLines[Core]); -+ } -+ spin_unlock(&Device->kernels[Core]->irq_lock); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckGALDEVICE_Start_Threads -+** -+** Start the daemon threads. -+** -+** INPUT: -+** -+** gckGALDEVICE Device -+** Pointer to an gckGALDEVICE object. -+** -+** OUTPUT: -+** -+** Nothing. -+** -+** RETURNS: -+** -+** gcvSTATUS_OK -+** Start successfully. -+** gcvSTATUS_GENERIC_IO -+** Start failed. -+*/ -+gceSTATUS -+gckGALDEVICE_Start_Threads( -+ IN gckGALDEVICE Device -+ ) -+{ -+ gceSTATUS status; -+ struct task_struct * task; -+ -+ gcmkHEADER_ARG("Device=0x%x", Device); -+ -+ gcmkVERIFY_ARGUMENT(Device != NULL); -+ -+ if (Device->kernels[gcvCORE_MAJOR] != gcvNULL) -+ { -+ /* Start the kernel thread. */ -+ task = kthread_run(threadRoutine, Device, "galcore daemon thread"); -+ -+ if (IS_ERR(task)) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_DRIVER, -+ "%s(%d): Could not start the kernel thread.\n", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ gcmkONERROR(gcvSTATUS_GENERIC_IO); -+ } -+ -+ Device->threadCtxts[gcvCORE_MAJOR] = task; -+ Device->threadInitializeds[gcvCORE_MAJOR] = gcvTRUE; -+ } -+ -+ if (Device->kernels[gcvCORE_2D] != gcvNULL) -+ { -+ /* Start the kernel thread. */ -+ task = kthread_run(threadRoutine2D, Device, "galcore daemon thread for 2D"); -+ -+ if (IS_ERR(task)) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_DRIVER, -+ "%s(%d): Could not start the kernel thread.\n", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ gcmkONERROR(gcvSTATUS_GENERIC_IO); -+ } -+ -+ Device->threadCtxts[gcvCORE_2D] = task; -+ Device->threadInitializeds[gcvCORE_2D] = gcvTRUE; -+ } -+ else -+ { -+ Device->threadInitializeds[gcvCORE_2D] = gcvFALSE; -+ } -+ -+ if (Device->kernels[gcvCORE_VG] != gcvNULL) -+ { -+ /* Start the kernel thread. */ -+ task = kthread_run(threadRoutineVG, Device, "galcore daemon thread for VG"); -+ -+ if (IS_ERR(task)) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_DRIVER, -+ "%s(%d): Could not start the kernel thread.\n", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ gcmkONERROR(gcvSTATUS_GENERIC_IO); -+ } -+ -+ Device->threadCtxts[gcvCORE_VG] = task; -+ Device->threadInitializeds[gcvCORE_VG] = gcvTRUE; -+ } -+ else -+ { -+ Device->threadInitializeds[gcvCORE_VG] = gcvFALSE; -+ } -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckGALDEVICE_Stop_Threads -+** -+** Stop the gal device, including the following actions: stop the daemon -+** thread, release the irq. -+** -+** INPUT: -+** -+** gckGALDEVICE Device -+** Pointer to an gckGALDEVICE object. -+** -+** OUTPUT: -+** -+** Nothing. -+** -+** RETURNS: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckGALDEVICE_Stop_Threads( -+ gckGALDEVICE Device -+ ) -+{ -+ gctINT i; -+ -+ gcmkHEADER_ARG("Device=0x%x", Device); -+ -+ gcmkVERIFY_ARGUMENT(Device != NULL); -+ -+ for (i = 0; i < gcdMAX_GPU_COUNT; i++) -+ { -+ /* Stop the kernel threads. */ -+ if (Device->threadInitializeds[i]) -+ { -+ Device->killThread = gcvTRUE; -+ up(&Device->semas[i]); -+ -+ kthread_stop(Device->threadCtxts[i]); -+ Device->threadCtxts[i] = gcvNULL; -+ Device->threadInitializeds[i] = gcvFALSE; -+ } -+ } -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckGALDEVICE_Start -+** -+** Start the gal device, including the following actions: setup the isr routine -+** and start the daemoni thread. -+** -+** INPUT: -+** -+** gckGALDEVICE Device -+** Pointer to an gckGALDEVICE object. -+** -+** OUTPUT: -+** -+** Nothing. -+** -+** RETURNS: -+** -+** gcvSTATUS_OK -+** Start successfully. -+*/ -+gceSTATUS -+gckGALDEVICE_Start( -+ IN gckGALDEVICE Device -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Device=0x%x", Device); -+ -+ /* Start the kernel thread. */ -+ gcmkONERROR(gckGALDEVICE_Start_Threads(Device)); -+ -+ if (Device->kernels[gcvCORE_MAJOR] != gcvNULL) -+ { -+ /* Setup the ISR routine. */ -+ gcmkONERROR(gckGALDEVICE_Setup_ISR(Device, gcvCORE_MAJOR)); -+ -+ /* Switch to SUSPEND power state. */ -+ gcmkONERROR(gckHARDWARE_SetPowerManagementState( -+ Device->kernels[gcvCORE_MAJOR]->hardware, gcvPOWER_OFF_ATPOWERON -+ )); -+ } -+ -+ if (Device->kernels[gcvCORE_2D] != gcvNULL) -+ { -+ /* Setup the ISR routine. */ -+ gcmkONERROR(gckGALDEVICE_Setup_ISR(Device, gcvCORE_2D)); -+ -+ /* Switch to SUSPEND power state. */ -+ gcmkONERROR(gckHARDWARE_SetPowerManagementState( -+ Device->kernels[gcvCORE_2D]->hardware, gcvPOWER_OFF_ATPOWERON -+ )); -+ } -+ -+ if (Device->kernels[gcvCORE_VG] != gcvNULL) -+ { -+ /* Setup the ISR routine. */ -+ gcmkONERROR(gckGALDEVICE_Setup_ISR(Device, gcvCORE_VG)); -+ -+#if gcdENABLE_VG -+ /* Switch to SUSPEND power state. */ -+ gcmkONERROR(gckVGHARDWARE_SetPowerManagementState( -+ Device->kernels[gcvCORE_VG]->vg->hardware, gcvPOWER_OFF_ATPOWERON -+ )); -+#endif -+ } -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckGALDEVICE_Stop -+** -+** Stop the gal device, including the following actions: stop the daemon -+** thread, release the irq. -+** -+** INPUT: -+** -+** gckGALDEVICE Device -+** Pointer to an gckGALDEVICE object. -+** -+** OUTPUT: -+** -+** Nothing. -+** -+** RETURNS: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckGALDEVICE_Stop( -+ gckGALDEVICE Device -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Device=0x%x", Device); -+ -+ gcmkVERIFY_ARGUMENT(Device != NULL); -+ -+ if (Device->kernels[gcvCORE_MAJOR] != gcvNULL) -+ { -+ /* Switch to OFF power state. */ -+ gcmkONERROR(gckHARDWARE_SetPowerManagementState( -+ Device->kernels[gcvCORE_MAJOR]->hardware, gcvPOWER_OFF -+ )); -+ -+ /* Remove the ISR routine. */ -+ gcmkONERROR(gckGALDEVICE_Release_ISR(Device, gcvCORE_MAJOR)); -+ } -+ -+ if (Device->kernels[gcvCORE_2D] != gcvNULL) -+ { -+ /* Setup the ISR routine. */ -+ gcmkONERROR(gckGALDEVICE_Release_ISR(Device, gcvCORE_2D)); -+ -+ /* Switch to OFF power state. */ -+ gcmkONERROR(gckHARDWARE_SetPowerManagementState( -+ Device->kernels[gcvCORE_2D]->hardware, gcvPOWER_OFF -+ )); -+ } -+ -+ if (Device->kernels[gcvCORE_VG] != gcvNULL) -+ { -+ /* Setup the ISR routine. */ -+ gcmkONERROR(gckGALDEVICE_Release_ISR(Device, gcvCORE_VG)); -+ -+#if gcdENABLE_VG -+ /* Switch to OFF power state. */ -+ gcmkONERROR(gckVGHARDWARE_SetPowerManagementState( -+ Device->kernels[gcvCORE_VG]->vg->hardware, gcvPOWER_OFF -+ )); -+#endif -+ } -+ -+ /* Stop the kernel thread. */ -+ gcmkONERROR(gckGALDEVICE_Stop_Threads(Device)); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ gcmkFOOTER(); -+ return status; -+} -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_device.h linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_device.h ---- linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_device.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_device.h 2015-11-30 17:56:13.576137991 +0100 -@@ -0,0 +1,185 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#ifndef __gc_hal_kernel_device_h_ -+#define __gc_hal_kernel_device_h_ -+ -+#include "gc_hal_kernel_debugfs.h" -+ -+/******************************************************************************\ -+******************************* gckGALDEVICE Structure ******************************* -+\******************************************************************************/ -+ -+typedef struct _gckGALDEVICE -+{ -+ /* Objects. */ -+ gckOS os; -+ gckKERNEL kernels[gcdMAX_GPU_COUNT]; -+ -+ gcsPLATFORM* platform; -+ -+ /* Attributes. */ -+ gctSIZE_T internalSize; -+ gctPHYS_ADDR internalPhysical; -+ gctUINT32 internalPhysicalName; -+ gctPOINTER internalLogical; -+ gckVIDMEM internalVidMem; -+ gctSIZE_T externalSize; -+ gctPHYS_ADDR externalPhysical; -+ gctUINT32 externalPhysicalName; -+ gctPOINTER externalLogical; -+ gckVIDMEM externalVidMem; -+ gckVIDMEM contiguousVidMem; -+ gctPOINTER contiguousBase; -+ gctPHYS_ADDR contiguousPhysical; -+ gctUINT32 contiguousPhysicalName; -+ gctSIZE_T contiguousSize; -+ gctBOOL contiguousMapped; -+ gctPOINTER contiguousMappedUser; -+ gctBOOL contiguousRequested; -+ gctSIZE_T systemMemorySize; -+ gctUINT32 systemMemoryBaseAddress; -+ gctPOINTER registerBases[gcdMAX_GPU_COUNT]; -+ gctSIZE_T registerSizes[gcdMAX_GPU_COUNT]; -+ gctUINT32 baseAddress; -+ gctUINT32 physBase; -+ gctUINT32 physSize; -+ gctBOOL mmu; -+ gctUINT32 requestedRegisterMemBases[gcdMAX_GPU_COUNT]; -+ gctSIZE_T requestedRegisterMemSizes[gcdMAX_GPU_COUNT]; -+ gctUINT32 requestedContiguousBase; -+ gctSIZE_T requestedContiguousSize; -+ -+ /* IRQ management. */ -+ gctINT irqLines[gcdMAX_GPU_COUNT]; -+ gctBOOL isrInitializeds[gcdMAX_GPU_COUNT]; -+ gctINT isrEnabled[gcdMAX_GPU_COUNT]; -+ -+ /* Thread management. */ -+ struct task_struct *threadCtxts[gcdMAX_GPU_COUNT]; -+ struct semaphore semas[gcdMAX_GPU_COUNT]; -+ gctBOOL threadInitializeds[gcdMAX_GPU_COUNT]; -+ gctBOOL killThread; -+ -+ /* Signal management. */ -+ gctINT signal; -+ -+ /* Core mapping */ -+ gceCORE coreMapping[8]; -+ -+ /* States before suspend. */ -+ gceCHIPPOWERSTATE statesStored[gcdMAX_GPU_COUNT]; -+ -+ /* Device Debug File System Entry in kernel. */ -+ struct _gcsDEBUGFS_Node * dbgNode; -+ -+ gcsDEBUGFS_DIR debugfsDir; -+} -+* gckGALDEVICE; -+ -+typedef struct _gcsHAL_PRIVATE_DATA -+{ -+ gckGALDEVICE device; -+ gctPOINTER mappedMemory; -+ gctPOINTER contiguousLogical; -+ /* The process opening the device may not be the same as the one that closes it. */ -+ gctUINT32 pidOpen; -+} -+gcsHAL_PRIVATE_DATA, * gcsHAL_PRIVATE_DATA_PTR; -+ -+typedef struct _gcsDEVICE_CONSTRUCT_ARGS -+{ -+ gctBOOL recovery; -+ gctUINT stuckDump; -+ gctUINT gpu3DMinClock; -+ -+ gctBOOL contiguousRequested; -+ gcsPLATFORM* platform; -+ gctBOOL mmu; -+} -+gcsDEVICE_CONSTRUCT_ARGS; -+ -+gceSTATUS gckGALDEVICE_Enable_ISR( -+ IN gckGALDEVICE Device, -+ IN gceCORE Core -+ ); -+ -+gceSTATUS gckGALDEVICE_Disable_ISR( -+ IN gckGALDEVICE Device, -+ IN gceCORE Core -+ ); -+ -+gceSTATUS gckGALDEVICE_Setup_ISR( -+ IN gckGALDEVICE Device, -+ IN gceCORE Core -+ ); -+ -+gceSTATUS gckGALDEVICE_Release_ISR( -+ IN gckGALDEVICE Device, -+ IN gceCORE Core -+ ); -+ -+gceSTATUS gckGALDEVICE_Start_Threads( -+ IN gckGALDEVICE Device -+ ); -+ -+gceSTATUS gckGALDEVICE_Stop_Threads( -+ gckGALDEVICE Device -+ ); -+ -+gceSTATUS gckGALDEVICE_Start( -+ IN gckGALDEVICE Device -+ ); -+ -+gceSTATUS gckGALDEVICE_Stop( -+ gckGALDEVICE Device -+ ); -+ -+gceSTATUS gckGALDEVICE_Construct( -+ IN gctINT IrqLine, -+ IN gctUINT32 RegisterMemBase, -+ IN gctSIZE_T RegisterMemSize, -+ IN gctINT IrqLine2D, -+ IN gctUINT32 RegisterMemBase2D, -+ IN gctSIZE_T RegisterMemSize2D, -+ IN gctINT IrqLineVG, -+ IN gctUINT32 RegisterMemBaseVG, -+ IN gctSIZE_T RegisterMemSizeVG, -+ IN gctUINT32 ContiguousBase, -+ IN gctSIZE_T ContiguousSize, -+ IN gctSIZE_T BankSize, -+ IN gctINT FastClear, -+ IN gctINT Compression, -+ IN gctUINT32 PhysBaseAddr, -+ IN gctUINT32 PhysSize, -+ IN gctINT Signal, -+ IN gctUINT LogFileSize, -+ IN gctINT PowerManagement, -+ IN gctINT GpuProfiler, -+ IN gcsDEVICE_CONSTRUCT_ARGS * Args, -+ OUT gckGALDEVICE *Device -+ ); -+ -+gceSTATUS gckGALDEVICE_Destroy( -+ IN gckGALDEVICE Device -+ ); -+ -+#endif /* __gc_hal_kernel_device_h_ */ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_event.c linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_event.c ---- linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_event.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_event.c 2015-11-30 17:56:13.576137991 +0100 -@@ -0,0 +1,2859 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#include "gc_hal_kernel_precomp.h" -+#include "gc_hal_kernel_buffer.h" -+ -+#define _GC_OBJ_ZONE gcvZONE_EVENT -+ -+#define gcdEVENT_ALLOCATION_COUNT (4096 / gcmSIZEOF(gcsHAL_INTERFACE)) -+#define gcdEVENT_MIN_THRESHOLD 4 -+ -+/******************************************************************************\ -+********************************* Support Code ********************************* -+\******************************************************************************/ -+ -+static gceSTATUS -+gckEVENT_AllocateQueue( -+ IN gckEVENT Event, -+ OUT gcsEVENT_QUEUE_PTR * Queue -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Event=0x%x", Event); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT); -+ gcmkVERIFY_ARGUMENT(Queue != gcvNULL); -+ -+ /* Do we have free queues? */ -+ if (Event->freeList == gcvNULL) -+ { -+ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES); -+ } -+ -+ /* Move one free queue from the free list. */ -+ * Queue = Event->freeList; -+ Event->freeList = Event->freeList->next; -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Queue=0x%x", gcmOPT_POINTER(Queue)); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+static gceSTATUS -+gckEVENT_FreeQueue( -+ IN gckEVENT Event, -+ OUT gcsEVENT_QUEUE_PTR Queue -+ ) -+{ -+ gceSTATUS status = gcvSTATUS_OK; -+ -+ gcmkHEADER_ARG("Event=0x%x", Event); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT); -+ gcmkVERIFY_ARGUMENT(Queue != gcvNULL); -+ -+ /* Move one free queue from the free list. */ -+ Queue->next = Event->freeList; -+ Event->freeList = Queue; -+ -+ /* Success. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+static gceSTATUS -+gckEVENT_FreeRecord( -+ IN gckEVENT Event, -+ IN gcsEVENT_PTR Record -+ ) -+{ -+ gceSTATUS status; -+ gctBOOL acquired = gcvFALSE; -+ -+ gcmkHEADER_ARG("Event=0x%x Record=0x%x", Event, Record); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT); -+ gcmkVERIFY_ARGUMENT(Record != gcvNULL); -+ -+ /* Acquire the mutex. */ -+ gcmkONERROR(gckOS_AcquireMutex(Event->os, -+ Event->freeEventMutex, -+ gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ /* Push the record on the free list. */ -+ Record->next = Event->freeEventList; -+ Event->freeEventList = Record; -+ Event->freeEventCount += 1; -+ -+ /* Release the mutex. */ -+ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->freeEventMutex)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Roll back. */ -+ if (acquired) -+ { -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->freeEventMutex)); -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return gcvSTATUS_OK; -+} -+ -+static gceSTATUS -+gckEVENT_IsEmpty( -+ IN gckEVENT Event, -+ OUT gctBOOL_PTR IsEmpty -+ ) -+{ -+ gceSTATUS status; -+ gctSIZE_T i; -+ -+ gcmkHEADER_ARG("Event=0x%x", Event); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT); -+ gcmkVERIFY_ARGUMENT(IsEmpty != gcvNULL); -+ -+ /* Assume the event queue is empty. */ -+ *IsEmpty = gcvTRUE; -+ -+ /* Try acquiring the mutex. */ -+ status = gckOS_AcquireMutex(Event->os, Event->eventQueueMutex, 0); -+ if (status == gcvSTATUS_TIMEOUT) -+ { -+ /* Timeout - queue is no longer empty. */ -+ *IsEmpty = gcvFALSE; -+ } -+ else -+ { -+ /* Bail out on error. */ -+ gcmkONERROR(status); -+ -+ /* Walk the event queue. */ -+ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i) -+ { -+ /* Check whether this event is in use. */ -+ if (Event->queues[i].head != gcvNULL) -+ { -+ /* The event is in use, hence the queue is not empty. */ -+ *IsEmpty = gcvFALSE; -+ break; -+ } -+ } -+ -+ /* Release the mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex)); -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*IsEmpty=%d", gcmOPT_VALUE(IsEmpty)); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+static gceSTATUS -+_TryToIdleGPU( -+ IN gckEVENT Event -+) -+{ -+ gceSTATUS status; -+ gctBOOL empty = gcvFALSE; -+ gckHARDWARE hardware; -+ -+ gcmkHEADER_ARG("Event=0x%x", Event); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT); -+ -+ /* Grab gckHARDWARE object. */ -+ hardware = Event->kernel->hardware; -+ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE); -+ -+ /* Check whether the event queue is empty. */ -+ gcmkONERROR(gckEVENT_IsEmpty(Event, &empty)); -+ -+ if (empty) -+ { -+ /* Inform the system of idle GPU. */ -+ gcmkONERROR(gckOS_Broadcast(Event->os, -+ Event->kernel->hardware, -+ gcvBROADCAST_GPU_IDLE)); -+ } -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ -+ gcmkFOOTER(); -+ return status; -+} -+ -+static gceSTATUS -+__RemoveRecordFromProcessDB( -+ IN gckEVENT Event, -+ IN gcsEVENT_PTR Record -+ ) -+{ -+ gcmkHEADER_ARG("Event=0x%x Record=0x%x", Event, Record); -+ gcmkVERIFY_ARGUMENT(Record != gcvNULL); -+ -+ while (Record != gcvNULL) -+ { -+ if (Record->info.command == gcvHAL_SIGNAL) -+ { -+ /* TODO: Find a better place to bind signal to hardware.*/ -+ gcmkVERIFY_OK(gckOS_SignalSetHardware(Event->os, -+ gcmUINT64_TO_PTR(Record->info.u.Signal.signal), -+ Event->kernel->hardware)); -+ } -+ -+ if (Record->fromKernel) -+ { -+ /* No need to check db if event is from kernel. */ -+ Record = Record->next; -+ continue; -+ } -+ -+ switch (Record->info.command) -+ { -+ case gcvHAL_FREE_NON_PAGED_MEMORY: -+ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB( -+ Event->kernel, -+ Record->processID, -+ gcvDB_NON_PAGED, -+ gcmUINT64_TO_PTR(Record->info.u.FreeNonPagedMemory.logical))); -+ break; -+ -+ case gcvHAL_FREE_CONTIGUOUS_MEMORY: -+ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB( -+ Event->kernel, -+ Record->processID, -+ gcvDB_CONTIGUOUS, -+ gcmUINT64_TO_PTR(Record->info.u.FreeContiguousMemory.logical))); -+ break; -+ -+ case gcvHAL_UNLOCK_VIDEO_MEMORY: -+ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB( -+ Event->kernel, -+ Record->processID, -+ gcvDB_VIDEO_MEMORY_LOCKED, -+ gcmUINT64_TO_PTR(Record->info.u.UnlockVideoMemory.node))); -+ break; -+ -+ case gcvHAL_UNMAP_USER_MEMORY: -+ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB( -+ Event->kernel, -+ Record->processID, -+ gcvDB_MAP_USER_MEMORY, -+ gcmINT2PTR(Record->info.u.UnmapUserMemory.info))); -+ break; -+ -+ case gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER: -+ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB( -+ Event->kernel, -+ Record->processID, -+ gcvDB_COMMAND_BUFFER, -+ gcmUINT64_TO_PTR(Record->info.u.FreeVirtualCommandBuffer.logical))); -+ break; -+ -+ default: -+ break; -+ } -+ -+ Record = Record->next; -+ } -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+_ReleaseVideoMemoryHandle( -+ IN gckKERNEL Kernel, -+ IN OUT gcsEVENT_PTR Record, -+ IN OUT gcsHAL_INTERFACE * Interface -+ ) -+{ -+ gceSTATUS status; -+ gckVIDMEM_NODE nodeObject; -+ gctUINT32 handle; -+ -+ switch(Interface->command) -+ { -+ case gcvHAL_UNLOCK_VIDEO_MEMORY: -+ handle = (gctUINT32)Interface->u.UnlockVideoMemory.node; -+ -+ gcmkONERROR(gckVIDMEM_HANDLE_Lookup( -+ Kernel, Record->processID, handle, &nodeObject)); -+ -+ Record->info.u.UnlockVideoMemory.node = gcmPTR_TO_UINT64(nodeObject); -+ -+ gckVIDMEM_HANDLE_Dereference(Kernel, Record->processID, handle); -+ break; -+ -+ default: -+ break; -+ } -+ -+ return gcvSTATUS_OK; -+OnError: -+ return status; -+} -+ -+/******************************************************************************* -+** -+** _QueryFlush -+** -+** Check the type of surfaces which will be released by current event and -+** determine the cache needed to flush. -+** -+*/ -+static gceSTATUS -+_QueryFlush( -+ IN gckEVENT Event, -+ IN gcsEVENT_PTR Record, -+ OUT gceKERNEL_FLUSH *Flush -+ ) -+{ -+ gceKERNEL_FLUSH flush = 0; -+ gcmkHEADER_ARG("Event=0x%x Record=0x%x", Event, Record); -+ gcmkVERIFY_ARGUMENT(Record != gcvNULL); -+ -+ while (Record != gcvNULL) -+ { -+ switch (Record->info.command) -+ { -+ case gcvHAL_UNLOCK_VIDEO_MEMORY: -+ switch(Record->info.u.UnlockVideoMemory.type) -+ { -+ case gcvSURF_TILE_STATUS: -+ flush |= gcvFLUSH_TILE_STATUS; -+ break; -+ case gcvSURF_RENDER_TARGET: -+ flush |= gcvFLUSH_COLOR; -+ break; -+ case gcvSURF_DEPTH: -+ flush |= gcvFLUSH_DEPTH; -+ break; -+ case gcvSURF_TEXTURE: -+ flush |= gcvFLUSH_TEXTURE; -+ break; -+ case gcvSURF_TYPE_UNKNOWN: -+ gcmkASSERT(0); -+ break; -+ default: -+ break; -+ } -+ break; -+ case gcvHAL_UNMAP_USER_MEMORY: -+ *Flush = gcvFLUSH_ALL; -+ return gcvSTATUS_OK; -+ -+ default: -+ break; -+ } -+ -+ Record = Record->next; -+ } -+ -+ *Flush = flush; -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+void -+_SubmitTimerFunction( -+ gctPOINTER Data -+ ) -+{ -+ gckEVENT event = (gckEVENT)Data; -+ gcmkVERIFY_OK(gckEVENT_Submit(event, gcvTRUE, gcvFALSE, gcvFALSE)); -+} -+ -+/******************************************************************************\ -+******************************* gckEVENT API Code ******************************* -+\******************************************************************************/ -+ -+/******************************************************************************* -+** -+** gckEVENT_Construct -+** -+** Construct a new gckEVENT object. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** OUTPUT: -+** -+** gckEVENT * Event -+** Pointer to a variable that receives the gckEVENT object pointer. -+*/ -+gceSTATUS -+gckEVENT_Construct( -+ IN gckKERNEL Kernel, -+ OUT gckEVENT * Event -+ ) -+{ -+ gckOS os; -+ gceSTATUS status; -+ gckEVENT eventObj = gcvNULL; -+ int i; -+ gcsEVENT_PTR record; -+ gctPOINTER pointer = gcvNULL; -+ -+ gcmkHEADER_ARG("Kernel=0x%x", Kernel); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ gcmkVERIFY_ARGUMENT(Event != gcvNULL); -+ -+ /* Extract the pointer to the gckOS object. */ -+ os = Kernel->os; -+ gcmkVERIFY_OBJECT(os, gcvOBJ_OS); -+ -+ /* Allocate the gckEVENT object. */ -+ gcmkONERROR(gckOS_Allocate(os, gcmSIZEOF(struct _gckEVENT), &pointer)); -+ -+ eventObj = pointer; -+ -+ /* Reset the object. */ -+ gcmkVERIFY_OK(gckOS_ZeroMemory(eventObj, gcmSIZEOF(struct _gckEVENT))); -+ -+ /* Initialize the gckEVENT object. */ -+ eventObj->object.type = gcvOBJ_EVENT; -+ eventObj->kernel = Kernel; -+ eventObj->os = os; -+ -+ /* Create the mutexes. */ -+ gcmkONERROR(gckOS_CreateMutex(os, &eventObj->eventQueueMutex)); -+ gcmkONERROR(gckOS_CreateMutex(os, &eventObj->freeEventMutex)); -+ gcmkONERROR(gckOS_CreateMutex(os, &eventObj->eventListMutex)); -+ -+ /* Create a bunch of event reccords. */ -+ for (i = 0; i < gcdEVENT_ALLOCATION_COUNT; i += 1) -+ { -+ /* Allocate an event record. */ -+ gcmkONERROR(gckOS_Allocate(os, gcmSIZEOF(gcsEVENT), &pointer)); -+ -+ record = pointer; -+ -+ /* Push it on the free list. */ -+ record->next = eventObj->freeEventList; -+ eventObj->freeEventList = record; -+ eventObj->freeEventCount += 1; -+ } -+ -+ /* Initialize the free list of event queues. */ -+ for (i = 0; i < gcdREPO_LIST_COUNT; i += 1) -+ { -+ eventObj->repoList[i].next = eventObj->freeList; -+ eventObj->freeList = &eventObj->repoList[i]; -+ } -+ -+ /* Construct the atom. */ -+ gcmkONERROR(gckOS_AtomConstruct(os, &eventObj->freeAtom)); -+ gcmkONERROR(gckOS_AtomSet(os, -+ eventObj->freeAtom, -+ gcmCOUNTOF(eventObj->queues))); -+ -+#if gcdSMP -+ gcmkONERROR(gckOS_AtomConstruct(os, &eventObj->pending)); -+#endif -+ -+ gcmkVERIFY_OK(gckOS_CreateTimer(os, -+ _SubmitTimerFunction, -+ (gctPOINTER)eventObj, -+ &eventObj->submitTimer)); -+ -+#if gcdINTERRUPT_STATISTIC -+ gcmkONERROR(gckOS_AtomConstruct(os, &eventObj->interruptCount)); -+ gcmkONERROR(gckOS_AtomSet(os,eventObj->interruptCount, 0)); -+#endif -+ -+ /* Return pointer to the gckEVENT object. */ -+ *Event = eventObj; -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Event=0x%x", *Event); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Roll back. */ -+ if (eventObj != gcvNULL) -+ { -+ if (eventObj->eventQueueMutex != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckOS_DeleteMutex(os, eventObj->eventQueueMutex)); -+ } -+ -+ if (eventObj->freeEventMutex != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckOS_DeleteMutex(os, eventObj->freeEventMutex)); -+ } -+ -+ if (eventObj->eventListMutex != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckOS_DeleteMutex(os, eventObj->eventListMutex)); -+ } -+ -+ while (eventObj->freeEventList != gcvNULL) -+ { -+ record = eventObj->freeEventList; -+ eventObj->freeEventList = record->next; -+ -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, record)); -+ } -+ -+ if (eventObj->freeAtom != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckOS_AtomDestroy(os, eventObj->freeAtom)); -+ } -+ -+#if gcdSMP -+ if (eventObj->pending != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckOS_AtomDestroy(os, eventObj->pending)); -+ } -+#endif -+ -+#if gcdINTERRUPT_STATISTIC -+ if (eventObj->interruptCount) -+ { -+ gcmkVERIFY_OK(gckOS_AtomDestroy(os, eventObj->interruptCount)); -+ } -+#endif -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, eventObj)); -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckEVENT_Destroy -+** -+** Destroy an gckEVENT object. -+** -+** INPUT: -+** -+** gckEVENT Event -+** Pointer to an gckEVENT object. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckEVENT_Destroy( -+ IN gckEVENT Event -+ ) -+{ -+ gcsEVENT_PTR record; -+ gcsEVENT_QUEUE_PTR queue; -+ -+ gcmkHEADER_ARG("Event=0x%x", Event); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT); -+ -+ if (Event->submitTimer != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckOS_StopTimer(Event->os, Event->submitTimer)); -+ gcmkVERIFY_OK(gckOS_DestroyTimer(Event->os, Event->submitTimer)); -+ } -+ -+ /* Delete the queue mutex. */ -+ gcmkVERIFY_OK(gckOS_DeleteMutex(Event->os, Event->eventQueueMutex)); -+ -+ /* Free all free events. */ -+ while (Event->freeEventList != gcvNULL) -+ { -+ record = Event->freeEventList; -+ Event->freeEventList = record->next; -+ -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Event->os, record)); -+ } -+ -+ /* Delete the free mutex. */ -+ gcmkVERIFY_OK(gckOS_DeleteMutex(Event->os, Event->freeEventMutex)); -+ -+ /* Free all pending queues. */ -+ while (Event->queueHead != gcvNULL) -+ { -+ /* Get the current queue. */ -+ queue = Event->queueHead; -+ -+ /* Free all pending events. */ -+ while (queue->head != gcvNULL) -+ { -+ record = queue->head; -+ queue->head = record->next; -+ -+ gcmkTRACE_ZONE_N( -+ gcvLEVEL_WARNING, gcvZONE_EVENT, -+ gcmSIZEOF(record) + gcmSIZEOF(queue->source), -+ "Event record 0x%x is still pending for %d.", -+ record, queue->source -+ ); -+ -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Event->os, record)); -+ } -+ -+ /* Remove the top queue from the list. */ -+ if (Event->queueHead == Event->queueTail) -+ { -+ Event->queueHead = -+ Event->queueTail = gcvNULL; -+ } -+ else -+ { -+ Event->queueHead = Event->queueHead->next; -+ } -+ -+ /* Free the queue. */ -+ gcmkVERIFY_OK(gckEVENT_FreeQueue(Event, queue)); -+ } -+ -+ /* Delete the list mutex. */ -+ gcmkVERIFY_OK(gckOS_DeleteMutex(Event->os, Event->eventListMutex)); -+ -+ /* Delete the atom. */ -+ gcmkVERIFY_OK(gckOS_AtomDestroy(Event->os, Event->freeAtom)); -+ -+#if gcdSMP -+ gcmkVERIFY_OK(gckOS_AtomDestroy(Event->os, Event->pending)); -+#endif -+ -+#if gcdINTERRUPT_STATISTIC -+ gcmkVERIFY_OK(gckOS_AtomDestroy(Event->os, Event->interruptCount)); -+#endif -+ -+ /* Mark the gckEVENT object as unknown. */ -+ Event->object.type = gcvOBJ_UNKNOWN; -+ -+ /* Free the gckEVENT object. */ -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Event->os, Event)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckEVENT_GetEvent -+** -+** Reserve the next available hardware event. -+** -+** INPUT: -+** -+** gckEVENT Event -+** Pointer to an gckEVENT object. -+** -+** gctBOOL Wait -+** Set to gcvTRUE to force the function to wait if no events are -+** immediately available. -+** -+** gceKERNEL_WHERE Source -+** Source of the event. -+** -+** OUTPUT: -+** -+** gctUINT8 * EventID -+** Reserved event ID. -+*/ -+#define gcdINVALID_EVENT_PTR ((gcsEVENT_PTR)gcvMAXUINTPTR_T) -+ -+static gceSTATUS -+gckEVENT_GetEvent( -+ IN gckEVENT Event, -+ IN gctBOOL Wait, -+ OUT gctUINT8 * EventID, -+ IN gcsEVENT_PTR Head, -+ IN gceKERNEL_WHERE Source -+ ) -+{ -+ gctINT i, id; -+ gceSTATUS status; -+ gctBOOL acquired = gcvFALSE; -+ gctINT32 free; -+ -+ gcmkHEADER_ARG("Event=0x%x Head=%p Source=%d", Event, Head, Source); -+ -+ while (gcvTRUE) -+ { -+ /* Grab the queue mutex. */ -+ gcmkONERROR(gckOS_AcquireMutex(Event->os, -+ Event->eventQueueMutex, -+ gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ /* Walk through all events. */ -+ id = Event->lastID; -+ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i) -+ { -+ gctINT nextID = gckMATH_ModuloInt((id + 1), -+ gcmCOUNTOF(Event->queues)); -+ -+ if (Event->queues[id].head == gcvNULL) -+ { -+ *EventID = (gctUINT8) id; -+ -+ Event->lastID = (gctUINT8) nextID; -+ -+ /* Save time stamp of event. */ -+ Event->queues[id].head = gcdINVALID_EVENT_PTR; -+ Event->queues[id].stamp = ++(Event->stamp); -+ Event->queues[id].head = Head; -+ Event->queues[id].source = Source; -+ -+ gcmkONERROR(gckOS_AtomDecrement(Event->os, -+ Event->freeAtom, -+ &free)); -+#if gcdDYNAMIC_SPEED -+ if (free <= gcdDYNAMIC_EVENT_THRESHOLD) -+ { -+ gcmkONERROR(gckOS_BroadcastHurry( -+ Event->os, -+ Event->kernel->hardware, -+ gcdDYNAMIC_EVENT_THRESHOLD - free)); -+ } -+#endif -+ -+ /* Release the queue mutex. */ -+ gcmkONERROR(gckOS_ReleaseMutex(Event->os, -+ Event->eventQueueMutex)); -+ -+ /* Success. */ -+ gcmkTRACE_ZONE_N( -+ gcvLEVEL_INFO, gcvZONE_EVENT, -+ gcmSIZEOF(id), -+ "Using id=%d", -+ id -+ ); -+ -+ gcmkFOOTER_ARG("*EventID=%u", *EventID); -+ return gcvSTATUS_OK; -+ } -+ -+ id = nextID; -+ } -+ -+#if gcdDYNAMIC_SPEED -+ /* No free events, speed up the GPU right now! */ -+ gcmkONERROR(gckOS_BroadcastHurry(Event->os, -+ Event->kernel->hardware, -+ gcdDYNAMIC_EVENT_THRESHOLD)); -+#endif -+ -+ /* Release the queue mutex. */ -+ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex)); -+ acquired = gcvFALSE; -+ -+ /* Fail if wait is not requested. */ -+ if (!Wait) -+ { -+ /* Out of resources. */ -+ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES); -+ } -+ -+ /* Delay a while. */ -+ gcmkONERROR(gckOS_Delay(Event->os, 1)); -+ } -+ -+OnError: -+ if (acquired) -+ { -+ /* Release the queue mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex)); -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckEVENT_AllocateRecord -+** -+** Allocate a record for the new event. -+** -+** INPUT: -+** -+** gckEVENT Event -+** Pointer to an gckEVENT object. -+** -+** gctBOOL AllocateAllowed -+** State for allocation if out of free events. -+** -+** OUTPUT: -+** -+** gcsEVENT_PTR * Record -+** Allocated event record. -+*/ -+gceSTATUS -+gckEVENT_AllocateRecord( -+ IN gckEVENT Event, -+ IN gctBOOL AllocateAllowed, -+ OUT gcsEVENT_PTR * Record -+ ) -+{ -+ gceSTATUS status; -+ gctBOOL acquired = gcvFALSE; -+ gctINT i; -+ gcsEVENT_PTR record; -+ gctPOINTER pointer = gcvNULL; -+ -+ gcmkHEADER_ARG("Event=0x%x AllocateAllowed=%d", Event, AllocateAllowed); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT); -+ gcmkVERIFY_ARGUMENT(Record != gcvNULL); -+ -+ /* Acquire the mutex. */ -+ gcmkONERROR(gckOS_AcquireMutex(Event->os, Event->freeEventMutex, gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ /* Test if we are below the allocation threshold. */ -+ if ( (AllocateAllowed && (Event->freeEventCount < gcdEVENT_MIN_THRESHOLD)) || -+ (Event->freeEventCount == 0) ) -+ { -+ /* Allocate a bunch of records. */ -+ for (i = 0; i < gcdEVENT_ALLOCATION_COUNT; i += 1) -+ { -+ /* Allocate an event record. */ -+ gcmkONERROR(gckOS_Allocate(Event->os, -+ gcmSIZEOF(gcsEVENT), -+ &pointer)); -+ -+ record = pointer; -+ -+ /* Push it on the free list. */ -+ record->next = Event->freeEventList; -+ Event->freeEventList = record; -+ Event->freeEventCount += 1; -+ } -+ } -+ -+ *Record = Event->freeEventList; -+ Event->freeEventList = Event->freeEventList->next; -+ Event->freeEventCount -= 1; -+ -+ /* Release the mutex. */ -+ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->freeEventMutex)); -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Record=0x%x", gcmOPT_POINTER(Record)); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Roll back. */ -+ if (acquired) -+ { -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->freeEventMutex)); -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckEVENT_AddList -+** -+** Add a new event to the list of events. -+** -+** INPUT: -+** -+** gckEVENT Event -+** Pointer to an gckEVENT object. -+** -+** gcsHAL_INTERFACE_PTR Interface -+** Pointer to the interface for the event to be added. -+** -+** gceKERNEL_WHERE FromWhere -+** Place in the pipe where the event needs to be generated. -+** -+** gctBOOL AllocateAllowed -+** State for allocation if out of free events. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckEVENT_AddList( -+ IN gckEVENT Event, -+ IN gcsHAL_INTERFACE_PTR Interface, -+ IN gceKERNEL_WHERE FromWhere, -+ IN gctBOOL AllocateAllowed, -+ IN gctBOOL FromKernel -+ ) -+{ -+ gceSTATUS status; -+ gctBOOL acquired = gcvFALSE; -+ gcsEVENT_PTR record = gcvNULL; -+ gcsEVENT_QUEUE_PTR queue; -+ gckVIRTUAL_COMMAND_BUFFER_PTR buffer; -+ gckKERNEL kernel = Event->kernel; -+ -+ gcmkHEADER_ARG("Event=0x%x Interface=0x%x", -+ Event, Interface); -+ -+ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, _GC_OBJ_ZONE, -+ "FromWhere=%d AllocateAllowed=%d", -+ FromWhere, AllocateAllowed); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT); -+ gcmkVERIFY_ARGUMENT(Interface != gcvNULL); -+ -+ /* Verify the event command. */ -+ gcmkASSERT -+ ( (Interface->command == gcvHAL_FREE_NON_PAGED_MEMORY) -+ || (Interface->command == gcvHAL_FREE_CONTIGUOUS_MEMORY) -+ || (Interface->command == gcvHAL_WRITE_DATA) -+ || (Interface->command == gcvHAL_UNLOCK_VIDEO_MEMORY) -+ || (Interface->command == gcvHAL_SIGNAL) -+ || (Interface->command == gcvHAL_UNMAP_USER_MEMORY) -+ || (Interface->command == gcvHAL_TIMESTAMP) -+ || (Interface->command == gcvHAL_COMMIT_DONE) -+ || (Interface->command == gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER) -+ || (Interface->command == gcvHAL_SYNC_POINT) -+ || (Interface->command == gcvHAL_DESTROY_MMU) -+ ); -+ -+ /* Validate the source. */ -+ if ((FromWhere != gcvKERNEL_COMMAND) && (FromWhere != gcvKERNEL_PIXEL)) -+ { -+ /* Invalid argument. */ -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ } -+ -+ /* Allocate a free record. */ -+ gcmkONERROR(gckEVENT_AllocateRecord(Event, AllocateAllowed, &record)); -+ -+ /* Termninate the record. */ -+ record->next = gcvNULL; -+ -+ /* Record the committer. */ -+ record->fromKernel = FromKernel; -+ -+ /* Copy the event interface into the record. */ -+ gckOS_MemCopy(&record->info, Interface, gcmSIZEOF(record->info)); -+ -+ /* Get process ID. */ -+ gcmkONERROR(gckOS_GetProcessID(&record->processID)); -+ -+ gcmkONERROR(__RemoveRecordFromProcessDB(Event, record)); -+ -+ /* Handle is belonged to current process, it must be released now. */ -+ if (FromKernel == gcvFALSE) -+ { -+ status = _ReleaseVideoMemoryHandle(Event->kernel, record, Interface); -+ -+ if (gcmIS_ERROR(status)) -+ { -+ /* Ingore error because there are other events in the queue. */ -+ status = gcvSTATUS_OK; -+ goto OnError; -+ } -+ } -+ -+ /* Acquire the mutex. */ -+ gcmkONERROR(gckOS_AcquireMutex(Event->os, Event->eventListMutex, gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ /* Do we need to allocate a new queue? */ -+ if ((Event->queueTail == gcvNULL) || (Event->queueTail->source < FromWhere)) -+ { -+ /* Allocate a new queue. */ -+ gcmkONERROR(gckEVENT_AllocateQueue(Event, &queue)); -+ -+ /* Initialize the queue. */ -+ queue->source = FromWhere; -+ queue->head = gcvNULL; -+ queue->next = gcvNULL; -+ -+ /* Attach it to the list of allocated queues. */ -+ if (Event->queueTail == gcvNULL) -+ { -+ Event->queueHead = -+ Event->queueTail = queue; -+ } -+ else -+ { -+ Event->queueTail->next = queue; -+ Event->queueTail = queue; -+ } -+ } -+ else -+ { -+ queue = Event->queueTail; -+ } -+ -+ /* Attach the record to the queue. */ -+ if (queue->head == gcvNULL) -+ { -+ queue->head = record; -+ queue->tail = record; -+ } -+ else -+ { -+ queue->tail->next = record; -+ queue->tail = record; -+ } -+ -+ /* Unmap user space logical address. -+ * Linux kernel does not support unmap the memory of other process any more since 3.5. -+ * Let's unmap memory of self process before submit the event to gpu. -+ * */ -+ switch(Interface->command) -+ { -+ case gcvHAL_FREE_NON_PAGED_MEMORY: -+ gcmkONERROR(gckOS_UnmapUserLogical( -+ Event->os, -+ gcmNAME_TO_PTR(Interface->u.FreeNonPagedMemory.physical), -+ (gctSIZE_T) Interface->u.FreeNonPagedMemory.bytes, -+ gcmUINT64_TO_PTR(Interface->u.FreeNonPagedMemory.logical))); -+ break; -+ case gcvHAL_FREE_CONTIGUOUS_MEMORY: -+ gcmkONERROR(gckOS_UnmapUserLogical( -+ Event->os, -+ gcmNAME_TO_PTR(Interface->u.FreeContiguousMemory.physical), -+ (gctSIZE_T) Interface->u.FreeContiguousMemory.bytes, -+ gcmUINT64_TO_PTR(Interface->u.FreeContiguousMemory.logical))); -+ break; -+ -+ case gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER: -+ buffer = (gckVIRTUAL_COMMAND_BUFFER_PTR)gcmNAME_TO_PTR(Interface->u.FreeVirtualCommandBuffer.physical); -+ if (buffer->userLogical) -+ { -+ gcmkONERROR(gckOS_DestroyUserVirtualMapping( -+ Event->os, -+ buffer->physical, -+ (gctSIZE_T) Interface->u.FreeVirtualCommandBuffer.bytes, -+ gcmUINT64_TO_PTR(Interface->u.FreeVirtualCommandBuffer.logical))); -+ } -+ break; -+ -+ default: -+ break; -+ } -+ -+ /* Release the mutex. */ -+ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->eventListMutex)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Roll back. */ -+ if (acquired) -+ { -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->eventListMutex)); -+ } -+ -+ if (record != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckEVENT_FreeRecord(Event, record)); -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckEVENT_Unlock -+** -+** Schedule an event to unlock virtual memory. -+** -+** INPUT: -+** -+** gckEVENT Event -+** Pointer to an gckEVENT object. -+** -+** gceKERNEL_WHERE FromWhere -+** Place in the pipe where the event needs to be generated. -+** -+** gcuVIDMEM_NODE_PTR Node -+** Pointer to a gcuVIDMEM_NODE union that specifies the virtual memory -+** to unlock. -+** -+** gceSURF_TYPE Type -+** Type of surface to unlock. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckEVENT_Unlock( -+ IN gckEVENT Event, -+ IN gceKERNEL_WHERE FromWhere, -+ IN gctPOINTER Node, -+ IN gceSURF_TYPE Type -+ ) -+{ -+ gceSTATUS status; -+ gcsHAL_INTERFACE iface; -+ -+ gcmkHEADER_ARG("Event=0x%x FromWhere=%d Node=0x%x Type=%d", -+ Event, FromWhere, Node, Type); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT); -+ gcmkVERIFY_ARGUMENT(Node != gcvNULL); -+ -+ /* Mark the event as an unlock. */ -+ iface.command = gcvHAL_UNLOCK_VIDEO_MEMORY; -+ iface.u.UnlockVideoMemory.node = gcmPTR_TO_UINT64(Node); -+ iface.u.UnlockVideoMemory.type = Type; -+ iface.u.UnlockVideoMemory.asynchroneous = 0; -+ -+ /* Append it to the queue. */ -+ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckEVENT_FreeNonPagedMemory -+** -+** Schedule an event to free non-paged memory. -+** -+** INPUT: -+** -+** gckEVENT Event -+** Pointer to an gckEVENT object. -+** -+** gctSIZE_T Bytes -+** Number of bytes of non-paged memory to free. -+** -+** gctPHYS_ADDR Physical -+** Physical address of non-paged memory to free. -+** -+** gctPOINTER Logical -+** Logical address of non-paged memory to free. -+** -+** gceKERNEL_WHERE FromWhere -+** Place in the pipe where the event needs to be generated. -+*/ -+gceSTATUS -+gckEVENT_FreeNonPagedMemory( -+ IN gckEVENT Event, -+ IN gctSIZE_T Bytes, -+ IN gctPHYS_ADDR Physical, -+ IN gctPOINTER Logical, -+ IN gceKERNEL_WHERE FromWhere -+ ) -+{ -+ gceSTATUS status; -+ gcsHAL_INTERFACE iface; -+ gckKERNEL kernel = Event->kernel; -+ -+ gcmkHEADER_ARG("Event=0x%x Bytes=%lu Physical=0x%x Logical=0x%x " -+ "FromWhere=%d", -+ Event, Bytes, Physical, Logical, FromWhere); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT); -+ gcmkVERIFY_ARGUMENT(Physical != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Logical != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Bytes > 0); -+ -+ /* Create an event. */ -+ iface.command = gcvHAL_FREE_NON_PAGED_MEMORY; -+ iface.u.FreeNonPagedMemory.bytes = Bytes; -+ iface.u.FreeNonPagedMemory.physical = gcmPTR_TO_NAME(Physical); -+ iface.u.FreeNonPagedMemory.logical = gcmPTR_TO_UINT64(Logical); -+ -+ /* Append it to the queue. */ -+ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckEVENT_DestroyVirtualCommandBuffer( -+ IN gckEVENT Event, -+ IN gctSIZE_T Bytes, -+ IN gctPHYS_ADDR Physical, -+ IN gctPOINTER Logical, -+ IN gceKERNEL_WHERE FromWhere -+ ) -+{ -+ gceSTATUS status; -+ gcsHAL_INTERFACE iface; -+ gckKERNEL kernel = Event->kernel; -+ -+ gcmkHEADER_ARG("Event=0x%x Bytes=%lu Physical=0x%x Logical=0x%x " -+ "FromWhere=%d", -+ Event, Bytes, Physical, Logical, FromWhere); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT); -+ gcmkVERIFY_ARGUMENT(Physical != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Logical != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Bytes > 0); -+ -+ /* Create an event. */ -+ iface.command = gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER; -+ iface.u.FreeVirtualCommandBuffer.bytes = Bytes; -+ iface.u.FreeVirtualCommandBuffer.physical = gcmPTR_TO_NAME(Physical); -+ iface.u.FreeVirtualCommandBuffer.logical = gcmPTR_TO_UINT64(Logical); -+ -+ /* Append it to the queue. */ -+ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckEVENT_FreeContigiuousMemory -+** -+** Schedule an event to free contiguous memory. -+** -+** INPUT: -+** -+** gckEVENT Event -+** Pointer to an gckEVENT object. -+** -+** gctSIZE_T Bytes -+** Number of bytes of contiguous memory to free. -+** -+** gctPHYS_ADDR Physical -+** Physical address of contiguous memory to free. -+** -+** gctPOINTER Logical -+** Logical address of contiguous memory to free. -+** -+** gceKERNEL_WHERE FromWhere -+** Place in the pipe where the event needs to be generated. -+*/ -+gceSTATUS -+gckEVENT_FreeContiguousMemory( -+ IN gckEVENT Event, -+ IN gctSIZE_T Bytes, -+ IN gctPHYS_ADDR Physical, -+ IN gctPOINTER Logical, -+ IN gceKERNEL_WHERE FromWhere -+ ) -+{ -+ gceSTATUS status; -+ gcsHAL_INTERFACE iface; -+ gckKERNEL kernel = Event->kernel; -+ -+ gcmkHEADER_ARG("Event=0x%x Bytes=%lu Physical=0x%x Logical=0x%x " -+ "FromWhere=%d", -+ Event, Bytes, Physical, Logical, FromWhere); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT); -+ gcmkVERIFY_ARGUMENT(Physical != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Logical != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Bytes > 0); -+ -+ /* Create an event. */ -+ iface.command = gcvHAL_FREE_CONTIGUOUS_MEMORY; -+ iface.u.FreeContiguousMemory.bytes = Bytes; -+ iface.u.FreeContiguousMemory.physical = gcmPTR_TO_NAME(Physical); -+ iface.u.FreeContiguousMemory.logical = gcmPTR_TO_UINT64(Logical); -+ -+ /* Append it to the queue. */ -+ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckEVENT_Signal -+** -+** Schedule an event to trigger a signal. -+** -+** INPUT: -+** -+** gckEVENT Event -+** Pointer to an gckEVENT object. -+** -+** gctSIGNAL Signal -+** Pointer to the signal to trigger. -+** -+** gceKERNEL_WHERE FromWhere -+** Place in the pipe where the event needs to be generated. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckEVENT_Signal( -+ IN gckEVENT Event, -+ IN gctSIGNAL Signal, -+ IN gceKERNEL_WHERE FromWhere -+ ) -+{ -+ gceSTATUS status; -+ gcsHAL_INTERFACE iface; -+ -+ gcmkHEADER_ARG("Event=0x%x Signal=0x%x FromWhere=%d", -+ Event, Signal, FromWhere); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT); -+ gcmkVERIFY_ARGUMENT(Signal != gcvNULL); -+ -+ /* Mark the event as a signal. */ -+ iface.command = gcvHAL_SIGNAL; -+ iface.u.Signal.signal = gcmPTR_TO_UINT64(Signal); -+ iface.u.Signal.auxSignal = 0; -+ iface.u.Signal.process = 0; -+ -+ /* Append it to the queue. */ -+ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckEVENT_CommitDone -+** -+** Schedule an event to wake up work thread when commit is done by GPU. -+** -+** INPUT: -+** -+** gckEVENT Event -+** Pointer to an gckEVENT object. -+** -+** gceKERNEL_WHERE FromWhere -+** Place in the pipe where the event needs to be generated. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckEVENT_CommitDone( -+ IN gckEVENT Event, -+ IN gceKERNEL_WHERE FromWhere -+ ) -+{ -+ gceSTATUS status; -+ gcsHAL_INTERFACE iface; -+ -+ gcmkHEADER_ARG("Event=0x%x FromWhere=%d", Event, FromWhere); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT); -+ -+ iface.command = gcvHAL_COMMIT_DONE; -+ -+ /* Append it to the queue. */ -+ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+#if gcdPROCESS_ADDRESS_SPACE -+gceSTATUS -+gckEVENT_DestroyMmu( -+ IN gckEVENT Event, -+ IN gckMMU Mmu, -+ IN gceKERNEL_WHERE FromWhere -+ ) -+{ -+ gceSTATUS status; -+ gcsHAL_INTERFACE iface; -+ -+ gcmkHEADER_ARG("Event=0x%x FromWhere=%d", Event, FromWhere); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT); -+ -+ iface.command = gcvHAL_DESTROY_MMU; -+ iface.u.DestroyMmu.mmu = gcmPTR_TO_UINT64(Mmu); -+ -+ /* Append it to the queue. */ -+ gcmkONERROR(gckEVENT_AddList(Event, &iface, FromWhere, gcvFALSE, gcvTRUE)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+#endif -+ -+/******************************************************************************* -+** -+** gckEVENT_Submit -+** -+** Submit the current event queue to the GPU. -+** -+** INPUT: -+** -+** gckEVENT Event -+** Pointer to an gckEVENT object. -+** -+** gctBOOL Wait -+** Submit requires one vacant event; if Wait is set to not zero, -+** and there are no vacant events at this time, the function will -+** wait until an event becomes vacant so that submission of the -+** queue is successful. -+** -+** gctBOOL FromPower -+** Determines whether the call originates from inside the power -+** management or not. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckEVENT_Submit( -+ IN gckEVENT Event, -+ IN gctBOOL Wait, -+ IN gctBOOL FromPower, -+ IN gctBOOL FromCommand -+ ) -+{ -+ gceSTATUS status; -+ gctUINT8 id = 0xFF; -+ gcsEVENT_QUEUE_PTR queue; -+ gctBOOL acquired = gcvFALSE; -+ gckCOMMAND command = gcvNULL; -+ gctBOOL commitEntered = gcvFALSE; -+#if !gcdNULL_DRIVER -+ gctUINT32 bytes; -+ gctPOINTER buffer; -+#endif -+ -+#if gcdINTERRUPT_STATISTIC -+ gctINT32 oldValue; -+#endif -+ -+ gctUINT32 flushBytes; -+ gctUINT32 executeBytes; -+ gckHARDWARE hardware; -+ -+ gceKERNEL_FLUSH flush = gcvFALSE; -+ -+ gcmkHEADER_ARG("Event=0x%x Wait=%d", Event, Wait); -+ -+ /* Get gckCOMMAND object. */ -+ command = Event->kernel->command; -+ hardware = Event->kernel->hardware; -+ -+ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE); -+ -+ gckOS_GetTicks(&Event->lastCommitStamp); -+ -+ /* Are there event queues? */ -+ if (Event->queueHead != gcvNULL) -+ { -+ /* Acquire the command queue. */ -+ gcmkONERROR(gckCOMMAND_EnterCommit(command, FromPower)); -+ commitEntered = gcvTRUE; -+ -+ /* Process all queues. */ -+ while (Event->queueHead != gcvNULL) -+ { -+ /* Acquire the list mutex. */ -+ gcmkONERROR(gckOS_AcquireMutex(Event->os, -+ Event->eventListMutex, -+ gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ /* Get the current queue. */ -+ queue = Event->queueHead; -+ -+ /* Allocate an event ID. */ -+ gcmkONERROR(gckEVENT_GetEvent(Event, Wait, &id, queue->head, queue->source)); -+ -+ /* Copy event list to event ID queue. */ -+ Event->queues[id].head = queue->head; -+ -+ /* Remove the top queue from the list. */ -+ if (Event->queueHead == Event->queueTail) -+ { -+ Event->queueHead = gcvNULL; -+ Event->queueTail = gcvNULL; -+ } -+ else -+ { -+ Event->queueHead = Event->queueHead->next; -+ } -+ -+ /* Free the queue. */ -+ gcmkONERROR(gckEVENT_FreeQueue(Event, queue)); -+ -+ /* Release the list mutex. */ -+ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->eventListMutex)); -+ acquired = gcvFALSE; -+ -+ /* Determine cache needed to flush. */ -+ gcmkVERIFY_OK(_QueryFlush(Event, Event->queues[id].head, &flush)); -+ -+#if gcdINTERRUPT_STATISTIC -+ gcmkVERIFY_OK(gckOS_AtomIncrement( -+ Event->os, -+ Event->interruptCount, -+ &oldValue -+ )); -+#endif -+ -+#if gcdNULL_DRIVER -+ /* Notify immediately on infinite hardware. */ -+ gcmkONERROR(gckEVENT_Interrupt(Event, 1 << id)); -+ -+ gcmkONERROR(gckEVENT_Notify(Event, 0)); -+#else -+ /* Get the size of the hardware event. */ -+ gcmkONERROR(gckHARDWARE_Event( -+ hardware, -+ gcvNULL, -+ id, -+ Event->queues[id].source, -+ &bytes -+ )); -+ -+ /* Get the size of flush command. */ -+ gcmkONERROR(gckHARDWARE_Flush( -+ hardware, -+ flush, -+ gcvNULL, -+ &flushBytes -+ )); -+ -+ bytes += flushBytes; -+ -+ /* Total bytes need to execute. */ -+ executeBytes = bytes; -+ -+ /* Reserve space in the command queue. */ -+ gcmkONERROR(gckCOMMAND_Reserve(command, bytes, &buffer, &bytes)); -+ -+ /* Set the flush in the command queue. */ -+ gcmkONERROR(gckHARDWARE_Flush( -+ hardware, -+ flush, -+ buffer, -+ &flushBytes -+ )); -+ -+ /* Advance to next command. */ -+ buffer = (gctUINT8_PTR)buffer + flushBytes; -+ -+ /* Set the hardware event in the command queue. */ -+ gcmkONERROR(gckHARDWARE_Event( -+ hardware, -+ buffer, -+ id, -+ Event->queues[id].source, -+ &bytes -+ )); -+ -+ /* Advance to next command. */ -+ buffer = (gctUINT8_PTR)buffer + bytes; -+ -+ /* Execute the hardware event. */ -+ gcmkONERROR(gckCOMMAND_Execute(command, executeBytes)); -+#endif -+ } -+ -+ /* Release the command queue. */ -+ gcmkONERROR(gckCOMMAND_ExitCommit(command, FromPower)); -+ -+#if !gcdNULL_DRIVER -+ if (!FromCommand) -+ gcmkVERIFY_OK(_TryToIdleGPU(Event)); -+#endif -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (acquired) -+ { -+ /* Need to unroll the mutex acquire. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->eventListMutex)); -+ } -+ -+ if (commitEntered) -+ { -+ /* Release the command queue mutex. */ -+ gcmkVERIFY_OK(gckCOMMAND_ExitCommit(command, FromPower)); -+ } -+ -+ if (id != 0xFF) -+ { -+ /* Need to unroll the event allocation. */ -+ Event->queues[id].head = gcvNULL; -+ } -+ -+ if (status == gcvSTATUS_GPU_NOT_RESPONDING) -+ { -+ /* Broadcast GPU stuck. */ -+ status = gckOS_Broadcast(Event->os, -+ Event->kernel->hardware, -+ gcvBROADCAST_GPU_STUCK); -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckEVENT_Commit -+** -+** Commit an event queue from the user. -+** -+** INPUT: -+** -+** gckEVENT Event -+** Pointer to an gckEVENT object. -+** -+** gcsQUEUE_PTR Queue -+** User event queue. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckEVENT_Commit( -+ IN gckEVENT Event, -+ IN gcsQUEUE_PTR Queue -+ ) -+{ -+ gceSTATUS status; -+ gcsQUEUE_PTR record = gcvNULL, next; -+ gctUINT32 processID; -+ gctBOOL needCopy = gcvFALSE; -+ -+ gcmkHEADER_ARG("Event=0x%x Queue=0x%x", Event, Queue); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT); -+ -+ /* Get the current process ID. */ -+ gcmkONERROR(gckOS_GetProcessID(&processID)); -+ -+ /* Query if we need to copy the client data. */ -+ gcmkONERROR(gckOS_QueryNeedCopy(Event->os, processID, &needCopy)); -+ -+ /* Loop while there are records in the queue. */ -+ while (Queue != gcvNULL) -+ { -+ gcsQUEUE queue; -+ -+ if (needCopy) -+ { -+ /* Point to stack record. */ -+ record = &queue; -+ -+ /* Copy the data from the client. */ -+ gcmkONERROR(gckOS_CopyFromUserData(Event->os, -+ record, -+ Queue, -+ gcmSIZEOF(gcsQUEUE))); -+ } -+ else -+ { -+ gctPOINTER pointer = gcvNULL; -+ -+ /* Map record into kernel memory. */ -+ gcmkONERROR(gckOS_MapUserPointer(Event->os, -+ Queue, -+ gcmSIZEOF(gcsQUEUE), -+ &pointer)); -+ -+ record = pointer; -+ } -+ -+ /* Append event record to event queue. */ -+ gcmkONERROR( -+ gckEVENT_AddList(Event, &record->iface, gcvKERNEL_PIXEL, gcvTRUE, gcvFALSE)); -+ -+ /* Next record in the queue. */ -+ next = gcmUINT64_TO_PTR(record->next); -+ -+ if (!needCopy) -+ { -+ /* Unmap record from kernel memory. */ -+ gcmkONERROR( -+ gckOS_UnmapUserPointer(Event->os, -+ Queue, -+ gcmSIZEOF(gcsQUEUE), -+ (gctPOINTER *) record)); -+ record = gcvNULL; -+ } -+ -+ Queue = next; -+ } -+ -+ /* Submit the event list. */ -+ gcmkONERROR(gckEVENT_Submit(Event, gcvTRUE, gcvFALSE, gcvFALSE)); -+ -+ /* Success */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if ((record != gcvNULL) && !needCopy) -+ { -+ /* Roll back. */ -+ gcmkVERIFY_OK(gckOS_UnmapUserPointer(Event->os, -+ Queue, -+ gcmSIZEOF(gcsQUEUE), -+ (gctPOINTER *) record)); -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckEVENT_Compose -+** -+** Schedule a composition event and start a composition. -+** -+** INPUT: -+** -+** gckEVENT Event -+** Pointer to an gckEVENT object. -+** -+** gcsHAL_COMPOSE_PTR Info -+** Pointer to the composition structure. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckEVENT_Compose( -+ IN gckEVENT Event, -+ IN gcsHAL_COMPOSE_PTR Info -+ ) -+{ -+ gceSTATUS status; -+ gcsEVENT_PTR headRecord; -+ gcsEVENT_PTR tailRecord; -+ gcsEVENT_PTR tempRecord; -+ gctUINT8 id = 0xFF; -+ gctUINT32 processID; -+ -+ gcmkHEADER_ARG("Event=0x%x Info=0x%x", Event, Info); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT); -+ gcmkVERIFY_ARGUMENT(Info != gcvNULL); -+ -+ /* Get process ID. */ -+ gcmkONERROR(gckOS_GetProcessID(&processID)); -+ -+ /* Allocate a record. */ -+ gcmkONERROR(gckEVENT_AllocateRecord(Event, gcvTRUE, &tempRecord)); -+ headRecord = tailRecord = tempRecord; -+ -+ /* Initialize the record. */ -+ tempRecord->info.command = gcvHAL_SIGNAL; -+ tempRecord->info.u.Signal.process = Info->process; -+ tempRecord->info.u.Signal.signal = Info->signal; -+ tempRecord->info.u.Signal.auxSignal = 0; -+ tempRecord->next = gcvNULL; -+ tempRecord->processID = processID; -+ -+ /* Allocate another record for user signal #1. */ -+ if (gcmUINT64_TO_PTR(Info->userSignal1) != gcvNULL) -+ { -+ /* Allocate a record. */ -+ gcmkONERROR(gckEVENT_AllocateRecord(Event, gcvTRUE, &tempRecord)); -+ tailRecord->next = tempRecord; -+ tailRecord = tempRecord; -+ -+ /* Initialize the record. */ -+ tempRecord->info.command = gcvHAL_SIGNAL; -+ tempRecord->info.u.Signal.process = Info->userProcess; -+ tempRecord->info.u.Signal.signal = Info->userSignal1; -+ tempRecord->info.u.Signal.auxSignal = 0; -+ tempRecord->next = gcvNULL; -+ tempRecord->processID = processID; -+ } -+ -+ /* Allocate another record for user signal #2. */ -+ if (gcmUINT64_TO_PTR(Info->userSignal2) != gcvNULL) -+ { -+ /* Allocate a record. */ -+ gcmkONERROR(gckEVENT_AllocateRecord(Event, gcvTRUE, &tempRecord)); -+ tailRecord->next = tempRecord; -+ -+ /* Initialize the record. */ -+ tempRecord->info.command = gcvHAL_SIGNAL; -+ tempRecord->info.u.Signal.process = Info->userProcess; -+ tempRecord->info.u.Signal.signal = Info->userSignal2; -+ tempRecord->info.u.Signal.auxSignal = 0; -+ tempRecord->next = gcvNULL; -+ tempRecord->processID = processID; -+ } -+ -+ /* Allocate an event ID. */ -+ gcmkONERROR(gckEVENT_GetEvent(Event, gcvTRUE, &id, headRecord, gcvKERNEL_PIXEL)); -+ -+ /* Start composition. */ -+ gcmkONERROR(gckHARDWARE_Compose( -+ Event->kernel->hardware, processID, -+ gcmUINT64_TO_PTR(Info->physical), gcmUINT64_TO_PTR(Info->logical), Info->offset, Info->size, id -+ )); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckEVENT_Interrupt -+** -+** Called by the interrupt service routine to store the triggered interrupt -+** mask to be later processed by gckEVENT_Notify. -+** -+** INPUT: -+** -+** gckEVENT Event -+** Pointer to an gckEVENT object. -+** -+** gctUINT32 Data -+** Mask for the 32 interrupts. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckEVENT_Interrupt( -+ IN gckEVENT Event, -+ IN gctUINT32 Data -+ ) -+{ -+ unsigned long flags; -+ gcmkHEADER_ARG("Event=0x%x Data=0x%x", Event, Data); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT); -+ -+ if (Data & 0x20000000) -+ { -+ gckENTRYDATA data; -+ gctUINT32 idle; -+ Data &= ~0x20000000; -+ -+ /* Get first entry information. */ -+ gcmkVERIFY_OK( -+ gckENTRYQUEUE_Dequeue(&Event->kernel->command->queue, &data)); -+ -+ /* Make sure FE is idle. */ -+ do -+ { -+ gcmkVERIFY_OK(gckOS_ReadRegisterEx( -+ Event->os, -+ Event->kernel->core, -+ 0x4, -+ &idle)); -+ } -+ while (idle != 0x7FFFFFFF); -+ -+ /* Start Command Parser. */ -+ gcmkVERIFY_OK(gckHARDWARE_Execute( -+ Event->kernel->hardware, -+ data->physical, -+ data->bytes -+ )); -+ } -+ -+ /* Combine current interrupt status with pending flags. */ -+ spin_lock_irqsave(&Event->kernel->irq_lock, flags); -+#if gcdSMP -+ gckOS_AtomSetMask(Event->pending, Data); -+#else -+ Event->pending |= Data; -+#endif -+ spin_unlock_irqrestore(&Event->kernel->irq_lock, flags); -+ -+#if gcdINTERRUPT_STATISTIC -+ { -+ gctINT j = 0; -+ gctINT32 oldValue; -+ -+ for (j = 0; j < gcmCOUNTOF(Event->queues); j++) -+ { -+ if ((Data & (1 << j))) -+ { -+ gcmkVERIFY_OK(gckOS_AtomDecrement(Event->os, -+ Event->interruptCount, -+ &oldValue)); -+ } -+ } -+ } -+#endif -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckEVENT_Notify -+** -+** Process all triggered interrupts. -+** -+** INPUT: -+** -+** gckEVENT Event -+** Pointer to an gckEVENT object. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckEVENT_Notify( -+ IN gckEVENT Event, -+ IN gctUINT32 IDs -+ ) -+{ -+ gceSTATUS status = gcvSTATUS_OK; -+ gctINT i; -+ gcsEVENT_QUEUE * queue; -+ gctUINT mask = 0; -+ gctBOOL acquired = gcvFALSE; -+ gctPOINTER info; -+ gctSIGNAL signal; -+ gctUINT pending = 0; -+ gckKERNEL kernel = Event->kernel; -+#if gcmIS_DEBUG(gcdDEBUG_TRACE) -+ gctINT eventNumber = 0; -+#endif -+ gctINT32 free; -+ gckVIDMEM_NODE nodeObject; -+ gcuVIDMEM_NODE_PTR node; -+ unsigned long flags; -+ -+ gcmkHEADER_ARG("Event=0x%x IDs=0x%x", Event, IDs); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT); -+ -+ gcmDEBUG_ONLY( -+ if (IDs != 0) -+ { -+ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i) -+ { -+ if (Event->queues[i].head != gcvNULL) -+ { -+ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT, -+ "Queue(%d): stamp=%llu source=%d", -+ i, -+ Event->queues[i].stamp, -+ Event->queues[i].source); -+ } -+ } -+ } -+ ); -+ -+ for (;;) -+ { -+ gcsEVENT_PTR record; -+ -+ spin_lock_irqsave(&Event->kernel->irq_lock, flags); -+#if gcdSMP -+ gckOS_AtomGet(Event->os, Event->pending, (gctINT32_PTR)&pending); -+#else -+ pending = Event->pending; -+#endif -+ spin_unlock_irqrestore(&Event->kernel->irq_lock, flags); -+ -+ if (pending & 0x80000000) -+ { -+ gctUINT32 AQAxiStatus = 0; -+ gckOS_ReadRegisterEx(Event->os, Event->kernel->hardware->core, 0xC, &AQAxiStatus); -+ -+ gcmkPRINT("GPU[%d]: AXI BUS ERROR, AQAxiStatus=0x%x\n", Event->kernel->hardware->core, AQAxiStatus); -+ pending &= 0x7FFFFFFF; -+ } -+ -+ if (pending & 0x40000000) -+ { -+ gckHARDWARE_DumpMMUException(Event->kernel->hardware); -+ -+ pending &= 0xBFFFFFFF; -+ } -+ -+ if (pending == 0) -+ { -+ /* No more pending interrupts - done. */ -+ break; -+ } -+ -+ gcmkTRACE_ZONE_N( -+ gcvLEVEL_INFO, gcvZONE_EVENT, -+ gcmSIZEOF(pending), -+ "Pending interrupts 0x%x", -+ pending -+ ); -+ -+ queue = gcvNULL; -+ -+ /* Grab the mutex queue. */ -+ gcmkONERROR(gckOS_AcquireMutex(Event->os, -+ Event->eventQueueMutex, -+ gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ gcmDEBUG_ONLY( -+ if (IDs == 0) -+ { -+ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i) -+ { -+ if (Event->queues[i].head != gcvNULL) -+ { -+ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT, -+ "Queue(%d): stamp=%llu source=%d", -+ i, -+ Event->queues[i].stamp, -+ Event->queues[i].source); -+ } -+ } -+ } -+ ); -+ -+ /* Find the oldest pending interrupt. */ -+ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i) -+ { -+ if ((Event->queues[i].head != gcvNULL) -+ && (pending & (1 << i)) -+ ) -+ { -+ if ((queue == gcvNULL) -+ || (Event->queues[i].stamp < queue->stamp) -+ ) -+ { -+ queue = &Event->queues[i]; -+ mask = 1 << i; -+#if gcmIS_DEBUG(gcdDEBUG_TRACE) -+ eventNumber = i; -+#endif -+ } -+ } -+ } -+ -+ if (queue == gcvNULL) -+ { -+ gcmkTRACE_ZONE_N( -+ gcvLEVEL_ERROR, gcvZONE_EVENT, -+ gcmSIZEOF(pending), -+ "Interrupts 0x%x are not pending.", -+ pending -+ ); -+ -+ spin_lock_irqsave(&Event->kernel->irq_lock, flags); -+#if gcdSMP -+ gckOS_AtomClearMask(Event->pending, pending); -+#else -+ Event->pending &= ~pending; -+#endif -+ spin_unlock_irqrestore(&Event->kernel->irq_lock, flags); -+ -+ /* Release the mutex queue. */ -+ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex)); -+ acquired = gcvFALSE; -+ break; -+ } -+ -+ /* Check whether there is a missed interrupt. */ -+ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i) -+ { -+ if ((Event->queues[i].head != gcvNULL) -+ && (Event->queues[i].stamp < queue->stamp) -+ && (Event->queues[i].source <= queue->source) -+ ) -+ { -+ gcmkTRACE_N( -+ gcvLEVEL_ERROR, -+ gcmSIZEOF(i) + gcmSIZEOF(Event->queues[i].stamp), -+ "Event %d lost (stamp %llu)", -+ i, Event->queues[i].stamp -+ ); -+ -+ /* Use this event instead. */ -+ queue = &Event->queues[i]; -+ mask = 0; -+ } -+ } -+ -+ if (mask != 0) -+ { -+#if gcmIS_DEBUG(gcdDEBUG_TRACE) -+ gcmkTRACE_ZONE_N( -+ gcvLEVEL_INFO, gcvZONE_EVENT, -+ gcmSIZEOF(eventNumber), -+ "Processing interrupt %d", -+ eventNumber -+ ); -+#endif -+ } -+ -+ spin_lock_irqsave(&Event->kernel->irq_lock, flags); -+#if gcdSMP -+ gckOS_AtomClearMask(Event->pending, mask); -+#else -+ Event->pending &= ~mask; -+#endif -+ spin_unlock_irqrestore(&Event->kernel->irq_lock, flags); -+ -+ /* Grab the event head. */ -+ record = queue->head; -+ -+ /* Now quickly clear its event list. */ -+ queue->head = gcvNULL; -+ -+ /* Release the mutex queue. */ -+ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex)); -+ acquired = gcvFALSE; -+ -+ /* Increase the number of free events. */ -+ gcmkONERROR(gckOS_AtomIncrement(Event->os, Event->freeAtom, &free)); -+ -+ /* Walk all events for this interrupt. */ -+ while (record != gcvNULL) -+ { -+ gcsEVENT_PTR recordNext; -+ gctPOINTER logical; -+ -+ /* Grab next record. */ -+ recordNext = record->next; -+ -+ gcmkTRACE_ZONE_N( -+ gcvLEVEL_INFO, gcvZONE_EVENT, -+ gcmSIZEOF(record->info.command), -+ "Processing event type: %d", -+ record->info.command -+ ); -+ -+ switch (record->info.command) -+ { -+ case gcvHAL_FREE_NON_PAGED_MEMORY: -+ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT, -+ "gcvHAL_FREE_NON_PAGED_MEMORY: 0x%x", -+ gcmNAME_TO_PTR(record->info.u.FreeNonPagedMemory.physical)); -+ -+ /* Free non-paged memory. */ -+ status = gckOS_FreeNonPagedMemory( -+ Event->os, -+ (gctSIZE_T) record->info.u.FreeNonPagedMemory.bytes, -+ gcmNAME_TO_PTR(record->info.u.FreeNonPagedMemory.physical), -+ gcmUINT64_TO_PTR(record->info.u.FreeNonPagedMemory.logical)); -+ -+ gcmRELEASE_NAME(record->info.u.FreeNonPagedMemory.physical); -+ break; -+ -+ case gcvHAL_FREE_CONTIGUOUS_MEMORY: -+ gcmkTRACE_ZONE( -+ gcvLEVEL_VERBOSE, gcvZONE_EVENT, -+ "gcvHAL_FREE_CONTIGUOUS_MEMORY: 0x%x", -+ gcmNAME_TO_PTR(record->info.u.FreeContiguousMemory.physical)); -+ -+ /* Unmap the user memory. */ -+ status = gckOS_FreeContiguous( -+ Event->os, -+ gcmNAME_TO_PTR(record->info.u.FreeContiguousMemory.physical), -+ gcmUINT64_TO_PTR(record->info.u.FreeContiguousMemory.logical), -+ (gctSIZE_T) record->info.u.FreeContiguousMemory.bytes); -+ -+ gcmRELEASE_NAME(record->info.u.FreeContiguousMemory.physical); -+ break; -+ -+ case gcvHAL_WRITE_DATA: -+ /* Convert physical into logical address. */ -+ gcmkERR_BREAK( -+ gckOS_MapPhysical(Event->os, -+ record->info.u.WriteData.address, -+ gcmSIZEOF(gctUINT32), -+ &logical)); -+ -+ /* Write data. */ -+ gcmkERR_BREAK( -+ gckOS_WriteMemory(Event->os, -+ logical, -+ record->info.u.WriteData.data)); -+ -+ /* Unmap the physical memory. */ -+ gcmkERR_BREAK( -+ gckOS_UnmapPhysical(Event->os, -+ logical, -+ gcmSIZEOF(gctUINT32))); -+ break; -+ -+ case gcvHAL_UNLOCK_VIDEO_MEMORY: -+ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT, -+ "gcvHAL_UNLOCK_VIDEO_MEMORY: 0x%x", -+ record->info.u.UnlockVideoMemory.node); -+ -+ nodeObject = gcmUINT64_TO_PTR(record->info.u.UnlockVideoMemory.node); -+ -+ node = nodeObject->node; -+ -+ /* Unlock. */ -+ status = gckVIDMEM_Unlock( -+ Event->kernel, -+ nodeObject, -+ record->info.u.UnlockVideoMemory.type, -+ gcvNULL); -+ -+#if gcdPROCESS_ADDRESS_SPACE -+ gcmkVERIFY_OK(gckVIDMEM_NODE_Unlock( -+ Event->kernel, -+ nodeObject, -+ record->processID -+ )); -+#endif -+ -+ status = gckVIDMEM_NODE_Dereference(Event->kernel, nodeObject); -+ break; -+ -+ case gcvHAL_SIGNAL: -+ signal = gcmUINT64_TO_PTR(record->info.u.Signal.signal); -+ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT, -+ "gcvHAL_SIGNAL: 0x%x", -+ signal); -+ -+ /* Set signal. */ -+ if (gcmUINT64_TO_PTR(record->info.u.Signal.process) == gcvNULL) -+ { -+ /* Kernel signal. */ -+ gcmkERR_BREAK( -+ gckOS_Signal(Event->os, -+ signal, -+ gcvTRUE)); -+ } -+ else -+ { -+ /* User signal. */ -+ gcmkERR_BREAK( -+ gckOS_UserSignal(Event->os, -+ signal, -+ gcmUINT64_TO_PTR(record->info.u.Signal.process))); -+ } -+ -+ gcmkASSERT(record->info.u.Signal.auxSignal == 0); -+ break; -+ -+ case gcvHAL_UNMAP_USER_MEMORY: -+ info = gcmNAME_TO_PTR(record->info.u.UnmapUserMemory.info); -+ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT, -+ "gcvHAL_UNMAP_USER_MEMORY: 0x%x", -+ info); -+ -+ /* Unmap the user memory. */ -+ status = gckOS_UnmapUserMemory( -+ Event->os, -+ Event->kernel->core, -+ gcmUINT64_TO_PTR(record->info.u.UnmapUserMemory.memory), -+ (gctSIZE_T) record->info.u.UnmapUserMemory.size, -+ info, -+ record->info.u.UnmapUserMemory.address); -+ -+ gcmRELEASE_NAME(record->info.u.UnmapUserMemory.info); -+ break; -+ -+ case gcvHAL_TIMESTAMP: -+ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT, -+ "gcvHAL_TIMESTAMP: %d %d", -+ record->info.u.TimeStamp.timer, -+ record->info.u.TimeStamp.request); -+ -+ /* Process the timestamp. */ -+ switch (record->info.u.TimeStamp.request) -+ { -+ case 0: -+ status = gckOS_GetTime(&Event->kernel->timers[ -+ record->info.u.TimeStamp.timer]. -+ stopTime); -+ break; -+ -+ case 1: -+ status = gckOS_GetTime(&Event->kernel->timers[ -+ record->info.u.TimeStamp.timer]. -+ startTime); -+ break; -+ -+ default: -+ gcmkTRACE_ZONE_N( -+ gcvLEVEL_ERROR, gcvZONE_EVENT, -+ gcmSIZEOF(record->info.u.TimeStamp.request), -+ "Invalid timestamp request: %d", -+ record->info.u.TimeStamp.request -+ ); -+ -+ status = gcvSTATUS_INVALID_ARGUMENT; -+ break; -+ } -+ break; -+ -+ case gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER: -+ gcmkVERIFY_OK( -+ gckKERNEL_DestroyVirtualCommandBuffer(Event->kernel, -+ (gctSIZE_T) record->info.u.FreeVirtualCommandBuffer.bytes, -+ gcmNAME_TO_PTR(record->info.u.FreeVirtualCommandBuffer.physical), -+ gcmUINT64_TO_PTR(record->info.u.FreeVirtualCommandBuffer.logical) -+ )); -+ gcmRELEASE_NAME(record->info.u.FreeVirtualCommandBuffer.physical); -+ break; -+ -+#if gcdANDROID_NATIVE_FENCE_SYNC -+ case gcvHAL_SYNC_POINT: -+ { -+ gctSYNC_POINT syncPoint; -+ -+ syncPoint = gcmUINT64_TO_PTR(record->info.u.SyncPoint.syncPoint); -+ status = gckOS_SignalSyncPoint(Event->os, syncPoint); -+ } -+ break; -+#endif -+ -+#if gcdPROCESS_ADDRESS_SPACE -+ case gcvHAL_DESTROY_MMU: -+ status = gckMMU_Destroy(gcmUINT64_TO_PTR(record->info.u.DestroyMmu.mmu)); -+ break; -+#endif -+ -+ case gcvHAL_COMMIT_DONE: -+ break; -+ -+ default: -+ /* Invalid argument. */ -+ gcmkTRACE_ZONE_N( -+ gcvLEVEL_ERROR, gcvZONE_EVENT, -+ gcmSIZEOF(record->info.command), -+ "Unknown event type: %d", -+ record->info.command -+ ); -+ -+ status = gcvSTATUS_INVALID_ARGUMENT; -+ break; -+ } -+ -+ /* Make sure there are no errors generated. */ -+ if (gcmIS_ERROR(status)) -+ { -+ gcmkTRACE_ZONE_N( -+ gcvLEVEL_WARNING, gcvZONE_EVENT, -+ gcmSIZEOF(status), -+ "Event produced status: %d(%s)", -+ status, gckOS_DebugStatus2Name(status)); -+ } -+ -+ /* Free the event. */ -+ gcmkVERIFY_OK(gckEVENT_FreeRecord(Event, record)); -+ -+ /* Advance to next record. */ -+ record = recordNext; -+ } -+ -+ gcmkTRACE_ZONE(gcvLEVEL_VERBOSE, gcvZONE_EVENT, -+ "Handled interrupt 0x%x", mask); -+ } -+ -+ if (IDs == 0) -+ { -+ gcmkONERROR(_TryToIdleGPU(Event)); -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (acquired) -+ { -+ /* Release mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex)); -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** gckEVENT_FreeProcess -+** -+** Free all events owned by a particular process ID. -+** -+** INPUT: -+** -+** gckEVENT Event -+** Pointer to an gckEVENT object. -+** -+** gctUINT32 ProcessID -+** Process ID of the process to be freed up. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckEVENT_FreeProcess( -+ IN gckEVENT Event, -+ IN gctUINT32 ProcessID -+ ) -+{ -+ gctSIZE_T i; -+ gctBOOL acquired = gcvFALSE; -+ gcsEVENT_PTR record, next; -+ gceSTATUS status; -+ gcsEVENT_PTR deleteHead, deleteTail; -+ -+ gcmkHEADER_ARG("Event=0x%x ProcessID=%d", Event, ProcessID); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT); -+ -+ /* Walk through all queues. */ -+ for (i = 0; i < gcmCOUNTOF(Event->queues); ++i) -+ { -+ if (Event->queues[i].head != gcvNULL) -+ { -+ /* Grab the event queue mutex. */ -+ gcmkONERROR(gckOS_AcquireMutex(Event->os, -+ Event->eventQueueMutex, -+ gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ /* Grab the mutex head. */ -+ record = Event->queues[i].head; -+ Event->queues[i].head = gcvNULL; -+ Event->queues[i].tail = gcvNULL; -+ deleteHead = gcvNULL; -+ deleteTail = gcvNULL; -+ -+ while (record != gcvNULL) -+ { -+ next = record->next; -+ if (record->processID == ProcessID) -+ { -+ if (deleteHead == gcvNULL) -+ { -+ deleteHead = record; -+ } -+ else -+ { -+ deleteTail->next = record; -+ } -+ -+ deleteTail = record; -+ } -+ else -+ { -+ if (Event->queues[i].head == gcvNULL) -+ { -+ Event->queues[i].head = record; -+ } -+ else -+ { -+ Event->queues[i].tail->next = record; -+ } -+ -+ Event->queues[i].tail = record; -+ } -+ -+ record->next = gcvNULL; -+ record = next; -+ } -+ -+ /* Release the mutex queue. */ -+ gcmkONERROR(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex)); -+ acquired = gcvFALSE; -+ -+ /* Loop through the entire list of events. */ -+ for (record = deleteHead; record != gcvNULL; record = next) -+ { -+ /* Get the next event record. */ -+ next = record->next; -+ -+ /* Free the event record. */ -+ gcmkONERROR(gckEVENT_FreeRecord(Event, record)); -+ } -+ } -+ } -+ -+ gcmkONERROR(_TryToIdleGPU(Event)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Release the event queue mutex. */ -+ if (acquired) -+ { -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Event->os, Event->eventQueueMutex)); -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** gckEVENT_Stop -+** -+** Stop the hardware using the End event mechanism. -+** -+** INPUT: -+** -+** gckEVENT Event -+** Pointer to an gckEVENT object. -+** -+** gctUINT32 ProcessID -+** Process ID Logical belongs. -+** -+** gctPHYS_ADDR Handle -+** Physical address handle. If gcvNULL it is video memory. -+** -+** gctPOINTER Logical -+** Logical address to flush. -+** -+** gctSIGNAL Signal -+** Pointer to the signal to trigger. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckEVENT_Stop( -+ IN gckEVENT Event, -+ IN gctUINT32 ProcessID, -+ IN gctPHYS_ADDR Handle, -+ IN gctPOINTER Logical, -+ IN gctSIGNAL Signal, -+ IN OUT gctUINT32 * waitSize -+ ) -+{ -+ gceSTATUS status; -+ /* gctSIZE_T waitSize;*/ -+ gcsEVENT_PTR record; -+ gctUINT8 id = 0xFF; -+ -+ gcmkHEADER_ARG("Event=0x%x ProcessID=%u Handle=0x%x Logical=0x%x " -+ "Signal=0x%x", -+ Event, ProcessID, Handle, Logical, Signal); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Event, gcvOBJ_EVENT); -+ -+ /* Submit the current event queue. */ -+ gcmkONERROR(gckEVENT_Submit(Event, gcvTRUE, gcvFALSE, gcvFALSE)); -+ -+ /* Allocate a record. */ -+ gcmkONERROR(gckEVENT_AllocateRecord(Event, gcvTRUE, &record)); -+ -+ /* Initialize the record. */ -+ record->next = gcvNULL; -+ record->processID = ProcessID; -+ record->info.command = gcvHAL_SIGNAL; -+ record->info.u.Signal.signal = gcmPTR_TO_UINT64(Signal); -+ record->info.u.Signal.auxSignal = 0; -+ record->info.u.Signal.process = 0; -+ -+ -+ gcmkONERROR(gckEVENT_GetEvent(Event, gcvTRUE, &id, record, gcvKERNEL_PIXEL)); -+ -+ /* Replace last WAIT with END. */ -+ gcmkONERROR(gckHARDWARE_End( -+ Event->kernel->hardware, Logical, waitSize -+ )); -+ -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ /* Flush the cache for the END. */ -+ gcmkONERROR(gckOS_CacheClean( -+ Event->os, -+ ProcessID, -+ gcvNULL, -+ (gctUINT32)Handle, -+ Logical, -+ *waitSize -+ )); -+#endif -+ -+ /* Wait for the signal. */ -+ gcmkONERROR(gckOS_WaitSignal(Event->os, Signal, gcvINFINITE)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+static void -+_PrintRecord( -+ gcsEVENT_PTR record -+ ) -+{ -+ switch (record->info.command) -+ { -+ case gcvHAL_FREE_NON_PAGED_MEMORY: -+ gcmkPRINT(" gcvHAL_FREE_NON_PAGED_MEMORY"); -+ break; -+ -+ case gcvHAL_FREE_CONTIGUOUS_MEMORY: -+ gcmkPRINT(" gcvHAL_FREE_CONTIGUOUS_MEMORY"); -+ break; -+ -+ case gcvHAL_WRITE_DATA: -+ gcmkPRINT(" gcvHAL_WRITE_DATA"); -+ break; -+ -+ case gcvHAL_UNLOCK_VIDEO_MEMORY: -+ gcmkPRINT(" gcvHAL_UNLOCK_VIDEO_MEMORY"); -+ break; -+ -+ case gcvHAL_SIGNAL: -+ gcmkPRINT(" gcvHAL_SIGNAL process=%d signal=0x%x", -+ record->info.u.Signal.process, -+ record->info.u.Signal.signal); -+ break; -+ -+ case gcvHAL_UNMAP_USER_MEMORY: -+ gcmkPRINT(" gcvHAL_UNMAP_USER_MEMORY"); -+ break; -+ -+ case gcvHAL_TIMESTAMP: -+ gcmkPRINT(" gcvHAL_TIMESTAMP"); -+ break; -+ -+ case gcvHAL_COMMIT_DONE: -+ gcmkPRINT(" gcvHAL_COMMIT_DONE"); -+ break; -+ -+ case gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER: -+ gcmkPRINT(" gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER logical=0x%08x", -+ record->info.u.FreeVirtualCommandBuffer.logical); -+ break; -+ -+ case gcvHAL_SYNC_POINT: -+ gcmkPRINT(" gcvHAL_SYNC_POINT syncPoint=0x%08x", -+ gcmUINT64_TO_PTR(record->info.u.SyncPoint.syncPoint)); -+ -+ break; -+ -+ case gcvHAL_DESTROY_MMU: -+ gcmkPRINT(" gcvHAL_DESTORY_MMU mmu=0x%08x", -+ gcmUINT64_TO_PTR(record->info.u.DestroyMmu.mmu)); -+ -+ break; -+ default: -+ gcmkPRINT(" Illegal Event %d", record->info.command); -+ break; -+ } -+} -+ -+/******************************************************************************* -+** gckEVENT_Dump -+** -+** Dump record in event queue when stuck happens. -+** No protection for the event queue. -+**/ -+gceSTATUS -+gckEVENT_Dump( -+ IN gckEVENT Event -+ ) -+{ -+ gcsEVENT_QUEUE_PTR queueHead = Event->queueHead; -+ gcsEVENT_QUEUE_PTR queue; -+ gcsEVENT_PTR record = gcvNULL; -+ gctINT i; -+#if gcdINTERRUPT_STATISTIC -+ gctINT32 pendingInterrupt; -+ gctUINT32 intrAcknowledge; -+#endif -+ -+ gcmkHEADER_ARG("Event=0x%x", Event); -+ -+ gcmkPRINT("**************************\n"); -+ gcmkPRINT("*** EVENT STATE DUMP ***\n"); -+ gcmkPRINT("**************************\n"); -+ -+ gcmkPRINT(" Unsumbitted Event:"); -+ while(queueHead) -+ { -+ queue = queueHead; -+ record = queueHead->head; -+ -+ gcmkPRINT(" [%x]:", queue); -+ while(record) -+ { -+ _PrintRecord(record); -+ record = record->next; -+ } -+ -+ if (queueHead == Event->queueTail) -+ { -+ queueHead = gcvNULL; -+ } -+ else -+ { -+ queueHead = queueHead->next; -+ } -+ } -+ -+ gcmkPRINT(" Untriggered Event:"); -+ for (i = 0; i < gcmCOUNTOF(Event->queues); i++) -+ { -+ queue = &Event->queues[i]; -+ record = queue->head; -+ -+ gcmkPRINT(" [%d]:", i); -+ while(record) -+ { -+ _PrintRecord(record); -+ record = record->next; -+ } -+ } -+ -+#if gcdINTERRUPT_STATISTIC -+ gckOS_AtomGet(Event->os, Event->interruptCount, &pendingInterrupt); -+ gcmkPRINT(" Number of Pending Interrupt: %d", pendingInterrupt); -+ -+ if (Event->kernel->recovery == 0) -+ { -+ gckOS_ReadRegisterEx( -+ Event->os, -+ Event->kernel->core, -+ 0x10, -+ &intrAcknowledge -+ ); -+ -+ gcmkPRINT(" INTR_ACKNOWLEDGE=0x%x", intrAcknowledge); -+ } -+#endif -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel.h linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel.h ---- linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel.h 2015-11-30 17:56:13.576137991 +0100 -@@ -0,0 +1,1353 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#ifndef __gc_hal_kernel_h_ -+#define __gc_hal_kernel_h_ -+ -+#include -+ -+#include "gc_hal.h" -+#include "gc_hal_kernel_hardware.h" -+#include "gc_hal_driver.h" -+ -+#if gcdENABLE_VG -+#include "gc_hal_kernel_vg.h" -+#endif -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+ -+/******************************************************************************* -+***** New MMU Defination *******************************************************/ -+#define gcdMMU_MTLB_SHIFT 22 -+#define gcdMMU_STLB_4K_SHIFT 12 -+#define gcdMMU_STLB_64K_SHIFT 16 -+ -+#define gcdMMU_MTLB_BITS (32 - gcdMMU_MTLB_SHIFT) -+#define gcdMMU_PAGE_4K_BITS gcdMMU_STLB_4K_SHIFT -+#define gcdMMU_STLB_4K_BITS (32 - gcdMMU_MTLB_BITS - gcdMMU_PAGE_4K_BITS) -+#define gcdMMU_PAGE_64K_BITS gcdMMU_STLB_64K_SHIFT -+#define gcdMMU_STLB_64K_BITS (32 - gcdMMU_MTLB_BITS - gcdMMU_PAGE_64K_BITS) -+ -+#define gcdMMU_MTLB_ENTRY_NUM (1 << gcdMMU_MTLB_BITS) -+#define gcdMMU_MTLB_SIZE (gcdMMU_MTLB_ENTRY_NUM << 2) -+#define gcdMMU_STLB_4K_ENTRY_NUM (1 << gcdMMU_STLB_4K_BITS) -+#define gcdMMU_STLB_4K_SIZE (gcdMMU_STLB_4K_ENTRY_NUM << 2) -+#define gcdMMU_PAGE_4K_SIZE (1 << gcdMMU_STLB_4K_SHIFT) -+#define gcdMMU_STLB_64K_ENTRY_NUM (1 << gcdMMU_STLB_64K_BITS) -+#define gcdMMU_STLB_64K_SIZE (gcdMMU_STLB_64K_ENTRY_NUM << 2) -+#define gcdMMU_PAGE_64K_SIZE (1 << gcdMMU_STLB_64K_SHIFT) -+ -+#define gcdMMU_MTLB_MASK (~((1U << gcdMMU_MTLB_SHIFT)-1)) -+#define gcdMMU_STLB_4K_MASK ((~0U << gcdMMU_STLB_4K_SHIFT) ^ gcdMMU_MTLB_MASK) -+#define gcdMMU_PAGE_4K_MASK (gcdMMU_PAGE_4K_SIZE - 1) -+#define gcdMMU_STLB_64K_MASK ((~((1U << gcdMMU_STLB_64K_SHIFT)-1)) ^ gcdMMU_MTLB_MASK) -+#define gcdMMU_PAGE_64K_MASK (gcdMMU_PAGE_64K_SIZE - 1) -+ -+/* Page offset definitions. */ -+#define gcdMMU_OFFSET_4K_BITS (32 - gcdMMU_MTLB_BITS - gcdMMU_STLB_4K_BITS) -+#define gcdMMU_OFFSET_4K_MASK ((1U << gcdMMU_OFFSET_4K_BITS) - 1) -+#define gcdMMU_OFFSET_16K_BITS (32 - gcdMMU_MTLB_BITS - gcdMMU_STLB_16K_BITS) -+#define gcdMMU_OFFSET_16K_MASK ((1U << gcdMMU_OFFSET_16K_BITS) - 1) -+ -+#define gcdMMU_MTLB_PRESENT 0x00000001 -+#define gcdMMU_MTLB_EXCEPTION 0x00000002 -+#define gcdMMU_MTLB_4K_PAGE 0x00000000 -+ -+#define gcdMMU_STLB_PRESENT 0x00000001 -+#define gcdMMU_STLB_EXCEPTION 0x00000002 -+#define gcdMMU_STLB_4K_PAGE 0x00000000 -+ -+/******************************************************************************* -+***** Stuck Dump Level ********************************************************/ -+ -+#define gcdSTUCK_DUMP_MINIMAL 1 -+#define gcdSTUCK_DUMP_MIDDLE 2 -+#define gcdSTUCK_DUMP_MAXIMAL 3 -+ -+/******************************************************************************* -+***** Process Secure Cache ****************************************************/ -+ -+#define gcdSECURE_CACHE_LRU 1 -+#define gcdSECURE_CACHE_LINEAR 2 -+#define gcdSECURE_CACHE_HASH 3 -+#define gcdSECURE_CACHE_TABLE 4 -+ -+#define gcvPAGE_TABLE_DIRTY_BIT_OTHER (1 << 0) -+#define gcvPAGE_TABLE_DIRTY_BIT_FE (1 << 1) -+ -+typedef struct _gcskLOGICAL_CACHE * gcskLOGICAL_CACHE_PTR; -+typedef struct _gcskLOGICAL_CACHE gcskLOGICAL_CACHE; -+struct _gcskLOGICAL_CACHE -+{ -+ /* Logical address. */ -+ gctPOINTER logical; -+ -+ /* DMAable address. */ -+ gctUINT32 dma; -+ -+#if gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_HASH -+ /* Pointer to the previous and next hash tables. */ -+ gcskLOGICAL_CACHE_PTR nextHash; -+ gcskLOGICAL_CACHE_PTR prevHash; -+#endif -+ -+#if gcdSECURE_CACHE_METHOD != gcdSECURE_CACHE_TABLE -+ /* Pointer to the previous and next slot. */ -+ gcskLOGICAL_CACHE_PTR next; -+ gcskLOGICAL_CACHE_PTR prev; -+#endif -+ -+#if gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_LINEAR -+ /* Time stamp. */ -+ gctUINT64 stamp; -+#endif -+}; -+ -+typedef struct _gcskSECURE_CACHE * gcskSECURE_CACHE_PTR; -+typedef struct _gcskSECURE_CACHE -+{ -+ /* Cache memory. */ -+ gcskLOGICAL_CACHE cache[1 + gcdSECURE_CACHE_SLOTS]; -+ -+ /* Last known index for LINEAR mode. */ -+ gcskLOGICAL_CACHE_PTR cacheIndex; -+ -+ /* Current free slot for LINEAR mode. */ -+ gctUINT32 cacheFree; -+ -+ /* Time stamp for LINEAR mode. */ -+ gctUINT64 cacheStamp; -+ -+#if gcdSECURE_CACHE_METHOD == gcdSECURE_CACHE_HASH -+ /* Hash table for HASH mode. */ -+ gcskLOGICAL_CACHE hash[256]; -+#endif -+} -+gcskSECURE_CACHE; -+ -+/******************************************************************************* -+***** Process Database Management *********************************************/ -+ -+typedef enum _gceDATABASE_TYPE -+{ -+ gcvDB_VIDEO_MEMORY = 1, /* Video memory created. */ -+ gcvDB_COMMAND_BUFFER, /* Command Buffer. */ -+ gcvDB_NON_PAGED, /* Non paged memory. */ -+ gcvDB_CONTIGUOUS, /* Contiguous memory. */ -+ gcvDB_SIGNAL, /* Signal. */ -+ gcvDB_VIDEO_MEMORY_LOCKED, /* Video memory locked. */ -+ gcvDB_CONTEXT, /* Context */ -+ gcvDB_IDLE, /* GPU idle. */ -+ gcvDB_MAP_MEMORY, /* Map memory */ -+ gcvDB_MAP_USER_MEMORY, /* Map user memory */ -+ gcvDB_SYNC_POINT, /* Sync point. */ -+ gcvDB_SHBUF, /* Shared buffer. */ -+} -+gceDATABASE_TYPE; -+ -+#define gcdDATABASE_TYPE_MASK 0x000000FF -+#define gcdDB_VIDEO_MEMORY_TYPE_MASK 0x0000FF00 -+#define gcdDB_VIDEO_MEMORY_TYPE_SHIFT 8 -+ -+#define gcdDB_VIDEO_MEMORY_POOL_MASK 0x00FF0000 -+#define gcdDB_VIDEO_MEMORY_POOL_SHIFT 16 -+ -+typedef struct _gcsDATABASE_RECORD * gcsDATABASE_RECORD_PTR; -+typedef struct _gcsDATABASE_RECORD -+{ -+ /* Pointer to kernel. */ -+ gckKERNEL kernel; -+ -+ /* Pointer to next database record. */ -+ gcsDATABASE_RECORD_PTR next; -+ -+ /* Type of record. */ -+ gceDATABASE_TYPE type; -+ -+ /* Data for record. */ -+ gctPOINTER data; -+ gctPHYS_ADDR physical; -+ gctSIZE_T bytes; -+} -+gcsDATABASE_RECORD; -+ -+typedef struct _gcsDATABASE * gcsDATABASE_PTR; -+typedef struct _gcsDATABASE -+{ -+ /* Pointer to next entry is hash list. */ -+ gcsDATABASE_PTR next; -+ gctSIZE_T slot; -+ -+ /* Process ID. */ -+ gctUINT32 processID; -+ -+ /* Sizes to query. */ -+ gcsDATABASE_COUNTERS vidMem; -+ gcsDATABASE_COUNTERS nonPaged; -+ gcsDATABASE_COUNTERS contiguous; -+ gcsDATABASE_COUNTERS mapUserMemory; -+ gcsDATABASE_COUNTERS mapMemory; -+ gcsDATABASE_COUNTERS virtualCommandBuffer; -+ -+ gcsDATABASE_COUNTERS vidMemType[gcvSURF_NUM_TYPES]; -+ /* Counter for each video memory pool. */ -+ gcsDATABASE_COUNTERS vidMemPool[gcvPOOL_NUMBER_OF_POOLS]; -+ gctPOINTER counterMutex; -+ -+ /* Idle time management. */ -+ gctUINT64 lastIdle; -+ gctUINT64 idle; -+ -+ /* Pointer to database. */ -+ gcsDATABASE_RECORD_PTR list[48]; -+ -+ gctPOINTER handleDatabase; -+ gctPOINTER handleDatabaseMutex; -+ -+#if gcdPROCESS_ADDRESS_SPACE -+ gckMMU mmu; -+#endif -+} -+gcsDATABASE; -+ -+typedef struct _gcsRECORDER * gckRECORDER; -+ -+typedef struct _gcsFDPRIVATE * gcsFDPRIVATE_PTR; -+typedef struct _gcsFDPRIVATE -+{ -+ gctINT (* release) (gcsFDPRIVATE_PTR Private); -+} -+gcsFDPRIVATE; -+ -+/* Create a process database that will contain all its allocations. */ -+gceSTATUS -+gckKERNEL_CreateProcessDB( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 ProcessID -+ ); -+ -+/* Add a record to the process database. */ -+gceSTATUS -+gckKERNEL_AddProcessDB( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 ProcessID, -+ IN gceDATABASE_TYPE Type, -+ IN gctPOINTER Pointer, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T Size -+ ); -+ -+/* Remove a record to the process database. */ -+gceSTATUS -+gckKERNEL_RemoveProcessDB( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 ProcessID, -+ IN gceDATABASE_TYPE Type, -+ IN gctPOINTER Pointer -+ ); -+ -+/* Destroy the process database. */ -+gceSTATUS -+gckKERNEL_DestroyProcessDB( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 ProcessID -+ ); -+ -+/* Find a record to the process database. */ -+gceSTATUS -+gckKERNEL_FindProcessDB( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 ProcessID, -+ IN gctUINT32 ThreadID, -+ IN gceDATABASE_TYPE Type, -+ IN gctPOINTER Pointer, -+ OUT gcsDATABASE_RECORD_PTR Record -+ ); -+ -+/* Query the process database. */ -+gceSTATUS -+gckKERNEL_QueryProcessDB( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 ProcessID, -+ IN gctBOOL LastProcessID, -+ IN gceDATABASE_TYPE Type, -+ OUT gcuDATABASE_INFO * Info -+ ); -+ -+/* Dump the process database. */ -+gceSTATUS -+gckKERNEL_DumpProcessDB( -+ IN gckKERNEL Kernel -+ ); -+ -+/* Dump the video memory usage for process specified. */ -+gceSTATUS -+gckKERNEL_DumpVidMemUsage( -+ IN gckKERNEL Kernel, -+ IN gctINT32 ProcessID -+ ); -+ -+gceSTATUS -+gckKERNEL_FindDatabase( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 ProcessID, -+ IN gctBOOL LastProcessID, -+ OUT gcsDATABASE_PTR * Database -+ ); -+ -+gceSTATUS -+gckKERNEL_FindHandleDatbase( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 ProcessID, -+ OUT gctPOINTER * HandleDatabase, -+ OUT gctPOINTER * HandleDatabaseMutex -+ ); -+ -+gceSTATUS -+gckKERNEL_GetProcessMMU( -+ IN gckKERNEL Kernel, -+ OUT gckMMU * Mmu -+ ); -+ -+gceSTATUS -+gckKERNEL_SetRecovery( -+ IN gckKERNEL Kernel, -+ IN gctBOOL Recovery, -+ IN gctUINT32 StuckDump -+ ); -+ -+gceSTATUS -+gckMMU_FlatMapping( -+ IN gckMMU Mmu, -+ IN gctUINT32 Physical -+ ); -+ -+gceSTATUS -+gckMMU_GetPageEntry( -+ IN gckMMU Mmu, -+ IN gctUINT32 Address, -+ IN gctUINT32_PTR *PageTable -+ ); -+ -+gceSTATUS -+gckMMU_FreePagesEx( -+ IN gckMMU Mmu, -+ IN gctUINT32 Address, -+ IN gctSIZE_T PageCount -+ ); -+ -+gceSTATUS -+gckKERNEL_CreateIntegerDatabase( -+ IN gckKERNEL Kernel, -+ OUT gctPOINTER * Database -+ ); -+ -+gceSTATUS -+gckKERNEL_DestroyIntegerDatabase( -+ IN gckKERNEL Kernel, -+ IN gctPOINTER Database -+ ); -+ -+gceSTATUS -+gckKERNEL_AllocateIntegerId( -+ IN gctPOINTER Database, -+ IN gctPOINTER Pointer, -+ OUT gctUINT32 * Id -+ ); -+ -+gceSTATUS -+gckKERNEL_FreeIntegerId( -+ IN gctPOINTER Database, -+ IN gctUINT32 Id -+ ); -+ -+gceSTATUS -+gckKERNEL_QueryIntegerId( -+ IN gctPOINTER Database, -+ IN gctUINT32 Id, -+ OUT gctPOINTER * Pointer -+ ); -+ -+/* Pointer rename */ -+gctUINT32 -+gckKERNEL_AllocateNameFromPointer( -+ IN gckKERNEL Kernel, -+ IN gctPOINTER Pointer -+ ); -+ -+gctPOINTER -+gckKERNEL_QueryPointerFromName( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 Name -+ ); -+ -+gceSTATUS -+gckKERNEL_DeleteName( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 Name -+ ); -+ -+/******************************************************************************* -+********* Timer Management ****************************************************/ -+typedef struct _gcsTIMER * gcsTIMER_PTR; -+typedef struct _gcsTIMER -+{ -+ /* Start and Stop time holders. */ -+ gctUINT64 startTime; -+ gctUINT64 stopTime; -+} -+gcsTIMER; -+ -+/******************************************************************************\ -+********************************** Structures ********************************** -+\******************************************************************************/ -+ -+/* gckDB object. */ -+struct _gckDB -+{ -+ /* Database management. */ -+ gcsDATABASE_PTR db[16]; -+ gctPOINTER dbMutex; -+ gcsDATABASE_PTR freeDatabase; -+ gcsDATABASE_RECORD_PTR freeRecord; -+ gcsDATABASE_PTR lastDatabase; -+ gctUINT32 lastProcessID; -+ gctUINT64 lastIdle; -+ gctUINT64 idleTime; -+ gctUINT64 lastSlowdown; -+ gctUINT64 lastSlowdownIdle; -+ gctPOINTER nameDatabase; -+ gctPOINTER nameDatabaseMutex; -+ -+ gctPOINTER pointerDatabase; -+ gctPOINTER pointerDatabaseMutex; -+}; -+ -+typedef struct _gckVIRTUAL_COMMAND_BUFFER * gckVIRTUAL_COMMAND_BUFFER_PTR; -+typedef struct _gckVIRTUAL_COMMAND_BUFFER -+{ -+ gctPHYS_ADDR physical; -+ gctPOINTER userLogical; -+ gctPOINTER kernelLogical; -+ gctSIZE_T bytes; -+ gctSIZE_T pageCount; -+ gctPOINTER pageTable; -+ gctUINT32 gpuAddress; -+ gctUINT pid; -+ gckVIRTUAL_COMMAND_BUFFER_PTR next; -+ gckVIRTUAL_COMMAND_BUFFER_PTR prev; -+ gckKERNEL kernel; -+#if gcdPROCESS_ADDRESS_SPACE -+ gckMMU mmu; -+#endif -+} -+gckVIRTUAL_COMMAND_BUFFER; -+ -+/* gckKERNEL object. */ -+struct _gckKERNEL -+{ -+ /* Object. */ -+ gcsOBJECT object; -+ -+ /* Pointer to gckOS object. */ -+ gckOS os; -+ -+ /* Core */ -+ gceCORE core; -+ -+ /* Pointer to gckHARDWARE object. */ -+ gckHARDWARE hardware; -+ -+ /* Pointer to gckCOMMAND object. */ -+ gckCOMMAND command; -+ -+ /* Pointer to gckEVENT object. */ -+ gckEVENT eventObj; -+ -+ /* Pointer to context. */ -+ gctPOINTER context; -+ -+ /* Pointer to gckMMU object. */ -+ gckMMU mmu; -+ -+ /* Arom holding number of clients. */ -+ gctPOINTER atomClients; -+ -+#if VIVANTE_PROFILER -+ /* Enable profiling */ -+ gctBOOL profileEnable; -+ /* Clear profile register or not*/ -+ gctBOOL profileCleanRegister; -+#endif -+ -+ /* Database management. */ -+ gckDB db; -+ gctBOOL dbCreated; -+ -+ gctUINT64 resetTimeStamp; -+ -+ /* Pointer to gckEVENT object. */ -+ gcsTIMER timers[8]; -+ gctUINT32 timeOut; -+ -+#if gcdENABLE_VG -+ gckVGKERNEL vg; -+#endif -+ -+ /* Virtual command buffer list. */ -+ gckVIRTUAL_COMMAND_BUFFER_PTR virtualBufferHead; -+ gckVIRTUAL_COMMAND_BUFFER_PTR virtualBufferTail; -+ gctPOINTER virtualBufferLock; -+ -+ /* Enable virtual command buffer. */ -+ gctBOOL virtualCommandBuffer; -+ -+#if gcdDVFS -+ gckDVFS dvfs; -+#endif -+ -+#if gcdANDROID_NATIVE_FENCE_SYNC -+ gctHANDLE timeline; -+#endif -+ -+ /* Enable recovery. */ -+ gctBOOL recovery; -+ -+ /* Level of dump information after stuck. */ -+ gctUINT stuckDump; -+ -+ /* Timer to monitor GPU stuck. */ -+ gctPOINTER monitorTimer; -+ -+ /* Flag to quit monitor timer. */ -+ gctBOOL monitorTimerStop; -+ -+ /* Monitor states. */ -+ gctBOOL monitoring; -+ gctUINT32 lastCommitStamp; -+ gctUINT32 timer; -+ gctUINT32 restoreAddress; -+ gctUINT32 restoreMask; -+ -+ spinlock_t irq_lock; -+}; -+ -+struct _FrequencyHistory -+{ -+ gctUINT32 frequency; -+ gctUINT32 count; -+}; -+ -+/* gckDVFS object. */ -+struct _gckDVFS -+{ -+ gckOS os; -+ gckHARDWARE hardware; -+ gctPOINTER timer; -+ gctUINT32 pollingTime; -+ gctBOOL stop; -+ gctUINT32 totalConfig; -+ gctUINT32 loads[8]; -+ gctUINT8 currentScale; -+ struct _FrequencyHistory frequencyHistory[16]; -+}; -+ -+/* gckCOMMAND object. */ -+struct _gckCOMMAND -+{ -+ /* Object. */ -+ gcsOBJECT object; -+ -+ /* Pointer to required object. */ -+ gckKERNEL kernel; -+ gckOS os; -+ -+ /* Number of bytes per page. */ -+ gctUINT32 pageSize; -+ -+ /* Current pipe select. */ -+ gcePIPE_SELECT pipeSelect; -+ -+ /* Command queue running flag. */ -+ gctBOOL running; -+ -+ /* Idle flag and commit stamp. */ -+ gctBOOL idle; -+ gctUINT64 commitStamp; -+ -+ /* Command queue mutex. */ -+ gctPOINTER mutexQueue; -+ -+ /* Context switching mutex. */ -+ gctPOINTER mutexContext; -+ -+#if VIVANTE_PROFILER_CONTEXT -+ /* Context sequence mutex. */ -+ gctPOINTER mutexContextSeq; -+#endif -+ -+ /* Command queue power semaphore. */ -+ gctPOINTER powerSemaphore; -+ -+ /* Current command queue. */ -+ struct _gcskCOMMAND_QUEUE -+ { -+ gctSIGNAL signal; -+ gctPHYS_ADDR physical; -+ gctPOINTER logical; -+ gctUINT32 address; -+ } -+ queues[gcdCOMMAND_QUEUES]; -+ -+ gctPHYS_ADDR physical; -+ gctPOINTER logical; -+ gctUINT32 address; -+ gctUINT32 offset; -+ gctINT index; -+#if gcmIS_DEBUG(gcdDEBUG_TRACE) -+ gctUINT wrapCount; -+#endif -+ -+ /* The command queue is new. */ -+ gctBOOL newQueue; -+ -+ /* Context management. */ -+ gckCONTEXT currContext; -+ -+ /* Pointer to last WAIT command. */ -+ gctPHYS_ADDR waitPhysical; -+ gctPOINTER waitLogical; -+ gctUINT32 waitSize; -+ -+ /* Command buffer alignment. */ -+ gctUINT32 alignment; -+ gctUINT32 reservedHead; -+ gctUINT32 reservedTail; -+ -+ /* Commit counter. */ -+ gctPOINTER atomCommit; -+ -+ /* Kernel process ID. */ -+ gctUINT32 kernelProcessID; -+ -+ /* End Event signal. */ -+ gctSIGNAL endEventSignal; -+ -+#if gcdPROCESS_ADDRESS_SPACE -+ gckMMU currentMmu; -+#endif -+ struct _gckENTRYQUEUE queue; -+}; -+ -+typedef struct _gcsEVENT * gcsEVENT_PTR; -+ -+/* Structure holding one event to be processed. */ -+typedef struct _gcsEVENT -+{ -+ /* Pointer to next event in queue. */ -+ gcsEVENT_PTR next; -+ -+ /* Event information. */ -+ gcsHAL_INTERFACE info; -+ -+ /* Process ID owning the event. */ -+ gctUINT32 processID; -+ -+ gctBOOL fromKernel; -+} -+gcsEVENT; -+ -+/* Structure holding a list of events to be processed by an interrupt. */ -+typedef struct _gcsEVENT_QUEUE * gcsEVENT_QUEUE_PTR; -+typedef struct _gcsEVENT_QUEUE -+{ -+ /* Time stamp. */ -+ gctUINT64 stamp; -+ -+ /* Source of the event. */ -+ gceKERNEL_WHERE source; -+ -+ /* Pointer to head of event queue. */ -+ gcsEVENT_PTR head; -+ -+ /* Pointer to tail of event queue. */ -+ gcsEVENT_PTR tail; -+ -+ /* Next list of events. */ -+ gcsEVENT_QUEUE_PTR next; -+} -+gcsEVENT_QUEUE; -+ -+/* -+ gcdREPO_LIST_COUNT defines the maximum number of event queues with different -+ hardware module sources that may coexist at the same time. Only two sources -+ are supported - gcvKERNEL_COMMAND and gcvKERNEL_PIXEL. gcvKERNEL_COMMAND -+ source is used only for managing the kernel command queue and is only issued -+ when the current command queue gets full. Since we commit event queues every -+ time we commit command buffers, in the worst case we can have up to three -+ pending event queues: -+ - gcvKERNEL_PIXEL -+ - gcvKERNEL_COMMAND (queue overflow) -+ - gcvKERNEL_PIXEL -+*/ -+#define gcdREPO_LIST_COUNT 3 -+ -+/* gckEVENT object. */ -+struct _gckEVENT -+{ -+ /* The object. */ -+ gcsOBJECT object; -+ -+ /* Pointer to required objects. */ -+ gckOS os; -+ gckKERNEL kernel; -+ -+ /* Time stamp. */ -+ gctUINT64 stamp; -+ gctUINT32 lastCommitStamp; -+ -+ /* Queue mutex. */ -+ gctPOINTER eventQueueMutex; -+ -+ /* Array of event queues. */ -+ gcsEVENT_QUEUE queues[29]; -+ gctUINT8 lastID; -+ gctPOINTER freeAtom; -+ -+ /* Pending events. */ -+#if gcdSMP -+ gctPOINTER pending; -+#else -+ volatile gctUINT pending; -+#endif -+ -+ /* List of free event structures and its mutex. */ -+ gcsEVENT_PTR freeEventList; -+ gctSIZE_T freeEventCount; -+ gctPOINTER freeEventMutex; -+ -+ /* Event queues. */ -+ gcsEVENT_QUEUE_PTR queueHead; -+ gcsEVENT_QUEUE_PTR queueTail; -+ gcsEVENT_QUEUE_PTR freeList; -+ gcsEVENT_QUEUE repoList[gcdREPO_LIST_COUNT]; -+ gctPOINTER eventListMutex; -+ -+ gctPOINTER submitTimer; -+ -+#if gcdINTERRUPT_STATISTIC -+ gctPOINTER interruptCount; -+#endif -+ -+#if gcdRECORD_COMMAND -+ gckRECORDER recorder; -+#endif -+}; -+ -+/* Free all events belonging to a process. */ -+gceSTATUS -+gckEVENT_FreeProcess( -+ IN gckEVENT Event, -+ IN gctUINT32 ProcessID -+ ); -+ -+gceSTATUS -+gckEVENT_Stop( -+ IN gckEVENT Event, -+ IN gctUINT32 ProcessID, -+ IN gctPHYS_ADDR Handle, -+ IN gctPOINTER Logical, -+ IN gctSIGNAL Signal, -+ IN OUT gctUINT32 * waitSize -+ ); -+ -+typedef struct _gcsLOCK_INFO * gcsLOCK_INFO_PTR; -+typedef struct _gcsLOCK_INFO -+{ -+ gctUINT32 GPUAddresses[gcdMAX_GPU_COUNT]; -+ gctPOINTER pageTables[gcdMAX_GPU_COUNT]; -+ gctUINT32 lockeds[gcdMAX_GPU_COUNT]; -+ gckKERNEL lockKernels[gcdMAX_GPU_COUNT]; -+ gckMMU lockMmus[gcdMAX_GPU_COUNT]; -+} -+gcsLOCK_INFO; -+ -+typedef struct _gcsGPU_MAP * gcsGPU_MAP_PTR; -+typedef struct _gcsGPU_MAP -+{ -+ gctINT pid; -+ gcsLOCK_INFO lockInfo; -+ gcsGPU_MAP_PTR prev; -+ gcsGPU_MAP_PTR next; -+} -+gcsGPU_MAP; -+ -+/* gcuVIDMEM_NODE structure. */ -+typedef union _gcuVIDMEM_NODE -+{ -+ /* Allocated from gckVIDMEM. */ -+ struct _gcsVIDMEM_NODE_VIDMEM -+ { -+ /* Owner of this node. */ -+ gckVIDMEM memory; -+ -+ /* Dual-linked list of nodes. */ -+ gcuVIDMEM_NODE_PTR next; -+ gcuVIDMEM_NODE_PTR prev; -+ -+ /* Dual linked list of free nodes. */ -+ gcuVIDMEM_NODE_PTR nextFree; -+ gcuVIDMEM_NODE_PTR prevFree; -+ -+ /* Information for this node. */ -+ gctSIZE_T offset; -+ gctSIZE_T bytes; -+ gctUINT32 alignment; -+ -+ /* Locked counter. */ -+ gctINT32 locked; -+ -+ /* Memory pool. */ -+ gcePOOL pool; -+ gctUINT32 physical; -+ -+ /* Process ID owning this memory. */ -+ gctUINT32 processID; -+ -+#if gcdENABLE_VG -+ gctPOINTER kernelVirtual; -+#endif -+ } -+ VidMem; -+ -+ /* Allocated from gckOS. */ -+ struct _gcsVIDMEM_NODE_VIRTUAL -+ { -+ /* Pointer to gckKERNEL object. */ -+ gckKERNEL kernel; -+ -+ /* Information for this node. */ -+ /* Contiguously allocated? */ -+ gctBOOL contiguous; -+ /* mdl record pointer... a kmalloc address. Process agnostic. */ -+ gctPHYS_ADDR physical; -+ gctSIZE_T bytes; -+ /* do_mmap_pgoff address... mapped per-process. */ -+ gctPOINTER logical; -+ -+#if gcdENABLE_VG -+ /* Physical address of this node, only meaningful when it is contiguous. */ -+ gctUINT32 physicalAddress; -+ -+ /* Kernel logical of this node. */ -+ gctPOINTER kernelVirtual; -+#endif -+ -+ /* Customer private handle */ -+ gctUINT32 gid; -+ -+ /* Page table information. */ -+ /* Used only when node is not contiguous */ -+ gctSIZE_T pageCount; -+ -+ /* Used only when node is not contiguous */ -+ gctPOINTER pageTables[gcdMAX_GPU_COUNT]; -+ /* Pointer to gckKERNEL object who lock this. */ -+ gckKERNEL lockKernels[gcdMAX_GPU_COUNT]; -+ /* Actual physical address */ -+ gctUINT32 addresses[gcdMAX_GPU_COUNT]; -+ -+ /* Locked counter. */ -+ gctINT32 lockeds[gcdMAX_GPU_COUNT]; -+ -+ /* Process ID owning this memory. */ -+ gctUINT32 processID; -+ -+ /* Surface type. */ -+ gceSURF_TYPE type; -+ } -+ Virtual; -+} -+gcuVIDMEM_NODE; -+ -+/* gckVIDMEM object. */ -+struct _gckVIDMEM -+{ -+ /* Object. */ -+ gcsOBJECT object; -+ -+ /* Pointer to gckOS object. */ -+ gckOS os; -+ -+ /* Information for this video memory heap. */ -+ gctUINT32 baseAddress; -+ gctSIZE_T bytes; -+ gctSIZE_T freeBytes; -+ -+ /* Mapping for each type of surface. */ -+ gctINT mapping[gcvSURF_NUM_TYPES]; -+ -+ /* Sentinel nodes for up to 8 banks. */ -+ gcuVIDMEM_NODE sentinel[8]; -+ -+ /* Allocation threshold. */ -+ gctSIZE_T threshold; -+ -+ /* The heap mutex. */ -+ gctPOINTER mutex; -+}; -+ -+typedef struct _gcsVIDMEM_NODE -+{ -+ /* Pointer to gcuVIDMEM_NODE. */ -+ gcuVIDMEM_NODE_PTR node; -+ -+ /* Mutex to protect node. */ -+ gctPOINTER mutex; -+ -+ /* Reference count. */ -+ gctPOINTER reference; -+ -+ /* Name for client to import. */ -+ gctUINT32 name; -+ -+#if gcdPROCESS_ADDRESS_SPACE -+ /* Head of mapping list. */ -+ gcsGPU_MAP_PTR mapHead; -+ -+ /* Tail of mapping list. */ -+ gcsGPU_MAP_PTR mapTail; -+ -+ gctPOINTER mapMutex; -+#endif -+ -+ /* Surface Type. */ -+ gceSURF_TYPE type; -+ -+ /* Pool from which node is allocated. */ -+ gcePOOL pool; -+} -+gcsVIDMEM_NODE; -+ -+typedef struct _gcsVIDMEM_HANDLE * gckVIDMEM_HANDLE; -+typedef struct _gcsVIDMEM_HANDLE -+{ -+ /* Pointer to gckVIDMEM_NODE. */ -+ gckVIDMEM_NODE node; -+ -+ /* Handle for current process. */ -+ gctUINT32 handle; -+ -+ /* Reference count for this handle. */ -+ gctPOINTER reference; -+} -+gcsVIDMEM_HANDLE; -+ -+typedef struct _gcsSHBUF * gcsSHBUF_PTR; -+typedef struct _gcsSHBUF -+{ -+ /* ID. */ -+ gctUINT32 id; -+ -+ /* Reference count. */ -+ gctPOINTER reference; -+ -+ /* Data size. */ -+ gctUINT32 size; -+ -+ /* Data. */ -+ gctPOINTER data; -+} -+gcsSHBUF; -+ -+gceSTATUS -+gckVIDMEM_HANDLE_Reference( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 ProcessID, -+ IN gctUINT32 Handle -+ ); -+ -+gceSTATUS -+gckVIDMEM_HANDLE_Dereference( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 ProcessID, -+ IN gctUINT32 Handle -+ ); -+ -+gceSTATUS -+gckVIDMEM_NODE_Allocate( -+ IN gckKERNEL Kernel, -+ IN gcuVIDMEM_NODE_PTR VideoNode, -+ IN gceSURF_TYPE Type, -+ IN gcePOOL Pool, -+ IN gctUINT32 * Handle -+ ); -+ -+gceSTATUS -+gckVIDMEM_Node_Lock( -+ IN gckKERNEL Kernel, -+ IN gckVIDMEM_NODE Node, -+ OUT gctUINT32 *Address -+ ); -+ -+gceSTATUS -+gckVIDMEM_NODE_Unlock( -+ IN gckKERNEL Kernel, -+ IN gckVIDMEM_NODE Node, -+ IN gctUINT32 ProcessID -+ ); -+ -+gceSTATUS -+gckVIDMEM_NODE_Dereference( -+ IN gckKERNEL Kernel, -+ IN gckVIDMEM_NODE Node -+ ); -+ -+gceSTATUS -+gckVIDMEM_NODE_Name( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 Handle, -+ IN gctUINT32 * Name -+ ); -+ -+gceSTATUS -+gckVIDMEM_NODE_Import( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 Name, -+ IN gctUINT32 * Handle -+ ); -+ -+gceSTATUS -+gckVIDMEM_HANDLE_LookupAndReference( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 Handle, -+ OUT gckVIDMEM_NODE * Node -+ ); -+ -+gceSTATUS -+gckVIDMEM_HANDLE_Lookup( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 ProcessID, -+ IN gctUINT32 Handle, -+ OUT gckVIDMEM_NODE * Node -+ ); -+ -+gceSTATUS -+gckVIDMEM_NODE_GetFd( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 Handle, -+ OUT gctINT * Fd -+ ); -+ -+#if gcdPROCESS_ADDRESS_SPACE -+gceSTATUS -+gckEVENT_DestroyMmu( -+ IN gckEVENT Event, -+ IN gckMMU Mmu, -+ IN gceKERNEL_WHERE FromWhere -+ ); -+#endif -+ -+/* gckMMU object. */ -+struct _gckMMU -+{ -+ /* The object. */ -+ gcsOBJECT object; -+ -+ /* Pointer to gckOS object. */ -+ gckOS os; -+ -+ /* Pointer to gckHARDWARE object. */ -+ gckHARDWARE hardware; -+ -+ /* The page table mutex. */ -+ gctPOINTER pageTableMutex; -+ -+ /* Page table information. */ -+ gctSIZE_T pageTableSize; -+ gctPHYS_ADDR pageTablePhysical; -+ gctUINT32_PTR pageTableLogical; -+ gctUINT32 pageTableEntries; -+ -+ /* Master TLB information. */ -+ gctSIZE_T mtlbSize; -+ gctPHYS_ADDR mtlbPhysical; -+ gctUINT32_PTR mtlbLogical; -+ gctUINT32 mtlbEntries; -+ -+ /* Free entries. */ -+ gctUINT32 heapList; -+ gctBOOL freeNodes; -+ -+ gctPOINTER staticSTLB; -+ gctBOOL enabled; -+ -+ gctUINT32 dynamicMappingStart; -+ -+ gctUINT32_PTR mapLogical; -+#if gcdPROCESS_ADDRESS_SPACE -+ gctPOINTER pageTableDirty[gcdMAX_GPU_COUNT]; -+ gctPOINTER stlbs; -+#endif -+}; -+ -+gceSTATUS -+gckOS_CreateKernelVirtualMapping( -+ IN gckOS Os, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T Bytes, -+ OUT gctPOINTER * Logical, -+ OUT gctSIZE_T * PageCount -+ ); -+ -+gceSTATUS -+gckOS_DestroyKernelVirtualMapping( -+ IN gckOS Os, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T Bytes, -+ IN gctPOINTER Logical -+ ); -+ -+gceSTATUS -+gckOS_CreateUserVirtualMapping( -+ IN gckOS Os, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T Bytes, -+ OUT gctPOINTER * Logical, -+ OUT gctSIZE_T * PageCount -+ ); -+ -+gceSTATUS -+gckOS_DestroyUserVirtualMapping( -+ IN gckOS Os, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T Bytes, -+ IN gctPOINTER Logical -+ ); -+ -+gceSTATUS -+gckOS_GetFd( -+ IN gctSTRING Name, -+ IN gcsFDPRIVATE_PTR Private, -+ OUT gctINT *Fd -+ ); -+ -+gceSTATUS -+gckKERNEL_AllocateVirtualCommandBuffer( -+ IN gckKERNEL Kernel, -+ IN gctBOOL InUserSpace, -+ IN OUT gctSIZE_T * Bytes, -+ OUT gctPHYS_ADDR * Physical, -+ OUT gctPOINTER * Logical -+ ); -+ -+gceSTATUS -+gckKERNEL_DestroyVirtualCommandBuffer( -+ IN gckKERNEL Kernel, -+ IN gctSIZE_T Bytes, -+ IN gctPHYS_ADDR Physical, -+ IN gctPOINTER Logical -+ ); -+ -+gceSTATUS -+gckKERNEL_GetGPUAddress( -+ IN gckKERNEL Kernel, -+ IN gctPOINTER Logical, -+ IN gctBOOL InUserSpace, -+ OUT gctUINT32 * Address -+ ); -+ -+gceSTATUS -+gckKERNEL_QueryGPUAddress( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 GpuAddress, -+ OUT gckVIRTUAL_COMMAND_BUFFER_PTR * Buffer -+ ); -+ -+gceSTATUS -+gckKERNEL_AttachProcess( -+ IN gckKERNEL Kernel, -+ IN gctBOOL Attach -+ ); -+ -+gceSTATUS -+gckKERNEL_AttachProcessEx( -+ IN gckKERNEL Kernel, -+ IN gctBOOL Attach, -+ IN gctUINT32 PID -+ ); -+ -+gceSTATUS -+gckHARDWARE_QueryIdle( -+ IN gckHARDWARE Hardware, -+ OUT gctBOOL_PTR IsIdle -+ ); -+ -+gceSTATUS -+gckKERNEL_CreateShBuffer( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 Size, -+ OUT gctSHBUF * ShBuf -+ ); -+ -+gceSTATUS -+gckKERNEL_DestroyShBuffer( -+ IN gckKERNEL Kernel, -+ IN gctSHBUF ShBuf -+ ); -+ -+gceSTATUS -+gckKERNEL_MapShBuffer( -+ IN gckKERNEL Kernel, -+ IN gctSHBUF ShBuf -+ ); -+ -+gceSTATUS -+gckKERNEL_WriteShBuffer( -+ IN gckKERNEL Kernel, -+ IN gctSHBUF ShBuf, -+ IN gctPOINTER UserData, -+ IN gctUINT32 ByteCount -+ ); -+ -+gceSTATUS -+gckKERNEL_ReadShBuffer( -+ IN gckKERNEL Kernel, -+ IN gctSHBUF ShBuf, -+ IN gctPOINTER UserData, -+ IN gctUINT32 ByteCount, -+ OUT gctUINT32 * BytesRead -+ ); -+ -+ -+/******************************************************************************\ -+******************************* gckCONTEXT Object ******************************* -+\******************************************************************************/ -+ -+gceSTATUS -+gckCONTEXT_Construct( -+ IN gckOS Os, -+ IN gckHARDWARE Hardware, -+ IN gctUINT32 ProcessID, -+ OUT gckCONTEXT * Context -+ ); -+ -+gceSTATUS -+gckCONTEXT_Destroy( -+ IN gckCONTEXT Context -+ ); -+ -+gceSTATUS -+gckCONTEXT_Update( -+ IN gckCONTEXT Context, -+ IN gctUINT32 ProcessID, -+ IN gcsSTATE_DELTA_PTR StateDelta -+ ); -+ -+gceSTATUS -+gckCONTEXT_MapBuffer( -+ IN gckCONTEXT Context, -+ OUT gctUINT32 *Physicals, -+ OUT gctUINT64 *Logicals, -+ OUT gctUINT32 *Bytes -+ ); -+ -+#if gcdLINK_QUEUE_SIZE -+void -+gckLINKQUEUE_Enqueue( -+ IN gckLINKQUEUE LinkQueue, -+ IN gctUINT32 start, -+ IN gctUINT32 end -+ ); -+ -+void -+gckLINKQUEUE_GetData( -+ IN gckLINKQUEUE LinkQueue, -+ IN gctUINT32 Index, -+ OUT gckLINKDATA * Data -+ ); -+#endif -+ -+gceSTATUS -+gckENTRYQUEUE_Enqueue( -+ IN gckKERNEL Kernel, -+ IN gckENTRYQUEUE Queue, -+ IN gctUINT32 physical, -+ IN gctUINT32 bytes -+ ); -+ -+gceSTATUS -+gckENTRYQUEUE_Dequeue( -+ IN gckENTRYQUEUE Queue, -+ OUT gckENTRYDATA * Data -+ ); -+ -+/******************************************************************************\ -+****************************** gckRECORDER Object ****************************** -+\******************************************************************************/ -+gceSTATUS -+gckRECORDER_Construct( -+ IN gckOS Os, -+ IN gckHARDWARE Hardware, -+ OUT gckRECORDER * Recorder -+ ); -+ -+gceSTATUS -+gckRECORDER_Destory( -+ IN gckOS Os, -+ IN gckRECORDER Recorder -+ ); -+ -+void -+gckRECORDER_AdvanceIndex( -+ gckRECORDER Recorder, -+ gctUINT64 CommitStamp -+ ); -+ -+void -+gckRECORDER_Record( -+ gckRECORDER Recorder, -+ gctUINT8_PTR CommandBuffer, -+ gctUINT32 CommandBytes, -+ gctUINT8_PTR ContextBuffer, -+ gctUINT32 ContextBytes -+ ); -+ -+void -+gckRECORDER_Dump( -+ gckRECORDER Recorder -+ ); -+ -+gceSTATUS -+gckRECORDER_UpdateMirror( -+ gckRECORDER Recorder, -+ gctUINT32 State, -+ gctUINT32 Data -+ ); -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* __gc_hal_kernel_h_ */ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_interrupt_vg.c linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_interrupt_vg.c ---- linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_interrupt_vg.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_interrupt_vg.c 2015-11-30 17:56:13.576137991 +0100 -@@ -0,0 +1,858 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#include "gc_hal_kernel_precomp.h" -+ -+#if gcdENABLE_VG -+ -+/******************************************************************************\ -+*********************** Support Functions and Definitions ********************** -+\******************************************************************************/ -+ -+/* Interruot statistics will be accumulated if not zero. */ -+#define gcmENABLE_INTERRUPT_STATISTICS 0 -+ -+#define _GC_OBJ_ZONE gcvZONE_INTERRUPT -+ -+/* Object structure. */ -+struct _gckVGINTERRUPT -+{ -+ /* Object. */ -+ gcsOBJECT object; -+ -+ /* gckVGKERNEL pointer. */ -+ gckVGKERNEL kernel; -+ -+ /* gckOS pointer. */ -+ gckOS os; -+ -+ /* Interrupt handlers. */ -+ gctINTERRUPT_HANDLER handlers[32]; -+ -+ /* Main interrupt handler thread. */ -+ gctTHREAD handler; -+ gctBOOL terminate; -+ -+ /* Interrupt FIFO. */ -+ gctSEMAPHORE fifoValid; -+ gctUINT32 fifo[256]; -+ gctUINT fifoItems; -+ gctUINT8 head; -+ gctUINT8 tail; -+ -+ /* Interrupt statistics. */ -+#if gcmENABLE_INTERRUPT_STATISTICS -+ gctUINT maxFifoItems; -+ gctUINT fifoOverflow; -+ gctUINT maxSimultaneous; -+ gctUINT multipleCount; -+#endif -+}; -+ -+ -+/******************************************************************************* -+** -+** _ProcessInterrupt -+** -+** The interrupt processor. -+** -+** INPUT: -+** -+** ThreadParameter -+** Pointer to the gckVGINTERRUPT object. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+ -+#if gcmENABLE_INTERRUPT_STATISTICS -+static void -+_ProcessInterrupt( -+ gckVGINTERRUPT Interrupt, -+ gctUINT_PTR TriggeredCount -+ ) -+#else -+static void -+_ProcessInterrupt( -+ gckVGINTERRUPT Interrupt -+ ) -+#endif -+{ -+ gceSTATUS status; -+ gctUINT32 triggered; -+ gctUINT i; -+ -+ /* Advance to the next entry. */ -+ Interrupt->tail += 1; -+ Interrupt->fifoItems -= 1; -+ -+ /* Get the interrupt value. */ -+ triggered = Interrupt->fifo[Interrupt->tail]; -+ gcmkASSERT(triggered != 0); -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_VERBOSE, gcvZONE_COMMAND, -+ "%s: triggered=0x%08X\n", -+ __FUNCTION__, -+ triggered -+ ); -+ -+ /* Walk through all possible interrupts. */ -+ for (i = 0; i < gcmSIZEOF(Interrupt->handlers); i += 1) -+ { -+ /* Test if interrupt happened. */ -+ if ((triggered & 1) == 1) -+ { -+#if gcmENABLE_INTERRUPT_STATISTICS -+ if (TriggeredCount != gcvNULL) -+ { -+ (* TriggeredCount) += 1; -+ } -+#endif -+ -+ /* Make sure we have valid handler. */ -+ if (Interrupt->handlers[i] == gcvNULL) -+ { -+ gcmkTRACE( -+ gcvLEVEL_ERROR, -+ "%s: Interrupt %d isn't registered.\n", -+ __FUNCTION__, i -+ ); -+ } -+ else -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_VERBOSE, gcvZONE_COMMAND, -+ "%s: interrupt=%d\n", -+ __FUNCTION__, -+ i -+ ); -+ -+ /* Call the handler. */ -+ status = Interrupt->handlers[i] (Interrupt->kernel); -+ -+ if (gcmkIS_ERROR(status)) -+ { -+ /* Failed to signal the semaphore. */ -+ gcmkTRACE( -+ gcvLEVEL_ERROR, -+ "%s: Error %d incrementing the semaphore #%d.\n", -+ __FUNCTION__, status, i -+ ); -+ } -+ } -+ } -+ -+ /* Next interrupt. */ -+ triggered >>= 1; -+ -+ /* No more interrupts to handle? */ -+ if (triggered == 0) -+ { -+ break; -+ } -+ } -+} -+ -+ -+/******************************************************************************* -+** -+** _MainInterruptHandler -+** -+** The main interrupt thread serves the interrupt FIFO and calls registered -+** handlers for the interrupts that occured. The handlers are called in the -+** sequence interrupts occured with the exception when multiple interrupts -+** occured at the same time. In that case the handler calls are "sorted" by -+** the interrupt number therefore giving the interrupts with lower numbers -+** higher priority. -+** -+** INPUT: -+** -+** ThreadParameter -+** Pointer to the gckVGINTERRUPT object. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+ -+static gctTHREADFUNCRESULT gctTHREADFUNCTYPE -+_MainInterruptHandler( -+ gctTHREADFUNCPARAMETER ThreadParameter -+ ) -+{ -+ gceSTATUS status; -+ gckVGINTERRUPT interrupt; -+ -+#if gcmENABLE_INTERRUPT_STATISTICS -+ gctUINT count; -+#endif -+ -+ /* Cast the object. */ -+ interrupt = (gckVGINTERRUPT) ThreadParameter; -+ -+ /* Enter the loop. */ -+ while (gcvTRUE) -+ { -+ /* Wait for an interrupt. */ -+ status = gckOS_DecrementSemaphore(interrupt->os, interrupt->fifoValid); -+ -+ /* Error? */ -+ if (gcmkIS_ERROR(status)) -+ { -+ break; -+ } -+ -+ /* System termination request? */ -+ if (status == gcvSTATUS_TERMINATE) -+ { -+ break; -+ } -+ -+ /* Driver is shutting down? */ -+ if (interrupt->terminate) -+ { -+ break; -+ } -+ -+#if gcmENABLE_INTERRUPT_STATISTICS -+ /* Reset triggered count. */ -+ count = 0; -+ -+ /* Process the interrupt. */ -+ _ProcessInterrupt(interrupt, &count); -+ -+ /* Update conters. */ -+ if (count > interrupt->maxSimultaneous) -+ { -+ interrupt->maxSimultaneous = count; -+ } -+ -+ if (count > 1) -+ { -+ interrupt->multipleCount += 1; -+ } -+#else -+ /* Process the interrupt. */ -+ _ProcessInterrupt(interrupt); -+#endif -+ } -+ -+ return 0; -+} -+ -+ -+/******************************************************************************* -+** -+** _StartInterruptHandler / _StopInterruptHandler -+** -+** Main interrupt handler routine control. -+** -+** INPUT: -+** -+** ThreadParameter -+** Pointer to the gckVGINTERRUPT object. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+ -+static gceSTATUS -+_StartInterruptHandler( -+ gckVGINTERRUPT Interrupt -+ ) -+{ -+ gceSTATUS status, last; -+ -+ do -+ { -+ /* Objects must not be already created. */ -+ gcmkASSERT(Interrupt->fifoValid == gcvNULL); -+ gcmkASSERT(Interrupt->handler == gcvNULL); -+ -+ /* Reset the termination request. */ -+ Interrupt->terminate = gcvFALSE; -+ -+#if !gcdENABLE_INFINITE_SPEED_HW -+ /* Construct the fifo semaphore. */ -+ gcmkERR_BREAK(gckOS_CreateSemaphoreVG( -+ Interrupt->os, &Interrupt->fifoValid -+ )); -+ -+ /* Start the interrupt handler thread. */ -+ gcmkERR_BREAK(gckOS_StartThread( -+ Interrupt->os, -+ _MainInterruptHandler, -+ Interrupt, -+ &Interrupt->handler -+ )); -+#endif -+ -+ /* Success. */ -+ return gcvSTATUS_OK; -+ } -+ while (gcvFALSE); -+ -+ /* Roll back. */ -+ if (Interrupt->fifoValid != gcvNULL) -+ { -+ gcmkCHECK_STATUS(gckOS_DestroySemaphore( -+ Interrupt->os, Interrupt->fifoValid -+ )); -+ -+ Interrupt->fifoValid = gcvNULL; -+ } -+ -+ /* Return the status. */ -+ return status; -+} -+ -+static gceSTATUS -+_StopInterruptHandler( -+ gckVGINTERRUPT Interrupt -+ ) -+{ -+ gceSTATUS status; -+ -+ do -+ { -+ /* Does the thread exist? */ -+ if (Interrupt->handler == gcvNULL) -+ { -+ /* The semaphore must be NULL as well. */ -+ gcmkASSERT(Interrupt->fifoValid == gcvNULL); -+ -+ /* Success. */ -+ status = gcvSTATUS_OK; -+ break; -+ } -+ -+ /* The semaphore must exist as well. */ -+ gcmkASSERT(Interrupt->fifoValid != gcvNULL); -+ -+ /* Set the termination request. */ -+ Interrupt->terminate = gcvTRUE; -+ -+ /* Unlock the thread. */ -+ gcmkERR_BREAK(gckOS_IncrementSemaphore( -+ Interrupt->os, Interrupt->fifoValid -+ )); -+ -+ /* Wait until the thread quits. */ -+ gcmkERR_BREAK(gckOS_StopThread( -+ Interrupt->os, -+ Interrupt->handler -+ )); -+ -+ /* Destroy the semaphore. */ -+ gcmkERR_BREAK(gckOS_DestroySemaphore( -+ Interrupt->os, Interrupt->fifoValid -+ )); -+ -+ /* Reset handles. */ -+ Interrupt->handler = gcvNULL; -+ Interrupt->fifoValid = gcvNULL; -+ } -+ while (gcvFALSE); -+ -+ /* Return the status. */ -+ return status; -+} -+ -+ -+/******************************************************************************\ -+***************************** Interrupt Object API ***************************** -+\******************************************************************************/ -+ -+/******************************************************************************* -+** -+** gckVGINTERRUPT_Construct -+** -+** Construct an interrupt object. -+** -+** INPUT: -+** -+** Kernel -+** Pointer to the gckVGKERNEL object. -+** -+** OUTPUT: -+** -+** Interrupt -+** Pointer to the new gckVGINTERRUPT object. -+*/ -+ -+gceSTATUS -+gckVGINTERRUPT_Construct( -+ IN gckVGKERNEL Kernel, -+ OUT gckVGINTERRUPT * Interrupt -+ ) -+{ -+ gceSTATUS status; -+ gckVGINTERRUPT interrupt = gcvNULL; -+ -+ gcmkHEADER_ARG("Kernel=0x%x Interrupt=0x%x", Kernel, Interrupt); -+ -+ /* Verify argeuments. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ gcmkVERIFY_ARGUMENT(Interrupt != gcvNULL); -+ -+ do -+ { -+ /* Allocate the gckVGINTERRUPT structure. */ -+ gcmkERR_BREAK(gckOS_Allocate( -+ Kernel->os, -+ gcmSIZEOF(struct _gckVGINTERRUPT), -+ (gctPOINTER *) &interrupt -+ )); -+ -+ /* Reset the object data. */ -+ gcmkVERIFY_OK(gckOS_ZeroMemory( -+ interrupt, gcmSIZEOF(struct _gckVGINTERRUPT) -+ )); -+ -+ /* Initialize the object. */ -+ interrupt->object.type = gcvOBJ_INTERRUPT; -+ -+ /* Initialize the object pointers. */ -+ interrupt->kernel = Kernel; -+ interrupt->os = Kernel->os; -+ -+ /* Initialize the current FIFO position. */ -+ interrupt->head = (gctUINT8)~0; -+ interrupt->tail = (gctUINT8)~0; -+ -+ /* Start the thread. */ -+ gcmkERR_BREAK(_StartInterruptHandler(interrupt)); -+ -+ /* Return interrupt object. */ -+ *Interrupt = interrupt; -+ -+ gcmkFOOTER_ARG("*Interrup=0x%x", *Interrupt); -+ /* Success. */ -+ return gcvSTATUS_OK; -+ } -+ while (gcvFALSE); -+ -+ /* Roll back. */ -+ if (interrupt != gcvNULL) -+ { -+ /* Free the gckVGINTERRUPT structure. */ -+ gcmkVERIFY_OK(gckOS_Free(interrupt->os, interrupt)); -+ } -+ -+ gcmkFOOTER(); -+ -+ /* Return the status. */ -+ return status; -+} -+ -+ -+/******************************************************************************* -+** -+** gckVGINTERRUPT_Destroy -+** -+** Destroy an interrupt object. -+** -+** INPUT: -+** -+** Interrupt -+** Pointer to the gckVGINTERRUPT object to destroy. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+ -+gceSTATUS -+gckVGINTERRUPT_Destroy( -+ IN gckVGINTERRUPT Interrupt -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Interrupt=0x%x", Interrupt); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Interrupt, gcvOBJ_INTERRUPT); -+ -+ do -+ { -+ /* Stop the interrupt thread. */ -+ gcmkERR_BREAK(_StopInterruptHandler(Interrupt)); -+ -+ /* Mark the object as unknown. */ -+ Interrupt->object.type = gcvOBJ_UNKNOWN; -+ -+ /* Free the gckVGINTERRUPT structure. */ -+ gcmkERR_BREAK(gckOS_Free(Interrupt->os, Interrupt)); -+ } -+ while (gcvFALSE); -+ -+ gcmkFOOTER(); -+ -+ /* Return the status. */ -+ return status; -+} -+ -+ -+/******************************************************************************* -+** -+** gckVGINTERRUPT_DumpState -+** -+** Print the current state of the interrupt manager. -+** -+** INPUT: -+** -+** Interrupt -+** Pointer to a gckVGINTERRUPT object. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+ -+#if gcvDEBUG -+gceSTATUS -+gckVGINTERRUPT_DumpState( -+ IN gckVGINTERRUPT Interrupt -+ ) -+{ -+ gcmkHEADER_ARG("Interrupt=0x%x", Interrupt); -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Interrupt, gcvOBJ_INTERRUPT); -+ -+ /* Print the header. */ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_VERBOSE, gcvZONE_COMMAND, -+ "%s: INTERRUPT OBJECT STATUS\n", -+ __FUNCTION__ -+ ); -+ -+ /* Print statistics. */ -+#if gcmENABLE_INTERRUPT_STATISTICS -+ gcmkTRACE_ZONE( -+ gcvLEVEL_VERBOSE, gcvZONE_COMMAND, -+ " Maximum number of FIFO items accumulated at a single time: %d\n", -+ Interrupt->maxFifoItems -+ ); -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_VERBOSE, gcvZONE_COMMAND, -+ " Interrupt FIFO overflow happened times: %d\n", -+ Interrupt->fifoOverflow -+ ); -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_VERBOSE, gcvZONE_COMMAND, -+ " Maximum number of interrupts simultaneously generated: %d\n", -+ Interrupt->maxSimultaneous -+ ); -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_VERBOSE, gcvZONE_COMMAND, -+ " Number of times when there were multiple interrupts generated: %d\n", -+ Interrupt->multipleCount -+ ); -+#endif -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_VERBOSE, gcvZONE_COMMAND, -+ " The current number of entries in the FIFO: %d\n", -+ Interrupt->fifoItems -+ ); -+ -+ /* Print the FIFO contents. */ -+ if (Interrupt->fifoItems != 0) -+ { -+ gctUINT8 index; -+ gctUINT8 last; -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_VERBOSE, gcvZONE_COMMAND, -+ " FIFO current contents:\n" -+ ); -+ -+ /* Get the current pointers. */ -+ index = Interrupt->tail; -+ last = Interrupt->head; -+ -+ while (index != last) -+ { -+ /* Advance to the next entry. */ -+ index += 1; -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_VERBOSE, gcvZONE_COMMAND, -+ " %d: 0x%08X\n", -+ index, Interrupt->fifo[index] -+ ); -+ } -+ } -+ -+ gcmkFOOTER_NO(); -+ /* Success. */ -+ return gcvSTATUS_OK; -+} -+#endif -+ -+ -+/******************************************************************************* -+** -+** gckVGINTERRUPT_Enable -+** -+** Enable the specified interrupt. -+** -+** INPUT: -+** -+** Interrupt -+** Pointer to a gckVGINTERRUPT object. -+** -+** Id -+** Pointer to the variable that holds the interrupt number to be -+** registered in range 0..31. -+** If the value is less then 0, gckVGINTERRUPT_Enable will attempt -+** to find an unused interrupt. If such interrupt is found, the number -+** will be assigned to the variable if the functuion call succeedes. -+** -+** Handler -+** Pointer to the handler to register for the interrupt. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+ -+gceSTATUS -+gckVGINTERRUPT_Enable( -+ IN gckVGINTERRUPT Interrupt, -+ IN OUT gctINT32_PTR Id, -+ IN gctINTERRUPT_HANDLER Handler -+ ) -+{ -+ gceSTATUS status; -+ gctINT32 i; -+ -+ gcmkHEADER_ARG("Interrupt=0x%x Id=0x%x Handler=0x%x", Interrupt, Id, Handler); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Interrupt, gcvOBJ_INTERRUPT); -+ gcmkVERIFY_ARGUMENT(Id != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Handler != gcvNULL); -+ -+ do -+ { -+ /* See if we need to allocate an ID. */ -+ if (*Id < 0) -+ { -+ /* Find the first unused interrupt handler. */ -+ for (i = 0; i < gcmCOUNTOF(Interrupt->handlers); ++i) -+ { -+ if (Interrupt->handlers[i] == gcvNULL) -+ { -+ break; -+ } -+ } -+ -+ /* No unused innterrupts? */ -+ if (i == gcmCOUNTOF(Interrupt->handlers)) -+ { -+ status = gcvSTATUS_OUT_OF_RESOURCES; -+ break; -+ } -+ -+ /* Update the interrupt ID. */ -+ *Id = i; -+ } -+ -+ /* Make sure the ID is in range. */ -+ else if (*Id >= gcmCOUNTOF(Interrupt->handlers)) -+ { -+ status = gcvSTATUS_INVALID_ARGUMENT; -+ break; -+ } -+ -+ /* Set interrupt handler. */ -+ Interrupt->handlers[*Id] = Handler; -+ -+ /* Success. */ -+ status = gcvSTATUS_OK; -+ } -+ while (gcvFALSE); -+ -+ gcmkFOOTER(); -+ /* Return the status. */ -+ return status; -+} -+ -+ -+/******************************************************************************* -+** -+** gckVGINTERRUPT_Disable -+** -+** Disable the specified interrupt. -+** -+** INPUT: -+** -+** Interrupt -+** Pointer to a gckVGINTERRUPT object. -+** -+** Id -+** Interrupt number to be disabled in range 0..31. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+ -+gceSTATUS -+gckVGINTERRUPT_Disable( -+ IN gckVGINTERRUPT Interrupt, -+ IN gctINT32 Id -+ ) -+{ -+ gcmkHEADER_ARG("Interrupt=0x%x Id=0x%x", Interrupt, Id); -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Interrupt, gcvOBJ_INTERRUPT); -+ gcmkVERIFY_ARGUMENT((Id >= 0) && (Id < gcmCOUNTOF(Interrupt->handlers))); -+ -+ /* Reset interrupt handler. */ -+ Interrupt->handlers[Id] = gcvNULL; -+ -+ gcmkFOOTER_NO(); -+ /* Success. */ -+ return gcvSTATUS_OK; -+} -+ -+ -+/******************************************************************************* -+** -+** gckVGINTERRUPT_Enque -+** -+** Read the interrupt status register and put the value in the interrupt FIFO. -+** -+** INPUT: -+** -+** Interrupt -+** Pointer to a gckVGINTERRUPT object. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+ -+gceSTATUS -+gckVGINTERRUPT_Enque( -+ IN gckVGINTERRUPT Interrupt -+ ) -+{ -+ gceSTATUS status; -+ gctUINT32 triggered; -+ -+ gcmkHEADER_ARG("Interrupt=0x%x", Interrupt); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Interrupt, gcvOBJ_INTERRUPT); -+ -+ do -+ { -+ /* Read interrupt status register. */ -+ gcmkERR_BREAK(gckVGHARDWARE_ReadInterrupt( -+ Interrupt->kernel->hardware, &triggered -+ )); -+ -+ /* Mask out TS overflow interrupt */ -+ triggered &= 0xfffffffe; -+ -+ /* No interrupts to process? */ -+ if (triggered == 0) -+ { -+ status = gcvSTATUS_NOT_OUR_INTERRUPT; -+ break; -+ } -+ -+ /* FIFO overflow? */ -+ if (Interrupt->fifoItems == gcmCOUNTOF(Interrupt->fifo)) -+ { -+#if gcmENABLE_INTERRUPT_STATISTICS -+ Interrupt->fifoOverflow += 1; -+#endif -+ -+ /* OR the interrupt with the last value in the FIFO. */ -+ Interrupt->fifo[Interrupt->head] |= triggered; -+ -+ /* Success (kind of). */ -+ status = gcvSTATUS_OK; -+ } -+ else -+ { -+ /* Advance to the next entry. */ -+ Interrupt->head += 1; -+ Interrupt->fifoItems += 1; -+ -+#if gcmENABLE_INTERRUPT_STATISTICS -+ if (Interrupt->fifoItems > Interrupt->maxFifoItems) -+ { -+ Interrupt->maxFifoItems = Interrupt->fifoItems; -+ } -+#endif -+ -+ /* Set the new value. */ -+ Interrupt->fifo[Interrupt->head] = triggered; -+ -+ /* Increment the FIFO semaphore. */ -+ gcmkERR_BREAK(gckOS_IncrementSemaphore( -+ Interrupt->os, Interrupt->fifoValid -+ )); -+ -+ /* Windows kills our threads prematurely when the application -+ exists. Verify here that the thread is still alive. */ -+ status = gckOS_VerifyThread(Interrupt->os, Interrupt->handler); -+ -+ /* Has the thread been prematurely terminated? */ -+ if (status != gcvSTATUS_OK) -+ { -+ /* Process all accumulated interrupts. */ -+ while (Interrupt->head != Interrupt->tail) -+ { -+#if gcmENABLE_INTERRUPT_STATISTICS -+ /* Process the interrupt. */ -+ _ProcessInterrupt(Interrupt, gcvNULL); -+#else -+ /* Process the interrupt. */ -+ _ProcessInterrupt(Interrupt); -+#endif -+ } -+ -+ /* Set success. */ -+ status = gcvSTATUS_OK; -+ } -+ } -+ } -+ while (gcvFALSE); -+ -+ gcmkFOOTER(); -+ /* Return status. */ -+ return status; -+} -+ -+#endif /* gcdENABLE_VG */ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_iommu.c linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_iommu.c ---- linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_iommu.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_iommu.c 2015-11-30 17:56:13.576137991 +0100 -@@ -0,0 +1,202 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#include "gc_hal_kernel_linux.h" -+#include "gc_hal_kernel_device.h" -+ -+#include -+#include -+ -+#define _GC_OBJ_ZONE gcvZONE_OS -+ -+typedef struct _gcsIOMMU -+{ -+ struct iommu_domain * domain; -+ struct device * device; -+} -+gcsIOMMU; -+ -+static int -+_IOMMU_Fault_Handler( -+ struct iommu_domain * Domain, -+ struct device * Dev, -+ unsigned long DomainAddress, -+ int flags, -+ void * args -+ ) -+{ -+ return 0; -+} -+ -+static int -+_FlatMapping( -+ IN gckIOMMU Iommu -+ ) -+{ -+ gceSTATUS status; -+ gctUINT32 physical; -+ -+ for (physical = 0; physical < 0x80000000; physical += PAGE_SIZE) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, gcvZONE_OS, -+ "Map %x => %x bytes = %d", -+ physical, physical, PAGE_SIZE -+ ); -+ -+ gcmkONERROR(gckIOMMU_Map(Iommu, physical, physical, PAGE_SIZE)); -+ } -+ -+ return gcvSTATUS_OK; -+ -+OnError: -+ return status; -+} -+ -+void -+gckIOMMU_Destory( -+ IN gckOS Os, -+ IN gckIOMMU Iommu -+ ) -+{ -+ gcmkHEADER(); -+ -+ if (Iommu->domain && Iommu->device) -+ { -+ iommu_attach_device(Iommu->domain, Iommu->device); -+ } -+ -+ if (Iommu->domain) -+ { -+ iommu_domain_free(Iommu->domain); -+ } -+ -+ if (Iommu) -+ { -+ gcmkOS_SAFE_FREE(Os, Iommu); -+ } -+ -+ gcmkFOOTER_NO(); -+} -+ -+gceSTATUS -+gckIOMMU_Construct( -+ IN gckOS Os, -+ OUT gckIOMMU * Iommu -+ ) -+{ -+ gceSTATUS status; -+ gckIOMMU iommu = gcvNULL; -+ struct device *dev; -+ int ret; -+ -+ gcmkHEADER(); -+ -+ dev = &Os->device->platform->device->dev; -+ -+ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(gcsIOMMU), (gctPOINTER *)&iommu)); -+ -+ gckOS_ZeroMemory(iommu, gcmSIZEOF(gcsIOMMU)); -+ -+ iommu->domain = iommu_domain_alloc(&platform_bus_type); -+ -+ if (!iommu->domain) -+ { -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_OS, "iommu_domain_alloc() fail"); -+ -+ gcmkONERROR(gcvSTATUS_NOT_SUPPORTED); -+ } -+ -+ iommu_set_fault_handler(iommu->domain, _IOMMU_Fault_Handler, dev); -+ -+ ret = iommu_attach_device(iommu->domain, dev); -+ -+ if (ret) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, gcvZONE_OS, "iommu_attach_device() fail %d", ret); -+ -+ gcmkONERROR(gcvSTATUS_NOT_SUPPORTED); -+ } -+ -+ iommu->device = dev; -+ -+ _FlatMapping(iommu); -+ -+ *Iommu = iommu; -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ -+ gckIOMMU_Destory(Os, iommu); -+ -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckIOMMU_Map( -+ IN gckIOMMU Iommu, -+ IN gctUINT32 DomainAddress, -+ IN gctUINT32 Physical, -+ IN gctUINT32 Bytes -+ ) -+{ -+ gceSTATUS status; -+ int ret; -+ -+ gcmkHEADER_ARG("DomainAddress=%#X, Physical=%#X, Bytes=%d", -+ DomainAddress, Physical, Bytes); -+ -+ ret = iommu_map(Iommu->domain, DomainAddress, Physical, Bytes, 0); -+ -+ if (ret) -+ { -+ gcmkONERROR(gcvSTATUS_NOT_SUPPORTED); -+ } -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ -+ gcmkFOOTER(); -+ return status; -+ -+} -+ -+gceSTATUS -+gckIOMMU_Unmap( -+ IN gckIOMMU Iommu, -+ IN gctUINT32 DomainAddress, -+ IN gctUINT32 Bytes -+ ) -+{ -+ gcmkHEADER(); -+ -+ iommu_unmap(Iommu->domain, DomainAddress, Bytes); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_linux.c linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_linux.c ---- linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_linux.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_linux.c 2015-11-30 17:56:13.576137991 +0100 -@@ -0,0 +1,487 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#include "gc_hal_kernel_linux.h" -+ -+#define _GC_OBJ_ZONE gcvZONE_KERNEL -+ -+/******************************************************************************\ -+******************************* gckKERNEL API Code ****************************** -+\******************************************************************************/ -+ -+/******************************************************************************* -+** -+** gckKERNEL_QueryVideoMemory -+** -+** Query the amount of video memory. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** OUTPUT: -+** -+** gcsHAL_INTERFACE * Interface -+** Pointer to an gcsHAL_INTERFACE structure that will be filled in with -+** the memory information. -+*/ -+gceSTATUS -+gckKERNEL_QueryVideoMemory( -+ IN gckKERNEL Kernel, -+ OUT gcsHAL_INTERFACE * Interface -+ ) -+{ -+ gckGALDEVICE device; -+ -+ gcmkHEADER_ARG("Kernel=%p", Kernel); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ gcmkVERIFY_ARGUMENT(Interface != NULL); -+ -+ /* Extract the pointer to the gckGALDEVICE class. */ -+ device = (gckGALDEVICE) Kernel->context; -+ -+ /* Get internal memory size and physical address. */ -+ Interface->u.QueryVideoMemory.internalSize = device->internalSize; -+ Interface->u.QueryVideoMemory.internalPhysical = device->internalPhysicalName; -+ -+ /* Get external memory size and physical address. */ -+ Interface->u.QueryVideoMemory.externalSize = device->externalSize; -+ Interface->u.QueryVideoMemory.externalPhysical = device->externalPhysicalName; -+ -+ /* Get contiguous memory size and physical address. */ -+ Interface->u.QueryVideoMemory.contiguousSize = device->contiguousSize; -+ Interface->u.QueryVideoMemory.contiguousPhysical = device->contiguousPhysicalName; -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckKERNEL_GetVideoMemoryPool -+** -+** Get the gckVIDMEM object belonging to the specified pool. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** gcePOOL Pool -+** Pool to query gckVIDMEM object for. -+** -+** OUTPUT: -+** -+** gckVIDMEM * VideoMemory -+** Pointer to a variable that will hold the pointer to the gckVIDMEM -+** object belonging to the requested pool. -+*/ -+gceSTATUS -+gckKERNEL_GetVideoMemoryPool( -+ IN gckKERNEL Kernel, -+ IN gcePOOL Pool, -+ OUT gckVIDMEM * VideoMemory -+ ) -+{ -+ gckGALDEVICE device; -+ gckVIDMEM videoMemory; -+ -+ gcmkHEADER_ARG("Kernel=%p Pool=%d", Kernel, Pool); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ gcmkVERIFY_ARGUMENT(VideoMemory != NULL); -+ -+ /* Extract the pointer to the gckGALDEVICE class. */ -+ device = (gckGALDEVICE) Kernel->context; -+ -+ /* Dispatch on pool. */ -+ switch (Pool) -+ { -+ case gcvPOOL_LOCAL_INTERNAL: -+ /* Internal memory. */ -+ videoMemory = device->internalVidMem; -+ break; -+ -+ case gcvPOOL_LOCAL_EXTERNAL: -+ /* External memory. */ -+ videoMemory = device->externalVidMem; -+ break; -+ -+ case gcvPOOL_SYSTEM: -+ /* System memory. */ -+ videoMemory = device->contiguousVidMem; -+ break; -+ -+ default: -+ /* Unknown pool. */ -+ videoMemory = NULL; -+ } -+ -+ /* Return pointer to the gckVIDMEM object. */ -+ *VideoMemory = videoMemory; -+ -+ /* Return status. */ -+ gcmkFOOTER_ARG("*VideoMemory=%p", *VideoMemory); -+ return (videoMemory == NULL) ? gcvSTATUS_OUT_OF_MEMORY : gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckKERNEL_MapMemory -+** -+** Map video memory into the current process space. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** gctPHYS_ADDR Physical -+** Physical address of video memory to map. -+** -+** gctSIZE_T Bytes -+** Number of bytes to map. -+** -+** OUTPUT: -+** -+** gctPOINTER * Logical -+** Pointer to a variable that will hold the base address of the mapped -+** memory region. -+*/ -+gceSTATUS -+gckKERNEL_MapMemory( -+ IN gckKERNEL Kernel, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T Bytes, -+ OUT gctPOINTER * Logical -+ ) -+{ -+ gckKERNEL kernel = Kernel; -+ gctPHYS_ADDR physical = gcmNAME_TO_PTR(Physical); -+ -+ return gckOS_MapMemory(Kernel->os, physical, Bytes, Logical); -+} -+ -+/******************************************************************************* -+** -+** gckKERNEL_UnmapMemory -+** -+** Unmap video memory from the current process space. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** gctPHYS_ADDR Physical -+** Physical address of video memory to map. -+** -+** gctSIZE_T Bytes -+** Number of bytes to map. -+** -+** gctPOINTER Logical -+** Base address of the mapped memory region. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckKERNEL_UnmapMemory( -+ IN gckKERNEL Kernel, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T Bytes, -+ IN gctPOINTER Logical -+ ) -+{ -+ gckKERNEL kernel = Kernel; -+ gctPHYS_ADDR physical = gcmNAME_TO_PTR(Physical); -+ -+ return gckOS_UnmapMemory(Kernel->os, physical, Bytes, Logical); -+} -+ -+/******************************************************************************* -+** -+** gckKERNEL_MapVideoMemory -+** -+** Get the logical address for a hardware specific memory address for the -+** current process. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** gctBOOL InUserSpace -+** gcvTRUE to map the memory into the user space. -+** -+** gctUINT32 Address -+** Hardware specific memory address. -+** -+** OUTPUT: -+** -+** gctPOINTER * Logical -+** Pointer to a variable that will hold the logical address of the -+** specified memory address. -+*/ -+gceSTATUS -+gckKERNEL_MapVideoMemoryEx( -+ IN gckKERNEL Kernel, -+ IN gceCORE Core, -+ IN gctBOOL InUserSpace, -+ IN gctUINT32 Address, -+ OUT gctPOINTER * Logical -+ ) -+{ -+ gckGALDEVICE device = gcvNULL; -+ PLINUX_MDL mdl = gcvNULL; -+ PLINUX_MDL_MAP mdlMap = gcvNULL; -+ gcePOOL pool = gcvPOOL_UNKNOWN; -+ gctUINT32 offset = 0; -+ gctUINT32 base = 0; -+ gceSTATUS status; -+ gctPOINTER logical = gcvNULL; -+ gctUINT32 baseAddress; -+ -+ gcmkHEADER_ARG("Kernel=%p InUserSpace=%d Address=%08x", -+ Kernel, InUserSpace, Address); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ gcmkVERIFY_ARGUMENT(Logical != NULL); -+ -+ /* Extract the pointer to the gckGALDEVICE class. */ -+ device = (gckGALDEVICE) Kernel->context; -+ -+#if gcdENABLE_VG -+ if (Core == gcvCORE_VG) -+ { -+ /* Split the memory address into a pool type and offset. */ -+ gcmkONERROR( -+ gckVGHARDWARE_SplitMemory(Kernel->vg->hardware, Address, &pool, &offset)); -+ } -+ else -+#endif -+ { -+ /* Split the memory address into a pool type and offset. */ -+ gcmkONERROR( -+ gckHARDWARE_SplitMemory(Kernel->hardware, Address, &pool, &offset)); -+ } -+ -+ /* Dispatch on pool. */ -+ switch (pool) -+ { -+ case gcvPOOL_LOCAL_INTERNAL: -+ /* Internal memory. */ -+ logical = device->internalLogical; -+ break; -+ -+ case gcvPOOL_LOCAL_EXTERNAL: -+ /* External memory. */ -+ logical = device->externalLogical; -+ break; -+ -+ case gcvPOOL_SYSTEM: -+ /* System memory. */ -+ if (device->contiguousMapped) -+ { -+ logical = device->contiguousBase; -+ } -+ else -+ { -+ gctINT processID; -+ gckOS_GetProcessID(&processID); -+ -+ mdl = (PLINUX_MDL) device->contiguousPhysical; -+ -+ mdlMap = FindMdlMap(mdl, processID); -+ gcmkASSERT(mdlMap); -+ -+ logical = (gctPOINTER) mdlMap->vmaAddr; -+ } -+#if gcdENABLE_VG -+ if (Core == gcvCORE_VG) -+ { -+ gcmkVERIFY_OK( -+ gckVGHARDWARE_SplitMemory(Kernel->vg->hardware, -+ device->contiguousVidMem->baseAddress, -+ &pool, -+ &base)); -+ } -+ else -+#endif -+ { -+ gctUINT32 systemBaseAddress = 0; -+ -+ if (Kernel->hardware->mmuVersion == 0) -+ { -+ gcmkONERROR(gckOS_GetBaseAddress(Kernel->os, &systemBaseAddress)); -+ } -+ -+ gcmkVERIFY_OK( -+ gckOS_CPUPhysicalToGPUPhysical( -+ Kernel->os, -+ device->contiguousVidMem->baseAddress - systemBaseAddress, -+ &baseAddress -+ )); -+ -+ gcmkVERIFY_OK( -+ gckHARDWARE_SplitMemory(Kernel->hardware, -+ baseAddress, -+ &pool, -+ &base)); -+ } -+ offset -= base; -+ break; -+ -+ default: -+ /* Invalid memory pool. */ -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ } -+ -+ /* Build logical address of specified address. */ -+ *Logical = (gctPOINTER) ((gctUINT8_PTR) logical + offset); -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Logical=%p", *Logical); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Retunn the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckKERNEL_MapVideoMemory -+** -+** Get the logical address for a hardware specific memory address for the -+** current process. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** gctBOOL InUserSpace -+** gcvTRUE to map the memory into the user space. -+** -+** gctUINT32 Address -+** Hardware specific memory address. -+** -+** OUTPUT: -+** -+** gctPOINTER * Logical -+** Pointer to a variable that will hold the logical address of the -+** specified memory address. -+*/ -+gceSTATUS -+gckKERNEL_MapVideoMemory( -+ IN gckKERNEL Kernel, -+ IN gctBOOL InUserSpace, -+ IN gctUINT32 Address, -+ OUT gctPOINTER * Logical -+ ) -+{ -+ return gckKERNEL_MapVideoMemoryEx(Kernel, gcvCORE_MAJOR, InUserSpace, Address, Logical); -+} -+/******************************************************************************* -+** -+** gckKERNEL_Notify -+** -+** This function iscalled by clients to notify the gckKERNRL object of an event. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** gceNOTIFY Notification -+** Notification event. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckKERNEL_Notify( -+ IN gckKERNEL Kernel, -+ IN gceNOTIFY Notification, -+ IN gctBOOL Data -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Kernel=%p Notification=%d Data=%d", -+ Kernel, Notification, Data); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ -+ /* Dispatch on notifcation. */ -+ switch (Notification) -+ { -+ case gcvNOTIFY_INTERRUPT: -+ /* Process the interrupt. */ -+ status = gckHARDWARE_Interrupt(Kernel->hardware, -+ Data); -+ break; -+ -+ default: -+ status = gcvSTATUS_OK; -+ break; -+ } -+ -+ /* Success. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckKERNEL_QuerySettings( -+ IN gckKERNEL Kernel, -+ OUT gcsKERNEL_SETTINGS * Settings -+ ) -+{ -+ gckGALDEVICE device; -+ -+ gcmkHEADER_ARG("Kernel=%p", Kernel); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ gcmkVERIFY_ARGUMENT(Settings != gcvNULL); -+ -+ /* Extract the pointer to the gckGALDEVICE class. */ -+ device = (gckGALDEVICE) Kernel->context; -+ -+ /* Fill in signal. */ -+ Settings->signal = device->signal; -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("Settings->signal=%d", Settings->signal); -+ return gcvSTATUS_OK; -+} -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_linux.h linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_linux.h ---- linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_linux.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_linux.h 2015-11-30 17:56:13.576137991 +0100 -@@ -0,0 +1,364 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#ifndef __gc_hal_kernel_linux_h_ -+#define __gc_hal_kernel_linux_h_ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#ifdef MODVERSIONS -+# include -+#endif -+#include -+#include -+ -+#include -+ -+#define NTSTRSAFE_NO_CCH_FUNCTIONS -+#include "gc_hal.h" -+#include "gc_hal_driver.h" -+#include "gc_hal_kernel.h" -+#include "gc_hal_kernel_platform.h" -+#include "gc_hal_kernel_device.h" -+#include "gc_hal_kernel_os.h" -+#include "gc_hal_kernel_debugfs.h" -+ -+ -+#define FIND_TASK_BY_PID(x) pid_task(find_vpid(x), PIDTYPE_PID) -+ -+#define _WIDE(string) L##string -+#define WIDE(string) _WIDE(string) -+ -+#define countof(a) (sizeof(a) / sizeof(a[0])) -+ -+#ifndef DEVICE_NAME -+# define DEVICE_NAME "galcore" -+#endif -+ -+#define GetPageCount(size, offset) ((((size) + ((offset) & ~PAGE_CACHE_MASK)) + PAGE_CACHE_SIZE - 1) >> PAGE_CACHE_SHIFT) -+ -+#define gcdVM_FLAGS (VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_DONTDUMP) -+ -+/* Protection bit when mapping memroy to user sapce */ -+#define gcmkPAGED_MEMROY_PROT(x) pgprot_writecombine(x) -+ -+#if gcdNONPAGED_MEMORY_BUFFERABLE -+#define gcmkIOREMAP ioremap_wc -+#define gcmkNONPAGED_MEMROY_PROT(x) pgprot_writecombine(x) -+#elif !gcdNONPAGED_MEMORY_CACHEABLE -+#define gcmkIOREMAP ioremap_nocache -+#define gcmkNONPAGED_MEMROY_PROT(x) pgprot_noncached(x) -+#endif -+ -+#define gcdSUPPRESS_OOM_MESSAGE 1 -+ -+#if gcdSUPPRESS_OOM_MESSAGE -+#define gcdNOWARN __GFP_NOWARN -+#else -+#define gcdNOWARN 0 -+#endif -+ -+/******************************************************************************\ -+********************************** Structures ********************************** -+\******************************************************************************/ -+typedef struct _gcsIOMMU * gckIOMMU; -+ -+typedef struct _gcsUSER_MAPPING * gcsUSER_MAPPING_PTR; -+typedef struct _gcsUSER_MAPPING -+{ -+ /* Pointer to next mapping structure. */ -+ gcsUSER_MAPPING_PTR next; -+ -+ /* Physical address of this mapping. */ -+ gctUINT32 physical; -+ -+ /* Logical address of this mapping. */ -+ gctPOINTER logical; -+ -+ /* Number of bytes of this mapping. */ -+ gctSIZE_T bytes; -+ -+ /* Starting address of this mapping. */ -+ gctINT8_PTR start; -+ -+ /* Ending address of this mapping. */ -+ gctINT8_PTR end; -+} -+gcsUSER_MAPPING; -+ -+typedef struct _gcsINTEGER_DB * gcsINTEGER_DB_PTR; -+typedef struct _gcsINTEGER_DB -+{ -+ struct idr idr; -+ spinlock_t lock; -+ gctINT curr; -+} -+gcsINTEGER_DB; -+ -+struct _gckOS -+{ -+ /* Object. */ -+ gcsOBJECT object; -+ -+ /* Pointer to device */ -+ gckGALDEVICE device; -+ -+ /* Memory management */ -+ gctPOINTER memoryLock; -+ gctPOINTER memoryMapLock; -+ -+ struct _LINUX_MDL *mdlHead; -+ struct _LINUX_MDL *mdlTail; -+ -+ /* Kernel process ID. */ -+ gctUINT32 kernelProcessID; -+ -+ /* Signal management. */ -+ -+ /* Lock. */ -+ gctPOINTER signalMutex; -+ -+ /* signal id database. */ -+ gcsINTEGER_DB signalDB; -+ -+#if gcdANDROID_NATIVE_FENCE_SYNC -+ /* Lock. */ -+ gctPOINTER syncPointMutex; -+ -+ /* sync point id database. */ -+ gcsINTEGER_DB syncPointDB; -+#endif -+ -+ gcsUSER_MAPPING_PTR userMap; -+ gctPOINTER debugLock; -+ -+ /* workqueue for os timer. */ -+ struct workqueue_struct * workqueue; -+ -+ /* Allocate extra page to avoid cache overflow */ -+ struct page* paddingPage; -+ -+ /* Detect unfreed allocation. */ -+ atomic_t allocateCount; -+ -+ struct list_head allocatorList; -+ -+ gcsDEBUGFS_DIR allocatorDebugfsDir; -+ -+ /* Lock for register access check. */ -+ struct mutex registerAccessLocks[gcdMAX_GPU_COUNT]; -+ -+ /* External power states. */ -+ gctBOOL powerStates[gcdMAX_GPU_COUNT]; -+ -+ /* External clock states. */ -+ gctBOOL clockStates[gcdMAX_GPU_COUNT]; -+ -+ /* IOMMU. */ -+ gckIOMMU iommu; -+}; -+ -+typedef struct _gcsSIGNAL * gcsSIGNAL_PTR; -+typedef struct _gcsSIGNAL -+{ -+ /* Kernel sync primitive. */ -+ struct completion obj; -+ -+ /* Manual reset flag. */ -+ gctBOOL manualReset; -+ -+ /* The reference counter. */ -+ atomic_t ref; -+ -+ /* The owner of the signal. */ -+ gctHANDLE process; -+ -+ gckHARDWARE hardware; -+ -+ /* ID. */ -+ gctUINT32 id; -+} -+gcsSIGNAL; -+ -+#if gcdANDROID_NATIVE_FENCE_SYNC -+typedef struct _gcsSYNC_POINT * gcsSYNC_POINT_PTR; -+typedef struct _gcsSYNC_POINT -+{ -+ /* The reference counter. */ -+ atomic_t ref; -+ -+ /* State. */ -+ atomic_t state; -+ -+ /* timeline. */ -+ struct sync_timeline * timeline; -+ -+ /* ID. */ -+ gctUINT32 id; -+} -+gcsSYNC_POINT; -+#endif -+ -+typedef struct _gcsPageInfo * gcsPageInfo_PTR; -+typedef struct _gcsPageInfo -+{ -+ struct page **pages; -+ gctUINT32_PTR pageTable; -+ gctUINT32 extraPage; -+ gctUINT32 address; -+#if gcdPROCESS_ADDRESS_SPACE -+ gckMMU mmu; -+#endif -+} -+gcsPageInfo; -+ -+typedef struct _gcsOSTIMER * gcsOSTIMER_PTR; -+typedef struct _gcsOSTIMER -+{ -+ struct delayed_work work; -+ gctTIMERFUNCTION function; -+ gctPOINTER data; -+} gcsOSTIMER; -+ -+gceSTATUS -+gckOS_ImportAllocators( -+ gckOS Os -+ ); -+ -+gceSTATUS -+gckOS_FreeAllocators( -+ gckOS Os -+ ); -+ -+gceSTATUS -+_HandleOuterCache( -+ IN gckOS Os, -+ IN gctUINT32 Physical, -+ IN gctPOINTER Logical, -+ IN gctSIZE_T Bytes, -+ IN gceCACHEOPERATION Type -+ ); -+ -+gceSTATUS -+_ConvertLogical2Physical( -+ IN gckOS Os, -+ IN gctPOINTER Logical, -+ IN gctUINT32 ProcessID, -+ IN PLINUX_MDL Mdl, -+ OUT gctUINT32_PTR Physical -+ ); -+ -+gctSTRING -+_CreateKernelVirtualMapping( -+ IN PLINUX_MDL Mdl -+ ); -+ -+void -+_DestoryKernelVirtualMapping( -+ IN gctSTRING Addr -+ ); -+ -+void -+_UnmapUserLogical( -+ IN gctPOINTER Logical, -+ IN gctUINT32 Size -+ ); -+ -+static inline gctINT -+_GetProcessID( -+ void -+ ) -+{ -+ return task_tgid_vnr(current); -+} -+ -+static inline struct page * -+_NonContiguousToPage( -+ IN struct page ** Pages, -+ IN gctUINT32 Index -+ ) -+{ -+ gcmkASSERT(Pages != gcvNULL); -+ return Pages[Index]; -+} -+ -+static inline unsigned long -+_NonContiguousToPfn( -+ IN struct page ** Pages, -+ IN gctUINT32 Index -+ ) -+{ -+ gcmkASSERT(Pages != gcvNULL); -+ return page_to_pfn(_NonContiguousToPage(Pages, Index)); -+} -+ -+static inline unsigned long -+_NonContiguousToPhys( -+ IN struct page ** Pages, -+ IN gctUINT32 Index -+ ) -+{ -+ gcmkASSERT(Pages != gcvNULL); -+ return page_to_phys(_NonContiguousToPage(Pages, Index)); -+} -+ -+#ifdef CONFIG_IOMMU_SUPPORT -+void -+gckIOMMU_Destory( -+ IN gckOS Os, -+ IN gckIOMMU Iommu -+ ); -+ -+gceSTATUS -+gckIOMMU_Construct( -+ IN gckOS Os, -+ OUT gckIOMMU * Iommu -+ ); -+ -+gceSTATUS -+gckIOMMU_Map( -+ IN gckIOMMU Iommu, -+ IN gctUINT32 DomainAddress, -+ IN gctUINT32 Physical, -+ IN gctUINT32 Bytes -+ ); -+ -+gceSTATUS -+gckIOMMU_Unmap( -+ IN gckIOMMU Iommu, -+ IN gctUINT32 DomainAddress, -+ IN gctUINT32 Bytes -+ ); -+#endif -+ -+#endif /* __gc_hal_kernel_linux_h_ */ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_math.c linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_math.c ---- linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_math.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_math.c 2015-11-30 17:56:13.576137991 +0100 -@@ -0,0 +1,32 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#include "gc_hal_kernel_linux.h" -+ -+gctINT -+gckMATH_ModuloInt( -+ IN gctINT X, -+ IN gctINT Y -+ ) -+{ -+ if(Y ==0) {return 0;} -+ else {return X % Y;} -+} -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_mmu.c linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_mmu.c ---- linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_mmu.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_mmu.c 2015-11-30 17:56:13.580137725 +0100 -@@ -0,0 +1,2260 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#include "gc_hal_kernel_precomp.h" -+ -+#define _GC_OBJ_ZONE gcvZONE_MMU -+ -+typedef enum _gceMMU_TYPE -+{ -+ gcvMMU_USED = (0 << 4), -+ gcvMMU_SINGLE = (1 << 4), -+ gcvMMU_FREE = (2 << 4), -+} -+gceMMU_TYPE; -+ -+#define gcmENTRY_TYPE(x) (x & 0xF0) -+ -+#define gcdMMU_TABLE_DUMP 0 -+ -+#define gcdUSE_MMU_EXCEPTION 1 -+ -+/* -+ gcdMMU_CLEAR_VALUE -+ -+ The clear value for the entry of the old MMU. -+*/ -+#ifndef gcdMMU_CLEAR_VALUE -+# define gcdMMU_CLEAR_VALUE 0x00000ABC -+#endif -+ -+#define gcdVERTEX_START (128 << 10) -+ -+typedef struct _gcsMMU_STLB *gcsMMU_STLB_PTR; -+ -+typedef struct _gcsMMU_STLB -+{ -+ gctPHYS_ADDR physical; -+ gctUINT32_PTR logical; -+ gctSIZE_T size; -+ gctUINT32 physBase; -+ gctSIZE_T pageCount; -+ gctUINT32 mtlbIndex; -+ gctUINT32 mtlbEntryNum; -+ gcsMMU_STLB_PTR next; -+} gcsMMU_STLB; -+ -+#if gcdSHARED_PAGETABLE -+typedef struct _gcsSharedPageTable * gcsSharedPageTable_PTR; -+typedef struct _gcsSharedPageTable -+{ -+ /* Shared gckMMU object. */ -+ gckMMU mmu; -+ -+ /* Hardwares which use this shared pagetable. */ -+ gckHARDWARE hardwares[gcdMAX_GPU_COUNT]; -+ -+ /* Number of cores use this shared pagetable. */ -+ gctUINT32 reference; -+} -+gcsSharedPageTable; -+ -+static gcsSharedPageTable_PTR sharedPageTable = gcvNULL; -+#endif -+ -+#if gcdMIRROR_PAGETABLE -+typedef struct _gcsMirrorPageTable * gcsMirrorPageTable_PTR; -+typedef struct _gcsMirrorPageTable -+{ -+ /* gckMMU objects. */ -+ gckMMU mmus[gcdMAX_GPU_COUNT]; -+ -+ /* Hardwares which use this shared pagetable. */ -+ gckHARDWARE hardwares[gcdMAX_GPU_COUNT]; -+ -+ /* Number of cores use this shared pagetable. */ -+ gctUINT32 reference; -+} -+gcsMirrorPageTable; -+ -+static gcsMirrorPageTable_PTR mirrorPageTable = gcvNULL; -+static gctPOINTER mirrorPageTableMutex = gcvNULL; -+#endif -+ -+typedef struct _gcsDynamicSpaceNode * gcsDynamicSpaceNode_PTR; -+typedef struct _gcsDynamicSpaceNode -+{ -+ gctUINT32 start; -+ gctINT32 entries; -+} -+gcsDynamicSpaceNode; -+ -+static void -+_WritePageEntry( -+ IN gctUINT32_PTR PageEntry, -+ IN gctUINT32 EntryValue -+ ) -+{ -+ static gctUINT16 data = 0xff00; -+ -+ if (*(gctUINT8 *)&data == 0xff) -+ { -+ *PageEntry = gcmSWAB32(EntryValue); -+ } -+ else -+ { -+ *PageEntry = EntryValue; -+ } -+} -+ -+static gctUINT32 -+_ReadPageEntry( -+ IN gctUINT32_PTR PageEntry -+ ) -+{ -+ static gctUINT16 data = 0xff00; -+ gctUINT32 entryValue; -+ -+ if (*(gctUINT8 *)&data == 0xff) -+ { -+ entryValue = *PageEntry; -+ return gcmSWAB32(entryValue); -+ } -+ else -+ { -+ return *PageEntry; -+ } -+} -+ -+static gceSTATUS -+_FillPageTable( -+ IN gctUINT32_PTR PageTable, -+ IN gctUINT32 PageCount, -+ IN gctUINT32 EntryValue -+) -+{ -+ gctUINT i; -+ -+ for (i = 0; i < PageCount; i++) -+ { -+ _WritePageEntry(PageTable + i, EntryValue); -+ } -+ -+ return gcvSTATUS_OK; -+} -+ -+static gceSTATUS -+_Link( -+ IN gckMMU Mmu, -+ IN gctUINT32 Index, -+ IN gctUINT32 Next -+ ) -+{ -+ if (Index >= Mmu->pageTableEntries) -+ { -+ /* Just move heap pointer. */ -+ Mmu->heapList = Next; -+ } -+ else -+ { -+ /* Address page table. */ -+ gctUINT32_PTR map = Mmu->mapLogical; -+ -+ /* Dispatch on node type. */ -+ switch (gcmENTRY_TYPE(_ReadPageEntry(&map[Index]))) -+ { -+ case gcvMMU_SINGLE: -+ /* Set single index. */ -+ _WritePageEntry(&map[Index], (Next << 8) | gcvMMU_SINGLE); -+ break; -+ -+ case gcvMMU_FREE: -+ /* Set index. */ -+ _WritePageEntry(&map[Index + 1], Next); -+ break; -+ -+ default: -+ gcmkFATAL("MMU table correcupted at index %u!", Index); -+ return gcvSTATUS_HEAP_CORRUPTED; -+ } -+ } -+ -+ /* Success. */ -+ return gcvSTATUS_OK; -+} -+ -+static gceSTATUS -+_AddFree( -+ IN gckMMU Mmu, -+ IN gctUINT32 Index, -+ IN gctUINT32 Node, -+ IN gctUINT32 Count -+ ) -+{ -+ gctUINT32_PTR map = Mmu->mapLogical; -+ -+ if (Count == 1) -+ { -+ /* Initialize a single page node. */ -+ _WritePageEntry(map + Node, (~((1U<<8)-1)) | gcvMMU_SINGLE); -+ } -+ else -+ { -+ /* Initialize the node. */ -+ _WritePageEntry(map + Node + 0, (Count << 8) | gcvMMU_FREE); -+ _WritePageEntry(map + Node + 1, ~0U); -+ } -+ -+ /* Append the node. */ -+ return _Link(Mmu, Index, Node); -+} -+ -+static gceSTATUS -+_Collect( -+ IN gckMMU Mmu -+ ) -+{ -+ gctUINT32_PTR map = Mmu->mapLogical; -+ gceSTATUS status; -+ gctUINT32 i, previous, start = 0, count = 0; -+ -+ previous = Mmu->heapList = ~0U; -+ Mmu->freeNodes = gcvFALSE; -+ -+ /* Walk the entire page table. */ -+ for (i = 0; i < Mmu->pageTableEntries; ++i) -+ { -+ /* Dispatch based on type of page. */ -+ switch (gcmENTRY_TYPE(_ReadPageEntry(&map[i]))) -+ { -+ case gcvMMU_USED: -+ /* Used page, so close any open node. */ -+ if (count > 0) -+ { -+ /* Add the node. */ -+ gcmkONERROR(_AddFree(Mmu, previous, start, count)); -+ -+ /* Reset the node. */ -+ previous = start; -+ count = 0; -+ } -+ break; -+ -+ case gcvMMU_SINGLE: -+ /* Single free node. */ -+ if (count++ == 0) -+ { -+ /* Start a new node. */ -+ start = i; -+ } -+ break; -+ -+ case gcvMMU_FREE: -+ /* A free node. */ -+ if (count == 0) -+ { -+ /* Start a new node. */ -+ start = i; -+ } -+ -+ /* Advance the count. */ -+ count += _ReadPageEntry(&map[i]) >> 8; -+ -+ /* Advance the index into the page table. */ -+ i += (_ReadPageEntry(&map[i]) >> 8) - 1; -+ break; -+ -+ default: -+ gcmkFATAL("MMU page table correcupted at index %u!", i); -+ return gcvSTATUS_HEAP_CORRUPTED; -+ } -+ } -+ -+ /* See if we have an open node left. */ -+ if (count > 0) -+ { -+ /* Add the node to the list. */ -+ gcmkONERROR(_AddFree(Mmu, previous, start, count)); -+ } -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_MMU, -+ "Performed a garbage collection of the MMU heap."); -+ -+ /* Success. */ -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the staus. */ -+ return status; -+} -+ -+static gctUINT32 -+_SetPage(gctUINT32 PageAddress) -+{ -+ return PageAddress -+ /* writable */ -+ | (1 << 2) -+ /* Ignore exception */ -+ | (0 << 1) -+ /* Present */ -+ | (1 << 0); -+} -+ -+#if gcdPROCESS_ADDRESS_SPACE -+gctUINT32 -+_AddressToIndex( -+ IN gckMMU Mmu, -+ IN gctUINT32 Address -+ ) -+{ -+ gctUINT32 mtlbOffset = (Address & gcdMMU_MTLB_MASK) >> gcdMMU_MTLB_SHIFT; -+ gctUINT32 stlbOffset = (Address & gcdMMU_STLB_4K_MASK) >> gcdMMU_STLB_4K_SHIFT; -+ -+ return (mtlbOffset - Mmu->dynamicMappingStart) * gcdMMU_STLB_4K_ENTRY_NUM + stlbOffset; -+} -+ -+gctUINT32 -+_MtlbOffset( -+ gctUINT32 Address -+ ) -+{ -+ return (Address & gcdMMU_MTLB_MASK) >> gcdMMU_MTLB_SHIFT; -+} -+ -+gctUINT32 -+_StlbOffset( -+ gctUINT32 Address -+ ) -+{ -+ return (Address & gcdMMU_STLB_4K_MASK) >> gcdMMU_STLB_4K_SHIFT; -+} -+ -+static gceSTATUS -+_AllocateStlb( -+ IN gckOS Os, -+ OUT gcsMMU_STLB_PTR *Stlb -+ ) -+{ -+ gceSTATUS status; -+ gcsMMU_STLB_PTR stlb; -+ gctPOINTER pointer; -+ -+ /* Allocate slave TLB record. */ -+ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(gcsMMU_STLB), &pointer)); -+ stlb = pointer; -+ -+ stlb->size = gcdMMU_STLB_4K_SIZE; -+ -+ /* Allocate slave TLB entries. */ -+ gcmkONERROR(gckOS_AllocateContiguous( -+ Os, -+ gcvFALSE, -+ &stlb->size, -+ &stlb->physical, -+ (gctPOINTER)&stlb->logical -+ )); -+ -+ gcmkONERROR(gckOS_GetPhysicalAddress(Os, stlb->logical, &stlb->physBase)); -+ -+#if gcdUSE_MMU_EXCEPTION -+ _FillPageTable(stlb->logical, stlb->size / 4, gcdMMU_STLB_EXCEPTION); -+#else -+ gckOS_ZeroMemory(stlb->logical, stlb->size); -+#endif -+ -+ *Stlb = stlb; -+ -+ return gcvSTATUS_OK; -+ -+OnError: -+ return status; -+} -+ -+gceSTATUS -+_SetupProcessAddressSpace( -+ IN gckMMU Mmu -+ ) -+{ -+ gceSTATUS status; -+ gctINT numEntries = 0; -+ gctUINT32_PTR map; -+ -+ numEntries = gcdPROCESS_ADDRESS_SPACE_SIZE -+ /* Address space mapped by one MTLB entry. */ -+ / (1 << gcdMMU_MTLB_SHIFT); -+ -+ Mmu->dynamicMappingStart = 0; -+ -+ Mmu->pageTableSize = numEntries * 4096; -+ -+ Mmu->pageTableEntries = Mmu->pageTableSize / gcmSIZEOF(gctUINT32); -+ -+ gcmkONERROR(gckOS_Allocate(Mmu->os, -+ Mmu->pageTableSize, -+ (void **)&Mmu->mapLogical)); -+ -+ /* Initilization. */ -+ map = Mmu->mapLogical; -+ _WritePageEntry(map, (Mmu->pageTableEntries << 8) | gcvMMU_FREE); -+ _WritePageEntry(map + 1, ~0U); -+ Mmu->heapList = 0; -+ Mmu->freeNodes = gcvFALSE; -+ -+ return gcvSTATUS_OK; -+ -+OnError: -+ return status; -+} -+#else -+static gceSTATUS -+_FillFlatMapping( -+ IN gckMMU Mmu, -+ IN gctUINT32 PhysBase, -+ OUT gctSIZE_T Size -+ ) -+{ -+ gceSTATUS status; -+ gctBOOL mutex = gcvFALSE; -+ gcsMMU_STLB_PTR head = gcvNULL, pre = gcvNULL; -+ gctUINT32 start = PhysBase & (~gcdMMU_PAGE_64K_MASK); -+ gctUINT32 end = (PhysBase + Size - 1) & (~gcdMMU_PAGE_64K_MASK); -+ gctUINT32 mStart = start >> gcdMMU_MTLB_SHIFT; -+ gctUINT32 mEnd = end >> gcdMMU_MTLB_SHIFT; -+ gctUINT32 sStart = (start & gcdMMU_STLB_64K_MASK) >> gcdMMU_STLB_64K_SHIFT; -+ gctUINT32 sEnd = (end & gcdMMU_STLB_64K_MASK) >> gcdMMU_STLB_64K_SHIFT; -+ gctBOOL ace = gckHARDWARE_IsFeatureAvailable(Mmu->hardware, gcvFEATURE_ACE); -+ -+ /* Grab the mutex. */ -+ gcmkONERROR(gckOS_AcquireMutex(Mmu->os, Mmu->pageTableMutex, gcvINFINITE)); -+ mutex = gcvTRUE; -+ -+ while (mStart <= mEnd) -+ { -+ gcmkASSERT(mStart < gcdMMU_MTLB_ENTRY_NUM); -+ if (*(Mmu->mtlbLogical + mStart) == 0) -+ { -+ gcsMMU_STLB_PTR stlb; -+ gctPOINTER pointer = gcvNULL; -+ gctUINT32 last = (mStart == mEnd) ? sEnd : (gcdMMU_STLB_64K_ENTRY_NUM - 1); -+ gctUINT32 mtlbEntry; -+ -+ gcmkONERROR(gckOS_Allocate(Mmu->os, sizeof(struct _gcsMMU_STLB), &pointer)); -+ stlb = pointer; -+ -+ stlb->mtlbEntryNum = 0; -+ stlb->next = gcvNULL; -+ stlb->physical = gcvNULL; -+ stlb->logical = gcvNULL; -+ stlb->size = gcdMMU_STLB_64K_SIZE; -+ stlb->pageCount = 0; -+ -+ if (pre == gcvNULL) -+ { -+ pre = head = stlb; -+ } -+ else -+ { -+ gcmkASSERT(pre->next == gcvNULL); -+ pre->next = stlb; -+ pre = stlb; -+ } -+ -+ gcmkONERROR( -+ gckOS_AllocateContiguous(Mmu->os, -+ gcvFALSE, -+ &stlb->size, -+ &stlb->physical, -+ (gctPOINTER)&stlb->logical)); -+ -+ gcmkONERROR(gckOS_ZeroMemory(stlb->logical, stlb->size)); -+ -+ gcmkONERROR(gckOS_GetPhysicalAddress( -+ Mmu->os, -+ stlb->logical, -+ &stlb->physBase)); -+ -+ if (stlb->physBase & (gcdMMU_STLB_64K_SIZE - 1)) -+ { -+ gcmkONERROR(gcvSTATUS_NOT_ALIGNED); -+ } -+ -+ mtlbEntry = stlb->physBase -+ /* 64KB page size */ -+ | (1 << 2) -+ /* Ignore exception */ -+ | (0 << 1) -+ /* Present */ -+ | (1 << 0); -+ -+ if (ace) -+ { -+ mtlbEntry = mtlbEntry -+ /* Secure */ -+ | (1 << 4); -+ } -+ -+ _WritePageEntry(Mmu->mtlbLogical + mStart, mtlbEntry); -+ -+#if gcdMMU_TABLE_DUMP -+ gckOS_Print("%s(%d): insert MTLB[%d]: %08x\n", -+ __FUNCTION__, __LINE__, -+ mStart, -+ _ReadPageEntry(Mmu->mtlbLogical + mStart)); -+#endif -+ -+ stlb->mtlbIndex = mStart; -+ stlb->mtlbEntryNum = 1; -+#if gcdMMU_TABLE_DUMP -+ gckOS_Print("%s(%d): STLB: logical:%08x -> physical:%08x\n", -+ __FUNCTION__, __LINE__, -+ stlb->logical, -+ stlb->physBase); -+#endif -+ -+ while (sStart <= last) -+ { -+ gcmkASSERT(!(start & gcdMMU_PAGE_64K_MASK)); -+ _WritePageEntry(stlb->logical + sStart, _SetPage(start)); -+#if gcdMMU_TABLE_DUMP -+ gckOS_Print("%s(%d): insert STLB[%d]: %08x\n", -+ __FUNCTION__, __LINE__, -+ sStart, -+ _ReadPageEntry(stlb->logical + sStart)); -+#endif -+ /* next page. */ -+ start += gcdMMU_PAGE_64K_SIZE; -+ sStart++; -+ stlb->pageCount++; -+ } -+ -+ sStart = 0; -+ ++mStart; -+ } -+ else -+ { -+ gcmkONERROR(gcvSTATUS_INVALID_REQUEST); -+ } -+ } -+ -+ /* Insert the stlb into staticSTLB. */ -+ if (Mmu->staticSTLB == gcvNULL) -+ { -+ Mmu->staticSTLB = head; -+ } -+ else -+ { -+ gcmkASSERT(pre == gcvNULL); -+ gcmkASSERT(pre->next == gcvNULL); -+ pre->next = Mmu->staticSTLB; -+ Mmu->staticSTLB = head; -+ } -+ -+ /* Release the mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex)); -+ -+ return gcvSTATUS_OK; -+ -+OnError: -+ -+ /* Roll back. */ -+ while (head != gcvNULL) -+ { -+ pre = head; -+ head = head->next; -+ -+ if (pre->physical != gcvNULL) -+ { -+ gcmkVERIFY_OK( -+ gckOS_FreeContiguous(Mmu->os, -+ pre->physical, -+ pre->logical, -+ pre->size)); -+ } -+ -+ if (pre->mtlbEntryNum != 0) -+ { -+ gcmkASSERT(pre->mtlbEntryNum == 1); -+ _WritePageEntry(Mmu->mtlbLogical + pre->mtlbIndex, 0); -+ } -+ -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Mmu->os, pre)); -+ } -+ -+ if (mutex) -+ { -+ /* Release the mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex)); -+ } -+ -+ return status; -+} -+ -+static gceSTATUS -+_FindDynamicSpace( -+ IN gckMMU Mmu, -+ OUT gcsDynamicSpaceNode_PTR *Array, -+ OUT gctINT * Size -+ ) -+{ -+ gceSTATUS status = gcvSTATUS_OK; -+ gctPOINTER pointer = gcvNULL; -+ gcsDynamicSpaceNode_PTR array = gcvNULL; -+ gctINT size = 0; -+ gctINT i = 0, nodeStart = -1, nodeEntries = 0; -+ -+ /* Allocate memory for the array. */ -+ gcmkONERROR(gckOS_Allocate(Mmu->os, -+ gcmSIZEOF(*array) * (gcdMMU_MTLB_ENTRY_NUM / 2), -+ &pointer)); -+ -+ array = (gcsDynamicSpaceNode_PTR)pointer; -+ -+ /* Loop all the entries. */ -+ while (i < gcdMMU_MTLB_ENTRY_NUM) -+ { -+ if (!Mmu->mtlbLogical[i]) -+ { -+ if (nodeStart < 0) -+ { -+ /* This is the first entry of the dynamic space. */ -+ nodeStart = i; -+ nodeEntries = 1; -+ } -+ else -+ { -+ /* Other entries of the dynamic space. */ -+ nodeEntries++; -+ } -+ } -+ else if (nodeStart >= 0) -+ { -+ /* Save the previous node. */ -+ array[size].start = nodeStart; -+ array[size].entries = nodeEntries; -+ size++; -+ -+ /* Reset the start. */ -+ nodeStart = -1; -+ nodeEntries = 0; -+ } -+ -+ i++; -+ } -+ -+ /* Save the previous node. */ -+ if (nodeStart >= 0) -+ { -+ array[size].start = nodeStart; -+ array[size].entries = nodeEntries; -+ size++; -+ } -+ -+#if gcdMMU_TABLE_DUMP -+ for (i = 0; i < size; i++) -+ { -+ gckOS_Print("%s(%d): [%d]: start=%d, entries=%d.\n", -+ __FUNCTION__, __LINE__, -+ i, -+ array[i].start, -+ array[i].entries); -+ } -+#endif -+ -+ *Array = array; -+ *Size = size; -+ -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (pointer != gcvNULL) -+ { -+ gckOS_Free(Mmu->os, pointer); -+ } -+ -+ return status; -+} -+ -+static gceSTATUS -+_SetupDynamicSpace( -+ IN gckMMU Mmu -+ ) -+{ -+ gceSTATUS status; -+ gcsDynamicSpaceNode_PTR nodeArray = gcvNULL; -+ gctINT i, nodeArraySize = 0; -+ gctUINT32 physical; -+ gctINT numEntries = 0; -+ gctUINT32_PTR map; -+ gctBOOL acquired = gcvFALSE; -+ gctUINT32 mtlbEntry; -+ gctBOOL ace = gckHARDWARE_IsFeatureAvailable(Mmu->hardware, gcvFEATURE_ACE); -+ -+ /* Find all the dynamic address space. */ -+ gcmkONERROR(_FindDynamicSpace(Mmu, &nodeArray, &nodeArraySize)); -+ -+ /* TODO: We only use the largest one for now. */ -+ for (i = 0; i < nodeArraySize; i++) -+ { -+ if (nodeArray[i].entries > numEntries) -+ { -+ Mmu->dynamicMappingStart = nodeArray[i].start; -+ numEntries = nodeArray[i].entries; -+ } -+ } -+ -+ gckOS_Free(Mmu->os, (gctPOINTER)nodeArray); -+ -+ Mmu->pageTableSize = numEntries * 4096; -+ -+ gcmkSAFECASTSIZET(Mmu->pageTableEntries, Mmu->pageTableSize / gcmSIZEOF(gctUINT32)); -+ -+ gcmkONERROR(gckOS_Allocate(Mmu->os, -+ Mmu->pageTableSize, -+ (void **)&Mmu->mapLogical)); -+ -+ /* Construct Slave TLB. */ -+ gcmkONERROR(gckOS_AllocateContiguous(Mmu->os, -+ gcvFALSE, -+ &Mmu->pageTableSize, -+ &Mmu->pageTablePhysical, -+ (gctPOINTER)&Mmu->pageTableLogical)); -+ -+#if gcdUSE_MMU_EXCEPTION -+ gcmkONERROR(_FillPageTable(Mmu->pageTableLogical, -+ Mmu->pageTableEntries, -+ /* Enable exception */ -+ 1 << 1)); -+#else -+ /* Invalidate all entries. */ -+ gcmkONERROR(gckOS_ZeroMemory(Mmu->pageTableLogical, -+ Mmu->pageTableSize)); -+#endif -+ -+ /* Initilization. */ -+ map = Mmu->mapLogical; -+ _WritePageEntry(map, (Mmu->pageTableEntries << 8) | gcvMMU_FREE); -+ _WritePageEntry(map + 1, ~0U); -+ Mmu->heapList = 0; -+ Mmu->freeNodes = gcvFALSE; -+ -+ gcmkONERROR(gckOS_GetPhysicalAddress(Mmu->os, -+ Mmu->pageTableLogical, -+ &physical)); -+ -+ /* Grab the mutex. */ -+ gcmkONERROR(gckOS_AcquireMutex(Mmu->os, Mmu->pageTableMutex, gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ /* Map to Master TLB. */ -+ for (i = (gctINT)Mmu->dynamicMappingStart; -+ i < (gctINT)Mmu->dynamicMappingStart + numEntries; -+ i++) -+ { -+ mtlbEntry = physical -+ /* 4KB page size */ -+ | (0 << 2) -+ /* Ignore exception */ -+ | (0 << 1) -+ /* Present */ -+ | (1 << 0); -+ -+ if (ace) -+ { -+ mtlbEntry = mtlbEntry -+ /* Secure */ -+ | (1 << 4); -+ } -+ -+ _WritePageEntry(Mmu->mtlbLogical + i, mtlbEntry); -+ -+#if gcdMMU_TABLE_DUMP -+ gckOS_Print("%s(%d): insert MTLB[%d]: %08x\n", -+ __FUNCTION__, __LINE__, -+ i, -+ _ReadPageEntry(Mmu->mtlbLogical + i)); -+#endif -+ physical += gcdMMU_STLB_4K_SIZE; -+ } -+ -+ /* Release the mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex)); -+ -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (Mmu->mapLogical) -+ { -+ gcmkVERIFY_OK( -+ gckOS_Free(Mmu->os, (gctPOINTER) Mmu->mapLogical)); -+ -+ -+ gcmkVERIFY_OK( -+ gckOS_FreeContiguous(Mmu->os, -+ Mmu->pageTablePhysical, -+ (gctPOINTER) Mmu->pageTableLogical, -+ Mmu->pageTableSize)); -+ } -+ -+ if (acquired) -+ { -+ /* Release the mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex)); -+ } -+ -+ return status; -+} -+#endif -+ -+/******************************************************************************* -+** -+** _Construct -+** -+** Construct a new gckMMU object. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** gctSIZE_T MmuSize -+** Number of bytes for the page table. -+** -+** OUTPUT: -+** -+** gckMMU * Mmu -+** Pointer to a variable that receives the gckMMU object pointer. -+*/ -+gceSTATUS -+_Construct( -+ IN gckKERNEL Kernel, -+ IN gctSIZE_T MmuSize, -+ OUT gckMMU * Mmu -+ ) -+{ -+ gckOS os; -+ gckHARDWARE hardware; -+ gceSTATUS status; -+ gckMMU mmu = gcvNULL; -+ gctUINT32_PTR map; -+ gctPOINTER pointer = gcvNULL; -+#if gcdPROCESS_ADDRESS_SPACE -+ gctUINT32 i; -+ gctUINT32 physical; -+#endif -+ gctUINT32 physBase; -+ gctUINT32 physSize; -+ gctUINT32 gpuAddress; -+ -+ gcmkHEADER_ARG("Kernel=0x%x MmuSize=%lu", Kernel, MmuSize); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ gcmkVERIFY_ARGUMENT(MmuSize > 0); -+ gcmkVERIFY_ARGUMENT(Mmu != gcvNULL); -+ -+ /* Extract the gckOS object pointer. */ -+ os = Kernel->os; -+ gcmkVERIFY_OBJECT(os, gcvOBJ_OS); -+ -+ /* Extract the gckHARDWARE object pointer. */ -+ hardware = Kernel->hardware; -+ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE); -+ -+ /* Allocate memory for the gckMMU object. */ -+ gcmkONERROR(gckOS_Allocate(os, sizeof(struct _gckMMU), &pointer)); -+ -+ mmu = pointer; -+ -+ /* Initialize the gckMMU object. */ -+ mmu->object.type = gcvOBJ_MMU; -+ mmu->os = os; -+ mmu->hardware = hardware; -+ mmu->pageTableMutex = gcvNULL; -+ mmu->pageTableLogical = gcvNULL; -+ mmu->mtlbLogical = gcvNULL; -+ mmu->staticSTLB = gcvNULL; -+ mmu->enabled = gcvFALSE; -+ mmu->mapLogical = gcvNULL; -+ -+ /* Create the page table mutex. */ -+ gcmkONERROR(gckOS_CreateMutex(os, &mmu->pageTableMutex)); -+ -+ if (hardware->mmuVersion == 0) -+ { -+ mmu->pageTableSize = MmuSize; -+ -+ /* Construct address space management table. */ -+ gcmkONERROR(gckOS_Allocate(mmu->os, -+ mmu->pageTableSize, -+ &pointer)); -+ -+ mmu->mapLogical = pointer; -+ -+ /* Construct page table read by GPU. */ -+ gcmkONERROR(gckOS_AllocateContiguous(mmu->os, -+ gcvFALSE, -+ &mmu->pageTableSize, -+ &mmu->pageTablePhysical, -+ (gctPOINTER)&mmu->pageTableLogical)); -+ -+ -+ /* Compute number of entries in page table. */ -+ gcmkSAFECASTSIZET(mmu->pageTableEntries, mmu->pageTableSize / sizeof(gctUINT32)); -+ -+ /* Mark all pages as free. */ -+ map = mmu->mapLogical; -+ -+#if gcdMMU_CLEAR_VALUE -+ _FillPageTable(mmu->pageTableLogical, mmu->pageTableEntries, gcdMMU_CLEAR_VALUE); -+#endif -+ -+ _WritePageEntry(map, (mmu->pageTableEntries << 8) | gcvMMU_FREE); -+ _WritePageEntry(map + 1, ~0U); -+ mmu->heapList = 0; -+ mmu->freeNodes = gcvFALSE; -+ } -+ else -+ { -+ /* Allocate the 4K mode MTLB table. */ -+ mmu->mtlbSize = gcdMMU_MTLB_SIZE + 64; -+ -+ gcmkONERROR( -+ gckOS_AllocateContiguous(os, -+ gcvFALSE, -+ &mmu->mtlbSize, -+ &mmu->mtlbPhysical, -+ &pointer)); -+ -+ mmu->mtlbLogical = pointer; -+ -+#if gcdPROCESS_ADDRESS_SPACE -+ _FillPageTable(pointer, mmu->mtlbSize / 4, gcdMMU_MTLB_EXCEPTION); -+ -+ /* Allocate a array to store stlbs. */ -+ gcmkONERROR(gckOS_Allocate(os, mmu->mtlbSize, &mmu->stlbs)); -+ -+ gckOS_ZeroMemory(mmu->stlbs, mmu->mtlbSize); -+ -+ for (i = 0; i < gcdMAX_GPU_COUNT; i++) -+ { -+ gcmkONERROR(gckOS_AtomConstruct(os, &mmu->pageTableDirty[i])); -+ } -+ -+ _SetupProcessAddressSpace(mmu); -+ -+ /* Map kernel command buffer in MMU. */ -+ for (i = 0; i < gcdCOMMAND_QUEUES; i++) -+ { -+ gcmkONERROR(gckOS_GetPhysicalAddress( -+ mmu->os, -+ Kernel->command->queues[i].logical, -+ &physical -+ )); -+ -+ gcmkONERROR(gckMMU_FlatMapping(mmu, physical)); -+ } -+#else -+ /* Invalid all the entries. */ -+ gcmkONERROR( -+ gckOS_ZeroMemory(pointer, mmu->mtlbSize)); -+ -+ gcmkONERROR( -+ gckOS_QueryOption(mmu->os, "physBase", &physBase)); -+ -+ gcmkONERROR( -+ gckOS_QueryOption(mmu->os, "physSize", &physSize)); -+ -+ gcmkONERROR( -+ gckOS_CPUPhysicalToGPUPhysical(mmu->os, physBase, &gpuAddress)); -+ -+ /* Setup [physBase - physSize) flat mapping. */ -+ gcmkONERROR(_FillFlatMapping( -+ mmu, -+ gpuAddress, -+ physSize -+ )); -+ -+ gcmkONERROR(_SetupDynamicSpace(mmu)); -+#endif -+ } -+ -+ /* Return the gckMMU object pointer. */ -+ *Mmu = mmu; -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Mmu=0x%x", *Mmu); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Roll back. */ -+ if (mmu != gcvNULL) -+ { -+ if (mmu->mapLogical != gcvNULL) -+ { -+ gcmkVERIFY_OK( -+ gckOS_Free(os, (gctPOINTER) mmu->mapLogical)); -+ -+ -+ gcmkVERIFY_OK( -+ gckOS_FreeContiguous(os, -+ mmu->pageTablePhysical, -+ (gctPOINTER) mmu->pageTableLogical, -+ mmu->pageTableSize)); -+ } -+ -+ if (mmu->mtlbLogical != gcvNULL) -+ { -+ gcmkVERIFY_OK( -+ gckOS_FreeContiguous(os, -+ mmu->mtlbPhysical, -+ (gctPOINTER) mmu->mtlbLogical, -+ mmu->mtlbSize)); -+ } -+ -+ if (mmu->pageTableMutex != gcvNULL) -+ { -+ /* Delete the mutex. */ -+ gcmkVERIFY_OK( -+ gckOS_DeleteMutex(os, mmu->pageTableMutex)); -+ } -+ -+ /* Mark the gckMMU object as unknown. */ -+ mmu->object.type = gcvOBJ_UNKNOWN; -+ -+ /* Free the allocates memory. */ -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, mmu)); -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** _Destroy -+** -+** Destroy a gckMMU object. -+** -+** INPUT: -+** -+** gckMMU Mmu -+** Pointer to an gckMMU object. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+_Destroy( -+ IN gckMMU Mmu -+ ) -+{ -+#if gcdPROCESS_ADDRESS_SPACE -+ gctUINT32 i; -+#endif -+ gcmkHEADER_ARG("Mmu=0x%x", Mmu); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU); -+ -+ while (Mmu->staticSTLB != gcvNULL) -+ { -+ gcsMMU_STLB_PTR pre = Mmu->staticSTLB; -+ Mmu->staticSTLB = pre->next; -+ -+ if (pre->physical != gcvNULL) -+ { -+ gcmkVERIFY_OK( -+ gckOS_FreeContiguous(Mmu->os, -+ pre->physical, -+ pre->logical, -+ pre->size)); -+ } -+ -+ if (pre->mtlbEntryNum != 0) -+ { -+ gcmkASSERT(pre->mtlbEntryNum == 1); -+ _WritePageEntry(Mmu->mtlbLogical + pre->mtlbIndex, 0); -+#if gcdMMU_TABLE_DUMP -+ gckOS_Print("%s(%d): clean MTLB[%d]\n", -+ __FUNCTION__, __LINE__, -+ pre->mtlbIndex); -+#endif -+ } -+ -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Mmu->os, pre)); -+ } -+ -+ if (Mmu->hardware->mmuVersion != 0) -+ { -+ gcmkVERIFY_OK( -+ gckOS_FreeContiguous(Mmu->os, -+ Mmu->mtlbPhysical, -+ (gctPOINTER) Mmu->mtlbLogical, -+ Mmu->mtlbSize)); -+ } -+ -+ /* Free address space management table. */ -+ if (Mmu->mapLogical != gcvNULL) -+ { -+ gcmkVERIFY_OK( -+ gckOS_Free(Mmu->os, (gctPOINTER) Mmu->mapLogical)); -+ } -+ -+ if (Mmu->pageTableLogical != gcvNULL) -+ { -+ /* Free page table. */ -+ gcmkVERIFY_OK( -+ gckOS_FreeContiguous(Mmu->os, -+ Mmu->pageTablePhysical, -+ (gctPOINTER) Mmu->pageTableLogical, -+ Mmu->pageTableSize)); -+ } -+ -+ /* Delete the page table mutex. */ -+ gcmkVERIFY_OK(gckOS_DeleteMutex(Mmu->os, Mmu->pageTableMutex)); -+ -+#if gcdPROCESS_ADDRESS_SPACE -+ for (i = 0; i < Mmu->mtlbSize / 4; i++) -+ { -+ struct _gcsMMU_STLB *stlb = ((struct _gcsMMU_STLB **)Mmu->stlbs)[i]; -+ -+ if (stlb) -+ { -+ gcmkVERIFY_OK(gckOS_FreeContiguous( -+ Mmu->os, -+ stlb->physical, -+ stlb->logical, -+ stlb->size)); -+ -+ gcmkOS_SAFE_FREE(Mmu->os, stlb); -+ } -+ } -+ -+ gcmkOS_SAFE_FREE(Mmu->os, Mmu->stlbs); -+#endif -+ -+ /* Mark the gckMMU object as unknown. */ -+ Mmu->object.type = gcvOBJ_UNKNOWN; -+ -+ /* Free the gckMMU object. */ -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Mmu->os, Mmu)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** _AdjstIndex -+** -+** Adjust the index from which we search for a usable node to make sure -+** index allocated is greater than Start. -+*/ -+gceSTATUS -+_AdjustIndex( -+ IN gckMMU Mmu, -+ IN gctUINT32 Index, -+ IN gctUINT32 PageCount, -+ IN gctUINT32 Start, -+ OUT gctUINT32 * IndexAdjusted -+ ) -+{ -+ gceSTATUS status; -+ gctUINT32 index = Index; -+ gctUINT32_PTR map = Mmu->mapLogical; -+ -+ gcmkHEADER(); -+ -+ for (; index < Mmu->pageTableEntries;) -+ { -+ gctUINT32 result = 0; -+ gctUINT32 nodeSize = 0; -+ -+ if (index >= Start) -+ { -+ break; -+ } -+ -+ switch (gcmENTRY_TYPE(map[index])) -+ { -+ case gcvMMU_SINGLE: -+ nodeSize = 1; -+ break; -+ -+ case gcvMMU_FREE: -+ nodeSize = map[index] >> 8; -+ break; -+ -+ default: -+ gcmkFATAL("MMU table correcupted at index %u!", index); -+ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES); -+ } -+ -+ if (nodeSize > PageCount) -+ { -+ result = index + (nodeSize - PageCount); -+ -+ if (result >= Start) -+ { -+ break; -+ } -+ } -+ -+ switch (gcmENTRY_TYPE(map[index])) -+ { -+ case gcvMMU_SINGLE: -+ index = map[index] >> 8; -+ break; -+ -+ case gcvMMU_FREE: -+ index = map[index + 1]; -+ break; -+ -+ default: -+ gcmkFATAL("MMU table correcupted at index %u!", index); -+ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES); -+ } -+ } -+ -+ *IndexAdjusted = index; -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckMMU_Construct( -+ IN gckKERNEL Kernel, -+ IN gctSIZE_T MmuSize, -+ OUT gckMMU * Mmu -+ ) -+{ -+#if gcdSHARED_PAGETABLE -+ gceSTATUS status; -+ gctPOINTER pointer; -+ -+ gcmkHEADER_ARG("Kernel=0x%08x", Kernel); -+ -+ if (sharedPageTable == gcvNULL) -+ { -+ gcmkONERROR( -+ gckOS_Allocate(Kernel->os, -+ sizeof(struct _gcsSharedPageTable), -+ &pointer)); -+ sharedPageTable = pointer; -+ -+ gcmkONERROR( -+ gckOS_ZeroMemory(sharedPageTable, -+ sizeof(struct _gcsSharedPageTable))); -+ -+ gcmkONERROR(_Construct(Kernel, MmuSize, &sharedPageTable->mmu)); -+ } -+ -+ *Mmu = sharedPageTable->mmu; -+ -+ sharedPageTable->hardwares[sharedPageTable->reference] = Kernel->hardware; -+ -+ sharedPageTable->reference++; -+ -+ gcmkFOOTER_ARG("sharedPageTable->reference=%lu", sharedPageTable->reference); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (sharedPageTable) -+ { -+ if (sharedPageTable->mmu) -+ { -+ gcmkVERIFY_OK(gckMMU_Destroy(sharedPageTable->mmu)); -+ } -+ -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, sharedPageTable)); -+ } -+ -+ gcmkFOOTER(); -+ return status; -+#elif gcdMIRROR_PAGETABLE -+ gceSTATUS status; -+ gctPOINTER pointer; -+ -+ gcmkHEADER_ARG("Kernel=0x%08x", Kernel); -+ -+ if (mirrorPageTable == gcvNULL) -+ { -+ gcmkONERROR( -+ gckOS_Allocate(Kernel->os, -+ sizeof(struct _gcsMirrorPageTable), -+ &pointer)); -+ mirrorPageTable = pointer; -+ -+ gcmkONERROR( -+ gckOS_ZeroMemory(mirrorPageTable, -+ sizeof(struct _gcsMirrorPageTable))); -+ -+ gcmkONERROR( -+ gckOS_CreateMutex(Kernel->os, &mirrorPageTableMutex)); -+ } -+ -+ gcmkONERROR(_Construct(Kernel, MmuSize, Mmu)); -+ -+ mirrorPageTable->mmus[mirrorPageTable->reference] = *Mmu; -+ -+ mirrorPageTable->hardwares[mirrorPageTable->reference] = Kernel->hardware; -+ -+ mirrorPageTable->reference++; -+ -+ gcmkFOOTER_ARG("mirrorPageTable->reference=%lu", mirrorPageTable->reference); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (mirrorPageTable && mirrorPageTable->reference == 0) -+ { -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, mirrorPageTable)); -+ } -+ -+ gcmkFOOTER(); -+ return status; -+#else -+ return _Construct(Kernel, MmuSize, Mmu); -+#endif -+} -+ -+gceSTATUS -+gckMMU_Destroy( -+ IN gckMMU Mmu -+ ) -+{ -+#if gcdSHARED_PAGETABLE -+ gckOS os = Mmu->os; -+ -+ sharedPageTable->reference--; -+ -+ if (sharedPageTable->reference == 0) -+ { -+ if (sharedPageTable->mmu) -+ { -+ gcmkVERIFY_OK(_Destroy(Mmu)); -+ } -+ -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, sharedPageTable)); -+ } -+ -+ return gcvSTATUS_OK; -+#elif gcdMIRROR_PAGETABLE -+ mirrorPageTable->reference--; -+ -+ if (mirrorPageTable->reference == 0) -+ { -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Mmu->os, mirrorPageTable)); -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Mmu->os, mirrorPageTableMutex)); -+ } -+ -+ return _Destroy(Mmu); -+#else -+ return _Destroy(Mmu); -+#endif -+} -+ -+/******************************************************************************* -+** -+** gckMMU_AllocatePages -+** -+** Allocate pages inside the page table. -+** -+** INPUT: -+** -+** gckMMU Mmu -+** Pointer to an gckMMU object. -+** -+** gctSIZE_T PageCount -+** Number of pages to allocate. -+** -+** OUTPUT: -+** -+** gctPOINTER * PageTable -+** Pointer to a variable that receives the base address of the page -+** table. -+** -+** gctUINT32 * Address -+** Pointer to a variable that receives the hardware specific address. -+*/ -+gceSTATUS -+_AllocatePages( -+ IN gckMMU Mmu, -+ IN gctSIZE_T PageCount, -+ IN gceSURF_TYPE Type, -+ OUT gctPOINTER * PageTable, -+ OUT gctUINT32 * Address -+ ) -+{ -+ gceSTATUS status; -+ gctBOOL mutex = gcvFALSE; -+ gctUINT32 index = 0, previous = ~0U, left; -+ gctUINT32_PTR map; -+ gctBOOL gotIt; -+ gctUINT32 address; -+ gctUINT32 pageCount; -+ -+ gcmkHEADER_ARG("Mmu=0x%x PageCount=%lu", Mmu, PageCount); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU); -+ gcmkVERIFY_ARGUMENT(PageCount > 0); -+ gcmkVERIFY_ARGUMENT(PageTable != gcvNULL); -+ -+ if (PageCount > Mmu->pageTableEntries) -+ { -+ /* Not enough pages avaiable. */ -+ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES); -+ } -+ -+ gcmkSAFECASTSIZET(pageCount, PageCount); -+ -+ /* Grab the mutex. */ -+ gcmkONERROR(gckOS_AcquireMutex(Mmu->os, Mmu->pageTableMutex, gcvINFINITE)); -+ mutex = gcvTRUE; -+ -+ /* Cast pointer to page table. */ -+ for (map = Mmu->mapLogical, gotIt = gcvFALSE; !gotIt;) -+ { -+ index = Mmu->heapList; -+ -+ if ((Mmu->hardware->mmuVersion == 0) && (Type == gcvSURF_VERTEX)) -+ { -+ gcmkONERROR(_AdjustIndex( -+ Mmu, -+ index, -+ pageCount, -+ gcdVERTEX_START / gcmSIZEOF(gctUINT32), -+ &index -+ )); -+ } -+ -+ /* Walk the heap list. */ -+ for (; !gotIt && (index < Mmu->pageTableEntries);) -+ { -+ /* Check the node type. */ -+ switch (gcmENTRY_TYPE(_ReadPageEntry(&map[index]))) -+ { -+ case gcvMMU_SINGLE: -+ /* Single odes are valid if we only need 1 page. */ -+ if (pageCount == 1) -+ { -+ gotIt = gcvTRUE; -+ } -+ else -+ { -+ /* Move to next node. */ -+ previous = index; -+ index = _ReadPageEntry(&map[index]) >> 8; -+ } -+ break; -+ -+ case gcvMMU_FREE: -+ /* Test if the node has enough space. */ -+ if (pageCount <= (_ReadPageEntry(&map[index]) >> 8)) -+ { -+ gotIt = gcvTRUE; -+ } -+ else -+ { -+ /* Move to next node. */ -+ previous = index; -+ index = _ReadPageEntry(&map[index + 1]); -+ } -+ break; -+ -+ default: -+ gcmkFATAL("MMU table correcupted at index %u!", index); -+ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES); -+ } -+ } -+ -+ /* Test if we are out of memory. */ -+ if (index >= Mmu->pageTableEntries) -+ { -+ if (Mmu->freeNodes) -+ { -+ /* Time to move out the trash! */ -+ gcmkONERROR(_Collect(Mmu)); -+ } -+ else -+ { -+ /* Out of resources. */ -+ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES); -+ } -+ } -+ } -+ -+ switch (gcmENTRY_TYPE(_ReadPageEntry(&map[index]))) -+ { -+ case gcvMMU_SINGLE: -+ /* Unlink single node from free list. */ -+ gcmkONERROR( -+ _Link(Mmu, previous, _ReadPageEntry(&map[index]) >> 8)); -+ break; -+ -+ case gcvMMU_FREE: -+ /* Check how many pages will be left. */ -+ left = (_ReadPageEntry(&map[index]) >> 8) - pageCount; -+ switch (left) -+ { -+ case 0: -+ /* The entire node is consumed, just unlink it. */ -+ gcmkONERROR( -+ _Link(Mmu, previous, _ReadPageEntry(&map[index + 1]))); -+ break; -+ -+ case 1: -+ /* One page will remain. Convert the node to a single node and -+ ** advance the index. */ -+ _WritePageEntry(&map[index], (_ReadPageEntry(&map[index + 1]) << 8) | gcvMMU_SINGLE); -+ index ++; -+ break; -+ -+ default: -+ /* Enough pages remain for a new node. However, we will just adjust -+ ** the size of the current node and advance the index. */ -+ _WritePageEntry(&map[index], (left << 8) | gcvMMU_FREE); -+ index += left; -+ break; -+ } -+ break; -+ } -+ -+ /* Mark node as used. */ -+ gcmkONERROR(_FillPageTable(&map[index], pageCount, gcvMMU_USED)); -+ -+ /* Return pointer to page table. */ -+ *PageTable = &Mmu->pageTableLogical[index]; -+ -+ /* Build virtual address. */ -+ if (Mmu->hardware->mmuVersion == 0) -+ { -+ gcmkONERROR( -+ gckHARDWARE_BuildVirtualAddress(Mmu->hardware, index, 0, &address)); -+ } -+ else -+ { -+ gctUINT32 masterOffset = index / gcdMMU_STLB_4K_ENTRY_NUM -+ + Mmu->dynamicMappingStart; -+ gctUINT32 slaveOffset = index % gcdMMU_STLB_4K_ENTRY_NUM; -+ -+ address = (masterOffset << gcdMMU_MTLB_SHIFT) -+ | (slaveOffset << gcdMMU_STLB_4K_SHIFT); -+ } -+ -+ if (Address != gcvNULL) -+ { -+ *Address = address; -+ } -+ -+ /* Release the mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex)); -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*PageTable=0x%x *Address=%08x", -+ *PageTable, gcmOPT_VALUE(Address)); -+ return gcvSTATUS_OK; -+ -+OnError: -+ -+ if (mutex) -+ { -+ /* Release the mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex)); -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckMMU_FreePages -+** -+** Free pages inside the page table. -+** -+** INPUT: -+** -+** gckMMU Mmu -+** Pointer to an gckMMU object. -+** -+** gctPOINTER PageTable -+** Base address of the page table to free. -+** -+** gctSIZE_T PageCount -+** Number of pages to free. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+_FreePages( -+ IN gckMMU Mmu, -+ IN gctPOINTER PageTable, -+ IN gctSIZE_T PageCount -+ ) -+{ -+ gctUINT32_PTR node; -+ gceSTATUS status; -+ gctBOOL acquired = gcvFALSE; -+ gctUINT32 pageCount; -+ -+ gcmkHEADER_ARG("Mmu=0x%x PageTable=0x%x PageCount=%lu", -+ Mmu, PageTable, PageCount); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU); -+ gcmkVERIFY_ARGUMENT(PageTable != gcvNULL); -+ gcmkVERIFY_ARGUMENT(PageCount > 0); -+ -+ gcmkSAFECASTSIZET(pageCount, PageCount); -+ -+ /* Get the node by index. */ -+ node = Mmu->mapLogical + ((gctUINT32_PTR)PageTable - Mmu->pageTableLogical); -+ -+ gcmkONERROR(gckOS_AcquireMutex(Mmu->os, Mmu->pageTableMutex, gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+#if gcdMMU_CLEAR_VALUE -+ if (Mmu->hardware->mmuVersion == 0) -+ { -+ _FillPageTable(PageTable, pageCount, gcdMMU_CLEAR_VALUE); -+ } -+#endif -+ -+ if (PageCount == 1) -+ { -+ /* Single page node. */ -+ _WritePageEntry(node, (~((1U<<8)-1)) | gcvMMU_SINGLE); -+#if gcdUSE_MMU_EXCEPTION -+ /* Enable exception */ -+ _WritePageEntry(PageTable, (1 << 1)); -+#endif -+ } -+ else -+ { -+ /* Mark the node as free. */ -+ _WritePageEntry(node, (pageCount << 8) | gcvMMU_FREE); -+ _WritePageEntry(node + 1, ~0U); -+ -+#if gcdUSE_MMU_EXCEPTION -+ /* Enable exception */ -+ gcmkVERIFY_OK(_FillPageTable(PageTable, pageCount, 1 << 1)); -+#endif -+ } -+ -+ /* We have free nodes. */ -+ Mmu->freeNodes = gcvTRUE; -+ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex)); -+ acquired = gcvFALSE; -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (acquired) -+ { -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex)); -+ } -+ -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckMMU_AllocatePages( -+ IN gckMMU Mmu, -+ IN gctSIZE_T PageCount, -+ OUT gctPOINTER * PageTable, -+ OUT gctUINT32 * Address -+ ) -+{ -+ return gckMMU_AllocatePagesEx( -+ Mmu, PageCount, gcvSURF_TYPE_UNKNOWN, PageTable, Address); -+} -+ -+gceSTATUS -+gckMMU_AllocatePagesEx( -+ IN gckMMU Mmu, -+ IN gctSIZE_T PageCount, -+ IN gceSURF_TYPE Type, -+ OUT gctPOINTER * PageTable, -+ OUT gctUINT32 * Address -+ ) -+{ -+#if gcdMIRROR_PAGETABLE -+ gceSTATUS status; -+ gctPOINTER pageTable; -+ gctUINT32 address; -+ gctINT i; -+ gckMMU mmu; -+ gctBOOL acquired = gcvFALSE; -+ gctBOOL allocated = gcvFALSE; -+ -+ gckOS_AcquireMutex(Mmu->os, mirrorPageTableMutex, gcvINFINITE); -+ acquired = gcvTRUE; -+ -+ /* Allocate page table for current MMU. */ -+ for (i = 0; i < (gctINT)mirrorPageTable->reference; i++) -+ { -+ if (Mmu == mirrorPageTable->mmus[i]) -+ { -+ gcmkONERROR(_AllocatePages(Mmu, PageCount, Type, PageTable, Address)); -+ allocated = gcvTRUE; -+ } -+ } -+ -+ /* Allocate page table for other MMUs. */ -+ for (i = 0; i < (gctINT)mirrorPageTable->reference; i++) -+ { -+ mmu = mirrorPageTable->mmus[i]; -+ -+ if (Mmu != mmu) -+ { -+ gcmkONERROR(_AllocatePages(mmu, PageCount, Type, &pageTable, &address)); -+ gcmkASSERT(address == *Address); -+ } -+ } -+ -+ gckOS_ReleaseMutex(Mmu->os, mirrorPageTableMutex); -+ acquired = gcvFALSE; -+ -+ return gcvSTATUS_OK; -+OnError: -+ -+ if (allocated) -+ { -+ /* Page tables for multiple GPU always keep the same. So it is impossible -+ * the fist one allocates successfully but others fail. -+ */ -+ gcmkASSERT(0); -+ } -+ -+ if (acquired) -+ { -+ gckOS_ReleaseMutex(Mmu->os, mirrorPageTableMutex); -+ } -+ -+ return status; -+#else -+ return _AllocatePages(Mmu, PageCount, Type, PageTable, Address); -+#endif -+} -+ -+gceSTATUS -+gckMMU_FreePages( -+ IN gckMMU Mmu, -+ IN gctPOINTER PageTable, -+ IN gctSIZE_T PageCount -+ ) -+{ -+#if gcdMIRROR_PAGETABLE -+ gctINT i; -+ gctUINT32 offset; -+ gckMMU mmu; -+ -+ gckOS_AcquireMutex(Mmu->os, mirrorPageTableMutex, gcvINFINITE); -+ -+ gcmkVERIFY_OK(_FreePages(Mmu, PageTable, PageCount)); -+ -+ offset = (gctUINT32)PageTable - (gctUINT32)Mmu->pageTableLogical; -+ -+ for (i = 0; i < (gctINT)mirrorPageTable->reference; i++) -+ { -+ mmu = mirrorPageTable->mmus[i]; -+ -+ if (mmu != Mmu) -+ { -+ gcmkVERIFY_OK(_FreePages(mmu, mmu->pageTableLogical + offset/4, PageCount)); -+ } -+ } -+ -+ gckOS_ReleaseMutex(Mmu->os, mirrorPageTableMutex); -+ -+ return gcvSTATUS_OK; -+#else -+ return _FreePages(Mmu, PageTable, PageCount); -+#endif -+} -+ -+gceSTATUS -+gckMMU_SetPage( -+ IN gckMMU Mmu, -+ IN gctUINT32 PageAddress, -+ IN gctUINT32 *PageEntry -+ ) -+{ -+#if gcdMIRROR_PAGETABLE -+ gctUINT32_PTR pageEntry; -+ gctINT i; -+ gckMMU mmu; -+ gctUINT32 offset = (gctUINT32)PageEntry - (gctUINT32)Mmu->pageTableLogical; -+#endif -+ -+ gcmkHEADER_ARG("Mmu=0x%x", Mmu); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU); -+ gcmkVERIFY_ARGUMENT(PageEntry != gcvNULL); -+ gcmkVERIFY_ARGUMENT(!(PageAddress & 0xFFF)); -+ -+ if (Mmu->hardware->mmuVersion == 0) -+ { -+ _WritePageEntry(PageEntry, PageAddress); -+ } -+ else -+ { -+ _WritePageEntry(PageEntry, _SetPage(PageAddress)); -+ } -+ -+#if gcdMIRROR_PAGETABLE -+ for (i = 0; i < (gctINT)mirrorPageTable->reference; i++) -+ { -+ mmu = mirrorPageTable->mmus[i]; -+ -+ if (mmu != Mmu) -+ { -+ pageEntry = mmu->pageTableLogical + offset / 4; -+ -+ if (mmu->hardware->mmuVersion == 0) -+ { -+ _WritePageEntry(pageEntry, PageAddress); -+ } -+ else -+ { -+ _WritePageEntry(pageEntry, _SetPage(PageAddress)); -+ } -+ } -+ -+ } -+#endif -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+#if gcdPROCESS_ADDRESS_SPACE -+gceSTATUS -+gckMMU_GetPageEntry( -+ IN gckMMU Mmu, -+ IN gctUINT32 Address, -+ IN gctUINT32_PTR *PageTable -+ ) -+{ -+ gceSTATUS status; -+ struct _gcsMMU_STLB *stlb; -+ struct _gcsMMU_STLB **stlbs = Mmu->stlbs; -+ gctUINT32 offset = _MtlbOffset(Address); -+ gctUINT32 mtlbEntry; -+ gctBOOL ace = gckHARDWARE_IsFeatureAvailable(Mmu->hardware, gcvFEATURE_ACE); -+ -+ gcmkHEADER_ARG("Mmu=0x%x", Mmu); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU); -+ gcmkVERIFY_ARGUMENT((Address & 0xFFF) == 0); -+ -+ stlb = stlbs[offset]; -+ -+ if (stlb == gcvNULL) -+ { -+ gcmkONERROR(_AllocateStlb(Mmu->os, &stlb)); -+ -+ mtlbEntry = stlb->physBase -+ | gcdMMU_MTLB_4K_PAGE -+ | gcdMMU_MTLB_PRESENT -+ ; -+ -+ if (ace) -+ { -+ mtlbEntry = mtlbEntry -+ /* Secure */ -+ | (1 << 4); -+ } -+ -+ /* Insert Slave TLB address to Master TLB entry.*/ -+ _WritePageEntry(Mmu->mtlbLogical + offset, mtlbEntry); -+ -+ /* Record stlb. */ -+ stlbs[offset] = stlb; -+ } -+ -+ *PageTable = &stlb->logical[_StlbOffset(Address)]; -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+_CheckMap( -+ IN gckMMU Mmu -+ ) -+{ -+ gceSTATUS status; -+ gctUINT32_PTR map = Mmu->mapLogical; -+ gctUINT32 index; -+ -+ for (index = Mmu->heapList; index < Mmu->pageTableEntries;) -+ { -+ /* Check the node type. */ -+ switch (gcmENTRY_TYPE(_ReadPageEntry(&map[index]))) -+ { -+ case gcvMMU_SINGLE: -+ /* Move to next node. */ -+ index = _ReadPageEntry(&map[index]) >> 8; -+ break; -+ -+ case gcvMMU_FREE: -+ /* Move to next node. */ -+ index = _ReadPageEntry(&map[index + 1]); -+ break; -+ -+ default: -+ gcmkFATAL("MMU table correcupted at index [%u] = %x!", index, map[index]); -+ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES); -+ } -+ } -+ -+ return gcvSTATUS_OK; -+ -+OnError: -+ return status; -+} -+ -+gceSTATUS -+gckMMU_FlatMapping( -+ IN gckMMU Mmu, -+ IN gctUINT32 Physical -+ ) -+{ -+ gceSTATUS status; -+ gctUINT32 index = _AddressToIndex(Mmu, Physical); -+ gctUINT32 i; -+ gctBOOL gotIt = gcvFALSE; -+ gctUINT32_PTR map = Mmu->mapLogical; -+ gctUINT32 previous = ~0U; -+ gctUINT32_PTR pageTable; -+ -+ gckMMU_GetPageEntry(Mmu, Physical, &pageTable); -+ -+ _WritePageEntry(pageTable, _SetPage(Physical)); -+ -+ if (map) -+ { -+ /* Find node which contains index. */ -+ for (i = 0; !gotIt && (i < Mmu->pageTableEntries);) -+ { -+ gctUINT32 numPages; -+ -+ switch (gcmENTRY_TYPE(_ReadPageEntry(&map[i]))) -+ { -+ case gcvMMU_SINGLE: -+ if (i == index) -+ { -+ gotIt = gcvTRUE; -+ } -+ else -+ { -+ previous = i; -+ i = _ReadPageEntry(&map[i]) >> 8; -+ } -+ break; -+ -+ case gcvMMU_FREE: -+ numPages = _ReadPageEntry(&map[i]) >> 8; -+ if (index >= i && index < i + numPages) -+ { -+ gotIt = gcvTRUE; -+ } -+ else -+ { -+ previous = i; -+ i = _ReadPageEntry(&map[i + 1]); -+ } -+ break; -+ -+ default: -+ gcmkFATAL("MMU table correcupted at index %u!", index); -+ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES); -+ } -+ } -+ -+ switch (gcmENTRY_TYPE(_ReadPageEntry(&map[i]))) -+ { -+ case gcvMMU_SINGLE: -+ /* Unlink single node from free list. */ -+ gcmkONERROR( -+ _Link(Mmu, previous, _ReadPageEntry(&map[i]) >> 8)); -+ break; -+ -+ case gcvMMU_FREE: -+ /* Split the node. */ -+ { -+ gctUINT32 start; -+ gctUINT32 next = _ReadPageEntry(&map[i+1]); -+ gctUINT32 total = _ReadPageEntry(&map[i]) >> 8; -+ gctUINT32 countLeft = index - i; -+ gctUINT32 countRight = total - countLeft - 1; -+ -+ if (countLeft) -+ { -+ start = i; -+ _AddFree(Mmu, previous, start, countLeft); -+ previous = start; -+ } -+ -+ if (countRight) -+ { -+ start = index + 1; -+ _AddFree(Mmu, previous, start, countRight); -+ previous = start; -+ } -+ -+ _Link(Mmu, previous, next); -+ } -+ break; -+ } -+ } -+ -+ return gcvSTATUS_OK; -+ -+OnError: -+ -+ /* Roll back. */ -+ return status; -+} -+ -+ -+ -+gceSTATUS -+gckMMU_FreePagesEx( -+ IN gckMMU Mmu, -+ IN gctUINT32 Address, -+ IN gctSIZE_T PageCount -+ ) -+{ -+ gctUINT32_PTR node; -+ gceSTATUS status; -+ -+#if gcdUSE_MMU_EXCEPTION -+ gctUINT32 i; -+ struct _gcsMMU_STLB *stlb; -+ struct _gcsMMU_STLB **stlbs = Mmu->stlbs; -+#endif -+ -+ gcmkHEADER_ARG("Mmu=0x%x Address=0x%x PageCount=%lu", -+ Mmu, Address, PageCount); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU); -+ gcmkVERIFY_ARGUMENT(PageCount > 0); -+ -+ /* Get the node by index. */ -+ node = Mmu->mapLogical + _AddressToIndex(Mmu, Address); -+ -+ gcmkONERROR(gckOS_AcquireMutex(Mmu->os, Mmu->pageTableMutex, gcvINFINITE)); -+ -+ if (PageCount == 1) -+ { -+ /* Single page node. */ -+ _WritePageEntry(node, (~((1U<<8)-1)) | gcvMMU_SINGLE); -+ } -+ else -+ { -+ /* Mark the node as free. */ -+ _WritePageEntry(node, (PageCount << 8) | gcvMMU_FREE); -+ _WritePageEntry(node + 1, ~0U); -+ } -+ -+ /* We have free nodes. */ -+ Mmu->freeNodes = gcvTRUE; -+ -+#if gcdUSE_MMU_EXCEPTION -+ for (i = 0; i < PageCount; i++) -+ { -+ /* Get */ -+ stlb = stlbs[_MtlbOffset(Address)]; -+ -+ /* Enable exception */ -+ stlb->logical[_StlbOffset(Address)] = gcdMMU_STLB_EXCEPTION; -+ } -+#endif -+ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->pageTableMutex)); -+ -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ gcmkFOOTER(); -+ return status; -+} -+#endif -+ -+gceSTATUS -+gckMMU_Flush( -+ IN gckMMU Mmu, -+ IN gceSURF_TYPE Type -+ ) -+{ -+ gckHARDWARE hardware; -+ gctUINT32 mask; -+ gctINT i; -+ -+ if (Type == gcvSURF_VERTEX || Type == gcvSURF_INDEX) -+ { -+ mask = gcvPAGE_TABLE_DIRTY_BIT_FE; -+ } -+ else -+ { -+ mask = gcvPAGE_TABLE_DIRTY_BIT_OTHER; -+ } -+ -+#if gcdPROCESS_ADDRESS_SPACE -+ for (i = 0; i < gcdMAX_GPU_COUNT; i++) -+ { -+ gcmkVERIFY_OK( -+ gckOS_AtomSetMask(Mmu->pageTableDirty[i], mask)); -+ } -+#else -+#if gcdSHARED_PAGETABLE -+ for (i = 0; i < gcdMAX_GPU_COUNT; i++) -+ { -+ hardware = sharedPageTable->hardwares[i]; -+ if (hardware) -+ { -+ gcmkVERIFY_OK(gckOS_AtomSetMask(hardware->pageTableDirty, mask)); -+ } -+ } -+#elif gcdMIRROR_PAGETABLE -+ for (i = 0; i < (gctINT)mirrorPageTable->reference; i++) -+ { -+ hardware = mirrorPageTable->hardwares[i]; -+ -+ /* Notify cores who use this page table. */ -+ gcmkVERIFY_OK( -+ gckOS_AtomSetMask(hardware->pageTableDirty, mask)); -+ } -+#else -+ hardware = Mmu->hardware; -+ gcmkVERIFY_OK( -+ gckOS_AtomSetMask(hardware->pageTableDirty, mask)); -+#endif -+#endif -+ -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckMMU_DumpPageTableEntry( -+ IN gckMMU Mmu, -+ IN gctUINT32 Address -+ ) -+{ -+#if gcdPROCESS_ADDRESS_SPACE -+ gcsMMU_STLB_PTR *stlbs = Mmu->stlbs; -+ gcsMMU_STLB_PTR stlbDesc = stlbs[_MtlbOffset(Address)]; -+#else -+ gctUINT32_PTR pageTable; -+ gctUINT32 index; -+ gctUINT32 mtlb, stlb; -+#endif -+ -+ gcmkHEADER_ARG("Mmu=0x%08X Address=0x%08X", Mmu, Address); -+ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU); -+ -+ gcmkASSERT(Mmu->hardware->mmuVersion > 0); -+ -+#if gcdPROCESS_ADDRESS_SPACE -+ if (stlbDesc) -+ { -+ gcmkPRINT(" STLB entry = 0x%08X", -+ _ReadPageEntry(&stlbDesc->logical[_StlbOffset(Address)])); -+ } -+ else -+ { -+ gcmkPRINT(" MTLB entry is empty."); -+ } -+#else -+ mtlb = (Address & gcdMMU_MTLB_MASK) >> gcdMMU_MTLB_SHIFT; -+ -+ if (mtlb >= Mmu->dynamicMappingStart) -+ { -+ stlb = (Address & gcdMMU_STLB_4K_MASK) >> gcdMMU_STLB_4K_SHIFT; -+ -+ pageTable = Mmu->pageTableLogical; -+ -+ index = (mtlb - Mmu->dynamicMappingStart) -+ * gcdMMU_STLB_4K_ENTRY_NUM -+ + stlb; -+ -+ gcmkPRINT(" Page table entry = 0x%08X", _ReadPageEntry(pageTable + index)); -+ } -+ else -+ { -+ gcsMMU_STLB_PTR stlbObj = Mmu->staticSTLB; -+ gctUINT32 entry = Mmu->mtlbLogical[mtlb]; -+ -+ stlb = (Address & gcdMMU_STLB_64K_MASK) >> gcdMMU_STLB_64K_SHIFT; -+ -+ entry &= 0xFFFFFFF0; -+ -+ while (stlbObj) -+ { -+ -+ if (entry == stlbObj->physBase) -+ { -+ gcmkPRINT(" Page table entry = 0x%08X", stlbObj->logical[stlb]); -+ break; -+ } -+ -+ stlbObj = stlbObj->next; -+ } -+ } -+#endif -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/****************************************************************************** -+****************************** T E S T C O D E ****************************** -+******************************************************************************/ -+ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_mmu_vg.c linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_mmu_vg.c ---- linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_mmu_vg.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_mmu_vg.c 2015-11-30 17:56:13.580137725 +0100 -@@ -0,0 +1,522 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#include "gc_hal_kernel_precomp.h" -+ -+#if gcdENABLE_VG -+ -+#define _GC_OBJ_ZONE gcvZONE_MMU -+ -+/******************************************************************************* -+** -+** gckVGMMU_Construct -+** -+** Construct a new gckVGMMU object. -+** -+** INPUT: -+** -+** gckVGKERNEL Kernel -+** Pointer to an gckVGKERNEL object. -+** -+** gctSIZE_T MmuSize -+** Number of bytes for the page table. -+** -+** OUTPUT: -+** -+** gckVGMMU * Mmu -+** Pointer to a variable that receives the gckVGMMU object pointer. -+*/ -+gceSTATUS gckVGMMU_Construct( -+ IN gckVGKERNEL Kernel, -+ IN gctUINT32 MmuSize, -+ OUT gckVGMMU * Mmu -+ ) -+{ -+ gckOS os; -+ gckVGHARDWARE hardware; -+ gceSTATUS status; -+ gckVGMMU mmu; -+ gctUINT32 * pageTable; -+ gctUINT32 i; -+ -+ gcmkHEADER_ARG("Kernel=0x%x MmuSize=0x%x Mmu=0x%x", Kernel, MmuSize, Mmu); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ gcmkVERIFY_ARGUMENT(MmuSize > 0); -+ gcmkVERIFY_ARGUMENT(Mmu != gcvNULL); -+ -+ /* Extract the gckOS object pointer. */ -+ os = Kernel->os; -+ gcmkVERIFY_OBJECT(os, gcvOBJ_OS); -+ -+ /* Extract the gckVGHARDWARE object pointer. */ -+ hardware = Kernel->hardware; -+ gcmkVERIFY_OBJECT(hardware, gcvOBJ_HARDWARE); -+ -+ /* Allocate memory for the gckVGMMU object. */ -+ status = gckOS_Allocate(os, sizeof(struct _gckVGMMU), (gctPOINTER *) &mmu); -+ -+ if (status < 0) -+ { -+ /* Error. */ -+ gcmkFATAL( -+ "%s(%d): could not allocate gckVGMMU object.", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ gcmkFOOTER(); -+ return status; -+ } -+ -+ /* Initialize the gckVGMMU object. */ -+ mmu->object.type = gcvOBJ_MMU; -+ mmu->os = os; -+ mmu->hardware = hardware; -+ -+ /* Create the mutex. */ -+ status = gckOS_CreateMutex(os, &mmu->mutex); -+ -+ if (status < 0) -+ { -+ /* Roll back. */ -+ mmu->object.type = gcvOBJ_UNKNOWN; -+ gcmkVERIFY_OK(gckOS_Free(os, mmu)); -+ -+ gcmkFOOTER(); -+ /* Error. */ -+ return status; -+ } -+ -+ /* Allocate the page table. */ -+ mmu->pageTableSize = (gctUINT32)MmuSize; -+ status = gckOS_AllocateContiguous(os, -+ gcvFALSE, -+ &mmu->pageTableSize, -+ &mmu->pageTablePhysical, -+ &mmu->pageTableLogical); -+ -+ if (status < 0) -+ { -+ /* Roll back. */ -+ gcmkVERIFY_OK(gckOS_DeleteMutex(os, mmu->mutex)); -+ -+ mmu->object.type = gcvOBJ_UNKNOWN; -+ gcmkVERIFY_OK(gckOS_Free(os, mmu)); -+ -+ /* Error. */ -+ gcmkFATAL( -+ "%s(%d): could not allocate page table.", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ gcmkFOOTER(); -+ return status; -+ } -+ -+ /* Compute number of entries in page table. */ -+ mmu->entryCount = (gctUINT32)mmu->pageTableSize / sizeof(gctUINT32); -+ mmu->entry = 0; -+ -+ /* Mark the entire page table as available. */ -+ pageTable = (gctUINT32 *) mmu->pageTableLogical; -+ for (i = 0; i < mmu->entryCount; i++) -+ { -+ pageTable[i] = (gctUINT32)~0; -+ } -+ -+ /* Set page table address. */ -+ status = gckVGHARDWARE_SetMMU(hardware, mmu->pageTableLogical); -+ -+ if (status < 0) -+ { -+ /* Free the page table. */ -+ gcmkVERIFY_OK(gckOS_FreeContiguous(mmu->os, -+ mmu->pageTablePhysical, -+ mmu->pageTableLogical, -+ mmu->pageTableSize)); -+ -+ /* Roll back. */ -+ gcmkVERIFY_OK(gckOS_DeleteMutex(os, mmu->mutex)); -+ -+ mmu->object.type = gcvOBJ_UNKNOWN; -+ gcmkVERIFY_OK(gckOS_Free(os, mmu)); -+ -+ /* Error. */ -+ gcmkFATAL( -+ "%s(%d): could not program page table.", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ gcmkFOOTER(); -+ return status; -+ } -+ -+ /* Return the gckVGMMU object pointer. */ -+ *Mmu = mmu; -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, gcvZONE_MMU, -+ "%s(%d): %u entries at %p.(0x%08X)\n", -+ __FUNCTION__, __LINE__, -+ mmu->entryCount, -+ mmu->pageTableLogical, -+ mmu->pageTablePhysical -+ ); -+ -+ gcmkFOOTER_NO(); -+ /* Success. */ -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckVGMMU_Destroy -+** -+** Destroy a nAQMMU object. -+** -+** INPUT: -+** -+** gckVGMMU Mmu -+** Pointer to an gckVGMMU object. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS gckVGMMU_Destroy( -+ IN gckVGMMU Mmu -+ ) -+{ -+ gcmkHEADER_ARG("Mmu=0x%x", Mmu); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU); -+ -+ /* Free the page table. */ -+ gcmkVERIFY_OK(gckOS_FreeContiguous(Mmu->os, -+ Mmu->pageTablePhysical, -+ Mmu->pageTableLogical, -+ Mmu->pageTableSize)); -+ -+ /* Roll back. */ -+ gcmkVERIFY_OK(gckOS_DeleteMutex(Mmu->os, Mmu->mutex)); -+ -+ /* Mark the gckVGMMU object as unknown. */ -+ Mmu->object.type = gcvOBJ_UNKNOWN; -+ -+ /* Free the gckVGMMU object. */ -+ gcmkVERIFY_OK(gckOS_Free(Mmu->os, Mmu)); -+ -+ gcmkFOOTER_NO(); -+ /* Success. */ -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckVGMMU_AllocatePages -+** -+** Allocate pages inside the page table. -+** -+** INPUT: -+** -+** gckVGMMU Mmu -+** Pointer to an gckVGMMU object. -+** -+** gctSIZE_T PageCount -+** Number of pages to allocate. -+** -+** OUTPUT: -+** -+** gctPOINTER * PageTable -+** Pointer to a variable that receives the base address of the page -+** table. -+** -+** gctUINT32 * Address -+** Pointer to a variable that receives the hardware specific address. -+*/ -+gceSTATUS gckVGMMU_AllocatePages( -+ IN gckVGMMU Mmu, -+ IN gctSIZE_T PageCount, -+ OUT gctPOINTER * PageTable, -+ OUT gctUINT32 * Address -+ ) -+{ -+ gceSTATUS status; -+ gctUINT32 tail, index, i; -+ gctUINT32 * table; -+ gctBOOL allocated = gcvFALSE; -+ -+ gcmkHEADER_ARG("Mmu=0x%x PageCount=0x%x PageTable=0x%x Address=0x%x", -+ Mmu, PageCount, PageTable, Address); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU); -+ gcmkVERIFY_ARGUMENT(PageCount > 0); -+ gcmkVERIFY_ARGUMENT(PageTable != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Address != gcvNULL); -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, gcvZONE_MMU, -+ "%s(%d): %u pages.\n", -+ __FUNCTION__, __LINE__, -+ PageCount -+ ); -+ -+ if (PageCount > Mmu->entryCount) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_MMU, -+ "%s(%d): page table too small for %u pages.\n", -+ __FUNCTION__, __LINE__, -+ PageCount -+ ); -+ -+ gcmkFOOTER_NO(); -+ /* Not enough pages avaiable. */ -+ return gcvSTATUS_OUT_OF_RESOURCES; -+ } -+ -+ /* Grab the mutex. */ -+ status = gckOS_AcquireMutex(Mmu->os, Mmu->mutex, gcvINFINITE); -+ -+ if (status < 0) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_MMU, -+ "%s(%d): could not acquire mutex.\n" -+ ,__FUNCTION__, __LINE__ -+ ); -+ -+ gcmkFOOTER(); -+ /* Error. */ -+ return status; -+ } -+ -+ /* Compute the tail for this allocation. */ -+ tail = Mmu->entryCount - (gctUINT32)PageCount; -+ -+ /* Walk all entries until we find enough slots. */ -+ for (index = Mmu->entry; index <= tail;) -+ { -+ /* Access page table. */ -+ table = (gctUINT32 *) Mmu->pageTableLogical + index; -+ -+ /* See if all slots are available. */ -+ for (i = 0; i < PageCount; i++, table++) -+ { -+ if (*table != ~0) -+ { -+ /* Start from next slot. */ -+ index += i + 1; -+ break; -+ } -+ } -+ -+ if (i == PageCount) -+ { -+ /* Bail out if we have enough page entries. */ -+ allocated = gcvTRUE; -+ break; -+ } -+ } -+ -+ if (!allocated) -+ { -+ if (status >= 0) -+ { -+ /* Walk all entries until we find enough slots. */ -+ for (index = 0; index <= tail;) -+ { -+ /* Access page table. */ -+ table = (gctUINT32 *) Mmu->pageTableLogical + index; -+ -+ /* See if all slots are available. */ -+ for (i = 0; i < PageCount; i++, table++) -+ { -+ if (*table != ~0) -+ { -+ /* Start from next slot. */ -+ index += i + 1; -+ break; -+ } -+ } -+ -+ if (i == PageCount) -+ { -+ /* Bail out if we have enough page entries. */ -+ allocated = gcvTRUE; -+ break; -+ } -+ } -+ } -+ } -+ -+ if (!allocated && (status >= 0)) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_MMU, -+ "%s(%d): not enough free pages for %u pages.\n", -+ __FUNCTION__, __LINE__, -+ PageCount -+ ); -+ -+ /* Not enough empty slots available. */ -+ status = gcvSTATUS_OUT_OF_RESOURCES; -+ } -+ -+ if (status >= 0) -+ { -+ /* Build virtual address. */ -+ status = gckVGHARDWARE_BuildVirtualAddress(Mmu->hardware, -+ index, -+ 0, -+ Address); -+ -+ if (status >= 0) -+ { -+ /* Update current entry into page table. */ -+ Mmu->entry = index + (gctUINT32)PageCount; -+ -+ /* Return pointer to page table. */ -+ *PageTable = (gctUINT32 *) Mmu->pageTableLogical + index; -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, gcvZONE_MMU, -+ "%s(%d): allocated %u pages at index %u (0x%08X) @ %p.\n", -+ __FUNCTION__, __LINE__, -+ PageCount, -+ index, -+ *Address, -+ *PageTable -+ ); -+ } -+ } -+ -+ /* Release the mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Mmu->os, Mmu->mutex)); -+ gcmkFOOTER(); -+ -+ /* Return status. */ -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckVGMMU_FreePages -+** -+** Free pages inside the page table. -+** -+** INPUT: -+** -+** gckVGMMU Mmu -+** Pointer to an gckVGMMU object. -+** -+** gctPOINTER PageTable -+** Base address of the page table to free. -+** -+** gctSIZE_T PageCount -+** Number of pages to free. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS gckVGMMU_FreePages( -+ IN gckVGMMU Mmu, -+ IN gctPOINTER PageTable, -+ IN gctSIZE_T PageCount -+ ) -+{ -+ gctUINT32 * table; -+ -+ gcmkHEADER_ARG("Mmu=0x%x PageTable=0x%x PageCount=0x%x", -+ Mmu, PageTable, PageCount); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU); -+ gcmkVERIFY_ARGUMENT(PageTable != gcvNULL); -+ gcmkVERIFY_ARGUMENT(PageCount > 0); -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, gcvZONE_MMU, -+ "%s(%d): freeing %u pages at index %u @ %p.\n", -+ __FUNCTION__, __LINE__, -+ PageCount, -+ ((gctUINT32 *) PageTable - (gctUINT32 *) Mmu->pageTableLogical), -+ PageTable -+ ); -+ -+ /* Convert pointer. */ -+ table = (gctUINT32 *) PageTable; -+ -+ /* Mark the page table entries as available. */ -+ while (PageCount-- > 0) -+ { -+ *table++ = (gctUINT32)~0; -+ } -+ -+ gcmkFOOTER_NO(); -+ /* Success. */ -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckVGMMU_SetPage( -+ IN gckVGMMU Mmu, -+ IN gctUINT32 PageAddress, -+ IN gctUINT32 *PageEntry -+ ) -+{ -+ gcmkHEADER_ARG("Mmu=0x%x", Mmu); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Mmu, gcvOBJ_MMU); -+ gcmkVERIFY_ARGUMENT(PageEntry != gcvNULL); -+ gcmkVERIFY_ARGUMENT(!(PageAddress & 0xFFF)); -+ -+ *PageEntry = PageAddress; -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckVGMMU_Flush( -+ IN gckVGMMU Mmu -+ ) -+{ -+ gckVGHARDWARE hardware; -+ -+ gcmkHEADER_ARG("Mmu=0x%x", Mmu); -+ -+ hardware = Mmu->hardware; -+ gcmkVERIFY_OK( -+ gckOS_AtomSet(hardware->os, hardware->pageTableDirty, 1)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+#endif /* gcdENABLE_VG */ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_os.c linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_os.c ---- linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_os.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_os.c 2015-11-30 17:56:13.580137725 +0100 -@@ -0,0 +1,8062 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#include "gc_hal_kernel_linux.h" -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+ -+#if gcdANDROID_NATIVE_FENCE_SYNC -+#include -+#include "gc_hal_kernel_sync.h" -+#endif -+ -+#define _GC_OBJ_ZONE gcvZONE_OS -+ -+#include "gc_hal_kernel_allocator.h" -+ -+#define MEMORY_LOCK(os) \ -+ gcmkVERIFY_OK(gckOS_AcquireMutex( \ -+ (os), \ -+ (os)->memoryLock, \ -+ gcvINFINITE)) -+ -+#define MEMORY_UNLOCK(os) \ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex((os), (os)->memoryLock)) -+ -+#define MEMORY_MAP_LOCK(os) \ -+ gcmkVERIFY_OK(gckOS_AcquireMutex( \ -+ (os), \ -+ (os)->memoryMapLock, \ -+ gcvINFINITE)) -+ -+#define MEMORY_MAP_UNLOCK(os) \ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex((os), (os)->memoryMapLock)) -+ -+ -+/* Create a new mutex. */ -+static gceSTATUS -+gckOS_CreateNamedMutex( -+ IN gckOS Os, -+ IN struct lock_class_key *key, -+ IN const char *name, -+ OUT gctPOINTER * Mutex -+ ); -+ -+static struct lock_class_key gckOS_key; -+static struct lock_class_key gckOS_MM_key; -+static struct lock_class_key gckOS_Signal_key; -+#if gcdANDROID_NATIVE_FENCE_SYNC -+static struct lock_class_key gckOS_SyncPoint_key; -+#endif -+ -+/******************************************************************************\ -+******************************* Private Functions ****************************** -+\******************************************************************************/ -+static gctINT -+_GetThreadID( -+ void -+ ) -+{ -+ return task_pid_vnr(current); -+} -+ -+static PLINUX_MDL -+_CreateMdl( -+ void -+ ) -+{ -+ PLINUX_MDL mdl; -+ -+ gcmkHEADER(); -+ -+ mdl = (PLINUX_MDL)kzalloc(sizeof(struct _LINUX_MDL), GFP_KERNEL | gcdNOWARN); -+ -+ gcmkFOOTER_ARG("0x%X", mdl); -+ return mdl; -+} -+ -+static gceSTATUS -+_DestroyMdlMap( -+ IN PLINUX_MDL Mdl, -+ IN PLINUX_MDL_MAP MdlMap -+ ); -+ -+static gceSTATUS -+_DestroyMdl( -+ IN PLINUX_MDL Mdl -+ ) -+{ -+ PLINUX_MDL_MAP mdlMap, next; -+ -+ gcmkHEADER_ARG("Mdl=0x%X", Mdl); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_ARGUMENT(Mdl != gcvNULL); -+ -+ mdlMap = Mdl->maps; -+ -+ while (mdlMap != gcvNULL) -+ { -+ next = mdlMap->next; -+ -+ gcmkVERIFY_OK(_DestroyMdlMap(Mdl, mdlMap)); -+ -+ mdlMap = next; -+ } -+ -+ kfree(Mdl); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+static PLINUX_MDL_MAP -+_CreateMdlMap( -+ IN PLINUX_MDL Mdl, -+ IN gctINT ProcessID -+ ) -+{ -+ PLINUX_MDL_MAP mdlMap; -+ -+ gcmkHEADER_ARG("Mdl=0x%X ProcessID=%d", Mdl, ProcessID); -+ -+ mdlMap = (PLINUX_MDL_MAP)kmalloc(sizeof(struct _LINUX_MDL_MAP), GFP_KERNEL | gcdNOWARN); -+ if (mdlMap == gcvNULL) -+ { -+ gcmkFOOTER_NO(); -+ return gcvNULL; -+ } -+ -+ mdlMap->pid = ProcessID; -+ mdlMap->vmaAddr = gcvNULL; -+ mdlMap->vma = gcvNULL; -+ mdlMap->count = 0; -+ -+ mdlMap->next = Mdl->maps; -+ Mdl->maps = mdlMap; -+ -+ gcmkFOOTER_ARG("0x%X", mdlMap); -+ return mdlMap; -+} -+ -+static gceSTATUS -+_DestroyMdlMap( -+ IN PLINUX_MDL Mdl, -+ IN PLINUX_MDL_MAP MdlMap -+ ) -+{ -+ PLINUX_MDL_MAP prevMdlMap; -+ -+ gcmkHEADER_ARG("Mdl=0x%X MdlMap=0x%X", Mdl, MdlMap); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_ARGUMENT(MdlMap != gcvNULL); -+ gcmkASSERT(Mdl->maps != gcvNULL); -+ -+ if (Mdl->maps == MdlMap) -+ { -+ Mdl->maps = MdlMap->next; -+ } -+ else -+ { -+ prevMdlMap = Mdl->maps; -+ -+ while (prevMdlMap->next != MdlMap) -+ { -+ prevMdlMap = prevMdlMap->next; -+ -+ gcmkASSERT(prevMdlMap != gcvNULL); -+ } -+ -+ prevMdlMap->next = MdlMap->next; -+ } -+ -+ kfree(MdlMap); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+extern PLINUX_MDL_MAP -+FindMdlMap( -+ IN PLINUX_MDL Mdl, -+ IN gctINT ProcessID -+ ) -+{ -+ PLINUX_MDL_MAP mdlMap; -+ -+ gcmkHEADER_ARG("Mdl=0x%X ProcessID=%d", Mdl, ProcessID); -+ if(Mdl == gcvNULL) -+ { -+ gcmkFOOTER_NO(); -+ return gcvNULL; -+ } -+ mdlMap = Mdl->maps; -+ -+ while (mdlMap != gcvNULL) -+ { -+ if (mdlMap->pid == ProcessID) -+ { -+ gcmkFOOTER_ARG("0x%X", mdlMap); -+ return mdlMap; -+ } -+ -+ mdlMap = mdlMap->next; -+ } -+ -+ gcmkFOOTER_NO(); -+ return gcvNULL; -+} -+ -+/******************************************************************************* -+** Integer Id Management. -+*/ -+gceSTATUS -+_AllocateIntegerId( -+ IN gcsINTEGER_DB_PTR Database, -+ IN gctPOINTER KernelPointer, -+ OUT gctUINT32 *Id -+ ) -+{ -+ int result; -+ gctINT next; -+ -+ idr_preload(GFP_KERNEL | gcdNOWARN); -+ -+ spin_lock(&Database->lock); -+ -+ next = (Database->curr + 1 <= 0) ? 1 : Database->curr + 1; -+ -+ result = idr_alloc(&Database->idr, KernelPointer, next, 0, GFP_ATOMIC); -+ -+ /* ID allocated should not be 0. */ -+ gcmkASSERT(result != 0); -+ -+ if (result > 0) -+ { -+ Database->curr = *Id = result; -+ } -+ -+ spin_unlock(&Database->lock); -+ -+ idr_preload_end(); -+ -+ if (result < 0) -+ { -+ return gcvSTATUS_OUT_OF_RESOURCES; -+ } -+ -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+_QueryIntegerId( -+ IN gcsINTEGER_DB_PTR Database, -+ IN gctUINT32 Id, -+ OUT gctPOINTER * KernelPointer -+ ) -+{ -+ gctPOINTER pointer; -+ -+ spin_lock(&Database->lock); -+ -+ pointer = idr_find(&Database->idr, Id); -+ -+ spin_unlock(&Database->lock); -+ -+ if(pointer) -+ { -+ *KernelPointer = pointer; -+ return gcvSTATUS_OK; -+ } -+ else -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_OS, -+ "%s(%d) Id = %d is not found", -+ __FUNCTION__, __LINE__, Id); -+ -+ return gcvSTATUS_NOT_FOUND; -+ } -+} -+ -+gceSTATUS -+_DestroyIntegerId( -+ IN gcsINTEGER_DB_PTR Database, -+ IN gctUINT32 Id -+ ) -+{ -+ spin_lock(&Database->lock); -+ -+ idr_remove(&Database->idr, Id); -+ -+ spin_unlock(&Database->lock); -+ -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+_QueryProcessPageTable( -+ IN gctPOINTER Logical, -+ OUT gctUINT32 * Address -+ ) -+{ -+ gctUINTPTR_T logical = (gctUINTPTR_T)Logical; -+ pgd_t *pgd; -+ pud_t *pud; -+ pmd_t *pmd; -+ pte_t *pte; -+ -+ if (!current->mm) -+ { -+ return gcvSTATUS_NOT_FOUND; -+ } -+ -+ pgd = pgd_offset(current->mm, logical); -+ if (pgd_none(*pgd) || pgd_bad(*pgd)) -+ { -+ return gcvSTATUS_NOT_FOUND; -+ } -+ -+ pud = pud_offset(pgd, logical); -+ if (pud_none(*pud) || pud_bad(*pud)) -+ { -+ return gcvSTATUS_NOT_FOUND; -+ } -+ -+ pmd = pmd_offset(pud, logical); -+ if (pmd_none(*pmd) || pmd_bad(*pmd)) -+ { -+ return gcvSTATUS_NOT_FOUND; -+ } -+ -+ pte = pte_offset_map(pmd, logical); -+ if (!pte) -+ { -+ return gcvSTATUS_NOT_FOUND; -+ } -+ -+ if (!pte_present(*pte)) -+ { -+ return gcvSTATUS_NOT_FOUND; -+ } -+ -+ *Address = (pte_pfn(*pte) << PAGE_SHIFT) | (logical & ~PAGE_MASK); -+ -+ return gcvSTATUS_OK; -+} -+ -+gctBOOL -+_AllowAccess( -+ IN gckOS Os, -+ IN gceCORE Core, -+ IN gctUINT32 Address -+ ) -+{ -+ gctUINT32 data; -+ -+ /* Check external clock state. */ -+ if (Os->clockStates[Core] == gcvFALSE) -+ { -+ gcmkPRINT("[galcore]: %s(%d) External clock off", __FUNCTION__, __LINE__); -+ return gcvFALSE; -+ } -+ -+ /* Check internal clock state. */ -+ if (Address == 0) -+ { -+ return gcvTRUE; -+ } -+ -+ data = readl((gctUINT8 *)Os->device->registerBases[Core] + 0x0); -+ -+ if ((data & 0x3) == 0x3) -+ { -+ gcmkPRINT("[galcore]: %s(%d) Internal clock off", __FUNCTION__, __LINE__); -+ return gcvFALSE; -+ } -+ -+ return gcvTRUE; -+} -+ -+static gceSTATUS -+_ShrinkMemory( -+ IN gckOS Os -+ ) -+{ -+ gcsPLATFORM * platform; -+ -+ gcmkHEADER_ARG("Os=0x%X", Os); -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ -+ platform = Os->device->platform; -+ -+ if (platform && platform->ops->shrinkMemory) -+ { -+ platform->ops->shrinkMemory(platform); -+ } -+ else -+ { -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_NOT_SUPPORTED; -+ } -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_Construct -+** -+** Construct a new gckOS object. -+** -+** INPUT: -+** -+** gctPOINTER Context -+** Pointer to the gckGALDEVICE class. -+** -+** OUTPUT: -+** -+** gckOS * Os -+** Pointer to a variable that will hold the pointer to the gckOS object. -+*/ -+gceSTATUS -+gckOS_Construct( -+ IN gctPOINTER Context, -+ OUT gckOS * Os -+ ) -+{ -+ gckOS os; -+ gceSTATUS status; -+ gctINT i; -+ -+ gcmkHEADER_ARG("Context=0x%X", Context); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_ARGUMENT(Os != gcvNULL); -+ -+ /* Allocate the gckOS object. */ -+ os = (gckOS) kmalloc(gcmSIZEOF(struct _gckOS), GFP_KERNEL | gcdNOWARN); -+ -+ if (os == gcvNULL) -+ { -+ /* Out of memory. */ -+ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_MEMORY); -+ return gcvSTATUS_OUT_OF_MEMORY; -+ } -+ -+ /* Zero the memory. */ -+ gckOS_ZeroMemory(os, gcmSIZEOF(struct _gckOS)); -+ -+ /* Initialize the gckOS object. */ -+ os->object.type = gcvOBJ_OS; -+ -+ /* Set device device. */ -+ os->device = Context; -+ -+ /* Set allocateCount to 0, gckOS_Allocate has not been used yet. */ -+ atomic_set(&os->allocateCount, 0); -+ -+ /* Initialize the memory lock. */ -+ gcmkONERROR(gckOS_CreateNamedMutex(os, &gckOS_key, "memoryLock", &os->memoryLock)); -+ gcmkONERROR(gckOS_CreateNamedMutex(os, &gckOS_MM_key, "memoryMapLock", &os->memoryMapLock)); -+ -+ /* Create debug lock mutex. */ -+ gcmkONERROR(gckOS_CreateMutex(os, &os->debugLock)); -+ -+ os->mdlHead = os->mdlTail = gcvNULL; -+ -+ /* Get the kernel process ID. */ -+ gcmkONERROR(gckOS_GetProcessID(&os->kernelProcessID)); -+ -+ /* -+ * Initialize the signal manager. -+ */ -+ -+ /* Initialize mutex. */ -+ gcmkONERROR(gckOS_CreateNamedMutex(os, &gckOS_Signal_key, "signalMutex", &os->signalMutex)); -+ -+ /* Initialize signal id database lock. */ -+ spin_lock_init(&os->signalDB.lock); -+ -+ /* Initialize signal id database. */ -+ idr_init(&os->signalDB.idr); -+ -+#if gcdANDROID_NATIVE_FENCE_SYNC -+ /* -+ * Initialize the sync point manager. -+ */ -+ -+ /* Initialize mutex. */ -+ gcmkONERROR(gckOS_CreateNamedMutex(os, &gckOS_SyncPoint_key, "syncPointMutex", &os->syncPointMutex)); -+ -+ /* Initialize sync point id database lock. */ -+ spin_lock_init(&os->syncPointDB.lock); -+ -+ /* Initialize sync point id database. */ -+ idr_init(&os->syncPointDB.idr); -+#endif -+ -+ /* Create a workqueue for os timer. */ -+ os->workqueue = create_singlethread_workqueue("galcore workqueue"); -+ -+ if (os->workqueue == gcvNULL) -+ { -+ /* Out of memory. */ -+ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); -+ } -+ -+ os->paddingPage = alloc_page(GFP_KERNEL | __GFP_HIGHMEM | gcdNOWARN); -+ if (os->paddingPage == gcvNULL) -+ { -+ /* Out of memory. */ -+ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); -+ } -+ else -+ { -+ SetPageReserved(os->paddingPage); -+ } -+ -+ for (i = 0; i < gcdMAX_GPU_COUNT; i++) -+ { -+ mutex_init(&os->registerAccessLocks[i]); -+ } -+ -+ gckOS_ImportAllocators(os); -+ -+#ifdef CONFIG_IOMMU_SUPPORT -+ if (((gckGALDEVICE)(os->device))->mmu == gcvFALSE) -+ { -+ /* Only use IOMMU when internal MMU is not enabled. */ -+ status = gckIOMMU_Construct(os, &os->iommu); -+ -+ if (gcmIS_ERROR(status)) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, gcvZONE_OS, -+ "%s(%d): Fail to setup IOMMU", -+ __FUNCTION__, __LINE__ -+ ); -+ } -+ } -+#endif -+ -+ /* Return pointer to the gckOS object. */ -+ *Os = os; -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Os=0x%X", *Os); -+ return gcvSTATUS_OK; -+ -+OnError: -+ -+#if gcdANDROID_NATIVE_FENCE_SYNC -+ if (os->syncPointMutex != gcvNULL) -+ { -+ gcmkVERIFY_OK( -+ gckOS_DeleteMutex(os, os->syncPointMutex)); -+ } -+#endif -+ -+ if (os->signalMutex != gcvNULL) -+ { -+ gcmkVERIFY_OK( -+ gckOS_DeleteMutex(os, os->signalMutex)); -+ } -+ -+ if (os->memoryMapLock != gcvNULL) -+ { -+ gcmkVERIFY_OK( -+ gckOS_DeleteMutex(os, os->memoryMapLock)); -+ } -+ -+ if (os->memoryLock != gcvNULL) -+ { -+ gcmkVERIFY_OK( -+ gckOS_DeleteMutex(os, os->memoryLock)); -+ } -+ -+ if (os->debugLock != gcvNULL) -+ { -+ gcmkVERIFY_OK( -+ gckOS_DeleteMutex(os, os->debugLock)); -+ } -+ -+ if (os->workqueue != gcvNULL) -+ { -+ destroy_workqueue(os->workqueue); -+ } -+ -+ kfree(os); -+ -+ /* Return the error. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckOS_Destroy -+** -+** Destroy an gckOS object. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object that needs to be destroyed. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_Destroy( -+ IN gckOS Os -+ ) -+{ -+ gcmkHEADER_ARG("Os=0x%X", Os); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ -+ if (Os->paddingPage != gcvNULL) -+ { -+ ClearPageReserved(Os->paddingPage); -+ __free_page(Os->paddingPage); -+ Os->paddingPage = gcvNULL; -+ } -+ -+#if gcdANDROID_NATIVE_FENCE_SYNC -+ /* -+ * Destroy the sync point manager. -+ */ -+ -+ /* Destroy the mutex. */ -+ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, Os->syncPointMutex)); -+#endif -+ -+ /* -+ * Destroy the signal manager. -+ */ -+ -+ /* Destroy the mutex. */ -+ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, Os->signalMutex)); -+ -+ /* Destroy the memory lock. */ -+ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, Os->memoryMapLock)); -+ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, Os->memoryLock)); -+ -+ /* Destroy debug lock mutex. */ -+ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, Os->debugLock)); -+ -+ /* Wait for all works done. */ -+ flush_workqueue(Os->workqueue); -+ -+ /* Destory work queue. */ -+ destroy_workqueue(Os->workqueue); -+ -+ gckOS_FreeAllocators(Os); -+ -+#ifdef CONFIG_IOMMU_SUPPORT -+ if (Os->iommu) -+ { -+ gckIOMMU_Destory(Os, Os->iommu); -+ } -+#endif -+ -+ /* Flush the debug cache. */ -+ gcmkDEBUGFLUSH(~0U); -+ -+ /* Mark the gckOS object as unknown. */ -+ Os->object.type = gcvOBJ_UNKNOWN; -+ -+ -+ /* Free the gckOS object. */ -+ kfree(Os); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckOS_CreateKernelVirtualMapping( -+ IN gckOS Os, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T Bytes, -+ OUT gctPOINTER * Logical, -+ OUT gctSIZE_T * PageCount -+ ) -+{ -+ gceSTATUS status; -+ PLINUX_MDL mdl = (PLINUX_MDL)Physical; -+ gckALLOCATOR allocator = mdl->allocator; -+ -+ gcmkHEADER(); -+ -+ *PageCount = mdl->numPages; -+ -+ gcmkONERROR(allocator->ops->MapKernel(allocator, mdl, Logical)); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckOS_DestroyKernelVirtualMapping( -+ IN gckOS Os, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T Bytes, -+ IN gctPOINTER Logical -+ ) -+{ -+ PLINUX_MDL mdl = (PLINUX_MDL)Physical; -+ gckALLOCATOR allocator = mdl->allocator; -+ -+ gcmkHEADER(); -+ -+ allocator->ops->UnmapKernel(allocator, mdl, Logical); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckOS_CreateUserVirtualMapping( -+ IN gckOS Os, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T Bytes, -+ OUT gctPOINTER * Logical, -+ OUT gctSIZE_T * PageCount -+ ) -+{ -+ return gckOS_LockPages(Os, Physical, Bytes, gcvFALSE, Logical, PageCount); -+} -+ -+gceSTATUS -+gckOS_DestroyUserVirtualMapping( -+ IN gckOS Os, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T Bytes, -+ IN gctPOINTER Logical -+ ) -+{ -+ return gckOS_UnlockPages(Os, Physical, Bytes, Logical); -+} -+ -+/******************************************************************************* -+** -+** gckOS_Allocate -+** -+** Allocate memory. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctSIZE_T Bytes -+** Number of bytes to allocate. -+** -+** OUTPUT: -+** -+** gctPOINTER * Memory -+** Pointer to a variable that will hold the allocated memory location. -+*/ -+gceSTATUS -+gckOS_Allocate( -+ IN gckOS Os, -+ IN gctSIZE_T Bytes, -+ OUT gctPOINTER * Memory -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Os=0x%X Bytes=%lu", Os, Bytes); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Bytes > 0); -+ gcmkVERIFY_ARGUMENT(Memory != gcvNULL); -+ -+ gcmkONERROR(gckOS_AllocateMemory(Os, Bytes, Memory)); -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Memory=0x%X", *Memory); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckOS_Free -+** -+** Free allocated memory. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctPOINTER Memory -+** Pointer to memory allocation to free. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_Free( -+ IN gckOS Os, -+ IN gctPOINTER Memory -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Os=0x%X Memory=0x%X", Os, Memory); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Memory != gcvNULL); -+ -+ gcmkONERROR(gckOS_FreeMemory(Os, Memory)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckOS_AllocateMemory -+** -+** Allocate memory wrapper. -+** -+** INPUT: -+** -+** gctSIZE_T Bytes -+** Number of bytes to allocate. -+** -+** OUTPUT: -+** -+** gctPOINTER * Memory -+** Pointer to a variable that will hold the allocated memory location. -+*/ -+gceSTATUS -+gckOS_AllocateMemory( -+ IN gckOS Os, -+ IN gctSIZE_T Bytes, -+ OUT gctPOINTER * Memory -+ ) -+{ -+ gctPOINTER memory; -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Os=0x%X Bytes=%lu", Os, Bytes); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_ARGUMENT(Bytes > 0); -+ gcmkVERIFY_ARGUMENT(Memory != gcvNULL); -+ -+ if (Bytes > PAGE_SIZE) -+ { -+ memory = (gctPOINTER) vmalloc(Bytes); -+ } -+ else -+ { -+ memory = (gctPOINTER) kmalloc(Bytes, GFP_KERNEL | gcdNOWARN); -+ } -+ -+ if (memory == gcvNULL) -+ { -+ /* Out of memory. */ -+ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); -+ } -+ -+ /* Increase count. */ -+ atomic_inc(&Os->allocateCount); -+ -+ /* Return pointer to the memory allocation. */ -+ *Memory = memory; -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Memory=0x%X", *Memory); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckOS_FreeMemory -+** -+** Free allocated memory wrapper. -+** -+** INPUT: -+** -+** gctPOINTER Memory -+** Pointer to memory allocation to free. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_FreeMemory( -+ IN gckOS Os, -+ IN gctPOINTER Memory -+ ) -+{ -+ gcmkHEADER_ARG("Memory=0x%X", Memory); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_ARGUMENT(Memory != gcvNULL); -+ -+ /* Free the memory from the OS pool. */ -+ if (is_vmalloc_addr(Memory)) -+ { -+ vfree(Memory); -+ } -+ else -+ { -+ kfree(Memory); -+ } -+ -+ /* Decrease count. */ -+ atomic_dec(&Os->allocateCount); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_MapMemory -+** -+** Map physical memory into the current process. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctPHYS_ADDR Physical -+** Start of physical address memory. -+** -+** gctSIZE_T Bytes -+** Number of bytes to map. -+** -+** OUTPUT: -+** -+** gctPOINTER * Memory -+** Pointer to a variable that will hold the logical address of the -+** mapped memory. -+*/ -+gceSTATUS -+gckOS_MapMemory( -+ IN gckOS Os, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T Bytes, -+ OUT gctPOINTER * Logical -+ ) -+{ -+ PLINUX_MDL_MAP mdlMap; -+ PLINUX_MDL mdl = (PLINUX_MDL)Physical; -+ -+ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%lu", Os, Physical, Bytes); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Physical != 0); -+ gcmkVERIFY_ARGUMENT(Bytes > 0); -+ gcmkVERIFY_ARGUMENT(Logical != gcvNULL); -+ -+ MEMORY_LOCK(Os); -+ -+ mdlMap = FindMdlMap(mdl, _GetProcessID()); -+ -+ if (mdlMap == gcvNULL) -+ { -+ mdlMap = _CreateMdlMap(mdl, _GetProcessID()); -+ -+ if (mdlMap == gcvNULL) -+ { -+ MEMORY_UNLOCK(Os); -+ -+ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_MEMORY); -+ return gcvSTATUS_OUT_OF_MEMORY; -+ } -+ } -+ -+ if (mdlMap->vmaAddr == gcvNULL) -+ { -+ mdlMap->vmaAddr = (char *)vm_mmap(gcvNULL, -+ 0L, -+ mdl->numPages * PAGE_SIZE, -+ PROT_READ | PROT_WRITE, -+ MAP_SHARED, -+ 0); -+ -+ if (IS_ERR(mdlMap->vmaAddr)) -+ { -+ gcmkTRACE( -+ gcvLEVEL_ERROR, -+ "%s(%d): do_mmap_pgoff error", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ gcmkTRACE( -+ gcvLEVEL_ERROR, -+ "%s(%d): mdl->numPages: %d mdl->vmaAddr: 0x%X", -+ __FUNCTION__, __LINE__, -+ mdl->numPages, -+ mdlMap->vmaAddr -+ ); -+ -+ mdlMap->vmaAddr = gcvNULL; -+ -+ MEMORY_UNLOCK(Os); -+ -+ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_MEMORY); -+ return gcvSTATUS_OUT_OF_MEMORY; -+ } -+ -+ down_write(¤t->mm->mmap_sem); -+ -+ mdlMap->vma = find_vma(current->mm, (unsigned long)mdlMap->vmaAddr); -+ -+ if (!mdlMap->vma) -+ { -+ gcmkTRACE( -+ gcvLEVEL_ERROR, -+ "%s(%d): find_vma error.", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ mdlMap->vmaAddr = gcvNULL; -+ -+ up_write(¤t->mm->mmap_sem); -+ -+ MEMORY_UNLOCK(Os); -+ -+ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_RESOURCES); -+ return gcvSTATUS_OUT_OF_RESOURCES; -+ } -+ -+#ifndef NO_DMA_COHERENT -+ if (dma_mmap_writecombine(gcvNULL, -+ mdlMap->vma, -+ mdl->addr, -+ mdl->dmaHandle, -+ mdl->numPages * PAGE_SIZE) < 0) -+ { -+ up_write(¤t->mm->mmap_sem); -+ -+ gcmkTRACE( -+ gcvLEVEL_ERROR, -+ "%s(%d): dma_mmap_coherent error.", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ mdlMap->vmaAddr = gcvNULL; -+ -+ MEMORY_UNLOCK(Os); -+ -+ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_RESOURCES); -+ return gcvSTATUS_OUT_OF_RESOURCES; -+ } -+#else -+#if !gcdPAGED_MEMORY_CACHEABLE -+ mdlMap->vma->vm_page_prot = gcmkPAGED_MEMROY_PROT(mdlMap->vma->vm_page_prot); -+ mdlMap->vma->vm_flags |= gcdVM_FLAGS; -+# endif -+ mdlMap->vma->vm_pgoff = 0; -+ -+ if (remap_pfn_range(mdlMap->vma, -+ mdlMap->vma->vm_start, -+ mdl->dmaHandle >> PAGE_SHIFT, -+ mdl->numPages*PAGE_SIZE, -+ mdlMap->vma->vm_page_prot) < 0) -+ { -+ up_write(¤t->mm->mmap_sem); -+ -+ gcmkTRACE( -+ gcvLEVEL_ERROR, -+ "%s(%d): remap_pfn_range error.", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ mdlMap->vmaAddr = gcvNULL; -+ -+ MEMORY_UNLOCK(Os); -+ -+ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_RESOURCES); -+ return gcvSTATUS_OUT_OF_RESOURCES; -+ } -+#endif -+ -+ up_write(¤t->mm->mmap_sem); -+ } -+ -+ MEMORY_UNLOCK(Os); -+ -+ *Logical = mdlMap->vmaAddr; -+ -+ gcmkFOOTER_ARG("*Logical=0x%X", *Logical); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_UnmapMemory -+** -+** Unmap physical memory out of the current process. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctPHYS_ADDR Physical -+** Start of physical address memory. -+** -+** gctSIZE_T Bytes -+** Number of bytes to unmap. -+** -+** gctPOINTER Memory -+** Pointer to a previously mapped memory region. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_UnmapMemory( -+ IN gckOS Os, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T Bytes, -+ IN gctPOINTER Logical -+ ) -+{ -+ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%lu Logical=0x%X", -+ Os, Physical, Bytes, Logical); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Physical != 0); -+ gcmkVERIFY_ARGUMENT(Bytes > 0); -+ gcmkVERIFY_ARGUMENT(Logical != gcvNULL); -+ -+ gckOS_UnmapMemoryEx(Os, Physical, Bytes, Logical, _GetProcessID()); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+ -+/******************************************************************************* -+** -+** gckOS_UnmapMemoryEx -+** -+** Unmap physical memory in the specified process. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctPHYS_ADDR Physical -+** Start of physical address memory. -+** -+** gctSIZE_T Bytes -+** Number of bytes to unmap. -+** -+** gctPOINTER Memory -+** Pointer to a previously mapped memory region. -+** -+** gctUINT32 PID -+** Pid of the process that opened the device and mapped this memory. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_UnmapMemoryEx( -+ IN gckOS Os, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T Bytes, -+ IN gctPOINTER Logical, -+ IN gctUINT32 PID -+ ) -+{ -+ PLINUX_MDL_MAP mdlMap; -+ PLINUX_MDL mdl = (PLINUX_MDL)Physical; -+ -+ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%lu Logical=0x%X PID=%d", -+ Os, Physical, Bytes, Logical, PID); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Physical != 0); -+ gcmkVERIFY_ARGUMENT(Bytes > 0); -+ gcmkVERIFY_ARGUMENT(Logical != gcvNULL); -+ gcmkVERIFY_ARGUMENT(PID != 0); -+ -+ MEMORY_LOCK(Os); -+ -+ if (Logical) -+ { -+ mdlMap = FindMdlMap(mdl, PID); -+ -+ if (mdlMap == gcvNULL || mdlMap->vmaAddr == gcvNULL) -+ { -+ MEMORY_UNLOCK(Os); -+ -+ gcmkFOOTER_ARG("status=%d", gcvSTATUS_INVALID_ARGUMENT); -+ return gcvSTATUS_INVALID_ARGUMENT; -+ } -+ -+ _UnmapUserLogical(mdlMap->vmaAddr, mdl->numPages * PAGE_SIZE); -+ -+ gcmkVERIFY_OK(_DestroyMdlMap(mdl, mdlMap)); -+ } -+ -+ MEMORY_UNLOCK(Os); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_UnmapUserLogical -+** -+** Unmap user logical memory out of physical memory. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctPHYS_ADDR Physical -+** Start of physical address memory. -+** -+** gctSIZE_T Bytes -+** Number of bytes to unmap. -+** -+** gctPOINTER Memory -+** Pointer to a previously mapped memory region. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_UnmapUserLogical( -+ IN gckOS Os, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T Bytes, -+ IN gctPOINTER Logical -+ ) -+{ -+ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%lu Logical=0x%X", -+ Os, Physical, Bytes, Logical); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Physical != 0); -+ gcmkVERIFY_ARGUMENT(Bytes > 0); -+ gcmkVERIFY_ARGUMENT(Logical != gcvNULL); -+ -+ gckOS_UnmapMemory(Os, Physical, Bytes, Logical); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+} -+ -+/******************************************************************************* -+** -+** gckOS_AllocateNonPagedMemory -+** -+** Allocate a number of pages from non-paged memory. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctBOOL InUserSpace -+** gcvTRUE if the pages need to be mapped into user space. -+** -+** gctSIZE_T * Bytes -+** Pointer to a variable that holds the number of bytes to allocate. -+** -+** OUTPUT: -+** -+** gctSIZE_T * Bytes -+** Pointer to a variable that hold the number of bytes allocated. -+** -+** gctPHYS_ADDR * Physical -+** Pointer to a variable that will hold the physical address of the -+** allocation. -+** -+** gctPOINTER * Logical -+** Pointer to a variable that will hold the logical address of the -+** allocation. -+*/ -+gceSTATUS -+gckOS_AllocateNonPagedMemory( -+ IN gckOS Os, -+ IN gctBOOL InUserSpace, -+ IN OUT gctSIZE_T * Bytes, -+ OUT gctPHYS_ADDR * Physical, -+ OUT gctPOINTER * Logical -+ ) -+{ -+ gctSIZE_T bytes; -+ gctINT numPages; -+ PLINUX_MDL mdl = gcvNULL; -+ PLINUX_MDL_MAP mdlMap = gcvNULL; -+ gctSTRING addr; -+ gckKERNEL kernel; -+#ifdef NO_DMA_COHERENT -+ struct page * page; -+ long size, order; -+ gctPOINTER vaddr; -+#endif -+ gctBOOL locked = gcvFALSE; -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Os=0x%X InUserSpace=%d *Bytes=%lu", -+ Os, InUserSpace, gcmOPT_VALUE(Bytes)); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Bytes != gcvNULL); -+ gcmkVERIFY_ARGUMENT(*Bytes > 0); -+ gcmkVERIFY_ARGUMENT(Physical != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Logical != gcvNULL); -+ -+ /* Align number of bytes to page size. */ -+ bytes = gcmALIGN(*Bytes, PAGE_SIZE); -+ -+ /* Get total number of pages.. */ -+ numPages = GetPageCount(bytes, 0); -+ -+ /* Allocate mdl+vector structure */ -+ mdl = _CreateMdl(); -+ if (mdl == gcvNULL) -+ { -+ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); -+ } -+ -+ mdl->pagedMem = 0; -+ mdl->numPages = numPages; -+ -+ MEMORY_LOCK(Os); -+ locked = gcvTRUE; -+ -+#ifndef NO_DMA_COHERENT -+#ifdef CONFIG_ARM64 -+ addr = dma_alloc_coherent(gcvNULL, -+#else -+ addr = dma_alloc_writecombine(gcvNULL, -+#endif -+ mdl->numPages * PAGE_SIZE, -+ &mdl->dmaHandle, -+ GFP_KERNEL | gcdNOWARN); -+#else -+ size = mdl->numPages * PAGE_SIZE; -+ order = get_order(size); -+ -+ page = alloc_pages(GFP_KERNEL | gcdNOWARN, order); -+ -+ if (page == gcvNULL) -+ { -+ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); -+ } -+ -+ vaddr = (gctPOINTER)page_address(page); -+ mdl->contiguous = gcvTRUE; -+ mdl->u.contiguousPages = page; -+ addr = _CreateKernelVirtualMapping(mdl); -+ mdl->dmaHandle = virt_to_phys(vaddr); -+ mdl->kaddr = vaddr; -+ -+ /* Trigger a page fault. */ -+ memset(addr, 0, numPages * PAGE_SIZE); -+ -+#if !defined(CONFIG_PPC) -+ /* Cache invalidate. */ -+ dma_sync_single_for_device( -+ gcvNULL, -+ page_to_phys(page), -+ bytes, -+ DMA_FROM_DEVICE); -+#endif -+ -+ while (size > 0) -+ { -+ SetPageReserved(virt_to_page(vaddr)); -+ -+ vaddr += PAGE_SIZE; -+ size -= PAGE_SIZE; -+ } -+#endif -+ -+ if (addr == gcvNULL) -+ { -+ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); -+ } -+ -+ kernel = Os->device->kernels[gcvCORE_MAJOR] != gcvNULL ? -+ Os->device->kernels[gcvCORE_MAJOR] : Os->device->kernels[gcvCORE_2D]; -+ if (((Os->device->baseAddress & 0x80000000) != (mdl->dmaHandle & 0x80000000)) && -+ kernel->hardware->mmuVersion == 0) -+ { -+ mdl->dmaHandle = (mdl->dmaHandle & ~0x80000000) -+ | (Os->device->baseAddress & 0x80000000); -+ } -+ -+ mdl->addr = addr; -+ -+ if (InUserSpace) -+ { -+ mdlMap = _CreateMdlMap(mdl, _GetProcessID()); -+ -+ if (mdlMap == gcvNULL) -+ { -+ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); -+ } -+ -+ /* Only after mmap this will be valid. */ -+ -+ /* We need to map this to user space. */ -+ mdlMap->vmaAddr = (gctSTRING) vm_mmap(gcvNULL, -+ 0L, -+ mdl->numPages * PAGE_SIZE, -+ PROT_READ | PROT_WRITE, -+ MAP_SHARED, -+ 0); -+ -+ if (IS_ERR(mdlMap->vmaAddr)) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_WARNING, gcvZONE_OS, -+ "%s(%d): do_mmap_pgoff error", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ mdlMap->vmaAddr = gcvNULL; -+ -+ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); -+ } -+ -+ down_write(¤t->mm->mmap_sem); -+ -+ mdlMap->vma = find_vma(current->mm, (unsigned long)mdlMap->vmaAddr); -+ -+ if (mdlMap->vma == gcvNULL) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_WARNING, gcvZONE_OS, -+ "%s(%d): find_vma error", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ up_write(¤t->mm->mmap_sem); -+ -+ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES); -+ } -+ -+#ifndef NO_DMA_COHERENT -+ if (dma_mmap_coherent(gcvNULL, -+ mdlMap->vma, -+ mdl->addr, -+ mdl->dmaHandle, -+ mdl->numPages * PAGE_SIZE) < 0) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_WARNING, gcvZONE_OS, -+ "%s(%d): dma_mmap_coherent error", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ up_write(¤t->mm->mmap_sem); -+ -+ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES); -+ } -+#else -+ mdlMap->vma->vm_page_prot = gcmkNONPAGED_MEMROY_PROT(mdlMap->vma->vm_page_prot); -+ mdlMap->vma->vm_flags |= gcdVM_FLAGS; -+ mdlMap->vma->vm_pgoff = 0; -+ -+ if (remap_pfn_range(mdlMap->vma, -+ mdlMap->vma->vm_start, -+ mdl->dmaHandle >> PAGE_SHIFT, -+ mdl->numPages * PAGE_SIZE, -+ mdlMap->vma->vm_page_prot)) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_WARNING, gcvZONE_OS, -+ "%s(%d): remap_pfn_range error", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ up_write(¤t->mm->mmap_sem); -+ -+ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES); -+ } -+#endif /* NO_DMA_COHERENT */ -+ -+ up_write(¤t->mm->mmap_sem); -+ -+ *Logical = mdlMap->vmaAddr; -+ } -+ else -+ { -+ *Logical = (gctPOINTER)mdl->addr; -+ } -+ -+ /* -+ * Add this to a global list. -+ * Will be used by get physical address -+ * and mapuser pointer functions. -+ */ -+ -+ if (!Os->mdlHead) -+ { -+ /* Initialize the queue. */ -+ Os->mdlHead = Os->mdlTail = mdl; -+ } -+ else -+ { -+ /* Add to the tail. */ -+ mdl->prev = Os->mdlTail; -+ Os->mdlTail->next = mdl; -+ Os->mdlTail = mdl; -+ } -+ -+ MEMORY_UNLOCK(Os); -+ -+ /* Return allocated memory. */ -+ *Bytes = bytes; -+ *Physical = (gctPHYS_ADDR) mdl; -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Bytes=%lu *Physical=0x%X *Logical=0x%X", -+ *Bytes, *Physical, *Logical); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (mdlMap != gcvNULL) -+ { -+ /* Free LINUX_MDL_MAP. */ -+ gcmkVERIFY_OK(_DestroyMdlMap(mdl, mdlMap)); -+ } -+ -+ if (mdl != gcvNULL) -+ { -+ /* Free LINUX_MDL. */ -+ gcmkVERIFY_OK(_DestroyMdl(mdl)); -+ } -+ *Physical = gcvNULL; -+ *Bytes = 0; -+ -+ if (locked) -+ { -+ /* Unlock memory. */ -+ MEMORY_UNLOCK(Os); -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckOS_FreeNonPagedMemory -+** -+** Free previously allocated and mapped pages from non-paged memory. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctSIZE_T Bytes -+** Number of bytes allocated. -+** -+** gctPHYS_ADDR Physical -+** Physical address of the allocated memory. -+** -+** gctPOINTER Logical -+** Logical address of the allocated memory. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS gckOS_FreeNonPagedMemory( -+ IN gckOS Os, -+ IN gctSIZE_T Bytes, -+ IN gctPHYS_ADDR Physical, -+ IN gctPOINTER Logical -+ ) -+{ -+ PLINUX_MDL mdl; -+ PLINUX_MDL_MAP mdlMap; -+#ifdef NO_DMA_COHERENT -+ unsigned size; -+ gctPOINTER vaddr; -+#endif /* NO_DMA_COHERENT */ -+ -+ gcmkHEADER_ARG("Os=0x%X Bytes=%lu Physical=0x%X Logical=0x%X", -+ Os, Bytes, Physical, Logical); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Bytes > 0); -+ gcmkVERIFY_ARGUMENT(Physical != 0); -+ gcmkVERIFY_ARGUMENT(Logical != gcvNULL); -+ -+ /* Convert physical address into a pointer to a MDL. */ -+ mdl = (PLINUX_MDL) Physical; -+ -+ MEMORY_LOCK(Os); -+ -+#ifndef NO_DMA_COHERENT -+#ifdef CONFIG_ARM64 -+ dma_free_coherent(gcvNULL, -+#else -+ dma_free_writecombine(gcvNULL, -+#endif -+ mdl->numPages * PAGE_SIZE, -+ mdl->addr, -+ mdl->dmaHandle); -+#else -+ size = mdl->numPages * PAGE_SIZE; -+ vaddr = mdl->kaddr; -+ -+ while (size > 0) -+ { -+ ClearPageReserved(virt_to_page(vaddr)); -+ -+ vaddr += PAGE_SIZE; -+ size -= PAGE_SIZE; -+ } -+ -+ free_pages((unsigned long)mdl->kaddr, get_order(mdl->numPages * PAGE_SIZE)); -+ -+ _DestoryKernelVirtualMapping(mdl->addr); -+#endif /* NO_DMA_COHERENT */ -+ -+ mdlMap = mdl->maps; -+ -+ while (mdlMap != gcvNULL) -+ { -+ /* No mapped memory exists when free nonpaged memory */ -+ gcmkASSERT(mdlMap->vmaAddr == gcvNULL); -+ -+ mdlMap = mdlMap->next; -+ } -+ -+ /* Remove the node from global list.. */ -+ if (mdl == Os->mdlHead) -+ { -+ if ((Os->mdlHead = mdl->next) == gcvNULL) -+ { -+ Os->mdlTail = gcvNULL; -+ } -+ } -+ else -+ { -+ mdl->prev->next = mdl->next; -+ if (mdl == Os->mdlTail) -+ { -+ Os->mdlTail = mdl->prev; -+ } -+ else -+ { -+ mdl->next->prev = mdl->prev; -+ } -+ } -+ -+ MEMORY_UNLOCK(Os); -+ -+ gcmkVERIFY_OK(_DestroyMdl(mdl)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_ReadRegister -+** -+** Read data from a register. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctUINT32 Address -+** Address of register. -+** -+** OUTPUT: -+** -+** gctUINT32 * Data -+** Pointer to a variable that receives the data read from the register. -+*/ -+gceSTATUS -+gckOS_ReadRegister( -+ IN gckOS Os, -+ IN gctUINT32 Address, -+ OUT gctUINT32 * Data -+ ) -+{ -+ return gckOS_ReadRegisterEx(Os, gcvCORE_MAJOR, Address, Data); -+} -+ -+gceSTATUS -+gckOS_ReadRegisterEx( -+ IN gckOS Os, -+ IN gceCORE Core, -+ IN gctUINT32 Address, -+ OUT gctUINT32 * Data -+ ) -+{ -+ gcmkHEADER_ARG("Os=0x%X Core=%d Address=0x%X", Os, Core, Address); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Address < Os->device->requestedRegisterMemSizes[Core]); -+ gcmkVERIFY_ARGUMENT(Data != gcvNULL); -+ -+ if (!in_interrupt()) -+ { -+ mutex_lock(&Os->registerAccessLocks[Core]); -+ } -+ -+ BUG_ON(!_AllowAccess(Os, Core, Address)); -+ -+ *Data = readl((gctUINT8 *)Os->device->registerBases[Core] + Address); -+ -+ if (!in_interrupt()) -+ { -+ mutex_unlock(&Os->registerAccessLocks[Core]); -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Data=0x%08x", *Data); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_WriteRegister -+** -+** Write data to a register. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctUINT32 Address -+** Address of register. -+** -+** gctUINT32 Data -+** Data for register. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_WriteRegister( -+ IN gckOS Os, -+ IN gctUINT32 Address, -+ IN gctUINT32 Data -+ ) -+{ -+ return gckOS_WriteRegisterEx(Os, gcvCORE_MAJOR, Address, Data); -+} -+ -+gceSTATUS -+gckOS_WriteRegisterEx( -+ IN gckOS Os, -+ IN gceCORE Core, -+ IN gctUINT32 Address, -+ IN gctUINT32 Data -+ ) -+{ -+ gcmkHEADER_ARG("Os=0x%X Core=%d Address=0x%X Data=0x%08x", Os, Core, Address, Data); -+ -+ gcmkVERIFY_ARGUMENT(Address < Os->device->requestedRegisterMemSizes[Core]); -+ -+ if (!in_interrupt()) -+ { -+ mutex_lock(&Os->registerAccessLocks[Core]); -+ } -+ -+ BUG_ON(!_AllowAccess(Os, Core, Address)); -+ -+ writel(Data, (gctUINT8 *)Os->device->registerBases[Core] + Address); -+ -+ if (!in_interrupt()) -+ { -+ mutex_unlock(&Os->registerAccessLocks[Core]); -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_GetPageSize -+** -+** Get the system's page size. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** OUTPUT: -+** -+** gctSIZE_T * PageSize -+** Pointer to a variable that will receive the system's page size. -+*/ -+gceSTATUS gckOS_GetPageSize( -+ IN gckOS Os, -+ OUT gctSIZE_T * PageSize -+ ) -+{ -+ gcmkHEADER_ARG("Os=0x%X", Os); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(PageSize != gcvNULL); -+ -+ /* Return the page size. */ -+ *PageSize = (gctSIZE_T) PAGE_SIZE; -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*PageSize", *PageSize); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_GetPhysicalAddress -+** -+** Get the physical system address of a corresponding virtual address. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctPOINTER Logical -+** Logical address. -+** -+** OUTPUT: -+** -+** gctUINT32 * Address -+** Poinetr to a variable that receives the 32-bit physical adress. -+*/ -+gceSTATUS -+gckOS_GetPhysicalAddress( -+ IN gckOS Os, -+ IN gctPOINTER Logical, -+ OUT gctUINT32 * Address -+ ) -+{ -+ gceSTATUS status; -+ gctUINT32 processID; -+ -+ gcmkHEADER_ARG("Os=0x%X Logical=0x%X", Os, Logical); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Address != gcvNULL); -+ -+ /* Query page table of current process first. */ -+ status = _QueryProcessPageTable(Logical, Address); -+ -+ if (gcmIS_ERROR(status)) -+ { -+ /* Get current process ID. */ -+ processID = _GetProcessID(); -+ -+ /* Route through other function. */ -+ gcmkONERROR( -+ gckOS_GetPhysicalAddressProcess(Os, Logical, processID, Address)); -+ } -+ -+ gcmkVERIFY_OK(gckOS_CPUPhysicalToGPUPhysical(Os, *Address, Address)); -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Address=0x%08x", *Address); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckOS_UserLogicalToPhysical -+** -+** Get the physical system address of a corresponding user virtual address. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctPOINTER Logical -+** Logical address. -+** -+** OUTPUT: -+** -+** gctUINT32 * Address -+** Pointer to a variable that receives the 32-bit physical address. -+*/ -+gceSTATUS gckOS_UserLogicalToPhysical( -+ IN gckOS Os, -+ IN gctPOINTER Logical, -+ OUT gctUINT32 * Address -+ ) -+{ -+ return gckOS_GetPhysicalAddress(Os, Logical, Address); -+} -+ -+gceSTATUS -+_ConvertLogical2Physical( -+ IN gckOS Os, -+ IN gctPOINTER Logical, -+ IN gctUINT32 ProcessID, -+ IN PLINUX_MDL Mdl, -+ OUT gctUINT32_PTR Physical -+ ) -+{ -+ gctINT8_PTR base, vBase; -+ gctUINT32 offset; -+ PLINUX_MDL_MAP map; -+ gcsUSER_MAPPING_PTR userMap; -+ -+ base = (Mdl == gcvNULL) ? gcvNULL : (gctINT8_PTR) Mdl->addr; -+ -+ /* Check for the logical address match. */ -+ if ((base != gcvNULL) -+ && ((gctINT8_PTR) Logical >= base) -+ && ((gctINT8_PTR) Logical < base + Mdl->numPages * PAGE_SIZE) -+ ) -+ { -+ offset = (gctINT8_PTR) Logical - base; -+ -+ if (Mdl->dmaHandle != 0) -+ { -+ /* The memory was from coherent area. */ -+ *Physical = (gctUINT32) Mdl->dmaHandle + offset; -+ } -+ else if (Mdl->pagedMem && !Mdl->contiguous) -+ { -+ /* paged memory is not mapped to kernel space. */ -+ return gcvSTATUS_INVALID_ADDRESS; -+ } -+ else -+ { -+ *Physical = gcmPTR2INT32(virt_to_phys(base)) + offset; -+ } -+ -+ return gcvSTATUS_OK; -+ } -+ -+ /* Walk user maps. */ -+ for (userMap = Os->userMap; userMap != gcvNULL; userMap = userMap->next) -+ { -+ if (((gctINT8_PTR) Logical >= userMap->start) -+ && ((gctINT8_PTR) Logical < userMap->end) -+ ) -+ { -+ *Physical = userMap->physical -+ + (gctUINT32) ((gctINT8_PTR) Logical - userMap->start); -+ -+ return gcvSTATUS_OK; -+ } -+ } -+ -+ if (ProcessID != Os->kernelProcessID) -+ { -+ map = FindMdlMap(Mdl, (gctINT) ProcessID); -+ vBase = (map == gcvNULL) ? gcvNULL : (gctINT8_PTR) map->vmaAddr; -+ -+ /* Is the given address within that range. */ -+ if ((vBase != gcvNULL) -+ && ((gctINT8_PTR) Logical >= vBase) -+ && ((gctINT8_PTR) Logical < vBase + Mdl->numPages * PAGE_SIZE) -+ ) -+ { -+ offset = (gctINT8_PTR) Logical - vBase; -+ -+ if (Mdl->dmaHandle != 0) -+ { -+ /* The memory was from coherent area. */ -+ *Physical = (gctUINT32) Mdl->dmaHandle + offset; -+ } -+ else if (Mdl->pagedMem && !Mdl->contiguous) -+ { -+ *Physical = _NonContiguousToPhys(Mdl->u.nonContiguousPages, offset/PAGE_SIZE); -+ } -+ else -+ { -+ *Physical = page_to_phys(Mdl->u.contiguousPages) + offset; -+ } -+ -+ return gcvSTATUS_OK; -+ } -+ } -+ -+ /* Address not yet found. */ -+ return gcvSTATUS_INVALID_ADDRESS; -+} -+ -+/******************************************************************************* -+** -+** gckOS_GetPhysicalAddressProcess -+** -+** Get the physical system address of a corresponding virtual address for a -+** given process. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to gckOS object. -+** -+** gctPOINTER Logical -+** Logical address. -+** -+** gctUINT32 ProcessID -+** Process ID. -+** -+** OUTPUT: -+** -+** gctUINT32 * Address -+** Poinetr to a variable that receives the 32-bit physical adress. -+*/ -+gceSTATUS -+gckOS_GetPhysicalAddressProcess( -+ IN gckOS Os, -+ IN gctPOINTER Logical, -+ IN gctUINT32 ProcessID, -+ OUT gctUINT32 * Address -+ ) -+{ -+ PLINUX_MDL mdl; -+ gctINT8_PTR base; -+ gckALLOCATOR allocator = gcvNULL; -+ gceSTATUS status = gcvSTATUS_INVALID_ADDRESS; -+ -+ gcmkHEADER_ARG("Os=0x%X Logical=0x%X ProcessID=%d", Os, Logical, ProcessID); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Address != gcvNULL); -+ -+ MEMORY_LOCK(Os); -+ -+ /* First try the contiguous memory pool. */ -+ if (Os->device->contiguousMapped) -+ { -+ base = (gctINT8_PTR) Os->device->contiguousBase; -+ -+ if (((gctINT8_PTR) Logical >= base) -+ && ((gctINT8_PTR) Logical < base + Os->device->contiguousSize) -+ ) -+ { -+ /* Convert logical address into physical. */ -+ *Address = Os->device->contiguousVidMem->baseAddress -+ + (gctINT8_PTR) Logical - base; -+ status = gcvSTATUS_OK; -+ } -+ } -+ else -+ { -+ /* Try the contiguous memory pool. */ -+ mdl = (PLINUX_MDL) Os->device->contiguousPhysical; -+ status = _ConvertLogical2Physical(Os, -+ Logical, -+ ProcessID, -+ mdl, -+ Address); -+ } -+ -+ if (gcmIS_ERROR(status)) -+ { -+ /* Walk all MDLs. */ -+ for (mdl = Os->mdlHead; mdl != gcvNULL; mdl = mdl->next) -+ { -+ /* Try this MDL. */ -+ allocator = mdl->allocator; -+ -+ if (allocator) -+ { -+ status = allocator->ops->LogicalToPhysical( -+ allocator, -+ mdl, -+ Logical, -+ ProcessID, -+ Address -+ ); -+ } -+ else -+ { -+ status = _ConvertLogical2Physical(Os, -+ Logical, -+ ProcessID, -+ mdl, -+ Address); -+ } -+ -+ if (gcmIS_SUCCESS(status)) -+ { -+ break; -+ } -+ } -+ } -+ -+ MEMORY_UNLOCK(Os); -+ -+ gcmkONERROR(status); -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Address=0x%08x", *Address); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckOS_MapPhysical -+** -+** Map a physical address into kernel space. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctUINT32 Physical -+** Physical address of the memory to map. -+** -+** gctSIZE_T Bytes -+** Number of bytes to map. -+** -+** OUTPUT: -+** -+** gctPOINTER * Logical -+** Pointer to a variable that receives the base address of the mapped -+** memory. -+*/ -+gceSTATUS -+gckOS_MapPhysical( -+ IN gckOS Os, -+ IN gctUINT32 Physical, -+ IN gctSIZE_T Bytes, -+ OUT gctPOINTER * Logical -+ ) -+{ -+ gctPOINTER logical; -+ PLINUX_MDL mdl; -+ gctUINT32 physical = Physical; -+ -+ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%lu", Os, Physical, Bytes); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Bytes > 0); -+ gcmkVERIFY_ARGUMENT(Logical != gcvNULL); -+ -+ MEMORY_LOCK(Os); -+ -+ /* Go through our mapping to see if we know this physical address already. */ -+ mdl = Os->mdlHead; -+ -+ while (mdl != gcvNULL) -+ { -+ if (mdl->dmaHandle != 0) -+ { -+ if ((physical >= mdl->dmaHandle) -+ && (physical < mdl->dmaHandle + mdl->numPages * PAGE_SIZE) -+ ) -+ { -+ *Logical = mdl->addr + (physical - mdl->dmaHandle); -+ break; -+ } -+ } -+ -+ mdl = mdl->next; -+ } -+ -+ MEMORY_UNLOCK(Os); -+ -+ if (mdl == gcvNULL) -+ { -+ struct page * page = pfn_to_page(physical >> PAGE_SHIFT); -+ -+ if (pfn_valid(page_to_pfn(page))) -+ { -+ gctUINT32 offset = physical & ~PAGE_MASK; -+ struct page ** pages; -+ gctUINT numPages; -+ gctINT i; -+ -+ numPages = GetPageCount(PAGE_ALIGN(offset + Bytes), 0); -+ -+ pages = kmalloc(sizeof(struct page *) * numPages, GFP_KERNEL | gcdNOWARN); -+ -+ if (!pages) -+ { -+ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_MEMORY); -+ return gcvSTATUS_OUT_OF_MEMORY; -+ } -+ -+ for (i = 0; i < numPages; i++) -+ { -+ pages[i] = nth_page(page, i); -+ } -+ -+ logical = vmap(pages, numPages, 0, gcmkNONPAGED_MEMROY_PROT(PAGE_KERNEL)); -+ -+ kfree(pages); -+ -+ if (logical == gcvNULL) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, gcvZONE_OS, -+ "%s(%d): Failed to vmap", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ /* Out of resources. */ -+ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_RESOURCES); -+ return gcvSTATUS_OUT_OF_RESOURCES; -+ } -+ -+ logical += offset; -+ } -+ else -+ { -+ /* Map memory as cached memory. */ -+ request_mem_region(physical, Bytes, "MapRegion"); -+ logical = (gctPOINTER) ioremap_nocache(physical, Bytes); -+ -+ if (logical == gcvNULL) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, gcvZONE_OS, -+ "%s(%d): Failed to ioremap", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ /* Out of resources. */ -+ gcmkFOOTER_ARG("status=%d", gcvSTATUS_OUT_OF_RESOURCES); -+ return gcvSTATUS_OUT_OF_RESOURCES; -+ } -+ } -+ -+ /* Return pointer to mapped memory. */ -+ *Logical = logical; -+ } -+ -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Logical=0x%X", *Logical); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_UnmapPhysical -+** -+** Unmap a previously mapped memory region from kernel memory. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctPOINTER Logical -+** Pointer to the base address of the memory to unmap. -+** -+** gctSIZE_T Bytes -+** Number of bytes to unmap. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_UnmapPhysical( -+ IN gckOS Os, -+ IN gctPOINTER Logical, -+ IN gctSIZE_T Bytes -+ ) -+{ -+ PLINUX_MDL mdl; -+ -+ gcmkHEADER_ARG("Os=0x%X Logical=0x%X Bytes=%lu", Os, Logical, Bytes); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Logical != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Bytes > 0); -+ -+ MEMORY_LOCK(Os); -+ -+ mdl = Os->mdlHead; -+ -+ while (mdl != gcvNULL) -+ { -+ if (mdl->addr != gcvNULL) -+ { -+ if (Logical >= (gctPOINTER)mdl->addr -+ && Logical < (gctPOINTER)((gctSTRING)mdl->addr + mdl->numPages * PAGE_SIZE)) -+ { -+ break; -+ } -+ } -+ -+ mdl = mdl->next; -+ } -+ -+ if (mdl == gcvNULL) -+ { -+ /* Unmap the memory. */ -+ vunmap((void *)((unsigned long)Logical & PAGE_MASK)); -+ } -+ -+ MEMORY_UNLOCK(Os); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_CreateMutex -+** -+** Create a new mutex. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** OUTPUT: -+** -+** gctPOINTER * Mutex -+** Pointer to a variable that will hold a pointer to the mutex. -+*/ -+gceSTATUS -+gckOS_CreateMutex( -+ IN gckOS Os, -+ OUT gctPOINTER * Mutex -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Os=0x%X", Os); -+ -+ /* Validate the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Mutex != gcvNULL); -+ -+ /* Allocate the mutex structure. */ -+ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(struct mutex), Mutex)); -+ -+ /* Initialize the mutex. */ -+ mutex_init(*Mutex); -+ -+ /* Return status. */ -+ gcmkFOOTER_ARG("*Mutex=0x%X", *Mutex); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+static gceSTATUS -+gckOS_CreateNamedMutex( -+ IN gckOS Os, -+ IN struct lock_class_key *key, -+ IN const char *name, -+ OUT gctPOINTER * Mutex -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Os=0x%X", Os); -+ -+ /* Validate the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Mutex != gcvNULL); -+ -+ /* Allocate the mutex structure. */ -+ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(struct mutex), Mutex)); -+ -+ /* Initialize the mutex. */ -+ mutex_init(*Mutex); -+ lockdep_set_class_and_name((struct mutex *)Mutex, key, name); -+ -+ /* Return status. */ -+ gcmkFOOTER_ARG("*Mutex=0x%X", *Mutex); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckOS_DeleteMutex -+** -+** Delete a mutex. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctPOINTER Mutex -+** Pointer to the mute to be deleted. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_DeleteMutex( -+ IN gckOS Os, -+ IN gctPOINTER Mutex -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Os=0x%X Mutex=0x%X", Os, Mutex); -+ -+ /* Validate the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Mutex != gcvNULL); -+ -+ /* Destroy the mutex. */ -+ mutex_destroy((struct mutex *)Mutex); -+ -+ /* Free the mutex structure. */ -+ gcmkONERROR(gckOS_Free(Os, Mutex)); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckOS_AcquireMutex -+** -+** Acquire a mutex. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctPOINTER Mutex -+** Pointer to the mutex to be acquired. -+** -+** gctUINT32 Timeout -+** Timeout value specified in milliseconds. -+** Specify the value of gcvINFINITE to keep the thread suspended -+** until the mutex has been acquired. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_AcquireMutex( -+ IN gckOS Os, -+ IN gctPOINTER Mutex, -+ IN gctUINT32 Timeout -+ ) -+{ -+ gcmkHEADER_ARG("Os=0x%X Mutex=0x%0x Timeout=%u", Os, Mutex, Timeout); -+ -+ /* Validate the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Mutex != gcvNULL); -+ -+ if (Timeout == gcvINFINITE) -+ { -+ /* Lock the mutex. */ -+ mutex_lock(Mutex); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ } -+ -+ for (;;) -+ { -+ /* Try to acquire the mutex. */ -+ if (mutex_trylock(Mutex)) -+ { -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ } -+ -+ if (Timeout-- == 0) -+ { -+ break; -+ } -+ -+ /* Wait for 1 millisecond. */ -+ gcmkVERIFY_OK(gckOS_Delay(Os, 1)); -+ } -+ -+ /* Timeout. */ -+ gcmkFOOTER_ARG("status=%d", gcvSTATUS_TIMEOUT); -+ return gcvSTATUS_TIMEOUT; -+} -+ -+/******************************************************************************* -+** -+** gckOS_ReleaseMutex -+** -+** Release an acquired mutex. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctPOINTER Mutex -+** Pointer to the mutex to be released. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_ReleaseMutex( -+ IN gckOS Os, -+ IN gctPOINTER Mutex -+ ) -+{ -+ gcmkHEADER_ARG("Os=0x%X Mutex=0x%0x", Os, Mutex); -+ -+ /* Validate the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Mutex != gcvNULL); -+ -+ /* Release the mutex. */ -+ mutex_unlock(Mutex); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_AtomicExchange -+** -+** Atomically exchange a pair of 32-bit values. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** IN OUT gctINT32_PTR Target -+** Pointer to the 32-bit value to exchange. -+** -+** IN gctINT32 NewValue -+** Specifies a new value for the 32-bit value pointed to by Target. -+** -+** OUT gctINT32_PTR OldValue -+** The old value of the 32-bit value pointed to by Target. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_AtomicExchange( -+ IN gckOS Os, -+ IN OUT gctUINT32_PTR Target, -+ IN gctUINT32 NewValue, -+ OUT gctUINT32_PTR OldValue -+ ) -+{ -+ gcmkHEADER_ARG("Os=0x%X Target=0x%X NewValue=%u", Os, Target, NewValue); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(OldValue != gcvNULL); -+ -+ /* Exchange the pair of 32-bit values. */ -+ *OldValue = (gctUINT32) atomic_xchg((atomic_t *) Target, (int) NewValue); -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*OldValue=%u", *OldValue); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_AtomicExchangePtr -+** -+** Atomically exchange a pair of pointers. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** IN OUT gctPOINTER * Target -+** Pointer to the 32-bit value to exchange. -+** -+** IN gctPOINTER NewValue -+** Specifies a new value for the pointer pointed to by Target. -+** -+** OUT gctPOINTER * OldValue -+** The old value of the pointer pointed to by Target. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_AtomicExchangePtr( -+ IN gckOS Os, -+ IN OUT gctPOINTER * Target, -+ IN gctPOINTER NewValue, -+ OUT gctPOINTER * OldValue -+ ) -+{ -+ gcmkHEADER_ARG("Os=0x%X Target=0x%X NewValue=0x%X", Os, Target, NewValue); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(OldValue != gcvNULL); -+ -+ /* Exchange the pair of pointers. */ -+ *OldValue = (gctPOINTER)(gctUINTPTR_T) atomic_xchg((atomic_t *) Target, (int)(gctUINTPTR_T) NewValue); -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*OldValue=0x%X", *OldValue); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_AtomicSetMask -+** -+** Atomically set mask to Atom -+** -+** INPUT: -+** IN OUT gctPOINTER Atom -+** Pointer to the atom to set. -+** -+** IN gctUINT32 Mask -+** Mask to set. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_AtomSetMask( -+ IN gctPOINTER Atom, -+ IN gctUINT32 Mask -+ ) -+{ -+ gctUINT32 oval, nval; -+ -+ gcmkHEADER_ARG("Atom=0x%0x", Atom); -+ gcmkVERIFY_ARGUMENT(Atom != gcvNULL); -+ -+ do -+ { -+ oval = atomic_read((atomic_t *) Atom); -+ nval = oval | Mask; -+ } while (atomic_cmpxchg((atomic_t *) Atom, oval, nval) != oval); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_AtomClearMask -+** -+** Atomically clear mask from Atom -+** -+** INPUT: -+** IN OUT gctPOINTER Atom -+** Pointer to the atom to clear. -+** -+** IN gctUINT32 Mask -+** Mask to clear. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_AtomClearMask( -+ IN gctPOINTER Atom, -+ IN gctUINT32 Mask -+ ) -+{ -+ gctUINT32 oval, nval; -+ -+ gcmkHEADER_ARG("Atom=0x%0x", Atom); -+ gcmkVERIFY_ARGUMENT(Atom != gcvNULL); -+ -+ do -+ { -+ oval = atomic_read((atomic_t *) Atom); -+ nval = oval & ~Mask; -+ } while (atomic_cmpxchg((atomic_t *) Atom, oval, nval) != oval); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_AtomConstruct -+** -+** Create an atom. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to a gckOS object. -+** -+** OUTPUT: -+** -+** gctPOINTER * Atom -+** Pointer to a variable receiving the constructed atom. -+*/ -+gceSTATUS -+gckOS_AtomConstruct( -+ IN gckOS Os, -+ OUT gctPOINTER * Atom -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Os=0x%X", Os); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Atom != gcvNULL); -+ -+ /* Allocate the atom. */ -+ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(atomic_t), Atom)); -+ -+ /* Initialize the atom. */ -+ atomic_set((atomic_t *) *Atom, 0); -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Atom=0x%X", *Atom); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckOS_AtomDestroy -+** -+** Destroy an atom. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to a gckOS object. -+** -+** gctPOINTER Atom -+** Pointer to the atom to destroy. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_AtomDestroy( -+ IN gckOS Os, -+ OUT gctPOINTER Atom -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Os=0x%X Atom=0x%0x", Os, Atom); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Atom != gcvNULL); -+ -+ /* Free the atom. */ -+ gcmkONERROR(gcmkOS_SAFE_FREE(Os, Atom)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckOS_AtomGet -+** -+** Get the 32-bit value protected by an atom. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to a gckOS object. -+** -+** gctPOINTER Atom -+** Pointer to the atom. -+** -+** OUTPUT: -+** -+** gctINT32_PTR Value -+** Pointer to a variable the receives the value of the atom. -+*/ -+gceSTATUS -+gckOS_AtomGet( -+ IN gckOS Os, -+ IN gctPOINTER Atom, -+ OUT gctINT32_PTR Value -+ ) -+{ -+ gcmkHEADER_ARG("Os=0x%X Atom=0x%0x", Os, Atom); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Atom != gcvNULL); -+ -+ /* Return the current value of atom. */ -+ *Value = atomic_read((atomic_t *) Atom); -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Value=%d", *Value); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_AtomSet -+** -+** Set the 32-bit value protected by an atom. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to a gckOS object. -+** -+** gctPOINTER Atom -+** Pointer to the atom. -+** -+** gctINT32 Value -+** The value of the atom. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_AtomSet( -+ IN gckOS Os, -+ IN gctPOINTER Atom, -+ IN gctINT32 Value -+ ) -+{ -+ gcmkHEADER_ARG("Os=0x%X Atom=0x%0x Value=%d", Os, Atom); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Atom != gcvNULL); -+ -+ /* Set the current value of atom. */ -+ atomic_set((atomic_t *) Atom, Value); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_AtomIncrement -+** -+** Atomically increment the 32-bit integer value inside an atom. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to a gckOS object. -+** -+** gctPOINTER Atom -+** Pointer to the atom. -+** -+** OUTPUT: -+** -+** gctINT32_PTR Value -+** Pointer to a variable that receives the original value of the atom. -+*/ -+gceSTATUS -+gckOS_AtomIncrement( -+ IN gckOS Os, -+ IN gctPOINTER Atom, -+ OUT gctINT32_PTR Value -+ ) -+{ -+ gcmkHEADER_ARG("Os=0x%X Atom=0x%0x", Os, Atom); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Atom != gcvNULL); -+ -+ /* Increment the atom. */ -+ *Value = atomic_inc_return((atomic_t *) Atom) - 1; -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Value=%d", *Value); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_AtomDecrement -+** -+** Atomically decrement the 32-bit integer value inside an atom. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to a gckOS object. -+** -+** gctPOINTER Atom -+** Pointer to the atom. -+** -+** OUTPUT: -+** -+** gctINT32_PTR Value -+** Pointer to a variable that receives the original value of the atom. -+*/ -+gceSTATUS -+gckOS_AtomDecrement( -+ IN gckOS Os, -+ IN gctPOINTER Atom, -+ OUT gctINT32_PTR Value -+ ) -+{ -+ gcmkHEADER_ARG("Os=0x%X Atom=0x%0x", Os, Atom); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Atom != gcvNULL); -+ -+ /* Decrement the atom. */ -+ *Value = atomic_dec_return((atomic_t *) Atom) + 1; -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Value=%d", *Value); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_Delay -+** -+** Delay execution of the current thread for a number of milliseconds. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctUINT32 Delay -+** Delay to sleep, specified in milliseconds. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_Delay( -+ IN gckOS Os, -+ IN gctUINT32 Delay -+ ) -+{ -+ gcmkHEADER_ARG("Os=0x%X Delay=%u", Os, Delay); -+ -+ if (Delay > 0) -+ { -+ ktime_t delay = ktime_set((Delay / MSEC_PER_SEC), (Delay % MSEC_PER_SEC) * NSEC_PER_MSEC); -+ __set_current_state(TASK_UNINTERRUPTIBLE); -+ schedule_hrtimeout(&delay, HRTIMER_MODE_REL); -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_GetTicks -+** -+** Get the number of milliseconds since the system started. -+** -+** INPUT: -+** -+** OUTPUT: -+** -+** gctUINT32_PTR Time -+** Pointer to a variable to get time. -+** -+*/ -+gceSTATUS -+gckOS_GetTicks( -+ OUT gctUINT32_PTR Time -+ ) -+{ -+ gcmkHEADER(); -+ -+ *Time = jiffies_to_msecs(jiffies); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_TicksAfter -+** -+** Compare time values got from gckOS_GetTicks. -+** -+** INPUT: -+** gctUINT32 Time1 -+** First time value to be compared. -+** -+** gctUINT32 Time2 -+** Second time value to be compared. -+** -+** OUTPUT: -+** -+** gctBOOL_PTR IsAfter -+** Pointer to a variable to result. -+** -+*/ -+gceSTATUS -+gckOS_TicksAfter( -+ IN gctUINT32 Time1, -+ IN gctUINT32 Time2, -+ OUT gctBOOL_PTR IsAfter -+ ) -+{ -+ gcmkHEADER(); -+ -+ *IsAfter = time_after((unsigned long)Time1, (unsigned long)Time2); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_GetTime -+** -+** Get the number of microseconds since the system started. -+** -+** INPUT: -+** -+** OUTPUT: -+** -+** gctUINT64_PTR Time -+** Pointer to a variable to get time. -+** -+*/ -+gceSTATUS -+gckOS_GetTime( -+ OUT gctUINT64_PTR Time -+ ) -+{ -+ struct timeval tv; -+ gcmkHEADER(); -+ -+ /* Return the time of day in microseconds. */ -+ do_gettimeofday(&tv); -+ *Time = (tv.tv_sec * 1000000ULL) + tv.tv_usec; -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_MemoryBarrier -+** -+** Make sure the CPU has executed everything up to this point and the data got -+** written to the specified pointer. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctPOINTER Address -+** Address of memory that needs to be barriered. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_MemoryBarrier( -+ IN gckOS Os, -+ IN gctPOINTER Address -+ ) -+{ -+ gcmkHEADER_ARG("Os=0x%X Address=0x%X", Os, Address); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ -+ mb(); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_AllocatePagedMemory -+** -+** Allocate memory from the paged pool. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctSIZE_T Bytes -+** Number of bytes to allocate. -+** -+** OUTPUT: -+** -+** gctPHYS_ADDR * Physical -+** Pointer to a variable that receives the physical address of the -+** memory allocation. -+*/ -+gceSTATUS -+gckOS_AllocatePagedMemory( -+ IN gckOS Os, -+ IN gctSIZE_T Bytes, -+ OUT gctPHYS_ADDR * Physical -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Os=0x%X Bytes=%lu", Os, Bytes); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Bytes > 0); -+ gcmkVERIFY_ARGUMENT(Physical != gcvNULL); -+ -+ /* Allocate the memory. */ -+ gcmkONERROR(gckOS_AllocatePagedMemoryEx(Os, gcvALLOC_FLAG_NONE, Bytes, gcvNULL, Physical)); -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Physical=0x%X", *Physical); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckOS_AllocatePagedMemoryEx -+** -+** Allocate memory from the paged pool. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctUINT32 Flag -+** Allocation attribute. -+** -+** gctSIZE_T Bytes -+** Number of bytes to allocate. -+** -+** OUTPUT: -+** -+** gctUINT32 * Gid -+** Save the global ID for the piece of allocated memory. -+** -+** gctPHYS_ADDR * Physical -+** Pointer to a variable that receives the physical address of the -+** memory allocation. -+*/ -+gceSTATUS -+gckOS_AllocatePagedMemoryEx( -+ IN gckOS Os, -+ IN gctUINT32 Flag, -+ IN gctSIZE_T Bytes, -+ OUT gctUINT32 * Gid, -+ OUT gctPHYS_ADDR * Physical -+ ) -+{ -+ gctINT numPages; -+ PLINUX_MDL mdl = gcvNULL; -+ gctSIZE_T bytes; -+ gceSTATUS status = gcvSTATUS_OUT_OF_MEMORY; -+ gckALLOCATOR allocator; -+ -+ gcmkHEADER_ARG("Os=0x%X Flag=%x Bytes=%lu", Os, Flag, Bytes); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Bytes > 0); -+ gcmkVERIFY_ARGUMENT(Physical != gcvNULL); -+ -+ bytes = gcmALIGN(Bytes, PAGE_SIZE); -+ -+ numPages = GetPageCount(bytes, 0); -+ -+ mdl = _CreateMdl(); -+ if (mdl == gcvNULL) -+ { -+ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); -+ } -+ -+ /* Walk all allocators. */ -+ list_for_each_entry(allocator, &Os->allocatorList, head) -+ { -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_OS, -+ "%s(%d) flag = %x allocator->capability = %x", -+ __FUNCTION__, __LINE__, Flag, allocator->capability); -+ -+ if ((Flag & allocator->capability) != Flag) -+ { -+ continue; -+ } -+ -+ status = allocator->ops->Alloc(allocator, mdl, numPages, Flag); -+ -+ if (gcmIS_SUCCESS(status)) -+ { -+ mdl->allocator = allocator; -+ break; -+ } -+ } -+ -+ /* Check status. */ -+ gcmkONERROR(status); -+ -+ mdl->dmaHandle = 0; -+ mdl->addr = 0; -+ mdl->numPages = numPages; -+ mdl->pagedMem = 1; -+ mdl->contiguous = Flag & gcvALLOC_FLAG_CONTIGUOUS; -+ -+ if (Gid != gcvNULL) -+ { -+ *Gid = mdl->gid; -+ } -+ -+ MEMORY_LOCK(Os); -+ -+ /* -+ * Add this to a global list. -+ * Will be used by get physical address -+ * and mapuser pointer functions. -+ */ -+ if (!Os->mdlHead) -+ { -+ /* Initialize the queue. */ -+ Os->mdlHead = Os->mdlTail = mdl; -+ } -+ else -+ { -+ /* Add to tail. */ -+ mdl->prev = Os->mdlTail; -+ Os->mdlTail->next = mdl; -+ Os->mdlTail = mdl; -+ } -+ -+ MEMORY_UNLOCK(Os); -+ -+ /* Return physical address. */ -+ *Physical = (gctPHYS_ADDR) mdl; -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Physical=0x%X", *Physical); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (mdl != gcvNULL) -+ { -+ /* Free the memory. */ -+ _DestroyMdl(mdl); -+ } -+ *Physical = gcvNULL; -+ -+ /* Return the status. */ -+ gcmkFOOTER_ARG("Os=0x%X Flag=%x Bytes=%lu", Os, Flag, Bytes); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckOS_FreePagedMemory -+** -+** Free memory allocated from the paged pool. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctPHYS_ADDR Physical -+** Physical address of the allocation. -+** -+** gctSIZE_T Bytes -+** Number of bytes of the allocation. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_FreePagedMemory( -+ IN gckOS Os, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T Bytes -+ ) -+{ -+ PLINUX_MDL mdl = (PLINUX_MDL) Physical; -+ gckALLOCATOR allocator = (gckALLOCATOR)mdl->allocator; -+ -+ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%lu", Os, Physical, Bytes); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Physical != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Bytes > 0); -+ -+ MEMORY_LOCK(Os); -+ -+ /* Remove the node from global list. */ -+ if (mdl == Os->mdlHead) -+ { -+ if ((Os->mdlHead = mdl->next) == gcvNULL) -+ { -+ Os->mdlTail = gcvNULL; -+ } -+ } -+ else -+ { -+ mdl->prev->next = mdl->next; -+ -+ if (mdl == Os->mdlTail) -+ { -+ Os->mdlTail = mdl->prev; -+ } -+ else -+ { -+ mdl->next->prev = mdl->prev; -+ } -+ } -+ -+ MEMORY_UNLOCK(Os); -+ -+ allocator->ops->Free(allocator, mdl); -+ -+ /* Free the structure... */ -+ gcmkVERIFY_OK(_DestroyMdl(mdl)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_LockPages -+** -+** Lock memory allocated from the paged pool. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctPHYS_ADDR Physical -+** Physical address of the allocation. -+** -+** gctSIZE_T Bytes -+** Number of bytes of the allocation. -+** -+** gctBOOL Cacheable -+** Cache mode of mapping. -+** -+** OUTPUT: -+** -+** gctPOINTER * Logical -+** Pointer to a variable that receives the address of the mapped -+** memory. -+** -+** gctSIZE_T * PageCount -+** Pointer to a variable that receives the number of pages required for -+** the page table according to the GPU page size. -+*/ -+gceSTATUS -+gckOS_LockPages( -+ IN gckOS Os, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T Bytes, -+ IN gctBOOL Cacheable, -+ OUT gctPOINTER * Logical, -+ OUT gctSIZE_T * PageCount -+ ) -+{ -+ gceSTATUS status; -+ PLINUX_MDL mdl; -+ PLINUX_MDL_MAP mdlMap; -+ gckALLOCATOR allocator; -+ -+ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%u", Os, Physical, Bytes); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Physical != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Logical != gcvNULL); -+ gcmkVERIFY_ARGUMENT(PageCount != gcvNULL); -+ -+ mdl = (PLINUX_MDL) Physical; -+ allocator = mdl->allocator; -+ -+ MEMORY_LOCK(Os); -+ -+ mdlMap = FindMdlMap(mdl, _GetProcessID()); -+ -+ if (mdlMap == gcvNULL) -+ { -+ mdlMap = _CreateMdlMap(mdl, _GetProcessID()); -+ -+ if (mdlMap == gcvNULL) -+ { -+ MEMORY_UNLOCK(Os); -+ -+ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY); -+ return gcvSTATUS_OUT_OF_MEMORY; -+ } -+ } -+ -+ if (mdlMap->vmaAddr == gcvNULL) -+ { -+ status = allocator->ops->MapUser(allocator, mdl, mdlMap, Cacheable); -+ -+ if (gcmIS_ERROR(status)) -+ { -+ MEMORY_UNLOCK(Os); -+ -+ gcmkFOOTER_ARG("*status=%d", status); -+ return status; -+ } -+ } -+ -+ mdlMap->count++; -+ -+ /* Convert pointer to MDL. */ -+ *Logical = mdlMap->vmaAddr; -+ -+ /* Return the page number according to the GPU page size. */ -+ gcmkASSERT((PAGE_SIZE / 4096) >= 1); -+ -+ *PageCount = mdl->numPages * (PAGE_SIZE / 4096); -+ -+ MEMORY_UNLOCK(Os); -+ -+ gcmkVERIFY_OK(gckOS_CacheFlush( -+ Os, -+ _GetProcessID(), -+ Physical, -+ gcvINVALID_ADDRESS, -+ (gctPOINTER)mdlMap->vmaAddr, -+ mdl->numPages * PAGE_SIZE -+ )); -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Logical=0x%X *PageCount=%lu", *Logical, *PageCount); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_MapPages -+** -+** Map paged memory into a page table. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctPHYS_ADDR Physical -+** Physical address of the allocation. -+** -+** gctSIZE_T PageCount -+** Number of pages required for the physical address. -+** -+** gctPOINTER PageTable -+** Pointer to the page table to fill in. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_MapPages( -+ IN gckOS Os, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T PageCount, -+ IN gctPOINTER PageTable -+ ) -+{ -+ return gckOS_MapPagesEx(Os, -+ gcvCORE_MAJOR, -+ Physical, -+ PageCount, -+ 0, -+ PageTable); -+} -+ -+gceSTATUS -+gckOS_MapPagesEx( -+ IN gckOS Os, -+ IN gceCORE Core, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T PageCount, -+ IN gctUINT32 Address, -+ IN gctPOINTER PageTable -+ ) -+{ -+ gceSTATUS status = gcvSTATUS_OK; -+ PLINUX_MDL mdl; -+ gctUINT32* table; -+ gctUINT32 offset; -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ gckMMU mmu; -+ PLINUX_MDL mmuMdl; -+ gctUINT32 bytes; -+ gctPHYS_ADDR pageTablePhysical; -+#endif -+ -+#if gcdPROCESS_ADDRESS_SPACE -+ gckKERNEL kernel = Os->device->kernels[Core]; -+ gckMMU mmu; -+#endif -+ gckALLOCATOR allocator; -+ -+ gcmkHEADER_ARG("Os=0x%X Core=%d Physical=0x%X PageCount=%u PageTable=0x%X", -+ Os, Core, Physical, PageCount, PageTable); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Physical != gcvNULL); -+ gcmkVERIFY_ARGUMENT(PageCount > 0); -+ gcmkVERIFY_ARGUMENT(PageTable != gcvNULL); -+ -+ /* Convert pointer to MDL. */ -+ mdl = (PLINUX_MDL)Physical; -+ -+ allocator = mdl->allocator; -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, gcvZONE_OS, -+ "%s(%d): Physical->0x%X PageCount->0x%X PagedMemory->?%d", -+ __FUNCTION__, __LINE__, -+ (gctUINT32)(gctUINTPTR_T)Physical, -+ (gctUINT32)(gctUINTPTR_T)PageCount, -+ mdl->pagedMem -+ ); -+ -+#if gcdPROCESS_ADDRESS_SPACE -+ gcmkONERROR(gckKERNEL_GetProcessMMU(kernel, &mmu)); -+#endif -+ -+ table = (gctUINT32 *)PageTable; -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ mmu = Os->device->kernels[Core]->mmu; -+ bytes = PageCount * sizeof(*table); -+ mmuMdl = (PLINUX_MDL)mmu->pageTablePhysical; -+#endif -+ -+ /* Get all the physical addresses and store them in the page table. */ -+ -+ offset = 0; -+ PageCount = PageCount / (PAGE_SIZE / 4096); -+ -+ /* Try to get the user pages so DMA can happen. */ -+ while (PageCount-- > 0) -+ { -+ gctUINT i; -+ gctUINT32 phys = ~0; -+ -+ if (mdl->pagedMem && !mdl->contiguous) -+ { -+ allocator->ops->Physical(allocator, mdl, offset, &phys); -+ } -+ else -+ { -+ if (!mdl->pagedMem) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, gcvZONE_OS, -+ "%s(%d): we should not get this call for Non Paged Memory!", -+ __FUNCTION__, __LINE__ -+ ); -+ } -+ -+ phys = page_to_phys(nth_page(mdl->u.contiguousPages, offset)); -+ } -+ -+ gcmkVERIFY_OK(gckOS_CPUPhysicalToGPUPhysical(Os, phys, &phys)); -+ -+#ifdef CONFIG_IOMMU_SUPPORT -+ if (Os->iommu) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, gcvZONE_OS, -+ "%s(%d): Setup mapping in IOMMU %x => %x", -+ __FUNCTION__, __LINE__, -+ Address + (offset * PAGE_SIZE), phys -+ ); -+ -+ /* When use IOMMU, GPU use system PAGE_SIZE. */ -+ gcmkONERROR(gckIOMMU_Map( -+ Os->iommu, Address + (offset * PAGE_SIZE), phys, PAGE_SIZE)); -+ } -+ else -+#endif -+ { -+ -+#if gcdENABLE_VG -+ if (Core == gcvCORE_VG) -+ { -+ for (i = 0; i < (PAGE_SIZE / 4096); i++) -+ { -+ gcmkONERROR( -+ gckVGMMU_SetPage(Os->device->kernels[Core]->vg->mmu, -+ phys + (i * 4096), -+ table++)); -+ } -+ } -+ else -+#endif -+ { -+ for (i = 0; i < (PAGE_SIZE / 4096); i++) -+ { -+#if gcdPROCESS_ADDRESS_SPACE -+ gctUINT32_PTR pageTableEntry; -+ gckMMU_GetPageEntry(mmu, Address + (offset * 4096), &pageTableEntry); -+ gcmkONERROR( -+ gckMMU_SetPage(mmu, -+ phys + (i * 4096), -+ pageTableEntry)); -+#else -+ gcmkONERROR( -+ gckMMU_SetPage(Os->device->kernels[Core]->mmu, -+ phys + (i * 4096), -+ table++)); -+#endif -+ } -+ } -+ } -+ -+ offset += 1; -+ } -+ -+#if gcdNONPAGED_MEMORY_CACHEABLE -+ /* Get physical address of pageTable */ -+ pageTablePhysical = (gctPHYS_ADDR)(mmuMdl->dmaHandle + -+ ((gctUINT32 *)PageTable - mmu->pageTableLogical)); -+ -+ /* Flush the mmu page table cache. */ -+ gcmkONERROR(gckOS_CacheClean( -+ Os, -+ _GetProcessID(), -+ gcvNULL, -+ pageTablePhysical, -+ PageTable, -+ bytes -+ )); -+#endif -+ -+OnError: -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckOS_UnmapPages( -+ IN gckOS Os, -+ IN gctSIZE_T PageCount, -+ IN gctUINT32 Address -+ ) -+{ -+#ifdef CONFIG_IOMMU_SUPPORT -+ if (Os->iommu) -+ { -+ gcmkVERIFY_OK(gckIOMMU_Unmap( -+ Os->iommu, Address, PageCount * PAGE_SIZE)); -+ } -+#endif -+ -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_UnlockPages -+** -+** Unlock memory allocated from the paged pool. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctPHYS_ADDR Physical -+** Physical address of the allocation. -+** -+** gctSIZE_T Bytes -+** Number of bytes of the allocation. -+** -+** gctPOINTER Logical -+** Address of the mapped memory. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_UnlockPages( -+ IN gckOS Os, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T Bytes, -+ IN gctPOINTER Logical -+ ) -+{ -+ PLINUX_MDL_MAP mdlMap; -+ PLINUX_MDL mdl = (PLINUX_MDL)Physical; -+ gckALLOCATOR allocator = mdl->allocator; -+ -+ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Bytes=%u Logical=0x%X", -+ Os, Physical, Bytes, Logical); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Physical != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Logical != gcvNULL); -+ -+ MEMORY_LOCK(Os); -+ -+ mdlMap = mdl->maps; -+ -+ while (mdlMap != gcvNULL) -+ { -+ if ((mdlMap->vmaAddr != gcvNULL) && (_GetProcessID() == mdlMap->pid)) -+ { -+ if (--mdlMap->count == 0) -+ { -+ allocator->ops->UnmapUser( -+ allocator, -+ mdlMap->vmaAddr, -+ mdl->numPages * PAGE_SIZE); -+ -+ mdlMap->vmaAddr = gcvNULL; -+ } -+ } -+ -+ mdlMap = mdlMap->next; -+ } -+ -+ MEMORY_UNLOCK(Os); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+ -+/******************************************************************************* -+** -+** gckOS_AllocateContiguous -+** -+** Allocate memory from the contiguous pool. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctBOOL InUserSpace -+** gcvTRUE if the pages need to be mapped into user space. -+** -+** gctSIZE_T * Bytes -+** Pointer to the number of bytes to allocate. -+** -+** OUTPUT: -+** -+** gctSIZE_T * Bytes -+** Pointer to a variable that receives the number of bytes allocated. -+** -+** gctPHYS_ADDR * Physical -+** Pointer to a variable that receives the physical address of the -+** memory allocation. -+** -+** gctPOINTER * Logical -+** Pointer to a variable that receives the logical address of the -+** memory allocation. -+*/ -+gceSTATUS -+gckOS_AllocateContiguous( -+ IN gckOS Os, -+ IN gctBOOL InUserSpace, -+ IN OUT gctSIZE_T * Bytes, -+ OUT gctPHYS_ADDR * Physical, -+ OUT gctPOINTER * Logical -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Os=0x%X InUserSpace=%d *Bytes=%lu", -+ Os, InUserSpace, gcmOPT_VALUE(Bytes)); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Bytes != gcvNULL); -+ gcmkVERIFY_ARGUMENT(*Bytes > 0); -+ gcmkVERIFY_ARGUMENT(Physical != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Logical != gcvNULL); -+ -+ /* Same as non-paged memory for now. */ -+ gcmkONERROR(gckOS_AllocateNonPagedMemory(Os, -+ InUserSpace, -+ Bytes, -+ Physical, -+ Logical)); -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Bytes=%lu *Physical=0x%X *Logical=0x%X", -+ *Bytes, *Physical, *Logical); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckOS_FreeContiguous -+** -+** Free memory allocated from the contiguous pool. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctPHYS_ADDR Physical -+** Physical address of the allocation. -+** -+** gctPOINTER Logical -+** Logicval address of the allocation. -+** -+** gctSIZE_T Bytes -+** Number of bytes of the allocation. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_FreeContiguous( -+ IN gckOS Os, -+ IN gctPHYS_ADDR Physical, -+ IN gctPOINTER Logical, -+ IN gctSIZE_T Bytes -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Os=0x%X Physical=0x%X Logical=0x%X Bytes=%lu", -+ Os, Physical, Logical, Bytes); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Physical != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Logical != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Bytes > 0); -+ -+ /* Same of non-paged memory for now. */ -+ gcmkONERROR(gckOS_FreeNonPagedMemory(Os, Bytes, Physical, Logical)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+#if gcdENABLE_VG -+/****************************************************************************** -+** -+** gckOS_GetKernelLogical -+** -+** Return the kernel logical pointer that corresponods to the specified -+** hardware address. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctUINT32 Address -+** Hardware physical address. -+** -+** OUTPUT: -+** -+** gctPOINTER * KernelPointer -+** Pointer to a variable receiving the pointer in kernel address space. -+*/ -+gceSTATUS -+gckOS_GetKernelLogical( -+ IN gckOS Os, -+ IN gctUINT32 Address, -+ OUT gctPOINTER * KernelPointer -+ ) -+{ -+ return gckOS_GetKernelLogicalEx(Os, gcvCORE_MAJOR, Address, KernelPointer); -+} -+ -+gceSTATUS -+gckOS_GetKernelLogicalEx( -+ IN gckOS Os, -+ IN gceCORE Core, -+ IN gctUINT32 Address, -+ OUT gctPOINTER * KernelPointer -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Os=0x%X Core=%d Address=0x%08x", Os, Core, Address); -+ -+ do -+ { -+ gckGALDEVICE device; -+ gckKERNEL kernel; -+ gcePOOL pool; -+ gctUINT32 offset; -+ gctPOINTER logical; -+ -+ /* Extract the pointer to the gckGALDEVICE class. */ -+ device = (gckGALDEVICE) Os->device; -+ -+ /* Kernel shortcut. */ -+ kernel = device->kernels[Core]; -+#if gcdENABLE_VG -+ if (Core == gcvCORE_VG) -+ { -+ gcmkERR_BREAK(gckVGHARDWARE_SplitMemory( -+ kernel->vg->hardware, Address, &pool, &offset -+ )); -+ } -+ else -+#endif -+ { -+ /* Split the memory address into a pool type and offset. */ -+ gcmkERR_BREAK(gckHARDWARE_SplitMemory( -+ kernel->hardware, Address, &pool, &offset -+ )); -+ } -+ -+ /* Dispatch on pool. */ -+ switch (pool) -+ { -+ case gcvPOOL_LOCAL_INTERNAL: -+ /* Internal memory. */ -+ logical = device->internalLogical; -+ break; -+ -+ case gcvPOOL_LOCAL_EXTERNAL: -+ /* External memory. */ -+ logical = device->externalLogical; -+ break; -+ -+ case gcvPOOL_SYSTEM: -+ /* System memory. */ -+ logical = device->contiguousBase; -+ break; -+ -+ default: -+ /* Invalid memory pool. */ -+ gcmkFOOTER(); -+ return gcvSTATUS_INVALID_ARGUMENT; -+ } -+ -+ /* Build logical address of specified address. */ -+ * KernelPointer = ((gctUINT8_PTR) logical) + offset; -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*KernelPointer=0x%X", *KernelPointer); -+ return gcvSTATUS_OK; -+ } -+ while (gcvFALSE); -+ -+ /* Return status. */ -+ gcmkFOOTER(); -+ return status; -+} -+#endif -+ -+/******************************************************************************* -+** -+** gckOS_MapUserPointer -+** -+** Map a pointer from the user process into the kernel address space. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctPOINTER Pointer -+** Pointer in user process space that needs to be mapped. -+** -+** gctSIZE_T Size -+** Number of bytes that need to be mapped. -+** -+** OUTPUT: -+** -+** gctPOINTER * KernelPointer -+** Pointer to a variable receiving the mapped pointer in kernel address -+** space. -+*/ -+gceSTATUS -+gckOS_MapUserPointer( -+ IN gckOS Os, -+ IN gctPOINTER Pointer, -+ IN gctSIZE_T Size, -+ OUT gctPOINTER * KernelPointer -+ ) -+{ -+ gctPOINTER buf = gcvNULL; -+ gctUINT32 len; -+ -+ gcmkHEADER_ARG("Os=0x%X Pointer=0x%X Size=%lu", Os, Pointer, Size); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Size > 0); -+ gcmkVERIFY_ARGUMENT(KernelPointer != gcvNULL); -+ -+ buf = kmalloc(Size, GFP_KERNEL | gcdNOWARN); -+ if (buf == gcvNULL) -+ { -+ gcmkTRACE( -+ gcvLEVEL_ERROR, -+ "%s(%d): Failed to allocate memory.", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_OUT_OF_MEMORY); -+ return gcvSTATUS_OUT_OF_MEMORY; -+ } -+ -+ len = copy_from_user(buf, Pointer, Size); -+ if (len != 0) -+ { -+ gcmkTRACE( -+ gcvLEVEL_ERROR, -+ "%s(%d): Failed to copy data from user.", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ if (buf != gcvNULL) -+ { -+ kfree(buf); -+ } -+ -+ gcmkFOOTER_ARG("*status=%d", gcvSTATUS_GENERIC_IO); -+ return gcvSTATUS_GENERIC_IO; -+ } -+ -+ *KernelPointer = buf; -+ -+ gcmkFOOTER_ARG("*KernelPointer=0x%X", *KernelPointer); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_UnmapUserPointer -+** -+** Unmap a user process pointer from the kernel address space. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctPOINTER Pointer -+** Pointer in user process space that needs to be unmapped. -+** -+** gctSIZE_T Size -+** Number of bytes that need to be unmapped. -+** -+** gctPOINTER KernelPointer -+** Pointer in kernel address space that needs to be unmapped. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_UnmapUserPointer( -+ IN gckOS Os, -+ IN gctPOINTER Pointer, -+ IN gctSIZE_T Size, -+ IN gctPOINTER KernelPointer -+ ) -+{ -+ gctUINT32 len; -+ -+ gcmkHEADER_ARG("Os=0x%X Pointer=0x%X Size=%lu KernelPointer=0x%X", -+ Os, Pointer, Size, KernelPointer); -+ -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Size > 0); -+ gcmkVERIFY_ARGUMENT(KernelPointer != gcvNULL); -+ -+ len = copy_to_user(Pointer, KernelPointer, Size); -+ -+ kfree(KernelPointer); -+ -+ if (len != 0) -+ { -+ gcmkTRACE( -+ gcvLEVEL_ERROR, -+ "%s(%d): Failed to copy data to user.", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ gcmkFOOTER_ARG("status=%d", gcvSTATUS_GENERIC_IO); -+ return gcvSTATUS_GENERIC_IO; -+ } -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_QueryNeedCopy -+** -+** Query whether the memory can be accessed or mapped directly or it has to be -+** copied. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctUINT32 ProcessID -+** Process ID of the current process. -+** -+** OUTPUT: -+** -+** gctBOOL_PTR NeedCopy -+** Pointer to a boolean receiving gcvTRUE if the memory needs a copy or -+** gcvFALSE if the memory can be accessed or mapped dircetly. -+*/ -+gceSTATUS -+gckOS_QueryNeedCopy( -+ IN gckOS Os, -+ IN gctUINT32 ProcessID, -+ OUT gctBOOL_PTR NeedCopy -+ ) -+{ -+ gcmkHEADER_ARG("Os=0x%X ProcessID=%d", Os, ProcessID); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(NeedCopy != gcvNULL); -+ -+ /* We need to copy data. */ -+ *NeedCopy = gcvTRUE; -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*NeedCopy=%d", *NeedCopy); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_CopyFromUserData -+** -+** Copy data from user to kernel memory. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctPOINTER KernelPointer -+** Pointer to kernel memory. -+** -+** gctPOINTER Pointer -+** Pointer to user memory. -+** -+** gctSIZE_T Size -+** Number of bytes to copy. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_CopyFromUserData( -+ IN gckOS Os, -+ IN gctPOINTER KernelPointer, -+ IN gctPOINTER Pointer, -+ IN gctSIZE_T Size -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Os=0x%X KernelPointer=0x%X Pointer=0x%X Size=%lu", -+ Os, KernelPointer, Pointer, Size); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(KernelPointer != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Size > 0); -+ -+ /* Copy data from user. */ -+ if (copy_from_user(KernelPointer, Pointer, Size) != 0) -+ { -+ /* Could not copy all the bytes. */ -+ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES); -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckOS_CopyToUserData -+** -+** Copy data from kernel to user memory. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctPOINTER KernelPointer -+** Pointer to kernel memory. -+** -+** gctPOINTER Pointer -+** Pointer to user memory. -+** -+** gctSIZE_T Size -+** Number of bytes to copy. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_CopyToUserData( -+ IN gckOS Os, -+ IN gctPOINTER KernelPointer, -+ IN gctPOINTER Pointer, -+ IN gctSIZE_T Size -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Os=0x%X KernelPointer=0x%X Pointer=0x%X Size=%lu", -+ Os, KernelPointer, Pointer, Size); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(KernelPointer != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Pointer != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Size > 0); -+ -+ /* Copy data to user. */ -+ if (copy_to_user(Pointer, KernelPointer, Size) != 0) -+ { -+ /* Could not copy all the bytes. */ -+ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES); -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckOS_WriteMemory -+** -+** Write data to a memory. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctPOINTER Address -+** Address of the memory to write to. -+** -+** gctUINT32 Data -+** Data for register. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_WriteMemory( -+ IN gckOS Os, -+ IN gctPOINTER Address, -+ IN gctUINT32 Data -+ ) -+{ -+ gceSTATUS status; -+ gcmkHEADER_ARG("Os=0x%X Address=0x%X Data=%u", Os, Address, Data); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_ARGUMENT(Address != gcvNULL); -+ -+ /* Write memory. */ -+ if (access_ok(VERIFY_WRITE, Address, 4)) -+ { -+ /* User address. */ -+ if(put_user(Data, (gctUINT32*)Address)) -+ { -+ gcmkONERROR(gcvSTATUS_INVALID_ADDRESS); -+ } -+ } -+ else -+ { -+ /* Kernel address. */ -+ *(gctUINT32 *)Address = Data; -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckOS_MapUserMemory -+** -+** Lock down a user buffer and return an DMA'able address to be used by the -+** hardware to access it. -+** -+** INPUT: -+** -+** gctPOINTER Memory -+** Pointer to memory to lock down. -+** -+** gctSIZE_T Size -+** Size in bytes of the memory to lock down. -+** -+** OUTPUT: -+** -+** gctPOINTER * Info -+** Pointer to variable receiving the information record required by -+** gckOS_UnmapUserMemory. -+** -+** gctUINT32_PTR Address -+** Pointer to a variable that will receive the address DMA'able by the -+** hardware. -+*/ -+gceSTATUS -+gckOS_MapUserMemory( -+ IN gckOS Os, -+ IN gceCORE Core, -+ IN gctPOINTER Memory, -+ IN gctUINT32 Physical, -+ IN gctSIZE_T Size, -+ OUT gctPOINTER * Info, -+ OUT gctUINT32_PTR Address -+ ) -+{ -+ gceSTATUS status; -+ gctSIZE_T pageCount, i, j; -+ gctUINT32_PTR pageTable; -+ gctUINT32 address = 0, physical = ~0U; -+ gctUINTPTR_T start, end, memory; -+ gctUINT32 offset; -+ gctINT result = 0; -+#if gcdPROCESS_ADDRESS_SPACE -+ gckMMU mmu; -+#endif -+ -+ gcsPageInfo_PTR info = gcvNULL; -+ struct page **pages = gcvNULL; -+ -+ gcmkHEADER_ARG("Os=0x%x Core=%d Memory=0x%x Size=%lu", Os, Core, Memory, Size); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Memory != gcvNULL || Physical != ~0U); -+ gcmkVERIFY_ARGUMENT(Size > 0); -+ gcmkVERIFY_ARGUMENT(Info != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Address != gcvNULL); -+ -+ do -+ { -+ gctSIZE_T extraPage; -+ -+ memory = (gctUINTPTR_T) Memory; -+ -+ /* Get the number of required pages. */ -+ end = (memory + Size + PAGE_SIZE - 1) >> PAGE_SHIFT; -+ start = memory >> PAGE_SHIFT; -+ pageCount = end - start; -+ -+ /* Allocate extra 64 bytes to avoid cache overflow */ -+ extraPage = (((memory + gcmALIGN(Size + 64, 64) + PAGE_SIZE - 1) >> PAGE_SHIFT) > end) ? 1 : 0; -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, gcvZONE_OS, -+ "%s(%d): pageCount: %d.", -+ __FUNCTION__, __LINE__, -+ pageCount -+ ); -+ -+ /* Overflow. */ -+ if ((memory + Size) < memory) -+ { -+ gcmkFOOTER_ARG("status=%d", gcvSTATUS_INVALID_ARGUMENT); -+ return gcvSTATUS_INVALID_ARGUMENT; -+ } -+ -+ MEMORY_MAP_LOCK(Os); -+ -+ /* Allocate the Info struct. */ -+ info = (gcsPageInfo_PTR)kmalloc(sizeof(gcsPageInfo), GFP_KERNEL | gcdNOWARN); -+ -+ if (info == gcvNULL) -+ { -+ status = gcvSTATUS_OUT_OF_MEMORY; -+ break; -+ } -+ -+ info->extraPage = 0; -+ -+ /* Allocate the array of page addresses. */ -+ pages = (struct page **)kmalloc((pageCount + extraPage) * sizeof(struct page *), GFP_KERNEL | gcdNOWARN); -+ -+ if (pages == gcvNULL) -+ { -+ status = gcvSTATUS_OUT_OF_MEMORY; -+ break; -+ } -+ -+ if (Physical != ~0U) -+ { -+ unsigned long pfn = Physical >> PAGE_SHIFT; -+ for (i = 0; i < pageCount; i++) -+ { -+ if (!pfn_valid(pfn + i)) -+ { -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ } -+ } -+ -+ for (i = 0; i < pageCount; i++) -+ { -+ pages[i] = pfn_to_page(pfn + i); -+ get_page(pages[i]); -+ } -+ } -+ else -+ { -+ /* Get the user pages. */ -+ down_read(¤t->mm->mmap_sem); -+ -+ result = get_user_pages(current, -+ current->mm, -+ memory & PAGE_MASK, -+ pageCount, -+ 1, -+ 0, -+ pages, -+ gcvNULL -+ ); -+ -+ up_read(¤t->mm->mmap_sem); -+ -+ if (result <=0 || result < pageCount) -+ { -+ struct vm_area_struct *vma; -+ -+ /* Release the pages if any. */ -+ if (result > 0) -+ { -+ for (i = 0; i < result; i++) -+ { -+ if (pages[i] != gcvNULL) -+ { -+ page_cache_release(pages[i]); -+ pages[i] = gcvNULL; -+ } -+ } -+ -+ result = 0; -+ } -+ -+ vma = find_vma(current->mm, memory); -+ -+ if (vma && (vma->vm_flags & VM_PFNMAP)) -+ { -+ pte_t * pte; -+ spinlock_t * ptl; -+ gctUINTPTR_T logical = memory; -+ -+ for (i = 0; i < pageCount; i++) -+ { -+ pgd_t * pgd = pgd_offset(current->mm, logical); -+ pud_t * pud = pud_offset(pgd, logical); -+ unsigned long pfn; -+ -+ if (pud) -+ { -+ pmd_t * pmd = pmd_offset(pud, logical); -+ pte = pte_offset_map_lock(current->mm, pmd, logical, &ptl); -+ if (!pte) -+ { -+ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES); -+ } -+ } -+ else -+ { -+ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES); -+ } -+ -+ if (pte_present(*pte)) -+ pfn = pte_pfn(*pte); -+ else -+ pfn = ~0UL; -+ pte_unmap_unlock(pte, ptl); -+ -+ if (pfn == ~0UL || !pfn_valid(pfn)) -+ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES); -+ -+ pages[i] = pfn_to_page(pfn); -+ -+ /* Advance to next. */ -+ logical += PAGE_SIZE; -+ } -+ } -+ else -+ { -+ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES); -+ } -+ -+ /* Check if this memory is contiguous for old mmu. */ -+ if (Os->device->kernels[Core]->hardware->mmuVersion == 0) -+ { -+ for (i = 1; i < pageCount; i++) -+ { -+ if (pages[i] != nth_page(pages[0], i)) -+ { -+ /* Non-contiguous. */ -+ break; -+ } -+ } -+ -+ if (i == pageCount) -+ { -+ /* Contiguous memory. */ -+ physical = page_to_phys(pages[0]) | (memory & ~PAGE_MASK); -+ -+ if (!((physical - Os->device->baseAddress) & 0x80000000)) -+ { -+ kfree(pages); -+ pages = gcvNULL; -+ -+ info->pages = gcvNULL; -+ info->pageTable = gcvNULL; -+ -+ MEMORY_MAP_UNLOCK(Os); -+ -+ *Address = physical - Os->device->baseAddress; -+ *Info = info; -+ -+ gcmkVERIFY_OK( -+ gckOS_CPUPhysicalToGPUPhysical(Os, *Address, Address)); -+ -+ gcmkFOOTER_ARG("*Info=0x%X *Address=0x%08x", -+ *Info, *Address); -+ -+ return gcvSTATUS_OK; -+ } -+ } -+ } -+ -+ /* Reference pages. */ -+ for (i = 0; i < pageCount; i++) -+ { -+ if (pfn_valid(page_to_pfn(pages[i]))) -+ { -+ get_page(pages[i]); -+ } -+ } -+ } -+ } -+ -+ for (i = 0; i < pageCount; i++) -+ { -+#ifdef CONFIG_ARM -+ gctUINT32 data; -+ get_user(data, (gctUINT32*)((memory & PAGE_MASK) + i * PAGE_SIZE)); -+#endif -+ -+ /* Flush(clean) the data cache. */ -+ gcmkONERROR(gckOS_CacheFlush(Os, _GetProcessID(), gcvNULL, -+ page_to_phys(pages[i]), -+ (gctPOINTER)(memory & PAGE_MASK) + i*PAGE_SIZE, -+ PAGE_SIZE)); -+ } -+ -+#if gcdPROCESS_ADDRESS_SPACE -+ gcmkONERROR(gckKERNEL_GetProcessMMU(Os->device->kernels[Core], &mmu)); -+#endif -+ -+ if (extraPage) -+ { -+ pages[pageCount++] = Os->paddingPage; -+ info->extraPage = 1; -+ } -+ -+#if gcdENABLE_VG -+ if (Core == gcvCORE_VG) -+ { -+ /* Allocate pages inside the page table. */ -+ gcmkERR_BREAK(gckVGMMU_AllocatePages(Os->device->kernels[Core]->vg->mmu, -+ pageCount * (PAGE_SIZE/4096), -+ (gctPOINTER *) &pageTable, -+ &address)); -+ } -+ else -+#endif -+ { -+#if gcdPROCESS_ADDRESS_SPACE -+ /* Allocate pages inside the page table. */ -+ gcmkERR_BREAK(gckMMU_AllocatePages(mmu, -+ pageCount * (PAGE_SIZE/4096), -+ (gctPOINTER *) &pageTable, -+ &address)); -+#else -+ /* Allocate pages inside the page table. */ -+ gcmkERR_BREAK(gckMMU_AllocatePages(Os->device->kernels[Core]->mmu, -+ pageCount * (PAGE_SIZE/4096), -+ (gctPOINTER *) &pageTable, -+ &address)); -+#endif -+ } -+ -+ /* Fill the page table. */ -+ for (i = 0; i < pageCount; i++) -+ { -+ gctUINT32 phys; -+ gctUINT32_PTR tab = pageTable + i * (PAGE_SIZE/4096); -+ -+#if gcdPROCESS_ADDRESS_SPACE -+ gckMMU_GetPageEntry(mmu, address + i * 4096, &tab); -+#endif -+ phys = page_to_phys(pages[i]); -+ -+#ifdef CONFIG_IOMMU_SUPPORT -+ if (Os->iommu) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, gcvZONE_OS, -+ "%s(%d): Setup mapping in IOMMU %x => %x", -+ __FUNCTION__, __LINE__, -+ Address + (i * PAGE_SIZE), phys -+ ); -+ -+ gcmkONERROR(gckIOMMU_Map( -+ Os->iommu, address + i * PAGE_SIZE, phys, PAGE_SIZE)); -+ } -+ else -+#endif -+ { -+ -+#if gcdENABLE_VG -+ if (Core == gcvCORE_VG) -+ { -+ gcmkVERIFY_OK( -+ gckOS_CPUPhysicalToGPUPhysical(Os, phys, &phys)); -+ -+ /* Get the physical address from page struct. */ -+ gcmkONERROR( -+ gckVGMMU_SetPage(Os->device->kernels[Core]->vg->mmu, -+ phys, -+ tab)); -+ } -+ else -+#endif -+ { -+ /* Get the physical address from page struct. */ -+ gcmkONERROR( -+ gckMMU_SetPage(Os->device->kernels[Core]->mmu, -+ phys, -+ tab)); -+ } -+ -+ for (j = 1; j < (PAGE_SIZE/4096); j++) -+ { -+ pageTable[i * (PAGE_SIZE/4096) + j] = pageTable[i * (PAGE_SIZE/4096)] + 4096 * j; -+ } -+ } -+ -+#if !gcdPROCESS_ADDRESS_SPACE -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, gcvZONE_OS, -+ "%s(%d): pageTable[%d]: 0x%X 0x%X.", -+ __FUNCTION__, __LINE__, -+ i, phys, pageTable[i]); -+#endif -+ } -+ -+#if gcdENABLE_VG -+ if (Core == gcvCORE_VG) -+ { -+ gcmkONERROR(gckVGMMU_Flush(Os->device->kernels[Core]->vg->mmu)); -+ } -+ else -+#endif -+ { -+#if gcdPROCESS_ADDRESS_SPACE -+ info->mmu = mmu; -+ gcmkONERROR(gckMMU_Flush(mmu)); -+#else -+ gcmkONERROR(gckMMU_Flush(Os->device->kernels[Core]->mmu, gcvSURF_TYPE_UNKNOWN)); -+#endif -+ } -+ info->address = address; -+ -+ /* Save pointer to page table. */ -+ info->pageTable = pageTable; -+ info->pages = pages; -+ -+ *Info = (gctPOINTER) info; -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, gcvZONE_OS, -+ "%s(%d): info->pages: 0x%X, info->pageTable: 0x%X, info: 0x%X.", -+ __FUNCTION__, __LINE__, -+ info->pages, -+ info->pageTable, -+ info -+ ); -+ -+ offset = (Physical != ~0U) -+ ? (Physical & ~PAGE_MASK) -+ : (memory & ~PAGE_MASK); -+ -+ /* Return address. */ -+ *Address = address + offset; -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, gcvZONE_OS, -+ "%s(%d): Address: 0x%X.", -+ __FUNCTION__, __LINE__, -+ *Address -+ ); -+ -+ /* Success. */ -+ status = gcvSTATUS_OK; -+ } -+ while (gcvFALSE); -+ -+OnError: -+ -+ if (gcmIS_ERROR(status)) -+ { -+ gcmkTRACE( -+ gcvLEVEL_ERROR, -+ "%s(%d): error occured: %d.", -+ __FUNCTION__, __LINE__, -+ status -+ ); -+ -+ /* Release page array. */ -+ if (result > 0 && pages != gcvNULL) -+ { -+ gcmkTRACE( -+ gcvLEVEL_ERROR, -+ "%s(%d): error: page table is freed.", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ for (i = 0; i < result; i++) -+ { -+ if (pages[i] == gcvNULL) -+ { -+ break; -+ } -+ page_cache_release(pages[i]); -+ } -+ } -+ -+ if (info!= gcvNULL && pages != gcvNULL) -+ { -+ gcmkTRACE( -+ gcvLEVEL_ERROR, -+ "%s(%d): error: pages is freed.", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ /* Free the page table. */ -+ kfree(pages); -+ info->pages = gcvNULL; -+ } -+ -+ /* Release page info struct. */ -+ if (info != gcvNULL) -+ { -+ gcmkTRACE( -+ gcvLEVEL_ERROR, -+ "%s(%d): error: info is freed.", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ /* Free the page info struct. */ -+ kfree(info); -+ *Info = gcvNULL; -+ } -+ } -+ -+ MEMORY_MAP_UNLOCK(Os); -+ -+ /* Return the status. */ -+ if (gcmIS_SUCCESS(status)) -+ { -+ gcmkFOOTER_ARG("*Info=0x%X *Address=0x%08x", *Info, *Address); -+ } -+ else -+ { -+ gcmkFOOTER(); -+ } -+ -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckOS_UnmapUserMemory -+** -+** Unlock a user buffer and that was previously locked down by -+** gckOS_MapUserMemory. -+** -+** INPUT: -+** -+** gctPOINTER Memory -+** Pointer to memory to unlock. -+** -+** gctSIZE_T Size -+** Size in bytes of the memory to unlock. -+** -+** gctPOINTER Info -+** Information record returned by gckOS_MapUserMemory. -+** -+** gctUINT32_PTR Address -+** The address returned by gckOS_MapUserMemory. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_UnmapUserMemory( -+ IN gckOS Os, -+ IN gceCORE Core, -+ IN gctPOINTER Memory, -+ IN gctSIZE_T Size, -+ IN gctPOINTER Info, -+ IN gctUINT32 Address -+ ) -+{ -+ gceSTATUS status; -+ gctUINTPTR_T memory, start, end; -+ gcsPageInfo_PTR info; -+ gctSIZE_T pageCount, i; -+ struct page **pages; -+ -+ gcmkHEADER_ARG("Os=0x%X Core=%d Memory=0x%X Size=%lu Info=0x%X Address0x%08x", -+ Os, Core, Memory, Size, Info, Address); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Memory != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Size > 0); -+ gcmkVERIFY_ARGUMENT(Info != gcvNULL); -+ -+ do -+ { -+ info = (gcsPageInfo_PTR) Info; -+ -+ pages = info->pages; -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, gcvZONE_OS, -+ "%s(%d): info=0x%X, pages=0x%X.", -+ __FUNCTION__, __LINE__, -+ info, pages -+ ); -+ -+ /* Invalid page array. */ -+ if (pages == gcvNULL && info->pageTable == gcvNULL) -+ { -+ kfree(info); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ } -+ -+ memory = (gctUINTPTR_T)Memory; -+ end = (memory + Size + PAGE_SIZE - 1) >> PAGE_SHIFT; -+ start = memory >> PAGE_SHIFT; -+ pageCount = end - start; -+ -+ /* Overflow. */ -+ if ((memory + Size) < memory) -+ { -+ gcmkFOOTER_ARG("status=%d", gcvSTATUS_INVALID_ARGUMENT); -+ return gcvSTATUS_INVALID_ARGUMENT; -+ } -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, gcvZONE_OS, -+ "%s(%d): memory: 0x%X, pageCount: %d, pageTable: 0x%X.", -+ __FUNCTION__, __LINE__, -+ memory, pageCount, info->pageTable -+ ); -+ -+ MEMORY_MAP_LOCK(Os); -+ -+ gcmkASSERT(info->pageTable != gcvNULL); -+ -+ if (info->extraPage) -+ { -+ pageCount += 1; -+ } -+ -+#if gcdENABLE_VG -+ if (Core == gcvCORE_VG) -+ { -+ /* Free the pages from the MMU. */ -+ gcmkERR_BREAK(gckVGMMU_FreePages(Os->device->kernels[Core]->vg->mmu, -+ info->pageTable, -+ pageCount * (PAGE_SIZE/4096) -+ )); -+ } -+ else -+#endif -+ { -+ /* Free the pages from the MMU. */ -+#if gcdPROCESS_ADDRESS_SPACE -+ gcmkERR_BREAK(gckMMU_FreePagesEx(info->mmu, -+ info->address, -+ pageCount * (PAGE_SIZE/4096) -+ )); -+ -+#else -+ gcmkERR_BREAK(gckMMU_FreePages(Os->device->kernels[Core]->mmu, -+ info->pageTable, -+ pageCount * (PAGE_SIZE/4096) -+ )); -+#endif -+ -+ gcmkERR_BREAK(gckOS_UnmapPages( -+ Os, -+ pageCount * (PAGE_SIZE/4096), -+ info->address -+ )); -+ } -+ -+ if (info->extraPage) -+ { -+ pageCount -= 1; -+ info->extraPage = 0; -+ } -+ -+ /* Release the page cache. */ -+ if (pages) -+ { -+ for (i = 0; i < pageCount; i++) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, gcvZONE_OS, -+ "%s(%d): pages[%d]: 0x%X.", -+ __FUNCTION__, __LINE__, -+ i, pages[i] -+ ); -+ -+ if (!PageReserved(pages[i])) -+ { -+ SetPageDirty(pages[i]); -+ } -+ -+ if (pfn_valid(page_to_pfn(pages[i]))) -+ { -+ page_cache_release(pages[i]); -+ } -+ } -+ } -+ -+ /* Success. */ -+ status = gcvSTATUS_OK; -+ } -+ while (gcvFALSE); -+ -+ if (info != gcvNULL) -+ { -+ /* Free the page array. */ -+ if (info->pages != gcvNULL) -+ { -+ kfree(info->pages); -+ } -+ -+ kfree(info); -+ } -+ -+ MEMORY_MAP_UNLOCK(Os); -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckOS_GetBaseAddress -+** -+** Get the base address for the physical memory. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to the gckOS object. -+** -+** OUTPUT: -+** -+** gctUINT32_PTR BaseAddress -+** Pointer to a variable that will receive the base address. -+*/ -+gceSTATUS -+gckOS_GetBaseAddress( -+ IN gckOS Os, -+ OUT gctUINT32_PTR BaseAddress -+ ) -+{ -+ gcmkHEADER_ARG("Os=0x%X", Os); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(BaseAddress != gcvNULL); -+ -+ /* Return base address. */ -+ *BaseAddress = Os->device->baseAddress; -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*BaseAddress=0x%08x", *BaseAddress); -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckOS_SuspendInterrupt( -+ IN gckOS Os -+ ) -+{ -+ return gckOS_SuspendInterruptEx(Os, gcvCORE_MAJOR); -+} -+ -+gceSTATUS -+gckOS_SuspendInterruptEx( -+ IN gckOS Os, -+ IN gceCORE Core -+ ) -+{ -+ gcmkHEADER_ARG("Os=0x%X Core=%d", Os, Core); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ -+ disable_irq(Os->device->irqLines[Core]); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckOS_ResumeInterrupt( -+ IN gckOS Os -+ ) -+{ -+ return gckOS_ResumeInterruptEx(Os, gcvCORE_MAJOR); -+} -+ -+gceSTATUS -+gckOS_ResumeInterruptEx( -+ IN gckOS Os, -+ IN gceCORE Core -+ ) -+{ -+ gcmkHEADER_ARG("Os=0x%X Core=%d", Os, Core); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ -+ enable_irq(Os->device->irqLines[Core]); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckOS_MemCopy( -+ IN gctPOINTER Destination, -+ IN gctCONST_POINTER Source, -+ IN gctSIZE_T Bytes -+ ) -+{ -+ gcmkHEADER_ARG("Destination=0x%X Source=0x%X Bytes=%lu", -+ Destination, Source, Bytes); -+ -+ gcmkVERIFY_ARGUMENT(Destination != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Source != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Bytes > 0); -+ -+ memcpy(Destination, Source, Bytes); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckOS_ZeroMemory( -+ IN gctPOINTER Memory, -+ IN gctSIZE_T Bytes -+ ) -+{ -+ gcmkHEADER_ARG("Memory=0x%X Bytes=%lu", Memory, Bytes); -+ -+ gcmkVERIFY_ARGUMENT(Memory != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Bytes > 0); -+ -+ memset(Memory, 0, Bytes); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+********************************* Cache Control ******************************** -+*******************************************************************************/ -+ -+/******************************************************************************* -+** gckOS_CacheClean -+** -+** Clean the cache for the specified addresses. The GPU is going to need the -+** data. If the system is allocating memory as non-cachable, this function can -+** be ignored. -+** -+** ARGUMENTS: -+** -+** gckOS Os -+** Pointer to gckOS object. -+** -+** gctUINT32 ProcessID -+** Process ID Logical belongs. -+** -+** gctPHYS_ADDR Handle -+** Physical address handle. If gcvNULL it is video memory. -+** -+** gctPOINTER Physical -+** Physical address to flush. -+** -+** gctPOINTER Logical -+** Logical address to flush. -+** -+** gctSIZE_T Bytes -+** Size of the address range in bytes to flush. -+*/ -+gceSTATUS -+gckOS_CacheClean( -+ IN gckOS Os, -+ IN gctUINT32 ProcessID, -+ IN gctPHYS_ADDR Handle, -+ IN gctUINT32 Physical, -+ IN gctPOINTER Logical, -+ IN gctSIZE_T Bytes -+ ) -+{ -+ gcsPLATFORM * platform; -+ -+ gcmkHEADER_ARG("Os=0x%X ProcessID=%d Handle=0x%X Logical=0x%X Bytes=%lu", -+ Os, ProcessID, Handle, Logical, Bytes); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Logical != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Bytes > 0); -+ -+ platform = Os->device->platform; -+ -+ if (platform && platform->ops->cache) -+ { -+ platform->ops->cache( -+ platform, -+ ProcessID, -+ Handle, -+ Physical, -+ Logical, -+ Bytes, -+ gcvCACHE_CLEAN -+ ); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ } -+ -+ dma_sync_single_for_device( -+ gcvNULL, -+ (dma_addr_t)Physical, -+ Bytes, -+ DMA_TO_DEVICE); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** gckOS_CacheInvalidate -+** -+** Invalidate the cache for the specified addresses. The GPU is going to need -+** data. If the system is allocating memory as non-cachable, this function can -+** be ignored. -+** -+** ARGUMENTS: -+** -+** gckOS Os -+** Pointer to gckOS object. -+** -+** gctUINT32 ProcessID -+** Process ID Logical belongs. -+** -+** gctPHYS_ADDR Handle -+** Physical address handle. If gcvNULL it is video memory. -+** -+** gctPOINTER Logical -+** Logical address to flush. -+** -+** gctSIZE_T Bytes -+** Size of the address range in bytes to flush. -+*/ -+gceSTATUS -+gckOS_CacheInvalidate( -+ IN gckOS Os, -+ IN gctUINT32 ProcessID, -+ IN gctPHYS_ADDR Handle, -+ IN gctUINT32 Physical, -+ IN gctPOINTER Logical, -+ IN gctSIZE_T Bytes -+ ) -+{ -+ gcsPLATFORM * platform; -+ -+ gcmkHEADER_ARG("Os=0x%X ProcessID=%d Handle=0x%X Logical=0x%X Bytes=%lu", -+ Os, ProcessID, Handle, Logical, Bytes); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Logical != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Bytes > 0); -+ -+ platform = Os->device->platform; -+ -+ if (platform && platform->ops->cache) -+ { -+ platform->ops->cache( -+ platform, -+ ProcessID, -+ Handle, -+ Physical, -+ Logical, -+ Bytes, -+ gcvCACHE_INVALIDATE -+ ); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ } -+ -+ dma_sync_single_for_device( -+ gcvNULL, -+ (dma_addr_t)Physical, -+ Bytes, -+ DMA_FROM_DEVICE); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** gckOS_CacheFlush -+** -+** Clean the cache for the specified addresses and invalidate the lines as -+** well. The GPU is going to need and modify the data. If the system is -+** allocating memory as non-cachable, this function can be ignored. -+** -+** ARGUMENTS: -+** -+** gckOS Os -+** Pointer to gckOS object. -+** -+** gctUINT32 ProcessID -+** Process ID Logical belongs. -+** -+** gctPHYS_ADDR Handle -+** Physical address handle. If gcvNULL it is video memory. -+** -+** gctPOINTER Logical -+** Logical address to flush. -+** -+** gctSIZE_T Bytes -+** Size of the address range in bytes to flush. -+*/ -+gceSTATUS -+gckOS_CacheFlush( -+ IN gckOS Os, -+ IN gctUINT32 ProcessID, -+ IN gctPHYS_ADDR Handle, -+ IN gctUINT32 Physical, -+ IN gctPOINTER Logical, -+ IN gctSIZE_T Bytes -+ ) -+{ -+ gcsPLATFORM * platform; -+ -+ gcmkHEADER_ARG("Os=0x%X ProcessID=%d Handle=0x%X Logical=0x%X Bytes=%lu", -+ Os, ProcessID, Handle, Logical, Bytes); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Logical != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Bytes > 0); -+ -+ platform = Os->device->platform; -+ -+ if (platform && platform->ops->cache) -+ { -+ platform->ops->cache( -+ platform, -+ ProcessID, -+ Handle, -+ Physical, -+ Logical, -+ Bytes, -+ gcvCACHE_FLUSH -+ ); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ } -+ -+ if (Physical != gcvINVALID_ADDRESS) -+ { -+ dma_sync_single_for_device( -+ gcvNULL, -+ (dma_addr_t)Physical, -+ Bytes, -+ DMA_BIDIRECTIONAL); -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+********************************* Broadcasting ********************************* -+*******************************************************************************/ -+ -+/******************************************************************************* -+** -+** gckOS_Broadcast -+** -+** System hook for broadcast events from the kernel driver. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to the gckOS object. -+** -+** gckHARDWARE Hardware -+** Pointer to the gckHARDWARE object. -+** -+** gceBROADCAST Reason -+** Reason for the broadcast. Can be one of the following values: -+** -+** gcvBROADCAST_GPU_IDLE -+** Broadcasted when the kernel driver thinks the GPU might be -+** idle. This can be used to handle power management. -+** -+** gcvBROADCAST_GPU_COMMIT -+** Broadcasted when any client process commits a command -+** buffer. This can be used to handle power management. -+** -+** gcvBROADCAST_GPU_STUCK -+** Broadcasted when the kernel driver hits the timeout waiting -+** for the GPU. -+** -+** gcvBROADCAST_FIRST_PROCESS -+** First process is trying to connect to the kernel. -+** -+** gcvBROADCAST_LAST_PROCESS -+** Last process has detached from the kernel. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_Broadcast( -+ IN gckOS Os, -+ IN gckHARDWARE Hardware, -+ IN gceBROADCAST Reason -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Os=0x%X Hardware=0x%X Reason=%d", Os, Hardware, Reason); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ -+ switch (Reason) -+ { -+ case gcvBROADCAST_FIRST_PROCESS: -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_OS, "First process has attached"); -+ break; -+ -+ case gcvBROADCAST_LAST_PROCESS: -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_OS, "Last process has detached"); -+ -+ /* Put GPU OFF. */ -+ gcmkONERROR( -+ gckHARDWARE_SetPowerManagementState(Hardware, -+ gcvPOWER_OFF_BROADCAST)); -+ break; -+ -+ case gcvBROADCAST_GPU_IDLE: -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_OS, "GPU idle."); -+ -+ /* Put GPU IDLE. */ -+ gcmkONERROR( -+ gckHARDWARE_SetPowerManagementState(Hardware, -+#if gcdPOWER_SUSPEND_WHEN_IDLE -+ gcvPOWER_SUSPEND_BROADCAST)); -+#else -+ gcvPOWER_IDLE_BROADCAST)); -+#endif -+ -+ /* Add idle process DB. */ -+ gcmkONERROR(gckKERNEL_AddProcessDB(Hardware->kernel, -+ 1, -+ gcvDB_IDLE, -+ gcvNULL, gcvNULL, 0)); -+ break; -+ -+ case gcvBROADCAST_GPU_COMMIT: -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_OS, "COMMIT has arrived."); -+ -+ /* Add busy process DB. */ -+ gcmkONERROR(gckKERNEL_AddProcessDB(Hardware->kernel, -+ 0, -+ gcvDB_IDLE, -+ gcvNULL, gcvNULL, 0)); -+ -+ /* Put GPU ON. */ -+ gcmkONERROR( -+ gckHARDWARE_SetPowerManagementState(Hardware, gcvPOWER_ON_AUTO)); -+ break; -+ -+ case gcvBROADCAST_GPU_STUCK: -+ gcmkTRACE_N(gcvLEVEL_ERROR, 0, "gcvBROADCAST_GPU_STUCK\n"); -+ gcmkONERROR(gckKERNEL_Recovery(Hardware->kernel)); -+ break; -+ -+ case gcvBROADCAST_AXI_BUS_ERROR: -+ gcmkTRACE_N(gcvLEVEL_ERROR, 0, "gcvBROADCAST_AXI_BUS_ERROR\n"); -+ gcmkONERROR(gckHARDWARE_DumpGPUState(Hardware)); -+ gcmkONERROR(gckKERNEL_Recovery(Hardware->kernel)); -+ break; -+ -+ case gcvBROADCAST_OUT_OF_MEMORY: -+ gcmkTRACE_N(gcvLEVEL_INFO, 0, "gcvBROADCAST_OUT_OF_MEMORY\n"); -+ -+ status = _ShrinkMemory(Os); -+ -+ if (status == gcvSTATUS_NOT_SUPPORTED) -+ { -+ goto OnError; -+ } -+ -+ gcmkONERROR(status); -+ -+ break; -+ -+ default: -+ /* Skip unimplemented broadcast. */ -+ break; -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckOS_BroadcastHurry -+** -+** The GPU is running too slow. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to the gckOS object. -+** -+** gckHARDWARE Hardware -+** Pointer to the gckHARDWARE object. -+** -+** gctUINT Urgency -+** The higher the number, the higher the urgency to speed up the GPU. -+** The maximum value is defined by the gcdDYNAMIC_EVENT_THRESHOLD. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_BroadcastHurry( -+ IN gckOS Os, -+ IN gckHARDWARE Hardware, -+ IN gctUINT Urgency -+ ) -+{ -+ gcmkHEADER_ARG("Os=0x%x Hardware=0x%x Urgency=%u", Os, Hardware, Urgency); -+ -+ /* Do whatever you need to do to speed up the GPU now. */ -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_BroadcastCalibrateSpeed -+** -+** Calibrate the speed of the GPU. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to the gckOS object. -+** -+** gckHARDWARE Hardware -+** Pointer to the gckHARDWARE object. -+** -+** gctUINT Idle, Time -+** Idle/Time will give the percentage the GPU is idle, so you can use -+** this to calibrate the working point of the GPU. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_BroadcastCalibrateSpeed( -+ IN gckOS Os, -+ IN gckHARDWARE Hardware, -+ IN gctUINT Idle, -+ IN gctUINT Time -+ ) -+{ -+ gcmkHEADER_ARG("Os=0x%x Hardware=0x%x Idle=%u Time=%u", -+ Os, Hardware, Idle, Time); -+ -+ /* Do whatever you need to do to callibrate the GPU speed. */ -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+********************************** Semaphores ********************************** -+*******************************************************************************/ -+ -+/******************************************************************************* -+** -+** gckOS_CreateSemaphore -+** -+** Create a semaphore. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to the gckOS object. -+** -+** OUTPUT: -+** -+** gctPOINTER * Semaphore -+** Pointer to the variable that will receive the created semaphore. -+*/ -+gceSTATUS -+gckOS_CreateSemaphore( -+ IN gckOS Os, -+ OUT gctPOINTER * Semaphore -+ ) -+{ -+ gceSTATUS status; -+ struct semaphore *sem = gcvNULL; -+ -+ gcmkHEADER_ARG("Os=0x%X", Os); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL); -+ -+ /* Allocate the semaphore structure. */ -+ sem = (struct semaphore *)kmalloc(gcmSIZEOF(struct semaphore), GFP_KERNEL | gcdNOWARN); -+ if (sem == gcvNULL) -+ { -+ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); -+ } -+ -+ /* Initialize the semaphore. */ -+ sema_init(sem, 1); -+ -+ /* Return to caller. */ -+ *Semaphore = (gctPOINTER) sem; -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckOS_AcquireSemaphore -+** -+** Acquire a semaphore. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to the gckOS object. -+** -+** gctPOINTER Semaphore -+** Pointer to the semaphore thet needs to be acquired. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_AcquireSemaphore( -+ IN gckOS Os, -+ IN gctPOINTER Semaphore -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Os=0x%08X Semaphore=0x%08X", Os, Semaphore); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL); -+ -+ /* Acquire the semaphore. */ -+ if (down_interruptible((struct semaphore *) Semaphore)) -+ { -+ gcmkONWARNING(gcvSTATUS_INTERRUPTED); -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckOS_TryAcquireSemaphore -+** -+** Try to acquire a semaphore. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to the gckOS object. -+** -+** gctPOINTER Semaphore -+** Pointer to the semaphore thet needs to be acquired. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_TryAcquireSemaphore( -+ IN gckOS Os, -+ IN gctPOINTER Semaphore -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Os=0x%x", Os); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL); -+ -+ /* Acquire the semaphore. */ -+ if (down_trylock((struct semaphore *) Semaphore)) -+ { -+ /* Timeout. */ -+ status = gcvSTATUS_TIMEOUT; -+ gcmkFOOTER(); -+ return status; -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_ReleaseSemaphore -+** -+** Release a previously acquired semaphore. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to the gckOS object. -+** -+** gctPOINTER Semaphore -+** Pointer to the semaphore thet needs to be released. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_ReleaseSemaphore( -+ IN gckOS Os, -+ IN gctPOINTER Semaphore -+ ) -+{ -+ gcmkHEADER_ARG("Os=0x%X Semaphore=0x%X", Os, Semaphore); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL); -+ -+ /* Release the semaphore. */ -+ up((struct semaphore *) Semaphore); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_DestroySemaphore -+** -+** Destroy a semaphore. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to the gckOS object. -+** -+** gctPOINTER Semaphore -+** Pointer to the semaphore thet needs to be destroyed. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_DestroySemaphore( -+ IN gckOS Os, -+ IN gctPOINTER Semaphore -+ ) -+{ -+ gcmkHEADER_ARG("Os=0x%X Semaphore=0x%X", Os, Semaphore); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL); -+ -+ /* Free the sempahore structure. */ -+ kfree(Semaphore); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_GetProcessID -+** -+** Get current process ID. -+** -+** INPUT: -+** -+** Nothing. -+** -+** OUTPUT: -+** -+** gctUINT32_PTR ProcessID -+** Pointer to the variable that receives the process ID. -+*/ -+gceSTATUS -+gckOS_GetProcessID( -+ OUT gctUINT32_PTR ProcessID -+ ) -+{ -+ /* Get process ID. */ -+ if (ProcessID != gcvNULL) -+ { -+ *ProcessID = _GetProcessID(); -+ } -+ -+ /* Success. */ -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_GetThreadID -+** -+** Get current thread ID. -+** -+** INPUT: -+** -+** Nothing. -+** -+** OUTPUT: -+** -+** gctUINT32_PTR ThreadID -+** Pointer to the variable that receives the thread ID. -+*/ -+gceSTATUS -+gckOS_GetThreadID( -+ OUT gctUINT32_PTR ThreadID -+ ) -+{ -+ /* Get thread ID. */ -+ if (ThreadID != gcvNULL) -+ { -+ *ThreadID = _GetThreadID(); -+ } -+ -+ /* Success. */ -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_SetGPUPower -+** -+** Set the power of the GPU on or off. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to a gckOS object. -+** -+** gceCORE Core -+** GPU whose power is set. -+** -+** gctBOOL Clock -+** gcvTRUE to turn on the clock, or gcvFALSE to turn off the clock. -+** -+** gctBOOL Power -+** gcvTRUE to turn on the power, or gcvFALSE to turn off the power. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_SetGPUPower( -+ IN gckOS Os, -+ IN gceCORE Core, -+ IN gctBOOL Clock, -+ IN gctBOOL Power -+ ) -+{ -+ gcsPLATFORM * platform; -+ -+ gctBOOL powerChange = gcvFALSE; -+ gctBOOL clockChange = gcvFALSE; -+ -+ gcmkHEADER_ARG("Os=0x%X Core=%d Clock=%d Power=%d", Os, Core, Clock, Power); -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ -+ platform = Os->device->platform; -+ -+ powerChange = (Power != Os->powerStates[Core]); -+ -+ clockChange = (Clock != Os->clockStates[Core]); -+ -+ if (powerChange && (Power == gcvTRUE)) -+ { -+ if (platform && platform->ops->setPower) -+ { -+ gcmkVERIFY_OK(platform->ops->setPower(platform, Core, Power)); -+ } -+ -+ Os->powerStates[Core] = Power; -+ } -+ -+ if (clockChange) -+ { -+ mutex_lock(&Os->registerAccessLocks[Core]); -+ -+ if (platform && platform->ops->setClock) -+ { -+ gcmkVERIFY_OK(platform->ops->setClock(platform, Core, Clock)); -+ } -+ -+ Os->clockStates[Core] = Clock; -+ -+ mutex_unlock(&Os->registerAccessLocks[Core]); -+ } -+ -+ if (powerChange && (Power == gcvFALSE)) -+ { -+ if (platform && platform->ops->setPower) -+ { -+ gcmkVERIFY_OK(platform->ops->setPower(platform, Core, Power)); -+ } -+ -+ Os->powerStates[Core] = Power; -+ } -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_ResetGPU -+** -+** Reset the GPU. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to a gckOS object. -+** -+** gckCORE Core -+** GPU whose power is set. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_ResetGPU( -+ IN gckOS Os, -+ IN gceCORE Core -+ ) -+{ -+ gceSTATUS status = gcvSTATUS_NOT_SUPPORTED; -+ gcsPLATFORM * platform; -+ -+ gcmkHEADER_ARG("Os=0x%X Core=%d", Os, Core); -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ -+ platform = Os->device->platform; -+ -+ if (platform && platform->ops->reset) -+ { -+ status = platform->ops->reset(platform, Core); -+ } -+ -+ gcmkFOOTER_NO(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckOS_PrepareGPUFrequency -+** -+** Prepare to set GPU frequency and voltage. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to a gckOS object. -+** -+** gckCORE Core -+** GPU whose frequency and voltage will be set. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_PrepareGPUFrequency( -+ IN gckOS Os, -+ IN gceCORE Core -+ ) -+{ -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_FinishGPUFrequency -+** -+** Finish GPU frequency setting. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to a gckOS object. -+** -+** gckCORE Core -+** GPU whose frequency and voltage is set. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_FinishGPUFrequency( -+ IN gckOS Os, -+ IN gceCORE Core -+ ) -+{ -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_QueryGPUFrequency -+** -+** Query the current frequency of the GPU. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to a gckOS object. -+** -+** gckCORE Core -+** GPU whose power is set. -+** -+** gctUINT32 * Frequency -+** Pointer to a gctUINT32 to obtain current frequency, in MHz. -+** -+** gctUINT8 * Scale -+** Pointer to a gctUINT8 to obtain current scale(1 - 64). -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_QueryGPUFrequency( -+ IN gckOS Os, -+ IN gceCORE Core, -+ OUT gctUINT32 * Frequency, -+ OUT gctUINT8 * Scale -+ ) -+{ -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_SetGPUFrequency -+** -+** Set frequency and voltage of the GPU. -+** -+** 1. DVFS manager gives the target scale of full frequency, BSP must find -+** a real frequency according to this scale and board's configure. -+** -+** 2. BSP should find a suitable voltage for this frequency. -+** -+** 3. BSP must make sure setting take effect before this function returns. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to a gckOS object. -+** -+** gckCORE Core -+** GPU whose power is set. -+** -+** gctUINT8 Scale -+** Target scale of full frequency, range is [1, 64]. 1 means 1/64 of -+** full frequency and 64 means 64/64 of full frequency. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_SetGPUFrequency( -+ IN gckOS Os, -+ IN gceCORE Core, -+ IN gctUINT8 Scale -+ ) -+{ -+ return gcvSTATUS_OK; -+} -+ -+/*----------------------------------------------------------------------------*/ -+/*----- Profile --------------------------------------------------------------*/ -+ -+gceSTATUS -+gckOS_GetProfileTick( -+ OUT gctUINT64_PTR Tick -+ ) -+{ -+ struct timespec time; -+ -+ ktime_get_ts(&time); -+ -+ *Tick = time.tv_nsec + time.tv_sec * 1000000000ULL; -+ -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckOS_QueryProfileTickRate( -+ OUT gctUINT64_PTR TickRate -+ ) -+{ -+ struct timespec res; -+ -+ hrtimer_get_res(CLOCK_MONOTONIC, &res); -+ -+ *TickRate = res.tv_nsec + res.tv_sec * 1000000000ULL; -+ -+ return gcvSTATUS_OK; -+} -+ -+gctUINT32 -+gckOS_ProfileToMS( -+ IN gctUINT64 Ticks -+ ) -+{ -+ return div_u64(Ticks, 1000000); -+} -+ -+/******************************************************************************\ -+******************************* Signal Management ****************************** -+\******************************************************************************/ -+ -+#undef _GC_OBJ_ZONE -+#define _GC_OBJ_ZONE gcvZONE_SIGNAL -+ -+/******************************************************************************* -+** -+** gckOS_CreateSignal -+** -+** Create a new signal. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctBOOL ManualReset -+** If set to gcvTRUE, gckOS_Signal with gcvFALSE must be called in -+** order to set the signal to nonsignaled state. -+** If set to gcvFALSE, the signal will automatically be set to -+** nonsignaled state by gckOS_WaitSignal function. -+** -+** OUTPUT: -+** -+** gctSIGNAL * Signal -+** Pointer to a variable receiving the created gctSIGNAL. -+*/ -+gceSTATUS -+gckOS_CreateSignal( -+ IN gckOS Os, -+ IN gctBOOL ManualReset, -+ OUT gctSIGNAL * Signal -+ ) -+{ -+ gceSTATUS status; -+ gcsSIGNAL_PTR signal; -+ -+ gcmkHEADER_ARG("Os=0x%X ManualReset=%d", Os, ManualReset); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Signal != gcvNULL); -+ -+ /* Create an event structure. */ -+ signal = (gcsSIGNAL_PTR) kmalloc(sizeof(gcsSIGNAL), GFP_KERNEL | gcdNOWARN); -+ -+ if (signal == gcvNULL) -+ { -+ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); -+ } -+ -+ /* Save the process ID. */ -+ signal->process = (gctHANDLE)(gctUINTPTR_T) _GetProcessID(); -+ signal->manualReset = ManualReset; -+ signal->hardware = gcvNULL; -+ init_completion(&signal->obj); -+ atomic_set(&signal->ref, 1); -+ -+ gcmkONERROR(_AllocateIntegerId(&Os->signalDB, signal, &signal->id)); -+ -+ *Signal = (gctSIGNAL)(gctUINTPTR_T)signal->id; -+ -+ gcmkFOOTER_ARG("*Signal=0x%X", *Signal); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (signal != gcvNULL) -+ { -+ kfree(signal); -+ } -+ -+ gcmkFOOTER_NO(); -+ return status; -+} -+ -+gceSTATUS -+gckOS_SignalQueryHardware( -+ IN gckOS Os, -+ IN gctSIGNAL Signal, -+ OUT gckHARDWARE * Hardware -+ ) -+{ -+ gceSTATUS status; -+ gcsSIGNAL_PTR signal; -+ -+ gcmkHEADER_ARG("Os=0x%X Signal=0x%X Hardware=0x%X", Os, Signal, Hardware); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Signal != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Hardware != gcvNULL); -+ -+ gcmkONERROR(_QueryIntegerId(&Os->signalDB, (gctUINT32)(gctUINTPTR_T)Signal, (gctPOINTER)&signal)); -+ -+ *Hardware = signal->hardware; -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+OnError: -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckOS_SignalSetHardware( -+ IN gckOS Os, -+ IN gctSIGNAL Signal, -+ IN gckHARDWARE Hardware -+ ) -+{ -+ gceSTATUS status; -+ gcsSIGNAL_PTR signal; -+ -+ gcmkHEADER_ARG("Os=0x%X Signal=0x%X Hardware=0x%X", Os, Signal, Hardware); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Signal != gcvNULL); -+ -+ gcmkONERROR(_QueryIntegerId(&Os->signalDB, (gctUINT32)(gctUINTPTR_T)Signal, (gctPOINTER)&signal)); -+ -+ signal->hardware = Hardware; -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+OnError: -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckOS_DestroySignal -+** -+** Destroy a signal. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctSIGNAL Signal -+** Pointer to the gctSIGNAL. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_DestroySignal( -+ IN gckOS Os, -+ IN gctSIGNAL Signal -+ ) -+{ -+ gceSTATUS status; -+ gcsSIGNAL_PTR signal; -+ gctBOOL acquired = gcvFALSE; -+ -+ gcmkHEADER_ARG("Os=0x%X Signal=0x%X", Os, Signal); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Signal != gcvNULL); -+ -+ gcmkONERROR(gckOS_AcquireMutex(Os, Os->signalMutex, gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ gcmkONERROR(_QueryIntegerId(&Os->signalDB, (gctUINT32)(gctUINTPTR_T)Signal, (gctPOINTER)&signal)); -+ -+ gcmkASSERT(signal->id == (gctUINT32)(gctUINTPTR_T)Signal); -+ -+ if (atomic_dec_and_test(&signal->ref)) -+ { -+ gcmkVERIFY_OK(_DestroyIntegerId(&Os->signalDB, signal->id)); -+ -+ /* Free the sgianl. */ -+ kfree(signal); -+ } -+ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->signalMutex)); -+ acquired = gcvFALSE; -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (acquired) -+ { -+ /* Release the mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->signalMutex)); -+ } -+ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckOS_Signal -+** -+** Set a state of the specified signal. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctSIGNAL Signal -+** Pointer to the gctSIGNAL. -+** -+** gctBOOL State -+** If gcvTRUE, the signal will be set to signaled state. -+** If gcvFALSE, the signal will be set to nonsignaled state. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_Signal( -+ IN gckOS Os, -+ IN gctSIGNAL Signal, -+ IN gctBOOL State -+ ) -+{ -+ gceSTATUS status; -+ gcsSIGNAL_PTR signal; -+ gctBOOL acquired = gcvFALSE; -+ -+ gcmkHEADER_ARG("Os=0x%X Signal=0x%X State=%d", Os, Signal, State); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Signal != gcvNULL); -+ -+ gcmkONERROR(gckOS_AcquireMutex(Os, Os->signalMutex, gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ gcmkONERROR(_QueryIntegerId(&Os->signalDB, (gctUINT32)(gctUINTPTR_T)Signal, (gctPOINTER)&signal)); -+ -+ gcmkASSERT(signal->id == (gctUINT32)(gctUINTPTR_T)Signal); -+ -+ if (State) -+ { -+ /* unbind the signal from hardware. */ -+ signal->hardware = gcvNULL; -+ -+ /* Set the event to a signaled state. */ -+ complete(&signal->obj); -+ } -+ else -+ { -+ /* Set the event to an unsignaled state. */ -+ reinit_completion(&signal->obj); -+ } -+ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->signalMutex)); -+ acquired = gcvFALSE; -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (acquired) -+ { -+ /* Release the mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->signalMutex)); -+ } -+ -+ gcmkFOOTER(); -+ return status; -+} -+ -+#if gcdENABLE_VG -+gceSTATUS -+gckOS_SetSignalVG( -+ IN gckOS Os, -+ IN gctHANDLE Process, -+ IN gctSIGNAL Signal -+ ) -+{ -+ gceSTATUS status; -+ gctINT result; -+ struct task_struct * userTask; -+ struct siginfo info; -+ -+ userTask = FIND_TASK_BY_PID((pid_t)(gctUINTPTR_T) Process); -+ -+ if (userTask != gcvNULL) -+ { -+ info.si_signo = 48; -+ info.si_code = __SI_CODE(__SI_RT, SI_KERNEL); -+ info.si_pid = 0; -+ info.si_uid = 0; -+ info.si_ptr = (gctPOINTER) Signal; -+ -+ /* Signals with numbers between 32 and 63 are real-time, -+ send a real-time signal to the user process. */ -+ result = send_sig_info(48, &info, userTask); -+ -+ printk("gckOS_SetSignalVG:0x%x\n", result); -+ /* Error? */ -+ if (result < 0) -+ { -+ status = gcvSTATUS_GENERIC_IO; -+ -+ gcmkTRACE( -+ gcvLEVEL_ERROR, -+ "%s(%d): an error has occurred.\n", -+ __FUNCTION__, __LINE__ -+ ); -+ } -+ else -+ { -+ status = gcvSTATUS_OK; -+ } -+ } -+ else -+ { -+ status = gcvSTATUS_GENERIC_IO; -+ -+ gcmkTRACE( -+ gcvLEVEL_ERROR, -+ "%s(%d): an error has occurred.\n", -+ __FUNCTION__, __LINE__ -+ ); -+ } -+ -+ /* Return status. */ -+ return status; -+} -+#endif -+ -+/******************************************************************************* -+** -+** gckOS_UserSignal -+** -+** Set the specified signal which is owned by a process to signaled state. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctSIGNAL Signal -+** Pointer to the gctSIGNAL. -+** -+** gctHANDLE Process -+** Handle of process owning the signal. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_UserSignal( -+ IN gckOS Os, -+ IN gctSIGNAL Signal, -+ IN gctHANDLE Process -+ ) -+{ -+ gceSTATUS status; -+ gctSIGNAL signal; -+ -+ gcmkHEADER_ARG("Os=0x%X Signal=0x%X Process=%d", -+ Os, Signal, (gctINT32)(gctUINTPTR_T)Process); -+ -+ /* Map the signal into kernel space. */ -+ gcmkONERROR(gckOS_MapSignal(Os, Signal, Process, &signal)); -+ -+ /* Signal. */ -+ status = gckOS_Signal(Os, signal, gcvTRUE); -+ -+ /* Unmap the signal */ -+ gcmkVERIFY_OK(gckOS_UnmapSignal(Os, Signal)); -+ -+ gcmkFOOTER(); -+ return status; -+ -+OnError: -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckOS_WaitSignal -+** -+** Wait for a signal to become signaled. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctSIGNAL Signal -+** Pointer to the gctSIGNAL. -+** -+** gctUINT32 Wait -+** Number of milliseconds to wait. -+** Pass the value of gcvINFINITE for an infinite wait. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_WaitSignal( -+ IN gckOS Os, -+ IN gctSIGNAL Signal, -+ IN gctUINT32 Wait -+ ) -+{ -+ gceSTATUS status = gcvSTATUS_OK; -+ gcsSIGNAL_PTR signal; -+ -+ gcmkHEADER_ARG("Os=0x%X Signal=0x%X Wait=0x%08X", Os, Signal, Wait); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Signal != gcvNULL); -+ -+ gcmkONERROR(_QueryIntegerId(&Os->signalDB, (gctUINT32)(gctUINTPTR_T)Signal, (gctPOINTER)&signal)); -+ -+ gcmkASSERT(signal->id == (gctUINT32)(gctUINTPTR_T)Signal); -+ -+ might_sleep(); -+ -+ spin_lock_irq(&signal->obj.wait.lock); -+ -+ if (signal->obj.done) -+ { -+ if (!signal->manualReset) -+ { -+ signal->obj.done = 0; -+ } -+ -+ status = gcvSTATUS_OK; -+ } -+ else if (Wait == 0) -+ { -+ status = gcvSTATUS_TIMEOUT; -+ } -+ else -+ { -+ /* Convert wait to milliseconds. */ -+ long timeout = (Wait == gcvINFINITE) -+ ? MAX_SCHEDULE_TIMEOUT -+ : Wait * HZ / 1000; -+ -+ DECLARE_WAITQUEUE(wait, current); -+ wait.flags |= WQ_FLAG_EXCLUSIVE; -+ __add_wait_queue_tail(&signal->obj.wait, &wait); -+ -+ while (gcvTRUE) -+ { -+ if (signal_pending(current)) -+ { -+ /* Interrupt received. */ -+ status = gcvSTATUS_INTERRUPTED; -+ break; -+ } -+ -+ __set_current_state(TASK_INTERRUPTIBLE); -+ spin_unlock_irq(&signal->obj.wait.lock); -+ timeout = schedule_timeout(timeout); -+ spin_lock_irq(&signal->obj.wait.lock); -+ -+ if (signal->obj.done) -+ { -+ if (!signal->manualReset) -+ { -+ signal->obj.done = 0; -+ } -+ -+ status = gcvSTATUS_OK; -+ break; -+ } -+ -+ if (timeout == 0) -+ { -+ -+ status = gcvSTATUS_TIMEOUT; -+ break; -+ } -+ } -+ -+ __remove_wait_queue(&signal->obj.wait, &wait); -+ } -+ -+ spin_unlock_irq(&signal->obj.wait.lock); -+ -+OnError: -+ /* Return status. */ -+ gcmkFOOTER_ARG("Signal=0x%X status=%d", Signal, status); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckOS_MapSignal -+** -+** Map a signal in to the current process space. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctSIGNAL Signal -+** Pointer to tha gctSIGNAL to map. -+** -+** gctHANDLE Process -+** Handle of process owning the signal. -+** -+** OUTPUT: -+** -+** gctSIGNAL * MappedSignal -+** Pointer to a variable receiving the mapped gctSIGNAL. -+*/ -+gceSTATUS -+gckOS_MapSignal( -+ IN gckOS Os, -+ IN gctSIGNAL Signal, -+ IN gctHANDLE Process, -+ OUT gctSIGNAL * MappedSignal -+ ) -+{ -+ gceSTATUS status; -+ gcsSIGNAL_PTR signal; -+ gcmkHEADER_ARG("Os=0x%X Signal=0x%X Process=0x%X", Os, Signal, Process); -+ -+ gcmkVERIFY_ARGUMENT(Signal != gcvNULL); -+ gcmkVERIFY_ARGUMENT(MappedSignal != gcvNULL); -+ -+ gcmkONERROR(_QueryIntegerId(&Os->signalDB, (gctUINT32)(gctUINTPTR_T)Signal, (gctPOINTER)&signal)); -+ -+ if(atomic_inc_return(&signal->ref) <= 1) -+ { -+ /* The previous value is 0, it has been deleted. */ -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ } -+ -+ *MappedSignal = (gctSIGNAL) Signal; -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*MappedSignal=0x%X", *MappedSignal); -+ return gcvSTATUS_OK; -+ -+OnError: -+ gcmkFOOTER_NO(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckOS_UnmapSignal -+** -+** Unmap a signal . -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctSIGNAL Signal -+** Pointer to that gctSIGNAL mapped. -+*/ -+gceSTATUS -+gckOS_UnmapSignal( -+ IN gckOS Os, -+ IN gctSIGNAL Signal -+ ) -+{ -+ return gckOS_DestroySignal(Os, Signal); -+} -+ -+/******************************************************************************* -+** -+** gckOS_CreateUserSignal -+** -+** Create a new signal to be used in the user space. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctBOOL ManualReset -+** If set to gcvTRUE, gckOS_Signal with gcvFALSE must be called in -+** order to set the signal to nonsignaled state. -+** If set to gcvFALSE, the signal will automatically be set to -+** nonsignaled state by gckOS_WaitSignal function. -+** -+** OUTPUT: -+** -+** gctINT * SignalID -+** Pointer to a variable receiving the created signal's ID. -+*/ -+gceSTATUS -+gckOS_CreateUserSignal( -+ IN gckOS Os, -+ IN gctBOOL ManualReset, -+ OUT gctINT * SignalID -+ ) -+{ -+ gceSTATUS status; -+ gctSIZE_T signal; -+ -+ /* Create a new signal. */ -+ gcmkONERROR(gckOS_CreateSignal(Os, ManualReset, (gctSIGNAL *) &signal)); -+ *SignalID = (gctINT) signal; -+ -+OnError: -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckOS_DestroyUserSignal -+** -+** Destroy a signal to be used in the user space. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctINT SignalID -+** The signal's ID. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_DestroyUserSignal( -+ IN gckOS Os, -+ IN gctINT SignalID -+ ) -+{ -+ return gckOS_DestroySignal(Os, (gctSIGNAL)(gctUINTPTR_T)SignalID); -+} -+ -+/******************************************************************************* -+** -+** gckOS_WaitUserSignal -+** -+** Wait for a signal used in the user mode to become signaled. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctINT SignalID -+** Signal ID. -+** -+** gctUINT32 Wait -+** Number of milliseconds to wait. -+** Pass the value of gcvINFINITE for an infinite wait. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_WaitUserSignal( -+ IN gckOS Os, -+ IN gctINT SignalID, -+ IN gctUINT32 Wait -+ ) -+{ -+ return gckOS_WaitSignal(Os, (gctSIGNAL)(gctUINTPTR_T)SignalID, Wait); -+} -+ -+/******************************************************************************* -+** -+** gckOS_SignalUserSignal -+** -+** Set a state of the specified signal to be used in the user space. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctINT SignalID -+** SignalID. -+** -+** gctBOOL State -+** If gcvTRUE, the signal will be set to signaled state. -+** If gcvFALSE, the signal will be set to nonsignaled state. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_SignalUserSignal( -+ IN gckOS Os, -+ IN gctINT SignalID, -+ IN gctBOOL State -+ ) -+{ -+ return gckOS_Signal(Os, (gctSIGNAL)(gctUINTPTR_T)SignalID, State); -+} -+ -+#if gcdENABLE_VG -+gceSTATUS -+gckOS_CreateSemaphoreVG( -+ IN gckOS Os, -+ OUT gctSEMAPHORE * Semaphore -+ ) -+{ -+ gceSTATUS status; -+ struct semaphore * newSemaphore; -+ -+ gcmkHEADER_ARG("Os=0x%X Semaphore=0x%x", Os, Semaphore); -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL); -+ -+ do -+ { -+ /* Allocate the semaphore structure. */ -+ newSemaphore = (struct semaphore *)kmalloc(gcmSIZEOF(struct semaphore), GFP_KERNEL | gcdNOWARN); -+ if (newSemaphore == gcvNULL) -+ { -+ gcmkERR_BREAK(gcvSTATUS_OUT_OF_MEMORY); -+ } -+ -+ /* Initialize the semaphore. */ -+ sema_init(newSemaphore, 0); -+ -+ /* Set the handle. */ -+ * Semaphore = (gctSEMAPHORE) newSemaphore; -+ -+ /* Success. */ -+ status = gcvSTATUS_OK; -+ } -+ while (gcvFALSE); -+ -+ gcmkFOOTER(); -+ /* Return the status. */ -+ return status; -+} -+ -+ -+gceSTATUS -+gckOS_IncrementSemaphore( -+ IN gckOS Os, -+ IN gctSEMAPHORE Semaphore -+ ) -+{ -+ gcmkHEADER_ARG("Os=0x%X Semaphore=0x%x", Os, Semaphore); -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL); -+ -+ /* Increment the semaphore's count. */ -+ up((struct semaphore *) Semaphore); -+ -+ gcmkFOOTER_NO(); -+ /* Success. */ -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckOS_DecrementSemaphore( -+ IN gckOS Os, -+ IN gctSEMAPHORE Semaphore -+ ) -+{ -+ gceSTATUS status; -+ gctINT result; -+ -+ gcmkHEADER_ARG("Os=0x%X Semaphore=0x%x", Os, Semaphore); -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Semaphore != gcvNULL); -+ -+ do -+ { -+ /* Decrement the semaphore's count. If the count is zero, wait -+ until it gets incremented. */ -+ result = down_interruptible((struct semaphore *) Semaphore); -+ -+ /* Signal received? */ -+ if (result != 0) -+ { -+ status = gcvSTATUS_TERMINATE; -+ break; -+ } -+ -+ /* Success. */ -+ status = gcvSTATUS_OK; -+ } -+ while (gcvFALSE); -+ -+ gcmkFOOTER(); -+ /* Return the status. */ -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckOS_SetSignal -+** -+** Set the specified signal to signaled state. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to the gckOS object. -+** -+** gctHANDLE Process -+** Handle of process owning the signal. -+** -+** gctSIGNAL Signal -+** Pointer to the gctSIGNAL. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_SetSignal( -+ IN gckOS Os, -+ IN gctHANDLE Process, -+ IN gctSIGNAL Signal -+ ) -+{ -+ gceSTATUS status; -+ gctINT result; -+ struct task_struct * userTask; -+ struct siginfo info; -+ -+ userTask = FIND_TASK_BY_PID((pid_t)(gctUINTPTR_T) Process); -+ -+ if (userTask != gcvNULL) -+ { -+ info.si_signo = 48; -+ info.si_code = __SI_CODE(__SI_RT, SI_KERNEL); -+ info.si_pid = 0; -+ info.si_uid = 0; -+ info.si_ptr = (gctPOINTER) Signal; -+ -+ /* Signals with numbers between 32 and 63 are real-time, -+ send a real-time signal to the user process. */ -+ result = send_sig_info(48, &info, userTask); -+ -+ /* Error? */ -+ if (result < 0) -+ { -+ status = gcvSTATUS_GENERIC_IO; -+ -+ gcmkTRACE( -+ gcvLEVEL_ERROR, -+ "%s(%d): an error has occurred.\n", -+ __FUNCTION__, __LINE__ -+ ); -+ } -+ else -+ { -+ status = gcvSTATUS_OK; -+ } -+ } -+ else -+ { -+ status = gcvSTATUS_GENERIC_IO; -+ -+ gcmkTRACE( -+ gcvLEVEL_ERROR, -+ "%s(%d): an error has occurred.\n", -+ __FUNCTION__, __LINE__ -+ ); -+ } -+ -+ /* Return status. */ -+ return status; -+} -+ -+/******************************************************************************\ -+******************************** Thread Object ********************************* -+\******************************************************************************/ -+ -+gceSTATUS -+gckOS_StartThread( -+ IN gckOS Os, -+ IN gctTHREADFUNC ThreadFunction, -+ IN gctPOINTER ThreadParameter, -+ OUT gctTHREAD * Thread -+ ) -+{ -+ gceSTATUS status; -+ struct task_struct * thread; -+ -+ gcmkHEADER_ARG("Os=0x%X ", Os); -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(ThreadFunction != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Thread != gcvNULL); -+ -+ do -+ { -+ /* Create the thread. */ -+ thread = kthread_create( -+ ThreadFunction, -+ ThreadParameter, -+ "Vivante Kernel Thread" -+ ); -+ -+ /* Failed? */ -+ if (IS_ERR(thread)) -+ { -+ status = gcvSTATUS_GENERIC_IO; -+ break; -+ } -+ -+ /* Start the thread. */ -+ wake_up_process(thread); -+ -+ /* Set the thread handle. */ -+ * Thread = (gctTHREAD) thread; -+ -+ /* Success. */ -+ status = gcvSTATUS_OK; -+ } -+ while (gcvFALSE); -+ -+ gcmkFOOTER(); -+ /* Return the status. */ -+ return status; -+} -+ -+gceSTATUS -+gckOS_StopThread( -+ IN gckOS Os, -+ IN gctTHREAD Thread -+ ) -+{ -+ gcmkHEADER_ARG("Os=0x%X Thread=0x%x", Os, Thread); -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Thread != gcvNULL); -+ -+ /* Thread should have already been enabled to terminate. */ -+ kthread_stop((struct task_struct *) Thread); -+ -+ gcmkFOOTER_NO(); -+ /* Success. */ -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckOS_VerifyThread( -+ IN gckOS Os, -+ IN gctTHREAD Thread -+ ) -+{ -+ gcmkHEADER_ARG("Os=0x%X Thread=0x%x", Os, Thread); -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Thread != gcvNULL); -+ -+ gcmkFOOTER_NO(); -+ /* Success. */ -+ return gcvSTATUS_OK; -+} -+#endif -+ -+/******************************************************************************\ -+******************************** Software Timer ******************************** -+\******************************************************************************/ -+ -+void -+_TimerFunction( -+ struct work_struct * work -+ ) -+{ -+ gcsOSTIMER_PTR timer = (gcsOSTIMER_PTR)work; -+ -+ gctTIMERFUNCTION function = timer->function; -+ -+ function(timer->data); -+} -+ -+/******************************************************************************* -+** -+** gckOS_CreateTimer -+** -+** Create a software timer. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to the gckOS object. -+** -+** gctTIMERFUNCTION Function. -+** Pointer to a call back function which will be called when timer is -+** expired. -+** -+** gctPOINTER Data. -+** Private data which will be passed to call back function. -+** -+** OUTPUT: -+** -+** gctPOINTER * Timer -+** Pointer to a variable receiving the created timer. -+*/ -+gceSTATUS -+gckOS_CreateTimer( -+ IN gckOS Os, -+ IN gctTIMERFUNCTION Function, -+ IN gctPOINTER Data, -+ OUT gctPOINTER * Timer -+ ) -+{ -+ gceSTATUS status; -+ gcsOSTIMER_PTR pointer; -+ gcmkHEADER_ARG("Os=0x%X Function=0x%X Data=0x%X", Os, Function, Data); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Timer != gcvNULL); -+ -+ gcmkONERROR(gckOS_Allocate(Os, sizeof(gcsOSTIMER), (gctPOINTER)&pointer)); -+ -+ pointer->function = Function; -+ pointer->data = Data; -+ -+ INIT_DELAYED_WORK(&pointer->work, _TimerFunction); -+ -+ *Timer = pointer; -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckOS_DestroyTimer -+** -+** Destory a software timer. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to the gckOS object. -+** -+** gctPOINTER Timer -+** Pointer to the timer to be destoryed. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_DestroyTimer( -+ IN gckOS Os, -+ IN gctPOINTER Timer -+ ) -+{ -+ gcsOSTIMER_PTR timer; -+ gcmkHEADER_ARG("Os=0x%X Timer=0x%X", Os, Timer); -+ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Timer != gcvNULL); -+ -+ timer = (gcsOSTIMER_PTR)Timer; -+ -+ cancel_delayed_work_sync(&timer->work); -+ -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Os, Timer)); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_StartTimer -+** -+** Schedule a software timer. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to the gckOS object. -+** -+** gctPOINTER Timer -+** Pointer to the timer to be scheduled. -+** -+** gctUINT32 Delay -+** Delay in milliseconds. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_StartTimer( -+ IN gckOS Os, -+ IN gctPOINTER Timer, -+ IN gctUINT32 Delay -+ ) -+{ -+ gcsOSTIMER_PTR timer; -+ -+ gcmkHEADER_ARG("Os=0x%X Timer=0x%X Delay=%u", Os, Timer, Delay); -+ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Timer != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Delay != 0); -+ -+ timer = (gcsOSTIMER_PTR)Timer; -+ -+ mod_delayed_work(Os->workqueue, &timer->work, msecs_to_jiffies(Delay)); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_StopTimer -+** -+** Cancel a unscheduled timer. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to the gckOS object. -+** -+** gctPOINTER Timer -+** Pointer to the timer to be cancel. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_StopTimer( -+ IN gckOS Os, -+ IN gctPOINTER Timer -+ ) -+{ -+ gcsOSTIMER_PTR timer; -+ gcmkHEADER_ARG("Os=0x%X Timer=0x%X", Os, Timer); -+ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Timer != gcvNULL); -+ -+ timer = (gcsOSTIMER_PTR)Timer; -+ -+ cancel_delayed_work(&timer->work); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckOS_GetProcessNameByPid( -+ IN gctINT Pid, -+ IN gctSIZE_T Length, -+ OUT gctUINT8_PTR String -+ ) -+{ -+ struct task_struct *task; -+ -+ /* Get the task_struct of the task with pid. */ -+ rcu_read_lock(); -+ -+ task = FIND_TASK_BY_PID(Pid); -+ -+ if (task == gcvNULL) -+ { -+ rcu_read_unlock(); -+ return gcvSTATUS_NOT_FOUND; -+ } -+ -+ /* Get name of process. */ -+ strncpy(String, task->comm, Length); -+ -+ rcu_read_unlock(); -+ -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckOS_DumpCallStack( -+ IN gckOS Os -+ ) -+{ -+ gcmkHEADER_ARG("Os=0x%X", Os); -+ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ -+ dump_stack(); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckOS_DetectProcessByName -+** -+** task->comm maybe part of process name, so this function -+** can only be used for debugging. -+** -+** INPUT: -+** -+** gctCONST_POINTER Name -+** Pointer to a string to hold name to be check. If the length -+** of name is longer than TASK_COMM_LEN (16), use part of name -+** to detect. -+** -+** OUTPUT: -+** -+** gcvSTATUS_TRUE if name of current process matches Name. -+** -+*/ -+gceSTATUS -+gckOS_DetectProcessByName( -+ IN gctCONST_POINTER Name -+ ) -+{ -+ char comm[sizeof(current->comm)]; -+ -+ memset(comm, 0, sizeof(comm)); -+ -+ gcmkVERIFY_OK( -+ gckOS_GetProcessNameByPid(_GetProcessID(), sizeof(current->comm), comm)); -+ -+ return strstr(comm, Name) ? gcvSTATUS_TRUE -+ : gcvSTATUS_FALSE; -+} -+ -+#if gcdANDROID_NATIVE_FENCE_SYNC -+ -+gceSTATUS -+gckOS_CreateSyncPoint( -+ IN gckOS Os, -+ OUT gctSYNC_POINT * SyncPoint -+ ) -+{ -+ gceSTATUS status; -+ gcsSYNC_POINT_PTR syncPoint; -+ -+ gcmkHEADER_ARG("Os=0x%X", Os); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ -+ /* Create an sync point structure. */ -+ syncPoint = (gcsSYNC_POINT_PTR) kmalloc( -+ sizeof(gcsSYNC_POINT), GFP_KERNEL | gcdNOWARN); -+ -+ if (syncPoint == gcvNULL) -+ { -+ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); -+ } -+ -+ /* Initialize the sync point. */ -+ atomic_set(&syncPoint->ref, 1); -+ atomic_set(&syncPoint->state, 0); -+ -+ gcmkONERROR(_AllocateIntegerId(&Os->syncPointDB, syncPoint, &syncPoint->id)); -+ -+ *SyncPoint = (gctSYNC_POINT)(gctUINTPTR_T)syncPoint->id; -+ -+ gcmkFOOTER_ARG("*SyncPonint=%d", syncPoint->id); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (syncPoint != gcvNULL) -+ { -+ kfree(syncPoint); -+ } -+ -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckOS_ReferenceSyncPoint( -+ IN gckOS Os, -+ IN gctSYNC_POINT SyncPoint -+ ) -+{ -+ gceSTATUS status; -+ gcsSYNC_POINT_PTR syncPoint; -+ -+ gcmkHEADER_ARG("Os=0x%X", Os); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(SyncPoint != gcvNULL); -+ -+ gcmkONERROR( -+ _QueryIntegerId(&Os->syncPointDB, -+ (gctUINT32)(gctUINTPTR_T)SyncPoint, -+ (gctPOINTER)&syncPoint)); -+ -+ /* Initialize the sync point. */ -+ atomic_inc(&syncPoint->ref); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckOS_DestroySyncPoint( -+ IN gckOS Os, -+ IN gctSYNC_POINT SyncPoint -+ ) -+{ -+ gceSTATUS status; -+ gcsSYNC_POINT_PTR syncPoint; -+ gctBOOL acquired = gcvFALSE; -+ -+ gcmkHEADER_ARG("Os=0x%X SyncPoint=%d", Os, (gctUINT32)(gctUINTPTR_T)SyncPoint); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(SyncPoint != gcvNULL); -+ -+ gcmkONERROR(gckOS_AcquireMutex(Os, Os->syncPointMutex, gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ gcmkONERROR( -+ _QueryIntegerId(&Os->syncPointDB, -+ (gctUINT32)(gctUINTPTR_T)SyncPoint, -+ (gctPOINTER)&syncPoint)); -+ -+ gcmkASSERT(syncPoint->id == (gctUINT32)(gctUINTPTR_T)SyncPoint); -+ -+ if (atomic_dec_and_test(&syncPoint->ref)) -+ { -+ gcmkVERIFY_OK(_DestroyIntegerId(&Os->syncPointDB, syncPoint->id)); -+ -+ /* Free the sgianl. */ -+ syncPoint->timeline = gcvNULL; -+ kfree(syncPoint); -+ } -+ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->syncPointMutex)); -+ acquired = gcvFALSE; -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (acquired) -+ { -+ /* Release the mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->syncPointMutex)); -+ } -+ -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckOS_SignalSyncPoint( -+ IN gckOS Os, -+ IN gctSYNC_POINT SyncPoint -+ ) -+{ -+ gceSTATUS status; -+ gcsSYNC_POINT_PTR syncPoint; -+ struct sync_timeline * timeline; -+ gctBOOL acquired = gcvFALSE; -+ -+ gcmkHEADER_ARG("Os=0x%X SyncPoint=%d", Os, (gctUINT32)(gctUINTPTR_T)SyncPoint); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(SyncPoint != gcvNULL); -+ -+ gcmkONERROR(gckOS_AcquireMutex(Os, Os->syncPointMutex, gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ gcmkONERROR( -+ _QueryIntegerId(&Os->syncPointDB, -+ (gctUINT32)(gctUINTPTR_T)SyncPoint, -+ (gctPOINTER)&syncPoint)); -+ -+ gcmkASSERT(syncPoint->id == (gctUINT32)(gctUINTPTR_T)SyncPoint); -+ -+ /* Set signaled state. */ -+ atomic_set(&syncPoint->state, 1); -+ -+ /* Get parent timeline. */ -+ timeline = syncPoint->timeline; -+ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->syncPointMutex)); -+ acquired = gcvFALSE; -+ -+ /* Signal timeline. */ -+ if (timeline) -+ { -+ sync_timeline_signal(timeline); -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (acquired) -+ { -+ /* Release the mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Os, Os->syncPointMutex)); -+ } -+ -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckOS_QuerySyncPoint( -+ IN gckOS Os, -+ IN gctSYNC_POINT SyncPoint, -+ OUT gctBOOL_PTR State -+ ) -+{ -+ gceSTATUS status; -+ gcsSYNC_POINT_PTR syncPoint; -+ -+ gcmkHEADER_ARG("Os=0x%X SyncPoint=%d", Os, (gctUINT32)(gctUINTPTR_T)SyncPoint); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(SyncPoint != gcvNULL); -+ -+ gcmkONERROR( -+ _QueryIntegerId(&Os->syncPointDB, -+ (gctUINT32)(gctUINTPTR_T)SyncPoint, -+ (gctPOINTER)&syncPoint)); -+ -+ gcmkASSERT(syncPoint->id == (gctUINT32)(gctUINTPTR_T)SyncPoint); -+ -+ /* Get state. */ -+ *State = atomic_read(&syncPoint->state); -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*State=%d", *State); -+ return gcvSTATUS_OK; -+ -+OnError: -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckOS_CreateSyncTimeline( -+ IN gckOS Os, -+ OUT gctHANDLE * Timeline -+ ) -+{ -+ struct viv_sync_timeline * timeline; -+ -+ /* Create viv sync timeline. */ -+ timeline = viv_sync_timeline_create("viv timeline", Os); -+ -+ if (timeline == gcvNULL) -+ { -+ /* Out of memory. */ -+ return gcvSTATUS_OUT_OF_MEMORY; -+ } -+ -+ *Timeline = (gctHANDLE) timeline; -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckOS_DestroySyncTimeline( -+ IN gckOS Os, -+ IN gctHANDLE Timeline -+ ) -+{ -+ struct viv_sync_timeline * timeline; -+ gcmkASSERT(Timeline != gcvNULL); -+ -+ /* Destroy timeline. */ -+ timeline = (struct viv_sync_timeline *) Timeline; -+ sync_timeline_destroy(&timeline->obj); -+ -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckOS_CreateNativeFence( -+ IN gckOS Os, -+ IN gctHANDLE Timeline, -+ IN gctSYNC_POINT SyncPoint, -+ OUT gctINT * FenceFD -+ ) -+{ -+ int fd = -1; -+ struct viv_sync_timeline *timeline; -+ struct sync_pt * pt = gcvNULL; -+ struct sync_fence * fence; -+ char name[32]; -+ gcsSYNC_POINT_PTR syncPoint; -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Os=0x%X Timeline=0x%X SyncPoint=%d", -+ Os, Timeline, (gctUINT)(gctUINTPTR_T)SyncPoint); -+ -+ gcmkONERROR( -+ _QueryIntegerId(&Os->syncPointDB, -+ (gctUINT32)(gctUINTPTR_T)SyncPoint, -+ (gctPOINTER)&syncPoint)); -+ -+ /* Cast timeline. */ -+ timeline = (struct viv_sync_timeline *) Timeline; -+ -+ fd = get_unused_fd(); -+ -+ if (fd < 0) -+ { -+ /* Out of resources. */ -+ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES); -+ } -+ -+ /* Create viv_sync_pt. */ -+ pt = viv_sync_pt_create(timeline, SyncPoint); -+ -+ if (pt == gcvNULL) -+ { -+ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); -+ } -+ -+ /* Reference sync_timeline. */ -+ syncPoint->timeline = &timeline->obj; -+ -+ /* Build fence name. */ -+ snprintf(name, 32, "viv sync_fence-%u", (gctUINT)(gctUINTPTR_T)SyncPoint); -+ -+ /* Create sync_fence. */ -+ fence = sync_fence_create(name, pt); -+ -+ if (fence == NULL) -+ { -+ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); -+ } -+ -+ /* Install fence to fd. */ -+ sync_fence_install(fence, fd); -+ -+ *FenceFD = fd; -+ gcmkFOOTER_ARG("*FenceFD=%d", fd); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Error roll back. */ -+ if (pt) -+ { -+ sync_pt_free(pt); -+ } -+ -+ if (fd > 0) -+ { -+ put_unused_fd(fd); -+ } -+ -+ gcmkFOOTER(); -+ return status; -+} -+#endif -+ -+gceSTATUS -+gckOS_CPUPhysicalToGPUPhysical( -+ IN gckOS Os, -+ IN gctUINT32 CPUPhysical, -+ IN gctUINT32_PTR GPUPhysical -+ ) -+{ -+ gcsPLATFORM * platform; -+ gcmkHEADER_ARG("CPUPhysical=0x%X", CPUPhysical); -+ -+ platform = Os->device->platform; -+ -+ if (platform && platform->ops->getGPUPhysical) -+ { -+ gcmkVERIFY_OK( -+ platform->ops->getGPUPhysical(platform, CPUPhysical, GPUPhysical)); -+ } -+ else -+ { -+ *GPUPhysical = CPUPhysical; -+ } -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckOS_GPUPhysicalToCPUPhysical( -+ IN gckOS Os, -+ IN gctUINT32 GPUPhysical, -+ IN gctUINT32_PTR CPUPhysical -+ ) -+{ -+ gcmkHEADER_ARG("GPUPhysical=0x%X", GPUPhysical); -+ -+ *CPUPhysical = GPUPhysical; -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckOS_PhysicalToPhysicalAddress( -+ IN gckOS Os, -+ IN gctPOINTER Physical, -+ OUT gctUINT32 * PhysicalAddress -+ ) -+{ -+ PLINUX_MDL mdl = (PLINUX_MDL)Physical; -+ gckALLOCATOR allocator = mdl->allocator; -+ -+ if (allocator) -+ { -+ return allocator->ops->Physical(allocator, mdl, 0, PhysicalAddress); -+ } -+ -+ return gcvSTATUS_NOT_SUPPORTED; -+} -+ -+gceSTATUS -+gckOS_QueryOption( -+ IN gckOS Os, -+ IN gctCONST_STRING Option, -+ OUT gctUINT32 * Value -+ ) -+{ -+ gckGALDEVICE device = Os->device; -+ -+ if (!strcmp(Option, "physBase")) -+ { -+ *Value = device->physBase; -+ return gcvSTATUS_OK; -+ } -+ else if (!strcmp(Option, "physSize")) -+ { -+ *Value = device->physSize; -+ return gcvSTATUS_OK; -+ } -+ else if (!strcmp(Option, "mmu")) -+ { -+ *Value = device->mmu; -+ return gcvSTATUS_OK; -+ } -+ -+ return gcvSTATUS_NOT_SUPPORTED; -+} -+ -+static int -+fd_release( -+ struct inode *inode, -+ struct file *file -+ ) -+{ -+ gcsFDPRIVATE_PTR private = (gcsFDPRIVATE_PTR)file->private_data; -+ -+ if (private && private->release) -+ { -+ return private->release(private); -+ } -+ -+ return 0; -+} -+ -+static const struct file_operations fd_fops = { -+ .release = fd_release, -+}; -+ -+gceSTATUS -+gckOS_GetFd( -+ IN gctSTRING Name, -+ IN gcsFDPRIVATE_PTR Private, -+ OUT gctINT *Fd -+ ) -+{ -+ *Fd = anon_inode_getfd(Name, &fd_fops, Private, O_RDWR); -+ -+ if (*Fd < 0) -+ { -+ return gcvSTATUS_OUT_OF_RESOURCES; -+ } -+ -+ return gcvSTATUS_OK; -+} -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_os.h linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_os.h ---- linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_os.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_os.h 2015-11-30 17:56:13.584137459 +0100 -@@ -0,0 +1,88 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#ifndef __gc_hal_kernel_os_h_ -+#define __gc_hal_kernel_os_h_ -+ -+typedef struct _LINUX_MDL_MAP -+{ -+ gctINT pid; -+ gctPOINTER vmaAddr; -+ gctUINT32 count; -+ struct vm_area_struct * vma; -+ struct _LINUX_MDL_MAP * next; -+} -+LINUX_MDL_MAP; -+ -+typedef struct _LINUX_MDL_MAP * PLINUX_MDL_MAP; -+ -+typedef struct _LINUX_MDL -+{ -+ char * addr; -+ -+ union _pages -+ { -+ /* Pointer to a array of pages. */ -+ struct page * contiguousPages; -+ /* Pointer to a array of pointers to page. */ -+ struct page ** nonContiguousPages; -+ } -+ u; -+ -+#ifdef NO_DMA_COHERENT -+ gctPOINTER kaddr; -+#endif /* NO_DMA_COHERENT */ -+ -+ gctINT numPages; -+ gctINT pagedMem; -+ gctBOOL contiguous; -+ gctBOOL exact; -+ dma_addr_t dmaHandle; -+ PLINUX_MDL_MAP maps; -+ struct _LINUX_MDL * prev; -+ struct _LINUX_MDL * next; -+ -+ /* Pointer to allocator which allocates memory for this mdl. */ -+ void * allocator; -+ -+ /* Private data used by allocator. */ -+ void * priv; -+ -+ uint gid; -+} -+LINUX_MDL, *PLINUX_MDL; -+ -+extern PLINUX_MDL_MAP -+FindMdlMap( -+ IN PLINUX_MDL Mdl, -+ IN gctINT PID -+ ); -+ -+typedef struct _DRIVER_ARGS -+{ -+ gctUINT64 InputBuffer; -+ gctUINT64 InputBufferSize; -+ gctUINT64 OutputBuffer; -+ gctUINT64 OutputBufferSize; -+} -+DRIVER_ARGS; -+ -+#endif /* __gc_hal_kernel_os_h_ */ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_platform.h linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_platform.h ---- linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_platform.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_platform.h 2015-11-30 17:56:13.584137459 +0100 -@@ -0,0 +1,270 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#ifndef _gc_hal_kernel_platform_h_ -+#define _gc_hal_kernel_platform_h_ -+#include -+ -+typedef struct _gcsMODULE_PARAMETERS -+{ -+ gctINT irqLine; -+ gctUINT registerMemBase; -+ gctUINT registerMemSize; -+ gctINT irqLine2D; -+ gctUINT registerMemBase2D; -+ gctUINT registerMemSize2D; -+ gctINT irqLineVG; -+ gctUINT registerMemBaseVG; -+ gctUINT registerMemSizeVG; -+ gctUINT contiguousSize; -+ gctUINT contiguousBase; -+ gctUINT contiguousRequested; -+ gctUINT bankSize; -+ gctINT fastClear; -+ gctINT compression; -+ gctINT powerManagement; -+ gctINT gpuProfiler; -+ gctINT signal; -+ gctUINT baseAddress; -+ gctUINT physSize; -+ gctUINT logFileSize; -+ gctUINT recovery; -+ gctUINT stuckDump; -+ gctUINT showArgs; -+ gctUINT gpu3DMinClock; -+} -+gcsMODULE_PARAMETERS; -+ -+typedef struct _gcsPLATFORM * gckPLATFORM; -+ -+typedef struct _gcsPLATFORM_OPERATIONS -+{ -+ /******************************************************************************* -+ ** -+ ** needAddDevice -+ ** -+ ** Determine whether platform_device is created by initialization code. -+ ** If platform_device is created by BSP, return gcvFLASE here. -+ */ -+ gctBOOL -+ (*needAddDevice)( -+ IN gckPLATFORM Platform -+ ); -+ -+ /******************************************************************************* -+ ** -+ ** adjustParam -+ ** -+ ** Override content of arguments, if a argument is not changed here, it will -+ ** keep as default value or value set by insmod command line. -+ */ -+ gceSTATUS -+ (*adjustParam)( -+ IN gckPLATFORM Platform, -+ OUT gcsMODULE_PARAMETERS *Args -+ ); -+ -+ /******************************************************************************* -+ ** -+ ** adjustDriver -+ ** -+ ** Override content of platform_driver which will be registered. -+ */ -+ gceSTATUS -+ (*adjustDriver)( -+ IN gckPLATFORM Platform -+ ); -+ -+ /******************************************************************************* -+ ** -+ ** getPower -+ ** -+ ** Prepare power and clock operation. -+ */ -+ gceSTATUS -+ (*getPower)( -+ IN gckPLATFORM Platform -+ ); -+ -+ /******************************************************************************* -+ ** -+ ** putPower -+ ** -+ ** Finish power and clock operation. -+ */ -+ gceSTATUS -+ (*putPower)( -+ IN gckPLATFORM Platform -+ ); -+ -+ /******************************************************************************* -+ ** -+ ** allocPriv -+ ** -+ ** Construct platform private data. -+ */ -+ gceSTATUS -+ (*allocPriv)( -+ IN gckPLATFORM Platform -+ ); -+ -+ /******************************************************************************* -+ ** -+ ** freePriv -+ ** -+ ** free platform private data. -+ */ -+ gceSTATUS -+ (*freePriv)( -+ IN gckPLATFORM Platform -+ ); -+ -+ /******************************************************************************* -+ ** -+ ** setPower -+ ** -+ ** Set power state of specified GPU. -+ ** -+ ** INPUT: -+ ** -+ ** gceCORE GPU -+ ** GPU neeed to config. -+ ** -+ ** gceBOOL Enable -+ ** Enable or disable power. -+ */ -+ gceSTATUS -+ (*setPower)( -+ IN gckPLATFORM Platform, -+ IN gceCORE GPU, -+ IN gctBOOL Enable -+ ); -+ -+ /******************************************************************************* -+ ** -+ ** setClock -+ ** -+ ** Set clock state of specified GPU. -+ ** -+ ** INPUT: -+ ** -+ ** gceCORE GPU -+ ** GPU neeed to config. -+ ** -+ ** gceBOOL Enable -+ ** Enable or disable clock. -+ */ -+ gceSTATUS -+ (*setClock)( -+ IN gckPLATFORM Platform, -+ IN gceCORE GPU, -+ IN gctBOOL Enable -+ ); -+ -+ /******************************************************************************* -+ ** -+ ** reset -+ ** -+ ** Reset GPU outside. -+ ** -+ ** INPUT: -+ ** -+ ** gceCORE GPU -+ ** GPU neeed to reset. -+ */ -+ gceSTATUS -+ (*reset)( -+ IN gckPLATFORM Platform, -+ IN gceCORE GPU -+ ); -+ -+ /******************************************************************************* -+ ** -+ ** getGPUPhysical -+ ** -+ ** Convert CPU physical address to GPU physical address if they are -+ ** different. -+ */ -+ gceSTATUS -+ (*getGPUPhysical)( -+ IN gckPLATFORM Platform, -+ IN gctUINT32 CPUPhysical, -+ OUT gctUINT32_PTR GPUPhysical -+ ); -+ -+ /******************************************************************************* -+ ** -+ ** adjustProt -+ ** -+ ** Override Prot flag when mapping paged memory to userspace. -+ */ -+ gceSTATUS -+ (*adjustProt)( -+ IN struct vm_area_struct * vma -+ ); -+ -+ /******************************************************************************* -+ ** -+ ** shrinkMemory -+ ** -+ ** Do something to collect memory, eg, act as oom killer. -+ */ -+ gceSTATUS -+ (*shrinkMemory)( -+ IN gckPLATFORM Platform -+ ); -+ -+ /******************************************************************************* -+ ** -+ ** cache -+ ** -+ ** Cache operation. -+ */ -+ gceSTATUS -+ (*cache)( -+ IN gckPLATFORM Platform, -+ IN gctUINT32 ProcessID, -+ IN gctPHYS_ADDR Handle, -+ IN gctUINT32 Physical, -+ IN gctPOINTER Logical, -+ IN gctSIZE_T Bytes, -+ IN gceCACHEOPERATION Operation -+ ); -+} -+gcsPLATFORM_OPERATIONS; -+ -+typedef struct _gcsPLATFORM -+{ -+ struct platform_device* device; -+ struct platform_driver* driver; -+ -+ gcsPLATFORM_OPERATIONS* ops; -+ -+ void* priv; -+} -+gcsPLATFORM; -+ -+void -+gckPLATFORM_QueryOperations( -+ IN gcsPLATFORM_OPERATIONS ** Operations -+ ); -+ -+#endif -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_power.c linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_power.c ---- linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_power.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_power.c 2015-11-30 17:56:13.584137459 +0100 -@@ -0,0 +1,347 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#include "gc_hal_kernel_precomp.h" -+ -+#define _GC_OBJ_ZONE gcvZONE_POWER -+ -+/******************************************************************************\ -+************************ Dynamic Voltage Frequency Setting ********************* -+\******************************************************************************/ -+#if gcdDVFS -+static gctUINT32 -+_GetLoadHistory( -+ IN gckDVFS Dvfs, -+ IN gctUINT32 Select, -+ IN gctUINT32 Index -+) -+{ -+ return Dvfs->loads[Index]; -+} -+ -+static void -+_IncreaseScale( -+ IN gckDVFS Dvfs, -+ IN gctUINT32 Load, -+ OUT gctUINT8 *Scale -+ ) -+{ -+ if (Dvfs->currentScale < 32) -+ { -+ *Scale = Dvfs->currentScale + 8; -+ } -+ else -+ { -+ *Scale = Dvfs->currentScale + 8; -+ *Scale = gcmMIN(64, *Scale); -+ } -+} -+ -+static void -+_RecordFrequencyHistory( -+ gckDVFS Dvfs, -+ gctUINT32 Frequency -+ ) -+{ -+ gctUINT32 i = 0; -+ -+ struct _FrequencyHistory *history = Dvfs->frequencyHistory; -+ -+ for (i = 0; i < 16; i++) -+ { -+ if (history->frequency == Frequency) -+ { -+ break; -+ } -+ -+ if (history->frequency == 0) -+ { -+ history->frequency = Frequency; -+ break; -+ } -+ -+ history++; -+ } -+ -+ if (i < 16) -+ { -+ history->count++; -+ } -+} -+ -+static gctUINT32 -+_GetFrequencyHistory( -+ gckDVFS Dvfs, -+ gctUINT32 Frequency -+ ) -+{ -+ gctUINT32 i = 0; -+ -+ struct _FrequencyHistory * history = Dvfs->frequencyHistory; -+ -+ for (i = 0; i < 16; i++) -+ { -+ if (history->frequency == Frequency) -+ { -+ break; -+ } -+ -+ history++; -+ } -+ -+ if (i < 16) -+ { -+ return history->count; -+ } -+ -+ return 0; -+} -+ -+static void -+_Policy( -+ IN gckDVFS Dvfs, -+ IN gctUINT32 Load, -+ OUT gctUINT8 *Scale -+ ) -+{ -+ gctUINT8 load[4], nextLoad; -+ gctUINT8 scale; -+ -+ /* Last 4 history. */ -+ load[0] = (Load & 0xFF); -+ load[1] = (Load & 0xFF00) >> 8; -+ load[2] = (Load & 0xFF0000) >> 16; -+ load[3] = (Load & 0xFF000000) >> 24; -+ -+ /* Determine target scale. */ -+ if (load[0] > 54) -+ { -+ _IncreaseScale(Dvfs, Load, &scale); -+ } -+ else -+ { -+ nextLoad = (load[0] + load[1] + load[2] + load[3])/4; -+ -+ scale = Dvfs->currentScale * (nextLoad) / 54; -+ -+ scale = gcmMAX(1, scale); -+ scale = gcmMIN(64, scale); -+ } -+ -+ Dvfs->totalConfig++; -+ -+ Dvfs->loads[(load[0]-1)/8]++; -+ -+ *Scale = scale; -+ -+ -+ if (Dvfs->totalConfig % 100 == 0) -+ { -+ gcmkPRINT("======================================================="); -+ gcmkPRINT("GPU Load: %-8d %-8d %-8d %-8d %-8d %-8d %-8d %-8d", -+ 8, 16, 24, 32, 40, 48, 56, 64); -+ gcmkPRINT(" %-8d %-8d %-8d %-8d %-8d %-8d %-8d %-8d", -+ _GetLoadHistory(Dvfs,2, 0), -+ _GetLoadHistory(Dvfs,2, 1), -+ _GetLoadHistory(Dvfs,2, 2), -+ _GetLoadHistory(Dvfs,2, 3), -+ _GetLoadHistory(Dvfs,2, 4), -+ _GetLoadHistory(Dvfs,2, 5), -+ _GetLoadHistory(Dvfs,2, 6), -+ _GetLoadHistory(Dvfs,2, 7) -+ ); -+ -+ gcmkPRINT("Frequency(MHz) %-8d %-8d %-8d %-8d %-8d", -+ 58, 120, 240, 360, 480); -+ gcmkPRINT(" %-8d %-8d %-8d %-8d %-8d", -+ _GetFrequencyHistory(Dvfs, 58), -+ _GetFrequencyHistory(Dvfs,120), -+ _GetFrequencyHistory(Dvfs,240), -+ _GetFrequencyHistory(Dvfs,360), -+ _GetFrequencyHistory(Dvfs,480) -+ ); -+ } -+} -+ -+static void -+_TimerFunction( -+ gctPOINTER Data -+ ) -+{ -+ gceSTATUS status; -+ gckDVFS dvfs = (gckDVFS) Data; -+ gckHARDWARE hardware = dvfs->hardware; -+ gctUINT32 value; -+ gctUINT32 frequency; -+ gctUINT8 scale; -+ gctUINT32 t1, t2, consumed; -+ -+ gckOS_GetTicks(&t1); -+ -+ gcmkONERROR(gckHARDWARE_QueryLoad(hardware, &value)); -+ -+ /* determine target sacle. */ -+ _Policy(dvfs, value, &scale); -+ -+ /* Set frequency and voltage. */ -+ gcmkONERROR(gckOS_SetGPUFrequency(hardware->os, hardware->core, scale)); -+ -+ /* Query real frequency. */ -+ gcmkONERROR( -+ gckOS_QueryGPUFrequency(hardware->os, -+ hardware->core, -+ &frequency, -+ &dvfs->currentScale)); -+ -+ _RecordFrequencyHistory(dvfs, frequency); -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_POWER, -+ "Current frequency = %d", -+ frequency); -+ -+ /* Set period. */ -+ gcmkONERROR(gckHARDWARE_SetDVFSPeroid(hardware, frequency)); -+ -+OnError: -+ /* Determine next querying time. */ -+ gckOS_GetTicks(&t2); -+ -+ consumed = gcmMIN(((long)t2 - (long)t1), 5); -+ -+ if (dvfs->stop == gcvFALSE) -+ { -+ gcmkVERIFY_OK(gckOS_StartTimer(hardware->os, -+ dvfs->timer, -+ dvfs->pollingTime - consumed)); -+ } -+ -+ return; -+} -+ -+gceSTATUS -+gckDVFS_Construct( -+ IN gckHARDWARE Hardware, -+ OUT gckDVFS * Dvfs -+ ) -+{ -+ gceSTATUS status; -+ gctPOINTER pointer; -+ gckDVFS dvfs = gcvNULL; -+ gckOS os = Hardware->os; -+ -+ gcmkHEADER_ARG("Hardware=0x%X", Hardware); -+ -+ gcmkVERIFY_OBJECT(Hardware, gcvOBJ_HARDWARE); -+ gcmkVERIFY_ARGUMENT(Dvfs != gcvNULL); -+ -+ /* Allocate a gckDVFS manager. */ -+ gcmkONERROR(gckOS_Allocate(os, gcmSIZEOF(struct _gckDVFS), &pointer)); -+ -+ gckOS_ZeroMemory(pointer, gcmSIZEOF(struct _gckDVFS)); -+ -+ dvfs = pointer; -+ -+ /* Initialization. */ -+ dvfs->hardware = Hardware; -+ dvfs->pollingTime = gcdDVFS_POLLING_TIME; -+ dvfs->os = Hardware->os; -+ dvfs->currentScale = 64; -+ -+ /* Create a polling timer. */ -+ gcmkONERROR(gckOS_CreateTimer(os, _TimerFunction, pointer, &dvfs->timer)); -+ -+ /* Initialize frequency and voltage adjustment helper. */ -+ gcmkONERROR(gckOS_PrepareGPUFrequency(os, Hardware->core)); -+ -+ /* Return result. */ -+ *Dvfs = dvfs; -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Roll back. */ -+ if (dvfs) -+ { -+ if (dvfs->timer) -+ { -+ gcmkVERIFY_OK(gckOS_DestroyTimer(os, dvfs->timer)); -+ } -+ -+ gcmkOS_SAFE_FREE(os, dvfs); -+ } -+ -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckDVFS_Destroy( -+ IN gckDVFS Dvfs -+ ) -+{ -+ gcmkHEADER_ARG("Dvfs=0x%X", Dvfs); -+ gcmkVERIFY_ARGUMENT(Dvfs != gcvNULL); -+ -+ /* Deinitialize helper fuunction. */ -+ gcmkVERIFY_OK(gckOS_FinishGPUFrequency(Dvfs->os, Dvfs->hardware->core)); -+ -+ /* DestroyTimer. */ -+ gcmkVERIFY_OK(gckOS_DestroyTimer(Dvfs->os, Dvfs->timer)); -+ -+ gcmkOS_SAFE_FREE(Dvfs->os, Dvfs); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckDVFS_Start( -+ IN gckDVFS Dvfs -+ ) -+{ -+ gcmkHEADER_ARG("Dvfs=0x%X", Dvfs); -+ gcmkVERIFY_ARGUMENT(Dvfs != gcvNULL); -+ -+ gckHARDWARE_InitDVFS(Dvfs->hardware); -+ -+ Dvfs->stop = gcvFALSE; -+ -+ gckOS_StartTimer(Dvfs->os, Dvfs->timer, Dvfs->pollingTime); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckDVFS_Stop( -+ IN gckDVFS Dvfs -+ ) -+{ -+ gcmkHEADER_ARG("Dvfs=0x%X", Dvfs); -+ gcmkVERIFY_ARGUMENT(Dvfs != gcvNULL); -+ -+ Dvfs->stop = gcvTRUE; -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+#endif -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_precomp.h linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_precomp.h ---- linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_precomp.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_precomp.h 2015-11-30 17:56:13.584137459 +0100 -@@ -0,0 +1,29 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#ifndef __gc_hal_kernel_precomp_h_ -+#define __gc_hal_kernel_precomp_h_ -+ -+#include "gc_hal.h" -+#include "gc_hal_driver.h" -+#include "gc_hal_kernel.h" -+ -+#endif /* __gc_hal_kernel_precomp_h_ */ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_probe.c linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_probe.c ---- linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_probe.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_probe.c 2015-11-30 17:56:13.584137459 +0100 -@@ -0,0 +1,1252 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#include -+#include -+ -+#include "gc_hal_kernel_linux.h" -+#include "gc_hal_driver.h" -+ -+#include -+ -+#ifdef CONFIG_PXA_DVFM -+# include -+# include -+#endif -+ -+ -+/* Zone used for header/footer. */ -+#define _GC_OBJ_ZONE gcvZONE_DRIVER -+ -+MODULE_DESCRIPTION("Vivante Graphics Driver"); -+MODULE_LICENSE("GPL"); -+ -+static struct class* gpuClass; -+ -+static gcsPLATFORM platform; -+ -+static gckGALDEVICE galDevice; -+ -+static uint major = 199; -+module_param(major, uint, 0644); -+ -+static int irqLine = -1; -+module_param(irqLine, int, 0644); -+ -+static ulong registerMemBase = 0x80000000; -+module_param(registerMemBase, ulong, 0644); -+ -+static ulong registerMemSize = 2 << 10; -+module_param(registerMemSize, ulong, 0644); -+ -+static int irqLine2D = -1; -+module_param(irqLine2D, int, 0644); -+ -+static ulong registerMemBase2D = 0x00000000; -+module_param(registerMemBase2D, ulong, 0644); -+ -+static ulong registerMemSize2D = 2 << 10; -+module_param(registerMemSize2D, ulong, 0644); -+ -+static int irqLineVG = -1; -+module_param(irqLineVG, int, 0644); -+ -+static ulong registerMemBaseVG = 0x00000000; -+module_param(registerMemBaseVG, ulong, 0644); -+ -+static ulong registerMemSizeVG = 2 << 10; -+module_param(registerMemSizeVG, ulong, 0644); -+ -+#ifndef gcdDEFAULT_CONTIGUOUS_SIZE -+#define gcdDEFAULT_CONTIGUOUS_SIZE (4 << 20) -+#endif -+static ulong contiguousSize = gcdDEFAULT_CONTIGUOUS_SIZE; -+module_param(contiguousSize, ulong, 0644); -+ -+static ulong contiguousBase = 0; -+module_param(contiguousBase, ulong, 0644); -+ -+static ulong bankSize = 0; -+module_param(bankSize, ulong, 0644); -+ -+static int fastClear = -1; -+module_param(fastClear, int, 0644); -+ -+static int compression = -1; -+module_param(compression, int, 0644); -+ -+static int powerManagement = -1; -+module_param(powerManagement, int, 0644); -+ -+static int gpuProfiler = 0; -+module_param(gpuProfiler, int, 0644); -+ -+static int signal = 48; -+module_param(signal, int, 0644); -+ -+static ulong baseAddress = 0; -+module_param(baseAddress, ulong, 0644); -+ -+static ulong physSize = 0; -+module_param(physSize, ulong, 0644); -+ -+static uint logFileSize = 0; -+module_param(logFileSize,uint, 0644); -+ -+static uint recovery = 1; -+module_param(recovery, uint, 0644); -+MODULE_PARM_DESC(recovery, "Recover GPU from stuck (1: Enable, 0: Disable)"); -+ -+/* Middle needs about 40KB buffer, Maximal may need more than 200KB buffer. */ -+static uint stuckDump = 1; -+module_param(stuckDump, uint, 0644); -+MODULE_PARM_DESC(stuckDump, "Level of stuck dump content (1: Minimal, 2: Middle, 3: Maximal)"); -+ -+static int showArgs = 0; -+module_param(showArgs, int, 0644); -+ -+static int mmu = 1; -+module_param(mmu, int, 0644); -+ -+static int gpu3DMinClock = 1; -+ -+static int contiguousRequested = 0; -+ -+static int drv_open( -+ struct inode* inode, -+ struct file* filp -+ ); -+ -+static int drv_release( -+ struct inode* inode, -+ struct file* filp -+ ); -+ -+static long drv_ioctl( -+ struct file* filp, -+ unsigned int ioctlCode, -+ unsigned long arg -+ ); -+ -+static int drv_mmap( -+ struct file* filp, -+ struct vm_area_struct* vma -+ ); -+ -+static struct file_operations driver_fops = -+{ -+ .owner = THIS_MODULE, -+ .open = drv_open, -+ .release = drv_release, -+ .unlocked_ioctl = drv_ioctl, -+#ifdef HAVE_COMPAT_IOCTL -+ .compat_ioctl = drv_ioctl, -+#endif -+ .mmap = drv_mmap, -+}; -+ -+void -+_UpdateModuleParam( -+ gcsMODULE_PARAMETERS *Param -+ ) -+{ -+ irqLine = Param->irqLine ; -+ registerMemBase = Param->registerMemBase; -+ registerMemSize = Param->registerMemSize; -+ irqLine2D = Param->irqLine2D ; -+ registerMemBase2D = Param->registerMemBase2D; -+ registerMemSize2D = Param->registerMemSize2D; -+ irqLineVG = Param->irqLineVG; -+ registerMemBaseVG = Param->registerMemBaseVG; -+ registerMemSizeVG = Param->registerMemSizeVG; -+ contiguousSize = Param->contiguousSize; -+ contiguousBase = Param->contiguousBase; -+ bankSize = Param->bankSize; -+ fastClear = Param->fastClear; -+ compression = Param->compression; -+ powerManagement = Param->powerManagement; -+ gpuProfiler = Param->gpuProfiler; -+ signal = Param->signal; -+ baseAddress = Param->baseAddress; -+ physSize = Param->physSize; -+ logFileSize = Param->logFileSize; -+ recovery = Param->recovery; -+ stuckDump = Param->stuckDump; -+ showArgs = Param->showArgs; -+ contiguousRequested = Param->contiguousRequested; -+ gpu3DMinClock = Param->gpu3DMinClock; -+} -+ -+void -+gckOS_DumpParam( -+ void -+ ) -+{ -+ printk("Galcore options:\n"); -+ printk(" irqLine = %d\n", irqLine); -+ printk(" registerMemBase = 0x%08lX\n", registerMemBase); -+ printk(" registerMemSize = 0x%08lX\n", registerMemSize); -+ -+ if (irqLine2D != -1) -+ { -+ printk(" irqLine2D = %d\n", irqLine2D); -+ printk(" registerMemBase2D = 0x%08lX\n", registerMemBase2D); -+ printk(" registerMemSize2D = 0x%08lX\n", registerMemSize2D); -+ } -+ -+ if (irqLineVG != -1) -+ { -+ printk(" irqLineVG = %d\n", irqLineVG); -+ printk(" registerMemBaseVG = 0x%08lX\n", registerMemBaseVG); -+ printk(" registerMemSizeVG = 0x%08lX\n", registerMemSizeVG); -+ } -+ -+ printk(" contiguousSize = %ld\n", contiguousSize); -+ printk(" contiguousBase = 0x%08lX\n", contiguousBase); -+ printk(" bankSize = 0x%08lX\n", bankSize); -+ printk(" fastClear = %d\n", fastClear); -+ printk(" compression = %d\n", compression); -+ printk(" signal = %d\n", signal); -+ printk(" powerManagement = %d\n", powerManagement); -+ printk(" baseAddress = 0x%08lX\n", baseAddress); -+ printk(" physSize = 0x%08lX\n", physSize); -+ printk(" logFileSize = %d KB \n", logFileSize); -+ printk(" recovery = %d\n", recovery); -+ printk(" stuckDump = %d\n", stuckDump); -+ printk(" gpuProfiler = %d\n", gpuProfiler); -+} -+ -+int drv_open( -+ struct inode* inode, -+ struct file* filp -+ ) -+{ -+ gceSTATUS status; -+ gctBOOL attached = gcvFALSE; -+ gcsHAL_PRIVATE_DATA_PTR data = gcvNULL; -+ gctINT i; -+ -+ gcmkHEADER_ARG("inode=0x%08X filp=0x%08X", inode, filp); -+ -+ if (filp == gcvNULL) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_DRIVER, -+ "%s(%d): filp is NULL\n", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ } -+ -+ data = kmalloc(sizeof(gcsHAL_PRIVATE_DATA), GFP_KERNEL | __GFP_NOWARN); -+ -+ if (data == gcvNULL) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_DRIVER, -+ "%s(%d): private_data is NULL\n", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); -+ } -+ -+ data->device = galDevice; -+ data->mappedMemory = gcvNULL; -+ data->contiguousLogical = gcvNULL; -+ gcmkONERROR(gckOS_GetProcessID(&data->pidOpen)); -+ -+ /* Attached the process. */ -+ for (i = 0; i < gcdMAX_GPU_COUNT; i++) -+ { -+ if (galDevice->kernels[i] != gcvNULL) -+ { -+ gcmkONERROR(gckKERNEL_AttachProcess(galDevice->kernels[i], gcvTRUE)); -+ } -+ } -+ attached = gcvTRUE; -+ -+ if (!galDevice->contiguousMapped) -+ { -+ if (galDevice->contiguousPhysical != gcvNULL) -+ { -+ gcmkONERROR(gckOS_MapMemory( -+ galDevice->os, -+ galDevice->contiguousPhysical, -+ galDevice->contiguousSize, -+ &data->contiguousLogical -+ )); -+ } -+ } -+ -+ filp->private_data = data; -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return 0; -+ -+OnError: -+ if (data != gcvNULL) -+ { -+ if (data->contiguousLogical != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckOS_UnmapMemory( -+ galDevice->os, -+ galDevice->contiguousPhysical, -+ galDevice->contiguousSize, -+ data->contiguousLogical -+ )); -+ } -+ -+ kfree(data); -+ } -+ -+ if (attached) -+ { -+ for (i = 0; i < gcdMAX_GPU_COUNT; i++) -+ { -+ if (galDevice->kernels[i] != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckKERNEL_AttachProcess(galDevice->kernels[i], gcvFALSE)); -+ } -+ } -+ } -+ -+ gcmkFOOTER(); -+ return -ENOTTY; -+} -+ -+int drv_release( -+ struct inode* inode, -+ struct file* filp -+ ) -+{ -+ gceSTATUS status; -+ gcsHAL_PRIVATE_DATA_PTR data; -+ gckGALDEVICE device; -+ gctINT i; -+ -+ gcmkHEADER_ARG("inode=0x%08X filp=0x%08X", inode, filp); -+ -+ if (filp == gcvNULL) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_DRIVER, -+ "%s(%d): filp is NULL\n", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ } -+ -+ data = filp->private_data; -+ -+ if (data == gcvNULL) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_DRIVER, -+ "%s(%d): private_data is NULL\n", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ } -+ -+ device = data->device; -+ -+ if (device == gcvNULL) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_DRIVER, -+ "%s(%d): device is NULL\n", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ } -+ -+ if (!device->contiguousMapped) -+ { -+ if (data->contiguousLogical != gcvNULL) -+ { -+ gcmkONERROR(gckOS_UnmapMemoryEx( -+ galDevice->os, -+ galDevice->contiguousPhysical, -+ galDevice->contiguousSize, -+ data->contiguousLogical, -+ data->pidOpen -+ )); -+ -+ data->contiguousLogical = gcvNULL; -+ } -+ } -+ -+ /* A process gets detached. */ -+ for (i = 0; i < gcdMAX_GPU_COUNT; i++) -+ { -+ if (galDevice->kernels[i] != gcvNULL) -+ { -+ gcmkONERROR(gckKERNEL_AttachProcessEx(galDevice->kernels[i], gcvFALSE, data->pidOpen)); -+ } -+ } -+ -+ kfree(data); -+ filp->private_data = NULL; -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return 0; -+ -+OnError: -+ gcmkFOOTER(); -+ return -ENOTTY; -+} -+ -+long drv_ioctl( -+ struct file* filp, -+ unsigned int ioctlCode, -+ unsigned long arg -+ ) -+{ -+ gceSTATUS status; -+ gcsHAL_INTERFACE iface; -+ gctUINT32 copyLen; -+ DRIVER_ARGS drvArgs; -+ gckGALDEVICE device; -+ gcsHAL_PRIVATE_DATA_PTR data; -+ gctINT32 i, count; -+ gckVIDMEM_NODE nodeObject; -+ -+ gcmkHEADER_ARG( -+ "filp=0x%08X ioctlCode=0x%08X arg=0x%08X", -+ filp, ioctlCode, arg -+ ); -+ -+ if (filp == gcvNULL) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_DRIVER, -+ "%s(%d): filp is NULL\n", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ } -+ -+ data = filp->private_data; -+ -+ if (data == gcvNULL) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_DRIVER, -+ "%s(%d): private_data is NULL\n", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ } -+ -+ device = data->device; -+ -+ if (device == gcvNULL) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_DRIVER, -+ "%s(%d): device is NULL\n", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ } -+ -+ if ((ioctlCode != IOCTL_GCHAL_INTERFACE) -+ && (ioctlCode != IOCTL_GCHAL_KERNEL_INTERFACE) -+ ) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_DRIVER, -+ "%s(%d): unknown command %d\n", -+ __FUNCTION__, __LINE__, -+ ioctlCode -+ ); -+ -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ } -+ -+ /* Get the drvArgs. */ -+ copyLen = copy_from_user( -+ &drvArgs, (void *) arg, sizeof(DRIVER_ARGS) -+ ); -+ -+ if (copyLen != 0) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_DRIVER, -+ "%s(%d): error copying of the input arguments.\n", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ } -+ -+ /* Now bring in the gcsHAL_INTERFACE structure. */ -+ if ((drvArgs.InputBufferSize != sizeof(gcsHAL_INTERFACE)) -+ || (drvArgs.OutputBufferSize != sizeof(gcsHAL_INTERFACE)) -+ ) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_DRIVER, -+ "%s(%d): input or/and output structures are invalid.\n", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ } -+ -+ copyLen = copy_from_user( -+ &iface, gcmUINT64_TO_PTR(drvArgs.InputBuffer), sizeof(gcsHAL_INTERFACE) -+ ); -+ -+ if (copyLen != 0) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_DRIVER, -+ "%s(%d): error copying of input HAL interface.\n", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ } -+ -+ if (iface.command == gcvHAL_CHIP_INFO) -+ { -+ count = 0; -+ for (i = 0; i < gcdMAX_GPU_COUNT; i++) -+ { -+ if (device->kernels[i] != gcvNULL) -+ { -+#if gcdENABLE_VG -+ if (i == gcvCORE_VG) -+ { -+ iface.u.ChipInfo.types[count] = gcvHARDWARE_VG; -+ } -+ else -+#endif -+ { -+ gcmkVERIFY_OK(gckHARDWARE_GetType(device->kernels[i]->hardware, -+ &iface.u.ChipInfo.types[count])); -+ } -+ count++; -+ } -+ } -+ -+ iface.u.ChipInfo.count = count; -+ iface.status = status = gcvSTATUS_OK; -+ } -+ else -+ { -+ if (iface.hardwareType > 7) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_DRIVER, -+ "%s(%d): unknown hardwareType %d\n", -+ __FUNCTION__, __LINE__, -+ iface.hardwareType -+ ); -+ -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ } -+ -+#if gcdENABLE_VG -+ if (device->coreMapping[iface.hardwareType] == gcvCORE_VG) -+ { -+ status = gckVGKERNEL_Dispatch(device->kernels[gcvCORE_VG], -+ (ioctlCode == IOCTL_GCHAL_INTERFACE), -+ &iface); -+ } -+ else -+#endif -+ { -+ status = gckKERNEL_Dispatch(device->kernels[device->coreMapping[iface.hardwareType]], -+ (ioctlCode == IOCTL_GCHAL_INTERFACE), -+ &iface); -+ } -+ } -+ -+ /* Redo system call after pending signal is handled. */ -+ if (status == gcvSTATUS_INTERRUPTED) -+ { -+ gcmkFOOTER(); -+ return -ERESTARTSYS; -+ } -+ -+ if (gcmIS_SUCCESS(status) && (iface.command == gcvHAL_LOCK_VIDEO_MEMORY)) -+ { -+ gcuVIDMEM_NODE_PTR node; -+ gctUINT32 processID; -+ -+ gckOS_GetProcessID(&processID); -+ -+ gcmkONERROR(gckVIDMEM_HANDLE_Lookup(device->kernels[device->coreMapping[iface.hardwareType]], -+ processID, -+ (gctUINT32)iface.u.LockVideoMemory.node, -+ &nodeObject)); -+ node = nodeObject->node; -+ -+ /* Special case for mapped memory. */ -+ if ((data->mappedMemory != gcvNULL) -+ && (node->VidMem.memory->object.type == gcvOBJ_VIDMEM) -+ ) -+ { -+ /* Compute offset into mapped memory. */ -+ gctUINT32 offset -+ = (gctUINT8 *) gcmUINT64_TO_PTR(iface.u.LockVideoMemory.memory) -+ - (gctUINT8 *) device->contiguousBase; -+ -+ /* Compute offset into user-mapped region. */ -+ iface.u.LockVideoMemory.memory = -+ gcmPTR_TO_UINT64((gctUINT8 *) data->mappedMemory + offset); -+ } -+ } -+ -+ /* Copy data back to the user. */ -+ copyLen = copy_to_user( -+ gcmUINT64_TO_PTR(drvArgs.OutputBuffer), &iface, sizeof(gcsHAL_INTERFACE) -+ ); -+ -+ if (copyLen != 0) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_DRIVER, -+ "%s(%d): error copying of output HAL interface.\n", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ } -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return 0; -+ -+OnError: -+ gcmkFOOTER(); -+ return -ENOTTY; -+} -+ -+static int drv_mmap( -+ struct file* filp, -+ struct vm_area_struct* vma -+ ) -+{ -+ gceSTATUS status = gcvSTATUS_OK; -+ gcsHAL_PRIVATE_DATA_PTR data; -+ gckGALDEVICE device; -+ -+ gcmkHEADER_ARG("filp=0x%08X vma=0x%08X", filp, vma); -+ -+ if (filp == gcvNULL) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_DRIVER, -+ "%s(%d): filp is NULL\n", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ } -+ -+ data = filp->private_data; -+ -+ if (data == gcvNULL) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_DRIVER, -+ "%s(%d): private_data is NULL\n", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ } -+ -+ device = data->device; -+ -+ if (device == gcvNULL) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_DRIVER, -+ "%s(%d): device is NULL\n", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ } -+ -+#if !gcdPAGED_MEMORY_CACHEABLE -+ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); -+ vma->vm_flags |= gcdVM_FLAGS; -+#endif -+ vma->vm_pgoff = 0; -+ -+ if (device->contiguousMapped) -+ { -+ unsigned long size = vma->vm_end - vma->vm_start; -+ int ret = 0; -+ -+ if (size > device->contiguousSize) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_DRIVER, -+ "%s(%d): Invalid mapping size.\n", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ } -+ -+ ret = io_remap_pfn_range( -+ vma, -+ vma->vm_start, -+ device->requestedContiguousBase >> PAGE_SHIFT, -+ size, -+ vma->vm_page_prot -+ ); -+ -+ if (ret != 0) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_DRIVER, -+ "%s(%d): io_remap_pfn_range failed %d\n", -+ __FUNCTION__, __LINE__, -+ ret -+ ); -+ -+ data->mappedMemory = gcvNULL; -+ -+ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES); -+ } -+ -+ data->mappedMemory = (gctPOINTER) vma->vm_start; -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return 0; -+ } -+ -+OnError: -+ gcmkFOOTER(); -+ return -ENOTTY; -+} -+ -+ -+static int drv_init(void) -+{ -+ int ret; -+ int result = -EINVAL; -+ gceSTATUS status; -+ gckGALDEVICE device = gcvNULL; -+ struct class* device_class = gcvNULL; -+ -+ gcsDEVICE_CONSTRUCT_ARGS args = { -+ .recovery = recovery, -+ .stuckDump = stuckDump, -+ .gpu3DMinClock = gpu3DMinClock, -+ .contiguousRequested = contiguousRequested, -+ .platform = &platform, -+ .mmu = mmu, -+ }; -+ -+ gcmkHEADER(); -+ -+ printk(KERN_INFO "Galcore version %d.%d.%d.%d\n", -+ gcvVERSION_MAJOR, gcvVERSION_MINOR, gcvVERSION_PATCH, gcvVERSION_BUILD); -+ -+#if !VIVANTE_PROFILER_PM -+ /* when enable gpu profiler, we need to turn off gpu powerMangement */ -+ if (gpuProfiler) -+ { -+ powerManagement = 0; -+ } -+#endif -+ -+ if (showArgs) -+ { -+ gckOS_DumpParam(); -+ } -+ -+ if (logFileSize != 0) -+ { -+ gckDEBUGFS_Initialize(); -+ } -+ -+ /* Create the GAL device. */ -+ status = gckGALDEVICE_Construct( -+ irqLine, -+ registerMemBase, registerMemSize, -+ irqLine2D, -+ registerMemBase2D, registerMemSize2D, -+ irqLineVG, -+ registerMemBaseVG, registerMemSizeVG, -+ contiguousBase, contiguousSize, -+ bankSize, fastClear, compression, baseAddress, physSize, signal, -+ logFileSize, -+ powerManagement, -+ gpuProfiler, -+ &args, -+ &device -+ ); -+ -+ if (gcmIS_ERROR(status)) -+ { -+ gcmkTRACE_ZONE(gcvLEVEL_ERROR, gcvZONE_DRIVER, -+ "%s(%d): Failed to create the GAL device: status=%d\n", -+ __FUNCTION__, __LINE__, status); -+ -+ goto OnError; -+ } -+ -+ /* Start the GAL device. */ -+ gcmkONERROR(gckGALDEVICE_Start(device)); -+ -+ if ((physSize != 0) -+ && (device->kernels[gcvCORE_MAJOR] != gcvNULL) -+ && (device->kernels[gcvCORE_MAJOR]->hardware->mmuVersion != 0)) -+ { -+ /* Reset the base address */ -+ device->baseAddress = 0; -+ } -+ -+ /* Register the character device. */ -+ ret = register_chrdev(major, DEVICE_NAME, &driver_fops); -+ -+ if (ret < 0) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_DRIVER, -+ "%s(%d): Could not allocate major number for mmap.\n", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); -+ } -+ -+ if (major == 0) -+ { -+ major = ret; -+ } -+ -+ /* Create the device class. */ -+ device_class = class_create(THIS_MODULE, "graphics_class"); -+ -+ if (IS_ERR(device_class)) -+ { -+ gcmkTRACE_ZONE( -+ gcvLEVEL_ERROR, gcvZONE_DRIVER, -+ "%s(%d): Failed to create the class.\n", -+ __FUNCTION__, __LINE__ -+ ); -+ -+ gcmkONERROR(gcvSTATUS_OUT_OF_RESOURCES); -+ } -+ -+ device_create(device_class, NULL, MKDEV(major, 0), NULL, DEVICE_NAME); -+ -+ galDevice = device; -+ gpuClass = device_class; -+ -+ gcmkTRACE_ZONE( -+ gcvLEVEL_INFO, gcvZONE_DRIVER, -+ "%s(%d): irqLine=%d, contiguousSize=%lu, memBase=0x%lX\n", -+ __FUNCTION__, __LINE__, -+ irqLine, contiguousSize, registerMemBase -+ ); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return 0; -+ -+OnError: -+ /* Roll back. */ -+ if (device_class != gcvNULL) -+ { -+ device_destroy(device_class, MKDEV(major, 0)); -+ class_destroy(device_class); -+ } -+ -+ if (device != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckGALDEVICE_Stop(device)); -+ gcmkVERIFY_OK(gckGALDEVICE_Destroy(device)); -+ } -+ -+ gcmkFOOTER(); -+ return result; -+} -+ -+static void drv_exit(void) -+{ -+ gcmkHEADER(); -+ -+ gcmkASSERT(gpuClass != gcvNULL); -+ device_destroy(gpuClass, MKDEV(major, 0)); -+ class_destroy(gpuClass); -+ -+ unregister_chrdev(major, DEVICE_NAME); -+ -+ gcmkVERIFY_OK(gckGALDEVICE_Stop(galDevice)); -+ gcmkVERIFY_OK(gckGALDEVICE_Destroy(galDevice)); -+ -+ if(gckDEBUGFS_IsEnabled()) -+ { -+ gckDEBUGFS_Terminate(); -+ } -+ -+ gcmkFOOTER_NO(); -+} -+ -+static int gpu_probe(struct platform_device *pdev) -+{ -+ int ret = -ENODEV; -+ gcsMODULE_PARAMETERS moduleParam = { -+ .irqLine = irqLine, -+ .registerMemBase = registerMemBase, -+ .registerMemSize = registerMemSize, -+ .irqLine2D = irqLine2D, -+ .registerMemBase2D = registerMemBase2D, -+ .registerMemSize2D = registerMemSize2D, -+ .irqLineVG = irqLineVG, -+ .registerMemBaseVG = registerMemBaseVG, -+ .registerMemSizeVG = registerMemSizeVG, -+ .contiguousSize = contiguousSize, -+ .contiguousBase = contiguousBase, -+ .bankSize = bankSize, -+ .fastClear = fastClear, -+ .compression = compression, -+ .powerManagement = powerManagement, -+ .gpuProfiler = gpuProfiler, -+ .signal = signal, -+ .baseAddress = baseAddress, -+ .physSize = physSize, -+ .logFileSize = logFileSize, -+ .recovery = recovery, -+ .stuckDump = stuckDump, -+ .showArgs = showArgs, -+ .gpu3DMinClock = gpu3DMinClock, -+ }; -+ -+ gcmkHEADER(); -+ -+ platform.device = pdev; -+ -+ if (platform.ops->getPower) -+ { -+ if (gcmIS_ERROR(platform.ops->getPower(&platform))) -+ { -+ gcmkFOOTER_NO(); -+ return ret; -+ } -+ } -+ -+ if (platform.ops->adjustParam) -+ { -+ /* Override default module param. */ -+ platform.ops->adjustParam(&platform, &moduleParam); -+ -+ /* Update module param because drv_init() uses them directly. */ -+ _UpdateModuleParam(&moduleParam); -+ } -+ -+ ret = drv_init(); -+ -+ if (!ret) -+ { -+ platform_set_drvdata(pdev, galDevice); -+ -+ gcmkFOOTER_NO(); -+ return ret; -+ } -+ -+ gcmkFOOTER_ARG(KERN_INFO "Failed to register gpu driver: %d\n", ret); -+ return ret; -+} -+ -+static int gpu_remove(struct platform_device *pdev) -+{ -+ gcmkHEADER(); -+ -+ drv_exit(); -+ -+ if (platform.ops->putPower) -+ { -+ platform.ops->putPower(&platform); -+ } -+ -+ gcmkFOOTER_NO(); -+ return 0; -+} -+ -+static int gpu_suspend(struct platform_device *dev, pm_message_t state) -+{ -+ gceSTATUS status; -+ gckGALDEVICE device; -+ gctINT i; -+ -+ device = platform_get_drvdata(dev); -+ -+ if (!device) -+ { -+ return -1; -+ } -+ -+ for (i = 0; i < gcdMAX_GPU_COUNT; i++) -+ { -+ if (device->kernels[i] != gcvNULL) -+ { -+ /* Store states. */ -+#if gcdENABLE_VG -+ if (i == gcvCORE_VG) -+ { -+ status = gckVGHARDWARE_QueryPowerManagementState(device->kernels[i]->vg->hardware, &device->statesStored[i]); -+ } -+ else -+#endif -+ { -+ status = gckHARDWARE_QueryPowerManagementState(device->kernels[i]->hardware, &device->statesStored[i]); -+ } -+ -+ if (gcmIS_ERROR(status)) -+ { -+ return -1; -+ } -+ -+#if gcdENABLE_VG -+ if (i == gcvCORE_VG) -+ { -+ status = gckVGHARDWARE_SetPowerManagementState(device->kernels[i]->vg->hardware, gcvPOWER_OFF); -+ } -+ else -+#endif -+ { -+ status = gckHARDWARE_SetPowerManagementState(device->kernels[i]->hardware, gcvPOWER_OFF); -+ } -+ -+ if (gcmIS_ERROR(status)) -+ { -+ return -1; -+ } -+ -+ } -+ } -+ -+ return 0; -+} -+ -+static int gpu_resume(struct platform_device *dev) -+{ -+ gceSTATUS status; -+ gckGALDEVICE device; -+ gctINT i; -+ gceCHIPPOWERSTATE statesStored; -+ -+ device = platform_get_drvdata(dev); -+ -+ if (!device) -+ { -+ return -1; -+ } -+ -+ for (i = 0; i < gcdMAX_GPU_COUNT; i++) -+ { -+ if (device->kernels[i] != gcvNULL) -+ { -+#if gcdENABLE_VG -+ if (i == gcvCORE_VG) -+ { -+ status = gckVGHARDWARE_SetPowerManagementState(device->kernels[i]->vg->hardware, gcvPOWER_ON); -+ } -+ else -+#endif -+ { -+ status = gckHARDWARE_SetPowerManagementState(device->kernels[i]->hardware, gcvPOWER_ON); -+ } -+ -+ if (gcmIS_ERROR(status)) -+ { -+ return -1; -+ } -+ -+ /* Convert global state to crossponding internal state. */ -+ switch(device->statesStored[i]) -+ { -+ case gcvPOWER_OFF: -+ statesStored = gcvPOWER_OFF_BROADCAST; -+ break; -+ case gcvPOWER_IDLE: -+ statesStored = gcvPOWER_IDLE_BROADCAST; -+ break; -+ case gcvPOWER_SUSPEND: -+ statesStored = gcvPOWER_SUSPEND_BROADCAST; -+ break; -+ case gcvPOWER_ON: -+ statesStored = gcvPOWER_ON_AUTO; -+ break; -+ default: -+ statesStored = device->statesStored[i]; -+ break; -+ } -+ -+ /* Restore states. */ -+#if gcdENABLE_VG -+ if (i == gcvCORE_VG) -+ { -+ status = gckVGHARDWARE_SetPowerManagementState(device->kernels[i]->vg->hardware, statesStored); -+ } -+ else -+#endif -+ { -+ status = gckHARDWARE_SetPowerManagementState(device->kernels[i]->hardware, statesStored); -+ } -+ -+ if (gcmIS_ERROR(status)) -+ { -+ return -1; -+ } -+ } -+ } -+ -+ return 0; -+} -+ -+#if defined(CONFIG_PM) -+static int gpu_runtime_suspend(struct device *dev) -+{ -+ pm_message_t state={0}; -+ return gpu_suspend(to_platform_device(dev), state); -+} -+ -+static int gpu_runtime_resume(struct device *dev) -+{ -+ return gpu_resume(to_platform_device(dev)); -+} -+ -+static const struct dev_pm_ops gpu_pm_ops = { -+ SET_RUNTIME_PM_OPS(gpu_runtime_suspend, gpu_runtime_resume, NULL) -+}; -+#endif -+ -+static struct platform_driver gpu_driver = { -+ .probe = gpu_probe, -+ .remove = gpu_remove, -+ -+ .driver = { -+ .name = DEVICE_NAME, -+ .pm = &gpu_pm_ops, -+ } -+}; -+ -+static int __init gpu_init(void) -+{ -+ int ret = 0; -+ -+ memset(&platform, 0, sizeof(gcsPLATFORM)); -+ -+ gckPLATFORM_QueryOperations(&platform.ops); -+ -+ if (platform.ops == gcvNULL) -+ { -+ printk(KERN_ERR "galcore: No platform specific operations.\n"); -+ ret = -ENODEV; -+ goto out; -+ } -+ -+ if (platform.ops->allocPriv) -+ { -+ /* Allocate platform private data. */ -+ if (gcmIS_ERROR(platform.ops->allocPriv(&platform))) -+ { -+ ret = -ENOMEM; -+ goto out; -+ } -+ } -+ -+ if (platform.ops->needAddDevice -+ && platform.ops->needAddDevice(&platform)) -+ { -+ /* Allocate device */ -+ platform.device = platform_device_alloc(DEVICE_NAME, -1); -+ if (!platform.device) -+ { -+ printk(KERN_ERR "galcore: platform_device_alloc failed.\n"); -+ ret = -ENOMEM; -+ goto out; -+ } -+ -+ /* Add device */ -+ ret = platform_device_add(platform.device); -+ if (ret) -+ { -+ printk(KERN_ERR "galcore: platform_device_add failed.\n"); -+ goto put_dev; -+ } -+ } -+ -+ platform.driver = &gpu_driver; -+ -+ if (platform.ops->adjustDriver) -+ { -+ /* Override default platform_driver struct. */ -+ platform.ops->adjustDriver(&platform); -+ } -+ -+ ret = platform_driver_register(&gpu_driver); -+ if (!ret) -+ { -+ goto out; -+ } -+ -+ platform_device_del(platform.device); -+put_dev: -+ platform_device_put(platform.device); -+ -+out: -+ return ret; -+} -+ -+static void __exit gpu_exit(void) -+{ -+ platform_driver_unregister(&gpu_driver); -+ -+ if (platform.ops->needAddDevice -+ && platform.ops->needAddDevice(&platform)) -+ { -+ platform_device_unregister(platform.device); -+ } -+ -+ if (platform.priv) -+ { -+ /* Free platform private data. */ -+ platform.ops->freePriv(&platform); -+ } -+} -+ -+module_init(gpu_init); -+module_exit(gpu_exit); -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_sync.c linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_sync.c ---- linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_sync.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_sync.c 2015-11-30 17:56:13.584137459 +0100 -@@ -0,0 +1,177 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#include -+#include -+ -+#if gcdANDROID_NATIVE_FENCE_SYNC -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "gc_hal_kernel_sync.h" -+ -+static struct sync_pt * -+viv_sync_pt_dup( -+ struct sync_pt * sync_pt -+ ) -+{ -+ gceSTATUS status; -+ struct viv_sync_pt *pt; -+ struct viv_sync_pt *src; -+ struct viv_sync_timeline *obj; -+ -+ src = (struct viv_sync_pt *) sync_pt; -+ obj = (struct viv_sync_timeline *) sync_pt->parent; -+ -+ /* Create the new sync_pt. */ -+ pt = (struct viv_sync_pt *) -+ sync_pt_create(&obj->obj, sizeof(struct viv_sync_pt)); -+ -+ pt->stamp = src->stamp; -+ pt->sync = src->sync; -+ -+ /* Reference sync point. */ -+ status = gckOS_ReferenceSyncPoint(obj->os, pt->sync); -+ -+ if (gcmIS_ERROR(status)) -+ { -+ sync_pt_free((struct sync_pt *)pt); -+ return NULL; -+ } -+ -+ return (struct sync_pt *)pt; -+} -+ -+static int -+viv_sync_pt_has_signaled( -+ struct sync_pt * sync_pt -+ ) -+{ -+ gceSTATUS status; -+ gctBOOL state; -+ struct viv_sync_pt * pt; -+ struct viv_sync_timeline * obj; -+ -+ pt = (struct viv_sync_pt *)sync_pt; -+ obj = (struct viv_sync_timeline *)sync_pt->parent; -+ -+ status = gckOS_QuerySyncPoint(obj->os, pt->sync, &state); -+ -+ if (gcmIS_ERROR(status)) -+ { -+ /* Error. */ -+ return -1; -+ } -+ -+ return state; -+} -+ -+static int -+viv_sync_pt_compare( -+ struct sync_pt * a, -+ struct sync_pt * b -+ ) -+{ -+ int ret; -+ struct viv_sync_pt * pt1 = (struct viv_sync_pt *) a; -+ struct viv_sync_pt * pt2 = (struct viv_sync_pt *) b; -+ -+ ret = (pt1->stamp < pt2->stamp) ? -1 -+ : (pt1->stamp == pt2->stamp) ? 0 -+ : 1; -+ -+ return ret; -+} -+ -+static void -+viv_sync_pt_free( -+ struct sync_pt * sync_pt -+ ) -+{ -+ struct viv_sync_pt * pt; -+ struct viv_sync_timeline * obj; -+ -+ pt = (struct viv_sync_pt *) sync_pt; -+ obj = (struct viv_sync_timeline *) sync_pt->parent; -+ -+ gckOS_DestroySyncPoint(obj->os, pt->sync); -+} -+ -+static struct sync_timeline_ops viv_timeline_ops = -+{ -+ .driver_name = "viv_sync", -+ .dup = viv_sync_pt_dup, -+ .has_signaled = viv_sync_pt_has_signaled, -+ .compare = viv_sync_pt_compare, -+ .free_pt = viv_sync_pt_free, -+}; -+ -+struct viv_sync_timeline * -+viv_sync_timeline_create( -+ const char * name, -+ gckOS os -+ ) -+{ -+ struct viv_sync_timeline * obj; -+ -+ obj = (struct viv_sync_timeline *) -+ sync_timeline_create(&viv_timeline_ops, sizeof(struct viv_sync_timeline), name); -+ -+ obj->os = os; -+ obj->stamp = 0; -+ -+ return obj; -+} -+ -+struct sync_pt * -+viv_sync_pt_create( -+ struct viv_sync_timeline * obj, -+ gctSYNC_POINT SyncPoint -+ ) -+{ -+ gceSTATUS status; -+ struct viv_sync_pt * pt; -+ -+ pt = (struct viv_sync_pt *) -+ sync_pt_create(&obj->obj, sizeof(struct viv_sync_pt)); -+ -+ pt->stamp = obj->stamp++; -+ pt->sync = SyncPoint; -+ -+ /* Dup signal. */ -+ status = gckOS_ReferenceSyncPoint(obj->os, SyncPoint); -+ -+ if (gcmIS_ERROR(status)) -+ { -+ sync_pt_free((struct sync_pt *)pt); -+ return NULL; -+ } -+ -+ return (struct sync_pt *) pt; -+} -+ -+#endif -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_sync.h linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_sync.h ---- linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_sync.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_sync.h 2015-11-30 17:56:13.584137459 +0100 -@@ -0,0 +1,72 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#ifndef __gc_hal_kernel_sync_h_ -+#define __gc_hal_kernel_sync_h_ -+ -+#include -+ -+/* sync.h is in drivers/staging/android/ for now. */ -+#include -+ -+#include -+#include -+ -+struct viv_sync_timeline -+{ -+ /* Parent object. */ -+ struct sync_timeline obj; -+ -+ /* Timestamp when sync_pt is created. */ -+ gctUINT stamp; -+ -+ /* Pointer to os struct. */ -+ gckOS os; -+}; -+ -+ -+struct viv_sync_pt -+{ -+ /* Parent object. */ -+ struct sync_pt pt; -+ -+ /* Reference sync point*/ -+ gctSYNC_POINT sync; -+ -+ /* Timestamp when sync_pt is created. */ -+ gctUINT stamp; -+}; -+ -+/* Create viv_sync_timeline object. */ -+struct viv_sync_timeline * -+viv_sync_timeline_create( -+ const char * Name, -+ gckOS Os -+ ); -+ -+/* Create viv_sync_pt object. */ -+struct sync_pt * -+viv_sync_pt_create( -+ struct viv_sync_timeline * Obj, -+ gctSYNC_POINT SyncPoint -+ ); -+ -+#endif /* __gc_hal_kernel_sync_h_ */ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_vg.c linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_vg.c ---- linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_vg.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_vg.c 2015-11-30 17:56:13.584137459 +0100 -@@ -0,0 +1,831 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#include "gc_hal_kernel_precomp.h" -+ -+#if gcdENABLE_VG -+ -+#define _GC_OBJ_ZONE gcvZONE_VG -+ -+/******************************************************************************\ -+******************************* gckKERNEL API Code ****************************** -+\******************************************************************************/ -+ -+/******************************************************************************* -+** -+** gckKERNEL_Construct -+** -+** Construct a new gckKERNEL object. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** IN gctPOINTER Context -+** Pointer to a driver defined context. -+** -+** OUTPUT: -+** -+** gckKERNEL * Kernel -+** Pointer to a variable that will hold the pointer to the gckKERNEL -+** object. -+*/ -+gceSTATUS gckVGKERNEL_Construct( -+ IN gckOS Os, -+ IN gctPOINTER Context, -+ IN gckKERNEL inKernel, -+ OUT gckVGKERNEL * Kernel -+ ) -+{ -+ gceSTATUS status; -+ gckVGKERNEL kernel = gcvNULL; -+ -+ gcmkHEADER_ARG("Os=0x%x Context=0x%x", Os, Context); -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Kernel != gcvNULL); -+ -+ do -+ { -+ /* Allocate the gckKERNEL object. */ -+ gcmkERR_BREAK(gckOS_Allocate( -+ Os, -+ sizeof(struct _gckVGKERNEL), -+ (gctPOINTER *) &kernel -+ )); -+ -+ /* Initialize the gckKERNEL object. */ -+ kernel->object.type = gcvOBJ_KERNEL; -+ kernel->os = Os; -+ kernel->context = Context; -+ kernel->hardware = gcvNULL; -+ kernel->interrupt = gcvNULL; -+ kernel->command = gcvNULL; -+ kernel->mmu = gcvNULL; -+ kernel->kernel = inKernel; -+ -+ /* Construct the gckVGHARDWARE object. */ -+ gcmkERR_BREAK(gckVGHARDWARE_Construct( -+ Os, &kernel->hardware -+ )); -+ -+ /* Set pointer to gckKERNEL object in gckVGHARDWARE object. */ -+ kernel->hardware->kernel = kernel; -+ -+ /* Construct the gckVGINTERRUPT object. */ -+ gcmkERR_BREAK(gckVGINTERRUPT_Construct( -+ kernel, &kernel->interrupt -+ )); -+ -+ /* Construct the gckVGCOMMAND object. */ -+ gcmkERR_BREAK(gckVGCOMMAND_Construct( -+ kernel, gcmKB2BYTES(8), gcmKB2BYTES(2), &kernel->command -+ )); -+ -+ /* Construct the gckVGMMU object. */ -+ gcmkERR_BREAK(gckVGMMU_Construct( -+ kernel, gcmKB2BYTES(32), &kernel->mmu -+ )); -+ -+ /* Return pointer to the gckKERNEL object. */ -+ *Kernel = kernel; -+ -+ gcmkFOOTER_ARG("*Kernel=0x%x", *Kernel); -+ /* Success. */ -+ return gcvSTATUS_OK; -+ } -+ while (gcvFALSE); -+ -+ /* Roll back. */ -+ if (kernel != gcvNULL) -+ { -+ if (kernel->mmu != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckVGMMU_Destroy(kernel->mmu)); -+ } -+ -+ if (kernel->command != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckVGCOMMAND_Destroy(kernel->command)); -+ } -+ -+ if (kernel->interrupt != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckVGINTERRUPT_Destroy(kernel->interrupt)); -+ } -+ -+ if (kernel->hardware != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckVGHARDWARE_Destroy(kernel->hardware)); -+ } -+ -+ gcmkVERIFY_OK(gckOS_Free(Os, kernel)); -+ } -+ -+ gcmkFOOTER(); -+ /* Return status. */ -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckKERNEL_Destroy -+** -+** Destroy an gckKERNEL object. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object to destroy. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS gckVGKERNEL_Destroy( -+ IN gckVGKERNEL Kernel -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Kernel=0x%x", Kernel); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ -+ do -+ { -+ /* Destroy the gckVGMMU object. */ -+ if (Kernel->mmu != gcvNULL) -+ { -+ gcmkERR_BREAK(gckVGMMU_Destroy(Kernel->mmu)); -+ Kernel->mmu = gcvNULL; -+ } -+ -+ /* Destroy the gckVGCOMMAND object. */ -+ if (Kernel->command != gcvNULL) -+ { -+ gcmkERR_BREAK(gckVGCOMMAND_Destroy(Kernel->command)); -+ Kernel->command = gcvNULL; -+ } -+ -+ /* Destroy the gckVGINTERRUPT object. */ -+ if (Kernel->interrupt != gcvNULL) -+ { -+ gcmkERR_BREAK(gckVGINTERRUPT_Destroy(Kernel->interrupt)); -+ Kernel->interrupt = gcvNULL; -+ } -+ -+ /* Destroy the gckVGHARDWARE object. */ -+ if (Kernel->hardware != gcvNULL) -+ { -+ gcmkERR_BREAK(gckVGHARDWARE_Destroy(Kernel->hardware)); -+ Kernel->hardware = gcvNULL; -+ } -+ -+ /* Mark the gckKERNEL object as unknown. */ -+ Kernel->object.type = gcvOBJ_UNKNOWN; -+ -+ /* Free the gckKERNEL object. */ -+ gcmkERR_BREAK(gckOS_Free(Kernel->os, Kernel)); -+ } -+ while (gcvFALSE); -+ -+ gcmkFOOTER(); -+ -+ /* Return status. */ -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckKERNEL_AllocateLinearMemory -+** -+** Function walks all required memory pools and allocates the requested -+** amount of video memory. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** gcePOOL * Pool -+** Pointer the desired memory pool. -+** -+** gctSIZE_T Bytes -+** Number of bytes to allocate. -+** -+** gctSIZE_T Alignment -+** Required buffer alignment. -+** -+** gceSURF_TYPE Type -+** Surface type. -+** -+** OUTPUT: -+** -+** gcePOOL * Pool -+** Pointer to the actual pool where the memory was allocated. -+** -+** gcuVIDMEM_NODE_PTR * Node -+** Allocated node. -+*/ -+gceSTATUS -+gckVGKERNEL_AllocateLinearMemory( -+ IN gckKERNEL Kernel, -+ IN OUT gcePOOL * Pool, -+ IN gctSIZE_T Bytes, -+ IN gctUINT32 Alignment, -+ IN gceSURF_TYPE Type, -+ OUT gcuVIDMEM_NODE_PTR * Node -+ ) -+{ -+ gcePOOL pool; -+ gceSTATUS status; -+ gckVIDMEM videoMemory; -+ -+ /* Get initial pool. */ -+ switch (pool = *Pool) -+ { -+ case gcvPOOL_DEFAULT: -+ case gcvPOOL_LOCAL: -+ pool = gcvPOOL_LOCAL_INTERNAL; -+ break; -+ -+ case gcvPOOL_UNIFIED: -+ pool = gcvPOOL_SYSTEM; -+ break; -+ -+ default: -+ break; -+ } -+ -+ do -+ { -+ /* Verify the number of bytes to allocate. */ -+ if (Bytes == 0) -+ { -+ status = gcvSTATUS_INVALID_ARGUMENT; -+ break; -+ } -+ -+ if (pool == gcvPOOL_VIRTUAL) -+ { -+ /* Create a gcuVIDMEM_NODE for virtual memory. */ -+ gcmkERR_BREAK(gckVIDMEM_ConstructVirtual(Kernel, gcvFALSE, Bytes, Node)); -+ -+ /* Success. */ -+ break; -+ } -+ -+ else -+ { -+ /* Get pointer to gckVIDMEM object for pool. */ -+ status = gckKERNEL_GetVideoMemoryPool(Kernel, pool, &videoMemory); -+ -+ if (status == gcvSTATUS_OK) -+ { -+ /* Allocate memory. */ -+ status = gckVIDMEM_AllocateLinear(Kernel, -+ videoMemory, -+ Bytes, -+ Alignment, -+ Type, -+ (*Pool == gcvPOOL_SYSTEM), -+ Node); -+ -+ if (status == gcvSTATUS_OK) -+ { -+ /* Memory allocated. */ -+ break; -+ } -+ } -+ } -+ -+ if (pool == gcvPOOL_LOCAL_INTERNAL) -+ { -+ /* Advance to external memory. */ -+ pool = gcvPOOL_LOCAL_EXTERNAL; -+ } -+ else if (pool == gcvPOOL_LOCAL_EXTERNAL) -+ { -+ /* Advance to contiguous system memory. */ -+ pool = gcvPOOL_SYSTEM; -+ } -+ else if (pool == gcvPOOL_SYSTEM) -+ { -+ /* Advance to virtual memory. */ -+ pool = gcvPOOL_VIRTUAL; -+ } -+ else -+ { -+ /* Out of pools. */ -+ break; -+ } -+ } -+ /* Loop only for multiple selection pools. */ -+ while ((*Pool == gcvPOOL_DEFAULT) -+ || (*Pool == gcvPOOL_LOCAL) -+ || (*Pool == gcvPOOL_UNIFIED) -+ ); -+ -+ if (gcmIS_SUCCESS(status)) -+ { -+ /* Return pool used for allocation. */ -+ *Pool = pool; -+ } -+ -+ /* Return status. */ -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckKERNEL_Dispatch -+** -+** Dispatch a command received from the user HAL layer. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** gcsHAL_INTERFACE * Interface -+** Pointer to a gcsHAL_INTERFACE structure that defines the command to -+** be dispatched. -+** -+** OUTPUT: -+** -+** gcsHAL_INTERFACE * Interface -+** Pointer to a gcsHAL_INTERFACE structure that receives any data to be -+** returned. -+*/ -+gceSTATUS gckVGKERNEL_Dispatch( -+ IN gckKERNEL Kernel, -+ IN gctBOOL FromUser, -+ IN OUT gcsHAL_INTERFACE * Interface -+ ) -+{ -+ gceSTATUS status; -+ gcsHAL_INTERFACE * kernelInterface = Interface; -+ gctUINT32 processID; -+ gckKERNEL kernel = Kernel; -+ gctPOINTER info = gcvNULL; -+ gctPHYS_ADDR physical = gcvNULL; -+ gctPOINTER logical = gcvNULL; -+ gctSIZE_T bytes = 0; -+ -+ gcmkHEADER_ARG("Kernel=0x%x Interface=0x%x ", Kernel, Interface); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ gcmkVERIFY_ARGUMENT(Interface != gcvNULL); -+ -+ gcmkONERROR(gckOS_GetProcessID(&processID)); -+ -+ /* Dispatch on command. */ -+ switch (Interface->command) -+ { -+ case gcvHAL_QUERY_VIDEO_MEMORY: -+ /* Query video memory size. */ -+ gcmkERR_BREAK(gckKERNEL_QueryVideoMemory( -+ Kernel, kernelInterface -+ )); -+ break; -+ -+ case gcvHAL_QUERY_CHIP_IDENTITY: -+ /* Query chip identity. */ -+ gcmkERR_BREAK(gckVGHARDWARE_QueryChipIdentity( -+ Kernel->vg->hardware, -+ &kernelInterface->u.QueryChipIdentity.chipModel, -+ &kernelInterface->u.QueryChipIdentity.chipRevision, -+ &kernelInterface->u.QueryChipIdentity.chipFeatures, -+ &kernelInterface->u.QueryChipIdentity.chipMinorFeatures, -+ &kernelInterface->u.QueryChipIdentity.chipMinorFeatures2 -+ )); -+ break; -+ -+ case gcvHAL_QUERY_COMMAND_BUFFER: -+ /* Query command buffer information. */ -+ gcmkERR_BREAK(gckKERNEL_QueryCommandBuffer( -+ Kernel, -+ &kernelInterface->u.QueryCommandBuffer.information -+ )); -+ break; -+ case gcvHAL_ALLOCATE_NON_PAGED_MEMORY: -+ bytes = (gctSIZE_T) kernelInterface->u.AllocateNonPagedMemory.bytes; -+ /* Allocate non-paged memory. */ -+ gcmkERR_BREAK(gckOS_AllocateNonPagedMemory( -+ Kernel->os, -+ gcvTRUE, -+ &bytes, -+ &physical, -+ &logical -+ )); -+ -+ kernelInterface->u.AllocateNonPagedMemory.bytes = bytes; -+ kernelInterface->u.AllocateNonPagedMemory.logical = gcmPTR_TO_UINT64(logical); -+ kernelInterface->u.AllocateNonPagedMemory.physical = gcmPTR_TO_NAME(physical); -+ break; -+ -+ case gcvHAL_FREE_NON_PAGED_MEMORY: -+ physical = gcmNAME_TO_PTR(kernelInterface->u.AllocateNonPagedMemory.physical); -+ -+ /* Unmap user logical out of physical memory first. */ -+ gcmkERR_BREAK(gckOS_UnmapUserLogical( -+ Kernel->os, -+ physical, -+ (gctSIZE_T) kernelInterface->u.AllocateNonPagedMemory.bytes, -+ gcmUINT64_TO_PTR(kernelInterface->u.AllocateNonPagedMemory.logical) -+ )); -+ -+ /* Free non-paged memory. */ -+ gcmkERR_BREAK(gckOS_FreeNonPagedMemory( -+ Kernel->os, -+ (gctSIZE_T) kernelInterface->u.AllocateNonPagedMemory.bytes, -+ physical, -+ gcmUINT64_TO_PTR(kernelInterface->u.AllocateNonPagedMemory.logical) -+ )); -+ -+ gcmRELEASE_NAME(kernelInterface->u.AllocateNonPagedMemory.physical); -+ break; -+ -+ case gcvHAL_ALLOCATE_CONTIGUOUS_MEMORY: -+ bytes = (gctSIZE_T) kernelInterface->u.AllocateNonPagedMemory.bytes; -+ /* Allocate contiguous memory. */ -+ gcmkERR_BREAK(gckOS_AllocateContiguous( -+ Kernel->os, -+ gcvTRUE, -+ &bytes, -+ &physical, -+ &logical -+ )); -+ -+ kernelInterface->u.AllocateNonPagedMemory.bytes = bytes; -+ kernelInterface->u.AllocateNonPagedMemory.logical = gcmPTR_TO_UINT64(logical); -+ kernelInterface->u.AllocateNonPagedMemory.physical = gcmPTR_TO_NAME(physical); -+ break; -+ -+ case gcvHAL_FREE_CONTIGUOUS_MEMORY: -+ physical = gcmNAME_TO_PTR(kernelInterface->u.AllocateNonPagedMemory.physical); -+ /* Unmap user logical out of physical memory first. */ -+ gcmkERR_BREAK(gckOS_UnmapUserLogical( -+ Kernel->os, -+ physical, -+ (gctSIZE_T) kernelInterface->u.AllocateNonPagedMemory.bytes, -+ gcmUINT64_TO_PTR(kernelInterface->u.AllocateNonPagedMemory.logical) -+ )); -+ -+ /* Free contiguous memory. */ -+ gcmkERR_BREAK(gckOS_FreeContiguous( -+ Kernel->os, -+ physical, -+ gcmUINT64_TO_PTR(kernelInterface->u.AllocateNonPagedMemory.logical), -+ (gctSIZE_T) kernelInterface->u.AllocateNonPagedMemory.bytes -+ )); -+ -+ gcmRELEASE_NAME(kernelInterface->u.AllocateNonPagedMemory.physical); -+ break; -+ -+ case gcvHAL_ALLOCATE_VIDEO_MEMORY: -+ gcmkERR_BREAK(gcvSTATUS_NOT_SUPPORTED); -+ break; -+ -+ case gcvHAL_ALLOCATE_LINEAR_VIDEO_MEMORY: -+ /* Allocate memory. */ -+ gcmkERR_BREAK(gckKERNEL_AllocateLinearMemory( -+ Kernel, processID, -+ &kernelInterface->u.AllocateLinearVideoMemory.pool, -+ kernelInterface->u.AllocateLinearVideoMemory.bytes, -+ kernelInterface->u.AllocateLinearVideoMemory.alignment, -+ kernelInterface->u.AllocateLinearVideoMemory.type, -+ kernelInterface->u.AllocateLinearVideoMemory.flag, -+ &kernelInterface->u.AllocateLinearVideoMemory.node -+ )); -+ -+ break; -+ -+ case gcvHAL_RELEASE_VIDEO_MEMORY: -+ /* Free video memory. */ -+ gcmkERR_BREAK(gckKERNEL_ReleaseVideoMemory( -+ Kernel, processID, -+ (gctUINT32)kernelInterface->u.ReleaseVideoMemory.node -+ )); -+ -+ break; -+ -+ case gcvHAL_MAP_MEMORY: -+ /* Map memory. */ -+ gcmkERR_BREAK(gckKERNEL_MapMemory( -+ Kernel, -+ gcmINT2PTR(kernelInterface->u.MapMemory.physical), -+ (gctSIZE_T) kernelInterface->u.MapMemory.bytes, -+ &logical -+ )); -+ kernelInterface->u.MapMemory.logical = gcmPTR_TO_UINT64(logical); -+ break; -+ -+ case gcvHAL_UNMAP_MEMORY: -+ /* Unmap memory. */ -+ gcmkERR_BREAK(gckKERNEL_UnmapMemory( -+ Kernel, -+ gcmINT2PTR(kernelInterface->u.MapMemory.physical), -+ (gctSIZE_T) kernelInterface->u.MapMemory.bytes, -+ gcmUINT64_TO_PTR(kernelInterface->u.MapMemory.logical) -+ )); -+ break; -+ -+ case gcvHAL_MAP_USER_MEMORY: -+ /* Map user memory to DMA. */ -+ gcmkERR_BREAK(gckOS_MapUserMemory( -+ Kernel->os, -+ gcvCORE_VG, -+ gcmUINT64_TO_PTR(kernelInterface->u.MapUserMemory.memory), -+ kernelInterface->u.MapUserMemory.physical, -+ (gctSIZE_T) kernelInterface->u.MapUserMemory.size, -+ &info, -+ &kernelInterface->u.MapUserMemory.address -+ )); -+ -+ kernelInterface->u.MapUserMemory.info = gcmPTR_TO_NAME(info); -+ -+ /* Clear temp storage. */ -+ info = gcvNULL; -+ break; -+ -+ case gcvHAL_UNMAP_USER_MEMORY: -+ /* Unmap user memory. */ -+ gcmkERR_BREAK(gckOS_UnmapUserMemory( -+ Kernel->os, -+ gcvCORE_VG, -+ gcmUINT64_TO_PTR(kernelInterface->u.UnmapUserMemory.memory), -+ (gctSIZE_T) kernelInterface->u.UnmapUserMemory.size, -+ gcmNAME_TO_PTR(kernelInterface->u.UnmapUserMemory.info), -+ kernelInterface->u.UnmapUserMemory.address -+ )); -+ -+ gcmRELEASE_NAME(kernelInterface->u.UnmapUserMemory.info); -+ break; -+ -+ case gcvHAL_LOCK_VIDEO_MEMORY: -+ gcmkONERROR(gckKERNEL_LockVideoMemory(Kernel, gcvCORE_VG, processID, FromUser, Interface)); -+ break; -+ -+ case gcvHAL_UNLOCK_VIDEO_MEMORY: -+ gcmkONERROR(gckKERNEL_UnlockVideoMemory(Kernel, processID, Interface)); -+ break; -+ -+ case gcvHAL_USER_SIGNAL: -+ /* Dispatch depends on the user signal subcommands. */ -+ switch(Interface->u.UserSignal.command) -+ { -+ case gcvUSER_SIGNAL_CREATE: -+ /* Create a signal used in the user space. */ -+ gcmkERR_BREAK( -+ gckOS_CreateUserSignal(Kernel->os, -+ Interface->u.UserSignal.manualReset, -+ &Interface->u.UserSignal.id)); -+ -+ gcmkVERIFY_OK( -+ gckKERNEL_AddProcessDB(Kernel, -+ processID, gcvDB_SIGNAL, -+ gcmINT2PTR(Interface->u.UserSignal.id), -+ gcvNULL, -+ 0)); -+ break; -+ -+ case gcvUSER_SIGNAL_DESTROY: -+ gcmkVERIFY_OK(gckKERNEL_RemoveProcessDB( -+ Kernel, -+ processID, gcvDB_SIGNAL, -+ gcmINT2PTR(Interface->u.UserSignal.id))); -+ -+ /* Destroy the signal. */ -+ gcmkERR_BREAK( -+ gckOS_DestroyUserSignal(Kernel->os, -+ Interface->u.UserSignal.id)); -+ -+ break; -+ -+ case gcvUSER_SIGNAL_SIGNAL: -+ /* Signal the signal. */ -+ gcmkERR_BREAK( -+ gckOS_SignalUserSignal(Kernel->os, -+ Interface->u.UserSignal.id, -+ Interface->u.UserSignal.state)); -+ break; -+ -+ case gcvUSER_SIGNAL_WAIT: -+ /* Wait on the signal. */ -+ status = gckOS_WaitUserSignal(Kernel->os, -+ Interface->u.UserSignal.id, -+ Interface->u.UserSignal.wait); -+ break; -+ -+ default: -+ /* Invalid user signal command. */ -+ gcmkERR_BREAK(gcvSTATUS_INVALID_ARGUMENT); -+ } -+ break; -+ -+ case gcvHAL_COMMIT: -+ /* Commit a command and context buffer. */ -+ gcmkERR_BREAK(gckVGCOMMAND_Commit( -+ Kernel->vg->command, -+ gcmUINT64_TO_PTR(kernelInterface->u.VGCommit.context), -+ gcmUINT64_TO_PTR(kernelInterface->u.VGCommit.queue), -+ kernelInterface->u.VGCommit.entryCount, -+ gcmUINT64_TO_PTR(kernelInterface->u.VGCommit.taskTable) -+ )); -+ break; -+ case gcvHAL_VERSION: -+ kernelInterface->u.Version.major = gcvVERSION_MAJOR; -+ kernelInterface->u.Version.minor = gcvVERSION_MINOR; -+ kernelInterface->u.Version.patch = gcvVERSION_PATCH; -+ kernelInterface->u.Version.build = gcvVERSION_BUILD; -+ status = gcvSTATUS_OK; -+ break; -+ -+ case gcvHAL_GET_BASE_ADDRESS: -+ /* Get base address. */ -+ gcmkERR_BREAK( -+ gckOS_GetBaseAddress(Kernel->os, -+ &kernelInterface->u.GetBaseAddress.baseAddress)); -+ break; -+ case gcvHAL_IMPORT_VIDEO_MEMORY: -+ gcmkONERROR(gckVIDMEM_NODE_Import(Kernel, -+ Interface->u.ImportVideoMemory.name, -+ &Interface->u.ImportVideoMemory.handle)); -+ gcmkONERROR(gckKERNEL_AddProcessDB(Kernel, -+ processID, gcvDB_VIDEO_MEMORY, -+ gcmINT2PTR(Interface->u.ImportVideoMemory.handle), -+ gcvNULL, -+ 0)); -+ break; -+ -+ case gcvHAL_NAME_VIDEO_MEMORY: -+ gcmkONERROR(gckVIDMEM_NODE_Name(Kernel, -+ Interface->u.NameVideoMemory.handle, -+ &Interface->u.NameVideoMemory.name)); -+ break; -+ -+ case gcvHAL_DATABASE: -+ gcmkONERROR(gckKERNEL_QueryDatabase(Kernel, processID, Interface)); -+ break; -+ case gcvHAL_SHBUF: -+ { -+ gctSHBUF shBuf; -+ gctPOINTER uData; -+ gctUINT32 bytes; -+ -+ switch (Interface->u.ShBuf.command) -+ { -+ case gcvSHBUF_CREATE: -+ bytes = Interface->u.ShBuf.bytes; -+ -+ /* Create. */ -+ gcmkONERROR(gckKERNEL_CreateShBuffer(Kernel, bytes, &shBuf)); -+ -+ Interface->u.ShBuf.id = gcmPTR_TO_UINT64(shBuf); -+ -+ gcmkVERIFY_OK( -+ gckKERNEL_AddProcessDB(Kernel, -+ processID, -+ gcvDB_SHBUF, -+ shBuf, -+ gcvNULL, -+ 0)); -+ break; -+ -+ case gcvSHBUF_DESTROY: -+ shBuf = gcmUINT64_TO_PTR(Interface->u.ShBuf.id); -+ -+ /* Check db first to avoid illegal destroy in the process. */ -+ gcmkONERROR( -+ gckKERNEL_RemoveProcessDB(Kernel, -+ processID, -+ gcvDB_SHBUF, -+ shBuf)); -+ -+ gcmkONERROR(gckKERNEL_DestroyShBuffer(Kernel, shBuf)); -+ break; -+ -+ case gcvSHBUF_MAP: -+ shBuf = gcmUINT64_TO_PTR(Interface->u.ShBuf.id); -+ -+ /* Map for current process access. */ -+ gcmkONERROR(gckKERNEL_MapShBuffer(Kernel, shBuf)); -+ -+ gcmkVERIFY_OK( -+ gckKERNEL_AddProcessDB(Kernel, -+ processID, -+ gcvDB_SHBUF, -+ shBuf, -+ gcvNULL, -+ 0)); -+ break; -+ -+ case gcvSHBUF_WRITE: -+ shBuf = gcmUINT64_TO_PTR(Interface->u.ShBuf.id); -+ uData = gcmUINT64_TO_PTR(Interface->u.ShBuf.data); -+ bytes = Interface->u.ShBuf.bytes; -+ -+ /* Write. */ -+ gcmkONERROR( -+ gckKERNEL_WriteShBuffer(Kernel, shBuf, uData, bytes)); -+ break; -+ -+ case gcvSHBUF_READ: -+ shBuf = gcmUINT64_TO_PTR(Interface->u.ShBuf.id); -+ uData = gcmUINT64_TO_PTR(Interface->u.ShBuf.data); -+ bytes = Interface->u.ShBuf.bytes; -+ -+ /* Read. */ -+ gcmkONERROR( -+ gckKERNEL_ReadShBuffer(Kernel, -+ shBuf, -+ uData, -+ bytes, -+ &bytes)); -+ -+ /* Return copied size. */ -+ Interface->u.ShBuf.bytes = bytes; -+ break; -+ -+ default: -+ gcmkONERROR(gcvSTATUS_INVALID_ARGUMENT); -+ break; -+ } -+ } -+ break; -+ default: -+ /* Invalid command. */ -+ status = gcvSTATUS_INVALID_ARGUMENT; -+ } -+ -+OnError: -+ /* Save status. */ -+ kernelInterface->status = status; -+ -+ gcmkFOOTER(); -+ -+ /* Return the status. */ -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckKERNEL_QueryCommandBuffer -+** -+** Query command buffer attributes. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckVGHARDWARE object. -+** -+** OUTPUT: -+** -+** gcsCOMMAND_BUFFER_INFO_PTR Information -+** Pointer to the information structure to receive buffer attributes. -+*/ -+gceSTATUS -+gckKERNEL_QueryCommandBuffer( -+ IN gckKERNEL Kernel, -+ OUT gcsCOMMAND_BUFFER_INFO_PTR Information -+ ) -+{ -+ gceSTATUS status; -+ -+ gcmkHEADER_ARG("Kernel=0x%x *Pool=0x%x", -+ Kernel, Information); -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ -+ /* Get the information. */ -+ status = gckVGCOMMAND_QueryCommandBuffer(Kernel->vg->command, Information); -+ -+ gcmkFOOTER(); -+ /* Return status. */ -+ return status; -+} -+ -+#endif /* gcdENABLE_VG */ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_vg.h linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_vg.h ---- linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_vg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_vg.h 2015-11-30 17:56:13.584137459 +0100 -@@ -0,0 +1,85 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#ifndef __gc_hal_kernel_vg_h_ -+#define __gc_hal_kernel_vg_h_ -+ -+#include "gc_hal.h" -+#include "gc_hal_driver.h" -+#include "gc_hal_kernel_hardware.h" -+ -+/******************************************************************************\ -+********************************** Structures ********************************** -+\******************************************************************************/ -+ -+/* gckKERNEL object. */ -+struct _gckVGKERNEL -+{ -+ /* Object. */ -+ gcsOBJECT object; -+ -+ /* Pointer to gckOS object. */ -+ gckOS os; -+ -+ /* Pointer to gckHARDWARE object. */ -+ gckVGHARDWARE hardware; -+ -+ /* Pointer to gckINTERRUPT object. */ -+ gckVGINTERRUPT interrupt; -+ -+ /* Pointer to gckCOMMAND object. */ -+ gckVGCOMMAND command; -+ -+ /* Pointer to context. */ -+ gctPOINTER context; -+ -+ /* Pointer to gckMMU object. */ -+ gckVGMMU mmu; -+ -+ gckKERNEL kernel; -+}; -+ -+/* gckMMU object. */ -+struct _gckVGMMU -+{ -+ /* The object. */ -+ gcsOBJECT object; -+ -+ /* Pointer to gckOS object. */ -+ gckOS os; -+ -+ /* Pointer to gckHARDWARE object. */ -+ gckVGHARDWARE hardware; -+ -+ /* The page table mutex. */ -+ gctPOINTER mutex; -+ -+ /* Page table information. */ -+ gctSIZE_T pageTableSize; -+ gctPHYS_ADDR pageTablePhysical; -+ gctPOINTER pageTableLogical; -+ -+ /* Allocation index. */ -+ gctUINT32 entryCount; -+ gctUINT32 entry; -+}; -+ -+#endif /* __gc_hal_kernel_h_ */ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_video_memory.c linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_video_memory.c ---- linux-4.1.13.orig/drivers/gpu/galcore/gc_hal_kernel_video_memory.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/gc_hal_kernel_video_memory.c 2015-11-30 17:56:13.584137459 +0100 -@@ -0,0 +1,2734 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#include "gc_hal_kernel_precomp.h" -+ -+#define _GC_OBJ_ZONE gcvZONE_VIDMEM -+ -+/******************************************************************************\ -+******************************* Private Functions ****************************** -+\******************************************************************************/ -+ -+/******************************************************************************* -+** -+** _Split -+** -+** Split a node on the required byte boundary. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gcuVIDMEM_NODE_PTR Node -+** Pointer to the node to split. -+** -+** gctSIZE_T Bytes -+** Number of bytes to keep in the node. -+** -+** OUTPUT: -+** -+** Nothing. -+** -+** RETURNS: -+** -+** gctBOOL -+** gcvTRUE if the node was split successfully, or gcvFALSE if there is an -+** error. -+** -+*/ -+static gctBOOL -+_Split( -+ IN gckOS Os, -+ IN gcuVIDMEM_NODE_PTR Node, -+ IN gctSIZE_T Bytes -+ ) -+{ -+ gcuVIDMEM_NODE_PTR node; -+ gctPOINTER pointer = gcvNULL; -+ -+ /* Make sure the byte boundary makes sense. */ -+ if ((Bytes <= 0) || (Bytes > Node->VidMem.bytes)) -+ { -+ return gcvFALSE; -+ } -+ -+ /* Allocate a new gcuVIDMEM_NODE object. */ -+ if (gcmIS_ERROR(gckOS_Allocate(Os, -+ gcmSIZEOF(gcuVIDMEM_NODE), -+ &pointer))) -+ { -+ /* Error. */ -+ return gcvFALSE; -+ } -+ -+ node = pointer; -+ -+ /* Initialize gcuVIDMEM_NODE structure. */ -+ node->VidMem.offset = Node->VidMem.offset + Bytes; -+ node->VidMem.bytes = Node->VidMem.bytes - Bytes; -+ node->VidMem.alignment = 0; -+ node->VidMem.locked = 0; -+ node->VidMem.memory = Node->VidMem.memory; -+ node->VidMem.pool = Node->VidMem.pool; -+ node->VidMem.physical = Node->VidMem.physical; -+ -+ /* Insert node behind specified node. */ -+ node->VidMem.next = Node->VidMem.next; -+ node->VidMem.prev = Node; -+ Node->VidMem.next = node->VidMem.next->VidMem.prev = node; -+ -+ /* Insert free node behind specified node. */ -+ node->VidMem.nextFree = Node->VidMem.nextFree; -+ node->VidMem.prevFree = Node; -+ Node->VidMem.nextFree = node->VidMem.nextFree->VidMem.prevFree = node; -+ -+ /* Adjust size of specified node. */ -+ Node->VidMem.bytes = Bytes; -+ -+ /* Success. */ -+ return gcvTRUE; -+} -+ -+/******************************************************************************* -+** -+** _Merge -+** -+** Merge two adjacent nodes together. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gcuVIDMEM_NODE_PTR Node -+** Pointer to the first of the two nodes to merge. -+** -+** OUTPUT: -+** -+** Nothing. -+** -+*/ -+static gceSTATUS -+_Merge( -+ IN gckOS Os, -+ IN gcuVIDMEM_NODE_PTR Node -+ ) -+{ -+ gcuVIDMEM_NODE_PTR node; -+ gceSTATUS status; -+ -+ /* Save pointer to next node. */ -+ node = Node->VidMem.next; -+ -+ /* This is a good time to make sure the heap is not corrupted. */ -+ if (Node->VidMem.offset + Node->VidMem.bytes != node->VidMem.offset) -+ { -+ /* Corrupted heap. */ -+ gcmkASSERT( -+ Node->VidMem.offset + Node->VidMem.bytes == node->VidMem.offset); -+ return gcvSTATUS_HEAP_CORRUPTED; -+ } -+ -+ /* Adjust byte count. */ -+ Node->VidMem.bytes += node->VidMem.bytes; -+ -+ /* Unlink next node from linked list. */ -+ Node->VidMem.next = node->VidMem.next; -+ Node->VidMem.nextFree = node->VidMem.nextFree; -+ -+ Node->VidMem.next->VidMem.prev = -+ Node->VidMem.nextFree->VidMem.prevFree = Node; -+ -+ /* Free next node. */ -+ status = gcmkOS_SAFE_FREE(Os, node); -+ return status; -+} -+ -+/******************************************************************************\ -+******************************* gckVIDMEM API Code ****************************** -+\******************************************************************************/ -+ -+/******************************************************************************* -+** -+** gckVIDMEM_ConstructVirtual -+** -+** Construct a new gcuVIDMEM_NODE union for virtual memory. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** gctSIZE_T Bytes -+** Number of byte to allocate. -+** -+** OUTPUT: -+** -+** gcuVIDMEM_NODE_PTR * Node -+** Pointer to a variable that receives the gcuVIDMEM_NODE union pointer. -+*/ -+gceSTATUS -+gckVIDMEM_ConstructVirtual( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 Flag, -+ IN gctSIZE_T Bytes, -+ OUT gcuVIDMEM_NODE_PTR * Node -+ ) -+{ -+ gckOS os; -+ gceSTATUS status; -+ gcuVIDMEM_NODE_PTR node = gcvNULL; -+ gctPOINTER pointer = gcvNULL; -+ gctINT i; -+ -+ gcmkHEADER_ARG("Kernel=0x%x Flag=%x Bytes=%lu", Kernel, Flag, Bytes); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ gcmkVERIFY_ARGUMENT(Bytes > 0); -+ gcmkVERIFY_ARGUMENT(Node != gcvNULL); -+ -+ /* Extract the gckOS object pointer. */ -+ os = Kernel->os; -+ gcmkVERIFY_OBJECT(os, gcvOBJ_OS); -+ -+ /* Allocate an gcuVIDMEM_NODE union. */ -+ gcmkONERROR(gckOS_Allocate(os, gcmSIZEOF(gcuVIDMEM_NODE), &pointer)); -+ -+ node = pointer; -+ -+ /* Initialize gcuVIDMEM_NODE union for virtual memory. */ -+ node->Virtual.kernel = Kernel; -+ node->Virtual.contiguous = Flag & gcvALLOC_FLAG_CONTIGUOUS; -+ node->Virtual.logical = gcvNULL; -+#if gcdENABLE_VG -+ node->Virtual.kernelVirtual = gcvNULL; -+#endif -+ -+ for (i = 0; i < gcdMAX_GPU_COUNT; i++) -+ { -+ node->Virtual.lockeds[i] = 0; -+ node->Virtual.pageTables[i] = gcvNULL; -+ node->Virtual.lockKernels[i] = gcvNULL; -+ } -+ -+ gcmkONERROR(gckOS_GetProcessID(&node->Virtual.processID)); -+ -+ /* Allocate the virtual memory. */ -+ gcmkONERROR( -+ gckOS_AllocatePagedMemoryEx(os, -+ Flag, -+ node->Virtual.bytes = Bytes, -+ &node->Virtual.gid, -+ &node->Virtual.physical)); -+ -+ /* Return pointer to the gcuVIDMEM_NODE union. */ -+ *Node = node; -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM, -+ "Created virtual node 0x%x for %u bytes @ 0x%x", -+ node, Bytes, node->Virtual.physical); -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Node=0x%x", *Node); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Roll back. */ -+ if (node != gcvNULL) -+ { -+ /* Free the structure. */ -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, node)); -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckVIDMEM_DestroyVirtual -+** -+** Destroy an gcuVIDMEM_NODE union for virtual memory. -+** -+** INPUT: -+** -+** gcuVIDMEM_NODE_PTR Node -+** Pointer to a gcuVIDMEM_NODE union. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckVIDMEM_DestroyVirtual( -+ IN gcuVIDMEM_NODE_PTR Node -+ ) -+{ -+ gckOS os; -+ -+ gcmkHEADER_ARG("Node=0x%x", Node); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Node->Virtual.kernel, gcvOBJ_KERNEL); -+ -+ /* Extact the gckOS object pointer. */ -+ os = Node->Virtual.kernel->os; -+ gcmkVERIFY_OBJECT(os, gcvOBJ_OS); -+ -+ /* Delete the gcuVIDMEM_NODE union. */ -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, Node)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckVIDMEM_Construct -+** -+** Construct a new gckVIDMEM object. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctUINT32 BaseAddress -+** Base address for the video memory heap. -+** -+** gctSIZE_T Bytes -+** Number of bytes in the video memory heap. -+** -+** gctSIZE_T Threshold -+** Minimum number of bytes beyond am allocation before the node is -+** split. Can be used as a minimum alignment requirement. -+** -+** gctSIZE_T BankSize -+** Number of bytes per physical memory bank. Used by bank -+** optimization. -+** -+** OUTPUT: -+** -+** gckVIDMEM * Memory -+** Pointer to a variable that will hold the pointer to the gckVIDMEM -+** object. -+*/ -+gceSTATUS -+gckVIDMEM_Construct( -+ IN gckOS Os, -+ IN gctUINT32 BaseAddress, -+ IN gctSIZE_T Bytes, -+ IN gctSIZE_T Threshold, -+ IN gctSIZE_T BankSize, -+ OUT gckVIDMEM * Memory -+ ) -+{ -+ gckVIDMEM memory = gcvNULL; -+ gceSTATUS status; -+ gcuVIDMEM_NODE_PTR node; -+ gctINT i, banks = 0; -+ gctPOINTER pointer = gcvNULL; -+ gctUINT32 heapBytes; -+ gctUINT32 bankSize; -+ -+ gcmkHEADER_ARG("Os=0x%x BaseAddress=%08x Bytes=%lu Threshold=%lu " -+ "BankSize=%lu", -+ Os, BaseAddress, Bytes, Threshold, BankSize); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Os, gcvOBJ_OS); -+ gcmkVERIFY_ARGUMENT(Bytes > 0); -+ gcmkVERIFY_ARGUMENT(Memory != gcvNULL); -+ -+ gcmkSAFECASTSIZET(heapBytes, Bytes); -+ gcmkSAFECASTSIZET(bankSize, BankSize); -+ -+ /* Allocate the gckVIDMEM object. */ -+ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(struct _gckVIDMEM), &pointer)); -+ -+ memory = pointer; -+ -+ /* Initialize the gckVIDMEM object. */ -+ memory->object.type = gcvOBJ_VIDMEM; -+ memory->os = Os; -+ -+ /* Set video memory heap information. */ -+ memory->baseAddress = BaseAddress; -+ memory->bytes = heapBytes; -+ memory->freeBytes = heapBytes; -+ memory->threshold = Threshold; -+ memory->mutex = gcvNULL; -+ -+ BaseAddress = 0; -+ -+ /* Walk all possible banks. */ -+ for (i = 0; i < gcmCOUNTOF(memory->sentinel); ++i) -+ { -+ gctUINT32 bytes; -+ -+ if (BankSize == 0) -+ { -+ /* Use all bytes for the first bank. */ -+ bytes = heapBytes; -+ } -+ else -+ { -+ /* Compute number of bytes for this bank. */ -+ bytes = gcmALIGN(BaseAddress + 1, bankSize) - BaseAddress; -+ -+ if (bytes > heapBytes) -+ { -+ /* Make sure we don't exceed the total number of bytes. */ -+ bytes = heapBytes; -+ } -+ } -+ -+ if (bytes == 0) -+ { -+ /* Mark heap is not used. */ -+ memory->sentinel[i].VidMem.next = -+ memory->sentinel[i].VidMem.prev = -+ memory->sentinel[i].VidMem.nextFree = -+ memory->sentinel[i].VidMem.prevFree = gcvNULL; -+ continue; -+ } -+ -+ /* Allocate one gcuVIDMEM_NODE union. */ -+ gcmkONERROR(gckOS_Allocate(Os, gcmSIZEOF(gcuVIDMEM_NODE), &pointer)); -+ -+ node = pointer; -+ -+ /* Initialize gcuVIDMEM_NODE union. */ -+ node->VidMem.memory = memory; -+ -+ node->VidMem.next = -+ node->VidMem.prev = -+ node->VidMem.nextFree = -+ node->VidMem.prevFree = &memory->sentinel[i]; -+ -+ node->VidMem.offset = BaseAddress; -+ node->VidMem.bytes = bytes; -+ node->VidMem.alignment = 0; -+ node->VidMem.physical = 0; -+ node->VidMem.pool = gcvPOOL_UNKNOWN; -+ -+ node->VidMem.locked = 0; -+ -+#if gcdENABLE_VG -+ node->VidMem.kernelVirtual = gcvNULL; -+#endif -+ -+ /* Initialize the linked list of nodes. */ -+ memory->sentinel[i].VidMem.next = -+ memory->sentinel[i].VidMem.prev = -+ memory->sentinel[i].VidMem.nextFree = -+ memory->sentinel[i].VidMem.prevFree = node; -+ -+ /* Mark sentinel. */ -+ memory->sentinel[i].VidMem.bytes = 0; -+ -+ /* Adjust address for next bank. */ -+ BaseAddress += bytes; -+ heapBytes -= bytes; -+ banks ++; -+ } -+ -+ /* Assign all the bank mappings. */ -+ memory->mapping[gcvSURF_RENDER_TARGET] = banks - 1; -+ memory->mapping[gcvSURF_BITMAP] = banks - 1; -+ if (banks > 1) --banks; -+ memory->mapping[gcvSURF_DEPTH] = banks - 1; -+ memory->mapping[gcvSURF_HIERARCHICAL_DEPTH] = banks - 1; -+ if (banks > 1) --banks; -+ memory->mapping[gcvSURF_TEXTURE] = banks - 1; -+ if (banks > 1) --banks; -+ memory->mapping[gcvSURF_VERTEX] = banks - 1; -+ if (banks > 1) --banks; -+ memory->mapping[gcvSURF_INDEX] = banks - 1; -+ if (banks > 1) --banks; -+ memory->mapping[gcvSURF_TILE_STATUS] = banks - 1; -+ if (banks > 1) --banks; -+ memory->mapping[gcvSURF_TYPE_UNKNOWN] = 0; -+ -+#if gcdENABLE_VG -+ memory->mapping[gcvSURF_IMAGE] = 0; -+ memory->mapping[gcvSURF_MASK] = 0; -+ memory->mapping[gcvSURF_SCISSOR] = 0; -+#endif -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM, -+ "[GALCORE] INDEX: bank %d", -+ memory->mapping[gcvSURF_INDEX]); -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM, -+ "[GALCORE] VERTEX: bank %d", -+ memory->mapping[gcvSURF_VERTEX]); -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM, -+ "[GALCORE] TEXTURE: bank %d", -+ memory->mapping[gcvSURF_TEXTURE]); -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM, -+ "[GALCORE] RENDER_TARGET: bank %d", -+ memory->mapping[gcvSURF_RENDER_TARGET]); -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM, -+ "[GALCORE] DEPTH: bank %d", -+ memory->mapping[gcvSURF_DEPTH]); -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM, -+ "[GALCORE] TILE_STATUS: bank %d", -+ memory->mapping[gcvSURF_TILE_STATUS]); -+ -+ /* Allocate the mutex. */ -+ gcmkONERROR(gckOS_CreateMutex(Os, &memory->mutex)); -+ -+ /* Return pointer to the gckVIDMEM object. */ -+ *Memory = memory; -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Memory=0x%x", *Memory); -+ return gcvSTATUS_OK; -+ -+OnError: -+ /* Roll back. */ -+ if (memory != gcvNULL) -+ { -+ if (memory->mutex != gcvNULL) -+ { -+ /* Delete the mutex. */ -+ gcmkVERIFY_OK(gckOS_DeleteMutex(Os, memory->mutex)); -+ } -+ -+ for (i = 0; i < banks; ++i) -+ { -+ /* Free the heap. */ -+ gcmkASSERT(memory->sentinel[i].VidMem.next != gcvNULL); -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Os, memory->sentinel[i].VidMem.next)); -+ } -+ -+ /* Free the object. */ -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Os, memory)); -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckVIDMEM_Destroy -+** -+** Destroy an gckVIDMEM object. -+** -+** INPUT: -+** -+** gckVIDMEM Memory -+** Pointer to an gckVIDMEM object to destroy. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckVIDMEM_Destroy( -+ IN gckVIDMEM Memory -+ ) -+{ -+ gcuVIDMEM_NODE_PTR node, next; -+ gctINT i; -+ -+ gcmkHEADER_ARG("Memory=0x%x", Memory); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Memory, gcvOBJ_VIDMEM); -+ -+ /* Walk all sentinels. */ -+ for (i = 0; i < gcmCOUNTOF(Memory->sentinel); ++i) -+ { -+ /* Bail out of the heap is not used. */ -+ if (Memory->sentinel[i].VidMem.next == gcvNULL) -+ { -+ break; -+ } -+ -+ /* Walk all the nodes until we reach the sentinel. */ -+ for (node = Memory->sentinel[i].VidMem.next; -+ node->VidMem.bytes != 0; -+ node = next) -+ { -+ /* Save pointer to the next node. */ -+ next = node->VidMem.next; -+ -+ /* Free the node. */ -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Memory->os, node)); -+ } -+ } -+ -+ /* Free the mutex. */ -+ gcmkVERIFY_OK(gckOS_DeleteMutex(Memory->os, Memory->mutex)); -+ -+ /* Mark the object as unknown. */ -+ Memory->object.type = gcvOBJ_UNKNOWN; -+ -+ /* Free the gckVIDMEM object. */ -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Memory->os, Memory)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+#if gcdENABLE_BANK_ALIGNMENT -+ -+#if !gcdBANK_BIT_START -+#error gcdBANK_BIT_START not defined. -+#endif -+ -+#if !gcdBANK_BIT_END -+#error gcdBANK_BIT_END not defined. -+#endif -+/******************************************************************************* -+** _GetSurfaceBankAlignment -+** -+** Return the required offset alignment required to the make BaseAddress -+** aligned properly. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to gcoOS object. -+** -+** gceSURF_TYPE Type -+** Type of allocation. -+** -+** gctUINT32 BaseAddress -+** Base address of current video memory node. -+** -+** OUTPUT: -+** -+** gctUINT32_PTR AlignmentOffset -+** Pointer to a variable that will hold the number of bytes to skip in -+** the current video memory node in order to make the alignment bank -+** aligned. -+*/ -+static gceSTATUS -+_GetSurfaceBankAlignment( -+ IN gckKERNEL Kernel, -+ IN gceSURF_TYPE Type, -+ IN gctUINT32 BaseAddress, -+ OUT gctUINT32_PTR AlignmentOffset -+ ) -+{ -+ gctUINT32 bank; -+ /* To retrieve the bank. */ -+ static const gctUINT32 bankMask = (0xFFFFFFFF << gcdBANK_BIT_START) -+ ^ (0xFFFFFFFF << (gcdBANK_BIT_END + 1)); -+ -+ /* To retrieve the bank and all the lower bytes. */ -+ static const gctUINT32 byteMask = ~(0xFFFFFFFF << (gcdBANK_BIT_END + 1)); -+ -+ gcmkHEADER_ARG("Type=%d BaseAddress=0x%x ", Type, BaseAddress); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_ARGUMENT(AlignmentOffset != gcvNULL); -+ -+ switch (Type) -+ { -+ case gcvSURF_RENDER_TARGET: -+ bank = (BaseAddress & bankMask) >> (gcdBANK_BIT_START); -+ -+ /* Align to the first bank. */ -+ *AlignmentOffset = (bank == 0) ? -+ 0 : -+ ((1 << (gcdBANK_BIT_END + 1)) + 0) - (BaseAddress & byteMask); -+ break; -+ -+ case gcvSURF_DEPTH: -+ bank = (BaseAddress & bankMask) >> (gcdBANK_BIT_START); -+ -+ /* Align to the third bank. */ -+ *AlignmentOffset = (bank == 2) ? -+ 0 : -+ ((1 << (gcdBANK_BIT_END + 1)) + (2 << gcdBANK_BIT_START)) - (BaseAddress & byteMask); -+ -+ /* Minimum 256 byte alignment needed for fast_msaa. */ -+ if ((gcdBANK_CHANNEL_BIT > 7) || -+ ((gckHARDWARE_IsFeatureAvailable(Kernel->hardware, gcvFEATURE_FAST_MSAA) != gcvSTATUS_TRUE) && -+ (gckHARDWARE_IsFeatureAvailable(Kernel->hardware, gcvFEATURE_SMALL_MSAA) != gcvSTATUS_TRUE))) -+ { -+ /* Add a channel offset at the channel bit. */ -+ *AlignmentOffset += (1 << gcdBANK_CHANNEL_BIT); -+ } -+ break; -+ -+ default: -+ /* no alignment needed. */ -+ *AlignmentOffset = 0; -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER_ARG("*AlignmentOffset=%u", *AlignmentOffset); -+ return gcvSTATUS_OK; -+} -+#endif -+ -+static gcuVIDMEM_NODE_PTR -+_FindNode( -+ IN gckKERNEL Kernel, -+ IN gckVIDMEM Memory, -+ IN gctINT Bank, -+ IN gctSIZE_T Bytes, -+ IN gceSURF_TYPE Type, -+ IN OUT gctUINT32_PTR Alignment -+ ) -+{ -+ gcuVIDMEM_NODE_PTR node; -+ gctUINT32 alignment; -+ -+#if gcdENABLE_BANK_ALIGNMENT -+ gctUINT32 bankAlignment; -+ gceSTATUS status; -+#endif -+ -+ if (Memory->sentinel[Bank].VidMem.nextFree == gcvNULL) -+ { -+ /* No free nodes left. */ -+ return gcvNULL; -+ } -+ -+#if gcdENABLE_BANK_ALIGNMENT -+ /* Walk all free nodes until we have one that is big enough or we have -+ ** reached the sentinel. */ -+ for (node = Memory->sentinel[Bank].VidMem.nextFree; -+ node->VidMem.bytes != 0; -+ node = node->VidMem.nextFree) -+ { -+ if (node->VidMem.bytes < Bytes) -+ { -+ continue; -+ } -+ -+ gcmkONERROR(_GetSurfaceBankAlignment( -+ Kernel, -+ Type, -+ node->VidMem.memory->baseAddress + node->VidMem.offset, -+ &bankAlignment)); -+ -+ bankAlignment = gcmALIGN(bankAlignment, *Alignment); -+ -+ /* Compute number of bytes to skip for alignment. */ -+ alignment = (*Alignment == 0) -+ ? 0 -+ : (*Alignment - (node->VidMem.offset % *Alignment)); -+ -+ if (alignment == *Alignment) -+ { -+ /* Node is already aligned. */ -+ alignment = 0; -+ } -+ -+ if (node->VidMem.bytes >= Bytes + alignment + bankAlignment) -+ { -+ /* This node is big enough. */ -+ *Alignment = alignment + bankAlignment; -+ return node; -+ } -+ } -+#endif -+ -+ /* Walk all free nodes until we have one that is big enough or we have -+ reached the sentinel. */ -+ for (node = Memory->sentinel[Bank].VidMem.nextFree; -+ node->VidMem.bytes != 0; -+ node = node->VidMem.nextFree) -+ { -+ gctUINT offset; -+ -+ gctINT modulo; -+ -+ gcmkSAFECASTSIZET(offset, node->VidMem.offset); -+ -+ modulo = gckMATH_ModuloInt(offset, *Alignment); -+ -+ /* Compute number of bytes to skip for alignment. */ -+ alignment = (*Alignment == 0) ? 0 : (*Alignment - modulo); -+ -+ if (alignment == *Alignment) -+ { -+ /* Node is already aligned. */ -+ alignment = 0; -+ } -+ -+ if (node->VidMem.bytes >= Bytes + alignment) -+ { -+ /* This node is big enough. */ -+ *Alignment = alignment; -+ return node; -+ } -+ } -+ -+#if gcdENABLE_BANK_ALIGNMENT -+OnError: -+#endif -+ /* Not enough memory. */ -+ return gcvNULL; -+} -+ -+/******************************************************************************* -+** -+** gckVIDMEM_AllocateLinear -+** -+** Allocate linear memory from the gckVIDMEM object. -+** -+** INPUT: -+** -+** gckVIDMEM Memory -+** Pointer to an gckVIDMEM object. -+** -+** gctSIZE_T Bytes -+** Number of bytes to allocate. -+** -+** gctUINT32 Alignment -+** Byte alignment for allocation. -+** -+** gceSURF_TYPE Type -+** Type of surface to allocate (use by bank optimization). -+** -+** gctBOOL Specified -+** If user must use this pool, it should set Specified to gcvTRUE, -+** otherwise allocator may reserve some memory for other usage, such -+** as small block size allocation request. -+** -+** OUTPUT: -+** -+** gcuVIDMEM_NODE_PTR * Node -+** Pointer to a variable that will hold the allocated memory node. -+*/ -+gceSTATUS -+gckVIDMEM_AllocateLinear( -+ IN gckKERNEL Kernel, -+ IN gckVIDMEM Memory, -+ IN gctSIZE_T Bytes, -+ IN gctUINT32 Alignment, -+ IN gceSURF_TYPE Type, -+ IN gctBOOL Specified, -+ OUT gcuVIDMEM_NODE_PTR * Node -+ ) -+{ -+ gceSTATUS status; -+ gcuVIDMEM_NODE_PTR node; -+ gctUINT32 alignment; -+ gctINT bank, i; -+ gctBOOL acquired = gcvFALSE; -+ -+ gcmkHEADER_ARG("Memory=0x%x Bytes=%lu Alignment=%u Type=%d", -+ Memory, Bytes, Alignment, Type); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_OBJECT(Memory, gcvOBJ_VIDMEM); -+ gcmkVERIFY_ARGUMENT(Bytes > 0); -+ gcmkVERIFY_ARGUMENT(Node != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Type < gcvSURF_NUM_TYPES); -+ -+ /* Acquire the mutex. */ -+ gcmkONERROR(gckOS_AcquireMutex(Memory->os, Memory->mutex, gcvINFINITE)); -+ -+ acquired = gcvTRUE; -+ -+ if (Bytes > Memory->freeBytes) -+ { -+ /* Not enough memory. */ -+ status = gcvSTATUS_OUT_OF_MEMORY; -+ goto OnError; -+ } -+ -+#if gcdSMALL_BLOCK_SIZE -+ if ((Memory->freeBytes < (Memory->bytes/gcdRATIO_FOR_SMALL_MEMORY)) -+ && (Bytes >= gcdSMALL_BLOCK_SIZE) -+ && (Specified == gcvFALSE) -+ ) -+ { -+ /* The left memory is for small memory.*/ -+ status = gcvSTATUS_OUT_OF_MEMORY; -+ goto OnError; -+ } -+#endif -+ -+ /* Find the default bank for this surface type. */ -+ gcmkASSERT((gctINT) Type < gcmCOUNTOF(Memory->mapping)); -+ bank = Memory->mapping[Type]; -+ alignment = Alignment; -+ -+ /* Find a free node in the default bank. */ -+ node = _FindNode(Kernel, Memory, bank, Bytes, Type, &alignment); -+ -+ /* Out of memory? */ -+ if (node == gcvNULL) -+ { -+ /* Walk all lower banks. */ -+ for (i = bank - 1; i >= 0; --i) -+ { -+ /* Find a free node inside the current bank. */ -+ node = _FindNode(Kernel, Memory, i, Bytes, Type, &alignment); -+ if (node != gcvNULL) -+ { -+ break; -+ } -+ } -+ } -+ -+ if (node == gcvNULL) -+ { -+ /* Walk all upper banks. */ -+ for (i = bank + 1; i < gcmCOUNTOF(Memory->sentinel); ++i) -+ { -+ if (Memory->sentinel[i].VidMem.nextFree == gcvNULL) -+ { -+ /* Abort when we reach unused banks. */ -+ break; -+ } -+ -+ /* Find a free node inside the current bank. */ -+ node = _FindNode(Kernel, Memory, i, Bytes, Type, &alignment); -+ if (node != gcvNULL) -+ { -+ break; -+ } -+ } -+ } -+ -+ if (node == gcvNULL) -+ { -+ /* Out of memory. */ -+ status = gcvSTATUS_OUT_OF_MEMORY; -+ goto OnError; -+ } -+ -+ /* Do we have an alignment? */ -+ if (alignment > 0) -+ { -+ /* Split the node so it is aligned. */ -+ if (_Split(Memory->os, node, alignment)) -+ { -+ /* Successful split, move to aligned node. */ -+ node = node->VidMem.next; -+ -+ /* Remove alignment. */ -+ alignment = 0; -+ } -+ } -+ -+ /* Do we have enough memory after the allocation to split it? */ -+ if (node->VidMem.bytes - Bytes > Memory->threshold) -+ { -+ /* Adjust the node size. */ -+ _Split(Memory->os, node, Bytes); -+ } -+ -+ /* Remove the node from the free list. */ -+ node->VidMem.prevFree->VidMem.nextFree = node->VidMem.nextFree; -+ node->VidMem.nextFree->VidMem.prevFree = node->VidMem.prevFree; -+ node->VidMem.nextFree = -+ node->VidMem.prevFree = gcvNULL; -+ -+ /* Fill in the information. */ -+ node->VidMem.alignment = alignment; -+ node->VidMem.memory = Memory; -+ -+ /* Adjust the number of free bytes. */ -+ Memory->freeBytes -= node->VidMem.bytes; -+ -+#if gcdENABLE_VG -+ node->VidMem.kernelVirtual = gcvNULL; -+#endif -+ -+ /* Release the mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Memory->os, Memory->mutex)); -+ -+ /* Return the pointer to the node. */ -+ *Node = node; -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM, -+ "Allocated %u bytes @ 0x%x [0x%08X]", -+ node->VidMem.bytes, node, node->VidMem.offset); -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Node=0x%x", *Node); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (acquired) -+ { -+ /* Release the mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Memory->os, Memory->mutex)); -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckVIDMEM_Free -+** -+** Free an allocated video memory node. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** gcuVIDMEM_NODE_PTR Node -+** Pointer to a gcuVIDMEM_NODE object. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckVIDMEM_Free( -+ IN gckKERNEL Kernel, -+ IN gcuVIDMEM_NODE_PTR Node -+ ) -+{ -+ gceSTATUS status; -+ gckKERNEL kernel = gcvNULL; -+ gckVIDMEM memory = gcvNULL; -+ gcuVIDMEM_NODE_PTR node; -+ gctBOOL mutexAcquired = gcvFALSE; -+ -+ gcmkHEADER_ARG("Node=0x%x", Node); -+ -+ /* Verify the arguments. */ -+ if ((Node == gcvNULL) -+ || (Node->VidMem.memory == gcvNULL) -+ ) -+ { -+ /* Invalid object. */ -+ gcmkONERROR(gcvSTATUS_INVALID_OBJECT); -+ } -+ -+ /**************************** Video Memory ********************************/ -+ -+ if (Node->VidMem.memory->object.type == gcvOBJ_VIDMEM) -+ { -+ /* Extract pointer to gckVIDMEM object owning the node. */ -+ memory = Node->VidMem.memory; -+ -+ /* Acquire the mutex. */ -+ gcmkONERROR( -+ gckOS_AcquireMutex(memory->os, memory->mutex, gcvINFINITE)); -+ -+ mutexAcquired = gcvTRUE; -+ -+#if gcdENABLE_VG -+ if (Node->VidMem.kernelVirtual) -+ { -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM, -+ "%s(%d) Unmap %x from kernel space.", -+ __FUNCTION__, __LINE__, -+ Node->VidMem.kernelVirtual); -+ -+ gcmkVERIFY_OK( -+ gckOS_UnmapPhysical(memory->os, -+ Node->VidMem.kernelVirtual, -+ Node->VidMem.bytes)); -+ -+ Node->VidMem.kernelVirtual = gcvNULL; -+ } -+#endif -+ -+ /* Check if Node is already freed. */ -+ if (Node->VidMem.nextFree) -+ { -+ /* Node is alread freed. */ -+ gcmkONERROR(gcvSTATUS_INVALID_DATA); -+ } -+ -+ /* Update the number of free bytes. */ -+ memory->freeBytes += Node->VidMem.bytes; -+ -+ /* Find the next free node. */ -+ for (node = Node->VidMem.next; -+ node != gcvNULL && node->VidMem.nextFree == gcvNULL; -+ node = node->VidMem.next) ; -+ -+ /* Insert this node in the free list. */ -+ Node->VidMem.nextFree = node; -+ Node->VidMem.prevFree = node->VidMem.prevFree; -+ -+ Node->VidMem.prevFree->VidMem.nextFree = -+ node->VidMem.prevFree = Node; -+ -+ /* Is the next node a free node and not the sentinel? */ -+ if ((Node->VidMem.next == Node->VidMem.nextFree) -+ && (Node->VidMem.next->VidMem.bytes != 0) -+ ) -+ { -+ /* Merge this node with the next node. */ -+ gcmkONERROR(_Merge(memory->os, node = Node)); -+ gcmkASSERT(node->VidMem.nextFree != node); -+ gcmkASSERT(node->VidMem.prevFree != node); -+ } -+ -+ /* Is the previous node a free node and not the sentinel? */ -+ if ((Node->VidMem.prev == Node->VidMem.prevFree) -+ && (Node->VidMem.prev->VidMem.bytes != 0) -+ ) -+ { -+ /* Merge this node with the previous node. */ -+ gcmkONERROR(_Merge(memory->os, node = Node->VidMem.prev)); -+ gcmkASSERT(node->VidMem.nextFree != node); -+ gcmkASSERT(node->VidMem.prevFree != node); -+ } -+ -+ /* Release the mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(memory->os, memory->mutex)); -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM, -+ "Node 0x%x is freed.", -+ Node); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ } -+ -+ /*************************** Virtual Memory *******************************/ -+ -+ /* Get gckKERNEL object. */ -+ kernel = Node->Virtual.kernel; -+ -+ /* Verify the gckKERNEL object pointer. */ -+ gcmkVERIFY_OBJECT(kernel, gcvOBJ_KERNEL); -+ -+#if gcdENABLE_VG -+ if (Node->Virtual.kernelVirtual) -+ { -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM, -+ "%s(%d) Unmap %x from kernel space.", -+ __FUNCTION__, __LINE__, -+ Node->Virtual.kernelVirtual); -+ -+ gcmkVERIFY_OK( -+ gckOS_UnmapPhysical(kernel->os, -+ Node->Virtual.kernelVirtual, -+ Node->Virtual.bytes)); -+ -+ Node->Virtual.kernelVirtual = gcvNULL; -+ } -+#endif -+ -+ /* Free the virtual memory. */ -+ gcmkVERIFY_OK(gckOS_FreePagedMemory(kernel->os, -+ Node->Virtual.physical, -+ Node->Virtual.bytes)); -+ -+ /* Destroy the gcuVIDMEM_NODE union. */ -+ gcmkVERIFY_OK(gckVIDMEM_DestroyVirtual(Node)); -+ -+ /* Success. */ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (mutexAcquired) -+ { -+ /* Release the mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex( -+ memory->os, memory->mutex -+ )); -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+#if !gcdPROCESS_ADDRESS_SPACE -+/******************************************************************************* -+** -+** _NeedVirtualMapping -+** -+** Whether setup GPU page table for video node. -+** -+** INPUT: -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** gcuVIDMEM_NODE_PTR Node -+** Pointer to a gcuVIDMEM_NODE union. -+** -+** gceCORE Core -+** Id of current GPU. -+** -+** OUTPUT: -+** gctBOOL * NeedMapping -+** A pointer hold the result whether Node should be mapping. -+*/ -+static gceSTATUS -+_NeedVirtualMapping( -+ IN gckKERNEL Kernel, -+ IN gceCORE Core, -+ IN gcuVIDMEM_NODE_PTR Node, -+ OUT gctBOOL * NeedMapping -+) -+{ -+ gceSTATUS status; -+ gctUINT32 phys; -+ gctUINT32 end; -+ gcePOOL pool; -+ gctUINT32 offset; -+ gctUINT32 baseAddress; -+ gctUINT32 bytes; -+ -+ gcmkHEADER_ARG("Node=0x%X", Node); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_ARGUMENT(Kernel != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Node != gcvNULL); -+ gcmkVERIFY_ARGUMENT(NeedMapping != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Core < gcdMAX_GPU_COUNT); -+ -+ if (Node->Virtual.contiguous) -+ { -+#if gcdENABLE_VG -+ if (Core == gcvCORE_VG) -+ { -+ *NeedMapping = gcvFALSE; -+ } -+ else -+#endif -+ { -+ /* Convert logical address into a physical address. */ -+ gcmkONERROR(gckOS_UserLogicalToPhysical( -+ Kernel->os, Node->Virtual.logical, &phys -+ )); -+ -+ gcmkONERROR(gckOS_GetBaseAddress(Kernel->os, &baseAddress)); -+ -+ gcmkASSERT(phys >= baseAddress); -+ -+ /* Subtract baseAddress to get a GPU address used for programming. */ -+ phys -= baseAddress; -+ -+ /* If part of region is belong to gcvPOOL_VIRTUAL, -+ ** whole region has to be mapped. */ -+ gcmkSAFECASTSIZET(bytes, Node->Virtual.bytes); -+ end = phys + bytes - 1; -+ -+ gcmkONERROR(gckHARDWARE_SplitMemory( -+ Kernel->hardware, end, &pool, &offset -+ )); -+ -+ *NeedMapping = (pool == gcvPOOL_VIRTUAL); -+ } -+ } -+ else -+ { -+ *NeedMapping = gcvTRUE; -+ } -+ -+ gcmkFOOTER_ARG("*NeedMapping=%d", *NeedMapping); -+ return gcvSTATUS_OK; -+ -+OnError: -+ gcmkFOOTER(); -+ return status; -+} -+#endif -+ -+#if gcdPROCESS_ADDRESS_SPACE -+gcsGPU_MAP_PTR -+_FindGPUMap( -+ IN gcsGPU_MAP_PTR Head, -+ IN gctINT ProcessID -+ ) -+{ -+ gcsGPU_MAP_PTR map = Head; -+ -+ while (map) -+ { -+ if (map->pid == ProcessID) -+ { -+ return map; -+ } -+ -+ map = map->next; -+ } -+ -+ return gcvNULL; -+} -+ -+gcsGPU_MAP_PTR -+_CreateGPUMap( -+ IN gckOS Os, -+ IN gcsGPU_MAP_PTR *Head, -+ IN gcsGPU_MAP_PTR *Tail, -+ IN gctINT ProcessID -+ ) -+{ -+ gcsGPU_MAP_PTR gpuMap; -+ gctPOINTER pointer = gcvNULL; -+ -+ gckOS_Allocate(Os, sizeof(gcsGPU_MAP), &pointer); -+ -+ if (pointer == gcvNULL) -+ { -+ return gcvNULL; -+ } -+ -+ gpuMap = pointer; -+ -+ gckOS_ZeroMemory(pointer, sizeof(gcsGPU_MAP)); -+ -+ gpuMap->pid = ProcessID; -+ -+ if (!*Head) -+ { -+ *Head = *Tail = gpuMap; -+ } -+ else -+ { -+ gpuMap->prev = *Tail; -+ (*Tail)->next = gpuMap; -+ *Tail = gpuMap; -+ } -+ -+ return gpuMap; -+} -+ -+void -+_DestroyGPUMap( -+ IN gckOS Os, -+ IN gcsGPU_MAP_PTR *Head, -+ IN gcsGPU_MAP_PTR *Tail, -+ IN gcsGPU_MAP_PTR gpuMap -+ ) -+{ -+ -+ if (gpuMap == *Head) -+ { -+ if ((*Head = gpuMap->next) == gcvNULL) -+ { -+ *Tail = gcvNULL; -+ } -+ } -+ else -+ { -+ gpuMap->prev->next = gpuMap->next; -+ if (gpuMap == *Tail) -+ { -+ *Tail = gpuMap->prev; -+ } -+ else -+ { -+ gpuMap->next->prev = gpuMap->prev; -+ } -+ } -+ -+ gcmkOS_SAFE_FREE(Os, gpuMap); -+} -+#endif -+ -+/******************************************************************************* -+** -+** gckVIDMEM_Lock -+** -+** Lock a video memory node and return its hardware specific address. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** gcuVIDMEM_NODE_PTR Node -+** Pointer to a gcuVIDMEM_NODE union. -+** -+** OUTPUT: -+** -+** gctUINT32 * Address -+** Pointer to a variable that will hold the hardware specific address. -+** -+** gctUINT32 * PhysicalAddress -+** Pointer to a variable that will hold the bus address of a contiguous -+** video node. -+*/ -+gceSTATUS -+gckVIDMEM_Lock( -+ IN gckKERNEL Kernel, -+ IN gckVIDMEM_NODE Node, -+ IN gctBOOL Cacheable, -+ OUT gctUINT32 * Address, -+ OUT gctUINT32 * Gid, -+ OUT gctUINT64 * PhysicalAddress -+ ) -+{ -+ gceSTATUS status; -+ gctBOOL acquired = gcvFALSE; -+ gctBOOL locked = gcvFALSE; -+ gckOS os = gcvNULL; -+#if !gcdPROCESS_ADDRESS_SPACE -+ gctBOOL needMapping = gcvFALSE; -+#endif -+ gctUINT32 baseAddress; -+ gctUINT32 physicalAddress; -+ gcuVIDMEM_NODE_PTR node = Node->node; -+ -+ gcmkHEADER_ARG("Node=0x%x", Node); -+ -+ /* Verify the arguments. */ -+ gcmkVERIFY_ARGUMENT(Address != gcvNULL); -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ -+ /* Extract the gckOS object pointer. */ -+ os = Kernel->os; -+ gcmkVERIFY_OBJECT(os, gcvOBJ_OS); -+ -+ if ((node == gcvNULL) -+ || (node->VidMem.memory == gcvNULL) -+ ) -+ { -+ /* Invalid object. */ -+ gcmkONERROR(gcvSTATUS_INVALID_OBJECT); -+ } -+ -+ /* Grab the mutex. */ -+ gcmkONERROR(gckOS_AcquireMutex(os, Node->mutex, gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ /**************************** Video Memory ********************************/ -+ -+ if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM) -+ { -+ gctUINT32 offset; -+ -+ if (Cacheable == gcvTRUE) -+ { -+ gcmkONERROR(gcvSTATUS_INVALID_REQUEST); -+ } -+ -+ /* Increment the lock count. */ -+ node->VidMem.locked ++; -+ -+ /* Return the physical address of the node. */ -+ gcmkSAFECASTSIZET(offset, node->VidMem.offset); -+ -+ *Address = node->VidMem.memory->baseAddress -+ + offset -+ + node->VidMem.alignment; -+ -+ physicalAddress = *Address; -+ -+ /* Get hardware specific address. */ -+#if gcdENABLE_VG -+ if (Kernel->vg == gcvNULL) -+#endif -+ { -+ if (Kernel->hardware->mmuVersion == 0) -+ { -+ /* Convert physical to GPU address for old mmu. */ -+ gcmkONERROR(gckOS_GetBaseAddress(Kernel->os, &baseAddress)); -+ gcmkASSERT(*Address > baseAddress); -+ *Address -= baseAddress; -+ } -+ } -+ -+ gcmkVERIFY_OK(gckOS_CPUPhysicalToGPUPhysical( -+ Kernel->os, -+ *Address, -+ Address -+ )); -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM, -+ "Locked node 0x%x (%d) @ 0x%08X", -+ node, -+ node->VidMem.locked, -+ *Address); -+ } -+ -+ /*************************** Virtual Memory *******************************/ -+ -+ else -+ { -+ -+ *Gid = node->Virtual.gid; -+ -+#if gcdPAGED_MEMORY_CACHEABLE -+ /* Force video memory cacheable. */ -+ Cacheable = gcvTRUE; -+#endif -+ -+ gcmkONERROR( -+ gckOS_LockPages(os, -+ node->Virtual.physical, -+ node->Virtual.bytes, -+ Cacheable, -+ &node->Virtual.logical, -+ &node->Virtual.pageCount)); -+ -+ gcmkONERROR(gckOS_GetPhysicalAddress( -+ os, -+ node->Virtual.logical, -+ &physicalAddress -+ )); -+ -+#if gcdENABLE_VG -+ node->Virtual.physicalAddress = physicalAddress; -+#endif -+ -+#if !gcdPROCESS_ADDRESS_SPACE -+ /* Increment the lock count. */ -+ if (node->Virtual.lockeds[Kernel->core] ++ == 0) -+ { -+ locked = gcvTRUE; -+ -+ gcmkONERROR(_NeedVirtualMapping(Kernel, Kernel->core, node, &needMapping)); -+ -+ if (needMapping == gcvFALSE) -+ { -+ /* Get hardware specific address. */ -+#if gcdENABLE_VG -+ if (Kernel->vg != gcvNULL) -+ { -+ gcmkONERROR(gckVGHARDWARE_ConvertLogical( -+ Kernel->vg->hardware, -+ node->Virtual.logical, -+ gcvTRUE, -+ &node->Virtual.addresses[Kernel->core])); -+ } -+ else -+#endif -+ { -+ gcmkONERROR(gckHARDWARE_ConvertLogical( -+ Kernel->hardware, -+ node->Virtual.logical, -+ gcvTRUE, -+ &node->Virtual.addresses[Kernel->core])); -+ } -+ } -+ else -+ { -+#if gcdENABLE_VG -+ if (Kernel->vg != gcvNULL) -+ { -+ /* Allocate pages inside the MMU. */ -+ gcmkONERROR( -+ gckVGMMU_AllocatePages(Kernel->vg->mmu, -+ node->Virtual.pageCount, -+ &node->Virtual.pageTables[Kernel->core], -+ &node->Virtual.addresses[Kernel->core])); -+ } -+ else -+#endif -+ { -+ /* Allocate pages inside the MMU. */ -+ gcmkONERROR( -+ gckMMU_AllocatePagesEx(Kernel->mmu, -+ node->Virtual.pageCount, -+ node->Virtual.type, -+ &node->Virtual.pageTables[Kernel->core], -+ &node->Virtual.addresses[Kernel->core])); -+ } -+ -+ node->Virtual.lockKernels[Kernel->core] = Kernel; -+ -+ /* Map the pages. */ -+ gcmkONERROR( -+ gckOS_MapPagesEx(os, -+ Kernel->core, -+ node->Virtual.physical, -+ node->Virtual.pageCount, -+ node->Virtual.addresses[Kernel->core], -+ node->Virtual.pageTables[Kernel->core])); -+ -+#if gcdENABLE_VG -+ if (Kernel->core == gcvCORE_VG) -+ { -+ gcmkONERROR(gckVGMMU_Flush(Kernel->vg->mmu)); -+ } -+ else -+#endif -+ { -+ gcmkONERROR(gckMMU_Flush(Kernel->mmu, node->Virtual.type)); -+ } -+ } -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM, -+ "Mapped virtual node 0x%x to 0x%08X", -+ node, -+ node->Virtual.addresses[Kernel->core]); -+ } -+ -+ /* Return hardware address. */ -+ *Address = node->Virtual.addresses[Kernel->core]; -+#endif -+ } -+ -+ /* Release the mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, Node->mutex)); -+ -+ *PhysicalAddress = (gctUINT64)physicalAddress; -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Address=%08x", *Address); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (locked) -+ { -+ if (node->Virtual.pageTables[Kernel->core] != gcvNULL) -+ { -+#if gcdENABLE_VG -+ if (Kernel->vg != gcvNULL) -+ { -+ /* Free the pages from the MMU. */ -+ gcmkVERIFY_OK( -+ gckVGMMU_FreePages(Kernel->vg->mmu, -+ node->Virtual.pageTables[Kernel->core], -+ node->Virtual.pageCount)); -+ } -+ else -+#endif -+ { -+ /* Free the pages from the MMU. */ -+ gcmkVERIFY_OK( -+ gckMMU_FreePages(Kernel->mmu, -+ node->Virtual.pageTables[Kernel->core], -+ node->Virtual.pageCount)); -+ } -+ node->Virtual.pageTables[Kernel->core] = gcvNULL; -+ node->Virtual.lockKernels[Kernel->core] = gcvNULL; -+ } -+ -+ /* Unlock the pages. */ -+ gcmkVERIFY_OK( -+ gckOS_UnlockPages(os, -+ node->Virtual.physical, -+ node->Virtual.bytes, -+ node->Virtual.logical -+ )); -+ -+ node->Virtual.lockeds[Kernel->core]--; -+ } -+ -+ if (acquired) -+ { -+ /* Release the mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, Node->mutex)); -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckVIDMEM_Unlock -+** -+** Unlock a video memory node. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** gcuVIDMEM_NODE_PTR Node -+** Pointer to a locked gcuVIDMEM_NODE union. -+** -+** gceSURF_TYPE Type -+** Type of surface to unlock. -+** -+** gctBOOL * Asynchroneous -+** Pointer to a variable specifying whether the surface should be -+** unlocked asynchroneously or not. -+** -+** OUTPUT: -+** -+** gctBOOL * Asynchroneous -+** Pointer to a variable receiving the number of bytes used in the -+** command buffer specified by 'Commands'. If gcvNULL, there is no -+** command buffer. -+*/ -+gceSTATUS -+gckVIDMEM_Unlock( -+ IN gckKERNEL Kernel, -+ IN gckVIDMEM_NODE Node, -+ IN gceSURF_TYPE Type, -+ IN OUT gctBOOL * Asynchroneous -+ ) -+{ -+ gceSTATUS status; -+ gckOS os = gcvNULL; -+ gctBOOL acquired = gcvFALSE; -+ gcuVIDMEM_NODE_PTR node = Node->node; -+ -+ gcmkHEADER_ARG("Node=0x%x Type=%d *Asynchroneous=%d", -+ Node, Type, gcmOPT_VALUE(Asynchroneous)); -+ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ -+ /* Get the gckOS object pointer. */ -+ os = Kernel->os; -+ gcmkVERIFY_OBJECT(os, gcvOBJ_OS); -+ -+ /* Verify the arguments. */ -+ if ((node == gcvNULL) -+ || (node->VidMem.memory == gcvNULL) -+ ) -+ { -+ /* Invalid object. */ -+ gcmkONERROR(gcvSTATUS_INVALID_OBJECT); -+ } -+ -+ /* Grab the mutex. */ -+ gcmkONERROR(gckOS_AcquireMutex(os, Node->mutex, gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ /**************************** Video Memory ********************************/ -+ -+ if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM) -+ { -+ if (node->VidMem.locked <= 0) -+ { -+ /* The surface was not locked. */ -+ status = gcvSTATUS_MEMORY_UNLOCKED; -+ goto OnError; -+ } -+ -+ if (Asynchroneous != gcvNULL) -+ { -+ /* Schedule an event to sync with GPU. */ -+ *Asynchroneous = gcvTRUE; -+ } -+ else -+ { -+ /* Decrement the lock count. */ -+ node->VidMem.locked --; -+ } -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM, -+ "Unlocked node 0x%x (%d)", -+ node, -+ node->VidMem.locked); -+ } -+ -+ /*************************** Virtual Memory *******************************/ -+ -+ else -+ { -+ -+ -+ if (Asynchroneous == gcvNULL) -+ { -+#if !gcdPROCESS_ADDRESS_SPACE -+ if (node->Virtual.lockeds[Kernel->core] == 0) -+ { -+ status = gcvSTATUS_MEMORY_UNLOCKED; -+ goto OnError; -+ } -+ -+ /* Decrement lock count. */ -+ -- node->Virtual.lockeds[Kernel->core]; -+ -+ /* See if we can unlock the resources. */ -+ if (node->Virtual.lockeds[Kernel->core] == 0) -+ { -+ /* Free the page table. */ -+ if (node->Virtual.pageTables[Kernel->core] != gcvNULL) -+ { -+#if gcdENABLE_VG -+ if (Kernel->vg != gcvNULL) -+ { -+ gcmkONERROR( -+ gckVGMMU_FreePages(Kernel->vg->mmu, -+ node->Virtual.pageTables[Kernel->core], -+ node->Virtual.pageCount)); -+ } -+ else -+#endif -+ { -+ gcmkONERROR( -+ gckMMU_FreePages(Kernel->mmu, -+ node->Virtual.pageTables[Kernel->core], -+ node->Virtual.pageCount)); -+ } -+ -+ gcmkONERROR(gckOS_UnmapPages( -+ Kernel->os, -+ node->Virtual.pageCount, -+ node->Virtual.addresses[Kernel->core] -+ )); -+ -+ /* Mark page table as freed. */ -+ node->Virtual.pageTables[Kernel->core] = gcvNULL; -+ node->Virtual.lockKernels[Kernel->core] = gcvNULL; -+ } -+ } -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM, -+ "Unmapped virtual node 0x%x from 0x%08X", -+ node, node->Virtual.addresses[Kernel->core]); -+#endif -+ -+ } -+ -+ else -+ { -+ gcmkONERROR( -+ gckOS_UnlockPages(os, -+ node->Virtual.physical, -+ node->Virtual.bytes, -+ node->Virtual.logical)); -+ -+ gcmkTRACE_ZONE(gcvLEVEL_INFO, gcvZONE_VIDMEM, -+ "Scheduled unlock for virtual node 0x%x", -+ node); -+ -+ /* Schedule the surface to be unlocked. */ -+ *Asynchroneous = gcvTRUE; -+ } -+ } -+ -+ /* Release the mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, Node->mutex)); -+ acquired = gcvFALSE; -+ -+ /* Success. */ -+ gcmkFOOTER_ARG("*Asynchroneous=%d", gcmOPT_VALUE(Asynchroneous)); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (acquired) -+ { -+ /* Release the mutex. */ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, Node->mutex)); -+ } -+ -+ /* Return the status. */ -+ gcmkFOOTER(); -+ return status; -+} -+ -+#if gcdPROCESS_ADDRESS_SPACE -+gceSTATUS -+gckVIDMEM_Node_Lock( -+ IN gckKERNEL Kernel, -+ IN gckVIDMEM_NODE Node, -+ OUT gctUINT32 *Address -+ ) -+{ -+ gceSTATUS status; -+ gckOS os; -+ gcuVIDMEM_NODE_PTR node = Node->node; -+ gcsGPU_MAP_PTR gpuMap; -+ gctPHYS_ADDR physical = gcvNULL; -+ gctUINT32 phys = gcvINVALID_ADDRESS; -+ gctUINT32 processID; -+ gcsLOCK_INFO_PTR lockInfo; -+ gctUINT32 pageCount; -+ gckMMU mmu; -+ gctUINT32 i; -+ gctUINT32_PTR pageTableEntry; -+ gctUINT32 offset = 0; -+ gctBOOL acquired = gcvFALSE; -+ -+ gcmkHEADER_ARG("Node = %x", Node); -+ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ gcmkVERIFY_ARGUMENT(Node != gcvNULL); -+ gcmkVERIFY_ARGUMENT(Address != gcvNULL); -+ -+ os = Kernel->os; -+ gcmkVERIFY_OBJECT(os, gcvOBJ_OS); -+ -+ gcmkONERROR(gckOS_GetProcessID(&processID)); -+ -+ gcmkONERROR(gckKERNEL_GetProcessMMU(Kernel, &mmu)); -+ -+ gcmkONERROR(gckOS_AcquireMutex(os, Node->mapMutex, gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ /* Get map information for current process. */ -+ gpuMap = _FindGPUMap(Node->mapHead, processID); -+ -+ if (gpuMap == gcvNULL) -+ { -+ gpuMap = _CreateGPUMap(os, &Node->mapHead, &Node->mapTail, processID); -+ -+ if (gpuMap == gcvNULL) -+ { -+ gcmkONERROR(gcvSTATUS_OUT_OF_MEMORY); -+ } -+ } -+ -+ lockInfo = &gpuMap->lockInfo; -+ -+ if (lockInfo->lockeds[Kernel->core] ++ == 0) -+ { -+ /* Get necessary information. */ -+ if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM) -+ { -+ phys = node->VidMem.memory->baseAddress -+ + node->VidMem.offset -+ + node->VidMem.alignment; -+ -+ /* GPU page table use 4K page. */ -+ pageCount = ((phys + node->VidMem.bytes + 4096 - 1) >> 12) -+ - (phys >> 12); -+ -+ offset = phys & 0xFFF; -+ } -+ else -+ { -+ pageCount = node->Virtual.pageCount; -+ physical = node->Virtual.physical; -+ } -+ -+ /* Allocate pages inside the MMU. */ -+ gcmkONERROR(gckMMU_AllocatePages( -+ mmu, -+ pageCount, -+ &lockInfo->pageTables[Kernel->core], -+ &lockInfo->GPUAddresses[Kernel->core])); -+ -+ /* Record MMU from which pages are allocated. */ -+ lockInfo->lockMmus[Kernel->core] = mmu; -+ -+ pageTableEntry = lockInfo->pageTables[Kernel->core]; -+ -+ /* Fill page table entries. */ -+ if (phys != gcvINVALID_ADDRESS) -+ { -+ gctUINT32 address = lockInfo->GPUAddresses[Kernel->core]; -+ for (i = 0; i < pageCount; i++) -+ { -+ gckMMU_GetPageEntry(mmu, address, &pageTableEntry); -+ gckMMU_SetPage(mmu, phys & 0xFFFFF000, pageTableEntry); -+ phys += 4096; -+ address += 4096; -+ pageTableEntry += 1; -+ } -+ } -+ else -+ { -+ gctUINT32 address = lockInfo->GPUAddresses[Kernel->core]; -+ gcmkASSERT(physical != gcvNULL); -+ gcmkONERROR(gckOS_MapPagesEx(os, -+ Kernel->core, -+ physical, -+ pageCount, -+ address, -+ pageTableEntry)); -+ } -+ -+ gcmkONERROR(gckMMU_Flush(mmu)); -+ } -+ -+ *Address = lockInfo->GPUAddresses[Kernel->core] + offset; -+ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, Node->mapMutex)); -+ acquired = gcvFALSE; -+ -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (acquired) -+ { -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(os, Node->mapMutex)); -+ } -+ -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckVIDMEM_NODE_Unlock( -+ IN gckKERNEL Kernel, -+ IN gckVIDMEM_NODE Node, -+ IN gctUINT32 ProcessID -+ ) -+{ -+ gceSTATUS status; -+ gcsGPU_MAP_PTR gpuMap; -+ gcsLOCK_INFO_PTR lockInfo; -+ gckMMU mmu; -+ gcuVIDMEM_NODE_PTR node; -+ gctUINT32 pageCount; -+ gctBOOL acquired = gcvFALSE; -+ -+ gcmkHEADER_ARG("Kernel=0x%08X, Node = %x, ProcessID=%d", -+ Kernel, Node, ProcessID); -+ -+ gcmkVERIFY_OBJECT(Kernel, gcvOBJ_KERNEL); -+ gcmkVERIFY_ARGUMENT(Node != gcvNULL); -+ -+ gcmkONERROR(gckOS_AcquireMutex(Kernel->os, Node->mapMutex, gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ /* Get map information for current process. */ -+ gpuMap = _FindGPUMap(Node->mapHead, ProcessID); -+ -+ if (gpuMap == gcvNULL) -+ { -+ /* No mapping for this process. */ -+ gcmkONERROR(gcvSTATUS_INVALID_DATA); -+ } -+ -+ lockInfo = &gpuMap->lockInfo; -+ -+ if (--lockInfo->lockeds[Kernel->core] == 0) -+ { -+ node = Node->node; -+ -+ /* Get necessary information. */ -+ if (node->VidMem.memory->object.type == gcvOBJ_VIDMEM) -+ { -+ gctUINT32 phys = node->VidMem.memory->baseAddress -+ + node->VidMem.offset -+ + node->VidMem.alignment; -+ -+ /* GPU page table use 4K page. */ -+ pageCount = ((phys + node->VidMem.bytes + 4096 - 1) >> 12) -+ - (phys >> 12); -+ } -+ else -+ { -+ pageCount = node->Virtual.pageCount; -+ } -+ -+ /* Get MMU which allocates pages. */ -+ mmu = lockInfo->lockMmus[Kernel->core]; -+ -+ /* Free virtual spaces in page table. */ -+ gcmkVERIFY_OK(gckMMU_FreePagesEx( -+ mmu, -+ lockInfo->GPUAddresses[Kernel->core], -+ pageCount -+ )); -+ -+ _DestroyGPUMap(Kernel->os, &Node->mapHead, &Node->mapTail, gpuMap); -+ } -+ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Node->mapMutex)); -+ acquired = gcvFALSE; -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (acquired) -+ { -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, Node->mapMutex)); -+ } -+ -+ gcmkFOOTER(); -+ return status; -+} -+#endif -+ -+/******************************************************************************* -+** -+** gckVIDMEM_HANDLE_Allocate -+** -+** Allocate a handle for a gckVIDMEM_NODE object. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** gckVIDMEM_NODE Node -+** Pointer to a gckVIDMEM_NODE object. -+** -+** OUTPUT: -+** -+** gctUINT32 * Handle -+** Pointer to a variable receiving a handle represent this -+** gckVIDMEM_NODE in userspace. -+*/ -+static gceSTATUS -+gckVIDMEM_HANDLE_Allocate( -+ IN gckKERNEL Kernel, -+ IN gckVIDMEM_NODE Node, -+ OUT gctUINT32 * Handle -+ ) -+{ -+ gceSTATUS status; -+ gctUINT32 processID = 0; -+ gctPOINTER pointer = gcvNULL; -+ gctPOINTER handleDatabase = gcvNULL; -+ gctPOINTER mutex = gcvNULL; -+ gctUINT32 handle = 0; -+ gckVIDMEM_HANDLE handleObject = gcvNULL; -+ gckOS os = Kernel->os; -+ -+ gcmkHEADER_ARG("Kernel=0x%X, Node=0x%X", Kernel, Node); -+ -+ gcmkVERIFY_OBJECT(os, gcvOBJ_OS); -+ -+ /* Allocate a gckVIDMEM_HANDLE object. */ -+ gcmkONERROR(gckOS_Allocate(os, gcmSIZEOF(gcsVIDMEM_HANDLE), &pointer)); -+ -+ gcmkVERIFY_OK(gckOS_ZeroMemory(pointer, gcmSIZEOF(gcsVIDMEM_HANDLE))); -+ -+ handleObject = pointer; -+ -+ gcmkONERROR(gckOS_AtomConstruct(os, &handleObject->reference)); -+ -+ /* Set default reference count to 1. */ -+ gckOS_AtomSet(os, handleObject->reference, 1); -+ -+ gcmkVERIFY_OK(gckOS_GetProcessID(&processID)); -+ -+ gcmkONERROR( -+ gckKERNEL_FindHandleDatbase(Kernel, -+ processID, -+ &handleDatabase, -+ &mutex)); -+ -+ /* Allocate a handle for this object. */ -+ gcmkONERROR( -+ gckKERNEL_AllocateIntegerId(handleDatabase, handleObject, &handle)); -+ -+ handleObject->node = Node; -+ handleObject->handle = handle; -+ -+ *Handle = handle; -+ -+ gcmkFOOTER_ARG("*Handle=%d", *Handle); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (handleObject != gcvNULL) -+ { -+ if (handleObject->reference != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckOS_AtomDestroy(os, handleObject->reference)); -+ } -+ -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, handleObject)); -+ } -+ -+ gcmkFOOTER(); -+ return status; -+} -+ -+static gceSTATUS -+gckVIDMEM_NODE_Reference( -+ IN gckKERNEL Kernel, -+ IN gckVIDMEM_NODE Node -+ ) -+{ -+ gctINT32 oldValue; -+ gcmkHEADER_ARG("Kernel=0x%X Node=0x%X", Kernel, Node); -+ -+ gckOS_AtomIncrement(Kernel->os, Node->reference, &oldValue); -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+gckVIDMEM_HANDLE_Reference( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 ProcessID, -+ IN gctUINT32 Handle -+ ) -+{ -+ gceSTATUS status; -+ gckVIDMEM_HANDLE handleObject = gcvNULL; -+ gctPOINTER database = gcvNULL; -+ gctPOINTER mutex = gcvNULL; -+ gctINT32 oldValue = 0; -+ gctBOOL acquired = gcvFALSE; -+ -+ gcmkHEADER_ARG("Handle=%d ProcessID=%d", Handle, ProcessID); -+ -+ gcmkONERROR( -+ gckKERNEL_FindHandleDatbase(Kernel, ProcessID, &database, &mutex)); -+ -+ gcmkVERIFY_OK(gckOS_AcquireMutex(Kernel->os, mutex, gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ /* Translate handle to gckVIDMEM_HANDLE object. */ -+ gcmkONERROR( -+ gckKERNEL_QueryIntegerId(database, Handle, (gctPOINTER *)&handleObject)); -+ -+ /* Increase the reference count. */ -+ gckOS_AtomIncrement(Kernel->os, handleObject->reference, &oldValue); -+ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex)); -+ acquired = gcvFALSE; -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (acquired) -+ { -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex)); -+ } -+ -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckVIDMEM_HANDLE_Dereference( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 ProcessID, -+ IN gctUINT32 Handle -+ ) -+{ -+ gceSTATUS status; -+ gctPOINTER handleDatabase = gcvNULL; -+ gctPOINTER mutex = gcvNULL; -+ gctINT32 oldValue = 0; -+ gckVIDMEM_HANDLE handleObject = gcvNULL; -+ gctBOOL acquired = gcvFALSE; -+ -+ gcmkHEADER_ARG("Handle=%d ProcessID=%d", Handle, ProcessID); -+ -+ gcmkONERROR( -+ gckKERNEL_FindHandleDatbase(Kernel, -+ ProcessID, -+ &handleDatabase, -+ &mutex)); -+ -+ gcmkVERIFY_OK(gckOS_AcquireMutex(Kernel->os, mutex, gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ /* Translate handle to gckVIDMEM_HANDLE. */ -+ gcmkONERROR( -+ gckKERNEL_QueryIntegerId(handleDatabase, Handle, (gctPOINTER *)&handleObject)); -+ -+ gckOS_AtomDecrement(Kernel->os, handleObject->reference, &oldValue); -+ -+ if (oldValue == 1) -+ { -+ /* Remove handle from database if this is the last reference. */ -+ gcmkVERIFY_OK(gckKERNEL_FreeIntegerId(handleDatabase, Handle)); -+ } -+ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex)); -+ acquired = gcvFALSE; -+ -+ if (oldValue == 1) -+ { -+ gcmkVERIFY_OK(gckOS_AtomDestroy(Kernel->os, handleObject->reference)); -+ gcmkOS_SAFE_FREE(Kernel->os, handleObject); -+ } -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (acquired) -+ { -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex)); -+ } -+ -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckVIDMEM_HANDLE_LookupAndReference( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 Handle, -+ OUT gckVIDMEM_NODE * Node -+ ) -+{ -+ gceSTATUS status; -+ gckVIDMEM_HANDLE handleObject = gcvNULL; -+ gckVIDMEM_NODE node = gcvNULL; -+ gctPOINTER database = gcvNULL; -+ gctPOINTER mutex = gcvNULL; -+ gctUINT32 processID = 0; -+ gctBOOL acquired = gcvFALSE; -+ -+ gcmkHEADER_ARG("Kernel=0x%X Handle=%d", Kernel, Handle); -+ -+ gckOS_GetProcessID(&processID); -+ -+ gcmkONERROR( -+ gckKERNEL_FindHandleDatbase(Kernel, processID, &database, &mutex)); -+ -+ gcmkVERIFY_OK(gckOS_AcquireMutex(Kernel->os, mutex, gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ /* Translate handle to gckVIDMEM_HANDLE object. */ -+ gcmkONERROR( -+ gckKERNEL_QueryIntegerId(database, Handle, (gctPOINTER *)&handleObject)); -+ -+ /* Get gckVIDMEM_NODE object. */ -+ node = handleObject->node; -+ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex)); -+ acquired = gcvFALSE; -+ -+ /* Reference this gckVIDMEM_NODE object. */ -+ gcmkVERIFY_OK(gckVIDMEM_NODE_Reference(Kernel, node)); -+ -+ /* Return result. */ -+ *Node = node; -+ -+ gcmkFOOTER_ARG("*Node=%X", *Node); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (acquired) -+ { -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex)); -+ } -+ -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckVIDMEM_HANDLE_Lookup( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 ProcessID, -+ IN gctUINT32 Handle, -+ OUT gckVIDMEM_NODE * Node -+ ) -+{ -+ gceSTATUS status; -+ gckVIDMEM_HANDLE handleObject = gcvNULL; -+ gckVIDMEM_NODE node = gcvNULL; -+ gctPOINTER database = gcvNULL; -+ gctPOINTER mutex = gcvNULL; -+ gctBOOL acquired = gcvFALSE; -+ -+ gcmkHEADER_ARG("Kernel=0x%X ProcessID=%d Handle=%d", -+ Kernel, ProcessID, Handle); -+ -+ gcmkONERROR( -+ gckKERNEL_FindHandleDatbase(Kernel, ProcessID, &database, &mutex)); -+ -+ gcmkVERIFY_OK(gckOS_AcquireMutex(Kernel->os, mutex, gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ gcmkONERROR( -+ gckKERNEL_QueryIntegerId(database, Handle, (gctPOINTER *)&handleObject)); -+ -+ node = handleObject->node; -+ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex)); -+ acquired = gcvFALSE; -+ -+ *Node = node; -+ -+ gcmkFOOTER_ARG("*Node=%X", *Node); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (acquired) -+ { -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex)); -+ } -+ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckVIDMEM_NODE_Allocate -+** -+** Allocate a gckVIDMEM_NODE object. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** gcuVIDMEM_NODE_PTR Node -+** Pointer to a gcuVIDMEM_NODE union. -+** -+** OUTPUT: -+** -+** gctUINT32 * Handle -+** Pointer to a variable receiving a handle represent this -+** gckVIDMEM_NODE in userspace. -+*/ -+gceSTATUS -+gckVIDMEM_NODE_Allocate( -+ IN gckKERNEL Kernel, -+ IN gcuVIDMEM_NODE_PTR VideoNode, -+ IN gceSURF_TYPE Type, -+ IN gcePOOL Pool, -+ IN gctUINT32 * Handle -+ ) -+{ -+ gceSTATUS status; -+ gckVIDMEM_NODE node = gcvNULL; -+ gctPOINTER pointer = gcvNULL; -+ gctUINT32 handle = 0; -+ gckOS os = Kernel->os; -+ -+ gcmkHEADER_ARG("Kernel=0x%X VideoNode=0x%X", Kernel, VideoNode); -+ -+ /* Construct a node. */ -+ gcmkONERROR(gckOS_Allocate(os, gcmSIZEOF(gcsVIDMEM_NODE), &pointer)); -+ -+ gcmkVERIFY_OK(gckOS_ZeroMemory(pointer, gcmSIZEOF(gcsVIDMEM_NODE))); -+ -+ node = pointer; -+ -+ node->node = VideoNode; -+ node->type = Type; -+ node->pool = Pool; -+ -+#if gcdPROCESS_ADDRESS_SPACE -+ gcmkONERROR(gckOS_CreateMutex(os, &node->mapMutex)); -+#endif -+ -+ gcmkONERROR(gckOS_AtomConstruct(os, &node->reference)); -+ -+ gcmkONERROR(gckOS_CreateMutex(os, &node->mutex)); -+ -+ /* Reference is 1 by default . */ -+ gckVIDMEM_NODE_Reference(Kernel, node); -+ -+ /* Create a handle to represent this node. */ -+ gcmkONERROR(gckVIDMEM_HANDLE_Allocate(Kernel, node, &handle)); -+ -+ *Handle = handle; -+ -+ gcmkFOOTER_ARG("*Handle=%d", *Handle); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (node != gcvNULL) -+ { -+#if gcdPROCESS_ADDRESS_SPACE -+ if (node->mapMutex != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckOS_DeleteMutex(os, node->mapMutex)); -+ } -+#endif -+ -+ if (node->mutex) -+ { -+ gcmkVERIFY_OK(gckOS_DeleteMutex(os, node->mutex)); -+ } -+ -+ if (node->reference != gcvNULL) -+ { -+ gcmkVERIFY_OK(gckOS_AtomDestroy(os, node->reference)); -+ } -+ -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(os, node)); -+ } -+ -+ gcmkFOOTER(); -+ return status; -+} -+ -+gceSTATUS -+gckVIDMEM_NODE_Dereference( -+ IN gckKERNEL Kernel, -+ IN gckVIDMEM_NODE Node -+ ) -+{ -+ gctINT32 oldValue = 0; -+ gctPOINTER database = Kernel->db->nameDatabase; -+ gctPOINTER mutex = Kernel->db->nameDatabaseMutex; -+ -+ gcmkHEADER_ARG("Kernel=0x%X Node=0x%X", Kernel, Node); -+ -+ gcmkVERIFY_OK(gckOS_AcquireMutex(Kernel->os, mutex, gcvINFINITE)); -+ -+ gcmkVERIFY_OK(gckOS_AtomDecrement(Kernel->os, Node->reference, &oldValue)); -+ -+ if (oldValue == 1 && Node->name) -+ { -+ /* Free name if exists. */ -+ gcmkVERIFY_OK(gckKERNEL_FreeIntegerId(database, Node->name)); -+ } -+ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex)); -+ -+ if (oldValue == 1) -+ { -+ /* Free gcuVIDMEM_NODE. */ -+ gcmkVERIFY_OK(gckVIDMEM_Free(Kernel, Node->node)); -+ gcmkVERIFY_OK(gckOS_AtomDestroy(Kernel->os, Node->reference)); -+#if gcdPROCESS_ADDRESS_SPACE -+ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, Node->mapMutex)); -+#endif -+ gcmkVERIFY_OK(gckOS_DeleteMutex(Kernel->os, Node->mutex)); -+ gcmkOS_SAFE_FREE(Kernel->os, Node); -+ } -+ -+ gcmkFOOTER_NO(); -+ return gcvSTATUS_OK; -+} -+ -+/******************************************************************************* -+** -+** gckVIDMEM_NODE_Name -+** -+** Naming a gckVIDMEM_NODE object. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** gctUINT32 Handle -+** Handle to a gckVIDMEM_NODE object. -+** -+** OUTPUT: -+** -+** gctUINT32 * Name -+** Pointer to a variable receiving a name which can be pass to another -+** process. -+*/ -+gceSTATUS -+gckVIDMEM_NODE_Name( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 Handle, -+ IN gctUINT32 * Name -+ ) -+{ -+ gceSTATUS status; -+ gckVIDMEM_NODE node = gcvNULL; -+ gctUINT32 name = 0; -+ gctUINT32 processID = 0; -+ gctPOINTER database = Kernel->db->nameDatabase; -+ gctPOINTER mutex = Kernel->db->nameDatabaseMutex; -+ gctBOOL acquired = gcvFALSE; -+ gctBOOL referenced = gcvFALSE; -+ gcmkHEADER_ARG("Kernel=0x%X Handle=%d", Kernel, Handle); -+ -+ gcmkONERROR(gckOS_GetProcessID(&processID)); -+ -+ gcmkONERROR(gckOS_AcquireMutex(Kernel->os, mutex, gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ gcmkONERROR(gckVIDMEM_HANDLE_LookupAndReference(Kernel, Handle, &node)); -+ referenced = gcvTRUE; -+ -+ if (node->name == 0) -+ { -+ /* Name this node. */ -+ gcmkONERROR(gckKERNEL_AllocateIntegerId(database, node, &name)); -+ node->name = name; -+ } -+ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex)); -+ acquired = gcvFALSE; -+ -+ gcmkVERIFY_OK(gckVIDMEM_NODE_Dereference(Kernel, node)); -+ -+ if(node) -+ { -+ *Name = node->name; -+ } -+ -+ gcmkFOOTER_ARG("*Name=%d", *Name); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (referenced) -+ { -+ gcmkVERIFY_OK(gckVIDMEM_NODE_Dereference(Kernel, node)); -+ } -+ -+ if (acquired) -+ { -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex)); -+ } -+ -+ gcmkFOOTER(); -+ return status; -+} -+ -+/******************************************************************************* -+** -+** gckVIDMEM_NODE_Import -+** -+** Import a gckVIDMEM_NODE object. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** gctUINT32 Name -+** Name of a gckVIDMEM_NODE object. -+** -+** OUTPUT: -+** -+** gctUINT32 * Handle -+** Pointer to a variable receiving a handle represent this -+** gckVIDMEM_NODE in userspace. -+*/ -+gceSTATUS -+gckVIDMEM_NODE_Import( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 Name, -+ IN gctUINT32 * Handle -+ ) -+{ -+ gceSTATUS status; -+ gckVIDMEM_NODE node = gcvNULL; -+ gctPOINTER database = Kernel->db->nameDatabase; -+ gctPOINTER mutex = Kernel->db->nameDatabaseMutex; -+ gctBOOL acquired = gcvFALSE; -+ gctBOOL referenced = gcvFALSE; -+ -+ gcmkHEADER_ARG("Kernel=0x%X Name=%d", Kernel, Name); -+ -+ gcmkONERROR(gckOS_AcquireMutex(Kernel->os, mutex, gcvINFINITE)); -+ acquired = gcvTRUE; -+ -+ /* Lookup in database to get the node. */ -+ gcmkONERROR(gckKERNEL_QueryIntegerId(database, Name, (gctPOINTER *)&node)); -+ -+ /* Reference the node. */ -+ gcmkONERROR(gckVIDMEM_NODE_Reference(Kernel, node)); -+ referenced = gcvTRUE; -+ -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex)); -+ acquired = gcvFALSE; -+ -+ /* Allocate a handle for current process. */ -+ gcmkONERROR(gckVIDMEM_HANDLE_Allocate(Kernel, node, Handle)); -+ -+ gcmkFOOTER_ARG("*Handle=%d", *Handle); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (referenced) -+ { -+ gcmkVERIFY_OK(gckVIDMEM_NODE_Dereference(Kernel, node)); -+ } -+ -+ if (acquired) -+ { -+ gcmkVERIFY_OK(gckOS_ReleaseMutex(Kernel->os, mutex)); -+ } -+ -+ gcmkFOOTER(); -+ return status; -+} -+ -+ -+typedef struct _gcsVIDMEM_NODE_FDPRIVATE -+{ -+ gcsFDPRIVATE base; -+ gckKERNEL kernel; -+ gckVIDMEM_NODE node; -+} -+gcsVIDMEM_NODE_FDPRIVATE; -+ -+ -+static gctINT -+_ReleaseFdPrivate( -+ gcsFDPRIVATE_PTR FdPrivate -+ ) -+{ -+ /* Cast private info. */ -+ gcsVIDMEM_NODE_FDPRIVATE * private = (gcsVIDMEM_NODE_FDPRIVATE *) FdPrivate; -+ -+ gckVIDMEM_NODE_Dereference(private->kernel, private->node); -+ gckOS_Free(private->kernel->os, private); -+ -+ return 0; -+} -+ -+/******************************************************************************* -+** -+** gckVIDMEM_NODE_GetFd -+** -+** Attach a gckVIDMEM_NODE object to a native fd. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** gctUINT32 Handle -+** Handle to a gckVIDMEM_NODE object. -+** -+** OUTPUT: -+** -+** gctUINT32 * Fd -+** Pointer to a variable receiving a native fd from os. -+*/ -+gceSTATUS -+gckVIDMEM_NODE_GetFd( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 Handle, -+ OUT gctINT * Fd -+ ) -+{ -+ gceSTATUS status; -+ gckVIDMEM_NODE node = gcvNULL; -+ gctBOOL referenced = gcvFALSE; -+ gcsVIDMEM_NODE_FDPRIVATE * fdPrivate = gcvNULL; -+ gcmkHEADER_ARG("Kernel=0x%X Handle=%d", Kernel, Handle); -+ -+ /* Query and reference handle. */ -+ gcmkONERROR(gckVIDMEM_HANDLE_LookupAndReference(Kernel, Handle, &node)); -+ referenced = gcvTRUE; -+ -+ /* Allocate memory for private info. */ -+ gcmkONERROR(gckOS_Allocate( -+ Kernel->os, -+ gcmSIZEOF(gcsVIDMEM_NODE_FDPRIVATE), -+ (gctPOINTER *)&fdPrivate -+ )); -+ -+ fdPrivate->base.release = _ReleaseFdPrivate; -+ fdPrivate->kernel = Kernel; -+ fdPrivate->node = node; -+ -+ /* Allocated fd owns a reference. */ -+ gcmkONERROR(gckOS_GetFd("vidmem", &fdPrivate->base, Fd)); -+ -+ gcmkFOOTER_ARG("*Fd=%d", *Fd); -+ return gcvSTATUS_OK; -+ -+OnError: -+ if (referenced) -+ { -+ gcmkVERIFY_OK(gckVIDMEM_NODE_Dereference(Kernel, node)); -+ } -+ -+ if (fdPrivate) -+ { -+ gcmkVERIFY_OK(gcmkOS_SAFE_FREE(Kernel->os, fdPrivate)); -+ } -+ -+ gcmkFOOTER(); -+ return status; -+} -+ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/inc/aqHal.h linux-4.1.13/drivers/gpu/galcore/inc/aqHal.h ---- linux-4.1.13.orig/drivers/gpu/galcore/inc/aqHal.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/inc/aqHal.h 2015-11-30 17:56:13.584137459 +0100 -@@ -0,0 +1 @@ -+#include "HAL/gc_hal.h" -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_base.h linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_base.h ---- linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_base.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_base.h 2015-11-30 17:56:13.588137194 +0100 -@@ -0,0 +1,5538 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+#ifndef __gc_hal_base_h_ -+#define __gc_hal_base_h_ -+ -+#include "gc_hal_enum.h" -+#include "gc_hal_types.h" -+#include "gc_hal_dump.h" -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+/******************************************************************************\ -+****************************** Object Declarations ***************************** -+\******************************************************************************/ -+ -+typedef struct _gckOS * gckOS; -+typedef struct _gcoHAL * gcoHAL; -+typedef struct _gcoOS * gcoOS; -+typedef struct _gco2D * gco2D; -+typedef struct gcsATOM * gcsATOM_PTR; -+ -+#if gcdENABLE_3D -+typedef struct _gco3D * gco3D; -+typedef struct _gcoCL * gcoCL; -+typedef struct _gcsFAST_FLUSH * gcsFAST_FLUSH_PTR; -+#endif -+ -+typedef struct _gcoSURF * gcoSURF; -+typedef struct _gcsSURF_INFO * gcsSURF_INFO_PTR; -+typedef struct _gcsSURF_NODE * gcsSURF_NODE_PTR; -+typedef struct _gcsSURF_FORMAT_INFO * gcsSURF_FORMAT_INFO_PTR; -+typedef struct _gcsPOINT * gcsPOINT_PTR; -+typedef struct _gcsSIZE * gcsSIZE_PTR; -+typedef struct _gcsRECT * gcsRECT_PTR; -+typedef struct _gcsBOUNDARY * gcsBOUNDARY_PTR; -+typedef struct _gcoDUMP * gcoDUMP; -+typedef struct _gcoHARDWARE * gcoHARDWARE; -+typedef union _gcuVIDMEM_NODE * gcuVIDMEM_NODE_PTR; -+typedef struct _gcsVIDMEM_NODE * gckVIDMEM_NODE; -+ -+#if gcdENABLE_VG -+typedef struct _gcoVG * gcoVG; -+typedef struct _gcsCOMPLETION_SIGNAL * gcsCOMPLETION_SIGNAL_PTR; -+typedef struct _gcsCONTEXT_MAP * gcsCONTEXT_MAP_PTR; -+#else -+typedef void * gcoVG; -+#endif -+ -+#if gcdSYNC -+typedef struct _gcoFENCE * gcoFENCE; -+typedef struct _gcsSYNC_CONTEXT * gcsSYNC_CONTEXT_PTR; -+#endif -+ -+#if defined(ANDROID) -+typedef struct _gcoOS_SymbolsList gcoOS_SymbolsList; -+#endif -+ -+/******************************************************************************\ -+******************************* Process local storage ************************* -+\******************************************************************************/ -+ -+typedef struct _gcsPLS * gcsPLS_PTR; -+ -+#if gcdENABLE_3D -+/****************************************************************************** -+** -+** Patch defines which should be moved to dedicate file later -+** -+** !!! ALWAYS ADD new ID in the TAIL, otherwise will break exising TRACE FILE -+*******************************************************************************/ -+typedef enum _gcePATCH_ID -+{ -+ gcvPATCH_NOTINIT = -1, -+ gcvPATCH_INVALID = 0, -+ -+#if gcdDEBUG_OPTION -+ gcvPATCH_DEBUG, -+#endif -+ -+ gcvPATCH_GTFES30, -+ gcvPATCH_CTGL11, -+ gcvPATCH_CTGL20, -+ gcvPATCH_GLBM11, -+ gcvPATCH_GLBM21, -+ gcvPATCH_GLBM25, -+ gcvPATCH_GLBM27, -+ gcvPATCH_GLBMGUI, -+ gcvPATCH_GFXBENCH, -+ gcvPATCH_ANTUTU, /* Antutu 3.x */ -+ gcvPATCH_ANTUTU4X, /* Antutu 4.x */ -+ gcvPATCH_QUADRANT, -+ gcvPATCH_GPUBENCH, -+ gcvPATCH_DUOKAN, -+ gcvPATCH_GLOFTSXHM, -+ gcvPATCH_XRUNNER, -+ gcvPATCH_BUSPARKING3D, -+ gcvPATCH_SIEGECRAFT, -+ gcvPATCH_PREMIUM, -+ gcvPATCH_RACEILLEGAL, -+ gcvPATCH_MEGARUN, -+ gcvPATCH_BMGUI, -+ gcvPATCH_NENAMARK, -+ gcvPATCH_NENAMARK2, -+ gcvPATCH_FISHNOODLE, -+ gcvPATCH_MM06, -+ gcvPATCH_MM07, -+ gcvPATCH_BM21, -+ gcvPATCH_SMARTBENCH, -+ gcvPATCH_JPCT, -+ gcvPATCH_NEOCORE, -+ gcvPATCH_RTESTVA, -+ gcvPATCH_NBA2013, -+ gcvPATCH_BARDTALE, -+ gcvPATCH_F18, -+ gcvPATCH_CARPARK, -+ gcvPATCH_CARCHALLENGE, -+ gcvPATCH_HEROESCALL, -+ gcvPATCH_GLOFTF3HM, -+ gcvPATCH_CRAZYRACING, -+ gcvPATCH_FIREFOX, -+ gcvPATCH_CHROME, -+ gcvPATCH_MONOPOLY, -+ gcvPATCH_SNOWCOLD, -+ gcvPATCH_BM3, -+ gcvPATCH_BASEMARKX, -+ gcvPATCH_DEQP, -+ gcvPATCH_SF4, -+ gcePATCH_MGOHEAVEN2, -+ gcePATCH_SILIBILI, -+ gcePATCH_ELEMENTSDEF, -+ gcePATCH_GLOFTKRHM, -+ gcvPATCH_OCLCTS, -+ gcvPATCH_A8HP, -+ gcvPATCH_A8CN, -+ gcvPATCH_WISTONESG, -+ gcvPATCH_SPEEDRACE, -+ gcvPATCH_FSBHAWAIIF, -+ gcvPATCH_AIRNAVY, -+ gcvPATCH_F18NEW, -+ gcvPATCH_CKZOMBIES2, -+ gcvPATCH_EADGKEEPER, -+ gcvPATCH_BASEMARK2V2, -+ gcvPATCH_RIPTIDEGP2, -+ gcvPATCH_OESCTS, -+ gcvPATCH_GANGSTAR, -+ gcvPATCH_WHRKYZIXOVAN, -+ gcvPATCH_NAMESGAS, -+ gcvPATCH_AFTERBURNER, -+ gcvPATCH_UIMARK, -+ gcvPATCH_FM_OES_PLAYER, -+ gcvPATCH_SUMSUNG_BENCH, -+ gcvPATCH_ROCKSTAR_MAXPAYNE, -+ gcvPATCH_TITANPACKING, -+ gcvPATCH_BASEMARKOSIICN, -+ gcvPATCH_FRUITNINJA, -+#if defined(ANDROID) -+ gcePATCH_ANDROID_CTS_MEDIA_PRESENTATIONTIME, -+#endif -+ gcvPATCH_ANDROID_COMPOSITOR, -+ gcvPATCH_CTS_TEXTUREVIEW, -+ gcvPATCH_WATER2_CHUKONG, -+ -+ gcvPATCH_COUNT -+} gcePATCH_ID; -+#endif /* gcdENABLE_3D */ -+ -+typedef void (* gctPLS_DESTRUCTOR) ( -+ gcsPLS_PTR -+ ); -+ -+typedef struct _gcsPLS -+{ -+ /* Global objects. */ -+ gcoOS os; -+ gcoHAL hal; -+ -+ /* Internal memory pool. */ -+ gctSIZE_T internalSize; -+ gctPHYS_ADDR internalPhysical; -+ gctPOINTER internalLogical; -+ -+ /* External memory pool. */ -+ gctSIZE_T externalSize; -+ gctPHYS_ADDR externalPhysical; -+ gctPOINTER externalLogical; -+ -+ /* Contiguous memory pool. */ -+ gctSIZE_T contiguousSize; -+ gctPHYS_ADDR contiguousPhysical; -+ gctPOINTER contiguousLogical; -+ -+ /* EGL-specific process-wide objects. */ -+ gctPOINTER eglDisplayInfo; -+ gctPOINTER eglSurfaceInfo; -+ gceSURF_FORMAT eglConfigFormat; -+ -+ /* PLS reference count */ -+ gcsATOM_PTR reference; -+ -+ /* PorcessID of the constrcutor process */ -+ gctUINT32 processID; -+ -+ /* ThreadID of the constrcutor process. */ -+ gctSIZE_T threadID; -+ /* Flag for calling module destructor. */ -+ gctBOOL exiting; -+ -+ gctBOOL bNeedSupportNP2Texture; -+ -+ gctPLS_DESTRUCTOR destructor; -+ /* Mutex to guard PLS access. currently it's for EGL. -+ ** We can use this mutex for every PLS access. -+ */ -+ gctPOINTER accessLock; -+#if gcdENABLE_3D -+ /* Global patchID to overwrite the detection */ -+ gcePATCH_ID patchID; -+#endif -+} -+gcsPLS; -+ -+extern gcsPLS gcPLS; -+ -+#if gcdENABLE_3D -+#define gcPLS_INITIALIZER \ -+{ \ -+ gcvNULL, /* gcoOS object. */ \ -+ gcvNULL, /* gcoHAL object. */ \ -+ 0, /* internalSize */ \ -+ gcvNULL, /* internalPhysical */ \ -+ gcvNULL, /* internalLogical */ \ -+ 0, /* externalSize */ \ -+ gcvNULL, /* externalPhysical */ \ -+ gcvNULL, /* externalLogical */ \ -+ 0, /* contiguousSize */ \ -+ gcvNULL, /* contiguousPhysical */ \ -+ gcvNULL, /* contiguousLogical */ \ -+ gcvNULL, /* eglDisplayInfo */ \ -+ gcvNULL, /* eglSurfaceInfo */ \ -+ gcvSURF_A8R8G8B8,/* eglConfigFormat */ \ -+ gcvNULL, /* reference */ \ -+ 0, /* processID */ \ -+ 0, /* threadID */ \ -+ gcvFALSE, /* exiting */ \ -+ gcvFALSE, /* Special flag for NP2 texture. */ \ -+ gcvNULL, /* destructor */ \ -+ gcvNULL, /* accessLock */ \ -+ gcvPATCH_NOTINIT,/* global patchID */ \ -+} -+#else -+#define gcPLS_INITIALIZER \ -+{ \ -+ gcvNULL, /* gcoOS object. */ \ -+ gcvNULL, /* gcoHAL object. */ \ -+ 0, /* internalSize */ \ -+ gcvNULL, /* internalPhysical */ \ -+ gcvNULL, /* internalLogical */ \ -+ 0, /* externalSize */ \ -+ gcvNULL, /* externalPhysical */ \ -+ gcvNULL, /* externalLogical */ \ -+ 0, /* contiguousSize */ \ -+ gcvNULL, /* contiguousPhysical */ \ -+ gcvNULL, /* contiguousLogical */ \ -+ gcvNULL, /* eglDisplayInfo */ \ -+ gcvNULL, /* eglSurfaceInfo */ \ -+ gcvSURF_A8R8G8B8,/* eglConfigFormat */ \ -+ gcvNULL, /* reference */ \ -+ 0, /* processID */ \ -+ 0, /* threadID */ \ -+ gcvFALSE, /* exiting */ \ -+ gcvFALSE, /* Special flag for NP2 texture. */ \ -+ gcvNULL, /* destructor */ \ -+ gcvNULL, /* accessLock */ \ -+} -+#endif -+ -+/******************************************************************************\ -+******************************* Thread local storage ************************* -+\******************************************************************************/ -+ -+typedef struct _gcsTLS * gcsTLS_PTR; -+ -+typedef void (* gctTLS_DESTRUCTOR) ( -+ gcsTLS_PTR -+ ); -+ -+typedef struct _gcsTLS -+{ -+ gceHARDWARE_TYPE currentType; -+ -+ /* Current 3D hardwre of this thread */ -+ gcoHARDWARE currentHardware; -+ -+ /* Default 3D hardware of this thread */ -+ gcoHARDWARE defaultHardware; -+ -+ /* Only for separated 3D and 2D */ -+ gcoHARDWARE hardware2D; -+#if gcdENABLE_VG -+ gcoVGHARDWARE vg; -+ gcoVG engineVG; -+#endif /* gcdENABLE_VG */ -+#if gcdENABLE_3D -+ gco3D engine3D; -+#endif -+#if gcdENABLE_2D -+ gco2D engine2D; -+#endif -+ -+ /*thread data */ -+ gctPOINTER context; -+ /* ES(including es1 and es2) client driver context which is current state */ -+ gctPOINTER esClientCtx; -+ gctTLS_DESTRUCTOR destructor; -+ -+ gctBOOL copied; -+ -+ /* libGAL.so handle */ -+ gctHANDLE handle; -+ -+ /* If true, do not releas 2d engine and hardware in hal layer */ -+ gctBOOL release2DUpper; -+} -+gcsTLS; -+ -+/******************************************************************************\ -+********************************* Enumerations ********************************* -+\******************************************************************************/ -+ -+typedef enum _gcePLS_VALUE -+{ -+ gcePLS_VALUE_EGL_DISPLAY_INFO, -+ gcePLS_VALUE_EGL_SURFACE_INFO, -+ gcePLS_VALUE_EGL_CONFIG_FORMAT_INFO, -+ gcePLS_VALUE_EGL_DESTRUCTOR_INFO, -+} -+gcePLS_VALUE; -+ -+/* Video memory pool type. */ -+typedef enum _gcePOOL -+{ -+ gcvPOOL_UNKNOWN = 0, -+ gcvPOOL_DEFAULT, -+ gcvPOOL_LOCAL, -+ gcvPOOL_LOCAL_INTERNAL, -+ gcvPOOL_LOCAL_EXTERNAL, -+ gcvPOOL_UNIFIED, -+ gcvPOOL_SYSTEM, -+ gcvPOOL_VIRTUAL, -+ gcvPOOL_USER, -+ gcvPOOL_CONTIGUOUS, -+ -+ gcvPOOL_NUMBER_OF_POOLS -+} -+gcePOOL; -+ -+#if gcdENABLE_3D -+/* Blending functions. */ -+typedef enum _gceBLEND_FUNCTION -+{ -+ gcvBLEND_ZERO, -+ gcvBLEND_ONE, -+ gcvBLEND_SOURCE_COLOR, -+ gcvBLEND_INV_SOURCE_COLOR, -+ gcvBLEND_SOURCE_ALPHA, -+ gcvBLEND_INV_SOURCE_ALPHA, -+ gcvBLEND_TARGET_COLOR, -+ gcvBLEND_INV_TARGET_COLOR, -+ gcvBLEND_TARGET_ALPHA, -+ gcvBLEND_INV_TARGET_ALPHA, -+ gcvBLEND_SOURCE_ALPHA_SATURATE, -+ gcvBLEND_CONST_COLOR, -+ gcvBLEND_INV_CONST_COLOR, -+ gcvBLEND_CONST_ALPHA, -+ gcvBLEND_INV_CONST_ALPHA, -+} -+gceBLEND_FUNCTION; -+ -+/* Blending modes. */ -+typedef enum _gceBLEND_MODE -+{ -+ gcvBLEND_ADD, -+ gcvBLEND_SUBTRACT, -+ gcvBLEND_REVERSE_SUBTRACT, -+ gcvBLEND_MIN, -+ gcvBLEND_MAX, -+} -+gceBLEND_MODE; -+ -+/* Depth modes. */ -+typedef enum _gceDEPTH_MODE -+{ -+ gcvDEPTH_NONE, -+ gcvDEPTH_Z, -+ gcvDEPTH_W, -+} -+gceDEPTH_MODE; -+#endif /* gcdENABLE_3D */ -+ -+#if (gcdENABLE_3D || gcdENABLE_VG) -+/* API flags. */ -+typedef enum _gceAPI -+{ -+ gcvAPI_D3D = 1, -+ gcvAPI_OPENGL_ES11, -+ gcvAPI_OPENGL_ES20, -+ gcvAPI_OPENGL_ES30, -+ gcvAPI_OPENGL, -+ gcvAPI_OPENVG, -+ gcvAPI_OPENCL, -+} -+gceAPI; -+#endif -+ -+ -+typedef enum _gceWHERE -+{ -+ gcvWHERE_COMMAND, -+ gcvWHERE_RASTER, -+ gcvWHERE_PIXEL, -+} -+gceWHERE; -+ -+typedef enum _gceHOW -+{ -+ gcvHOW_SEMAPHORE = 0x1, -+ gcvHOW_STALL = 0x2, -+ gcvHOW_SEMAPHORE_STALL = 0x3, -+} -+gceHOW; -+ -+typedef enum _gceSignalHandlerType -+{ -+ gcvHANDLE_SIGFPE_WHEN_SIGNAL_CODE_IS_0 = 0x1, -+} -+gceSignalHandlerType; -+ -+/* gcsHAL_Limits*/ -+typedef struct _gcsHAL_LIMITS -+{ -+ /* chip info */ -+ gceCHIPMODEL chipModel; -+ gctUINT32 chipRevision; -+ gctUINT32 featureCount; -+ gctUINT32 *chipFeatures; -+ -+ /* target caps */ -+ gctUINT32 maxWidth; -+ gctUINT32 maxHeight; -+ gctUINT32 multiTargetCount; -+ gctUINT32 maxSamples; -+ -+}gcsHAL_LIMITS; -+ -+/******************************************************************************\ -+*********** Generic Memory Allocation Optimization Using Containers ************ -+\******************************************************************************/ -+ -+/* Generic container definition. */ -+typedef struct _gcsCONTAINER_LINK * gcsCONTAINER_LINK_PTR; -+typedef struct _gcsCONTAINER_LINK -+{ -+ /* Points to the next container. */ -+ gcsCONTAINER_LINK_PTR next; -+} -+gcsCONTAINER_LINK; -+ -+typedef struct _gcsCONTAINER_RECORD * gcsCONTAINER_RECORD_PTR; -+typedef struct _gcsCONTAINER_RECORD -+{ -+ gcsCONTAINER_RECORD_PTR prev; -+ gcsCONTAINER_RECORD_PTR next; -+} -+gcsCONTAINER_RECORD; -+ -+typedef struct _gcsCONTAINER * gcsCONTAINER_PTR; -+typedef struct _gcsCONTAINER -+{ -+ gctUINT containerSize; -+ gctUINT recordSize; -+ gctUINT recordCount; -+ gcsCONTAINER_LINK_PTR containers; -+ gcsCONTAINER_RECORD freeList; -+ gcsCONTAINER_RECORD allocList; -+} -+gcsCONTAINER; -+ -+gceSTATUS -+gcsCONTAINER_Construct( -+ IN gcsCONTAINER_PTR Container, -+ gctUINT RecordsPerContainer, -+ gctUINT RecordSize -+ ); -+ -+gceSTATUS -+gcsCONTAINER_Destroy( -+ IN gcsCONTAINER_PTR Container -+ ); -+ -+gceSTATUS -+gcsCONTAINER_AllocateRecord( -+ IN gcsCONTAINER_PTR Container, -+ OUT gctPOINTER * Record -+ ); -+ -+gceSTATUS -+gcsCONTAINER_FreeRecord( -+ IN gcsCONTAINER_PTR Container, -+ IN gctPOINTER Record -+ ); -+ -+gceSTATUS -+gcsCONTAINER_FreeAll( -+ IN gcsCONTAINER_PTR Container -+ ); -+ -+/******************************************************************************\ -+********************************* gcoHAL Object ********************************* -+\******************************************************************************/ -+ -+/* Construct a new gcoHAL object. */ -+gceSTATUS -+gcoHAL_ConstructEx( -+ IN gctPOINTER Context, -+ IN gcoOS Os, -+ OUT gcoHAL * Hal -+ ); -+ -+/* Destroy an gcoHAL object. */ -+gceSTATUS -+gcoHAL_DestroyEx( -+ IN gcoHAL Hal -+ ); -+ -+/* Empty function for compatibility. */ -+gceSTATUS -+gcoHAL_Construct( -+ IN gctPOINTER Context, -+ IN gcoOS Os, -+ OUT gcoHAL * Hal -+ ); -+ -+/* Empty function for compatibility. */ -+gceSTATUS -+gcoHAL_Destroy( -+ IN gcoHAL Hal -+ ); -+ -+/* Get HAL options */ -+gceSTATUS -+gcoHAL_GetOption( -+ IN gcoHAL Hal, -+ IN gceOPTION Option -+ ); -+ -+gceSTATUS -+gcoHAL_FrameInfoOps( -+ IN gcoHAL Hal, -+ IN gceFRAMEINFO FrameInfo, -+ IN gceFRAMEINFO_OP Op, -+ IN OUT gctUINT * Val -+ ); -+ -+ -+gceSTATUS -+gcoHAL_GetHardware( -+ IN gcoHAL Hal, -+ OUT gcoHARDWARE* Hw -+ ); -+ -+#if gcdENABLE_2D -+/* Get pointer to gco2D object. */ -+gceSTATUS -+gcoHAL_Get2DEngine( -+ IN gcoHAL Hal, -+ OUT gco2D * Engine -+ ); -+#endif -+ -+#if gcdENABLE_3D -+gceSTATUS -+gcoHAL_GetSpecialHintData( -+ IN gcoHAL Hal, -+ OUT gctINT * Hint -+ ); -+/* -+** Deprecated(Don't use it), keep it here for external library(libgcu.so) -+*/ -+gceSTATUS -+gcoHAL_Get3DEngine( -+ IN gcoHAL Hal, -+ OUT gco3D * Engine -+ ); -+#endif /* gcdEANBLE_3D */ -+ -+ -+gceSTATUS -+gcoHAL_GetProductName( -+ IN gcoHAL Hal, -+ OUT gctSTRING *ProductName -+ ); -+ -+gceSTATUS -+gcoHAL_SetFscaleValue( -+ IN gctUINT FscaleValue -+ ); -+ -+gceSTATUS -+gcoHAL_GetFscaleValue( -+ OUT gctUINT * FscaleValue, -+ OUT gctUINT * MinFscaleValue, -+ OUT gctUINT * MaxFscaleValue -+ ); -+ -+gceSTATUS -+gcoHAL_SetBltNP2Texture( -+ gctBOOL enable -+ ); -+ -+gceSTATUS -+gcoHAL_NameVideoMemory( -+ IN gctUINT32 Handle, -+ OUT gctUINT32 * Name -+ ); -+ -+gceSTATUS -+gcoHAL_ImportVideoMemory( -+ IN gctUINT32 Name, -+ OUT gctUINT32 * Handle -+ ); -+ -+gceSTATUS -+gcoHAL_GetVideoMemoryFd( -+ IN gctUINT32 Handle, -+ OUT gctINT * Fd -+ ); -+ -+/* Verify whether the specified feature is available in hardware. */ -+gceSTATUS -+gcoHAL_IsFeatureAvailable( -+ IN gcoHAL Hal, -+ IN gceFEATURE Feature -+ ); -+ -+gceSTATUS -+gcoHAL_IsSwwaNeeded( -+ IN gcoHAL Hal, -+ IN gceSWWA Swwa -+ ); -+ -+gceSTATUS -+gcoHAL_IsFeatureAvailable1( -+ IN gcoHAL Hal, -+ IN gceFEATURE Feature -+ ); -+ -+/* Query the identity of the hardware. */ -+gceSTATUS -+gcoHAL_QueryChipIdentity( -+ IN gcoHAL Hal, -+ OUT gceCHIPMODEL* ChipModel, -+ OUT gctUINT32* ChipRevision, -+ OUT gctUINT32* ChipFeatures, -+ OUT gctUINT32* ChipMinorFeatures -+ ); -+ -+/* Query the minor features of the hardware. */ -+gceSTATUS gcoHAL_QueryChipMinorFeatures( -+ IN gcoHAL Hal, -+ OUT gctUINT32* NumFeatures, -+ OUT gctUINT32* ChipMinorFeatures -+ ); -+ -+gctINT32 -+gcoOS_EndRecordAllocation(void); -+void -+gcoOS_RecordAllocation(void); -+void -+gcoOS_AddRecordAllocation(gctSIZE_T Size); -+ -+/* Query the amount of video memory. */ -+gceSTATUS -+gcoHAL_QueryVideoMemory( -+ IN gcoHAL Hal, -+ OUT gctPHYS_ADDR * InternalAddress, -+ OUT gctSIZE_T * InternalSize, -+ OUT gctPHYS_ADDR * ExternalAddress, -+ OUT gctSIZE_T * ExternalSize, -+ OUT gctPHYS_ADDR * ContiguousAddress, -+ OUT gctSIZE_T * ContiguousSize -+ ); -+ -+/* Map video memory. */ -+gceSTATUS -+gcoHAL_MapMemory( -+ IN gcoHAL Hal, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T NumberOfBytes, -+ OUT gctPOINTER * Logical -+ ); -+ -+/* Unmap video memory. */ -+gceSTATUS -+gcoHAL_UnmapMemory( -+ IN gcoHAL Hal, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T NumberOfBytes, -+ IN gctPOINTER Logical -+ ); -+ -+/* Schedule an unmap of a buffer mapped through its physical address. */ -+gceSTATUS -+gcoHAL_ScheduleUnmapMemory( -+ IN gcoHAL Hal, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T NumberOfBytes, -+ IN gctPOINTER Logical -+ ); -+ -+/* Allocate video memory. */ -+gceSTATUS -+gcoOS_AllocateVideoMemory( -+ IN gcoOS Os, -+ IN gctBOOL InUserSpace, -+ IN gctBOOL InCacheable, -+ IN OUT gctSIZE_T * Bytes, -+ OUT gctUINT32 * Physical, -+ OUT gctPOINTER * Logical, -+ OUT gctPOINTER * Handle -+ ); -+ -+/* Free video memory. */ -+gceSTATUS -+gcoOS_FreeVideoMemory( -+ IN gcoOS Os, -+ IN gctPOINTER Handle -+ ); -+ -+/* Lock video memory. */ -+gceSTATUS -+gcoOS_LockVideoMemory( -+ IN gcoOS Os, -+ IN gctPOINTER Handle, -+ IN gctBOOL InUserSpace, -+ IN gctBOOL InCacheable, -+ OUT gctUINT32 * Physical, -+ OUT gctPOINTER * Logical -+ ); -+ -+/* Map user memory. */ -+gceSTATUS -+gcoHAL_MapUserMemory( -+ IN gctPOINTER Logical, -+ IN gctUINT32 Physical, -+ IN gctSIZE_T Size, -+ OUT gctPOINTER * Info, -+ OUT gctUINT32_PTR GPUAddress -+ ); -+ -+/* Unmap user memory. */ -+gceSTATUS -+gcoHAL_UnmapUserMemory( -+ IN gctPOINTER Logical, -+ IN gctSIZE_T Size, -+ IN gctPOINTER Info, -+ IN gctUINT32 GPUAddress -+ ); -+ -+/* Schedule an unmap of a user buffer using event mechanism. */ -+gceSTATUS -+gcoHAL_ScheduleUnmapUserMemory( -+ IN gcoHAL Hal, -+ IN gctPOINTER Info, -+ IN gctSIZE_T Size, -+ IN gctUINT32 Address, -+ IN gctPOINTER Memory -+ ); -+ -+/* Commit the current command buffer. */ -+gceSTATUS -+gcoHAL_Commit( -+ IN gcoHAL Hal, -+ IN gctBOOL Stall -+ ); -+ -+#if gcdENABLE_3D -+/* Sencd fence command. */ -+gceSTATUS -+gcoHAL_SendFence( -+ IN gcoHAL Hal -+ ); -+#endif /* gcdENABLE_3D */ -+ -+/* Query the tile capabilities. */ -+gceSTATUS -+gcoHAL_QueryTiled( -+ IN gcoHAL Hal, -+ OUT gctINT32 * TileWidth2D, -+ OUT gctINT32 * TileHeight2D, -+ OUT gctINT32 * TileWidth3D, -+ OUT gctINT32 * TileHeight3D -+ ); -+ -+gceSTATUS -+gcoHAL_Compact( -+ IN gcoHAL Hal -+ ); -+ -+#if VIVANTE_PROFILER -+gceSTATUS -+gcoHAL_ProfileStart( -+ IN gcoHAL Hal -+ ); -+ -+gceSTATUS -+gcoHAL_ProfileEnd( -+ IN gcoHAL Hal, -+ IN gctCONST_STRING Title -+ ); -+#endif -+ -+/* Power Management */ -+gceSTATUS -+gcoHAL_SetPowerManagementState( -+ IN gcoHAL Hal, -+ IN gceCHIPPOWERSTATE State -+ ); -+ -+gceSTATUS -+gcoHAL_QueryPowerManagementState( -+ IN gcoHAL Hal, -+ OUT gceCHIPPOWERSTATE *State -+ ); -+ -+/* Set the filter type for filter blit. */ -+gceSTATUS -+gcoHAL_SetFilterType( -+ IN gcoHAL Hal, -+ IN gceFILTER_TYPE FilterType -+ ); -+ -+gceSTATUS -+gcoHAL_GetDump( -+ IN gcoHAL Hal, -+ OUT gcoDUMP * Dump -+ ); -+ -+#if gcdENABLE_3D -+gceSTATUS -+gcoHAL_SetPatchID( -+ IN gcoHAL Hal, -+ IN gcePATCH_ID PatchID -+ ); -+ -+/* Get Patch ID based on process name */ -+gceSTATUS -+gcoHAL_GetPatchID( -+ IN gcoHAL Hal, -+ OUT gcePATCH_ID * PatchID -+ ); -+ -+gceSTATUS -+gcoHAL_SetGlobalPatchID( -+ IN gcoHAL Hal, -+ IN gcePATCH_ID PatchID -+ ); -+#endif /* gcdENABLE_3D */ -+/* Call the kernel HAL layer. */ -+gceSTATUS -+gcoHAL_Call( -+ IN gcoHAL Hal, -+ IN OUT gcsHAL_INTERFACE_PTR Interface -+ ); -+ -+/* Schedule an event. */ -+gceSTATUS -+gcoHAL_ScheduleEvent( -+ IN gcoHAL Hal, -+ IN OUT gcsHAL_INTERFACE_PTR Interface -+ ); -+ -+/* Destroy a surface. */ -+gceSTATUS -+gcoHAL_DestroySurface( -+ IN gcoHAL Hal, -+ IN gcoSURF Surface -+ ); -+ -+/* Request a start/stop timestamp. */ -+gceSTATUS -+gcoHAL_SetTimer( -+ IN gcoHAL Hal, -+ IN gctUINT32 Index, -+ IN gctBOOL Start -+ ); -+ -+/* Get Time delta from a Timer in microseconds. */ -+gceSTATUS -+gcoHAL_GetTimerTime( -+ IN gcoHAL Hal, -+ IN gctUINT32 Timer, -+ OUT gctINT32_PTR TimeDelta -+ ); -+ -+/* set timeout value. */ -+gceSTATUS -+gcoHAL_SetTimeOut( -+ IN gcoHAL Hal, -+ IN gctUINT32 timeOut -+ ); -+ -+gceSTATUS -+gcoHAL_SetHardwareType( -+ IN gcoHAL Hal, -+ IN gceHARDWARE_TYPE HardwardType -+ ); -+ -+gceSTATUS -+gcoHAL_GetHardwareType( -+ IN gcoHAL Hal, -+ OUT gceHARDWARE_TYPE * HardwardType -+ ); -+ -+gceSTATUS -+gcoHAL_QueryChipCount( -+ IN gcoHAL Hal, -+ OUT gctINT32 * Count -+ ); -+ -+gceSTATUS -+gcoHAL_Query3DCoreCount( -+ IN gcoHAL Hal, -+ OUT gctUINT32 *Count -+ ); -+ -+gceSTATUS -+gcoHAL_QuerySeparated2D( -+ IN gcoHAL Hal -+ ); -+ -+gceSTATUS -+gcoHAL_Is3DAvailable( -+ IN gcoHAL Hal -+ ); -+ -+/* Get pointer to gcoVG object. */ -+gceSTATUS -+gcoHAL_GetVGEngine( -+ IN gcoHAL Hal, -+ OUT gcoVG * Engine -+ ); -+ -+gceSTATUS -+gcoHAL_QueryChipLimits( -+ IN gcoHAL Hal, -+ IN gctINT32 Chip, -+ IN gctINT32 Mask, -+ OUT gcsHAL_LIMITS *Limits); -+ -+gceSTATUS -+gcoHAL_QueryChipFeature( -+ IN gcoHAL Hal, -+ IN gctINT32 Chip, -+ IN gctINT32 Mask, -+ IN gceFEATURE Feature); -+ -+/*----------------------------------------------------------------------------*/ -+/*----- Shared Buffer --------------------------------------------------------*/ -+ -+/* Create shared buffer. */ -+gceSTATUS -+gcoHAL_CreateShBuffer( -+ IN gctUINT32 Size, -+ OUT gctSHBUF * ShBuf -+ ); -+ -+/* Destroy shared buffer. */ -+gceSTATUS -+gcoHAL_DestroyShBuffer( -+ IN gctSHBUF ShBuf -+ ); -+ -+/* Map shared buffer to current process. */ -+gceSTATUS -+gcoHAL_MapShBuffer( -+ IN gctSHBUF ShBuf -+ ); -+ -+/* Write user data to shared buffer. */ -+gceSTATUS -+gcoHAL_WriteShBuffer( -+ IN gctSHBUF ShBuf, -+ IN gctCONST_POINTER Data, -+ IN gctUINT32 ByteCount -+ ); -+ -+/* Read user data from shared buffer. */ -+gceSTATUS -+gcoHAL_ReadShBuffer( -+ IN gctSHBUF ShBuf, -+ IN gctPOINTER Data, -+ IN gctUINT32 BytesCount, -+ OUT gctUINT32 * BytesRead -+ ); -+ -+/* Config power management to be enabled or disabled. */ -+gceSTATUS -+gcoHAL_ConfigPowerManagement( -+ IN gctBOOL Enable -+ ); -+ -+#if gcdENABLE_3D || gcdENABLE_VG -+/* Query the target capabilities. */ -+gceSTATUS -+gcoHAL_QueryTargetCaps( -+ IN gcoHAL Hal, -+ OUT gctUINT * MaxWidth, -+ OUT gctUINT * MaxHeight, -+ OUT gctUINT * MultiTargetCount, -+ OUT gctUINT * MaxSamples -+ ); -+#endif -+ -+/******************************************************************************\ -+********************************** gcoOS Object ********************************* -+\******************************************************************************/ -+/* Lock PLS access */ -+gceSTATUS -+gcoOS_LockPLS( -+ void -+ ); -+ -+/* Unlock PLS access */ -+gceSTATUS -+gcoOS_UnLockPLS( -+ void -+ ); -+ -+/* Get PLS value for given key */ -+gctPOINTER -+gcoOS_GetPLSValue( -+ IN gcePLS_VALUE key -+ ); -+ -+/* Set PLS value of a given key */ -+void -+gcoOS_SetPLSValue( -+ IN gcePLS_VALUE key, -+ OUT gctPOINTER value -+ ); -+ -+/* Get access to the thread local storage. */ -+gceSTATUS -+gcoOS_GetTLS( -+ OUT gcsTLS_PTR * TLS -+ ); -+ -+ /* Copy the TLS from a source thread. */ -+ gceSTATUS gcoOS_CopyTLS(IN gcsTLS_PTR Source); -+ -+/* Destroy the objects associated with the current thread. */ -+void -+gcoOS_FreeThreadData( -+ void -+ ); -+ -+/* Empty function for compatibility. */ -+gceSTATUS -+gcoOS_Construct( -+ IN gctPOINTER Context, -+ OUT gcoOS * Os -+ ); -+ -+/* Empty function for compatibility. */ -+gceSTATUS -+gcoOS_Destroy( -+ IN gcoOS Os -+ ); -+ -+/* Get the base address for the physical memory. */ -+gceSTATUS -+gcoOS_GetBaseAddress( -+ IN gcoOS Os, -+ OUT gctUINT32_PTR BaseAddress -+ ); -+ -+/* Allocate memory from the heap. */ -+gceSTATUS -+gcoOS_Allocate( -+ IN gcoOS Os, -+ IN gctSIZE_T Bytes, -+ OUT gctPOINTER * Memory -+ ); -+ -+/* Get allocated memory size. */ -+gceSTATUS -+gcoOS_GetMemorySize( -+ IN gcoOS Os, -+ IN gctPOINTER Memory, -+ OUT gctSIZE_T_PTR MemorySize -+ ); -+ -+/* Free allocated memory. */ -+gceSTATUS -+gcoOS_Free( -+ IN gcoOS Os, -+ IN gctPOINTER Memory -+ ); -+ -+/* Allocate memory. */ -+gceSTATUS -+gcoOS_AllocateSharedMemory( -+ IN gcoOS Os, -+ IN gctSIZE_T Bytes, -+ OUT gctPOINTER * Memory -+ ); -+ -+/* Free memory. */ -+gceSTATUS -+gcoOS_FreeSharedMemory( -+ IN gcoOS Os, -+ IN gctPOINTER Memory -+ ); -+ -+/* Allocate memory. */ -+gceSTATUS -+gcoOS_AllocateMemory( -+ IN gcoOS Os, -+ IN gctSIZE_T Bytes, -+ OUT gctPOINTER * Memory -+ ); -+ -+/* Free memory. */ -+gceSTATUS -+gcoOS_FreeMemory( -+ IN gcoOS Os, -+ IN gctPOINTER Memory -+ ); -+ -+/* Allocate contiguous memory. */ -+gceSTATUS -+gcoOS_AllocateContiguous( -+ IN gcoOS Os, -+ IN gctBOOL InUserSpace, -+ IN OUT gctSIZE_T * Bytes, -+ OUT gctPHYS_ADDR * Physical, -+ OUT gctPOINTER * Logical -+ ); -+ -+/* Free contiguous memory. */ -+gceSTATUS -+gcoOS_FreeContiguous( -+ IN gcoOS Os, -+ IN gctPHYS_ADDR Physical, -+ IN gctPOINTER Logical, -+ IN gctSIZE_T Bytes -+ ); -+ -+/* Map user memory. */ -+gceSTATUS -+gcoOS_MapUserMemory( -+ IN gcoOS Os, -+ IN gctPOINTER Memory, -+ IN gctSIZE_T Size, -+ OUT gctPOINTER * Info, -+ OUT gctUINT32_PTR Address -+ ); -+ -+/* Map user memory. */ -+gceSTATUS -+gcoOS_MapUserMemoryEx( -+ IN gcoOS Os, -+ IN gctPOINTER Memory, -+ IN gctUINT32 Physical, -+ IN gctSIZE_T Size, -+ OUT gctPOINTER * Info, -+ OUT gctUINT32_PTR Address -+ ); -+ -+/* Unmap user memory. */ -+gceSTATUS -+gcoOS_UnmapUserMemory( -+ IN gcoOS Os, -+ IN gctPOINTER Memory, -+ IN gctSIZE_T Size, -+ IN gctPOINTER Info, -+ IN gctUINT32 Address -+ ); -+ -+/* Device I/O Control call to the kernel HAL layer. */ -+gceSTATUS -+gcoOS_DeviceControl( -+ IN gcoOS Os, -+ IN gctUINT32 IoControlCode, -+ IN gctPOINTER InputBuffer, -+ IN gctSIZE_T InputBufferSize, -+ IN gctPOINTER OutputBuffer, -+ IN gctSIZE_T OutputBufferSize -+ ); -+ -+/* Allocate non paged memory. */ -+gceSTATUS -+gcoOS_AllocateNonPagedMemory( -+ IN gcoOS Os, -+ IN gctBOOL InUserSpace, -+ IN OUT gctSIZE_T * Bytes, -+ OUT gctPHYS_ADDR * Physical, -+ OUT gctPOINTER * Logical -+ ); -+ -+/* Free non paged memory. */ -+gceSTATUS -+gcoOS_FreeNonPagedMemory( -+ IN gcoOS Os, -+ IN gctSIZE_T Bytes, -+ IN gctPHYS_ADDR Physical, -+ IN gctPOINTER Logical -+ ); -+ -+#define gcmOS_SAFE_FREE(os, mem) \ -+ gcoOS_Free(os, mem); \ -+ mem = gcvNULL -+ -+#define gcmOS_SAFE_FREE_SHARED_MEMORY(os, mem) \ -+ gcoOS_FreeSharedMemory(os, mem); \ -+ mem = gcvNULL -+ -+#define gcmkOS_SAFE_FREE(os, mem) \ -+ gckOS_Free(os, mem); \ -+ mem = gcvNULL -+ -+typedef enum _gceFILE_MODE -+{ -+ gcvFILE_CREATE = 0, -+ gcvFILE_APPEND, -+ gcvFILE_READ, -+ gcvFILE_CREATETEXT, -+ gcvFILE_APPENDTEXT, -+ gcvFILE_READTEXT, -+} -+gceFILE_MODE; -+ -+/* Open a file. */ -+gceSTATUS -+gcoOS_Open( -+ IN gcoOS Os, -+ IN gctCONST_STRING FileName, -+ IN gceFILE_MODE Mode, -+ OUT gctFILE * File -+ ); -+ -+/* Close a file. */ -+gceSTATUS -+gcoOS_Close( -+ IN gcoOS Os, -+ IN gctFILE File -+ ); -+ -+/* Read data from a file. */ -+gceSTATUS -+gcoOS_Read( -+ IN gcoOS Os, -+ IN gctFILE File, -+ IN gctSIZE_T ByteCount, -+ IN gctPOINTER Data, -+ OUT gctSIZE_T * ByteRead -+ ); -+ -+/* Write data to a file. */ -+gceSTATUS -+gcoOS_Write( -+ IN gcoOS Os, -+ IN gctFILE File, -+ IN gctSIZE_T ByteCount, -+ IN gctCONST_POINTER Data -+ ); -+ -+/* Flush data to a file. */ -+gceSTATUS -+gcoOS_Flush( -+ IN gcoOS Os, -+ IN gctFILE File -+ ); -+ -+/* Close a file descriptor. */ -+gceSTATUS -+gcoOS_CloseFD( -+ IN gcoOS Os, -+ IN gctINT FD -+ ); -+ -+/* Dup file descriptor to another. */ -+gceSTATUS -+gcoOS_DupFD( -+ IN gcoOS Os, -+ IN gctINT FD, -+ OUT gctINT * FD2 -+ ); -+ -+/* Create an endpoint for communication. */ -+gceSTATUS -+gcoOS_Socket( -+ IN gcoOS Os, -+ IN gctINT Domain, -+ IN gctINT Type, -+ IN gctINT Protocol, -+ OUT gctINT *SockFd -+ ); -+ -+/* Close a socket. */ -+gceSTATUS -+gcoOS_CloseSocket( -+ IN gcoOS Os, -+ IN gctINT SockFd -+ ); -+ -+/* Initiate a connection on a socket. */ -+gceSTATUS -+gcoOS_Connect( -+ IN gcoOS Os, -+ IN gctINT SockFd, -+ IN gctCONST_POINTER HostName, -+ IN gctUINT Port); -+ -+/* Shut down part of connection on a socket. */ -+gceSTATUS -+gcoOS_Shutdown( -+ IN gcoOS Os, -+ IN gctINT SockFd, -+ IN gctINT How -+ ); -+ -+/* Send a message on a socket. */ -+gceSTATUS -+gcoOS_Send( -+ IN gcoOS Os, -+ IN gctINT SockFd, -+ IN gctSIZE_T ByteCount, -+ IN gctCONST_POINTER Data, -+ IN gctINT Flags -+ ); -+ -+/* Initiate a connection on a socket. */ -+gceSTATUS -+gcoOS_WaitForSend( -+ IN gcoOS Os, -+ IN gctINT SockFd, -+ IN gctINT Seconds, -+ IN gctINT MicroSeconds); -+ -+/* Get environment variable value. */ -+gceSTATUS -+gcoOS_GetEnv( -+ IN gcoOS Os, -+ IN gctCONST_STRING VarName, -+ OUT gctSTRING * Value -+ ); -+ -+/* Set environment variable value. */ -+gceSTATUS -+gcoOS_SetEnv( -+ IN gcoOS Os, -+ IN gctCONST_STRING VarName, -+ IN gctSTRING Value -+ ); -+ -+/* Get current working directory. */ -+gceSTATUS -+gcoOS_GetCwd( -+ IN gcoOS Os, -+ IN gctINT SizeInBytes, -+ OUT gctSTRING Buffer -+ ); -+ -+/* Get file status info. */ -+gceSTATUS -+gcoOS_Stat( -+ IN gcoOS Os, -+ IN gctCONST_STRING FileName, -+ OUT gctPOINTER Buffer -+ ); -+ -+typedef enum _gceFILE_WHENCE -+{ -+ gcvFILE_SEEK_SET, -+ gcvFILE_SEEK_CUR, -+ gcvFILE_SEEK_END -+} -+gceFILE_WHENCE; -+ -+/* Set the current position of a file. */ -+gceSTATUS -+gcoOS_Seek( -+ IN gcoOS Os, -+ IN gctFILE File, -+ IN gctUINT32 Offset, -+ IN gceFILE_WHENCE Whence -+ ); -+ -+/* Set the current position of a file. */ -+gceSTATUS -+gcoOS_SetPos( -+ IN gcoOS Os, -+ IN gctFILE File, -+ IN gctUINT32 Position -+ ); -+ -+/* Get the current position of a file. */ -+gceSTATUS -+gcoOS_GetPos( -+ IN gcoOS Os, -+ IN gctFILE File, -+ OUT gctUINT32 * Position -+ ); -+ -+/* Same as strstr. */ -+gceSTATUS -+gcoOS_StrStr( -+ IN gctCONST_STRING String, -+ IN gctCONST_STRING SubString, -+ OUT gctSTRING * Output -+ ); -+ -+/* Find the last occurance of a character inside a string. */ -+gceSTATUS -+gcoOS_StrFindReverse( -+ IN gctCONST_STRING String, -+ IN gctINT8 Character, -+ OUT gctSTRING * Output -+ ); -+ -+gceSTATUS -+gcoOS_StrDup( -+ IN gcoOS Os, -+ IN gctCONST_STRING String, -+ OUT gctSTRING * Target -+ ); -+ -+/* Copy a string. */ -+gceSTATUS -+gcoOS_StrCopySafe( -+ IN gctSTRING Destination, -+ IN gctSIZE_T DestinationSize, -+ IN gctCONST_STRING Source -+ ); -+ -+/* Append a string. */ -+gceSTATUS -+gcoOS_StrCatSafe( -+ IN gctSTRING Destination, -+ IN gctSIZE_T DestinationSize, -+ IN gctCONST_STRING Source -+ ); -+ -+/* Compare two strings. */ -+gceSTATUS -+gcoOS_StrCmp( -+ IN gctCONST_STRING String1, -+ IN gctCONST_STRING String2 -+ ); -+ -+/* Compare characters of two strings. */ -+gceSTATUS -+gcoOS_StrNCmp( -+ IN gctCONST_STRING String1, -+ IN gctCONST_STRING String2, -+ IN gctSIZE_T Count -+ ); -+ -+/* Convert string to float. */ -+gceSTATUS -+gcoOS_StrToFloat( -+ IN gctCONST_STRING String, -+ OUT gctFLOAT * Float -+ ); -+ -+/* Convert hex string to integer. */ -+gceSTATUS gcoOS_HexStrToInt( -+ IN gctCONST_STRING String, -+ OUT gctINT * Int -+ ); -+ -+/* Convert hex string to float. */ -+gceSTATUS -+gcoOS_HexStrToFloat( -+ IN gctCONST_STRING String, -+ OUT gctFLOAT * Float -+ ); -+ -+/* Convert string to integer. */ -+gceSTATUS -+gcoOS_StrToInt( -+ IN gctCONST_STRING String, -+ OUT gctINT * Int -+ ); -+ -+gceSTATUS -+gcoOS_MemCmp( -+ IN gctCONST_POINTER Memory1, -+ IN gctCONST_POINTER Memory2, -+ IN gctSIZE_T Bytes -+ ); -+ -+gceSTATUS -+gcoOS_PrintStrSafe( -+ OUT gctSTRING String, -+ IN gctSIZE_T StringSize, -+ IN OUT gctUINT * Offset, -+ IN gctCONST_STRING Format, -+ ... -+ ); -+ -+gceSTATUS -+gcoOS_LoadLibrary( -+ IN gcoOS Os, -+ IN gctCONST_STRING Library, -+ OUT gctHANDLE * Handle -+ ); -+ -+gceSTATUS -+gcoOS_FreeLibrary( -+ IN gcoOS Os, -+ IN gctHANDLE Handle -+ ); -+ -+gceSTATUS -+gcoOS_GetProcAddress( -+ IN gcoOS Os, -+ IN gctHANDLE Handle, -+ IN gctCONST_STRING Name, -+ OUT gctPOINTER * Function -+ ); -+ -+gceSTATUS -+gcoOS_Compact( -+ IN gcoOS Os -+ ); -+ -+gceSTATUS -+gcoOS_AddSignalHandler ( -+ IN gceSignalHandlerType SignalHandlerType -+ ); -+ -+#if VIVANTE_PROFILER -+gceSTATUS -+gcoOS_ProfileStart( -+ IN gcoOS Os -+ ); -+ -+gceSTATUS -+gcoOS_ProfileEnd( -+ IN gcoOS Os, -+ IN gctCONST_STRING Title -+ ); -+ -+gceSTATUS -+gcoOS_SetProfileSetting( -+ IN gcoOS Os, -+ IN gctBOOL Enable, -+ IN gctCONST_STRING FileName -+ ); -+#endif -+ -+/* Query the video memory. */ -+gceSTATUS -+gcoOS_QueryVideoMemory( -+ IN gcoOS Os, -+ OUT gctPHYS_ADDR * InternalAddress, -+ OUT gctSIZE_T * InternalSize, -+ OUT gctPHYS_ADDR * ExternalAddress, -+ OUT gctSIZE_T * ExternalSize, -+ OUT gctPHYS_ADDR * ContiguousAddress, -+ OUT gctSIZE_T * ContiguousSize -+ ); -+ -+/* Detect if the process is the executable specified. */ -+gceSTATUS -+gcoOS_DetectProcessByNamePid( -+ IN gctCONST_STRING Name, -+ IN gctHANDLE Pid -+ ); -+ -+/* Detect if the current process is the executable specified. */ -+gceSTATUS -+gcoOS_DetectProcessByName( -+ IN gctCONST_STRING Name -+ ); -+ -+gceSTATUS -+gcoOS_DetectProcessByEncryptedName( -+ IN gctCONST_STRING Name -+ ); -+ -+#if defined(ANDROID) -+gceSTATUS -+gcoOS_DetectProgrameByEncryptedSymbols( -+ IN gcoOS_SymbolsList Symbols -+ ); -+#endif -+ -+/*----------------------------------------------------------------------------*/ -+/*----- Atoms ----------------------------------------------------------------*/ -+ -+/* Construct an atom. */ -+gceSTATUS -+gcoOS_AtomConstruct( -+ IN gcoOS Os, -+ OUT gcsATOM_PTR * Atom -+ ); -+ -+/* Destroy an atom. */ -+gceSTATUS -+gcoOS_AtomDestroy( -+ IN gcoOS Os, -+ IN gcsATOM_PTR Atom -+ ); -+ -+/* Get the 32-bit value protected by an atom. */ -+gceSTATUS -+gcoOS_AtomGet( -+ IN gcoOS Os, -+ IN gcsATOM_PTR Atom, -+ OUT gctINT32_PTR Value -+ ); -+ -+/* Set the 32-bit value protected by an atom. */ -+gceSTATUS -+gcoOS_AtomSet( -+ IN gcoOS Os, -+ IN gcsATOM_PTR Atom, -+ IN gctINT32 Value -+ ); -+ -+/* Increment an atom. */ -+gceSTATUS -+gcoOS_AtomIncrement( -+ IN gcoOS Os, -+ IN gcsATOM_PTR Atom, -+ OUT gctINT32_PTR OldValue -+ ); -+ -+/* Decrement an atom. */ -+gceSTATUS -+gcoOS_AtomDecrement( -+ IN gcoOS Os, -+ IN gcsATOM_PTR Atom, -+ OUT gctINT32_PTR OldValue -+ ); -+ -+gctHANDLE -+gcoOS_GetCurrentProcessID( -+ void -+ ); -+ -+gctHANDLE -+gcoOS_GetCurrentThreadID( -+ void -+ ); -+ -+/*----------------------------------------------------------------------------*/ -+/*----- Time -----------------------------------------------------------------*/ -+ -+/* Get the number of milliseconds since the system started. */ -+gctUINT32 -+gcoOS_GetTicks( -+ void -+ ); -+ -+/* Get time in microseconds. */ -+gceSTATUS -+gcoOS_GetTime( -+ gctUINT64_PTR Time -+ ); -+ -+/* Get CPU usage in microseconds. */ -+gceSTATUS -+gcoOS_GetCPUTime( -+ gctUINT64_PTR CPUTime -+ ); -+ -+/* Get memory usage. */ -+gceSTATUS -+gcoOS_GetMemoryUsage( -+ gctUINT32_PTR MaxRSS, -+ gctUINT32_PTR IxRSS, -+ gctUINT32_PTR IdRSS, -+ gctUINT32_PTR IsRSS -+ ); -+ -+/* Delay a number of microseconds. */ -+gceSTATUS -+gcoOS_Delay( -+ IN gcoOS Os, -+ IN gctUINT32 Delay -+ ); -+ -+/*----------------------------------------------------------------------------*/ -+/*----- Threads --------------------------------------------------------------*/ -+ -+typedef void * gctTHREAD_RETURN; -+typedef void * (* gcTHREAD_ROUTINE)(void *); -+ -+/* Create a new thread. */ -+gceSTATUS -+gcoOS_CreateThread( -+ IN gcoOS Os, -+ IN gcTHREAD_ROUTINE Worker, -+ IN gctPOINTER Argument, -+ OUT gctPOINTER * Thread -+ ); -+ -+/* Close a thread. */ -+gceSTATUS -+gcoOS_CloseThread( -+ IN gcoOS Os, -+ IN gctPOINTER Thread -+ ); -+ -+/*----------------------------------------------------------------------------*/ -+/*----- Mutexes --------------------------------------------------------------*/ -+ -+/* Create a new mutex. */ -+gceSTATUS -+gcoOS_CreateMutex( -+ IN gcoOS Os, -+ OUT gctPOINTER * Mutex -+ ); -+ -+/* Delete a mutex. */ -+gceSTATUS -+gcoOS_DeleteMutex( -+ IN gcoOS Os, -+ IN gctPOINTER Mutex -+ ); -+ -+/* Acquire a mutex. */ -+gceSTATUS -+gcoOS_AcquireMutex( -+ IN gcoOS Os, -+ IN gctPOINTER Mutex, -+ IN gctUINT32 Timeout -+ ); -+ -+/* Release a mutex. */ -+gceSTATUS -+gcoOS_ReleaseMutex( -+ IN gcoOS Os, -+ IN gctPOINTER Mutex -+ ); -+ -+/*----------------------------------------------------------------------------*/ -+/*----- Signals --------------------------------------------------------------*/ -+ -+/* Create a signal. */ -+gceSTATUS -+gcoOS_CreateSignal( -+ IN gcoOS Os, -+ IN gctBOOL ManualReset, -+ OUT gctSIGNAL * Signal -+ ); -+ -+/* Destroy a signal. */ -+gceSTATUS -+gcoOS_DestroySignal( -+ IN gcoOS Os, -+ IN gctSIGNAL Signal -+ ); -+ -+/* Signal a signal. */ -+gceSTATUS -+gcoOS_Signal( -+ IN gcoOS Os, -+ IN gctSIGNAL Signal, -+ IN gctBOOL State -+ ); -+ -+/* Wait for a signal. */ -+gceSTATUS -+gcoOS_WaitSignal( -+ IN gcoOS Os, -+ IN gctSIGNAL Signal, -+ IN gctUINT32 Wait -+ ); -+ -+/* Map a signal from another process */ -+gceSTATUS -+gcoOS_MapSignal( -+ IN gctSIGNAL RemoteSignal, -+ OUT gctSIGNAL * LocalSignal -+ ); -+ -+/* Unmap a signal mapped from another process */ -+gceSTATUS -+gcoOS_UnmapSignal( -+ IN gctSIGNAL Signal -+ ); -+ -+/*----------------------------------------------------------------------------*/ -+/*----- Android Native Fence -------------------------------------------------*/ -+ -+/* Create sync point. */ -+gceSTATUS -+gcoOS_CreateSyncPoint( -+ IN gcoOS Os, -+ OUT gctSYNC_POINT * SyncPoint -+ ); -+ -+/* Destroy sync point. */ -+gceSTATUS -+gcoOS_DestroySyncPoint( -+ IN gcoOS Os, -+ IN gctSYNC_POINT SyncPoint -+ ); -+ -+/* Create native fence. */ -+gceSTATUS -+gcoOS_CreateNativeFence( -+ IN gcoOS Os, -+ IN gctSYNC_POINT SyncPoint, -+ OUT gctINT * FenceFD -+ ); -+ -+/* Wait on native fence. */ -+gceSTATUS -+gcoOS_WaitNativeFence( -+ IN gcoOS Os, -+ IN gctINT FenceFD, -+ IN gctUINT32 Timeout -+ ); -+ -+/*----------------------------------------------------------------------------*/ -+/*----- Memory Access and Cache ----------------------------------------------*/ -+ -+/* Write a register. */ -+gceSTATUS -+gcoOS_WriteRegister( -+ IN gcoOS Os, -+ IN gctUINT32 Address, -+ IN gctUINT32 Data -+ ); -+ -+/* Read a register. */ -+gceSTATUS -+gcoOS_ReadRegister( -+ IN gcoOS Os, -+ IN gctUINT32 Address, -+ OUT gctUINT32 * Data -+ ); -+ -+gceSTATUS -+gcoOS_CacheClean( -+ IN gcoOS Os, -+ IN gctUINT32 Node, -+ IN gctPOINTER Logical, -+ IN gctSIZE_T Bytes -+ ); -+ -+gceSTATUS -+gcoOS_CacheFlush( -+ IN gcoOS Os, -+ IN gctUINT32 Node, -+ IN gctPOINTER Logical, -+ IN gctSIZE_T Bytes -+ ); -+ -+gceSTATUS -+gcoOS_CacheInvalidate( -+ IN gcoOS Os, -+ IN gctUINT32 Node, -+ IN gctPOINTER Logical, -+ IN gctSIZE_T Bytes -+ ); -+ -+gceSTATUS -+gcoOS_MemoryBarrier( -+ IN gcoOS Os, -+ IN gctPOINTER Logical -+ ); -+ -+gceSTATUS -+gcoOS_CPUPhysicalToGPUPhysical( -+ IN gctUINT32 CPUPhysical, -+ OUT gctUINT32_PTR GPUPhysical -+ ); -+ -+/*----------------------------------------------------------------------------*/ -+/*----- Profile --------------------------------------------------------------*/ -+ -+gceSTATUS -+gckOS_GetProfileTick( -+ OUT gctUINT64_PTR Tick -+ ); -+ -+gceSTATUS -+gckOS_QueryProfileTickRate( -+ OUT gctUINT64_PTR TickRate -+ ); -+ -+gctUINT32 -+gckOS_ProfileToMS( -+ IN gctUINT64 Ticks -+ ); -+ -+gceSTATUS -+gcoOS_GetProfileTick( -+ OUT gctUINT64_PTR Tick -+ ); -+ -+gceSTATUS -+gcoOS_QueryProfileTickRate( -+ OUT gctUINT64_PTR TickRate -+ ); -+ -+#define _gcmPROFILE_INIT(prefix, freq, start) \ -+ do { \ -+ prefix ## OS_QueryProfileTickRate(&(freq)); \ -+ prefix ## OS_GetProfileTick(&(start)); \ -+ } while (gcvFALSE) -+ -+#define _gcmPROFILE_QUERY(prefix, start, ticks) \ -+ do { \ -+ prefix ## OS_GetProfileTick(&(ticks)); \ -+ (ticks) = ((ticks) > (start)) ? ((ticks) - (start)) \ -+ : (~0ull - (start) + (ticks) + 1); \ -+ } while (gcvFALSE) -+ -+#if gcdENABLE_PROFILING -+# define gcmkPROFILE_INIT(freq, start) _gcmPROFILE_INIT(gck, freq, start) -+# define gcmkPROFILE_QUERY(start, ticks) _gcmPROFILE_QUERY(gck, start, ticks) -+# define gcmPROFILE_INIT(freq, start) _gcmPROFILE_INIT(gco, freq, start) -+# define gcmPROFILE_QUERY(start, ticks) _gcmPROFILE_QUERY(gco, start, ticks) -+# define gcmPROFILE_ONLY(x) x -+# define gcmPROFILE_ELSE(x) do { } while (gcvFALSE) -+# define gcmPROFILE_DECLARE_ONLY(x) x -+# define gcmPROFILE_DECLARE_ELSE(x) typedef x -+#else -+# define gcmkPROFILE_INIT(start, freq) do { } while (gcvFALSE) -+# define gcmkPROFILE_QUERY(start, ticks) do { } while (gcvFALSE) -+# define gcmPROFILE_INIT(start, freq) do { } while (gcvFALSE) -+# define gcmPROFILE_QUERY(start, ticks) do { } while (gcvFALSE) -+# define gcmPROFILE_ONLY(x) do { } while (gcvFALSE) -+# define gcmPROFILE_ELSE(x) x -+# define gcmPROFILE_DECLARE_ONLY(x) do { } while (gcvFALSE) -+# define gcmPROFILE_DECLARE_ELSE(x) x -+#endif -+ -+/******************************************************************************* -+** gcoMATH object -+*/ -+ -+#define gcdPI 3.14159265358979323846f -+ -+/* Kernel. */ -+gctINT -+gckMATH_ModuloInt( -+ IN gctINT X, -+ IN gctINT Y -+ ); -+ -+/* User. */ -+gctUINT32 -+gcoMATH_Log2in5dot5( -+ IN gctINT X -+ ); -+ -+ -+gctFLOAT -+gcoMATH_UIntAsFloat( -+ IN gctUINT32 X -+ ); -+ -+gctUINT32 -+gcoMATH_FloatAsUInt( -+ IN gctFLOAT X -+ ); -+ -+gctBOOL -+gcoMATH_CompareEqualF( -+ IN gctFLOAT X, -+ IN gctFLOAT Y -+ ); -+ -+gctUINT16 -+gcoMATH_UInt8AsFloat16( -+ IN gctUINT8 X -+ ); -+ -+gctUINT32 -+gcoMATH_Float16ToFloat( -+ IN gctUINT16 In -+ ); -+ -+gctUINT16 -+gcoMATH_FloatToFloat16( -+ IN gctUINT32 In -+ ); -+ -+gctUINT32 -+gcoMATH_Float11ToFloat( -+ IN gctUINT32 In -+ ); -+ -+gctUINT16 -+gcoMATH_FloatToFloat11( -+ IN gctUINT32 In -+ ); -+ -+gctUINT32 -+gcoMATH_Float10ToFloat( -+ IN gctUINT32 In -+ ); -+ -+gctUINT16 -+gcoMATH_FloatToFloat10( -+ IN gctUINT32 In -+ ); -+ -+gctUINT32 -+gcoMATH_Float14ToFloat( -+ IN gctUINT16 In -+ ); -+ -+/******************************************************************************\ -+**************************** Coordinate Structures ***************************** -+\******************************************************************************/ -+ -+typedef struct _gcsPOINT -+{ -+ gctINT32 x; -+ gctINT32 y; -+} -+gcsPOINT; -+ -+typedef struct _gcsSIZE -+{ -+ gctINT32 width; -+ gctINT32 height; -+} -+gcsSIZE; -+ -+typedef struct _gcsRECT -+{ -+ gctINT32 left; -+ gctINT32 top; -+ gctINT32 right; -+ gctINT32 bottom; -+} -+gcsRECT; -+ -+typedef union _gcsPIXEL -+{ -+ struct -+ { -+ gctFLOAT r, g, b, a; -+ gctFLOAT d, s; -+ } pf; -+ -+ struct -+ { -+ gctINT32 r, g, b, a; -+ gctINT32 d, s; -+ } pi; -+ -+ struct -+ { -+ gctUINT32 r, g, b, a; -+ gctUINT32 d, s; -+ } pui; -+ -+} gcsPIXEL; -+ -+/******************************************************************************\ -+********************************* gcoSURF Object ******************************** -+\******************************************************************************/ -+ -+/*----------------------------------------------------------------------------*/ -+/*------------------------------- gcoSURF Common ------------------------------*/ -+ -+/* Color format classes. */ -+typedef enum _gceFORMAT_CLASS -+{ -+ gcvFORMAT_CLASS_RGBA = 4500, -+ gcvFORMAT_CLASS_YUV, -+ gcvFORMAT_CLASS_INDEX, -+ gcvFORMAT_CLASS_LUMINANCE, -+ gcvFORMAT_CLASS_BUMP, -+ gcvFORMAT_CLASS_DEPTH, -+ gcvFORMAT_CLASS_ASTC, -+ gcvFORMAT_CLASS_OTHER -+} -+gceFORMAT_CLASS; -+ -+/* Color format data type */ -+typedef enum _gceFORMAT_DATATYPE -+{ -+ gcvFORMAT_DATATYPE_UNSIGNED_NORMALIZED, -+ gcvFORMAT_DATATYPE_SIGNED_NORMALIZED, -+ gcvFORMAT_DATATYPE_UNSIGNED_INTEGER, -+ gcvFORMAT_DATATYPE_SIGNED_INTEGER, -+ gcvFORMAT_DATATYPE_FLOAT16, -+ gcvFORMAT_DATATYPE_FLOAT32, -+ gcvFORMAT_DATATYPE_FLOAT_E5B9G9R9, -+ gcvFORMAT_DATATYPE_FLOAT_B10G11R11F, -+ gcvFORMAT_DATATYPE_INDEX, -+ gcvFORMAT_DATATYPE_SRGB, -+ gcvFORMAT_DATATYPE_FLOAT32_UINT, -+} -+gceFORMAT_DATATYPE; -+ -+/* Special enums for width field in gcsFORMAT_COMPONENT. */ -+typedef enum _gceCOMPONENT_CONTROL -+{ -+ gcvCOMPONENT_NOTPRESENT = 0x00, -+ gcvCOMPONENT_DONTCARE = 0x80, -+ gcvCOMPONENT_WIDTHMASK = 0x7F, -+ gcvCOMPONENT_ODD = 0x80 -+} -+gceCOMPONENT_CONTROL; -+ -+/* Color format component parameters. */ -+typedef struct _gcsFORMAT_COMPONENT -+{ -+ gctUINT8 start; -+ gctUINT8 width; -+} -+gcsFORMAT_COMPONENT; -+ -+/* RGBA color format class. */ -+typedef struct _gcsFORMAT_CLASS_TYPE_RGBA -+{ -+ gcsFORMAT_COMPONENT alpha; -+ gcsFORMAT_COMPONENT red; -+ gcsFORMAT_COMPONENT green; -+ gcsFORMAT_COMPONENT blue; -+} -+gcsFORMAT_CLASS_TYPE_RGBA; -+ -+/* YUV color format class. */ -+typedef struct _gcsFORMAT_CLASS_TYPE_YUV -+{ -+ gcsFORMAT_COMPONENT y; -+ gcsFORMAT_COMPONENT u; -+ gcsFORMAT_COMPONENT v; -+} -+gcsFORMAT_CLASS_TYPE_YUV; -+ -+/* Index color format class. */ -+typedef struct _gcsFORMAT_CLASS_TYPE_INDEX -+{ -+ gcsFORMAT_COMPONENT value; -+} -+gcsFORMAT_CLASS_TYPE_INDEX; -+ -+/* Luminance color format class. */ -+typedef struct _gcsFORMAT_CLASS_TYPE_LUMINANCE -+{ -+ gcsFORMAT_COMPONENT alpha; -+ gcsFORMAT_COMPONENT value; -+} -+gcsFORMAT_CLASS_TYPE_LUMINANCE; -+ -+/* Bump map color format class. */ -+typedef struct _gcsFORMAT_CLASS_TYPE_BUMP -+{ -+ gcsFORMAT_COMPONENT alpha; -+ gcsFORMAT_COMPONENT l; -+ gcsFORMAT_COMPONENT v; -+ gcsFORMAT_COMPONENT u; -+ gcsFORMAT_COMPONENT q; -+ gcsFORMAT_COMPONENT w; -+} -+gcsFORMAT_CLASS_TYPE_BUMP; -+ -+/* Depth and stencil format class. */ -+typedef struct _gcsFORMAT_CLASS_TYPE_DEPTH -+{ -+ gcsFORMAT_COMPONENT depth; -+ gcsFORMAT_COMPONENT stencil; -+} -+gcsFORMAT_CLASS_TYPE_DEPTH; -+ -+typedef union _gcuPIXEL_FORMAT_CLASS -+{ -+ gcsFORMAT_CLASS_TYPE_BUMP bump; -+ gcsFORMAT_CLASS_TYPE_RGBA rgba; -+ gcsFORMAT_CLASS_TYPE_YUV yuv; -+ gcsFORMAT_CLASS_TYPE_LUMINANCE lum; -+ gcsFORMAT_CLASS_TYPE_INDEX index; -+ gcsFORMAT_CLASS_TYPE_DEPTH depth; -+} -+gcuPIXEL_FORMAT_CLASS; -+ -+/* Format parameters. */ -+typedef struct _gcsSURF_FORMAT_INFO -+{ -+ /* Name of the format */ -+ gctCONST_STRING formatName; -+ -+ /* Format code and class. */ -+ gceSURF_FORMAT format; -+ gceFORMAT_CLASS fmtClass; -+ -+ /* Format data type */ -+ gceFORMAT_DATATYPE fmtDataType; -+ -+ /* The size of one pixel in bits. */ -+ gctUINT8 bitsPerPixel; -+ -+ /* Pixel block dimensions. */ -+ gctUINT blockWidth; -+ gctUINT blockHeight; -+ -+ /* Pixel block size in bits. */ -+ gctUINT blockSize; -+ -+ /* Some formats are larger than what the GPU can support. */ -+ /* These formats are read in the number of layers specified. */ -+ gctUINT8 layers; -+ -+ /* The format is faked and software will interpret it differently -+ ** with HW. Most of them can't be blendable(PE) or filterable(TX). -+ */ -+ gctBOOL fakedFormat; -+ -+ /* Some formats have two neighbour pixels interleaved together. */ -+ /* To describe such format, set the flag to 1 and add another */ -+ /* like this one describing the odd pixel format. */ -+ gctBOOL interleaved; -+ -+ /* sRGB format. */ -+ gctBOOL sRGB; -+ -+ /* Format components. */ -+ gcuPIXEL_FORMAT_CLASS u; -+ -+ /* Format components. */ -+ gcuPIXEL_FORMAT_CLASS uOdd; -+ -+ /* Render format. */ -+ gceSURF_FORMAT closestRenderFormat; -+ /*gctCLOSEST_FORMAT dynamicClosestRenderFormat;*/ -+ gctUINT renderFormat; -+ const gceTEXTURE_SWIZZLE * pixelSwizzle; -+ -+ /* Texture format. */ -+ gceSURF_FORMAT closestTXFormat; -+ gctUINT txFormat; -+ const gceTEXTURE_SWIZZLE * txSwizzle; -+ gctBOOL txIntFilter; -+} -+gcsSURF_FORMAT_INFO; -+ -+/* Frame buffer information. */ -+typedef struct _gcsSURF_FRAMEBUFFER -+{ -+ gctPOINTER logical; -+ gctUINT width, height; -+ gctINT stride; -+ gceSURF_FORMAT format; -+} -+gcsSURF_FRAMEBUFFER; -+ -+/* Generic pixel component descriptors. */ -+extern gcsFORMAT_COMPONENT gcvPIXEL_COMP_XXX8; -+extern gcsFORMAT_COMPONENT gcvPIXEL_COMP_XX8X; -+extern gcsFORMAT_COMPONENT gcvPIXEL_COMP_X8XX; -+extern gcsFORMAT_COMPONENT gcvPIXEL_COMP_8XXX; -+ -+typedef enum _gceORIENTATION -+{ -+ gcvORIENTATION_TOP_BOTTOM, -+ gcvORIENTATION_BOTTOM_TOP, -+} -+gceORIENTATION; -+ -+ -+/* Construct a new gcoSURF object. */ -+gceSTATUS -+gcoSURF_Construct( -+ IN gcoHAL Hal, -+ IN gctUINT Width, -+ IN gctUINT Height, -+ IN gctUINT Depth, -+ IN gceSURF_TYPE Type, -+ IN gceSURF_FORMAT Format, -+ IN gcePOOL Pool, -+ OUT gcoSURF * Surface -+ ); -+ -+/* Destroy an gcoSURF object. */ -+gceSTATUS -+gcoSURF_Destroy( -+ IN gcoSURF Surface -+ ); -+ -+/* Map user-allocated surface. */ -+gceSTATUS -+gcoSURF_MapUserSurface( -+ IN gcoSURF Surface, -+ IN gctUINT Alignment, -+ IN gctPOINTER Logical, -+ IN gctUINT32 Physical -+ ); -+ -+/* Wrapp surface with known logical/GPU address */ -+gceSTATUS -+gcoSURF_WrapSurface( -+ IN gcoSURF Surface, -+ IN gctUINT Alignment, -+ IN gctPOINTER Logical, -+ IN gctUINT32 Physical -+ ); -+ -+ -+/* Query vid mem node info. */ -+gceSTATUS -+gcoSURF_QueryVidMemNode( -+ IN gcoSURF Surface, -+ OUT gctUINT32 * Node, -+ OUT gcePOOL * Pool, -+ OUT gctSIZE_T_PTR Bytes -+ ); -+ -+/* Set the color type of the surface. */ -+gceSTATUS -+gcoSURF_SetColorType( -+ IN gcoSURF Surface, -+ IN gceSURF_COLOR_TYPE ColorType -+ ); -+ -+/* Get the color type of the surface. */ -+gceSTATUS -+gcoSURF_GetColorType( -+ IN gcoSURF Surface, -+ OUT gceSURF_COLOR_TYPE *ColorType -+ ); -+ -+/* Set the color space of the surface. */ -+gceSTATUS -+gcoSURF_SetColorSpace( -+ IN gcoSURF Surface, -+ IN gceSURF_COLOR_SPACE ColorSpace -+ ); -+ -+/* Get the color space of the surface. */ -+gceSTATUS -+gcoSURF_GetColorSpace( -+ IN gcoSURF Surface, -+ OUT gceSURF_COLOR_SPACE *ColorSpace -+ ); -+ -+ -+/* Set the surface ration angle. */ -+gceSTATUS -+gcoSURF_SetRotation( -+ IN gcoSURF Surface, -+ IN gceSURF_ROTATION Rotation -+ ); -+ -+gceSTATUS -+gcoSURF_IsValid( -+ IN gcoSURF Surface -+ ); -+ -+#if gcdENABLE_3D -+/* Verify and return the state of the tile status mechanism. */ -+gceSTATUS -+gcoSURF_IsTileStatusSupported( -+ IN gcoSURF Surface -+ ); -+ -+/* Verify if surface has tile status enabled. */ -+gceSTATUS -+gcoSURF_IsTileStatusEnabled( -+ IN gcoSURF Surface -+ ); -+ -+/* Verify if surface is compressed. */ -+gceSTATUS -+gcoSURF_IsCompressed( -+ IN gcoSURF Surface -+ ); -+ -+/* Enable tile status for the specified surface on zero slot. */ -+gceSTATUS -+gcoSURF_EnableTileStatus( -+ IN gcoSURF Surface -+ ); -+ -+/* Enable tile status for the specified surface on specified slot. */ -+gceSTATUS -+gcoSURF_EnableTileStatusEx( -+ IN gcoSURF Surface, -+ IN gctUINT RtIndex -+ ); -+ -+/* Disable tile status for the specified surface. */ -+gceSTATUS -+gcoSURF_DisableTileStatus( -+ IN gcoSURF Surface, -+ IN gctBOOL Decompress -+ ); -+ -+/* Flush tile status cache for the specified surface. */ -+gceSTATUS -+gcoSURF_FlushTileStatus( -+ IN gcoSURF Surface, -+ IN gctBOOL Decompress -+ ); -+#endif /* gcdENABLE_3D */ -+ -+/* Get surface size. */ -+gceSTATUS -+gcoSURF_GetSize( -+ IN gcoSURF Surface, -+ OUT gctUINT * Width, -+ OUT gctUINT * Height, -+ OUT gctUINT * Depth -+ ); -+ -+/* Get surface aligned sizes. */ -+gceSTATUS -+gcoSURF_GetAlignedSize( -+ IN gcoSURF Surface, -+ OUT gctUINT * Width, -+ OUT gctUINT * Height, -+ OUT gctINT * Stride -+ ); -+ -+/* Get alignments. */ -+gceSTATUS -+gcoSURF_GetAlignment( -+ IN gceSURF_TYPE Type, -+ IN gceSURF_FORMAT Format, -+ OUT gctUINT * AddressAlignment, -+ OUT gctUINT * XAlignment, -+ OUT gctUINT * YAlignment -+ ); -+ -+gceSTATUS -+gcoSURF_AlignResolveRect( -+ IN gcoSURF Surf, -+ IN gcsPOINT_PTR RectOrigin, -+ IN gcsPOINT_PTR RectSize, -+ OUT gcsPOINT_PTR AlignedOrigin, -+ OUT gcsPOINT_PTR AlignedSize -+ ); -+ -+/* Get surface type and format. */ -+gceSTATUS -+gcoSURF_GetFormat( -+ IN gcoSURF Surface, -+ OUT OPTIONAL gceSURF_TYPE * Type, -+ OUT OPTIONAL gceSURF_FORMAT * Format -+ ); -+ -+/* Get surface information */ -+gceSTATUS -+gcoSURF_GetFormatInfo( -+ IN gcoSURF Surface, -+ OUT gcsSURF_FORMAT_INFO_PTR * formatInfo -+ ); -+ -+/* Get Surface pack format */ -+gceSTATUS -+gcoSURF_GetPackedFormat( -+ IN gcoSURF Surface, -+ OUT gceSURF_FORMAT * Format -+ ); -+ -+/* Get surface tiling. */ -+gceSTATUS -+gcoSURF_GetTiling( -+ IN gcoSURF Surface, -+ OUT gceTILING * Tiling -+ ); -+ -+/* Get flip bitmap offset bytes. */ -+gceSTATUS -+gcoSURF_GetFlipBitmapOffset( -+ IN gcoSURF Surface, -+ OUT gctUINT_PTR FlipBitmapOffset -+ ); -+ -+/* Get bottom buffer offset bytes. */ -+gceSTATUS -+gcoSURF_GetBottomBufferOffset( -+ IN gcoSURF Surface, -+ OUT gctUINT_PTR BottomBufferOffset -+ ); -+ -+/* Lock the surface. */ -+gceSTATUS -+gcoSURF_Lock( -+ IN gcoSURF Surface, -+ IN OUT gctUINT32 * Address, -+ IN OUT gctPOINTER * Memory -+ ); -+ -+/* Unlock the surface. */ -+gceSTATUS -+gcoSURF_Unlock( -+ IN gcoSURF Surface, -+ IN gctPOINTER Memory -+ ); -+ -+/*. Query surface flags.*/ -+gceSTATUS -+gcoSURF_QueryFlags( -+ IN gcoSURF Surface, -+ IN gceSURF_FLAG Flag -+ ); -+ -+/* Return pixel format parameters; Info is required to be a pointer to an -+ * array of at least two items because some formats have up to two records -+ * of description. */ -+gceSTATUS -+gcoSURF_QueryFormat( -+ IN gceSURF_FORMAT Format, -+ OUT gcsSURF_FORMAT_INFO_PTR * Info -+ ); -+ -+/* Compute the color pixel mask. */ -+gceSTATUS -+gcoSURF_ComputeColorMask( -+ IN gcsSURF_FORMAT_INFO_PTR Format, -+ OUT gctUINT32_PTR ColorMask -+ ); -+ -+/* Flush the surface. */ -+gceSTATUS -+gcoSURF_Flush( -+ IN gcoSURF Surface -+ ); -+ -+/* Fill surface from it's tile status buffer. */ -+gceSTATUS -+gcoSURF_FillFromTile( -+ IN gcoSURF Surface -+ ); -+ -+/* Fill surface with a value. */ -+gceSTATUS -+gcoSURF_Fill( -+ IN gcoSURF Surface, -+ IN gcsPOINT_PTR Origin, -+ IN gcsSIZE_PTR Size, -+ IN gctUINT32 Value, -+ IN gctUINT32 Mask -+ ); -+ -+/* Alpha blend two surfaces together. */ -+gceSTATUS -+gcoSURF_Blend( -+ IN gcoSURF SrcSurface, -+ IN gcoSURF DestSurface, -+ IN gcsPOINT_PTR SrcOrig, -+ IN gcsPOINT_PTR DestOrigin, -+ IN gcsSIZE_PTR Size, -+ IN gceSURF_BLEND_MODE Mode -+ ); -+ -+/* Create a new gcoSURF wrapper object. */ -+gceSTATUS -+gcoSURF_ConstructWrapper( -+ IN gcoHAL Hal, -+ OUT gcoSURF * Surface -+ ); -+ -+/* Set surface flags.*/ -+gceSTATUS -+gcoSURF_SetFlags( -+ IN gcoSURF Surface, -+ IN gceSURF_FLAG Flag, -+ IN gctBOOL Value -+ ); -+ -+/* Set the underlying buffer for the surface wrapper. */ -+gceSTATUS -+gcoSURF_SetBuffer( -+ IN gcoSURF Surface, -+ IN gceSURF_TYPE Type, -+ IN gceSURF_FORMAT Format, -+ IN gctUINT Stride, -+ IN gctPOINTER Logical, -+ IN gctUINT32 Physical -+ ); -+ -+/* Set the underlying video buffer for the surface wrapper. */ -+gceSTATUS -+gcoSURF_SetVideoBuffer( -+ IN gcoSURF Surface, -+ IN gceSURF_TYPE Type, -+ IN gceSURF_FORMAT Format, -+ IN gctUINT Width, -+ IN gctUINT Height, -+ IN gctUINT Stride, -+ IN gctPOINTER *LogicalPlane1, -+ IN gctUINT32 *PhysicalPlane1 -+ ); -+ -+/* Set the size of the surface in pixels and map the underlying buffer. */ -+gceSTATUS -+gcoSURF_SetWindow( -+ IN gcoSURF Surface, -+ IN gctUINT X, -+ IN gctUINT Y, -+ IN gctUINT Width, -+ IN gctUINT Height -+ ); -+ -+/* Set width/height alignment of the surface directly and calculate stride/size. This is only for dri backend now. Please be careful before use. */ -+gceSTATUS -+gcoSURF_SetAlignment( -+ IN gcoSURF Surface, -+ IN gctUINT Width, -+ IN gctUINT Height -+ ); -+ -+/* Increase reference count of the surface. */ -+gceSTATUS -+gcoSURF_ReferenceSurface( -+ IN gcoSURF Surface -+ ); -+ -+/* Get surface reference count. */ -+gceSTATUS -+gcoSURF_QueryReferenceCount( -+ IN gcoSURF Surface, -+ OUT gctINT32 * ReferenceCount -+ ); -+ -+/* Set surface orientation. */ -+gceSTATUS -+gcoSURF_SetOrientation( -+ IN gcoSURF Surface, -+ IN gceORIENTATION Orientation -+ ); -+ -+/* Query surface orientation. */ -+gceSTATUS -+gcoSURF_QueryOrientation( -+ IN gcoSURF Surface, -+ OUT gceORIENTATION * Orientation -+ ); -+ -+gceSTATUS -+gcoSURF_SetOffset( -+ IN gcoSURF Surface, -+ IN gctSIZE_T Offset -+ ); -+ -+gceSTATUS -+gcoSURF_NODE_Cache( -+ IN gcsSURF_NODE_PTR Node, -+ IN gctPOINTER Logical, -+ IN gctSIZE_T Bytes, -+ IN gceCACHEOPERATION Operation -+ ); -+ -+/* Lock and unlock surface node */ -+gceSTATUS -+gcoSURF_LockNode( -+ IN gcsSURF_NODE_PTR Node, -+ OUT gctUINT32 * Address, -+ OUT gctPOINTER * Memory -+ ); -+ -+gceSTATUS -+gcoSURF_UnLockNode( -+ IN gcsSURF_NODE_PTR Node, -+ IN gceSURF_TYPE Type -+ ); -+ -+/* Perform CPU cache operation on surface node */ -+gceSTATUS -+gcoSURF_NODE_CPUCacheOperation( -+ IN gcsSURF_NODE_PTR Node, -+ IN gceSURF_TYPE Type, -+ IN gctSIZE_T Offset, -+ IN gctSIZE_T Length, -+ IN gceCACHEOPERATION Operation -+ ); -+ -+/* Perform CPU cache operation on surface */ -+gceSTATUS -+gcoSURF_CPUCacheOperation( -+ IN gcoSURF Surface, -+ IN gceCACHEOPERATION Operation -+ ); -+ -+ -+gceSTATUS -+gcoSURF_Swap( -+ IN gcoSURF Surface1, -+ IN gcoSURF Surface2 -+ ); -+ -+gceSTATUS -+gcoSURF_ResetSurWH( -+ IN gcoSURF Surface, -+ IN gctUINT oriw, -+ IN gctUINT orih, -+ IN gctUINT alignw, -+ IN gctUINT alignh, -+ IN gceSURF_FORMAT fmt -+); -+ -+/* Update surface timestamp. */ -+gceSTATUS -+gcoSURF_UpdateTimeStamp( -+ IN gcoSURF Surface -+ ); -+ -+/* Query surface current timestamp. */ -+gceSTATUS -+gcoSURF_QueryTimeStamp( -+ IN gcoSURF Surface, -+ OUT gctUINT64 * TimeStamp -+ ); -+ -+/* -+ * Allocate shared buffer for this surface, so that -+ * surface states can be shared across processes. -+ */ -+gceSTATUS -+gcoSURF_AllocShBuffer( -+ IN gcoSURF Surface, -+ OUT gctSHBUF * ShBuf -+ ); -+ -+/* Bind shared buffer to this surface */ -+gceSTATUS -+gcoSURF_BindShBuffer( -+ IN gcoSURF Surface, -+ IN gctSHBUF ShBuf -+ ); -+ -+/* Push surface shared states to shared buffer. */ -+gceSTATUS -+gcoSURF_PushSharedInfo( -+ IN gcoSURF Surface -+ ); -+ -+/* Pop shared states from shared buffer. */ -+gceSTATUS -+gcoSURF_PopSharedInfo( -+ IN gcoSURF Surface -+ ); -+ -+#if (gcdENABLE_3D || gcdENABLE_VG) -+/* Copy surface. */ -+gceSTATUS -+gcoSURF_Copy( -+ IN gcoSURF Surface, -+ IN gcoSURF Source -+ ); -+ -+/* Set number of samples for a gcoSURF object. */ -+gceSTATUS -+gcoSURF_SetSamples( -+ IN gcoSURF Surface, -+ IN gctUINT Samples -+ ); -+ -+/* Get the number of samples per pixel. */ -+gceSTATUS -+gcoSURF_GetSamples( -+ IN gcoSURF Surface, -+ OUT gctUINT_PTR Samples -+ ); -+#endif -+ -+/******************************************************************************\ -+********************************* gcoDUMP Object ******************************** -+\******************************************************************************/ -+ -+/* Construct a new gcoDUMP object. */ -+gceSTATUS -+gcoDUMP_Construct( -+ IN gcoOS Os, -+ IN gcoHAL Hal, -+ OUT gcoDUMP * Dump -+ ); -+ -+/* Destroy a gcoDUMP object. */ -+gceSTATUS -+gcoDUMP_Destroy( -+ IN gcoDUMP Dump -+ ); -+ -+/* Enable/disable dumping. */ -+gceSTATUS -+gcoDUMP_Control( -+ IN gcoDUMP Dump, -+ IN gctSTRING FileName -+ ); -+ -+gceSTATUS -+gcoDUMP_IsEnabled( -+ IN gcoDUMP Dump, -+ OUT gctBOOL * Enabled -+ ); -+ -+/* Add surface. */ -+gceSTATUS -+gcoDUMP_AddSurface( -+ IN gcoDUMP Dump, -+ IN gctINT32 Width, -+ IN gctINT32 Height, -+ IN gceSURF_FORMAT PixelFormat, -+ IN gctUINT32 Address, -+ IN gctSIZE_T ByteCount -+ ); -+ -+/* Mark the beginning of a frame. */ -+gceSTATUS -+gcoDUMP_FrameBegin( -+ IN gcoDUMP Dump -+ ); -+ -+/* Mark the end of a frame. */ -+gceSTATUS -+gcoDUMP_FrameEnd( -+ IN gcoDUMP Dump -+ ); -+ -+/* Dump data. */ -+gceSTATUS -+gcoDUMP_DumpData( -+ IN gcoDUMP Dump, -+ IN gceDUMP_TAG Type, -+ IN gctUINT32 Address, -+ IN gctSIZE_T ByteCount, -+ IN gctCONST_POINTER Data -+ ); -+ -+/* Delete an address. */ -+gceSTATUS -+gcoDUMP_Delete( -+ IN gcoDUMP Dump, -+ IN gctUINT32 Address -+ ); -+ -+/* Enable dump or not. */ -+gceSTATUS -+gcoDUMP_SetDumpFlag( -+ IN gctBOOL DumpState -+ ); -+ -+/******************************************************************************\ -+******************************* gcsRECT Structure ****************************** -+\******************************************************************************/ -+ -+/* Initialize rectangle structure. */ -+gceSTATUS -+gcsRECT_Set( -+ OUT gcsRECT_PTR Rect, -+ IN gctINT32 Left, -+ IN gctINT32 Top, -+ IN gctINT32 Right, -+ IN gctINT32 Bottom -+ ); -+ -+/* Return the width of the rectangle. */ -+gceSTATUS -+gcsRECT_Width( -+ IN gcsRECT_PTR Rect, -+ OUT gctINT32 * Width -+ ); -+ -+/* Return the height of the rectangle. */ -+gceSTATUS -+gcsRECT_Height( -+ IN gcsRECT_PTR Rect, -+ OUT gctINT32 * Height -+ ); -+ -+/* Ensure that top left corner is to the left and above the right bottom. */ -+gceSTATUS -+gcsRECT_Normalize( -+ IN OUT gcsRECT_PTR Rect -+ ); -+ -+/* Compare two rectangles. */ -+gceSTATUS -+gcsRECT_IsEqual( -+ IN gcsRECT_PTR Rect1, -+ IN gcsRECT_PTR Rect2, -+ OUT gctBOOL * Equal -+ ); -+ -+/* Compare the sizes of two rectangles. */ -+gceSTATUS -+gcsRECT_IsOfEqualSize( -+ IN gcsRECT_PTR Rect1, -+ IN gcsRECT_PTR Rect2, -+ OUT gctBOOL * EqualSize -+ ); -+ -+gceSTATUS -+gcsRECT_RelativeRotation( -+ IN gceSURF_ROTATION Orientation, -+ IN OUT gceSURF_ROTATION *Relation); -+ -+gceSTATUS -+ -+gcsRECT_Rotate( -+ -+ IN OUT gcsRECT_PTR Rect, -+ -+ IN gceSURF_ROTATION Rotation, -+ -+ IN gceSURF_ROTATION toRotation, -+ -+ IN gctINT32 SurfaceWidth, -+ -+ IN gctINT32 SurfaceHeight -+ -+ ); -+ -+/******************************************************************************\ -+**************************** gcsBOUNDARY Structure ***************************** -+\******************************************************************************/ -+ -+typedef struct _gcsBOUNDARY -+{ -+ gctINT x; -+ gctINT y; -+ gctINT width; -+ gctINT height; -+} -+gcsBOUNDARY; -+ -+/******************************************************************************\ -+********************************* gcoHEAP Object ******************************** -+\******************************************************************************/ -+ -+typedef struct _gcoHEAP * gcoHEAP; -+ -+/* Construct a new gcoHEAP object. */ -+gceSTATUS -+gcoHEAP_Construct( -+ IN gcoOS Os, -+ IN gctSIZE_T AllocationSize, -+ OUT gcoHEAP * Heap -+ ); -+ -+/* Destroy an gcoHEAP object. */ -+gceSTATUS -+gcoHEAP_Destroy( -+ IN gcoHEAP Heap -+ ); -+ -+/* Allocate memory. */ -+gceSTATUS -+gcoHEAP_Allocate( -+ IN gcoHEAP Heap, -+ IN gctSIZE_T Bytes, -+ OUT gctPOINTER * Node -+ ); -+ -+gceSTATUS -+gcoHEAP_GetMemorySize( -+ IN gcoHEAP Heap, -+ IN gctPOINTER Memory, -+ OUT gctSIZE_T_PTR MemorySize -+ ); -+ -+/* Free memory. */ -+gceSTATUS -+gcoHEAP_Free( -+ IN gcoHEAP Heap, -+ IN gctPOINTER Node -+ ); -+ -+#if (VIVANTE_PROFILER || gcdDEBUG) -+/* Profile the heap. */ -+gceSTATUS -+gcoHEAP_ProfileStart( -+ IN gcoHEAP Heap -+ ); -+ -+gceSTATUS -+gcoHEAP_ProfileEnd( -+ IN gcoHEAP Heap, -+ IN gctCONST_STRING Title -+ ); -+#endif -+ -+ -+/******************************************************************************\ -+******************************* Debugging Macros ******************************* -+\******************************************************************************/ -+ -+void -+gcoOS_SetDebugLevel( -+ IN gctUINT32 Level -+ ); -+ -+void -+gcoOS_GetDebugLevel( -+ OUT gctUINT32_PTR DebugLevel -+ ); -+ -+void -+gcoOS_SetDebugZone( -+ IN gctUINT32 Zone -+ ); -+ -+void -+gcoOS_GetDebugZone( -+ IN gctUINT32 Zone, -+ OUT gctUINT32_PTR DebugZone -+ ); -+ -+void -+gcoOS_SetDebugLevelZone( -+ IN gctUINT32 Level, -+ IN gctUINT32 Zone -+ ); -+ -+void -+gcoOS_SetDebugZones( -+ IN gctUINT32 Zones, -+ IN gctBOOL Enable -+ ); -+ -+void -+gcoOS_SetDebugFile( -+ IN gctCONST_STRING FileName -+ ); -+ -+gctFILE -+gcoOS_ReplaceDebugFile( -+ IN gctFILE fp -+ ); -+ -+void -+gcoOS_SysTraceBegin( -+ IN gctCONST_STRING FuncName -+ ); -+ -+void -+gcoOS_SysTraceEnd( -+ IN void); -+ -+/******************************************************************************* -+** -+** gcmFATAL -+** -+** Print a message to the debugger and execute a break point. -+** -+** ARGUMENTS: -+** -+** message Message. -+** ... Optional arguments. -+*/ -+ -+void -+gckOS_DebugFatal( -+ IN gctCONST_STRING Message, -+ ... -+ ); -+ -+void -+gcoOS_DebugFatal( -+ IN gctCONST_STRING Message, -+ ... -+ ); -+ -+#if gcmIS_DEBUG(gcdDEBUG_FATAL) -+# define gcmFATAL gcoOS_DebugFatal -+# define gcmkFATAL gckOS_DebugFatal -+#elif gcdHAS_ELLIPSIS -+# define gcmFATAL(...) -+# define gcmkFATAL(...) -+#else -+ gcmINLINE static void -+ __dummy_fatal( -+ IN gctCONST_STRING Message, -+ ... -+ ) -+ { -+ } -+# define gcmFATAL __dummy_fatal -+# define gcmkFATAL __dummy_fatal -+#endif -+ -+#define gcmENUM2TEXT(e) case e: return #e -+ -+/******************************************************************************* -+** -+** gcmTRACE -+** -+** Print a message to the debugfer if the correct level has been set. In -+** retail mode this macro does nothing. -+** -+** ARGUMENTS: -+** -+** level Level of message. -+** message Message. -+** ... Optional arguments. -+*/ -+#define gcvLEVEL_NONE -1 -+#define gcvLEVEL_ERROR 0 -+#define gcvLEVEL_WARNING 1 -+#define gcvLEVEL_INFO 2 -+#define gcvLEVEL_VERBOSE 3 -+ -+void -+gckOS_DebugTrace( -+ IN gctUINT32 Level, -+ IN gctCONST_STRING Message, -+ ... -+ ); -+ -+void -+gckOS_DebugTraceN( -+ IN gctUINT32 Level, -+ IN gctUINT ArgumentSize, -+ IN gctCONST_STRING Message, -+ ... -+ ); -+ -+void -+gcoOS_DebugTrace( -+ IN gctUINT32 Level, -+ IN gctCONST_STRING Message, -+ ... -+ ); -+ -+#if gcmIS_DEBUG(gcdDEBUG_TRACE) -+# define gcmTRACE gcoOS_DebugTrace -+# define gcmkTRACE gckOS_DebugTrace -+# define gcmkTRACE_N gckOS_DebugTraceN -+#elif gcdHAS_ELLIPSIS -+# define gcmTRACE(...) -+# define gcmkTRACE(...) -+# define gcmkTRACE_N(...) -+#else -+ gcmINLINE static void -+ __dummy_trace( -+ IN gctUINT32 Level, -+ IN gctCONST_STRING Message, -+ ... -+ ) -+ { -+ } -+ -+ gcmINLINE static void -+ __dummy_trace_n( -+ IN gctUINT32 Level, -+ IN gctUINT ArgumentSize, -+ IN gctCONST_STRING Message, -+ ... -+ ) -+ { -+ } -+ -+# define gcmTRACE __dummy_trace -+# define gcmkTRACE __dummy_trace -+# define gcmkTRACE_N __dummy_trace_n -+#endif -+ -+/* Zones common for kernel and user. */ -+#define gcvZONE_OS (1 << 0) -+#define gcvZONE_HARDWARE (1 << 1) -+#define gcvZONE_HEAP (1 << 2) -+#define gcvZONE_SIGNAL (1 << 27) -+ -+/* Kernel zones. */ -+#define gcvZONE_KERNEL (1 << 3) -+#define gcvZONE_VIDMEM (1 << 4) -+#define gcvZONE_COMMAND (1 << 5) -+#define gcvZONE_DRIVER (1 << 6) -+#define gcvZONE_CMODEL (1 << 7) -+#define gcvZONE_MMU (1 << 8) -+#define gcvZONE_EVENT (1 << 9) -+#define gcvZONE_DEVICE (1 << 10) -+#define gcvZONE_DATABASE (1 << 11) -+#define gcvZONE_INTERRUPT (1 << 12) -+#define gcvZONE_POWER (1 << 13) -+ -+/* User zones. */ -+#define gcvZONE_HAL (1 << 3) -+#define gcvZONE_BUFFER (1 << 4) -+#define gcvZONE_CONTEXT (1 << 5) -+#define gcvZONE_SURFACE (1 << 6) -+#define gcvZONE_INDEX (1 << 7) -+#define gcvZONE_STREAM (1 << 8) -+#define gcvZONE_TEXTURE (1 << 9) -+#define gcvZONE_2D (1 << 10) -+#define gcvZONE_3D (1 << 11) -+#define gcvZONE_COMPILER (1 << 12) -+#define gcvZONE_MEMORY (1 << 13) -+#define gcvZONE_STATE (1 << 14) -+#define gcvZONE_AUX (1 << 15) -+#define gcvZONE_VERTEX (1 << 16) -+#define gcvZONE_CL (1 << 17) -+#define gcvZONE_COMPOSITION (1 << 17) -+#define gcvZONE_VG (1 << 18) -+#define gcvZONE_IMAGE (1 << 19) -+#define gcvZONE_UTILITY (1 << 20) -+#define gcvZONE_PARAMETERS (1 << 21) -+#define gcvZONE_BUFOBJ (1 << 22) -+#define gcvZONE_SHADER (1 << 23) -+#define gcvZONE_STREAM_OUT (1 << 24) -+ -+/* API definitions. */ -+#define gcvZONE_API_HAL (1 << 28) -+#define gcvZONE_API_EGL (2 << 28) -+#define gcvZONE_API_ES11 (3 << 28) -+#define gcvZONE_API_ES20 (4 << 28) -+#define gcvZONE_API_VG11 (5 << 28) -+#define gcvZONE_API_GL (6 << 28) -+#define gcvZONE_API_DFB (7 << 28) -+#define gcvZONE_API_GDI ((gctUINT32)8 << 28) -+#define gcvZONE_API_D3D ((gctUINT32)9 << 28) -+#define gcvZONE_API_ES30 ((gctUINT32)10 << 28) -+ -+ -+#define gcmZONE_GET_API(zone) ((zone) >> 28) -+/*Set gcdZONE_MASE like 0x0 | gcvZONE_API_EGL -+will enable print EGL module debug info*/ -+#define gcdZONE_MASK 0x0FFFFFFF -+ -+/* Handy zones. */ -+#define gcvZONE_NONE 0 -+#define gcvZONE_ALL 0x0FFFFFFF -+ -+/*Dump API depth set 1 for API, 2 for API and API behavior*/ -+#define gcvDUMP_API_DEPTH 1 -+ -+/******************************************************************************* -+** -+** gcmTRACE_ZONE -+** -+** Print a message to the debugger if the correct level and zone has been -+** set. In retail mode this macro does nothing. -+** -+** ARGUMENTS: -+** -+** Level Level of message. -+** Zone Zone of message. -+** Message Message. -+** ... Optional arguments. -+*/ -+ -+void -+gckOS_DebugTraceZone( -+ IN gctUINT32 Level, -+ IN gctUINT32 Zone, -+ IN gctCONST_STRING Message, -+ ... -+ ); -+ -+void -+gckOS_DebugTraceZoneN( -+ IN gctUINT32 Level, -+ IN gctUINT32 Zone, -+ IN gctUINT ArgumentSize, -+ IN gctCONST_STRING Message, -+ ... -+ ); -+ -+void -+gcoOS_DebugTraceZone( -+ IN gctUINT32 Level, -+ IN gctUINT32 Zone, -+ IN gctCONST_STRING Message, -+ ... -+ ); -+ -+#if gcmIS_DEBUG(gcdDEBUG_TRACE) -+# define gcmTRACE_ZONE gcoOS_DebugTraceZone -+# define gcmkTRACE_ZONE gckOS_DebugTraceZone -+# define gcmkTRACE_ZONE_N gckOS_DebugTraceZoneN -+#elif gcdHAS_ELLIPSIS -+# define gcmTRACE_ZONE(...) -+# define gcmkTRACE_ZONE(...) -+# define gcmkTRACE_ZONE_N(...) -+#else -+ gcmINLINE static void -+ __dummy_trace_zone( -+ IN gctUINT32 Level, -+ IN gctUINT32 Zone, -+ IN gctCONST_STRING Message, -+ ... -+ ) -+ { -+ } -+ -+ gcmINLINE static void -+ __dummy_trace_zone_n( -+ IN gctUINT32 Level, -+ IN gctUINT32 Zone, -+ IN gctUINT ArgumentSize, -+ IN gctCONST_STRING Message, -+ ... -+ ) -+ { -+ } -+ -+# define gcmTRACE_ZONE __dummy_trace_zone -+# define gcmkTRACE_ZONE __dummy_trace_zone -+# define gcmkTRACE_ZONE_N __dummy_trace_zone_n -+#endif -+ -+/******************************************************************************* -+** -+** gcmDEBUG_ONLY -+** -+** Execute a statement or function only in DEBUG mode. -+** -+** ARGUMENTS: -+** -+** f Statement or function to execute. -+*/ -+#if gcmIS_DEBUG(gcdDEBUG_CODE) -+# define gcmDEBUG_ONLY(f) f -+#else -+# define gcmDEBUG_ONLY(f) -+#endif -+ -+/******************************************************************************* -+** -+** gcmSTACK_PUSH -+** gcmSTACK_POP -+** gcmSTACK_DUMP -+** -+** Push or pop a function with entry arguments on the trace stack. -+** -+** ARGUMENTS: -+** -+** Function Name of function. -+** Line Line number. -+** Text Optional text. -+** ... Optional arguments for text. -+*/ -+#if gcmIS_DEBUG(gcdDEBUG_STACK) -+ void gcoOS_StackPush(IN gctINT8_PTR Identity, IN gctCONST_STRING Function, IN gctINT Line, IN gctCONST_STRING Text, ...); -+ void gcoOS_StackPop(IN gctINT8_PTR Identity, IN gctCONST_STRING Function); -+ void gcoOS_StackDump(void); -+ void gcoOS_StackRemove(IN gctHANDLE Thread); -+ -+# define gcmSTACK_PUSH gcoOS_StackPush -+# define gcmSTACK_POP gcoOS_StackPop -+# define gcmSTACK_DUMP gcoOS_StackDump -+# define gcmSTACK_REMOVE gcoOS_StackRemove -+#elif gcdHAS_ELLIPSIS -+# define gcmSTACK_PUSH(...) do { } while (0) -+# define gcmSTACK_POP(...) do { } while (0) -+# define gcmSTACK_DUMP() do { } while (0) -+# define gcmSTACK_REMOVE(...) do { } while (0) -+#else -+ gcmINLINE static void -+ __dummy_stack_push( -+ IN gctCONST_STRING Function, -+ IN gctINT Line, -+ IN gctCONST_STRING Text, ... -+ ) -+ { -+ } -+# define gcmSTACK_PUSH __dummy_stack_push -+# define gcmSTACK_POP(a,b) do { } while (0) -+# define gcmSTACK_DUMP() do { } while (0) -+# define gcmSTACK_REMOVE(a) do { } while (0) -+#endif -+ -+/******************************************************************************\ -+******************************** Binary Trace ********************************** -+\******************************************************************************/ -+typedef struct _gcsBINARY_TRACE_MESSAGE * gcsBINARY_TRACE_MESSAGE_PTR; -+typedef struct _gcsBINARY_TRACE_MESSAGE -+{ -+ gctUINT32 signature; -+ gctUINT32 pid; -+ gctUINT32 tid; -+ gctUINT32 line; -+ gctUINT32 numArguments; -+ gctUINT8 payload; -+} -+gcsBINARY_TRACE_MESSAGE; -+ -+#define gcdBINARY_TRACE_MESSAGE_SIZE 240 -+ -+#if gcdBINARY_TRACE -+ void -+ gcoOS_BinaryTrace( -+ IN gctCONST_STRING Function, -+ IN gctINT Line, -+ IN gctCONST_STRING Text OPTIONAL, -+ ... -+ ); -+ -+ void -+ gckOS_BinaryTrace( -+ IN gctCONST_STRING Function, -+ IN gctINT Line, -+ IN gctCONST_STRING Text OPTIONAL, -+ ... -+ ); -+ -+# define gcmBINARY_TRACE gcoOS_BinaryTrace -+# define gcmkBINARY_TRACE gckOS_BinaryTrace -+#elif gcdHAS_ELLIPSIS -+# define gcmBINARY_TRACE(Function, Line, Text, ...) -+# define gcmkBINARY_TRACE(Function, Line, Text, ...) -+#else -+ gcmINLINE static void -+ __dummy_binary_trace( -+ IN gctCONST_STRING Function, -+ IN gctINT Line, -+ IN gctCONST_STRING Text, -+ ) -+ { -+ } -+ -+# define gcmBINARY_TRACE __dummy_binary_trace -+# define gcmkBINARY_TRACE __dummy_binary_trace -+#endif -+ -+/******************************************************************************\ -+******************************** Logging Macros ******************************** -+\******************************************************************************/ -+ -+#define gcdHEADER_LEVEL gcvLEVEL_VERBOSE -+ -+#ifndef gcdEMPTY_HEADER_FOOTER -+#define gcdEMPTY_HEADER_FOOTER 0 -+#endif -+ -+#if gcdENABLE_PROFILING -+void -+gcoOS_ProfileDB( -+ IN gctCONST_STRING Function, -+ IN OUT gctBOOL_PTR Initialized -+ ); -+ -+#define gcmHEADER() \ -+ gctINT8 __user__ = 1; \ -+ static gctBOOL __profile__initialized__ = gcvFALSE; \ -+ gcmSTACK_PUSH(&__user__, __FUNCTION__, __LINE__, gcvNULL, gcvNULL); \ -+ gcoOS_ProfileDB(__FUNCTION__, &__profile__initialized__) -+#define gcmHEADER_ARG(...) \ -+ gctINT8 __user__ = 1; \ -+ static gctBOOL __profile__initialized__ = gcvFALSE; \ -+ gcmSTACK_PUSH(&__user__, __FUNCTION__, __LINE__, Text, __VA_ARGS__); \ -+ gcoOS_ProfileDB(__FUNCTION__, &__profile__initialized__) -+#define gcmFOOTER() \ -+ gcmSTACK_POP(&__user__, __FUNCTION__); \ -+ gcoOS_ProfileDB(__FUNCTION__, gcvNULL) -+#define gcmFOOTER_NO() \ -+ gcmSTACK_POP(&__user__, __FUNCTION__); \ -+ gcoOS_ProfileDB(__FUNCTION__, gcvNULL) -+#define gcmFOOTER_ARG(...) \ -+ gcmSTACK_POP(&__user__, __FUNCTION__); \ -+ gcoOS_ProfileDB(__FUNCTION__, gcvNULL) -+#define gcmFOOTER_KILL() \ -+ gcmSTACK_POP(&__user__, __FUNCTION__); \ -+ gcoOS_ProfileDB(gcvNULL, gcvNULL) -+ -+#else /* gcdENABLE_PROFILING */ -+ -+#ifdef gcdFSL_REL_BUILD -+#define gcmHEADER() -+#elif gcdEMPTY_HEADER_FOOTER -+# define gcmHEADER() -+#elif gcdHAS_ELLIPSIS -+#define gcmHEADER() \ -+ gctINT8 __user__ = 1; \ -+ gctINT8_PTR __user_ptr__ = &__user__; \ -+ gcmSTACK_PUSH(__user_ptr__, __FUNCTION__, __LINE__, gcvNULL, gcvNULL); \ -+ gcmBINARY_TRACE(__FUNCTION__, __LINE__, gcvNULL, gcvNULL); \ -+ gcmTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \ -+ "++%s(%d)", __FUNCTION__, __LINE__) -+#else -+ gcmINLINE static void -+ __dummy_header(void) -+ { -+ } -+# define gcmHEADER __dummy_header -+#endif -+ -+#ifdef gcdFSL_REL_BUILD -+#define gcmHEADER_ARG(Text, ...) -+#elif gcdHAS_ELLIPSIS -+#if gcdEMPTY_HEADER_FOOTER -+# define gcmHEADER_ARG(Text, ...) -+#else -+# define gcmHEADER_ARG(Text, ...) \ -+ gctINT8 __user__ = 1; \ -+ gctINT8_PTR __user_ptr__ = &__user__; \ -+ gcmSTACK_PUSH(__user_ptr__, __FUNCTION__, __LINE__, Text, __VA_ARGS__); \ -+ gcmBINARY_TRACE(__FUNCTION__, __LINE__, Text, __VA_ARGS__); \ -+ gcmTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \ -+ "++%s(%d): " Text, __FUNCTION__, __LINE__, __VA_ARGS__) -+#endif -+#else -+ gcmINLINE static void -+ __dummy_header_arg( -+ IN gctCONST_STRING Text, -+ ... -+ ) -+ { -+ } -+# define gcmHEADER_ARG __dummy_header_arg -+#endif -+ -+#ifdef gcdFSL_REL_BUILD -+# define gcmFOOTER() -+#elif gcdEMPTY_HEADER_FOOTER -+# define gcmFOOTER() -+#elif gcdHAS_ELLIPSIS -+# define gcmFOOTER() \ -+ gcmSTACK_POP(__user_ptr__, __FUNCTION__); \ -+ gcmBINARY_TRACE(__FUNCTION__, __LINE__, gcvNULL, gcvNULL); \ -+ gcmTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \ -+ "--%s(%d): status=%d(%s)", \ -+ __FUNCTION__, __LINE__, \ -+ status, gcoOS_DebugStatus2Name(status)); \ -+ *__user_ptr__ -= 1 -+#else -+ gcmINLINE static void -+ __dummy_footer(void) -+ { -+ } -+# define gcmFOOTER __dummy_footer -+#endif -+ -+#ifdef gcdFSL_REL_BUILD -+#define gcmFOOTER_NO() -+#elif gcdEMPTY_HEADER_FOOTER -+# define gcmFOOTER_NO() -+#elif gcdHAS_ELLIPSIS -+#define gcmFOOTER_NO() \ -+ gcmSTACK_POP(__user_ptr__, __FUNCTION__); \ -+ gcmBINARY_TRACE(__FUNCTION__, __LINE__, gcvNULL, gcvNULL); \ -+ gcmTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \ -+ "--%s(%d)", __FUNCTION__, __LINE__); \ -+ *__user_ptr__ -= 1 -+#else -+ gcmINLINE static void -+ __dummy_footer_no(void) -+ { -+ } -+# define gcmFOOTER_NO __dummy_footer_no -+#endif -+ -+#ifdef gcdFSL_REL_BUILD -+#define gcmFOOTER_KILL() -+#elif gcdEMPTY_HEADER_FOOTER -+# define gcmFOOTER_KILL() -+#elif gcdHAS_ELLIPSIS -+#define gcmFOOTER_KILL() \ -+ gcmSTACK_POP(__user_ptr__, __FUNCTION__); \ -+ gcmBINARY_TRACE(__FUNCTION__, __LINE__, gcvNULL, gcvNULL); \ -+ gcmTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \ -+ "--%s(%d)", __FUNCTION__, __LINE__); \ -+ *__user_ptr__ -= 1 -+#else -+ gcmINLINE static void -+ __dummy_footer_kill(void) -+ { -+ } -+# define gcmFOOTER_KILL __dummy_footer_kill -+#endif -+ -+#ifdef gcdFSL_REL_BUILD -+# define gcmFOOTER_ARG(Text, ...) -+#elif gcdHAS_ELLIPSIS -+#if gcdEMPTY_HEADER_FOOTER -+# define gcmFOOTER_ARG(Text, ...) -+#else -+# define gcmFOOTER_ARG(Text, ...) \ -+ gcmSTACK_POP(__user_ptr__, __FUNCTION__); \ -+ gcmBINARY_TRACE(__FUNCTION__, __LINE__, Text, __VA_ARGS__); \ -+ gcmTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \ -+ "--%s(%d): " Text, __FUNCTION__, __LINE__, __VA_ARGS__); \ -+ *__user_ptr__ -= 1 -+#endif -+#else -+ gcmINLINE static void -+ __dummy_footer_arg( -+ IN gctCONST_STRING Text, -+ ... -+ ) -+ { -+ } -+# define gcmFOOTER_ARG __dummy_footer_arg -+#endif -+ -+#endif /* gcdENABLE_PROFILING */ -+ -+#ifdef gcdFSL_REL_BUILD -+#define gcmkHEADER() -+#elif gcdHAS_ELLIPSIS -+#define gcmkHEADER() \ -+ gctINT8 __kernel__ = 1; \ -+ gctINT8_PTR __kernel_ptr__ = &__kernel__; \ -+ gcmkBINARY_TRACE(__FUNCTION__, __LINE__, gcvNULL, gcvNULL); \ -+ gcmkTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \ -+ "++%s(%d)", __FUNCTION__, __LINE__) -+#else -+ gcmINLINE static void -+ __dummy_kheader(void) -+ { -+ } -+# define gcmkHEADER __dummy_kheader -+#endif -+ -+#ifdef gcdFSL_REL_BUILD -+# define gcmkHEADER_ARG(Text, ...) -+#elif gcdHAS_ELLIPSIS -+# define gcmkHEADER_ARG(Text, ...) \ -+ gctINT8 __kernel__ = 1; \ -+ gctINT8_PTR __kernel_ptr__ = &__kernel__; \ -+ gcmkBINARY_TRACE(__FUNCTION__, __LINE__, Text, __VA_ARGS__); \ -+ gcmkTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \ -+ "++%s(%d): " Text, __FUNCTION__, __LINE__, __VA_ARGS__) -+#else -+ gcmINLINE static void -+ __dummy_kheader_arg( -+ IN gctCONST_STRING Text, -+ ... -+ ) -+ { -+ } -+# define gcmkHEADER_ARG __dummy_kheader_arg -+#endif -+ -+#ifdef gcdFSL_REL_BUILD -+#define gcmkFOOTER() -+#elif gcdHAS_ELLIPSIS -+#define gcmkFOOTER() \ -+ gcmkBINARY_TRACE(__FUNCTION__, __LINE__, gcvNULL, status); \ -+ gcmkTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \ -+ "--%s(%d): status=%d(%s)", \ -+ __FUNCTION__, __LINE__, status, gckOS_DebugStatus2Name(status)); \ -+ *__kernel_ptr__ -= 1 -+#else -+ gcmINLINE static void -+ __dummy_kfooter(void) -+ { -+ } -+# define gcmkFOOTER __dummy_kfooter -+#endif -+ -+#ifdef gcdFSL_REL_BUILD -+#define gcmkFOOTER_NO() -+#elif gcdHAS_ELLIPSIS -+#define gcmkFOOTER_NO() \ -+ gcmkBINARY_TRACE(__FUNCTION__, __LINE__, gcvNULL, gcvNULL); \ -+ gcmkTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \ -+ "--%s(%d)", __FUNCTION__, __LINE__); \ -+ *__kernel_ptr__ -= 1 -+#else -+ gcmINLINE static void -+ __dummy_kfooter_no(void) -+ { -+ } -+# define gcmkFOOTER_NO __dummy_kfooter_no -+#endif -+ -+#ifdef gcdFSL_REL_BUILD -+# define gcmkFOOTER_ARG(Text, ...) -+#elif gcdHAS_ELLIPSIS -+# define gcmkFOOTER_ARG(Text, ...) \ -+ gcmkBINARY_TRACE(__FUNCTION__, __LINE__, Text, __VA_ARGS__); \ -+ gcmkTRACE_ZONE(gcdHEADER_LEVEL, _GC_OBJ_ZONE, \ -+ "--%s(%d): " Text, \ -+ __FUNCTION__, __LINE__, __VA_ARGS__); \ -+ *__kernel_ptr__ -= 1 -+#else -+ gcmINLINE static void -+ __dummy_kfooter_arg( -+ IN gctCONST_STRING Text, -+ ... -+ ) -+ { -+ } -+# define gcmkFOOTER_ARG __dummy_kfooter_arg -+#endif -+ -+#define gcmOPT_VALUE(ptr) (((ptr) == gcvNULL) ? 0 : *(ptr)) -+#define gcmOPT_VALUE_INDEX(ptr, index) (((ptr) == gcvNULL) ? 0 : ptr[index]) -+#define gcmOPT_POINTER(ptr) (((ptr) == gcvNULL) ? gcvNULL : *(ptr)) -+#define gcmOPT_STRING(ptr) (((ptr) == gcvNULL) ? "(nil)" : (ptr)) -+ -+void -+gckOS_Print( -+ IN gctCONST_STRING Message, -+ ... -+ ); -+ -+void -+gckOS_PrintN( -+ IN gctUINT ArgumentSize, -+ IN gctCONST_STRING Message, -+ ... -+ ); -+ -+void -+gckOS_CopyPrint( -+ IN gctCONST_STRING Message, -+ ... -+ ); -+ -+void -+gcoOS_Print( -+ IN gctCONST_STRING Message, -+ ... -+ ); -+ -+#define gcmPRINT gcoOS_Print -+#define gcmkPRINT gckOS_Print -+#define gcmkPRINT_N gckOS_PrintN -+ -+#if gcdPRINT_VERSION -+# define gcmPRINT_VERSION() do { \ -+ _gcmPRINT_VERSION(gcm); \ -+ gcmSTACK_DUMP(); \ -+ } while (0) -+# define gcmkPRINT_VERSION() _gcmPRINT_VERSION(gcmk) -+# define _gcmPRINT_VERSION(prefix) \ -+ prefix##TRACE(gcvLEVEL_ERROR, \ -+ "Vivante HAL version %d.%d.%d build %d %s %s", \ -+ gcvVERSION_MAJOR, gcvVERSION_MINOR, gcvVERSION_PATCH, \ -+ gcvVERSION_BUILD, gcvVERSION_DATE, gcvVERSION_TIME ) -+#else -+# define gcmPRINT_VERSION() do { gcmSTACK_DUMP(); } while (gcvFALSE) -+# define gcmkPRINT_VERSION() do { } while (gcvFALSE) -+#endif -+ -+typedef enum _gceDUMP_BUFFER -+{ -+ gceDUMP_BUFFER_CONTEXT, -+ gceDUMP_BUFFER_USER, -+ gceDUMP_BUFFER_KERNEL, -+ gceDUMP_BUFFER_LINK, -+ gceDUMP_BUFFER_WAITLINK, -+ gceDUMP_BUFFER_FROM_USER, -+} -+gceDUMP_BUFFER; -+ -+void -+gckOS_DumpBuffer( -+ IN gckOS Os, -+ IN gctPOINTER Buffer, -+ IN gctUINT Size, -+ IN gceDUMP_BUFFER Type, -+ IN gctBOOL CopyMessage -+ ); -+ -+#define gcmkDUMPBUFFER gckOS_DumpBuffer -+ -+#if gcdDUMP_COMMAND -+# define gcmkDUMPCOMMAND(Os, Buffer, Size, Type, CopyMessage) \ -+ gcmkDUMPBUFFER(Os, Buffer, Size, Type, CopyMessage) -+#else -+# define gcmkDUMPCOMMAND(Os, Buffer, Size, Type, CopyMessage) -+#endif -+ -+#if gcmIS_DEBUG(gcdDEBUG_CODE) -+ -+void -+gckOS_DebugFlush( -+ gctCONST_STRING CallerName, -+ gctUINT LineNumber, -+ gctUINT32 DmaAddress -+ ); -+ -+# define gcmkDEBUGFLUSH(DmaAddress) \ -+ gckOS_DebugFlush(__FUNCTION__, __LINE__, DmaAddress) -+#else -+# define gcmkDEBUGFLUSH(DmaAddress) -+#endif -+ -+/******************************************************************************* -+** -+** gcmDUMP_FRAMERATE -+** -+** Print average frame rate -+** -+*/ -+#if gcdDUMP_FRAMERATE -+ gceSTATUS -+ gcfDumpFrameRate( -+ void -+ ); -+# define gcmDUMP_FRAMERATE gcfDumpFrameRate -+#elif gcdHAS_ELLIPSIS -+# define gcmDUMP_FRAMERATE(...) -+#else -+ gcmINLINE static void -+ __dummy_dump_frame_rate( -+ void -+ ) -+ { -+ } -+# define gcmDUMP_FRAMERATE __dummy_dump_frame_rate -+#endif -+ -+ -+/******************************************************************************* -+** -+** gcmDUMP -+** -+** Print a dump message. -+** -+** ARGUMENTS: -+** -+** gctSTRING Message. -+** -+** ... Optional arguments. -+*/ -+#if gcdDUMP -+ gceSTATUS -+ gcfDump( -+ IN gcoOS Os, -+ IN gctCONST_STRING String, -+ ... -+ ); -+# define gcmDUMP gcfDump -+#elif gcdHAS_ELLIPSIS -+# define gcmDUMP(...) -+#else -+ gcmINLINE static void -+ __dummy_dump( -+ IN gcoOS Os, -+ IN gctCONST_STRING Message, -+ ... -+ ) -+ { -+ } -+# define gcmDUMP __dummy_dump -+#endif -+ -+/******************************************************************************* -+** -+** gcmDUMP_DATA -+** -+** Add data to the dump. -+** -+** ARGUMENTS: -+** -+** gctSTRING Tag -+** Tag for dump. -+** -+** gctPOINTER Logical -+** Logical address of buffer. -+** -+** gctSIZE_T Bytes -+** Number of bytes. -+*/ -+ -+#if gcdDUMP || gcdDUMP_COMMAND -+ gceSTATUS -+ gcfDumpData( -+ IN gcoOS Os, -+ IN gctSTRING Tag, -+ IN gctPOINTER Logical, -+ IN gctSIZE_T Bytes -+ ); -+# define gcmDUMP_DATA gcfDumpData -+#elif gcdHAS_ELLIPSIS -+# define gcmDUMP_DATA(...) -+#else -+ gcmINLINE static void -+ __dummy_dump_data( -+ IN gcoOS Os, -+ IN gctSTRING Tag, -+ IN gctPOINTER Logical, -+ IN gctSIZE_T Bytes -+ ) -+ { -+ } -+# define gcmDUMP_DATA __dummy_dump_data -+#endif -+ -+/******************************************************************************* -+** -+** gcmDUMP_BUFFER -+** -+** Print a buffer to the dump. -+** -+** ARGUMENTS: -+** -+** gctSTRING Tag -+** Tag for dump. -+** -+** gctUINT32 Physical -+** Physical address of buffer. -+** -+** gctPOINTER Logical -+** Logical address of buffer. -+** -+** gctUINT32 Offset -+** Offset into buffer. -+** -+** gctSIZE_T Bytes -+** Number of bytes. -+*/ -+ -+#if gcdDUMP || gcdDUMP_COMMAND -+gceSTATUS -+gcfDumpBuffer( -+ IN gcoOS Os, -+ IN gctSTRING Tag, -+ IN gctUINT32 Physical, -+ IN gctPOINTER Logical, -+ IN gctUINT32 Offset, -+ IN gctSIZE_T Bytes -+ ); -+# define gcmDUMP_BUFFER gcfDumpBuffer -+#elif gcdHAS_ELLIPSIS -+# define gcmDUMP_BUFFER(...) -+#else -+ gcmINLINE static void -+ __dummy_dump_buffer( -+ IN gcoOS Os, -+ IN gctSTRING Tag, -+ IN gctUINT32 Physical, -+ IN gctPOINTER Logical, -+ IN gctUINT32 Offset, -+ IN gctSIZE_T Bytes -+ ) -+ { -+ } -+# define gcmDUMP_BUFFER __dummy_dump_buffer -+#endif -+ -+/******************************************************************************* -+** -+** gcmDUMP_API -+** -+** Print a dump message for a high level API prefixed by the function name. -+** -+** ARGUMENTS: -+** -+** gctSTRING Message. -+** -+** ... Optional arguments. -+*/ -+gceSTATUS gcfDumpApi(IN gctCONST_STRING String, ...); -+#if gcdDUMP_API -+# define gcmDUMP_API gcfDumpApi -+#elif gcdHAS_ELLIPSIS -+# define gcmDUMP_API(...) -+#else -+ gcmINLINE static void -+ __dummy_dump_api( -+ IN gctCONST_STRING Message, -+ ... -+ ) -+ { -+ } -+# define gcmDUMP_API __dummy_dump_api -+#endif -+ -+/******************************************************************************* -+** -+** gcmDUMP_API_ARRAY -+** -+** Print an array of data. -+** -+** ARGUMENTS: -+** -+** gctUINT32_PTR Pointer to array. -+** gctUINT32 Size. -+*/ -+gceSTATUS gcfDumpArray(IN gctCONST_POINTER Data, IN gctUINT32 Size); -+#if gcdDUMP_API -+# define gcmDUMP_API_ARRAY gcfDumpArray -+#elif gcdHAS_ELLIPSIS -+# define gcmDUMP_API_ARRAY(...) -+#else -+ gcmINLINE static void -+ __dummy_dump_api_array( -+ IN gctCONST_POINTER Data, -+ IN gctUINT32 Size -+ ) -+ { -+ } -+# define gcmDUMP_API_ARRAY __dummy_dump_api_array -+#endif -+ -+/******************************************************************************* -+** -+** gcmDUMP_API_ARRAY_TOKEN -+** -+** Print an array of data terminated by a token. -+** -+** ARGUMENTS: -+** -+** gctUINT32_PTR Pointer to array. -+** gctUINT32 Termination. -+*/ -+gceSTATUS gcfDumpArrayToken(IN gctCONST_POINTER Data, IN gctUINT32 Termination); -+#if gcdDUMP_API -+# define gcmDUMP_API_ARRAY_TOKEN gcfDumpArrayToken -+#elif gcdHAS_ELLIPSIS -+# define gcmDUMP_API_ARRAY_TOKEN(...) -+#else -+ gcmINLINE static void -+ __dummy_dump_api_array_token( -+ IN gctCONST_POINTER Data, -+ IN gctUINT32 Termination -+ ) -+ { -+ } -+# define gcmDUMP_API_ARRAY_TOKEN __dummy_dump_api_array_token -+#endif -+ -+/******************************************************************************* -+** -+** gcmDUMP_API_DATA -+** -+** Print an array of bytes. -+** -+** ARGUMENTS: -+** -+** gctCONST_POINTER Pointer to array. -+** gctSIZE_T Size. -+*/ -+gceSTATUS gcfDumpApiData(IN gctCONST_POINTER Data, IN gctSIZE_T Size); -+#if gcdDUMP_API -+# define gcmDUMP_API_DATA gcfDumpApiData -+#elif gcdHAS_ELLIPSIS -+# define gcmDUMP_API_DATA(...) -+#else -+ gcmINLINE static void -+ __dummy_dump_api_data( -+ IN gctCONST_POINTER Data, -+ IN gctSIZE_T Size -+ ) -+ { -+ } -+# define gcmDUMP_API_DATA __dummy_dump_api_data -+#endif -+ -+/******************************************************************************* -+** gcmDUMP_2D_COMMAND -+** -+** Print the 2D command buffer. -+** -+** ARGUMENTS: -+** -+** gctUINT32_PTR Pointer to the command buffer. -+** gctUINT32 Command buffer size. -+*/ -+gceSTATUS gcfDump2DCommand(IN gctUINT32_PTR Command, IN gctUINT32 Size); -+#if gcdDUMP_2D -+# define gcmDUMP_2D_COMMAND gcfDump2DCommand -+#elif gcdHAS_ELLIPSIS -+# define gcmDUMP_2D_COMMAND(...) -+#else -+ gcmINLINE static void -+ __dummy_dump_2d_command( -+ IN gctUINT32_PTR Command, -+ IN gctUINT32 Size -+ ) -+ { -+ } -+# define gcmDUMP_2D_COMMAND __dummy_dump_2d_command -+#endif -+ -+/******************************************************************************* -+** gcmDUMP_2D_SURFACE -+** -+** Print the 2D surface memory. -+** -+** ARGUMENTS: -+** -+** gctBOOL Src. -+** gctUINT32 Address. -+*/ -+gceSTATUS gcfDump2DSurface(IN gctBOOL Src, IN gctUINT32 Address); -+#if gcdDUMP_2D -+# define gcmDUMP_2D_SURFACE gcfDump2DSurface -+#elif gcdHAS_ELLIPSIS -+# define gcmDUMP_2D_SURFACE(...) -+#else -+ gcmINLINE static void -+ __dummy_dump_2d_surface( -+ IN gctBOOL Src, -+ IN gctUINT32 Address -+ ) -+ { -+ } -+# define gcmDUMP_2D_SURFACE __dummy_dump_2d_surface -+#endif -+ -+/******************************************************************************* -+** gcmDUMP_ADD_MEMORY_INFO -+** -+** Record the memory info. -+** -+** ARGUMENTS: -+** -+** gctUINT32 Address. -+** gctSIZE_T Size. -+*/ -+gceSTATUS gcfAddMemoryInfo(IN gctUINT32 GPUAddress, IN gctPOINTER Logical, IN gctUINT32 Physical, IN gctUINT32 Size); -+#if gcdDUMP_2D -+# define gcmDUMP_ADD_MEMORY_INFO gcfAddMemoryInfo -+#elif gcdHAS_ELLIPSIS -+# define gcmDUMP_ADD_MEMORY_INFO(...) -+#else -+ gcmINLINE static void -+ __dummy_dump_add_memory_info( -+ IN gctUINT32 GPUAddress, -+ IN gctPOINTER Logical, -+ IN gctUINT32 Physical, -+ IN gctUINT32 Size -+ ) -+ { -+ } -+# define gcmDUMP_ADD_MEMORY_INFO __dummy_dump_add_memory_info -+#endif -+ -+/******************************************************************************* -+** gcmDUMP_DEL_MEMORY_INFO -+** -+** Record the memory info. -+** -+** ARGUMENTS: -+** -+** gctUINT32 Address. -+*/ -+gceSTATUS gcfDelMemoryInfo(IN gctUINT32 Address); -+#if gcdDUMP_2D -+# define gcmDUMP_DEL_MEMORY_INFO gcfDelMemoryInfo -+#elif gcdHAS_ELLIPSIS -+# define gcmDUMP_DEL_MEMORY_INFO(...) -+#else -+ gcmINLINE static void -+ __dummy_dump_del_memory_info( -+ IN gctUINT32 Address -+ ) -+ { -+ } -+# define gcmDUMP_DEL_MEMORY_INFO __dummy_dump_del_memory_info -+#endif -+ -+#if gcdDUMP_2D -+extern gctPOINTER dumpMemInfoListMutex; -+extern gctBOOL dump2DFlag; -+#endif -+ -+/******************************************************************************* -+** -+** gcmTRACE_RELEASE -+** -+** Print a message to the shader debugger. -+** -+** ARGUMENTS: -+** -+** message Message. -+** ... Optional arguments. -+*/ -+ -+#define gcmTRACE_RELEASE gcoOS_DebugShaderTrace -+ -+void -+gcoOS_DebugShaderTrace( -+ IN gctCONST_STRING Message, -+ ... -+ ); -+ -+void -+gcoOS_SetDebugShaderFiles( -+ IN gctCONST_STRING VSFileName, -+ IN gctCONST_STRING FSFileName -+ ); -+ -+void -+gcoOS_SetDebugShaderFileType( -+ IN gctUINT32 ShaderType -+ ); -+ -+void -+gcoOS_EnableDebugBuffer( -+ IN gctBOOL Enable -+ ); -+ -+/******************************************************************************* -+** -+** gcmBREAK -+** -+** Break into the debugger. In retail mode this macro does nothing. -+** -+** ARGUMENTS: -+** -+** None. -+*/ -+ -+void -+gcoOS_DebugBreak( -+ void -+ ); -+ -+void -+gckOS_DebugBreak( -+ void -+ ); -+ -+#if gcmIS_DEBUG(gcdDEBUG_BREAK) -+# define gcmBREAK gcoOS_DebugBreak -+# define gcmkBREAK gckOS_DebugBreak -+#else -+# define gcmBREAK() -+# define gcmkBREAK() -+#endif -+ -+/******************************************************************************* -+** -+** gcmASSERT -+** -+** Evaluate an expression and break into the debugger if the expression -+** evaluates to false. In retail mode this macro does nothing. -+** -+** ARGUMENTS: -+** -+** exp Expression to evaluate. -+*/ -+#if gcmIS_DEBUG(gcdDEBUG_ASSERT) -+# define _gcmASSERT(prefix, exp) \ -+ do \ -+ { \ -+ if (!(exp)) \ -+ { \ -+ prefix##TRACE(gcvLEVEL_ERROR, \ -+ #prefix "ASSERT at %s(%d)", \ -+ __FUNCTION__, __LINE__); \ -+ prefix##TRACE(gcvLEVEL_ERROR, \ -+ "(%s)", #exp); \ -+ prefix##BREAK(); \ -+ } \ -+ } \ -+ while (gcvFALSE) -+# define gcmASSERT(exp) _gcmASSERT(gcm, exp) -+# define gcmkASSERT(exp) _gcmASSERT(gcmk, exp) -+#else -+# define gcmASSERT(exp) -+# define gcmkASSERT(exp) -+#endif -+ -+/******************************************************************************* -+** -+** gcmVERIFY -+** -+** Verify if an expression returns true. If the expression does not -+** evaluates to true, an assertion will happen in debug mode. -+** -+** ARGUMENTS: -+** -+** exp Expression to evaluate. -+*/ -+#if gcmIS_DEBUG(gcdDEBUG_ASSERT) -+# define gcmVERIFY(exp) gcmASSERT(exp) -+# define gcmkVERIFY(exp) gcmkASSERT(exp) -+#else -+# define gcmVERIFY(exp) exp -+# define gcmkVERIFY(exp) exp -+#endif -+ -+/******************************************************************************* -+** -+** gcmVERIFY_OK -+** -+** Verify a fucntion returns gcvSTATUS_OK. If the function does not return -+** gcvSTATUS_OK, an assertion will happen in debug mode. -+** -+** ARGUMENTS: -+** -+** func Function to evaluate. -+*/ -+ -+void -+gcoOS_Verify( -+ IN gceSTATUS status -+ ); -+ -+void -+gckOS_Verify( -+ IN gceSTATUS status -+ ); -+ -+#if gcmIS_DEBUG(gcdDEBUG_ASSERT) -+# define gcmVERIFY_OK(func) \ -+ do \ -+ { \ -+ gceSTATUS verifyStatus = func; \ -+ gcoOS_Verify(verifyStatus); \ -+ if (verifyStatus != gcvSTATUS_OK) \ -+ { \ -+ gcmTRACE( \ -+ gcvLEVEL_ERROR, \ -+ "gcmVERIFY_OK(%d): function returned %d", \ -+ __LINE__, verifyStatus \ -+ ); \ -+ } \ -+ gcmASSERT(verifyStatus == gcvSTATUS_OK); \ -+ } \ -+ while (gcvFALSE) -+# define gcmkVERIFY_OK(func) \ -+ do \ -+ { \ -+ gceSTATUS verifyStatus = func; \ -+ if (verifyStatus != gcvSTATUS_OK) \ -+ { \ -+ gcmkTRACE( \ -+ gcvLEVEL_ERROR, \ -+ "gcmkVERIFY_OK(%d): function returned %d", \ -+ __LINE__, verifyStatus \ -+ ); \ -+ } \ -+ gckOS_Verify(verifyStatus); \ -+ gcmkASSERT(verifyStatus == gcvSTATUS_OK); \ -+ } \ -+ while (gcvFALSE) -+#else -+# define gcmVERIFY_OK(func) func -+# define gcmkVERIFY_OK(func) func -+#endif -+ -+gctCONST_STRING -+gcoOS_DebugStatus2Name( -+ gceSTATUS status -+ ); -+ -+gctCONST_STRING -+gckOS_DebugStatus2Name( -+ gceSTATUS status -+ ); -+ -+/******************************************************************************* -+** -+** gcmERR_BREAK -+** -+** Executes a break statement on error. -+** -+** ASSUMPTIONS: -+** -+** 'status' variable of gceSTATUS type must be defined. -+** -+** ARGUMENTS: -+** -+** func Function to evaluate. -+*/ -+#define _gcmERR_BREAK(prefix, func) \ -+ status = func; \ -+ if (gcmIS_ERROR(status)) \ -+ { \ -+ prefix##PRINT_VERSION(); \ -+ prefix##TRACE(gcvLEVEL_ERROR, \ -+ #prefix "ERR_BREAK: status=%d(%s) @ %s(%d)", \ -+ status, gcoOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \ -+ break; \ -+ } \ -+ do { } while (gcvFALSE) -+#define _gcmkERR_BREAK(prefix, func) \ -+ status = func; \ -+ if (gcmIS_ERROR(status)) \ -+ { \ -+ prefix##PRINT_VERSION(); \ -+ prefix##TRACE(gcvLEVEL_ERROR, \ -+ #prefix "ERR_BREAK: status=%d(%s) @ %s(%d)", \ -+ status, gckOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \ -+ break; \ -+ } \ -+ do { } while (gcvFALSE) -+#define gcmERR_BREAK(func) _gcmERR_BREAK(gcm, func) -+#define gcmkERR_BREAK(func) _gcmkERR_BREAK(gcmk, func) -+ -+/******************************************************************************* -+** -+** gcmERR_RETURN -+** -+** Executes a return on error. -+** -+** ASSUMPTIONS: -+** -+** 'status' variable of gceSTATUS type must be defined. -+** -+** ARGUMENTS: -+** -+** func Function to evaluate. -+*/ -+#define _gcmERR_RETURN(prefix, func) \ -+ status = func; \ -+ if (gcmIS_ERROR(status)) \ -+ { \ -+ prefix##PRINT_VERSION(); \ -+ prefix##TRACE(gcvLEVEL_ERROR, \ -+ #prefix "ERR_RETURN: status=%d(%s) @ %s(%d)", \ -+ status, gcoOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \ -+ prefix##FOOTER(); \ -+ return status; \ -+ } \ -+ do { } while (gcvFALSE) -+#define _gcmkERR_RETURN(prefix, func) \ -+ status = func; \ -+ if (gcmIS_ERROR(status)) \ -+ { \ -+ prefix##PRINT_VERSION(); \ -+ prefix##TRACE(gcvLEVEL_ERROR, \ -+ #prefix "ERR_RETURN: status=%d(%s) @ %s(%d)", \ -+ status, gckOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \ -+ prefix##FOOTER(); \ -+ return status; \ -+ } \ -+ do { } while (gcvFALSE) -+#define gcmERR_RETURN(func) _gcmERR_RETURN(gcm, func) -+#define gcmkERR_RETURN(func) _gcmkERR_RETURN(gcmk, func) -+ -+/******************************************************************************* -+** -+** gcmONWARNING -+** -+** Jump to the error handler in case there is an error, but only report at -+** the WARNING debug level. This is for non fatal errors. -+** -+** ASSUMPTIONS: -+** -+** 'status' variable of gceSTATUS type must be defined. -+** -+** ARGUMENTS: -+** -+** func Function to evaluate. -+*/ -+#define _gcmONWARNING(prefix, func) \ -+ do \ -+ { \ -+ status = func; \ -+ if (gcmIS_ERROR(status)) \ -+ { \ -+ prefix##PRINT_VERSION(); \ -+ prefix##TRACE(gcvLEVEL_WARNING, \ -+ #prefix "ONWARNING: status=%d(%s) @ %s(%d)", \ -+ status, gcoOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \ -+ status = gcvSTATUS_WARNING; \ -+ goto OnError; \ -+ } \ -+ } \ -+ while (gcvFALSE) -+#define _gcmkONWARNING(prefix, func) \ -+ do \ -+ { \ -+ status = func; \ -+ if (gcmIS_WARNING(status)) \ -+ { \ -+ prefix##PRINT_VERSION(); \ -+ prefix##TRACE(gcvLEVEL_WARNING, \ -+ #prefix "ONWARNING: status=%d(%s) @ %s(%d)", \ -+ status, gckOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \ -+ status = gcvSTATUS_WARNING; \ -+ goto OnError; \ -+ } \ -+ } \ -+ while (gcvFALSE) -+#define gcmONWARNING(func) _gcmONWARNING(gcm, func) -+#define gcmkONWARNING(func) _gcmkONWARNING(gcmk, func) -+ -+/******************************************************************************* -+** -+** gcmONERROR -+** -+** Jump to the error handler in case there is an error. -+** -+** ASSUMPTIONS: -+** -+** 'status' variable of gceSTATUS type must be defined. -+** -+** ARGUMENTS: -+** -+** func Function to evaluate. -+*/ -+#define _gcmONERROR(prefix, func) \ -+ do \ -+ { \ -+ status = func; \ -+ if (gcmIS_WARNING(status)) \ -+ { \ -+ prefix##PRINT_VERSION(); \ -+ prefix##TRACE(gcvLEVEL_WARNING, \ -+ #prefix "ONWARNING: status=%d(%s) @ %s(%d)", \ -+ status, gcoOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \ -+ goto OnError; \ -+ } \ -+ else if (gcmIS_ERROR(status)) \ -+ { \ -+ prefix##PRINT_VERSION(); \ -+ prefix##TRACE(gcvLEVEL_ERROR, \ -+ #prefix "ONERROR: status=%d(%s) @ %s(%d)", \ -+ status, gcoOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \ -+ goto OnError; \ -+ } \ -+ } \ -+ while (gcvFALSE) -+#define _gcmkONERROR(prefix, func) \ -+ do \ -+ { \ -+ status = func; \ -+ if (gcmIS_WARNING(status)) \ -+ { \ -+ prefix##PRINT_VERSION(); \ -+ prefix##TRACE(gcvLEVEL_WARNING, \ -+ #prefix "ONWARNING: status=%d(%s) @ %s(%d)", \ -+ status, gckOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \ -+ goto OnError; \ -+ } \ -+ else if (gcmIS_ERROR(status)) \ -+ { \ -+ prefix##PRINT_VERSION(); \ -+ prefix##TRACE(gcvLEVEL_ERROR, \ -+ #prefix "ONERROR: status=%d(%s) @ %s(%d)", \ -+ status, gckOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \ -+ goto OnError; \ -+ } \ -+ } \ -+ while (gcvFALSE) -+#define gcmONERROR(func) _gcmONERROR(gcm, func) -+#define gcmkONERROR(func) _gcmkONERROR(gcmk, func) -+ -+/******************************************************************************* -+** -+** gcmkSAFECASTSIZET -+** -+** Check wether value of a gctSIZE_T varible beyond the capability -+** of 32bits GPU hardware. -+** -+** ASSUMPTIONS: -+** -+** -+** -+** ARGUMENTS: -+** -+** x A gctUINT32 variable -+** y A gctSIZE_T variable -+*/ -+#define gcmkSAFECASTSIZET(x, y) \ -+ do \ -+ { \ -+ gctUINT32 tmp = (gctUINT32)(y); \ -+ if (gcmSIZEOF(gctSIZE_T) > gcmSIZEOF(gctUINT32)) \ -+ { \ -+ gcmkASSERT(tmp <= gcvMAXUINT32); \ -+ } \ -+ (x) = tmp; \ -+ } \ -+ while (gcvFALSE) -+ -+#define gcmSAFECASTSIZET(x, y) \ -+ do \ -+ { \ -+ gctUINT32 tmp = (gctUINT32)(y); \ -+ if (gcmSIZEOF(gctSIZE_T) > gcmSIZEOF(gctUINT32)) \ -+ { \ -+ gcmASSERT(tmp <= gcvMAXUINT32); \ -+ } \ -+ (x) = tmp; \ -+ } \ -+ while (gcvFALSE) -+ -+/******************************************************************************* -+** -+** gcmVERIFY_LOCK -+** -+** Verifies whether the surface is locked. -+** -+** ARGUMENTS: -+** -+** surfaceInfo Pointer to the surface iniformational structure. -+*/ -+#define gcmVERIFY_LOCK(surfaceInfo) \ -+ if (!surfaceInfo->node.valid) \ -+ { \ -+ gcmONERROR(gcvSTATUS_MEMORY_UNLOCKED); \ -+ } \ -+ -+/******************************************************************************* -+** -+** gcmVERIFY_NODE_LOCK -+** -+** Verifies whether the surface node is locked. -+** -+** ARGUMENTS: -+** -+** surfaceInfo Pointer to the surface iniformational structure. -+*/ -+#define gcmVERIFY_NODE_LOCK(surfaceNode) \ -+ if (!(surfaceNode)->valid) \ -+ { \ -+ status = gcvSTATUS_MEMORY_UNLOCKED; \ -+ break; \ -+ } \ -+ do { } while (gcvFALSE) -+ -+/******************************************************************************* -+** -+** gcmBADOBJECT_BREAK -+** -+** Executes a break statement on bad object. -+** -+** ARGUMENTS: -+** -+** obj Object to test. -+** t Expected type of the object. -+*/ -+#define gcmBADOBJECT_BREAK(obj, t) \ -+ if ((obj == gcvNULL) \ -+ || (((gcsOBJECT *)(obj))->type != t) \ -+ ) \ -+ { \ -+ status = gcvSTATUS_INVALID_OBJECT; \ -+ break; \ -+ } \ -+ do { } while (gcvFALSE) -+ -+/******************************************************************************* -+** -+** gcmCHECK_STATUS -+** -+** Executes a break statement on error. -+** -+** ASSUMPTIONS: -+** -+** 'status' variable of gceSTATUS type must be defined. -+** -+** ARGUMENTS: -+** -+** func Function to evaluate. -+*/ -+#define _gcmCHECK_STATUS(prefix, func) \ -+ do \ -+ { \ -+ last = func; \ -+ if (gcmIS_ERROR(last)) \ -+ { \ -+ prefix##TRACE(gcvLEVEL_ERROR, \ -+ #prefix "CHECK_STATUS: status=%d(%s) @ %s(%d)", \ -+ last, gcoOS_DebugStatus2Name(last), __FUNCTION__, __LINE__); \ -+ status = last; \ -+ } \ -+ } \ -+ while (gcvFALSE) -+#define _gcmkCHECK_STATUS(prefix, func) \ -+ do \ -+ { \ -+ last = func; \ -+ if (gcmIS_ERROR(last)) \ -+ { \ -+ prefix##TRACE(gcvLEVEL_ERROR, \ -+ #prefix "CHECK_STATUS: status=%d(%s) @ %s(%d)", \ -+ last, gckOS_DebugStatus2Name(last), __FUNCTION__, __LINE__); \ -+ status = last; \ -+ } \ -+ } \ -+ while (gcvFALSE) -+#define gcmCHECK_STATUS(func) _gcmCHECK_STATUS(gcm, func) -+#define gcmkCHECK_STATUS(func) _gcmkCHECK_STATUS(gcmk, func) -+ -+/******************************************************************************* -+** -+** gcmVERIFY_ARGUMENT -+** -+** Assert if an argument does not apply to the specified expression. If -+** the argument evaluates to false, gcvSTATUS_INVALID_ARGUMENT will be -+** returned from the current function. In retail mode this macro does -+** nothing. -+** -+** ARGUMENTS: -+** -+** arg Argument to evaluate. -+*/ -+# define _gcmVERIFY_ARGUMENT(prefix, arg) \ -+ do \ -+ { \ -+ if (!(arg)) \ -+ { \ -+ prefix##TRACE(gcvLEVEL_ERROR, #prefix "VERIFY_ARGUMENT failed:"); \ -+ prefix##ASSERT(arg); \ -+ prefix##FOOTER_ARG("status=%d", gcvSTATUS_INVALID_ARGUMENT); \ -+ return gcvSTATUS_INVALID_ARGUMENT; \ -+ } \ -+ } \ -+ while (gcvFALSE) -+# define gcmVERIFY_ARGUMENT(arg) _gcmVERIFY_ARGUMENT(gcm, arg) -+# define gcmkVERIFY_ARGUMENT(arg) _gcmVERIFY_ARGUMENT(gcmk, arg) -+ -+/******************************************************************************* -+** -+** gcmDEBUG_VERIFY_ARGUMENT -+** -+** Works just like gcmVERIFY_ARGUMENT, but is only valid in debug mode. -+** Use this to verify arguments inside non-public API functions. -+*/ -+#if gcdDEBUG -+# define gcmDEBUG_VERIFY_ARGUMENT(arg) _gcmVERIFY_ARGUMENT(gcm, arg) -+# define gcmkDEBUG_VERIFY_ARGUMENT(arg) _gcmkVERIFY_ARGUMENT(gcm, arg) -+#else -+# define gcmDEBUG_VERIFY_ARGUMENT(arg) -+# define gcmkDEBUG_VERIFY_ARGUMENT(arg) -+#endif -+ -+/******************************************************************************* -+** -+** gcmVERIFY_ARGUMENT_RETURN -+** -+** Assert if an argument does not apply to the specified expression. If -+** the argument evaluates to false, gcvSTATUS_INVALID_ARGUMENT will be -+** returned from the current function. In retail mode this macro does -+** nothing. -+** -+** ARGUMENTS: -+** -+** arg Argument to evaluate. -+*/ -+# define _gcmVERIFY_ARGUMENT_RETURN(prefix, arg, value) \ -+ do \ -+ { \ -+ if (!(arg)) \ -+ { \ -+ prefix##TRACE(gcvLEVEL_ERROR, \ -+ #prefix "gcmVERIFY_ARGUMENT_RETURN failed:"); \ -+ prefix##ASSERT(arg); \ -+ prefix##FOOTER_ARG("value=%d", value); \ -+ return value; \ -+ } \ -+ } \ -+ while (gcvFALSE) -+# define gcmVERIFY_ARGUMENT_RETURN(arg, value) \ -+ _gcmVERIFY_ARGUMENT_RETURN(gcm, arg, value) -+# define gcmkVERIFY_ARGUMENT_RETURN(arg, value) \ -+ _gcmVERIFY_ARGUMENT_RETURN(gcmk, arg, value) -+ -+#define MAX_LOOP_COUNT 0x7FFFFFFF -+ -+/******************************************************************************\ -+****************************** User Debug Option ****************************** -+\******************************************************************************/ -+ -+/* User option. */ -+typedef enum _gceDEBUG_MSG -+{ -+ gcvDEBUG_MSG_NONE, -+ gcvDEBUG_MSG_ERROR, -+ gcvDEBUG_MSG_WARNING -+} -+gceDEBUG_MSG; -+ -+typedef struct _gcsUSER_DEBUG_OPTION -+{ -+ gceDEBUG_MSG debugMsg; -+} -+gcsUSER_DEBUG_OPTION; -+ -+gcsUSER_DEBUG_OPTION * -+gcGetUserDebugOption( -+ void -+ ); -+ -+#if defined(ANDROID) -+struct _gcoOS_SymbolsList -+{ -+#if gcdENABLE_3D -+ gcePATCH_ID patchId; -+#endif -+ const char * symList[10]; -+}; -+#endif -+ -+#if gcdHAS_ELLIPSIS -+#define gcmUSER_DEBUG_MSG(level, ...) \ -+ do \ -+ { \ -+ if (level <= gcGetUserDebugOption()->debugMsg) \ -+ { \ -+ gcoOS_Print(__VA_ARGS__); \ -+ } \ -+ } while (gcvFALSE) -+ -+#define gcmUSER_DEBUG_ERROR_MSG(...) gcmUSER_DEBUG_MSG(gcvDEBUG_MSG_ERROR, "Error: " __VA_ARGS__) -+#define gcmUSER_DEBUG_WARNING_MSG(...) gcmUSER_DEBUG_MSG(gcvDEBUG_MSG_WARNING, "Warring: " __VA_ARGS__) -+#else -+#define gcmUSER_DEBUG_MSG -+#define gcmUSER_DEBUG_ERROR_MSG -+#define gcmUSER_DEBUG_WARNING_MSG -+#endif -+ -+/******************************************************************************* -+** -+** A set of macros to aid state loading. -+** -+** ARGUMENTS: -+** -+** CommandBuffer Pointer to a gcoCMDBUF object. -+** StateDelta Pointer to a gcsSTATE_DELTA state delta structure. -+** Memory Destination memory pointer of gctUINT32_PTR type. -+** PartOfContext Whether or not the state is a part of the context. -+** FixedPoint Whether or not the state is of the fixed point format. -+** Count Number of consecutive states to be loaded. -+** Address State address. -+** Data Data to be set to the state. -+*/ -+ -+/*----------------------------------------------------------------------------*/ -+ -+#if gcmIS_DEBUG(gcdDEBUG_CODE) -+ -+# define gcmSTORELOADSTATE(CommandBuffer, Memory, Address, Count) \ -+ CommandBuffer->lastLoadStatePtr = gcmPTR_TO_UINT64(Memory); \ -+ CommandBuffer->lastLoadStateAddress = Address; \ -+ CommandBuffer->lastLoadStateCount = Count -+ -+# define gcmVERIFYLOADSTATE(CommandBuffer, Memory, Address) \ -+ gcmASSERT( \ -+ (gctUINT) (Memory - gcmUINT64_TO_TYPE(CommandBuffer->lastLoadStatePtr, gctUINT32_PTR) - 1) \ -+ == \ -+ (gctUINT) (Address - CommandBuffer->lastLoadStateAddress) \ -+ ); \ -+ \ -+ gcmASSERT(CommandBuffer->lastLoadStateCount > 0); \ -+ \ -+ CommandBuffer->lastLoadStateCount -= 1 -+ -+# define gcmVERIFYLOADSTATEDONE(CommandBuffer) \ -+ gcmASSERT(CommandBuffer->lastLoadStateCount == 0); -+ -+# define gcmDEFINELOADSTATEBASE() \ -+ gctUINT32_PTR LoadStateBase; -+ -+# define gcmSETLOADSTATEBASE(CommandBuffer, OutSide) \ -+ if (OutSide) \ -+ {\ -+ LoadStateBase = (gctUINT32_PTR)*OutSide; \ -+ }\ -+ else\ -+ {\ -+ LoadStateBase = (gctUINT_PTR)CommandBuffer->buffer;\ -+ } -+ -+ -+# define gcmVERIFYLOADSTATEALIGNED(CommandBuffer, Memory) \ -+ gcmASSERT(((Memory - LoadStateBase) & 1) == 0); -+ -+# define gcmUNSETLOADSTATEBASE() \ -+ LoadStateBase = LoadStateBase; -+ -+#else -+ -+# define gcmSTORELOADSTATE(CommandBuffer, Memory, Address, Count) -+# define gcmVERIFYLOADSTATE(CommandBuffer, Memory, Address) -+# define gcmVERIFYLOADSTATEDONE(CommandBuffer) -+ -+# define gcmDEFINELOADSTATEBASE() -+# define gcmSETLOADSTATEBASE(CommandBuffer, OutSide) -+# define gcmVERIFYLOADSTATEALIGNED(CommandBuffer, Memory) -+# define gcmUNSETLOADSTATEBASE() -+ -+#endif -+ -+/*----------------------------------------------------------------------------*/ -+ -+#if gcdDUMP -+# define gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, Data) \ -+ if (FixedPoint) \ -+ { \ -+ gcmDUMP(gcvNULL, "#[state.x 0x%04X 0x%08X]", \ -+ Address, Data \ -+ ); \ -+ } \ -+ else \ -+ { \ -+ gcmDUMP(gcvNULL, "#[state 0x%04X 0x%08X]", \ -+ Address, Data \ -+ ); \ -+ } -+#else -+# define gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, Data) -+#endif -+ -+#define gcmDEFINESTATEBUFFER(CommandBuffer, StateDelta, Memory, ReserveSize) \ -+ gcmDEFINESECUREUSER() \ -+ gctSIZE_T ReserveSize; \ -+ gcoCMDBUF CommandBuffer; \ -+ gctUINT32_PTR Memory; \ -+ gcsSTATE_DELTA_PTR StateDelta -+ -+#define gcmBEGINSTATEBUFFER(Hardware, CommandBuffer, StateDelta, Memory, ReserveSize) \ -+{ \ -+ gcmONERROR(gcoBUFFER_Reserve( \ -+ Hardware->buffer, ReserveSize, gcvTRUE, gcvCOMMAND_3D, &CommandBuffer \ -+ )); \ -+ \ -+ Memory = (gctUINT32_PTR) gcmUINT64_TO_PTR(CommandBuffer->lastReserve); \ -+ \ -+ StateDelta = Hardware->delta; \ -+ \ -+ gcmBEGINSECUREUSER(); \ -+} -+ -+#define gcmENDSTATEBUFFER(Hardware, CommandBuffer, Memory, ReserveSize) \ -+{ \ -+ gcmENDSECUREUSER(); \ -+ \ -+ gcmASSERT( \ -+ gcmUINT64_TO_TYPE(CommandBuffer->lastReserve, gctUINT8_PTR) + ReserveSize \ -+ == \ -+ (gctUINT8_PTR) Memory \ -+ ); \ -+} -+ -+/*----------------------------------------------------------------------------*/ -+ -+#define gcmBEGINSTATEBATCH(CommandBuffer, Memory, FixedPoint, Address, Count) \ -+{ \ -+ gcmASSERT(((Memory - gcmUINT64_TO_TYPE(CommandBuffer->lastReserve, gctUINT32_PTR)) & 1) == 0); \ -+ gcmASSERT((gctUINT32)Count <= 1024); \ -+ \ -+ gcmVERIFYLOADSTATEDONE(CommandBuffer); \ -+ \ -+ gcmSTORELOADSTATE(CommandBuffer, Memory, Address, Count); \ -+ \ -+ *Memory++ \ -+ = gcmSETFIELDVALUE(0, AQ_COMMAND_LOAD_STATE_COMMAND, OPCODE, LOAD_STATE) \ -+ | gcmSETFIELD (0, AQ_COMMAND_LOAD_STATE_COMMAND, FLOAT, FixedPoint) \ -+ | gcmSETFIELD (0, AQ_COMMAND_LOAD_STATE_COMMAND, COUNT, Count) \ -+ | gcmSETFIELD (0, AQ_COMMAND_LOAD_STATE_COMMAND, ADDRESS, Address); \ -+ \ -+ gcmSKIPSECUREUSER(); \ -+} -+ -+#define gcmENDSTATEBATCH(CommandBuffer, Memory) \ -+{ \ -+ gcmVERIFYLOADSTATEDONE(CommandBuffer); \ -+ \ -+ gcmASSERT(((Memory - gcmUINT64_TO_TYPE(CommandBuffer->lastReserve, gctUINT32_PTR)) & 1) == 0); \ -+} -+ -+/*----------------------------------------------------------------------------*/ -+ -+#define gcmSETSTATEDATA(StateDelta, CommandBuffer, Memory, FixedPoint, \ -+ Address, Data) \ -+{ \ -+ gctUINT32 __temp_data32__; \ -+ \ -+ gcmVERIFYLOADSTATE(CommandBuffer, Memory, Address); \ -+ \ -+ gcmSAFECASTSIZET(__temp_data32__, Data); \ -+ \ -+ *Memory++ = __temp_data32__; \ -+ \ -+ gcoHARDWARE_UpdateDelta( \ -+ StateDelta, Address, 0, __temp_data32__ \ -+ ); \ -+ \ -+ gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, __temp_data32__); \ -+ \ -+ gcmUPDATESECUREUSER(); \ -+} -+ -+#define gcmSETSTATEDATAWITHMASK(StateDelta, CommandBuffer, Memory, FixedPoint, \ -+ Address, Mask, Data) \ -+{ \ -+ gctUINT32 __temp_data32__; \ -+ \ -+ gcmVERIFYLOADSTATE(CommandBuffer, Memory, Address); \ -+ \ -+ __temp_data32__ = Data; \ -+ \ -+ *Memory++ = __temp_data32__; \ -+ \ -+ gcoHARDWARE_UpdateDelta( \ -+ StateDelta, Address, Mask, __temp_data32__ \ -+ ); \ -+ \ -+ gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, __temp_data32__); \ -+ \ -+ gcmUPDATESECUREUSER(); \ -+} -+ -+ -+#define gcmSETCTRLSTATE(StateDelta, CommandBuffer, Memory, Address, Data) \ -+{ \ -+ gctUINT32 __temp_data32__; \ -+ \ -+ gcmVERIFYLOADSTATE(CommandBuffer, Memory, Address); \ -+ \ -+ __temp_data32__ = Data; \ -+ \ -+ *Memory++ = __temp_data32__; \ -+ \ -+ gcmDUMPSTATEDATA(StateDelta, gcvFALSE, Address, __temp_data32__); \ -+ \ -+ gcmSKIPSECUREUSER(); \ -+} -+ -+#define gcmSETFILLER(CommandBuffer, Memory) \ -+{ \ -+ gcmVERIFYLOADSTATEDONE(CommandBuffer); \ -+ \ -+ Memory += 1; \ -+ \ -+ gcmSKIPSECUREUSER(); \ -+} -+ -+/*----------------------------------------------------------------------------*/ -+ -+#define gcmSETSINGLESTATE(StateDelta, CommandBuffer, Memory, FixedPoint, \ -+ Address, Data) \ -+{ \ -+ gcmBEGINSTATEBATCH(CommandBuffer, Memory, FixedPoint, Address, 1); \ -+ gcmSETSTATEDATA(StateDelta, CommandBuffer, Memory, FixedPoint, \ -+ Address, Data); \ -+ gcmENDSTATEBATCH(CommandBuffer, Memory); \ -+} -+ -+#define gcmSETSINGLESTATEWITHMASK(StateDelta, CommandBuffer, Memory, FixedPoint, \ -+ Address, Mask, Data) \ -+{ \ -+ gcmBEGINSTATEBATCH(CommandBuffer, Memory, FixedPoint, Address, 1); \ -+ gcmSETSTATEDATAWITHMASK(StateDelta, CommandBuffer, Memory, FixedPoint, \ -+ Address, Mask, Data); \ -+ gcmENDSTATEBATCH(CommandBuffer, Memory); \ -+} -+ -+ -+#define gcmSETSINGLECTRLSTATE(StateDelta, CommandBuffer, Memory, FixedPoint, \ -+ Address, Data) \ -+{ \ -+ gcmBEGINSTATEBATCH(CommandBuffer, Memory, FixedPoint, Address, 1); \ -+ gcmSETCTRLSTATE(StateDelta, CommandBuffer, Memory, Address, Data); \ -+ gcmENDSTATEBATCH(CommandBuffer, Memory); \ -+} -+ -+ -+ -+#define gcmSETSEMASTALLPIPE(StateDelta, CommandBuffer, Memory, Data) \ -+{ \ -+ gcmSETSINGLESTATE(StateDelta, CommandBuffer, Memory, gcvFALSE, AQSemaphoreRegAddrs, Data); \ -+ \ -+ *Memory++ = gcmSETFIELDVALUE(0, STALL_COMMAND, OPCODE, STALL); \ -+ \ -+ *Memory++ = Data; \ -+ \ -+ gcmDUMP(gcvNULL, "#[stall 0x%08X 0x%08X]", \ -+ gcmSETFIELDVALUE(0, AQ_SEMAPHORE, SOURCE, FRONT_END), \ -+ gcmSETFIELDVALUE(0, AQ_SEMAPHORE, DESTINATION, PIXEL_ENGINE)); \ -+ \ -+ gcmSKIPSECUREUSER(); \ -+} -+ -+/******************************************************************************* -+** -+** gcmSETSTARTDECOMMAND -+** -+** Form a START_DE command. -+** -+** ARGUMENTS: -+** -+** Memory Destination memory pointer of gctUINT32_PTR type. -+** Count Number of the rectangles. -+*/ -+ -+#define gcmSETSTARTDECOMMAND(Memory, Count) \ -+{ \ -+ *Memory++ \ -+ = gcmSETFIELDVALUE(0, AQ_COMMAND_START_DE_COMMAND, OPCODE, START_DE) \ -+ | gcmSETFIELD (0, AQ_COMMAND_START_DE_COMMAND, COUNT, Count) \ -+ | gcmSETFIELD (0, AQ_COMMAND_START_DE_COMMAND, DATA_COUNT, 0); \ -+ \ -+ *Memory++ = 0xDEADDEED; \ -+} -+ -+/***************************************** -+** Temp command buffer macro -+*/ -+#define gcmDEFINESTATEBUFFER_NEW(CommandBuffer, StateDelta, Memory) \ -+ gcmDEFINESECUREUSER() \ -+ gcmDEFINELOADSTATEBASE() \ -+ gcsTEMPCMDBUF CommandBuffer = gcvNULL; \ -+ gctUINT32_PTR Memory; \ -+ gcsSTATE_DELTA_PTR StateDelta -+ -+ -+#define gcmBEGINSTATEBUFFER_NEW(Hardware, CommandBuffer, StateDelta, Memory, OutSide) \ -+{ \ -+ if (OutSide) \ -+ {\ -+ Memory = (gctUINT32_PTR)*OutSide; \ -+ }\ -+ else \ -+ {\ -+ gcmONERROR(gcoBUFFER_StartTEMPCMDBUF( \ -+ Hardware->buffer, &CommandBuffer \ -+ ));\ -+ \ -+ Memory = (gctUINT32_PTR)(CommandBuffer->buffer); \ -+ \ -+ }\ -+ StateDelta = Hardware->delta; \ -+ \ -+ gcmBEGINSECUREUSER(); \ -+ gcmSETLOADSTATEBASE(CommandBuffer,OutSide);\ -+} -+ -+#define gcmENDSTATEBUFFER_NEW(Hardware, CommandBuffer, Memory, OutSide) \ -+{ \ -+ gcmENDSECUREUSER(); \ -+ \ -+ if (OutSide) \ -+ {\ -+ *OutSide = Memory; \ -+ }\ -+ else \ -+ {\ -+ CommandBuffer->currentByteSize = (gctUINT32)((gctUINT8_PTR)Memory - \ -+ (gctUINT8_PTR)CommandBuffer->buffer); \ -+ \ -+ gcmONERROR(gcoBUFFER_EndTEMPCMDBUF(Hardware->buffer));\ -+ }\ -+ gcmUNSETLOADSTATEBASE()\ -+} -+ -+/*----------------------------------------------------------------------------*/ -+ -+#define gcmBEGINSTATEBATCH_NEW(CommandBuffer, Memory, FixedPoint, Address, Count) \ -+{ \ -+ gcmVERIFYLOADSTATEALIGNED(CommandBuffer,Memory);\ -+ gcmASSERT((gctUINT32)Count <= 1024); \ -+ \ -+ *Memory++ \ -+ = gcmSETFIELDVALUE(0, AQ_COMMAND_LOAD_STATE_COMMAND, OPCODE, LOAD_STATE) \ -+ | gcmSETFIELD (0, AQ_COMMAND_LOAD_STATE_COMMAND, FLOAT, FixedPoint) \ -+ | gcmSETFIELD (0, AQ_COMMAND_LOAD_STATE_COMMAND, COUNT, Count) \ -+ | gcmSETFIELD (0, AQ_COMMAND_LOAD_STATE_COMMAND, ADDRESS, Address); \ -+ \ -+ gcmSKIPSECUREUSER(); \ -+} -+ -+#define gcmENDSTATEBATCH_NEW(CommandBuffer, Memory) \ -+ gcmVERIFYLOADSTATEALIGNED(CommandBuffer,Memory); -+ -+/*----------------------------------------------------------------------------*/ -+ -+#define gcmSETSTATEDATA_NEW(StateDelta, CommandBuffer, Memory, FixedPoint, \ -+ Address, Data) \ -+{ \ -+ gctUINT32 __temp_data32__; \ -+ \ -+ __temp_data32__ = Data; \ -+ \ -+ *Memory++ = __temp_data32__; \ -+ \ -+ gcoHARDWARE_UpdateDelta( \ -+ StateDelta, Address, 0, __temp_data32__ \ -+ ); \ -+ \ -+ gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, __temp_data32__); \ -+ \ -+ gcmUPDATESECUREUSER(); \ -+} -+ -+#define gcmSETSTATEDATAWITHMASK_NEW(StateDelta, CommandBuffer, Memory, FixedPoint, \ -+ Address, Mask, Data) \ -+{ \ -+ gctUINT32 __temp_data32__; \ -+ \ -+ __temp_data32__ = Data; \ -+ \ -+ *Memory++ = __temp_data32__; \ -+ \ -+ gcoHARDWARE_UpdateDelta( \ -+ StateDelta, Address, Mask, __temp_data32__ \ -+ ); \ -+ \ -+ gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, __temp_data32__); \ -+ \ -+ gcmUPDATESECUREUSER(); \ -+} -+ -+ -+#define gcmSETCTRLSTATE_NEW(StateDelta, CommandBuffer, Memory, Address, Data) \ -+{ \ -+ gctUINT32 __temp_data32__; \ -+ \ -+ __temp_data32__ = Data; \ -+ \ -+ *Memory++ = __temp_data32__; \ -+ \ -+ gcmDUMPSTATEDATA(StateDelta, gcvFALSE, Address, __temp_data32__); \ -+ \ -+ gcmSKIPSECUREUSER(); \ -+} -+ -+#define gcmSETFILLER_NEW(CommandBuffer, Memory) \ -+{ \ -+ Memory += 1; \ -+ \ -+ gcmSKIPSECUREUSER(); \ -+} -+ -+/*----------------------------------------------------------------------------*/ -+ -+#define gcmSETSINGLESTATE_NEW(StateDelta, CommandBuffer, Memory, FixedPoint, \ -+ Address, Data) \ -+{ \ -+ gcmBEGINSTATEBATCH_NEW(CommandBuffer, Memory, FixedPoint, Address, 1); \ -+ gcmSETSTATEDATA_NEW(StateDelta, CommandBuffer, Memory, FixedPoint, \ -+ Address, Data); \ -+ gcmENDSTATEBATCH_NEW(CommandBuffer, Memory); \ -+} -+ -+#define gcmSETSINGLESTATEWITHMASK_NEW(StateDelta, CommandBuffer, Memory, FixedPoint, \ -+ Address, Mask, Data) \ -+{ \ -+ gcmBEGINSTATEBATCH_NEW(CommandBuffer, Memory, FixedPoint, Address, 1); \ -+ gcmSETSTATEDATAWITHMASK_NEW(StateDelta, CommandBuffer, Memory, FixedPoint, \ -+ Address, Mask, Data); \ -+ gcmENDSTATEBATCH_NEW(CommandBuffer, Memory); \ -+} -+ -+ -+#define gcmSETSINGLECTRLSTATE_NEW(StateDelta, CommandBuffer, Memory, FixedPoint, \ -+ Address, Data) \ -+{ \ -+ gcmBEGINSTATEBATCH_NEW(CommandBuffer, Memory, FixedPoint, Address, 1); \ -+ gcmSETCTRLSTATE_NEW(StateDelta, CommandBuffer, Memory, Address, Data); \ -+ gcmENDSTATEBATCH_NEW(CommandBuffer, Memory); \ -+} -+ -+ -+ -+#define gcmSETSEMASTALLPIPE_NEW(StateDelta, CommandBuffer, Memory, Data) \ -+{ \ -+ gcmSETSINGLESTATE_NEW(StateDelta, CommandBuffer, Memory, gcvFALSE, AQSemaphoreRegAddrs, Data); \ -+ \ -+ *Memory++ = gcmSETFIELDVALUE(0, STALL_COMMAND, OPCODE, STALL); \ -+ \ -+ *Memory++ = Data; \ -+ \ -+ gcmDUMP(gcvNULL, "#[stall 0x%08X 0x%08X]", \ -+ gcmSETFIELDVALUE(0, AQ_SEMAPHORE, SOURCE, FRONT_END), \ -+ gcmSETFIELDVALUE(0, AQ_SEMAPHORE, DESTINATION, PIXEL_ENGINE)); \ -+ \ -+ gcmSKIPSECUREUSER(); \ -+} -+ -+#define gcmSETSTARTDECOMMAND_NEW(CommandBuffer, Memory, Count) \ -+{ \ -+ *Memory++ \ -+ = gcmSETFIELDVALUE(0, AQ_COMMAND_START_DE_COMMAND, OPCODE, START_DE) \ -+ | gcmSETFIELD (0, AQ_COMMAND_START_DE_COMMAND, COUNT, Count) \ -+ | gcmSETFIELD (0, AQ_COMMAND_START_DE_COMMAND, DATA_COUNT, 0); \ -+ \ -+ *Memory++ = 0xDEADDEED; \ -+ \ -+} -+ -+#define gcmSETSTATEDATA_NEW_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \ -+ Address, Data) \ -+{ \ -+ gctUINT32 __temp_data32__; \ -+ \ -+ __temp_data32__ = Data; \ -+ \ -+ *Memory++ = __temp_data32__; \ -+ \ -+ gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, __temp_data32__); \ -+ \ -+ gcmUPDATESECUREUSER(); \ -+} -+ -+#define gcmSETSTATEDATAWITHMASK_NEW_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \ -+ Address, Mask, Data) \ -+{ \ -+ gctUINT32 __temp_data32__; \ -+ \ -+ __temp_data32__ = Data; \ -+ \ -+ *Memory++ = __temp_data32__; \ -+ \ -+ gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, __temp_data32__); \ -+ \ -+ gcmUPDATESECUREUSER(); \ -+} -+ -+#define gcmSETSINGLESTATE_NEW_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \ -+ Address, Data) \ -+{ \ -+ gcmBEGINSTATEBATCH_NEW(CommandBuffer, Memory, FixedPoint, Address, 1); \ -+ gcmSETSTATEDATA_NEW_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \ -+ Address, Data); \ -+ gcmENDSTATEBATCH_NEW(CommandBuffer, Memory); \ -+} -+ -+#define gcmSETSINGLESTATEWITHMASK_NEW_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \ -+ Address, Mask, Data) \ -+{ \ -+ gcmBEGINSTATEBATCH_NEW(CommandBuffer, Memory, FixedPoint, Address, 1); \ -+ gcmSETSTATEDATAWITHMASK_NEW_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \ -+ Address, Mask, Data); \ -+ gcmENDSTATEBATCH_NEW(CommandBuffer, Memory); \ -+} -+ -+#define gcmSETSTATEDATA_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \ -+ Address, Data) \ -+{ \ -+ gctUINT32 __temp_data32__; \ -+ \ -+ gcmVERIFYLOADSTATE(CommandBuffer, Memory, Address); \ -+ \ -+ gcmSAFECASTSIZET(__temp_data32__, Data); \ -+ \ -+ *Memory++ = __temp_data32__; \ -+ \ -+ gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, __temp_data32__); \ -+ \ -+ gcmUPDATESECUREUSER(); \ -+} -+ -+#define gcmSETSTATEDATAWITHMASK_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \ -+ Address, Mask, Data) \ -+{ \ -+ gctUINT32 __temp_data32__; \ -+ \ -+ gcmVERIFYLOADSTATE(CommandBuffer, Memory, Address); \ -+ \ -+ __temp_data32__ = Data; \ -+ \ -+ *Memory++ = __temp_data32__; \ -+ \ -+ gcmDUMPSTATEDATA(StateDelta, FixedPoint, Address, __temp_data32__); \ -+ \ -+ gcmUPDATESECUREUSER(); \ -+} -+ -+#define gcmSETSINGLESTATE_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \ -+ Address, Data) \ -+{ \ -+ gcmBEGINSTATEBATCH(CommandBuffer, Memory, FixedPoint, Address, 1); \ -+ gcmSETSTATEDATA_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \ -+ Address, Data); \ -+ gcmENDSTATEBATCH(CommandBuffer, Memory); \ -+} -+ -+#define gcmSETSINGLESTATEWITHMASK_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \ -+ Address, Mask, Data) \ -+{ \ -+ gcmBEGINSTATEBATCH(CommandBuffer, Memory, FixedPoint, Address, 1); \ -+ gcmSETSTATEDATAWITHMASK_FAST(StateDelta, CommandBuffer, Memory, FixedPoint, \ -+ Address, Mask, Data); \ -+ gcmENDSTATEBATCH(CommandBuffer, Memory); \ -+} -+ -+#define gcmDEFINESTATEBUFFER_NEW_FAST(CommandBuffer, Memory) \ -+ gcmDEFINESECUREUSER() \ -+ gcmDEFINELOADSTATEBASE() \ -+ gcsTEMPCMDBUF CommandBuffer = gcvNULL; \ -+ gctUINT32_PTR Memory; -+ -+#define gcmDEFINESTATEBUFFER_FAST(CommandBuffer, Memory, ReserveSize) \ -+ gcmDEFINESECUREUSER() \ -+ gctSIZE_T ReserveSize; \ -+ gcoCMDBUF CommandBuffer; \ -+ gctUINT32_PTR Memory; -+ -+#define gcmBEGINSTATEBUFFER_FAST(Hardware, CommandBuffer, Memory, ReserveSize) \ -+{ \ -+ gcmONERROR(gcoBUFFER_Reserve( \ -+ Hardware->buffer, ReserveSize, gcvTRUE, &CommandBuffer \ -+ )); \ -+ \ -+ Memory = (gctUINT32_PTR) gcmUINT64_TO_PTR(CommandBuffer->lastReserve); \ -+ \ -+ gcmBEGINSECUREUSER(); \ -+} -+ -+#define gcmBEGINSTATEBUFFER_NEW_FAST(Hardware, CommandBuffer, Memory, OutSide) \ -+{ \ -+ if (OutSide) \ -+ {\ -+ Memory = (gctUINT32_PTR)*OutSide; \ -+ }\ -+ else \ -+ {\ -+ gcmONERROR(gcoBUFFER_StartTEMPCMDBUF( \ -+ Hardware->buffer, &CommandBuffer \ -+ ));\ -+ \ -+ Memory = (gctUINT32_PTR)(CommandBuffer->buffer); \ -+ \ -+ }\ -+ \ -+ gcmBEGINSECUREUSER(); \ -+ gcmSETLOADSTATEBASE(CommandBuffer,OutSide);\ -+} -+/******************************************************************************* -+** -+** gcmCONFIGUREUNIFORMS -+** -+** Configure uniforms according to chip and numConstants. -+*/ -+#if !gcdENABLE_UNIFIED_CONSTANT -+#define gcmCONFIGUREUNIFORMS(ChipModel, ChipRevision, NumConstants, \ -+ UnifiedConst, VsConstBase, PsConstBase, VsConstMax, PsConstMax, ConstMax) \ -+{ \ -+ if (ChipModel == gcv2000 && ChipRevision == 0x5118) \ -+ { \ -+ UnifiedConst = gcvFALSE; \ -+ VsConstBase = AQVertexShaderConstRegAddrs; \ -+ PsConstBase = AQPixelShaderConstRegAddrs; \ -+ VsConstMax = 256; \ -+ PsConstMax = 64; \ -+ ConstMax = 320; \ -+ } \ -+ else if (NumConstants == 320) \ -+ { \ -+ UnifiedConst = gcvFALSE; \ -+ VsConstBase = AQVertexShaderConstRegAddrs; \ -+ PsConstBase = AQPixelShaderConstRegAddrs; \ -+ VsConstMax = 256; \ -+ PsConstMax = 64; \ -+ ConstMax = 320; \ -+ } \ -+ /* All GC1000 series chips can only support 64 uniforms for ps on non-unified const mode. */ \ -+ else if (NumConstants > 256 && ChipModel == gcv1000) \ -+ { \ -+ UnifiedConst = gcvFALSE; \ -+ VsConstBase = AQVertexShaderConstRegAddrs; \ -+ PsConstBase = AQPixelShaderConstRegAddrs; \ -+ VsConstMax = 256; \ -+ PsConstMax = 64; \ -+ ConstMax = 320; \ -+ } \ -+ else if (NumConstants > 256) \ -+ { \ -+ UnifiedConst = gcvFALSE; \ -+ VsConstBase = AQVertexShaderConstRegAddrs; \ -+ PsConstBase = AQPixelShaderConstRegAddrs; \ -+ VsConstMax = 256; \ -+ PsConstMax = 256; \ -+ ConstMax = 512; \ -+ } \ -+ else if (NumConstants == 256) \ -+ { \ -+ UnifiedConst = gcvFALSE; \ -+ VsConstBase = AQVertexShaderConstRegAddrs; \ -+ PsConstBase = AQPixelShaderConstRegAddrs; \ -+ VsConstMax = 256; \ -+ PsConstMax = 256; \ -+ ConstMax = 512; \ -+ } \ -+ else \ -+ { \ -+ UnifiedConst = gcvFALSE; \ -+ VsConstBase = AQVertexShaderConstRegAddrs; \ -+ PsConstBase = AQPixelShaderConstRegAddrs; \ -+ VsConstMax = 168; \ -+ PsConstMax = 64; \ -+ ConstMax = 232; \ -+ } \ -+} -+#else -+#define gcmCONFIGUREUNIFORMS(ChipModel, ChipRevision, NumConstants, \ -+ UnifiedConst, VsConstBase, PsConstBase, VsConstMax, PsConstMax, ConstMax) \ -+{ \ -+ if (NumConstants > 256) \ -+ { \ -+ UnifiedConst = gcvTRUE; \ -+ VsConstBase = gcregSHUniformsRegAddrs; \ -+ PsConstBase = gcregSHUniformsRegAddrs; \ -+ ConstMax = NumConstants; \ -+ VsConstMax = 256; \ -+ PsConstMax = ConstMax - VsConstMax; \ -+ } \ -+ else if (NumConstants == 256) \ -+ { \ -+ if (ChipModel == gcv2000 && ChipRevision == 0x5118) \ -+ { \ -+ UnifiedConst = gcvFALSE; \ -+ VsConstBase = AQVertexShaderConstRegAddrs; \ -+ PsConstBase = AQPixelShaderConstRegAddrs; \ -+ VsConstMax = 256; \ -+ PsConstMax = 64; \ -+ ConstMax = 320; \ -+ } \ -+ else \ -+ { \ -+ UnifiedConst = gcvFALSE; \ -+ VsConstBase = AQVertexShaderConstRegAddrs; \ -+ PsConstBase = AQPixelShaderConstRegAddrs; \ -+ VsConstMax = 256; \ -+ PsConstMax = 256; \ -+ ConstMax = 512; \ -+ } \ -+ } \ -+ else \ -+ { \ -+ UnifiedConst = gcvFALSE; \ -+ VsConstBase = AQVertexShaderConstRegAddrs; \ -+ PsConstBase = AQPixelShaderConstRegAddrs; \ -+ VsConstMax = 168; \ -+ PsConstMax = 64; \ -+ ConstMax = 232; \ -+ } \ -+} -+#endif -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* __gc_hal_base_h_ */ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_driver.h linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_driver.h ---- linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_driver.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_driver.h 2015-11-30 17:56:13.588137194 +0100 -@@ -0,0 +1,1064 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+#ifndef __gc_hal_driver_h_ -+#define __gc_hal_driver_h_ -+ -+#include "gc_hal_enum.h" -+#include "gc_hal_types.h" -+ -+#if gcdENABLE_VG -+#include "gc_hal_driver_vg.h" -+#endif -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+/******************************************************************************\ -+******************************* I/O Control Codes ****************************** -+\******************************************************************************/ -+ -+#define gcvHAL_CLASS "galcore" -+#define IOCTL_GCHAL_INTERFACE 30000 -+#define IOCTL_GCHAL_KERNEL_INTERFACE 30001 -+#define IOCTL_GCHAL_TERMINATE 30002 -+ -+#undef CONFIG_ANDROID_RESERVED_MEMORY_ACCOUNT -+/******************************************************************************\ -+********************************* Command Codes ******************************** -+\******************************************************************************/ -+ -+typedef enum _gceHAL_COMMAND_CODES -+{ -+ /* Generic query. */ -+ gcvHAL_QUERY_VIDEO_MEMORY, -+ gcvHAL_QUERY_CHIP_IDENTITY, -+ -+ /* Contiguous memory. */ -+ gcvHAL_ALLOCATE_NON_PAGED_MEMORY, -+ gcvHAL_FREE_NON_PAGED_MEMORY, -+ gcvHAL_ALLOCATE_CONTIGUOUS_MEMORY, -+ gcvHAL_FREE_CONTIGUOUS_MEMORY, -+ -+ /* Video memory allocation. */ -+ gcvHAL_ALLOCATE_VIDEO_MEMORY, /* Enforced alignment. */ -+ gcvHAL_ALLOCATE_LINEAR_VIDEO_MEMORY, /* No alignment. */ -+ gcvHAL_RELEASE_VIDEO_MEMORY, -+ -+ /* Physical-to-logical mapping. */ -+ gcvHAL_MAP_MEMORY, -+ gcvHAL_UNMAP_MEMORY, -+ -+ /* Logical-to-physical mapping. */ -+ gcvHAL_MAP_USER_MEMORY, -+ gcvHAL_UNMAP_USER_MEMORY, -+ -+ /* Surface lock/unlock. */ -+ gcvHAL_LOCK_VIDEO_MEMORY, -+ gcvHAL_UNLOCK_VIDEO_MEMORY, -+ -+ /* Event queue. */ -+ gcvHAL_EVENT_COMMIT, -+ -+ gcvHAL_USER_SIGNAL, -+ gcvHAL_SIGNAL, -+ gcvHAL_WRITE_DATA, -+ -+ gcvHAL_COMMIT, -+ gcvHAL_STALL, -+ -+ gcvHAL_READ_REGISTER, -+ gcvHAL_WRITE_REGISTER, -+ -+ gcvHAL_GET_PROFILE_SETTING, -+ gcvHAL_SET_PROFILE_SETTING, -+ -+ gcvHAL_READ_ALL_PROFILE_REGISTERS, -+ gcvHAL_PROFILE_REGISTERS_2D, -+#if VIVANTE_PROFILER_PERDRAW -+ gcvHAL_READ_PROFILER_REGISTER_SETTING, -+#endif -+ -+ /* Power management. */ -+ gcvHAL_SET_POWER_MANAGEMENT_STATE, -+ gcvHAL_QUERY_POWER_MANAGEMENT_STATE, -+ -+ gcvHAL_GET_BASE_ADDRESS, -+ -+ gcvHAL_SET_IDLE, /* reserved */ -+ -+ /* Queries. */ -+ gcvHAL_QUERY_KERNEL_SETTINGS, -+ -+ /* Reset. */ -+ gcvHAL_RESET, -+ -+ /* Map physical address into handle. */ -+ gcvHAL_MAP_PHYSICAL, -+ -+ /* Debugger stuff. */ -+ gcvHAL_DEBUG, -+ -+ /* Cache stuff. */ -+ gcvHAL_CACHE, -+ -+ /* TimeStamp */ -+ gcvHAL_TIMESTAMP, -+ -+ /* Database. */ -+ gcvHAL_DATABASE, -+ -+ /* Version. */ -+ gcvHAL_VERSION, -+ -+ /* Chip info */ -+ gcvHAL_CHIP_INFO, -+ -+ /* Process attaching/detaching. */ -+ gcvHAL_ATTACH, -+ gcvHAL_DETACH, -+ -+ /* Composition. */ -+ gcvHAL_COMPOSE, -+ -+ /* Set timeOut value */ -+ gcvHAL_SET_TIMEOUT, -+ -+ /* Frame database. */ -+ gcvHAL_GET_FRAME_INFO, -+ -+ gcvHAL_QUERY_COMMAND_BUFFER, -+ -+ gcvHAL_COMMIT_DONE, -+ -+ /* GPU and event dump */ -+ gcvHAL_DUMP_GPU_STATE, -+ gcvHAL_DUMP_EVENT, -+ -+ /* Virtual command buffer. */ -+ gcvHAL_ALLOCATE_VIRTUAL_COMMAND_BUFFER, -+ gcvHAL_FREE_VIRTUAL_COMMAND_BUFFER, -+ -+ /* FSCALE_VAL. */ -+ gcvHAL_SET_FSCALE_VALUE, -+ gcvHAL_GET_FSCALE_VALUE, -+ -+ gcvHAL_NAME_VIDEO_MEMORY, -+ gcvHAL_IMPORT_VIDEO_MEMORY, -+ -+ /* Reset time stamp. */ -+ gcvHAL_QUERY_RESET_TIME_STAMP, -+ -+ /* Multi-GPU read/write. */ -+ gcvHAL_READ_REGISTER_EX, -+ gcvHAL_WRITE_REGISTER_EX, -+ -+ /* Sync point operations. */ -+ gcvHAL_SYNC_POINT, -+ -+ /* Create native fence and return its fd. */ -+ gcvHAL_CREATE_NATIVE_FENCE, -+ -+ /* Destory MMU. */ -+ gcvHAL_DESTROY_MMU, -+ -+ /* Shared buffer. */ -+ gcvHAL_SHBUF, -+ -+ /* Config power management. */ -+ gcvHAL_CONFIG_POWER_MANAGEMENT, -+ -+ /* Connect a video node to an OS native fd. */ -+ gcvHAL_GET_VIDEO_MEMORY_FD, -+} -+gceHAL_COMMAND_CODES; -+ -+/******************************************************************************\ -+****************************** Interface Structure ***************************** -+\******************************************************************************/ -+ -+#define gcdMAX_PROFILE_FILE_NAME 128 -+ -+/* Kernel settings. */ -+typedef struct _gcsKERNEL_SETTINGS -+{ -+ /* Used RealTime signal between kernel and user. */ -+ gctINT signal; -+} -+gcsKERNEL_SETTINGS; -+ -+ -+/* gcvHAL_QUERY_CHIP_IDENTITY */ -+typedef struct _gcsHAL_QUERY_CHIP_IDENTITY * gcsHAL_QUERY_CHIP_IDENTITY_PTR; -+typedef struct _gcsHAL_QUERY_CHIP_IDENTITY -+{ -+ -+ /* Chip model. */ -+ gceCHIPMODEL chipModel; -+ -+ /* Revision value.*/ -+ gctUINT32 chipRevision; -+ -+ /* Supported feature fields. */ -+ gctUINT32 chipFeatures; -+ -+ /* Supported minor feature fields. */ -+ gctUINT32 chipMinorFeatures; -+ -+ /* Supported minor feature 1 fields. */ -+ gctUINT32 chipMinorFeatures1; -+ -+ /* Supported minor feature 2 fields. */ -+ gctUINT32 chipMinorFeatures2; -+ -+ /* Supported minor feature 3 fields. */ -+ gctUINT32 chipMinorFeatures3; -+ -+ /* Supported minor feature 4 fields. */ -+ gctUINT32 chipMinorFeatures4; -+ -+ /* Supported minor feature 5 fields. */ -+ gctUINT32 chipMinorFeatures5; -+ -+ /* Number of streams supported. */ -+ gctUINT32 streamCount; -+ -+ /* Total number of temporary registers per thread. */ -+ gctUINT32 registerMax; -+ -+ /* Maximum number of threads. */ -+ gctUINT32 threadCount; -+ -+ /* Number of shader cores. */ -+ gctUINT32 shaderCoreCount; -+ -+ /* Size of the vertex cache. */ -+ gctUINT32 vertexCacheSize; -+ -+ /* Number of entries in the vertex output buffer. */ -+ gctUINT32 vertexOutputBufferSize; -+ -+ /* Number of pixel pipes. */ -+ gctUINT32 pixelPipes; -+ -+ /* Number of instructions. */ -+ gctUINT32 instructionCount; -+ -+ /* Number of constants. */ -+ gctUINT32 numConstants; -+ -+ /* Buffer size */ -+ gctUINT32 bufferSize; -+ -+ /* Number of varyings */ -+ gctUINT32 varyingsCount; -+ -+ /* Supertile layout style in hardware */ -+ gctUINT32 superTileMode; -+ -+ /* Special control bits for 2D chip. */ -+ gctUINT32 chip2DControl; -+ -+ /* Product ID */ -+ gctUINT32 productID; -+} -+gcsHAL_QUERY_CHIP_IDENTITY; -+ -+/* gcvHAL_COMPOSE. */ -+typedef struct _gcsHAL_COMPOSE * gcsHAL_COMPOSE_PTR; -+typedef struct _gcsHAL_COMPOSE -+{ -+ /* Composition state buffer. */ -+ gctUINT64 physical; -+ gctUINT64 logical; -+ gctUINT offset; -+ gctUINT size; -+ -+ /* Composition end signal. */ -+ gctUINT64 process; -+ gctUINT64 signal; -+ -+ /* User signals. */ -+ gctUINT64 userProcess; -+ gctUINT64 userSignal1; -+ gctUINT64 userSignal2; -+} -+gcsHAL_COMPOSE; -+ -+ -+typedef struct _gcsHAL_INTERFACE -+{ -+ /* Command code. */ -+ gceHAL_COMMAND_CODES command; -+ -+ /* Hardware type. */ -+ gceHARDWARE_TYPE hardwareType; -+ -+ /* Status value. */ -+ gceSTATUS status; -+ -+ /* Handle to this interface channel. */ -+ gctUINT64 handle; -+ -+ /* Pid of the client. */ -+ gctUINT32 pid; -+ -+ /* Union of command structures. */ -+ union _u -+ { -+ /* gcvHAL_GET_BASE_ADDRESS */ -+ struct _gcsHAL_GET_BASE_ADDRESS -+ { -+ /* Physical memory address of internal memory. */ -+ OUT gctUINT32 baseAddress; -+ } -+ GetBaseAddress; -+ -+ /* gcvHAL_QUERY_VIDEO_MEMORY */ -+ struct _gcsHAL_QUERY_VIDEO_MEMORY -+ { -+ /* Physical memory address of internal memory. Just a name. */ -+ OUT gctUINT32 internalPhysical; -+ -+ /* Size in bytes of internal memory. */ -+ OUT gctUINT64 internalSize; -+ -+ /* Physical memory address of external memory. Just a name. */ -+ OUT gctUINT32 externalPhysical; -+ -+ /* Size in bytes of external memory.*/ -+ OUT gctUINT64 externalSize; -+ -+ /* Physical memory address of contiguous memory. Just a name. */ -+ OUT gctUINT32 contiguousPhysical; -+ -+ /* Size in bytes of contiguous memory.*/ -+ OUT gctUINT64 contiguousSize; -+ } -+ QueryVideoMemory; -+ -+ /* gcvHAL_QUERY_CHIP_IDENTITY */ -+ gcsHAL_QUERY_CHIP_IDENTITY QueryChipIdentity; -+ -+ /* gcvHAL_MAP_MEMORY */ -+ struct _gcsHAL_MAP_MEMORY -+ { -+ /* Physical memory address to map. Just a name on Linux/Qnx. */ -+ IN gctUINT32 physical; -+ -+ /* Number of bytes in physical memory to map. */ -+ IN gctUINT64 bytes; -+ -+ /* Address of mapped memory. */ -+ OUT gctUINT64 logical; -+ } -+ MapMemory; -+ -+ /* gcvHAL_UNMAP_MEMORY */ -+ struct _gcsHAL_UNMAP_MEMORY -+ { -+ /* Physical memory address to unmap. Just a name on Linux/Qnx. */ -+ IN gctUINT32 physical; -+ -+ /* Number of bytes in physical memory to unmap. */ -+ IN gctUINT64 bytes; -+ -+ /* Address of mapped memory to unmap. */ -+ IN gctUINT64 logical; -+ } -+ UnmapMemory; -+ -+ /* gcvHAL_ALLOCATE_LINEAR_VIDEO_MEMORY */ -+ struct _gcsHAL_ALLOCATE_LINEAR_VIDEO_MEMORY -+ { -+ /* Number of bytes to allocate. */ -+ IN OUT gctUINT bytes; -+ -+ /* Buffer alignment. */ -+ IN gctUINT alignment; -+ -+ /* Type of allocation. */ -+ IN gceSURF_TYPE type; -+ -+ /* Flag of allocation. */ -+ IN gctUINT32 flag; -+ -+ /* Memory pool to allocate from. */ -+ IN OUT gcePOOL pool; -+ -+ /* Allocated video memory. */ -+ OUT gctUINT32 node; -+ } -+ AllocateLinearVideoMemory; -+ -+ /* gcvHAL_ALLOCATE_VIDEO_MEMORY */ -+ struct _gcsHAL_ALLOCATE_VIDEO_MEMORY -+ { -+ /* Width of rectangle to allocate. */ -+ IN OUT gctUINT width; -+ -+ /* Height of rectangle to allocate. */ -+ IN OUT gctUINT height; -+ -+ /* Depth of rectangle to allocate. */ -+ IN gctUINT depth; -+ -+ /* Format rectangle to allocate in gceSURF_FORMAT. */ -+ IN gceSURF_FORMAT format; -+ -+ /* Type of allocation. */ -+ IN gceSURF_TYPE type; -+ -+ /* Memory pool to allocate from. */ -+ IN OUT gcePOOL pool; -+ -+ /* Allocated video memory. */ -+ OUT gctUINT32 node; -+ } -+ AllocateVideoMemory; -+ -+ /* gcvHAL_RELEASE_VIDEO_MEMORY */ -+ struct _gcsHAL_RELEASE_VIDEO_MEMORY -+ { -+ /* Allocated video memory. */ -+ IN gctUINT32 node; -+ } -+ ReleaseVideoMemory; -+ -+ /* gcvHAL_LOCK_VIDEO_MEMORY */ -+ struct _gcsHAL_LOCK_VIDEO_MEMORY -+ { -+ /* Allocated video memory. */ -+ IN gctUINT32 node; -+ -+ /* Cache configuration. */ -+ /* Only gcvPOOL_CONTIGUOUS and gcvPOOL_VIRUTAL -+ ** can be configured */ -+ IN gctBOOL cacheable; -+ -+ /* Hardware specific address. */ -+ OUT gctUINT32 address; -+ -+ /* Mapped logical address. */ -+ OUT gctUINT64 memory; -+ -+ /* Customer priviate handle*/ -+ OUT gctUINT32 gid; -+ -+ /* Bus address of a contiguous video node. */ -+ OUT gctUINT64 physicalAddress; -+ } -+ LockVideoMemory; -+ -+ /* gcvHAL_UNLOCK_VIDEO_MEMORY */ -+ struct _gcsHAL_UNLOCK_VIDEO_MEMORY -+ { -+ /* Allocated video memory. */ -+ IN gctUINT64 node; -+ -+ /* Type of surface. */ -+ IN gceSURF_TYPE type; -+ -+ /* Flag to unlock surface asynchroneously. */ -+ IN OUT gctBOOL asynchroneous; -+ } -+ UnlockVideoMemory; -+ -+ /* gcvHAL_ALLOCATE_NON_PAGED_MEMORY */ -+ struct _gcsHAL_ALLOCATE_NON_PAGED_MEMORY -+ { -+ /* Number of bytes to allocate. */ -+ IN OUT gctUINT64 bytes; -+ -+ /* Physical address of allocation. Just a name. */ -+ OUT gctUINT32 physical; -+ -+ /* Logical address of allocation. */ -+ OUT gctUINT64 logical; -+ } -+ AllocateNonPagedMemory; -+ -+ /* gcvHAL_FREE_NON_PAGED_MEMORY */ -+ struct _gcsHAL_FREE_NON_PAGED_MEMORY -+ { -+ /* Number of bytes allocated. */ -+ IN gctUINT64 bytes; -+ -+ /* Physical address of allocation. Just a name. */ -+ IN gctUINT32 physical; -+ -+ /* Logical address of allocation. */ -+ IN gctUINT64 logical; -+ } -+ FreeNonPagedMemory; -+ -+ /* gcvHAL_ALLOCATE_NON_PAGED_MEMORY */ -+ struct _gcsHAL_ALLOCATE_VIRTUAL_COMMAND_BUFFER -+ { -+ /* Number of bytes to allocate. */ -+ IN OUT gctUINT64 bytes; -+ -+ /* Physical address of allocation. Just a name. */ -+ OUT gctUINT32 physical; -+ -+ /* Logical address of allocation. */ -+ OUT gctUINT64 logical; -+ } -+ AllocateVirtualCommandBuffer; -+ -+ /* gcvHAL_FREE_NON_PAGED_MEMORY */ -+ struct _gcsHAL_FREE_VIRTUAL_COMMAND_BUFFER -+ { -+ /* Number of bytes allocated. */ -+ IN gctUINT64 bytes; -+ -+ /* Physical address of allocation. Just a name. */ -+ IN gctUINT32 physical; -+ -+ /* Logical address of allocation. */ -+ IN gctUINT64 logical; -+ } -+ FreeVirtualCommandBuffer; -+ -+ /* gcvHAL_EVENT_COMMIT. */ -+ struct _gcsHAL_EVENT_COMMIT -+ { -+ /* Event queue in gcsQUEUE. */ -+ IN gctUINT64 queue; -+ } -+ Event; -+ -+ /* gcvHAL_COMMIT */ -+ struct _gcsHAL_COMMIT -+ { -+ /* Context buffer object gckCONTEXT. */ -+ IN gctUINT64 context; -+ -+ /* Command buffer gcoCMDBUF. */ -+ IN gctUINT64 commandBuffer; -+ -+ /* State delta buffer in gcsSTATE_DELTA. */ -+ gctUINT64 delta; -+ -+ /* Event queue in gcsQUEUE. */ -+ IN gctUINT64 queue; -+ } -+ Commit; -+ -+ /* gcvHAL_MAP_USER_MEMORY */ -+ struct _gcsHAL_MAP_USER_MEMORY -+ { -+ /* Base address of user memory to map. */ -+ IN gctUINT64 memory; -+ -+ /* Physical address of user memory to map. */ -+ IN gctUINT32 physical; -+ -+ /* Size of user memory in bytes to map. */ -+ IN gctUINT64 size; -+ -+ /* Info record required by gcvHAL_UNMAP_USER_MEMORY. Just a name. */ -+ OUT gctUINT32 info; -+ -+ /* Physical address of mapped memory. */ -+ OUT gctUINT32 address; -+ } -+ MapUserMemory; -+ -+ /* gcvHAL_UNMAP_USER_MEMORY */ -+ struct _gcsHAL_UNMAP_USER_MEMORY -+ { -+ /* Base address of user memory to unmap. */ -+ IN gctUINT64 memory; -+ -+ /* Size of user memory in bytes to unmap. */ -+ IN gctUINT64 size; -+ -+ /* Info record returned by gcvHAL_MAP_USER_MEMORY. Just a name. */ -+ IN gctUINT32 info; -+ -+ /* Physical address of mapped memory as returned by -+ gcvHAL_MAP_USER_MEMORY. */ -+ IN gctUINT32 address; -+ } -+ UnmapUserMemory; -+ /* gcsHAL_USER_SIGNAL */ -+ struct _gcsHAL_USER_SIGNAL -+ { -+ /* Command. */ -+ gceUSER_SIGNAL_COMMAND_CODES command; -+ -+ /* Signal ID. */ -+ IN OUT gctINT id; -+ -+ /* Reset mode. */ -+ IN gctBOOL manualReset; -+ -+ /* Wait timedout. */ -+ IN gctUINT32 wait; -+ -+ /* State. */ -+ IN gctBOOL state; -+ } -+ UserSignal; -+ -+ /* gcvHAL_SIGNAL. */ -+ struct _gcsHAL_SIGNAL -+ { -+ /* Signal handle to signal gctSIGNAL. */ -+ IN gctUINT64 signal; -+ -+ /* Reserved gctSIGNAL. */ -+ IN gctUINT64 auxSignal; -+ -+ /* Process owning the signal gctHANDLE. */ -+ IN gctUINT64 process; -+ /* Event generated from where of pipeline */ -+ IN gceKERNEL_WHERE fromWhere; -+ } -+ Signal; -+ -+ /* gcvHAL_WRITE_DATA. */ -+ struct _gcsHAL_WRITE_DATA -+ { -+ /* Address to write data to. */ -+ IN gctUINT32 address; -+ -+ /* Data to write. */ -+ IN gctUINT32 data; -+ } -+ WriteData; -+ -+ /* gcvHAL_ALLOCATE_CONTIGUOUS_MEMORY */ -+ struct _gcsHAL_ALLOCATE_CONTIGUOUS_MEMORY -+ { -+ /* Number of bytes to allocate. */ -+ IN OUT gctUINT64 bytes; -+ -+ /* Hardware address of allocation. */ -+ OUT gctUINT32 address; -+ -+ /* Physical address of allocation. Just a name. */ -+ OUT gctUINT32 physical; -+ -+ /* Logical address of allocation. */ -+ OUT gctUINT64 logical; -+ } -+ AllocateContiguousMemory; -+ -+ /* gcvHAL_FREE_CONTIGUOUS_MEMORY */ -+ struct _gcsHAL_FREE_CONTIGUOUS_MEMORY -+ { -+ /* Number of bytes allocated. */ -+ IN gctUINT64 bytes; -+ -+ /* Physical address of allocation. Just a name. */ -+ IN gctUINT32 physical; -+ -+ /* Logical address of allocation. */ -+ IN gctUINT64 logical; -+ } -+ FreeContiguousMemory; -+ -+ /* gcvHAL_READ_REGISTER */ -+ struct _gcsHAL_READ_REGISTER -+ { -+ /* Logical address of memory to write data to. */ -+ IN gctUINT32 address; -+ -+ /* Data read. */ -+ OUT gctUINT32 data; -+ } -+ ReadRegisterData; -+ -+ /* gcvHAL_WRITE_REGISTER */ -+ struct _gcsHAL_WRITE_REGISTER -+ { -+ /* Logical address of memory to write data to. */ -+ IN gctUINT32 address; -+ -+ /* Data read. */ -+ IN gctUINT32 data; -+ } -+ WriteRegisterData; -+ -+#if VIVANTE_PROFILER -+ /* gcvHAL_GET_PROFILE_SETTING */ -+ struct _gcsHAL_GET_PROFILE_SETTING -+ { -+ /* Enable profiling */ -+ OUT gctBOOL enable; -+ } -+ GetProfileSetting; -+ -+ /* gcvHAL_SET_PROFILE_SETTING */ -+ struct _gcsHAL_SET_PROFILE_SETTING -+ { -+ /* Enable profiling */ -+ IN gctBOOL enable; -+ } -+ SetProfileSetting; -+ -+#if VIVANTE_PROFILER_PERDRAW -+ /* gcvHAL_READ_PROFILER_REGISTER_SETTING */ -+ struct _gcsHAL_READ_PROFILER_REGISTER_SETTING -+ { -+ /*Should Clear Register*/ -+ IN gctBOOL bclear; -+ } -+ SetProfilerRegisterClear; -+#endif -+ -+ /* gcvHAL_READ_ALL_PROFILE_REGISTERS */ -+ struct _gcsHAL_READ_ALL_PROFILE_REGISTERS -+ { -+#if VIVANTE_PROFILER_CONTEXT -+ /* Context buffer object gckCONTEXT. Just a name. */ -+ IN gctUINT32 context; -+#endif -+ -+ /* Data read. */ -+ OUT gcsPROFILER_COUNTERS counters; -+ } -+ RegisterProfileData; -+ -+ /* gcvHAL_PROFILE_REGISTERS_2D */ -+ struct _gcsHAL_PROFILE_REGISTERS_2D -+ { -+ /* Data read in gcs2D_PROFILE. */ -+ OUT gctUINT64 hwProfile2D; -+ } -+ RegisterProfileData2D; -+#endif -+ -+ /* Power management. */ -+ /* gcvHAL_SET_POWER_MANAGEMENT_STATE */ -+ struct _gcsHAL_SET_POWER_MANAGEMENT -+ { -+ /* Data read. */ -+ IN gceCHIPPOWERSTATE state; -+ } -+ SetPowerManagement; -+ -+ /* gcvHAL_QUERY_POWER_MANAGEMENT_STATE */ -+ struct _gcsHAL_QUERY_POWER_MANAGEMENT -+ { -+ /* Data read. */ -+ OUT gceCHIPPOWERSTATE state; -+ -+ /* Idle query. */ -+ OUT gctBOOL isIdle; -+ } -+ QueryPowerManagement; -+ -+ /* gcvHAL_QUERY_KERNEL_SETTINGS */ -+ struct _gcsHAL_QUERY_KERNEL_SETTINGS -+ { -+ /* Settings.*/ -+ OUT gcsKERNEL_SETTINGS settings; -+ } -+ QueryKernelSettings; -+ -+ /* gcvHAL_MAP_PHYSICAL */ -+ struct _gcsHAL_MAP_PHYSICAL -+ { -+ /* gcvTRUE to map, gcvFALSE to unmap. */ -+ IN gctBOOL map; -+ -+ /* Physical address. */ -+ IN OUT gctUINT64 physical; -+ } -+ MapPhysical; -+ -+ /* gcvHAL_DEBUG */ -+ struct _gcsHAL_DEBUG -+ { -+ /* If gcvTRUE, set the debug information. */ -+ IN gctBOOL set; -+ IN gctUINT32 level; -+ IN gctUINT32 zones; -+ IN gctBOOL enable; -+ -+ IN gceDEBUG_MESSAGE_TYPE type; -+ IN gctUINT32 messageSize; -+ -+ /* Message to print if not empty. */ -+ IN gctCHAR message[80]; -+ } -+ Debug; -+ -+ /* gcvHAL_CACHE */ -+ struct _gcsHAL_CACHE -+ { -+ IN gceCACHEOPERATION operation; -+ IN gctUINT64 process; -+ IN gctUINT64 logical; -+ IN gctUINT64 bytes; -+ IN gctUINT32 node; -+ } -+ Cache; -+ -+ /* gcvHAL_TIMESTAMP */ -+ struct _gcsHAL_TIMESTAMP -+ { -+ /* Timer select. */ -+ IN gctUINT32 timer; -+ -+ /* Timer request type (0-stop, 1-start, 2-send delta). */ -+ IN gctUINT32 request; -+ -+ /* Result of delta time in microseconds. */ -+ OUT gctINT32 timeDelta; -+ } -+ TimeStamp; -+ -+ /* gcvHAL_DATABASE */ -+ struct _gcsHAL_DATABASE -+ { -+ /* Set to gcvTRUE if you want to query a particular process ID. -+ ** Set to gcvFALSE to query the last detached process. */ -+ IN gctBOOL validProcessID; -+ -+ /* Process ID to query. */ -+ IN gctUINT32 processID; -+ -+ /* Information. */ -+ OUT gcuDATABASE_INFO vidMem; -+ OUT gcuDATABASE_INFO nonPaged; -+ OUT gcuDATABASE_INFO contiguous; -+ OUT gcuDATABASE_INFO gpuIdle; -+ -+ /* Detail information about video memory. */ -+ OUT gcuDATABASE_INFO vidMemPool[3]; -+ } -+ Database; -+ -+ /* gcvHAL_VERSION */ -+ struct _gcsHAL_VERSION -+ { -+ /* Major version: N.n.n. */ -+ OUT gctINT32 major; -+ -+ /* Minor version: n.N.n. */ -+ OUT gctINT32 minor; -+ -+ /* Patch version: n.n.N. */ -+ OUT gctINT32 patch; -+ -+ /* Build version. */ -+ OUT gctUINT32 build; -+ } -+ Version; -+ -+ /* gcvHAL_CHIP_INFO */ -+ struct _gcsHAL_CHIP_INFO -+ { -+ /* Chip count. */ -+ OUT gctINT32 count; -+ -+ /* Chip types. */ -+ OUT gceHARDWARE_TYPE types[gcdCHIP_COUNT]; -+ } -+ ChipInfo; -+ -+ /* gcvHAL_ATTACH */ -+ struct _gcsHAL_ATTACH -+ { -+ /* Handle of context buffer object. */ -+ OUT gctUINT32 context; -+ -+ /* Number of states in the buffer. */ -+ OUT gctUINT64 stateCount; -+ -+ /* Map context buffer to user or not. */ -+ IN gctBOOL map; -+ -+ /* Physical of context buffer. */ -+ OUT gctUINT32 physicals[2]; -+ -+ /* Physical of context buffer. */ -+ OUT gctUINT64 logicals[2]; -+ -+ /* Bytes of context buffer. */ -+ OUT gctUINT32 bytes; -+ } -+ Attach; -+ -+ /* gcvHAL_DETACH */ -+ struct _gcsHAL_DETACH -+ { -+ /* Context buffer object gckCONTEXT. Just a name. */ -+ IN gctUINT32 context; -+ } -+ Detach; -+ -+ /* gcvHAL_COMPOSE. */ -+ gcsHAL_COMPOSE Compose; -+ -+ /* gcvHAL_GET_FRAME_INFO. */ -+ struct _gcsHAL_GET_FRAME_INFO -+ { -+ /* gcsHAL_FRAME_INFO* */ -+ OUT gctUINT64 frameInfo; -+ } -+ GetFrameInfo; -+ -+ /* gcvHAL_SET_TIME_OUT. */ -+ struct _gcsHAL_SET_TIMEOUT -+ { -+ gctUINT32 timeOut; -+ } -+ SetTimeOut; -+ -+#if gcdENABLE_VG -+ /* gcvHAL_COMMIT */ -+ struct _gcsHAL_VGCOMMIT -+ { -+ /* Context buffer. gcsVGCONTEXT_PTR */ -+ IN gctUINT64 context; -+ -+ /* Command queue. gcsVGCMDQUEUE_PTR */ -+ IN gctUINT64 queue; -+ -+ /* Number of entries in the queue. */ -+ IN gctUINT entryCount; -+ -+ /* Task table. gcsTASK_MASTER_TABLE_PTR */ -+ IN gctUINT64 taskTable; -+ } -+ VGCommit; -+ -+ /* gcvHAL_QUERY_COMMAND_BUFFER */ -+ struct _gcsHAL_QUERY_COMMAND_BUFFER -+ { -+ /* Command buffer attributes. */ -+ OUT gcsCOMMAND_BUFFER_INFO information; -+ } -+ QueryCommandBuffer; -+ -+#endif -+ -+ struct _gcsHAL_SET_FSCALE_VALUE -+ { -+ IN gctUINT value; -+ } -+ SetFscaleValue; -+ -+ struct _gcsHAL_GET_FSCALE_VALUE -+ { -+ OUT gctUINT value; -+ OUT gctUINT minValue; -+ OUT gctUINT maxValue; -+ } -+ GetFscaleValue; -+ -+ struct _gcsHAL_NAME_VIDEO_MEMORY -+ { -+ IN gctUINT32 handle; -+ OUT gctUINT32 name; -+ } -+ NameVideoMemory; -+ -+ struct _gcsHAL_IMPORT_VIDEO_MEMORY -+ { -+ IN gctUINT32 name; -+ OUT gctUINT32 handle; -+ } -+ ImportVideoMemory; -+ -+ struct _gcsHAL_QUERY_RESET_TIME_STAMP -+ { -+ OUT gctUINT64 timeStamp; -+ } -+ QueryResetTimeStamp; -+ -+ struct _gcsHAL_SYNC_POINT -+ { -+ /* Command. */ -+ gceSYNC_POINT_COMMAND_CODES command; -+ -+ /* Sync point. */ -+ IN OUT gctUINT64 syncPoint; -+ -+ /* From where. */ -+ IN gceKERNEL_WHERE fromWhere; -+ -+ /* Signaled state. */ -+ OUT gctBOOL state; -+ } -+ SyncPoint; -+ -+ struct _gcsHAL_CREATE_NATIVE_FENCE -+ { -+ /* Signal id to dup. */ -+ IN gctUINT64 syncPoint; -+ -+ /* Native fence file descriptor. */ -+ OUT gctINT fenceFD; -+ -+ } -+ CreateNativeFence; -+ -+ struct _gcsHAL_DESTROY_MMU -+ { -+ /* Mmu object. */ -+ IN gctUINT64 mmu; -+ } -+ DestroyMmu; -+ -+ struct _gcsHAL_SHBUF -+ { -+ gceSHBUF_COMMAND_CODES command; -+ -+ /* Shared buffer. */ -+ IN OUT gctUINT64 id; -+ -+ /* User data to be shared. */ -+ IN gctUINT64 data; -+ -+ /* Data size. */ -+ IN OUT gctUINT32 bytes; -+ } -+ ShBuf; -+ -+ struct _gcsHAL_CONFIG_POWER_MANAGEMENT -+ { -+ IN gctBOOL enable; -+ } -+ ConfigPowerManagement; -+ -+ struct _gcsHAL_GET_VIDEO_MEMORY_FD -+ { -+ IN gctUINT32 handle; -+ OUT gctINT fd; -+ } -+ GetVideoMemoryFd; -+ } -+ u; -+} -+gcsHAL_INTERFACE; -+ -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* __gc_hal_driver_h_ */ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_driver_vg.h linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_driver_vg.h ---- linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_driver_vg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_driver_vg.h 2015-11-30 17:56:13.588137194 +0100 -@@ -0,0 +1,265 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#ifndef __gc_hal_driver_vg_h_ -+#define __gc_hal_driver_vg_h_ -+ -+ -+ -+#include "gc_hal_types.h" -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+/******************************************************************************\ -+******************************* I/O Control Codes ****************************** -+\******************************************************************************/ -+ -+#define gcvHAL_CLASS "galcore" -+#define IOCTL_GCHAL_INTERFACE 30000 -+ -+/******************************************************************************\ -+********************************* Command Codes ******************************** -+\******************************************************************************/ -+ -+/******************************************************************************\ -+********************* Command buffer information structure. ******************** -+\******************************************************************************/ -+ -+typedef struct _gcsCOMMAND_BUFFER_INFO * gcsCOMMAND_BUFFER_INFO_PTR; -+typedef struct _gcsCOMMAND_BUFFER_INFO -+{ -+ /* FE command buffer interrupt ID. */ -+ gctINT32 feBufferInt; -+ -+ /* TS overflow interrupt ID. */ -+ gctINT32 tsOverflowInt; -+ -+ /* Alignment and mask for the buffer address. */ -+ gctUINT addressMask; -+ gctUINT32 addressAlignment; -+ -+ /* Alignment for each command. */ -+ gctUINT32 commandAlignment; -+ -+ /* Number of bytes required by the STATE command. */ -+ gctUINT32 stateCommandSize; -+ -+ /* Number of bytes required by the RESTART command. */ -+ gctUINT32 restartCommandSize; -+ -+ /* Number of bytes required by the FETCH command. */ -+ gctUINT32 fetchCommandSize; -+ -+ /* Number of bytes required by the CALL command. */ -+ gctUINT32 callCommandSize; -+ -+ /* Number of bytes required by the RETURN command. */ -+ gctUINT32 returnCommandSize; -+ -+ /* Number of bytes required by the EVENT command. */ -+ gctUINT32 eventCommandSize; -+ -+ /* Number of bytes required by the END command. */ -+ gctUINT32 endCommandSize; -+ -+ /* Number of bytes reserved at the tail of a static command buffer. */ -+ gctUINT32 staticTailSize; -+ -+ /* Number of bytes reserved at the tail of a dynamic command buffer. */ -+ gctUINT32 dynamicTailSize; -+} -+gcsCOMMAND_BUFFER_INFO; -+ -+/******************************************************************************\ -+******************************** Task Structures ******************************* -+\******************************************************************************/ -+ -+typedef enum _gceTASK -+{ -+ gcvTASK_LINK, -+ gcvTASK_CLUSTER, -+ gcvTASK_INCREMENT, -+ gcvTASK_DECREMENT, -+ gcvTASK_SIGNAL, -+ gcvTASK_LOCKDOWN, -+ gcvTASK_UNLOCK_VIDEO_MEMORY, -+ gcvTASK_FREE_VIDEO_MEMORY, -+ gcvTASK_FREE_CONTIGUOUS_MEMORY, -+ gcvTASK_UNMAP_USER_MEMORY -+} -+gceTASK; -+ -+typedef struct _gcsTASK_HEADER * gcsTASK_HEADER_PTR; -+typedef struct _gcsTASK_HEADER -+{ -+ /* Task ID. */ -+ IN gceTASK id; -+} -+gcsTASK_HEADER; -+ -+typedef struct _gcsTASK_LINK * gcsTASK_LINK_PTR; -+typedef struct _gcsTASK_LINK -+{ -+ /* Task ID (gcvTASK_LINK). */ -+ IN gceTASK id; -+ -+ /* Pointer to the next task container. */ -+ IN gctPOINTER cotainer; -+ -+ /* Pointer to the next task from the next task container. */ -+ IN gcsTASK_HEADER_PTR task; -+} -+gcsTASK_LINK; -+ -+typedef struct _gcsTASK_CLUSTER * gcsTASK_CLUSTER_PTR; -+typedef struct _gcsTASK_CLUSTER -+{ -+ /* Task ID (gcvTASK_CLUSTER). */ -+ IN gceTASK id; -+ -+ /* Number of tasks in the cluster. */ -+ IN gctUINT taskCount; -+} -+gcsTASK_CLUSTER; -+ -+typedef struct _gcsTASK_INCREMENT * gcsTASK_INCREMENT_PTR; -+typedef struct _gcsTASK_INCREMENT -+{ -+ /* Task ID (gcvTASK_INCREMENT). */ -+ IN gceTASK id; -+ -+ /* Address of the variable to increment. */ -+ IN gctUINT32 address; -+} -+gcsTASK_INCREMENT; -+ -+typedef struct _gcsTASK_DECREMENT * gcsTASK_DECREMENT_PTR; -+typedef struct _gcsTASK_DECREMENT -+{ -+ /* Task ID (gcvTASK_DECREMENT). */ -+ IN gceTASK id; -+ -+ /* Address of the variable to decrement. */ -+ IN gctUINT32 address; -+} -+gcsTASK_DECREMENT; -+ -+typedef struct _gcsTASK_SIGNAL * gcsTASK_SIGNAL_PTR; -+typedef struct _gcsTASK_SIGNAL -+{ -+ /* Task ID (gcvTASK_SIGNAL). */ -+ IN gceTASK id; -+ -+ /* Process owning the signal. */ -+ IN gctHANDLE process; -+ -+ /* Signal handle to signal. */ -+ IN gctSIGNAL signal; -+} -+gcsTASK_SIGNAL; -+ -+typedef struct _gcsTASK_LOCKDOWN * gcsTASK_LOCKDOWN_PTR; -+typedef struct _gcsTASK_LOCKDOWN -+{ -+ /* Task ID (gcvTASK_LOCKDOWN). */ -+ IN gceTASK id; -+ -+ /* Address of the user space counter. */ -+ IN gctUINT32 userCounter; -+ -+ /* Address of the kernel space counter. */ -+ IN gctUINT32 kernelCounter; -+ -+ /* Process owning the signal. */ -+ IN gctHANDLE process; -+ -+ /* Signal handle to signal. */ -+ IN gctSIGNAL signal; -+} -+gcsTASK_LOCKDOWN; -+ -+typedef struct _gcsTASK_UNLOCK_VIDEO_MEMORY * gcsTASK_UNLOCK_VIDEO_MEMORY_PTR; -+typedef struct _gcsTASK_UNLOCK_VIDEO_MEMORY -+{ -+ /* Task ID (gcvTASK_UNLOCK_VIDEO_MEMORY). */ -+ IN gceTASK id; -+ -+ /* Allocated video memory. */ -+ IN gctUINT64 node; -+} -+gcsTASK_UNLOCK_VIDEO_MEMORY; -+ -+typedef struct _gcsTASK_FREE_VIDEO_MEMORY * gcsTASK_FREE_VIDEO_MEMORY_PTR; -+typedef struct _gcsTASK_FREE_VIDEO_MEMORY -+{ -+ /* Task ID (gcvTASK_FREE_VIDEO_MEMORY). */ -+ IN gceTASK id; -+ -+ /* Allocated video memory. */ -+ IN gctUINT32 node; -+} -+gcsTASK_FREE_VIDEO_MEMORY; -+ -+typedef struct _gcsTASK_FREE_CONTIGUOUS_MEMORY * gcsTASK_FREE_CONTIGUOUS_MEMORY_PTR; -+typedef struct _gcsTASK_FREE_CONTIGUOUS_MEMORY -+{ -+ /* Task ID (gcvTASK_FREE_CONTIGUOUS_MEMORY). */ -+ IN gceTASK id; -+ -+ /* Number of bytes allocated. */ -+ IN gctSIZE_T bytes; -+ -+ /* Physical address of allocation. */ -+ IN gctPHYS_ADDR physical; -+ -+ /* Logical address of allocation. */ -+ IN gctPOINTER logical; -+} -+gcsTASK_FREE_CONTIGUOUS_MEMORY; -+ -+typedef struct _gcsTASK_UNMAP_USER_MEMORY * gcsTASK_UNMAP_USER_MEMORY_PTR; -+typedef struct _gcsTASK_UNMAP_USER_MEMORY -+{ -+ /* Task ID (gcvTASK_UNMAP_USER_MEMORY). */ -+ IN gceTASK id; -+ -+ /* Base address of user memory to unmap. */ -+ IN gctPOINTER memory; -+ -+ /* Size of user memory in bytes to unmap. */ -+ IN gctSIZE_T size; -+ -+ /* Info record returned by gcvHAL_MAP_USER_MEMORY. */ -+ IN gctPOINTER info; -+ -+ /* Physical address of mapped memory as returned by -+ gcvHAL_MAP_USER_MEMORY. */ -+ IN gctUINT32 address; -+} -+gcsTASK_UNMAP_USER_MEMORY; -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* __gc_hal_driver_h_ */ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_dump.h linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_dump.h ---- linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_dump.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_dump.h 2015-11-30 17:56:13.588137194 +0100 -@@ -0,0 +1,89 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#ifndef __gc_hal_dump_h_ -+#define __gc_hal_dump_h_ -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+/* -+** FILE LAYOUT: -+** -+** gcsDUMP_FILE structure -+** -+** gcsDUMP_DATA frame -+** gcsDUMP_DATA or gcDUMP_DATA_SIZE records rendingring the frame -+** gctUINT8 data[length] -+*/ -+ -+#define gcvDUMP_FILE_SIGNATURE gcmCC('g','c','D','B') -+ -+typedef struct _gcsDUMP_FILE -+{ -+ gctUINT32 signature; /* File signature */ -+ gctSIZE_T length; /* Length of file */ -+ gctUINT32 frames; /* Number of frames in file */ -+} -+gcsDUMP_FILE; -+ -+typedef enum _gceDUMP_TAG -+{ -+ gcvTAG_SURFACE = gcmCC('s','u','r','f'), -+ gcvTAG_FRAME = gcmCC('f','r','m',' '), -+ gcvTAG_COMMAND = gcmCC('c','m','d',' '), -+ gcvTAG_INDEX = gcmCC('i','n','d','x'), -+ gcvTAG_STREAM = gcmCC('s','t','r','m'), -+ gcvTAG_TEXTURE = gcmCC('t','e','x','t'), -+ gcvTAG_RENDER_TARGET = gcmCC('r','n','d','r'), -+ gcvTAG_DEPTH = gcmCC('z','b','u','f'), -+ gcvTAG_RESOLVE = gcmCC('r','s','l','v'), -+ gcvTAG_DELETE = gcmCC('d','e','l',' '), -+ gcvTAG_BUFOBJ = gcmCC('b','u','f','o'), -+} -+gceDUMP_TAG; -+ -+typedef struct _gcsDUMP_SURFACE -+{ -+ gceDUMP_TAG type; /* Type of record. */ -+ gctUINT32 address; /* Address of the surface. */ -+ gctINT16 width; /* Width of surface. */ -+ gctINT16 height; /* Height of surface. */ -+ gceSURF_FORMAT format; /* Surface pixel format. */ -+ gctSIZE_T length; /* Number of bytes inside the surface. */ -+} -+gcsDUMP_SURFACE; -+ -+typedef struct _gcsDUMP_DATA -+{ -+ gceDUMP_TAG type; /* Type of record. */ -+ gctSIZE_T length; /* Number of bytes of data. */ -+ gctUINT32 address; /* Address for the data. */ -+} -+gcsDUMP_DATA; -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* __gc_hal_dump_h_ */ -+ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_eglplatform.h linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_eglplatform.h ---- linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_eglplatform.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_eglplatform.h 2015-11-30 17:56:13.588137194 +0100 -@@ -0,0 +1,651 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#ifndef __gc_hal_eglplatform_h_ -+#define __gc_hal_eglplatform_h_ -+ -+/* Include VDK types. */ -+#include "gc_hal_types.h" -+#include "gc_hal_base.h" -+#include "gc_hal_eglplatform_type.h" -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+#if defined(LINUX) && defined(EGL_API_DFB) -+#include -+typedef struct _DFBDisplay * HALNativeDisplayType; -+typedef struct _DFBWindow * HALNativeWindowType; -+typedef struct _DFBPixmap * HALNativePixmapType; -+ -+#elif defined(LINUX) && defined(EGL_API_FB) -+ -+#if defined(EGL_API_WL) -+ -+#if defined(__GNUC__) -+# define inline __inline__ /* GNU keyword. */ -+#endif -+ -+/* Wayland platform. */ -+#include -+ -+#define WL_EGL_NUM_BACKBUFFERS 3 -+ -+typedef struct _gcsWL_VIV_BUFFER -+{ -+ struct wl_resource *wl_buffer; -+ gcoSURF surface; -+ gctINT32 width, height; -+} gcsWL_VIV_BUFFER; -+ -+typedef struct _gcsWL_EGL_DISPLAY -+{ -+ struct wl_display* wl_display; -+ struct wl_viv* wl_viv; -+ struct wl_registry *registry; -+ struct wl_event_queue *wl_queue; -+ gctINT swapInterval; -+} gcsWL_EGL_DISPLAY; -+ -+typedef struct _gcsWL_EGL_BUFFER_INFO -+{ -+ gctINT32 width; -+ gctINT32 height; -+ gctINT32 stride; -+ gceSURF_FORMAT format; -+ gcuVIDMEM_NODE_PTR node; -+ gcePOOL pool; -+ gctUINT bytes; -+ gcoSURF surface; -+ gcoSURF attached_surface; -+ gctINT32 invalidate; -+ gctBOOL locked; -+} gcsWL_EGL_BUFFER_INFO; -+ -+typedef struct _gcsWL_EGL_BUFFER -+{ -+ struct wl_buffer* wl_buffer; -+ gcsWL_EGL_BUFFER_INFO info; -+} gcsWL_EGL_BUFFER; -+ -+typedef struct _gcsWL_EGL_WINDOW_INFO -+{ -+ gctINT32 dx; -+ gctINT32 dy; -+ gctUINT width; -+ gctUINT height; -+ gctINT32 attached_width; -+ gctINT32 attached_height; -+ gceSURF_FORMAT format; -+ gctUINT bpp; -+} gcsWL_EGL_WINDOW_INFO; -+ -+struct wl_egl_window -+{ -+ gcsWL_EGL_DISPLAY* display; -+ gcsWL_EGL_BUFFER backbuffers[WL_EGL_NUM_BACKBUFFERS]; -+ gcsWL_EGL_WINDOW_INFO info; -+ gctUINT current; -+ struct wl_surface* surface; -+ struct wl_callback* frame_callback; -+}; -+ -+typedef void* HALNativeDisplayType; -+typedef void* HALNativeWindowType; -+typedef void* HALNativePixmapType; -+#else -+/* Linux platform for FBDEV. */ -+typedef struct _FBDisplay * HALNativeDisplayType; -+typedef struct _FBWindow * HALNativeWindowType; -+typedef struct _FBPixmap * HALNativePixmapType; -+#endif -+#elif defined(__ANDROID__) || defined(ANDROID) -+ -+struct egl_native_pixmap_t; -+ -+#if ANDROID_SDK_VERSION >= 9 -+ #include -+ -+ typedef struct ANativeWindow* HALNativeWindowType; -+ typedef struct egl_native_pixmap_t* HALNativePixmapType; -+ typedef void* HALNativeDisplayType; -+#else -+ struct android_native_window_t; -+ typedef struct android_native_window_t* HALNativeWindowType; -+ typedef struct egl_native_pixmap_t * HALNativePixmapType; -+ typedef void* HALNativeDisplayType; -+#endif -+ -+#elif defined(LINUX) -+/* X11 platform. */ -+#include -+#include -+ -+typedef Display * HALNativeDisplayType; -+typedef Window HALNativeWindowType; -+ -+#ifdef CUSTOM_PIXMAP -+typedef void * HALNativePixmapType; -+#else -+typedef Pixmap HALNativePixmapType; -+#endif /* CUSTOM_PIXMAP */ -+ -+/* Rename some badly named X defines. */ -+#ifdef Status -+# define XStatus int -+# undef Status -+#endif -+#ifdef Always -+# define XAlways 2 -+# undef Always -+#endif -+#ifdef CurrentTime -+# undef CurrentTime -+# define XCurrentTime 0 -+#endif -+ -+#else -+ -+#error "Platform not recognized" -+ -+/* VOID */ -+typedef void * HALNativeDisplayType; -+typedef void * HALNativeWindowType; -+typedef void * HALNativePixmapType; -+ -+#endif -+ -+/* define DUMMY according to the system */ -+#if defined(EGL_API_WL) -+# define WL_DUMMY (31415926) -+# define EGL_DUMMY WL_DUMMY -+#elif defined(__ANDROID__) || defined(ANDROID) -+# define ANDROID_DUMMY (31415926) -+# define EGL_DUMMY ANDROID_DUMMY -+#else -+# define EGL_DUMMY (31415926) -+#endif -+ -+/******************************************************************************* -+** Display. ******************************************************************** -+*/ -+ -+gceSTATUS -+gcoOS_GetDisplay( -+ OUT HALNativeDisplayType * Display, -+ IN gctPOINTER Context -+ ); -+ -+gceSTATUS -+gcoOS_GetDisplayByIndex( -+ IN gctINT DisplayIndex, -+ OUT HALNativeDisplayType * Display, -+ IN gctPOINTER Context -+ ); -+ -+gceSTATUS -+gcoOS_GetDisplayInfo( -+ IN HALNativeDisplayType Display, -+ OUT gctINT * Width, -+ OUT gctINT * Height, -+ OUT gctSIZE_T * Physical, -+ OUT gctINT * Stride, -+ OUT gctINT * BitsPerPixel -+ ); -+ -+ -+ -+gceSTATUS -+gcoOS_GetDisplayInfoEx( -+ IN HALNativeDisplayType Display, -+ IN HALNativeWindowType Window, -+ IN gctUINT DisplayInfoSize, -+ OUT halDISPLAY_INFO * DisplayInfo -+ ); -+ -+gceSTATUS -+gcoOS_GetNextDisplayInfoExByIndex( -+ IN gctINT Index, -+ IN HALNativeDisplayType Display, -+ IN HALNativeWindowType Window, -+ IN gctUINT DisplayInfoSize, -+ OUT halDISPLAY_INFO * DisplayInfo -+ ); -+ -+gceSTATUS -+gcoOS_GetDisplayVirtual( -+ IN HALNativeDisplayType Display, -+ OUT gctINT * Width, -+ OUT gctINT * Height -+ ); -+ -+gceSTATUS -+gcoOS_GetDisplayBackbuffer( -+ IN HALNativeDisplayType Display, -+ IN HALNativeWindowType Window, -+ OUT gctPOINTER * context, -+ OUT gcoSURF * surface, -+ OUT gctUINT * Offset, -+ OUT gctINT * X, -+ OUT gctINT * Y -+ ); -+ -+gceSTATUS -+gcoOS_SetDisplayVirtual( -+ IN HALNativeDisplayType Display, -+ IN HALNativeWindowType Window, -+ IN gctUINT Offset, -+ IN gctINT X, -+ IN gctINT Y -+ ); -+ -+gceSTATUS -+gcoOS_SetDisplayVirtualEx( -+ IN HALNativeDisplayType Display, -+ IN HALNativeWindowType Window, -+ IN gctPOINTER Context, -+ IN gcoSURF Surface, -+ IN gctUINT Offset, -+ IN gctINT X, -+ IN gctINT Y -+ ); -+ -+gceSTATUS -+gcoOS_SetSwapInterval( -+ IN HALNativeDisplayType Display, -+ IN gctINT Interval -+); -+ -+gceSTATUS -+gcoOS_SetSwapIntervalEx( -+ IN HALNativeDisplayType Display, -+ IN gctINT Interval, -+ IN gctPOINTER localDisplay); -+ -+gceSTATUS -+gcoOS_GetSwapInterval( -+ IN HALNativeDisplayType Display, -+ IN gctINT_PTR Min, -+ IN gctINT_PTR Max -+); -+ -+gceSTATUS -+gcoOS_DisplayBufferRegions( -+ IN HALNativeDisplayType Display, -+ IN HALNativeWindowType Window, -+ IN gctINT NumRects, -+ IN gctINT_PTR Rects -+ ); -+ -+gceSTATUS -+gcoOS_DestroyDisplay( -+ IN HALNativeDisplayType Display -+ ); -+ -+gceSTATUS -+gcoOS_InitLocalDisplayInfo( -+ IN HALNativeDisplayType Display, -+ IN OUT gctPOINTER * localDisplay -+ ); -+ -+gceSTATUS -+gcoOS_DeinitLocalDisplayInfo( -+ IN HALNativeDisplayType Display, -+ IN OUT gctPOINTER * localDisplay -+ ); -+ -+gceSTATUS -+gcoOS_GetDisplayInfoEx2( -+ IN HALNativeDisplayType Display, -+ IN HALNativeWindowType Window, -+ IN gctPOINTER localDisplay, -+ IN gctUINT DisplayInfoSize, -+ OUT halDISPLAY_INFO * DisplayInfo -+ ); -+ -+gceSTATUS -+gcoOS_GetDisplayBackbufferEx( -+ IN HALNativeDisplayType Display, -+ IN HALNativeWindowType Window, -+ IN gctPOINTER localDisplay, -+ OUT gctPOINTER * context, -+ OUT gcoSURF * surface, -+ OUT gctUINT * Offset, -+ OUT gctINT * X, -+ OUT gctINT * Y -+ ); -+ -+gceSTATUS -+gcoOS_IsValidDisplay( -+ IN HALNativeDisplayType Display -+ ); -+ -+gceSTATUS -+gcoOS_GetNativeVisualId( -+ IN HALNativeDisplayType Display, -+ OUT gctINT* nativeVisualId -+ ); -+ -+gctBOOL -+gcoOS_SynchronousFlip( -+ IN HALNativeDisplayType Display -+ ); -+ -+/******************************************************************************* -+** Windows. ******************************************************************** -+*/ -+ -+gceSTATUS -+gcoOS_CreateWindow( -+ IN HALNativeDisplayType Display, -+ IN gctINT X, -+ IN gctINT Y, -+ IN gctINT Width, -+ IN gctINT Height, -+ OUT HALNativeWindowType * Window -+ ); -+ -+gceSTATUS -+gcoOS_GetWindowInfo( -+ IN HALNativeDisplayType Display, -+ IN HALNativeWindowType Window, -+ OUT gctINT * X, -+ OUT gctINT * Y, -+ OUT gctINT * Width, -+ OUT gctINT * Height, -+ OUT gctINT * BitsPerPixel, -+ OUT gctUINT * Offset -+ ); -+ -+gceSTATUS -+gcoOS_DestroyWindow( -+ IN HALNativeDisplayType Display, -+ IN HALNativeWindowType Window -+ ); -+ -+gceSTATUS -+gcoOS_DrawImage( -+ IN HALNativeDisplayType Display, -+ IN HALNativeWindowType Window, -+ IN gctINT Left, -+ IN gctINT Top, -+ IN gctINT Right, -+ IN gctINT Bottom, -+ IN gctINT Width, -+ IN gctINT Height, -+ IN gctINT BitsPerPixel, -+ IN gctPOINTER Bits -+ ); -+ -+gceSTATUS -+gcoOS_GetImage( -+ IN HALNativeWindowType Window, -+ IN gctINT Left, -+ IN gctINT Top, -+ IN gctINT Right, -+ IN gctINT Bottom, -+ OUT gctINT * BitsPerPixel, -+ OUT gctPOINTER * Bits -+ ); -+ -+gceSTATUS -+gcoOS_GetWindowInfoEx( -+ IN HALNativeDisplayType Display, -+ IN HALNativeWindowType Window, -+ OUT gctINT * X, -+ OUT gctINT * Y, -+ OUT gctINT * Width, -+ OUT gctINT * Height, -+ OUT gctINT * BitsPerPixel, -+ OUT gctUINT * Offset, -+ OUT gceSURF_FORMAT * Format -+ ); -+ -+gceSTATUS -+gcoOS_DrawImageEx( -+ IN HALNativeDisplayType Display, -+ IN HALNativeWindowType Window, -+ IN gctINT Left, -+ IN gctINT Top, -+ IN gctINT Right, -+ IN gctINT Bottom, -+ IN gctINT Width, -+ IN gctINT Height, -+ IN gctINT BitsPerPixel, -+ IN gctPOINTER Bits, -+ IN gceSURF_FORMAT Format -+ ); -+ -+/******************************************************************************* -+** Pixmaps. ******************************************************************** -+*/ -+ -+gceSTATUS -+gcoOS_CreatePixmap( -+ IN HALNativeDisplayType Display, -+ IN gctINT Width, -+ IN gctINT Height, -+ IN gctINT BitsPerPixel, -+ OUT HALNativePixmapType * Pixmap -+ ); -+ -+gceSTATUS -+gcoOS_GetPixmapInfo( -+ IN HALNativeDisplayType Display, -+ IN HALNativePixmapType Pixmap, -+ OUT gctINT * Width, -+ OUT gctINT * Height, -+ OUT gctINT * BitsPerPixel, -+ OUT gctINT * Stride, -+ OUT gctPOINTER * Bits -+ ); -+ -+gceSTATUS -+gcoOS_DrawPixmap( -+ IN HALNativeDisplayType Display, -+ IN HALNativePixmapType Pixmap, -+ IN gctINT Left, -+ IN gctINT Top, -+ IN gctINT Right, -+ IN gctINT Bottom, -+ IN gctINT Width, -+ IN gctINT Height, -+ IN gctINT BitsPerPixel, -+ IN gctPOINTER Bits -+ ); -+ -+gceSTATUS -+gcoOS_DestroyPixmap( -+ IN HALNativeDisplayType Display, -+ IN HALNativePixmapType Pixmap -+ ); -+ -+gceSTATUS -+gcoOS_GetPixmapInfoEx( -+ IN HALNativeDisplayType Display, -+ IN HALNativePixmapType Pixmap, -+ OUT gctINT * Width, -+ OUT gctINT * Height, -+ OUT gctINT * BitsPerPixel, -+ OUT gctINT * Stride, -+ OUT gctPOINTER * Bits, -+ OUT gceSURF_FORMAT * Format -+ ); -+ -+gceSTATUS -+gcoOS_CopyPixmapBits( -+ IN HALNativeDisplayType Display, -+ IN HALNativePixmapType Pixmap, -+ IN gctUINT DstWidth, -+ IN gctUINT DstHeight, -+ IN gctINT DstStride, -+ IN gceSURF_FORMAT DstFormat, -+ OUT gctPOINTER DstBits -+ ); -+ -+/******************************************************************************* -+** OS relative. **************************************************************** -+*/ -+gceSTATUS -+gcoOS_LoadEGLLibrary( -+ OUT gctHANDLE * Handle -+ ); -+ -+gceSTATUS -+gcoOS_FreeEGLLibrary( -+ IN gctHANDLE Handle -+ ); -+ -+gceSTATUS -+gcoOS_ShowWindow( -+ IN HALNativeDisplayType Display, -+ IN HALNativeWindowType Window -+ ); -+ -+gceSTATUS -+gcoOS_HideWindow( -+ IN HALNativeDisplayType Display, -+ IN HALNativeWindowType Window -+ ); -+ -+gceSTATUS -+gcoOS_SetWindowTitle( -+ IN HALNativeDisplayType Display, -+ IN HALNativeWindowType Window, -+ IN gctCONST_STRING Title -+ ); -+ -+gceSTATUS -+gcoOS_CapturePointer( -+ IN HALNativeDisplayType Display, -+ IN HALNativeWindowType Window -+ ); -+ -+gceSTATUS -+gcoOS_GetEvent( -+ IN HALNativeDisplayType Display, -+ IN HALNativeWindowType Window, -+ OUT halEvent * Event -+ ); -+ -+gceSTATUS -+gcoOS_CreateClientBuffer( -+ IN gctINT Width, -+ IN gctINT Height, -+ IN gctINT Format, -+ IN gctINT Type, -+ OUT gctPOINTER * ClientBuffer -+ ); -+ -+gceSTATUS -+gcoOS_GetClientBufferInfo( -+ IN gctPOINTER ClientBuffer, -+ OUT gctINT * Width, -+ OUT gctINT * Height, -+ OUT gctINT * Stride, -+ OUT gctPOINTER * Bits -+ ); -+ -+gceSTATUS -+gcoOS_DestroyClientBuffer( -+ IN gctPOINTER ClientBuffer -+ ); -+ -+gceSTATUS -+gcoOS_DestroyContext( -+ IN gctPOINTER Display, -+ IN gctPOINTER Context -+ ); -+ -+gceSTATUS -+gcoOS_CreateContext( -+ IN gctPOINTER LocalDisplay, -+ IN gctPOINTER Context -+ ); -+ -+gceSTATUS -+gcoOS_MakeCurrent( -+ IN gctPOINTER LocalDisplay, -+ IN HALNativeWindowType DrawDrawable, -+ IN HALNativeWindowType ReadDrawable, -+ IN gctPOINTER Context, -+ IN gcoSURF ResolveTarget -+ ); -+ -+gceSTATUS -+gcoOS_CreateDrawable( -+ IN gctPOINTER LocalDisplay, -+ IN HALNativeWindowType Drawable -+ ); -+ -+gceSTATUS -+gcoOS_DestroyDrawable( -+ IN gctPOINTER LocalDisplay, -+ IN HALNativeWindowType Drawable -+ ); -+gceSTATUS -+gcoOS_SwapBuffers( -+ IN gctPOINTER LocalDisplay, -+ IN HALNativeWindowType Drawable, -+ IN gcoSURF RenderTarget, -+ IN gcoSURF ResolveTarget, -+ IN gctPOINTER ResolveBits, -+ OUT gctUINT *Width, -+ OUT gctUINT *Height -+ ); -+ -+#ifdef EGL_API_DRI -+gceSTATUS -+gcoOS_ResizeWindow( -+ IN gctPOINTER localDisplay, -+ IN HALNativeWindowType Drawable, -+ IN gctUINT Width, -+ IN gctUINT Height) -+ ; -+ -+#ifdef USE_FREESCALE_EGL_ACCEL -+gceSTATUS -+gcoOS_SwapBuffersGeneric_Async( -+ IN gctPOINTER localDisplay, -+ IN HALNativeWindowType Drawable, -+ IN gcoSURF RenderTarget, -+ IN gcoSURF ResolveTarget, -+ IN gctPOINTER ResolveBits, -+ OUT gctUINT *Width, -+ OUT gctUINT *Height, -+ IN void * resolveRect -+ ); -+ -+gceSTATUS -+gcoOS_DrawSurface( -+ IN gctPOINTER localDisplay, -+ IN HALNativeWindowType Drawable -+ ); -+#endif -+ -+#endif -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* __gc_hal_eglplatform_h_ */ -+ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_eglplatform_type.h linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_eglplatform_type.h ---- linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_eglplatform_type.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_eglplatform_type.h 2015-11-30 17:56:13.588137194 +0100 -@@ -0,0 +1,280 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#ifndef __gc_hal_eglplatform_type_h_ -+#define __gc_hal_eglplatform_type_h_ -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+/******************************************************************************* -+** Events. ********************************************************************* -+*/ -+ -+typedef enum _halEventType -+{ -+ /* Keyboard event. */ -+ HAL_KEYBOARD, -+ -+ /* Mouse move event. */ -+ HAL_POINTER, -+ -+ /* Mouse button event. */ -+ HAL_BUTTON, -+ -+ /* Application close event. */ -+ HAL_CLOSE, -+ -+ /* Application window has been updated. */ -+ HAL_WINDOW_UPDATE -+} -+halEventType; -+ -+/* Scancodes for keyboard. */ -+typedef enum _halKeys -+{ -+ HAL_UNKNOWN = -1, -+ -+ HAL_BACKSPACE = 0x08, -+ HAL_TAB, -+ HAL_ENTER = 0x0D, -+ HAL_ESCAPE = 0x1B, -+ -+ HAL_SPACE = 0x20, -+ HAL_SINGLEQUOTE = 0x27, -+ HAL_PAD_ASTERISK = 0x2A, -+ HAL_COMMA = 0x2C, -+ HAL_HYPHEN, -+ HAL_PERIOD, -+ HAL_SLASH, -+ HAL_0, -+ HAL_1, -+ HAL_2, -+ HAL_3, -+ HAL_4, -+ HAL_5, -+ HAL_6, -+ HAL_7, -+ HAL_8, -+ HAL_9, -+ HAL_SEMICOLON = 0x3B, -+ HAL_EQUAL = 0x3D, -+ HAL_A = 0x41, -+ HAL_B, -+ HAL_C, -+ HAL_D, -+ HAL_E, -+ HAL_F, -+ HAL_G, -+ HAL_H, -+ HAL_I, -+ HAL_J, -+ HAL_K, -+ HAL_L, -+ HAL_M, -+ HAL_N, -+ HAL_O, -+ HAL_P, -+ HAL_Q, -+ HAL_R, -+ HAL_S, -+ HAL_T, -+ HAL_U, -+ HAL_V, -+ HAL_W, -+ HAL_X, -+ HAL_Y, -+ HAL_Z, -+ HAL_LBRACKET, -+ HAL_BACKSLASH, -+ HAL_RBRACKET, -+ HAL_BACKQUOTE = 0x60, -+ -+ HAL_F1 = 0x80, -+ HAL_F2, -+ HAL_F3, -+ HAL_F4, -+ HAL_F5, -+ HAL_F6, -+ HAL_F7, -+ HAL_F8, -+ HAL_F9, -+ HAL_F10, -+ HAL_F11, -+ HAL_F12, -+ -+ HAL_LCTRL, -+ HAL_RCTRL, -+ HAL_LSHIFT, -+ HAL_RSHIFT, -+ HAL_LALT, -+ HAL_RALT, -+ HAL_CAPSLOCK, -+ HAL_NUMLOCK, -+ HAL_SCROLLLOCK, -+ HAL_PAD_0, -+ HAL_PAD_1, -+ HAL_PAD_2, -+ HAL_PAD_3, -+ HAL_PAD_4, -+ HAL_PAD_5, -+ HAL_PAD_6, -+ HAL_PAD_7, -+ HAL_PAD_8, -+ HAL_PAD_9, -+ HAL_PAD_HYPHEN, -+ HAL_PAD_PLUS, -+ HAL_PAD_SLASH, -+ HAL_PAD_PERIOD, -+ HAL_PAD_ENTER, -+ HAL_SYSRQ, -+ HAL_PRNTSCRN, -+ HAL_BREAK, -+ HAL_UP, -+ HAL_LEFT, -+ HAL_RIGHT, -+ HAL_DOWN, -+ HAL_HOME, -+ HAL_END, -+ HAL_PGUP, -+ HAL_PGDN, -+ HAL_INSERT, -+ HAL_DELETE, -+ HAL_LWINDOW, -+ HAL_RWINDOW, -+ HAL_MENU, -+ HAL_POWER, -+ HAL_SLEEP, -+ HAL_WAKE -+} -+halKeys; -+ -+/* Structure that defined keyboard mapping. */ -+typedef struct _halKeyMap -+{ -+ /* Normal key. */ -+ halKeys normal; -+ -+ /* Extended key. */ -+ halKeys extended; -+} -+halKeyMap; -+ -+/* Event structure. */ -+typedef struct _halEvent -+{ -+ /* Event type. */ -+ halEventType type; -+ -+ /* Event data union. */ -+ union _halEventData -+ { -+ /* Event data for keyboard. */ -+ struct _halKeyboard -+ { -+ /* Scancode. */ -+ halKeys scancode; -+ -+ /* ASCII characte of the key pressed. */ -+ char key; -+ -+ /* Flag whether the key was pressed (1) or released (0). */ -+ char pressed; -+ } -+ keyboard; -+ -+ /* Event data for pointer. */ -+ struct _halPointer -+ { -+ /* Current pointer coordinate. */ -+ int x; -+ int y; -+ } -+ pointer; -+ -+ /* Event data for mouse buttons. */ -+ struct _halButton -+ { -+ /* Left button state. */ -+ int left; -+ -+ /* Middle button state. */ -+ int middle; -+ -+ /* Right button state. */ -+ int right; -+ -+ /* Current pointer coordinate. */ -+ int x; -+ int y; -+ } -+ button; -+ } -+ data; -+} -+halEvent; -+ -+/* VFK_DISPLAY_INFO structure defining information returned by -+ vdkGetDisplayInfoEx. */ -+typedef struct _halDISPLAY_INFO -+{ -+ /* The size of the display in pixels. */ -+ int width; -+ int height; -+ -+ /* The stride of the dispay. -1 is returned if the stride is not known -+ ** for the specified display.*/ -+ int stride; -+ -+ /* The color depth of the display in bits per pixel. */ -+ int bitsPerPixel; -+ -+ /* The logical pointer to the display memory buffer. NULL is returned -+ ** if the pointer is not known for the specified display. */ -+ void * logical; -+ -+ /* The physical address of the display memory buffer. ~0 is returned -+ ** if the address is not known for the specified display. */ -+ unsigned long physical; -+ -+ int wrapFB; /* true if compositor, false otherwise. */ -+ -+ /* The color info of the display. */ -+ unsigned int alphaLength; -+ unsigned int alphaOffset; -+ unsigned int redLength; -+ unsigned int redOffset; -+ unsigned int greenLength; -+ unsigned int greenOffset; -+ unsigned int blueLength; -+ unsigned int blueOffset; -+ -+ /* Display flip support. */ -+ int flip; -+} -+halDISPLAY_INFO; -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* __gc_hal_eglplatform_type_h_ */ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_engine.h linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_engine.h ---- linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_engine.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_engine.h 2015-11-30 17:56:13.588137194 +0100 -@@ -0,0 +1,2587 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#ifndef __gc_hal_engine_h_ -+#define __gc_hal_engine_h_ -+ -+#include "gc_hal_types.h" -+#include "gc_hal_enum.h" -+ -+#if gcdENABLE_3D -+#if gcdENABLE_VG -+#include "gc_hal_engine_vg.h" -+#endif -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+/******************************************************************************\ -+****************************** Object Declarations ***************************** -+\******************************************************************************/ -+ -+typedef struct _gcoSTREAM * gcoSTREAM; -+typedef struct _gcoVERTEX * gcoVERTEX; -+typedef struct _gcoTEXTURE * gcoTEXTURE; -+typedef struct _gcoINDEX * gcoINDEX; -+typedef struct _gcsVERTEX_ATTRIBUTES * gcsVERTEX_ATTRIBUTES_PTR; -+typedef struct _gcoVERTEXARRAY * gcoVERTEXARRAY; -+typedef struct _gcoBUFOBJ * gcoBUFOBJ; -+ -+#define gcdATTRIBUTE_COUNT 16 -+ -+typedef enum _gcePROGRAM_STAGE -+{ -+ gcvPROGRAM_STAGE_VERTEX = 0x0, -+ gcvPROGRAM_STAGE_TES = 0x1, -+ gcvPROGRAM_STAGE_TCS = 0x2, -+ gcvPROGRAM_STAGE_GEOMETRY = 0x3, -+ gcvPROGRAM_STAGE_FRAGMENT = 0x4, -+ gcvPROGRAM_STAGE_COMPUTE = 0x5, -+ gcvPROGRAM_STAGE_OPENCL = 0x6, -+ gcvPROGRAM_STAGE_LAST -+} -+gcePROGRAM_STAGE; -+ -+typedef enum _gcePROGRAM_STAGE_BIT -+{ -+ gcvPROGRAM_STAGE_VERTEX_BIT = 1 << gcvPROGRAM_STAGE_VERTEX, -+ gcvPROGRAM_STAGE_TES_BIT = 1 << gcvPROGRAM_STAGE_TES, -+ gcvPROGRAM_STAGE_TCS_BIT = 1 << gcvPROGRAM_STAGE_TCS, -+ gcvPROGRAM_STAGE_GEOMETRY_BIT = 1 << gcvPROGRAM_STAGE_GEOMETRY, -+ gcvPROGRAM_STAGE_FRAGMENT_BIT = 1 << gcvPROGRAM_STAGE_FRAGMENT, -+ gcvPROGRAM_STAGE_COMPUTE_BIT = 1 << gcvPROGRAM_STAGE_COMPUTE, -+ gcvPROGRAM_STAGE_OPENCL_BIT = 1 << gcvPROGRAM_STAGE_OPENCL, -+} -+gcePROGRAM_STAGE_BIT; -+ -+ -+/******************************************************************************\ -+********************************* gcoHAL Object ********************************* -+\******************************************************************************/ -+ -+gceSTATUS -+gcoHAL_QueryShaderCaps( -+ IN gcoHAL Hal, -+ OUT gctUINT * VertexUniforms, -+ OUT gctUINT * FragmentUniforms, -+ OUT gctUINT * Varyings -+ ); -+ -+gceSTATUS -+gcoHAL_QueryShaderCapsEx( -+ IN gcoHAL Hal, -+ OUT gctUINT * ShaderCoreCount, -+ OUT gctUINT * ThreadCount, -+ OUT gctUINT * VertexInstructionCount, -+ OUT gctUINT * FragmentInstructionCount -+ ); -+ -+gceSTATUS -+gcoHAL_QuerySamplerBase( -+ IN gcoHAL Hal, -+ OUT gctUINT32 * VertexCount, -+ OUT gctINT_PTR VertexBase, -+ OUT gctUINT32 * FragmentCount, -+ OUT gctINT_PTR FragmentBase -+ ); -+ -+gceSTATUS -+gcoHAL_QueryUniformBase( -+ IN gcoHAL Hal, -+ OUT gctUINT32 * VertexBase, -+ OUT gctUINT32 * FragmentBase -+ ); -+ -+gceSTATUS -+gcoHAL_QueryTextureCaps( -+ IN gcoHAL Hal, -+ OUT gctUINT * MaxWidth, -+ OUT gctUINT * MaxHeight, -+ OUT gctUINT * MaxDepth, -+ OUT gctBOOL * Cubic, -+ OUT gctBOOL * NonPowerOfTwo, -+ OUT gctUINT * VertexSamplers, -+ OUT gctUINT * PixelSamplers -+ ); -+ -+gceSTATUS -+gcoHAL_QueryTextureMaxAniso( -+ IN gcoHAL Hal, -+ OUT gctUINT * MaxAnisoValue -+ ); -+ -+gceSTATUS -+gcoHAL_QueryStreamCaps( -+ IN gcoHAL Hal, -+ OUT gctUINT32 * MaxAttributes, -+ OUT gctUINT32 * MaxStreamSize, -+ OUT gctUINT32 * NumberOfStreams, -+ OUT gctUINT32 * Alignment -+ ); -+ -+/******************************************************************************\ -+********************************* gcoSURF Object ******************************** -+\******************************************************************************/ -+ -+/*----------------------------------------------------------------------------*/ -+/*--------------------------------- gcoSURF 3D --------------------------------*/ -+typedef enum _gceBLIT_FLAG -+{ -+ gcvBLIT_FLAG_SKIP_DEPTH_WRITE = 0x1, -+ gcvBLIT_FLAG_SKIP_STENCIL_WRITE = 0x2, -+} gceBLIT_FLAG; -+ -+typedef struct _gcsSURF_BLIT_ARGS -+{ -+ gcoSURF srcSurface; -+ gctINT srcX, srcY, srcZ; -+ gctINT srcWidth, srcHeight, srcDepth; -+ gcoSURF dstSurface; -+ gctINT dstX, dstY, dstZ; -+ gctINT dstWidth, dstHeight, dstDepth; -+ gctBOOL xReverse; -+ gctBOOL yReverse; -+ gctBOOL scissorTest; -+ gcsRECT scissor; -+ gctUINT flags; -+} -+gcsSURF_BLIT_ARGS; -+ -+ -+ -+ -+/* Clear flags. */ -+typedef enum _gceCLEAR -+{ -+ gcvCLEAR_COLOR = 0x1, -+ gcvCLEAR_DEPTH = 0x2, -+ gcvCLEAR_STENCIL = 0x4, -+ gcvCLEAR_HZ = 0x8, -+ gcvCLEAR_HAS_VAA = 0x10, -+ gcvCLEAR_WITH_GPU_ONLY = 0x100, -+ gcvCLEAR_WITH_CPU_ONLY = 0x200, -+} -+gceCLEAR; -+ -+typedef struct _gcsSURF_CLEAR_ARGS -+{ -+ /* -+ ** Color to fill the color portion of the framebuffer when clear -+ ** is called. -+ */ -+ struct { -+ gcuVALUE r; -+ gcuVALUE g; -+ gcuVALUE b; -+ gcuVALUE a; -+ /* -+ ** Color has multiple value type so we must specify it. -+ */ -+ gceVALUE_TYPE valueType; -+ } color; -+ -+ gcuVALUE depth; -+ -+ gctUINT stencil; -+ -+ -+ -+ /* -+ ** stencil bit-wise mask -+ */ -+ gctUINT8 stencilMask; -+ /* -+ ** Depth Write Mask -+ */ -+ gctBOOL depthMask; -+ /* -+ ** 4-bit channel Mask: ABGR:MSB->LSB -+ */ -+ gctUINT8 colorMask; -+ /* -+ ** If ClearRect is NULL, it means full clear -+ */ -+ gcsRECT_PTR clearRect; -+ /* -+ ** clear flags -+ */ -+ gceCLEAR flags; -+ -+ /* -+ ** Offset in surface to cube/array/3D -+ */ -+ gctUINT32 offset; -+ -+} gcsSURF_CLEAR_ARGS; -+ -+ -+typedef gcsSURF_CLEAR_ARGS* gcsSURF_CLEAR_ARGS_PTR; -+ -+typedef struct _gscSURF_BLITDRAW_BLIT -+{ -+ gcoSURF srcSurface; -+ gcoSURF dstSurface; -+ gcsRECT srcRect; -+ gcsRECT dstRect; -+ gceTEXTURE_FILTER filterMode; -+ gctBOOL xReverse; -+ gctBOOL yReverse; -+ gctBOOL scissorEnabled; -+ gcsRECT scissor; -+}gscSURF_BLITDRAW_BLIT; -+ -+ -+typedef enum _gceBLITDRAW_TYPE -+{ -+ gcvBLITDRAW_CLEAR = 0, -+ gcvBLITDRAW_BLIT = 1, -+ -+ /* last number, not a real type */ -+ gcvBLITDRAW_NUM_TYPE -+ } -+gceBLITDRAW_TYPE; -+ -+ -+typedef struct _gscSURF_BLITDRAW_ARGS -+{ -+ /* always the fist member */ -+ gceHAL_ARG_VERSION version; -+ -+ union _gcsSURF_BLITDRAW_ARGS_UNION -+ { -+ struct _gscSURF_BLITDRAW_ARG_v1 -+ { -+ /* Whether it's clear or blit operation, can be extended. */ -+ gceBLITDRAW_TYPE type; -+ -+ union _gscSURF_BLITDRAW_UNION -+ { -+ gscSURF_BLITDRAW_BLIT blit; -+ -+ struct _gscSURF_BLITDRAW_CLEAR -+ { -+ gcsSURF_CLEAR_ARGS clearArgs; -+ gcoSURF rtSurface; -+ gcoSURF dsSurface; -+ } clear; -+ } u; -+ } v1; -+ } uArgs; -+} -+gcsSURF_BLITDRAW_ARGS; -+ -+ -+typedef struct _gcsSURF_RESOLVE_ARGS -+{ -+ gceHAL_ARG_VERSION version; -+ union _gcsSURF_RESOLVE_ARGS_UNION -+ { -+ struct _gcsSURF_RESOLVE_ARG_v1 -+ { -+ gctBOOL yInverted; -+ }v1; -+ } uArgs; -+} -+gcsSURF_RESOLVE_ARGS; -+ -+ -+/* CPU Blit with format (including linear <-> tile) conversion*/ -+gceSTATUS -+gcoSURF_BlitCPU( -+ gcsSURF_BLIT_ARGS* args -+ ); -+ -+ -+gceSTATUS -+gcoSURF_BlitDraw( -+ IN gcsSURF_BLITDRAW_ARGS *args -+ ); -+#endif /* gcdENABLE_3D */ -+ -+ -+ -+#if gcdENABLE_3D -+/* Clear surface function. */ -+gceSTATUS -+gcoSURF_Clear( -+ IN gcoSURF Surface, -+ IN gcsSURF_CLEAR_ARGS_PTR clearArg -+ ); -+ -+/* Preserve pixels from source. */ -+gceSTATUS -+gcoSURF_Preserve( -+ IN gcoSURF Source, -+ IN gcoSURF Dest, -+ IN gcsRECT_PTR MaskRect -+ ); -+ -+ -+/* TO BE REMOVED */ -+ gceSTATUS -+ depr_gcoSURF_Resolve( -+ IN gcoSURF SrcSurface, -+ IN gcoSURF DestSurface, -+ IN gctUINT32 DestAddress, -+ IN gctPOINTER DestBits, -+ IN gctINT DestStride, -+ IN gceSURF_TYPE DestType, -+ IN gceSURF_FORMAT DestFormat, -+ IN gctUINT DestWidth, -+ IN gctUINT DestHeight -+ ); -+ -+ gceSTATUS -+ depr_gcoSURF_ResolveRect( -+ IN gcoSURF SrcSurface, -+ IN gcoSURF DestSurface, -+ IN gctUINT32 DestAddress, -+ IN gctPOINTER DestBits, -+ IN gctINT DestStride, -+ IN gceSURF_TYPE DestType, -+ IN gceSURF_FORMAT DestFormat, -+ IN gctUINT DestWidth, -+ IN gctUINT DestHeight, -+ IN gcsPOINT_PTR SrcOrigin, -+ IN gcsPOINT_PTR DestOrigin, -+ IN gcsPOINT_PTR RectSize -+ ); -+ -+/* Resample surface. */ -+gceSTATUS -+gcoSURF_Resample( -+ IN gcoSURF SrcSurface, -+ IN gcoSURF DestSurface -+ ); -+ -+/* Resolve surface. */ -+gceSTATUS -+gcoSURF_Resolve( -+ IN gcoSURF SrcSurface, -+ IN gcoSURF DestSurface -+ ); -+ -+gceSTATUS -+gcoSURF_ResolveEx( -+ IN gcoSURF SrcSurface, -+ IN gcoSURF DestSurface, -+ IN gcsSURF_RESOLVE_ARGS *args -+ ); -+ -+ -+/* Resolve rectangular area of a surface. */ -+gceSTATUS -+gcoSURF_ResolveRect( -+ IN gcoSURF SrcSurface, -+ IN gcoSURF DestSurface, -+ IN gcsPOINT_PTR SrcOrigin, -+ IN gcsPOINT_PTR DestOrigin, -+ IN gcsPOINT_PTR RectSize -+ ); -+ -+/* Resolve rectangular area of a surface. */ -+gceSTATUS -+gcoSURF_ResolveRectEx( -+ IN gcoSURF SrcSurface, -+ IN gcoSURF DestSurface, -+ IN gcsPOINT_PTR SrcOrigin, -+ IN gcsPOINT_PTR DestOrigin, -+ IN gcsPOINT_PTR RectSize, -+ IN gcsSURF_RESOLVE_ARGS *args -+ ); -+ -+ -+gceSTATUS -+gcoSURF_GetResolveAlignment( -+ IN gcoSURF Surface, -+ OUT gctUINT *originX, -+ OUT gctUINT *originY, -+ OUT gctUINT *sizeX, -+ OUT gctUINT *sizeY -+ ); -+ -+gceSTATUS -+gcoSURF_IsHWResolveable( -+ IN gcoSURF SrcSurface, -+ IN gcoSURF DestSurface, -+ IN gcsPOINT_PTR SrcOrigin, -+ IN gcsPOINT_PTR DestOrigin, -+ IN gcsPOINT_PTR RectSize -+ ); -+ -+/* Set surface resolvability. */ -+gceSTATUS -+gcoSURF_SetResolvability( -+ IN gcoSURF Surface, -+ IN gctBOOL Resolvable -+ ); -+ -+gceSTATUS -+gcoSURF_IsRenderable( -+ IN gcoSURF Surface -+ ); -+ -+gceSTATUS -+gcoSURF_IsFormatRenderableAsRT( -+ IN gcoSURF Surface -+ ); -+ -+gceSTATUS -+gcoSURF_GetFence( -+ IN gcoSURF Surface -+ ); -+ -+gceSTATUS -+gcoBUFOBJ_GetFence( -+ IN gcoBUFOBJ bufObj -+ ); -+ -+gceSTATUS -+gcoBUFOBJ_WaitFence( -+ IN gcoBUFOBJ bufObj -+ ); -+ -+gceSTATUS -+gcoBUFOBJ_IsFenceEnabled( -+ IN gcoBUFOBJ bufObj -+ ); -+ -+gceSTATUS -+gcoSURF_WaitFence( -+ IN gcoSURF Surface -+ ); -+ -+gceSTATUS -+gcoSTREAM_GetFence( -+ IN gcoSTREAM stream -+ ); -+ -+gceSTATUS -+gcoSTREAM_WaitFence( -+ IN gcoSTREAM stream -+ ); -+ -+gceSTATUS -+gcoINDEX_GetFence( -+ IN gcoINDEX index -+ ); -+ -+gceSTATUS -+gcoINDEX_WaitFence( -+ IN gcoINDEX index -+ ); -+ -+gceSTATUS -+gcoSURF_3DBlitClearRect( -+ IN gcoSURF Surface, -+ IN gcsSURF_CLEAR_ARGS_PTR ClearArgs -+ ); -+ -+ -+gceSTATUS -+gcoSURF_3DBlitBltRect( -+ IN gcoSURF SrcSurf, -+ IN gcoSURF DestSurf, -+ IN gcsPOINT_PTR SrcOrigin, -+ IN gcsPOINT_PTR DestOrigin, -+ IN gcsPOINT_PTR RectSize -+ ); -+ -+gceSTATUS -+gcoSURF_3DBlitCopy( -+ IN gctUINT32 SrcAddress, -+ IN gctUINT32 DestAddress, -+ IN gctUINT32 Bytes -+ ); -+ -+ -+/******************************************************************************\ -+******************************** gcoINDEX Object ******************************* -+\******************************************************************************/ -+ -+/* Construct a new gcoINDEX object. */ -+gceSTATUS -+gcoINDEX_Construct( -+ IN gcoHAL Hal, -+ OUT gcoINDEX * Index -+ ); -+ -+/* Destroy a gcoINDEX object. */ -+gceSTATUS -+gcoINDEX_Destroy( -+ IN gcoINDEX Index -+ ); -+ -+/* Lock index in memory. */ -+gceSTATUS -+gcoINDEX_Lock( -+ IN gcoINDEX Index, -+ OUT gctUINT32 * Address, -+ OUT gctPOINTER * Memory -+ ); -+ -+/* Unlock index that was previously locked with gcoINDEX_Lock. */ -+gceSTATUS -+gcoINDEX_Unlock( -+ IN gcoINDEX Index -+ ); -+ -+/* Upload index data into the memory. */ -+gceSTATUS -+gcoINDEX_Load( -+ IN gcoINDEX Index, -+ IN gceINDEX_TYPE IndexType, -+ IN gctUINT32 IndexCount, -+ IN gctPOINTER IndexBuffer -+ ); -+ -+/* Bind an index object to the hardware. */ -+gceSTATUS -+gcoINDEX_Bind( -+ IN gcoINDEX Index, -+ IN gceINDEX_TYPE Type -+ ); -+ -+/* Bind an index object to the hardware. */ -+gceSTATUS -+gcoINDEX_BindOffset( -+ IN gcoINDEX Index, -+ IN gceINDEX_TYPE Type, -+ IN gctUINT32 Offset -+ ); -+ -+/* Free existing index buffer. */ -+gceSTATUS -+gcoINDEX_Free( -+ IN gcoINDEX Index -+ ); -+ -+/* Upload data into an index buffer. */ -+gceSTATUS -+gcoINDEX_Upload( -+ IN gcoINDEX Index, -+ IN gctCONST_POINTER Buffer, -+ IN gctSIZE_T Bytes -+ ); -+ -+/* Upload data into an index buffer starting at an offset. */ -+gceSTATUS -+gcoINDEX_UploadOffset( -+ IN gcoINDEX Index, -+ IN gctSIZE_T Offset, -+ IN gctCONST_POINTER Buffer, -+ IN gctSIZE_T Bytes -+ ); -+ -+/*Merge index2 to index1 from 0, index2 must subset of inex1*/ -+gceSTATUS -+gcoINDEX_Merge( -+ IN gcoINDEX Index1, -+ IN gcoINDEX Index2 -+ ); -+ -+/*check if index buffer is enough for this draw*/ -+gctBOOL -+gcoINDEX_CheckRange( -+ IN gcoINDEX Index, -+ IN gceINDEX_TYPE Type, -+ IN gctINT Count, -+ IN gctUINT32 Indices -+ ); -+ -+/* Query the index capabilities. */ -+gceSTATUS -+gcoINDEX_QueryCaps( -+ OUT gctBOOL * Index8, -+ OUT gctBOOL * Index16, -+ OUT gctBOOL * Index32, -+ OUT gctUINT * MaxIndex -+ ); -+ -+/* Determine the index range in the current index buffer. */ -+gceSTATUS -+gcoINDEX_GetIndexRange( -+ IN gcoINDEX Index, -+ IN gceINDEX_TYPE Type, -+ IN gctUINT32 Offset, -+ IN gctUINT32 Count, -+ OUT gctUINT32 * MinimumIndex, -+ OUT gctUINT32 * MaximumIndex -+ ); -+ -+/* Dynamic buffer management. */ -+gceSTATUS -+gcoINDEX_SetDynamic( -+ IN gcoINDEX Index, -+ IN gctSIZE_T Bytes, -+ IN gctUINT Buffers -+ ); -+ -+/******************************************************************************\ -+********************************** gco3D Object ********************************* -+\******************************************************************************/ -+ -+/* Blending targets. */ -+typedef enum _gceBLEND_UNIT -+{ -+ gcvBLEND_SOURCE, -+ gcvBLEND_TARGET, -+} -+gceBLEND_UNIT; -+ -+/* Construct a new gco3D object. */ -+gceSTATUS -+gco3D_Construct( -+ IN gcoHAL Hal, -+ OUT gco3D * Engine -+ ); -+ -+/* Destroy an gco3D object. */ -+gceSTATUS -+gco3D_Destroy( -+ IN gco3D Engine -+ ); -+ -+/* Set 3D API type. */ -+gceSTATUS -+gco3D_SetAPI( -+ IN gco3D Engine, -+ IN gceAPI ApiType -+ ); -+ -+/* Get 3D API type. */ -+gceSTATUS -+gco3D_GetAPI( -+ IN gco3D Engine, -+ OUT gceAPI * ApiType -+ ); -+ -+/* Set render target. */ -+gceSTATUS -+gco3D_SetTarget( -+ IN gco3D Engine, -+ IN gcoSURF Surface -+ ); -+ -+/* Unset render target. */ -+gceSTATUS -+gco3D_UnsetTarget( -+ IN gco3D Engine, -+ IN gcoSURF Surface -+ ); -+ -+gceSTATUS -+gco3D_SetTargetEx( -+ IN gco3D Engine, -+ IN gctUINT32 TargetIndex, -+ IN gcoSURF Surface, -+ IN gctUINT32 LayerIndex -+ ); -+ -+gceSTATUS -+gco3D_UnsetTargetEx( -+ IN gco3D Engine, -+ IN gctUINT32 TargetIndex, -+ IN gcoSURF Surface -+ ); -+ -+gceSTATUS -+gco3D_SetTargetOffsetEx( -+ IN gco3D Engine, -+ IN gctUINT32 TargetIndex, -+ IN gctSIZE_T Offset -+ ); -+ -+ -+gceSTATUS -+gco3D_SetPSOutputMapping( -+ IN gco3D Engine, -+ IN gctINT32 * psOutputMapping -+ ); -+ -+ -+/* Set depth buffer. */ -+gceSTATUS -+gco3D_SetDepth( -+ IN gco3D Engine, -+ IN gcoSURF Surface -+ ); -+ -+gceSTATUS -+gco3D_SetDepthBufferOffset( -+ IN gco3D Engine, -+ IN gctSIZE_T Offset -+ ); -+ -+/* Unset depth buffer. */ -+gceSTATUS -+gco3D_UnsetDepth( -+ IN gco3D Engine, -+ IN gcoSURF Surface -+ ); -+ -+/* Set viewport. */ -+gceSTATUS -+gco3D_SetViewport( -+ IN gco3D Engine, -+ IN gctINT32 Left, -+ IN gctINT32 Top, -+ IN gctINT32 Right, -+ IN gctINT32 Bottom -+ ); -+ -+/* Set scissors. */ -+gceSTATUS -+gco3D_SetScissors( -+ IN gco3D Engine, -+ IN gctINT32 Left, -+ IN gctINT32 Top, -+ IN gctINT32 Right, -+ IN gctINT32 Bottom -+ ); -+ -+/* Set clear color. */ -+gceSTATUS -+gco3D_SetClearColor( -+ IN gco3D Engine, -+ IN gctUINT8 Red, -+ IN gctUINT8 Green, -+ IN gctUINT8 Blue, -+ IN gctUINT8 Alpha -+ ); -+ -+/* Set fixed point clear color. */ -+gceSTATUS -+gco3D_SetClearColorX( -+ IN gco3D Engine, -+ IN gctFIXED_POINT Red, -+ IN gctFIXED_POINT Green, -+ IN gctFIXED_POINT Blue, -+ IN gctFIXED_POINT Alpha -+ ); -+ -+/* Set floating point clear color. */ -+gceSTATUS -+gco3D_SetClearColorF( -+ IN gco3D Engine, -+ IN gctFLOAT Red, -+ IN gctFLOAT Green, -+ IN gctFLOAT Blue, -+ IN gctFLOAT Alpha -+ ); -+ -+/* Set fixed point clear depth. */ -+gceSTATUS -+gco3D_SetClearDepthX( -+ IN gco3D Engine, -+ IN gctFIXED_POINT Depth -+ ); -+ -+/* Set floating point clear depth. */ -+gceSTATUS -+gco3D_SetClearDepthF( -+ IN gco3D Engine, -+ IN gctFLOAT Depth -+ ); -+ -+/* Set clear stencil. */ -+gceSTATUS -+gco3D_SetClearStencil( -+ IN gco3D Engine, -+ IN gctUINT32 Stencil -+ ); -+ -+/* Set shading mode. */ -+gceSTATUS -+gco3D_SetShading( -+ IN gco3D Engine, -+ IN gceSHADING Shading -+ ); -+ -+/* Set blending mode. */ -+gceSTATUS -+gco3D_EnableBlending( -+ IN gco3D Engine, -+ IN gctBOOL Enable -+ ); -+ -+/* Set blending function. */ -+gceSTATUS -+gco3D_SetBlendFunction( -+ IN gco3D Engine, -+ IN gceBLEND_UNIT Unit, -+ IN gceBLEND_FUNCTION FunctionRGB, -+ IN gceBLEND_FUNCTION FunctionAlpha -+ ); -+ -+/* Set blending mode. */ -+gceSTATUS -+gco3D_SetBlendMode( -+ IN gco3D Engine, -+ IN gceBLEND_MODE ModeRGB, -+ IN gceBLEND_MODE ModeAlpha -+ ); -+ -+/* Set blending color. */ -+gceSTATUS -+gco3D_SetBlendColor( -+ IN gco3D Engine, -+ IN gctUINT Red, -+ IN gctUINT Green, -+ IN gctUINT Blue, -+ IN gctUINT Alpha -+ ); -+ -+/* Set fixed point blending color. */ -+gceSTATUS -+gco3D_SetBlendColorX( -+ IN gco3D Engine, -+ IN gctFIXED_POINT Red, -+ IN gctFIXED_POINT Green, -+ IN gctFIXED_POINT Blue, -+ IN gctFIXED_POINT Alpha -+ ); -+ -+/* Set floating point blending color. */ -+gceSTATUS -+gco3D_SetBlendColorF( -+ IN gco3D Engine, -+ IN gctFLOAT Red, -+ IN gctFLOAT Green, -+ IN gctFLOAT Blue, -+ IN gctFLOAT Alpha -+ ); -+ -+/* Set culling mode. */ -+gceSTATUS -+gco3D_SetCulling( -+ IN gco3D Engine, -+ IN gceCULL Mode -+ ); -+ -+/* Enable point size */ -+gceSTATUS -+gco3D_SetPointSizeEnable( -+ IN gco3D Engine, -+ IN gctBOOL Enable -+ ); -+ -+/* Set point sprite */ -+gceSTATUS -+gco3D_SetPointSprite( -+ IN gco3D Engine, -+ IN gctBOOL Enable -+ ); -+ -+/* Set fill mode. */ -+gceSTATUS -+gco3D_SetFill( -+ IN gco3D Engine, -+ IN gceFILL Mode -+ ); -+ -+/* Set depth compare mode. */ -+gceSTATUS -+gco3D_SetDepthCompare( -+ IN gco3D Engine, -+ IN gceCOMPARE Compare -+ ); -+ -+/* Enable depth writing. */ -+gceSTATUS -+gco3D_EnableDepthWrite( -+ IN gco3D Engine, -+ IN gctBOOL Enable -+ ); -+ -+/* Set depth mode. */ -+gceSTATUS -+gco3D_SetDepthMode( -+ IN gco3D Engine, -+ IN gceDEPTH_MODE Mode -+ ); -+ -+/* Set depth range. */ -+gceSTATUS -+gco3D_SetDepthRangeX( -+ IN gco3D Engine, -+ IN gceDEPTH_MODE Mode, -+ IN gctFIXED_POINT Near, -+ IN gctFIXED_POINT Far -+ ); -+ -+/* Set depth range. */ -+gceSTATUS -+gco3D_SetDepthRangeF( -+ IN gco3D Engine, -+ IN gceDEPTH_MODE Mode, -+ IN gctFLOAT Near, -+ IN gctFLOAT Far -+ ); -+ -+/* Set last pixel enable */ -+gceSTATUS -+gco3D_SetLastPixelEnable( -+ IN gco3D Engine, -+ IN gctBOOL Enable -+ ); -+ -+/* Set depth Bias and Scale */ -+gceSTATUS -+gco3D_SetDepthScaleBiasX( -+ IN gco3D Engine, -+ IN gctFIXED_POINT DepthScale, -+ IN gctFIXED_POINT DepthBias -+ ); -+ -+gceSTATUS -+gco3D_SetDepthScaleBiasF( -+ IN gco3D Engine, -+ IN gctFLOAT DepthScale, -+ IN gctFLOAT DepthBias -+ ); -+ -+/* Set depth near and far clipping plane. */ -+gceSTATUS -+gco3D_SetDepthPlaneF( -+ IN gco3D Engine, -+ IN gctFLOAT Near, -+ IN gctFLOAT Far -+ ); -+ -+/* Enable or disable dithering. */ -+gceSTATUS -+gco3D_EnableDither( -+ IN gco3D Engine, -+ IN gctBOOL Enable -+ ); -+ -+/* Set color write enable bits. */ -+gceSTATUS -+gco3D_SetColorWrite( -+ IN gco3D Engine, -+ IN gctUINT8 Enable -+ ); -+ -+/* Enable or disable early depth. */ -+gceSTATUS -+gco3D_SetEarlyDepth( -+ IN gco3D Engine, -+ IN gctBOOL Enable -+ ); -+ -+/* Deprecated: Enable or disable all early depth operations. */ -+gceSTATUS -+gco3D_SetAllEarlyDepthModes( -+ IN gco3D Engine, -+ IN gctBOOL Disable -+ ); -+ -+/* Enable or disable all early depth operations. */ -+gceSTATUS -+gco3D_SetAllEarlyDepthModesEx( -+ IN gco3D Engine, -+ IN gctBOOL Disable, -+ IN gctBOOL DisableModify, -+ IN gctBOOL DisablePassZ -+ ); -+ -+/* Switch dynamic early mode */ -+gceSTATUS -+gco3D_SwitchDynamicEarlyDepthMode( -+ IN gco3D Engine -+ ); -+ -+/* Set dynamic early mode */ -+gceSTATUS -+gco3D_DisableDynamicEarlyDepthMode( -+ IN gco3D Engine, -+ IN gctBOOL Disable -+ ); -+ -+/* Enable or disable depth-only mode. */ -+gceSTATUS -+gco3D_SetDepthOnly( -+ IN gco3D Engine, -+ IN gctBOOL Enable -+ ); -+ -+typedef struct _gcsSTENCIL_INFO * gcsSTENCIL_INFO_PTR; -+typedef struct _gcsSTENCIL_INFO -+{ -+ gceSTENCIL_MODE mode; -+ -+ gctUINT8 maskFront; -+ gctUINT8 maskBack; -+ gctUINT8 writeMaskFront; -+ gctUINT8 writeMaskBack; -+ -+ gctUINT8 referenceFront; -+ -+ gceCOMPARE compareFront; -+ gceSTENCIL_OPERATION passFront; -+ gceSTENCIL_OPERATION failFront; -+ gceSTENCIL_OPERATION depthFailFront; -+ -+ gctUINT8 referenceBack; -+ gceCOMPARE compareBack; -+ gceSTENCIL_OPERATION passBack; -+ gceSTENCIL_OPERATION failBack; -+ gceSTENCIL_OPERATION depthFailBack; -+} -+gcsSTENCIL_INFO; -+ -+/* Set stencil mode. */ -+gceSTATUS -+gco3D_SetStencilMode( -+ IN gco3D Engine, -+ IN gceSTENCIL_MODE Mode -+ ); -+ -+/* Set stencil mask. */ -+gceSTATUS -+gco3D_SetStencilMask( -+ IN gco3D Engine, -+ IN gctUINT8 Mask -+ ); -+ -+/* Set stencil back mask. */ -+gceSTATUS -+gco3D_SetStencilMaskBack( -+ IN gco3D Engine, -+ IN gctUINT8 Mask -+ ); -+ -+/* Set stencil write mask. */ -+gceSTATUS -+gco3D_SetStencilWriteMask( -+ IN gco3D Engine, -+ IN gctUINT8 Mask -+ ); -+ -+/* Set stencil back write mask. */ -+gceSTATUS -+gco3D_SetStencilWriteMaskBack( -+ IN gco3D Engine, -+ IN gctUINT8 Mask -+ ); -+ -+/* Set stencil reference. */ -+gceSTATUS -+gco3D_SetStencilReference( -+ IN gco3D Engine, -+ IN gctUINT8 Reference, -+ IN gctBOOL Front -+ ); -+ -+/* Set stencil compare. */ -+gceSTATUS -+gco3D_SetStencilCompare( -+ IN gco3D Engine, -+ IN gceSTENCIL_WHERE Where, -+ IN gceCOMPARE Compare -+ ); -+ -+/* Set stencil operation on pass. */ -+gceSTATUS -+gco3D_SetStencilPass( -+ IN gco3D Engine, -+ IN gceSTENCIL_WHERE Where, -+ IN gceSTENCIL_OPERATION Operation -+ ); -+ -+/* Set stencil operation on fail. */ -+gceSTATUS -+gco3D_SetStencilFail( -+ IN gco3D Engine, -+ IN gceSTENCIL_WHERE Where, -+ IN gceSTENCIL_OPERATION Operation -+ ); -+ -+/* Set stencil operation on depth fail. */ -+gceSTATUS -+gco3D_SetStencilDepthFail( -+ IN gco3D Engine, -+ IN gceSTENCIL_WHERE Where, -+ IN gceSTENCIL_OPERATION Operation -+ ); -+ -+/* Set all stencil states in one blow. */ -+gceSTATUS -+gco3D_SetStencilAll( -+ IN gco3D Engine, -+ IN gcsSTENCIL_INFO_PTR Info -+ ); -+ -+typedef struct _gcsALPHA_INFO * gcsALPHA_INFO_PTR; -+typedef struct _gcsALPHA_INFO -+{ -+ /* Alpha test states. */ -+ gctBOOL test; -+ gceCOMPARE compare; -+ gctUINT8 reference; -+ gctFLOAT floatReference; -+ -+ /* Alpha blending states. */ -+ gctBOOL blend; -+ -+ gceBLEND_FUNCTION srcFuncColor; -+ gceBLEND_FUNCTION srcFuncAlpha; -+ gceBLEND_FUNCTION trgFuncColor; -+ gceBLEND_FUNCTION trgFuncAlpha; -+ -+ gceBLEND_MODE modeColor; -+ gceBLEND_MODE modeAlpha; -+ -+ gctUINT32 color; -+} -+gcsALPHA_INFO; -+ -+/* Enable or disable alpha test. */ -+gceSTATUS -+gco3D_SetAlphaTest( -+ IN gco3D Engine, -+ IN gctBOOL Enable -+ ); -+ -+/* Set alpha test compare. */ -+gceSTATUS -+gco3D_SetAlphaCompare( -+ IN gco3D Engine, -+ IN gceCOMPARE Compare -+ ); -+ -+/* Set alpha test reference in unsigned integer. */ -+gceSTATUS -+gco3D_SetAlphaReference( -+ IN gco3D Engine, -+ IN gctUINT8 Reference, -+ IN gctFLOAT FloatReference -+ ); -+ -+/* Set alpha test reference in fixed point. */ -+gceSTATUS -+gco3D_SetAlphaReferenceX( -+ IN gco3D Engine, -+ IN gctFIXED_POINT Reference -+ ); -+ -+/* Set alpha test reference in floating point. */ -+gceSTATUS -+gco3D_SetAlphaReferenceF( -+ IN gco3D Engine, -+ IN gctFLOAT Reference -+ ); -+ -+/* Enable/Disable anti-alias line. */ -+gceSTATUS -+gco3D_SetAntiAliasLine( -+ IN gco3D Engine, -+ IN gctBOOL Enable -+ ); -+ -+/* Set texture slot for anti-alias line. */ -+gceSTATUS -+gco3D_SetAALineTexSlot( -+ IN gco3D Engine, -+ IN gctUINT TexSlot -+ ); -+ -+/* Set anti-alias line width scale. */ -+gceSTATUS -+gco3D_SetAALineWidth( -+ IN gco3D Engine, -+ IN gctFLOAT Width -+ ); -+ -+/* Draw a number of primitives. */ -+gceSTATUS -+gco3D_DrawPrimitives( -+ IN gco3D Engine, -+ IN gcePRIMITIVE Type, -+ IN gctSIZE_T StartVertex, -+ IN gctSIZE_T PrimitiveCount -+ ); -+ -+gceSTATUS -+gco3D_DrawInstancedPrimitives( -+ IN gco3D Engine, -+ IN gcePRIMITIVE Type, -+ IN gctBOOL DrawIndex, -+ IN gctSIZE_T StartVertex, -+ IN gctSIZE_T StartIndex, -+ IN gctSIZE_T PrimitiveCount, -+ IN gctSIZE_T VertexCount, -+ IN gctSIZE_T InstanceCount -+ ); -+ -+gceSTATUS -+gco3D_DrawPrimitivesCount( -+ IN gco3D Engine, -+ IN gcePRIMITIVE Type, -+ IN gctINT* StartVertex, -+ IN gctSIZE_T* VertexCount, -+ IN gctSIZE_T PrimitiveCount -+ ); -+ -+ -+/* Draw a number of primitives using offsets. */ -+gceSTATUS -+gco3D_DrawPrimitivesOffset( -+ IN gco3D Engine, -+ IN gcePRIMITIVE Type, -+ IN gctINT32 StartOffset, -+ IN gctSIZE_T PrimitiveCount -+ ); -+ -+/* Draw a number of indexed primitives. */ -+gceSTATUS -+gco3D_DrawIndexedPrimitives( -+ IN gco3D Engine, -+ IN gcePRIMITIVE Type, -+ IN gctSIZE_T BaseVertex, -+ IN gctSIZE_T StartIndex, -+ IN gctSIZE_T PrimitiveCount -+ ); -+ -+/* Draw a number of indexed primitives using offsets. */ -+gceSTATUS -+gco3D_DrawIndexedPrimitivesOffset( -+ IN gco3D Engine, -+ IN gcePRIMITIVE Type, -+ IN gctINT32 BaseOffset, -+ IN gctINT32 StartOffset, -+ IN gctSIZE_T PrimitiveCount -+ ); -+ -+/* Draw a element from pattern */ -+gceSTATUS -+gco3D_DrawPattern( -+ IN gco3D Engine, -+ IN gcsFAST_FLUSH_PTR FastFlushInfo -+ ); -+ -+/* Enable or disable anti-aliasing. */ -+gceSTATUS -+gco3D_SetAntiAlias( -+ IN gco3D Engine, -+ IN gctBOOL Enable -+ ); -+ -+/* Write data into the command buffer. */ -+gceSTATUS -+gco3D_WriteBuffer( -+ IN gco3D Engine, -+ IN gctCONST_POINTER Data, -+ IN gctSIZE_T Bytes, -+ IN gctBOOL Aligned -+ ); -+ -+/* Send sempahore and stall until sempahore is signalled. */ -+gceSTATUS -+gco3D_Semaphore( -+ IN gco3D Engine, -+ IN gceWHERE From, -+ IN gceWHERE To, -+ IN gceHOW How); -+ -+/* Explicitly flush shader L1 cache */ -+gceSTATUS -+gco3D_FlushSHL1Cache( -+ IN gco3D Engine -+ ); -+ -+/* Set the subpixels center. */ -+gceSTATUS -+gco3D_SetCentroids( -+ IN gco3D Engine, -+ IN gctUINT32 Index, -+ IN gctPOINTER Centroids -+ ); -+ -+gceSTATUS -+gco3D_SetLogicOp( -+ IN gco3D Engine, -+ IN gctUINT8 Rop -+ ); -+ -+gceSTATUS -+gco3D_SetOQ( -+ IN gco3D Engine, -+ INOUT gctPOINTER * Result, -+ IN gctBOOL Enable -+ ); -+ -+gceSTATUS -+gco3D_GetOQ( -+ IN gco3D Engine, -+ IN gctPOINTER Result, -+ OUT gctINT64 * Logical -+ ); -+ -+gceSTATUS -+gco3D_DeleteOQ( -+ IN gco3D Engine, -+ INOUT gctPOINTER Result -+ ); -+ -+gceSTATUS -+gco3D_SetColorOutCount( -+ IN gco3D Engine, -+ IN gctUINT32 ColorOutCount -+ ); -+ -+gceSTATUS -+gco3D_Set3DEngine( -+ IN gco3D Engine -+ ); -+ -+gceSTATUS -+gco3D_UnSet3DEngine( -+ IN gco3D Engine -+ ); -+ -+gceSTATUS -+gco3D_Get3DEngine( -+ OUT gco3D * Engine -+ ); -+ -+ -+/* OCL thread walker information. */ -+typedef struct _gcsTHREAD_WALKER_INFO * gcsTHREAD_WALKER_INFO_PTR; -+typedef struct _gcsTHREAD_WALKER_INFO -+{ -+ gctUINT32 dimensions; -+ gctUINT32 traverseOrder; -+ gctUINT32 enableSwathX; -+ gctUINT32 enableSwathY; -+ gctUINT32 enableSwathZ; -+ gctUINT32 swathSizeX; -+ gctUINT32 swathSizeY; -+ gctUINT32 swathSizeZ; -+ gctUINT32 valueOrder; -+ -+ gctUINT32 globalSizeX; -+ gctUINT32 globalOffsetX; -+ gctUINT32 globalSizeY; -+ gctUINT32 globalOffsetY; -+ gctUINT32 globalSizeZ; -+ gctUINT32 globalOffsetZ; -+ -+ gctUINT32 workGroupSizeX; -+ gctUINT32 workGroupCountX; -+ gctUINT32 workGroupSizeY; -+ gctUINT32 workGroupCountY; -+ gctUINT32 workGroupSizeZ; -+ gctUINT32 workGroupCountZ; -+ -+ gctUINT32 threadAllocation; -+} -+gcsTHREAD_WALKER_INFO; -+ -+/* Start OCL thread walker. */ -+gceSTATUS -+gco3D_InvokeThreadWalker( -+ IN gco3D Engine, -+ IN gcsTHREAD_WALKER_INFO_PTR Info -+ ); -+ -+gceSTATUS -+gco3D_GetClosestRenderFormat( -+ IN gco3D Engine, -+ IN gceSURF_FORMAT InFormat, -+ OUT gceSURF_FORMAT* OutFormat -+ ); -+ -+/* Set w clip and w plane limit value. */ -+gceSTATUS -+gco3D_SetWClipEnable( -+ IN gco3D Engine, -+ IN gctBOOL Enable -+ ); -+ -+gceSTATUS -+gco3D_GetWClipEnable( -+ IN gco3D Engine, -+ OUT gctBOOL * Enable -+ ); -+ -+gceSTATUS -+gco3D_SetWPlaneLimitF( -+ IN gco3D Engine, -+ IN gctFLOAT Value -+ ); -+ -+gceSTATUS -+gco3D_SetWPlaneLimitX( -+ IN gco3D Engine, -+ IN gctFIXED_POINT Value -+ ); -+ -+gceSTATUS -+gco3D_SetWPlaneLimit( -+ IN gco3D Engine, -+ IN gctFLOAT Value -+ ); -+ -+gceSTATUS -+gco3D_PrimitiveRestart( -+ IN gco3D Engine, -+ IN gctBOOL PrimitiveRestart); -+ -+#if gcdSTREAM_OUT_BUFFER -+ -+gceSTATUS -+gco3D_QueryStreamOut( -+ IN gco3D Engine, -+ IN gctUINT32 OriginalIndexAddress, -+ IN gctUINT32 OriginalIndexOffset, -+ IN gctUINT32 OriginalIndexCount, -+ OUT gctBOOL_PTR Found -+ ); -+ -+gceSTATUS -+gco3D_StartStreamOut( -+ IN gco3D Engine, -+ IN gctINT StreamOutStatus, -+ IN gctUINT32 IndexAddress, -+ IN gctUINT32 IndexOffset, -+ IN gctUINT32 IndexCount -+ ); -+ -+gceSTATUS -+gco3D_StopStreamOut( -+ IN gco3D Engine -+ ); -+ -+gceSTATUS -+gco3D_ReplayStreamOut( -+ IN gco3D Engine, -+ IN gctUINT32 IndexAddress, -+ IN gctUINT32 IndexOffset, -+ IN gctUINT32 IndexCount -+ ); -+ -+gceSTATUS -+gco3D_EndStreamOut( -+ IN gco3D Engine -+ ); -+ -+#endif -+ -+/*----------------------------------------------------------------------------*/ -+/*-------------------------- gco3D Fragment Processor ------------------------*/ -+ -+/* Set the fragment processor configuration. */ -+gceSTATUS -+gco3D_SetFragmentConfiguration( -+ IN gco3D Engine, -+ IN gctBOOL ColorFromStream, -+ IN gctBOOL EnableFog, -+ IN gctBOOL EnableSmoothPoint, -+ IN gctUINT32 ClipPlanes -+ ); -+ -+/* Enable/disable texture stage operation. */ -+gceSTATUS -+gco3D_EnableTextureStage( -+ IN gco3D Engine, -+ IN gctINT Stage, -+ IN gctBOOL Enable -+ ); -+ -+/* Program the channel enable masks for the color texture function. */ -+gceSTATUS -+gco3D_SetTextureColorMask( -+ IN gco3D Engine, -+ IN gctINT Stage, -+ IN gctBOOL ColorEnabled, -+ IN gctBOOL AlphaEnabled -+ ); -+ -+/* Program the channel enable masks for the alpha texture function. */ -+gceSTATUS -+gco3D_SetTextureAlphaMask( -+ IN gco3D Engine, -+ IN gctINT Stage, -+ IN gctBOOL ColorEnabled, -+ IN gctBOOL AlphaEnabled -+ ); -+ -+/* Program the constant fragment color. */ -+gceSTATUS -+gco3D_SetFragmentColorX( -+ IN gco3D Engine, -+ IN gctFIXED_POINT Red, -+ IN gctFIXED_POINT Green, -+ IN gctFIXED_POINT Blue, -+ IN gctFIXED_POINT Alpha -+ ); -+ -+gceSTATUS -+gco3D_SetFragmentColorF( -+ IN gco3D Engine, -+ IN gctFLOAT Red, -+ IN gctFLOAT Green, -+ IN gctFLOAT Blue, -+ IN gctFLOAT Alpha -+ ); -+ -+/* Program the constant fog color. */ -+gceSTATUS -+gco3D_SetFogColorX( -+ IN gco3D Engine, -+ IN gctFIXED_POINT Red, -+ IN gctFIXED_POINT Green, -+ IN gctFIXED_POINT Blue, -+ IN gctFIXED_POINT Alpha -+ ); -+ -+gceSTATUS -+gco3D_SetFogColorF( -+ IN gco3D Engine, -+ IN gctFLOAT Red, -+ IN gctFLOAT Green, -+ IN gctFLOAT Blue, -+ IN gctFLOAT Alpha -+ ); -+ -+/* Program the constant texture color. */ -+gceSTATUS -+gco3D_SetTetxureColorX( -+ IN gco3D Engine, -+ IN gctINT Stage, -+ IN gctFIXED_POINT Red, -+ IN gctFIXED_POINT Green, -+ IN gctFIXED_POINT Blue, -+ IN gctFIXED_POINT Alpha -+ ); -+ -+gceSTATUS -+gco3D_SetTetxureColorF( -+ IN gco3D Engine, -+ IN gctINT Stage, -+ IN gctFLOAT Red, -+ IN gctFLOAT Green, -+ IN gctFLOAT Blue, -+ IN gctFLOAT Alpha -+ ); -+ -+/* Configure color texture function. */ -+gceSTATUS -+gco3D_SetColorTextureFunction( -+ IN gco3D Engine, -+ IN gctINT Stage, -+ IN gceTEXTURE_FUNCTION Function, -+ IN gceTEXTURE_SOURCE Source0, -+ IN gceTEXTURE_CHANNEL Channel0, -+ IN gceTEXTURE_SOURCE Source1, -+ IN gceTEXTURE_CHANNEL Channel1, -+ IN gceTEXTURE_SOURCE Source2, -+ IN gceTEXTURE_CHANNEL Channel2, -+ IN gctINT Scale -+ ); -+ -+/* Configure alpha texture function. */ -+gceSTATUS -+gco3D_SetAlphaTextureFunction( -+ IN gco3D Engine, -+ IN gctINT Stage, -+ IN gceTEXTURE_FUNCTION Function, -+ IN gceTEXTURE_SOURCE Source0, -+ IN gceTEXTURE_CHANNEL Channel0, -+ IN gceTEXTURE_SOURCE Source1, -+ IN gceTEXTURE_CHANNEL Channel1, -+ IN gceTEXTURE_SOURCE Source2, -+ IN gceTEXTURE_CHANNEL Channel2, -+ IN gctINT Scale -+ ); -+ -+/******************************************************************************\ -+******************************* gcoTEXTURE Object ******************************* -+\******************************************************************************/ -+ -+/* Cube faces. */ -+typedef enum _gceTEXTURE_FACE -+{ -+ gcvFACE_NONE, -+ gcvFACE_POSITIVE_X, -+ gcvFACE_NEGATIVE_X, -+ gcvFACE_POSITIVE_Y, -+ gcvFACE_NEGATIVE_Y, -+ gcvFACE_POSITIVE_Z, -+ gcvFACE_NEGATIVE_Z, -+} -+gceTEXTURE_FACE; -+ -+typedef struct _gcsTEXTURE -+{ -+ /* Addressing modes. */ -+ gceTEXTURE_ADDRESSING s; -+ gceTEXTURE_ADDRESSING t; -+ gceTEXTURE_ADDRESSING r; -+ -+ gceTEXTURE_SWIZZLE swizzle[gcvTEXTURE_COMPONENT_NUM]; -+ -+ /* Border color. */ -+ gctUINT8 border[gcvTEXTURE_COMPONENT_NUM]; -+ -+ /* Filters. */ -+ gceTEXTURE_FILTER minFilter; -+ gceTEXTURE_FILTER magFilter; -+ gceTEXTURE_FILTER mipFilter; -+ gctUINT anisoFilter; -+ -+ /* Level of detail. */ -+ gctFLOAT lodBias; -+ gctFLOAT lodMin; -+ gctFLOAT lodMax; -+ -+ /* base/max level */ -+ gctINT32 baseLevel; -+ gctINT32 maxLevel; -+ -+ /* depth texture comparison */ -+ gceTEXTURE_COMPARE_MODE compareMode; -+ gceCOMPARE compareFunc; -+ -+} -+gcsTEXTURE, * gcsTEXTURE_PTR; -+ -+/* Construct a new gcoTEXTURE object. */ -+gceSTATUS -+gcoTEXTURE_Construct( -+ IN gcoHAL Hal, -+ OUT gcoTEXTURE * Texture -+ ); -+ -+/* Construct a new gcoTEXTURE object with type information. */ -+gceSTATUS -+gcoTEXTURE_ConstructEx( -+ IN gcoHAL Hal, -+ IN gceTEXTURE_TYPE Type, -+ OUT gcoTEXTURE * Texture -+ ); -+ -+ -+/* Construct a new sized gcoTEXTURE object. */ -+gceSTATUS -+gcoTEXTURE_ConstructSized( -+ IN gcoHAL Hal, -+ IN gceSURF_FORMAT Format, -+ IN gctUINT Width, -+ IN gctUINT Height, -+ IN gctUINT Depth, -+ IN gctUINT Faces, -+ IN gctUINT MipMapCount, -+ IN gcePOOL Pool, -+ OUT gcoTEXTURE * Texture -+ ); -+ -+/* Destroy an gcoTEXTURE object. */ -+gceSTATUS -+gcoTEXTURE_Destroy( -+ IN gcoTEXTURE Texture -+ ); -+ -+/* Upload data to an gcoTEXTURE object. */ -+gceSTATUS -+gcoTEXTURE_Upload( -+ IN gcoTEXTURE Texture, -+ IN gctINT MipMap, -+ IN gceTEXTURE_FACE Face, -+ IN gctSIZE_T Width, -+ IN gctSIZE_T Height, -+ IN gctUINT Slice, -+ IN gctCONST_POINTER Memory, -+ IN gctSIZE_T Stride, -+ IN gceSURF_FORMAT Format, -+ IN gceSURF_COLOR_SPACE SrcColorSpace -+ ); -+ -+/* Upload data to an gcoTEXTURE object. */ -+gceSTATUS -+gcoTEXTURE_UploadSub( -+ IN gcoTEXTURE Texture, -+ IN gctINT MipMap, -+ IN gceTEXTURE_FACE Face, -+ IN gctSIZE_T X, -+ IN gctSIZE_T Y, -+ IN gctSIZE_T Width, -+ IN gctSIZE_T Height, -+ IN gctUINT Slice, -+ IN gctCONST_POINTER Memory, -+ IN gctSIZE_T Stride, -+ IN gceSURF_FORMAT Format, -+ IN gceSURF_COLOR_SPACE SrcColorSpace, -+ IN gctUINT32 PhysicalAddress -+ ); -+ -+ -+/* Upload YUV data to an gcoTEXTURE object. */ -+gceSTATUS -+gcoTEXTURE_UploadYUV( -+ IN gcoTEXTURE Texture, -+ IN gceTEXTURE_FACE Face, -+ IN gctUINT Width, -+ IN gctUINT Height, -+ IN gctUINT Slice, -+ IN gctPOINTER Memory[3], -+ IN gctINT Stride[3], -+ IN gceSURF_FORMAT Format -+ ); -+ -+/* Upload compressed data to an gcoTEXTURE object. */ -+gceSTATUS -+gcoTEXTURE_UploadCompressed( -+ IN gcoTEXTURE Texture, -+ IN gctINT MipMap, -+ IN gceTEXTURE_FACE Face, -+ IN gctSIZE_T Width, -+ IN gctSIZE_T Height, -+ IN gctUINT Slice, -+ IN gctCONST_POINTER Memory, -+ IN gctSIZE_T Bytes -+ ); -+ -+/* Upload compressed sub data to an gcoTEXTURE object. */ -+gceSTATUS -+gcoTEXTURE_UploadCompressedSub( -+ IN gcoTEXTURE Texture, -+ IN gctINT MipMap, -+ IN gceTEXTURE_FACE Face, -+ IN gctSIZE_T XOffset, -+ IN gctSIZE_T YOffset, -+ IN gctSIZE_T Width, -+ IN gctSIZE_T Height, -+ IN gctUINT Slice, -+ IN gctCONST_POINTER Memory, -+ IN gctSIZE_T Size -+ ); -+ -+/* Get gcoSURF object for a mipmap level. */ -+gceSTATUS -+gcoTEXTURE_GetMipMap( -+ IN gcoTEXTURE Texture, -+ IN gctUINT MipMap, -+ OUT gcoSURF * Surface -+ ); -+ -+/* Get gcoSURF object for a mipmap level and face offset. */ -+gceSTATUS -+gcoTEXTURE_GetMipMapFace( -+ IN gcoTEXTURE Texture, -+ IN gctUINT MipMap, -+ IN gceTEXTURE_FACE Face, -+ OUT gcoSURF * Surface, -+ OUT gctSIZE_T_PTR Offset -+ ); -+ -+gceSTATUS -+gcoTEXTURE_GetMipMapSlice( -+ IN gcoTEXTURE Texture, -+ IN gctUINT MipMap, -+ IN gctUINT Slice, -+ OUT gcoSURF * Surface, -+ OUT gctSIZE_T_PTR Offset -+ ); -+ -+gceSTATUS -+gcoTEXTURE_AddMipMap( -+ IN gcoTEXTURE Texture, -+ IN gctINT Level, -+ IN gctINT InternalFormat, -+ IN gceSURF_FORMAT Format, -+ IN gctSIZE_T Width, -+ IN gctSIZE_T Height, -+ IN gctSIZE_T Depth, -+ IN gctUINT Faces, -+ IN gcePOOL Pool, -+ OUT gcoSURF * Surface -+ ); -+ -+gceSTATUS -+gcoTEXTURE_AddMipMapWithFlag( -+ IN gcoTEXTURE Texture, -+ IN gctINT Level, -+ IN gctINT InternalFormat, -+ IN gceSURF_FORMAT Format, -+ IN gctSIZE_T Width, -+ IN gctSIZE_T Height, -+ IN gctSIZE_T Depth, -+ IN gctUINT Faces, -+ IN gcePOOL Pool, -+ IN gctBOOL Protected, -+ OUT gcoSURF * Surface -+ ); -+ -+gceSTATUS -+gcoTEXTURE_AddMipMapFromClient( -+ IN gcoTEXTURE Texture, -+ IN gctINT Level, -+ IN gcoSURF Surface -+ ); -+ -+gceSTATUS -+gcoTEXTURE_AddMipMapFromSurface( -+ IN gcoTEXTURE Texture, -+ IN gctINT Level, -+ IN gcoSURF Surface -+ ); -+ -+gceSTATUS -+gcoTEXTURE_SetEndianHint( -+ IN gcoTEXTURE Texture, -+ IN gceENDIAN_HINT EndianHint -+ ); -+ -+gceSTATUS -+gcoTEXTURE_Disable( -+ IN gcoHAL Hal, -+ IN gctINT Sampler -+ ); -+ -+gceSTATUS -+gcoTEXTURE_Flush( -+ IN gcoTEXTURE Texture -+ ); -+ -+gceSTATUS -+gcoTEXTURE_FlushVS( -+ IN gcoTEXTURE Texture -+ ); -+ -+gceSTATUS -+gcoTEXTURE_QueryCaps( -+ IN gcoHAL Hal, -+ OUT gctUINT * MaxWidth, -+ OUT gctUINT * MaxHeight, -+ OUT gctUINT * MaxDepth, -+ OUT gctBOOL * Cubic, -+ OUT gctBOOL * NonPowerOfTwo, -+ OUT gctUINT * VertexSamplers, -+ OUT gctUINT * PixelSamplers -+ ); -+ -+gceSTATUS -+gcoTEXTURE_GetClosestFormat( -+ IN gcoHAL Hal, -+ IN gceSURF_FORMAT InFormat, -+ OUT gceSURF_FORMAT* OutFormat -+ ); -+ -+gceSTATUS -+gcoTEXTURE_GetClosestFormatEx( -+ IN gcoHAL Hal, -+ IN gceSURF_FORMAT InFormat, -+ IN gceTEXTURE_TYPE TextureType, -+ OUT gceSURF_FORMAT* OutFormat -+ ); -+ -+gceSTATUS -+gcoTEXTURE_GetFormatInfo( -+ IN gcoTEXTURE Texture, -+ IN gctINT preferLevel, -+ OUT gcsSURF_FORMAT_INFO_PTR * TxFormatInfo -+ ); -+ -+gceSTATUS -+gcoTEXTURE_GetTextureFormatName( -+ IN gcsSURF_FORMAT_INFO_PTR TxFormatInfo, -+ OUT gctCONST_STRING * TxName -+ ); -+ -+gceSTATUS -+gcoTEXTURE_RenderIntoMipMap( -+ IN gcoTEXTURE Texture, -+ IN gctINT Level -+ ); -+ -+gceSTATUS -+gcoTEXTURE_RenderIntoMipMap2( -+ IN gcoTEXTURE Texture, -+ IN gctINT Level, -+ IN gctBOOL Sync -+ ); -+ -+gceSTATUS -+gcoTEXTURE_IsRenderable( -+ IN gcoTEXTURE Texture, -+ IN gctUINT Level -+ ); -+ -+gceSTATUS -+gcoTEXTURE_IsComplete( -+ IN gcoTEXTURE Texture, -+ IN gcsTEXTURE_PTR Info, -+ IN gctINT BaseLevel, -+ IN gctINT MaxLevel -+ ); -+ -+gceSTATUS -+gcoTEXTURE_BindTexture( -+ IN gcoTEXTURE Texture, -+ IN gctINT Target, -+ IN gctINT Sampler, -+ IN gcsTEXTURE_PTR Info -+ ); -+ -+gceSTATUS -+gcoTEXTURE_BindTextureEx( -+ IN gcoTEXTURE Texture, -+ IN gctINT Target, -+ IN gctINT Sampler, -+ IN gcsTEXTURE_PTR Info, -+ IN gctINT textureLayer -+ ); -+ -+gceSTATUS -+gcoTEXTURE_InitParams( -+ IN gcoHAL Hal, -+ IN gcsTEXTURE_PTR TexParams -+ ); -+ -+gceSTATUS -+gcoTEXTURE_SetDepthTextureFlag( -+ IN gcoTEXTURE Texture, -+ IN gctBOOL unsized -+ ); -+ -+ -+/******************************************************************************\ -+******************************* gcoSTREAM Object ****************************** -+\******************************************************************************/ -+ -+typedef enum _gceVERTEX_FORMAT -+{ -+ gcvVERTEX_BYTE, -+ gcvVERTEX_UNSIGNED_BYTE, -+ gcvVERTEX_SHORT, -+ gcvVERTEX_UNSIGNED_SHORT, -+ gcvVERTEX_INT, -+ gcvVERTEX_UNSIGNED_INT, -+ gcvVERTEX_FIXED, -+ gcvVERTEX_HALF, -+ gcvVERTEX_FLOAT, -+ gcvVERTEX_UNSIGNED_INT_10_10_10_2, -+ gcvVERTEX_INT_10_10_10_2, -+ gcvVERTEX_UNSIGNED_INT_2_10_10_10_REV, -+ gcvVERTEX_INT_2_10_10_10_REV, -+ /* integer format */ -+ gcvVERTEX_INT8, -+ gcvVERTEX_INT16, -+ gcvVERTEX_INT32, -+} -+gceVERTEX_FORMAT; -+ -+/* What the SW converting scheme to create temp attrib */ -+typedef enum _gceATTRIB_SCHEME -+{ -+ gcvATTRIB_SCHEME_KEEP = 0, -+ gcvATTRIB_SCHEME_2_10_10_10_REV_TO_FLOAT, -+ gcvATTRIB_SCHEME_BYTE_TO_INT, -+ gcvATTRIB_SCHEME_SHORT_TO_INT, -+ gcvATTRIB_SCHEME_UBYTE_TO_UINT, -+ gcvATTRIB_SCHEME_USHORT_TO_UINT, -+} gceATTRIB_SCHEME; -+ -+gceSTATUS -+gcoSTREAM_Construct( -+ IN gcoHAL Hal, -+ OUT gcoSTREAM * Stream -+ ); -+ -+gceSTATUS -+gcoSTREAM_Destroy( -+ IN gcoSTREAM Stream -+ ); -+ -+gceSTATUS -+gcoSTREAM_Upload( -+ IN gcoSTREAM Stream, -+ IN gctCONST_POINTER Buffer, -+ IN gctSIZE_T Offset, -+ IN gctSIZE_T Bytes, -+ IN gctBOOL Dynamic -+ ); -+ -+gceSTATUS -+gcoSTREAM_SetStride( -+ IN gcoSTREAM Stream, -+ IN gctUINT32 Stride -+ ); -+ -+gceSTATUS -+gcoSTREAM_Size( -+ IN gcoSTREAM Stream, -+ OUT gctSIZE_T *Size -+ ); -+ -+gceSTATUS -+gcoSTREAM_Node( -+ IN gcoSTREAM Stream, -+ OUT gcsSURF_NODE_PTR * Node -+ ); -+ -+gceSTATUS -+gcoSTREAM_Lock( -+ IN gcoSTREAM Stream, -+ OUT gctPOINTER * Logical, -+ OUT gctUINT32 * Physical -+ ); -+ -+gceSTATUS -+gcoSTREAM_Unlock( -+ IN gcoSTREAM Stream -+ ); -+ -+gceSTATUS -+gcoSTREAM_Reserve( -+ IN gcoSTREAM Stream, -+ IN gctSIZE_T Bytes -+ ); -+ -+gceSTATUS -+gcoSTREAM_Flush( -+ IN gcoSTREAM Stream -+ ); -+ -+/* Dynamic buffer API. */ -+gceSTATUS -+gcoSTREAM_SetDynamic( -+ IN gcoSTREAM Stream, -+ IN gctSIZE_T Bytes, -+ IN gctUINT Buffers -+ ); -+ -+typedef struct _gcsSTREAM_INFO -+{ -+ gctUINT index; -+ gceVERTEX_FORMAT format; -+ gctBOOL normalized; -+ gctUINT components; -+ gctSIZE_T size; -+ gctCONST_POINTER data; -+ gctUINT stride; -+} -+gcsSTREAM_INFO, * gcsSTREAM_INFO_PTR; -+ -+gceSTATUS -+gcoSTREAM_UploadDynamic( -+ IN gcoSTREAM Stream, -+ IN gctUINT VertexCount, -+ IN gctUINT InfoCount, -+ IN gcsSTREAM_INFO_PTR Info, -+ IN gcoVERTEX Vertex -+ ); -+ -+gceSTATUS -+gcoSTREAM_CPUCacheOperation( -+ IN gcoSTREAM Stream, -+ IN gceCACHEOPERATION Operation -+ ); -+ -+gceSTATUS -+gcoSTREAM_CPUCacheOperation_Range( -+ IN gcoSTREAM Stream, -+ IN gctSIZE_T Offset, -+ IN gctSIZE_T Length, -+ IN gceCACHEOPERATION Operation -+ ); -+ -+/******************************************************************************\ -+******************************** gcoVERTEX Object ****************************** -+\******************************************************************************/ -+ -+typedef struct _gcsVERTEX_ATTRIBUTES -+{ -+ gceVERTEX_FORMAT format; -+ gctBOOL normalized; -+ gctUINT32 components; -+ gctSIZE_T size; -+ gctUINT32 stream; -+ gctUINT32 offset; -+ gctUINT32 stride; -+} -+gcsVERTEX_ATTRIBUTES; -+ -+gceSTATUS -+gcoVERTEX_Construct( -+ IN gcoHAL Hal, -+ OUT gcoVERTEX * Vertex -+ ); -+ -+gceSTATUS -+gcoVERTEX_Destroy( -+ IN gcoVERTEX Vertex -+ ); -+ -+gceSTATUS -+gcoVERTEX_Reset( -+ IN gcoVERTEX Vertex -+ ); -+ -+gceSTATUS -+gcoVERTEX_EnableAttribute( -+ IN gcoVERTEX Vertex, -+ IN gctUINT32 Index, -+ IN gceVERTEX_FORMAT Format, -+ IN gctBOOL Normalized, -+ IN gctUINT32 Components, -+ IN gcoSTREAM Stream, -+ IN gctUINT32 Offset, -+ IN gctUINT32 Stride -+ ); -+ -+gceSTATUS -+gcoVERTEX_DisableAttribute( -+ IN gcoVERTEX Vertex, -+ IN gctUINT32 Index -+ ); -+ -+gceSTATUS -+gcoVERTEX_Bind( -+ IN gcoVERTEX Vertex -+ ); -+ -+/******************************************************************************* -+***** gcoVERTEXARRAY Object ***************************************************/ -+ -+typedef struct _gcsATTRIBUTE -+{ -+ /* Enabled. */ -+ gctBOOL enable; -+ -+ /* Number of components. */ -+ gctINT size; -+ -+ /* Attribute format. */ -+ gceVERTEX_FORMAT format; -+ -+ /* Flag whether the attribute is normalized or not. */ -+ gctBOOL normalized; -+ -+ /* Stride of the component. */ -+ gctSIZE_T stride; -+ -+ /* Divisor of the attribute */ -+ gctUINT divisor; -+ -+ /* Pointer to the attribute data. */ -+ gctCONST_POINTER pointer; -+ -+ /* Stream object owning the attribute data. */ -+ gcoBUFOBJ stream; -+ -+ /* Generic values for attribute. */ -+ gctFLOAT genericValue[4]; -+ -+ /* Generic size for attribute. */ -+ gctINT genericSize; -+ -+ /* Vertex shader linkage. */ -+ gctUINT linkage; -+ -+#if gcdUSE_WCLIP_PATCH -+ /* Does it hold positions? */ -+ gctBOOL isPosition; -+#endif -+ -+ /* Index to vertex array */ -+ gctINT arrayIdx; -+ -+ gceATTRIB_SCHEME convertScheme; -+ -+ /* Pointer to the temporary buffer to be freed */ -+ gcoBUFOBJ tempStream; -+ -+ /* Pointer to the temporary memory to be freed */ -+ gctCONST_POINTER tempMemory; -+} -+gcsATTRIBUTE, -+* gcsATTRIBUTE_PTR; -+ -+ -+typedef struct _gcsVERTEXARRAY -+{ -+ /* Enabled. */ -+ gctBOOL enable; -+ -+ /* Number of components. */ -+ gctINT size; -+ -+ /* Attribute format. */ -+ gceVERTEX_FORMAT format; -+ -+ /* Flag whether the attribute is normalized or not. */ -+ gctBOOL normalized; -+ -+ /* Stride of the component. */ -+ gctUINT stride; -+ -+ /* Divisor of the attribute */ -+ gctUINT divisor; -+ -+ /* Pointer to the attribute data. */ -+ gctCONST_POINTER pointer; -+ -+ /* Stream object owning the attribute data. */ -+ gcoSTREAM stream; -+ -+ /* Generic values for attribute. */ -+ gctFLOAT genericValue[4]; -+ -+ /* Generic size for attribute. */ -+ gctINT genericSize; -+ -+ /* Vertex shader linkage. */ -+ gctUINT linkage; -+ -+ gctBOOL isPosition; -+} -+gcsVERTEXARRAY, -+* gcsVERTEXARRAY_PTR; -+ -+gceSTATUS -+gcoVERTEXARRAY_Construct( -+ IN gcoHAL Hal, -+ OUT gcoVERTEXARRAY * Vertex -+ ); -+ -+gceSTATUS -+gcoVERTEXARRAY_Destroy( -+ IN gcoVERTEXARRAY Vertex -+ ); -+ -+gceSTATUS -+gcoVERTEXARRAY_Bind_Ex( -+ IN gcoVERTEXARRAY Vertex, -+ IN gctUINT32 EnableBits, -+ IN gcsVERTEXARRAY_PTR VertexArray, -+ IN gctUINT First, -+ IN gctSIZE_T Count, -+ IN gctBOOL DrawArraysInstanced, -+ IN gctSIZE_T InstanceCount, -+ IN gceINDEX_TYPE IndexType, -+ IN gcoINDEX IndexObject, -+ IN gctPOINTER IndexMemory, -+ IN OUT gcePRIMITIVE * PrimitiveType, -+#if gcdUSE_WCLIP_PATCH -+ IN OUT gctUINT * PrimitiveCount, -+ IN OUT gctFLOAT * wLimitRms, -+ IN OUT gctBOOL * wLimitDirty -+#else -+ IN OUT gctUINT * PrimitiveCount -+#endif -+ ); -+ -+gceSTATUS -+gcoVERTEXARRAY_Bind_Ex2( -+ IN gcoVERTEXARRAY Vertex, -+ IN gctUINT32 EnableBits, -+ IN gcsATTRIBUTE_PTR VertexArray, -+ IN gctSIZE_T First, -+ IN gctSIZE_T Count, -+ IN gctBOOL DrawArraysInstanced, -+ IN gctSIZE_T InstanceCount, -+ IN gceINDEX_TYPE IndexType, -+ IN gcoBUFOBJ IndexObject, -+ IN gctPOINTER IndexMemory, -+ IN OUT gcePRIMITIVE * PrimitiveType, -+#if gcdUSE_WCLIP_PATCH -+ IN OUT gctSIZE_T * PrimitiveCount, -+ IN OUT gctFLOAT * wLimitRms, -+ IN OUT gctBOOL * wLimitDirty, -+#else -+ IN OUT gctUINT * PrimitiveCount, -+#endif -+ IN gctINT VertexInstanceIdLinkage -+ ); -+ -+gceSTATUS -+gcoVERTEXARRAY_Bind( -+ IN gcoVERTEXARRAY Vertex, -+ IN gctUINT32 EnableBits, -+ IN gcsVERTEXARRAY_PTR VertexArray, -+ IN gctUINT First, -+ IN gctSIZE_T Count, -+ IN gceINDEX_TYPE IndexType, -+ IN gcoINDEX IndexObject, -+ IN gctPOINTER IndexMemory, -+ IN OUT gcePRIMITIVE * PrimitiveType, -+#if gcdUSE_WCLIP_PATCH -+ IN OUT gctUINT * PrimitiveCount, -+ IN OUT gctFLOAT * wLimitRms, -+ IN OUT gctBOOL * wLimitDirty -+#else -+ IN OUT gctUINT * PrimitiveCount -+#endif -+ ); -+ -+/******************************************************************************* -+***** Composition *************************************************************/ -+ -+typedef enum _gceCOMPOSITION -+{ -+ gcvCOMPOSE_CLEAR = 1, -+ gcvCOMPOSE_BLUR, -+ gcvCOMPOSE_DIM, -+ gcvCOMPOSE_LAYER -+} -+gceCOMPOSITION; -+ -+typedef struct _gcsCOMPOSITION * gcsCOMPOSITION_PTR; -+typedef struct _gcsCOMPOSITION -+{ -+ /* Structure size. */ -+ gctUINT structSize; -+ -+ /* Composition operation. */ -+ gceCOMPOSITION operation; -+ -+ /* Layer to be composed. */ -+ gcoSURF layer; -+ -+ /* Source and target coordinates. */ -+ gcsRECT srcRect; -+ gcsRECT trgRect; -+ -+ /* Target rectangle */ -+ gcsPOINT v0; -+ gcsPOINT v1; -+ gcsPOINT v2; -+ -+ /* Blending parameters. */ -+ gctBOOL enableBlending; -+ gctBOOL premultiplied; -+ gctUINT8 alphaValue; -+ -+ /* Clear color. */ -+ gctFLOAT r; -+ gctFLOAT g; -+ gctFLOAT b; -+ gctFLOAT a; -+} -+gcsCOMPOSITION; -+ -+gceSTATUS -+gco3D_ProbeComposition( -+ IN gcoHARDWARE Hardware, -+ IN gctBOOL ResetIfEmpty -+ ); -+ -+gceSTATUS -+gco3D_CompositionBegin( -+ IN gcoHARDWARE Hardware -+ ); -+ -+gceSTATUS -+gco3D_ComposeLayer( -+ IN gcoHARDWARE Hardware, -+ IN gcsCOMPOSITION_PTR Layer -+ ); -+ -+gceSTATUS -+gco3D_CompositionSignals( -+ IN gcoHARDWARE Hardware, -+ IN gctHANDLE Process, -+ IN gctSIGNAL Signal1, -+ IN gctSIGNAL Signal2 -+ ); -+ -+gceSTATUS -+gco3D_CompositionEnd( -+ IN gcoHARDWARE Hardware, -+ IN gcoSURF Target, -+ IN gctBOOL Synchronous -+ ); -+ -+/* Frame Database */ -+gceSTATUS -+gcoHAL_AddFrameDB( -+ void -+ ); -+ -+gceSTATUS -+gcoHAL_DumpFrameDB( -+ gctCONST_STRING Filename OPTIONAL -+ ); -+ -+/****************************************************************************** -+**********************gcoBUFOBJ object***************************************** -+*******************************************************************************/ -+typedef enum _gceBUFOBJ_TYPE -+{ -+ gcvBUFOBJ_TYPE_ARRAY_BUFFER = 1, -+ gcvBUFOBJ_TYPE_ELEMENT_ARRAY_BUFFER = 2, -+ gcvBUFOBJ_TYPE_GENERIC_BUFFER = 100 -+ -+} gceBUFOBJ_TYPE; -+ -+typedef enum _gceBUFOBJ_USAGE -+{ -+ gcvBUFOBJ_USAGE_STREAM_DRAW = 1, -+ gcvBUFOBJ_USAGE_STREAM_READ, -+ gcvBUFOBJ_USAGE_STREAM_COPY, -+ gcvBUFOBJ_USAGE_STATIC_DRAW, -+ gcvBUFOBJ_USAGE_STATIC_READ, -+ gcvBUFOBJ_USAGE_STATIC_COPY, -+ gcvBUFOBJ_USAGE_DYNAMIC_DRAW, -+ gcvBUFOBJ_USAGE_DYNAMIC_READ, -+ gcvBUFOBJ_USAGE_DYNAMIC_COPY, -+ -+} gceBUFOBJ_USAGE; -+ -+/* Construct a new gcoBUFOBJ object. */ -+gceSTATUS -+gcoBUFOBJ_Construct( -+ IN gcoHAL Hal, -+ IN gceBUFOBJ_TYPE Type, -+ OUT gcoBUFOBJ * BufObj -+ ); -+ -+/* Destroy a gcoBUFOBJ object. */ -+gceSTATUS -+gcoBUFOBJ_Destroy( -+ IN gcoBUFOBJ BufObj -+ ); -+ -+/* Lock pbo in memory. */ -+gceSTATUS -+gcoBUFOBJ_Lock( -+ IN gcoBUFOBJ BufObj, -+ OUT gctUINT32 * Address, -+ OUT gctPOINTER * Memory -+ ); -+ -+/* Lock pbo in memory. */ -+gceSTATUS -+gcoBUFOBJ_FastLock( -+ IN gcoBUFOBJ BufObj, -+ OUT gctUINT32 * Address, -+ OUT gctPOINTER * Memory -+ ); -+ -+/* Unlock pbo that was previously locked with gcoBUFOBJ_Lock. */ -+gceSTATUS -+gcoBUFOBJ_Unlock( -+ IN gcoBUFOBJ BufObj -+ ); -+ -+/* Free existing pbo buffer. */ -+gceSTATUS -+gcoBUFOBJ_Free( -+ IN gcoBUFOBJ BufObj -+ ); -+ -+/* Upload data into an pbo buffer. */ -+gceSTATUS -+gcoBUFOBJ_Upload( -+ IN gcoBUFOBJ BufObj, -+ IN gctCONST_POINTER Buffer, -+ IN gctSIZE_T Offset, -+ IN gctSIZE_T Bytes, -+ IN gceBUFOBJ_USAGE Usage -+ ); -+ -+/* Bind an index object to the hardware. */ -+gceSTATUS -+gcoBUFOBJ_IndexBind ( -+ IN gcoBUFOBJ Index, -+ IN gceINDEX_TYPE Type, -+ IN gctUINT32 Offset, -+ IN gctSIZE_T Count -+ ); -+ -+/* Find min and max index for the index buffer */ -+gceSTATUS -+gcoBUFOBJ_IndexGetRange( -+ IN gcoBUFOBJ Index, -+ IN gceINDEX_TYPE Type, -+ IN gctUINT32 Offset, -+ IN gctUINT32 Count, -+ OUT gctUINT32 * MinimumIndex, -+ OUT gctUINT32 * MaximumIndex -+ ); -+ -+/* Sets a buffer object as dirty */ -+gceSTATUS -+gcoBUFOBJ_SetDirty( -+ IN gcoBUFOBJ BufObj -+ ); -+ -+/* Creates a new buffer if needed */ -+gceSTATUS -+gcoBUFOBJ_AlignIndexBufferWhenNeeded( -+ IN gcoBUFOBJ BufObj, -+ IN gctSIZE_T Offset, -+ OUT gcoBUFOBJ * AlignedBufObj -+ ); -+ -+/* Cache operations on whole range */ -+gceSTATUS -+gcoBUFOBJ_CPUCacheOperation( -+ IN gcoBUFOBJ BufObj, -+ IN gceCACHEOPERATION Operation -+ ); -+ -+/* Cache operations on a specified range */ -+gceSTATUS -+gcoBUFOBJ_CPUCacheOperation_Range( -+ IN gcoBUFOBJ BufObj, -+ IN gctSIZE_T Offset, -+ IN gctSIZE_T Length, -+ IN gceCACHEOPERATION Operation -+ ); -+ -+/* Return size of the bufobj */ -+gceSTATUS -+gcoBUFOBJ_GetSize( -+ IN gcoBUFOBJ BufObj, -+ OUT gctSIZE_T_PTR Size -+ ); -+ -+/* Return memory node of the bufobj */ -+gceSTATUS -+gcoBUFOBJ_GetNode( -+ IN gcoBUFOBJ BufObj, -+ OUT gcsSURF_NODE_PTR * Node -+ ); -+ -+/* Handle GPU cache operations */ -+gceSTATUS -+gcoBUFOBJ_GPUCacheOperation( -+ gcoBUFOBJ BufObj -+ ); -+ -+/* Dump buffer. */ -+void -+gcoBUFOBJ_Dump( -+ IN gcoBUFOBJ BufObj -+ ); -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* gcdENABLE_3D */ -+#endif /* __gc_hal_engine_h_ */ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_engine_vg.h linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_engine_vg.h ---- linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_engine_vg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_engine_vg.h 2015-11-30 17:56:13.592136927 +0100 -@@ -0,0 +1,1215 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#ifndef __gc_hal_engine_vg_h_ -+#define __gc_hal_engine_vg_h_ -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+#include "gc_hal_types.h" -+ -+/******************************************************************************\ -+******************************** VG Enumerations ******************************* -+\******************************************************************************/ -+ -+/** -+** @ingroup gcoVG -+** -+** @brief Tiling mode for painting and imagig. -+** -+** This enumeration defines the tiling modes supported by the HAL. This is -+** in fact a one-to-one mapping of the OpenVG 1.1 tile modes. -+*/ -+typedef enum _gceTILE_MODE -+{ -+ gcvTILE_FILL, -+ gcvTILE_PAD, -+ gcvTILE_REPEAT, -+ gcvTILE_REFLECT -+} -+gceTILE_MODE; -+ -+/******************************************************************************/ -+/** @ingroup gcoVG -+** -+** @brief The different paint modes. -+** -+** This enumeration lists the available paint modes. -+*/ -+typedef enum _gcePAINT_TYPE -+{ -+ /** Solid color. */ -+ gcvPAINT_MODE_SOLID, -+ -+ /** Linear gradient. */ -+ gcvPAINT_MODE_LINEAR, -+ -+ /** Radial gradient. */ -+ gcvPAINT_MODE_RADIAL, -+ -+ /** Pattern. */ -+ gcvPAINT_MODE_PATTERN, -+ -+ /** Mode count. */ -+ gcvPAINT_MODE_COUNT -+} -+gcePAINT_TYPE; -+ -+/** -+** @ingroup gcoVG -+** -+** @brief Types of path data supported by HAL. -+** -+** This enumeration defines the types of path data supported by the HAL. -+** This is in fact a one-to-one mapping of the OpenVG 1.1 path types. -+*/ -+typedef enum _gcePATHTYPE -+{ -+ gcePATHTYPE_UNKNOWN = -1, -+ gcePATHTYPE_INT8, -+ gcePATHTYPE_INT16, -+ gcePATHTYPE_INT32, -+ gcePATHTYPE_FLOAT -+} -+gcePATHTYPE; -+ -+/** -+** @ingroup gcoVG -+** -+** @brief Supported path segment commands. -+** -+** This enumeration defines the path segment commands supported by the HAL. -+*/ -+typedef enum _gceVGCMD -+{ -+ gcvVGCMD_END, /* 0: GCCMD_TS_OPCODE_END */ -+ gcvVGCMD_CLOSE, /* 1: GCCMD_TS_OPCODE_CLOSE */ -+ gcvVGCMD_MOVE, /* 2: GCCMD_TS_OPCODE_MOVE */ -+ gcvVGCMD_MOVE_REL, /* 3: GCCMD_TS_OPCODE_MOVE_REL */ -+ gcvVGCMD_LINE, /* 4: GCCMD_TS_OPCODE_LINE */ -+ gcvVGCMD_LINE_REL, /* 5: GCCMD_TS_OPCODE_LINE_REL */ -+ gcvVGCMD_QUAD, /* 6: GCCMD_TS_OPCODE_QUADRATIC */ -+ gcvVGCMD_QUAD_REL, /* 7: GCCMD_TS_OPCODE_QUADRATIC_REL */ -+ gcvVGCMD_CUBIC, /* 8: GCCMD_TS_OPCODE_CUBIC */ -+ gcvVGCMD_CUBIC_REL, /* 9: GCCMD_TS_OPCODE_CUBIC_REL */ -+ gcvVGCMD_BREAK, /* 10: GCCMD_TS_OPCODE_BREAK */ -+ gcvVGCMD_HLINE, /* 11: ******* R E S E R V E D *******/ -+ gcvVGCMD_HLINE_REL, /* 12: ******* R E S E R V E D *******/ -+ gcvVGCMD_VLINE, /* 13: ******* R E S E R V E D *******/ -+ gcvVGCMD_VLINE_REL, /* 14: ******* R E S E R V E D *******/ -+ gcvVGCMD_SQUAD, /* 15: ******* R E S E R V E D *******/ -+ gcvVGCMD_SQUAD_REL, /* 16: ******* R E S E R V E D *******/ -+ gcvVGCMD_SCUBIC, /* 17: ******* R E S E R V E D *******/ -+ gcvVGCMD_SCUBIC_REL, /* 18: ******* R E S E R V E D *******/ -+ gcvVGCMD_SCCWARC, /* 19: ******* R E S E R V E D *******/ -+ gcvVGCMD_SCCWARC_REL, /* 20: ******* R E S E R V E D *******/ -+ gcvVGCMD_SCWARC, /* 21: ******* R E S E R V E D *******/ -+ gcvVGCMD_SCWARC_REL, /* 22: ******* R E S E R V E D *******/ -+ gcvVGCMD_LCCWARC, /* 23: ******* R E S E R V E D *******/ -+ gcvVGCMD_LCCWARC_REL, /* 24: ******* R E S E R V E D *******/ -+ gcvVGCMD_LCWARC, /* 25: ******* R E S E R V E D *******/ -+ gcvVGCMD_LCWARC_REL, /* 26: ******* R E S E R V E D *******/ -+ -+ /* The width of the command recognized by the hardware on bits. */ -+ gcvVGCMD_WIDTH = 5, -+ -+ /* Hardware command mask. */ -+ gcvVGCMD_MASK = (1 << gcvVGCMD_WIDTH) - 1, -+ -+ /* Command modifiers. */ -+ gcvVGCMD_H_MOD = 1 << gcvVGCMD_WIDTH, /* = 32 */ -+ gcvVGCMD_V_MOD = 2 << gcvVGCMD_WIDTH, /* = 64 */ -+ gcvVGCMD_S_MOD = 3 << gcvVGCMD_WIDTH, /* = 96 */ -+ gcvVGCMD_ARC_MOD = 4 << gcvVGCMD_WIDTH, /* = 128 */ -+ -+ /* Emulated LINE commands. */ -+ gcvVGCMD_HLINE_EMUL = gcvVGCMD_H_MOD | gcvVGCMD_LINE, /* = 36 */ -+ gcvVGCMD_HLINE_EMUL_REL = gcvVGCMD_H_MOD | gcvVGCMD_LINE_REL, /* = 37 */ -+ gcvVGCMD_VLINE_EMUL = gcvVGCMD_V_MOD | gcvVGCMD_LINE, /* = 68 */ -+ gcvVGCMD_VLINE_EMUL_REL = gcvVGCMD_V_MOD | gcvVGCMD_LINE_REL, /* = 69 */ -+ -+ /* Emulated SMOOTH commands. */ -+ gcvVGCMD_SQUAD_EMUL = gcvVGCMD_S_MOD | gcvVGCMD_QUAD, /* = 102 */ -+ gcvVGCMD_SQUAD_EMUL_REL = gcvVGCMD_S_MOD | gcvVGCMD_QUAD_REL, /* = 103 */ -+ gcvVGCMD_SCUBIC_EMUL = gcvVGCMD_S_MOD | gcvVGCMD_CUBIC, /* = 104 */ -+ gcvVGCMD_SCUBIC_EMUL_REL = gcvVGCMD_S_MOD | gcvVGCMD_CUBIC_REL, /* = 105 */ -+ -+ /* Emulation ARC commands. */ -+ gcvVGCMD_ARC_LINE = gcvVGCMD_ARC_MOD | gcvVGCMD_LINE, /* = 132 */ -+ gcvVGCMD_ARC_LINE_REL = gcvVGCMD_ARC_MOD | gcvVGCMD_LINE_REL, /* = 133 */ -+ gcvVGCMD_ARC_QUAD = gcvVGCMD_ARC_MOD | gcvVGCMD_QUAD, /* = 134 */ -+ gcvVGCMD_ARC_QUAD_REL = gcvVGCMD_ARC_MOD | gcvVGCMD_QUAD_REL /* = 135 */ -+} -+gceVGCMD; -+typedef enum _gceVGCMD * gceVGCMD_PTR; -+ -+/** -+** @ingroup gcoVG -+** -+** @brief Blending modes supported by the HAL. -+** -+** This enumeration defines the blending modes supported by the HAL. This is -+** in fact a one-to-one mapping of the OpenVG 1.1 blending modes. -+*/ -+typedef enum _gceVG_BLEND -+{ -+ gcvVG_BLEND_SRC, -+ gcvVG_BLEND_SRC_OVER, -+ gcvVG_BLEND_DST_OVER, -+ gcvVG_BLEND_SRC_IN, -+ gcvVG_BLEND_DST_IN, -+ gcvVG_BLEND_MULTIPLY, -+ gcvVG_BLEND_SCREEN, -+ gcvVG_BLEND_DARKEN, -+ gcvVG_BLEND_LIGHTEN, -+ gcvVG_BLEND_ADDITIVE, -+ gcvVG_BLEND_SUBTRACT, -+ gcvVG_BLEND_FILTER -+} -+gceVG_BLEND; -+ -+/** -+** @ingroup gcoVG -+** -+** @brief Image modes supported by the HAL. -+** -+** This enumeration defines the image modes supported by the HAL. This is -+** in fact a one-to-one mapping of the OpenVG 1.1 image modes with the addition -+** of NO IMAGE. -+*/ -+typedef enum _gceVG_IMAGE -+{ -+ gcvVG_IMAGE_NONE, -+ gcvVG_IMAGE_NORMAL, -+ gcvVG_IMAGE_MULTIPLY, -+ gcvVG_IMAGE_STENCIL, -+ gcvVG_IMAGE_FILTER -+} -+gceVG_IMAGE; -+ -+/** -+** @ingroup gcoVG -+** -+** @brief Filter mode patterns and imaging. -+** -+** This enumeration defines the filter modes supported by the HAL. -+*/ -+typedef enum _gceIMAGE_FILTER -+{ -+ gcvFILTER_POINT, -+ gcvFILTER_LINEAR, -+ gcvFILTER_BI_LINEAR -+} -+gceIMAGE_FILTER; -+ -+/** -+** @ingroup gcoVG -+** -+** @brief Primitive modes supported by the HAL. -+** -+** This enumeration defines the primitive modes supported by the HAL. -+*/ -+typedef enum _gceVG_PRIMITIVE -+{ -+ gcvVG_SCANLINE, -+ gcvVG_RECTANGLE, -+ gcvVG_TESSELLATED, -+ gcvVG_TESSELLATED_TILED -+} -+gceVG_PRIMITIVE; -+ -+/** -+** @ingroup gcoVG -+** -+** @brief Rendering quality modes supported by the HAL. -+** -+** This enumeration defines the rendering quality modes supported by the HAL. -+*/ -+typedef enum _gceRENDER_QUALITY -+{ -+ gcvVG_NONANTIALIASED, -+ gcvVG_2X2_MSAA, -+ gcvVG_2X4_MSAA, -+ gcvVG_4X4_MSAA -+} -+gceRENDER_QUALITY; -+ -+/** -+** @ingroup gcoVG -+** -+** @brief Fill rules supported by the HAL. -+** -+** This enumeration defines the fill rules supported by the HAL. -+*/ -+typedef enum _gceFILL_RULE -+{ -+ gcvVG_EVEN_ODD, -+ gcvVG_NON_ZERO -+} -+gceFILL_RULE; -+ -+/** -+** @ingroup gcoVG -+** -+** @brief Cap styles supported by the HAL. -+** -+** This enumeration defines the cap styles supported by the HAL. -+*/ -+typedef enum _gceCAP_STYLE -+{ -+ gcvCAP_BUTT, -+ gcvCAP_ROUND, -+ gcvCAP_SQUARE -+} -+gceCAP_STYLE; -+ -+/** -+** @ingroup gcoVG -+** -+** @brief Join styles supported by the HAL. -+** -+** This enumeration defines the join styles supported by the HAL. -+*/ -+typedef enum _gceJOIN_STYLE -+{ -+ gcvJOIN_MITER, -+ gcvJOIN_ROUND, -+ gcvJOIN_BEVEL -+} -+gceJOIN_STYLE; -+ -+/** -+** @ingroup gcoVG -+** -+** @brief Channel mask values. -+** -+** This enumeration defines the values for channel mask used in image -+** filtering. -+*/ -+ -+/* Base values for channel mask definitions. */ -+#define gcvCHANNEL_X (0) -+#define gcvCHANNEL_R (1 << 0) -+#define gcvCHANNEL_G (1 << 1) -+#define gcvCHANNEL_B (1 << 2) -+#define gcvCHANNEL_A (1 << 3) -+ -+typedef enum _gceCHANNEL -+{ -+ gcvCHANNEL_XXXX = (gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_X), -+ gcvCHANNEL_XXXA = (gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_A), -+ gcvCHANNEL_XXBX = (gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_B | gcvCHANNEL_X), -+ gcvCHANNEL_XXBA = (gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_B | gcvCHANNEL_A), -+ -+ gcvCHANNEL_XGXX = (gcvCHANNEL_X | gcvCHANNEL_G | gcvCHANNEL_X | gcvCHANNEL_X), -+ gcvCHANNEL_XGXA = (gcvCHANNEL_X | gcvCHANNEL_G | gcvCHANNEL_X | gcvCHANNEL_A), -+ gcvCHANNEL_XGBX = (gcvCHANNEL_X | gcvCHANNEL_G | gcvCHANNEL_B | gcvCHANNEL_X), -+ gcvCHANNEL_XGBA = (gcvCHANNEL_X | gcvCHANNEL_G | gcvCHANNEL_B | gcvCHANNEL_A), -+ -+ gcvCHANNEL_RXXX = (gcvCHANNEL_R | gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_X), -+ gcvCHANNEL_RXXA = (gcvCHANNEL_R | gcvCHANNEL_X | gcvCHANNEL_X | gcvCHANNEL_A), -+ gcvCHANNEL_RXBX = (gcvCHANNEL_R | gcvCHANNEL_X | gcvCHANNEL_B | gcvCHANNEL_X), -+ gcvCHANNEL_RXBA = (gcvCHANNEL_R | gcvCHANNEL_X | gcvCHANNEL_B | gcvCHANNEL_A), -+ -+ gcvCHANNEL_RGXX = (gcvCHANNEL_R | gcvCHANNEL_G | gcvCHANNEL_X | gcvCHANNEL_X), -+ gcvCHANNEL_RGXA = (gcvCHANNEL_R | gcvCHANNEL_G | gcvCHANNEL_X | gcvCHANNEL_A), -+ gcvCHANNEL_RGBX = (gcvCHANNEL_R | gcvCHANNEL_G | gcvCHANNEL_B | gcvCHANNEL_X), -+ gcvCHANNEL_RGBA = (gcvCHANNEL_R | gcvCHANNEL_G | gcvCHANNEL_B | gcvCHANNEL_A), -+} -+gceCHANNEL; -+ -+/******************************************************************************\ -+******************************** VG Structures ******************************* -+\******************************************************************************/ -+ -+/** -+** @ingroup gcoVG -+** -+** @brief Definition of the color ramp used by the gradient paints. -+** -+** The gcsCOLOR_RAMP structure defines the layout of one single color inside -+** a color ramp which is used by gradient paints. -+*/ -+typedef struct _gcsCOLOR_RAMP -+{ -+ /** Value for the color stop. */ -+ gctFLOAT stop; -+ -+ /** Red color channel value for the color stop. */ -+ gctFLOAT red; -+ -+ /** Green color channel value for the color stop. */ -+ gctFLOAT green; -+ -+ /** Blue color channel value for the color stop. */ -+ gctFLOAT blue; -+ -+ /** Alpha color channel value for the color stop. */ -+ gctFLOAT alpha; -+} -+gcsCOLOR_RAMP, * gcsCOLOR_RAMP_PTR; -+ -+/** -+** @ingroup gcoVG -+** -+** @brief Definition of the color ramp used by the gradient paints in fixed form. -+** -+** The gcsCOLOR_RAMP structure defines the layout of one single color inside -+** a color ramp which is used by gradient paints. -+*/ -+typedef struct _gcsFIXED_COLOR_RAMP -+{ -+ /** Value for the color stop. */ -+ gctFIXED_POINT stop; -+ -+ /** Red color channel value for the color stop. */ -+ gctFIXED_POINT red; -+ -+ /** Green color channel value for the color stop. */ -+ gctFIXED_POINT green; -+ -+ /** Blue color channel value for the color stop. */ -+ gctFIXED_POINT blue; -+ -+ /** Alpha color channel value for the color stop. */ -+ gctFIXED_POINT alpha; -+} -+gcsFIXED_COLOR_RAMP, * gcsFIXED_COLOR_RAMP_PTR; -+ -+ -+/** -+** @ingroup gcoVG -+** -+** @brief Rectangle structure used by the gcoVG object. -+** -+** This structure defines the layout of a rectangle. Make sure width and -+** height are larger than 0. -+*/ -+typedef struct _gcsVG_RECT * gcsVG_RECT_PTR; -+typedef struct _gcsVG_RECT -+{ -+ /** Left location of the rectangle. */ -+ gctINT x; -+ -+ /** Top location of the rectangle. */ -+ gctINT y; -+ -+ /** Width of the rectangle. */ -+ gctINT width; -+ -+ /** Height of the rectangle. */ -+ gctINT height; -+} -+gcsVG_RECT; -+ -+/** -+** @ingroup gcoVG -+** -+** @brief Path command buffer attribute structure. -+** -+** The gcsPATH_BUFFER_INFO structure contains the specifics about -+** the layout of the path data command buffer. -+*/ -+typedef struct _gcsPATH_BUFFER_INFO * gcsPATH_BUFFER_INFO_PTR; -+typedef struct _gcsPATH_BUFFER_INFO -+{ -+ gctUINT reservedForHead; -+ gctUINT reservedForTail; -+} -+gcsPATH_BUFFER_INFO; -+ -+/** -+** @ingroup gcoVG -+** -+** @brief Definition of the path data container structure. -+** -+** The gcsPATH structure defines the layout of the path data container. -+*/ -+typedef struct _gcsPATH_DATA * gcsPATH_DATA_PTR; -+typedef struct _gcsPATH_DATA -+{ -+ /* Data container in command buffer format. */ -+ gcsCMDBUFFER data; -+ -+ /* Path data type. */ -+ gcePATHTYPE dataType; -+} -+gcsPATH_DATA; -+ -+ -+/******************************************************************************\ -+********************************* gcoHAL Object ******************************** -+\******************************************************************************/ -+ -+/* Query path data storage attributes. */ -+gceSTATUS -+gcoHAL_QueryPathStorage( -+ IN gcoHAL Hal, -+#if GC355_PROFILER -+ IN gcoVG Vg, -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ OUT gcsPATH_BUFFER_INFO_PTR Information -+ ); -+ -+/* Associate a completion signal with the command buffer. */ -+gceSTATUS -+gcoHAL_AssociateCompletion( -+ IN gcoHAL Hal, -+#if GC355_PROFILER -+ IN gcoVG Vg, -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gcsPATH_DATA_PTR PathData -+ ); -+ -+/* Release the current command buffer completion signal. */ -+gceSTATUS -+gcoHAL_DeassociateCompletion( -+ IN gcoHAL Hal, -+#if GC355_PROFILER -+ IN gcoVG Vg, -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gcsPATH_DATA_PTR PathData -+ ); -+ -+/* Verify whether the command buffer is still in use. */ -+gceSTATUS -+gcoHAL_CheckCompletion( -+ IN gcoHAL Hal, -+#if GC355_PROFILER -+ IN gcoVG Vg, -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gcsPATH_DATA_PTR PathData -+ ); -+ -+/* Wait until the command buffer is no longer in use. */ -+gceSTATUS -+gcoHAL_WaitCompletion( -+ IN gcoHAL Hal, -+#if GC355_PROFILER -+ IN gcoVG Vg, -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gcsPATH_DATA_PTR PathData -+ ); -+ -+/* Flush the pixel cache. */ -+gceSTATUS -+gcoHAL_Flush( -+ IN gcoHAL Hal -+#if GC355_PROFILER -+ , -+ IN gcoVG Vg, -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth -+#endif -+ ); -+ -+/* Split a harwdare address into pool and offset. */ -+gceSTATUS -+gcoHAL_SplitAddress( -+ IN gcoHAL Hal, -+#if GC355_PROFILER -+ IN gcoVG Vg, -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gctUINT32 Address, -+ OUT gcePOOL * Pool, -+ OUT gctUINT32 * Offset -+ ); -+ -+/* Combine pool and offset into a harwdare address. */ -+gceSTATUS -+gcoHAL_CombineAddress( -+ IN gcoHAL Hal, -+#if GC355_PROFILER -+ IN gcoVG Vg, -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gcePOOL Pool, -+ IN gctUINT32 Offset, -+ OUT gctUINT32 * Address -+ ); -+ -+/* Schedule to free linear video memory allocated. */ -+gceSTATUS -+gcoHAL_ScheduleVideoMemory( -+ IN gcoHAL Hal, -+#if GC355_PROFILER -+ IN gcoVG Vg, -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gctUINT32 Node -+ ); -+ -+/* Free linear video memory allocated with gcoHAL_AllocateLinearVideoMemory. */ -+gceSTATUS -+gcoHAL_FreeVideoMemory( -+ IN gcoHAL Hal, -+#if GC355_PROFILER -+ IN gcoVG Vg, -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gctUINT32 Node -+ ); -+ -+/* Query command buffer attributes. */ -+gceSTATUS -+gcoHAL_QueryCommandBuffer( -+ IN gcoHAL Hal, -+#if GC355_PROFILER -+ IN gcoVG Vg, -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ OUT gcsCOMMAND_BUFFER_INFO_PTR Information -+ ); -+/* Allocate and lock linear video memory. */ -+gceSTATUS -+gcoHAL_AllocateLinearVideoMemory( -+ IN gcoHAL Hal, -+#if GC355_PROFILER -+ IN gcoVG Vg, -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gctUINT Size, -+ IN gctUINT Alignment, -+ IN gcePOOL Pool, -+ OUT gctUINT32 * Node, -+ OUT gctUINT32 * Address, -+ OUT gctPOINTER * Memory -+ ); -+ -+/* Align the specified size accordingly to the hardware requirements. */ -+gceSTATUS -+gcoHAL_GetAlignedSurfaceSize( -+ IN gcoHAL Hal, -+#if GC355_PROFILER -+ IN gcoVG Vg, -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gceSURF_TYPE Type, -+ IN OUT gctUINT32_PTR Width, -+ IN OUT gctUINT32_PTR Height -+ ); -+ -+gceSTATUS -+gcoHAL_ReserveTask( -+ IN gcoHAL Hal, -+#if GC355_PROFILER -+ IN gcoVG Vg, -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gceBLOCK Block, -+ IN gctUINT TaskCount, -+ IN gctUINT32 Bytes, -+ OUT gctPOINTER * Memory -+ ); -+/******************************************************************************\ -+********************************** gcoVG Object ******************************** -+\******************************************************************************/ -+ -+/** @defgroup gcoVG gcoVG -+** -+** The gcoVG object abstracts the VG hardware pipe. -+*/ -+#if GC355_PROFILER -+void -+gcoVG_ProfilerEnableDisable( -+ IN gcoVG Vg, -+ IN gctUINT enableGetAPITimes, -+ IN gctFILE apiTimeFile -+ ); -+ -+void -+gcoVG_ProfilerTreeDepth( -+ IN gcoVG Vg, -+ IN gctUINT TreeDepth -+ ); -+ -+void -+gcoVG_ProfilerSetStates( -+ IN gcoVG Vg, -+ IN gctUINT treeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth -+ ); -+#endif -+ -+gctBOOL -+gcoVG_IsMaskSupported( -+#if GC355_PROFILER -+ IN gcoVG Vg, -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gceSURF_FORMAT Format -+ ); -+ -+gctBOOL -+gcoVG_IsTargetSupported( -+#if GC355_PROFILER -+ IN gcoVG Vg, -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gceSURF_FORMAT Format -+ ); -+ -+gctBOOL -+gcoVG_IsImageSupported( -+#if GC355_PROFILER -+ IN gcoVG Vg, -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gceSURF_FORMAT Format -+ ); -+ -+gctUINT8 gcoVG_PackColorComponent( -+#if GC355_PROFILER -+ gcoVG Vg, -+ gctUINT TreeDepth, -+ gctUINT saveLayerTreeDepth, -+ gctUINT varTreeDepth, -+#endif -+ gctFLOAT Value -+ ); -+ -+gceSTATUS -+gcoVG_Construct( -+ IN gcoHAL Hal, -+ OUT gcoVG * Vg -+ ); -+ -+gceSTATUS -+gcoVG_Destroy( -+ IN gcoVG Vg -+#if GC355_PROFILER -+ , -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth -+#endif -+ ); -+ -+gceSTATUS -+gcoVG_SetTarget( -+ IN gcoVG Vg, -+#if GC355_PROFILER -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gcoSURF Target -+ ); -+ -+gceSTATUS -+gcoVG_UnsetTarget( -+ IN gcoVG Vg, -+#if GC355_PROFILER -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gcoSURF Surface -+ ); -+ -+gceSTATUS -+gcoVG_SetUserToSurface( -+ IN gcoVG Vg, -+#if GC355_PROFILER -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gctFLOAT UserToSurface[9] -+ ); -+ -+gceSTATUS -+gcoVG_SetSurfaceToImage( -+ IN gcoVG Vg, -+#if GC355_PROFILER -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gctFLOAT SurfaceToImage[9] -+ ); -+ -+gceSTATUS -+gcoVG_EnableMask( -+ IN gcoVG Vg, -+#if GC355_PROFILER -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gctBOOL Enable -+ ); -+ -+gceSTATUS -+gcoVG_SetMask( -+ IN gcoVG Vg, -+#if GC355_PROFILER -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gcoSURF Mask -+ ); -+ -+gceSTATUS -+gcoVG_UnsetMask( -+ IN gcoVG Vg, -+#if GC355_PROFILER -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gcoSURF Surface -+ ); -+ -+gceSTATUS -+gcoVG_FlushMask( -+ IN gcoVG Vg -+#if GC355_PROFILER -+ , -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth -+#endif -+ ); -+ -+gceSTATUS -+gcoVG_EnableScissor( -+ IN gcoVG Vg, -+#if GC355_PROFILER -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gctBOOL Enable -+ ); -+ -+gceSTATUS -+gcoVG_SetScissor( -+ IN gcoVG Vg, -+#if GC355_PROFILER -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gctSIZE_T RectangleCount, -+ IN gcsVG_RECT_PTR Rectangles -+ ); -+ -+gceSTATUS -+gcoVG_EnableColorTransform( -+ IN gcoVG Vg, -+#if GC355_PROFILER -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gctBOOL Enable -+ ); -+ -+gceSTATUS -+gcoVG_SetColorTransform( -+ IN gcoVG Vg, -+#if GC355_PROFILER -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gctFLOAT ColorTransform[8] -+ ); -+ -+gceSTATUS -+gcoVG_SetTileFillColor( -+ IN gcoVG Vg, -+#if GC355_PROFILER -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gctFLOAT Red, -+ IN gctFLOAT Green, -+ IN gctFLOAT Blue, -+ IN gctFLOAT Alpha -+ ); -+ -+gceSTATUS -+gcoVG_SetSolidPaint( -+ IN gcoVG Vg, -+#if GC355_PROFILER -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gctUINT8 Red, -+ IN gctUINT8 Green, -+ IN gctUINT8 Blue, -+ IN gctUINT8 Alpha -+ ); -+ -+gceSTATUS -+gcoVG_SetLinearPaint( -+ IN gcoVG Vg, -+#if GC355_PROFILER -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gctFLOAT Constant, -+ IN gctFLOAT StepX, -+ IN gctFLOAT StepY -+ ); -+ -+gceSTATUS -+gcoVG_SetRadialPaint( -+ IN gcoVG Vg, -+#if GC355_PROFILER -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gctFLOAT LinConstant, -+ IN gctFLOAT LinStepX, -+ IN gctFLOAT LinStepY, -+ IN gctFLOAT RadConstant, -+ IN gctFLOAT RadStepX, -+ IN gctFLOAT RadStepY, -+ IN gctFLOAT RadStepXX, -+ IN gctFLOAT RadStepYY, -+ IN gctFLOAT RadStepXY -+ ); -+ -+gceSTATUS -+gcoVG_SetPatternPaint( -+ IN gcoVG Vg, -+#if GC355_PROFILER -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gctFLOAT UConstant, -+ IN gctFLOAT UStepX, -+ IN gctFLOAT UStepY, -+ IN gctFLOAT VConstant, -+ IN gctFLOAT VStepX, -+ IN gctFLOAT VStepY, -+ IN gctBOOL Linear -+ ); -+ -+gceSTATUS -+gcoVG_SetColorRamp( -+ IN gcoVG Vg, -+#if GC355_PROFILER -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gcoSURF ColorRamp, -+ IN gceTILE_MODE ColorRampSpreadMode -+ ); -+ -+gceSTATUS -+gcoVG_SetPattern( -+ IN gcoVG Vg, -+#if GC355_PROFILER -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gctINT32 width, -+ IN gctINT32 height, -+ IN gcoSURF Pattern, -+ IN gceTILE_MODE TileMode, -+ IN gceIMAGE_FILTER Filter -+ ); -+ -+gceSTATUS -+gcoVG_SetImageMode( -+ IN gcoVG Vg, -+#if GC355_PROFILER -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gceVG_IMAGE Mode -+ ); -+ -+gceSTATUS -+gcoVG_SetBlendMode( -+ IN gcoVG Vg, -+#if GC355_PROFILER -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gceVG_BLEND Mode -+ ); -+ -+gceSTATUS -+gcoVG_SetRenderingQuality( -+ IN gcoVG Vg, -+#if GC355_PROFILER -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gceRENDER_QUALITY Quality -+ ); -+ -+gceSTATUS -+gcoVG_SetFillRule( -+ IN gcoVG Vg, -+#if GC355_PROFILER -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gceFILL_RULE FillRule -+ ); -+ -+gceSTATUS -+gcoVG_FinalizePath( -+ IN gcoVG Vg, -+ IN gcsPATH_DATA_PTR PathData -+ ); -+ -+gceSTATUS -+gcoVG_Clear( -+ IN gcoVG Vg, -+#if GC355_PROFILER -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gctINT X, -+ IN gctINT Y, -+ IN gctINT Width, -+ IN gctINT Height -+ ); -+ -+gceSTATUS -+gcoVG_DrawPath( -+ IN gcoVG Vg, -+#if GC355_PROFILER -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gcsPATH_DATA_PTR PathData, -+ IN gctFLOAT Scale, -+ IN gctFLOAT Bias, -+#if gcdMOVG -+ IN gctUINT32 Width, -+ IN gctUINT32 Height, -+ IN gctFLOAT *Bounds, -+#endif -+ IN gctBOOL SoftwareTesselation -+ ); -+ -+gceSTATUS -+gcoVG_DrawImage( -+ IN gcoVG Vg, -+#if GC355_PROFILER -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gcoSURF Source, -+ IN gcsPOINT_PTR SourceOrigin, -+ IN gcsPOINT_PTR TargetOrigin, -+ IN gcsSIZE_PTR SourceSize, -+ IN gctINT SourceX, -+ IN gctINT SourceY, -+ IN gctINT TargetX, -+ IN gctINT TargetY, -+ IN gctINT Width, -+ IN gctINT Height, -+ IN gctBOOL Mask, -+ IN gctBOOL isDrawImage -+ ); -+ -+gceSTATUS -+gcoVG_TesselateImage( -+ IN gcoVG Vg, -+#if GC355_PROFILER -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gcoSURF Image, -+ IN gcsVG_RECT_PTR Rectangle, -+ IN gceIMAGE_FILTER Filter, -+ IN gctBOOL Mask, -+#if gcdMOVG -+ IN gctBOOL SoftwareTesselation, -+ IN gceVG_BLEND BlendMode -+#else -+ IN gctBOOL SoftwareTesselation -+#endif -+ ); -+ -+gceSTATUS -+gcoVG_Blit( -+ IN gcoVG Vg, -+#if GC355_PROFILER -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gcoSURF Source, -+ IN gcoSURF Target, -+ IN gcsVG_RECT_PTR SrcRect, -+ IN gcsVG_RECT_PTR TrgRect, -+ IN gceIMAGE_FILTER Filter, -+ IN gceVG_BLEND Mode -+ ); -+ -+gceSTATUS -+gcoVG_ColorMatrix( -+ IN gcoVG Vg, -+#if GC355_PROFILER -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gcoSURF Source, -+ IN gcoSURF Target, -+ IN const gctFLOAT * Matrix, -+ IN gceCHANNEL ColorChannels, -+ IN gctBOOL FilterLinear, -+ IN gctBOOL FilterPremultiplied, -+ IN gcsPOINT_PTR SourceOrigin, -+ IN gcsPOINT_PTR TargetOrigin, -+ IN gctINT Width, -+ IN gctINT Height -+ ); -+ -+gceSTATUS -+gcoVG_SeparableConvolve( -+ IN gcoVG Vg, -+#if GC355_PROFILER -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gcoSURF Source, -+ IN gcoSURF Target, -+ IN gctINT KernelWidth, -+ IN gctINT KernelHeight, -+ IN gctINT ShiftX, -+ IN gctINT ShiftY, -+ IN const gctINT16 * KernelX, -+ IN const gctINT16 * KernelY, -+ IN gctFLOAT Scale, -+ IN gctFLOAT Bias, -+ IN gceTILE_MODE TilingMode, -+ IN gctFLOAT_PTR FillColor, -+ IN gceCHANNEL ColorChannels, -+ IN gctBOOL FilterLinear, -+ IN gctBOOL FilterPremultiplied, -+ IN gcsPOINT_PTR SourceOrigin, -+ IN gcsPOINT_PTR TargetOrigin, -+ IN gcsSIZE_PTR SourceSize, -+ IN gctINT Width, -+ IN gctINT Height -+ ); -+ -+gceSTATUS -+gcoVG_GaussianBlur( -+ IN gcoVG Vg, -+#if GC355_PROFILER -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gcoSURF Source, -+ IN gcoSURF Target, -+ IN gctFLOAT StdDeviationX, -+ IN gctFLOAT StdDeviationY, -+ IN gceTILE_MODE TilingMode, -+ IN gctFLOAT_PTR FillColor, -+ IN gceCHANNEL ColorChannels, -+ IN gctBOOL FilterLinear, -+ IN gctBOOL FilterPremultiplied, -+ IN gcsPOINT_PTR SourceOrigin, -+ IN gcsPOINT_PTR TargetOrigin, -+ IN gcsSIZE_PTR SourceSize, -+ IN gctINT Width, -+ IN gctINT Height -+ ); -+ -+gceSTATUS -+gcoVG_EnableDither( -+ IN gcoVG Vg, -+#if GC355_PROFILER -+ IN gctUINT TreeDepth, -+ IN gctUINT saveLayerTreeDepth, -+ IN gctUINT varTreeDepth, -+#endif -+ IN gctBOOL Enable -+ ); -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* __gc_hal_vg_h_ */ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_enum.h linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_enum.h ---- linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_enum.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_enum.h 2015-11-30 17:56:13.592136927 +0100 -@@ -0,0 +1,1605 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#ifndef __gc_hal_enum_h_ -+#define __gc_hal_enum_h_ -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+/* Chip models. */ -+typedef enum _gceCHIPMODEL -+{ -+ gcv200 = 0x0200, -+ gcv300 = 0x0300, -+ gcv320 = 0x0320, -+ gcv328 = 0x0328, -+ gcv350 = 0x0350, -+ gcv355 = 0x0355, -+ gcv400 = 0x0400, -+ gcv410 = 0x0410, -+ gcv420 = 0x0420, -+ gcv428 = 0x0428, -+ gcv450 = 0x0450, -+ gcv500 = 0x0500, -+ gcv520 = 0x0520, -+ gcv530 = 0x0530, -+ gcv600 = 0x0600, -+ gcv700 = 0x0700, -+ gcv800 = 0x0800, -+ gcv860 = 0x0860, -+ gcv880 = 0x0880, -+ gcv1000 = 0x1000, -+ gcv1500 = 0x1500, -+ gcv2000 = 0x2000, -+ gcv2100 = 0x2100, -+ gcv2200 = 0x2200, -+ gcv2500 = 0x2500, -+ gcv3000 = 0x3000, -+ gcv4000 = 0x4000, -+ gcv5000 = 0x5000, -+ gcv5200 = 0x5200, -+ gcv6400 = 0x6400, -+} -+gceCHIPMODEL; -+ -+/* Chip features. */ -+typedef enum _gceFEATURE -+{ -+ gcvFEATURE_PIPE_2D = 0, -+ gcvFEATURE_PIPE_3D, -+ gcvFEATURE_PIPE_VG, -+ gcvFEATURE_DC, -+ gcvFEATURE_HIGH_DYNAMIC_RANGE, -+ gcvFEATURE_MODULE_CG, -+ gcvFEATURE_MIN_AREA, -+ gcvFEATURE_BUFFER_INTERLEAVING, -+ gcvFEATURE_BYTE_WRITE_2D, -+ gcvFEATURE_ENDIANNESS_CONFIG, -+ gcvFEATURE_DUAL_RETURN_BUS, -+ gcvFEATURE_DEBUG_MODE, -+ gcvFEATURE_YUY2_RENDER_TARGET, -+ gcvFEATURE_FRAGMENT_PROCESSOR, -+ gcvFEATURE_2DPE20, -+ gcvFEATURE_FAST_CLEAR, -+ gcvFEATURE_YUV420_TILER, -+ gcvFEATURE_YUY2_AVERAGING, -+ gcvFEATURE_FLIP_Y, -+ gcvFEATURE_EARLY_Z, -+ gcvFEATURE_COMPRESSION, -+ gcvFEATURE_MSAA, -+ gcvFEATURE_SPECIAL_ANTI_ALIASING, -+ gcvFEATURE_SPECIAL_MSAA_LOD, -+ gcvFEATURE_422_TEXTURE_COMPRESSION, -+ gcvFEATURE_DXT_TEXTURE_COMPRESSION, -+ gcvFEATURE_ETC1_TEXTURE_COMPRESSION, -+ gcvFEATURE_CORRECT_TEXTURE_CONVERTER, -+ gcvFEATURE_TEXTURE_8K, -+ gcvFEATURE_SCALER, -+ gcvFEATURE_YUV420_SCALER, -+ gcvFEATURE_SHADER_HAS_W, -+ gcvFEATURE_SHADER_HAS_SIGN, -+ gcvFEATURE_SHADER_HAS_FLOOR, -+ gcvFEATURE_SHADER_HAS_CEIL, -+ gcvFEATURE_SHADER_HAS_SQRT, -+ gcvFEATURE_SHADER_HAS_TRIG, -+ gcvFEATURE_VAA, -+ gcvFEATURE_HZ, -+ gcvFEATURE_CORRECT_STENCIL, -+ gcvFEATURE_VG20, -+ gcvFEATURE_VG_FILTER, -+ gcvFEATURE_VG21, -+ gcvFEATURE_VG_DOUBLE_BUFFER, -+ gcvFEATURE_MC20, -+ gcvFEATURE_SUPER_TILED, -+ gcvFEATURE_FAST_CLEAR_FLUSH, -+ gcvFEATURE_2D_FILTERBLIT_PLUS_ALPHABLEND, -+ gcvFEATURE_2D_DITHER, -+ gcvFEATURE_2D_A8_TARGET, -+ gcvFEATURE_2D_A8_NO_ALPHA, -+ gcvFEATURE_2D_FILTERBLIT_FULLROTATION, -+ gcvFEATURE_2D_BITBLIT_FULLROTATION, -+ gcvFEATURE_WIDE_LINE, -+ gcvFEATURE_FC_FLUSH_STALL, -+ gcvFEATURE_FULL_DIRECTFB, -+ gcvFEATURE_HALF_FLOAT_PIPE, -+ gcvFEATURE_LINE_LOOP, -+ gcvFEATURE_2D_YUV_BLIT, -+ gcvFEATURE_2D_TILING, -+ gcvFEATURE_NON_POWER_OF_TWO, -+ gcvFEATURE_3D_TEXTURE, -+ gcvFEATURE_TEXTURE_ARRAY, -+ gcvFEATURE_TILE_FILLER, -+ gcvFEATURE_LOGIC_OP, -+ gcvFEATURE_COMPOSITION, -+ gcvFEATURE_MIXED_STREAMS, -+ gcvFEATURE_2D_MULTI_SOURCE_BLT, -+ gcvFEATURE_END_EVENT, -+ gcvFEATURE_VERTEX_10_10_10_2, -+ gcvFEATURE_TEXTURE_10_10_10_2, -+ gcvFEATURE_TEXTURE_ANISOTROPIC_FILTERING, -+ gcvFEATURE_TEXTURE_FLOAT_HALF_FLOAT, -+ gcvFEATURE_2D_ROTATION_STALL_FIX, -+ gcvFEATURE_2D_MULTI_SOURCE_BLT_EX, -+ gcvFEATURE_BUG_FIXES10, -+ gcvFEATURE_2D_MINOR_TILING, -+ /* Supertiled compressed textures are supported. */ -+ gcvFEATURE_TEX_COMPRRESSION_SUPERTILED, -+ gcvFEATURE_FAST_MSAA, -+ gcvFEATURE_BUG_FIXED_INDEXED_TRIANGLE_STRIP, -+ gcvFEATURE_TEXTURE_TILE_STATUS_READ, -+ gcvFEATURE_DEPTH_BIAS_FIX, -+ gcvFEATURE_RECT_PRIMITIVE, -+ gcvFEATURE_BUG_FIXES11, -+ gcvFEATURE_SUPERTILED_TEXTURE, -+ gcvFEATURE_2D_NO_COLORBRUSH_INDEX8, -+ gcvFEATURE_RS_YUV_TARGET, -+ gcvFEATURE_2D_FC_SOURCE, -+ gcvFEATURE_2D_CC_NOAA_SOURCE, -+ gcvFEATURE_PE_DITHER_FIX, -+ gcvFEATURE_2D_YUV_SEPARATE_STRIDE, -+ gcvFEATURE_FRUSTUM_CLIP_FIX, -+ gcvFEATURE_TEXTURE_SWIZZLE, -+ gcvFEATURE_PRIMITIVE_RESTART, -+ gcvFEATURE_TEXTURE_LINEAR, -+ gcvFEATURE_TEXTURE_YUV_ASSEMBLER, -+ gcvFEATURE_LINEAR_RENDER_TARGET, -+ gcvFEATURE_SHADER_HAS_ATOMIC, -+ gcvFEATURE_SHADER_HAS_INSTRUCTION_CACHE, -+ gcvFEATURE_SHADER_ENHANCEMENTS2, -+ gcvFEATURE_BUG_FIXES7, -+ gcvFEATURE_SHADER_HAS_RTNE, -+ gcvFEATURE_SHADER_HAS_EXTRA_INSTRUCTIONS2, -+ gcvFEATURE_SHADER_ENHANCEMENTS3, -+ gcvFEATURE_DYNAMIC_FREQUENCY_SCALING, -+ gcvFEATURE_SINGLE_BUFFER, -+ gcvFEATURE_OCCLUSION_QUERY, -+ gcvFEATURE_2D_GAMMA, -+ gcvFEATURE_2D_COLOR_SPACE_CONVERSION, -+ gcvFEATURE_2D_SUPER_TILE_VERSION, -+ gcvFEATURE_HALTI0, -+ gcvFEATURE_HALTI1, -+ gcvFEATURE_HALTI2, -+ gcvFEATURE_2D_MIRROR_EXTENSION, -+ gcvFEATURE_TEXTURE_ASTC, -+ gcvFEATURE_2D_SUPER_TILE_V1, -+ gcvFEATURE_2D_SUPER_TILE_V2, -+ gcvFEATURE_2D_SUPER_TILE_V3, -+ gcvFEATURE_2D_MULTI_SOURCE_BLT_EX2, -+ gcvFEATURE_NEW_RA, -+ gcvFEATURE_BUG_FIXED_IMPLICIT_PRIMITIVE_RESTART, -+ gcvFEATURE_PE_MULTI_RT_BLEND_ENABLE_CONTROL, -+ gcvFEATURE_SMALL_MSAA, /* An upgraded version of Fast MSAA */ -+ gcvFEATURE_VERTEX_INST_ID_AS_ATTRIBUTE, -+ gcvFEATURE_DUAL_16, -+ gcvFEATURE_BRANCH_ON_IMMEDIATE_REG, -+ gcvFEATURE_2D_COMPRESSION, -+ gcvFEATURE_TPC_COMPRESSION, -+ gcvFEATURE_2D_OPF_YUV_OUTPUT, -+ gcvFEATURE_2D_FILTERBLIT_A8_ALPHA, -+ gcvFEATURE_2D_MULTI_SRC_BLT_TO_UNIFIED_DST_RECT, -+ gcvFEATURE_V2_COMPRESSION_Z16_FIX, -+ -+ gcvFEATURE_VERTEX_INST_ID_AS_INTEGER, -+ gcvFEATURE_2D_YUV_MODE, -+ gcvFEATURE_ACE, -+ gcvFEATURE_COLOR_COMPRESSION, -+ -+ gcvFEATURE_32BPP_COMPONENT_TEXTURE_CHANNEL_SWIZZLE, -+ gcvFEATURE_64BPP_HW_CLEAR_SUPPORT, -+ gcvFEATURE_TX_LERP_PRECISION_FIX, -+ gcvFEATURE_COMPRESSION_V2, -+ gcvFEATURE_MMU, -+ gcvFEATURE_COMPRESSION_V3, -+ gcvFEATURE_TX_DECOMPRESSOR, -+ gcvFEATURE_MRT_TILE_STATUS_BUFFER, -+ gcvFEATURE_COMPRESSION_V1, -+ gcvFEATURE_V1_COMPRESSION_Z16_DECOMPRESS_FIX, -+ gcvFEATURE_RTT, -+ gcvFEATURE_GENERICS, -+ gcvFEATURE_2D_ONE_PASS_FILTER, -+ gcvFEATURE_2D_ONE_PASS_FILTER_TAP, -+ gcvFEATURE_2D_POST_FLIP, -+ gcvFEATURE_2D_PIXEL_ALIGNMENT, -+ gcvFEATURE_CORRECT_AUTO_DISABLE_COUNT, -+ gcvFEATURE_CORRECT_AUTO_DISABLE_COUNT_WIDTH, -+ -+ gcvFEATURE_HALTI3, -+ gcvFEATURE_EEZ, -+ gcvFEATURE_INTEGER_PIPE_FIX, -+ gcvFEATURE_PSOUTPUT_MAPPING, -+ gcvFEATURE_8K_RT_FIX, -+ gcvFEATURE_TX_TILE_STATUS_MAPPING, -+ gcvFEATURE_SRGB_RT_SUPPORT, -+ gcvFEATURE_UNIFORM_APERTURE, -+ gcvFEATURE_TEXTURE_16K, -+ gcvFEATURE_PA_FARZCLIPPING_FIX, -+ gcvFEATURE_PE_DITHER_COLORMASK_FIX, -+ gcvFEATURE_ZSCALE_FIX, -+ -+ gcvFEATURE_MULTI_PIXELPIPES, -+ gcvFEATURE_PIPE_CL, -+ -+ gcvFEATURE_BUG_FIXES18, -+ -+ gcvFEATURE_UNIFIED_SAMPLERS, -+ gcvFEATURE_CL_PS_WALKER, -+ gcvFEATURE_NEW_HZ, -+ -+ gcvFEATURE_TX_FRAC_PRECISION_6BIT, -+ gcvFEATURE_SH_INSTRUCTION_PREFETCH, -+ gcvFEATURE_PROBE, -+ -+ gcvFEATURE_BUG_FIXES8, -+ gcvFEATURE_2D_ALL_QUAD, -+ -+ gcvFEATURE_SINGLE_PIPE_HALTI1, -+ -+ gcvFEATURE_BLOCK_SIZE_16x16, -+ -+ gcvFEATURE_NO_USER_CSC, -+ gcvFEATURE_ANDROID_ONLY, -+ gcvFEATURE_HAS_PRODUCTID, -+ -+ gcvFEATURE_V2_MSAA_COMP_FIX, -+ -+ gcvFEATURE_S8_ONLY_RENDERING, -+ -+ gcvFEATURE_SEPARATE_SRC_DST, -+ -+ gcvFEATURE_FE_START_VERTEX_SUPPORT, -+ gcvFEATURE_RS_DEPTHSTENCIL_NATIVE_SUPPORT, -+ -+ /* Insert features above this comment only. */ -+ gcvFEATURE_COUNT /* Not a feature. */ -+} -+gceFEATURE; -+ -+/* Chip SWWA. */ -+typedef enum _gceSWWA -+{ -+ gcvSWWA_601 = 0, -+ gcvSWWA_706, -+ gcvSWWA_1163, -+ gcvSWWA_1165, -+ /* Insert SWWA above this comment only. */ -+ gcvSWWA_COUNT /* Not a SWWA. */ -+} -+gceSWWA; -+ -+ -+/* Option Set*/ -+typedef enum _gceOPITON -+{ -+ /* HW setting we take PREFER */ -+ gcvOPTION_PREFER_MULTIPIPE_RS = 0, -+ gcvOPTION_PREFER_ZCONVERT_BYPASS =1, -+ -+ -+ gcvOPTION_HW_NULL = 50, -+ gcvOPTION_PRINT_OPTION = 51, -+ -+ gcvOPTION_FBO_PREFER_MEM = 80, -+ -+ /* Insert option above this comment only */ -+ gcvOPTION_COUNT /* Not a OPTION*/ -+} -+gceOPTION; -+ -+typedef enum _gceFRAMEINFO -+{ -+ gcvFRAMEINFO_FRAME_NUM = 0, -+ gcvFRAMEINFO_DRAW_NUM = 1, -+ gcvFRAMEINFO_DRAW_DUAL16_NUM = 2, -+ gcvFRAMEINFO_DRAW_FL32_NUM = 3, -+ -+ -+ gcvFRAMEINFO_COUNT, -+} -+gceFRAMEINFO; -+ -+typedef enum _gceFRAMEINFO_OP -+{ -+ gcvFRAMEINFO_OP_INC = 0, -+ gcvFRAMEINFO_OP_DEC = 1, -+ gcvFRAMEINFO_OP_ZERO = 2, -+ gcvFRAMEINFO_OP_GET = 3, -+ -+ -+ gcvFRAMEINFO_OP_COUNT, -+} -+gceFRAMEINFO_OP; -+ -+ -+/* Chip Power Status. */ -+typedef enum _gceCHIPPOWERSTATE -+{ -+ gcvPOWER_ON = 0, -+ gcvPOWER_OFF, -+ gcvPOWER_IDLE, -+ gcvPOWER_SUSPEND, -+ gcvPOWER_SUSPEND_ATPOWERON, -+ gcvPOWER_OFF_ATPOWERON, -+ gcvPOWER_IDLE_BROADCAST, -+ gcvPOWER_SUSPEND_BROADCAST, -+ gcvPOWER_OFF_BROADCAST, -+ gcvPOWER_OFF_RECOVERY, -+ gcvPOWER_OFF_TIMEOUT, -+ gcvPOWER_ON_AUTO -+} -+gceCHIPPOWERSTATE; -+ -+/* CPU cache operations */ -+typedef enum _gceCACHEOPERATION -+{ -+ gcvCACHE_CLEAN = 0x01, -+ gcvCACHE_INVALIDATE = 0x02, -+ gcvCACHE_FLUSH = gcvCACHE_CLEAN | gcvCACHE_INVALIDATE, -+ gcvCACHE_MEMORY_BARRIER = 0x04 -+} -+gceCACHEOPERATION; -+ -+/* Surface types. */ -+typedef enum _gceSURF_TYPE -+{ -+ gcvSURF_TYPE_UNKNOWN = 0, -+ gcvSURF_INDEX, -+ gcvSURF_VERTEX, -+ gcvSURF_TEXTURE, -+ gcvSURF_RENDER_TARGET, -+ gcvSURF_DEPTH, -+ gcvSURF_BITMAP, -+ gcvSURF_TILE_STATUS, -+ gcvSURF_IMAGE, -+ gcvSURF_MASK, -+ gcvSURF_SCISSOR, -+ gcvSURF_HIERARCHICAL_DEPTH, -+ gcvSURF_NUM_TYPES, /* Make sure this is the last one! */ -+ -+ /* Combinations. */ -+ gcvSURF_NO_TILE_STATUS = 0x100, -+ gcvSURF_NO_VIDMEM = 0x200, /* Used to allocate surfaces with no underlying vidmem node. -+ In Android, vidmem node is allocated by another process. */ -+ gcvSURF_CACHEABLE = 0x400, /* Used to allocate a cacheable surface */ -+ -+ gcvSURF_FLIP = 0x800, /* The Resolve Target the will been flip resolve from RT */ -+ -+ gcvSURF_TILE_STATUS_DIRTY = 0x1000, /* Init tile status to all dirty */ -+ -+ gcvSURF_LINEAR = 0x2000, -+ -+ gcvSURF_CREATE_AS_TEXTURE = 0x4000, /* create it as a texture */ -+ -+ gcvSURF_PROTECTED_CONTENT = 0x8000, /* create it as content protected */ -+ -+ /* Create it as no compression, valid on when it has tile status. */ -+ gcvSURF_NO_COMPRESSION = 0x40000, -+ -+ gcvSURF_CONTIGUOUS = 0x20000, /*create it as contiguous */ -+ -+ gcvSURF_TEXTURE_LINEAR = gcvSURF_TEXTURE -+ | gcvSURF_LINEAR, -+ -+ gcvSURF_RENDER_TARGET_LINEAR = gcvSURF_RENDER_TARGET -+ | gcvSURF_LINEAR, -+ -+ gcvSURF_RENDER_TARGET_NO_TILE_STATUS = gcvSURF_RENDER_TARGET -+ | gcvSURF_NO_TILE_STATUS, -+ -+ gcvSURF_RENDER_TARGET_TS_DIRTY = gcvSURF_RENDER_TARGET -+ | gcvSURF_TILE_STATUS_DIRTY, -+ -+ gcvSURF_DEPTH_NO_TILE_STATUS = gcvSURF_DEPTH -+ | gcvSURF_NO_TILE_STATUS, -+ -+ gcvSURF_DEPTH_TS_DIRTY = gcvSURF_DEPTH -+ | gcvSURF_TILE_STATUS_DIRTY, -+ -+ /* Supported surface types with no vidmem node. */ -+ gcvSURF_BITMAP_NO_VIDMEM = gcvSURF_BITMAP -+ | gcvSURF_NO_VIDMEM, -+ -+ gcvSURF_TEXTURE_NO_VIDMEM = gcvSURF_TEXTURE -+ | gcvSURF_NO_VIDMEM, -+ -+ /* Cacheable surface types with no vidmem node. */ -+ gcvSURF_CACHEABLE_BITMAP_NO_VIDMEM = gcvSURF_BITMAP_NO_VIDMEM -+ | gcvSURF_CACHEABLE, -+ -+ gcvSURF_CACHEABLE_BITMAP = gcvSURF_BITMAP -+ | gcvSURF_CACHEABLE, -+ -+ gcvSURF_FLIP_BITMAP = gcvSURF_BITMAP -+ | gcvSURF_FLIP, -+} -+gceSURF_TYPE; -+ -+typedef enum _gceSURF_USAGE -+{ -+ gcvSURF_USAGE_UNKNOWN, -+ gcvSURF_USAGE_RESOLVE_AFTER_CPU, -+ gcvSURF_USAGE_RESOLVE_AFTER_3D -+} -+gceSURF_USAGE; -+ -+typedef enum _gceSURF_COLOR_SPACE -+{ -+ gcvSURF_COLOR_SPACE_UNKNOWN, -+ gcvSURF_COLOR_SPACE_LINEAR, -+ gcvSURF_COLOR_SPACE_NONLINEAR, -+} -+gceSURF_COLOR_SPACE; -+ -+typedef enum _gceSURF_COLOR_TYPE -+{ -+ gcvSURF_COLOR_UNKNOWN = 0, -+ gcvSURF_COLOR_LINEAR = 0x01, -+ gcvSURF_COLOR_ALPHA_PRE = 0x02, -+} -+gceSURF_COLOR_TYPE; -+ -+/* Rotation. */ -+typedef enum _gceSURF_ROTATION -+{ -+ gcvSURF_0_DEGREE = 0, -+ gcvSURF_90_DEGREE, -+ gcvSURF_180_DEGREE, -+ gcvSURF_270_DEGREE, -+ gcvSURF_FLIP_X, -+ gcvSURF_FLIP_Y, -+ -+ gcvSURF_POST_FLIP_X = 0x40000000, -+ gcvSURF_POST_FLIP_Y = 0x80000000, -+} -+gceSURF_ROTATION; -+ -+/* Surface flag */ -+typedef enum _gceSURF_FLAG -+{ -+ /* None flag */ -+ gcvSURF_FLAG_NONE = 0x0, -+ /* content is preserved after swap */ -+ gcvSURF_FLAG_CONTENT_PRESERVED = 0x1, -+ /* content is updated after swap*/ -+ gcvSURF_FLAG_CONTENT_UPDATED = 0x2, -+ /* content is y inverted */ -+ gcvSURF_FLAG_CONTENT_YINVERTED = 0x4, -+ /* content is protected */ -+ gcvSURF_FLAG_CONTENT_PROTECTED = 0x8, -+ /* surface is contiguous. */ -+ gcvSURF_FLAG_CONTIGUOUS = (1 << 4), -+} -+gceSURF_FLAG; -+ -+typedef enum _gceMIPMAP_IMAGE_FORMAT -+{ -+ gcvUNKNOWN_MIPMAP_IMAGE_FORMAT = -2 -+} -+gceMIPMAP_IMAGE_FORMAT; -+ -+/* Surface formats. */ -+typedef enum _gceSURF_FORMAT -+{ -+ /* Unknown format. */ -+ gcvSURF_UNKNOWN = 0, -+ -+ /* Palettized formats. */ -+ gcvSURF_INDEX1 = 100, -+ gcvSURF_INDEX4, -+ gcvSURF_INDEX8, -+ -+ /* RGB formats. */ -+ gcvSURF_A2R2G2B2 = 200, -+ gcvSURF_R3G3B2, -+ gcvSURF_A8R3G3B2, -+ gcvSURF_X4R4G4B4, -+ gcvSURF_A4R4G4B4, -+ gcvSURF_R4G4B4A4, -+ gcvSURF_X1R5G5B5, -+ gcvSURF_A1R5G5B5, -+ gcvSURF_R5G5B5A1, -+ gcvSURF_R5G6B5, -+ gcvSURF_R8G8B8, -+ gcvSURF_X8R8G8B8, -+ gcvSURF_A8R8G8B8, -+ gcvSURF_R8G8B8A8, -+ gcvSURF_G8R8G8B8, -+ gcvSURF_R8G8B8G8, -+ gcvSURF_X2R10G10B10, -+ gcvSURF_A2R10G10B10, -+ gcvSURF_X12R12G12B12, -+ gcvSURF_A12R12G12B12, -+ gcvSURF_X16R16G16B16, -+ gcvSURF_A16R16G16B16, -+ gcvSURF_A32R32G32B32, -+ gcvSURF_R8G8B8X8, -+ gcvSURF_R5G5B5X1, -+ gcvSURF_R4G4B4X4, -+ gcvSURF_X16R16G16B16_2_A8R8G8B8, -+ gcvSURF_A16R16G16B16_2_A8R8G8B8, -+ gcvSURF_A32R32G32B32_2_G32R32F, -+ gcvSURF_A32R32G32B32_4_A8R8G8B8, -+ -+ /* BGR formats. */ -+ gcvSURF_A4B4G4R4 = 300, -+ gcvSURF_A1B5G5R5, -+ gcvSURF_B5G6R5, -+ gcvSURF_B8G8R8, -+ gcvSURF_B16G16R16, -+ gcvSURF_X8B8G8R8, -+ gcvSURF_A8B8G8R8, -+ gcvSURF_A2B10G10R10, -+ gcvSURF_X16B16G16R16, -+ gcvSURF_A16B16G16R16, -+ gcvSURF_B32G32R32, -+ gcvSURF_X32B32G32R32, -+ gcvSURF_A32B32G32R32, -+ gcvSURF_B4G4R4A4, -+ gcvSURF_B5G5R5A1, -+ gcvSURF_B8G8R8X8, -+ gcvSURF_B8G8R8A8, -+ gcvSURF_X4B4G4R4, -+ gcvSURF_X1B5G5R5, -+ gcvSURF_B4G4R4X4, -+ gcvSURF_B5G5R5X1, -+ gcvSURF_X2B10G10R10, -+ gcvSURF_B8G8R8_SNORM, -+ gcvSURF_X8B8G8R8_SNORM, -+ gcvSURF_A8B8G8R8_SNORM, -+ gcvSURF_A8B12G12R12_2_A8R8G8B8, -+ -+ /* Compressed formats. */ -+ gcvSURF_DXT1 = 400, -+ gcvSURF_DXT2, -+ gcvSURF_DXT3, -+ gcvSURF_DXT4, -+ gcvSURF_DXT5, -+ gcvSURF_CXV8U8, -+ gcvSURF_ETC1, -+ gcvSURF_R11_EAC, -+ gcvSURF_SIGNED_R11_EAC, -+ gcvSURF_RG11_EAC, -+ gcvSURF_SIGNED_RG11_EAC, -+ gcvSURF_RGB8_ETC2, -+ gcvSURF_SRGB8_ETC2, -+ gcvSURF_RGB8_PUNCHTHROUGH_ALPHA1_ETC2, -+ gcvSURF_SRGB8_PUNCHTHROUGH_ALPHA1_ETC2, -+ gcvSURF_RGBA8_ETC2_EAC, -+ gcvSURF_SRGB8_ALPHA8_ETC2_EAC, -+ -+ /* YUV formats. */ -+ gcvSURF_YUY2 = 500, -+ gcvSURF_UYVY, -+ gcvSURF_YV12, -+ gcvSURF_I420, -+ gcvSURF_NV12, -+ gcvSURF_NV21, -+ gcvSURF_NV16, -+ gcvSURF_NV61, -+ gcvSURF_YVYU, -+ gcvSURF_VYUY, -+ -+ /* Depth formats. */ -+ gcvSURF_D16 = 600, -+ gcvSURF_D24S8, -+ gcvSURF_D32, -+ gcvSURF_D24X8, -+ gcvSURF_D32F, -+ gcvSURF_S8D32F, -+ gcvSURF_S8D32F_1_G32R32F, -+ gcvSURF_S8D32F_2_A8R8G8B8, -+ gcvSURF_D24S8_1_A8R8G8B8, -+ gcvSURF_S8, -+ -+ /* Alpha formats. */ -+ gcvSURF_A4 = 700, -+ gcvSURF_A8, -+ gcvSURF_A12, -+ gcvSURF_A16, -+ gcvSURF_A32, -+ gcvSURF_A1, -+ -+ /* Luminance formats. */ -+ gcvSURF_L4 = 800, -+ gcvSURF_L8, -+ gcvSURF_L12, -+ gcvSURF_L16, -+ gcvSURF_L32, -+ gcvSURF_L1, -+ -+ /* Alpha/Luminance formats. */ -+ gcvSURF_A4L4 = 900, -+ gcvSURF_A2L6, -+ gcvSURF_A8L8, -+ gcvSURF_A4L12, -+ gcvSURF_A12L12, -+ gcvSURF_A16L16, -+ -+ /* Bump formats. */ -+ gcvSURF_L6V5U5 = 1000, -+ gcvSURF_V8U8, -+ gcvSURF_X8L8V8U8, -+ gcvSURF_Q8W8V8U8, -+ gcvSURF_A2W10V10U10, -+ gcvSURF_V16U16, -+ gcvSURF_Q16W16V16U16, -+ -+ /* R/RG/RA formats. */ -+ gcvSURF_R8 = 1100, -+ gcvSURF_X8R8, -+ gcvSURF_G8R8, -+ gcvSURF_X8G8R8, -+ gcvSURF_A8R8, -+ gcvSURF_R16, -+ gcvSURF_X16R16, -+ gcvSURF_G16R16, -+ gcvSURF_X16G16R16, -+ gcvSURF_A16R16, -+ gcvSURF_R32, -+ gcvSURF_X32R32, -+ gcvSURF_G32R32, -+ gcvSURF_X32G32R32, -+ gcvSURF_A32R32, -+ gcvSURF_RG16, -+ gcvSURF_R8_SNORM, -+ gcvSURF_G8R8_SNORM, -+ -+ gcvSURF_R8_1_X8R8G8B8, -+ gcvSURF_G8R8_1_X8R8G8B8, -+ -+ /* Floating point formats. */ -+ gcvSURF_R16F = 1200, -+ gcvSURF_X16R16F, -+ gcvSURF_G16R16F, -+ gcvSURF_X16G16R16F, -+ gcvSURF_B16G16R16F, -+ gcvSURF_X16B16G16R16F, -+ gcvSURF_A16B16G16R16F, -+ gcvSURF_R32F, -+ gcvSURF_X32R32F, -+ gcvSURF_G32R32F, -+ gcvSURF_X32G32R32F, -+ gcvSURF_B32G32R32F, -+ gcvSURF_X32B32G32R32F, -+ gcvSURF_A32B32G32R32F, -+ gcvSURF_A16F, -+ gcvSURF_L16F, -+ gcvSURF_A16L16F, -+ gcvSURF_A16R16F, -+ gcvSURF_A32F, -+ gcvSURF_L32F, -+ gcvSURF_A32L32F, -+ gcvSURF_A32R32F, -+ gcvSURF_E5B9G9R9, -+ gcvSURF_B10G11R11F, -+ -+ gcvSURF_X16B16G16R16F_2_A8R8G8B8, -+ gcvSURF_A16B16G16R16F_2_A8R8G8B8, -+ gcvSURF_G32R32F_2_A8R8G8B8, -+ gcvSURF_X32B32G32R32F_2_G32R32F, -+ gcvSURF_A32B32G32R32F_2_G32R32F, -+ gcvSURF_X32B32G32R32F_4_A8R8G8B8, -+ gcvSURF_A32B32G32R32F_4_A8R8G8B8, -+ -+ gcvSURF_R16F_1_A4R4G4B4, -+ gcvSURF_G16R16F_1_A8R8G8B8, -+ gcvSURF_B16G16R16F_2_A8R8G8B8, -+ -+ gcvSURF_R32F_1_A8R8G8B8, -+ gcvSURF_B32G32R32F_3_A8R8G8B8, -+ -+ gcvSURF_B10G11R11F_1_A8R8G8B8, -+ -+ -+ /* sRGB format. */ -+ gcvSURF_SBGR8 = 1400, -+ gcvSURF_A8_SBGR8, -+ gcvSURF_X8_SBGR8, -+ -+ /* Integer formats. */ -+ gcvSURF_R8I = 1500, -+ gcvSURF_R8UI, -+ gcvSURF_R16I, -+ gcvSURF_R16UI, -+ gcvSURF_R32I, -+ gcvSURF_R32UI, -+ gcvSURF_X8R8I, -+ gcvSURF_G8R8I, -+ gcvSURF_X8R8UI, -+ gcvSURF_G8R8UI, -+ gcvSURF_X16R16I, -+ gcvSURF_G16R16I, -+ gcvSURF_X16R16UI, -+ gcvSURF_G16R16UI, -+ gcvSURF_X32R32I, -+ gcvSURF_G32R32I, -+ gcvSURF_X32R32UI, -+ gcvSURF_G32R32UI, -+ gcvSURF_X8G8R8I, -+ gcvSURF_B8G8R8I, -+ gcvSURF_X8G8R8UI, -+ gcvSURF_B8G8R8UI, -+ gcvSURF_X16G16R16I, -+ gcvSURF_B16G16R16I, -+ gcvSURF_X16G16R16UI, -+ gcvSURF_B16G16R16UI, -+ gcvSURF_X32G32R32I, -+ gcvSURF_B32G32R32I, -+ gcvSURF_X32G32R32UI, -+ gcvSURF_B32G32R32UI, -+ gcvSURF_X8B8G8R8I, -+ gcvSURF_A8B8G8R8I, -+ gcvSURF_X8B8G8R8UI, -+ gcvSURF_A8B8G8R8UI, -+ gcvSURF_X16B16G16R16I, -+ gcvSURF_A16B16G16R16I, -+ gcvSURF_X16B16G16R16UI, -+ gcvSURF_A16B16G16R16UI, -+ gcvSURF_X32B32G32R32I, -+ gcvSURF_A32B32G32R32I, -+ gcvSURF_X32B32G32R32UI, -+ gcvSURF_A32B32G32R32UI, -+ gcvSURF_A2B10G10R10UI, -+ gcvSURF_G32R32I_2_A8R8G8B8, -+ gcvSURF_G32R32UI_2_A8R8G8B8, -+ gcvSURF_X16B16G16R16I_2_A8R8G8B8, -+ gcvSURF_A16B16G16R16I_2_A8R8G8B8, -+ gcvSURF_X16B16G16R16UI_2_A8R8G8B8, -+ gcvSURF_A16B16G16R16UI_2_A8R8G8B8, -+ gcvSURF_X32B32G32R32I_2_G32R32I, -+ gcvSURF_A32B32G32R32I_2_G32R32I, -+ gcvSURF_X32B32G32R32I_3_A8R8G8B8, -+ gcvSURF_A32B32G32R32I_4_A8R8G8B8, -+ gcvSURF_X32B32G32R32UI_2_G32R32UI, -+ gcvSURF_A32B32G32R32UI_2_G32R32UI, -+ gcvSURF_X32B32G32R32UI_3_A8R8G8B8, -+ gcvSURF_A32B32G32R32UI_4_A8R8G8B8, -+ gcvSURF_A2B10G10R10UI_1_A8R8G8B8, -+ gcvSURF_A8B8G8R8I_1_A8R8G8B8, -+ gcvSURF_A8B8G8R8UI_1_A8R8G8B8, -+ gcvSURF_R8I_1_A4R4G4B4, -+ gcvSURF_R8UI_1_A4R4G4B4, -+ gcvSURF_R16I_1_A4R4G4B4, -+ gcvSURF_R16UI_1_A4R4G4B4, -+ gcvSURF_R32I_1_A8R8G8B8, -+ gcvSURF_R32UI_1_A8R8G8B8, -+ gcvSURF_X8R8I_1_A4R4G4B4, -+ gcvSURF_X8R8UI_1_A4R4G4B4, -+ gcvSURF_G8R8I_1_A4R4G4B4, -+ gcvSURF_G8R8UI_1_A4R4G4B4, -+ gcvSURF_X16R16I_1_A4R4G4B4, -+ gcvSURF_X16R16UI_1_A4R4G4B4, -+ gcvSURF_G16R16I_1_A8R8G8B8, -+ gcvSURF_G16R16UI_1_A8R8G8B8, -+ gcvSURF_X32R32I_1_A8R8G8B8, -+ gcvSURF_X32R32UI_1_A8R8G8B8, -+ gcvSURF_X8G8R8I_1_A4R4G4B4, -+ gcvSURF_X8G8R8UI_1_A4R4G4B4, -+ gcvSURF_B8G8R8I_1_A8R8G8B8, -+ gcvSURF_B8G8R8UI_1_A8R8G8B8, -+ gcvSURF_B16G16R16I_2_A8R8G8B8, -+ gcvSURF_B16G16R16UI_2_A8R8G8B8, -+ gcvSURF_B32G32R32I_3_A8R8G8B8, -+ gcvSURF_B32G32R32UI_3_A8R8G8B8, -+ -+ /* ASTC formats. */ -+ gcvSURF_ASTC4x4 = 1600, -+ gcvSURF_ASTC5x4, -+ gcvSURF_ASTC5x5, -+ gcvSURF_ASTC6x5, -+ gcvSURF_ASTC6x6, -+ gcvSURF_ASTC8x5, -+ gcvSURF_ASTC8x6, -+ gcvSURF_ASTC8x8, -+ gcvSURF_ASTC10x5, -+ gcvSURF_ASTC10x6, -+ gcvSURF_ASTC10x8, -+ gcvSURF_ASTC10x10, -+ gcvSURF_ASTC12x10, -+ gcvSURF_ASTC12x12, -+ gcvSURF_ASTC4x4_SRGB, -+ gcvSURF_ASTC5x4_SRGB, -+ gcvSURF_ASTC5x5_SRGB, -+ gcvSURF_ASTC6x5_SRGB, -+ gcvSURF_ASTC6x6_SRGB, -+ gcvSURF_ASTC8x5_SRGB, -+ gcvSURF_ASTC8x6_SRGB, -+ gcvSURF_ASTC8x8_SRGB, -+ gcvSURF_ASTC10x5_SRGB, -+ gcvSURF_ASTC10x6_SRGB, -+ gcvSURF_ASTC10x8_SRGB, -+ gcvSURF_ASTC10x10_SRGB, -+ gcvSURF_ASTC12x10_SRGB, -+ gcvSURF_ASTC12x12_SRGB, -+ -+ gcvSURF_FORMAT_COUNT -+} -+gceSURF_FORMAT; -+ -+/* Format modifiers. */ -+typedef enum _gceSURF_FORMAT_MODE -+{ -+ gcvSURF_FORMAT_OCL = 0x80000000 -+} -+gceSURF_FORMAT_MODE; -+ -+/* Pixel swizzle modes. */ -+typedef enum _gceSURF_SWIZZLE -+{ -+ gcvSURF_NOSWIZZLE = 0, -+ gcvSURF_ARGB, -+ gcvSURF_ABGR, -+ gcvSURF_RGBA, -+ gcvSURF_BGRA -+} -+gceSURF_SWIZZLE; -+ -+/* Transparency modes. */ -+typedef enum _gceSURF_TRANSPARENCY -+{ -+ /* Valid only for PE 1.0 */ -+ gcvSURF_OPAQUE = 0, -+ gcvSURF_SOURCE_MATCH, -+ gcvSURF_SOURCE_MASK, -+ gcvSURF_PATTERN_MASK, -+} -+gceSURF_TRANSPARENCY; -+ -+/* Surface Alignment. */ -+typedef enum _gceSURF_ALIGNMENT -+{ -+ gcvSURF_FOUR = 0, -+ gcvSURF_SIXTEEN, -+ gcvSURF_SUPER_TILED, -+ gcvSURF_SPLIT_TILED, -+ gcvSURF_SPLIT_SUPER_TILED -+} -+gceSURF_ALIGNMENT; -+ -+/* Surface Addressing. */ -+typedef enum _gceSURF_ADDRESSING -+{ -+ gcvSURF_NO_STRIDE_TILED = 0, -+ gcvSURF_NO_STRIDE_LINEAR, -+ gcvSURF_STRIDE_TILED, -+ gcvSURF_STRIDE_LINEAR -+} -+gceSURF_ADDRESSING; -+ -+/* Transparency modes. */ -+typedef enum _gce2D_TRANSPARENCY -+{ -+ /* Valid only for PE 2.0 */ -+ gcv2D_OPAQUE = 0, -+ gcv2D_KEYED, -+ gcv2D_MASKED -+} -+gce2D_TRANSPARENCY; -+ -+/* Mono packing modes. */ -+typedef enum _gceSURF_MONOPACK -+{ -+ gcvSURF_PACKED8 = 0, -+ gcvSURF_PACKED16, -+ gcvSURF_PACKED32, -+ gcvSURF_UNPACKED, -+} -+gceSURF_MONOPACK; -+ -+/* Blending modes. */ -+typedef enum _gceSURF_BLEND_MODE -+{ -+ /* Porter-Duff blending modes. */ -+ /* Fsrc Fdst */ -+ gcvBLEND_CLEAR = 0, /* 0 0 */ -+ gcvBLEND_SRC, /* 1 0 */ -+ gcvBLEND_DST, /* 0 1 */ -+ gcvBLEND_SRC_OVER_DST, /* 1 1 - Asrc */ -+ gcvBLEND_DST_OVER_SRC, /* 1 - Adst 1 */ -+ gcvBLEND_SRC_IN_DST, /* Adst 0 */ -+ gcvBLEND_DST_IN_SRC, /* 0 Asrc */ -+ gcvBLEND_SRC_OUT_DST, /* 1 - Adst 0 */ -+ gcvBLEND_DST_OUT_SRC, /* 0 1 - Asrc */ -+ gcvBLEND_SRC_ATOP_DST, /* Adst 1 - Asrc */ -+ gcvBLEND_DST_ATOP_SRC, /* 1 - Adst Asrc */ -+ gcvBLEND_SRC_XOR_DST, /* 1 - Adst 1 - Asrc */ -+ -+ /* Special blending modes. */ -+ gcvBLEND_SET, /* DST = 1 */ -+ gcvBLEND_SUB /* DST = DST * (1 - SRC) */ -+} -+gceSURF_BLEND_MODE; -+ -+/* Per-pixel alpha modes. */ -+typedef enum _gceSURF_PIXEL_ALPHA_MODE -+{ -+ gcvSURF_PIXEL_ALPHA_STRAIGHT = 0, -+ gcvSURF_PIXEL_ALPHA_INVERSED -+} -+gceSURF_PIXEL_ALPHA_MODE; -+ -+/* Global alpha modes. */ -+typedef enum _gceSURF_GLOBAL_ALPHA_MODE -+{ -+ gcvSURF_GLOBAL_ALPHA_OFF = 0, -+ gcvSURF_GLOBAL_ALPHA_ON, -+ gcvSURF_GLOBAL_ALPHA_SCALE -+} -+gceSURF_GLOBAL_ALPHA_MODE; -+ -+/* Color component modes for alpha blending. */ -+typedef enum _gceSURF_PIXEL_COLOR_MODE -+{ -+ gcvSURF_COLOR_STRAIGHT = 0, -+ gcvSURF_COLOR_MULTIPLY -+} -+gceSURF_PIXEL_COLOR_MODE; -+ -+/* Color component modes for alpha blending. */ -+typedef enum _gce2D_PIXEL_COLOR_MULTIPLY_MODE -+{ -+ gcv2D_COLOR_MULTIPLY_DISABLE = 0, -+ gcv2D_COLOR_MULTIPLY_ENABLE -+} -+gce2D_PIXEL_COLOR_MULTIPLY_MODE; -+ -+/* Color component modes for alpha blending. */ -+typedef enum _gce2D_GLOBAL_COLOR_MULTIPLY_MODE -+{ -+ gcv2D_GLOBAL_COLOR_MULTIPLY_DISABLE = 0, -+ gcv2D_GLOBAL_COLOR_MULTIPLY_ALPHA, -+ gcv2D_GLOBAL_COLOR_MULTIPLY_COLOR -+} -+gce2D_GLOBAL_COLOR_MULTIPLY_MODE; -+ -+/* Alpha blending factor modes. */ -+typedef enum _gceSURF_BLEND_FACTOR_MODE -+{ -+ gcvSURF_BLEND_ZERO = 0, -+ gcvSURF_BLEND_ONE, -+ gcvSURF_BLEND_STRAIGHT, -+ gcvSURF_BLEND_INVERSED, -+ gcvSURF_BLEND_COLOR, -+ gcvSURF_BLEND_COLOR_INVERSED, -+ gcvSURF_BLEND_SRC_ALPHA_SATURATED, -+ gcvSURF_BLEND_STRAIGHT_NO_CROSS, -+ gcvSURF_BLEND_INVERSED_NO_CROSS, -+ gcvSURF_BLEND_COLOR_NO_CROSS, -+ gcvSURF_BLEND_COLOR_INVERSED_NO_CROSS, -+ gcvSURF_BLEND_SRC_ALPHA_SATURATED_CROSS -+} -+gceSURF_BLEND_FACTOR_MODE; -+ -+/* Alpha blending porter duff rules. */ -+typedef enum _gce2D_PORTER_DUFF_RULE -+{ -+ gcvPD_CLEAR = 0, -+ gcvPD_SRC, -+ gcvPD_SRC_OVER, -+ gcvPD_DST_OVER, -+ gcvPD_SRC_IN, -+ gcvPD_DST_IN, -+ gcvPD_SRC_OUT, -+ gcvPD_DST_OUT, -+ gcvPD_SRC_ATOP, -+ gcvPD_DST_ATOP, -+ gcvPD_ADD, -+ gcvPD_XOR, -+ gcvPD_DST -+} -+gce2D_PORTER_DUFF_RULE; -+ -+/* Alpha blending factor modes. */ -+typedef enum _gce2D_YUV_COLOR_MODE -+{ -+ gcv2D_YUV_601= 0, -+ gcv2D_YUV_709, -+ gcv2D_YUV_USER_DEFINED, -+ gcv2D_YUV_USER_DEFINED_CLAMP, -+ -+ /* Default setting is for src. gcv2D_YUV_DST -+ can be ORed to set dst. -+ */ -+ gcv2D_YUV_DST = 0x80000000, -+} -+gce2D_YUV_COLOR_MODE; -+ -+typedef enum _gce2D_COMMAND -+{ -+ gcv2D_CLEAR = 0, -+ gcv2D_LINE, -+ gcv2D_BLT, -+ gcv2D_STRETCH, -+ gcv2D_HOR_FILTER, -+ gcv2D_VER_FILTER, -+ gcv2D_MULTI_SOURCE_BLT, -+ gcv2D_FILTER_BLT, -+} -+gce2D_COMMAND; -+ -+typedef enum _gce2D_TILE_STATUS_CONFIG -+{ -+ gcv2D_TSC_DISABLE = 0, -+ gcv2D_TSC_ENABLE = 0x00000001, -+ gcv2D_TSC_COMPRESSED = 0x00000002, -+ gcv2D_TSC_DOWN_SAMPLER = 0x00000004, -+ gcv2D_TSC_2D_COMPRESSED = 0x00000008, -+ gcv2D_TSC_TPC_COMPRESSED = 0x00000010, -+} -+gce2D_TILE_STATUS_CONFIG; -+ -+typedef enum _gce2D_QUERY -+{ -+ gcv2D_QUERY_RGB_ADDRESS_MIN_ALIGN = 0, -+ gcv2D_QUERY_RGB_STRIDE_MIN_ALIGN, -+ gcv2D_QUERY_YUV_ADDRESS_MIN_ALIGN, -+ gcv2D_QUERY_YUV_STRIDE_MIN_ALIGN, -+} -+gce2D_QUERY; -+ -+typedef enum _gce2D_SUPER_TILE_VERSION -+{ -+ gcv2D_SUPER_TILE_VERSION_V1 = 1, -+ gcv2D_SUPER_TILE_VERSION_V2 = 2, -+ gcv2D_SUPER_TILE_VERSION_V3 = 3, -+} -+gce2D_SUPER_TILE_VERSION; -+ -+typedef enum _gce2D_STATE -+{ -+ gcv2D_STATE_SPECIAL_FILTER_MIRROR_MODE = 1, -+ gcv2D_STATE_SUPER_TILE_VERSION, -+ gcv2D_STATE_EN_GAMMA, -+ gcv2D_STATE_DE_GAMMA, -+ gcv2D_STATE_MULTI_SRC_BLIT_UNIFIED_DST_RECT, -+ gcv2D_STATE_PROFILE_ENABLE, -+ gcv2D_STATE_XRGB_ENABLE, -+ -+ gcv2D_STATE_ARRAY_EN_GAMMA = 0x10001, -+ gcv2D_STATE_ARRAY_DE_GAMMA, -+ gcv2D_STATE_ARRAY_CSC_YUV_TO_RGB, -+ gcv2D_STATE_ARRAY_CSC_RGB_TO_YUV, -+} -+gce2D_STATE; -+ -+typedef enum _gce2D_STATE_PROFILE -+{ -+ gcv2D_STATE_PROFILE_NONE = 0x0, -+ gcv2D_STATE_PROFILE_COMMAND = 0x1, -+ gcv2D_STATE_PROFILE_SURFACE = 0x2, -+ gcv2D_STATE_PROFILE_ALL = 0xFFFF, -+} -+gce2D_STATE_PROFILE; -+ -+/* Texture object types */ -+typedef enum _gceTEXTURE_TYPE -+{ -+ gcvTEXTURE_UNKNOWN = 0, -+ gcvTEXTURE_1D, -+ gcvTEXTURE_2D, -+ gcvTEXTURE_3D, -+ gcvTEXTURE_CUBEMAP, -+ gcvTEXTURE_1D_ARRAY, -+ gcvTEXTURE_2D_ARRAY, -+ gcvTEXTURE_EXTERNAL -+} -+gceTEXTURE_TYPE; -+ -+#if gcdENABLE_3D -+/* Texture functions. */ -+typedef enum _gceTEXTURE_FUNCTION -+{ -+ gcvTEXTURE_DUMMY = 0, -+ gcvTEXTURE_REPLACE = 0, -+ gcvTEXTURE_MODULATE, -+ gcvTEXTURE_ADD, -+ gcvTEXTURE_ADD_SIGNED, -+ gcvTEXTURE_INTERPOLATE, -+ gcvTEXTURE_SUBTRACT, -+ gcvTEXTURE_DOT3 -+} -+gceTEXTURE_FUNCTION; -+ -+/* Texture sources. */ -+typedef enum _gceTEXTURE_SOURCE -+{ -+ gcvCOLOR_FROM_TEXTURE = 0, -+ gcvCOLOR_FROM_CONSTANT_COLOR, -+ gcvCOLOR_FROM_PRIMARY_COLOR, -+ gcvCOLOR_FROM_PREVIOUS_COLOR -+} -+gceTEXTURE_SOURCE; -+ -+/* Texture source channels. */ -+typedef enum _gceTEXTURE_CHANNEL -+{ -+ gcvFROM_COLOR = 0, -+ gcvFROM_ONE_MINUS_COLOR, -+ gcvFROM_ALPHA, -+ gcvFROM_ONE_MINUS_ALPHA -+} -+gceTEXTURE_CHANNEL; -+#endif /* gcdENABLE_3D */ -+ -+/* Filter types. */ -+typedef enum _gceFILTER_TYPE -+{ -+ gcvFILTER_SYNC = 0, -+ gcvFILTER_BLUR, -+ gcvFILTER_USER -+} -+gceFILTER_TYPE; -+ -+/* Filter pass types. */ -+typedef enum _gceFILTER_PASS_TYPE -+{ -+ gcvFILTER_HOR_PASS = 0, -+ gcvFILTER_VER_PASS -+} -+gceFILTER_PASS_TYPE; -+ -+/* Endian hints. */ -+typedef enum _gceENDIAN_HINT -+{ -+ gcvENDIAN_NO_SWAP = 0, -+ gcvENDIAN_SWAP_WORD, -+ gcvENDIAN_SWAP_DWORD -+} -+gceENDIAN_HINT; -+ -+/* Tiling modes. */ -+typedef enum _gceTILING -+{ -+ gcvINVALIDTILED = 0x0, /* Invalid tiling */ -+ /* Tiling basic modes enum'ed in power of 2. */ -+ gcvLINEAR = 0x1, /* No tiling. */ -+ gcvTILED = 0x2, /* 4x4 tiling. */ -+ gcvSUPERTILED = 0x4, /* 64x64 tiling. */ -+ gcvMINORTILED = 0x8, /* 2x2 tiling. */ -+ -+ /* Tiling special layouts. */ -+ gcvTILING_SPLIT_BUFFER = 0x100, -+ -+ /* Tiling combination layouts. */ -+ gcvMULTI_TILED = gcvTILED -+ | gcvTILING_SPLIT_BUFFER, -+ -+ gcvMULTI_SUPERTILED = gcvSUPERTILED -+ | gcvTILING_SPLIT_BUFFER, -+} -+gceTILING; -+ -+/* 2D pattern type. */ -+typedef enum _gce2D_PATTERN -+{ -+ gcv2D_PATTERN_SOLID = 0, -+ gcv2D_PATTERN_MONO, -+ gcv2D_PATTERN_COLOR, -+ gcv2D_PATTERN_INVALID -+} -+gce2D_PATTERN; -+ -+/* 2D source type. */ -+typedef enum _gce2D_SOURCE -+{ -+ gcv2D_SOURCE_MASKED = 0, -+ gcv2D_SOURCE_MONO, -+ gcv2D_SOURCE_COLOR, -+ gcv2D_SOURCE_INVALID -+} -+gce2D_SOURCE; -+ -+/* Pipes. */ -+typedef enum _gcePIPE_SELECT -+{ -+ gcvPIPE_INVALID = ~0, -+ gcvPIPE_3D = 0, -+ gcvPIPE_2D -+} -+gcePIPE_SELECT; -+ -+/* Hardware type. */ -+typedef enum _gceHARDWARE_TYPE -+{ -+ gcvHARDWARE_INVALID = 0x00, -+ gcvHARDWARE_3D = 0x01, -+ gcvHARDWARE_2D = 0x02, -+ gcvHARDWARE_VG = 0x04, -+ gcvHARDWARE_3D2D = gcvHARDWARE_3D | gcvHARDWARE_2D -+} -+gceHARDWARE_TYPE; -+ -+#define gcdCHIP_COUNT 3 -+ -+typedef enum _gceMMU_MODE -+{ -+ gcvMMU_MODE_1K, -+ gcvMMU_MODE_4K, -+} gceMMU_MODE; -+ -+/* User signal command codes. */ -+typedef enum _gceUSER_SIGNAL_COMMAND_CODES -+{ -+ gcvUSER_SIGNAL_CREATE, -+ gcvUSER_SIGNAL_DESTROY, -+ gcvUSER_SIGNAL_SIGNAL, -+ gcvUSER_SIGNAL_WAIT, -+ gcvUSER_SIGNAL_MAP, -+ gcvUSER_SIGNAL_UNMAP, -+} -+gceUSER_SIGNAL_COMMAND_CODES; -+ -+/* Sync point command codes. */ -+typedef enum _gceSYNC_POINT_COMMAND_CODES -+{ -+ gcvSYNC_POINT_CREATE, -+ gcvSYNC_POINT_DESTROY, -+ gcvSYNC_POINT_SIGNAL, -+} -+gceSYNC_POINT_COMMAND_CODES; -+ -+/* Shared buffer command codes. */ -+typedef enum _gceSHBUF_COMMAND_CODES -+{ -+ gcvSHBUF_CREATE, -+ gcvSHBUF_DESTROY, -+ gcvSHBUF_MAP, -+ gcvSHBUF_WRITE, -+ gcvSHBUF_READ, -+} -+gceSHBUF_COMMAND_CODES; -+ -+/* Event locations. */ -+typedef enum _gceKERNEL_WHERE -+{ -+ gcvKERNEL_COMMAND, -+ gcvKERNEL_VERTEX, -+ gcvKERNEL_TRIANGLE, -+ gcvKERNEL_TEXTURE, -+ gcvKERNEL_PIXEL, -+} -+gceKERNEL_WHERE; -+ -+#if gcdENABLE_VG -+/* Hardware blocks. */ -+typedef enum _gceBLOCK -+{ -+ gcvBLOCK_COMMAND, -+ gcvBLOCK_TESSELLATOR, -+ gcvBLOCK_TESSELLATOR2, -+ gcvBLOCK_TESSELLATOR3, -+ gcvBLOCK_RASTER, -+ gcvBLOCK_VG, -+ gcvBLOCK_VG2, -+ gcvBLOCK_VG3, -+ gcvBLOCK_PIXEL, -+ -+ /* Number of defined blocks. */ -+ gcvBLOCK_COUNT -+} -+gceBLOCK; -+#endif -+ -+/* gcdDUMP message type. */ -+typedef enum _gceDEBUG_MESSAGE_TYPE -+{ -+ gcvMESSAGE_TEXT, -+ gcvMESSAGE_DUMP -+} -+gceDEBUG_MESSAGE_TYPE; -+ -+/* Shading format. */ -+typedef enum _gceSHADING -+{ -+ gcvSHADING_SMOOTH, -+ gcvSHADING_FLAT_D3D, -+ gcvSHADING_FLAT_OPENGL, -+} -+gceSHADING; -+ -+/* Culling modes. */ -+typedef enum _gceCULL -+{ -+ gcvCULL_NONE, -+ gcvCULL_CCW, -+ gcvCULL_CW, -+} -+gceCULL; -+ -+/* Fill modes. */ -+typedef enum _gceFILL -+{ -+ gcvFILL_POINT, -+ gcvFILL_WIRE_FRAME, -+ gcvFILL_SOLID, -+} -+gceFILL; -+ -+/* Compare modes. */ -+typedef enum _gceCOMPARE -+{ -+ gcvCOMPARE_INVALID = 0, -+ gcvCOMPARE_NEVER, -+ gcvCOMPARE_NOT_EQUAL, -+ gcvCOMPARE_LESS, -+ gcvCOMPARE_LESS_OR_EQUAL, -+ gcvCOMPARE_EQUAL, -+ gcvCOMPARE_GREATER, -+ gcvCOMPARE_GREATER_OR_EQUAL, -+ gcvCOMPARE_ALWAYS, -+} -+gceCOMPARE; -+ -+/* Stencil modes. */ -+typedef enum _gceSTENCIL_MODE -+{ -+ gcvSTENCIL_NONE, -+ gcvSTENCIL_SINGLE_SIDED, -+ gcvSTENCIL_DOUBLE_SIDED, -+} -+gceSTENCIL_MODE; -+ -+/* Stencil operations. */ -+typedef enum _gceSTENCIL_OPERATION -+{ -+ gcvSTENCIL_KEEP, -+ gcvSTENCIL_REPLACE, -+ gcvSTENCIL_ZERO, -+ gcvSTENCIL_INVERT, -+ gcvSTENCIL_INCREMENT, -+ gcvSTENCIL_DECREMENT, -+ gcvSTENCIL_INCREMENT_SATURATE, -+ gcvSTENCIL_DECREMENT_SATURATE, -+ gcvSTENCIL_OPERATION_INVALID = -1 -+} -+gceSTENCIL_OPERATION; -+ -+/* Stencil selection. */ -+typedef enum _gceSTENCIL_WHERE -+{ -+ gcvSTENCIL_FRONT, -+ gcvSTENCIL_BACK, -+} -+gceSTENCIL_WHERE; -+ -+/* Texture addressing selection. */ -+typedef enum _gceTEXTURE_WHICH -+{ -+ gcvTEXTURE_S, -+ gcvTEXTURE_T, -+ gcvTEXTURE_R, -+} -+gceTEXTURE_WHICH; -+ -+/* Texture addressing modes. */ -+typedef enum _gceTEXTURE_ADDRESSING -+{ -+ gcvTEXTURE_INVALID = 0, -+ gcvTEXTURE_CLAMP, -+ gcvTEXTURE_WRAP, -+ gcvTEXTURE_MIRROR, -+ gcvTEXTURE_BORDER, -+ gcvTEXTURE_MIRROR_ONCE, -+} -+gceTEXTURE_ADDRESSING; -+ -+/* Texture filters. */ -+typedef enum _gceTEXTURE_FILTER -+{ -+ gcvTEXTURE_NONE, -+ gcvTEXTURE_POINT, -+ gcvTEXTURE_LINEAR, -+ gcvTEXTURE_ANISOTROPIC, -+} -+gceTEXTURE_FILTER; -+ -+typedef enum _gceTEXTURE_COMPONENT -+{ -+ gcvTEXTURE_COMPONENT_R, -+ gcvTEXTURE_COMPONENT_G, -+ gcvTEXTURE_COMPONENT_B, -+ gcvTEXTURE_COMPONENT_A, -+ -+ gcvTEXTURE_COMPONENT_NUM, -+} gceTEXTURE_COMPONENT; -+ -+/* Texture swizzle modes. */ -+typedef enum _gceTEXTURE_SWIZZLE -+{ -+ gcvTEXTURE_SWIZZLE_R = 0, -+ gcvTEXTURE_SWIZZLE_G, -+ gcvTEXTURE_SWIZZLE_B, -+ gcvTEXTURE_SWIZZLE_A, -+ gcvTEXTURE_SWIZZLE_0, -+ gcvTEXTURE_SWIZZLE_1, -+ -+ gcvTEXTURE_SWIZZLE_INVALID, -+} gceTEXTURE_SWIZZLE; -+ -+typedef enum _gceTEXTURE_COMPARE_MODE -+{ -+ gcvTEXTURE_COMPARE_MODE_INVALID = 0, -+ gcvTEXTURE_COMPARE_MODE_NONE, -+ gcvTEXTURE_COMPARE_MODE_REF, -+} gceTEXTURE_COMPARE_MODE; -+ -+/* Pixel output swizzle modes. */ -+typedef enum _gcePIXEL_SWIZZLE -+{ -+ gcvPIXEL_SWIZZLE_R = gcvTEXTURE_SWIZZLE_R, -+ gcvPIXEL_SWIZZLE_G = gcvTEXTURE_SWIZZLE_G, -+ gcvPIXEL_SWIZZLE_B = gcvTEXTURE_SWIZZLE_B, -+ gcvPIXEL_SWIZZLE_A = gcvTEXTURE_SWIZZLE_A, -+ -+ gcvPIXEL_SWIZZLE_INVALID, -+} gcePIXEL_SWIZZLE; -+ -+/* Primitive types. */ -+typedef enum _gcePRIMITIVE -+{ -+ gcvPRIMITIVE_POINT_LIST, -+ gcvPRIMITIVE_LINE_LIST, -+ gcvPRIMITIVE_LINE_STRIP, -+ gcvPRIMITIVE_LINE_LOOP, -+ gcvPRIMITIVE_TRIANGLE_LIST, -+ gcvPRIMITIVE_TRIANGLE_STRIP, -+ gcvPRIMITIVE_TRIANGLE_FAN, -+ gcvPRIMITIVE_RECTANGLE, -+} -+gcePRIMITIVE; -+ -+/* Index types. */ -+typedef enum _gceINDEX_TYPE -+{ -+ gcvINDEX_8, -+ gcvINDEX_16, -+ gcvINDEX_32, -+} -+gceINDEX_TYPE; -+ -+/* Multi GPU rendering modes. */ -+typedef enum _gceMULTI_GPU_RENDERING_MODE -+{ -+ gcvMULTI_GPU_RENDERING_MODE_OFF, -+ gcvMULTI_GPU_RENDERING_MODE_SPLIT_WIDTH, -+ gcvMULTI_GPU_RENDERING_MODE_SPLIT_HEIGHT, -+ gcvMULTI_GPU_RENDERING_MODE_INTERLEAVED_64x64, -+ gcvMULTI_GPU_RENDERING_MODE_INTERLEAVED_128x64, -+ gcvMULTI_GPU_RENDERING_MODE_INTERLEAVED_128x128 -+} -+gceMULTI_GPU_RENDERING_MODE; -+ -+typedef enum _gceCORE_3D_MASK -+{ -+ gcvCORE_3D_0_MASK = (1 << 0), -+ gcvCORE_3D_1_MASK = (1 << 1), -+ -+ gcvCORE_3D_ALL_MASK = (0xFFFF) -+} -+gceCORE_3D_MASK; -+ -+typedef enum _gceCORE_3D_ID -+{ -+ gcvCORE_3D_0_ID = 0, -+ gcvCORE_3D_1_ID = 1, -+ -+ gcvCORE_3D_ID_INVALID = ~0UL -+} -+gceCORE_3D_ID; -+ -+typedef enum _gceMULTI_GPU_MODE -+{ -+ gcvMULTI_GPU_MODE_COMBINED = 0, -+ gcvMULTI_GPU_MODE_INDEPENDENT = 1 -+} -+gceMULTI_GPU_MODE; -+ -+typedef enum _gceMACHINECODE -+{ -+ gcvMACHINECODE_ANTUTU0 = 0x0, -+ -+ gcvMACHINECODE_GLB27_RELEASE_0, -+ -+ gcvMACHINECODE_GLB25_RELEASE_0, -+ gcvMACHINECODE_GLB25_RELEASE_1, -+ gcvMACHINECODE_GLB25_RELEASE_2, -+ -+ /* keep it as the last enum */ -+ gcvMACHINECODE_COUNT -+} -+gceMACHINECODE; -+ -+typedef enum _gceUNIFORMCVT -+{ -+ gcvUNIFORMCVT_NONE = 0, -+ gcvUNIFORMCVT_TO_BOOL, -+ gcvUNIFORMCVT_TO_FLOAT, -+} gceUNIFORMCVT; -+ -+typedef enum _gceHAL_ARG_VERSION -+{ -+ gcvHAL_ARG_VERSION_V1 = 0x0, -+} -+gceHAL_ARG_VERSION; -+ -+ -+/* -+* Bit of a requirment is 1 means requirement is a must, 0 means requirement can -+* be ignored. -+*/ -+#define gcvALLOC_FLAG_CONTIGUOUS_BIT 0 -+#define gcvALLOC_FLAG_CACHEABLE_BIT 1 -+#define gcvALLOC_FLAG_SECURITY_BIT 2 -+#define gcvALLOC_FLAG_NON_CONTIGUOUS_BIT 3 -+#define gcvALLOC_FLAG_MEMLIMIT_BIT 4 -+ -+/* No special needs. */ -+#define gcvALLOC_FLAG_NONE (0) -+/* Physical contiguous. */ -+#define gcvALLOC_FLAG_CONTIGUOUS (1 << gcvALLOC_FLAG_CONTIGUOUS_BIT) -+/* Can be remapped as cacheable. */ -+#define gcvALLOC_FLAG_CACHEABLE (1 << gcvALLOC_FLAG_CACHEABLE_BIT) -+/* Secure buffer. */ -+#define gcvALLOC_FLAG_SECURITY (1 << gcvALLOC_FLAG_SECURITY_BIT) -+/* Physical non contiguous. */ -+#define gcvALLOC_FLAG_NON_CONTIGUOUS (1 << gcvALLOC_FLAG_NON_CONTIGUOUS_BIT) -+#define gcvALLOC_FLAG_MEMLIMIT (1 << gcvALLOC_FLAG_MEMLIMIT_BIT) -+ -+/* GL_VIV internal usage */ -+#ifndef GL_MAP_BUFFER_OBJ_VIV -+#define GL_MAP_BUFFER_OBJ_VIV 0x10000 -+#endif -+ -+/* Command buffer usage. */ -+#define gcvCOMMAND_2D (1 << 0) -+#define gcvCOMMAND_3D (1 << 1) -+ -+/******************************************************************************\ -+****************************** Object Declarations ***************************** -+\******************************************************************************/ -+ -+typedef struct _gckCONTEXT * gckCONTEXT; -+typedef struct _gcoCMDBUF * gcoCMDBUF; -+ -+typedef struct _gcsSTATE_DELTA * gcsSTATE_DELTA_PTR; -+typedef struct _gcsQUEUE * gcsQUEUE_PTR; -+typedef struct _gcoQUEUE * gcoQUEUE; -+typedef struct _gcsHAL_INTERFACE * gcsHAL_INTERFACE_PTR; -+typedef struct _gcs2D_PROFILE * gcs2D_PROFILE_PTR; -+ -+#if gcdENABLE_VG -+typedef struct _gcoVGHARDWARE * gcoVGHARDWARE; -+typedef struct _gcoVGBUFFER * gcoVGBUFFER; -+typedef struct _gckVGHARDWARE * gckVGHARDWARE; -+typedef struct _gcsVGCONTEXT * gcsVGCONTEXT_PTR; -+typedef struct _gcsVGCONTEXT_MAP * gcsVGCONTEXT_MAP_PTR; -+typedef struct _gcsVGCMDQUEUE * gcsVGCMDQUEUE_PTR; -+typedef struct _gcsTASK_MASTER_TABLE * gcsTASK_MASTER_TABLE_PTR; -+typedef struct _gckVGKERNEL * gckVGKERNEL; -+typedef void * gctTHREAD; -+#endif -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* __gc_hal_enum_h_ */ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal.h linux-4.1.13/drivers/gpu/galcore/inc/gc_hal.h ---- linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/inc/gc_hal.h 2015-11-30 17:56:13.592136927 +0100 -@@ -0,0 +1,2677 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#ifndef __gc_hal_h_ -+#define __gc_hal_h_ -+ -+#include "gc_hal_rename.h" -+#include "gc_hal_types.h" -+#include "gc_hal_enum.h" -+#include "gc_hal_base.h" -+#include "gc_hal_profiler.h" -+#include "gc_hal_driver.h" -+#if gcdENABLE_3D -+#include "gc_hal_statistics.h" -+#endif -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+/******************************************************************************\ -+******************************* Alignment Macros ******************************* -+\******************************************************************************/ -+ -+/* Alignment with a non-power of two value. */ -+#define gcmALIGN_NP2(n, align) \ -+( \ -+ ((n) + (align) - 1) - (((n) + (align) - 1) % (align)) \ -+) -+ -+/* Alignment with a power of two value. */ -+#define gcmALIGN(n, align) \ -+( \ -+ ((n) + ((align) - 1)) & ~((align) - 1) \ -+) -+ -+#define gcmALIGN_BASE(n, align) \ -+( \ -+ ((n) & ~((align) - 1)) \ -+) -+ -+/******************************************************************************\ -+***************************** Element Count Macro ***************************** -+\******************************************************************************/ -+ -+#define gcmSIZEOF(a) \ -+( \ -+ (gctSIZE_T) (sizeof(a)) \ -+) -+ -+#define gcmCOUNTOF(a) \ -+( \ -+ sizeof(a) / sizeof(a[0]) \ -+) -+ -+/******************************************************************************\ -+********************************* Cast Macro ********************************** -+\******************************************************************************/ -+#define gcmNAME_TO_PTR(na) \ -+ gckKERNEL_QueryPointerFromName(kernel, gcmALL_TO_UINT32(na)) -+ -+#define gcmPTR_TO_NAME(ptr) \ -+ gckKERNEL_AllocateNameFromPointer(kernel, ptr) -+ -+#define gcmRELEASE_NAME(na) \ -+ gckKERNEL_DeleteName(kernel, gcmALL_TO_UINT32(na)) -+ -+#define gcmALL_TO_UINT32(t) \ -+( \ -+ (gctUINT32) (gctUINTPTR_T) (t)\ -+) -+ -+#define gcmPTR_TO_UINT64(p) \ -+( \ -+ (gctUINT64) (gctUINTPTR_T) (p)\ -+) -+ -+#define gcmUINT64_TO_PTR(u) \ -+( \ -+ (gctPOINTER) (gctUINTPTR_T) (u)\ -+) -+ -+#define gcmUINT64_TO_TYPE(u, t) \ -+( \ -+ (t) (gctUINTPTR_T) (u)\ -+) -+ -+/******************************************************************************\ -+******************************** Useful Macro ********************************* -+\******************************************************************************/ -+ -+#define gcvINVALID_ADDRESS ~0U -+ -+#define gcmGET_PRE_ROTATION(rotate) \ -+ ((rotate) & (~(gcvSURF_POST_FLIP_X | gcvSURF_POST_FLIP_Y))) -+ -+#define gcmGET_POST_ROTATION(rotate) \ -+ ((rotate) & (gcvSURF_POST_FLIP_X | gcvSURF_POST_FLIP_Y)) -+ -+/******************************************************************************\ -+******************************** gcsOBJECT Object ******************************* -+\******************************************************************************/ -+ -+/* Type of objects. */ -+typedef enum _gceOBJECT_TYPE -+{ -+ gcvOBJ_UNKNOWN = 0, -+ gcvOBJ_2D = gcmCC('2','D',' ',' '), -+ gcvOBJ_3D = gcmCC('3','D',' ',' '), -+ gcvOBJ_ATTRIBUTE = gcmCC('A','T','T','R'), -+ gcvOBJ_BRUSHCACHE = gcmCC('B','R','U','$'), -+ gcvOBJ_BRUSHNODE = gcmCC('B','R','U','n'), -+ gcvOBJ_BRUSH = gcmCC('B','R','U','o'), -+ gcvOBJ_BUFFER = gcmCC('B','U','F','R'), -+ gcvOBJ_COMMAND = gcmCC('C','M','D',' '), -+ gcvOBJ_COMMANDBUFFER = gcmCC('C','M','D','B'), -+ gcvOBJ_CONTEXT = gcmCC('C','T','X','T'), -+ gcvOBJ_DEVICE = gcmCC('D','E','V',' '), -+ gcvOBJ_DUMP = gcmCC('D','U','M','P'), -+ gcvOBJ_EVENT = gcmCC('E','V','N','T'), -+ gcvOBJ_FUNCTION = gcmCC('F','U','N','C'), -+ gcvOBJ_HAL = gcmCC('H','A','L',' '), -+ gcvOBJ_HARDWARE = gcmCC('H','A','R','D'), -+ gcvOBJ_HEAP = gcmCC('H','E','A','P'), -+ gcvOBJ_INDEX = gcmCC('I','N','D','X'), -+ gcvOBJ_INTERRUPT = gcmCC('I','N','T','R'), -+ gcvOBJ_KERNEL = gcmCC('K','E','R','N'), -+ gcvOBJ_KERNEL_FUNCTION = gcmCC('K','F','C','N'), -+ gcvOBJ_MEMORYBUFFER = gcmCC('M','E','M','B'), -+ gcvOBJ_MMU = gcmCC('M','M','U',' '), -+ gcvOBJ_OS = gcmCC('O','S',' ',' '), -+ gcvOBJ_OUTPUT = gcmCC('O','U','T','P'), -+ gcvOBJ_PAINT = gcmCC('P','N','T',' '), -+ gcvOBJ_PATH = gcmCC('P','A','T','H'), -+ gcvOBJ_QUEUE = gcmCC('Q','U','E',' '), -+ gcvOBJ_SAMPLER = gcmCC('S','A','M','P'), -+ gcvOBJ_SHADER = gcmCC('S','H','D','R'), -+ gcvOBJ_STREAM = gcmCC('S','T','R','M'), -+ gcvOBJ_SURF = gcmCC('S','U','R','F'), -+ gcvOBJ_TEXTURE = gcmCC('T','X','T','R'), -+ gcvOBJ_UNIFORM = gcmCC('U','N','I','F'), -+ gcvOBJ_VARIABLE = gcmCC('V','A','R','I'), -+ gcvOBJ_VERTEX = gcmCC('V','R','T','X'), -+ gcvOBJ_VIDMEM = gcmCC('V','M','E','M'), -+ gcvOBJ_VG = gcmCC('V','G',' ',' '), -+ gcvOBJ_BUFOBJ = gcmCC('B','U','F','O'), -+ gcvOBJ_UNIFORM_BLOCK = gcmCC('U','B','L','K'), -+ gcvOBJ_CL = gcmCC('C','L',' ',' '), -+} -+gceOBJECT_TYPE; -+ -+/* gcsOBJECT object defintinon. */ -+typedef struct _gcsOBJECT -+{ -+ /* Type of an object. */ -+ gceOBJECT_TYPE type; -+} -+gcsOBJECT; -+ -+typedef struct _gckHARDWARE * gckHARDWARE; -+ -+/* CORE flags. */ -+typedef enum _gceCORE -+{ -+ gcvCORE_MAJOR = 0x0, -+ gcvCORE_2D = 0x1, -+ gcvCORE_VG = 0x2, -+} -+gceCORE; -+ -+#define gcdMAX_GPU_COUNT 3 -+ -+#define gcdMAX_SURF_LAYER 4 -+ -+#define gcdMAX_DRAW_BUFFERS 4 -+ -+/******************************************************************************* -+** -+** gcmVERIFY_OBJECT -+** -+** Assert if an object is invalid or is not of the specified type. If the -+** object is invalid or not of the specified type, gcvSTATUS_INVALID_OBJECT -+** will be returned from the current function. In retail mode this macro -+** does nothing. -+** -+** ARGUMENTS: -+** -+** obj Object to test. -+** t Expected type of the object. -+*/ -+#if gcmIS_DEBUG(gcdDEBUG_TRACE) -+#define _gcmVERIFY_OBJECT(prefix, obj, t) \ -+ if ((obj) == gcvNULL) \ -+ { \ -+ prefix##TRACE(gcvLEVEL_ERROR, \ -+ #prefix "VERIFY_OBJECT failed: NULL"); \ -+ prefix##TRACE(gcvLEVEL_ERROR, " expected: %c%c%c%c", \ -+ gcmCC_PRINT(t)); \ -+ prefix##ASSERT((obj) != gcvNULL); \ -+ prefix##FOOTER_ARG("status=%d", gcvSTATUS_INVALID_OBJECT); \ -+ return gcvSTATUS_INVALID_OBJECT; \ -+ } \ -+ else if (((gcsOBJECT*) (obj))->type != t) \ -+ { \ -+ prefix##TRACE(gcvLEVEL_ERROR, \ -+ #prefix "VERIFY_OBJECT failed: %c%c%c%c", \ -+ gcmCC_PRINT(((gcsOBJECT*) (obj))->type)); \ -+ prefix##TRACE(gcvLEVEL_ERROR, " expected: %c%c%c%c", \ -+ gcmCC_PRINT(t)); \ -+ prefix##ASSERT(((gcsOBJECT*)(obj))->type == t); \ -+ prefix##FOOTER_ARG("status=%d", gcvSTATUS_INVALID_OBJECT); \ -+ return gcvSTATUS_INVALID_OBJECT; \ -+ } -+ -+# define gcmVERIFY_OBJECT(obj, t) _gcmVERIFY_OBJECT(gcm, obj, t) -+# define gcmkVERIFY_OBJECT(obj, t) _gcmVERIFY_OBJECT(gcmk, obj, t) -+#else -+# define gcmVERIFY_OBJECT(obj, t) do {} while (gcvFALSE) -+# define gcmkVERIFY_OBJECT(obj, t) do {} while (gcvFALSE) -+#endif -+ -+/******************************************************************************/ -+/*VERIFY_OBJECT if special return expected*/ -+/******************************************************************************/ -+#ifndef EGL_API_ANDROID -+# define _gcmVERIFY_OBJECT_RETURN(prefix, obj, t, retVal) \ -+ do \ -+ { \ -+ if ((obj) == gcvNULL) \ -+ { \ -+ prefix##PRINT_VERSION(); \ -+ prefix##TRACE(gcvLEVEL_ERROR, \ -+ #prefix "VERIFY_OBJECT_RETURN failed: NULL"); \ -+ prefix##TRACE(gcvLEVEL_ERROR, " expected: %c%c%c%c", \ -+ gcmCC_PRINT(t)); \ -+ prefix##ASSERT((obj) != gcvNULL); \ -+ prefix##FOOTER_ARG("retVal=%d", retVal); \ -+ return retVal; \ -+ } \ -+ else if (((gcsOBJECT*) (obj))->type != t) \ -+ { \ -+ prefix##PRINT_VERSION(); \ -+ prefix##TRACE(gcvLEVEL_ERROR, \ -+ #prefix "VERIFY_OBJECT_RETURN failed: %c%c%c%c", \ -+ gcmCC_PRINT(((gcsOBJECT*) (obj))->type)); \ -+ prefix##TRACE(gcvLEVEL_ERROR, " expected: %c%c%c%c", \ -+ gcmCC_PRINT(t)); \ -+ prefix##ASSERT(((gcsOBJECT*)(obj))->type == t); \ -+ prefix##FOOTER_ARG("retVal=%d", retVal); \ -+ return retVal; \ -+ } \ -+ } \ -+ while (gcvFALSE) -+# define gcmVERIFY_OBJECT_RETURN(obj, t, retVal) \ -+ _gcmVERIFY_OBJECT_RETURN(gcm, obj, t, retVal) -+# define gcmkVERIFY_OBJECT_RETURN(obj, t, retVal) \ -+ _gcmVERIFY_OBJECT_RETURN(gcmk, obj, t, retVal) -+#else -+# define gcmVERIFY_OBJECT_RETURN(obj, t) do {} while (gcvFALSE) -+# define gcmVERIFY_OBJECT_RETURN(obj, t) do {} while (gcvFALSE) -+#endif -+ -+/******************************************************************************\ -+********************************** gckOS Object ********************************* -+\******************************************************************************/ -+ -+/* Construct a new gckOS object. */ -+gceSTATUS -+gckOS_Construct( -+ IN gctPOINTER Context, -+ OUT gckOS * Os -+ ); -+ -+/* Destroy an gckOS object. */ -+gceSTATUS -+gckOS_Destroy( -+ IN gckOS Os -+ ); -+ -+/* Query the video memory. */ -+gceSTATUS -+gckOS_QueryVideoMemory( -+ IN gckOS Os, -+ OUT gctPHYS_ADDR * InternalAddress, -+ OUT gctSIZE_T * InternalSize, -+ OUT gctPHYS_ADDR * ExternalAddress, -+ OUT gctSIZE_T * ExternalSize, -+ OUT gctPHYS_ADDR * ContiguousAddress, -+ OUT gctSIZE_T * ContiguousSize -+ ); -+ -+/* Allocate memory from the heap. */ -+gceSTATUS -+gckOS_Allocate( -+ IN gckOS Os, -+ IN gctSIZE_T Bytes, -+ OUT gctPOINTER * Memory -+ ); -+ -+/* Free allocated memory. */ -+gceSTATUS -+gckOS_Free( -+ IN gckOS Os, -+ IN gctPOINTER Memory -+ ); -+ -+/* Wrapper for allocation memory.. */ -+gceSTATUS -+gckOS_AllocateMemory( -+ IN gckOS Os, -+ IN gctSIZE_T Bytes, -+ OUT gctPOINTER * Memory -+ ); -+ -+/* Wrapper for freeing memory. */ -+gceSTATUS -+gckOS_FreeMemory( -+ IN gckOS Os, -+ IN gctPOINTER Memory -+ ); -+ -+/* Allocate paged memory. */ -+gceSTATUS -+gckOS_AllocatePagedMemory( -+ IN gckOS Os, -+ IN gctSIZE_T Bytes, -+ OUT gctPHYS_ADDR * Physical -+ ); -+ -+/* Allocate paged memory. */ -+gceSTATUS -+gckOS_AllocatePagedMemoryEx( -+ IN gckOS Os, -+ IN gctUINT32 Flag, -+ IN gctSIZE_T Bytes, -+ OUT gctUINT32 * Gid, -+ OUT gctPHYS_ADDR * Physical -+ ); -+ -+/* Lock pages. */ -+gceSTATUS -+gckOS_LockPages( -+ IN gckOS Os, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T Bytes, -+ IN gctBOOL Cacheable, -+ OUT gctPOINTER * Logical, -+ OUT gctSIZE_T * PageCount -+ ); -+ -+/* Map pages. */ -+gceSTATUS -+gckOS_MapPages( -+ IN gckOS Os, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T PageCount, -+ IN gctPOINTER PageTable -+ ); -+ -+/* Map pages. */ -+gceSTATUS -+gckOS_MapPagesEx( -+ IN gckOS Os, -+ IN gceCORE Core, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T PageCount, -+ IN gctUINT32 Address, -+ IN gctPOINTER PageTable -+ ); -+ -+gceSTATUS -+gckOS_UnmapPages( -+ IN gckOS Os, -+ IN gctSIZE_T PageCount, -+ IN gctUINT32 Address -+ ); -+ -+/* Unlock pages. */ -+gceSTATUS -+gckOS_UnlockPages( -+ IN gckOS Os, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T Bytes, -+ IN gctPOINTER Logical -+ ); -+ -+/* Free paged memory. */ -+gceSTATUS -+gckOS_FreePagedMemory( -+ IN gckOS Os, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T Bytes -+ ); -+ -+/* Allocate non-paged memory. */ -+gceSTATUS -+gckOS_AllocateNonPagedMemory( -+ IN gckOS Os, -+ IN gctBOOL InUserSpace, -+ IN OUT gctSIZE_T * Bytes, -+ OUT gctPHYS_ADDR * Physical, -+ OUT gctPOINTER * Logical -+ ); -+ -+/* Free non-paged memory. */ -+gceSTATUS -+gckOS_FreeNonPagedMemory( -+ IN gckOS Os, -+ IN gctSIZE_T Bytes, -+ IN gctPHYS_ADDR Physical, -+ IN gctPOINTER Logical -+ ); -+ -+/* Allocate contiguous memory. */ -+gceSTATUS -+gckOS_AllocateContiguous( -+ IN gckOS Os, -+ IN gctBOOL InUserSpace, -+ IN OUT gctSIZE_T * Bytes, -+ OUT gctPHYS_ADDR * Physical, -+ OUT gctPOINTER * Logical -+ ); -+ -+/* Free contiguous memory. */ -+gceSTATUS -+gckOS_FreeContiguous( -+ IN gckOS Os, -+ IN gctPHYS_ADDR Physical, -+ IN gctPOINTER Logical, -+ IN gctSIZE_T Bytes -+ ); -+ -+/* Get the number fo bytes per page. */ -+gceSTATUS -+gckOS_GetPageSize( -+ IN gckOS Os, -+ OUT gctSIZE_T * PageSize -+ ); -+ -+/* Get the physical address of a corresponding logical address. */ -+gceSTATUS -+gckOS_GetPhysicalAddress( -+ IN gckOS Os, -+ IN gctPOINTER Logical, -+ OUT gctUINT32 * Address -+ ); -+ -+/* Get the physical address of a corresponding user logical address. */ -+gceSTATUS -+gckOS_UserLogicalToPhysical( -+ IN gckOS Os, -+ IN gctPOINTER Logical, -+ OUT gctUINT32 * Address -+ ); -+ -+/* Get the physical address of a corresponding logical address. */ -+gceSTATUS -+gckOS_GetPhysicalAddressProcess( -+ IN gckOS Os, -+ IN gctPOINTER Logical, -+ IN gctUINT32 ProcessID, -+ OUT gctUINT32 * Address -+ ); -+ -+/* Map physical memory. */ -+gceSTATUS -+gckOS_MapPhysical( -+ IN gckOS Os, -+ IN gctUINT32 Physical, -+ IN gctSIZE_T Bytes, -+ OUT gctPOINTER * Logical -+ ); -+ -+/* Unmap previously mapped physical memory. */ -+gceSTATUS -+gckOS_UnmapPhysical( -+ IN gckOS Os, -+ IN gctPOINTER Logical, -+ IN gctSIZE_T Bytes -+ ); -+ -+/* Get real physical address from descriptor. */ -+gceSTATUS -+gckOS_PhysicalToPhysicalAddress( -+ IN gckOS Os, -+ IN gctPOINTER Physical, -+ OUT gctUINT32 * PhysicalAddress -+ ); -+ -+/* Read data from a hardware register. */ -+gceSTATUS -+gckOS_ReadRegister( -+ IN gckOS Os, -+ IN gctUINT32 Address, -+ OUT gctUINT32 * Data -+ ); -+ -+/* Read data from a hardware register. */ -+gceSTATUS -+gckOS_ReadRegisterEx( -+ IN gckOS Os, -+ IN gceCORE Core, -+ IN gctUINT32 Address, -+ OUT gctUINT32 * Data -+ ); -+ -+/* Write data to a hardware register. */ -+gceSTATUS -+gckOS_WriteRegister( -+ IN gckOS Os, -+ IN gctUINT32 Address, -+ IN gctUINT32 Data -+ ); -+ -+/* Write data to a hardware register. */ -+gceSTATUS -+gckOS_WriteRegisterEx( -+ IN gckOS Os, -+ IN gceCORE Core, -+ IN gctUINT32 Address, -+ IN gctUINT32 Data -+ ); -+ -+/* Write data to a 32-bit memory location. */ -+gceSTATUS -+gckOS_WriteMemory( -+ IN gckOS Os, -+ IN gctPOINTER Address, -+ IN gctUINT32 Data -+ ); -+ -+/* Map physical memory into the process space. */ -+gceSTATUS -+gckOS_MapMemory( -+ IN gckOS Os, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T Bytes, -+ OUT gctPOINTER * Logical -+ ); -+ -+/* Unmap physical memory from the specified process space. */ -+gceSTATUS -+gckOS_UnmapMemoryEx( -+ IN gckOS Os, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T Bytes, -+ IN gctPOINTER Logical, -+ IN gctUINT32 PID -+ ); -+ -+/* Unmap physical memory from the process space. */ -+gceSTATUS -+gckOS_UnmapMemory( -+ IN gckOS Os, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T Bytes, -+ IN gctPOINTER Logical -+ ); -+ -+/* Unmap user logical memory out of physical memory. -+ * This function is only supported in Linux currently. -+ */ -+gceSTATUS -+gckOS_UnmapUserLogical( -+ IN gckOS Os, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T Bytes, -+ IN gctPOINTER Logical -+ ); -+ -+/* Create a new mutex. */ -+gceSTATUS -+gckOS_CreateMutex( -+ IN gckOS Os, -+ OUT gctPOINTER * Mutex -+ ); -+ -+/* Delete a mutex. */ -+gceSTATUS -+gckOS_DeleteMutex( -+ IN gckOS Os, -+ IN gctPOINTER Mutex -+ ); -+ -+/* Acquire a mutex. */ -+gceSTATUS -+gckOS_AcquireMutex( -+ IN gckOS Os, -+ IN gctPOINTER Mutex, -+ IN gctUINT32 Timeout -+ ); -+ -+/* Release a mutex. */ -+gceSTATUS -+gckOS_ReleaseMutex( -+ IN gckOS Os, -+ IN gctPOINTER Mutex -+ ); -+ -+/* Atomically exchange a pair of 32-bit values. */ -+gceSTATUS -+gckOS_AtomicExchange( -+ IN gckOS Os, -+ IN OUT gctUINT32_PTR Target, -+ IN gctUINT32 NewValue, -+ OUT gctUINT32_PTR OldValue -+ ); -+ -+/* Atomically exchange a pair of pointers. */ -+gceSTATUS -+gckOS_AtomicExchangePtr( -+ IN gckOS Os, -+ IN OUT gctPOINTER * Target, -+ IN gctPOINTER NewValue, -+ OUT gctPOINTER * OldValue -+ ); -+ -+gceSTATUS -+gckOS_AtomSetMask( -+ IN gctPOINTER Atom, -+ IN gctUINT32 Mask -+ ); -+ -+gceSTATUS -+gckOS_AtomClearMask( -+ IN gctPOINTER Atom, -+ IN gctUINT32 Mask -+ ); -+ -+gceSTATUS -+gckOS_DumpCallStack( -+ IN gckOS Os -+ ); -+ -+gceSTATUS -+gckOS_GetProcessNameByPid( -+ IN gctINT Pid, -+ IN gctSIZE_T Length, -+ OUT gctUINT8_PTR String -+ ); -+ -+/******************************************************************************* -+** -+** gckOS_AtomConstruct -+** -+** Create an atom. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to a gckOS object. -+** -+** OUTPUT: -+** -+** gctPOINTER * Atom -+** Pointer to a variable receiving the constructed atom. -+*/ -+gceSTATUS -+gckOS_AtomConstruct( -+ IN gckOS Os, -+ OUT gctPOINTER * Atom -+ ); -+ -+/******************************************************************************* -+** -+** gckOS_AtomDestroy -+** -+** Destroy an atom. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to a gckOS object. -+** -+** gctPOINTER Atom -+** Pointer to the atom to destroy. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_AtomDestroy( -+ IN gckOS Os, -+ OUT gctPOINTER Atom -+ ); -+ -+/******************************************************************************* -+** -+** gckOS_AtomGet -+** -+** Get the 32-bit value protected by an atom. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to a gckOS object. -+** -+** gctPOINTER Atom -+** Pointer to the atom. -+** -+** OUTPUT: -+** -+** gctINT32_PTR Value -+** Pointer to a variable the receives the value of the atom. -+*/ -+gceSTATUS -+gckOS_AtomGet( -+ IN gckOS Os, -+ IN gctPOINTER Atom, -+ OUT gctINT32_PTR Value -+ ); -+ -+/******************************************************************************* -+** -+** gckOS_AtomSet -+** -+** Set the 32-bit value protected by an atom. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to a gckOS object. -+** -+** gctPOINTER Atom -+** Pointer to the atom. -+** -+** gctINT32 Value -+** The value of the atom. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_AtomSet( -+ IN gckOS Os, -+ IN gctPOINTER Atom, -+ IN gctINT32 Value -+ ); -+ -+/******************************************************************************* -+** -+** gckOS_AtomIncrement -+** -+** Atomically increment the 32-bit integer value inside an atom. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to a gckOS object. -+** -+** gctPOINTER Atom -+** Pointer to the atom. -+** -+** OUTPUT: -+** -+** gctINT32_PTR Value -+** Pointer to a variable the receives the original value of the atom. -+*/ -+gceSTATUS -+gckOS_AtomIncrement( -+ IN gckOS Os, -+ IN gctPOINTER Atom, -+ OUT gctINT32_PTR Value -+ ); -+ -+/******************************************************************************* -+** -+** gckOS_AtomDecrement -+** -+** Atomically decrement the 32-bit integer value inside an atom. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to a gckOS object. -+** -+** gctPOINTER Atom -+** Pointer to the atom. -+** -+** OUTPUT: -+** -+** gctINT32_PTR Value -+** Pointer to a variable the receives the original value of the atom. -+*/ -+gceSTATUS -+gckOS_AtomDecrement( -+ IN gckOS Os, -+ IN gctPOINTER Atom, -+ OUT gctINT32_PTR Value -+ ); -+ -+/* Delay a number of microseconds. */ -+gceSTATUS -+gckOS_Delay( -+ IN gckOS Os, -+ IN gctUINT32 Delay -+ ); -+ -+/* Get time in milliseconds. */ -+gceSTATUS -+gckOS_GetTicks( -+ OUT gctUINT32_PTR Time -+ ); -+ -+/* Compare time value. */ -+gceSTATUS -+gckOS_TicksAfter( -+ IN gctUINT32 Time1, -+ IN gctUINT32 Time2, -+ OUT gctBOOL_PTR IsAfter -+ ); -+ -+/* Get time in microseconds. */ -+gceSTATUS -+gckOS_GetTime( -+ OUT gctUINT64_PTR Time -+ ); -+ -+/* Memory barrier. */ -+gceSTATUS -+gckOS_MemoryBarrier( -+ IN gckOS Os, -+ IN gctPOINTER Address -+ ); -+ -+/* Map user pointer. */ -+gceSTATUS -+gckOS_MapUserPointer( -+ IN gckOS Os, -+ IN gctPOINTER Pointer, -+ IN gctSIZE_T Size, -+ OUT gctPOINTER * KernelPointer -+ ); -+ -+/* Unmap user pointer. */ -+gceSTATUS -+gckOS_UnmapUserPointer( -+ IN gckOS Os, -+ IN gctPOINTER Pointer, -+ IN gctSIZE_T Size, -+ IN gctPOINTER KernelPointer -+ ); -+ -+/******************************************************************************* -+** -+** gckOS_QueryNeedCopy -+** -+** Query whether the memory can be accessed or mapped directly or it has to be -+** copied. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctUINT32 ProcessID -+** Process ID of the current process. -+** -+** OUTPUT: -+** -+** gctBOOL_PTR NeedCopy -+** Pointer to a boolean receiving gcvTRUE if the memory needs a copy or -+** gcvFALSE if the memory can be accessed or mapped dircetly. -+*/ -+gceSTATUS -+gckOS_QueryNeedCopy( -+ IN gckOS Os, -+ IN gctUINT32 ProcessID, -+ OUT gctBOOL_PTR NeedCopy -+ ); -+ -+/******************************************************************************* -+** -+** gckOS_CopyFromUserData -+** -+** Copy data from user to kernel memory. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctPOINTER KernelPointer -+** Pointer to kernel memory. -+** -+** gctPOINTER Pointer -+** Pointer to user memory. -+** -+** gctSIZE_T Size -+** Number of bytes to copy. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_CopyFromUserData( -+ IN gckOS Os, -+ IN gctPOINTER KernelPointer, -+ IN gctPOINTER Pointer, -+ IN gctSIZE_T Size -+ ); -+ -+/******************************************************************************* -+** -+** gckOS_CopyToUserData -+** -+** Copy data from kernel to user memory. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to an gckOS object. -+** -+** gctPOINTER KernelPointer -+** Pointer to kernel memory. -+** -+** gctPOINTER Pointer -+** Pointer to user memory. -+** -+** gctSIZE_T Size -+** Number of bytes to copy. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_CopyToUserData( -+ IN gckOS Os, -+ IN gctPOINTER KernelPointer, -+ IN gctPOINTER Pointer, -+ IN gctSIZE_T Size -+ ); -+ -+gceSTATUS -+gckOS_SuspendInterrupt( -+ IN gckOS Os -+ ); -+ -+gceSTATUS -+gckOS_SuspendInterruptEx( -+ IN gckOS Os, -+ IN gceCORE Core -+ ); -+ -+gceSTATUS -+gckOS_ResumeInterrupt( -+ IN gckOS Os -+ ); -+ -+gceSTATUS -+gckOS_ResumeInterruptEx( -+ IN gckOS Os, -+ IN gceCORE Core -+ ); -+ -+/* Get the base address for the physical memory. */ -+gceSTATUS -+gckOS_GetBaseAddress( -+ IN gckOS Os, -+ OUT gctUINT32_PTR BaseAddress -+ ); -+ -+/* Perform a memory copy. */ -+gceSTATUS -+gckOS_MemCopy( -+ IN gctPOINTER Destination, -+ IN gctCONST_POINTER Source, -+ IN gctSIZE_T Bytes -+ ); -+ -+/* Zero memory. */ -+gceSTATUS -+gckOS_ZeroMemory( -+ IN gctPOINTER Memory, -+ IN gctSIZE_T Bytes -+ ); -+ -+/* Device I/O control to the kernel HAL layer. */ -+gceSTATUS -+gckOS_DeviceControl( -+ IN gckOS Os, -+ IN gctBOOL FromUser, -+ IN gctUINT32 IoControlCode, -+ IN gctPOINTER InputBuffer, -+ IN gctSIZE_T InputBufferSize, -+ OUT gctPOINTER OutputBuffer, -+ IN gctSIZE_T OutputBufferSize -+ ); -+ -+/******************************************************************************* -+** -+** gckOS_GetProcessID -+** -+** Get current process ID. -+** -+** INPUT: -+** -+** Nothing. -+** -+** OUTPUT: -+** -+** gctUINT32_PTR ProcessID -+** Pointer to the variable that receives the process ID. -+*/ -+gceSTATUS -+gckOS_GetProcessID( -+ OUT gctUINT32_PTR ProcessID -+ ); -+ -+gceSTATUS -+gckOS_GetCurrentProcessID( -+ OUT gctUINT32_PTR ProcessID -+ ); -+ -+/******************************************************************************* -+** -+** gckOS_GetThreadID -+** -+** Get current thread ID. -+** -+** INPUT: -+** -+** Nothing. -+** -+** OUTPUT: -+** -+** gctUINT32_PTR ThreadID -+** Pointer to the variable that receives the thread ID. -+*/ -+gceSTATUS -+gckOS_GetThreadID( -+ OUT gctUINT32_PTR ThreadID -+ ); -+ -+/******************************************************************************\ -+********************************** Signal Object ********************************* -+\******************************************************************************/ -+ -+/* Create a signal. */ -+gceSTATUS -+gckOS_CreateSignal( -+ IN gckOS Os, -+ IN gctBOOL ManualReset, -+ OUT gctSIGNAL * Signal -+ ); -+ -+/* Destroy a signal. */ -+gceSTATUS -+gckOS_DestroySignal( -+ IN gckOS Os, -+ IN gctSIGNAL Signal -+ ); -+ -+/* Signal a signal. */ -+gceSTATUS -+gckOS_Signal( -+ IN gckOS Os, -+ IN gctSIGNAL Signal, -+ IN gctBOOL State -+ ); -+ -+/* Wait for a signal. */ -+gceSTATUS -+gckOS_WaitSignal( -+ IN gckOS Os, -+ IN gctSIGNAL Signal, -+ IN gctUINT32 Wait -+ ); -+ -+/* Map a user signal to the kernel space. */ -+gceSTATUS -+gckOS_MapSignal( -+ IN gckOS Os, -+ IN gctSIGNAL Signal, -+ IN gctHANDLE Process, -+ OUT gctSIGNAL * MappedSignal -+ ); -+ -+/* Unmap a user signal */ -+gceSTATUS -+gckOS_UnmapSignal( -+ IN gckOS Os, -+ IN gctSIGNAL Signal -+ ); -+ -+/* Map user memory. */ -+gceSTATUS -+gckOS_MapUserMemory( -+ IN gckOS Os, -+ IN gceCORE Core, -+ IN gctPOINTER Memory, -+ IN gctUINT32 Physical, -+ IN gctSIZE_T Size, -+ OUT gctPOINTER * Info, -+ OUT gctUINT32_PTR Address -+ ); -+ -+/* Unmap user memory. */ -+gceSTATUS -+gckOS_UnmapUserMemory( -+ IN gckOS Os, -+ IN gceCORE Core, -+ IN gctPOINTER Memory, -+ IN gctSIZE_T Size, -+ IN gctPOINTER Info, -+ IN gctUINT32 Address -+ ); -+ -+/******************************************************************************\ -+************************** Android Native Fence Sync *************************** -+\******************************************************************************/ -+gceSTATUS -+gckOS_CreateSyncTimeline( -+ IN gckOS Os, -+ OUT gctHANDLE * Timeline -+ ); -+ -+gceSTATUS -+gckOS_DestroySyncTimeline( -+ IN gckOS Os, -+ IN gctHANDLE Timeline -+ ); -+ -+gceSTATUS -+gckOS_CreateSyncPoint( -+ IN gckOS Os, -+ OUT gctSYNC_POINT * SyncPoint -+ ); -+ -+gceSTATUS -+gckOS_ReferenceSyncPoint( -+ IN gckOS Os, -+ IN gctSYNC_POINT SyncPoint -+ ); -+ -+gceSTATUS -+gckOS_DestroySyncPoint( -+ IN gckOS Os, -+ IN gctSYNC_POINT SyncPoint -+ ); -+ -+gceSTATUS -+gckOS_SignalSyncPoint( -+ IN gckOS Os, -+ IN gctSYNC_POINT SyncPoint -+ ); -+ -+gceSTATUS -+gckOS_QuerySyncPoint( -+ IN gckOS Os, -+ IN gctSYNC_POINT SyncPoint, -+ OUT gctBOOL_PTR State -+ ); -+ -+gceSTATUS -+gckOS_CreateNativeFence( -+ IN gckOS Os, -+ IN gctHANDLE Timeline, -+ IN gctSYNC_POINT SyncPoint, -+ OUT gctINT * FenceFD -+ ); -+ -+/* Create signal to be used in the user space. */ -+gceSTATUS -+gckOS_CreateUserSignal( -+ IN gckOS Os, -+ IN gctBOOL ManualReset, -+ OUT gctINT * SignalID -+ ); -+ -+/* Destroy signal used in the user space. */ -+gceSTATUS -+gckOS_DestroyUserSignal( -+ IN gckOS Os, -+ IN gctINT SignalID -+ ); -+ -+/* Wait for signal used in the user space. */ -+gceSTATUS -+gckOS_WaitUserSignal( -+ IN gckOS Os, -+ IN gctINT SignalID, -+ IN gctUINT32 Wait -+ ); -+ -+/* Signal a signal used in the user space. */ -+gceSTATUS -+gckOS_SignalUserSignal( -+ IN gckOS Os, -+ IN gctINT SignalID, -+ IN gctBOOL State -+ ); -+ -+/* Set a signal owned by a process. */ -+gceSTATUS -+gckOS_UserSignal( -+ IN gckOS Os, -+ IN gctSIGNAL Signal, -+ IN gctHANDLE Process -+ ); -+ -+/******************************************************************************\ -+** Cache Support -+*/ -+ -+gceSTATUS -+gckOS_CacheClean( -+ gckOS Os, -+ gctUINT32 ProcessID, -+ gctPHYS_ADDR Handle, -+ gctUINT32 Physical, -+ gctPOINTER Logical, -+ gctSIZE_T Bytes -+ ); -+ -+gceSTATUS -+gckOS_CacheFlush( -+ gckOS Os, -+ gctUINT32 ProcessID, -+ gctPHYS_ADDR Handle, -+ gctUINT32 Physical, -+ gctPOINTER Logical, -+ gctSIZE_T Bytes -+ ); -+ -+gceSTATUS -+gckOS_CacheInvalidate( -+ gckOS Os, -+ gctUINT32 ProcessID, -+ gctPHYS_ADDR Handle, -+ gctUINT32 Physical, -+ gctPOINTER Logical, -+ gctSIZE_T Bytes -+ ); -+ -+gceSTATUS -+gckOS_CPUPhysicalToGPUPhysical( -+ IN gckOS Os, -+ IN gctUINT32 CPUPhysical, -+ IN gctUINT32_PTR GPUPhysical -+ ); -+ -+gceSTATUS -+gckOS_GPUPhysicalToCPUPhysical( -+ IN gckOS Os, -+ IN gctUINT32 GPUPhysical, -+ IN gctUINT32_PTR CPUPhysical -+ ); -+ -+gceSTATUS -+gckOS_QueryOption( -+ IN gckOS Os, -+ IN gctCONST_STRING Option, -+ OUT gctUINT32 * Value -+ ); -+ -+/******************************************************************************\ -+** Debug Support -+*/ -+ -+void -+gckOS_SetDebugLevel( -+ IN gctUINT32 Level -+ ); -+ -+void -+gckOS_SetDebugZone( -+ IN gctUINT32 Zone -+ ); -+ -+void -+gckOS_SetDebugLevelZone( -+ IN gctUINT32 Level, -+ IN gctUINT32 Zone -+ ); -+ -+void -+gckOS_SetDebugZones( -+ IN gctUINT32 Zones, -+ IN gctBOOL Enable -+ ); -+ -+void -+gckOS_SetDebugFile( -+ IN gctCONST_STRING FileName -+ ); -+ -+/******************************************************************************* -+** Broadcast interface. -+*/ -+ -+typedef enum _gceBROADCAST -+{ -+ /* GPU might be idle. */ -+ gcvBROADCAST_GPU_IDLE, -+ -+ /* A commit is going to happen. */ -+ gcvBROADCAST_GPU_COMMIT, -+ -+ /* GPU seems to be stuck. */ -+ gcvBROADCAST_GPU_STUCK, -+ -+ /* First process gets attached. */ -+ gcvBROADCAST_FIRST_PROCESS, -+ -+ /* Last process gets detached. */ -+ gcvBROADCAST_LAST_PROCESS, -+ -+ /* AXI bus error. */ -+ gcvBROADCAST_AXI_BUS_ERROR, -+ -+ /* Out of memory. */ -+ gcvBROADCAST_OUT_OF_MEMORY, -+} -+gceBROADCAST; -+ -+gceSTATUS -+gckOS_Broadcast( -+ IN gckOS Os, -+ IN gckHARDWARE Hardware, -+ IN gceBROADCAST Reason -+ ); -+ -+gceSTATUS -+gckOS_BroadcastHurry( -+ IN gckOS Os, -+ IN gckHARDWARE Hardware, -+ IN gctUINT Urgency -+ ); -+ -+gceSTATUS -+gckOS_BroadcastCalibrateSpeed( -+ IN gckOS Os, -+ IN gckHARDWARE Hardware, -+ IN gctUINT Idle, -+ IN gctUINT Time -+ ); -+ -+/******************************************************************************* -+** -+** gckOS_SetGPUPower -+** -+** Set the power of the GPU on or off. -+** -+** INPUT: -+** -+** gckOS Os -+** Pointer to a gckOS object. -+** -+** gceCORE Core -+** GPU whose power is set. -+** -+** gctBOOL Clock -+** gcvTRUE to turn on the clock, or gcvFALSE to turn off the clock. -+** -+** gctBOOL Power -+** gcvTRUE to turn on the power, or gcvFALSE to turn off the power. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckOS_SetGPUPower( -+ IN gckOS Os, -+ IN gceCORE Core, -+ IN gctBOOL Clock, -+ IN gctBOOL Power -+ ); -+ -+gceSTATUS -+gckOS_ResetGPU( -+ IN gckOS Os, -+ IN gceCORE Core -+ ); -+ -+gceSTATUS -+gckOS_PrepareGPUFrequency( -+ IN gckOS Os, -+ IN gceCORE Core -+ ); -+ -+gceSTATUS -+gckOS_FinishGPUFrequency( -+ IN gckOS Os, -+ IN gceCORE Core -+ ); -+ -+gceSTATUS -+gckOS_QueryGPUFrequency( -+ IN gckOS Os, -+ IN gceCORE Core, -+ OUT gctUINT32 * Frequency, -+ OUT gctUINT8 * Scale -+ ); -+ -+gceSTATUS -+gckOS_SetGPUFrequency( -+ IN gckOS Os, -+ IN gceCORE Core, -+ IN gctUINT8 Scale -+ ); -+ -+/******************************************************************************* -+** Semaphores. -+*/ -+ -+/* Create a new semaphore. */ -+gceSTATUS -+gckOS_CreateSemaphore( -+ IN gckOS Os, -+ OUT gctPOINTER * Semaphore -+ ); -+ -+#if gcdENABLE_VG -+gceSTATUS -+gckOS_CreateSemaphoreVG( -+ IN gckOS Os, -+ OUT gctPOINTER * Semaphore -+ ); -+#endif -+ -+/* Delete a semahore. */ -+gceSTATUS -+gckOS_DestroySemaphore( -+ IN gckOS Os, -+ IN gctPOINTER Semaphore -+ ); -+ -+/* Acquire a semahore. */ -+gceSTATUS -+gckOS_AcquireSemaphore( -+ IN gckOS Os, -+ IN gctPOINTER Semaphore -+ ); -+ -+/* Try to acquire a semahore. */ -+gceSTATUS -+gckOS_TryAcquireSemaphore( -+ IN gckOS Os, -+ IN gctPOINTER Semaphore -+ ); -+ -+/* Release a semahore. */ -+gceSTATUS -+gckOS_ReleaseSemaphore( -+ IN gckOS Os, -+ IN gctPOINTER Semaphore -+ ); -+ -+/******************************************************************************* -+** Timer API. -+*/ -+ -+typedef void (*gctTIMERFUNCTION)(gctPOINTER); -+ -+/* Create a timer. */ -+gceSTATUS -+gckOS_CreateTimer( -+ IN gckOS Os, -+ IN gctTIMERFUNCTION Function, -+ IN gctPOINTER Data, -+ OUT gctPOINTER * Timer -+ ); -+ -+/* Destory a timer. */ -+gceSTATUS -+gckOS_DestroyTimer( -+ IN gckOS Os, -+ IN gctPOINTER Timer -+ ); -+ -+/* Start a timer. */ -+gceSTATUS -+gckOS_StartTimer( -+ IN gckOS Os, -+ IN gctPOINTER Timer, -+ IN gctUINT32 Delay -+ ); -+ -+/* Stop a timer. */ -+gceSTATUS -+gckOS_StopTimer( -+ IN gckOS Os, -+ IN gctPOINTER Timer -+ ); -+ -+/******************************************************************************\ -+********************************* gckHEAP Object ******************************** -+\******************************************************************************/ -+ -+typedef struct _gckHEAP * gckHEAP; -+ -+/* Construct a new gckHEAP object. */ -+gceSTATUS -+gckHEAP_Construct( -+ IN gckOS Os, -+ IN gctSIZE_T AllocationSize, -+ OUT gckHEAP * Heap -+ ); -+ -+/* Destroy an gckHEAP object. */ -+gceSTATUS -+gckHEAP_Destroy( -+ IN gckHEAP Heap -+ ); -+ -+/* Allocate memory. */ -+gceSTATUS -+gckHEAP_Allocate( -+ IN gckHEAP Heap, -+ IN gctSIZE_T Bytes, -+ OUT gctPOINTER * Node -+ ); -+ -+/* Free memory. */ -+gceSTATUS -+gckHEAP_Free( -+ IN gckHEAP Heap, -+ IN gctPOINTER Node -+ ); -+ -+/* Profile the heap. */ -+gceSTATUS -+gckHEAP_ProfileStart( -+ IN gckHEAP Heap -+ ); -+ -+gceSTATUS -+gckHEAP_ProfileEnd( -+ IN gckHEAP Heap, -+ IN gctCONST_STRING Title -+ ); -+ -+ -+/******************************************************************************\ -+******************************** gckVIDMEM Object ****************************** -+\******************************************************************************/ -+ -+typedef struct _gckVIDMEM * gckVIDMEM; -+typedef struct _gckKERNEL * gckKERNEL; -+typedef struct _gckDB * gckDB; -+typedef struct _gckDVFS * gckDVFS; -+ -+/* Construct a new gckVIDMEM object. */ -+gceSTATUS -+gckVIDMEM_Construct( -+ IN gckOS Os, -+ IN gctUINT32 BaseAddress, -+ IN gctSIZE_T Bytes, -+ IN gctSIZE_T Threshold, -+ IN gctSIZE_T Banking, -+ OUT gckVIDMEM * Memory -+ ); -+ -+/* Destroy an gckVDIMEM object. */ -+gceSTATUS -+gckVIDMEM_Destroy( -+ IN gckVIDMEM Memory -+ ); -+ -+/* Allocate linear memory. */ -+gceSTATUS -+gckVIDMEM_AllocateLinear( -+ IN gckKERNEL Kernel, -+ IN gckVIDMEM Memory, -+ IN gctSIZE_T Bytes, -+ IN gctUINT32 Alignment, -+ IN gceSURF_TYPE Type, -+ IN gctBOOL Specified, -+ OUT gcuVIDMEM_NODE_PTR * Node -+ ); -+ -+/* Free memory. */ -+gceSTATUS -+gckVIDMEM_Free( -+ IN gckKERNEL Kernel, -+ IN gcuVIDMEM_NODE_PTR Node -+ ); -+ -+/* Lock memory. */ -+gceSTATUS -+gckVIDMEM_Lock( -+ IN gckKERNEL Kernel, -+ IN gckVIDMEM_NODE Node, -+ IN gctBOOL Cacheable, -+ OUT gctUINT32 * Address, -+ OUT gctUINT32 * Gid, -+ OUT gctUINT64 * PhysicalAddress -+ ); -+ -+/* Unlock memory. */ -+gceSTATUS -+gckVIDMEM_Unlock( -+ IN gckKERNEL Kernel, -+ IN gckVIDMEM_NODE Node, -+ IN gceSURF_TYPE Type, -+ IN OUT gctBOOL * Asynchroneous -+ ); -+ -+/* Construct a gcuVIDMEM_NODE union for virtual memory. */ -+gceSTATUS -+gckVIDMEM_ConstructVirtual( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 Flag, -+ IN gctSIZE_T Bytes, -+ OUT gcuVIDMEM_NODE_PTR * Node -+ ); -+ -+/* Destroy a gcuVIDMEM_NODE union for virtual memory. */ -+gceSTATUS -+gckVIDMEM_DestroyVirtual( -+ IN gcuVIDMEM_NODE_PTR Node -+ ); -+ -+/******************************************************************************\ -+******************************** gckKERNEL Object ****************************** -+\******************************************************************************/ -+ -+struct _gcsHAL_INTERFACE; -+ -+/* Notifications. */ -+typedef enum _gceNOTIFY -+{ -+ gcvNOTIFY_INTERRUPT, -+ gcvNOTIFY_COMMAND_QUEUE, -+} -+gceNOTIFY; -+ -+/* Flush flags. */ -+typedef enum _gceKERNEL_FLUSH -+{ -+ gcvFLUSH_COLOR = 0x01, -+ gcvFLUSH_DEPTH = 0x02, -+ gcvFLUSH_TEXTURE = 0x04, -+ gcvFLUSH_2D = 0x08, -+ gcvFLUSH_TILE_STATUS = 0x20, -+ gcvFLUSH_ALL = gcvFLUSH_COLOR -+ | gcvFLUSH_DEPTH -+ | gcvFLUSH_TEXTURE -+ | gcvFLUSH_2D -+ | gcvFLUSH_TILE_STATUS -+} -+gceKERNEL_FLUSH; -+ -+/* Construct a new gckKERNEL object. */ -+gceSTATUS -+gckKERNEL_Construct( -+ IN gckOS Os, -+ IN gceCORE Core, -+ IN gctPOINTER Context, -+ IN gckDB SharedDB, -+ OUT gckKERNEL * Kernel -+ ); -+ -+/* Destroy an gckKERNEL object. */ -+gceSTATUS -+gckKERNEL_Destroy( -+ IN gckKERNEL Kernel -+ ); -+ -+/* Dispatch a user-level command. */ -+gceSTATUS -+gckKERNEL_Dispatch( -+ IN gckKERNEL Kernel, -+ IN gctBOOL FromUser, -+ IN OUT struct _gcsHAL_INTERFACE * Interface -+ ); -+ -+/* Query Database requirements. */ -+gceSTATUS -+ gckKERNEL_QueryDatabase( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 ProcessID, -+ IN OUT gcsHAL_INTERFACE * Interface -+ ); -+ -+/* Query the video memory. */ -+gceSTATUS -+gckKERNEL_QueryVideoMemory( -+ IN gckKERNEL Kernel, -+ OUT struct _gcsHAL_INTERFACE * Interface -+ ); -+ -+/* Lookup the gckVIDMEM object for a pool. */ -+gceSTATUS -+gckKERNEL_GetVideoMemoryPool( -+ IN gckKERNEL Kernel, -+ IN gcePOOL Pool, -+ OUT gckVIDMEM * VideoMemory -+ ); -+ -+gceSTATUS -+gckKERNEL_AllocateLinearMemory( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 ProcessID, -+ IN OUT gcePOOL * Pool, -+ IN gctSIZE_T Bytes, -+ IN gctUINT32 Alignment, -+ IN gceSURF_TYPE Type, -+ IN gctUINT32 Flag, -+ OUT gctUINT32 * Node -+ ); -+ -+gceSTATUS -+gckKERNEL_ReleaseVideoMemory( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 ProcessID, -+ IN gctUINT32 Handle -+ ); -+ -+gceSTATUS -+gckKERNEL_LockVideoMemory( -+ IN gckKERNEL Kernel, -+ IN gceCORE Core, -+ IN gctUINT32 ProcessID, -+ IN gctBOOL FromUser, -+ IN OUT gcsHAL_INTERFACE * Interface -+ ); -+ -+gceSTATUS -+gckKERNEL_UnlockVideoMemory( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 ProcessID, -+ IN OUT gcsHAL_INTERFACE * Interface -+ ); -+ -+/* Map video memory. */ -+gceSTATUS -+gckKERNEL_MapVideoMemory( -+ IN gckKERNEL Kernel, -+ IN gctBOOL InUserSpace, -+ IN gctUINT32 Address, -+ OUT gctPOINTER * Logical -+ ); -+ -+/* Map video memory. */ -+gceSTATUS -+gckKERNEL_MapVideoMemoryEx( -+ IN gckKERNEL Kernel, -+ IN gceCORE Core, -+ IN gctBOOL InUserSpace, -+ IN gctUINT32 Address, -+ OUT gctPOINTER * Logical -+ ); -+ -+/* Map memory. */ -+gceSTATUS -+gckKERNEL_MapMemory( -+ IN gckKERNEL Kernel, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T Bytes, -+ OUT gctPOINTER * Logical -+ ); -+ -+/* Unmap memory. */ -+gceSTATUS -+gckKERNEL_UnmapMemory( -+ IN gckKERNEL Kernel, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T Bytes, -+ IN gctPOINTER Logical -+ ); -+ -+/* Notification of events. */ -+gceSTATUS -+gckKERNEL_Notify( -+ IN gckKERNEL Kernel, -+ IN gceNOTIFY Notifcation, -+ IN gctBOOL Data -+ ); -+ -+gceSTATUS -+gckKERNEL_QuerySettings( -+ IN gckKERNEL Kernel, -+ OUT gcsKERNEL_SETTINGS * Settings -+ ); -+ -+/******************************************************************************* -+** -+** gckKERNEL_Recovery -+** -+** Try to recover the GPU from a fatal error. -+** -+** INPUT: -+** -+** gckKERNEL Kernel -+** Pointer to an gckKERNEL object. -+** -+** OUTPUT: -+** -+** Nothing. -+*/ -+gceSTATUS -+gckKERNEL_Recovery( -+ IN gckKERNEL Kernel -+ ); -+ -+/* Set the value of timeout on HW operation. */ -+void -+gckKERNEL_SetTimeOut( -+ IN gckKERNEL Kernel, -+ IN gctUINT32 timeOut -+ ); -+ -+/* Get access to the user data. */ -+gceSTATUS -+gckKERNEL_OpenUserData( -+ IN gckKERNEL Kernel, -+ IN gctBOOL NeedCopy, -+ IN gctPOINTER StaticStorage, -+ IN gctPOINTER UserPointer, -+ IN gctSIZE_T Size, -+ OUT gctPOINTER * KernelPointer -+ ); -+ -+/* Release resources associated with the user data connection. */ -+gceSTATUS -+gckKERNEL_CloseUserData( -+ IN gckKERNEL Kernel, -+ IN gctBOOL NeedCopy, -+ IN gctBOOL FlushData, -+ IN gctPOINTER UserPointer, -+ IN gctSIZE_T Size, -+ OUT gctPOINTER * KernelPointer -+ ); -+ -+gceSTATUS -+gckDVFS_Construct( -+ IN gckHARDWARE Hardware, -+ OUT gckDVFS * Frequency -+ ); -+ -+gceSTATUS -+gckDVFS_Destroy( -+ IN gckDVFS Dvfs -+ ); -+ -+gceSTATUS -+gckDVFS_Start( -+ IN gckDVFS Dvfs -+ ); -+ -+gceSTATUS -+gckDVFS_Stop( -+ IN gckDVFS Dvfs -+ ); -+ -+/******************************************************************************\ -+******************************* gckHARDWARE Object ***************************** -+\******************************************************************************/ -+ -+/* Construct a new gckHARDWARE object. */ -+gceSTATUS -+gckHARDWARE_Construct( -+ IN gckOS Os, -+ IN gceCORE Core, -+ OUT gckHARDWARE * Hardware -+ ); -+ -+/* Destroy an gckHARDWARE object. */ -+gceSTATUS -+gckHARDWARE_Destroy( -+ IN gckHARDWARE Hardware -+ ); -+ -+/* Get hardware type. */ -+gceSTATUS -+gckHARDWARE_GetType( -+ IN gckHARDWARE Hardware, -+ OUT gceHARDWARE_TYPE * Type -+ ); -+ -+/* Query system memory requirements. */ -+gceSTATUS -+gckHARDWARE_QuerySystemMemory( -+ IN gckHARDWARE Hardware, -+ OUT gctSIZE_T * SystemSize, -+ OUT gctUINT32 * SystemBaseAddress -+ ); -+ -+/* Build virtual address. */ -+gceSTATUS -+gckHARDWARE_BuildVirtualAddress( -+ IN gckHARDWARE Hardware, -+ IN gctUINT32 Index, -+ IN gctUINT32 Offset, -+ OUT gctUINT32 * Address -+ ); -+ -+/* Query command buffer requirements. */ -+gceSTATUS -+gckHARDWARE_QueryCommandBuffer( -+ IN gckHARDWARE Hardware, -+ OUT gctUINT32 * Alignment, -+ OUT gctUINT32 * ReservedHead, -+ OUT gctUINT32 * ReservedTail -+ ); -+ -+/* Add a WAIT/LINK pair in the command queue. */ -+gceSTATUS -+gckHARDWARE_WaitLink( -+ IN gckHARDWARE Hardware, -+ IN gctPOINTER Logical, -+ IN gctUINT32 Offset, -+ IN OUT gctUINT32 * Bytes, -+ OUT gctUINT32 * WaitOffset, -+ OUT gctUINT32 * WaitBytes -+ ); -+ -+/* Kickstart the command processor. */ -+gceSTATUS -+gckHARDWARE_Execute( -+ IN gckHARDWARE Hardware, -+ IN gctUINT32 Address, -+ IN gctSIZE_T Bytes -+ ); -+ -+/* Add an END command in the command queue. */ -+gceSTATUS -+gckHARDWARE_End( -+ IN gckHARDWARE Hardware, -+ IN gctPOINTER Logical, -+ IN OUT gctUINT32 * Bytes -+ ); -+ -+/* Add a NOP command in the command queue. */ -+gceSTATUS -+gckHARDWARE_Nop( -+ IN gckHARDWARE Hardware, -+ IN gctPOINTER Logical, -+ IN OUT gctSIZE_T * Bytes -+ ); -+ -+/* Add a PIPESELECT command in the command queue. */ -+gceSTATUS -+gckHARDWARE_PipeSelect( -+ IN gckHARDWARE Hardware, -+ IN gctPOINTER Logical, -+ IN gcePIPE_SELECT Pipe, -+ IN OUT gctUINT32 * Bytes -+ ); -+ -+/* Add a LINK command in the command queue. */ -+gceSTATUS -+gckHARDWARE_Link( -+ IN gckHARDWARE Hardware, -+ IN gctPOINTER Logical, -+ IN gctUINT32 FetchAddress, -+ IN gctUINT32 FetchSize, -+ IN OUT gctUINT32 * Bytes -+ ); -+ -+/* Add an EVENT command in the command queue. */ -+gceSTATUS -+gckHARDWARE_Event( -+ IN gckHARDWARE Hardware, -+ IN gctPOINTER Logical, -+ IN gctUINT8 Event, -+ IN gceKERNEL_WHERE FromWhere, -+ IN OUT gctUINT32 * Bytes -+ ); -+ -+/* Query the available memory. */ -+gceSTATUS -+gckHARDWARE_QueryMemory( -+ IN gckHARDWARE Hardware, -+ OUT gctSIZE_T * InternalSize, -+ OUT gctUINT32 * InternalBaseAddress, -+ OUT gctUINT32 * InternalAlignment, -+ OUT gctSIZE_T * ExternalSize, -+ OUT gctUINT32 * ExternalBaseAddress, -+ OUT gctUINT32 * ExternalAlignment, -+ OUT gctUINT32 * HorizontalTileSize, -+ OUT gctUINT32 * VerticalTileSize -+ ); -+ -+/* Query the identity of the hardware. */ -+gceSTATUS -+gckHARDWARE_QueryChipIdentity( -+ IN gckHARDWARE Hardware, -+ OUT gcsHAL_QUERY_CHIP_IDENTITY_PTR Identity -+ ); -+ -+/* Query the shader uniforms support. */ -+gceSTATUS -+gckHARDWARE_QueryShaderCaps( -+ IN gckHARDWARE Hardware, -+ OUT gctUINT * VertexUniforms, -+ OUT gctUINT * FragmentUniforms, -+ OUT gctBOOL * UnifiedUnforms -+ ); -+ -+/* Split a harwdare specific address into API stuff. */ -+gceSTATUS -+gckHARDWARE_SplitMemory( -+ IN gckHARDWARE Hardware, -+ IN gctUINT32 Address, -+ OUT gcePOOL * Pool, -+ OUT gctUINT32 * Offset -+ ); -+ -+/* Update command queue tail pointer. */ -+gceSTATUS -+gckHARDWARE_UpdateQueueTail( -+ IN gckHARDWARE Hardware, -+ IN gctPOINTER Logical, -+ IN gctUINT32 Offset -+ ); -+ -+/* Convert logical address to hardware specific address. */ -+gceSTATUS -+gckHARDWARE_ConvertLogical( -+ IN gckHARDWARE Hardware, -+ IN gctPOINTER Logical, -+ IN gctBOOL InUserSpace, -+ OUT gctUINT32 * Address -+ ); -+ -+/* Interrupt manager. */ -+gceSTATUS -+gckHARDWARE_Interrupt( -+ IN gckHARDWARE Hardware, -+ IN gctBOOL InterruptValid -+ ); -+ -+/* Program MMU. */ -+gceSTATUS -+gckHARDWARE_SetMMU( -+ IN gckHARDWARE Hardware, -+ IN gctPOINTER Logical -+ ); -+ -+/* Flush the MMU. */ -+gceSTATUS -+gckHARDWARE_FlushMMU( -+ IN gckHARDWARE Hardware -+ ); -+ -+/* Set the page table base address. */ -+gceSTATUS -+gckHARDWARE_SetMMUv2( -+ IN gckHARDWARE Hardware, -+ IN gctBOOL Enable, -+ IN gctPOINTER MtlbAddress, -+ IN gceMMU_MODE Mode, -+ IN gctPOINTER SafeAddress, -+ IN gctBOOL FromPower -+ ); -+ -+#if gcdPROCESS_ADDRESS_SPACE -+/* Configure mmu configuration. */ -+gceSTATUS -+gckHARDWARE_ConfigMMU( -+ IN gckHARDWARE Hardware, -+ IN gctPOINTER Logical, -+ IN gctPOINTER MtlbLogical, -+ IN gctUINT32 Offset, -+ IN OUT gctSIZE_T * Bytes, -+ OUT gctSIZE_T * WaitLinkOffset, -+ OUT gctSIZE_T * WaitLinkBytes -+ ); -+#endif -+ -+/* Get idle register. */ -+gceSTATUS -+gckHARDWARE_GetIdle( -+ IN gckHARDWARE Hardware, -+ IN gctBOOL Wait, -+ OUT gctUINT32 * Data -+ ); -+ -+/* Flush the caches. */ -+gceSTATUS -+gckHARDWARE_Flush( -+ IN gckHARDWARE Hardware, -+ IN gceKERNEL_FLUSH Flush, -+ IN gctPOINTER Logical, -+ IN OUT gctUINT32 * Bytes -+ ); -+ -+/* Enable/disable fast clear. */ -+gceSTATUS -+gckHARDWARE_SetFastClear( -+ IN gckHARDWARE Hardware, -+ IN gctINT Enable, -+ IN gctINT Compression -+ ); -+ -+gceSTATUS -+gckHARDWARE_ReadInterrupt( -+ IN gckHARDWARE Hardware, -+ OUT gctUINT32_PTR IDs -+ ); -+ -+/* Power management. */ -+gceSTATUS -+gckHARDWARE_SetPowerManagementState( -+ IN gckHARDWARE Hardware, -+ IN gceCHIPPOWERSTATE State -+ ); -+ -+gceSTATUS -+gckHARDWARE_QueryPowerManagementState( -+ IN gckHARDWARE Hardware, -+ OUT gceCHIPPOWERSTATE* State -+ ); -+ -+gceSTATUS -+gckHARDWARE_SetPowerManagement( -+ IN gckHARDWARE Hardware, -+ IN gctBOOL PowerManagement -+ ); -+ -+gceSTATUS -+gckHARDWARE_SetPowerManagementLock( -+ IN gckHARDWARE Hardware, -+ IN gctBOOL Lock -+ ); -+ -+gceSTATUS -+gckHARDWARE_SetGpuProfiler( -+ IN gckHARDWARE Hardware, -+ IN gctBOOL GpuProfiler -+ ); -+ -+#if gcdENABLE_FSCALE_VAL_ADJUST -+gceSTATUS -+gckHARDWARE_SetFscaleValue( -+ IN gckHARDWARE Hardware, -+ IN gctUINT32 FscaleValue -+ ); -+ -+gceSTATUS -+gckHARDWARE_GetFscaleValue( -+ IN gckHARDWARE Hardware, -+ IN gctUINT * FscaleValue, -+ IN gctUINT * MinFscaleValue, -+ IN gctUINT * MaxFscaleValue -+ ); -+ -+gceSTATUS -+gckHARDWARE_SetMinFscaleValue( -+ IN gckHARDWARE Hardware, -+ IN gctUINT MinFscaleValue -+ ); -+#endif -+ -+#if gcdPOWEROFF_TIMEOUT -+gceSTATUS -+gckHARDWARE_SetPowerOffTimeout( -+ IN gckHARDWARE Hardware, -+ IN gctUINT32 Timeout -+); -+ -+gceSTATUS -+gckHARDWARE_QueryPowerOffTimeout( -+ IN gckHARDWARE Hardware, -+ OUT gctUINT32* Timeout -+); -+#endif -+ -+/* Profile 2D Engine. */ -+gceSTATUS -+gckHARDWARE_ProfileEngine2D( -+ IN gckHARDWARE Hardware, -+ OUT gcs2D_PROFILE_PTR Profile -+ ); -+ -+gceSTATUS -+gckHARDWARE_InitializeHardware( -+ IN gckHARDWARE Hardware -+ ); -+ -+gceSTATUS -+gckHARDWARE_Reset( -+ IN gckHARDWARE Hardware -+ ); -+ -+typedef gceSTATUS (*gctISRMANAGERFUNC)(gctPOINTER Context, gceCORE Core); -+ -+gceSTATUS -+gckHARDWARE_SetIsrManager( -+ IN gckHARDWARE Hardware, -+ IN gctISRMANAGERFUNC StartIsr, -+ IN gctISRMANAGERFUNC StopIsr, -+ IN gctPOINTER Context -+ ); -+ -+/* Start a composition. */ -+gceSTATUS -+gckHARDWARE_Compose( -+ IN gckHARDWARE Hardware, -+ IN gctUINT32 ProcessID, -+ IN gctPHYS_ADDR Physical, -+ IN gctPOINTER Logical, -+ IN gctSIZE_T Offset, -+ IN gctSIZE_T Size, -+ IN gctUINT8 EventID -+ ); -+ -+/* Check for Hardware features. */ -+gceSTATUS -+gckHARDWARE_IsFeatureAvailable( -+ IN gckHARDWARE Hardware, -+ IN gceFEATURE Feature -+ ); -+ -+gceSTATUS -+gckHARDWARE_DumpMMUException( -+ IN gckHARDWARE Hardware -+ ); -+ -+gceSTATUS -+gckHARDWARE_DumpGPUState( -+ IN gckHARDWARE Hardware -+ ); -+ -+gceSTATUS -+gckHARDWARE_InitDVFS( -+ IN gckHARDWARE Hardware -+ ); -+ -+gceSTATUS -+gckHARDWARE_QueryLoad( -+ IN gckHARDWARE Hardware, -+ OUT gctUINT32 * Load -+ ); -+ -+gceSTATUS -+gckHARDWARE_SetDVFSPeroid( -+ IN gckHARDWARE Hardware, -+ IN gctUINT32 Frequency -+ ); -+ -+gceSTATUS -+gckHARDWARE_PrepareFunctions( -+ gckHARDWARE Hardware -+ ); -+ -+gceSTATUS -+gckHARDWARE_SetMMUStates( -+ IN gckHARDWARE Hardware, -+ IN gctPOINTER MtlbAddress, -+ IN gceMMU_MODE Mode, -+ IN gctPOINTER SafeAddress, -+ IN gctPOINTER Logical, -+ IN OUT gctUINT32 * Bytes -+ ); -+ -+#if !gcdENABLE_VG -+/******************************************************************************\ -+***************************** gckINTERRUPT Object ****************************** -+\******************************************************************************/ -+ -+typedef struct _gckINTERRUPT * gckINTERRUPT; -+ -+typedef gceSTATUS (* gctINTERRUPT_HANDLER)( -+ IN gckKERNEL Kernel -+ ); -+ -+gceSTATUS -+gckINTERRUPT_Construct( -+ IN gckKERNEL Kernel, -+ OUT gckINTERRUPT * Interrupt -+ ); -+ -+gceSTATUS -+gckINTERRUPT_Destroy( -+ IN gckINTERRUPT Interrupt -+ ); -+ -+gceSTATUS -+gckINTERRUPT_SetHandler( -+ IN gckINTERRUPT Interrupt, -+ IN OUT gctINT32_PTR Id, -+ IN gctINTERRUPT_HANDLER Handler -+ ); -+ -+gceSTATUS -+gckINTERRUPT_Notify( -+ IN gckINTERRUPT Interrupt, -+ IN gctBOOL Valid -+ ); -+#endif -+/******************************************************************************\ -+******************************** gckEVENT Object ******************************* -+\******************************************************************************/ -+ -+typedef struct _gckEVENT * gckEVENT; -+ -+/* Construct a new gckEVENT object. */ -+gceSTATUS -+gckEVENT_Construct( -+ IN gckKERNEL Kernel, -+ OUT gckEVENT * Event -+ ); -+ -+/* Destroy an gckEVENT object. */ -+gceSTATUS -+gckEVENT_Destroy( -+ IN gckEVENT Event -+ ); -+ -+/* Add a new event to the list of events. */ -+gceSTATUS -+gckEVENT_AddList( -+ IN gckEVENT Event, -+ IN gcsHAL_INTERFACE_PTR Interface, -+ IN gceKERNEL_WHERE FromWhere, -+ IN gctBOOL AllocateAllowed, -+ IN gctBOOL FromKernel -+ ); -+ -+/* Schedule a FreeNonPagedMemory event. */ -+gceSTATUS -+gckEVENT_FreeNonPagedMemory( -+ IN gckEVENT Event, -+ IN gctSIZE_T Bytes, -+ IN gctPHYS_ADDR Physical, -+ IN gctPOINTER Logical, -+ IN gceKERNEL_WHERE FromWhere -+ ); -+ -+/* Schedule a FreeContiguousMemory event. */ -+gceSTATUS -+gckEVENT_FreeContiguousMemory( -+ IN gckEVENT Event, -+ IN gctSIZE_T Bytes, -+ IN gctPHYS_ADDR Physical, -+ IN gctPOINTER Logical, -+ IN gceKERNEL_WHERE FromWhere -+ ); -+ -+/* Schedule a FreeVideoMemory event. */ -+gceSTATUS -+gckEVENT_FreeVideoMemory( -+ IN gckEVENT Event, -+ IN gcuVIDMEM_NODE_PTR VideoMemory, -+ IN gceKERNEL_WHERE FromWhere -+ ); -+ -+/* Schedule a signal event. */ -+gceSTATUS -+gckEVENT_Signal( -+ IN gckEVENT Event, -+ IN gctSIGNAL Signal, -+ IN gceKERNEL_WHERE FromWhere -+ ); -+ -+/* Schedule an Unlock event. */ -+gceSTATUS -+gckEVENT_Unlock( -+ IN gckEVENT Event, -+ IN gceKERNEL_WHERE FromWhere, -+ IN gctPOINTER Node, -+ IN gceSURF_TYPE Type -+ ); -+ -+gceSTATUS -+gckEVENT_CommitDone( -+ IN gckEVENT Event, -+ IN gceKERNEL_WHERE FromWhere -+ ); -+ -+/* Schedule a FreeVirtualCommandBuffer event. */ -+gceSTATUS -+gckEVENT_DestroyVirtualCommandBuffer( -+ IN gckEVENT Event, -+ IN gctSIZE_T Bytes, -+ IN gctPHYS_ADDR Physical, -+ IN gctPOINTER Logical, -+ IN gceKERNEL_WHERE FromWhere -+ ); -+ -+gceSTATUS -+gckEVENT_Submit( -+ IN gckEVENT Event, -+ IN gctBOOL Wait, -+ IN gctBOOL FromPower, -+ IN gctBOOL FromCommand -+ ); -+ -+gceSTATUS -+gckEVENT_Commit( -+ IN gckEVENT Event, -+ IN gcsQUEUE_PTR Queue -+ ); -+ -+/* Schedule a composition event. */ -+gceSTATUS -+gckEVENT_Compose( -+ IN gckEVENT Event, -+ IN gcsHAL_COMPOSE_PTR Info -+ ); -+ -+/* Event callback routine. */ -+gceSTATUS -+gckEVENT_Notify( -+ IN gckEVENT Event, -+ IN gctUINT32 IDs -+ ); -+ -+/* Event callback routine. */ -+gceSTATUS -+gckEVENT_Interrupt( -+ IN gckEVENT Event, -+ IN gctUINT32 IDs -+ ); -+ -+gceSTATUS -+gckEVENT_Dump( -+ IN gckEVENT Event -+ ); -+/******************************************************************************\ -+******************************* gckCOMMAND Object ****************************** -+\******************************************************************************/ -+ -+typedef struct _gckCOMMAND * gckCOMMAND; -+ -+/* Construct a new gckCOMMAND object. */ -+gceSTATUS -+gckCOMMAND_Construct( -+ IN gckKERNEL Kernel, -+ OUT gckCOMMAND * Command -+ ); -+ -+/* Destroy an gckCOMMAND object. */ -+gceSTATUS -+gckCOMMAND_Destroy( -+ IN gckCOMMAND Command -+ ); -+ -+/* Acquire command queue synchronization objects. */ -+gceSTATUS -+gckCOMMAND_EnterCommit( -+ IN gckCOMMAND Command, -+ IN gctBOOL FromPower -+ ); -+ -+/* Release command queue synchronization objects. */ -+gceSTATUS -+gckCOMMAND_ExitCommit( -+ IN gckCOMMAND Command, -+ IN gctBOOL FromPower -+ ); -+ -+/* Start the command queue. */ -+gceSTATUS -+gckCOMMAND_Start( -+ IN gckCOMMAND Command -+ ); -+ -+/* Stop the command queue. */ -+gceSTATUS -+gckCOMMAND_Stop( -+ IN gckCOMMAND Command, -+ IN gctBOOL FromRecovery -+ ); -+ -+gceSTATUS -+gckCOMMAND_Commit( -+ IN gckCOMMAND Command, -+ IN gckCONTEXT Context, -+ IN gcoCMDBUF CommandBuffer, -+ IN gcsSTATE_DELTA_PTR StateDelta, -+ IN gcsQUEUE_PTR EventQueue, -+ IN gctUINT32 ProcessID -+ ); -+ -+/* Reserve space in the command buffer. */ -+gceSTATUS -+gckCOMMAND_Reserve( -+ IN gckCOMMAND Command, -+ IN gctUINT32 RequestedBytes, -+ OUT gctPOINTER * Buffer, -+ OUT gctUINT32 * BufferSize -+ ); -+ -+/* Execute reserved space in the command buffer. */ -+gceSTATUS -+gckCOMMAND_Execute( -+ IN gckCOMMAND Command, -+ IN gctUINT32 RequstedBytes -+ ); -+ -+/* Stall the command queue. */ -+gceSTATUS -+gckCOMMAND_Stall( -+ IN gckCOMMAND Command, -+ IN gctBOOL FromPower -+ ); -+ -+/* Attach user process. */ -+gceSTATUS -+gckCOMMAND_Attach( -+ IN gckCOMMAND Command, -+ OUT gckCONTEXT * Context, -+ OUT gctSIZE_T * StateCount, -+ IN gctUINT32 ProcessID -+ ); -+ -+/* Detach user process. */ -+gceSTATUS -+gckCOMMAND_Detach( -+ IN gckCOMMAND Command, -+ IN gckCONTEXT Context -+ ); -+ -+/* Dump command buffer being executed by GPU. */ -+gceSTATUS -+gckCOMMAND_DumpExecutingBuffer( -+ IN gckCOMMAND Command -+ ); -+ -+/* Whether a kernel command buffer address. */ -+gceSTATUS -+gckCOMMAND_AddressInKernelCommandBuffer( -+ IN gckCOMMAND Command, -+ IN gctUINT32 Address, -+ OUT gctBOOL *In -+ ); -+ -+/******************************************************************************\ -+********************************* gckMMU Object ******************************** -+\******************************************************************************/ -+ -+typedef struct _gckMMU * gckMMU; -+ -+/* Construct a new gckMMU object. */ -+gceSTATUS -+gckMMU_Construct( -+ IN gckKERNEL Kernel, -+ IN gctSIZE_T MmuSize, -+ OUT gckMMU * Mmu -+ ); -+ -+/* Destroy an gckMMU object. */ -+gceSTATUS -+gckMMU_Destroy( -+ IN gckMMU Mmu -+ ); -+ -+/* Allocate pages inside the MMU. */ -+gceSTATUS -+gckMMU_AllocatePages( -+ IN gckMMU Mmu, -+ IN gctSIZE_T PageCount, -+ OUT gctPOINTER * PageTable, -+ OUT gctUINT32 * Address -+ ); -+ -+gceSTATUS -+gckMMU_AllocatePagesEx( -+ IN gckMMU Mmu, -+ IN gctSIZE_T PageCount, -+ IN gceSURF_TYPE Type, -+ OUT gctPOINTER * PageTable, -+ OUT gctUINT32 * Address -+ ); -+ -+/* Remove a page table from the MMU. */ -+gceSTATUS -+gckMMU_FreePages( -+ IN gckMMU Mmu, -+ IN gctPOINTER PageTable, -+ IN gctSIZE_T PageCount -+ ); -+ -+/* Set the MMU page with info. */ -+gceSTATUS -+gckMMU_SetPage( -+ IN gckMMU Mmu, -+ IN gctUINT32 PageAddress, -+ IN gctUINT32 *PageEntry -+ ); -+ -+gceSTATUS -+gckMMU_Flush( -+ IN gckMMU Mmu, -+ IN gceSURF_TYPE Type -+ ); -+ -+gceSTATUS -+gckMMU_DumpPageTableEntry( -+ IN gckMMU Mmu, -+ IN gctUINT32 Address -+ ); -+ -+ -+#if VIVANTE_PROFILER -+gceSTATUS -+gckHARDWARE_QueryProfileRegisters( -+ IN gckHARDWARE Hardware, -+ IN gctBOOL Reset, -+ OUT gcsPROFILER_COUNTERS * Counters -+ ); -+#endif -+ -+#if VIVANTE_PROFILER_CONTEXT -+gceSTATUS -+gckHARDWARE_QueryContextProfile( -+ IN gckHARDWARE Hardware, -+ IN gctBOOL Reset, -+ IN gckCONTEXT Context, -+ OUT gcsPROFILER_COUNTERS * Counters -+ ); -+ -+gceSTATUS -+gckHARDWARE_UpdateContextProfile( -+ IN gckHARDWARE Hardware, -+ IN gckCONTEXT Context -+ ); -+#endif -+ -+#if VIVANTE_PROFILER_NEW -+gceSTATUS -+gckHARDWARE_InitProfiler( -+ IN gckHARDWARE Hardware -+ ); -+#endif -+ -+gceSTATUS -+gckOS_SignalQueryHardware( -+ IN gckOS Os, -+ IN gctSIGNAL Signal, -+ OUT gckHARDWARE * Hardware -+ ); -+ -+gceSTATUS -+gckOS_SignalSetHardware( -+ IN gckOS Os, -+ IN gctSIGNAL Signal, -+ gckHARDWARE Hardware -+ ); -+ -+gceSTATUS -+gckOS_DetectProcessByName( -+ IN gctCONST_POINTER Name -+ ); -+ -+void -+gckOS_DumpParam( -+ void -+ ); -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#if gcdENABLE_VG -+#include "gc_hal_vg.h" -+#endif -+ -+#endif /* __gc_hal_h_ */ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_kernel_buffer.h linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_kernel_buffer.h ---- linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_kernel_buffer.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_kernel_buffer.h 2015-11-30 17:56:13.592136927 +0100 -@@ -0,0 +1,218 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#ifndef __gc_hal_kernel_buffer_h_ -+#define __gc_hal_kernel_buffer_h_ -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+/******************************************************************************\ -+************************ Command Buffer and Event Objects ********************** -+\******************************************************************************/ -+ -+/* The number of context buffers per user. */ -+#define gcdCONTEXT_BUFFER_COUNT 2 -+ -+/* State delta record. */ -+typedef struct _gcsSTATE_DELTA_RECORD * gcsSTATE_DELTA_RECORD_PTR; -+typedef struct _gcsSTATE_DELTA_RECORD -+{ -+ /* State address. */ -+ gctUINT address; -+ -+ /* State mask. */ -+ gctUINT32 mask; -+ -+ /* State data. */ -+ gctUINT32 data; -+} -+gcsSTATE_DELTA_RECORD; -+ -+/* State delta. */ -+typedef struct _gcsSTATE_DELTA -+{ -+ /* For debugging: the number of delta in the order of creation. */ -+#if gcmIS_DEBUG(gcdDEBUG_CODE) -+ gctUINT num; -+#endif -+ -+ /* Main state delta ID. Every time state delta structure gets reinitialized, -+ main ID is incremented. If main state ID overflows, all map entry IDs get -+ reinitialized to make sure there is no potential erroneous match after -+ the overflow.*/ -+ gctUINT id; -+ -+ /* The number of contexts pending modification by the delta. */ -+ gctINT refCount; -+ -+ /* Vertex element count for the delta buffer. */ -+ gctUINT elementCount; -+ -+ /* Number of states currently stored in the record array. */ -+ gctUINT recordCount; -+ -+ /* Record array; holds all modified states in gcsSTATE_DELTA_RECORD. */ -+ gctUINT64 recordArray; -+ -+ /* Map entry ID is used for map entry validation. If map entry ID does not -+ match the main state delta ID, the entry and the corresponding state are -+ considered not in use. */ -+ gctUINT64 mapEntryID; -+ gctUINT mapEntryIDSize; -+ -+ /* If the map entry ID matches the main state delta ID, index points to -+ the state record in the record array. */ -+ gctUINT64 mapEntryIndex; -+ -+ /* Previous and next state deltas in gcsSTATE_DELTA. */ -+ gctUINT64 prev; -+ gctUINT64 next; -+} -+gcsSTATE_DELTA; -+ -+/* Command buffer patch record. */ -+struct _gcsPATCH -+{ -+ /* Pointer within the buffer. */ -+ gctUINT32_PTR pointer; -+ -+ /* 32-bit data to write at the specified offset. */ -+ gctUINT32 data; -+}; -+ -+/* List of patches for the command buffer. */ -+struct _gcsPATCH_LIST -+{ -+ /* Array of patch records. */ -+ struct _gcsPATCH patch[1024]; -+ -+ /* Number of patches in the array. */ -+ gctUINT count; -+ -+ /* Next item in the list. */ -+ struct _gcsPATCH_LIST *next; -+}; -+ -+/* Command buffer object. */ -+struct _gcoCMDBUF -+{ -+ /* The object. */ -+ gcsOBJECT object; -+ -+ /* Commit count. */ -+ gctUINT count; -+ -+ /* Command buffer entry and exit pipes. */ -+ gcePIPE_SELECT entryPipe; -+ gcePIPE_SELECT exitPipe; -+ -+ /* Feature usage flags. */ -+ gctBOOL using2D; -+ gctBOOL using3D; -+ gctBOOL usingFilterBlit; -+ gctBOOL usingPalette; -+ -+ /* Physical address of command buffer. Just a name. */ -+ gctUINT32 physical; -+ -+ /* Logical address of command buffer. */ -+ gctUINT64 logical; -+ -+ /* Number of bytes in command buffer. */ -+ gctUINT32 bytes; -+ -+ /* Start offset into the command buffer. */ -+ gctUINT32 startOffset; -+ -+ /* Current offset into the command buffer. */ -+ gctUINT32 offset; -+ -+ /* Number of free bytes in command buffer. */ -+ gctUINT32 free; -+ -+ /* Location of the last reserved area. */ -+ gctUINT64 lastReserve; -+ gctUINT32 lastOffset; -+ -+#if gcmIS_DEBUG(gcdDEBUG_CODE) -+ /* Last load state command location and hardware address. */ -+ gctUINT64 lastLoadStatePtr; -+ gctUINT32 lastLoadStateAddress; -+ gctUINT32 lastLoadStateCount; -+#endif -+ -+ /* Completion signal. */ -+ gctSIGNAL signal; -+ -+ /* List of patches. */ -+ struct _gcsPATCH_LIST *patchHead; -+ struct _gcsPATCH_LIST *patchTail; -+ -+ /* Link to the siblings. */ -+ gcoCMDBUF prev; -+ gcoCMDBUF next; -+}; -+ -+typedef struct _gcsQUEUE -+{ -+ /* Pointer to next gcsQUEUE structure in gcsQUEUE. */ -+ gctUINT64 next; -+ -+ /* Event information. */ -+ gcsHAL_INTERFACE iface; -+} -+gcsQUEUE; -+ -+/* Event queue. */ -+struct _gcoQUEUE -+{ -+ /* The object. */ -+ gcsOBJECT object; -+ -+ /* Pointer to current event queue. */ -+ gcsQUEUE_PTR head; -+ gcsQUEUE_PTR tail; -+ -+ /* chunks of the records. */ -+ gctPOINTER chunks; -+ -+ /* List of free records. */ -+ gcsQUEUE_PTR freeList; -+ -+ #define gcdIN_QUEUE_RECORD_LIMIT 16 -+ /* Number of records currently in queue */ -+ gctUINT32 recordCount; -+}; -+ -+struct _gcsTEMPCMDBUF -+{ -+ gctUINT32 currentByteSize; -+ gctPOINTER buffer; -+ gctBOOL inUse; -+}; -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* __gc_hal_kernel_buffer_h_ */ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_mem.h linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_mem.h ---- linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_mem.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_mem.h 2015-11-30 17:56:13.592136927 +0100 -@@ -0,0 +1,530 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+/* -+** Include file for the local memory management. -+*/ -+ -+#ifndef __gc_hal_mem_h_ -+#define __gc_hal_mem_h_ -+#if (gcdENABLE_3D || gcdENABLE_VG) -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+/******************************************************************************* -+** Usage: -+ -+ The macros to declare MemPool type and functions are -+ gcmMEM_DeclareFSMemPool (Type, TypeName, Prefix) -+ gcmMEM_DeclareVSMemPool (Type, TypeName, Prefix) -+ gcmMEM_DeclareAFSMemPool(Type, TypeName, Prefix) -+ -+ The data structures for MemPool are -+ typedef struct _gcsMEM_FS_MEM_POOL * gcsMEM_FS_MEM_POOL; -+ typedef struct _gcsMEM_VS_MEM_POOL * gcsMEM_VS_MEM_POOL; -+ typedef struct _gcsMEM_AFS_MEM_POOL * gcsMEM_AFS_MEM_POOL; -+ -+ The MemPool constructor and destructor functions are -+ gcfMEM_InitFSMemPool(gcsMEM_FS_MEM_POOL *, gcoOS, gctUINT, gctUINT); -+ gcfMEM_FreeFSMemPool(gcsMEM_FS_MEM_POOL *); -+ gcfMEM_InitVSMemPool(gcsMEM_VS_MEM_POOL *, gcoOS, gctUINT, gctBOOL); -+ gcfMEM_FreeVSMemPool(gcsMEM_VS_MEM_POOL *); -+ gcfMEM_InitAFSMemPool(gcsMEM_AFS_MEM_POOL *, gcoOS, gctUINT); -+ gcfMEM_FreeAFSMemPool(gcsMEM_AFS_MEM_POOL *); -+ -+ FS: for Fixed-Size data structures -+ VS: for Variable-size data structures -+ AFS: for Array of Fixed-Size data structures -+ -+ -+ // Example 1: For a fixed-size data structure, struct gcsNode. -+ // It is used locally in a file, so the functions are static without prefix. -+ // At top level, declear allocate and free functions. -+ // The first argument is the data type. -+ // The second armument is the short name used in the fuctions. -+ gcmMEM_DeclareFSMemPool(struct gcsNode, Node, ); -+ -+ // The previous macro creates two inline functions, -+ // _AllocateNode and _FreeNode. -+ -+ // In function or struct -+ gcsMEM_FS_MEM_POOL nodeMemPool; -+ -+ // In function, -+ struct gcsNode * node; -+ gceSTATUS status; -+ -+ // Before using the memory pool, initialize it. -+ // The second argument is the gcoOS object. -+ // The third argument is the number of data structures to allocate for each chunk. -+ status = gcfMEM_InitFSMemPool(&nodeMemPool, os, 100, sizeof(struct gcsNode)); -+ ... -+ -+ // Allocate a node. -+ status = _AllocateNode(nodeMemPool, &node); -+ ... -+ // Free a node. -+ _FreeNode(nodeMemPool, node); -+ -+ // After using the memory pool, free it. -+ gcfMEM_FreeFSMemPool(&nodeMemPool); -+ -+ -+ // Example 2: For array of fixed-size data structures, struct gcsNode. -+ // It is used in several files, so the functions are extern with prefix. -+ // At top level, declear allocate and free functions. -+ // The first argument is the data type, and the second one is the short name -+ // used in the fuctions. -+ gcmMEM_DeclareAFSMemPool(struct gcsNode, NodeArray, gcfOpt); -+ -+ // The previous macro creates two inline functions, -+ // gcfOpt_AllocateNodeArray and gcfOpt_FreeNodeArray. -+ -+ // In function or struct -+ gcsMEM_AFS_MEM_POOL nodeArrayMemPool; -+ -+ // In function, -+ struct gcsNode * nodeArray; -+ gceSTATUS status; -+ -+ // Before using the array memory pool, initialize it. -+ // The second argument is the gcoOS object, the third is the number of data -+ // structures to allocate for each chunk. -+ status = gcfMEM_InitAFSMemPool(&nodeArrayMemPool, os, sizeof(struct gcsNode)); -+ ... -+ -+ // Allocate a node array of size 100. -+ status = gcfOpt_AllocateNodeArray(nodeArrayMemPool, &nodeArray, 100); -+ ... -+ // Free a node array. -+ gcfOpt_FreeNodeArray(&nodeArrayMemPool, nodeArray); -+ -+ // After using the array memory pool, free it. -+ gcfMEM_FreeAFSMemPool(&nodeArrayMemPool); -+ -+*******************************************************************************/ -+ -+/******************************************************************************* -+** To switch back to use gcoOS_Allocate and gcoOS_Free, add -+** #define USE_LOCAL_MEMORY_POOL 0 -+** before including this file. -+*******************************************************************************/ -+#ifndef USE_LOCAL_MEMORY_POOL -+/* -+ USE_LOCAL_MEMORY_POOL -+ -+ This define enables the local memory management to improve performance. -+*/ -+#define USE_LOCAL_MEMORY_POOL 1 -+#endif -+ -+/******************************************************************************* -+** Memory Pool Data Structures -+*******************************************************************************/ -+#if USE_LOCAL_MEMORY_POOL -+ typedef struct _gcsMEM_FS_MEM_POOL * gcsMEM_FS_MEM_POOL; -+ typedef struct _gcsMEM_VS_MEM_POOL * gcsMEM_VS_MEM_POOL; -+ typedef struct _gcsMEM_AFS_MEM_POOL * gcsMEM_AFS_MEM_POOL; -+#else -+ typedef gcoOS gcsMEM_FS_MEM_POOL; -+ typedef gcoOS gcsMEM_VS_MEM_POOL; -+ typedef gcoOS gcsMEM_AFS_MEM_POOL; -+#endif -+ -+/******************************************************************************* -+** Memory Pool Macros -+*******************************************************************************/ -+#if USE_LOCAL_MEMORY_POOL -+#define gcmMEM_DeclareFSMemPool(Type, TypeName, Prefix) \ -+gceSTATUS \ -+Prefix##_Allocate##TypeName( \ -+ gcsMEM_FS_MEM_POOL MemPool, \ -+ Type ** Pointer \ -+ ) \ -+{ \ -+ return(gcfMEM_FSMemPoolGetANode(MemPool, (gctPOINTER *) Pointer)); \ -+} \ -+ \ -+gceSTATUS \ -+Prefix##_CAllocate##TypeName( \ -+ gcsMEM_FS_MEM_POOL MemPool, \ -+ Type ** Pointer \ -+ ) \ -+{ \ -+ gceSTATUS status; \ -+ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \ -+ gcmERR_RETURN(gcfMEM_FSMemPoolGetANode(MemPool, (gctPOINTER *) Pointer)); \ -+ gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, gcmSIZEOF(Type)); \ -+ gcmFOOTER(); \ -+ return gcvSTATUS_OK; \ -+} \ -+ \ -+gceSTATUS \ -+Prefix##_Free##TypeName( \ -+ gcsMEM_FS_MEM_POOL MemPool, \ -+ Type * Pointer \ -+ ) \ -+{ \ -+ gceSTATUS status; \ -+ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \ -+ status = gcfMEM_FSMemPoolFreeANode(MemPool, (gctPOINTER) Pointer); \ -+ gcmFOOTER(); \ -+ return status; \ -+} \ -+ \ -+gceSTATUS \ -+Prefix##_Free##TypeName##List( \ -+ gcsMEM_FS_MEM_POOL MemPool, \ -+ Type * FirstPointer, \ -+ Type * LastPointer \ -+ ) \ -+{ \ -+ gceSTATUS status; \ -+ gcmHEADER_ARG("MemPool=0x%x FirstPointer=0x%x LastPointer=0x%x", MemPool, FirstPointer, LastPointer); \ -+ status = gcfMEM_FSMemPoolFreeAList(MemPool, (gctPOINTER) FirstPointer, (gctPOINTER) LastPointer); \ -+ gcmFOOTER(); \ -+ return status; \ -+} -+ -+#define gcmMEM_DeclareVSMemPool(Type, TypeName, Prefix) \ -+gceSTATUS \ -+Prefix##_Allocate##TypeName( \ -+ gcsMEM_FS_MEM_POOL MemPool, \ -+ Type ** Pointer, \ -+ gctUINT Size \ -+ ) \ -+{ \ -+ gceSTATUS status;\ -+ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Size=%u", MemPool, Pointer, Size); \ -+ status = gcfMEM_VSMemPoolGetANode(MemPool, Size, (gctPOINTER *) Pointer); \ -+ gcmFOOTER(); \ -+ return status; \ -+} \ -+ \ -+gceSTATUS \ -+ Prefix##_CAllocate##TypeName( \ -+ gcsMEM_FS_MEM_POOL MemPool, \ -+ Type ** Pointer, \ -+ gctUINT Size \ -+ ) \ -+{ \ -+ gceSTATUS status; \ -+ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Size=%u", MemPool, Pointer, Size); \ -+ gcmERR_RETURN(gcfMEM_VSMemPoolGetANode(MemPool, Size, (gctPOINTER *) Pointer)); \ -+ gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, size); \ -+ gcmFOOTER(); \ -+ return gcvSTATUS_OK; \ -+} \ -+ \ -+gceSTATUS \ -+Prefix##_Free##TypeName( \ -+ gcsMEM_FS_MEM_POOL MemPool, \ -+ Type * Pointer \ -+ ) \ -+{ \ -+ gceSTATUS status; \ -+ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pinter); \ -+ status = gcfMEM_VSMemPoolFreeANode(MemPool, (gctPOINTER) Pointer); \ -+ gcmFOOTER(); \ -+ return status; \ -+} -+ -+#define gcmMEM_DeclareAFSMemPool(Type, TypeName, Prefix) \ -+gceSTATUS \ -+Prefix##_Allocate##TypeName( \ -+ gcsMEM_AFS_MEM_POOL MemPool, \ -+ Type ** Pointer, \ -+ gctUINT Count \ -+ ) \ -+{ \ -+ gceSTATUS status; \ -+ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Count=%u", MemPool, Pointer, Count); \ -+ status = gcfMEM_AFSMemPoolGetANode(MemPool, Count, (gctPOINTER *) Pointer); \ -+ gcmFOOTER(); \ -+ return status; \ -+} \ -+ \ -+gceSTATUS \ -+Prefix##_CAllocate##TypeName( \ -+ gcsMEM_AFS_MEM_POOL MemPool, \ -+ Type ** Pointer, \ -+ gctUINT Count \ -+ ) \ -+{ \ -+ gceSTATUS status; \ -+ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Count=%u", MemPool, Pointer, Count); \ -+ gcmERR_RETURN(gcfMEM_AFSMemPoolGetANode(MemPool, Count, (gctPOINTER *) Pointer)); \ -+ gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, Count * gcmSIZEOF(Type)); \ -+ gcmFOOTER(); \ -+ return gcvSTATUS_OK; \ -+} \ -+ \ -+gceSTATUS \ -+Prefix##_Free##TypeName( \ -+ gcsMEM_AFS_MEM_POOL MemPool, \ -+ Type * Pointer \ -+ ) \ -+{ \ -+ gceSTATUS status; \ -+ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \ -+ status = gcfMEM_AFSMemPoolFreeANode(MemPool, (gctPOINTER) Pointer); \ -+ gcmFOOTER(); \ -+ return status; \ -+} -+ -+#else -+ -+#define gcmMEM_DeclareFSMemPool(Type, TypeName, Prefix) \ -+gceSTATUS \ -+Prefix##_Allocate##TypeName( \ -+ gcsMEM_FS_MEM_POOL MemPool, \ -+ Type ** Pointer \ -+ ) \ -+{ \ -+ gceSTATUS status; \ -+ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \ -+ status = gcoOS_Allocate(MemPool, \ -+ gcmSIZEOF(Type), \ -+ (gctPOINTER *) Pointer); \ -+ gcmFOOTER(); \ -+ return status; \ -+} \ -+ \ -+gceSTATUS \ -+Prefix##_CAllocate##TypeName( \ -+ gcsMEM_FS_MEM_POOL MemPool, \ -+ Type ** Pointer \ -+ ) \ -+{ \ -+ gceSTATUS status; \ -+ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \ -+ gcmERR_RETURN(gcoOS_Allocate(MemPool, \ -+ gcmSIZEOF(Type), \ -+ (gctPOINTER *) Pointer)); \ -+ gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, gcmSIZEOF(Type)); \ -+ gcmFOOTER(); \ -+ return gcvSTATUS_OK; \ -+} \ -+ \ -+gceSTATUS \ -+Prefix##_Free##TypeName( \ -+ gcsMEM_FS_MEM_POOL MemPool, \ -+ Type * Pointer \ -+ ) \ -+{ \ -+ gceSTATUS status; \ -+ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \ -+ status = gcmOS_SAFE_FREE(MemPool, Pointer); \ -+ gcmFOOTER(); \ -+ return status; \ -+} -+ -+#define gcmMEM_DeclareVSMemPool(Type, TypeName, Prefix) \ -+gceSTATUS \ -+Prefix##_Allocate##TypeName( \ -+ gcsMEM_VS_MEM_POOL MemPool, \ -+ Type ** Pointer, \ -+ gctUINT Size \ -+ ) \ -+{ \ -+ gceSTATUS status; \ -+ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Size=%u", MemPool, Pointer, Size); \ -+ status = gcoOS_Allocate(MemPool, \ -+ Size, \ -+ (gctPOINTER *) Pointer); \ -+ gcmFOOTER(); \ -+ return status; \ -+} \ -+ \ -+gceSTATUS \ -+Prefix##_CAllocate##TypeName( \ -+ gcsMEM_VS_MEM_POOL MemPool, \ -+ Type ** Pointer, \ -+ gctUINT Size \ -+ ) \ -+{ \ -+ gceSTATUS status; \ -+ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Size=%u", MemPool, Pointer, Size); \ -+ gcmERR_RETURN(gcoOS_Allocate(MemPool, \ -+ Size, \ -+ (gctPOINTER *) Pointer)); \ -+ gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, Size); \ -+ gcmFOOTER(); \ -+ return gcvSTATUS_OK; \ -+} \ -+ \ -+gceSTATUS \ -+Prefix##_Free##TypeName( \ -+ gcsMEM_VS_MEM_POOL MemPool, \ -+ Type * Pointer \ -+ ) \ -+{ \ -+ gceSTATUS status; \ -+ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \ -+ status = gcmOS_SAFE_FREE(MemPool, Pointer); \ -+ gcmFOOTER(); \ -+ return status; \ -+} -+ -+#define gcmMEM_DeclareAFSMemPool(Type, TypeName, Prefix) \ -+gceSTATUS \ -+Prefix##_Allocate##TypeName( \ -+ gcsMEM_AFS_MEM_POOL MemPool, \ -+ Type ** Pointer, \ -+ gctUINT Count \ -+ ) \ -+{ \ -+ gceSTATUS status; \ -+ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Count=%u", MemPool, Pointer, Count); \ -+ status = gcoOS_Allocate(MemPool, \ -+ Count * gcmSIZEOF(Type), \ -+ (gctPOINTER *) Pointer); \ -+ gcmFOOTER(); \ -+ return status; \ -+} \ -+ \ -+gceSTATUS \ -+Prefix##_CAllocate##TypeName( \ -+ gcsMEM_AFS_MEM_POOL MemPool, \ -+ Type ** Pointer, \ -+ gctUINT Count \ -+ ) \ -+{ \ -+ gceSTATUS status; \ -+ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x Count=%u", MemPool, Pointer, Count); \ -+ gcmERR_RETURN(gcoOS_Allocate(MemPool, \ -+ Count * gcmSIZEOF(Type), \ -+ (gctPOINTER *) Pointer)); \ -+ gcoOS_ZeroMemory(*(gctPOINTER *) Pointer, Count * gcmSIZEOF(Type)); \ -+ gcmFOOTER(); \ -+ return gcvSTATUS_OK; \ -+} \ -+ \ -+gceSTATUS \ -+Prefix##_Free##TypeName( \ -+ gcsMEM_AFS_MEM_POOL MemPool, \ -+ Type * Pointer \ -+ ) \ -+{ \ -+ gceSTATUS status; \ -+ gcmHEADER_ARG("MemPool=0x%x Pointer=0x%x", MemPool, Pointer); \ -+ status = gcmOS_SAFE_FREE(MemPool, Pointer); \ -+ gcmFOOTER(); \ -+ return status; \ -+} -+#endif -+ -+/******************************************************************************* -+** Memory Pool Data Functions -+*******************************************************************************/ -+gceSTATUS -+gcfMEM_InitFSMemPool( -+ IN gcsMEM_FS_MEM_POOL * MemPool, -+ IN gcoOS OS, -+ IN gctUINT NodeCount, -+ IN gctUINT NodeSize -+ ); -+ -+gceSTATUS -+gcfMEM_FreeFSMemPool( -+ IN gcsMEM_FS_MEM_POOL * MemPool -+ ); -+ -+gceSTATUS -+gcfMEM_FSMemPoolGetANode( -+ IN gcsMEM_FS_MEM_POOL MemPool, -+ OUT gctPOINTER * Node -+ ); -+ -+gceSTATUS -+gcfMEM_FSMemPoolFreeANode( -+ IN gcsMEM_FS_MEM_POOL MemPool, -+ IN gctPOINTER Node -+ ); -+ -+gceSTATUS -+gcfMEM_FSMemPoolFreeAList( -+ IN gcsMEM_FS_MEM_POOL MemPool, -+ IN gctPOINTER FirstNode, -+ IN gctPOINTER LastNode -+ ); -+ -+gceSTATUS -+gcfMEM_InitVSMemPool( -+ IN gcsMEM_VS_MEM_POOL * MemPool, -+ IN gcoOS OS, -+ IN gctUINT BlockSize, -+ IN gctBOOL RecycleFreeNode -+ ); -+ -+gceSTATUS -+gcfMEM_FreeVSMemPool( -+ IN gcsMEM_VS_MEM_POOL * MemPool -+ ); -+ -+gceSTATUS -+gcfMEM_VSMemPoolGetANode( -+ IN gcsMEM_VS_MEM_POOL MemPool, -+ IN gctUINT Size, -+ IN gctUINT Alignment, -+ OUT gctPOINTER * Node -+ ); -+ -+gceSTATUS -+gcfMEM_VSMemPoolFreeANode( -+ IN gcsMEM_VS_MEM_POOL MemPool, -+ IN gctPOINTER Node -+ ); -+ -+gceSTATUS -+gcfMEM_InitAFSMemPool( -+ IN gcsMEM_AFS_MEM_POOL *MemPool, -+ IN gcoOS OS, -+ IN gctUINT NodeCount, -+ IN gctUINT NodeSize -+ ); -+ -+gceSTATUS -+gcfMEM_FreeAFSMemPool( -+ IN gcsMEM_AFS_MEM_POOL *MemPool -+ ); -+ -+gceSTATUS -+gcfMEM_AFSMemPoolGetANode( -+ IN gcsMEM_AFS_MEM_POOL MemPool, -+ IN gctUINT Count, -+ OUT gctPOINTER * Node -+ ); -+ -+gceSTATUS -+gcfMEM_AFSMemPoolFreeANode( -+ IN gcsMEM_AFS_MEM_POOL MemPool, -+ IN gctPOINTER Node -+ ); -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* (gcdENABLE_3D || gcdENABLE_VG) */ -+#endif /* __gc_hal_mem_h_ */ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_options.h linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_options.h ---- linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_options.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_options.h 2015-11-30 17:56:13.592136927 +0100 -@@ -0,0 +1,1194 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+#ifndef __gc_hal_options_h_ -+#define __gc_hal_options_h_ -+ -+/* -+ gcdPRINT_VERSION -+ -+ Print HAL version. -+*/ -+#ifndef gcdPRINT_VERSION -+# define gcdPRINT_VERSION 0 -+#endif -+ -+/* -+ VIVANTE_PROFILER -+ -+ This define enables the profiler. -+*/ -+#ifndef VIVANTE_PROFILER -+# define VIVANTE_PROFILER 1 -+#endif -+ -+/* -+ VIVANTE_PROFILER_CONTEXT -+ -+ This define enables the profiler according each context. -+*/ -+#ifndef VIVANTE_PROFILER_CONTEXT -+# define VIVANTE_PROFILER_CONTEXT 1 -+#endif -+ -+#ifndef VIVANTE_PROFILER_PERDRAW -+# define VIVANTE_PROFILER_PERDRAW 0 -+#endif -+ -+#ifndef VIVANTE_PROFILER_NEW -+# define VIVANTE_PROFILER_NEW 0 -+#endif -+ -+#ifndef VIVANTE_PROFILER_PM -+# define VIVANTE_PROFILER_PM 1 -+#endif -+/* -+ gcdUSE_VG -+ -+ Enable VG HAL layer (only for GC350). -+*/ -+#ifndef gcdUSE_VG -+# define gcdUSE_VG 0 -+#endif -+ -+/* -+ USE_SW_FB -+ -+ Set to 1 if the frame buffer memory cannot be accessed by the GPU. -+*/ -+#ifndef USE_SW_FB -+# define USE_SW_FB 0 -+#endif -+ -+/* -+ PROFILE_HAL_COUNTERS -+ -+ This define enables HAL counter profiling support. HW and SHADER -+ counter profiling depends on this. -+*/ -+#ifndef PROFILE_HAL_COUNTERS -+# define PROFILE_HAL_COUNTERS 1 -+#endif -+ -+/* -+ PROFILE_HW_COUNTERS -+ -+ This define enables HW counter profiling support. -+*/ -+#ifndef PROFILE_HW_COUNTERS -+# define PROFILE_HW_COUNTERS 1 -+#endif -+ -+/* -+ PROFILE_SHADER_COUNTERS -+ -+ This define enables SHADER counter profiling support. -+*/ -+#ifndef PROFILE_SHADER_COUNTERS -+# define PROFILE_SHADER_COUNTERS 1 -+#endif -+ -+/* -+ gcdDUMP_KEY -+ -+ Set this to a string that appears in 'cat /proc//cmdline'. E.g. 'camera'. -+ HAL will create dumps for the processes matching this key. -+*/ -+#ifndef gcdDUMP_KEY -+# define gcdDUMP_KEY "process" -+#endif -+ -+/* -+ gcdDUMP_PATH -+ -+ The dump file location. Some processes cannot write to the sdcard. -+ Try apps' data dir, e.g. /data/data/com.android.launcher -+*/ -+#ifndef gcdDUMP_PATH -+#if defined(ANDROID) -+# define gcdDUMP_PATH "/mnt/sdcard/" -+#else -+# define gcdDUMP_PATH "./" -+#endif -+#endif -+ -+/* -+ gcdDUMP -+ -+ When set to 1, a dump of all states and memory uploads, as well as other -+ hardware related execution will be printed to the debug console. This -+ data can be used for playing back applications. -+*/ -+#ifndef gcdDUMP -+# define gcdDUMP 0 -+#endif -+ -+/* -+ gcdDUMP_API -+ -+ When set to 1, a high level dump of the EGL and GL/VG APs's are -+ captured. -+*/ -+#ifndef gcdDUMP_API -+# define gcdDUMP_API 0 -+#endif -+ -+ -+ -+/* -+ gcdDEBUG_OPTION -+ When set to 1, the debug options are enabled. We must set other MACRO to enable -+ sub case. -+*/ -+#ifndef gcdDEBUG_OPTION -+# define gcdDEBUG_OPTION 0 -+ -+#if gcdDEBUG_OPTION -+/* -+ gcdDEBUG_OPTION_KEY -+ The process name of debug application. -+*/ -+#ifndef gcdDEBUG_OPTION_KEY -+# define gcdDEBUG_OPTION_KEY "process" -+# endif -+/* -+ gcdDEBUG_OPTION_NO_GL_DRAWS -+ When set to 1, all glDrawArrays and glDrawElements will be skip. -+*/ -+#ifndef gcdDEBUG_OPTION_NO_GL_DRAWS -+# define gcdDEBUG_OPTION_NO_GL_DRAWS 0 -+# endif -+/* -+ gcdDEBUG_OPTION_NO_DRAW_PRIMITIVES -+ When set to 1, all DrawPrimitives will be skip. -+*/ -+#ifndef gcdDEBUG_OPTION_NO_DRAW_PRIMITIVES -+# define gcdDEBUG_OPTION_NO_DRAW_PRIMITIVES 0 -+# endif -+/* -+ gcdDEBUG_OPTION_SKIP_SWAP -+ When set to 1, just one out of gcdDEBUG_OPTION_SKIP_FRAMES(such as 1/10) eglSwapBuffers will be resolve, -+ others skip. -+*/ -+#ifndef gcdDEBUG_OPTION_SKIP_SWAP -+# define gcdDEBUG_OPTION_SKIP_SWAP 0 -+# define gcdDEBUG_OPTION_SKIP_FRAMES 10 -+# endif -+/* -+ gcdDEBUG_OPTION_FORCE_16BIT_RENDER_TARGET -+ When set to 1, the format of render target will force to RGB565. -+*/ -+#ifndef gcdDEBUG_OPTION_FORCE_16BIT_RENDER_TARGET -+# define gcdDEBUG_OPTION_FORCE_16BIT_RENDER_TARGET 0 -+# endif -+/* -+ gcdDEBUG_OPTION_NONE_TEXTURE -+ When set to 1, the type of texture will be set to AQ_TEXTURE_SAMPLE_MODE_TYPE_NONE. -+*/ -+#ifndef gcdDEBUG_OPTION_NONE_TEXTURE -+# define gcdDEBUG_OPTION_NONE_TEXTURE 0 -+# endif -+/* -+ gcdDEBUG_OPTION_NONE_DEPTH -+ When set to 1, the depth format of surface will be set to gcvSURF_UNKNOWN. -+*/ -+#ifndef gcdDEBUG_OPTION_NONE_DEPTH -+# define gcdDEBUG_OPTION_NONE_DEPTH 0 -+# endif -+ -+# endif -+#endif -+ -+/* -+ gcdDUMP_SWAP_PER_DRAW -+ -+ When set to 1, dump swap command for every single draw to make simulation comparison happy. -+ Only valid for ES3 driver for now. -+*/ -+#ifndef gcdDUMP_SWAP_PER_DRAW -+# define gcdDUMP_SWAP_PER_DRAW 0 -+#endif -+ -+/* -+ gcdDUMP_FRAMERATE -+ When set to a value other than zero, averaqe frame rate will be dumped. -+ The value set is the starting frame that the average will be calculated. -+ This is needed because sometimes first few frames are too slow to be included -+ in the average. Frame count starts from 1. -+*/ -+#ifndef gcdDUMP_FRAMERATE -+# define gcdDUMP_FRAMERATE 0 -+#endif -+ -+/* -+ gcdENABLE_FSCALE_VAL_ADJUST -+ When non-zero, FSCALE_VAL when gcvPOWER_ON can be adjusted externally. -+ */ -+#ifndef gcdENABLE_FSCALE_VAL_ADJUST -+# define gcdENABLE_FSCALE_VAL_ADJUST 1 -+#endif -+ -+/* -+ gcdDUMP_IN_KERNEL -+ -+ When set to 1, all dumps will happen in the kernel. This is handy if -+ you want the kernel to dump its command buffers as well and the data -+ needs to be in sync. -+*/ -+#ifndef gcdDUMP_IN_KERNEL -+# define gcdDUMP_IN_KERNEL 0 -+#endif -+ -+/* -+ gcdDUMP_COMMAND -+ -+ When set to non-zero, the command queue will dump all incoming command -+ and context buffers as well as all other modifications to the command -+ queue. -+*/ -+#ifndef gcdDUMP_COMMAND -+# define gcdDUMP_COMMAND 0 -+#endif -+ -+/* -+ gcdDUMP_2D -+ -+ When set to non-zero, it will dump the 2D command and surface. -+*/ -+#ifndef gcdDUMP_2D -+# define gcdDUMP_2D 0 -+#endif -+ -+/* -+ gcdDUMP_FRAME_TGA -+ -+ When set to a value other than 0, a dump of the frame specified by the value, -+ will be done into frame.tga. Frame count starts from 1. -+ */ -+#ifndef gcdDUMP_FRAME_TGA -+# define gcdDUMP_FRAME_TGA 0 -+#endif -+/* -+ gcdNULL_DRIVER -+ -+ Set to 1 for infinite speed hardware. -+ Set to 2 for bypassing the HAL. -+ Set to 3 for bypassing the drivers. -+*/ -+#ifndef gcdNULL_DRIVER -+# define gcdNULL_DRIVER 0 -+#endif -+ -+/* -+ gcdENABLE_TIMEOUT_DETECTION -+ -+ Enable timeout detection. -+*/ -+#ifndef gcdENABLE_TIMEOUT_DETECTION -+# define gcdENABLE_TIMEOUT_DETECTION 0 -+#endif -+ -+/* -+ gcdCMD_BUFFER_SIZE -+ -+ Number of bytes in a command buffer. -+*/ -+#ifndef gcdCMD_BUFFER_SIZE -+# define gcdCMD_BUFFER_SIZE (128 << 10) -+#endif -+ -+/* -+ gcdCMD_BUFFERS -+ -+ Number of command buffers to use per client. -+*/ -+#ifndef gcdCMD_BUFFERS -+# define gcdCMD_BUFFERS 2 -+#endif -+ -+/* -+ gcdMAX_CMD_BUFFERS -+ -+ Maximum number of command buffers to use per client. -+*/ -+#ifndef gcdMAX_CMD_BUFFERS -+# define gcdMAX_CMD_BUFFERS 8 -+#endif -+ -+/* -+ gcdCOMMAND_QUEUES -+ -+ Number of command queues in the kernel. -+*/ -+#ifndef gcdCOMMAND_QUEUES -+# define gcdCOMMAND_QUEUES 2 -+#endif -+ -+/* -+ gcdPOWER_CONTROL_DELAY -+ -+ The delay in milliseconds required to wait until the GPU has woke up -+ from a suspend or power-down state. This is system dependent because -+ the bus clock also needs to stabalize. -+*/ -+#ifndef gcdPOWER_CONTROL_DELAY -+# define gcdPOWER_CONTROL_DELAY 0 -+#endif -+ -+/* -+ gcdMIRROR_PAGETABLE -+ -+ Enable it when GPUs with old MMU and new MMU exist at same SoC. It makes -+ each GPU use same virtual address to access same physical memory. -+*/ -+#ifndef gcdMIRROR_PAGETABLE -+# define gcdMIRROR_PAGETABLE 0 -+#endif -+ -+/* -+ gcdMMU_SIZE -+ -+ Size of the MMU page table in bytes. Each 4 bytes can hold 4kB worth of -+ virtual data. -+*/ -+#ifndef gcdMMU_SIZE -+#if gcdMIRROR_PAGETABLE -+# define gcdMMU_SIZE 0x200000 -+#else -+# define gcdMMU_SIZE (2048 << 10) -+#endif -+#endif -+ -+/* -+ gcdSECURE_CACHE_SLOTS -+ -+ Number of slots in the logical to DMA address cache table. Each time a -+ logical address needs to be translated into a DMA address for the GPU, -+ this cache will be walked. The replacement scheme is LRU. -+*/ -+#ifndef gcdSECURE_CACHE_SLOTS -+# define gcdSECURE_CACHE_SLOTS 1024 -+#endif -+ -+/* -+ gcdSECURE_CACHE_METHOD -+ -+ Replacement scheme used for Secure Cache. The following options are -+ available: -+ -+ gcdSECURE_CACHE_LRU -+ A standard LRU cache. -+ -+ gcdSECURE_CACHE_LINEAR -+ A linear walker with the idea that an application will always -+ render the scene in a similar way, so the next entry in the -+ cache should be a hit most of the time. -+ -+ gcdSECURE_CACHE_HASH -+ A 256-entry hash table. -+ -+ gcdSECURE_CACHE_TABLE -+ A simple cache but with potential of a lot of cache replacement. -+*/ -+#ifndef gcdSECURE_CACHE_METHOD -+# define gcdSECURE_CACHE_METHOD gcdSECURE_CACHE_HASH -+#endif -+ -+/* -+ gcdREGISTER_ACCESS_FROM_USER -+ -+ Set to 1 to allow IOCTL calls to get through from user land. This -+ should only be in debug or development drops. -+*/ -+#ifndef gcdREGISTER_ACCESS_FROM_USER -+# define gcdREGISTER_ACCESS_FROM_USER 1 -+#endif -+ -+/* -+ gcdHEAP_SIZE -+ -+ Set the allocation size for the internal heaps. Each time a heap is -+ full, a new heap will be allocated with this minmimum amount of bytes. -+ The bigger this size, the fewer heaps there are to allocate, the better -+ the performance. However, heaps won't be freed until they are -+ completely free, so there might be some more memory waste if the size is -+ too big. -+*/ -+#ifndef gcdHEAP_SIZE -+# define gcdHEAP_SIZE (64 << 10) -+#endif -+ -+/* -+ gcdPOWER_SUSPEND_WHEN_IDLE -+ -+ Set to 1 to make GPU enter gcvPOWER_SUSPEND when idle detected, -+ otherwise GPU will enter gcvPOWER_IDLE. -+*/ -+#ifndef gcdPOWER_SUSPEND_WHEN_IDLE -+# define gcdPOWER_SUSPEND_WHEN_IDLE 0 -+#endif -+ -+#ifndef gcdFPGA_BUILD -+# define gcdFPGA_BUILD 0 -+#endif -+ -+/* -+ gcdGPU_TIMEOUT -+ -+ This define specified the number of milliseconds the system will wait -+ before it broadcasts the GPU is stuck. In other words, it will define -+ the timeout of any operation that needs to wait for the GPU. -+ -+ If the value is 0, no timeout will be checked for. -+*/ -+#ifndef gcdGPU_TIMEOUT -+#if gcdFPGA_BUILD -+# define gcdGPU_TIMEOUT 0 -+# define gcdGPU_2D_TIMEOUT 0 -+# else -+# define gcdGPU_TIMEOUT 20000 -+# define gcdGPU_2D_TIMEOUT 4000 -+# endif -+#endif -+ -+/* -+ gcdGPU_ADVANCETIMER -+ -+ it is advance timer. -+*/ -+#ifndef gcdGPU_ADVANCETIMER -+# define gcdGPU_ADVANCETIMER 250 -+#endif -+ -+/* -+ gcdSTATIC_LINK -+ -+ This define disalbes static linking; -+*/ -+#ifndef gcdSTATIC_LINK -+# define gcdSTATIC_LINK 0 -+#endif -+ -+/* -+ gcdUSE_NEW_HEAP -+ -+ Setting this define to 1 enables new heap. -+*/ -+#ifndef gcdUSE_NEW_HEAP -+# define gcdUSE_NEW_HEAP 0 -+#endif -+ -+/* -+ gcdCMD_NO_2D_CONTEXT -+ -+ This define enables no-context 2D command buffer. -+*/ -+#ifndef gcdCMD_NO_2D_CONTEXT -+# define gcdCMD_NO_2D_CONTEXT 1 -+#endif -+ -+/* -+ gcdENABLE_BUFFER_ALIGNMENT -+ -+ When enabled, video memory is allocated with atleast 16KB aligment -+ between multiple sub-buffers. -+*/ -+#ifndef gcdENABLE_BUFFER_ALIGNMENT -+# define gcdENABLE_BUFFER_ALIGNMENT 1 -+#endif -+ -+/* -+ gcdENABLE_BANK_ALIGNMENT -+ -+ When enabled, video memory is allocated bank aligned. The vendor can modify -+ _GetSurfaceBankAlignment() and _GetBankOffsetBytes() to define how -+ different types of allocations are bank and channel aligned. -+ When disabled (default), no bank alignment is done. -+*/ -+#ifndef gcdENABLE_BANK_ALIGNMENT -+# define gcdENABLE_BANK_ALIGNMENT 0 -+#endif -+ -+/* -+ gcdBANK_BIT_START -+ -+ Specifies the start bit of the bank (inclusive). -+*/ -+#ifndef gcdBANK_BIT_START -+# define gcdBANK_BIT_START 12 -+#endif -+ -+/* -+ gcdBANK_BIT_END -+ -+ Specifies the end bit of the bank (inclusive). -+*/ -+#ifndef gcdBANK_BIT_END -+# define gcdBANK_BIT_END 14 -+#endif -+ -+/* -+ gcdBANK_CHANNEL_BIT -+ -+ When set, video memory when allocated bank aligned is allocated such that -+ render and depth buffer addresses alternate on the channel bit specified. -+ This option has an effect only when gcdENABLE_BANK_ALIGNMENT is enabled. -+ When disabled (default), no alteration is done. -+*/ -+#ifndef gcdBANK_CHANNEL_BIT -+# define gcdBANK_CHANNEL_BIT 7 -+#endif -+ -+/* -+ gcdDYNAMIC_SPEED -+ -+ When non-zero, it informs the kernel driver to use the speed throttling -+ broadcasting functions to inform the system the GPU should be spet up or -+ slowed down. It will send a broadcast for slowdown each "interval" -+ specified by this define in milliseconds -+ (gckOS_BroadcastCalibrateSpeed). -+*/ -+#ifndef gcdDYNAMIC_SPEED -+# define gcdDYNAMIC_SPEED 2000 -+#endif -+ -+/* -+ gcdDYNAMIC_EVENT_THRESHOLD -+ -+ When non-zero, it specifies the maximum number of available events at -+ which the kernel driver will issue a broadcast to speed up the GPU -+ (gckOS_BroadcastHurry). -+*/ -+#ifndef gcdDYNAMIC_EVENT_THRESHOLD -+# define gcdDYNAMIC_EVENT_THRESHOLD 5 -+#endif -+ -+/* -+ gcdENABLE_PROFILING -+ -+ Enable profiling macros. -+*/ -+#ifndef gcdENABLE_PROFILING -+# define gcdENABLE_PROFILING 0 -+#endif -+ -+/* -+ gcdENABLE_128B_MERGE -+ -+ Enable 128B merge for the BUS control. -+*/ -+#ifndef gcdENABLE_128B_MERGE -+# define gcdENABLE_128B_MERGE 0 -+#endif -+ -+/* -+ gcdFRAME_DB -+ -+ When non-zero, it specified the number of frames inside the frame -+ database. The frame DB will collect per-frame timestamps and hardware -+ counters. -+*/ -+#ifndef gcdFRAME_DB -+# define gcdFRAME_DB 0 -+# define gcdFRAME_DB_RESET 0 -+# define gcdFRAME_DB_NAME "/var/log/frameDB.log" -+#endif -+ -+/* -+ gcdDISABLE_CORES_2D3D -+ disable the 2D3D cores for 2D openVG -+*/ -+#ifndef gcdDISABLE_CORES_2D3D -+# define gcdDISABLE_CORES_2D3D 0 -+#endif -+ -+/* -+ gcdPAGED_MEMORY_CACHEABLE -+ -+ When non-zero, paged memory will be cacheable. -+ -+ Normally, driver will detemines whether a video memory -+ is cacheable or not. When cacheable is not neccessary, -+ it will be writecombine. -+ -+ This option is only for those SOC which can't enable -+ writecombine without enabling cacheable. -+*/ -+#ifndef gcdPAGED_MEMORY_CACHEABLE -+# define gcdPAGED_MEMORY_CACHEABLE 0 -+#endif -+ -+/* -+ gcdNONPAGED_MEMORY_CACHEABLE -+ -+ When non-zero, non paged memory will be cacheable. -+*/ -+#ifndef gcdNONPAGED_MEMORY_CACHEABLE -+# define gcdNONPAGED_MEMORY_CACHEABLE 0 -+#endif -+ -+/* -+ gcdNONPAGED_MEMORY_BUFFERABLE -+ -+ When non-zero, non paged memory will be bufferable. -+ gcdNONPAGED_MEMORY_BUFFERABLE and gcdNONPAGED_MEMORY_CACHEABLE -+ can't be set 1 at same time -+*/ -+#ifndef gcdNONPAGED_MEMORY_BUFFERABLE -+# define gcdNONPAGED_MEMORY_BUFFERABLE 1 -+#endif -+ -+/* -+ gcdENABLE_INFINITE_SPEED_HW -+ enable the Infinte HW , this is for 2D openVG -+*/ -+#ifndef gcdENABLE_INFINITE_SPEED_HW -+# define gcdENABLE_INFINITE_SPEED_HW 0 -+#endif -+ -+/* -+ gcdPOWEROFF_TIMEOUT -+ -+ When non-zero, GPU will power off automatically from -+ idle state, and gcdPOWEROFF_TIMEOUT is also the default -+ timeout in milliseconds. -+ */ -+#ifndef gcdPOWEROFF_TIMEOUT -+# define gcdPOWEROFF_TIMEOUT 300 -+#endif -+ -+/* -+ gcdRENDER_THREADS -+ -+ Number of render threads. Make it zero, and there will be no render -+ threads. -+*/ -+#ifndef gcdRENDER_THREADS -+# define gcdRENDER_THREADS 0 -+#endif -+ -+/* -+ gcdSMP -+ -+ This define enables SMP support. -+ -+ Currently, it only works on Linux/Android, -+ Kbuild will config it according to whether -+ CONFIG_SMP is set. -+ -+*/ -+#ifndef gcdSMP -+# define gcdSMP 0 -+#endif -+ -+/* -+ gcdSHARED_RESOLVE_BUFFER_ENABLED -+ -+ Use shared resolve buffer for all app buffers. -+*/ -+#ifndef gcdSHARED_RESOLVE_BUFFER_ENABLED -+# define gcdSHARED_RESOLVE_BUFFER_ENABLED 0 -+#endif -+ -+/* -+ gcdUSE_TRIANGLE_STRIP_PATCH -+ */ -+#ifndef gcdUSE_TRIANGLE_STRIP_PATCH -+# define gcdUSE_TRIANGLE_STRIP_PATCH 1 -+#endif -+ -+/* -+ gcdPROCESS_ADDRESS_SPACE -+ -+ When non-zero, every process which attaches to galcore has its own GPU -+ address space, size of which is gcdPROCESS_ADDRESS_SPACE_SIZE. -+*/ -+#ifndef gcdPROCESS_ADDRESS_SPACE -+# define gcdPROCESS_ADDRESS_SPACE 0 -+# define gcdPROCESS_ADDRESS_SPACE_SIZE 0x80000000 -+#endif -+ -+/* -+ gcdSHARED_PAGETABLE -+ -+ When non-zero, multiple GPUs in one chip with same MMU use -+ one shared pagetable. So that when accessing same surface, -+ they can use same GPU virtual address. -+*/ -+#ifndef gcdSHARED_PAGETABLE -+# define gcdSHARED_PAGETABLE !gcdPROCESS_ADDRESS_SPACE -+#endif -+ -+#ifndef gcdUSE_PVR -+# define gcdUSE_PVR 1 -+#endif -+ -+/* -+ gcdSMALL_BLOCK_SIZE -+ -+ When non-zero, a part of VIDMEM will be reserved for requests -+ whose requesting size is less than gcdSMALL_BLOCK_SIZE. -+ -+ For Linux, it's the size of a page. If this requeset fallbacks -+ to gcvPOOL_CONTIGUOUS or gcvPOOL_VIRTUAL, memory will be wasted -+ because they allocate a page at least. -+*/ -+#ifndef gcdSMALL_BLOCK_SIZE -+# define gcdSMALL_BLOCK_SIZE 4096 -+# define gcdRATIO_FOR_SMALL_MEMORY 32 -+#endif -+ -+/* -+ gcdCONTIGUOUS_SIZE_LIMIT -+ When non-zero, size of video node from gcvPOOL_CONTIGUOUS is -+ limited by gcdCONTIGUOUS_SIZE_LIMIT. -+*/ -+#ifndef gcdCONTIGUOUS_SIZE_LIMIT -+# define gcdCONTIGUOUS_SIZE_LIMIT 0 -+#endif -+ -+/* -+ gcdLINK_QUEUE_SIZE -+ -+ When non-zero, driver maintains a queue to record information of -+ latest lined context buffer and command buffer. Data in this queue -+ is be used to debug. -+*/ -+#ifndef gcdLINK_QUEUE_SIZE -+# define gcdLINK_QUEUE_SIZE 5 -+#endif -+ -+/* gcdALPHA_KILL_IN_SHADER -+ -+ Enable alpha kill inside the shader. This will be set automatically by the -+ HAL if certain states match a criteria. -+*/ -+#ifndef gcdALPHA_KILL_IN_SHADER -+# define gcdALPHA_KILL_IN_SHADER 1 -+#endif -+ -+ -+ -+/* -+ gcdDVFS -+ -+ When non-zero, software will make use of dynamic voltage and -+ frequency feature. -+ */ -+#ifndef gcdDVFS -+# define gcdDVFS 0 -+# define gcdDVFS_ANAYLSE_WINDOW 4 -+# define gcdDVFS_POLLING_TIME (gcdDVFS_ANAYLSE_WINDOW * 4) -+#endif -+ -+#ifndef gcdSYNC -+# define gcdSYNC 1 -+#endif -+ -+#ifndef gcdSHADER_SRC_BY_MACHINECODE -+# define gcdSHADER_SRC_BY_MACHINECODE 1 -+#endif -+ -+#ifndef gcdGLB27_SHADER_REPLACE_OPTIMIZATION -+# define gcdGLB27_SHADER_REPLACE_OPTIMIZATION 1 -+#endif -+ -+/* -+ gcdSTREAM_OUT_BUFFER -+ -+ Enable suppport for the secondary stream out buffer. -+*/ -+#ifndef gcdSTREAM_OUT_BUFFER -+# define gcdSTREAM_OUT_BUFFER 0 -+# define gcdSTREAM_OUT_NAIVE_SYNC 0 -+#endif -+ -+/* -+ gcdUSE_HARDWARE_CONFIGURATION_TABLES -+ -+ Enable the use of hardware configuration tables, -+ instead of query hardware and determine the features. -+*/ -+#ifndef gcdUSE_HARDWARE_CONFIGURATION_TABLES -+# define gcdUSE_HARDWARE_CONFIGURATION_TABLES 0 -+#endif -+ -+/* -+ gcdSUPPORT_SWAP_RECTANGLE -+ -+ Support swap with a specific rectangle. -+ -+ Set the rectangle with eglSetSwapRectangleVIV api. -+ Android only. -+*/ -+#ifndef gcdSUPPORT_SWAP_RECTANGLE -+# define gcdSUPPORT_SWAP_RECTANGLE 1 -+#endif -+ -+/* -+ gcdGPU_LINEAR_BUFFER_ENABLED -+ -+ Use linear buffer for GPU apps so HWC can do 2D composition. -+ Android only. -+*/ -+#ifndef gcdGPU_LINEAR_BUFFER_ENABLED -+# define gcdGPU_LINEAR_BUFFER_ENABLED 1 -+#endif -+ -+/* -+ gcdENABLE_RENDER_INTO_WINDOW -+ -+ Enable Render-Into-Window (ie, No-Resolve) feature on android. -+ NOTE that even if enabled, it still depends on hardware feature and -+ android application behavior. When hardware feature or application -+ behavior can not support render into window mode, it will fail back -+ to normal mode. -+ When Render-Into-Window is finally used, window back buffer of android -+ applications will be allocated matching render target tiling format. -+ Otherwise buffer tiling is decided by the above option -+ 'gcdGPU_LINEAR_BUFFER_ENABLED'. -+ Android only for now. -+*/ -+#ifndef gcdENABLE_RENDER_INTO_WINDOW -+# define gcdENABLE_RENDER_INTO_WINDOW 1 -+#endif -+ -+/* -+ gcdENABLE_RENDER_INTO_WINDOW_WITH_FC -+ -+ Enable Direct-rendering (ie, No-Resolve) with tile status. -+ This is expremental and in development stage. -+ This will dynamically check if color compression is available. -+*/ -+#ifndef gcdENABLE_RENDER_INTO_WINDOW_WITH_FC -+# define gcdENABLE_RENDER_INTO_WINDOW_WITH_FC 1 -+#endif -+ -+/* -+ gcdENABLE_BLIT_BUFFER_PRESERVE -+ -+ Render-Into-Window (ie, No-Resolve) does not include preserved swap -+ behavior. This feature can enable buffer preserve in No-Resolve mode. -+ When enabled, previous buffer (may be part of ) will be resolve-blitted -+ to current buffer. -+*/ -+#ifndef gcdENABLE_BLIT_BUFFER_PRESERVE -+# define gcdENABLE_BLIT_BUFFER_PRESERVE 1 -+#endif -+ -+/* -+ gcdANDROID_NATIVE_FENCE_SYNC -+ -+ Enable android native fence sync. It is introduced since jellybean-4.2. -+ Depends on linux kernel option: CONFIG_SYNC. -+ -+ 0: Disabled -+ 1: Build framework for native fence sync feature, and EGL extension -+ 2: Enable async swap buffers for client -+ * Native fence sync for client 'queueBuffer' in EGL, which is -+ 'acquireFenceFd' for layer in compositor side. -+ 3. Enable async hwcomposer composition. -+ * 'releaseFenceFd' for layer in compositor side, which is native -+ fence sync when client 'dequeueBuffer' -+ * Native fence sync for compositor 'queueBuffer' in EGL, which is -+ 'acquireFenceFd' for framebuffer target for DC -+ */ -+#ifndef gcdANDROID_NATIVE_FENCE_SYNC -+# define gcdANDROID_NATIVE_FENCE_SYNC 0 -+#endif -+ -+/* -+ gcdANDROID_IMPLICIT_NATIVE_BUFFER_SYNC -+ -+ Enable implicit android native buffer sync. -+ -+ For non-HW_RENDER buffer, CPU (or other hardware) and GPU can access -+ the buffer at the same time. This is to add implicit synchronization -+ between CPU (or the hardware) and GPU. -+ -+ Eventually, please do not use implicit native buffer sync, but use -+ "fence sync" or "android native fence sync" instead in libgui, which -+ can be enabled in frameworks/native/libs/gui/Android.mk. This kind -+ of synchronization should be done by app but not driver itself. -+ -+ Please disable this option when either "fence sync" or -+ "android native fence sync" is enabled. -+ */ -+#ifndef gcdANDROID_IMPLICIT_NATIVE_BUFFER_SYNC -+# define gcdANDROID_IMPLICIT_NATIVE_BUFFER_SYNC 1 -+#endif -+ -+/* -+ * Implicit native buffer sync is not needed when ANDROID_native_fence_sync -+ * is available. -+ */ -+#if gcdANDROID_NATIVE_FENCE_SYNC -+# undef gcdANDROID_IMPLICIT_NATIVE_BUFFER_SYNC -+# define gcdANDROID_IMPLICIT_NATIVE_BUFFER_SYNC 0 -+#endif -+ -+/* -+ gcdANDROID_UNALIGNED_LINEAR_COMPOSITION_ADJUST -+ -+ Enable source surface address adjust when composition on android. -+ Android only. -+*/ -+#ifndef gcdANDROID_UNALIGNED_LINEAR_COMPOSITION_ADJUST -+# define gcdANDROID_UNALIGNED_LINEAR_COMPOSITION_ADJUST 1 -+#endif -+ -+/* -+ gcdUSE_WCLIP_PATCH -+ -+ Enable wclipping patch. -+*/ -+#ifndef gcdUSE_WCLIP_PATCH -+# define gcdUSE_WCLIP_PATCH 1 -+#endif -+ -+#ifndef gcdUSE_NPOT_PATCH -+# define gcdUSE_NPOT_PATCH 1 -+#endif -+ -+/* -+ gcd3DBLIT -+ -+ TODO: Should be replaced by feature bit if available. -+*/ -+#ifndef gcd3DBLIT -+# define gcd3DBLIT 0 -+#endif -+ -+/* -+ gcdINTERNAL_COMMENT -+ -+ Wrap internal comment, content wrapped by it and the macor itself -+ will be removed in release driver. -+*/ -+#ifndef gcdINTERNAL_COMMENT -+# define gcdINTERNAL_COMMENT 1 -+#endif -+ -+/* -+ gcdRTT_DISABLE_FC -+ -+ Disable RTT FC support. For test only. -+*/ -+#ifndef gcdRTT_DISABLE_FC -+# define gcdRTT_DISABLE_FC 0 -+#endif -+ -+/* -+ gcdFORCE_MIPMAP -+ -+ Force generate mipmap for texture. -+*/ -+#ifndef gcdFORCE_MIPMAP -+# define gcdFORCE_MIPMAP 0 -+#endif -+ -+/* -+ gcdFORCE_BILINEAR -+ -+ Force bilinear for mipfilter. -+*/ -+#ifndef gcdFORCE_BILINEAR -+# define gcdFORCE_BILINEAR 1 -+#endif -+ -+/* -+ gcdBINARY_TRACE -+ -+ When non-zero, binary trace will be generated. -+ -+ When gcdBINARY_TRACE_FILE_SIZE is non-zero, binary trace buffer will -+ be written to a file which size is limited to -+ gcdBINARY_TRACE_FILE_SIZE. -+*/ -+#ifndef gcdBINARY_TRACE -+# define gcdBINARY_TRACE 0 -+# define gcdBINARY_TRACE_FILE_SIZE 0 -+#endif -+ -+#ifndef gcdMOVG -+# define gcdMOVG 0 -+#if gcdMOVG -+# define GC355_PROFILER 1 -+# endif -+# define gcdENABLE_TS_DOUBLE_BUFFER 1 -+#else -+#if gcdMOVG -+# define GC355_PROFILER 1 -+# define gcdENABLE_TS_DOUBLE_BUFFER 0 -+#else -+# define gcdENABLE_TS_DOUBLE_BUFFER 1 -+#endif -+#endif -+ -+/* gcdINTERRUPT_STATISTIC -+ * -+ * Monitor the event send to GPU and interrupt issued by GPU. -+ */ -+ -+#ifndef gcdINTERRUPT_STATISTIC -+#if defined(LINUX) -+# define gcdINTERRUPT_STATISTIC 1 -+#else -+# define gcdINTERRUPT_STATISTIC 0 -+#endif -+#endif -+ -+/* -+ gcdYINVERTED_RENDERING -+ When it's not zero, we will rendering display buffer -+ with top-bottom direction. All other offscreen rendering -+ will be bottom-top, which follow OpenGL ES spec. -+*/ -+#ifndef gcdYINVERTED_RENDERING -+# define gcdYINVERTED_RENDERING 1 -+#endif -+ -+#if gcdYINVERTED_RENDERING -+/* disable unaligned linear composition adjust in Y-inverted rendering mode. */ -+# undef gcdANDROID_UNALIGNED_LINEAR_COMPOSITION_ADJUST -+# define gcdANDROID_UNALIGNED_LINEAR_COMPOSITION_ADJUST 0 -+#endif -+ -+/* -+ gcdFENCE_WAIT_LOOP_COUNT -+ Wait fence, loop count. -+*/ -+#ifndef gcdFENCE_WAIT_LOOP_COUNT -+# define gcdFENCE_WAIT_LOOP_COUNT 100 -+#endif -+ -+/* -+ gcdHAL_3D_DRAWBLIT -+ When it's not zero, we will enable HAL 3D drawblit -+ to replace client 3dblit. -+*/ -+#ifndef gcdHAL_3D_DRAWBLIT -+# define gcdHAL_3D_DRAWBLIT 1 -+#endif -+ -+/* -+ gcdPARTIAL_FAST_CLEAR -+ When it's not zero, partial fast clear is enabled. -+ Depends on gcdHAL_3D_DRAWBLIT, if gcdHAL_3D_DRAWBLIT is not enabled, -+ only available when scissor box is completely aligned. -+ Expremental, under test. -+*/ -+#ifndef gcdPARTIAL_FAST_CLEAR -+# define gcdPARTIAL_FAST_CLEAR 1 -+#endif -+ -+/* -+ gcdREMOVE_SURF_ORIENTATION -+ When it's not zero, we will remove surface orientation function. -+ It wil become to a parameter of resolve function. -+*/ -+#ifndef gcdREMOVE_SURF_ORIENTATION -+# define gcdREMOVE_SURF_ORIENTATION 0 -+#endif -+ -+/* -+ gcdPATTERN_FAST_PATH -+ For pattern match -+*/ -+#ifndef gcdPATTERN_FAST_PATH -+# define gcdPATTERN_FAST_PATH 1 -+#endif -+ -+/* -+ gcdUSE_INPUT_DEVICE -+ disable input devices usage under fb mode to support fb+vdk multi-process -+*/ -+#ifndef gcdUSE_INPUT_DEVICE -+# define gcdUSE_INPUT_DEVICE 1 -+#endif -+ -+ -+/* -+ gcdFRAMEINFO_STATISTIC -+ When enable, collect frame information. -+*/ -+#ifndef gcdFRAMEINFO_STATISTIC -+ -+#if (defined(DBG) && DBG) || defined(DEBUG) || defined(_DEBUG) || gcdDUMP -+# define gcdFRAMEINFO_STATISTIC 1 -+#else -+# define gcdFRAMEINFO_STATISTIC 0 -+#endif -+ -+#endif -+ -+/* -+ gcdPACKED_OUTPUT_ADDRESS -+ When it's not zero, ps output is already packed after linked -+*/ -+#ifndef gcdPACKED_OUTPUT_ADDRESS -+# define gcdPACKED_OUTPUT_ADDRESS 1 -+#endif -+ -+/* -+ gcdENABLE_THIRD_PARTY_OPERATION -+ Enable third party operation like tpc or not. -+*/ -+#ifndef gcdENABLE_THIRD_PARTY_OPERATION -+# define gcdENABLE_THIRD_PARTY_OPERATION 1 -+#endif -+ -+ -+/* -+ Core configurations. By default enable all cores. -+*/ -+#ifndef gcdENABLE_3D -+# define gcdENABLE_3D 1 -+#endif -+ -+#ifndef gcdENABLE_2D -+# define gcdENABLE_2D 1 -+#endif -+ -+#ifndef gcdENABLE_VG -+# define gcdENABLE_VG 0 -+#endif -+ -+#ifndef gcdGC355_MEM_PRINT -+# define gcdGC355_MEM_PRINT 0 -+#else -+#if (!((gcdENABLE_3D == 0) && (gcdENABLE_2D == 0) && (gcdENABLE_VG == 1))) -+# undef gcdGC355_MEM_PRINT -+# define gcdGC355_MEM_PRINT 0 -+# endif -+#endif -+ -+#ifndef gcdENABLE_UNIFIED_CONSTANT -+# define gcdENABLE_UNIFIED_CONSTANT 1 -+#endif -+ -+/* -+ gcdRECORD_COMMAND -+*/ -+#ifndef gcdRECORD_COMMAND -+# define gcdRECORD_COMMAND 0 -+#endif -+ -+#endif /* __gc_hal_options_h_ */ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_profiler.h linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_profiler.h ---- linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_profiler.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_profiler.h 2015-11-30 17:56:13.592136927 +0100 -@@ -0,0 +1,585 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#ifndef __gc_hal_profiler_h_ -+#define __gc_hal_profiler_h_ -+ -+#if VIVANTE_PROFILER_NEW -+#include "gc_hal_engine.h" -+#endif -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+#define GLVERTEX_OBJECT 10 -+#define GLVERTEX_OBJECT_BYTES 11 -+ -+#define GLINDEX_OBJECT 20 -+#define GLINDEX_OBJECT_BYTES 21 -+ -+#define GLTEXTURE_OBJECT 30 -+#define GLTEXTURE_OBJECT_BYTES 31 -+ -+#define GLBUFOBJ_OBJECT 40 -+#define GLBUFOBJ_OBJECT_BYTES 41 -+ -+#if VIVANTE_PROFILER -+#define gcmPROFILE_GC(Enum, Value) gcoPROFILER_Count(gcvNULL, Enum, Value) -+#else -+#define gcmPROFILE_GC(Enum, Value) do { } while (gcvFALSE) -+#endif -+ -+#ifndef gcdNEW_PROFILER_FILE -+#define gcdNEW_PROFILER_FILE 1 -+#endif -+ -+#define ES11_CALLS 151 -+#define ES11_DRAWCALLS (ES11_CALLS + 1) -+#define ES11_STATECHANGECALLS (ES11_DRAWCALLS + 1) -+#define ES11_POINTCOUNT (ES11_STATECHANGECALLS + 1) -+#define ES11_LINECOUNT (ES11_POINTCOUNT + 1) -+#define ES11_TRIANGLECOUNT (ES11_LINECOUNT + 1) -+ -+#define ES30_CALLS 159 -+#define ES30_DRAWCALLS (ES30_CALLS + 1) -+#define ES30_STATECHANGECALLS (ES30_DRAWCALLS + 1) -+#define ES30_POINTCOUNT (ES30_STATECHANGECALLS + 1) -+#define ES30_LINECOUNT (ES30_POINTCOUNT + 1) -+#define ES30_TRIANGLECOUNT (ES30_LINECOUNT + 1) -+ -+#define VG11_CALLS 88 -+#define VG11_DRAWCALLS (VG11_CALLS + 1) -+#define VG11_STATECHANGECALLS (VG11_DRAWCALLS + 1) -+#define VG11_FILLCOUNT (VG11_STATECHANGECALLS + 1) -+#define VG11_STROKECOUNT (VG11_FILLCOUNT + 1) -+/* End of Driver API ID Definitions. */ -+ -+/* HAL & MISC IDs. */ -+#define HAL_VERTBUFNEWBYTEALLOC 1 -+#define HAL_VERTBUFTOTALBYTEALLOC (HAL_VERTBUFNEWBYTEALLOC + 1) -+#define HAL_VERTBUFNEWOBJALLOC (HAL_VERTBUFTOTALBYTEALLOC + 1) -+#define HAL_VERTBUFTOTALOBJALLOC (HAL_VERTBUFNEWOBJALLOC + 1) -+#define HAL_INDBUFNEWBYTEALLOC (HAL_VERTBUFTOTALOBJALLOC + 1) -+#define HAL_INDBUFTOTALBYTEALLOC (HAL_INDBUFNEWBYTEALLOC + 1) -+#define HAL_INDBUFNEWOBJALLOC (HAL_INDBUFTOTALBYTEALLOC + 1) -+#define HAL_INDBUFTOTALOBJALLOC (HAL_INDBUFNEWOBJALLOC + 1) -+#define HAL_TEXBUFNEWBYTEALLOC (HAL_INDBUFTOTALOBJALLOC + 1) -+#define HAL_TEXBUFTOTALBYTEALLOC (HAL_TEXBUFNEWBYTEALLOC + 1) -+#define HAL_TEXBUFNEWOBJALLOC (HAL_TEXBUFTOTALBYTEALLOC + 1) -+#define HAL_TEXBUFTOTALOBJALLOC (HAL_TEXBUFNEWOBJALLOC + 1) -+ -+#define GPU_CYCLES 1 -+#define GPU_READ64BYTE (GPU_CYCLES + 1) -+#define GPU_WRITE64BYTE (GPU_READ64BYTE + 1) -+#define GPU_TOTALCYCLES (GPU_WRITE64BYTE + 1) -+#define GPU_IDLECYCLES (GPU_TOTALCYCLES + 1) -+ -+#define VS_INSTCOUNT 1 -+#define VS_BRANCHINSTCOUNT (VS_INSTCOUNT + 1) -+#define VS_TEXLDINSTCOUNT (VS_BRANCHINSTCOUNT + 1) -+#define VS_RENDEREDVERTCOUNT (VS_TEXLDINSTCOUNT + 1) -+#define VS_SOURCE (VS_RENDEREDVERTCOUNT + 1) -+ -+#define PS_INSTCOUNT 1 -+#define PS_BRANCHINSTCOUNT (PS_INSTCOUNT + 1) -+#define PS_TEXLDINSTCOUNT (PS_BRANCHINSTCOUNT + 1) -+#define PS_RENDEREDPIXCOUNT (PS_TEXLDINSTCOUNT + 1) -+#define PS_SOURCE (PS_RENDEREDPIXCOUNT + 1) -+ -+#define PA_INVERTCOUNT 1 -+#define PA_INPRIMCOUNT (PA_INVERTCOUNT + 1) -+#define PA_OUTPRIMCOUNT (PA_INPRIMCOUNT + 1) -+#define PA_DEPTHCLIPCOUNT (PA_OUTPRIMCOUNT + 1) -+#define PA_TRIVIALREJCOUNT (PA_DEPTHCLIPCOUNT + 1) -+#define PA_CULLCOUNT (PA_TRIVIALREJCOUNT + 1) -+ -+#define SE_TRIANGLECOUNT 1 -+#define SE_LINECOUNT (SE_TRIANGLECOUNT + 1) -+ -+#define RA_VALIDPIXCOUNT 1 -+#define RA_TOTALQUADCOUNT (RA_VALIDPIXCOUNT + 1) -+#define RA_VALIDQUADCOUNTEZ (RA_TOTALQUADCOUNT + 1) -+#define RA_TOTALPRIMCOUNT (RA_VALIDQUADCOUNTEZ + 1) -+#define RA_PIPECACHEMISSCOUNT (RA_TOTALPRIMCOUNT + 1) -+#define RA_PREFCACHEMISSCOUNT (RA_PIPECACHEMISSCOUNT + 1) -+#define RA_EEZCULLCOUNT (RA_PREFCACHEMISSCOUNT + 1) -+ -+#define TX_TOTBILINEARREQ 1 -+#define TX_TOTTRILINEARREQ (TX_TOTBILINEARREQ + 1) -+#define TX_TOTDISCARDTEXREQ (TX_TOTTRILINEARREQ + 1) -+#define TX_TOTTEXREQ (TX_TOTDISCARDTEXREQ + 1) -+#define TX_MEMREADCOUNT (TX_TOTTEXREQ + 1) -+#define TX_MEMREADIN8BCOUNT (TX_MEMREADCOUNT + 1) -+#define TX_CACHEMISSCOUNT (TX_MEMREADIN8BCOUNT + 1) -+#define TX_CACHEHITTEXELCOUNT (TX_CACHEMISSCOUNT + 1) -+#define TX_CACHEMISSTEXELCOUNT (TX_CACHEHITTEXELCOUNT + 1) -+ -+#define PE_KILLEDBYCOLOR 1 -+#define PE_KILLEDBYDEPTH (PE_KILLEDBYCOLOR + 1) -+#define PE_DRAWNBYCOLOR (PE_KILLEDBYDEPTH + 1) -+#define PE_DRAWNBYDEPTH (PE_DRAWNBYCOLOR + 1) -+ -+#define MC_READREQ8BPIPE 1 -+#define MC_READREQ8BIP (MC_READREQ8BPIPE + 1) -+#define MC_WRITEREQ8BPIPE (MC_READREQ8BIP + 1) -+ -+#define AXI_READREQSTALLED 1 -+#define AXI_WRITEREQSTALLED (AXI_READREQSTALLED + 1) -+#define AXI_WRITEDATASTALLED (AXI_WRITEREQSTALLED + 1) -+ -+#define PVS_INSTRCOUNT 1 -+#define PVS_ALUINSTRCOUNT (PVS_INSTRCOUNT + 1) -+#define PVS_TEXINSTRCOUNT (PVS_ALUINSTRCOUNT + 1) -+#define PVS_ATTRIBCOUNT (PVS_TEXINSTRCOUNT + 1) -+#define PVS_UNIFORMCOUNT (PVS_ATTRIBCOUNT + 1) -+#define PVS_FUNCTIONCOUNT (PVS_UNIFORMCOUNT + 1) -+#define PVS_SOURCE (PVS_FUNCTIONCOUNT + 1) -+ -+#define PPS_INSTRCOUNT 1 -+#define PPS_ALUINSTRCOUNT (PPS_INSTRCOUNT + 1) -+#define PPS_TEXINSTRCOUNT (PPS_ALUINSTRCOUNT + 1) -+#define PPS_ATTRIBCOUNT (PPS_TEXINSTRCOUNT + 1) -+#define PPS_UNIFORMCOUNT (PPS_ATTRIBCOUNT + 1) -+#define PPS_FUNCTIONCOUNT (PPS_UNIFORMCOUNT + 1) -+#define PPS_SOURCE (PPS_FUNCTIONCOUNT + 1) -+/* End of MISC Counter IDs. */ -+ -+#ifdef gcdNEW_PROFILER_FILE -+ -+/* Category Constants. */ -+#define VPHEADER 0x010000 -+#define VPG_INFO 0x020000 -+#define VPG_TIME 0x030000 -+#define VPG_MEM 0x040000 -+#define VPG_ES11 0x050000 -+#define VPG_ES30 0x060000 -+#define VPG_VG11 0x070000 -+#define VPG_HAL 0x080000 -+#define VPG_HW 0x090000 -+#define VPG_GPU 0x0a0000 -+#define VPG_VS 0x0b0000 -+#define VPG_PS 0x0c0000 -+#define VPG_PA 0x0d0000 -+#define VPG_SETUP 0x0e0000 -+#define VPG_RA 0x0f0000 -+#define VPG_TX 0x100000 -+#define VPG_PE 0x110000 -+#define VPG_MC 0x120000 -+#define VPG_AXI 0x130000 -+#define VPG_PROG 0x140000 -+#define VPG_PVS 0x150000 -+#define VPG_PPS 0x160000 -+#define VPG_ES11_TIME 0x170000 -+#define VPG_ES30_TIME 0x180000 -+#define VPG_FRAME 0x190000 -+#define VPG_ES11_DRAW 0x200000 -+#define VPG_ES30_DRAW 0x210000 -+#define VPG_VG11_TIME 0x220000 -+#define VPG_END 0xff0000 -+ -+/* Info. */ -+#define VPC_INFOCOMPANY (VPG_INFO + 1) -+#define VPC_INFOVERSION (VPC_INFOCOMPANY + 1) -+#define VPC_INFORENDERER (VPC_INFOVERSION + 1) -+#define VPC_INFOREVISION (VPC_INFORENDERER + 1) -+#define VPC_INFODRIVER (VPC_INFOREVISION + 1) -+#define VPC_INFODRIVERMODE (VPC_INFODRIVER + 1) -+#define VPC_INFOSCREENSIZE (VPC_INFODRIVERMODE + 1) -+ -+/* Counter Constants. */ -+#define VPC_ELAPSETIME (VPG_TIME + 1) -+#define VPC_CPUTIME (VPC_ELAPSETIME + 1) -+ -+#define VPC_MEMMAXRES (VPG_MEM + 1) -+#define VPC_MEMSHARED (VPC_MEMMAXRES + 1) -+#define VPC_MEMUNSHAREDDATA (VPC_MEMSHARED + 1) -+#define VPC_MEMUNSHAREDSTACK (VPC_MEMUNSHAREDDATA + 1) -+ -+/* OpenGL ES11 Statics Counter IDs. */ -+#define VPC_ES11CALLS (VPG_ES11 + ES11_CALLS) -+#define VPC_ES11DRAWCALLS (VPG_ES11 + ES11_DRAWCALLS) -+#define VPC_ES11STATECHANGECALLS (VPG_ES11 + ES11_STATECHANGECALLS) -+#define VPC_ES11POINTCOUNT (VPG_ES11 + ES11_POINTCOUNT) -+#define VPC_ES11LINECOUNT (VPG_ES11 + ES11_LINECOUNT) -+#define VPC_ES11TRIANGLECOUNT (VPG_ES11 + ES11_TRIANGLECOUNT) -+ -+/* OpenGL ES30 Statistics Counter IDs. */ -+#define VPC_ES30CALLS (VPG_ES30 + ES30_CALLS) -+#define VPC_ES30DRAWCALLS (VPG_ES30 + ES30_DRAWCALLS) -+#define VPC_ES30STATECHANGECALLS (VPG_ES30 + ES30_STATECHANGECALLS) -+#define VPC_ES30POINTCOUNT (VPG_ES30 + ES30_POINTCOUNT) -+#define VPC_ES30LINECOUNT (VPG_ES30 + ES30_LINECOUNT) -+#define VPC_ES30TRIANGLECOUNT (VPG_ES30 + ES30_TRIANGLECOUNT) -+ -+/* OpenVG Statistics Counter IDs. */ -+#define VPC_VG11CALLS (VPG_VG11 + VG11_CALLS) -+#define VPC_VG11DRAWCALLS (VPG_VG11 + VG11_DRAWCALLS) -+#define VPC_VG11STATECHANGECALLS (VPG_VG11 + VG11_STATECHANGECALLS) -+#define VPC_VG11FILLCOUNT (VPG_VG11 + VG11_FILLCOUNT) -+#define VPC_VG11STROKECOUNT (VPG_VG11 + VG11_STROKECOUNT) -+ -+/* HAL Counters. */ -+#define VPC_HALVERTBUFNEWBYTEALLOC (VPG_HAL + HAL_VERTBUFNEWBYTEALLOC) -+#define VPC_HALVERTBUFTOTALBYTEALLOC (VPG_HAL + HAL_VERTBUFTOTALBYTEALLOC) -+#define VPC_HALVERTBUFNEWOBJALLOC (VPG_HAL + HAL_VERTBUFNEWOBJALLOC) -+#define VPC_HALVERTBUFTOTALOBJALLOC (VPG_HAL + HAL_VERTBUFTOTALOBJALLOC) -+#define VPC_HALINDBUFNEWBYTEALLOC (VPG_HAL + HAL_INDBUFNEWBYTEALLOC) -+#define VPC_HALINDBUFTOTALBYTEALLOC (VPG_HAL + HAL_INDBUFTOTALBYTEALLOC) -+#define VPC_HALINDBUFNEWOBJALLOC (VPG_HAL + HAL_INDBUFNEWOBJALLOC) -+#define VPC_HALINDBUFTOTALOBJALLOC (VPG_HAL + HAL_INDBUFTOTALOBJALLOC) -+#define VPC_HALTEXBUFNEWBYTEALLOC (VPG_HAL + HAL_TEXBUFNEWBYTEALLOC) -+#define VPC_HALTEXBUFTOTALBYTEALLOC (VPG_HAL + HAL_TEXBUFTOTALBYTEALLOC) -+#define VPC_HALTEXBUFNEWOBJALLOC (VPG_HAL + HAL_TEXBUFNEWOBJALLOC) -+#define VPC_HALTEXBUFTOTALOBJALLOC (VPG_HAL + HAL_TEXBUFTOTALOBJALLOC) -+ -+/* HW: GPU Counters. */ -+#define VPC_GPUCYCLES (VPG_GPU + GPU_CYCLES) -+#define VPC_GPUREAD64BYTE (VPG_GPU + GPU_READ64BYTE) -+#define VPC_GPUWRITE64BYTE (VPG_GPU + GPU_WRITE64BYTE) -+#define VPC_GPUTOTALCYCLES (VPG_GPU + GPU_TOTALCYCLES) -+#define VPC_GPUIDLECYCLES (VPG_GPU + GPU_IDLECYCLES) -+ -+/* HW: Shader Counters. */ -+#define VPC_VSINSTCOUNT (VPG_VS + VS_INSTCOUNT) -+#define VPC_VSBRANCHINSTCOUNT (VPG_VS + VS_BRANCHINSTCOUNT) -+#define VPC_VSTEXLDINSTCOUNT (VPG_VS + VS_TEXLDINSTCOUNT) -+#define VPC_VSRENDEREDVERTCOUNT (VPG_VS + VS_RENDEREDVERTCOUNT) -+/* HW: PS Count. */ -+#define VPC_PSINSTCOUNT (VPG_PS + PS_INSTCOUNT) -+#define VPC_PSBRANCHINSTCOUNT (VPG_PS + PS_BRANCHINSTCOUNT) -+#define VPC_PSTEXLDINSTCOUNT (VPG_PS + PS_TEXLDINSTCOUNT) -+#define VPC_PSRENDEREDPIXCOUNT (VPG_PS + PS_RENDEREDPIXCOUNT) -+ -+ -+/* HW: PA Counters. */ -+#define VPC_PAINVERTCOUNT (VPG_PA + PA_INVERTCOUNT) -+#define VPC_PAINPRIMCOUNT (VPG_PA + PA_INPRIMCOUNT) -+#define VPC_PAOUTPRIMCOUNT (VPG_PA + PA_OUTPRIMCOUNT) -+#define VPC_PADEPTHCLIPCOUNT (VPG_PA + PA_DEPTHCLIPCOUNT) -+#define VPC_PATRIVIALREJCOUNT (VPG_PA + PA_TRIVIALREJCOUNT) -+#define VPC_PACULLCOUNT (VPG_PA + PA_CULLCOUNT) -+ -+/* HW: Setup Counters. */ -+#define VPC_SETRIANGLECOUNT (VPG_SETUP + SE_TRIANGLECOUNT) -+#define VPC_SELINECOUNT (VPG_SETUP + SE_LINECOUNT) -+ -+/* HW: RA Counters. */ -+#define VPC_RAVALIDPIXCOUNT (VPG_RA + RA_VALIDPIXCOUNT) -+#define VPC_RATOTALQUADCOUNT (VPG_RA + RA_TOTALQUADCOUNT) -+#define VPC_RAVALIDQUADCOUNTEZ (VPG_RA + RA_VALIDQUADCOUNTEZ) -+#define VPC_RATOTALPRIMCOUNT (VPG_RA + RA_TOTALPRIMCOUNT) -+#define VPC_RAPIPECACHEMISSCOUNT (VPG_RA + RA_PIPECACHEMISSCOUNT) -+#define VPC_RAPREFCACHEMISSCOUNT (VPG_RA + RA_PREFCACHEMISSCOUNT) -+#define VPC_RAEEZCULLCOUNT (VPG_RA + RA_EEZCULLCOUNT) -+ -+/* HW: TEX Counters. */ -+#define VPC_TXTOTBILINEARREQ (VPG_TX + TX_TOTBILINEARREQ) -+#define VPC_TXTOTTRILINEARREQ (VPG_TX + TX_TOTTRILINEARREQ) -+#define VPC_TXTOTDISCARDTEXREQ (VPG_TX + TX_TOTDISCARDTEXREQ) -+#define VPC_TXTOTTEXREQ (VPG_TX + TX_TOTTEXREQ) -+#define VPC_TXMEMREADCOUNT (VPG_TX + TX_MEMREADCOUNT) -+#define VPC_TXMEMREADIN8BCOUNT (VPG_TX + TX_MEMREADIN8BCOUNT) -+#define VPC_TXCACHEMISSCOUNT (VPG_TX + TX_CACHEMISSCOUNT) -+#define VPC_TXCACHEHITTEXELCOUNT (VPG_TX + TX_CACHEHITTEXELCOUNT) -+#define VPC_TXCACHEMISSTEXELCOUNT (VPG_TX + TX_CACHEMISSTEXELCOUNT) -+ -+/* HW: PE Counters. */ -+#define VPC_PEKILLEDBYCOLOR (VPG_PE + PE_KILLEDBYCOLOR) -+#define VPC_PEKILLEDBYDEPTH (VPG_PE + PE_KILLEDBYDEPTH) -+#define VPC_PEDRAWNBYCOLOR (VPG_PE + PE_DRAWNBYCOLOR) -+#define VPC_PEDRAWNBYDEPTH (VPG_PE + PE_DRAWNBYDEPTH) -+ -+/* HW: MC Counters. */ -+#define VPC_MCREADREQ8BPIPE (VPG_MC + MC_READREQ8BPIPE) -+#define VPC_MCREADREQ8BIP (VPG_MC + MC_READREQ8BIP) -+#define VPC_MCWRITEREQ8BPIPE (VPG_MC + MC_WRITEREQ8BPIPE) -+ -+/* HW: AXI Counters. */ -+#define VPC_AXIREADREQSTALLED (VPG_AXI + AXI_READREQSTALLED) -+#define VPC_AXIWRITEREQSTALLED (VPG_AXI + AXI_WRITEREQSTALLED) -+#define VPC_AXIWRITEDATASTALLED (VPG_AXI + AXI_WRITEDATASTALLED) -+ -+/* PROGRAM: Shader program counters. */ -+#define VPC_PVSINSTRCOUNT (VPG_PVS + PVS_INSTRCOUNT) -+#define VPC_PVSALUINSTRCOUNT (VPG_PVS + PVS_ALUINSTRCOUNT) -+#define VPC_PVSTEXINSTRCOUNT (VPG_PVS + PVS_TEXINSTRCOUNT) -+#define VPC_PVSATTRIBCOUNT (VPG_PVS + PVS_ATTRIBCOUNT) -+#define VPC_PVSUNIFORMCOUNT (VPG_PVS + PVS_UNIFORMCOUNT) -+#define VPC_PVSFUNCTIONCOUNT (VPG_PVS + PVS_FUNCTIONCOUNT) -+#define VPC_PVSSOURCE (VPG_PVS + PVS_SOURCE) -+ -+#define VPC_PPSINSTRCOUNT (VPG_PPS + PPS_INSTRCOUNT) -+#define VPC_PPSALUINSTRCOUNT (VPG_PPS + PPS_ALUINSTRCOUNT) -+#define VPC_PPSTEXINSTRCOUNT (VPG_PPS + PPS_TEXINSTRCOUNT) -+#define VPC_PPSATTRIBCOUNT (VPG_PPS + PPS_ATTRIBCOUNT) -+#define VPC_PPSUNIFORMCOUNT (VPG_PPS + PPS_UNIFORMCOUNT) -+#define VPC_PPSFUNCTIONCOUNT (VPG_PPS + PPS_FUNCTIONCOUNT) -+#define VPC_PPSSOURCE (VPG_PPS + PPS_SOURCE) -+ -+#define VPC_PROGRAMHANDLE (VPG_PROG + 1) -+ -+#define VPC_ES30_DRAW_NO (VPG_ES30_DRAW + 1) -+#define VPC_ES11_DRAW_NO (VPG_ES11_DRAW + 1) -+#endif -+ -+ -+/* HW profile information. */ -+typedef struct _gcsPROFILER_COUNTERS -+{ -+ /* HW static counters. */ -+ gctUINT32 gpuClock; -+ gctUINT32 axiClock; -+ gctUINT32 shaderClock; -+ -+ /* HW vairable counters. */ -+ gctUINT32 gpuClockStart; -+ gctUINT32 gpuClockEnd; -+ -+ /* HW vairable counters. */ -+ gctUINT32 gpuCyclesCounter; -+ gctUINT32 gpuTotalCyclesCounter; -+ gctUINT32 gpuIdleCyclesCounter; -+ gctUINT32 gpuTotalRead64BytesPerFrame; -+ gctUINT32 gpuTotalWrite64BytesPerFrame; -+ -+ /* PE */ -+ gctUINT32 pe_pixel_count_killed_by_color_pipe; -+ gctUINT32 pe_pixel_count_killed_by_depth_pipe; -+ gctUINT32 pe_pixel_count_drawn_by_color_pipe; -+ gctUINT32 pe_pixel_count_drawn_by_depth_pipe; -+ -+ /* SH */ -+ gctUINT32 ps_inst_counter; -+ gctUINT32 rendered_pixel_counter; -+ gctUINT32 vs_inst_counter; -+ gctUINT32 rendered_vertice_counter; -+ gctUINT32 vtx_branch_inst_counter; -+ gctUINT32 vtx_texld_inst_counter; -+ gctUINT32 pxl_branch_inst_counter; -+ gctUINT32 pxl_texld_inst_counter; -+ -+ /* PA */ -+ gctUINT32 pa_input_vtx_counter; -+ gctUINT32 pa_input_prim_counter; -+ gctUINT32 pa_output_prim_counter; -+ gctUINT32 pa_depth_clipped_counter; -+ gctUINT32 pa_trivial_rejected_counter; -+ gctUINT32 pa_culled_counter; -+ -+ /* SE */ -+ gctUINT32 se_culled_triangle_count; -+ gctUINT32 se_culled_lines_count; -+ -+ /* RA */ -+ gctUINT32 ra_valid_pixel_count; -+ gctUINT32 ra_total_quad_count; -+ gctUINT32 ra_valid_quad_count_after_early_z; -+ gctUINT32 ra_total_primitive_count; -+ gctUINT32 ra_pipe_cache_miss_counter; -+ gctUINT32 ra_prefetch_cache_miss_counter; -+ gctUINT32 ra_eez_culled_counter; -+ -+ /* TX */ -+ gctUINT32 tx_total_bilinear_requests; -+ gctUINT32 tx_total_trilinear_requests; -+ gctUINT32 tx_total_discarded_texture_requests; -+ gctUINT32 tx_total_texture_requests; -+ gctUINT32 tx_mem_read_count; -+ gctUINT32 tx_mem_read_in_8B_count; -+ gctUINT32 tx_cache_miss_count; -+ gctUINT32 tx_cache_hit_texel_count; -+ gctUINT32 tx_cache_miss_texel_count; -+ -+ /* MC */ -+ gctUINT32 mc_total_read_req_8B_from_pipeline; -+ gctUINT32 mc_total_read_req_8B_from_IP; -+ gctUINT32 mc_total_write_req_8B_from_pipeline; -+ -+ /* HI */ -+ gctUINT32 hi_axi_cycles_read_request_stalled; -+ gctUINT32 hi_axi_cycles_write_request_stalled; -+ gctUINT32 hi_axi_cycles_write_data_stalled; -+} -+gcsPROFILER_COUNTERS; -+ -+#if VIVANTE_PROFILER_NEW -+#define NumOfDrawBuf 64 -+#endif -+ -+/* HAL profile information. */ -+typedef struct _gcsPROFILER -+{ -+ gctUINT32 enable; -+ gctBOOL enableHal; -+ gctBOOL enableHW; -+ gctBOOL enableSH; -+ gctBOOL isSyncMode; -+ gctBOOL disableOutputCounter; -+ -+ gctBOOL useSocket; -+ gctINT sockFd; -+ -+ gctFILE file; -+ -+ /* Aggregate Information */ -+ -+ /* Clock Info */ -+ gctUINT64 frameStart; -+ gctUINT64 frameEnd; -+ -+ /* Current frame information */ -+ gctUINT32 frameNumber; -+ gctUINT64 frameStartTimeusec; -+ gctUINT64 frameEndTimeusec; -+ gctUINT64 frameStartCPUTimeusec; -+ gctUINT64 frameEndCPUTimeusec; -+ -+#if PROFILE_HAL_COUNTERS -+ gctUINT32 vertexBufferTotalBytesAlloc; -+ gctUINT32 vertexBufferNewBytesAlloc; -+ int vertexBufferTotalObjectsAlloc; -+ int vertexBufferNewObjectsAlloc; -+ -+ gctUINT32 indexBufferTotalBytesAlloc; -+ gctUINT32 indexBufferNewBytesAlloc; -+ int indexBufferTotalObjectsAlloc; -+ int indexBufferNewObjectsAlloc; -+ -+ gctUINT32 textureBufferTotalBytesAlloc; -+ gctUINT32 textureBufferNewBytesAlloc; -+ int textureBufferTotalObjectsAlloc; -+ int textureBufferNewObjectsAlloc; -+ -+ gctUINT32 numCommits; -+ gctUINT32 drawPointCount; -+ gctUINT32 drawLineCount; -+ gctUINT32 drawTriangleCount; -+ gctUINT32 drawVertexCount; -+ gctUINT32 redundantStateChangeCalls; -+#endif -+ -+ gctUINT32 prevVSInstCount; -+ gctUINT32 prevVSBranchInstCount; -+ gctUINT32 prevVSTexInstCount; -+ gctUINT32 prevVSVertexCount; -+ gctUINT32 prevPSInstCount; -+ gctUINT32 prevPSBranchInstCount; -+ gctUINT32 prevPSTexInstCount; -+ gctUINT32 prevPSPixelCount; -+ -+#if VIVANTE_PROFILER_NEW -+ gcoBUFOBJ newCounterBuf[NumOfDrawBuf]; -+ gctUINT32 curBufId; -+#endif -+ -+} -+gcsPROFILER; -+ -+/* Memory profile information. */ -+struct _gcsMemProfile -+{ -+ /* Memory Usage */ -+ gctUINT32 videoMemUsed; -+ gctUINT32 systemMemUsed; -+ gctUINT32 commitBufferSize; -+ gctUINT32 contextBufferCopyBytes; -+}; -+ -+/* Shader profile information. */ -+struct _gcsSHADER_PROFILER -+{ -+ gctUINT32 shaderLength; -+ gctUINT32 shaderALUCycles; -+ gctUINT32 shaderTexLoadCycles; -+ gctUINT32 shaderTempRegCount; -+ gctUINT32 shaderSamplerRegCount; -+ gctUINT32 shaderInputRegCount; -+ gctUINT32 shaderOutputRegCount; -+}; -+ -+/* Initialize the gcsProfiler. */ -+gceSTATUS -+gcoPROFILER_Initialize( -+ IN gcoHAL Hal, -+ IN gctBOOL Enable -+ ); -+ -+/* Destroy the gcProfiler. */ -+gceSTATUS -+gcoPROFILER_Destroy( -+ IN gcoHAL Hal -+ ); -+ -+/* Write data to profiler. */ -+gceSTATUS -+gcoPROFILER_Write( -+ IN gcoHAL Hal, -+ IN gctSIZE_T ByteCount, -+ IN gctCONST_POINTER Data -+ ); -+ -+/* Flush data out. */ -+gceSTATUS -+gcoPROFILER_Flush( -+ IN gcoHAL Hal -+ ); -+ -+/* Call to signal end of frame. */ -+gceSTATUS -+gcoPROFILER_EndFrame( -+ IN gcoHAL Hal -+ ); -+ -+/* Call to signal end of draw. */ -+gceSTATUS -+gcoPROFILER_EndDraw( -+ IN gcoHAL Hal, -+ IN gctBOOL FirstDraw -+ ); -+ -+/* Increase profile counter Enum by Value. */ -+gceSTATUS -+gcoPROFILER_Count( -+ IN gcoHAL Hal, -+ IN gctUINT32 Enum, -+ IN gctINT Value -+ ); -+ -+/* Profile input vertex shader. */ -+gceSTATUS -+gcoPROFILER_ShaderVS( -+ IN gcoHAL Hal, -+ IN gctPOINTER Vs -+ ); -+ -+/* Profile input fragment shader. */ -+gceSTATUS -+gcoPROFILER_ShaderFS( -+ IN gcoHAL Hal, -+ IN gctPOINTER Fs -+ ); -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* __gc_hal_profiler_h_ */ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_raster.h linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_raster.h ---- linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_raster.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_raster.h 2015-11-30 17:56:13.592136927 +0100 -@@ -0,0 +1,1038 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#ifndef __gc_hal_raster_h_ -+#define __gc_hal_raster_h_ -+ -+#include "gc_hal_enum.h" -+#include "gc_hal_types.h" -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+/******************************************************************************\ -+****************************** Object Declarations ***************************** -+\******************************************************************************/ -+ -+typedef struct _gcoBRUSH * gcoBRUSH; -+typedef struct _gcoBRUSH_CACHE * gcoBRUSH_CACHE; -+ -+/******************************************************************************\ -+******************************** gcoBRUSH Object ******************************* -+\******************************************************************************/ -+ -+/* Create a new solid color gcoBRUSH object. */ -+gceSTATUS -+gcoBRUSH_ConstructSingleColor( -+ IN gcoHAL Hal, -+ IN gctUINT32 ColorConvert, -+ IN gctUINT32 Color, -+ IN gctUINT64 Mask, -+ gcoBRUSH * Brush -+ ); -+ -+/* Create a new monochrome gcoBRUSH object. */ -+gceSTATUS -+gcoBRUSH_ConstructMonochrome( -+ IN gcoHAL Hal, -+ IN gctUINT32 OriginX, -+ IN gctUINT32 OriginY, -+ IN gctUINT32 ColorConvert, -+ IN gctUINT32 FgColor, -+ IN gctUINT32 BgColor, -+ IN gctUINT64 Bits, -+ IN gctUINT64 Mask, -+ gcoBRUSH * Brush -+ ); -+ -+/* Create a color gcoBRUSH object. */ -+gceSTATUS -+gcoBRUSH_ConstructColor( -+ IN gcoHAL Hal, -+ IN gctUINT32 OriginX, -+ IN gctUINT32 OriginY, -+ IN gctPOINTER Address, -+ IN gceSURF_FORMAT Format, -+ IN gctUINT64 Mask, -+ gcoBRUSH * Brush -+ ); -+ -+/* Destroy an gcoBRUSH object. */ -+gceSTATUS -+gcoBRUSH_Destroy( -+ IN gcoBRUSH Brush -+ ); -+ -+/******************************************************************************\ -+******************************** gcoSURF Object ******************************* -+\******************************************************************************/ -+ -+/* Set cipping rectangle. */ -+gceSTATUS -+gcoSURF_SetClipping( -+ IN gcoSURF Surface -+ ); -+ -+/* Clear one or more rectangular areas. */ -+gceSTATUS -+gcoSURF_Clear2D( -+ IN gcoSURF DestSurface, -+ IN gctUINT32 RectCount, -+ IN gcsRECT_PTR DestRect, -+ IN gctUINT32 LoColor, -+ IN gctUINT32 HiColor -+ ); -+ -+/* Draw one or more Bresenham lines. */ -+gceSTATUS -+gcoSURF_Line( -+ IN gcoSURF Surface, -+ IN gctUINT32 LineCount, -+ IN gcsRECT_PTR Position, -+ IN gcoBRUSH Brush, -+ IN gctUINT8 FgRop, -+ IN gctUINT8 BgRop -+ ); -+ -+/* Generic rectangular blit. */ -+gceSTATUS -+gcoSURF_Blit( -+ IN OPTIONAL gcoSURF SrcSurface, -+ IN gcoSURF DestSurface, -+ IN gctUINT32 RectCount, -+ IN OPTIONAL gcsRECT_PTR SrcRect, -+ IN gcsRECT_PTR DestRect, -+ IN OPTIONAL gcoBRUSH Brush, -+ IN gctUINT8 FgRop, -+ IN gctUINT8 BgRop, -+ IN OPTIONAL gceSURF_TRANSPARENCY Transparency, -+ IN OPTIONAL gctUINT32 TransparencyColor, -+ IN OPTIONAL gctPOINTER Mask, -+ IN OPTIONAL gceSURF_MONOPACK MaskPack -+ ); -+ -+/* Monochrome blit. */ -+gceSTATUS -+gcoSURF_MonoBlit( -+ IN gcoSURF DestSurface, -+ IN gctPOINTER Source, -+ IN gceSURF_MONOPACK SourcePack, -+ IN gcsPOINT_PTR SourceSize, -+ IN gcsPOINT_PTR SourceOrigin, -+ IN gcsRECT_PTR DestRect, -+ IN OPTIONAL gcoBRUSH Brush, -+ IN gctUINT8 FgRop, -+ IN gctUINT8 BgRop, -+ IN gctBOOL ColorConvert, -+ IN gctUINT8 MonoTransparency, -+ IN gceSURF_TRANSPARENCY Transparency, -+ IN gctUINT32 FgColor, -+ IN gctUINT32 BgColor -+ ); -+ -+/* Filter blit. */ -+gceSTATUS -+gcoSURF_FilterBlit( -+ IN gcoSURF SrcSurface, -+ IN gcoSURF DestSurface, -+ IN gcsRECT_PTR SrcRect, -+ IN gcsRECT_PTR DestRect, -+ IN gcsRECT_PTR DestSubRect -+ ); -+ -+/* Enable alpha blending engine in the hardware and disengage the ROP engine. */ -+gceSTATUS -+gcoSURF_EnableAlphaBlend( -+ IN gcoSURF Surface, -+ IN gctUINT8 SrcGlobalAlphaValue, -+ IN gctUINT8 DstGlobalAlphaValue, -+ IN gceSURF_PIXEL_ALPHA_MODE SrcAlphaMode, -+ IN gceSURF_PIXEL_ALPHA_MODE DstAlphaMode, -+ IN gceSURF_GLOBAL_ALPHA_MODE SrcGlobalAlphaMode, -+ IN gceSURF_GLOBAL_ALPHA_MODE DstGlobalAlphaMode, -+ IN gceSURF_BLEND_FACTOR_MODE SrcFactorMode, -+ IN gceSURF_BLEND_FACTOR_MODE DstFactorMode, -+ IN gceSURF_PIXEL_COLOR_MODE SrcColorMode, -+ IN gceSURF_PIXEL_COLOR_MODE DstColorMode -+ ); -+ -+/* Disable alpha blending engine in the hardware and engage the ROP engine. */ -+gceSTATUS -+gcoSURF_DisableAlphaBlend( -+ IN gcoSURF Surface -+ ); -+ -+/* Copy a rectangular area with format conversion. */ -+gceSTATUS -+gcoSURF_CopyPixels( -+ IN gcoSURF Source, -+ IN gcoSURF Target, -+ IN gctINT SourceX, -+ IN gctINT SourceY, -+ IN gctINT TargetX, -+ IN gctINT TargetY, -+ IN gctINT Width, -+ IN gctINT Height -+ ); -+ -+/* Read surface pixel. */ -+gceSTATUS -+gcoSURF_ReadPixel( -+ IN gcoSURF Surface, -+ IN gctPOINTER Memory, -+ IN gctINT X, -+ IN gctINT Y, -+ IN gceSURF_FORMAT Format, -+ OUT gctPOINTER PixelValue -+ ); -+ -+/* Write surface pixel. */ -+gceSTATUS -+gcoSURF_WritePixel( -+ IN gcoSURF Surface, -+ IN gctPOINTER Memory, -+ IN gctINT X, -+ IN gctINT Y, -+ IN gceSURF_FORMAT Format, -+ IN gctPOINTER PixelValue -+ ); -+ -+gceSTATUS -+gcoSURF_SetDither( -+ IN gcoSURF Surface, -+ IN gctBOOL Dither -+ ); -+ -+gceSTATUS -+gcoSURF_Set2DSource( -+ gcoSURF Surface, -+ gceSURF_ROTATION Rotation -+ ); -+ -+gceSTATUS -+gcoSURF_Set2DTarget( -+ gcoSURF Surface, -+ gceSURF_ROTATION Rotation -+ ); -+ -+/******************************************************************************\ -+********************************** gco2D Object ********************************* -+\******************************************************************************/ -+ -+/* Construct a new gco2D object. */ -+gceSTATUS -+gco2D_Construct( -+ IN gcoHAL Hal, -+ OUT gco2D * Hardware -+ ); -+ -+/* Destroy an gco2D object. */ -+gceSTATUS -+gco2D_Destroy( -+ IN gco2D Hardware -+ ); -+ -+/* Sets the maximum number of brushes in the brush cache. */ -+gceSTATUS -+gco2D_SetBrushLimit( -+ IN gco2D Hardware, -+ IN gctUINT MaxCount -+ ); -+ -+/* Flush the brush. */ -+gceSTATUS -+gco2D_FlushBrush( -+ IN gco2D Engine, -+ IN gcoBRUSH Brush, -+ IN gceSURF_FORMAT Format -+ ); -+ -+/* Program the specified solid color brush. */ -+gceSTATUS -+gco2D_LoadSolidBrush( -+ IN gco2D Engine, -+ IN gceSURF_FORMAT Format, -+ IN gctUINT32 ColorConvert, -+ IN gctUINT32 Color, -+ IN gctUINT64 Mask -+ ); -+ -+gceSTATUS -+gco2D_LoadMonochromeBrush( -+ IN gco2D Engine, -+ IN gctUINT32 OriginX, -+ IN gctUINT32 OriginY, -+ IN gctUINT32 ColorConvert, -+ IN gctUINT32 FgColor, -+ IN gctUINT32 BgColor, -+ IN gctUINT64 Bits, -+ IN gctUINT64 Mask -+ ); -+ -+gceSTATUS -+gco2D_LoadColorBrush( -+ IN gco2D Engine, -+ IN gctUINT32 OriginX, -+ IN gctUINT32 OriginY, -+ IN gctUINT32 Address, -+ IN gceSURF_FORMAT Format, -+ IN gctUINT64 Mask -+ ); -+ -+/* Configure monochrome source. */ -+gceSTATUS -+gco2D_SetMonochromeSource( -+ IN gco2D Engine, -+ IN gctBOOL ColorConvert, -+ IN gctUINT8 MonoTransparency, -+ IN gceSURF_MONOPACK DataPack, -+ IN gctBOOL CoordRelative, -+ IN gceSURF_TRANSPARENCY Transparency, -+ IN gctUINT32 FgColor, -+ IN gctUINT32 BgColor -+ ); -+ -+/* Configure color source. */ -+gceSTATUS -+gco2D_SetColorSource( -+ IN gco2D Engine, -+ IN gctUINT32 Address, -+ IN gctUINT32 Stride, -+ IN gceSURF_FORMAT Format, -+ IN gceSURF_ROTATION Rotation, -+ IN gctUINT32 SurfaceWidth, -+ IN gctBOOL CoordRelative, -+ IN gceSURF_TRANSPARENCY Transparency, -+ IN gctUINT32 TransparencyColor -+ ); -+ -+/* Configure color source extension for full rotation. */ -+gceSTATUS -+gco2D_SetColorSourceEx( -+ IN gco2D Engine, -+ IN gctUINT32 Address, -+ IN gctUINT32 Stride, -+ IN gceSURF_FORMAT Format, -+ IN gceSURF_ROTATION Rotation, -+ IN gctUINT32 SurfaceWidth, -+ IN gctUINT32 SurfaceHeight, -+ IN gctBOOL CoordRelative, -+ IN gceSURF_TRANSPARENCY Transparency, -+ IN gctUINT32 TransparencyColor -+ ); -+ -+/* Configure color source. */ -+gceSTATUS -+gco2D_SetColorSourceAdvanced( -+ IN gco2D Engine, -+ IN gctUINT32 Address, -+ IN gctUINT32 Stride, -+ IN gceSURF_FORMAT Format, -+ IN gceSURF_ROTATION Rotation, -+ IN gctUINT32 SurfaceWidth, -+ IN gctUINT32 SurfaceHeight, -+ IN gctBOOL CoordRelative -+ ); -+ -+gceSTATUS -+gco2D_SetColorSourceN( -+ IN gco2D Engine, -+ IN gctUINT32 Address, -+ IN gctUINT32 Stride, -+ IN gceSURF_FORMAT Format, -+ IN gceSURF_ROTATION Rotation, -+ IN gctUINT32 SurfaceWidth, -+ IN gctUINT32 SurfaceHeight, -+ IN gctUINT32 SurfaceNumber -+ ); -+ -+/* Configure masked color source. */ -+gceSTATUS -+gco2D_SetMaskedSource( -+ IN gco2D Engine, -+ IN gctUINT32 Address, -+ IN gctUINT32 Stride, -+ IN gceSURF_FORMAT Format, -+ IN gctBOOL CoordRelative, -+ IN gceSURF_MONOPACK MaskPack -+ ); -+ -+/* Configure masked color source extension for full rotation. */ -+gceSTATUS -+gco2D_SetMaskedSourceEx( -+ IN gco2D Engine, -+ IN gctUINT32 Address, -+ IN gctUINT32 Stride, -+ IN gceSURF_FORMAT Format, -+ IN gctBOOL CoordRelative, -+ IN gceSURF_MONOPACK MaskPack, -+ IN gceSURF_ROTATION Rotation, -+ IN gctUINT32 SurfaceWidth, -+ IN gctUINT32 SurfaceHeight -+ ); -+ -+/* Setup the source rectangle. */ -+gceSTATUS -+gco2D_SetSource( -+ IN gco2D Engine, -+ IN gcsRECT_PTR SrcRect -+ ); -+ -+/* Set clipping rectangle. */ -+gceSTATUS -+gco2D_SetClipping( -+ IN gco2D Engine, -+ IN gcsRECT_PTR Rect -+ ); -+ -+/* Configure destination. */ -+gceSTATUS -+gco2D_SetTarget( -+ IN gco2D Engine, -+ IN gctUINT32 Address, -+ IN gctUINT32 Stride, -+ IN gceSURF_ROTATION Rotation, -+ IN gctUINT32 SurfaceWidth -+ ); -+ -+/* Configure destination extension for full rotation. */ -+gceSTATUS -+gco2D_SetTargetEx( -+ IN gco2D Engine, -+ IN gctUINT32 Address, -+ IN gctUINT32 Stride, -+ IN gceSURF_ROTATION Rotation, -+ IN gctUINT32 SurfaceWidth, -+ IN gctUINT32 SurfaceHeight -+ ); -+ -+/* Calculate and program the stretch factors. */ -+gceSTATUS -+gco2D_CalcStretchFactor( -+ IN gco2D Engine, -+ IN gctINT32 SrcSize, -+ IN gctINT32 DestSize, -+ OUT gctUINT32_PTR Factor -+ ); -+ -+gceSTATUS -+gco2D_SetStretchFactors( -+ IN gco2D Engine, -+ IN gctUINT32 HorFactor, -+ IN gctUINT32 VerFactor -+ ); -+ -+/* Calculate and program the stretch factors based on the rectangles. */ -+gceSTATUS -+gco2D_SetStretchRectFactors( -+ IN gco2D Engine, -+ IN gcsRECT_PTR SrcRect, -+ IN gcsRECT_PTR DestRect -+ ); -+ -+/* Create a new solid color gcoBRUSH object. */ -+gceSTATUS -+gco2D_ConstructSingleColorBrush( -+ IN gco2D Engine, -+ IN gctUINT32 ColorConvert, -+ IN gctUINT32 Color, -+ IN gctUINT64 Mask, -+ gcoBRUSH * Brush -+ ); -+ -+/* Create a new monochrome gcoBRUSH object. */ -+gceSTATUS -+gco2D_ConstructMonochromeBrush( -+ IN gco2D Engine, -+ IN gctUINT32 OriginX, -+ IN gctUINT32 OriginY, -+ IN gctUINT32 ColorConvert, -+ IN gctUINT32 FgColor, -+ IN gctUINT32 BgColor, -+ IN gctUINT64 Bits, -+ IN gctUINT64 Mask, -+ gcoBRUSH * Brush -+ ); -+ -+/* Create a color gcoBRUSH object. */ -+gceSTATUS -+gco2D_ConstructColorBrush( -+ IN gco2D Engine, -+ IN gctUINT32 OriginX, -+ IN gctUINT32 OriginY, -+ IN gctPOINTER Address, -+ IN gceSURF_FORMAT Format, -+ IN gctUINT64 Mask, -+ gcoBRUSH * Brush -+ ); -+ -+/* Clear one or more rectangular areas. */ -+gceSTATUS -+gco2D_Clear( -+ IN gco2D Engine, -+ IN gctUINT32 RectCount, -+ IN gcsRECT_PTR Rect, -+ IN gctUINT32 Color32, -+ IN gctUINT8 FgRop, -+ IN gctUINT8 BgRop, -+ IN gceSURF_FORMAT DestFormat -+ ); -+ -+/* Draw one or more Bresenham lines. */ -+gceSTATUS -+gco2D_Line( -+ IN gco2D Engine, -+ IN gctUINT32 LineCount, -+ IN gcsRECT_PTR Position, -+ IN gcoBRUSH Brush, -+ IN gctUINT8 FgRop, -+ IN gctUINT8 BgRop, -+ IN gceSURF_FORMAT DestFormat -+ ); -+ -+/* Draw one or more Bresenham lines based on the 32-bit color. */ -+gceSTATUS -+gco2D_ColorLine( -+ IN gco2D Engine, -+ IN gctUINT32 LineCount, -+ IN gcsRECT_PTR Position, -+ IN gctUINT32 Color32, -+ IN gctUINT8 FgRop, -+ IN gctUINT8 BgRop, -+ IN gceSURF_FORMAT DestFormat -+ ); -+ -+/* Generic blit. */ -+gceSTATUS -+gco2D_Blit( -+ IN gco2D Engine, -+ IN gctUINT32 RectCount, -+ IN gcsRECT_PTR Rect, -+ IN gctUINT8 FgRop, -+ IN gctUINT8 BgRop, -+ IN gceSURF_FORMAT DestFormat -+ ); -+ -+gceSTATUS -+gco2D_Blend( -+ IN gco2D Engine, -+ IN gctUINT32 SrcCount, -+ IN gctUINT32 RectCount, -+ IN gcsRECT_PTR Rect, -+ IN gctUINT8 FgRop, -+ IN gctUINT8 BgRop, -+ IN gceSURF_FORMAT DestFormat -+ ); -+ -+/* Batch blit. */ -+gceSTATUS -+gco2D_BatchBlit( -+ IN gco2D Engine, -+ IN gctUINT32 RectCount, -+ IN gcsRECT_PTR SrcRect, -+ IN gcsRECT_PTR DestRect, -+ IN gctUINT8 FgRop, -+ IN gctUINT8 BgRop, -+ IN gceSURF_FORMAT DestFormat -+ ); -+ -+/* Stretch blit. */ -+gceSTATUS -+gco2D_StretchBlit( -+ IN gco2D Engine, -+ IN gctUINT32 RectCount, -+ IN gcsRECT_PTR Rect, -+ IN gctUINT8 FgRop, -+ IN gctUINT8 BgRop, -+ IN gceSURF_FORMAT DestFormat -+ ); -+ -+/* Monochrome blit. */ -+gceSTATUS -+gco2D_MonoBlit( -+ IN gco2D Engine, -+ IN gctPOINTER StreamBits, -+ IN gcsPOINT_PTR StreamSize, -+ IN gcsRECT_PTR StreamRect, -+ IN gceSURF_MONOPACK SrcStreamPack, -+ IN gceSURF_MONOPACK DestStreamPack, -+ IN gcsRECT_PTR DestRect, -+ IN gctUINT32 FgRop, -+ IN gctUINT32 BgRop, -+ IN gceSURF_FORMAT DestFormat -+ ); -+ -+gceSTATUS -+gco2D_MonoBlitEx( -+ IN gco2D Engine, -+ IN gctPOINTER StreamBits, -+ IN gctINT32 StreamStride, -+ IN gctINT32 StreamWidth, -+ IN gctINT32 StreamHeight, -+ IN gctINT32 StreamX, -+ IN gctINT32 StreamY, -+ IN gctUINT32 FgColor, -+ IN gctUINT32 BgColor, -+ IN gcsRECT_PTR SrcRect, -+ IN gcsRECT_PTR DstRect, -+ IN gctUINT8 FgRop, -+ IN gctUINT8 BgRop -+ ); -+ -+/* Set kernel size. */ -+gceSTATUS -+gco2D_SetKernelSize( -+ IN gco2D Engine, -+ IN gctUINT8 HorKernelSize, -+ IN gctUINT8 VerKernelSize -+ ); -+ -+/* Set filter type. */ -+gceSTATUS -+gco2D_SetFilterType( -+ IN gco2D Engine, -+ IN gceFILTER_TYPE FilterType -+ ); -+ -+/* Set the filter kernel by user. */ -+gceSTATUS -+gco2D_SetUserFilterKernel( -+ IN gco2D Engine, -+ IN gceFILTER_PASS_TYPE PassType, -+ IN gctUINT16_PTR KernelArray -+ ); -+ -+/* Select the pass(es) to be done for user defined filter. */ -+gceSTATUS -+gco2D_EnableUserFilterPasses( -+ IN gco2D Engine, -+ IN gctBOOL HorPass, -+ IN gctBOOL VerPass -+ ); -+ -+/* Frees the temporary buffer allocated by filter blit operation. */ -+gceSTATUS -+gco2D_FreeFilterBuffer( -+ IN gco2D Engine -+ ); -+ -+/* Filter blit. */ -+gceSTATUS -+gco2D_FilterBlit( -+ IN gco2D Engine, -+ IN gctUINT32 SrcAddress, -+ IN gctUINT SrcStride, -+ IN gctUINT32 SrcUAddress, -+ IN gctUINT SrcUStride, -+ IN gctUINT32 SrcVAddress, -+ IN gctUINT SrcVStride, -+ IN gceSURF_FORMAT SrcFormat, -+ IN gceSURF_ROTATION SrcRotation, -+ IN gctUINT32 SrcSurfaceWidth, -+ IN gcsRECT_PTR SrcRect, -+ IN gctUINT32 DestAddress, -+ IN gctUINT DestStride, -+ IN gceSURF_FORMAT DestFormat, -+ IN gceSURF_ROTATION DestRotation, -+ IN gctUINT32 DestSurfaceWidth, -+ IN gcsRECT_PTR DestRect, -+ IN gcsRECT_PTR DestSubRect -+ ); -+ -+/* Filter blit extension for full rotation. */ -+gceSTATUS -+gco2D_FilterBlitEx( -+ IN gco2D Engine, -+ IN gctUINT32 SrcAddress, -+ IN gctUINT SrcStride, -+ IN gctUINT32 SrcUAddress, -+ IN gctUINT SrcUStride, -+ IN gctUINT32 SrcVAddress, -+ IN gctUINT SrcVStride, -+ IN gceSURF_FORMAT SrcFormat, -+ IN gceSURF_ROTATION SrcRotation, -+ IN gctUINT32 SrcSurfaceWidth, -+ IN gctUINT32 SrcSurfaceHeight, -+ IN gcsRECT_PTR SrcRect, -+ IN gctUINT32 DestAddress, -+ IN gctUINT DestStride, -+ IN gceSURF_FORMAT DestFormat, -+ IN gceSURF_ROTATION DestRotation, -+ IN gctUINT32 DestSurfaceWidth, -+ IN gctUINT32 DestSurfaceHeight, -+ IN gcsRECT_PTR DestRect, -+ IN gcsRECT_PTR DestSubRect -+ ); -+ -+gceSTATUS -+gco2D_FilterBlitEx2( -+ IN gco2D Engine, -+ IN gctUINT32_PTR SrcAddresses, -+ IN gctUINT32 SrcAddressNum, -+ IN gctUINT32_PTR SrcStrides, -+ IN gctUINT32 SrcStrideNum, -+ IN gceTILING SrcTiling, -+ IN gceSURF_FORMAT SrcFormat, -+ IN gceSURF_ROTATION SrcRotation, -+ IN gctUINT32 SrcSurfaceWidth, -+ IN gctUINT32 SrcSurfaceHeight, -+ IN gcsRECT_PTR SrcRect, -+ IN gctUINT32_PTR DestAddresses, -+ IN gctUINT32 DestAddressNum, -+ IN gctUINT32_PTR DestStrides, -+ IN gctUINT32 DestStrideNum, -+ IN gceTILING DestTiling, -+ IN gceSURF_FORMAT DestFormat, -+ IN gceSURF_ROTATION DestRotation, -+ IN gctUINT32 DestSurfaceWidth, -+ IN gctUINT32 DestSurfaceHeight, -+ IN gcsRECT_PTR DestRect, -+ IN gcsRECT_PTR DestSubRect -+ ); -+ -+/* Enable alpha blending engine in the hardware and disengage the ROP engine. */ -+gceSTATUS -+gco2D_EnableAlphaBlend( -+ IN gco2D Engine, -+ IN gctUINT8 SrcGlobalAlphaValue, -+ IN gctUINT8 DstGlobalAlphaValue, -+ IN gceSURF_PIXEL_ALPHA_MODE SrcAlphaMode, -+ IN gceSURF_PIXEL_ALPHA_MODE DstAlphaMode, -+ IN gceSURF_GLOBAL_ALPHA_MODE SrcGlobalAlphaMode, -+ IN gceSURF_GLOBAL_ALPHA_MODE DstGlobalAlphaMode, -+ IN gceSURF_BLEND_FACTOR_MODE SrcFactorMode, -+ IN gceSURF_BLEND_FACTOR_MODE DstFactorMode, -+ IN gceSURF_PIXEL_COLOR_MODE SrcColorMode, -+ IN gceSURF_PIXEL_COLOR_MODE DstColorMode -+ ); -+ -+/* Enable alpha blending engine in the hardware. */ -+gceSTATUS -+gco2D_EnableAlphaBlendAdvanced( -+ IN gco2D Engine, -+ IN gceSURF_PIXEL_ALPHA_MODE SrcAlphaMode, -+ IN gceSURF_PIXEL_ALPHA_MODE DstAlphaMode, -+ IN gceSURF_GLOBAL_ALPHA_MODE SrcGlobalAlphaMode, -+ IN gceSURF_GLOBAL_ALPHA_MODE DstGlobalAlphaMode, -+ IN gceSURF_BLEND_FACTOR_MODE SrcFactorMode, -+ IN gceSURF_BLEND_FACTOR_MODE DstFactorMode -+ ); -+ -+/* Enable alpha blending engine with Porter Duff rule. */ -+gceSTATUS -+gco2D_SetPorterDuffBlending( -+ IN gco2D Engine, -+ IN gce2D_PORTER_DUFF_RULE Rule -+ ); -+ -+/* Disable alpha blending engine in the hardware and engage the ROP engine. */ -+gceSTATUS -+gco2D_DisableAlphaBlend( -+ IN gco2D Engine -+ ); -+ -+/* Retrieve the maximum number of 32-bit data chunks for a single DE command. */ -+gctUINT32 -+gco2D_GetMaximumDataCount( -+ void -+ ); -+ -+/* Retrieve the maximum number of rectangles, that can be passed in a single DE command. */ -+gctUINT32 -+gco2D_GetMaximumRectCount( -+ void -+ ); -+ -+/* Returns the pixel alignment of the surface. */ -+gceSTATUS -+gco2D_GetPixelAlignment( -+ gceSURF_FORMAT Format, -+ gcsPOINT_PTR Alignment -+ ); -+ -+/* Retrieve monochrome stream pack size. */ -+gceSTATUS -+gco2D_GetPackSize( -+ IN gceSURF_MONOPACK StreamPack, -+ OUT gctUINT32 * PackWidth, -+ OUT gctUINT32 * PackHeight -+ ); -+ -+/* Flush the 2D pipeline. */ -+gceSTATUS -+gco2D_Flush( -+ IN gco2D Engine -+ ); -+ -+/* Load 256-entry color table for INDEX8 source surfaces. */ -+gceSTATUS -+gco2D_LoadPalette( -+ IN gco2D Engine, -+ IN gctUINT FirstIndex, -+ IN gctUINT IndexCount, -+ IN gctPOINTER ColorTable, -+ IN gctBOOL ColorConvert -+ ); -+ -+/* Enable/disable 2D BitBlt mirrorring. */ -+gceSTATUS -+gco2D_SetBitBlitMirror( -+ IN gco2D Engine, -+ IN gctBOOL HorizontalMirror, -+ IN gctBOOL VerticalMirror -+ ); -+ -+/* -+ * Set the transparency for source, destination and pattern. -+ * It also enable or disable the DFB color key mode. -+ */ -+gceSTATUS -+gco2D_SetTransparencyAdvancedEx( -+ IN gco2D Engine, -+ IN gce2D_TRANSPARENCY SrcTransparency, -+ IN gce2D_TRANSPARENCY DstTransparency, -+ IN gce2D_TRANSPARENCY PatTransparency, -+ IN gctBOOL EnableDFBColorKeyMode -+ ); -+ -+/* Set the transparency for source, destination and pattern. */ -+gceSTATUS -+gco2D_SetTransparencyAdvanced( -+ IN gco2D Engine, -+ IN gce2D_TRANSPARENCY SrcTransparency, -+ IN gce2D_TRANSPARENCY DstTransparency, -+ IN gce2D_TRANSPARENCY PatTransparency -+ ); -+ -+/* Set the source color key. */ -+gceSTATUS -+gco2D_SetSourceColorKeyAdvanced( -+ IN gco2D Engine, -+ IN gctUINT32 ColorKey -+ ); -+ -+/* Set the source color key range. */ -+gceSTATUS -+gco2D_SetSourceColorKeyRangeAdvanced( -+ IN gco2D Engine, -+ IN gctUINT32 ColorKeyLow, -+ IN gctUINT32 ColorKeyHigh -+ ); -+ -+/* Set the target color key. */ -+gceSTATUS -+gco2D_SetTargetColorKeyAdvanced( -+ IN gco2D Engine, -+ IN gctUINT32 ColorKey -+ ); -+ -+/* Set the target color key range. */ -+gceSTATUS -+gco2D_SetTargetColorKeyRangeAdvanced( -+ IN gco2D Engine, -+ IN gctUINT32 ColorKeyLow, -+ IN gctUINT32 ColorKeyHigh -+ ); -+ -+/* Set the YUV color space mode. */ -+gceSTATUS -+gco2D_SetYUVColorMode( -+ IN gco2D Engine, -+ IN gce2D_YUV_COLOR_MODE Mode -+ ); -+ -+/* Setup the source global color value in ARGB8 format. */ -+gceSTATUS gco2D_SetSourceGlobalColorAdvanced( -+ IN gco2D Engine, -+ IN gctUINT32 Color32 -+ ); -+ -+/* Setup the target global color value in ARGB8 format. */ -+gceSTATUS gco2D_SetTargetGlobalColorAdvanced( -+ IN gco2D Engine, -+ IN gctUINT32 Color32 -+ ); -+ -+/* Setup the source and target pixel multiply modes. */ -+gceSTATUS -+gco2D_SetPixelMultiplyModeAdvanced( -+ IN gco2D Engine, -+ IN gce2D_PIXEL_COLOR_MULTIPLY_MODE SrcPremultiplySrcAlpha, -+ IN gce2D_PIXEL_COLOR_MULTIPLY_MODE DstPremultiplyDstAlpha, -+ IN gce2D_GLOBAL_COLOR_MULTIPLY_MODE SrcPremultiplyGlobalMode, -+ IN gce2D_PIXEL_COLOR_MULTIPLY_MODE DstDemultiplyDstAlpha -+ ); -+ -+/* Set the GPU clock cycles after which the idle engine will keep auto-flushing. */ -+gceSTATUS -+gco2D_SetAutoFlushCycles( -+ IN gco2D Engine, -+ IN gctUINT32 Cycles -+ ); -+ -+#if VIVANTE_PROFILER -+/* Read the profile registers available in the 2D engine and sets them in the profile. -+ The function will also reset the pixelsRendered counter every time. -+*/ -+gceSTATUS -+gco2D_ProfileEngine( -+ IN gco2D Engine, -+ OPTIONAL gcs2D_PROFILE_PTR Profile -+ ); -+#endif -+ -+/* Enable or disable 2D dithering. */ -+gceSTATUS -+gco2D_EnableDither( -+ IN gco2D Engine, -+ IN gctBOOL Enable -+ ); -+ -+gceSTATUS -+gco2D_SetGenericSource( -+ IN gco2D Engine, -+ IN gctUINT32_PTR Addresses, -+ IN gctUINT32 AddressNum, -+ IN gctUINT32_PTR Strides, -+ IN gctUINT32 StrideNum, -+ IN gceTILING Tiling, -+ IN gceSURF_FORMAT Format, -+ IN gceSURF_ROTATION Rotation, -+ IN gctUINT32 SurfaceWidth, -+ IN gctUINT32 SurfaceHeight -+); -+ -+gceSTATUS -+gco2D_SetGenericTarget( -+ IN gco2D Engine, -+ IN gctUINT32_PTR Addresses, -+ IN gctUINT32 AddressNum, -+ IN gctUINT32_PTR Strides, -+ IN gctUINT32 StrideNum, -+ IN gceTILING Tiling, -+ IN gceSURF_FORMAT Format, -+ IN gceSURF_ROTATION Rotation, -+ IN gctUINT32 SurfaceWidth, -+ IN gctUINT32 SurfaceHeight -+); -+ -+gceSTATUS -+gco2D_SetCurrentSourceIndex( -+ IN gco2D Engine, -+ IN gctUINT32 SrcIndex -+ ); -+ -+gceSTATUS -+gco2D_MultiSourceBlit( -+ IN gco2D Engine, -+ IN gctUINT32 SourceMask, -+ IN gcsRECT_PTR DestRect, -+ IN gctUINT32 RectCount -+ ); -+ -+gceSTATUS -+gco2D_SetROP( -+ IN gco2D Engine, -+ IN gctUINT8 FgRop, -+ IN gctUINT8 BgRop -+ ); -+ -+gceSTATUS -+gco2D_SetGdiStretchMode( -+ IN gco2D Engine, -+ IN gctBOOL Enable -+ ); -+ -+gceSTATUS -+gco2D_SetSourceTileStatus( -+ IN gco2D Engine, -+ IN gce2D_TILE_STATUS_CONFIG TSControl, -+ IN gceSURF_FORMAT CompressedFormat, -+ IN gctUINT32 ClearValue, -+ IN gctUINT32 GpuAddress -+ ); -+ -+gceSTATUS -+gco2D_SetTargetTileStatus( -+ IN gco2D Engine, -+ IN gce2D_TILE_STATUS_CONFIG TileStatusConfig, -+ IN gceSURF_FORMAT CompressedFormat, -+ IN gctUINT32 ClearValue, -+ IN gctUINT32 GpuAddress -+ ); -+ -+gceSTATUS -+gco2D_QueryU32( -+ IN gco2D Engine, -+ IN gce2D_QUERY Item, -+ OUT gctUINT32_PTR Value -+ ); -+ -+gceSTATUS -+gco2D_SetStateU32( -+ IN gco2D Engine, -+ IN gce2D_STATE State, -+ IN gctUINT32 Value -+ ); -+ -+gceSTATUS -+gco2D_SetStateArrayI32( -+ IN gco2D Engine, -+ IN gce2D_STATE State, -+ IN gctINT32_PTR Array, -+ IN gctINT32 ArraySize -+ ); -+ -+gceSTATUS -+gco2D_SetStateArrayU32( -+ IN gco2D Engine, -+ IN gce2D_STATE State, -+ IN gctUINT32_PTR Array, -+ IN gctINT32 ArraySize -+ ); -+ -+gceSTATUS -+gco2D_SetTargetRect( -+ IN gco2D Engine, -+ IN gcsRECT_PTR Rect -+ ); -+ -+gceSTATUS -+gco2D_Set2DEngine( -+ IN gco2D Engine -+ ); -+ -+gceSTATUS -+gco2D_UnSet2DEngine( -+ IN gco2D Engine -+ ); -+ -+gceSTATUS -+gco2D_Get2DEngine( -+ OUT gco2D * Engine -+ ); -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* __gc_hal_raster_h_ */ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_rename.h linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_rename.h ---- linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_rename.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_rename.h 2015-11-30 17:56:13.596136660 +0100 -@@ -0,0 +1,243 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#ifndef __gc_hal_rename_h_ -+#define __gc_hal_rename_h_ -+ -+ -+#if defined(_HAL2D_APPENDIX) -+ -+#define _HAL2D_RENAME_2(api, appendix) api ## appendix -+#define _HAL2D_RENAME_1(api, appendix) _HAL2D_RENAME_2(api, appendix) -+#define gcmHAL2D(api) _HAL2D_RENAME_1(api, _HAL2D_APPENDIX) -+ -+ -+#define gckOS_Construct gcmHAL2D(gckOS_Construct) -+#define gckOS_Destroy gcmHAL2D(gckOS_Destroy) -+#define gckOS_QueryVideoMemory gcmHAL2D(gckOS_QueryVideoMemory) -+#define gckOS_Allocate gcmHAL2D(gckOS_Allocate) -+#define gckOS_Free gcmHAL2D(gckOS_Free) -+#define gckOS_AllocateMemory gcmHAL2D(gckOS_AllocateMemory) -+#define gckOS_FreeMemory gcmHAL2D(gckOS_FreeMemory) -+#define gckOS_AllocatePagedMemory gcmHAL2D(gckOS_AllocatePagedMemory) -+#define gckOS_AllocatePagedMemoryEx gcmHAL2D(gckOS_AllocatePagedMemoryEx) -+#define gckOS_LockPages gcmHAL2D(gckOS_LockPages) -+#define gckOS_MapPages gcmHAL2D(gckOS_MapPages) -+#define gckOS_UnlockPages gcmHAL2D(gckOS_UnlockPages) -+#define gckOS_FreePagedMemory gcmHAL2D(gckOS_FreePagedMemory) -+#define gckOS_AllocateNonPagedMemory gcmHAL2D(gckOS_AllocateNonPagedMemory) -+#define gckOS_FreeNonPagedMemory gcmHAL2D(gckOS_FreeNonPagedMemory) -+#define gckOS_AllocateContiguous gcmHAL2D(gckOS_AllocateContiguous) -+#define gckOS_FreeContiguous gcmHAL2D(gckOS_FreeContiguous) -+#define gckOS_GetPageSize gcmHAL2D(gckOS_GetPageSize) -+#define gckOS_GetPhysicalAddress gcmHAL2D(gckOS_GetPhysicalAddress) -+#define gckOS_UserLogicalToPhysical gcmHAL2D(gckOS_UserLogicalToPhysical) -+#define gckOS_GetPhysicalAddressProcess gcmHAL2D(gckOS_GetPhysicalAddressProcess) -+#define gckOS_MapPhysical gcmHAL2D(gckOS_MapPhysical) -+#define gckOS_UnmapPhysical gcmHAL2D(gckOS_UnmapPhysical) -+#define gckOS_ReadRegister gcmHAL2D(gckOS_ReadRegister) -+#define gckOS_WriteRegister gcmHAL2D(gckOS_WriteRegister) -+#define gckOS_WriteMemory gcmHAL2D(gckOS_WriteMemory) -+#define gckOS_MapMemory gcmHAL2D(gckOS_MapMemory) -+#define gckOS_UnmapMemory gcmHAL2D(gckOS_UnmapMemory) -+#define gckOS_UnmapMemoryEx gcmHAL2D(gckOS_UnmapMemoryEx) -+#define gckOS_CreateMutex gcmHAL2D(gckOS_CreateMutex) -+#define gckOS_DeleteMutex gcmHAL2D(gckOS_DeleteMutex) -+#define gckOS_AcquireMutex gcmHAL2D(gckOS_AcquireMutex) -+#define gckOS_ReleaseMutex gcmHAL2D(gckOS_ReleaseMutex) -+#define gckOS_AtomicExchange gcmHAL2D(gckOS_AtomicExchange) -+#define gckOS_AtomicExchangePtr gcmHAL2D(gckOS_AtomicExchangePtr) -+#define gckOS_AtomConstruct gcmHAL2D(gckOS_AtomConstruct) -+#define gckOS_AtomDestroy gcmHAL2D(gckOS_AtomDestroy) -+#define gckOS_AtomGet gcmHAL2D(gckOS_AtomGet) -+#define gckOS_AtomIncrement gcmHAL2D(gckOS_AtomIncrement) -+#define gckOS_AtomDecrement gcmHAL2D(gckOS_AtomDecrement) -+#define gckOS_Delay gcmHAL2D(gckOS_Delay) -+#define gckOS_GetTime gcmHAL2D(gckOS_GetTime) -+#define gckOS_MemoryBarrier gcmHAL2D(gckOS_MemoryBarrier) -+#define gckOS_MapUserPointer gcmHAL2D(gckOS_MapUserPointer) -+#define gckOS_UnmapUserPointer gcmHAL2D(gckOS_UnmapUserPointer) -+#define gckOS_QueryNeedCopy gcmHAL2D(gckOS_QueryNeedCopy) -+#define gckOS_CopyFromUserData gcmHAL2D(gckOS_CopyFromUserData) -+#define gckOS_CopyToUserData gcmHAL2D(gckOS_CopyToUserData) -+#define gckOS_SuspendInterrupt gcmHAL2D(gckOS_SuspendInterrupt) -+#define gckOS_ResumeInterrupt gcmHAL2D(gckOS_ResumeInterrupt) -+#define gckOS_GetBaseAddress gcmHAL2D(gckOS_GetBaseAddress) -+#define gckOS_MemCopy gcmHAL2D(gckOS_MemCopy) -+#define gckOS_ZeroMemory gcmHAL2D(gckOS_ZeroMemory) -+#define gckOS_DeviceControl gcmHAL2D(gckOS_DeviceControl) -+#define gckOS_GetProcessID gcmHAL2D(gckOS_GetProcessID) -+#define gckOS_GetThreadID gcmHAL2D(gckOS_GetThreadID) -+#define gckOS_CreateSignal gcmHAL2D(gckOS_CreateSignal) -+#define gckOS_DestroySignal gcmHAL2D(gckOS_DestroySignal) -+#define gckOS_Signal gcmHAL2D(gckOS_Signal) -+#define gckOS_WaitSignal gcmHAL2D(gckOS_WaitSignal) -+#define gckOS_MapSignal gcmHAL2D(gckOS_MapSignal) -+#define gckOS_MapUserMemory gcmHAL2D(gckOS_MapUserMemory) -+#define gckOS_UnmapUserMemory gcmHAL2D(gckOS_UnmapUserMemory) -+#define gckOS_CreateUserSignal gcmHAL2D(gckOS_CreateUserSignal) -+#define gckOS_DestroyUserSignal gcmHAL2D(gckOS_DestroyUserSignal) -+#define gckOS_WaitUserSignal gcmHAL2D(gckOS_WaitUserSignal) -+#define gckOS_SignalUserSignal gcmHAL2D(gckOS_SignalUserSignal) -+#define gckOS_UserSignal gcmHAL2D(gckOS_UserSignal) -+#define gckOS_UserSignal gcmHAL2D(gckOS_UserSignal) -+#define gckOS_CacheClean gcmHAL2D(gckOS_CacheClean) -+#define gckOS_CacheFlush gcmHAL2D(gckOS_CacheFlush) -+#define gckOS_SetDebugLevel gcmHAL2D(gckOS_SetDebugLevel) -+#define gckOS_SetDebugZone gcmHAL2D(gckOS_SetDebugZone) -+#define gckOS_SetDebugLevelZone gcmHAL2D(gckOS_SetDebugLevelZone) -+#define gckOS_SetDebugZones gcmHAL2D(gckOS_SetDebugZones) -+#define gckOS_SetDebugFile gcmHAL2D(gckOS_SetDebugFile) -+#define gckOS_Broadcast gcmHAL2D(gckOS_Broadcast) -+#define gckOS_SetGPUPower gcmHAL2D(gckOS_SetGPUPower) -+#define gckOS_CreateSemaphore gcmHAL2D(gckOS_CreateSemaphore) -+#define gckOS_DestroySemaphore gcmHAL2D(gckOS_DestroySemaphore) -+#define gckOS_AcquireSemaphore gcmHAL2D(gckOS_AcquireSemaphore) -+#define gckOS_ReleaseSemaphore gcmHAL2D(gckOS_ReleaseSemaphore) -+#define gckHEAP_Construct gcmHAL2D(gckHEAP_Construct) -+#define gckHEAP_Destroy gcmHAL2D(gckHEAP_Destroy) -+#define gckHEAP_Allocate gcmHAL2D(gckHEAP_Allocate) -+#define gckHEAP_Free gcmHAL2D(gckHEAP_Free) -+#define gckHEAP_ProfileStart gcmHAL2D(gckHEAP_ProfileStart) -+#define gckHEAP_ProfileEnd gcmHAL2D(gckHEAP_ProfileEnd) -+#define gckHEAP_Test gcmHAL2D(gckHEAP_Test) -+#define gckVIDMEM_Construct gcmHAL2D(gckVIDMEM_Construct) -+#define gckVIDMEM_Destroy gcmHAL2D(gckVIDMEM_Destroy) -+#define gckVIDMEM_Allocate gcmHAL2D(gckVIDMEM_Allocate) -+#define gckVIDMEM_AllocateLinear gcmHAL2D(gckVIDMEM_AllocateLinear) -+#define gckVIDMEM_Free gcmHAL2D(gckVIDMEM_Free) -+#define gckVIDMEM_Lock gcmHAL2D(gckVIDMEM_Lock) -+#define gckVIDMEM_Unlock gcmHAL2D(gckVIDMEM_Unlock) -+#define gckVIDMEM_ConstructVirtual gcmHAL2D(gckVIDMEM_ConstructVirtual) -+#define gckVIDMEM_DestroyVirtual gcmHAL2D(gckVIDMEM_DestroyVirtual) -+#define gckKERNEL_Construct gcmHAL2D(gckKERNEL_Construct) -+#define gckKERNEL_Destroy gcmHAL2D(gckKERNEL_Destroy) -+#define gckKERNEL_Dispatch gcmHAL2D(gckKERNEL_Dispatch) -+#define gckKERNEL_QueryVideoMemory gcmHAL2D(gckKERNEL_QueryVideoMemory) -+#define gckKERNEL_GetVideoMemoryPool gcmHAL2D(gckKERNEL_GetVideoMemoryPool) -+#define gckKERNEL_MapVideoMemory gcmHAL2D(gckKERNEL_MapVideoMemory) -+#define gckKERNEL_UnmapVideoMemory gcmHAL2D(gckKERNEL_UnmapVideoMemory) -+#define gckKERNEL_MapMemory gcmHAL2D(gckKERNEL_MapMemory) -+#define gckKERNEL_UnmapMemory gcmHAL2D(gckKERNEL_UnmapMemory) -+#define gckKERNEL_Notify gcmHAL2D(gckKERNEL_Notify) -+#define gckKERNEL_QuerySettings gcmHAL2D(gckKERNEL_QuerySettings) -+#define gckKERNEL_Recovery gcmHAL2D(gckKERNEL_Recovery) -+#define gckKERNEL_OpenUserData gcmHAL2D(gckKERNEL_OpenUserData) -+#define gckKERNEL_CloseUserData gcmHAL2D(gckKERNEL_CloseUserData) -+#define gckHARDWARE_Construct gcmHAL2D(gckHARDWARE_Construct) -+#define gckHARDWARE_Destroy gcmHAL2D(gckHARDWARE_Destroy) -+#define gckHARDWARE_QuerySystemMemory gcmHAL2D(gckHARDWARE_QuerySystemMemory) -+#define gckHARDWARE_BuildVirtualAddress gcmHAL2D(gckHARDWARE_BuildVirtualAddress) -+#define gckHARDWARE_QueryCommandBuffer gcmHAL2D(gckHARDWARE_QueryCommandBuffer) -+#define gckHARDWARE_WaitLink gcmHAL2D(gckHARDWARE_WaitLink) -+#define gckHARDWARE_Execute gcmHAL2D(gckHARDWARE_Execute) -+#define gckHARDWARE_End gcmHAL2D(gckHARDWARE_End) -+#define gckHARDWARE_Nop gcmHAL2D(gckHARDWARE_Nop) -+#define gckHARDWARE_PipeSelect gcmHAL2D(gckHARDWARE_PipeSelect) -+#define gckHARDWARE_Link gcmHAL2D(gckHARDWARE_Link) -+#define gckHARDWARE_Event gcmHAL2D(gckHARDWARE_Event) -+#define gckHARDWARE_QueryMemory gcmHAL2D(gckHARDWARE_QueryMemory) -+#define gckHARDWARE_QueryChipIdentity gcmHAL2D(gckHARDWARE_QueryChipIdentity) -+#define gckHARDWARE_QueryChipSpecs gcmHAL2D(gckHARDWARE_QueryChipSpecs) -+#define gckHARDWARE_QueryShaderCaps gcmHAL2D(gckHARDWARE_QueryShaderCaps) -+#define gckHARDWARE_ConvertFormat gcmHAL2D(gckHARDWARE_ConvertFormat) -+#define gckHARDWARE_SplitMemory gcmHAL2D(gckHARDWARE_SplitMemory) -+#define gckHARDWARE_AlignToTile gcmHAL2D(gckHARDWARE_AlignToTile) -+#define gckHARDWARE_UpdateQueueTail gcmHAL2D(gckHARDWARE_UpdateQueueTail) -+#define gckHARDWARE_ConvertLogical gcmHAL2D(gckHARDWARE_ConvertLogical) -+#define gckHARDWARE_Interrupt gcmHAL2D(gckHARDWARE_Interrupt) -+#define gckHARDWARE_SetMMU gcmHAL2D(gckHARDWARE_SetMMU) -+#define gckHARDWARE_FlushMMU gcmHAL2D(gckHARDWARE_FlushMMU) -+#define gckHARDWARE_GetIdle gcmHAL2D(gckHARDWARE_GetIdle) -+#define gckHARDWARE_Flush gcmHAL2D(gckHARDWARE_Flush) -+#define gckHARDWARE_SetFastClear gcmHAL2D(gckHARDWARE_SetFastClear) -+#define gckHARDWARE_ReadInterrupt gcmHAL2D(gckHARDWARE_ReadInterrupt) -+#define gckHARDWARE_SetPowerManagementState gcmHAL2D(gckHARDWARE_SetPowerManagementState) -+#define gckHARDWARE_QueryPowerManagementState gcmHAL2D(gckHARDWARE_QueryPowerManagementState) -+#define gckHARDWARE_ProfileEngine2D gcmHAL2D(gckHARDWARE_ProfileEngine2D) -+#define gckHARDWARE_InitializeHardware gcmHAL2D(gckHARDWARE_InitializeHardware) -+#define gckHARDWARE_Reset gcmHAL2D(gckHARDWARE_Reset) -+#define gckINTERRUPT_Construct gcmHAL2D(gckINTERRUPT_Construct) -+#define gckINTERRUPT_Destroy gcmHAL2D(gckINTERRUPT_Destroy) -+#define gckINTERRUPT_SetHandler gcmHAL2D(gckINTERRUPT_SetHandler) -+#define gckINTERRUPT_Notify gcmHAL2D(gckINTERRUPT_Notify) -+#define gckEVENT_Construct gcmHAL2D(gckEVENT_Construct) -+#define gckEVENT_Destroy gcmHAL2D(gckEVENT_Destroy) -+#define gckEVENT_AddList gcmHAL2D(gckEVENT_AddList) -+#define gckEVENT_FreeNonPagedMemory gcmHAL2D(gckEVENT_FreeNonPagedMemory) -+#define gckEVENT_FreeContiguousMemory gcmHAL2D(gckEVENT_FreeContiguousMemory) -+#define gckEVENT_FreeVideoMemory gcmHAL2D(gckEVENT_FreeVideoMemory) -+#define gckEVENT_Signal gcmHAL2D(gckEVENT_Signal) -+#define gckEVENT_Unlock gcmHAL2D(gckEVENT_Unlock) -+#define gckEVENT_Submit gcmHAL2D(gckEVENT_Submit) -+#define gckEVENT_Commit gcmHAL2D(gckEVENT_Commit) -+#define gckEVENT_Notify gcmHAL2D(gckEVENT_Notify) -+#define gckEVENT_Interrupt gcmHAL2D(gckEVENT_Interrupt) -+#define gckCOMMAND_Construct gcmHAL2D(gckCOMMAND_Construct) -+#define gckCOMMAND_Destroy gcmHAL2D(gckCOMMAND_Destroy) -+#define gckCOMMAND_EnterCommit gcmHAL2D(gckCOMMAND_EnterCommit) -+#define gckCOMMAND_ExitCommit gcmHAL2D(gckCOMMAND_ExitCommit) -+#define gckCOMMAND_Start gcmHAL2D(gckCOMMAND_Start) -+#define gckCOMMAND_Stop gcmHAL2D(gckCOMMAND_Stop) -+#define gckCOMMAND_Commit gcmHAL2D(gckCOMMAND_Commit) -+#define gckCOMMAND_Reserve gcmHAL2D(gckCOMMAND_Reserve) -+#define gckCOMMAND_Execute gcmHAL2D(gckCOMMAND_Execute) -+#define gckCOMMAND_Stall gcmHAL2D(gckCOMMAND_Stall) -+#define gckCOMMAND_Attach gcmHAL2D(gckCOMMAND_Attach) -+#define gckCOMMAND_Detach gcmHAL2D(gckCOMMAND_Detach) -+#define gckMMU_Construct gcmHAL2D(gckMMU_Construct) -+#define gckMMU_Destroy gcmHAL2D(gckMMU_Destroy) -+#define gckMMU_AllocatePages gcmHAL2D(gckMMU_AllocatePages) -+#define gckMMU_FreePages gcmHAL2D(gckMMU_FreePages) -+#define gckMMU_Test gcmHAL2D(gckMMU_Test) -+#define gckHARDWARE_QueryProfileRegisters gcmHAL2D(gckHARDWARE_QueryProfileRegisters) -+ -+ -+#define FindMdlMap gcmHAL2D(FindMdlMap) -+#define OnProcessExit gcmHAL2D(OnProcessExit) -+ -+#define gckGALDEVICE_Destroy gcmHAL2D(gckGALDEVICE_Destroy) -+#define gckOS_Print gcmHAL2D(gckOS_Print) -+#define gckGALDEVICE_FreeMemory gcmHAL2D(gckGALDEVICE_FreeMemory) -+#define gckGALDEVICE_AllocateMemory gcmHAL2D(gckGALDEVICE_AllocateMemory) -+#define gckOS_DebugBreak gcmHAL2D(gckOS_DebugBreak) -+#define gckGALDEVICE_Release_ISR gcmHAL2D(gckGALDEVICE_Release_ISR) -+#define gckOS_Verify gcmHAL2D(gckOS_Verify) -+#define gckCOMMAND_Release gcmHAL2D(gckCOMMAND_Release) -+#define gckGALDEVICE_Stop gcmHAL2D(gckGALDEVICE_Stop) -+#define gckGALDEVICE_Construct gcmHAL2D(gckGALDEVICE_Construct) -+#define gckOS_DebugFatal gcmHAL2D(gckOS_DebugFatal) -+#define gckOS_DebugTrace gcmHAL2D(gckOS_DebugTrace) -+#define gckHARDWARE_GetBaseAddress gcmHAL2D(gckHARDWARE_GetBaseAddress) -+#define gckGALDEVICE_Setup_ISR gcmHAL2D(gckGALDEVICE_Setup_ISR) -+#define gckKERNEL_AttachProcess gcmHAL2D(gckKERNEL_AttachProcess) -+#define gckKERNEL_AttachProcessEx gcmHAL2D(gckKERNEL_AttachProcessEx) -+#define gckGALDEVICE_Start_Thread gcmHAL2D(gckGALDEVICE_Start_Thread) -+#define gckHARDWARE_QueryIdle gcmHAL2D(gckHARDWARE_QueryIdle) -+#define gckGALDEVICE_Start gcmHAL2D(gckGALDEVICE_Start) -+#define gckOS_GetKernelLogical gcmHAL2D(gckOS_GetKernelLogical) -+#define gckOS_DebugTraceZone gcmHAL2D(gckOS_DebugTraceZone) -+#define gckGALDEVICE_Stop_Thread gcmHAL2D(gckGALDEVICE_Stop_Thread) -+#define gckHARDWARE_NeedBaseAddress gcmHAL2D(gckHARDWARE_NeedBaseAddress) -+ -+#endif -+ -+#endif /* __gc_hal_rename_h_ */ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_statistics.h linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_statistics.h ---- linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_statistics.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_statistics.h 2015-11-30 17:56:13.596136660 +0100 -@@ -0,0 +1,99 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#ifndef __gc_hal_statistics_h_ -+#define __gc_hal_statistics_h_ -+ -+ -+#define VIV_STAT_ENABLE_STATISTICS 0 -+ -+/* Toal number of frames for which the frame time is accounted. We have storage -+ to keep frame times for last this many frames. -+*/ -+#define VIV_STAT_FRAME_BUFFER_SIZE 30 -+ -+ -+/* -+ Total number of frames sampled for a mode. This means -+ -+ # of frames for HZ Current : VIV_STAT_EARLY_Z_SAMPLE_FRAMES -+ # of frames for HZ Switched : VIV_STAT_EARLY_Z_SAMPLE_FRAMES -+ + -+ -------------------------------------------------------- -+ : (2 * VIV_STAT_EARLY_Z_SAMPLE_FRAMES) frames needed -+ -+ IMPORTANT: This total must be smaller than VIV_STAT_FRAME_BUFFER_SIZE -+*/ -+#define VIV_STAT_EARLY_Z_SAMPLE_FRAMES 7 -+#define VIV_STAT_EARLY_Z_LATENCY_FRAMES 2 -+ -+/* Multiplication factor for previous Hz off mode. Make it more than 1.0 to advertise HZ on.*/ -+#define VIV_STAT_EARLY_Z_FACTOR (1.05f) -+ -+/* Defines the statistical data keys monitored by the statistics module */ -+typedef enum _gceSTATISTICS -+{ -+ gcvFRAME_FPS = 1, -+} -+gceSTATISTICS; -+ -+/* HAL statistics information. */ -+typedef struct _gcsSTATISTICS_EARLYZ -+{ -+ gctUINT switchBackCount; -+ gctUINT nextCheckPoint; -+ gctBOOL disabled; -+} -+gcsSTATISTICS_EARLYZ; -+ -+ -+/* HAL statistics information. */ -+typedef struct _gcsSTATISTICS -+{ -+ gctUINT64 frameTime[VIV_STAT_FRAME_BUFFER_SIZE]; -+ gctUINT64 previousFrameTime; -+ gctUINT frame; -+ gcsSTATISTICS_EARLYZ earlyZ; -+} -+gcsSTATISTICS; -+ -+ -+/* Add a frame based data into current statistics. */ -+void -+gcfSTATISTICS_AddData( -+ IN gceSTATISTICS Key, -+ IN gctUINT Value -+ ); -+ -+/* Marks the frame end and triggers statistical calculations and decisions.*/ -+void -+gcfSTATISTICS_MarkFrameEnd ( -+ void -+ ); -+ -+/* Sets whether the dynmaic HZ is disabled or not .*/ -+void -+gcfSTATISTICS_DisableDynamicEarlyZ ( -+ IN gctBOOL Disabled -+ ); -+ -+#endif /*__gc_hal_statistics_h_ */ -+ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_types.h linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_types.h ---- linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_types.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_types.h 2015-11-30 17:56:13.596136660 +0100 -@@ -0,0 +1,911 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#ifndef __gc_hal_types_h_ -+#define __gc_hal_types_h_ -+ -+#include "gc_hal_version.h" -+#include "gc_hal_options.h" -+ -+#if !defined(VIV_KMD) -+#if defined(__KERNEL__) -+#include "linux/version.h" -+#include "linux/types.h" -+#else -+#include -+#include -+#include -+#endif -+#endif -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+/******************************************************************************\ -+** Platform macros. -+*/ -+ -+#if defined(__GNUC__) -+# define gcdHAS_ELLIPSIS 1 /* GCC always has it. */ -+#elif defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L) -+# define gcdHAS_ELLIPSIS 1 /* C99 has it. */ -+#elif defined(_MSC_VER) && (_MSC_VER >= 1500) -+# define gcdHAS_ELLIPSIS 1 /* MSVC 2007+ has it. */ -+#elif defined(UNDER_CE) -+#if UNDER_CE >= 600 -+# define gcdHAS_ELLIPSIS 1 -+# else -+# define gcdHAS_ELLIPSIS 0 -+# endif -+#else -+# error "gcdHAS_ELLIPSIS: Platform could not be determined" -+#endif -+ -+/******************************************************************************\ -+************************************ Keyword *********************************** -+\******************************************************************************/ -+#if defined(ANDROID) && defined(__BIONIC_FORTIFY) -+# define gcmINLINE __inline__ __attribute__ ((always_inline)) __attribute__ ((gnu_inline)) __attribute__ ((artificial)) -+#elif ((defined(__STDC_VERSION__) && (__STDC_VERSION__ >= 199901L))) -+# define gcmINLINE inline /* C99 keyword. */ -+#elif defined(__GNUC__) -+# define gcmINLINE __inline__ /* GNU keyword. */ -+#elif defined(_MSC_VER) || defined(UNDER_CE) -+# define gcmINLINE __inline /* Internal keyword. */ -+#else -+# error "gcmINLINE: Platform could not be determined" -+#endif -+ -+/* Possible debug flags. */ -+#define gcdDEBUG_NONE 0 -+#define gcdDEBUG_ALL (1 << 0) -+#define gcdDEBUG_FATAL (1 << 1) -+#define gcdDEBUG_TRACE (1 << 2) -+#define gcdDEBUG_BREAK (1 << 3) -+#define gcdDEBUG_ASSERT (1 << 4) -+#define gcdDEBUG_CODE (1 << 5) -+#define gcdDEBUG_STACK (1 << 6) -+ -+#define gcmIS_DEBUG(flag) ( gcdDEBUG & (flag | gcdDEBUG_ALL) ) -+ -+#ifndef gcdDEBUG -+#if defined(DEBUG) -+# define gcdDEBUG ( gcdDEBUG_FATAL | gcdDEBUG_TRACE | gcdDEBUG_BREAK | gcdDEBUG_ASSERT ) -+# else -+# define gcdDEBUG gcdDEBUG_NONE -+# endif -+#endif -+ -+#ifdef _USRDLL -+#ifdef _MSC_VER -+#ifdef HAL_EXPORTS -+# define HALAPI __declspec(dllexport) -+# else -+# define HALAPI __declspec(dllimport) -+# endif -+# define HALDECL __cdecl -+# else -+#ifdef HAL_EXPORTS -+# define HALAPI -+# else -+# define HALAPI extern -+# endif -+# endif -+#else -+# define HALAPI -+# define HALDECL -+#endif -+ -+/******************************************************************************\ -+********************************** Common Types ******************************** -+\******************************************************************************/ -+ -+#define gcvFALSE 0 -+#define gcvTRUE 1 -+ -+#define gcvINFINITE ((gctUINT32) ~0U) -+ -+#define gcvINVALID_HANDLE ((gctHANDLE) ~0U) -+ -+typedef int gctBOOL; -+typedef gctBOOL * gctBOOL_PTR; -+ -+typedef int gctINT; -+typedef signed char gctINT8; -+typedef signed short gctINT16; -+typedef signed int gctINT32; -+typedef signed long long gctINT64; -+ -+typedef gctINT * gctINT_PTR; -+typedef gctINT8 * gctINT8_PTR; -+typedef gctINT16 * gctINT16_PTR; -+typedef gctINT32 * gctINT32_PTR; -+typedef gctINT64 * gctINT64_PTR; -+ -+typedef unsigned int gctUINT; -+typedef unsigned char gctUINT8; -+typedef unsigned short gctUINT16; -+typedef unsigned int gctUINT32; -+typedef unsigned long long gctUINT64; -+typedef uintptr_t gctUINTPTR_T; -+ -+typedef gctUINT * gctUINT_PTR; -+typedef gctUINT8 * gctUINT8_PTR; -+typedef gctUINT16 * gctUINT16_PTR; -+typedef gctUINT32 * gctUINT32_PTR; -+typedef gctUINT64 * gctUINT64_PTR; -+ -+typedef size_t gctSIZE_T; -+typedef gctSIZE_T * gctSIZE_T_PTR; -+typedef gctUINT32 gctTRACE; -+ -+#ifdef __cplusplus -+# define gcvNULL 0 -+#else -+# define gcvNULL ((void *) 0) -+#endif -+ -+#define gcvMAXINT8 0x7f -+#define gcvMININT8 0x80 -+#define gcvMAXINT16 0x7fff -+#define gcvMININT16 0x8000 -+#define gcvMAXINT32 0x7fffffff -+#define gcvMININT32 0x80000000 -+#define gcvMAXINT64 0x7fffffffffffffff -+#define gcvMININT64 0x8000000000000000 -+#define gcvMAXUINT8 0xff -+#define gcvMINUINT8 0x0 -+#define gcvMAXUINT16 0xffff -+#define gcvMINUINT16 0x8000 -+#define gcvMAXUINT32 0xffffffff -+#define gcvMINUINT32 0x80000000 -+#define gcvMAXUINT64 0xffffffffffffffff -+#define gcvMINUINT64 0x8000000000000000 -+#define gcvMAXUINTPTR_T (~(gctUINTPTR_T)0) -+ -+typedef float gctFLOAT; -+typedef signed int gctFIXED_POINT; -+typedef float * gctFLOAT_PTR; -+ -+typedef void * gctPHYS_ADDR; -+typedef void * gctHANDLE; -+typedef void * gctFILE; -+typedef void * gctSIGNAL; -+typedef void * gctWINDOW; -+typedef void * gctIMAGE; -+typedef void * gctSYNC_POINT; -+typedef void * gctSHBUF; -+ -+typedef void * gctSEMAPHORE; -+ -+typedef void * gctPOINTER; -+typedef const void * gctCONST_POINTER; -+ -+typedef char gctCHAR; -+typedef char * gctSTRING; -+typedef const char * gctCONST_STRING; -+ -+typedef struct _gcsCOUNT_STRING -+{ -+ gctSIZE_T Length; -+ gctCONST_STRING String; -+} -+gcsCOUNT_STRING; -+ -+typedef union _gcuFLOAT_UINT32 -+{ -+ gctFLOAT f; -+ gctUINT32 u; -+} -+gcuFLOAT_UINT32; -+ -+/* Fixed point constants. */ -+#define gcvZERO_X ((gctFIXED_POINT) 0x00000000) -+#define gcvHALF_X ((gctFIXED_POINT) 0x00008000) -+#define gcvONE_X ((gctFIXED_POINT) 0x00010000) -+#define gcvNEGONE_X ((gctFIXED_POINT) 0xFFFF0000) -+#define gcvTWO_X ((gctFIXED_POINT) 0x00020000) -+ -+ -+ -+#define gcmFIXEDCLAMP_NEG1_TO_1(_x) \ -+ (((_x) < gcvNEGONE_X) \ -+ ? gcvNEGONE_X \ -+ : (((_x) > gcvONE_X) \ -+ ? gcvONE_X \ -+ : (_x))) -+ -+#define gcmFLOATCLAMP_NEG1_TO_1(_f) \ -+ (((_f) < -1.0f) \ -+ ? -1.0f \ -+ : (((_f) > 1.0f) \ -+ ? 1.0f \ -+ : (_f))) -+ -+ -+#define gcmFIXEDCLAMP_0_TO_1(_x) \ -+ (((_x) < 0) \ -+ ? 0 \ -+ : (((_x) > gcvONE_X) \ -+ ? gcvONE_X \ -+ : (_x))) -+ -+#define gcmFLOATCLAMP_0_TO_1(_f) \ -+ (((_f) < 0.0f) \ -+ ? 0.0f \ -+ : (((_f) > 1.0f) \ -+ ? 1.0f \ -+ : (_f))) -+ -+ -+/******************************************************************************\ -+******************************* Multicast Values ******************************* -+\******************************************************************************/ -+ -+/* Value types. */ -+typedef enum _gceVALUE_TYPE -+{ -+ gcvVALUE_UINT = 0x0, -+ gcvVALUE_FIXED, -+ gcvVALUE_FLOAT, -+ gcvVALUE_INT, -+ -+ /* -+ ** The value need be unsigned denormalized. clamp (0.0-1.0) should be done first. -+ */ -+ gcvVALUE_FLAG_UNSIGNED_DENORM = 0x00010000, -+ -+ /* -+ ** The value need be signed denormalized. clamp (-1.0-1.0) should be done first. -+ */ -+ gcvVALUE_FLAG_SIGNED_DENORM = 0x00020000, -+ -+ /* -+ ** The value need to gammar -+ */ -+ gcvVALUE_FLAG_GAMMAR = 0x00040000, -+ -+ /* -+ ** The value need to convert from float to float16 -+ */ -+ gcvVALUE_FLAG_FLOAT_TO_FLOAT16 = 0x0080000, -+ -+ /* -+ ** Mask for flag field. -+ */ -+ gcvVALUE_FLAG_MASK = 0xFFFF0000, -+} -+gceVALUE_TYPE; -+ -+/* Value unions. */ -+typedef union _gcuVALUE -+{ -+ gctUINT uintValue; -+ gctFIXED_POINT fixedValue; -+ gctFLOAT floatValue; -+ gctINT intValue; -+} -+gcuVALUE; -+ -+ -+ -+ -+/* Stringizing macro. */ -+#define gcmSTRING(Value) #Value -+ -+/******************************************************************************\ -+******************************* Fixed Point Math ******************************* -+\******************************************************************************/ -+ -+#define gcmXMultiply(x1, x2) gcoMATH_MultiplyFixed(x1, x2) -+#define gcmXDivide(x1, x2) gcoMATH_DivideFixed(x1, x2) -+#define gcmXMultiplyDivide(x1, x2, x3) gcoMATH_MultiplyDivideFixed(x1, x2, x3) -+ -+/* 2D Engine profile. */ -+typedef struct _gcs2D_PROFILE -+{ -+ /* Cycle count. -+ 32bit counter incremented every 2D clock cycle. -+ Wraps back to 0 when the counter overflows. -+ */ -+ gctUINT32 cycleCount; -+ -+ /* Pixels rendered by the 2D engine. -+ Resets to 0 every time it is read. */ -+ gctUINT32 pixelsRendered; -+} -+gcs2D_PROFILE; -+ -+/* Macro to combine four characters into a Charcater Code. */ -+#define gcmCC(c1, c2, c3, c4) \ -+( \ -+ (char) (c1) \ -+ | \ -+ ((char) (c2) << 8) \ -+ | \ -+ ((char) (c3) << 16) \ -+ | \ -+ ((char) (c4) << 24) \ -+) -+ -+#define gcmPRINTABLE(c) ((((c) >= ' ') && ((c) <= '}')) ? ((c) != '%' ? (c) : ' ') : ' ') -+ -+#define gcmCC_PRINT(cc) \ -+ gcmPRINTABLE((char) ( (cc) & 0xFF)), \ -+ gcmPRINTABLE((char) (((cc) >> 8) & 0xFF)), \ -+ gcmPRINTABLE((char) (((cc) >> 16) & 0xFF)), \ -+ gcmPRINTABLE((char) (((cc) >> 24) & 0xFF)) -+ -+/******************************************************************************\ -+****************************** Function Parameters ***************************** -+\******************************************************************************/ -+ -+#define IN -+#define OUT -+#define INOUT -+#define OPTIONAL -+ -+/******************************************************************************\ -+********************************* Status Codes ********************************* -+\******************************************************************************/ -+ -+typedef enum _gceSTATUS -+{ -+ gcvSTATUS_OK = 0, -+ gcvSTATUS_FALSE = 0, -+ gcvSTATUS_TRUE = 1, -+ gcvSTATUS_NO_MORE_DATA = 2, -+ gcvSTATUS_CACHED = 3, -+ gcvSTATUS_MIPMAP_TOO_LARGE = 4, -+ gcvSTATUS_NAME_NOT_FOUND = 5, -+ gcvSTATUS_NOT_OUR_INTERRUPT = 6, -+ gcvSTATUS_MISMATCH = 7, -+ gcvSTATUS_MIPMAP_TOO_SMALL = 8, -+ gcvSTATUS_LARGER = 9, -+ gcvSTATUS_SMALLER = 10, -+ gcvSTATUS_CHIP_NOT_READY = 11, -+ gcvSTATUS_NEED_CONVERSION = 12, -+ gcvSTATUS_SKIP = 13, -+ gcvSTATUS_DATA_TOO_LARGE = 14, -+ gcvSTATUS_INVALID_CONFIG = 15, -+ gcvSTATUS_CHANGED = 16, -+ gcvSTATUS_NOT_SUPPORT_DITHER = 17, -+ gcvSTATUS_EXECUTED = 18, -+ gcvSTATUS_TERMINATE = 19, -+ -+ gcvSTATUS_INVALID_ARGUMENT = -1, -+ gcvSTATUS_INVALID_OBJECT = -2, -+ gcvSTATUS_OUT_OF_MEMORY = -3, -+ gcvSTATUS_MEMORY_LOCKED = -4, -+ gcvSTATUS_MEMORY_UNLOCKED = -5, -+ gcvSTATUS_HEAP_CORRUPTED = -6, -+ gcvSTATUS_GENERIC_IO = -7, -+ gcvSTATUS_INVALID_ADDRESS = -8, -+ gcvSTATUS_CONTEXT_LOSSED = -9, -+ gcvSTATUS_TOO_COMPLEX = -10, -+ gcvSTATUS_BUFFER_TOO_SMALL = -11, -+ gcvSTATUS_INTERFACE_ERROR = -12, -+ gcvSTATUS_NOT_SUPPORTED = -13, -+ gcvSTATUS_MORE_DATA = -14, -+ gcvSTATUS_TIMEOUT = -15, -+ gcvSTATUS_OUT_OF_RESOURCES = -16, -+ gcvSTATUS_INVALID_DATA = -17, -+ gcvSTATUS_INVALID_MIPMAP = -18, -+ gcvSTATUS_NOT_FOUND = -19, -+ gcvSTATUS_NOT_ALIGNED = -20, -+ gcvSTATUS_INVALID_REQUEST = -21, -+ gcvSTATUS_GPU_NOT_RESPONDING = -22, -+ gcvSTATUS_TIMER_OVERFLOW = -23, -+ gcvSTATUS_VERSION_MISMATCH = -24, -+ gcvSTATUS_LOCKED = -25, -+ gcvSTATUS_INTERRUPTED = -26, -+ gcvSTATUS_DEVICE = -27, -+ gcvSTATUS_NOT_MULTI_PIPE_ALIGNED = -28, -+ -+ /* Linker errors. */ -+ gcvSTATUS_GLOBAL_TYPE_MISMATCH = -1000, -+ gcvSTATUS_TOO_MANY_ATTRIBUTES = -1001, -+ gcvSTATUS_TOO_MANY_UNIFORMS = -1002, -+ gcvSTATUS_TOO_MANY_VARYINGS = -1003, -+ gcvSTATUS_UNDECLARED_VARYING = -1004, -+ gcvSTATUS_VARYING_TYPE_MISMATCH = -1005, -+ gcvSTATUS_MISSING_MAIN = -1006, -+ gcvSTATUS_NAME_MISMATCH = -1007, -+ gcvSTATUS_INVALID_INDEX = -1008, -+ gcvSTATUS_UNIFORM_MISMATCH = -1009, -+ gcvSTATUS_UNSAT_LIB_SYMBOL = -1010, -+ gcvSTATUS_TOO_MANY_SHADERS = -1011, -+ gcvSTATUS_LINK_INVALID_SHADERS = -1012, -+ gcvSTATUS_CS_NO_WORKGROUP_SIZE = -1013, -+ gcvSTATUS_LINK_LIB_ERROR = -1014, -+ gcvSTATUS_SHADER_VERSION_MISMATCH = -1015, -+ gcvSTATUS_TOO_MANY_INSTRUCTION = -1016, -+ gcvSTATUS_SSBO_MISMATCH = -1017, -+ gcvSTATUS_TOO_MANY_OUTPUT = -1018, -+ gcvSTATUS_TOO_MANY_INPUT = -1019, -+ gcvSTATUS_NOT_SUPPORT_CL = -1020, -+ gcvSTATUS_NOT_SUPPORT_INTEGER = -1021, -+ gcvSTATUS_UNIFORM_TYPE_MISMATCH = -1022, -+ gcvSTATUS_TOO_MANY_SAMPLER = -1023, -+ -+ /* Compiler errors. */ -+ gcvSTATUS_COMPILER_FE_PREPROCESSOR_ERROR = -2000, -+ gcvSTATUS_COMPILER_FE_PARSER_ERROR = -2001, -+ -+ /* Recompilation Errors */ -+ gcvSTATUS_RECOMPILER_CONVERT_UNIMPLEMENTED = -3000, -+ -+ gcvSTATUS_WARNING = -9999, -+} -+gceSTATUS; -+ -+/******************************************************************************\ -+********************************* Status Macros ******************************** -+\******************************************************************************/ -+ -+#define gcmIS_ERROR(status) (status < 0) -+#define gcmNO_ERROR(status) (status >= 0) -+#define gcmIS_SUCCESS(status) (status == gcvSTATUS_OK) -+#define gcmIS_WARNING(status) (status == gcvSTATUS_WARNING) -+ -+/******************************************************************************\ -+********************************* Field Macros ********************************* -+\******************************************************************************/ -+ -+#define __gcmSTART(reg_field) \ -+ (0 ? reg_field) -+ -+#define __gcmEND(reg_field) \ -+ (1 ? reg_field) -+ -+#define __gcmGETSIZE(reg_field) \ -+ (__gcmEND(reg_field) - __gcmSTART(reg_field) + 1) -+ -+#define __gcmALIGN(data, reg_field) \ -+ (((gctUINT32) (data)) << __gcmSTART(reg_field)) -+ -+#define __gcmMASK(reg_field) \ -+ ((gctUINT32) ((__gcmGETSIZE(reg_field) == 32) \ -+ ? ~0 \ -+ : (~(~0 << __gcmGETSIZE(reg_field))))) -+ -+/******************************************************************************* -+** -+** gcmFIELDMASK -+** -+** Get aligned field mask. -+** -+** ARGUMENTS: -+** -+** reg Name of register. -+** field Name of field within register. -+*/ -+#define gcmFIELDMASK(reg, field) \ -+( \ -+ __gcmALIGN(__gcmMASK(reg##_##field), reg##_##field) \ -+) -+ -+/******************************************************************************* -+** -+** gcmGETFIELD -+** -+** Extract the value of a field from specified data. -+** -+** ARGUMENTS: -+** -+** data Data value. -+** reg Name of register. -+** field Name of field within register. -+*/ -+#define gcmGETFIELD(data, reg, field) \ -+( \ -+ ((((gctUINT32) (data)) >> __gcmSTART(reg##_##field)) \ -+ & __gcmMASK(reg##_##field)) \ -+) -+ -+/******************************************************************************* -+** -+** gcmSETFIELD -+** -+** Set the value of a field within specified data. -+** -+** ARGUMENTS: -+** -+** data Data value. -+** reg Name of register. -+** field Name of field within register. -+** value Value for field. -+*/ -+#define gcmSETFIELD(data, reg, field, value) \ -+( \ -+ (((gctUINT32) (data)) \ -+ & ~__gcmALIGN(__gcmMASK(reg##_##field), reg##_##field)) \ -+ | __gcmALIGN((gctUINT32) (value) \ -+ & __gcmMASK(reg##_##field), reg##_##field) \ -+) -+ -+/******************************************************************************* -+** -+** gcmSETFIELDVALUE -+** -+** Set the value of a field within specified data with a -+** predefined value. -+** -+** ARGUMENTS: -+** -+** data Data value. -+** reg Name of register. -+** field Name of field within register. -+** value Name of the value within the field. -+*/ -+#define gcmSETFIELDVALUE(data, reg, field, value) \ -+( \ -+ (((gctUINT32) (data)) \ -+ & ~__gcmALIGN(__gcmMASK(reg##_##field), reg##_##field)) \ -+ | __gcmALIGN(reg##_##field##_##value \ -+ & __gcmMASK(reg##_##field), reg##_##field) \ -+) -+ -+/******************************************************************************* -+** -+** gcmGETMASKEDFIELDMASK -+** -+** Determine field mask of a masked field. -+** -+** ARGUMENTS: -+** -+** reg Name of register. -+** field Name of field within register. -+*/ -+#define gcmGETMASKEDFIELDMASK(reg, field) \ -+( \ -+ gcmSETFIELD(0, reg, field, ~0) | \ -+ gcmSETFIELD(0, reg, MASK_ ## field, ~0) \ -+) -+ -+/******************************************************************************* -+** -+** gcmSETMASKEDFIELD -+** -+** Set the value of a masked field with specified data. -+** -+** ARGUMENTS: -+** -+** reg Name of register. -+** field Name of field within register. -+** value Value for field. -+*/ -+#define gcmSETMASKEDFIELD(reg, field, value) \ -+( \ -+ gcmSETFIELD (~0, reg, field, value) & \ -+ gcmSETFIELDVALUE(~0, reg, MASK_ ## field, ENABLED) \ -+) -+ -+/******************************************************************************* -+** -+** gcmSETMASKEDFIELDVALUE -+** -+** Set the value of a masked field with specified data. -+** -+** ARGUMENTS: -+** -+** reg Name of register. -+** field Name of field within register. -+** value Value for field. -+*/ -+#define gcmSETMASKEDFIELDVALUE(reg, field, value) \ -+( \ -+ gcmSETFIELDVALUE(~0, reg, field, value) & \ -+ gcmSETFIELDVALUE(~0, reg, MASK_ ## field, ENABLED) \ -+) -+ -+/******************************************************************************* -+** -+** gcmVERIFYFIELDVALUE -+** -+** Verify if the value of a field within specified data equals a -+** predefined value. -+** -+** ARGUMENTS: -+** -+** data Data value. -+** reg Name of register. -+** field Name of field within register. -+** value Name of the value within the field. -+*/ -+#define gcmVERIFYFIELDVALUE(data, reg, field, value) \ -+( \ -+ (((gctUINT32) (data)) >> __gcmSTART(reg##_##field) & \ -+ __gcmMASK(reg##_##field)) \ -+ == \ -+ (reg##_##field##_##value & __gcmMASK(reg##_##field)) \ -+) -+ -+/******************************************************************************* -+** Bit field macros. -+*/ -+ -+#define __gcmSTARTBIT(Field) \ -+ ( 1 ? Field ) -+ -+#define __gcmBITSIZE(Field) \ -+ ( 0 ? Field ) -+ -+#define __gcmBITMASK(Field) \ -+( \ -+ (1 << __gcmBITSIZE(Field)) - 1 \ -+) -+ -+#define gcmGETBITS(Value, Type, Field) \ -+( \ -+ ( ((Type) (Value)) >> __gcmSTARTBIT(Field) ) \ -+ & \ -+ __gcmBITMASK(Field) \ -+) -+ -+#define gcmSETBITS(Value, Type, Field, NewValue) \ -+( \ -+ ( ((Type) (Value)) \ -+ & ~(__gcmBITMASK(Field) << __gcmSTARTBIT(Field)) \ -+ ) \ -+ | \ -+ ( ( ((Type) (NewValue)) \ -+ & __gcmBITMASK(Field) \ -+ ) << __gcmSTARTBIT(Field) \ -+ ) \ -+) -+ -+/******************************************************************************* -+** -+** gcmISINREGRANGE -+** -+** Verify whether the specified address is in the register range. -+** -+** ARGUMENTS: -+** -+** Address Address to be verified. -+** Name Name of a register. -+*/ -+ -+#define gcmISINREGRANGE(Address, Name) \ -+( \ -+ ((Address & (~0U << Name ## _LSB)) == (Name ## _Address >> 2)) \ -+) -+ -+/******************************************************************************\ -+******************************** Ceiling Macro ******************************** -+\******************************************************************************/ -+#define gcmCEIL(x) ((x - (gctUINT32)x) == 0 ? (gctUINT32)x : (gctUINT32)x + 1) -+ -+/******************************************************************************\ -+******************************** Min/Max Macros ******************************** -+\******************************************************************************/ -+ -+#define gcmMIN(x, y) (((x) <= (y)) ? (x) : (y)) -+#define gcmMAX(x, y) (((x) >= (y)) ? (x) : (y)) -+#define gcmCLAMP(x, min, max) (((x) < (min)) ? (min) : \ -+ ((x) > (max)) ? (max) : (x)) -+#define gcmABS(x) (((x) < 0) ? -(x) : (x)) -+#define gcmNEG(x) (((x) < 0) ? (x) : -(x)) -+ -+/******************************************************************************\ -+******************************** Bit Macro ******************************** -+\******************************************************************************/ -+#define gcmBITSET(x, y) ((x) & (y)) -+/******************************************************************************* -+** -+** gcmPTR2INT -+** -+** Convert a pointer to an integer value. -+** -+** ARGUMENTS: -+** -+** p Pointer value. -+*/ -+#define gcmPTR2INT(p) \ -+( \ -+ (gctUINTPTR_T) (p) \ -+) -+ -+#define gcmPTR2INT32(p) \ -+( \ -+ (gctUINT32)(gctUINTPTR_T) (p) \ -+) -+ -+/******************************************************************************* -+** -+** gcmINT2PTR -+** -+** Convert an integer value into a pointer. -+** -+** ARGUMENTS: -+** -+** v Integer value. -+*/ -+ -+#define gcmINT2PTR(i) \ -+( \ -+ (gctPOINTER) (gctUINTPTR_T)(i) \ -+) -+ -+/******************************************************************************* -+** -+** gcmOFFSETOF -+** -+** Compute the byte offset of a field inside a structure. -+** -+** ARGUMENTS: -+** -+** s Structure name. -+** field Field name. -+*/ -+#define gcmOFFSETOF(s, field) \ -+( \ -+ gcmPTR2INT32(& (((struct s *) 0)->field)) \ -+) -+ -+/******************************************************************************* -+** -+** gcmSWAB32 -+** -+** Return a value with all bytes in the 32 bit argument swapped. -+*/ -+#define gcmSWAB32(x) ((gctUINT32)( \ -+ (((gctUINT32)(x) & (gctUINT32)0x000000FFUL) << 24) | \ -+ (((gctUINT32)(x) & (gctUINT32)0x0000FF00UL) << 8) | \ -+ (((gctUINT32)(x) & (gctUINT32)0x00FF0000UL) >> 8) | \ -+ (((gctUINT32)(x) & (gctUINT32)0xFF000000UL) >> 24))) -+ -+/******************************************************************************* -+***** Database ****************************************************************/ -+ -+typedef struct _gcsDATABASE_COUNTERS -+{ -+ /* Number of currently allocated bytes. */ -+ gctUINT64 bytes; -+ -+ /* Maximum number of bytes allocated (memory footprint). */ -+ gctUINT64 maxBytes; -+ -+ /* Total number of bytes allocated. */ -+ gctUINT64 totalBytes; -+} -+gcsDATABASE_COUNTERS; -+ -+typedef struct _gcuDATABASE_INFO -+{ -+ /* Counters. */ -+ gcsDATABASE_COUNTERS counters; -+ -+ /* Time value. */ -+ gctUINT64 time; -+} -+gcuDATABASE_INFO; -+ -+/******************************************************************************* -+***** Frame database **********************************************************/ -+ -+/* gcsHAL_FRAME_INFO */ -+typedef struct _gcsHAL_FRAME_INFO -+{ -+ /* Current timer tick. */ -+ OUT gctUINT64 ticks; -+ -+ /* Bandwidth counters. */ -+ OUT gctUINT readBytes8[8]; -+ OUT gctUINT writeBytes8[8]; -+ -+ /* Counters. */ -+ OUT gctUINT cycles[8]; -+ OUT gctUINT idleCycles[8]; -+ OUT gctUINT mcCycles[8]; -+ OUT gctUINT readRequests[8]; -+ OUT gctUINT writeRequests[8]; -+ -+ /* 3D counters. */ -+ OUT gctUINT vertexCount; -+ OUT gctUINT primitiveCount; -+ OUT gctUINT rejectedPrimitives; -+ OUT gctUINT culledPrimitives; -+ OUT gctUINT clippedPrimitives; -+ OUT gctUINT outPrimitives; -+ OUT gctUINT inPrimitives; -+ OUT gctUINT culledQuadCount; -+ OUT gctUINT totalQuadCount; -+ OUT gctUINT quadCount; -+ OUT gctUINT totalPixelCount; -+ -+ /* PE counters. */ -+ OUT gctUINT colorKilled[8]; -+ OUT gctUINT colorDrawn[8]; -+ OUT gctUINT depthKilled[8]; -+ OUT gctUINT depthDrawn[8]; -+ -+ /* Shader counters. */ -+ OUT gctUINT shaderCycles; -+ OUT gctUINT vsInstructionCount; -+ OUT gctUINT vsTextureCount; -+ OUT gctUINT psInstructionCount; -+ OUT gctUINT psTextureCount; -+ -+ /* Texture counters. */ -+ OUT gctUINT bilinearRequests; -+ OUT gctUINT trilinearRequests; -+ OUT gctUINT txBytes8; -+ OUT gctUINT txHitCount; -+ OUT gctUINT txMissCount; -+} -+gcsHAL_FRAME_INFO; -+ -+#if gcdLINK_QUEUE_SIZE -+typedef struct _gckLINKDATA * gckLINKDATA; -+struct _gckLINKDATA -+{ -+ gctUINT32 start; -+ gctUINT32 end; -+ gctUINT32 pid; -+}; -+ -+typedef struct _gckLINKQUEUE * gckLINKQUEUE; -+struct _gckLINKQUEUE -+{ -+ struct _gckLINKDATA data[gcdLINK_QUEUE_SIZE]; -+ gctUINT32 rear; -+ gctUINT32 front; -+ gctUINT32 count; -+}; -+#endif -+ -+#define gcdENTRY_QUEUE_SIZE 256 -+typedef struct _gckENTRYDATA * gckENTRYDATA; -+struct _gckENTRYDATA -+{ -+ gctUINT32 physical; -+ gctUINT32 bytes; -+}; -+ -+typedef struct _gckENTRYQUEUE * gckENTRYQUEUE; -+struct _gckENTRYQUEUE -+{ -+ struct _gckENTRYDATA data[gcdENTRY_QUEUE_SIZE]; -+ gctUINT32 rear; -+ gctUINT32 front; -+ gctUINT32 count; -+}; -+ -+typedef enum _gceTRACEMODE -+{ -+ gcvTRACEMODE_NONE = 0, -+ gcvTRACEMODE_FULL = 1, -+ gcvTRACEMODE_LOGGER = 2, -+ gcvTRACEMODE_PRE = 3, -+ gcvTRACEMODE_POST = 4, -+ gcvTRACEMODE_SYSTRACE = 5, -+ -+} gceTRACEMODE; -+ -+ -+#ifdef __cplusplus -+} -+#endif -+ -+#endif /* __gc_hal_types_h_ */ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_version.h linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_version.h ---- linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_version.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_version.h 2015-11-30 17:56:13.596136660 +0100 -@@ -0,0 +1,39 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#ifndef __gc_hal_version_h_ -+#define __gc_hal_version_h_ -+ -+#define gcvVERSION_MAJOR 5 -+ -+#define gcvVERSION_MINOR 0 -+ -+#define gcvVERSION_PATCH 11 -+ -+#define gcvVERSION_BUILD 25762 -+ -+#define gcvVERSION_STRING "5.0.11.p4.25762" -+ -+#define gcvVERSION_DATE __DATE__ -+ -+#define gcvVERSION_TIME __TIME__ -+ -+#endif /* __gc_hal_version_h_ */ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_vg.h linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_vg.h ---- linux-4.1.13.orig/drivers/gpu/galcore/inc/gc_hal_vg.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/inc/gc_hal_vg.h 2015-11-30 17:56:13.596136660 +0100 -@@ -0,0 +1,863 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#ifndef __gc_hal_vg_h_ -+#define __gc_hal_vg_h_ -+ -+#ifdef __cplusplus -+extern "C" { -+#endif -+ -+ -+#include "gc_hal_rename.h" -+#include "gc_hal_types.h" -+#include "gc_hal_enum.h" -+#include "gc_hal_base.h" -+ -+#if gcdENABLE_VG -+ -+/* Thread routine type. */ -+typedef gctINT gctTHREADFUNCRESULT; -+typedef gctPOINTER gctTHREADFUNCPARAMETER; -+#define gctTHREADFUNCTYPE -+ -+typedef gctTHREADFUNCRESULT (gctTHREADFUNCTYPE * gctTHREADFUNC) ( -+ gctTHREADFUNCPARAMETER ThreadParameter -+ ); -+ -+ -+#if defined(gcvDEBUG) -+# undef gcvDEBUG -+#endif -+ -+#define gcdFORCE_DEBUG 0 -+#define gcdFORCE_MESSAGES 0 -+ -+ -+#if defined(DEBUG) -+# define gcvDEBUG 1 -+#else -+# define gcvDEBUG 0 -+#endif -+ -+#define _gcmERROR_RETURN(prefix, func) \ -+ status = func; \ -+ if (gcmIS_ERROR(status)) \ -+ { \ -+ prefix##PRINT_VERSION(); \ -+ prefix##TRACE(gcvLEVEL_ERROR, \ -+ #prefix "ERR_RETURN: status=%d(%s) @ %s(%d)", \ -+ status, gcoOS_DebugStatus2Name(status), __FUNCTION__, __LINE__); \ -+ return status; \ -+ } \ -+ do { } while (gcvFALSE) -+ -+#define gcmERROR_RETURN(func) _gcmERROR_RETURN(gcm, func) -+ -+#define gcmLOG_LOCATION() -+ -+#define gcmkIS_ERROR(status) (status < 0) -+ -+#define gcmALIGNDOWN(n, align) \ -+( \ -+ (n) & ~((align) - 1) \ -+) -+ -+#define gcmIS_VALID_INDEX(Index, Array) \ -+ (((gctUINT) (Index)) < gcmCOUNTOF(Array)) -+ -+ -+#define gcmIS_NAN(x) \ -+( \ -+ ((* (gctUINT32_PTR) &(x)) & 0x7FFFFFFF) == 0x7FFFFFFF \ -+) -+ -+#define gcmLERP(v1, v2, w) \ -+ ((v1) * (w) + (v2) * (1.0f - (w))) -+ -+#define gcmINTERSECT(Start1, Start2, Length) \ -+ (gcmABS((Start1) - (Start2)) < (Length)) -+ -+/******************************************************************************* -+** -+** gcmERR_GOTO -+** -+** Prints a message and terminates the current loop on error. -+** -+** ASSUMPTIONS: -+** -+** 'status' variable of gceSTATUS type must be defined. -+** -+** ARGUMENTS: -+** -+** Function -+** Function to evaluate. -+*/ -+ -+#define gcmERR_GOTO(Function) \ -+ status = Function; \ -+ if (gcmIS_ERROR(status)) \ -+ { \ -+ gcmTRACE( \ -+ gcvLEVEL_ERROR, \ -+ "gcmERR_GOTO: status=%d @ line=%d in function %s.\n", \ -+ status, __LINE__, __FUNCTION__ \ -+ ); \ -+ goto ErrorHandler; \ -+ } -+ -+#if gcvDEBUG || gcdFORCE_MESSAGES -+# define gcmVERIFY_BOOLEAN(Expression) \ -+ gcmASSERT( \ -+ ( (Expression) == gcvFALSE ) || \ -+ ( (Expression) == gcvTRUE ) \ -+ ) -+#else -+# define gcmVERIFY_BOOLEAN(Expression) -+#endif -+ -+/******************************************************************************* -+** -+** gcmVERIFYFIELDFIT -+** -+** Verify whether the value fits in the field. -+** -+** ARGUMENTS: -+** -+** data Data value. -+** reg Name of register. -+** field Name of field within register. -+** value Value for field. -+*/ -+#define gcmVERIFYFIELDFIT(reg, field, value) \ -+ gcmASSERT( \ -+ (value) <= gcmFIELDMAX(reg, field) \ -+ ) -+/******************************************************************************* -+** -+** gcmFIELDMAX -+** -+** Get field maximum value. -+** -+** ARGUMENTS: -+** -+** reg Name of register. -+** field Name of field within register. -+*/ -+#define gcmFIELDMAX(reg, field) \ -+( \ -+ (gctUINT32) \ -+ ( \ -+ (__gcmGETSIZE(reg##_##field) == 32) \ -+ ? ~0 \ -+ : (~(~0 << __gcmGETSIZE(reg##_##field))) \ -+ ) \ -+) -+ -+ -+/* ANSI C does not have the 'f' functions, define replacements here. */ -+#define gcmSINF(x) ((gctFLOAT) sin(x)) -+#define gcmCOSF(x) ((gctFLOAT) cos(x)) -+#define gcmASINF(x) ((gctFLOAT) asin(x)) -+#define gcmACOSF(x) ((gctFLOAT) acos(x)) -+#define gcmSQRTF(x) ((gctFLOAT) sqrt(x)) -+#define gcmFABSF(x) ((gctFLOAT) fabs(x)) -+#define gcmFMODF(x, y) ((gctFLOAT) fmod((x), (y))) -+#define gcmCEILF(x) ((gctFLOAT) ceil(x)) -+#define gcmFLOORF(x) ((gctFLOAT) floor(x)) -+ -+ -+ -+/* Fixed point constants. */ -+#define gcvZERO_X ((gctFIXED_POINT) 0x00000000) -+#define gcvHALF_X ((gctFIXED_POINT) 0x00008000) -+#define gcvONE_X ((gctFIXED_POINT) 0x00010000) -+#define gcvNEGONE_X ((gctFIXED_POINT) 0xFFFF0000) -+#define gcvTWO_X ((gctFIXED_POINT) 0x00020000) -+ -+/* Integer constants. */ -+#define gcvMAX_POS_INT ((gctINT) 0x7FFFFFFF) -+#define gcvMAX_NEG_INT ((gctINT) 0x80000000) -+ -+/* Float constants. */ -+#define gcvMAX_POS_FLOAT ((gctFLOAT) 3.4028235e+038) -+#define gcvMAX_NEG_FLOAT ((gctFLOAT) -3.4028235e+038) -+ -+/******************************************************************************\ -+***************************** Miscellaneous Macro ****************************** -+\******************************************************************************/ -+ -+#define gcmKB2BYTES(Kilobyte) \ -+( \ -+ (Kilobyte) << 10 \ -+) -+ -+#define gcmMB2BYTES(Megabyte) \ -+( \ -+ (Megabyte) << 20 \ -+) -+ -+#define gcmMAT(Matrix, Row, Column) \ -+( \ -+ (Matrix) [(Row) * 3 + (Column)] \ -+) -+ -+#define gcmMAKE2CHAR(Char1, Char2) \ -+( \ -+ ((gctUINT16) (gctUINT8) (Char1) << 0) | \ -+ ((gctUINT16) (gctUINT8) (Char2) << 8) \ -+) -+ -+#define gcmMAKE4CHAR(Char1, Char2, Char3, Char4) \ -+( \ -+ ((gctUINT32)(gctUINT8) (Char1) << 0) | \ -+ ((gctUINT32)(gctUINT8) (Char2) << 8) | \ -+ ((gctUINT32)(gctUINT8) (Char3) << 16) | \ -+ ((gctUINT32)(gctUINT8) (Char4) << 24) \ -+) -+ -+/* some platforms need to fix the physical address for HW to access*/ -+#define gcmFIXADDRESS(address) \ -+(\ -+ (address)\ -+) -+ -+#define gcmkFIXADDRESS(address) \ -+(\ -+ (address)\ -+) -+ -+/******************************************************************************\ -+****************************** Kernel Debug Macro ****************************** -+\******************************************************************************/ -+ -+/* Set signal to signaled state for specified process. */ -+gceSTATUS -+gckOS_SetSignal( -+ IN gckOS Os, -+ IN gctHANDLE Process, -+ IN gctSIGNAL Signal -+ ); -+ -+/* Return the kernel logical pointer for the given physical one. */ -+gceSTATUS -+gckOS_GetKernelLogical( -+ IN gckOS Os, -+ IN gctUINT32 Address, -+ OUT gctPOINTER * KernelPointer -+ ); -+ -+/* Return the kernel logical pointer for the given physical one. */ -+gceSTATUS -+gckOS_GetKernelLogicalEx( -+ IN gckOS Os, -+ IN gceCORE Core, -+ IN gctUINT32 Address, -+ OUT gctPOINTER * KernelPointer -+ ); -+ -+/*----------------------------------------------------------------------------*/ -+/*----------------------------- Semaphore Object -----------------------------*/ -+ -+/* Increment the value of a semaphore. */ -+gceSTATUS -+gckOS_IncrementSemaphore( -+ IN gckOS Os, -+ IN gctSEMAPHORE Semaphore -+ ); -+ -+/* Decrement the value of a semaphore (waiting might occur). */ -+gceSTATUS -+gckOS_DecrementSemaphore( -+ IN gckOS Os, -+ IN gctSEMAPHORE Semaphore -+ ); -+ -+ -+/*----------------------------------------------------------------------------*/ -+/*------------------------------- Thread Object ------------------------------*/ -+ -+/* Start a thread. */ -+gceSTATUS -+gckOS_StartThread( -+ IN gckOS Os, -+ IN gctTHREADFUNC ThreadFunction, -+ IN gctPOINTER ThreadParameter, -+ OUT gctTHREAD * Thread -+ ); -+ -+/* Stop a thread. */ -+gceSTATUS -+gckOS_StopThread( -+ IN gckOS Os, -+ IN gctTHREAD Thread -+ ); -+ -+/* Verify whether the thread is still running. */ -+gceSTATUS -+gckOS_VerifyThread( -+ IN gckOS Os, -+ IN gctTHREAD Thread -+ ); -+ -+ -+/* Construct a new gckVGKERNEL object. */ -+gceSTATUS -+gckVGKERNEL_Construct( -+ IN gckOS Os, -+ IN gctPOINTER Context, -+ IN gckKERNEL inKernel, -+ OUT gckVGKERNEL * Kernel -+ ); -+ -+/* Destroy an gckVGKERNEL object. */ -+gceSTATUS -+gckVGKERNEL_Destroy( -+ IN gckVGKERNEL Kernel -+ ); -+ -+/* Allocate linear video memory. */ -+gceSTATUS -+gckVGKERNEL_AllocateLinearMemory( -+ IN gckKERNEL Kernel, -+ IN OUT gcePOOL * Pool, -+ IN gctSIZE_T Bytes, -+ IN gctUINT32 Alignment, -+ IN gceSURF_TYPE Type, -+ OUT gcuVIDMEM_NODE_PTR * Node -+ ); -+ -+/* Unmap memory. */ -+gceSTATUS -+gckKERNEL_UnmapMemory( -+ IN gckKERNEL Kernel, -+ IN gctPHYS_ADDR Physical, -+ IN gctSIZE_T Bytes, -+ IN gctPOINTER Logical -+ ); -+ -+/* Dispatch a user-level command. */ -+gceSTATUS -+gckVGKERNEL_Dispatch( -+ IN gckKERNEL Kernel, -+ IN gctBOOL FromUser, -+ IN OUT struct _gcsHAL_INTERFACE * Interface -+ ); -+ -+/* Query command buffer requirements. */ -+gceSTATUS -+gckKERNEL_QueryCommandBuffer( -+ IN gckKERNEL Kernel, -+ OUT gcsCOMMAND_BUFFER_INFO_PTR Information -+ ); -+ -+/******************************************************************************\ -+******************************* gckVGHARDWARE Object ****************************** -+\******************************************************************************/ -+ -+/* Construct a new gckVGHARDWARE object. */ -+gceSTATUS -+gckVGHARDWARE_Construct( -+ IN gckOS Os, -+ OUT gckVGHARDWARE * Hardware -+ ); -+ -+/* Destroy an gckVGHARDWARE object. */ -+gceSTATUS -+gckVGHARDWARE_Destroy( -+ IN gckVGHARDWARE Hardware -+ ); -+ -+/* Query system memory requirements. */ -+gceSTATUS -+gckVGHARDWARE_QuerySystemMemory( -+ IN gckVGHARDWARE Hardware, -+ OUT gctSIZE_T * SystemSize, -+ OUT gctUINT32 * SystemBaseAddress -+ ); -+ -+/* Build virtual address. */ -+gceSTATUS -+gckVGHARDWARE_BuildVirtualAddress( -+ IN gckVGHARDWARE Hardware, -+ IN gctUINT32 Index, -+ IN gctUINT32 Offset, -+ OUT gctUINT32 * Address -+ ); -+ -+/* Kickstart the command processor. */ -+gceSTATUS -+gckVGHARDWARE_Execute( -+ IN gckVGHARDWARE Hardware, -+ IN gctUINT32 Address, -+ IN gctUINT32 Count -+ ); -+ -+/* Query the available memory. */ -+gceSTATUS -+gckVGHARDWARE_QueryMemory( -+ IN gckVGHARDWARE Hardware, -+ OUT gctSIZE_T * InternalSize, -+ OUT gctUINT32 * InternalBaseAddress, -+ OUT gctUINT32 * InternalAlignment, -+ OUT gctSIZE_T * ExternalSize, -+ OUT gctUINT32 * ExternalBaseAddress, -+ OUT gctUINT32 * ExternalAlignment, -+ OUT gctUINT32 * HorizontalTileSize, -+ OUT gctUINT32 * VerticalTileSize -+ ); -+ -+/* Query the identity of the hardware. */ -+gceSTATUS -+gckVGHARDWARE_QueryChipIdentity( -+ IN gckVGHARDWARE Hardware, -+ OUT gceCHIPMODEL* ChipModel, -+ OUT gctUINT32* ChipRevision, -+ OUT gctUINT32* ChipFeatures, -+ OUT gctUINT32* ChipMinorFeatures, -+ OUT gctUINT32* ChipMinorFeatures1 -+ ); -+ -+/* Convert an API format. */ -+gceSTATUS -+gckVGHARDWARE_ConvertFormat( -+ IN gckVGHARDWARE Hardware, -+ IN gceSURF_FORMAT Format, -+ OUT gctUINT32 * BitsPerPixel, -+ OUT gctUINT32 * BytesPerTile -+ ); -+ -+/* Split a harwdare specific address into API stuff. */ -+gceSTATUS -+gckVGHARDWARE_SplitMemory( -+ IN gckVGHARDWARE Hardware, -+ IN gctUINT32 Address, -+ OUT gcePOOL * Pool, -+ OUT gctUINT32 * Offset -+ ); -+ -+/* Align size to tile boundary. */ -+gceSTATUS -+gckVGHARDWARE_AlignToTile( -+ IN gckVGHARDWARE Hardware, -+ IN gceSURF_TYPE Type, -+ IN OUT gctUINT32_PTR Width, -+ IN OUT gctUINT32_PTR Height -+ ); -+ -+/* Convert logical address to hardware specific address. */ -+gceSTATUS -+gckVGHARDWARE_ConvertLogical( -+ IN gckVGHARDWARE Hardware, -+ IN gctPOINTER Logical, -+ IN gctBOOL InUserSpace, -+ OUT gctUINT32 * Address -+ ); -+ -+/* Program MMU. */ -+gceSTATUS -+gckVGHARDWARE_SetMMU( -+ IN gckVGHARDWARE Hardware, -+ IN gctPOINTER Logical -+ ); -+ -+/* Flush the MMU. */ -+gceSTATUS -+gckVGHARDWARE_FlushMMU( -+ IN gckVGHARDWARE Hardware -+ ); -+ -+/* Get idle register. */ -+gceSTATUS -+gckVGHARDWARE_GetIdle( -+ IN gckVGHARDWARE Hardware, -+ OUT gctUINT32 * Data -+ ); -+ -+/* Flush the caches. */ -+gceSTATUS -+gckVGHARDWARE_Flush( -+ IN gckVGHARDWARE Hardware, -+ IN gceKERNEL_FLUSH Flush, -+ IN gctPOINTER Logical, -+ IN OUT gctSIZE_T * Bytes -+ ); -+ -+/* Enable/disable fast clear. */ -+gceSTATUS -+gckVGHARDWARE_SetFastClear( -+ IN gckVGHARDWARE Hardware, -+ IN gctINT Enable -+ ); -+ -+gceSTATUS -+gckVGHARDWARE_ReadInterrupt( -+ IN gckVGHARDWARE Hardware, -+ OUT gctUINT32_PTR IDs -+ ); -+ -+/* Power management. */ -+gceSTATUS -+gckVGHARDWARE_SetPowerManagementState( -+ IN gckVGHARDWARE Hardware, -+ IN gceCHIPPOWERSTATE State -+ ); -+ -+gceSTATUS -+gckVGHARDWARE_QueryPowerManagementState( -+ IN gckVGHARDWARE Hardware, -+ OUT gceCHIPPOWERSTATE* State -+ ); -+ -+gceSTATUS -+gckVGHARDWARE_SetPowerManagement( -+ IN gckVGHARDWARE Hardware, -+ IN gctBOOL PowerManagement -+ ); -+ -+gceSTATUS -+gckVGHARDWARE_SetPowerOffTimeout( -+ IN gckVGHARDWARE Hardware, -+ IN gctUINT32 Timeout -+ ); -+ -+gceSTATUS -+gckVGHARDWARE_QueryPowerOffTimeout( -+ IN gckVGHARDWARE Hardware, -+ OUT gctUINT32* Timeout -+ ); -+ -+gceSTATUS -+gckVGHARDWARE_QueryIdle( -+ IN gckVGHARDWARE Hardware, -+ OUT gctBOOL_PTR IsIdle -+ ); -+/******************************************************************************\ -+*************************** Command Buffer Structures ************************** -+\******************************************************************************/ -+ -+/* Vacant command buffer marker. */ -+#define gcvVACANT_BUFFER ((gcsCOMPLETION_SIGNAL_PTR) ((gctSIZE_T)1)) -+ -+/* Command buffer header. */ -+typedef struct _gcsCMDBUFFER * gcsCMDBUFFER_PTR; -+typedef struct _gcsCMDBUFFER -+{ -+ /* Pointer to the completion signal. */ -+ gcsCOMPLETION_SIGNAL_PTR completion; -+ -+ /* The user sets this to the node of the container buffer whitin which -+ this particular command buffer resides. The kernel sets this to the -+ node of the internally allocated buffer. */ -+ gcuVIDMEM_NODE_PTR node; -+ -+ /* Command buffer hardware address. */ -+ gctUINT32 address; -+ -+ /* The offset of the buffer from the beginning of the header. */ -+ gctUINT32 bufferOffset; -+ -+ /* Size of the area allocated for the data portion of this particular -+ command buffer (headers and tail reserves are excluded). */ -+ gctUINT32 size; -+ -+ /* Offset into the buffer [0..size]; reflects exactly how much data has -+ been put into the command buffer. */ -+ gctUINT offset; -+ -+ /* The number of command units in the buffer for the hardware to -+ execute. */ -+ gctUINT32 dataCount; -+ -+ /* MANAGED BY : user HAL (gcoBUFFER object). -+ USED BY : user HAL (gcoBUFFER object). -+ Points to the immediate next allocated command buffer. */ -+ gcsCMDBUFFER_PTR nextAllocated; -+ -+ /* MANAGED BY : user layers (HAL and drivers). -+ USED BY : kernel HAL (gcoBUFFER object). -+ Points to the next subbuffer if any. A family of subbuffers are chained -+ together and are meant to be executed inseparably as a unit. Meaning -+ that context switching cannot occur while a chain of subbuffers is being -+ executed. */ -+ gcsCMDBUFFER_PTR nextSubBuffer; -+} -+gcsCMDBUFFER; -+ -+/* Command queue element. */ -+typedef struct _gcsVGCMDQUEUE -+{ -+ /* Pointer to the command buffer header. */ -+ gcsCMDBUFFER_PTR commandBuffer; -+ -+ /* Dynamic vs. static command buffer state. */ -+ gctBOOL dynamic; -+} -+gcsVGCMDQUEUE; -+ -+/* Context map entry. */ -+typedef struct _gcsVGCONTEXT_MAP -+{ -+ /* State index. */ -+ gctUINT32 index; -+ -+ /* New state value. */ -+ gctUINT32 data; -+ -+ /* Points to the next entry in the mod list. */ -+ gcsVGCONTEXT_MAP_PTR next; -+} -+gcsVGCONTEXT_MAP; -+ -+/* gcsVGCONTEXT structure that holds the current context. */ -+typedef struct _gcsVGCONTEXT -+{ -+ /* Context ID. */ -+ gctUINT64 id; -+ -+ /* State caching ebable flag. */ -+ gctBOOL stateCachingEnabled; -+ -+ /* Current pipe. */ -+ gctUINT32 currentPipe; -+ -+ /* State map/mod buffer. */ -+ gctUINT32 mapFirst; -+ gctUINT32 mapLast; -+ gcsVGCONTEXT_MAP_PTR mapContainer; -+ gcsVGCONTEXT_MAP_PTR mapPrev; -+ gcsVGCONTEXT_MAP_PTR mapCurr; -+ gcsVGCONTEXT_MAP_PTR firstPrevMap; -+ gcsVGCONTEXT_MAP_PTR firstCurrMap; -+ -+ /* Main context buffer. */ -+ gcsCMDBUFFER_PTR header; -+ gctUINT32_PTR buffer; -+ -+ /* Completion signal. */ -+ gctHANDLE process; -+ gctSIGNAL signal; -+} -+gcsVGCONTEXT; -+ -+/* User space task header. */ -+typedef struct _gcsTASK * gcsTASK_PTR; -+typedef struct _gcsTASK -+{ -+ /* Pointer to the next task for the same interrupt in user space. */ -+ gcsTASK_PTR next; -+ -+ /* Size of the task data that immediately follows the structure. */ -+ gctUINT size; -+ -+ /* Task data starts here. */ -+ /* ... */ -+} -+gcsTASK; -+ -+/* User space task master table entry. */ -+typedef struct _gcsTASK_MASTER_ENTRY * gcsTASK_MASTER_ENTRY_PTR; -+typedef struct _gcsTASK_MASTER_ENTRY -+{ -+ /* Pointers to the head and to the tail of the task chain. */ -+ gcsTASK_PTR head; -+ gcsTASK_PTR tail; -+} -+gcsTASK_MASTER_ENTRY; -+ -+/* User space task master table entry. */ -+typedef struct _gcsTASK_MASTER_TABLE -+{ -+ /* Table with one entry per block. */ -+ gcsTASK_MASTER_ENTRY table[gcvBLOCK_COUNT]; -+ -+ /* The total number of tasks sckeduled. */ -+ gctUINT count; -+ -+ /* The total size of event data in bytes. */ -+ gctUINT size; -+} -+gcsTASK_MASTER_TABLE; -+ -+/******************************************************************************\ -+***************************** gckVGINTERRUPT Object ****************************** -+\******************************************************************************/ -+ -+typedef struct _gckVGINTERRUPT * gckVGINTERRUPT; -+ -+typedef gceSTATUS (* gctINTERRUPT_HANDLER)( -+ IN gckVGKERNEL Kernel -+ ); -+ -+gceSTATUS -+gckVGINTERRUPT_Construct( -+ IN gckVGKERNEL Kernel, -+ OUT gckVGINTERRUPT * Interrupt -+ ); -+ -+gceSTATUS -+gckVGINTERRUPT_Destroy( -+ IN gckVGINTERRUPT Interrupt -+ ); -+ -+gceSTATUS -+gckVGINTERRUPT_Enable( -+ IN gckVGINTERRUPT Interrupt, -+ IN OUT gctINT32_PTR Id, -+ IN gctINTERRUPT_HANDLER Handler -+ ); -+ -+gceSTATUS -+gckVGINTERRUPT_Disable( -+ IN gckVGINTERRUPT Interrupt, -+ IN gctINT32 Id -+ ); -+ -+gceSTATUS -+gckVGINTERRUPT_Enque( -+ IN gckVGINTERRUPT Interrupt -+ ); -+ -+gceSTATUS -+gckVGINTERRUPT_DumpState( -+ IN gckVGINTERRUPT Interrupt -+ ); -+ -+ -+/******************************************************************************\ -+******************************* gckVGCOMMAND Object ******************************* -+\******************************************************************************/ -+ -+typedef struct _gckVGCOMMAND * gckVGCOMMAND; -+ -+/* Construct a new gckVGCOMMAND object. */ -+gceSTATUS -+gckVGCOMMAND_Construct( -+ IN gckVGKERNEL Kernel, -+ IN gctUINT TaskGranularity, -+ IN gctUINT QueueSize, -+ OUT gckVGCOMMAND * Command -+ ); -+ -+/* Destroy an gckVGCOMMAND object. */ -+gceSTATUS -+gckVGCOMMAND_Destroy( -+ IN gckVGCOMMAND Command -+ ); -+ -+/* Query command buffer attributes. */ -+gceSTATUS -+gckVGCOMMAND_QueryCommandBuffer( -+ IN gckVGCOMMAND Command, -+ OUT gcsCOMMAND_BUFFER_INFO_PTR Information -+ ); -+ -+/* Allocate a command queue. */ -+gceSTATUS -+gckVGCOMMAND_Allocate( -+ IN gckVGCOMMAND Command, -+ IN gctSIZE_T Size, -+ OUT gcsCMDBUFFER_PTR * CommandBuffer, -+ OUT gctPOINTER * Data -+ ); -+ -+/* Release memory held by the command queue. */ -+gceSTATUS -+gckVGCOMMAND_Free( -+ IN gckVGCOMMAND Command, -+ IN gcsCMDBUFFER_PTR CommandBuffer -+ ); -+ -+/* Schedule the command queue for execution. */ -+gceSTATUS -+gckVGCOMMAND_Execute( -+ IN gckVGCOMMAND Command, -+ IN gcsCMDBUFFER_PTR CommandBuffer -+ ); -+ -+/* Commit a buffer to the command queue. */ -+gceSTATUS -+gckVGCOMMAND_Commit( -+ IN gckVGCOMMAND Command, -+ IN gcsVGCONTEXT_PTR Context, -+ IN gcsVGCMDQUEUE_PTR Queue, -+ IN gctUINT EntryCount, -+ IN gcsTASK_MASTER_TABLE_PTR TaskTable -+ ); -+ -+/******************************************************************************\ -+********************************* gckVGMMU Object ******************************** -+\******************************************************************************/ -+ -+typedef struct _gckVGMMU * gckVGMMU; -+ -+/* Construct a new gckVGMMU object. */ -+gceSTATUS -+gckVGMMU_Construct( -+ IN gckVGKERNEL Kernel, -+ IN gctUINT32 MmuSize, -+ OUT gckVGMMU * Mmu -+ ); -+ -+/* Destroy an gckVGMMU object. */ -+gceSTATUS -+gckVGMMU_Destroy( -+ IN gckVGMMU Mmu -+ ); -+ -+/* Allocate pages inside the MMU. */ -+gceSTATUS -+gckVGMMU_AllocatePages( -+ IN gckVGMMU Mmu, -+ IN gctSIZE_T PageCount, -+ OUT gctPOINTER * PageTable, -+ OUT gctUINT32 * Address -+ ); -+ -+/* Remove a page table from the MMU. */ -+gceSTATUS -+gckVGMMU_FreePages( -+ IN gckVGMMU Mmu, -+ IN gctPOINTER PageTable, -+ IN gctSIZE_T PageCount -+ ); -+ -+/* Set the MMU page with info. */ -+gceSTATUS -+gckVGMMU_SetPage( -+ IN gckVGMMU Mmu, -+ IN gctUINT32 PageAddress, -+ IN gctUINT32 *PageEntry -+ ); -+ -+/* Flush MMU */ -+gceSTATUS -+gckVGMMU_Flush( -+ IN gckVGMMU Mmu -+ ); -+ -+#endif /* gcdENABLE_VG */ -+ -+#ifdef __cplusplus -+} /* extern "C" */ -+#endif -+ -+#endif /* __gc_hal_h_ */ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/Kbuild linux-4.1.13/drivers/gpu/galcore/Kbuild ---- linux-4.1.13.orig/drivers/gpu/galcore/Kbuild 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/Kbuild 2015-11-30 17:56:13.596136660 +0100 -@@ -0,0 +1,233 @@ -+############################################################################## -+# -+# Copyright (C) 2005 - 2014 by Vivante Corp. -+# -+# This program is free software; you can redistribute it and/or modify -+# it under the terms of the GNU General Public License as published by -+# the Free Software Foundation; either version 2 of the license, or -+# (at your option) any later version. -+# -+# This program is distributed in the hope that it will be useful, -+# but WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+# GNU General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with this program; if not write to the Free Software -+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+# -+############################################################################## -+ -+ -+# -+# Linux build file for kernel HAL driver. -+# -+ -+AQROOT := $(srctree)/drivers/gpu/galcore -+ -+include $(AQROOT)/config -+ -+KERNEL_DIR ?= $(TOOL_DIR)/kernel -+ -+# Check and include platform config. -+ifneq ($(PLATFORM),) -+ -+# Get platform config path. -+PLATFORM_CONFIG ?= $(AQROOT)/platform/$(PLATFORM).config -+ -+# Check whether it exists. -+PLATFORM_CONFIG := $(wildcard $(PLATFORM_CONFIG)) -+ -+# Include it if exists. -+ifneq ($(PLATFORM_CONFIG),) -+include $(PLATFORM_CONFIG) -+endif -+ -+endif -+ -+MODULE_NAME ?= galcore -+CUSTOMER_ALLOCATOR_OBJS ?= -+ALLOCATOR_ARRAY_H_LOCATION ?= allocator/default/ -+ -+#EXTRA_CFLAGS += -Werror -+ -+OBJS := gc_hal_kernel_device.o \ -+ gc_hal_kernel_linux.o \ -+ gc_hal_kernel_math.o \ -+ gc_hal_kernel_os.o \ -+ gc_hal_kernel_debugfs.o \ -+ gc_hal_kernel_allocator.o \ -+ -+ifneq ($(CONFIG_IOMMU_SUPPORT),) -+OBJS += gc_hal_kernel_iommu.o -+endif -+ -+OBJS += gc_hal_kernel_probe.o -+ifneq ($(PLATFORM),) -+OBJS += platform/$(PLATFORM).o -+endif -+ -+OBJS += gc_hal_kernel.o \ -+ gc_hal_kernel_command.o \ -+ gc_hal_kernel_db.o \ -+ gc_hal_kernel_debug.o \ -+ gc_hal_kernel_event.o \ -+ gc_hal_kernel_mmu.o \ -+ gc_hal_kernel_video_memory.o \ -+ gc_hal_kernel_power.o \ -+ -+OBJS += arch/gc_hal_kernel_context.o \ -+ arch/gc_hal_kernel_hardware.o -+ -+ifeq ($(VIVANTE_ENABLE_3D), 1) -+OBJS += arch/gc_hal_kernel_recorder.o -+endif -+ -+ifeq ($(VIVANTE_ENABLE_VG), 1) -+OBJS +=\ -+ gc_hal_kernel_vg.o \ -+ gc_hal_kernel_command_vg.o \ -+ gc_hal_kernel_interrupt_vg.o \ -+ gc_hal_kernel_mmu_vg.o \ -+ archvg/gc_hal_kernel_hardware_command_vg.o \ -+ archvg/gc_hal_kernel_hardware_vg.o -+endif -+ -+ifneq ($(CONFIG_SYNC),) -+EXTRA_CFLAGS += -Idrivers/staging/android -+ -+OBJS += gc_hal_kernel_sync.o -+endif -+ -+ifneq ($(CUSTOMER_ALLOCATOR_OBJS),) -+OBJS += $(CUSTOMER_ALLOCATOR_OBJS) -+endif -+ -+ifeq ($(KERNELRELEASE), ) -+ -+.PHONY: all clean install -+ -+# Define targets. -+all: -+ @make V=$(V) ARCH=$(ARCH_TYPE) -C $(KERNEL_DIR) SUBDIRS=`pwd` modules -+ -+clean: -+ @rm -rf $(OBJS) -+ @rm -rf modules.order Module.symvers -+ @find $(AQROOT) -name ".gc_*.cmd" | xargs rm -f -+ -+install: all -+ @mkdir -p $(SDK_DIR)/drivers -+ -+else -+ -+ -+EXTRA_CFLAGS += -DLINUX -DDRIVER -+ -+ifeq ($(DEBUG), 1) -+EXTRA_CFLAGS += -DDEBUG=1 -+else -+EXTRA_CFLAGS += -DDEBUG=0 -+endif -+ -+ifeq ($(NO_DMA_COHERENT), 1) -+EXTRA_CFLAGS += -DNO_DMA_COHERENT -+endif -+ -+ifneq ($(USE_PLATFORM_DRIVER), 0) -+EXTRA_CFLAGS += -DUSE_PLATFORM_DRIVER=1 -+else -+EXTRA_CFLAGS += -DUSE_PLATFORM_DRIVER=0 -+endif -+ -+EXTRA_CFLAGS += -DVIVANTE_PROFILER=1 -+EXTRA_CFLAGS += -DVIVANTE_PROFILER_CONTEXT=1 -+ -+ifeq ($(ENABLE_GPU_CLOCK_BY_DRIVER), 1) -+EXTRA_CFLAGS += -DENABLE_GPU_CLOCK_BY_DRIVER=1 -+else -+EXTRA_CFLAGS += -DENABLE_GPU_CLOCK_BY_DRIVER=0 -+endif -+ -+ifeq ($(FORCE_ALL_VIDEO_MEMORY_CACHED), 1) -+EXTRA_CFLAGS += -DgcdPAGED_MEMORY_CACHEABLE=1 -+else -+EXTRA_CFLAGS += -DgcdPAGED_MEMORY_CACHEABLE=0 -+endif -+ -+ifeq ($(NONPAGED_MEMORY_CACHEABLE), 1) -+EXTRA_CFLAGS += -DgcdNONPAGED_MEMORY_CACHEABLE=1 -+else -+EXTRA_CFLAGS += -DgcdNONPAGED_MEMORY_CACHEABLE=0 -+endif -+ -+ifeq ($(NONPAGED_MEMORY_BUFFERABLE), 1) -+EXTRA_CFLAGS += -DgcdNONPAGED_MEMORY_BUFFERABLE=1 -+else -+EXTRA_CFLAGS += -DgcdNONPAGED_MEMORY_BUFFERABLE=0 -+endif -+ -+ifeq ($(CACHE_FUNCTION_UNIMPLEMENTED), 1) -+EXTRA_CFLAGS += -DgcdCACHE_FUNCTION_UNIMPLEMENTED=1 -+else -+EXTRA_CFLAGS += -DgcdCACHE_FUNCTION_UNIMPLEMENTED=0 -+endif -+ -+ifeq ($(CONFIG_SMP), y) -+EXTRA_CFLAGS += -DgcdSMP=1 -+else -+EXTRA_CFLAGS += -DgcdSMP=0 -+endif -+ -+ifeq ($(VIVANTE_ENABLE_3D),0) -+EXTRA_CFLAGS += -DgcdENABLE_3D=0 -+else -+EXTRA_CFLAGS += -DgcdENABLE_3D=1 -+endif -+ -+ifeq ($(VIVANTE_ENABLE_2D),0) -+EXTRA_CFLAGS += -DgcdENABLE_2D=0 -+else -+EXTRA_CFLAGS += -DgcdENABLE_2D=1 -+endif -+ -+ifeq ($(VIVANTE_ENABLE_VG),0) -+EXTRA_CFLAGS += -DgcdENABLE_VG=0 -+else -+EXTRA_CFLAGS += -DgcdENABLE_VG=1 -+endif -+ -+ifeq ($(USE_BANK_ALIGNMENT), 1) -+ EXTRA_CFLAGS += -DgcdENABLE_BANK_ALIGNMENT=1 -+ ifneq ($(BANK_BIT_START), 0) -+ ifneq ($(BANK_BIT_END), 0) -+ EXTRA_CFLAGS += -DgcdBANK_BIT_START=$(BANK_BIT_START) -+ EXTRA_CFLAGS += -DgcdBANK_BIT_END=$(BANK_BIT_END) -+ endif -+ endif -+ -+ ifneq ($(BANK_CHANNEL_BIT), 0) -+ EXTRA_CFLAGS += -DgcdBANK_CHANNEL_BIT=$(BANK_CHANNEL_BIT) -+ endif -+endif -+ -+ifeq ($(gcdFPGA_BUILD), 1) -+EXTRA_CFLAGS += -DgcdFPGA_BUILD=1 -+else -+EXTRA_CFLAGS += -DgcdFPGA_BUILD=0 -+endif -+ -+EXTRA_CFLAGS += -I$(AQROOT) -+EXTRA_CFLAGS += -I$(AQROOT)/arch -+EXTRA_CFLAGS += -I$(AQROOT)/inc -+EXTRA_CFLAGS += -I$(AQROOT)/$(ALLOCATOR_ARRAY_H_LOCATION) -+ -+ifeq ($(VIVANTE_ENABLE_VG), 1) -+EXTRA_CFLAGS += -I$(AQROOT)/archvg -+endif -+ -+obj-$(CONFIG_MXC_GPU_VIV_V5) += galcore.o -+ -+galcore-objs := $(OBJS) -+ -+endif -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/platform/freescale/gc_hal_kernel_platform_imx6q14.c linux-4.1.13/drivers/gpu/galcore/platform/freescale/gc_hal_kernel_platform_imx6q14.c ---- linux-4.1.13.orig/drivers/gpu/galcore/platform/freescale/gc_hal_kernel_platform_imx6q14.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/platform/freescale/gc_hal_kernel_platform_imx6q14.c 2015-11-30 17:56:13.596136660 +0100 -@@ -0,0 +1,693 @@ -+/**************************************************************************** -+* -+* Copyright (C) 2005 - 2014 by Vivante Corp. -+* -+* This program is free software; you can redistribute it and/or modify -+* it under the terms of the GNU General Public License as published by -+* the Free Software Foundation; either version 2 of the license, or -+* (at your option) any later version. -+* -+* This program is distributed in the hope that it will be useful, -+* but WITHOUT ANY WARRANTY; without even the implied warranty of -+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+* GNU General Public License for more details. -+* -+* You should have received a copy of the GNU General Public License -+* along with this program; if not write to the Free Software -+* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+* -+*****************************************************************************/ -+ -+ -+#include "gc_hal_kernel_linux.h" -+#include "gc_hal_kernel_platform.h" -+#include "gc_hal_kernel_device.h" -+#include "gc_hal_driver.h" -+#include -+ -+#if USE_PLATFORM_DRIVER -+# include -+#endif -+ -+#include -+#include -+#include -+#include -+ -+#include -+ -+ -+#ifdef CONFIG_IMX_THERMAL -+#include -+#define REG_THERMAL_NOTIFIER(a) register_devfreq_cooling_notifier(a); -+#define UNREG_THERMAL_NOTIFIER(a) unregister_devfreq_cooling_notifier(a); -+#else -+#define REG_THERMAL_NOTIFIER(a); -+#define UNREG_THERMAL_NOTIFIER(a); -+#endif -+ -+#if gcdENABLE_FSCALE_VAL_ADJUST -+static int initgpu3DMinClock = 1; -+module_param(initgpu3DMinClock, int, 0644); -+#endif -+ -+struct platform_device *pdevice; -+ -+#ifdef CONFIG_GPU_LOW_MEMORY_KILLER -+# include -+# include -+# include -+# include -+ -+struct task_struct *lowmem_deathpending; -+ -+static int -+task_notify_func(struct notifier_block *self, unsigned long val, void *data); -+ -+static struct notifier_block task_nb = { -+ .notifier_call = task_notify_func, -+}; -+ -+static int -+task_notify_func(struct notifier_block *self, unsigned long val, void *data) -+{ -+ struct task_struct *task = data; -+ -+ if (task == lowmem_deathpending) -+ lowmem_deathpending = NULL; -+ -+ return NOTIFY_OK; -+} -+ -+extern struct task_struct *lowmem_deathpending; -+static unsigned long lowmem_deathpending_timeout; -+ -+static int force_contiguous_lowmem_shrink(IN gckKERNEL Kernel) -+{ -+ struct task_struct *p; -+ struct task_struct *selected = NULL; -+ int tasksize; -+ int ret = -1; -+ int min_adj = 0; -+ int selected_tasksize = 0; -+ int selected_oom_adj; -+ /* -+ * If we already have a death outstanding, then -+ * bail out right away; indicating to vmscan -+ * that we have nothing further to offer on -+ * this pass. -+ * -+ */ -+ if (lowmem_deathpending && -+ time_before_eq(jiffies, lowmem_deathpending_timeout)) -+ return 0; -+ selected_oom_adj = min_adj; -+ -+ rcu_read_lock(); -+ for_each_process(p) { -+ struct mm_struct *mm; -+ struct signal_struct *sig; -+ gcuDATABASE_INFO info; -+ int oom_adj; -+ -+ task_lock(p); -+ mm = p->mm; -+ sig = p->signal; -+ if (!mm || !sig) { -+ task_unlock(p); -+ continue; -+ } -+ oom_adj = sig->oom_score_adj; -+ if (oom_adj < min_adj) { -+ task_unlock(p); -+ continue; -+ } -+ -+ tasksize = 0; -+ task_unlock(p); -+ rcu_read_unlock(); -+ -+ if (gckKERNEL_QueryProcessDB(Kernel, p->pid, gcvFALSE, gcvDB_VIDEO_MEMORY, &info) == gcvSTATUS_OK){ -+ tasksize += info.counters.bytes / PAGE_SIZE; -+ } -+ if (gckKERNEL_QueryProcessDB(Kernel, p->pid, gcvFALSE, gcvDB_CONTIGUOUS, &info) == gcvSTATUS_OK){ -+ tasksize += info.counters.bytes / PAGE_SIZE; -+ } -+ -+ rcu_read_lock(); -+ -+ if (tasksize <= 0) -+ continue; -+ -+ gckOS_Print(" pid %d (%s), adj %d, size %d \n", p->pid, p->comm, oom_adj, tasksize); -+ -+ if (selected) { -+ if (oom_adj < selected_oom_adj) -+ continue; -+ if (oom_adj == selected_oom_adj && -+ tasksize <= selected_tasksize) -+ continue; -+ } -+ selected = p; -+ selected_tasksize = tasksize; -+ selected_oom_adj = oom_adj; -+ } -+ if (selected) { -+ gckOS_Print(" send sigkill to %d (%s), adj %d, size %d\n", -+ selected->pid, selected->comm, -+ selected_oom_adj, selected_tasksize); -+ lowmem_deathpending = selected; -+ lowmem_deathpending_timeout = jiffies + HZ; -+ force_sig(SIGKILL, selected); -+ ret = 0; -+ } -+ rcu_read_unlock(); -+ return ret; -+} -+ -+ -+gceSTATUS -+_ShrinkMemory( -+ IN gckPLATFORM Platform -+ ) -+{ -+ struct platform_device *pdev; -+ gckGALDEVICE galDevice; -+ gckKERNEL kernel; -+ -+ pdev = Platform->device; -+ -+ galDevice = platform_get_drvdata(pdev); -+ -+ kernel = galDevice->kernels[gcvCORE_MAJOR]; -+ -+ if (kernel != gcvNULL) -+ { -+ force_contiguous_lowmem_shrink(kernel); -+ } -+ else -+ { -+ gcmkPRINT("%s(%d) can't find kernel! ", __FUNCTION__, __LINE__); -+ } -+ -+ return gcvSTATUS_OK; -+} -+#endif -+ -+#if gcdENABLE_FSCALE_VAL_ADJUST -+#ifdef CONFIG_IMX_THERMAL -+static int thermal_hot_pm_notify(struct notifier_block *nb, unsigned long event, -+ void *dummy) -+{ -+ static gctUINT orgFscale, minFscale, maxFscale; -+ static gctBOOL critical; -+ gckHARDWARE hardware; -+ gckGALDEVICE galDevice; -+ -+ galDevice = platform_get_drvdata(pdevice); -+ if (!galDevice) -+ { -+ /* GPU is not ready, so it is meaningless to change GPU freq. */ -+ return NOTIFY_OK; -+ } -+ -+ if (!galDevice->kernels[gcvCORE_MAJOR]) -+ { -+ return NOTIFY_OK; -+ } -+ -+ hardware = galDevice->kernels[gcvCORE_MAJOR]->hardware; -+ -+ if (!hardware) -+ { -+ return NOTIFY_OK; -+ } -+ -+ if (event > 4) { -+ critical = gcvTRUE; -+ gckHARDWARE_GetFscaleValue(hardware,&orgFscale,&minFscale, &maxFscale); -+ gckHARDWARE_SetFscaleValue(hardware, minFscale); -+ gckOS_Print("System is too hot. GPU3D will work at %d/64 clock.\n", minFscale); -+ } else if (event > 1) { -+ gckHARDWARE_GetFscaleValue(hardware,&orgFscale,&minFscale, &maxFscale); -+ gckHARDWARE_SetFscaleValue(hardware, maxFscale - (8 * event)); -+ } else if (orgFscale) { -+ gckHARDWARE_SetFscaleValue(hardware, orgFscale); -+ if (critical) { -+ gckOS_Print("Hot alarm is canceled. GPU3D clock will return to %d/64\n", orgFscale); -+ critical = gcvFALSE; -+ } -+ } -+ return NOTIFY_OK; -+} -+ -+static struct notifier_block thermal_hot_pm_notifier = { -+ .notifier_call = thermal_hot_pm_notify, -+ }; -+#endif -+ -+static ssize_t show_gpu3DMinClock(struct device_driver *dev, char *buf) -+{ -+ gctUINT currentf,minf,maxf; -+ gckGALDEVICE galDevice; -+ -+ galDevice = platform_get_drvdata(pdevice); -+ if(galDevice->kernels[gcvCORE_MAJOR]) -+ { -+ gckHARDWARE_GetFscaleValue(galDevice->kernels[gcvCORE_MAJOR]->hardware, -+ ¤tf, &minf, &maxf); -+ } -+ snprintf(buf, PAGE_SIZE, "%d\n", minf); -+ return strlen(buf); -+} -+ -+static ssize_t update_gpu3DMinClock(struct device_driver *dev, const char *buf, size_t count) -+{ -+ -+ gctINT fields; -+ gctUINT MinFscaleValue; -+ gckGALDEVICE galDevice; -+ -+ galDevice = platform_get_drvdata(pdevice); -+ if(galDevice->kernels[gcvCORE_MAJOR]) -+ { -+ fields = sscanf(buf, "%d", &MinFscaleValue); -+ if (fields < 1) -+ return -EINVAL; -+ -+ gckHARDWARE_SetMinFscaleValue(galDevice->kernels[gcvCORE_MAJOR]->hardware,MinFscaleValue); -+ } -+ -+ return count; -+} -+ -+static DRIVER_ATTR(gpu3DMinClock, S_IRUGO | S_IWUSR, show_gpu3DMinClock, update_gpu3DMinClock); -+#endif -+ -+ -+ -+ -+static const struct of_device_id mxs_gpu_dt_ids[] = { -+ { .compatible = "fsl,imx6q-gpu", }, -+ { .compatible = "fsl,imx-gpu-subsystem", }, -+ {/* sentinel */} -+}; -+MODULE_DEVICE_TABLE(of, mxs_gpu_dt_ids); -+ -+ -+struct contiguous_mem_pool { -+ struct dma_attrs attrs; -+ dma_addr_t phys; -+ void *virt; -+ size_t size; -+}; -+ -+struct imx_priv { -+ /* Clock management.*/ -+ struct clk *clk_3d_core; -+ struct clk *clk_3d_shader; -+ struct clk *clk_3d_axi; -+ struct clk *clk_2d_core; -+ struct clk *clk_2d_axi; -+ struct clk *clk_vg_axi; -+ -+ /*Run time pm*/ -+ struct device *pmdev; -+ struct contiguous_mem_pool *pool; -+ struct reset_control *rstc[gcdMAX_GPU_COUNT]; -+}; -+ -+static struct imx_priv imxPriv; -+ -+gceSTATUS -+gckPLATFORM_AdjustParam( -+ IN gckPLATFORM Platform, -+ OUT gcsMODULE_PARAMETERS *Args -+ ) -+{ -+ struct resource* res; -+ struct platform_device* pdev = Platform->device; -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phys_baseaddr"); -+ if (res) -+ Args->baseAddress = res->start; -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "irq_3d"); -+ if (res) -+ Args->irqLine = res->start; -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "iobase_3d"); -+ if (res) -+ { -+ Args->registerMemBase = res->start; -+ Args->registerMemSize = res->end - res->start + 1; -+ } -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "irq_2d"); -+ if (res) -+ Args->irqLine2D = res->start; -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "iobase_2d"); -+ if (res) -+ { -+ Args->registerMemBase2D = res->start; -+ Args->registerMemSize2D = res->end - res->start + 1; -+ } -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "irq_vg"); -+ if (res) -+ Args->irqLineVG = res->start; -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "iobase_vg"); -+ if (res) -+ { -+ Args->registerMemBaseVG = res->start; -+ Args->registerMemSizeVG = res->end - res->start + 1; -+ } -+ -+#if gcdENABLE_FSCALE_VAL_ADJUST -+ Args->gpu3DMinClock = initgpu3DMinClock; -+#endif -+ -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+_AllocPriv( -+ IN gckPLATFORM Platform -+ ) -+{ -+ Platform->priv = &imxPriv; -+ -+#ifdef CONFIG_GPU_LOW_MEMORY_KILLER -+ task_free_register(&task_nb); -+#endif -+ -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+_FreePriv( -+ IN gckPLATFORM Platform -+ ) -+{ -+#ifdef CONFIG_GPU_LOW_MEMORY_KILLER -+ task_free_unregister(&task_nb); -+#endif -+ -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+_GetPower( -+ IN gckPLATFORM Platform -+ ) -+{ -+ struct device* pdev = &Platform->device->dev; -+ struct imx_priv *priv = Platform->priv; -+ struct reset_control *rstc; -+ -+#ifdef CONFIG_PM -+ /*Init runtime pm for gpu*/ -+ pm_runtime_use_autosuspend(pdev); -+ pm_runtime_set_autosuspend_delay(pdev, 200); -+ pm_runtime_enable(pdev); -+ priv->pmdev = pdev; -+#endif -+ -+ -+ rstc = devm_reset_control_get(pdev, "gpu3d"); -+ priv->rstc[gcvCORE_MAJOR] = IS_ERR(rstc) ? NULL : rstc; -+ rstc = devm_reset_control_get(pdev, "gpu2d"); -+ priv->rstc[gcvCORE_2D] = IS_ERR(rstc) ? NULL : rstc; -+ rstc = devm_reset_control_get(pdev, "gpuvg"); -+ priv->rstc[gcvCORE_VG] = IS_ERR(rstc) ? NULL : rstc; -+ -+ /*Initialize the clock structure*/ -+ priv->clk_3d_core = clk_get(pdev, "gpu3d_clk"); -+ if (!IS_ERR(priv->clk_3d_core)) { -+ priv->clk_3d_axi = clk_get(pdev, "gpu3d_axi_clk"); -+ priv->clk_3d_shader = clk_get(pdev, "gpu3d_shader_clk"); -+ if (IS_ERR(priv->clk_3d_shader)) { -+ clk_put(priv->clk_3d_core); -+ priv->clk_3d_core = NULL; -+ priv->clk_3d_shader = NULL; -+ gckOS_Print("galcore: clk_get gpu3d_shader_clk failed, disable 3d!\n"); -+ } -+ } else { -+ priv->clk_3d_core = NULL; -+ gckOS_Print("galcore: clk_get gpu3d_clk failed, disable 3d!\n"); -+ } -+ -+ priv->clk_2d_core = clk_get(pdev, "gpu2d_clk"); -+ if (IS_ERR(priv->clk_2d_core)) { -+ priv->clk_2d_core = NULL; -+ gckOS_Print("galcore: clk_get 2d core clock failed, disable 2d/vg!\n"); -+ } else { -+ priv->clk_2d_axi = clk_get(pdev, "gpu2d_axi_clk"); -+ if (IS_ERR(priv->clk_2d_axi)) { -+ priv->clk_2d_axi = NULL; -+ gckOS_Print("galcore: clk_get 2d axi clock failed, disable 2d\n"); -+ } -+ -+ priv->clk_vg_axi = clk_get(pdev, "openvg_axi_clk"); -+ if (IS_ERR(priv->clk_vg_axi)) { -+ priv->clk_vg_axi = NULL; -+ gckOS_Print("galcore: clk_get vg clock failed, disable vg!\n"); -+ } -+ } -+ -+ -+#if gcdENABLE_FSCALE_VAL_ADJUST -+ pdevice = Platform->device; -+ REG_THERMAL_NOTIFIER(&thermal_hot_pm_notifier); -+ { -+ int ret = 0; -+ ret = driver_create_file(pdevice->dev.driver, &driver_attr_gpu3DMinClock); -+ if(ret) -+ dev_err(&pdevice->dev, "create gpu3DMinClock attr failed (%d)\n", ret); -+ } -+#endif -+ -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+_PutPower( -+ IN gckPLATFORM Platform -+ ) -+{ -+ struct imx_priv *priv = Platform->priv; -+ -+ /*Disable clock*/ -+ if (priv->clk_3d_axi) { -+ clk_put(priv->clk_3d_axi); -+ priv->clk_3d_axi = NULL; -+ } -+ if (priv->clk_3d_core) { -+ clk_put(priv->clk_3d_core); -+ priv->clk_3d_core = NULL; -+ } -+ if (priv->clk_3d_shader) { -+ clk_put(priv->clk_3d_shader); -+ priv->clk_3d_shader = NULL; -+ } -+ if (priv->clk_2d_core) { -+ clk_put(priv->clk_2d_core); -+ priv->clk_2d_core = NULL; -+ } -+ if (priv->clk_2d_axi) { -+ clk_put(priv->clk_2d_axi); -+ priv->clk_2d_axi = NULL; -+ } -+ if (priv->clk_vg_axi) { -+ clk_put(priv->clk_vg_axi); -+ priv->clk_vg_axi = NULL; -+ } -+ -+#ifdef CONFIG_PM -+ if(priv->pmdev) -+ pm_runtime_disable(priv->pmdev); -+#endif -+ -+#if gcdENABLE_FSCALE_VAL_ADJUST -+ UNREG_THERMAL_NOTIFIER(&thermal_hot_pm_notifier); -+ -+ driver_remove_file(pdevice->dev.driver, &driver_attr_gpu3DMinClock); -+#endif -+ -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+_SetPower( -+ IN gckPLATFORM Platform, -+ IN gceCORE GPU, -+ IN gctBOOL Enable -+ ) -+{ -+ struct imx_priv* priv = Platform->priv; -+ -+ if (Enable) -+ { -+#ifdef CONFIG_PM -+ pm_runtime_get_sync(priv->pmdev); -+#endif -+ } -+ else -+ { -+#ifdef CONFIG_PM -+ pm_runtime_put_sync(priv->pmdev); -+#endif -+ } -+ -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+_SetClock( -+ IN gckPLATFORM Platform, -+ IN gceCORE GPU, -+ IN gctBOOL Enable -+ ) -+{ -+ struct imx_priv* priv = Platform->priv; -+ struct clk *clk_3dcore = priv->clk_3d_core; -+ struct clk *clk_3dshader = priv->clk_3d_shader; -+ struct clk *clk_3d_axi = priv->clk_3d_axi; -+ struct clk *clk_2dcore = priv->clk_2d_core; -+ struct clk *clk_2d_axi = priv->clk_2d_axi; -+ struct clk *clk_vg_axi = priv->clk_vg_axi; -+ -+ -+ if (Enable) { -+ switch (GPU) { -+ case gcvCORE_MAJOR: -+ clk_prepare(clk_3dcore); -+ clk_enable(clk_3dcore); -+ clk_prepare(clk_3dshader); -+ clk_enable(clk_3dshader); -+ clk_prepare(clk_3d_axi); -+ clk_enable(clk_3d_axi); -+ break; -+ case gcvCORE_2D: -+ clk_prepare(clk_2dcore); -+ clk_enable(clk_2dcore); -+ clk_prepare(clk_2d_axi); -+ clk_enable(clk_2d_axi); -+ break; -+ case gcvCORE_VG: -+ clk_prepare(clk_2dcore); -+ clk_enable(clk_2dcore); -+ clk_prepare(clk_vg_axi); -+ clk_enable(clk_vg_axi); -+ break; -+ default: -+ break; -+ } -+ } else { -+ switch (GPU) { -+ case gcvCORE_MAJOR: -+ clk_disable(clk_3dshader); -+ clk_unprepare(clk_3dshader); -+ clk_disable(clk_3dcore); -+ clk_unprepare(clk_3dcore); -+ clk_disable(clk_3d_axi); -+ clk_unprepare(clk_3d_axi); -+ break; -+ case gcvCORE_2D: -+ clk_disable(clk_2dcore); -+ clk_unprepare(clk_2dcore); -+ clk_disable(clk_2d_axi); -+ clk_unprepare(clk_2d_axi); -+ break; -+ case gcvCORE_VG: -+ clk_disable(clk_2dcore); -+ clk_unprepare(clk_2dcore); -+ clk_disable(clk_vg_axi); -+ clk_unprepare(clk_vg_axi); -+ break; -+ default: -+ break; -+ } -+ } -+ -+ return gcvSTATUS_OK; -+} -+ -+#ifdef CONFIG_PM -+static int gpu_runtime_suspend(struct device *dev) -+{ -+ release_bus_freq(BUS_FREQ_HIGH); -+ return 0; -+} -+ -+static int gpu_runtime_resume(struct device *dev) -+{ -+ request_bus_freq(BUS_FREQ_HIGH); -+ return 0; -+} -+ -+static struct dev_pm_ops gpu_pm_ops; -+#endif -+ -+gceSTATUS -+_AdjustDriver( -+ IN gckPLATFORM Platform -+ ) -+{ -+ struct platform_driver * driver = Platform->driver; -+ driver->driver.of_match_table = mxs_gpu_dt_ids; -+ -+ /* Fill local structure with original value. */ -+ memcpy(&gpu_pm_ops, driver->driver.pm, sizeof(struct dev_pm_ops)); -+ -+ /* Add runtime PM callback. */ -+#ifdef CONFIG_PM -+ gpu_pm_ops.runtime_suspend = gpu_runtime_suspend; -+ gpu_pm_ops.runtime_resume = gpu_runtime_resume; -+ gpu_pm_ops.runtime_idle = NULL; -+ -+ /* Replace callbacks. */ -+ driver->driver.pm = &gpu_pm_ops; -+#endif -+ -+ return gcvSTATUS_OK; -+} -+ -+gceSTATUS -+_Reset( -+ IN gckPLATFORM Platform, -+ gceCORE GPU -+ ) -+{ -+ struct imx_priv* priv = Platform->priv; -+ struct reset_control *rstc = priv->rstc[GPU]; -+ if (rstc) -+ reset_control_reset(rstc); -+ return gcvSTATUS_OK; -+} -+ -+gcsPLATFORM_OPERATIONS platformOperations = { -+ .adjustParam = gckPLATFORM_AdjustParam, -+ .allocPriv = _AllocPriv, -+ .freePriv = _FreePriv, -+ .getPower = _GetPower, -+ .putPower = _PutPower, -+ .setPower = _SetPower, -+ .setClock = _SetClock, -+ .adjustDriver = _AdjustDriver, -+ .reset = _Reset, -+#ifdef CONFIG_GPU_LOW_MEMORY_KILLER -+ .shrinkMemory = _ShrinkMemory, -+#endif -+}; -+ -+void -+gckPLATFORM_QueryOperations( -+ IN gcsPLATFORM_OPERATIONS ** Operations -+ ) -+{ -+ *Operations = &platformOperations; -+} -+ -diff -Nur linux-4.1.13.orig/drivers/gpu/galcore/platform/freescale/gc_hal_kernel_platform_imx6q14.config linux-4.1.13/drivers/gpu/galcore/platform/freescale/gc_hal_kernel_platform_imx6q14.config ---- linux-4.1.13.orig/drivers/gpu/galcore/platform/freescale/gc_hal_kernel_platform_imx6q14.config 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/gpu/galcore/platform/freescale/gc_hal_kernel_platform_imx6q14.config 2015-11-30 17:56:13.596136660 +0100 -@@ -0,0 +1,15 @@ -+EXTRA_CFLAGS += -DgcdDEFAULT_CONTIGUOUS_SIZE=134217728 -+ -+ifneq ($(CONFIG_ANDROID),) -+# build for android -+EXTRA_CFLAGS += -DgcdANDROID_NATIVE_FENCE_SYNC=3 -+ -+ifeq ($(CONFIG_SYNC),) -+$(warn CONFIG_SYNC is not set in kernel config) -+$(warn Android native fence sync needs CONFIG_SYNC) -+endif -+endif -+ -+EXTRA_CFLAGS += -DLINUX_CMA_FSL=1 -+ALLOCATOR_ARRAY_H_LOCATION := $(OS_KERNEL_DIR)/allocator/freescale -+CUSTOMER_ALLOCATOR_OBJS := $(ALLOCATOR_ARRAY_H_LOCATION)/gc_hal_kernel_allocator_cma.o -diff -Nur linux-4.1.13.orig/drivers/Kconfig linux-4.1.13/drivers/Kconfig ---- linux-4.1.13.orig/drivers/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/Kconfig 2015-11-30 17:56:13.596136660 +0100 -@@ -182,4 +182,6 @@ - - source "drivers/android/Kconfig" - -+source "drivers/mxc/Kconfig" -+ - endmenu -diff -Nur linux-4.1.13.orig/drivers/Makefile linux-4.1.13/drivers/Makefile ---- linux-4.1.13.orig/drivers/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/Makefile 2015-11-30 17:56:13.596136660 +0100 -@@ -165,3 +165,4 @@ - obj-$(CONFIG_THUNDERBOLT) += thunderbolt/ - obj-$(CONFIG_CORESIGHT) += hwtracing/coresight/ - obj-$(CONFIG_ANDROID) += android/ -+obj-y += mxc/ -diff -Nur linux-4.1.13.orig/drivers/media/pci/Kconfig linux-4.1.13/drivers/media/pci/Kconfig ---- linux-4.1.13.orig/drivers/media/pci/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/media/pci/Kconfig 2015-11-30 17:56:13.596136660 +0100 -@@ -12,6 +12,7 @@ - comment "Media capture support" - source "drivers/media/pci/meye/Kconfig" - source "drivers/media/pci/sta2x11/Kconfig" -+source "drivers/media/pci/tw6869/Kconfig" - endif - - if MEDIA_ANALOG_TV_SUPPORT -diff -Nur linux-4.1.13.orig/drivers/media/pci/Makefile linux-4.1.13/drivers/media/pci/Makefile ---- linux-4.1.13.orig/drivers/media/pci/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/media/pci/Makefile 2015-11-30 17:56:13.596136660 +0100 -@@ -27,3 +27,4 @@ - obj-$(CONFIG_VIDEO_MEYE) += meye/ - obj-$(CONFIG_STA2X11_VIP) += sta2x11/ - obj-$(CONFIG_VIDEO_SOLO6X10) += solo6x10/ -+obj-$(CONFIG_VIDEO_TW6869) += tw6869/ -diff -Nur linux-4.1.13.orig/drivers/media/pci/tw6869/Kconfig linux-4.1.13/drivers/media/pci/tw6869/Kconfig ---- linux-4.1.13.orig/drivers/media/pci/tw6869/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/media/pci/tw6869/Kconfig 2015-11-30 17:56:13.596136660 +0100 -@@ -0,0 +1,9 @@ -+config VIDEO_TW6869 -+ tristate "Techwell tw6869 Video For Linux" -+ depends on VIDEO_DEV && PCI && VIDEO_V4L2 -+ select VIDEOBUF2_DMA_CONTIG -+ ---help--- -+ Support for Techwell tw6869 based frame grabber boards. -+ -+ To compile this driver as a module, choose M here: the -+ module will be called tw6869. -diff -Nur linux-4.1.13.orig/drivers/media/pci/tw6869/Makefile linux-4.1.13/drivers/media/pci/tw6869/Makefile ---- linux-4.1.13.orig/drivers/media/pci/tw6869/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/media/pci/tw6869/Makefile 2015-11-30 17:56:13.596136660 +0100 -@@ -0,0 +1 @@ -+obj-$(CONFIG_VIDEO_TW6869) += tw6869.o -diff -Nur linux-4.1.13.orig/drivers/media/pci/tw6869/tw6869.c linux-4.1.13/drivers/media/pci/tw6869/tw6869.c ---- linux-4.1.13.orig/drivers/media/pci/tw6869/tw6869.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/media/pci/tw6869/tw6869.c 2015-11-30 17:56:13.596136660 +0100 -@@ -0,0 +1,1439 @@ -+/* -+ * Copyright 2015 www.starterkit.ru -+ * -+ * Based on: -+ * Driver for Intersil|Techwell TW6869 based DVR cards -+ * (c) 2011-12 liran [Intersil|Techwell China] -+ * -+ * V4L2 PCI Skeleton Driver -+ * Copyright 2014 Cisco Systems, Inc. and/or its affiliates. -+ * All rights reserved. -+ * -+ * This program is free software; you may redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; version 2 of the License. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN -+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -+ * SOFTWARE. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+ -+#include "tw6869.h" -+ -+MODULE_DESCRIPTION("tw6869/65 media bridge driver"); -+MODULE_AUTHOR("starterkit "); -+MODULE_LICENSE("GPL"); -+MODULE_VERSION("0.3.2"); -+ -+static const struct pci_device_id tw6869_pci_tbl[] = { -+ {PCI_DEVICE(PCI_VENDOR_ID_TECHWELL, PCI_DEVICE_ID_6869)}, -+ { 0, } -+}; -+ -+struct tw6869_buf { -+ struct vb2_buffer vb; -+ struct list_head list; -+ dma_addr_t dma; -+}; -+ -+/** -+ * struct tw6869_vch - instance of one video channel -+ * @dev: parent device -+ * @vdev: video channel (v4l2 video device) -+ * @id: DMA id (0...7) -+ * @p_buf: DMA P-buffer -+ * @b_buf: DMA B-buffer -+ * @pb: P-buffer | B-buffer ping-pong state -+ * @mlock: the main serialization lock -+ * @queue: queue maintained by videobuf2 layer -+ * @buf_list: list of buffer in use -+ * @lock: spinlock controlling access to channel -+ * @hdl: handler for control framework -+ * @format: pixel format -+ * @std: video standard (e.g. PAL/NTSC) -+ * @input: input line for video signal -+ * @sequence: sequence number of acquired buffer -+ * @dcount: number of dropped frames -+ * @fps: current frame rate -+ */ -+struct tw6869_vch { -+ struct tw6869_dev *dev; -+ struct video_device vdev; -+ -+ unsigned int id; -+ struct tw6869_buf *p_buf; -+ struct tw6869_buf *b_buf; -+ unsigned int pb; -+ -+ struct mutex mlock; -+ struct vb2_queue queue; -+ struct list_head buf_list; -+ spinlock_t lock; -+ -+ struct v4l2_ctrl_handler hdl; -+ struct v4l2_pix_format format; -+ v4l2_std_id std; -+ unsigned int input; -+ -+ unsigned int sequence; -+ unsigned int dcount; -+ unsigned int fps; -+}; -+ -+/** -+ * struct tw6869_ach - instance of one audio channel -+ * @dev: parent device -+ * @ss: audio channel (pcm substream) -+ * @id: DMA id (8...15) -+ * @p_buf: DMA P-buffer -+ * @b_buf: DMA B-buffer -+ * @pb: P-buffer | B-buffer ping-pong state -+ * @buf: split an contiguous buffer into chunks -+ * @buf_list: chunk list -+ * @lock: spinlock controlling access to channel -+ * @ptr: PCM buffer pointer -+ */ -+struct tw6869_ach { -+ struct tw6869_dev *dev; -+ struct snd_pcm_substream *ss; -+ -+ unsigned int id; -+ struct tw6869_buf *p_buf; -+ struct tw6869_buf *b_buf; -+ unsigned int pb; -+ -+ struct tw6869_buf buf[TW_APAGE_MAX]; -+ struct list_head buf_list; -+ spinlock_t lock; -+ -+ dma_addr_t ptr; -+}; -+ -+/** -+ * struct tw6869_dev - instance of device -+ * @pdev: PCI device -+ * @mmio: hardware base address -+ * @rlock: spinlock controlling access to registers -+ * @ch_max: channels used -+ * @id_err: DMA error counters -+ * @v4l2_dev: device registered in v4l2 layer -+ * @alloc_ctx: context for videobuf2 -+ * @vch: array of video channel instance -+ * @snd_card: device registered in ALSA layer -+ * @ach: array of audio channel instance -+ */ -+struct tw6869_dev { -+ struct pci_dev *pdev; -+ unsigned char __iomem *mmio; -+ spinlock_t rlock; -+ -+ unsigned int ch_max; -+ unsigned int id_err[2 * TW_CH_MAX]; -+ -+ struct v4l2_device v4l2_dev; -+ struct vb2_alloc_ctx *alloc_ctx; -+ struct tw6869_vch vch[TW_CH_MAX]; -+ -+ struct snd_card *snd_card; -+ struct tw6869_ach ach[TW_CH_MAX]; -+}; -+ -+/**********************************************************************/ -+ -+static inline void tw_write(struct tw6869_dev *dev, unsigned int reg, -+ unsigned int val) -+{ -+ iowrite32(val, dev->mmio + reg); -+} -+ -+static inline unsigned int tw_read(struct tw6869_dev *dev, -+ unsigned int reg) -+{ -+ return ioread32(dev->mmio + reg); -+} -+ -+static inline void tw_write_mask(struct tw6869_dev *dev, -+ unsigned int reg, unsigned int val, unsigned int mask) -+{ -+ unsigned int v = tw_read(dev, reg); -+ -+ v = (v & ~mask) | (val & mask); -+ tw_write(dev, reg, v); -+} -+ -+static inline void tw_clear(struct tw6869_dev *dev, -+ unsigned int reg, unsigned int val) -+{ -+ tw_write_mask(dev, reg, 0, val); -+} -+ -+static inline void tw_set(struct tw6869_dev *dev, -+ unsigned int reg, unsigned int val) -+{ -+ tw_write_mask(dev, reg, val, val); -+} -+ -+static inline unsigned int tw_id_is_on(struct tw6869_dev *dev, -+ unsigned int id) -+{ -+ unsigned int e = tw_read(dev, R32_DMA_CHANNEL_ENABLE); -+ unsigned int c = tw_read(dev, R32_DMA_CMD); -+ -+ return (c & BIT(31)) && (c & e & BIT_ID(id)); -+} -+ -+static inline unsigned int tw_id_is_off(struct tw6869_dev *dev, -+ unsigned int id) -+{ -+ unsigned int e = tw_read(dev, R32_DMA_CHANNEL_ENABLE); -+ unsigned int c = tw_read(dev, R32_DMA_CMD); -+ -+ return !((c | e) & BIT_ID(id)); -+} -+ -+static inline void tw_id_on(struct tw6869_dev *dev, unsigned int id) -+{ -+ int c = 3; -+ -+ while (!tw_id_is_on(dev, id) && c--) { -+ tw_set(dev, R32_DMA_CMD, BIT(31) | BIT_ID(id)); -+ tw_set(dev, R32_DMA_CHANNEL_ENABLE, BIT_ID(id)); -+ } -+} -+ -+static inline void tw_id_off(struct tw6869_dev *dev, unsigned int id) -+{ -+ int c = 3; -+ -+ while (!tw_id_is_off(dev, id) && c--) { -+ tw_clear(dev, R32_DMA_CMD, BIT_ID(id)); -+ tw_clear(dev, R32_DMA_CHANNEL_ENABLE, BIT_ID(id)); -+ } -+ -+ if (!tw_read(dev, R32_DMA_CHANNEL_ENABLE)) -+ tw_write(dev, R32_DMA_CMD, 0); -+} -+ -+static void tw6869_id_dma_cmd(struct tw6869_dev *dev, -+ unsigned int id, -+ unsigned int cmd) -+{ -+ switch (cmd) { -+ case TW_DMA_ON: -+ dev->id_err[ID2ID(id)] = 0; -+ tw_id_on(dev, id); -+ dev_info(&dev->pdev->dev, "DMA %u ON\n", id); -+ break; -+ case TW_DMA_OFF: -+ tw_id_off(dev, id); -+ dev_info(&dev->pdev->dev, "DMA %u OFF\n", id); -+ break; -+ case TW_DMA_RST: -+ if (tw_id_is_on(dev, id)) { -+ tw_id_off(dev, id); -+ if (++dev->id_err[ID2ID(id)] > TW_DMA_ERR_MAX) { -+ dev_err(&dev->pdev->dev, "DMA %u forced OFF\n", id); -+ break; -+ } -+ tw_id_on(dev, id); -+ dev_info(&dev->pdev->dev, "DMA %u RST\n", id); -+ } else { -+ dev_info(&dev->pdev->dev, "DMA %u spurious RST\n", id); -+ } -+ break; -+ default: -+ dev_err(&dev->pdev->dev, "DMA %u unknown cmd %u\n", id, cmd); -+ } -+} -+ -+static unsigned int tw6869_virq(struct tw6869_dev *dev, -+ unsigned int id, -+ unsigned int pb, -+ unsigned int err) -+{ -+ struct tw6869_vch *vch = &dev->vch[ID2CH(id)]; -+ struct tw6869_buf *done = NULL; -+ struct tw6869_buf *next = NULL; -+ -+ spin_lock(&vch->lock); -+ if (!vb2_is_streaming(&vch->queue) || !vch->p_buf || !vch->b_buf) { -+ spin_unlock(&vch->lock); -+ return TW_DMA_OFF; -+ } -+ -+ if (err || (vch->pb != pb)) { -+ vch->pb = 0; -+ spin_unlock(&vch->lock); -+ return TW_DMA_RST; -+ } -+ -+ if (!list_empty(&vch->buf_list)) { -+ next = list_first_entry(&vch->buf_list, struct tw6869_buf, list); -+ list_del(&next->list); -+ if (pb) { -+ done = vch->b_buf; -+ vch->b_buf = next; -+ } else { -+ done = vch->p_buf; -+ vch->p_buf = next; -+ } -+ } -+ vch->pb = !pb; -+ spin_unlock(&vch->lock); -+ -+ if (done && next) { -+ tw_write(dev, pb ? R32_DMA_B_ADDR(id) : R32_DMA_P_ADDR(id), next->dma); -+ v4l2_get_timestamp(&done->vb.v4l2_buf.timestamp); -+ done->vb.v4l2_buf.sequence = vch->sequence++; -+ vb2_buffer_done(&done->vb, VB2_BUF_STATE_DONE); -+ } else { -+ dev_info(&dev->pdev->dev, "vch%u NOBUF seq=%u dcount=%u\n", -+ ID2CH(id), vch->sequence, ++vch->dcount); -+ } -+ return 0; -+} -+ -+static unsigned int tw6869_airq(struct tw6869_dev *dev, -+ unsigned int id, -+ unsigned int pb) -+{ -+ struct tw6869_ach *ach = &dev->ach[ID2CH(id)]; -+ struct tw6869_buf *done = NULL; -+ struct tw6869_buf *next = NULL; -+ -+ spin_lock(&ach->lock); -+ if (!ach->ss || !ach->p_buf || !ach->b_buf) { -+ spin_unlock(&ach->lock); -+ return TW_DMA_OFF; -+ } -+ -+ if (ach->pb != pb) { -+ ach->pb = 0; -+ spin_unlock(&ach->lock); -+ return TW_DMA_RST; -+ } -+ -+ if (!list_empty(&ach->buf_list)) { -+ next = list_first_entry(&ach->buf_list, struct tw6869_buf, list); -+ list_move_tail(&next->list, &ach->buf_list); -+ if (pb) { -+ done = ach->p_buf; -+ ach->b_buf = next; -+ } else { -+ done = ach->b_buf; -+ ach->p_buf = next; -+ } -+ } -+ ach->pb = !pb; -+ spin_unlock(&ach->lock); -+ -+ if (done && next) { -+ tw_write(dev, pb ? R32_DMA_B_ADDR(id) : R32_DMA_P_ADDR(id), next->dma); -+ ach->ptr = done->dma - ach->buf[0].dma; -+ snd_pcm_period_elapsed(ach->ss); -+ } else { -+ return TW_DMA_OFF; -+ } -+ return 0; -+} -+ -+static irqreturn_t tw6869_irq(int irq, void *dev_id) -+{ -+ struct tw6869_dev *dev = dev_id; -+ unsigned int int_sts, fifo_sts, pb_sts, dma_en, id; -+ -+ int_sts = tw_read(dev, R32_INT_STATUS); -+ fifo_sts = tw_read(dev, R32_FIFO_STATUS); -+ pb_sts = tw_read(dev, R32_PB_STATUS); -+ dma_en = tw_read(dev, R32_DMA_CHANNEL_ENABLE); -+ dma_en &= tw_read(dev, R32_DMA_CMD); -+ -+ for (id = 0; id < (2 * TW_CH_MAX); id++) { -+ unsigned int verr = fifo_sts & TW_VERR(id); -+ -+ if ((dma_en & BIT(id)) && ((int_sts & BIT(id)) || verr)) { -+ unsigned int pb = !!(pb_sts & BIT(id)); -+ unsigned int cmd = (BIT(id) & TW_VID) ? -+ tw6869_virq(dev, id, pb, verr) : -+ tw6869_airq(dev, id, pb); -+ -+ if (cmd) { -+ spin_lock(&dev->rlock); -+ tw6869_id_dma_cmd(dev, id, cmd); -+ spin_unlock(&dev->rlock); -+ } else { -+ dev->id_err[id] = 0; -+ } -+ } -+ } -+ return IRQ_HANDLED; -+} -+ -+/**********************************************************************/ -+ -+static inline struct tw6869_buf *to_tw6869_buf(struct vb2_buffer *vb2) -+{ -+ return container_of(vb2, struct tw6869_buf, vb); -+} -+ -+static int to_tw6869_pixformat(unsigned int pixelformat) -+{ -+ int ret; -+ -+ switch (pixelformat) { -+ case V4L2_PIX_FMT_YUYV: -+ ret = TW_FMT_YUYV; -+ break; -+ case V4L2_PIX_FMT_UYVY: -+ ret = TW_FMT_UYVY; -+ break; -+ case V4L2_PIX_FMT_RGB565: -+ ret = TW_FMT_RGB565; -+ break; -+ default: -+ ret = -EINVAL; -+ } -+ return ret; -+} -+ -+static unsigned int tw6869_fields_map(v4l2_std_id std, unsigned int rate) -+{ -+ unsigned int map[15] = { -+ 0x00000000, 0x00000001, 0x00004001, 0x00104001, 0x00404041, -+ 0x01041041, 0x01104411, 0x01111111, 0x04444445, 0x04511445, -+ 0x05145145, 0x05151515, 0x05515455, 0x05551555, 0x05555555 -+ }; -+ unsigned int std_625_50[26] = { -+ 0, 1, 1, 2, 3, 3, 4, 4, 5, 5, 6, 7, 7, -+ 8, 8, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 0 -+ }; -+ unsigned int std_525_60[31] = { -+ 0, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, -+ 8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 0, 0 -+ }; -+ unsigned int i = (std & V4L2_STD_625_50) ? -+ std_625_50[(rate > 25) ? 25 : rate] : -+ std_525_60[(rate > 30) ? 30 : rate]; -+ -+ return map[i]; -+} -+ -+static void tw6869_fill_pix_format(struct tw6869_vch *vch, -+ struct v4l2_pix_format *pix) -+{ -+ pix->width = 720; -+ pix->height = (vch->std & V4L2_STD_625_50) ? 576 : 480; -+ pix->field = V4L2_FIELD_INTERLACED_BT; -+ pix->colorspace = V4L2_COLORSPACE_SMPTE170M; -+ pix->bytesperline = pix->width * 2; -+ pix->sizeimage = pix->bytesperline * pix->height; -+ pix->priv = 0; -+} -+ -+static void tw6869_vch_hw_cfg(struct tw6869_vch *vch) -+{ -+ struct tw6869_dev *dev = vch->dev; -+ struct v4l2_pix_format *pix = &vch->format; -+ unsigned int cfg; -+ -+ if (vch->std & V4L2_STD_625_50) -+ tw_set(dev, R32_VIDEO_CONTROL1, BIT_CH(vch->id) << 13); -+ else -+ tw_clear(dev, R32_VIDEO_CONTROL1, BIT_CH(vch->id) << 13); -+ -+ cfg = tw6869_fields_map(vch->std, vch->fps) << 1; -+ cfg |= cfg << 1; -+ if (cfg > 0) -+ cfg |= BIT(31); -+ tw_write(dev, R32_VIDEO_FIELD_CTRL(vch->id), cfg); -+ -+ /* Analog mux input0, no drop, enable master */ -+ cfg = ((vch->input & 0x0) << 30) | -+ BIT(27) | (ID2SC(vch->id) << 25) | -+ ((to_tw6869_pixformat(pix->pixelformat) & 0x7) << 20); -+ tw_write(dev, R32_DMA_CHANNEL_CONFIG(vch->id), cfg); -+ -+ cfg = (((pix->height >> 1) & 0x3FF) << 22) | -+ ((pix->bytesperline & 0x7FF) << 11) | -+ (pix->bytesperline & 0x7FF); -+ tw_write(dev, R32_DMA_WHP(vch->id), cfg); -+ -+ tw_write(dev, R32_DMA_P_ADDR(vch->id), vch->p_buf->dma); -+ tw_write(dev, R32_DMA_B_ADDR(vch->id), vch->b_buf->dma); -+} -+ -+/* -+ * Videobuf2 Operations -+ */ -+static int queue_setup(struct vb2_queue *vq, const struct v4l2_format *fmt, -+ unsigned int *nbuffers, unsigned int *nplanes, -+ unsigned int sizes[], void *alloc_ctxs[]) -+{ -+ struct tw6869_vch *vch = vb2_get_drv_priv(vq); -+ struct tw6869_dev *dev = vch->dev; -+ -+ if (vq->num_buffers + *nbuffers < TW_FRAME_MAX) -+ *nbuffers = TW_FRAME_MAX - vq->num_buffers; -+ -+ if (fmt && fmt->fmt.pix.sizeimage < vch->format.sizeimage) -+ return -EINVAL; -+ -+ *nplanes = 1; -+ sizes[0] = fmt ? fmt->fmt.pix.sizeimage : vch->format.sizeimage; -+ alloc_ctxs[0] = dev->alloc_ctx; -+ return 0; -+} -+ -+static int buffer_init(struct vb2_buffer *vb) -+{ -+ struct tw6869_buf *buf = to_tw6869_buf(vb); -+ -+ buf->dma = vb2_dma_contig_plane_dma_addr(vb, 0); -+ INIT_LIST_HEAD(&buf->list); -+ { /* pass the buffer physical address */ -+ unsigned int *cpu = vb2_plane_vaddr(vb, 0); -+ *cpu = buf->dma; -+ } -+ return 0; -+} -+ -+static int buffer_prepare(struct vb2_buffer *vb) -+{ -+ struct tw6869_vch *vch = vb2_get_drv_priv(vb->vb2_queue); -+ unsigned long size = vch->format.sizeimage; -+ -+ if (vb2_plane_size(vb, 0) < size) { -+ v4l2_err(&vch->dev->v4l2_dev, "buffer too small (%lu < %lu)\n", -+ vb2_plane_size(vb, 0), size); -+ return -EINVAL; -+ } -+ -+ vb2_set_plane_payload(vb, 0, size); -+ return 0; -+} -+ -+static void buffer_queue(struct vb2_buffer *vb) -+{ -+ struct tw6869_vch *vch = vb2_get_drv_priv(vb->vb2_queue); -+ struct tw6869_buf *buf = to_tw6869_buf(vb); -+ unsigned long flags; -+ -+ spin_lock_irqsave(&vch->lock, flags); -+ list_add_tail(&buf->list, &vch->buf_list); -+ spin_unlock_irqrestore(&vch->lock, flags); -+} -+ -+static int start_streaming(struct vb2_queue *vq, unsigned int count) -+{ -+ struct tw6869_vch *vch = vb2_get_drv_priv(vq); -+ struct tw6869_dev *dev = vch->dev; -+ unsigned long flags; -+ -+ if (count < 2) -+ return -ENOBUFS; -+ -+ spin_lock_irqsave(&vch->lock, flags); -+ vch->p_buf = list_first_entry(&vch->buf_list, struct tw6869_buf, list); -+ list_del(&vch->p_buf->list); -+ -+ vch->b_buf = list_first_entry(&vch->buf_list, struct tw6869_buf, list); -+ list_del(&vch->b_buf->list); -+ -+ vch->sequence = 0; -+ vch->dcount = 0; -+ vch->pb = 0; -+ spin_unlock_irqrestore(&vch->lock, flags); -+ -+ spin_lock_irqsave(&dev->rlock, flags); -+ tw6869_vch_hw_cfg(vch); -+ tw6869_id_dma_cmd(dev, vch->id, TW_DMA_ON); -+ spin_unlock_irqrestore(&dev->rlock, flags); -+ -+ return 0; -+} -+ -+static int stop_streaming(struct vb2_queue *vq) -+{ -+ struct tw6869_vch *vch = vb2_get_drv_priv(vq); -+ struct tw6869_dev *dev = vch->dev; -+ struct tw6869_buf *buf, *node; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&dev->rlock, flags); -+ tw6869_id_dma_cmd(dev, vch->id, TW_DMA_OFF); -+ spin_unlock_irqrestore(&dev->rlock, flags); -+ -+ spin_lock_irqsave(&vch->lock, flags); -+ if (vch->p_buf) { -+ buf = vch->p_buf; -+ vch->p_buf = NULL; -+ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); -+ } -+ -+ if (vch->b_buf) { -+ buf = vch->b_buf; -+ vch->b_buf = NULL; -+ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); -+ } -+ -+ list_for_each_entry_safe(buf, node, &vch->buf_list, list) { -+ vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); -+ list_del(&buf->list); -+ } -+ spin_unlock_irqrestore(&vch->lock, flags); -+ -+ return 0; -+} -+ -+static struct vb2_ops tw6869_qops = { -+ .queue_setup = queue_setup, -+ .buf_init = buffer_init, -+ .buf_prepare = buffer_prepare, -+ .buf_queue = buffer_queue, -+ .start_streaming = start_streaming, -+ .stop_streaming = stop_streaming, -+ .wait_prepare = vb2_ops_wait_prepare, -+ .wait_finish = vb2_ops_wait_finish, -+}; -+ -+static int tw6869_querycap(struct file *file, void *priv, -+ struct v4l2_capability *cap) -+{ -+ struct tw6869_vch *vch = video_drvdata(file); -+ struct tw6869_dev *dev = vch->dev; -+ -+ strlcpy(cap->driver, KBUILD_MODNAME, sizeof(cap->driver)); -+ snprintf(cap->card, sizeof(cap->card), "tw6869 vch%u", ID2CH(vch->id)); -+ snprintf(cap->bus_info, sizeof(cap->bus_info), "PCI:%s", -+ pci_name(dev->pdev)); -+ cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_READWRITE | -+ V4L2_CAP_STREAMING; -+ cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS; -+ return 0; -+} -+ -+static int tw6869_try_fmt_vid_cap(struct file *file, void *priv, -+ struct v4l2_format *f) -+{ -+ struct tw6869_vch *vch = video_drvdata(file); -+ struct v4l2_pix_format *pix = &f->fmt.pix; -+ int ret; -+ -+ ret = to_tw6869_pixformat(pix->pixelformat); -+ if (ret < 0) -+ return ret; -+ -+ tw6869_fill_pix_format(vch, pix); -+ return 0; -+} -+ -+static int tw6869_s_fmt_vid_cap(struct file *file, void *priv, -+ struct v4l2_format *f) -+{ -+ struct tw6869_vch *vch = video_drvdata(file); -+ int ret; -+ -+ ret = tw6869_try_fmt_vid_cap(file, priv, f); -+ if (ret) -+ return ret; -+ -+ if (vb2_is_busy(&vch->queue)) -+ return -EBUSY; -+ -+ vch->format = f->fmt.pix; -+ return 0; -+} -+ -+static int tw6869_g_fmt_vid_cap(struct file *file, void *priv, -+ struct v4l2_format *f) -+{ -+ struct tw6869_vch *vch = video_drvdata(file); -+ -+ f->fmt.pix = vch->format; -+ return 0; -+} -+ -+static int tw6869_enum_fmt_vid_cap(struct file *file, void *priv, -+ struct v4l2_fmtdesc *f) -+{ -+ if (f->index > 2) -+ return -EINVAL; -+ -+ switch (f->index) { -+ case 1: -+ strcpy(f->description, "4:2:2, packed, YUYV"); -+ f->pixelformat = V4L2_PIX_FMT_YUYV; -+ break; -+ case 2: -+ strcpy(f->description, "16 bpp RGB, le"); -+ f->pixelformat = V4L2_PIX_FMT_RGB565; -+ break; -+ default: -+ strcpy(f->description, "4:2:2, packed, UYVY"); -+ f->pixelformat = V4L2_PIX_FMT_UYVY; -+ } -+ f->flags = 0; -+ return 0; -+} -+ -+static int tw6869_enum_framesizes(struct file *file, void *priv, -+ struct v4l2_frmsizeenum *fsize) -+{ -+ struct tw6869_vch *vch = video_drvdata(file); -+ -+ if (fsize->index != 0) -+ return -EINVAL; -+ -+ fsize->discrete.width = vch->format.width; -+ fsize->discrete.height = vch->format.height; -+ -+ return 0; -+} -+ -+static int tw6869_querystd(struct file *file, void *priv, v4l2_std_id *std) -+{ -+ struct tw6869_vch *vch = video_drvdata(file); -+ struct tw6869_dev *dev = vch->dev; -+ unsigned int std_now; -+ char *std_str; -+ -+ std_now = (tw_read(dev, R8_STANDARD_SEL(vch->id)) & 0x70) >> 4; -+ -+ switch (std_now) { -+ case TW_STD_PAL_M: -+ std_str = "PAL (M)"; -+ *std = V4L2_STD_525_60; -+ break; -+ case TW_STD_PAL_60: -+ std_str = "PAL 60"; -+ *std = V4L2_STD_525_60; -+ break; -+ case TW_STD_NTSC_M: -+ std_str = "NTSC (M)"; -+ *std = V4L2_STD_525_60; -+ break; -+ case TW_STD_NTSC_443: -+ std_str = "NTSC 4.43"; -+ *std = V4L2_STD_525_60; -+ break; -+ case TW_STD_PAL: -+ std_str = "PAL (B,D,G,H,I)"; -+ *std = V4L2_STD_625_50; -+ break; -+ case TW_STD_PAL_CN: -+ std_str = "PAL (CN)"; -+ *std = V4L2_STD_625_50; -+ break; -+ case TW_STD_SECAM: -+ std_str = "SECAM"; -+ *std = V4L2_STD_625_50; -+ break; -+ default: -+ std_str = "Not valid"; -+ *std = 0; -+ } -+ v4l2_info(&dev->v4l2_dev, "vch%u std %s\n", ID2CH(vch->id), std_str); -+ return 0; -+} -+ -+static int tw6869_s_std(struct file *file, void *priv, v4l2_std_id std) -+{ -+ struct tw6869_vch *vch = video_drvdata(file); -+ v4l2_std_id new_std = (std & V4L2_STD_625_50) ? -+ V4L2_STD_625_50 : V4L2_STD_525_60; -+ -+ if (new_std == vch->std) -+ return 0; -+ -+ if (vb2_is_busy(&vch->queue)) -+ return -EBUSY; -+ -+ vch->std = new_std; -+ vch->fps = (new_std & V4L2_STD_625_50) ? 25 : 30; -+ tw6869_fill_pix_format(vch, &vch->format); -+ return 0; -+} -+ -+static int tw6869_g_std(struct file *file, void *priv, v4l2_std_id *std) -+{ -+ struct tw6869_vch *vch = video_drvdata(file); -+ v4l2_std_id new_std = 0; -+ -+ tw6869_querystd(file, priv, &new_std); -+ if (new_std) -+ tw6869_s_std(file, priv, new_std); -+ -+ vch->fps = (vch->std & V4L2_STD_625_50) ? 25 : 30; -+ *std = vch->std; -+ return 0; -+} -+ -+/* SK-TW6869: only input0 is available */ -+static int tw6869_enum_input(struct file *file, void *priv, -+ struct v4l2_input *i) -+{ -+ if (i->index >= TW_VIN_MAX) -+ return -EINVAL; -+ -+ i->type = V4L2_INPUT_TYPE_CAMERA; -+ i->std = V4L2_STD_ALL; -+ sprintf(i->name, "Camera %d", i->index); -+ return 0; -+} -+ -+static int tw6869_s_input(struct file *file, void *priv, unsigned int i) -+{ -+ struct tw6869_vch *vch = video_drvdata(file); -+ -+ vch->input = i; -+ return 0; -+} -+ -+static int tw6869_g_input(struct file *file, void *priv, unsigned int *i) -+{ -+ struct tw6869_vch *vch = video_drvdata(file); -+ -+ *i = vch->input; -+ return 0; -+} -+ -+static int tw6869_g_parm(struct file *file, void *priv, -+ struct v4l2_streamparm *sp) -+{ -+ struct tw6869_vch *vch = video_drvdata(file); -+ struct v4l2_captureparm *cp = &sp->parm.capture; -+ -+ cp->capability = V4L2_CAP_TIMEPERFRAME; -+ cp->timeperframe.numerator = 1; -+ cp->timeperframe.denominator = vch->fps; -+ return 0; -+} -+ -+static int tw6869_s_parm(struct file *file, void *priv, -+ struct v4l2_streamparm *sp) -+{ -+ struct tw6869_vch *vch = video_drvdata(file); -+ unsigned int denominator = sp->parm.capture.timeperframe.denominator; -+ unsigned int numerator = sp->parm.capture.timeperframe.numerator; -+ unsigned int fps; -+ -+ fps = (!numerator || !denominator) ? 0 : denominator / numerator; -+ if (vch->std & V4L2_STD_625_50) -+ fps = (!fps || fps > 25) ? 25 : fps; -+ else -+ fps = (!fps || fps > 30) ? 30 : fps; -+ -+ vch->fps = fps; -+ v4l2_info(&vch->dev->v4l2_dev, -+ "vch%u fps %u\n", ID2CH(vch->id), vch->fps); -+ -+ return tw6869_g_parm(file, priv, sp); -+} -+ -+/* The control handler */ -+static int tw6869_s_ctrl(struct v4l2_ctrl *ctrl) -+{ -+ struct tw6869_vch *vch = -+ container_of(ctrl->handler, struct tw6869_vch, hdl); -+ struct tw6869_dev *dev = vch->dev; -+ unsigned int id = vch->id; -+ int ret = 0; -+ -+ switch (ctrl->id) { -+ case V4L2_CID_BRIGHTNESS: -+ tw_write(dev, R8_BRIGHT_CTRL(id), ctrl->val); -+ break; -+ case V4L2_CID_CONTRAST: -+ tw_write(dev, R8_CONTRAST_CTRL(id), ctrl->val); -+ break; -+ case V4L2_CID_SATURATION: -+ tw_write(dev, R8_SAT_U_CTRL(id), ctrl->val); -+ tw_write(dev, R8_SAT_V_CTRL(id), ctrl->val); -+ break; -+ case V4L2_CID_HUE: -+ tw_write(dev, R8_HUE_CTRL(id), ctrl->val); -+ break; -+ default: -+ ret = -EINVAL; -+ } -+ return ret; -+} -+ -+/* -+ * File operations for the device -+ */ -+static const struct v4l2_ctrl_ops tw6869_ctrl_ops = { -+ .s_ctrl = tw6869_s_ctrl, -+}; -+ -+static const struct v4l2_ioctl_ops tw6869_ioctl_ops = { -+ .vidioc_querycap = tw6869_querycap, -+ .vidioc_try_fmt_vid_cap = tw6869_try_fmt_vid_cap, -+ .vidioc_s_fmt_vid_cap = tw6869_s_fmt_vid_cap, -+ .vidioc_g_fmt_vid_cap = tw6869_g_fmt_vid_cap, -+ .vidioc_enum_fmt_vid_cap = tw6869_enum_fmt_vid_cap, -+ .vidioc_enum_framesizes = tw6869_enum_framesizes, -+ -+ .vidioc_querystd = tw6869_querystd, -+ .vidioc_s_std = tw6869_s_std, -+ .vidioc_g_std = tw6869_g_std, -+ -+ .vidioc_enum_input = tw6869_enum_input, -+ .vidioc_s_input = tw6869_s_input, -+ .vidioc_g_input = tw6869_g_input, -+ -+ .vidioc_g_parm = tw6869_g_parm, -+ .vidioc_s_parm = tw6869_s_parm, -+ -+ .vidioc_reqbufs = vb2_ioctl_reqbufs, -+ .vidioc_create_bufs = vb2_ioctl_create_bufs, -+ .vidioc_querybuf = vb2_ioctl_querybuf, -+ .vidioc_qbuf = vb2_ioctl_qbuf, -+ .vidioc_dqbuf = vb2_ioctl_dqbuf, -+ .vidioc_expbuf = vb2_ioctl_expbuf, -+ .vidioc_streamon = vb2_ioctl_streamon, -+ .vidioc_streamoff = vb2_ioctl_streamoff, -+ -+ .vidioc_log_status = v4l2_ctrl_log_status, -+ .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, -+ .vidioc_unsubscribe_event = v4l2_event_unsubscribe, -+}; -+ -+static const struct v4l2_file_operations tw6869_fops = { -+ .owner = THIS_MODULE, -+ .open = v4l2_fh_open, -+ .release = vb2_fop_release, -+ .unlocked_ioctl = video_ioctl2, -+ .read = vb2_fop_read, -+ .mmap = vb2_fop_mmap, -+ .poll = vb2_fop_poll, -+}; -+ -+static int tw6869_vch_register(struct tw6869_vch *vch) -+{ -+ struct tw6869_dev *dev = vch->dev; -+ struct v4l2_ctrl_handler *hdl = &vch->hdl; -+ struct vb2_queue *q = &vch->queue; -+ struct video_device *vdev = &vch->vdev; -+ int ret = 0; -+ -+ /* Add the controls */ -+ v4l2_ctrl_handler_init(hdl, 4); -+ v4l2_ctrl_new_std(hdl, &tw6869_ctrl_ops, -+ V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); -+ v4l2_ctrl_new_std(hdl, &tw6869_ctrl_ops, -+ V4L2_CID_CONTRAST, 0, 255, 1, 100); -+ v4l2_ctrl_new_std(hdl, &tw6869_ctrl_ops, -+ V4L2_CID_SATURATION, 0, 255, 1, 128); -+ v4l2_ctrl_new_std(hdl, &tw6869_ctrl_ops, -+ V4L2_CID_HUE, -128, 127, 1, 0); -+ if (hdl->error) { -+ ret = hdl->error; -+ return ret; -+ } -+ -+ /* Fill in the initial format-related settings */ -+ vch->std = V4L2_STD_525_60; -+ vch->fps = 30; -+ vch->format.pixelformat = V4L2_PIX_FMT_UYVY; -+ tw6869_fill_pix_format(vch, &vch->format); -+ -+ mutex_init(&vch->mlock); -+ -+ /* Initialize the vb2 queue */ -+ q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; -+ q->io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ; -+ q->drv_priv = vch; -+ q->buf_struct_size = sizeof(struct tw6869_buf); -+ q->ops = &tw6869_qops; -+ q->mem_ops = &vb2_dma_contig_memops; -+ q->timestamp_type = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; -+ q->lock = &vch->mlock; -+ q->gfp_flags = __GFP_DMA32; -+ ret = vb2_queue_init(q); -+ if (ret) -+ goto free_hdl; -+ -+ spin_lock_init(&vch->lock); -+ INIT_LIST_HEAD(&vch->buf_list); -+ -+ /* Initialize the video_device structure */ -+ strlcpy(vdev->name, KBUILD_MODNAME, sizeof(vdev->name)); -+ vdev->release = video_device_release_empty; -+ vdev->fops = &tw6869_fops, -+ vdev->ioctl_ops = &tw6869_ioctl_ops, -+ vdev->lock = &vch->mlock; -+ vdev->queue = q; -+ vdev->v4l2_dev = &dev->v4l2_dev; -+ vdev->ctrl_handler = hdl; -+ vdev->tvnorms = V4L2_STD_ALL; -+ video_set_drvdata(vdev, vch); -+ ret = video_register_device(vdev, VFL_TYPE_GRABBER, -1); -+ if (!ret) -+ return 0; -+ -+free_hdl: -+ v4l2_ctrl_handler_free(hdl); -+ return ret; -+} -+ -+static void tw6869_video_unregister(struct tw6869_dev *dev) -+{ -+ unsigned int i; -+ -+ /* Reset and disable all DMA channels */ -+ tw_write(dev, R32_DMA_CMD, 0); -+ tw_write(dev, R32_DMA_CHANNEL_ENABLE, 0); -+ -+ if (!dev->alloc_ctx) -+ return; -+ -+ if (dev->ch_max > TW_CH_MAX) -+ dev->ch_max = TW_CH_MAX; -+ -+ for (i = 0; i < dev->ch_max; i++) { -+ struct tw6869_vch *vch = &dev->vch[ID2CH(i)]; -+ video_unregister_device(&vch->vdev); -+ v4l2_ctrl_handler_free(&vch->hdl); -+ } -+ -+ v4l2_device_unregister(&dev->v4l2_dev); -+ vb2_dma_contig_cleanup_ctx(dev->alloc_ctx); -+ dev->alloc_ctx = NULL; -+} -+ -+static int tw6869_video_register(struct tw6869_dev *dev) -+{ -+ struct pci_dev *pdev = dev->pdev; -+ unsigned int i; -+ int ret; -+ -+ /* Initialize the top-level structure */ -+ ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev); -+ if (ret) -+ return ret; -+ -+ dev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev); -+ if (IS_ERR(dev->alloc_ctx)) { -+ ret = PTR_ERR(dev->alloc_ctx); -+ v4l2_err(&dev->v4l2_dev, "can't allocate buffer context\n"); -+ v4l2_device_unregister(&dev->v4l2_dev); -+ dev->alloc_ctx = NULL; -+ return ret; -+ } -+ -+ for (i = 0; i < TW_CH_MAX; i++) { -+ struct tw6869_vch *vch = &dev->vch[ID2CH(i)]; -+ vch->dev = dev; -+ vch->id = i; -+ ret = tw6869_vch_register(vch); -+ if (ret) { -+ dev->ch_max = i; -+ tw6869_video_unregister(dev); -+ return ret; -+ } -+ dev_info(&pdev->dev, "vch%i registered as %s\n", -+ vch->id, -+ video_device_node_name(&vch->vdev)); -+ } -+ return 0; -+} -+ -+/**********************************************************************/ -+ -+static int tw6869_pcm_hw_params(struct snd_pcm_substream *ss, -+ struct snd_pcm_hw_params *hw_params) -+{ -+ return snd_pcm_lib_malloc_pages(ss, params_buffer_bytes(hw_params)); -+} -+ -+static int tw6869_pcm_hw_free(struct snd_pcm_substream *ss) -+{ -+ return snd_pcm_lib_free_pages(ss); -+} -+ -+static const struct snd_pcm_hardware tw6869_capture_hw = { -+ .info = (SNDRV_PCM_INFO_MMAP | -+ SNDRV_PCM_INFO_INTERLEAVED | -+ SNDRV_PCM_INFO_BLOCK_TRANSFER | -+ SNDRV_PCM_INFO_MMAP_VALID), -+ .formats = SNDRV_PCM_FMTBIT_S16_LE, -+ .rates = SNDRV_PCM_RATE_48000, -+ .rate_min = 48000, -+ .rate_max = 48000, -+ .channels_min = 1, -+ .channels_max = 1, -+ .buffer_bytes_max = TW_PAGE_SIZE * TW_APAGE_MAX, -+ .period_bytes_min = TW_PAGE_SIZE, -+ .period_bytes_max = TW_PAGE_SIZE, -+ .periods_min = 2, -+ .periods_max = TW_APAGE_MAX, -+}; -+ -+static int tw6869_pcm_open(struct snd_pcm_substream *ss) -+{ -+ struct tw6869_dev *dev = snd_pcm_substream_chip(ss); -+ struct tw6869_ach *ach = &dev->ach[ID2CH(ss->number)]; -+ struct snd_pcm_runtime *rt = ss->runtime; -+ int ret; -+ -+ rt->hw = tw6869_capture_hw; -+ ret = snd_pcm_hw_constraint_integer(rt, SNDRV_PCM_HW_PARAM_PERIODS); -+ if (ret < 0) -+ return ret; -+ -+ ach->ss = ss; -+ return 0; -+} -+ -+static int tw6869_pcm_close(struct snd_pcm_substream *ss) -+{ -+ struct tw6869_dev *dev = snd_pcm_substream_chip(ss); -+ struct tw6869_ach *ach = &dev->ach[ID2CH(ss->number)]; -+ -+ ach->ss = NULL; -+ return 0; -+} -+ -+static int tw6869_pcm_prepare(struct snd_pcm_substream *ss) -+{ -+ struct tw6869_dev *dev = snd_pcm_substream_chip(ss); -+ struct tw6869_ach *ach = &dev->ach[ID2CH(ss->number)]; -+ struct snd_pcm_runtime *rt = ss->runtime; -+ unsigned int period = snd_pcm_lib_period_bytes(ss); -+ unsigned long flags; -+ unsigned int i; -+ -+ spin_lock_irqsave(&ach->lock, flags); -+ ach->p_buf = NULL; -+ ach->b_buf = NULL; -+ -+ if ((period != TW_PAGE_SIZE) || -+ (rt->periods < 2) || -+ (rt->periods > TW_APAGE_MAX)) { -+ spin_unlock_irqrestore(&ach->lock, flags); -+ return -EINVAL; -+ } -+ -+ INIT_LIST_HEAD(&ach->buf_list); -+ for (i = 0; i < rt->periods; i++) { -+ ach->buf[i].dma = rt->dma_addr + period * i; -+ INIT_LIST_HEAD(&ach->buf[i].list); -+ list_add_tail(&ach->buf[i].list, &ach->buf_list); -+ } -+ -+ ach->p_buf = list_first_entry(&ach->buf_list, struct tw6869_buf, list); -+ list_move_tail(&ach->p_buf->list, &ach->buf_list); -+ -+ ach->b_buf = list_first_entry(&ach->buf_list, struct tw6869_buf, list); -+ list_move_tail(&ach->b_buf->list, &ach->buf_list); -+ -+ ach->ptr = 0; -+ ach->pb = 0; -+ spin_unlock_irqrestore(&ach->lock, flags); -+ -+ return 0; -+} -+ -+static void tw6869_ach_hw_cfg(struct tw6869_ach *ach) -+{ -+ struct tw6869_dev *dev = ach->dev; -+ -+ tw_write(dev, R32_DMA_P_ADDR(ach->id), ach->p_buf->dma); -+ tw_write(dev, R32_DMA_B_ADDR(ach->id), ach->b_buf->dma); -+} -+ -+static int tw6869_pcm_trigger(struct snd_pcm_substream *ss, int cmd) -+{ -+ struct tw6869_dev *dev = snd_pcm_substream_chip(ss); -+ struct tw6869_ach *ach = &dev->ach[ID2CH(ss->number)]; -+ unsigned long flags; -+ int ret = 0; -+ -+ switch (cmd) { -+ case SNDRV_PCM_TRIGGER_START: -+ if (ach->p_buf && ach->b_buf) { -+ spin_lock_irqsave(&dev->rlock, flags); -+ tw6869_ach_hw_cfg(ach); -+ tw6869_id_dma_cmd(dev, ach->id, TW_DMA_ON); -+ spin_unlock_irqrestore(&dev->rlock, flags); -+ } else { -+ ret = -EIO; -+ } -+ break; -+ case SNDRV_PCM_TRIGGER_STOP: -+ spin_lock_irqsave(&dev->rlock, flags); -+ tw6869_id_dma_cmd(dev, ach->id, TW_DMA_OFF); -+ spin_unlock_irqrestore(&dev->rlock, flags); -+ -+ spin_lock_irqsave(&ach->lock, flags); -+ ach->p_buf = NULL; -+ ach->b_buf = NULL; -+ spin_unlock_irqrestore(&ach->lock, flags); -+ break; -+ default: -+ ret = -EINVAL; -+ } -+ return ret; -+} -+ -+static snd_pcm_uframes_t tw6869_pcm_pointer(struct snd_pcm_substream *ss) -+{ -+ struct tw6869_dev *dev = snd_pcm_substream_chip(ss); -+ struct tw6869_ach *ach = &dev->ach[ID2CH(ss->number)]; -+ -+ return bytes_to_frames(ss->runtime, ach->ptr); -+} -+ -+static struct snd_pcm_ops tw6869_pcm_ops = { -+ .open = tw6869_pcm_open, -+ .close = tw6869_pcm_close, -+ .ioctl = snd_pcm_lib_ioctl, -+ .hw_params = tw6869_pcm_hw_params, -+ .hw_free = tw6869_pcm_hw_free, -+ .prepare = tw6869_pcm_prepare, -+ .trigger = tw6869_pcm_trigger, -+ .pointer = tw6869_pcm_pointer, -+}; -+ -+static int tw6869_snd_pcm_init(struct tw6869_dev *dev) -+{ -+ struct snd_card *card = dev->snd_card; -+ struct snd_pcm *pcm; -+ struct snd_pcm_substream *ss; -+ int ret; -+ -+ ret = snd_pcm_new(card, card->driver, 0, 0, TW_CH_MAX, &pcm); -+ if (ret < 0) -+ return ret; -+ -+ snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &tw6869_pcm_ops); -+ snd_pcm_chip(pcm) = dev; -+ pcm->info_flags = 0; -+ strcpy(pcm->name, card->shortname); -+ -+ ss = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream; -+ while (ss && (ss->next != ss)) { -+ struct tw6869_ach *ach = &dev->ach[ID2CH(ss->number)]; -+ ach->dev = dev; -+ ach->id = ID2CH(ss->number) + TW_CH_MAX; -+ spin_lock_init(&ach->lock); -+ sprintf(ss->name, "vch%u audio", ID2CH(ss->number)); -+ ss = ss->next; -+ } -+ -+ return snd_pcm_lib_preallocate_pages_for_all(pcm, -+ SNDRV_DMA_TYPE_DEV, -+ snd_dma_pci_data(dev->pdev), -+ TW_APAGE_MAX * TW_PAGE_SIZE, -+ TW_APAGE_MAX * TW_PAGE_SIZE); -+} -+ -+static void tw6869_audio_unregister(struct tw6869_dev *dev) -+{ -+ /* Reset and disable audio DMA */ -+ tw_clear(dev, R32_DMA_CMD, TW_AID); -+ tw_clear(dev, R32_DMA_CHANNEL_ENABLE, TW_AID); -+ -+ if (!dev->snd_card) -+ return; -+ -+ snd_card_free(dev->snd_card); -+ dev->snd_card = NULL; -+} -+ -+/* TODO: mixer controls */ -+static int tw6869_audio_register(struct tw6869_dev *dev) -+{ -+ struct pci_dev *pdev = dev->pdev; -+ static struct snd_device_ops ops = { NULL }; -+ struct snd_card *card; -+ int ret; -+ -+ ret = snd_card_create(SNDRV_DEFAULT_IDX1, KBUILD_MODNAME, -+ THIS_MODULE, 0, &card); -+ if (ret < 0) -+ return ret; -+ -+ dev->snd_card = card; -+ -+ strcpy(card->driver, KBUILD_MODNAME); -+ strcpy(card->shortname, KBUILD_MODNAME); -+ sprintf(card->longname, "%s on %s IRQ %d", card->shortname, -+ pci_name(pdev), pdev->irq); -+ -+ ret = snd_device_new(card, SNDRV_DEV_LOWLEVEL, dev, &ops); -+ if (ret < 0) -+ goto snd_error; -+ -+ snd_card_set_dev(card, &pdev->dev); -+ -+ ret = tw6869_snd_pcm_init(dev); -+ if (ret < 0) -+ goto snd_error; -+ -+ ret = snd_card_register(card); -+ if (!ret) -+ return 0; -+ -+snd_error: -+ snd_card_free(card); -+ dev->snd_card = NULL; -+ return ret; -+} -+ -+/**********************************************************************/ -+ -+static void tw6869_reset(struct tw6869_dev *dev) -+{ -+ /* Software Reset */ -+ tw_write(dev, R32_SYS_SOFT_RST, 0x01); -+ tw_write(dev, R32_SYS_SOFT_RST, 0x0F); -+ -+ /* Reset Internal audio and video decoders */ -+ tw_write(dev, R8_AVSRST(0), 0x1F); -+ tw_write(dev, R8_AVSRST(4), 0x1F); -+ -+ /* Reset all DMA channels */ -+ tw_write(dev, R32_DMA_CMD, 0); -+ -+ /* Disable all DMA channels */ -+ tw_write(dev, R32_DMA_CHANNEL_ENABLE, 0); -+ -+ /* Enable DMA FIFO overflow and pointer check */ -+ tw_write(dev, R32_DMA_CONFIG, 0x00FFFF04); -+ -+ /* Minimum time span for DMA interrupting host (default: 0x00098968) */ -+ tw_write(dev, R32_DMA_TIMER_INTERVAL, 0x00098968); -+ -+ /* DMA timeout (default: 0x140C8584) */ -+ tw_write(dev, R32_DMA_CHANNEL_TIMEOUT, 0x140C8584); -+ -+ /* Frame mode DMA */ -+ tw_write(dev, R32_PHASE_REF, 0xAAAA144D); -+ -+ /* Show blue background if no signal */ -+ tw_write(dev, R8_MISC_CONTROL1(0), 0xE7); -+ tw_write(dev, R8_MISC_CONTROL1(4), 0xE7); -+ -+ /* Audio DMA 4096 bytes, sampling frequency reference 48 kHz */ -+ tw_write(dev, R32_AUDIO_CONTROL1, 0x80000001 | (0x0A2C << 5)); -+ tw_write(dev, R32_AUDIO_CONTROL2, 0x0A2C2AAA); -+} -+ -+static int tw6869_probe(struct pci_dev *pdev, const struct pci_device_id *ent) -+{ -+ struct tw6869_dev *dev; -+ int ret; -+ -+ /* Allocate a new instance */ -+ dev = devm_kzalloc(&pdev->dev, sizeof(struct tw6869_dev), GFP_KERNEL); -+ if (!dev) -+ return -ENOMEM; -+ -+ ret = pci_enable_device(pdev); -+ if (ret) -+ return ret; -+ -+ pci_set_master(pdev); -+ ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); -+ if (ret) { -+ dev_err(&pdev->dev, "no suitable DMA available\n"); -+ goto disable_pci; -+ } -+ -+ ret = pci_request_regions(pdev, KBUILD_MODNAME); -+ if (ret) -+ goto disable_pci; -+ -+ dev->mmio = pci_iomap(pdev, 0, 0); -+ if (!dev->mmio) { -+ ret = -EIO; -+ goto release_regs; -+ } -+ -+ tw6869_reset(dev); -+ -+ ret = devm_request_irq(&pdev->dev, pdev->irq, -+ tw6869_irq, IRQF_SHARED, KBUILD_MODNAME, dev); -+ if (ret) { -+ dev_err(&pdev->dev, "request_irq failed\n"); -+ goto unmap_regs; -+ } -+ -+ dev->pdev = pdev; -+ dev->ch_max = TW_CH_MAX; -+ spin_lock_init(&dev->rlock); -+ -+ ret = tw6869_video_register(dev); -+ if (ret) -+ goto unmap_regs; -+ -+ ret = tw6869_audio_register(dev); -+ if (ret) -+ goto video_unreg; -+ -+ dev_info(&pdev->dev, "driver loaded\n"); -+ return 0; -+ -+video_unreg: -+ tw6869_video_unregister(dev); -+unmap_regs: -+ pci_iounmap(pdev, dev->mmio); -+release_regs: -+ pci_release_regions(pdev); -+disable_pci: -+ pci_disable_device(pdev); -+ return ret; -+} -+ -+static void tw6869_remove(struct pci_dev *pdev) -+{ -+ struct v4l2_device *v4l2_dev = pci_get_drvdata(pdev); -+ struct tw6869_dev *dev = -+ container_of(v4l2_dev, struct tw6869_dev, v4l2_dev); -+ -+ tw6869_audio_unregister(dev); -+ tw6869_video_unregister(dev); -+ pci_iounmap(pdev, dev->mmio); -+ pci_release_regions(pdev); -+ pci_disable_device(pdev); -+} -+ -+/* TODO: PM */ -+static struct pci_driver tw6869_driver = { -+ .name = KBUILD_MODNAME, -+ .probe = tw6869_probe, -+ .remove = tw6869_remove, -+ .id_table = tw6869_pci_tbl, -+}; -+ -+module_pci_driver(tw6869_driver); -diff -Nur linux-4.1.13.orig/drivers/media/pci/tw6869/tw6869.h linux-4.1.13/drivers/media/pci/tw6869/tw6869.h ---- linux-4.1.13.orig/drivers/media/pci/tw6869/tw6869.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/media/pci/tw6869/tw6869.h 2015-11-30 17:56:13.596136660 +0100 -@@ -0,0 +1,119 @@ -+/* -+ * Copyright 2015 www.starterkit.ru -+ * -+ * Based on: -+ * tw686x common header file -+ * Copyright 2009-10 liran [Techwell China] -+ * -+ * This program is free software; you may redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; version 2 of the License. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN -+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN -+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -+ * SOFTWARE. -+ */ -+ -+#ifndef __TW6869_H -+#define __TW6869_H -+ -+#define PCI_VENDOR_ID_TECHWELL 0x1797 -+#define PCI_DEVICE_ID_6869 0x6869 -+ -+#define TW_CH_MAX 8 -+#define TW_VIN_MAX 4 -+#define TW_FRAME_MAX 4 -+#define TW_APAGE_MAX 16 -+#define TW_DMA_ERR_MAX 5 -+#define TW_PAGE_SIZE 4096 -+ -+#define TW_VID 0x00FF -+#define TW_AID 0xFF00 -+#define TW_CH_0to3 0x0F -+#define TW_CH_4to7 0xF0 -+ -+#define ID2ID(id) ((id) & 0xF) -+#define ID2CH(id) ((id) & 0x7) -+#define ID2SC(id) ((id) & 0x3) -+ -+#define BIT_ID(id) BIT((id) & 0xF) -+#define BIT_CH(id) BIT((id) & 0x7) -+#define BIT_SC(id) BIT((id) & 0x3) -+ -+#define IS_VID(id) (BIT_ID(id) & TW_VID) -+#define IS_CH03(id) (BIT_CH(id) & TW_CH_0to3) -+ -+#define TW_FIFO_ERR(id) ((BIT(24) | BIT(16)) << ID2CH(id)) -+#define TW_PARS_ERR(id) ((BIT(8) | BIT(0)) << ID2CH(id)) -+#define TW_VERR(id) (IS_VID(id) ? TW_FIFO_ERR(id) : 0) -+ -+#define TW_DMA_ON 1 -+#define TW_DMA_OFF 2 -+#define TW_DMA_RST 3 -+ -+#define TW_STD_NTSC_M 0 -+#define TW_STD_PAL 1 -+#define TW_STD_SECAM 2 -+#define TW_STD_NTSC_443 3 -+#define TW_STD_PAL_M 4 -+#define TW_STD_PAL_CN 5 -+#define TW_STD_PAL_60 6 -+ -+#define TW_FMT_UYVY 0 -+#define TW_FMT_RGB565 5 -+#define TW_FMT_YUYV 6 -+ -+/** -+ * Register definitions -+ */ -+#define R32_INT_STATUS 0x000 /* 0x00 */ -+#define R32_PB_STATUS 0x004 /* 0x01 */ -+#define R32_DMA_CMD 0x008 /* 0x02 */ -+#define R32_FIFO_STATUS 0x00C /* 0x03 */ -+#define R32_VIDEO_CHANNEL_ID 0x010 /* 0x04 */ -+#define R32_VIDEO_PARSER_STATUS 0x014 /* 0x05 */ -+#define R32_SYS_SOFT_RST 0x018 /* 0x06 */ -+#define R32_DMA_CHANNEL_ENABLE 0x028 /* 0x0a */ -+#define R32_DMA_CONFIG 0x02C /* 0x0b */ -+#define R32_DMA_TIMER_INTERVAL 0x030 /* 0x0c */ -+#define R32_DMA_CHANNEL_TIMEOUT 0x034 /* 0x0d */ -+#define R32_DMA_CHANNEL_CONFIG(id) (0x040 + ID2CH(id) * 0x04) /* 0x10 */ -+#define R32_VIDEO_CONTROL1 0x0A8 /* 0x2A */ -+#define R32_VIDEO_CONTROL2 0x0AC /* 0x2B */ -+#define R32_AUDIO_CONTROL1 0x0B0 /* 0x2C */ -+#define R32_AUDIO_CONTROL2 0x0B4 /* 0x2D */ -+#define R32_PHASE_REF 0x0B8 /* 0x2E */ -+#define R32_VIDEO_FIELD_CTRL(id) (0x0E4 + ID2CH(id) * 0x04) /* 0x39 */ -+#define R32_DMA_P_ADDR(id) (IS_VID(id) ? (0x200 + ID2CH(id) * 0x20) : (0x060 + ID2CH(id) * 0x08)) -+#define R32_DMA_B_ADDR(id) (IS_VID(id) ? (0x208 + ID2CH(id) * 0x20) : (0x064 + ID2CH(id) * 0x08)) -+#define R32_DMA_WHP(id) (0x204 + ID2CH(id) * 0x20) /* 0x81 */ -+ -+/* 0x100, 0x200 */ -+#define R8_VIDEO_STATUS(id) ((IS_CH03(id) ? 0x400 : 0x800) + ID2SC(id) * 0x40) -+/* 0x101, 0x201 */ -+#define R8_BRIGHT_CTRL(id) ((IS_CH03(id) ? 0x404 : 0x804) + ID2SC(id) * 0x40) -+/* 0x102, 0x202 */ -+#define R8_CONTRAST_CTRL(id) ((IS_CH03(id) ? 0x408 : 0x808) + ID2SC(id) * 0x40) -+/* 0x104, 0x204 */ -+#define R8_SAT_U_CTRL(id) ((IS_CH03(id) ? 0x410 : 0x810) + ID2SC(id) * 0x40) -+/* 0x105, 0x205 */ -+#define R8_SAT_V_CTRL(id) ((IS_CH03(id) ? 0x414 : 0x814) + ID2SC(id) * 0x40) -+/* 0x106, 0x206 */ -+#define R8_HUE_CTRL(id) ((IS_CH03(id) ? 0x418 : 0x818) + ID2SC(id) * 0x40) -+/* 0x10E, 0x20E */ -+#define R8_STANDARD_SEL(id) ((IS_CH03(id) ? 0x438 : 0x838) + ID2SC(id) * 0x40) -+/* 0x180, 0x280 */ -+#define R8_AVSRST(id) (IS_CH03(id) ? 0x600 : 0xA00) -+/* 0x18F, 0x28F */ -+#define R8_VERTICAL_CONTROL1(id) (IS_CH03(id) ? 0x63C : 0xA3C) -+/* 0x196, 0x296 */ -+#define R8_MISC_CONTROL1(id) (IS_CH03(id) ? 0x658 : 0xA58) -+/* 0x1D0, 0x2D0 */ -+#define R8_AIGAIN_CTRL(id) ((IS_CH03(id) ? 0x740 : 0xB40) + ID2SC(id) * 0x04) -+ -+#endif /* __TW6869_H */ -diff -Nur linux-4.1.13.orig/drivers/media/platform/Kconfig linux-4.1.13/drivers/media/platform/Kconfig ---- linux-4.1.13.orig/drivers/media/platform/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/media/platform/Kconfig 2015-11-30 17:56:13.596136660 +0100 -@@ -114,6 +114,22 @@ - To compile this driver as a module, choose M here: the module - will be called s3c-camif. - -+config VIDEO_MXC_OUTPUT -+ tristate "MXC Video For Linux Video Output" -+ depends on VIDEO_DEV && ARCH_MXC && FB_MXC -+ select VIDEOBUF_DMA_CONTIG -+ ---help--- -+ This is the video4linux2 output driver based on MXC module. -+ -+config VIDEO_MXC_CAPTURE -+ tristate "MXC Video For Linux Video Capture" -+ depends on VIDEO_V4L2 -+ select VIDEO_V4L2_INT_DEVICE -+ ---help--- -+ This is the video4linux2 capture driver based on i.MX video-in module. -+ -+source "drivers/media/platform/mxc/capture/Kconfig" -+source "drivers/media/platform/mxc/output/Kconfig" - source "drivers/media/platform/soc_camera/Kconfig" - source "drivers/media/platform/exynos4-is/Kconfig" - source "drivers/media/platform/s5p-tv/Kconfig" -diff -Nur linux-4.1.13.orig/drivers/media/platform/Makefile linux-4.1.13/drivers/media/platform/Makefile ---- linux-4.1.13.orig/drivers/media/platform/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/media/platform/Makefile 2015-11-30 17:56:13.596136660 +0100 -@@ -50,4 +50,7 @@ - - obj-$(CONFIG_VIDEO_XILINX) += xilinx/ - -+obj-y += mxc/capture/ -+obj-y += mxc/output/ -+ - ccflags-y += -I$(srctree)/drivers/media/i2c -diff -Nur linux-4.1.13.orig/drivers/media/platform/mxc/capture/adv7180.c linux-4.1.13/drivers/media/platform/mxc/capture/adv7180.c ---- linux-4.1.13.orig/drivers/media/platform/mxc/capture/adv7180.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/media/platform/mxc/capture/adv7180.c 2015-11-30 17:56:13.600136395 +0100 -@@ -0,0 +1,1344 @@ -+/* -+ * Copyright 2005-2013 Freescale Semiconductor, Inc. All Rights Reserved. -+ */ -+ -+/* -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/*! -+ * @file adv7180.c -+ * -+ * @brief Analog Device ADV7180 video decoder functions -+ * -+ * @ingroup Camera -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "mxc_v4l2_capture.h" -+ -+#define ADV7180_VOLTAGE_ANALOG 1800000 -+#define ADV7180_VOLTAGE_DIGITAL_CORE 1800000 -+#define ADV7180_VOLTAGE_DIGITAL_IO 3300000 -+#define ADV7180_VOLTAGE_PLL 1800000 -+ -+static struct regulator *dvddio_regulator; -+static struct regulator *dvdd_regulator; -+static struct regulator *avdd_regulator; -+static struct regulator *pvdd_regulator; -+static int pwn_gpio; -+ -+static int adv7180_probe(struct i2c_client *adapter, -+ const struct i2c_device_id *id); -+static int adv7180_detach(struct i2c_client *client); -+ -+static const struct i2c_device_id adv7180_id[] = { -+ {"adv7180", 0}, -+ {}, -+}; -+ -+MODULE_DEVICE_TABLE(i2c, adv7180_id); -+ -+static struct i2c_driver adv7180_i2c_driver = { -+ .driver = { -+ .owner = THIS_MODULE, -+ .name = "adv7180", -+ }, -+ .probe = adv7180_probe, -+ .remove = adv7180_detach, -+ .id_table = adv7180_id, -+}; -+ -+/*! -+ * Maintains the information on the current state of the sensor. -+ */ -+struct sensor { -+ struct sensor_data sen; -+ v4l2_std_id std_id; -+} adv7180_data; -+ -+ -+/*! List of input video formats supported. The video formats is corresponding -+ * with v4l2 id in video_fmt_t -+ */ -+typedef enum { -+ ADV7180_NTSC = 0, /*!< Locked on (M) NTSC video signal. */ -+ ADV7180_PAL, /*!< (B, G, H, I, N)PAL video signal. */ -+ ADV7180_NOT_LOCKED, /*!< Not locked on a signal. */ -+} video_fmt_idx; -+ -+/*! Number of video standards supported (including 'not locked' signal). */ -+#define ADV7180_STD_MAX (ADV7180_PAL + 1) -+ -+/*! Video format structure. */ -+typedef struct { -+ int v4l2_id; /*!< Video for linux ID. */ -+ char name[16]; /*!< Name (e.g., "NTSC", "PAL", etc.) */ -+ u16 raw_width; /*!< Raw width. */ -+ u16 raw_height; /*!< Raw height. */ -+ u16 active_width; /*!< Active width. */ -+ u16 active_height; /*!< Active height. */ -+} video_fmt_t; -+ -+/*! Description of video formats supported. -+ * -+ * PAL: raw=720x625, active=720x576. -+ * NTSC: raw=720x525, active=720x480. -+ */ -+static video_fmt_t video_fmts[] = { -+ { /*! NTSC */ -+ .v4l2_id = V4L2_STD_NTSC, -+ .name = "NTSC", -+ .raw_width = 720, /* SENS_FRM_WIDTH */ -+ .raw_height = 525, /* SENS_FRM_HEIGHT */ -+ .active_width = 720, /* ACT_FRM_WIDTH plus 1 */ -+ .active_height = 480, /* ACT_FRM_WIDTH plus 1 */ -+ }, -+ { /*! (B, G, H, I, N) PAL */ -+ .v4l2_id = V4L2_STD_PAL, -+ .name = "PAL", -+ .raw_width = 720, -+ .raw_height = 625, -+ .active_width = 720, -+ .active_height = 576, -+ }, -+ { /*! Unlocked standard */ -+ .v4l2_id = V4L2_STD_ALL, -+ .name = "Autodetect", -+ .raw_width = 720, -+ .raw_height = 625, -+ .active_width = 720, -+ .active_height = 576, -+ }, -+}; -+ -+/*!* Standard index of ADV7180. */ -+static video_fmt_idx video_idx = ADV7180_PAL; -+ -+/*! @brief This mutex is used to provide mutual exclusion. -+ * -+ * Create a mutex that can be used to provide mutually exclusive -+ * read/write access to the globally accessible data structures -+ * and variables that were defined above. -+ */ -+static DEFINE_MUTEX(mutex); -+ -+#define IF_NAME "adv7180" -+#define ADV7180_INPUT_CTL 0x00 /* Input Control */ -+#define ADV7180_STATUS_1 0x10 /* Status #1 */ -+#define ADV7180_BRIGHTNESS 0x0a /* Brightness */ -+#define ADV7180_IDENT 0x11 /* IDENT */ -+#define ADV7180_VSYNC_FIELD_CTL_1 0x31 /* VSYNC Field Control #1 */ -+#define ADV7180_MANUAL_WIN_CTL 0x3d /* Manual Window Control */ -+#define ADV7180_SD_SATURATION_CB 0xe3 /* SD Saturation Cb */ -+#define ADV7180_SD_SATURATION_CR 0xe4 /* SD Saturation Cr */ -+#define ADV7180_PWR_MNG 0x0f /* Power Management */ -+ -+/* supported controls */ -+/* This hasn't been fully implemented yet. -+ * This is how it should work, though. */ -+static struct v4l2_queryctrl adv7180_qctrl[] = { -+ { -+ .id = V4L2_CID_BRIGHTNESS, -+ .type = V4L2_CTRL_TYPE_INTEGER, -+ .name = "Brightness", -+ .minimum = 0, /* check this value */ -+ .maximum = 255, /* check this value */ -+ .step = 1, /* check this value */ -+ .default_value = 127, /* check this value */ -+ .flags = 0, -+ }, { -+ .id = V4L2_CID_SATURATION, -+ .type = V4L2_CTRL_TYPE_INTEGER, -+ .name = "Saturation", -+ .minimum = 0, /* check this value */ -+ .maximum = 255, /* check this value */ -+ .step = 0x1, /* check this value */ -+ .default_value = 127, /* check this value */ -+ .flags = 0, -+ } -+}; -+ -+static inline void adv7180_power_down(int enable) -+{ -+ gpio_set_value_cansleep(pwn_gpio, !enable); -+ msleep(2); -+} -+ -+static int adv7180_regulator_enable(struct device *dev) -+{ -+ int ret = 0; -+ -+ dvddio_regulator = devm_regulator_get(dev, "DOVDD"); -+ -+ if (!IS_ERR(dvddio_regulator)) { -+ regulator_set_voltage(dvddio_regulator, -+ ADV7180_VOLTAGE_DIGITAL_IO, -+ ADV7180_VOLTAGE_DIGITAL_IO); -+ ret = regulator_enable(dvddio_regulator); -+ if (ret) { -+ dev_err(dev, "set io voltage failed\n"); -+ return ret; -+ } else { -+ dev_dbg(dev, "set io voltage ok\n"); -+ } -+ } else { -+ dev_warn(dev, "cannot get io voltage\n"); -+ } -+ -+ dvdd_regulator = devm_regulator_get(dev, "DVDD"); -+ if (!IS_ERR(dvdd_regulator)) { -+ regulator_set_voltage(dvdd_regulator, -+ ADV7180_VOLTAGE_DIGITAL_CORE, -+ ADV7180_VOLTAGE_DIGITAL_CORE); -+ ret = regulator_enable(dvdd_regulator); -+ if (ret) { -+ dev_err(dev, "set core voltage failed\n"); -+ return ret; -+ } else { -+ dev_dbg(dev, "set core voltage ok\n"); -+ } -+ } else { -+ dev_warn(dev, "cannot get core voltage\n"); -+ } -+ -+ avdd_regulator = devm_regulator_get(dev, "AVDD"); -+ if (!IS_ERR(avdd_regulator)) { -+ regulator_set_voltage(avdd_regulator, -+ ADV7180_VOLTAGE_ANALOG, -+ ADV7180_VOLTAGE_ANALOG); -+ ret = regulator_enable(avdd_regulator); -+ if (ret) { -+ dev_err(dev, "set analog voltage failed\n"); -+ return ret; -+ } else { -+ dev_dbg(dev, "set analog voltage ok\n"); -+ } -+ } else { -+ dev_warn(dev, "cannot get analog voltage\n"); -+ } -+ -+ pvdd_regulator = devm_regulator_get(dev, "PVDD"); -+ if (!IS_ERR(pvdd_regulator)) { -+ regulator_set_voltage(pvdd_regulator, -+ ADV7180_VOLTAGE_PLL, -+ ADV7180_VOLTAGE_PLL); -+ ret = regulator_enable(pvdd_regulator); -+ if (ret) { -+ dev_err(dev, "set pll voltage failed\n"); -+ return ret; -+ } else { -+ dev_dbg(dev, "set pll voltage ok\n"); -+ } -+ } else { -+ dev_warn(dev, "cannot get pll voltage\n"); -+ } -+ -+ return ret; -+} -+ -+ -+/*********************************************************************** -+ * I2C transfert. -+ ***********************************************************************/ -+ -+/*! Read one register from a ADV7180 i2c slave device. -+ * -+ * @param *reg register in the device we wish to access. -+ * -+ * @return 0 if success, an error code otherwise. -+ */ -+static inline int adv7180_read(u8 reg) -+{ -+ int val; -+ -+ val = i2c_smbus_read_byte_data(adv7180_data.sen.i2c_client, reg); -+ if (val < 0) { -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ "%s:read reg error: reg=%2x\n", __func__, reg); -+ return -1; -+ } -+ return val; -+} -+ -+/*! Write one register of a ADV7180 i2c slave device. -+ * -+ * @param *reg register in the device we wish to access. -+ * -+ * @return 0 if success, an error code otherwise. -+ */ -+static int adv7180_write_reg(u8 reg, u8 val) -+{ -+ s32 ret; -+ -+ ret = i2c_smbus_write_byte_data(adv7180_data.sen.i2c_client, reg, val); -+ if (ret < 0) { -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ "%s:write reg error:reg=%2x,val=%2x\n", __func__, -+ reg, val); -+ return -1; -+ } -+ return 0; -+} -+ -+/*********************************************************************** -+ * mxc_v4l2_capture interface. -+ ***********************************************************************/ -+ -+/*! -+ * Return attributes of current video standard. -+ * Since this device autodetects the current standard, this function also -+ * sets the values that need to be changed if the standard changes. -+ * There is no set std equivalent function. -+ * -+ * @return None. -+ */ -+static void adv7180_get_std(v4l2_std_id *std) -+{ -+ int tmp; -+ int idx; -+ -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, "In adv7180_get_std\n"); -+ -+ /* Read the AD_RESULT to get the detect output video standard */ -+ tmp = adv7180_read(ADV7180_STATUS_1) & 0x70; -+ -+ mutex_lock(&mutex); -+ if (tmp == 0x40) { -+ /* PAL */ -+ *std = V4L2_STD_PAL; -+ idx = ADV7180_PAL; -+ } else if (tmp == 0) { -+ /*NTSC*/ -+ *std = V4L2_STD_NTSC; -+ idx = ADV7180_NTSC; -+ } else { -+ *std = V4L2_STD_ALL; -+ idx = ADV7180_NOT_LOCKED; -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ "Got invalid video standard!\n"); -+ } -+ mutex_unlock(&mutex); -+ -+ /* This assumes autodetect which this device uses. */ -+ if (*std != adv7180_data.std_id) { -+ video_idx = idx; -+ adv7180_data.std_id = *std; -+ adv7180_data.sen.pix.width = video_fmts[video_idx].raw_width; -+ adv7180_data.sen.pix.height = video_fmts[video_idx].raw_height; -+ } -+} -+ -+/*********************************************************************** -+ * IOCTL Functions from v4l2_int_ioctl_desc. -+ ***********************************************************************/ -+ -+/*! -+ * ioctl_g_ifparm - V4L2 sensor interface handler for vidioc_int_g_ifparm_num -+ * s: pointer to standard V4L2 device structure -+ * p: pointer to standard V4L2 vidioc_int_g_ifparm_num ioctl structure -+ * -+ * Gets slave interface parameters. -+ * Calculates the required xclk value to support the requested -+ * clock parameters in p. This value is returned in the p -+ * parameter. -+ * -+ * vidioc_int_g_ifparm returns platform-specific information about the -+ * interface settings used by the sensor. -+ * -+ * Called on open. -+ */ -+static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p) -+{ -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, "adv7180:ioctl_g_ifparm\n"); -+ -+ if (s == NULL) { -+ pr_err(" ERROR!! no slave device set!\n"); -+ return -1; -+ } -+ -+ /* Initialize structure to 0s then set any non-0 values. */ -+ memset(p, 0, sizeof(*p)); -+ p->if_type = V4L2_IF_TYPE_BT656; /* This is the only possibility. */ -+ p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT; -+ p->u.bt656.nobt_hs_inv = 1; -+ p->u.bt656.bt_sync_correct = 1; -+ -+ /* ADV7180 has a dedicated clock so no clock settings needed. */ -+ -+ return 0; -+} -+ -+/*! -+ * Sets the camera power. -+ * -+ * s pointer to the camera device -+ * on if 1, power is to be turned on. 0 means power is to be turned off -+ * -+ * ioctl_s_power - V4L2 sensor interface handler for vidioc_int_s_power_num -+ * @s: pointer to standard V4L2 device structure -+ * @on: power state to which device is to be set -+ * -+ * Sets devices power state to requrested state, if possible. -+ * This is called on open, close, suspend and resume. -+ */ -+static int ioctl_s_power(struct v4l2_int_device *s, int on) -+{ -+ struct sensor *sensor = s->priv; -+ -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, "adv7180:ioctl_s_power\n"); -+ -+ if (on && !sensor->sen.on) { -+ if (adv7180_write_reg(ADV7180_PWR_MNG, 0x04) != 0) -+ return -EIO; -+ -+ /* -+ * FIXME:Additional 400ms to wait the chip to be stable? -+ * This is a workaround for preview scrolling issue. -+ */ -+ msleep(400); -+ } else if (!on && sensor->sen.on) { -+ if (adv7180_write_reg(ADV7180_PWR_MNG, 0x24) != 0) -+ return -EIO; -+ } -+ -+ sensor->sen.on = on; -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure -+ * -+ * Returns the sensor's video CAPTURE parameters. -+ */ -+static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) -+{ -+ struct sensor *sensor = s->priv; -+ struct v4l2_captureparm *cparm = &a->parm.capture; -+ -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, "In adv7180:ioctl_g_parm\n"); -+ -+ switch (a->type) { -+ /* These are all the possible cases. */ -+ case V4L2_BUF_TYPE_VIDEO_CAPTURE: -+ pr_debug(" type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n"); -+ memset(a, 0, sizeof(*a)); -+ a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; -+ cparm->capability = sensor->sen.streamcap.capability; -+ cparm->timeperframe = sensor->sen.streamcap.timeperframe; -+ cparm->capturemode = sensor->sen.streamcap.capturemode; -+ break; -+ -+ case V4L2_BUF_TYPE_VIDEO_OUTPUT: -+ case V4L2_BUF_TYPE_VIDEO_OVERLAY: -+ case V4L2_BUF_TYPE_VBI_CAPTURE: -+ case V4L2_BUF_TYPE_VBI_OUTPUT: -+ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: -+ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: -+ break; -+ -+ default: -+ pr_debug("ioctl_g_parm:type is unknown %d\n", a->type); -+ break; -+ } -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure -+ * -+ * Configures the sensor to use the input parameters, if possible. If -+ * not possible, reverts to the old parameters and returns the -+ * appropriate error code. -+ * -+ * This driver cannot change these settings. -+ */ -+static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) -+{ -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, "In adv7180:ioctl_s_parm\n"); -+ -+ switch (a->type) { -+ /* These are all the possible cases. */ -+ case V4L2_BUF_TYPE_VIDEO_CAPTURE: -+ case V4L2_BUF_TYPE_VIDEO_OUTPUT: -+ case V4L2_BUF_TYPE_VIDEO_OVERLAY: -+ case V4L2_BUF_TYPE_VBI_CAPTURE: -+ case V4L2_BUF_TYPE_VBI_OUTPUT: -+ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: -+ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: -+ break; -+ -+ default: -+ pr_debug(" type is unknown - %d\n", a->type); -+ break; -+ } -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap -+ * @s: pointer to standard V4L2 device structure -+ * @f: pointer to standard V4L2 v4l2_format structure -+ * -+ * Returns the sensor's current pixel format in the v4l2_format -+ * parameter. -+ */ -+static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) -+{ -+ struct sensor *sensor = s->priv; -+ -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, "adv7180:ioctl_g_fmt_cap\n"); -+ -+ switch (f->type) { -+ case V4L2_BUF_TYPE_VIDEO_CAPTURE: -+ pr_debug(" Returning size of %dx%d\n", -+ sensor->sen.pix.width, sensor->sen.pix.height); -+ f->fmt.pix = sensor->sen.pix; -+ break; -+ -+ case V4L2_BUF_TYPE_PRIVATE: { -+ v4l2_std_id std; -+ adv7180_get_std(&std); -+ f->fmt.pix.pixelformat = (u32)std; -+ } -+ break; -+ -+ default: -+ f->fmt.pix = sensor->sen.pix; -+ break; -+ } -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_queryctrl - V4L2 sensor interface handler for VIDIOC_QUERYCTRL ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @qc: standard V4L2 VIDIOC_QUERYCTRL ioctl structure -+ * -+ * If the requested control is supported, returns the control information -+ * from the video_control[] array. Otherwise, returns -EINVAL if the -+ * control is not supported. -+ */ -+static int ioctl_queryctrl(struct v4l2_int_device *s, -+ struct v4l2_queryctrl *qc) -+{ -+ int i; -+ -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, "adv7180:ioctl_queryctrl\n"); -+ -+ for (i = 0; i < ARRAY_SIZE(adv7180_qctrl); i++) -+ if (qc->id && qc->id == adv7180_qctrl[i].id) { -+ memcpy(qc, &(adv7180_qctrl[i]), -+ sizeof(*qc)); -+ return 0; -+ } -+ -+ return -EINVAL; -+} -+ -+/*! -+ * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure -+ * -+ * If the requested control is supported, returns the control's current -+ * value from the video_control[] array. Otherwise, returns -EINVAL -+ * if the control is not supported. -+ */ -+static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) -+{ -+ int ret = 0; -+ int sat = 0; -+ -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, "In adv7180:ioctl_g_ctrl\n"); -+ -+ switch (vc->id) { -+ case V4L2_CID_BRIGHTNESS: -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ " V4L2_CID_BRIGHTNESS\n"); -+ adv7180_data.sen.brightness = adv7180_read(ADV7180_BRIGHTNESS); -+ vc->value = adv7180_data.sen.brightness; -+ break; -+ case V4L2_CID_CONTRAST: -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ " V4L2_CID_CONTRAST\n"); -+ vc->value = adv7180_data.sen.contrast; -+ break; -+ case V4L2_CID_SATURATION: -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ " V4L2_CID_SATURATION\n"); -+ sat = adv7180_read(ADV7180_SD_SATURATION_CB); -+ adv7180_data.sen.saturation = sat; -+ vc->value = adv7180_data.sen.saturation; -+ break; -+ case V4L2_CID_HUE: -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ " V4L2_CID_HUE\n"); -+ vc->value = adv7180_data.sen.hue; -+ break; -+ case V4L2_CID_AUTO_WHITE_BALANCE: -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ " V4L2_CID_AUTO_WHITE_BALANCE\n"); -+ break; -+ case V4L2_CID_DO_WHITE_BALANCE: -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ " V4L2_CID_DO_WHITE_BALANCE\n"); -+ break; -+ case V4L2_CID_RED_BALANCE: -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ " V4L2_CID_RED_BALANCE\n"); -+ vc->value = adv7180_data.sen.red; -+ break; -+ case V4L2_CID_BLUE_BALANCE: -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ " V4L2_CID_BLUE_BALANCE\n"); -+ vc->value = adv7180_data.sen.blue; -+ break; -+ case V4L2_CID_GAMMA: -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ " V4L2_CID_GAMMA\n"); -+ break; -+ case V4L2_CID_EXPOSURE: -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ " V4L2_CID_EXPOSURE\n"); -+ vc->value = adv7180_data.sen.ae_mode; -+ break; -+ case V4L2_CID_AUTOGAIN: -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ " V4L2_CID_AUTOGAIN\n"); -+ break; -+ case V4L2_CID_GAIN: -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ " V4L2_CID_GAIN\n"); -+ break; -+ case V4L2_CID_HFLIP: -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ " V4L2_CID_HFLIP\n"); -+ break; -+ case V4L2_CID_VFLIP: -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ " V4L2_CID_VFLIP\n"); -+ break; -+ default: -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ " Default case\n"); -+ vc->value = 0; -+ ret = -EPERM; -+ break; -+ } -+ -+ return ret; -+} -+ -+/*! -+ * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure -+ * -+ * If the requested control is supported, sets the control's current -+ * value in HW (and updates the video_control[] array). Otherwise, -+ * returns -EINVAL if the control is not supported. -+ */ -+static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) -+{ -+ int retval = 0; -+ u8 tmp; -+ -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, "In adv7180:ioctl_s_ctrl\n"); -+ -+ switch (vc->id) { -+ case V4L2_CID_BRIGHTNESS: -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ " V4L2_CID_BRIGHTNESS\n"); -+ tmp = vc->value; -+ adv7180_write_reg(ADV7180_BRIGHTNESS, tmp); -+ adv7180_data.sen.brightness = vc->value; -+ break; -+ case V4L2_CID_CONTRAST: -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ " V4L2_CID_CONTRAST\n"); -+ break; -+ case V4L2_CID_SATURATION: -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ " V4L2_CID_SATURATION\n"); -+ tmp = vc->value; -+ adv7180_write_reg(ADV7180_SD_SATURATION_CB, tmp); -+ adv7180_write_reg(ADV7180_SD_SATURATION_CR, tmp); -+ adv7180_data.sen.saturation = vc->value; -+ break; -+ case V4L2_CID_HUE: -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ " V4L2_CID_HUE\n"); -+ break; -+ case V4L2_CID_AUTO_WHITE_BALANCE: -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ " V4L2_CID_AUTO_WHITE_BALANCE\n"); -+ break; -+ case V4L2_CID_DO_WHITE_BALANCE: -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ " V4L2_CID_DO_WHITE_BALANCE\n"); -+ break; -+ case V4L2_CID_RED_BALANCE: -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ " V4L2_CID_RED_BALANCE\n"); -+ break; -+ case V4L2_CID_BLUE_BALANCE: -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ " V4L2_CID_BLUE_BALANCE\n"); -+ break; -+ case V4L2_CID_GAMMA: -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ " V4L2_CID_GAMMA\n"); -+ break; -+ case V4L2_CID_EXPOSURE: -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ " V4L2_CID_EXPOSURE\n"); -+ break; -+ case V4L2_CID_AUTOGAIN: -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ " V4L2_CID_AUTOGAIN\n"); -+ break; -+ case V4L2_CID_GAIN: -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ " V4L2_CID_GAIN\n"); -+ break; -+ case V4L2_CID_HFLIP: -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ " V4L2_CID_HFLIP\n"); -+ break; -+ case V4L2_CID_VFLIP: -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ " V4L2_CID_VFLIP\n"); -+ break; -+ default: -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ " Default case\n"); -+ retval = -EPERM; -+ break; -+ } -+ -+ return retval; -+} -+ -+/*! -+ * ioctl_enum_framesizes - V4L2 sensor interface handler for -+ * VIDIOC_ENUM_FRAMESIZES ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure -+ * -+ * Return 0 if successful, otherwise -EINVAL. -+ */ -+static int ioctl_enum_framesizes(struct v4l2_int_device *s, -+ struct v4l2_frmsizeenum *fsize) -+{ -+ if (fsize->index >= 1) -+ return -EINVAL; -+ -+ fsize->discrete.width = video_fmts[video_idx].active_width; -+ fsize->discrete.height = video_fmts[video_idx].active_height; -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_g_chip_ident - V4L2 sensor interface handler for -+ * VIDIOC_DBG_G_CHIP_IDENT ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @id: pointer to int -+ * -+ * Return 0. -+ */ -+static int ioctl_g_chip_ident(struct v4l2_int_device *s, int *id) -+{ -+ ((struct v4l2_dbg_chip_ident *)id)->match.type = -+ V4L2_CHIP_MATCH_I2C_DRIVER; -+ strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name, -+ "adv7180_decoder"); -+ ((struct v4l2_dbg_chip_ident *)id)->ident = V4L2_IDENT_ADV7180; -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT -+ * @s: pointer to standard V4L2 device structure -+ */ -+static int ioctl_init(struct v4l2_int_device *s) -+{ -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, "In adv7180:ioctl_init\n"); -+ return 0; -+} -+ -+/*! -+ * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num -+ * @s: pointer to standard V4L2 device structure -+ * -+ * Initialise the device when slave attaches to the master. -+ */ -+static int ioctl_dev_init(struct v4l2_int_device *s) -+{ -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, "adv7180:ioctl_dev_init\n"); -+ return 0; -+} -+ -+/*! -+ * This structure defines all the ioctls for this module. -+ */ -+static struct v4l2_int_ioctl_desc adv7180_ioctl_desc[] = { -+ -+ {vidioc_int_dev_init_num, (v4l2_int_ioctl_func*)ioctl_dev_init}, -+ -+ /*! -+ * Delinitialise the dev. at slave detach. -+ * The complement of ioctl_dev_init. -+ */ -+/* {vidioc_int_dev_exit_num, (v4l2_int_ioctl_func *)ioctl_dev_exit}, */ -+ -+ {vidioc_int_s_power_num, (v4l2_int_ioctl_func*)ioctl_s_power}, -+ {vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func*)ioctl_g_ifparm}, -+/* {vidioc_int_g_needs_reset_num, -+ (v4l2_int_ioctl_func *)ioctl_g_needs_reset}, */ -+/* {vidioc_int_reset_num, (v4l2_int_ioctl_func *)ioctl_reset}, */ -+ {vidioc_int_init_num, (v4l2_int_ioctl_func*)ioctl_init}, -+ -+ /*! -+ * VIDIOC_ENUM_FMT ioctl for the CAPTURE buffer type. -+ */ -+/* {vidioc_int_enum_fmt_cap_num, -+ (v4l2_int_ioctl_func *)ioctl_enum_fmt_cap}, */ -+ -+ /*! -+ * VIDIOC_TRY_FMT ioctl for the CAPTURE buffer type. -+ * This ioctl is used to negotiate the image capture size and -+ * pixel format without actually making it take effect. -+ */ -+/* {vidioc_int_try_fmt_cap_num, -+ (v4l2_int_ioctl_func *)ioctl_try_fmt_cap}, */ -+ -+ {vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func*)ioctl_g_fmt_cap}, -+ -+ /*! -+ * If the requested format is supported, configures the HW to use that -+ * format, returns error code if format not supported or HW can't be -+ * correctly configured. -+ */ -+/* {vidioc_int_s_fmt_cap_num, (v4l2_int_ioctl_func *)ioctl_s_fmt_cap}, */ -+ -+ {vidioc_int_g_parm_num, (v4l2_int_ioctl_func*)ioctl_g_parm}, -+ {vidioc_int_s_parm_num, (v4l2_int_ioctl_func*)ioctl_s_parm}, -+ {vidioc_int_queryctrl_num, (v4l2_int_ioctl_func*)ioctl_queryctrl}, -+ {vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func*)ioctl_g_ctrl}, -+ {vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func*)ioctl_s_ctrl}, -+ {vidioc_int_enum_framesizes_num, -+ (v4l2_int_ioctl_func *) ioctl_enum_framesizes}, -+ {vidioc_int_g_chip_ident_num, -+ (v4l2_int_ioctl_func *)ioctl_g_chip_ident}, -+}; -+ -+static struct v4l2_int_slave adv7180_slave = { -+ .ioctls = adv7180_ioctl_desc, -+ .num_ioctls = ARRAY_SIZE(adv7180_ioctl_desc), -+}; -+ -+static struct v4l2_int_device adv7180_int_device = { -+ .module = THIS_MODULE, -+ .name = "adv7180", -+ .type = v4l2_int_type_slave, -+ .u = { -+ .slave = &adv7180_slave, -+ }, -+}; -+ -+ -+/*********************************************************************** -+ * I2C client and driver. -+ ***********************************************************************/ -+ -+/*! ADV7180 Reset function. -+ * -+ * @return None. -+ */ -+static void adv7180_hard_reset(bool cvbs) -+{ -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ "In adv7180:adv7180_hard_reset\n"); -+ -+ if (cvbs) { -+ /* Set CVBS input on AIN1 */ -+ adv7180_write_reg(ADV7180_INPUT_CTL, 0x00); -+ } else { -+ /* -+ * Set YPbPr input on AIN1,4,5 and normal -+ * operations(autodection of all stds). -+ */ -+ adv7180_write_reg(ADV7180_INPUT_CTL, 0x09); -+ } -+ -+ /* Datasheet recommends */ -+ adv7180_write_reg(0x01, 0xc8); -+ adv7180_write_reg(0x02, 0x04); -+ adv7180_write_reg(0x03, 0x00); -+ adv7180_write_reg(0x04, 0x45); -+ adv7180_write_reg(0x05, 0x00); -+ adv7180_write_reg(0x06, 0x02); -+ adv7180_write_reg(0x07, 0x7F); -+ adv7180_write_reg(0x08, 0x80); -+ adv7180_write_reg(0x0A, 0x00); -+ adv7180_write_reg(0x0B, 0x00); -+ adv7180_write_reg(0x0C, 0x36); -+ adv7180_write_reg(0x0D, 0x7C); -+ adv7180_write_reg(0x0E, 0x00); -+ adv7180_write_reg(0x0F, 0x00); -+ adv7180_write_reg(0x13, 0x00); -+ adv7180_write_reg(0x14, 0x12); -+ adv7180_write_reg(0x15, 0x00); -+ adv7180_write_reg(0x16, 0x00); -+ adv7180_write_reg(0x17, 0x01); -+ adv7180_write_reg(0x18, 0x93); -+ adv7180_write_reg(0xF1, 0x19); -+ adv7180_write_reg(0x1A, 0x00); -+ adv7180_write_reg(0x1B, 0x00); -+ adv7180_write_reg(0x1C, 0x00); -+ adv7180_write_reg(0x1D, 0x40); -+ adv7180_write_reg(0x1E, 0x00); -+ adv7180_write_reg(0x1F, 0x00); -+ adv7180_write_reg(0x20, 0x00); -+ adv7180_write_reg(0x21, 0x00); -+ adv7180_write_reg(0x22, 0x00); -+ adv7180_write_reg(0x23, 0xC0); -+ adv7180_write_reg(0x24, 0x00); -+ adv7180_write_reg(0x25, 0x00); -+ adv7180_write_reg(0x26, 0x00); -+ adv7180_write_reg(0x27, 0x58); -+ adv7180_write_reg(0x28, 0x00); -+ adv7180_write_reg(0x29, 0x00); -+ adv7180_write_reg(0x2A, 0x00); -+ adv7180_write_reg(0x2B, 0xE1); -+ adv7180_write_reg(0x2C, 0xAE); -+ adv7180_write_reg(0x2D, 0xF4); -+ adv7180_write_reg(0x2E, 0x00); -+ adv7180_write_reg(0x2F, 0xF0); -+ adv7180_write_reg(0x30, 0x00); -+ adv7180_write_reg(0x31, 0x12); -+ adv7180_write_reg(0x32, 0x41); -+ adv7180_write_reg(0x33, 0x84); -+ adv7180_write_reg(0x34, 0x00); -+ adv7180_write_reg(0x35, 0x02); -+ adv7180_write_reg(0x36, 0x00); -+ adv7180_write_reg(0x37, 0x01); -+ adv7180_write_reg(0x38, 0x80); -+ adv7180_write_reg(0x39, 0xC0); -+ adv7180_write_reg(0x3A, 0x10); -+ adv7180_write_reg(0x3B, 0x05); -+ adv7180_write_reg(0x3C, 0x58); -+ adv7180_write_reg(0x3D, 0xB2); -+ adv7180_write_reg(0x3E, 0x64); -+ adv7180_write_reg(0x3F, 0xE4); -+ adv7180_write_reg(0x40, 0x90); -+ adv7180_write_reg(0x41, 0x01); -+ adv7180_write_reg(0x42, 0x7E); -+ adv7180_write_reg(0x43, 0xA4); -+ adv7180_write_reg(0x44, 0xFF); -+ adv7180_write_reg(0x45, 0xB6); -+ adv7180_write_reg(0x46, 0x12); -+ adv7180_write_reg(0x48, 0x00); -+ adv7180_write_reg(0x49, 0x00); -+ adv7180_write_reg(0x4A, 0x00); -+ adv7180_write_reg(0x4B, 0x00); -+ adv7180_write_reg(0x4C, 0x00); -+ adv7180_write_reg(0x4D, 0xEF); -+ adv7180_write_reg(0x4E, 0x08); -+ adv7180_write_reg(0x4F, 0x08); -+ adv7180_write_reg(0x50, 0x08); -+ adv7180_write_reg(0x51, 0x24); -+ adv7180_write_reg(0x52, 0x0B); -+ adv7180_write_reg(0x53, 0x4E); -+ adv7180_write_reg(0x54, 0x80); -+ adv7180_write_reg(0x55, 0x00); -+ adv7180_write_reg(0x56, 0x10); -+ adv7180_write_reg(0x57, 0x00); -+ adv7180_write_reg(0x58, 0x00); -+ adv7180_write_reg(0x59, 0x00); -+ adv7180_write_reg(0x5A, 0x00); -+ adv7180_write_reg(0x5B, 0x00); -+ adv7180_write_reg(0x5C, 0x00); -+ adv7180_write_reg(0x5D, 0x00); -+ adv7180_write_reg(0x5E, 0x00); -+ adv7180_write_reg(0x5F, 0x00); -+ adv7180_write_reg(0x60, 0x00); -+ adv7180_write_reg(0x61, 0x00); -+ adv7180_write_reg(0x62, 0x20); -+ adv7180_write_reg(0x63, 0x00); -+ adv7180_write_reg(0x64, 0x00); -+ adv7180_write_reg(0x65, 0x00); -+ adv7180_write_reg(0x66, 0x00); -+ adv7180_write_reg(0x67, 0x03); -+ adv7180_write_reg(0x68, 0x01); -+ adv7180_write_reg(0x69, 0x00); -+ adv7180_write_reg(0x6A, 0x00); -+ adv7180_write_reg(0x6B, 0xC0); -+ adv7180_write_reg(0x6C, 0x00); -+ adv7180_write_reg(0x6D, 0x00); -+ adv7180_write_reg(0x6E, 0x00); -+ adv7180_write_reg(0x6F, 0x00); -+ adv7180_write_reg(0x70, 0x00); -+ adv7180_write_reg(0x71, 0x00); -+ adv7180_write_reg(0x72, 0x00); -+ adv7180_write_reg(0x73, 0x10); -+ adv7180_write_reg(0x74, 0x04); -+ adv7180_write_reg(0x75, 0x01); -+ adv7180_write_reg(0x76, 0x00); -+ adv7180_write_reg(0x77, 0x3F); -+ adv7180_write_reg(0x78, 0xFF); -+ adv7180_write_reg(0x79, 0xFF); -+ adv7180_write_reg(0x7A, 0xFF); -+ adv7180_write_reg(0x7B, 0x1E); -+ adv7180_write_reg(0x7C, 0xC0); -+ adv7180_write_reg(0x7D, 0x00); -+ adv7180_write_reg(0x7E, 0x00); -+ adv7180_write_reg(0x7F, 0x00); -+ adv7180_write_reg(0x80, 0x00); -+ adv7180_write_reg(0x81, 0xC0); -+ adv7180_write_reg(0x82, 0x04); -+ adv7180_write_reg(0x83, 0x00); -+ adv7180_write_reg(0x84, 0x0C); -+ adv7180_write_reg(0x85, 0x02); -+ adv7180_write_reg(0x86, 0x03); -+ adv7180_write_reg(0x87, 0x63); -+ adv7180_write_reg(0x88, 0x5A); -+ adv7180_write_reg(0x89, 0x08); -+ adv7180_write_reg(0x8A, 0x10); -+ adv7180_write_reg(0x8B, 0x00); -+ adv7180_write_reg(0x8C, 0x40); -+ adv7180_write_reg(0x8D, 0x00); -+ adv7180_write_reg(0x8E, 0x40); -+ adv7180_write_reg(0x8F, 0x00); -+ adv7180_write_reg(0x90, 0x00); -+ adv7180_write_reg(0x91, 0x50); -+ adv7180_write_reg(0x92, 0x00); -+ adv7180_write_reg(0x93, 0x00); -+ adv7180_write_reg(0x94, 0x00); -+ adv7180_write_reg(0x95, 0x00); -+ adv7180_write_reg(0x96, 0x00); -+ adv7180_write_reg(0x97, 0xF0); -+ adv7180_write_reg(0x98, 0x00); -+ adv7180_write_reg(0x99, 0x00); -+ adv7180_write_reg(0x9A, 0x00); -+ adv7180_write_reg(0x9B, 0x00); -+ adv7180_write_reg(0x9C, 0x00); -+ adv7180_write_reg(0x9D, 0x00); -+ adv7180_write_reg(0x9E, 0x00); -+ adv7180_write_reg(0x9F, 0x00); -+ adv7180_write_reg(0xA0, 0x00); -+ adv7180_write_reg(0xA1, 0x00); -+ adv7180_write_reg(0xA2, 0x00); -+ adv7180_write_reg(0xA3, 0x00); -+ adv7180_write_reg(0xA4, 0x00); -+ adv7180_write_reg(0xA5, 0x00); -+ adv7180_write_reg(0xA6, 0x00); -+ adv7180_write_reg(0xA7, 0x00); -+ adv7180_write_reg(0xA8, 0x00); -+ adv7180_write_reg(0xA9, 0x00); -+ adv7180_write_reg(0xAA, 0x00); -+ adv7180_write_reg(0xAB, 0x00); -+ adv7180_write_reg(0xAC, 0x00); -+ adv7180_write_reg(0xAD, 0x00); -+ adv7180_write_reg(0xAE, 0x60); -+ adv7180_write_reg(0xAF, 0x00); -+ adv7180_write_reg(0xB0, 0x00); -+ adv7180_write_reg(0xB1, 0x60); -+ adv7180_write_reg(0xB2, 0x1C); -+ adv7180_write_reg(0xB3, 0x54); -+ adv7180_write_reg(0xB4, 0x00); -+ adv7180_write_reg(0xB5, 0x00); -+ adv7180_write_reg(0xB6, 0x00); -+ adv7180_write_reg(0xB7, 0x13); -+ adv7180_write_reg(0xB8, 0x03); -+ adv7180_write_reg(0xB9, 0x33); -+ adv7180_write_reg(0xBF, 0x02); -+ adv7180_write_reg(0xC0, 0x00); -+ adv7180_write_reg(0xC1, 0x00); -+ adv7180_write_reg(0xC2, 0x00); -+ adv7180_write_reg(0xC3, 0x00); -+ adv7180_write_reg(0xC4, 0x00); -+ adv7180_write_reg(0xC5, 0x81); -+ adv7180_write_reg(0xC6, 0x00); -+ adv7180_write_reg(0xC7, 0x00); -+ adv7180_write_reg(0xC8, 0x00); -+ adv7180_write_reg(0xC9, 0x04); -+ adv7180_write_reg(0xCC, 0x69); -+ adv7180_write_reg(0xCD, 0x00); -+ adv7180_write_reg(0xCE, 0x01); -+ adv7180_write_reg(0xCF, 0xB4); -+ adv7180_write_reg(0xD0, 0x00); -+ adv7180_write_reg(0xD1, 0x10); -+ adv7180_write_reg(0xD2, 0xFF); -+ adv7180_write_reg(0xD3, 0xFF); -+ adv7180_write_reg(0xD4, 0x7F); -+ adv7180_write_reg(0xD5, 0x7F); -+ adv7180_write_reg(0xD6, 0x3E); -+ adv7180_write_reg(0xD7, 0x08); -+ adv7180_write_reg(0xD8, 0x3C); -+ adv7180_write_reg(0xD9, 0x08); -+ adv7180_write_reg(0xDA, 0x3C); -+ adv7180_write_reg(0xDB, 0x9B); -+ adv7180_write_reg(0xDC, 0xAC); -+ adv7180_write_reg(0xDD, 0x4C); -+ adv7180_write_reg(0xDE, 0x00); -+ adv7180_write_reg(0xDF, 0x00); -+ adv7180_write_reg(0xE0, 0x14); -+ adv7180_write_reg(0xE1, 0x80); -+ adv7180_write_reg(0xE2, 0x80); -+ adv7180_write_reg(0xE3, 0x80); -+ adv7180_write_reg(0xE4, 0x80); -+ adv7180_write_reg(0xE5, 0x25); -+ adv7180_write_reg(0xE6, 0x44); -+ adv7180_write_reg(0xE7, 0x63); -+ adv7180_write_reg(0xE8, 0x65); -+ adv7180_write_reg(0xE9, 0x14); -+ adv7180_write_reg(0xEA, 0x63); -+ adv7180_write_reg(0xEB, 0x55); -+ adv7180_write_reg(0xEC, 0x55); -+ adv7180_write_reg(0xEE, 0x00); -+ adv7180_write_reg(0xEF, 0x4A); -+ adv7180_write_reg(0xF0, 0x44); -+ adv7180_write_reg(0xF1, 0x0C); -+ adv7180_write_reg(0xF2, 0x32); -+ adv7180_write_reg(0xF3, 0x00); -+ adv7180_write_reg(0xF4, 0x3F); -+ adv7180_write_reg(0xF5, 0xE0); -+ adv7180_write_reg(0xF6, 0x69); -+ adv7180_write_reg(0xF7, 0x10); -+ adv7180_write_reg(0xF8, 0x00); -+ adv7180_write_reg(0xF9, 0x03); -+ adv7180_write_reg(0xFA, 0xFA); -+ adv7180_write_reg(0xFB, 0x40); -+} -+ -+/*! ADV7180 I2C attach function. -+ * -+ * @param *adapter struct i2c_adapter *. -+ * -+ * @return Error code indicating success or failure. -+ */ -+ -+/*! -+ * ADV7180 I2C probe function. -+ * Function set in i2c_driver struct. -+ * Called by insmod. -+ * -+ * @param *adapter I2C adapter descriptor. -+ * -+ * @return Error code indicating success or failure. -+ */ -+static int adv7180_probe(struct i2c_client *client, -+ const struct i2c_device_id *id) -+{ -+ int rev_id; -+ int ret = 0; -+ u32 cvbs = true; -+ struct pinctrl *pinctrl; -+ struct device *dev = &client->dev; -+ -+ printk(KERN_ERR"DBG sensor data is at %p\n", &adv7180_data); -+ -+ /* ov5640 pinctrl */ -+ pinctrl = devm_pinctrl_get_select_default(dev); -+ if (IS_ERR(pinctrl)) { -+ dev_err(dev, "setup pinctrl failed\n"); -+ return PTR_ERR(pinctrl); -+ } -+ -+ /* request power down pin */ -+ pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0); -+ if (!gpio_is_valid(pwn_gpio)) { -+ dev_err(dev, "no sensor pwdn pin available\n"); -+ return -ENODEV; -+ } -+ ret = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH, -+ "adv7180_pwdn"); -+ if (ret < 0) { -+ dev_err(dev, "no power pin available!\n"); -+ return ret; -+ } -+ -+ adv7180_regulator_enable(dev); -+ -+ adv7180_power_down(0); -+ -+ msleep(1); -+ -+ /* Set initial values for the sensor struct. */ -+ memset(&adv7180_data, 0, sizeof(adv7180_data)); -+ adv7180_data.sen.i2c_client = client; -+ adv7180_data.sen.streamcap.timeperframe.denominator = 30; -+ adv7180_data.sen.streamcap.timeperframe.numerator = 1; -+ adv7180_data.std_id = V4L2_STD_ALL; -+ video_idx = ADV7180_NOT_LOCKED; -+ adv7180_data.sen.pix.width = video_fmts[video_idx].raw_width; -+ adv7180_data.sen.pix.height = video_fmts[video_idx].raw_height; -+ adv7180_data.sen.pix.pixelformat = V4L2_PIX_FMT_UYVY; /* YUV422 */ -+ adv7180_data.sen.pix.priv = 1; /* 1 is used to indicate TV in */ -+ adv7180_data.sen.on = true; -+ -+ adv7180_data.sen.sensor_clk = devm_clk_get(dev, "csi_mclk"); -+ if (IS_ERR(adv7180_data.sen.sensor_clk)) { -+ dev_err(dev, "get mclk failed\n"); -+ return PTR_ERR(adv7180_data.sen.sensor_clk); -+ } -+ -+ ret = of_property_read_u32(dev->of_node, "mclk", -+ &adv7180_data.sen.mclk); -+ if (ret) { -+ dev_err(dev, "mclk frequency is invalid\n"); -+ return ret; -+ } -+ -+ ret = of_property_read_u32( -+ dev->of_node, "mclk_source", -+ (u32 *) &(adv7180_data.sen.mclk_source)); -+ if (ret) { -+ dev_err(dev, "mclk_source invalid\n"); -+ return ret; -+ } -+ -+ ret = of_property_read_u32(dev->of_node, "csi_id", -+ &(adv7180_data.sen.csi)); -+ if (ret) { -+ dev_err(dev, "csi_id invalid\n"); -+ return ret; -+ } -+ -+ clk_prepare_enable(adv7180_data.sen.sensor_clk); -+ -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ "%s:adv7180 probe i2c address is 0x%02X\n", -+ __func__, adv7180_data.sen.i2c_client->addr); -+ -+ /*! Read the revision ID of the tvin chip */ -+ rev_id = adv7180_read(ADV7180_IDENT); -+ dev_dbg(dev, -+ "%s:Analog Device adv7%2X0 detected!\n", __func__, -+ rev_id); -+ -+ ret = of_property_read_u32(dev->of_node, "cvbs", &(cvbs)); -+ if (ret) { -+ dev_err(dev, "cvbs setting is not found\n"); -+ cvbs = true; -+ } -+ -+ /*! ADV7180 initialization. */ -+ adv7180_hard_reset(cvbs); -+ -+ pr_debug(" type is %d (expect %d)\n", -+ adv7180_int_device.type, v4l2_int_type_slave); -+ pr_debug(" num ioctls is %d\n", -+ adv7180_int_device.u.slave->num_ioctls); -+ -+ /* This function attaches this structure to the /dev/video0 device. -+ * The pointer in priv points to the adv7180_data structure here.*/ -+ adv7180_int_device.priv = &adv7180_data; -+ ret = v4l2_int_device_register(&adv7180_int_device); -+ -+ clk_disable_unprepare(adv7180_data.sen.sensor_clk); -+ -+ return ret; -+} -+ -+/*! -+ * ADV7180 I2C detach function. -+ * Called on rmmod. -+ * -+ * @param *client struct i2c_client*. -+ * -+ * @return Error code indicating success or failure. -+ */ -+static int adv7180_detach(struct i2c_client *client) -+{ -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, -+ "%s:Removing %s video decoder @ 0x%02X from adapter %s\n", -+ __func__, IF_NAME, client->addr << 1, client->adapter->name); -+ -+ /* Power down via i2c */ -+ adv7180_write_reg(ADV7180_PWR_MNG, 0x24); -+ -+ if (dvddio_regulator) -+ regulator_disable(dvddio_regulator); -+ -+ if (dvdd_regulator) -+ regulator_disable(dvdd_regulator); -+ -+ if (avdd_regulator) -+ regulator_disable(avdd_regulator); -+ -+ if (pvdd_regulator) -+ regulator_disable(pvdd_regulator); -+ -+ v4l2_int_device_unregister(&adv7180_int_device); -+ -+ return 0; -+} -+ -+/*! -+ * ADV7180 init function. -+ * Called on insmod. -+ * -+ * @return Error code indicating success or failure. -+ */ -+static __init int adv7180_init(void) -+{ -+ u8 err = 0; -+ -+ pr_debug("In adv7180_init\n"); -+ -+ /* Tells the i2c driver what functions to call for this driver. */ -+ err = i2c_add_driver(&adv7180_i2c_driver); -+ if (err != 0) -+ pr_err("%s:driver registration failed, error=%d\n", -+ __func__, err); -+ -+ return err; -+} -+ -+/*! -+ * ADV7180 cleanup function. -+ * Called on rmmod. -+ * -+ * @return Error code indicating success or failure. -+ */ -+static void __exit adv7180_clean(void) -+{ -+ dev_dbg(&adv7180_data.sen.i2c_client->dev, "In adv7180_clean\n"); -+ i2c_del_driver(&adv7180_i2c_driver); -+} -+ -+module_init(adv7180_init); -+module_exit(adv7180_clean); -+ -+MODULE_AUTHOR("Freescale Semiconductor"); -+MODULE_DESCRIPTION("Anolog Device ADV7180 video decoder driver"); -+MODULE_LICENSE("GPL"); -diff -Nur linux-4.1.13.orig/drivers/media/platform/mxc/capture/csi_v4l2_capture.c linux-4.1.13/drivers/media/platform/mxc/capture/csi_v4l2_capture.c ---- linux-4.1.13.orig/drivers/media/platform/mxc/capture/csi_v4l2_capture.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/media/platform/mxc/capture/csi_v4l2_capture.c 2015-11-30 17:56:13.600136395 +0100 -@@ -0,0 +1,2047 @@ -+/* -+ * Copyright 2009-2013 Freescale Semiconductor, Inc. All Rights Reserved. -+ */ -+ -+/* -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/*! -+ * @file drivers/media/video/mxc/capture/csi_v4l2_capture.c -+ * This file is derived from mxc_v4l2_capture.c -+ * -+ * @brief Video For Linux 2 capture driver -+ * -+ * @ingroup MXC_V4L2_CAPTURE -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "mxc_v4l2_capture.h" -+#include "fsl_csi.h" -+ -+static int video_nr = -1; -+static cam_data *g_cam; -+static int req_buf_number; -+ -+static int csi_v4l2_master_attach(struct v4l2_int_device *slave); -+static void csi_v4l2_master_detach(struct v4l2_int_device *slave); -+static u8 camera_power(cam_data *cam, bool cameraOn); -+struct v4l2_crop crop_current; -+struct v4l2_window win_current; -+ -+/*! Information about this driver. */ -+static struct v4l2_int_master csi_v4l2_master = { -+ .attach = csi_v4l2_master_attach, -+ .detach = csi_v4l2_master_detach, -+}; -+ -+static struct v4l2_int_device csi_v4l2_int_device = { -+ .module = THIS_MODULE, -+ .name = "csi_v4l2_cap", -+ .type = v4l2_int_type_master, -+ .u = { -+ .master = &csi_v4l2_master, -+ }, -+}; -+ -+static struct v4l2_queryctrl pxp_controls[] = { -+ { -+ .id = V4L2_CID_HFLIP, -+ .type = V4L2_CTRL_TYPE_BOOLEAN, -+ .name = "Horizontal Flip", -+ .minimum = 0, -+ .maximum = 1, -+ .step = 1, -+ .default_value = 0, -+ .flags = 0, -+ }, { -+ .id = V4L2_CID_VFLIP, -+ .type = V4L2_CTRL_TYPE_BOOLEAN, -+ .name = "Vertical Flip", -+ .minimum = 0, -+ .maximum = 1, -+ .step = 1, -+ .default_value = 0, -+ .flags = 0, -+ }, { -+ .id = V4L2_CID_PRIVATE_BASE, -+ .type = V4L2_CTRL_TYPE_INTEGER, -+ .name = "Rotation", -+ .minimum = 0, -+ .maximum = 270, -+ .step = 90, -+ .default_value = 0, -+ .flags = 0, -+ }, -+}; -+ -+/* Callback function triggered after PxP receives an EOF interrupt */ -+static void pxp_dma_done(void *arg) -+{ -+ struct pxp_tx_desc *tx_desc = to_tx_desc(arg); -+ struct dma_chan *chan = tx_desc->txd.chan; -+ struct pxp_channel *pxp_chan = to_pxp_channel(chan); -+ cam_data *cam = pxp_chan->client; -+ -+ /* This call will signal wait_for_completion_timeout() */ -+ complete(&cam->pxp_tx_cmpl); -+} -+ -+static bool chan_filter(struct dma_chan *chan, void *arg) -+{ -+ if (imx_dma_is_pxp(chan)) -+ return true; -+ else -+ return false; -+} -+ -+/* Function to request PXP DMA channel */ -+static int pxp_chan_init(cam_data *cam) -+{ -+ dma_cap_mask_t mask; -+ struct dma_chan *chan; -+ -+ /* Request a free channel */ -+ dma_cap_zero(mask); -+ dma_cap_set(DMA_SLAVE, mask); -+ dma_cap_set(DMA_PRIVATE, mask); -+ chan = dma_request_channel(mask, chan_filter, NULL); -+ if (!chan) { -+ pr_err("Unsuccessfully request channel!\n"); -+ return -EBUSY; -+ } -+ -+ cam->pxp_chan = to_pxp_channel(chan); -+ cam->pxp_chan->client = cam; -+ -+ init_completion(&cam->pxp_tx_cmpl); -+ -+ return 0; -+} -+ -+/* -+ * Function to call PxP DMA driver and send our new V4L2 buffer -+ * through the PxP. -+ * Note: This is a blocking call, so upon return the PxP tx should be complete. -+ */ -+static int pxp_process_update(cam_data *cam) -+{ -+ dma_cookie_t cookie; -+ struct scatterlist *sg = cam->sg; -+ struct dma_chan *dma_chan; -+ struct pxp_tx_desc *desc; -+ struct dma_async_tx_descriptor *txd; -+ struct pxp_config_data *pxp_conf = &cam->pxp_conf; -+ struct pxp_proc_data *proc_data = &cam->pxp_conf.proc_data; -+ int i, ret; -+ int length; -+ -+ pr_debug("Starting PxP Send Buffer\n"); -+ -+ /* First, check to see that we have acquired a PxP Channel object */ -+ if (cam->pxp_chan == NULL) { -+ /* -+ * PxP Channel has not yet been created and initialized, -+ * so let's go ahead and try -+ */ -+ ret = pxp_chan_init(cam); -+ if (ret) { -+ /* -+ * PxP channel init failed, and we can't use the -+ * PxP until the PxP DMA driver has loaded, so we abort -+ */ -+ pr_err("PxP chan init failed\n"); -+ return -ENODEV; -+ } -+ } -+ -+ /* -+ * Init completion, so that we can be properly informed of -+ * the completion of the PxP task when it is done. -+ */ -+ init_completion(&cam->pxp_tx_cmpl); -+ -+ dma_chan = &cam->pxp_chan->dma_chan; -+ -+ txd = dma_chan->device->device_prep_slave_sg(dma_chan, sg, 2, -+ DMA_TO_DEVICE, -+ DMA_PREP_INTERRUPT, -+ NULL); -+ if (!txd) { -+ pr_err("Error preparing a DMA transaction descriptor.\n"); -+ return -EIO; -+ } -+ -+ txd->callback_param = txd; -+ txd->callback = pxp_dma_done; -+ -+ /* -+ * Configure PxP for processing of new v4l2 buf -+ */ -+ pxp_conf->s0_param.pixel_fmt = PXP_PIX_FMT_UYVY; -+ pxp_conf->s0_param.color_key = -1; -+ pxp_conf->s0_param.color_key_enable = false; -+ pxp_conf->s0_param.width = cam->v2f.fmt.pix.width; -+ pxp_conf->s0_param.height = cam->v2f.fmt.pix.height; -+ -+ pxp_conf->ol_param[0].combine_enable = false; -+ -+ proc_data->srect.top = 0; -+ proc_data->srect.left = 0; -+ proc_data->srect.width = pxp_conf->s0_param.width; -+ proc_data->srect.height = pxp_conf->s0_param.height; -+ -+ if (crop_current.c.top != 0) -+ proc_data->srect.top = crop_current.c.top; -+ if (crop_current.c.left != 0) -+ proc_data->srect.left = crop_current.c.left; -+ if (crop_current.c.width != 0) -+ proc_data->srect.width = crop_current.c.width; -+ if (crop_current.c.height != 0) -+ proc_data->srect.height = crop_current.c.height; -+ -+ proc_data->drect.left = 0; -+ proc_data->drect.top = 0; -+ proc_data->drect.width = proc_data->srect.width; -+ proc_data->drect.height = proc_data->srect.height; -+ -+ if (win_current.w.left != 0) -+ proc_data->drect.left = win_current.w.left; -+ if (win_current.w.top != 0) -+ proc_data->drect.top = win_current.w.top; -+ if (win_current.w.width != 0) -+ proc_data->drect.width = win_current.w.width; -+ if (win_current.w.height != 0) -+ proc_data->drect.height = win_current.w.height; -+ -+ pr_debug("srect l: %d, t: %d, w: %d, h: %d; " -+ "drect l: %d, t: %d, w: %d, h: %d\n", -+ proc_data->srect.left, proc_data->srect.top, -+ proc_data->srect.width, proc_data->srect.height, -+ proc_data->drect.left, proc_data->drect.top, -+ proc_data->drect.width, proc_data->drect.height); -+ -+ pxp_conf->out_param.pixel_fmt = PXP_PIX_FMT_RGB565; -+ pxp_conf->out_param.width = proc_data->drect.width; -+ pxp_conf->out_param.height = proc_data->drect.height; -+ -+ if (cam->rotation % 180) -+ pxp_conf->out_param.stride = pxp_conf->out_param.height; -+ else -+ pxp_conf->out_param.stride = pxp_conf->out_param.width; -+ -+ desc = to_tx_desc(txd); -+ length = desc->len; -+ for (i = 0; i < length; i++) { -+ if (i == 0) {/* S0 */ -+ memcpy(&desc->proc_data, proc_data, -+ sizeof(struct pxp_proc_data)); -+ pxp_conf->s0_param.paddr = sg_dma_address(&sg[0]); -+ memcpy(&desc->layer_param.s0_param, &pxp_conf->s0_param, -+ sizeof(struct pxp_layer_param)); -+ } else if (i == 1) { -+ pxp_conf->out_param.paddr = sg_dma_address(&sg[1]); -+ memcpy(&desc->layer_param.out_param, -+ &pxp_conf->out_param, -+ sizeof(struct pxp_layer_param)); -+ } -+ -+ desc = desc->next; -+ } -+ -+ /* Submitting our TX starts the PxP processing task */ -+ cookie = txd->tx_submit(txd); -+ if (cookie < 0) { -+ pr_err("Error sending FB through PxP\n"); -+ return -EIO; -+ } -+ -+ cam->txd = txd; -+ -+ /* trigger PxP */ -+ dma_async_issue_pending(dma_chan); -+ -+ return 0; -+} -+ -+static int pxp_complete_update(cam_data *cam) -+{ -+ int ret; -+ /* -+ * Wait for completion event, which will be set -+ * through our TX callback function. -+ */ -+ ret = wait_for_completion_timeout(&cam->pxp_tx_cmpl, HZ / 10); -+ if (ret <= 0) { -+ pr_warning("PxP operation failed due to %s\n", -+ ret < 0 ? "user interrupt" : "timeout"); -+ dma_release_channel(&cam->pxp_chan->dma_chan); -+ cam->pxp_chan = NULL; -+ return ret ? : -ETIMEDOUT; -+ } -+ -+ dma_release_channel(&cam->pxp_chan->dma_chan); -+ cam->pxp_chan = NULL; -+ -+ pr_debug("TX completed\n"); -+ -+ return 0; -+} -+ -+/*! -+ * Camera V4l2 callback function. -+ * -+ * @param mask u32 -+ * @param dev void device structure -+ * -+ * @return none -+ */ -+static void camera_callback(u32 mask, void *dev) -+{ -+ struct mxc_v4l_frame *done_frame; -+ struct mxc_v4l_frame *ready_frame; -+ cam_data *cam; -+ -+ cam = (cam_data *) dev; -+ if (cam == NULL) -+ return; -+ -+ spin_lock(&cam->queue_int_lock); -+ spin_lock(&cam->dqueue_int_lock); -+ if (!list_empty(&cam->working_q)) { -+ done_frame = list_entry(cam->working_q.next, -+ struct mxc_v4l_frame, queue); -+ -+ if (done_frame->csi_buf_num != cam->ping_pong_csi) -+ goto next; -+ -+ if (done_frame->buffer.flags & V4L2_BUF_FLAG_QUEUED) { -+ done_frame->buffer.flags |= V4L2_BUF_FLAG_DONE; -+ done_frame->buffer.flags &= ~V4L2_BUF_FLAG_QUEUED; -+ -+ /* Added to the done queue */ -+ list_del(cam->working_q.next); -+ list_add_tail(&done_frame->queue, &cam->done_q); -+ cam->enc_counter++; -+ wake_up_interruptible(&cam->enc_queue); -+ } else { -+ pr_err("ERROR: v4l2 capture: %s: " -+ "buffer not queued\n", __func__); -+ } -+ } -+ -+next: -+ if (!list_empty(&cam->ready_q)) { -+ ready_frame = list_entry(cam->ready_q.next, -+ struct mxc_v4l_frame, queue); -+ list_del(cam->ready_q.next); -+ list_add_tail(&ready_frame->queue, &cam->working_q); -+ -+ __raw_writel(ready_frame->paddress, -+ cam->ping_pong_csi == 1 ? CSI_CSIDMASA_FB1 : -+ CSI_CSIDMASA_FB2); -+ ready_frame->csi_buf_num = cam->ping_pong_csi; -+ } else { -+ __raw_writel(cam->dummy_frame.paddress, -+ cam->ping_pong_csi == 1 ? CSI_CSIDMASA_FB1 : -+ CSI_CSIDMASA_FB2); -+ } -+ spin_unlock(&cam->dqueue_int_lock); -+ spin_unlock(&cam->queue_int_lock); -+ -+ return; -+} -+ -+/*! -+ * Make csi ready for capture image. -+ * -+ * @param cam structure cam_data * -+ * -+ * @return status 0 success -+ */ -+static int csi_cap_image(cam_data *cam) -+{ -+ unsigned int value; -+ -+ value = __raw_readl(CSI_CSICR3); -+ __raw_writel(value | BIT_FRMCNT_RST, CSI_CSICR3); -+ value = __raw_readl(CSI_CSISR); -+ __raw_writel(value, CSI_CSISR); -+ -+ return 0; -+} -+ -+/*************************************************************************** -+ * Functions for handling Frame buffers. -+ **************************************************************************/ -+ -+/*! -+ * Free frame buffers -+ * -+ * @param cam Structure cam_data * -+ * -+ * @return status 0 success. -+ */ -+static int csi_free_frame_buf(cam_data *cam) -+{ -+ int i; -+ -+ pr_debug("MVC: In %s\n", __func__); -+ -+ for (i = 0; i < FRAME_NUM; i++) { -+ if (cam->frame[i].vaddress != 0) { -+ dma_free_coherent(0, cam->frame[i].buffer.length, -+ cam->frame[i].vaddress, -+ cam->frame[i].paddress); -+ cam->frame[i].vaddress = 0; -+ } -+ } -+ -+ if (cam->dummy_frame.vaddress != 0) { -+ dma_free_coherent(0, cam->dummy_frame.buffer.length, -+ cam->dummy_frame.vaddress, -+ cam->dummy_frame.paddress); -+ cam->dummy_frame.vaddress = 0; -+ } -+ -+ return 0; -+} -+ -+/*! -+ * Allocate frame buffers -+ * -+ * @param cam Structure cam_data * -+ * @param count int number of buffer need to allocated -+ * -+ * @return status -0 Successfully allocated a buffer, -ENOBUFS failed. -+ */ -+static int csi_allocate_frame_buf(cam_data *cam, int count) -+{ -+ int i; -+ -+ pr_debug("In MVC:%s- size=%d\n", -+ __func__, cam->v2f.fmt.pix.sizeimage); -+ for (i = 0; i < count; i++) { -+ cam->frame[i].vaddress = dma_alloc_coherent(0, PAGE_ALIGN -+ (cam->v2f.fmt. -+ pix.sizeimage), -+ &cam->frame[i]. -+ paddress, -+ GFP_DMA | -+ GFP_KERNEL); -+ if (cam->frame[i].vaddress == 0) { -+ pr_err("ERROR: v4l2 capture: " -+ "%s failed.\n", __func__); -+ csi_free_frame_buf(cam); -+ return -ENOBUFS; -+ } -+ cam->frame[i].buffer.index = i; -+ cam->frame[i].buffer.flags = V4L2_BUF_FLAG_MAPPED; -+ cam->frame[i].buffer.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; -+ cam->frame[i].buffer.length = cam->v2f.fmt.pix.sizeimage; -+ cam->frame[i].buffer.memory = V4L2_MEMORY_MMAP; -+ cam->frame[i].buffer.m.offset = cam->frame[i].paddress; -+ cam->frame[i].index = i; -+ cam->frame[i].csi_buf_num = 0; -+ } -+ -+ return 0; -+} -+ -+/*! -+ * Free frame buffers status -+ * -+ * @param cam Structure cam_data * -+ * -+ * @return none -+ */ -+static void csi_free_frames(cam_data *cam) -+{ -+ int i; -+ -+ pr_debug("In MVC: %s\n", __func__); -+ -+ for (i = 0; i < FRAME_NUM; i++) -+ cam->frame[i].buffer.flags = V4L2_BUF_FLAG_MAPPED; -+ -+ cam->enc_counter = 0; -+ INIT_LIST_HEAD(&cam->ready_q); -+ INIT_LIST_HEAD(&cam->working_q); -+ INIT_LIST_HEAD(&cam->done_q); -+ -+ return; -+} -+ -+/*! -+ * Return the buffer status -+ * -+ * @param cam Structure cam_data * -+ * @param buf Structure v4l2_buffer * -+ * -+ * @return status 0 success, EINVAL failed. -+ */ -+static int csi_v4l2_buffer_status(cam_data *cam, struct v4l2_buffer *buf) -+{ -+ pr_debug("In MVC: %s\n", __func__); -+ -+ if (buf->index < 0 || buf->index >= FRAME_NUM) { -+ pr_err("ERROR: v4l2 capture: %s buffers " -+ "not allocated\n", __func__); -+ return -EINVAL; -+ } -+ -+ memcpy(buf, &(cam->frame[buf->index].buffer), sizeof(*buf)); -+ -+ return 0; -+} -+ -+static int csi_v4l2_release_bufs(cam_data *cam) -+{ -+ pr_debug("In MVC:csi_v4l2_release_bufs\n"); -+ return 0; -+} -+ -+static int csi_v4l2_prepare_bufs(cam_data *cam, struct v4l2_buffer *buf) -+{ -+ pr_debug("In MVC:csi_v4l2_prepare_bufs\n"); -+ -+ if (buf->index < 0 || buf->index >= FRAME_NUM || buf->length < -+ cam->v2f.fmt.pix.sizeimage) { -+ pr_err("ERROR: v4l2 capture: csi_v4l2_prepare_bufs buffers " -+ "not allocated,index=%d, length=%d\n", buf->index, -+ buf->length); -+ return -EINVAL; -+ } -+ -+ cam->frame[buf->index].buffer.index = buf->index; -+ cam->frame[buf->index].buffer.flags = V4L2_BUF_FLAG_MAPPED; -+ cam->frame[buf->index].buffer.length = buf->length; -+ cam->frame[buf->index].buffer.m.offset = cam->frame[buf->index].paddress -+ = buf->m.offset; -+ cam->frame[buf->index].buffer.type = buf->type; -+ cam->frame[buf->index].buffer.memory = V4L2_MEMORY_USERPTR; -+ cam->frame[buf->index].index = buf->index; -+ -+ return 0; -+} -+ -+/*! -+ * Indicates whether the palette is supported. -+ * -+ * @param palette V4L2_PIX_FMT_RGB565, V4L2_PIX_FMT_UYVY or V4L2_PIX_FMT_YUV420 -+ * -+ * @return 0 if failed -+ */ -+static inline int valid_mode(u32 palette) -+{ -+ return (palette == V4L2_PIX_FMT_RGB565) || -+ (palette == V4L2_PIX_FMT_YUYV) || -+ (palette == V4L2_PIX_FMT_UYVY) || (palette == V4L2_PIX_FMT_YUV420); -+} -+ -+/*! -+ * Start stream I/O -+ * -+ * @param cam structure cam_data * -+ * -+ * @return status 0 Success -+ */ -+static int csi_streamon(cam_data *cam) -+{ -+ struct mxc_v4l_frame *frame; -+ unsigned long flags; -+ unsigned long val; -+ int timeout, timeout2; -+ -+ pr_debug("In MVC: %s\n", __func__); -+ -+ if (NULL == cam) { -+ pr_err("ERROR: v4l2 capture: %s cam parameter is NULL\n", -+ __func__); -+ return -1; -+ } -+ cam->dummy_frame.vaddress = dma_alloc_coherent(0, -+ PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage), -+ &cam->dummy_frame.paddress, -+ GFP_DMA | GFP_KERNEL); -+ if (cam->dummy_frame.vaddress == 0) { -+ pr_err("ERROR: v4l2 capture: Allocate dummy frame " -+ "failed.\n"); -+ return -ENOBUFS; -+ } -+ cam->dummy_frame.buffer.type = V4L2_BUF_TYPE_PRIVATE; -+ cam->dummy_frame.buffer.length = cam->v2f.fmt.pix.sizeimage; -+ cam->dummy_frame.buffer.m.offset = cam->dummy_frame.paddress; -+ -+ spin_lock_irqsave(&cam->queue_int_lock, flags); -+ /* move the frame from readyq to workingq */ -+ if (list_empty(&cam->ready_q)) { -+ pr_err("ERROR: v4l2 capture: %s: " -+ "ready_q queue empty\n", __func__); -+ spin_unlock_irqrestore(&cam->queue_int_lock, flags); -+ return -1; -+ } -+ frame = list_entry(cam->ready_q.next, struct mxc_v4l_frame, queue); -+ list_del(cam->ready_q.next); -+ list_add_tail(&frame->queue, &cam->working_q); -+ __raw_writel(frame->paddress, CSI_CSIDMASA_FB1); -+ frame->csi_buf_num = 1; -+ -+ if (list_empty(&cam->ready_q)) { -+ pr_err("ERROR: v4l2 capture: %s: " -+ "ready_q queue empty\n", __func__); -+ spin_unlock_irqrestore(&cam->queue_int_lock, flags); -+ return -1; -+ } -+ frame = list_entry(cam->ready_q.next, struct mxc_v4l_frame, queue); -+ list_del(cam->ready_q.next); -+ list_add_tail(&frame->queue, &cam->working_q); -+ __raw_writel(frame->paddress, CSI_CSIDMASA_FB2); -+ frame->csi_buf_num = 2; -+ spin_unlock_irqrestore(&cam->queue_int_lock, flags); -+ -+ cam->capture_pid = current->pid; -+ cam->capture_on = true; -+ csi_cap_image(cam); -+ -+ local_irq_save(flags); -+ for (timeout = 1000000; timeout > 0; timeout--) { -+ if (__raw_readl(CSI_CSISR) & BIT_SOF_INT) { -+ val = __raw_readl(CSI_CSICR3); -+ __raw_writel(val | BIT_DMA_REFLASH_RFF, CSI_CSICR3); -+ for (timeout2 = 1000000; timeout2 > 0; timeout2--) { -+ if (__raw_readl(CSI_CSICR3) & -+ BIT_DMA_REFLASH_RFF) -+ cpu_relax(); -+ else -+ break; -+ } -+ if (timeout2 <= 0) { -+ pr_err("timeout when wait for reflash done.\n"); -+ local_irq_restore(flags); -+ return -ETIME; -+ } -+ -+ csi_dmareq_rff_enable(); -+ csi_enable_int(1); -+ break; -+ } else -+ cpu_relax(); -+ } -+ if (timeout <= 0) { -+ pr_err("timeout when wait for SOF\n"); -+ local_irq_restore(flags); -+ return -ETIME; -+ } -+ local_irq_restore(flags); -+ -+ return 0; -+} -+ -+/*! -+ * Stop stream I/O -+ * -+ * @param cam structure cam_data * -+ * -+ * @return status 0 Success -+ */ -+static int csi_streamoff(cam_data *cam) -+{ -+ pr_debug("In MVC: %s\n", __func__); -+ -+ if (cam->capture_on == false) -+ return 0; -+ -+ csi_dmareq_rff_disable(); -+ csi_disable_int(); -+ cam->capture_on = false; -+ -+ /* set CSI_CSIDMASA_FB1 and CSI_CSIDMASA_FB2 to default value */ -+ __raw_writel(0, CSI_CSIDMASA_FB1); -+ __raw_writel(0, CSI_CSIDMASA_FB2); -+ -+ csi_free_frames(cam); -+ csi_free_frame_buf(cam); -+ -+ return 0; -+} -+ -+/*! -+ * start the viewfinder job -+ * -+ * @param cam structure cam_data * -+ * -+ * @return status 0 Success -+ */ -+static int start_preview(cam_data *cam) -+{ -+ unsigned long fb_addr = (unsigned long)cam->v4l2_fb.base; -+ -+ __raw_writel(fb_addr, CSI_CSIDMASA_FB1); -+ __raw_writel(fb_addr, CSI_CSIDMASA_FB2); -+ __raw_writel(__raw_readl(CSI_CSICR3) | BIT_DMA_REFLASH_RFF, CSI_CSICR3); -+ -+ csi_enable_int(0); -+ -+ return 0; -+} -+ -+/*! -+ * shut down the viewfinder job -+ * -+ * @param cam structure cam_data * -+ * -+ * @return status 0 Success -+ */ -+static int stop_preview(cam_data *cam) -+{ -+ csi_disable_int(); -+ -+ /* set CSI_CSIDMASA_FB1 and CSI_CSIDMASA_FB2 to default value */ -+ __raw_writel(0, CSI_CSIDMASA_FB1); -+ __raw_writel(0, CSI_CSIDMASA_FB2); -+ __raw_writel(__raw_readl(CSI_CSICR3) | BIT_DMA_REFLASH_RFF, CSI_CSICR3); -+ -+ return 0; -+} -+ -+/*************************************************************************** -+ * VIDIOC Functions. -+ **************************************************************************/ -+ -+/*! -+ * -+ * @param cam structure cam_data * -+ * -+ * @param f structure v4l2_format * -+ * -+ * @return status 0 success, EINVAL failed -+ */ -+static int csi_v4l2_g_fmt(cam_data *cam, struct v4l2_format *f) -+{ -+ int retval = 0; -+ -+ switch (f->type) { -+ case V4L2_BUF_TYPE_VIDEO_CAPTURE: -+ pr_debug(" type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n"); -+ f->fmt.pix = cam->v2f.fmt.pix; -+ break; -+ case V4L2_BUF_TYPE_VIDEO_OVERLAY: -+ pr_debug(" type is V4L2_BUF_TYPE_VIDEO_OVERLAY\n"); -+ f->fmt.win = cam->win; -+ break; -+ default: -+ pr_debug(" type is invalid\n"); -+ retval = -EINVAL; -+ } -+ -+ pr_debug("End of %s: v2f pix widthxheight %d x %d\n", -+ __func__, cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height); -+ -+ return retval; -+} -+ -+/*! -+ * V4L2 - csi_v4l2_s_fmt function -+ * -+ * @param cam structure cam_data * -+ * -+ * @param f structure v4l2_format * -+ * -+ * @return status 0 success, EINVAL failed -+ */ -+static int csi_v4l2_s_fmt(cam_data *cam, struct v4l2_format *f) -+{ -+ int retval = 0; -+ int size = 0; -+ int bytesperline = 0; -+ int *width, *height; -+ -+ pr_debug("In MVC: %s\n", __func__); -+ -+ switch (f->type) { -+ case V4L2_BUF_TYPE_VIDEO_CAPTURE: -+ pr_debug(" type=V4L2_BUF_TYPE_VIDEO_CAPTURE\n"); -+ if (!valid_mode(f->fmt.pix.pixelformat)) { -+ pr_err("ERROR: v4l2 capture: %s: format " -+ "not supported\n", __func__); -+ return -EINVAL; -+ } -+ -+ /* Handle case where size requested is larger than cuurent -+ * camera setting. */ -+ if ((f->fmt.pix.width > cam->crop_bounds.width) -+ || (f->fmt.pix.height > cam->crop_bounds.height)) { -+ /* Need the logic here, calling vidioc_s_param if -+ * camera can change. */ -+ pr_debug("csi_v4l2_s_fmt size changed\n"); -+ } -+ if (cam->rotation % 180) { -+ height = &f->fmt.pix.width; -+ width = &f->fmt.pix.height; -+ } else { -+ width = &f->fmt.pix.width; -+ height = &f->fmt.pix.height; -+ } -+ -+ if ((cam->crop_bounds.width / *width > 8) || -+ ((cam->crop_bounds.width / *width == 8) && -+ (cam->crop_bounds.width % *width))) { -+ *width = cam->crop_bounds.width / 8; -+ if (*width % 8) -+ *width += 8 - *width % 8; -+ pr_err("ERROR: v4l2 capture: width exceeds limit " -+ "resize to %d.\n", *width); -+ } -+ -+ if ((cam->crop_bounds.height / *height > 8) || -+ ((cam->crop_bounds.height / *height == 8) && -+ (cam->crop_bounds.height % *height))) { -+ *height = cam->crop_bounds.height / 8; -+ if (*height % 8) -+ *height += 8 - *height % 8; -+ pr_err("ERROR: v4l2 capture: height exceeds limit " -+ "resize to %d.\n", *height); -+ } -+ -+ switch (f->fmt.pix.pixelformat) { -+ case V4L2_PIX_FMT_RGB565: -+ size = f->fmt.pix.width * f->fmt.pix.height * 2; -+ csi_init_format(V4L2_PIX_FMT_UYVY); -+ csi_set_16bit_imagpara(f->fmt.pix.width, -+ f->fmt.pix.height); -+ bytesperline = f->fmt.pix.width * 2; -+ break; -+ case V4L2_PIX_FMT_UYVY: -+ size = f->fmt.pix.width * f->fmt.pix.height * 2; -+ csi_init_format(f->fmt.pix.pixelformat); -+ csi_set_16bit_imagpara(f->fmt.pix.width, -+ f->fmt.pix.height); -+ bytesperline = f->fmt.pix.width * 2; -+ break; -+ case V4L2_PIX_FMT_YUYV: -+ size = f->fmt.pix.width * f->fmt.pix.height * 2; -+ csi_init_format(f->fmt.pix.pixelformat); -+ csi_set_16bit_imagpara(f->fmt.pix.width, -+ f->fmt.pix.height); -+ bytesperline = f->fmt.pix.width * 2; -+ break; -+ case V4L2_PIX_FMT_YUV420: -+ size = f->fmt.pix.width * f->fmt.pix.height * 3 / 2; -+ csi_set_12bit_imagpara(f->fmt.pix.width, -+ f->fmt.pix.height); -+ bytesperline = f->fmt.pix.width; -+ break; -+ case V4L2_PIX_FMT_YUV422P: -+ case V4L2_PIX_FMT_RGB24: -+ case V4L2_PIX_FMT_BGR24: -+ case V4L2_PIX_FMT_BGR32: -+ case V4L2_PIX_FMT_RGB32: -+ case V4L2_PIX_FMT_NV12: -+ default: -+ pr_debug(" case not supported\n"); -+ break; -+ } -+ -+ if (f->fmt.pix.bytesperline < bytesperline) -+ f->fmt.pix.bytesperline = bytesperline; -+ else -+ bytesperline = f->fmt.pix.bytesperline; -+ -+ if (f->fmt.pix.sizeimage < size) -+ f->fmt.pix.sizeimage = size; -+ else -+ size = f->fmt.pix.sizeimage; -+ -+ cam->v2f.fmt.pix = f->fmt.pix; -+ -+ if (cam->v2f.fmt.pix.priv != 0) { -+ if (copy_from_user(&cam->offset, -+ (void *)cam->v2f.fmt.pix.priv, -+ sizeof(cam->offset))) { -+ retval = -EFAULT; -+ break; -+ } -+ } -+ break; -+ case V4L2_BUF_TYPE_VIDEO_OVERLAY: -+ pr_debug(" type=V4L2_BUF_TYPE_VIDEO_OVERLAY\n"); -+ cam->win = f->fmt.win; -+ win_current = f->fmt.win; -+ size = win_current.w.width * win_current.w.height * 2; -+ if (cam->v2f.fmt.pix.sizeimage < size) -+ cam->v2f.fmt.pix.sizeimage = size; -+ -+ break; -+ default: -+ retval = -EINVAL; -+ } -+ -+ pr_debug("End of %s: v2f pix widthxheight %d x %d\n", -+ __func__, cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height); -+ -+ return retval; -+} -+ -+/*! -+ * V4L2 - csi_v4l2_s_param function -+ * Allows setting of capturemode and frame rate. -+ * -+ * @param cam structure cam_data * -+ * @param parm structure v4l2_streamparm * -+ * -+ * @return status 0 success, EINVAL failed -+ */ -+static int csi_v4l2_s_param(cam_data *cam, struct v4l2_streamparm *parm) -+{ -+ struct v4l2_ifparm ifparm; -+ struct v4l2_format cam_fmt; -+ struct v4l2_streamparm currentparm; -+ int err = 0; -+ -+ pr_debug("In %s\n", __func__); -+ -+ if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { -+ pr_err(KERN_ERR "%s invalid type\n", __func__); -+ return -EINVAL; -+ } -+ -+ /* Stop the viewfinder */ -+ if (cam->overlay_on == true) -+ stop_preview(cam); -+ -+ currentparm.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; -+ -+ /* First check that this device can support the changes requested. */ -+ err = vidioc_int_g_parm(cam->sensor, ¤tparm); -+ if (err) { -+ pr_err("%s: vidioc_int_g_parm returned an error %d\n", -+ __func__, err); -+ goto exit; -+ } -+ -+ pr_debug(" Current capabilities are %x\n", -+ currentparm.parm.capture.capability); -+ pr_debug(" Current capturemode is %d change to %d\n", -+ currentparm.parm.capture.capturemode, -+ parm->parm.capture.capturemode); -+ pr_debug(" Current framerate is %d change to %d\n", -+ currentparm.parm.capture.timeperframe.denominator, -+ parm->parm.capture.timeperframe.denominator); -+ -+ err = vidioc_int_s_parm(cam->sensor, parm); -+ if (err) { -+ pr_err("%s: vidioc_int_s_parm returned an error %d\n", -+ __func__, err); -+ goto exit; -+ } -+ -+ vidioc_int_g_ifparm(cam->sensor, &ifparm); -+ cam_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; -+ vidioc_int_g_fmt_cap(cam->sensor, &cam_fmt); -+ pr_debug(" g_fmt_cap returns widthxheight of input as %d x %d\n", -+ cam_fmt.fmt.pix.width, cam_fmt.fmt.pix.height); -+ -+ cam->crop_bounds.top = cam->crop_bounds.left = 0; -+ cam->crop_bounds.width = cam_fmt.fmt.pix.width; -+ cam->crop_bounds.height = cam_fmt.fmt.pix.height; -+ cam->crop_current.width = cam->crop_bounds.width; -+ cam->crop_current.height = cam->crop_bounds.height; -+ -+exit: -+ return err; -+} -+ -+static int pxp_set_cstate(cam_data *cam, struct v4l2_control *vc) -+{ -+ struct pxp_proc_data *proc_data = &cam->pxp_conf.proc_data; -+ -+ if (vc->id == V4L2_CID_HFLIP) { -+ proc_data->hflip = vc->value; -+ } else if (vc->id == V4L2_CID_VFLIP) { -+ proc_data->vflip = vc->value; -+ } else if (vc->id == V4L2_CID_PRIVATE_BASE) { -+ if (vc->value % 90) -+ return -ERANGE; -+ proc_data->rotate = vc->value; -+ cam->rotation = vc->value; -+ } -+ -+ return 0; -+} -+ -+static int pxp_get_cstate(cam_data *cam, struct v4l2_control *vc) -+{ -+ struct pxp_proc_data *proc_data = &cam->pxp_conf.proc_data; -+ -+ if (vc->id == V4L2_CID_HFLIP) -+ vc->value = proc_data->hflip; -+ else if (vc->id == V4L2_CID_VFLIP) -+ vc->value = proc_data->vflip; -+ else if (vc->id == V4L2_CID_PRIVATE_BASE) -+ vc->value = proc_data->rotate; -+ -+ return 0; -+} -+ -+ -+/*! -+ * Dequeue one V4L capture buffer -+ * -+ * @param cam structure cam_data * -+ * @param buf structure v4l2_buffer * -+ * -+ * @return status 0 success, EINVAL invalid frame number -+ * ETIME timeout, ERESTARTSYS interrupted by user -+ */ -+static int csi_v4l_dqueue(cam_data *cam, struct v4l2_buffer *buf) -+{ -+ int retval = 0; -+ struct mxc_v4l_frame *frame; -+ unsigned long lock_flags; -+ -+ if (!wait_event_interruptible_timeout(cam->enc_queue, -+ cam->enc_counter != 0, 10 * HZ)) { -+ pr_err("ERROR: v4l2 capture: mxc_v4l_dqueue timeout " -+ "enc_counter %x\n", cam->enc_counter); -+ return -ETIME; -+ } else if (signal_pending(current)) { -+ pr_err("ERROR: v4l2 capture: mxc_v4l_dqueue() " -+ "interrupt received\n"); -+ return -ERESTARTSYS; -+ } -+ -+ if (down_interruptible(&cam->busy_lock)) -+ return -EBUSY; -+ -+ spin_lock_irqsave(&cam->dqueue_int_lock, lock_flags); -+ -+ if (list_empty(&cam->done_q)) { -+ spin_unlock_irqrestore(&cam->dqueue_int_lock, lock_flags); -+ up(&cam->busy_lock); -+ return -EINVAL; -+ } -+ -+ cam->enc_counter--; -+ -+ frame = list_entry(cam->done_q.next, struct mxc_v4l_frame, queue); -+ list_del(cam->done_q.next); -+ -+ if (frame->buffer.flags & V4L2_BUF_FLAG_DONE) { -+ frame->buffer.flags &= ~V4L2_BUF_FLAG_DONE; -+ } else if (frame->buffer.flags & V4L2_BUF_FLAG_QUEUED) { -+ pr_err("ERROR: v4l2 capture: VIDIOC_DQBUF: " -+ "Buffer not filled.\n"); -+ frame->buffer.flags &= ~V4L2_BUF_FLAG_QUEUED; -+ retval = -EINVAL; -+ } else if ((frame->buffer.flags & 0x7) == V4L2_BUF_FLAG_MAPPED) { -+ pr_err("ERROR: v4l2 capture: VIDIOC_DQBUF: " -+ "Buffer not queued.\n"); -+ retval = -EINVAL; -+ } -+ -+ spin_unlock_irqrestore(&cam->dqueue_int_lock, lock_flags); -+ -+ buf->bytesused = cam->v2f.fmt.pix.sizeimage; -+ buf->index = frame->index; -+ buf->flags = frame->buffer.flags; -+ buf->m = cam->frame[frame->index].buffer.m; -+ -+ /* -+ * Note: -+ * If want to do preview on LCD, use PxP CSC to convert from UYVY -+ * to RGB565; but for encoding, usually we don't use RGB format. -+ */ -+ if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB565) { -+ sg_dma_address(&cam->sg[0]) = buf->m.offset; -+ sg_dma_address(&cam->sg[1]) = -+ cam->frame[req_buf_number].paddress; -+ retval = pxp_process_update(cam); -+ if (retval) { -+ pr_err("Unable to submit PxP update task.\n"); -+ return retval; -+ } -+ pxp_complete_update(cam); -+ if (cam->frame[buf->index].vaddress) -+ memcpy(cam->frame[buf->index].vaddress, -+ cam->frame[req_buf_number].vaddress, -+ cam->v2f.fmt.pix.sizeimage); -+ } -+ up(&cam->busy_lock); -+ -+ return retval; -+} -+ -+/*! -+ * V4L interface - open function -+ * -+ * @param file structure file * -+ * -+ * @return status 0 success, ENODEV invalid device instance, -+ * ENODEV timeout, ERESTARTSYS interrupted by user -+ */ -+static int csi_v4l_open(struct file *file) -+{ -+ struct v4l2_ifparm ifparm; -+ struct v4l2_format cam_fmt; -+ struct video_device *dev = video_devdata(file); -+ cam_data *cam = video_get_drvdata(dev); -+ struct sensor_data *sensor; -+ int err = 0; -+ -+ pr_debug(" device name is %s\n", dev->name); -+ -+ if (!cam) { -+ pr_err("%s: Internal error, cam_data not found!\n", __func__); -+ return -EBADF; -+ } -+ -+ if (!cam->sensor) { -+ pr_err("%s: Internal error, camera is not found!\n", __func__); -+ return -EBADF; -+ } -+ -+ sensor = cam->sensor->priv; -+ if (!sensor) { -+ pr_err("%s: Internal error, sensor_data is not found!\n", __func__); -+ return -EBADF; -+ } -+ -+ down(&cam->busy_lock); -+ err = 0; -+ if (signal_pending(current)) -+ goto oops; -+ -+ if (cam->open_count++ == 0) { -+ wait_event_interruptible(cam->power_queue, -+ cam->low_power == false); -+ -+ cam->enc_counter = 0; -+ INIT_LIST_HEAD(&cam->ready_q); -+ INIT_LIST_HEAD(&cam->working_q); -+ INIT_LIST_HEAD(&cam->done_q); -+ -+ vidioc_int_g_ifparm(cam->sensor, &ifparm); -+ -+ cam_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; -+ clk_prepare_enable(sensor->sensor_clk); -+ vidioc_int_s_power(cam->sensor, 1); -+ vidioc_int_init(cam->sensor); -+ vidioc_int_dev_init(cam->sensor); -+ } -+ -+ file->private_data = dev; -+ -+oops: -+ up(&cam->busy_lock); -+ return err; -+} -+ -+/*! -+ * V4L interface - close function -+ * -+ * @param file struct file * -+ * -+ * @return 0 success -+ */ -+static int csi_v4l_close(struct file *file) -+{ -+ struct video_device *dev = video_devdata(file); -+ int err = 0; -+ cam_data *cam = video_get_drvdata(dev); -+ struct sensor_data *sensor; -+ -+ pr_debug("In MVC:%s\n", __func__); -+ -+ if (!cam) { -+ pr_err("%s: Internal error, cam_data not found!\n", __func__); -+ return -EBADF; -+ } -+ -+ if (!cam->sensor) { -+ pr_err("%s: Internal error, camera is not found!\n", __func__); -+ return -EBADF; -+ } -+ -+ sensor = cam->sensor->priv; -+ if (!sensor) { -+ pr_err("%s: Internal error, sensor_data is not found!\n", __func__); -+ return -EBADF; -+ } -+ -+ /* for the case somebody hit the ctrl C */ -+ if (cam->overlay_pid == current->pid) { -+ err = stop_preview(cam); -+ cam->overlay_on = false; -+ } -+ -+ if (--cam->open_count == 0) { -+ wait_event_interruptible(cam->power_queue, -+ cam->low_power == false); -+ file->private_data = NULL; -+ vidioc_int_s_power(cam->sensor, 0); -+ clk_disable_unprepare(sensor->sensor_clk); -+ } -+ -+ return err; -+} -+ -+/* -+ * V4L interface - read function -+ * -+ * @param file struct file * -+ * @param read buf char * -+ * @param count size_t -+ * @param ppos structure loff_t * -+ * -+ * @return bytes read -+ */ -+static ssize_t csi_v4l_read(struct file *file, char *buf, size_t count, -+ loff_t *ppos) -+{ -+ int err = 0; -+ struct video_device *dev = video_devdata(file); -+ cam_data *cam = video_get_drvdata(dev); -+ -+ if (down_interruptible(&cam->busy_lock)) -+ return -EINTR; -+ -+ /* Stop the viewfinder */ -+ if (cam->overlay_on == true) -+ stop_preview(cam); -+ -+ if (cam->still_buf_vaddr == NULL) { -+ cam->still_buf_vaddr = dma_alloc_coherent(0, -+ PAGE_ALIGN -+ (cam->v2f.fmt. -+ pix.sizeimage), -+ &cam-> -+ still_buf[0], -+ GFP_DMA | GFP_KERNEL); -+ if (cam->still_buf_vaddr == NULL) { -+ pr_err("alloc dma memory failed\n"); -+ return -ENOMEM; -+ } -+ cam->still_counter = 0; -+ __raw_writel(cam->still_buf[0], CSI_CSIDMASA_FB2); -+ __raw_writel(cam->still_buf[0], CSI_CSIDMASA_FB1); -+ __raw_writel(__raw_readl(CSI_CSICR3) | BIT_DMA_REFLASH_RFF, -+ CSI_CSICR3); -+ __raw_writel(__raw_readl(CSI_CSISR), CSI_CSISR); -+ __raw_writel(__raw_readl(CSI_CSICR3) | BIT_FRMCNT_RST, -+ CSI_CSICR3); -+ csi_enable_int(1); -+ } -+ -+ wait_event_interruptible(cam->still_queue, cam->still_counter); -+ csi_disable_int(); -+ err = copy_to_user(buf, cam->still_buf_vaddr, -+ cam->v2f.fmt.pix.sizeimage); -+ -+ if (cam->still_buf_vaddr != NULL) { -+ dma_free_coherent(0, PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage), -+ cam->still_buf_vaddr, cam->still_buf[0]); -+ cam->still_buf[0] = 0; -+ cam->still_buf_vaddr = NULL; -+ } -+ -+ if (cam->overlay_on == true) -+ start_preview(cam); -+ -+ up(&cam->busy_lock); -+ if (err < 0) -+ return err; -+ -+ return cam->v2f.fmt.pix.sizeimage - err; -+} -+ -+/*! -+ * V4L interface - ioctl function -+ * -+ * @param file struct file* -+ * -+ * @param ioctlnr unsigned int -+ * -+ * @param arg void* -+ * -+ * @return 0 success, ENODEV for invalid device instance, -+ * -1 for other errors. -+ */ -+static long csi_v4l_do_ioctl(struct file *file, -+ unsigned int ioctlnr, void *arg) -+{ -+ struct video_device *dev = video_devdata(file); -+ cam_data *cam = video_get_drvdata(dev); -+ int retval = 0; -+ unsigned long lock_flags; -+ -+ pr_debug("In MVC: %s, %x\n", __func__, ioctlnr); -+ wait_event_interruptible(cam->power_queue, cam->low_power == false); -+ /* make this _really_ smp-safe */ -+ if (ioctlnr != VIDIOC_DQBUF) -+ if (down_interruptible(&cam->busy_lock)) -+ return -EBUSY; -+ -+ switch (ioctlnr) { -+ /*! -+ * V4l2 VIDIOC_G_FMT ioctl -+ */ -+ case VIDIOC_G_FMT:{ -+ struct v4l2_format *gf = arg; -+ pr_debug(" case VIDIOC_G_FMT\n"); -+ retval = csi_v4l2_g_fmt(cam, gf); -+ break; -+ } -+ -+ /*! -+ * V4l2 VIDIOC_S_FMT ioctl -+ */ -+ case VIDIOC_S_FMT:{ -+ struct v4l2_format *sf = arg; -+ pr_debug(" case VIDIOC_S_FMT\n"); -+ retval = csi_v4l2_s_fmt(cam, sf); -+ vidioc_int_s_fmt_cap(cam->sensor, sf); -+ break; -+ } -+ -+ /*! -+ * V4l2 VIDIOC_OVERLAY ioctl -+ */ -+ case VIDIOC_OVERLAY:{ -+ int *on = arg; -+ pr_debug(" case VIDIOC_OVERLAY\n"); -+ if (*on) { -+ cam->overlay_on = true; -+ cam->overlay_pid = current->pid; -+ start_preview(cam); -+ } -+ if (!*on) { -+ stop_preview(cam); -+ cam->overlay_on = false; -+ } -+ break; -+ } -+ -+ /*! -+ * V4l2 VIDIOC_G_FBUF ioctl -+ */ -+ case VIDIOC_G_FBUF:{ -+ struct v4l2_framebuffer *fb = arg; -+ *fb = cam->v4l2_fb; -+ fb->capability = V4L2_FBUF_CAP_EXTERNOVERLAY; -+ break; -+ } -+ -+ /*! -+ * V4l2 VIDIOC_S_FBUF ioctl -+ */ -+ case VIDIOC_S_FBUF:{ -+ struct v4l2_framebuffer *fb = arg; -+ cam->v4l2_fb = *fb; -+ break; -+ } -+ -+ case VIDIOC_G_PARM:{ -+ struct v4l2_streamparm *parm = arg; -+ pr_debug(" case VIDIOC_G_PARM\n"); -+ vidioc_int_g_parm(cam->sensor, parm); -+ break; -+ } -+ -+ case VIDIOC_S_PARM:{ -+ struct v4l2_streamparm *parm = arg; -+ pr_debug(" case VIDIOC_S_PARM\n"); -+ retval = csi_v4l2_s_param(cam, parm); -+ break; -+ } -+ -+ case VIDIOC_QUERYCAP:{ -+ struct v4l2_capability *cap = arg; -+ pr_debug(" case VIDIOC_QUERYCAP\n"); -+ strcpy(cap->driver, "csi_v4l2"); -+ cap->version = KERNEL_VERSION(0, 1, 11); -+ cap->capabilities = V4L2_CAP_VIDEO_OVERLAY | -+ V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING | -+ V4L2_CAP_VIDEO_OUTPUT_OVERLAY | V4L2_CAP_READWRITE; -+ cap->card[0] = '\0'; -+ cap->bus_info[0] = '\0'; -+ break; -+ } -+ -+ case VIDIOC_CROPCAP: -+ { -+ struct v4l2_cropcap *cap = arg; -+ -+ if (cap->type != V4L2_BUF_TYPE_VIDEO_CAPTURE && -+ cap->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) { -+ retval = -EINVAL; -+ break; -+ } -+ cap->bounds = cam->crop_bounds; -+ cap->defrect = cam->crop_defrect; -+ break; -+ } -+ case VIDIOC_S_CROP: -+ { -+ struct v4l2_crop *crop = arg; -+ struct v4l2_rect *b = &cam->crop_bounds; -+ -+ if (crop->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { -+ retval = -EINVAL; -+ break; -+ } -+ -+ crop->c.top = (crop->c.top < b->top) ? b->top -+ : crop->c.top; -+ if (crop->c.top > b->top + b->height) -+ crop->c.top = b->top + b->height - 1; -+ if (crop->c.height > b->top + b->height - crop->c.top) -+ crop->c.height = -+ b->top + b->height - crop->c.top; -+ -+ crop->c.left = (crop->c.left < b->left) ? b->left -+ : crop->c.left; -+ if (crop->c.left > b->left + b->width) -+ crop->c.left = b->left + b->width - 1; -+ if (crop->c.width > b->left - crop->c.left + b->width) -+ crop->c.width = -+ b->left - crop->c.left + b->width; -+ -+ crop->c.width -= crop->c.width % 8; -+ crop->c.height -= crop->c.height % 8; -+ -+ crop_current.c = crop->c; -+ -+ break; -+ } -+ case VIDIOC_G_CROP: -+ { -+ struct v4l2_crop *crop = arg; -+ -+ if (crop->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { -+ retval = -EINVAL; -+ break; -+ } -+ crop->c = crop_current.c; -+ -+ break; -+ -+ } -+ case VIDIOC_REQBUFS: { -+ struct v4l2_requestbuffers *req = arg; -+ pr_debug(" case VIDIOC_REQBUFS\n"); -+ -+ if (req->count > FRAME_NUM) { -+ pr_err("ERROR: v4l2 capture: VIDIOC_REQBUFS: " -+ "not enough buffers\n"); -+ req->count = FRAME_NUM; -+ } -+ -+ if (req->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { -+ pr_err("ERROR: v4l2 capture: VIDIOC_REQBUFS: " -+ "wrong buffer type\n"); -+ retval = -EINVAL; -+ break; -+ } -+ -+ csi_streamoff(cam); -+ if (req->memory & V4L2_MEMORY_MMAP) { -+ csi_free_frame_buf(cam); -+ retval = csi_allocate_frame_buf(cam, req->count + 1); -+ req_buf_number = req->count; -+ } -+ break; -+ } -+ -+ case VIDIOC_QUERYBUF: { -+ struct v4l2_buffer *buf = arg; -+ int index = buf->index; -+ pr_debug(" case VIDIOC_QUERYBUF\n"); -+ -+ if (buf->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { -+ retval = -EINVAL; -+ break; -+ } -+ -+ if (buf->memory & V4L2_MEMORY_MMAP) { -+ memset(buf, 0, sizeof(buf)); -+ buf->index = index; -+ } -+ -+ down(&cam->param_lock); -+ if (buf->memory & V4L2_MEMORY_USERPTR) { -+ csi_v4l2_release_bufs(cam); -+ retval = csi_v4l2_prepare_bufs(cam, buf); -+ } -+ if (buf->memory & V4L2_MEMORY_MMAP) -+ retval = csi_v4l2_buffer_status(cam, buf); -+ up(&cam->param_lock); -+ break; -+ } -+ -+ case VIDIOC_QBUF: { -+ struct v4l2_buffer *buf = arg; -+ int index = buf->index; -+ pr_debug(" case VIDIOC_QBUF\n"); -+ -+ spin_lock_irqsave(&cam->queue_int_lock, lock_flags); -+ cam->frame[index].buffer.m.offset = buf->m.offset; -+ if ((cam->frame[index].buffer.flags & 0x7) == -+ V4L2_BUF_FLAG_MAPPED) { -+ cam->frame[index].buffer.flags |= V4L2_BUF_FLAG_QUEUED; -+ list_add_tail(&cam->frame[index].queue, &cam->ready_q); -+ } else if (cam->frame[index].buffer.flags & -+ V4L2_BUF_FLAG_QUEUED) { -+ pr_err("ERROR: v4l2 capture: VIDIOC_QBUF: " -+ "buffer already queued\n"); -+ retval = -EINVAL; -+ } else if (cam->frame[index].buffer. -+ flags & V4L2_BUF_FLAG_DONE) { -+ pr_err("ERROR: v4l2 capture: VIDIOC_QBUF: " -+ "overwrite done buffer.\n"); -+ cam->frame[index].buffer.flags &= -+ ~V4L2_BUF_FLAG_DONE; -+ cam->frame[index].buffer.flags |= -+ V4L2_BUF_FLAG_QUEUED; -+ retval = -EINVAL; -+ } -+ buf->flags = cam->frame[index].buffer.flags; -+ spin_unlock_irqrestore(&cam->queue_int_lock, lock_flags); -+ -+ break; -+ } -+ -+ case VIDIOC_DQBUF: { -+ struct v4l2_buffer *buf = arg; -+ pr_debug(" case VIDIOC_DQBUF\n"); -+ -+ retval = csi_v4l_dqueue(cam, buf); -+ -+ break; -+ } -+ -+ case VIDIOC_STREAMON: { -+ pr_debug(" case VIDIOC_STREAMON\n"); -+ retval = csi_streamon(cam); -+ break; -+ } -+ -+ case VIDIOC_STREAMOFF: { -+ pr_debug(" case VIDIOC_STREAMOFF\n"); -+ retval = csi_streamoff(cam); -+ break; -+ } -+ case VIDIOC_ENUM_FMT: { -+ struct v4l2_fmtdesc *fmt = arg; -+ if (cam->sensor) -+ retval = vidioc_int_enum_fmt_cap(cam->sensor, fmt); -+ else { -+ pr_err("ERROR: v4l2 capture: slave not found!\n"); -+ retval = -ENODEV; -+ } -+ break; -+ } -+ case VIDIOC_ENUM_FRAMESIZES: { -+ struct v4l2_frmsizeenum *fsize = arg; -+ if (cam->sensor) -+ retval = vidioc_int_enum_framesizes(cam->sensor, fsize); -+ else { -+ pr_err("ERROR: v4l2 capture: slave not found!\n"); -+ retval = -ENODEV; -+ } -+ break; -+ } -+ case VIDIOC_ENUM_FRAMEINTERVALS: { -+ struct v4l2_frmivalenum *fival = arg; -+ if (cam->sensor) -+ retval = vidioc_int_enum_frameintervals(cam->sensor, -+ fival); -+ else { -+ pr_err("ERROR: v4l2 capture: slave not found!\n"); -+ retval = -ENODEV; -+ } -+ break; -+ } -+ case VIDIOC_DBG_G_CHIP_IDENT: { -+ struct v4l2_dbg_chip_ident *p = arg; -+ p->ident = V4L2_IDENT_NONE; -+ p->revision = 0; -+ if (cam->sensor) -+ retval = vidioc_int_g_chip_ident(cam->sensor, (int *)p); -+ else { -+ pr_err("ERROR: v4l2 capture: slave not found!\n"); -+ retval = -ENODEV; -+ } -+ break; -+ } -+ -+ case VIDIOC_S_CTRL: -+ { -+ struct v4l2_control *vc = arg; -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(pxp_controls); i++) -+ if (vc->id == pxp_controls[i].id) { -+ if (vc->value < pxp_controls[i].minimum || -+ vc->value > pxp_controls[i].maximum) { -+ retval = -ERANGE; -+ break; -+ } -+ retval = pxp_set_cstate(cam, vc); -+ break; -+ } -+ -+ if (i >= ARRAY_SIZE(pxp_controls)) -+ retval = -EINVAL; -+ break; -+ -+ } -+ case VIDIOC_G_CTRL: -+ { -+ struct v4l2_control *vc = arg; -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(pxp_controls); i++) -+ if (vc->id == pxp_controls[i].id) { -+ retval = pxp_get_cstate(cam, vc); -+ break; -+ } -+ -+ if (i >= ARRAY_SIZE(pxp_controls)) -+ retval = -EINVAL; -+ break; -+ } -+ case VIDIOC_QUERYCTRL: -+ { -+ struct v4l2_queryctrl *qc = arg; -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(pxp_controls); i++) -+ if (qc->id && qc->id == pxp_controls[i].id) { -+ memcpy(qc, &(pxp_controls[i]), sizeof(*qc)); -+ break; -+ } -+ -+ if (i >= ARRAY_SIZE(pxp_controls)) -+ retval = -EINVAL; -+ break; -+ } -+ case VIDIOC_G_STD: -+ case VIDIOC_G_OUTPUT: -+ case VIDIOC_S_OUTPUT: -+ case VIDIOC_ENUMSTD: -+ case VIDIOC_S_STD: -+ case VIDIOC_TRY_FMT: -+ case VIDIOC_ENUMINPUT: -+ case VIDIOC_G_INPUT: -+ case VIDIOC_S_INPUT: -+ case VIDIOC_G_TUNER: -+ case VIDIOC_S_TUNER: -+ case VIDIOC_G_FREQUENCY: -+ case VIDIOC_S_FREQUENCY: -+ case VIDIOC_ENUMOUTPUT: -+ default: -+ pr_debug(" case not supported\n"); -+ retval = -EINVAL; -+ break; -+ } -+ -+ if (ioctlnr != VIDIOC_DQBUF) -+ up(&cam->busy_lock); -+ return retval; -+} -+ -+/* -+ * V4L interface - ioctl function -+ * -+ * @return None -+ */ -+static long csi_v4l_ioctl(struct file *file, -+ unsigned int cmd, unsigned long arg) -+{ -+ return video_usercopy(file, cmd, arg, csi_v4l_do_ioctl); -+} -+ -+/*! -+ * V4L interface - mmap function -+ * -+ * @param file structure file * -+ * -+ * @param vma structure vm_area_struct * -+ * -+ * @return status 0 Success, EINTR busy lock error, ENOBUFS remap_page error -+ */ -+static int csi_mmap(struct file *file, struct vm_area_struct *vma) -+{ -+ struct video_device *dev = video_devdata(file); -+ unsigned long size; -+ int res = 0; -+ cam_data *cam = video_get_drvdata(dev); -+ -+ pr_debug("%s\n", __func__); -+ pr_debug("\npgoff=0x%lx, start=0x%lx, end=0x%lx\n", -+ vma->vm_pgoff, vma->vm_start, vma->vm_end); -+ -+ /* make this _really_ smp-safe */ -+ if (down_interruptible(&cam->busy_lock)) -+ return -EINTR; -+ -+ size = vma->vm_end - vma->vm_start; -+ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); -+ -+ if (remap_pfn_range(vma, vma->vm_start, -+ vma->vm_pgoff, size, vma->vm_page_prot)) { -+ pr_err("ERROR: v4l2 capture: %s : " -+ "remap_pfn_range failed\n", __func__); -+ res = -ENOBUFS; -+ goto csi_mmap_exit; -+ } -+ -+ vma->vm_flags &= ~VM_IO; /* using shared anonymous pages */ -+ -+csi_mmap_exit: -+ up(&cam->busy_lock); -+ return res; -+} -+ -+/*! -+ * This structure defines the functions to be called in this driver. -+ */ -+static struct v4l2_file_operations csi_v4l_fops = { -+ .owner = THIS_MODULE, -+ .open = csi_v4l_open, -+ .release = csi_v4l_close, -+ .read = csi_v4l_read, -+ .ioctl = csi_v4l_ioctl, -+ .mmap = csi_mmap, -+}; -+ -+static struct video_device csi_v4l_template = { -+ .name = "Mx25 Camera", -+ .fops = &csi_v4l_fops, -+ .release = video_device_release, -+}; -+ -+/*! -+ * initialize cam_data structure -+ * -+ * @param cam structure cam_data * -+ * -+ * @return status 0 Success -+ */ -+static void init_camera_struct(cam_data *cam) -+{ -+ struct pxp_proc_data *proc_data = &cam->pxp_conf.proc_data; -+ pr_debug("In MVC: %s\n", __func__); -+ -+ proc_data->hflip = 0; -+ proc_data->vflip = 0; -+ proc_data->rotate = 0; -+ proc_data->bgcolor = 0; -+ -+ /* Default everything to 0 */ -+ memset(cam, 0, sizeof(cam_data)); -+ -+ sema_init(&cam->param_lock, 1); -+ sema_init(&cam->busy_lock, 1); -+ -+ cam->video_dev = video_device_alloc(); -+ if (cam->video_dev == NULL) -+ return; -+ -+ *(cam->video_dev) = csi_v4l_template; -+ -+ video_set_drvdata(cam->video_dev, cam); -+ cam->video_dev->minor = -1; -+ -+ init_waitqueue_head(&cam->enc_queue); -+ init_waitqueue_head(&cam->still_queue); -+ -+ cam->streamparm.parm.capture.capturemode = 0; -+ -+ cam->standard.index = 0; -+ cam->standard.id = V4L2_STD_UNKNOWN; -+ cam->standard.frameperiod.denominator = 30; -+ cam->standard.frameperiod.numerator = 1; -+ cam->standard.framelines = 480; -+ cam->standard_autodetect = true; -+ cam->streamparm.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; -+ cam->streamparm.parm.capture.timeperframe = cam->standard.frameperiod; -+ cam->streamparm.parm.capture.capability = V4L2_CAP_TIMEPERFRAME; -+ cam->overlay_on = false; -+ cam->capture_on = false; -+ cam->v4l2_fb.flags = V4L2_FBUF_FLAG_OVERLAY; -+ -+ cam->v2f.fmt.pix.sizeimage = 480 * 640 * 2; -+ cam->v2f.fmt.pix.bytesperline = 640 * 2; -+ cam->v2f.fmt.pix.width = 640; -+ cam->v2f.fmt.pix.height = 480; -+ cam->v2f.fmt.pix.pixelformat = V4L2_PIX_FMT_UYVY; -+ cam->win.w.width = 160; -+ cam->win.w.height = 160; -+ cam->win.w.left = 0; -+ cam->win.w.top = 0; -+ cam->still_counter = 0; -+ /* setup cropping */ -+ cam->crop_bounds.left = 0; -+ cam->crop_bounds.width = 640; -+ cam->crop_bounds.top = 0; -+ cam->crop_bounds.height = 480; -+ cam->crop_current = cam->crop_defrect = cam->crop_bounds; -+ -+ cam->enc_callback = camera_callback; -+ csi_start_callback(cam); -+ init_waitqueue_head(&cam->power_queue); -+ spin_lock_init(&cam->queue_int_lock); -+ spin_lock_init(&cam->dqueue_int_lock); -+} -+ -+/*! -+ * camera_power function -+ * Turns Sensor power On/Off -+ * -+ * @param cam cam data struct -+ * @param cameraOn true to turn camera on, false to turn off power. -+ * -+ * @return status -+ */ -+static u8 camera_power(cam_data *cam, bool cameraOn) -+{ -+ pr_debug("In MVC: %s on=%d\n", __func__, cameraOn); -+ -+ if (cameraOn == true) { -+ vidioc_int_s_power(cam->sensor, 1); -+ } else { -+ vidioc_int_s_power(cam->sensor, 0); -+ } -+ return 0; -+} -+ -+static const struct of_device_id imx_csi_v4l2_dt_ids[] = { -+ { .compatible = "fsl,imx6sl-csi-v4l2", }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, imx_csi_v4l2_dt_ids); -+ -+static int csi_v4l2_probe(struct platform_device *pdev) -+{ -+ struct scatterlist *sg; -+ u8 err = 0; -+ -+ /* Create g_cam and initialize it. */ -+ g_cam = kmalloc(sizeof(cam_data), GFP_KERNEL); -+ if (g_cam == NULL) { -+ pr_err("ERROR: v4l2 capture: failed to register camera\n"); -+ err = -ENOMEM; -+ goto out; -+ } -+ memset(&crop_current, 0, sizeof(crop_current)); -+ memset(&win_current, 0, sizeof(win_current)); -+ init_camera_struct(g_cam); -+ platform_set_drvdata(pdev, (void *)g_cam); -+ -+ /* Set up the v4l2 device and register it */ -+ csi_v4l2_int_device.priv = g_cam; -+ /* This function contains a bug that won't let this be rmmod'd. */ -+ v4l2_int_device_register(&csi_v4l2_int_device); -+ -+ /* register v4l video device */ -+ if (video_register_device(g_cam->video_dev, VFL_TYPE_GRABBER, video_nr) -+ == -1) { -+ kfree(g_cam); -+ g_cam = NULL; -+ pr_err("ERROR: v4l2 capture: video_register_device failed\n"); -+ err = -ENODEV; -+ goto out; -+ } -+ pr_debug(" Video device registered: %s #%d\n", -+ g_cam->video_dev->name, g_cam->video_dev->minor); -+ -+ g_cam->pxp_chan = NULL; -+ /* Initialize Scatter-gather list containing 2 buffer addresses. */ -+ sg = g_cam->sg; -+ sg_init_table(sg, 2); -+ -+out: -+ return err; -+} -+ -+static int csi_v4l2_remove(struct platform_device *pdev) -+{ -+ if (g_cam->open_count) { -+ pr_err("ERROR: v4l2 capture:camera open " -+ "-- setting ops to NULL\n"); -+ } else { -+ pr_info("V4L2 freeing image input device\n"); -+ v4l2_int_device_unregister(&csi_v4l2_int_device); -+ csi_stop_callback(g_cam); -+ video_unregister_device(g_cam->video_dev); -+ platform_set_drvdata(pdev, NULL); -+ -+ kfree(g_cam); -+ g_cam = NULL; -+ } -+ -+ return 0; -+} -+ -+/*! -+ * This function is called to put the sensor in a low power state. -+ * Refer to the document driver-model/driver.txt in the kernel source tree -+ * for more information. -+ * -+ * @param pdev the device structure used to give information on which I2C -+ * to suspend -+ * @param state the power state the device is entering -+ * -+ * @return The function returns 0 on success and -1 on failure. -+ */ -+static int csi_v4l2_suspend(struct platform_device *pdev, pm_message_t state) -+{ -+ cam_data *cam = platform_get_drvdata(pdev); -+ -+ pr_debug("In MVC: %s\n", __func__); -+ -+ if (cam == NULL) -+ return -1; -+ -+ cam->low_power = true; -+ -+ if (cam->overlay_on == true) -+ stop_preview(cam); -+ -+ if (cam->capture_on == true || cam->overlay_on == true) -+ camera_power(cam, false); -+ -+ return 0; -+} -+ -+/*! -+ * This function is called to bring the sensor back from a low power state. -+ * Refer to the document driver-model/driver.txt in the kernel source tree -+ * for more information. -+ * -+ * @param pdev the device structure -+ * -+ * @return The function returns 0 on success and -1 on failure -+ */ -+static int csi_v4l2_resume(struct platform_device *pdev) -+{ -+ cam_data *cam = platform_get_drvdata(pdev); -+ -+ pr_debug("In MVC: %s\n", __func__); -+ -+ if (cam == NULL) -+ return -1; -+ -+ cam->low_power = false; -+ wake_up_interruptible(&cam->power_queue); -+ if (cam->capture_on == true || cam->overlay_on == true) -+ camera_power(cam, true); -+ -+ if (cam->overlay_on == true) -+ start_preview(cam); -+ -+ return 0; -+} -+ -+/*! -+ * This structure contains pointers to the power management callback functions. -+ */ -+static struct platform_driver csi_v4l2_driver = { -+ .driver = { -+ .name = "csi_v4l2", -+ .of_match_table = of_match_ptr(imx_csi_v4l2_dt_ids), -+ }, -+ .probe = csi_v4l2_probe, -+ .remove = csi_v4l2_remove, -+#ifdef CONFIG_PM -+ .suspend = csi_v4l2_suspend, -+ .resume = csi_v4l2_resume, -+#endif -+ .shutdown = NULL, -+}; -+ -+/*! -+ * Initializes the camera driver. -+ */ -+static int csi_v4l2_master_attach(struct v4l2_int_device *slave) -+{ -+ cam_data *cam = slave->u.slave->master->priv; -+ struct v4l2_format cam_fmt; -+ -+ pr_debug("In MVC: %s\n", __func__); -+ pr_debug(" slave.name = %s\n", slave->name); -+ pr_debug(" master.name = %s\n", slave->u.slave->master->name); -+ -+ cam->sensor = slave; -+ if (slave == NULL) { -+ pr_err("ERROR: v4l2 capture: slave parameter not valid.\n"); -+ return -1; -+ } -+ -+ cam_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; -+ vidioc_int_g_fmt_cap(cam->sensor, &cam_fmt); -+ -+ /* Used to detect TV in (type 1) vs. camera (type 0) */ -+ cam->device_type = cam_fmt.fmt.pix.priv; -+ -+ cam->crop_bounds.top = cam->crop_bounds.left = 0; -+ cam->crop_bounds.width = cam_fmt.fmt.pix.width; -+ cam->crop_bounds.height = cam_fmt.fmt.pix.height; -+ -+ /* This also is the max crop size for this device. */ -+ cam->crop_defrect.top = cam->crop_defrect.left = 0; -+ cam->crop_defrect.width = cam_fmt.fmt.pix.width; -+ cam->crop_defrect.height = cam_fmt.fmt.pix.height; -+ -+ /* At this point, this is also the current image size. */ -+ cam->crop_current.top = cam->crop_current.left = 0; -+ cam->crop_current.width = cam_fmt.fmt.pix.width; -+ cam->crop_current.height = cam_fmt.fmt.pix.height; -+ -+ pr_debug("End of %s: v2f pix widthxheight %d x %d\n", -+ __func__, cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height); -+ -+ return 0; -+} -+ -+/*! -+ * Disconnects the camera driver. -+ */ -+static void csi_v4l2_master_detach(struct v4l2_int_device *slave) -+{ -+ pr_debug("In MVC: %s\n", __func__); -+ -+ vidioc_int_dev_exit(slave); -+} -+ -+module_platform_driver(csi_v4l2_driver); -+ -+module_param(video_nr, int, 0444); -+MODULE_AUTHOR("Freescale Semiconductor, Inc."); -+MODULE_DESCRIPTION("V4L2 capture driver for Mx25 based cameras"); -+MODULE_LICENSE("GPL"); -+MODULE_SUPPORTED_DEVICE("video"); -diff -Nur linux-4.1.13.orig/drivers/media/platform/mxc/capture/fsl_csi.c linux-4.1.13/drivers/media/platform/mxc/capture/fsl_csi.c ---- linux-4.1.13.orig/drivers/media/platform/mxc/capture/fsl_csi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/media/platform/mxc/capture/fsl_csi.c 2015-11-30 17:56:13.600136395 +0100 -@@ -0,0 +1,302 @@ -+/* -+ * Copyright 2009-2013 Freescale Semiconductor, Inc. All Rights Reserved. -+ */ -+ -+/* -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/*! -+ * @file fsl_csi.c, this file is derived from mx27_csi.c -+ * -+ * @brief mx25 CMOS Sensor interface functions -+ * -+ * @ingroup CSI -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "mxc_v4l2_capture.h" -+#include "fsl_csi.h" -+ -+void __iomem *csi_regbase; -+EXPORT_SYMBOL(csi_regbase); -+static int irq_nr; -+static csi_irq_callback_t g_callback; -+static void *g_callback_data; -+ -+static irqreturn_t csi_irq_handler(int irq, void *data) -+{ -+ cam_data *cam = (cam_data *) data; -+ unsigned long status = __raw_readl(CSI_CSISR); -+ -+ __raw_writel(status, CSI_CSISR); -+ -+ if (status & BIT_HRESP_ERR_INT) -+ pr_warning("Hresponse error is detected.\n"); -+ -+ if (status & BIT_DMA_TSF_DONE_FB1) { -+ if (cam->capture_on) { -+ spin_lock(&cam->queue_int_lock); -+ cam->ping_pong_csi = 1; -+ spin_unlock(&cam->queue_int_lock); -+ cam->enc_callback(0, cam); -+ } else { -+ cam->still_counter++; -+ wake_up_interruptible(&cam->still_queue); -+ } -+ } -+ -+ if (status & BIT_DMA_TSF_DONE_FB2) { -+ if (cam->capture_on) { -+ spin_lock(&cam->queue_int_lock); -+ cam->ping_pong_csi = 2; -+ spin_unlock(&cam->queue_int_lock); -+ cam->enc_callback(0, cam); -+ } else { -+ cam->still_counter++; -+ wake_up_interruptible(&cam->still_queue); -+ } -+ } -+ -+ if (g_callback) -+ g_callback(g_callback_data, status); -+ -+ pr_debug("CSI status = 0x%08lX\n", status); -+ -+ return IRQ_HANDLED; -+} -+ -+static void csihw_reset_frame_count(void) -+{ -+ __raw_writel(__raw_readl(CSI_CSICR3) | BIT_FRMCNT_RST, CSI_CSICR3); -+} -+ -+static void csihw_reset(void) -+{ -+ csihw_reset_frame_count(); -+ __raw_writel(CSICR1_RESET_VAL, CSI_CSICR1); -+ __raw_writel(CSICR2_RESET_VAL, CSI_CSICR2); -+ __raw_writel(CSICR3_RESET_VAL, CSI_CSICR3); -+} -+ -+/*! -+ * csi_init_interface -+ * Init csi interface -+ */ -+void csi_init_interface(void) -+{ -+ unsigned int val = 0; -+ unsigned int imag_para; -+ -+ val |= BIT_SOF_POL; -+ val |= BIT_REDGE; -+ val |= BIT_GCLK_MODE; -+ val |= BIT_HSYNC_POL; -+ val |= BIT_PACK_DIR; -+ val |= BIT_FCC; -+ val |= BIT_SWAP16_EN; -+ val |= 1 << SHIFT_MCLKDIV; -+ val |= BIT_MCLKEN; -+ __raw_writel(val, CSI_CSICR1); -+ -+ imag_para = (640 << 16) | 960; -+ __raw_writel(imag_para, CSI_CSIIMAG_PARA); -+ -+ val = 0x1010; -+ val |= BIT_DMA_REFLASH_RFF; -+ __raw_writel(val, CSI_CSICR3); -+} -+EXPORT_SYMBOL(csi_init_interface); -+ -+void csi_init_format(int fmt) -+{ -+ unsigned int val; -+ -+ val = __raw_readl(CSI_CSICR1); -+ if (fmt == V4L2_PIX_FMT_YUYV) { -+ val &= ~BIT_PACK_DIR; -+ val &= ~BIT_SWAP16_EN; -+ } else if (fmt == V4L2_PIX_FMT_UYVY) { -+ val |= BIT_PACK_DIR; -+ val |= BIT_SWAP16_EN; -+ } else -+ pr_warning("unsupported format, old format remains.\n"); -+ -+ __raw_writel(val, CSI_CSICR1); -+} -+EXPORT_SYMBOL(csi_init_format); -+ -+/*! -+ * csi_read_mclk_flag -+ * -+ * @return gcsi_mclk_source -+ */ -+int csi_read_mclk_flag(void) -+{ -+ return 0; -+} -+EXPORT_SYMBOL(csi_read_mclk_flag); -+ -+void csi_start_callback(void *data) -+{ -+ cam_data *cam = (cam_data *) data; -+ -+ if (request_irq(irq_nr, csi_irq_handler, 0, "csi", cam) < 0) -+ pr_debug("CSI error: irq request fail\n"); -+ -+} -+EXPORT_SYMBOL(csi_start_callback); -+ -+void csi_stop_callback(void *data) -+{ -+ cam_data *cam = (cam_data *) data; -+ -+ free_irq(irq_nr, cam); -+} -+EXPORT_SYMBOL(csi_stop_callback); -+ -+void csi_enable_int(int arg) -+{ -+ unsigned long cr1 = __raw_readl(CSI_CSICR1); -+ -+ cr1 |= BIT_SOF_INTEN; -+ if (arg == 1) { -+ /* still capture needs DMA intterrupt */ -+ cr1 |= BIT_FB1_DMA_DONE_INTEN; -+ cr1 |= BIT_FB2_DMA_DONE_INTEN; -+ } -+ __raw_writel(cr1, CSI_CSICR1); -+} -+EXPORT_SYMBOL(csi_enable_int); -+ -+void csi_disable_int(void) -+{ -+ unsigned long cr1 = __raw_readl(CSI_CSICR1); -+ -+ cr1 &= ~BIT_SOF_INTEN; -+ cr1 &= ~BIT_FB1_DMA_DONE_INTEN; -+ cr1 &= ~BIT_FB2_DMA_DONE_INTEN; -+ __raw_writel(cr1, CSI_CSICR1); -+} -+EXPORT_SYMBOL(csi_disable_int); -+ -+void csi_set_16bit_imagpara(int width, int height) -+{ -+ int imag_para = 0; -+ unsigned long cr3 = __raw_readl(CSI_CSICR3); -+ -+ imag_para = (width << 16) | (height * 2); -+ __raw_writel(imag_para, CSI_CSIIMAG_PARA); -+ -+ /* reflash the embeded DMA controller */ -+ __raw_writel(cr3 | BIT_DMA_REFLASH_RFF, CSI_CSICR3); -+} -+EXPORT_SYMBOL(csi_set_16bit_imagpara); -+ -+void csi_set_12bit_imagpara(int width, int height) -+{ -+ int imag_para = 0; -+ unsigned long cr3 = __raw_readl(CSI_CSICR3); -+ -+ imag_para = (width << 16) | (height * 3 / 2); -+ __raw_writel(imag_para, CSI_CSIIMAG_PARA); -+ -+ /* reflash the embeded DMA controller */ -+ __raw_writel(cr3 | BIT_DMA_REFLASH_RFF, CSI_CSICR3); -+} -+EXPORT_SYMBOL(csi_set_12bit_imagpara); -+ -+void csi_dmareq_rff_enable(void) -+{ -+ unsigned long cr3 = __raw_readl(CSI_CSICR3); -+ -+ cr3 |= BIT_DMA_REQ_EN_RFF; -+ cr3 |= BIT_HRESP_ERR_EN; -+ __raw_writel(cr3, CSI_CSICR3); -+} -+EXPORT_SYMBOL(csi_dmareq_rff_enable); -+ -+void csi_dmareq_rff_disable(void) -+{ -+ unsigned long cr3 = __raw_readl(CSI_CSICR3); -+ -+ cr3 &= ~BIT_DMA_REQ_EN_RFF; -+ cr3 &= ~BIT_HRESP_ERR_EN; -+ __raw_writel(cr3, CSI_CSICR3); -+} -+EXPORT_SYMBOL(csi_dmareq_rff_disable); -+ -+static const struct of_device_id fsl_csi_dt_ids[] = { -+ { .compatible = "fsl,imx6sl-csi", }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, fsl_csi_dt_ids); -+ -+static int csi_probe(struct platform_device *pdev) -+{ -+ int ret = 0; -+ struct resource *res; -+ -+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); -+ if (!res) { -+ dev_err(&pdev->dev, "No csi irq found.\n"); -+ ret = -ENODEV; -+ goto err; -+ } -+ irq_nr = res->start; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!res) { -+ dev_err(&pdev->dev, "No csi base address found.\n"); -+ ret = -ENODEV; -+ goto err; -+ } -+ csi_regbase = devm_ioremap(&pdev->dev, res->start, resource_size(res)); -+ if (!csi_regbase) { -+ dev_err(&pdev->dev, "ioremap failed with csi base\n"); -+ ret = -ENOMEM; -+ goto err; -+ } -+ -+ csihw_reset(); -+ csi_init_interface(); -+ csi_dmareq_rff_disable(); -+ -+err: -+ return ret; -+} -+ -+static int csi_remove(struct platform_device *pdev) -+{ -+ return 0; -+} -+ -+static struct platform_driver csi_driver = { -+ .driver = { -+ .name = "fsl_csi", -+ .of_match_table = of_match_ptr(fsl_csi_dt_ids), -+ }, -+ .probe = csi_probe, -+ .remove = csi_remove, -+}; -+ -+module_platform_driver(csi_driver); -+ -+MODULE_AUTHOR("Freescale Semiconductor, Inc."); -+MODULE_DESCRIPTION("fsl CSI driver"); -+MODULE_LICENSE("GPL"); -diff -Nur linux-4.1.13.orig/drivers/media/platform/mxc/capture/fsl_csi.h linux-4.1.13/drivers/media/platform/mxc/capture/fsl_csi.h ---- linux-4.1.13.orig/drivers/media/platform/mxc/capture/fsl_csi.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/media/platform/mxc/capture/fsl_csi.h 2015-11-30 17:56:13.600136395 +0100 -@@ -0,0 +1,198 @@ -+/* -+ * Copyright 2009-2013 Freescale Semiconductor, Inc. All Rights Reserved. -+ */ -+ -+/* -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/*! -+ * @file fsl_csi.h -+ * -+ * @brief mx25 CMOS Sensor interface functions -+ * -+ * @ingroup CSI -+ */ -+ -+#ifndef MX25_CSI_H -+#define MX25_CSI_H -+ -+#include -+ -+/* reset values */ -+#define CSICR1_RESET_VAL 0x40000800 -+#define CSICR2_RESET_VAL 0x0 -+#define CSICR3_RESET_VAL 0x0 -+ -+/* csi control reg 1 */ -+#define BIT_SWAP16_EN (0x1 << 31) -+#define BIT_EXT_VSYNC (0x1 << 30) -+#define BIT_EOF_INT_EN (0x1 << 29) -+#define BIT_PRP_IF_EN (0x1 << 28) -+#define BIT_CCIR_MODE (0x1 << 27) -+#define BIT_COF_INT_EN (0x1 << 26) -+#define BIT_SF_OR_INTEN (0x1 << 25) -+#define BIT_RF_OR_INTEN (0x1 << 24) -+#define BIT_SFF_DMA_DONE_INTEN (0x1 << 22) -+#define BIT_STATFF_INTEN (0x1 << 21) -+#define BIT_FB2_DMA_DONE_INTEN (0x1 << 20) -+#define BIT_FB1_DMA_DONE_INTEN (0x1 << 19) -+#define BIT_RXFF_INTEN (0x1 << 18) -+#define BIT_SOF_POL (0x1 << 17) -+#define BIT_SOF_INTEN (0x1 << 16) -+#define BIT_MCLKDIV (0xF << 12) -+#define BIT_HSYNC_POL (0x1 << 11) -+#define BIT_CCIR_EN (0x1 << 10) -+#define BIT_MCLKEN (0x1 << 9) -+#define BIT_FCC (0x1 << 8) -+#define BIT_PACK_DIR (0x1 << 7) -+#define BIT_CLR_STATFIFO (0x1 << 6) -+#define BIT_CLR_RXFIFO (0x1 << 5) -+#define BIT_GCLK_MODE (0x1 << 4) -+#define BIT_INV_DATA (0x1 << 3) -+#define BIT_INV_PCLK (0x1 << 2) -+#define BIT_REDGE (0x1 << 1) -+#define BIT_PIXEL_BIT (0x1 << 0) -+ -+#define SHIFT_MCLKDIV 12 -+ -+/* control reg 3 */ -+#define BIT_FRMCNT (0xFFFF << 16) -+#define BIT_FRMCNT_RST (0x1 << 15) -+#define BIT_DMA_REFLASH_RFF (0x1 << 14) -+#define BIT_DMA_REFLASH_SFF (0x1 << 13) -+#define BIT_DMA_REQ_EN_RFF (0x1 << 12) -+#define BIT_DMA_REQ_EN_SFF (0x1 << 11) -+#define BIT_STATFF_LEVEL (0x7 << 8) -+#define BIT_HRESP_ERR_EN (0x1 << 7) -+#define BIT_RXFF_LEVEL (0x7 << 4) -+#define BIT_TWO_8BIT_SENSOR (0x1 << 3) -+#define BIT_ZERO_PACK_EN (0x1 << 2) -+#define BIT_ECC_INT_EN (0x1 << 1) -+#define BIT_ECC_AUTO_EN (0x1 << 0) -+ -+#define SHIFT_FRMCNT 16 -+ -+/* csi status reg */ -+#define BIT_SFF_OR_INT (0x1 << 25) -+#define BIT_RFF_OR_INT (0x1 << 24) -+#define BIT_DMA_TSF_DONE_SFF (0x1 << 22) -+#define BIT_STATFF_INT (0x1 << 21) -+#define BIT_DMA_TSF_DONE_FB2 (0x1 << 20) -+#define BIT_DMA_TSF_DONE_FB1 (0x1 << 19) -+#define BIT_RXFF_INT (0x1 << 18) -+#define BIT_EOF_INT (0x1 << 17) -+#define BIT_SOF_INT (0x1 << 16) -+#define BIT_F2_INT (0x1 << 15) -+#define BIT_F1_INT (0x1 << 14) -+#define BIT_COF_INT (0x1 << 13) -+#define BIT_HRESP_ERR_INT (0x1 << 7) -+#define BIT_ECC_INT (0x1 << 1) -+#define BIT_DRDY (0x1 << 0) -+ -+#define CSI_MCLK_VF 1 -+#define CSI_MCLK_ENC 2 -+#define CSI_MCLK_RAW 4 -+#define CSI_MCLK_I2C 8 -+#endif -+ -+extern void __iomem *csi_regbase; -+#define CSI_CSICR1 (csi_regbase) -+#define CSI_CSICR2 (csi_regbase + 0x4) -+#define CSI_CSICR3 (csi_regbase + 0x8) -+#define CSI_STATFIFO (csi_regbase + 0xC) -+#define CSI_CSIRXFIFO (csi_regbase + 0x10) -+#define CSI_CSIRXCNT (csi_regbase + 0x14) -+#define CSI_CSISR (csi_regbase + 0x18) -+ -+#define CSI_CSIDBG (csi_regbase + 0x1C) -+#define CSI_CSIDMASA_STATFIFO (csi_regbase + 0x20) -+#define CSI_CSIDMATS_STATFIFO (csi_regbase + 0x24) -+#define CSI_CSIDMASA_FB1 (csi_regbase + 0x28) -+#define CSI_CSIDMASA_FB2 (csi_regbase + 0x2C) -+#define CSI_CSIFBUF_PARA (csi_regbase + 0x30) -+#define CSI_CSIIMAG_PARA (csi_regbase + 0x34) -+ -+static inline void csi_clear_status(unsigned long status) -+{ -+ __raw_writel(status, CSI_CSISR); -+} -+ -+struct csi_signal_cfg_t { -+ unsigned data_width:3; -+ unsigned clk_mode:2; -+ unsigned ext_vsync:1; -+ unsigned Vsync_pol:1; -+ unsigned Hsync_pol:1; -+ unsigned pixclk_pol:1; -+ unsigned data_pol:1; -+ unsigned sens_clksrc:1; -+}; -+ -+struct csi_config_t { -+ /* control reg 1 */ -+ unsigned int swap16_en:1; -+ unsigned int ext_vsync:1; -+ unsigned int eof_int_en:1; -+ unsigned int prp_if_en:1; -+ unsigned int ccir_mode:1; -+ unsigned int cof_int_en:1; -+ unsigned int sf_or_inten:1; -+ unsigned int rf_or_inten:1; -+ unsigned int sff_dma_done_inten:1; -+ unsigned int statff_inten:1; -+ unsigned int fb2_dma_done_inten:1; -+ unsigned int fb1_dma_done_inten:1; -+ unsigned int rxff_inten:1; -+ unsigned int sof_pol:1; -+ unsigned int sof_inten:1; -+ unsigned int mclkdiv:4; -+ unsigned int hsync_pol:1; -+ unsigned int ccir_en:1; -+ unsigned int mclken:1; -+ unsigned int fcc:1; -+ unsigned int pack_dir:1; -+ unsigned int gclk_mode:1; -+ unsigned int inv_data:1; -+ unsigned int inv_pclk:1; -+ unsigned int redge:1; -+ unsigned int pixel_bit:1; -+ -+ /* control reg 3 */ -+ unsigned int frmcnt:16; -+ unsigned int frame_reset:1; -+ unsigned int dma_reflash_rff:1; -+ unsigned int dma_reflash_sff:1; -+ unsigned int dma_req_en_rff:1; -+ unsigned int dma_req_en_sff:1; -+ unsigned int statff_level:3; -+ unsigned int hresp_err_en:1; -+ unsigned int rxff_level:3; -+ unsigned int two_8bit_sensor:1; -+ unsigned int zero_pack_en:1; -+ unsigned int ecc_int_en:1; -+ unsigned int ecc_auto_en:1; -+ /* fifo counter */ -+ unsigned int rxcnt; -+}; -+ -+typedef void (*csi_irq_callback_t) (void *data, unsigned long status); -+ -+void csi_init_interface(void); -+void csi_init_format(int fmt); -+void csi_set_16bit_imagpara(int width, int height); -+void csi_set_12bit_imagpara(int width, int height); -+int csi_read_mclk_flag(void); -+void csi_start_callback(void *data); -+void csi_stop_callback(void *data); -+void csi_enable_int(int arg); -+void csi_disable_int(void); -+void csi_mclk_enable(void); -+void csi_mclk_disable(void); -+void csi_dmareq_rff_enable(void); -+void csi_dmareq_rff_disable(void); -diff -Nur linux-4.1.13.orig/drivers/media/platform/mxc/capture/ipu_bg_overlay_sdc.c linux-4.1.13/drivers/media/platform/mxc/capture/ipu_bg_overlay_sdc.c ---- linux-4.1.13.orig/drivers/media/platform/mxc/capture/ipu_bg_overlay_sdc.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/media/platform/mxc/capture/ipu_bg_overlay_sdc.c 2015-11-30 17:56:13.600136395 +0100 -@@ -0,0 +1,493 @@ -+ -+/* -+ * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved. -+ */ -+ -+/* -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/*! -+ * @file ipu_bg_overlay_sdc_bg.c -+ * -+ * @brief IPU Use case for PRP-VF back-ground -+ * -+ * @ingroup IPU -+ */ -+#include -+#include -+#include -+#include -+#include -+#include "mxc_v4l2_capture.h" -+#include "ipu_prp_sw.h" -+ -+static int csi_buffer_num; -+static u32 bpp, csi_mem_bufsize = 3; -+static u32 out_format; -+static struct ipu_soc *disp_ipu; -+static u32 offset; -+ -+static void csi_buf_work_func(struct work_struct *work) -+{ -+ int err = 0; -+ cam_data *cam = -+ container_of(work, struct _cam_data, csi_work_struct); -+ -+ struct ipu_task task; -+ memset(&task, 0, sizeof(task)); -+ -+ if (csi_buffer_num) -+ task.input.paddr = cam->vf_bufs[0]; -+ else -+ task.input.paddr = cam->vf_bufs[1]; -+ task.input.width = cam->crop_current.width; -+ task.input.height = cam->crop_current.height; -+ task.input.format = IPU_PIX_FMT_UYVY; -+ -+ task.output.paddr = offset; -+ task.output.width = cam->overlay_fb->var.xres; -+ task.output.height = cam->overlay_fb->var.yres; -+ task.output.format = out_format; -+ task.output.rotate = cam->rotation; -+ task.output.crop.pos.x = cam->win.w.left; -+ task.output.crop.pos.y = cam->win.w.top; -+ if (cam->win.w.width > 1024 || cam->win.w.height > 1024) { -+ task.output.crop.w = cam->overlay_fb->var.xres; -+ task.output.crop.h = cam->overlay_fb->var.yres; -+ } else { -+ task.output.crop.w = cam->win.w.width; -+ task.output.crop.h = cam->win.w.height; -+ } -+again: -+ err = ipu_check_task(&task); -+ if (err != IPU_CHECK_OK) { -+ if (err > IPU_CHECK_ERR_MIN) { -+ if (err == IPU_CHECK_ERR_SPLIT_INPUTW_OVER) { -+ task.input.crop.w -= 8; -+ goto again; -+ } -+ if (err == IPU_CHECK_ERR_SPLIT_INPUTH_OVER) { -+ task.input.crop.h -= 8; -+ goto again; -+ } -+ if (err == IPU_CHECK_ERR_SPLIT_OUTPUTW_OVER) { -+ task.output.width -= 8; -+ task.output.crop.w = task.output.width; -+ goto again; -+ } -+ if (err == IPU_CHECK_ERR_SPLIT_OUTPUTH_OVER) { -+ task.output.height -= 8; -+ task.output.crop.h = task.output.height; -+ goto again; -+ } -+ printk(KERN_ERR "check ipu taks fail\n"); -+ return; -+ } -+ printk(KERN_ERR "check ipu taks fail\n"); -+ return; -+ } -+ err = ipu_queue_task(&task); -+ if (err < 0) -+ printk(KERN_ERR "queue ipu task error\n"); -+} -+ -+static void get_disp_ipu(cam_data *cam) -+{ -+ if (cam->output > 2) -+ disp_ipu = ipu_get_soc(1); /* using DISP4 */ -+ else -+ disp_ipu = ipu_get_soc(0); -+} -+ -+ -+/*! -+ * csi ENC callback function. -+ * -+ * @param irq int irq line -+ * @param dev_id void * device id -+ * -+ * @return status IRQ_HANDLED for handled -+ */ -+static irqreturn_t csi_enc_callback(int irq, void *dev_id) -+{ -+ cam_data *cam = (cam_data *) dev_id; -+ -+ ipu_select_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER, csi_buffer_num); -+ schedule_work(&cam->csi_work_struct); -+ csi_buffer_num = (csi_buffer_num == 0) ? 1 : 0; -+ return IRQ_HANDLED; -+} -+ -+static int csi_enc_setup(cam_data *cam) -+{ -+ ipu_channel_params_t params; -+ u32 pixel_fmt; -+ int err = 0, sensor_protocol = 0; -+ -+ if (!cam) { -+ printk(KERN_ERR "cam private is NULL\n"); -+ return -ENXIO; -+ } -+ -+ memset(¶ms, 0, sizeof(ipu_channel_params_t)); -+ params.csi_mem.csi = cam->csi; -+ -+ sensor_protocol = ipu_csi_get_sensor_protocol(cam->ipu, cam->csi); -+ switch (sensor_protocol) { -+ case IPU_CSI_CLK_MODE_GATED_CLK: -+ case IPU_CSI_CLK_MODE_NONGATED_CLK: -+ case IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE: -+ case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR: -+ case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR: -+ params.csi_mem.interlaced = false; -+ break; -+ case IPU_CSI_CLK_MODE_CCIR656_INTERLACED: -+ case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR: -+ case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR: -+ params.csi_mem.interlaced = true; -+ break; -+ default: -+ printk(KERN_ERR "sensor protocol unsupported\n"); -+ return -EINVAL; -+ } -+ err = cam_mipi_csi2_enable(cam, ¶ms.csi_mem.mipi); -+ if (err) -+ return err; -+ -+ if (cam->vf_bufs_vaddr[0]) { -+ dma_free_coherent(0, cam->vf_bufs_size[0], -+ cam->vf_bufs_vaddr[0], -+ (dma_addr_t) cam->vf_bufs[0]); -+ } -+ if (cam->vf_bufs_vaddr[1]) { -+ dma_free_coherent(0, cam->vf_bufs_size[1], -+ cam->vf_bufs_vaddr[1], -+ (dma_addr_t) cam->vf_bufs[1]); -+ } -+ csi_mem_bufsize = -+ cam->crop_current.width * cam->crop_current.height * 2; -+ cam->vf_bufs_size[0] = PAGE_ALIGN(csi_mem_bufsize); -+ cam->vf_bufs_vaddr[0] = (void *)dma_alloc_coherent(0, -+ cam->vf_bufs_size[0], -+ (dma_addr_t *) & -+ cam->vf_bufs[0], -+ GFP_DMA | -+ GFP_KERNEL); -+ if (cam->vf_bufs_vaddr[0] == NULL) { -+ printk(KERN_ERR "Error to allocate vf buffer\n"); -+ err = -ENOMEM; -+ goto out_2; -+ } -+ cam->vf_bufs_size[1] = PAGE_ALIGN(csi_mem_bufsize); -+ cam->vf_bufs_vaddr[1] = (void *)dma_alloc_coherent(0, -+ cam->vf_bufs_size[1], -+ (dma_addr_t *) & -+ cam->vf_bufs[1], -+ GFP_DMA | -+ GFP_KERNEL); -+ if (cam->vf_bufs_vaddr[1] == NULL) { -+ printk(KERN_ERR "Error to allocate vf buffer\n"); -+ err = -ENOMEM; -+ goto out_1; -+ } -+ pr_debug("vf_bufs %x %x\n", cam->vf_bufs[0], cam->vf_bufs[1]); -+ -+ err = ipu_channel_request(cam->ipu, CSI_MEM, ¶ms, &cam->ipu_chan); -+ if (err) { -+ pr_err("%s:ipu_channel_request %d\n", __func__, err); -+ goto out_1; -+ } -+ -+ pixel_fmt = IPU_PIX_FMT_UYVY; -+ err = ipu_init_channel_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER, -+ pixel_fmt, cam->crop_current.width, -+ cam->crop_current.height, -+ cam->crop_current.width, IPU_ROTATE_NONE, -+ cam->vf_bufs[0], cam->vf_bufs[1], 0, -+ cam->offset.u_offset, cam->offset.u_offset); -+ if (err != 0) { -+ printk(KERN_ERR "CSI_MEM output buffer\n"); -+ goto out_1; -+ } -+ err = ipu_enable_channel(cam->ipu, CSI_MEM); -+ if (err < 0) { -+ printk(KERN_ERR "ipu_enable_channel CSI_MEM\n"); -+ goto out_1; -+ } -+ -+ csi_buffer_num = 0; -+ -+ ipu_select_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER, 0); -+ ipu_select_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER, 1); -+ return err; -+out_1: -+ if (cam->vf_bufs_vaddr[0]) { -+ dma_free_coherent(0, cam->vf_bufs_size[0], -+ cam->vf_bufs_vaddr[0], -+ (dma_addr_t) cam->vf_bufs[0]); -+ cam->vf_bufs_vaddr[0] = NULL; -+ cam->vf_bufs[0] = 0; -+ } -+ if (cam->vf_bufs_vaddr[1]) { -+ dma_free_coherent(0, cam->vf_bufs_size[1], -+ cam->vf_bufs_vaddr[1], -+ (dma_addr_t) cam->vf_bufs[1]); -+ cam->vf_bufs_vaddr[1] = NULL; -+ cam->vf_bufs[1] = 0; -+ } -+out_2: -+ return err; -+} -+ -+/*! -+ * Enable encoder task -+ * @param private struct cam_data * mxc capture instance -+ * -+ * @return status -+ */ -+static int csi_enc_enabling_tasks(void *private) -+{ -+ cam_data *cam = (cam_data *) private; -+ int err = 0; -+ -+ ipu_clear_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF); -+ err = ipu_request_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF, -+ csi_enc_callback, 0, "Mxc Camera", cam); -+ if (err != 0) { -+ printk(KERN_ERR "Error registering CSI0_OUT_EOF irq\n"); -+ return err; -+ } -+ -+ INIT_WORK(&cam->csi_work_struct, csi_buf_work_func); -+ -+ err = csi_enc_setup(cam); -+ if (err != 0) { -+ printk(KERN_ERR "csi_enc_setup %d\n", err); -+ goto out1; -+ } -+ -+ return err; -+out1: -+ ipu_free_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF, cam); -+ return err; -+} -+ -+/*! -+ * bg_overlay_start - start the overlay task -+ * -+ * @param private cam_data * mxc v4l2 main structure -+ * -+ */ -+static int bg_overlay_start(void *private) -+{ -+ cam_data *cam = (cam_data *) private; -+ int err = 0; -+ -+ if (!cam) { -+ printk(KERN_ERR "private is NULL\n"); -+ return -EIO; -+ } -+ -+ if (cam->overlay_active == true) { -+ pr_debug("already start.\n"); -+ return 0; -+ } -+ -+ get_disp_ipu(cam); -+ -+ out_format = cam->v4l2_fb.fmt.pixelformat; -+ if (cam->v4l2_fb.fmt.pixelformat == IPU_PIX_FMT_BGR24) { -+ bpp = 3, csi_mem_bufsize = 3; -+ pr_info("BGR24\n"); -+ } else if (cam->v4l2_fb.fmt.pixelformat == IPU_PIX_FMT_RGB565) { -+ bpp = 2, csi_mem_bufsize = 2; -+ pr_info("RGB565\n"); -+ } else if (cam->v4l2_fb.fmt.pixelformat == IPU_PIX_FMT_BGR32) { -+ bpp = 4, csi_mem_bufsize = 4; -+ pr_info("BGR32\n"); -+ } else { -+ printk(KERN_ERR -+ "unsupported fix format from the framebuffer.\n"); -+ return -EINVAL; -+ } -+ -+ offset = cam->v4l2_fb.fmt.bytesperline * cam->win.w.top + -+ csi_mem_bufsize * cam->win.w.left; -+ -+ if (cam->v4l2_fb.base == 0) -+ printk(KERN_ERR "invalid frame buffer address.\n"); -+ else -+ offset += (u32) cam->v4l2_fb.base; -+ -+ csi_mem_bufsize = cam->win.w.width * cam->win.w.height -+ * csi_mem_bufsize; -+ -+ err = csi_enc_enabling_tasks(cam); -+ if (err != 0) { -+ printk(KERN_ERR "Error csi enc enable fail\n"); -+ return err; -+ } -+ -+ cam->overlay_active = true; -+ return err; -+} -+ -+/*! -+ * bg_overlay_stop - stop the overlay task -+ * -+ * @param private cam_data * mxc v4l2 main structure -+ * -+ */ -+static int bg_overlay_stop(void *private) -+{ -+ int err = 0; -+ int err2 = 0; -+ cam_data *cam = (cam_data *) private; -+ -+ if (cam->overlay_active == false) -+ return 0; -+ -+ err = ipu_channel_disable(cam->ipu_chan, true); -+ -+ ipu_channel_free(&cam->ipu_chan); -+ -+ csi_buffer_num = 0; -+ -+ err2 = cam_mipi_csi2_disable(cam); -+ flush_work(&cam->csi_work_struct); -+ cancel_work_sync(&cam->csi_work_struct); -+ -+ if (cam->vf_bufs_vaddr[0]) { -+ dma_free_coherent(0, cam->vf_bufs_size[0], -+ cam->vf_bufs_vaddr[0], cam->vf_bufs[0]); -+ cam->vf_bufs_vaddr[0] = NULL; -+ cam->vf_bufs[0] = 0; -+ } -+ if (cam->vf_bufs_vaddr[1]) { -+ dma_free_coherent(0, cam->vf_bufs_size[1], -+ cam->vf_bufs_vaddr[1], cam->vf_bufs[1]); -+ cam->vf_bufs_vaddr[1] = NULL; -+ cam->vf_bufs[1] = 0; -+ } -+ if (cam->rot_vf_bufs_vaddr[0]) { -+ dma_free_coherent(0, cam->rot_vf_buf_size[0], -+ cam->rot_vf_bufs_vaddr[0], -+ cam->rot_vf_bufs[0]); -+ cam->rot_vf_bufs_vaddr[0] = NULL; -+ cam->rot_vf_bufs[0] = 0; -+ } -+ if (cam->rot_vf_bufs_vaddr[1]) { -+ dma_free_coherent(0, cam->rot_vf_buf_size[1], -+ cam->rot_vf_bufs_vaddr[1], -+ cam->rot_vf_bufs[1]); -+ cam->rot_vf_bufs_vaddr[1] = NULL; -+ cam->rot_vf_bufs[1] = 0; -+ } -+ -+ cam->overlay_active = false; -+ return err ? err : err2; -+} -+ -+/*! -+ * Enable csi -+ * @param private struct cam_data * mxc capture instance -+ * -+ * @return status -+ */ -+static int bg_overlay_enable_csi(void *private) -+{ -+ return cam_ipu_enable_csi((cam_data *)private); -+} -+ -+/*! -+ * Disable csi -+ * @param private struct cam_data * mxc capture instance -+ * -+ * @return status -+ */ -+static int bg_overlay_disable_csi(void *private) -+{ -+ cam_data *cam = (cam_data *) private; -+ -+ /* free csi eof irq firstly. -+ * when disable csi, wait for idmac eof. -+ * it requests eof irq again */ -+ ipu_free_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF, cam); -+ return cam_ipu_disable_csi(cam); -+} -+ -+/*! -+ * function to select bg as the working path -+ * -+ * @param private cam_data * mxc v4l2 main structure -+ * -+ * @return status -+ */ -+int bg_overlay_sdc_select(void *private) -+{ -+ cam_data *cam = (cam_data *) private; -+ -+ if (cam) { -+ cam->vf_start_sdc = bg_overlay_start; -+ cam->vf_stop_sdc = bg_overlay_stop; -+ cam->vf_enable_csi = bg_overlay_enable_csi; -+ cam->vf_disable_csi = bg_overlay_disable_csi; -+ cam->overlay_active = false; -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL(bg_overlay_sdc_select); -+ -+/*! -+ * function to de-select bg as the working path -+ * -+ * @param private cam_data * mxc v4l2 main structure -+ * -+ * @return status -+ */ -+int bg_overlay_sdc_deselect(void *private) -+{ -+ cam_data *cam = (cam_data *) private; -+ -+ if (cam) { -+ cam->vf_start_sdc = NULL; -+ cam->vf_stop_sdc = NULL; -+ cam->vf_enable_csi = NULL; -+ cam->vf_disable_csi = NULL; -+ } -+ return 0; -+} -+EXPORT_SYMBOL(bg_overlay_sdc_deselect); -+ -+/*! -+ * Init background overlay task. -+ * -+ * @return Error code indicating success or failure -+ */ -+__init int bg_overlay_sdc_init(void) -+{ -+ return 0; -+} -+ -+/*! -+ * Deinit background overlay task. -+ * -+ * @return Error code indicating success or failure -+ */ -+void __exit bg_overlay_sdc_exit(void) -+{ -+} -+ -+module_init(bg_overlay_sdc_init); -+module_exit(bg_overlay_sdc_exit); -+ -+MODULE_AUTHOR("Freescale Semiconductor, Inc."); -+MODULE_DESCRIPTION("IPU PRP VF SDC Backgroud Driver"); -+MODULE_LICENSE("GPL"); -diff -Nur linux-4.1.13.orig/drivers/media/platform/mxc/capture/ipu_csi_enc.c linux-4.1.13/drivers/media/platform/mxc/capture/ipu_csi_enc.c ---- linux-4.1.13.orig/drivers/media/platform/mxc/capture/ipu_csi_enc.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/media/platform/mxc/capture/ipu_csi_enc.c 2015-11-30 17:56:13.600136395 +0100 -@@ -0,0 +1,384 @@ -+/* -+ * Copyright 2009-2014 Freescale Semiconductor, Inc. All Rights Reserved. -+ */ -+ -+/* -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/*! -+ * @file ipu_csi_enc.c -+ * -+ * @brief CSI Use case for video capture -+ * -+ * @ingroup IPU -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "mxc_v4l2_capture.h" -+#include "ipu_prp_sw.h" -+ -+#ifdef CAMERA_DBG -+ #define CAMERA_TRACE(x) (printk)x -+#else -+ #define CAMERA_TRACE(x) -+#endif -+ -+/* -+ * Function definitions -+ */ -+ -+/*! -+ * csi ENC callback function. -+ * -+ * @param irq int irq line -+ * @param dev_id void * device id -+ * -+ * @return status IRQ_HANDLED for handled -+ */ -+static irqreturn_t csi_enc_callback(int irq, void *dev_id) -+{ -+ cam_data *cam = (cam_data *) dev_id; -+ -+ if (cam->enc_callback == NULL) -+ return IRQ_HANDLED; -+ -+ cam->enc_callback(irq, dev_id); -+ return IRQ_HANDLED; -+} -+ -+/*! -+ * CSI ENC enable channel setup function -+ * -+ * @param cam struct cam_data * mxc capture instance -+ * -+ * @return status -+ */ -+static int csi_enc_setup(cam_data *cam) -+{ -+ ipu_channel_params_t params; -+ u32 pixel_fmt; -+ int err = 0, sensor_protocol = 0; -+ dma_addr_t dummy = cam->dummy_frame.buffer.m.offset; -+#ifdef CONFIG_MXC_MIPI_CSI2 -+ void *mipi_csi2_info; -+ int ipu_id; -+ int csi_id; -+#endif -+ struct v4l2_format cam_fmt; -+ -+ CAMERA_TRACE("In csi_enc_setup\n"); -+ if (!cam) { -+ printk(KERN_ERR "cam private is NULL\n"); -+ return -ENXIO; -+ } -+ -+ memset(¶ms, 0, sizeof(ipu_channel_params_t)); -+ params.csi_mem.csi = cam->csi; -+ -+ sensor_protocol = ipu_csi_get_sensor_protocol(cam->ipu, cam->csi); -+ switch (sensor_protocol) { -+ case IPU_CSI_CLK_MODE_GATED_CLK: -+ case IPU_CSI_CLK_MODE_NONGATED_CLK: -+ case IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE: -+ case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR: -+ case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR: -+ params.csi_mem.interlaced = false; -+ break; -+ case IPU_CSI_CLK_MODE_CCIR656_INTERLACED: -+ case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR: -+ case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR: -+ params.csi_mem.interlaced = true; -+ break; -+ default: -+ printk(KERN_ERR "sensor protocol unsupported\n"); -+ return -EINVAL; -+ } -+ -+ if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420) -+ pixel_fmt = IPU_PIX_FMT_YUV420P; -+ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YVU420) -+ pixel_fmt = IPU_PIX_FMT_YVU420P; -+ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV422P) -+ pixel_fmt = IPU_PIX_FMT_YUV422P; -+ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_UYVY) -+ { -+ cam_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; -+ vidioc_int_g_fmt_cap(cam->sensor, &cam_fmt); -+ if (cam_fmt.fmt.pix.pixelformat == IPU_PIX_FMT_GENERIC_16) -+ pixel_fmt = cam_fmt.fmt.pix.pixelformat; -+ else -+ pixel_fmt = IPU_PIX_FMT_UYVY; -+ } -+ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV) -+ pixel_fmt = IPU_PIX_FMT_YUYV; -+ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_NV12) -+ pixel_fmt = IPU_PIX_FMT_NV12; -+ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_BGR24) -+ pixel_fmt = IPU_PIX_FMT_BGR24; -+ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB24) -+ pixel_fmt = IPU_PIX_FMT_RGB24; -+ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB565) -+ pixel_fmt = IPU_PIX_FMT_RGB565; -+ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_BGR32) -+ pixel_fmt = IPU_PIX_FMT_BGR32; -+ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB32) -+ pixel_fmt = IPU_PIX_FMT_RGB32; -+ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_SBGGR8) -+ pixel_fmt = IPU_PIX_FMT_GENERIC; -+ else { -+ printk(KERN_ERR "format not supported\n"); -+ return -EINVAL; -+ } -+ err = cam_mipi_csi2_enable(cam, ¶ms.csi_mem.mipi); -+ if (err) -+ return err; -+ -+ err = ipu_channel_request(cam->ipu, CSI_MEM, ¶ms, &cam->ipu_chan); -+ if (err) { -+ pr_err("%s:ipu_channel_request %d\n", __func__, err); -+ return err; -+ } -+ -+ err = ipu_init_channel_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER, -+ pixel_fmt, cam->v2f.fmt.pix.width, -+ cam->v2f.fmt.pix.height, -+ cam->v2f.fmt.pix.bytesperline, -+ cam->rotation, -+ dummy, dummy, 0, -+ cam->offset.u_offset, -+ cam->offset.v_offset); -+ if (err != 0) { -+ printk(KERN_ERR "CSI_MEM output buffer\n"); -+ return err; -+ } -+ err = ipu_enable_channel(cam->ipu, CSI_MEM); -+ if (err < 0) { -+ printk(KERN_ERR "ipu_enable_channel CSI_MEM\n"); -+ return err; -+ } -+ -+ return err; -+} -+ -+/*! -+ * function to update physical buffer address for encorder IDMA channel -+ * -+ * @param eba physical buffer address for encorder IDMA channel -+ * @param buffer_num int buffer 0 or buffer 1 -+ * -+ * @return status -+ */ -+static int csi_enc_eba_update(struct ipu_soc *ipu, dma_addr_t eba, -+ int *buffer_num) -+{ -+ int err = 0; -+ -+ pr_debug("eba %x\n", eba); -+ err = ipu_update_channel_buffer(ipu, CSI_MEM, IPU_OUTPUT_BUFFER, -+ *buffer_num, eba); -+ if (err != 0) { -+ ipu_clear_buffer_ready(ipu, CSI_MEM, IPU_OUTPUT_BUFFER, -+ *buffer_num); -+ -+ err = ipu_update_channel_buffer(ipu, CSI_MEM, IPU_OUTPUT_BUFFER, -+ *buffer_num, eba); -+ if (err != 0) { -+ pr_err("ERROR: v4l2 capture: fail to update " -+ "buf%d\n", *buffer_num); -+ return err; -+ } -+ } -+ -+ ipu_select_buffer(ipu, CSI_MEM, IPU_OUTPUT_BUFFER, *buffer_num); -+ -+ *buffer_num = (*buffer_num == 0) ? 1 : 0; -+ -+ return 0; -+} -+ -+/*! -+ * Enable encoder task -+ * @param private struct cam_data * mxc capture instance -+ * -+ * @return status -+ */ -+static int csi_enc_enabling_tasks(void *private) -+{ -+ cam_data *cam = (cam_data *) private; -+ int err = 0; -+ CAMERA_TRACE("IPU:In csi_enc_enabling_tasks\n"); -+ -+ if (cam->dummy_frame.vaddress && -+ cam->dummy_frame.buffer.length -+ < PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage)) { -+ dma_free_coherent(0, cam->dummy_frame.buffer.length, -+ cam->dummy_frame.vaddress, -+ cam->dummy_frame.paddress); -+ cam->dummy_frame.vaddress = 0; -+ } -+ -+ if (!cam->dummy_frame.vaddress) { -+ cam->dummy_frame.vaddress = dma_alloc_coherent(0, -+ PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage), -+ &cam->dummy_frame.paddress, -+ GFP_DMA | GFP_KERNEL); -+ if (cam->dummy_frame.vaddress == 0) { -+ pr_err("ERROR: v4l2 capture: Allocate dummy frame " -+ "failed.\n"); -+ return -ENOBUFS; -+ } -+ cam->dummy_frame.buffer.length = -+ PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage); -+ } -+ cam->dummy_frame.buffer.type = V4L2_BUF_TYPE_PRIVATE; -+ cam->dummy_frame.buffer.m.offset = cam->dummy_frame.paddress; -+ -+ ipu_clear_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF); -+ err = ipu_request_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF, -+ csi_enc_callback, 0, "Mxc Camera", cam); -+ if (err != 0) { -+ pr_err("%s: Error requesting IPU_IRQ_CSI0_OUT_EOF\n", __func__); -+ return err; -+ } -+ -+ err = csi_enc_setup(cam); -+ if (err != 0) { -+ printk(KERN_ERR "csi_enc_setup %d\n", err); -+ return err; -+ } -+ -+ return err; -+} -+ -+/*! -+ * Disable encoder task -+ * @param private struct cam_data * mxc capture instance -+ * -+ * @return int -+ */ -+static int csi_enc_disabling_tasks(void *private) -+{ -+ cam_data *cam = (cam_data *) private; -+ int err = 0; -+ int err2 = 0; -+ -+ err = ipu_channel_disable(cam->ipu_chan, true); -+ -+ ipu_channel_free(&cam->ipu_chan); -+ -+ err2 = cam_mipi_csi2_disable(cam); -+ return err ? err : err2; -+} -+ -+/*! -+ * Enable csi -+ * @param private struct cam_data * mxc capture instance -+ * -+ * @return status -+ */ -+static int csi_enc_enable_csi(void *private) -+{ -+ return cam_ipu_enable_csi((cam_data *)private); -+} -+ -+/*! -+ * Disable csi -+ * @param private struct cam_data * mxc capture instance -+ * -+ * @return status -+ */ -+static int csi_enc_disable_csi(void *private) -+{ -+ cam_data *cam = (cam_data *) private; -+ -+ /* free csi eof irq firstly. -+ * when disable csi, wait for idmac eof. -+ * it requests eof irq again */ -+ ipu_free_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF, cam); -+ return cam_ipu_disable_csi(cam); -+} -+ -+/*! -+ * function to select CSI ENC as the working path -+ * -+ * @param private struct cam_data * mxc capture instance -+ * -+ * @return int -+ */ -+int csi_enc_select(void *private) -+{ -+ cam_data *cam = (cam_data *) private; -+ int err = 0; -+ -+ if (cam) { -+ cam->enc_update_eba = csi_enc_eba_update; -+ cam->enc_enable = csi_enc_enabling_tasks; -+ cam->enc_disable = csi_enc_disabling_tasks; -+ cam->enc_enable_csi = csi_enc_enable_csi; -+ cam->enc_disable_csi = csi_enc_disable_csi; -+ } else { -+ err = -EIO; -+ } -+ -+ return err; -+} -+EXPORT_SYMBOL(csi_enc_select); -+ -+/*! -+ * function to de-select CSI ENC as the working path -+ * -+ * @param private struct cam_data * mxc capture instance -+ * -+ * @return int -+ */ -+int csi_enc_deselect(void *private) -+{ -+ cam_data *cam = (cam_data *) private; -+ int err = 0; -+ -+ if (cam) { -+ cam->enc_update_eba = NULL; -+ cam->enc_enable = NULL; -+ cam->enc_disable = NULL; -+ cam->enc_enable_csi = NULL; -+ cam->enc_disable_csi = NULL; -+ } -+ -+ return err; -+} -+EXPORT_SYMBOL(csi_enc_deselect); -+ -+/*! -+ * Init the Encorder channels -+ * -+ * @return Error code indicating success or failure -+ */ -+__init int csi_enc_init(void) -+{ -+ return 0; -+} -+ -+/*! -+ * Deinit the Encorder channels -+ * -+ */ -+void __exit csi_enc_exit(void) -+{ -+} -+ -+module_init(csi_enc_init); -+module_exit(csi_enc_exit); -+ -+MODULE_AUTHOR("Freescale Semiconductor, Inc."); -+MODULE_DESCRIPTION("CSI ENC Driver"); -+MODULE_LICENSE("GPL"); -diff -Nur linux-4.1.13.orig/drivers/media/platform/mxc/capture/ipu_fg_overlay_sdc.c linux-4.1.13/drivers/media/platform/mxc/capture/ipu_fg_overlay_sdc.c ---- linux-4.1.13.orig/drivers/media/platform/mxc/capture/ipu_fg_overlay_sdc.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/media/platform/mxc/capture/ipu_fg_overlay_sdc.c 2015-11-30 17:56:13.600136395 +0100 -@@ -0,0 +1,580 @@ -+/* -+ * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved. -+ */ -+/* * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/*! -+ * @file ipu_foreground_sdc.c -+ * -+ * @brief IPU Use case for PRP-VF -+ * -+ * @ingroup IPU -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "mxc_v4l2_capture.h" -+#include "ipu_prp_sw.h" -+ -+#ifdef CAMERA_DBG -+ #define CAMERA_TRACE(x) (printk)x -+#else -+ #define CAMERA_TRACE(x) -+#endif -+ -+static int csi_buffer_num, buffer_num; -+static u32 csi_mem_bufsize; -+static struct ipu_soc *disp_ipu; -+static struct fb_info *fbi; -+static struct fb_var_screeninfo fbvar; -+static u32 vf_out_format; -+static void csi_buf_work_func(struct work_struct *work) -+{ -+ int err = 0; -+ cam_data *cam = -+ container_of(work, struct _cam_data, csi_work_struct); -+ -+ struct ipu_task task; -+ memset(&task, 0, sizeof(task)); -+ -+ if (csi_buffer_num) -+ task.input.paddr = cam->vf_bufs[0]; -+ else -+ task.input.paddr = cam->vf_bufs[1]; -+ task.input.width = cam->crop_current.width; -+ task.input.height = cam->crop_current.height; -+ task.input.format = IPU_PIX_FMT_NV12; -+ -+ if (buffer_num == 0) -+ task.output.paddr = fbi->fix.smem_start + -+ (fbi->fix.line_length * fbvar.yres); -+ else -+ task.output.paddr = fbi->fix.smem_start; -+ task.output.width = cam->win.w.width; -+ task.output.height = cam->win.w.height; -+ task.output.format = vf_out_format; -+ task.output.rotate = cam->rotation; -+again: -+ err = ipu_check_task(&task); -+ if (err != IPU_CHECK_OK) { -+ if (err > IPU_CHECK_ERR_MIN) { -+ if (err == IPU_CHECK_ERR_SPLIT_INPUTW_OVER) { -+ task.input.crop.w -= 8; -+ goto again; -+ } -+ if (err == IPU_CHECK_ERR_SPLIT_INPUTH_OVER) { -+ task.input.crop.h -= 8; -+ goto again; -+ } -+ if (err == IPU_CHECK_ERR_SPLIT_OUTPUTW_OVER) { -+ task.output.width -= 8; -+ task.output.crop.w = task.output.width; -+ goto again; -+ } -+ if (err == IPU_CHECK_ERR_SPLIT_OUTPUTH_OVER) { -+ task.output.height -= 8; -+ task.output.crop.h = task.output.height; -+ goto again; -+ } -+ printk(KERN_ERR "check ipu taks fail\n"); -+ return; -+ } -+ printk(KERN_ERR "check ipu taks fail\n"); -+ return; -+ } -+ err = ipu_queue_task(&task); -+ if (err < 0) -+ printk(KERN_ERR "queue ipu task error\n"); -+ ipu_select_buffer(disp_ipu, MEM_FG_SYNC, IPU_INPUT_BUFFER, buffer_num); -+ buffer_num = (buffer_num == 0) ? 1 : 0; -+} -+ -+static void get_disp_ipu(cam_data *cam) -+{ -+ if (cam->output > 2) -+ disp_ipu = ipu_get_soc(1); /* using DISP4 */ -+ else -+ disp_ipu = ipu_get_soc(0); -+} -+ -+/*! -+ * csi ENC callback function. -+ * -+ * @param irq int irq line -+ * @param dev_id void * device id -+ * -+ * @return status IRQ_HANDLED for handled -+ */ -+static irqreturn_t csi_enc_callback(int irq, void *dev_id) -+{ -+ cam_data *cam = (cam_data *) dev_id; -+ -+ ipu_select_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER, csi_buffer_num); -+ if ((cam->crop_current.width != cam->win.w.width) || -+ (cam->crop_current.height != cam->win.w.height) || -+ (vf_out_format != IPU_PIX_FMT_NV12) || -+ (cam->rotation >= IPU_ROTATE_VERT_FLIP)) -+ schedule_work(&cam->csi_work_struct); -+ csi_buffer_num = (csi_buffer_num == 0) ? 1 : 0; -+ return IRQ_HANDLED; -+} -+ -+static int csi_enc_setup(cam_data *cam) -+{ -+ ipu_channel_params_t params; -+ int err = 0, sensor_protocol = 0; -+ -+ CAMERA_TRACE("In csi_enc_setup\n"); -+ if (!cam) { -+ printk(KERN_ERR "cam private is NULL\n"); -+ return -ENXIO; -+ } -+ -+ memset(¶ms, 0, sizeof(ipu_channel_params_t)); -+ params.csi_mem.csi = cam->csi; -+ -+ sensor_protocol = ipu_csi_get_sensor_protocol(cam->ipu, cam->csi); -+ switch (sensor_protocol) { -+ case IPU_CSI_CLK_MODE_GATED_CLK: -+ case IPU_CSI_CLK_MODE_NONGATED_CLK: -+ case IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE: -+ case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR: -+ case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR: -+ params.csi_mem.interlaced = false; -+ break; -+ case IPU_CSI_CLK_MODE_CCIR656_INTERLACED: -+ case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR: -+ case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR: -+ params.csi_mem.interlaced = true; -+ break; -+ default: -+ printk(KERN_ERR "sensor protocol unsupported\n"); -+ return -EINVAL; -+ } -+ err = cam_mipi_csi2_enable(cam, ¶ms.csi_mem.mipi); -+ if (err) -+ return err; -+ -+ if (cam->vf_bufs_vaddr[0]) { -+ dma_free_coherent(0, cam->vf_bufs_size[0], -+ cam->vf_bufs_vaddr[0], -+ (dma_addr_t) cam->vf_bufs[0]); -+ } -+ if (cam->vf_bufs_vaddr[1]) { -+ dma_free_coherent(0, cam->vf_bufs_size[1], -+ cam->vf_bufs_vaddr[1], -+ (dma_addr_t) cam->vf_bufs[1]); -+ } -+ csi_mem_bufsize = cam->crop_current.width * -+ cam->crop_current.height * 3/2; -+ cam->vf_bufs_size[0] = PAGE_ALIGN(csi_mem_bufsize); -+ cam->vf_bufs_vaddr[0] = (void *)dma_alloc_coherent(0, -+ cam->vf_bufs_size[0], -+ (dma_addr_t *) & -+ cam->vf_bufs[0], -+ GFP_DMA | -+ GFP_KERNEL); -+ if (cam->vf_bufs_vaddr[0] == NULL) { -+ printk(KERN_ERR "Error to allocate vf buffer\n"); -+ err = -ENOMEM; -+ goto out_2; -+ } -+ cam->vf_bufs_size[1] = PAGE_ALIGN(csi_mem_bufsize); -+ cam->vf_bufs_vaddr[1] = (void *)dma_alloc_coherent(0, -+ cam->vf_bufs_size[1], -+ (dma_addr_t *) & -+ cam->vf_bufs[1], -+ GFP_DMA | -+ GFP_KERNEL); -+ if (cam->vf_bufs_vaddr[1] == NULL) { -+ printk(KERN_ERR "Error to allocate vf buffer\n"); -+ err = -ENOMEM; -+ goto out_1; -+ } -+ pr_debug("vf_bufs %x %x\n", cam->vf_bufs[0], cam->vf_bufs[1]); -+ -+ err = ipu_channel_request(cam->ipu, CSI_MEM, ¶ms, &cam->ipu_chan); -+ if (err) { -+ pr_err("%s:ipu_channel_request %d\n", __func__, err); -+ goto out_1; -+ } -+ -+ if ((cam->crop_current.width == cam->win.w.width) && -+ (cam->crop_current.height == cam->win.w.height) && -+ (vf_out_format == IPU_PIX_FMT_NV12) && -+ (cam->rotation < IPU_ROTATE_VERT_FLIP)) { -+ err = ipu_init_channel_buffer(cam->ipu, CSI_MEM, -+ IPU_OUTPUT_BUFFER, -+ IPU_PIX_FMT_NV12, -+ cam->crop_current.width, -+ cam->crop_current.height, -+ cam->crop_current.width, IPU_ROTATE_NONE, -+ fbi->fix.smem_start + -+ (fbi->fix.line_length * fbvar.yres), -+ fbi->fix.smem_start, 0, -+ cam->offset.u_offset, cam->offset.u_offset); -+ } else { -+ err = ipu_init_channel_buffer(cam->ipu, CSI_MEM, -+ IPU_OUTPUT_BUFFER, -+ IPU_PIX_FMT_NV12, -+ cam->crop_current.width, -+ cam->crop_current.height, -+ cam->crop_current.width, IPU_ROTATE_NONE, -+ cam->vf_bufs[0], cam->vf_bufs[1], 0, -+ cam->offset.u_offset, cam->offset.u_offset); -+ } -+ if (err != 0) { -+ printk(KERN_ERR "CSI_MEM output buffer\n"); -+ goto out_1; -+ } -+ err = ipu_enable_channel(cam->ipu, CSI_MEM); -+ if (err < 0) { -+ printk(KERN_ERR "ipu_enable_channel CSI_MEM\n"); -+ goto out_1; -+ } -+ -+ csi_buffer_num = 0; -+ -+ ipu_select_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER, 0); -+ ipu_select_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER, 1); -+ return err; -+out_1: -+ if (cam->vf_bufs_vaddr[0]) { -+ dma_free_coherent(0, cam->vf_bufs_size[0], -+ cam->vf_bufs_vaddr[0], -+ (dma_addr_t) cam->vf_bufs[0]); -+ cam->vf_bufs_vaddr[0] = NULL; -+ cam->vf_bufs[0] = 0; -+ } -+ if (cam->vf_bufs_vaddr[1]) { -+ dma_free_coherent(0, cam->vf_bufs_size[1], -+ cam->vf_bufs_vaddr[1], -+ (dma_addr_t) cam->vf_bufs[1]); -+ cam->vf_bufs_vaddr[1] = NULL; -+ cam->vf_bufs[1] = 0; -+ } -+out_2: -+ return err; -+} -+ -+/*! -+ * Enable encoder task -+ * @param private struct cam_data * mxc capture instance -+ * -+ * @return status -+ */ -+static int csi_enc_enabling_tasks(void *private) -+{ -+ cam_data *cam = (cam_data *) private; -+ int err = 0; -+ CAMERA_TRACE("IPU:In csi_enc_enabling_tasks\n"); -+ -+ ipu_clear_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF); -+ err = ipu_request_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF, -+ csi_enc_callback, 0, "Mxc Camera", cam); -+ if (err != 0) { -+ printk(KERN_ERR "Error registering CSI0_OUT_EOF irq\n"); -+ return err; -+ } -+ -+ INIT_WORK(&cam->csi_work_struct, csi_buf_work_func); -+ -+ err = csi_enc_setup(cam); -+ if (err != 0) { -+ printk(KERN_ERR "csi_enc_setup %d\n", err); -+ goto out1; -+ } -+ -+ return err; -+out1: -+ ipu_free_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF, cam); -+ return err; -+} -+ -+/* -+ * Function definitions -+ */ -+ -+/*! -+ * foreground_start - start the vf task -+ * -+ * @param private cam_data * mxc v4l2 main structure -+ * -+ */ -+static int foreground_start(void *private) -+{ -+ cam_data *cam = (cam_data *) private; -+ int err = 0, i = 0, screen_size; -+ char *base; -+ -+ if (!cam) { -+ printk(KERN_ERR "private is NULL\n"); -+ return -EIO; -+ } -+ -+ if (cam->overlay_active == true) { -+ pr_debug("already started.\n"); -+ return 0; -+ } -+ -+ get_disp_ipu(cam); -+ -+ for (i = 0; i < num_registered_fb; i++) { -+ char *idstr = registered_fb[i]->fix.id; -+ if (((strcmp(idstr, "DISP3 FG") == 0) && (cam->output < 3)) || -+ ((strcmp(idstr, "DISP4 FG") == 0) && (cam->output >= 3))) { -+ fbi = registered_fb[i]; -+ break; -+ } -+ } -+ -+ if (fbi == NULL) { -+ printk(KERN_ERR "DISP FG fb not found\n"); -+ return -EPERM; -+ } -+ -+ fbvar = fbi->var; -+ -+ /* Store the overlay frame buffer's original std */ -+ cam->fb_origin_std = fbvar.nonstd; -+ -+ if (cam->devtype == IMX5_V4L2 || cam->devtype == IMX6_V4L2) { -+ /* Use DP to do CSC so that we can get better performance */ -+ vf_out_format = IPU_PIX_FMT_NV12; -+ fbvar.nonstd = vf_out_format; -+ } else { -+ vf_out_format = IPU_PIX_FMT_RGB565; -+ fbvar.nonstd = 0; -+ } -+ -+ fbvar.bits_per_pixel = 16; -+ fbvar.xres = fbvar.xres_virtual = cam->win.w.width; -+ fbvar.yres = cam->win.w.height; -+ fbvar.yres_virtual = cam->win.w.height * 2; -+ fbvar.yoffset = 0; -+ fbvar.vmode &= ~FB_VMODE_YWRAP; -+ fbvar.accel_flags = FB_ACCEL_DOUBLE_FLAG; -+ fbvar.activate |= FB_ACTIVATE_FORCE; -+ fb_set_var(fbi, &fbvar); -+ -+ ipu_disp_set_window_pos(disp_ipu, MEM_FG_SYNC, cam->win.w.left, -+ cam->win.w.top); -+ -+ /* Fill black color for framebuffer */ -+ base = (char *) fbi->screen_base; -+ screen_size = fbi->var.xres * fbi->var.yres; -+ if (cam->devtype == IMX5_V4L2 || cam->devtype == IMX6_V4L2) { -+ memset(base, 0, screen_size); -+ base += screen_size; -+ for (i = 0; i < screen_size / 2; i++, base++) -+ *base = 0x80; -+ } else { -+ for (i = 0; i < screen_size * 2; i++, base++) -+ *base = 0x00; -+ } -+ -+ console_lock(); -+ fb_blank(fbi, FB_BLANK_UNBLANK); -+ console_unlock(); -+ -+ /* correct display ch buffer address */ -+ ipu_update_channel_buffer(disp_ipu, MEM_FG_SYNC, IPU_INPUT_BUFFER, -+ 0, fbi->fix.smem_start + -+ (fbi->fix.line_length * fbvar.yres)); -+ ipu_update_channel_buffer(disp_ipu, MEM_FG_SYNC, IPU_INPUT_BUFFER, -+ 1, fbi->fix.smem_start); -+ -+ err = csi_enc_enabling_tasks(cam); -+ if (err != 0) { -+ printk(KERN_ERR "Error csi enc enable fail\n"); -+ return err; -+ } -+ -+ cam->overlay_active = true; -+ return err; -+ -+} -+ -+/*! -+ * foreground_stop - stop the vf task -+ * -+ * @param private cam_data * mxc v4l2 main structure -+ * -+ */ -+static int foreground_stop(void *private) -+{ -+ cam_data *cam = (cam_data *) private; -+ int err = 0, i = 0; -+ int err2 = 0; -+ struct fb_info *fbi = NULL; -+ struct fb_var_screeninfo fbvar; -+ -+ if (cam->overlay_active == false) -+ return 0; -+ -+ err = ipu_channel_disable(cam->ipu_chan, true); -+ -+ ipu_channel_free(&cam->ipu_chan); -+ -+ csi_buffer_num = 0; -+ buffer_num = 0; -+ -+ for (i = 0; i < num_registered_fb; i++) { -+ char *idstr = registered_fb[i]->fix.id; -+ if (((strcmp(idstr, "DISP3 FG") == 0) && (cam->output < 3)) || -+ ((strcmp(idstr, "DISP4 FG") == 0) && (cam->output >= 3))) { -+ fbi = registered_fb[i]; -+ break; -+ } -+ } -+ -+ if (fbi == NULL) { -+ printk(KERN_ERR "DISP FG fb not found\n"); -+ return -EPERM; -+ } -+ -+ console_lock(); -+ fb_blank(fbi, FB_BLANK_POWERDOWN); -+ console_unlock(); -+ -+ /* Set the overlay frame buffer std to what it is used to be */ -+ fbvar = fbi->var; -+ fbvar.accel_flags = FB_ACCEL_TRIPLE_FLAG; -+ fbvar.nonstd = cam->fb_origin_std; -+ fbvar.activate |= FB_ACTIVATE_FORCE; -+ fb_set_var(fbi, &fbvar); -+ err2 = cam_mipi_csi2_disable(cam); -+ -+ flush_work(&cam->csi_work_struct); -+ cancel_work_sync(&cam->csi_work_struct); -+ -+ if (cam->vf_bufs_vaddr[0]) { -+ dma_free_coherent(0, cam->vf_bufs_size[0], -+ cam->vf_bufs_vaddr[0], -+ (dma_addr_t) cam->vf_bufs[0]); -+ cam->vf_bufs_vaddr[0] = NULL; -+ cam->vf_bufs[0] = 0; -+ } -+ if (cam->vf_bufs_vaddr[1]) { -+ dma_free_coherent(0, cam->vf_bufs_size[1], -+ cam->vf_bufs_vaddr[1], -+ (dma_addr_t) cam->vf_bufs[1]); -+ cam->vf_bufs_vaddr[1] = NULL; -+ cam->vf_bufs[1] = 0; -+ } -+ -+ cam->overlay_active = false; -+ return err ? err : err2; -+} -+ -+/*! -+ * Enable csi -+ * @param private struct cam_data * mxc capture instance -+ * -+ * @return status -+ */ -+static int foreground_enable_csi(void *private) -+{ -+ return cam_ipu_enable_csi((cam_data *)private); -+} -+ -+/*! -+ * Disable csi -+ * @param private struct cam_data * mxc capture instance -+ * -+ * @return status -+ */ -+static int foreground_disable_csi(void *private) -+{ -+ cam_data *cam = (cam_data *) private; -+ -+ /* free csi eof irq firstly. -+ * when disable csi, wait for idmac eof. -+ * it requests eof irq again */ -+ ipu_free_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF, cam); -+ return cam_ipu_disable_csi(cam); -+} -+ -+/*! -+ * function to select foreground as the working path -+ * -+ * @param private cam_data * mxc v4l2 main structure -+ * -+ * @return status -+ */ -+int foreground_sdc_select(void *private) -+{ -+ cam_data *cam; -+ int err = 0; -+ if (private) { -+ cam = (cam_data *) private; -+ cam->vf_start_sdc = foreground_start; -+ cam->vf_stop_sdc = foreground_stop; -+ cam->vf_enable_csi = foreground_enable_csi; -+ cam->vf_disable_csi = foreground_disable_csi; -+ cam->overlay_active = false; -+ } else -+ err = -EIO; -+ -+ return err; -+} -+EXPORT_SYMBOL(foreground_sdc_select); -+ -+/*! -+ * function to de-select foreground as the working path -+ * -+ * @param private cam_data * mxc v4l2 main structure -+ * -+ * @return int -+ */ -+int foreground_sdc_deselect(void *private) -+{ -+ cam_data *cam; -+ -+ if (private) { -+ cam = (cam_data *) private; -+ cam->vf_start_sdc = NULL; -+ cam->vf_stop_sdc = NULL; -+ cam->vf_enable_csi = NULL; -+ cam->vf_disable_csi = NULL; -+ } -+ return 0; -+} -+EXPORT_SYMBOL(foreground_sdc_deselect); -+ -+/*! -+ * Init viewfinder task. -+ * -+ * @return Error code indicating success or failure -+ */ -+__init int foreground_sdc_init(void) -+{ -+ return 0; -+} -+ -+/*! -+ * Deinit viewfinder task. -+ * -+ * @return Error code indicating success or failure -+ */ -+void __exit foreground_sdc_exit(void) -+{ -+} -+ -+module_init(foreground_sdc_init); -+module_exit(foreground_sdc_exit); -+ -+MODULE_AUTHOR("Freescale Semiconductor, Inc."); -+MODULE_DESCRIPTION("IPU PRP VF SDC Driver"); -+MODULE_LICENSE("GPL"); -diff -Nur linux-4.1.13.orig/drivers/media/platform/mxc/capture/ipu_prp_enc.c linux-4.1.13/drivers/media/platform/mxc/capture/ipu_prp_enc.c ---- linux-4.1.13.orig/drivers/media/platform/mxc/capture/ipu_prp_enc.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/media/platform/mxc/capture/ipu_prp_enc.c 2015-11-30 17:56:13.600136395 +0100 -@@ -0,0 +1,538 @@ -+/* -+ * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved. -+ */ -+ -+/* -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/*! -+ * @file ipu_prp_enc.c -+ * -+ * @brief IPU Use case for PRP-ENC -+ * -+ * @ingroup IPU -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include "mxc_v4l2_capture.h" -+#include "ipu_prp_sw.h" -+ -+#ifdef CAMERA_DBG -+ #define CAMERA_TRACE(x) (printk)x -+#else -+ #define CAMERA_TRACE(x) -+#endif -+ -+static ipu_rotate_mode_t grotation = IPU_ROTATE_NONE; -+ -+/* -+ * Function definitions -+ */ -+ -+/*! -+ * IPU ENC callback function. -+ * -+ * @param irq int irq line -+ * @param dev_id void * device id -+ * -+ * @return status IRQ_HANDLED for handled -+ */ -+static irqreturn_t prp_enc_callback(int irq, void *dev_id) -+{ -+ cam_data *cam = (cam_data *) dev_id; -+ -+ if (cam->enc_callback == NULL) -+ return IRQ_HANDLED; -+ -+ cam->enc_callback(irq, dev_id); -+ -+ return IRQ_HANDLED; -+} -+ -+/*! -+ * PrpENC enable channel setup function -+ * -+ * @param cam struct cam_data * mxc capture instance -+ * -+ * @return status -+ */ -+static int prp_enc_setup(cam_data *cam) -+{ -+ ipu_channel_params_t enc; -+ int err = 0; -+ dma_addr_t dummy = cam->dummy_frame.buffer.m.offset; -+ -+ CAMERA_TRACE("In prp_enc_setup\n"); -+ if (!cam) { -+ printk(KERN_ERR "cam private is NULL\n"); -+ return -ENXIO; -+ } -+ memset(&enc, 0, sizeof(ipu_channel_params_t)); -+ -+ ipu_csi_get_window_size(cam->ipu, &enc.csi_prp_enc_mem.in_width, -+ &enc.csi_prp_enc_mem.in_height, cam->csi); -+ -+ enc.csi_prp_enc_mem.in_pixel_fmt = IPU_PIX_FMT_UYVY; -+ enc.csi_prp_enc_mem.out_width = cam->v2f.fmt.pix.width; -+ enc.csi_prp_enc_mem.out_height = cam->v2f.fmt.pix.height; -+ enc.csi_prp_enc_mem.csi = cam->csi; -+ if (cam->rotation >= IPU_ROTATE_90_RIGHT) { -+ enc.csi_prp_enc_mem.out_width = cam->v2f.fmt.pix.height; -+ enc.csi_prp_enc_mem.out_height = cam->v2f.fmt.pix.width; -+ } -+ -+ if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420) { -+ enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_YUV420P; -+ pr_info("YUV420\n"); -+ } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YVU420) { -+ enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_YVU420P; -+ pr_info("YVU420\n"); -+ } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV422P) { -+ enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_YUV422P; -+ pr_info("YUV422P\n"); -+ } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV) { -+ enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_YUYV; -+ pr_info("YUYV\n"); -+ } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_UYVY) { -+ enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_UYVY; -+ pr_info("UYVY\n"); -+ } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_NV12) { -+ enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_NV12; -+ pr_info("NV12\n"); -+ } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_BGR24) { -+ enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_BGR24; -+ pr_info("BGR24\n"); -+ } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB24) { -+ enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_RGB24; -+ pr_info("RGB24\n"); -+ } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB565) { -+ enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_RGB565; -+ pr_info("RGB565\n"); -+ } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_BGR32) { -+ enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_BGR32; -+ pr_info("BGR32\n"); -+ } else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB32) { -+ enc.csi_prp_enc_mem.out_pixel_fmt = IPU_PIX_FMT_RGB32; -+ pr_info("RGB32\n"); -+ } else { -+ printk(KERN_ERR "format not supported\n"); -+ return -EINVAL; -+ } -+ err = cam_mipi_csi2_enable(cam, &enc.csi_prp_enc_mem.mipi); -+ if (err) -+ return err; -+ -+ err = ipu_channel_request(cam->ipu, CSI_PRP_ENC_MEM, &enc, &cam->ipu_chan); -+ if (err) { -+ pr_err("%s:ipu_channel_request %d\n", __func__, err); -+ return err; -+ } -+ -+ grotation = cam->rotation; -+ if (cam->rotation >= IPU_ROTATE_90_RIGHT) { -+ if (cam->rot_enc_bufs_vaddr[0]) { -+ dma_free_coherent(0, cam->rot_enc_buf_size[0], -+ cam->rot_enc_bufs_vaddr[0], -+ cam->rot_enc_bufs[0]); -+ } -+ if (cam->rot_enc_bufs_vaddr[1]) { -+ dma_free_coherent(0, cam->rot_enc_buf_size[1], -+ cam->rot_enc_bufs_vaddr[1], -+ cam->rot_enc_bufs[1]); -+ } -+ cam->rot_enc_buf_size[0] = -+ PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage); -+ cam->rot_enc_bufs_vaddr[0] = -+ (void *)dma_alloc_coherent(0, cam->rot_enc_buf_size[0], -+ &cam->rot_enc_bufs[0], -+ GFP_DMA | GFP_KERNEL); -+ if (!cam->rot_enc_bufs_vaddr[0]) { -+ printk(KERN_ERR "alloc enc_bufs0\n"); -+ return -ENOMEM; -+ } -+ cam->rot_enc_buf_size[1] = -+ PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage); -+ cam->rot_enc_bufs_vaddr[1] = -+ (void *)dma_alloc_coherent(0, cam->rot_enc_buf_size[1], -+ &cam->rot_enc_bufs[1], -+ GFP_DMA | GFP_KERNEL); -+ if (!cam->rot_enc_bufs_vaddr[1]) { -+ dma_free_coherent(0, cam->rot_enc_buf_size[0], -+ cam->rot_enc_bufs_vaddr[0], -+ cam->rot_enc_bufs[0]); -+ cam->rot_enc_bufs_vaddr[0] = NULL; -+ cam->rot_enc_bufs[0] = 0; -+ printk(KERN_ERR "alloc enc_bufs1\n"); -+ return -ENOMEM; -+ } -+ -+ err = ipu_init_channel_buffer(cam->ipu, CSI_PRP_ENC_MEM, -+ IPU_OUTPUT_BUFFER, -+ enc.csi_prp_enc_mem.out_pixel_fmt, -+ enc.csi_prp_enc_mem.out_width, -+ enc.csi_prp_enc_mem.out_height, -+ enc.csi_prp_enc_mem.out_width, -+ IPU_ROTATE_NONE, -+ cam->rot_enc_bufs[0], -+ cam->rot_enc_bufs[1], 0, 0, 0); -+ if (err != 0) { -+ printk(KERN_ERR "CSI_PRP_ENC_MEM err\n"); -+ return err; -+ } -+ -+ err = ipu_channel_request(cam->ipu, MEM_ROT_ENC_MEM, NULL, &cam->ipu_chan_rot); -+ if (err) { -+ pr_err("%s:ipu_channel_request %d for rot\n", __func__, err); -+ return err; -+ } -+ -+ err = ipu_init_channel_buffer(cam->ipu, MEM_ROT_ENC_MEM, -+ IPU_INPUT_BUFFER, -+ enc.csi_prp_enc_mem.out_pixel_fmt, -+ enc.csi_prp_enc_mem.out_width, -+ enc.csi_prp_enc_mem.out_height, -+ enc.csi_prp_enc_mem.out_width, -+ cam->rotation, -+ cam->rot_enc_bufs[0], -+ cam->rot_enc_bufs[1], 0, 0, 0); -+ if (err != 0) { -+ printk(KERN_ERR "MEM_ROT_ENC_MEM input buffer\n"); -+ return err; -+ } -+ -+ err = -+ ipu_init_channel_buffer(cam->ipu, MEM_ROT_ENC_MEM, -+ IPU_OUTPUT_BUFFER, -+ enc.csi_prp_enc_mem.out_pixel_fmt, -+ enc.csi_prp_enc_mem.out_height, -+ enc.csi_prp_enc_mem.out_width, -+ cam->v2f.fmt.pix.bytesperline / -+ bytes_per_pixel(enc.csi_prp_enc_mem. -+ out_pixel_fmt), -+ IPU_ROTATE_NONE, -+ dummy, dummy, 0, -+ cam->offset.u_offset, -+ cam->offset.v_offset); -+ if (err != 0) { -+ printk(KERN_ERR "MEM_ROT_ENC_MEM output buffer\n"); -+ return err; -+ } -+ -+ err = ipu_link_channels(cam->ipu, -+ CSI_PRP_ENC_MEM, MEM_ROT_ENC_MEM); -+ if (err < 0) { -+ printk(KERN_ERR -+ "link CSI_PRP_ENC_MEM-MEM_ROT_ENC_MEM\n"); -+ return err; -+ } -+ -+ err = ipu_enable_channel(cam->ipu, CSI_PRP_ENC_MEM); -+ if (err < 0) { -+ printk(KERN_ERR "ipu_enable_channel CSI_PRP_ENC_MEM\n"); -+ return err; -+ } -+ err = ipu_enable_channel(cam->ipu, MEM_ROT_ENC_MEM); -+ if (err < 0) { -+ printk(KERN_ERR "ipu_enable_channel MEM_ROT_ENC_MEM\n"); -+ return err; -+ } -+ -+ ipu_select_buffer(cam->ipu, CSI_PRP_ENC_MEM, -+ IPU_OUTPUT_BUFFER, 0); -+ ipu_select_buffer(cam->ipu, CSI_PRP_ENC_MEM, -+ IPU_OUTPUT_BUFFER, 1); -+ } else { -+ err = -+ ipu_init_channel_buffer(cam->ipu, CSI_PRP_ENC_MEM, -+ IPU_OUTPUT_BUFFER, -+ enc.csi_prp_enc_mem.out_pixel_fmt, -+ enc.csi_prp_enc_mem.out_width, -+ enc.csi_prp_enc_mem.out_height, -+ cam->v2f.fmt.pix.bytesperline / -+ bytes_per_pixel(enc.csi_prp_enc_mem. -+ out_pixel_fmt), -+ cam->rotation, -+ dummy, dummy, 0, -+ cam->offset.u_offset, -+ cam->offset.v_offset); -+ if (err != 0) { -+ printk(KERN_ERR "CSI_PRP_ENC_MEM output buffer\n"); -+ return err; -+ } -+ err = ipu_enable_channel(cam->ipu, CSI_PRP_ENC_MEM); -+ if (err < 0) { -+ printk(KERN_ERR "ipu_enable_channel CSI_PRP_ENC_MEM\n"); -+ return err; -+ } -+ } -+ -+ return err; -+} -+ -+/*! -+ * function to update physical buffer address for encorder IDMA channel -+ * -+ * @param eba physical buffer address for encorder IDMA channel -+ * @param buffer_num int buffer 0 or buffer 1 -+ * -+ * @return status -+ */ -+static int prp_enc_eba_update(struct ipu_soc *ipu, dma_addr_t eba, -+ int *buffer_num) -+{ -+ int err = 0; -+ -+ pr_debug("eba %x\n", eba); -+ if (grotation >= IPU_ROTATE_90_RIGHT) { -+ err = ipu_update_channel_buffer(ipu, MEM_ROT_ENC_MEM, -+ IPU_OUTPUT_BUFFER, *buffer_num, -+ eba); -+ } else { -+ err = ipu_update_channel_buffer(ipu, CSI_PRP_ENC_MEM, -+ IPU_OUTPUT_BUFFER, *buffer_num, -+ eba); -+ } -+ if (err != 0) { -+ if (grotation >= IPU_ROTATE_90_RIGHT) { -+ ipu_clear_buffer_ready(ipu, MEM_ROT_ENC_MEM, -+ IPU_OUTPUT_BUFFER, -+ *buffer_num); -+ err = ipu_update_channel_buffer(ipu, MEM_ROT_ENC_MEM, -+ IPU_OUTPUT_BUFFER, -+ *buffer_num, -+ eba); -+ } else { -+ ipu_clear_buffer_ready(ipu, CSI_PRP_ENC_MEM, -+ IPU_OUTPUT_BUFFER, -+ *buffer_num); -+ err = ipu_update_channel_buffer(ipu, CSI_PRP_ENC_MEM, -+ IPU_OUTPUT_BUFFER, -+ *buffer_num, -+ eba); -+ } -+ -+ if (err != 0) { -+ pr_err("ERROR: v4l2 capture: fail to update " -+ "buf%d\n", *buffer_num); -+ return err; -+ } -+ } -+ -+ if (grotation >= IPU_ROTATE_90_RIGHT) { -+ ipu_select_buffer(ipu, MEM_ROT_ENC_MEM, IPU_OUTPUT_BUFFER, -+ *buffer_num); -+ } else { -+ ipu_select_buffer(ipu, CSI_PRP_ENC_MEM, IPU_OUTPUT_BUFFER, -+ *buffer_num); -+ } -+ -+ *buffer_num = (*buffer_num == 0) ? 1 : 0; -+ return 0; -+} -+ -+/*! -+ * Enable encoder task -+ * @param private struct cam_data * mxc capture instance -+ * -+ * @return status -+ */ -+static int prp_enc_enabling_tasks(void *private) -+{ -+ cam_data *cam = (cam_data *) private; -+ int err = 0; -+ int irq; -+ CAMERA_TRACE("IPU:In prp_enc_enabling_tasks\n"); -+ -+ cam->dummy_frame.vaddress = dma_alloc_coherent(0, -+ PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage), -+ &cam->dummy_frame.paddress, -+ GFP_DMA | GFP_KERNEL); -+ if (cam->dummy_frame.vaddress == 0) { -+ pr_err("ERROR: v4l2 capture: Allocate dummy frame " -+ "failed.\n"); -+ return -ENOBUFS; -+ } -+ cam->dummy_frame.buffer.type = V4L2_BUF_TYPE_PRIVATE; -+ cam->dummy_frame.buffer.length = -+ PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage); -+ cam->dummy_frame.buffer.m.offset = cam->dummy_frame.paddress; -+ -+ irq = (cam->rotation >= IPU_ROTATE_90_RIGHT) ? -+ IPU_IRQ_PRP_ENC_ROT_OUT_EOF : IPU_IRQ_PRP_ENC_OUT_EOF; -+ err = ipu_request_irq(cam->ipu, irq, -+ prp_enc_callback, 0, "Mxc Camera", cam); -+ if (err) { -+ pr_err("%s: Error requesting irq=%d\n", __func__, irq); -+ return err; -+ } -+ -+ err = prp_enc_setup(cam); -+ if (err != 0) { -+ printk(KERN_ERR "prp_enc_setup %d\n", err); -+ return err; -+ } -+ -+ return err; -+} -+ -+/*! -+ * Disable encoder task -+ * @param private struct cam_data * mxc capture instance -+ * -+ * @return int -+ */ -+static int prp_enc_disabling_tasks(void *private) -+{ -+ cam_data *cam = (cam_data *) private; -+ int err = 0; -+ int err2 = 0; -+ int err3 = 0; -+ -+ if (cam->rotation >= IPU_ROTATE_90_RIGHT) { -+ ipu_free_irq(cam->ipu, IPU_IRQ_PRP_ENC_ROT_OUT_EOF, cam); -+ ipu_unlink_channels(cam->ipu, CSI_PRP_ENC_MEM, MEM_ROT_ENC_MEM); -+ } -+ -+ err = ipu_channel_disable(cam->ipu_chan, true); -+ err2 = ipu_channel_disable(cam->ipu_chan_rot, true); -+ -+ ipu_channel_free(&cam->ipu_chan); -+ ipu_channel_free(&cam->ipu_chan_rot); -+ -+ if (cam->dummy_frame.vaddress != 0) { -+ dma_free_coherent(0, cam->dummy_frame.buffer.length, -+ cam->dummy_frame.vaddress, -+ cam->dummy_frame.paddress); -+ cam->dummy_frame.vaddress = 0; -+ } -+ err3 = cam_mipi_csi2_disable(cam); -+ return err ? err : (err2 ? err2 : err3); -+} -+ -+/*! -+ * Enable csi -+ * @param private struct cam_data * mxc capture instance -+ * -+ * @return status -+ */ -+static int prp_enc_enable_csi(void *private) -+{ -+ return cam_ipu_enable_csi((cam_data *)private); -+} -+ -+/*! -+ * Disable csi -+ * @param private struct cam_data * mxc capture instance -+ * -+ * @return status -+ */ -+static int prp_enc_disable_csi(void *private) -+{ -+ cam_data *cam = (cam_data *) private; -+ -+ /* free csi eof irq firstly. -+ * when disable csi, wait for idmac eof. -+ * it requests eof irq again */ -+ if (cam->rotation < IPU_ROTATE_90_RIGHT) -+ ipu_free_irq(cam->ipu, IPU_IRQ_PRP_ENC_OUT_EOF, cam); -+ return cam_ipu_disable_csi(cam); -+} -+ -+/*! -+ * function to select PRP-ENC as the working path -+ * -+ * @param private struct cam_data * mxc capture instance -+ * -+ * @return int -+ */ -+int prp_enc_select(void *private) -+{ -+ cam_data *cam = (cam_data *) private; -+ int err = 0; -+ -+ if (cam) { -+ cam->enc_update_eba = prp_enc_eba_update; -+ cam->enc_enable = prp_enc_enabling_tasks; -+ cam->enc_disable = prp_enc_disabling_tasks; -+ cam->enc_enable_csi = prp_enc_enable_csi; -+ cam->enc_disable_csi = prp_enc_disable_csi; -+ } else { -+ err = -EIO; -+ } -+ -+ return err; -+} -+EXPORT_SYMBOL(prp_enc_select); -+ -+/*! -+ * function to de-select PRP-ENC as the working path -+ * -+ * @param private struct cam_data * mxc capture instance -+ * -+ * @return int -+ */ -+int prp_enc_deselect(void *private) -+{ -+ cam_data *cam = (cam_data *) private; -+ int err = 0; -+ -+ if (cam) { -+ cam->enc_update_eba = NULL; -+ cam->enc_enable = NULL; -+ cam->enc_disable = NULL; -+ cam->enc_enable_csi = NULL; -+ cam->enc_disable_csi = NULL; -+ if (cam->rot_enc_bufs_vaddr[0]) { -+ dma_free_coherent(0, cam->rot_enc_buf_size[0], -+ cam->rot_enc_bufs_vaddr[0], -+ cam->rot_enc_bufs[0]); -+ cam->rot_enc_bufs_vaddr[0] = NULL; -+ cam->rot_enc_bufs[0] = 0; -+ } -+ if (cam->rot_enc_bufs_vaddr[1]) { -+ dma_free_coherent(0, cam->rot_enc_buf_size[1], -+ cam->rot_enc_bufs_vaddr[1], -+ cam->rot_enc_bufs[1]); -+ cam->rot_enc_bufs_vaddr[1] = NULL; -+ cam->rot_enc_bufs[1] = 0; -+ } -+ } -+ -+ return err; -+} -+EXPORT_SYMBOL(prp_enc_deselect); -+ -+/*! -+ * Init the Encorder channels -+ * -+ * @return Error code indicating success or failure -+ */ -+__init int prp_enc_init(void) -+{ -+ return 0; -+} -+ -+/*! -+ * Deinit the Encorder channels -+ * -+ */ -+void __exit prp_enc_exit(void) -+{ -+} -+ -+module_init(prp_enc_init); -+module_exit(prp_enc_exit); -+ -+MODULE_AUTHOR("Freescale Semiconductor, Inc."); -+MODULE_DESCRIPTION("IPU PRP ENC Driver"); -+MODULE_LICENSE("GPL"); -diff -Nur linux-4.1.13.orig/drivers/media/platform/mxc/capture/ipu_prp_sw.h linux-4.1.13/drivers/media/platform/mxc/capture/ipu_prp_sw.h ---- linux-4.1.13.orig/drivers/media/platform/mxc/capture/ipu_prp_sw.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/media/platform/mxc/capture/ipu_prp_sw.h 2015-11-30 17:56:13.600136395 +0100 -@@ -0,0 +1,43 @@ -+/* -+ * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved. -+ */ -+ -+/* -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/*! -+ * @file ipu_prp_sw.h -+ * -+ * @brief This file contains the IPU PRP use case driver header. -+ * -+ * @ingroup IPU -+ */ -+ -+#ifndef _INCLUDE_IPU__PRP_SW_H_ -+#define _INCLUDE_IPU__PRP_SW_H_ -+ -+int csi_enc_select(void *private); -+int csi_enc_deselect(void *private); -+int prp_enc_select(void *private); -+int prp_enc_deselect(void *private); -+#ifdef CONFIG_MXC_IPU_PRP_VF_SDC -+int prp_vf_sdc_select(void *private); -+int prp_vf_sdc_deselect(void *private); -+int prp_vf_sdc_select_bg(void *private); -+int prp_vf_sdc_deselect_bg(void *private); -+#else -+int foreground_sdc_select(void *private); -+int foreground_sdc_deselect(void *private); -+int bg_overlay_sdc_select(void *private); -+int bg_overlay_sdc_deselect(void *private); -+#endif -+int prp_still_select(void *private); -+int prp_still_deselect(void *private); -+ -+#endif -diff -Nur linux-4.1.13.orig/drivers/media/platform/mxc/capture/ipu_prp_vf_sdc_bg.c linux-4.1.13/drivers/media/platform/mxc/capture/ipu_prp_vf_sdc_bg.c ---- linux-4.1.13.orig/drivers/media/platform/mxc/capture/ipu_prp_vf_sdc_bg.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/media/platform/mxc/capture/ipu_prp_vf_sdc_bg.c 2015-11-30 17:56:13.600136395 +0100 -@@ -0,0 +1,472 @@ -+/* -+ * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved. -+ */ -+ -+/* -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/*! -+ * @file ipu_prp_vf_sdc_bg.c -+ * -+ * @brief IPU Use case for PRP-VF back-ground -+ * -+ * @ingroup IPU -+ */ -+#include -+#include -+#include -+#include -+#include -+#include "mxc_v4l2_capture.h" -+#include "ipu_prp_sw.h" -+ -+static int buffer_num; -+static int buffer_ready; -+static struct ipu_soc *disp_ipu; -+ -+static void get_disp_ipu(cam_data *cam) -+{ -+ if (cam->output > 2) -+ disp_ipu = ipu_get_soc(1); /* using DISP4 */ -+ else -+ disp_ipu = ipu_get_soc(0); -+} -+ -+/* -+ * Function definitions -+ */ -+ -+/*! -+ * SDC V-Sync callback function. -+ * -+ * @param irq int irq line -+ * @param dev_id void * device id -+ * -+ * @return status IRQ_HANDLED for handled -+ */ -+static irqreturn_t prpvf_sdc_vsync_callback(int irq, void *dev_id) -+{ -+ cam_data *cam = dev_id; -+ if (buffer_ready > 0) { -+ ipu_select_buffer(cam->ipu, MEM_ROT_VF_MEM, -+ IPU_OUTPUT_BUFFER, 0); -+ buffer_ready--; -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+/*! -+ * VF EOF callback function. -+ * -+ * @param irq int irq line -+ * @param dev_id void * device id -+ * -+ * @return status IRQ_HANDLED for handled -+ */ -+static irqreturn_t prpvf_vf_eof_callback(int irq, void *dev_id) -+{ -+ cam_data *cam = dev_id; -+ pr_debug("buffer_ready %d buffer_num %d\n", buffer_ready, buffer_num); -+ -+ ipu_select_buffer(cam->ipu, MEM_ROT_VF_MEM, -+ IPU_INPUT_BUFFER, buffer_num); -+ buffer_num = (buffer_num == 0) ? 1 : 0; -+ ipu_select_buffer(cam->ipu, CSI_PRP_VF_MEM, -+ IPU_OUTPUT_BUFFER, buffer_num); -+ buffer_ready++; -+ return IRQ_HANDLED; -+} -+ -+/*! -+ * prpvf_start - start the vf task -+ * -+ * @param private cam_data * mxc v4l2 main structure -+ * -+ */ -+static int prpvf_start(void *private) -+{ -+ cam_data *cam = (cam_data *) private; -+ ipu_channel_params_t vf; -+ u32 format; -+ u32 offset; -+ u32 bpp, size = 3; -+ int err = 0; -+ -+ if (!cam) { -+ printk(KERN_ERR "private is NULL\n"); -+ return -EIO; -+ } -+ -+ if (cam->overlay_active == true) { -+ pr_debug("already start.\n"); -+ return 0; -+ } -+ -+ get_disp_ipu(cam); -+ -+ format = cam->v4l2_fb.fmt.pixelformat; -+ if (cam->v4l2_fb.fmt.pixelformat == IPU_PIX_FMT_BGR24) { -+ bpp = 3, size = 3; -+ pr_info("BGR24\n"); -+ } else if (cam->v4l2_fb.fmt.pixelformat == IPU_PIX_FMT_RGB565) { -+ bpp = 2, size = 2; -+ pr_info("RGB565\n"); -+ } else if (cam->v4l2_fb.fmt.pixelformat == IPU_PIX_FMT_BGR32) { -+ bpp = 4, size = 4; -+ pr_info("BGR32\n"); -+ } else { -+ printk(KERN_ERR -+ "unsupported fix format from the framebuffer.\n"); -+ return -EINVAL; -+ } -+ -+ offset = cam->v4l2_fb.fmt.bytesperline * cam->win.w.top + -+ size * cam->win.w.left; -+ -+ if (cam->v4l2_fb.base == 0) -+ printk(KERN_ERR "invalid frame buffer address.\n"); -+ else -+ offset += (u32) cam->v4l2_fb.base; -+ -+ memset(&vf, 0, sizeof(ipu_channel_params_t)); -+ ipu_csi_get_window_size(cam->ipu, &vf.csi_prp_vf_mem.in_width, -+ &vf.csi_prp_vf_mem.in_height, cam->csi); -+ vf.csi_prp_vf_mem.in_pixel_fmt = IPU_PIX_FMT_UYVY; -+ vf.csi_prp_vf_mem.out_width = cam->win.w.width; -+ vf.csi_prp_vf_mem.out_height = cam->win.w.height; -+ vf.csi_prp_vf_mem.csi = cam->csi; -+ if (cam->vf_rotation >= IPU_ROTATE_90_RIGHT) { -+ vf.csi_prp_vf_mem.out_width = cam->win.w.height; -+ vf.csi_prp_vf_mem.out_height = cam->win.w.width; -+ } -+ vf.csi_prp_vf_mem.out_pixel_fmt = format; -+ size = cam->win.w.width * cam->win.w.height * size; -+ -+ err = cam_mipi_csi2_enable(cam, &vf.csi_prp_vf_mem.mipi); -+ if (err) -+ return err; -+ -+ err = ipu_channel_request(cam->ipu, CSI_PRP_VF_MEM, &vf, &cam->ipu_chan); -+ if (err) { -+ pr_err("%s:ipu_channel_request %d\n", __func__, err); -+ goto out_4; -+ } -+ -+ if (cam->vf_bufs_vaddr[0]) { -+ dma_free_coherent(0, cam->vf_bufs_size[0], -+ cam->vf_bufs_vaddr[0], cam->vf_bufs[0]); -+ } -+ if (cam->vf_bufs_vaddr[1]) { -+ dma_free_coherent(0, cam->vf_bufs_size[1], -+ cam->vf_bufs_vaddr[1], cam->vf_bufs[1]); -+ } -+ cam->vf_bufs_size[0] = PAGE_ALIGN(size); -+ cam->vf_bufs_vaddr[0] = (void *)dma_alloc_coherent(0, -+ cam->vf_bufs_size[0], -+ &cam->vf_bufs[0], -+ GFP_DMA | -+ GFP_KERNEL); -+ if (cam->vf_bufs_vaddr[0] == NULL) { -+ printk(KERN_ERR "Error to allocate vf buffer\n"); -+ err = -ENOMEM; -+ goto out_3; -+ } -+ cam->vf_bufs_size[1] = PAGE_ALIGN(size); -+ cam->vf_bufs_vaddr[1] = (void *)dma_alloc_coherent(0, -+ cam->vf_bufs_size[1], -+ &cam->vf_bufs[1], -+ GFP_DMA | -+ GFP_KERNEL); -+ if (cam->vf_bufs_vaddr[1] == NULL) { -+ printk(KERN_ERR "Error to allocate vf buffer\n"); -+ err = -ENOMEM; -+ goto out_3; -+ } -+ -+ err = ipu_init_channel_buffer(cam->ipu, CSI_PRP_VF_MEM, -+ IPU_OUTPUT_BUFFER, -+ format, vf.csi_prp_vf_mem.out_width, -+ vf.csi_prp_vf_mem.out_height, -+ vf.csi_prp_vf_mem.out_width, -+ IPU_ROTATE_NONE, -+ cam->vf_bufs[0], -+ cam->vf_bufs[1], -+ 0, 0, 0); -+ if (err != 0) { -+ printk(KERN_ERR "Error initializing CSI_PRP_VF_MEM\n"); -+ goto out_3; -+ } -+ err = ipu_channel_request(cam->ipu, MEM_ROT_VF_MEM, NULL, &cam->ipu_chan_rot); -+ if (err) { -+ pr_err("%s:ipu_channel_request %d for rot\n", __func__, err); -+ goto out_3; -+ } -+ -+ err = ipu_init_channel_buffer(cam->ipu, MEM_ROT_VF_MEM, -+ IPU_INPUT_BUFFER, -+ format, vf.csi_prp_vf_mem.out_width, -+ vf.csi_prp_vf_mem.out_height, -+ vf.csi_prp_vf_mem.out_width, -+ cam->vf_rotation, -+ cam->vf_bufs[0], -+ cam->vf_bufs[1], -+ 0, 0, 0); -+ if (err != 0) { -+ printk(KERN_ERR "Error MEM_ROT_VF_MEM input buffer\n"); -+ goto out_2; -+ } -+ -+ if (cam->vf_rotation >= IPU_ROTATE_90_RIGHT) { -+ err = ipu_init_channel_buffer(cam->ipu, MEM_ROT_VF_MEM, -+ IPU_OUTPUT_BUFFER, -+ format, -+ vf.csi_prp_vf_mem.out_height, -+ vf.csi_prp_vf_mem.out_width, -+ cam->overlay_fb->var.xres * bpp, -+ IPU_ROTATE_NONE, -+ offset, 0, 0, 0, 0); -+ -+ if (err != 0) { -+ printk(KERN_ERR "Error MEM_ROT_VF_MEM output buffer\n"); -+ goto out_2; -+ } -+ } else { -+ err = ipu_init_channel_buffer(cam->ipu, MEM_ROT_VF_MEM, -+ IPU_OUTPUT_BUFFER, -+ format, -+ vf.csi_prp_vf_mem.out_width, -+ vf.csi_prp_vf_mem.out_height, -+ cam->overlay_fb->var.xres * bpp, -+ IPU_ROTATE_NONE, -+ offset, 0, 0, 0, 0); -+ if (err != 0) { -+ printk(KERN_ERR "Error MEM_ROT_VF_MEM output buffer\n"); -+ goto out_2; -+ } -+ } -+ -+ ipu_clear_irq(cam->ipu, IPU_IRQ_PRP_VF_OUT_EOF); -+ err = ipu_request_irq(cam->ipu, IPU_IRQ_PRP_VF_OUT_EOF, -+ prpvf_vf_eof_callback, -+ 0, "Mxc Camera", cam); -+ if (err != 0) { -+ printk(KERN_ERR -+ "Error registering IPU_IRQ_PRP_VF_OUT_EOF irq.\n"); -+ goto out_2; -+ } -+ -+ ipu_clear_irq(disp_ipu, IPU_IRQ_BG_SF_END); -+ err = ipu_request_irq(disp_ipu, IPU_IRQ_BG_SF_END, -+ prpvf_sdc_vsync_callback, -+ 0, "Mxc Camera", cam); -+ if (err != 0) { -+ printk(KERN_ERR "Error registering IPU_IRQ_BG_SF_END irq.\n"); -+ goto out_1; -+ } -+ -+ ipu_enable_channel(cam->ipu, CSI_PRP_VF_MEM); -+ ipu_enable_channel(cam->ipu, MEM_ROT_VF_MEM); -+ -+ buffer_num = 0; -+ buffer_ready = 0; -+ ipu_select_buffer(cam->ipu, CSI_PRP_VF_MEM, IPU_OUTPUT_BUFFER, 0); -+ -+ cam->overlay_active = true; -+ return err; -+ -+out_1: -+ ipu_free_irq(cam->ipu, IPU_IRQ_PRP_VF_OUT_EOF, NULL); -+out_2: -+ ipu_channel_free(&cam->ipu_chan_rot); -+out_3: -+ ipu_channel_free(&cam->ipu_chan); -+out_4: -+ if (cam->vf_bufs_vaddr[0]) { -+ dma_free_coherent(0, cam->vf_bufs_size[0], -+ cam->vf_bufs_vaddr[0], cam->vf_bufs[0]); -+ cam->vf_bufs_vaddr[0] = NULL; -+ cam->vf_bufs[0] = 0; -+ } -+ if (cam->vf_bufs_vaddr[1]) { -+ dma_free_coherent(0, cam->vf_bufs_size[1], -+ cam->vf_bufs_vaddr[1], cam->vf_bufs[1]); -+ cam->vf_bufs_vaddr[1] = NULL; -+ cam->vf_bufs[1] = 0; -+ } -+ if (cam->rot_vf_bufs_vaddr[0]) { -+ dma_free_coherent(0, cam->rot_vf_buf_size[0], -+ cam->rot_vf_bufs_vaddr[0], -+ cam->rot_vf_bufs[0]); -+ cam->rot_vf_bufs_vaddr[0] = NULL; -+ cam->rot_vf_bufs[0] = 0; -+ } -+ if (cam->rot_vf_bufs_vaddr[1]) { -+ dma_free_coherent(0, cam->rot_vf_buf_size[1], -+ cam->rot_vf_bufs_vaddr[1], -+ cam->rot_vf_bufs[1]); -+ cam->rot_vf_bufs_vaddr[1] = NULL; -+ cam->rot_vf_bufs[1] = 0; -+ } -+ return err; -+} -+ -+/*! -+ * prpvf_stop - stop the vf task -+ * -+ * @param private cam_data * mxc v4l2 main structure -+ * -+ */ -+static int prpvf_stop(void *private) -+{ -+ int err = 0; -+ cam_data *cam = (cam_data *) private; -+ -+ if (cam->overlay_active == false) -+ return 0; -+ -+ ipu_free_irq(disp_ipu, IPU_IRQ_BG_SF_END, cam); -+ -+ ipu_channel_disable(cam->ipu_chan, true); -+ ipu_channel_disable(cam->ipu_chan_rot, true); -+ ipu_channel_free(&cam->ipu_chan); -+ ipu_channel_free(&cam->ipu_chan_rot); -+ -+ err = cam_mipi_csi2_disable(cam); -+ -+ if (cam->vf_bufs_vaddr[0]) { -+ dma_free_coherent(0, cam->vf_bufs_size[0], -+ cam->vf_bufs_vaddr[0], cam->vf_bufs[0]); -+ cam->vf_bufs_vaddr[0] = NULL; -+ cam->vf_bufs[0] = 0; -+ } -+ if (cam->vf_bufs_vaddr[1]) { -+ dma_free_coherent(0, cam->vf_bufs_size[1], -+ cam->vf_bufs_vaddr[1], cam->vf_bufs[1]); -+ cam->vf_bufs_vaddr[1] = NULL; -+ cam->vf_bufs[1] = 0; -+ } -+ if (cam->rot_vf_bufs_vaddr[0]) { -+ dma_free_coherent(0, cam->rot_vf_buf_size[0], -+ cam->rot_vf_bufs_vaddr[0], -+ cam->rot_vf_bufs[0]); -+ cam->rot_vf_bufs_vaddr[0] = NULL; -+ cam->rot_vf_bufs[0] = 0; -+ } -+ if (cam->rot_vf_bufs_vaddr[1]) { -+ dma_free_coherent(0, cam->rot_vf_buf_size[1], -+ cam->rot_vf_bufs_vaddr[1], -+ cam->rot_vf_bufs[1]); -+ cam->rot_vf_bufs_vaddr[1] = NULL; -+ cam->rot_vf_bufs[1] = 0; -+ } -+ -+ buffer_num = 0; -+ buffer_ready = 0; -+ cam->overlay_active = false; -+ return err; -+} -+ -+/*! -+ * Enable csi -+ * @param private struct cam_data * mxc capture instance -+ * -+ * @return status -+ */ -+static int prp_vf_enable_csi(void *private) -+{ -+ return cam_ipu_enable_csi((cam_data *)private); -+} -+ -+/*! -+ * Disable csi -+ * @param private struct cam_data * mxc capture instance -+ * -+ * @return status -+ */ -+static int prp_vf_disable_csi(void *private) -+{ -+ cam_data *cam = (cam_data *) private; -+ -+ /* free csi eof irq firstly. -+ * when disable csi, wait for idmac eof. -+ * it requests eof irq again */ -+ ipu_free_irq(cam->ipu, IPU_IRQ_PRP_VF_OUT_EOF, cam); -+ return cam_ipu_disable_csi(cam); -+} -+ -+/*! -+ * function to select PRP-VF as the working path -+ * -+ * @param private cam_data * mxc v4l2 main structure -+ * -+ * @return status -+ */ -+int prp_vf_sdc_select_bg(void *private) -+{ -+ cam_data *cam = (cam_data *) private; -+ -+ if (cam) { -+ cam->vf_start_sdc = prpvf_start; -+ cam->vf_stop_sdc = prpvf_stop; -+ cam->vf_enable_csi = prp_vf_enable_csi; -+ cam->vf_disable_csi = prp_vf_disable_csi; -+ cam->overlay_active = false; -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL(prp_vf_sdc_select_bg); -+ -+/*! -+ * function to de-select PRP-VF as the working path -+ * -+ * @param private cam_data * mxc v4l2 main structure -+ * -+ * @return status -+ */ -+int prp_vf_sdc_deselect_bg(void *private) -+{ -+ cam_data *cam = (cam_data *) private; -+ -+ if (cam) { -+ cam->vf_start_sdc = NULL; -+ cam->vf_stop_sdc = NULL; -+ cam->vf_enable_csi = NULL; -+ cam->vf_disable_csi = NULL; -+ } -+ return 0; -+} -+EXPORT_SYMBOL(prp_vf_sdc_deselect_bg); -+ -+/*! -+ * Init viewfinder task. -+ * -+ * @return Error code indicating success or failure -+ */ -+__init int prp_vf_sdc_init_bg(void) -+{ -+ return 0; -+} -+ -+/*! -+ * Deinit viewfinder task. -+ * -+ * @return Error code indicating success or failure -+ */ -+void __exit prp_vf_sdc_exit_bg(void) -+{ -+} -+ -+module_init(prp_vf_sdc_init_bg); -+module_exit(prp_vf_sdc_exit_bg); -+ -+MODULE_AUTHOR("Freescale Semiconductor, Inc."); -+MODULE_DESCRIPTION("IPU PRP VF SDC Backgroud Driver"); -+MODULE_LICENSE("GPL"); -diff -Nur linux-4.1.13.orig/drivers/media/platform/mxc/capture/ipu_prp_vf_sdc.c linux-4.1.13/drivers/media/platform/mxc/capture/ipu_prp_vf_sdc.c ---- linux-4.1.13.orig/drivers/media/platform/mxc/capture/ipu_prp_vf_sdc.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/media/platform/mxc/capture/ipu_prp_vf_sdc.c 2015-11-30 17:56:13.600136395 +0100 -@@ -0,0 +1,528 @@ -+/* -+ * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved. -+ */ -+/* * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/*! -+ * @file ipu_prp_vf_sdc.c -+ * -+ * @brief IPU Use case for PRP-VF -+ * -+ * @ingroup IPU -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "mxc_v4l2_capture.h" -+#include "ipu_prp_sw.h" -+ -+static int buffer_num; -+static struct ipu_soc *disp_ipu; -+ -+static void get_disp_ipu(cam_data *cam) -+{ -+ if (cam->output > 2) -+ disp_ipu = ipu_get_soc(1); /* using DISP4 */ -+ else -+ disp_ipu = ipu_get_soc(0); -+} -+ -+static irqreturn_t prpvf_rot_eof_callback(int irq, void *dev_id) -+{ -+ cam_data *cam = dev_id; -+ pr_debug("buffer_num %d\n", buffer_num); -+ -+ if (cam->vf_rotation >= IPU_ROTATE_VERT_FLIP) { -+ ipu_select_buffer(disp_ipu, MEM_FG_SYNC, -+ IPU_INPUT_BUFFER, buffer_num); -+ buffer_num = (buffer_num == 0) ? 1 : 0; -+ ipu_select_buffer(cam->ipu, MEM_ROT_VF_MEM, -+ IPU_OUTPUT_BUFFER, buffer_num); -+ } else { -+ ipu_select_buffer(disp_ipu, MEM_FG_SYNC, -+ IPU_INPUT_BUFFER, buffer_num); -+ buffer_num = (buffer_num == 0) ? 1 : 0; -+ ipu_select_buffer(cam->ipu, CSI_PRP_VF_MEM, -+ IPU_OUTPUT_BUFFER, buffer_num); -+ } -+ return IRQ_HANDLED; -+} -+/* -+ * Function definitions -+ */ -+ -+/*! -+ * prpvf_start - start the vf task -+ * -+ * @param private cam_data * mxc v4l2 main structure -+ * -+ */ -+static int prpvf_start(void *private) -+{ -+ struct fb_var_screeninfo fbvar; -+ struct fb_info *fbi = NULL; -+ cam_data *cam = (cam_data *) private; -+ ipu_channel_params_t vf; -+ u32 vf_out_format = 0; -+ u32 size = 2, temp = 0; -+ int err = 0, i = 0; -+ short *tmp, color; -+ -+ if (!cam) { -+ printk(KERN_ERR "private is NULL\n"); -+ return -EIO; -+ } -+ -+ if (cam->overlay_active == true) { -+ pr_debug("already started.\n"); -+ return 0; -+ } -+ -+ get_disp_ipu(cam); -+ -+ for (i = 0; i < num_registered_fb; i++) { -+ char *idstr = registered_fb[i]->fix.id; -+ if (((strcmp(idstr, "DISP3 FG") == 0) && (cam->output < 3)) || -+ ((strcmp(idstr, "DISP4 FG") == 0) && (cam->output >= 3))) { -+ fbi = registered_fb[i]; -+ break; -+ } -+ } -+ -+ if (fbi == NULL) { -+ printk(KERN_ERR "DISP FG fb not found\n"); -+ return -EPERM; -+ } -+ -+ fbvar = fbi->var; -+ -+ /* Store the overlay frame buffer's original std */ -+ cam->fb_origin_std = fbvar.nonstd; -+ -+ if (cam->devtype == IMX5_V4L2 || cam->devtype == IMX6_V4L2) { -+ /* Use DP to do CSC so that we can get better performance */ -+ vf_out_format = IPU_PIX_FMT_UYVY; -+ fbvar.nonstd = vf_out_format; -+ color = 0x80; -+ } else { -+ vf_out_format = IPU_PIX_FMT_RGB565; -+ fbvar.nonstd = 0; -+ color = 0x0; -+ } -+ -+ fbvar.bits_per_pixel = 16; -+ fbvar.xres = fbvar.xres_virtual = cam->win.w.width; -+ fbvar.yres = cam->win.w.height; -+ fbvar.yres_virtual = cam->win.w.height * 2; -+ fbvar.yoffset = 0; -+ fbvar.accel_flags = FB_ACCEL_DOUBLE_FLAG; -+ fbvar.activate |= FB_ACTIVATE_FORCE; -+ fb_set_var(fbi, &fbvar); -+ -+ ipu_disp_set_window_pos(disp_ipu, MEM_FG_SYNC, cam->win.w.left, -+ cam->win.w.top); -+ -+ /* Fill black color for framebuffer */ -+ tmp = (short *) fbi->screen_base; -+ for (i = 0; i < (fbi->fix.line_length * fbi->var.yres)/2; -+ i++, tmp++) -+ *tmp = color; -+ -+ console_lock(); -+ fb_blank(fbi, FB_BLANK_UNBLANK); -+ console_unlock(); -+ -+ /* correct display ch buffer address */ -+ ipu_update_channel_buffer(disp_ipu, MEM_FG_SYNC, IPU_INPUT_BUFFER, -+ 0, fbi->fix.smem_start + -+ (fbi->fix.line_length * fbvar.yres)); -+ ipu_update_channel_buffer(disp_ipu, MEM_FG_SYNC, IPU_INPUT_BUFFER, -+ 1, fbi->fix.smem_start); -+ -+ memset(&vf, 0, sizeof(ipu_channel_params_t)); -+ ipu_csi_get_window_size(cam->ipu, &vf.csi_prp_vf_mem.in_width, -+ &vf.csi_prp_vf_mem.in_height, cam->csi); -+ vf.csi_prp_vf_mem.in_pixel_fmt = IPU_PIX_FMT_UYVY; -+ vf.csi_prp_vf_mem.out_width = cam->win.w.width; -+ vf.csi_prp_vf_mem.out_height = cam->win.w.height; -+ vf.csi_prp_vf_mem.csi = cam->csi; -+ if (cam->vf_rotation >= IPU_ROTATE_90_RIGHT) { -+ vf.csi_prp_vf_mem.out_width = cam->win.w.height; -+ vf.csi_prp_vf_mem.out_height = cam->win.w.width; -+ } -+ vf.csi_prp_vf_mem.out_pixel_fmt = vf_out_format; -+ size = cam->win.w.width * cam->win.w.height * size; -+ -+ err = cam_mipi_csi2_enable(cam, &vf.csi_prp_vf_mem.mipi); -+ if (err) -+ return err; -+ -+ err = ipu_channel_request(cam->ipu, CSI_PRP_VF_MEM, &vf, &cam->ipu_chan); -+ if (err) { -+ pr_err("%s:ipu_channel_request %d\n", __func__, err); -+ goto out_5; -+ } -+ -+ if (cam->vf_bufs_vaddr[0]) { -+ dma_free_coherent(0, cam->vf_bufs_size[0], -+ cam->vf_bufs_vaddr[0], -+ (dma_addr_t) cam->vf_bufs[0]); -+ } -+ if (cam->vf_bufs_vaddr[1]) { -+ dma_free_coherent(0, cam->vf_bufs_size[1], -+ cam->vf_bufs_vaddr[1], -+ (dma_addr_t) cam->vf_bufs[1]); -+ } -+ cam->vf_bufs_size[0] = PAGE_ALIGN(size); -+ cam->vf_bufs_vaddr[0] = (void *)dma_alloc_coherent(0, -+ cam->vf_bufs_size[0], -+ (dma_addr_t *) & -+ cam->vf_bufs[0], -+ GFP_DMA | -+ GFP_KERNEL); -+ if (cam->vf_bufs_vaddr[0] == NULL) { -+ printk(KERN_ERR "Error to allocate vf buffer\n"); -+ err = -ENOMEM; -+ goto out_4; -+ } -+ cam->vf_bufs_size[1] = PAGE_ALIGN(size); -+ cam->vf_bufs_vaddr[1] = (void *)dma_alloc_coherent(0, -+ cam->vf_bufs_size[1], -+ (dma_addr_t *) & -+ cam->vf_bufs[1], -+ GFP_DMA | -+ GFP_KERNEL); -+ if (cam->vf_bufs_vaddr[1] == NULL) { -+ printk(KERN_ERR "Error to allocate vf buffer\n"); -+ err = -ENOMEM; -+ goto out_3; -+ } -+ pr_debug("vf_bufs %x %x\n", cam->vf_bufs[0], cam->vf_bufs[1]); -+ -+ if (cam->vf_rotation >= IPU_ROTATE_VERT_FLIP) { -+ err = ipu_init_channel_buffer(cam->ipu, CSI_PRP_VF_MEM, -+ IPU_OUTPUT_BUFFER, -+ vf_out_format, -+ vf.csi_prp_vf_mem.out_width, -+ vf.csi_prp_vf_mem.out_height, -+ vf.csi_prp_vf_mem.out_width, -+ IPU_ROTATE_NONE, -+ cam->vf_bufs[0], cam->vf_bufs[1], -+ 0, 0, 0); -+ if (err != 0) -+ goto out_3; -+ -+ err = ipu_channel_request(cam->ipu, MEM_ROT_VF_MEM, NULL, &cam->ipu_chan_rot); -+ if (err) { -+ pr_err("%s:ipu_channel_request %d for rot\n", __func__, err); -+ goto out_3; -+ } -+ -+ err = ipu_init_channel_buffer(cam->ipu, MEM_ROT_VF_MEM, -+ IPU_INPUT_BUFFER, -+ vf_out_format, -+ vf.csi_prp_vf_mem.out_width, -+ vf.csi_prp_vf_mem.out_height, -+ vf.csi_prp_vf_mem.out_width, -+ cam->vf_rotation, -+ cam->vf_bufs[0], -+ cam->vf_bufs[1], -+ 0, 0, 0); -+ if (err != 0) { -+ printk(KERN_ERR "Error MEM_ROT_VF_MEM input buffer\n"); -+ goto out_2; -+ } -+ -+ if (cam->vf_rotation < IPU_ROTATE_90_RIGHT) { -+ temp = vf.csi_prp_vf_mem.out_width; -+ vf.csi_prp_vf_mem.out_width = -+ vf.csi_prp_vf_mem.out_height; -+ vf.csi_prp_vf_mem.out_height = temp; -+ } -+ -+ err = ipu_init_channel_buffer(cam->ipu, MEM_ROT_VF_MEM, -+ IPU_OUTPUT_BUFFER, -+ vf_out_format, -+ vf.csi_prp_vf_mem.out_height, -+ vf.csi_prp_vf_mem.out_width, -+ vf.csi_prp_vf_mem.out_height, -+ IPU_ROTATE_NONE, -+ fbi->fix.smem_start + -+ (fbi->fix.line_length * -+ fbi->var.yres), -+ fbi->fix.smem_start, 0, 0, 0); -+ -+ if (err != 0) { -+ printk(KERN_ERR "Error MEM_ROT_VF_MEM output buffer\n"); -+ goto out_2; -+ } -+ -+ ipu_clear_irq(cam->ipu, IPU_IRQ_PRP_VF_ROT_OUT_EOF); -+ err = ipu_request_irq(cam->ipu, IPU_IRQ_PRP_VF_ROT_OUT_EOF, -+ prpvf_rot_eof_callback, -+ 0, "Mxc Camera", cam); -+ if (err < 0) { -+ printk(KERN_ERR "Error request irq:IPU_IRQ_PRP_VF_ROT_OUT_EOF\n"); -+ goto out_2; -+ } -+ -+ err = ipu_link_channels(cam->ipu, -+ CSI_PRP_VF_MEM, MEM_ROT_VF_MEM); -+ if (err < 0) { -+ printk(KERN_ERR -+ "Error link CSI_PRP_VF_MEM-MEM_ROT_VF_MEM\n"); -+ goto out_1; -+ } -+ -+ ipu_enable_channel(cam->ipu, CSI_PRP_VF_MEM); -+ ipu_enable_channel(cam->ipu, MEM_ROT_VF_MEM); -+ -+ ipu_select_buffer(cam->ipu, CSI_PRP_VF_MEM, -+ IPU_OUTPUT_BUFFER, 0); -+ ipu_select_buffer(cam->ipu, CSI_PRP_VF_MEM, -+ IPU_OUTPUT_BUFFER, 1); -+ ipu_select_buffer(cam->ipu, MEM_ROT_VF_MEM, -+ IPU_OUTPUT_BUFFER, 0); -+ } else { -+ err = ipu_init_channel_buffer(cam->ipu, CSI_PRP_VF_MEM, -+ IPU_OUTPUT_BUFFER, -+ vf_out_format, cam->win.w.width, -+ cam->win.w.height, -+ cam->win.w.width, -+ cam->vf_rotation, -+ fbi->fix.smem_start + -+ (fbi->fix.line_length * -+ fbi->var.yres), -+ fbi->fix.smem_start, 0, 0, 0); -+ if (err != 0) { -+ printk(KERN_ERR "Error initializing CSI_PRP_VF_MEM\n"); -+ goto out_4; -+ } -+ ipu_clear_irq(cam->ipu, IPU_IRQ_PRP_VF_OUT_EOF); -+ err = ipu_request_irq(cam->ipu, IPU_IRQ_PRP_VF_OUT_EOF, -+ prpvf_rot_eof_callback, -+ 0, "Mxc Camera", cam); -+ if (err < 0) { -+ printk(KERN_ERR "Error request irq:IPU_IRQ_PRP_VF_OUT_EOF\n"); -+ goto out_4; -+ } -+ -+ ipu_enable_channel(cam->ipu, CSI_PRP_VF_MEM); -+ -+ ipu_select_buffer(cam->ipu, CSI_PRP_VF_MEM, -+ IPU_OUTPUT_BUFFER, 0); -+ } -+ -+ cam->overlay_active = true; -+ return err; -+ -+out_1: -+ ipu_free_irq(cam->ipu, IPU_IRQ_PRP_VF_OUT_EOF, NULL); -+out_2: -+ ipu_channel_free(&cam->ipu_chan_rot); -+out_3: -+ if (cam->vf_bufs_vaddr[0]) { -+ dma_free_coherent(0, cam->vf_bufs_size[0], -+ cam->vf_bufs_vaddr[0], -+ (dma_addr_t) cam->vf_bufs[0]); -+ cam->vf_bufs_vaddr[0] = NULL; -+ cam->vf_bufs[0] = 0; -+ } -+ if (cam->vf_bufs_vaddr[1]) { -+ dma_free_coherent(0, cam->vf_bufs_size[1], -+ cam->vf_bufs_vaddr[1], -+ (dma_addr_t) cam->vf_bufs[1]); -+ cam->vf_bufs_vaddr[1] = NULL; -+ cam->vf_bufs[1] = 0; -+ } -+out_4: -+ ipu_channel_free(&cam->ipu_chan); -+out_5: -+ return err; -+} -+ -+/*! -+ * prpvf_stop - stop the vf task -+ * -+ * @param private cam_data * mxc v4l2 main structure -+ * -+ */ -+static int prpvf_stop(void *private) -+{ -+ cam_data *cam = (cam_data *) private; -+ int err = 0, i = 0; -+ int err2; -+ struct fb_info *fbi = NULL; -+ struct fb_var_screeninfo fbvar; -+ -+ if (cam->overlay_active == false) -+ return 0; -+ -+ for (i = 0; i < num_registered_fb; i++) { -+ char *idstr = registered_fb[i]->fix.id; -+ if (((strcmp(idstr, "DISP3 FG") == 0) && (cam->output < 3)) || -+ ((strcmp(idstr, "DISP4 FG") == 0) && (cam->output >= 3))) { -+ fbi = registered_fb[i]; -+ break; -+ } -+ } -+ -+ if (fbi == NULL) { -+ printk(KERN_ERR "DISP FG fb not found\n"); -+ return -EPERM; -+ } -+ -+ if (cam->vf_rotation >= IPU_ROTATE_VERT_FLIP) { -+ ipu_unlink_channels(cam->ipu, CSI_PRP_VF_MEM, MEM_ROT_VF_MEM); -+ ipu_free_irq(cam->ipu, IPU_IRQ_PRP_VF_ROT_OUT_EOF, cam); -+ } -+ buffer_num = 0; -+ -+ ipu_channel_disable(cam->ipu_chan, true); -+ ipu_channel_disable(cam->ipu_chan_rot, true); -+ ipu_channel_free(&cam->ipu_chan_rot); -+ ipu_channel_free(&cam->ipu_chan); -+ -+ console_lock(); -+ fb_blank(fbi, FB_BLANK_POWERDOWN); -+ console_unlock(); -+ -+ /* Set the overlay frame buffer std to what it is used to be */ -+ fbvar = fbi->var; -+ fbvar.accel_flags = FB_ACCEL_TRIPLE_FLAG; -+ fbvar.nonstd = cam->fb_origin_std; -+ fbvar.activate |= FB_ACTIVATE_FORCE; -+ fb_set_var(fbi, &fbvar); -+ err2 = cam_mipi_csi2_disable(cam); -+ -+ if (cam->vf_bufs_vaddr[0]) { -+ dma_free_coherent(0, cam->vf_bufs_size[0], -+ cam->vf_bufs_vaddr[0], -+ (dma_addr_t) cam->vf_bufs[0]); -+ cam->vf_bufs_vaddr[0] = NULL; -+ cam->vf_bufs[0] = 0; -+ } -+ if (cam->vf_bufs_vaddr[1]) { -+ dma_free_coherent(0, cam->vf_bufs_size[1], -+ cam->vf_bufs_vaddr[1], -+ (dma_addr_t) cam->vf_bufs[1]); -+ cam->vf_bufs_vaddr[1] = NULL; -+ cam->vf_bufs[1] = 0; -+ } -+ -+ cam->overlay_active = false; -+ return err ? err : err2; -+} -+ -+/*! -+ * Enable csi -+ * @param private struct cam_data * mxc capture instance -+ * -+ * @return status -+ */ -+static int prp_vf_enable_csi(void *private) -+{ -+ return cam_ipu_enable_csi((cam_data *)private); -+} -+ -+/*! -+ * Disable csi -+ * @param private struct cam_data * mxc capture instance -+ * -+ * @return status -+ */ -+static int prp_vf_disable_csi(void *private) -+{ -+ cam_data *cam = (cam_data *) private; -+ -+ /* free csi eof irq firstly. -+ * when disable csi, wait for idmac eof. -+ * it requests eof irq again */ -+ if (cam->vf_rotation < IPU_ROTATE_VERT_FLIP) -+ ipu_free_irq(cam->ipu, IPU_IRQ_PRP_VF_OUT_EOF, cam); -+ return cam_ipu_disable_csi(cam); -+} -+ -+/*! -+ * function to select PRP-VF as the working path -+ * -+ * @param private cam_data * mxc v4l2 main structure -+ * -+ * @return status -+ */ -+int prp_vf_sdc_select(void *private) -+{ -+ cam_data *cam; -+ int err = 0; -+ if (private) { -+ cam = (cam_data *) private; -+ cam->vf_start_sdc = prpvf_start; -+ cam->vf_stop_sdc = prpvf_stop; -+ cam->vf_enable_csi = prp_vf_enable_csi; -+ cam->vf_disable_csi = prp_vf_disable_csi; -+ cam->overlay_active = false; -+ } else -+ err = -EIO; -+ -+ return err; -+} -+EXPORT_SYMBOL(prp_vf_sdc_select); -+ -+/*! -+ * function to de-select PRP-VF as the working path -+ * -+ * @param private cam_data * mxc v4l2 main structure -+ * -+ * @return int -+ */ -+int prp_vf_sdc_deselect(void *private) -+{ -+ cam_data *cam; -+ -+ if (private) { -+ cam = (cam_data *) private; -+ cam->vf_start_sdc = NULL; -+ cam->vf_stop_sdc = NULL; -+ cam->vf_enable_csi = NULL; -+ cam->vf_disable_csi = NULL; -+ } -+ return 0; -+} -+EXPORT_SYMBOL(prp_vf_sdc_deselect); -+ -+/*! -+ * Init viewfinder task. -+ * -+ * @return Error code indicating success or failure -+ */ -+__init int prp_vf_sdc_init(void) -+{ -+ return 0; -+} -+ -+/*! -+ * Deinit viewfinder task. -+ * -+ * @return Error code indicating success or failure -+ */ -+void __exit prp_vf_sdc_exit(void) -+{ -+} -+ -+module_init(prp_vf_sdc_init); -+module_exit(prp_vf_sdc_exit); -+ -+MODULE_AUTHOR("Freescale Semiconductor, Inc."); -+MODULE_DESCRIPTION("IPU PRP VF SDC Driver"); -+MODULE_LICENSE("GPL"); -diff -Nur linux-4.1.13.orig/drivers/media/platform/mxc/capture/ipu_still.c linux-4.1.13/drivers/media/platform/mxc/capture/ipu_still.c ---- linux-4.1.13.orig/drivers/media/platform/mxc/capture/ipu_still.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/media/platform/mxc/capture/ipu_still.c 2015-11-30 17:56:13.600136395 +0100 -@@ -0,0 +1,269 @@ -+/* -+ * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved. -+ */ -+ -+/* -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/*! -+ * @file ipu_still.c -+ * -+ * @brief IPU Use case for still image capture -+ * -+ * @ingroup IPU -+ */ -+ -+#include -+#include -+#include -+#include -+#include "mxc_v4l2_capture.h" -+#include "ipu_prp_sw.h" -+ -+static int callback_eof_flag; -+#ifndef CONFIG_MXC_IPU_V1 -+static int buffer_num; -+#endif -+ -+#ifdef CONFIG_MXC_IPU_V1 -+static int callback_flag; -+/* -+ * Function definitions -+ */ -+/*! -+ * CSI EOF callback function. -+ * -+ * @param irq int irq line -+ * @param dev_id void * device id -+ * -+ * @return status IRQ_HANDLED for handled -+ */ -+static irqreturn_t prp_csi_eof_callback(int irq, void *dev_id) -+{ -+ cam_data *cam = devid; -+ ipu_select_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER, -+ callback_flag%2 ? 1 : 0); -+ if (callback_flag == 0) -+ ipu_enable_channel(cam->ipu, CSI_MEM); -+ -+ callback_flag++; -+ return IRQ_HANDLED; -+} -+#endif -+ -+/*! -+ * CSI callback function. -+ * -+ * @param irq int irq line -+ * @param dev_id void * device id -+ * -+ * @return status IRQ_HANDLED for handled -+ */ -+static irqreturn_t prp_still_callback(int irq, void *dev_id) -+{ -+ cam_data *cam = (cam_data *) dev_id; -+ -+ callback_eof_flag++; -+ if (callback_eof_flag < 5) { -+#ifndef CONFIG_MXC_IPU_V1 -+ buffer_num = (buffer_num == 0) ? 1 : 0; -+ ipu_select_buffer(cam->ipu, CSI_MEM, -+ IPU_OUTPUT_BUFFER, buffer_num); -+#endif -+ } else { -+ cam->still_counter++; -+ wake_up_interruptible(&cam->still_queue); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+/*! -+ * start csi->mem task -+ * @param private struct cam_data * mxc capture instance -+ * -+ * @return status -+ */ -+static int prp_still_start(void *private) -+{ -+ cam_data *cam = (cam_data *) private; -+ u32 pixel_fmt; -+ int err; -+ ipu_channel_params_t params; -+ -+ if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420) -+ pixel_fmt = IPU_PIX_FMT_YUV420P; -+ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_NV12) -+ pixel_fmt = IPU_PIX_FMT_NV12; -+ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV422P) -+ pixel_fmt = IPU_PIX_FMT_YUV422P; -+ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_UYVY) -+ pixel_fmt = IPU_PIX_FMT_UYVY; -+ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_YUYV) -+ pixel_fmt = IPU_PIX_FMT_YUYV; -+ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_BGR24) -+ pixel_fmt = IPU_PIX_FMT_BGR24; -+ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB24) -+ pixel_fmt = IPU_PIX_FMT_RGB24; -+ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB565) -+ pixel_fmt = IPU_PIX_FMT_RGB565; -+ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_BGR32) -+ pixel_fmt = IPU_PIX_FMT_BGR32; -+ else if (cam->v2f.fmt.pix.pixelformat == V4L2_PIX_FMT_RGB32) -+ pixel_fmt = IPU_PIX_FMT_RGB32; -+ else { -+ printk(KERN_ERR "format not supported\n"); -+ return -EINVAL; -+ } -+ -+ memset(¶ms, 0, sizeof(params)); -+ err = ipu_channel_request(cam->ipu, CSI_MEM, ¶ms, &cam->ipu_chan); -+ if (err) { -+ pr_err("%s:ipu_channel_request %d\n", __func__, err); -+ return err; -+ } -+ -+ err = ipu_init_channel_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER, -+ pixel_fmt, cam->v2f.fmt.pix.width, -+ cam->v2f.fmt.pix.height, -+ cam->v2f.fmt.pix.width, IPU_ROTATE_NONE, -+ cam->still_buf[0], cam->still_buf[1], 0, -+ 0, 0); -+ if (err != 0) -+ return err; -+ -+#ifdef CONFIG_MXC_IPU_V1 -+ ipu_clear_irq(IPU_IRQ_SENSOR_OUT_EOF); -+ err = ipu_request_irq(IPU_IRQ_SENSOR_OUT_EOF, prp_still_callback, -+ 0, "Mxc Camera", cam); -+ if (err != 0) { -+ printk(KERN_ERR "Error registering irq.\n"); -+ return err; -+ } -+ callback_flag = 0; -+ callback_eof_flag = 0; -+ ipu_clear_irq(IPU_IRQ_SENSOR_EOF); -+ err = ipu_request_irq(IPU_IRQ_SENSOR_EOF, prp_csi_eof_callback, -+ 0, "Mxc Camera", cam); -+ if (err != 0) { -+ printk(KERN_ERR "Error IPU_IRQ_SENSOR_EOF\n"); -+ return err; -+ } -+#else -+ callback_eof_flag = 0; -+ buffer_num = 0; -+ -+ ipu_clear_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF); -+ err = ipu_request_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF, -+ prp_still_callback, -+ 0, "Mxc Camera", cam); -+ if (err != 0) { -+ printk(KERN_ERR "Error registering irq.\n"); -+ return err; -+ } -+ -+ ipu_select_buffer(cam->ipu, CSI_MEM, IPU_OUTPUT_BUFFER, 0); -+ ipu_enable_channel(cam->ipu, CSI_MEM); -+ cam_ipu_enable_csi(cam); -+#endif -+ -+ return err; -+} -+ -+/*! -+ * stop csi->mem encoder task -+ * @param private struct cam_data * mxc capture instance -+ * -+ * @return status -+ */ -+static int prp_still_stop(void *private) -+{ -+ cam_data *cam = (cam_data *) private; -+ int err = 0; -+ -+#ifdef CONFIG_MXC_IPU_V1 -+ ipu_free_irq(IPU_IRQ_SENSOR_EOF, NULL); -+ ipu_free_irq(IPU_IRQ_SENSOR_OUT_EOF, cam); -+#else -+ ipu_free_irq(cam->ipu, IPU_IRQ_CSI0_OUT_EOF, cam); -+#endif -+ -+ cam_ipu_disable_csi(cam); -+ ipu_channel_disable(cam->ipu_chan, true); -+ ipu_channel_free(&cam->ipu_chan); -+ return err; -+} -+ -+/*! -+ * function to select CSI_MEM as the working path -+ * -+ * @param private struct cam_data * mxc capture instance -+ * -+ * @return status -+ */ -+int prp_still_select(void *private) -+{ -+ cam_data *cam = (cam_data *) private; -+ -+ if (cam) { -+ cam->csi_start = prp_still_start; -+ cam->csi_stop = prp_still_stop; -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL(prp_still_select); -+ -+/*! -+ * function to de-select CSI_MEM as the working path -+ * -+ * @param private struct cam_data * mxc capture instance -+ * -+ * @return status -+ */ -+int prp_still_deselect(void *private) -+{ -+ cam_data *cam = (cam_data *) private; -+ int err = 0; -+ -+ err = prp_still_stop(cam); -+ -+ if (cam) { -+ cam->csi_start = NULL; -+ cam->csi_stop = NULL; -+ } -+ -+ return err; -+} -+EXPORT_SYMBOL(prp_still_deselect); -+ -+/*! -+ * Init the Encorder channels -+ * -+ * @return Error code indicating success or failure -+ */ -+__init int prp_still_init(void) -+{ -+ return 0; -+} -+ -+/*! -+ * Deinit the Encorder channels -+ * -+ */ -+void __exit prp_still_exit(void) -+{ -+} -+ -+module_init(prp_still_init); -+module_exit(prp_still_exit); -+ -+MODULE_AUTHOR("Freescale Semiconductor, Inc."); -+MODULE_DESCRIPTION("IPU PRP STILL IMAGE Driver"); -+MODULE_LICENSE("GPL"); -diff -Nur linux-4.1.13.orig/drivers/media/platform/mxc/capture/Kconfig linux-4.1.13/drivers/media/platform/mxc/capture/Kconfig ---- linux-4.1.13.orig/drivers/media/platform/mxc/capture/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/media/platform/mxc/capture/Kconfig 2015-11-30 17:56:13.600136395 +0100 -@@ -0,0 +1,106 @@ -+if VIDEO_MXC_CAPTURE -+ -+menu "MXC Camera/V4L2 PRP Features support" -+config VIDEO_MXC_IPU_CAMERA -+ bool -+ depends on VIDEO_MXC_CAPTURE && MXC_IPU -+ default y -+ -+config VIDEO_MXC_CSI_CAMERA -+ tristate "CSI camera support" -+ depends on VIDEO_MXC_CAPTURE && VIDEO_V4L2 -+ ---help--- -+ This is the video4linux2 capture driver based on CSI module. -+ -+config MXC_TVIN_TDA1997X -+ tristate "NXP TDA1997x HDMI Receiver Input support" -+ depends on I2C -+ ---help--- -+ If you plan to use the NXP tda1997x/tdf1997x HDMI reciever with your i -+ -+config MXC_CAMERA_OV5640 -+ tristate "OmniVision ov5640 camera support" -+ depends on !VIDEO_MXC_EMMA_CAMERA && I2C -+ ---help--- -+ If you plan to use the ov5640 Camera with your MXC system, say Y here. -+ -+config MXC_CAMERA_OV5642 -+ tristate "OmniVision ov5642 camera support" -+ depends on !VIDEO_MXC_EMMA_CAMERA && I2C -+ ---help--- -+ If you plan to use the ov5642 Camera with your MXC system, say Y here. -+ -+config MXC_CAMERA_OV5640_MIPI -+ tristate "OmniVision ov5640 camera support using mipi" -+ depends on !VIDEO_MXC_EMMA_CAMERA && I2C -+ ---help--- -+ If you plan to use the ov5640 Camera with mipi interface in your MXC system, say Y here. -+ -+config MXC_CAMERA_OV5647_MIPI -+ tristate "OmniVision ov5647 camera support using mipi" -+ depends on !VIDEO_MXC_EMMA_CAMERA && I2C -+ ---help--- -+ If you plan to use the ov5647 Camera with mipi interface in your MXC system, say Y here. -+ -+config MXC_HDMI_CSI2_TC358743 -+ tristate "Toshiba tc358743 Hdmi to CSI 2 bridge" -+ depends on !VIDEO_MXC_EMMA_CAMERA && I2C -+ select MXC_MIPI_CSI2 if ARCH_MX6Q -+ select MXC_CAMERA_SENSOR_CLK -+ ---help--- -+ Toshina HDMI to MIPI-CSI2 bridge -+ -+config MXC_TVIN_ADV7180 -+ tristate "Analog Device adv7180 TV Decoder Input support" -+ depends on !VIDEO_MXC_EMMA_CAMERA && I2C -+ ---help--- -+ If you plan to use the adv7180 video decoder with your MXC system, say Y here. -+ -+choice -+ prompt "Select Overlay Rounting" -+ default MXC_IPU_DEVICE_QUEUE_SDC -+ depends on VIDEO_MXC_IPU_CAMERA && FB_MXC_SYNC_PANEL -+ -+config MXC_IPU_DEVICE_QUEUE_SDC -+ tristate "Queue ipu device for overlay library" -+ depends on VIDEO_MXC_IPU_CAMERA -+ ---help--- -+ Use case CSI->MEM->IPU DEVICE->SDC: -+ Images from sensor will be frist recieved in memory,then -+ queue to ipu device for processing if needed, and displaying -+ it on synchronous display with SDC use case. -+ -+config MXC_IPU_PRP_VF_SDC -+ bool "Pre-Processor VF SDC library" -+ depends on VIDEO_MXC_IPU_CAMERA -+ ---help--- -+ Use case PRP_VF_SDC: -+ Preprocessing image from smart sensor for viewfinder and -+ displaying it on synchronous display with SDC use case. -+ If SDC BG is selected, Rotation will not be supported. -+ CSI -> IC (PRP VF) -> MEM -+ MEM -> IC (ROT) -> MEM -+ MEM -> SDC (FG/BG) -+ -+endchoice -+ -+config MXC_IPU_PRP_ENC -+ tristate "Pre-processor Encoder library" -+ depends on VIDEO_MXC_IPU_CAMERA -+ default y -+ ---help--- -+ Use case PRP_ENC: -+ Preprocessing image from smart sensor for encoder. -+ CSI -> IC (PRP ENC) -> MEM -+ -+config MXC_IPU_CSI_ENC -+ tristate "IPU CSI Encoder library" -+ depends on VIDEO_MXC_IPU_CAMERA -+ default y -+ ---help--- -+ Use case IPU_CSI_ENC: -+ Get raw image with CSI from smart sensor for encoder. -+ CSI -> MEM -+endmenu -+ -+endif -diff -Nur linux-4.1.13.orig/drivers/media/platform/mxc/capture/Makefile linux-4.1.13/drivers/media/platform/mxc/capture/Makefile ---- linux-4.1.13.orig/drivers/media/platform/mxc/capture/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/media/platform/mxc/capture/Makefile 2015-11-30 17:56:13.600136395 +0100 -@@ -0,0 +1,32 @@ -+obj-$(CONFIG_VIDEO_MXC_CSI_CAMERA) += fsl_csi.o csi_v4l2_capture.o -+ -+ifeq ($(CONFIG_VIDEO_MXC_IPU_CAMERA),y) -+ obj-$(CONFIG_VIDEO_MXC_CAPTURE) += mxc_v4l2_capture.o -+ obj-$(CONFIG_MXC_IPU_PRP_VF_SDC) += ipu_prp_vf_sdc.o ipu_prp_vf_sdc_bg.o -+ obj-$(CONFIG_MXC_IPU_DEVICE_QUEUE_SDC) += ipu_fg_overlay_sdc.o ipu_bg_overlay_sdc.o -+ obj-$(CONFIG_MXC_IPU_PRP_ENC) += ipu_prp_enc.o ipu_still.o -+ obj-$(CONFIG_MXC_IPU_CSI_ENC) += ipu_csi_enc.o ipu_still.o -+endif -+ -+ov5640_camera-objs := ov5640.o -+obj-$(CONFIG_MXC_CAMERA_OV5640) += ov5640_camera.o -+ -+ov5642_camera-objs := ov5642.o -+obj-$(CONFIG_MXC_CAMERA_OV5642) += ov5642_camera.o -+ -+ov5640_camera_mipi-objs := ov5640_mipi.o -+obj-$(CONFIG_MXC_CAMERA_OV5640_MIPI) += ov5640_camera_mipi.o -+ -+ov5647_camera_mipi-objs := ov5647_mipi.o -+obj-$(CONFIG_MXC_CAMERA_OV5647_MIPI) += ov5647_camera_mipi.o -+ -+tc358743_h2c_bridge-objs := tc358743_h2c.o -+obj-$(CONFIG_MXC_HDMI_CSI2_TC358743) += tc358743_h2c_bridge.o -+ -+adv7180_tvin-objs := adv7180.o -+obj-$(CONFIG_MXC_TVIN_ADV7180) += adv7180_tvin.o -+ -+obj-$(CONFIG_VIDEO_V4L2_INT_DEVICE) += v4l2-int-device.o -+ -+tda1997x-video-objs := tda1997x.o -+obj-$(CONFIG_MXC_TVIN_TDA1997X) += tda1997x-video.o -diff -Nur linux-4.1.13.orig/drivers/media/platform/mxc/capture/mxc_v4l2_capture.c linux-4.1.13/drivers/media/platform/mxc/capture/mxc_v4l2_capture.c ---- linux-4.1.13.orig/drivers/media/platform/mxc/capture/mxc_v4l2_capture.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/media/platform/mxc/capture/mxc_v4l2_capture.c 2015-11-30 17:56:13.604136128 +0100 -@@ -0,0 +1,3384 @@ -+/* -+ * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved. -+ */ -+ -+/* -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/*! -+ * @file drivers/media/video/mxc/capture/mxc_v4l2_capture.c -+ * -+ * @brief Mxc Video For Linux 2 driver -+ * -+ * @ingroup MXC_V4L2_CAPTURE -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "v4l2-int-device.h" -+#include -+#include "mxc_v4l2_capture.h" -+#include "../v4l2-extra.h" -+#include "ipu_prp_sw.h" -+ -+#define init_MUTEX(sem) sema_init(sem, 1) -+ -+static struct platform_device_id imx_v4l2_devtype[] = { -+ { -+ .name = "v4l2-capture-imx5", -+ .driver_data = IMX5_V4L2, -+ }, { -+ .name = "v4l2-capture-imx6", -+ .driver_data = IMX6_V4L2, -+ }, { -+ /* sentinel */ -+ } -+}; -+MODULE_DEVICE_TABLE(platform, imx_v4l2_devtype); -+ -+static const struct of_device_id mxc_v4l2_dt_ids[] = { -+ { -+ .compatible = "fsl,imx6q-v4l2-capture", -+ .data = &imx_v4l2_devtype[IMX6_V4L2], -+ }, { -+ /* sentinel */ -+ } -+}; -+MODULE_DEVICE_TABLE(of, mxc_v4l2_dt_ids); -+ -+static int video_nr = -1; -+ -+/*! This data is used for the output to the display. */ -+#define MXC_V4L2_CAPTURE_NUM_OUTPUTS 6 -+#define MXC_V4L2_CAPTURE_NUM_INPUTS 2 -+static struct v4l2_output mxc_capture_outputs[MXC_V4L2_CAPTURE_NUM_OUTPUTS] = { -+ { -+ .index = 0, -+ .name = "DISP3 BG", -+ .type = V4L2_OUTPUT_TYPE_ANALOG, -+ .audioset = 0, -+ .modulator = 0, -+ .std = V4L2_STD_UNKNOWN, -+ }, -+ { -+ .index = 1, -+ .name = "DISP3 BG - DI1", -+ .type = V4L2_OUTPUT_TYPE_ANALOG, -+ .audioset = 0, -+ .modulator = 0, -+ .std = V4L2_STD_UNKNOWN, -+ }, -+ { -+ .index = 2, -+ .name = "DISP3 FG", -+ .type = V4L2_OUTPUT_TYPE_ANALOG, -+ .audioset = 0, -+ .modulator = 0, -+ .std = V4L2_STD_UNKNOWN, -+ }, -+ { -+ .index = 3, -+ .name = "DISP4 BG", -+ .type = V4L2_OUTPUT_TYPE_ANALOG, -+ .audioset = 0, -+ .modulator = 0, -+ .std = V4L2_STD_UNKNOWN, -+ }, -+ { -+ .index = 4, -+ .name = "DISP4 BG - DI1", -+ .type = V4L2_OUTPUT_TYPE_ANALOG, -+ .audioset = 0, -+ .modulator = 0, -+ .std = V4L2_STD_UNKNOWN, -+ }, -+ { -+ .index = 5, -+ .name = "DISP4 FG", -+ .type = V4L2_OUTPUT_TYPE_ANALOG, -+ .audioset = 0, -+ .modulator = 0, -+ .std = V4L2_STD_UNKNOWN, -+ }, -+}; -+ -+static struct v4l2_input mxc_capture_inputs[MXC_V4L2_CAPTURE_NUM_INPUTS] = { -+ { -+ .index = 0, -+ .name = "CSI IC MEM", -+ .type = V4L2_INPUT_TYPE_CAMERA, -+ .audioset = 0, -+ .tuner = 0, -+ .std = V4L2_STD_UNKNOWN, -+ .status = 0, -+ }, -+ { -+ .index = 1, -+ .name = "CSI MEM", -+ .type = V4L2_INPUT_TYPE_CAMERA, -+ .audioset = 0, -+ .tuner = 0, -+ .std = V4L2_STD_UNKNOWN, -+ .status = V4L2_IN_ST_NO_POWER, -+ }, -+}; -+ -+/*! List of TV input video formats supported. The video formats is corresponding -+ * to the v4l2_id in video_fmt_t. -+ * Currently, only PAL and NTSC is supported. Needs to be expanded in the -+ * future. -+ */ -+typedef enum { -+ TV_NTSC = 0, /*!< Locked on (M) NTSC video signal. */ -+ TV_PAL, /*!< (B, G, H, I, N)PAL video signal. */ -+ TV_NOT_LOCKED, /*!< Not locked on a signal. */ -+} video_fmt_idx; -+ -+/*! Number of video standards supported (including 'not locked' signal). */ -+#define TV_STD_MAX (TV_NOT_LOCKED + 1) -+ -+/*! Video format structure. */ -+typedef struct { -+ int v4l2_id; /*!< Video for linux ID. */ -+ char name[16]; /*!< Name (e.g., "NTSC", "PAL", etc.) */ -+ u16 raw_width; /*!< Raw width. */ -+ u16 raw_height; /*!< Raw height. */ -+ u16 active_width; /*!< Active width. */ -+ u16 active_height; /*!< Active height. */ -+ u16 active_top; /*!< Active top. */ -+ u16 active_left; /*!< Active left. */ -+} video_fmt_t; -+ -+/*! -+ * Description of video formats supported. -+ * -+ * PAL: raw=720x625, active=720x576. -+ * NTSC: raw=720x525, active=720x480. -+ */ -+static video_fmt_t video_fmts[] = { -+ { /*! NTSC */ -+ .v4l2_id = V4L2_STD_NTSC, -+ .name = "NTSC", -+ .raw_width = 720, /* SENS_FRM_WIDTH */ -+ .raw_height = 525, /* SENS_FRM_HEIGHT */ -+ .active_width = 720, /* ACT_FRM_WIDTH */ -+ .active_height = 480, /* ACT_FRM_HEIGHT */ -+ .active_top = 0, -+ .active_left = 0, -+ }, -+ { /*! (B, G, H, I, N) PAL */ -+ .v4l2_id = V4L2_STD_PAL, -+ .name = "PAL", -+ .raw_width = 720, -+ .raw_height = 625, -+ .active_width = 720, -+ .active_height = 576, -+ .active_top = 0, -+ .active_left = 0, -+ }, -+ { /*! Unlocked standard */ -+ .v4l2_id = V4L2_STD_ALL, -+ .name = "Autodetect", -+ .raw_width = 720, -+ .raw_height = 625, -+ .active_width = 720, -+ .active_height = 576, -+ .active_top = 0, -+ .active_left = 0, -+ }, -+}; -+ -+/*!* Standard index of TV. */ -+static video_fmt_idx video_index = TV_NOT_LOCKED; -+ -+static int mxc_v4l2_master_attach(struct v4l2_int_device *slave); -+static void mxc_v4l2_master_detach(struct v4l2_int_device *slave); -+static int start_preview(cam_data *cam); -+static int stop_preview(cam_data *cam); -+ -+/*! Information about this driver. */ -+static struct v4l2_int_master mxc_v4l2_master = { -+ .attach = mxc_v4l2_master_attach, -+ .detach = mxc_v4l2_master_detach, -+}; -+ -+/*************************************************************************** -+ * Functions for handling Frame buffers. -+ **************************************************************************/ -+ -+/*! -+ * Free frame buffers -+ * -+ * @param cam Structure cam_data * -+ * -+ * @return status 0 success. -+ */ -+static int mxc_free_frame_buf(cam_data *cam) -+{ -+ int i; -+ -+ pr_debug("%s\n", __func__); -+ -+ for (i = 0; i < FRAME_NUM; i++) { -+ if (cam->frame[i].vaddress != 0) { -+ dma_free_coherent(0, cam->frame[i].buffer.length, -+ cam->frame[i].vaddress, -+ cam->frame[i].paddress); -+ cam->frame[i].vaddress = 0; -+ } -+ } -+ -+ return 0; -+} -+ -+/*! -+ * Allocate frame buffers -+ * -+ * @param cam Structure cam_data* -+ * @param count int number of buffer need to allocated -+ * -+ * @return status -0 Successfully allocated a buffer, -ENOBUFS failed. -+ */ -+static int mxc_allocate_frame_buf(cam_data *cam, int count) -+{ -+ int i; -+ u32 map_sizeimage; -+ struct sensor_data *sensor = cam->sensor->priv; -+ -+ if (sensor && sensor->adata) { -+ const struct additional_data *adata = sensor->adata; -+ map_sizeimage = adata->map_sizeimage; -+ } -+ else { -+ map_sizeimage = cam->v2f.fmt.pix.sizeimage; -+ } -+ -+ pr_debug("%s: size=%d\n", __func__, map_sizeimage); -+ -+ for (i = 0; i < count; i++) { -+ cam->frame[i].vaddress = -+ dma_alloc_coherent(0, -+ PAGE_ALIGN(map_sizeimage), -+ &cam->frame[i].paddress, -+ GFP_DMA | GFP_KERNEL); -+ if (cam->frame[i].vaddress == 0) { -+ pr_err("%s: failed.\n", __func__); -+ mxc_free_frame_buf(cam); -+ return -ENOBUFS; -+ } -+ cam->frame[i].buffer.index = i; -+ cam->frame[i].buffer.flags = V4L2_BUF_FLAG_MAPPED; -+ cam->frame[i].buffer.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; -+ cam->frame[i].buffer.length = PAGE_ALIGN(map_sizeimage); -+ cam->frame[i].buffer.memory = V4L2_MEMORY_MMAP; -+ cam->frame[i].buffer.m.offset = cam->frame[i].paddress; -+ cam->frame[i].index = i; -+ } -+ -+ return 0; -+} -+ -+/*! -+ * Free frame buffers status -+ * -+ * @param cam Structure cam_data * -+ * -+ * @return none -+ */ -+static void mxc_free_frames(cam_data *cam) -+{ -+ int i; -+ -+ pr_debug("%s\n", __func__); -+ -+ for (i = 0; i < FRAME_NUM; i++) -+ cam->frame[i].buffer.flags = V4L2_BUF_FLAG_MAPPED; -+ -+ cam->enc_counter = 0; -+ INIT_LIST_HEAD(&cam->ready_q); -+ INIT_LIST_HEAD(&cam->working_q); -+ INIT_LIST_HEAD(&cam->done_q); -+} -+ -+/*! -+ * Return the buffer status -+ * -+ * @param cam Structure cam_data * -+ * @param buf Structure v4l2_buffer * -+ * -+ * @return status 0 success, EINVAL failed. -+ */ -+static int mxc_v4l2_buffer_status(cam_data *cam, struct v4l2_buffer *buf) -+{ -+ pr_debug("%s\n", __func__); -+ -+ if (buf->index < 0 || buf->index >= FRAME_NUM) { -+ pr_err("ERROR: v4l2 capture: mxc_v4l2_buffer_status buffers " -+ "not allocated\n"); -+ return -EINVAL; -+ } -+ -+ memcpy(buf, &(cam->frame[buf->index].buffer), sizeof(*buf)); -+ return 0; -+} -+ -+static int mxc_v4l2_release_bufs(cam_data *cam) -+{ -+ pr_debug("%s\n", __func__); -+ return 0; -+} -+ -+static int mxc_v4l2_prepare_bufs(cam_data *cam, struct v4l2_buffer *buf) -+{ -+ pr_debug("%s\n", __func__); -+ -+ if (buf->index < 0 || buf->index >= FRAME_NUM || buf->length < -+ cam->v2f.fmt.pix.sizeimage) { -+ pr_err("ERROR: v4l2 capture: mxc_v4l2_prepare_bufs buffers " -+ "not allocated,index=%d, length=%d\n", buf->index, -+ buf->length); -+ return -EINVAL; -+ } -+ -+ cam->frame[buf->index].buffer.index = buf->index; -+ cam->frame[buf->index].buffer.flags = V4L2_BUF_FLAG_MAPPED; -+ cam->frame[buf->index].buffer.length = buf->length; -+ cam->frame[buf->index].buffer.m.offset = cam->frame[buf->index].paddress -+ = buf->m.offset; -+ cam->frame[buf->index].buffer.type = buf->type; -+ cam->frame[buf->index].buffer.memory = V4L2_MEMORY_USERPTR; -+ cam->frame[buf->index].index = buf->index; -+ -+ return 0; -+} -+ -+/*************************************************************************** -+ * Functions for handling the video stream. -+ **************************************************************************/ -+ -+/*! -+ * Indicates whether the palette is supported. -+ * -+ * @param palette V4L2_PIX_FMT_RGB565, V4L2_PIX_FMT_BGR24 or V4L2_PIX_FMT_BGR32 -+ * -+ * @return 0 if failed -+ */ -+static inline int valid_mode(u32 palette) -+{ -+ return ((palette == V4L2_PIX_FMT_RGB565) || -+ (palette == V4L2_PIX_FMT_BGR24) || -+ (palette == V4L2_PIX_FMT_RGB24) || -+ (palette == V4L2_PIX_FMT_BGR32) || -+ (palette == V4L2_PIX_FMT_RGB32) || -+ (palette == V4L2_PIX_FMT_YUV422P) || -+ (palette == V4L2_PIX_FMT_UYVY) || -+ (palette == V4L2_PIX_FMT_YUYV) || -+ (palette == V4L2_PIX_FMT_YUV420) || -+ (palette == V4L2_PIX_FMT_YVU420) || -+ (palette == V4L2_PIX_FMT_NV12 || -+ palette == V4L2_PIX_FMT_SBGGR8)); -+} -+ -+/*! -+ * Start the encoder job -+ * -+ * @param cam structure cam_data * -+ * -+ * @return status 0 Success -+ */ -+static int mxc_streamon(cam_data *cam) -+{ -+ struct mxc_v4l_frame *frame; -+ unsigned long lock_flags; -+ int err = 0; -+ -+ pr_debug("%s\n", __func__); -+ -+ if (NULL == cam) { -+ pr_err("ERROR! cam parameter is NULL\n"); -+ return -1; -+ } -+ -+ if (cam->capture_on) { -+ pr_err("ERROR: v4l2 capture: Capture stream has been turned " -+ " on\n"); -+ return -1; -+ } -+ -+ if (list_empty(&cam->ready_q)) { -+ pr_err("ERROR: v4l2 capture: mxc_streamon buffer has not been " -+ "queued yet\n"); -+ return -EINVAL; -+ } -+ if (cam->enc_update_eba && -+ cam->ready_q.prev == cam->ready_q.next) { -+ pr_err("ERROR: v4l2 capture: mxc_streamon buffer need " -+ "ping pong at least two buffers\n"); -+ return -EINVAL; -+ } -+ -+ cam->capture_pid = current->pid; -+ -+ if (cam->overlay_on == true) -+ stop_preview(cam); -+ -+ if (cam->enc_enable) { -+ err = cam->enc_enable(cam); -+ if (err != 0) -+ return err; -+ } -+ -+ spin_lock_irqsave(&cam->queue_int_lock, lock_flags); -+ cam->ping_pong_csi = 0; -+ cam->local_buf_num = 0; -+ if (cam->enc_update_eba) { -+ frame = -+ list_entry(cam->ready_q.next, struct mxc_v4l_frame, queue); -+ list_del(cam->ready_q.next); -+ list_add_tail(&frame->queue, &cam->working_q); -+ frame->ipu_buf_num = cam->ping_pong_csi; -+ err = cam->enc_update_eba(cam->ipu, frame->buffer.m.offset, -+ &cam->ping_pong_csi); -+ -+ frame = -+ list_entry(cam->ready_q.next, struct mxc_v4l_frame, queue); -+ list_del(cam->ready_q.next); -+ list_add_tail(&frame->queue, &cam->working_q); -+ frame->ipu_buf_num = cam->ping_pong_csi; -+ err |= cam->enc_update_eba(cam->ipu, frame->buffer.m.offset, -+ &cam->ping_pong_csi); -+ spin_unlock_irqrestore(&cam->queue_int_lock, lock_flags); -+ } else { -+ spin_unlock_irqrestore(&cam->queue_int_lock, lock_flags); -+ return -EINVAL; -+ } -+ -+ if (cam->overlay_on == true) -+ start_preview(cam); -+ -+ if (cam->enc_enable_csi) { -+ err = cam->enc_enable_csi(cam); -+ if (err != 0) -+ return err; -+ } -+ -+ cam->capture_on = true; -+ -+ return err; -+} -+ -+/*! -+ * Shut down the encoder job -+ * -+ * @param cam structure cam_data * -+ * -+ * @return status 0 Success -+ */ -+static int mxc_streamoff(cam_data *cam) -+{ -+ int err = 0; -+ -+ pr_debug("%s: ipu%d/csi%d capture_on=%d %s\n", __func__, cam->ipu_id, -+ cam->csi, cam->capture_on, -+ mxc_capture_inputs[cam->current_input].name); -+ if (cam->capture_on == false) -+ return 0; -+ /* For both CSI--MEM and CSI--IC--MEM -+ * 1. wait for idmac eof -+ * 2. disable csi first -+ * 3. disable idmac -+ * 4. disable smfc (CSI--MEM channel) -+ */ -+ if (mxc_capture_inputs[cam->current_input].name != NULL) { -+ if (cam->enc_disable_csi) { -+ err = cam->enc_disable_csi(cam); -+ if (err != 0) -+ return err; -+ } -+ if (cam->enc_disable) { -+ err = cam->enc_disable(cam); -+ if (err != 0) -+ return err; -+ } -+ } -+ -+ mxc_free_frames(cam); -+ mxc_capture_inputs[cam->current_input].status |= V4L2_IN_ST_NO_POWER; -+ cam->capture_on = false; -+ return err; -+} -+ -+/*! -+ * Valid and adjust the overlay window size, position -+ * -+ * @param cam structure cam_data * -+ * @param win struct v4l2_window * -+ * -+ * @return 0 -+ */ -+static int verify_preview(cam_data *cam, struct v4l2_window *win) -+{ -+ int i = 0, width_bound = 0, height_bound = 0; -+ int *width, *height; -+ unsigned int ipu_ch = CHAN_NONE; -+ struct fb_info *bg_fbi = NULL, *fbi = NULL; -+ bool foregound_fb = false; -+ mm_segment_t old_fs; -+ -+ pr_debug("%s\n", __func__); -+ -+ do { -+ fbi = (struct fb_info *)registered_fb[i]; -+ if (fbi == NULL) { -+ pr_err("ERROR: verify_preview frame buffer NULL.\n"); -+ return -1; -+ } -+ -+ /* Which DI supports 2 layers? */ -+ if (((strncmp(fbi->fix.id, "DISP3 BG", 8) == 0) && -+ (cam->output < 3)) || -+ ((strncmp(fbi->fix.id, "DISP4 BG", 8) == 0) && -+ (cam->output >= 3))) { -+ if (fbi->fbops->fb_ioctl) { -+ old_fs = get_fs(); -+ set_fs(KERNEL_DS); -+ fbi->fbops->fb_ioctl(fbi, MXCFB_GET_FB_IPU_CHAN, -+ (unsigned long)&ipu_ch); -+ set_fs(old_fs); -+ } -+ if (ipu_ch == MEM_BG_SYNC) { -+ bg_fbi = fbi; -+ pr_debug("Found background frame buffer.\n"); -+ } -+ } -+ -+ /* Found the frame buffer to preview on. */ -+ if (strcmp(fbi->fix.id, -+ mxc_capture_outputs[cam->output].name) == 0) { -+ if (((strcmp(fbi->fix.id, "DISP3 FG") == 0) && -+ (cam->output < 3)) || -+ ((strcmp(fbi->fix.id, "DISP4 FG") == 0) && -+ (cam->output >= 3))) -+ foregound_fb = true; -+ -+ cam->overlay_fb = fbi; -+ break; -+ } -+ } while (++i < FB_MAX); -+ -+ if (foregound_fb) { -+ width_bound = bg_fbi->var.xres; -+ height_bound = bg_fbi->var.yres; -+ -+ if (win->w.width + win->w.left > bg_fbi->var.xres || -+ win->w.height + win->w.top > bg_fbi->var.yres) { -+ pr_err("ERROR: FG window position exceeds.\n"); -+ return -1; -+ } -+ } else { -+ /* 4 bytes alignment for BG */ -+ width_bound = cam->overlay_fb->var.xres; -+ height_bound = cam->overlay_fb->var.yres; -+ -+ if (cam->overlay_fb->var.bits_per_pixel == 24) -+ win->w.left -= win->w.left % 4; -+ else if (cam->overlay_fb->var.bits_per_pixel == 16) -+ win->w.left -= win->w.left % 2; -+ -+ if (win->w.width + win->w.left > cam->overlay_fb->var.xres) -+ win->w.width = cam->overlay_fb->var.xres - win->w.left; -+ if (win->w.height + win->w.top > cam->overlay_fb->var.yres) -+ win->w.height = cam->overlay_fb->var.yres - win->w.top; -+ } -+ -+ /* stride line limitation */ -+ win->w.height -= win->w.height % 8; -+ win->w.width -= win->w.width % 8; -+ -+ if (cam->rotation >= IPU_ROTATE_90_RIGHT) { -+ height = &win->w.width; -+ width = &win->w.height; -+ } else { -+ width = &win->w.width; -+ height = &win->w.height; -+ } -+ -+ if (*width == 0 || *height == 0) { -+ pr_err("ERROR: v4l2 capture: width or height" -+ " too small.\n"); -+ return -EINVAL; -+ } -+ -+ if ((cam->crop_bounds.width / *width > 8) || -+ ((cam->crop_bounds.width / *width == 8) && -+ (cam->crop_bounds.width % *width))) { -+ *width = cam->crop_bounds.width / 8; -+ if (*width % 8) -+ *width += 8 - *width % 8; -+ if (*width + win->w.left > width_bound) { -+ pr_err("ERROR: v4l2 capture: width exceeds " -+ "resize limit.\n"); -+ return -1; -+ } -+ pr_err("ERROR: v4l2 capture: width exceeds limit. " -+ "Resize to %d.\n", -+ *width); -+ } -+ -+ if ((cam->crop_bounds.height / *height > 8) || -+ ((cam->crop_bounds.height / *height == 8) && -+ (cam->crop_bounds.height % *height))) { -+ *height = cam->crop_bounds.height / 8; -+ if (*height % 8) -+ *height += 8 - *height % 8; -+ if (*height + win->w.top > height_bound) { -+ pr_err("ERROR: v4l2 capture: height exceeds " -+ "resize limit.\n"); -+ return -1; -+ } -+ pr_err("ERROR: v4l2 capture: height exceeds limit " -+ "resize to %d.\n", -+ *height); -+ } -+ -+ return 0; -+} -+ -+/*! -+ * start the viewfinder job -+ * -+ * @param cam structure cam_data * -+ * -+ * @return status 0 Success -+ */ -+static int start_preview(cam_data *cam) -+{ -+ int err = 0; -+ -+ pr_debug("MVC: start_preview\n"); -+ -+ if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_OVERLAY) -+ #ifdef CONFIG_MXC_IPU_PRP_VF_SDC -+ err = prp_vf_sdc_select(cam); -+ #else -+ err = foreground_sdc_select(cam); -+ #endif -+ else if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_PRIMARY) -+ #ifdef CONFIG_MXC_IPU_PRP_VF_SDC -+ err = prp_vf_sdc_select_bg(cam); -+ #else -+ err = bg_overlay_sdc_select(cam); -+ #endif -+ if (err != 0) -+ return err; -+ -+ if (cam->vf_start_sdc) { -+ err = cam->vf_start_sdc(cam); -+ if (err != 0) -+ return err; -+ } -+ -+ if (cam->vf_enable_csi) -+ err = cam->vf_enable_csi(cam); -+ -+ pr_debug("End of %s: v2f pix widthxheight %d x %d\n", -+ __func__, -+ cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height); -+ pr_debug("End of %s: crop_bounds widthxheight %d x %d\n", -+ __func__, -+ cam->crop_bounds.width, cam->crop_bounds.height); -+ pr_debug("End of %s: crop_defrect widthxheight %d x %d\n", -+ __func__, -+ cam->crop_defrect.width, cam->crop_defrect.height); -+ pr_debug("End of %s: crop_current widthxheight %d x %d\n", -+ __func__, -+ cam->crop_current.width, cam->crop_current.height); -+ -+ return err; -+} -+ -+/*! -+ * shut down the viewfinder job -+ * -+ * @param cam structure cam_data * -+ * -+ * @return status 0 Success -+ */ -+static int stop_preview(cam_data *cam) -+{ -+ int err = 0; -+ -+ if (cam->vf_disable_csi) { -+ err = cam->vf_disable_csi(cam); -+ if (err != 0) -+ return err; -+ } -+ -+ if (cam->vf_stop_sdc) { -+ err = cam->vf_stop_sdc(cam); -+ if (err != 0) -+ return err; -+ } -+ -+ if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_OVERLAY) -+ #ifdef CONFIG_MXC_IPU_PRP_VF_SDC -+ err = prp_vf_sdc_deselect(cam); -+ #else -+ err = foreground_sdc_deselect(cam); -+ #endif -+ else if (cam->v4l2_fb.flags == V4L2_FBUF_FLAG_PRIMARY) -+ #ifdef CONFIG_MXC_IPU_PRP_VF_SDC -+ err = prp_vf_sdc_deselect_bg(cam); -+ #else -+ err = bg_overlay_sdc_deselect(cam); -+ #endif -+ -+ return err; -+} -+ -+/*************************************************************************** -+ * VIDIOC Functions. -+ **************************************************************************/ -+ -+/*! -+ * V4L2 - mxc_v4l2_g_fmt function -+ * -+ * @param cam structure cam_data * -+ * -+ * @param f structure v4l2_format * -+ * -+ * @return status 0 success, EINVAL failed -+ */ -+static int mxc_v4l2_g_fmt(cam_data *cam, struct v4l2_format *f) -+{ -+ int retval = 0; -+ -+ pr_debug("%s: type=%d\n", __func__, f->type); -+ -+ switch (f->type) { -+ case V4L2_BUF_TYPE_VIDEO_CAPTURE: -+ pr_debug(" type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n"); -+ f->fmt.pix = cam->v2f.fmt.pix; -+ break; -+ case V4L2_BUF_TYPE_VIDEO_OVERLAY: -+ pr_debug(" type is V4L2_BUF_TYPE_VIDEO_OVERLAY\n"); -+ f->fmt.win = cam->win; -+ break; -+ default: -+ pr_debug(" type is invalid\n"); -+ retval = -EINVAL; -+ } -+ -+ pr_debug("End of %s: v2f pix widthxheight %d x %d\n", -+ __func__, -+ cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height); -+ pr_debug("End of %s: crop_bounds widthxheight %d x %d\n", -+ __func__, -+ cam->crop_bounds.width, cam->crop_bounds.height); -+ pr_debug("End of %s: crop_defrect widthxheight %d x %d\n", -+ __func__, -+ cam->crop_defrect.width, cam->crop_defrect.height); -+ pr_debug("End of %s: crop_current widthxheight %d x %d\n", -+ __func__, -+ cam->crop_current.width, cam->crop_current.height); -+ -+ return retval; -+} -+ -+/*! -+ * V4L2 - mxc_v4l2_s_fmt function -+ * -+ * @param cam structure cam_data * -+ * -+ * @param f structure v4l2_format * -+ * -+ * @return status 0 success, EINVAL failed -+ */ -+static int mxc_v4l2_s_fmt(cam_data *cam, struct v4l2_format *f, bool try_fmt) -+{ -+ int retval = 0; -+ int size = 0; -+ int bytesperline = 0; -+ int *width, *height; -+ -+ pr_debug("%s\n", __func__); -+ -+ switch (f->type) { -+ case V4L2_BUF_TYPE_VIDEO_CAPTURE: -+ pr_debug(" type=V4L2_BUF_TYPE_VIDEO_CAPTURE\n"); -+ if (!valid_mode(f->fmt.pix.pixelformat)) { -+ pr_err("ERROR: v4l2 capture: mxc_v4l2_s_fmt: format " -+ "not supported\n"); -+ return -EINVAL; -+ } -+ -+ /* -+ * Force the capture window resolution to be crop bounds -+ * for CSI MEM input mode. -+ */ -+ if (strcmp(mxc_capture_inputs[cam->current_input].name, -+ "CSI MEM") == 0) { -+ f->fmt.pix.width = cam->crop_current.width; -+ f->fmt.pix.height = cam->crop_current.height; -+ } -+ -+ if (cam->rotation >= IPU_ROTATE_90_RIGHT) { -+ height = &f->fmt.pix.width; -+ width = &f->fmt.pix.height; -+ } else { -+ width = &f->fmt.pix.width; -+ height = &f->fmt.pix.height; -+ } -+ -+ /* stride line limitation */ -+ *width -= *width % 8; -+ *height -= *height % 8; -+ -+ if (*width == 0 || *height == 0) { -+ pr_err("ERROR: v4l2 capture: width or height" -+ " too small.\n"); -+ return -EINVAL; -+ } -+ -+ if ((cam->crop_current.width / *width > 8) || -+ ((cam->crop_current.width / *width == 8) && -+ (cam->crop_current.width % *width))) { -+ *width = cam->crop_current.width / 8; -+ if (*width % 8) -+ *width += 8 - *width % 8; -+ pr_err("ERROR: v4l2 capture: width exceeds limit " -+ "resize to %d.\n", -+ *width); -+ } -+ -+ if ((cam->crop_current.height / *height > 8) || -+ ((cam->crop_current.height / *height == 8) && -+ (cam->crop_current.height % *height))) { -+ *height = cam->crop_current.height / 8; -+ if (*height % 8) -+ *height += 8 - *height % 8; -+ pr_err("ERROR: v4l2 capture: height exceeds limit " -+ "resize to %d.\n", -+ *height); -+ } -+ -+ switch (f->fmt.pix.pixelformat) { -+ case V4L2_PIX_FMT_RGB565: -+ size = f->fmt.pix.width * f->fmt.pix.height * 2; -+ bytesperline = f->fmt.pix.width * 2; -+ break; -+ case V4L2_PIX_FMT_BGR24: -+ size = f->fmt.pix.width * f->fmt.pix.height * 3; -+ bytesperline = f->fmt.pix.width * 3; -+ break; -+ case V4L2_PIX_FMT_RGB24: -+ size = f->fmt.pix.width * f->fmt.pix.height * 3; -+ bytesperline = f->fmt.pix.width * 3; -+ break; -+ case V4L2_PIX_FMT_BGR32: -+ size = f->fmt.pix.width * f->fmt.pix.height * 4; -+ bytesperline = f->fmt.pix.width * 4; -+ break; -+ case V4L2_PIX_FMT_RGB32: -+ size = f->fmt.pix.width * f->fmt.pix.height * 4; -+ bytesperline = f->fmt.pix.width * 4; -+ break; -+ case V4L2_PIX_FMT_YUV422P: -+ size = f->fmt.pix.width * f->fmt.pix.height * 2; -+ bytesperline = f->fmt.pix.width; -+ break; -+ case V4L2_PIX_FMT_UYVY: -+ case V4L2_PIX_FMT_YUYV: -+ size = f->fmt.pix.width * f->fmt.pix.height * 2; -+ bytesperline = f->fmt.pix.width * 2; -+ break; -+ case V4L2_PIX_FMT_YUV420: -+ case V4L2_PIX_FMT_YVU420: -+ size = f->fmt.pix.width * f->fmt.pix.height * 3 / 2; -+ bytesperline = f->fmt.pix.width; -+ break; -+ case V4L2_PIX_FMT_NV12: -+ size = f->fmt.pix.width * f->fmt.pix.height * 3 / 2; -+ bytesperline = f->fmt.pix.width; -+ break; -+ case V4L2_PIX_FMT_SBGGR8: -+ size = f->fmt.pix.width * f->fmt.pix.height; -+ bytesperline = f->fmt.pix.width; -+ break; -+ default: -+ break; -+ } -+ -+ if (f->fmt.pix.bytesperline < bytesperline) -+ f->fmt.pix.bytesperline = bytesperline; -+ else -+ bytesperline = f->fmt.pix.bytesperline; -+ -+ if (try_fmt) { -+ /* XXX: workaround for gstreamer */ -+ if (f->fmt.pix.sizeimage < size || -+ f->fmt.pix.sizeimage % size) -+ f->fmt.pix.sizeimage = size; -+ else -+ size = f->fmt.pix.sizeimage; -+ -+ break; -+ } -+ else { -+ if (f->fmt.pix.sizeimage < size) -+ f->fmt.pix.sizeimage = size; -+ else -+ size = f->fmt.pix.sizeimage; -+ } -+ -+ cam->v2f.fmt.pix = f->fmt.pix; -+ -+ if (cam->v2f.fmt.pix.priv != 0) { -+ if (copy_from_user(&cam->offset, -+ (void *)cam->v2f.fmt.pix.priv, -+ sizeof(cam->offset))) { -+ retval = -EFAULT; -+ break; -+ } -+ } -+ break; -+ case V4L2_BUF_TYPE_VIDEO_OVERLAY: -+ pr_debug(" type=V4L2_BUF_TYPE_VIDEO_OVERLAY\n"); -+ retval = verify_preview(cam, &f->fmt.win); -+ if (!try_fmt) -+ cam->win = f->fmt.win; -+ break; -+ default: -+ retval = -EINVAL; -+ } -+ -+ pr_debug("End of %s: v2f pix widthxheight %d x %d\n", -+ __func__, -+ cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height); -+ pr_debug("End of %s: crop_bounds widthxheight %d x %d\n", -+ __func__, -+ cam->crop_bounds.width, cam->crop_bounds.height); -+ pr_debug("End of %s: crop_defrect widthxheight %d x %d\n", -+ __func__, -+ cam->crop_defrect.width, cam->crop_defrect.height); -+ pr_debug("End of %s: crop_current widthxheight %d x %d\n", -+ __func__, -+ cam->crop_current.width, cam->crop_current.height); -+ -+ return retval; -+} -+ -+/*! -+ * get control param -+ * -+ * @param cam structure cam_data * -+ * -+ * @param c structure v4l2_control * -+ * -+ * @return status 0 success, EINVAL failed -+ */ -+static int mxc_v4l2_g_ctrl(cam_data *cam, struct v4l2_control *c) -+{ -+ int status = 0; -+ -+ pr_debug("%s\n", __func__); -+ -+ /* probably don't need to store the values that can be retrieved, -+ * locally, but they are for now. */ -+ switch (c->id) { -+ case V4L2_CID_HFLIP: -+ /* This is handled in the ipu. */ -+ if (cam->rotation == IPU_ROTATE_HORIZ_FLIP) -+ c->value = 1; -+ break; -+ case V4L2_CID_VFLIP: -+ /* This is handled in the ipu. */ -+ if (cam->rotation == IPU_ROTATE_VERT_FLIP) -+ c->value = 1; -+ break; -+ case V4L2_CID_MXC_ROT: -+ /* This is handled in the ipu. */ -+ c->value = cam->rotation; -+ break; -+ case V4L2_CID_BRIGHTNESS: -+ if (cam->sensor) { -+ c->value = cam->bright; -+ status = vidioc_int_g_ctrl(cam->sensor, c); -+ cam->bright = c->value; -+ } else { -+ pr_err("ERROR: v4l2 capture: slave not found!\n"); -+ status = -ENODEV; -+ } -+ break; -+ case V4L2_CID_HUE: -+ if (cam->sensor) { -+ c->value = cam->hue; -+ status = vidioc_int_g_ctrl(cam->sensor, c); -+ cam->hue = c->value; -+ } else { -+ pr_err("ERROR: v4l2 capture: slave not found!\n"); -+ status = -ENODEV; -+ } -+ break; -+ case V4L2_CID_CONTRAST: -+ if (cam->sensor) { -+ c->value = cam->contrast; -+ status = vidioc_int_g_ctrl(cam->sensor, c); -+ cam->contrast = c->value; -+ } else { -+ pr_err("ERROR: v4l2 capture: slave not found!\n"); -+ status = -ENODEV; -+ } -+ break; -+ case V4L2_CID_SATURATION: -+ if (cam->sensor) { -+ c->value = cam->saturation; -+ status = vidioc_int_g_ctrl(cam->sensor, c); -+ cam->saturation = c->value; -+ } else { -+ pr_err("ERROR: v4l2 capture: slave not found!\n"); -+ status = -ENODEV; -+ } -+ break; -+ case V4L2_CID_RED_BALANCE: -+ if (cam->sensor) { -+ c->value = cam->red; -+ status = vidioc_int_g_ctrl(cam->sensor, c); -+ cam->red = c->value; -+ } else { -+ pr_err("ERROR: v4l2 capture: slave not found!\n"); -+ status = -ENODEV; -+ } -+ break; -+ case V4L2_CID_BLUE_BALANCE: -+ if (cam->sensor) { -+ c->value = cam->blue; -+ status = vidioc_int_g_ctrl(cam->sensor, c); -+ cam->blue = c->value; -+ } else { -+ pr_err("ERROR: v4l2 capture: slave not found!\n"); -+ status = -ENODEV; -+ } -+ break; -+ case V4L2_CID_BLACK_LEVEL: -+ if (cam->sensor) { -+ c->value = cam->ae_mode; -+ status = vidioc_int_g_ctrl(cam->sensor, c); -+ cam->ae_mode = c->value; -+ } else { -+ pr_err("ERROR: v4l2 capture: slave not found!\n"); -+ status = -ENODEV; -+ } -+ break; -+ default: -+ pr_err("ERROR: v4l2 capture: unsupported ioctrl!\n"); -+ } -+ -+ return status; -+} -+ -+static int mxc_v4l2_send_command(cam_data *cam, -+ struct v4l2_send_command_control *c) { -+ int ret =0; -+ -+ if (vidioc_int_send_command(cam->sensor, c)) { -+ ret = -EINVAL; -+ } -+ return ret; -+} -+ -+/*! -+ * V4L2 - set_control function -+ * V4L2_CID_PRIVATE_BASE is the extention for IPU preprocessing. -+ * 0 for normal operation -+ * 1 for vertical flip -+ * 2 for horizontal flip -+ * 3 for horizontal and vertical flip -+ * 4 for 90 degree rotation -+ * @param cam structure cam_data * -+ * -+ * @param c structure v4l2_control * -+ * -+ * @return status 0 success, EINVAL failed -+ */ -+static int mxc_v4l2_s_ctrl(cam_data *cam, struct v4l2_control *c) -+{ -+ int i, ret = 0; -+ int tmp_rotation = IPU_ROTATE_NONE; -+ struct sensor_data *sensor_data; -+ -+ pr_debug("%s\n", __func__); -+ -+ switch (c->id) { -+ case V4L2_CID_HFLIP: -+ /* This is done by the IPU */ -+ if (c->value == 1) { -+ if ((cam->rotation != IPU_ROTATE_VERT_FLIP) && -+ (cam->rotation != IPU_ROTATE_180)) -+ cam->rotation = IPU_ROTATE_HORIZ_FLIP; -+ else -+ cam->rotation = IPU_ROTATE_180; -+ } else { -+ if (cam->rotation == IPU_ROTATE_HORIZ_FLIP) -+ cam->rotation = IPU_ROTATE_NONE; -+ if (cam->rotation == IPU_ROTATE_180) -+ cam->rotation = IPU_ROTATE_VERT_FLIP; -+ } -+ break; -+ case V4L2_CID_VFLIP: -+ /* This is done by the IPU */ -+ if (c->value == 1) { -+ if ((cam->rotation != IPU_ROTATE_HORIZ_FLIP) && -+ (cam->rotation != IPU_ROTATE_180)) -+ cam->rotation = IPU_ROTATE_VERT_FLIP; -+ else -+ cam->rotation = IPU_ROTATE_180; -+ } else { -+ if (cam->rotation == IPU_ROTATE_VERT_FLIP) -+ cam->rotation = IPU_ROTATE_NONE; -+ if (cam->rotation == IPU_ROTATE_180) -+ cam->rotation = IPU_ROTATE_HORIZ_FLIP; -+ } -+ break; -+ case V4L2_CID_MXC_ROT: -+ case V4L2_CID_MXC_VF_ROT: -+ /* This is done by the IPU */ -+ switch (c->value) { -+ case V4L2_MXC_ROTATE_NONE: -+ tmp_rotation = IPU_ROTATE_NONE; -+ break; -+ case V4L2_MXC_ROTATE_VERT_FLIP: -+ tmp_rotation = IPU_ROTATE_VERT_FLIP; -+ break; -+ case V4L2_MXC_ROTATE_HORIZ_FLIP: -+ tmp_rotation = IPU_ROTATE_HORIZ_FLIP; -+ break; -+ case V4L2_MXC_ROTATE_180: -+ tmp_rotation = IPU_ROTATE_180; -+ break; -+ case V4L2_MXC_ROTATE_90_RIGHT: -+ tmp_rotation = IPU_ROTATE_90_RIGHT; -+ break; -+ case V4L2_MXC_ROTATE_90_RIGHT_VFLIP: -+ tmp_rotation = IPU_ROTATE_90_RIGHT_VFLIP; -+ break; -+ case V4L2_MXC_ROTATE_90_RIGHT_HFLIP: -+ tmp_rotation = IPU_ROTATE_90_RIGHT_HFLIP; -+ break; -+ case V4L2_MXC_ROTATE_90_LEFT: -+ tmp_rotation = IPU_ROTATE_90_LEFT; -+ break; -+ case V4L2_MXC_CAM_ROTATE_NONE: -+ if (vidioc_int_s_ctrl(cam->sensor, c)) { -+ ret = -EINVAL; -+ } -+ break; -+ case V4L2_MXC_CAM_ROTATE_VERT_FLIP: -+ if (vidioc_int_s_ctrl(cam->sensor, c)) { -+ ret = -EINVAL; -+ } -+ break; -+ case V4L2_MXC_CAM_ROTATE_HORIZ_FLIP: -+ if (vidioc_int_s_ctrl(cam->sensor, c)) { -+ ret = -EINVAL; -+ } -+ break; -+ case V4L2_MXC_CAM_ROTATE_180: -+ if (vidioc_int_s_ctrl(cam->sensor, c)) { -+ ret = -EINVAL; -+ } -+ break; -+ default: -+ ret = -EINVAL; -+ } -+ #ifdef CONFIG_MXC_IPU_PRP_VF_SDC -+ if (c->id == V4L2_CID_MXC_VF_ROT) -+ cam->vf_rotation = tmp_rotation; -+ else -+ cam->rotation = tmp_rotation; -+ #else -+ cam->rotation = tmp_rotation; -+ #endif -+ -+ break; -+ case V4L2_CID_HUE: -+ if (cam->sensor) { -+ cam->hue = c->value; -+ ret = vidioc_int_s_ctrl(cam->sensor, c); -+ } else { -+ pr_err("ERROR: v4l2 capture: slave not found!\n"); -+ ret = -ENODEV; -+ } -+ break; -+ case V4L2_CID_CONTRAST: -+ if (cam->sensor) { -+ cam->contrast = c->value; -+ ret = vidioc_int_s_ctrl(cam->sensor, c); -+ } else { -+ pr_err("ERROR: v4l2 capture: slave not found!\n"); -+ ret = -ENODEV; -+ } -+ break; -+ case V4L2_CID_BRIGHTNESS: -+ if (cam->sensor) { -+ cam->bright = c->value; -+ ret = vidioc_int_s_ctrl(cam->sensor, c); -+ } else { -+ pr_err("ERROR: v4l2 capture: slave not found!\n"); -+ ret = -ENODEV; -+ } -+ break; -+ case V4L2_CID_SATURATION: -+ if (cam->sensor) { -+ cam->saturation = c->value; -+ ret = vidioc_int_s_ctrl(cam->sensor, c); -+ } else { -+ pr_err("ERROR: v4l2 capture: slave not found!\n"); -+ ret = -ENODEV; -+ } -+ break; -+ case V4L2_CID_RED_BALANCE: -+ if (cam->sensor) { -+ cam->red = c->value; -+ ret = vidioc_int_s_ctrl(cam->sensor, c); -+ } else { -+ pr_err("ERROR: v4l2 capture: slave not found!\n"); -+ ret = -ENODEV; -+ } -+ break; -+ case V4L2_CID_BLUE_BALANCE: -+ if (cam->sensor) { -+ cam->blue = c->value; -+ ret = vidioc_int_s_ctrl(cam->sensor, c); -+ } else { -+ pr_err("ERROR: v4l2 capture: slave not found!\n"); -+ ret = -ENODEV; -+ } -+ break; -+ case V4L2_CID_EXPOSURE: -+ if (cam->sensor) { -+ cam->ae_mode = c->value; -+ ret = vidioc_int_s_ctrl(cam->sensor, c); -+ } else { -+ pr_err("ERROR: v4l2 capture: slave not found!\n"); -+ ret = -ENODEV; -+ } -+ break; -+ case V4L2_CID_MXC_FLASH: -+#ifdef CONFIG_MXC_IPU_V1 -+ ipu_csi_flash_strobe(true); -+#endif -+ break; -+ -+ case V4L2_CID_AUTO_FOCUS_START: { -+ ret = vidioc_int_s_ctrl(cam->sensor, c); -+ break; -+ } -+ -+ case V4L2_CID_AUTO_FOCUS_STOP: { -+ if (vidioc_int_s_ctrl(cam->sensor, c)) { -+ ret = -EINVAL; -+ } -+ break; -+ } -+ -+ case V4L2_CID_MXC_SWITCH_CAM: -+ if (cam->sensor == cam->all_sensors[c->value]) -+ break; -+ -+ /* power down other cameraes before enable new one */ -+ for (i = 0; i < cam->sensor_index; i++) { -+ if (i != c->value) { -+ vidioc_int_dev_exit(cam->all_sensors[i]); -+ vidioc_int_s_power(cam->all_sensors[i], 0); -+ if (cam->mclk_on[cam->mclk_source]) { -+ ipu_csi_enable_mclk_if(cam->ipu, -+ CSI_MCLK_I2C, -+ cam->mclk_source, -+ false, false); -+ cam->mclk_on[cam->mclk_source] = -+ false; -+ } -+ } -+ } -+ sensor_data = cam->all_sensors[c->value]->priv; -+ if (sensor_data->io_init) -+ sensor_data->io_init(); -+ cam->sensor = cam->all_sensors[c->value]; -+ cam->mclk_source = sensor_data->mclk_source; -+ ipu_csi_enable_mclk_if(cam->ipu, CSI_MCLK_I2C, -+ cam->mclk_source, true, true); -+ cam->mclk_on[cam->mclk_source] = true; -+ vidioc_int_s_power(cam->sensor, 1); -+ vidioc_int_dev_init(cam->sensor); -+ break; -+ default: -+ pr_debug(" default case\n"); -+ ret = -EINVAL; -+ break; -+ } -+ -+ return ret; -+} -+ -+void setup_ifparm(cam_data *cam, int init_defrect) -+{ -+ struct v4l2_format cam_fmt; -+ ipu_csi_signal_cfg_t csi_param; -+ struct v4l2_ifparm ifparm; -+ int swidth, sheight; -+ int sleft, stop; -+ -+ vidioc_int_g_ifparm(cam->sensor, &ifparm); -+ memset(&csi_param, 0, sizeof(csi_param)); -+ csi_param.csi = cam->csi; -+ csi_param.mclk = ifparm.u.bt656.clock_curr; -+ -+ pr_debug(" clock_curr=mclk=%d\n", ifparm.u.bt656.clock_curr); -+ switch (ifparm.if_type) { -+ case V4L2_IF_TYPE_BT1120_PROGRESSIVE_DDR: -+ csi_param.clk_mode = IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR; -+ break; -+ case V4L2_IF_TYPE_BT1120_PROGRESSIVE_SDR: -+ csi_param.clk_mode = IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR; -+ break; -+ case V4L2_IF_TYPE_BT1120_INTERLACED_DDR: -+ csi_param.clk_mode = IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR; -+ break; -+ case V4L2_IF_TYPE_BT1120_INTERLACED_SDR: -+ csi_param.clk_mode = IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR; -+ break; -+ case V4L2_IF_TYPE_BT656_PROGRESSIVE: -+ csi_param.clk_mode = IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE; -+ break; -+ case V4L2_IF_TYPE_BT656_INTERLACED: -+ csi_param.clk_mode = IPU_CSI_CLK_MODE_CCIR656_INTERLACED; -+ break; -+ case V4L2_IF_TYPE_BT656: -+// csi_param.clk_mode = IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE; -+// break; -+ default: -+ if (ifparm.u.bt656.clock_curr == 0) { -+ csi_param.clk_mode = IPU_CSI_CLK_MODE_CCIR656_INTERLACED; -+ /*protocol bt656 use 27Mhz pixel clock */ -+ csi_param.mclk = 27000000; -+ } else if (ifparm.u.bt656.clock_curr == 1) { -+ csi_param.clk_mode = IPU_CSI_CLK_MODE_GATED_CLK; -+ } else -+ csi_param.clk_mode = IPU_CSI_CLK_MODE_GATED_CLK; -+ } -+ -+ csi_param.pixclk_pol = ifparm.u.bt656.latch_clk_inv; -+ -+ csi_param.data_width = -+ (ifparm.u.bt656.mode == V4L2_IF_TYPE_BT656_MODE_NOBT_10BIT) || -+ (ifparm.u.bt656.mode == V4L2_IF_TYPE_BT656_MODE_BT_10BIT) ? -+ IPU_CSI_DATA_WIDTH_10 : IPU_CSI_DATA_WIDTH_8; -+ -+ csi_param.pack_tight = (csi_param.data_width == IPU_CSI_DATA_WIDTH_10) ? 1 : 0; -+ -+ csi_param.Vsync_pol = ifparm.u.bt656.nobt_vs_inv; -+ csi_param.Hsync_pol = ifparm.u.bt656.nobt_hs_inv; -+ csi_param.ext_vsync = ifparm.u.bt656.bt_sync_correct; -+ pr_debug("vsync_pol(%d) hsync_pol(%d) ext_vsync(%d)\n", csi_param.Vsync_pol, csi_param.Hsync_pol, csi_param.ext_vsync); -+ -+ /* if the capturemode changed, the size bounds will have changed. */ -+ cam_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; -+ vidioc_int_g_fmt_cap(cam->sensor, &cam_fmt); -+ pr_debug(" g_fmt_cap returns widthxheight of input as %d x %d\n", -+ cam_fmt.fmt.pix.width, cam_fmt.fmt.pix.height); -+ -+ switch (cam_fmt.fmt.pix.pixelformat) { -+ case V4L2_PIX_FMT_RGB565: -+ csi_param.data_fmt = IPU_PIX_FMT_RGB565; -+ break; -+ case V4L2_PIX_FMT_BGR24: -+ csi_param.data_fmt = IPU_PIX_FMT_BGR24; -+ break; -+ case V4L2_PIX_FMT_RGB24: -+ csi_param.data_fmt = IPU_PIX_FMT_RGB24; -+ break; -+ case V4L2_PIX_FMT_BGR32: -+ csi_param.data_fmt = IPU_PIX_FMT_BGR32; -+ break; -+ case V4L2_PIX_FMT_RGB32: -+ csi_param.data_fmt = IPU_PIX_FMT_RGB32; -+ break; -+ case V4L2_PIX_FMT_YUV422P: -+ csi_param.data_fmt = IPU_PIX_FMT_YUV422P; -+ break; -+ case V4L2_PIX_FMT_UYVY: -+ csi_param.data_fmt = IPU_PIX_FMT_UYVY; -+ break; -+ case V4L2_PIX_FMT_YUYV: -+ csi_param.data_fmt = IPU_PIX_FMT_YUYV; -+ break; -+ case V4L2_PIX_FMT_YUV420: -+ csi_param.data_fmt = IPU_PIX_FMT_YUV420P; -+ break; -+ case V4L2_PIX_FMT_YVU420: -+ csi_param.data_fmt = IPU_PIX_FMT_YVU420P;; -+ break; -+ case V4L2_PIX_FMT_NV12: -+ csi_param.data_fmt = IPU_PIX_FMT_NV12; -+ break; -+ case V4L2_PIX_FMT_SBGGR8: -+ default: -+ csi_param.data_fmt = IPU_PIX_FMT_GENERIC; -+ break; -+ } -+ -+ cam->crop_bounds.top = cam->crop_bounds.left = 0; -+ cam->crop_bounds.width = cam_fmt.fmt.pix.width; -+ cam->crop_bounds.height = cam_fmt.fmt.pix.height; -+ -+ /* -+ * Set the default current cropped resolution to be the same with -+ * the cropping boundary(except for tvin module). -+ */ -+ if (cam->device_type != 1) { -+ cam->crop_current.width = cam->crop_bounds.width; -+ cam->crop_current.height = cam->crop_bounds.height; -+ } -+ -+ if (init_defrect) { -+ /* This also is the max crop size for this device. */ -+ cam->crop_defrect.top = cam->crop_defrect.left = 0; -+ cam->crop_defrect.width = cam_fmt.fmt.pix.width; -+ cam->crop_defrect.height = cam_fmt.fmt.pix.height; -+ -+ /* At this point, this is also the current image size. */ -+ cam->crop_current.top = cam->crop_current.left = 0; -+ cam->crop_current.width = cam_fmt.fmt.pix.width; -+ cam->crop_current.height = cam_fmt.fmt.pix.height; -+ pr_debug("On Open: Input to ipu size is %d x %d\n", -+ cam_fmt.fmt.pix.width, cam_fmt.fmt.pix.height); -+ pr_debug("End of %s: v2f pix widthxheight %d x %d\n", __func__, -+ cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height); -+ pr_debug("End of %s: crop_bounds widthxheight %d x %d\n", __func__, -+ cam->crop_bounds.width, cam->crop_bounds.height); -+ pr_debug("End of %s: crop_defrect widthxheight %d x %d\n", __func__, -+ cam->crop_defrect.width, cam->crop_defrect.height); -+ pr_debug("End of %s: crop_current widthxheight %d x %d\n", __func__, -+ cam->crop_current.width, cam->crop_current.height); -+ } -+ swidth = cam->crop_current.width; -+ sheight = cam->crop_current.height; -+ sleft = 0; -+ stop = 0; -+ cam_fmt.type = V4L2_BUF_TYPE_SENSOR; -+ cam_fmt.fmt.spix.swidth = 0; -+ vidioc_int_g_fmt_cap(cam->sensor, &cam_fmt); -+ if (cam_fmt.fmt.spix.swidth) { -+ swidth = cam_fmt.fmt.spix.swidth; -+ sheight = cam_fmt.fmt.spix.sheight; -+ sleft = cam_fmt.fmt.spix.left; -+ stop = cam_fmt.fmt.spix.top; -+ } -+ /* This essentially loses the data at the left and bottom of the image -+ * giving a digital zoom image, if crop_current is less than the full -+ * size of the image. */ -+ ipu_csi_window_size_crop(cam->ipu, -+ swidth, sheight, -+ cam->crop_current.width, cam->crop_current.height, -+ sleft + cam->crop_current.left, stop + cam->crop_current.top, -+ cam->csi); -+ ipu_csi_init_interface(cam->ipu, cam->crop_bounds.width, -+ cam->crop_bounds.height, -+ csi_param.data_fmt, csi_param); -+} -+ -+/*! -+ * V4L2 - mxc_v4l2_s_param function -+ * Allows setting of capturemode and frame rate. -+ * -+ * @param cam structure cam_data * -+ * @param parm structure v4l2_streamparm * -+ * -+ * @return status 0 success, EINVAL failed -+ */ -+static int mxc_v4l2_s_param(cam_data *cam, struct v4l2_streamparm *parm) -+{ -+ struct v4l2_streamparm currentparm; -+ u32 current_fps, parm_fps; -+ int err = 0; -+ -+ pr_debug("%s\n", __func__); -+ -+ if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { -+ pr_err(KERN_ERR "mxc_v4l2_s_param invalid type\n"); -+ return -EINVAL; -+ } -+ -+ /* Stop the viewfinder */ -+ if (cam->overlay_on == true) -+ stop_preview(cam); -+ -+ currentparm.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; -+ -+ /* First check that this device can support the changes requested. */ -+ err = vidioc_int_g_parm(cam->sensor, ¤tparm); -+ if (err) { -+ pr_err("%s: vidioc_int_g_parm returned an error %d\n", -+ __func__, err); -+ goto exit; -+ } -+ -+ current_fps = currentparm.parm.capture.timeperframe.denominator -+ / currentparm.parm.capture.timeperframe.numerator; -+ parm_fps = parm->parm.capture.timeperframe.denominator -+ / parm->parm.capture.timeperframe.numerator; -+ -+ pr_debug(" Current capabilities are %x\n", -+ currentparm.parm.capture.capability); -+ pr_debug(" Current capturemode is %d change to %d\n", -+ currentparm.parm.capture.capturemode, -+ parm->parm.capture.capturemode); -+ pr_debug(" Current framerate is %d change to %d\n", -+ current_fps, parm_fps); -+ -+ /* This will change any camera settings needed. */ -+ err = vidioc_int_s_parm(cam->sensor, parm); -+ if (err) { -+ pr_err("%s: vidioc_int_s_parm returned an error %d\n", -+ __func__, err); -+ goto exit; -+ } -+ -+ /* If resolution changed, need to re-program the CSI */ -+ /* Get new values. */ -+ setup_ifparm(cam, 0); -+ -+exit: -+ if (cam->overlay_on == true) -+ start_preview(cam); -+ -+ return err; -+} -+ -+/*! -+ * V4L2 - mxc_v4l2_s_std function -+ * -+ * Sets the TV standard to be used. -+ * -+ * @param cam structure cam_data * -+ * @param parm structure v4l2_streamparm * -+ * -+ * @return status 0 success, EINVAL failed -+ */ -+static int mxc_v4l2_s_std(cam_data *cam, v4l2_std_id e) -+{ -+ pr_debug("%s: %Lx\n", __func__, e); -+ switch (e) { -+ case V4L2_STD_PAL: -+ pr_debug(" Setting standard to PAL %Lx\n", V4L2_STD_PAL); -+ cam->standard.id = V4L2_STD_PAL; -+ video_index = TV_PAL; -+ break; -+ case V4L2_STD_NTSC: -+ pr_debug(" Setting standard to NTSC %Lx\n", -+ V4L2_STD_NTSC); -+ /* Get rid of the white dot line in NTSC signal input */ -+ cam->standard.id = V4L2_STD_NTSC; -+ video_index = TV_NTSC; -+ break; -+ case V4L2_STD_UNKNOWN: -+ case V4L2_STD_ALL: -+ /* auto-detect don't report an error */ -+ cam->standard.id = V4L2_STD_ALL; -+ video_index = TV_NOT_LOCKED; -+ break; -+ default: -+ cam->standard.id = V4L2_STD_ALL; -+ video_index = TV_NOT_LOCKED; -+ pr_err("ERROR: unrecognized std! %Lx (PAL=%Lx, NTSC=%Lx\n", -+ e, V4L2_STD_PAL, V4L2_STD_NTSC); -+ } -+ -+ cam->standard.index = video_index; -+ strcpy(cam->standard.name, video_fmts[video_index].name); -+ cam->crop_bounds.width = video_fmts[video_index].raw_width; -+ cam->crop_bounds.height = video_fmts[video_index].raw_height; -+ cam->crop_current.width = video_fmts[video_index].active_width; -+ cam->crop_current.height = video_fmts[video_index].active_height; -+ cam->crop_current.top = video_fmts[video_index].active_top; -+ cam->crop_current.left = video_fmts[video_index].active_left; -+ -+ return 0; -+} -+ -+/*! -+ * V4L2 - mxc_v4l2_g_std function -+ * -+ * Gets the TV standard from the TV input device. -+ * -+ * @param cam structure cam_data * -+ * -+ * @param e structure v4l2_streamparm * -+ * -+ * @return status 0 success, EINVAL failed -+ */ -+static int mxc_v4l2_g_std(cam_data *cam, v4l2_std_id *e) -+{ -+ struct v4l2_format tv_fmt; -+ -+ pr_debug("%s\n", __func__); -+ -+ if (cam->device_type == 1) { -+ /* Use this function to get what the TV-In device detects the -+ * format to be. pixelformat is used to return the std value -+ * since the interface has no vidioc_g_std.*/ -+ tv_fmt.type = V4L2_BUF_TYPE_PRIVATE; -+ vidioc_int_g_fmt_cap(cam->sensor, &tv_fmt); -+ -+ /* If the TV-in automatically detects the standard, then if it -+ * changes, the settings need to change. */ -+ if (cam->standard_autodetect) { -+ if (cam->standard.id != tv_fmt.fmt.pix.pixelformat) { -+ pr_debug("MVC: mxc_v4l2_g_std: " -+ "Changing standard\n"); -+ mxc_v4l2_s_std(cam, tv_fmt.fmt.pix.pixelformat); -+ } -+ } -+ -+ *e = tv_fmt.fmt.pix.pixelformat; -+ } -+ -+ return 0; -+} -+ -+/*! -+ * Dequeue one V4L capture buffer -+ * -+ * @param cam structure cam_data * -+ * @param buf structure v4l2_buffer * -+ * -+ * @return status 0 success, EINVAL invalid frame number, -+ * ETIME timeout, ERESTARTSYS interrupted by user -+ */ -+static int mxc_v4l_dqueue(cam_data *cam, struct v4l2_buffer *buf) -+{ -+ int retval = 0; -+ struct mxc_v4l_frame *frame; -+ unsigned long lock_flags; -+ -+ pr_debug("%s\n", __func__); -+ -+ if (!wait_event_interruptible_timeout(cam->enc_queue, -+ cam->enc_counter != 0, -+ 50 * HZ)) { -+ pr_err("ERROR: v4l2 capture: mxc_v4l_dqueue timeout " -+ "enc_counter %x\n", -+ cam->enc_counter); -+ return -ETIME; -+ } else if (signal_pending(current)) { -+ pr_err("ERROR: v4l2 capture: mxc_v4l_dqueue() " -+ "interrupt received\n"); -+ return -ERESTARTSYS; -+ } -+ -+ if (down_interruptible(&cam->busy_lock)) -+ return -EBUSY; -+ -+ spin_lock_irqsave(&cam->dqueue_int_lock, lock_flags); -+ cam->enc_counter--; -+ -+ frame = list_entry(cam->done_q.next, struct mxc_v4l_frame, queue); -+ list_del(cam->done_q.next); -+ if (frame->buffer.flags & V4L2_BUF_FLAG_DONE) { -+ frame->buffer.flags &= ~V4L2_BUF_FLAG_DONE; -+ } else if (frame->buffer.flags & V4L2_BUF_FLAG_QUEUED) { -+ pr_err("ERROR: v4l2 capture: VIDIOC_DQBUF: " -+ "Buffer not filled.\n"); -+ frame->buffer.flags &= ~V4L2_BUF_FLAG_QUEUED; -+ retval = -EINVAL; -+ } else if ((frame->buffer.flags & 0x7) == V4L2_BUF_FLAG_MAPPED) { -+ pr_err("ERROR: v4l2 capture: VIDIOC_DQBUF: " -+ "Buffer not queued.\n"); -+ retval = -EINVAL; -+ } -+ -+ cam->frame[frame->index].buffer.field = cam->device_type ? -+ V4L2_FIELD_INTERLACED : V4L2_FIELD_NONE; -+ -+ buf->bytesused = cam->v2f.fmt.pix.sizeimage; -+ buf->index = frame->index; -+ buf->flags = frame->buffer.flags; -+ buf->m = cam->frame[frame->index].buffer.m; -+ buf->timestamp = cam->frame[frame->index].buffer.timestamp; -+ buf->field = cam->frame[frame->index].buffer.field; -+ spin_unlock_irqrestore(&cam->dqueue_int_lock, lock_flags); -+ -+ up(&cam->busy_lock); -+ return retval; -+} -+ -+static void power_down_callback(struct work_struct *work) -+{ -+ cam_data *cam = container_of(work, struct _cam_data, power_down_work.work); -+ -+ down(&cam->busy_lock); -+ if (!cam->open_count) { -+ pr_info("%s: ipu%d/csi%d\n", __func__, cam->ipu_id, cam->csi); -+ vidioc_int_s_power(cam->sensor, 0); -+ cam->power_on = 0; -+ } -+ up(&cam->busy_lock); -+} -+ -+/* cam->busy_lock is held */ -+void power_up_camera(cam_data *cam) -+{ -+ if (cam->power_on) { -+ cancel_delayed_work(&cam->power_down_work); -+ return; -+ } -+ vidioc_int_s_power(cam->sensor, 1); -+ vidioc_int_init(cam->sensor); -+ vidioc_int_dev_init(cam->sensor); -+ cam->power_on = 1; -+} -+ -+ -+void power_off_camera(cam_data *cam) -+{ -+ schedule_delayed_work(&cam->power_down_work, (HZ * 2)); -+} -+ -+unsigned long csi_in_use; -+ -+/*! -+ * V4L interface - open function -+ * -+ * @param file structure file * -+ * -+ * @return status 0 success, ENODEV invalid device instance, -+ * ENODEV timeout, ERESTARTSYS interrupted by user -+ */ -+static int mxc_v4l_open(struct file *file) -+{ -+ struct video_device *dev = video_devdata(file); -+ cam_data *cam = video_get_drvdata(dev); -+ int err = 0; -+ struct sensor_data *sensor; -+ int csi_bit; -+ -+ if (!cam) { -+ pr_err("%s: %s cam_data not found!\n", __func__, dev->name); -+ return -EBADF; -+ } -+ if (!cam->sensor) { -+ pr_err("%s: %s no sensor ipu%d/csi%d\n", -+ __func__, dev->name, cam->ipu_id, cam->csi); -+ return -EAGAIN; -+ } -+ if (cam->sensor->type != v4l2_int_type_slave) { -+ pr_err("%s: %s wrong type ipu%d/csi%d, type=%d/%d\n", -+ __func__, dev->name, cam->ipu_id, cam->csi, -+ cam->sensor->type, v4l2_int_type_slave); -+ return -EAGAIN; -+ } -+ -+ sensor = cam->sensor->priv; -+ if (!sensor) { -+ pr_err("%s: Internal error, sensor_data is not found!\n", -+ __func__); -+ return -EBADF; -+ } -+ pr_debug("%s: %s ipu%d/csi%d\n", __func__, dev->name, -+ cam->ipu_id, cam->csi); -+ -+ down(&cam->busy_lock); -+ -+ err = 0; -+ if (signal_pending(current)) -+ goto oops; -+ -+ if (cam->open_count++ == 0) { -+ struct regmap *gpr; -+ -+ csi_bit = (cam->ipu_id << 1) | cam->csi; -+ if (test_and_set_bit(csi_bit, &csi_in_use)) { -+ pr_err("%s: %s CSI already in use\n", __func__, dev->name); -+ err = -EBUSY; -+ cam->open_count = 0; -+ goto oops; -+ } -+ cam->csi_in_use = 1; -+ -+ gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); -+ if (!IS_ERR(gpr)) { -+ if (of_machine_is_compatible("fsl,imx6q")) { -+ if (cam->ipu_id == cam->csi) { -+ unsigned shift = 19 + cam->csi; -+ unsigned mask = 1 << shift; -+ unsigned val = (cam->mipi_camera ? 0 : 1) << shift; -+ -+ regmap_update_bits(gpr, IOMUXC_GPR1, mask, val); -+ } -+ } else if (of_machine_is_compatible("fsl,imx6dl")) { -+ unsigned shift = cam->csi * 3; -+ unsigned mask = 7 << shift; -+ unsigned val = (cam->mipi_camera ? csi_bit : 4) << shift; -+ -+ regmap_update_bits(gpr, IOMUXC_GPR13, mask, val); -+ } -+ } else { -+ pr_err("%s: failed to find fsl,imx6q-iomux-gpr regmap\n", -+ __func__); -+ } -+ -+ wait_event_interruptible(cam->power_queue, -+ cam->low_power == false); -+ -+ if (strcmp(mxc_capture_inputs[cam->current_input].name, -+ "CSI MEM") == 0) { -+#if defined(CONFIG_MXC_IPU_CSI_ENC) || defined(CONFIG_MXC_IPU_CSI_ENC_MODULE) -+ err = csi_enc_select(cam); -+#endif -+ } else if (strcmp(mxc_capture_inputs[cam->current_input].name, -+ "CSI IC MEM") == 0) { -+#if defined(CONFIG_MXC_IPU_PRP_ENC) || defined(CONFIG_MXC_IPU_PRP_ENC_MODULE) -+ err = prp_enc_select(cam); -+#endif -+ } -+ -+ cam->enc_counter = 0; -+ INIT_LIST_HEAD(&cam->ready_q); -+ INIT_LIST_HEAD(&cam->working_q); -+ INIT_LIST_HEAD(&cam->done_q); -+ setup_ifparm(cam, 1); -+ if (!IS_ERR(sensor->sensor_clk)) -+ clk_prepare_enable(sensor->sensor_clk); -+ power_up_camera(cam); -+ } -+ -+ file->private_data = dev; -+ -+oops: -+ up(&cam->busy_lock); -+ return err; -+} -+ -+/*! -+ * V4L interface - close function -+ * -+ * @param file struct file * -+ * -+ * @return 0 success -+ */ -+static int mxc_v4l_close(struct file *file) -+{ -+ struct video_device *dev = video_devdata(file); -+ int err = 0; -+ cam_data *cam = video_get_drvdata(dev); -+ struct sensor_data *sensor; -+ pr_debug("%s\n", __func__); -+ -+ if (!cam) { -+ pr_err("%s: cam_data not found!\n", __func__); -+ return -EBADF; -+ } -+ -+ if (!cam->sensor) { -+ pr_err("%s: Internal error, camera is not found!\n", -+ __func__); -+ return -EBADF; -+ } -+ -+ sensor = cam->sensor->priv; -+ if (!sensor) { -+ pr_err("%s: Internal error, sensor_data is not found!\n", -+ __func__); -+ return -EBADF; -+ } -+ -+ down(&cam->busy_lock); -+ -+ /* for the case somebody hit the ctrl C */ -+ if (cam->overlay_pid == current->pid && cam->overlay_on) { -+ err = stop_preview(cam); -+ cam->overlay_on = false; -+ } -+ -+ if (--cam->open_count == 0) { -+ if (cam->capture_pid == current->pid) { -+ err |= mxc_streamoff(cam); -+ wake_up_interruptible(&cam->enc_queue); -+ } -+ if (!IS_ERR(sensor->sensor_clk)) -+ clk_disable_unprepare(sensor->sensor_clk); -+ wait_event_interruptible(cam->power_queue, -+ cam->low_power == false); -+ pr_debug("mxc_v4l_close: release resource\n"); -+ -+ if (strcmp(mxc_capture_inputs[cam->current_input].name, -+ "CSI MEM") == 0) { -+#if defined(CONFIG_MXC_IPU_CSI_ENC) || defined(CONFIG_MXC_IPU_CSI_ENC_MODULE) -+ err |= csi_enc_deselect(cam); -+#endif -+ } else if (strcmp(mxc_capture_inputs[cam->current_input].name, -+ "CSI IC MEM") == 0) { -+#if defined(CONFIG_MXC_IPU_PRP_ENC) || defined(CONFIG_MXC_IPU_PRP_ENC_MODULE) -+ err |= prp_enc_deselect(cam); -+#endif -+ } -+ -+ mxc_free_frame_buf(cam); -+ file->private_data = NULL; -+ -+ /* capture off */ -+ wake_up_interruptible(&cam->enc_queue); -+ mxc_free_frames(cam); -+ cam->enc_counter++; -+ power_off_camera(cam); -+ -+ if (cam->csi_in_use) { -+ int csi_bit = (cam->ipu_id << 1) | cam->csi; -+ -+ clear_bit(csi_bit, &csi_in_use); -+ cam->csi_in_use = 0; -+ } -+ } -+ -+ up(&cam->busy_lock); -+ -+ return err; -+} -+ -+#if defined(CONFIG_MXC_IPU_PRP_ENC) || defined(CONFIG_MXC_IPU_CSI_ENC) || \ -+ defined(CONFIG_MXC_IPU_PRP_ENC_MODULE) || \ -+ defined(CONFIG_MXC_IPU_CSI_ENC_MODULE) -+/* -+ * V4L interface - read function -+ * -+ * @param file struct file * -+ * @param read buf char * -+ * @param count size_t -+ * @param ppos structure loff_t * -+ * -+ * @return bytes read -+ */ -+static ssize_t mxc_v4l_read(struct file *file, char *buf, size_t count, -+ loff_t *ppos) -+{ -+ int err = 0; -+ u8 *v_address[2]; -+ struct video_device *dev = video_devdata(file); -+ cam_data *cam = video_get_drvdata(dev); -+ -+ if (down_interruptible(&cam->busy_lock)) -+ return -EINTR; -+ -+ /* Stop the viewfinder */ -+ if (cam->overlay_on == true) -+ stop_preview(cam); -+ -+ v_address[0] = dma_alloc_coherent(0, -+ PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage), -+ &cam->still_buf[0], -+ GFP_DMA | GFP_KERNEL); -+ -+ v_address[1] = dma_alloc_coherent(0, -+ PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage), -+ &cam->still_buf[1], -+ GFP_DMA | GFP_KERNEL); -+ -+ if (!v_address[0] || !v_address[1]) { -+ err = -ENOBUFS; -+ goto exit0; -+ } -+ -+ err = prp_still_select(cam); -+ if (err != 0) { -+ err = -EIO; -+ goto exit0; -+ } -+ -+ cam->still_counter = 0; -+ err = cam->csi_start(cam); -+ if (err != 0) { -+ err = -EIO; -+ goto exit1; -+ } -+ -+ if (!wait_event_interruptible_timeout(cam->still_queue, -+ cam->still_counter != 0, -+ 10 * HZ)) { -+ pr_err("ERROR: v4l2 capture: mxc_v4l_read timeout counter %x\n", -+ cam->still_counter); -+ err = -ETIME; -+ goto exit1; -+ } -+ err = copy_to_user(buf, v_address[1], cam->v2f.fmt.pix.sizeimage); -+ -+exit1: -+ prp_still_deselect(cam); -+ -+exit0: -+ if (v_address[0] != 0) -+ dma_free_coherent(0, cam->v2f.fmt.pix.sizeimage, v_address[0], -+ cam->still_buf[0]); -+ if (v_address[1] != 0) -+ dma_free_coherent(0, cam->v2f.fmt.pix.sizeimage, v_address[1], -+ cam->still_buf[1]); -+ -+ cam->still_buf[0] = cam->still_buf[1] = 0; -+ -+ if (cam->overlay_on == true) -+ start_preview(cam); -+ -+ up(&cam->busy_lock); -+ if (err < 0) -+ return err; -+ -+ return cam->v2f.fmt.pix.sizeimage - err; -+} -+#endif -+ -+/*! -+ * V4L interface - ioctl function -+ * -+ * @param file struct file* -+ * -+ * @param ioctlnr unsigned int -+ * -+ * @param arg void* -+ * -+ * @return 0 success, ENODEV for invalid device instance, -+ * -1 for other errors. -+ */ -+static long mxc_v4l_do_ioctl(struct file *file, -+ unsigned int ioctlnr, void *arg) -+{ -+ struct video_device *dev = video_devdata(file); -+ cam_data *cam = video_get_drvdata(dev); -+ int retval = 0; -+ unsigned long lock_flags; -+ -+ pr_debug("%s: %x ipu%d/csi%d\n", __func__, ioctlnr, cam->ipu_id, cam->csi); -+ wait_event_interruptible(cam->power_queue, cam->low_power == false); -+ /* make this _really_ smp-safe */ -+ if (ioctlnr != VIDIOC_DQBUF) -+ if (down_interruptible(&cam->busy_lock)) -+ return -EBUSY; -+ -+ switch (ioctlnr) { -+ /*! -+ * V4l2 VIDIOC_QUERYCAP ioctl -+ */ -+ case VIDIOC_QUERYCAP: { -+ struct v4l2_capability *cap = arg; -+ pr_debug(" case VIDIOC_QUERYCAP\n"); -+ strcpy(cap->driver, "mxc_v4l2"); -+ cap->version = KERNEL_VERSION(0, 1, 11); -+ cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | -+ V4L2_CAP_VIDEO_OVERLAY | -+ V4L2_CAP_STREAMING | -+ V4L2_CAP_READWRITE; -+ cap->card[0] = '\0'; -+ cap->bus_info[0] = '\0'; -+ break; -+ } -+ -+ /*! -+ * V4l2 VIDIOC_G_FMT ioctl -+ */ -+ case VIDIOC_G_FMT: { -+ struct v4l2_format *gf = arg; -+ pr_debug(" case VIDIOC_G_FMT\n"); -+ retval = mxc_v4l2_g_fmt(cam, gf); -+ break; -+ } -+ -+ /*! -+ * V4l2 VIDIOC_S_FMT ioctl -+ */ -+ /* XXX: workaround for gstreamer */ -+ case VIDIOC_TRY_FMT: { -+ struct v4l2_format *sf = arg; -+ pr_debug(" case VIDIOC_TRY_FMT\n"); -+ retval = mxc_v4l2_s_fmt(cam, sf, true); -+ break; -+ } -+ case VIDIOC_S_FMT: { -+ struct v4l2_format *sf = arg; -+ pr_debug(" case VIDIOC_S_FMT\n"); -+ retval = mxc_v4l2_s_fmt(cam, sf, false); -+ break; -+ } -+ -+ /*! -+ * V4l2 VIDIOC_REQBUFS ioctl -+ */ -+ case VIDIOC_REQBUFS: { -+ struct v4l2_requestbuffers *req = arg; -+ pr_debug(" case VIDIOC_REQBUFS\n"); -+ -+ if (req->count > FRAME_NUM) { -+ pr_err("ERROR: v4l2 capture: VIDIOC_REQBUFS: " -+ "not enough buffers\n"); -+ req->count = FRAME_NUM; -+ } -+ -+ if ((req->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) { -+ pr_err("ERROR: v4l2 capture: VIDIOC_REQBUFS: " -+ "wrong buffer type\n"); -+ retval = -EINVAL; -+ break; -+ } -+ -+ mxc_streamoff(cam); -+ if (req->memory & V4L2_MEMORY_MMAP) { -+ mxc_free_frame_buf(cam); -+ retval = mxc_allocate_frame_buf(cam, req->count); -+ } -+ break; -+ } -+ -+ /*! -+ * V4l2 VIDIOC_QUERYBUF ioctl -+ */ -+ case VIDIOC_QUERYBUF: { -+ struct v4l2_buffer *buf = arg; -+ int index = buf->index; -+ pr_debug(" case VIDIOC_QUERYBUF\n"); -+ -+ if (buf->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { -+ pr_err("ERROR: v4l2 capture: " -+ "VIDIOC_QUERYBUFS: " -+ "wrong buffer type\n"); -+ retval = -EINVAL; -+ break; -+ } -+ -+ if (buf->memory & V4L2_MEMORY_MMAP) { -+ memset(buf, 0, sizeof(buf)); -+ buf->index = index; -+ } -+ -+ down(&cam->param_lock); -+ if (buf->memory & V4L2_MEMORY_USERPTR) { -+ mxc_v4l2_release_bufs(cam); -+ retval = mxc_v4l2_prepare_bufs(cam, buf); -+ } -+ -+ if (buf->memory & V4L2_MEMORY_MMAP) -+ retval = mxc_v4l2_buffer_status(cam, buf); -+ up(&cam->param_lock); -+ break; -+ } -+ -+ /*! -+ * V4l2 VIDIOC_QBUF ioctl -+ */ -+ case VIDIOC_QBUF: { -+ struct v4l2_buffer *buf = arg; -+ int index = buf->index; -+ pr_debug(" case VIDIOC_QBUF\n"); -+ -+ spin_lock_irqsave(&cam->queue_int_lock, lock_flags); -+ if ((cam->frame[index].buffer.flags & 0x7) == -+ V4L2_BUF_FLAG_MAPPED) { -+ cam->frame[index].buffer.flags |= -+ V4L2_BUF_FLAG_QUEUED; -+ list_add_tail(&cam->frame[index].queue, -+ &cam->ready_q); -+ } else if (cam->frame[index].buffer. -+ flags & V4L2_BUF_FLAG_QUEUED) { -+ pr_err("ERROR: v4l2 capture: VIDIOC_QBUF: " -+ "buffer already queued\n"); -+ retval = -EINVAL; -+ } else if (cam->frame[index].buffer. -+ flags & V4L2_BUF_FLAG_DONE) { -+ pr_err("ERROR: v4l2 capture: VIDIOC_QBUF: " -+ "overwrite done buffer.\n"); -+ cam->frame[index].buffer.flags &= -+ ~V4L2_BUF_FLAG_DONE; -+ cam->frame[index].buffer.flags |= -+ V4L2_BUF_FLAG_QUEUED; -+ retval = -EINVAL; -+ } -+ -+ buf->flags = cam->frame[index].buffer.flags; -+ spin_unlock_irqrestore(&cam->queue_int_lock, lock_flags); -+ break; -+ } -+ -+ /*! -+ * V4l2 VIDIOC_DQBUF ioctl -+ */ -+ case VIDIOC_DQBUF: { -+ struct v4l2_buffer *buf = arg; -+ pr_debug(" case VIDIOC_DQBUF\n"); -+ -+ if ((cam->enc_counter == 0) && -+ (file->f_flags & O_NONBLOCK)) { -+ retval = -EAGAIN; -+ break; -+ } -+ -+ retval = mxc_v4l_dqueue(cam, buf); -+ break; -+ } -+ -+ /*! -+ * V4l2 VIDIOC_STREAMON ioctl -+ */ -+ case VIDIOC_STREAMON: { -+ pr_debug(" case VIDIOC_STREAMON\n"); -+ retval = mxc_streamon(cam); -+ break; -+ } -+ -+ /*! -+ * V4l2 VIDIOC_STREAMOFF ioctl -+ */ -+ case VIDIOC_STREAMOFF: { -+ pr_debug(" case VIDIOC_STREAMOFF\n"); -+ retval = mxc_streamoff(cam); -+ break; -+ } -+ -+ /*! -+ * V4l2 VIDIOC_G_CTRL ioctl -+ */ -+ case VIDIOC_G_CTRL: { -+ pr_debug(" case VIDIOC_G_CTRL\n"); -+ retval = mxc_v4l2_g_ctrl(cam, arg); -+ break; -+ } -+ -+ /*! -+ * V4l2 VIDIOC_S_CTRL ioctl -+ */ -+ case VIDIOC_S_CTRL: { -+ pr_debug(" case VIDIOC_S_CTRL\n"); -+ retval = mxc_v4l2_s_ctrl(cam, arg); -+ break; -+ } -+ -+ /*! -+ * V4l2 VIDIOC_CROPCAP ioctl -+ */ -+ case VIDIOC_CROPCAP: { -+ struct v4l2_cropcap *cap = arg; -+ pr_debug(" case VIDIOC_CROPCAP\n"); -+ if (cap->type != V4L2_BUF_TYPE_VIDEO_CAPTURE && -+ cap->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) { -+ retval = -EINVAL; -+ break; -+ } -+ cap->bounds = cam->crop_bounds; -+ cap->defrect = cam->crop_defrect; -+ break; -+ } -+ -+ /*! -+ * V4l2 VIDIOC_G_CROP ioctl -+ */ -+ case VIDIOC_G_CROP: { -+ struct v4l2_crop *crop = arg; -+ pr_debug(" case VIDIOC_G_CROP\n"); -+ -+ if (crop->type != V4L2_BUF_TYPE_VIDEO_CAPTURE && -+ crop->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) { -+ retval = -EINVAL; -+ break; -+ } -+ crop->c = cam->crop_current; -+ break; -+ } -+ -+ /*! -+ * V4l2 VIDIOC_S_CROP ioctl -+ */ -+ case VIDIOC_S_CROP: { -+ struct v4l2_crop *crop = arg; -+ struct v4l2_rect *b = &cam->crop_bounds; -+ pr_debug(" case VIDIOC_S_CROP\n"); -+ -+ if (crop->type != V4L2_BUF_TYPE_VIDEO_CAPTURE && -+ crop->type != V4L2_BUF_TYPE_VIDEO_OVERLAY) { -+ retval = -EINVAL; -+ break; -+ } -+ -+ crop->c.top = (crop->c.top < b->top) ? b->top -+ : crop->c.top; -+ if (crop->c.top > b->top + b->height) -+ crop->c.top = b->top + b->height - 1; -+ if (crop->c.height > b->top + b->height - crop->c.top) -+ crop->c.height = -+ b->top + b->height - crop->c.top; -+ -+ crop->c.left = (crop->c.left < b->left) ? b->left -+ : crop->c.left; -+ if (crop->c.left > b->left + b->width) -+ crop->c.left = b->left + b->width - 1; -+ if (crop->c.width > b->left - crop->c.left + b->width) -+ crop->c.width = -+ b->left - crop->c.left + b->width; -+ -+ crop->c.width -= crop->c.width % 8; -+ crop->c.left -= crop->c.left % 4; -+ cam->crop_current = crop->c; -+ -+ pr_debug(" Cropping Input to ipu size %d x %d\n", -+ cam->crop_current.width, -+ cam->crop_current.height); -+ ipu_csi_set_window_size(cam->ipu, cam->crop_current.width, -+ cam->crop_current.height, -+ cam->csi); -+ ipu_csi_set_window_pos(cam->ipu, cam->crop_current.left, -+ cam->crop_current.top, -+ cam->csi); -+ break; -+ } -+ -+ /*! -+ * V4l2 VIDIOC_OVERLAY ioctl -+ */ -+ case VIDIOC_OVERLAY: { -+ int *on = arg; -+ pr_debug(" VIDIOC_OVERLAY on=%d\n", *on); -+ if (*on) { -+ cam->overlay_on = true; -+ cam->overlay_pid = current->pid; -+ retval = start_preview(cam); -+ } -+ if (!*on) { -+ retval = stop_preview(cam); -+ cam->overlay_on = false; -+ } -+ break; -+ } -+ -+ /*! -+ * V4l2 VIDIOC_G_FBUF ioctl -+ */ -+ case VIDIOC_G_FBUF: { -+ struct v4l2_framebuffer *fb = arg; -+ pr_debug(" case VIDIOC_G_FBUF\n"); -+ *fb = cam->v4l2_fb; -+ fb->capability = V4L2_FBUF_CAP_EXTERNOVERLAY; -+ break; -+ } -+ -+ /*! -+ * V4l2 VIDIOC_S_FBUF ioctl -+ */ -+ case VIDIOC_S_FBUF: { -+ struct v4l2_framebuffer *fb = arg; -+ pr_debug(" case VIDIOC_S_FBUF\n"); -+ cam->v4l2_fb = *fb; -+ break; -+ } -+ -+ case VIDIOC_G_PARM: { -+ struct v4l2_streamparm *parm = arg; -+ pr_debug(" case VIDIOC_G_PARM\n"); -+ if (cam->sensor) -+ retval = vidioc_int_g_parm(cam->sensor, parm); -+ else { -+ pr_err("ERROR: v4l2 capture: slave not found!\n"); -+ retval = -ENODEV; -+ } -+ break; -+ } -+ -+ case VIDIOC_S_PARM: { -+ struct v4l2_streamparm *parm = arg; -+ pr_debug(" case VIDIOC_S_PARM\n"); -+ if (cam->sensor) -+ retval = mxc_v4l2_s_param(cam, parm); -+ else { -+ pr_err("ERROR: v4l2 capture: slave not found!\n"); -+ retval = -ENODEV; -+ } -+ break; -+ } -+ -+ /* linux v4l2 bug, kernel c0485619 user c0405619 */ -+ case VIDIOC_ENUMSTD: { -+ struct v4l2_standard *e = arg; -+ pr_debug(" case VIDIOC_ENUMSTD\n"); -+ if (e->index > 0) { -+ retval = -EINVAL; -+ break; -+ } -+ *e = cam->standard; -+ break; -+ } -+ -+ case VIDIOC_G_STD: { -+ v4l2_std_id *e = arg; -+ pr_debug(" case VIDIOC_G_STD\n"); -+ if (cam->sensor) -+ retval = mxc_v4l2_g_std(cam, e); -+ else { -+ pr_err("ERROR: v4l2 capture: slave not found!\n"); -+ retval = -ENODEV; -+ } -+ break; -+ } -+ -+ case VIDIOC_S_STD: { -+ v4l2_std_id *e = arg; -+ pr_debug(" case VIDIOC_S_STD\n"); -+ retval = mxc_v4l2_s_std(cam, *e); -+ -+ break; -+ } -+ -+ case VIDIOC_ENUMOUTPUT: { -+ struct v4l2_output *output = arg; -+ pr_debug(" case VIDIOC_ENUMOUTPUT\n"); -+ if (output->index >= MXC_V4L2_CAPTURE_NUM_OUTPUTS) { -+ retval = -EINVAL; -+ break; -+ } -+ *output = mxc_capture_outputs[output->index]; -+ -+ break; -+ } -+ case VIDIOC_G_OUTPUT: { -+ int *p_output_num = arg; -+ pr_debug(" case VIDIOC_G_OUTPUT\n"); -+ *p_output_num = cam->output; -+ break; -+ } -+ -+ case VIDIOC_S_OUTPUT: { -+ int *p_output_num = arg; -+ pr_debug(" case VIDIOC_S_OUTPUT\n"); -+ if (*p_output_num >= MXC_V4L2_CAPTURE_NUM_OUTPUTS) { -+ retval = -EINVAL; -+ break; -+ } -+ cam->output = *p_output_num; -+ break; -+ } -+ -+ case VIDIOC_ENUMINPUT: { -+ struct v4l2_input *input = arg; -+ pr_debug(" case VIDIOC_ENUMINPUT\n"); -+ if (input->index >= MXC_V4L2_CAPTURE_NUM_INPUTS) { -+ retval = -EINVAL; -+ break; -+ } -+ *input = mxc_capture_inputs[input->index]; -+ break; -+ } -+ -+ case VIDIOC_G_INPUT: { -+ int *index = arg; -+ pr_debug(" case VIDIOC_G_INPUT\n"); -+ *index = cam->current_input; -+ break; -+ } -+ -+ case VIDIOC_S_INPUT: { -+ int *index = arg; -+ pr_debug(" case VIDIOC_S_INPUT\n"); -+ if (*index >= MXC_V4L2_CAPTURE_NUM_INPUTS) { -+ retval = -EINVAL; -+ break; -+ } -+ -+ if (*index == cam->current_input) -+ break; -+ -+ if ((mxc_capture_inputs[cam->current_input].status & -+ V4L2_IN_ST_NO_POWER) == 0) { -+ retval = mxc_streamoff(cam); -+ if (retval) -+ break; -+ mxc_capture_inputs[cam->current_input].status |= -+ V4L2_IN_ST_NO_POWER; -+ } -+ -+ if (strcmp(mxc_capture_inputs[*index].name, "CSI MEM") == 0) { -+#if defined(CONFIG_MXC_IPU_CSI_ENC) || defined(CONFIG_MXC_IPU_CSI_ENC_MODULE) -+ retval = csi_enc_select(cam); -+ if (retval) -+ break; -+#endif -+ } else if (strcmp(mxc_capture_inputs[*index].name, -+ "CSI IC MEM") == 0) { -+#if defined(CONFIG_MXC_IPU_PRP_ENC) || defined(CONFIG_MXC_IPU_PRP_ENC_MODULE) -+ retval = prp_enc_select(cam); -+ if (retval) -+ break; -+#endif -+ } -+ -+ mxc_capture_inputs[*index].status &= ~V4L2_IN_ST_NO_POWER; -+ cam->current_input = *index; -+ break; -+ } -+ case VIDIOC_ENUM_FMT: { -+ struct v4l2_fmtdesc *f = arg; -+ if (cam->sensor) -+ retval = vidioc_int_enum_fmt_cap(cam->sensor, f); -+ else { -+ pr_err("ERROR: v4l2 capture: slave not found!\n"); -+ retval = -ENODEV; -+ } -+ break; -+ } -+ case VIDIOC_ENUM_FRAMESIZES: { -+ struct v4l2_frmsizeenum *fsize = arg; -+ if (cam->sensor) -+ retval = vidioc_int_enum_framesizes(cam->sensor, fsize); -+ else { -+ pr_err("ERROR: v4l2 capture: slave not found!\n"); -+ retval = -ENODEV; -+ } -+ break; -+ } -+ case VIDIOC_ENUM_FRAMEINTERVALS: { -+ struct v4l2_frmivalenum *fival = arg; -+ if (cam->sensor) { -+ retval = vidioc_int_enum_frameintervals(cam->sensor, -+ fival); -+ } else { -+ pr_err("ERROR: v4l2 capture: slave not found!\n"); -+ retval = -ENODEV; -+ } -+ break; -+ } -+ case VIDIOC_DBG_G_CHIP_IDENT: { -+ struct v4l2_dbg_chip_ident *p = arg; -+ p->ident = V4L2_IDENT_NONE; -+ p->revision = 0; -+ if (cam->sensor) -+ retval = vidioc_int_g_chip_ident(cam->sensor, (int *)p); -+ else { -+ pr_err("ERROR: v4l2 capture: slave not found!\n"); -+ retval = -ENODEV; -+ } -+ break; -+ } -+ -+ case VIDIOC_SEND_COMMAND: { -+ retval = mxc_v4l2_send_command(cam, arg); -+ break; -+ } -+ -+ /* XXX: workaround for gstreamer */ -+/* case VIDIOC_TRY_FMT: */ -+ case VIDIOC_QUERYCTRL: -+ case VIDIOC_G_TUNER: -+ case VIDIOC_S_TUNER: -+ case VIDIOC_G_FREQUENCY: -+ case VIDIOC_S_FREQUENCY: -+ default: -+ pr_debug(" case default or not supported\n"); -+ retval = -EINVAL; -+ break; -+ } -+ -+ if (ioctlnr != VIDIOC_DQBUF) -+ up(&cam->busy_lock); -+ return retval; -+} -+ -+/* -+ * V4L interface - ioctl function -+ * -+ * @return None -+ */ -+static long mxc_v4l_ioctl(struct file *file, unsigned int cmd, -+ unsigned long arg) -+{ -+ pr_debug("%s\n", __func__); -+ return video_usercopy(file, cmd, arg, mxc_v4l_do_ioctl); -+} -+ -+/*! -+ * V4L interface - mmap function -+ * -+ * @param file structure file * -+ * -+ * @param vma structure vm_area_struct * -+ * -+ * @return status 0 Success, EINTR busy lock error, ENOBUFS remap_page error -+ */ -+static int mxc_mmap(struct file *file, struct vm_area_struct *vma) -+{ -+ struct video_device *dev = video_devdata(file); -+ unsigned long size; -+ int res = 0; -+ cam_data *cam = video_get_drvdata(dev); -+ -+ pr_debug("%s:pgoff=0x%lx, start=0x%lx, end=0x%lx\n", __func__, -+ vma->vm_pgoff, vma->vm_start, vma->vm_end); -+ -+ /* make this _really_ smp-safe */ -+ if (down_interruptible(&cam->busy_lock)) -+ return -EINTR; -+ -+ size = vma->vm_end - vma->vm_start; -+ vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); -+ -+ if (remap_pfn_range(vma, vma->vm_start, -+ vma->vm_pgoff, size, vma->vm_page_prot)) { -+ pr_err("ERROR: v4l2 capture: mxc_mmap: " -+ "remap_pfn_range failed\n"); -+ res = -ENOBUFS; -+ goto mxc_mmap_exit; -+ } -+ -+ vma->vm_flags &= ~VM_IO; /* using shared anonymous pages */ -+ -+mxc_mmap_exit: -+ up(&cam->busy_lock); -+ return res; -+} -+ -+/*! -+ * V4L interface - poll function -+ * -+ * @param file structure file * -+ * -+ * @param wait structure poll_table_struct * -+ * -+ * @return status POLLIN | POLLRDNORM -+ */ -+static unsigned int mxc_poll(struct file *file, struct poll_table_struct *wait) -+{ -+ struct video_device *dev = video_devdata(file); -+ cam_data *cam = video_get_drvdata(dev); -+ wait_queue_head_t *queue = NULL; -+ int res = POLLIN | POLLRDNORM; -+ -+ pr_debug("%s\n", __func__); -+ -+ if (down_interruptible(&cam->busy_lock)) -+ return -EINTR; -+ -+ queue = &cam->enc_queue; -+ poll_wait(file, queue, wait); -+ -+ up(&cam->busy_lock); -+ -+ return res; -+} -+ -+/*! -+ * This structure defines the functions to be called in this driver. -+ */ -+static struct v4l2_file_operations mxc_v4l_fops = { -+ .owner = THIS_MODULE, -+ .open = mxc_v4l_open, -+ .release = mxc_v4l_close, -+ .read = mxc_v4l_read, -+ .unlocked_ioctl = mxc_v4l_ioctl, -+ .mmap = mxc_mmap, -+ .poll = mxc_poll, -+}; -+ -+static struct video_device mxc_v4l_template = { -+ .name = "Mxc Camera", -+ .fops = &mxc_v4l_fops, -+ .release = video_device_release, -+}; -+ -+/*! -+ * This function can be used to release any platform data on closing. -+ */ -+static void camera_platform_release(struct device *device) -+{ -+} -+ -+/*! -+ * Camera V4l2 callback function. -+ * -+ * @param mask u32 -+ * -+ * @param dev void device structure -+ * -+ * @return status -+ */ -+static void camera_callback(u32 mask, void *dev) -+{ -+ struct mxc_v4l_frame *done_frame; -+ struct mxc_v4l_frame *ready_frame; -+ struct timeval cur_time; -+ -+ cam_data *cam = (cam_data *) dev; -+ if (cam == NULL) -+ return; -+ -+ pr_debug("%s\n", __func__); -+ -+ spin_lock(&cam->queue_int_lock); -+ spin_lock(&cam->dqueue_int_lock); -+ if (!list_empty(&cam->working_q)) { -+ do_gettimeofday(&cur_time); -+ -+ done_frame = list_entry(cam->working_q.next, -+ struct mxc_v4l_frame, -+ queue); -+ -+ if (done_frame->ipu_buf_num != cam->local_buf_num) -+ goto next; -+ -+ /* -+ * Set the current time to done frame buffer's -+ * timestamp. Users can use this information to judge -+ * the frame's usage. -+ */ -+ done_frame->buffer.timestamp = cur_time; -+ -+ if (done_frame->buffer.flags & V4L2_BUF_FLAG_QUEUED) { -+ done_frame->buffer.flags |= V4L2_BUF_FLAG_DONE; -+ done_frame->buffer.flags &= ~V4L2_BUF_FLAG_QUEUED; -+ -+ /* Added to the done queue */ -+ list_del(cam->working_q.next); -+ list_add_tail(&done_frame->queue, &cam->done_q); -+ -+ /* Wake up the queue */ -+ cam->enc_counter++; -+ wake_up_interruptible(&cam->enc_queue); -+ } else -+ pr_err("ERROR: v4l2 capture: camera_callback: " -+ "buffer not queued\n"); -+ } -+ -+next: -+ if (!list_empty(&cam->ready_q)) { -+ ready_frame = list_entry(cam->ready_q.next, -+ struct mxc_v4l_frame, -+ queue); -+ if (cam->enc_update_eba) -+ if (cam->enc_update_eba(cam->ipu, -+ ready_frame->buffer.m.offset, -+ &cam->ping_pong_csi) == 0) { -+ list_del(cam->ready_q.next); -+ list_add_tail(&ready_frame->queue, -+ &cam->working_q); -+ ready_frame->ipu_buf_num = cam->local_buf_num; -+ } -+ } else { -+ if (cam->enc_update_eba) -+ cam->enc_update_eba( -+ cam->ipu, cam->dummy_frame.buffer.m.offset, -+ &cam->ping_pong_csi); -+ } -+ -+ cam->local_buf_num = (cam->local_buf_num == 0) ? 1 : 0; -+ spin_unlock(&cam->dqueue_int_lock); -+ spin_unlock(&cam->queue_int_lock); -+ -+ return; -+} -+ -+/*! -+ * initialize cam_data structure -+ * -+ * @param cam structure cam_data * -+ * -+ * @return status 0 Success -+ */ -+static int init_camera_struct(cam_data *cam, struct platform_device *pdev) -+{ -+ const struct of_device_id *of_id = -+ of_match_device(mxc_v4l2_dt_ids, &pdev->dev); -+ struct device_node *np = pdev->dev.of_node; -+ int ipu_id, csi_id, mclk_source, mipi_camera, def_input; -+ int ret = 0; -+ struct v4l2_device *v4l2_dev; -+ static int camera_id; -+ -+ pr_debug("%s\n", __func__); -+ -+ ret = of_property_read_u32(np, "ipu_id", &ipu_id); -+ if (ret) { -+ dev_err(&pdev->dev, "ipu_id missing or invalid\n"); -+ return ret; -+ } -+ -+ ret = of_property_read_u32(np, "csi_id", &csi_id); -+ if (ret) { -+ dev_err(&pdev->dev, "csi_id missing or invalid\n"); -+ return ret; -+ } -+ -+ ret = of_property_read_u32(np, "mclk_source", &mclk_source); -+ if (ret) { -+ dev_err(&pdev->dev, "sensor mclk missing or invalid\n"); -+ return ret; -+ } -+ -+ ret = of_property_read_u32(np, "mipi_camera", &mipi_camera); -+ if (ret) -+ mipi_camera = 0; -+ -+ ret = of_property_read_u32(np, "default_input", &def_input); -+ if (ret || (def_input != 0 && def_input != 1)) -+ def_input = 0; -+ -+ /* Default everything to 0 */ -+ memset(cam, 0, sizeof(cam_data)); -+ -+ /* get devtype to distinguish if the cpu is imx5 or imx6 -+ * IMX5_V4L2 specify the cpu is imx5 -+ * IMX6_V4L2 specify the cpu is imx6q or imx6sdl -+ */ -+ if (of_id) -+ pdev->id_entry = of_id->data; -+ cam->devtype = pdev->id_entry->driver_data; -+ -+ cam->ipu = ipu_get_soc(ipu_id); -+ if (cam->ipu == NULL) { -+ pr_err("ERROR: v4l2 capture: failed to get ipu\n"); -+ return -EINVAL; -+ } else if (cam->ipu == ERR_PTR(-ENODEV)) { -+ pr_err("ERROR: v4l2 capture: get invalid ipu\n"); -+ return -ENODEV; -+ } -+ -+ init_MUTEX(&cam->param_lock); -+ init_MUTEX(&cam->busy_lock); -+ INIT_DELAYED_WORK(&cam->power_down_work, power_down_callback); -+ -+ cam->video_dev = video_device_alloc(); -+ if (cam->video_dev == NULL) -+ return -ENODEV; -+ -+ *(cam->video_dev) = mxc_v4l_template; -+ -+ video_set_drvdata(cam->video_dev, cam); -+ dev_set_drvdata(&pdev->dev, (void *)cam); -+ cam->video_dev->minor = -1; -+ -+ v4l2_dev = kzalloc(sizeof(*v4l2_dev), GFP_KERNEL); -+ if (!v4l2_dev) { -+ dev_err(&pdev->dev, "failed to allocate v4l2_dev structure\n"); -+ video_device_release(cam->video_dev); -+ return -ENOMEM; -+ } -+ -+ if (v4l2_device_register(&pdev->dev, v4l2_dev) < 0) { -+ dev_err(&pdev->dev, "register v4l2 device failed\n"); -+ video_device_release(cam->video_dev); -+ kfree(v4l2_dev); -+ return -ENODEV; -+ } -+ cam->video_dev->v4l2_dev = v4l2_dev; -+ -+ init_waitqueue_head(&cam->enc_queue); -+ init_waitqueue_head(&cam->still_queue); -+ -+ /* setup cropping */ -+ cam->crop_bounds.left = 0; -+ cam->crop_bounds.width = 640; -+ cam->crop_bounds.top = 0; -+ cam->crop_bounds.height = 480; -+ cam->crop_current = cam->crop_defrect = cam->crop_bounds; -+ ipu_csi_set_window_size(cam->ipu, cam->crop_current.width, -+ cam->crop_current.height, cam->csi); -+ ipu_csi_set_window_pos(cam->ipu, cam->crop_current.left, -+ cam->crop_current.top, cam->csi); -+ cam->streamparm.parm.capture.capturemode = 0; -+ -+ cam->standard.index = 0; -+ cam->standard.id = V4L2_STD_UNKNOWN; -+ cam->standard.frameperiod.denominator = 30; -+ cam->standard.frameperiod.numerator = 1; -+ cam->standard.framelines = 480; -+ cam->standard_autodetect = true; -+ cam->streamparm.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; -+ cam->streamparm.parm.capture.timeperframe = cam->standard.frameperiod; -+ cam->streamparm.parm.capture.capability = V4L2_CAP_TIMEPERFRAME; -+ cam->overlay_on = false; -+ cam->capture_on = false; -+ cam->v4l2_fb.flags = V4L2_FBUF_FLAG_OVERLAY; -+ -+ cam->v2f.fmt.pix.sizeimage = 352 * 288 * 3 / 2; -+ cam->v2f.fmt.pix.bytesperline = 288 * 3 / 2; -+ cam->v2f.fmt.pix.width = 288; -+ cam->v2f.fmt.pix.height = 352; -+ cam->v2f.fmt.pix.pixelformat = V4L2_PIX_FMT_YUV420; -+ cam->win.w.width = 160; -+ cam->win.w.height = 160; -+ cam->win.w.left = 0; -+ cam->win.w.top = 0; -+ -+ cam->ipu_id = ipu_id; -+ cam->csi = csi_id; -+ cam->mipi_camera = mipi_camera; -+ cam->mclk_source = mclk_source; -+ cam->mclk_on[cam->mclk_source] = false; -+ cam->current_input = def_input; -+ -+ cam->enc_callback = camera_callback; -+ init_waitqueue_head(&cam->power_queue); -+ spin_lock_init(&cam->queue_int_lock); -+ spin_lock_init(&cam->dqueue_int_lock); -+ -+ cam->dummy_frame.vaddress = dma_alloc_coherent(0, -+ SZ_8M, &cam->dummy_frame.paddress, -+ GFP_DMA | GFP_KERNEL); -+ if (cam->dummy_frame.vaddress == 0) -+ pr_err("ERROR: v4l2 capture: Allocate dummy frame " -+ "failed.\n"); -+ cam->dummy_frame.buffer.length = SZ_8M; -+ -+ cam->self = kmalloc(sizeof(struct v4l2_int_device), GFP_KERNEL); -+ cam->self->module = THIS_MODULE; -+ sprintf(cam->self->name, "mxc_v4l2_cap%d", camera_id++); -+ cam->self->type = v4l2_int_type_master; -+ cam->self->u.master = &mxc_v4l2_master; -+ -+ return 0; -+} -+ -+static ssize_t show_streaming(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct video_device *video_dev = container_of(dev, -+ struct video_device, dev); -+ cam_data *cam = video_get_drvdata(video_dev); -+ -+ if (cam->capture_on) -+ return sprintf(buf, "stream on\n"); -+ else -+ return sprintf(buf, "stream off\n"); -+} -+static DEVICE_ATTR(fsl_v4l2_capture_property, S_IRUGO, show_streaming, NULL); -+ -+static ssize_t show_overlay(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct video_device *video_dev = container_of(dev, -+ struct video_device, dev); -+ cam_data *cam = video_get_drvdata(video_dev); -+ -+ if (cam->overlay_on) -+ return sprintf(buf, "overlay on\n"); -+ else -+ return sprintf(buf, "overlay off\n"); -+} -+static DEVICE_ATTR(fsl_v4l2_overlay_property, S_IRUGO, show_overlay, NULL); -+ -+static ssize_t show_csi(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct video_device *video_dev = container_of(dev, -+ struct video_device, dev); -+ cam_data *cam = video_get_drvdata(video_dev); -+ -+ return sprintf(buf, "ipu%d_csi%d\n", cam->ipu_id, cam->csi); -+} -+static DEVICE_ATTR(fsl_csi_property, S_IRUGO, show_csi, NULL); -+ -+/*! -+ * This function is called to probe the devices if registered. -+ * -+ * @param pdev the device structure used to give information on which device -+ * to probe -+ * -+ * @return The function returns 0 on success and -1 on failure. -+ */ -+static int mxc_v4l2_probe(struct platform_device *pdev) -+{ -+ int err; -+ -+ /* Create cam and initialize it. */ -+ cam_data *cam = kmalloc(sizeof(cam_data), GFP_KERNEL); -+ if (cam == NULL) { -+ pr_err("ERROR: v4l2 capture: failed to register camera\n"); -+ return -1; -+ } -+ -+ err = init_camera_struct(cam, pdev); -+ if (err) -+ return err; -+ pdev->dev.release = camera_platform_release; -+ -+ /* Set up the v4l2 device and register it*/ -+ cam->self->priv = cam; -+ v4l2_int_device_register(cam->self); -+ -+ /* register v4l video device */ -+ if (video_register_device(cam->video_dev, VFL_TYPE_GRABBER, video_nr) -+ < 0) { -+ kfree(cam); -+ cam = NULL; -+ pr_err("ERROR: v4l2 capture: video_register_device failed\n"); -+ return -1; -+ } -+ -+ pr_info("V4L2 device '%s' on IPU%d_CSI%d registered as %s\n", -+ cam->video_dev->name, -+ cam->ipu_id + 1, cam->csi, -+ video_device_node_name(cam->video_dev)); -+ -+ if (device_create_file(&cam->video_dev->dev, -+ &dev_attr_fsl_v4l2_capture_property)) -+ dev_err(&pdev->dev, "Error on creating sysfs file" -+ " for capture\n"); -+ -+ if (device_create_file(&cam->video_dev->dev, -+ &dev_attr_fsl_v4l2_overlay_property)) -+ dev_err(&pdev->dev, "Error on creating sysfs file" -+ " for overlay\n"); -+ -+ if (device_create_file(&cam->video_dev->dev, -+ &dev_attr_fsl_csi_property)) -+ dev_err(&pdev->dev, "Error on creating sysfs file" -+ " for csi number\n"); -+ -+ return 0; -+} -+ -+/*! -+ * This function is called to remove the devices when device unregistered. -+ * -+ * @param pdev the device structure used to give information on which device -+ * to remove -+ * -+ * @return The function returns 0 on success and -1 on failure. -+ */ -+static int mxc_v4l2_remove(struct platform_device *pdev) -+{ -+ cam_data *cam = (cam_data *)platform_get_drvdata(pdev); -+ -+ if (cam->open_count) { -+ pr_err("ERROR: v4l2 capture:camera open " -+ "-- setting ops to NULL\n"); -+ return -EBUSY; -+ } else { -+ struct v4l2_device *v4l2_dev = cam->video_dev->v4l2_dev; -+ device_remove_file(&cam->video_dev->dev, -+ &dev_attr_fsl_v4l2_capture_property); -+ device_remove_file(&cam->video_dev->dev, -+ &dev_attr_fsl_v4l2_overlay_property); -+ device_remove_file(&cam->video_dev->dev, -+ &dev_attr_fsl_csi_property); -+ -+ pr_info("V4L2 freeing image input device\n"); -+ v4l2_int_device_unregister(cam->self); -+ video_unregister_device(cam->video_dev); -+ -+ if (cam->dummy_frame.vaddress != 0) { -+ dma_free_coherent(0, cam->dummy_frame.buffer.length, -+ cam->dummy_frame.vaddress, -+ cam->dummy_frame.paddress); -+ cam->dummy_frame.vaddress = 0; -+ } -+ -+ mxc_free_frame_buf(cam); -+ kfree(cam); -+ -+ v4l2_device_unregister(v4l2_dev); -+ kfree(v4l2_dev); -+ } -+ -+ pr_info("V4L2 unregistering video\n"); -+ return 0; -+} -+ -+/*! -+ * This function is called to put the sensor in a low power state. -+ * Refer to the document driver-model/driver.txt in the kernel source tree -+ * for more information. -+ * -+ * @param pdev the device structure used to give information on which I2C -+ * to suspend -+ * @param state the power state the device is entering -+ * -+ * @return The function returns 0 on success and -1 on failure. -+ */ -+static int mxc_v4l2_suspend(struct platform_device *pdev, pm_message_t state) -+{ -+ cam_data *cam = platform_get_drvdata(pdev); -+ -+ pr_debug("%s\n", __func__); -+ -+ if (cam == NULL) -+ return -1; -+ -+ down(&cam->busy_lock); -+ -+ cam->low_power = true; -+ -+ if (cam->overlay_on == true) -+ stop_preview(cam); -+ if ((cam->capture_on == true) && cam->enc_disable) -+ cam->enc_disable(cam); -+ -+ if (cam->sensor && cam->open_count) { -+ if (cam->mclk_on[cam->mclk_source]) { -+ ipu_csi_enable_mclk_if(cam->ipu, CSI_MCLK_I2C, -+ cam->mclk_source, -+ false, false); -+ cam->mclk_on[cam->mclk_source] = false; -+ } -+ vidioc_int_s_power(cam->sensor, 0); -+ } -+ -+ up(&cam->busy_lock); -+ -+ return 0; -+} -+ -+/*! -+ * This function is called to bring the sensor back from a low power state. -+ * Refer to the document driver-model/driver.txt in the kernel source tree -+ * for more information. -+ * -+ * @param pdev the device structure -+ * -+ * @return The function returns 0 on success and -1 on failure -+ */ -+static int mxc_v4l2_resume(struct platform_device *pdev) -+{ -+ cam_data *cam = platform_get_drvdata(pdev); -+ -+ pr_debug("%s\n", __func__); -+ -+ if (cam == NULL) -+ return -1; -+ -+ down(&cam->busy_lock); -+ -+ cam->low_power = false; -+ wake_up_interruptible(&cam->power_queue); -+ -+ if (cam->sensor && cam->open_count) { -+ if ((cam->overlay_on == true) || (cam->capture_on == true)) -+ vidioc_int_s_power(cam->sensor, 1); -+ -+ if (!cam->mclk_on[cam->mclk_source]) { -+ ipu_csi_enable_mclk_if(cam->ipu, CSI_MCLK_I2C, -+ cam->mclk_source, -+ true, true); -+ cam->mclk_on[cam->mclk_source] = true; -+ } -+ } -+ -+ if (cam->overlay_on == true) -+ start_preview(cam); -+ if (cam->capture_on == true) -+ mxc_streamon(cam); -+ -+ up(&cam->busy_lock); -+ -+ return 0; -+} -+ -+/*! -+ * This structure contains pointers to the power management callback functions. -+ */ -+static struct platform_driver mxc_v4l2_driver = { -+ .driver = { -+ .name = "mxc_v4l2_capture", -+ .owner = THIS_MODULE, -+ .of_match_table = mxc_v4l2_dt_ids, -+ }, -+ .id_table = imx_v4l2_devtype, -+ .probe = mxc_v4l2_probe, -+ .remove = mxc_v4l2_remove, -+ .suspend = mxc_v4l2_suspend, -+ .resume = mxc_v4l2_resume, -+ .shutdown = NULL, -+}; -+ -+/*! -+ * Initializes the camera driver. -+ */ -+static int mxc_v4l2_master_attach(struct v4l2_int_device *slave) -+{ -+ cam_data *cam = slave->u.slave->master->priv; -+ struct v4l2_format cam_fmt; -+ int i; -+ struct sensor_data *sdata = slave->priv; -+ -+ pr_debug("%s:slave.name = %s, master.name = %s\n", __func__, -+ slave->name, slave->u.slave->master->name); -+ -+ if (slave == NULL) { -+ pr_err("ERROR: v4l2 capture: slave parameter not valid.\n"); -+ return -1; -+ } -+ -+ if ((sdata->ipu_id != cam->ipu_id) || (sdata->csi != cam->csi) || (sdata->mipi_camera != cam->mipi_camera)) { -+ pr_info("%s: ipu(%d:%d)/csi(%d:%d)/mipi(%d:%d) doesn't match\n", __func__, -+ sdata->ipu_id, cam->ipu_id, sdata->csi, cam->csi, sdata->mipi_camera, cam->mipi_camera); -+ return -1; -+ } -+ -+ cam->sensor = slave; -+ -+ if (cam->sensor_index < MXC_SENSOR_NUM) { -+ cam->all_sensors[cam->sensor_index] = slave; -+ cam->sensor_index++; -+ } else { -+ pr_err("ERROR: v4l2 capture: slave number exceeds " -+ "the maximum.\n"); -+ return -1; -+ } -+ -+ for (i = 0; i < cam->sensor_index; i++) { -+ pr_err("%s: %x\n", __func__, i); -+ vidioc_int_dev_exit(cam->all_sensors[i]); -+ vidioc_int_s_power(cam->all_sensors[i], 0); -+ } -+ -+ cam_fmt.type = V4L2_BUF_TYPE_VIDEO_CAPTURE; -+ vidioc_int_g_fmt_cap(cam->sensor, &cam_fmt); -+ -+ /* Used to detect TV in (type 1) vs. camera (type 0)*/ -+ cam->device_type = cam_fmt.fmt.pix.priv; -+ -+ /* Set the input size to the ipu for this device */ -+ cam->crop_bounds.top = cam->crop_bounds.left = 0; -+ cam->crop_bounds.width = cam_fmt.fmt.pix.width; -+ cam->crop_bounds.height = cam_fmt.fmt.pix.height; -+ -+ /* This also is the max crop size for this device. */ -+ cam->crop_defrect.top = cam->crop_defrect.left = 0; -+ cam->crop_defrect.width = cam_fmt.fmt.pix.width; -+ cam->crop_defrect.height = cam_fmt.fmt.pix.height; -+ -+ /* At this point, this is also the current image size. */ -+ cam->crop_current.top = cam->crop_current.left = 0; -+ cam->crop_current.width = cam_fmt.fmt.pix.width; -+ cam->crop_current.height = cam_fmt.fmt.pix.height; -+ -+ pr_debug("End of %s: v2f pix widthxheight %d x %d\n", -+ __func__, -+ cam->v2f.fmt.pix.width, cam->v2f.fmt.pix.height); -+ pr_debug("End of %s: crop_bounds widthxheight %d x %d\n", -+ __func__, -+ cam->crop_bounds.width, cam->crop_bounds.height); -+ pr_debug("End of %s: crop_defrect widthxheight %d x %d\n", -+ __func__, -+ cam->crop_defrect.width, cam->crop_defrect.height); -+ pr_debug("End of %s: crop_current widthxheight %d x %d\n", -+ __func__, -+ cam->crop_current.width, cam->crop_current.height); -+ -+ pr_info("%s: ipu%d:/csi%d %s attached %s:%s\n", __func__, -+ cam->ipu_id, cam->csi, cam->mipi_camera ? "mipi" : "parallel", -+ slave->name, slave->u.slave->master->name); -+ return 0; -+} -+ -+/*! -+ * Disconnects the camera driver. -+ */ -+static void mxc_v4l2_master_detach(struct v4l2_int_device *slave) -+{ -+ unsigned int i; -+ cam_data *cam = slave->u.slave->master->priv; -+ -+ pr_debug("%s\n", __func__); -+ -+ if (cam->sensor_index > 1) { -+ for (i = 0; i < cam->sensor_index; i++) { -+ if (cam->all_sensors[i] != slave) -+ continue; -+ /* Move all the sensors behind this -+ * sensor one step forward -+ */ -+ for (; i <= MXC_SENSOR_NUM - 2; i++) -+ cam->all_sensors[i] = cam->all_sensors[i+1]; -+ break; -+ } -+ /* Point current sensor to the last one */ -+ cam->sensor = cam->all_sensors[cam->sensor_index - 2]; -+ } else -+ cam->sensor = NULL; -+ -+ cam->sensor_index--; -+ vidioc_int_dev_exit(slave); -+} -+ -+DEFINE_MUTEX(camera_common_mutex); -+ -+void mxc_camera_common_lock(void) -+{ -+ mutex_lock(&camera_common_mutex); -+} -+EXPORT_SYMBOL(mxc_camera_common_lock); -+ -+void mxc_camera_common_unlock(void) -+{ -+ mutex_unlock(&camera_common_mutex); -+} -+EXPORT_SYMBOL(mxc_camera_common_unlock); -+ -+/*! -+ * Entry point for the V4L2 -+ * -+ * @return Error code indicating success or failure -+ */ -+static __init int camera_init(void) -+{ -+ u8 err = 0; -+ -+ pr_debug("%s\n", __func__); -+ -+ /* Register the device driver structure. */ -+ err = platform_driver_register(&mxc_v4l2_driver); -+ if (err != 0) { -+ pr_err("ERROR: v4l2 capture:camera_init: " -+ "platform_driver_register failed.\n"); -+ return err; -+ } -+ -+ return err; -+} -+ -+/*! -+ * Exit and cleanup for the V4L2 -+ */ -+static void __exit camera_exit(void) -+{ -+ pr_debug("%s\n", __func__); -+ -+ platform_driver_unregister(&mxc_v4l2_driver); -+} -+ -+module_init(camera_init); -+module_exit(camera_exit); -+ -+module_param(video_nr, int, 0444); -+MODULE_AUTHOR("Freescale Semiconductor, Inc."); -+MODULE_DESCRIPTION("V4L2 capture driver for Mxc based cameras"); -+MODULE_LICENSE("GPL"); -+MODULE_SUPPORTED_DEVICE("video"); -diff -Nur linux-4.1.13.orig/drivers/media/platform/mxc/capture/mxc_v4l2_capture.h linux-4.1.13/drivers/media/platform/mxc/capture/mxc_v4l2_capture.h ---- linux-4.1.13.orig/drivers/media/platform/mxc/capture/mxc_v4l2_capture.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/media/platform/mxc/capture/mxc_v4l2_capture.h 2015-11-30 17:56:13.604136128 +0100 -@@ -0,0 +1,355 @@ -+/* -+ * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved. -+ */ -+ -+/* -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+/*! -+ * @defgroup MXC_V4L2_CAPTURE MXC V4L2 Video Capture Driver -+ */ -+/*! -+ * @file mxc_v4l2_capture.h -+ * -+ * @brief mxc V4L2 capture device API Header file -+ * -+ * It include all the defines for frame operations, also three structure defines -+ * use case ops structure, common v4l2 driver structure and frame structure. -+ * -+ * @ingroup MXC_V4L2_CAPTURE -+ */ -+#ifndef __MXC_V4L2_CAPTURE_H__ -+#define __MXC_V4L2_CAPTURE_H__ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include "v4l2-int-device.h" -+ -+ -+#define FRAME_NUM 10 -+#define MXC_SENSOR_NUM 2 -+ -+enum imx_v4l2_devtype { -+ IMX5_V4L2, -+ IMX6_V4L2, -+}; -+ -+/*! -+ * v4l2 frame structure. -+ */ -+struct mxc_v4l_frame { -+ u32 paddress; -+ void *vaddress; -+ int count; -+ int width; -+ int height; -+ -+ struct v4l2_buffer buffer; -+ struct list_head queue; -+ int index; -+ union { -+ int ipu_buf_num; -+ int csi_buf_num; -+ }; -+}; -+ -+/* Only for old version. Will go away soon. */ -+typedef struct { -+ u8 clk_mode; -+ u8 ext_vsync; -+ u8 Vsync_pol; -+ u8 Hsync_pol; -+ u8 pixclk_pol; -+ u8 data_pol; -+ u8 data_width; -+ u8 pack_tight; -+ u8 force_eof; -+ u8 data_en_pol; -+ u16 width; -+ u16 height; -+ u32 pixel_fmt; -+ u32 mclk; -+ u16 active_width; -+ u16 active_height; -+} sensor_interface; -+ -+/* Sensor control function */ -+/* Only for old version. Will go away soon. */ -+struct camera_sensor { -+ void (*set_color) (int bright, int saturation, int red, int green, -+ int blue); -+ void (*get_color) (int *bright, int *saturation, int *red, int *green, -+ int *blue); -+ void (*set_ae_mode) (int ae_mode); -+ void (*get_ae_mode) (int *ae_mode); -+ sensor_interface *(*config) (int *frame_rate, int high_quality); -+ sensor_interface *(*reset) (void); -+ void (*get_std) (v4l2_std_id *std); -+ void (*set_std) (v4l2_std_id std); -+ unsigned int csi; -+}; -+ -+/*! -+ * common v4l2 driver structure. -+ */ -+typedef struct _cam_data { -+ struct video_device *video_dev; -+ int device_type; -+ -+ /* semaphore guard against SMP multithreading */ -+ struct semaphore busy_lock; -+ -+ int open_count; -+ struct delayed_work power_down_work; -+ int power_on; -+ -+ /* params lock for this camera */ -+ struct semaphore param_lock; -+ -+ /* Encoder */ -+ struct list_head ready_q; -+ struct list_head done_q; -+ struct list_head working_q; -+ int ping_pong_csi; -+ spinlock_t queue_int_lock; -+ spinlock_t dqueue_int_lock; -+ struct mxc_v4l_frame frame[FRAME_NUM]; -+ struct mxc_v4l_frame dummy_frame; -+ wait_queue_head_t enc_queue; -+ int enc_counter; -+ dma_addr_t rot_enc_bufs[2]; -+ void *rot_enc_bufs_vaddr[2]; -+ int rot_enc_buf_size[2]; -+ enum v4l2_buf_type type; -+ -+ /* still image capture */ -+ wait_queue_head_t still_queue; -+ int still_counter; -+ dma_addr_t still_buf[2]; -+ void *still_buf_vaddr; -+ -+ /* overlay */ -+ struct v4l2_window win; -+ struct v4l2_framebuffer v4l2_fb; -+ dma_addr_t vf_bufs[2]; -+ void *vf_bufs_vaddr[2]; -+ int vf_bufs_size[2]; -+ dma_addr_t rot_vf_bufs[2]; -+ void *rot_vf_bufs_vaddr[2]; -+ int rot_vf_buf_size[2]; -+ bool overlay_active; -+ int output; -+ struct fb_info *overlay_fb; -+ int fb_origin_std; -+ struct work_struct csi_work_struct; -+ -+ /* v4l2 format */ -+ struct v4l2_format v2f; -+ int rotation; /* for IPUv1 and IPUv3, this means encoder rotation */ -+ int vf_rotation; /* viewfinder rotation only for IPUv1 and IPUv3 */ -+ struct v4l2_mxc_offset offset; -+ -+ /* V4l2 control bit */ -+ int bright; -+ int hue; -+ int contrast; -+ int saturation; -+ int red; -+ int green; -+ int blue; -+ int ae_mode; -+ -+ /* standard */ -+ struct v4l2_streamparm streamparm; -+ struct v4l2_standard standard; -+ bool standard_autodetect; -+ -+ /* crop */ -+ struct v4l2_rect crop_bounds; -+ struct v4l2_rect crop_defrect; -+ struct v4l2_rect crop_current; -+ -+ int (*enc_update_eba) (struct ipu_soc *ipu, dma_addr_t eba, -+ int *bufferNum); -+ int (*enc_enable) (void *private); -+ int (*enc_disable) (void *private); -+ int (*enc_enable_csi) (void *private); -+ int (*enc_disable_csi) (void *private); -+ void (*enc_callback) (u32 mask, void *dev); -+ int (*vf_start_adc) (void *private); -+ int (*vf_stop_adc) (void *private); -+ int (*vf_start_sdc) (void *private); -+ int (*vf_stop_sdc) (void *private); -+ int (*vf_enable_csi) (void *private); -+ int (*vf_disable_csi) (void *private); -+ int (*csi_start) (void *private); -+ int (*csi_stop) (void *private); -+ -+ /* misc status flag */ -+ bool overlay_on; -+ bool capture_on; -+ bool ipu_enable_csi_called; -+ bool mipi_pixelclk_enabled; -+ struct ipu_chan *ipu_chan; -+ struct ipu_chan *ipu_chan_rot; -+ int overlay_pid; -+ int capture_pid; -+ bool low_power; -+ wait_queue_head_t power_queue; -+ unsigned int ipu_id; -+ unsigned int csi; -+ unsigned mipi_camera; -+ int csi_in_use; -+ u8 mclk_source; -+ bool mclk_on[2]; /* two mclk sources at most now */ -+ int current_input; -+ -+ int local_buf_num; -+ -+ /* camera sensor interface */ -+ struct camera_sensor *cam_sensor; /* old version */ -+ struct v4l2_int_device *all_sensors[MXC_SENSOR_NUM]; -+ struct v4l2_int_device *sensor; -+ struct v4l2_int_device *self; -+ int sensor_index; -+ void *ipu; -+ enum imx_v4l2_devtype devtype; -+ -+ /* v4l2 buf elements related to PxP DMA */ -+ struct completion pxp_tx_cmpl; -+ struct pxp_channel *pxp_chan; -+ struct pxp_config_data pxp_conf; -+ struct dma_async_tx_descriptor *txd; -+ dma_cookie_t cookie; -+ struct scatterlist sg[2]; -+} cam_data; -+ -+struct additional_data { -+ u32 map_sizeimage; -+}; -+ -+struct sensor_data { -+ const struct additional_data *adata; -+ struct v4l2_int_device *v4l2_int_device; -+ struct i2c_client *i2c_client; -+ struct v4l2_pix_format pix; -+ struct v4l2_sensor_dimension spix; -+ struct v4l2_captureparm streamcap; -+ bool on; -+ -+ /* control settings */ -+ int brightness; -+ int hue; -+ int contrast; -+ int saturation; -+ int red; -+ int green; -+ int blue; -+ int ae_mode; -+ -+ u32 mclk; -+ u8 mclk_source; -+ struct clk *sensor_clk; -+ int ipu_id; -+ int csi; -+ int last_reg; -+ unsigned mipi_camera; -+ unsigned virtual_channel; /* Used with mipi */ -+ -+ void (*io_init)(void); -+}; -+ -+void set_mclk_rate(uint32_t *p_mclk_freq, uint32_t csi); -+void mxc_camera_common_lock(void); -+void mxc_camera_common_unlock(void); -+ -+static inline int cam_ipu_enable_csi(cam_data *cam) -+{ -+ int ret = ipu_enable_csi(cam->ipu, cam->csi); -+ if (!ret) -+ cam->ipu_enable_csi_called = 1; -+ return ret; -+} -+ -+static inline int cam_ipu_disable_csi(cam_data *cam) -+{ -+ if (!cam->ipu_enable_csi_called) -+ return 0; -+ cam->ipu_enable_csi_called = 0; -+ return ipu_disable_csi(cam->ipu, cam->csi); -+} -+ -+static inline int cam_mipi_csi2_enable(cam_data *cam, struct mipi_fields *mf) -+{ -+#ifdef CONFIG_MXC_MIPI_CSI2 -+ void *mipi_csi2_info; -+ struct sensor_data *sensor; -+ -+ if (!cam->sensor) -+ return 0; -+ sensor = cam->sensor->priv; -+ if (!sensor) -+ return 0; -+ if (!sensor->mipi_camera) -+ return 0; -+ mipi_csi2_info = mipi_csi2_get_info(); -+ -+ if (!mipi_csi2_info) { -+// printk(KERN_ERR "%s() in %s: Fail to get mipi_csi2_info!\n", -+// __func__, __FILE__); -+// return -EPERM; -+ return 0; -+ } -+ if (mipi_csi2_get_status(mipi_csi2_info)) { -+ mf->en = true; -+ mf->vc = 0;//sensor->virtual_channel; -+ mf->id = mipi_csi2_get_datatype(mipi_csi2_info); -+ if (!mipi_csi2_pixelclk_enable(mipi_csi2_info)) -+ cam->mipi_pixelclk_enabled = 1; -+ return 0; -+ } -+ mf->en = false; -+ mf->vc = 0; -+ mf->id = 0; -+#endif -+ return 0; -+} -+ -+static inline int cam_mipi_csi2_disable(cam_data *cam) -+{ -+#ifdef CONFIG_MXC_MIPI_CSI2 -+ void *mipi_csi2_info; -+ -+ if (!cam->mipi_pixelclk_enabled) -+ return 0; -+ cam->mipi_pixelclk_enabled = 0; -+ -+ mipi_csi2_info = mipi_csi2_get_info(); -+ -+ if (!mipi_csi2_info) { -+// printk(KERN_ERR "%s() in %s: Fail to get mipi_csi2_info!\n", -+// __func__, __FILE__); -+// return -EPERM; -+ return 0; -+ } -+ if (mipi_csi2_get_status(mipi_csi2_info)) -+ mipi_csi2_pixelclk_disable(mipi_csi2_info); -+#endif -+ return 0; -+} -+#endif /* __MXC_V4L2_CAPTURE_H__ */ -diff -Nur linux-4.1.13.orig/drivers/media/platform/mxc/capture/ov5640.c linux-4.1.13/drivers/media/platform/mxc/capture/ov5640.c ---- linux-4.1.13.orig/drivers/media/platform/mxc/capture/ov5640.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/media/platform/mxc/capture/ov5640.c 2015-11-30 17:56:13.604136128 +0100 -@@ -0,0 +1,1959 @@ -+/* -+ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved. -+ */ -+ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "mxc_v4l2_capture.h" -+ -+#define OV5640_VOLTAGE_ANALOG 2800000 -+#define OV5640_VOLTAGE_DIGITAL_CORE 1500000 -+#define OV5640_VOLTAGE_DIGITAL_IO 1800000 -+ -+#define MIN_FPS 15 -+#define MAX_FPS 30 -+#define DEFAULT_FPS 30 -+ -+#define OV5640_XCLK_MIN 6000000 -+#define OV5640_XCLK_MAX 24000000 -+ -+#define OV5640_CHIP_ID_HIGH_BYTE 0x300A -+#define OV5640_CHIP_ID_LOW_BYTE 0x300B -+ -+enum ov5640_mode { -+ ov5640_mode_MIN = 0, -+ ov5640_mode_VGA_640_480 = 0, -+ ov5640_mode_QVGA_320_240 = 1, -+ ov5640_mode_NTSC_720_480 = 2, -+ ov5640_mode_PAL_720_576 = 3, -+ ov5640_mode_720P_1280_720 = 4, -+ ov5640_mode_1080P_1920_1080 = 5, -+ ov5640_mode_QSXGA_2592_1944 = 6, -+ ov5640_mode_QCIF_176_144 = 7, -+ ov5640_mode_XGA_1024_768 = 8, -+ ov5640_mode_MAX = 8 -+}; -+ -+enum ov5640_frame_rate { -+ ov5640_15_fps, -+ ov5640_30_fps -+}; -+ -+static int ov5640_framerates[] = { -+ [ov5640_15_fps] = 15, -+ [ov5640_30_fps] = 30, -+}; -+ -+struct reg_value { -+ u16 u16RegAddr; -+ u8 u8Val; -+ u8 u8Mask; -+ u32 u32Delay_ms; -+}; -+ -+struct ov5640_mode_info { -+ enum ov5640_mode mode; -+ u32 width; -+ u32 height; -+ struct reg_value *init_data_ptr; -+ u32 init_data_size; -+}; -+ -+/*! -+ * Maintains the information on the current state of the sesor. -+ */ -+static struct sensor_data ov5640_data; -+static int pwn_gpio, rst_gpio; -+static int prev_sysclk; -+static int AE_Target = 52, night_mode; -+static int prev_HTS; -+static int AE_high, AE_low; -+ -+static struct reg_value ov5640_global_init_setting[] = { -+ {0x3008, 0x42, 0, 0}, -+ {0x3103, 0x03, 0, 0}, {0x3017, 0xff, 0, 0}, {0x3018, 0xff, 0, 0}, -+ {0x3034, 0x1a, 0, 0}, {0x3037, 0x13, 0, 0}, {0x3108, 0x01, 0, 0}, -+ {0x3630, 0x36, 0, 0}, {0x3631, 0x0e, 0, 0}, {0x3632, 0xe2, 0, 0}, -+ {0x3633, 0x12, 0, 0}, {0x3621, 0xe0, 0, 0}, {0x3704, 0xa0, 0, 0}, -+ {0x3703, 0x5a, 0, 0}, {0x3715, 0x78, 0, 0}, {0x3717, 0x01, 0, 0}, -+ {0x370b, 0x60, 0, 0}, {0x3705, 0x1a, 0, 0}, {0x3905, 0x02, 0, 0}, -+ {0x3906, 0x10, 0, 0}, {0x3901, 0x0a, 0, 0}, {0x3731, 0x12, 0, 0}, -+ {0x3600, 0x08, 0, 0}, {0x3601, 0x33, 0, 0}, {0x302d, 0x60, 0, 0}, -+ {0x3620, 0x52, 0, 0}, {0x371b, 0x20, 0, 0}, {0x471c, 0x50, 0, 0}, -+ {0x3a13, 0x43, 0, 0}, {0x3a18, 0x00, 0, 0}, {0x3a19, 0x7c, 0, 0}, -+ {0x3635, 0x13, 0, 0}, {0x3636, 0x03, 0, 0}, {0x3634, 0x40, 0, 0}, -+ {0x3622, 0x01, 0, 0}, {0x3c01, 0x34, 0, 0}, {0x3c04, 0x28, 0, 0}, -+ {0x3c05, 0x98, 0, 0}, {0x3c06, 0x00, 0, 0}, {0x3c07, 0x07, 0, 0}, -+ {0x3c08, 0x00, 0, 0}, {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, -+ {0x3c0b, 0x40, 0, 0}, {0x3810, 0x00, 0, 0}, {0x3811, 0x10, 0, 0}, -+ {0x3812, 0x00, 0, 0}, {0x3708, 0x64, 0, 0}, {0x4001, 0x02, 0, 0}, -+ {0x4005, 0x1a, 0, 0}, {0x3000, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, -+ {0x300e, 0x58, 0, 0}, {0x302e, 0x00, 0, 0}, {0x4300, 0x30, 0, 0}, -+ {0x501f, 0x00, 0, 0}, {0x440e, 0x00, 0, 0}, {0x5000, 0xa7, 0, 0}, -+ {0x3008, 0x02, 0, 0}, -+}; -+ -+static struct reg_value ov5640_init_setting_30fps_VGA[] = { -+ {0x3008, 0x42, 0, 0}, -+ {0x3103, 0x03, 0, 0}, {0x3017, 0xff, 0, 0}, {0x3018, 0xff, 0, 0}, -+ {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0}, {0x3036, 0x46, 0, 0}, -+ {0x3037, 0x13, 0, 0}, {0x3108, 0x01, 0, 0}, {0x3630, 0x36, 0, 0}, -+ {0x3631, 0x0e, 0, 0}, {0x3632, 0xe2, 0, 0}, {0x3633, 0x12, 0, 0}, -+ {0x3621, 0xe0, 0, 0}, {0x3704, 0xa0, 0, 0}, {0x3703, 0x5a, 0, 0}, -+ {0x3715, 0x78, 0, 0}, {0x3717, 0x01, 0, 0}, {0x370b, 0x60, 0, 0}, -+ {0x3705, 0x1a, 0, 0}, {0x3905, 0x02, 0, 0}, {0x3906, 0x10, 0, 0}, -+ {0x3901, 0x0a, 0, 0}, {0x3731, 0x12, 0, 0}, {0x3600, 0x08, 0, 0}, -+ {0x3601, 0x33, 0, 0}, {0x302d, 0x60, 0, 0}, {0x3620, 0x52, 0, 0}, -+ {0x371b, 0x20, 0, 0}, {0x471c, 0x50, 0, 0}, {0x3a13, 0x43, 0, 0}, -+ {0x3a18, 0x00, 0, 0}, {0x3a19, 0xf8, 0, 0}, {0x3635, 0x13, 0, 0}, -+ {0x3636, 0x03, 0, 0}, {0x3634, 0x40, 0, 0}, {0x3622, 0x01, 0, 0}, -+ {0x3c01, 0x34, 0, 0}, {0x3c04, 0x28, 0, 0}, {0x3c05, 0x98, 0, 0}, -+ {0x3c06, 0x00, 0, 0}, {0x3c07, 0x08, 0, 0}, {0x3c08, 0x00, 0, 0}, -+ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, -+ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, -+ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, -+ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, -+ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, -+ {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, -+ {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, -+ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0}, -+ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, -+ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, -+ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, -+ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, -+ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, -+ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, -+ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x3000, 0x00, 0, 0}, -+ {0x3002, 0x1c, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3006, 0xc3, 0, 0}, -+ {0x300e, 0x58, 0, 0}, {0x302e, 0x00, 0, 0}, {0x4300, 0x30, 0, 0}, -+ {0x501f, 0x00, 0, 0}, {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, -+ {0x440e, 0x00, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, -+ {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0}, {0x5000, 0xa7, 0, 0}, -+ {0x5001, 0xa3, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0xf2, 0, 0}, -+ {0x5182, 0x00, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, -+ {0x5185, 0x24, 0, 0}, {0x5186, 0x09, 0, 0}, {0x5187, 0x09, 0, 0}, -+ {0x5188, 0x09, 0, 0}, {0x5189, 0x88, 0, 0}, {0x518a, 0x54, 0, 0}, -+ {0x518b, 0xee, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x50, 0, 0}, -+ {0x518e, 0x34, 0, 0}, {0x518f, 0x6b, 0, 0}, {0x5190, 0x46, 0, 0}, -+ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, -+ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, -+ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x6c, 0, 0}, -+ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x09, 0, 0}, -+ {0x519d, 0x2b, 0, 0}, {0x519e, 0x38, 0, 0}, {0x5381, 0x1e, 0, 0}, -+ {0x5382, 0x5b, 0, 0}, {0x5383, 0x08, 0, 0}, {0x5384, 0x0a, 0, 0}, -+ {0x5385, 0x7e, 0, 0}, {0x5386, 0x88, 0, 0}, {0x5387, 0x7c, 0, 0}, -+ {0x5388, 0x6c, 0, 0}, {0x5389, 0x10, 0, 0}, {0x538a, 0x01, 0, 0}, -+ {0x538b, 0x98, 0, 0}, {0x5300, 0x08, 0, 0}, {0x5301, 0x30, 0, 0}, -+ {0x5302, 0x10, 0, 0}, {0x5303, 0x00, 0, 0}, {0x5304, 0x08, 0, 0}, -+ {0x5305, 0x30, 0, 0}, {0x5306, 0x08, 0, 0}, {0x5307, 0x16, 0, 0}, -+ {0x5309, 0x08, 0, 0}, {0x530a, 0x30, 0, 0}, {0x530b, 0x04, 0, 0}, -+ {0x530c, 0x06, 0, 0}, {0x5480, 0x01, 0, 0}, {0x5481, 0x08, 0, 0}, -+ {0x5482, 0x14, 0, 0}, {0x5483, 0x28, 0, 0}, {0x5484, 0x51, 0, 0}, -+ {0x5485, 0x65, 0, 0}, {0x5486, 0x71, 0, 0}, {0x5487, 0x7d, 0, 0}, -+ {0x5488, 0x87, 0, 0}, {0x5489, 0x91, 0, 0}, {0x548a, 0x9a, 0, 0}, -+ {0x548b, 0xaa, 0, 0}, {0x548c, 0xb8, 0, 0}, {0x548d, 0xcd, 0, 0}, -+ {0x548e, 0xdd, 0, 0}, {0x548f, 0xea, 0, 0}, {0x5490, 0x1d, 0, 0}, -+ {0x5580, 0x02, 0, 0}, {0x5583, 0x40, 0, 0}, {0x5584, 0x10, 0, 0}, -+ {0x5589, 0x10, 0, 0}, {0x558a, 0x00, 0, 0}, {0x558b, 0xf8, 0, 0}, -+ {0x5800, 0x23, 0, 0}, {0x5801, 0x14, 0, 0}, {0x5802, 0x0f, 0, 0}, -+ {0x5803, 0x0f, 0, 0}, {0x5804, 0x12, 0, 0}, {0x5805, 0x26, 0, 0}, -+ {0x5806, 0x0c, 0, 0}, {0x5807, 0x08, 0, 0}, {0x5808, 0x05, 0, 0}, -+ {0x5809, 0x05, 0, 0}, {0x580a, 0x08, 0, 0}, {0x580b, 0x0d, 0, 0}, -+ {0x580c, 0x08, 0, 0}, {0x580d, 0x03, 0, 0}, {0x580e, 0x00, 0, 0}, -+ {0x580f, 0x00, 0, 0}, {0x5810, 0x03, 0, 0}, {0x5811, 0x09, 0, 0}, -+ {0x5812, 0x07, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x00, 0, 0}, -+ {0x5815, 0x01, 0, 0}, {0x5816, 0x03, 0, 0}, {0x5817, 0x08, 0, 0}, -+ {0x5818, 0x0d, 0, 0}, {0x5819, 0x08, 0, 0}, {0x581a, 0x05, 0, 0}, -+ {0x581b, 0x06, 0, 0}, {0x581c, 0x08, 0, 0}, {0x581d, 0x0e, 0, 0}, -+ {0x581e, 0x29, 0, 0}, {0x581f, 0x17, 0, 0}, {0x5820, 0x11, 0, 0}, -+ {0x5821, 0x11, 0, 0}, {0x5822, 0x15, 0, 0}, {0x5823, 0x28, 0, 0}, -+ {0x5824, 0x46, 0, 0}, {0x5825, 0x26, 0, 0}, {0x5826, 0x08, 0, 0}, -+ {0x5827, 0x26, 0, 0}, {0x5828, 0x64, 0, 0}, {0x5829, 0x26, 0, 0}, -+ {0x582a, 0x24, 0, 0}, {0x582b, 0x22, 0, 0}, {0x582c, 0x24, 0, 0}, -+ {0x582d, 0x24, 0, 0}, {0x582e, 0x06, 0, 0}, {0x582f, 0x22, 0, 0}, -+ {0x5830, 0x40, 0, 0}, {0x5831, 0x42, 0, 0}, {0x5832, 0x24, 0, 0}, -+ {0x5833, 0x26, 0, 0}, {0x5834, 0x24, 0, 0}, {0x5835, 0x22, 0, 0}, -+ {0x5836, 0x22, 0, 0}, {0x5837, 0x26, 0, 0}, {0x5838, 0x44, 0, 0}, -+ {0x5839, 0x24, 0, 0}, {0x583a, 0x26, 0, 0}, {0x583b, 0x28, 0, 0}, -+ {0x583c, 0x42, 0, 0}, {0x583d, 0xce, 0, 0}, {0x5025, 0x00, 0, 0}, -+ {0x3a0f, 0x30, 0, 0}, {0x3a10, 0x28, 0, 0}, {0x3a1b, 0x30, 0, 0}, -+ {0x3a1e, 0x26, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x14, 0, 0}, -+ {0x3008, 0x02, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0}, -+ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0}, -+}; -+ -+static struct reg_value ov5640_setting_30fps_VGA_640_480[] = { -+ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, -+ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, -+ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, -+ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, -+ {0x3807, 0x9b, 0, 0}, {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0}, -+ {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, -+ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, -+ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, -+ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0}, -+ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0}, -+ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0}, -+ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, -+ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0}, -+ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0}, -+ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0}, {0x3503, 0x00, 0, 0}, -+}; -+ -+static struct reg_value ov5640_setting_15fps_VGA_640_480[] = { -+ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, -+ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, -+ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, -+ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, -+ {0x3807, 0x9b, 0, 0}, {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0}, -+ {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, -+ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, -+ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, -+ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0}, -+ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0}, -+ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0}, -+ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, -+ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0}, -+ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0}, -+ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0}, {0x3503, 0x00, 0, 0}, -+}; -+ -+static struct reg_value ov5640_setting_30fps_QVGA_320_240[] = { -+ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, -+ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, -+ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, -+ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, -+ {0x3807, 0x9b, 0, 0}, {0x3808, 0x01, 0, 0}, {0x3809, 0x40, 0, 0}, -+ {0x380a, 0x00, 0, 0}, {0x380b, 0xf0, 0, 0}, {0x380c, 0x07, 0, 0}, -+ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, -+ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, -+ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0}, -+ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0}, -+ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0}, -+ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, -+ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0}, -+ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0}, -+ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0}, -+}; -+ -+static struct reg_value ov5640_setting_15fps_QVGA_320_240[] = { -+ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, -+ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, -+ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, -+ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, -+ {0x3807, 0x9b, 0, 0}, {0x3808, 0x01, 0, 0}, {0x3809, 0x40, 0, 0}, -+ {0x380a, 0x00, 0, 0}, {0x380b, 0xf0, 0, 0}, {0x380c, 0x07, 0, 0}, -+ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, -+ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, -+ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0}, -+ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0}, -+ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0}, -+ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, -+ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0}, -+ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0}, -+ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0}, -+}; -+ -+static struct reg_value ov5640_setting_30fps_NTSC_720_480[] = { -+ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, -+ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, -+ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, -+ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x06, 0, 0}, -+ {0x3807, 0xd4, 0, 0}, {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0}, -+ {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, -+ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, -+ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, -+ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0}, -+ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0}, -+ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0}, -+ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, -+ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0}, -+ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0}, -+ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0}, -+}; -+ -+static struct reg_value ov5640_setting_15fps_NTSC_720_480[] = { -+ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, -+ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, -+ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, -+ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x06, 0, 0}, -+ {0x3807, 0xd4, 0, 0}, {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0}, -+ {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, -+ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, -+ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, -+ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0}, -+ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0}, -+ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0}, -+ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, -+ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0}, -+ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0}, -+ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0}, -+}; -+ -+static struct reg_value ov5640_setting_30fps_PAL_720_576[] = { -+ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, -+ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, -+ {0x3801, 0x60, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, -+ {0x3804, 0x09, 0, 0}, {0x3805, 0x7e, 0, 0}, {0x3806, 0x07, 0, 0}, -+ {0x3807, 0x9b, 0, 0}, {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0}, -+ {0x380a, 0x02, 0, 0}, {0x380b, 0x40, 0, 0}, {0x380c, 0x07, 0, 0}, -+ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, -+ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, -+ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0}, -+ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0}, -+ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0}, -+ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, -+ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0}, -+ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0}, -+ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0}, -+}; -+ -+static struct reg_value ov5640_setting_15fps_PAL_720_576[] = { -+ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, -+ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, -+ {0x3801, 0x60, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, -+ {0x3804, 0x09, 0, 0}, {0x3805, 0x7e, 0, 0}, {0x3806, 0x07, 0, 0}, -+ {0x3807, 0x9b, 0, 0}, {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0}, -+ {0x380a, 0x02, 0, 0}, {0x380b, 0x40, 0, 0}, {0x380c, 0x07, 0, 0}, -+ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, -+ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, -+ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0}, -+ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0}, -+ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0}, -+ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, -+ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0}, -+ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0}, -+ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0}, -+}; -+ -+static struct reg_value ov5640_setting_30fps_720P_1280_720[] = { -+ {0x3035, 0x21, 0, 0}, {0x3036, 0x69, 0, 0}, {0x3c07, 0x07, 0, 0}, -+ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, -+ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, -+ {0x3802, 0x00, 0, 0}, {0x3803, 0xfa, 0, 0}, {0x3804, 0x0a, 0, 0}, -+ {0x3805, 0x3f, 0, 0}, {0x3806, 0x06, 0, 0}, {0x3807, 0xa9, 0, 0}, -+ {0x3808, 0x05, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x02, 0, 0}, -+ {0x380b, 0xd0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x64, 0, 0}, -+ {0x380e, 0x02, 0, 0}, {0x380f, 0xe4, 0, 0}, {0x3813, 0x04, 0, 0}, -+ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3709, 0x52, 0, 0}, -+ {0x370c, 0x03, 0, 0}, {0x3a02, 0x02, 0, 0}, {0x3a03, 0xe0, 0, 0}, -+ {0x3a14, 0x02, 0, 0}, {0x3a15, 0xe0, 0, 0}, {0x4004, 0x02, 0, 0}, -+ {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0}, {0x4713, 0x03, 0, 0}, -+ {0x4407, 0x04, 0, 0}, {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0}, -+ {0x4837, 0x16, 0, 0}, {0x3824, 0x04, 0, 0}, {0x5001, 0x83, 0, 0}, -+ {0x3503, 0x00, 0, 0}, -+}; -+ -+static struct reg_value ov5640_setting_15fps_720P_1280_720[] = { -+ {0x3035, 0x41, 0, 0}, {0x3036, 0x69, 0, 0}, {0x3c07, 0x07, 0, 0}, -+ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, -+ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, -+ {0x3802, 0x00, 0, 0}, {0x3803, 0xfa, 0, 0}, {0x3804, 0x0a, 0, 0}, -+ {0x3805, 0x3f, 0, 0}, {0x3806, 0x06, 0, 0}, {0x3807, 0xa9, 0, 0}, -+ {0x3808, 0x05, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x02, 0, 0}, -+ {0x380b, 0xd0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x64, 0, 0}, -+ {0x380e, 0x02, 0, 0}, {0x380f, 0xe4, 0, 0}, {0x3813, 0x04, 0, 0}, -+ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3709, 0x52, 0, 0}, -+ {0x370c, 0x03, 0, 0}, {0x3a02, 0x02, 0, 0}, {0x3a03, 0xe0, 0, 0}, -+ {0x3a14, 0x02, 0, 0}, {0x3a15, 0xe0, 0, 0}, {0x4004, 0x02, 0, 0}, -+ {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0}, {0x4713, 0x03, 0, 0}, -+ {0x4407, 0x04, 0, 0}, {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0}, -+ {0x4837, 0x16, 0, 0}, {0x3824, 0x04, 0, 0}, {0x5001, 0x83, 0, 0}, -+ {0x3503, 0x00, 0, 0}, -+}; -+ -+static struct reg_value ov5640_setting_30fps_QCIF_176_144[] = { -+ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, -+ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, -+ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, -+ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, -+ {0x3807, 0x9b, 0, 0}, {0x3808, 0x00, 0, 0}, {0x3809, 0xb0, 0, 0}, -+ {0x380a, 0x00, 0, 0}, {0x380b, 0x90, 0, 0}, {0x380c, 0x07, 0, 0}, -+ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, -+ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, -+ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0}, -+ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0}, -+ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0}, -+ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, -+ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0}, -+ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x11, 0, 0}, -+ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0}, -+}; -+ -+static struct reg_value ov5640_setting_15fps_QCIF_176_144[] = { -+ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, -+ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, -+ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, -+ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, -+ {0x3807, 0x9b, 0, 0}, {0x3808, 0x00, 0, 0}, {0x3809, 0xb0, 0, 0}, -+ {0x380a, 0x00, 0, 0}, {0x380b, 0x90, 0, 0}, {0x380c, 0x07, 0, 0}, -+ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, -+ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, -+ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0}, -+ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0}, -+ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0}, -+ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, -+ {0x460c, 0x22, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x02, 0, 0}, -+ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0}, -+ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0}, -+}; -+ -+static struct reg_value ov5640_setting_30fps_XGA_1024_768[] = { -+ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, -+ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, -+ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, -+ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, -+ {0x3807, 0x9b, 0, 0}, {0x3808, 0x04, 0, 0}, {0x3809, 0x00, 0, 0}, -+ {0x380a, 0x03, 0, 0}, {0x380b, 0x00, 0, 0}, {0x380c, 0x07, 0, 0}, -+ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, -+ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, -+ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0}, -+ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0}, -+ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0}, -+ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, -+ {0x460c, 0x20, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x01, 0, 0}, -+ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0}, -+ {0x3036, 0x69, 0, 0}, {0x3037, 0x13, 0, 0}, -+}; -+ -+static struct reg_value ov5640_setting_15fps_XGA_1024_768[] = { -+ {0x3c07, 0x08, 0, 0}, {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, -+ {0x3814, 0x31, 0, 0}, {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, -+ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, -+ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, -+ {0x3807, 0x9b, 0, 0}, {0x3808, 0x04, 0, 0}, {0x3809, 0x00, 0, 0}, -+ {0x380a, 0x03, 0, 0}, {0x380b, 0x00, 0, 0}, {0x380c, 0x07, 0, 0}, -+ {0x380d, 0x68, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, -+ {0x3813, 0x06, 0, 0}, {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, -+ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x0b, 0, 0}, -+ {0x3a03, 0x88, 0, 0}, {0x3a14, 0x0b, 0, 0}, {0x3a15, 0x88, 0, 0}, -+ {0x4004, 0x02, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0}, -+ {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, -+ {0x460c, 0x20, 0, 0}, {0x4837, 0x22, 0, 0}, {0x3824, 0x01, 0, 0}, -+ {0x5001, 0xa3, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0}, -+ {0x3036, 0x46, 0, 0}, {0x3037, 0x13, 0, 0}, -+}; -+ -+ -+static struct reg_value ov5640_setting_15fps_1080P_1920_1080[] = { -+ {0x3c07, 0x07, 0, 0}, {0x3820, 0x40, 0, 0}, {0x3821, 0x06, 0, 0}, -+ {0x3814, 0x11, 0, 0}, {0x3815, 0x11, 0, 0}, {0x3800, 0x00, 0, 0}, -+ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0xee, 0, 0}, -+ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x05, 0, 0}, -+ {0x3807, 0xc3, 0, 0}, {0x3808, 0x07, 0, 0}, {0x3809, 0x80, 0, 0}, -+ {0x380a, 0x04, 0, 0}, {0x380b, 0x38, 0, 0}, {0x380c, 0x0b, 0, 0}, -+ {0x380d, 0x1c, 0, 0}, {0x380e, 0x07, 0, 0}, {0x380f, 0xb0, 0, 0}, -+ {0x3813, 0x04, 0, 0}, {0x3618, 0x04, 0, 0}, {0x3612, 0x2b, 0, 0}, -+ {0x3709, 0x12, 0, 0}, {0x370c, 0x00, 0, 0}, {0x3a02, 0x07, 0, 0}, -+ {0x3a03, 0xae, 0, 0}, {0x3a14, 0x07, 0, 0}, {0x3a15, 0xae, 0, 0}, -+ {0x4004, 0x06, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0}, -+ {0x4713, 0x02, 0, 0}, {0x4407, 0x0c, 0, 0}, {0x460b, 0x37, 0, 0}, -+ {0x460c, 0x20, 0, 0}, {0x4837, 0x2c, 0, 0}, {0x3824, 0x01, 0, 0}, -+ {0x5001, 0x83, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0}, -+ {0x3036, 0x69, 0, 0}, {0x3037, 0x13, 0, 0}, -+}; -+ -+static struct reg_value ov5640_setting_15fps_QSXGA_2592_1944[] = { -+ {0x3c07, 0x07, 0, 0}, {0x3820, 0x40, 0, 0}, {0x3821, 0x06, 0, 0}, -+ {0x3814, 0x11, 0, 0}, {0x3815, 0x11, 0, 0}, {0x3800, 0x00, 0, 0}, -+ {0x3801, 0x00, 0, 0}, {0x3802, 0x00, 0, 0}, {0x3803, 0x00, 0, 0}, -+ {0x3804, 0x0a, 0, 0}, {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, -+ {0x3807, 0x9f, 0, 0}, {0x3808, 0x0a, 0, 0}, {0x3809, 0x20, 0, 0}, -+ {0x380a, 0x07, 0, 0}, {0x380b, 0x98, 0, 0}, {0x380c, 0x0b, 0, 0}, -+ {0x380d, 0x1c, 0, 0}, {0x380e, 0x07, 0, 0}, {0x380f, 0xb0, 0, 0}, -+ {0x3813, 0x04, 0, 0}, {0x3618, 0x04, 0, 0}, {0x3612, 0x2b, 0, 0}, -+ {0x3709, 0x12, 0, 0}, {0x370c, 0x00, 0, 0}, {0x3a02, 0x07, 0, 0}, -+ {0x3a03, 0xae, 0, 0}, {0x3a14, 0x07, 0, 0}, {0x3a15, 0xae, 0, 0}, -+ {0x4004, 0x06, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3006, 0xc3, 0, 0}, -+ {0x4713, 0x02, 0, 0}, {0x4407, 0x0c, 0, 0}, {0x460b, 0x37, 0, 0}, -+ {0x460c, 0x20, 0, 0}, {0x4837, 0x2c, 0, 0}, {0x3824, 0x01, 0, 0}, -+ {0x5001, 0x83, 0, 0}, {0x3034, 0x1a, 0, 0}, {0x3035, 0x21, 0, 0}, -+ {0x3036, 0x69, 0, 0}, {0x3037, 0x13, 0, 0}, -+}; -+ -+static struct ov5640_mode_info ov5640_mode_info_data[2][ov5640_mode_MAX + 1] = { -+ { -+ {ov5640_mode_VGA_640_480, 640, 480, -+ ov5640_setting_15fps_VGA_640_480, -+ ARRAY_SIZE(ov5640_setting_15fps_VGA_640_480)}, -+ {ov5640_mode_QVGA_320_240, 320, 240, -+ ov5640_setting_15fps_QVGA_320_240, -+ ARRAY_SIZE(ov5640_setting_15fps_QVGA_320_240)}, -+ {ov5640_mode_NTSC_720_480, 720, 480, -+ ov5640_setting_15fps_NTSC_720_480, -+ ARRAY_SIZE(ov5640_setting_15fps_NTSC_720_480)}, -+ {ov5640_mode_PAL_720_576, 720, 576, -+ ov5640_setting_15fps_PAL_720_576, -+ ARRAY_SIZE(ov5640_setting_15fps_PAL_720_576)}, -+ {ov5640_mode_720P_1280_720, 1280, 720, -+ ov5640_setting_15fps_720P_1280_720, -+ ARRAY_SIZE(ov5640_setting_15fps_720P_1280_720)}, -+ {ov5640_mode_1080P_1920_1080, 1920, 1080, -+ ov5640_setting_15fps_1080P_1920_1080, -+ ARRAY_SIZE(ov5640_setting_15fps_1080P_1920_1080)}, -+ {ov5640_mode_QSXGA_2592_1944, 2592, 1944, -+ ov5640_setting_15fps_QSXGA_2592_1944, -+ ARRAY_SIZE(ov5640_setting_15fps_QSXGA_2592_1944)}, -+ {ov5640_mode_QCIF_176_144, 176, 144, -+ ov5640_setting_15fps_QCIF_176_144, -+ ARRAY_SIZE(ov5640_setting_15fps_QCIF_176_144)}, -+ {ov5640_mode_XGA_1024_768, 1024, 768, -+ ov5640_setting_15fps_XGA_1024_768, -+ ARRAY_SIZE(ov5640_setting_15fps_XGA_1024_768)}, -+ }, -+ { -+ {ov5640_mode_VGA_640_480, 640, 480, -+ ov5640_setting_30fps_VGA_640_480, -+ ARRAY_SIZE(ov5640_setting_30fps_VGA_640_480)}, -+ {ov5640_mode_QVGA_320_240, 320, 240, -+ ov5640_setting_30fps_QVGA_320_240, -+ ARRAY_SIZE(ov5640_setting_30fps_QVGA_320_240)}, -+ {ov5640_mode_NTSC_720_480, 720, 480, -+ ov5640_setting_30fps_NTSC_720_480, -+ ARRAY_SIZE(ov5640_setting_30fps_NTSC_720_480)}, -+ {ov5640_mode_PAL_720_576, 720, 576, -+ ov5640_setting_30fps_PAL_720_576, -+ ARRAY_SIZE(ov5640_setting_30fps_PAL_720_576)}, -+ {ov5640_mode_720P_1280_720, 1280, 720, -+ ov5640_setting_30fps_720P_1280_720, -+ ARRAY_SIZE(ov5640_setting_30fps_720P_1280_720)}, -+ {ov5640_mode_1080P_1920_1080, 0, 0, NULL, 0}, -+ {ov5640_mode_QSXGA_2592_1944, 0, 0, NULL, 0}, -+ {ov5640_mode_QCIF_176_144, 176, 144, -+ ov5640_setting_30fps_QCIF_176_144, -+ ARRAY_SIZE(ov5640_setting_30fps_QCIF_176_144)}, -+ {ov5640_mode_XGA_1024_768, 1024, 768, -+ ov5640_setting_30fps_XGA_1024_768, -+ ARRAY_SIZE(ov5640_setting_30fps_XGA_1024_768)}, -+ }, -+}; -+ -+static struct regulator *io_regulator; -+static struct regulator *core_regulator; -+static struct regulator *analog_regulator; -+ -+static int ov5640_probe(struct i2c_client *adapter, -+ const struct i2c_device_id *device_id); -+static int ov5640_remove(struct i2c_client *client); -+ -+static s32 ov5640_read_reg(u16 reg, u8 *val); -+static s32 ov5640_write_reg(u16 reg, u8 val); -+ -+static const struct i2c_device_id ov5640_id[] = { -+ {"ov5640", 0}, -+ {"ov564x", 0}, -+ {}, -+}; -+ -+MODULE_DEVICE_TABLE(i2c, ov5640_id); -+ -+static struct i2c_driver ov5640_i2c_driver = { -+ .driver = { -+ .owner = THIS_MODULE, -+ .name = "ov5640", -+ }, -+ .probe = ov5640_probe, -+ .remove = ov5640_remove, -+ .id_table = ov5640_id, -+}; -+ -+static inline void ov5640_power_down(int enable) -+{ -+ gpio_set_value(pwn_gpio, enable); -+ -+ msleep(2); -+} -+ -+static inline void ov5640_reset(void) -+{ -+ /* camera reset */ -+ gpio_set_value(rst_gpio, 1); -+ -+ /* camera power down */ -+ gpio_set_value(pwn_gpio, 1); -+ msleep(5); -+ gpio_set_value(pwn_gpio, 0); -+ msleep(5); -+ gpio_set_value(rst_gpio, 0); -+ msleep(1); -+ gpio_set_value(rst_gpio, 1); -+ msleep(5); -+ gpio_set_value(pwn_gpio, 1); -+} -+ -+static int ov5640_regulator_enable(struct device *dev) -+{ -+ int ret = 0; -+ -+ io_regulator = devm_regulator_get(dev, "DOVDD"); -+ if (!IS_ERR(io_regulator)) { -+ regulator_set_voltage(io_regulator, -+ OV5640_VOLTAGE_DIGITAL_IO, -+ OV5640_VOLTAGE_DIGITAL_IO); -+ ret = regulator_enable(io_regulator); -+ if (ret) { -+ dev_err(dev, "set io voltage failed\n"); -+ return ret; -+ } else { -+ dev_dbg(dev, "set io voltage ok\n"); -+ } -+ } else { -+ io_regulator = NULL; -+ dev_warn(dev, "cannot get io voltage\n"); -+ } -+ -+ core_regulator = devm_regulator_get(dev, "DVDD"); -+ if (!IS_ERR(core_regulator)) { -+ regulator_set_voltage(core_regulator, -+ OV5640_VOLTAGE_DIGITAL_CORE, -+ OV5640_VOLTAGE_DIGITAL_CORE); -+ ret = regulator_enable(core_regulator); -+ if (ret) { -+ dev_err(dev, "set core voltage failed\n"); -+ return ret; -+ } else { -+ dev_dbg(dev, "set core voltage ok\n"); -+ } -+ } else { -+ core_regulator = NULL; -+ dev_warn(dev, "cannot get core voltage\n"); -+ } -+ -+ analog_regulator = devm_regulator_get(dev, "AVDD"); -+ if (!IS_ERR(analog_regulator)) { -+ regulator_set_voltage(analog_regulator, -+ OV5640_VOLTAGE_ANALOG, -+ OV5640_VOLTAGE_ANALOG); -+ ret = regulator_enable(analog_regulator); -+ if (ret) { -+ dev_err(dev, "set analog voltage failed\n"); -+ return ret; -+ } else { -+ dev_dbg(dev, "set analog voltage ok\n"); -+ } -+ } else { -+ analog_regulator = NULL; -+ dev_warn(dev, "cannot get analog voltage\n"); -+ } -+ -+ return ret; -+} -+ -+static s32 ov5640_write_reg(u16 reg, u8 val) -+{ -+ u8 au8Buf[3] = {0}; -+ -+ au8Buf[0] = reg >> 8; -+ au8Buf[1] = reg & 0xff; -+ au8Buf[2] = val; -+ -+ if (i2c_master_send(ov5640_data.i2c_client, au8Buf, 3) < 0) { -+ pr_err("%s:write reg error:reg=%x,val=%x\n", -+ __func__, reg, val); -+ return -1; -+ } -+ -+ return 0; -+} -+ -+static s32 ov5640_read_reg(u16 reg, u8 *val) -+{ -+ u8 au8RegBuf[2] = {0}; -+ u8 u8RdVal = 0; -+ -+ au8RegBuf[0] = reg >> 8; -+ au8RegBuf[1] = reg & 0xff; -+ -+ if (2 != i2c_master_send(ov5640_data.i2c_client, au8RegBuf, 2)) { -+ pr_err("%s:write reg error:reg=%x\n", -+ __func__, reg); -+ return -1; -+ } -+ -+ if (1 != i2c_master_recv(ov5640_data.i2c_client, &u8RdVal, 1)) { -+ pr_err("%s:read reg error:reg=%x,val=%x\n", -+ __func__, reg, u8RdVal); -+ return -1; -+ } -+ -+ *val = u8RdVal; -+ -+ return u8RdVal; -+} -+ -+static void ov5640_soft_reset(void) -+{ -+ /* sysclk from pad */ -+ ov5640_write_reg(0x3103, 0x11); -+ -+ /* software reset */ -+ ov5640_write_reg(0x3008, 0x82); -+ -+ /* delay at least 5ms */ -+ msleep(10); -+} -+ -+/* set sensor driver capability -+ * 0x302c[7:6] - strength -+ 00 - 1x -+ 01 - 2x -+ 10 - 3x -+ 11 - 4x -+ */ -+static int ov5640_driver_capability(int strength) -+{ -+ u8 temp = 0; -+ -+ if (strength > 4 || strength < 1) { -+ pr_err("The valid driver capability of ov5640 is 1x~4x\n"); -+ return -EINVAL; -+ } -+ -+ ov5640_read_reg(0x302c, &temp); -+ -+ temp &= ~0xc0; /* clear [7:6] */ -+ temp |= ((strength - 1) << 6); /* set [7:6] */ -+ -+ ov5640_write_reg(0x302c, temp); -+ -+ return 0; -+} -+ -+/* calculate sysclk */ -+static int ov5640_get_sysclk(void) -+{ -+ int xvclk = ov5640_data.mclk / 10000; -+ int sysclk; -+ int temp1, temp2; -+ int Multiplier, PreDiv, VCO, SysDiv, Pll_rdiv, Bit_div2x, sclk_rdiv; -+ int sclk_rdiv_map[] = {1, 2, 4, 8}; -+ u8 regval = 0; -+ -+ temp1 = ov5640_read_reg(0x3034, ®val); -+ temp2 = temp1 & 0x0f; -+ if (temp2 == 8 || temp2 == 10) { -+ Bit_div2x = temp2 / 2; -+ } else { -+ pr_err("ov5640: unsupported bit mode %d\n", temp2); -+ return -1; -+ } -+ -+ temp1 = ov5640_read_reg(0x3035, ®val); -+ SysDiv = temp1 >> 4; -+ if (SysDiv == 0) -+ SysDiv = 16; -+ -+ temp1 = ov5640_read_reg(0x3036, ®val); -+ Multiplier = temp1; -+ temp1 = ov5640_read_reg(0x3037, ®val); -+ PreDiv = temp1 & 0x0f; -+ Pll_rdiv = ((temp1 >> 4) & 0x01) + 1; -+ -+ temp1 = ov5640_read_reg(0x3108, ®val); -+ temp2 = temp1 & 0x03; -+ -+ sclk_rdiv = sclk_rdiv_map[temp2]; -+ VCO = xvclk * Multiplier / PreDiv; -+ sysclk = VCO / SysDiv / Pll_rdiv * 2 / Bit_div2x / sclk_rdiv; -+ -+ return sysclk; -+} -+ -+/* read HTS from register settings */ -+static int ov5640_get_HTS(void) -+{ -+ int HTS; -+ u8 temp = 0; -+ -+ HTS = ov5640_read_reg(0x380c, &temp); -+ HTS = (HTS<<8) + ov5640_read_reg(0x380d, &temp); -+ return HTS; -+} -+ -+/* read VTS from register settings */ -+static int ov5640_get_VTS(void) -+{ -+ int VTS; -+ u8 temp = 0; -+ -+ VTS = ov5640_read_reg(0x380e, &temp); -+ VTS = (VTS<<8) + ov5640_read_reg(0x380f, &temp); -+ -+ return VTS; -+} -+ -+/* write VTS to registers */ -+static int ov5640_set_VTS(int VTS) -+{ -+ int temp; -+ -+ temp = VTS & 0xff; -+ ov5640_write_reg(0x380f, temp); -+ -+ temp = VTS>>8; -+ ov5640_write_reg(0x380e, temp); -+ return 0; -+} -+ -+/* read shutter, in number of line period */ -+static int ov5640_get_shutter(void) -+{ -+ int shutter; -+ u8 regval; -+ -+ shutter = (ov5640_read_reg(0x03500, ®val) & 0x0f); -+ -+ shutter = (shutter<<8) + ov5640_read_reg(0x3501, ®val); -+ shutter = (shutter<<4) + (ov5640_read_reg(0x3502, ®val)>>4); -+ -+ return shutter; -+} -+ -+/* write shutter, in number of line period */ -+static int ov5640_set_shutter(int shutter) -+{ -+ int temp; -+ -+ shutter = shutter & 0xffff; -+ temp = shutter & 0x0f; -+ temp = temp<<4; -+ ov5640_write_reg(0x3502, temp); -+ -+ temp = shutter & 0xfff; -+ temp = temp>>4; -+ ov5640_write_reg(0x3501, temp); -+ -+ temp = shutter>>12; -+ ov5640_write_reg(0x3500, temp); -+ -+ return 0; -+} -+ -+/* read gain, 16 = 1x */ -+static int ov5640_get_gain16(void) -+{ -+ int gain16; -+ u8 regval; -+ -+ gain16 = ov5640_read_reg(0x350a, ®val) & 0x03; -+ gain16 = (gain16<<8) + ov5640_read_reg(0x350b, ®val); -+ -+ return gain16; -+} -+ -+/* write gain, 16 = 1x */ -+static int ov5640_set_gain16(int gain16) -+{ -+ int temp; -+ -+ gain16 = gain16 & 0x3ff; -+ temp = gain16 & 0xff; -+ -+ ov5640_write_reg(0x350b, temp); -+ temp = gain16>>8; -+ -+ ov5640_write_reg(0x350a, temp); -+ return 0; -+} -+ -+/* get banding filter value */ -+static int ov5640_get_light_freq(void) -+{ -+ int temp, temp1, light_frequency; -+ u8 regval; -+ -+ temp = ov5640_read_reg(0x3c01, ®val); -+ if (temp & 0x80) { -+ /* manual */ -+ temp1 = ov5640_read_reg(0x3c00, ®val); -+ if (temp1 & 0x04) { -+ /* 50Hz */ -+ light_frequency = 50; -+ } else { -+ /* 60Hz */ -+ light_frequency = 60; -+ } -+ } else { -+ /* auto */ -+ temp1 = ov5640_read_reg(0x3c0c, ®val); -+ if (temp1 & 0x01) { -+ /* 50Hz */ -+ light_frequency = 50; -+ } else { -+ /* 60Hz */ -+ light_frequency = 60; -+ } -+ } -+ -+ return light_frequency; -+} -+ -+static void ov5640_set_bandingfilter(void) -+{ -+ int prev_VTS; -+ int band_step60, max_band60, band_step50, max_band50; -+ -+ /* read preview PCLK */ -+ prev_sysclk = ov5640_get_sysclk(); -+ -+ /* read preview HTS */ -+ prev_HTS = ov5640_get_HTS(); -+ -+ /* read preview VTS */ -+ prev_VTS = ov5640_get_VTS(); -+ -+ /* calculate banding filter */ -+ /* 60Hz */ -+ band_step60 = prev_sysclk * 100/prev_HTS * 100/120; -+ ov5640_write_reg(0x3a0a, (band_step60 >> 8)); -+ ov5640_write_reg(0x3a0b, (band_step60 & 0xff)); -+ -+ max_band60 = (int)((prev_VTS-4)/band_step60); -+ ov5640_write_reg(0x3a0d, max_band60); -+ -+ /* 50Hz */ -+ band_step50 = prev_sysclk * 100/prev_HTS; -+ ov5640_write_reg(0x3a08, (band_step50 >> 8)); -+ ov5640_write_reg(0x3a09, (band_step50 & 0xff)); -+ -+ max_band50 = (int)((prev_VTS-4)/band_step50); -+ ov5640_write_reg(0x3a0e, max_band50); -+} -+ -+/* stable in high */ -+static int ov5640_set_AE_target(int target) -+{ -+ int fast_high, fast_low; -+ -+ AE_low = target * 23 / 25; /* 0.92 */ -+ AE_high = target * 27 / 25; /* 1.08 */ -+ fast_high = AE_high << 1; -+ -+ if (fast_high > 255) -+ fast_high = 255; -+ fast_low = AE_low >> 1; -+ -+ ov5640_write_reg(0x3a0f, AE_high); -+ ov5640_write_reg(0x3a10, AE_low); -+ ov5640_write_reg(0x3a1b, AE_high); -+ ov5640_write_reg(0x3a1e, AE_low); -+ ov5640_write_reg(0x3a11, fast_high); -+ ov5640_write_reg(0x3a1f, fast_low); -+ -+ return 0; -+} -+ -+/* enable = 0 to turn off night mode -+ enable = 1 to turn on night mode */ -+static int ov5640_set_night_mode(int enable) -+{ -+ u8 mode; -+ -+ ov5640_read_reg(0x3a00, &mode); -+ -+ if (enable) { -+ /* night mode on */ -+ mode |= 0x04; -+ ov5640_write_reg(0x3a00, mode); -+ } else { -+ /* night mode off */ -+ mode &= 0xfb; -+ ov5640_write_reg(0x3a00, mode); -+ } -+ -+ return 0; -+} -+ -+/* enable = 0 to turn off AEC/AGC -+ enable = 1 to turn on AEC/AGC */ -+void ov5640_turn_on_AE_AG(int enable) -+{ -+ u8 ae_ag_ctrl; -+ -+ ov5640_read_reg(0x3503, &ae_ag_ctrl); -+ if (enable) { -+ /* turn on auto AE/AG */ -+ ae_ag_ctrl = ae_ag_ctrl & ~(0x03); -+ } else { -+ /* turn off AE/AG */ -+ ae_ag_ctrl = ae_ag_ctrl | 0x03; -+ } -+ ov5640_write_reg(0x3503, ae_ag_ctrl); -+} -+ -+/* download ov5640 settings to sensor through i2c */ -+static int ov5640_download_firmware(struct reg_value *pModeSetting, s32 ArySize) -+{ -+ register u32 Delay_ms = 0; -+ register u16 RegAddr = 0; -+ register u8 Mask = 0; -+ register u8 Val = 0; -+ u8 RegVal = 0; -+ int i, retval = 0; -+ -+ for (i = 0; i < ArySize; ++i, ++pModeSetting) { -+ Delay_ms = pModeSetting->u32Delay_ms; -+ RegAddr = pModeSetting->u16RegAddr; -+ Val = pModeSetting->u8Val; -+ Mask = pModeSetting->u8Mask; -+ -+ if (Mask) { -+ retval = ov5640_read_reg(RegAddr, &RegVal); -+ if (retval < 0) -+ goto err; -+ -+ RegVal &= ~(u8)Mask; -+ Val &= Mask; -+ Val |= RegVal; -+ } -+ -+ retval = ov5640_write_reg(RegAddr, Val); -+ if (retval < 0) -+ goto err; -+ -+ if (Delay_ms) -+ msleep(Delay_ms); -+ } -+err: -+ return retval; -+} -+ -+static int ov5640_init_mode(void) -+{ -+ struct reg_value *pModeSetting = NULL; -+ int ArySize = 0, retval = 0; -+ -+ ov5640_soft_reset(); -+ -+ pModeSetting = ov5640_global_init_setting; -+ ArySize = ARRAY_SIZE(ov5640_global_init_setting); -+ retval = ov5640_download_firmware(pModeSetting, ArySize); -+ if (retval < 0) -+ goto err; -+ -+ pModeSetting = ov5640_init_setting_30fps_VGA; -+ ArySize = ARRAY_SIZE(ov5640_init_setting_30fps_VGA); -+ retval = ov5640_download_firmware(pModeSetting, ArySize); -+ if (retval < 0) -+ goto err; -+ -+ /* change driver capability to 2x according to validation board. -+ * if the image is not stable, please increase the driver strength. -+ */ -+ ov5640_driver_capability(2); -+ ov5640_set_bandingfilter(); -+ ov5640_set_AE_target(AE_Target); -+ ov5640_set_night_mode(night_mode); -+ -+ /* skip 9 vysnc: start capture at 10th vsync */ -+ msleep(300); -+ -+ /* turn off night mode */ -+ night_mode = 0; -+ ov5640_data.pix.width = 640; -+ ov5640_data.pix.height = 480; -+err: -+ return retval; -+} -+ -+/* change to or back to subsampling mode set the mode directly -+ * image size below 1280 * 960 is subsampling mode */ -+static int ov5640_change_mode_direct(enum ov5640_frame_rate frame_rate, -+ enum ov5640_mode mode) -+{ -+ struct reg_value *pModeSetting = NULL; -+ s32 ArySize = 0; -+ int retval = 0; -+ -+ if (mode > ov5640_mode_MAX || mode < ov5640_mode_MIN) { -+ pr_err("Wrong ov5640 mode detected!\n"); -+ return -1; -+ } -+ -+ pModeSetting = ov5640_mode_info_data[frame_rate][mode].init_data_ptr; -+ ArySize = -+ ov5640_mode_info_data[frame_rate][mode].init_data_size; -+ -+ ov5640_data.pix.width = ov5640_mode_info_data[frame_rate][mode].width; -+ ov5640_data.pix.height = ov5640_mode_info_data[frame_rate][mode].height; -+ -+ if (ov5640_data.pix.width == 0 || ov5640_data.pix.height == 0 || -+ pModeSetting == NULL || ArySize == 0) -+ return -EINVAL; -+ -+ /* set ov5640 to subsampling mode */ -+ retval = ov5640_download_firmware(pModeSetting, ArySize); -+ -+ /* turn on AE AG for subsampling mode, in case the firmware didn't */ -+ ov5640_turn_on_AE_AG(1); -+ -+ /* calculate banding filter */ -+ ov5640_set_bandingfilter(); -+ -+ /* set AE target */ -+ ov5640_set_AE_target(AE_Target); -+ -+ /* update night mode setting */ -+ ov5640_set_night_mode(night_mode); -+ -+ /* skip 9 vysnc: start capture at 10th vsync */ -+ if (mode == ov5640_mode_XGA_1024_768 && frame_rate == ov5640_30_fps) { -+ pr_warning("ov5640: actual frame rate of XGA is 22.5fps\n"); -+ /* 1/22.5 * 9*/ -+ msleep(400); -+ return retval; -+ } -+ -+ if (frame_rate == ov5640_15_fps) { -+ /* 1/15 * 9*/ -+ msleep(600); -+ } else if (frame_rate == ov5640_30_fps) { -+ /* 1/30 * 9*/ -+ msleep(300); -+ } -+ -+ return retval; -+} -+ -+/* change to scaling mode go through exposure calucation -+ * image size above 1280 * 960 is scaling mode */ -+static int ov5640_change_mode_exposure_calc(enum ov5640_frame_rate frame_rate, -+ enum ov5640_mode mode) -+{ -+ int prev_shutter, prev_gain16, average; -+ int cap_shutter, cap_gain16; -+ int cap_sysclk, cap_HTS, cap_VTS; -+ int light_freq, cap_bandfilt, cap_maxband; -+ long cap_gain16_shutter; -+ u8 temp; -+ struct reg_value *pModeSetting = NULL; -+ s32 ArySize = 0; -+ int retval = 0; -+ -+ /* check if the input mode and frame rate is valid */ -+ pModeSetting = -+ ov5640_mode_info_data[frame_rate][mode].init_data_ptr; -+ ArySize = -+ ov5640_mode_info_data[frame_rate][mode].init_data_size; -+ -+ ov5640_data.pix.width = -+ ov5640_mode_info_data[frame_rate][mode].width; -+ ov5640_data.pix.height = -+ ov5640_mode_info_data[frame_rate][mode].height; -+ -+ if (ov5640_data.pix.width == 0 || ov5640_data.pix.height == 0 || -+ pModeSetting == NULL || ArySize == 0) -+ return -EINVAL; -+ -+ /* read preview shutter */ -+ prev_shutter = ov5640_get_shutter(); -+ -+ /* read preview gain */ -+ prev_gain16 = ov5640_get_gain16(); -+ -+ /* get average */ -+ average = ov5640_read_reg(0x56a1, &temp); -+ -+ /* turn off night mode for capture */ -+ ov5640_set_night_mode(0); -+ -+ /* turn off overlay */ -+ ov5640_write_reg(0x3022, 0x06); -+ -+ /* Write capture setting */ -+ retval = ov5640_download_firmware(pModeSetting, ArySize); -+ if (retval < 0) -+ goto err; -+ -+ /* turn off AE AG when capture image. */ -+ ov5640_turn_on_AE_AG(0); -+ -+ /* read capture VTS */ -+ cap_VTS = ov5640_get_VTS(); -+ cap_HTS = ov5640_get_HTS(); -+ cap_sysclk = ov5640_get_sysclk(); -+ -+ /* calculate capture banding filter */ -+ light_freq = ov5640_get_light_freq(); -+ if (light_freq == 60) { -+ /* 60Hz */ -+ cap_bandfilt = cap_sysclk * 100 / cap_HTS * 100 / 120; -+ } else { -+ /* 50Hz */ -+ cap_bandfilt = cap_sysclk * 100 / cap_HTS; -+ } -+ cap_maxband = (int)((cap_VTS - 4)/cap_bandfilt); -+ /* calculate capture shutter/gain16 */ -+ if (average > AE_low && average < AE_high) { -+ /* in stable range */ -+ cap_gain16_shutter = -+ prev_gain16 * prev_shutter * cap_sysclk/prev_sysclk * -+ prev_HTS/cap_HTS * AE_Target / average; -+ } else { -+ cap_gain16_shutter = -+ prev_gain16 * prev_shutter * cap_sysclk/prev_sysclk * -+ prev_HTS/cap_HTS; -+ } -+ -+ /* gain to shutter */ -+ if (cap_gain16_shutter < (cap_bandfilt * 16)) { -+ /* shutter < 1/100 */ -+ cap_shutter = cap_gain16_shutter/16; -+ if (cap_shutter < 1) -+ cap_shutter = 1; -+ cap_gain16 = cap_gain16_shutter/cap_shutter; -+ if (cap_gain16 < 16) -+ cap_gain16 = 16; -+ } else { -+ if (cap_gain16_shutter > (cap_bandfilt*cap_maxband*16)) { -+ /* exposure reach max */ -+ cap_shutter = cap_bandfilt*cap_maxband; -+ cap_gain16 = cap_gain16_shutter / cap_shutter; -+ } else { -+ /* 1/100 < cap_shutter =< max, cap_shutter = n/100 */ -+ cap_shutter = -+ ((int)(cap_gain16_shutter/16/cap_bandfilt)) -+ * cap_bandfilt; -+ cap_gain16 = cap_gain16_shutter / cap_shutter; -+ } -+ } -+ -+ /* write capture gain */ -+ ov5640_set_gain16(cap_gain16); -+ -+ /* write capture shutter */ -+ if (cap_shutter > (cap_VTS - 4)) { -+ cap_VTS = cap_shutter + 4; -+ ov5640_set_VTS(cap_VTS); -+ } -+ -+ ov5640_set_shutter(cap_shutter); -+ -+ /* skip 2 vysnc: start capture at 3rd vsync -+ * frame rate of QSXGA and 1080P is 7.5fps: 1/7.5 * 2 -+ */ -+ pr_warning("ov5640: the actual frame rate of %s is 7.5fps\n", -+ mode == ov5640_mode_1080P_1920_1080 ? "1080P" : "QSXGA"); -+ msleep(267); -+err: -+ return retval; -+} -+ -+static int ov5640_change_mode(enum ov5640_frame_rate frame_rate, -+ enum ov5640_mode mode) -+{ -+ int retval = 0; -+ -+ if (mode > ov5640_mode_MAX || mode < ov5640_mode_MIN) { -+ pr_err("Wrong ov5640 mode detected!\n"); -+ return -1; -+ } -+ -+ if (mode == ov5640_mode_1080P_1920_1080 || -+ mode == ov5640_mode_QSXGA_2592_1944) { -+ /* change to scaling mode go through exposure calucation -+ * image size above 1280 * 960 is scaling mode */ -+ retval = ov5640_change_mode_exposure_calc(frame_rate, mode); -+ } else { -+ /* change back to subsampling modem download firmware directly -+ * image size below 1280 * 960 is subsampling mode */ -+ retval = ov5640_change_mode_direct(frame_rate, mode); -+ } -+ -+ return retval; -+} -+ -+/* --------------- IOCTL functions from v4l2_int_ioctl_desc --------------- */ -+ -+static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p) -+{ -+ if (s == NULL) { -+ pr_err(" ERROR!! no slave device set!\n"); -+ return -1; -+ } -+ -+ memset(p, 0, sizeof(*p)); -+ p->u.bt656.clock_curr = ov5640_data.mclk; -+ pr_debug(" clock_curr=mclk=%d\n", ov5640_data.mclk); -+ p->if_type = V4L2_IF_TYPE_BT656; -+ p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT; -+ p->u.bt656.clock_min = OV5640_XCLK_MIN; -+ p->u.bt656.clock_max = OV5640_XCLK_MAX; -+ p->u.bt656.bt_sync_correct = 1; /* Indicate external vsync */ -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_s_power - V4L2 sensor interface handler for VIDIOC_S_POWER ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @on: indicates power mode (on or off) -+ * -+ * Turns the power on or off, depending on the value of on and returns the -+ * appropriate error code. -+ */ -+static int ioctl_s_power(struct v4l2_int_device *s, int on) -+{ -+ struct sensor_data *sensor = s->priv; -+ -+ if (on && !sensor->on) { -+ if (io_regulator) -+ if (regulator_enable(io_regulator) != 0) -+ return -EIO; -+ if (core_regulator) -+ if (regulator_enable(core_regulator) != 0) -+ return -EIO; -+ if (analog_regulator) -+ if (regulator_enable(analog_regulator) != 0) -+ return -EIO; -+ /* Make sure power on */ -+ ov5640_power_down(0); -+ } else if (!on && sensor->on) { -+ if (analog_regulator) -+ regulator_disable(analog_regulator); -+ if (core_regulator) -+ regulator_disable(core_regulator); -+ if (io_regulator) -+ regulator_disable(io_regulator); -+ -+ ov5640_power_down(1); -+} -+ -+ sensor->on = on; -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure -+ * -+ * Returns the sensor's video CAPTURE parameters. -+ */ -+static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) -+{ -+ struct sensor_data *sensor = s->priv; -+ struct v4l2_captureparm *cparm = &a->parm.capture; -+ int ret = 0; -+ -+ switch (a->type) { -+ /* This is the only case currently handled. */ -+ case V4L2_BUF_TYPE_VIDEO_CAPTURE: -+ memset(a, 0, sizeof(*a)); -+ a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; -+ cparm->capability = sensor->streamcap.capability; -+ cparm->timeperframe = sensor->streamcap.timeperframe; -+ cparm->capturemode = sensor->streamcap.capturemode; -+ ret = 0; -+ break; -+ -+ /* These are all the possible cases. */ -+ case V4L2_BUF_TYPE_VIDEO_OUTPUT: -+ case V4L2_BUF_TYPE_VIDEO_OVERLAY: -+ case V4L2_BUF_TYPE_VBI_CAPTURE: -+ case V4L2_BUF_TYPE_VBI_OUTPUT: -+ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: -+ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: -+ ret = -EINVAL; -+ break; -+ -+ default: -+ pr_debug(" type is unknown - %d\n", a->type); -+ ret = -EINVAL; -+ break; -+ } -+ -+ return ret; -+} -+ -+/*! -+ * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure -+ * -+ * Configures the sensor to use the input parameters, if possible. If -+ * not possible, reverts to the old parameters and returns the -+ * appropriate error code. -+ */ -+static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) -+{ -+ struct sensor_data *sensor = s->priv; -+ struct v4l2_fract *timeperframe = &a->parm.capture.timeperframe; -+ u32 tgt_fps; /* target frames per secound */ -+ enum ov5640_frame_rate frame_rate; -+ int ret = 0; -+ -+ /* Make sure power on */ -+ ov5640_power_down(0); -+ -+ switch (a->type) { -+ /* This is the only case currently handled. */ -+ case V4L2_BUF_TYPE_VIDEO_CAPTURE: -+ /* Check that the new frame rate is allowed. */ -+ if ((timeperframe->numerator == 0) || -+ (timeperframe->denominator == 0)) { -+ timeperframe->denominator = DEFAULT_FPS; -+ timeperframe->numerator = 1; -+ } -+ -+ tgt_fps = timeperframe->denominator / -+ timeperframe->numerator; -+ -+ if (tgt_fps > MAX_FPS) { -+ timeperframe->denominator = MAX_FPS; -+ timeperframe->numerator = 1; -+ } else if (tgt_fps < MIN_FPS) { -+ timeperframe->denominator = MIN_FPS; -+ timeperframe->numerator = 1; -+ } -+ -+ /* Actual frame rate we use */ -+ tgt_fps = timeperframe->denominator / -+ timeperframe->numerator; -+ -+ if (tgt_fps == 15) -+ frame_rate = ov5640_15_fps; -+ else if (tgt_fps == 30) -+ frame_rate = ov5640_30_fps; -+ else { -+ pr_err(" The camera frame rate is not supported!\n"); -+ return -EINVAL; -+ } -+ -+ ret = ov5640_change_mode(frame_rate, -+ a->parm.capture.capturemode); -+ if (ret < 0) -+ return ret; -+ -+ sensor->streamcap.timeperframe = *timeperframe; -+ sensor->streamcap.capturemode = a->parm.capture.capturemode; -+ -+ break; -+ -+ /* These are all the possible cases. */ -+ case V4L2_BUF_TYPE_VIDEO_OUTPUT: -+ case V4L2_BUF_TYPE_VIDEO_OVERLAY: -+ case V4L2_BUF_TYPE_VBI_CAPTURE: -+ case V4L2_BUF_TYPE_VBI_OUTPUT: -+ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: -+ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: -+ pr_debug(" type is not " \ -+ "V4L2_BUF_TYPE_VIDEO_CAPTURE but %d\n", -+ a->type); -+ ret = -EINVAL; -+ break; -+ -+ default: -+ pr_debug(" type is unknown - %d\n", a->type); -+ ret = -EINVAL; -+ break; -+ } -+ -+ return ret; -+} -+ -+/*! -+ * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap -+ * @s: pointer to standard V4L2 device structure -+ * @f: pointer to standard V4L2 v4l2_format structure -+ * -+ * Returns the sensor's current pixel format in the v4l2_format -+ * parameter. -+ */ -+static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) -+{ -+ struct sensor_data *sensor = s->priv; -+ -+ f->fmt.pix = sensor->pix; -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure -+ * -+ * If the requested control is supported, returns the control's current -+ * value from the video_control[] array. Otherwise, returns -EINVAL -+ * if the control is not supported. -+ */ -+static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) -+{ -+ int ret = 0; -+ -+ switch (vc->id) { -+ case V4L2_CID_BRIGHTNESS: -+ vc->value = ov5640_data.brightness; -+ break; -+ case V4L2_CID_HUE: -+ vc->value = ov5640_data.hue; -+ break; -+ case V4L2_CID_CONTRAST: -+ vc->value = ov5640_data.contrast; -+ break; -+ case V4L2_CID_SATURATION: -+ vc->value = ov5640_data.saturation; -+ break; -+ case V4L2_CID_RED_BALANCE: -+ vc->value = ov5640_data.red; -+ break; -+ case V4L2_CID_BLUE_BALANCE: -+ vc->value = ov5640_data.blue; -+ break; -+ case V4L2_CID_EXPOSURE: -+ vc->value = ov5640_data.ae_mode; -+ break; -+ default: -+ ret = -EINVAL; -+ } -+ -+ return ret; -+} -+ -+/*! -+ * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure -+ * -+ * If the requested control is supported, sets the control's current -+ * value in HW (and updates the video_control[] array). Otherwise, -+ * returns -EINVAL if the control is not supported. -+ */ -+static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) -+{ -+ int retval = 0; -+ -+ pr_debug("In ov5640:ioctl_s_ctrl %d\n", -+ vc->id); -+ -+ switch (vc->id) { -+ case V4L2_CID_BRIGHTNESS: -+ break; -+ case V4L2_CID_CONTRAST: -+ break; -+ case V4L2_CID_SATURATION: -+ break; -+ case V4L2_CID_HUE: -+ break; -+ case V4L2_CID_AUTO_WHITE_BALANCE: -+ break; -+ case V4L2_CID_DO_WHITE_BALANCE: -+ break; -+ case V4L2_CID_RED_BALANCE: -+ break; -+ case V4L2_CID_BLUE_BALANCE: -+ break; -+ case V4L2_CID_GAMMA: -+ break; -+ case V4L2_CID_EXPOSURE: -+ break; -+ case V4L2_CID_AUTOGAIN: -+ break; -+ case V4L2_CID_GAIN: -+ break; -+ case V4L2_CID_HFLIP: -+ break; -+ case V4L2_CID_VFLIP: -+ break; -+ default: -+ retval = -EPERM; -+ break; -+ } -+ -+ return retval; -+} -+ -+/*! -+ * ioctl_enum_framesizes - V4L2 sensor interface handler for -+ * VIDIOC_ENUM_FRAMESIZES ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure -+ * -+ * Return 0 if successful, otherwise -EINVAL. -+ */ -+static int ioctl_enum_framesizes(struct v4l2_int_device *s, -+ struct v4l2_frmsizeenum *fsize) -+{ -+ if (fsize->index > ov5640_mode_MAX) -+ return -EINVAL; -+ -+ fsize->pixel_format = ov5640_data.pix.pixelformat; -+ fsize->discrete.width = -+ max(ov5640_mode_info_data[0][fsize->index].width, -+ ov5640_mode_info_data[1][fsize->index].width); -+ fsize->discrete.height = -+ max(ov5640_mode_info_data[0][fsize->index].height, -+ ov5640_mode_info_data[1][fsize->index].height); -+ return 0; -+} -+ -+/*! -+ * ioctl_enum_frameintervals - V4L2 sensor interface handler for -+ * VIDIOC_ENUM_FRAMEINTERVALS ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @fival: standard V4L2 VIDIOC_ENUM_FRAMEINTERVALS ioctl structure -+ * -+ * Return 0 if successful, otherwise -EINVAL. -+ */ -+static int ioctl_enum_frameintervals(struct v4l2_int_device *s, -+ struct v4l2_frmivalenum *fival) -+{ -+ int i, j, count; -+ -+ if (fival->index < 0 || fival->index > ov5640_mode_MAX) -+ return -EINVAL; -+ -+ if (fival->width == 0 || fival->height == 0 || -+ fival->pixel_format == 0) { -+ pr_warning("Please assign pixelformat, width and height.\n"); -+ return -EINVAL; -+ } -+ -+ fival->type = V4L2_FRMIVAL_TYPE_DISCRETE; -+ fival->discrete.numerator = 1; -+ -+ count = 0; -+ for (i = 0; i < ARRAY_SIZE(ov5640_mode_info_data); i++) { -+ for (j = 0; j < (ov5640_mode_MAX + 1); j++) { -+ if (fival->pixel_format == ov5640_data.pix.pixelformat -+ && fival->width == ov5640_mode_info_data[i][j].width -+ && fival->height == ov5640_mode_info_data[i][j].height -+ && ov5640_mode_info_data[i][j].init_data_ptr != NULL) { -+ count++; -+ } -+ if (fival->index == (count - 1)) { -+ fival->discrete.denominator = -+ ov5640_framerates[i]; -+ return 0; -+ } -+ } -+ } -+ -+ return -EINVAL; -+} -+ -+/*! -+ * ioctl_g_chip_ident - V4L2 sensor interface handler for -+ * VIDIOC_DBG_G_CHIP_IDENT ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @id: pointer to int -+ * -+ * Return 0. -+ */ -+static int ioctl_g_chip_ident(struct v4l2_int_device *s, int *id) -+{ -+ ((struct v4l2_dbg_chip_ident *)id)->match.type = -+ V4L2_CHIP_MATCH_I2C_DRIVER; -+ strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name, "ov5640_camera"); -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT -+ * @s: pointer to standard V4L2 device structure -+ */ -+static int ioctl_init(struct v4l2_int_device *s) -+{ -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_enum_fmt_cap - V4L2 sensor interface handler for VIDIOC_ENUM_FMT -+ * @s: pointer to standard V4L2 device structure -+ * @fmt: pointer to standard V4L2 fmt description structure -+ * -+ * Return 0. -+ */ -+static int ioctl_enum_fmt_cap(struct v4l2_int_device *s, -+ struct v4l2_fmtdesc *fmt) -+{ -+ if (fmt->index > ov5640_mode_MAX) -+ return -EINVAL; -+ -+ fmt->pixelformat = ov5640_data.pix.pixelformat; -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num -+ * @s: pointer to standard V4L2 device structure -+ * -+ * Initialise the device when slave attaches to the master. -+ */ -+static int ioctl_dev_init(struct v4l2_int_device *s) -+{ -+ struct sensor_data *sensor = s->priv; -+ u32 tgt_xclk; /* target xclk */ -+ u32 tgt_fps; /* target frames per secound */ -+ enum ov5640_frame_rate frame_rate; -+ int ret; -+ -+ ov5640_data.on = true; -+ -+ /* mclk */ -+ tgt_xclk = ov5640_data.mclk; -+ tgt_xclk = min(tgt_xclk, (u32)OV5640_XCLK_MAX); -+ tgt_xclk = max(tgt_xclk, (u32)OV5640_XCLK_MIN); -+ ov5640_data.mclk = tgt_xclk; -+ -+ pr_debug(" Setting mclk to %d MHz\n", tgt_xclk / 1000000); -+ clk_set_rate(ov5640_data.sensor_clk, ov5640_data.mclk); -+ -+ /* Default camera frame rate is set in probe */ -+ tgt_fps = sensor->streamcap.timeperframe.denominator / -+ sensor->streamcap.timeperframe.numerator; -+ -+ if (tgt_fps == 15) -+ frame_rate = ov5640_15_fps; -+ else if (tgt_fps == 30) -+ frame_rate = ov5640_30_fps; -+ else -+ return -EINVAL; /* Only support 15fps or 30fps now. */ -+ -+ ret = ov5640_init_mode(); -+ return ret; -+} -+ -+/*! -+ * ioctl_dev_exit - V4L2 sensor interface handler for vidioc_int_dev_exit_num -+ * @s: pointer to standard V4L2 device structure -+ * -+ * Delinitialise the device when slave detaches to the master. -+ */ -+static int ioctl_dev_exit(struct v4l2_int_device *s) -+{ -+ return 0; -+} -+ -+/*! -+ * This structure defines all the ioctls for this module and links them to the -+ * enumeration. -+ */ -+static struct v4l2_int_ioctl_desc ov5640_ioctl_desc[] = { -+ { vidioc_int_dev_init_num, -+ (v4l2_int_ioctl_func *)ioctl_dev_init }, -+ { vidioc_int_dev_exit_num, -+ ioctl_dev_exit}, -+ { vidioc_int_s_power_num, -+ (v4l2_int_ioctl_func *)ioctl_s_power }, -+ { vidioc_int_g_ifparm_num, -+ (v4l2_int_ioctl_func *)ioctl_g_ifparm }, -+ { vidioc_int_init_num, -+ (v4l2_int_ioctl_func *)ioctl_init }, -+ { vidioc_int_enum_fmt_cap_num, -+ (v4l2_int_ioctl_func *)ioctl_enum_fmt_cap }, -+ { vidioc_int_g_fmt_cap_num, -+ (v4l2_int_ioctl_func *)ioctl_g_fmt_cap }, -+ { vidioc_int_g_parm_num, -+ (v4l2_int_ioctl_func *)ioctl_g_parm }, -+ { vidioc_int_s_parm_num, -+ (v4l2_int_ioctl_func *)ioctl_s_parm }, -+ { vidioc_int_g_ctrl_num, -+ (v4l2_int_ioctl_func *)ioctl_g_ctrl }, -+ { vidioc_int_s_ctrl_num, -+ (v4l2_int_ioctl_func *)ioctl_s_ctrl }, -+ { vidioc_int_enum_framesizes_num, -+ (v4l2_int_ioctl_func *)ioctl_enum_framesizes }, -+ { vidioc_int_enum_frameintervals_num, -+ (v4l2_int_ioctl_func *)ioctl_enum_frameintervals }, -+ { vidioc_int_g_chip_ident_num, -+ (v4l2_int_ioctl_func *)ioctl_g_chip_ident }, -+}; -+ -+static struct v4l2_int_slave ov5640_slave = { -+ .ioctls = ov5640_ioctl_desc, -+ .num_ioctls = ARRAY_SIZE(ov5640_ioctl_desc), -+}; -+ -+static struct v4l2_int_device ov5640_int_device = { -+ .module = THIS_MODULE, -+ .name = "ov5640", -+ .type = v4l2_int_type_slave, -+ .u = { -+ .slave = &ov5640_slave, -+ }, -+}; -+ -+/*! -+ * ov5640 I2C probe function -+ * -+ * @param adapter struct i2c_adapter * -+ * @return Error code indicating success or failure -+ */ -+static int ov5640_probe(struct i2c_client *client, -+ const struct i2c_device_id *id) -+{ -+ struct pinctrl *pinctrl; -+ struct device *dev = &client->dev; -+ int retval; -+ u8 chip_id_high, chip_id_low; -+ struct sensor_data *sensor = &ov5640_data; -+ -+ /* ov5640 pinctrl */ -+ pinctrl = devm_pinctrl_get_select_default(dev); -+ if (IS_ERR(pinctrl)) { -+ dev_err(dev, "setup pinctrl failed\n"); -+ return PTR_ERR(pinctrl); -+ } -+ -+ /* request power down pin */ -+ pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0); -+ if (!gpio_is_valid(pwn_gpio)) { -+ dev_err(dev, "no sensor pwdn pin available\n"); -+ return -ENODEV; -+ } -+ retval = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH, -+ "ov5640_pwdn"); -+ if (retval < 0) -+ return retval; -+ -+ /* request reset pin */ -+ rst_gpio = of_get_named_gpio(dev->of_node, "rst-gpios", 0); -+ if (!gpio_is_valid(rst_gpio)) { -+ dev_err(dev, "no sensor reset pin available\n"); -+ return -EINVAL; -+ } -+ retval = devm_gpio_request_one(dev, rst_gpio, GPIOF_OUT_INIT_HIGH, -+ "ov5640_reset"); -+ if (retval < 0) -+ return retval; -+ -+ /* Set initial values for the sensor struct. */ -+ memset(&ov5640_data, 0, sizeof(ov5640_data)); -+ ov5640_data.sensor_clk = devm_clk_get(dev, "csi_mclk"); -+ if (IS_ERR(ov5640_data.sensor_clk)) { -+ dev_err(dev, "get mclk failed\n"); -+ return PTR_ERR(ov5640_data.sensor_clk); -+ } -+ -+ retval = of_property_read_u32(dev->of_node, "mclk", -+ &ov5640_data.mclk); -+ if (retval) { -+ dev_err(dev, "mclk frequency is invalid\n"); -+ return retval; -+ } -+ -+ retval = of_property_read_u32(dev->of_node, "mclk_source", -+ (u32 *) &(ov5640_data.mclk_source)); -+ if (retval) { -+ dev_err(dev, "mclk_source invalid\n"); -+ return retval; -+ } -+ -+ retval = of_property_read_u32(dev->of_node, "ipu_id", -+ &sensor->ipu_id); -+ if (retval) { -+ dev_err(dev, "ipu_id missing or invalid\n"); -+ return retval; -+ } -+ -+ retval = of_property_read_u32(dev->of_node, "csi_id", -+ &(ov5640_data.csi)); -+ if (retval) { -+ dev_err(dev, "csi_id invalid\n"); -+ return retval; -+ } -+ -+ clk_prepare_enable(ov5640_data.sensor_clk); -+ -+ ov5640_data.io_init = ov5640_reset; -+ ov5640_data.i2c_client = client; -+ ov5640_data.pix.pixelformat = V4L2_PIX_FMT_YUYV; -+ ov5640_data.pix.width = 640; -+ ov5640_data.pix.height = 480; -+ ov5640_data.streamcap.capability = V4L2_MODE_HIGHQUALITY | -+ V4L2_CAP_TIMEPERFRAME; -+ ov5640_data.streamcap.capturemode = 0; -+ ov5640_data.streamcap.timeperframe.denominator = DEFAULT_FPS; -+ ov5640_data.streamcap.timeperframe.numerator = 1; -+ -+ ov5640_regulator_enable(&client->dev); -+ -+ ov5640_reset(); -+ -+ ov5640_power_down(0); -+ -+ retval = ov5640_read_reg(OV5640_CHIP_ID_HIGH_BYTE, &chip_id_high); -+ if (retval < 0 || chip_id_high != 0x56) { -+ clk_disable_unprepare(ov5640_data.sensor_clk); -+ pr_warning("camera ov5640 is not found\n"); -+ return -ENODEV; -+ } -+ retval = ov5640_read_reg(OV5640_CHIP_ID_LOW_BYTE, &chip_id_low); -+ if (retval < 0 || chip_id_low != 0x40) { -+ clk_disable_unprepare(ov5640_data.sensor_clk); -+ pr_warning("camera ov5640 is not found\n"); -+ return -ENODEV; -+ } -+ -+ ov5640_power_down(1); -+ -+ clk_disable_unprepare(ov5640_data.sensor_clk); -+ -+ ov5640_int_device.priv = &ov5640_data; -+ retval = v4l2_int_device_register(&ov5640_int_device); -+ -+ pr_info("camera ov5640 is found\n"); -+ return retval; -+} -+ -+/*! -+ * ov5640 I2C detach function -+ * -+ * @param client struct i2c_client * -+ * @return Error code indicating success or failure -+ */ -+static int ov5640_remove(struct i2c_client *client) -+{ -+ v4l2_int_device_unregister(&ov5640_int_device); -+ -+ if (analog_regulator) -+ regulator_disable(analog_regulator); -+ -+ if (core_regulator) -+ regulator_disable(core_regulator); -+ -+ if (io_regulator) -+ regulator_disable(io_regulator); -+ -+ return 0; -+} -+ -+module_i2c_driver(ov5640_i2c_driver); -+ -+MODULE_AUTHOR("Freescale Semiconductor, Inc."); -+MODULE_DESCRIPTION("OV5640 Camera Driver"); -+MODULE_LICENSE("GPL"); -+MODULE_VERSION("1.0"); -+MODULE_ALIAS("CSI"); -diff -Nur linux-4.1.13.orig/drivers/media/platform/mxc/capture/ov5640_mipi.c linux-4.1.13/drivers/media/platform/mxc/capture/ov5640_mipi.c ---- linux-4.1.13.orig/drivers/media/platform/mxc/capture/ov5640_mipi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/media/platform/mxc/capture/ov5640_mipi.c 2015-11-30 17:56:13.604136128 +0100 -@@ -0,0 +1,2193 @@ -+/* -+ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved. -+ */ -+ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "mxc_v4l2_capture.h" -+ -+#define OV5640_VOLTAGE_ANALOG 2800000 -+#define OV5640_VOLTAGE_DIGITAL_CORE 1500000 -+#define OV5640_VOLTAGE_DIGITAL_IO 1800000 -+ -+#define MIN_FPS 15 -+#define MAX_FPS 30 -+#define DEFAULT_FPS 30 -+ -+#define OV5640_XCLK_MIN 6000000 -+#define OV5640_XCLK_MAX 24000000 -+ -+#define OV5640_CHIP_ID_HIGH_BYTE 0x300A -+#define OV5640_CHIP_ID_LOW_BYTE 0x300B -+ -+enum ov5640_mode { -+ ov5640_mode_MIN = 0, -+ ov5640_mode_VGA_640_480 = 0, -+ ov5640_mode_QVGA_320_240 = 1, -+ ov5640_mode_NTSC_720_480 = 2, -+ ov5640_mode_PAL_720_576 = 3, -+ ov5640_mode_720P_1280_720 = 4, -+ ov5640_mode_1080P_1920_1080 = 5, -+ ov5640_mode_QSXGA_2592_1944 = 6, -+ ov5640_mode_QCIF_176_144 = 7, -+ ov5640_mode_XGA_1024_768 = 8, -+ ov5640_mode_MAX = 8, -+ ov5640_mode_INIT = 0xff, /*only for sensor init*/ -+}; -+ -+enum ov5640_frame_rate { -+ ov5640_15_fps, -+ ov5640_30_fps -+}; -+ -+/* image size under 1280 * 960 are SUBSAMPLING -+ * image size upper 1280 * 960 are SCALING -+ */ -+enum ov5640_downsize_mode { -+ SUBSAMPLING, -+ SCALING, -+}; -+ -+struct reg_value { -+ u16 u16RegAddr; -+ u8 u8Val; -+ u8 u8Mask; -+ u32 u32Delay_ms; -+}; -+ -+struct ov5640_mode_info { -+ enum ov5640_mode mode; -+ enum ov5640_downsize_mode dn_mode; -+ u32 width; -+ u32 height; -+ struct reg_value *init_data_ptr; -+ u32 init_data_size; -+}; -+ -+/*! -+ * Maintains the information on the current state of the sesor. -+ */ -+static struct sensor_data ov5640_data; -+static int pwn_gpio, rst_gpio; -+ -+static struct reg_value ov5640_init_setting_30fps_VGA[] = { -+ -+ {0x3103, 0x11, 0, 0}, {0x3008, 0x82, 0, 5}, {0x3008, 0x42, 0, 0}, -+ {0x3103, 0x03, 0, 0}, {0x3017, 0x00, 0, 0}, {0x3018, 0x00, 0, 0}, -+ {0x3034, 0x18, 0, 0}, {0x3035, 0x14, 0, 0}, {0x3036, 0x38, 0, 0}, -+ {0x3037, 0x13, 0, 0}, {0x3108, 0x01, 0, 0}, {0x3630, 0x36, 0, 0}, -+ {0x3631, 0x0e, 0, 0}, {0x3632, 0xe2, 0, 0}, {0x3633, 0x12, 0, 0}, -+ {0x3621, 0xe0, 0, 0}, {0x3704, 0xa0, 0, 0}, {0x3703, 0x5a, 0, 0}, -+ {0x3715, 0x78, 0, 0}, {0x3717, 0x01, 0, 0}, {0x370b, 0x60, 0, 0}, -+ {0x3705, 0x1a, 0, 0}, {0x3905, 0x02, 0, 0}, {0x3906, 0x10, 0, 0}, -+ {0x3901, 0x0a, 0, 0}, {0x3731, 0x12, 0, 0}, {0x3600, 0x08, 0, 0}, -+ {0x3601, 0x33, 0, 0}, {0x302d, 0x60, 0, 0}, {0x3620, 0x52, 0, 0}, -+ {0x371b, 0x20, 0, 0}, {0x471c, 0x50, 0, 0}, {0x3a13, 0x43, 0, 0}, -+ {0x3a18, 0x00, 0, 0}, {0x3a19, 0xf8, 0, 0}, {0x3635, 0x13, 0, 0}, -+ {0x3636, 0x03, 0, 0}, {0x3634, 0x40, 0, 0}, {0x3622, 0x01, 0, 0}, -+ {0x3c01, 0xa4, 0, 0}, {0x3c04, 0x28, 0, 0}, {0x3c05, 0x98, 0, 0}, -+ {0x3c06, 0x00, 0, 0}, {0x3c07, 0x08, 0, 0}, {0x3c08, 0x00, 0, 0}, -+ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, -+ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, -+ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, -+ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, -+ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, -+ {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, -+ {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, -+ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0}, -+ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, -+ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, -+ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, -+ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, -+ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, -+ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, -+ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x3000, 0x00, 0, 0}, -+ {0x3002, 0x1c, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3006, 0xc3, 0, 0}, -+ {0x300e, 0x45, 0, 0}, {0x302e, 0x08, 0, 0}, {0x4300, 0x3f, 0, 0}, -+ {0x501f, 0x00, 0, 0}, {0x4713, 0x03, 0, 0}, {0x4407, 0x04, 0, 0}, -+ {0x440e, 0x00, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, -+ {0x4837, 0x0a, 0, 0}, {0x4800, 0x04, 0, 0}, {0x3824, 0x02, 0, 0}, -+ {0x5000, 0xa7, 0, 0}, {0x5001, 0xa3, 0, 0}, {0x5180, 0xff, 0, 0}, -+ {0x5181, 0xf2, 0, 0}, {0x5182, 0x00, 0, 0}, {0x5183, 0x14, 0, 0}, -+ {0x5184, 0x25, 0, 0}, {0x5185, 0x24, 0, 0}, {0x5186, 0x09, 0, 0}, -+ {0x5187, 0x09, 0, 0}, {0x5188, 0x09, 0, 0}, {0x5189, 0x88, 0, 0}, -+ {0x518a, 0x54, 0, 0}, {0x518b, 0xee, 0, 0}, {0x518c, 0xb2, 0, 0}, -+ {0x518d, 0x50, 0, 0}, {0x518e, 0x34, 0, 0}, {0x518f, 0x6b, 0, 0}, -+ {0x5190, 0x46, 0, 0}, {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, -+ {0x5193, 0x70, 0, 0}, {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, -+ {0x5196, 0x03, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, -+ {0x5199, 0x6c, 0, 0}, {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, -+ {0x519c, 0x09, 0, 0}, {0x519d, 0x2b, 0, 0}, {0x519e, 0x38, 0, 0}, -+ {0x5381, 0x1e, 0, 0}, {0x5382, 0x5b, 0, 0}, {0x5383, 0x08, 0, 0}, -+ {0x5384, 0x0a, 0, 0}, {0x5385, 0x7e, 0, 0}, {0x5386, 0x88, 0, 0}, -+ {0x5387, 0x7c, 0, 0}, {0x5388, 0x6c, 0, 0}, {0x5389, 0x10, 0, 0}, -+ {0x538a, 0x01, 0, 0}, {0x538b, 0x98, 0, 0}, {0x5300, 0x08, 0, 0}, -+ {0x5301, 0x30, 0, 0}, {0x5302, 0x10, 0, 0}, {0x5303, 0x00, 0, 0}, -+ {0x5304, 0x08, 0, 0}, {0x5305, 0x30, 0, 0}, {0x5306, 0x08, 0, 0}, -+ {0x5307, 0x16, 0, 0}, {0x5309, 0x08, 0, 0}, {0x530a, 0x30, 0, 0}, -+ {0x530b, 0x04, 0, 0}, {0x530c, 0x06, 0, 0}, {0x5480, 0x01, 0, 0}, -+ {0x5481, 0x08, 0, 0}, {0x5482, 0x14, 0, 0}, {0x5483, 0x28, 0, 0}, -+ {0x5484, 0x51, 0, 0}, {0x5485, 0x65, 0, 0}, {0x5486, 0x71, 0, 0}, -+ {0x5487, 0x7d, 0, 0}, {0x5488, 0x87, 0, 0}, {0x5489, 0x91, 0, 0}, -+ {0x548a, 0x9a, 0, 0}, {0x548b, 0xaa, 0, 0}, {0x548c, 0xb8, 0, 0}, -+ {0x548d, 0xcd, 0, 0}, {0x548e, 0xdd, 0, 0}, {0x548f, 0xea, 0, 0}, -+ {0x5490, 0x1d, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5583, 0x40, 0, 0}, -+ {0x5584, 0x10, 0, 0}, {0x5589, 0x10, 0, 0}, {0x558a, 0x00, 0, 0}, -+ {0x558b, 0xf8, 0, 0}, {0x5800, 0x23, 0, 0}, {0x5801, 0x14, 0, 0}, -+ {0x5802, 0x0f, 0, 0}, {0x5803, 0x0f, 0, 0}, {0x5804, 0x12, 0, 0}, -+ {0x5805, 0x26, 0, 0}, {0x5806, 0x0c, 0, 0}, {0x5807, 0x08, 0, 0}, -+ {0x5808, 0x05, 0, 0}, {0x5809, 0x05, 0, 0}, {0x580a, 0x08, 0, 0}, -+ {0x580b, 0x0d, 0, 0}, {0x580c, 0x08, 0, 0}, {0x580d, 0x03, 0, 0}, -+ {0x580e, 0x00, 0, 0}, {0x580f, 0x00, 0, 0}, {0x5810, 0x03, 0, 0}, -+ {0x5811, 0x09, 0, 0}, {0x5812, 0x07, 0, 0}, {0x5813, 0x03, 0, 0}, -+ {0x5814, 0x00, 0, 0}, {0x5815, 0x01, 0, 0}, {0x5816, 0x03, 0, 0}, -+ {0x5817, 0x08, 0, 0}, {0x5818, 0x0d, 0, 0}, {0x5819, 0x08, 0, 0}, -+ {0x581a, 0x05, 0, 0}, {0x581b, 0x06, 0, 0}, {0x581c, 0x08, 0, 0}, -+ {0x581d, 0x0e, 0, 0}, {0x581e, 0x29, 0, 0}, {0x581f, 0x17, 0, 0}, -+ {0x5820, 0x11, 0, 0}, {0x5821, 0x11, 0, 0}, {0x5822, 0x15, 0, 0}, -+ {0x5823, 0x28, 0, 0}, {0x5824, 0x46, 0, 0}, {0x5825, 0x26, 0, 0}, -+ {0x5826, 0x08, 0, 0}, {0x5827, 0x26, 0, 0}, {0x5828, 0x64, 0, 0}, -+ {0x5829, 0x26, 0, 0}, {0x582a, 0x24, 0, 0}, {0x582b, 0x22, 0, 0}, -+ {0x582c, 0x24, 0, 0}, {0x582d, 0x24, 0, 0}, {0x582e, 0x06, 0, 0}, -+ {0x582f, 0x22, 0, 0}, {0x5830, 0x40, 0, 0}, {0x5831, 0x42, 0, 0}, -+ {0x5832, 0x24, 0, 0}, {0x5833, 0x26, 0, 0}, {0x5834, 0x24, 0, 0}, -+ {0x5835, 0x22, 0, 0}, {0x5836, 0x22, 0, 0}, {0x5837, 0x26, 0, 0}, -+ {0x5838, 0x44, 0, 0}, {0x5839, 0x24, 0, 0}, {0x583a, 0x26, 0, 0}, -+ {0x583b, 0x28, 0, 0}, {0x583c, 0x42, 0, 0}, {0x583d, 0xce, 0, 0}, -+ {0x5025, 0x00, 0, 0}, {0x3a0f, 0x30, 0, 0}, {0x3a10, 0x28, 0, 0}, -+ {0x3a1b, 0x30, 0, 0}, {0x3a1e, 0x26, 0, 0}, {0x3a11, 0x60, 0, 0}, -+ {0x3a1f, 0x14, 0, 0}, {0x3008, 0x02, 0, 0}, {0x3c00, 0x04, 0, 300}, -+}; -+ -+static struct reg_value ov5640_setting_30fps_VGA_640_480[] = { -+ -+ {0x3035, 0x14, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, -+ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, -+ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, -+ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, -+ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, -+ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, -+ {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, -+ {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, -+ {0x380e, 0x04, 0, 0}, {0x380f, 0x38, 0, 0}, {0x3810, 0x00, 0, 0}, -+ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, -+ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, -+ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, -+ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x0e, 0, 0}, -+ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, -+ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, -+ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, -+ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, -+ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, {0x3503, 0x00, 0, 0}, -+}; -+ -+static struct reg_value ov5640_setting_15fps_VGA_640_480[] = { -+ {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, -+ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, -+ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, -+ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, -+ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, -+ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, -+ {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, -+ {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, -+ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0}, -+ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, -+ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, -+ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, -+ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, -+ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, -+ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, -+ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, -+ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, -+ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, -+}; -+ -+static struct reg_value ov5640_setting_30fps_XGA_1024_768[] = { -+ -+ {0x3035, 0x14, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, -+ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, -+ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, -+ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, -+ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, -+ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, -+ {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, -+ {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, -+ {0x380e, 0x04, 0, 0}, {0x380f, 0x38, 0, 0}, {0x3810, 0x00, 0, 0}, -+ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, -+ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, -+ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, -+ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x0e, 0, 0}, -+ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, -+ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, -+ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, -+ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, -+ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, {0x3503, 0x00, 0, 0}, -+ {0x3808, 0x04, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x03, 0, 0}, -+ {0x380b, 0x00, 0, 0}, {0x3035, 0x12, 0, 0}, -+}; -+ -+static struct reg_value ov5640_setting_15fps_XGA_1024_768[] = { -+ {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, -+ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, -+ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, -+ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, -+ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, -+ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, -+ {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, -+ {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, -+ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0}, -+ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, -+ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, -+ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, -+ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, -+ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, -+ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, -+ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, -+ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, -+ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, {0x3808, 0x04, 0, 0}, -+ {0x3809, 0x00, 0, 0}, {0x380a, 0x03, 0, 0}, {0x380b, 0x00, 0, 0}, -+}; -+ -+static struct reg_value ov5640_setting_30fps_QVGA_320_240[] = { -+ {0x3035, 0x14, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, -+ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, -+ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, -+ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, -+ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, -+ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, -+ {0x3808, 0x01, 0, 0}, {0x3809, 0x40, 0, 0}, {0x380a, 0x00, 0, 0}, -+ {0x380b, 0xf0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, -+ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0}, -+ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, -+ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, -+ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, -+ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, -+ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, -+ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, -+ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, -+ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, -+ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, -+}; -+ -+static struct reg_value ov5640_setting_15fps_QVGA_320_240[] = { -+ {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, -+ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, -+ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, -+ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, -+ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, -+ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, -+ {0x3808, 0x01, 0, 0}, {0x3809, 0x40, 0, 0}, {0x380a, 0x00, 0, 0}, -+ {0x380b, 0xf0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, -+ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0}, -+ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, -+ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, -+ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, -+ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, -+ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, -+ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, -+ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, -+ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, -+ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, -+}; -+ -+static struct reg_value ov5640_setting_30fps_QCIF_176_144[] = { -+ {0x3035, 0x14, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, -+ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, -+ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, -+ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, -+ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, -+ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, -+ {0x3808, 0x00, 0, 0}, {0x3809, 0xb0, 0, 0}, {0x380a, 0x00, 0, 0}, -+ {0x380b, 0x90, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, -+ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0}, -+ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, -+ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, -+ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, -+ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, -+ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, -+ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, -+ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, -+ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, -+ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, -+}; -+static struct reg_value ov5640_setting_15fps_QCIF_176_144[] = { -+ {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, -+ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, -+ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, -+ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, -+ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, -+ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, -+ {0x3808, 0x00, 0, 0}, {0x3809, 0xb0, 0, 0}, {0x380a, 0x00, 0, 0}, -+ {0x380b, 0x90, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, -+ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0}, -+ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, -+ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, -+ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, -+ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, -+ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, -+ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, -+ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, -+ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, -+ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, -+}; -+ -+static struct reg_value ov5640_setting_30fps_NTSC_720_480[] = { -+ {0x3035, 0x12, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, -+ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, -+ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, -+ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, -+ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, -+ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, -+ {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0}, {0x380a, 0x01, 0, 0}, -+ {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, -+ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0}, -+ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x3c, 0, 0}, -+ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, -+ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, -+ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, -+ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, -+ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, -+ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, -+ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, -+ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, -+}; -+ -+static struct reg_value ov5640_setting_15fps_NTSC_720_480[] = { -+ {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, -+ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, -+ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, -+ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, -+ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, -+ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, -+ {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0}, {0x380a, 0x01, 0, 0}, -+ {0x380b, 0xe0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, -+ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0}, -+ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x3c, 0, 0}, -+ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, -+ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, -+ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, -+ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, -+ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, -+ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, -+ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, -+ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, -+}; -+ -+static struct reg_value ov5640_setting_30fps_PAL_720_576[] = { -+ {0x3035, 0x12, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, -+ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, -+ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, -+ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, -+ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, -+ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, -+ {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0}, {0x380a, 0x02, 0, 0}, -+ {0x380b, 0x40, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, -+ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0}, -+ {0x3811, 0x38, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, -+ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, -+ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, -+ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, -+ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, -+ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, -+ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, -+ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, -+ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, -+}; -+ -+static struct reg_value ov5640_setting_15fps_PAL_720_576[] = { -+ {0x3035, 0x22, 0, 0}, {0x3036, 0x38, 0, 0}, {0x3c07, 0x08, 0, 0}, -+ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, -+ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, -+ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, -+ {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0}, -+ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0}, -+ {0x3808, 0x02, 0, 0}, {0x3809, 0xd0, 0, 0}, {0x380a, 0x02, 0, 0}, -+ {0x380b, 0x40, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x68, 0, 0}, -+ {0x380e, 0x03, 0, 0}, {0x380f, 0xd8, 0, 0}, {0x3810, 0x00, 0, 0}, -+ {0x3811, 0x38, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0}, -+ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, -+ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0}, -+ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, -+ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, -+ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, -+ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x03, 0, 0}, -+ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, -+ {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0}, -+}; -+ -+static struct reg_value ov5640_setting_30fps_720P_1280_720[] = { -+ {0x3008, 0x42, 0, 0}, -+ {0x3035, 0x21, 0, 0}, {0x3036, 0x54, 0, 0}, {0x3c07, 0x07, 0, 0}, -+ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, -+ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, -+ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, -+ {0x3802, 0x00, 0, 0}, {0x3803, 0xfa, 0, 0}, {0x3804, 0x0a, 0, 0}, -+ {0x3805, 0x3f, 0, 0}, {0x3806, 0x06, 0, 0}, {0x3807, 0xa9, 0, 0}, -+ {0x3808, 0x05, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x02, 0, 0}, -+ {0x380b, 0xd0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x64, 0, 0}, -+ {0x380e, 0x02, 0, 0}, {0x380f, 0xe4, 0, 0}, {0x3810, 0x00, 0, 0}, -+ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0}, -+ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, -+ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x02, 0, 0}, -+ {0x3a03, 0xe4, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0xbc, 0, 0}, -+ {0x3a0a, 0x01, 0, 0}, {0x3a0b, 0x72, 0, 0}, {0x3a0e, 0x01, 0, 0}, -+ {0x3a0d, 0x02, 0, 0}, {0x3a14, 0x02, 0, 0}, {0x3a15, 0xe4, 0, 0}, -+ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x02, 0, 0}, -+ {0x4407, 0x04, 0, 0}, {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0}, -+ {0x3824, 0x04, 0, 0}, {0x5001, 0x83, 0, 0}, {0x4005, 0x1a, 0, 0}, -+ {0x3008, 0x02, 0, 0}, {0x3503, 0, 0, 0}, -+}; -+ -+static struct reg_value ov5640_setting_15fps_720P_1280_720[] = { -+ {0x3035, 0x41, 0, 0}, {0x3036, 0x54, 0, 0}, {0x3c07, 0x07, 0, 0}, -+ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, -+ {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0}, -+ {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, -+ {0x3802, 0x00, 0, 0}, {0x3803, 0xfa, 0, 0}, {0x3804, 0x0a, 0, 0}, -+ {0x3805, 0x3f, 0, 0}, {0x3806, 0x06, 0, 0}, {0x3807, 0xa9, 0, 0}, -+ {0x3808, 0x05, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x02, 0, 0}, -+ {0x380b, 0xd0, 0, 0}, {0x380c, 0x07, 0, 0}, {0x380d, 0x64, 0, 0}, -+ {0x380e, 0x02, 0, 0}, {0x380f, 0xe4, 0, 0}, {0x3810, 0x00, 0, 0}, -+ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0}, -+ {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0}, -+ {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x02, 0, 0}, -+ {0x3a03, 0xe4, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0xbc, 0, 0}, -+ {0x3a0a, 0x01, 0, 0}, {0x3a0b, 0x72, 0, 0}, {0x3a0e, 0x01, 0, 0}, -+ {0x3a0d, 0x02, 0, 0}, {0x3a14, 0x02, 0, 0}, {0x3a15, 0xe4, 0, 0}, -+ {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x4713, 0x02, 0, 0}, -+ {0x4407, 0x04, 0, 0}, {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0}, -+ {0x3824, 0x04, 0, 0}, {0x5001, 0x83, 0, 0}, -+}; -+ -+static struct reg_value ov5640_setting_30fps_1080P_1920_1080[] = { -+ {0x3008, 0x42, 0, 0}, -+ {0x3035, 0x21, 0, 0}, {0x3036, 0x54, 0, 0}, {0x3c07, 0x08, 0, 0}, -+ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, -+ {0x3820, 0x40, 0, 0}, {0x3821, 0x06, 0, 0}, {0x3814, 0x11, 0, 0}, -+ {0x3815, 0x11, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, -+ {0x3802, 0x00, 0, 0}, {0x3803, 0x00, 0, 0}, {0x3804, 0x0a, 0, 0}, -+ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9f, 0, 0}, -+ {0x3808, 0x0a, 0, 0}, {0x3809, 0x20, 0, 0}, {0x380a, 0x07, 0, 0}, -+ {0x380b, 0x98, 0, 0}, {0x380c, 0x0b, 0, 0}, {0x380d, 0x1c, 0, 0}, -+ {0x380e, 0x07, 0, 0}, {0x380f, 0xb0, 0, 0}, {0x3810, 0x00, 0, 0}, -+ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0}, -+ {0x3618, 0x04, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x21, 0, 0}, -+ {0x3709, 0x12, 0, 0}, {0x370c, 0x00, 0, 0}, {0x3a02, 0x03, 0, 0}, -+ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, -+ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, -+ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, -+ {0x4001, 0x02, 0, 0}, {0x4004, 0x06, 0, 0}, {0x4713, 0x03, 0, 0}, -+ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, -+ {0x3824, 0x02, 0, 0}, {0x5001, 0x83, 0, 0}, {0x3035, 0x11, 0, 0}, -+ {0x3036, 0x54, 0, 0}, {0x3c07, 0x07, 0, 0}, {0x3c08, 0x00, 0, 0}, -+ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, -+ {0x3800, 0x01, 0, 0}, {0x3801, 0x50, 0, 0}, {0x3802, 0x01, 0, 0}, -+ {0x3803, 0xb2, 0, 0}, {0x3804, 0x08, 0, 0}, {0x3805, 0xef, 0, 0}, -+ {0x3806, 0x05, 0, 0}, {0x3807, 0xf1, 0, 0}, {0x3808, 0x07, 0, 0}, -+ {0x3809, 0x80, 0, 0}, {0x380a, 0x04, 0, 0}, {0x380b, 0x38, 0, 0}, -+ {0x380c, 0x09, 0, 0}, {0x380d, 0xc4, 0, 0}, {0x380e, 0x04, 0, 0}, -+ {0x380f, 0x60, 0, 0}, {0x3612, 0x2b, 0, 0}, {0x3708, 0x64, 0, 0}, -+ {0x3a02, 0x04, 0, 0}, {0x3a03, 0x60, 0, 0}, {0x3a08, 0x01, 0, 0}, -+ {0x3a09, 0x50, 0, 0}, {0x3a0a, 0x01, 0, 0}, {0x3a0b, 0x18, 0, 0}, -+ {0x3a0e, 0x03, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x04, 0, 0}, -+ {0x3a15, 0x60, 0, 0}, {0x4713, 0x02, 0, 0}, {0x4407, 0x04, 0, 0}, -+ {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3824, 0x04, 0, 0}, -+ {0x4005, 0x1a, 0, 0}, {0x3008, 0x02, 0, 0}, -+ {0x3503, 0, 0, 0}, -+}; -+ -+static struct reg_value ov5640_setting_15fps_1080P_1920_1080[] = { -+ {0x3008, 0x42, 0, 0}, -+ {0x3035, 0x21, 0, 0}, {0x3036, 0x54, 0, 0}, {0x3c07, 0x08, 0, 0}, -+ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, -+ {0x3820, 0x40, 0, 0}, {0x3821, 0x06, 0, 0}, {0x3814, 0x11, 0, 0}, -+ {0x3815, 0x11, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, -+ {0x3802, 0x00, 0, 0}, {0x3803, 0x00, 0, 0}, {0x3804, 0x0a, 0, 0}, -+ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9f, 0, 0}, -+ {0x3808, 0x0a, 0, 0}, {0x3809, 0x20, 0, 0}, {0x380a, 0x07, 0, 0}, -+ {0x380b, 0x98, 0, 0}, {0x380c, 0x0b, 0, 0}, {0x380d, 0x1c, 0, 0}, -+ {0x380e, 0x07, 0, 0}, {0x380f, 0xb0, 0, 0}, {0x3810, 0x00, 0, 0}, -+ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0}, -+ {0x3618, 0x04, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x21, 0, 0}, -+ {0x3709, 0x12, 0, 0}, {0x370c, 0x00, 0, 0}, {0x3a02, 0x03, 0, 0}, -+ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, -+ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, -+ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, -+ {0x4001, 0x02, 0, 0}, {0x4004, 0x06, 0, 0}, {0x4713, 0x03, 0, 0}, -+ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, -+ {0x3824, 0x02, 0, 0}, {0x5001, 0x83, 0, 0}, {0x3035, 0x21, 0, 0}, -+ {0x3036, 0x54, 0, 1}, {0x3c07, 0x07, 0, 0}, {0x3c08, 0x00, 0, 0}, -+ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, -+ {0x3800, 0x01, 0, 0}, {0x3801, 0x50, 0, 0}, {0x3802, 0x01, 0, 0}, -+ {0x3803, 0xb2, 0, 0}, {0x3804, 0x08, 0, 0}, {0x3805, 0xef, 0, 0}, -+ {0x3806, 0x05, 0, 0}, {0x3807, 0xf1, 0, 0}, {0x3808, 0x07, 0, 0}, -+ {0x3809, 0x80, 0, 0}, {0x380a, 0x04, 0, 0}, {0x380b, 0x38, 0, 0}, -+ {0x380c, 0x09, 0, 0}, {0x380d, 0xc4, 0, 0}, {0x380e, 0x04, 0, 0}, -+ {0x380f, 0x60, 0, 0}, {0x3612, 0x2b, 0, 0}, {0x3708, 0x64, 0, 0}, -+ {0x3a02, 0x04, 0, 0}, {0x3a03, 0x60, 0, 0}, {0x3a08, 0x01, 0, 0}, -+ {0x3a09, 0x50, 0, 0}, {0x3a0a, 0x01, 0, 0}, {0x3a0b, 0x18, 0, 0}, -+ {0x3a0e, 0x03, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x04, 0, 0}, -+ {0x3a15, 0x60, 0, 0}, {0x4713, 0x02, 0, 0}, {0x4407, 0x04, 0, 0}, -+ {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3824, 0x04, 0, 0}, -+ {0x4005, 0x1a, 0, 0}, {0x3008, 0x02, 0, 0}, {0x3503, 0, 0, 0}, -+}; -+ -+static struct reg_value ov5640_setting_15fps_QSXGA_2592_1944[] = { -+ {0x4202, 0x0f, 0, 0}, /* stream off the sensor */ -+ {0x3820, 0x40, 0, 0}, {0x3821, 0x06, 0, 0}, /*disable flip*/ -+ {0x3035, 0x21, 0, 0}, {0x3036, 0x54, 0, 0}, {0x3c07, 0x08, 0, 0}, -+ {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0}, -+ {0x3820, 0x40, 0, 0}, {0x3821, 0x06, 0, 0}, {0x3814, 0x11, 0, 0}, -+ {0x3815, 0x11, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0}, -+ {0x3802, 0x00, 0, 0}, {0x3803, 0x00, 0, 0}, {0x3804, 0x0a, 0, 0}, -+ {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9f, 0, 0}, -+ {0x3808, 0x0a, 0, 0}, {0x3809, 0x20, 0, 0}, {0x380a, 0x07, 0, 0}, -+ {0x380b, 0x98, 0, 0}, {0x380c, 0x0b, 0, 0}, {0x380d, 0x1c, 0, 0}, -+ {0x380e, 0x07, 0, 0}, {0x380f, 0xb0, 0, 0}, {0x3810, 0x00, 0, 0}, -+ {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0}, -+ {0x3618, 0x04, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x21, 0, 0}, -+ {0x3709, 0x12, 0, 0}, {0x370c, 0x00, 0, 0}, {0x3a02, 0x03, 0, 0}, -+ {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0}, -+ {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0}, -+ {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0}, -+ {0x4001, 0x02, 0, 0}, {0x4004, 0x06, 0, 0}, {0x4713, 0x03, 0, 0}, -+ {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0}, -+ {0x3824, 0x02, 0, 0}, {0x5001, 0x83, 0, 70}, -+ {0x4202, 0x00, 0, 0}, /* stream on the sensor */ -+}; -+ -+static struct ov5640_mode_info ov5640_mode_info_data[2][ov5640_mode_MAX + 1] = { -+ { -+ {ov5640_mode_VGA_640_480, SUBSAMPLING, 640, 480, -+ ov5640_setting_15fps_VGA_640_480, -+ ARRAY_SIZE(ov5640_setting_15fps_VGA_640_480)}, -+ {ov5640_mode_QVGA_320_240, SUBSAMPLING, 320, 240, -+ ov5640_setting_15fps_QVGA_320_240, -+ ARRAY_SIZE(ov5640_setting_15fps_QVGA_320_240)}, -+ {ov5640_mode_NTSC_720_480, SUBSAMPLING, 720, 480, -+ ov5640_setting_15fps_NTSC_720_480, -+ ARRAY_SIZE(ov5640_setting_15fps_NTSC_720_480)}, -+ {ov5640_mode_PAL_720_576, SUBSAMPLING, 720, 576, -+ ov5640_setting_15fps_PAL_720_576, -+ ARRAY_SIZE(ov5640_setting_15fps_PAL_720_576)}, -+ {ov5640_mode_720P_1280_720, SUBSAMPLING, 1280, 720, -+ ov5640_setting_15fps_720P_1280_720, -+ ARRAY_SIZE(ov5640_setting_15fps_720P_1280_720)}, -+ {ov5640_mode_1080P_1920_1080, SCALING, 1920, 1080, -+ ov5640_setting_15fps_1080P_1920_1080, -+ ARRAY_SIZE(ov5640_setting_15fps_1080P_1920_1080)}, -+ {ov5640_mode_QSXGA_2592_1944, SCALING, 2592, 1944, -+ ov5640_setting_15fps_QSXGA_2592_1944, -+ ARRAY_SIZE(ov5640_setting_15fps_QSXGA_2592_1944)}, -+ {ov5640_mode_QCIF_176_144, SUBSAMPLING, 176, 144, -+ ov5640_setting_15fps_QCIF_176_144, -+ ARRAY_SIZE(ov5640_setting_15fps_QCIF_176_144)}, -+ {ov5640_mode_XGA_1024_768, SUBSAMPLING, 1024, 768, -+ ov5640_setting_15fps_XGA_1024_768, -+ ARRAY_SIZE(ov5640_setting_15fps_XGA_1024_768)}, -+ }, -+ { -+ {ov5640_mode_VGA_640_480, SUBSAMPLING, 640, 480, -+ ov5640_setting_30fps_VGA_640_480, -+ ARRAY_SIZE(ov5640_setting_30fps_VGA_640_480)}, -+ {ov5640_mode_QVGA_320_240, SUBSAMPLING, 320, 240, -+ ov5640_setting_30fps_QVGA_320_240, -+ ARRAY_SIZE(ov5640_setting_30fps_QVGA_320_240)}, -+ {ov5640_mode_NTSC_720_480, SUBSAMPLING, 720, 480, -+ ov5640_setting_30fps_NTSC_720_480, -+ ARRAY_SIZE(ov5640_setting_30fps_NTSC_720_480)}, -+ {ov5640_mode_PAL_720_576, SUBSAMPLING, 720, 576, -+ ov5640_setting_30fps_PAL_720_576, -+ ARRAY_SIZE(ov5640_setting_30fps_PAL_720_576)}, -+ {ov5640_mode_720P_1280_720, SUBSAMPLING, 1280, 720, -+ ov5640_setting_30fps_720P_1280_720, -+ ARRAY_SIZE(ov5640_setting_30fps_720P_1280_720)}, -+ {ov5640_mode_1080P_1920_1080, SCALING, 1920, 1080, -+ ov5640_setting_30fps_1080P_1920_1080, -+ ARRAY_SIZE(ov5640_setting_30fps_1080P_1920_1080)}, -+ {ov5640_mode_QSXGA_2592_1944, -1, 0, 0, NULL, 0}, -+ {ov5640_mode_QCIF_176_144, SUBSAMPLING, 176, 144, -+ ov5640_setting_30fps_QCIF_176_144, -+ ARRAY_SIZE(ov5640_setting_30fps_QCIF_176_144)}, -+ {ov5640_mode_XGA_1024_768, SUBSAMPLING, 1024, 768, -+ ov5640_setting_30fps_XGA_1024_768, -+ ARRAY_SIZE(ov5640_setting_30fps_XGA_1024_768)}, -+ }, -+}; -+ -+static struct regulator *io_regulator; -+static struct regulator *core_regulator; -+static struct regulator *analog_regulator; -+static struct regulator *gpo_regulator; -+ -+static int ov5640_probe(struct i2c_client *adapter, -+ const struct i2c_device_id *device_id); -+static int ov5640_remove(struct i2c_client *client); -+ -+static s32 ov5640_read_reg(u16 reg, u8 *val); -+static s32 ov5640_write_reg(u16 reg, u8 val); -+ -+static const struct i2c_device_id ov5640_id[] = { -+ {"ov5640_mipi", 0}, -+ {}, -+}; -+ -+MODULE_DEVICE_TABLE(i2c, ov5640_id); -+ -+static struct i2c_driver ov5640_i2c_driver = { -+ .driver = { -+ .owner = THIS_MODULE, -+ .name = "ov5640_mipi", -+ }, -+ .probe = ov5640_probe, -+ .remove = ov5640_remove, -+ .id_table = ov5640_id, -+}; -+ -+static void ov5640_standby(s32 enable) -+{ -+ if (enable) -+ gpio_set_value(pwn_gpio, 1); -+ else -+ gpio_set_value(pwn_gpio, 0); -+ pr_debug("ov5640_mipi_camera_powerdown: powerdown=%x, power_gp=0x%x\n", enable, pwn_gpio); -+ msleep(2); -+} -+ -+static void ov5640_reset(void) -+{ -+ /* camera reset */ -+ gpio_set_value(rst_gpio, 1); -+ -+ /* camera power dowmn */ -+ gpio_set_value(pwn_gpio, 1); -+ msleep(5); -+ -+ gpio_set_value(pwn_gpio, 0); -+ msleep(5); -+ -+ gpio_set_value(rst_gpio, 0); -+ msleep(1); -+ -+ gpio_set_value(rst_gpio, 1); -+ msleep(5); -+ -+ gpio_set_value(pwn_gpio, 1); -+} -+ -+static int ov5640_power_on(struct device *dev) -+{ -+ int ret = 0; -+ -+ io_regulator = devm_regulator_get(dev, "DOVDD"); -+ if (!IS_ERR(io_regulator)) { -+ regulator_set_voltage(io_regulator, -+ OV5640_VOLTAGE_DIGITAL_IO, -+ OV5640_VOLTAGE_DIGITAL_IO); -+ ret = regulator_enable(io_regulator); -+ if (ret) { -+ pr_err("%s:io set voltage error\n", __func__); -+ return ret; -+ } else { -+ dev_dbg(dev, -+ "%s:io set voltage ok\n", __func__); -+ } -+ } else { -+ pr_err("%s: cannot get io voltage error\n", __func__); -+ io_regulator = NULL; -+ } -+ -+ core_regulator = devm_regulator_get(dev, "DVDD"); -+ if (!IS_ERR(core_regulator)) { -+ regulator_set_voltage(core_regulator, -+ OV5640_VOLTAGE_DIGITAL_CORE, -+ OV5640_VOLTAGE_DIGITAL_CORE); -+ ret = regulator_enable(core_regulator); -+ if (ret) { -+ pr_err("%s:core set voltage error\n", __func__); -+ return ret; -+ } else { -+ dev_dbg(dev, -+ "%s:core set voltage ok\n", __func__); -+ } -+ } else { -+ core_regulator = NULL; -+ pr_err("%s: cannot get core voltage error\n", __func__); -+ } -+ -+ analog_regulator = devm_regulator_get(dev, "AVDD"); -+ if (!IS_ERR(analog_regulator)) { -+ regulator_set_voltage(analog_regulator, -+ OV5640_VOLTAGE_ANALOG, -+ OV5640_VOLTAGE_ANALOG); -+ ret = regulator_enable(analog_regulator); -+ if (ret) { -+ pr_err("%s:analog set voltage error\n", -+ __func__); -+ return ret; -+ } else { -+ dev_dbg(dev, -+ "%s:analog set voltage ok\n", __func__); -+ } -+ } else { -+ analog_regulator = NULL; -+ pr_err("%s: cannot get analog voltage error\n", __func__); -+ } -+ -+ return ret; -+} -+ -+static s32 ov5640_write_reg(u16 reg, u8 val) -+{ -+ u8 au8Buf[3] = {0}; -+ -+ au8Buf[0] = reg >> 8; -+ au8Buf[1] = reg & 0xff; -+ au8Buf[2] = val; -+ -+ if (i2c_master_send(ov5640_data.i2c_client, au8Buf, 3) < 0) { -+ pr_err("%s:write reg error:reg=%x,val=%x\n", -+ __func__, reg, val); -+ return -1; -+ } -+ pr_debug("reg=%x,val=%x\n", reg, val); -+ return 0; -+} -+ -+static s32 ov5640_read_reg(u16 reg, u8 *val) -+{ -+ struct sensor_data *sensor = &ov5640_data; -+ struct i2c_client *client = sensor->i2c_client; -+ struct i2c_msg msgs[2]; -+ u8 buf[2]; -+ int ret; -+ -+ buf[0] = reg >> 8; -+ buf[1] = reg & 0xff; -+ msgs[0].addr = client->addr; -+ msgs[0].flags = 0; -+ msgs[0].len = 2; -+ msgs[0].buf = buf; -+ -+ msgs[1].addr = client->addr; -+ msgs[1].flags = I2C_M_RD; -+ msgs[1].len = 1; -+ msgs[1].buf = buf; -+ -+ ret = i2c_transfer(client->adapter, msgs, 2); -+ if (ret < 0) { -+ pr_err("%s(mipi):reg=%x ret=%d\n", __func__, reg, ret); -+ return ret; -+ } -+ *val = buf[0]; -+ pr_debug("%s(mipi):reg=%x,val=%x\n", __func__, reg, buf[0]); -+ return buf[0]; -+} -+ -+static int prev_sysclk, prev_HTS; -+static int AE_low, AE_high, AE_Target = 52; -+ -+void OV5640_stream_on(void) -+{ -+ ov5640_write_reg(0x4202, 0x00); -+} -+ -+void OV5640_stream_off(void) -+{ -+ ov5640_write_reg(0x4202, 0x0f); -+} -+ -+static const int sclk_rdiv_map[] = {1, 2, 4, 8}; -+ -+int OV5640_get_sysclk(void) -+{ -+ /* calculate sysclk */ -+ int tmp; -+ unsigned Multiplier, PreDiv, SysDiv, Pll_rdiv, Bit_div2x = 1; -+ unsigned div, sclk_rdiv, sysclk; -+ u8 temp; -+ -+ tmp = ov5640_read_reg(0x3034, &temp); -+ if (tmp < 0) -+ return tmp; -+ tmp &= 0x0f; -+ if (tmp == 8 || tmp == 10) -+ Bit_div2x = tmp / 2; -+ -+ tmp = ov5640_read_reg(0x3035, &temp); -+ if (tmp < 0) -+ return tmp; -+ SysDiv = tmp >> 4; -+ if (SysDiv == 0) -+ SysDiv = 16; -+ -+ tmp = ov5640_read_reg(0x3036, &temp); -+ if (tmp < 0) -+ return tmp; -+ Multiplier = tmp; -+ -+ tmp = ov5640_read_reg(0x3037, &temp); -+ if (tmp < 0) -+ return tmp; -+ PreDiv = tmp & 0x0f; -+ Pll_rdiv = ((tmp >> 4) & 0x01) + 1; -+ -+ tmp = ov5640_read_reg(0x3108, &temp); -+ if (tmp < 0) -+ return tmp; -+ sclk_rdiv = sclk_rdiv_map[tmp & 0x03]; -+ -+ sysclk = ov5640_data.mclk / 10000 * Multiplier; -+ div = PreDiv * SysDiv * Pll_rdiv * Bit_div2x * sclk_rdiv; -+ if (!div) { -+ pr_err("%s:Error divide by 0, (%d * %d * %d * %d * %d)\n", -+ __func__, PreDiv, SysDiv, Pll_rdiv, Bit_div2x, sclk_rdiv); -+ return -EINVAL; -+ } -+ if (!sysclk) { -+ pr_err("%s:Error 0 clk, ov5640_data.mclk=%d, Multiplier=%d\n", -+ __func__, ov5640_data.mclk, Multiplier); -+ return -EINVAL; -+ } -+ sysclk /= div; -+ pr_debug("%s: sysclk(%d) = %d / 10000 * %d / (%d * %d * %d * %d * %d)\n", -+ __func__, sysclk, ov5640_data.mclk, Multiplier, -+ PreDiv, SysDiv, Pll_rdiv, Bit_div2x, sclk_rdiv); -+ return sysclk; -+} -+ -+void OV5640_set_night_mode(void) -+{ -+ /* read HTS from register settings */ -+ u8 mode; -+ -+ ov5640_read_reg(0x3a00, &mode); -+ mode &= 0xfb; -+ ov5640_write_reg(0x3a00, mode); -+} -+ -+int OV5640_get_HTS(void) -+{ -+ /* read HTS from register settings */ -+ int HTS; -+ u8 temp; -+ -+ HTS = ov5640_read_reg(0x380c, &temp); -+ HTS = (HTS<<8) + ov5640_read_reg(0x380d, &temp); -+ -+ return HTS; -+} -+ -+int OV5640_get_VTS(void) -+{ -+ /* read VTS from register settings */ -+ int VTS; -+ u8 temp; -+ -+ /* total vertical size[15:8] high byte */ -+ VTS = ov5640_read_reg(0x380e, &temp); -+ -+ VTS = (VTS<<8) + ov5640_read_reg(0x380f, &temp); -+ -+ return VTS; -+} -+ -+int OV5640_set_VTS(int VTS) -+{ -+ /* write VTS to registers */ -+ int temp; -+ -+ temp = VTS & 0xff; -+ ov5640_write_reg(0x380f, temp); -+ -+ temp = VTS>>8; -+ ov5640_write_reg(0x380e, temp); -+ -+ return 0; -+} -+ -+int OV5640_get_shutter(void) -+{ -+ /* read shutter, in number of line period */ -+ int shutter; -+ u8 temp; -+ -+ shutter = (ov5640_read_reg(0x03500, &temp) & 0x0f); -+ shutter = (shutter<<8) + ov5640_read_reg(0x3501, &temp); -+ shutter = (shutter<<4) + (ov5640_read_reg(0x3502, &temp)>>4); -+ -+ return shutter; -+} -+ -+int OV5640_set_shutter(int shutter) -+{ -+ /* write shutter, in number of line period */ -+ int temp; -+ -+ shutter = shutter & 0xffff; -+ -+ temp = shutter & 0x0f; -+ temp = temp<<4; -+ ov5640_write_reg(0x3502, temp); -+ -+ temp = shutter & 0xfff; -+ temp = temp>>4; -+ ov5640_write_reg(0x3501, temp); -+ -+ temp = shutter>>12; -+ ov5640_write_reg(0x3500, temp); -+ -+ return 0; -+} -+ -+int OV5640_get_gain16(void) -+{ -+ /* read gain, 16 = 1x */ -+ int gain16; -+ u8 temp; -+ -+ gain16 = ov5640_read_reg(0x350a, &temp) & 0x03; -+ gain16 = (gain16<<8) + ov5640_read_reg(0x350b, &temp); -+ -+ return gain16; -+} -+ -+int OV5640_set_gain16(int gain16) -+{ -+ /* write gain, 16 = 1x */ -+ u8 temp; -+ gain16 = gain16 & 0x3ff; -+ -+ temp = gain16 & 0xff; -+ ov5640_write_reg(0x350b, temp); -+ -+ temp = gain16>>8; -+ ov5640_write_reg(0x350a, temp); -+ -+ return 0; -+} -+ -+int OV5640_get_light_freq(void) -+{ -+ /* get banding filter value */ -+ int temp, temp1, light_freq = 0; -+ u8 tmp; -+ -+ temp = ov5640_read_reg(0x3c01, &tmp); -+ -+ if (temp & 0x80) { -+ /* manual */ -+ temp1 = ov5640_read_reg(0x3c00, &tmp); -+ if (temp1 & 0x04) { -+ /* 50Hz */ -+ light_freq = 50; -+ } else { -+ /* 60Hz */ -+ light_freq = 60; -+ } -+ } else { -+ /* auto */ -+ temp1 = ov5640_read_reg(0x3c0c, &tmp); -+ if (temp1 & 0x01) { -+ /* 50Hz */ -+ light_freq = 50; -+ } else { -+ /* 60Hz */ -+ light_freq = 60; -+ } -+ } -+ return light_freq; -+} -+ -+void OV5640_set_bandingfilter(void) -+{ -+ int prev_VTS; -+ int band_step60, max_band60, band_step50, max_band50; -+ -+ /* read preview PCLK */ -+ prev_sysclk = OV5640_get_sysclk(); -+ /* read preview HTS */ -+ prev_HTS = OV5640_get_HTS(); -+ -+ /* read preview VTS */ -+ prev_VTS = OV5640_get_VTS(); -+ -+ /* calculate banding filter */ -+ /* 60Hz */ -+ band_step60 = prev_sysclk * 100/prev_HTS * 100/120; -+ ov5640_write_reg(0x3a0a, (band_step60 >> 8)); -+ ov5640_write_reg(0x3a0b, (band_step60 & 0xff)); -+ -+ max_band60 = (int)((prev_VTS-4)/band_step60); -+ ov5640_write_reg(0x3a0d, max_band60); -+ -+ /* 50Hz */ -+ band_step50 = prev_sysclk * 100/prev_HTS; -+ ov5640_write_reg(0x3a08, (band_step50 >> 8)); -+ ov5640_write_reg(0x3a09, (band_step50 & 0xff)); -+ -+ max_band50 = (int)((prev_VTS-4)/band_step50); -+ ov5640_write_reg(0x3a0e, max_band50); -+} -+ -+int OV5640_set_AE_target(int target) -+{ -+ /* stable in high */ -+ int fast_high, fast_low; -+ AE_low = target * 23 / 25; /* 0.92 */ -+ AE_high = target * 27 / 25; /* 1.08 */ -+ -+ fast_high = AE_high<<1; -+ if (fast_high > 255) -+ fast_high = 255; -+ -+ fast_low = AE_low >> 1; -+ -+ ov5640_write_reg(0x3a0f, AE_high); -+ ov5640_write_reg(0x3a10, AE_low); -+ ov5640_write_reg(0x3a1b, AE_high); -+ ov5640_write_reg(0x3a1e, AE_low); -+ ov5640_write_reg(0x3a11, fast_high); -+ ov5640_write_reg(0x3a1f, fast_low); -+ -+ return 0; -+} -+ -+void OV5640_turn_on_AE_AG(int enable) -+{ -+ u8 ae_ag_ctrl; -+ -+ ov5640_read_reg(0x3503, &ae_ag_ctrl); -+ if (enable) { -+ /* turn on auto AE/AG */ -+ ae_ag_ctrl = ae_ag_ctrl & ~(0x03); -+ } else { -+ /* turn off AE/AG */ -+ ae_ag_ctrl = ae_ag_ctrl | 0x03; -+ } -+ ov5640_write_reg(0x3503, ae_ag_ctrl); -+} -+ -+bool binning_on(void) -+{ -+ u8 temp; -+ ov5640_read_reg(0x3821, &temp); -+ temp &= 0xfe; -+ if (temp) -+ return true; -+ else -+ return false; -+} -+ -+static void ov5640_set_virtual_channel(int channel) -+{ -+ u8 channel_id; -+ -+ ov5640_read_reg(0x4814, &channel_id); -+ channel_id &= ~(3 << 6); -+ ov5640_write_reg(0x4814, channel_id | (channel << 6)); -+} -+ -+/* download ov5640 settings to sensor through i2c */ -+static int ov5640_download_firmware(struct reg_value *pModeSetting, s32 ArySize) -+{ -+ register u32 Delay_ms = 0; -+ register u16 RegAddr = 0; -+ register u8 Mask = 0; -+ register u8 Val = 0; -+ u8 RegVal = 0; -+ int i, retval = 0; -+ -+ for (i = 0; i < ArySize; ++i, ++pModeSetting) { -+ Delay_ms = pModeSetting->u32Delay_ms; -+ RegAddr = pModeSetting->u16RegAddr; -+ Val = pModeSetting->u8Val; -+ Mask = pModeSetting->u8Mask; -+ -+ if (Mask) { -+ retval = ov5640_read_reg(RegAddr, &RegVal); -+ if (retval < 0) -+ goto err; -+ -+ RegVal &= ~(u8)Mask; -+ Val &= Mask; -+ Val |= RegVal; -+ } -+ -+ retval = ov5640_write_reg(RegAddr, Val); -+ if (retval < 0) -+ goto err; -+ -+ if (Delay_ms) -+ msleep(Delay_ms); -+ } -+err: -+ return retval; -+} -+ -+/* sensor changes between scaling and subsampling -+ * go through exposure calcualtion -+ */ -+static int ov5640_change_mode_exposure_calc(enum ov5640_frame_rate frame_rate, -+ enum ov5640_mode mode) -+{ -+ struct reg_value *pModeSetting = NULL; -+ s32 ArySize = 0; -+ u8 average; -+ int prev_shutter, prev_gain16; -+ int cap_shutter, cap_gain16; -+ int cap_sysclk, cap_HTS, cap_VTS; -+ int light_freq, cap_bandfilt, cap_maxband; -+ long cap_gain16_shutter; -+ int retval = 0; -+ -+ /* check if the input mode and frame rate is valid */ -+ pModeSetting = -+ ov5640_mode_info_data[frame_rate][mode].init_data_ptr; -+ ArySize = -+ ov5640_mode_info_data[frame_rate][mode].init_data_size; -+ -+ ov5640_data.pix.width = -+ ov5640_mode_info_data[frame_rate][mode].width; -+ ov5640_data.pix.height = -+ ov5640_mode_info_data[frame_rate][mode].height; -+ -+ if (ov5640_data.pix.width == 0 || ov5640_data.pix.height == 0 || -+ pModeSetting == NULL || ArySize == 0) -+ return -EINVAL; -+ -+ /* auto focus */ -+ /* OV5640_auto_focus();//if no af function, just skip it */ -+ -+ /* turn off AE/AG */ -+ OV5640_turn_on_AE_AG(0); -+ -+ /* read preview shutter */ -+ prev_shutter = OV5640_get_shutter(); -+ if ((binning_on()) && (mode != ov5640_mode_720P_1280_720) -+ && (mode != ov5640_mode_1080P_1920_1080)) -+ prev_shutter *= 2; -+ -+ /* read preview gain */ -+ prev_gain16 = OV5640_get_gain16(); -+ -+ /* get average */ -+ ov5640_read_reg(0x56a1, &average); -+ -+ /* turn off night mode for capture */ -+ OV5640_set_night_mode(); -+ -+ /* turn off overlay */ -+ /* ov5640_write_reg(0x3022, 0x06);//if no af function, just skip it */ -+ -+ OV5640_stream_off(); -+ -+ /* Write capture setting */ -+ retval = ov5640_download_firmware(pModeSetting, ArySize); -+ if (retval < 0) -+ goto err; -+ -+ /* read capture VTS */ -+ cap_VTS = OV5640_get_VTS(); -+ cap_HTS = OV5640_get_HTS(); -+ cap_sysclk = OV5640_get_sysclk(); -+ -+ /* calculate capture banding filter */ -+ light_freq = OV5640_get_light_freq(); -+ if (light_freq == 60) { -+ /* 60Hz */ -+ cap_bandfilt = cap_sysclk * 100 / cap_HTS * 100 / 120; -+ } else { -+ /* 50Hz */ -+ cap_bandfilt = cap_sysclk * 100 / cap_HTS; -+ } -+ cap_maxband = (int)((cap_VTS - 4)/cap_bandfilt); -+ -+ /* calculate capture shutter/gain16 */ -+ if (average > AE_low && average < AE_high) { -+ /* in stable range */ -+ cap_gain16_shutter = -+ prev_gain16 * prev_shutter * cap_sysclk/prev_sysclk -+ * prev_HTS/cap_HTS * AE_Target / average; -+ } else { -+ cap_gain16_shutter = -+ prev_gain16 * prev_shutter * cap_sysclk/prev_sysclk -+ * prev_HTS/cap_HTS; -+ } -+ -+ /* gain to shutter */ -+ if (cap_gain16_shutter < (cap_bandfilt * 16)) { -+ /* shutter < 1/100 */ -+ cap_shutter = cap_gain16_shutter/16; -+ if (cap_shutter < 1) -+ cap_shutter = 1; -+ -+ cap_gain16 = cap_gain16_shutter/cap_shutter; -+ if (cap_gain16 < 16) -+ cap_gain16 = 16; -+ } else { -+ if (cap_gain16_shutter > -+ (cap_bandfilt * cap_maxband * 16)) { -+ /* exposure reach max */ -+ cap_shutter = cap_bandfilt * cap_maxband; -+ cap_gain16 = cap_gain16_shutter / cap_shutter; -+ } else { -+ /* 1/100 < (cap_shutter = n/100) =< max */ -+ cap_shutter = -+ ((int) (cap_gain16_shutter/16 / cap_bandfilt)) -+ *cap_bandfilt; -+ cap_gain16 = cap_gain16_shutter / cap_shutter; -+ } -+ } -+ -+ /* write capture gain */ -+ OV5640_set_gain16(cap_gain16); -+ -+ /* write capture shutter */ -+ if (cap_shutter > (cap_VTS - 4)) { -+ cap_VTS = cap_shutter + 4; -+ OV5640_set_VTS(cap_VTS); -+ } -+ OV5640_set_shutter(cap_shutter); -+ -+ OV5640_stream_on(); -+ -+err: -+ return retval; -+} -+ -+/* if sensor changes inside scaling or subsampling -+ * change mode directly -+ * */ -+static int ov5640_change_mode_direct(enum ov5640_frame_rate frame_rate, -+ enum ov5640_mode mode) -+{ -+ struct reg_value *pModeSetting = NULL; -+ s32 ArySize = 0; -+ int retval = 0; -+ -+ /* check if the input mode and frame rate is valid */ -+ pModeSetting = -+ ov5640_mode_info_data[frame_rate][mode].init_data_ptr; -+ ArySize = -+ ov5640_mode_info_data[frame_rate][mode].init_data_size; -+ -+ ov5640_data.pix.width = -+ ov5640_mode_info_data[frame_rate][mode].width; -+ ov5640_data.pix.height = -+ ov5640_mode_info_data[frame_rate][mode].height; -+ -+ if (ov5640_data.pix.width == 0 || ov5640_data.pix.height == 0 || -+ pModeSetting == NULL || ArySize == 0) -+ return -EINVAL; -+ -+ /* turn off AE/AG */ -+ OV5640_turn_on_AE_AG(0); -+ -+ OV5640_stream_off(); -+ -+ /* Write capture setting */ -+ retval = ov5640_download_firmware(pModeSetting, ArySize); -+ if (retval < 0) -+ goto err; -+ -+ OV5640_stream_on(); -+ -+ OV5640_turn_on_AE_AG(1); -+ -+err: -+ return retval; -+} -+ -+static int ov5640_init_mode(enum ov5640_frame_rate frame_rate, -+ enum ov5640_mode mode, enum ov5640_mode orig_mode) -+{ -+ struct reg_value *pModeSetting = NULL; -+ s32 ArySize = 0; -+ int retval = 0; -+ void *mipi_csi2_info; -+ u32 mipi_reg, msec_wait4stable = 0; -+ enum ov5640_downsize_mode dn_mode, orig_dn_mode; -+ -+ if ((mode > ov5640_mode_MAX || mode < ov5640_mode_MIN) -+ && (mode != ov5640_mode_INIT)) { -+ pr_err("Wrong ov5640 mode detected!\n"); -+ return -1; -+ } -+ -+ mipi_csi2_info = mipi_csi2_get_info(); -+ -+ /* initial mipi dphy */ -+ if (!mipi_csi2_info) { -+ printk(KERN_ERR "%s() in %s: Fail to get mipi_csi2_info!\n", -+ __func__, __FILE__); -+ return -1; -+ } -+ -+ if (!mipi_csi2_get_status(mipi_csi2_info)) -+ mipi_csi2_enable(mipi_csi2_info); -+ -+ if (!mipi_csi2_get_status(mipi_csi2_info)) { -+ pr_err("Can not enable mipi csi2 driver!\n"); -+ return -1; -+ } -+ -+ mipi_csi2_set_lanes(mipi_csi2_info, 2); -+ -+ /*Only reset MIPI CSI2 HW at sensor initialize*/ -+ if (mode == ov5640_mode_INIT) -+ mipi_csi2_reset(mipi_csi2_info); -+ -+ if (ov5640_data.pix.pixelformat == V4L2_PIX_FMT_UYVY) -+ mipi_csi2_set_datatype(mipi_csi2_info, MIPI_DT_YUV422); -+ else if (ov5640_data.pix.pixelformat == V4L2_PIX_FMT_RGB565) -+ mipi_csi2_set_datatype(mipi_csi2_info, MIPI_DT_RGB565); -+ else -+ pr_err("currently this sensor format can not be supported!\n"); -+ -+ dn_mode = ov5640_mode_info_data[frame_rate][mode].dn_mode; -+ orig_dn_mode = ov5640_mode_info_data[frame_rate][orig_mode].dn_mode; -+ if (mode == ov5640_mode_INIT) { -+ pModeSetting = ov5640_init_setting_30fps_VGA; -+ ArySize = ARRAY_SIZE(ov5640_init_setting_30fps_VGA); -+ -+ ov5640_data.pix.width = 640; -+ ov5640_data.pix.height = 480; -+ retval = ov5640_download_firmware(pModeSetting, ArySize); -+ if (retval < 0) -+ goto err; -+ -+ pModeSetting = ov5640_setting_30fps_VGA_640_480; -+ ArySize = ARRAY_SIZE(ov5640_setting_30fps_VGA_640_480); -+ retval = ov5640_download_firmware(pModeSetting, ArySize); -+ } else if ((dn_mode == SUBSAMPLING && orig_dn_mode == SCALING) || -+ (dn_mode == SCALING && orig_dn_mode == SUBSAMPLING)) { -+ /* change between subsampling and scaling -+ * go through exposure calucation */ -+ retval = ov5640_change_mode_exposure_calc(frame_rate, mode); -+ } else { -+ /* change inside subsampling or scaling -+ * download firmware directly */ -+ retval = ov5640_change_mode_direct(frame_rate, mode); -+ } -+ -+ if (retval < 0) -+ goto err; -+ -+ OV5640_set_AE_target(AE_Target); -+ OV5640_get_light_freq(); -+ OV5640_set_bandingfilter(); -+ ov5640_set_virtual_channel(ov5640_data.virtual_channel); -+ -+ /* add delay to wait for sensor stable */ -+ if (mode == ov5640_mode_QSXGA_2592_1944) { -+ /* dump the first two frames: 1/7.5*2 -+ * the frame rate of QSXGA is 7.5fps */ -+ msec_wait4stable = 267; -+ } else if (frame_rate == ov5640_15_fps) { -+ /* dump the first nine frames: 1/15*9 */ -+ msec_wait4stable = 600; -+ } else if (frame_rate == ov5640_30_fps) { -+ /* dump the first nine frames: 1/30*9 */ -+ msec_wait4stable = 300; -+ } -+ msleep(msec_wait4stable); -+ -+ if (mipi_csi2_info) { -+ unsigned int i = 0; -+ -+ /* wait for mipi sensor ready */ -+ while (1) { -+ mipi_reg = mipi_csi2_dphy_status(mipi_csi2_info); -+ if (mipi_reg != 0x200) -+ break; -+ if (i++ >= 20) { -+ pr_err("mipi csi2 can not receive sensor clk! %x\n", mipi_reg); -+ return -1; -+ } -+ msleep(10); -+ } -+ -+ i = 0; -+ /* wait for mipi stable */ -+ while (1) { -+ mipi_reg = mipi_csi2_get_error1(mipi_csi2_info); -+ if (!mipi_reg) -+ break; -+ if (i++ >= 20) { -+ pr_err("mipi csi2 can not receive data correctly!\n"); -+ return -1; -+ } -+ msleep(10); -+ } -+ -+ } -+err: -+ return retval; -+} -+ -+/* --------------- IOCTL functions from v4l2_int_ioctl_desc --------------- */ -+ -+static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p) -+{ -+ if (s == NULL) { -+ pr_err(" ERROR!! no slave device set!\n"); -+ return -1; -+ } -+ -+ memset(p, 0, sizeof(*p)); -+ p->u.bt656.clock_curr = ov5640_data.mclk; -+ pr_debug(" clock_curr=mclk=%d\n", ov5640_data.mclk); -+ p->if_type = V4L2_IF_TYPE_BT656; -+ p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT; -+ p->u.bt656.clock_min = OV5640_XCLK_MIN; -+ p->u.bt656.clock_max = OV5640_XCLK_MAX; -+ p->u.bt656.bt_sync_correct = 1; /* Indicate external vsync */ -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_s_power - V4L2 sensor interface handler for VIDIOC_S_POWER ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @on: indicates power mode (on or off) -+ * -+ * Turns the power on or off, depending on the value of on and returns the -+ * appropriate error code. -+ */ -+static int ioctl_s_power(struct v4l2_int_device *s, int on) -+{ -+ struct sensor_data *sensor = s->priv; -+ -+ if (on && !sensor->on) { -+ if (io_regulator) -+ if (regulator_enable(io_regulator) != 0) -+ return -EIO; -+ if (core_regulator) -+ if (regulator_enable(core_regulator) != 0) -+ return -EIO; -+ if (gpo_regulator) -+ if (regulator_enable(gpo_regulator) != 0) -+ return -EIO; -+ if (analog_regulator) -+ if (regulator_enable(analog_regulator) != 0) -+ return -EIO; -+ /* Make sure power on */ -+ ov5640_standby(0); -+ } else if (!on && sensor->on) { -+ if (analog_regulator) -+ regulator_disable(analog_regulator); -+ if (core_regulator) -+ regulator_disable(core_regulator); -+ if (io_regulator) -+ regulator_disable(io_regulator); -+ if (gpo_regulator) -+ regulator_disable(gpo_regulator); -+ -+ ov5640_standby(1); -+ } -+ -+ sensor->on = on; -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure -+ * -+ * Returns the sensor's video CAPTURE parameters. -+ */ -+static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) -+{ -+ struct sensor_data *sensor = s->priv; -+ struct v4l2_captureparm *cparm = &a->parm.capture; -+ int ret = 0; -+ -+ switch (a->type) { -+ /* This is the only case currently handled. */ -+ case V4L2_BUF_TYPE_VIDEO_CAPTURE: -+ memset(a, 0, sizeof(*a)); -+ a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; -+ cparm->capability = sensor->streamcap.capability; -+ cparm->timeperframe = sensor->streamcap.timeperframe; -+ cparm->capturemode = sensor->streamcap.capturemode; -+ ret = 0; -+ break; -+ -+ /* These are all the possible cases. */ -+ case V4L2_BUF_TYPE_VIDEO_OUTPUT: -+ case V4L2_BUF_TYPE_VIDEO_OVERLAY: -+ case V4L2_BUF_TYPE_VBI_CAPTURE: -+ case V4L2_BUF_TYPE_VBI_OUTPUT: -+ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: -+ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: -+ ret = -EINVAL; -+ break; -+ -+ default: -+ pr_debug(" type is unknown - %d\n", a->type); -+ ret = -EINVAL; -+ break; -+ } -+ -+ return ret; -+} -+ -+/*! -+ * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure -+ * -+ * Configures the sensor to use the input parameters, if possible. If -+ * not possible, reverts to the old parameters and returns the -+ * appropriate error code. -+ */ -+static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) -+{ -+ struct sensor_data *sensor = s->priv; -+ struct v4l2_fract *timeperframe = &a->parm.capture.timeperframe; -+ u32 tgt_fps; /* target frames per secound */ -+ enum ov5640_frame_rate frame_rate; -+ enum ov5640_mode orig_mode; -+ int ret = 0; -+ -+ /* Make sure power on */ -+ ov5640_standby(0); -+ -+ switch (a->type) { -+ /* This is the only case currently handled. */ -+ case V4L2_BUF_TYPE_VIDEO_CAPTURE: -+ /* Check that the new frame rate is allowed. */ -+ if ((timeperframe->numerator == 0) || -+ (timeperframe->denominator == 0)) { -+ timeperframe->denominator = DEFAULT_FPS; -+ timeperframe->numerator = 1; -+ } -+ -+ tgt_fps = timeperframe->denominator / -+ timeperframe->numerator; -+ -+ if (tgt_fps > MAX_FPS) { -+ timeperframe->denominator = MAX_FPS; -+ timeperframe->numerator = 1; -+ } else if (tgt_fps < MIN_FPS) { -+ timeperframe->denominator = MIN_FPS; -+ timeperframe->numerator = 1; -+ } -+ -+ /* Actual frame rate we use */ -+ tgt_fps = timeperframe->denominator / -+ timeperframe->numerator; -+ -+ if (tgt_fps == 15) -+ frame_rate = ov5640_15_fps; -+ else if (tgt_fps == 30) -+ frame_rate = ov5640_30_fps; -+ else { -+ pr_err(" The camera frame rate is not supported!\n"); -+ return -EINVAL; -+ } -+ -+ orig_mode = sensor->streamcap.capturemode; -+ ret = ov5640_init_mode(frame_rate, -+ (u32)a->parm.capture.capturemode, orig_mode); -+ if (ret < 0) -+ return ret; -+ -+ sensor->streamcap.timeperframe = *timeperframe; -+ sensor->streamcap.capturemode = -+ (u32)a->parm.capture.capturemode; -+ -+ break; -+ -+ /* These are all the possible cases. */ -+ case V4L2_BUF_TYPE_VIDEO_OUTPUT: -+ case V4L2_BUF_TYPE_VIDEO_OVERLAY: -+ case V4L2_BUF_TYPE_VBI_CAPTURE: -+ case V4L2_BUF_TYPE_VBI_OUTPUT: -+ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: -+ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: -+ pr_debug(" type is not " \ -+ "V4L2_BUF_TYPE_VIDEO_CAPTURE but %d\n", -+ a->type); -+ ret = -EINVAL; -+ break; -+ -+ default: -+ pr_debug(" type is unknown - %d\n", a->type); -+ ret = -EINVAL; -+ break; -+ } -+ -+ return ret; -+} -+ -+/*! -+ * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap -+ * @s: pointer to standard V4L2 device structure -+ * @f: pointer to standard V4L2 v4l2_format structure -+ * -+ * Returns the sensor's current pixel format in the v4l2_format -+ * parameter. -+ */ -+static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) -+{ -+ struct sensor_data *sensor = s->priv; -+ -+ switch (f->type) { -+ case V4L2_BUF_TYPE_VIDEO_CAPTURE: -+ f->fmt.pix = sensor->pix; -+ pr_debug("%s: %dx%d\n", __func__, sensor->pix.width, sensor->pix.height); -+ break; -+ -+ case V4L2_BUF_TYPE_SENSOR: -+ pr_debug("%s: left=%d, top=%d, %dx%d\n", __func__, -+ sensor->spix.left, sensor->spix.top, -+ sensor->spix.swidth, sensor->spix.sheight); -+ f->fmt.spix = sensor->spix; -+ break; -+ -+ case V4L2_BUF_TYPE_PRIVATE: -+ break; -+ -+ default: -+ f->fmt.pix = sensor->pix; -+ break; -+ } -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure -+ * -+ * If the requested control is supported, returns the control's current -+ * value from the video_control[] array. Otherwise, returns -EINVAL -+ * if the control is not supported. -+ */ -+static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) -+{ -+ int ret = 0; -+ -+ switch (vc->id) { -+ case V4L2_CID_BRIGHTNESS: -+ vc->value = ov5640_data.brightness; -+ break; -+ case V4L2_CID_HUE: -+ vc->value = ov5640_data.hue; -+ break; -+ case V4L2_CID_CONTRAST: -+ vc->value = ov5640_data.contrast; -+ break; -+ case V4L2_CID_SATURATION: -+ vc->value = ov5640_data.saturation; -+ break; -+ case V4L2_CID_RED_BALANCE: -+ vc->value = ov5640_data.red; -+ break; -+ case V4L2_CID_BLUE_BALANCE: -+ vc->value = ov5640_data.blue; -+ break; -+ case V4L2_CID_EXPOSURE: -+ vc->value = ov5640_data.ae_mode; -+ break; -+ default: -+ ret = -EINVAL; -+ } -+ -+ return ret; -+} -+ -+/*! -+ * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure -+ * -+ * If the requested control is supported, sets the control's current -+ * value in HW (and updates the video_control[] array). Otherwise, -+ * returns -EINVAL if the control is not supported. -+ */ -+static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) -+{ -+ int retval = 0; -+ -+ pr_debug("In ov5640:ioctl_s_ctrl %d\n", -+ vc->id); -+ -+ switch (vc->id) { -+ case V4L2_CID_BRIGHTNESS: -+ break; -+ case V4L2_CID_CONTRAST: -+ break; -+ case V4L2_CID_SATURATION: -+ break; -+ case V4L2_CID_HUE: -+ break; -+ case V4L2_CID_AUTO_WHITE_BALANCE: -+ break; -+ case V4L2_CID_DO_WHITE_BALANCE: -+ break; -+ case V4L2_CID_RED_BALANCE: -+ break; -+ case V4L2_CID_BLUE_BALANCE: -+ break; -+ case V4L2_CID_GAMMA: -+ break; -+ case V4L2_CID_EXPOSURE: -+ break; -+ case V4L2_CID_AUTOGAIN: -+ break; -+ case V4L2_CID_GAIN: -+ break; -+ case V4L2_CID_HFLIP: -+ break; -+ case V4L2_CID_VFLIP: -+ break; -+ default: -+ retval = -EPERM; -+ break; -+ } -+ -+ return retval; -+} -+ -+/*! -+ * ioctl_enum_framesizes - V4L2 sensor interface handler for -+ * VIDIOC_ENUM_FRAMESIZES ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure -+ * -+ * Return 0 if successful, otherwise -EINVAL. -+ */ -+static int ioctl_enum_framesizes(struct v4l2_int_device *s, -+ struct v4l2_frmsizeenum *fsize) -+{ -+ if (fsize->index > ov5640_mode_MAX) -+ return -EINVAL; -+ -+ fsize->pixel_format = ov5640_data.pix.pixelformat; -+ fsize->discrete.width = -+ max(ov5640_mode_info_data[0][fsize->index].width, -+ ov5640_mode_info_data[1][fsize->index].width); -+ fsize->discrete.height = -+ max(ov5640_mode_info_data[0][fsize->index].height, -+ ov5640_mode_info_data[1][fsize->index].height); -+ return 0; -+} -+ -+/*! -+ * ioctl_g_chip_ident - V4L2 sensor interface handler for -+ * VIDIOC_DBG_G_CHIP_IDENT ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @id: pointer to int -+ * -+ * Return 0. -+ */ -+static int ioctl_g_chip_ident(struct v4l2_int_device *s, int *id) -+{ -+ ((struct v4l2_dbg_chip_ident *)id)->match.type = -+ V4L2_CHIP_MATCH_I2C_DRIVER; -+ strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name, -+ "ov5640_mipi_camera"); -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT -+ * @s: pointer to standard V4L2 device structure -+ */ -+static int ioctl_init(struct v4l2_int_device *s) -+{ -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_enum_fmt_cap - V4L2 sensor interface handler for VIDIOC_ENUM_FMT -+ * @s: pointer to standard V4L2 device structure -+ * @fmt: pointer to standard V4L2 fmt description structure -+ * -+ * Return 0. -+ */ -+static int ioctl_enum_fmt_cap(struct v4l2_int_device *s, -+ struct v4l2_fmtdesc *fmt) -+{ -+ if (fmt->index > ov5640_mode_MAX) -+ return -EINVAL; -+ -+ fmt->pixelformat = ov5640_data.pix.pixelformat; -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num -+ * @s: pointer to standard V4L2 device structure -+ * -+ * Initialise the device when slave attaches to the master. -+ */ -+static int ioctl_dev_init(struct v4l2_int_device *s) -+{ -+ struct sensor_data *sensor = s->priv; -+ u32 tgt_xclk; /* target xclk */ -+ u32 tgt_fps; /* target frames per secound */ -+ int ret; -+ enum ov5640_frame_rate frame_rate; -+ void *mipi_csi2_info; -+ -+ ov5640_data.on = true; -+ -+ /* mclk */ -+ tgt_xclk = ov5640_data.mclk; -+ tgt_xclk = min(tgt_xclk, (u32)OV5640_XCLK_MAX); -+ tgt_xclk = max(tgt_xclk, (u32)OV5640_XCLK_MIN); -+ ov5640_data.mclk = tgt_xclk; -+ -+ pr_debug(" Setting mclk to %d MHz\n", tgt_xclk / 1000000); -+ -+ /* Default camera frame rate is set in probe */ -+ tgt_fps = sensor->streamcap.timeperframe.denominator / -+ sensor->streamcap.timeperframe.numerator; -+ -+ if (tgt_fps == 15) -+ frame_rate = ov5640_15_fps; -+ else if (tgt_fps == 30) -+ frame_rate = ov5640_30_fps; -+ else -+ return -EINVAL; /* Only support 15fps or 30fps now. */ -+ -+ mipi_csi2_info = mipi_csi2_get_info(); -+ -+ /* enable mipi csi2 */ -+ if (mipi_csi2_info) -+ mipi_csi2_enable(mipi_csi2_info); -+ else { -+ printk(KERN_ERR "%s() in %s: Fail to get mipi_csi2_info!\n", -+ __func__, __FILE__); -+ return -EPERM; -+ } -+ -+ ret = ov5640_init_mode(frame_rate, ov5640_mode_INIT, ov5640_mode_INIT); -+ -+ return ret; -+} -+ -+/*! -+ * ioctl_dev_exit - V4L2 sensor interface handler for vidioc_int_dev_exit_num -+ * @s: pointer to standard V4L2 device structure -+ * -+ * Delinitialise the device when slave detaches to the master. -+ */ -+static int ioctl_dev_exit(struct v4l2_int_device *s) -+{ -+ void *mipi_csi2_info; -+ -+ mipi_csi2_info = mipi_csi2_get_info(); -+ -+ /* disable mipi csi2 */ -+ if (mipi_csi2_info) -+ if (mipi_csi2_get_status(mipi_csi2_info)) -+ mipi_csi2_disable(mipi_csi2_info); -+ -+ return 0; -+} -+ -+/*! -+ * This structure defines all the ioctls for this module and links them to the -+ * enumeration. -+ */ -+static struct v4l2_int_ioctl_desc ov5640_ioctl_desc[] = { -+ {vidioc_int_dev_init_num, (v4l2_int_ioctl_func *) ioctl_dev_init}, -+ {vidioc_int_dev_exit_num, ioctl_dev_exit}, -+ {vidioc_int_s_power_num, (v4l2_int_ioctl_func *) ioctl_s_power}, -+ {vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func *) ioctl_g_ifparm}, -+/* {vidioc_int_g_needs_reset_num, -+ (v4l2_int_ioctl_func *)ioctl_g_needs_reset}, */ -+/* {vidioc_int_reset_num, (v4l2_int_ioctl_func *)ioctl_reset}, */ -+ {vidioc_int_init_num, (v4l2_int_ioctl_func *) ioctl_init}, -+ {vidioc_int_enum_fmt_cap_num, -+ (v4l2_int_ioctl_func *) ioctl_enum_fmt_cap}, -+/* {vidioc_int_try_fmt_cap_num, -+ (v4l2_int_ioctl_func *)ioctl_try_fmt_cap}, */ -+ {vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func *) ioctl_g_fmt_cap}, -+/* {vidioc_int_s_fmt_cap_num, (v4l2_int_ioctl_func *) ioctl_s_fmt_cap}, */ -+ {vidioc_int_g_parm_num, (v4l2_int_ioctl_func *) ioctl_g_parm}, -+ {vidioc_int_s_parm_num, (v4l2_int_ioctl_func *) ioctl_s_parm}, -+/* {vidioc_int_queryctrl_num, (v4l2_int_ioctl_func *)ioctl_queryctrl}, */ -+ {vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func *) ioctl_g_ctrl}, -+ {vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func *) ioctl_s_ctrl}, -+ {vidioc_int_enum_framesizes_num, -+ (v4l2_int_ioctl_func *) ioctl_enum_framesizes}, -+ {vidioc_int_g_chip_ident_num, -+ (v4l2_int_ioctl_func *) ioctl_g_chip_ident}, -+}; -+ -+static struct v4l2_int_slave ov5640_slave = { -+ .ioctls = ov5640_ioctl_desc, -+ .num_ioctls = ARRAY_SIZE(ov5640_ioctl_desc), -+}; -+ -+static struct v4l2_int_device ov5640_int_device = { -+ .module = THIS_MODULE, -+ .name = "ov5640_mipi", -+ .type = v4l2_int_type_slave, -+ .u = { -+ .slave = &ov5640_slave, -+ }, -+}; -+ -+static ssize_t show_reg(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ u8 val; -+ s32 rval = ov5640_read_reg(ov5640_data.last_reg, &val); -+ -+ return sprintf(buf, "ov5640[0x%04x]=0x%02x\n",ov5640_data.last_reg, rval); -+} -+static ssize_t set_reg(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ int regnum, value; -+ int num_parsed = sscanf(buf, "%04x=%02x", ®num, &value); -+ if (1 <= num_parsed) { -+ if (0xffff < (unsigned)regnum){ -+ pr_err("%s:invalid regnum %x\n", __func__, regnum); -+ return 0; -+ } -+ ov5640_data.last_reg = regnum; -+ } -+ if (2 == num_parsed) { -+ if (0xff < (unsigned)value) { -+ pr_err("%s:invalid value %x\n", __func__, value); -+ return 0; -+ } -+ ov5640_write_reg(ov5640_data.last_reg, value); -+ } -+ return count; -+} -+static DEVICE_ATTR(ov5640_reg, S_IRUGO|S_IWUSR|S_IWGRP, show_reg, set_reg); -+ -+/*! -+ * ov5640 I2C probe function -+ * -+ * @param adapter struct i2c_adapter * -+ * @return Error code indicating success or failure -+ */ -+static int ov5640_probe(struct i2c_client *client, -+ const struct i2c_device_id *id) -+{ -+ struct device *dev = &client->dev; -+ int retval; -+ u8 chip_id_high, chip_id_low; -+ struct sensor_data *sensor = &ov5640_data; -+ -+ /* request power down pin */ -+ pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0); -+ if (!gpio_is_valid(pwn_gpio)) { -+ dev_warn(dev, "no sensor pwdn pin available"); -+ return -EINVAL; -+ } -+ retval = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH, -+ "ov5640_mipi_pwdn"); -+ if (retval < 0) { -+ dev_warn(dev, "request of pwn_gpio failed"); -+ return retval; -+ } -+ -+ /* request reset pin */ -+ rst_gpio = of_get_named_gpio(dev->of_node, "rst-gpios", 0); -+ if (!gpio_is_valid(rst_gpio)) { -+ dev_warn(dev, "no sensor reset pin available"); -+ return -EINVAL; -+ } -+ retval = devm_gpio_request_one(dev, rst_gpio, GPIOF_OUT_INIT_HIGH, -+ "ov5640_mipi_reset"); -+ if (retval < 0) { -+ dev_warn(dev, "request of ov5640_mipi_reset failed"); -+ return retval; -+ } -+ -+ /* Set initial values for the sensor struct. */ -+ memset(&ov5640_data, 0, sizeof(ov5640_data)); -+ -+ sensor->mipi_camera = 1; -+ ov5640_data.sensor_clk = devm_clk_get(dev, "csi_mclk"); -+ if (IS_ERR(ov5640_data.sensor_clk)) { -+ /* assuming clock enabled by default */ -+ ov5640_data.sensor_clk = NULL; -+ dev_err(dev, "clock-frequency missing or invalid\n"); -+ return PTR_ERR(ov5640_data.sensor_clk); -+ } -+ -+ retval = of_property_read_u32(dev->of_node, "mclk", -+ &(ov5640_data.mclk)); -+ if (retval) { -+ dev_err(dev, "mclk missing or invalid\n"); -+ return retval; -+ } -+ -+ retval = of_property_read_u32(dev->of_node, "mclk_source", -+ (u32 *) &(ov5640_data.mclk_source)); -+ if (retval) { -+ dev_err(dev, "mclk_source missing or invalid\n"); -+ return retval; -+ } -+ -+ retval = of_property_read_u32(dev->of_node, "ipu_id", -+ &sensor->ipu_id); -+ if (retval) { -+ dev_err(dev, "ipu_id missing or invalid\n"); -+ return retval; -+ } -+ -+ retval = of_property_read_u32(dev->of_node, "csi_id", -+ &(ov5640_data.csi)); -+ if (retval) { -+ dev_err(dev, "csi id missing or invalid\n"); -+ return retval; -+ } -+ -+ clk_prepare_enable(ov5640_data.sensor_clk); -+ -+ ov5640_data.io_init = ov5640_reset; -+ ov5640_data.i2c_client = client; -+ ov5640_data.pix.pixelformat = V4L2_PIX_FMT_UYVY; -+ ov5640_data.pix.width = 640; -+ ov5640_data.pix.height = 480; -+ ov5640_data.streamcap.capability = V4L2_MODE_HIGHQUALITY | -+ V4L2_CAP_TIMEPERFRAME; -+ ov5640_data.streamcap.capturemode = 0; -+ ov5640_data.streamcap.timeperframe.denominator = DEFAULT_FPS; -+ ov5640_data.streamcap.timeperframe.numerator = 1; -+ -+ ov5640_power_on(dev); -+ -+ ov5640_reset(); -+ -+ ov5640_standby(0); -+ -+ retval = ov5640_read_reg(OV5640_CHIP_ID_HIGH_BYTE, &chip_id_high); -+ if (retval < 0 || chip_id_high != 0x56) { -+ pr_warning("camera ov5640_mipi is not found\n"); -+ clk_disable_unprepare(ov5640_data.sensor_clk); -+ return -ENODEV; -+ } -+ retval = ov5640_read_reg(OV5640_CHIP_ID_LOW_BYTE, &chip_id_low); -+ if (retval < 0 || chip_id_low != 0x40) { -+ pr_warning("camera ov5640_mipi is not found\n"); -+ clk_disable_unprepare(ov5640_data.sensor_clk); -+ return -ENODEV; -+ } -+ -+ sensor->virtual_channel = sensor->csi | (sensor->ipu_id << 1); -+ ov5640_standby(1); -+ -+ ov5640_int_device.priv = &ov5640_data; -+ retval = v4l2_int_device_register(&ov5640_int_device); -+ -+// clk_disable_unprepare(ov5640_data.sensor_clk); -+ -+ if (device_create_file(dev, &dev_attr_ov5640_reg)) -+ dev_err(dev, "%s: error creating ov5640_reg entry\n", __func__); -+ pr_info("camera ov5640_mipi is found\n"); -+ return retval; -+} -+ -+/*! -+ * ov5640 I2C detach function -+ * -+ * @param client struct i2c_client * -+ * @return Error code indicating success or failure -+ */ -+static int ov5640_remove(struct i2c_client *client) -+{ -+ v4l2_int_device_unregister(&ov5640_int_device); -+ -+ if (gpo_regulator) -+ regulator_disable(gpo_regulator); -+ -+ if (analog_regulator) -+ regulator_disable(analog_regulator); -+ -+ if (core_regulator) -+ regulator_disable(core_regulator); -+ -+ if (io_regulator) -+ regulator_disable(io_regulator); -+ -+ return 0; -+} -+ -+/*! -+ * ov5640 init function -+ * Called by insmod ov5640_camera.ko. -+ * -+ * @return Error code indicating success or failure -+ */ -+static __init int ov5640_init(void) -+{ -+ u8 err; -+ -+ err = i2c_add_driver(&ov5640_i2c_driver); -+ if (err != 0) -+ pr_err("%s:driver registration failed, error=%d\n", -+ __func__, err); -+ -+ return err; -+} -+ -+/*! -+ * OV5640 cleanup function -+ * Called on rmmod ov5640_camera.ko -+ * -+ * @return Error code indicating success or failure -+ */ -+static void __exit ov5640_clean(void) -+{ -+ i2c_del_driver(&ov5640_i2c_driver); -+} -+ -+module_init(ov5640_init); -+module_exit(ov5640_clean); -+ -+MODULE_AUTHOR("Freescale Semiconductor, Inc."); -+MODULE_DESCRIPTION("OV5640 MIPI Camera Driver"); -+MODULE_LICENSE("GPL"); -+MODULE_VERSION("1.0"); -+MODULE_ALIAS("CSI"); -diff -Nur linux-4.1.13.orig/drivers/media/platform/mxc/capture/ov5642.c linux-4.1.13/drivers/media/platform/mxc/capture/ov5642.c ---- linux-4.1.13.orig/drivers/media/platform/mxc/capture/ov5642.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/media/platform/mxc/capture/ov5642.c 2015-11-30 17:56:13.612135595 +0100 -@@ -0,0 +1,6294 @@ -+/* -+ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved. -+ */ -+ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "mxc_v4l2_capture.h" -+ -+#define OV5642_VOLTAGE_ANALOG 2800000 -+#define OV5642_VOLTAGE_DIGITAL_CORE 1500000 -+#define OV5642_VOLTAGE_DIGITAL_IO 1800000 -+ -+#define MIN_FPS 15 -+#define MAX_FPS 30 -+#define DEFAULT_FPS 30 -+ -+#define OV5642_XCLK_MIN 6000000 -+#define OV5642_XCLK_MAX 24000000 -+ -+/* OV5642 Camera Auto Focus Registers */ -+#define REG_CMD_MAIN 0x3024 -+#define REG_STA_FOCUS 0x3027 -+#define REG_STA_ZONE 0x3026 -+#define REG_CMD_TAG 0x3025 -+#define REG_CMD_PARA3 0x5082 -+#define REG_CMD_PARA2 0x5083 -+#define REG_CMD_PARA1 0x5084 -+#define REG_CMD_PARA0 0x5085 -+ -+ -+/* OV5642 Auto Focus Commands and Responses */ -+#define S_STARTUP 0xFA -+#define S_FIRWARE 0xFF -+#define S_STARTUP 0xFA -+#define S_ERROR 0xFE -+#define S_DRVICERR 0xEE -+#define S_IDLE 0x00 -+#define S_FOCUSING 0x01 -+#define S_FOCUSED 0x02 -+#define S_CAPTURE 0x12 -+#define S_STEP 0x20 -+ -+/*OV5642 AWB Registers*/ -+#define REG_AWB_MANUAL 0x3406 -+#define REG_AWB_R_GAIN_HIGH 0x3400 -+#define REG_AWB_R_GAIN_LOW 0x3401 -+#define REG_AWB_G_GAIN_HIGH 0x3402 -+#define REG_AWB_G_GAIN_LOW 0x3403 -+#define REG_AWB_B_GAIN_HIGH 0x3404 -+#define REG_AWB_B_GAIN_LOW 0x3405 -+ -+#define CMD_ENABLE_OVERLAY 0x01 -+#define CMD_DISABLE_OVERLAY 0x02 -+#define CMD_SINGLE_FOCUS_MODE 0x03 -+#define CMD_CONST_FOCUS_MODE 0x04 -+#define CMD_STEP_FOCUS_MODE 0x05 -+#define CMD_PAUSE 0x06 -+#define CMD_IDLE_MODE 0x08 -+#define CMD_SET_ZONE_MODE 0x10 -+#define CMD_UPDATE_ZONE_MODE 0x12 -+#define CMD_MOTOR_MODE 0x20 -+#define CMD_SCAN_MODE 0x30 -+ -+#define OV5642_CHIP_ID_HIGH_BYTE 0x300A -+#define OV5642_CHIP_ID_LOW_BYTE 0x300B -+ -+enum ov5642_mode { -+ ov5642_mode_MIN = 0, -+ ov5642_mode_VGA_640_480 = 0, -+ ov5642_mode_QVGA_320_240 = 1, -+ ov5642_mode_NTSC_720_480 = 2, -+ ov5642_mode_PAL_720_576 = 3, -+ ov5642_mode_720P_1280_720 = 4, -+ ov5642_mode_1080P_1920_1080 = 5, -+ ov5642_mode_QSXGA_2592_1944 = 6, -+ ov5642_mode_QCIF_176_144 = 7, -+ ov5642_mode_XGA_1024_768 = 8, -+ ov5642_mode_MAX = 8 -+}; -+ -+enum ov5642_frame_rate { -+ ov5642_15_fps, -+ ov5642_30_fps -+}; -+ -+static int ov5642_framerates[] = { -+ [ov5642_15_fps] = 15, -+ [ov5642_30_fps] = 30, -+}; -+ -+struct reg_value { -+ u16 u16RegAddr; -+ u8 u8Val; -+ u8 u8Mask; -+ u32 u32Delay_ms; -+}; -+ -+struct ov5642_mode_info { -+ enum ov5642_mode mode; -+ u32 width; -+ u32 height; -+ struct reg_value *init_data_ptr; -+ u32 init_data_size; -+}; -+ -+/*! -+ * Maintains the information on the current state of the sesor. -+ */ -+static struct sensor_data ov5642_data; -+static int pwn_gpio, rst_gpio; -+ -+static struct reg_value ov5642_rot_none_VGA[] = { -+ {0x3818, 0xc1, 0x00, 0x00}, {0x3621, 0x87, 0x00, 0x00}, -+}; -+ -+static struct reg_value ov5642_rot_vert_flip_VGA[] = { -+ {0x3818, 0x20, 0xbf, 0x00}, {0x3621, 0x20, 0xff, 0x00}, -+}; -+ -+static struct reg_value ov5642_rot_horiz_flip_VGA[] = { -+ {0x3818, 0x81, 0x00, 0x01}, {0x3621, 0xa7, 0x00, 0x00}, -+}; -+ -+static struct reg_value ov5642_rot_180_VGA[] = { -+ {0x3818, 0x60, 0xff, 0x00}, {0x3621, 0x00, 0xdf, 0x00}, -+}; -+ -+ -+static struct reg_value ov5642_rot_none_FULL[] = { -+ {0x3818, 0xc0, 0x00, 0x00}, {0x3621, 0x09, 0x00, 0x00}, -+}; -+ -+static struct reg_value ov5642_rot_vert_flip_FULL[] = { -+ {0x3818, 0x20, 0xbf, 0x01}, {0x3621, 0x20, 0xff, 0x00}, -+}; -+ -+static struct reg_value ov5642_rot_horiz_flip_FULL[] = { -+ {0x3818, 0x80, 0x00, 0x01}, {0x3621, 0x29, 0x00, 0x00}, -+}; -+ -+static struct reg_value ov5642_rot_180_FULL[] = { -+ {0x3818, 0x60, 0xff, 0x00}, {0x3621, 0x00, 0xdf, 0x00}, -+}; -+ -+ -+static struct reg_value ov5642_initial_setting[] = { -+ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0}, -+ {0x3018, 0xfc, 0, 0}, {0x3810, 0xc2, 0, 0}, {0x3615, 0xf0, 0, 0}, -+ {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0}, -+ {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0}, -+ {0x3006, 0x43, 0, 0}, {0x3007, 0x37, 0, 0}, {0x3011, 0x08, 0, 0}, -+ {0x3010, 0x00, 0, 0}, {0x460c, 0x22, 0, 0}, {0x3815, 0x04, 0, 0}, -+ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0}, -+ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0}, -+ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0}, -+ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0}, -+ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0}, -+ {0x3606, 0x3f, 0, 0}, {0x3c00, 0x04, 0, 0}, {0x3c01, 0x80, 0, 0}, -+ {0x5000, 0x4f, 0, 0}, {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, -+ {0x5182, 0x00, 0, 0}, {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, -+ {0x5001, 0xff, 0, 0}, {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, -+ {0x5505, 0x7f, 0, 0}, {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, -+ {0x4610, 0x00, 0, 0}, {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, -+ {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, -+ {0x380b, 0xe0, 0, 0}, {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, -+ {0x501f, 0x00, 0, 0}, {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, -+ {0x3503, 0x07, 0, 0}, {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, -+ {0x350b, 0x00, 0, 0}, {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, -+ {0x3501, 0x1e, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0}, -+ {0x380c, 0x0c, 0, 0}, {0x380d, 0x80, 0, 0}, {0x380e, 0x03, 0, 0}, -+ {0x380f, 0xe8, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, -+ {0x3818, 0xc1, 0, 0}, {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0}, -+ {0x3801, 0x80, 0, 0}, {0x3621, 0x87, 0, 0}, {0x3801, 0x50, 0, 0}, -+ {0x3803, 0x08, 0, 0}, {0x3827, 0x08, 0, 0}, {0x3810, 0x40, 0, 0}, -+ {0x3804, 0x05, 0, 0}, {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0}, -+ {0x5683, 0x00, 0, 0}, {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0}, -+ {0x5686, 0x03, 0, 0}, {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0}, -+ {0x3a1a, 0x05, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0}, -+ {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, -+ {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0}, -+ {0x350d, 0xd0, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0}, -+ {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0}, -+ {0x3503, 0x00, 0, 0}, {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0}, -+ {0x528c, 0x08, 0, 0}, {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0}, -+ {0x528f, 0x10, 0, 0}, {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0}, -+ {0x5293, 0x02, 0, 0}, {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0}, -+ {0x5296, 0x00, 0, 0}, {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0}, -+ {0x5299, 0x02, 0, 0}, {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0}, -+ {0x529c, 0x00, 0, 0}, {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0}, -+ {0x529f, 0x02, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0}, -+ {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0}, -+ {0x3a1f, 0x10, 0, 0}, {0x3030, 0x0b, 0, 0}, {0x3a02, 0x00, 0, 0}, -+ {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0}, -+ {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0}, -+ {0x5193, 0x70, 0, 0}, {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0}, -+ {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0}, -+ {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, -+ {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0}, -+ {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0}, -+ {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0}, -+ {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0}, -+ {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0}, -+ {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0}, -+ {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0}, -+ {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0}, -+ {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0}, -+ {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0}, -+ {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0}, -+ {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0}, -+ {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0}, -+ {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0}, -+ {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0}, -+ {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0}, -+ {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0}, -+ {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0}, -+ {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0}, -+ {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0}, -+ {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0}, -+ {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0}, -+ {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0}, -+ {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0}, -+ {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0}, -+ {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0}, -+ {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0}, -+ {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0}, -+ {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0}, -+ {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0}, -+ {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0}, -+ {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0}, -+ {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0}, -+ {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0}, -+ {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0}, -+ {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0}, -+ {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0}, -+ {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0}, -+ {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0}, -+ {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0}, -+ {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0}, -+ {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, -+ {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0}, -+ {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0}, -+ {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0}, -+ {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0}, -+ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, -+ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, -+ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0}, -+ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0}, -+ {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0}, -+ {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0}, -+ {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0}, -+ {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0}, -+ {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0}, -+ {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0}, -+ {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0}, -+ {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0}, -+ {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0}, -+ {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0}, -+ {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0}, -+ {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0}, -+ {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0}, -+ {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0}, -+ {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0}, -+ {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0}, -+ {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0}, -+ {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0}, -+ {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0}, -+ {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0}, -+ {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0}, -+ {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0}, -+ {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0}, -+ {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0}, -+ {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0}, -+ {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0}, -+ {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0}, -+ {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0}, -+ {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0}, -+ {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0}, -+ {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0}, -+ {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0}, -+ {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0}, -+ {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0}, -+ {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0}, -+ {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0}, -+ {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0}, -+ {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0}, -+ {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0}, -+ {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0}, -+ {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0}, -+ {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0}, -+ {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0}, -+ {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0}, -+ {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0}, -+ {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0}, -+ {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0}, -+ {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0}, -+ {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0}, -+ {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0}, -+ {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0}, -+ {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0}, -+ {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0}, -+ {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0}, -+ {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0}, -+ {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0}, -+ {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0}, -+ {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0}, -+ {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0}, -+ {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0}, -+ {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0}, -+ {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0}, -+ {0x302b, 0x00, 0, 300}, -+}; -+ -+static struct reg_value ov5642_af_firmware[] = { -+ {0x3000, 0x20, 0, 0},{0x8000, 0x02, 0, 0},{0x8001, 0x00, 0, 0}, -+ {0x8002, 0x06, 0, 0},{0x8003, 0x02, 0, 0},{0x8004, 0x0b, 0, 0}, -+ {0x8005, 0x44, 0, 0},{0x8006, 0x78, 0, 0},{0x8007, 0x7f, 0, 0}, -+ {0x8008, 0xe4, 0, 0},{0x8009, 0xf6, 0, 0},{0x800a, 0xd8, 0, 0}, -+ {0x800b, 0xfd, 0, 0},{0x800c, 0x75, 0, 0},{0x800d, 0x81, 0, 0}, -+ {0x800e, 0x7d, 0, 0},{0x800f, 0x02, 0, 0},{0x8010, 0x13, 0, 0}, -+ {0x8011, 0xb6, 0, 0},{0x8012, 0x00, 0, 0},{0x8013, 0x02, 0, 0}, -+ {0x8014, 0x12, 0, 0},{0x8015, 0xe1, 0, 0},{0x8016, 0xe0, 0, 0}, -+ {0x8017, 0xf5, 0, 0},{0x8018, 0x71, 0, 0},{0x8019, 0xa3, 0, 0}, -+ {0x801a, 0xe0, 0, 0},{0x801b, 0xf5, 0, 0},{0x801c, 0x72, 0, 0}, -+ {0x801d, 0xae, 0, 0},{0x801e, 0x69, 0, 0},{0x801f, 0xe4, 0, 0}, -+ {0x8020, 0x85, 0, 0},{0x8021, 0x6a, 0, 0},{0x8022, 0x55, 0, 0}, -+ {0x8023, 0x8e, 0, 0},{0x8024, 0x54, 0, 0},{0x8025, 0xf5, 0, 0}, -+ {0x8026, 0x53, 0, 0},{0x8027, 0xf5, 0, 0},{0x8028, 0x52, 0, 0}, -+ {0x8029, 0xab, 0, 0},{0x802a, 0x55, 0, 0},{0x802b, 0xaa, 0, 0}, -+ {0x802c, 0x54, 0, 0},{0x802d, 0xa9, 0, 0},{0x802e, 0x53, 0, 0}, -+ {0x802f, 0xa8, 0, 0},{0x8030, 0x52, 0, 0},{0x8031, 0xaf, 0, 0}, -+ {0x8032, 0x2c, 0, 0},{0x8033, 0xfc, 0, 0},{0x8034, 0xfd, 0, 0}, -+ {0x8035, 0xfe, 0, 0},{0x8036, 0x12, 0, 0},{0x8037, 0x08, 0, 0}, -+ {0x8038, 0x7f, 0, 0},{0x8039, 0x8f, 0, 0},{0x803a, 0x55, 0, 0}, -+ {0x803b, 0x8e, 0, 0},{0x803c, 0x54, 0, 0},{0x803d, 0x8d, 0, 0}, -+ {0x803e, 0x53, 0, 0},{0x803f, 0x8c, 0, 0},{0x8040, 0x52, 0, 0}, -+ {0x8041, 0xaf, 0, 0},{0x8042, 0x55, 0, 0},{0x8043, 0xae, 0, 0}, -+ {0x8044, 0x54, 0, 0},{0x8045, 0xad, 0, 0},{0x8046, 0x53, 0, 0}, -+ {0x8047, 0xac, 0, 0},{0x8048, 0x52, 0, 0},{0x8049, 0x8f, 0, 0}, -+ {0x804a, 0x2b, 0, 0},{0x804b, 0x8e, 0, 0},{0x804c, 0x2a, 0, 0}, -+ {0x804d, 0x8d, 0, 0},{0x804e, 0x29, 0, 0},{0x804f, 0x8c, 0, 0}, -+ {0x8050, 0x28, 0, 0},{0x8051, 0xae, 0, 0},{0x8052, 0x6b, 0, 0}, -+ {0x8053, 0xe4, 0, 0},{0x8054, 0x85, 0, 0},{0x8055, 0x6c, 0, 0}, -+ {0x8056, 0x55, 0, 0},{0x8057, 0x8e, 0, 0},{0x8058, 0x54, 0, 0}, -+ {0x8059, 0xf5, 0, 0},{0x805a, 0x53, 0, 0},{0x805b, 0xf5, 0, 0}, -+ {0x805c, 0x52, 0, 0},{0x805d, 0xab, 0, 0},{0x805e, 0x55, 0, 0}, -+ {0x805f, 0xaa, 0, 0},{0x8060, 0x54, 0, 0},{0x8061, 0xa9, 0, 0}, -+ {0x8062, 0x53, 0, 0},{0x8063, 0xa8, 0, 0},{0x8064, 0x52, 0, 0}, -+ {0x8065, 0xaf, 0, 0},{0x8066, 0x2d, 0, 0},{0x8067, 0xfc, 0, 0}, -+ {0x8068, 0xfd, 0, 0},{0x8069, 0xfe, 0, 0},{0x806a, 0x12, 0, 0}, -+ {0x806b, 0x08, 0, 0},{0x806c, 0x7f, 0, 0},{0x806d, 0x8f, 0, 0}, -+ {0x806e, 0x55, 0, 0},{0x806f, 0x8e, 0, 0},{0x8070, 0x54, 0, 0}, -+ {0x8071, 0x8d, 0, 0},{0x8072, 0x53, 0, 0},{0x8073, 0x8c, 0, 0}, -+ {0x8074, 0x52, 0, 0},{0x8075, 0xe5, 0, 0},{0x8076, 0x2b, 0, 0}, -+ {0x8077, 0x25, 0, 0},{0x8078, 0x55, 0, 0},{0x8079, 0xf5, 0, 0}, -+ {0x807a, 0x2b, 0, 0},{0x807b, 0xe5, 0, 0},{0x807c, 0x2a, 0, 0}, -+ {0x807d, 0x35, 0, 0},{0x807e, 0x54, 0, 0},{0x807f, 0xf5, 0, 0}, -+ {0x8080, 0x2a, 0, 0},{0x8081, 0xe5, 0, 0},{0x8082, 0x29, 0, 0}, -+ {0x8083, 0x35, 0, 0},{0x8084, 0x53, 0, 0},{0x8085, 0xf5, 0, 0}, -+ {0x8086, 0x29, 0, 0},{0x8087, 0xe5, 0, 0},{0x8088, 0x28, 0, 0}, -+ {0x8089, 0x35, 0, 0},{0x808a, 0x52, 0, 0},{0x808b, 0xf5, 0, 0}, -+ {0x808c, 0x28, 0, 0},{0x808d, 0xae, 0, 0},{0x808e, 0x6d, 0, 0}, -+ {0x808f, 0xe4, 0, 0},{0x8090, 0x85, 0, 0},{0x8091, 0x6e, 0, 0}, -+ {0x8092, 0x55, 0, 0},{0x8093, 0x8e, 0, 0},{0x8094, 0x54, 0, 0}, -+ {0x8095, 0xf5, 0, 0},{0x8096, 0x53, 0, 0},{0x8097, 0xf5, 0, 0}, -+ {0x8098, 0x52, 0, 0},{0x8099, 0xab, 0, 0},{0x809a, 0x55, 0, 0}, -+ {0x809b, 0xaa, 0, 0},{0x809c, 0x54, 0, 0},{0x809d, 0xa9, 0, 0}, -+ {0x809e, 0x53, 0, 0},{0x809f, 0xa8, 0, 0},{0x80a0, 0x52, 0, 0}, -+ {0x80a1, 0xaf, 0, 0},{0x80a2, 0x2e, 0, 0},{0x80a3, 0xfc, 0, 0}, -+ {0x80a4, 0xfd, 0, 0},{0x80a5, 0xfe, 0, 0},{0x80a6, 0x12, 0, 0}, -+ {0x80a7, 0x08, 0, 0},{0x80a8, 0x7f, 0, 0},{0x80a9, 0x8f, 0, 0}, -+ {0x80aa, 0x55, 0, 0},{0x80ab, 0x8e, 0, 0},{0x80ac, 0x54, 0, 0}, -+ {0x80ad, 0x8d, 0, 0},{0x80ae, 0x53, 0, 0},{0x80af, 0x8c, 0, 0}, -+ {0x80b0, 0x52, 0, 0},{0x80b1, 0xe5, 0, 0},{0x80b2, 0x2b, 0, 0}, -+ {0x80b3, 0x25, 0, 0},{0x80b4, 0x55, 0, 0},{0x80b5, 0xf5, 0, 0}, -+ {0x80b6, 0x2b, 0, 0},{0x80b7, 0xe5, 0, 0},{0x80b8, 0x2a, 0, 0}, -+ {0x80b9, 0x35, 0, 0},{0x80ba, 0x54, 0, 0},{0x80bb, 0xf5, 0, 0}, -+ {0x80bc, 0x2a, 0, 0},{0x80bd, 0xe5, 0, 0},{0x80be, 0x29, 0, 0}, -+ {0x80bf, 0x35, 0, 0},{0x80c0, 0x53, 0, 0},{0x80c1, 0xf5, 0, 0}, -+ {0x80c2, 0x29, 0, 0},{0x80c3, 0xe5, 0, 0},{0x80c4, 0x28, 0, 0}, -+ {0x80c5, 0x35, 0, 0},{0x80c6, 0x52, 0, 0},{0x80c7, 0xf5, 0, 0}, -+ {0x80c8, 0x28, 0, 0},{0x80c9, 0xae, 0, 0},{0x80ca, 0x6f, 0, 0}, -+ {0x80cb, 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0x80, 0, 0},{0x93f3, 0xd5, 0, 0}, -+ {0x93f4, 0x12, 0, 0},{0x93f5, 0x10, 0, 0},{0x93f6, 0x3d, 0, 0}, -+ {0x93f7, 0xd2, 0, 0},{0x93f8, 0x3c, 0, 0},{0x93f9, 0x12, 0, 0}, -+ {0x93fa, 0x0f, 0, 0},{0x93fb, 0xb0, 0, 0},{0x93fc, 0xd2, 0, 0}, -+ {0x93fd, 0x3c, 0, 0},{0x93fe, 0x12, 0, 0},{0x93ff, 0x11, 0, 0}, -+ {0x9400, 0x1a, 0, 0},{0x9401, 0xe5, 0, 0},{0x9402, 0x7b, 0, 0}, -+ {0x9403, 0xd3, 0, 0},{0x9404, 0x95, 0, 0},{0x9405, 0x7c, 0, 0}, -+ {0x9406, 0x40, 0, 0},{0x9407, 0x03, 0, 0},{0x9408, 0xd3, 0, 0}, -+ {0x9409, 0x80, 0, 0},{0x940a, 0x01, 0, 0},{0x940b, 0xc3, 0, 0}, -+ {0x940c, 0x50, 0, 0},{0x940d, 0x14, 0, 0},{0x940e, 0x20, 0, 0}, -+ {0x940f, 0x37, 0, 0},{0x9410, 0x0e, 0, 0},{0x9411, 0xe5, 0, 0}, -+ {0x9412, 0x24, 0, 0},{0x9413, 0x54, 0, 0},{0x9414, 0x1f, 0, 0}, -+ {0x9415, 0xff, 0, 0},{0x9416, 0xbf, 0, 0},{0x9417, 0x1f, 0, 0}, -+ {0x9418, 0x06, 0, 0},{0x9419, 0x30, 0, 0},{0x941a, 0x25, 0, 0}, -+ {0x941b, 0x03, 0, 0},{0x941c, 0x20, 0, 0},{0x941d, 0x26, 0, 0}, -+ {0x941e, 0x03, 0, 0},{0x941f, 0x02, 0, 0},{0x9420, 0x15, 0, 0}, -+ {0x9421, 0x2c, 0, 0},{0x9422, 0x12, 0, 0},{0x9423, 0x02, 0, 0}, -+ {0x9424, 0xb6, 0, 0},{0x9425, 0x22, 0, 0},{0x9426, 0xe5, 0, 0}, -+ {0x9427, 0x7c, 0, 0},{0x9428, 0x70, 0, 0},{0x9429, 0x19, 0, 0}, -+ {0x942a, 0x12, 0, 0},{0x942b, 0x15, 0, 0},{0x942c, 0x04, 0, 0}, -+ {0x942d, 0xc2, 0, 0},{0x942e, 0x3c, 0, 0},{0x942f, 0x12, 0, 0}, -+ {0x9430, 0x0f, 0, 0},{0x9431, 0xb0, 0, 0},{0x9432, 0xc2, 0, 0}, -+ {0x9433, 0x3c, 0, 0},{0x9434, 0x12, 0, 0},{0x9435, 0x11, 0, 0}, -+ {0x9436, 0x1a, 0, 0},{0x9437, 0xc2, 0, 0},{0x9438, 0x03, 0, 0}, -+ {0x9439, 0x12, 0, 0},{0x943a, 0x15, 0, 0},{0x943b, 0x2c, 0, 0}, -+ {0x943c, 0xd2, 0, 0},{0x943d, 0x02, 0, 0},{0x943e, 0xd2, 0, 0}, -+ {0x943f, 0x01, 0, 0},{0x9440, 0xd2, 0, 0},{0x9441, 0x00, 0, 0}, -+ {0x9442, 0x22, 0, 0},{0x9443, 0x30, 0, 0},{0x9444, 0x03, 0, 0}, -+ {0x9445, 0x08, 0, 0},{0x9446, 0xc2, 0, 0},{0x9447, 0x03, 0, 0}, -+ {0x9448, 0xc2, 0, 0},{0x9449, 0x04, 0, 0},{0x944a, 0x12, 0, 0}, -+ {0x944b, 0x02, 0, 0},{0x944c, 0xa5, 0, 0},{0x944d, 0x22, 0, 0}, -+ {0x944e, 0xe4, 0, 0},{0x944f, 0xf5, 0, 0},{0x9450, 0x0c, 0, 0}, -+ {0x9451, 0x12, 0, 0},{0x9452, 0x0f, 0, 0},{0x9453, 0x11, 0, 0}, -+ {0x9454, 0xd2, 0, 0},{0x9455, 0x03, 0, 0},{0x9456, 0x22, 0, 0}, -+ {0x9457, 0xe5, 0, 0},{0x9458, 0x20, 0, 0},{0x9459, 0x54, 0, 0}, -+ {0x945a, 0x07, 0, 0},{0x945b, 0xff, 0, 0},{0x945c, 0xbf, 0, 0}, -+ {0x945d, 0x01, 0, 0},{0x945e, 0x03, 0, 0},{0x945f, 0x02, 0, 0}, -+ {0x9460, 0x14, 0, 0},{0x9461, 0x26, 0, 0},{0x9462, 0xe5, 0, 0}, -+ {0x9463, 0x20, 0, 0},{0x9464, 0x54, 0, 0},{0x9465, 0x07, 0, 0}, -+ {0x9466, 0xff, 0, 0},{0x9467, 0xbf, 0, 0},{0x9468, 0x07, 0, 0}, -+ {0x9469, 0x03, 0, 0},{0x946a, 0x02, 0, 0},{0x946b, 0x14, 0, 0}, -+ {0x946c, 0xaa, 0, 0},{0x946d, 0xe5, 0, 0},{0x946e, 0x20, 0, 0}, -+ {0x946f, 0x54, 0, 0},{0x9470, 0x07, 0, 0},{0x9471, 0xff, 0, 0}, -+ {0x9472, 0xbf, 0, 0},{0x9473, 0x03, 0, 0},{0x9474, 0x03, 0, 0}, -+ {0x9475, 0x02, 0, 0},{0x9476, 0x13, 0, 0},{0x9477, 0xf4, 0, 0}, -+ {0x9478, 0xe5, 0, 0},{0x9479, 0x20, 0, 0},{0x947a, 0x54, 0, 0}, -+ {0x947b, 0x07, 0, 0},{0x947c, 0xff, 0, 0},{0x947d, 0xbf, 0, 0}, -+ {0x947e, 0x05, 0, 0},{0x947f, 0x03, 0, 0},{0x9480, 0x12, 0, 0}, -+ {0x9481, 0x15, 0, 0},{0x9482, 0x6a, 0, 0},{0x9483, 0x22, 0, 0}, -+ {0x9484, 0x12, 0, 0},{0x9485, 0x13, 0, 0},{0x9486, 0x2b, 0, 0}, -+ {0x9487, 0x12, 0, 0},{0x9488, 0x15, 0, 0},{0x9489, 0x78, 0, 0}, -+ {0x948a, 0x50, 0, 0},{0x948b, 0x04, 0, 0},{0x948c, 0xd2, 0, 0}, -+ {0x948d, 0x05, 0, 0},{0x948e, 0x80, 0, 0},{0x948f, 0x02, 0, 0}, -+ {0x9490, 0xc2, 0, 0},{0x9491, 0x05, 0, 0},{0x9492, 0x12, 0, 0}, -+ {0x9493, 0x02, 0, 0},{0x9494, 0x40, 0, 0},{0x9495, 0xc2, 0, 0}, -+ {0x9496, 0x37, 0, 0},{0x9497, 0xc2, 0, 0},{0x9498, 0x31, 0, 0}, -+ {0x9499, 0xd2, 0, 0},{0x949a, 0x34, 0, 0},{0x949b, 0x12, 0, 0}, -+ {0x949c, 0x02, 0, 0},{0x949d, 0x85, 0, 0},{0x949e, 0xb5, 0, 0}, -+ {0x949f, 0x07, 0, 0},{0x94a0, 0x03, 0, 0},{0x94a1, 0xd3, 0, 0}, -+ {0x94a2, 0x80, 0, 0},{0x94a3, 0x01, 0, 0},{0x94a4, 0xc3, 0, 0}, -+ {0x94a5, 0x40, 0, 0},{0x94a6, 0x02, 0, 0},{0x94a7, 0xc2, 0, 0}, -+ {0x94a8, 0x05, 0, 0},{0x94a9, 0x22, 0, 0},{0x94aa, 0x12, 0, 0}, -+ {0x94ab, 0x10, 0, 0},{0x94ac, 0x3d, 0, 0},{0x94ad, 0xd2, 0, 0}, -+ {0x94ae, 0x3c, 0, 0},{0x94af, 0x12, 0, 0},{0x94b0, 0x0f, 0, 0}, -+ {0x94b1, 0xb0, 0, 0},{0x94b2, 0xd2, 0, 0},{0x94b3, 0x3c, 0, 0}, -+ {0x94b4, 0x12, 0, 0},{0x94b5, 0x11, 0, 0},{0x94b6, 0x1a, 0, 0}, -+ {0x94b7, 0x12, 0, 0},{0x94b8, 0x15, 0, 0},{0x94b9, 0x2c, 0, 0}, -+ {0x94ba, 0xe5, 0, 0},{0x94bb, 0x32, 0, 0},{0x94bc, 0xd3, 0, 0}, -+ {0x94bd, 0x95, 0, 0},{0x94be, 0x7c, 0, 0},{0x94bf, 0x40, 0, 0}, -+ {0x94c0, 0x05, 0, 0},{0x94c1, 0xe4, 0, 0},{0x94c2, 0x95, 0, 0}, -+ {0x94c3, 0x7c, 0, 0},{0x94c4, 0x40, 0, 0},{0x94c5, 0x06, 0, 0}, -+ {0x94c6, 0xc2, 0, 0},{0x94c7, 0x02, 0, 0},{0x94c8, 0xd2, 0, 0}, -+ {0x94c9, 0x01, 0, 0},{0x94ca, 0xd2, 0, 0},{0x94cb, 0x00, 0, 0}, -+ {0x94cc, 0x22, 0, 0},{0x94cd, 0xe4, 0, 0},{0x94ce, 0xff, 0, 0}, -+ {0x94cf, 0xfe, 0, 0},{0x94d0, 0xc3, 0, 0},{0x94d1, 0xef, 0, 0}, -+ {0x94d2, 0x95, 0, 0},{0x94d3, 0x11, 0, 0},{0x94d4, 0xee, 0, 0}, -+ {0x94d5, 0x95, 0, 0},{0x94d6, 0x10, 0, 0},{0x94d7, 0x50, 0, 0}, -+ {0x94d8, 0x15, 0, 0},{0x94d9, 0x7d, 0, 0},{0x94da, 0x8a, 0, 0}, -+ {0x94db, 0x7c, 0, 0},{0x94dc, 0x02, 0, 0},{0x94dd, 0xed, 0, 0}, -+ {0x94de, 0x1d, 0, 0},{0x94df, 0xaa, 0, 0},{0x94e0, 0x04, 0, 0}, -+ {0x94e1, 0x70, 0, 0},{0x94e2, 0x01, 0, 0},{0x94e3, 0x1c, 0, 0}, -+ {0x94e4, 0x4a, 0, 0},{0x94e5, 0x70, 0, 0},{0x94e6, 0xf6, 0, 0}, -+ {0x94e7, 0x0f, 0, 0},{0x94e8, 0xbf, 0, 0},{0x94e9, 0x00, 0, 0}, -+ {0x94ea, 0x01, 0, 0},{0x94eb, 0x0e, 0, 0},{0x94ec, 0x80, 0, 0}, -+ {0x94ed, 0xe2, 0, 0},{0x94ee, 0x22, 0, 0},{0x94ef, 0x75, 0, 0}, -+ {0x94f0, 0x48, 0, 0},{0x94f1, 0x11, 0, 0},{0x94f2, 0x75, 0, 0}, -+ {0x94f3, 0x49, 0, 0},{0x94f4, 0xe0, 0, 0},{0x94f5, 0x90, 0, 0}, -+ {0x94f6, 0x11, 0, 0},{0x94f7, 0xde, 0, 0},{0x94f8, 0xe4, 0, 0}, -+ {0x94f9, 0x93, 0, 0},{0x94fa, 0xf5, 0, 0},{0x94fb, 0x7b, 0, 0}, -+ {0x94fc, 0xa3, 0, 0},{0x94fd, 0xe4, 0, 0},{0x94fe, 0x93, 0, 0}, -+ {0x94ff, 0xf5, 0, 0},{0x9500, 0x32, 0, 0},{0x9501, 0xc2, 0, 0}, -+ {0x9502, 0x38, 0, 0},{0x9503, 0x22, 0, 0},{0x9504, 0xe4, 0, 0}, -+ {0x9505, 0xff, 0, 0},{0x9506, 0xef, 0, 0},{0x9507, 0x25, 0, 0}, -+ {0x9508, 0xe0, 0, 0},{0x9509, 0x24, 0, 0},{0x950a, 0x56, 0, 0}, -+ {0x950b, 0xf8, 0, 0},{0x950c, 0xe4, 0, 0},{0x950d, 0xf6, 0, 0}, -+ {0x950e, 0x08, 0, 0},{0x950f, 0xf6, 0, 0},{0x9510, 0x0f, 0, 0}, -+ {0x9511, 0xbf, 0, 0},{0x9512, 0x07, 0, 0},{0x9513, 0xf2, 0, 0}, -+ {0x9514, 0x53, 0, 0},{0x9515, 0x24, 0, 0},{0x9516, 0x80, 0, 0}, -+ {0x9517, 0x22, 0, 0},{0x9518, 0xc2, 0, 0},{0x9519, 0x03, 0, 0}, -+ {0x951a, 0xd2, 0, 0},{0x951b, 0x04, 0, 0},{0x951c, 0x12, 0, 0}, -+ {0x951d, 0x02, 0, 0},{0x951e, 0xa5, 0, 0},{0x951f, 0xc2, 0, 0}, -+ {0x9520, 0x3c, 0, 0},{0x9521, 0x12, 0, 0},{0x9522, 0x0f, 0, 0}, -+ {0x9523, 0xb0, 0, 0},{0x9524, 0xc2, 0, 0},{0x9525, 0x3c, 0, 0}, -+ {0x9526, 0x12, 0, 0},{0x9527, 0x11, 0, 0},{0x9528, 0x1a, 0, 0}, -+ {0x9529, 0xd2, 0, 0},{0x952a, 0x34, 0, 0},{0x952b, 0x22, 0, 0}, -+ {0x952c, 0xe5, 0, 0},{0x952d, 0x7c, 0, 0},{0x952e, 0xc3, 0, 0}, -+ {0x952f, 0x95, 0, 0},{0x9530, 0x7b, 0, 0},{0x9531, 0x40, 0, 0}, -+ {0x9532, 0x01, 0, 0},{0x9533, 0x22, 0, 0},{0x9534, 0xe5, 0, 0}, -+ {0x9535, 0x7c, 0, 0},{0x9536, 0x04, 0, 0},{0x9537, 0xf5, 0, 0}, -+ {0x9538, 0x0c, 0, 0},{0x9539, 0x12, 0, 0},{0x953a, 0x0f, 0, 0}, -+ {0x953b, 0x11, 0, 0},{0x953c, 0x22, 0, 0},{0x953d, 0xe5, 0, 0}, -+ {0x953e, 0x7c, 0, 0},{0x953f, 0x70, 0, 0},{0x9540, 0x02, 0, 0}, -+ {0x9541, 0xc3, 0, 0},{0x9542, 0x22, 0, 0},{0x9543, 0xe5, 0, 0}, -+ {0x9544, 0x7c, 0, 0},{0x9545, 0x14, 0, 0},{0x9546, 0xf5, 0, 0}, -+ {0x9547, 0x0c, 0, 0},{0x9548, 0x12, 0, 0},{0x9549, 0x0f, 0, 0}, -+ {0x954a, 0x11, 0, 0},{0x954b, 0x22, 0, 0},{0x954c, 0xe5, 0, 0}, -+ {0x954d, 0x7d, 0, 0},{0x954e, 0xb4, 0, 0},{0x954f, 0x01, 0, 0}, -+ {0x9550, 0x09, 0, 0},{0x9551, 0x12, 0, 0},{0x9552, 0x14, 0, 0}, -+ {0x9553, 0xef, 0, 0},{0x9554, 0xe4, 0, 0},{0x9555, 0xf5, 0, 0}, -+ {0x9556, 0x0c, 0, 0},{0x9557, 0x12, 0, 0},{0x9558, 0x0f, 0, 0}, -+ {0x9559, 0x11, 0, 0},{0x955a, 0x22, 0, 0},{0x955b, 0xe5, 0, 0}, -+ {0x955c, 0x7d, 0, 0},{0x955d, 0x24, 0, 0},{0x955e, 0xfe, 0, 0}, -+ {0x955f, 0x60, 0, 0},{0x9560, 0x06, 0, 0},{0x9561, 0x04, 0, 0}, -+ {0x9562, 0x70, 0, 0},{0x9563, 0x05, 0, 0},{0x9564, 0xd2, 0, 0}, -+ {0x9565, 0x37, 0, 0},{0x9566, 0x22, 0, 0},{0x9567, 0xc2, 0, 0}, -+ {0x9568, 0x37, 0, 0},{0x9569, 0x22, 0, 0},{0x956a, 0xe5, 0, 0}, -+ {0x956b, 0x31, 0, 0},{0x956c, 0xd3, 0, 0},{0x956d, 0x94, 0, 0}, -+ {0x956e, 0x00, 0, 0},{0x956f, 0x40, 0, 0},{0x9570, 0x03, 0, 0}, -+ {0x9571, 0x15, 0, 0},{0x9572, 0x31, 0, 0},{0x9573, 0x22, 0, 0}, -+ {0x9574, 0x12, 0, 0},{0x9575, 0x15, 0, 0},{0x9576, 0x18, 0, 0}, -+ {0x9577, 0x22, 0, 0},{0x9578, 0x12, 0, 0},{0x9579, 0x14, 0, 0}, -+ {0x957a, 0xef, 0, 0},{0x957b, 0xe4, 0, 0},{0x957c, 0xf5, 0, 0}, -+ {0x957d, 0x0c, 0, 0},{0x957e, 0x12, 0, 0},{0x957f, 0x0f, 0, 0}, -+ {0x9580, 0x11, 0, 0},{0x9581, 0x22, 0, 0},{0x3024, 0x00, 0, 0}, -+ {0x3025, 0x00, 0, 0},{0x5082, 0x00, 0, 0},{0x5083, 0x00, 0, 0}, -+ {0x5084, 0x00, 0, 0},{0x5085, 0x00, 0, 0},{0x3026, 0x00, 0, 0}, -+ {0x3027, 0xFF, 0, 0},{0x3000, 0x00, 0, 0}, -+}; -+ -+static struct reg_value ov5642_setting_15fps_QCIF_176_144[] = { -+ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0}, -+ {0x3018, 0xfc, 0, 0}, {0x3810, 0xc2, 0, 0}, {0x3615, 0xf0, 0, 0}, -+ {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0}, -+ {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0}, -+ {0x3006, 0x43, 0, 0}, {0x3007, 0x37, 0, 0}, {0x3011, 0x08, 0, 0}, -+ {0x3010, 0x10, 0, 0}, {0x460c, 0x22, 0, 0}, {0x3815, 0x04, 0, 0}, -+ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0}, -+ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0}, -+ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0}, -+ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0}, -+ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0}, -+ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0}, -+ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0}, -+ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0}, -+ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0}, -+ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0}, -+ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0}, -+ {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, -+ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0}, -+ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0}, -+ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0}, -+ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3501, 0x1e, 0, 0}, -+ {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0}, {0x380c, 0x0c, 0, 0}, -+ {0x380d, 0x80, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xe8, 0, 0}, -+ {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, {0x3818, 0xc1, 0, 0}, -+ {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0}, {0x3801, 0x80, 0, 0}, -+ {0x3621, 0x87, 0, 0}, {0x3801, 0x50, 0, 0}, {0x3803, 0x08, 0, 0}, -+ {0x3827, 0x08, 0, 0}, {0x3810, 0x40, 0, 0}, {0x3804, 0x05, 0, 0}, -+ {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0}, {0x5683, 0x00, 0, 0}, -+ {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0}, {0x5686, 0x03, 0, 0}, -+ {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0}, {0x3a1a, 0x05, 0, 0}, -+ {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0}, {0x3a19, 0x7c, 0, 0}, -+ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0}, -+ {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0}, {0x350d, 0xd0, 0, 0}, -+ {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0}, {0x3502, 0x00, 0, 0}, -+ {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0}, {0x3503, 0x00, 0, 0}, -+ {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, -+ {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0}, {0x528f, 0x10, 0, 0}, -+ {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x02, 0, 0}, -+ {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0}, {0x5296, 0x00, 0, 0}, -+ {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x02, 0, 0}, -+ {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0}, {0x529c, 0x00, 0, 0}, -+ {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x02, 0, 0}, -+ {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3c, 0, 0}, -+ {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0}, {0x3a1f, 0x10, 0, 0}, -+ {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0}, {0x3a03, 0x7d, 0, 0}, -+ {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0}, {0x3a15, 0x7d, 0, 0}, -+ {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0}, {0x3a08, 0x09, 0, 0}, -+ {0x3a09, 0x60, 0, 0}, {0x3a0a, 0x07, 0, 0}, {0x3a0b, 0xd0, 0, 0}, -+ {0x3a0d, 0x08, 0, 0}, {0x3a0e, 0x06, 0, 0}, {0x5193, 0x70, 0, 0}, -+ {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0}, {0x401e, 0x20, 0, 0}, -+ {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0}, {0x528a, 0x01, 0, 0}, -+ {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, {0x528d, 0x10, 0, 0}, -+ {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0}, {0x5290, 0x30, 0, 0}, -+ {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0}, {0x5294, 0x00, 0, 0}, -+ {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0}, {0x5297, 0x08, 0, 0}, -+ {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0}, {0x529a, 0x00, 0, 0}, -+ {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0}, {0x529d, 0x28, 0, 0}, -+ {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0}, {0x5282, 0x00, 0, 0}, -+ {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0}, {0x5302, 0x00, 0, 0}, -+ {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0}, {0x530d, 0x0c, 0, 0}, -+ {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0}, {0x5310, 0x20, 0, 0}, -+ {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0}, {0x5309, 0x40, 0, 0}, -+ {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0}, {0x5306, 0x00, 0, 0}, -+ {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0}, {0x5315, 0x20, 0, 0}, -+ {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0}, {0x5317, 0x00, 0, 0}, -+ {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0}, {0x5381, 0x00, 0, 0}, -+ {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0}, {0x5384, 0x00, 0, 0}, -+ {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0}, {0x5387, 0x00, 0, 0}, -+ {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0}, {0x538a, 0x00, 0, 0}, -+ {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0}, {0x538d, 0x00, 0, 0}, -+ {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0}, {0x5390, 0x00, 0, 0}, -+ {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0}, {0x5393, 0xa2, 0, 0}, -+ {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0}, {0x5481, 0x21, 0, 0}, -+ {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0}, {0x5484, 0x65, 0, 0}, -+ {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0}, {0x5487, 0x87, 0, 0}, -+ {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0}, {0x548a, 0xaa, 0, 0}, -+ {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0}, {0x548d, 0xdd, 0, 0}, -+ {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0}, {0x5490, 0x05, 0, 0}, -+ {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0}, {0x5493, 0x20, 0, 0}, -+ {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0}, {0x5496, 0x02, 0, 0}, -+ {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0}, {0x5499, 0x86, 0, 0}, -+ {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0}, {0x549c, 0x02, 0, 0}, -+ {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0}, {0x549f, 0x1c, 0, 0}, -+ {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0}, {0x54a2, 0x01, 0, 0}, -+ {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0}, {0x54a5, 0xc5, 0, 0}, -+ {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0}, {0x54a8, 0x01, 0, 0}, -+ {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0}, {0x54ab, 0x41, 0, 0}, -+ {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0}, {0x54ae, 0x00, 0, 0}, -+ {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0}, {0x54b1, 0x20, 0, 0}, -+ {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0}, {0x54b4, 0x00, 0, 0}, -+ {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0}, {0x54b7, 0xdf, 0, 0}, -+ {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0}, {0x3406, 0x00, 0, 0}, -+ {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0}, {0x5182, 0x11, 0, 0}, -+ {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, {0x5185, 0x24, 0, 0}, -+ {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0}, {0x5188, 0x08, 0, 0}, -+ {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0}, {0x518b, 0xb2, 0, 0}, -+ {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0}, {0x518e, 0x3d, 0, 0}, -+ {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0}, {0x5191, 0xf8, 0, 0}, -+ {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, {0x5194, 0xf0, 0, 0}, -+ {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, {0x5197, 0x01, 0, 0}, -+ {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0}, {0x519a, 0x04, 0, 0}, -+ {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0}, {0x519d, 0x82, 0, 0}, -+ {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0}, {0x3a0f, 0x38, 0, 0}, -+ {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0}, {0x3a1e, 0x2e, 0, 0}, -+ {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0}, {0x5688, 0xa6, 0, 0}, -+ {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0}, {0x568b, 0xae, 0, 0}, -+ {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0}, {0x568e, 0x62, 0, 0}, -+ {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0}, {0x5584, 0x40, 0, 0}, -+ {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0}, {0x5800, 0x27, 0, 0}, -+ {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0}, {0x5803, 0x0f, 0, 0}, -+ {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0}, {0x5806, 0x1e, 0, 0}, -+ {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0}, {0x5809, 0x0d, 0, 0}, -+ {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0}, {0x580c, 0x0a, 0, 0}, -+ {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0}, {0x580f, 0x19, 0, 0}, -+ {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0}, {0x5812, 0x04, 0, 0}, -+ {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0}, {0x5815, 0x06, 0, 0}, -+ {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0}, {0x5818, 0x0a, 0, 0}, -+ {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0}, {0x581b, 0x00, 0, 0}, -+ {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0}, {0x581e, 0x08, 0, 0}, -+ {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0}, {0x5821, 0x05, 0, 0}, -+ {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0}, {0x5824, 0x00, 0, 0}, -+ {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0}, {0x5827, 0x0c, 0, 0}, -+ {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0}, {0x582a, 0x06, 0, 0}, -+ {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0}, {0x582d, 0x07, 0, 0}, -+ {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0}, {0x5830, 0x18, 0, 0}, -+ {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0}, {0x5833, 0x0a, 0, 0}, -+ {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0}, {0x5836, 0x15, 0, 0}, -+ {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0}, {0x5839, 0x1f, 0, 0}, -+ {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0}, {0x583c, 0x17, 0, 0}, -+ {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0}, {0x583f, 0x53, 0, 0}, -+ {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0}, {0x5842, 0x0d, 0, 0}, -+ {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0}, {0x5845, 0x09, 0, 0}, -+ {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0}, {0x5848, 0x10, 0, 0}, -+ {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0}, {0x584b, 0x0e, 0, 0}, -+ {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0}, {0x584e, 0x11, 0, 0}, -+ {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0}, {0x5851, 0x0c, 0, 0}, -+ {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0}, {0x5854, 0x10, 0, 0}, -+ {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0}, {0x5857, 0x0b, 0, 0}, -+ {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0}, {0x585a, 0x0d, 0, 0}, -+ {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0}, {0x585d, 0x0c, 0, 0}, -+ {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0}, {0x5860, 0x0c, 0, 0}, -+ {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0}, {0x5863, 0x08, 0, 0}, -+ {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0}, {0x5866, 0x18, 0, 0}, -+ {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0}, {0x5869, 0x19, 0, 0}, -+ {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0}, {0x586c, 0x13, 0, 0}, -+ {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0}, {0x586f, 0x16, 0, 0}, -+ {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0}, {0x5872, 0x10, 0, 0}, -+ {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0}, {0x5875, 0x16, 0, 0}, -+ {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0}, {0x5878, 0x10, 0, 0}, -+ {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0}, {0x587b, 0x14, 0, 0}, -+ {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0}, {0x587e, 0x11, 0, 0}, -+ {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0}, {0x5881, 0x15, 0, 0}, -+ {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0}, {0x5884, 0x15, 0, 0}, -+ {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0}, {0x5887, 0x17, 0, 0}, -+ {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0}, {0x3702, 0x10, 0, 0}, -+ {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0}, {0x370b, 0x40, 0, 0}, -+ {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0}, {0x3632, 0x52, 0, 0}, -+ {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0}, {0x5785, 0x07, 0, 0}, -+ {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0}, {0x3604, 0x48, 0, 0}, -+ {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0}, {0x370f, 0xc0, 0, 0}, -+ {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0}, {0x5007, 0x00, 0, 0}, -+ {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0}, {0x5013, 0x00, 0, 0}, -+ {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0}, {0x5087, 0x00, 0, 0}, -+ {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0}, {0x302b, 0x00, 0, 0}, -+ {0x3808, 0x00, 0, 0}, {0x3809, 0xb0, 0, 0}, {0x380a, 0x00, 0, 0}, -+ {0x380b, 0x90, 0, 0}, {0x3a00, 0x78, 0, 0}, -+}; -+ -+static struct reg_value ov5642_setting_30fps_QCIF_176_144[] = { -+ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0}, -+ {0x3018, 0xfc, 0, 0}, {0x3810, 0xc2, 0, 0}, {0x3615, 0xf0, 0, 0}, -+ {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0}, -+ {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0}, -+ {0x3006, 0x43, 0, 0}, {0x3007, 0x37, 0, 0}, {0x3011, 0x10, 0, 0}, -+ {0x3010, 0x10, 0, 0}, {0x460c, 0x22, 0, 0}, {0x3815, 0x04, 0, 0}, -+ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0}, -+ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0}, -+ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0}, -+ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0}, -+ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0}, -+ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0}, -+ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0}, -+ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0}, -+ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0}, -+ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0}, -+ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0}, -+ {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, -+ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0}, -+ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0}, -+ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0}, -+ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3501, 0x1e, 0, 0}, -+ {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0}, {0x380c, 0x0c, 0, 0}, -+ {0x380d, 0x80, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xe8, 0, 0}, -+ {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, {0x3818, 0xc1, 0, 0}, -+ {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0}, {0x3801, 0x80, 0, 0}, -+ {0x3621, 0x87, 0, 0}, {0x3801, 0x50, 0, 0}, {0x3803, 0x08, 0, 0}, -+ {0x3827, 0x08, 0, 0}, {0x3810, 0x40, 0, 0}, {0x3804, 0x05, 0, 0}, -+ {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0}, {0x5683, 0x00, 0, 0}, -+ {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0}, {0x5686, 0x03, 0, 0}, -+ {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0}, {0x3a1a, 0x05, 0, 0}, -+ {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0}, {0x3a19, 0x7c, 0, 0}, -+ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0}, -+ {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0}, {0x350d, 0xd0, 0, 0}, -+ {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0}, {0x3502, 0x00, 0, 0}, -+ {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0}, {0x3503, 0x00, 0, 0}, -+ {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, -+ {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0}, {0x528f, 0x10, 0, 0}, -+ {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x02, 0, 0}, -+ {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0}, {0x5296, 0x00, 0, 0}, -+ {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x02, 0, 0}, -+ {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0}, {0x529c, 0x00, 0, 0}, -+ {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x02, 0, 0}, -+ {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3c, 0, 0}, -+ {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0}, {0x3a1f, 0x10, 0, 0}, -+ {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0}, {0x3a03, 0x7d, 0, 0}, -+ {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0}, {0x3a15, 0x7d, 0, 0}, -+ {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0}, {0x3a08, 0x09, 0, 0}, -+ {0x3a09, 0x60, 0, 0}, {0x3a0a, 0x07, 0, 0}, {0x3a0b, 0xd0, 0, 0}, -+ {0x3a0d, 0x08, 0, 0}, {0x3a0e, 0x06, 0, 0}, {0x5193, 0x70, 0, 0}, -+ {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0}, {0x401e, 0x20, 0, 0}, -+ {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0}, {0x528a, 0x01, 0, 0}, -+ {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, {0x528d, 0x10, 0, 0}, -+ {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0}, {0x5290, 0x30, 0, 0}, -+ {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0}, {0x5294, 0x00, 0, 0}, -+ {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0}, {0x5297, 0x08, 0, 0}, -+ {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0}, {0x529a, 0x00, 0, 0}, -+ {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0}, {0x529d, 0x28, 0, 0}, -+ {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0}, {0x5282, 0x00, 0, 0}, -+ {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0}, {0x5302, 0x00, 0, 0}, -+ {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0}, {0x530d, 0x0c, 0, 0}, -+ {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0}, {0x5310, 0x20, 0, 0}, -+ {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0}, {0x5309, 0x40, 0, 0}, -+ {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0}, {0x5306, 0x00, 0, 0}, -+ {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0}, {0x5315, 0x20, 0, 0}, -+ {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0}, {0x5317, 0x00, 0, 0}, -+ {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0}, {0x5381, 0x00, 0, 0}, -+ {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0}, {0x5384, 0x00, 0, 0}, -+ {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0}, {0x5387, 0x00, 0, 0}, -+ {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0}, {0x538a, 0x00, 0, 0}, -+ {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0}, {0x538d, 0x00, 0, 0}, -+ {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0}, {0x5390, 0x00, 0, 0}, -+ {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0}, {0x5393, 0xa2, 0, 0}, -+ {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0}, {0x5481, 0x21, 0, 0}, -+ {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0}, {0x5484, 0x65, 0, 0}, -+ {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0}, {0x5487, 0x87, 0, 0}, -+ {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0}, {0x548a, 0xaa, 0, 0}, -+ {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0}, {0x548d, 0xdd, 0, 0}, -+ {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0}, {0x5490, 0x05, 0, 0}, -+ {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0}, {0x5493, 0x20, 0, 0}, -+ {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0}, {0x5496, 0x02, 0, 0}, -+ {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0}, {0x5499, 0x86, 0, 0}, -+ {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0}, {0x549c, 0x02, 0, 0}, -+ {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0}, {0x549f, 0x1c, 0, 0}, -+ {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0}, {0x54a2, 0x01, 0, 0}, -+ {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0}, {0x54a5, 0xc5, 0, 0}, -+ {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0}, {0x54a8, 0x01, 0, 0}, -+ {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0}, {0x54ab, 0x41, 0, 0}, -+ {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0}, {0x54ae, 0x00, 0, 0}, -+ {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0}, {0x54b1, 0x20, 0, 0}, -+ {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0}, {0x54b4, 0x00, 0, 0}, -+ {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0}, {0x54b7, 0xdf, 0, 0}, -+ {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0}, {0x3406, 0x00, 0, 0}, -+ {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0}, {0x5182, 0x11, 0, 0}, -+ {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, {0x5185, 0x24, 0, 0}, -+ {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0}, {0x5188, 0x08, 0, 0}, -+ {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0}, {0x518b, 0xb2, 0, 0}, -+ {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0}, {0x518e, 0x3d, 0, 0}, -+ {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0}, {0x5191, 0xf8, 0, 0}, -+ {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, {0x5194, 0xf0, 0, 0}, -+ {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, {0x5197, 0x01, 0, 0}, -+ {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0}, {0x519a, 0x04, 0, 0}, -+ {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0}, {0x519d, 0x82, 0, 0}, -+ {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0}, {0x3a0f, 0x38, 0, 0}, -+ {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0}, {0x3a1e, 0x2e, 0, 0}, -+ {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0}, {0x5688, 0xa6, 0, 0}, -+ {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0}, {0x568b, 0xae, 0, 0}, -+ {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0}, {0x568e, 0x62, 0, 0}, -+ {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0}, {0x5584, 0x40, 0, 0}, -+ {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0}, {0x5800, 0x27, 0, 0}, -+ {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0}, {0x5803, 0x0f, 0, 0}, -+ {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0}, {0x5806, 0x1e, 0, 0}, -+ {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0}, {0x5809, 0x0d, 0, 0}, -+ {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0}, {0x580c, 0x0a, 0, 0}, -+ {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0}, {0x580f, 0x19, 0, 0}, -+ {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0}, {0x5812, 0x04, 0, 0}, -+ {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0}, {0x5815, 0x06, 0, 0}, -+ {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0}, {0x5818, 0x0a, 0, 0}, -+ {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0}, {0x581b, 0x00, 0, 0}, -+ {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0}, {0x581e, 0x08, 0, 0}, -+ {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0}, {0x5821, 0x05, 0, 0}, -+ {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0}, {0x5824, 0x00, 0, 0}, -+ {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0}, {0x5827, 0x0c, 0, 0}, -+ {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0}, {0x582a, 0x06, 0, 0}, -+ {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0}, {0x582d, 0x07, 0, 0}, -+ {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0}, {0x5830, 0x18, 0, 0}, -+ {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0}, {0x5833, 0x0a, 0, 0}, -+ {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0}, {0x5836, 0x15, 0, 0}, -+ {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0}, {0x5839, 0x1f, 0, 0}, -+ {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0}, {0x583c, 0x17, 0, 0}, -+ {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0}, {0x583f, 0x53, 0, 0}, -+ {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0}, {0x5842, 0x0d, 0, 0}, -+ {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0}, {0x5845, 0x09, 0, 0}, -+ {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0}, {0x5848, 0x10, 0, 0}, -+ {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0}, {0x584b, 0x0e, 0, 0}, -+ {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0}, {0x584e, 0x11, 0, 0}, -+ {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0}, {0x5851, 0x0c, 0, 0}, -+ {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0}, {0x5854, 0x10, 0, 0}, -+ {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0}, {0x5857, 0x0b, 0, 0}, -+ {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0}, {0x585a, 0x0d, 0, 0}, -+ {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0}, {0x585d, 0x0c, 0, 0}, -+ {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0}, {0x5860, 0x0c, 0, 0}, -+ {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0}, {0x5863, 0x08, 0, 0}, -+ {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0}, {0x5866, 0x18, 0, 0}, -+ {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0}, {0x5869, 0x19, 0, 0}, -+ {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0}, {0x586c, 0x13, 0, 0}, -+ {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0}, {0x586f, 0x16, 0, 0}, -+ {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0}, {0x5872, 0x10, 0, 0}, -+ {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0}, {0x5875, 0x16, 0, 0}, -+ {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0}, {0x5878, 0x10, 0, 0}, -+ {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0}, {0x587b, 0x14, 0, 0}, -+ {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0}, {0x587e, 0x11, 0, 0}, -+ {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0}, {0x5881, 0x15, 0, 0}, -+ {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0}, {0x5884, 0x15, 0, 0}, -+ {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0}, {0x5887, 0x17, 0, 0}, -+ {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0}, {0x3702, 0x10, 0, 0}, -+ {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0}, {0x370b, 0x40, 0, 0}, -+ {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0}, {0x3632, 0x52, 0, 0}, -+ {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0}, {0x5785, 0x07, 0, 0}, -+ {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0}, {0x3604, 0x48, 0, 0}, -+ {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0}, {0x370f, 0xc0, 0, 0}, -+ {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0}, {0x5007, 0x00, 0, 0}, -+ {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0}, {0x5013, 0x00, 0, 0}, -+ {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0}, {0x5087, 0x00, 0, 0}, -+ {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0}, {0x302b, 0x00, 0, 0}, -+ {0x3808, 0x00, 0, 0}, {0x3809, 0xb0, 0, 0}, {0x380a, 0x00, 0, 0}, -+ {0x380b, 0x90, 0, 0}, {0x3a00, 0x78, 0, 0}, -+}; -+ -+static struct reg_value ov5642_setting_15fps_QSXGA_2592_1944[] = { -+ {0x3503, 0x07, 0, 0}, {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0}, -+ {0x3002, 0x00, 0, 0}, {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, -+ {0x3005, 0xff, 0, 0}, {0x3006, 0xff, 0, 0}, {0x3007, 0x3f, 0, 0}, -+ {0x3011, 0x08, 0, 0}, {0x3010, 0x10, 0, 0}, {0x3818, 0xc0, 0, 0}, -+ {0x3621, 0x09, 0, 0}, {0x350c, 0x07, 0, 0}, {0x350d, 0xd0, 0, 0}, -+ {0x3602, 0xe4, 0, 0}, {0x3612, 0xac, 0, 0}, {0x3613, 0x44, 0, 0}, -+ {0x3622, 0x60, 0, 0}, {0x3623, 0x22, 0, 0}, {0x3604, 0x48, 0, 0}, -+ {0x3705, 0xda, 0, 0}, {0x370a, 0x80, 0, 0}, {0x3801, 0x95, 0, 0}, -+ {0x3803, 0x0e, 0, 0}, {0x3804, 0x0a, 0, 0}, {0x3805, 0x20, 0, 0}, -+ {0x3806, 0x07, 0, 0}, {0x3807, 0x98, 0, 0}, {0x3808, 0x0a, 0, 0}, -+ {0x3809, 0x20, 0, 0}, {0x380a, 0x07, 0, 0}, {0x380b, 0x98, 0, 0}, -+ {0x380c, 0x0c, 0, 0}, {0x380d, 0x80, 0, 0}, {0x380e, 0x07, 0, 0}, -+ {0x380f, 0xd0, 0, 0}, {0x3810, 0xc2, 0, 0}, {0x3815, 0x44, 0, 0}, -+ {0x3824, 0x11, 0, 0}, {0x3825, 0xac, 0, 0}, {0x3827, 0x0c, 0, 0}, -+ {0x3a00, 0x78, 0, 0}, {0x3a0d, 0x10, 0, 0}, {0x3a0e, 0x0d, 0, 0}, -+ {0x5682, 0x0a, 0, 0}, {0x5683, 0x20, 0, 0}, {0x5686, 0x07, 0, 0}, -+ {0x5687, 0x98, 0, 0}, {0x5001, 0xff, 0, 0}, {0x589b, 0x00, 0, 0}, -+ {0x589a, 0xc0, 0, 0}, {0x4407, 0x04, 0, 0}, {0x3008, 0x02, 0, 0}, -+ {0x460b, 0x37, 0, 0}, {0x460c, 0x22, 0, 0}, {0x471d, 0x05, 0, 0}, -+ {0x4713, 0x03, 0, 0}, {0x471c, 0xd0, 0, 0}, {0x3815, 0x01, 0, 0}, -+ {0x501f, 0x00, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3819, 0x80, 0, 0}, -+ {0x5002, 0xe0, 0, 0}, {0x530a, 0x01, 0, 0}, {0x530d, 0x10, 0, 0}, -+ {0x530c, 0x04, 0, 0}, {0x5312, 0x20, 0, 0}, {0x5282, 0x01, 0, 0}, -+ {0x3010, 0x10, 0, 0}, {0x3012, 0x00, 0, 0}, -+}; -+ -+ -+static struct reg_value ov5642_setting_VGA_2_QVGA[] = { -+ {0x3808, 0x01, 0, 0}, {0x3809, 0x40, 0, 0}, {0x380a, 0x00, 0, 0}, -+ {0x380b, 0xf0, 0, 0}, {0x3815, 0x04, 0, 0}, -+}; -+ -+static struct reg_value ov5642_setting_QSXGA_2_VGA[] = { -+ {0x3503, 0x00, 0, 0}, {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0}, -+ {0x3002, 0x5c, 0, 0}, {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, -+ {0x3005, 0xff, 0, 0}, {0x3006, 0x43, 0, 0}, {0x3007, 0x37, 0, 0}, -+ {0x3010, 0x00, 0, 0}, {0x3818, 0xc1, 0, 0}, {0x3621, 0x87, 0, 0}, -+ {0x350c, 0x03, 0, 0}, {0x350d, 0xe8, 0, 0}, {0x3602, 0xfc, 0, 0}, -+ {0x3612, 0xff, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3622, 0x60, 0, 0}, -+ {0x3623, 0x01, 0, 0}, {0x3604, 0x48, 0, 0}, {0x3705, 0xdb, 0, 0}, -+ {0x370a, 0x81, 0, 0}, {0x3801, 0x50, 0, 0}, {0x3803, 0x08, 0, 0}, -+ {0x3804, 0x05, 0, 0}, {0x3805, 0x00, 0, 0}, {0x3806, 0x03, 0, 0}, -+ {0x3807, 0xc0, 0, 0}, {0x3808, 0x02, 0, 0}, {0x3809, 0x80, 0, 0}, -+ {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, {0x380c, 0x0c, 0, 0}, -+ {0x380d, 0x80, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xe8, 0, 0}, -+ {0x3810, 0x40, 0, 0}, {0x3815, 0x04, 0, 0}, {0x3824, 0x11, 0, 0}, -+ {0x3825, 0xb4, 0, 0}, {0x3827, 0x08, 0, 0}, {0x3a00, 0x78, 0, 0}, -+ {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, {0x5682, 0x05, 0, 0}, -+ {0x5683, 0x00, 0, 0}, {0x5686, 0x03, 0, 0}, {0x5687, 0xbc, 0, 0}, -+ {0x5001, 0xff, 0, 0}, {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0}, -+ {0x4407, 0x0c, 0, 0}, {0x3008, 0x02, 0, 0}, {0x460b, 0x37, 0, 0}, -+ {0x460c, 0x22, 0, 0}, {0x471d, 0x05, 0, 0}, {0x4713, 0x02, 0, 0}, -+ {0x471c, 0xd0, 0, 0}, {0x3815, 0x04, 0, 0}, {0x501f, 0x00, 0, 0}, -+ {0x3002, 0x5c, 0, 0}, {0x3819, 0x80, 0, 0}, {0x5002, 0xe0, 0, 0}, -+ {0x530a, 0x01, 0, 0}, {0x530d, 0x0c, 0, 0}, {0x530c, 0x00, 0, 0}, -+ {0x5312, 0x40, 0, 0}, {0x5282, 0x00, 0, 0}, -+ {0x3012, 0x02, 0, 0}, {0x3010, 0x00, 0, 0}, -+}; -+ -+static struct reg_value ov5642_setting_30fps_VGA_640_480[] = { -+ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0}, -+ {0x3018, 0xfc, 0, 0}, {0x3615, 0xf0, 0, 0}, {0x3000, 0x00, 0, 0}, -+ {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0}, {0x3003, 0x00, 0, 0}, -+ {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0}, {0x3006, 0x43, 0, 0}, -+ {0x3007, 0x37, 0, 0}, {0x3011, 0x09, 0, 0}, {0x3012, 0x02, 0, 0}, -+ {0x3010, 0x00, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3815, 0x04, 0, 0}, -+ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0}, -+ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0}, -+ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0}, -+ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0}, -+ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0}, -+ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0}, -+ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0}, -+ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0}, -+ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0}, -+ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0}, -+ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0}, -+ {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, -+ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0}, -+ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0}, -+ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0}, -+ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3825, 0xb0, 0, 0}, -+ {0x3501, 0x1e, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0}, -+ {0x380c, 0x07, 0, 0}, {0x380d, 0x2a, 0, 0}, {0x380e, 0x03, 0, 0}, -+ {0x380f, 0xe8, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, -+ {0x3818, 0xc1, 0, 0}, {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0}, -+ {0x3801, 0x80, 0, 0}, {0x3621, 0xc7, 0, 0}, {0x3801, 0x50, 0, 0}, -+ {0x3803, 0x08, 0, 0}, {0x3827, 0x08, 0, 0}, {0x3810, 0x80, 0, 0}, -+ {0x3804, 0x05, 0, 0}, {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0}, -+ {0x5683, 0x00, 0, 0}, {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0}, -+ {0x5686, 0x03, 0, 0}, {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0}, -+ {0x3a1a, 0x05, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0}, -+ {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, -+ {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0}, -+ {0x350d, 0xd0, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0}, -+ {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0}, -+ {0x3503, 0x00, 0, 0}, {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0}, -+ {0x528c, 0x08, 0, 0}, {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0}, -+ {0x528f, 0x10, 0, 0}, {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0}, -+ {0x5293, 0x02, 0, 0}, {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0}, -+ {0x5296, 0x00, 0, 0}, {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0}, -+ {0x5299, 0x02, 0, 0}, {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0}, -+ {0x529c, 0x00, 0, 0}, {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0}, -+ {0x529f, 0x02, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0}, -+ {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0}, -+ {0x3a1f, 0x10, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0}, -+ {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0}, -+ {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0}, -+ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0}, -+ {0x3a0b, 0xa0, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, -+ {0x5193, 0x70, 0, 0}, {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0}, -+ {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0}, -+ {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, -+ {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0}, -+ {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0}, -+ {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0}, -+ {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0}, -+ {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0}, -+ {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0}, -+ {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0}, -+ {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0}, -+ {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0}, -+ {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0}, -+ {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0}, -+ {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0}, -+ {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0}, -+ {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0}, -+ {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0}, -+ {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0}, -+ {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0}, -+ {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0}, -+ {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0}, -+ {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0}, -+ {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0}, -+ {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0}, -+ {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0}, -+ {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0}, -+ {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0}, -+ {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0}, -+ {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0}, -+ {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0}, -+ {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0}, -+ {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0}, -+ {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0}, -+ {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0}, -+ {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0}, -+ {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0}, -+ {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0}, -+ {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0}, -+ {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0}, -+ {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0}, -+ {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0}, -+ {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0}, -+ {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0}, -+ {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, -+ {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0}, -+ {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0}, -+ {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0}, -+ {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0}, -+ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, -+ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, -+ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0}, -+ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0}, -+ {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0}, -+ {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0}, -+ {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0}, -+ {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0}, -+ {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0}, -+ {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0}, -+ {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0}, -+ {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0}, -+ {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0}, -+ {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0}, -+ {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0}, -+ {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0}, -+ {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0}, -+ {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0}, -+ {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0}, -+ {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0}, -+ {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0}, -+ {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0}, -+ {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0}, -+ {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0}, -+ {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0}, -+ {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0}, -+ {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0}, -+ {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0}, -+ {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0}, -+ {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0}, -+ {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0}, -+ {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0}, -+ {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0}, -+ {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0}, -+ {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0}, -+ {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0}, -+ {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0}, -+ {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0}, -+ {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0}, -+ {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0}, -+ {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0}, -+ {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0}, -+ {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0}, -+ {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0}, -+ {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0}, -+ {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0}, -+ {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0}, -+ {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0}, -+ {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0}, -+ {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0}, -+ {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0}, -+ {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0}, -+ {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0}, -+ {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0}, -+ {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0}, -+ {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0}, -+ {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0}, -+ {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0}, -+ {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0}, -+ {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0}, -+ {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0}, -+ {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0}, -+ {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0}, -+ {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0}, -+ {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0}, -+ {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0}, -+ {0x302b, 0x00, 0, 0}, {0x3621, 0x87, 0, 0}, {0x3a00, 0x78, 0, 0}, -+}; -+ -+static struct reg_value ov5642_setting_15fps_VGA_640_480[] = { -+ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0}, -+ {0x3018, 0xfc, 0, 0}, {0x3615, 0xf0, 0, 0}, {0x3000, 0x00, 0, 0}, -+ {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0}, {0x3003, 0x00, 0, 0}, -+ {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0}, {0x3006, 0x43, 0, 0}, -+ {0x3007, 0x37, 0, 0}, {0x3011, 0x09, 0, 0}, {0x3012, 0x02, 0, 0}, -+ {0x3010, 0x00, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3815, 0x04, 0, 0}, -+ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0}, -+ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0}, -+ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0}, -+ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0}, -+ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0}, -+ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0}, -+ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0}, -+ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0}, -+ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0}, -+ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0}, -+ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0}, -+ {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, -+ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0}, -+ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0}, -+ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0}, -+ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3825, 0xb0, 0, 0}, -+ {0x3501, 0x1e, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0}, -+ {0x380c, 0x07, 0, 0}, {0x380d, 0x2a, 0, 0}, {0x380e, 0x07, 0, 0}, -+ {0x380f, 0xd0, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, -+ {0x3818, 0xc1, 0, 0}, {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0}, -+ {0x3801, 0x80, 0, 0}, {0x3621, 0xc7, 0, 0}, {0x3801, 0x50, 0, 0}, -+ {0x3803, 0x08, 0, 0}, {0x3827, 0x08, 0, 0}, {0x3810, 0x80, 0, 0}, -+ {0x3804, 0x05, 0, 0}, {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0}, -+ {0x5683, 0x00, 0, 0}, {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0}, -+ {0x5686, 0x03, 0, 0}, {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0}, -+ {0x3a1a, 0x05, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0}, -+ {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, -+ {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0}, -+ {0x350d, 0xd0, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0}, -+ {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0}, -+ {0x3503, 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{0x5492, 0x04, 0, 0}, -+ {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0}, -+ {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0}, -+ {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0}, -+ {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0}, -+ {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0}, -+ {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0}, -+ {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0}, -+ {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0}, -+ {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0}, -+ {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0}, -+ {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0}, -+ {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0}, -+ {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0}, -+ {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0}, -+ {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, -+ {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0}, -+ {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0}, -+ {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0}, -+ {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0}, -+ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, -+ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, -+ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0}, -+ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0}, -+ {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0}, -+ {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0}, -+ {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0}, -+ {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0}, -+ {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0}, -+ {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0}, -+ {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0}, -+ {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0}, -+ {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0}, -+ {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0}, -+ {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0}, -+ {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0}, -+ {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0}, -+ {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0}, -+ {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0}, -+ {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0}, -+ {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0}, -+ {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0}, -+ {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0}, -+ {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0}, -+ {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0}, -+ {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0}, -+ {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0}, -+ {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0}, -+ {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0}, -+ {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0}, -+ {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0}, -+ {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0}, -+ {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0}, -+ {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0}, -+ {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0}, -+ {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0}, -+ {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0}, -+ {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0}, -+ {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0}, -+ {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0}, -+ {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0}, -+ {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0}, -+ {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0}, -+ {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0}, -+ {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0}, -+ {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0}, -+ {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0}, -+ {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0}, -+ {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0}, -+ {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0}, -+ {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0}, -+ {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0}, -+ {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0}, -+ {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0}, -+ {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0}, -+ {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0}, -+ {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0}, -+ {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0}, -+ {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0}, -+ {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0}, -+ {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0}, -+ {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0}, -+ {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0}, -+ {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0}, -+ {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0}, -+ {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0}, -+ {0x302b, 0x00, 0, 0}, {0x3621, 0x87, 0, 0}, {0x3a00, 0x78, 0, 0}, -+}; -+ -+ -+static struct reg_value ov5642_setting_30fps_XGA_1024_768[] = { -+ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0}, -+ {0x3018, 0xfc, 0, 0}, {0x3615, 0xf0, 0, 0}, {0x3000, 0x00, 0, 0}, -+ {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0}, {0x3003, 0x00, 0, 0}, -+ {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0}, {0x3006, 0x43, 0, 0}, -+ {0x3007, 0x37, 0, 0}, {0x3011, 0x09, 0, 0}, {0x3012, 0x02, 0, 0}, -+ {0x3010, 0x00, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3815, 0x04, 0, 0}, -+ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0}, -+ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0}, -+ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0}, -+ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0}, -+ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0}, -+ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0}, -+ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0}, -+ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0}, -+ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0}, -+ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0}, -+ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0}, -+ {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, -+ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0}, -+ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0}, -+ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0}, -+ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3825, 0xb0, 0, 0}, -+ {0x3501, 0x1e, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0}, -+ {0x380c, 0x07, 0, 0}, {0x380d, 0x2a, 0, 0}, {0x380e, 0x03, 0, 0}, -+ {0x380f, 0xe8, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, -+ {0x3818, 0xc1, 0, 0}, {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0}, -+ {0x3801, 0x80, 0, 0}, {0x3621, 0xc7, 0, 0}, {0x3801, 0x50, 0, 0}, -+ {0x3803, 0x08, 0, 0}, {0x3827, 0x08, 0, 0}, {0x3810, 0x80, 0, 0}, -+ {0x3804, 0x05, 0, 0}, {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0}, -+ {0x5683, 0x00, 0, 0}, {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0}, -+ {0x5686, 0x03, 0, 0}, {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0}, -+ {0x3a1a, 0x05, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0}, -+ {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, -+ {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0}, -+ {0x350d, 0xd0, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0}, -+ {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0}, -+ {0x3503, 0x00, 0, 0}, {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0}, -+ {0x528c, 0x08, 0, 0}, {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0}, -+ {0x528f, 0x10, 0, 0}, {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0}, -+ {0x5293, 0x02, 0, 0}, {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0}, -+ {0x5296, 0x00, 0, 0}, {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0}, -+ {0x5299, 0x02, 0, 0}, {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0}, -+ {0x529c, 0x00, 0, 0}, {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0}, -+ {0x529f, 0x02, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0}, -+ {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0}, -+ {0x3a1f, 0x10, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0}, -+ {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0}, -+ {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0}, -+ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0}, -+ {0x3a0b, 0xa0, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, -+ {0x5193, 0x70, 0, 0}, {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0}, -+ {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0}, -+ {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, -+ {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0}, -+ {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0}, -+ {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0}, -+ {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0}, -+ {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0}, -+ {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0}, -+ {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0}, -+ {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0}, -+ {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0}, -+ {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0}, -+ {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0}, -+ {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0}, -+ {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0}, -+ {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0}, -+ {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0}, -+ {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0}, -+ {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0}, -+ {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0}, -+ {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0}, -+ {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0}, -+ {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0}, -+ {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0}, -+ {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0}, -+ {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0}, -+ {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0}, -+ {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0}, -+ {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0}, -+ {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0}, -+ {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0}, -+ {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0}, -+ {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0}, -+ {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0}, -+ {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0}, -+ {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0}, -+ {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0}, -+ {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0}, -+ {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0}, -+ {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0}, -+ {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0}, -+ {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0}, -+ {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0}, -+ {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, -+ {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0}, -+ {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0}, -+ {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0}, -+ {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0}, -+ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, -+ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, -+ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0}, -+ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0}, -+ {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0}, -+ {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0}, -+ {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0}, -+ {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0}, -+ {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0}, -+ {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0}, -+ {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0}, -+ {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0}, -+ {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0}, -+ {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0}, -+ {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0}, -+ {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0}, -+ {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0}, -+ {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0}, -+ {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0}, -+ {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0}, -+ {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0}, -+ {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0}, -+ {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0}, -+ {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0}, -+ {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0}, -+ {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0}, -+ {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0}, -+ {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0}, -+ {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0}, -+ {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0}, -+ {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0}, -+ {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0}, -+ {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0}, -+ {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0}, -+ {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0}, -+ {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0}, -+ {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0}, -+ {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0}, -+ {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0}, -+ {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0}, -+ {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0}, -+ {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0}, -+ {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0}, -+ {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0}, -+ {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0}, -+ {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0}, -+ {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0}, -+ {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0}, -+ {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0}, -+ {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0}, -+ {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0}, -+ {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0}, -+ {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0}, -+ {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0}, -+ {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0}, -+ {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0}, -+ {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0}, -+ {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0}, -+ {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0}, -+ {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0}, -+ {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0}, -+ {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0}, -+ {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0}, -+ {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0}, -+ {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0}, -+ {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0}, -+ {0x302b, 0x00, 0, 0}, {0x3621, 0x87, 0, 0}, {0x3a00, 0x78, 0, 0}, -+ {0x3808, 0x04, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x03, 0, 0}, -+ {0x380b, 0x00, 0, 0}, {0x3815, 0x02, 0, 0}, {0x302c, 0x60, 0x60, 0}, -+}; -+ -+static struct reg_value ov5642_setting_15fps_XGA_1024_768[] = { -+ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0}, -+ {0x3018, 0xfc, 0, 0}, {0x3615, 0xf0, 0, 0}, {0x3000, 0x00, 0, 0}, -+ {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0}, {0x3003, 0x00, 0, 0}, -+ {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0}, {0x3006, 0x43, 0, 0}, -+ {0x3007, 0x37, 0, 0}, {0x3011, 0x09, 0, 0}, {0x3012, 0x02, 0, 0}, -+ {0x3010, 0x00, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3815, 0x04, 0, 0}, -+ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0}, -+ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0}, -+ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0}, -+ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0}, -+ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0}, -+ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0}, -+ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0}, -+ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0}, -+ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0}, -+ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0}, -+ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0}, -+ {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, -+ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0}, -+ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0}, -+ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0}, -+ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3825, 0xb0, 0, 0}, -+ {0x3501, 0x1e, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0}, -+ {0x380c, 0x07, 0, 0}, {0x380d, 0x2a, 0, 0}, {0x380e, 0x07, 0, 0}, -+ {0x380f, 0xd0, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, -+ {0x3818, 0xc1, 0, 0}, {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0}, -+ {0x3801, 0x80, 0, 0}, {0x3621, 0xc7, 0, 0}, {0x3801, 0x50, 0, 0}, -+ {0x3803, 0x08, 0, 0}, {0x3827, 0x08, 0, 0}, {0x3810, 0x80, 0, 0}, -+ {0x3804, 0x05, 0, 0}, {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0}, -+ {0x5683, 0x00, 0, 0}, {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0}, -+ {0x5686, 0x03, 0, 0}, {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0}, -+ {0x3a1a, 0x05, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0}, -+ {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, -+ {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0}, -+ {0x350d, 0xd0, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0}, -+ {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0}, -+ {0x3503, 0x00, 0, 0}, {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0}, -+ {0x528c, 0x08, 0, 0}, {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0}, -+ {0x528f, 0x10, 0, 0}, {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0}, -+ {0x5293, 0x02, 0, 0}, {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0}, -+ {0x5296, 0x00, 0, 0}, {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0}, -+ {0x5299, 0x02, 0, 0}, {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0}, -+ {0x529c, 0x00, 0, 0}, {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0}, -+ {0x529f, 0x02, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0}, -+ {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0}, -+ {0x3a1f, 0x10, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0}, -+ {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0}, -+ {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0}, -+ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0}, -+ {0x3a0b, 0xa0, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, -+ {0x5193, 0x70, 0, 0}, {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0}, -+ {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0}, -+ {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, -+ {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0}, -+ {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0}, -+ {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0}, -+ {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0}, -+ {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0}, -+ {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0}, -+ {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0}, -+ {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0}, -+ {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0}, -+ {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0}, -+ {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0}, -+ {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0}, -+ {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0}, -+ {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0}, -+ {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0}, -+ {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0}, -+ {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0}, -+ {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0}, -+ {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0}, -+ {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0}, -+ {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0}, -+ {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0}, -+ {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0}, -+ {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0}, -+ {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0}, -+ {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0}, -+ {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0}, -+ {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0}, -+ {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0}, -+ {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0}, -+ {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0}, -+ {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0}, -+ {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0}, -+ {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0}, -+ {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0}, -+ {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0}, -+ {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0}, -+ {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0}, -+ {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0}, -+ {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0}, -+ {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0}, -+ {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, -+ {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0}, -+ {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0}, -+ {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0}, -+ {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0}, -+ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, -+ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, -+ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0}, -+ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0}, -+ {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0}, -+ {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0}, -+ {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0}, -+ {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0}, -+ {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0}, -+ {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0}, -+ {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0}, -+ {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0}, -+ {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0}, -+ {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0}, -+ {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0}, -+ {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0}, -+ {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0}, -+ {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0}, -+ {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0}, -+ {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0}, -+ {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0}, -+ {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0}, -+ {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0}, -+ {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0}, -+ {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0}, -+ {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0}, -+ {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0}, -+ {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0}, -+ {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0}, -+ {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0}, -+ {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0}, -+ {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0}, -+ {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0}, -+ {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0}, -+ {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0}, -+ {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0}, -+ {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0}, -+ {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0}, -+ {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0}, -+ {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0}, -+ {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0}, -+ {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0}, -+ {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0}, -+ {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0}, -+ {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0}, -+ {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0}, -+ {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0}, -+ {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0}, -+ {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0}, -+ {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0}, -+ {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0}, -+ {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0}, -+ {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0}, -+ {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0}, -+ {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0}, -+ {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0}, -+ {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0}, -+ {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0}, -+ {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0}, -+ {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0}, -+ {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0}, -+ {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0}, -+ {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0}, -+ {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0}, -+ {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0}, -+ {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0}, -+ {0x302b, 0x00, 0, 0}, {0x3621, 0x87, 0, 0}, {0x3a00, 0x78, 0, 0}, -+ {0x3808, 0x04, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x03, 0, 0}, -+ {0x380b, 0x00, 0, 0}, {0x3815, 0x02, 0, 0}, {0x302c, 0x60, 0x60, 0}, -+}; -+ -+static struct reg_value ov5642_setting_30fps_QVGA_320_240[] = { -+ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0}, -+ {0x3018, 0xfc, 0, 0}, {0x3615, 0xf0, 0, 0}, {0x3000, 0x00, 0, 0}, -+ {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0}, {0x3003, 0x00, 0, 0}, -+ {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0}, {0x3006, 0x43, 0, 0}, -+ {0x3007, 0x37, 0, 0}, {0x3011, 0x09, 0, 0}, {0x3012, 0x02, 0, 0}, -+ {0x3010, 0x00, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3815, 0x04, 0, 0}, -+ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0}, -+ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0}, -+ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0}, -+ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0}, -+ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0}, -+ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0}, -+ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0}, -+ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0}, -+ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0}, -+ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0}, -+ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0}, -+ {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, -+ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0}, -+ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0}, -+ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0}, -+ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3825, 0xb0, 0, 0}, -+ {0x3501, 0x1e, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0}, -+ {0x380c, 0x07, 0, 0}, {0x380d, 0x2a, 0, 0}, {0x380e, 0x03, 0, 0}, -+ {0x380f, 0xe8, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, -+ {0x3818, 0xc1, 0, 0}, {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0}, -+ {0x3801, 0x80, 0, 0}, {0x3621, 0xc7, 0, 0}, {0x3801, 0x50, 0, 0}, -+ {0x3803, 0x08, 0, 0}, {0x3827, 0x08, 0, 0}, {0x3810, 0x80, 0, 0}, -+ {0x3804, 0x05, 0, 0}, {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0}, -+ {0x5683, 0x00, 0, 0}, {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0}, -+ {0x5686, 0x03, 0, 0}, {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0}, -+ {0x3a1a, 0x05, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0}, -+ {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, -+ {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0}, -+ {0x350d, 0xd0, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0}, -+ {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0}, -+ {0x3503, 0x00, 0, 0}, {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0}, -+ {0x528c, 0x08, 0, 0}, {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0}, -+ {0x528f, 0x10, 0, 0}, {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0}, -+ {0x5293, 0x02, 0, 0}, {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0}, -+ {0x5296, 0x00, 0, 0}, {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0}, -+ {0x5299, 0x02, 0, 0}, {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0}, -+ {0x529c, 0x00, 0, 0}, {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0}, -+ {0x529f, 0x02, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0}, -+ {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0}, -+ {0x3a1f, 0x10, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0}, -+ {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0}, -+ {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0}, -+ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0}, -+ {0x3a0b, 0xa0, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, -+ {0x5193, 0x70, 0, 0}, {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0}, -+ {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0}, -+ {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, -+ {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0}, -+ {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0}, -+ {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0}, -+ {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0}, -+ {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0}, -+ {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0}, -+ {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0}, -+ {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0}, -+ {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0}, -+ {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0}, -+ {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0}, -+ {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0}, -+ {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0}, -+ {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0}, -+ {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0}, -+ {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0}, -+ {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0}, -+ {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0}, -+ {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0}, -+ {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0}, -+ {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0}, -+ {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0}, -+ {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0}, -+ {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0}, -+ {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0}, -+ {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0}, -+ {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0}, -+ {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0}, -+ {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0}, -+ {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0}, -+ {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0}, -+ {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0}, -+ {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0}, -+ {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0}, -+ {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0}, -+ {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0}, -+ {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0}, -+ {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0}, -+ {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0}, -+ {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0}, -+ {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0}, -+ {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, -+ {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0}, -+ {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0}, -+ {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0}, -+ {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0}, -+ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, -+ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, -+ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0}, -+ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0}, -+ {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0}, -+ {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0}, -+ {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0}, -+ {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0}, -+ {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0}, -+ {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0}, -+ {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0}, -+ {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0}, -+ {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0}, -+ {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0}, -+ {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0}, -+ {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0}, -+ {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0}, -+ {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0}, -+ {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0}, -+ {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0}, -+ {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0}, -+ {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0}, -+ {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0}, -+ {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0}, -+ {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0}, -+ {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0}, -+ {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0}, -+ {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0}, -+ {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0}, -+ {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0}, -+ {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0}, -+ {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0}, -+ {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0}, -+ {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0}, -+ {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0}, -+ {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0}, -+ {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0}, -+ {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0}, -+ {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0}, -+ {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0}, -+ {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0}, -+ {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0}, -+ {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0}, -+ {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0}, -+ {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0}, -+ {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0}, -+ {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0}, -+ {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0}, -+ {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0}, -+ {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0}, -+ {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0}, -+ {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0}, -+ {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0}, -+ {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0}, -+ {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0}, -+ {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0}, -+ {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0}, -+ {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0}, -+ {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0}, -+ {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0}, -+ {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0}, -+ {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0}, -+ {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0}, -+ {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0}, -+ {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0}, -+ {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0}, -+ {0x302b, 0x00, 0, 0}, {0x3621, 0x87, 0, 0}, {0x3808, 0x01, 0, 0}, -+ {0x3809, 0x40, 0, 0}, {0x380a, 0x00, 0, 0}, {0x380b, 0xf0, 0, 0}, -+}; -+ -+static struct reg_value ov5642_setting_30fps_NTSC_720_480[] = { -+ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0}, -+ {0x3018, 0xfc, 0, 0}, {0x3615, 0xf0, 0, 0}, {0x3000, 0x00, 0, 0}, -+ {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0}, {0x3003, 0x00, 0, 0}, -+ {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0}, {0x3006, 0x43, 0, 0}, -+ {0x3007, 0x37, 0, 0}, {0x3011, 0x09, 0, 0}, {0x3012, 0x02, 0, 0}, -+ {0x3010, 0x00, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3815, 0x04, 0, 0}, -+ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0}, -+ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0}, -+ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0}, -+ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0}, -+ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0}, -+ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0}, -+ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0}, -+ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0}, -+ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0}, -+ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0}, -+ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0}, -+ {0x3809, 0xd0, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, -+ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0}, -+ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0}, -+ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0}, -+ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3825, 0xb0, 0, 0}, -+ {0x3501, 0x1e, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0}, -+ {0x380c, 0x07, 0, 0}, {0x380d, 0x2a, 0, 0}, {0x380e, 0x03, 0, 0}, -+ {0x380f, 0xe8, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, -+ {0x3818, 0xc1, 0, 0}, {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0}, -+ {0x3801, 0x80, 0, 0}, {0x3621, 0xc7, 0, 0}, {0x3801, 0x50, 0, 0}, -+ {0x3803, 0x08, 0, 0}, {0x3827, 0x3c, 0, 0}, {0x3810, 0x80, 0, 0}, -+ {0x3804, 0x05, 0, 0}, {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0}, -+ {0x5683, 0x00, 0, 0}, {0x3806, 0x03, 0, 0}, {0x3807, 0x58, 0, 0}, -+ {0x5686, 0x03, 0, 0}, {0x5687, 0x58, 0, 0}, {0x3a00, 0x78, 0, 0}, -+ {0x3a1a, 0x05, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0}, -+ {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, -+ {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0}, -+ {0x350d, 0xd0, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0}, -+ {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0}, -+ {0x3503, 0x00, 0, 0}, {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0}, -+ {0x528c, 0x08, 0, 0}, {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0}, -+ {0x528f, 0x10, 0, 0}, {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0}, -+ {0x5293, 0x02, 0, 0}, {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0}, -+ {0x5296, 0x00, 0, 0}, {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0}, -+ {0x5299, 0x02, 0, 0}, {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0}, -+ {0x529c, 0x00, 0, 0}, {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0}, -+ {0x529f, 0x02, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0}, -+ {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0}, -+ {0x3a1f, 0x10, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0}, -+ {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0}, -+ {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0}, -+ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0}, -+ {0x3a0b, 0xa0, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, -+ {0x5193, 0x70, 0, 0}, {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0}, -+ {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0}, -+ {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, -+ {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0}, -+ {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0}, -+ {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0}, -+ {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0}, -+ {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0}, -+ {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0}, -+ {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0}, -+ {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0}, -+ {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0}, -+ {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0}, -+ {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0}, -+ {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0}, -+ {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0}, -+ {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0}, -+ {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0}, -+ {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0}, -+ {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0}, -+ {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0}, -+ {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0}, -+ {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0}, -+ {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0}, -+ {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0}, -+ {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0}, -+ {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0}, -+ {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0}, -+ {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0}, -+ {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0}, -+ {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0}, -+ {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0}, -+ {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0}, -+ {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0}, -+ {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0}, -+ {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0}, -+ {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0}, -+ {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0}, -+ {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0}, -+ {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0}, -+ {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0}, -+ {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0}, -+ {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0}, -+ {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0}, -+ {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, -+ {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0}, -+ {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0}, -+ {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0}, -+ {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0}, -+ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, -+ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, -+ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0}, -+ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0}, -+ {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0}, -+ {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0}, -+ {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0}, -+ {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0}, -+ {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0}, -+ {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0}, -+ {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0}, -+ {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0}, -+ {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0}, -+ {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0}, -+ {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0}, -+ {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0}, -+ {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0}, -+ {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0}, -+ {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0}, -+ {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0}, -+ {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0}, -+ {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0}, -+ {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0}, -+ {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0}, -+ {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0}, -+ {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0}, -+ {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0}, -+ {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0}, -+ {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0}, -+ {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0}, -+ {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0}, -+ {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0}, -+ {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0}, -+ {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0}, -+ {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0}, -+ {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0}, -+ {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0}, -+ {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0}, -+ {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0}, -+ {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0}, -+ {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0}, -+ {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0}, -+ {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0}, -+ {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0}, -+ {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0}, -+ {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0}, -+ {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0}, -+ {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0}, -+ {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0}, -+ {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0}, -+ {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0}, -+ {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0}, -+ {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0}, -+ {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0}, -+ {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0}, -+ {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0}, -+ {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0}, -+ {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0}, -+ {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0}, -+ {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0}, -+ {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0}, -+ {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0}, -+ {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0}, -+ {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0}, -+ {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0}, -+ {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0}, -+ {0x302b, 0x00, 0, 0}, {0x3621, 0x87, 0, 0}, {0x3a00, 0x78, 0, 0}, -+ {0x302c, 0x60, 0x60, 0}, -+}; -+ -+static struct reg_value ov5642_setting_30fps_PAL_720_576[] = { -+ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0}, -+ {0x3018, 0xfc, 0, 0}, {0x3615, 0xf0, 0, 0}, {0x3000, 0x00, 0, 0}, -+ {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0}, {0x3003, 0x00, 0, 0}, -+ {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0}, {0x3006, 0x43, 0, 0}, -+ {0x3007, 0x37, 0, 0}, {0x3011, 0x09, 0, 0}, {0x3012, 0x02, 0, 0}, -+ {0x3010, 0x00, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3815, 0x04, 0, 0}, -+ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0}, -+ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0}, -+ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0}, -+ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0}, -+ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0}, -+ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0}, -+ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0}, -+ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0}, -+ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0}, -+ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0}, -+ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0}, -+ {0x3809, 0xd0, 0, 0}, {0x380a, 0x02, 0, 0}, {0x380b, 0x40, 0, 0}, -+ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0}, -+ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0}, -+ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0}, -+ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3825, 0xd8, 0, 0}, -+ {0x3501, 0x1e, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0}, -+ {0x380c, 0x07, 0, 0}, {0x380d, 0x2a, 0, 0}, {0x380e, 0x03, 0, 0}, -+ {0x380f, 0xe8, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, -+ {0x3818, 0xc1, 0, 0}, {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0}, -+ {0x3801, 0x80, 0, 0}, {0x3621, 0xc7, 0, 0}, {0x3801, 0x50, 0, 0}, -+ {0x3803, 0x08, 0, 0}, {0x3827, 0x3c, 0, 0}, {0x3810, 0x80, 0, 0}, -+ {0x3804, 0x04, 0, 0}, {0x3805, 0xb0, 0, 0}, {0x5682, 0x04, 0, 0}, -+ {0x5683, 0xb0, 0, 0}, {0x3806, 0x03, 0, 0}, {0x3807, 0x58, 0, 0}, -+ {0x5686, 0x03, 0, 0}, {0x5687, 0x58, 0, 0}, {0x3a00, 0x78, 0, 0}, -+ {0x3a1a, 0x05, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0}, -+ {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, -+ {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0}, -+ {0x350d, 0xd0, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0}, -+ {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0}, -+ {0x3503, 0x00, 0, 0}, {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0}, -+ {0x528c, 0x08, 0, 0}, {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0}, -+ {0x528f, 0x10, 0, 0}, {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0}, -+ {0x5293, 0x02, 0, 0}, {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0}, -+ {0x5296, 0x00, 0, 0}, {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0}, -+ {0x5299, 0x02, 0, 0}, {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0}, -+ {0x529c, 0x00, 0, 0}, {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0}, -+ {0x529f, 0x02, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0}, -+ {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0}, -+ {0x3a1f, 0x10, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0}, -+ {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0}, -+ {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0}, -+ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0}, -+ {0x3a0b, 0xa0, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, -+ {0x5193, 0x70, 0, 0}, {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0}, -+ {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0}, -+ {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, -+ {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0}, -+ {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0}, -+ {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0}, -+ {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0}, -+ {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0}, -+ {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0}, -+ {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0}, -+ {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0}, -+ {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0}, -+ {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0}, -+ {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0}, -+ {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0}, -+ {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0}, -+ {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0}, -+ {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0}, -+ {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0}, -+ {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0}, -+ {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0}, -+ {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0}, -+ {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0}, -+ {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0}, -+ {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0}, -+ {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0}, -+ {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0}, -+ {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0}, -+ {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0}, -+ {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0}, -+ {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0}, -+ {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0}, -+ {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0}, -+ {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0}, -+ {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0}, -+ {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0}, -+ {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0}, -+ {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0}, -+ {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0}, -+ {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0}, -+ {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0}, -+ {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0}, -+ {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0}, -+ {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0}, -+ {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, -+ {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0}, -+ {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0}, -+ {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0}, -+ {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0}, -+ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, -+ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, -+ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0}, -+ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0}, -+ {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0}, -+ {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0}, -+ {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0}, -+ {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0}, -+ {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0}, -+ {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0}, -+ {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0}, -+ {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0}, -+ {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0}, -+ {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0}, -+ {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0}, -+ {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0}, -+ {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0}, -+ {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0}, -+ {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0}, -+ {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0}, -+ {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0}, -+ {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0}, -+ {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0}, -+ {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0}, -+ {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0}, -+ {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0}, -+ {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0}, -+ {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0}, -+ {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0}, -+ {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0}, -+ {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0}, -+ {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0}, -+ {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0}, -+ {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0}, -+ {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0}, -+ {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0}, -+ {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0}, -+ {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0}, -+ {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0}, -+ {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0}, -+ {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0}, -+ {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0}, -+ {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0}, -+ {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0}, -+ {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0}, -+ {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0}, -+ {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0}, -+ {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0}, -+ {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0}, -+ {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0}, -+ {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0}, -+ {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0}, -+ {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0}, -+ {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0}, -+ {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0}, -+ {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0}, -+ {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0}, -+ {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0}, -+ {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0}, -+ {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0}, -+ {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0}, -+ {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0}, -+ {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0}, -+ {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0}, -+ {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0}, -+ {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0}, -+ {0x302b, 0x00, 0, 0}, {0x3621, 0x87, 0, 0}, {0x3a00, 0x78, 0, 0}, -+ {0x302c, 0x60, 0x60, 0}, -+}; -+ -+static struct reg_value ov5642_setting_15fps_720P_1280_720[] = { -+ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0}, -+ {0x3018, 0xfc, 0, 0}, {0x3810, 0xc2, 0, 0}, {0x3615, 0xf0, 0, 0}, -+ {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0}, {0x3002, 0x00, 0, 0}, -+ {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3030, 0x2b, 0, 0}, -+ {0x3011, 0x08, 0, 0}, {0x3010, 0x10, 0, 0}, {0x3604, 0x60, 0, 0}, -+ {0x3622, 0x60, 0, 0}, {0x3621, 0x09, 0, 0}, {0x3709, 0x00, 0, 0}, -+ {0x4000, 0x21, 0, 0}, {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, -+ {0x3605, 0x04, 0, 0}, {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, -+ {0x300d, 0x22, 0, 0}, {0x3623, 0x22, 0, 0}, {0x5000, 0x4f, 0, 0}, -+ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0}, -+ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5500, 0x0a, 0, 0}, -+ {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0}, {0x5080, 0x08, 0, 0}, -+ {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0}, {0x471d, 0x05, 0, 0}, -+ {0x4708, 0x06, 0, 0}, {0x370c, 0xa0, 0, 0}, {0x3808, 0x0a, 0, 0}, -+ {0x3809, 0x20, 0, 0}, {0x380a, 0x07, 0, 0}, {0x380b, 0x98, 0, 0}, -+ {0x380c, 0x0c, 0, 0}, {0x380d, 0x80, 0, 0}, {0x380e, 0x07, 0, 0}, -+ {0x380f, 0xd0, 0, 0}, {0x5687, 0x94, 0, 0}, {0x501f, 0x00, 0, 0}, -+ {0x5000, 0x4f, 0, 0}, {0x5001, 0xcf, 0, 0}, {0x4300, 0x30, 0, 0}, -+ {0x4300, 0x30, 0, 0}, {0x460b, 0x35, 0, 0}, {0x471d, 0x00, 0, 0}, -+ {0x3002, 0x0c, 0, 0}, {0x3002, 0x00, 0, 0}, {0x4713, 0x03, 0, 0}, -+ {0x471c, 0x50, 0, 0}, {0x4721, 0x02, 0, 0}, {0x4402, 0x90, 0, 0}, -+ {0x460c, 0x22, 0, 0}, {0x3815, 0x44, 0, 0}, {0x3503, 0x07, 0, 0}, -+ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0}, -+ {0x3818, 0xc8, 0, 0}, {0x3801, 0x88, 0, 0}, {0x3824, 0x11, 0, 0}, -+ {0x3a00, 0x78, 0, 0}, {0x3a1a, 0x04, 0, 0}, {0x3a13, 0x30, 0, 0}, -+ {0x3a18, 0x00, 0, 0}, {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0}, -+ {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0}, -+ {0x350c, 0x07, 0, 0}, {0x350d, 0xd0, 0, 0}, {0x3a0d, 0x08, 0, 0}, -+ {0x3a0e, 0x06, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0}, -+ {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0}, -+ {0x3503, 0x00, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x32, 0, 0}, -+ {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x32, 0, 0}, {0x3a11, 0x80, 0, 0}, -+ {0x3a1f, 0x20, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0}, -+ {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0}, -+ {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0}, -+ {0x3a08, 0x09, 0, 0}, {0x3a09, 0x60, 0, 0}, {0x3a0a, 0x07, 0, 0}, -+ {0x3a0b, 0xd0, 0, 0}, {0x3a0d, 0x10, 0, 0}, {0x3a0e, 0x0d, 0, 0}, -+ {0x4407, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, {0x589b, 0x00, 0, 0}, -+ {0x589a, 0xc0, 0, 0}, {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0}, -+ {0x401c, 0x06, 0, 0}, {0x3825, 0xac, 0, 0}, {0x3827, 0x0c, 0, 0}, -+ {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, -+ {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0}, -+ {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0}, -+ {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0}, -+ {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0}, -+ {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0}, -+ {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0}, -+ {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0}, -+ {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0}, -+ {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0}, -+ {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0}, -+ {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0}, -+ {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0}, -+ {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0}, -+ {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0}, -+ {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0}, -+ {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0}, -+ {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0}, -+ {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0}, -+ {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0}, -+ {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0}, -+ {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0}, -+ {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0}, -+ {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0}, -+ {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0}, -+ {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0}, -+ {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0}, -+ {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0}, -+ {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0}, -+ {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0}, -+ {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0}, -+ {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0}, -+ {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0}, -+ {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0}, -+ {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0}, -+ {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0}, -+ {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0}, -+ {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0}, -+ {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0}, -+ {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0}, -+ {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0}, -+ {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0}, -+ {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, -+ {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0}, -+ {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0}, -+ {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0}, -+ {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0}, -+ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, -+ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, -+ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0}, -+ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0}, -+ {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0}, -+ {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0}, -+ {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0}, -+ {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0}, -+ {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0}, -+ {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0}, -+ {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0}, -+ {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0}, -+ {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0}, -+ {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0}, -+ {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0}, -+ {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0}, -+ {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0}, -+ {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0}, -+ {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0}, -+ {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0}, -+ {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0}, -+ {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0}, -+ {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0}, -+ {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0}, -+ {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0}, -+ {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0}, -+ {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0}, -+ {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0}, -+ {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0}, -+ {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0}, -+ {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0}, -+ {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0}, -+ {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0}, -+ {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0}, -+ {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0}, -+ {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0}, -+ {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0}, -+ {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0}, -+ {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0}, -+ {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0}, -+ {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0}, -+ {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0}, -+ {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0}, -+ {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0}, -+ {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0}, -+ {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0}, -+ {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0}, -+ {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0}, -+ {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0}, -+ {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0}, -+ {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0}, -+ {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0}, -+ {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0}, -+ {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0}, -+ {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0}, -+ {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0}, -+ {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0}, -+ {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0}, -+ {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0}, -+ {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0}, -+ {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0}, -+ {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0}, -+ {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0}, -+ {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0}, -+ {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0}, -+ {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0}, -+ {0x302b, 0x00, 0, 0}, {0x3503, 0x07, 0, 0}, {0x3011, 0x08, 0, 0}, -+ {0x350c, 0x02, 0, 0}, {0x350d, 0xe4, 0, 0}, {0x3621, 0xc9, 0, 0}, -+ {0x370a, 0x81, 0, 0}, {0x3803, 0x08, 0, 0}, {0x3804, 0x05, 0, 0}, -+ {0x3805, 0x00, 0, 0}, {0x3806, 0x02, 0, 0}, {0x3807, 0xd0, 0, 0}, -+ {0x3808, 0x05, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x02, 0, 0}, -+ {0x380b, 0xd0, 0, 0}, {0x380c, 0x08, 0, 0}, {0x380d, 0x72, 0, 0}, -+ {0x380e, 0x02, 0, 0}, {0x380f, 0xe4, 0, 0}, {0x3810, 0xc0, 0, 0}, -+ {0x3818, 0xc9, 0, 0}, {0x381c, 0x10, 0, 0}, {0x381d, 0xa0, 0, 0}, -+ {0x381e, 0x05, 0, 0}, {0x381f, 0xb0, 0, 0}, {0x3820, 0x00, 0, 0}, -+ {0x3821, 0x00, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3a08, 0x1b, 0, 0}, -+ {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x17, 0, 0}, {0x3a0b, 0x20, 0, 0}, -+ {0x3a0d, 0x02, 0, 0}, {0x3a0e, 0x01, 0, 0}, {0x401c, 0x04, 0, 0}, -+ {0x5682, 0x05, 0, 0}, {0x5683, 0x00, 0, 0}, {0x5686, 0x02, 0, 0}, -+ {0x5687, 0xcc, 0, 0}, {0x5001, 0x7f, 0, 0}, {0x589b, 0x06, 0, 0}, -+ {0x589a, 0xc5, 0, 0}, {0x3503, 0x00, 0, 0}, {0x3010, 0x10, 0, 0}, -+ {0x460c, 0x20, 0, 0}, {0x460b, 0x37, 0, 0}, {0x471c, 0xd0, 0, 0}, -+ {0x471d, 0x05, 0, 0}, {0x3815, 0x01, 0, 0}, {0x3818, 0x00, 0x08, 0}, -+ {0x501f, 0x00, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3002, 0x1c, 0, 0}, -+ {0x3819, 0x80, 0, 0}, {0x5002, 0xe0, 0, 0}, {0x3010, 0x30, 0, 0}, -+ {0x3a08, 0x06, 0, 0}, {0x3a09, 0x60, 0, 0}, {0x3a0a, 0x05, 0, 0}, -+ {0x3a0b, 0x50, 0, 0}, {0x3a0d, 0x08, 0, 0}, {0x3a0e, 0x07, 0, 0}, -+}; -+ -+static struct reg_value ov5642_setting_30fps_720P_1280_720[] = { -+ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0}, -+ {0x3018, 0xfc, 0, 0}, {0x3810, 0xc2, 0, 0}, {0x3615, 0xf0, 0, 0}, -+ {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0}, {0x3002, 0x00, 0, 0}, -+ {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3030, 0x2b, 0, 0}, -+ {0x3011, 0x08, 0, 0}, {0x3010, 0x10, 0, 0}, {0x3604, 0x60, 0, 0}, -+ {0x3622, 0x60, 0, 0}, {0x3621, 0x09, 0, 0}, {0x3709, 0x00, 0, 0}, -+ {0x4000, 0x21, 0, 0}, {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, -+ {0x3605, 0x04, 0, 0}, {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, -+ {0x300d, 0x22, 0, 0}, {0x3623, 0x22, 0, 0}, {0x5000, 0x4f, 0, 0}, -+ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0}, -+ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5500, 0x0a, 0, 0}, -+ {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0}, {0x5080, 0x08, 0, 0}, -+ {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0}, {0x471d, 0x05, 0, 0}, -+ {0x4708, 0x06, 0, 0}, {0x370c, 0xa0, 0, 0}, {0x3808, 0x0a, 0, 0}, -+ {0x3809, 0x20, 0, 0}, {0x380a, 0x07, 0, 0}, {0x380b, 0x98, 0, 0}, -+ {0x380c, 0x0c, 0, 0}, {0x380d, 0x80, 0, 0}, {0x380e, 0x07, 0, 0}, -+ {0x380f, 0xd0, 0, 0}, {0x5687, 0x94, 0, 0}, {0x501f, 0x00, 0, 0}, -+ {0x5000, 0x4f, 0, 0}, {0x5001, 0xcf, 0, 0}, {0x4300, 0x30, 0, 0}, -+ {0x4300, 0x30, 0, 0}, {0x460b, 0x35, 0, 0}, {0x471d, 0x00, 0, 0}, -+ {0x3002, 0x0c, 0, 0}, {0x3002, 0x00, 0, 0}, {0x4713, 0x03, 0, 0}, -+ {0x471c, 0x50, 0, 0}, {0x4721, 0x02, 0, 0}, {0x4402, 0x90, 0, 0}, -+ {0x460c, 0x22, 0, 0}, {0x3815, 0x44, 0, 0}, {0x3503, 0x07, 0, 0}, -+ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0}, -+ {0x3818, 0xc8, 0, 0}, {0x3801, 0x88, 0, 0}, {0x3824, 0x11, 0, 0}, -+ {0x3a00, 0x78, 0, 0}, {0x3a1a, 0x04, 0, 0}, {0x3a13, 0x30, 0, 0}, -+ {0x3a18, 0x00, 0, 0}, {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0}, -+ {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0}, -+ {0x350c, 0x07, 0, 0}, {0x350d, 0xd0, 0, 0}, {0x3a0d, 0x08, 0, 0}, -+ {0x3a0e, 0x06, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0}, -+ {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0}, -+ {0x3503, 0x00, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x32, 0, 0}, -+ {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x32, 0, 0}, {0x3a11, 0x80, 0, 0}, -+ {0x3a1f, 0x20, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0}, -+ {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0}, -+ {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0}, -+ {0x3a08, 0x09, 0, 0}, {0x3a09, 0x60, 0, 0}, {0x3a0a, 0x07, 0, 0}, -+ {0x3a0b, 0xd0, 0, 0}, {0x3a0d, 0x10, 0, 0}, {0x3a0e, 0x0d, 0, 0}, -+ {0x4407, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, {0x589b, 0x00, 0, 0}, -+ {0x589a, 0xc0, 0, 0}, {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0}, -+ {0x401c, 0x06, 0, 0}, {0x3825, 0xac, 0, 0}, {0x3827, 0x0c, 0, 0}, -+ {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, -+ {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0}, -+ {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0}, -+ {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0}, -+ {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0}, -+ {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0}, -+ {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0}, -+ {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0}, -+ {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0}, -+ {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0}, -+ {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0}, -+ {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0}, -+ {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0}, -+ {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0}, -+ {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0}, -+ {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0}, -+ {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0}, -+ {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0}, -+ {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0}, -+ {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0}, -+ {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0}, -+ {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0}, -+ {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0}, -+ {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0}, -+ {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0}, -+ {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0}, -+ {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0}, -+ {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0}, -+ {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0}, -+ {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0}, -+ {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0}, -+ {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0}, -+ {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0}, -+ {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0}, -+ {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0}, -+ {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0}, -+ {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0}, -+ {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0}, -+ {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0}, -+ {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0}, -+ {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0}, -+ {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0}, -+ {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, -+ {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0}, -+ {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0}, -+ {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0}, -+ {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0}, -+ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, -+ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, -+ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0}, -+ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0}, -+ {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0}, -+ {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0}, -+ {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0}, -+ {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0}, -+ {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0}, -+ {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0}, -+ {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0}, -+ {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0}, -+ {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0}, -+ {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0}, -+ {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0}, -+ {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0}, -+ {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0}, -+ {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0}, -+ {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0}, -+ {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0}, -+ {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0}, -+ {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0}, -+ {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0}, -+ {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0}, -+ {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0}, -+ {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0}, -+ {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0}, -+ {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0}, -+ {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0}, -+ {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0}, -+ {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0}, -+ {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0}, -+ {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0}, -+ {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0}, -+ {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0}, -+ {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0}, -+ {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0}, -+ {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0}, -+ {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0}, -+ {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0}, -+ {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0}, -+ {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0}, -+ {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0}, -+ {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0}, -+ {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0}, -+ {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0}, -+ {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0}, -+ {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0}, -+ {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0}, -+ {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0}, -+ {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0}, -+ {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0}, -+ {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0}, -+ {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0}, -+ {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0}, -+ {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0}, -+ {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0}, -+ {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0}, -+ {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0}, -+ {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0}, -+ {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0}, -+ {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0}, -+ {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0}, -+ {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0}, -+ {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0}, -+ {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0}, -+ {0x302b, 0x00, 0, 0}, {0x3503, 0x07, 0, 0}, {0x3011, 0x08, 0, 0}, -+ {0x350c, 0x02, 0, 0}, {0x350d, 0xe4, 0, 0}, {0x3621, 0xc9, 0, 0}, -+ {0x370a, 0x81, 0, 0}, {0x3803, 0x08, 0, 0}, {0x3804, 0x05, 0, 0}, -+ {0x3805, 0x00, 0, 0}, {0x3806, 0x02, 0, 0}, {0x3807, 0xd0, 0, 0}, -+ {0x3808, 0x05, 0, 0}, {0x3809, 0x00, 0, 0}, {0x380a, 0x02, 0, 0}, -+ {0x380b, 0xd0, 0, 0}, {0x380c, 0x08, 0, 0}, {0x380d, 0x72, 0, 0}, -+ {0x380e, 0x02, 0, 0}, {0x380f, 0xe4, 0, 0}, {0x3810, 0xc0, 0, 0}, -+ {0x3818, 0xc9, 0, 0}, {0x381c, 0x10, 0, 0}, {0x381d, 0xa0, 0, 0}, -+ {0x381e, 0x05, 0, 0}, {0x381f, 0xb0, 0, 0}, {0x3820, 0x00, 0, 0}, -+ {0x3821, 0x00, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3a08, 0x1b, 0, 0}, -+ {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x17, 0, 0}, {0x3a0b, 0x20, 0, 0}, -+ {0x3a0d, 0x02, 0, 0}, {0x3a0e, 0x01, 0, 0}, {0x401c, 0x04, 0, 0}, -+ {0x5682, 0x05, 0, 0}, {0x5683, 0x00, 0, 0}, {0x5686, 0x02, 0, 0}, -+ {0x5687, 0xcc, 0, 0}, {0x5001, 0x7f, 0, 0}, {0x589b, 0x06, 0, 0}, -+ {0x589a, 0xc5, 0, 0}, {0x3503, 0x00, 0, 0}, {0x3010, 0x10, 0, 0}, -+ {0x460c, 0x20, 0, 0}, {0x460b, 0x37, 0, 0}, {0x471c, 0xd0, 0, 0}, -+ {0x471d, 0x05, 0, 0}, {0x3815, 0x01, 0, 0}, {0x3818, 0x00, 0x08, 0}, -+ {0x501f, 0x00, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3002, 0x1c, 0, 0}, -+ {0x3819, 0x80, 0, 0}, {0x5002, 0xe0, 0, 0}, -+}; -+ -+static struct reg_value ov5642_setting_15fps_1080P_1920_1080[] = { -+ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0}, -+ {0x3018, 0xfc, 0, 0}, {0x3810, 0xc2, 0, 0}, {0x3615, 0xf0, 0, 0}, -+ {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0}, {0x3002, 0x00, 0, 0}, -+ {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3030, 0x2b, 0, 0}, -+ {0x3011, 0x08, 0, 0}, {0x3010, 0x10, 0, 0}, {0x3604, 0x60, 0, 0}, -+ {0x3622, 0x60, 0, 0}, {0x3621, 0x09, 0, 0}, {0x3709, 0x00, 0, 0}, -+ {0x4000, 0x21, 0, 0}, {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, -+ {0x3605, 0x04, 0, 0}, {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, -+ {0x300d, 0x22, 0, 0}, {0x3623, 0x22, 0, 0}, {0x5000, 0x4f, 0, 0}, -+ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0}, -+ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5500, 0x0a, 0, 0}, -+ {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0}, {0x5080, 0x08, 0, 0}, -+ {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0}, {0x471d, 0x05, 0, 0}, -+ {0x4708, 0x06, 0, 0}, {0x370c, 0xa0, 0, 0}, {0x3808, 0x0a, 0, 0}, -+ {0x3809, 0x20, 0, 0}, {0x380a, 0x07, 0, 0}, {0x380b, 0x98, 0, 0}, -+ {0x380c, 0x0c, 0, 0}, {0x380d, 0x80, 0, 0}, {0x380e, 0x07, 0, 0}, -+ {0x380f, 0xd0, 0, 0}, {0x5687, 0x94, 0, 0}, {0x501f, 0x00, 0, 0}, -+ {0x5000, 0x4f, 0, 0}, {0x5001, 0xcf, 0, 0}, {0x4300, 0x30, 0, 0}, -+ {0x4300, 0x30, 0, 0}, {0x460b, 0x35, 0, 0}, {0x471d, 0x00, 0, 0}, -+ {0x3002, 0x0c, 0, 0}, {0x3002, 0x00, 0, 0}, {0x4713, 0x03, 0, 0}, -+ {0x471c, 0x50, 0, 0}, {0x4721, 0x02, 0, 0}, {0x4402, 0x90, 0, 0}, -+ {0x460c, 0x22, 0, 0}, {0x3815, 0x44, 0, 0}, {0x3503, 0x07, 0, 0}, -+ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0}, -+ {0x3818, 0xc8, 0, 0}, {0x3801, 0x88, 0, 0}, {0x3824, 0x11, 0, 0}, -+ {0x3a00, 0x78, 0, 0}, {0x3a1a, 0x04, 0, 0}, {0x3a13, 0x30, 0, 0}, -+ {0x3a18, 0x00, 0, 0}, {0x3a19, 0x7c, 0, 0}, {0x3a08, 0x12, 0, 0}, -+ {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0}, {0x3a0b, 0xa0, 0, 0}, -+ {0x350c, 0x07, 0, 0}, {0x350d, 0xd0, 0, 0}, {0x3a0d, 0x08, 0, 0}, -+ {0x3a0e, 0x06, 0, 0}, {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0}, -+ {0x3502, 0x00, 0, 0}, {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0}, -+ {0x3503, 0x00, 0, 0}, {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x32, 0, 0}, -+ {0x3a1b, 0x3c, 0, 0}, {0x3a1e, 0x32, 0, 0}, {0x3a11, 0x80, 0, 0}, -+ {0x3a1f, 0x20, 0, 0}, {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0}, -+ {0x3a03, 0x7d, 0, 0}, {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0}, -+ {0x3a15, 0x7d, 0, 0}, {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0}, -+ {0x3a08, 0x09, 0, 0}, {0x3a09, 0x60, 0, 0}, {0x3a0a, 0x07, 0, 0}, -+ {0x3a0b, 0xd0, 0, 0}, {0x3a0d, 0x10, 0, 0}, {0x3a0e, 0x0d, 0, 0}, -+ {0x4407, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, {0x589b, 0x00, 0, 0}, -+ {0x589a, 0xc0, 0, 0}, {0x401e, 0x20, 0, 0}, {0x4001, 0x42, 0, 0}, -+ {0x401c, 0x06, 0, 0}, {0x3825, 0xac, 0, 0}, {0x3827, 0x0c, 0, 0}, -+ {0x528a, 0x01, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, -+ {0x528d, 0x10, 0, 0}, {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0}, -+ {0x5290, 0x30, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0}, -+ {0x5294, 0x00, 0, 0}, {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0}, -+ {0x5297, 0x08, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0}, -+ {0x529a, 0x00, 0, 0}, {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0}, -+ {0x529d, 0x28, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0}, -+ {0x5282, 0x00, 0, 0}, {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0}, -+ {0x5302, 0x00, 0, 0}, {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0}, -+ {0x530d, 0x0c, 0, 0}, {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0}, -+ {0x5310, 0x20, 0, 0}, {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0}, -+ {0x5309, 0x40, 0, 0}, {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0}, -+ {0x5306, 0x00, 0, 0}, {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0}, -+ {0x5315, 0x20, 0, 0}, {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0}, -+ {0x5317, 0x00, 0, 0}, {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0}, -+ {0x5381, 0x00, 0, 0}, {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0}, -+ {0x5384, 0x00, 0, 0}, {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0}, -+ {0x5387, 0x00, 0, 0}, {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0}, -+ {0x538a, 0x00, 0, 0}, {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0}, -+ {0x538d, 0x00, 0, 0}, {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0}, -+ {0x5390, 0x00, 0, 0}, {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0}, -+ {0x5393, 0xa2, 0, 0}, {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0}, -+ {0x5481, 0x21, 0, 0}, {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0}, -+ {0x5484, 0x65, 0, 0}, {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0}, -+ {0x5487, 0x87, 0, 0}, {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0}, -+ {0x548a, 0xaa, 0, 0}, {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0}, -+ {0x548d, 0xdd, 0, 0}, {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0}, -+ {0x5490, 0x05, 0, 0}, {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0}, -+ {0x5493, 0x20, 0, 0}, {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0}, -+ {0x5496, 0x02, 0, 0}, {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0}, -+ {0x5499, 0x86, 0, 0}, {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0}, -+ {0x549c, 0x02, 0, 0}, {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0}, -+ {0x549f, 0x1c, 0, 0}, {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0}, -+ {0x54a2, 0x01, 0, 0}, {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0}, -+ {0x54a5, 0xc5, 0, 0}, {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0}, -+ {0x54a8, 0x01, 0, 0}, {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0}, -+ {0x54ab, 0x41, 0, 0}, {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0}, -+ {0x54ae, 0x00, 0, 0}, {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0}, -+ {0x54b1, 0x20, 0, 0}, {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0}, -+ {0x54b4, 0x00, 0, 0}, {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0}, -+ {0x54b7, 0xdf, 0, 0}, {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0}, -+ {0x3406, 0x00, 0, 0}, {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0}, -+ {0x5182, 0x11, 0, 0}, {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, -+ {0x5185, 0x24, 0, 0}, {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0}, -+ {0x5188, 0x08, 0, 0}, {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0}, -+ {0x518b, 0xb2, 0, 0}, {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0}, -+ {0x518e, 0x3d, 0, 0}, {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0}, -+ {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, -+ {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, -+ {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0}, -+ {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0}, -+ {0x519d, 0x82, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0}, -+ {0x3a0f, 0x38, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0}, -+ {0x3a1e, 0x2e, 0, 0}, {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0}, -+ {0x5688, 0xa6, 0, 0}, {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0}, -+ {0x568b, 0xae, 0, 0}, {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0}, -+ {0x568e, 0x62, 0, 0}, {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0}, -+ {0x5584, 0x40, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0}, -+ {0x5800, 0x27, 0, 0}, {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0}, -+ {0x5803, 0x0f, 0, 0}, {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0}, -+ {0x5806, 0x1e, 0, 0}, {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0}, -+ {0x5809, 0x0d, 0, 0}, {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0}, -+ {0x580c, 0x0a, 0, 0}, {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0}, -+ {0x580f, 0x19, 0, 0}, {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0}, -+ {0x5812, 0x04, 0, 0}, {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0}, -+ {0x5815, 0x06, 0, 0}, {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0}, -+ {0x5818, 0x0a, 0, 0}, {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0}, -+ {0x581b, 0x00, 0, 0}, {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0}, -+ {0x581e, 0x08, 0, 0}, {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0}, -+ {0x5821, 0x05, 0, 0}, {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0}, -+ {0x5824, 0x00, 0, 0}, {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0}, -+ {0x5827, 0x0c, 0, 0}, {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0}, -+ {0x582a, 0x06, 0, 0}, {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0}, -+ {0x582d, 0x07, 0, 0}, {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0}, -+ {0x5830, 0x18, 0, 0}, {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0}, -+ {0x5833, 0x0a, 0, 0}, {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0}, -+ {0x5836, 0x15, 0, 0}, {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0}, -+ {0x5839, 0x1f, 0, 0}, {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0}, -+ {0x583c, 0x17, 0, 0}, {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0}, -+ {0x583f, 0x53, 0, 0}, {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0}, -+ {0x5842, 0x0d, 0, 0}, {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0}, -+ {0x5845, 0x09, 0, 0}, {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0}, -+ {0x5848, 0x10, 0, 0}, {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0}, -+ {0x584b, 0x0e, 0, 0}, {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0}, -+ {0x584e, 0x11, 0, 0}, {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0}, -+ {0x5851, 0x0c, 0, 0}, {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0}, -+ {0x5854, 0x10, 0, 0}, {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0}, -+ {0x5857, 0x0b, 0, 0}, {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0}, -+ {0x585a, 0x0d, 0, 0}, {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0}, -+ {0x585d, 0x0c, 0, 0}, {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0}, -+ {0x5860, 0x0c, 0, 0}, {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0}, -+ {0x5863, 0x08, 0, 0}, {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0}, -+ {0x5866, 0x18, 0, 0}, {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0}, -+ {0x5869, 0x19, 0, 0}, {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0}, -+ {0x586c, 0x13, 0, 0}, {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0}, -+ {0x586f, 0x16, 0, 0}, {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0}, -+ {0x5872, 0x10, 0, 0}, {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0}, -+ {0x5875, 0x16, 0, 0}, {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0}, -+ {0x5878, 0x10, 0, 0}, {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0}, -+ {0x587b, 0x14, 0, 0}, {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0}, -+ {0x587e, 0x11, 0, 0}, {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0}, -+ {0x5881, 0x15, 0, 0}, {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0}, -+ {0x5884, 0x15, 0, 0}, {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0}, -+ {0x5887, 0x17, 0, 0}, {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0}, -+ {0x3702, 0x10, 0, 0}, {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0}, -+ {0x370b, 0x40, 0, 0}, {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0}, -+ {0x3632, 0x52, 0, 0}, {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0}, -+ {0x5785, 0x07, 0, 0}, {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0}, -+ {0x3604, 0x48, 0, 0}, {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0}, -+ {0x370f, 0xc0, 0, 0}, {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0}, -+ {0x5007, 0x00, 0, 0}, {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0}, -+ {0x5013, 0x00, 0, 0}, {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0}, -+ {0x5087, 0x00, 0, 0}, {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0}, -+ {0x302b, 0x00, 0, 0}, {0x3503, 0x07, 0, 0}, {0x3011, 0x07, 0, 0}, -+ {0x350c, 0x04, 0, 0}, {0x350d, 0x58, 0, 0}, {0x3801, 0x8a, 0, 0}, -+ {0x3803, 0x0a, 0, 0}, {0x3804, 0x07, 0, 0}, {0x3805, 0x80, 0, 0}, -+ {0x3806, 0x04, 0, 0}, {0x3807, 0x39, 0, 0}, {0x3808, 0x07, 0, 0}, -+ {0x3809, 0x80, 0, 0}, {0x380a, 0x04, 0, 0}, {0x380b, 0x38, 0, 0}, -+ {0x380c, 0x09, 0, 0}, {0x380d, 0xd6, 0, 0}, {0x380e, 0x04, 0, 0}, -+ {0x380f, 0x58, 0, 0}, {0x381c, 0x11, 0, 0}, {0x381d, 0xba, 0, 0}, -+ {0x381e, 0x04, 0, 0}, {0x381f, 0x48, 0, 0}, {0x3820, 0x04, 0, 0}, -+ {0x3821, 0x18, 0, 0}, {0x3a08, 0x14, 0, 0}, {0x3a09, 0xe0, 0, 0}, -+ {0x3a0a, 0x11, 0, 0}, {0x3a0b, 0x60, 0, 0}, {0x3a0d, 0x04, 0, 0}, -+ {0x3a0e, 0x03, 0, 0}, {0x5682, 0x07, 0, 0}, {0x5683, 0x60, 0, 0}, -+ {0x5686, 0x04, 0, 0}, {0x5687, 0x1c, 0, 0}, {0x5001, 0x7f, 0, 0}, -+ {0x3503, 0x00, 0, 0}, {0x3010, 0x10, 0, 0}, {0x460c, 0x20, 0, 0}, -+ {0x460b, 0x37, 0, 0}, {0x471c, 0xd0, 0, 0}, {0x471d, 0x05, 0, 0}, -+ {0x3815, 0x01, 0, 0}, {0x3818, 0x00, 0x08, 0}, {0x501f, 0x00, 0, 0}, -+ {0x4300, 0x30, 0, 0}, {0x3002, 0x1c, 0, 0}, {0x3819, 0x80, 0, 0}, -+ {0x5002, 0xe0, 0, 0}, -+}; -+ -+static struct reg_value ov5642_setting_15fps_QVGA_320_240[] = { -+ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0}, -+ {0x3018, 0xfc, 0, 0}, {0x3810, 0xc2, 0, 0}, {0x3615, 0xf0, 0, 0}, -+ {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0}, -+ {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0}, -+ {0x3006, 0x43, 0, 0}, {0x3007, 0x37, 0, 0}, {0x3011, 0x08, 0, 0}, -+ {0x3010, 0x10, 0, 0}, {0x460c, 0x22, 0, 0}, {0x3815, 0x04, 0, 0}, -+ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0}, -+ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0}, -+ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0}, -+ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0}, -+ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0}, -+ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0}, -+ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0}, -+ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0}, -+ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0}, -+ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0}, -+ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0}, -+ {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, -+ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0}, -+ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0}, -+ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0}, -+ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3501, 0x1e, 0, 0}, -+ {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0}, {0x380c, 0x0c, 0, 0}, -+ {0x380d, 0x80, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xe8, 0, 0}, -+ {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, {0x3818, 0xc1, 0, 0}, -+ {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0}, {0x3801, 0x80, 0, 0}, -+ {0x3621, 0x87, 0, 0}, {0x3801, 0x50, 0, 0}, {0x3803, 0x08, 0, 0}, -+ {0x3827, 0x08, 0, 0}, {0x3810, 0x40, 0, 0}, {0x3804, 0x05, 0, 0}, -+ {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0}, {0x5683, 0x00, 0, 0}, -+ {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0}, {0x5686, 0x03, 0, 0}, -+ {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0}, {0x3a1a, 0x05, 0, 0}, -+ {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0}, {0x3a19, 0x7c, 0, 0}, -+ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0}, -+ {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0}, {0x350d, 0xd0, 0, 0}, -+ {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0}, {0x3502, 0x00, 0, 0}, -+ {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0}, {0x3503, 0x00, 0, 0}, -+ {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, -+ {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0}, {0x528f, 0x10, 0, 0}, -+ {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x02, 0, 0}, -+ {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0}, {0x5296, 0x00, 0, 0}, -+ {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x02, 0, 0}, -+ {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0}, {0x529c, 0x00, 0, 0}, -+ {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x02, 0, 0}, -+ {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3c, 0, 0}, -+ {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0}, {0x3a1f, 0x10, 0, 0}, -+ {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0}, {0x3a03, 0x7d, 0, 0}, -+ {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0}, {0x3a15, 0x7d, 0, 0}, -+ {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0}, {0x3a08, 0x09, 0, 0}, -+ {0x3a09, 0x60, 0, 0}, {0x3a0a, 0x07, 0, 0}, {0x3a0b, 0xd0, 0, 0}, -+ {0x3a0d, 0x08, 0, 0}, {0x3a0e, 0x06, 0, 0}, {0x5193, 0x70, 0, 0}, -+ {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0}, {0x401e, 0x20, 0, 0}, -+ {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0}, {0x528a, 0x01, 0, 0}, -+ {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, {0x528d, 0x10, 0, 0}, -+ {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0}, {0x5290, 0x30, 0, 0}, -+ {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0}, {0x5294, 0x00, 0, 0}, -+ {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0}, {0x5297, 0x08, 0, 0}, -+ {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0}, {0x529a, 0x00, 0, 0}, -+ {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0}, {0x529d, 0x28, 0, 0}, -+ {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0}, {0x5282, 0x00, 0, 0}, -+ {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0}, {0x5302, 0x00, 0, 0}, -+ {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0}, {0x530d, 0x0c, 0, 0}, -+ {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0}, {0x5310, 0x20, 0, 0}, -+ {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0}, {0x5309, 0x40, 0, 0}, -+ {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0}, {0x5306, 0x00, 0, 0}, -+ {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0}, {0x5315, 0x20, 0, 0}, -+ {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0}, {0x5317, 0x00, 0, 0}, -+ {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0}, {0x5381, 0x00, 0, 0}, -+ {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0}, {0x5384, 0x00, 0, 0}, -+ {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0}, {0x5387, 0x00, 0, 0}, -+ {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0}, {0x538a, 0x00, 0, 0}, -+ {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0}, {0x538d, 0x00, 0, 0}, -+ {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0}, {0x5390, 0x00, 0, 0}, -+ {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0}, {0x5393, 0xa2, 0, 0}, -+ {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0}, {0x5481, 0x21, 0, 0}, -+ {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0}, {0x5484, 0x65, 0, 0}, -+ {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0}, {0x5487, 0x87, 0, 0}, -+ {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0}, {0x548a, 0xaa, 0, 0}, -+ {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0}, {0x548d, 0xdd, 0, 0}, -+ {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0}, {0x5490, 0x05, 0, 0}, -+ {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0}, {0x5493, 0x20, 0, 0}, -+ {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0}, {0x5496, 0x02, 0, 0}, -+ {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0}, {0x5499, 0x86, 0, 0}, -+ {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0}, {0x549c, 0x02, 0, 0}, -+ {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0}, {0x549f, 0x1c, 0, 0}, -+ {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0}, {0x54a2, 0x01, 0, 0}, -+ {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0}, {0x54a5, 0xc5, 0, 0}, -+ {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0}, {0x54a8, 0x01, 0, 0}, -+ {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0}, {0x54ab, 0x41, 0, 0}, -+ {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0}, {0x54ae, 0x00, 0, 0}, -+ {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0}, {0x54b1, 0x20, 0, 0}, -+ {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0}, {0x54b4, 0x00, 0, 0}, -+ {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0}, {0x54b7, 0xdf, 0, 0}, -+ {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0}, {0x3406, 0x00, 0, 0}, -+ {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0}, {0x5182, 0x11, 0, 0}, -+ {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, {0x5185, 0x24, 0, 0}, -+ {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0}, {0x5188, 0x08, 0, 0}, -+ {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0}, {0x518b, 0xb2, 0, 0}, -+ {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0}, {0x518e, 0x3d, 0, 0}, -+ {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0}, {0x5191, 0xf8, 0, 0}, -+ {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, {0x5194, 0xf0, 0, 0}, -+ {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, {0x5197, 0x01, 0, 0}, -+ {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0}, {0x519a, 0x04, 0, 0}, -+ {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0}, {0x519d, 0x82, 0, 0}, -+ {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0}, {0x3a0f, 0x38, 0, 0}, -+ {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0}, {0x3a1e, 0x2e, 0, 0}, -+ {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0}, {0x5688, 0xa6, 0, 0}, -+ {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0}, {0x568b, 0xae, 0, 0}, -+ {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0}, {0x568e, 0x62, 0, 0}, -+ {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0}, {0x5584, 0x40, 0, 0}, -+ {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0}, {0x5800, 0x27, 0, 0}, -+ {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0}, {0x5803, 0x0f, 0, 0}, -+ {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0}, {0x5806, 0x1e, 0, 0}, -+ {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0}, {0x5809, 0x0d, 0, 0}, -+ {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0}, {0x580c, 0x0a, 0, 0}, -+ {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0}, {0x580f, 0x19, 0, 0}, -+ {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0}, {0x5812, 0x04, 0, 0}, -+ {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0}, {0x5815, 0x06, 0, 0}, -+ {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0}, {0x5818, 0x0a, 0, 0}, -+ {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0}, {0x581b, 0x00, 0, 0}, -+ {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0}, {0x581e, 0x08, 0, 0}, -+ {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0}, {0x5821, 0x05, 0, 0}, -+ {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0}, {0x5824, 0x00, 0, 0}, -+ {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0}, {0x5827, 0x0c, 0, 0}, -+ {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0}, {0x582a, 0x06, 0, 0}, -+ {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0}, {0x582d, 0x07, 0, 0}, -+ {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0}, {0x5830, 0x18, 0, 0}, -+ {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0}, {0x5833, 0x0a, 0, 0}, -+ {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0}, {0x5836, 0x15, 0, 0}, -+ {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0}, {0x5839, 0x1f, 0, 0}, -+ {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0}, {0x583c, 0x17, 0, 0}, -+ {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0}, {0x583f, 0x53, 0, 0}, -+ {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0}, {0x5842, 0x0d, 0, 0}, -+ {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0}, {0x5845, 0x09, 0, 0}, -+ {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0}, {0x5848, 0x10, 0, 0}, -+ {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0}, {0x584b, 0x0e, 0, 0}, -+ {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0}, {0x584e, 0x11, 0, 0}, -+ {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0}, {0x5851, 0x0c, 0, 0}, -+ {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0}, {0x5854, 0x10, 0, 0}, -+ {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0}, {0x5857, 0x0b, 0, 0}, -+ {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0}, {0x585a, 0x0d, 0, 0}, -+ {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0}, {0x585d, 0x0c, 0, 0}, -+ {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0}, {0x5860, 0x0c, 0, 0}, -+ {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0}, {0x5863, 0x08, 0, 0}, -+ {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0}, {0x5866, 0x18, 0, 0}, -+ {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0}, {0x5869, 0x19, 0, 0}, -+ {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0}, {0x586c, 0x13, 0, 0}, -+ {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0}, {0x586f, 0x16, 0, 0}, -+ {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0}, {0x5872, 0x10, 0, 0}, -+ {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0}, {0x5875, 0x16, 0, 0}, -+ {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0}, {0x5878, 0x10, 0, 0}, -+ {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0}, {0x587b, 0x14, 0, 0}, -+ {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0}, {0x587e, 0x11, 0, 0}, -+ {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0}, {0x5881, 0x15, 0, 0}, -+ {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0}, {0x5884, 0x15, 0, 0}, -+ {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0}, {0x5887, 0x17, 0, 0}, -+ {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0}, {0x3702, 0x10, 0, 0}, -+ {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0}, {0x370b, 0x40, 0, 0}, -+ {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0}, {0x3632, 0x52, 0, 0}, -+ {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0}, {0x5785, 0x07, 0, 0}, -+ {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0}, {0x3604, 0x48, 0, 0}, -+ {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0}, {0x370f, 0xc0, 0, 0}, -+ {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0}, {0x5007, 0x00, 0, 0}, -+ {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0}, {0x5013, 0x00, 0, 0}, -+ {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0}, {0x5087, 0x00, 0, 0}, -+ {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0}, {0x302b, 0x00, 0, 0}, -+ {0x3808, 0x01, 0, 0}, {0x3809, 0x40, 0, 0}, {0x380a, 0x00, 0, 0}, -+ {0x380b, 0xf0, 0, 0}, {0x3a00, 0x78, 0, 0}, -+}; -+ -+static struct reg_value ov5642_setting_15fps_NTSC_720_480[] = { -+ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0}, -+ {0x3018, 0xfc, 0, 0}, {0x3810, 0xc2, 0, 0}, {0x3615, 0xf0, 0, 0}, -+ {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0}, -+ {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0}, -+ {0x3006, 0x43, 0, 0}, {0x3007, 0x37, 0, 0}, {0x3011, 0x08, 0, 0}, -+ {0x3010, 0x10, 0, 0}, {0x460c, 0x22, 0, 0}, {0x3815, 0x04, 0, 0}, -+ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0}, -+ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0}, -+ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0}, -+ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0}, -+ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0}, -+ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0}, -+ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0}, -+ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0}, -+ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0}, -+ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0}, -+ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0}, -+ {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, -+ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0}, -+ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0}, -+ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0}, -+ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3501, 0x1e, 0, 0}, -+ {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0}, {0x380c, 0x0c, 0, 0}, -+ {0x380d, 0x80, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xe8, 0, 0}, -+ {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, {0x3818, 0xc1, 0, 0}, -+ {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0}, {0x3801, 0x80, 0, 0}, -+ {0x3621, 0x87, 0, 0}, {0x3801, 0x50, 0, 0}, {0x3803, 0x08, 0, 0}, -+ {0x3827, 0x08, 0, 0}, {0x3810, 0x40, 0, 0}, {0x3804, 0x05, 0, 0}, -+ {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0}, {0x5683, 0x00, 0, 0}, -+ {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0}, {0x5686, 0x03, 0, 0}, -+ {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0}, {0x3a1a, 0x05, 0, 0}, -+ {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0}, {0x3a19, 0x7c, 0, 0}, -+ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0}, -+ {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0}, {0x350d, 0xd0, 0, 0}, -+ {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0}, {0x3502, 0x00, 0, 0}, -+ {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0}, {0x3503, 0x00, 0, 0}, -+ {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, -+ {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0}, {0x528f, 0x10, 0, 0}, -+ {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x02, 0, 0}, -+ {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0}, {0x5296, 0x00, 0, 0}, -+ {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x02, 0, 0}, -+ {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0}, {0x529c, 0x00, 0, 0}, -+ {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x02, 0, 0}, -+ {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3c, 0, 0}, -+ {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0}, {0x3a1f, 0x10, 0, 0}, -+ {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0}, {0x3a03, 0x7d, 0, 0}, -+ {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0}, {0x3a15, 0x7d, 0, 0}, -+ {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0}, {0x3a08, 0x09, 0, 0}, -+ {0x3a09, 0x60, 0, 0}, {0x3a0a, 0x07, 0, 0}, {0x3a0b, 0xd0, 0, 0}, -+ {0x3a0d, 0x08, 0, 0}, {0x3a0e, 0x06, 0, 0}, {0x5193, 0x70, 0, 0}, -+ {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0}, {0x401e, 0x20, 0, 0}, -+ {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0}, {0x528a, 0x01, 0, 0}, -+ {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, {0x528d, 0x10, 0, 0}, -+ {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0}, {0x5290, 0x30, 0, 0}, -+ {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0}, {0x5294, 0x00, 0, 0}, -+ {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0}, {0x5297, 0x08, 0, 0}, -+ {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0}, {0x529a, 0x00, 0, 0}, -+ {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0}, {0x529d, 0x28, 0, 0}, -+ {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0}, {0x5282, 0x00, 0, 0}, -+ {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0}, {0x5302, 0x00, 0, 0}, -+ {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0}, {0x530d, 0x0c, 0, 0}, -+ {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0}, {0x5310, 0x20, 0, 0}, -+ {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0}, {0x5309, 0x40, 0, 0}, -+ {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0}, {0x5306, 0x00, 0, 0}, -+ {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0}, {0x5315, 0x20, 0, 0}, -+ {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0}, {0x5317, 0x00, 0, 0}, -+ {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0}, {0x5381, 0x00, 0, 0}, -+ {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0}, {0x5384, 0x00, 0, 0}, -+ {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0}, {0x5387, 0x00, 0, 0}, -+ {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0}, {0x538a, 0x00, 0, 0}, -+ {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0}, {0x538d, 0x00, 0, 0}, -+ {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0}, {0x5390, 0x00, 0, 0}, -+ {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0}, {0x5393, 0xa2, 0, 0}, -+ {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0}, {0x5481, 0x21, 0, 0}, -+ {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0}, {0x5484, 0x65, 0, 0}, -+ {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0}, {0x5487, 0x87, 0, 0}, -+ {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0}, {0x548a, 0xaa, 0, 0}, -+ {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0}, {0x548d, 0xdd, 0, 0}, -+ {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0}, {0x5490, 0x05, 0, 0}, -+ {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0}, {0x5493, 0x20, 0, 0}, -+ {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0}, {0x5496, 0x02, 0, 0}, -+ {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0}, {0x5499, 0x86, 0, 0}, -+ {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0}, {0x549c, 0x02, 0, 0}, -+ {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0}, {0x549f, 0x1c, 0, 0}, -+ {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0}, {0x54a2, 0x01, 0, 0}, -+ {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0}, {0x54a5, 0xc5, 0, 0}, -+ {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0}, {0x54a8, 0x01, 0, 0}, -+ {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0}, {0x54ab, 0x41, 0, 0}, -+ {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0}, {0x54ae, 0x00, 0, 0}, -+ {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0}, {0x54b1, 0x20, 0, 0}, -+ {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0}, {0x54b4, 0x00, 0, 0}, -+ {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0}, {0x54b7, 0xdf, 0, 0}, -+ {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0}, {0x3406, 0x00, 0, 0}, -+ {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0}, {0x5182, 0x11, 0, 0}, -+ {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, {0x5185, 0x24, 0, 0}, -+ {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0}, {0x5188, 0x08, 0, 0}, -+ {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0}, {0x518b, 0xb2, 0, 0}, -+ {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0}, {0x518e, 0x3d, 0, 0}, -+ {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0}, {0x5191, 0xf8, 0, 0}, -+ {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, {0x5194, 0xf0, 0, 0}, -+ {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, {0x5197, 0x01, 0, 0}, -+ {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0}, {0x519a, 0x04, 0, 0}, -+ {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0}, {0x519d, 0x82, 0, 0}, -+ {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0}, {0x3a0f, 0x38, 0, 0}, -+ {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0}, {0x3a1e, 0x2e, 0, 0}, -+ {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0}, {0x5688, 0xa6, 0, 0}, -+ {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0}, {0x568b, 0xae, 0, 0}, -+ {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0}, {0x568e, 0x62, 0, 0}, -+ {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0}, {0x5584, 0x40, 0, 0}, -+ {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0}, {0x5800, 0x27, 0, 0}, -+ {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0}, {0x5803, 0x0f, 0, 0}, -+ {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0}, {0x5806, 0x1e, 0, 0}, -+ {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0}, {0x5809, 0x0d, 0, 0}, -+ {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0}, {0x580c, 0x0a, 0, 0}, -+ {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0}, {0x580f, 0x19, 0, 0}, -+ {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0}, {0x5812, 0x04, 0, 0}, -+ {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0}, {0x5815, 0x06, 0, 0}, -+ {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0}, {0x5818, 0x0a, 0, 0}, -+ {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0}, {0x581b, 0x00, 0, 0}, -+ {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0}, {0x581e, 0x08, 0, 0}, -+ {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0}, {0x5821, 0x05, 0, 0}, -+ {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0}, {0x5824, 0x00, 0, 0}, -+ {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0}, {0x5827, 0x0c, 0, 0}, -+ {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0}, {0x582a, 0x06, 0, 0}, -+ {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0}, {0x582d, 0x07, 0, 0}, -+ {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0}, {0x5830, 0x18, 0, 0}, -+ {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0}, {0x5833, 0x0a, 0, 0}, -+ {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0}, {0x5836, 0x15, 0, 0}, -+ {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0}, {0x5839, 0x1f, 0, 0}, -+ {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0}, {0x583c, 0x17, 0, 0}, -+ {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0}, {0x583f, 0x53, 0, 0}, -+ {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0}, {0x5842, 0x0d, 0, 0}, -+ {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0}, {0x5845, 0x09, 0, 0}, -+ {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0}, {0x5848, 0x10, 0, 0}, -+ {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0}, {0x584b, 0x0e, 0, 0}, -+ {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0}, {0x584e, 0x11, 0, 0}, -+ {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0}, {0x5851, 0x0c, 0, 0}, -+ {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0}, {0x5854, 0x10, 0, 0}, -+ {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0}, {0x5857, 0x0b, 0, 0}, -+ {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0}, {0x585a, 0x0d, 0, 0}, -+ {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0}, {0x585d, 0x0c, 0, 0}, -+ {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0}, {0x5860, 0x0c, 0, 0}, -+ {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0}, {0x5863, 0x08, 0, 0}, -+ {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0}, {0x5866, 0x18, 0, 0}, -+ {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0}, {0x5869, 0x19, 0, 0}, -+ {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0}, {0x586c, 0x13, 0, 0}, -+ {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0}, {0x586f, 0x16, 0, 0}, -+ {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0}, {0x5872, 0x10, 0, 0}, -+ {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0}, {0x5875, 0x16, 0, 0}, -+ {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0}, {0x5878, 0x10, 0, 0}, -+ {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0}, {0x587b, 0x14, 0, 0}, -+ {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0}, {0x587e, 0x11, 0, 0}, -+ {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0}, {0x5881, 0x15, 0, 0}, -+ {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0}, {0x5884, 0x15, 0, 0}, -+ {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0}, {0x5887, 0x17, 0, 0}, -+ {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0}, {0x3702, 0x10, 0, 0}, -+ {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0}, {0x370b, 0x40, 0, 0}, -+ {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0}, {0x3632, 0x52, 0, 0}, -+ {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0}, {0x5785, 0x07, 0, 0}, -+ {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0}, {0x3604, 0x48, 0, 0}, -+ {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0}, {0x370f, 0xc0, 0, 0}, -+ {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0}, {0x5007, 0x00, 0, 0}, -+ {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0}, {0x5013, 0x00, 0, 0}, -+ {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0}, {0x5087, 0x00, 0, 0}, -+ {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0}, {0x302b, 0x00, 0, 0}, -+ {0x3824, 0x11, 0, 0}, {0x3825, 0xb4, 0, 0}, {0x3826, 0x00, 0, 0}, -+ {0x3827, 0x3d, 0, 0}, {0x380c, 0x0c, 0, 0}, {0x380d, 0x80, 0, 0}, -+ {0x380e, 0x03, 0, 0}, {0x380f, 0xe8, 0, 0}, {0x3808, 0x02, 0, 0}, -+ {0x3809, 0xd0, 0, 0}, {0x380A, 0x01, 0, 0}, {0x380B, 0xe0, 0, 0}, -+ {0x3804, 0x05, 0, 0}, {0x3805, 0x00, 0, 0}, {0x3806, 0x03, 0, 0}, -+ {0x3807, 0x55, 0, 0}, {0x5686, 0x03, 0, 0}, {0x5687, 0x55, 0, 0}, -+ {0x5682, 0x05, 0, 0}, {0x5683, 0x00, 0, 0}, -+}; -+ -+static struct reg_value ov5642_setting_15fps_PAL_720_576[] = { -+ {0x3103, 0x93, 0, 0}, {0x3008, 0x82, 0, 0}, {0x3017, 0x7f, 0, 0}, -+ {0x3018, 0xfc, 0, 0}, {0x3810, 0xc2, 0, 0}, {0x3615, 0xf0, 0, 0}, -+ {0x3000, 0x00, 0, 0}, {0x3001, 0x00, 0, 0}, {0x3002, 0x5c, 0, 0}, -+ {0x3003, 0x00, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3005, 0xff, 0, 0}, -+ {0x3006, 0x43, 0, 0}, {0x3007, 0x37, 0, 0}, {0x3011, 0x08, 0, 0}, -+ {0x3010, 0x10, 0, 0}, {0x460c, 0x22, 0, 0}, {0x3815, 0x04, 0, 0}, -+ {0x370c, 0xa0, 0, 0}, {0x3602, 0xfc, 0, 0}, {0x3612, 0xff, 0, 0}, -+ {0x3634, 0xc0, 0, 0}, {0x3613, 0x00, 0, 0}, {0x3605, 0x7c, 0, 0}, -+ {0x3621, 0x09, 0, 0}, {0x3622, 0x60, 0, 0}, {0x3604, 0x40, 0, 0}, -+ {0x3603, 0xa7, 0, 0}, {0x3603, 0x27, 0, 0}, {0x4000, 0x21, 0, 0}, -+ {0x401d, 0x22, 0, 0}, {0x3600, 0x54, 0, 0}, {0x3605, 0x04, 0, 0}, -+ {0x3606, 0x3f, 0, 0}, {0x3c01, 0x80, 0, 0}, {0x5000, 0x4f, 0, 0}, -+ {0x5020, 0x04, 0, 0}, {0x5181, 0x79, 0, 0}, {0x5182, 0x00, 0, 0}, -+ {0x5185, 0x22, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5001, 0xff, 0, 0}, -+ {0x5500, 0x0a, 0, 0}, {0x5504, 0x00, 0, 0}, {0x5505, 0x7f, 0, 0}, -+ {0x5080, 0x08, 0, 0}, {0x300e, 0x18, 0, 0}, {0x4610, 0x00, 0, 0}, -+ {0x471d, 0x05, 0, 0}, {0x4708, 0x06, 0, 0}, {0x3808, 0x02, 0, 0}, -+ {0x3809, 0x80, 0, 0}, {0x380a, 0x01, 0, 0}, {0x380b, 0xe0, 0, 0}, -+ {0x380e, 0x07, 0, 0}, {0x380f, 0xd0, 0, 0}, {0x501f, 0x00, 0, 0}, -+ {0x5000, 0x4f, 0, 0}, {0x4300, 0x30, 0, 0}, {0x3503, 0x07, 0, 0}, -+ {0x3501, 0x73, 0, 0}, {0x3502, 0x80, 0, 0}, {0x350b, 0x00, 0, 0}, -+ {0x3503, 0x07, 0, 0}, {0x3824, 0x11, 0, 0}, {0x3501, 0x1e, 0, 0}, -+ {0x3502, 0x80, 0, 0}, {0x350b, 0x7f, 0, 0}, {0x380c, 0x0c, 0, 0}, -+ {0x380d, 0x80, 0, 0}, {0x380e, 0x03, 0, 0}, {0x380f, 0xe8, 0, 0}, -+ {0x3a0d, 0x04, 0, 0}, {0x3a0e, 0x03, 0, 0}, {0x3818, 0xc1, 0, 0}, -+ {0x3705, 0xdb, 0, 0}, {0x370a, 0x81, 0, 0}, {0x3801, 0x80, 0, 0}, -+ {0x3621, 0x87, 0, 0}, {0x3801, 0x50, 0, 0}, {0x3803, 0x08, 0, 0}, -+ {0x3827, 0x08, 0, 0}, {0x3810, 0x40, 0, 0}, {0x3804, 0x05, 0, 0}, -+ {0x3805, 0x00, 0, 0}, {0x5682, 0x05, 0, 0}, {0x5683, 0x00, 0, 0}, -+ {0x3806, 0x03, 0, 0}, {0x3807, 0xc0, 0, 0}, {0x5686, 0x03, 0, 0}, -+ {0x5687, 0xbc, 0, 0}, {0x3a00, 0x78, 0, 0}, {0x3a1a, 0x05, 0, 0}, -+ {0x3a13, 0x30, 0, 0}, {0x3a18, 0x00, 0, 0}, {0x3a19, 0x7c, 0, 0}, -+ {0x3a08, 0x12, 0, 0}, {0x3a09, 0xc0, 0, 0}, {0x3a0a, 0x0f, 0, 0}, -+ {0x3a0b, 0xa0, 0, 0}, {0x350c, 0x07, 0, 0}, {0x350d, 0xd0, 0, 0}, -+ {0x3500, 0x00, 0, 0}, {0x3501, 0x00, 0, 0}, {0x3502, 0x00, 0, 0}, -+ {0x350a, 0x00, 0, 0}, {0x350b, 0x00, 0, 0}, {0x3503, 0x00, 0, 0}, -+ {0x528a, 0x02, 0, 0}, {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, -+ {0x528d, 0x08, 0, 0}, {0x528e, 0x08, 0, 0}, {0x528f, 0x10, 0, 0}, -+ {0x5290, 0x10, 0, 0}, {0x5292, 0x00, 0, 0}, {0x5293, 0x02, 0, 0}, -+ {0x5294, 0x00, 0, 0}, {0x5295, 0x02, 0, 0}, {0x5296, 0x00, 0, 0}, -+ {0x5297, 0x02, 0, 0}, {0x5298, 0x00, 0, 0}, {0x5299, 0x02, 0, 0}, -+ {0x529a, 0x00, 0, 0}, {0x529b, 0x02, 0, 0}, {0x529c, 0x00, 0, 0}, -+ {0x529d, 0x02, 0, 0}, {0x529e, 0x00, 0, 0}, {0x529f, 0x02, 0, 0}, -+ {0x3a0f, 0x3c, 0, 0}, {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3c, 0, 0}, -+ {0x3a1e, 0x30, 0, 0}, {0x3a11, 0x70, 0, 0}, {0x3a1f, 0x10, 0, 0}, -+ {0x3030, 0x2b, 0, 0}, {0x3a02, 0x00, 0, 0}, {0x3a03, 0x7d, 0, 0}, -+ {0x3a04, 0x00, 0, 0}, {0x3a14, 0x00, 0, 0}, {0x3a15, 0x7d, 0, 0}, -+ {0x3a16, 0x00, 0, 0}, {0x3a00, 0x78, 0, 0}, {0x3a08, 0x09, 0, 0}, -+ {0x3a09, 0x60, 0, 0}, {0x3a0a, 0x07, 0, 0}, {0x3a0b, 0xd0, 0, 0}, -+ {0x3a0d, 0x08, 0, 0}, {0x3a0e, 0x06, 0, 0}, {0x5193, 0x70, 0, 0}, -+ {0x589b, 0x04, 0, 0}, {0x589a, 0xc5, 0, 0}, {0x401e, 0x20, 0, 0}, -+ {0x4001, 0x42, 0, 0}, {0x401c, 0x04, 0, 0}, {0x528a, 0x01, 0, 0}, -+ {0x528b, 0x04, 0, 0}, {0x528c, 0x08, 0, 0}, {0x528d, 0x10, 0, 0}, -+ {0x528e, 0x20, 0, 0}, {0x528f, 0x28, 0, 0}, {0x5290, 0x30, 0, 0}, -+ {0x5292, 0x00, 0, 0}, {0x5293, 0x01, 0, 0}, {0x5294, 0x00, 0, 0}, -+ {0x5295, 0x04, 0, 0}, {0x5296, 0x00, 0, 0}, {0x5297, 0x08, 0, 0}, -+ {0x5298, 0x00, 0, 0}, {0x5299, 0x10, 0, 0}, {0x529a, 0x00, 0, 0}, -+ {0x529b, 0x20, 0, 0}, {0x529c, 0x00, 0, 0}, {0x529d, 0x28, 0, 0}, -+ {0x529e, 0x00, 0, 0}, {0x529f, 0x30, 0, 0}, {0x5282, 0x00, 0, 0}, -+ {0x5300, 0x00, 0, 0}, {0x5301, 0x20, 0, 0}, {0x5302, 0x00, 0, 0}, -+ {0x5303, 0x7c, 0, 0}, {0x530c, 0x00, 0, 0}, {0x530d, 0x0c, 0, 0}, -+ {0x530e, 0x20, 0, 0}, {0x530f, 0x80, 0, 0}, {0x5310, 0x20, 0, 0}, -+ {0x5311, 0x80, 0, 0}, {0x5308, 0x20, 0, 0}, {0x5309, 0x40, 0, 0}, -+ {0x5304, 0x00, 0, 0}, {0x5305, 0x30, 0, 0}, {0x5306, 0x00, 0, 0}, -+ {0x5307, 0x80, 0, 0}, {0x5314, 0x08, 0, 0}, {0x5315, 0x20, 0, 0}, -+ {0x5319, 0x30, 0, 0}, {0x5316, 0x10, 0, 0}, {0x5317, 0x00, 0, 0}, -+ {0x5318, 0x02, 0, 0}, {0x5380, 0x01, 0, 0}, {0x5381, 0x00, 0, 0}, -+ {0x5382, 0x00, 0, 0}, {0x5383, 0x4e, 0, 0}, {0x5384, 0x00, 0, 0}, -+ {0x5385, 0x0f, 0, 0}, {0x5386, 0x00, 0, 0}, {0x5387, 0x00, 0, 0}, -+ {0x5388, 0x01, 0, 0}, {0x5389, 0x15, 0, 0}, {0x538a, 0x00, 0, 0}, -+ {0x538b, 0x31, 0, 0}, {0x538c, 0x00, 0, 0}, {0x538d, 0x00, 0, 0}, -+ {0x538e, 0x00, 0, 0}, {0x538f, 0x0f, 0, 0}, {0x5390, 0x00, 0, 0}, -+ {0x5391, 0xab, 0, 0}, {0x5392, 0x00, 0, 0}, {0x5393, 0xa2, 0, 0}, -+ {0x5394, 0x08, 0, 0}, {0x5480, 0x14, 0, 0}, {0x5481, 0x21, 0, 0}, -+ {0x5482, 0x36, 0, 0}, {0x5483, 0x57, 0, 0}, {0x5484, 0x65, 0, 0}, -+ {0x5485, 0x71, 0, 0}, {0x5486, 0x7d, 0, 0}, {0x5487, 0x87, 0, 0}, -+ {0x5488, 0x91, 0, 0}, {0x5489, 0x9a, 0, 0}, {0x548a, 0xaa, 0, 0}, -+ {0x548b, 0xb8, 0, 0}, {0x548c, 0xcd, 0, 0}, {0x548d, 0xdd, 0, 0}, -+ {0x548e, 0xea, 0, 0}, {0x548f, 0x1d, 0, 0}, {0x5490, 0x05, 0, 0}, -+ {0x5491, 0x00, 0, 0}, {0x5492, 0x04, 0, 0}, {0x5493, 0x20, 0, 0}, -+ {0x5494, 0x03, 0, 0}, {0x5495, 0x60, 0, 0}, {0x5496, 0x02, 0, 0}, -+ {0x5497, 0xb8, 0, 0}, {0x5498, 0x02, 0, 0}, {0x5499, 0x86, 0, 0}, -+ {0x549a, 0x02, 0, 0}, {0x549b, 0x5b, 0, 0}, {0x549c, 0x02, 0, 0}, -+ {0x549d, 0x3b, 0, 0}, {0x549e, 0x02, 0, 0}, {0x549f, 0x1c, 0, 0}, -+ {0x54a0, 0x02, 0, 0}, {0x54a1, 0x04, 0, 0}, {0x54a2, 0x01, 0, 0}, -+ {0x54a3, 0xed, 0, 0}, {0x54a4, 0x01, 0, 0}, {0x54a5, 0xc5, 0, 0}, -+ {0x54a6, 0x01, 0, 0}, {0x54a7, 0xa5, 0, 0}, {0x54a8, 0x01, 0, 0}, -+ {0x54a9, 0x6c, 0, 0}, {0x54aa, 0x01, 0, 0}, {0x54ab, 0x41, 0, 0}, -+ {0x54ac, 0x01, 0, 0}, {0x54ad, 0x20, 0, 0}, {0x54ae, 0x00, 0, 0}, -+ {0x54af, 0x16, 0, 0}, {0x54b0, 0x01, 0, 0}, {0x54b1, 0x20, 0, 0}, -+ {0x54b2, 0x00, 0, 0}, {0x54b3, 0x10, 0, 0}, {0x54b4, 0x00, 0, 0}, -+ {0x54b5, 0xf0, 0, 0}, {0x54b6, 0x00, 0, 0}, {0x54b7, 0xdf, 0, 0}, -+ {0x5402, 0x3f, 0, 0}, {0x5403, 0x00, 0, 0}, {0x3406, 0x00, 0, 0}, -+ {0x5180, 0xff, 0, 0}, {0x5181, 0x52, 0, 0}, {0x5182, 0x11, 0, 0}, -+ {0x5183, 0x14, 0, 0}, {0x5184, 0x25, 0, 0}, {0x5185, 0x24, 0, 0}, -+ {0x5186, 0x06, 0, 0}, {0x5187, 0x08, 0, 0}, {0x5188, 0x08, 0, 0}, -+ {0x5189, 0x7c, 0, 0}, {0x518a, 0x60, 0, 0}, {0x518b, 0xb2, 0, 0}, -+ {0x518c, 0xb2, 0, 0}, {0x518d, 0x44, 0, 0}, {0x518e, 0x3d, 0, 0}, -+ {0x518f, 0x58, 0, 0}, {0x5190, 0x46, 0, 0}, {0x5191, 0xf8, 0, 0}, -+ {0x5192, 0x04, 0, 0}, {0x5193, 0x70, 0, 0}, {0x5194, 0xf0, 0, 0}, -+ {0x5195, 0xf0, 0, 0}, {0x5196, 0x03, 0, 0}, {0x5197, 0x01, 0, 0}, -+ {0x5198, 0x04, 0, 0}, {0x5199, 0x12, 0, 0}, {0x519a, 0x04, 0, 0}, -+ {0x519b, 0x00, 0, 0}, {0x519c, 0x06, 0, 0}, {0x519d, 0x82, 0, 0}, -+ {0x519e, 0x00, 0, 0}, {0x5025, 0x80, 0, 0}, {0x3a0f, 0x38, 0, 0}, -+ {0x3a10, 0x30, 0, 0}, {0x3a1b, 0x3a, 0, 0}, {0x3a1e, 0x2e, 0, 0}, -+ {0x3a11, 0x60, 0, 0}, {0x3a1f, 0x10, 0, 0}, {0x5688, 0xa6, 0, 0}, -+ {0x5689, 0x6a, 0, 0}, {0x568a, 0xea, 0, 0}, {0x568b, 0xae, 0, 0}, -+ {0x568c, 0xa6, 0, 0}, {0x568d, 0x6a, 0, 0}, {0x568e, 0x62, 0, 0}, -+ {0x568f, 0x26, 0, 0}, {0x5583, 0x40, 0, 0}, {0x5584, 0x40, 0, 0}, -+ {0x5580, 0x02, 0, 0}, {0x5000, 0xcf, 0, 0}, {0x5800, 0x27, 0, 0}, -+ {0x5801, 0x19, 0, 0}, {0x5802, 0x12, 0, 0}, {0x5803, 0x0f, 0, 0}, -+ {0x5804, 0x10, 0, 0}, {0x5805, 0x15, 0, 0}, {0x5806, 0x1e, 0, 0}, -+ {0x5807, 0x2f, 0, 0}, {0x5808, 0x15, 0, 0}, {0x5809, 0x0d, 0, 0}, -+ {0x580a, 0x0a, 0, 0}, {0x580b, 0x09, 0, 0}, {0x580c, 0x0a, 0, 0}, -+ {0x580d, 0x0c, 0, 0}, {0x580e, 0x12, 0, 0}, {0x580f, 0x19, 0, 0}, -+ {0x5810, 0x0b, 0, 0}, {0x5811, 0x07, 0, 0}, {0x5812, 0x04, 0, 0}, -+ {0x5813, 0x03, 0, 0}, {0x5814, 0x03, 0, 0}, {0x5815, 0x06, 0, 0}, -+ {0x5816, 0x0a, 0, 0}, {0x5817, 0x0f, 0, 0}, {0x5818, 0x0a, 0, 0}, -+ {0x5819, 0x05, 0, 0}, {0x581a, 0x01, 0, 0}, {0x581b, 0x00, 0, 0}, -+ {0x581c, 0x00, 0, 0}, {0x581d, 0x03, 0, 0}, {0x581e, 0x08, 0, 0}, -+ {0x581f, 0x0c, 0, 0}, {0x5820, 0x0a, 0, 0}, {0x5821, 0x05, 0, 0}, -+ {0x5822, 0x01, 0, 0}, {0x5823, 0x00, 0, 0}, {0x5824, 0x00, 0, 0}, -+ {0x5825, 0x03, 0, 0}, {0x5826, 0x08, 0, 0}, {0x5827, 0x0c, 0, 0}, -+ {0x5828, 0x0e, 0, 0}, {0x5829, 0x08, 0, 0}, {0x582a, 0x06, 0, 0}, -+ {0x582b, 0x04, 0, 0}, {0x582c, 0x05, 0, 0}, {0x582d, 0x07, 0, 0}, -+ {0x582e, 0x0b, 0, 0}, {0x582f, 0x12, 0, 0}, {0x5830, 0x18, 0, 0}, -+ {0x5831, 0x10, 0, 0}, {0x5832, 0x0c, 0, 0}, {0x5833, 0x0a, 0, 0}, -+ {0x5834, 0x0b, 0, 0}, {0x5835, 0x0e, 0, 0}, {0x5836, 0x15, 0, 0}, -+ {0x5837, 0x19, 0, 0}, {0x5838, 0x32, 0, 0}, {0x5839, 0x1f, 0, 0}, -+ {0x583a, 0x18, 0, 0}, {0x583b, 0x16, 0, 0}, {0x583c, 0x17, 0, 0}, -+ {0x583d, 0x1e, 0, 0}, {0x583e, 0x26, 0, 0}, {0x583f, 0x53, 0, 0}, -+ {0x5840, 0x10, 0, 0}, {0x5841, 0x0f, 0, 0}, {0x5842, 0x0d, 0, 0}, -+ {0x5843, 0x0c, 0, 0}, {0x5844, 0x0e, 0, 0}, {0x5845, 0x09, 0, 0}, -+ {0x5846, 0x11, 0, 0}, {0x5847, 0x10, 0, 0}, {0x5848, 0x10, 0, 0}, -+ {0x5849, 0x10, 0, 0}, {0x584a, 0x10, 0, 0}, {0x584b, 0x0e, 0, 0}, -+ {0x584c, 0x10, 0, 0}, {0x584d, 0x10, 0, 0}, {0x584e, 0x11, 0, 0}, -+ {0x584f, 0x10, 0, 0}, {0x5850, 0x0f, 0, 0}, {0x5851, 0x0c, 0, 0}, -+ {0x5852, 0x0f, 0, 0}, {0x5853, 0x10, 0, 0}, {0x5854, 0x10, 0, 0}, -+ {0x5855, 0x0f, 0, 0}, {0x5856, 0x0e, 0, 0}, {0x5857, 0x0b, 0, 0}, -+ {0x5858, 0x10, 0, 0}, {0x5859, 0x0d, 0, 0}, {0x585a, 0x0d, 0, 0}, -+ {0x585b, 0x0c, 0, 0}, {0x585c, 0x0c, 0, 0}, {0x585d, 0x0c, 0, 0}, -+ {0x585e, 0x0b, 0, 0}, {0x585f, 0x0c, 0, 0}, {0x5860, 0x0c, 0, 0}, -+ {0x5861, 0x0c, 0, 0}, {0x5862, 0x0d, 0, 0}, {0x5863, 0x08, 0, 0}, -+ {0x5864, 0x11, 0, 0}, {0x5865, 0x18, 0, 0}, {0x5866, 0x18, 0, 0}, -+ {0x5867, 0x19, 0, 0}, {0x5868, 0x17, 0, 0}, {0x5869, 0x19, 0, 0}, -+ {0x586a, 0x16, 0, 0}, {0x586b, 0x13, 0, 0}, {0x586c, 0x13, 0, 0}, -+ {0x586d, 0x12, 0, 0}, {0x586e, 0x13, 0, 0}, {0x586f, 0x16, 0, 0}, -+ {0x5870, 0x14, 0, 0}, {0x5871, 0x12, 0, 0}, {0x5872, 0x10, 0, 0}, -+ {0x5873, 0x11, 0, 0}, {0x5874, 0x11, 0, 0}, {0x5875, 0x16, 0, 0}, -+ {0x5876, 0x14, 0, 0}, {0x5877, 0x11, 0, 0}, {0x5878, 0x10, 0, 0}, -+ {0x5879, 0x0f, 0, 0}, {0x587a, 0x10, 0, 0}, {0x587b, 0x14, 0, 0}, -+ {0x587c, 0x13, 0, 0}, {0x587d, 0x12, 0, 0}, {0x587e, 0x11, 0, 0}, -+ {0x587f, 0x11, 0, 0}, {0x5880, 0x12, 0, 0}, {0x5881, 0x15, 0, 0}, -+ {0x5882, 0x14, 0, 0}, {0x5883, 0x15, 0, 0}, {0x5884, 0x15, 0, 0}, -+ {0x5885, 0x15, 0, 0}, {0x5886, 0x13, 0, 0}, {0x5887, 0x17, 0, 0}, -+ {0x3710, 0x10, 0, 0}, {0x3632, 0x51, 0, 0}, {0x3702, 0x10, 0, 0}, -+ {0x3703, 0xb2, 0, 0}, {0x3704, 0x18, 0, 0}, {0x370b, 0x40, 0, 0}, -+ {0x370d, 0x03, 0, 0}, {0x3631, 0x01, 0, 0}, {0x3632, 0x52, 0, 0}, -+ {0x3606, 0x24, 0, 0}, {0x3620, 0x96, 0, 0}, {0x5785, 0x07, 0, 0}, -+ {0x3a13, 0x30, 0, 0}, {0x3600, 0x52, 0, 0}, {0x3604, 0x48, 0, 0}, -+ {0x3606, 0x1b, 0, 0}, {0x370d, 0x0b, 0, 0}, {0x370f, 0xc0, 0, 0}, -+ {0x3709, 0x01, 0, 0}, {0x3823, 0x00, 0, 0}, {0x5007, 0x00, 0, 0}, -+ {0x5009, 0x00, 0, 0}, {0x5011, 0x00, 0, 0}, {0x5013, 0x00, 0, 0}, -+ {0x519e, 0x00, 0, 0}, {0x5086, 0x00, 0, 0}, {0x5087, 0x00, 0, 0}, -+ {0x5088, 0x00, 0, 0}, {0x5089, 0x00, 0, 0}, {0x302b, 0x00, 0, 0}, -+ {0x3824, 0x11, 0, 0}, {0x3825, 0xdc, 0, 0}, {0x3826, 0x00, 0, 0}, -+ {0x3827, 0x08, 0, 0}, {0x380c, 0x0c, 0, 0}, {0x380d, 0x80, 0, 0}, -+ {0x380e, 0x03, 0, 0}, {0x380f, 0xe8, 0, 0}, {0x3808, 0x02, 0, 0}, -+ {0x3809, 0xd0, 0, 0}, {0x380A, 0x02, 0, 0}, {0x380B, 0x40, 0, 0}, -+ {0x3804, 0x04, 0, 0}, {0x3805, 0xb0, 0, 0}, {0x3806, 0x03, 0, 0}, -+ {0x3807, 0xc0, 0, 0}, {0x5686, 0x03, 0, 0}, {0x5687, 0xc0, 0, 0}, -+ {0x5682, 0x04, 0, 0}, {0x5683, 0xb0, 0, 0}, -+}; -+ -+static struct ov5642_mode_info ov5642_mode_info_data[2][ov5642_mode_MAX + 1] = { -+ { -+ {ov5642_mode_VGA_640_480, 640, 480, -+ ov5642_setting_15fps_VGA_640_480, -+ ARRAY_SIZE(ov5642_setting_15fps_VGA_640_480)}, -+ {ov5642_mode_QVGA_320_240, 320, 240, -+ ov5642_setting_15fps_QVGA_320_240, -+ ARRAY_SIZE(ov5642_setting_15fps_QVGA_320_240)}, -+ {ov5642_mode_NTSC_720_480, 720, 480, -+ ov5642_setting_15fps_NTSC_720_480, -+ ARRAY_SIZE(ov5642_setting_15fps_NTSC_720_480)}, -+ {ov5642_mode_PAL_720_576, 720, 576, -+ ov5642_setting_15fps_PAL_720_576, -+ ARRAY_SIZE(ov5642_setting_15fps_PAL_720_576)}, -+ {ov5642_mode_720P_1280_720, 1280, 720, -+ ov5642_setting_15fps_720P_1280_720, -+ ARRAY_SIZE(ov5642_setting_15fps_720P_1280_720)}, -+ {ov5642_mode_1080P_1920_1080, 1920, 1080, -+ ov5642_setting_15fps_1080P_1920_1080, -+ ARRAY_SIZE(ov5642_setting_15fps_1080P_1920_1080)}, -+ {ov5642_mode_QSXGA_2592_1944, 2592, 1944, -+ ov5642_setting_15fps_QSXGA_2592_1944, -+ ARRAY_SIZE(ov5642_setting_15fps_QSXGA_2592_1944)}, -+ {ov5642_mode_QCIF_176_144, 176, 144, -+ ov5642_setting_15fps_QCIF_176_144, -+ ARRAY_SIZE(ov5642_setting_15fps_QCIF_176_144)}, -+ {ov5642_mode_XGA_1024_768, 1024, 768, -+ ov5642_setting_15fps_XGA_1024_768, -+ ARRAY_SIZE(ov5642_setting_15fps_XGA_1024_768)}, -+ }, -+ { -+ {ov5642_mode_VGA_640_480, 640, 480, -+ ov5642_setting_30fps_VGA_640_480, -+ ARRAY_SIZE(ov5642_setting_30fps_VGA_640_480)}, -+ {ov5642_mode_QVGA_320_240, 320, 240, -+ ov5642_setting_30fps_QVGA_320_240, -+ ARRAY_SIZE(ov5642_setting_30fps_QVGA_320_240)}, -+ {ov5642_mode_NTSC_720_480, 720, 480, -+ ov5642_setting_30fps_NTSC_720_480, -+ ARRAY_SIZE(ov5642_setting_30fps_NTSC_720_480)}, -+ {ov5642_mode_PAL_720_576, 720, 576, -+ ov5642_setting_30fps_PAL_720_576, -+ ARRAY_SIZE(ov5642_setting_30fps_PAL_720_576)}, -+ {ov5642_mode_720P_1280_720, 1280, 720, -+ ov5642_setting_30fps_720P_1280_720, -+ ARRAY_SIZE(ov5642_setting_30fps_720P_1280_720)}, -+ {ov5642_mode_1080P_1920_1080, 0, 0, NULL, 0}, -+ {ov5642_mode_QSXGA_2592_1944, 0, 0, NULL, 0}, -+ {ov5642_mode_QCIF_176_144, 176, 144, -+ ov5642_setting_30fps_QCIF_176_144, -+ ARRAY_SIZE(ov5642_setting_30fps_QCIF_176_144)}, -+ {ov5642_mode_XGA_1024_768, 1024, 768, -+ ov5642_setting_30fps_XGA_1024_768, -+ ARRAY_SIZE(ov5642_setting_30fps_XGA_1024_768)}, -+ }, -+}; -+ -+static struct regulator *io_regulator; -+static struct regulator *core_regulator; -+static struct regulator *analog_regulator; -+static struct regulator *gpo_regulator; -+ -+static int ov5642_probe(struct i2c_client *adapter, -+ const struct i2c_device_id *device_id); -+static int ov5642_remove(struct i2c_client *client); -+ -+static s32 ov5642_read_reg(u16 reg, u8 *val); -+static s32 ov5642_write_reg(u16 reg, u8 val); -+ -+static const struct i2c_device_id ov5642_id[] = { -+ {"ov5642", 0}, -+ {"ov564x", 0}, -+ {}, -+}; -+ -+MODULE_DEVICE_TABLE(i2c, ov5642_id); -+ -+static struct i2c_driver ov5642_i2c_driver = { -+ .driver = { -+ .owner = THIS_MODULE, -+ .name = "ov5642", -+ }, -+ .probe = ov5642_probe, -+ .remove = ov5642_remove, -+ .id_table = ov5642_id, -+}; -+ -+static void ov5642_standby(s32 enable) -+{ -+ if (enable) -+ gpio_set_value(pwn_gpio, 1); -+ else -+ gpio_set_value(pwn_gpio, 0); -+ -+ msleep(2); -+} -+ -+static void ov5642_reset(void) -+{ -+ /* camera reset */ -+ gpio_set_value(rst_gpio, 1); -+ -+ /* camera power down */ -+ gpio_set_value(pwn_gpio, 1); -+ msleep(5); -+ -+ gpio_set_value(pwn_gpio, 0); -+ msleep(5); -+ -+ gpio_set_value(rst_gpio, 0); -+ msleep(1); -+ -+ gpio_set_value(rst_gpio, 1); -+ msleep(5); -+ -+ gpio_set_value(pwn_gpio, 1); -+} -+ -+static int ov5642_power_on(struct device *dev) -+{ -+ int ret = 0; -+ -+ io_regulator = devm_regulator_get(dev, "DOVDD"); -+ if (!IS_ERR(io_regulator)) { -+ regulator_set_voltage(io_regulator, -+ OV5642_VOLTAGE_DIGITAL_IO, -+ OV5642_VOLTAGE_DIGITAL_IO); -+ ret = regulator_enable(io_regulator); -+ if (ret) { -+ pr_err("%s:io set voltage error\n", __func__); -+ return ret; -+ } else { -+ dev_dbg(dev, -+ "%s:io set voltage ok\n", __func__); -+ } -+ } else { -+ pr_err("%s: cannot get io voltage error\n", __func__); -+ io_regulator = NULL; -+ } -+ -+ core_regulator = devm_regulator_get(dev, "DVDD"); -+ if (!IS_ERR(core_regulator)) { -+ regulator_set_voltage(core_regulator, -+ OV5642_VOLTAGE_DIGITAL_CORE, -+ OV5642_VOLTAGE_DIGITAL_CORE); -+ ret = regulator_enable(core_regulator); -+ if (ret) { -+ pr_err("%s:core set voltage error\n", __func__); -+ return ret; -+ } else { -+ dev_dbg(dev, -+ "%s:core set voltage ok\n", __func__); -+ } -+ } else { -+ core_regulator = NULL; -+ pr_err("%s: cannot get core voltage error\n", __func__); -+ } -+ -+ analog_regulator = devm_regulator_get(dev, "AVDD"); -+ if (!IS_ERR(analog_regulator)) { -+ regulator_set_voltage(analog_regulator, -+ OV5642_VOLTAGE_ANALOG, -+ OV5642_VOLTAGE_ANALOG); -+ ret = regulator_enable(analog_regulator); -+ if (ret) { -+ pr_err("%s:analog set voltage error\n", -+ __func__); -+ return ret; -+ } else { -+ dev_dbg(dev, -+ "%s:analog set voltage ok\n", __func__); -+ } -+ } else { -+ analog_regulator = NULL; -+ pr_err("%s: cannot get analog voltage error\n", __func__); -+ } -+ -+ return ret; -+} -+ -+static s32 ov5642_write_reg(u16 reg, u8 val) -+{ -+ u8 au8Buf[3] = {0}; -+ -+ au8Buf[0] = reg >> 8; -+ au8Buf[1] = reg & 0xff; -+ au8Buf[2] = val; -+ -+ if (i2c_master_send(ov5642_data.i2c_client, au8Buf, 3) < 0) { -+ pr_err("%s:write reg error:reg=%x,val=%x\n", -+ __func__, reg, val); -+ return -1; -+ } -+ -+ return 0; -+} -+ -+static s32 ov5642_read_reg(u16 reg, u8 *val) -+{ -+ u8 au8RegBuf[2] = {0}; -+ u8 u8RdVal = 0; -+ -+ au8RegBuf[0] = reg >> 8; -+ au8RegBuf[1] = reg & 0xff; -+ -+ if (2 != i2c_master_send(ov5642_data.i2c_client, au8RegBuf, 2)) { -+ pr_err("%s:write reg error:reg=%x\n", -+ __func__, reg); -+ return -1; -+ } -+ -+ if (1 != i2c_master_recv(ov5642_data.i2c_client, &u8RdVal, 1)) { -+ pr_err("%s:read reg error:reg=%x,val=%x\n", -+ __func__, reg, u8RdVal); -+ return -1; -+ } -+ -+ *val = u8RdVal; -+ -+ return u8RdVal; -+} -+ -+static int ov5642_set_idle_mode(void) { -+ register u16 RegAddr = 0; -+ u8 ReadVal = 0; -+ u8 WriteVal = 0; -+ int retval = 0; -+ int lc = 0; -+ -+ ReadVal = -1; -+ RegAddr = REG_STA_FOCUS; -+ retval = ov5642_read_reg(RegAddr, &ReadVal); -+ if (retval < 0) { -+ pr_err("%s, read reg 0x%x failed\n", __FUNCTION__, RegAddr); -+ } -+ -+ for (lc = 0; (lc < 100) && (ReadVal != S_IDLE); ++lc) { -+ WriteVal = CMD_IDLE_MODE; -+ RegAddr = REG_CMD_MAIN; -+ retval = ov5642_write_reg(RegAddr, WriteVal); -+ if (retval < 0) { -+ pr_err("%s, write reg 0x%x failed\n", __FUNCTION__, RegAddr); -+ } -+ -+ mdelay(1); -+ -+ ReadVal = -1; -+ RegAddr = REG_STA_FOCUS; -+ retval = ov5642_read_reg(RegAddr, &ReadVal); -+ if (retval < 0) { -+ pr_err("%s, read reg 0x%x failed\n", __FUNCTION__, RegAddr); -+ } -+ } -+ -+ if (ReadVal != S_IDLE) -+ retval = -1; -+ else -+ retval = 0; -+ return retval; -+} -+ -+static int ov5642_config_auto_focus(void){ -+ ov5642_write_reg(REG_CMD_TAG, 0x01); -+ ov5642_write_reg(REG_CMD_MAIN, 0x10); -+ return 0; -+} -+ -+static int ov5642_set_rot_mode(struct reg_value *rot_mode) -+{ -+ s32 i = 0; -+ s32 iModeSettingArySize = 2; -+ register u32 Delay_ms = 0; -+ register u16 RegAddr = 0; -+ register u8 Mask = 0; -+ register u8 Val = 0; -+ u8 RegVal = 0; -+ int retval = 0; -+ for (i = 0; i < iModeSettingArySize; ++i, ++rot_mode) { -+ Delay_ms = rot_mode->u32Delay_ms; -+ RegAddr = rot_mode->u16RegAddr; -+ Val = rot_mode->u8Val; -+ Mask = rot_mode->u8Mask; -+ -+ if (Mask) { -+ retval = ov5642_read_reg(RegAddr, &RegVal); -+ if (retval < 0) { -+ pr_err("%s, read reg 0x%x failed\n", -+ __func__, RegAddr); -+ goto err; -+ } -+ -+ Val |= RegVal; -+ Val &= Mask; -+ } -+ -+ retval = ov5642_write_reg(RegAddr, Val); -+ if (retval < 0) { -+ pr_err("%s, write reg 0x%x failed\n", -+ __func__, RegAddr); -+ goto err; -+ } -+ -+ if (Delay_ms) -+ mdelay(Delay_ms); -+ } -+err: -+ return retval; -+} -+ -+static int ov5642_auto_focus_start(void) { -+ register u16 RegAddr = 0; -+ u8 RegVal = 0; -+ int retval = 0; -+ -+ retval = ov5642_set_idle_mode(); -+ ov5642_config_auto_focus(); -+ -+ if (retval > -1) { -+ RegVal = CMD_SINGLE_FOCUS_MODE; -+ RegAddr = REG_CMD_MAIN; -+ retval = ov5642_write_reg(RegAddr, RegVal); -+ if (retval < 0) { -+ pr_err("%s, write reg 0x%x failed\n", __FUNCTION__, RegAddr); -+ } -+ } else { -+ pr_err("Could not get camera into idle mode. Abandoning focus attempt"); -+ } -+ -+ return retval; -+} -+ -+static int ov5642_init_mode(enum ov5642_frame_rate frame_rate, -+ enum ov5642_mode mode); -+static int ov5642_write_snapshot_para(enum ov5642_frame_rate frame_rate, -+ enum ov5642_mode mode); -+static int ov5642_change_mode(enum ov5642_frame_rate new_frame_rate, -+ enum ov5642_frame_rate old_frame_rate, -+ enum ov5642_mode new_mode, -+ enum ov5642_mode orig_mode) -+{ -+ struct reg_value *pModeSetting = NULL; -+ s32 i = 0; -+ s32 iModeSettingArySize = 0; -+ register u32 Delay_ms = 0; -+ register u16 RegAddr = 0; -+ register u8 Mask = 0; -+ register u8 Val = 0; -+ u8 RegVal = 0; -+ int retval = 0; -+ -+ if (new_mode > ov5642_mode_MAX || new_mode < ov5642_mode_MIN) { -+ pr_err("Wrong ov5642 mode detected!\n"); -+ return -1; -+ } -+ -+ if ((new_frame_rate == old_frame_rate) && -+ (new_mode == ov5642_mode_VGA_640_480) && -+ (orig_mode == ov5642_mode_QSXGA_2592_1944)) { -+ pModeSetting = ov5642_setting_QSXGA_2_VGA; -+ iModeSettingArySize = ARRAY_SIZE(ov5642_setting_QSXGA_2_VGA); -+ ov5642_data.pix.width = 640; -+ ov5642_data.pix.height = 480; -+ } else if ((new_frame_rate == old_frame_rate) && -+ (new_mode == ov5642_mode_QVGA_320_240) && -+ (orig_mode == ov5642_mode_VGA_640_480)) { -+ pModeSetting = ov5642_setting_VGA_2_QVGA; -+ iModeSettingArySize = ARRAY_SIZE(ov5642_setting_VGA_2_QVGA); -+ ov5642_data.pix.width = 320; -+ ov5642_data.pix.height = 240; -+ } else { -+ retval = ov5642_write_snapshot_para(new_frame_rate, new_mode); -+ goto err; -+ } -+ -+ if (ov5642_data.pix.width == 0 || ov5642_data.pix.height == 0 || -+ pModeSetting == NULL || iModeSettingArySize == 0) -+ return -EINVAL; -+ -+ for (i = 0; i < iModeSettingArySize; ++i, ++pModeSetting) { -+ Delay_ms = pModeSetting->u32Delay_ms; -+ RegAddr = pModeSetting->u16RegAddr; -+ Val = pModeSetting->u8Val; -+ Mask = pModeSetting->u8Mask; -+ -+ if (Mask) { -+ retval = ov5642_read_reg(RegAddr, &RegVal); -+ if (retval < 0) { -+ pr_err("read reg error addr=0x%x", RegAddr); -+ goto err; -+ } -+ -+ RegVal &= ~(u8)Mask; -+ Val &= Mask; -+ Val |= RegVal; -+ } -+ -+ retval = ov5642_write_reg(RegAddr, Val); -+ if (retval < 0) { -+ pr_err("write reg error addr=0x%x", RegAddr); -+ goto err; -+ } -+ -+ if (Delay_ms) -+ msleep(Delay_ms); -+ } -+err: -+ return retval; -+} -+static int ov5642_init_mode(enum ov5642_frame_rate frame_rate, -+ enum ov5642_mode mode) -+{ -+ struct reg_value *pModeSetting = NULL; -+ s32 i = 0; -+ s32 iModeSettingArySize = 0; -+ register u32 Delay_ms = 0; -+ register u16 RegAddr = 0; -+ register u8 Mask = 0; -+ register u8 Val = 0; -+ u8 RegVal = 0; -+ int retval = 0; -+ -+ if (mode > ov5642_mode_MAX || mode < ov5642_mode_MIN) { -+ pr_err("Wrong ov5642 mode detected!\n"); -+ return -1; -+ } -+ -+ pModeSetting = ov5642_mode_info_data[frame_rate][mode].init_data_ptr; -+ iModeSettingArySize = -+ ov5642_mode_info_data[frame_rate][mode].init_data_size; -+ -+ ov5642_data.pix.width = ov5642_mode_info_data[frame_rate][mode].width; -+ ov5642_data.pix.height = ov5642_mode_info_data[frame_rate][mode].height; -+ -+ if (ov5642_data.pix.width == 0 || ov5642_data.pix.height == 0 || -+ pModeSetting == NULL || iModeSettingArySize == 0) -+ return -EINVAL; -+ -+ for (i = 0; i < iModeSettingArySize; ++i, ++pModeSetting) { -+ Delay_ms = pModeSetting->u32Delay_ms; -+ RegAddr = pModeSetting->u16RegAddr; -+ Val = pModeSetting->u8Val; -+ Mask = pModeSetting->u8Mask; -+ -+ if (Mask) { -+ retval = ov5642_read_reg(RegAddr, &RegVal); -+ if (retval < 0) { -+ pr_err("read reg error addr=0x%x", RegAddr); -+ goto err; -+ } -+ -+ RegVal &= ~(u8)Mask; -+ Val &= Mask; -+ Val |= RegVal; -+ } -+ -+ retval = ov5642_write_reg(RegAddr, Val); -+ if (retval < 0) { -+ pr_err("write reg error addr=0x%x", RegAddr); -+ goto err; -+ } -+ -+ if (Delay_ms) -+ msleep(Delay_ms); -+ } -+err: -+ return retval; -+} -+ -+static int ov5642_write_snapshot_para(enum ov5642_frame_rate frame_rate, -+ enum ov5642_mode mode) -+{ -+ int ret = 0; -+ bool m_60Hz = false; -+ u16 cap_frame_rate = 50; -+ u16 g_prev_frame_rate = 225; -+ -+ u8 ev_low, ev_mid, ev_high; -+ u8 ret_l, ret_m, ret_h, gain, lines_10ms; -+ u16 ulcap_ev, icap_gain, prev_maxlines; -+ u32 ulcap_ev_gain, cap_maxlines, g_prev_ev; -+ -+ ov5642_write_reg(0x3503, 0x07); -+ -+ ret_h = ret_m = ret_l = 0; -+ g_prev_ev = 0; -+ ov5642_read_reg(0x3500, &ret_h); -+ ov5642_read_reg(0x3501, &ret_m); -+ ov5642_read_reg(0x3502, &ret_l); -+ g_prev_ev = (ret_h << 12) + (ret_m << 4) + (ret_l >> 4); -+ -+ ret_h = ret_m = ret_l = 0; -+ prev_maxlines = 0; -+ ov5642_read_reg(0x380e, &ret_h); -+ ov5642_read_reg(0x380f, &ret_l); -+ prev_maxlines = (ret_h << 8) + ret_l; -+ /*Read back AGC Gain for preview*/ -+ gain = 0; -+ ov5642_read_reg(0x350b, &gain); -+ -+ ret = ov5642_init_mode(frame_rate, mode); -+ if (ret < 0) -+ return ret; -+ -+ ret_h = ret_m = ret_l = 0; -+ ov5642_read_reg(0x380e, &ret_h); -+ ov5642_read_reg(0x380f, &ret_l); -+ cap_maxlines = (ret_h << 8) + ret_l; -+ if (m_60Hz == true) -+ lines_10ms = cap_frame_rate * cap_maxlines/12000; -+ else -+ lines_10ms = cap_frame_rate * cap_maxlines/10000; -+ -+ if (prev_maxlines == 0) -+ prev_maxlines = 1; -+ -+ ulcap_ev = (g_prev_ev*(cap_frame_rate)*(cap_maxlines))/ -+ (((prev_maxlines)*(g_prev_frame_rate))); -+ icap_gain = (gain & 0x0f) + 16; -+ if (gain & 0x10) -+ icap_gain = icap_gain << 1; -+ -+ if (gain & 0x20) -+ icap_gain = icap_gain << 1; -+ -+ if (gain & 0x40) -+ icap_gain = icap_gain << 1; -+ -+ if (gain & 0x80) -+ icap_gain = icap_gain << 1; -+ -+ ulcap_ev_gain = 2 * ulcap_ev * icap_gain; -+ -+ if (ulcap_ev_gain < cap_maxlines*16) { -+ ulcap_ev = ulcap_ev_gain/16; -+ if (ulcap_ev > lines_10ms) { -+ ulcap_ev /= lines_10ms; -+ ulcap_ev *= lines_10ms; -+ } -+ } else -+ ulcap_ev = cap_maxlines; -+ -+ if (ulcap_ev == 0) -+ ulcap_ev = 1; -+ -+ icap_gain = (ulcap_ev_gain*2/ulcap_ev + 1)/2; -+ ev_low = ((unsigned char)ulcap_ev)<<4; -+ ev_mid = (unsigned char)(ulcap_ev >> 4) & 0xff; -+ ev_high = (unsigned char)(ulcap_ev >> 12); -+ -+ gain = 0; -+ if (icap_gain > 31) { -+ gain |= 0x10; -+ icap_gain = icap_gain >> 1; -+ } -+ if (icap_gain > 31) { -+ gain |= 0x20; -+ icap_gain = icap_gain >> 1; -+ } -+ if (icap_gain > 31) { -+ gain |= 0x40; -+ icap_gain = icap_gain >> 1; -+ } -+ if (icap_gain > 31) { -+ gain |= 0x80; -+ icap_gain = icap_gain >> 1; -+ } -+ if (icap_gain > 16) -+ gain |= ((icap_gain - 16) & 0x0f); -+ -+ if (gain == 0x10) -+ gain = 0x11; -+ -+ ov5642_write_reg(0x350b, gain); -+ ov5642_write_reg(0x3502, ev_low); -+ ov5642_write_reg(0x3501, ev_mid); -+ ov5642_write_reg(0x3500, ev_high); -+ msleep(500); -+ -+ return ret ; -+} -+ -+ -+/* --------------- IOCTL functions from v4l2_int_ioctl_desc --------------- */ -+ -+static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p) -+{ -+ if (s == NULL) { -+ pr_err(" ERROR!! no slave device set!\n"); -+ return -1; -+ } -+ -+ memset(p, 0, sizeof(*p)); -+ p->u.bt656.clock_curr = ov5642_data.mclk; -+ pr_debug(" clock_curr=mclk=%d\n", ov5642_data.mclk); -+ p->if_type = V4L2_IF_TYPE_BT656; -+ p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT; -+ p->u.bt656.clock_min = OV5642_XCLK_MIN; -+ p->u.bt656.clock_max = OV5642_XCLK_MAX; -+ p->u.bt656.bt_sync_correct = 1; /* Indicate external vsync */ -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_s_power - V4L2 sensor interface handler for VIDIOC_S_POWER ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @on: indicates power mode (on or off) -+ * -+ * Turns the power on or off, depending on the value of on and returns the -+ * appropriate error code. -+ */ -+static int ioctl_s_power(struct v4l2_int_device *s, int on) -+{ -+ struct sensor_data *sensor = s->priv; -+ -+ if (on && !sensor->on) { -+ if (io_regulator) -+ if (regulator_enable(io_regulator) != 0) -+ return -EIO; -+ if (core_regulator) -+ if (regulator_enable(core_regulator) != 0) -+ return -EIO; -+ if (gpo_regulator) -+ if (regulator_enable(gpo_regulator) != 0) -+ return -EIO; -+ if (analog_regulator) -+ if (regulator_enable(analog_regulator) != 0) -+ return -EIO; -+ /* Make sure power on */ -+ ov5642_standby(0); -+ } else if (!on && sensor->on) { -+ if (analog_regulator) -+ regulator_disable(analog_regulator); -+ if (core_regulator) -+ regulator_disable(core_regulator); -+ if (io_regulator) -+ regulator_disable(io_regulator); -+ if (gpo_regulator) -+ regulator_disable(gpo_regulator); -+ -+ ov5642_standby(1); -+ } -+ -+ sensor->on = on; -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure -+ * -+ * Returns the sensor's video CAPTURE parameters. -+ */ -+static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) -+{ -+ struct sensor_data *sensor = s->priv; -+ struct v4l2_captureparm *cparm = &a->parm.capture; -+ int ret = 0; -+ -+ switch (a->type) { -+ /* This is the only case currently handled. */ -+ case V4L2_BUF_TYPE_VIDEO_CAPTURE: -+ memset(a, 0, sizeof(*a)); -+ a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; -+ cparm->capability = sensor->streamcap.capability; -+ cparm->timeperframe = sensor->streamcap.timeperframe; -+ cparm->capturemode = sensor->streamcap.capturemode; -+ ret = 0; -+ break; -+ -+ /* These are all the possible cases. */ -+ case V4L2_BUF_TYPE_VIDEO_OUTPUT: -+ case V4L2_BUF_TYPE_VIDEO_OVERLAY: -+ case V4L2_BUF_TYPE_VBI_CAPTURE: -+ case V4L2_BUF_TYPE_VBI_OUTPUT: -+ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: -+ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: -+ ret = -EINVAL; -+ break; -+ -+ default: -+ pr_debug(" type is unknown - %d\n", a->type); -+ ret = -EINVAL; -+ break; -+ } -+ -+ return ret; -+} -+ -+/*! -+ * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure -+ * -+ * Configures the sensor to use the input parameters, if possible. If -+ * not possible, reverts to the old parameters and returns the -+ * appropriate error code. -+ */ -+static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) -+{ -+ struct sensor_data *sensor = s->priv; -+ struct v4l2_fract *timeperframe = &a->parm.capture.timeperframe; -+ u32 tgt_fps, old_fps; /* target frames per secound */ -+ enum ov5642_frame_rate new_frame_rate, old_frame_rate; -+ int ret = 0; -+ -+ /* Make sure power on */ -+ ov5642_standby(0); -+ -+ switch (a->type) { -+ /* This is the only case currently handled. */ -+ case V4L2_BUF_TYPE_VIDEO_CAPTURE: -+ /* Check that the new frame rate is allowed. */ -+ if ((timeperframe->numerator == 0) || -+ (timeperframe->denominator == 0)) { -+ timeperframe->denominator = DEFAULT_FPS; -+ timeperframe->numerator = 1; -+ } -+ -+ tgt_fps = timeperframe->denominator / -+ timeperframe->numerator; -+ -+ if (tgt_fps > MAX_FPS) { -+ timeperframe->denominator = MAX_FPS; -+ timeperframe->numerator = 1; -+ } else if (tgt_fps < MIN_FPS) { -+ timeperframe->denominator = MIN_FPS; -+ timeperframe->numerator = 1; -+ } -+ -+ /* Actual frame rate we use */ -+ tgt_fps = timeperframe->denominator / -+ timeperframe->numerator; -+ -+ if (tgt_fps == 15) -+ new_frame_rate = ov5642_15_fps; -+ else if (tgt_fps == 30) -+ new_frame_rate = ov5642_30_fps; -+ else { -+ pr_err(" The camera frame rate is not supported!\n"); -+ return -EINVAL; -+ } -+ -+ if (sensor->streamcap.timeperframe.numerator != 0) -+ old_fps = sensor->streamcap.timeperframe.denominator / -+ sensor->streamcap.timeperframe.numerator; -+ else -+ old_fps = 30; -+ -+ if (old_fps == 15) -+ old_frame_rate = ov5642_15_fps; -+ else if (old_fps == 30) -+ old_frame_rate = ov5642_30_fps; -+ else { -+ pr_warning(" No valid frame rate set!\n"); -+ old_frame_rate = ov5642_30_fps; -+ } -+ -+ ret = ov5642_change_mode(new_frame_rate, old_frame_rate, -+ a->parm.capture.capturemode, -+ sensor->streamcap.capturemode); -+ if (ret < 0) -+ return ret; -+ -+ sensor->streamcap.timeperframe = *timeperframe; -+ sensor->streamcap.capturemode = -+ (u32)a->parm.capture.capturemode; -+ break; -+ -+ /* These are all the possible cases. */ -+ case V4L2_BUF_TYPE_VIDEO_OUTPUT: -+ case V4L2_BUF_TYPE_VIDEO_OVERLAY: -+ case V4L2_BUF_TYPE_VBI_CAPTURE: -+ case V4L2_BUF_TYPE_VBI_OUTPUT: -+ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: -+ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: -+ pr_debug(" type is not " \ -+ "V4L2_BUF_TYPE_VIDEO_CAPTURE but %d\n", -+ a->type); -+ ret = -EINVAL; -+ break; -+ -+ default: -+ pr_debug(" type is unknown - %d\n", a->type); -+ ret = -EINVAL; -+ break; -+ } -+ -+ return ret; -+} -+ -+/*! -+ * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap -+ * @s: pointer to standard V4L2 device structure -+ * @f: pointer to standard V4L2 v4l2_format structure -+ * -+ * Returns the sensor's current pixel format in the v4l2_format -+ * parameter. -+ */ -+static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) -+{ -+ struct sensor_data *sensor = s->priv; -+ -+ f->fmt.pix = sensor->pix; -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure -+ * -+ * If the requested control is supported, returns the control's current -+ * value from the video_control[] array. Otherwise, returns -EINVAL -+ * if the control is not supported. -+ */ -+static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) -+{ -+ int ret = 0; -+ -+ switch (vc->id) { -+ case V4L2_CID_BRIGHTNESS: -+ vc->value = ov5642_data.brightness; -+ break; -+ case V4L2_CID_HUE: -+ vc->value = ov5642_data.hue; -+ break; -+ case V4L2_CID_CONTRAST: -+ vc->value = ov5642_data.contrast; -+ break; -+ case V4L2_CID_SATURATION: -+ vc->value = ov5642_data.saturation; -+ break; -+ case V4L2_CID_RED_BALANCE: -+ vc->value = ov5642_data.red; -+ break; -+ case V4L2_CID_BLUE_BALANCE: -+ vc->value = ov5642_data.blue; -+ break; -+ case V4L2_CID_EXPOSURE: -+ vc->value = ov5642_data.ae_mode; -+ break; -+ default: -+ ret = -EINVAL; -+ } -+ -+ return ret; -+} -+ -+/*! -+ * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure -+ * -+ * If the requested control is supported, sets the control's current -+ * value in HW (and updates the video_control[] array). Otherwise, -+ * returns -EINVAL if the control is not supported. -+ */ -+static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) -+{ -+ int retval = 0; -+ struct sensor_data *sensor = s->priv; -+ __u32 captureMode = sensor->streamcap.capturemode; -+ struct reg_value *rot_mode = NULL; -+ -+ pr_debug("In ov5642:ioctl_s_ctrl %d\n", -+ vc->id); -+ -+ switch (vc->id) { -+ case V4L2_CID_BRIGHTNESS: -+ break; -+ case V4L2_CID_AUTO_FOCUS_START: -+ retval = ov5642_auto_focus_start(); -+ break; -+ case V4L2_CID_AUTO_FOCUS_STOP: -+ retval = ov5642_set_idle_mode(); -+ break; -+ case V4L2_CID_CONTRAST: -+ break; -+ case V4L2_CID_SATURATION: -+ break; -+ case V4L2_CID_HUE: -+ break; -+ case V4L2_CID_AUTO_WHITE_BALANCE: -+ break; -+ case V4L2_CID_DO_WHITE_BALANCE: -+ break; -+ case V4L2_CID_RED_BALANCE: -+ break; -+ case V4L2_CID_BLUE_BALANCE: -+ break; -+ case V4L2_CID_GAMMA: -+ break; -+ case V4L2_CID_EXPOSURE: -+ break; -+ case V4L2_CID_AUTOGAIN: -+ break; -+ case V4L2_CID_GAIN: -+ break; -+ case V4L2_CID_HFLIP: -+ break; -+ case V4L2_CID_VFLIP: -+ break; -+ case V4L2_CID_MXC_ROT: -+ case V4L2_CID_MXC_VF_ROT: -+ switch (vc->value) { -+ case V4L2_MXC_ROTATE_NONE: -+ if (captureMode == ov5642_mode_QSXGA_2592_1944) -+ rot_mode = ov5642_rot_none_FULL; -+ else -+ rot_mode = ov5642_rot_none_VGA; -+ -+ if (ov5642_set_rot_mode(rot_mode)) -+ retval = -EPERM; -+ break; -+ case V4L2_MXC_ROTATE_VERT_FLIP: -+ if (captureMode == ov5642_mode_QSXGA_2592_1944) -+ rot_mode = ov5642_rot_vert_flip_FULL; -+ else -+ rot_mode = ov5642_rot_vert_flip_VGA ; -+ -+ if (ov5642_set_rot_mode(rot_mode)) -+ retval = -EPERM; -+ break; -+ case V4L2_MXC_ROTATE_HORIZ_FLIP: -+ if (captureMode == ov5642_mode_QSXGA_2592_1944) -+ rot_mode = ov5642_rot_horiz_flip_FULL; -+ else -+ rot_mode = ov5642_rot_horiz_flip_VGA; -+ -+ if (ov5642_set_rot_mode(rot_mode)) -+ retval = -EPERM; -+ break; -+ case V4L2_MXC_ROTATE_180: -+ if (captureMode == ov5642_mode_QSXGA_2592_1944) -+ rot_mode = ov5642_rot_180_FULL; -+ else -+ rot_mode = ov5642_rot_180_VGA; -+ -+ if (ov5642_set_rot_mode(rot_mode)) -+ retval = -EPERM; -+ break; -+ default: -+ retval = -EPERM; -+ break; -+ } -+ break; -+ default: -+ retval = -EPERM; -+ break; -+ } -+ -+ return retval; -+} -+ -+static int ioctl_send_command(struct v4l2_int_device *s, struct v4l2_send_command_control *vc) { -+ int ret = -1; -+ int retval1,retval2; -+ u8 loca_val=0; -+ -+ ret = ov5642_set_idle_mode(); -+ if (0 != ret) -+ pr_err("error %d setting idle mode\n", ret); -+ ov5642_config_auto_focus(); -+ switch (vc->id) { -+ case 101: //step to near -+ pr_debug("Stepping to near object\n"); -+ retval1=ov5642_write_reg(REG_CMD_TAG, 0x01); -+ retval2=ov5642_write_reg(REG_CMD_MAIN, 0x05); -+ if(retval1 == 0 && retval2 == 0) -+ ret = 0; -+ break; -+ case 102: //step to far -+ pr_debug("Stepping to far object\n"); -+ retval1=ov5642_write_reg(REG_CMD_TAG, 0x02); -+ retval2=ov5642_write_reg(REG_CMD_MAIN, 0x05); -+ if(retval1 == 0 && retval2 == 0) -+ ret = 0; -+ break; -+ -+ case 103: //step to furthest -+ pr_debug("Stepping to furthest object\n"); -+ retval1=ov5642_write_reg(REG_CMD_TAG, 0x03); -+ retval2=ov5642_write_reg(REG_CMD_MAIN, 0x05); -+ if(retval1 == 0 && retval2 == 0) -+ ret = 0; -+ break; -+ -+ case 104: //step to nearest -+ pr_debug("Stepping to nearest object\n"); -+ retval1=ov5642_write_reg(REG_CMD_TAG, 0x04); -+ retval2=ov5642_write_reg(REG_CMD_MAIN, 0x05); -+ if(retval1 == 0 && retval2 == 0) -+ ret = 0; -+ break; -+ -+ -+ case 105: //step to specified position -+ pr_debug("Stepping to position: %d\n", vc->value0); -+ if(vc->value0 < 0 || vc->value0 > 255) -+ return ret; -+ loca_val = vc->value0; -+ retval1=ov5642_write_reg(REG_CMD_TAG, 0x10); -+ retval2=ov5642_write_reg(REG_CMD_PARA0, loca_val); -+ ret=ov5642_write_reg(REG_CMD_MAIN, 0x05); -+ if(retval1 != 0 && retval2 != 0 && ret != 0) -+ ret = -1; -+ break; -+ default: -+ break; -+ } -+ -+ return ret; -+} -+ -+/*! -+ * ioctl_enum_framesizes - V4L2 sensor interface handler for -+ * VIDIOC_ENUM_FRAMESIZES ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure -+ * -+ * Return 0 if successful, otherwise -EINVAL. -+ */ -+static int ioctl_enum_framesizes(struct v4l2_int_device *s, -+ struct v4l2_frmsizeenum *fsize) -+{ -+ if (fsize->index > ov5642_mode_MAX) -+ return -EINVAL; -+ -+ fsize->pixel_format = ov5642_data.pix.pixelformat; -+ fsize->discrete.width = -+ max(ov5642_mode_info_data[0][fsize->index].width, -+ ov5642_mode_info_data[1][fsize->index].width); -+ fsize->discrete.height = -+ max(ov5642_mode_info_data[0][fsize->index].height, -+ ov5642_mode_info_data[1][fsize->index].height); -+ return 0; -+} -+ -+/*! -+ * ioctl_enum_frameintervals - V4L2 sensor interface handler for -+ * VIDIOC_ENUM_FRAMEINTERVALS ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @fival: standard V4L2 VIDIOC_ENUM_FRAMEINTERVALS ioctl structure -+ * -+ * Return 0 if successful, otherwise -EINVAL. -+ */ -+static int ioctl_enum_frameintervals(struct v4l2_int_device *s, -+ struct v4l2_frmivalenum *fival) -+{ -+ int i, j, count; -+ -+ if (fival->index < 0 || fival->index > ov5642_mode_MAX) -+ return -EINVAL; -+ -+ if (fival->pixel_format == 0 || fival->width == 0 || -+ fival->height == 0) { -+ pr_warning("Please assign pixelformat, width and height.\n"); -+ return -EINVAL; -+ } -+ -+ fival->type = V4L2_FRMIVAL_TYPE_DISCRETE; -+ fival->discrete.numerator = 1; -+ -+ count = 0; -+ for (i = 0; i < ARRAY_SIZE(ov5642_mode_info_data); i++) { -+ for (j = 0; j < (ov5642_mode_MAX + 1); j++) { -+ if (fival->pixel_format == ov5642_data.pix.pixelformat -+ && fival->width == ov5642_mode_info_data[i][j].width -+ && fival->height == ov5642_mode_info_data[i][j].height -+ && ov5642_mode_info_data[i][j].init_data_ptr != NULL) { -+ count++; -+ } -+ if (fival->index == (count - 1)) { -+ fival->discrete.denominator = -+ ov5642_framerates[i]; -+ return 0; -+ } -+ } -+ } -+ -+ return -EINVAL; -+} -+ -+/*! -+ * ioctl_g_chip_ident - V4L2 sensor interface handler for -+ * VIDIOC_DBG_G_CHIP_IDENT ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @id: pointer to int -+ * -+ * Return 0. -+ */ -+static int ioctl_g_chip_ident(struct v4l2_int_device *s, int *id) -+{ -+ ((struct v4l2_dbg_chip_ident *)id)->match.type = -+ V4L2_CHIP_MATCH_I2C_DRIVER; -+ strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name, "ov5642_camera"); -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT -+ * @s: pointer to standard V4L2 device structure -+ */ -+static int ioctl_init(struct v4l2_int_device *s) -+{ -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_enum_fmt_cap - V4L2 sensor interface handler for VIDIOC_ENUM_FMT -+ * @s: pointer to standard V4L2 device structure -+ * @fmt: pointer to standard V4L2 fmt description structure -+ * -+ * Return 0. -+ */ -+static int ioctl_enum_fmt_cap(struct v4l2_int_device *s, -+ struct v4l2_fmtdesc *fmt) -+{ -+ if (fmt->index > 0) /* only 1 pixelformat support so far */ -+ return -EINVAL; -+ -+ fmt->pixelformat = ov5642_data.pix.pixelformat; -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num -+ * @s: pointer to standard V4L2 device structure -+ * -+ * Initialise the device when slave attaches to the master. -+ */ -+static int ioctl_dev_init(struct v4l2_int_device *s) -+{ -+ struct reg_value *pModeSetting = NULL; -+ s32 i = 0; -+ s32 iModeSettingArySize = 0; -+ register u32 Delay_ms = 0; -+ register u16 RegAddr = 0; -+ register u8 Mask = 0; -+ register u8 Val = 0; -+ u8 RegVal = 0; -+ int retval = 0; -+ -+ struct sensor_data *sensor = s->priv; -+ u32 tgt_xclk; /* target xclk */ -+ u32 tgt_fps; /* target frames per secound */ -+ enum ov5642_frame_rate frame_rate; -+ -+ ov5642_data.on = true; -+ -+ /* mclk */ -+ tgt_xclk = ov5642_data.mclk; -+ tgt_xclk = min(tgt_xclk, (u32)OV5642_XCLK_MAX); -+ tgt_xclk = max(tgt_xclk, (u32)OV5642_XCLK_MIN); -+ ov5642_data.mclk = tgt_xclk; -+ -+ pr_debug(" Setting mclk to %d MHz\n", tgt_xclk / 1000000); -+ -+ /* Default camera frame rate is set in probe */ -+ tgt_fps = sensor->streamcap.timeperframe.denominator / -+ sensor->streamcap.timeperframe.numerator; -+ -+ if (tgt_fps == 15) -+ frame_rate = ov5642_15_fps; -+ else if (tgt_fps == 30) -+ frame_rate = ov5642_30_fps; -+ else -+ return -EINVAL; /* Only support 15fps or 30fps now. */ -+ -+ pModeSetting = ov5642_initial_setting; -+ iModeSettingArySize = ARRAY_SIZE(ov5642_initial_setting); -+ -+ for (i = 0; i < iModeSettingArySize; ++i, ++pModeSetting) { -+ Delay_ms = pModeSetting->u32Delay_ms; -+ RegAddr = pModeSetting->u16RegAddr; -+ Val = pModeSetting->u8Val; -+ Mask = pModeSetting->u8Mask; -+ if (Mask) { -+ retval = ov5642_read_reg(RegAddr, &RegVal); -+ if (retval < 0) -+ goto err; -+ -+ RegVal &= ~(u8)Mask; -+ Val &= Mask; -+ Val |= RegVal; -+ } -+ -+ retval = ov5642_write_reg(RegAddr, Val); -+ if (retval < 0) -+ goto err; -+ -+ if (Delay_ms) -+ msleep(Delay_ms); -+ } -+err: -+ return retval; -+} -+ -+/*! -+ * ioctl_dev_exit - V4L2 sensor interface handler for vidioc_int_dev_exit_num -+ * @s: pointer to standard V4L2 device structure -+ * -+ * Delinitialise the device when slave detaches to the master. -+ */ -+static int ioctl_dev_exit(struct v4l2_int_device *s) -+{ -+ return 0; -+} -+ -+/*! -+ * This structure defines all the ioctls for this module and links them to the -+ * enumeration. -+ */ -+static struct v4l2_int_ioctl_desc ov5642_ioctl_desc[] = { -+ { vidioc_int_dev_init_num, -+ (v4l2_int_ioctl_func *)ioctl_dev_init }, -+ { vidioc_int_dev_exit_num, ioctl_dev_exit}, -+ { vidioc_int_s_power_num, -+ (v4l2_int_ioctl_func *)ioctl_s_power }, -+ { vidioc_int_g_ifparm_num, -+ (v4l2_int_ioctl_func *)ioctl_g_ifparm }, -+/* { vidioc_int_g_needs_reset_num, -+ (v4l2_int_ioctl_func *)ioctl_g_needs_reset }, */ -+/* { vidioc_int_reset_num, -+ (v4l2_int_ioctl_func *)ioctl_reset }, */ -+ { vidioc_int_init_num, -+ (v4l2_int_ioctl_func *)ioctl_init }, -+ { vidioc_int_enum_fmt_cap_num, -+ (v4l2_int_ioctl_func *)ioctl_enum_fmt_cap }, -+/* { vidioc_int_try_fmt_cap_num, -+ (v4l2_int_ioctl_func *)ioctl_try_fmt_cap }, */ -+ { vidioc_int_g_fmt_cap_num, -+ (v4l2_int_ioctl_func *)ioctl_g_fmt_cap }, -+/* { vidioc_int_s_fmt_cap_num, -+ (v4l2_int_ioctl_func *)ioctl_s_fmt_cap }, */ -+ { vidioc_int_g_parm_num, -+ (v4l2_int_ioctl_func *)ioctl_g_parm }, -+ { vidioc_int_s_parm_num, -+ (v4l2_int_ioctl_func *)ioctl_s_parm }, -+/* { vidioc_int_queryctrl_num, -+ (v4l2_int_ioctl_func *)ioctl_queryctrl }, */ -+ { vidioc_int_g_ctrl_num, -+ (v4l2_int_ioctl_func *)ioctl_g_ctrl }, -+ { vidioc_int_s_ctrl_num, -+ (v4l2_int_ioctl_func *)ioctl_s_ctrl }, -+ { vidioc_int_enum_framesizes_num, -+ (v4l2_int_ioctl_func *)ioctl_enum_framesizes }, -+ { vidioc_int_enum_frameintervals_num, -+ (v4l2_int_ioctl_func *)ioctl_enum_frameintervals }, -+ { vidioc_int_g_chip_ident_num, -+ (v4l2_int_ioctl_func *)ioctl_g_chip_ident }, -+ {vidioc_int_send_command_num, -+ (v4l2_int_ioctl_func *) ioctl_send_command}, -+}; -+ -+static struct v4l2_int_slave ov5642_slave = { -+ .ioctls = ov5642_ioctl_desc, -+ .num_ioctls = ARRAY_SIZE(ov5642_ioctl_desc), -+}; -+ -+static struct v4l2_int_device ov5642_int_device = { -+ .module = THIS_MODULE, -+ .name = "ov5642", -+ .type = v4l2_int_type_slave, -+ .u = { -+ .slave = &ov5642_slave, -+ }, -+}; -+ -+/*! -+ * ov5642 I2C probe function -+ * -+ * @param adapter struct i2c_adapter * -+ * @return Error code indicating success or failure -+ */ -+static int ov5642_probe(struct i2c_client *client, -+ const struct i2c_device_id *id) -+{ -+ struct pinctrl *pinctrl; -+ struct device *dev = &client->dev; -+ int retval; -+ u8 chip_id_high, chip_id_low; -+ struct reg_value *firmware_regs; -+ int i; -+ struct sensor_data *sensor = &ov5642_data; -+ -+ /* ov5642 pinctrl */ -+ pinctrl = devm_pinctrl_get_select_default(dev); -+ if (IS_ERR(pinctrl)) { -+ dev_err(dev, "ov5642 setup pinctrl failed!"); -+ return PTR_ERR(pinctrl); -+ } -+ -+ /* request power down pin */ -+ pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0); -+ if (!gpio_is_valid(pwn_gpio)) { -+ dev_warn(dev, "no sensor pwdn pin available"); -+ return -EINVAL; -+ } -+ retval = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH, -+ "ov5642_pwdn"); -+ if (retval < 0) -+ return retval; -+ -+ /* request reset pin */ -+ rst_gpio = of_get_named_gpio(dev->of_node, "rst-gpios", 0); -+ if (!gpio_is_valid(rst_gpio)) { -+ dev_warn(dev, "no sensor reset pin available"); -+ return -EINVAL; -+ } -+ retval = devm_gpio_request_one(dev, rst_gpio, GPIOF_OUT_INIT_HIGH, -+ "ov5642_reset"); -+ if (retval < 0) -+ return retval; -+ -+ /* Set initial values for the sensor struct. */ -+ memset(&ov5642_data, 0, sizeof(ov5642_data)); -+ ov5642_data.sensor_clk = devm_clk_get(dev, "csi_mclk"); -+ if (IS_ERR(ov5642_data.sensor_clk)) { -+ /* assuming clock enabled by default */ -+ ov5642_data.sensor_clk = NULL; -+ dev_err(dev, "clock-frequency missing or invalid\n"); -+ return PTR_ERR(ov5642_data.sensor_clk); -+ } -+ -+ retval = of_property_read_u32(dev->of_node, "mclk", -+ (u32 *) &(ov5642_data.mclk)); -+ if (retval) { -+ dev_err(dev, "mclk missing or invalid\n"); -+ return retval; -+ } -+ -+ retval = of_property_read_u32(dev->of_node, "mclk_source", -+ (u32 *) &(ov5642_data.mclk_source)); -+ if (retval) { -+ dev_err(dev, "mclk_source missing or invalid\n"); -+ return retval; -+ } -+ -+ retval = of_property_read_u32(dev->of_node, "ipu_id", -+ &sensor->ipu_id); -+ if (retval) { -+ dev_err(dev, "ipu_id missing or invalid\n"); -+ return retval; -+ } -+ -+ retval = of_property_read_u32(dev->of_node, "csi_id", -+ &(ov5642_data.csi)); -+ if (retval) { -+ dev_err(dev, "csi_id missing or invalid\n"); -+ return retval; -+ } -+ -+ clk_prepare_enable(ov5642_data.sensor_clk); -+ -+ ov5642_data.io_init = ov5642_reset; -+ ov5642_data.i2c_client = client; -+ ov5642_data.pix.pixelformat = V4L2_PIX_FMT_YUYV; -+ ov5642_data.pix.width = 640; -+ ov5642_data.pix.height = 480; -+ ov5642_data.streamcap.capability = V4L2_MODE_HIGHQUALITY | -+ V4L2_CAP_TIMEPERFRAME; -+ ov5642_data.streamcap.capturemode = 0; -+ ov5642_data.streamcap.timeperframe.denominator = DEFAULT_FPS; -+ ov5642_data.streamcap.timeperframe.numerator = 1; -+ -+ ov5642_power_on(&client->dev); -+ -+ ov5642_reset(); -+ -+ ov5642_standby(0); -+ -+ retval = ov5642_read_reg(OV5642_CHIP_ID_HIGH_BYTE, &chip_id_high); -+ if (retval < 0 || chip_id_high != 0x56) { -+ pr_warning("camera ov5642 is not found\n"); -+ clk_disable_unprepare(ov5642_data.sensor_clk); -+ return -ENODEV; -+ } -+ retval = ov5642_read_reg(OV5642_CHIP_ID_LOW_BYTE, &chip_id_low); -+ if (retval < 0 || chip_id_low != 0x42) { -+ pr_warning("camera ov5642 is not found\n"); -+ clk_disable_unprepare(ov5642_data.sensor_clk); -+ return -ENODEV; -+ } -+ -+ ov5642_standby(1); -+ -+ ov5642_int_device.priv = &ov5642_data; -+ -+ pr_info("Upload Auto-focus firmware"); -+ firmware_regs = ov5642_af_firmware; -+ for (i = 0; i < ARRAY_SIZE(ov5642_af_firmware); ++i, ++firmware_regs) { -+ retval = ov5642_write_reg(firmware_regs->u16RegAddr, -+ firmware_regs->u8Val); -+ if (retval < 0) -+ break; -+ } -+ -+ retval = v4l2_int_device_register(&ov5642_int_device); -+ -+ clk_disable_unprepare(ov5642_data.sensor_clk); -+ -+ pr_info("camera ov5642 is found\n"); -+ return retval; -+} -+ -+/*! -+ * ov5642 I2C detach function -+ * -+ * @param client struct i2c_client * -+ * @return Error code indicating success or failure -+ */ -+static int ov5642_remove(struct i2c_client *client) -+{ -+ v4l2_int_device_unregister(&ov5642_int_device); -+ -+ if (gpo_regulator) -+ regulator_disable(gpo_regulator); -+ -+ if (analog_regulator) -+ regulator_disable(analog_regulator); -+ -+ if (core_regulator) -+ regulator_disable(core_regulator); -+ -+ if (io_regulator) -+ regulator_disable(io_regulator); -+ -+ return 0; -+} -+ -+/*! -+ * ov5642 init function -+ * Called by insmod ov5642_camera.ko. -+ * -+ * @return Error code indicating success or failure -+ */ -+static __init int ov5642_init(void) -+{ -+ u8 err; -+ -+ err = i2c_add_driver(&ov5642_i2c_driver); -+ if (err != 0) -+ pr_err("%s:driver registration failed, error=%d\n", -+ __func__, err); -+ -+ return err; -+} -+ -+/*! -+ * OV5642 cleanup function -+ * Called on rmmod ov5642_camera.ko -+ * -+ * @return Error code indicating success or failure -+ */ -+static void __exit ov5642_clean(void) -+{ -+ i2c_del_driver(&ov5642_i2c_driver); -+} -+ -+module_init(ov5642_init); -+module_exit(ov5642_clean); -+ -+MODULE_AUTHOR("Freescale Semiconductor, Inc."); -+MODULE_DESCRIPTION("OV5642 Camera Driver"); -+MODULE_LICENSE("GPL"); -+MODULE_VERSION("1.0"); -+MODULE_ALIAS("CSI"); -diff -Nur linux-4.1.13.orig/drivers/media/platform/mxc/capture/ov5647_mipi.c linux-4.1.13/drivers/media/platform/mxc/capture/ov5647_mipi.c ---- linux-4.1.13.orig/drivers/media/platform/mxc/capture/ov5647_mipi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/media/platform/mxc/capture/ov5647_mipi.c 2015-11-30 17:56:13.612135595 +0100 -@@ -0,0 +1,3780 @@ -+/* -+ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved. -+ */ -+ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "mxc_v4l2_capture.h" -+ -+#define OV5647_VOLTAGE_ANALOG 2800000 -+#define OV5647_VOLTAGE_DIGITAL_CORE 1500000 -+#define OV5647_VOLTAGE_DIGITAL_IO 1800000 -+ -+#define MIN_FPS 15 -+#define MAX_FPS 30 -+#define DEFAULT_FPS 30 -+ -+#define OV5647_XCLK_MIN 6000000 -+#define OV5647_XCLK_MAX 27000000 -+ -+#define OV5647_CHIP_ID_HIGH_BYTE 0x300A -+#define OV5647_CHIP_ID_LOW_BYTE 0x300B -+ -+enum ov5647_mode { -+ ov5647_mode_MIN = 0, -+ ov5647_mode_960P_1280_960 = 0, -+ ov5647_mode_720P_1280_720 = 1, -+ ov5647_mode_1080P_1920_1080 = 2, -+ ov5647_mode_VGA_640_480 = 3, -+ ov5647_mode_XGA_1024_768 = 4, -+ ov5647_mode_960_720 = 5, -+ ov5647_mode_VGA_640_480_narrow = 6, -+ ov5647_mode_MAX = 6, -+ ov5647_mode_INIT = 0xff, /*only for sensor init*/ -+}; -+ -+enum ov5647_frame_rate { -+ ov5647_15_fps, -+ ov5647_30_fps -+}; -+ -+/* image size under 1280 * 960 are SUBSAMPLING -+ * image size upper 1280 * 960 are SCALING -+ */ -+enum ov5647_downsize_mode { -+ SUBSAMPLING, -+ SCALING, -+}; -+ -+struct reg_value { -+ u16 u16RegAddr; -+ u8 u8Val; -+ u8 u8Mask; -+ u32 u32Delay_ms; -+}; -+ -+struct ov5647_mode_info { -+ enum ov5647_mode mode; -+ enum ov5647_downsize_mode dn_mode; -+ u32 width; -+ u32 height; -+ struct reg_value *init_data_ptr; -+ u32 init_data_size; -+}; -+ -+/*! -+ * Maintains the information on the current state of the sesor. -+ */ -+static struct sensor_data ov5647_data; -+static struct additional_data ov5647_data_add; -+static int pwn_gpio = -EINVAL; -+static int powon_active; -+static int rst_gpio = -EINVAL; -+static int rst_active; -+static int led_gpio = -EINVAL; -+static int led_active; -+ -+static struct reg_value ov5647_setting_30fps_960P_1280_960[] = { -+ { 0x0100 , 0x00 , 0 , 0 } , -+ { 0x0103 , 0x01 , 0 , 0 } , -+ { 0x3034 , 0x18 , 0 , 0 } , /* was 0x1A */ -+ { 0x3035 , 0x21 , 0 , 0 } , -+ { 0x3036 , 0x52 , 0 , 0 } , -+ { 0x303c , 0x11 , 0 , 0 } , -+ { 0x3106 , 0xf5 , 0 , 0 } , -+ { 0x3821 , 0x07 , 0 , 0 } , -+ { 0x3820 , 0x41 , 0 , 0 } , -+ { 0x3827 , 0xec , 0 , 0 } , -+ { 0x370c , 0x03 , 0 , 0 } , -+ { 0x3612 , 0x4b , 0 , 0 } , -+ { 0x3618 , 0x00 , 0 , 0 } , -+ { 0x5001 , 0x01 , 0 , 0 } , -+ { 0x5002 , 0x40 , 0 , 0 } , -+ { 0x5003 , 0x08 , 0 , 0 } , -+ { 0x5a00 , 0x08 , 0 , 0 } , -+ { 0x3000 , 0x00 , 0 , 0 } , -+ { 0x3001 , 0x00 , 0 , 0 } , -+ { 0x3002 , 0x00 , 0 , 0 } , -+ { 0x3016 , 0x08 , 0 , 0 } , -+ { 0x3017 , 0xe0 , 0 , 0 } , -+ { 0x3018 , 0x44 , 0 , 0 } , -+ { 0x301c , 0xf8 , 0 , 0 } , -+ { 0x301d , 0xf0 , 0 , 0 } , -+ { 0x3a18 , 0x00 , 0 , 0 } , -+ { 0x3a19 , 0xf8 , 0 , 0 } , -+ { 0x3c01 , 0x80 , 0 , 0 } , -+ { 0x3b07 , 0x0c , 0 , 0 } , -+ { 0x380c , 0x07 , 0 , 0 } , -+ { 0x380d , 0x68 , 0 , 0 } , -+ { 0x380e , 0x03 , 0 , 0 } , -+ { 0x380f , 0xd8 , 0 , 0 } , -+ { 0x3814 , 0x31 , 0 , 0 } , -+ { 0x3815 , 0x31 , 0 , 0 } , -+ { 0x3708 , 0x64 , 0 , 0 } , -+ { 0x3709 , 0x52 , 0 , 0 } , -+ { 0x3808 , 0x05 , 0 , 0 } , -+ { 0x3809 , 0x00 , 0 , 0 } , -+ { 0x380a , 0x03 , 0 , 0 } , -+ { 0x380b , 0xc0 , 0 , 0 } , -+ { 0x3800 , 0x00 , 0 , 0 } , -+ { 0x3801 , 0x00 , 0 , 0 } , -+ { 0x3802 , 0x00 , 0 , 0 } , -+ { 0x3803 , 0x00 , 0 , 0 } , -+ { 0x3804 , 0x0a , 0 , 0 } , -+ { 0x3805 , 0x3f , 0 , 0 } , -+ { 0x3806 , 0x07 , 0 , 0 } , -+ { 0x3807 , 0xa1 , 0 , 0 } , -+ { 0x3811 , 0x08 , 0 , 0 } , -+ { 0x3813 , 0x02 , 0 , 0 } , -+ { 0x3630 , 0x2e , 0 , 0 } , -+ { 0x3632 , 0xe2 , 0 , 0 } , -+ { 0x3633 , 0x23 , 0 , 0 } , -+ { 0x3634 , 0x44 , 0 , 0 } , -+ { 0x3636 , 0x06 , 0 , 0 } , -+ { 0x3620 , 0x64 , 0 , 0 } , -+ { 0x3621 , 0xe0 , 0 , 0 } , -+ { 0x3600 , 0x37 , 0 , 0 } , -+ { 0x3704 , 0xa0 , 0 , 0 } , -+ { 0x3703 , 0x5a , 0 , 0 } , -+ { 0x3715 , 0x78 , 0 , 0 } , -+ { 0x3717 , 0x01 , 0 , 0 } , -+ { 0x3731 , 0x02 , 0 , 0 } , -+ { 0x370b , 0x60 , 0 , 0 } , -+ { 0x3705 , 0x1a , 0 , 0 } , -+ { 0x3f05 , 0x02 , 0 , 0 } , -+ { 0x3f06 , 0x10 , 0 , 0 } , -+ { 0x3f01 , 0x0a , 0 , 0 } , -+ { 0x3a08 , 0x01 , 0 , 0 } , -+ { 0x3a09 , 0x27 , 0 , 0 } , -+ { 0x3a0a , 0x00 , 0 , 0 } , -+ { 0x3a0b , 0xf6 , 0 , 0 } , -+ { 0x3a0d , 0x04 , 0 , 0 } , -+ { 0x3a0e , 0x03 , 0 , 0 } , -+ { 0x3a0f , 0x58 , 0 , 0 } , -+ { 0x3a10 , 0x50 , 0 , 0 } , -+ { 0x3a1b , 0x58 , 0 , 0 } , -+ { 0x3a1e , 0x50 , 0 , 0 } , -+ { 0x3a11 , 0x60 , 0 , 0 } , -+ { 0x3a1f , 0x28 , 0 , 300 } , -+ { 0x4001 , 0x02 , 0 , 0 } , -+ { 0x4004 , 0x02 , 0 , 0 } , -+ { 0x4000 , 0x09 , 0 , 0 } , -+ { 0x4837 , 0x24 , 0 , 0 } , -+ { 0x4050 , 0x6e , 0 , 0 } , -+ { 0x4051 , 0x8f , 0 , 0 } , -+ { 0x0100 , 0x01 , 0 , 0 } , -+#if 0 -+ { 0x503d , 0xc0 , 0 , 0 } , /* test pattern */ -+ { 0x503e , 0x11 , 0 , 0 } , /* test pattern */ -+#endif -+ { 0x5000 , 0x86 , 0 , 0 } , /* enable LENC registers */ -+ { 0x5800 , 0x00 , 0 , 0 } , -+ { 0x5801 , 0x00 , 0 , 0 } , -+ { 0x5802 , 0x00 , 0 , 0 } , -+ { 0x5803 , 0x00 , 0 , 0 } , -+ { 0x5804 , 0x00 , 0 , 0 } , -+ { 0x5805 , 0x00 , 0 , 0 } , -+ { 0x5806 , 0x00 , 0 , 0 } , -+ { 0x5807 , 0x00 , 0 , 0 } , -+ { 0x5808 , 0x00 , 0 , 0 } , -+ { 0x5809 , 0x00 , 0 , 0 } , -+ { 0x580a , 0x00 , 0 , 0 } , -+ { 0x580b , 0x00 , 0 , 0 } , -+ { 0x580c , 0x00 , 0 , 0 } , -+ { 0x580d , 0x00 , 0 , 0 } , -+ { 0x580e , 0x00 , 0 , 0 } , -+ { 0x580f , 0x00 , 0 , 0 } , -+ { 0x5810 , 0x00 , 0 , 0 } , -+ { 0x5811 , 0x00 , 0 , 0 } , -+ { 0x5812 , 0x00 , 0 , 0 } , -+ { 0x5813 , 0x00 , 0 , 0 } , -+ { 0x5814 , 0x00 , 0 , 0 } , -+ { 0x5815 , 0x00 , 0 , 0 } , -+ { 0x5816 , 0x00 , 0 , 0 } , -+ { 0x5817 , 0x00 , 0 , 0 } , -+ { 0x5818 , 0x00 , 0 , 0 } , -+ { 0x5819 , 0x00 , 0 , 0 } , -+ { 0x581a , 0x00 , 0 , 0 } , -+ { 0x581b , 0x00 , 0 , 0 } , -+ { 0x581c , 0x00 , 0 , 0 } , -+ { 0x581d , 0x00 , 0 , 0 } , -+ { 0x581e , 0x00 , 0 , 0 } , -+ { 0x581f , 0x00 , 0 , 0 } , -+ { 0x5820 , 0x00 , 0 , 0 } , -+ { 0x5821 , 0x00 , 0 , 0 } , -+ { 0x5822 , 0x00 , 0 , 0 } , -+ { 0x5823 , 0x00 , 0 , 0 } , -+ { 0x5824 , 0xfe , 0 , 0 } , -+ { 0x5825 , 0xfe , 0 , 0 } , -+ { 0x5826 , 0xfe , 0 , 0 } , -+ { 0x5827 , 0xfe , 0 , 0 } , -+ { 0x5828 , 0xfe , 0 , 0 } , -+ { 0x5829 , 0xfe , 0 , 0 } , -+ { 0x582a , 0xed , 0 , 0 } , -+ { 0x582b , 0xed , 0 , 0 } , -+ { 0x582c , 0xed , 0 , 0 } , -+ { 0x582d , 0xfe , 0 , 0 } , -+ { 0x582e , 0xfe , 0 , 0 } , -+ { 0x582f , 0xed , 0 , 0 } , -+ { 0x5830 , 0xdc , 0 , 0 } , -+ { 0x5831 , 0xed , 0 , 0 } , -+ { 0x5832 , 0xfe , 0 , 0 } , -+ { 0x5833 , 0xfe , 0 , 0 } , -+ { 0x5834 , 0xed , 0 , 0 } , -+ { 0x5835 , 0xed , 0 , 0 } , -+ { 0x5836 , 0xed , 0 , 0 } , -+ { 0x5837 , 0xfe , 0 , 0 } , -+ { 0x5838 , 0xfe , 0 , 0 } , -+ { 0x5839 , 0xfe , 0 , 0 } , -+ { 0x583a , 0xfe , 0 , 0 } , -+ { 0x583b , 0xfe , 0 , 0 } , -+ { 0x583c , 0xfe , 0 , 0 } , -+ { 0x583d , 0xce , 0 , 0 } , -+ { 0x3501 , 0x10 , 0 , 0 } , -+ { 0x3502 , 0x80 , 0 , 0 } , -+ { 0x350a , 0x00 , 0 , 0 } , -+ { 0x350b , 0x7f , 0 , 0 } , -+ { 0x3c00 , 0x04 , 0 , 300 } , -+ { 0x3002 , 0xe4 , 0x01, 0 } , /* enable all outputs */ -+}; -+ -+static struct reg_value ov5647_setting_15fps_960P_1280_960[] = { -+ { 0x0100 , 0x00 , 0 , 0 } , -+ { 0x0103 , 0x01 , 0 , 0 } , -+ { 0x3034 , 0x18 , 0 , 0 } , /* was 0x1A */ -+ { 0x3035 , 0x41 , 0 , 0 } , -+ { 0x3036 , 0x52 , 0 , 0 } , -+ { 0x303c , 0x11 , 0 , 0 } , -+ { 0x3106 , 0xf5 , 0 , 0 } , -+ { 0x3821 , 0x07 , 0 , 0 } , -+ { 0x3820 , 0x41 , 0 , 0 } , -+ { 0x3827 , 0xec , 0 , 0 } , -+ { 0x370c , 0x03 , 0 , 0 } , -+ { 0x3612 , 0x4b , 0 , 0 } , -+ { 0x3618 , 0x00 , 0 , 0 } , -+ { 0x5001 , 0x01 , 0 , 0 } , -+ { 0x5002 , 0x40 , 0 , 0 } , -+ { 0x5003 , 0x08 , 0 , 0 } , -+ { 0x5a00 , 0x08 , 0 , 0 } , -+ { 0x3000 , 0x00 , 0 , 0 } , -+ { 0x3001 , 0x00 , 0 , 0 } , -+ { 0x3002 , 0x00 , 0 , 0 } , -+ { 0x3016 , 0x08 , 0 , 0 } , -+ { 0x3017 , 0xe0 , 0 , 0 } , -+ { 0x3018 , 0x44 , 0 , 0 } , -+ { 0x301c , 0xf8 , 0 , 0 } , -+ { 0x301d , 0xf0 , 0 , 0 } , -+ { 0x3a18 , 0x00 , 0 , 0 } , -+ { 0x3a19 , 0xf8 , 0 , 0 } , -+ { 0x3c01 , 0x80 , 0 , 0 } , -+ { 0x3b07 , 0x0c , 0 , 0 } , -+ { 0x380c , 0x07 , 0 , 0 } , -+ { 0x380d , 0x68 , 0 , 0 } , -+ { 0x380e , 0x03 , 0 , 0 } , -+ { 0x380f , 0xd8 , 0 , 0 } , -+ { 0x3814 , 0x31 , 0 , 0 } , -+ { 0x3815 , 0x31 , 0 , 0 } , -+ { 0x3708 , 0x64 , 0 , 0 } , -+ { 0x3709 , 0x52 , 0 , 0 } , -+ { 0x3808 , 0x05 , 0 , 0 } , -+ { 0x3809 , 0x00 , 0 , 0 } , -+ { 0x380a , 0x03 , 0 , 0 } , -+ { 0x380b , 0xc0 , 0 , 0 } , -+ { 0x3800 , 0x00 , 0 , 0 } , -+ { 0x3801 , 0x00 , 0 , 0 } , -+ { 0x3802 , 0x00 , 0 , 0 } , -+ { 0x3803 , 0x00 , 0 , 0 } , -+ { 0x3804 , 0x0a , 0 , 0 } , -+ { 0x3805 , 0x3f , 0 , 0 } , -+ { 0x3806 , 0x07 , 0 , 0 } , -+ { 0x3807 , 0xa1 , 0 , 0 } , -+ { 0x3811 , 0x08 , 0 , 0 } , -+ { 0x3813 , 0x02 , 0 , 0 } , -+ { 0x3630 , 0x2e , 0 , 0 } , -+ { 0x3632 , 0xe2 , 0 , 0 } , -+ { 0x3633 , 0x23 , 0 , 0 } , -+ { 0x3634 , 0x44 , 0 , 0 } , -+ { 0x3636 , 0x06 , 0 , 0 } , -+ { 0x3620 , 0x64 , 0 , 0 } , -+ { 0x3621 , 0xe0 , 0 , 0 } , -+ { 0x3600 , 0x37 , 0 , 0 } , -+ { 0x3704 , 0xa0 , 0 , 0 } , -+ { 0x3703 , 0x5a , 0 , 0 } , -+ { 0x3715 , 0x78 , 0 , 0 } , -+ { 0x3717 , 0x01 , 0 , 0 } , -+ { 0x3731 , 0x02 , 0 , 0 } , -+ { 0x370b , 0x60 , 0 , 0 } , -+ { 0x3705 , 0x1a , 0 , 0 } , -+ { 0x3f05 , 0x02 , 0 , 0 } , -+ { 0x3f06 , 0x10 , 0 , 0 } , -+ { 0x3f01 , 0x0a , 0 , 0 } , -+ { 0x3a08 , 0x01 , 0 , 0 } , -+ { 0x3a09 , 0x27 , 0 , 0 } , -+ { 0x3a0a , 0x00 , 0 , 0 } , -+ { 0x3a0b , 0xf6 , 0 , 0 } , -+ { 0x3a0d , 0x04 , 0 , 0 } , -+ { 0x3a0e , 0x03 , 0 , 0 } , -+ { 0x3a0f , 0x58 , 0 , 0 } , -+ { 0x3a10 , 0x50 , 0 , 0 } , -+ { 0x3a1b , 0x58 , 0 , 0 } , -+ { 0x3a1e , 0x50 , 0 , 0 } , -+ { 0x3a11 , 0x60 , 0 , 0 } , -+ { 0x3a1f , 0x28 , 0 , 300 } , -+ { 0x4001 , 0x02 , 0 , 0 } , -+ { 0x4004 , 0x02 , 0 , 0 } , -+ { 0x4000 , 0x09 , 0 , 0 } , -+ { 0x4837 , 0x24 , 0 , 0 } , -+ { 0x4050 , 0x6e , 0 , 0 } , -+ { 0x4051 , 0x8f , 0 , 0 } , -+ { 0x0100 , 0x01 , 0 , 0 } , -+#if 0 -+ { 0x503d , 0xc0 , 0 , 0 } , /* test pattern */ -+ { 0x503e , 0x11 , 0 , 0 } , /* test pattern */ -+#endif -+ { 0x5000 , 0x86 , 0 , 0 } , /* enable LENC registers */ -+ { 0x5800 , 0x00 , 0 , 0 } , -+ { 0x5801 , 0x00 , 0 , 0 } , -+ { 0x5802 , 0x00 , 0 , 0 } , -+ { 0x5803 , 0x00 , 0 , 0 } , -+ { 0x5804 , 0x00 , 0 , 0 } , -+ { 0x5805 , 0x00 , 0 , 0 } , -+ { 0x5806 , 0x00 , 0 , 0 } , -+ { 0x5807 , 0x00 , 0 , 0 } , -+ { 0x5808 , 0x00 , 0 , 0 } , -+ { 0x5809 , 0x00 , 0 , 0 } , -+ { 0x580a , 0x00 , 0 , 0 } , -+ { 0x580b , 0x00 , 0 , 0 } , -+ { 0x580c , 0x00 , 0 , 0 } , -+ { 0x580d , 0x00 , 0 , 0 } , -+ { 0x580e , 0x00 , 0 , 0 } , -+ { 0x580f , 0x00 , 0 , 0 } , -+ { 0x5810 , 0x00 , 0 , 0 } , -+ { 0x5811 , 0x00 , 0 , 0 } , -+ { 0x5812 , 0x00 , 0 , 0 } , -+ { 0x5813 , 0x00 , 0 , 0 } , -+ { 0x5814 , 0x00 , 0 , 0 } , -+ { 0x5815 , 0x00 , 0 , 0 } , -+ { 0x5816 , 0x00 , 0 , 0 } , -+ { 0x5817 , 0x00 , 0 , 0 } , -+ { 0x5818 , 0x00 , 0 , 0 } , -+ { 0x5819 , 0x00 , 0 , 0 } , -+ { 0x581a , 0x00 , 0 , 0 } , -+ { 0x581b , 0x00 , 0 , 0 } , -+ { 0x581c , 0x00 , 0 , 0 } , -+ { 0x581d , 0x00 , 0 , 0 } , -+ { 0x581e , 0x00 , 0 , 0 } , -+ { 0x581f , 0x00 , 0 , 0 } , -+ { 0x5820 , 0x00 , 0 , 0 } , -+ { 0x5821 , 0x00 , 0 , 0 } , -+ { 0x5822 , 0x00 , 0 , 0 } , -+ { 0x5823 , 0x00 , 0 , 0 } , -+ { 0x5824 , 0xfe , 0 , 0 } , -+ { 0x5825 , 0xfe , 0 , 0 } , -+ { 0x5826 , 0xfe , 0 , 0 } , -+ { 0x5827 , 0xfe , 0 , 0 } , -+ { 0x5828 , 0xfe , 0 , 0 } , -+ { 0x5829 , 0xfe , 0 , 0 } , -+ { 0x582a , 0xed , 0 , 0 } , -+ { 0x582b , 0xed , 0 , 0 } , -+ { 0x582c , 0xed , 0 , 0 } , -+ { 0x582d , 0xfe , 0 , 0 } , -+ { 0x582e , 0xfe , 0 , 0 } , -+ { 0x582f , 0xed , 0 , 0 } , -+ { 0x5830 , 0xdc , 0 , 0 } , -+ { 0x5831 , 0xed , 0 , 0 } , -+ { 0x5832 , 0xfe , 0 , 0 } , -+ { 0x5833 , 0xfe , 0 , 0 } , -+ { 0x5834 , 0xed , 0 , 0 } , -+ { 0x5835 , 0xed , 0 , 0 } , -+ { 0x5836 , 0xed , 0 , 0 } , -+ { 0x5837 , 0xfe , 0 , 0 } , -+ { 0x5838 , 0xfe , 0 , 0 } , -+ { 0x5839 , 0xfe , 0 , 0 } , -+ { 0x583a , 0xfe , 0 , 0 } , -+ { 0x583b , 0xfe , 0 , 0 } , -+ { 0x583c , 0xfe , 0 , 0 } , -+ { 0x583d , 0xce , 0 , 0 } , -+ { 0x3501 , 0x10 , 0 , 0 } , -+ { 0x3502 , 0x80 , 0 , 0 } , -+ { 0x350a , 0x00 , 0 , 0 } , -+ { 0x350b , 0x7f , 0 , 0 } , -+ { 0x3c00 , 0x04 , 0 , 300 } , -+ { 0x3002 , 0xe4 , 0x01, 0 } , /* enable all outputs */ -+}; -+ -+static struct reg_value ov5647_setting_30fps_720P_1280_720[] = { -+ { 0x0100 , 0x00 , 0 , 0 } , -+ { 0x0103 , 0x01 , 0 , 0 } , -+ { 0x3034 , 0x18 , 0 , 0 } , /* was 0x1A */ -+ { 0x3035 , 0x41 , 0 , 0 } , -+ { 0x3036 , 0xa0 , 0 , 0 } , -+ { 0x303c , 0x11 , 0 , 0 } , -+ { 0x3106 , 0xf5 , 0 , 0 } , -+ { 0x3821 , 0x07 , 0 , 0 } , -+ { 0x3820 , 0x41 , 0 , 0 } , -+ { 0x3827 , 0xec , 0 , 0 } , -+ { 0x370c , 0x03 , 0 , 0 } , -+ { 0x3612 , 0x4b , 0 , 0 } , -+ { 0x3618 , 0x00 , 0 , 0 } , -+ { 0x5001 , 0x01 , 0 , 0 } , -+ { 0x5002 , 0x40 , 0 , 0 } , -+ { 0x5003 , 0x08 , 0 , 0 } , -+ { 0x5a00 , 0x08 , 0 , 0 } , -+ { 0x3000 , 0x00 , 0 , 0 } , -+ { 0x3001 , 0x00 , 0 , 0 } , -+ { 0x3002 , 0x00 , 0 , 0 } , -+ { 0x3016 , 0x08 , 0 , 0 } , -+ { 0x3017 , 0xe0 , 0 , 0 } , -+ { 0x3018 , 0x44 , 0 , 0 } , -+ { 0x301c , 0xf8 , 0 , 0 } , -+ { 0x301d , 0xf0 , 0 , 0 } , -+ { 0x3a18 , 0x00 , 0 , 0 } , -+ { 0x3a19 , 0xf8 , 0 , 0 } , -+ { 0x3c01 , 0x80 , 0 , 0 } , -+ { 0x3b07 , 0x0c , 0 , 0 } , -+ { 0x380c , 0x06 , 0 , 0 } , -+ { 0x380d , 0xd6 , 0 , 0 } , -+ { 0x380e , 0x03 , 0 , 0 } , -+ { 0x380f , 0xd8 , 0 , 0 } , -+ { 0x3814 , 0x31 , 0 , 0 } , -+ { 0x3815 , 0x31 , 0 , 0 } , -+ { 0x3708 , 0x64 , 0 , 0 } , -+ { 0x3709 , 0x52 , 0 , 0 } , -+ { 0x3808 , 0x05 , 0 , 0 } , -+ { 0x3809 , 0x00 , 0 , 0 } , -+ { 0x380a , 0x02 , 0 , 0 } , -+ { 0x380b , 0xd0 , 0 , 0 } , -+ { 0x3800 , 0x00 , 0 , 0 } , -+ { 0x3801 , 0x00 , 0 , 0 } , -+ { 0x3802 , 0x00 , 0 , 0 } , -+ { 0x3803 , 0x00 , 0 , 0 } , -+ { 0x3804 , 0x0a , 0 , 0 } , -+ { 0x3805 , 0x3f , 0 , 0 } , -+ { 0x3806 , 0x06 , 0 , 0 } , -+ { 0x3807 , 0xb2 , 0 , 0 } , -+ { 0x3811 , 0x08 , 0 , 0 } , -+ { 0x3813 , 0x02 , 0 , 0 } , -+ { 0x3630 , 0x2e , 0 , 0 } , -+ { 0x3632 , 0xe2 , 0 , 0 } , -+ { 0x3633 , 0x23 , 0 , 0 } , -+ { 0x3634 , 0x44 , 0 , 0 } , -+ { 0x3636 , 0x06 , 0 , 0 } , -+ { 0x3620 , 0x64 , 0 , 0 } , -+ { 0x3621 , 0xe0 , 0 , 0 } , -+ { 0x3600 , 0x37 , 0 , 0 } , -+ { 0x3704 , 0xa0 , 0 , 0 } , -+ { 0x3703 , 0x5a , 0 , 0 } , -+ { 0x3715 , 0x78 , 0 , 0 } , -+ { 0x3717 , 0x01 , 0 , 0 } , -+ { 0x3731 , 0x02 , 0 , 0 } , -+ { 0x370b , 0x60 , 0 , 0 } , -+ { 0x3705 , 0x1a , 0 , 0 } , -+ { 0x3f05 , 0x02 , 0 , 0 } , -+ { 0x3f06 , 0x10 , 0 , 0 } , -+ { 0x3f01 , 0x0a , 0 , 0 } , -+ { 0x3a08 , 0x01 , 0 , 0 } , -+ { 0x3a09 , 0x27 , 0 , 0 } , -+ { 0x3a0a , 0x00 , 0 , 0 } , -+ { 0x3a0b , 0xf6 , 0 , 0 } , -+ { 0x3a0d , 0x04 , 0 , 0 } , -+ { 0x3a0e , 0x03 , 0 , 0 } , -+ { 0x3a0f , 0x58 , 0 , 0 } , -+ { 0x3a10 , 0x50 , 0 , 0 } , -+ { 0x3a1b , 0x58 , 0 , 0 } , -+ { 0x3a1e , 0x50 , 0 , 0 } , -+ { 0x3a11 , 0x60 , 0 , 0 } , -+ { 0x3a1f , 0x28 , 0 , 300 } , -+ { 0x4001 , 0x02 , 0 , 0 } , -+ { 0x4004 , 0x02 , 0 , 0 } , -+ { 0x4000 , 0x09 , 0 , 0 } , -+ { 0x4837 , 0x24 , 0 , 0 } , -+ { 0x4050 , 0x6e , 0 , 0 } , -+ { 0x4051 , 0x8f , 0 , 0 } , -+ { 0x0100 , 0x01 , 0 , 0 } , -+#if 0 -+ { 0x503d , 0xc0 , 0 , 0 } , /* test pattern */ -+ { 0x503e , 0x11 , 0 , 0 } , /* test pattern */ -+#endif -+ { 0x5000 , 0x86 , 0 , 0 } , /* enable LENC registers */ -+ { 0x5800 , 0x00 , 0 , 0 } , -+ { 0x5801 , 0x00 , 0 , 0 } , -+ { 0x5802 , 0x00 , 0 , 0 } , -+ { 0x5803 , 0x00 , 0 , 0 } , -+ { 0x5804 , 0x00 , 0 , 0 } , -+ { 0x5805 , 0x00 , 0 , 0 } , -+ { 0x5806 , 0x00 , 0 , 0 } , -+ { 0x5807 , 0x00 , 0 , 0 } , -+ { 0x5808 , 0x00 , 0 , 0 } , -+ { 0x5809 , 0x00 , 0 , 0 } , -+ { 0x580a , 0x00 , 0 , 0 } , -+ { 0x580b , 0x00 , 0 , 0 } , -+ { 0x580c , 0x00 , 0 , 0 } , -+ { 0x580d , 0x00 , 0 , 0 } , -+ { 0x580e , 0x00 , 0 , 0 } , -+ { 0x580f , 0x00 , 0 , 0 } , -+ { 0x5810 , 0x00 , 0 , 0 } , -+ { 0x5811 , 0x00 , 0 , 0 } , -+ { 0x5812 , 0x00 , 0 , 0 } , -+ { 0x5813 , 0x00 , 0 , 0 } , -+ { 0x5814 , 0x00 , 0 , 0 } , -+ { 0x5815 , 0x00 , 0 , 0 } , -+ { 0x5816 , 0x00 , 0 , 0 } , -+ { 0x5817 , 0x00 , 0 , 0 } , -+ { 0x5818 , 0x00 , 0 , 0 } , -+ { 0x5819 , 0x00 , 0 , 0 } , -+ { 0x581a , 0x00 , 0 , 0 } , -+ { 0x581b , 0x00 , 0 , 0 } , -+ { 0x581c , 0x00 , 0 , 0 } , -+ { 0x581d , 0x00 , 0 , 0 } , -+ { 0x581e , 0x00 , 0 , 0 } , -+ { 0x581f , 0x00 , 0 , 0 } , -+ { 0x5820 , 0x00 , 0 , 0 } , -+ { 0x5821 , 0x00 , 0 , 0 } , -+ { 0x5822 , 0x00 , 0 , 0 } , -+ { 0x5823 , 0x00 , 0 , 0 } , -+ { 0x5824 , 0xfe , 0 , 0 } , -+ { 0x5825 , 0xfe , 0 , 0 } , -+ { 0x5826 , 0xfe , 0 , 0 } , -+ { 0x5827 , 0xfe , 0 , 0 } , -+ { 0x5828 , 0xfe , 0 , 0 } , -+ { 0x5829 , 0xfe , 0 , 0 } , -+ { 0x582a , 0xed , 0 , 0 } , -+ { 0x582b , 0xed , 0 , 0 } , -+ { 0x582c , 0xed , 0 , 0 } , -+ { 0x582d , 0xfe , 0 , 0 } , -+ { 0x582e , 0xfe , 0 , 0 } , -+ { 0x582f , 0xed , 0 , 0 } , -+ { 0x5830 , 0xdc , 0 , 0 } , -+ { 0x5831 , 0xed , 0 , 0 } , -+ { 0x5832 , 0xfe , 0 , 0 } , -+ { 0x5833 , 0xfe , 0 , 0 } , -+ { 0x5834 , 0xed , 0 , 0 } , -+ { 0x5835 , 0xed , 0 , 0 } , -+ { 0x5836 , 0xed , 0 , 0 } , -+ { 0x5837 , 0xfe , 0 , 0 } , -+ { 0x5838 , 0xfe , 0 , 0 } , -+ { 0x5839 , 0xfe , 0 , 0 } , -+ { 0x583a , 0xfe , 0 , 0 } , -+ { 0x583b , 0xfe , 0 , 0 } , -+ { 0x583c , 0xfe , 0 , 0 } , -+ { 0x583d , 0xce , 0 , 0 } , -+ { 0x3501 , 0x10 , 0 , 0 } , -+ { 0x3502 , 0x80 , 0 , 0 } , -+ { 0x350a , 0x00 , 0 , 0 } , -+ { 0x350b , 0x7f , 0 , 0 } , -+ { 0x3c00 , 0x04 , 0 , 300 } , -+ { 0x3002 , 0xe4 , 0x01, 0 } , /* enable all outputs */ -+}; -+ -+static struct reg_value ov5647_setting_15fps_720P_1280_720[] = { -+ { 0x0100 , 0x00 , 0 , 0 } , -+ { 0x0103 , 0x01 , 0 , 0 } , -+ { 0x3034 , 0x18 , 0 , 0 } , /* was 0x1A */ -+ { 0x3035 , 0x41 , 0 , 0 } , -+ { 0x3036 , 0x49 , 0 , 0 } , -+ { 0x303c , 0x11 , 0 , 0 } , -+ { 0x3106 , 0xf5 , 0 , 0 } , -+ { 0x3821 , 0x07 , 0 , 0 } , -+ { 0x3820 , 0x41 , 0 , 0 } , -+ { 0x3827 , 0xec , 0 , 0 } , -+ { 0x370c , 0x03 , 0 , 0 } , -+ { 0x3612 , 0x4b , 0 , 0 } , -+ { 0x3618 , 0x00 , 0 , 0 } , -+ { 0x5001 , 0x01 , 0 , 0 } , -+ { 0x5002 , 0x40 , 0 , 0 } , -+ { 0x5003 , 0x08 , 0 , 0 } , -+ { 0x5a00 , 0x08 , 0 , 0 } , -+ { 0x3000 , 0x00 , 0 , 0 } , -+ { 0x3001 , 0x00 , 0 , 0 } , -+ { 0x3002 , 0x00 , 0 , 0 } , -+ { 0x3016 , 0x08 , 0 , 0 } , -+ { 0x3017 , 0xe0 , 0 , 0 } , -+ { 0x3018 , 0x44 , 0 , 0 } , -+ { 0x301c , 0xf8 , 0 , 0 } , -+ { 0x301d , 0xf0 , 0 , 0 } , -+ { 0x3a18 , 0x00 , 0 , 0 } , -+ { 0x3a19 , 0xf8 , 0 , 0 } , -+ { 0x3c01 , 0x80 , 0 , 0 } , -+ { 0x3b07 , 0x0c , 0 , 0 } , -+ { 0x380c , 0x06 , 0 , 0 } , -+ { 0x380d , 0xd6 , 0 , 0 } , -+ { 0x380e , 0x03 , 0 , 0 } , -+ { 0x380f , 0xd8 , 0 , 0 } , -+ { 0x3814 , 0x31 , 0 , 0 } , -+ { 0x3815 , 0x31 , 0 , 0 } , -+ { 0x3708 , 0x64 , 0 , 0 } , -+ { 0x3709 , 0x52 , 0 , 0 } , -+ { 0x3808 , 0x05 , 0 , 0 } , -+ { 0x3809 , 0x00 , 0 , 0 } , -+ { 0x380a , 0x02 , 0 , 0 } , -+ { 0x380b , 0xd0 , 0 , 0 } , -+ { 0x3800 , 0x00 , 0 , 0 } , -+ { 0x3801 , 0x00 , 0 , 0 } , -+ { 0x3802 , 0x00 , 0 , 0 } , -+ { 0x3803 , 0x00 , 0 , 0 } , -+ { 0x3804 , 0x0a , 0 , 0 } , -+ { 0x3805 , 0x3f , 0 , 0 } , -+ { 0x3806 , 0x06 , 0 , 0 } , -+ { 0x3807 , 0xb2 , 0 , 0 } , -+ { 0x3811 , 0x08 , 0 , 0 } , -+ { 0x3813 , 0x02 , 0 , 0 } , -+ { 0x3630 , 0x2e , 0 , 0 } , -+ { 0x3632 , 0xe2 , 0 , 0 } , -+ { 0x3633 , 0x23 , 0 , 0 } , -+ { 0x3634 , 0x44 , 0 , 0 } , -+ { 0x3636 , 0x06 , 0 , 0 } , -+ { 0x3620 , 0x64 , 0 , 0 } , -+ { 0x3621 , 0xe0 , 0 , 0 } , -+ { 0x3600 , 0x37 , 0 , 0 } , -+ { 0x3704 , 0xa0 , 0 , 0 } , -+ { 0x3703 , 0x5a , 0 , 0 } , -+ { 0x3715 , 0x78 , 0 , 0 } , -+ { 0x3717 , 0x01 , 0 , 0 } , -+ { 0x3731 , 0x02 , 0 , 0 } , -+ { 0x370b , 0x60 , 0 , 0 } , -+ { 0x3705 , 0x1a , 0 , 0 } , -+ { 0x3f05 , 0x02 , 0 , 0 } , -+ { 0x3f06 , 0x10 , 0 , 0 } , -+ { 0x3f01 , 0x0a , 0 , 0 } , -+ { 0x3a08 , 0x01 , 0 , 0 } , -+ { 0x3a09 , 0x27 , 0 , 0 } , -+ { 0x3a0a , 0x00 , 0 , 0 } , -+ { 0x3a0b , 0xf6 , 0 , 0 } , -+ { 0x3a0d , 0x04 , 0 , 0 } , -+ { 0x3a0e , 0x03 , 0 , 0 } , -+ { 0x3a0f , 0x58 , 0 , 0 } , -+ { 0x3a10 , 0x50 , 0 , 0 } , -+ { 0x3a1b , 0x58 , 0 , 0 } , -+ { 0x3a1e , 0x50 , 0 , 0 } , -+ { 0x3a11 , 0x60 , 0 , 0 } , -+ { 0x3a1f , 0x28 , 0 , 300 } , -+ { 0x4001 , 0x02 , 0 , 0 } , -+ { 0x4004 , 0x02 , 0 , 0 } , -+ { 0x4000 , 0x09 , 0 , 0 } , -+ { 0x4837 , 0x24 , 0 , 0 } , -+ { 0x4050 , 0x6e , 0 , 0 } , -+ { 0x4051 , 0x8f , 0 , 0 } , -+ { 0x0100 , 0x01 , 0 , 0 } , -+#if 0 -+ { 0x503d , 0xc0 , 0 , 0 } , /* test pattern */ -+ { 0x503e , 0x11 , 0 , 0 } , /* test pattern */ -+#endif -+ { 0x5000 , 0x86 , 0 , 0 } , /* enable LENC registers */ -+ { 0x5800 , 0x00 , 0 , 0 } , -+ { 0x5801 , 0x00 , 0 , 0 } , -+ { 0x5802 , 0x00 , 0 , 0 } , -+ { 0x5803 , 0x00 , 0 , 0 } , -+ { 0x5804 , 0x00 , 0 , 0 } , -+ { 0x5805 , 0x00 , 0 , 0 } , -+ { 0x5806 , 0x00 , 0 , 0 } , -+ { 0x5807 , 0x00 , 0 , 0 } , -+ { 0x5808 , 0x00 , 0 , 0 } , -+ { 0x5809 , 0x00 , 0 , 0 } , -+ { 0x580a , 0x00 , 0 , 0 } , -+ { 0x580b , 0x00 , 0 , 0 } , -+ { 0x580c , 0x00 , 0 , 0 } , -+ { 0x580d , 0x00 , 0 , 0 } , -+ { 0x580e , 0x00 , 0 , 0 } , -+ { 0x580f , 0x00 , 0 , 0 } , -+ { 0x5810 , 0x00 , 0 , 0 } , -+ { 0x5811 , 0x00 , 0 , 0 } , -+ { 0x5812 , 0x00 , 0 , 0 } , -+ { 0x5813 , 0x00 , 0 , 0 } , -+ { 0x5814 , 0x00 , 0 , 0 } , -+ { 0x5815 , 0x00 , 0 , 0 } , -+ { 0x5816 , 0x00 , 0 , 0 } , -+ { 0x5817 , 0x00 , 0 , 0 } , -+ { 0x5818 , 0x00 , 0 , 0 } , -+ { 0x5819 , 0x00 , 0 , 0 } , -+ { 0x581a , 0x00 , 0 , 0 } , -+ { 0x581b , 0x00 , 0 , 0 } , -+ { 0x581c , 0x00 , 0 , 0 } , -+ { 0x581d , 0x00 , 0 , 0 } , -+ { 0x581e , 0x00 , 0 , 0 } , -+ { 0x581f , 0x00 , 0 , 0 } , -+ { 0x5820 , 0x00 , 0 , 0 } , -+ { 0x5821 , 0x00 , 0 , 0 } , -+ { 0x5822 , 0x00 , 0 , 0 } , -+ { 0x5823 , 0x00 , 0 , 0 } , -+ { 0x5824 , 0xfe , 0 , 0 } , -+ { 0x5825 , 0xfe , 0 , 0 } , -+ { 0x5826 , 0xfe , 0 , 0 } , -+ { 0x5827 , 0xfe , 0 , 0 } , -+ { 0x5828 , 0xfe , 0 , 0 } , -+ { 0x5829 , 0xfe , 0 , 0 } , -+ { 0x582a , 0xed , 0 , 0 } , -+ { 0x582b , 0xed , 0 , 0 } , -+ { 0x582c , 0xed , 0 , 0 } , -+ { 0x582d , 0xfe , 0 , 0 } , -+ { 0x582e , 0xfe , 0 , 0 } , -+ { 0x582f , 0xed , 0 , 0 } , -+ { 0x5830 , 0xdc , 0 , 0 } , -+ { 0x5831 , 0xed , 0 , 0 } , -+ { 0x5832 , 0xfe , 0 , 0 } , -+ { 0x5833 , 0xfe , 0 , 0 } , -+ { 0x5834 , 0xed , 0 , 0 } , -+ { 0x5835 , 0xed , 0 , 0 } , -+ { 0x5836 , 0xed , 0 , 0 } , -+ { 0x5837 , 0xfe , 0 , 0 } , -+ { 0x5838 , 0xfe , 0 , 0 } , -+ { 0x5839 , 0xfe , 0 , 0 } , -+ { 0x583a , 0xfe , 0 , 0 } , -+ { 0x583b , 0xfe , 0 , 0 } , -+ { 0x583c , 0xfe , 0 , 0 } , -+ { 0x583d , 0xce , 0 , 0 } , -+ { 0x3501 , 0x10 , 0 , 0 } , -+ { 0x3502 , 0x80 , 0 , 0 } , -+ { 0x350a , 0x00 , 0 , 0 } , -+ { 0x350b , 0x7f , 0 , 0 } , -+ { 0x3c00 , 0x04 , 0 , 300 } , -+ { 0x3002 , 0xe4 , 0x01, 0 } , /* enable all outputs */ -+}; -+ -+static struct reg_value ov5647_setting_30fps_1080P_1920_1080[] = { -+ { 0x0100 , 0x00 , 0 , 0 } , -+ { 0x0103 , 0x01 , 0 , 0 } , -+ { 0x3034 , 0x18 , 0 , 0 } , /* was 0x1A */ -+ { 0x3035 , 0x21 , 0 , 0 } , -+ { 0x3036 , 0x7b , 0 , 0 } , -+ { 0x303c , 0x11 , 0 , 0 } , -+ { 0x3106 , 0xf5 , 0 , 0 } , -+ { 0x3821 , 0x06 , 0 , 0 } , -+ { 0x3820 , 0x00 , 0 , 0 } , -+ { 0x3827 , 0xec , 0 , 0 } , -+ { 0x370c , 0x03 , 0 , 0 } , -+ { 0x3612 , 0x4b , 0 , 0 } , -+ { 0x3618 , 0x04 , 0 , 0 } , -+ { 0x5001 , 0x01 , 0 , 0 } , -+ { 0x5002 , 0x40 , 0 , 0 } , -+ { 0x5003 , 0x08 , 0 , 0 } , -+ { 0x5a00 , 0x08 , 0 , 0 } , -+ { 0x3000 , 0x00 , 0 , 0 } , -+ { 0x3001 , 0x00 , 0 , 0 } , -+ { 0x3002 , 0x00 , 0 , 0 } , -+ { 0x3016 , 0x08 , 0 , 0 } , -+ { 0x3017 , 0xe0 , 0 , 0 } , -+ { 0x3018 , 0x44 , 0 , 0 } , -+ { 0x301c , 0xf8 , 0 , 0 } , -+ { 0x301d , 0xf0 , 0 , 0 } , -+ { 0x3a18 , 0x00 , 0 , 0 } , -+ { 0x3a19 , 0xf8 , 0 , 0 } , -+ { 0x3c01 , 0x80 , 0 , 0 } , -+ { 0x3b07 , 0x0c , 0 , 0 } , -+ { 0x380c , 0x36 , 0 , 0 } , -+ { 0x380d , 0x4e , 0 , 0 } , -+ { 0x380e , 0x04 , 0 , 0 } , -+ { 0x380f , 0x60 , 0 , 0 } , -+ { 0x3814 , 0x11 , 0 , 0 } , -+ { 0x3815 , 0x11 , 0 , 0 } , -+ { 0x3708 , 0x64 , 0 , 0 } , -+ { 0x3709 , 0x52 , 0 , 0 } , -+ { 0x3808 , 0x07 , 0 , 0 } , -+ { 0x3809 , 0x80 , 0 , 0 } , -+ { 0x380a , 0x04 , 0 , 0 } , -+ { 0x380b , 0x39 , 0 , 0 } , -+ { 0x3800 , 0x01 , 0 , 0 } , -+ { 0x3801 , 0x5c , 0 , 0 } , -+ { 0x3802 , 0x01 , 0 , 0 } , -+ { 0x3803 , 0xb2 , 0 , 0 } , -+ { 0x3804 , 0x08 , 0 , 0 } , -+ { 0x3805 , 0xe7 , 0 , 0 } , -+ { 0x3806 , 0x05 , 0 , 0 } , -+ { 0x3807 , 0xf1 , 0 , 0 } , -+ { 0x3811 , 0x08 , 0 , 0 } , -+ { 0x3813 , 0x02 , 0 , 0 } , -+ { 0x3630 , 0x2e , 0 , 0 } , -+ { 0x3632 , 0xe2 , 0 , 0 } , -+ { 0x3633 , 0x23 , 0 , 0 } , -+ { 0x3634 , 0x44 , 0 , 0 } , -+ { 0x3636 , 0x06 , 0 , 0 } , -+ { 0x3620 , 0x64 , 0 , 0 } , -+ { 0x3621 , 0xe0 , 0 , 0 } , -+ { 0x3600 , 0x37 , 0 , 0 } , -+ { 0x3704 , 0xa0 , 0 , 0 } , -+ { 0x3703 , 0x5a , 0 , 0 } , -+ { 0x3715 , 0x78 , 0 , 0 } , -+ { 0x3717 , 0x01 , 0 , 0 } , -+ { 0x3731 , 0x02 , 0 , 0 } , -+ { 0x370b , 0x60 , 0 , 0 } , -+ { 0x3705 , 0x1a , 0 , 0 } , -+ { 0x3f05 , 0x02 , 0 , 0 } , -+ { 0x3f06 , 0x10 , 0 , 0 } , -+ { 0x3f01 , 0x0a , 0 , 0 } , -+ { 0x3a08 , 0x01 , 0 , 0 } , -+ { 0x3a09 , 0x27 , 0 , 0 } , -+ { 0x3a0a , 0x00 , 0 , 0 } , -+ { 0x3a0b , 0xf6 , 0 , 0 } , -+ { 0x3a0d , 0x04 , 0 , 0 } , -+ { 0x3a0e , 0x03 , 0 , 0 } , -+ { 0x3a0f , 0x58 , 0 , 0 } , -+ { 0x3a10 , 0x50 , 0 , 0 } , -+ { 0x3a1b , 0x58 , 0 , 0 } , -+ { 0x3a1e , 0x50 , 0 , 0 } , -+ { 0x3a11 , 0x60 , 0 , 0 } , -+ { 0x3a1f , 0x28 , 0 , 300 } , -+ { 0x4001 , 0x02 , 0 , 0 } , -+ { 0x4004 , 0x02 , 0 , 0 } , -+ { 0x4000 , 0x09 , 0 , 0 } , -+ { 0x4837 , 0x24 , 0 , 0 } , -+ { 0x4050 , 0x6e , 0 , 0 } , -+ { 0x4051 , 0x8f , 0 , 0 } , -+ { 0x0100 , 0x01 , 0 , 0 } , -+#if 0 -+ { 0x503d , 0xc0 , 0 , 0 } , /* test pattern */ -+ { 0x503e , 0x11 , 0 , 0 } , /* test pattern */ -+#endif -+ { 0x5000 , 0x86 , 0 , 0 } , /* enable LENC registers */ -+ { 0x5800 , 0x00 , 0 , 0 } , -+ { 0x5801 , 0x00 , 0 , 0 } , -+ { 0x5802 , 0x00 , 0 , 0 } , -+ { 0x5803 , 0x00 , 0 , 0 } , -+ { 0x5804 , 0x00 , 0 , 0 } , -+ { 0x5805 , 0x00 , 0 , 0 } , -+ { 0x5806 , 0x00 , 0 , 0 } , -+ { 0x5807 , 0x00 , 0 , 0 } , -+ { 0x5808 , 0x00 , 0 , 0 } , -+ { 0x5809 , 0x00 , 0 , 0 } , -+ { 0x580a , 0x00 , 0 , 0 } , -+ { 0x580b , 0x00 , 0 , 0 } , -+ { 0x580c , 0x00 , 0 , 0 } , -+ { 0x580d , 0x00 , 0 , 0 } , -+ { 0x580e , 0x00 , 0 , 0 } , -+ { 0x580f , 0x00 , 0 , 0 } , -+ { 0x5810 , 0x00 , 0 , 0 } , -+ { 0x5811 , 0x00 , 0 , 0 } , -+ { 0x5812 , 0x00 , 0 , 0 } , -+ { 0x5813 , 0x00 , 0 , 0 } , -+ { 0x5814 , 0x00 , 0 , 0 } , -+ { 0x5815 , 0x00 , 0 , 0 } , -+ { 0x5816 , 0x00 , 0 , 0 } , -+ { 0x5817 , 0x00 , 0 , 0 } , -+ { 0x5818 , 0x00 , 0 , 0 } , -+ { 0x5819 , 0x00 , 0 , 0 } , -+ { 0x581a , 0x00 , 0 , 0 } , -+ { 0x581b , 0x00 , 0 , 0 } , -+ { 0x581c , 0x00 , 0 , 0 } , -+ { 0x581d , 0x00 , 0 , 0 } , -+ { 0x581e , 0x00 , 0 , 0 } , -+ { 0x581f , 0x00 , 0 , 0 } , -+ { 0x5820 , 0x00 , 0 , 0 } , -+ { 0x5821 , 0x00 , 0 , 0 } , -+ { 0x5822 , 0x00 , 0 , 0 } , -+ { 0x5823 , 0x00 , 0 , 0 } , -+ { 0x5824 , 0xfe , 0 , 0 } , -+ { 0x5825 , 0xfe , 0 , 0 } , -+ { 0x5826 , 0xfe , 0 , 0 } , -+ { 0x5827 , 0xfe , 0 , 0 } , -+ { 0x5828 , 0xfe , 0 , 0 } , -+ { 0x5829 , 0xfe , 0 , 0 } , -+ { 0x582a , 0xed , 0 , 0 } , -+ { 0x582b , 0xed , 0 , 0 } , -+ { 0x582c , 0xed , 0 , 0 } , -+ { 0x582d , 0xfe , 0 , 0 } , -+ { 0x582e , 0xfe , 0 , 0 } , -+ { 0x582f , 0xed , 0 , 0 } , -+ { 0x5830 , 0xdc , 0 , 0 } , -+ { 0x5831 , 0xed , 0 , 0 } , -+ { 0x5832 , 0xfe , 0 , 0 } , -+ { 0x5833 , 0xfe , 0 , 0 } , -+ { 0x5834 , 0xed , 0 , 0 } , -+ { 0x5835 , 0xed , 0 , 0 } , -+ { 0x5836 , 0xed , 0 , 0 } , -+ { 0x5837 , 0xfe , 0 , 0 } , -+ { 0x5838 , 0xfe , 0 , 0 } , -+ { 0x5839 , 0xfe , 0 , 0 } , -+ { 0x583a , 0xfe , 0 , 0 } , -+ { 0x583b , 0xfe , 0 , 0 } , -+ { 0x583c , 0xfe , 0 , 0 } , -+ { 0x583d , 0xce , 0 , 0 } , -+ { 0x3501 , 0x10 , 0 , 0 } , -+ { 0x3502 , 0x80 , 0 , 0 } , -+ { 0x350a , 0x00 , 0 , 0 } , -+ { 0x350b , 0x7f , 0 , 0 } , -+ { 0x3c00 , 0x04 , 0 , 300 } , -+ { 0x3002 , 0xe4 , 0x01, 0 } , /* enable all outputs */ -+}; -+ -+static struct reg_value ov5647_setting_15fps_1080P_1920_1080[] = { -+ { 0x0100 , 0x00 , 0 , 0 } , -+ { 0x0103 , 0x01 , 0 , 0 } , -+ { 0x3034 , 0x18 , 0 , 0 } , /* was 0x1A */ -+ { 0x3035 , 0x41 , 0 , 0 } , -+ { 0x3036 , 0x7b , 0 , 0 } , -+ { 0x303c , 0x11 , 0 , 0 } , -+ { 0x3106 , 0xf5 , 0 , 0 } , -+ { 0x3821 , 0x06 , 0 , 0 } , -+ { 0x3820 , 0x00 , 0 , 0 } , -+ { 0x3827 , 0xec , 0 , 0 } , -+ { 0x370c , 0x03 , 0 , 0 } , -+ { 0x3612 , 0x4b , 0 , 0 } , -+ { 0x3618 , 0x04 , 0 , 0 } , -+ { 0x5001 , 0x01 , 0 , 0 } , -+ { 0x5002 , 0x40 , 0 , 0 } , -+ { 0x5003 , 0x08 , 0 , 0 } , -+ { 0x5a00 , 0x08 , 0 , 0 } , -+ { 0x3000 , 0x00 , 0 , 0 } , -+ { 0x3001 , 0x00 , 0 , 0 } , -+ { 0x3002 , 0x00 , 0 , 0 } , -+ { 0x3016 , 0x08 , 0 , 0 } , -+ { 0x3017 , 0xe0 , 0 , 0 } , -+ { 0x3018 , 0x44 , 0 , 0 } , -+ { 0x301c , 0xf8 , 0 , 0 } , -+ { 0x301d , 0xf0 , 0 , 0 } , -+ { 0x3a18 , 0x00 , 0 , 0 } , -+ { 0x3a19 , 0xf8 , 0 , 0 } , -+ { 0x3c01 , 0x80 , 0 , 0 } , -+ { 0x3b07 , 0x0c , 0 , 0 } , -+ { 0x380c , 0x36 , 0 , 0 } , -+ { 0x380d , 0x4e , 0 , 0 } , -+ { 0x380e , 0x04 , 0 , 0 } , -+ { 0x380f , 0x60 , 0 , 0 } , -+ { 0x3814 , 0x11 , 0 , 0 } , -+ { 0x3815 , 0x11 , 0 , 0 } , -+ { 0x3708 , 0x64 , 0 , 0 } , -+ { 0x3709 , 0x52 , 0 , 0 } , -+ { 0x3808 , 0x07 , 0 , 0 } , -+ { 0x3809 , 0x80 , 0 , 0 } , -+ { 0x380a , 0x04 , 0 , 0 } , -+ { 0x380b , 0x39 , 0 , 0 } , -+ { 0x3800 , 0x01 , 0 , 0 } , -+ { 0x3801 , 0x5c , 0 , 0 } , -+ { 0x3802 , 0x01 , 0 , 0 } , -+ { 0x3803 , 0xb2 , 0 , 0 } , -+ { 0x3804 , 0x08 , 0 , 0 } , -+ { 0x3805 , 0xe7 , 0 , 0 } , -+ { 0x3806 , 0x05 , 0 , 0 } , -+ { 0x3807 , 0xf1 , 0 , 0 } , -+ { 0x3811 , 0x08 , 0 , 0 } , -+ { 0x3813 , 0x02 , 0 , 0 } , -+ { 0x3630 , 0x2e , 0 , 0 } , -+ { 0x3632 , 0xe2 , 0 , 0 } , -+ { 0x3633 , 0x23 , 0 , 0 } , -+ { 0x3634 , 0x44 , 0 , 0 } , -+ { 0x3636 , 0x06 , 0 , 0 } , -+ { 0x3620 , 0x64 , 0 , 0 } , -+ { 0x3621 , 0xe0 , 0 , 0 } , -+ { 0x3600 , 0x37 , 0 , 0 } , -+ { 0x3704 , 0xa0 , 0 , 0 } , -+ { 0x3703 , 0x5a , 0 , 0 } , -+ { 0x3715 , 0x78 , 0 , 0 } , -+ { 0x3717 , 0x01 , 0 , 0 } , -+ { 0x3731 , 0x02 , 0 , 0 } , -+ { 0x370b , 0x60 , 0 , 0 } , -+ { 0x3705 , 0x1a , 0 , 0 } , -+ { 0x3f05 , 0x02 , 0 , 0 } , -+ { 0x3f06 , 0x10 , 0 , 0 } , -+ { 0x3f01 , 0x0a , 0 , 0 } , -+ { 0x3a08 , 0x01 , 0 , 0 } , -+ { 0x3a09 , 0x27 , 0 , 0 } , -+ { 0x3a0a , 0x00 , 0 , 0 } , -+ { 0x3a0b , 0xf6 , 0 , 0 } , -+ { 0x3a0d , 0x04 , 0 , 0 } , -+ { 0x3a0e , 0x03 , 0 , 0 } , -+ { 0x3a0f , 0x58 , 0 , 0 } , -+ { 0x3a10 , 0x50 , 0 , 0 } , -+ { 0x3a1b , 0x58 , 0 , 0 } , -+ { 0x3a1e , 0x50 , 0 , 0 } , -+ { 0x3a11 , 0x60 , 0 , 0 } , -+ { 0x3a1f , 0x28 , 0 , 300 } , -+ { 0x4001 , 0x02 , 0 , 0 } , -+ { 0x4004 , 0x02 , 0 , 0 } , -+ { 0x4000 , 0x09 , 0 , 0 } , -+ { 0x4837 , 0x24 , 0 , 0 } , -+ { 0x4050 , 0x6e , 0 , 0 } , -+ { 0x4051 , 0x8f , 0 , 0 } , -+ { 0x0100 , 0x01 , 0 , 0 } , -+#if 0 -+ { 0x503d , 0xc0 , 0 , 0 } , /* test pattern */ -+ { 0x503e , 0x11 , 0 , 0 } , /* test pattern */ -+#endif -+ { 0x5000 , 0x86 , 0 , 0 } , /* enable LENC registers */ -+ { 0x5800 , 0x00 , 0 , 0 } , -+ { 0x5801 , 0x00 , 0 , 0 } , -+ { 0x5802 , 0x00 , 0 , 0 } , -+ { 0x5803 , 0x00 , 0 , 0 } , -+ { 0x5804 , 0x00 , 0 , 0 } , -+ { 0x5805 , 0x00 , 0 , 0 } , -+ { 0x5806 , 0x00 , 0 , 0 } , -+ { 0x5807 , 0x00 , 0 , 0 } , -+ { 0x5808 , 0x00 , 0 , 0 } , -+ { 0x5809 , 0x00 , 0 , 0 } , -+ { 0x580a , 0x00 , 0 , 0 } , -+ { 0x580b , 0x00 , 0 , 0 } , -+ { 0x580c , 0x00 , 0 , 0 } , -+ { 0x580d , 0x00 , 0 , 0 } , -+ { 0x580e , 0x00 , 0 , 0 } , -+ { 0x580f , 0x00 , 0 , 0 } , -+ { 0x5810 , 0x00 , 0 , 0 } , -+ { 0x5811 , 0x00 , 0 , 0 } , -+ { 0x5812 , 0x00 , 0 , 0 } , -+ { 0x5813 , 0x00 , 0 , 0 } , -+ { 0x5814 , 0x00 , 0 , 0 } , -+ { 0x5815 , 0x00 , 0 , 0 } , -+ { 0x5816 , 0x00 , 0 , 0 } , -+ { 0x5817 , 0x00 , 0 , 0 } , -+ { 0x5818 , 0x00 , 0 , 0 } , -+ { 0x5819 , 0x00 , 0 , 0 } , -+ { 0x581a , 0x00 , 0 , 0 } , -+ { 0x581b , 0x00 , 0 , 0 } , -+ { 0x581c , 0x00 , 0 , 0 } , -+ { 0x581d , 0x00 , 0 , 0 } , -+ { 0x581e , 0x00 , 0 , 0 } , -+ { 0x581f , 0x00 , 0 , 0 } , -+ { 0x5820 , 0x00 , 0 , 0 } , -+ { 0x5821 , 0x00 , 0 , 0 } , -+ { 0x5822 , 0x00 , 0 , 0 } , -+ { 0x5823 , 0x00 , 0 , 0 } , -+ { 0x5824 , 0xfe , 0 , 0 } , -+ { 0x5825 , 0xfe , 0 , 0 } , -+ { 0x5826 , 0xfe , 0 , 0 } , -+ { 0x5827 , 0xfe , 0 , 0 } , -+ { 0x5828 , 0xfe , 0 , 0 } , -+ { 0x5829 , 0xfe , 0 , 0 } , -+ { 0x582a , 0xed , 0 , 0 } , -+ { 0x582b , 0xed , 0 , 0 } , -+ { 0x582c , 0xed , 0 , 0 } , -+ { 0x582d , 0xfe , 0 , 0 } , -+ { 0x582e , 0xfe , 0 , 0 } , -+ { 0x582f , 0xed , 0 , 0 } , -+ { 0x5830 , 0xdc , 0 , 0 } , -+ { 0x5831 , 0xed , 0 , 0 } , -+ { 0x5832 , 0xfe , 0 , 0 } , -+ { 0x5833 , 0xfe , 0 , 0 } , -+ { 0x5834 , 0xed , 0 , 0 } , -+ { 0x5835 , 0xed , 0 , 0 } , -+ { 0x5836 , 0xed , 0 , 0 } , -+ { 0x5837 , 0xfe , 0 , 0 } , -+ { 0x5838 , 0xfe , 0 , 0 } , -+ { 0x5839 , 0xfe , 0 , 0 } , -+ { 0x583a , 0xfe , 0 , 0 } , -+ { 0x583b , 0xfe , 0 , 0 } , -+ { 0x583c , 0xfe , 0 , 0 } , -+ { 0x583d , 0xce , 0 , 0 } , -+ { 0x3501 , 0x10 , 0 , 0 } , -+ { 0x3502 , 0x80 , 0 , 0 } , -+ { 0x350a , 0x00 , 0 , 0 } , -+ { 0x350b , 0x7f , 0 , 0 } , -+ { 0x3c00 , 0x04 , 0 , 300 } , -+ { 0x3002 , 0xe4 , 0x01, 0 } , /* enable all outputs */ -+}; -+ -+static struct reg_value ov5647_setting_30fps_VGA_640_480[] = { -+ { 0x0100 , 0x00 , 0 , 0 } , -+ { 0x0103 , 0x01 , 0 , 0 } , -+ { 0x3034 , 0x18 , 0 , 0 } , /* was 0x1A */ -+ { 0x3035 , 0x21 , 0 , 0 } , -+ { 0x3036 , 0x52 , 0 , 0 } , -+ { 0x303c , 0x11 , 0 , 0 } , -+ { 0x3106 , 0xf5 , 0 , 0 } , -+ { 0x3821 , 0x07 , 0 , 0 } , -+ { 0x3820 , 0x41 , 0 , 0 } , -+ { 0x3827 , 0xec , 0 , 0 } , -+ { 0x370c , 0x03 , 0 , 0 } , -+ { 0x3612 , 0x4b , 0 , 0 } , -+ { 0x3618 , 0x00 , 0 , 0 } , -+ { 0x5001 , 0x01 , 0 , 0 } , -+ { 0x5002 , 0x40 , 0 , 0 } , -+ { 0x5003 , 0x08 , 0 , 0 } , -+ { 0x5a00 , 0x08 , 0 , 0 } , -+ { 0x3000 , 0x00 , 0 , 0 } , -+ { 0x3001 , 0x00 , 0 , 0 } , -+ { 0x3002 , 0x00 , 0 , 0 } , -+ { 0x3016 , 0x08 , 0 , 0 } , -+ { 0x3017 , 0xe0 , 0 , 0 } , -+ { 0x3018 , 0x44 , 0 , 0 } , -+ { 0x301c , 0xf8 , 0 , 0 } , -+ { 0x301d , 0xf0 , 0 , 0 } , -+ { 0x3a18 , 0x00 , 0 , 0 } , -+ { 0x3a19 , 0xf8 , 0 , 0 } , -+ { 0x3c01 , 0x80 , 0 , 0 } , -+ { 0x3b07 , 0x0c , 0 , 0 } , -+ { 0x380c , 0x07 , 0 , 0 } , -+ { 0x380d , 0x68 , 0 , 0 } , -+ { 0x380e , 0x03 , 0 , 0 } , -+ { 0x380f , 0xd8 , 0 , 0 } , -+ { 0x3814 , 0x71 , 0 , 0 } , -+ { 0x3815 , 0x71 , 0 , 0 } , -+ { 0x3708 , 0x64 , 0 , 0 } , -+ { 0x3709 , 0x52 , 0 , 0 } , -+ { 0x3808 , 0x02 , 0 , 0 } , -+ { 0x3809 , 0x80 , 0 , 0 } , -+ { 0x380a , 0x01 , 0 , 0 } , -+ { 0x380b , 0xe0 , 0 , 0 } , -+ { 0x3800 , 0x00 , 0 , 0 } , -+ { 0x3801 , 0x00 , 0 , 0 } , -+ { 0x3802 , 0x00 , 0 , 0 } , -+ { 0x3803 , 0x00 , 0 , 0 } , -+ { 0x3804 , 0x0a , 0 , 0 } , -+ { 0x3805 , 0x3f , 0 , 0 } , -+ { 0x3806 , 0x07 , 0 , 0 } , -+ { 0x3807 , 0xa1 , 0 , 0 } , -+ { 0x3811 , 0x08 , 0 , 0 } , -+ { 0x3813 , 0x02 , 0 , 0 } , -+ { 0x3630 , 0x2e , 0 , 0 } , -+ { 0x3632 , 0xe2 , 0 , 0 } , -+ { 0x3633 , 0x23 , 0 , 0 } , -+ { 0x3634 , 0x44 , 0 , 0 } , -+ { 0x3636 , 0x06 , 0 , 0 } , -+ { 0x3620 , 0x64 , 0 , 0 } , -+ { 0x3621 , 0xe0 , 0 , 0 } , -+ { 0x3600 , 0x37 , 0 , 0 } , -+ { 0x3704 , 0xa0 , 0 , 0 } , -+ { 0x3703 , 0x5a , 0 , 0 } , -+ { 0x3715 , 0x78 , 0 , 0 } , -+ { 0x3717 , 0x01 , 0 , 0 } , -+ { 0x3731 , 0x02 , 0 , 0 } , -+ { 0x370b , 0x60 , 0 , 0 } , -+ { 0x3705 , 0x1a , 0 , 0 } , -+ { 0x3f05 , 0x02 , 0 , 0 } , -+ { 0x3f06 , 0x10 , 0 , 0 } , -+ { 0x3f01 , 0x0a , 0 , 0 } , -+ { 0x3a08 , 0x01 , 0 , 0 } , -+ { 0x3a09 , 0x27 , 0 , 0 } , -+ { 0x3a0a , 0x00 , 0 , 0 } , -+ { 0x3a0b , 0xf6 , 0 , 0 } , -+ { 0x3a0d , 0x04 , 0 , 0 } , -+ { 0x3a0e , 0x03 , 0 , 0 } , -+ { 0x3a0f , 0x58 , 0 , 0 } , -+ { 0x3a10 , 0x50 , 0 , 0 } , -+ { 0x3a1b , 0x58 , 0 , 0 } , -+ { 0x3a1e , 0x50 , 0 , 0 } , -+ { 0x3a11 , 0x60 , 0 , 0 } , -+ { 0x3a1f , 0x28 , 0 , 300 } , -+ { 0x4001 , 0x02 , 0 , 0 } , -+ { 0x4004 , 0x02 , 0 , 0 } , -+ { 0x4000 , 0x09 , 0 , 0 } , -+ { 0x4837 , 0x24 , 0 , 0 } , -+ { 0x4050 , 0x6e , 0 , 0 } , -+ { 0x4051 , 0x8f , 0 , 0 } , -+ { 0x0100 , 0x01 , 0 , 0 } , -+#if 0 -+ { 0x503d , 0xc0 , 0 , 0 } , /* test pattern */ -+ { 0x503e , 0x11 , 0 , 0 } , /* test pattern */ -+#endif -+ { 0x5000 , 0x86 , 0 , 0 } , /* enable LENC registers */ -+ { 0x5800 , 0x00 , 0 , 0 } , -+ { 0x5801 , 0x00 , 0 , 0 } , -+ { 0x5802 , 0x00 , 0 , 0 } , -+ { 0x5803 , 0x00 , 0 , 0 } , -+ { 0x5804 , 0x00 , 0 , 0 } , -+ { 0x5805 , 0x00 , 0 , 0 } , -+ { 0x5806 , 0x00 , 0 , 0 } , -+ { 0x5807 , 0x00 , 0 , 0 } , -+ { 0x5808 , 0x00 , 0 , 0 } , -+ { 0x5809 , 0x00 , 0 , 0 } , -+ { 0x580a , 0x00 , 0 , 0 } , -+ { 0x580b , 0x00 , 0 , 0 } , -+ { 0x580c , 0x00 , 0 , 0 } , -+ { 0x580d , 0x00 , 0 , 0 } , -+ { 0x580e , 0x00 , 0 , 0 } , -+ { 0x580f , 0x00 , 0 , 0 } , -+ { 0x5810 , 0x00 , 0 , 0 } , -+ { 0x5811 , 0x00 , 0 , 0 } , -+ { 0x5812 , 0x00 , 0 , 0 } , -+ { 0x5813 , 0x00 , 0 , 0 } , -+ { 0x5814 , 0x00 , 0 , 0 } , -+ { 0x5815 , 0x00 , 0 , 0 } , -+ { 0x5816 , 0x00 , 0 , 0 } , -+ { 0x5817 , 0x00 , 0 , 0 } , -+ { 0x5818 , 0x00 , 0 , 0 } , -+ { 0x5819 , 0x00 , 0 , 0 } , -+ { 0x581a , 0x00 , 0 , 0 } , -+ { 0x581b , 0x00 , 0 , 0 } , -+ { 0x581c , 0x00 , 0 , 0 } , -+ { 0x581d , 0x00 , 0 , 0 } , -+ { 0x581e , 0x00 , 0 , 0 } , -+ { 0x581f , 0x00 , 0 , 0 } , -+ { 0x5820 , 0x00 , 0 , 0 } , -+ { 0x5821 , 0x00 , 0 , 0 } , -+ { 0x5822 , 0x00 , 0 , 0 } , -+ { 0x5823 , 0x00 , 0 , 0 } , -+ { 0x5824 , 0xfe , 0 , 0 } , -+ { 0x5825 , 0xfe , 0 , 0 } , -+ { 0x5826 , 0xfe , 0 , 0 } , -+ { 0x5827 , 0xfe , 0 , 0 } , -+ { 0x5828 , 0xfe , 0 , 0 } , -+ { 0x5829 , 0xfe , 0 , 0 } , -+ { 0x582a , 0xed , 0 , 0 } , -+ { 0x582b , 0xed , 0 , 0 } , -+ { 0x582c , 0xed , 0 , 0 } , -+ { 0x582d , 0xfe , 0 , 0 } , -+ { 0x582e , 0xfe , 0 , 0 } , -+ { 0x582f , 0xed , 0 , 0 } , -+ { 0x5830 , 0xdc , 0 , 0 } , -+ { 0x5831 , 0xed , 0 , 0 } , -+ { 0x5832 , 0xfe , 0 , 0 } , -+ { 0x5833 , 0xfe , 0 , 0 } , -+ { 0x5834 , 0xed , 0 , 0 } , -+ { 0x5835 , 0xed , 0 , 0 } , -+ { 0x5836 , 0xed , 0 , 0 } , -+ { 0x5837 , 0xfe , 0 , 0 } , -+ { 0x5838 , 0xfe , 0 , 0 } , -+ { 0x5839 , 0xfe , 0 , 0 } , -+ { 0x583a , 0xfe , 0 , 0 } , -+ { 0x583b , 0xfe , 0 , 0 } , -+ { 0x583c , 0xfe , 0 , 0 } , -+ { 0x583d , 0xce , 0 , 0 } , -+ { 0x3501 , 0x10 , 0 , 0 } , -+ { 0x3502 , 0x80 , 0 , 0 } , -+ { 0x350a , 0x00 , 0 , 0 } , -+ { 0x350b , 0x7f , 0 , 0 } , -+ { 0x3c00 , 0x04 , 0 , 300 } , -+ { 0x3002 , 0xe4 , 0x01, 0 } , /* enable all outputs */ -+ { 0x3814 , 0x31 , 0 , 0 } , /* overwrite */ -+ { 0x3815 , 0x31 , 0 , 0 } , /* overwrite */ -+}; -+ -+static struct reg_value ov5647_setting_15fps_VGA_640_480[] = { -+ { 0x0100 , 0x00 , 0 , 0 } , -+ { 0x0103 , 0x01 , 0 , 0 } , -+ { 0x3034 , 0x18 , 0 , 0 } , /* was 0x1A */ -+ { 0x3035 , 0x41 , 0 , 0 } , -+ { 0x3036 , 0x52 , 0 , 0 } , -+ { 0x303c , 0x11 , 0 , 0 } , -+ { 0x3106 , 0xf5 , 0 , 0 } , -+ { 0x3821 , 0x07 , 0 , 0 } , -+ { 0x3820 , 0x41 , 0 , 0 } , -+ { 0x3827 , 0xec , 0 , 0 } , -+ { 0x370c , 0x03 , 0 , 0 } , -+ { 0x3612 , 0x4b , 0 , 0 } , -+ { 0x3618 , 0x00 , 0 , 0 } , -+ { 0x5001 , 0x01 , 0 , 0 } , -+ { 0x5002 , 0x40 , 0 , 0 } , -+ { 0x5003 , 0x08 , 0 , 0 } , -+ { 0x5a00 , 0x08 , 0 , 0 } , -+ { 0x3000 , 0x00 , 0 , 0 } , -+ { 0x3001 , 0x00 , 0 , 0 } , -+ { 0x3002 , 0x00 , 0 , 0 } , -+ { 0x3016 , 0x08 , 0 , 0 } , -+ { 0x3017 , 0xe0 , 0 , 0 } , -+ { 0x3018 , 0x44 , 0 , 0 } , -+ { 0x301c , 0xf8 , 0 , 0 } , -+ { 0x301d , 0xf0 , 0 , 0 } , -+ { 0x3a18 , 0x00 , 0 , 0 } , -+ { 0x3a19 , 0xf8 , 0 , 0 } , -+ { 0x3c01 , 0x80 , 0 , 0 } , -+ { 0x3b07 , 0x0c , 0 , 0 } , -+ { 0x380c , 0x07 , 0 , 0 } , -+ { 0x380d , 0x68 , 0 , 0 } , -+ { 0x380e , 0x03 , 0 , 0 } , -+ { 0x380f , 0xd8 , 0 , 0 } , -+ { 0x3814 , 0x71 , 0 , 0 } , -+ { 0x3815 , 0x71 , 0 , 0 } , -+ { 0x3708 , 0x64 , 0 , 0 } , -+ { 0x3709 , 0x52 , 0 , 0 } , -+ { 0x3808 , 0x02 , 0 , 0 } , -+ { 0x3809 , 0x80 , 0 , 0 } , -+ { 0x380a , 0x01 , 0 , 0 } , -+ { 0x380b , 0xe0 , 0 , 0 } , -+ { 0x3800 , 0x00 , 0 , 0 } , -+ { 0x3801 , 0x00 , 0 , 0 } , -+ { 0x3802 , 0x00 , 0 , 0 } , -+ { 0x3803 , 0x00 , 0 , 0 } , -+ { 0x3804 , 0x0a , 0 , 0 } , -+ { 0x3805 , 0x3f , 0 , 0 } , -+ { 0x3806 , 0x07 , 0 , 0 } , -+ { 0x3807 , 0xa1 , 0 , 0 } , -+ { 0x3811 , 0x08 , 0 , 0 } , -+ { 0x3813 , 0x02 , 0 , 0 } , -+ { 0x3630 , 0x2e , 0 , 0 } , -+ { 0x3632 , 0xe2 , 0 , 0 } , -+ { 0x3633 , 0x23 , 0 , 0 } , -+ { 0x3634 , 0x44 , 0 , 0 } , -+ { 0x3636 , 0x06 , 0 , 0 } , -+ { 0x3620 , 0x64 , 0 , 0 } , -+ { 0x3621 , 0xe0 , 0 , 0 } , -+ { 0x3600 , 0x37 , 0 , 0 } , -+ { 0x3704 , 0xa0 , 0 , 0 } , -+ { 0x3703 , 0x5a , 0 , 0 } , -+ { 0x3715 , 0x78 , 0 , 0 } , -+ { 0x3717 , 0x01 , 0 , 0 } , -+ { 0x3731 , 0x02 , 0 , 0 } , -+ { 0x370b , 0x60 , 0 , 0 } , -+ { 0x3705 , 0x1a , 0 , 0 } , -+ { 0x3f05 , 0x02 , 0 , 0 } , -+ { 0x3f06 , 0x10 , 0 , 0 } , -+ { 0x3f01 , 0x0a , 0 , 0 } , -+ { 0x3a08 , 0x01 , 0 , 0 } , -+ { 0x3a09 , 0x27 , 0 , 0 } , -+ { 0x3a0a , 0x00 , 0 , 0 } , -+ { 0x3a0b , 0xf6 , 0 , 0 } , -+ { 0x3a0d , 0x04 , 0 , 0 } , -+ { 0x3a0e , 0x03 , 0 , 0 } , -+ { 0x3a0f , 0x58 , 0 , 0 } , -+ { 0x3a10 , 0x50 , 0 , 0 } , -+ { 0x3a1b , 0x58 , 0 , 0 } , -+ { 0x3a1e , 0x50 , 0 , 0 } , -+ { 0x3a11 , 0x60 , 0 , 0 } , -+ { 0x3a1f , 0x28 , 0 , 300 } , -+ { 0x4001 , 0x02 , 0 , 0 } , -+ { 0x4004 , 0x02 , 0 , 0 } , -+ { 0x4000 , 0x09 , 0 , 0 } , -+ { 0x4837 , 0x24 , 0 , 0 } , -+ { 0x4050 , 0x6e , 0 , 0 } , -+ { 0x4051 , 0x8f , 0 , 0 } , -+ { 0x0100 , 0x01 , 0 , 0 } , -+#if 0 -+ { 0x503d , 0xc0 , 0 , 0 } , /* test pattern */ -+ { 0x503e , 0x11 , 0 , 0 } , /* test pattern */ -+#endif -+ { 0x5000 , 0x86 , 0 , 0 } , /* enable LENC registers */ -+ { 0x5800 , 0x00 , 0 , 0 } , -+ { 0x5801 , 0x00 , 0 , 0 } , -+ { 0x5802 , 0x00 , 0 , 0 } , -+ { 0x5803 , 0x00 , 0 , 0 } , -+ { 0x5804 , 0x00 , 0 , 0 } , -+ { 0x5805 , 0x00 , 0 , 0 } , -+ { 0x5806 , 0x00 , 0 , 0 } , -+ { 0x5807 , 0x00 , 0 , 0 } , -+ { 0x5808 , 0x00 , 0 , 0 } , -+ { 0x5809 , 0x00 , 0 , 0 } , -+ { 0x580a , 0x00 , 0 , 0 } , -+ { 0x580b , 0x00 , 0 , 0 } , -+ { 0x580c , 0x00 , 0 , 0 } , -+ { 0x580d , 0x00 , 0 , 0 } , -+ { 0x580e , 0x00 , 0 , 0 } , -+ { 0x580f , 0x00 , 0 , 0 } , -+ { 0x5810 , 0x00 , 0 , 0 } , -+ { 0x5811 , 0x00 , 0 , 0 } , -+ { 0x5812 , 0x00 , 0 , 0 } , -+ { 0x5813 , 0x00 , 0 , 0 } , -+ { 0x5814 , 0x00 , 0 , 0 } , -+ { 0x5815 , 0x00 , 0 , 0 } , -+ { 0x5816 , 0x00 , 0 , 0 } , -+ { 0x5817 , 0x00 , 0 , 0 } , -+ { 0x5818 , 0x00 , 0 , 0 } , -+ { 0x5819 , 0x00 , 0 , 0 } , -+ { 0x581a , 0x00 , 0 , 0 } , -+ { 0x581b , 0x00 , 0 , 0 } , -+ { 0x581c , 0x00 , 0 , 0 } , -+ { 0x581d , 0x00 , 0 , 0 } , -+ { 0x581e , 0x00 , 0 , 0 } , -+ { 0x581f , 0x00 , 0 , 0 } , -+ { 0x5820 , 0x00 , 0 , 0 } , -+ { 0x5821 , 0x00 , 0 , 0 } , -+ { 0x5822 , 0x00 , 0 , 0 } , -+ { 0x5823 , 0x00 , 0 , 0 } , -+ { 0x5824 , 0xfe , 0 , 0 } , -+ { 0x5825 , 0xfe , 0 , 0 } , -+ { 0x5826 , 0xfe , 0 , 0 } , -+ { 0x5827 , 0xfe , 0 , 0 } , -+ { 0x5828 , 0xfe , 0 , 0 } , -+ { 0x5829 , 0xfe , 0 , 0 } , -+ { 0x582a , 0xed , 0 , 0 } , -+ { 0x582b , 0xed , 0 , 0 } , -+ { 0x582c , 0xed , 0 , 0 } , -+ { 0x582d , 0xfe , 0 , 0 } , -+ { 0x582e , 0xfe , 0 , 0 } , -+ { 0x582f , 0xed , 0 , 0 } , -+ { 0x5830 , 0xdc , 0 , 0 } , -+ { 0x5831 , 0xed , 0 , 0 } , -+ { 0x5832 , 0xfe , 0 , 0 } , -+ { 0x5833 , 0xfe , 0 , 0 } , -+ { 0x5834 , 0xed , 0 , 0 } , -+ { 0x5835 , 0xed , 0 , 0 } , -+ { 0x5836 , 0xed , 0 , 0 } , -+ { 0x5837 , 0xfe , 0 , 0 } , -+ { 0x5838 , 0xfe , 0 , 0 } , -+ { 0x5839 , 0xfe , 0 , 0 } , -+ { 0x583a , 0xfe , 0 , 0 } , -+ { 0x583b , 0xfe , 0 , 0 } , -+ { 0x583c , 0xfe , 0 , 0 } , -+ { 0x583d , 0xce , 0 , 0 } , -+ { 0x3501 , 0x10 , 0 , 0 } , -+ { 0x3502 , 0x80 , 0 , 0 } , -+ { 0x350a , 0x00 , 0 , 0 } , -+ { 0x350b , 0x7f , 0 , 0 } , -+ { 0x3c00 , 0x04 , 0 , 300 } , -+ { 0x3002 , 0xe4 , 0x01, 0 } , /* enable all outputs */ -+ { 0x3814 , 0x31 , 0 , 0 } , /* overwrite */ -+ { 0x3815 , 0x31 , 0 , 0 } , /* overwrite */ -+}; -+ -+static struct reg_value ov5647_setting_30fps_XGA_1024_768[] = { -+ { 0x0100 , 0x00 , 0 , 0 } , -+ { 0x0103 , 0x01 , 0 , 0 } , -+ { 0x3034 , 0x18 , 0 , 0 } , /* was 0x1A */ -+ { 0x3035 , 0x21 , 0 , 0 } , -+ { 0x3036 , 0x52 , 0 , 0 } , -+ { 0x303c , 0x11 , 0 , 0 } , -+ { 0x3106 , 0xf5 , 0 , 0 } , -+ { 0x3821 , 0x07 , 0 , 0 } , -+ { 0x3820 , 0x41 , 0 , 0 } , -+ { 0x3827 , 0xec , 0 , 0 } , -+ { 0x370c , 0x03 , 0 , 0 } , -+ { 0x3612 , 0x4b , 0 , 0 } , -+ { 0x3618 , 0x00 , 0 , 0 } , -+ { 0x5001 , 0x01 , 0 , 0 } , -+ { 0x5002 , 0x40 , 0 , 0 } , -+ { 0x5003 , 0x08 , 0 , 0 } , -+ { 0x5a00 , 0x08 , 0 , 0 } , -+ { 0x3000 , 0x00 , 0 , 0 } , -+ { 0x3001 , 0x00 , 0 , 0 } , -+ { 0x3002 , 0x00 , 0 , 0 } , -+ { 0x3016 , 0x08 , 0 , 0 } , -+ { 0x3017 , 0xe0 , 0 , 0 } , -+ { 0x3018 , 0x44 , 0 , 0 } , -+ { 0x301c , 0xf8 , 0 , 0 } , -+ { 0x301d , 0xf0 , 0 , 0 } , -+ { 0x3a18 , 0x00 , 0 , 0 } , -+ { 0x3a19 , 0xf8 , 0 , 0 } , -+ { 0x3c01 , 0x80 , 0 , 0 } , -+ { 0x3b07 , 0x0c , 0 , 0 } , -+ { 0x380c , 0x07 , 0 , 0 } , -+ { 0x380d , 0x68 , 0 , 0 } , -+ { 0x380e , 0x03 , 0 , 0 } , -+ { 0x380f , 0xd8 , 0 , 0 } , -+ { 0x3814 , 0x31 , 0 , 0 } , -+ { 0x3815 , 0x31 , 0 , 0 } , -+ { 0x3708 , 0x64 , 0 , 0 } , -+ { 0x3709 , 0x52 , 0 , 0 } , -+ { 0x3808 , 0x04 , 0 , 0 } , -+ { 0x3809 , 0x00 , 0 , 0 } , -+ { 0x380a , 0x03 , 0 , 0 } , -+ { 0x380b , 0x00 , 0 , 0 } , -+ { 0x3800 , 0x00 , 0 , 0 } , -+ { 0x3801 , 0x00 , 0 , 0 } , -+ { 0x3802 , 0x00 , 0 , 0 } , -+ { 0x3803 , 0x00 , 0 , 0 } , -+ { 0x3804 , 0x0a , 0 , 0 } , -+ { 0x3805 , 0x3f , 0 , 0 } , -+ { 0x3806 , 0x07 , 0 , 0 } , -+ { 0x3807 , 0xa1 , 0 , 0 } , -+ { 0x3811 , 0x08 , 0 , 0 } , -+ { 0x3813 , 0x02 , 0 , 0 } , -+ { 0x3630 , 0x2e , 0 , 0 } , -+ { 0x3632 , 0xe2 , 0 , 0 } , -+ { 0x3633 , 0x23 , 0 , 0 } , -+ { 0x3634 , 0x44 , 0 , 0 } , -+ { 0x3636 , 0x06 , 0 , 0 } , -+ { 0x3620 , 0x64 , 0 , 0 } , -+ { 0x3621 , 0xe0 , 0 , 0 } , -+ { 0x3600 , 0x37 , 0 , 0 } , -+ { 0x3704 , 0xa0 , 0 , 0 } , -+ { 0x3703 , 0x5a , 0 , 0 } , -+ { 0x3715 , 0x78 , 0 , 0 } , -+ { 0x3717 , 0x01 , 0 , 0 } , -+ { 0x3731 , 0x02 , 0 , 0 } , -+ { 0x370b , 0x60 , 0 , 0 } , -+ { 0x3705 , 0x1a , 0 , 0 } , -+ { 0x3f05 , 0x02 , 0 , 0 } , -+ { 0x3f06 , 0x10 , 0 , 0 } , -+ { 0x3f01 , 0x0a , 0 , 0 } , -+ { 0x3a08 , 0x01 , 0 , 0 } , -+ { 0x3a09 , 0x27 , 0 , 0 } , -+ { 0x3a0a , 0x00 , 0 , 0 } , -+ { 0x3a0b , 0xf6 , 0 , 0 } , -+ { 0x3a0d , 0x04 , 0 , 0 } , -+ { 0x3a0e , 0x03 , 0 , 0 } , -+ { 0x3a0f , 0x58 , 0 , 0 } , -+ { 0x3a10 , 0x50 , 0 , 0 } , -+ { 0x3a1b , 0x58 , 0 , 0 } , -+ { 0x3a1e , 0x50 , 0 , 0 } , -+ { 0x3a11 , 0x60 , 0 , 0 } , -+ { 0x3a1f , 0x28 , 0 , 300 } , -+ { 0x4001 , 0x02 , 0 , 0 } , -+ { 0x4004 , 0x02 , 0 , 0 } , -+ { 0x4000 , 0x09 , 0 , 0 } , -+ { 0x4837 , 0x24 , 0 , 0 } , -+ { 0x4050 , 0x6e , 0 , 0 } , -+ { 0x4051 , 0x8f , 0 , 0 } , -+ { 0x0100 , 0x01 , 0 , 0 } , -+#if 0 -+ { 0x503d , 0xc0 , 0 , 0 } , /* test pattern */ -+ { 0x503e , 0x11 , 0 , 0 } , /* test pattern */ -+#endif -+ { 0x5000 , 0x86 , 0 , 0 } , /* enable LENC registers */ -+ { 0x5800 , 0x00 , 0 , 0 } , -+ { 0x5801 , 0x00 , 0 , 0 } , -+ { 0x5802 , 0x00 , 0 , 0 } , -+ { 0x5803 , 0x00 , 0 , 0 } , -+ { 0x5804 , 0x00 , 0 , 0 } , -+ { 0x5805 , 0x00 , 0 , 0 } , -+ { 0x5806 , 0x00 , 0 , 0 } , -+ { 0x5807 , 0x00 , 0 , 0 } , -+ { 0x5808 , 0x00 , 0 , 0 } , -+ { 0x5809 , 0x00 , 0 , 0 } , -+ { 0x580a , 0x00 , 0 , 0 } , -+ { 0x580b , 0x00 , 0 , 0 } , -+ { 0x580c , 0x00 , 0 , 0 } , -+ { 0x580d , 0x00 , 0 , 0 } , -+ { 0x580e , 0x00 , 0 , 0 } , -+ { 0x580f , 0x00 , 0 , 0 } , -+ { 0x5810 , 0x00 , 0 , 0 } , -+ { 0x5811 , 0x00 , 0 , 0 } , -+ { 0x5812 , 0x00 , 0 , 0 } , -+ { 0x5813 , 0x00 , 0 , 0 } , -+ { 0x5814 , 0x00 , 0 , 0 } , -+ { 0x5815 , 0x00 , 0 , 0 } , -+ { 0x5816 , 0x00 , 0 , 0 } , -+ { 0x5817 , 0x00 , 0 , 0 } , -+ { 0x5818 , 0x00 , 0 , 0 } , -+ { 0x5819 , 0x00 , 0 , 0 } , -+ { 0x581a , 0x00 , 0 , 0 } , -+ { 0x581b , 0x00 , 0 , 0 } , -+ { 0x581c , 0x00 , 0 , 0 } , -+ { 0x581d , 0x00 , 0 , 0 } , -+ { 0x581e , 0x00 , 0 , 0 } , -+ { 0x581f , 0x00 , 0 , 0 } , -+ { 0x5820 , 0x00 , 0 , 0 } , -+ { 0x5821 , 0x00 , 0 , 0 } , -+ { 0x5822 , 0x00 , 0 , 0 } , -+ { 0x5823 , 0x00 , 0 , 0 } , -+ { 0x5824 , 0xfe , 0 , 0 } , -+ { 0x5825 , 0xfe , 0 , 0 } , -+ { 0x5826 , 0xfe , 0 , 0 } , -+ { 0x5827 , 0xfe , 0 , 0 } , -+ { 0x5828 , 0xfe , 0 , 0 } , -+ { 0x5829 , 0xfe , 0 , 0 } , -+ { 0x582a , 0xed , 0 , 0 } , -+ { 0x582b , 0xed , 0 , 0 } , -+ { 0x582c , 0xed , 0 , 0 } , -+ { 0x582d , 0xfe , 0 , 0 } , -+ { 0x582e , 0xfe , 0 , 0 } , -+ { 0x582f , 0xed , 0 , 0 } , -+ { 0x5830 , 0xdc , 0 , 0 } , -+ { 0x5831 , 0xed , 0 , 0 } , -+ { 0x5832 , 0xfe , 0 , 0 } , -+ { 0x5833 , 0xfe , 0 , 0 } , -+ { 0x5834 , 0xed , 0 , 0 } , -+ { 0x5835 , 0xed , 0 , 0 } , -+ { 0x5836 , 0xed , 0 , 0 } , -+ { 0x5837 , 0xfe , 0 , 0 } , -+ { 0x5838 , 0xfe , 0 , 0 } , -+ { 0x5839 , 0xfe , 0 , 0 } , -+ { 0x583a , 0xfe , 0 , 0 } , -+ { 0x583b , 0xfe , 0 , 0 } , -+ { 0x583c , 0xfe , 0 , 0 } , -+ { 0x583d , 0xce , 0 , 0 } , -+ { 0x3501 , 0x10 , 0 , 0 } , -+ { 0x3502 , 0x80 , 0 , 0 } , -+ { 0x350a , 0x00 , 0 , 0 } , -+ { 0x350b , 0x7f , 0 , 0 } , -+ { 0x3c00 , 0x04 , 0 , 300 } , -+ { 0x3002 , 0xe4 , 0x01, 0 } , /* enable all outputs */ -+}; -+ -+static struct reg_value ov5647_setting_15fps_XGA_1024_768[] = { -+ { 0x0100 , 0x00 , 0 , 0 } , -+ { 0x0103 , 0x01 , 0 , 0 } , -+ { 0x3034 , 0x18 , 0 , 0 } , /* was 0x1A */ -+ { 0x3035 , 0x41 , 0 , 0 } , -+ { 0x3036 , 0x52 , 0 , 0 } , -+ { 0x303c , 0x11 , 0 , 0 } , -+ { 0x3106 , 0xf5 , 0 , 0 } , -+ { 0x3821 , 0x07 , 0 , 0 } , -+ { 0x3820 , 0x41 , 0 , 0 } , -+ { 0x3827 , 0xec , 0 , 0 } , -+ { 0x370c , 0x03 , 0 , 0 } , -+ { 0x3612 , 0x4b , 0 , 0 } , -+ { 0x3618 , 0x00 , 0 , 0 } , -+ { 0x5001 , 0x01 , 0 , 0 } , -+ { 0x5002 , 0x40 , 0 , 0 } , -+ { 0x5003 , 0x08 , 0 , 0 } , -+ { 0x5a00 , 0x08 , 0 , 0 } , -+ { 0x3000 , 0x00 , 0 , 0 } , -+ { 0x3001 , 0x00 , 0 , 0 } , -+ { 0x3002 , 0x00 , 0 , 0 } , -+ { 0x3016 , 0x08 , 0 , 0 } , -+ { 0x3017 , 0xe0 , 0 , 0 } , -+ { 0x3018 , 0x44 , 0 , 0 } , -+ { 0x301c , 0xf8 , 0 , 0 } , -+ { 0x301d , 0xf0 , 0 , 0 } , -+ { 0x3a18 , 0x00 , 0 , 0 } , -+ { 0x3a19 , 0xf8 , 0 , 0 } , -+ { 0x3c01 , 0x80 , 0 , 0 } , -+ { 0x3b07 , 0x0c , 0 , 0 } , -+ { 0x380c , 0x07 , 0 , 0 } , -+ { 0x380d , 0x68 , 0 , 0 } , -+ { 0x380e , 0x03 , 0 , 0 } , -+ { 0x380f , 0xd8 , 0 , 0 } , -+ { 0x3814 , 0x31 , 0 , 0 } , -+ { 0x3815 , 0x31 , 0 , 0 } , -+ { 0x3708 , 0x64 , 0 , 0 } , -+ { 0x3709 , 0x52 , 0 , 0 } , -+ { 0x3808 , 0x04 , 0 , 0 } , -+ { 0x3809 , 0x00 , 0 , 0 } , -+ { 0x380a , 0x03 , 0 , 0 } , -+ { 0x380b , 0x00 , 0 , 0 } , -+ { 0x3800 , 0x00 , 0 , 0 } , -+ { 0x3801 , 0x00 , 0 , 0 } , -+ { 0x3802 , 0x00 , 0 , 0 } , -+ { 0x3803 , 0x00 , 0 , 0 } , -+ { 0x3804 , 0x0a , 0 , 0 } , -+ { 0x3805 , 0x3f , 0 , 0 } , -+ { 0x3806 , 0x07 , 0 , 0 } , -+ { 0x3807 , 0xa1 , 0 , 0 } , -+ { 0x3811 , 0x08 , 0 , 0 } , -+ { 0x3813 , 0x02 , 0 , 0 } , -+ { 0x3630 , 0x2e , 0 , 0 } , -+ { 0x3632 , 0xe2 , 0 , 0 } , -+ { 0x3633 , 0x23 , 0 , 0 } , -+ { 0x3634 , 0x44 , 0 , 0 } , -+ { 0x3636 , 0x06 , 0 , 0 } , -+ { 0x3620 , 0x64 , 0 , 0 } , -+ { 0x3621 , 0xe0 , 0 , 0 } , -+ { 0x3600 , 0x37 , 0 , 0 } , -+ { 0x3704 , 0xa0 , 0 , 0 } , -+ { 0x3703 , 0x5a , 0 , 0 } , -+ { 0x3715 , 0x78 , 0 , 0 } , -+ { 0x3717 , 0x01 , 0 , 0 } , -+ { 0x3731 , 0x02 , 0 , 0 } , -+ { 0x370b , 0x60 , 0 , 0 } , -+ { 0x3705 , 0x1a , 0 , 0 } , -+ { 0x3f05 , 0x02 , 0 , 0 } , -+ { 0x3f06 , 0x10 , 0 , 0 } , -+ { 0x3f01 , 0x0a , 0 , 0 } , -+ { 0x3a08 , 0x01 , 0 , 0 } , -+ { 0x3a09 , 0x27 , 0 , 0 } , -+ { 0x3a0a , 0x00 , 0 , 0 } , -+ { 0x3a0b , 0xf6 , 0 , 0 } , -+ { 0x3a0d , 0x04 , 0 , 0 } , -+ { 0x3a0e , 0x03 , 0 , 0 } , -+ { 0x3a0f , 0x58 , 0 , 0 } , -+ { 0x3a10 , 0x50 , 0 , 0 } , -+ { 0x3a1b , 0x58 , 0 , 0 } , -+ { 0x3a1e , 0x50 , 0 , 0 } , -+ { 0x3a11 , 0x60 , 0 , 0 } , -+ { 0x3a1f , 0x28 , 0 , 300 } , -+ { 0x4001 , 0x02 , 0 , 0 } , -+ { 0x4004 , 0x02 , 0 , 0 } , -+ { 0x4000 , 0x09 , 0 , 0 } , -+ { 0x4837 , 0x24 , 0 , 0 } , -+ { 0x4050 , 0x6e , 0 , 0 } , -+ { 0x4051 , 0x8f , 0 , 0 } , -+ { 0x0100 , 0x01 , 0 , 0 } , -+#if 0 -+ { 0x503d , 0xc0 , 0 , 0 } , /* test pattern */ -+ { 0x503e , 0x11 , 0 , 0 } , /* test pattern */ -+#endif -+ { 0x5000 , 0x86 , 0 , 0 } , /* enable LENC registers */ -+ { 0x5800 , 0x00 , 0 , 0 } , -+ { 0x5801 , 0x00 , 0 , 0 } , -+ { 0x5802 , 0x00 , 0 , 0 } , -+ { 0x5803 , 0x00 , 0 , 0 } , -+ { 0x5804 , 0x00 , 0 , 0 } , -+ { 0x5805 , 0x00 , 0 , 0 } , -+ { 0x5806 , 0x00 , 0 , 0 } , -+ { 0x5807 , 0x00 , 0 , 0 } , -+ { 0x5808 , 0x00 , 0 , 0 } , -+ { 0x5809 , 0x00 , 0 , 0 } , -+ { 0x580a , 0x00 , 0 , 0 } , -+ { 0x580b , 0x00 , 0 , 0 } , -+ { 0x580c , 0x00 , 0 , 0 } , -+ { 0x580d , 0x00 , 0 , 0 } , -+ { 0x580e , 0x00 , 0 , 0 } , -+ { 0x580f , 0x00 , 0 , 0 } , -+ { 0x5810 , 0x00 , 0 , 0 } , -+ { 0x5811 , 0x00 , 0 , 0 } , -+ { 0x5812 , 0x00 , 0 , 0 } , -+ { 0x5813 , 0x00 , 0 , 0 } , -+ { 0x5814 , 0x00 , 0 , 0 } , -+ { 0x5815 , 0x00 , 0 , 0 } , -+ { 0x5816 , 0x00 , 0 , 0 } , -+ { 0x5817 , 0x00 , 0 , 0 } , -+ { 0x5818 , 0x00 , 0 , 0 } , -+ { 0x5819 , 0x00 , 0 , 0 } , -+ { 0x581a , 0x00 , 0 , 0 } , -+ { 0x581b , 0x00 , 0 , 0 } , -+ { 0x581c , 0x00 , 0 , 0 } , -+ { 0x581d , 0x00 , 0 , 0 } , -+ { 0x581e , 0x00 , 0 , 0 } , -+ { 0x581f , 0x00 , 0 , 0 } , -+ { 0x5820 , 0x00 , 0 , 0 } , -+ { 0x5821 , 0x00 , 0 , 0 } , -+ { 0x5822 , 0x00 , 0 , 0 } , -+ { 0x5823 , 0x00 , 0 , 0 } , -+ { 0x5824 , 0xfe , 0 , 0 } , -+ { 0x5825 , 0xfe , 0 , 0 } , -+ { 0x5826 , 0xfe , 0 , 0 } , -+ { 0x5827 , 0xfe , 0 , 0 } , -+ { 0x5828 , 0xfe , 0 , 0 } , -+ { 0x5829 , 0xfe , 0 , 0 } , -+ { 0x582a , 0xed , 0 , 0 } , -+ { 0x582b , 0xed , 0 , 0 } , -+ { 0x582c , 0xed , 0 , 0 } , -+ { 0x582d , 0xfe , 0 , 0 } , -+ { 0x582e , 0xfe , 0 , 0 } , -+ { 0x582f , 0xed , 0 , 0 } , -+ { 0x5830 , 0xdc , 0 , 0 } , -+ { 0x5831 , 0xed , 0 , 0 } , -+ { 0x5832 , 0xfe , 0 , 0 } , -+ { 0x5833 , 0xfe , 0 , 0 } , -+ { 0x5834 , 0xed , 0 , 0 } , -+ { 0x5835 , 0xed , 0 , 0 } , -+ { 0x5836 , 0xed , 0 , 0 } , -+ { 0x5837 , 0xfe , 0 , 0 } , -+ { 0x5838 , 0xfe , 0 , 0 } , -+ { 0x5839 , 0xfe , 0 , 0 } , -+ { 0x583a , 0xfe , 0 , 0 } , -+ { 0x583b , 0xfe , 0 , 0 } , -+ { 0x583c , 0xfe , 0 , 0 } , -+ { 0x583d , 0xce , 0 , 0 } , -+ { 0x3501 , 0x10 , 0 , 0 } , -+ { 0x3502 , 0x80 , 0 , 0 } , -+ { 0x350a , 0x00 , 0 , 0 } , -+ { 0x350b , 0x7f , 0 , 0 } , -+ { 0x3c00 , 0x04 , 0 , 300 } , -+ { 0x3002 , 0xe4 , 0x01, 0 } , /* enable all outputs */ -+}; -+ -+static struct reg_value ov5647_setting_30fps_960_720[] = { -+ { 0x0100 , 0x00 , 0 , 0 } , -+ { 0x0103 , 0x01 , 0 , 0 } , -+ { 0x3034 , 0x18 , 0 , 0 } , /* was 0x1A */ -+ { 0x3035 , 0x41 , 0 , 0 } , -+ { 0x3036 , 0xa0 , 0 , 0 } , -+ { 0x303c , 0x11 , 0 , 0 } , -+ { 0x3106 , 0xf5 , 0 , 0 } , -+ { 0x3821 , 0x07 , 0 , 0 } , -+ { 0x3820 , 0x41 , 0 , 0 } , -+ { 0x3827 , 0xec , 0 , 0 } , -+ { 0x370c , 0x03 , 0 , 0 } , -+ { 0x3612 , 0x4b , 0 , 0 } , -+ { 0x3618 , 0x00 , 0 , 0 } , -+ { 0x5001 , 0x01 , 0 , 0 } , -+ { 0x5002 , 0x40 , 0 , 0 } , -+ { 0x5003 , 0x08 , 0 , 0 } , -+ { 0x5a00 , 0x08 , 0 , 0 } , -+ { 0x3000 , 0x00 , 0 , 0 } , -+ { 0x3001 , 0x00 , 0 , 0 } , -+ { 0x3002 , 0x00 , 0 , 0 } , -+ { 0x3016 , 0x08 , 0 , 0 } , -+ { 0x3017 , 0xe0 , 0 , 0 } , -+ { 0x3018 , 0x44 , 0 , 0 } , -+ { 0x301c , 0xf8 , 0 , 0 } , -+ { 0x301d , 0xf0 , 0 , 0 } , -+ { 0x3a18 , 0x00 , 0 , 0 } , -+ { 0x3a19 , 0xf8 , 0 , 0 } , -+ { 0x3c01 , 0x80 , 0 , 0 } , -+ { 0x3b07 , 0x0c , 0 , 0 } , -+ { 0x380c , 0x06 , 0 , 0 } , -+ { 0x380d , 0xd6 , 0 , 0 } , -+ { 0x380e , 0x03 , 0 , 0 } , -+ { 0x380f , 0xd8 , 0 , 0 } , -+ { 0x3814 , 0x31 , 0 , 0 } , -+ { 0x3815 , 0x31 , 0 , 0 } , -+ { 0x3708 , 0x64 , 0 , 0 } , -+ { 0x3709 , 0x52 , 0 , 0 } , -+ { 0x3808 , 0x03 , 0 , 0 } , -+ { 0x3809 , 0xc0 , 0 , 0 } , -+ { 0x380a , 0x02 , 0 , 0 } , -+ { 0x380b , 0xd0 , 0 , 0 } , -+ { 0x3800 , 0x00 , 0 , 0 } , -+ { 0x3801 , 0x00 , 0 , 0 } , -+ { 0x3802 , 0x00 , 0 , 0 } , -+ { 0x3803 , 0x00 , 0 , 0 } , -+ { 0x3804 , 0x0a , 0 , 0 } , -+ { 0x3805 , 0x3f , 0 , 0 } , -+ { 0x3806 , 0x06 , 0 , 0 } , -+ { 0x3807 , 0xb2 , 0 , 0 } , -+ { 0x3811 , 0x08 , 0 , 0 } , -+ { 0x3813 , 0x02 , 0 , 0 } , -+ { 0x3630 , 0x2e , 0 , 0 } , -+ { 0x3632 , 0xe2 , 0 , 0 } , -+ { 0x3633 , 0x23 , 0 , 0 } , -+ { 0x3634 , 0x44 , 0 , 0 } , -+ { 0x3636 , 0x06 , 0 , 0 } , -+ { 0x3620 , 0x64 , 0 , 0 } , -+ { 0x3621 , 0xe0 , 0 , 0 } , -+ { 0x3600 , 0x37 , 0 , 0 } , -+ { 0x3704 , 0xa0 , 0 , 0 } , -+ { 0x3703 , 0x5a , 0 , 0 } , -+ { 0x3715 , 0x78 , 0 , 0 } , -+ { 0x3717 , 0x01 , 0 , 0 } , -+ { 0x3731 , 0x02 , 0 , 0 } , -+ { 0x370b , 0x60 , 0 , 0 } , -+ { 0x3705 , 0x1a , 0 , 0 } , -+ { 0x3f05 , 0x02 , 0 , 0 } , -+ { 0x3f06 , 0x10 , 0 , 0 } , -+ { 0x3f01 , 0x0a , 0 , 0 } , -+ { 0x3a08 , 0x01 , 0 , 0 } , -+ { 0x3a09 , 0x27 , 0 , 0 } , -+ { 0x3a0a , 0x00 , 0 , 0 } , -+ { 0x3a0b , 0xf6 , 0 , 0 } , -+ { 0x3a0d , 0x04 , 0 , 0 } , -+ { 0x3a0e , 0x03 , 0 , 0 } , -+ { 0x3a0f , 0x58 , 0 , 0 } , -+ { 0x3a10 , 0x50 , 0 , 0 } , -+ { 0x3a1b , 0x58 , 0 , 0 } , -+ { 0x3a1e , 0x50 , 0 , 0 } , -+ { 0x3a11 , 0x60 , 0 , 0 } , -+ { 0x3a1f , 0x28 , 0 , 300 } , -+ { 0x4001 , 0x02 , 0 , 0 } , -+ { 0x4004 , 0x02 , 0 , 0 } , -+ { 0x4000 , 0x09 , 0 , 0 } , -+ { 0x4837 , 0x24 , 0 , 0 } , -+ { 0x4050 , 0x6e , 0 , 0 } , -+ { 0x4051 , 0x8f , 0 , 0 } , -+ { 0x0100 , 0x01 , 0 , 0 } , -+#if 0 -+ { 0x503d , 0xc0 , 0 , 0 } , /* test pattern */ -+ { 0x503e , 0x11 , 0 , 0 } , /* test pattern */ -+#endif -+ { 0x5000 , 0x86 , 0 , 0 } , /* enable LENC registers */ -+ { 0x5800 , 0x00 , 0 , 0 } , -+ { 0x5801 , 0x00 , 0 , 0 } , -+ { 0x5802 , 0x00 , 0 , 0 } , -+ { 0x5803 , 0x00 , 0 , 0 } , -+ { 0x5804 , 0x00 , 0 , 0 } , -+ { 0x5805 , 0x00 , 0 , 0 } , -+ { 0x5806 , 0x00 , 0 , 0 } , -+ { 0x5807 , 0x00 , 0 , 0 } , -+ { 0x5808 , 0x00 , 0 , 0 } , -+ { 0x5809 , 0x00 , 0 , 0 } , -+ { 0x580a , 0x00 , 0 , 0 } , -+ { 0x580b , 0x00 , 0 , 0 } , -+ { 0x580c , 0x00 , 0 , 0 } , -+ { 0x580d , 0x00 , 0 , 0 } , -+ { 0x580e , 0x00 , 0 , 0 } , -+ { 0x580f , 0x00 , 0 , 0 } , -+ { 0x5810 , 0x00 , 0 , 0 } , -+ { 0x5811 , 0x00 , 0 , 0 } , -+ { 0x5812 , 0x00 , 0 , 0 } , -+ { 0x5813 , 0x00 , 0 , 0 } , -+ { 0x5814 , 0x00 , 0 , 0 } , -+ { 0x5815 , 0x00 , 0 , 0 } , -+ { 0x5816 , 0x00 , 0 , 0 } , -+ { 0x5817 , 0x00 , 0 , 0 } , -+ { 0x5818 , 0x00 , 0 , 0 } , -+ { 0x5819 , 0x00 , 0 , 0 } , -+ { 0x581a , 0x00 , 0 , 0 } , -+ { 0x581b , 0x00 , 0 , 0 } , -+ { 0x581c , 0x00 , 0 , 0 } , -+ { 0x581d , 0x00 , 0 , 0 } , -+ { 0x581e , 0x00 , 0 , 0 } , -+ { 0x581f , 0x00 , 0 , 0 } , -+ { 0x5820 , 0x00 , 0 , 0 } , -+ { 0x5821 , 0x00 , 0 , 0 } , -+ { 0x5822 , 0x00 , 0 , 0 } , -+ { 0x5823 , 0x00 , 0 , 0 } , -+ { 0x5824 , 0xfe , 0 , 0 } , -+ { 0x5825 , 0xfe , 0 , 0 } , -+ { 0x5826 , 0xfe , 0 , 0 } , -+ { 0x5827 , 0xfe , 0 , 0 } , -+ { 0x5828 , 0xfe , 0 , 0 } , -+ { 0x5829 , 0xfe , 0 , 0 } , -+ { 0x582a , 0xed , 0 , 0 } , -+ { 0x582b , 0xed , 0 , 0 } , -+ { 0x582c , 0xed , 0 , 0 } , -+ { 0x582d , 0xfe , 0 , 0 } , -+ { 0x582e , 0xfe , 0 , 0 } , -+ { 0x582f , 0xed , 0 , 0 } , -+ { 0x5830 , 0xdc , 0 , 0 } , -+ { 0x5831 , 0xed , 0 , 0 } , -+ { 0x5832 , 0xfe , 0 , 0 } , -+ { 0x5833 , 0xfe , 0 , 0 } , -+ { 0x5834 , 0xed , 0 , 0 } , -+ { 0x5835 , 0xed , 0 , 0 } , -+ { 0x5836 , 0xed , 0 , 0 } , -+ { 0x5837 , 0xfe , 0 , 0 } , -+ { 0x5838 , 0xfe , 0 , 0 } , -+ { 0x5839 , 0xfe , 0 , 0 } , -+ { 0x583a , 0xfe , 0 , 0 } , -+ { 0x583b , 0xfe , 0 , 0 } , -+ { 0x583c , 0xfe , 0 , 0 } , -+ { 0x583d , 0xce , 0 , 0 } , -+ { 0x3501 , 0x10 , 0 , 0 } , -+ { 0x3502 , 0x80 , 0 , 0 } , -+ { 0x350a , 0x00 , 0 , 0 } , -+ { 0x350b , 0x7f , 0 , 0 } , -+ { 0x3c00 , 0x04 , 0 , 300 } , -+ { 0x3002 , 0xe4 , 0x01, 0 } , /* enable all outputs */ -+}; -+ -+static struct reg_value ov5647_setting_15fps_960_720[] = { -+ { 0x0100 , 0x00 , 0 , 0 } , -+ { 0x0103 , 0x01 , 0 , 0 } , -+ { 0x3034 , 0x18 , 0 , 0 } , /* was 0x1A */ -+ { 0x3035 , 0x41 , 0 , 0 } , -+ { 0x3036 , 0x49 , 0 , 0 } , -+ { 0x303c , 0x11 , 0 , 0 } , -+ { 0x3106 , 0xf5 , 0 , 0 } , -+ { 0x3821 , 0x07 , 0 , 0 } , -+ { 0x3820 , 0x41 , 0 , 0 } , -+ { 0x3827 , 0xec , 0 , 0 } , -+ { 0x370c , 0x03 , 0 , 0 } , -+ { 0x3612 , 0x4b , 0 , 0 } , -+ { 0x3618 , 0x00 , 0 , 0 } , -+ { 0x5001 , 0x01 , 0 , 0 } , -+ { 0x5002 , 0x40 , 0 , 0 } , -+ { 0x5003 , 0x08 , 0 , 0 } , -+ { 0x5a00 , 0x08 , 0 , 0 } , -+ { 0x3000 , 0x00 , 0 , 0 } , -+ { 0x3001 , 0x00 , 0 , 0 } , -+ { 0x3002 , 0x00 , 0 , 0 } , -+ { 0x3016 , 0x08 , 0 , 0 } , -+ { 0x3017 , 0xe0 , 0 , 0 } , -+ { 0x3018 , 0x44 , 0 , 0 } , -+ { 0x301c , 0xf8 , 0 , 0 } , -+ { 0x301d , 0xf0 , 0 , 0 } , -+ { 0x3a18 , 0x00 , 0 , 0 } , -+ { 0x3a19 , 0xf8 , 0 , 0 } , -+ { 0x3c01 , 0x80 , 0 , 0 } , -+ { 0x3b07 , 0x0c , 0 , 0 } , -+ { 0x380c , 0x06 , 0 , 0 } , -+ { 0x380d , 0xd6 , 0 , 0 } , -+ { 0x380e , 0x03 , 0 , 0 } , -+ { 0x380f , 0xd8 , 0 , 0 } , -+ { 0x3814 , 0x31 , 0 , 0 } , -+ { 0x3815 , 0x31 , 0 , 0 } , -+ { 0x3708 , 0x64 , 0 , 0 } , -+ { 0x3709 , 0x52 , 0 , 0 } , -+ { 0x3808 , 0x03 , 0 , 0 } , -+ { 0x3809 , 0xc0 , 0 , 0 } , -+ { 0x380a , 0x02 , 0 , 0 } , -+ { 0x380b , 0xd0 , 0 , 0 } , -+ { 0x3800 , 0x00 , 0 , 0 } , -+ { 0x3801 , 0x00 , 0 , 0 } , -+ { 0x3802 , 0x00 , 0 , 0 } , -+ { 0x3803 , 0x00 , 0 , 0 } , -+ { 0x3804 , 0x0a , 0 , 0 } , -+ { 0x3805 , 0x3f , 0 , 0 } , -+ { 0x3806 , 0x06 , 0 , 0 } , -+ { 0x3807 , 0xb2 , 0 , 0 } , -+ { 0x3811 , 0x08 , 0 , 0 } , -+ { 0x3813 , 0x02 , 0 , 0 } , -+ { 0x3630 , 0x2e , 0 , 0 } , -+ { 0x3632 , 0xe2 , 0 , 0 } , -+ { 0x3633 , 0x23 , 0 , 0 } , -+ { 0x3634 , 0x44 , 0 , 0 } , -+ { 0x3636 , 0x06 , 0 , 0 } , -+ { 0x3620 , 0x64 , 0 , 0 } , -+ { 0x3621 , 0xe0 , 0 , 0 } , -+ { 0x3600 , 0x37 , 0 , 0 } , -+ { 0x3704 , 0xa0 , 0 , 0 } , -+ { 0x3703 , 0x5a , 0 , 0 } , -+ { 0x3715 , 0x78 , 0 , 0 } , -+ { 0x3717 , 0x01 , 0 , 0 } , -+ { 0x3731 , 0x02 , 0 , 0 } , -+ { 0x370b , 0x60 , 0 , 0 } , -+ { 0x3705 , 0x1a , 0 , 0 } , -+ { 0x3f05 , 0x02 , 0 , 0 } , -+ { 0x3f06 , 0x10 , 0 , 0 } , -+ { 0x3f01 , 0x0a , 0 , 0 } , -+ { 0x3a08 , 0x01 , 0 , 0 } , -+ { 0x3a09 , 0x27 , 0 , 0 } , -+ { 0x3a0a , 0x00 , 0 , 0 } , -+ { 0x3a0b , 0xf6 , 0 , 0 } , -+ { 0x3a0d , 0x04 , 0 , 0 } , -+ { 0x3a0e , 0x03 , 0 , 0 } , -+ { 0x3a0f , 0x58 , 0 , 0 } , -+ { 0x3a10 , 0x50 , 0 , 0 } , -+ { 0x3a1b , 0x58 , 0 , 0 } , -+ { 0x3a1e , 0x50 , 0 , 0 } , -+ { 0x3a11 , 0x60 , 0 , 0 } , -+ { 0x3a1f , 0x28 , 0 , 300 } , -+ { 0x4001 , 0x02 , 0 , 0 } , -+ { 0x4004 , 0x02 , 0 , 0 } , -+ { 0x4000 , 0x09 , 0 , 0 } , -+ { 0x4837 , 0x24 , 0 , 0 } , -+ { 0x4050 , 0x6e , 0 , 0 } , -+ { 0x4051 , 0x8f , 0 , 0 } , -+ { 0x0100 , 0x01 , 0 , 0 } , -+#if 0 -+ { 0x503d , 0xc0 , 0 , 0 } , /* test pattern */ -+ { 0x503e , 0x11 , 0 , 0 } , /* test pattern */ -+#endif -+ { 0x5000 , 0x86 , 0 , 0 } , /* enable LENC registers */ -+ { 0x5800 , 0x00 , 0 , 0 } , -+ { 0x5801 , 0x00 , 0 , 0 } , -+ { 0x5802 , 0x00 , 0 , 0 } , -+ { 0x5803 , 0x00 , 0 , 0 } , -+ { 0x5804 , 0x00 , 0 , 0 } , -+ { 0x5805 , 0x00 , 0 , 0 } , -+ { 0x5806 , 0x00 , 0 , 0 } , -+ { 0x5807 , 0x00 , 0 , 0 } , -+ { 0x5808 , 0x00 , 0 , 0 } , -+ { 0x5809 , 0x00 , 0 , 0 } , -+ { 0x580a , 0x00 , 0 , 0 } , -+ { 0x580b , 0x00 , 0 , 0 } , -+ { 0x580c , 0x00 , 0 , 0 } , -+ { 0x580d , 0x00 , 0 , 0 } , -+ { 0x580e , 0x00 , 0 , 0 } , -+ { 0x580f , 0x00 , 0 , 0 } , -+ { 0x5810 , 0x00 , 0 , 0 } , -+ { 0x5811 , 0x00 , 0 , 0 } , -+ { 0x5812 , 0x00 , 0 , 0 } , -+ { 0x5813 , 0x00 , 0 , 0 } , -+ { 0x5814 , 0x00 , 0 , 0 } , -+ { 0x5815 , 0x00 , 0 , 0 } , -+ { 0x5816 , 0x00 , 0 , 0 } , -+ { 0x5817 , 0x00 , 0 , 0 } , -+ { 0x5818 , 0x00 , 0 , 0 } , -+ { 0x5819 , 0x00 , 0 , 0 } , -+ { 0x581a , 0x00 , 0 , 0 } , -+ { 0x581b , 0x00 , 0 , 0 } , -+ { 0x581c , 0x00 , 0 , 0 } , -+ { 0x581d , 0x00 , 0 , 0 } , -+ { 0x581e , 0x00 , 0 , 0 } , -+ { 0x581f , 0x00 , 0 , 0 } , -+ { 0x5820 , 0x00 , 0 , 0 } , -+ { 0x5821 , 0x00 , 0 , 0 } , -+ { 0x5822 , 0x00 , 0 , 0 } , -+ { 0x5823 , 0x00 , 0 , 0 } , -+ { 0x5824 , 0xfe , 0 , 0 } , -+ { 0x5825 , 0xfe , 0 , 0 } , -+ { 0x5826 , 0xfe , 0 , 0 } , -+ { 0x5827 , 0xfe , 0 , 0 } , -+ { 0x5828 , 0xfe , 0 , 0 } , -+ { 0x5829 , 0xfe , 0 , 0 } , -+ { 0x582a , 0xed , 0 , 0 } , -+ { 0x582b , 0xed , 0 , 0 } , -+ { 0x582c , 0xed , 0 , 0 } , -+ { 0x582d , 0xfe , 0 , 0 } , -+ { 0x582e , 0xfe , 0 , 0 } , -+ { 0x582f , 0xed , 0 , 0 } , -+ { 0x5830 , 0xdc , 0 , 0 } , -+ { 0x5831 , 0xed , 0 , 0 } , -+ { 0x5832 , 0xfe , 0 , 0 } , -+ { 0x5833 , 0xfe , 0 , 0 } , -+ { 0x5834 , 0xed , 0 , 0 } , -+ { 0x5835 , 0xed , 0 , 0 } , -+ { 0x5836 , 0xed , 0 , 0 } , -+ { 0x5837 , 0xfe , 0 , 0 } , -+ { 0x5838 , 0xfe , 0 , 0 } , -+ { 0x5839 , 0xfe , 0 , 0 } , -+ { 0x583a , 0xfe , 0 , 0 } , -+ { 0x583b , 0xfe , 0 , 0 } , -+ { 0x583c , 0xfe , 0 , 0 } , -+ { 0x583d , 0xce , 0 , 0 } , -+ { 0x3501 , 0x10 , 0 , 0 } , -+ { 0x3502 , 0x80 , 0 , 0 } , -+ { 0x350a , 0x00 , 0 , 0 } , -+ { 0x350b , 0x7f , 0 , 0 } , -+ { 0x3c00 , 0x04 , 0 , 300 } , -+ { 0x3002 , 0xe4 , 0x01, 0 } , /* enable all outputs */ -+}; -+ -+static struct ov5647_mode_info ov5647_mode_info_data[2][ov5647_mode_MAX + 1] = { -+ { -+ {ov5647_mode_960P_1280_960, SUBSAMPLING, 1280, 960, -+ ov5647_setting_15fps_960P_1280_960, -+ ARRAY_SIZE(ov5647_setting_15fps_960P_1280_960)}, -+ {ov5647_mode_720P_1280_720, SUBSAMPLING, 1280, 720, -+ ov5647_setting_15fps_720P_1280_720, -+ ARRAY_SIZE(ov5647_setting_15fps_720P_1280_720)}, -+ {ov5647_mode_1080P_1920_1080, SCALING, 1920, 1080, -+ ov5647_setting_15fps_1080P_1920_1080, -+ ARRAY_SIZE(ov5647_setting_15fps_1080P_1920_1080)}, -+ {ov5647_mode_VGA_640_480, SUBSAMPLING, 640, 480, -+ ov5647_setting_15fps_VGA_640_480, -+ ARRAY_SIZE(ov5647_setting_15fps_VGA_640_480) - 2}, -+ {ov5647_mode_XGA_1024_768, SUBSAMPLING, 1024, 768, -+ ov5647_setting_15fps_XGA_1024_768, -+ ARRAY_SIZE(ov5647_setting_15fps_XGA_1024_768)}, -+ {ov5647_mode_960_720, SUBSAMPLING, 960, 720, -+ ov5647_setting_15fps_960_720, -+ ARRAY_SIZE(ov5647_setting_15fps_960_720)}, -+ {ov5647_mode_VGA_640_480_narrow, SUBSAMPLING, 640, 480, -+ ov5647_setting_15fps_VGA_640_480, -+ ARRAY_SIZE(ov5647_setting_15fps_VGA_640_480)}, -+ }, -+ { -+ {ov5647_mode_960P_1280_960, SUBSAMPLING, 1280, 960, -+ ov5647_setting_30fps_960P_1280_960, -+ ARRAY_SIZE(ov5647_setting_30fps_960P_1280_960)}, -+ {ov5647_mode_720P_1280_720, SUBSAMPLING, 1280, 720, -+ ov5647_setting_30fps_720P_1280_720, -+ ARRAY_SIZE(ov5647_setting_30fps_720P_1280_720)}, -+ {ov5647_mode_1080P_1920_1080, SCALING, 1920, 1080, -+ ov5647_setting_30fps_1080P_1920_1080, -+ ARRAY_SIZE(ov5647_setting_30fps_1080P_1920_1080)}, -+ {ov5647_mode_VGA_640_480, SUBSAMPLING, 640, 480, -+ ov5647_setting_30fps_VGA_640_480, -+ ARRAY_SIZE(ov5647_setting_30fps_VGA_640_480) - 2}, -+ {ov5647_mode_XGA_1024_768, SUBSAMPLING, 1024, 768, -+ ov5647_setting_30fps_XGA_1024_768, -+ ARRAY_SIZE(ov5647_setting_30fps_XGA_1024_768)}, -+ {ov5647_mode_960_720, SUBSAMPLING, 960, 720, -+ ov5647_setting_30fps_960_720, -+ ARRAY_SIZE(ov5647_setting_15fps_960_720)}, -+ {ov5647_mode_VGA_640_480_narrow, SUBSAMPLING, 640, 480, -+ ov5647_setting_30fps_VGA_640_480, -+ ARRAY_SIZE(ov5647_setting_30fps_VGA_640_480)}, -+ }, -+}; -+ -+static struct regulator *io_regulator; -+static struct regulator *core_regulator; -+static struct regulator *analog_regulator; -+static struct regulator *gpo_regulator; -+ -+static int ov5647_probe(struct i2c_client *adapter, -+ const struct i2c_device_id *device_id); -+static int ov5647_remove(struct i2c_client *client); -+ -+static s32 ov5647_read_reg(u16 reg, u8 *val); -+static s32 ov5647_write_reg(u16 reg, u8 val); -+ -+static const struct i2c_device_id ov5647_id[] = { -+ {"ov5647_mipi", 0}, -+ {}, -+}; -+ -+MODULE_DEVICE_TABLE(i2c, ov5647_id); -+ -+static struct i2c_driver ov5647_i2c_driver = { -+ .driver = { -+ .owner = THIS_MODULE, -+ .name = "ov5647_mipi", -+ }, -+ .probe = ov5647_probe, -+ .remove = ov5647_remove, -+ .id_table = ov5647_id, -+}; -+ -+static void ov5647_standby(s32 enable) -+{ -+ if (!gpio_is_valid(pwn_gpio)) -+ return; -+ -+ if (enable) { -+ gpio_set_value(pwn_gpio, !powon_active); -+ if (gpio_is_valid(led_gpio)) -+ gpio_set_value(led_gpio, !led_active); -+ } -+ else { -+ gpio_set_value(pwn_gpio, powon_active); -+ if (gpio_is_valid(led_gpio)) -+ gpio_set_value(led_gpio, led_active); -+ } -+ -+ pr_debug("ov5647_mipi_camera_powerdown: powerdown=%x, power_gp=0x%x\n", enable, pwn_gpio); -+ msleep(2); -+} -+ -+static void ov5647_reset(void) -+{ -+ if (!gpio_is_valid(rst_gpio)) -+ return; -+ -+ /* camera reset */ -+ gpio_set_value(rst_gpio, !rst_active); -+ -+ /* camera power dowmn */ -+ if (gpio_is_valid(pwn_gpio)) { -+ gpio_set_value(pwn_gpio, !powon_active); -+ msleep(5); -+ -+ gpio_set_value(pwn_gpio, powon_active); -+ msleep(5); -+ } -+ -+ gpio_set_value(rst_gpio, rst_active); -+ msleep(1); -+ -+ gpio_set_value(rst_gpio, !rst_active); -+ msleep(5); -+ -+ if (gpio_is_valid(pwn_gpio)) -+ gpio_set_value(pwn_gpio, !powon_active); -+} -+ -+static int ov5647_power_on(struct device *dev) -+{ -+ int ret = 0; -+ -+ io_regulator = devm_regulator_get(dev, "DOVDD"); -+ if (!IS_ERR(io_regulator)) { -+ regulator_set_voltage(io_regulator, -+ OV5647_VOLTAGE_DIGITAL_IO, -+ OV5647_VOLTAGE_DIGITAL_IO); -+ ret = regulator_enable(io_regulator); -+ if (ret) { -+ pr_err("%s:io set voltage error\n", __func__); -+ return ret; -+ } else { -+ dev_dbg(dev, -+ "%s:io set voltage ok\n", __func__); -+ } -+ } else { -+ pr_err("%s: cannot get io voltage error\n", __func__); -+ io_regulator = NULL; -+ } -+ -+ core_regulator = devm_regulator_get(dev, "DVDD"); -+ if (!IS_ERR(core_regulator)) { -+ regulator_set_voltage(core_regulator, -+ OV5647_VOLTAGE_DIGITAL_CORE, -+ OV5647_VOLTAGE_DIGITAL_CORE); -+ ret = regulator_enable(core_regulator); -+ if (ret) { -+ pr_err("%s:core set voltage error\n", __func__); -+ return ret; -+ } else { -+ dev_dbg(dev, -+ "%s:core set voltage ok\n", __func__); -+ } -+ } else { -+ core_regulator = NULL; -+ pr_err("%s: cannot get core voltage error\n", __func__); -+ } -+ -+ analog_regulator = devm_regulator_get(dev, "AVDD"); -+ if (!IS_ERR(analog_regulator)) { -+ regulator_set_voltage(analog_regulator, -+ OV5647_VOLTAGE_ANALOG, -+ OV5647_VOLTAGE_ANALOG); -+ ret = regulator_enable(analog_regulator); -+ if (ret) { -+ pr_err("%s:analog set voltage error\n", -+ __func__); -+ return ret; -+ } else { -+ dev_dbg(dev, -+ "%s:analog set voltage ok\n", __func__); -+ } -+ } else { -+ analog_regulator = NULL; -+ pr_err("%s: cannot get analog voltage error\n", __func__); -+ } -+ -+ return ret; -+} -+ -+static s32 ov5647_write_reg(u16 reg, u8 val) -+{ -+ u8 au8Buf[3] = {0}; -+ -+ au8Buf[0] = reg >> 8; -+ au8Buf[1] = reg & 0xff; -+ au8Buf[2] = val; -+ -+ if (i2c_master_send(ov5647_data.i2c_client, au8Buf, 3) < 0) { -+ pr_err("%s:write reg error:reg=%x,val=%x\n", -+ __func__, reg, val); -+ return -1; -+ } -+ pr_debug("reg=%x,val=%x\n", reg, val); -+ return 0; -+} -+ -+static s32 ov5647_read_reg(u16 reg, u8 *val) -+{ -+ struct sensor_data *sensor = &ov5647_data; -+ struct i2c_client *client = sensor->i2c_client; -+ struct i2c_msg msgs[2]; -+ u8 buf[2]; -+ int ret; -+ -+ buf[0] = reg >> 8; -+ buf[1] = reg & 0xff; -+ msgs[0].addr = client->addr; -+ msgs[0].flags = 0; -+ msgs[0].len = 2; -+ msgs[0].buf = buf; -+ -+ msgs[1].addr = client->addr; -+ msgs[1].flags = I2C_M_RD; -+ msgs[1].len = 1; -+ msgs[1].buf = buf; -+ -+ ret = i2c_transfer(client->adapter, msgs, 2); -+ if (ret < 0) { -+ pr_err("%s(mipi):reg=%x ret=%d\n", __func__, reg, ret); -+ return ret; -+ } -+ *val = buf[0]; -+ pr_debug("%s(mipi):reg=%x,val=%x\n", __func__, reg, buf[0]); -+ return buf[0]; -+} -+ -+static int prev_sysclk, prev_HTS; -+static int AE_low, AE_high, AE_Target = 44; -+ -+void OV5647_stream_on(void) -+{ -+ ov5647_write_reg(0x4202, 0x00); -+ ov5647_write_reg(0x300D, 0x00); -+} -+ -+void OV5647_stream_off(void) -+{ -+ ov5647_write_reg(0x4202, 0x0f); -+ ov5647_write_reg(0x300D, 0x01); -+} -+ -+static const int sclk_rdiv_map[] = {1, 2, 4, 8}; -+ -+int OV5647_get_sysclk(void) -+{ -+ /* calculate sysclk */ -+ int tmp; -+ unsigned Multiplier, PreDiv, SysDiv, Pll_rdiv, Bit_div2x = 1; -+ unsigned div, sclk_rdiv, sysclk; -+ u8 temp; -+ -+ tmp = ov5647_read_reg(0x3034, &temp); -+ if (tmp < 0) -+ return tmp; -+ tmp &= 0x0f; -+ if (tmp == 8 || tmp == 10) -+ Bit_div2x = tmp / 2; -+ -+ tmp = ov5647_read_reg(0x3035, &temp); -+ if (tmp < 0) -+ return tmp; -+ SysDiv = tmp >> 4; -+ if (SysDiv == 0) -+ SysDiv = 16; -+ -+ tmp = ov5647_read_reg(0x3036, &temp); -+ if (tmp < 0) -+ return tmp; -+ Multiplier = tmp; -+ -+ tmp = ov5647_read_reg(0x3037, &temp); -+ if (tmp < 0) -+ return tmp; -+ PreDiv = tmp & 0x0f; -+ Pll_rdiv = ((tmp >> 4) & 0x01) + 1; -+ -+ tmp = ov5647_read_reg(0x3108, &temp); -+ if (tmp < 0) -+ return tmp; -+ sclk_rdiv = sclk_rdiv_map[tmp & 0x03]; -+ -+ sysclk = ov5647_data.mclk / 10000 * Multiplier; -+ div = PreDiv * SysDiv * Pll_rdiv * Bit_div2x * sclk_rdiv; -+ if (!div) { -+ pr_err("%s:Error divide by 0, (%d * %d * %d * %d * %d)\n", -+ __func__, PreDiv, SysDiv, Pll_rdiv, Bit_div2x, sclk_rdiv); -+ return -EINVAL; -+ } -+ if (!sysclk) { -+ pr_err("%s:Error 0 clk, ov5647_data.mclk=%d, Multiplier=%d\n", -+ __func__, ov5647_data.mclk, Multiplier); -+ return -EINVAL; -+ } -+ sysclk /= div; -+ pr_debug("%s: sysclk(%d) = %d / 10000 * %d / (%d * %d * %d * %d * %d)\n", -+ __func__, sysclk, ov5647_data.mclk, Multiplier, -+ PreDiv, SysDiv, Pll_rdiv, Bit_div2x, sclk_rdiv); -+ return sysclk; -+} -+ -+void OV5647_set_night_mode(void) -+{ -+ /* read HTS from register settings */ -+ u8 mode; -+ -+ ov5647_read_reg(0x3a00, &mode); -+ mode &= 0xfb; -+ ov5647_write_reg(0x3a00, mode); -+} -+ -+int OV5647_get_HTS(void) -+{ -+ /* read HTS from register settings */ -+ int HTS; -+ u8 temp; -+ -+ HTS = ov5647_read_reg(0x380c, &temp); -+ HTS = (HTS<<8) + ov5647_read_reg(0x380d, &temp); -+ -+ return HTS; -+} -+ -+int OV5647_get_VTS(void) -+{ -+ /* read VTS from register settings */ -+ int VTS; -+ u8 temp; -+ -+ /* total vertical size[15:8] high byte */ -+ VTS = ov5647_read_reg(0x380e, &temp); -+ -+ VTS = (VTS<<8) + ov5647_read_reg(0x380f, &temp); -+ -+ return VTS; -+} -+ -+int OV5647_set_VTS(int VTS) -+{ -+ /* write VTS to registers */ -+ int temp; -+ -+ temp = VTS & 0xff; -+ ov5647_write_reg(0x380f, temp); -+ -+ temp = VTS>>8; -+ ov5647_write_reg(0x380e, temp); -+ -+ return 0; -+} -+ -+int OV5647_get_shutter(void) -+{ -+ /* read shutter, in number of line period */ -+ int shutter; -+ u8 temp; -+ -+ shutter = (ov5647_read_reg(0x03500, &temp) & 0x0f); -+ shutter = (shutter<<8) + ov5647_read_reg(0x3501, &temp); -+ shutter = (shutter<<4) + (ov5647_read_reg(0x3502, &temp)>>4); -+ -+ return shutter; -+} -+ -+int OV5647_set_shutter(int shutter) -+{ -+ /* write shutter, in number of line period */ -+ int temp; -+ -+ shutter = shutter & 0xffff; -+ -+ temp = shutter & 0x0f; -+ temp = temp<<4; -+ ov5647_write_reg(0x3502, temp); -+ -+ temp = shutter & 0xfff; -+ temp = temp>>4; -+ ov5647_write_reg(0x3501, temp); -+ -+ temp = shutter>>12; -+ ov5647_write_reg(0x3500, temp); -+ -+ return 0; -+} -+ -+int OV5647_get_gain16(void) -+{ -+ /* read gain, 16 = 1x */ -+ int gain16; -+ u8 temp; -+ -+ gain16 = ov5647_read_reg(0x350a, &temp) & 0x03; -+ gain16 = (gain16<<8) + ov5647_read_reg(0x350b, &temp); -+ -+ return gain16; -+} -+ -+int OV5647_set_gain16(int gain16) -+{ -+ /* write gain, 16 = 1x */ -+ u8 temp; -+ gain16 = gain16 & 0x3ff; -+ -+ temp = gain16 & 0xff; -+ ov5647_write_reg(0x350b, temp); -+ -+ temp = gain16>>8; -+ ov5647_write_reg(0x350a, temp); -+ -+ return 0; -+} -+ -+int OV5647_get_light_freq(void) -+{ -+ /* get banding filter value */ -+ int temp, temp1, light_freq = 0; -+ u8 tmp; -+ -+ temp = ov5647_read_reg(0x3c01, &tmp); -+ -+ if (temp & 0x80) { -+ /* manual */ -+ temp1 = ov5647_read_reg(0x3c00, &tmp); -+ if (temp1 & 0x04) { -+ /* 50Hz */ -+ light_freq = 50; -+ } else { -+ /* 60Hz */ -+ light_freq = 60; -+ } -+ } else { -+ /* auto */ -+ temp1 = ov5647_read_reg(0x3c0c, &tmp); -+ if (temp1 & 0x01) { -+ /* 50Hz */ -+ light_freq = 50; -+ } else { -+ /* 60Hz */ -+ light_freq = 60; -+ } -+ } -+ return light_freq; -+} -+ -+void OV5647_set_bandingfilter(void) -+{ -+ int prev_VTS; -+ int band_step60, max_band60, band_step50, max_band50; -+ -+ /* read preview PCLK */ -+ prev_sysclk = OV5647_get_sysclk(); -+ /* read preview HTS */ -+ prev_HTS = OV5647_get_HTS(); -+ -+ /* read preview VTS */ -+ prev_VTS = OV5647_get_VTS(); -+ -+ /* calculate banding filter */ -+ /* 60Hz */ -+ band_step60 = prev_sysclk * 100/prev_HTS * 100/120; -+ ov5647_write_reg(0x3a0a, (band_step60 >> 8)); -+ ov5647_write_reg(0x3a0b, (band_step60 & 0xff)); -+ -+ max_band60 = (int)((prev_VTS-4)/band_step60); -+ ov5647_write_reg(0x3a0d, max_band60); -+ -+ /* 50Hz */ -+ band_step50 = prev_sysclk * 100/prev_HTS; -+ ov5647_write_reg(0x3a08, (band_step50 >> 8)); -+ ov5647_write_reg(0x3a09, (band_step50 & 0xff)); -+ -+ max_band50 = (int)((prev_VTS-4)/band_step50); -+ ov5647_write_reg(0x3a0e, max_band50); -+} -+ -+int OV5647_set_AE_target(int target) -+{ -+ /* stable in high */ -+ int fast_high, fast_low; -+ AE_low = target * 23 / 25; /* 0.92 */ -+ AE_high = target * 27 / 25; /* 1.08 */ -+ -+ fast_high = AE_high<<1; -+ if (fast_high > 255) -+ fast_high = 255; -+ -+ fast_low = AE_low >> 1; -+ -+ ov5647_write_reg(0x3a0f, AE_high); -+ ov5647_write_reg(0x3a10, AE_low); -+ ov5647_write_reg(0x3a1b, AE_high); -+ ov5647_write_reg(0x3a1e, AE_low); -+ ov5647_write_reg(0x3a11, fast_high); -+ ov5647_write_reg(0x3a1f, fast_low); -+ -+ return 0; -+} -+ -+void OV5647_turn_on_AE_AG(int enable) -+{ -+ u8 ae_ag_ctrl; -+ -+ ov5647_read_reg(0x3503, &ae_ag_ctrl); -+ if (enable) { -+ /* turn on auto AE/AG */ -+ ae_ag_ctrl = ae_ag_ctrl & ~(0x03); -+ } else { -+ /* turn off AE/AG */ -+ ae_ag_ctrl = ae_ag_ctrl | 0x03; -+ } -+ ov5647_write_reg(0x3503, ae_ag_ctrl); -+} -+ -+bool ov5647_binning_on(void) -+{ -+ u8 temp; -+ ov5647_read_reg(0x3821, &temp); -+ temp &= 0xfe; -+ if (temp) -+ return true; -+ else -+ return false; -+} -+ -+static void ov5647_set_virtual_channel(int channel) -+{ -+ u8 channel_id; -+ -+ ov5647_read_reg(0x4814, &channel_id); -+ channel_id &= ~(3 << 6); -+ ov5647_write_reg(0x4814, channel_id | (channel << 6)); -+} -+ -+/* download ov5647 settings to sensor through i2c */ -+static int ov5647_download_firmware(struct reg_value *pModeSetting, s32 ArySize) -+{ -+ register u32 Delay_ms = 0; -+ register u16 RegAddr = 0; -+ register u8 Mask = 0; -+ register u8 Val = 0; -+ u8 RegVal = 0; -+ int i, retval = 0; -+ -+ for (i = 0; i < ArySize; ++i, ++pModeSetting) { -+ Delay_ms = pModeSetting->u32Delay_ms; -+ RegAddr = pModeSetting->u16RegAddr; -+ Val = pModeSetting->u8Val; -+ Mask = pModeSetting->u8Mask; -+ -+ if (Mask) { -+ retval = ov5647_read_reg(RegAddr, &RegVal); -+ if (retval < 0) -+ goto err; -+ -+ RegVal &= ~(u8)Mask; -+ Val &= Mask; -+ Val |= RegVal; -+ } -+ -+ retval = ov5647_write_reg(RegAddr, Val); -+ if (retval < 0) -+ goto err; -+ -+ if (Delay_ms) -+ msleep(Delay_ms); -+ } -+err: -+ return retval; -+} -+ -+/* sensor changes between scaling and subsampling -+ * go through exposure calcualtion -+ */ -+static int ov5647_change_mode_exposure_calc(enum ov5647_frame_rate frame_rate, -+ enum ov5647_mode mode) -+{ -+ struct reg_value *pModeSetting = NULL; -+ s32 ArySize = 0; -+ u8 average; -+ int prev_shutter, prev_gain16; -+ int cap_shutter, cap_gain16; -+ int cap_sysclk, cap_HTS, cap_VTS; -+ int light_freq, cap_bandfilt, cap_maxband; -+ long cap_gain16_shutter; -+ int retval = 0; -+ -+ /* check if the input mode and frame rate is valid */ -+ pModeSetting = -+ ov5647_mode_info_data[frame_rate][mode].init_data_ptr; -+ ArySize = -+ ov5647_mode_info_data[frame_rate][mode].init_data_size; -+ -+ ov5647_data.pix.width = -+ ov5647_mode_info_data[frame_rate][mode].width; -+ ov5647_data.pix.height = -+ ov5647_mode_info_data[frame_rate][mode].height; -+ ov5647_data_add.map_sizeimage = -+ ov5647_data.pix.width * ov5647_data.pix.height * 3 / 2; -+ -+ if (ov5647_data.pix.width == 0 || ov5647_data.pix.height == 0 || -+ pModeSetting == NULL || ArySize == 0) -+ return -EINVAL; -+ -+ /* turn off AE/AG */ -+ OV5647_turn_on_AE_AG(0); -+ -+ /* read preview shutter */ -+ prev_shutter = OV5647_get_shutter(); -+ if ((ov5647_binning_on()) && (mode != ov5647_mode_960P_1280_960) && -+ (mode != ov5647_mode_720P_1280_720) && (mode != ov5647_mode_1080P_1920_1080)) -+ prev_shutter *= 2; -+ -+ /* read preview gain */ -+ prev_gain16 = OV5647_get_gain16(); -+ -+ /* get average */ -+ ov5647_read_reg(0x5693, &average); -+ -+ /* turn off night mode for capture */ -+ OV5647_set_night_mode(); -+ -+ /* turn off overlay */ -+ /* ov5647_write_reg(0x3022, 0x06);//if no af function, just skip it */ -+ -+ OV5647_stream_off(); -+ -+ /* Write capture setting */ -+ retval = ov5647_download_firmware(pModeSetting, ArySize); -+ if (retval < 0) -+ goto err; -+ -+ /* read capture VTS */ -+ cap_VTS = OV5647_get_VTS(); -+ cap_HTS = OV5647_get_HTS(); -+ cap_sysclk = OV5647_get_sysclk(); -+ -+ /* calculate capture banding filter */ -+ light_freq = OV5647_get_light_freq(); -+ if (light_freq == 60) { -+ /* 60Hz */ -+ cap_bandfilt = cap_sysclk * 100 / cap_HTS * 100 / 120; -+ } else { -+ /* 50Hz */ -+ cap_bandfilt = cap_sysclk * 100 / cap_HTS; -+ } -+ cap_maxband = (int)((cap_VTS - 4)/cap_bandfilt); -+ -+ /* calculate capture shutter/gain16 */ -+ if (average > AE_low && average < AE_high) { -+ /* in stable range */ -+ cap_gain16_shutter = -+ prev_gain16 * prev_shutter * cap_sysclk/prev_sysclk -+ * prev_HTS/cap_HTS * AE_Target / average; -+ } else { -+ cap_gain16_shutter = -+ prev_gain16 * prev_shutter * cap_sysclk/prev_sysclk -+ * prev_HTS/cap_HTS; -+ } -+ -+ /* gain to shutter */ -+ if (cap_gain16_shutter < (cap_bandfilt * 16)) { -+ /* shutter < 1/100 */ -+ cap_shutter = cap_gain16_shutter/16; -+ if (cap_shutter < 1) -+ cap_shutter = 1; -+ -+ cap_gain16 = cap_gain16_shutter/cap_shutter; -+ if (cap_gain16 < 16) -+ cap_gain16 = 16; -+ } else { -+ if (cap_gain16_shutter > -+ (cap_bandfilt * cap_maxband * 16)) { -+ /* exposure reach max */ -+ cap_shutter = cap_bandfilt * cap_maxband; -+ cap_gain16 = cap_gain16_shutter / cap_shutter; -+ } else { -+ /* 1/100 < (cap_shutter = n/100) =< max */ -+ cap_shutter = -+ ((int) (cap_gain16_shutter/16 / cap_bandfilt)) -+ *cap_bandfilt; -+ cap_gain16 = cap_gain16_shutter / cap_shutter; -+ } -+ } -+ -+ /* write capture gain */ -+ OV5647_set_gain16(cap_gain16); -+ -+ /* write capture shutter */ -+ if (cap_shutter > (cap_VTS - 4)) { -+ cap_VTS = cap_shutter + 4; -+ OV5647_set_VTS(cap_VTS); -+ } -+ OV5647_set_shutter(cap_shutter); -+ -+ OV5647_stream_on(); -+ -+err: -+ return retval; -+} -+ -+/* if sensor changes inside scaling or subsampling -+ * change mode directly -+ * */ -+static int ov5647_change_mode_direct(enum ov5647_frame_rate frame_rate, -+ enum ov5647_mode mode) -+{ -+ struct reg_value *pModeSetting = NULL; -+ s32 ArySize = 0; -+ int retval = 0; -+ -+ /* check if the input mode and frame rate is valid */ -+ pModeSetting = -+ ov5647_mode_info_data[frame_rate][mode].init_data_ptr; -+ ArySize = -+ ov5647_mode_info_data[frame_rate][mode].init_data_size; -+ -+ ov5647_data.pix.width = -+ ov5647_mode_info_data[frame_rate][mode].width; -+ ov5647_data.pix.height = -+ ov5647_mode_info_data[frame_rate][mode].height; -+ ov5647_data_add.map_sizeimage = -+ ov5647_data.pix.width * ov5647_data.pix.height * 3 / 2; -+ -+ if (ov5647_data.pix.width == 0 || ov5647_data.pix.height == 0 || -+ pModeSetting == NULL || ArySize == 0) -+ return -EINVAL; -+ -+ /* turn off AE/AG */ -+ OV5647_turn_on_AE_AG(0); -+ -+ OV5647_stream_off(); -+ -+ /* Write capture setting */ -+ retval = ov5647_download_firmware(pModeSetting, ArySize); -+ if (retval < 0) -+ goto err; -+ -+ OV5647_stream_on(); -+ -+ OV5647_turn_on_AE_AG(1); -+ -+err: -+ return retval; -+} -+ -+static int ov5647_init_mode(enum ov5647_frame_rate frame_rate, -+ enum ov5647_mode mode, enum ov5647_mode orig_mode) -+{ -+ struct reg_value *pModeSetting = NULL; -+ s32 ArySize = 0; -+ int retval = 0; -+ void *mipi_csi2_info; -+ u32 mipi_reg, msec_wait4stable = 0; -+ enum ov5647_downsize_mode dn_mode, orig_dn_mode; -+ -+ if ((mode > ov5647_mode_MAX || mode < ov5647_mode_MIN) -+ && (mode != ov5647_mode_INIT)) { -+ pr_err("Wrong ov5647 mode detected!\n"); -+ return -1; -+ } -+ -+ mipi_csi2_info = mipi_csi2_get_info(); -+ -+ /* initial mipi dphy */ -+ if (!mipi_csi2_info) { -+ printk(KERN_ERR "%s() in %s: Fail to get mipi_csi2_info!\n", -+ __func__, __FILE__); -+ return -1; -+ } -+ -+ ov5647_write_reg(0x4800, 0x25); -+ OV5647_stream_off(); -+ -+ if (!mipi_csi2_get_status(mipi_csi2_info)) -+ mipi_csi2_enable(mipi_csi2_info); -+ -+ if (!mipi_csi2_get_status(mipi_csi2_info)) { -+ pr_err("Can not enable mipi csi2 driver!\n"); -+ return -1; -+ } -+ -+ mipi_csi2_set_lanes(mipi_csi2_info, 2); -+ -+ /*Only reset MIPI CSI2 HW at sensor initialize*/ -+ if (mode == ov5647_mode_INIT) -+ mipi_csi2_reset(mipi_csi2_info); -+ -+ /* reg 0x3034[3:0] == 0x8 is 8bit mode */ -+ mipi_csi2_set_datatype(mipi_csi2_info, MIPI_DT_RAW8); -+ -+ if (orig_mode != ov5647_mode_INIT) { -+ dn_mode = ov5647_mode_info_data[frame_rate][mode].dn_mode; -+ orig_dn_mode = ov5647_mode_info_data[frame_rate][orig_mode].dn_mode; -+ } -+ else { -+ orig_dn_mode = dn_mode = 0; -+ } -+ -+ if (mode == ov5647_mode_INIT) { -+ int index = (int)ov5647_data.streamcap.capturemode; -+ -+ pModeSetting = ov5647_mode_info_data[frame_rate][index].init_data_ptr; -+ ArySize = ov5647_mode_info_data[frame_rate][index].init_data_size; -+ retval = ov5647_download_firmware(pModeSetting, ArySize); -+ if (retval < 0) -+ goto err; -+ } else if ((dn_mode == SUBSAMPLING && orig_dn_mode == SCALING) || -+ (dn_mode == SCALING && orig_dn_mode == SUBSAMPLING)) { -+ /* change between subsampling and scaling -+ * go through exposure calucation */ -+ retval = ov5647_change_mode_exposure_calc(frame_rate, mode); -+ } else { -+ /* change inside subsampling or scaling -+ * download firmware directly */ -+ retval = ov5647_change_mode_direct(frame_rate, mode); -+ } -+ -+ if (retval < 0) -+ goto err; -+ -+ OV5647_set_AE_target(AE_Target); -+ OV5647_get_light_freq(); -+ OV5647_set_bandingfilter(); -+ ov5647_set_virtual_channel(ov5647_data.virtual_channel); -+ -+ /* add delay to wait for sensor stable */ -+ if (frame_rate == ov5647_15_fps) { -+ /* dump the first nine frames: 1/15*9 */ -+ msec_wait4stable = 600; -+ } else if (frame_rate == ov5647_30_fps) { -+ /* dump the first nine frames: 1/30*9 */ -+ msec_wait4stable = 300; -+ } -+ msleep(msec_wait4stable); -+ -+ if (mipi_csi2_info) { -+ unsigned int i = 0; -+ u8 resetval; -+ -+ /* wait for mipi sensor ready */ -+ while (1) { -+ mipi_reg = mipi_csi2_dphy_status(mipi_csi2_info); -+ if (mipi_reg != 0x200) -+ break; -+ if (i++ >= 20) { -+ pr_err("mipi csi2 can not receive sensor clk! %x\n", mipi_reg); -+ return -1; -+ } -+ msleep(10); -+ } -+ -+ i = 0; -+ /* wait for mipi stable */ -+ while (1) { -+ mipi_reg = mipi_csi2_get_error1(mipi_csi2_info); -+ if (!mipi_reg) -+ break; -+ if (i++ >= 20) { -+ pr_err("mipi csi2 can not receive data correctly!\n"); -+ return -1; -+ } -+ msleep(10); -+ } -+ -+ pr_debug("receiving data"); -+ mipi_reg = mipi_csi2_get_error2(mipi_csi2_info); -+ pr_debug("mipi_csi2 error2 = 0x%X\n", mipi_reg); -+ mipi_reg = mipi_csi2_dphy_status(mipi_csi2_info); -+ pr_debug("mipi_csi2_dphy_status = 0x%X\n", mipi_reg); -+ -+ ov5647_read_reg(0x0100, &resetval); -+ if (!resetval&0x01) { -+ pr_info("DEVICE WAS IN SOFTWARE STANDBY"); -+ ov5647_write_reg(0x0100, 0x01); -+ } -+ -+ ov5647_write_reg(0x4800, 0x04); -+ msleep(266); -+ OV5647_stream_on(); -+ msleep(30); -+ OV5647_turn_on_AE_AG(1); -+ } -+err: -+ return retval; -+} -+ -+/* --------------- IOCTL functions from v4l2_int_ioctl_desc --------------- */ -+ -+static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p) -+{ -+ if (s == NULL) { -+ pr_err(" ERROR!! no slave device set!\n"); -+ return -1; -+ } -+ -+ memset(p, 0, sizeof(*p)); -+ p->u.bt656.clock_curr = ov5647_data.mclk; -+ pr_debug(" clock_curr=mclk=%d\n", ov5647_data.mclk); -+ p->if_type = V4L2_IF_TYPE_BT656; -+ p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_10BIT; -+ p->u.bt656.clock_min = OV5647_XCLK_MIN; -+ p->u.bt656.clock_max = OV5647_XCLK_MAX; -+ p->u.bt656.bt_sync_correct = 1; /* Indicate external vsync */ -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_s_power - V4L2 sensor interface handler for VIDIOC_S_POWER ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @on: indicates power mode (on or off) -+ * -+ * Turns the power on or off, depending on the value of on and returns the -+ * appropriate error code. -+ */ -+static int ioctl_s_power(struct v4l2_int_device *s, int on) -+{ -+ struct sensor_data *sensor = s->priv; -+ -+ if (on && !sensor->on) { -+ if (io_regulator) -+ if (regulator_enable(io_regulator) != 0) -+ return -EIO; -+ if (core_regulator) -+ if (regulator_enable(core_regulator) != 0) -+ return -EIO; -+ if (gpo_regulator) -+ if (regulator_enable(gpo_regulator) != 0) -+ return -EIO; -+ if (analog_regulator) -+ if (regulator_enable(analog_regulator) != 0) -+ return -EIO; -+ /* Make sure power on */ -+ ov5647_standby(0); -+ } else if (!on && sensor->on) { -+ if (analog_regulator) -+ regulator_disable(analog_regulator); -+ if (core_regulator) -+ regulator_disable(core_regulator); -+ if (io_regulator) -+ regulator_disable(io_regulator); -+ if (gpo_regulator) -+ regulator_disable(gpo_regulator); -+ -+ ov5647_standby(1); -+ } -+ -+ sensor->on = on; -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure -+ * -+ * Returns the sensor's video CAPTURE parameters. -+ */ -+static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) -+{ -+ struct sensor_data *sensor = s->priv; -+ struct v4l2_captureparm *cparm = &a->parm.capture; -+ int ret = 0; -+ -+ switch (a->type) { -+ /* This is the only case currently handled. */ -+ case V4L2_BUF_TYPE_VIDEO_CAPTURE: -+ memset(a, 0, sizeof(*a)); -+ a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; -+ cparm->capability = sensor->streamcap.capability; -+ cparm->timeperframe = sensor->streamcap.timeperframe; -+ cparm->capturemode = sensor->streamcap.capturemode; -+ ret = 0; -+ break; -+ -+ /* These are all the possible cases. */ -+ case V4L2_BUF_TYPE_VIDEO_OUTPUT: -+ case V4L2_BUF_TYPE_VIDEO_OVERLAY: -+ case V4L2_BUF_TYPE_VBI_CAPTURE: -+ case V4L2_BUF_TYPE_VBI_OUTPUT: -+ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: -+ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: -+ ret = -EINVAL; -+ break; -+ -+ default: -+ pr_debug(" type is unknown - %d\n", a->type); -+ ret = -EINVAL; -+ break; -+ } -+ -+ return ret; -+} -+ -+/*! -+ * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure -+ * -+ * Configures the sensor to use the input parameters, if possible. If -+ * not possible, reverts to the old parameters and returns the -+ * appropriate error code. -+ */ -+static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) -+{ -+ struct sensor_data *sensor = s->priv; -+ struct v4l2_fract *timeperframe = &a->parm.capture.timeperframe; -+ u32 tgt_fps; /* target frames per secound */ -+ enum ov5647_frame_rate frame_rate; -+ enum ov5647_mode orig_mode; -+ int ret = 0; -+ -+ /* Make sure power on */ -+ ov5647_standby(0); -+ -+ switch (a->type) { -+ /* This is the only case currently handled. */ -+ case V4L2_BUF_TYPE_VIDEO_CAPTURE: -+ /* Check that the new frame rate is allowed. */ -+ if ((timeperframe->numerator == 0) || -+ (timeperframe->denominator == 0)) { -+ timeperframe->denominator = DEFAULT_FPS; -+ timeperframe->numerator = 1; -+ } -+ -+ tgt_fps = timeperframe->denominator / -+ timeperframe->numerator; -+ -+ if (tgt_fps > MAX_FPS) { -+ timeperframe->denominator = MAX_FPS; -+ timeperframe->numerator = 1; -+ } else if (tgt_fps < MIN_FPS) { -+ timeperframe->denominator = MIN_FPS; -+ timeperframe->numerator = 1; -+ } -+ -+ /* Actual frame rate we use */ -+ tgt_fps = timeperframe->denominator / -+ timeperframe->numerator; -+ -+ if (tgt_fps == 15) -+ frame_rate = ov5647_15_fps; -+ else if (tgt_fps == 30) -+ frame_rate = ov5647_30_fps; -+ else { -+ pr_err(" The camera frame rate is not supported!\n"); -+ return -EINVAL; -+ } -+ -+ orig_mode = sensor->streamcap.capturemode; -+ ret = ov5647_init_mode(frame_rate, -+ (u32)a->parm.capture.capturemode, orig_mode); -+ if (ret < 0) -+ return ret; -+ -+ sensor->streamcap.timeperframe = *timeperframe; -+ sensor->streamcap.capturemode = -+ (u32)a->parm.capture.capturemode; -+ -+ break; -+ -+ /* These are all the possible cases. */ -+ case V4L2_BUF_TYPE_VIDEO_OUTPUT: -+ case V4L2_BUF_TYPE_VIDEO_OVERLAY: -+ case V4L2_BUF_TYPE_VBI_CAPTURE: -+ case V4L2_BUF_TYPE_VBI_OUTPUT: -+ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: -+ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: -+ pr_debug(" type is not " \ -+ "V4L2_BUF_TYPE_VIDEO_CAPTURE but %d\n", -+ a->type); -+ ret = -EINVAL; -+ break; -+ -+ default: -+ pr_debug(" type is unknown - %d\n", a->type); -+ ret = -EINVAL; -+ break; -+ } -+ -+ return ret; -+} -+ -+/*! -+ * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap -+ * @s: pointer to standard V4L2 device structure -+ * @f: pointer to standard V4L2 v4l2_format structure -+ * -+ * Returns the sensor's current pixel format in the v4l2_format -+ * parameter. -+ */ -+static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) -+{ -+ struct sensor_data *sensor = s->priv; -+ -+ switch (f->type) { -+ case V4L2_BUF_TYPE_VIDEO_CAPTURE: -+ f->fmt.pix = sensor->pix; -+ pr_debug("%s: %dx%d\n", __func__, sensor->pix.width, sensor->pix.height); -+ break; -+ -+ case V4L2_BUF_TYPE_SENSOR: -+ pr_debug("%s: left=%d, top=%d, %dx%d\n", __func__, -+ sensor->spix.left, sensor->spix.top, -+ sensor->spix.swidth, sensor->spix.sheight); -+ f->fmt.spix = sensor->spix; -+ break; -+ -+ case V4L2_BUF_TYPE_PRIVATE: -+ break; -+ -+ default: -+ f->fmt.pix = sensor->pix; -+ break; -+ } -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure -+ * -+ * If the requested control is supported, returns the control's current -+ * value from the video_control[] array. Otherwise, returns -EINVAL -+ * if the control is not supported. -+ */ -+static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) -+{ -+ int ret = 0; -+ -+ switch (vc->id) { -+ case V4L2_CID_BRIGHTNESS: -+ vc->value = ov5647_data.brightness; -+ break; -+ case V4L2_CID_HUE: -+ vc->value = ov5647_data.hue; -+ break; -+ case V4L2_CID_CONTRAST: -+ vc->value = ov5647_data.contrast; -+ break; -+ case V4L2_CID_SATURATION: -+ vc->value = ov5647_data.saturation; -+ break; -+ case V4L2_CID_RED_BALANCE: -+ vc->value = ov5647_data.red; -+ break; -+ case V4L2_CID_BLUE_BALANCE: -+ vc->value = ov5647_data.blue; -+ break; -+ case V4L2_CID_EXPOSURE: -+ vc->value = ov5647_data.ae_mode; -+ break; -+ default: -+ ret = -EINVAL; -+ } -+ -+ return ret; -+} -+ -+/*! -+ * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure -+ * -+ * If the requested control is supported, sets the control's current -+ * value in HW (and updates the video_control[] array). Otherwise, -+ * returns -EINVAL if the control is not supported. -+ */ -+static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) -+{ -+ int retval = 0; -+ -+ pr_debug("In ov5647:ioctl_s_ctrl %d\n", -+ vc->id); -+ -+ switch (vc->id) { -+ case V4L2_CID_BRIGHTNESS: -+ break; -+ case V4L2_CID_CONTRAST: -+ break; -+ case V4L2_CID_SATURATION: -+ break; -+ case V4L2_CID_HUE: -+ break; -+ case V4L2_CID_AUTO_WHITE_BALANCE: -+ break; -+ case V4L2_CID_DO_WHITE_BALANCE: -+ break; -+ case V4L2_CID_RED_BALANCE: -+ break; -+ case V4L2_CID_BLUE_BALANCE: -+ break; -+ case V4L2_CID_GAMMA: -+ break; -+ case V4L2_CID_EXPOSURE: -+ break; -+ case V4L2_CID_AUTOGAIN: -+ break; -+ case V4L2_CID_GAIN: -+ break; -+ case V4L2_CID_HFLIP: -+ break; -+ case V4L2_CID_VFLIP: -+ break; -+ default: -+ retval = -EPERM; -+ break; -+ } -+ -+ return retval; -+} -+ -+/*! -+ * ioctl_enum_framesizes - V4L2 sensor interface handler for -+ * VIDIOC_ENUM_FRAMESIZES ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure -+ * -+ * Return 0 if successful, otherwise -EINVAL. -+ */ -+static int ioctl_enum_framesizes(struct v4l2_int_device *s, -+ struct v4l2_frmsizeenum *fsize) -+{ -+ if (fsize->index > ov5647_mode_MAX) -+ return -EINVAL; -+ -+ fsize->pixel_format = ov5647_data.pix.pixelformat; -+ fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE; -+ fsize->discrete.width = -+ max(ov5647_mode_info_data[0][fsize->index].width, -+ ov5647_mode_info_data[1][fsize->index].width); -+ fsize->discrete.height = -+ max(ov5647_mode_info_data[0][fsize->index].height, -+ ov5647_mode_info_data[1][fsize->index].height); -+ return 0; -+} -+ -+/*! -+ * ioctl_g_chip_ident - V4L2 sensor interface handler for -+ * VIDIOC_DBG_G_CHIP_IDENT ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @id: pointer to int -+ * -+ * Return 0. -+ */ -+static int ioctl_g_chip_ident(struct v4l2_int_device *s, int *id) -+{ -+ ((struct v4l2_dbg_chip_ident *)id)->match.type = -+ V4L2_CHIP_MATCH_I2C_DRIVER; -+ strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name, -+ "ov5647_mipi_camera"); -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT -+ * @s: pointer to standard V4L2 device structure -+ */ -+static int ioctl_init(struct v4l2_int_device *s) -+{ -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_enum_fmt_cap - V4L2 sensor interface handler for VIDIOC_ENUM_FMT -+ * @s: pointer to standard V4L2 device structure -+ * @fmt: pointer to standard V4L2 fmt description structure -+ * -+ * Return 0. -+ */ -+static int ioctl_enum_fmt_cap(struct v4l2_int_device *s, -+ struct v4l2_fmtdesc *fmt) -+{ -+ if (fmt->index > ov5647_mode_MAX) -+ return -EINVAL; -+ -+ fmt->pixelformat = ov5647_data.pix.pixelformat; -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num -+ * @s: pointer to standard V4L2 device structure -+ * -+ * Initialise the device when slave attaches to the master. -+ */ -+static int ioctl_dev_init(struct v4l2_int_device *s) -+{ -+ struct sensor_data *sensor = s->priv; -+ u32 tgt_xclk; /* target xclk */ -+ u32 tgt_fps; /* target frames per secound */ -+ int ret; -+ enum ov5647_frame_rate frame_rate; -+ void *mipi_csi2_info; -+ -+ ov5647_data.on = true; -+ -+ /* mclk */ -+ tgt_xclk = ov5647_data.mclk; -+ tgt_xclk = min(tgt_xclk, (u32)OV5647_XCLK_MAX); -+ tgt_xclk = max(tgt_xclk, (u32)OV5647_XCLK_MIN); -+ ov5647_data.mclk = tgt_xclk; -+ -+ pr_debug(" Setting mclk to %d MHz\n", tgt_xclk / 1000000); -+ -+ /* Default camera frame rate is set in probe */ -+ tgt_fps = sensor->streamcap.timeperframe.denominator / -+ sensor->streamcap.timeperframe.numerator; -+ -+ if (tgt_fps == 15) -+ frame_rate = ov5647_15_fps; -+ else if (tgt_fps == 30) -+ frame_rate = ov5647_30_fps; -+ else -+ return -EINVAL; /* Only support 15fps or 30fps now. */ -+ -+ mipi_csi2_info = mipi_csi2_get_info(); -+ -+ /* enable mipi csi2 */ -+ if (mipi_csi2_info) -+ mipi_csi2_enable(mipi_csi2_info); -+ else { -+ printk(KERN_ERR "%s() in %s: Fail to get mipi_csi2_info!\n", -+ __func__, __FILE__); -+ return -EPERM; -+ } -+ -+ ret = ov5647_init_mode(frame_rate, ov5647_mode_INIT, ov5647_mode_INIT); -+ -+ return ret; -+} -+ -+/*! -+ * ioctl_dev_exit - V4L2 sensor interface handler for vidioc_int_dev_exit_num -+ * @s: pointer to standard V4L2 device structure -+ * -+ * Delinitialise the device when slave detaches to the master. -+ */ -+static int ioctl_dev_exit(struct v4l2_int_device *s) -+{ -+ void *mipi_csi2_info; -+ -+ mipi_csi2_info = mipi_csi2_get_info(); -+ -+ /* disable mipi csi2 */ -+ if (mipi_csi2_info) -+ if (mipi_csi2_get_status(mipi_csi2_info)) -+ mipi_csi2_disable(mipi_csi2_info); -+ -+ return 0; -+} -+ -+/*! -+ * This structure defines all the ioctls for this module and links them to the -+ * enumeration. -+ */ -+static struct v4l2_int_ioctl_desc ov5647_ioctl_desc[] = { -+ {vidioc_int_dev_init_num, (v4l2_int_ioctl_func *) ioctl_dev_init}, -+ {vidioc_int_dev_exit_num, ioctl_dev_exit}, -+ {vidioc_int_s_power_num, (v4l2_int_ioctl_func *) ioctl_s_power}, -+ {vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func *) ioctl_g_ifparm}, -+/* {vidioc_int_g_needs_reset_num, -+ (v4l2_int_ioctl_func *)ioctl_g_needs_reset}, */ -+/* {vidioc_int_reset_num, (v4l2_int_ioctl_func *)ioctl_reset}, */ -+ {vidioc_int_init_num, (v4l2_int_ioctl_func *) ioctl_init}, -+ {vidioc_int_enum_fmt_cap_num, -+ (v4l2_int_ioctl_func *) ioctl_enum_fmt_cap}, -+/* {vidioc_int_try_fmt_cap_num, -+ (v4l2_int_ioctl_func *)ioctl_try_fmt_cap}, */ -+ {vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func *) ioctl_g_fmt_cap}, -+/* {vidioc_int_s_fmt_cap_num, (v4l2_int_ioctl_func *) ioctl_s_fmt_cap}, */ -+ {vidioc_int_g_parm_num, (v4l2_int_ioctl_func *) ioctl_g_parm}, -+ {vidioc_int_s_parm_num, (v4l2_int_ioctl_func *) ioctl_s_parm}, -+/* {vidioc_int_queryctrl_num, (v4l2_int_ioctl_func *)ioctl_queryctrl}, */ -+ {vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func *) ioctl_g_ctrl}, -+ {vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func *) ioctl_s_ctrl}, -+ {vidioc_int_enum_framesizes_num, -+ (v4l2_int_ioctl_func *) ioctl_enum_framesizes}, -+ {vidioc_int_g_chip_ident_num, -+ (v4l2_int_ioctl_func *) ioctl_g_chip_ident}, -+}; -+ -+static struct v4l2_int_slave ov5647_slave = { -+ .ioctls = ov5647_ioctl_desc, -+ .num_ioctls = ARRAY_SIZE(ov5647_ioctl_desc), -+}; -+ -+static struct v4l2_int_device ov5647_int_device = { -+ .module = THIS_MODULE, -+ .name = "ov5647_mipi", -+ .type = v4l2_int_type_slave, -+ .u = { -+ .slave = &ov5647_slave, -+ }, -+}; -+ -+static ssize_t show_reg(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ u8 val; -+ s32 rval = ov5647_read_reg(ov5647_data.last_reg, &val); -+ -+ return sprintf(buf, "ov5647[0x%04x]=0x%02x\n",ov5647_data.last_reg, rval); -+} -+static ssize_t set_reg(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ int regnum, value; -+ int num_parsed = sscanf(buf, "%04x=%02x", ®num, &value); -+ if (1 <= num_parsed) { -+ if (0xffff < (unsigned)regnum){ -+ pr_err("%s:invalid regnum %x\n", __func__, regnum); -+ return 0; -+ } -+ ov5647_data.last_reg = regnum; -+ } -+ if (2 == num_parsed) { -+ if (0xff < (unsigned)value) { -+ pr_err("%s:invalid value %x\n", __func__, value); -+ return 0; -+ } -+ ov5647_write_reg(ov5647_data.last_reg, value); -+ } -+ return count; -+} -+ -+/* XXX: workaround for v4l2 client except for gstreamer-imx */ -+static ssize_t show_mode(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ return sprintf(buf, "ov5647 mode = 0x%02x\n", (int)ov5647_data.streamcap.capturemode); -+} -+ -+static ssize_t set_mode(struct device *dev, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ unsigned long mode; -+ -+ mode = simple_strtoul(buf, NULL, 10); -+ if ((enum ov5647_mode)mode >= ov5647_mode_MIN && -+ (enum ov5647_mode)mode <= ov5647_mode_MAX) { -+ -+ ov5647_data.streamcap.capturemode = mode; -+ ov5647_data.pix.width = -+ max(ov5647_mode_info_data[0][mode].width, -+ ov5647_mode_info_data[1][mode].width); -+ ov5647_data.pix.height = -+ max(ov5647_mode_info_data[0][mode].height, -+ ov5647_mode_info_data[1][mode].height); -+ ov5647_data_add.map_sizeimage = -+ ov5647_data.pix.width * ov5647_data.pix.height * 3 / 2; -+ } -+ -+ return count; -+} -+ -+static DEVICE_ATTR(ov5647_reg, S_IRUGO|S_IWUSR|S_IWGRP, show_reg, set_reg); -+static DEVICE_ATTR(ov5647_mode, S_IRUGO|S_IWUSR|S_IWGRP, show_mode, set_mode); -+ -+/*! -+ * ov5647 I2C probe function -+ * -+ * @param adapter struct i2c_adapter * -+ * @return Error code indicating success or failure -+ */ -+static int ov5647_probe(struct i2c_client *client, -+ const struct i2c_device_id *id) -+{ -+ struct device *dev = &client->dev; -+ int retval, init, gpio; -+ u8 chip_id_high, chip_id_low; -+ struct sensor_data *sensor = &ov5647_data; -+ enum of_gpio_flags flags; -+ bool extbuf; -+ -+ /* request power down pin */ -+ pwn_gpio = of_get_named_gpio_flags(dev->of_node, "pwn-gpios", 0, &flags); -+ if (gpio_is_valid(pwn_gpio)) { -+ /* powon_active - camera power on */ -+ /* !powon_active - camera power down */ -+ powon_active = !(flags & OF_GPIO_ACTIVE_LOW); -+ init = (flags & OF_GPIO_ACTIVE_LOW) ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW; -+ -+ retval = devm_gpio_request_one(dev, pwn_gpio, init, "ov5647_mipi_pwdn"); -+ if (retval < 0) { -+ dev_warn(dev, "request of pwn_gpio failed"); -+ pwn_gpio = -EINVAL; -+ } -+ } -+ -+ /* request reset pin */ -+ rst_gpio = of_get_named_gpio_flags(dev->of_node, "rst-gpios", 0, &flags); -+ if (gpio_is_valid(rst_gpio)) { -+ /* rst_active - camera reset */ -+ /* !rst_active - clear camera reset */ -+ rst_active = !(flags & OF_GPIO_ACTIVE_LOW); -+ init = (flags & OF_GPIO_ACTIVE_LOW) ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW; -+ -+ retval = devm_gpio_request_one(dev, rst_gpio, init, "ov5647_mipi_reset"); -+ if (retval < 0) { -+ dev_warn(dev, "request of ov5647_mipi_reset failed"); -+ rst_gpio = -EINVAL; -+ } -+ } -+ -+ /* request LED(for sanity) pin */ -+ gpio = of_get_named_gpio_flags(dev->of_node, "led-gpios", 0, &flags); -+ if (gpio_is_valid(gpio)) { -+ /* led_active - LED turn on */ -+ /* !led_active - LED trun off */ -+ led_active = !(flags & OF_GPIO_ACTIVE_LOW); -+ init = (flags & OF_GPIO_ACTIVE_LOW) ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW; -+ -+ retval = devm_gpio_request_one(dev, gpio, init, "ov5647_mipi_led"); -+ if (retval < 0) { -+ dev_warn(dev, "request of led_gpio failed"); -+ gpio = -EINVAL; -+ } -+ } -+ -+ /* allocate extended video frame buffer */ -+ extbuf = of_find_property(dev->of_node, "extended-buffer", NULL); -+ -+ /* Set initial values for the sensor struct. */ -+ memset(&ov5647_data, 0, sizeof(ov5647_data)); -+ memset(&ov5647_data_add, 0, sizeof(ov5647_data_add)); -+ -+ sensor->mipi_camera = 1; -+ ov5647_data.sensor_clk = devm_clk_get(dev, "csi_mclk"); -+ if (IS_ERR(ov5647_data.sensor_clk)) { -+ /* assuming clock enabled by default */ -+ ov5647_data.sensor_clk = NULL; -+ dev_err(dev, "clock-frequency missing or invalid\n"); -+ return PTR_ERR(ov5647_data.sensor_clk); -+ } -+ -+ retval = of_property_read_u32(dev->of_node, "mclk", -+ &(ov5647_data.mclk)); -+ if (retval) { -+ dev_err(dev, "mclk missing or invalid\n"); -+ return retval; -+ } -+ -+ retval = of_property_read_u32(dev->of_node, "mclk_source", -+ (u32 *) &(ov5647_data.mclk_source)); -+ if (retval) { -+ dev_err(dev, "mclk_source missing or invalid\n"); -+ return retval; -+ } -+ -+ retval = of_property_read_u32(dev->of_node, "ipu_id", -+ &sensor->ipu_id); -+ if (retval) { -+ dev_err(dev, "ipu_id missing or invalid\n"); -+ return retval; -+ } -+ -+ retval = of_property_read_u32(dev->of_node, "csi_id", -+ &(ov5647_data.csi)); -+ if (retval) { -+ dev_err(dev, "csi id missing or invalid\n"); -+ return retval; -+ } -+ -+ clk_prepare_enable(ov5647_data.sensor_clk); -+ -+ ov5647_data.io_init = ov5647_reset; -+ ov5647_data.i2c_client = client; -+ /* real OV5647 pixelformat is V4L2_PIX_FMT_SBGGR10. */ -+ /* i.MX6 CSI CPD convert 10 bits color data to 8 bits. */ -+ /* (see drivers/mxc/ipu3/ipu_capture.c - _ipu_csi_init) */ -+ ov5647_data.pix.pixelformat = V4L2_PIX_FMT_SBGGR8; -+ ov5647_data.pix.width = 1024; -+ ov5647_data.pix.height = 768; -+ ov5647_data.streamcap.capability = V4L2_MODE_HIGHQUALITY | -+ V4L2_CAP_TIMEPERFRAME; -+ ov5647_data.streamcap.capturemode = ov5647_mode_XGA_1024_768; -+ ov5647_data.streamcap.timeperframe.denominator = DEFAULT_FPS; -+ ov5647_data.streamcap.timeperframe.numerator = 1; -+ -+ /* lager memory allocate for Vivante direct texture mapping API */ -+ /* (VIDIOC_REQBUFS ioctl) */ -+ ov5647_data_add.map_sizeimage = -+ ov5647_data.pix.width * ov5647_data.pix.height * 3 / 2; /* I420 */ -+ -+ if (extbuf) { -+ ov5647_data.adata = &ov5647_data_add; -+ } -+ -+ ov5647_power_on(dev); -+ -+ ov5647_reset(); -+ -+ ov5647_standby(0); -+ -+ retval = ov5647_read_reg(OV5647_CHIP_ID_HIGH_BYTE, &chip_id_high); -+ if (retval < 0 || chip_id_high != 0x56) { -+ pr_warning("camera ov5647_mipi is not found\n"); -+ clk_disable_unprepare(ov5647_data.sensor_clk); -+ return -ENODEV; -+ } -+ retval = ov5647_read_reg(OV5647_CHIP_ID_LOW_BYTE, &chip_id_low); -+ if (retval < 0 || chip_id_low != 0x47) { -+ pr_warning("camera ov5647_mipi is not found\n"); -+ clk_disable_unprepare(ov5647_data.sensor_clk); -+ return -ENODEV; -+ } -+ -+ sensor->virtual_channel = sensor->csi | (sensor->ipu_id << 1); -+ ov5647_standby(1); -+ -+ led_gpio = gpio; -+ ov5647_int_device.priv = &ov5647_data; -+ retval = v4l2_int_device_register(&ov5647_int_device); -+ -+// clk_disable_unprepare(ov5647_data.sensor_clk); -+ -+ if (device_create_file(dev, &dev_attr_ov5647_reg)) -+ dev_err(dev, "%s: error creating ov5647_reg entry\n", __func__); -+ if (device_create_file(dev, &dev_attr_ov5647_mode)) -+ dev_err(dev, "%s: error creating ov5647_mode entry\n", __func__); -+ -+ pr_info("camera ov5647_mipi is found\n"); -+ return retval; -+} -+ -+/*! -+ * ov5647 I2C detach function -+ * -+ * @param client struct i2c_client * -+ * @return Error code indicating success or failure -+ */ -+static int ov5647_remove(struct i2c_client *client) -+{ -+ v4l2_int_device_unregister(&ov5647_int_device); -+ -+ if (gpo_regulator) -+ regulator_disable(gpo_regulator); -+ -+ if (analog_regulator) -+ regulator_disable(analog_regulator); -+ -+ if (core_regulator) -+ regulator_disable(core_regulator); -+ -+ if (io_regulator) -+ regulator_disable(io_regulator); -+ -+ return 0; -+} -+ -+/*! -+ * ov5647 init function -+ * Called by insmod ov5647_camera.ko. -+ * -+ * @return Error code indicating success or failure -+ */ -+static __init int ov5647_init(void) -+{ -+ u8 err; -+ -+ err = i2c_add_driver(&ov5647_i2c_driver); -+ if (err != 0) -+ pr_err("%s:driver registration failed, error=%d\n", -+ __func__, err); -+ -+ return err; -+} -+ -+/*! -+ * OV5647 cleanup function -+ * Called on rmmod ov5647_camera.ko -+ * -+ * @return Error code indicating success or failure -+ */ -+static void __exit ov5647_clean(void) -+{ -+ i2c_del_driver(&ov5647_i2c_driver); -+} -+ -+module_init(ov5647_init); -+module_exit(ov5647_clean); -+ -+MODULE_AUTHOR("Viion Systems Inc."); -+MODULE_DESCRIPTION("OV5647 MIPI Camera Driver"); -+MODULE_LICENSE("GPL"); -+MODULE_VERSION("1.0"); -+MODULE_ALIAS("CSI"); -diff -Nur linux-4.1.13.orig/drivers/media/platform/mxc/capture/tc358743_h2c.c linux-4.1.13/drivers/media/platform/mxc/capture/tc358743_h2c.c ---- linux-4.1.13.orig/drivers/media/platform/mxc/capture/tc358743_h2c.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/media/platform/mxc/capture/tc358743_h2c.c 2015-11-30 17:56:13.616135330 +0100 -@@ -0,0 +1,3674 @@ -+/* -+ * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. -+ * Copyright (C) 2014 Boundary Devices -+ */ -+ -+/* -+ * Modifyed by: Edison Fernández -+ * Added support to use it with Nitrogen6x -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "v4l2-int-device.h" -+#include -+#include -+#include -+#include -+#include -+#include -+//#include -+#include -+#include "mxc_v4l2_capture.h" -+ -+#define CODEC_CLOCK 16500000 -+/* SSI clock sources */ -+#define IMX_SSP_SYS_CLK 0 -+ -+#define MIN_FPS 30 -+#define MAX_FPS 60 -+#define DEFAULT_FPS 60 -+ -+#define TC358743_XCLK_MIN 27000000 -+#define TC358743_XCLK_MAX 42000000 -+ -+#define TC358743_CHIP_ID_HIGH_BYTE 0x0 -+#define TC358743_CHIP_ID_LOW_BYTE 0x0 -+#define TC3587430_HDMI_DETECT 0x0f //0x10 -+ -+#define TC_VOLTAGE_DIGITAL_IO 1800000 -+#define TC_VOLTAGE_DIGITAL_CORE 1500000 -+#define TC_VOLTAGE_DIGITAL_GPO 1500000 -+#define TC_VOLTAGE_ANALOG 2800000 -+ -+#define MAX_COLORBAR tc358743_mode_INIT6 -+#define IS_COLORBAR(a) (a <= MAX_COLORBAR) -+ -+enum tc358743_mode { -+ tc358743_mode_INIT, -+ tc358743_mode_INIT1, -+ tc358743_mode_INIT2, -+ tc358743_mode_INIT3, -+ tc358743_mode_INIT4, -+ tc358743_mode_INIT5, -+ tc358743_mode_INIT6, -+ tc358743_mode_480P_720_480, -+ tc358743_mode_720P_60_1280_720, -+ tc358743_mode_480P_640_480, -+ tc358743_mode_1080P_1920_1080, -+ tc358743_mode_720P_1280_720, -+ tc358743_mode_1024x768, -+ tc358743_mode_MAX, -+}; -+ -+enum tc358743_frame_rate { -+ tc358743_60_fps, -+ tc358743_30_fps, -+ tc358743_max_fps -+}; -+ -+struct reg_value { -+ u16 u16RegAddr; -+ u32 u32Val; -+ u32 u32Mask; -+ u8 u8Length; -+ u32 u32Delay_ms; -+}; -+ -+struct tc358743_mode_info { -+ const char *name; -+ enum tc358743_mode mode; -+ u32 width; -+ u32 height; -+ u32 vformat; -+ u32 fps; -+ u32 lanes; -+ u32 freq; -+ const struct reg_value *init_data_ptr; -+ u32 init_data_size; -+ __u32 flags; -+}; -+ -+/*! -+ * Maintains the information on the current state of the sensor. -+ */ -+struct tc_data { -+ struct sensor_data sensor; -+ struct delayed_work det_work; -+ struct mutex access_lock; -+ int det_work_enable; -+ int det_work_timeout; -+ int det_changed; -+#define REGULATOR_IO 0 -+#define REGULATOR_CORE 1 -+#define REGULATOR_GPO 2 -+#define REGULATOR_ANALOG 3 -+#define REGULATOR_CNT 4 -+ struct regulator *regulator[REGULATOR_CNT]; -+#ifdef CONFIG_TC358743_AUDIO -+ struct platform_device *snd_device; -+#endif -+ u32 lock; -+ u32 bounce; -+ enum tc358743_mode mode; -+ u32 fps; -+ u32 audio; -+ int pwn_gpio; -+ int rst_gpio; -+ u16 hpd_active; -+ int edid_initialized; -+}; -+ -+static struct tc_data *g_td; -+ -+ -+#define DET_WORK_TIMEOUT_DEFAULT 100 -+#define DET_WORK_TIMEOUT_DEFERRED 2000 -+#define MAX_BOUNCE 5 -+ -+static void tc_standby(struct tc_data *td, s32 standby) -+{ -+ if (gpio_is_valid(td->pwn_gpio)) -+ gpio_set_value(td->pwn_gpio, standby ? 1 : 0); -+ pr_debug("tc_standby: powerdown=%x, power_gp=0x%x\n", standby, td->pwn_gpio); -+ msleep(2); -+} -+ -+static void tc_reset(struct tc_data *td) -+{ -+ /* camera reset */ -+ gpio_set_value(td->rst_gpio, 1); -+ -+ /* camera power dowmn */ -+ if (gpio_is_valid(td->pwn_gpio)) { -+ gpio_set_value(td->pwn_gpio, 1); -+ msleep(5); -+ -+ gpio_set_value(td->pwn_gpio, 0); -+ } -+ msleep(5); -+ -+ gpio_set_value(td->rst_gpio, 0); -+ msleep(1); -+ -+ gpio_set_value(td->rst_gpio, 1); -+ msleep(20); -+ -+ if (gpio_is_valid(td->pwn_gpio)) -+ gpio_set_value(td->pwn_gpio, 1); -+} -+ -+static void tc_io_init(void) -+{ -+ return tc_reset(g_td); -+} -+ -+const char * const sregulator[REGULATOR_CNT] = { -+ [REGULATOR_IO] = "DOVDD", -+ [REGULATOR_CORE] = "DVDD", -+ [REGULATOR_GPO] = "DGPO", -+ [REGULATOR_ANALOG] = "AVDD", -+}; -+ -+static const int voltages[REGULATOR_CNT] = { -+ [REGULATOR_IO] = TC_VOLTAGE_DIGITAL_IO, -+ [REGULATOR_CORE] = TC_VOLTAGE_DIGITAL_CORE, -+ [REGULATOR_GPO] = TC_VOLTAGE_DIGITAL_GPO, -+ [REGULATOR_ANALOG] = TC_VOLTAGE_ANALOG, -+}; -+ -+static int tc_regulator_init(struct tc_data *td, struct device *dev) -+{ -+ int i; -+ int ret = 0; -+ -+ for (i = 0; i < REGULATOR_CNT; i++) { -+ td->regulator[i] = devm_regulator_get(dev, sregulator[i]); -+ if (!IS_ERR(td->regulator[i])) { -+ regulator_set_voltage(td->regulator[i], -+ voltages[i], voltages[i]); -+ } else { -+ pr_err("%s:%s devm_regulator_get failed\n", __func__, sregulator[i]); -+ td->regulator[i] = NULL; -+ } -+ } -+ return ret; -+} -+ -+static void det_work_enable(struct tc_data *td, int enable) -+{ -+ td->det_work_enable = enable; -+ td->det_work_timeout = DET_WORK_TIMEOUT_DEFERRED; -+ if (enable) -+ schedule_delayed_work(&td->det_work, msecs_to_jiffies(10)); -+ pr_debug("%s: %d %d\n", __func__, td->det_work_enable, td->det_work_timeout); -+} -+ -+static const u8 cHDMIEDID[256] = { -+ /* FIXME! This is the edid that my ASUS HDMI monitor returns */ -+ 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, //0 - header[8] - fixed pattern -+ 0x04, 0x69, //8 - manufacturer_name[2] -+ 0xf3, 0x24, //10 - product_code[2] -+ 0xd6, 0x12, 0x00, 0x00, //12 - serial_number[4] -+ 0x16, //16 - week -+ 0x16, //17 - year 22+1990=2012 -+ 0x01, //18 - version -+ 0x03, //19 - revision -+ 0x80, //20 - video_input_definition(digital input) -+ 0x34, //21 - max_size_horizontal 52cm -+ 0x1d, //22 - max_size_vertical 29cm -+ 0x78, //23 - gamma -+ 0x3a, //24 - feature_support (RGB 4:4:4 + YCrCb 4:4:4 + YCrCb 4:2:2) -+ 0xc7, 0x20, 0xa4, 0x55, 0x49, 0x99, 0x27, 0x13, 0x50, 0x54, //25 - color_characteristics[10] -+ 0xbf, 0xef, 0x00, //35 - established_timings[3] -+ 0x71, 0x4f, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 0xb3, 0x00, 0xd1, 0xc0, 0x01, 0x01, 0x01, 0x01, //38 - standard_timings[8] -+/* 1080P */ -+ 0x02, 0x3a, //54(0) - descriptor[0], 0x3a02 = 148.50 MHz -+ 0x80, //56(2) h - active 0x780 (1920) -+ 0x18, //57(3) h - blank 0x118 (280) -+ 0x71, //58(4) -+ 0x38, //59(5) v - active 0x438 (1080) -+ 0x2d, //60(6) v - blank 0x02d(45) -+ 0x40, //61(7) -+ 0x58, //62(8) - h sync offset(0x58) -+ 0x2c, //63(9) - h sync width(0x2c) -+ 0x45, //64(10) - v sync offset(0x4), v sync width(0x5) -+ 0x00, //65(11) -+ 0x09, //66(12) - h display size (0x209) 521 mm -+ 0x25, //67(13) - v display size (0x125) 293 mm -+ 0x21, //68(14) -+ 0x00, //69(15) - h border pixels -+ 0x00, //70(16) - v border pixels -+ 0x1e, //71(17) - no stereo, digital separate, hsync+, vsync+ -+ 0x00, 0x00, 0x00, 0xff, 0x00, //72 - descriptor[1] -+ 0x43, 0x36, 0x4c, 0x4d, 0x54, 0x46, 0x30, 0x30, 0x34, 0x38, 0x32, 0x32, 0x0a, //"C6LMTF004822\n" -+ 0x00, 0x00, 0x00, 0xfd, 0x00, //90 - descriptor[2] -+ 0x37, 0x4b, 0x1e, 0x55, 0x10, 0x00, 0x0a, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, -+ 0x00, 0x00, 0x00, 0xfc, 0x00, //108 - descriptor[3] -+ 0x41, 0x53, 0x55, 0x53, 0x20, 0x56, 0x48, 0x32, 0x34, 0x32, 0x48, 0x0a, 0x20, //"ASUS VH242H\n " -+ 0x01, //126 - extension_flag -+ 0x68, //127 - checksum -+ -+ 0x02, //0 - cea-861 extension -+ 0x03, //1 - rev 3 -+ 0x22, //2 - detailed timings at offset 34 -+ 0x71, //3 - # of detailed timing descriptor -+ 0x4f, 0x01, 0x02, 0x03, 0x11, 0x12, //4 -+ 0x13, 0x04, 0x14, 0x05, 0x0e, 0x0f, //10 -+ 0x1d, 0x1e, 0x1f, 0x10, 0x23, 0x09, //16 -+ 0x07, 0x01, 0x83, 0x01, 0x00, 0x00, //22 -+ 0x65, 0x03, 0x0c, 0x00, 0x10, 0x00, //28 -+/* 720x480@59.94 27000000/858/525 = 59.94 Hz */ -+ 0x8c, 0x0a, //34 - descriptor[0] - 0x0a8c - 27 Mhz -+ 0xd0, //h - active 0x2d0 (720) -+ 0x8a, //h - blank 0x8a(138) -+ 0x20, -+ 0xe0, //v - active 0x1e0 (480) -+ 0x2d, //v - blank 0x2d (45) -+ 0x10, -+ 0x10, 0x3e, 0x96, 0x00, 0x09, 0x25, 0x21, 0x00, 0x00, 0x18, -+/* 1280x720@60 74250000/1650/750 = 60 Hz*/ -+ 0x01, 0x1d, //52 - 0x1d01 74.25MHz -+ 0x00, //h - active (0x500)1280 -+ 0x72, //h - blank (0x172)370 -+ 0x51, -+ 0xd0, //v active 0x2d0(720) -+ 0x1e, //v blank 0x1e(30) -+ 0x20, -+ 0x6e, 0x28, 0x55, 0x00, 0x09, 0x25, 0x21, 0x00, 0x00, 0x1e, -+/* 1280x720@50 74250000/1980/750 = 50 Hz */ -+ 0x01, 0x1d, //70 - 0x1d01 74.25MHz -+ 0x00, //h - active (0x500)1280 -+ 0xbc, //h - blank (0x2bc)700 -+ 0x52, -+ 0xd0, //v active 0x2d0 (720) -+ 0x1e, //v blank 0x1e(30) -+ 0x20, -+ 0xb8, 0x28, 0x55, 0x40, 0x09, 0x25, 0x21, 0x00, 0x00, 0x1e, -+/* 720x576@50 27000000/864/625 = 50 Hz */ -+ 0x8c, 0x0a, //88 0x0a8c - 27 Mhz -+ 0xd0, //h - active 0x2d0(720) -+ 0x90, //h - blank 0x90(144) -+ 0x20, -+ 0x40, //v active 0x240(576) -+ 0x31, //v blanking 0x31(49) -+ 0x20, -+ 0x0c, 0x40, 0x55, 0x00, 0x09, 0x25, 0x21, 0x00, 0x00, 0x18, -+/* done */ -+ 0x00, 0x00, 0x00, 0x00, 0x00, //106 -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, //124 -+ 0x00, //126 - extension_flag -+ 0x73, //127 - checksum -+}; -+ -+static const struct reg_value tc358743_setting_YUV422_2lane_30fps_720P_1280_720_125MHz[] = { -+ {0x0006, 0x00000040, 0x00000000, 2, 0}, -+ {0x0014, 0x00000000, 0x00000000, 2, 0}, -+ {0x0016, 0x000005ff, 0x00000000, 2, 0}, -+// Program CSI Tx PLL -+ {0x0020, 0x0000402d, 0x00000000, 2, 0}, -+ {0x0022, 0x00000213, 0x00000000, 2, 0}, -+// CSI Tx PHY (32-bit Registers) -+ {0x0140, 0x00000000, 0x00000000, 4, 0}, -+ {0x0144, 0x00000000, 0x00000000, 4, 0}, -+ {0x0148, 0x00000000, 0x00000000, 4, 0}, -+ {0x014c, 0x00000000, 0x00000000, 4, 0}, -+ {0x0150, 0x00000000, 0x00000000, 4, 0}, -+// CSI Tx PPI (32-bit Registers) -+ {0x0210, 0x00000e00, 0x00000000, 4, 0}, -+ {0x0214, 0x00000001, 0x00000000, 4, 0}, -+ {0x0218, 0x00000801, 0x00000000, 4, 0}, -+ {0x021c, 0x00000001, 0x00000000, 4, 0}, -+ {0x0220, 0x00000001, 0x00000000, 4, 0}, -+ {0x0224, 0x00004800, 0x00000000, 4, 0}, -+ {0x0228, 0x00000005, 0x00000000, 4, 0}, -+ {0x022c, 0x00000000, 0x00000000, 4, 0}, -+ {0x0234, 0x0000001f, 0x00000000, 4, 0}, -+ {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock -+ {0x0204, 0x00000001, 0x00000000, 4, 0}, -+ {0x0518, 0x00000001, 0x00000000, 4, 0}, -+ {0x0500, 0xa300be82, 0x00000000, 4, 0}, -+// HDMI Interrupt Mask -+ {0x8502, 0x00000001, 0x00000000, 1, 0}, -+ {0x8512, 0x000000fe, 0x00000000, 1, 0}, -+ {0x8514, 0x00000000, 0x00000000, 1, 0}, -+ {0x8515, 0x00000000, 0x00000000, 1, 0}, -+ {0x8516, 0x00000000, 0x00000000, 1, 0}, -+// HDMI Audio -+ {0x8531, 0x00000001, 0x00000000, 1, 0}, -+ {0x8630, 0x000000b0, 0x00000000, 1, 0}, -+ {0x8631, 0x0000001e, 0x00000000, 1, 0}, -+ {0x8632, 0x00000004, 0x00000000, 1, 0}, -+ {0x8670, 0x00000001, 0x00000000, 1, 0}, -+// HDMI PHY -+ {0x8532, 0x00000080, 0x00000000, 1, 0}, -+ {0x8536, 0x00000040, 0x00000000, 1, 0}, -+ {0x853f, 0x0000000a, 0x00000000, 1, 0}, -+// HDMI System -+ {0x8545, 0x00000031, 0x00000000, 1, 0}, -+ {0x8546, 0x0000002d, 0x00000000, 1, 0}, -+// HDCP Setting -+ {0x85d1, 0x00000001, 0x00000000, 1, 0}, -+ {0x8560, 0x00000024, 0x00000000, 1, 0}, -+ {0x8563, 0x00000011, 0x00000000, 1, 0}, -+ {0x8564, 0x0000000f, 0x00000000, 1, 0}, -+// Video settings -+ {0x8573, 0x00000081, 0x00000000, 1, 0}, -+ {0x8571, 0x00000002, 0x00000000, 1, 0}, -+// HDMI Audio In Setting -+ {0x8600, 0x00000000, 0x00000000, 1, 0}, -+ {0x8602, 0x000000f3, 0x00000000, 1, 0}, -+ {0x8603, 0x00000002, 0x00000000, 1, 0}, -+ {0x8604, 0x0000000c, 0x00000000, 1, 0}, -+ {0x8606, 0x00000005, 0x00000000, 1, 0}, -+ {0x8607, 0x00000000, 0x00000000, 1, 0}, -+ {0x8620, 0x00000022, 0x00000000, 1, 0}, -+ {0x8640, 0x00000001, 0x00000000, 1, 0}, -+ {0x8641, 0x00000065, 0x00000000, 1, 0}, -+ {0x8642, 0x00000007, 0x00000000, 1, 0}, -+// {0x8651, 0x00000003, 0x00000000, 1, 0}, // Inverted LRCK polarity - (Sony) format -+ {0x8652, 0x00000002, 0x00000000, 1, 0}, // Left-justified I2S (Phillips) format -+// {0x8652, 0x00000000, 0x00000000, 1, 0}, // Right-justified (Sony) format -+ {0x8665, 0x00000010, 0x00000000, 1, 0}, -+// InfoFrame Extraction -+ {0x8709, 0x000000ff, 0x00000000, 1, 0}, -+ {0x870b, 0x0000002c, 0x00000000, 1, 0}, -+ {0x870c, 0x00000053, 0x00000000, 1, 0}, -+ {0x870d, 0x00000001, 0x00000000, 1, 0}, -+ {0x870e, 0x00000030, 0x00000000, 1, 0}, -+ {0x9007, 0x00000010, 0x00000000, 1, 0}, -+ {0x854a, 0x00000001, 0x00000000, 1, 0}, -+// Output Control -+ {0x0004, 0x00000cf7, 0x00000000, 2, 0}, -+ }; -+ -+static const struct reg_value tc358743_setting_YUV422_4lane_1024x768_60fps_125MHz[] = { -+ {0x0006, 0x00000000, 0x00000000, 2, 0}, -+ {0x0014, 0x0000ffff, 0x00000000, 2, 0}, -+ {0x0016, 0x000005ff, 0x00000000, 2, 0}, -+// Program CSI Tx PLL -+ {0x0020, 0x0000405c, 0x00000000, 2, 0}, /* Input divide 5(4+1), Feedback divide 92(0x5c+1)*/ -+ {0x0022, 0x00000613, 0x00000000, 2, 0}, -+// CSI Tx PHY (32-bit Registers) -+ {0x0140, 0x00000000, 0x00000000, 4, 0}, -+ {0x0144, 0x00000000, 0x00000000, 4, 0}, -+ {0x0148, 0x00000000, 0x00000000, 4, 0}, -+ {0x014c, 0x00000000, 0x00000000, 4, 0}, -+ {0x0150, 0x00000000, 0x00000000, 4, 0}, -+// CSI Tx PPI (32-bit Registers) -+ {0x0210, 0x00000d00, 0x00000000, 4, 0}, -+ {0x0214, 0x00000001, 0x00000000, 4, 0}, -+ {0x0218, 0x00000701, 0x00000000, 4, 0}, -+ {0x021c, 0x00000000, 0x00000000, 4, 0}, -+ {0x0220, 0x00000001, 0x00000000, 4, 0}, -+ {0x0224, 0x00004000, 0x00000000, 4, 0}, -+ {0x0228, 0x00000005, 0x00000000, 4, 0}, -+ {0x022c, 0x00000000, 0x00000000, 4, 0}, -+ {0x0234, 0x0000001f, 0x00000000, 4, 0}, -+ {0x0238, 0x00000001, 0x00000000, 4, 0}, -+ {0x0204, 0x00000001, 0x00000000, 4, 0}, -+ {0x0518, 0x00000001, 0x00000000, 4, 0}, -+ {0x0500, 0xa300be86, 0x00000000, 4, 0}, -+// HDMI Interrupt Mask -+ {0x8502, 0x00000001, 0x00000000, 1, 0}, -+ {0x8512, 0x000000fe, 0x00000000, 1, 0}, -+ {0x8514, 0x00000000, 0x00000000, 1, 0}, -+ {0x8515, 0x00000000, 0x00000000, 1, 0}, -+ {0x8516, 0x00000000, 0x00000000, 1, 0}, -+// HDMI Audio -+ {0x8531, 0x00000001, 0x00000000, 1, 0}, -+ {0x8630, 0x00041eb0, 0x00000000, 1, 0}, -+ {0x8670, 0x00000001, 0x00000000, 1, 0}, -+// HDMI PHY -+ {0x8532, 0x00000080, 0x00000000, 1, 0}, -+ {0x8536, 0x00000040, 0x00000000, 1, 0}, -+ {0x853f, 0x0000000a, 0x00000000, 1, 0}, -+// HDMI System -+ {0x8545, 0x00000031, 0x00000000, 1, 0}, -+ {0x8546, 0x0000002d, 0x00000000, 1, 0}, -+// HDCP Setting -+ {0x85d1, 0x00000001, 0x00000000, 1, 0}, -+ {0x8560, 0x00000024, 0x00000000, 1, 0}, -+ {0x8563, 0x00000011, 0x00000000, 1, 0}, -+ {0x8564, 0x0000000f, 0x00000000, 1, 0}, -+// RGB --> YUV Conversion -+// {0x8574, 0x00000000, 0x00000000, 1, 0}, -+ {0x8573, 0x00000081, 0x00000000, 1, 0}, -+ {0x8571, 0x00000002, 0x00000000, 1, 0}, -+// HDMI Audio In Setting -+ {0x8600, 0x00000000, 0x00000000, 1, 0}, -+ {0x8602, 0x000000f3, 0x00000000, 1, 0}, -+ {0x8603, 0x00000002, 0x00000000, 1, 0}, -+ {0x8604, 0x0000000c, 0x00000000, 1, 0}, -+ {0x8606, 0x00000005, 0x00000000, 1, 0}, -+ {0x8607, 0x00000000, 0x00000000, 1, 0}, -+ {0x8620, 0x00000022, 0x00000000, 1, 0}, -+ {0x8640, 0x00000001, 0x00000000, 1, 0}, -+ {0x8641, 0x00000065, 0x00000000, 1, 0}, -+ {0x8642, 0x00000007, 0x00000000, 1, 0}, -+ {0x8652, 0x00000002, 0x00000000, 1, 0}, -+ {0x8665, 0x00000010, 0x00000000, 1, 0}, -+// InfoFrame Extraction -+ {0x8709, 0x000000ff, 0x00000000, 1, 0}, -+ {0x870b, 0x0000002c, 0x00000000, 1, 0}, -+ {0x870c, 0x00000053, 0x00000000, 1, 0}, -+ {0x870d, 0x00000001, 0x00000000, 1, 0}, -+ {0x870e, 0x00000030, 0x00000000, 1, 0}, -+ {0x9007, 0x00000010, 0x00000000, 1, 0}, -+ {0x854a, 0x00000001, 0x00000000, 1, 0}, -+// Output Control -+ {0x0004, 0x00000cf7, 0x00000000, 2, 0}, -+ -+}; -+ -+static const struct reg_value tc358743_setting_YUV422_4lane_720P_60fps_1280_720_133Mhz[] = { -+ {0x0006, 0x00000000, 0x00000000, 2, 0}, -+ {0x0014, 0x0000ffff, 0x00000000, 2, 0}, -+ {0x0016, 0x000005ff, 0x00000000, 2, 0}, -+// Program CSI Tx PLL -+ {0x0020, 0x00004062, 0x00000000, 2, 0}, -+ {0x0022, 0x00000613, 0x00000000, 2, 0}, -+// CSI Tx PHY (32-bit Registers) -+ {0x0140, 0x00000000, 0x00000000, 4, 0}, -+ {0x0144, 0x00000000, 0x00000000, 4, 0}, -+ {0x0148, 0x00000000, 0x00000000, 4, 0}, -+ {0x014c, 0x00000000, 0x00000000, 4, 0}, -+ {0x0150, 0x00000000, 0x00000000, 4, 0}, -+// CSI Tx PPI (32-bit Registers) -+ {0x0210, 0x00000d00, 0x00000000, 4, 0}, -+ {0x0214, 0x00000001, 0x00000000, 4, 0}, -+ {0x0218, 0x00000701, 0x00000000, 4, 0}, -+ {0x021c, 0x00000000, 0x00000000, 4, 0}, -+ {0x0220, 0x00000001, 0x00000000, 4, 0}, -+ {0x0224, 0x00004000, 0x00000000, 4, 0}, -+ {0x0228, 0x00000005, 0x00000000, 4, 0}, -+ {0x022c, 0x00000000, 0x00000000, 4, 0}, -+ {0x0234, 0x0000001f, 0x00000000, 4, 0}, -+ {0x0238, 0x00000001, 0x00000000, 4, 0}, -+ {0x0204, 0x00000001, 0x00000000, 4, 0}, -+ {0x0518, 0x00000001, 0x00000000, 4, 0}, -+ {0x0500, 0xa300be86, 0x00000000, 4, 0}, -+// HDMI Interrupt Mask -+ {0x8502, 0x00000001, 0x00000000, 1, 0}, -+ {0x8512, 0x000000fe, 0x00000000, 1, 0}, -+ {0x8514, 0x00000000, 0x00000000, 1, 0}, -+ {0x8515, 0x00000000, 0x00000000, 1, 0}, -+ {0x8516, 0x00000000, 0x00000000, 1, 0}, -+// HDMI Audio -+ {0x8531, 0x00000001, 0x00000000, 1, 0}, -+ {0x8630, 0x00041eb0, 0x00000000, 1, 0}, -+ {0x8670, 0x00000001, 0x00000000, 1, 0}, -+// HDMI PHY -+ {0x8532, 0x00000080, 0x00000000, 1, 0}, -+ {0x8536, 0x00000040, 0x00000000, 1, 0}, -+ {0x853f, 0x0000000a, 0x00000000, 1, 0}, -+// HDMI System -+ {0x8545, 0x00000031, 0x00000000, 1, 0}, -+ {0x8546, 0x0000002d, 0x00000000, 1, 0}, -+// HDCP Setting -+ {0x85d1, 0x00000001, 0x00000000, 1, 0}, -+ {0x8560, 0x00000024, 0x00000000, 1, 0}, -+ {0x8563, 0x00000011, 0x00000000, 1, 0}, -+ {0x8564, 0x0000000f, 0x00000000, 1, 0}, -+// RGB --> YUV Conversion -+// {0x8574, 0x00000000, 0x00000000, 1, 0}, -+ {0x8573, 0x00000081, 0x00000000, 1, 0}, -+ {0x8571, 0x00000002, 0x00000000, 1, 0}, -+// HDMI Audio In Setting -+ {0x8600, 0x00000000, 0x00000000, 1, 0}, -+ {0x8602, 0x000000f3, 0x00000000, 1, 0}, -+ {0x8603, 0x00000002, 0x00000000, 1, 0}, -+ {0x8604, 0x0000000c, 0x00000000, 1, 0}, -+ {0x8606, 0x00000005, 0x00000000, 1, 0}, -+ {0x8607, 0x00000000, 0x00000000, 1, 0}, -+ {0x8620, 0x00000022, 0x00000000, 1, 0}, -+ {0x8640, 0x00000001, 0x00000000, 1, 0}, -+ {0x8641, 0x00000065, 0x00000000, 1, 0}, -+ {0x8642, 0x00000007, 0x00000000, 1, 0}, -+ {0x8652, 0x00000002, 0x00000000, 1, 0}, -+ {0x8665, 0x00000010, 0x00000000, 1, 0}, -+// InfoFrame Extraction -+ {0x8709, 0x000000ff, 0x00000000, 1, 0}, -+ {0x870b, 0x0000002c, 0x00000000, 1, 0}, -+ {0x870c, 0x00000053, 0x00000000, 1, 0}, -+ {0x870d, 0x00000001, 0x00000000, 1, 0}, -+ {0x870e, 0x00000030, 0x00000000, 1, 0}, -+ {0x9007, 0x00000010, 0x00000000, 1, 0}, -+ {0x854a, 0x00000001, 0x00000000, 1, 0}, -+// Output Control -+ {0x0004, 0x00000cf7, 0x00000000, 2, 0}, -+}; -+ -+static const struct reg_value tc358743_setting_YUV422_2lane_color_bar_1280_720_125MHz[] = { -+ {0x0006, 0x00000000, 0x00000000, 2, 0}, -+ {0x0004, 0x00000084, 0x00000000, 2, 0}, -+ {0x0010, 0x0000001e, 0x00000000, 2, 0}, -+// Program CSI Tx PLL -+ {0x0020, 0x0000405c, 0x00000000, 2, 0}, -+ {0x0022, 0x00000613, 0x00000000, 2, 0}, -+// CSI Tx PHY (32-bit Registers) -+ {0x0140, 0x00000000, 0x00000000, 4, 0}, -+ {0x0144, 0x00000000, 0x00000000, 4, 0}, -+ {0x0148, 0x00000000, 0x00000000, 4, 0}, -+ {0x014c, 0x00000000, 0x00000000, 4, 0}, -+ {0x0150, 0x00000000, 0x00000000, 4, 0}, -+// CSI Tx PPI (32-bit Registers) -+ {0x0210, 0x00000e00, 0x00000000, 4, 0}, -+ {0x0214, 0x00000001, 0x00000000, 4, 0}, -+ {0x0218, 0x00000801, 0x00000000, 4, 0}, -+ {0x021c, 0x00000000, 0x00000000, 4, 0}, -+ {0x0220, 0x00000001, 0x00000000, 4, 0}, -+ {0x0224, 0x00004000, 0x00000000, 4, 0}, -+ {0x0228, 0x00000006, 0x00000000, 4, 0}, -+ {0x022c, 0x00000000, 0x00000000, 4, 0}, -+ {0x0234, 0x00000007, 0x00000000, 4, 0}, -+ {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock -+ {0x0204, 0x00000001, 0x00000000, 4, 0}, -+ {0x0518, 0x00000001, 0x00000000, 4, 0}, -+ {0x0500, 0xa30080a2, 0x00000000, 4, 0}, -+// 1280x720 colorbar -+ {0x000a, 0x00000a00, 0x00000000, 2, 0}, -+ {0x7080, 0x00000082, 0x00000000, 2, 0}, -+// 128 pixel black - repeat 128 times -+ {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(128<<16)}, -+// 128 pixel blue - repeat 64 times -+ {0x7000, 0x000000ff, 0x00000000, 2, 0}, -+ {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 128 pixel red - repeat 64 times -+ {0x7000, 0x00000000, 0x00000000, 2, 0}, -+ {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 128 pixel pink - repeat 64 times -+ {0x7000, 0x00007fff, 0x00000000, 2, 0}, -+ {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 128 pixel green - repeat 64 times -+ {0x7000, 0x00007f00, 0x00000000, 2, 0}, -+ {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 128 pixel light blue - repeat 64 times -+ {0x7000, 0x0000c0ff, 0x00000000, 2, 0}, -+ {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 128 pixel yellow - repeat 64 times -+ {0x7000, 0x0000ff00, 0x00000000, 2, 0}, -+ {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 128 pixel white - repeat 64 times -+ {0x7000, 0x0000ff7f, 0x00000000, 2, 0}, -+ {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 720 lines -+ {0x7090, 0x000002cf, 0x00000000, 2, 0}, -+ {0x7092, 0x00000580, 0x00000000, 2, 0}, -+ {0x7094, 0x00000010, 0x00000000, 2, 0}, -+ {0x7080, 0x00000083, 0x00000000, 2, 0}, -+}; -+ -+static const struct reg_value tc358743_setting_YUV422_4lane_color_bar_1280_720_125MHz[] = { -+ {0x0006, 0x00000000, 0x00000000, 2, 0}, -+ {0x0004, 0x00000084, 0x00000000, 2, 0}, -+ {0x0010, 0x0000001e, 0x00000000, 2, 0}, -+// Program CSI Tx PLL -+ {0x0020, 0x0000405c, 0x00000000, 2, 0}, -+ {0x0022, 0x00000613, 0x00000000, 2, 0}, -+// CSI Tx PHY (32-bit Registers) -+ {0x0140, 0x00000000, 0x00000000, 4, 0}, -+ {0x0144, 0x00000000, 0x00000000, 4, 0}, -+ {0x0148, 0x00000000, 0x00000000, 4, 0}, -+ {0x014c, 0x00000000, 0x00000000, 4, 0}, -+ {0x0150, 0x00000000, 0x00000000, 4, 0}, -+// CSI Tx PPI (32-bit Registers) -+ {0x0210, 0x00000e00, 0x00000000, 4, 0}, -+ {0x0214, 0x00000001, 0x00000000, 4, 0}, -+ {0x0218, 0x00000801, 0x00000000, 4, 0}, -+ {0x021c, 0x00000000, 0x00000000, 4, 0}, -+ {0x0220, 0x00000001, 0x00000000, 4, 0}, -+ {0x0224, 0x00004000, 0x00000000, 4, 0}, -+ {0x0228, 0x00000006, 0x00000000, 4, 0}, -+ {0x022c, 0x00000000, 0x00000000, 4, 0}, -+ {0x0234, 0x0000001F, 0x00000000, 4, 0}, //{0x0234, 0x00000007, 0x00000000, 4, 0}, -+ {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock -+ {0x0204, 0x00000001, 0x00000000, 4, 0}, -+ {0x0518, 0x00000001, 0x00000000, 4, 0}, -+ {0x0500, 0xa30080a6, 0x00000000, 4, 0}, //{0x0500, 0xa30080a2, 0x00000000, 4, 0}, -+// 1280x720 colorbar -+ {0x000a, 0x00000a00, 0x00000000, 2, 0}, -+ {0x7080, 0x00000082, 0x00000000, 2, 0}, -+// 128 pixel black - repeat 128 times -+ {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(128<<16)}, -+// 128 pixel blue - repeat 64 times -+ {0x7000, 0x000000ff, 0x00000000, 2, 0}, -+ {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 128 pixel red - repeat 64 times -+ {0x7000, 0x00000000, 0x00000000, 2, 0}, -+ {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 128 pixel pink - repeat 64 times -+ {0x7000, 0x00007fff, 0x00000000, 2, 0}, -+ {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 128 pixel green - repeat 64 times -+ {0x7000, 0x00007f00, 0x00000000, 2, 0}, -+ {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 128 pixel light blue - repeat 64 times -+ {0x7000, 0x0000c0ff, 0x00000000, 2, 0}, -+ {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 128 pixel yellow - repeat 64 times -+ {0x7000, 0x0000ff00, 0x00000000, 2, 0}, -+ {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 128 pixel white - repeat 64 times -+ {0x7000, 0x0000ff7f, 0x00000000, 2, 0}, -+ {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 720 lines -+ {0x7090, 0x000002cf, 0x00000000, 2, 0}, -+ {0x7092, 0x00000300, 0x00000000, 2, 0}, //{0x7092, 0x00000580, 0x00000000, 2, 0}, -+ {0x7094, 0x00000010, 0x00000000, 2, 0}, -+ {0x7080, 0x00000083, 0x00000000, 2, 0}, -+}; -+ -+ -+static const struct reg_value tc358743_setting_YUV422_4lane_color_bar_1024_720_200MHz[] = { -+ {0x0006, 0x00000000, 0x00000000, 2, 0}, -+ {0x0004, 0x00000084, 0x00000000, 2, 0}, -+ {0x0010, 0x0000001e, 0x00000000, 2, 0}, -+// Program CSI Tx PLL -+ {0x0020, 0x00004050, 0x00000000, 2, 0}, -+ {0x0022, 0x00000213, 0x00000000, 2, 0}, -+// CSI Tx PHY (32-bit Registers) -+ {0x0140, 0x00000000, 0x00000000, 4, 0}, -+ {0x0144, 0x00000000, 0x00000000, 4, 0}, -+ {0x0148, 0x00000000, 0x00000000, 4, 0}, -+ {0x014c, 0x00000000, 0x00000000, 4, 0}, -+ {0x0150, 0x00000000, 0x00000000, 4, 0}, -+// CSI Tx PPI (32-bit Registers) -+ {0x0210, 0x00001800, 0x00000000, 4, 0}, -+ {0x0214, 0x00000002, 0x00000000, 4, 0}, -+ {0x0218, 0x00001102, 0x00000000, 4, 0}, -+ {0x021c, 0x00000000, 0x00000000, 4, 0}, -+ {0x0220, 0x00000003, 0x00000000, 4, 0}, -+ {0x0224, 0x00004000, 0x00000000, 4, 0}, -+ {0x0228, 0x00000007, 0x00000000, 4, 0}, -+ {0x022c, 0x00000001, 0x00000000, 4, 0}, -+ {0x0234, 0x0000001f, 0x00000000, 4, 0}, -+ {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock -+ {0x0204, 0x00000001, 0x00000000, 4, 0}, -+ {0x0518, 0x00000001, 0x00000000, 4, 0}, -+ {0x0500, 0xa30080a6, 0x00000000, 4, 0}, -+// 1280x720 colorbar -+ {0x000a, 0x00000800, 0x00000000, 2, 0}, -+ {0x7080, 0x00000082, 0x00000000, 2, 0}, -+// 128 pixel black - repeat 128 times -+ {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(128<<16)}, -+// 128 pixel blue - repeat 64 times -+ {0x7000, 0x000000ff, 0x00000000, 2, 0}, -+ {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 128 pixel red - repeat 64 times -+ {0x7000, 0x00000000, 0x00000000, 2, 0}, -+ {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 128 pixel pink - repeat 64 times -+ {0x7000, 0x00007fff, 0x00000000, 2, 0}, -+ {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 128 pixel green - repeat 64 times -+ {0x7000, 0x00007f00, 0x00000000, 2, 0}, -+ {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 128 pixel light blue - repeat 64 times -+ {0x7000, 0x0000c0ff, 0x00000000, 2, 0}, -+ {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 128 pixel yellow - repeat 64 times -+ {0x7000, 0x0000ff00, 0x00000000, 2, 0}, -+ {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 128 pixel white - repeat 64 times -+ {0x7000, 0x0000ff7f, 0x00000000, 2, 0}, -+ {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 720 lines -+ {0x0020, 0x0000406f, 0x00000000, 2, 100}, -+ {0x7090, 0x000002cf, 0x00000000, 2, 0}, -+ {0x7092, 0x00000540, 0x00000000, 2, 0}, -+ {0x7094, 0x00000010, 0x00000000, 2, 0}, -+ {0x7080, 0x00000083, 0x00000000, 2, 0}, -+}; -+ -+static const struct reg_value tc358743_setting_YUV422_4lane_color_bar_1280_720_300MHz[] = { -+ {0x0006, 0x00000000, 0x00000000, 2, 0}, -+ {0x0004, 0x00000084, 0x00000000, 2, 0}, -+ {0x0010, 0x0000001e, 0x00000000, 2, 0}, -+// Program CSI Tx PLL -+ {0x0020, 0x000080c7, 0x00000000, 2, 0}, -+ {0x0022, 0x00000213, 0x00000000, 2, 0}, -+// CSI Tx PHY (32-bit Registers) -+ {0x0140, 0x00000000, 0x00000000, 4, 0}, -+ {0x0144, 0x00000000, 0x00000000, 4, 0}, -+ {0x0148, 0x00000000, 0x00000000, 4, 0}, -+ {0x014c, 0x00000000, 0x00000000, 4, 0}, -+ {0x0150, 0x00000000, 0x00000000, 4, 0}, -+// CSI Tx PPI (32-bit Registers) -+ {0x0210, 0x00001e00, 0x00000000, 4, 0}, -+ {0x0214, 0x00000003, 0x00000000, 4, 0}, -+ {0x0218, 0x00001402, 0x00000000, 4, 0}, -+ {0x021c, 0x00000000, 0x00000000, 4, 0}, -+ {0x0220, 0x00000003, 0x00000000, 4, 0}, -+ {0x0224, 0x00004a00, 0x00000000, 4, 0}, -+ {0x0228, 0x00000008, 0x00000000, 4, 0}, -+ {0x022c, 0x00000002, 0x00000000, 4, 0}, -+ {0x0234, 0x0000001f, 0x00000000, 4, 0}, -+ {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock -+ {0x0204, 0x00000001, 0x00000000, 4, 0}, -+ {0x0518, 0x00000001, 0x00000000, 4, 0}, -+ {0x0500, 0xa30080a6, 0x00000000, 4, 0}, -+// 1280x720 colorbar -+ {0x000a, 0x00000a00, 0x00000000, 2, 0}, -+ {0x7080, 0x00000082, 0x00000000, 2, 0}, -+// 128 pixel black - repeat 128 times -+ {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(128<<16)}, -+// 128 pixel blue - repeat 64 times -+ {0x7000, 0x000000ff, 0x00000000, 2, 0}, -+ {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 128 pixel red - repeat 64 times -+ {0x7000, 0x00000000, 0x00000000, 2, 0}, -+ {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 128 pixel pink - repeat 64 times -+ {0x7000, 0x00007fff, 0x00000000, 2, 0}, -+ {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 128 pixel green - repeat 64 times -+ {0x7000, 0x00007f00, 0x00000000, 2, 0}, -+ {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 128 pixel light blue - repeat 64 times -+ {0x7000, 0x0000c0ff, 0x00000000, 2, 0}, -+ {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 128 pixel yellow - repeat 64 times -+ {0x7000, 0x0000ff00, 0x00000000, 2, 0}, -+ {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 128 pixel white - repeat 64 times -+ {0x7000, 0x0000ff7f, 0x00000000, 2, 0}, -+ {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 720 lines -+ {0x7090, 0x000002cf, 0x00000000, 2, 0}, -+ {0x7092, 0x000006b8, 0x00000000, 2, 0}, -+ {0x7094, 0x00000010, 0x00000000, 2, 0}, -+ {0x7080, 0x00000083, 0x00000000, 2, 0}, -+}; -+ -+static const struct reg_value tc358743_setting_YUV422_4lane_color_bar_1920_1023_300MHz[] = { -+ {0x0006, 0x00000000, 0x00000000, 2, 0}, -+ {0x0004, 0x00000084, 0x00000000, 2, 0}, -+ {0x0010, 0x0000001e, 0x00000000, 2, 0}, -+// Program CSI Tx PLL -+ {0x0020, 0x000080c7, 0x00000000, 2, 0}, -+ {0x0022, 0x00000213, 0x00000000, 2, 0}, -+// CSI Tx PHY (32-bit Registers) -+ {0x0140, 0x00000000, 0x00000000, 4, 0}, -+ {0x0144, 0x00000000, 0x00000000, 4, 0}, -+ {0x0148, 0x00000000, 0x00000000, 4, 0}, -+ {0x014c, 0x00000000, 0x00000000, 4, 0}, -+ {0x0150, 0x00000000, 0x00000000, 4, 0}, -+// CSI Tx PPI (32-bit Registers) -+ {0x0210, 0x00001e00, 0x00000000, 4, 0}, -+ {0x0214, 0x00000003, 0x00000000, 4, 0}, -+ {0x0218, 0x00001402, 0x00000000, 4, 0}, -+ {0x021c, 0x00000000, 0x00000000, 4, 0}, -+ {0x0220, 0x00000003, 0x00000000, 4, 0}, -+ {0x0224, 0x00004a00, 0x00000000, 4, 0}, -+ {0x0228, 0x00000008, 0x00000000, 4, 0}, -+ {0x022c, 0x00000002, 0x00000000, 4, 0}, -+ {0x0234, 0x0000001f, 0x00000000, 4, 0}, -+ {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock -+ {0x0204, 0x00000001, 0x00000000, 4, 0}, -+ {0x0518, 0x00000001, 0x00000000, 4, 0}, -+ {0x0500, 0xa30080a6, 0x00000000, 4, 0}, -+// 1920x1023 colorbar -+ {0x000a, 0x00000f00, 0x00000000, 2, 0}, -+ {0x7080, 0x00000082, 0x00000000, 2, 0}, -+// 128 pixel black - repeat 128 times -+ {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(128<<16)}, -+// 128 pixel blue - repeat 64 times -+ {0x7000, 0x000000ff, 0x00000000, 2, 0}, -+ {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 128 pixel red - repeat 64 times -+ {0x7000, 0x00000000, 0x00000000, 2, 0}, -+ {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 128 pixel pink - repeat 64 times -+ {0x7000, 0x00007fff, 0x00000000, 2, 0}, -+ {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 128 pixel green - repeat 64 times -+ {0x7000, 0x00007f00, 0x00000000, 2, 0}, -+ {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 128 pixel light blue - repeat 64 times -+ {0x7000, 0x0000c0ff, 0x00000000, 2, 0}, -+ {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 128 pixel yellow - repeat 64 times -+ {0x7000, 0x0000ff00, 0x00000000, 2, 0}, -+ {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 128 pixel white - repeat 64 times -+ {0x7000, 0x0000ff7f, 0x00000000, 2, 0}, -+ {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(64<<16)}, -+// 1023 lines -+ {0x7090, 0x000003fe, 0x00000000, 2, 0}, -+ {0x7092, 0x000004d8, 0x00000000, 2, 0}, -+ {0x7094, 0x0000002d, 0x00000000, 2, 0}, -+ {0x7080, 0x00000083, 0x00000000, 2, 0}, -+}; -+ -+static const struct reg_value tc358743_setting_YUV422_2lane_color_bar_640_480_174MHz[] = { -+ {0x0006, 0x00000000, 0x00000000, 2, 0}, -+ {0x0004, 0x00000084, 0x00000000, 2, 0}, -+ {0x0010, 0x0000001e, 0x00000000, 2, 0}, -+// Program CSI Tx PLL -+ {0x0020, 0x00008073, 0x00000000, 2, 0}, -+ {0x0022, 0x00000213, 0x00000000, 2, 0}, -+// CSI Tx PHY (32-bit Registers) -+ {0x0140, 0x00000000, 0x00000000, 4, 0}, -+ {0x0144, 0x00000000, 0x00000000, 4, 0}, -+ {0x0148, 0x00000000, 0x00000000, 4, 0}, -+// {0x014c, 0x00000000, 0x00000000, 4, 0}, -+// {0x0150, 0x00000000, 0x00000000, 4, 0}, -+// CSI Tx PPI (32-bit Registers) -+ {0x0210, 0x00001200, 0x00000000, 4, 0}, -+ {0x0214, 0x00000002, 0x00000000, 4, 0}, -+ {0x0218, 0x00000b02, 0x00000000, 4, 0}, -+ {0x021c, 0x00000001, 0x00000000, 4, 0}, -+ {0x0220, 0x00000103, 0x00000000, 4, 0}, -+ {0x0224, 0x00004000, 0x00000000, 4, 0}, -+ {0x0228, 0x00000008, 0x00000000, 4, 0}, -+ {0x022c, 0x00000002, 0x00000000, 4, 0}, -+ {0x0234, 0x0000001f, 0x00000000, 4, 0}, -+ {0x0238, 0x00000000, 0x00000000, 4, 0}, -+ {0x0204, 0x00000001, 0x00000000, 4, 0}, -+ {0x0518, 0x00000001, 0x00000000, 4, 0}, -+ {0x0500, 0xA3008082, 0x00000000, 4, 0}, -+// 640x480 colorbar -+ {0x000a, 0x00000500, 0x00000000, 2, 0}, -+ {0x7080, 0x00000082, 0x00000000, 2, 0}, -+// 80 pixel black - repeate 80 times -+ {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(80<<16)}, -+// 80 pixel blue - repeate 40 times -+ {0x7000, 0x000000ff, 0x00000000, 2, 0}, -+ {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(40<<16)}, -+// 80 pixel red - repeate 40 times -+ {0x7000, 0x00000000, 0x00000000, 2, 0}, -+ {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(40<<16)}, -+// 80 pixel pink - repeate 40 times -+ {0x7000, 0x00007fff, 0x00000000, 2, 0}, -+ {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(40<<16)}, -+// 80 pixel green - repeate 40 times -+ {0x7000, 0x00007f00, 0x00000000, 2, 0}, -+ {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(40<<16)}, -+// 80 pixel light blue - repeate 40 times -+ {0x7000, 0x0000c0ff, 0x00000000, 2, 0}, -+ {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(40<<16)}, -+// 80 pixel yellow - repeate 40 times -+ {0x7000, 0x0000ff00, 0x00000000, 2, 0}, -+ {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(40<<16)}, -+// 80 pixel white - repeate 40 times -+ {0x7000, 0x0000ff7f, 0x00000000, 2, 0}, -+ {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(40<<16)}, -+// 480 lines -+ {0x7090, 0x000001df, 0x00000000, 2, 0}, -+ {0x7092, 0x00000898, 0x00000000, 2, 0}, -+ {0x7094, 0x00000285, 0x00000000, 2, 0}, -+ {0x7080, 0x00000083, 0x00000000, 2, 0}, -+}; -+ -+static const struct reg_value tc358743_setting_YUV422_2lane_color_bar_640_480_108MHz_cont[] = { -+ {0x0006, 0x00000000, 0x00000000, 2, 0}, -+ {0x0004, 0x00000084, 0x00000000, 2, 0}, -+ {0x0010, 0x0000001e, 0x00000000, 2, 0}, -+// Program CSI Tx PLL -+ {0x0020, 0x0000404F, 0x00000000, 2, 0}, -+ {0x0022, 0x00000613, 0x00000000, 2, 0}, -+// CSI Tx PHY (32-bit Registers) -+ {0x0140, 0x00000000, 0x00000000, 4, 0}, -+ {0x0144, 0x00000000, 0x00000000, 4, 0}, -+ {0x0148, 0x00000000, 0x00000000, 4, 0}, -+ {0x014c, 0x00000000, 0x00000000, 4, 0}, -+ {0x0150, 0x00000000, 0x00000000, 4, 0}, -+// CSI Tx PPI (32-bit Registers) -+ {0x0210, 0x00001800, 0x00000000, 4, 0}, -+ {0x0214, 0x00000002, 0x00000000, 4, 0}, -+ {0x0218, 0x00001102, 0x00000000, 4, 0}, -+ {0x021c, 0x00000000, 0x00000000, 4, 0}, -+ {0x0220, 0x00000003, 0x00000000, 4, 0}, -+ {0x0224, 0x00004000, 0x00000000, 4, 0}, -+ {0x0228, 0x00000007, 0x00000000, 4, 0}, -+ {0x022c, 0x00000001, 0x00000000, 4, 0}, -+ {0x0234, 0x0000001f, 0x00000000, 4, 0}, -+ {0x0238, 0x00000001, 0x00000000, 4, 0}, -+ {0x0204, 0x00000001, 0x00000000, 4, 0}, -+ {0x0518, 0x00000001, 0x00000000, 4, 0}, -+ {0x0500, 0xA30080A2, 0x00000000, 4, 0}, -+// 640x480 colorbar -+ {0x000a, 0x00000500, 0x00000000, 2, 0}, -+ {0x7080, 0x00000082, 0x00000000, 2, 0}, -+// 80 pixel black - repeate 80 times -+ {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(80<<16)}, -+// 80 pixel blue - repeate 40 times -+ {0x7000, 0x000000ff, 0x00000000, 2, 0}, -+ {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(40<<16)}, -+// 80 pixel red - repeate 40 times -+ {0x7000, 0x00000000, 0x00000000, 2, 0}, -+ {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(40<<16)}, -+// 80 pixel pink - repeate 40 times -+ {0x7000, 0x00007fff, 0x00000000, 2, 0}, -+ {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(40<<16)}, -+// 80 pixel green - repeate 40 times -+ {0x7000, 0x00007f00, 0x00000000, 2, 0}, -+ {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(40<<16)}, -+// 80 pixel light blue - repeate 40 times -+ {0x7000, 0x0000c0ff, 0x00000000, 2, 0}, -+ {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(40<<16)}, -+// 80 pixel yellow - repeate 40 times -+ {0x7000, 0x0000ff00, 0x00000000, 2, 0}, -+ {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(40<<16)}, -+// 80 pixel white - repeate 40 times -+ {0x7000, 0x0000ff7f, 0x00000000, 2, 0}, -+ {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(40<<16)}, -+// 480 lines -+ {0x7090, 0x000001df, 0x00000000, 2, 0}, -+ {0x7092, 0x00000700, 0x00000000, 2, 0}, -+ {0x7094, 0x00000010, 0x00000000, 2, 0}, -+ {0x7080, 0x00000083, 0x00000000, 2, 0}, -+}; -+ -+//480p RGB2YUV442 -+static const struct reg_value tc358743_setting_YUV422_2lane_60fps_640_480_125Mhz[] = { -+ {0x0006, 0x00000040, 0x00000000, 2, 0}, -+// {0x000a, 0x000005a0, 0x00000000, 2, 0}, -+// {0x0010, 0x0000001e, 0x00000000, 2, 0}, -+ {0x0014, 0x00000000, 0x00000000, 2, 0}, -+ {0x0016, 0x000005ff, 0x00000000, 2, 0}, -+// Program CSI Tx PLL -+ {0x0020, 0x0000405c, 0x00000000, 2, 0}, -+ {0x0022, 0x00000613, 0x00000000, 2, 0}, -+// CSI Tx PHY (32-bit Registers) -+ {0x0140, 0x00000000, 0x00000000, 4, 0}, -+ {0x0144, 0x00000000, 0x00000000, 4, 0}, -+ {0x0148, 0x00000000, 0x00000000, 4, 0}, -+ {0x014c, 0x00000000, 0x00000000, 4, 0}, -+ {0x0150, 0x00000000, 0x00000000, 4, 0}, -+// CSI Tx PPI (32-bit Registers) -+ {0x0210, 0x00000d00, 0x00000000, 4, 0}, -+ {0x0214, 0x00000001, 0x00000000, 4, 0}, -+ {0x0218, 0x00000701, 0x00000000, 4, 0}, -+ {0x021c, 0x00000000, 0x00000000, 4, 0}, -+ {0x0220, 0x00000001, 0x00000000, 4, 0}, -+ {0x0224, 0x00004000, 0x00000000, 4, 0}, -+ {0x0228, 0x00000005, 0x00000000, 4, 0}, -+ {0x022c, 0x00000000, 0x00000000, 4, 0}, -+ {0x0234, 0x0000001f, 0x00000000, 4, 0}, -+ {0x0238, 0x00000001, 0x00000000, 4, 0}, -+ {0x0204, 0x00000001, 0x00000000, 4, 0}, -+ {0x0518, 0x00000001, 0x00000000, 4, 0}, -+ {0x0500, 0xA30080A2, 0x00000000, 4, 0}, -+// HDMI Interrupt Mask -+ {0x8502, 0x00000001, 0x00000000, 1, 0}, -+ {0x8512, 0x000000fe, 0x00000000, 1, 0}, -+ {0x8514, 0x00000000, 0x00000000, 1, 0}, -+ {0x8515, 0x00000000, 0x00000000, 1, 0}, -+ {0x8516, 0x00000000, 0x00000000, 1, 0}, -+// HDMI Audio -+ {0x8531, 0x00000001, 0x00000000, 1, 0}, -+ {0x8630, 0x00041eb0, 0x00000000, 1, 0}, -+ {0x8670, 0x00000001, 0x00000000, 1, 0}, -+// HDMI PHY -+ {0x8532, 0x00000080, 0x00000000, 1, 0}, -+ {0x8536, 0x00000040, 0x00000000, 1, 0}, -+ {0x853f, 0x0000000a, 0x00000000, 1, 0}, -+// HDMI System -+ {0x8545, 0x00000031, 0x00000000, 1, 0}, -+ {0x8546, 0x0000002d, 0x00000000, 1, 0}, -+// HDCP Setting -+ {0x85d1, 0x00000001, 0x00000000, 1, 0}, -+ {0x8560, 0x00000024, 0x00000000, 1, 0}, -+ {0x8563, 0x00000011, 0x00000000, 1, 0}, -+ {0x8564, 0x0000000f, 0x00000000, 1, 0}, -+// RGB --> YUV Conversion -+ {0x8573, 0x00000081, 0x00000000, 1, 0}, -+ {0x8571, 0x00000002, 0x00000000, 1, 0}, -+// HDMI Audio In Setting -+ {0x8600, 0x00000000, 0x00000000, 1, 0}, -+ {0x8602, 0x000000f3, 0x00000000, 1, 0}, -+ {0x8603, 0x00000002, 0x00000000, 1, 0}, -+ {0x8604, 0x0000000c, 0x00000000, 1, 0}, -+ {0x8606, 0x00000005, 0x00000000, 1, 0}, -+ {0x8607, 0x00000000, 0x00000000, 1, 0}, -+ {0x8620, 0x00000022, 0x00000000, 1, 0}, -+ {0x8640, 0x00000001, 0x00000000, 1, 0}, -+ {0x8641, 0x00000065, 0x00000000, 1, 0}, -+ {0x8642, 0x00000007, 0x00000000, 1, 0}, -+ {0x8652, 0x00000002, 0x00000000, 1, 0}, -+ {0x8665, 0x00000010, 0x00000000, 1, 0}, -+// InfoFrame Extraction -+ {0x8709, 0x000000ff, 0x00000000, 1, 0}, -+ {0x870b, 0x0000002c, 0x00000000, 1, 0}, -+ {0x870c, 0x00000053, 0x00000000, 1, 0}, -+ {0x870d, 0x00000001, 0x00000000, 1, 0}, -+ {0x870e, 0x00000030, 0x00000000, 1, 0}, -+ {0x9007, 0x00000010, 0x00000000, 1, 0}, -+ {0x854a, 0x00000001, 0x00000000, 1, 0}, -+// Output Control -+ {0x0004, 0x00000cf7, 0x00000000, 2, 0}, -+ }; -+ -+//480p RGB2YUV442 -+static const struct reg_value tc358743_setting_YUV422_2lane_60fps_720_480_125Mhz[] = { -+ {0x0006, 0x00000040, 0x00000000, 2, 0}, -+ {0x000a, 0x000005a0, 0x00000000, 2, 0}, -+// {0x0010, 0x0000001e, 0x00000000, 2, 0}, -+ {0x0014, 0x00000000, 0x00000000, 2, 0}, -+ {0x0016, 0x000005ff, 0x00000000, 2, 0}, -+// Program CSI Tx PLL -+ {0x0020, 0x0000405b, 0x00000000, 2, 0}, -+ {0x0022, 0x00000613, 0x00000000, 2, 0}, -+// CSI Tx PHY (32-bit Registers) -+ {0x0140, 0x00000000, 0x00000000, 4, 0}, -+ {0x0144, 0x00000000, 0x00000000, 4, 0}, -+ {0x0148, 0x00000000, 0x00000000, 4, 0}, -+ {0x014c, 0x00000000, 0x00000000, 4, 0}, -+ {0x0150, 0x00000000, 0x00000000, 4, 0}, -+// CSI Tx PPI (32-bit Registers) -+ {0x0210, 0x00000d00, 0x00000000, 4, 0}, -+ {0x0214, 0x00000001, 0x00000000, 4, 0}, -+ {0x0218, 0x00000701, 0x00000000, 4, 0}, -+ {0x021c, 0x00000000, 0x00000000, 4, 0}, -+ {0x0220, 0x00000001, 0x00000000, 4, 0}, -+ {0x0224, 0x00004000, 0x00000000, 4, 0}, -+ {0x0228, 0x00000005, 0x00000000, 4, 0}, -+ {0x022c, 0x00000000, 0x00000000, 4, 0}, -+ {0x0234, 0x0000001f, 0x00000000, 4, 0}, -+ {0x0238, 0x00000001, 0x00000000, 4, 0}, -+ {0x0204, 0x00000001, 0x00000000, 4, 0}, -+ {0x0518, 0x00000001, 0x00000000, 4, 0}, -+ {0x0500, 0xA30080A2, 0x00000000, 4, 0}, -+// HDMI Interrupt Mask -+ {0x8502, 0x00000001, 0x00000000, 1, 0}, -+ {0x8512, 0x000000fe, 0x00000000, 1, 0}, -+ {0x8514, 0x00000000, 0x00000000, 1, 0}, -+ {0x8515, 0x00000000, 0x00000000, 1, 0}, -+ {0x8516, 0x00000000, 0x00000000, 1, 0}, -+// HDMI Audio -+ {0x8531, 0x00000001, 0x00000000, 1, 0}, -+ {0x8630, 0x00041eb0, 0x00000000, 1, 0}, -+ {0x8670, 0x00000001, 0x00000000, 1, 0}, -+// HDMI PHY -+ {0x8532, 0x00000080, 0x00000000, 1, 0}, -+ {0x8536, 0x00000040, 0x00000000, 1, 0}, -+ {0x853f, 0x0000000a, 0x00000000, 1, 0}, -+// HDMI System -+ {0x8545, 0x00000031, 0x00000000, 1, 0}, -+ {0x8546, 0x0000002d, 0x00000000, 1, 0}, -+// HDCP Setting -+ {0x85d1, 0x00000001, 0x00000000, 1, 0}, -+ {0x8560, 0x00000024, 0x00000000, 1, 0}, -+ {0x8563, 0x00000011, 0x00000000, 1, 0}, -+ {0x8564, 0x0000000f, 0x00000000, 1, 0}, -+// RGB --> YUV Conversion -+ {0x8573, 0x00000081, 0x00000000, 1, 0}, -+ {0x8571, 0x00000002, 0x00000000, 1, 0}, -+// HDMI Audio In Setting -+ {0x8600, 0x00000000, 0x00000000, 1, 0}, -+ {0x8602, 0x000000f3, 0x00000000, 1, 0}, -+ {0x8603, 0x00000002, 0x00000000, 1, 0}, -+ {0x8604, 0x0000000c, 0x00000000, 1, 0}, -+ {0x8606, 0x00000005, 0x00000000, 1, 0}, -+ {0x8607, 0x00000000, 0x00000000, 1, 0}, -+ {0x8620, 0x00000022, 0x00000000, 1, 0}, -+ {0x8640, 0x00000001, 0x00000000, 1, 0}, -+ {0x8641, 0x00000065, 0x00000000, 1, 0}, -+ {0x8642, 0x00000007, 0x00000000, 1, 0}, -+ {0x8652, 0x00000002, 0x00000000, 1, 0}, -+ {0x8665, 0x00000010, 0x00000000, 1, 0}, -+// InfoFrame Extraction -+ {0x8709, 0x000000ff, 0x00000000, 1, 0}, -+ {0x870b, 0x0000002c, 0x00000000, 1, 0}, -+ {0x870c, 0x00000053, 0x00000000, 1, 0}, -+ {0x870d, 0x00000001, 0x00000000, 1, 0}, -+ {0x870e, 0x00000030, 0x00000000, 1, 0}, -+ {0x9007, 0x00000010, 0x00000000, 1, 0}, -+ {0x854a, 0x00000001, 0x00000000, 1, 0}, -+// Output Control -+ {0x0004, 0x00000cf7, 0x00000000, 2, 0}, -+ }; -+ -+static const struct reg_value tc358743_setting_YUV422_4lane_1080P_60fps_1920_1080_300MHz[] = { -+ {0x0004, 0x00000084, 0x00000000, 2, 0}, -+ {0x0006, 0x00000000, 0x00000000, 2, 0}, -+ {0x0014, 0x00000000, 0x00000000, 2, 0}, -+ {0x0016, 0x000005ff, 0x00000000, 2, 0}, -+// Program CSI Tx PLL -+ {0x0020, 0x000080c7, 0x00000000, 2, 0}, -+ {0x0022, 0x00000213, 0x00000000, 2, 0}, -+// CSI Tx PHY (32-bit Registers) -+ {0x0140, 0x00000000, 0x00000000, 4, 0}, -+ {0x0144, 0x00000000, 0x00000000, 4, 0}, -+ {0x0148, 0x00000000, 0x00000000, 4, 0}, -+ {0x014c, 0x00000000, 0x00000000, 4, 0}, -+ {0x0150, 0x00000000, 0x00000000, 4, 0}, -+// CSI Tx PPI (32-bit Registers) -+ {0x0210, 0x00001e00, 0x00000000, 4, 0}, -+ {0x0214, 0x00000003, 0x00000000, 4, 0}, -+ {0x0218, 0x00001402, 0x00000000, 4, 0}, -+ {0x021c, 0x00000000, 0x00000000, 4, 0}, -+ {0x0220, 0x00000003, 0x00000000, 4, 0}, -+ {0x0224, 0x00004a00, 0x00000000, 4, 0}, -+ {0x0228, 0x00000008, 0x00000000, 4, 0}, -+ {0x022c, 0x00000002, 0x00000000, 4, 0}, -+ {0x0234, 0x0000001f, 0x00000000, 4, 0}, -+ {0x0238, 0x00000001, 0x00000000, 4, 0}, -+ {0x0204, 0x00000001, 0x00000000, 4, 0}, -+ {0x0518, 0x00000001, 0x00000000, 4, 0}, -+ {0x0500, 0xa30080a6, 0x00000000, 4, 0}, -+// HDMI Interrupt Mask -+ {0x8502, 0x00000001, 0x00000000, 1, 0}, -+ {0x8512, 0x000000fe, 0x00000000, 1, 0}, -+ {0x8514, 0x00000000, 0x00000000, 1, 0}, -+ {0x8515, 0x00000000, 0x00000000, 1, 0}, -+ {0x8516, 0x00000000, 0x00000000, 1, 0}, -+// HDMI Audio -+ {0x8531, 0x00000001, 0x00000000, 1, 0}, -+ {0x8630, 0x00041eb0, 0x00000000, 1, 0}, -+ {0x8670, 0x00000001, 0x00000000, 1, 0}, -+// HDMI PHY -+ {0x8532, 0x00000080, 0x00000000, 1, 0}, -+ {0x8536, 0x00000040, 0x00000000, 1, 0}, -+ {0x853f, 0x0000000a, 0x00000000, 1, 0}, -+// HDMI System -+ {0x8545, 0x00000031, 0x00000000, 1, 0}, -+ {0x8546, 0x0000002d, 0x00000000, 1, 0}, -+// HDCP Setting -+ {0x85d1, 0x00000001, 0x00000000, 1, 0}, -+ {0x8560, 0x00000024, 0x00000000, 1, 0}, -+ {0x8563, 0x00000011, 0x00000000, 1, 0}, -+ {0x8564, 0x0000000f, 0x00000000, 1, 0}, -+// RGB --> YUV Conversion -+ {0x8571, 0x00000002, 0x00000000, 1, 0}, -+ {0x8573, 0x00000081, 0x00000000, 1, 0}, -+ {0x8576, 0x00000060, 0x00000000, 1, 0}, -+// HDMI Audio In Setting -+ {0x8600, 0x00000000, 0x00000000, 1, 0}, -+ {0x8602, 0x000000f3, 0x00000000, 1, 0}, -+ {0x8603, 0x00000002, 0x00000000, 1, 0}, -+ {0x8604, 0x0000000c, 0x00000000, 1, 0}, -+ {0x8606, 0x00000005, 0x00000000, 1, 0}, -+ {0x8607, 0x00000000, 0x00000000, 1, 0}, -+ {0x8620, 0x00000022, 0x00000000, 1, 0}, -+ {0x8640, 0x00000001, 0x00000000, 1, 0}, -+ {0x8641, 0x00000065, 0x00000000, 1, 0}, -+ {0x8642, 0x00000007, 0x00000000, 1, 0}, -+ {0x8652, 0x00000002, 0x00000000, 1, 0}, -+ {0x8665, 0x00000010, 0x00000000, 1, 0}, -+// InfoFrame Extraction -+ {0x8709, 0x000000ff, 0x00000000, 1, 0}, -+ {0x870b, 0x0000002c, 0x00000000, 1, 0}, -+ {0x870c, 0x00000053, 0x00000000, 1, 0}, -+ {0x870d, 0x00000001, 0x00000000, 1, 0}, -+ {0x870e, 0x00000030, 0x00000000, 1, 0}, -+ {0x9007, 0x00000010, 0x00000000, 1, 0}, -+ {0x854a, 0x00000001, 0x00000000, 1, 0}, -+// Output Control -+ {0x0004, 0x00000cf7, 0x00000000, 2, 0}, -+}; -+ -+static const struct reg_value tc358743_setting_YUV422_4lane_1080P_30fps_1920_1080_300MHz[] = { -+ {0x0004, 0x00000084, 0x00000000, 2, 0}, // Internal Generated output pattern,Do not send InfoFrame data out to CSI2,Audio output to CSI2-TX i/f,I2C address index increments on every data byte transfer, disable audio and video TX buffers -+ {0x0006, 0x000001f8, 0x00000000, 2, 0}, // FIFO level = 1f8 = 504 -+ {0x0014, 0x00000000, 0x00000000, 2, 0}, // Clear interrupt status bits -+ {0x0016, 0x000005ff, 0x00000000, 2, 0}, // Mask audio mute, CSI-TX, and the other interrups -+// Program CSI Tx PLL -+ //{0x0020, 0x000080c7, 0x00000000, 2, 0}, // Input divider setting = 0x8 -> Division ratio = (PRD3..0) + 1 = 9, Feedback divider setting = 0xc7 -> Division ratio = (FBD8...0) + 1 = 200 -+ {0x0020, 0x000080c7, 0x00000000, 2, 0}, // Input divider setting = 0x8 -> Division ratio = (PRD3..0) + 1 = 9, Feedback divider setting = 0xc7 -> Division ratio = (FBD8...0) + 1 = 200 -+ {0x0022, 0x00000213, 0x00000000, 2, 0}, // HSCK frequency = 500MHz – 1GHz HSCK frequency, Loop bandwidth setting = 50% of maximum loop bandwidth (default), REFCLK toggling –> normal operation, REFCLK stops -> no oscillation, Bypass clock = normal operation, clocks switched off (output LOW), PLL Reset normal operation, PLL Enable = PLL on -+// CSI Tx PHY (32-bit Registers) -+ {0x0140, 0x00000000, 0x00000000, 4, 0}, // Clock Lane DPHY Control: Bypass Lane Enable from PPI Layer enable. -+ {0x0144, 0x00000000, 0x00000000, 4, 0}, // Data Lane 0 DPHY Control: Bypass Lane Enable from PPI Layer enable. -+ {0x0148, 0x00000000, 0x00000000, 4, 0}, // Data Lane 1 DPHY Control: Bypass Lane Enable from PPI Layer enable. -+ {0x014c, 0x00000000, 0x00000000, 4, 0}, // Data Lane 2 DPHY Control: Bypass Lane Enable from PPI Layer enable. -+ {0x0150, 0x00000000, 0x00000000, 4, 0}, // Data Lane 3 DPHY Control: Bypass Lane Enable from PPI Layer enable. -+// CSI Tx PPI (32-bit Registers) -+ {0x0210, 0x00001e00, 0x00000000, 4, 0}, // LINEINITCNT: Line Initialization Wait Counter = 0x1e00 = 7680 -+ {0x0214, 0x00000003, 0x00000000, 4, 0}, // LPTXTIMECNT: SYSLPTX Timing Generation Counter = 3 -+ {0x0218, 0x00001402, 0x00000000, 4, 0}, // TCLK_HEADERCNT: TCLK_ZERO Counter = 0x14 = 20, TCLK_PREPARE Counter = 0x02 = 2 -+ {0x021c, 0x00000000, 0x00000000, 4, 0}, // TCLK_TRAILCNT: TCLK_TRAIL Counter = 0 -+ {0x0220, 0x00000003, 0x00000000, 4, 0}, // THS_HEADERCNT: THS_ZERO Counter = 0, THS_PREPARE Counter = 3 -+ {0x0224, 0x00004a00, 0x00000000, 4, 0}, // TWAKEUP: TWAKEUP Counter = 0x4a00 = 18944 -+ {0x0228, 0x00000008, 0x00000000, 4, 0}, // TCLK_POSTCNT: TCLK_POST Counter = 8 -+ {0x022c, 0x00000002, 0x00000000, 4, 0}, // THS_TRAILCNT: THS_TRAIL Counter = 2 -+ {0x0234, 0x0000001f, 0x00000000, 4, 0}, // HSTXVREGEN: Enable voltage regulators for lanes and clk -+ {0x0238, 0x00000001, 0x00000000, 4, 0}, // TXOPTIONCNTRL: Set Continuous Clock Mode -+ {0x0204, 0x00000001, 0x00000000, 4, 0}, // PPI STARTCNTRL: start PPI function -+ {0x0518, 0x00000001, 0x00000000, 4, 0}, // CSI_START: start -+ {0x0500, 0xa30080a6, 0x00000000, 4, 0}, // CSI Configuration Register: set register 0x040C with data 0x80a6 (CSI MOde, Disables the HTX_TO timer, High-Speed data transfer is performed to Tx, DSCClk Stays in HS mode when Data Lane goes to LP, 4 Data Lanes,The EOT packet is automatically granted at the end of HS transfer then is transmitted) -+// HDMI Interrupt Mask -+ {0x8502, 0x00000001, 0x00000000, 1, 0}, // SYSTEM INTERRUPT: clear DDC power change detection interrupt -+ {0x8512, 0x000000fe, 0x00000000, 1, 0}, // SYS INTERRUPT MASK: DDC power change detection interrupt not masked -+ {0x8514, 0x00000000, 0x00000000, 1, 0}, // PACKET INTERRUPT MASK: unmask all -+ {0x8515, 0x00000000, 0x00000000, 1, 0}, // CBIT INTERRUPT MASK: unmask all -+ {0x8516, 0x00000000, 0x00000000, 1, 0}, // AUDIO INTERRUPT MASK: unmask all -+// HDMI Audio -+ {0x8531, 0x00000001, 0x00000000, 1, 0}, // PHY CONTROL0: 27MHz, DDC5V detection operation. -+ {0x8630, 0x00041eb0, 0x00000000, 1, 0}, // Audio FS Lock Detect Control: for 27MHz -+ {0x8670, 0x00000001, 0x00000000, 1, 0}, -+// HDMI PHY -+ {0x8532, 0x00000080, 0x00000000, 1, 0}, // -+ {0x8536, 0x00000040, 0x00000000, 1, 0}, // -+ {0x853f, 0x0000000a, 0x00000000, 1, 0}, // -+// HDMI System -+ {0x8545, 0x00000031, 0x00000000, 1, 0}, // ANA CONTROL: PLL charge pump setting for Audio = normal, DAC/PLL power ON/OFF setting for Audio = ON -+ {0x8546, 0x0000002d, 0x00000000, 1, 0}, // AVMUTE CONTROL: AVM_CTL = 0x2d -+// HDCP Setting -+ {0x85d1, 0x00000001, 0x00000000, 1, 0}, // -+ {0x8560, 0x00000024, 0x00000000, 1, 0}, // HDCP MODE: HDCP automatic reset when DVI⇔HDMI switched = on, HDCP Line Rekey timing switch = 7clk mode (Data island delay ON), Bcaps[5] KSVINFO_READY(0x8840[5]) auto clear mode = Auto clear using AKSV write -+ {0x8563, 0x00000011, 0x00000000, 1, 0}, // -+ {0x8564, 0x0000000f, 0x00000000, 1, 0}, // -+// RGB --> YUV Conversion -+ {0x8571, 0x00000002, 0x00000000, 1, 0}, // -+ {0x8573, 0x000000c1, 0x00000000, 1, 0}, // VOUT SET2 REGISTER: 422 fixed output, Video Output 422 conversion mode selection 000: During 444 input, 3tap filter; during 422 input, simple decimation, Enable RGB888 to YUV422 Conversion (Fixed Color output) -+ {0x8574, 0x00000008, 0x00000000, 1, 0}, // VOUT SET3 REGISTER (VOUT_SET3): Follow register bit 0x8573[7] setting -+ {0x8576, 0x00000060, 0x00000000, 1, 0}, // VOUT_COLOR: Output Color = 601 YCbCr Limited, Input Pixel Repetition judgment = automatic, Input Pixel Repetition HOST setting = no repetition -+// HDMI Audio In Setting -+ {0x8600, 0x00000000, 0x00000000, 1, 0}, -+ {0x8602, 0x000000f3, 0x00000000, 1, 0}, -+ {0x8603, 0x00000002, 0x00000000, 1, 0}, -+ {0x8604, 0x0000000c, 0x00000000, 1, 0}, -+ {0x8606, 0x00000005, 0x00000000, 1, 0}, -+ {0x8607, 0x00000000, 0x00000000, 1, 0}, -+ {0x8620, 0x00000022, 0x00000000, 1, 0}, -+ {0x8640, 0x00000001, 0x00000000, 1, 0}, -+ {0x8641, 0x00000065, 0x00000000, 1, 0}, -+ {0x8642, 0x00000007, 0x00000000, 1, 0}, -+ {0x8652, 0x00000002, 0x00000000, 1, 0}, -+ {0x8665, 0x00000010, 0x00000000, 1, 0}, -+// InfoFrame Extraction -+ {0x8709, 0x000000ff, 0x00000000, 1, 0}, // PACKET INTERRUPT MODE: all enable -+ {0x870b, 0x0000002c, 0x00000000, 1, 0}, // NO PACKET LIMIT: NO_ACP_LIMIT = 0x2, NO_AVI_LIMIT = 0xC -+ {0x870c, 0x00000053, 0x00000000, 1, 0}, // When VS receive interrupt is detected, VS storage register automatic clear, When ACP receive interrupt is detected, ACP storage register automatic clear, When AVI receive interrupt occurs, judge input video signal with RGB and no Repetition, When AVI receive interrupt is detected, AVI storage register automatic clear. -+ {0x870d, 0x00000001, 0x00000000, 1, 0}, // ERROR PACKET LIMIT: Packet continuing receive error occurrence detection threshold = 1 -+ {0x870e, 0x00000030, 0x00000000, 1, 0}, // NO PACKET LIMIT: -+ {0x9007, 0x00000010, 0x00000000, 1, 0}, // -+ {0x854a, 0x00000001, 0x00000000, 1, 0}, // Initialization completed flag -+// Output Control -+ {0x0004, 0x00000cf7, 0x00000000, 2, 0}, // Configuration Control Register: Power Island Normal, I2S/TDM clock are free running, Enable 2 Audio channels, Audio channel number Auto detect by HW, I2S/TDM Data no delay, Select YCbCr422 8-bit (HDMI YCbCr422 12-bit data format), Send InfoFrame data out to CSI2, Audio output to I2S i/f (valid for 2 channel only), I2C address index increments on every data byte transfer, Audio and Video tx buffres enable. -+}; -+ -+/* list of image formats supported by TCM825X sensor */ -+static const struct v4l2_fmtdesc tc358743_formats[] = { -+ { -+ .description = "RGB888 (RGB24)", -+ .pixelformat = V4L2_PIX_FMT_RGB24, /* 24 RGB-8-8-8 */ -+ .flags = MIPI_DT_RGB888 // 0x24 -+ }, -+ { -+ .description = "RAW12 (Y/CbCr 4:2:0)", -+ .pixelformat = V4L2_PIX_FMT_UYVY, /* 12 Y/CbCr 4:2:0 */ -+ .flags = MIPI_DT_RAW12 // 0x2c -+ }, -+ { -+ .description = "YUV 4:2:2 8-bit", -+ .pixelformat = V4L2_PIX_FMT_YUYV, /* 8 8-bit color */ -+ .flags = MIPI_DT_YUV422 // 0x1e /* UYVY... */ -+ }, -+}; -+ -+ -+static const struct tc358743_mode_info tc358743_mode_info_data[2][tc358743_mode_MAX] = { -+/* Color bar test settings */ -+ [1][tc358743_mode_INIT] = -+ {"cb640x480-108MHz@30", tc358743_mode_INIT, 640, 480, -+ 6, 1, 2, 108, -+ tc358743_setting_YUV422_2lane_color_bar_640_480_108MHz_cont, -+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_640_480_108MHz_cont), -+ MIPI_DT_YUV422 -+ }, -+ [0][tc358743_mode_INIT] = -+ {"cb640x480-108MHz@60", tc358743_mode_INIT, 640, 480, -+ 6, 1, 2, 108, -+ tc358743_setting_YUV422_2lane_color_bar_640_480_108MHz_cont, -+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_640_480_108MHz_cont), -+ MIPI_DT_YUV422 -+ }, -+ [1][tc358743_mode_INIT4] = -+ {"cb640x480-174Mhz@30", tc358743_mode_INIT4, 640, 480, -+ 6, 1, 2, 174, -+ tc358743_setting_YUV422_2lane_color_bar_640_480_174MHz, -+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_640_480_174MHz), -+ MIPI_DT_YUV422 -+ }, -+ [0][tc358743_mode_INIT4] = -+ {"cb640x480-174MHz@60", tc358743_mode_INIT4, 640, 480, -+ 6, 1, 2, 174, -+ tc358743_setting_YUV422_2lane_color_bar_640_480_174MHz, -+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_640_480_174MHz), -+ MIPI_DT_YUV422 -+ }, -+ [1][tc358743_mode_INIT3] = -+ {"cb1024x720-4lane@30", tc358743_mode_INIT3, 1024, 720, -+ 6, 1, 4, 300, -+ tc358743_setting_YUV422_4lane_color_bar_1024_720_200MHz, -+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1024_720_200MHz), -+ MIPI_DT_YUV422 -+ }, -+ [0][tc358743_mode_INIT3] = -+ {"cb1024x720-4lane@60", tc358743_mode_INIT3, 1024, 720, -+ 6, 1, 4, 300, -+ tc358743_setting_YUV422_4lane_color_bar_1024_720_200MHz, -+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1024_720_200MHz), -+ MIPI_DT_YUV422 -+ }, -+ [1][tc358743_mode_INIT1] = -+ {"cb1280x720-2lane@30", tc358743_mode_INIT1, 1280, 720, -+ 12, 0, 2, 125, -+ tc358743_setting_YUV422_2lane_color_bar_1280_720_125MHz, -+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_1280_720_125MHz), -+ MIPI_DT_YUV422 -+ }, -+ [0][tc358743_mode_INIT1] = -+ {"cb1280x720-2lane@60", tc358743_mode_INIT1, 1280, 720, -+ 12, 0, 2, 125, -+ tc358743_setting_YUV422_2lane_color_bar_1280_720_125MHz, -+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_1280_720_125MHz), -+ MIPI_DT_YUV422 -+ }, -+ [1][tc358743_mode_INIT2] = -+ {"cb1280x720-4lane-125MHz@30", tc358743_mode_INIT2, 1280, 720, -+ 12, 0, 4, 125, -+ tc358743_setting_YUV422_4lane_color_bar_1280_720_125MHz, -+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1280_720_125MHz), -+ MIPI_DT_YUV422 -+ }, -+ [0][tc358743_mode_INIT2] = -+ {"cb1280x720-4lane-125MHz@60", tc358743_mode_INIT2, 1280, 720, -+ 12, 0, 4, 125, -+ tc358743_setting_YUV422_4lane_color_bar_1280_720_125MHz, -+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1280_720_125MHz), -+ MIPI_DT_YUV422 -+ }, -+ [1][tc358743_mode_INIT5] = -+ {"cb1280x720-4lane-300MHz@30", tc358743_mode_INIT5, 1280, 720, -+ 12, 0, 4, 300, -+ tc358743_setting_YUV422_4lane_color_bar_1280_720_300MHz, -+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1280_720_300MHz), -+ MIPI_DT_YUV422 -+ }, -+ [0][tc358743_mode_INIT5] = -+ {"cb1280x720-4lane-300MHz@60", tc358743_mode_INIT5, 1280, 720, -+ 12, 0, 4, 300, -+ tc358743_setting_YUV422_4lane_color_bar_1280_720_300MHz, -+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1280_720_300MHz), -+ MIPI_DT_YUV422 -+ }, -+ [1][tc358743_mode_INIT6] = -+ {"cb1920x1023@30", tc358743_mode_INIT6, 1920, 1023, -+ 15, 0, 4, 300, -+ tc358743_setting_YUV422_4lane_color_bar_1920_1023_300MHz, -+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1920_1023_300MHz), -+ MIPI_DT_YUV422 -+ }, -+ [0][tc358743_mode_INIT6] = -+ {"cb1920x1023@60", tc358743_mode_INIT6, 1920, 1023, -+ 15, 0, 4, 300, -+ tc358743_setting_YUV422_4lane_color_bar_1920_1023_300MHz, -+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1920_1023_300MHz), -+ MIPI_DT_YUV422 -+ }, -+/* Input settings */ -+ [tc358743_60_fps][tc358743_mode_480P_640_480] = -+ {"640x480@60", tc358743_mode_480P_640_480, 640, 480, -+ 1, (0x02)<<8|(0x00), 2, 125, -+ tc358743_setting_YUV422_2lane_60fps_640_480_125Mhz, -+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_60fps_640_480_125Mhz), -+ MIPI_DT_YUV422, -+ }, -+ [1][tc358743_mode_480P_720_480] = -+ {"720x480@30", tc358743_mode_480P_720_480, 720, 480, -+ 6, (0x02)<<8|(0x00), 2, 125, -+ tc358743_setting_YUV422_2lane_60fps_720_480_125Mhz, -+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_60fps_720_480_125Mhz), -+ MIPI_DT_YUV422, -+ }, -+ [tc358743_60_fps][tc358743_mode_480P_720_480] = -+ {"720x480@60", tc358743_mode_480P_720_480, 720, 480, -+ 6, (0x02)<<8|(0x00), 2, 125, -+ tc358743_setting_YUV422_2lane_60fps_720_480_125Mhz, -+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_60fps_720_480_125Mhz), -+ MIPI_DT_YUV422, -+ }, -+ [tc358743_60_fps][tc358743_mode_1024x768] = -+ {"1024x768@60", tc358743_mode_1024x768, 1024, 768, -+ 16, 60, 4, 125, -+ tc358743_setting_YUV422_4lane_1024x768_60fps_125MHz, -+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_1024x768_60fps_125MHz), -+ MIPI_DT_YUV422 -+ }, -+ [1][tc358743_mode_720P_1280_720] = -+ {"1280x720-2lane@30", tc358743_mode_720P_1280_720, 1280, 720, -+ 12, (0x3e)<<8|(0x3c), 2, 125, -+ tc358743_setting_YUV422_2lane_30fps_720P_1280_720_125MHz, -+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_30fps_720P_1280_720_125MHz), -+ MIPI_DT_YUV422, -+ }, -+ [0][tc358743_mode_720P_1280_720] = -+ {"1280x720-2lane@60", tc358743_mode_720P_1280_720, 1280, 720, -+ 12, (0x3e)<<8|(0x3c), 2, 125, -+ tc358743_setting_YUV422_2lane_30fps_720P_1280_720_125MHz, -+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_30fps_720P_1280_720_125MHz), -+ MIPI_DT_YUV422, -+ }, -+ [1][tc358743_mode_720P_60_1280_720] = -+ {"1280x720-4lane-133Mhz@30", tc358743_mode_720P_60_1280_720, 1280, 720, -+ 12, 0, 4, 133, -+ tc358743_setting_YUV422_4lane_720P_60fps_1280_720_133Mhz, -+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_720P_60fps_1280_720_133Mhz), -+ MIPI_DT_YUV422 -+ }, -+ [tc358743_60_fps][tc358743_mode_720P_60_1280_720] = -+ {"1280x720-4lane@60", tc358743_mode_720P_60_1280_720, 1280, 720, -+ 12, 0, 4, 133, -+ tc358743_setting_YUV422_4lane_720P_60fps_1280_720_133Mhz, -+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_720P_60fps_1280_720_133Mhz), -+ MIPI_DT_YUV422 -+ }, -+ [1][tc358743_mode_1080P_1920_1080] = -+ {"1920x1080@30", tc358743_mode_1080P_1920_1080, 1920, 1080, -+ 15, 0xa, 4, 300, -+ tc358743_setting_YUV422_4lane_1080P_30fps_1920_1080_300MHz, -+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_1080P_30fps_1920_1080_300MHz), -+ MIPI_DT_YUV422 -+ }, -+ [tc358743_60_fps][tc358743_mode_1080P_1920_1080] = -+ {"1920x1080@60", tc358743_mode_1080P_1920_1080, 1920, 1080, -+ 15, 0x0b, 4, 300, -+ tc358743_setting_YUV422_4lane_1080P_60fps_1920_1080_300MHz, -+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_1080P_60fps_1920_1080_300MHz), -+ MIPI_DT_YUV422 -+ }, -+}; -+ -+static int tc358743_probe(struct i2c_client *adapter, -+ const struct i2c_device_id *device_id); -+static int tc358743_remove(struct i2c_client *client); -+ -+static const struct i2c_device_id tc358743_id[] = { -+ {"tc358743_mipi", 0}, -+ {}, -+}; -+ -+MODULE_DEVICE_TABLE(i2c, tc358743_id); -+ -+static struct i2c_driver tc358743_i2c_driver = { -+ .driver = { -+ .owner = THIS_MODULE, -+ .name = "tc358743_mipi", -+ }, -+ .probe = tc358743_probe, -+ .remove = tc358743_remove, -+ .id_table = tc358743_id, -+}; -+ -+struct _reg_size -+{ -+ u16 startaddr, endaddr; -+ int size; -+}; -+ -+static const struct _reg_size tc358743_read_reg_size[] = -+{ -+ {0x0000, 0x005a, 2}, -+ {0x0140, 0x0150, 4}, -+ {0x0204, 0x0238, 4}, -+ {0x040c, 0x0418, 4}, -+ {0x044c, 0x0454, 4}, -+ {0x0500, 0x0518, 4}, -+ {0x0600, 0x06cc, 4}, -+ {0x7000, 0x7100, 2}, -+ {0x8500, 0x8bff, 1}, -+ {0x8c00, 0x8fff, 4}, -+ {0x9000, 0x90ff, 1}, -+ {0x9100, 0x92ff, 1}, -+ {0, 0, 0}, -+}; -+ -+int get_reg_size(u16 reg, int len) -+{ -+ const struct _reg_size *p = tc358743_read_reg_size; -+ int size; -+ -+#if 0 //later #ifndef DEBUG -+ if (len) -+ return len; -+#endif -+ while (p->size) { -+ if ((p->startaddr <= reg) && (reg <= p->endaddr)) { -+ size = p->size; -+ if (len && (size != len)) { -+ pr_err("%s:reg len error:reg=%x %d instead of %d\n", -+ __func__, reg, len, size); -+ return 0; -+ } -+ if (reg % size) { -+ pr_err("%s:cannot read from the middle of a register, reg(%x) size(%d)\n", -+ __func__, reg, size); -+ return 0; -+ } -+ return size; -+ } -+ p++; -+ } -+ pr_err("%s:reg=%x size is not defined\n",__func__, reg); -+ return 0; -+} -+ -+static s32 tc358743_read_reg(struct sensor_data *sensor, u16 reg, void *rxbuf) -+{ -+ struct i2c_client *client = sensor->i2c_client; -+ struct i2c_msg msgs[2]; -+ u8 txbuf[2]; -+ int ret; -+ int size = get_reg_size(reg, 0); -+ -+ if (!size) -+ return -EINVAL; -+ -+ txbuf[0] = reg >> 8; -+ txbuf[1] = reg & 0xff; -+ msgs[0].addr = client->addr; -+ msgs[0].flags = 0; -+ msgs[0].len = 2; -+ msgs[0].buf = txbuf; -+ -+ msgs[1].addr = client->addr; -+ msgs[1].flags = I2C_M_RD; -+ msgs[1].len = size; -+ msgs[1].buf = rxbuf; -+ -+ ret = i2c_transfer(client->adapter, msgs, 2); -+ if (ret < 0) { -+ pr_err("%s:reg=%x ret=%d\n", __func__, reg, ret); -+ return ret; -+ } -+// pr_debug("%s:reg=%x,val=%x\n", __func__, reg, ((char *)rxbuf)[0]); -+ return 0; -+} -+ -+static s32 tc358743_read_reg_val(struct sensor_data *sensor, u16 reg) -+{ -+ u32 val = 0; -+ tc358743_read_reg(sensor, reg, &val); -+ return val; -+} -+ -+static s32 tc358743_read_reg_val16(struct sensor_data *sensor, u16 reg) -+{ -+#if 0 -+ struct i2c_client *client = sensor->i2c_client; -+ struct i2c_msg msgs[3]; -+ u8 txbuf[4]; -+ u8 rxbuf1[4]; -+ u8 rxbuf2[4]; -+ int ret; -+ int size = get_reg_size(reg, 0); -+ -+ if (size != 1) -+ return -EINVAL; -+ -+ txbuf[0] = reg >> 8; -+ txbuf[1] = reg & 0xff; -+ msgs[0].addr = client->addr; -+ msgs[0].flags = 0; -+ msgs[0].len = 2; -+ msgs[0].buf = txbuf; -+ -+ msgs[1].addr = client->addr; -+ msgs[1].flags = I2C_M_RD; -+ msgs[1].len = size; -+ msgs[1].buf = rxbuf1; -+ -+ msgs[2].addr = client->addr; -+ msgs[2].flags = I2C_M_RD; -+ msgs[2].len = size; -+ msgs[2].buf = rxbuf2; -+ -+ ret = i2c_transfer(client->adapter, msgs, 3); -+ if (ret < 0) { -+ pr_err("%s:reg=%x ret=%d\n", __func__, reg, ret); -+ return ret; -+ } -+// pr_debug("%s:reg=%x,val=%x\n", __func__, reg, ((char *)rxbuf)[0]); -+ return rxbuf1[0] | (rxbuf2[0] << 8); -+#else -+ u32 val1 = 0; -+ u32 val2 = 0; -+ tc358743_read_reg(sensor, reg, &val1); -+ tc358743_read_reg(sensor, reg+1, &val2); -+ return val1 | (val2 << 8); -+ -+#endif -+} -+ -+static s32 tc358743_write_reg(struct sensor_data *sensor, u16 reg, u32 val, int len) -+{ -+ int ret; -+ int i = 0; -+ u32 data = val; -+ u8 au8Buf[6] = {0}; -+ int size = get_reg_size(reg, len); -+ -+ if (!size) -+ return -EINVAL; -+ -+ au8Buf[i++] = reg >> 8; -+ au8Buf[i++] = reg & 0xff; -+ while (size-- > 0) { -+ au8Buf[i++] = (u8)data; -+ data >>= 8; -+ } -+ -+ ret = i2c_master_send(sensor->i2c_client, au8Buf, i); -+ if (ret < 0) { -+ pr_err("%s:write reg error(%d):reg=%x,val=%x\n", -+ __func__, ret, reg, val); -+ return ret; -+ } -+ if ((reg < 0x7000) || (reg >= 0x7100)) { -+ if (0) pr_debug("%s:reg=%x,val=%x 8543=%02x\n", __func__, reg, val, tc358743_read_reg_val(sensor, 0x8543)); -+ } -+ return 0; -+} -+ -+static void tc358743_software_reset(struct sensor_data *sensor) -+{ -+ int freq = sensor->mclk / 10000; -+ tc358743_write_reg(sensor, 0x7080, 0, 2); -+ tc358743_write_reg(sensor, 0x0002, 0x0f00, 2); -+ msleep(100); -+ tc358743_write_reg(sensor, 0x0002, 0x0000, 2); -+ msleep(1000); -+ tc358743_write_reg(sensor, 0x0004, 0x0004, 2); /* autoinc */ -+ pr_debug("%s:freq=%d\n", __func__, freq); -+ tc358743_write_reg(sensor, 0x8540, freq, 1); -+ tc358743_write_reg(sensor, 0x8541, freq >> 8, 1); -+} -+ -+static void tc358743_enable_edid(struct sensor_data *sensor) -+{ -+ pr_debug("Activate EDID\n"); -+ // EDID -+ tc358743_write_reg(sensor, 0x85c7, 0x01, 1); // EDID MODE REGISTER: nternal EDID-RAM & DDC2B mode -+ tc358743_write_reg(sensor, 0x85ca, 0x00, 1); -+ tc358743_write_reg(sensor, 0x85cb, 0x01, 1); // 0x85cb:0x85ca - EDID Length = 0x01:00 (Size = 0x100 = 256) -+ tc358743_write_reg(sensor, 0x8543, 0x36, 1); // DDC CONTROL: DDC_ACK output terminal H active, DDC5V_active detect delay 200ms -+ tc358743_write_reg(sensor, 0x854a, 0x01, 1); // mark init done -+ if (0) pr_debug("%s: c7=%02x ca=%02x cb=%02x 43=%02x 4a=%02x\n", __func__, -+ tc358743_read_reg_val(sensor, 0x85c7), -+ tc358743_read_reg_val(sensor, 0x85ca), -+ tc358743_read_reg_val(sensor, 0x85cb), -+ tc358743_read_reg_val(sensor, 0x8543), -+ tc358743_read_reg_val(sensor, 0x854a)); -+} -+ -+static int tc358743_write_edid(struct sensor_data *sensor, const u8 *edid, int len) -+{ -+ int i = 0, off = 0; -+ u8 au8Buf[16+2] = {0}; -+ int size = 0; -+ int checksum = 0; -+ u16 reg; -+ -+ reg = 0x8C00; -+ off = 0; -+ size = ARRAY_SIZE(au8Buf) - 2; -+ pr_debug("Write EDID: %d (%d)\n", len, size); -+ while (len > 0) { -+ i = 0; -+ au8Buf[i++] = (reg >> 8) & 0xff; -+ au8Buf[i++] = reg & 0xff; -+ if (size > len) -+ size = len; -+ while (i < size + 2) { -+ u8 byte = edid[off++]; -+ if ((off & 0x7f) == 0) { -+ checksum &= 0xff; -+ if (checksum != byte) { -+ pr_info("%schecksum=%x, byte=%x\n", __func__, checksum, byte); -+ byte = checksum; -+ checksum = 0; -+ } -+ } else { -+ checksum -= byte; -+ } -+ au8Buf[i++] = byte; -+ } -+ -+ if (i2c_master_send(sensor->i2c_client, au8Buf, i) < 0) { -+ pr_err("%s:write reg error:reg=%x,val=%x\n", -+ __func__, reg, off); -+ return -1; -+ } -+ len -= (u8)size; -+ reg += (u16)size; -+ } -+ tc358743_enable_edid(sensor); -+ return 0; -+} -+ -+static s32 power_control(struct tc_data *td, int on) -+{ -+ struct sensor_data *sensor = &td->sensor; -+ int i; -+ int ret = 0; -+ -+ pr_debug("%s: %d\n", __func__, on); -+ if (sensor->on != on) { -+ if (on) { -+ for (i = 0; i < REGULATOR_CNT; i++) { -+ if (td->regulator[i]) { -+ ret = regulator_enable(td->regulator[i]); -+ if (ret) { -+ pr_err("%s:regulator_enable failed(%d)\n", -+ __func__, ret); -+ on = 0; /* power all off */ -+ break; -+ } -+ } -+ } -+ } -+ tc_standby(td, on ? 0 : 1); -+ sensor->on = on; -+ if (!on) { -+ for (i = REGULATOR_CNT - 1; i >= 0; i--) { -+ if (td->regulator[i]) -+ regulator_disable(td->regulator[i]); -+ } -+ } -+ } -+ return ret; -+} -+ -+static int tc358743_toggle_hpd(struct sensor_data *sensor, int active) -+{ -+ int ret = 0; -+ if (active) { -+ ret += tc358743_write_reg(sensor, 0x8544, 0x00, 1); -+ mdelay(500); -+ ret += tc358743_write_reg(sensor, 0x8544, 0x10, 1); -+ } else { -+ ret += tc358743_write_reg(sensor, 0x8544, 0x10, 1); -+ mdelay(500); -+ ret += tc358743_write_reg(sensor, 0x8544, 0x00, 1); -+ } -+ return ret; -+} -+ -+static int get_format_index(enum tc358743_frame_rate frame_rate, enum tc358743_mode mode) -+{ -+ int ifmt; -+ u32 flags = tc358743_mode_info_data[frame_rate][mode].flags; -+ -+ for (ifmt = 0; ifmt < ARRAY_SIZE(tc358743_formats); ifmt++) { -+ if (flags == tc358743_formats[ifmt].flags) -+ return ifmt; -+ } -+ return -1; -+} -+ -+static int get_pixelformat(enum tc358743_frame_rate frame_rate, enum tc358743_mode mode) -+{ -+ int ifmt = get_format_index(frame_rate, mode); -+ -+ if (ifmt < 0) { -+ pr_debug("%s: unsupported format, %d, %d\n", __func__, frame_rate, mode); -+ return 0; -+ } -+ pr_debug("%s: %s (%x, %x)\n", __func__, -+ tc358743_formats[ifmt].description, -+ tc358743_formats[ifmt].pixelformat, -+ tc358743_formats[ifmt].flags); -+ return tc358743_formats[ifmt].pixelformat; -+} -+ -+int set_frame_rate_mode(struct tc_data *td, -+ enum tc358743_frame_rate frame_rate, enum tc358743_mode mode) -+{ -+ struct sensor_data *sensor = &td->sensor; -+ const struct reg_value *pModeSetting = NULL; -+ s32 i = 0; -+ s32 iModeSettingArySize = 0; -+ register u32 RepeateLines = 0; -+ register int RepeateTimes = 0; -+ register u32 Delay_ms = 0; -+ register u16 RegAddr = 0; -+ register u32 Mask = 0; -+ register u32 Val = 0; -+ u8 Length; -+ int retval = 0; -+ -+ pModeSetting = -+ tc358743_mode_info_data[frame_rate][mode].init_data_ptr; -+ iModeSettingArySize = -+ tc358743_mode_info_data[frame_rate][mode].init_data_size; -+ -+ sensor->pix.pixelformat = get_pixelformat(frame_rate, mode); -+ sensor->pix.width = -+ tc358743_mode_info_data[frame_rate][mode].width; -+ sensor->pix.height = -+ tc358743_mode_info_data[frame_rate][mode].height; -+ pr_debug("%s: Set %d regs from %p for frs %d mode %d with width %d height %d\n", __func__, -+ iModeSettingArySize, -+ pModeSetting, -+ frame_rate, -+ mode, -+ sensor->pix.width, -+ sensor->pix.height); -+ for (i = 0; i < iModeSettingArySize; ++i) { -+ pModeSetting = tc358743_mode_info_data[frame_rate][mode].init_data_ptr + i; -+ -+ Delay_ms = pModeSetting->u32Delay_ms & (0xffff); -+ RegAddr = pModeSetting->u16RegAddr; -+ Val = pModeSetting->u32Val; -+ Mask = pModeSetting->u32Mask; -+ Length = pModeSetting->u8Length; -+ if (Mask) { -+ u32 RegVal = 0; -+ -+ retval = tc358743_read_reg(sensor, RegAddr, &RegVal); -+ if (retval < 0) { -+ pr_err("%s: read failed, reg=0x%x\n", __func__, RegAddr); -+ return retval; -+ } -+ RegVal &= ~(u8)Mask; -+ Val &= Mask; -+ Val |= RegVal; -+ } -+ -+ retval = tc358743_write_reg(sensor, RegAddr, Val, Length); -+ if (retval < 0) { -+ pr_err("%s: write failed, reg=0x%x\n", __func__, RegAddr); -+ return retval; -+ } -+ if (Delay_ms) -+ msleep(Delay_ms); -+ -+ if (0 != ((pModeSetting->u32Delay_ms>>16) & (0xff))) { -+ if (!RepeateTimes) { -+ RepeateTimes = (pModeSetting->u32Delay_ms>>16) & (0xff); -+ RepeateLines = (pModeSetting->u32Delay_ms>>24) & (0xff); -+ } -+ if (--RepeateTimes > 0) { -+ i -= RepeateLines; -+ } -+ } -+ } -+ tc358743_enable_edid(sensor); -+ if (!td->edid_initialized) { -+ retval = tc358743_write_edid(sensor, cHDMIEDID, ARRAY_SIZE(cHDMIEDID)); -+ if (retval) -+ pr_err("%s: Fail to write EDID(%d) to tc35874!\n", __func__, retval); -+ else -+ td->edid_initialized = 1; -+ } -+ -+ return retval; -+} -+ -+void mipi_csi2_swreset(struct mipi_csi2_info *info); -+#include "../../../../mxc/mipi/mxc_mipi_csi2.h" -+ -+int mipi_reset(void *mipi_csi2_info, -+ enum tc358743_frame_rate frame_rate, -+ enum tc358743_mode mode) -+{ -+ int lanes = tc358743_mode_info_data[frame_rate][mode].lanes; -+ -+ if (!lanes) -+ lanes = 4; -+ -+ pr_debug("%s: mipi_csi2_info:\n" -+ "mipi_en: %d\n" -+ "datatype: %d\n" -+ "dphy_clk: %p\n" -+ "pixel_clk: %p\n" -+ "mipi_csi2_base:%p\n" -+ "pdev: %p\n" -+ , __func__, -+ ((struct mipi_csi2_info *)mipi_csi2_info)->mipi_en, -+ ((struct mipi_csi2_info *)mipi_csi2_info)->datatype, -+ ((struct mipi_csi2_info *)mipi_csi2_info)->dphy_clk, -+ ((struct mipi_csi2_info *)mipi_csi2_info)->pixel_clk, -+ ((struct mipi_csi2_info *)mipi_csi2_info)->mipi_csi2_base, -+ ((struct mipi_csi2_info *)mipi_csi2_info)->pdev -+ ); -+ if (mipi_csi2_get_status(mipi_csi2_info)) { -+ mipi_csi2_disable(mipi_csi2_info); -+ msleep(1); -+ } -+ mipi_csi2_enable(mipi_csi2_info); -+ -+ if (!mipi_csi2_get_status(mipi_csi2_info)) { -+ pr_err("Can not enable mipi csi2 driver!\n"); -+ return -1; -+ } -+ lanes = mipi_csi2_set_lanes(mipi_csi2_info, lanes); -+ pr_debug("Now Using %d lanes\n", lanes); -+ -+ mipi_csi2_reset(mipi_csi2_info); -+ mipi_csi2_set_datatype(mipi_csi2_info, tc358743_mode_info_data[frame_rate][mode].flags); -+ return 0; -+} -+ -+int mipi_wait(void *mipi_csi2_info) -+{ -+ unsigned i = 0; -+ unsigned j; -+ u32 mipi_reg; -+ u32 mipi_reg_test[10]; -+ -+ /* wait for mipi sensor ready */ -+ for (;;) { -+ mipi_reg = mipi_csi2_dphy_status(mipi_csi2_info); -+ mipi_reg_test[i++] = mipi_reg; -+ if (mipi_reg != 0x200) -+ break; -+ if (i >= 10) { -+ pr_err("mipi csi2 can not receive sensor clk!\n"); -+ return -1; -+ } -+ msleep(10); -+ } -+ -+ for (j = 0; j < i; j++) { -+ pr_debug("%d mipi csi2 dphy status %x\n", j, mipi_reg_test[j]); -+ } -+ -+ i = 0; -+ -+ /* wait for mipi stable */ -+ for (;;) { -+ mipi_reg = mipi_csi2_get_error1(mipi_csi2_info); -+ mipi_reg_test[i++] = mipi_reg; -+ if (!mipi_reg) -+ break; -+ if (i >= 10) { -+ pr_err("mipi csi2 can not reveive data correctly!\n"); -+ return -1; -+ } -+ msleep(10); -+ } -+ -+ for (j = 0; j < i; j++) { -+ pr_debug("%d mipi csi2 err1 %x\n", j, mipi_reg_test[j]); -+ } -+ return 0; -+} -+ -+static int tc358743_init_mode(struct tc_data *td, -+ enum tc358743_frame_rate frame_rate, -+ enum tc358743_mode mode) -+{ -+ struct sensor_data *sensor = &td->sensor; -+ int retval = 0; -+ void *mipi_csi2_info; -+ -+ pr_debug("%s rate: %d mode: %d\n", __func__, frame_rate, mode); -+ if ((mode >= tc358743_mode_MAX || mode < 0) -+ && (mode != tc358743_mode_INIT)) { -+ pr_debug("%s Wrong tc358743 mode detected! %d. Set mode 0\n", __func__, mode); -+ mode = 0; -+ } -+ /* initial mipi dphy */ -+ tc358743_toggle_hpd(sensor, 0); -+ tc358743_software_reset(sensor); -+ -+ mipi_csi2_info = mipi_csi2_get_info(); -+ pr_debug("%s rate: %d mode: %d, info %p\n", __func__, frame_rate, mode, mipi_csi2_info); -+ -+ if (!mipi_csi2_info) { -+ pr_err("Fail to get mipi_csi2_info!\n"); -+ return -1; -+ } -+ retval = mipi_reset(mipi_csi2_info, frame_rate, tc358743_mode_INIT); -+ if (retval) -+ return retval; -+ retval = set_frame_rate_mode(td, frame_rate, tc358743_mode_INIT); -+ if (retval) -+ return retval; -+ retval = mipi_wait(mipi_csi2_info); -+ -+ if (mode != tc358743_mode_INIT) { -+ tc358743_software_reset(sensor); -+ retval = mipi_reset(mipi_csi2_info, frame_rate, mode); -+ if (retval) -+ return retval; -+ retval = set_frame_rate_mode(td, frame_rate, mode); -+ if (retval) -+ return retval; -+ retval = mipi_wait(mipi_csi2_info); -+ } -+ if (td->hpd_active) -+ tc358743_toggle_hpd(sensor, td->hpd_active); -+ return retval; -+} -+ -+static int tc358743_minit(struct tc_data *td) -+{ -+ struct sensor_data *sensor = &td->sensor; -+ int ret; -+ enum tc358743_frame_rate frame_rate = tc358743_60_fps; -+ u32 tgt_fps = sensor->streamcap.timeperframe.denominator / -+ sensor->streamcap.timeperframe.numerator; -+ -+ if (tgt_fps == 60) -+ frame_rate = tc358743_60_fps; -+ else if (tgt_fps == 30) -+ frame_rate = tc358743_30_fps; -+ -+ pr_debug("%s: capture mode: %d fps: %d\n", __func__, -+ sensor->streamcap.capturemode, tgt_fps); -+ -+ ret = tc358743_init_mode(td, frame_rate, sensor->streamcap.capturemode); -+ if (ret) -+ pr_err("%s: Fail to init tc35874!\n", __func__); -+ return ret; -+} -+ -+static int tc358743_reset(struct tc_data *td) -+{ -+ int loop = 0; -+ int ret; -+ -+ det_work_enable(td, 0); -+ for (;;) { -+ pr_debug("%s: RESET\n", __func__); -+ power_control(td, 0); -+ mdelay(100); -+ power_control(td, 1); -+ mdelay(1000); -+ -+ ret = tc358743_minit(td); -+ if (!ret) -+ break; -+ if (loop++ >= 3) { -+ pr_err("%s:failed(%d)\n", __func__, ret); -+ break; -+ } -+ } -+ det_work_enable(td, 1); -+ return ret; -+} -+ -+/* --------------- IOCTL functions from v4l2_int_ioctl_desc --------------- */ -+ -+static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p) -+{ -+ struct tc_data *td = s->priv; -+ struct sensor_data *sensor = &td->sensor; -+ -+ pr_debug("%s\n", __func__); -+ -+ memset(p, 0, sizeof(*p)); -+ p->u.bt656.clock_curr = TC358743_XCLK_MIN; //sensor->mclk; -+ pr_debug("%s: clock_curr=mclk=%d\n", __func__, sensor->mclk); -+ p->if_type = V4L2_IF_TYPE_BT656; -+ p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT; -+ p->u.bt656.clock_min = TC358743_XCLK_MIN; -+ p->u.bt656.clock_max = TC358743_XCLK_MAX; -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_s_power - V4L2 sensor interface handler for VIDIOC_S_POWER ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @on: indicates power mode (on or off) -+ * -+ * Turns the power on or off, depending on the value of on and returns the -+ * appropriate error code. -+ */ -+static int ioctl_s_power(struct v4l2_int_device *s, int on) -+{ -+ struct tc_data *td = s->priv; -+ int ret; -+ -+ mutex_lock(&td->access_lock); -+ if (on && !td->mode) { -+ ret = tc358743_reset(td); -+ } else { -+ ret = power_control(td, on); -+ } -+ mutex_unlock(&td->access_lock); -+ return ret; -+} -+ -+/*! -+ * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure -+ * -+ * Returns the sensor's video CAPTURE parameters. -+ */ -+static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) -+{ -+ struct tc_data *td = s->priv; -+ struct sensor_data *sensor = &td->sensor; -+ struct v4l2_captureparm *cparm = &a->parm.capture; -+ int ret = 0; -+ -+ pr_debug("%s type: %x\n", __func__, a->type); -+ switch (a->type) { -+ /* This is the only case currently handled. */ -+ case V4L2_BUF_TYPE_VIDEO_CAPTURE: -+ memset(a, 0, sizeof(*a)); -+ a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; -+ cparm->capability = sensor->streamcap.capability; -+ cparm->timeperframe = sensor->streamcap.timeperframe; -+ cparm->capturemode = sensor->streamcap.capturemode; -+ cparm->extendedmode = sensor->streamcap.extendedmode; -+ ret = 0; -+ break; -+ -+ /* These are all the possible cases. */ -+ case V4L2_BUF_TYPE_VIDEO_OUTPUT: -+ case V4L2_BUF_TYPE_VIDEO_OVERLAY: -+ case V4L2_BUF_TYPE_VBI_CAPTURE: -+ case V4L2_BUF_TYPE_VBI_OUTPUT: -+ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: -+ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: -+ ret = -EINVAL; -+ break; -+ -+ default: -+ pr_debug(" type is unknown - %d\n", a->type); -+ ret = -EINVAL; -+ break; -+ } -+ pr_debug("%s done %d\n", __func__, ret); -+ return ret; -+} -+ -+/*! -+ * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure -+ * -+ * Configures the sensor to use the input parameters, if possible. If -+ * not possible, reverts to the old parameters and returns the -+ * appropriate error code. -+ */ -+static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) -+{ -+ struct tc_data *td = s->priv; -+ struct sensor_data *sensor = &td->sensor; -+ struct v4l2_fract *timeperframe = &a->parm.capture.timeperframe; -+ u32 tgt_fps; /* target frames per secound */ -+ enum tc358743_frame_rate frame_rate = tc358743_60_fps, frame_rate_now = tc358743_60_fps; -+ enum tc358743_mode mode; -+ int ret = 0; -+ -+ pr_debug("%s\n", __func__); -+ mutex_lock(&td->access_lock); -+ det_work_enable(td, 0); -+ /* Make sure power on */ -+ power_control(td, 1); -+ -+ switch (a->type) { -+ /* This is the only case currently handled. */ -+ case V4L2_BUF_TYPE_VIDEO_CAPTURE: -+ /* Check that the new frame rate is allowed. */ -+ if ((timeperframe->numerator == 0) || -+ (timeperframe->denominator == 0)) { -+ timeperframe->denominator = DEFAULT_FPS; -+ timeperframe->numerator = 1; -+ } -+ -+ tgt_fps = timeperframe->denominator / -+ timeperframe->numerator; -+ -+ if (tgt_fps > MAX_FPS) { -+ timeperframe->denominator = MAX_FPS; -+ timeperframe->numerator = 1; -+ } else if (tgt_fps < MIN_FPS) { -+ timeperframe->denominator = MIN_FPS; -+ timeperframe->numerator = 1; -+ } -+ -+ /* Actual frame rate we use */ -+ tgt_fps = timeperframe->denominator / -+ timeperframe->numerator; -+ -+ if (tgt_fps == 60) -+ frame_rate = tc358743_60_fps; -+ else if (tgt_fps == 30) -+ frame_rate = tc358743_30_fps; -+ else { -+ pr_err(" The camera frame rate is not supported!\n"); -+ ret = -EINVAL; -+ break; -+ } -+ -+ if ((u32)a->parm.capture.capturemode >= tc358743_mode_MAX) { -+ a->parm.capture.capturemode = 0; -+ pr_debug("%s: Force mode: %d \n", __func__, -+ (u32)a->parm.capture.capturemode); -+ } -+ -+ tgt_fps = sensor->streamcap.timeperframe.denominator / -+ sensor->streamcap.timeperframe.numerator; -+ -+ if (tgt_fps == 60) -+ frame_rate_now = tc358743_60_fps; -+ else if (tgt_fps == 30) -+ frame_rate_now = tc358743_30_fps; -+ -+ mode = td->mode; -+ if (IS_COLORBAR(mode)) { -+ mode = (u32)a->parm.capture.capturemode; -+ } else { -+ a->parm.capture.capturemode = mode; -+ frame_rate = td->fps; -+ timeperframe->denominator = (frame_rate == tc358743_60_fps) ? 60 : 30; -+ timeperframe->numerator = 1; -+ } -+ -+ if (frame_rate_now != frame_rate || -+ sensor->streamcap.capturemode != mode || -+ sensor->streamcap.extendedmode != (u32)a->parm.capture.extendedmode) { -+ -+ if (mode != tc358743_mode_INIT) { -+ sensor->streamcap.capturemode = mode; -+ sensor->streamcap.timeperframe = *timeperframe; -+ sensor->streamcap.extendedmode = -+ (u32)a->parm.capture.extendedmode; -+ pr_debug("%s: capture mode: %d\n", __func__, -+ mode); -+ ret = tc358743_init_mode(td, frame_rate, mode); -+ } else { -+ a->parm.capture.capturemode = sensor->streamcap.capturemode; -+ *timeperframe = sensor->streamcap.timeperframe; -+ a->parm.capture.extendedmode = sensor->streamcap.extendedmode; -+ } -+ } else { -+ pr_debug("%s: Keep current settings\n", __func__); -+ } -+ break; -+ -+ /* These are all the possible cases. */ -+ case V4L2_BUF_TYPE_VIDEO_OUTPUT: -+ case V4L2_BUF_TYPE_VIDEO_OVERLAY: -+ case V4L2_BUF_TYPE_VBI_CAPTURE: -+ case V4L2_BUF_TYPE_VBI_OUTPUT: -+ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: -+ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: -+ pr_debug(" type is not " \ -+ "V4L2_BUF_TYPE_VIDEO_CAPTURE but %d\n", -+ a->type); -+ ret = -EINVAL; -+ break; -+ -+ default: -+ pr_debug(" type is unknown - %d\n", a->type); -+ ret = -EINVAL; -+ break; -+ } -+ -+ det_work_enable(td, 1); -+ mutex_unlock(&td->access_lock); -+ return ret; -+} -+ -+/*! -+ * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure -+ * -+ * If the requested control is supported, returns the control's current -+ * value from the video_control[] array. Otherwise, returns -EINVAL -+ * if the control is not supported. -+ */ -+static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) -+{ -+ struct tc_data *td = s->priv; -+ struct sensor_data *sensor = &td->sensor; -+ int ret = 0; -+ -+ pr_debug("%s\n", __func__); -+ switch (vc->id) { -+ case V4L2_CID_BRIGHTNESS: -+ vc->value = sensor->brightness; -+ break; -+ case V4L2_CID_HUE: -+ vc->value = sensor->hue; -+ break; -+ case V4L2_CID_CONTRAST: -+ vc->value = sensor->contrast; -+ break; -+ case V4L2_CID_SATURATION: -+ vc->value = sensor->saturation; -+ break; -+ case V4L2_CID_RED_BALANCE: -+ vc->value = sensor->red; -+ break; -+ case V4L2_CID_BLUE_BALANCE: -+ vc->value = sensor->blue; -+ break; -+ case V4L2_CID_EXPOSURE: -+ vc->value = sensor->ae_mode; -+ break; -+ default: -+ ret = -EINVAL; -+ } -+ -+ return ret; -+} -+ -+/*! -+ * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure -+ * -+ * If the requested control is supported, sets the control's current -+ * value in HW (and updates the video_control[] array). Otherwise, -+ * returns -EINVAL if the control is not supported. -+ */ -+static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) -+{ -+ int retval = 0; -+ -+ pr_debug("In tc358743:ioctl_s_ctrl %d\n", -+ vc->id); -+ -+ switch (vc->id) { -+ case V4L2_CID_BRIGHTNESS: -+ break; -+ case V4L2_CID_CONTRAST: -+ break; -+ case V4L2_CID_SATURATION: -+ break; -+ case V4L2_CID_HUE: -+ break; -+ case V4L2_CID_AUTO_WHITE_BALANCE: -+ break; -+ case V4L2_CID_DO_WHITE_BALANCE: -+ break; -+ case V4L2_CID_RED_BALANCE: -+ break; -+ case V4L2_CID_BLUE_BALANCE: -+ break; -+ case V4L2_CID_GAMMA: -+ break; -+ case V4L2_CID_EXPOSURE: -+ break; -+ case V4L2_CID_AUTOGAIN: -+ break; -+ case V4L2_CID_GAIN: -+ break; -+ case V4L2_CID_HFLIP: -+ break; -+ case V4L2_CID_VFLIP: -+ break; -+ default: -+ retval = -EPERM; -+ break; -+ } -+ -+ return retval; -+} -+ -+/*! -+ * ioctl_enum_framesizes - V4L2 sensor interface handler for -+ * VIDIOC_ENUM_FRAMESIZES ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure -+ * -+ * Return 0 if successful, otherwise -EINVAL. -+ */ -+static int ioctl_enum_framesizes(struct v4l2_int_device *s, -+ struct v4l2_frmsizeenum *fsize) -+{ -+ struct tc_data *td = s->priv; -+ enum tc358743_mode query_mode= fsize->index; -+ enum tc358743_mode mode = td->mode; -+ -+ if (IS_COLORBAR(mode)) { -+ if (query_mode > MAX_COLORBAR) -+ return -EINVAL; -+ mode = query_mode; -+ } else { -+ if (query_mode) -+ return -EINVAL; -+ } -+ pr_debug("%s, mode: %d\n", __func__, mode); -+ -+ fsize->pixel_format = get_pixelformat(0, mode); -+ fsize->discrete.width = -+ tc358743_mode_info_data[0][mode].width; -+ fsize->discrete.height = -+ tc358743_mode_info_data[0][mode].height; -+ pr_debug("%s %d:%d format: %x\n", __func__, fsize->discrete.width, fsize->discrete.height, fsize->pixel_format); -+ return 0; -+} -+ -+/*! -+ * ioctl_g_chip_ident - V4L2 sensor interface handler for -+ * VIDIOC_DBG_G_CHIP_IDENT ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @id: pointer to int -+ * -+ * Return 0. -+ */ -+static int ioctl_g_chip_ident(struct v4l2_int_device *s, int *id) -+{ -+ ((struct v4l2_dbg_chip_ident *)id)->match.type = -+ V4L2_CHIP_MATCH_I2C_DRIVER; -+ strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name, -+ "tc358743_mipi"); -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT -+ * @s: pointer to standard V4L2 device structure -+ */ -+static int ioctl_init(struct v4l2_int_device *s) -+{ -+ pr_debug("%s\n", __func__); -+ return 0; -+} -+ -+/*! -+ * ioctl_enum_fmt_cap - V4L2 sensor interface handler for VIDIOC_ENUM_FMT -+ * @s: pointer to standard V4L2 device structure -+ * @fmt: pointer to standard V4L2 fmt description structure -+ * -+ * Return 0. -+ */ -+static int ioctl_enum_fmt_cap(struct v4l2_int_device *s, -+ struct v4l2_fmtdesc *fmt) -+{ -+ struct tc_data *td = s->priv; -+ struct sensor_data *sensor = &td->sensor; -+ int index = fmt->index; -+ -+ if (!index) -+ index = sensor->streamcap.capturemode; -+ pr_debug("%s, INDEX: %d\n", __func__, index); -+ if (index >= tc358743_mode_MAX) -+ return -EINVAL; -+ -+ fmt->pixelformat = get_pixelformat(0, index); -+ -+ pr_debug("%s: format: %x\n", __func__, fmt->pixelformat); -+ return 0; -+} -+ -+static int ioctl_try_fmt_cap(struct v4l2_int_device *s, -+ struct v4l2_format *f) -+{ -+ struct tc_data *td = s->priv; -+ struct sensor_data *sensor = &td->sensor; -+ u32 tgt_fps; /* target frames per secound */ -+ enum tc358743_frame_rate frame_rate; -+// enum image_size isize; -+ int ret = 0; -+ struct v4l2_pix_format *pix = &f->fmt.pix; -+ int mode; -+ -+ pr_debug("%s\n", __func__); -+ -+ mutex_lock(&td->access_lock); -+ tgt_fps = sensor->streamcap.timeperframe.denominator / -+ sensor->streamcap.timeperframe.numerator; -+ -+ if (tgt_fps == 60) { -+ frame_rate = tc358743_60_fps; -+ } else if (tgt_fps == 30) { -+ frame_rate = tc358743_30_fps; -+ } else { -+ pr_debug("%s: %d fps (%d,%d) is not supported\n", __func__, tgt_fps, sensor->streamcap.timeperframe.denominator,sensor->streamcap.timeperframe.numerator); -+ ret = -EINVAL; -+ goto out; -+ } -+ mode = sensor->streamcap.capturemode; -+ sensor->pix.pixelformat = get_pixelformat(frame_rate, mode); -+ sensor->pix.width = pix->width = tc358743_mode_info_data[frame_rate][mode].width; -+ sensor->pix.height = pix->height = tc358743_mode_info_data[frame_rate][mode].height; -+ pr_debug("%s: %dx%d\n", __func__, sensor->pix.width, sensor->pix.height); -+ -+ pix->pixelformat = sensor->pix.pixelformat; -+ pix->field = V4L2_FIELD_NONE; -+ pix->bytesperline = pix->width * 4; -+ pix->sizeimage = pix->bytesperline * pix->height; -+ pix->priv = 0; -+ -+ switch (pix->pixelformat) { -+ case V4L2_PIX_FMT_UYVY: -+ default: -+ pix->colorspace = V4L2_COLORSPACE_SRGB; -+ break; -+ } -+ -+ { -+ pr_debug("SYS_STATUS: 0x%x\n", tc358743_read_reg_val(sensor, 0x8520)); -+ pr_debug("VI_STATUS0: 0x%x\n", tc358743_read_reg_val(sensor, 0x8521)); -+ pr_debug("VI_STATUS1: 0x%x\n", tc358743_read_reg_val(sensor, 0x8522)); -+ pr_debug("VI_STATUS2: 0x%x\n", tc358743_read_reg_val(sensor, 0x8525)); -+ pr_debug("VI_STATUS3: 0x%x\n", tc358743_read_reg_val(sensor, 0x8528)); -+ pr_debug("%s %d:%d format: %x\n", __func__, pix->width, pix->height, pix->pixelformat); -+ } -+out: -+ mutex_unlock(&td->access_lock); -+ return ret; -+} -+ -+/*! -+ * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap -+ * @s: pointer to standard V4L2 device structure -+ * @f: pointer to standard V4L2 v4l2_format structure -+ * -+ * Returns the sensor's current pixel format in the v4l2_format -+ * parameter. -+ */ -+static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) -+{ -+ struct tc_data *td = s->priv; -+ struct sensor_data *sensor = &td->sensor; -+ int mode = sensor->streamcap.capturemode; -+ -+ sensor->pix.pixelformat = get_pixelformat(0, mode); -+ sensor->pix.width = tc358743_mode_info_data[0][mode].width; -+ sensor->pix.height = tc358743_mode_info_data[0][mode].height; -+ -+ switch (f->type) { -+ case V4L2_BUF_TYPE_VIDEO_CAPTURE: -+ f->fmt.pix = sensor->pix; -+ pr_debug("%s: %dx%d\n", __func__, sensor->pix.width, sensor->pix.height); -+ break; -+ -+ case V4L2_BUF_TYPE_SENSOR: -+ pr_debug("%s: left=%d, top=%d, %dx%d\n", __func__, -+ sensor->spix.left, sensor->spix.top, -+ sensor->spix.swidth, sensor->spix.sheight); -+ f->fmt.spix = sensor->spix; -+ break; -+ -+ case V4L2_BUF_TYPE_PRIVATE: -+ pr_debug("%s: private\n", __func__); -+ break; -+ -+ default: -+ f->fmt.pix = sensor->pix; -+ pr_debug("%s: type=%d, %dx%d\n", __func__, f->type, sensor->pix.width, sensor->pix.height); -+ break; -+ } -+ return 0; -+} -+ -+/*! -+ * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num -+ * @s: pointer to standard V4L2 device structure -+ * -+ * Initialise the device when slave attaches to the master. -+ */ -+static int ioctl_dev_init(struct v4l2_int_device *s) -+{ -+ struct tc_data *td = s->priv; -+ -+ if (td->det_changed) { -+ mutex_lock(&td->access_lock); -+ td->det_changed = 0; -+ pr_debug("%s\n", __func__); -+ tc358743_minit(td); -+ mutex_unlock(&td->access_lock); -+ } -+ pr_debug("%s\n", __func__); -+ return 0; -+} -+ -+/*! -+ * ioctl_dev_exit - V4L2 sensor interface handler for vidioc_int_dev_exit_num -+ * @s: pointer to standard V4L2 device structure -+ * -+ * Delinitialise the device when slave detaches to the master. -+ */ -+static int ioctl_dev_exit(struct v4l2_int_device *s) -+{ -+ void *mipi_csi2_info; -+ -+ mipi_csi2_info = mipi_csi2_get_info(); -+ -+ /* disable mipi csi2 */ -+ if (mipi_csi2_info) -+ if (mipi_csi2_get_status(mipi_csi2_info)) -+ mipi_csi2_disable(mipi_csi2_info); -+ -+ return 0; -+} -+ -+/*! -+ * This structure defines all the ioctls for this module and links them to the -+ * enumeration. -+ */ -+static struct v4l2_int_ioctl_desc tc358743_ioctl_desc[] = { -+ {vidioc_int_dev_init_num, (v4l2_int_ioctl_func*) ioctl_dev_init}, -+ {vidioc_int_dev_exit_num, ioctl_dev_exit}, -+ {vidioc_int_s_power_num, (v4l2_int_ioctl_func*) ioctl_s_power}, -+ {vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func*) ioctl_g_ifparm}, -+ {vidioc_int_init_num, (v4l2_int_ioctl_func*) ioctl_init}, -+ {vidioc_int_enum_fmt_cap_num, -+ (v4l2_int_ioctl_func *) ioctl_enum_fmt_cap}, -+ {vidioc_int_try_fmt_cap_num, -+ (v4l2_int_ioctl_func *)ioctl_try_fmt_cap}, -+ {vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func *) ioctl_g_fmt_cap}, -+ {vidioc_int_g_parm_num, (v4l2_int_ioctl_func *) ioctl_g_parm}, -+ {vidioc_int_s_parm_num, (v4l2_int_ioctl_func *) ioctl_s_parm}, -+ {vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func *) ioctl_g_ctrl}, -+ {vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func *) ioctl_s_ctrl}, -+ {vidioc_int_enum_framesizes_num, -+ (v4l2_int_ioctl_func *) ioctl_enum_framesizes}, -+ {vidioc_int_g_chip_ident_num, -+ (v4l2_int_ioctl_func *) ioctl_g_chip_ident}, -+}; -+ -+static struct v4l2_int_slave tc358743_slave = { -+ .ioctls = tc358743_ioctl_desc, -+ .num_ioctls = ARRAY_SIZE(tc358743_ioctl_desc), -+}; -+ -+static struct v4l2_int_device tc358743_int_device = { -+ .module = THIS_MODULE, -+ .name = "tc358743", -+ .type = v4l2_int_type_slave, -+ .u = { -+ .slave = &tc358743_slave, -+ }, -+}; -+ -+ -+#ifdef CONFIG_TC358743_AUDIO -+struct imx_ssi { -+ struct platform_device *ac97_dev; -+ -+ struct snd_soc_dai *imx_ac97; -+ struct clk *clk; -+ void __iomem *base; -+ int irq; -+ int fiq_enable; -+ unsigned int offset; -+ -+ unsigned int flags; -+ -+ void (*ac97_reset) (struct snd_ac97 *ac97); -+ void (*ac97_warm_reset)(struct snd_ac97 *ac97); -+ -+ struct imx_pcm_dma_params dma_params_rx; -+ struct imx_pcm_dma_params dma_params_tx; -+ -+ int enabled; -+ -+ struct platform_device *soc_platform_pdev; -+ struct platform_device *soc_platform_pdev_fiq; -+}; -+#define SSI_SCR 0x10 -+#define SSI_SRCR 0x20 -+#define SSI_STCCR 0x24 -+#define SSI_SRCCR 0x28 -+#define SSI_SCR_I2S_MODE_NORM (0 << 5) -+#define SSI_SCR_I2S_MODE_MSTR (1 << 5) -+#define SSI_SCR_I2S_MODE_SLAVE (2 << 5) -+#define SSI_I2S_MODE_MASK (3 << 5) -+#define SSI_SCR_SYN (1 << 4) -+#define SSI_SRCR_RSHFD (1 << 4) -+#define SSI_SRCR_RSCKP (1 << 3) -+#define SSI_SRCR_RFSI (1 << 2) -+#define SSI_SRCR_REFS (1 << 0) -+#define SSI_STCCR_WL(x) ((((x) - 2) >> 1) << 13) -+#define SSI_STCCR_WL_MASK (0xf << 13) -+#define SSI_SRCCR_WL(x) ((((x) - 2) >> 1) << 13) -+#define SSI_SRCCR_WL_MASK (0xf << 13) -+/* Audio setup */ -+ -+static int imxpac_tc358743_hw_params(struct snd_pcm_substream *substream, -+ struct snd_pcm_hw_params *params) -+{ -+ struct snd_soc_pcm_runtime *rtd = substream->private_data; -+ struct snd_soc_dai *codec_dai = rtd->codec_dai; -+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai; -+ int ret; -+ -+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | -+ SND_SOC_DAIFMT_NB_IF | -+ SND_SOC_DAIFMT_CBM_CFM); -+ if (ret) { -+ pr_err("%s: failed set cpu dai format\n", __func__); -+ return ret; -+ } -+ -+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | -+ SND_SOC_DAIFMT_NB_NF | -+ SND_SOC_DAIFMT_CBM_CFM); -+ if (ret) { -+ pr_err("%s: failed set codec dai format\n", __func__); -+ return ret; -+ } -+ -+ ret = snd_soc_dai_set_sysclk(codec_dai, 0, -+ CODEC_CLOCK, SND_SOC_CLOCK_OUT); -+ if (ret) { -+ pr_err("%s: failed setting codec sysclk\n", __func__); -+ return ret; -+ } -+ snd_soc_dai_set_tdm_slot(cpu_dai, 0xffffffc, 0xffffffc, 2, 0); -+ -+ ret = snd_soc_dai_set_sysclk(cpu_dai, IMX_SSP_SYS_CLK, 0, -+ SND_SOC_CLOCK_IN); -+ if (ret) { -+ pr_err("can't set CPU system clock IMX_SSP_SYS_CLK\n"); -+ return ret; -+ } -+#if 1 -+// clear SSI_SRCR_RXBIT0 and SSI_SRCR_RSHFD in order to push Right-justified MSB data fro -+ { -+ struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai); -+ u32 scr = 0, srcr = 0, stccr = 0, srccr = 0; -+ -+ pr_debug("%s: base %p\n", __func__, (void *)ssi->base); -+ scr = readl(ssi->base + SSI_SCR); -+ pr_debug("%s: SSI_SCR before: %p\n", __func__, (void *)scr); -+ writel(scr, ssi->base + SSI_SCR); -+ pr_debug("%s: SSI_SCR after: %p\n", __func__, (void *)scr); -+ -+ srcr = readl(ssi->base + SSI_SRCR); -+ pr_debug("%s: SSI_SRCR before: %p\n", __func__, (void *)srcr); -+ writel(srcr, ssi->base + SSI_SRCR); -+ pr_debug("%s: SSI_SRCR after: %p\n", __func__, (void *)srcr); -+ -+ stccr = readl(ssi->base + SSI_STCCR); -+ pr_debug("%s: SSI_STCCR before: %p\n", __func__, (void *)stccr); -+ stccr &= ~SSI_STCCR_WL_MASK; -+ stccr |= SSI_STCCR_WL(16); -+ writel(stccr, ssi->base + SSI_STCCR); -+ pr_debug("%s: SSI_STCCR after: %p\n", __func__, (void *)stccr); -+ -+ srccr = readl(ssi->base + SSI_SRCCR); -+ pr_debug("%s: SSI_SRCCR before: %p\n", __func__, (void *)srccr); -+ srccr &= ~SSI_SRCCR_WL_MASK; -+ srccr |= SSI_SRCCR_WL(16); -+ writel(srccr, ssi->base + SSI_SRCCR); -+ pr_debug("%s: SSI_SRCCR after: %p\n", __func__, (void *)srccr); -+ } -+#endif -+ return 0; -+} -+ -+ -+ -+/* imx_3stack card dapm widgets */ -+static const struct snd_soc_dapm_widget imx_3stack_dapm_widgets_a[] = { -+}; -+ -+ -+ -+static const struct snd_kcontrol_new tc358743_machine_controls_a[] = { -+}; -+ -+/* imx_3stack machine connections to the codec pins */ -+static const struct snd_soc_dapm_route audio_map_a[] = { -+}; -+ -+static int imx_3stack_tc358743_init(struct snd_soc_pcm_runtime *rtd) -+{ -+ struct snd_soc_codec *codec = rtd->codec; -+ int ret; -+ -+ const struct snd_soc_dapm_widget *imx_3stack_dapm_widgets; -+ int imx_3stack_dapm_widgets_size; -+ const struct snd_kcontrol_new *tc358743_machine_controls; -+ int tc358743_machine_controls_size; -+ const struct snd_soc_dapm_route *audio_map; -+ int audio_map_size; -+ int gpio_num = -1; -+ char *gpio_name; -+ -+ pr_debug("%s started\n", __func__); -+ -+ imx_3stack_dapm_widgets = imx_3stack_dapm_widgets_a; -+ imx_3stack_dapm_widgets_size = ARRAY_SIZE(imx_3stack_dapm_widgets_a); -+ tc358743_machine_controls = tc358743_machine_controls_a; -+ tc358743_machine_controls_size = ARRAY_SIZE(tc358743_machine_controls_a); -+ audio_map = audio_map_a; -+ audio_map_size = ARRAY_SIZE(audio_map_a); -+ gpio_num = -1; //card_a_gpio_num; -+ gpio_name = NULL; -+ -+ ret = snd_soc_add_controls(codec, tc358743_machine_controls, -+ tc358743_machine_controls_size); -+ if (ret) { -+ pr_err("%s: snd_soc_add_controls failed. err = %d\n", __func__, ret); -+ return ret; -+ } -+ /* Add imx_3stack specific widgets */ -+ snd_soc_dapm_new_controls(&codec->dapm, imx_3stack_dapm_widgets, -+ imx_3stack_dapm_widgets_size); -+ -+ /* Set up imx_3stack specific audio path audio_map */ -+ snd_soc_dapm_add_routes(&codec->dapm, audio_map, audio_map_size); -+ snd_soc_dapm_sync(&codec->dapm); -+ return 0; -+} -+ -+ -+static struct snd_soc_ops imxpac_tc358743_snd_ops = { -+ .hw_params = imxpac_tc358743_hw_params, -+}; -+ -+static struct snd_soc_dai_link imxpac_tc358743_dai = { -+ .name = "tc358743", -+ .stream_name = "TC358743", -+ .codec_dai_name = "tc358743-hifi", -+ .platform_name = "imx-pcm-audio.2", -+ .codec_name = "tc358743_mipi.1-000f", -+ .cpu_dai_name = "imx-ssi.2", -+ .init = imx_3stack_tc358743_init, -+ .ops = &imxpac_tc358743_snd_ops, -+}; -+ -+static struct snd_soc_card imxpac_tc358743 = { -+ .name = "cpuimx-audio_hdmi_in", -+ .dai_link = &imxpac_tc358743_dai, -+ .num_links = 1, -+}; -+ -+static int imx_audmux_config(int slave, int master) -+{ -+ unsigned int ptcr, pdcr; -+ slave = slave - 1; -+ master = master - 1; -+ -+ /* SSI0 mastered by port 5 */ -+ ptcr = MXC_AUDMUX_V2_PTCR_SYN | -+ MXC_AUDMUX_V2_PTCR_TFSDIR | -+ MXC_AUDMUX_V2_PTCR_TFSEL(master | 0x8) | -+ MXC_AUDMUX_V2_PTCR_TCLKDIR | -+ MXC_AUDMUX_V2_PTCR_RFSDIR | -+ MXC_AUDMUX_V2_PTCR_RFSEL(master | 0x8) | -+ MXC_AUDMUX_V2_PTCR_RCLKDIR | -+ MXC_AUDMUX_V2_PTCR_RCSEL(master | 0x8) | -+ MXC_AUDMUX_V2_PTCR_TCSEL(master | 0x8); -+ pdcr = MXC_AUDMUX_V2_PDCR_RXDSEL(master); -+ mxc_audmux_v2_configure_port(slave, ptcr, pdcr); -+ -+ ptcr = MXC_AUDMUX_V2_PTCR_SYN; -+ pdcr = MXC_AUDMUX_V2_PDCR_RXDSEL(master); -+ mxc_audmux_v2_configure_port(master, ptcr, pdcr); -+ return 0; -+} -+ -+static int __devinit imx_tc358743_probe(struct platform_device *pdev) -+{ -+ struct mxc_audio_platform_data *plat = pdev->dev.platform_data; -+ int ret = 0; -+ -+ -+ imx_audmux_config(plat->src_port, plat->ext_port); -+ -+ ret = -EINVAL; -+ if (plat->init && plat->init()) -+ return ret; -+ -+ printk("%s %d %s\n",__func__,__LINE__,pdev->name); -+ return 0; -+} -+ -+static int imx_tc358743_remove(struct platform_device *pdev) -+{ -+ struct mxc_audio_platform_data *plat = pdev->dev.platform_data; -+ -+ if (plat->finit) -+ plat->finit(); -+ -+ return 0; -+} -+ -+static struct platform_driver imx_tc358743_audio1_driver = { -+ .probe = imx_tc358743_probe, -+ .remove = imx_tc358743_remove, -+ .driver = { -+ .name = "imx-tc358743", -+ }, -+}; -+ -+ -+/* Codec setup */ -+static int tc358743_codec_probe(struct snd_soc_codec *codec) -+{ -+ return 0; -+} -+ -+static int tc358743_codec_remove(struct snd_soc_codec *codec) -+{ -+ return 0; -+} -+ -+static int tc358743_codec_suspend(struct snd_soc_codec *codec, pm_message_t state) -+{ -+// tc358743_set_bias_level(codec, SND_SOC_BIAS_OFF); -+ return 0; -+} -+ -+static int tc358743_codec_resume(struct snd_soc_codec *codec) -+{ -+// tc358743_set_bias_level(codec, SND_SOC_BIAS_STANDBY); -+ return 0; -+} -+ -+static int tc358743_set_bias_level(struct snd_soc_codec *codec, -+ enum snd_soc_bias_level level) -+{ -+ return 0; -+} -+ -+static const u8 tc358743_reg[0] = { -+}; -+ -+static struct snd_soc_codec_driver soc_codec_dev_tc358743 = { -+ .set_bias_level = tc358743_set_bias_level, -+ .reg_cache_size = ARRAY_SIZE(tc358743_reg), -+ .reg_word_size = sizeof(u8), -+ .reg_cache_default = tc358743_reg, -+ .probe = tc358743_codec_probe, -+ .remove = tc358743_codec_remove, -+ .suspend = tc358743_codec_suspend, -+ .resume = tc358743_codec_resume, -+}; -+ -+#define AIC3X_RATES SNDRV_PCM_RATE_8000_96000 -+#define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ -+ SNDRV_PCM_FMTBIT_S24_LE) -+ -+static int tc358743_hw_params(struct snd_pcm_substream *substream, -+ struct snd_pcm_hw_params *params, -+ struct snd_soc_dai *dai) -+{ -+ return 0; -+} -+ -+static int tc358743_mute(struct snd_soc_dai *dai, int mute) -+{ -+ return 0; -+} -+ -+static int tc358743_set_dai_sysclk(struct snd_soc_dai *codec_dai, -+ int clk_id, unsigned int freq, int dir) -+{ -+ return 0; -+} -+ -+static int tc358743_set_dai_fmt(struct snd_soc_dai *codec_dai, -+ unsigned int fmt) -+{ -+ return 0; -+} -+ -+static struct snd_soc_dai_ops tc358743_dai_ops = { -+ .hw_params = tc358743_hw_params, -+ .digital_mute = tc358743_mute, -+ .set_sysclk = tc358743_set_dai_sysclk, -+ .set_fmt = tc358743_set_dai_fmt, -+}; -+ -+static struct snd_soc_dai_driver tc358743_dai = { -+ .name = "tc358743-hifi", -+ .capture = { -+ .stream_name = "Capture", -+ .channels_min = 1, -+ .channels_max = 2, -+ .rates = AIC3X_RATES, -+ .formats = AIC3X_FORMATS,}, -+ .ops = &tc358743_dai_ops, -+ .symmetric_rates = 1, -+}; -+ -+#endif -+ -+struct tc_mode_list { -+ const char *name; -+ enum tc358743_mode mode; -+}; -+ -+static const struct tc_mode_list tc358743_mode_list[] = -+{ -+ {"None", 0}, /* 0 */ -+ {"VGA", tc358743_mode_480P_640_480}, /* 1 */ -+ {"240p/480i", 0}, /* 2 */ -+ {"288p/576i", 0}, /* 3 */ -+ {"W240p/480i", 0}, /* 4 */ -+ {"W288p/576i", 0}, /* 5 */ -+ {"480p", 0}, /* 6 */ -+ {"576p", 0}, /* 7 */ -+ {"W480p", tc358743_mode_480P_720_480}, /* 8 */ -+ {"W576p", 0}, /* 9 */ -+ {"WW480p", 0}, /* 10 */ -+ {"WW576p", 0}, /* 11 */ -+ {"720p", tc358743_mode_720P_60_1280_720}, /* 12 */ -+ {"1035i", 0}, /* 13 */ -+ {"1080i", 0}, /* 14 */ -+ {"1080p", tc358743_mode_1080P_1920_1080}, /* 15 */ -+}; -+ -+static char tc358743_fps_list[tc358743_max_fps+1] = -+{ -+[tc358743_60_fps] = 60, -+[tc358743_30_fps] = 30, -+[tc358743_max_fps] = 0 -+}; -+ -+static int tc358743_audio_list[16] = -+{ -+ 44100, -+ 0, -+ 48000, -+ 32000, -+ 22050, -+ 384000, -+ 24000, -+ 352800, -+ 88200, -+ 768000, -+ 96000, -+ 705600, -+ 176400, -+ 0, -+ 192000, -+ 0 -+}; -+ -+static char str_on[80]; -+static void report_netlink(struct tc_data *td) -+{ -+ struct sensor_data *sensor = &td->sensor; -+ char *envp[2]; -+ envp[0] = &str_on[0]; -+ envp[1] = NULL; -+ sprintf(envp[0], "HDMI RX: %d (%s) %d %d", -+ td->mode, -+ tc358743_mode_info_data[td->fps][td->mode].name, -+ tc358743_fps_list[td->fps], tc358743_audio_list[td->audio]); -+ kobject_uevent_env(&(sensor->i2c_client->dev.kobj), KOBJ_CHANGE, envp); -+ td->det_work_timeout = DET_WORK_TIMEOUT_DEFAULT; -+ pr_debug("%s: HDMI RX (%d) mode: %s fps: %d (%d, %d) audio: %d\n", -+ __func__, td->mode, -+ tc358743_mode_info_data[td->fps][td->mode].name, td->fps, td->bounce, -+ td->det_work_timeout, tc358743_audio_list[td->audio]); -+} -+ -+static void tc_det_worker(struct work_struct *work) -+{ -+ struct tc_data *td = container_of(work, struct tc_data, det_work.work); -+ struct sensor_data *sensor = &td->sensor; -+ int ret; -+ u32 u32val, u852f; -+ enum tc358743_mode mode = tc358743_mode_INIT; -+ -+ -+ if (!td->det_work_enable) -+ return; -+ mutex_lock(&td->access_lock); -+ -+ if (!td->det_work_enable) { -+ goto out2; -+ } -+ u32val = 0; -+ ret = tc358743_read_reg(sensor, 0x8621, &u32val); -+ if (ret >= 0) { -+ if (td->audio != (((unsigned char)u32val) & 0x0f)) { -+ td->audio = ((unsigned char)u32val) & 0x0f; -+ report_netlink(td); -+ } -+ } -+ u852f = 0; -+ ret = tc358743_read_reg(sensor, 0x852f, &u852f); -+ if (ret < 0) { -+ pr_err("%s: Error reading lock\n", __func__); -+ td->det_work_timeout = DET_WORK_TIMEOUT_DEFERRED; -+ goto out; -+ } -+// pr_info("%s: 852f=%x\n", __func__, u32val); -+ if (u852f & TC3587430_HDMI_DETECT) { -+ pr_info("%s: hdmi detect %x\n", __func__, u852f); -+ td->lock = u852f & TC3587430_HDMI_DETECT; -+ u32val = 0; -+ ret = tc358743_read_reg(sensor, 0x8521, &u32val); -+ if (ret < 0) { -+ pr_err("%s: Error reading mode\n", __func__); -+ } -+ pr_info("%s: detect 8521=%x\n", __func__, u32val); -+ u32val &= 0x0f; -+ td->fps = tc358743_60_fps; -+ if (!u32val) { -+ int hsize, vsize; -+ -+ hsize = tc358743_read_reg_val16(sensor, 0x8582); -+ vsize = tc358743_read_reg_val16(sensor, 0x8588); -+ pr_info("%s: detect hsize=%d, vsize=%d\n", __func__, hsize, vsize); -+ if ((hsize == 1024) && (vsize == 768)) -+ mode = tc358743_mode_1024x768; -+ } else { -+ mode = tc358743_mode_list[u32val].mode; -+ if (td->mode != mode) -+ pr_debug("%s: %s detected\n", __func__, tc358743_mode_list[u32val].name); -+ if (u852f >= 0xe) -+ td->fps = ((u852f & 0x0f) > 0xa)? tc358743_60_fps: tc358743_30_fps; -+ } -+ } else { -+ if (td->lock) -+ td->lock = 0; -+ u32val = 0; -+ ret = tc358743_read_reg(sensor, 0x8521, &u32val); -+ if (ret < 0) { -+ pr_err("%s: Error reading mode\n", __func__); -+ } -+// pr_info("%s: 8521=%x\n", __func__, u32val); -+ } -+ if (td->mode != mode) { -+ td->det_work_timeout = DET_WORK_TIMEOUT_DEFAULT; -+ td->bounce = MAX_BOUNCE; -+ pr_debug("%s: HDMI RX (%d != %d) mode: %s fps: %d (%d, %d)\n", -+ __func__, td->mode, mode, -+ tc358743_mode_info_data[td->fps][mode].name, -+ td->fps, td->bounce, td->det_work_timeout); -+ td->mode = mode; -+ sensor->streamcap.capturemode = mode; -+ sensor->spix.swidth = tc358743_mode_info_data[td->fps][mode].width; -+ sensor->spix.sheight = tc358743_mode_info_data[td->fps][mode].height; -+ td->det_changed = 1; -+ } else if (td->bounce) { -+ td->bounce--; -+ td->det_work_timeout = DET_WORK_TIMEOUT_DEFAULT; -+ -+ if (!td->bounce) { -+ u32val = 0; -+ ret = tc358743_read_reg(sensor, 0x8621, &u32val); -+ if (ret >= 0) { -+ td->audio = ((unsigned char)u32val) & 0x0f; -+ report_netlink(td); -+ } -+ if (td->mode) { -+ td->det_work_timeout = DET_WORK_TIMEOUT_DEFERRED; -+ goto out2; -+ } -+ } -+ } else if (td->mode && !td->bounce) { -+ goto out2; -+ } -+out: -+ schedule_delayed_work(&td->det_work, msecs_to_jiffies(td->det_work_timeout)); -+out2: -+ mutex_unlock(&td->access_lock); -+} -+ -+static irqreturn_t tc358743_detect_handler(int irq, void *data) -+{ -+ struct tc_data *td = data; -+ struct sensor_data *sensor = &td->sensor; -+ -+ pr_debug("%s: IRQ %d\n", __func__, sensor->i2c_client->irq); -+ schedule_delayed_work(&td->det_work, msecs_to_jiffies(10)); -+ return IRQ_HANDLED; -+} -+ -+ -+/*! -+ * tc358743 I2C probe function -+ * -+ * @param adapter struct i2c_adapter * -+ * @return Error code indicating success or failure -+ */ -+#define DUMP_LENGTH 256 -+static u16 regoffs = 0; -+ -+static ssize_t tc358743_show_regdump(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct tc_data *td = g_td; -+ struct sensor_data *sensor = &td->sensor; -+ int i, len = 0; -+ int retval; -+ -+ if (!td) -+ return len; -+ mutex_lock(&td->access_lock); -+ for (i=0; iaccess_lock); -+ len += sprintf(buf+len, "\n"); -+ return len; -+} -+ -+static DEVICE_ATTR(regdump, S_IRUGO, tc358743_show_regdump, NULL); -+ -+static ssize_t tc358743_store_regoffs(struct device *device, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ u32 val; -+ int retval; -+ retval = sscanf(buf, "%x", &val); -+ if (1 == retval) -+ regoffs = (u16)val; -+ return count; -+} -+ -+static ssize_t tc358743_show_regoffs(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ int len = 0; -+ -+ len += sprintf(buf+len, "0x%04X\n", regoffs); -+ return len; -+} -+ -+static DEVICE_ATTR(regoffs, S_IRUGO|S_IWUSR, tc358743_show_regoffs, tc358743_store_regoffs); -+ -+static ssize_t tc358743_store_hpd(struct device *device, -+ struct device_attribute *attr, -+ const char *buf, size_t count) -+{ -+ struct tc_data *td = g_td; -+ u32 val; -+ int retval; -+ retval = sscanf(buf, "%d", &val); -+ if (1 == retval) -+ td->hpd_active = (u16)val; -+ return count; -+} -+ -+static ssize_t tc358743_show_hpd(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct tc_data *td = g_td; -+ int len = 0; -+ -+ len += sprintf(buf+len, "%d\n", td->hpd_active); -+ return len; -+} -+ -+static DEVICE_ATTR(hpd, S_IRUGO|S_IWUSR, tc358743_show_hpd, tc358743_store_hpd); -+ -+static ssize_t tc358743_show_hdmirx(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct tc_data *td = g_td; -+ int len = 0; -+ -+ len += sprintf(buf+len, "%d\n", td->mode); -+ return len; -+} -+ -+static DEVICE_ATTR(hdmirx, S_IRUGO, tc358743_show_hdmirx, NULL); -+ -+static ssize_t tc358743_show_fps(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct tc_data *td = g_td; -+ int len = 0; -+ -+ len += sprintf(buf+len, "%d\n", tc358743_fps_list[td->fps]); -+ return len; -+} -+ -+static DEVICE_ATTR(fps, S_IRUGO, tc358743_show_fps, NULL); -+ -+#ifdef CONFIG_TC358743_AUDIO -+static ssize_t tc358743_show_audio(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct tc_data *td = g_td; -+ int len = 0; -+ -+ len += sprintf(buf+len, "%d\n", tc358743_audio_list[td->audio]); -+ return len; -+} -+ -+static DEVICE_ATTR(audio, S_IRUGO, tc358743_show_audio, NULL); -+#endif -+ -+static int tc358743_probe(struct i2c_client *client, -+ const struct i2c_device_id *id) -+{ -+ struct device *dev = &client->dev; -+ int retval; -+ struct tc_data *td; -+ struct sensor_data *sensor; -+ u8 chip_id_high; -+ u32 u32val; -+ int mode = tc358743_mode_INIT; -+ -+ td = kzalloc(sizeof(*td), GFP_KERNEL); -+ if (!td) -+ return -ENOMEM; -+ td->hpd_active = 1; -+ td->det_work_timeout = DET_WORK_TIMEOUT_DEFAULT; -+ td->audio = 2; -+ mutex_init(&td->access_lock); -+ mutex_lock(&td->access_lock); -+ sensor = &td->sensor; -+ -+ /* request power down pin */ -+ td->pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0); -+ if (!gpio_is_valid(td->pwn_gpio)) { -+ dev_warn(dev, "no sensor pwdn pin available"); -+ } else { -+ retval = devm_gpio_request_one(dev, td->pwn_gpio, GPIOF_OUT_INIT_HIGH, -+ "tc_mipi_pwdn"); -+ if (retval < 0) { -+ dev_warn(dev, "request of pwn_gpio failed"); -+ return retval; -+ } -+ } -+ /* request reset pin */ -+ td->rst_gpio = of_get_named_gpio(dev->of_node, "rst-gpios", 0); -+ if (!gpio_is_valid(td->rst_gpio)) { -+ dev_warn(dev, "no sensor reset pin available"); -+ return -EINVAL; -+ } -+ retval = devm_gpio_request_one(dev, td->rst_gpio, GPIOF_OUT_INIT_HIGH, -+ "tc_mipi_reset"); -+ if (retval < 0) { -+ dev_warn(dev, "request of tc_mipi_reset failed"); -+ return retval; -+ } -+ -+ /* Set initial values for the sensor struct. */ -+ sensor->mipi_camera = 1; -+ sensor->virtual_channel = 0; -+ sensor->sensor_clk = devm_clk_get(dev, "csi_mclk"); -+ -+ retval = of_property_read_u32(dev->of_node, "mclk", -+ &(sensor->mclk)); -+ if (retval) { -+ dev_err(dev, "mclk missing or invalid\n"); -+ return retval; -+ } -+ -+ retval = of_property_read_u32(dev->of_node, "mclk_source", -+ (u32 *) &(sensor->mclk_source)); -+ if (retval) { -+ dev_err(dev, "mclk_source missing or invalid\n"); -+ return retval; -+ } -+ -+ retval = of_property_read_u32(dev->of_node, "ipu_id", -+ &sensor->ipu_id); -+ if (retval) { -+ dev_err(dev, "ipu_id missing or invalid\n"); -+ return retval; -+ } -+ -+ retval = of_property_read_u32(dev->of_node, "csi_id", -+ &(sensor->csi)); -+ if (retval) { -+ dev_err(dev, "csi id missing or invalid\n"); -+ return retval; -+ } -+ if ((unsigned)sensor->ipu_id || (unsigned)sensor->csi) { -+ dev_err(dev, "invalid ipu/csi\n"); -+ return -EINVAL; -+ } -+ -+ if (!IS_ERR(sensor->sensor_clk)) -+ clk_prepare_enable(sensor->sensor_clk); -+ -+ sensor->io_init = tc_io_init; -+ sensor->i2c_client = client; -+ sensor->streamcap.capability = V4L2_MODE_HIGHQUALITY | -+ V4L2_CAP_TIMEPERFRAME; -+ sensor->streamcap.capturemode = mode; -+ sensor->streamcap.timeperframe.denominator = DEFAULT_FPS; -+ sensor->streamcap.timeperframe.numerator = 1; -+ -+ sensor->pix.pixelformat = get_pixelformat(0, mode); -+ sensor->pix.width = tc358743_mode_info_data[0][mode].width; -+ sensor->pix.height = tc358743_mode_info_data[0][mode].height; -+ pr_debug("%s: format: %x, capture mode: %d fps: %d width: %d height: %d\n", -+ __func__, sensor->pix.pixelformat, mode, -+ sensor->streamcap.timeperframe.denominator * -+ sensor->streamcap.timeperframe.numerator, -+ sensor->pix.width, -+ sensor->pix.height); -+ -+ tc_regulator_init(td, dev); -+ power_control(td, 1); -+ tc_reset(td); -+ -+ u32val = 0; -+ retval = tc358743_read_reg(sensor, TC358743_CHIP_ID_HIGH_BYTE, &u32val); -+ if (retval < 0) { -+ pr_err("%s:cannot find camera\n", __func__); -+ retval = -ENODEV; -+ goto err4; -+ } -+ chip_id_high = (u8)u32val; -+ -+ tc358743_int_device.priv = td; -+ if (!g_td) -+ g_td = td; -+ -+#ifdef CONFIG_TC358743_AUDIO -+ retval = device_create_file(&client->dev, &dev_attr_audio); -+#endif -+ retval = device_create_file(&client->dev, &dev_attr_fps); -+ retval = device_create_file(&client->dev, &dev_attr_hdmirx); -+ retval = device_create_file(&client->dev, &dev_attr_hpd); -+ retval = device_create_file(&client->dev, &dev_attr_regoffs); -+ retval = device_create_file(&client->dev, &dev_attr_regdump); -+ -+ if (retval) { -+ pr_err("%s: create bin file failed, error=%d\n", -+ __func__, retval); -+ goto err4; -+ } -+ -+#ifdef CONFIG_TC358743_AUDIO -+/* Audio setup */ -+ retval = snd_soc_register_codec(&client->dev, -+ &soc_codec_dev_tc358743, &tc358743_dai, 1); -+ if (retval) { -+ pr_err("%s: register failed, error=%d\n", -+ __func__, retval); -+ goto err4; -+ } -+ -+ retval = platform_driver_register(&imx_tc358743_audio1_driver); -+ if (retval) { -+ pr_err("%s: Platform driver register failed, error=%d\n", -+ __func__, retval); -+ goto err4; -+ } -+ -+ td->snd_device = platform_device_alloc("soc-audio", 5); -+ if (!td->snd_device) { -+ pr_err("%s: Platform device allocation failed, error=%d\n", -+ __func__, retval); -+ goto err4; -+ } -+ -+ platform_set_drvdata(td->snd_device, &imxpac_tc358743); -+ retval = platform_device_add(td->snd_device); -+ -+ if (retval) { -+ pr_err("%s: Platform device add failed, error=%d\n", -+ __func__, retval); -+ platform_device_put(td->snd_device); -+ goto err4; -+ } -+#endif -+ -+#if 1 -+ INIT_DELAYED_WORK(&td->det_work, tc_det_worker); -+ if (sensor->i2c_client->irq) { -+ retval = request_irq(sensor->i2c_client->irq, tc358743_detect_handler, -+ IRQF_SHARED | IRQF_TRIGGER_FALLING, -+ "tc358743_det", td); -+ if (retval < 0) -+ dev_warn(&sensor->i2c_client->dev, -+ "cound not request det irq %d\n", -+ sensor->i2c_client->irq); -+ } -+ -+ schedule_delayed_work(&td->det_work, msecs_to_jiffies(td->det_work_timeout)); -+#endif -+ retval = tc358743_reset(td); -+ if (retval) -+ goto err4; -+ -+ i2c_set_clientdata(client, td); -+ mutex_unlock(&td->access_lock); -+ retval = v4l2_int_device_register(&tc358743_int_device); -+ mutex_lock(&td->access_lock); -+ if (retval) { -+ pr_err("%s: v4l2_int_device_register failed, error=%d\n", -+ __func__, retval); -+ goto err4; -+ } -+ power_control(td, 0); -+ mutex_unlock(&td->access_lock); -+ pr_debug("%s: finished, error=%d\n", __func__, retval); -+ return retval; -+ -+err4: -+ power_control(td, 0); -+ mutex_unlock(&td->access_lock); -+ pr_err("%s: failed, error=%d\n", __func__, retval); -+ if (g_td == td) -+ g_td = NULL; -+ mutex_destroy(&td->access_lock); -+ kfree(td); -+ return retval; -+} -+ -+/*! -+ * tc358743 I2C detach function -+ * -+ * @param client struct i2c_client * -+ * @return Error code indicating success or failure -+ */ -+static int tc358743_remove(struct i2c_client *client) -+{ -+ int i; -+ struct tc_data *td = i2c_get_clientdata(client); -+ struct sensor_data *sensor = &td->sensor; -+ -+ // Stop delayed work -+ cancel_delayed_work_sync(&td->det_work); -+ mutex_lock(&td->access_lock); -+ -+ power_control(td, 0); -+ // Remove IRQ -+ if (sensor->i2c_client->irq) { -+ free_irq(sensor->i2c_client->irq, sensor); -+ } -+ -+#ifdef CONFIG_TC358743_AUDIO -+/* Audio breakdown */ -+ snd_soc_unregister_codec(&client->dev); -+ platform_driver_unregister(&imx_tc358743_audio1_driver); -+ platform_device_unregister(td->snd_device); -+#endif -+ /*Remove sysfs entries*/ -+#ifdef CONFIG_TC358743_AUDIO -+ device_remove_file(&client->dev, &dev_attr_audio); -+#endif -+ device_remove_file(&client->dev, &dev_attr_fps); -+ device_remove_file(&client->dev, &dev_attr_hdmirx); -+ device_remove_file(&client->dev, &dev_attr_hpd); -+ device_remove_file(&client->dev, &dev_attr_regoffs); -+ device_remove_file(&client->dev, &dev_attr_regdump); -+ -+ mutex_unlock(&td->access_lock); -+ v4l2_int_device_unregister(&tc358743_int_device); -+ -+ for (i = REGULATOR_CNT - 1; i >= 0; i--) { -+ if (td->regulator[i]) { -+ regulator_disable(td->regulator[i]); -+ } -+ } -+ mutex_destroy(&td->access_lock); -+ if (g_td == td) -+ g_td = NULL; -+ kfree(td); -+ return 0; -+} -+ -+/*! -+ * tc358743 init function -+ * Called by insmod tc358743_camera.ko. -+ * -+ * @return Error code indicating success or failure -+ */ -+static __init int tc358743_init(void) -+{ -+ int err; -+ -+ err = i2c_add_driver(&tc358743_i2c_driver); -+ if (err != 0) -+ pr_err("%s:driver registration failed, error=%d\n", -+ __func__, err); -+ -+ return err; -+} -+ -+/*! -+ * tc358743 cleanup function -+ * Called on rmmod tc358743_camera.ko -+ * -+ * @return Error code indicating success or failure -+ */ -+static void __exit tc358743_clean(void) -+{ -+ i2c_del_driver(&tc358743_i2c_driver); -+} -+ -+module_init(tc358743_init); -+module_exit(tc358743_clean); -+ -+MODULE_AUTHOR("Panasonic Avionics Corp."); -+MODULE_DESCRIPTION("Toshiba TC358743 HDMI-to-CSI2 Bridge MIPI Input Driver"); -+MODULE_LICENSE("GPL"); -+MODULE_VERSION("1.0"); -+MODULE_ALIAS("CSI"); -diff -Nur linux-4.1.13.orig/drivers/media/platform/mxc/capture/tda1997x.c linux-4.1.13/drivers/media/platform/mxc/capture/tda1997x.c ---- linux-4.1.13.orig/drivers/media/platform/mxc/capture/tda1997x.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/media/platform/mxc/capture/tda1997x.c 2015-11-30 17:56:13.616135330 +0100 -@@ -0,0 +1,451 @@ -+/* -+ * tda1997x.c -- MXC video capture driver for i.MX boards with -+ * tda1997x HDMI receiver -+ * -+ * Copyright (C) 2013 Gateworks Corporation -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ * -+ */ -+ -+/* The tda1997x-core driver manages the i2c interface with the device. -+ * This driver merely calls into that driver for current video parameters -+ * when necessary. The platform data for the core driver contains the -+ * video output bus configuration that configures the video port -+ * mapping between the tda1997x and a i.MX6 CSI parallel bus for 8bit -+ * bt656 with embedded syncs as this is the only video format compatible -+ * between the tda1997x and the i.MX6 CSI. -+ * -+ * see for details -+ */ -+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "v4l2-int-device.h" -+#include "mxc_v4l2_capture.h" -+ -+/*! -+ * Maintains the information on the current state of the sensor. -+ */ -+struct sensor { -+ struct sensor_data sen; -+ tda1997x_videofmt_t vidfmt; -+} tda1997x_data; -+ -+/*********************************************************************** -+ * mxc_v4l2_capture interface. -+ ***********************************************************************/ -+ -+/*********************************************************************** -+ * IOCTL Functions from v4l2_int_ioctl_desc. -+ ***********************************************************************/ -+ -+/*! -+ * ioctl_g_ifparm - V4L2 sensor interface handler for vidioc_int_g_ifparm_num -+ * s: pointer to standard V4L2 device structure -+ * p: pointer to standard V4L2 vidioc_int_g_ifparm_num ioctl structure -+ * -+ * Gets slave interface parameters. -+ * Calculates the required xclk value to support the requested -+ * clock parameters in p. This value is returned in the p -+ * parameter. -+ * -+ * vidioc_int_g_ifparm returns platform-specific information about the -+ * interface settings used by the sensor. -+ * -+ * Called on open. -+ */ -+static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p) -+{ -+ struct sensor *sensor = s->priv; -+ tda1997x_vidout_fmt_t fmt; -+ -+ if (s == NULL) { -+ pr_err(" ERROR!! no slave device set!\n"); -+ return -ENODEV; -+ } -+ -+ if (tda1997x_get_vidout_fmt(&fmt)) -+ return -ENODEV; -+ pr_debug("%s: %dx%d%c@%dfps\n", __func__, fmt.width, fmt.height, -+ fmt.interlaced?'i':'p', fmt.fps); -+ -+ /* Initialize structure to 0s then set any non-0 values. */ -+ memset(p, 0, sizeof(*p)); -+ p->if_type = V4L2_IF_TYPE_BT656; /* This is the only possibility. */ -+ -+ if (sensor->vidfmt == VIDEOFMT_422_SMP) { /* YCbCr 4:2:2 semi-planar */ -+ p->u.bt656.nobt_vs_inv = 0; -+ p->u.bt656.nobt_hs_inv = 1; -+ p->u.bt656.bt_sync_correct = 1; -+ p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_16BIT; -+ p->u.bt656.clock_curr = -1; /* gated clock mode */ -+ } else if (sensor->vidfmt == VIDEOFMT_422_CCIR) { /* YCbCr 4:2:2 CCIR656 */ -+ p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT; -+ p->u.bt656.clock_curr = (fmt.interlaced)?0:1; -+ } -+ -+ return 0; -+} -+ -+/*! -+ * Sets the device power. -+ * -+ * s pointer to the device device -+ * on if 1, power is to be turned on. 0 means power is to be turned off -+ * -+ * ioctl_s_power - V4L2 sensor interface handler for vidioc_int_s_power_num -+ * @s: pointer to standard V4L2 device structure -+ * @on: power state to which device is to be set -+ * -+ * Sets devices power state to requrested state, if possible. -+ * This is called on open, close, suspend and resume. -+static int ioctl_s_power(struct v4l2_int_device *s, int on) -+{ -+ struct sensor *sensor = s->priv; -+ -+ if (on && !sensor->sen.on) { -+ } else if (!on && sensor->sen.on) { -+ } -+ -+ sensor->sen.on = on; -+ -+ return 0; -+} -+ */ -+ -+/*! -+ * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure -+ * -+ * Returns the sensor's video CAPTURE parameters. -+ */ -+static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) -+{ -+ struct sensor *sensor = s->priv; -+ struct v4l2_captureparm *cparm = &a->parm.capture; -+ -+ switch (a->type) { -+ /* These are all the possible cases. */ -+ case V4L2_BUF_TYPE_VIDEO_CAPTURE: -+ pr_debug(" type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n"); -+ memset(a, 0, sizeof(*a)); -+ a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; -+ cparm->capability = sensor->sen.streamcap.capability; -+ cparm->timeperframe = sensor->sen.streamcap.timeperframe; -+ cparm->capturemode = sensor->sen.streamcap.capturemode; -+ break; -+ -+ case V4L2_BUF_TYPE_VIDEO_OUTPUT: -+ case V4L2_BUF_TYPE_VIDEO_OVERLAY: -+ case V4L2_BUF_TYPE_VBI_CAPTURE: -+ case V4L2_BUF_TYPE_VBI_OUTPUT: -+ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: -+ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: -+ break; -+ -+ default: -+ pr_debug("ioctl_g_parm:type is unknown %d\n", a->type); -+ break; -+ } -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure -+ * -+ * Configures the sensor to use the input parameters, if possible. If -+ * not possible, reverts to the old parameters and returns the -+ * appropriate error code. -+ * -+ * This driver cannot change these settings. -+ */ -+static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) -+{ -+ switch (a->type) { -+ /* These are all the possible cases. */ -+ case V4L2_BUF_TYPE_VIDEO_CAPTURE: -+ case V4L2_BUF_TYPE_VIDEO_OUTPUT: -+ case V4L2_BUF_TYPE_VIDEO_OVERLAY: -+ case V4L2_BUF_TYPE_VBI_CAPTURE: -+ case V4L2_BUF_TYPE_VBI_OUTPUT: -+ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: -+ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: -+ break; -+ -+ default: -+ pr_debug(" type is unknown - %d\n", a->type); -+ break; -+ } -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap -+ * @s: pointer to standard V4L2 device structure -+ * @f: pointer to standard V4L2 v4l2_format structure -+ * -+ * Returns the sensor's current pixel format in the v4l2_format -+ * parameter. -+ */ -+static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) -+{ -+ struct sensor *sensor = s->priv; -+ tda1997x_vidout_fmt_t fmt; -+ -+ if (tda1997x_get_vidout_fmt(&fmt)) -+ return -ENODEV; -+ -+ pr_debug("%s: %dx%d%c@%dfps\n", __func__, fmt.width, fmt.height, -+ fmt.interlaced?'i':'p', fmt.fps); -+ sensor->sen.pix.height = fmt.height; -+ sensor->sen.pix.width = fmt.width; -+ sensor->sen.streamcap.timeperframe.denominator = fmt.fps; -+ sensor->sen.streamcap.timeperframe.numerator = 1; -+ switch (f->type) { -+ case V4L2_BUF_TYPE_VIDEO_CAPTURE: -+ pr_debug(" Returning size of %dx%d\n", -+ sensor->sen.pix.width, sensor->sen.pix.height); -+ f->fmt.pix = sensor->sen.pix; -+ pr_debug(" Returning format of %s\n", (char*)&f->fmt.pix.pixelformat); -+ break; -+ -+ case V4L2_BUF_TYPE_PRIVATE: { -+ } -+ break; -+ -+ default: -+ f->fmt.pix = sensor->sen.pix; -+ break; -+ } -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_enum_framesizes - V4L2 sensor interface handler for -+ * VIDIOC_ENUM_FRAMESIZES ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure -+ * -+ * Return 0 if successful, otherwise -EINVAL. -+ */ -+static int ioctl_enum_framesizes(struct v4l2_int_device *s, -+ struct v4l2_frmsizeenum *fsize) -+{ -+ struct sensor *sensor = s->priv; -+ tda1997x_vidout_fmt_t fmt; -+ -+ if (fsize->index >= 1) -+ return -EINVAL; -+ -+ if (tda1997x_get_vidout_fmt(&fmt)) -+ return -ENODEV; -+ -+ pr_debug("%s: %dx%d%c@%dfps\n", __func__, fmt.height, fmt.width, -+ fmt.interlaced?'i':'p', fmt.fps); -+ sensor->sen.pix.height = fmt.height; -+ sensor->sen.pix.width = fmt.width; -+ fsize->discrete.width = sensor->sen.pix.width; -+ fsize->discrete.height = sensor->sen.pix.height; -+ -+ return 0; -+} -+ -+/*! -+ * ioctl_g_chip_ident - V4L2 sensor interface handler for -+ * VIDIOC_DBG_G_CHIP_IDENT ioctl -+ * @s: pointer to standard V4L2 device structure -+ * @id: pointer to int -+ * -+ * Return 0. -+ */ -+static int ioctl_g_chip_ident(struct v4l2_int_device *s, int *id) -+{ -+ struct sensor *sensor = s->priv; -+ ((struct v4l2_dbg_chip_ident *)id)->match.type = -+ V4L2_CHIP_MATCH_I2C_DRIVER; -+ if (sensor->vidfmt == VIDEOFMT_422_SMP) { /* YCbCr 4:2:2 semi-planar */ -+ strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name, -+ "tda1997x_decoder_yuv422"); -+ } else -+ strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name, -+ "tda1997x_decoder_bt656"); -+ ((struct v4l2_dbg_chip_ident *)id)->ident = V4L2_IDENT_TDA19971; -+ -+ return 0; -+} -+ -+/*! -+ * This structure defines all the ioctls for this module. -+ */ -+static struct v4l2_int_ioctl_desc tda1997x_ioctl_desc[] = { -+ -+/* {vidioc_int_s_power_num, (v4l2_int_ioctl_func*)ioctl_s_power}, */ -+ {vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func*)ioctl_g_ifparm}, -+ {vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func*)ioctl_g_fmt_cap}, -+ /*! -+ * If the requested format is supported, configures the HW to use that -+ * format, returns error code if format not supported or HW can't be -+ * correctly configured. -+ */ -+ {vidioc_int_g_parm_num, (v4l2_int_ioctl_func*)ioctl_g_parm}, -+ {vidioc_int_s_parm_num, (v4l2_int_ioctl_func*)ioctl_s_parm}, -+ {vidioc_int_enum_framesizes_num, -+ (v4l2_int_ioctl_func *) ioctl_enum_framesizes}, -+ {vidioc_int_g_chip_ident_num, -+ (v4l2_int_ioctl_func *)ioctl_g_chip_ident}, -+}; -+ -+static struct v4l2_int_slave tda1997x_slave = { -+ .ioctls = tda1997x_ioctl_desc, -+ .num_ioctls = ARRAY_SIZE(tda1997x_ioctl_desc), -+}; -+ -+static struct v4l2_int_device tda1997x_int_device = { -+ .module = THIS_MODULE, -+ .name = "tda1997x-video", -+ .type = v4l2_int_type_slave, -+ .u = { -+ .slave = &tda1997x_slave, -+ }, -+}; -+ -+static int tda1997x_video_probe(struct platform_device *pdev) -+{ -+ struct sensor *sens = &tda1997x_data; -+ struct pinctrl *pinctrl; -+ struct device *dev = &pdev->dev; -+ struct regmap *gpr; -+ tda1997x_vidout_fmt_t fmt; -+ int ret; -+ -+ dev_dbg(dev, "%s\n", __func__); -+ -+ /* pinctrl */ -+ pinctrl = devm_pinctrl_get_select_default(dev); -+ if (IS_ERR(pinctrl)) { -+ dev_err(dev, "setup pinctrl failed\n"); -+ return PTR_ERR(pinctrl); -+ } -+ -+ /* Set initial values for the sensor struct. */ -+ memset(sens, 0, sizeof(tda1997x_data)); -+ if (tda1997x_get_vidout_fmt(&fmt)) -+ return -ENODEV; -+ sens->vidfmt = fmt.sensor_vidfmt; -+ sens->sen.streamcap.timeperframe.denominator = 0; -+ sens->sen.streamcap.timeperframe.numerator = 0; -+ sens->sen.pix.width = 0; -+ sens->sen.pix.height = 0; -+ if (sens->vidfmt == VIDEOFMT_422_SMP) -+ sens->sen.pix.pixelformat = IPU_PIX_FMT_GENERIC_16; -+ else -+ sens->sen.pix.pixelformat = V4L2_PIX_FMT_UYVY; -+ sens->sen.on = true; -+ -+ ret = of_property_read_u32(dev->of_node, "csi_id", -+ &(sens->sen.csi)); -+ if (ret) { -+ dev_err(dev, "csi_id invalid\n"); -+ return ret; -+ } -+ -+ ret = of_property_read_u32(dev->of_node, "ipu_id", -+ &(sens->sen.ipu_id)); -+ if (ret) { -+ dev_err(dev, "ipu_id invalid\n"); -+ return ret; -+ } -+ -+ gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); -+ if (!IS_ERR(gpr)) { -+ if (of_machine_is_compatible("fsl,imx6q")) { -+ int mask = sens->sen.csi ? (1 << 20) : (1 << 19); -+ -+ regmap_update_bits(gpr, IOMUXC_GPR1, mask, mask); -+ } else if (of_machine_is_compatible("fsl,imx6dl")) { -+ int mask = sens->sen.csi ? (7 << 3) : (7 << 0); -+ int val = sens->sen.csi ? (4 << 3) : (4 << 0); -+ -+ regmap_update_bits(gpr, IOMUXC_GPR13, mask, val); -+ } -+ } else { -+ pr_err("%s: failed to find fsl,imx6q-iomux-gpr regmap\n", -+ __func__); -+ } -+ -+ dev_dbg(dev, "IPU%d_CSI%d\n", sens->sen.ipu_id + 1, sens->sen.csi); -+ dev_dbg(dev, "type is %d (expect %d)\n", -+ tda1997x_int_device.type, v4l2_int_type_slave); -+ dev_dbg(dev, "num ioctls is %d\n", -+ tda1997x_int_device.u.slave->num_ioctls); -+ -+ /* This function attaches this structure to the /dev/video device */ -+ tda1997x_int_device.priv = sens; -+ ret = v4l2_int_device_register(&tda1997x_int_device); -+ -+ return ret; -+} -+ -+static int tda1997x_video_remove(struct platform_device *pdev) -+{ -+ v4l2_int_device_unregister(&tda1997x_int_device); -+ -+ return 0; -+} -+ -+static const struct of_device_id tda1997x_video_driver_ids[] = { -+ { .compatible = "fsl,imx-tda1997x-video", }, -+ { /* sentinel */ } -+}; -+ -+static struct platform_driver tda1997x_video_driver = { -+ .driver = { -+ .owner = THIS_MODULE, -+ .name = "imx-tda1997x-video", -+ .of_match_table = tda1997x_video_driver_ids, -+ }, -+ .probe = tda1997x_video_probe, -+ .remove = tda1997x_video_remove, -+}; -+module_platform_driver(tda1997x_video_driver); -+ -+MODULE_AUTHOR("Tim Harvey "); -+MODULE_DESCRIPTION("TDA1997X hdmi receiver MXC video capture driver"); -+MODULE_LICENSE("GPL"); -+MODULE_ALIAS("platform:imx-tda1997x-video"); -diff -Nur linux-4.1.13.orig/drivers/media/platform/mxc/capture/v4l2-int-device.c linux-4.1.13/drivers/media/platform/mxc/capture/v4l2-int-device.c ---- linux-4.1.13.orig/drivers/media/platform/mxc/capture/v4l2-int-device.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/media/platform/mxc/capture/v4l2-int-device.c 2015-11-30 17:56:13.616135330 +0100 -@@ -0,0 +1,165 @@ -+/* -+ * drivers/media/video/v4l2-int-device.c -+ * -+ * V4L2 internal ioctl interface. -+ * -+ * Copyright 2005-2014 Freescale Semiconductor, Inc. -+ * Copyright (C) 2007 Nokia Corporation. -+ * -+ * Contact: Sakari Ailus -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA -+ * 02110-1301 USA -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "v4l2-int-device.h" -+ -+static DEFINE_MUTEX(mutex); -+static LIST_HEAD(int_list); -+ -+void v4l2_int_device_try_attach_all(void) -+{ -+ struct v4l2_int_device *m, *s; -+ -+ list_for_each_entry(m, &int_list, head) { -+ if (m->type != v4l2_int_type_master) -+ continue; -+ -+ list_for_each_entry(s, &int_list, head) { -+ if (s->type != v4l2_int_type_slave) -+ continue; -+ -+ /* Slave is connected? */ -+ if (s->u.slave->master) -+ continue; -+ -+ /* Slave wants to attach to master? */ -+ if (s->u.slave->attach_to[0] != 0 -+ && strncmp(m->name, s->u.slave->attach_to, -+ V4L2NAMESIZE)) -+ continue; -+ -+ if (!try_module_get(m->module)) -+ continue; -+ -+ s->u.slave->master = m; -+ if (m->u.master->attach(s)) { -+ s->u.slave->master = NULL; -+ module_put(m->module); -+ continue; -+ } -+ } -+ } -+} -+EXPORT_SYMBOL_GPL(v4l2_int_device_try_attach_all); -+ -+static int ioctl_sort_cmp(const void *a, const void *b) -+{ -+ const struct v4l2_int_ioctl_desc *d1 = a, *d2 = b; -+ -+ if (d1->num > d2->num) -+ return 1; -+ -+ if (d1->num < d2->num) -+ return -1; -+ -+ return 0; -+} -+ -+int v4l2_int_device_register(struct v4l2_int_device *d) -+{ -+ if (d->type == v4l2_int_type_slave) -+ sort(d->u.slave->ioctls, d->u.slave->num_ioctls, -+ sizeof(struct v4l2_int_ioctl_desc), -+ &ioctl_sort_cmp, NULL); -+ mutex_lock(&mutex); -+ list_add(&d->head, &int_list); -+ v4l2_int_device_try_attach_all(); -+ mutex_unlock(&mutex); -+ -+ return 0; -+} -+EXPORT_SYMBOL_GPL(v4l2_int_device_register); -+ -+void v4l2_int_device_unregister(struct v4l2_int_device *d) -+{ -+ mutex_lock(&mutex); -+ list_del(&d->head); -+ if (d->type == v4l2_int_type_slave -+ && d->u.slave->master != NULL) { -+ d->u.slave->master->u.master->detach(d); -+ module_put(d->u.slave->master->module); -+ d->u.slave->master = NULL; -+ } -+ mutex_unlock(&mutex); -+} -+EXPORT_SYMBOL_GPL(v4l2_int_device_unregister); -+ -+/* Adapted from search_extable in extable.c. */ -+static v4l2_int_ioctl_func *find_ioctl(struct v4l2_int_slave *slave, int cmd, -+ v4l2_int_ioctl_func *no_such_ioctl) -+{ -+ const struct v4l2_int_ioctl_desc *first = slave->ioctls; -+ const struct v4l2_int_ioctl_desc *last = -+ first + slave->num_ioctls - 1; -+ -+ while (first <= last) { -+ const struct v4l2_int_ioctl_desc *mid; -+ -+ mid = (last - first) / 2 + first; -+ -+ if (mid->num < cmd) -+ first = mid + 1; -+ else if (mid->num > cmd) -+ last = mid - 1; -+ else -+ return mid->func; -+ } -+ -+ return no_such_ioctl; -+} -+ -+static int no_such_ioctl_0(struct v4l2_int_device *d) -+{ -+ return -ENOIOCTLCMD; -+} -+ -+int v4l2_int_ioctl_0(struct v4l2_int_device *d, int cmd) -+{ -+ return ((v4l2_int_ioctl_func_0 *) -+ find_ioctl(d->u.slave, cmd, -+ (v4l2_int_ioctl_func *)no_such_ioctl_0))(d); -+} -+EXPORT_SYMBOL_GPL(v4l2_int_ioctl_0); -+ -+static int no_such_ioctl_1(struct v4l2_int_device *d, void *arg) -+{ -+ return -ENOIOCTLCMD; -+} -+ -+int v4l2_int_ioctl_1(struct v4l2_int_device *d, int cmd, void *arg) -+{ -+ return ((v4l2_int_ioctl_func_1 *) -+ find_ioctl(d->u.slave, cmd, -+ (v4l2_int_ioctl_func *)no_such_ioctl_1))(d, arg); -+} -+EXPORT_SYMBOL_GPL(v4l2_int_ioctl_1); -+ -+MODULE_LICENSE("GPL"); -diff -Nur linux-4.1.13.orig/drivers/media/platform/mxc/capture/v4l2-int-device.h linux-4.1.13/drivers/media/platform/mxc/capture/v4l2-int-device.h ---- linux-4.1.13.orig/drivers/media/platform/mxc/capture/v4l2-int-device.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/media/platform/mxc/capture/v4l2-int-device.h 2015-11-30 17:56:13.616135330 +0100 -@@ -0,0 +1,317 @@ -+/* -+ * include/media/v4l2-int-device.h -+ * -+ * V4L2 internal ioctl interface. -+ * -+ * Copyright 2005-2014 Freescale Semiconductor, Inc. -+ * Copyright (C) 2007 Nokia Corporation. -+ * -+ * Contact: Sakari Ailus -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA -+ * 02110-1301 USA -+ */ -+ -+#ifndef V4L2_INT_DEVICE_H -+#define V4L2_INT_DEVICE_H -+ -+#include -+ -+#define V4L2NAMESIZE 32 -+ -+/* -+ * -+ * The internal V4L2 device interface core. -+ * -+ */ -+ -+enum v4l2_int_type { -+ v4l2_int_type_master = 1, -+ v4l2_int_type_slave -+}; -+ -+struct module; -+ -+struct v4l2_int_device; -+ -+struct v4l2_int_master { -+ int (*attach)(struct v4l2_int_device *slave); -+ void (*detach)(struct v4l2_int_device *slave); -+}; -+ -+typedef int (v4l2_int_ioctl_func)(struct v4l2_int_device *); -+typedef int (v4l2_int_ioctl_func_0)(struct v4l2_int_device *); -+typedef int (v4l2_int_ioctl_func_1)(struct v4l2_int_device *, void *); -+ -+struct v4l2_int_ioctl_desc { -+ int num; -+ v4l2_int_ioctl_func *func; -+}; -+ -+struct v4l2_int_slave { -+ /* Don't touch master. */ -+ struct v4l2_int_device *master; -+ -+ char attach_to[V4L2NAMESIZE]; -+ -+ int num_ioctls; -+ struct v4l2_int_ioctl_desc *ioctls; -+}; -+ -+struct v4l2_int_device { -+ /* Don't touch head. */ -+ struct list_head head; -+ -+ struct module *module; -+ -+ char name[V4L2NAMESIZE]; -+ -+ enum v4l2_int_type type; -+ union { -+ struct v4l2_int_master *master; -+ struct v4l2_int_slave *slave; -+ } u; -+ -+ void *priv; -+}; -+ -+void v4l2_int_device_try_attach_all(void); -+ -+int v4l2_int_device_register(struct v4l2_int_device *d); -+void v4l2_int_device_unregister(struct v4l2_int_device *d); -+ -+int v4l2_int_ioctl_0(struct v4l2_int_device *d, int cmd); -+int v4l2_int_ioctl_1(struct v4l2_int_device *d, int cmd, void *arg); -+ -+/* -+ * -+ * Types and definitions for IOCTL commands. -+ * -+ */ -+ -+enum v4l2_power { -+ V4L2_POWER_OFF = 0, -+ V4L2_POWER_ON, -+ V4L2_POWER_STANDBY, -+}; -+ -+/* Slave interface type. */ -+enum v4l2_if_type { -+ /* -+ * Parallel 8-, 10- or 12-bit interface, used by for example -+ * on certain image sensors. -+ */ -+ V4L2_IF_TYPE_BT656, -+ V4L2_IF_TYPE_BT1120_PROGRESSIVE_DDR, -+ V4L2_IF_TYPE_BT1120_PROGRESSIVE_SDR, -+ V4L2_IF_TYPE_BT1120_INTERLACED_DDR, -+ V4L2_IF_TYPE_BT1120_INTERLACED_SDR, -+ V4L2_IF_TYPE_BT656_PROGRESSIVE, -+ V4L2_IF_TYPE_BT656_INTERLACED, -+}; -+ -+enum v4l2_if_type_bt656_mode { -+ /* -+ * Modes without Bt synchronisation codes. Separate -+ * synchronisation signal lines are used. -+ */ -+ V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT, -+ V4L2_IF_TYPE_BT656_MODE_NOBT_10BIT, -+ V4L2_IF_TYPE_BT656_MODE_NOBT_12BIT, -+ /* -+ * Use Bt synchronisation codes. The vertical and horizontal -+ * synchronisation is done based on synchronisation codes. -+ */ -+ V4L2_IF_TYPE_BT656_MODE_BT_8BIT, -+ V4L2_IF_TYPE_BT656_MODE_BT_10BIT, -+}; -+ -+struct v4l2_if_type_bt656 { -+ /* -+ * 0: Frame begins when vsync is high. -+ * 1: Frame begins when vsync changes from low to high. -+ */ -+ unsigned frame_start_on_rising_vs:1; -+ /* Use Bt synchronisation codes for sync correction. */ -+ unsigned bt_sync_correct:1; -+ /* Swap every two adjacent image data elements. */ -+ unsigned swap:1; -+ /* Inverted latch clock polarity from slave. */ -+ unsigned latch_clk_inv:1; -+ /* Hs polarity. 0 is active high, 1 active low. */ -+ unsigned nobt_hs_inv:1; -+ /* Vs polarity. 0 is active high, 1 active low. */ -+ unsigned nobt_vs_inv:1; -+ enum v4l2_if_type_bt656_mode mode; -+ /* Minimum accepted bus clock for slave (in Hz). */ -+ u32 clock_min; -+ /* Maximum accepted bus clock for slave. */ -+ u32 clock_max; -+ /* -+ * Current wish of the slave. May only change in response to -+ * ioctls that affect image capture. -+ */ -+ u32 clock_curr; -+}; -+ -+struct v4l2_ifparm { -+ enum v4l2_if_type if_type; -+ union { -+ struct v4l2_if_type_bt656 bt656; -+ } u; -+}; -+ -+/* IOCTL command numbers. */ -+enum v4l2_int_ioctl_num { -+ /* -+ * -+ * "Proper" V4L ioctls, as in struct video_device. -+ * -+ */ -+ vidioc_int_enum_fmt_cap_num = 1, -+ vidioc_int_g_fmt_cap_num, -+ vidioc_int_s_fmt_cap_num, -+ vidioc_int_try_fmt_cap_num, -+ vidioc_int_queryctrl_num, -+ vidioc_int_g_ctrl_num, -+ vidioc_int_s_ctrl_num, -+ vidioc_int_cropcap_num, -+ vidioc_int_g_crop_num, -+ vidioc_int_s_crop_num, -+ vidioc_int_g_parm_num, -+ vidioc_int_s_parm_num, -+ vidioc_int_querystd_num, -+ vidioc_int_s_std_num, -+ vidioc_int_s_video_routing_num, -+ vidioc_int_send_command_num, -+ -+ /* -+ * -+ * Strictly internal ioctls. -+ * -+ */ -+ /* Initialise the device when slave attaches to the master. */ -+ vidioc_int_dev_init_num = 1000, -+ /* Delinitialise the device at slave detach. */ -+ vidioc_int_dev_exit_num, -+ /* Set device power state. */ -+ vidioc_int_s_power_num, -+ /* -+ * Get slave private data, e.g. platform-specific slave -+ * configuration used by the master. -+ */ -+ vidioc_int_g_priv_num, -+ /* Get slave interface parameters. */ -+ vidioc_int_g_ifparm_num, -+ /* Does the slave need to be reset after VIDIOC_DQBUF? */ -+ vidioc_int_g_needs_reset_num, -+ vidioc_int_enum_framesizes_num, -+ vidioc_int_enum_frameintervals_num, -+ -+ /* -+ * -+ * VIDIOC_INT_* ioctls. -+ * -+ */ -+ /* VIDIOC_INT_RESET */ -+ vidioc_int_reset_num, -+ /* VIDIOC_INT_INIT */ -+ vidioc_int_init_num, -+ /* VIDIOC_DBG_G_CHIP_IDENT */ -+ vidioc_int_g_chip_ident_num, -+ -+ /* -+ * -+ * Start of private ioctls. -+ * -+ */ -+ vidioc_int_priv_start_num = 2000, -+}; -+ -+/* -+ * -+ * IOCTL wrapper functions for better type checking. -+ * -+ */ -+ -+#define V4L2_INT_WRAPPER_0(name) \ -+ static inline int vidioc_int_##name(struct v4l2_int_device *d) \ -+ { \ -+ return v4l2_int_ioctl_0(d, vidioc_int_##name##_num); \ -+ } \ -+ \ -+ static inline struct v4l2_int_ioctl_desc \ -+ vidioc_int_##name##_cb(int (*func) \ -+ (struct v4l2_int_device *)) \ -+ { \ -+ struct v4l2_int_ioctl_desc desc; \ -+ \ -+ desc.num = vidioc_int_##name##_num; \ -+ desc.func = (v4l2_int_ioctl_func *)func; \ -+ \ -+ return desc; \ -+ } -+ -+#define V4L2_INT_WRAPPER_1(name, arg_type, asterisk) \ -+ static inline int vidioc_int_##name(struct v4l2_int_device *d, \ -+ arg_type asterisk arg) \ -+ { \ -+ return v4l2_int_ioctl_1(d, vidioc_int_##name##_num, \ -+ (void *)(unsigned long)arg); \ -+ } \ -+ \ -+ static inline struct v4l2_int_ioctl_desc \ -+ vidioc_int_##name##_cb(int (*func) \ -+ (struct v4l2_int_device *, \ -+ arg_type asterisk)) \ -+ { \ -+ struct v4l2_int_ioctl_desc desc; \ -+ \ -+ desc.num = vidioc_int_##name##_num; \ -+ desc.func = (v4l2_int_ioctl_func *)func; \ -+ \ -+ return desc; \ -+ } -+ -+V4L2_INT_WRAPPER_1(enum_fmt_cap, struct v4l2_fmtdesc, *); -+V4L2_INT_WRAPPER_1(g_fmt_cap, struct v4l2_format, *); -+V4L2_INT_WRAPPER_1(s_fmt_cap, struct v4l2_format, *); -+V4L2_INT_WRAPPER_1(try_fmt_cap, struct v4l2_format, *); -+V4L2_INT_WRAPPER_1(queryctrl, struct v4l2_queryctrl, *); -+V4L2_INT_WRAPPER_1(g_ctrl, struct v4l2_control, *); -+V4L2_INT_WRAPPER_1(s_ctrl, struct v4l2_control, *); -+V4L2_INT_WRAPPER_1(cropcap, struct v4l2_cropcap, *); -+V4L2_INT_WRAPPER_1(g_crop, struct v4l2_crop, *); -+V4L2_INT_WRAPPER_1(s_crop, struct v4l2_crop, *); -+V4L2_INT_WRAPPER_1(g_parm, struct v4l2_streamparm, *); -+V4L2_INT_WRAPPER_1(s_parm, struct v4l2_streamparm, *); -+V4L2_INT_WRAPPER_1(querystd, v4l2_std_id, *); -+V4L2_INT_WRAPPER_1(s_std, v4l2_std_id, *); -+V4L2_INT_WRAPPER_1(s_video_routing, struct v4l2_routing, *); -+V4L2_INT_WRAPPER_1(send_command, struct v4l2_send_command_control, *); -+ -+V4L2_INT_WRAPPER_0(dev_init); -+V4L2_INT_WRAPPER_0(dev_exit); -+V4L2_INT_WRAPPER_1(s_power, enum v4l2_power, /*dummy arg*/); -+V4L2_INT_WRAPPER_1(g_priv, void, *); -+V4L2_INT_WRAPPER_1(g_ifparm, struct v4l2_ifparm, *); -+V4L2_INT_WRAPPER_1(g_needs_reset, void, *); -+V4L2_INT_WRAPPER_1(enum_framesizes, struct v4l2_frmsizeenum, *); -+V4L2_INT_WRAPPER_1(enum_frameintervals, struct v4l2_frmivalenum, *); -+ -+V4L2_INT_WRAPPER_0(reset); -+V4L2_INT_WRAPPER_0(init); -+V4L2_INT_WRAPPER_1(g_chip_ident, int, *); -+ -+#endif -diff -Nur linux-4.1.13.orig/drivers/media/platform/mxc/output/Kconfig linux-4.1.13/drivers/media/platform/mxc/output/Kconfig ---- linux-4.1.13.orig/drivers/media/platform/mxc/output/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/media/platform/mxc/output/Kconfig 2015-11-30 17:56:13.616135330 +0100 -@@ -0,0 +1,5 @@ -+config VIDEO_MXC_IPU_OUTPUT -+ tristate "IPU v4l2 output support" -+ depends on VIDEO_MXC_OUTPUT && MXC_IPU -+ ---help--- -+ This is the video4linux2 driver for IPU post processing video output. -diff -Nur linux-4.1.13.orig/drivers/media/platform/mxc/output/Makefile linux-4.1.13/drivers/media/platform/mxc/output/Makefile ---- linux-4.1.13.orig/drivers/media/platform/mxc/output/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/media/platform/mxc/output/Makefile 2015-11-30 17:56:13.616135330 +0100 -@@ -0,0 +1 @@ -+obj-$(CONFIG_VIDEO_MXC_IPU_OUTPUT) += mxc_vout.o -diff -Nur linux-4.1.13.orig/drivers/media/platform/mxc/output/mxc_vout.c linux-4.1.13/drivers/media/platform/mxc/output/mxc_vout.c ---- linux-4.1.13.orig/drivers/media/platform/mxc/output/mxc_vout.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/media/platform/mxc/output/mxc_vout.c 2015-11-30 17:56:13.616135330 +0100 -@@ -0,0 +1,2265 @@ -+/* -+ * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved. -+ */ -+ -+/* -+ * The code contained herein is licensed under the GNU General Public -+ * License. You may obtain a copy of the GNU General Public License -+ * Version 2 or later at the following locations: -+ * -+ * http://www.opensource.org/licenses/gpl-license.html -+ * http://www.gnu.org/copyleft/gpl.html -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#define UYVY_BLACK (0x00800080) -+#define RGB_BLACK (0x0) -+#define UV_BLACK (0x80) -+#define Y_BLACK (0x0) -+ -+#define MAX_FB_NUM 6 -+#define FB_BUFS 3 -+#define VDOA_FB_BUFS (FB_BUFS - 1) -+#define VALID_HEIGHT_1080P (1080) -+#define FRAME_HEIGHT_1080P (1088) -+#define FRAME_WIDTH_1080P (1920) -+#define CHECK_TILED_1080P_DISPLAY(vout) \ -+ ((((vout)->task.input.format == IPU_PIX_FMT_TILED_NV12) || \ -+ ((vout)->task.input.format == IPU_PIX_FMT_TILED_NV12F)) &&\ -+ ((vout)->task.input.width == FRAME_WIDTH_1080P) && \ -+ ((vout)->task.input.height == FRAME_HEIGHT_1080P) && \ -+ ((vout)->task.input.crop.w == FRAME_WIDTH_1080P) && \ -+ (((vout)->task.input.crop.h == FRAME_HEIGHT_1080P) || \ -+ ((vout)->task.input.crop.h == VALID_HEIGHT_1080P)) && \ -+ ((vout)->task.output.width == FRAME_WIDTH_1080P) && \ -+ ((vout)->task.output.height == VALID_HEIGHT_1080P) && \ -+ ((vout)->task.output.crop.w == FRAME_WIDTH_1080P) && \ -+ ((vout)->task.output.crop.h == VALID_HEIGHT_1080P)) -+#define CHECK_TILED_1080P_STREAM(vout) \ -+ ((((vout)->task.input.format == IPU_PIX_FMT_TILED_NV12) || \ -+ ((vout)->task.input.format == IPU_PIX_FMT_TILED_NV12F)) &&\ -+ ((vout)->task.input.width == FRAME_WIDTH_1080P) && \ -+ ((vout)->task.input.crop.w == FRAME_WIDTH_1080P) && \ -+ ((vout)->task.input.height == FRAME_HEIGHT_1080P) && \ -+ ((vout)->task.input.crop.h == FRAME_HEIGHT_1080P)) -+#define IS_PLANAR_PIXEL_FORMAT(format) \ -+ (format == IPU_PIX_FMT_NV12 || \ -+ format == IPU_PIX_FMT_YUV420P2 || \ -+ format == IPU_PIX_FMT_YUV420P || \ -+ format == IPU_PIX_FMT_YVU420P || \ -+ format == IPU_PIX_FMT_YUV422P || \ -+ format == IPU_PIX_FMT_YVU422P || \ -+ format == IPU_PIX_FMT_YUV444P) -+ -+#define NSEC_PER_FRAME_30FPS (33333333) -+ -+struct mxc_vout_fb { -+ char *name; -+ int ipu_id; -+ struct v4l2_rect crop_bounds; -+ unsigned int disp_fmt; -+ bool disp_support_csc; -+ bool disp_support_windows; -+}; -+ -+struct dma_mem { -+ void *vaddr; -+ dma_addr_t paddr; -+ size_t size; -+}; -+ -+struct mxc_vout_output { -+ int open_cnt; -+ struct fb_info *fbi; -+ unsigned long fb_smem_start; -+ unsigned long fb_smem_len; -+ struct video_device *vfd; -+ struct mutex mutex; -+ struct mutex task_lock; -+ enum v4l2_buf_type type; -+ -+ struct videobuf_queue vbq; -+ spinlock_t vbq_lock; -+ -+ struct list_head queue_list; -+ struct list_head active_list; -+ -+ struct v4l2_rect crop_bounds; -+ unsigned int disp_fmt; -+ struct mxcfb_pos win_pos; -+ bool disp_support_windows; -+ bool disp_support_csc; -+ -+ bool fmt_init; -+ bool release; -+ bool linear_bypass_pp; -+ bool vdoa_1080p; -+ bool tiled_bypass_pp; -+ struct v4l2_rect in_rect; -+ struct ipu_task task; -+ struct ipu_task vdoa_task; -+ struct dma_mem vdoa_work; -+ struct dma_mem vdoa_output[VDOA_FB_BUFS]; -+ -+ bool timer_stop; -+ struct hrtimer timer; -+ struct workqueue_struct *v4l_wq; -+ struct work_struct disp_work; -+ unsigned long frame_count; -+ unsigned long vdi_frame_cnt; -+ ktime_t start_ktime; -+ -+ int ctrl_rotate; -+ int ctrl_vflip; -+ int ctrl_hflip; -+ -+ dma_addr_t disp_bufs[FB_BUFS]; -+ -+ struct videobuf_buffer *pre1_vb; -+ struct videobuf_buffer *pre2_vb; -+}; -+ -+struct mxc_vout_dev { -+ struct device *dev; -+ struct v4l2_device v4l2_dev; -+ struct mxc_vout_output *out[MAX_FB_NUM]; -+ int out_num; -+}; -+ -+/* Driver Configuration macros */ -+#define VOUT_NAME "mxc_vout" -+ -+/* Variables configurable through module params*/ -+static int debug; -+static int vdi_rate_double; -+static int video_nr = 16; -+ -+/* Module parameters */ -+module_param(video_nr, int, S_IRUGO); -+MODULE_PARM_DESC(video_nr, "video device numbers"); -+module_param(debug, int, 0600); -+MODULE_PARM_DESC(debug, "Debug level (0-1)"); -+module_param(vdi_rate_double, int, 0600); -+MODULE_PARM_DESC(vdi_rate_double, "vdi frame rate double on/off"); -+ -+static const struct v4l2_fmtdesc mxc_formats[] = { -+ { -+ .description = "RGB565", -+ .pixelformat = V4L2_PIX_FMT_RGB565, -+ }, -+ { -+ .description = "BGR24", -+ .pixelformat = V4L2_PIX_FMT_BGR24, -+ }, -+ { -+ .description = "RGB24", -+ .pixelformat = V4L2_PIX_FMT_RGB24, -+ }, -+ { -+ .description = "RGB32", -+ .pixelformat = V4L2_PIX_FMT_RGB32, -+ }, -+ { -+ .description = "BGR32", -+ .pixelformat = V4L2_PIX_FMT_BGR32, -+ }, -+ { -+ .description = "NV12", -+ .pixelformat = V4L2_PIX_FMT_NV12, -+ }, -+ { -+ .description = "UYVY", -+ .pixelformat = V4L2_PIX_FMT_UYVY, -+ }, -+ { -+ .description = "YUYV", -+ .pixelformat = V4L2_PIX_FMT_YUYV, -+ }, -+ { -+ .description = "YUV422 planar", -+ .pixelformat = V4L2_PIX_FMT_YUV422P, -+ }, -+ { -+ .description = "YUV444", -+ .pixelformat = V4L2_PIX_FMT_YUV444, -+ }, -+ { -+ .description = "YUV420", -+ .pixelformat = V4L2_PIX_FMT_YUV420, -+ }, -+ { -+ .description = "YVU420", -+ .pixelformat = V4L2_PIX_FMT_YVU420, -+ }, -+ { -+ .description = "TILED NV12P", -+ .pixelformat = IPU_PIX_FMT_TILED_NV12, -+ }, -+ { -+ .description = "TILED NV12F", -+ .pixelformat = IPU_PIX_FMT_TILED_NV12F, -+ }, -+ { -+ .description = "YUV444 planar", -+ .pixelformat = IPU_PIX_FMT_YUV444P, -+ }, -+}; -+ -+#define NUM_MXC_VOUT_FORMATS (ARRAY_SIZE(mxc_formats)) -+ -+#define DEF_INPUT_WIDTH 320 -+#define DEF_INPUT_HEIGHT 240 -+ -+static int mxc_vidioc_streamoff(struct file *file, void *fh, -+ enum v4l2_buf_type i); -+ -+static struct mxc_vout_fb g_fb_setting[MAX_FB_NUM]; -+static int config_disp_output(struct mxc_vout_output *vout); -+static void release_disp_output(struct mxc_vout_output *vout); -+ -+static unsigned int get_frame_size(struct mxc_vout_output *vout) -+{ -+ unsigned int size; -+ -+ if (IPU_PIX_FMT_TILED_NV12 == vout->task.input.format) -+ size = TILED_NV12_FRAME_SIZE(vout->task.input.width, -+ vout->task.input.height); -+ else if (IPU_PIX_FMT_TILED_NV12F == vout->task.input.format) { -+ size = TILED_NV12_FRAME_SIZE(vout->task.input.width, -+ vout->task.input.height/2); -+ size *= 2; -+ } else -+ size = vout->task.input.width * vout->task.input.height * -+ fmt_to_bpp(vout->task.input.format)/8; -+ -+ return size; -+} -+ -+static void free_dma_buf(struct mxc_vout_output *vout, struct dma_mem *buf) -+{ -+ dma_free_coherent(vout->vbq.dev, buf->size, buf->vaddr, buf->paddr); -+ v4l2_dbg(1, debug, vout->vfd->v4l2_dev, -+ "free dma size:0x%x, paddr:0x%x\n", -+ buf->size, buf->paddr); -+ memset(buf, 0, sizeof(*buf)); -+} -+ -+static int alloc_dma_buf(struct mxc_vout_output *vout, struct dma_mem *buf) -+{ -+ -+ buf->vaddr = dma_alloc_coherent(vout->vbq.dev, buf->size, &buf->paddr, -+ GFP_DMA | GFP_KERNEL); -+ if (!buf->vaddr) { -+ v4l2_err(vout->vfd->v4l2_dev, -+ "cannot get dma buf size:0x%x\n", buf->size); -+ return -ENOMEM; -+ } -+ v4l2_dbg(1, debug, vout->vfd->v4l2_dev, -+ "alloc dma buf size:0x%x, paddr:0x%x\n", buf->size, buf->paddr); -+ return 0; -+} -+ -+static ipu_channel_t get_ipu_channel(struct fb_info *fbi) -+{ -+ ipu_channel_t ipu_ch = CHAN_NONE; -+ mm_segment_t old_fs; -+ -+ if (fbi->fbops->fb_ioctl) { -+ old_fs = get_fs(); -+ set_fs(KERNEL_DS); -+ fbi->fbops->fb_ioctl(fbi, MXCFB_GET_FB_IPU_CHAN, -+ (unsigned long)&ipu_ch); -+ set_fs(old_fs); -+ } -+ -+ return ipu_ch; -+} -+ -+static unsigned int get_ipu_fmt(struct fb_info *fbi) -+{ -+ mm_segment_t old_fs; -+ unsigned int fb_fmt; -+ -+ if (fbi->fbops->fb_ioctl) { -+ old_fs = get_fs(); -+ set_fs(KERNEL_DS); -+ fbi->fbops->fb_ioctl(fbi, MXCFB_GET_DIFMT, -+ (unsigned long)&fb_fmt); -+ set_fs(old_fs); -+ } -+ -+ return fb_fmt; -+} -+ -+static void update_display_setting(void) -+{ -+ int i; -+ struct fb_info *fbi; -+ struct v4l2_rect bg_crop_bounds[2]; -+ -+ for (i = 0; i < num_registered_fb; i++) { -+ fbi = registered_fb[i]; -+ -+ memset(&g_fb_setting[i], 0, sizeof(struct mxc_vout_fb)); -+ -+ if (!strncmp(fbi->fix.id, "DISP3", 5)) -+ g_fb_setting[i].ipu_id = 0; -+ else -+ g_fb_setting[i].ipu_id = 1; -+ -+ g_fb_setting[i].name = fbi->fix.id; -+ g_fb_setting[i].crop_bounds.left = 0; -+ g_fb_setting[i].crop_bounds.top = 0; -+ g_fb_setting[i].crop_bounds.width = fbi->var.xres; -+ g_fb_setting[i].crop_bounds.height = fbi->var.yres; -+ g_fb_setting[i].disp_fmt = get_ipu_fmt(fbi); -+ -+ if (get_ipu_channel(fbi) == MEM_BG_SYNC) { -+ bg_crop_bounds[g_fb_setting[i].ipu_id] = -+ g_fb_setting[i].crop_bounds; -+ g_fb_setting[i].disp_support_csc = true; -+ } else if (get_ipu_channel(fbi) == MEM_FG_SYNC) { -+ g_fb_setting[i].disp_support_csc = true; -+ g_fb_setting[i].disp_support_windows = true; -+ } -+ } -+ -+ for (i = 0; i < num_registered_fb; i++) { -+ fbi = registered_fb[i]; -+ -+ if (get_ipu_channel(fbi) == MEM_FG_SYNC) -+ g_fb_setting[i].crop_bounds = -+ bg_crop_bounds[g_fb_setting[i].ipu_id]; -+ } -+} -+ -+/* called after g_fb_setting filled by update_display_setting */ -+static int update_setting_from_fbi(struct mxc_vout_output *vout, -+ struct fb_info *fbi) -+{ -+ int i; -+ bool found = false; -+ -+ for (i = 0; i < MAX_FB_NUM; i++) { -+ if (g_fb_setting[i].name) { -+ if (!strcmp(fbi->fix.id, g_fb_setting[i].name)) { -+ vout->crop_bounds = g_fb_setting[i].crop_bounds; -+ vout->disp_fmt = g_fb_setting[i].disp_fmt; -+ vout->disp_support_csc = -+ g_fb_setting[i].disp_support_csc; -+ vout->disp_support_windows = -+ g_fb_setting[i].disp_support_windows; -+ found = true; -+ break; -+ } -+ } -+ } -+ -+ if (!found) { -+ v4l2_err(vout->vfd->v4l2_dev, "can not find output\n"); -+ return -EINVAL; -+ } -+ strlcpy(vout->vfd->name, fbi->fix.id, sizeof(vout->vfd->name)); -+ -+ memset(&vout->task, 0, sizeof(struct ipu_task)); -+ -+ vout->task.input.width = DEF_INPUT_WIDTH; -+ vout->task.input.height = DEF_INPUT_HEIGHT; -+ vout->task.input.crop.pos.x = 0; -+ vout->task.input.crop.pos.y = 0; -+ vout->task.input.crop.w = DEF_INPUT_WIDTH; -+ vout->task.input.crop.h = DEF_INPUT_HEIGHT; -+ -+ vout->task.output.width = vout->crop_bounds.width; -+ vout->task.output.height = vout->crop_bounds.height; -+ vout->task.output.crop.pos.x = 0; -+ vout->task.output.crop.pos.y = 0; -+ vout->task.output.crop.w = vout->crop_bounds.width; -+ vout->task.output.crop.h = vout->crop_bounds.height; -+ if (colorspaceofpixel(vout->disp_fmt) == YUV_CS) -+ vout->task.output.format = IPU_PIX_FMT_UYVY; -+ else -+ vout->task.output.format = IPU_PIX_FMT_RGB565; -+ -+ return 0; -+} -+ -+static inline unsigned long get_jiffies(struct timeval *t) -+{ -+ struct timeval cur; -+ -+ if (t->tv_usec >= 1000000) { -+ t->tv_sec += t->tv_usec / 1000000; -+ t->tv_usec = t->tv_usec % 1000000; -+ } -+ -+ do_gettimeofday(&cur); -+ if ((t->tv_sec < cur.tv_sec) -+ || ((t->tv_sec == cur.tv_sec) && (t->tv_usec < cur.tv_usec))) -+ return jiffies; -+ -+ if (t->tv_usec < cur.tv_usec) { -+ cur.tv_sec = t->tv_sec - cur.tv_sec - 1; -+ cur.tv_usec = t->tv_usec + 1000000 - cur.tv_usec; -+ } else { -+ cur.tv_sec = t->tv_sec - cur.tv_sec; -+ cur.tv_usec = t->tv_usec - cur.tv_usec; -+ } -+ -+ return jiffies + timeval_to_jiffies(&cur); -+} -+ -+static bool deinterlace_3_field(struct mxc_vout_output *vout) -+{ -+ return (vout->task.input.deinterlace.enable && -+ (vout->task.input.deinterlace.motion != HIGH_MOTION)); -+} -+ -+static int set_field_fmt(struct mxc_vout_output *vout, enum v4l2_field field) -+{ -+ struct ipu_deinterlace *deinterlace = &vout->task.input.deinterlace; -+ -+ switch (field) { -+ /* Images are in progressive format, not interlaced */ -+ case V4L2_FIELD_NONE: -+ case V4L2_FIELD_ANY: -+ deinterlace->enable = false; -+ deinterlace->field_fmt = 0; -+ v4l2_dbg(1, debug, vout->vfd->v4l2_dev, "Progressive frame.\n"); -+ break; -+ case V4L2_FIELD_INTERLACED_TB: -+ v4l2_dbg(1, debug, vout->vfd->v4l2_dev, -+ "Enable deinterlace TB.\n"); -+ deinterlace->enable = true; -+ deinterlace->field_fmt = IPU_DEINTERLACE_FIELD_TOP; -+ break; -+ case V4L2_FIELD_INTERLACED_BT: -+ v4l2_dbg(1, debug, vout->vfd->v4l2_dev, -+ "Enable deinterlace BT.\n"); -+ deinterlace->enable = true; -+ deinterlace->field_fmt = IPU_DEINTERLACE_FIELD_BOTTOM; -+ break; -+ default: -+ v4l2_err(vout->vfd->v4l2_dev, -+ "field format:%d not supported yet!\n", field); -+ return -EINVAL; -+ } -+ -+ if (IPU_PIX_FMT_TILED_NV12F == vout->task.input.format) { -+ v4l2_dbg(1, debug, vout->vfd->v4l2_dev, -+ "tiled fmt enable deinterlace.\n"); -+ deinterlace->enable = true; -+ } -+ -+ if (deinterlace->enable && vdi_rate_double) -+ deinterlace->field_fmt |= IPU_DEINTERLACE_RATE_EN; -+ -+ return 0; -+} -+ -+static bool is_pp_bypass(struct mxc_vout_output *vout) -+{ -+ if ((IPU_PIX_FMT_TILED_NV12 == vout->task.input.format) || -+ (IPU_PIX_FMT_TILED_NV12F == vout->task.input.format)) -+ return false; -+ if ((vout->task.input.width == vout->task.output.width) && -+ (vout->task.input.height == vout->task.output.height) && -+ (vout->task.input.crop.w == vout->task.output.crop.w) && -+ (vout->task.input.crop.h == vout->task.output.crop.h) && -+ (vout->task.output.rotate < IPU_ROTATE_HORIZ_FLIP) && -+ !vout->task.input.deinterlace.enable) { -+ if (vout->disp_support_csc) -+ return true; -+ else if (!need_csc(vout->task.input.format, vout->disp_fmt)) -+ return true; -+ /* -+ * input crop show to full output which can show based on -+ * xres_virtual/yres_virtual -+ */ -+ } else if ((vout->task.input.crop.w == vout->task.output.crop.w) && -+ (vout->task.output.crop.w == vout->task.output.width) && -+ (vout->task.input.crop.h == vout->task.output.crop.h) && -+ (vout->task.output.crop.h == -+ vout->task.output.height) && -+ (vout->task.output.rotate < IPU_ROTATE_HORIZ_FLIP) && -+ !vout->task.input.deinterlace.enable) { -+ if (vout->disp_support_csc) -+ return true; -+ else if (!need_csc(vout->task.input.format, vout->disp_fmt)) -+ return true; -+ } -+ return false; -+} -+ -+static void setup_buf_timer(struct mxc_vout_output *vout, -+ struct videobuf_buffer *vb) -+{ -+ ktime_t expiry_time, now; -+ -+ /* if timestamp is 0, then default to 30fps */ -+ if ((vb->ts.tv_sec == 0) && (vb->ts.tv_usec == 0)) -+ expiry_time = ktime_add_ns(vout->start_ktime, -+ NSEC_PER_FRAME_30FPS * vout->frame_count); -+ else -+ expiry_time = timeval_to_ktime(vb->ts); -+ -+ now = hrtimer_cb_get_time(&vout->timer); -+ if ((now.tv64 > expiry_time.tv64)) { -+ v4l2_dbg(1, debug, vout->vfd->v4l2_dev, -+ "warning: timer timeout already expired.\n"); -+ expiry_time = now; -+ } -+ -+ hrtimer_start(&vout->timer, expiry_time, HRTIMER_MODE_ABS); -+ -+ v4l2_dbg(1, debug, vout->vfd->v4l2_dev, "timer handler next " -+ "schedule: %lldnsecs\n", expiry_time.tv64); -+} -+ -+static int show_buf(struct mxc_vout_output *vout, int idx, -+ struct ipu_pos *ipos) -+{ -+ struct fb_info *fbi = vout->fbi; -+ struct fb_var_screeninfo var; -+ int ret; -+ u32 fb_base = 0; -+ -+ memcpy(&var, &fbi->var, sizeof(var)); -+ -+ if (vout->linear_bypass_pp || vout->tiled_bypass_pp) { -+ /* -+ * crack fb base -+ * NOTE: should not do other fb operation during v4l2 -+ */ -+ console_lock(); -+ fb_base = fbi->fix.smem_start; -+ fbi->fix.smem_start = vout->task.output.paddr; -+ fbi->var.yoffset = ipos->y + 1; -+ var.xoffset = ipos->x; -+ var.yoffset = ipos->y; -+ var.vmode |= FB_VMODE_YWRAP; -+ ret = fb_pan_display(fbi, &var); -+ fbi->fix.smem_start = fb_base; -+ console_unlock(); -+ } else { -+ console_lock(); -+ var.yoffset = idx * fbi->var.yres; -+ var.vmode &= ~FB_VMODE_YWRAP; -+ ret = fb_pan_display(fbi, &var); -+ console_unlock(); -+ } -+ -+ return ret; -+} -+ -+static void disp_work_func(struct work_struct *work) -+{ -+ struct mxc_vout_output *vout = -+ container_of(work, struct mxc_vout_output, disp_work); -+ struct videobuf_queue *q = &vout->vbq; -+ struct videobuf_buffer *vb, *vb_next = NULL; -+ unsigned long flags = 0; -+ struct ipu_pos ipos; -+ int ret = 0; -+ u32 in_fmt = 0; -+ u32 vdi_cnt = 0; -+ u32 vdi_frame; -+ u32 index = 0; -+ u32 ocrop_h = 0; -+ u32 o_height = 0; -+ u32 tiled_interlaced = 0; -+ bool tiled_fmt = false; -+ -+ v4l2_dbg(1, debug, vout->vfd->v4l2_dev, "disp work begin one frame\n"); -+ -+ spin_lock_irqsave(q->irqlock, flags); -+ -+ if (list_empty(&vout->active_list)) { -+ v4l2_warn(vout->vfd->v4l2_dev, -+ "no entry in active_list, should not be here\n"); -+ spin_unlock_irqrestore(q->irqlock, flags); -+ return; -+ } -+ -+ vb = list_first_entry(&vout->active_list, -+ struct videobuf_buffer, queue); -+ ret = set_field_fmt(vout, vb->field); -+ if (ret < 0) { -+ spin_unlock_irqrestore(q->irqlock, flags); -+ return; -+ } -+ if (deinterlace_3_field(vout)) { -+ if (list_is_singular(&vout->active_list)) { -+ if (list_empty(&vout->queue_list)) { -+ vout->timer_stop = true; -+ spin_unlock_irqrestore(q->irqlock, flags); -+ v4l2_warn(vout->vfd->v4l2_dev, -+ "no enough entry for 3 fields " -+ "deinterlacer\n"); -+ return; -+ } -+ -+ /* -+ * We need to use the next vb even if it is -+ * not on the active list. -+ */ -+ vb_next = list_first_entry(&vout->queue_list, -+ struct videobuf_buffer, queue); -+ } else -+ vb_next = list_first_entry(vout->active_list.next, -+ struct videobuf_buffer, queue); -+ v4l2_dbg(1, debug, vout->vfd->v4l2_dev, -+ "cur field_fmt:%d, next field_fmt:%d.\n", -+ vb->field, vb_next->field); -+ /* repeat the last field during field format changing */ -+ if ((vb->field != vb_next->field) && -+ (vb_next->field != V4L2_FIELD_NONE)) -+ vb_next = vb; -+ } -+ -+ spin_unlock_irqrestore(q->irqlock, flags); -+ -+vdi_frame_rate_double: -+ mutex_lock(&vout->task_lock); -+ -+ v4l2_dbg(1, debug, vout->vfd->v4l2_dev, -+ "v4l2 frame_cnt:%ld, vb_field:%d, fmt:%d\n", -+ vout->frame_count, vb->field, -+ vout->task.input.deinterlace.field_fmt); -+ if (vb->memory == V4L2_MEMORY_USERPTR) -+ vout->task.input.paddr = vb->baddr; -+ else -+ vout->task.input.paddr = videobuf_to_dma_contig(vb); -+ -+ if (vout->task.input.deinterlace.field_fmt & IPU_DEINTERLACE_RATE_EN) -+ index = vout->vdi_frame_cnt % FB_BUFS; -+ else -+ index = vout->frame_count % FB_BUFS; -+ if (vout->linear_bypass_pp) { -+ vout->task.output.paddr = vout->task.input.paddr; -+ ipos.x = vout->task.input.crop.pos.x; -+ ipos.y = vout->task.input.crop.pos.y; -+ } else { -+ if (deinterlace_3_field(vout)) { -+ if (vb->memory == V4L2_MEMORY_USERPTR) -+ vout->task.input.paddr_n = vb_next->baddr; -+ else -+ vout->task.input.paddr_n = -+ videobuf_to_dma_contig(vb_next); -+ } -+ vout->task.output.paddr = vout->disp_bufs[index]; -+ if (vout->vdoa_1080p) { -+ o_height = vout->task.output.height; -+ ocrop_h = vout->task.output.crop.h; -+ vout->task.output.height = FRAME_HEIGHT_1080P; -+ vout->task.output.crop.h = FRAME_HEIGHT_1080P; -+ } -+ tiled_fmt = -+ (IPU_PIX_FMT_TILED_NV12 == vout->task.input.format) || -+ (IPU_PIX_FMT_TILED_NV12F == vout->task.input.format); -+ if (vout->tiled_bypass_pp) { -+ ipos.x = vout->task.input.crop.pos.x; -+ ipos.y = vout->task.input.crop.pos.y; -+ } else if (tiled_fmt) { -+ vout->vdoa_task.input.paddr = vout->task.input.paddr; -+ if (deinterlace_3_field(vout)) -+ vout->vdoa_task.input.paddr_n = -+ vout->task.input.paddr_n; -+ vout->vdoa_task.output.paddr = vout->vdoa_work.paddr; -+ ret = ipu_queue_task(&vout->vdoa_task); -+ if (ret < 0) { -+ mutex_unlock(&vout->task_lock); -+ goto err; -+ } -+ vout->task.input.paddr = vout->vdoa_task.output.paddr; -+ in_fmt = vout->task.input.format; -+ vout->task.input.format = vout->vdoa_task.output.format; -+ if (vout->task.input.deinterlace.enable) { -+ tiled_interlaced = 1; -+ vout->task.input.deinterlace.enable = 0; -+ } -+ v4l2_dbg(1, debug, vout->vfd->v4l2_dev, -+ "tiled queue task\n"); -+ } -+ ret = ipu_queue_task(&vout->task); -+ if ((!vout->tiled_bypass_pp) && tiled_fmt) -+ vout->task.input.format = in_fmt; -+ if (tiled_interlaced) -+ vout->task.input.deinterlace.enable = 1; -+ if (ret < 0) { -+ mutex_unlock(&vout->task_lock); -+ goto err; -+ } -+ if (vout->vdoa_1080p) { -+ vout->task.output.crop.h = ocrop_h; -+ vout->task.output.height = o_height; -+ } -+ } -+ -+ mutex_unlock(&vout->task_lock); -+ -+ ret = show_buf(vout, index, &ipos); -+ if (ret < 0) -+ v4l2_dbg(1, debug, vout->vfd->v4l2_dev, -+ "show buf with ret %d\n", ret); -+ -+ if (vout->task.input.deinterlace.field_fmt & IPU_DEINTERLACE_RATE_EN) { -+ vdi_frame = vout->task.input.deinterlace.field_fmt -+ & IPU_DEINTERLACE_RATE_FRAME1; -+ if (vdi_frame) -+ vout->task.input.deinterlace.field_fmt &= -+ ~IPU_DEINTERLACE_RATE_FRAME1; -+ else -+ vout->task.input.deinterlace.field_fmt |= -+ IPU_DEINTERLACE_RATE_FRAME1; -+ vout->vdi_frame_cnt++; -+ vdi_cnt++; -+ if (vdi_cnt < IPU_DEINTERLACE_MAX_FRAME) -+ goto vdi_frame_rate_double; -+ } -+ spin_lock_irqsave(q->irqlock, flags); -+ -+ list_del(&vb->queue); -+ -+ /* -+ * The videobuf before the last one has been shown. Set -+ * VIDEOBUF_DONE state here to avoid tearing issue in ic bypass -+ * case, which makes sure a buffer being shown will not be -+ * dequeued to be overwritten. It also brings side-effect that -+ * the last 2 buffers can not be dequeued correctly, apps need -+ * to take care of it. -+ */ -+ if (vout->pre2_vb) { -+ vout->pre2_vb->state = VIDEOBUF_DONE; -+ wake_up_interruptible(&vout->pre2_vb->done); -+ vout->pre2_vb = NULL; -+ } -+ -+ if (vout->linear_bypass_pp) { -+ vout->pre2_vb = vout->pre1_vb; -+ vout->pre1_vb = vb; -+ } else { -+ if (vout->pre1_vb) { -+ vout->pre1_vb->state = VIDEOBUF_DONE; -+ wake_up_interruptible(&vout->pre1_vb->done); -+ vout->pre1_vb = NULL; -+ } -+ vb->state = VIDEOBUF_DONE; -+ wake_up_interruptible(&vb->done); -+ } -+ -+ vout->frame_count++; -+ -+ /* pick next queue buf to setup timer */ -+ if (list_empty(&vout->queue_list)) -+ vout->timer_stop = true; -+ else { -+ vb = list_first_entry(&vout->queue_list, -+ struct videobuf_buffer, queue); -+ setup_buf_timer(vout, vb); -+ } -+ -+ spin_unlock_irqrestore(q->irqlock, flags); -+ -+ v4l2_dbg(1, debug, vout->vfd->v4l2_dev, "disp work finish one frame\n"); -+ -+ return; -+err: -+ v4l2_err(vout->vfd->v4l2_dev, "display work fail ret = %d\n", ret); -+ vout->timer_stop = true; -+ vb->state = VIDEOBUF_ERROR; -+ return; -+} -+ -+static enum hrtimer_restart mxc_vout_timer_handler(struct hrtimer *timer) -+{ -+ struct mxc_vout_output *vout = container_of(timer, -+ struct mxc_vout_output, -+ timer); -+ struct videobuf_queue *q = &vout->vbq; -+ struct videobuf_buffer *vb; -+ unsigned long flags = 0; -+ -+ spin_lock_irqsave(q->irqlock, flags); -+ -+ /* -+ * put first queued entry into active, if previous entry did not -+ * finish, setup current entry's timer again. -+ */ -+ if (list_empty(&vout->queue_list)) { -+ spin_unlock_irqrestore(q->irqlock, flags); -+ return HRTIMER_NORESTART; -+ } -+ -+ /* move videobuf from queued list to active list */ -+ vb = list_first_entry(&vout->queue_list, -+ struct videobuf_buffer, queue); -+ list_del(&vb->queue); -+ list_add_tail(&vb->queue, &vout->active_list); -+ -+ if (queue_work(vout->v4l_wq, &vout->disp_work) == 0) { -+ v4l2_warn(vout->vfd->v4l2_dev, -+ "disp work was in queue already, queue buf again next time\n"); -+ list_del(&vb->queue); -+ list_add(&vb->queue, &vout->queue_list); -+ spin_unlock_irqrestore(q->irqlock, flags); -+ return HRTIMER_NORESTART; -+ } -+ -+ vb->state = VIDEOBUF_ACTIVE; -+ -+ spin_unlock_irqrestore(q->irqlock, flags); -+ -+ return HRTIMER_NORESTART; -+} -+ -+/* Video buffer call backs */ -+ -+/* -+ * Buffer setup function is called by videobuf layer when REQBUF ioctl is -+ * called. This is used to setup buffers and return size and count of -+ * buffers allocated. After the call to this buffer, videobuf layer will -+ * setup buffer queue depending on the size and count of buffers -+ */ -+static int mxc_vout_buffer_setup(struct videobuf_queue *q, unsigned int *count, -+ unsigned int *size) -+{ -+ struct mxc_vout_output *vout = q->priv_data; -+ unsigned int frame_size; -+ -+ if (!vout) -+ return -EINVAL; -+ -+ if (V4L2_BUF_TYPE_VIDEO_OUTPUT != q->type) -+ return -EINVAL; -+ -+ frame_size = get_frame_size(vout); -+ *size = PAGE_ALIGN(frame_size); -+ -+ return 0; -+} -+ -+/* -+ * This function will be called when VIDIOC_QBUF ioctl is called. -+ * It prepare buffers before give out for the display. This function -+ * converts user space virtual address into physical address if userptr memory -+ * exchange mechanism is used. -+ */ -+static int mxc_vout_buffer_prepare(struct videobuf_queue *q, -+ struct videobuf_buffer *vb, -+ enum v4l2_field field) -+{ -+ vb->state = VIDEOBUF_PREPARED; -+ return 0; -+} -+ -+/* -+ * Buffer queue funtion will be called from the videobuf layer when _QBUF -+ * ioctl is called. It is used to enqueue buffer, which is ready to be -+ * displayed. -+ * This function is protected by q->irqlock. -+ */ -+static void mxc_vout_buffer_queue(struct videobuf_queue *q, -+ struct videobuf_buffer *vb) -+{ -+ struct mxc_vout_output *vout = q->priv_data; -+ struct videobuf_buffer *active_vb; -+ -+ list_add_tail(&vb->queue, &vout->queue_list); -+ vb->state = VIDEOBUF_QUEUED; -+ -+ if (vout->timer_stop) { -+ if (deinterlace_3_field(vout) && -+ !list_empty(&vout->active_list)) { -+ active_vb = list_first_entry(&vout->active_list, -+ struct videobuf_buffer, queue); -+ setup_buf_timer(vout, active_vb); -+ } else { -+ setup_buf_timer(vout, vb); -+ } -+ vout->timer_stop = false; -+ } -+} -+ -+/* -+ * Buffer release function is called from videobuf layer to release buffer -+ * which are already allocated -+ */ -+static void mxc_vout_buffer_release(struct videobuf_queue *q, -+ struct videobuf_buffer *vb) -+{ -+ vb->state = VIDEOBUF_NEEDS_INIT; -+} -+ -+static int mxc_vout_mmap(struct file *file, struct vm_area_struct *vma) -+{ -+ int ret; -+ struct mxc_vout_output *vout = file->private_data; -+ -+ if (!vout) -+ return -ENODEV; -+ -+ ret = videobuf_mmap_mapper(&vout->vbq, vma); -+ if (ret < 0) -+ v4l2_err(vout->vfd->v4l2_dev, -+ "offset invalid [offset=0x%lx]\n", -+ (vma->vm_pgoff << PAGE_SHIFT)); -+ -+ return ret; -+} -+ -+static int mxc_vout_release(struct file *file) -+{ -+ unsigned int ret = 0; -+ struct videobuf_queue *q; -+ struct mxc_vout_output *vout = file->private_data; -+ -+ if (!vout) -+ return 0; -+ -+ if (--vout->open_cnt == 0) { -+ q = &vout->vbq; -+ if (q->streaming) -+ mxc_vidioc_streamoff(file, vout, vout->type); -+ else { -+ release_disp_output(vout); -+ videobuf_queue_cancel(q); -+ } -+ destroy_workqueue(vout->v4l_wq); -+ ret = videobuf_mmap_free(q); -+ } -+ -+ return ret; -+} -+ -+static int mxc_vout_open(struct file *file) -+{ -+ struct mxc_vout_output *vout = NULL; -+ int ret = 0; -+ -+ vout = video_drvdata(file); -+ -+ if (vout == NULL) -+ return -ENODEV; -+ -+ if (vout->open_cnt++ == 0) { -+ vout->ctrl_rotate = 0; -+ vout->ctrl_vflip = 0; -+ vout->ctrl_hflip = 0; -+ update_display_setting(); -+ ret = update_setting_from_fbi(vout, vout->fbi); -+ if (ret < 0) -+ goto err; -+ -+ vout->v4l_wq = create_singlethread_workqueue("v4l2q"); -+ if (!vout->v4l_wq) { -+ v4l2_err(vout->vfd->v4l2_dev, -+ "Could not create work queue\n"); -+ ret = -ENOMEM; -+ goto err; -+ } -+ -+ INIT_WORK(&vout->disp_work, disp_work_func); -+ -+ INIT_LIST_HEAD(&vout->queue_list); -+ INIT_LIST_HEAD(&vout->active_list); -+ -+ vout->fmt_init = false; -+ vout->frame_count = 0; -+ vout->vdi_frame_cnt = 0; -+ -+ vout->win_pos.x = 0; -+ vout->win_pos.y = 0; -+ vout->release = true; -+ } -+ -+ file->private_data = vout; -+ -+err: -+ return ret; -+} -+ -+/* -+ * V4L2 ioctls -+ */ -+static int mxc_vidioc_querycap(struct file *file, void *fh, -+ struct v4l2_capability *cap) -+{ -+ struct mxc_vout_output *vout = fh; -+ -+ strlcpy(cap->driver, VOUT_NAME, sizeof(cap->driver)); -+ strlcpy(cap->card, vout->vfd->name, sizeof(cap->card)); -+ cap->bus_info[0] = '\0'; -+ cap->capabilities = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_OUTPUT; -+ -+ return 0; -+} -+ -+static int mxc_vidioc_enum_fmt_vid_out(struct file *file, void *fh, -+ struct v4l2_fmtdesc *fmt) -+{ -+ if (fmt->index >= NUM_MXC_VOUT_FORMATS) -+ return -EINVAL; -+ -+ strlcpy(fmt->description, mxc_formats[fmt->index].description, -+ sizeof(fmt->description)); -+ fmt->pixelformat = mxc_formats[fmt->index].pixelformat; -+ -+ return 0; -+} -+ -+static int mxc_vidioc_g_fmt_vid_out(struct file *file, void *fh, -+ struct v4l2_format *f) -+{ -+ struct mxc_vout_output *vout = fh; -+ struct v4l2_rect rect; -+ -+ f->fmt.pix.width = vout->task.input.width; -+ f->fmt.pix.height = vout->task.input.height; -+ f->fmt.pix.pixelformat = vout->task.input.format; -+ f->fmt.pix.sizeimage = get_frame_size(vout); -+ -+ if (f->fmt.pix.priv) { -+ rect.left = vout->task.input.crop.pos.x; -+ rect.top = vout->task.input.crop.pos.y; -+ rect.width = vout->task.input.crop.w; -+ rect.height = vout->task.input.crop.h; -+ if (copy_to_user((void __user *)f->fmt.pix.priv, -+ &rect, sizeof(rect))) -+ return -EFAULT; -+ } -+ v4l2_dbg(1, debug, vout->vfd->v4l2_dev, -+ "frame_size:0x%x, pix_fmt:0x%x\n", -+ f->fmt.pix.sizeimage, -+ vout->task.input.format); -+ -+ return 0; -+} -+ -+static inline int ipu_try_task(struct mxc_vout_output *vout) -+{ -+ int ret; -+ struct ipu_task *task = &vout->task; -+ -+again: -+ ret = ipu_check_task(task); -+ if (ret != IPU_CHECK_OK) { -+ if (ret > IPU_CHECK_ERR_MIN) { -+ if (ret == IPU_CHECK_ERR_SPLIT_INPUTW_OVER || -+ ret == IPU_CHECK_ERR_W_DOWNSIZE_OVER) { -+ task->input.crop.w -= 8; -+ goto again; -+ } -+ if (ret == IPU_CHECK_ERR_SPLIT_INPUTH_OVER || -+ ret == IPU_CHECK_ERR_H_DOWNSIZE_OVER) { -+ task->input.crop.h -= 8; -+ goto again; -+ } -+ if (ret == IPU_CHECK_ERR_SPLIT_OUTPUTW_OVER) { -+ if (vout->disp_support_windows) { -+ task->output.width -= 8; -+ task->output.crop.w = -+ task->output.width; -+ } else -+ task->output.crop.w -= 8; -+ goto again; -+ } -+ if (ret == IPU_CHECK_ERR_SPLIT_OUTPUTH_OVER) { -+ if (vout->disp_support_windows) { -+ task->output.height -= 8; -+ task->output.crop.h = -+ task->output.height; -+ } else -+ task->output.crop.h -= 8; -+ goto again; -+ } -+ ret = -EINVAL; -+ } -+ } else -+ ret = 0; -+ -+ return ret; -+} -+ -+static inline int vdoaipu_try_task(struct mxc_vout_output *vout) -+{ -+ int ret; -+ int is_1080p_stream; -+ size_t size; -+ struct ipu_task *ipu_task = &vout->task; -+ struct ipu_crop *icrop = &ipu_task->input.crop; -+ struct ipu_task *vdoa_task = &vout->vdoa_task; -+ u32 deinterlace = 0; -+ u32 in_fmt; -+ -+ if (vout->task.input.deinterlace.enable) -+ deinterlace = 1; -+ -+ memset(vdoa_task, 0, sizeof(*vdoa_task)); -+ vdoa_task->output.format = IPU_PIX_FMT_NV12; -+ memcpy(&vdoa_task->input, &ipu_task->input, -+ sizeof(ipu_task->input)); -+ if ((icrop->w % IPU_PIX_FMT_TILED_NV12_MBALIGN) || -+ (icrop->h % IPU_PIX_FMT_TILED_NV12_MBALIGN)) { -+ vdoa_task->input.crop.w = -+ ALIGN(icrop->w, IPU_PIX_FMT_TILED_NV12_MBALIGN); -+ vdoa_task->input.crop.h = -+ ALIGN(icrop->h, IPU_PIX_FMT_TILED_NV12_MBALIGN); -+ } -+ vdoa_task->output.width = vdoa_task->input.crop.w; -+ vdoa_task->output.height = vdoa_task->input.crop.h; -+ vdoa_task->output.crop.w = vdoa_task->input.crop.w; -+ vdoa_task->output.crop.h = vdoa_task->input.crop.h; -+ -+ size = PAGE_ALIGN(vdoa_task->input.crop.w * -+ vdoa_task->input.crop.h * -+ fmt_to_bpp(vdoa_task->output.format)/8); -+ if (size > vout->vdoa_work.size) { -+ if (vout->vdoa_work.vaddr) -+ free_dma_buf(vout, &vout->vdoa_work); -+ vout->vdoa_work.size = size; -+ ret = alloc_dma_buf(vout, &vout->vdoa_work); -+ if (ret < 0) -+ return ret; -+ } -+ ret = ipu_check_task(vdoa_task); -+ if (ret != IPU_CHECK_OK) -+ return -EINVAL; -+ -+ is_1080p_stream = CHECK_TILED_1080P_STREAM(vout); -+ if (is_1080p_stream) -+ ipu_task->input.crop.h = VALID_HEIGHT_1080P; -+ in_fmt = ipu_task->input.format; -+ ipu_task->input.format = vdoa_task->output.format; -+ ipu_task->input.height = vdoa_task->output.height; -+ ipu_task->input.width = vdoa_task->output.width; -+ if (deinterlace) -+ ipu_task->input.deinterlace.enable = 0; -+ ret = ipu_try_task(vout); -+ if (deinterlace) -+ ipu_task->input.deinterlace.enable = 1; -+ ipu_task->input.format = in_fmt; -+ -+ return ret; -+} -+ -+static int mxc_vout_try_task(struct mxc_vout_output *vout) -+{ -+ int ret = 0; -+ struct ipu_output *output = &vout->task.output; -+ struct ipu_input *input = &vout->task.input; -+ struct ipu_crop *crop = &input->crop; -+ u32 o_height = 0; -+ u32 ocrop_h = 0; -+ bool tiled_fmt = false; -+ bool tiled_need_pp = false; -+ -+ vout->vdoa_1080p = CHECK_TILED_1080P_DISPLAY(vout); -+ if (vout->vdoa_1080p) { -+ input->crop.h = FRAME_HEIGHT_1080P; -+ o_height = output->height; -+ ocrop_h = output->crop.h; -+ output->height = FRAME_HEIGHT_1080P; -+ output->crop.h = FRAME_HEIGHT_1080P; -+ } -+ -+ if ((IPU_PIX_FMT_TILED_NV12 == input->format) || -+ (IPU_PIX_FMT_TILED_NV12F == input->format)) { -+ if ((input->width % IPU_PIX_FMT_TILED_NV12_MBALIGN) || -+ (input->height % IPU_PIX_FMT_TILED_NV12_MBALIGN) || -+ (crop->pos.x % IPU_PIX_FMT_TILED_NV12_MBALIGN) || -+ (crop->pos.y % IPU_PIX_FMT_TILED_NV12_MBALIGN)) { -+ v4l2_err(vout->vfd->v4l2_dev, -+ "ERR: tiled fmt needs 16 pixel align.\n"); -+ return -EINVAL; -+ } -+ if ((crop->w % IPU_PIX_FMT_TILED_NV12_MBALIGN) || -+ (crop->h % IPU_PIX_FMT_TILED_NV12_MBALIGN)) -+ tiled_need_pp = true; -+ } else { -+ crop->w -= crop->w % 8; -+ crop->h -= crop->h % 8; -+ } -+ /* assume task.output already set by S_CROP */ -+ vout->linear_bypass_pp = is_pp_bypass(vout); -+ if (vout->linear_bypass_pp) { -+ v4l2_info(vout->vfd->v4l2_dev, "Bypass IC.\n"); -+ output->format = input->format; -+ } else { -+ /* if need CSC, choose IPU-DP or IPU_IC do it */ -+ if (vout->disp_support_csc) { -+ if (colorspaceofpixel(input->format) == YUV_CS) -+ output->format = IPU_PIX_FMT_UYVY; -+ else -+ output->format = IPU_PIX_FMT_RGB565; -+ } else { -+ if (colorspaceofpixel(vout->disp_fmt) == YUV_CS) -+ output->format = IPU_PIX_FMT_UYVY; -+ else -+ output->format = IPU_PIX_FMT_RGB565; -+ } -+ -+ vout->tiled_bypass_pp = false; -+ if ((IPU_PIX_FMT_TILED_NV12 == input->format) || -+ (IPU_PIX_FMT_TILED_NV12F == input->format)) { -+ /* check resize/rotate/flip, or csc task */ -+ if (!(tiled_need_pp || -+ (IPU_ROTATE_NONE != output->rotate) || -+ (input->crop.w != output->crop.w) || -+ (input->crop.h != output->crop.h) || -+ (!vout->disp_support_csc && -+ (colorspaceofpixel(vout->disp_fmt) == RGB_CS))) -+ ) { -+ /* IC bypass */ -+ output->format = IPU_PIX_FMT_NV12; -+ v4l2_dbg(1, debug, vout->vfd->v4l2_dev, -+ "tiled bypass pp\n"); -+ vout->tiled_bypass_pp = true; -+ } -+ tiled_fmt = true; -+ } -+ -+ if ((!vout->tiled_bypass_pp) && tiled_fmt) -+ ret = vdoaipu_try_task(vout); -+ else -+ ret = ipu_try_task(vout); -+ } -+ -+ if (vout->vdoa_1080p) { -+ output->height = o_height; -+ output->crop.h = ocrop_h; -+ } -+ -+ v4l2_dbg(1, debug, vout->vfd->v4l2_dev, -+ "icrop.w:%u, icrop.h:%u, iw:%u, ih:%u," -+ "ocrop.w:%u, ocrop.h:%u, ow:%u, oh:%u\n", -+ input->crop.w, input->crop.h, -+ input->width, input->height, -+ output->crop.w, output->crop.h, -+ output->width, output->height); -+ return ret; -+} -+ -+static int mxc_vout_try_format(struct mxc_vout_output *vout, -+ struct v4l2_format *f) -+{ -+ int ret = 0; -+ struct v4l2_rect rect; -+ -+ if ((f->fmt.pix.field != V4L2_FIELD_NONE) && -+ (IPU_PIX_FMT_TILED_NV12 == vout->task.input.format)) { -+ v4l2_err(vout->vfd->v4l2_dev, -+ "progressive tiled fmt should used V4L2_FIELD_NONE!\n"); -+ return -EINVAL; -+ } -+ -+ if (f->fmt.pix.priv && copy_from_user(&rect, -+ (void __user *)f->fmt.pix.priv, sizeof(rect))) -+ return -EFAULT; -+ -+ vout->task.input.width = f->fmt.pix.width; -+ vout->task.input.height = f->fmt.pix.height; -+ vout->task.input.format = f->fmt.pix.pixelformat; -+ -+ ret = set_field_fmt(vout, f->fmt.pix.field); -+ if (ret < 0) -+ return ret; -+ -+ if (f->fmt.pix.priv) { -+ vout->task.input.crop.pos.x = rect.left; -+ vout->task.input.crop.pos.y = rect.top; -+ vout->task.input.crop.w = rect.width; -+ vout->task.input.crop.h = rect.height; -+ } else { -+ vout->task.input.crop.pos.x = 0; -+ vout->task.input.crop.pos.y = 0; -+ vout->task.input.crop.w = f->fmt.pix.width; -+ vout->task.input.crop.h = f->fmt.pix.height; -+ } -+ memcpy(&vout->in_rect, &vout->task.input.crop, sizeof(vout->in_rect)); -+ -+ ret = mxc_vout_try_task(vout); -+ if (!ret) { -+ if (f->fmt.pix.priv) { -+ rect.width = vout->task.input.crop.w; -+ rect.height = vout->task.input.crop.h; -+ if (copy_to_user((void __user *)f->fmt.pix.priv, -+ &rect, sizeof(rect))) -+ ret = -EFAULT; -+ } else { -+ f->fmt.pix.width = vout->task.input.crop.w; -+ f->fmt.pix.height = vout->task.input.crop.h; -+ } -+ } -+ -+ return ret; -+} -+ -+static bool mxc_vout_need_fb_reconfig(struct mxc_vout_output *vout, -+ struct mxc_vout_output *pre_vout) -+{ -+ if (!vout->vbq.streaming) -+ return false; -+ -+ if (vout->tiled_bypass_pp) -+ return true; -+ -+ if (vout->linear_bypass_pp != pre_vout->linear_bypass_pp) -+ return true; -+ -+ /* cropped output resolution or format are changed */ -+ if (vout->task.output.format != pre_vout->task.output.format || -+ vout->task.output.crop.w != pre_vout->task.output.crop.w || -+ vout->task.output.crop.h != pre_vout->task.output.crop.h) -+ return true; -+ -+ /* overlay: window position or resolution are changed */ -+ if (vout->disp_support_windows && -+ (vout->win_pos.x != pre_vout->win_pos.x || -+ vout->win_pos.y != pre_vout->win_pos.y || -+ vout->task.output.width != pre_vout->task.output.width || -+ vout->task.output.height != pre_vout->task.output.height)) -+ return true; -+ -+ /* background: cropped position is changed */ -+ if (!vout->disp_support_windows && -+ (vout->task.output.crop.pos.x != -+ pre_vout->task.output.crop.pos.x || -+ vout->task.output.crop.pos.y != -+ pre_vout->task.output.crop.pos.y)) -+ return true; -+ -+ return false; -+} -+ -+static int mxc_vidioc_s_fmt_vid_out(struct file *file, void *fh, -+ struct v4l2_format *f) -+{ -+ struct mxc_vout_output *vout = fh; -+ int ret = 0; -+ -+ if (vout->vbq.streaming) -+ return -EBUSY; -+ -+ mutex_lock(&vout->task_lock); -+ ret = mxc_vout_try_format(vout, f); -+ if (ret >= 0) -+ vout->fmt_init = true; -+ mutex_unlock(&vout->task_lock); -+ -+ return ret; -+} -+ -+static int mxc_vidioc_cropcap(struct file *file, void *fh, -+ struct v4l2_cropcap *cropcap) -+{ -+ struct mxc_vout_output *vout = fh; -+ -+ if (cropcap->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) -+ return -EINVAL; -+ -+ cropcap->bounds = vout->crop_bounds; -+ cropcap->defrect = vout->crop_bounds; -+ -+ return 0; -+} -+ -+static int mxc_vidioc_g_crop(struct file *file, void *fh, -+ struct v4l2_crop *crop) -+{ -+ struct mxc_vout_output *vout = fh; -+ -+ if (crop->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) -+ return -EINVAL; -+ -+ if (vout->disp_support_windows) { -+ crop->c.left = vout->win_pos.x; -+ crop->c.top = vout->win_pos.y; -+ crop->c.width = vout->task.output.width; -+ crop->c.height = vout->task.output.height; -+ } else { -+ if (vout->task.output.crop.w && vout->task.output.crop.h) { -+ crop->c.left = vout->task.output.crop.pos.x; -+ crop->c.top = vout->task.output.crop.pos.y; -+ crop->c.width = vout->task.output.crop.w; -+ crop->c.height = vout->task.output.crop.h; -+ } else { -+ crop->c.left = 0; -+ crop->c.top = 0; -+ crop->c.width = vout->task.output.width; -+ crop->c.height = vout->task.output.height; -+ } -+ } -+ -+ return 0; -+} -+ -+static int mxc_vidioc_s_crop(struct file *file, void *fh, -+ const struct v4l2_crop *crop) -+{ -+ struct mxc_vout_output *vout = fh, *pre_vout; -+ struct v4l2_rect *b = &vout->crop_bounds; -+ struct v4l2_crop fix_up_crop; -+ int ret = 0; -+ -+ memcpy(&fix_up_crop, crop, sizeof(*crop)); -+ -+ if (crop->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) -+ return -EINVAL; -+ -+ if (crop->c.width < 0 || crop->c.height < 0) -+ return -EINVAL; -+ -+ if (crop->c.width == 0) -+ fix_up_crop.c.width = b->width - b->left; -+ if (crop->c.height == 0) -+ fix_up_crop.c.height = b->height - b->top; -+ -+ if (crop->c.top < b->top) -+ fix_up_crop.c.top = b->top; -+ if (crop->c.top >= b->top + b->height) -+ fix_up_crop.c.top = b->top + b->height - 1; -+ if (crop->c.height > b->top - crop->c.top + b->height) -+ fix_up_crop.c.height = -+ b->top - fix_up_crop.c.top + b->height; -+ -+ if (crop->c.left < b->left) -+ fix_up_crop.c.left = b->left; -+ if (crop->c.left >= b->left + b->width) -+ fix_up_crop.c.left = b->left + b->width - 1; -+ if (crop->c.width > b->left - crop->c.left + b->width) -+ fix_up_crop.c.width = -+ b->left - fix_up_crop.c.left + b->width; -+ -+ /* stride line limitation */ -+ fix_up_crop.c.height -= fix_up_crop.c.height % 8; -+ fix_up_crop.c.width -= fix_up_crop.c.width % 8; -+ if ((fix_up_crop.c.width <= 0) || (fix_up_crop.c.height <= 0) || -+ ((fix_up_crop.c.left + fix_up_crop.c.width) > -+ (b->left + b->width)) || -+ ((fix_up_crop.c.top + fix_up_crop.c.height) > -+ (b->top + b->height))) { -+ v4l2_err(vout->vfd->v4l2_dev, "s_crop err: %d, %d, %d, %d", -+ fix_up_crop.c.left, fix_up_crop.c.top, -+ fix_up_crop.c.width, fix_up_crop.c.height); -+ return -EINVAL; -+ } -+ -+ /* the same setting, return */ -+ if (vout->disp_support_windows) { -+ if ((vout->win_pos.x == fix_up_crop.c.left) && -+ (vout->win_pos.y == fix_up_crop.c.top) && -+ (vout->task.output.crop.w == fix_up_crop.c.width) && -+ (vout->task.output.crop.h == fix_up_crop.c.height)) -+ return 0; -+ } else { -+ if ((vout->task.output.crop.pos.x == fix_up_crop.c.left) && -+ (vout->task.output.crop.pos.y == fix_up_crop.c.top) && -+ (vout->task.output.crop.w == fix_up_crop.c.width) && -+ (vout->task.output.crop.h == fix_up_crop.c.height)) -+ return 0; -+ } -+ -+ pre_vout = vmalloc(sizeof(*pre_vout)); -+ if (!pre_vout) -+ return -ENOMEM; -+ -+ /* wait current work finish */ -+ if (vout->vbq.streaming) -+ flush_workqueue(vout->v4l_wq); -+ -+ mutex_lock(&vout->task_lock); -+ -+ memcpy(pre_vout, vout, sizeof(*vout)); -+ -+ if (vout->disp_support_windows) { -+ vout->task.output.crop.pos.x = 0; -+ vout->task.output.crop.pos.y = 0; -+ vout->win_pos.x = fix_up_crop.c.left; -+ vout->win_pos.y = fix_up_crop.c.top; -+ vout->task.output.width = fix_up_crop.c.width; -+ vout->task.output.height = fix_up_crop.c.height; -+ } else { -+ vout->task.output.crop.pos.x = fix_up_crop.c.left; -+ vout->task.output.crop.pos.y = fix_up_crop.c.top; -+ } -+ -+ vout->task.output.crop.w = fix_up_crop.c.width; -+ vout->task.output.crop.h = fix_up_crop.c.height; -+ -+ /* -+ * must S_CROP before S_FMT, for fist time S_CROP, will not check -+ * ipu task, it will check in S_FMT, after S_FMT, S_CROP should -+ * check ipu task too. -+ */ -+ if (vout->fmt_init) { -+ memcpy(&vout->task.input.crop, &vout->in_rect, -+ sizeof(vout->in_rect)); -+ ret = mxc_vout_try_task(vout); -+ if (ret < 0) { -+ v4l2_err(vout->vfd->v4l2_dev, -+ "vout check task failed\n"); -+ memcpy(vout, pre_vout, sizeof(*vout)); -+ goto done; -+ } -+ -+ if (mxc_vout_need_fb_reconfig(vout, pre_vout)) { -+ ret = config_disp_output(vout); -+ if (ret < 0) -+ v4l2_err(vout->vfd->v4l2_dev, -+ "Config display output failed\n"); -+ } -+ } -+ -+done: -+ vfree(pre_vout); -+ mutex_unlock(&vout->task_lock); -+ -+ return ret; -+} -+ -+static int mxc_vidioc_queryctrl(struct file *file, void *fh, -+ struct v4l2_queryctrl *ctrl) -+{ -+ int ret = 0; -+ -+ switch (ctrl->id) { -+ case V4L2_CID_ROTATE: -+ ret = v4l2_ctrl_query_fill(ctrl, 0, 270, 90, 0); -+ break; -+ case V4L2_CID_VFLIP: -+ ret = v4l2_ctrl_query_fill(ctrl, 0, 1, 1, 0); -+ break; -+ case V4L2_CID_HFLIP: -+ ret = v4l2_ctrl_query_fill(ctrl, 0, 1, 1, 0); -+ break; -+ case V4L2_CID_MXC_MOTION: -+ ret = v4l2_ctrl_query_fill(ctrl, 0, 2, 1, 0); -+ break; -+ default: -+ ctrl->name[0] = '\0'; -+ ret = -EINVAL; -+ } -+ return ret; -+} -+ -+static int mxc_vidioc_g_ctrl(struct file *file, void *fh, -+ struct v4l2_control *ctrl) -+{ -+ int ret = 0; -+ struct mxc_vout_output *vout = fh; -+ -+ switch (ctrl->id) { -+ case V4L2_CID_ROTATE: -+ ctrl->value = vout->ctrl_rotate; -+ break; -+ case V4L2_CID_VFLIP: -+ ctrl->value = vout->ctrl_vflip; -+ break; -+ case V4L2_CID_HFLIP: -+ ctrl->value = vout->ctrl_hflip; -+ break; -+ case V4L2_CID_MXC_MOTION: -+ if (vout->task.input.deinterlace.enable) -+ ctrl->value = vout->task.input.deinterlace.motion; -+ else -+ ctrl->value = 0; -+ break; -+ default: -+ ret = -EINVAL; -+ } -+ return ret; -+} -+ -+static void setup_task_rotation(struct mxc_vout_output *vout) -+{ -+ if (vout->ctrl_rotate == 0) { -+ if (vout->ctrl_vflip && vout->ctrl_hflip) -+ vout->task.output.rotate = IPU_ROTATE_180; -+ else if (vout->ctrl_vflip) -+ vout->task.output.rotate = IPU_ROTATE_VERT_FLIP; -+ else if (vout->ctrl_hflip) -+ vout->task.output.rotate = IPU_ROTATE_HORIZ_FLIP; -+ else -+ vout->task.output.rotate = IPU_ROTATE_NONE; -+ } else if (vout->ctrl_rotate == 90) { -+ if (vout->ctrl_vflip && vout->ctrl_hflip) -+ vout->task.output.rotate = IPU_ROTATE_90_LEFT; -+ else if (vout->ctrl_vflip) -+ vout->task.output.rotate = IPU_ROTATE_90_RIGHT_VFLIP; -+ else if (vout->ctrl_hflip) -+ vout->task.output.rotate = IPU_ROTATE_90_RIGHT_HFLIP; -+ else -+ vout->task.output.rotate = IPU_ROTATE_90_RIGHT; -+ } else if (vout->ctrl_rotate == 180) { -+ if (vout->ctrl_vflip && vout->ctrl_hflip) -+ vout->task.output.rotate = IPU_ROTATE_NONE; -+ else if (vout->ctrl_vflip) -+ vout->task.output.rotate = IPU_ROTATE_HORIZ_FLIP; -+ else if (vout->ctrl_hflip) -+ vout->task.output.rotate = IPU_ROTATE_VERT_FLIP; -+ else -+ vout->task.output.rotate = IPU_ROTATE_180; -+ } else if (vout->ctrl_rotate == 270) { -+ if (vout->ctrl_vflip && vout->ctrl_hflip) -+ vout->task.output.rotate = IPU_ROTATE_90_RIGHT; -+ else if (vout->ctrl_vflip) -+ vout->task.output.rotate = IPU_ROTATE_90_RIGHT_HFLIP; -+ else if (vout->ctrl_hflip) -+ vout->task.output.rotate = IPU_ROTATE_90_RIGHT_VFLIP; -+ else -+ vout->task.output.rotate = IPU_ROTATE_90_LEFT; -+ } -+} -+ -+static int mxc_vidioc_s_ctrl(struct file *file, void *fh, -+ struct v4l2_control *ctrl) -+{ -+ int ret = 0; -+ struct mxc_vout_output *vout = fh, *pre_vout; -+ -+ pre_vout = vmalloc(sizeof(*pre_vout)); -+ if (!pre_vout) -+ return -ENOMEM; -+ -+ /* wait current work finish */ -+ if (vout->vbq.streaming) -+ flush_workqueue(vout->v4l_wq); -+ -+ mutex_lock(&vout->task_lock); -+ -+ memcpy(pre_vout, vout, sizeof(*vout)); -+ -+ switch (ctrl->id) { -+ case V4L2_CID_ROTATE: -+ { -+ vout->ctrl_rotate = (ctrl->value/90) * 90; -+ if (vout->ctrl_rotate > 270) -+ vout->ctrl_rotate = 270; -+ setup_task_rotation(vout); -+ break; -+ } -+ case V4L2_CID_VFLIP: -+ { -+ vout->ctrl_vflip = ctrl->value; -+ setup_task_rotation(vout); -+ break; -+ } -+ case V4L2_CID_HFLIP: -+ { -+ vout->ctrl_hflip = ctrl->value; -+ setup_task_rotation(vout); -+ break; -+ } -+ case V4L2_CID_MXC_MOTION: -+ { -+ vout->task.input.deinterlace.motion = ctrl->value; -+ break; -+ } -+ default: -+ ret = -EINVAL; -+ goto done; -+ } -+ -+ if (vout->fmt_init) { -+ memcpy(&vout->task.input.crop, &vout->in_rect, -+ sizeof(vout->in_rect)); -+ ret = mxc_vout_try_task(vout); -+ if (ret < 0) { -+ v4l2_err(vout->vfd->v4l2_dev, -+ "vout check task failed\n"); -+ memcpy(vout, pre_vout, sizeof(*vout)); -+ goto done; -+ } -+ -+ if (mxc_vout_need_fb_reconfig(vout, pre_vout)) { -+ ret = config_disp_output(vout); -+ if (ret < 0) -+ v4l2_err(vout->vfd->v4l2_dev, -+ "Config display output failed\n"); -+ } -+ } -+ -+done: -+ vfree(pre_vout); -+ mutex_unlock(&vout->task_lock); -+ -+ return ret; -+} -+ -+static int mxc_vidioc_reqbufs(struct file *file, void *fh, -+ struct v4l2_requestbuffers *req) -+{ -+ int ret = 0; -+ struct mxc_vout_output *vout = fh; -+ struct videobuf_queue *q = &vout->vbq; -+ -+ if (req->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) -+ return -EINVAL; -+ -+ /* should not be here after streaming, videobuf_reqbufs will control */ -+ mutex_lock(&vout->task_lock); -+ -+ ret = videobuf_reqbufs(q, req); -+ -+ mutex_unlock(&vout->task_lock); -+ return ret; -+} -+ -+static int mxc_vidioc_querybuf(struct file *file, void *fh, -+ struct v4l2_buffer *b) -+{ -+ int ret; -+ struct mxc_vout_output *vout = fh; -+ -+ ret = videobuf_querybuf(&vout->vbq, b); -+ if (!ret) { -+ /* return physical address */ -+ struct videobuf_buffer *vb = vout->vbq.bufs[b->index]; -+ if (b->flags & V4L2_BUF_FLAG_MAPPED) -+ b->m.offset = videobuf_to_dma_contig(vb); -+ } -+ -+ return ret; -+} -+ -+static int mxc_vidioc_qbuf(struct file *file, void *fh, -+ struct v4l2_buffer *buffer) -+{ -+ struct mxc_vout_output *vout = fh; -+ -+ return videobuf_qbuf(&vout->vbq, buffer); -+} -+ -+static int mxc_vidioc_dqbuf(struct file *file, void *fh, struct v4l2_buffer *b) -+{ -+ struct mxc_vout_output *vout = fh; -+ -+ if (!vout->vbq.streaming) -+ return -EINVAL; -+ -+ if (file->f_flags & O_NONBLOCK) -+ return videobuf_dqbuf(&vout->vbq, (struct v4l2_buffer *)b, 1); -+ else -+ return videobuf_dqbuf(&vout->vbq, (struct v4l2_buffer *)b, 0); -+} -+ -+static int set_window_position(struct mxc_vout_output *vout, -+ struct mxcfb_pos *pos) -+{ -+ struct fb_info *fbi = vout->fbi; -+ mm_segment_t old_fs; -+ int ret = 0; -+ -+ if (vout->disp_support_windows) { -+ old_fs = get_fs(); -+ set_fs(KERNEL_DS); -+ ret = fbi->fbops->fb_ioctl(fbi, MXCFB_SET_OVERLAY_POS, -+ (unsigned long)pos); -+ set_fs(old_fs); -+ } -+ -+ return ret; -+} -+ -+static int config_disp_output(struct mxc_vout_output *vout) -+{ -+ struct dma_mem *buf = NULL; -+ struct fb_info *fbi = vout->fbi; -+ struct fb_var_screeninfo var; -+ struct mxcfb_pos pos; -+ int i, fb_num, ret; -+ u32 fb_base; -+ u32 size; -+ u32 display_buf_size; -+ u32 *pixel = NULL; -+ u32 color; -+ int j; -+ -+ memcpy(&var, &fbi->var, sizeof(var)); -+ fb_base = fbi->fix.smem_start; -+ -+ var.xres = vout->task.output.width; -+ var.yres = vout->task.output.height; -+ if (vout->linear_bypass_pp || vout->tiled_bypass_pp) { -+ fb_num = 1; -+ /* input crop */ -+ if (vout->task.input.width > vout->task.output.width) -+ var.xres_virtual = vout->task.input.width; -+ else -+ var.xres_virtual = var.xres; -+ if (vout->task.input.height > vout->task.output.height) -+ var.yres_virtual = vout->task.input.height; -+ else -+ var.yres_virtual = var.yres; -+ var.rotate = vout->task.output.rotate; -+ var.vmode |= FB_VMODE_YWRAP; -+ } else { -+ fb_num = FB_BUFS; -+ var.xres_virtual = var.xres; -+ var.yres_virtual = fb_num * var.yres; -+ var.vmode &= ~FB_VMODE_YWRAP; -+ } -+ var.bits_per_pixel = fmt_to_bpp(vout->task.output.format); -+ var.nonstd = vout->task.output.format; -+ -+ v4l2_dbg(1, debug, vout->vfd->v4l2_dev, -+ "set display fb to %d %d\n", -+ var.xres, var.yres); -+ -+ /* -+ * To setup the overlay fb from scratch without -+ * the last time overlay fb position or resolution's -+ * impact, we take the following steps: -+ * - blank fb -+ * - set fb position to the starting point -+ * - reconfigure fb -+ * - set fb position to a specific point -+ * - unblank fb -+ * This procedure applies to non-overlay fbs as well. -+ */ -+ console_lock(); -+ fbi->flags |= FBINFO_MISC_USEREVENT; -+ fb_blank(fbi, FB_BLANK_POWERDOWN); -+ fbi->flags &= ~FBINFO_MISC_USEREVENT; -+ console_unlock(); -+ -+ pos.x = 0; -+ pos.y = 0; -+ ret = set_window_position(vout, &pos); -+ if (ret < 0) { -+ v4l2_err(vout->vfd->v4l2_dev, "failed to set fb position " -+ "to starting point\n"); -+ return ret; -+ } -+ -+ /* Init display channel through fb API */ -+ var.yoffset = 0; -+ var.activate |= FB_ACTIVATE_FORCE; -+ console_lock(); -+ fbi->flags |= FBINFO_MISC_USEREVENT; -+ ret = fb_set_var(fbi, &var); -+ fbi->flags &= ~FBINFO_MISC_USEREVENT; -+ console_unlock(); -+ if (ret < 0) { -+ v4l2_err(vout->vfd->v4l2_dev, -+ "ERR:%s fb_set_var ret:%d\n", __func__, ret); -+ return ret; -+ } -+ -+ ret = set_window_position(vout, &vout->win_pos); -+ if (ret < 0) { -+ v4l2_err(vout->vfd->v4l2_dev, "failed to set fb position\n"); -+ return ret; -+ } -+ -+ if (vout->linear_bypass_pp || vout->tiled_bypass_pp) -+ display_buf_size = fbi->fix.line_length * fbi->var.yres_virtual; -+ else -+ display_buf_size = fbi->fix.line_length * fbi->var.yres; -+ for (i = 0; i < fb_num; i++) -+ vout->disp_bufs[i] = fbi->fix.smem_start + i * display_buf_size; -+ if (vout->tiled_bypass_pp) { -+ size = PAGE_ALIGN(vout->task.input.crop.w * -+ vout->task.input.crop.h * -+ fmt_to_bpp(vout->task.output.format)/8); -+ if (size > vout->vdoa_output[0].size) { -+ for (i = 0; i < VDOA_FB_BUFS; i++) { -+ buf = &vout->vdoa_output[i]; -+ if (buf->vaddr) -+ free_dma_buf(vout, buf); -+ buf->size = size; -+ ret = alloc_dma_buf(vout, buf); -+ if (ret < 0) -+ goto err; -+ } -+ } -+ for (i = fb_num; i < (fb_num + VDOA_FB_BUFS); i++) -+ vout->disp_bufs[i] = -+ vout->vdoa_output[i - fb_num].paddr; -+ } -+ vout->fb_smem_len = fbi->fix.smem_len; -+ vout->fb_smem_start = fbi->fix.smem_start; -+ if (fb_base != fbi->fix.smem_start) { -+ v4l2_dbg(1, debug, vout->vfd->v4l2_dev, -+ "realloc fb mem size:0x%x@0x%lx,old paddr @0x%x\n", -+ fbi->fix.smem_len, fbi->fix.smem_start, fb_base); -+ } -+ -+ /* fill black when video config changed */ -+ color = colorspaceofpixel(vout->task.output.format) == YUV_CS ? -+ UYVY_BLACK : RGB_BLACK; -+ if (IS_PLANAR_PIXEL_FORMAT(vout->task.output.format)) { -+ size = display_buf_size * 8 / -+ fmt_to_bpp(vout->task.output.format); -+ memset(fbi->screen_base, Y_BLACK, size); -+ memset(fbi->screen_base + size, UV_BLACK, -+ display_buf_size - size); -+ } else { -+ pixel = (u32 *)fbi->screen_base; -+ for (i = 0; i < (display_buf_size >> 2); i++) -+ *pixel++ = color; -+ } -+ console_lock(); -+ fbi->flags |= FBINFO_MISC_USEREVENT; -+ ret = fb_blank(fbi, FB_BLANK_UNBLANK); -+ fbi->flags &= ~FBINFO_MISC_USEREVENT; -+ console_unlock(); -+ vout->release = false; -+ -+ return ret; -+err: -+ for (j = i - 1; j >= 0; j--) { -+ buf = &vout->vdoa_output[j]; -+ if (buf->vaddr) -+ free_dma_buf(vout, buf); -+ } -+ return ret; -+} -+ -+static inline void wait_for_vsync(struct mxc_vout_output *vout) -+{ -+ struct fb_info *fbi = vout->fbi; -+ mm_segment_t old_fs; -+ -+ if (fbi->fbops->fb_ioctl) { -+ old_fs = get_fs(); -+ set_fs(KERNEL_DS); -+ fbi->fbops->fb_ioctl(fbi, MXCFB_WAIT_FOR_VSYNC, -+ (unsigned long)NULL); -+ set_fs(old_fs); -+ } -+ -+ return; -+} -+ -+static void release_disp_output(struct mxc_vout_output *vout) -+{ -+ struct fb_info *fbi = vout->fbi; -+ struct mxcfb_pos pos; -+ -+ if (vout->release) -+ return; -+ console_lock(); -+ fbi->flags |= FBINFO_MISC_USEREVENT; -+ fb_blank(fbi, FB_BLANK_POWERDOWN); -+ fbi->flags &= ~FBINFO_MISC_USEREVENT; -+ console_unlock(); -+ -+ /* restore pos to 0,0 avoid fb pan display hang? */ -+ pos.x = 0; -+ pos.y = 0; -+ set_window_position(vout, &pos); -+ -+ if (get_ipu_channel(fbi) == MEM_BG_SYNC) { -+ console_lock(); -+ fbi->fix.smem_start = vout->disp_bufs[0]; -+ fbi->flags |= FBINFO_MISC_USEREVENT; -+ fb_blank(fbi, FB_BLANK_UNBLANK); -+ fbi->flags &= ~FBINFO_MISC_USEREVENT; -+ console_unlock(); -+ -+ } -+ -+ vout->release = true; -+} -+ -+static int mxc_vidioc_streamon(struct file *file, void *fh, -+ enum v4l2_buf_type i) -+{ -+ struct mxc_vout_output *vout = fh; -+ struct videobuf_queue *q = &vout->vbq; -+ int ret; -+ -+ if (q->streaming) { -+ v4l2_err(vout->vfd->v4l2_dev, -+ "video output already run\n"); -+ ret = -EBUSY; -+ goto done; -+ } -+ -+ if (deinterlace_3_field(vout) && list_is_singular(&q->stream)) { -+ v4l2_err(vout->vfd->v4l2_dev, -+ "deinterlacing: need queue 2 frame before streamon\n"); -+ ret = -EINVAL; -+ goto done; -+ } -+ -+ ret = config_disp_output(vout); -+ if (ret < 0) { -+ v4l2_err(vout->vfd->v4l2_dev, -+ "Config display output failed\n"); -+ goto done; -+ } -+ -+ hrtimer_init(&vout->timer, CLOCK_REALTIME, HRTIMER_MODE_ABS); -+ vout->timer.function = mxc_vout_timer_handler; -+ vout->timer_stop = true; -+ -+ vout->start_ktime = hrtimer_cb_get_time(&vout->timer); -+ -+ vout->pre1_vb = NULL; -+ vout->pre2_vb = NULL; -+ -+ ret = videobuf_streamon(q); -+done: -+ return ret; -+} -+ -+static int mxc_vidioc_streamoff(struct file *file, void *fh, -+ enum v4l2_buf_type i) -+{ -+ struct mxc_vout_output *vout = fh; -+ struct videobuf_queue *q = &vout->vbq; -+ int ret = 0; -+ -+ if (q->streaming) { -+ flush_workqueue(vout->v4l_wq); -+ -+ hrtimer_cancel(&vout->timer); -+ -+ /* -+ * Wait for 2 vsyncs to make sure -+ * frames are drained on triple -+ * buffer. -+ */ -+ wait_for_vsync(vout); -+ wait_for_vsync(vout); -+ -+ release_disp_output(vout); -+ -+ ret = videobuf_streamoff(&vout->vbq); -+ } -+ INIT_LIST_HEAD(&vout->queue_list); -+ INIT_LIST_HEAD(&vout->active_list); -+ -+ return ret; -+} -+ -+static const struct v4l2_ioctl_ops mxc_vout_ioctl_ops = { -+ .vidioc_querycap = mxc_vidioc_querycap, -+ .vidioc_enum_fmt_vid_out = mxc_vidioc_enum_fmt_vid_out, -+ .vidioc_g_fmt_vid_out = mxc_vidioc_g_fmt_vid_out, -+ .vidioc_s_fmt_vid_out = mxc_vidioc_s_fmt_vid_out, -+ .vidioc_cropcap = mxc_vidioc_cropcap, -+ .vidioc_g_crop = mxc_vidioc_g_crop, -+ .vidioc_s_crop = mxc_vidioc_s_crop, -+ .vidioc_queryctrl = mxc_vidioc_queryctrl, -+ .vidioc_g_ctrl = mxc_vidioc_g_ctrl, -+ .vidioc_s_ctrl = mxc_vidioc_s_ctrl, -+ .vidioc_reqbufs = mxc_vidioc_reqbufs, -+ .vidioc_querybuf = mxc_vidioc_querybuf, -+ .vidioc_qbuf = mxc_vidioc_qbuf, -+ .vidioc_dqbuf = mxc_vidioc_dqbuf, -+ .vidioc_streamon = mxc_vidioc_streamon, -+ .vidioc_streamoff = mxc_vidioc_streamoff, -+}; -+ -+static const struct v4l2_file_operations mxc_vout_fops = { -+ .owner = THIS_MODULE, -+ .unlocked_ioctl = video_ioctl2, -+ .mmap = mxc_vout_mmap, -+ .open = mxc_vout_open, -+ .release = mxc_vout_release, -+}; -+ -+static struct video_device mxc_vout_template = { -+ .name = "MXC Video Output", -+ .fops = &mxc_vout_fops, -+ .ioctl_ops = &mxc_vout_ioctl_ops, -+ .release = video_device_release, -+}; -+ -+static struct videobuf_queue_ops mxc_vout_vbq_ops = { -+ .buf_setup = mxc_vout_buffer_setup, -+ .buf_prepare = mxc_vout_buffer_prepare, -+ .buf_release = mxc_vout_buffer_release, -+ .buf_queue = mxc_vout_buffer_queue, -+}; -+ -+static void mxc_vout_free_output(struct mxc_vout_dev *dev) -+{ -+ int i; -+ int j; -+ struct mxc_vout_output *vout; -+ struct video_device *vfd; -+ -+ for (i = 0; i < dev->out_num; i++) { -+ vout = dev->out[i]; -+ vfd = vout->vfd; -+ if (vout->vdoa_work.vaddr) -+ free_dma_buf(vout, &vout->vdoa_work); -+ for (j = 0; j < VDOA_FB_BUFS; j++) { -+ if (vout->vdoa_output[j].vaddr) -+ free_dma_buf(vout, &vout->vdoa_output[j]); -+ } -+ if (vfd) { -+ if (!video_is_registered(vfd)) -+ video_device_release(vfd); -+ else -+ video_unregister_device(vfd); -+ } -+ kfree(vout); -+ } -+} -+ -+static int mxc_vout_setup_output(struct mxc_vout_dev *dev) -+{ -+ struct videobuf_queue *q; -+ struct fb_info *fbi; -+ struct mxc_vout_output *vout; -+ int i, ret = 0; -+ -+ update_display_setting(); -+ -+ /* all output/overlay based on fb */ -+ for (i = 0; i < num_registered_fb; i++) { -+ fbi = registered_fb[i]; -+ -+ vout = kzalloc(sizeof(struct mxc_vout_output), GFP_KERNEL); -+ if (!vout) { -+ ret = -ENOMEM; -+ break; -+ } -+ -+ dev->out[dev->out_num] = vout; -+ dev->out_num++; -+ -+ vout->fbi = fbi; -+ vout->type = V4L2_BUF_TYPE_VIDEO_OUTPUT; -+ vout->vfd = video_device_alloc(); -+ if (!vout->vfd) { -+ ret = -ENOMEM; -+ break; -+ } -+ -+ *vout->vfd = mxc_vout_template; -+ vout->vfd->dev_debug = debug; -+ vout->vfd->v4l2_dev = &dev->v4l2_dev; -+ vout->vfd->lock = &vout->mutex; -+ vout->vfd->vfl_dir = VFL_DIR_TX; -+ -+ mutex_init(&vout->mutex); -+ mutex_init(&vout->task_lock); -+ -+ strlcpy(vout->vfd->name, fbi->fix.id, sizeof(vout->vfd->name)); -+ -+ video_set_drvdata(vout->vfd, vout); -+ -+ if (video_register_device(vout->vfd, -+ VFL_TYPE_GRABBER, video_nr + i) < 0) { -+ ret = -ENODEV; -+ break; -+ } -+ -+ q = &vout->vbq; -+ q->dev = dev->dev; -+ spin_lock_init(&vout->vbq_lock); -+ videobuf_queue_dma_contig_init(q, &mxc_vout_vbq_ops, q->dev, -+ &vout->vbq_lock, vout->type, V4L2_FIELD_NONE, -+ sizeof(struct videobuf_buffer), vout, NULL); -+ -+ v4l2_info(vout->vfd->v4l2_dev, "V4L2 device registered as %s\n", -+ video_device_node_name(vout->vfd)); -+ -+ } -+ -+ return ret; -+} -+ -+static int mxc_vout_probe(struct platform_device *pdev) -+{ -+ int ret; -+ struct mxc_vout_dev *dev; -+ -+ dev = kzalloc(sizeof(*dev), GFP_KERNEL); -+ if (!dev) -+ return -ENOMEM; -+ -+ dev->dev = &pdev->dev; -+ dev->dev->dma_mask = kmalloc(sizeof(*dev->dev->dma_mask), GFP_KERNEL); -+ *dev->dev->dma_mask = DMA_BIT_MASK(32); -+ dev->dev->coherent_dma_mask = DMA_BIT_MASK(32); -+ -+ ret = v4l2_device_register(dev->dev, &dev->v4l2_dev); -+ if (ret) { -+ dev_err(dev->dev, "v4l2_device_register failed\n"); -+ goto free_dev; -+ } -+ -+ ret = mxc_vout_setup_output(dev); -+ if (ret < 0) -+ goto rel_vdev; -+ -+ return 0; -+ -+rel_vdev: -+ mxc_vout_free_output(dev); -+ v4l2_device_unregister(&dev->v4l2_dev); -+free_dev: -+ kfree(dev); -+ return ret; -+} -+ -+static int mxc_vout_remove(struct platform_device *pdev) -+{ -+ struct v4l2_device *v4l2_dev = platform_get_drvdata(pdev); -+ struct mxc_vout_dev *dev = container_of(v4l2_dev, struct -+ mxc_vout_dev, v4l2_dev); -+ -+ mxc_vout_free_output(dev); -+ v4l2_device_unregister(v4l2_dev); -+ kfree(dev); -+ return 0; -+} -+ -+static const struct of_device_id mxc_v4l2_dt_ids[] = { -+ { .compatible = "fsl,mxc_v4l2_output", }, -+ { /* sentinel */ } -+}; -+ -+static struct platform_driver mxc_vout_driver = { -+ .driver = { -+ .name = "mxc_v4l2_output", -+ .of_match_table = mxc_v4l2_dt_ids, -+ }, -+ .probe = mxc_vout_probe, -+ .remove = mxc_vout_remove, -+}; -+ -+static int __init mxc_vout_init(void) -+{ -+ if (platform_driver_register(&mxc_vout_driver) != 0) { -+ printk(KERN_ERR VOUT_NAME ":Could not register Video driver\n"); -+ return -EINVAL; -+ } -+ return 0; -+} -+ -+static void mxc_vout_cleanup(void) -+{ -+ platform_driver_unregister(&mxc_vout_driver); -+} -+ -+module_init(mxc_vout_init); -+module_exit(mxc_vout_cleanup); -+ -+MODULE_AUTHOR("Freescale Semiconductor, Inc."); -+MODULE_DESCRIPTION("V4L2-driver for MXC video output"); -+MODULE_LICENSE("GPL"); -diff -Nur linux-4.1.13.orig/drivers/media/platform/mxc/v4l2-extra.h linux-4.1.13/drivers/media/platform/mxc/v4l2-extra.h ---- linux-4.1.13.orig/drivers/media/platform/mxc/v4l2-extra.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/media/platform/mxc/v4l2-extra.h 2015-11-30 17:56:13.616135330 +0100 -@@ -0,0 +1,11 @@ -+/* -+struct v4l2_send_command_control { -+ __u32 id; -+ __u32 value0; -+ __u32 value1; -+ char debug[256]; -+}; -+*/ -+ -+#define VIDIOC_SEND_COMMAND _IOWR('V', 92, struct v4l2_send_command_control) -+ -diff -Nur linux-4.1.13.orig/drivers/media/v4l2-core/Kconfig linux-4.1.13/drivers/media/v4l2-core/Kconfig ---- linux-4.1.13.orig/drivers/media/v4l2-core/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/media/v4l2-core/Kconfig 2015-11-30 17:56:13.616135330 +0100 -@@ -44,6 +44,10 @@ - tristate - depends on VIDEOBUF2_CORE - -+config VIDEO_V4L2_INT_DEVICE -+ tristate -+ depends on VIDEO_V4L2 -+ - # Used by drivers that need Videobuf modules - config VIDEOBUF_GEN - tristate -diff -Nur linux-4.1.13.orig/drivers/media/v4l2-core/Makefile linux-4.1.13/drivers/media/v4l2-core/Makefile ---- linux-4.1.13.orig/drivers/media/v4l2-core/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/media/v4l2-core/Makefile 2015-11-30 17:56:13.616135330 +0100 -@@ -21,6 +21,7 @@ - obj-$(CONFIG_VIDEO_TUNER) += tuner.o - - obj-$(CONFIG_V4L2_MEM2MEM_DEV) += v4l2-mem2mem.o -+obj-$(CONFIG_V4L2_INT_DEVICE) += v4l2-int-device.o - - obj-$(CONFIG_VIDEOBUF_GEN) += videobuf-core.o - obj-$(CONFIG_VIDEOBUF_DMA_SG) += videobuf-dma-sg.o -diff -Nur linux-4.1.13.orig/drivers/media/v4l2-core/v4l2-compat-ioctl32.c linux-4.1.13/drivers/media/v4l2-core/v4l2-compat-ioctl32.c ---- linux-4.1.13.orig/drivers/media/v4l2-core/v4l2-compat-ioctl32.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/media/v4l2-core/v4l2-compat-ioctl32.c 2015-11-30 17:56:13.616135330 +0100 -@@ -251,7 +251,8 @@ - - static int put_v4l2_format32(struct v4l2_format *kp, struct v4l2_format32 __user *up) - { -- if (!access_ok(VERIFY_WRITE, up, sizeof(struct v4l2_format32))) -+ if (!access_ok(VERIFY_WRITE, up, sizeof(struct v4l2_format32)) || -+ put_user(kp->type, &up->type)) - return -EFAULT; - return __put_v4l2_format32(kp, up); - } -@@ -259,8 +260,8 @@ - static int put_v4l2_create32(struct v4l2_create_buffers *kp, struct v4l2_create_buffers32 __user *up) - { - if (!access_ok(VERIFY_WRITE, up, sizeof(struct v4l2_create_buffers32)) || -- copy_to_user(up, kp, offsetof(struct v4l2_create_buffers32, format))) -- return -EFAULT; -+ copy_to_user(up, kp, offsetof(struct v4l2_create_buffers32, format.fmt))) -+ return -EFAULT; - return __put_v4l2_format32(&kp->format, &up->format); - } - -@@ -330,7 +331,7 @@ - __u32 reserved; - }; - --static int get_v4l2_plane32(struct v4l2_plane __user *up, struct v4l2_plane32 __user *up32, -+static int get_v4l2_plane32(struct v4l2_plane *up, struct v4l2_plane32 *up32, - enum v4l2_memory memory) - { - void __user *up_pln; -@@ -359,7 +360,7 @@ - return 0; - } - --static int put_v4l2_plane32(struct v4l2_plane __user *up, struct v4l2_plane32 __user *up32, -+static int put_v4l2_plane32(struct v4l2_plane *up, struct v4l2_plane32 *up32, - enum v4l2_memory memory) - { - if (copy_in_user(up32, up, 2 * sizeof(__u32)) || -@@ -429,7 +430,7 @@ - * by passing a very big num_planes value */ - uplane = compat_alloc_user_space(num_planes * - sizeof(struct v4l2_plane)); -- kp->m.planes = (__force struct v4l2_plane *)uplane; -+ kp->m.planes = uplane; - - while (--num_planes >= 0) { - ret = get_v4l2_plane32(uplane, uplane32, kp->memory); -@@ -500,7 +501,7 @@ - if (num_planes == 0) - return 0; - -- uplane = (__force struct v4l2_plane __user *)kp->m.planes; -+ uplane = kp->m.planes; - if (get_user(p, &up->m.planes)) - return -EFAULT; - uplane32 = compat_ptr(p); -@@ -542,16 +543,7 @@ - __u32 capability; - __u32 flags; - compat_caddr_t base; -- struct { -- __u32 width; -- __u32 height; -- __u32 pixelformat; -- __u32 field; -- __u32 bytesperline; -- __u32 sizeimage; -- __u32 colorspace; -- __u32 priv; -- } fmt; -+ struct v4l2_pix_format fmt; - }; - - static int get_v4l2_framebuffer32(struct v4l2_framebuffer *kp, struct v4l2_framebuffer32 __user *up) -@@ -561,10 +553,10 @@ - if (!access_ok(VERIFY_READ, up, sizeof(struct v4l2_framebuffer32)) || - get_user(tmp, &up->base) || - get_user(kp->capability, &up->capability) || -- get_user(kp->flags, &up->flags) || -- copy_from_user(&kp->fmt, &up->fmt, sizeof(up->fmt))) -+ get_user(kp->flags, &up->flags)) - return -EFAULT; -- kp->base = (__force void *)compat_ptr(tmp); -+ kp->base = compat_ptr(tmp); -+ get_v4l2_pix_format(&kp->fmt, &up->fmt); - return 0; - } - -@@ -575,9 +567,9 @@ - if (!access_ok(VERIFY_WRITE, up, sizeof(struct v4l2_framebuffer32)) || - put_user(tmp, &up->base) || - put_user(kp->capability, &up->capability) || -- put_user(kp->flags, &up->flags) || -- copy_to_user(&up->fmt, &kp->fmt, sizeof(up->fmt))) -+ put_user(kp->flags, &up->flags)) - return -EFAULT; -+ put_v4l2_pix_format(&kp->fmt, &up->fmt); - return 0; - } - -@@ -669,15 +661,11 @@ - n * sizeof(struct v4l2_ext_control32))) - return -EFAULT; - kcontrols = compat_alloc_user_space(n * sizeof(struct v4l2_ext_control)); -- kp->controls = (__force struct v4l2_ext_control *)kcontrols; -+ kp->controls = kcontrols; - while (--n >= 0) { -- u32 id; -- - if (copy_in_user(kcontrols, ucontrols, sizeof(*ucontrols))) - return -EFAULT; -- if (get_user(id, &kcontrols->id)) -- return -EFAULT; -- if (ctrl_is_pointer(id)) { -+ if (ctrl_is_pointer(kcontrols->id)) { - void __user *s; - - if (get_user(p, &ucontrols->string)) -@@ -695,8 +683,7 @@ - static int put_v4l2_ext_controls32(struct v4l2_ext_controls *kp, struct v4l2_ext_controls32 __user *up) - { - struct v4l2_ext_control32 __user *ucontrols; -- struct v4l2_ext_control __user *kcontrols = -- (__force struct v4l2_ext_control __user *)kp->controls; -+ struct v4l2_ext_control __user *kcontrols = kp->controls; - int n = kp->count; - compat_caddr_t p; - -@@ -718,14 +705,11 @@ - - while (--n >= 0) { - unsigned size = sizeof(*ucontrols); -- u32 id; - -- if (get_user(id, &kcontrols->id)) -- return -EFAULT; - /* Do not modify the pointer when copying a pointer control. - The contents of the pointer was changed, not the pointer - itself. */ -- if (ctrl_is_pointer(id)) -+ if (ctrl_is_pointer(kcontrols->id)) - size -= sizeof(ucontrols->value64); - if (copy_in_user(ucontrols, kcontrols, size)) - return -EFAULT; -@@ -754,14 +738,14 @@ - copy_to_user(&up->u, &kp->u, sizeof(kp->u)) || - put_user(kp->pending, &up->pending) || - put_user(kp->sequence, &up->sequence) || -- compat_put_timespec(&kp->timestamp, &up->timestamp) || -+ put_compat_timespec(&kp->timestamp, &up->timestamp) || - put_user(kp->id, &up->id) || - copy_to_user(up->reserved, kp->reserved, 8 * sizeof(__u32))) - return -EFAULT; - return 0; - } - --struct v4l2_edid32 { -+struct v4l2_subdev_edid32 { - __u32 pad; - __u32 start_block; - __u32 blocks; -@@ -769,31 +753,31 @@ - compat_caddr_t edid; - }; - --static int get_v4l2_edid32(struct v4l2_edid *kp, struct v4l2_edid32 __user *up) -+static int get_v4l2_subdev_edid32(struct v4l2_subdev_edid *kp, struct v4l2_subdev_edid32 __user *up) - { - u32 tmp; - -- if (!access_ok(VERIFY_READ, up, sizeof(struct v4l2_edid32)) || -+ if (!access_ok(VERIFY_READ, up, sizeof(struct v4l2_subdev_edid32)) || - get_user(kp->pad, &up->pad) || - get_user(kp->start_block, &up->start_block) || - get_user(kp->blocks, &up->blocks) || - get_user(tmp, &up->edid) || - copy_from_user(kp->reserved, up->reserved, sizeof(kp->reserved))) - return -EFAULT; -- kp->edid = (__force u8 *)compat_ptr(tmp); -+ kp->edid = compat_ptr(tmp); - return 0; - } - --static int put_v4l2_edid32(struct v4l2_edid *kp, struct v4l2_edid32 __user *up) -+static int put_v4l2_subdev_edid32(struct v4l2_subdev_edid *kp, struct v4l2_subdev_edid32 __user *up) - { - u32 tmp = (u32)((unsigned long)kp->edid); - -- if (!access_ok(VERIFY_WRITE, up, sizeof(struct v4l2_edid32)) || -+ if (!access_ok(VERIFY_WRITE, up, sizeof(struct v4l2_subdev_edid32)) || - put_user(kp->pad, &up->pad) || - put_user(kp->start_block, &up->start_block) || - put_user(kp->blocks, &up->blocks) || - put_user(tmp, &up->edid) || -- copy_to_user(up->reserved, kp->reserved, sizeof(up->reserved))) -+ copy_to_user(kp->reserved, up->reserved, sizeof(kp->reserved))) - return -EFAULT; - return 0; - } -@@ -837,7 +821,7 @@ - struct v4l2_ext_controls v2ecs; - struct v4l2_event v2ev; - struct v4l2_create_buffers v2crt; -- struct v4l2_edid v2edid; -+ struct v4l2_subdev_edid v2edid; - unsigned long vx; - int vi; - } karg; -@@ -987,9 +971,9 @@ - err = put_v4l2_event32(&karg.v2ev, up); - break; - -- case VIDIOC_G_EDID: -- case VIDIOC_S_EDID: -- err = put_v4l2_edid32(&karg.v2edid, up); -+ case VIDIOC_SUBDEV_G_EDID: -+ case VIDIOC_SUBDEV_S_EDID: -+ err = put_v4l2_subdev_edid32(&karg.v2edid, up); - break; - - case VIDIOC_G_FMT: -@@ -1027,14 +1011,104 @@ - if (!file->f_op->unlocked_ioctl) - return ret; - -- if (_IOC_TYPE(cmd) == 'V' && _IOC_NR(cmd) < BASE_VIDIOC_PRIVATE) -+ switch (cmd) { -+ case VIDIOC_QUERYCAP: -+ case VIDIOC_RESERVED: -+ case VIDIOC_ENUM_FMT: -+ case VIDIOC_G_FMT32: -+ case VIDIOC_S_FMT32: -+ case VIDIOC_REQBUFS: -+ case VIDIOC_QUERYBUF32: -+ case VIDIOC_G_FBUF32: -+ case VIDIOC_S_FBUF32: -+ case VIDIOC_OVERLAY32: -+ case VIDIOC_QBUF32: -+ case VIDIOC_EXPBUF: -+ case VIDIOC_DQBUF32: -+ case VIDIOC_STREAMON32: -+ case VIDIOC_STREAMOFF32: -+ case VIDIOC_G_PARM: -+ case VIDIOC_S_PARM: -+ case VIDIOC_G_STD: -+ case VIDIOC_S_STD: -+ case VIDIOC_ENUMSTD32: -+ case VIDIOC_ENUMINPUT32: -+ case VIDIOC_G_CTRL: -+ case VIDIOC_S_CTRL: -+ case VIDIOC_G_TUNER: -+ case VIDIOC_S_TUNER: -+ case VIDIOC_G_AUDIO: -+ case VIDIOC_S_AUDIO: -+ case VIDIOC_QUERYCTRL: -+ case VIDIOC_QUERYMENU: -+ case VIDIOC_G_INPUT32: -+ case VIDIOC_S_INPUT32: -+ case VIDIOC_G_OUTPUT32: -+ case VIDIOC_S_OUTPUT32: -+ case VIDIOC_ENUMOUTPUT: -+ case VIDIOC_G_AUDOUT: -+ case VIDIOC_S_AUDOUT: -+ case VIDIOC_G_MODULATOR: -+ case VIDIOC_S_MODULATOR: -+ case VIDIOC_S_FREQUENCY: -+ case VIDIOC_G_FREQUENCY: -+ case VIDIOC_CROPCAP: -+ case VIDIOC_G_CROP: -+ case VIDIOC_S_CROP: -+ case VIDIOC_G_SELECTION: -+ case VIDIOC_S_SELECTION: -+ case VIDIOC_G_JPEGCOMP: -+ case VIDIOC_S_JPEGCOMP: -+ case VIDIOC_QUERYSTD: -+ case VIDIOC_TRY_FMT32: -+ case VIDIOC_ENUMAUDIO: -+ case VIDIOC_ENUMAUDOUT: -+ case VIDIOC_G_PRIORITY: -+ case VIDIOC_S_PRIORITY: -+ case VIDIOC_G_SLICED_VBI_CAP: -+ case VIDIOC_LOG_STATUS: -+ case VIDIOC_G_EXT_CTRLS32: -+ case VIDIOC_S_EXT_CTRLS32: -+ case VIDIOC_TRY_EXT_CTRLS32: -+ case VIDIOC_ENUM_FRAMESIZES: -+ case VIDIOC_ENUM_FRAMEINTERVALS: -+ case VIDIOC_G_ENC_INDEX: -+ case VIDIOC_ENCODER_CMD: -+ case VIDIOC_TRY_ENCODER_CMD: -+ case VIDIOC_DECODER_CMD: -+ case VIDIOC_TRY_DECODER_CMD: -+ case VIDIOC_DBG_S_REGISTER: -+ case VIDIOC_DBG_G_REGISTER: -+ case VIDIOC_DBG_G_CHIP_IDENT: -+ case VIDIOC_S_HW_FREQ_SEEK: -+ case VIDIOC_S_DV_TIMINGS: -+ case VIDIOC_G_DV_TIMINGS: -+ case VIDIOC_DQEVENT: -+ case VIDIOC_DQEVENT32: -+ case VIDIOC_SUBSCRIBE_EVENT: -+ case VIDIOC_UNSUBSCRIBE_EVENT: -+ case VIDIOC_CREATE_BUFS32: -+ case VIDIOC_PREPARE_BUF32: -+ case VIDIOC_ENUM_DV_TIMINGS: -+ case VIDIOC_QUERY_DV_TIMINGS: -+ case VIDIOC_DV_TIMINGS_CAP: -+ case VIDIOC_ENUM_FREQ_BANDS: -+ case VIDIOC_SUBDEV_G_EDID32: -+ case VIDIOC_SUBDEV_S_EDID32: - ret = do_video_ioctl(file, cmd, arg); -- else if (vdev->fops->compat_ioctl32) -- ret = vdev->fops->compat_ioctl32(file, cmd, arg); -+ break; - -- if (ret == -ENOIOCTLCMD) -- pr_warn("compat_ioctl32: unknown ioctl '%c', dir=%d, #%d (0x%08x)\n", -- _IOC_TYPE(cmd), _IOC_DIR(cmd), _IOC_NR(cmd), cmd); -+ default: -+ if (vdev->fops->compat_ioctl32) -+ ret = vdev->fops->compat_ioctl32(file, cmd, arg); -+ -+ if (ret == -ENOIOCTLCMD) -+ printk(KERN_WARNING "compat_ioctl32: " -+ "unknown ioctl '%c', dir=%d, #%d (0x%08x)\n", -+ _IOC_TYPE(cmd), _IOC_DIR(cmd), _IOC_NR(cmd), -+ cmd); -+ break; -+ } - return ret; - } - EXPORT_SYMBOL_GPL(v4l2_compat_ioctl32); -diff -Nur linux-4.1.13.orig/drivers/media/v4l2-core/v4l2-dev.c linux-4.1.13/drivers/media/v4l2-core/v4l2-dev.c ---- linux-4.1.13.orig/drivers/media/v4l2-core/v4l2-dev.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/media/v4l2-core/v4l2-dev.c 2015-11-30 17:56:13.616135330 +0100 -@@ -563,6 +563,7 @@ - set_bit(_IOC_NR(VIDIOC_DBG_G_REGISTER), valid_ioctls); - set_bit(_IOC_NR(VIDIOC_DBG_S_REGISTER), valid_ioctls); - #endif -+ SET_VALID_IOCTL(ops, VIDIOC_DBG_G_CHIP_IDENT, vidioc_g_chip_ident); - /* yes, really vidioc_subscribe_event */ - SET_VALID_IOCTL(ops, VIDIOC_DQEVENT, vidioc_subscribe_event); - SET_VALID_IOCTL(ops, VIDIOC_SUBSCRIBE_EVENT, vidioc_subscribe_event); -diff -Nur linux-4.1.13.orig/drivers/media/v4l2-core/v4l2-ioctl.c linux-4.1.13/drivers/media/v4l2-core/v4l2-ioctl.c ---- linux-4.1.13.orig/drivers/media/v4l2-core/v4l2-ioctl.c 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/media/v4l2-core/v4l2-ioctl.c 2015-11-30 17:56:13.616135330 +0100 -@@ -26,6 +26,7 @@ - #include - #include - #include -+#include - #include - - #define CREATE_TRACE_POINTS -@@ -649,6 +650,20 @@ - pr_info("pts=%llu\n", p->stop.pts); - } - -+static void v4l_print_dbg_chip_ident(const void *arg, bool write_only) -+{ -+ const struct v4l2_dbg_chip_ident *p = arg; -+ -+ pr_cont("type=%u, ", p->match.type); -+ if (p->match.type == V4L2_CHIP_MATCH_I2C_DRIVER) -+ pr_cont("name=%.*s, ", -+ (int)sizeof(p->match.name), p->match.name); -+ else -+ pr_cont("addr=%u, ", p->match.addr); -+ pr_cont("chip_ident=%u, revision=0x%x\n", -+ p->ident, p->revision); -+} -+ - static void v4l_print_dbg_chip_info(const void *arg, bool write_only) - { - const struct v4l2_dbg_chip_info *p = arg; -@@ -2002,6 +2017,18 @@ - #endif - } - -+static int v4l_dbg_g_chip_ident(const struct v4l2_ioctl_ops *ops, -+ struct file *file, void *fh, void *arg) -+{ -+ struct v4l2_dbg_chip_ident *p = arg; -+ -+ p->ident = V4L2_IDENT_NONE; -+ p->revision = 0; -+ if (p->match.type == V4L2_CHIP_MATCH_SUBDEV) -+ return -EINVAL; -+ return ops->vidioc_g_chip_ident(file, fh, p); -+} -+ - static int v4l_dbg_g_chip_info(const struct v4l2_ioctl_ops *ops, - struct file *file, void *fh, void *arg) - { -@@ -2256,6 +2283,7 @@ - IOCTL_INFO_STD(VIDIOC_TRY_DECODER_CMD, vidioc_try_decoder_cmd, v4l_print_decoder_cmd, 0), - IOCTL_INFO_FNC(VIDIOC_DBG_S_REGISTER, v4l_dbg_s_register, v4l_print_dbg_register, 0), - IOCTL_INFO_FNC(VIDIOC_DBG_G_REGISTER, v4l_dbg_g_register, v4l_print_dbg_register, 0), -+ IOCTL_INFO_FNC(VIDIOC_DBG_G_CHIP_IDENT, v4l_dbg_g_chip_ident, v4l_print_dbg_chip_ident, 0), - IOCTL_INFO_FNC(VIDIOC_S_HW_FREQ_SEEK, v4l_s_hw_freq_seek, v4l_print_hw_freq_seek, INFO_FL_PRIO), - IOCTL_INFO_STD(VIDIOC_S_DV_TIMINGS, vidioc_s_dv_timings, v4l_print_dv_timings, INFO_FL_PRIO), - IOCTL_INFO_STD(VIDIOC_G_DV_TIMINGS, vidioc_g_dv_timings, v4l_print_dv_timings, 0), -diff -Nur linux-4.1.13.orig/drivers/mfd/Kconfig linux-4.1.13/drivers/mfd/Kconfig ---- linux-4.1.13.orig/drivers/mfd/Kconfig 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/mfd/Kconfig 2015-11-30 17:56:13.616135330 +0100 -@@ -207,6 +207,13 @@ - Additional drivers must be enabled in order to use the specific - features of the device. - -+config MFD_MXC_HDMI -+ tristate "Freescale HDMI Core" -+ select MFD_CORE -+ help -+ This is the core driver for the Freescale i.MX6 on-chip HDMI. -+ This MFD driver connects with the video and audio drivers for HDMI. -+ - config MFD_DLN2 - tristate "Diolan DLN2 support" - select MFD_CORE -@@ -1466,5 +1473,13 @@ - System Registers are the platform configuration block - on the ARM Ltd. Versatile Express board. - -+config MFD_TDA1997X -+ tristate "TDA1997X HDMI Receiver Core" -+ select MFD_CORE -+ depends on I2C=y -+ help -+ This is the core driver for the TDA1997X HDMI Reciver. This MFD -+ driver connects with video and audio drivers for HDMI Input. -+ - endmenu - endif -diff -Nur linux-4.1.13.orig/drivers/mfd/Makefile linux-4.1.13/drivers/mfd/Makefile ---- linux-4.1.13.orig/drivers/mfd/Makefile 2015-11-09 23:34:10.000000000 +0100 -+++ linux-4.1.13/drivers/mfd/Makefile 2015-11-30 17:56:13.616135330 +0100 -@@ -185,3 +185,5 @@ - intel-soc-pmic-objs := intel_soc_pmic_core.o intel_soc_pmic_crc.o - obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o - obj-$(CONFIG_MFD_MT6397) += mt6397-core.o -+obj-$(CONFIG_MFD_MXC_HDMI) += mxc-hdmi-core.o -+obj-$(CONFIG_MFD_TDA1997X) += tda1997x-core.o -diff -Nur linux-4.1.13.orig/drivers/mfd/mxc-hdmi-core.c linux-4.1.13/drivers/mfd/mxc-hdmi-core.c ---- linux-4.1.13.orig/drivers/mfd/mxc-hdmi-core.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-4.1.13/drivers/mfd/mxc-hdmi-core.c 2015-11-30 17:56:13.620135063 +0100 -@@ -0,0 +1,795 @@ -+/* -+ * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ * -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include